[ { "path": ".gitignore", "content": "" }, { "path": "GNUmakefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. 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For software which is copyrighted by the Free\nSoftware Foundation, write to the Free Software Foundation; we sometimes\nmake exceptions for this. Our decision will be guided by the two goals\nof preserving the free status of all derivatives of our free software and\nof promoting the sharing and reuse of software generally.\n\n\t\t\t NO WARRANTY\n\n 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY\nFOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN\nOTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES\nPROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED\nOR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\nMERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS\nTO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE\nPROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\nREPAIR OR CORRECTION.\n\n 12. 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You can do so by permitting\nredistribution under these terms (or, alternatively, under the terms of the\nordinary General Public License).\n\n To apply these terms, attach the following notices to the library. It is\nsafest to attach them to the start of each source file to most effectively\nconvey the exclusion of warranty; and each file should have at least the\n\"copyright\" line and a pointer to where the full notice is found.\n\n \n Copyright (C) \n\n This library is free software; you can redistribute it and/or\n modify it under the terms of the GNU Lesser General Public\n License as published by the Free Software Foundation; either\n version 2.1 of the License, or (at your option) any later version.\n\n This library is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n Lesser General Public License for more details.\n\n You should have received a copy of the GNU Lesser General Public\n License along with this library; if not, write to the Free Software\n Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA\n\nAlso add information on how to contact you by electronic and paper mail.\n\nYou should also get your employer (if you work as a programmer) or your\nschool, if any, to sign a \"copyright disclaimer\" for the library, if\nnecessary. Here is a sample; alter the names:\n\n Yoyodyne, Inc., hereby disclaims all copyright interest in the\n library `Frob' (a library for tweaking knobs) written by James Random Hacker.\n\n , 1 April 1990\n Ty Coon, President of Vice\n\nThat's all there is to it!\n" }, { "path": "MAINTAINERS", "content": "DPDK Maintainers\n================\n\nThe intention of this file is to provide a set of names that we can rely on\nfor helping in patch reviews and questions.\nThese names are additional recipients for emails sent to dev@dpdk.org.\nPlease avoid private emails.\n\nDescriptions of section entries:\n\n\tM: Maintainer's Full Name \n\tT: Git tree location.\n\tF: Files and directories with wildcard patterns.\n\t A trailing slash includes all files and subdirectory files.\n\t A wildcard includes all files but not subdirectories.\n\t One pattern per line. Multiple F: lines acceptable.\n\tX: Files and directories exclusion, same rules as F:\n\tK: Keyword regex pattern to match content.\n\t One regex pattern per line. Multiple K: lines acceptable.\n\n\nGeneral Project Administration\n------------------------------\nM: Thomas Monjalon \nT: git://dpdk.org/dpdk\nF: MAINTAINERS\nF: scripts/check-maintainers.sh\n\n\nSecurity Issues\n---------------\nM: maintainers@dpdk.org\n\n\nDocumentation (with overlaps)\n-------------\nM: Siobhan Butler \nM: John McNamara \nF: doc/\n\n\nBuild System\n------------\nM: Olivier Matz \nF: GNUmakefile\nF: Makefile\nF: config/\nF: mk/\nF: pkg/\nF: scripts/auto-config-h.sh\nF: scripts/depdirs-rule.sh\nF: scripts/gen-build-mk.sh\nF: scripts/gen-config-h.sh\nF: scripts/relpath.sh\nF: doc/build-sdk-quick.txt\nF: doc/guides/prog_guide/build_app.rst\nF: doc/guides/prog_guide/dev_kit_*\nF: doc/guides/prog_guide/ext_app_lib_make_help.rst\n\nABI versioning\nM: Neil Horman \nF: lib/librte_compat/\nF: doc/guides/rel_notes/deprecation.rst\nF: scripts/validate-abi.sh\n\n\nEnvironment Abstraction Layer\n-----------------------------\n\nEAL API and common code\nM: David Marchand \nF: lib/librte_eal/common/*\nF: lib/librte_eal/common/include/*\nF: lib/librte_eal/common/include/generic/\nF: doc/guides/prog_guide/env_abstraction_layer.rst\nF: app/test/test_alarm.c\nF: app/test/test_atomic.c\nF: app/test/test_byteorder.c\nF: app/test/test_common.c\nF: app/test/test_cpuflags.c\nF: app/test/test_cycles.c\nF: app/test/test_debug.c\nF: app/test/test_devargs.c\nF: app/test/test_eal*\nF: app/test/test_errno.c\nF: app/test/test_interrupts.c\nF: app/test/test_logs.c\nF: app/test/test_memcpy*\nF: app/test/test_pci.c\nF: app/test/test_per_lcore.c\nF: app/test/test_prefetch.c\nF: app/test/test_rwlock.c\nF: app/test/test_spinlock.c\nF: app/test/test_string_fns.c\nF: app/test/test_tailq.c\nF: app/test/test_version.c\n\nMemory Allocation\nM: Sergio Gonzalez Monroy \nF: lib/librte_eal/common/include/rte_mem*\nF: lib/librte_eal/common/include/rte_malloc.h\nF: lib/librte_eal/common/*malloc*\nF: lib/librte_eal/common/eal_common_mem*\nF: lib/librte_eal/common/eal_hugepages.h\nF: lib/librte_malloc/\nF: doc/guides/prog_guide/env_abstraction_layer.rst\nF: app/test/test_func_reentrancy.c\nF: app/test/test_malloc.c\nF: app/test/test_memory.c\nF: app/test/test_memzone.c\n\nSecondary process\nK: RTE_PROC_\nF: doc/guides/prog_guide/multi_proc_support.rst\nF: app/test/test_mp_secondary.c\nF: examples/multi_process/\nF: doc/guides/sample_app_ug/multi_process.rst\n\nEZchip TILE-Gx\nM: Zhigang Lu \nF: lib/librte_eal/common/include/arch/tile/\nF: drivers/net/mpipe/\n\nIBM POWER\nM: Chao Zhu \nF: lib/librte_eal/common/include/arch/ppc_64/\n\nIntel x86\nM: Bruce Richardson \nM: Konstantin Ananyev \nF: lib/librte_eal/common/include/arch/x86/\n\nLinux EAL (with overlaps)\nM: David Marchand \nF: lib/librte_eal/linuxapp/Makefile\nF: lib/librte_eal/linuxapp/eal/\nF: doc/guides/linux_gsg/\n\nLinux UIO\nF: lib/librte_eal/linuxapp/igb_uio/\nF: lib/librte_eal/linuxapp/eal/*uio*\n\nLinux VFIO\nM: Anatoly Burakov \nF: lib/librte_eal/linuxapp/eal/*vfio*\n\nLinux Xen\nF: lib/librte_eal/linuxapp/xen_dom0/\nF: lib/librte_eal/linuxapp/eal/*xen*\nF: lib/librte_eal/linuxapp/eal/include/exec-env/rte_dom0_common.h\nF: lib/librte_mempool/rte_dom0_mempool.c\nF: drivers/net/xenvirt/\nF: doc/guides/xen/\nF: app/test-pmd/mempool_*\nF: examples/vhost_xen/\n\nFreeBSD EAL (with overlaps)\nM: Bruce Richardson \nF: lib/librte_eal/bsdapp/Makefile\nF: lib/librte_eal/bsdapp/eal/\nF: doc/guides/freebsd_gsg/\n\nFreeBSD contigmem\nM: Bruce Richardson \nF: lib/librte_eal/bsdapp/contigmem/\n\nFreeBSD UIO\nM: Bruce Richardson \nF: lib/librte_eal/bsdapp/nic_uio/\n\n\nCore Libraries\n--------------\n\nMemory pool\nM: Olivier Matz \nF: lib/librte_mempool/\nF: doc/guides/prog_guide/mempool_lib.rst\nF: app/test/test_mempool*\nF: app/test/test_func_reentrancy.c\n\nRing queue\nM: Olivier Matz \nF: lib/librte_ring/\nF: doc/guides/prog_guide/ring_lib.rst\nF: app/test/test_ring*\nF: app/test/test_func_reentrancy.c\n\nPacket buffer\nM: Olivier Matz \nF: lib/librte_mbuf/\nF: doc/guides/prog_guide/mbuf_lib.rst\nF: app/test/test_mbuf.c\n\nEthernet API\nM: Thomas Monjalon \nF: lib/librte_ether/\nF: scripts/test-null.sh\n\n\nDrivers\n-------\n\nLink bonding\nM: Declan Doherty \nF: drivers/net/bonding/\nF: doc/guides/prog_guide/link_bonding_poll_mode_drv_lib.rst\nF: app/test/test_link_bonding*\nF: examples/bond/\n\nLinux KNI\nM: Helin Zhang \nF: lib/librte_eal/linuxapp/kni/\nF: lib/librte_kni/\nF: doc/guides/prog_guide/kernel_nic_interface.rst\nF: app/test/test_kni.c\nF: examples/kni/\nF: doc/guides/sample_app_ug/kernel_nic_interface.rst\n\nLinux AF_PACKET\nM: John W. Linville \nF: drivers/net/af_packet/\n\nChelsio cxgbe\nM: Rahul Lakkireddy \nF: drivers/net/cxgbe/\nF: doc/guides/nics/cxgbe.rst\n\nCisco enic\nF: drivers/net/enic/\n\nIntel e1000\nM: Wenzhuo Lu \nF: drivers/net/e1000/\nF: doc/guides/nics/e1000em.rst\nF: doc/guides/nics/intel_vf.rst\n\nIntel ixgbe\nM: Helin Zhang \nM: Konstantin Ananyev \nF: drivers/net/ixgbe/\nF: doc/guides/nics/ixgbe.rst\nF: doc/guides/nics/intel_vf.rst\n\nIntel i40e\nM: Helin Zhang \nF: drivers/net/i40e/\nF: doc/guides/nics/intel_vf.rst\n\nIntel fm10k\nM: Jing Chen \nF: drivers/net/fm10k/\n\nMellanox mlx4\nM: Adrien Mazarguil \nF: drivers/net/mlx4/\nF: doc/guides/nics/mlx4.rst\n\nRedHat virtio\nM: Huawei Xie \nM: Changchun Ouyang \nF: drivers/net/virtio/\nF: doc/guides/nics/virtio.rst\nF: lib/librte_vhost/\nF: doc/guides/prog_guide/vhost_lib.rst\nF: examples/vhost/\nF: doc/guides/sample_app_ug/vhost.rst\n\nVMware vmxnet3\nM: Yong Wang \nF: drivers/net/vmxnet3/\nF: doc/guides/nics/vmxnet3.rst\n\nPCAP PMD\nM: Nicolás Pernas Maradei \nM: John McNamara \nF: drivers/net/pcap/\nF: doc/guides/nics/pcap_ring.rst\n\nQLogic/Broadcom bnx2x\nF: drivers/net/bnx2x/\n\nRing PMD\nM: Bruce Richardson \nF: drivers/net/ring/\nF: doc/guides/nics/pcap_ring.rst\nF: app/test/test_pmd_ring.c\n\nNull PMD\nM: Tetsuya Mukawa \nF: drivers/net/null/\n\n\nPacket processing\n-----------------\n\nNetwork headers\nF: lib/librte_net/\n\nIP fragmentation & reassembly\nM: Konstantin Ananyev \nF: lib/librte_ip_frag/\nF: doc/guides/prog_guide/ip_fragment_reassembly_lib.rst\nF: examples/ip_fragmentation/\nF: doc/guides/sample_app_ug/ip_frag.rst\nF: examples/ip_reassembly/\nF: doc/guides/sample_app_ug/ip_reassembly.rst\n\nDistributor\nM: Bruce Richardson \nF: lib/librte_distributor/\nF: doc/guides/prog_guide/packet_distrib_lib.rst\nF: app/test/test_distributor*\nF: examples/distributor/\nF: doc/guides/sample_app_ug/dist_app.rst\n\nReorder\nM: Sergio Gonzalez Monroy \nF: lib/librte_reorder/\nF: doc/guides/prog_guide/reorder_lib.rst\nF: app/test/test_reorder*\nF: examples/packet_ordering/\nF: doc/guides/sample_app_ug/packet_ordering.rst\n\nHierarchical scheduler\nM: Cristian Dumitrescu \nF: lib/librte_sched/\nF: doc/guides/prog_guide/qos_framework.rst\nF: app/test/test_red.c\nF: app/test/test_sched.c\nF: examples/qos_sched/\nF: doc/guides/sample_app_ug/qos_scheduler.rst\n\n\nPacket Framework\n----------------\nM: Cristian Dumitrescu \nF: lib/librte_pipeline/\nF: lib/librte_port/\nF: lib/librte_table/\nF: doc/guides/prog_guide/packet_framework.rst\nF: app/test/test_table*\nF: app/test-pipeline/\nF: doc/guides/sample_app_ug/test_pipeline.rst\nF: examples/ip_pipeline/\nF: doc/guides/sample_app_ug/ip_pipeline.rst\n\n\nAlgorithms\n----------\n\nACL\nM: Konstantin Ananyev \nF: lib/librte_acl/\nF: doc/guides/prog_guide/packet_classif_access_ctrl.rst\nF: app/test-acl/\nF: app/test/test_acl.*\nF: examples/l3fwd-acl/\nF: doc/guides/sample_app_ug/l3_forward_access_ctrl.rst\n\nHashes\nM: Bruce Richardson \nM: Pablo de Lara \nF: lib/librte_hash/\nF: doc/guides/prog_guide/hash_lib.rst\nF: app/test/test_*hash*\nF: app/test/test_func_reentrancy.c\n\nLPM\nM: Bruce Richardson \nF: lib/librte_lpm/\nF: doc/guides/prog_guide/lpm*\nF: app/test/test_lpm*\nF: app/test/test_func_reentrancy.c\n\nTraffic metering\nM: Cristian Dumitrescu \nF: lib/librte_meter/\nF: doc/guides/sample_app_ug/qos_scheduler.rst\nF: app/test/test_meter.c\nF: examples/qos_meter/\nF: doc/guides/sample_app_ug/qos_metering.rst\n\n\nOther libraries\n---------------\n\nConfiguration file\nM: Cristian Dumitrescu \nF: lib/librte_cfgfile/\n\nInteractive command line\nM: Olivier Matz \nF: lib/librte_cmdline/\nF: app/cmdline_test/\nF: app/test/test_cmdline*\nF: examples/cmdline/\nF: doc/guides/sample_app_ug/cmd_line.rst\n\nQemu IVSHMEM\nM: Anatoly Burakov \nF: lib/librte_ivshmem/\nF: lib/librte_eal/linuxapp/eal/eal_ivshmem.c\nF: doc/guides/prog_guide/ivshmem_lib.rst\nF: app/test/test_ivshmem.c\nF: examples/l2fwd-ivshmem/\n\nKey/Value parsing\nM: Olivier Matz \nF: lib/librte_kvargs/\nF: app/test/test_kvargs.c\n\nPower management\nF: lib/librte_power/\nF: doc/guides/prog_guide/power_man.rst\nF: app/test/test_power*\nF: examples/l3fwd-power/\nF: doc/guides/sample_app_ug/l3_forward_power_man.rst\nF: examples/vm_power_manager/\nF: doc/guides/sample_app_ug/vm_power_management.rst\n\nTimers\nM: Robert Sanford \nF: lib/librte_timer/\nF: doc/guides/prog_guide/timer_lib.rst\nF: app/test/test_timer*\nF: examples/timer/\nF: doc/guides/sample_app_ug/timer.rst\n\nJob statistics\nM: Pawel Wodkowski \nF: lib/librte_jobstats/\nF: examples/l2fwd-jobstats/\nF: doc/guides/sample_app_ug/l2_forward_job_stats.rst\n\n\nTest Applications\n-----------------\n\nUnit tests framework\nF: app/test/autotest*\nF: app/test/commands.c\nF: app/test/packet_burst_generator.c\nF: app/test/packet_burst_generator.h\nF: app/test/process.h\nF: app/test/test.c\nF: app/test/test.h\nF: app/test/test_pmd_perf.c\nF: app/test/virtual_pmd.c\nF: app/test/virtual_pmd.h\n\nDriver testing tool\nM: Pablo de Lara \nF: app/test-pmd/\nF: doc/guides/testpmd_app_ug/\n\nDump tool\nM: Maryam Tahhan \nM: John McNamara \nF: app/proc_info/\n\n\nOther Example Applications\n--------------------------\n\nM: Bruce Richardson \nF: examples/dpdk_qat/\nF: doc/guides/sample_app_ug/intel_quickassist.rst\n\nF: examples/exception_path/\nF: doc/guides/sample_app_ug/exception_path.rst\n\nM: Bruce Richardson \nF: examples/helloworld/\nF: doc/guides/sample_app_ug/hello_world.rst\n\nF: examples/ipv4_multicast/\nF: doc/guides/sample_app_ug/ipv4_multicast.rst\n\nM: Bruce Richardson \nF: examples/l2fwd/\nF: doc/guides/sample_app_ug/l2_forward_real_virtual.rst\n\nF: examples/l3fwd/\nF: doc/guides/sample_app_ug/l3_forward.rst\n\nF: examples/l3fwd-vf/\nF: doc/guides/sample_app_ug/l3_forward_virtual.rst\n\nF: examples/link_status_interrupt/\nF: doc/guides/sample_app_ug/link_status_intr.rst\n\nF: examples/load_balancer/\nF: doc/guides/sample_app_ug/load_balancer.rst\n\nF: examples/netmap_compat/\nF: doc/guides/sample_app_ug/netmap_compatibility.rst\n\nF: examples/quota_watermark/\nF: doc/guides/sample_app_ug/quota_watermark.rst\n\nM: Bruce Richardson \nM: John McNamara \nF: examples/rxtx_callbacks/\nF: doc/guides/sample_app_ug/rxtx_callbacks.rst\n\nM: Bruce Richardson \nM: John McNamara \nF: examples/skeleton/\nF: doc/guides/sample_app_ug/skeleton.rst\n\nM: Jijiang Liu \nF: examples/tep_termination/\n\nF: examples/vmdq/\nF: examples/vmdq_dcb/\nF: doc/guides/sample_app_ug/vmdq_dcb_forwarding.rst\n" }, { "path": "Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.error Error please compile using GNU Make (gmake)\n\n" }, { "path": "app/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nDIRS-$(CONFIG_RTE_APP_TEST) += test\nDIRS-$(CONFIG_RTE_LIBRTE_ACL) += test-acl\nDIRS-$(CONFIG_RTE_LIBRTE_PIPELINE) += test-pipeline\nDIRS-$(CONFIG_RTE_TEST_PMD) += test-pmd\nDIRS-$(CONFIG_RTE_LIBRTE_CMDLINE) += cmdline_test\nDIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += proc_info\n\ninclude $(RTE_SDK)/mk/rte.subdir.mk\n" }, { "path": "app/cmdline_test/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifeq ($(CONFIG_RTE_LIBRTE_CMDLINE),y)\n\n#\n# library name\n#\nAPP = cmdline_test\n\n#\n# all sources are stored in SRCS-y\n#\nSRCS-y += cmdline_test.c\nSRCS-y += commands.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.app.mk\n\nendif\n" }, { "path": "app/cmdline_test/cmdline_test.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"cmdline_test.h\"\n\nint\nmain(int __attribute__((unused)) argc, char __attribute__((unused)) ** argv)\n{\n\tstruct cmdline *cl;\n\n\tcl = cmdline_stdin_new(main_ctx, \"CMDLINE_TEST>>\");\n\tif (cl == NULL) {\n\t\treturn -1;\n\t}\n\tcmdline_interact(cl);\n\tcmdline_stdin_exit(cl);\n\n\treturn 0;\n}\n" }, { "path": "app/cmdline_test/cmdline_test.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _CMDLINE_TEST_H_\n#define _CMDLINE_TEST_H_\n\nextern cmdline_parse_ctx_t main_ctx[];\n\n#endif\n" }, { "path": "app/cmdline_test/cmdline_test.py", "content": "#!/usr/bin/python\n\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# Script that runs cmdline_test app and feeds keystrokes into it.\n\nimport sys, pexpect, string, os, cmdline_test_data\n\n#\n# function to run test\n#\ndef runTest(child,test):\n\tchild.send(test[\"Sequence\"])\n\tif test[\"Result\"] == None:\n\t\treturn 0\n\tchild.expect(test[\"Result\"],1)\n\n#\n# history test is a special case\n#\n# This test does the following:\n# 1) fills the history with garbage up to its full capacity\n# (just enough to remove last entry)\n# 2) scrolls back history to the very beginning\n# 3) checks if the output is as expected, that is, the first\n# number in the sequence (not the last entry before it)\n#\n# This is a self-contained test, it needs only a pexpect child\n#\ndef runHistoryTest(child):\n\t# find out history size\n\tchild.sendline(cmdline_test_data.CMD_GET_BUFSIZE)\n\tchild.expect(\"History buffer size: \\\\d+\", timeout=1)\n\thistory_size = int(child.after[len(cmdline_test_data.BUFSIZE_TEMPLATE):])\n\ti = 0\n\n\t# fill the history with numbers\n\twhile i < history_size / 10:\n\t\t# add 1 to prevent from parsing as octals\n\t\tchild.send(\"1\" + str(i).zfill(8) + cmdline_test_data.ENTER)\n\t\t# the app will simply print out the number\n\t\tchild.expect(str(i + 100000000), timeout=1)\n\t\ti += 1\n\t# scroll back history\n\tchild.send(cmdline_test_data.UP * (i + 2) + cmdline_test_data.ENTER)\n\tchild.expect(\"100000000\", timeout=1)\n\n# the path to cmdline_test executable is supplied via command-line.\nif len(sys.argv) < 2:\n\tprint \"Error: please supply cmdline_test app path\"\n\tsys.exit(1)\n\ntest_app_path = sys.argv[1]\n\nif not os.path.exists(test_app_path):\n\tprint \"Error: please supply cmdline_test app path\"\n\tsys.exit(1)\n\nchild = pexpect.spawn(test_app_path)\n\nprint \"Running command-line tests...\"\nfor test in cmdline_test_data.tests:\n\tprint (test[\"Name\"] + \":\").ljust(30),\n\ttry:\n\t\trunTest(child,test)\n\t\tprint \"PASS\"\n\texcept:\n\t\tprint \"FAIL\"\n\t\tprint child\n\t\tsys.exit(1)\n\n# since last test quits the app, run new instance\nchild = pexpect.spawn(test_app_path)\n\nprint (\"History fill test:\").ljust(30),\ntry:\n\trunHistoryTest(child)\n\tprint \"PASS\"\nexcept:\n\tprint \"FAIL\"\n\tprint child\n\tsys.exit(1)\nchild.close()\nsys.exit(0)\n" }, { "path": "app/cmdline_test/cmdline_test_data.py", "content": "#!/usr/bin/python\n\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# collection of static data\n\nimport sys\n\n# keycode constants\nCTRL_A = chr(1)\nCTRL_B = chr(2)\nCTRL_C = chr(3)\nCTRL_D = chr(4)\nCTRL_E = chr(5)\nCTRL_F = chr(6)\nCTRL_K = chr(11)\nCTRL_L = chr(12)\nCTRL_N = chr(14)\nCTRL_P = chr(16)\nCTRL_W = chr(23)\nCTRL_Y = chr(25)\nALT_B = chr(27) + chr(98)\nALT_D = chr(27) + chr(100)\nALT_F = chr(27) + chr(102)\nALT_BKSPACE = chr(27) + chr(127)\nDEL = chr(27) + chr(91) + chr(51) + chr(126)\nTAB = chr(9)\nHELP = chr(63)\nBKSPACE = chr(127)\nRIGHT = chr(27) + chr(91) + chr(67)\nDOWN = chr(27) + chr(91) + chr(66)\nLEFT = chr(27) + chr(91) + chr(68)\nUP = chr(27) + chr(91) + chr(65)\nENTER2 = '\\r'\nENTER = '\\n'\n\n# expected result constants\nNOT_FOUND = \"Command not found\"\nBAD_ARG = \"Bad arguments\"\nAMBIG = \"Ambiguous command\"\nCMD1 = \"Command 1 parsed!\"\nCMD2 = \"Command 2 parsed!\"\nSINGLE = \"Single word command parsed!\"\nSINGLE_LONG = \"Single long word command parsed!\"\nAUTO1 = \"Autocomplete command 1 parsed!\"\nAUTO2 = \"Autocomplete command 2 parsed!\"\n\n# misc defines\nCMD_QUIT = \"quit\"\nCMD_GET_BUFSIZE = \"get_history_bufsize\"\nBUFSIZE_TEMPLATE = \"History buffer size: \"\nPROMPT = \"CMDLINE_TEST>>\"\n\n# test defines\n# each test tests progressively diverse set of keys. this way for example\n# if we want to use some key sequence in the test, we first need to test\n# that it itself does what it is expected to do. Most of the tests are\n# designed that way.\n#\n# example: \"arrows & delete test 1\". we enter a partially valid command,\n# then move 3 chars left and use delete three times. this way we get to\n# know that \"delete\", \"left\" and \"ctrl+B\" all work (because if any of\n# them fails, the whole test will fail and next tests won't be run).\n#\n# each test consists of name, character sequence to send to child,\n# and expected output (if any).\n\ntests = [\n# test basic commands\n\t{\"Name\" : \"command test 1\",\n\t \"Sequence\" : \"ambiguous first\" + ENTER,\n\t \"Result\" : CMD1},\n\t{\"Name\" : \"command test 2\",\n\t \"Sequence\" : \"ambiguous second\" + ENTER,\n\t \"Result\" : CMD2},\n\t{\"Name\" : \"command test 3\",\n\t \"Sequence\" : \"ambiguous ambiguous\" + ENTER,\n\t \"Result\" : AMBIG},\n\t{\"Name\" : \"command test 4\",\n\t \"Sequence\" : \"ambiguous ambiguous2\" + ENTER,\n\t \"Result\" : AMBIG},\n\n\t{\"Name\" : \"invalid command test 1\",\n\t \"Sequence\" : \"ambiguous invalid\" + ENTER,\n\t \"Result\" : BAD_ARG},\n# test invalid commands\n\t{\"Name\" : \"invalid command test 2\",\n\t \"Sequence\" : \"invalid\" + ENTER,\n\t \"Result\" : NOT_FOUND},\n\t{\"Name\" : \"invalid command test 3\",\n\t \"Sequence\" : \"ambiguousinvalid\" + ENTER2,\n\t \"Result\" : NOT_FOUND},\n\n# test arrows and deletes\n\t{\"Name\" : \"arrows & delete test 1\",\n\t \"Sequence\" : \"singlebad\" + LEFT*2 + CTRL_B + DEL*3 + ENTER,\n\t \"Result\" : SINGLE},\n\t{\"Name\" : \"arrows & delete test 2\",\n\t \"Sequence\" : \"singlebad\" + LEFT*5 + RIGHT + CTRL_F + DEL*3 + ENTER,\n\t \"Result\" : SINGLE},\n\n# test backspace\n\t{\"Name\" : \"backspace test\",\n\t \"Sequence\" : \"singlebad\" + BKSPACE*3 + ENTER,\n\t \"Result\" : SINGLE},\n\n# test goto left and goto right\n\t{\"Name\" : \"goto left test\",\n\t \"Sequence\" : \"biguous first\" + CTRL_A + \"am\" + ENTER,\n\t \"Result\" : CMD1},\n\t{\"Name\" : \"goto right test\",\n\t \"Sequence\" : \"biguous fir\" + CTRL_A + \"am\" + CTRL_E + \"st\" + ENTER,\n\t \"Result\" : CMD1},\n\n# test goto words\n\t{\"Name\" : \"goto left word test\",\n\t \"Sequence\" : \"ambiguous st\" + ALT_B + \"fir\" + ENTER,\n\t \"Result\" : CMD1},\n\t{\"Name\" : \"goto right word test\",\n\t \"Sequence\" : \"ambig first\" + CTRL_A + ALT_F + \"uous\" + ENTER,\n\t \"Result\" : CMD1},\n\n# test removing words\n\t{\"Name\" : \"remove left word 1\",\n\t \"Sequence\" : \"single invalid\" + CTRL_W + ENTER,\n\t \"Result\" : SINGLE},\n\t{\"Name\" : \"remove left word 2\",\n\t \"Sequence\" : \"single invalid\" + ALT_BKSPACE + ENTER,\n\t \"Result\" : SINGLE},\n\t{\"Name\" : \"remove right word\",\n\t \"Sequence\" : \"single invalid\" + ALT_B + ALT_D + ENTER,\n\t \"Result\" : SINGLE},\n\n# test kill buffer (copy and paste)\n\t{\"Name\" : \"killbuffer test 1\",\n\t \"Sequence\" : \"ambiguous\" + CTRL_A + CTRL_K + \" first\" + CTRL_A + CTRL_Y + ENTER,\n\t \"Result\" : CMD1},\n\t{\"Name\" : \"killbuffer test 2\",\n\t \"Sequence\" : \"ambiguous\" + CTRL_A + CTRL_K + CTRL_Y*26 + ENTER,\n\t \"Result\" : NOT_FOUND},\n\n# test newline\n\t{\"Name\" : \"newline test\",\n\t \"Sequence\" : \"invalid\" + CTRL_C + \"single\" + ENTER,\n\t \"Result\" : SINGLE},\n\n# test redisplay (nothing should really happen)\n\t{\"Name\" : \"redisplay test\",\n\t \"Sequence\" : \"single\" + CTRL_L + ENTER,\n\t \"Result\" : SINGLE},\n\n# test autocomplete\n\t{\"Name\" : \"autocomplete test 1\",\n\t \"Sequence\" : \"si\" + TAB + ENTER,\n\t \"Result\" : SINGLE},\n\t{\"Name\" : \"autocomplete test 2\",\n\t \"Sequence\" : \"si\" + TAB + \"_\" + TAB + ENTER,\n\t \"Result\" : SINGLE_LONG},\n\t{\"Name\" : \"autocomplete test 3\",\n\t \"Sequence\" : \"in\" + TAB + ENTER,\n\t \"Result\" : NOT_FOUND},\n\t{\"Name\" : \"autocomplete test 4\",\n\t \"Sequence\" : \"am\" + TAB + ENTER,\n\t \"Result\" : BAD_ARG},\n\t{\"Name\" : \"autocomplete test 5\",\n\t \"Sequence\" : \"am\" + TAB + \"fir\" + TAB + ENTER,\n\t \"Result\" : CMD1},\n\t{\"Name\" : \"autocomplete test 6\",\n\t \"Sequence\" : \"am\" + TAB + \"fir\" + TAB + TAB + ENTER,\n\t \"Result\" : CMD1},\n\t{\"Name\" : \"autocomplete test 7\",\n\t \"Sequence\" : \"am\" + TAB + \"fir\" + TAB + \" \" + TAB + ENTER,\n\t \"Result\" : CMD1},\n\t{\"Name\" : \"autocomplete test 8\",\n\t \"Sequence\" : \"am\" + TAB + \" am\" + TAB + \" \" + ENTER,\n\t \"Result\" : AMBIG},\n\t{\"Name\" : \"autocomplete test 9\",\n\t \"Sequence\" : \"am\" + TAB + \"inv\" + TAB + ENTER,\n\t \"Result\" : BAD_ARG},\n\t{\"Name\" : \"autocomplete test 10\",\n\t \"Sequence\" : \"au\" + TAB + ENTER,\n\t \"Result\" : NOT_FOUND},\n\t{\"Name\" : \"autocomplete test 11\",\n\t \"Sequence\" : \"au\" + TAB + \"1\" + ENTER,\n\t \"Result\" : AUTO1},\n\t{\"Name\" : \"autocomplete test 12\",\n\t \"Sequence\" : \"au\" + TAB + \"2\" + ENTER,\n\t \"Result\" : AUTO2},\n\t{\"Name\" : \"autocomplete test 13\",\n\t \"Sequence\" : \"au\" + TAB + \"2\" + TAB + ENTER,\n\t \"Result\" : AUTO2},\n\t{\"Name\" : \"autocomplete test 14\",\n\t \"Sequence\" : \"au\" + TAB + \"2 \" + TAB + ENTER,\n\t \"Result\" : AUTO2},\n\t{\"Name\" : \"autocomplete test 15\",\n\t \"Sequence\" : \"24\" + TAB + ENTER,\n\t \"Result\" : \"24\"},\n\n# test history\n\t{\"Name\" : \"history test 1\",\n\t \"Sequence\" : \"invalid\" + ENTER + \"single\" + ENTER + \"invalid\" + ENTER + UP + CTRL_P + ENTER,\n\t \"Result\" : SINGLE},\n\t{\"Name\" : \"history test 2\",\n\t \"Sequence\" : \"invalid\" + ENTER + \"ambiguous first\" + ENTER + \"invalid\" + ENTER + \"single\" + ENTER + UP * 3 + CTRL_N + DOWN + ENTER,\n\t \"Result\" : SINGLE},\n\n#\n# tests that improve coverage\n#\n\n# empty space tests\n\t{\"Name\" : \"empty space test 1\",\n\t \"Sequence\" : RIGHT + LEFT + CTRL_B + CTRL_F + ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"empty space test 2\",\n\t \"Sequence\" : BKSPACE + ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"empty space test 3\",\n\t \"Sequence\" : CTRL_E*2 + CTRL_A*2 + ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"empty space test 4\",\n\t \"Sequence\" : ALT_F*2 + ALT_B*2 + ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"empty space test 5\",\n\t \"Sequence\" : \" \" + CTRL_E*2 + CTRL_A*2 + ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"empty space test 6\",\n\t \"Sequence\" : \" \" + CTRL_A + ALT_F*2 + ALT_B*2 + ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"empty space test 7\",\n\t \"Sequence\" : \" \" + CTRL_A + CTRL_D + CTRL_E + CTRL_D + ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"empty space test 8\",\n\t \"Sequence\" : \" space\" + CTRL_W*2 + ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"empty space test 9\",\n\t \"Sequence\" : \" space\" + ALT_BKSPACE*2 + ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"empty space test 10\",\n\t \"Sequence\" : \" space \" + CTRL_A + ALT_D*3 + ENTER,\n\t \"Result\" : PROMPT},\n\n# non-printable char tests\n\t{\"Name\" : \"non-printable test 1\",\n\t \"Sequence\" : chr(27) + chr(47) + ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"non-printable test 2\",\n\t \"Sequence\" : chr(27) + chr(128) + ENTER*7,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"non-printable test 3\",\n\t \"Sequence\" : chr(27) + chr(91) + chr(127) + ENTER*6,\n\t \"Result\" : PROMPT},\n\n# miscellaneous tests\n\t{\"Name\" : \"misc test 1\",\n\t \"Sequence\" : ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"misc test 2\",\n\t \"Sequence\" : \"single #comment\" + ENTER,\n\t \"Result\" : SINGLE},\n\t{\"Name\" : \"misc test 3\",\n\t \"Sequence\" : \"#empty line\" + ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"misc test 4\",\n\t \"Sequence\" : \" single \" + ENTER,\n\t \"Result\" : SINGLE},\n\t{\"Name\" : \"misc test 5\",\n\t \"Sequence\" : \"single#\" + ENTER,\n\t \"Result\" : SINGLE},\n\t{\"Name\" : \"misc test 6\",\n\t \"Sequence\" : 'a' * 257 + ENTER,\n\t \"Result\" : NOT_FOUND},\n\t{\"Name\" : \"misc test 7\",\n\t \"Sequence\" : \"clear_history\" + UP*5 + DOWN*5 + ENTER,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"misc test 8\",\n\t \"Sequence\" : \"a\" + HELP + CTRL_C,\n\t \"Result\" : PROMPT},\n\t{\"Name\" : \"misc test 9\",\n\t \"Sequence\" : CTRL_D*3,\n\t \"Result\" : None},\n]\n" }, { "path": "app/cmdline_test/commands.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"cmdline_test.h\"\n\n/*** quit ***/\n/* exit application */\n\nstruct cmd_quit_result {\n\tcmdline_fixed_string_t quit;\n};\n\nstatic void\ncmd_quit_parsed(__attribute__((unused)) void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tcmdline_quit(cl);\n}\n\ncmdline_parse_token_string_t cmd_quit_tok =\n\tTOKEN_STRING_INITIALIZER(struct cmd_quit_result, quit,\n\t\t\t\t \"quit\");\n\ncmdline_parse_inst_t cmd_quit = {\n\t.f = cmd_quit_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"exit application\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_quit_tok,\n\t\tNULL,\n\t},\n};\n\n\n\n/*** single ***/\n/* a simple single-word command */\n\nstruct cmd_single_result {\n\tcmdline_fixed_string_t single;\n};\n\nstatic void\ncmd_single_parsed(__attribute__((unused)) void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tcmdline_printf(cl, \"Single word command parsed!\\n\");\n}\n\ncmdline_parse_token_string_t cmd_single_tok =\n\tTOKEN_STRING_INITIALIZER(struct cmd_single_result, single,\n\t\t\t\t \"single\");\n\ncmdline_parse_inst_t cmd_single = {\n\t.f = cmd_single_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"a simple single-word command\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_single_tok,\n\t\tNULL,\n\t},\n};\n\n\n\n/*** single_long ***/\n/* a variant of \"single\" command. useful to test autocomplete */\n\nstruct cmd_single_long_result {\n\tcmdline_fixed_string_t single_long;\n};\n\nstatic void\ncmd_single_long_parsed(__attribute__((unused)) void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tcmdline_printf(cl, \"Single long word command parsed!\\n\");\n}\n\ncmdline_parse_token_string_t cmd_single_long_tok =\n\tTOKEN_STRING_INITIALIZER(struct cmd_single_long_result, single_long,\n\t\t\t\t \"single_long\");\n\ncmdline_parse_inst_t cmd_single_long = {\n\t.f = cmd_single_long_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"a variant of \\\"single\\\" command, useful to test autocomplete\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_single_long_tok,\n\t\tNULL,\n\t},\n};\n\n\n\n/*** autocomplete_1 ***/\n/* first command to test autocomplete when multiple commands have chars\n * in common but none should complete due to ambiguity\n */\n\nstruct cmd_autocomplete_1_result {\n\tcmdline_fixed_string_t token;\n};\n\nstatic void\ncmd_autocomplete_1_parsed(__attribute__((unused)) void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tcmdline_printf(cl, \"Autocomplete command 1 parsed!\\n\");\n}\n\ncmdline_parse_token_string_t cmd_autocomplete_1_tok =\n\tTOKEN_STRING_INITIALIZER(struct cmd_autocomplete_1_result, token,\n\t\t\t\t \"autocomplete_1\");\n\ncmdline_parse_inst_t cmd_autocomplete_1 = {\n\t.f = cmd_autocomplete_1_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"first ambiguous autocomplete command\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_autocomplete_1_tok,\n\t\tNULL,\n\t},\n};\n\n\n\n/*** autocomplete_2 ***/\n/* second command to test autocomplete when multiple commands have chars\n * in common but none should complete due to ambiguity\n */\n\nstruct cmd_autocomplete_2_result {\n\tcmdline_fixed_string_t token;\n};\n\nstatic void\ncmd_autocomplete_2_parsed(__attribute__((unused)) void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tcmdline_printf(cl, \"Autocomplete command 2 parsed!\\n\");\n}\n\ncmdline_parse_token_string_t cmd_autocomplete_2_tok =\n\tTOKEN_STRING_INITIALIZER(struct cmd_autocomplete_2_result, token,\n\t\t\t\t \"autocomplete_2\");\n\ncmdline_parse_inst_t cmd_autocomplete_2 = {\n\t.f = cmd_autocomplete_2_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"second ambiguous autocomplete command\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_autocomplete_2_tok,\n\t\tNULL,\n\t},\n};\n\n\n\n/*** number command ***/\n/* a command that simply returns whatever (uint32) number is supplied to it */\n\nstruct cmd_num_result {\n\tunsigned num;\n};\n\nstatic void\ncmd_num_parsed(void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tunsigned result = ((struct cmd_num_result*)parsed_result)->num;\n\tcmdline_printf(cl, \"%u\\n\", result);\n}\n\ncmdline_parse_token_num_t cmd_num_tok =\n\tTOKEN_NUM_INITIALIZER(struct cmd_num_result, num, UINT32);\n\ncmdline_parse_inst_t cmd_num = {\n\t.f = cmd_num_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"a command that simply returns whatever number is entered\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_num_tok,\n\t\tNULL,\n\t},\n};\n\n\n\n/*** ambiguous first|ambiguous ***/\n/* first command used to test command ambiguity */\n\nstruct cmd_ambig_result_1 {\n\tcmdline_fixed_string_t common_part;\n\tcmdline_fixed_string_t ambig_part;\n};\n\nstatic void\ncmd_ambig_1_parsed(__attribute__((unused)) void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tcmdline_printf(cl, \"Command 1 parsed!\\n\");\n}\n\ncmdline_parse_token_string_t cmd_ambig_common_1 =\n\tTOKEN_STRING_INITIALIZER(struct cmd_ambig_result_1, common_part,\n\t\t\t\t \"ambiguous\");\ncmdline_parse_token_string_t cmd_ambig_ambig_1 =\n\tTOKEN_STRING_INITIALIZER(struct cmd_ambig_result_1, ambig_part,\n\t\t\t\t \"first#ambiguous#ambiguous2\");\n\ncmdline_parse_inst_t cmd_ambig_1 = {\n\t.f = cmd_ambig_1_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"first command used to test command ambiguity\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_ambig_common_1,\n\t\t(void*)&cmd_ambig_ambig_1,\n\t\tNULL,\n\t},\n};\n\n\n\n/*** ambiguous second|ambiguous ***/\n/* second command used to test command ambiguity */\n\nstruct cmd_ambig_result_2 {\n\tcmdline_fixed_string_t common_part;\n\tcmdline_fixed_string_t ambig_part;\n};\n\nstatic void\ncmd_ambig_2_parsed(__attribute__((unused)) void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tcmdline_printf(cl, \"Command 2 parsed!\\n\");\n}\n\ncmdline_parse_token_string_t cmd_ambig_common_2 =\n\tTOKEN_STRING_INITIALIZER(struct cmd_ambig_result_2, common_part,\n\t\t\t\t \"ambiguous\");\ncmdline_parse_token_string_t cmd_ambig_ambig_2 =\n\tTOKEN_STRING_INITIALIZER(struct cmd_ambig_result_2, ambig_part,\n\t\t\t\t \"second#ambiguous#ambiguous2\");\n\ncmdline_parse_inst_t cmd_ambig_2 = {\n\t.f = cmd_ambig_2_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"second command used to test command ambiguity\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_ambig_common_2,\n\t\t(void*)&cmd_ambig_ambig_2,\n\t\tNULL,\n\t},\n};\n\n\n\n/*** get_history_bufsize ***/\n/* command that displays total space in history buffer\n * this will be useful for testing history (to fill it up just enough to\n * remove the last entry, we need to know how big it is).\n */\n\nstruct cmd_get_history_bufsize_result {\n\tcmdline_fixed_string_t str;\n};\n\nstatic void\ncmd_get_history_bufsize_parsed(__attribute__((unused)) void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tcmdline_printf(cl, \"History buffer size: %zu\\n\",\n\t\t\tsizeof(cl->rdl.history_buf));\n}\n\ncmdline_parse_token_string_t cmd_get_history_bufsize_tok =\n\tTOKEN_STRING_INITIALIZER(struct cmd_get_history_bufsize_result, str,\n\t\t\t\t \"get_history_bufsize\");\n\ncmdline_parse_inst_t cmd_get_history_bufsize = {\n\t.f = cmd_get_history_bufsize_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"command that displays total space in history buffer\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_get_history_bufsize_tok,\n\t\tNULL,\n\t},\n};\n\n\n\n/*** clear_history ***/\n/* clears history buffer */\n\nstruct cmd_clear_history_result {\n\tcmdline_fixed_string_t str;\n};\n\nstatic void\ncmd_clear_history_parsed(__attribute__((unused)) void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\trdline_clear_history(&cl->rdl);\n}\n\ncmdline_parse_token_string_t cmd_clear_history_tok =\n\tTOKEN_STRING_INITIALIZER(struct cmd_clear_history_result, str,\n\t\t\t\t \"clear_history\");\n\ncmdline_parse_inst_t cmd_clear_history = {\n\t.f = cmd_clear_history_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"clear command history\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_clear_history_tok,\n\t\tNULL,\n\t},\n};\n\n\n\n/****************/\n\ncmdline_parse_ctx_t main_ctx[] = {\n\t\t(cmdline_parse_inst_t *)&cmd_quit,\n\t\t(cmdline_parse_inst_t *)&cmd_ambig_1,\n\t\t(cmdline_parse_inst_t *)&cmd_ambig_2,\n\t\t(cmdline_parse_inst_t *)&cmd_single,\n\t\t(cmdline_parse_inst_t *)&cmd_single_long,\n\t\t(cmdline_parse_inst_t *)&cmd_num,\n\t\t(cmdline_parse_inst_t *)&cmd_get_history_bufsize,\n\t\t(cmdline_parse_inst_t *)&cmd_clear_history,\n\t\t(cmdline_parse_inst_t *)&cmd_autocomplete_1,\n\t\t(cmdline_parse_inst_t *)&cmd_autocomplete_2,\n\tNULL,\n};\n" }, { "path": "app/proc_info/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nAPP = proc_info\n\nCFLAGS += $(WERROR_FLAGS)\n\n# all source are stored in SRCS-y\n\nSRCS-y := main.c\n\n# this application needs libraries first\nDEPDIRS-y += lib\n\ninclude $(RTE_SDK)/mk/rte.app.mk\n" }, { "path": "app/proc_info/main.c", "content": "/*\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/* Maximum long option length for option parsing. */\n#define MAX_LONG_OPT_SZ 64\n#define RTE_LOGTYPE_APP RTE_LOGTYPE_USER1\n\n/**< mask of enabled ports */\nstatic uint32_t enabled_port_mask;\n/**< Enable stats. */\nstatic uint32_t enable_stats;\n/**< Enable xstats. */\nstatic uint32_t enable_xstats;\n/**< Enable stats reset. */\nstatic uint32_t reset_stats;\n/**< Enable xstats reset. */\nstatic uint32_t reset_xstats;\n/**< Enable memory info. */\nstatic uint32_t mem_info;\n\n/**< display usage */\nstatic void\nproc_info_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK\\n\"\n\t\t\" -m to display DPDK memory zones, segments and TAILQ information\\n\"\n\t\t\" -p PORTMASK: hexadecimal bitmask of ports to retrieve stats for\\n\"\n\t\t\" --stats: to display port statistics, enabled by default\\n\"\n\t\t\" --xstats: to display extended port statistics, disabled by \"\n\t\t\t\"default\\n\"\n\t\t\" --stats-reset: to reset port statistics\\n\"\n\t\t\" --xstats-reset: to reset port extended statistics\\n\",\n\t\tprgname);\n}\n\n/*\n * Parse the portmask provided at run time.\n */\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\terrno = 0;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0') ||\n\t\t(errno != 0)) {\n\t\tprintf(\"%s ERROR parsing the port mask\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nproc_info_parse_args(int argc, char **argv)\n{\n\tint opt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option long_option[] = {\n\t\t{\"stats\", 0, NULL, 0},\n\t\t{\"stats-reset\", 0, NULL, 0},\n\t\t{\"xstats\", 0, NULL, 0},\n\t\t{\"xstats-reset\", 0, NULL, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\tif (argc == 1)\n\t\tproc_info_usage(prgname);\n\n\t/* Parse command line */\n\twhile ((opt = getopt_long(argc, argv, \"p:m\",\n\t\t\tlong_option, &option_index)) != EOF) {\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tproc_info_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'm':\n\t\t\tmem_info = 1;\n\t\t\tbreak;\n\t\tcase 0:\n\t\t\t/* Print stats */\n\t\t\tif (!strncmp(long_option[option_index].name, \"stats\",\n\t\t\t\t\tMAX_LONG_OPT_SZ))\n\t\t\t\tenable_stats = 1;\n\t\t\t/* Print xstats */\n\t\t\telse if (!strncmp(long_option[option_index].name, \"xstats\",\n\t\t\t\t\tMAX_LONG_OPT_SZ))\n\t\t\t\tenable_xstats = 1;\n\t\t\t/* Reset stats */\n\t\t\tif (!strncmp(long_option[option_index].name, \"stats-reset\",\n\t\t\t\t\tMAX_LONG_OPT_SZ))\n\t\t\t\treset_stats = 1;\n\t\t\t/* Reset xstats */\n\t\t\telse if (!strncmp(long_option[option_index].name, \"xstats-reset\",\n\t\t\t\t\tMAX_LONG_OPT_SZ))\n\t\t\t\treset_xstats = 1;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tproc_info_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic void\nmeminfo_display(void)\n{\n\tprintf(\"----------- MEMORY_SEGMENTS -----------\\n\");\n\trte_dump_physmem_layout(stdout);\n\tprintf(\"--------- END_MEMORY_SEGMENTS ---------\\n\");\n\n\tprintf(\"------------ MEMORY_ZONES -------------\\n\");\n\trte_memzone_dump(stdout);\n\tprintf(\"---------- END_MEMORY_ZONES -----------\\n\");\n\n\tprintf(\"------------- TAIL_QUEUES -------------\\n\");\n\trte_dump_tailq(stdout);\n\tprintf(\"---------- END_TAIL_QUEUES ------------\\n\");\n}\n\nstatic void\nnic_stats_display(uint8_t port_id)\n{\n\tstruct rte_eth_stats stats;\n\tuint8_t i;\n\n\tstatic const char *nic_stats_border = \"########################\";\n\n\trte_eth_stats_get(port_id, &stats);\n\tprintf(\"\\n %s NIC statistics for port %-2d %s\\n\",\n\t\t nic_stats_border, port_id, nic_stats_border);\n\n\tprintf(\" RX-packets: %-10\"PRIu64\" RX-errors: %-10\"PRIu64\n\t \" RX-bytes: %-10\"PRIu64\"\\n\", stats.ipackets, stats.ierrors,\n\t stats.ibytes);\n\tprintf(\" RX-nombuf: %-10\"PRIu64\"\\n\", stats.rx_nombuf);\n\tprintf(\" TX-packets: %-10\"PRIu64\" TX-errors: %-10\"PRIu64\n\t \" TX-bytes: %-10\"PRIu64\"\\n\", stats.opackets, stats.oerrors,\n\t stats.obytes);\n\n\tprintf(\"\\n\");\n\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) {\n\t\tprintf(\" Stats reg %2d RX-packets: %-10\"PRIu64\n\t\t \" RX-errors: %-10\"PRIu64\n\t\t \" RX-bytes: %-10\"PRIu64\"\\n\",\n\t\t i, stats.q_ipackets[i], stats.q_errors[i], stats.q_ibytes[i]);\n\t}\n\n\tprintf(\"\\n\");\n\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) {\n\t\tprintf(\" Stats reg %2d TX-packets: %-10\"PRIu64\n\t\t \" TX-bytes: %-10\"PRIu64\"\\n\",\n\t\t i, stats.q_opackets[i], stats.q_obytes[i]);\n\t}\n\n\tprintf(\" %s############################%s\\n\",\n\t\t nic_stats_border, nic_stats_border);\n}\n\nstatic void\nnic_stats_clear(uint8_t port_id)\n{\n\tprintf(\"\\n Clearing NIC stats for port %d\\n\", port_id);\n\trte_eth_stats_reset(port_id);\n\tprintf(\"\\n NIC statistics for port %d cleared\\n\", port_id);\n}\n\nstatic void\nnic_xstats_display(uint8_t port_id)\n{\n\tstruct rte_eth_xstats *xstats;\n\tint len, ret, i;\n\tstatic const char *nic_stats_border = \"########################\";\n\n\tlen = rte_eth_xstats_get(port_id, NULL, 0);\n\tif (len < 0) {\n\t\tprintf(\"Cannot get xstats count\\n\");\n\t\treturn;\n\t}\n\txstats = malloc(sizeof(xstats[0]) * len);\n\tif (xstats == NULL) {\n\t\tprintf(\"Cannot allocate memory for xstats\\n\");\n\t\treturn;\n\t}\n\n\tprintf(\"###### NIC extended statistics for port %-2d #########\\n\",\n\t\t\t port_id);\n\tprintf(\"%s############################\\n\",\n\t\t\t nic_stats_border);\n\tret = rte_eth_xstats_get(port_id, xstats, len);\n\tif (ret < 0 || ret > len) {\n\t\tprintf(\"Cannot get xstats\\n\");\n\t\tfree(xstats);\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < len; i++)\n\t\tprintf(\"%s: %\"PRIu64\"\\n\", xstats[i].name, xstats[i].value);\n\n\tprintf(\"%s############################\\n\",\n\t\t\t nic_stats_border);\n\tfree(xstats);\n}\n\nstatic void\nnic_xstats_clear(uint8_t port_id)\n{\n\tprintf(\"\\n Clearing NIC xstats for port %d\\n\", port_id);\n\trte_eth_xstats_reset(port_id);\n\tprintf(\"\\n NIC extended statistics for port %d cleared\\n\", port_id);\n}\n\nint\nmain(int argc, char **argv)\n{\n\tint ret;\n\tint i;\n\tchar c_flag[] = \"-c1\";\n\tchar n_flag[] = \"-n4\";\n\tchar mp_flag[] = \"--proc-type=secondary\";\n\tchar *argp[argc + 3];\n\tuint8_t nb_ports;\n\n\targp[0] = argv[0];\n\targp[1] = c_flag;\n\targp[2] = n_flag;\n\targp[3] = mp_flag;\n\n\tfor (i = 1; i < argc; i++)\n\t\targp[i + 3] = argv[i];\n\n\targc += 3;\n\n\tret = rte_eal_init(argc, argp);\n\tif (ret < 0)\n\t\trte_panic(\"Cannot init EAL\\n\");\n\n\targc -= ret;\n\targv += (ret - 3);\n\n\t/* parse app arguments */\n\tret = proc_info_parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid argument\\n\");\n\n\tif (mem_info) {\n\t\tmeminfo_display();\n\t\treturn 0;\n\t}\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports == 0)\n\t\trte_exit(EXIT_FAILURE, \"No Ethernet ports - bye\\n\");\n\n\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\t/* If no port mask was specified*/\n\tif (enabled_port_mask == 0)\n\t\tenabled_port_mask = 0xffff;\n\n\tfor (i = 0; i < nb_ports; i++) {\n\t\tif (enabled_port_mask & (1 << i)) {\n\t\t\tif (enable_stats)\n\t\t\t\tnic_stats_display(i);\n\t\t\telse if (enable_xstats)\n\t\t\t\tnic_xstats_display(i);\n\t\t\telse if (reset_stats)\n\t\t\t\tnic_stats_clear(i);\n\t\t\telse if (reset_xstats)\n\t\t\t\tnic_xstats_clear(i);\n\t\t}\n\t}\n\n\treturn 0;\n}\n" }, { "path": "app/test/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifeq ($(CONFIG_RTE_APP_TEST),y)\n\n#\n# library name\n#\nAPP = test\n\n#\n# all sources are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) := commands.c\nSRCS-y += test.c\nSRCS-y += test_pci.c\nSRCS-y += test_prefetch.c\nSRCS-y += test_byteorder.c\nSRCS-y += test_per_lcore.c\nSRCS-y += test_atomic.c\nSRCS-y += test_malloc.c\nSRCS-y += test_cycles.c\nSRCS-y += test_spinlock.c\nSRCS-y += test_memory.c\nSRCS-y += test_memzone.c\n\nSRCS-y += test_ring.c\nSRCS-y += test_ring_perf.c\nSRCS-y += test_pmd_perf.c\n\nifeq ($(CONFIG_RTE_LIBRTE_TABLE),y)\nSRCS-y += test_table.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += test_table_pipeline.c\nSRCS-y += test_table_tables.c\nSRCS-y += test_table_ports.c\nSRCS-y += test_table_combined.c\nSRCS-$(CONFIG_RTE_LIBRTE_ACL) += test_table_acl.c\nendif\n\nSRCS-y += test_rwlock.c\n\nSRCS-$(CONFIG_RTE_LIBRTE_TIMER) += test_timer.c\nSRCS-$(CONFIG_RTE_LIBRTE_TIMER) += test_timer_perf.c\nSRCS-$(CONFIG_RTE_LIBRTE_TIMER) += test_timer_racecond.c\n\nSRCS-y += test_mempool.c\nSRCS-y += test_mempool_perf.c\n\nSRCS-y += test_mbuf.c\nSRCS-y += test_logs.c\n\nSRCS-y += test_memcpy.c\nSRCS-y += test_memcpy_perf.c\n\nSRCS-$(CONFIG_RTE_LIBRTE_HASH) += test_hash.c\nSRCS-$(CONFIG_RTE_LIBRTE_HASH) += test_thash.c\nSRCS-$(CONFIG_RTE_LIBRTE_HASH) += test_hash_perf.c\nSRCS-$(CONFIG_RTE_LIBRTE_HASH) += test_hash_functions.c\nSRCS-$(CONFIG_RTE_LIBRTE_HASH) += test_hash_scaling.c\n\nSRCS-$(CONFIG_RTE_LIBRTE_LPM) += test_lpm.c\nSRCS-$(CONFIG_RTE_LIBRTE_LPM) += test_lpm6.c\n\nSRCS-y += test_debug.c\nSRCS-y += test_errno.c\nSRCS-y += test_tailq.c\nSRCS-y += test_string_fns.c\nSRCS-y += test_cpuflags.c\nSRCS-y += test_mp_secondary.c\nSRCS-y += test_eal_flags.c\nSRCS-y += test_eal_fs.c\nSRCS-y += test_alarm.c\nSRCS-y += test_interrupts.c\nSRCS-y += test_version.c\nSRCS-y += test_func_reentrancy.c\n\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += test_cmdline.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += test_cmdline_num.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += test_cmdline_etheraddr.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += test_cmdline_portlist.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += test_cmdline_ipaddr.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += test_cmdline_cirbuf.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += test_cmdline_string.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += test_cmdline_lib.c\n\nifeq ($(CONFIG_RTE_LIBRTE_SCHED),y)\nSRCS-y += test_red.c\nSRCS-$(CONFIG_RTE_ARCH_X86_64) += test_sched.c\nendif\n\nSRCS-$(CONFIG_RTE_LIBRTE_METER) += test_meter.c\nSRCS-$(CONFIG_RTE_LIBRTE_KNI) += test_kni.c\nSRCS-$(CONFIG_RTE_LIBRTE_POWER) += test_power.c test_power_acpi_cpufreq.c\nSRCS-$(CONFIG_RTE_LIBRTE_POWER) += test_power_kvm_vm.c\nSRCS-y += test_common.c\nSRCS-$(CONFIG_RTE_LIBRTE_IVSHMEM) += test_ivshmem.c\n\nSRCS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) += test_distributor.c\nSRCS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) += test_distributor_perf.c\n\nSRCS-$(CONFIG_RTE_LIBRTE_REORDER) += test_reorder.c\n\nSRCS-y += test_devargs.c\nSRCS-y += virtual_pmd.c\nSRCS-y += packet_burst_generator.c\nSRCS-$(CONFIG_RTE_LIBRTE_ACL) += test_acl.c\n\nifeq ($(CONFIG_RTE_LIBRTE_PMD_RING),y)\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += test_link_bonding.c\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += test_link_bonding_mode4.c\nendif\n\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_RING) += test_pmd_ring.c\nSRCS-$(CONFIG_RTE_LIBRTE_KVARGS) += test_kvargs.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\n# Disable warnings of deprecated-declarations in test_kni.c\nifeq ($(CC), icc)\nCFLAGS_test_kni.o += -wd1478\nelse\nCFLAGS_test_kni.o += -Wno-deprecated-declarations\nendif\nCFLAGS += -D_GNU_SOURCE\n\n# Disable VTA for memcpy test\nifeq ($(CC), gcc)\nifeq ($(shell test $(GCC_VERSION) -ge 44 && echo 1), 1)\nCFLAGS_test_memcpy.o += -fno-var-tracking-assignments\nCFLAGS_test_memcpy_perf.o += -fno-var-tracking-assignments\nendif\nendif\n\n# this application needs libraries first\nDEPDIRS-y += lib drivers\n\n# Link against shared libraries when needed\nifeq ($(CONFIG_RTE_LIBRTE_PMD_BOND),y)\nifneq ($(CONFIG_RTE_LIBRTE_PMD_RING),y)\n$(error Link bonding tests require CONFIG_RTE_LIBRTE_PMD_RING=y)\nelse\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),y)\nLDLIBS += -lrte_pmd_ring\nendif\nendif\nendif\n\ninclude $(RTE_SDK)/mk/rte.app.mk\n\nendif\n" }, { "path": "app/test/autotest.py", "content": "#!/usr/bin/python\n\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# Script that uses either test app or qemu controlled by python-pexpect\n\nimport sys, autotest_data, autotest_runner\n\n\n\ndef usage():\n\tprint\"Usage: autotest.py [test app|test iso image]\",\n\tprint \"[target] [whitelist|-blacklist]\"\n\nif len(sys.argv) < 3:\n\tusage()\n\tsys.exit(1)\n\ntarget = sys.argv[2]\n\ntest_whitelist=None\ntest_blacklist=None\n\n# get blacklist/whitelist\nif len(sys.argv) > 3:\n\ttestlist = sys.argv[3].split(',')\n\ttestlist = [test.lower() for test in testlist]\n\tif testlist[0].startswith('-'):\n\t\ttestlist[0] = testlist[0].lstrip('-')\n\t\ttest_blacklist = testlist\n\telse:\n\t\ttest_whitelist = testlist\n\ncmdline = \"%s -c f -n 4\"%(sys.argv[1])\n\nprint cmdline\n\nrunner = autotest_runner.AutotestRunner(cmdline, target, test_blacklist, test_whitelist)\n\nfor test_group in autotest_data.parallel_test_group_list:\n\trunner.add_parallel_test_group(test_group)\n\nfor test_group in autotest_data.non_parallel_test_group_list:\n\trunner.add_non_parallel_test_group(test_group)\n\nnum_fails = runner.run_all_tests()\n\nsys.exit(num_fails)\n" }, { "path": "app/test/autotest_data.py", "content": "#!/usr/bin/python\n\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# Test data for autotests\n\nfrom glob import glob\nfrom autotest_test_funcs import *\n\n# quick and dirty function to find out number of sockets\ndef num_sockets():\n\tresult = len(glob(\"/sys/devices/system/node/node*\"))\n\tif result == 0:\n\t\treturn 1\n\treturn result\n\n# Assign given number to each socket\n# e.g. 32 becomes 32,32 or 32,32,32,32\ndef per_sockets(num):\n return \",\".join([str(num)] * num_sockets())\n\n# groups of tests that can be run in parallel\n# the grouping has been found largely empirically\nparallel_test_group_list = [\n\n{\n\t\"Prefix\":\t\"group_1\",\n\t\"Memory\" :\tper_sockets(8),\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"Timer autotest\",\n\t\t \"Command\" : \t\"timer_autotest\",\n\t\t \"Func\" :\ttimer_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Debug autotest\",\n\t\t \"Command\" : \t\"debug_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Errno autotest\",\n\t\t \"Command\" : \t\"errno_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Meter autotest\",\n\t\t \"Command\" : \t\"meter_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Common autotest\",\n\t\t \"Command\" : \t\"common_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Dump log history\",\n\t\t \"Command\" :\t\"dump_log_history\",\n\t\t \"Func\" :\tdump_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Dump rings\",\n\t\t \"Command\" :\t\"dump_ring\",\n\t\t \"Func\" :\tdump_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Dump mempools\",\n\t\t \"Command\" :\t\"dump_mempool\",\n\t\t \"Func\" :\tdump_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t]\n},\n{\n\t\"Prefix\":\t\"group_2\",\n\t\"Memory\" :\t\"32\",\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"Memory autotest\",\n\t\t \"Command\" :\t\"memory_autotest\",\n\t\t \"Func\" :\tmemory_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Read/write lock autotest\",\n\t\t \"Command\" : \t\"rwlock_autotest\",\n\t\t \"Func\" :\trwlock_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Logs autotest\",\n\t\t \"Command\" : \t\"logs_autotest\",\n\t\t \"Func\" :\tlogs_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"CPU flags autotest\",\n\t\t \"Command\" : \t\"cpuflags_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Version autotest\",\n\t\t \"Command\" : \t\"version_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"EAL filesystem autotest\",\n\t\t \"Command\" : \t\"eal_fs_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"EAL flags autotest\",\n\t\t \"Command\" : \t\"eal_flags_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Hash autotest\",\n\t\t \"Command\" : \t\"hash_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t],\n},\n{\n\t\"Prefix\":\t\"group_3\",\n\t\"Memory\" :\tper_sockets(1024),\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"LPM autotest\",\n\t\t \"Command\" : \t\"lpm_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"IVSHMEM autotest\",\n\t\t \"Command\" : \t\"ivshmem_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Memcpy autotest\",\n\t\t \"Command\" : \t\"memcpy_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Memzone autotest\",\n\t\t \"Command\" : \t\"memzone_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"String autotest\",\n\t\t \"Command\" : \t\"string_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Alarm autotest\",\n\t\t \"Command\" :\t\"alarm_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t]\n},\n{\n\t\"Prefix\":\t\"group_4\",\n\t\"Memory\" :\tper_sockets(128),\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"PCI autotest\",\n\t\t \"Command\" :\t\"pci_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Malloc autotest\",\n\t\t \"Command\" : \t\"malloc_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Multi-process autotest\",\n\t\t \"Command\" : \t\"multiprocess_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Mbuf autotest\",\n\t\t \"Command\" : \t\"mbuf_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Per-lcore autotest\",\n\t\t \"Command\" : \t\"per_lcore_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Ring autotest\",\n\t\t \"Command\" : \t\"ring_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t]\n},\n{\n\t\"Prefix\":\t\"group_5\",\n\t\"Memory\" :\t\"32\",\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"Spinlock autotest\",\n\t\t \"Command\" : \t\"spinlock_autotest\",\n\t\t \"Func\" :\tspinlock_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Byte order autotest\",\n\t\t \"Command\" : \t\"byteorder_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"TAILQ autotest\",\n\t\t \"Command\" : \t\"tailq_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Command-line autotest\",\n\t\t \"Command\" : \t\"cmdline_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Interrupts autotest\",\n\t\t \"Command\" : \t\"interrupt_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t]\n},\n{\n\t\"Prefix\":\t\"group_6\",\n\t\"Memory\" :\tper_sockets(620),\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"Function reentrancy autotest\",\n\t\t \"Command\" : \t\"func_reentrancy_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Mempool autotest\",\n\t\t \"Command\" : \t\"mempool_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Atomics autotest\",\n\t\t \"Command\" : \t\"atomic_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Prefetch autotest\",\n\t\t \"Command\" : \t\"prefetch_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t },\n\t\t{\n\t\t \"Name\" :\"Red autotest\",\n\t\t \"Command\" : \"red_autotest\",\n\t\t \"Func\" :default_autotest,\n\t\t \"Report\" :None,\n\t\t },\n\t]\n},\n{\n\t\"Prefix\" :\t\"group_7\",\n\t\"Memory\" :\t\"400\",\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"PMD ring autotest\",\n\t\t \"Command\" :\t\"ring_pmd_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Access list control autotest\",\n\t\t \"Command\" : \t\"acl_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t {\n\t\t \"Name\" :\"Sched autotest\",\n\t\t \"Command\" : \"sched_autotest\",\n\t\t \"Func\" :default_autotest,\n\t\t \"Report\" :None,\n\t\t },\n\t]\n},\n]\n\n# tests that should not be run when any other tests are running\nnon_parallel_test_group_list = [\n\n{\n\t\"Prefix\" :\t\"kni\",\n\t\"Memory\" :\t\"512\",\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"KNI autotest\",\n\t\t \"Command\" :\t\"kni_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t]\n},\n{\n\t\"Prefix\":\t\"mempool_perf\",\n\t\"Memory\" :\tper_sockets(256),\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"Cycles autotest\",\n\t\t \"Command\" : \t\"cycles_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t\t{\n\t\t \"Name\" :\t\"Mempool performance autotest\",\n\t\t \"Command\" : \t\"mempool_perf_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t]\n},\n{\n\t\"Prefix\":\t\"memcpy_perf\",\n\t\"Memory\" :\tper_sockets(512),\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"Memcpy performance autotest\",\n\t\t \"Command\" : \t\"memcpy_perf_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t]\n},\n{\n\t\"Prefix\":\t\"hash_perf\",\n\t\"Memory\" :\tper_sockets(512),\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"Hash performance autotest\",\n\t\t \"Command\" : \t\"hash_perf_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t]\n},\n{\n\t\"Prefix\" : \"power\",\n\t\"Memory\" : per_sockets(512),\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" : \"Power autotest\",\n\t\t \"Command\" : \"power_autotest\",\n\t\t \"Func\" : default_autotest,\n\t\t \"Report\" : None,\n\t\t},\n\t]\n},\n{\n\t\"Prefix\" : \"power_acpi_cpufreq\",\n\t\"Memory\" : per_sockets(512),\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" : \"Power ACPI cpufreq autotest\",\n\t\t \"Command\" : \"power_acpi_cpufreq_autotest\",\n\t\t \"Func\" : default_autotest,\n\t\t \"Report\" : None,\n\t\t},\n\t]\n},\n{\n\t\"Prefix\" : \"power_kvm_vm\",\n\t\"Memory\" : \"512\",\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" : \"Power KVM VM autotest\",\n\t\t \"Command\" : \"power_kvm_vm_autotest\",\n\t\t \"Func\" : default_autotest,\n\t\t \"Report\" : None,\n\t\t},\n\t]\n},\n{\n\t\"Prefix\" :\t\"lpm6\",\n\t\"Memory\" :\t\"512\",\n\t\"Tests\" :\n\t[\n\t\t{\n \"Name\" : \"LPM6 autotest\",\n \"Command\" : \"lpm6_autotest\",\n \"Func\" : default_autotest,\n \"Report\" : None,\n },\n\t]\n},\n{\n\t\"Prefix\":\t\"timer_perf\",\n\t\"Memory\" :\tper_sockets(512),\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"Timer performance autotest\",\n\t\t \"Command\" : \t\"timer_perf_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t]\n},\n\n#\n# Please always make sure that ring_perf is the last test!\n#\n{\n\t\"Prefix\":\t\"ring_perf\",\n\t\"Memory\" :\tper_sockets(512),\n\t\"Tests\" :\n\t[\n\t\t{\n\t\t \"Name\" :\t\"Ring performance autotest\",\n\t\t \"Command\" : \t\"ring_perf_autotest\",\n\t\t \"Func\" :\tdefault_autotest,\n\t\t \"Report\" :\tNone,\n\t\t},\n\t]\n},\n]\n" }, { "path": "app/test/autotest_runner.py", "content": "#!/usr/bin/python\n\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# The main logic behind running autotests in parallel\n\nimport multiprocessing, sys, pexpect, time, os, StringIO, csv\n\n# wait for prompt\ndef wait_prompt(child):\n\ttry:\n\t\tchild.sendline()\n\t\tresult = child.expect([\"RTE>>\", pexpect.TIMEOUT, pexpect.EOF],\n\t\t\ttimeout = 120)\n\texcept:\n\t\treturn False\n\tif result == 0:\n\t\treturn True\n\telse:\n\t\treturn False\n\n# run a test group\n# each result tuple in results list consists of:\n# result value (0 or -1)\n# result string\n# test name\n# total test run time (double)\n# raw test log\n# test report (if not available, should be None)\n#\n# this function needs to be outside AutotestRunner class\n# because otherwise Pool won't work (or rather it will require\n# quite a bit of effort to make it work).\ndef run_test_group(cmdline, test_group):\n\tresults = []\n\tchild = None\n\tstart_time = time.time()\n\tstartuplog = None\n\n\t# run test app\n\ttry:\n\t\t# prepare logging of init\n\t\tstartuplog = StringIO.StringIO()\n\n\t\tprint >>startuplog, \"\\n%s %s\\n\" % (\"=\"*20, test_group[\"Prefix\"])\n\n\t\tchild = pexpect.spawn(cmdline, logfile=startuplog)\n\n\t\t# wait for target to boot\n\t\tif not wait_prompt(child):\n\t\t\tchild.close()\n\n\t\t\tresults.append((-1, \"Fail [No prompt]\", \"Start %s\" % test_group[\"Prefix\"],\n\t\t\t\ttime.time() - start_time, startuplog.getvalue(), None))\n\n\t\t\t# mark all tests as failed\n\t\t\tfor test in test_group[\"Tests\"]:\n\t\t\t\tresults.append((-1, \"Fail [No prompt]\", test[\"Name\"],\n\t\t\t\ttime.time() - start_time, \"\", None))\n\t\t\t# exit test\n\t\t\treturn results\n\n\texcept:\n\t\tresults.append((-1, \"Fail [Can't run]\", \"Start %s\" % test_group[\"Prefix\"],\n\t\t\t\ttime.time() - start_time, startuplog.getvalue(), None))\n\n\t\t# mark all tests as failed\n\t\tfor t in test_group[\"Tests\"]:\n\t\t\tresults.append((-1, \"Fail [Can't run]\", t[\"Name\"],\n\t\t\t\ttime.time() - start_time, \"\", None))\n\t\t# exit test\n\t\treturn results\n\n\t# startup was successful\n\tresults.append((0, \"Success\", \"Start %s\" % test_group[\"Prefix\"],\n\t\ttime.time() - start_time, startuplog.getvalue(), None))\n\n\t# run all tests in test group\n\tfor test in test_group[\"Tests\"]:\n\n\t\t# create log buffer for each test\n\t\t# in multiprocessing environment, the logging would be\n\t\t# interleaved and will create a mess, hence the buffering\n\t\tlogfile = StringIO.StringIO()\n\t\tchild.logfile = logfile\n\n\t\tresult = ()\n\n\t\t# make a note when the test started\n\t\tstart_time = time.time()\n\n\t\ttry:\n\t\t\t# print test name to log buffer\n\t\t\tprint >>logfile, \"\\n%s %s\\n\" % (\"-\"*20, test[\"Name\"])\n\n\t\t\t# run test function associated with the test\n\t\t\tresult = test[\"Func\"](child, test[\"Command\"])\n\n\t\t\t# make a note when the test was finished\n\t\t\tend_time = time.time()\n\n\t\t\t# append test data to the result tuple\n\t\t\tresult += (test[\"Name\"], end_time - start_time,\n\t\t\t\tlogfile.getvalue())\n\n\t\t\t# call report function, if any defined, and supply it with\n\t\t\t# target and complete log for test run\n\t\t\tif test[\"Report\"]:\n\t\t\t\treport = test[\"Report\"](self.target, log)\n\n\t\t\t\t# append report to results tuple\n\t\t\t\tresult += (report,)\n\t\t\telse:\n\t\t\t\t# report is None\n\t\t\t\tresult += (None,)\n\t\texcept:\n\t\t\t# make a note when the test crashed\n\t\t\tend_time = time.time()\n\n\t\t\t# mark test as failed\n\t\t\tresult = (-1, \"Fail [Crash]\", test[\"Name\"],\n\t\t\t\tend_time - start_time, logfile.getvalue(), None)\n\t\tfinally:\n\t\t\t# append the results to the results list\n\t\t\tresults.append(result)\n\n\t# regardless of whether test has crashed, try quitting it\n\ttry:\n\t\tchild.sendline(\"quit\")\n\t\tchild.close()\n\t# if the test crashed, just do nothing instead\n\texcept:\n\t\t# nop\n\t\tpass\n\n\t# return test results\n\treturn results\n\n\n\n\n\n# class representing an instance of autotests run\nclass AutotestRunner:\n\tcmdline = \"\"\n\tparallel_test_groups = []\n\tnon_parallel_test_groups = []\n\tlogfile = None\n\tcsvwriter = None\n\ttarget = \"\"\n\tstart = None\n\tn_tests = 0\n\tfails = 0\n\tlog_buffers = []\n\tblacklist = []\n\twhitelist = []\n\n\n\tdef __init__(self, cmdline, target, blacklist, whitelist):\n\t\tself.cmdline = cmdline\n\t\tself.target = target\n\t\tself.blacklist = blacklist\n\t\tself.whitelist = whitelist\n\n\t\t# log file filename\n\t\tlogfile = \"%s.log\" % target\n\t\tcsvfile = \"%s.csv\" % target\n\n\t\tself.logfile = open(logfile, \"w\")\n\t\tcsvfile = open(csvfile, \"w\")\n\t\tself.csvwriter = csv.writer(csvfile)\n\n\t\t# prepare results table\n\t\tself.csvwriter.writerow([\"test_name\",\"test_result\",\"result_str\"])\n\n\n\n\t# set up cmdline string\n\tdef __get_cmdline(self, test):\n\t\tcmdline = self.cmdline\n\n\t\t# append memory limitations for each test\n\t\t# otherwise tests won't run in parallel\n\t\tif not \"i686\" in self.target:\n\t\t\tcmdline += \" --socket-mem=%s\"% test[\"Memory\"]\n\t\telse:\n\t\t\t# affinitize startup so that tests don't fail on i686\n\t\t\tcmdline = \"taskset 1 \" + cmdline\n\t\t\tcmdline += \" -m \" + str(sum(map(int,test[\"Memory\"].split(\",\"))))\n\n\t\t# set group prefix for autotest group\n\t\t# otherwise they won't run in parallel\n\t\tcmdline += \" --file-prefix=%s\"% test[\"Prefix\"]\n\n\t\treturn cmdline\n\n\n\n\tdef add_parallel_test_group(self,test_group):\n\t\tself.parallel_test_groups.append(test_group)\n\n\tdef add_non_parallel_test_group(self,test_group):\n\t\tself.non_parallel_test_groups.append(test_group)\n\n\n\tdef __process_results(self, results):\n\t\t# this iterates over individual test results\n\t\tfor i, result in enumerate(results):\n\n\t\t\t# increase total number of tests that were run\n\t\t\t# do not include \"start\" test\n\t\t\tif i > 0:\n\t\t\t\tself.n_tests += 1\n\n\t\t\t# unpack result tuple\n\t\t\ttest_result, result_str, test_name, \\\n\t\t\t\ttest_time, log, report = result\n\n\t\t\t# get total run time\n\t\t\tcur_time = time.time()\n\t\t\ttotal_time = int(cur_time - self.start)\n\n\t\t\t# print results, test run time and total time since start\n\t\t\tprint (\"%s:\" % test_name).ljust(30),\n\t\t\tprint result_str.ljust(29),\n\t\t\tprint \"[%02dm %02ds]\" % (test_time / 60, test_time % 60),\n\n\t\t\t# don't print out total time every line, it's the same anyway\n\t\t\tif i == len(results) - 1:\n\t\t\t\tprint \"[%02dm %02ds]\" % (total_time / 60, total_time % 60)\n\t\t\telse:\n\t\t\t\tprint \"\"\n\n\t\t\t# if test failed and it wasn't a \"start\" test\n\t\t\tif test_result < 0 and not i == 0:\n\t\t\t\tself.fails += 1\n\n\t\t\t# collect logs\n\t\t\tself.log_buffers.append(log)\n\n\t\t\t# create report if it exists\n\t\t\tif report:\n\t\t\t\ttry:\n\t\t\t\t\tf = open(\"%s_%s_report.rst\" % (self.target,test_name), \"w\")\n\t\t\t\texcept IOError:\n\t\t\t\t\tprint \"Report for %s could not be created!\" % test_name\n\t\t\t\telse:\n\t\t\t\t\twith f:\n\t\t\t\t\t\tf.write(report)\n\n\t\t\t# write test result to CSV file\n\t\t\tif i != 0:\n\t\t\t\tself.csvwriter.writerow([test_name, test_result, result_str])\n\n\n\n\n\t# this function iterates over test groups and removes each\n\t# test that is not in whitelist/blacklist\n\tdef __filter_groups(self, test_groups):\n\t\tgroups_to_remove = []\n\n\t\t# filter out tests from parallel test groups\n\t\tfor i, test_group in enumerate(test_groups):\n\n\t\t\t# iterate over a copy so that we could safely delete individual tests\n\t\t\tfor test in test_group[\"Tests\"][:]:\n\t\t\t\ttest_id = test[\"Command\"]\n\n\t\t\t\t# dump tests are specified in full e.g. \"Dump_mempool\"\n\t\t\t\tif \"_autotest\" in test_id:\n\t\t\t\t\ttest_id = test_id[:-len(\"_autotest\")]\n\n\t\t\t\t# filter out blacklisted/whitelisted tests\n\t\t\t\tif self.blacklist and test_id in self.blacklist:\n\t\t\t\t\ttest_group[\"Tests\"].remove(test)\n\t\t\t\t\tcontinue\n\t\t\t\tif self.whitelist and test_id not in self.whitelist:\n\t\t\t\t\ttest_group[\"Tests\"].remove(test)\n\t\t\t\t\tcontinue\n\n\t\t\t# modify or remove original group\n\t\t\tif len(test_group[\"Tests\"]) > 0:\n\t\t\t\ttest_groups[i] = test_group\n\t\t\telse:\n\t\t\t\t# remember which groups should be deleted\n\t\t\t\t# put the numbers backwards so that we start\n\t\t\t\t# deleting from the end, not from the beginning\n\t\t\t\tgroups_to_remove.insert(0, i)\n\n\t\t# remove test groups that need to be removed\n\t\tfor i in groups_to_remove:\n\t\t\tdel test_groups[i]\n\n\t\treturn test_groups\n\n\n\n\t# iterate over test groups and run tests associated with them\n\tdef run_all_tests(self):\n\t\t# filter groups\n\t\tself.parallel_test_groups = \\\n\t\t\tself.__filter_groups(self.parallel_test_groups)\n\t\tself.non_parallel_test_groups = \\\n\t\t\tself.__filter_groups(self.non_parallel_test_groups)\n\n\t\t# create a pool of worker threads\n\t\tpool = multiprocessing.Pool(processes=1)\n\n\t\tresults = []\n\n\t\t# whatever happens, try to save as much logs as possible\n\t\ttry:\n\n\t\t\t# create table header\n\t\t\tprint \"\"\n\t\t\tprint \"Test name\".ljust(30),\n\t\t\tprint \"Test result\".ljust(29),\n\t\t\tprint \"Test\".center(9),\n\t\t\tprint \"Total\".center(9)\n\t\t\tprint \"=\" * 80\n\n\t\t\t# make a note of tests start time\n\t\t\tself.start = time.time()\n\n\t\t\t# assign worker threads to run test groups\n\t\t\tfor test_group in self.parallel_test_groups:\n\t\t\t\tresult = pool.apply_async(run_test_group,\n\t\t\t\t\t[self.__get_cmdline(test_group), test_group])\n\t\t\t\tresults.append(result)\n\n\t\t\t# iterate while we have group execution results to get\n\t\t\twhile len(results) > 0:\n\n\t\t\t\t# iterate over a copy to be able to safely delete results\n\t\t\t\t# this iterates over a list of group results\n\t\t\t\tfor group_result in results[:]:\n\n\t\t\t\t\t# if the thread hasn't finished yet, continue\n\t\t\t\t\tif not group_result.ready():\n\t\t\t\t\t\tcontinue\n\n\t\t\t\t\tres = group_result.get()\n\n\t\t\t\t\tself.__process_results(res)\n\n\t\t\t\t\t# remove result from results list once we're done with it\n\t\t\t\t\tresults.remove(group_result)\n\n\t\t\t# run non_parallel tests. they are run one by one, synchronously\n\t\t\tfor test_group in self.non_parallel_test_groups:\n\t\t\t\tgroup_result = run_test_group(self.__get_cmdline(test_group), test_group)\n\n\t\t\t\tself.__process_results(group_result)\n\n\t\t\t# get total run time\n\t\t\tcur_time = time.time()\n\t\t\ttotal_time = int(cur_time - self.start)\n\n\t\t\t# print out summary\n\t\t\tprint \"=\" * 80\n\t\t\tprint \"Total run time: %02dm %02ds\" % (total_time / 60, total_time % 60)\n\t\t\tif self.fails != 0:\n\t\t\t\tprint \"Number of failed tests: %s\" % str(self.fails)\n\n\t\t\t# write summary to logfile\n\t\t\tself.logfile.write(\"Summary\\n\")\n\t\t\tself.logfile.write(\"Target: \".ljust(15) + \"%s\\n\" % self.target)\n\t\t\tself.logfile.write(\"Tests: \".ljust(15) + \"%i\\n\" % self.n_tests)\n\t\t\tself.logfile.write(\"Failed tests: \".ljust(15) + \"%i\\n\" % self.fails)\n\t\texcept:\n\t\t\tprint \"Exception occured\"\n\t\t\tprint sys.exc_info()\n\t\t\tself.fails = 1\n\n\t\t# drop logs from all executions to a logfile\n\t\tfor buf in self.log_buffers:\n\t\t\tself.logfile.write(buf.replace(\"\\r\",\"\"))\n\n\t\tlog_buffers = []\n\n\t\treturn self.fails\n" }, { "path": "app/test/autotest_test_funcs.py", "content": "#!/usr/bin/python\n\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# Test functions\n\nimport sys, pexpect, time, os, re\n\n# default autotest, used to run most tests\n# waits for \"Test OK\"\ndef default_autotest(child, test_name):\n\tchild.sendline(test_name)\n\tresult = child.expect([\"Test OK\", \"Test Failed\",\n\t\t\"Command not found\", pexpect.TIMEOUT], timeout = 900)\n\tif result == 1:\n\t\treturn -1, \"Fail\"\n\telif result == 2:\n\t\treturn -1, \"Fail [Not found]\"\n\telif result == 3:\n\t\treturn -1, \"Fail [Timeout]\"\n\treturn 0, \"Success\"\n\n# autotest used to run dump commands\n# just fires the command\ndef dump_autotest(child, test_name):\n\tchild.sendline(test_name)\n\treturn 0, \"Success\"\n\n# memory autotest\n# reads output and waits for Test OK\ndef memory_autotest(child, test_name):\n\tchild.sendline(test_name)\n\tregexp = \"phys:0x[0-9a-f]*, len:([0-9]*), virt:0x[0-9a-f]*, socket_id:[0-9]*\"\n\tindex = child.expect([regexp, pexpect.TIMEOUT], timeout = 180)\n\tif index != 0:\n\t\treturn -1, \"Fail [Timeout]\"\n\tsize = int(child.match.groups()[0], 16)\n\tif size <= 0:\n\t\treturn -1, \"Fail [Bad size]\"\n\tindex = child.expect([\"Test OK\", \"Test Failed\",\n\t\t pexpect.TIMEOUT], timeout = 10)\n\tif index == 1:\n\t\treturn -1, \"Fail\"\n\telif index == 2:\n\t\treturn -1, \"Fail [Timeout]\"\n\treturn 0, \"Success\"\n\ndef spinlock_autotest(child, test_name):\n\ti = 0\n\tir = 0\n\tchild.sendline(test_name)\n\twhile True:\n\t\tindex = child.expect([\"Test OK\",\n\t\t\t\"Test Failed\",\n\t\t\t\"Hello from core ([0-9]*) !\",\n\t\t\t\"Hello from within recursive locks from ([0-9]*) !\",\n\t\tpexpect.TIMEOUT], timeout = 20)\n\t\t# ok\n\t\tif index == 0:\n\t\t\tbreak\n\n\t\t# message, check ordering\n\t\telif index == 2:\n\t\t\tif int(child.match.groups()[0]) < i:\n\t\t\t\treturn -1, \"Fail [Bad order]\"\n\t\t\ti = int(child.match.groups()[0])\n\t\telif index == 3:\n\t\t\tif int(child.match.groups()[0]) < ir:\n\t\t\t\treturn -1, \"Fail [Bad order]\"\n\t\t\tir = int(child.match.groups()[0])\n\n\t\t# fail\n\t\telif index == 4:\n\t\t\treturn -1, \"Fail [Timeout]\"\n\t\telif index == 1:\n\t\t\treturn -1, \"Fail\"\n\n\treturn 0, \"Success\"\n\ndef rwlock_autotest(child, test_name):\n\ti = 0\n\tchild.sendline(test_name)\n\twhile True:\n\t\tindex = child.expect([\"Test OK\",\n\t\t\t\"Test Failed\",\n\t\t\t\"Hello from core ([0-9]*) !\",\n\t\t\t\"Global write lock taken on master core ([0-9]*)\",\n\t\tpexpect.TIMEOUT], timeout = 10)\n\t\t# ok\n\t\tif index == 0:\n\t\t\tif i != 0xffff:\n\t\t\t\treturn -1, \"Fail [Message is missing]\"\n\t\t\tbreak\n\n\t\t# message, check ordering\n\t\telif index == 2:\n\t\t\tif int(child.match.groups()[0]) < i:\n\t\t\t\treturn -1, \"Fail [Bad order]\"\n\t\t\ti = int(child.match.groups()[0])\n\n\t\t# must be the last message, check ordering\n\t\telif index == 3:\n\t\t\ti = 0xffff\n\n\t\telif index == 4:\n\t\t\treturn -1, \"Fail [Timeout]\"\n\n\t\t# fail\n\t\telse:\n\t\t\treturn -1, \"Fail\"\n\n\treturn 0, \"Success\"\n\ndef logs_autotest(child, test_name):\n\ti = 0\n\tchild.sendline(test_name)\n\n\tlog_list = [\n\t\t\"TESTAPP1: this is a debug level message\",\n\t\t\"TESTAPP1: this is a info level message\",\n\t\t\"TESTAPP1: this is a warning level message\",\n\t\t\"TESTAPP2: this is a info level message\",\n\t\t\"TESTAPP2: this is a warning level message\",\n\t\t\"TESTAPP1: this is a debug level message\",\n\t\t\"TESTAPP1: this is a debug level message\",\n\t\t\"TESTAPP1: this is a info level message\",\n\t\t\"TESTAPP1: this is a warning level message\",\n\t\t\"TESTAPP2: this is a info level message\",\n\t\t\"TESTAPP2: this is a warning level message\",\n\t\t\"TESTAPP1: this is a debug level message\",\n\t]\n\n\tfor log_msg in log_list:\n\t\tindex = child.expect([log_msg,\n\t\t\t\t \"Test OK\",\n\t\t\t\t \"Test Failed\",\n\t\t\t\t pexpect.TIMEOUT], timeout = 10)\n\n\t\tif index == 3:\n\t\t\treturn -1, \"Fail [Timeout]\"\n\t\t# not ok\n\t\telif index != 0:\n\t\t\treturn -1, \"Fail\"\n\n\tindex = child.expect([\"Test OK\",\n\t\t\"Test Failed\",\n\t\tpexpect.TIMEOUT], timeout = 10)\n\n\treturn 0, \"Success\"\n\ndef timer_autotest(child, test_name):\n\ti = 0\n\tchild.sendline(test_name)\n\n\tindex = child.expect([\"Start timer stress tests \\(20 seconds\\)\",\n\t\t\"Test Failed\",\n\t\tpexpect.TIMEOUT], timeout = 10)\n\n\tif index == 1:\n\t\treturn -1, \"Fail\"\n\telif index == 2:\n\t\treturn -1, \"Fail [Timeout]\"\n\n\tindex = child.expect([\"Start timer stress tests 2\",\n\t\t\"Test Failed\",\n\t\tpexpect.TIMEOUT], timeout = 40)\n\n\tif index == 1:\n\t\treturn -1, \"Fail\"\n\telif index == 2:\n\t\treturn -1, \"Fail [Timeout]\"\n\n\tindex = child.expect([\"Start timer basic tests \\(20 seconds\\)\",\n\t\t\"Test Failed\",\n\t\tpexpect.TIMEOUT], timeout = 20)\n\n\tif index == 1:\n\t\treturn -1, \"Fail\"\n\telif index == 2:\n\t\treturn -1, \"Fail [Timeout]\"\n\n\tprev_lcore_timer1 = -1\n\n\tlcore_tim0 = -1\n\tlcore_tim1 = -1\n\tlcore_tim2 = -1\n\tlcore_tim3 = -1\n\n\twhile True:\n\t\tindex = child.expect([\"TESTTIMER: ([0-9]*): callback id=([0-9]*) count=([0-9]*) on core ([0-9]*)\",\n\t\t\t\"Test OK\",\n\t\t\t\"Test Failed\",\n\t\t\tpexpect.TIMEOUT], timeout = 10)\n\n\t\tif index == 1:\n\t\t\tbreak\n\n\t\tif index == 2:\n\t\t\treturn -1, \"Fail\"\n\t\telif index == 3:\n\t\t\treturn -1, \"Fail [Timeout]\"\n\n\t\ttry:\n\t\t\tt = int(child.match.groups()[0])\n\t\t\tid = int(child.match.groups()[1])\n\t\t\tcnt = int(child.match.groups()[2])\n\t\t\tlcore = int(child.match.groups()[3])\n\t\texcept:\n\t\t\treturn -1, \"Fail [Cannot parse]\"\n\n\t\t# timer0 always expires on the same core when cnt < 20\n\t\tif id == 0:\n\t\t\tif lcore_tim0 == -1:\n\t\t\t\tlcore_tim0 = lcore\n\t\t\telif lcore != lcore_tim0 and cnt < 20:\n\t\t\t\treturn -1, \"Fail [lcore != lcore_tim0 (%d, %d)]\"%(lcore, lcore_tim0)\n\t\t\tif cnt > 21:\n\t\t\t\treturn -1, \"Fail [tim0 cnt > 21]\"\n\n\t\t# timer1 each time expires on a different core\n\t\tif id == 1:\n\t\t\tif lcore == lcore_tim1:\n\t\t\t\treturn -1, \"Fail [lcore == lcore_tim1 (%d, %d)]\"%(lcore, lcore_tim1)\n\t\t\tlcore_tim1 = lcore\n\t\t\tif cnt > 10:\n\t\t\t\treturn -1, \"Fail [tim1 cnt > 30]\"\n\n\t\t# timer0 always expires on the same core\n\t\tif id == 2:\n\t\t\tif lcore_tim2 == -1:\n\t\t\t\tlcore_tim2 = lcore\n\t\t\telif lcore != lcore_tim2:\n\t\t\t\treturn -1, \"Fail [lcore != lcore_tim2 (%d, %d)]\"%(lcore, lcore_tim2)\n\t\t\tif cnt > 30:\n\t\t\t\treturn -1, \"Fail [tim2 cnt > 30]\"\n\n\t\t# timer0 always expires on the same core\n\t\tif id == 3:\n\t\t\tif lcore_tim3 == -1:\n\t\t\t\tlcore_tim3 = lcore\n\t\t\telif lcore != lcore_tim3:\n\t\t\t\treturn -1, \"Fail [lcore_tim3 changed (%d -> %d)]\"%(lcore, lcore_tim3)\n\t\t\tif cnt > 30:\n\t\t\t\treturn -1, \"Fail [tim3 cnt > 30]\"\n\n\t# must be 2 different cores\n\tif lcore_tim0 == lcore_tim3:\n\t\treturn -1, \"Fail [lcore_tim0 (%d) == lcore_tim3 (%d)]\"%(lcore_tim0, lcore_tim3)\n\n\treturn 0, \"Success\"\n\ndef ring_autotest(child, test_name):\n\tchild.sendline(test_name)\n\tindex = child.expect([\"Test OK\", \"Test Failed\",\n\t\tpexpect.TIMEOUT], timeout = 15)\n\tif index == 1:\n\t\treturn -1, \"Fail\"\n\telif index == 2:\n\t\treturn -1, \"Fail [Timeout]\"\n\n\tchild.sendline(\"set_watermark test 100\")\n\tchild.sendline(\"dump_ring test\")\n\tindex = child.expect([\" watermark=100\",\n\t\tpexpect.TIMEOUT], timeout = 1)\n\tif index != 0:\n\t\treturn -1, \"Fail [Bad watermark]\"\n\n\treturn 0, \"Success\"\n" }, { "path": "app/test/commands.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#ifndef __linux__\n#ifndef __FreeBSD__\n#include \n#endif\n#endif\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n/****************/\n\nstatic struct test_commands_list commands_list =\n\tTAILQ_HEAD_INITIALIZER(commands_list);\n\nvoid\nadd_test_command(struct test_command *t)\n{\n\tTAILQ_INSERT_TAIL(&commands_list, t, next);\n}\n\nstruct cmd_autotest_result {\n\tcmdline_fixed_string_t autotest;\n};\n\nstatic void cmd_autotest_parsed(void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct test_command *t;\n\tstruct cmd_autotest_result *res = parsed_result;\n\tint ret = 0;\n\n\tTAILQ_FOREACH(t, &commands_list, next) {\n\t\tif (!strcmp(res->autotest, t->command))\n\t\t\tret = t->callback();\n\t}\n\n\tif (ret == 0)\n\t\tprintf(\"Test OK\\n\");\n\telse\n\t\tprintf(\"Test Failed\\n\");\n\tfflush(stdout);\n}\n\ncmdline_parse_token_string_t cmd_autotest_autotest =\n\tTOKEN_STRING_INITIALIZER(struct cmd_autotest_result, autotest,\n\t\t\t\t \"\");\n\ncmdline_parse_inst_t cmd_autotest = {\n\t.f = cmd_autotest_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"launch autotest\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_autotest_autotest,\n\t\tNULL,\n\t},\n};\n\n/****************/\n\nstruct cmd_dump_result {\n\tcmdline_fixed_string_t dump;\n};\n\nstatic void\ndump_struct_sizes(void)\n{\n#define DUMP_SIZE(t) printf(\"sizeof(\" #t \") = %u\\n\", (unsigned)sizeof(t));\n\tDUMP_SIZE(struct rte_mbuf);\n\tDUMP_SIZE(struct rte_mempool);\n\tDUMP_SIZE(struct rte_ring);\n#undef DUMP_SIZE\n}\n\nstatic void cmd_dump_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_dump_result *res = parsed_result;\n\n\tif (!strcmp(res->dump, \"dump_physmem\"))\n\t\trte_dump_physmem_layout(stdout);\n\telse if (!strcmp(res->dump, \"dump_memzone\"))\n\t\trte_memzone_dump(stdout);\n\telse if (!strcmp(res->dump, \"dump_log_history\"))\n\t\trte_log_dump_history(stdout);\n\telse if (!strcmp(res->dump, \"dump_struct_sizes\"))\n\t\tdump_struct_sizes();\n\telse if (!strcmp(res->dump, \"dump_ring\"))\n\t\trte_ring_list_dump(stdout);\n\telse if (!strcmp(res->dump, \"dump_mempool\"))\n\t\trte_mempool_list_dump(stdout);\n\telse if (!strcmp(res->dump, \"dump_devargs\"))\n\t\trte_eal_devargs_dump(stdout);\n}\n\ncmdline_parse_token_string_t cmd_dump_dump =\n\tTOKEN_STRING_INITIALIZER(struct cmd_dump_result, dump,\n\t\t\t\t \"dump_physmem#dump_memzone#dump_log_history#\"\n\t\t\t\t \"dump_struct_sizes#dump_ring#dump_mempool#\"\n\t\t\t\t \"dump_devargs\");\n\ncmdline_parse_inst_t cmd_dump = {\n\t.f = cmd_dump_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"dump status\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_dump_dump,\n\t\tNULL,\n\t},\n};\n\n/****************/\n\nstruct cmd_dump_one_result {\n\tcmdline_fixed_string_t dump;\n\tcmdline_fixed_string_t name;\n};\n\nstatic void cmd_dump_one_parsed(void *parsed_result, struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_dump_one_result *res = parsed_result;\n\n\tif (!strcmp(res->dump, \"dump_ring\")) {\n\t\tstruct rte_ring *r;\n\t\tr = rte_ring_lookup(res->name);\n\t\tif (r == NULL) {\n\t\t\tcmdline_printf(cl, \"Cannot find ring\\n\");\n\t\t\treturn;\n\t\t}\n\t\trte_ring_dump(stdout, r);\n\t}\n\telse if (!strcmp(res->dump, \"dump_mempool\")) {\n\t\tstruct rte_mempool *mp;\n\t\tmp = rte_mempool_lookup(res->name);\n\t\tif (mp == NULL) {\n\t\t\tcmdline_printf(cl, \"Cannot find mempool\\n\");\n\t\t\treturn;\n\t\t}\n\t\trte_mempool_dump(stdout, mp);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_dump_one_dump =\n\tTOKEN_STRING_INITIALIZER(struct cmd_dump_one_result, dump,\n\t\t\t\t \"dump_ring#dump_mempool\");\n\ncmdline_parse_token_string_t cmd_dump_one_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_dump_one_result, name, NULL);\n\ncmdline_parse_inst_t cmd_dump_one = {\n\t.f = cmd_dump_one_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"dump one ring/mempool: dump_ring|dump_mempool \",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_dump_one_dump,\n\t\t(void *)&cmd_dump_one_name,\n\t\tNULL,\n\t},\n};\n\n/****************/\n\nstruct cmd_set_ring_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t name;\n\tuint32_t value;\n};\n\nstatic void cmd_set_ring_parsed(void *parsed_result, struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_ring_result *res = parsed_result;\n\tstruct rte_ring *r;\n\tint ret;\n\n\tr = rte_ring_lookup(res->name);\n\tif (r == NULL) {\n\t\tcmdline_printf(cl, \"Cannot find ring\\n\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->set, \"set_watermark\")) {\n\t\tret = rte_ring_set_water_mark(r, res->value);\n\t\tif (ret != 0)\n\t\t\tcmdline_printf(cl, \"Cannot set water mark\\n\");\n\t}\n}\n\ncmdline_parse_token_string_t cmd_set_ring_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_ring_result, set,\n\t\t\t\t \"set_watermark\");\n\ncmdline_parse_token_string_t cmd_set_ring_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_ring_result, name, NULL);\n\ncmdline_parse_token_num_t cmd_set_ring_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_ring_result, value, UINT32);\n\ncmdline_parse_inst_t cmd_set_ring = {\n\t.f = cmd_set_ring_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"set watermark: \"\n\t\t\t\"set_watermark \",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_set_ring_set,\n\t\t(void *)&cmd_set_ring_name,\n\t\t(void *)&cmd_set_ring_value,\n\t\tNULL,\n\t},\n};\n\n/****************/\n\nstruct cmd_quit_result {\n\tcmdline_fixed_string_t quit;\n};\n\nstatic void\ncmd_quit_parsed(__attribute__((unused)) void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tcmdline_quit(cl);\n}\n\ncmdline_parse_token_string_t cmd_quit_quit =\n\tTOKEN_STRING_INITIALIZER(struct cmd_quit_result, quit,\n\t\t\t\t \"quit\");\n\ncmdline_parse_inst_t cmd_quit = {\n\t.f = cmd_quit_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"exit application\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_quit_quit,\n\t\tNULL,\n\t},\n};\n\n/****************/\n\nstruct cmd_set_rxtx_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t mode;\n};\n\nstatic void cmd_set_rxtx_parsed(void *parsed_result, struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_rxtx_result *res = parsed_result;\n\tif (test_set_rxtx_conf(res->mode) < 0)\n\t\tcmdline_printf(cl, \"Cannot find such mode\\n\");\n}\n\ncmdline_parse_token_string_t cmd_set_rxtx_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_rxtx_result, set,\n\t\t\t\t \"set_rxtx_mode\");\n\ncmdline_parse_token_string_t cmd_set_rxtx_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_rxtx_result, mode, NULL);\n\ncmdline_parse_inst_t cmd_set_rxtx = {\n\t.f = cmd_set_rxtx_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"set rxtx routine: \"\n\t\t\t\"set_rxtx \",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_set_rxtx_set,\n\t\t(void *)&cmd_set_rxtx_mode,\n\t\tNULL,\n\t},\n};\n\n/****************/\n\nstruct cmd_set_rxtx_anchor {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t type;\n};\n\nstatic void\ncmd_set_rxtx_anchor_parsed(void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_set_rxtx_anchor *res = parsed_result;\n\tif (test_set_rxtx_anchor(res->type) < 0)\n\t\tcmdline_printf(cl, \"Cannot find such anchor\\n\");\n}\n\ncmdline_parse_token_string_t cmd_set_rxtx_anchor_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_rxtx_anchor, set,\n\t\t\t\t \"set_rxtx_anchor\");\n\ncmdline_parse_token_string_t cmd_set_rxtx_anchor_type =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_rxtx_anchor, type, NULL);\n\ncmdline_parse_inst_t cmd_set_rxtx_anchor = {\n\t.f = cmd_set_rxtx_anchor_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"set rxtx anchor: \"\n\t\t\t\"set_rxtx_anchor \",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_set_rxtx_anchor_set,\n\t\t(void *)&cmd_set_rxtx_anchor_type,\n\t\tNULL,\n\t},\n};\n\n/****************/\n\n/* for stream control */\nstruct cmd_set_rxtx_sc {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t type;\n};\n\nstatic void\ncmd_set_rxtx_sc_parsed(void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_set_rxtx_sc *res = parsed_result;\n\tif (test_set_rxtx_sc(res->type) < 0)\n\t\tcmdline_printf(cl, \"Cannot find such stream control\\n\");\n}\n\ncmdline_parse_token_string_t cmd_set_rxtx_sc_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_rxtx_sc, set,\n\t\t\t\t \"set_rxtx_sc\");\n\ncmdline_parse_token_string_t cmd_set_rxtx_sc_type =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_rxtx_sc, type, NULL);\n\ncmdline_parse_inst_t cmd_set_rxtx_sc = {\n\t.f = cmd_set_rxtx_sc_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"set rxtx stream control: \"\n\t\t\t\"set_rxtx_sc \",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_set_rxtx_sc_set,\n\t\t(void *)&cmd_set_rxtx_sc_type,\n\t\tNULL,\n\t},\n};\n\n/****************/\n\n\ncmdline_parse_ctx_t main_ctx[] = {\n\t(cmdline_parse_inst_t *)&cmd_autotest,\n\t(cmdline_parse_inst_t *)&cmd_dump,\n\t(cmdline_parse_inst_t *)&cmd_dump_one,\n\t(cmdline_parse_inst_t *)&cmd_set_ring,\n\t(cmdline_parse_inst_t *)&cmd_quit,\n\t(cmdline_parse_inst_t *)&cmd_set_rxtx,\n\t(cmdline_parse_inst_t *)&cmd_set_rxtx_anchor,\n\t(cmdline_parse_inst_t *)&cmd_set_rxtx_sc,\n\tNULL,\n};\n\nint commands_init(void)\n{\n\tstruct test_command *t;\n\tchar *commands, *ptr;\n\tint commands_len = 0;\n\n\tTAILQ_FOREACH(t, &commands_list, next) {\n\t\tcommands_len += strlen(t->command) + 1;\n\t}\n\n\tcommands = malloc(commands_len);\n\tif (!commands)\n\t\treturn -1;\n\n\tptr = commands;\n\tTAILQ_FOREACH(t, &commands_list, next) {\n\t\tptr += sprintf(ptr, \"%s#\", t->command);\n\t}\n\tptr--;\n\tptr[0] = '\\0';\n\n\tcmd_autotest_autotest.string_data.str = commands;\n\treturn 0;\n}\n" }, { "path": "app/test/packet_burst_generator.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \"packet_burst_generator.h\"\n\n#define UDP_SRC_PORT 1024\n#define UDP_DST_PORT 1024\n\n\n#define IP_DEFTTL 64 /* from RFC 1340. */\n#define IP_VERSION 0x40\n#define IP_HDRLEN 0x05 /* default IP header length == five 32-bits words. */\n#define IP_VHL_DEF (IP_VERSION | IP_HDRLEN)\n\nstatic void\ncopy_buf_to_pkt_segs(void *buf, unsigned len, struct rte_mbuf *pkt,\n\t\tunsigned offset)\n{\n\tstruct rte_mbuf *seg;\n\tvoid *seg_buf;\n\tunsigned copy_len;\n\n\tseg = pkt;\n\twhile (offset >= seg->data_len) {\n\t\toffset -= seg->data_len;\n\t\tseg = seg->next;\n\t}\n\tcopy_len = seg->data_len - offset;\n\tseg_buf = rte_pktmbuf_mtod_offset(seg, char *, offset);\n\twhile (len > copy_len) {\n\t\trte_memcpy(seg_buf, buf, (size_t) copy_len);\n\t\tlen -= copy_len;\n\t\tbuf = ((char *) buf + copy_len);\n\t\tseg = seg->next;\n\t\tseg_buf = rte_pktmbuf_mtod(seg, void *);\n\t}\n\trte_memcpy(seg_buf, buf, (size_t) len);\n}\n\nstatic inline void\ncopy_buf_to_pkt(void *buf, unsigned len, struct rte_mbuf *pkt, unsigned offset)\n{\n\tif (offset + len <= pkt->data_len) {\n\t\trte_memcpy(rte_pktmbuf_mtod_offset(pkt, char *, offset), buf,\n\t\t\t (size_t) len);\n\t\treturn;\n\t}\n\tcopy_buf_to_pkt_segs(buf, len, pkt, offset);\n}\n\nvoid\ninitialize_eth_header(struct ether_hdr *eth_hdr, struct ether_addr *src_mac,\n\t\tstruct ether_addr *dst_mac, uint16_t ether_type,\n\t\tuint8_t vlan_enabled, uint16_t van_id)\n{\n\tether_addr_copy(dst_mac, ð_hdr->d_addr);\n\tether_addr_copy(src_mac, ð_hdr->s_addr);\n\n\tif (vlan_enabled) {\n\t\tstruct vlan_hdr *vhdr = (struct vlan_hdr *)((uint8_t *)eth_hdr +\n\t\t\t\tsizeof(struct ether_hdr));\n\n\t\teth_hdr->ether_type = rte_cpu_to_be_16(ETHER_TYPE_VLAN);\n\n\t\tvhdr->eth_proto = rte_cpu_to_be_16(ether_type);\n\t\tvhdr->vlan_tci = van_id;\n\t} else {\n\t\teth_hdr->ether_type = rte_cpu_to_be_16(ether_type);\n\t}\n}\n\nvoid\ninitialize_arp_header(struct arp_hdr *arp_hdr, struct ether_addr *src_mac,\n\t\tstruct ether_addr *dst_mac, uint32_t src_ip, uint32_t dst_ip,\n\t\tuint32_t opcode)\n{\n\tarp_hdr->arp_hrd = rte_cpu_to_be_16(ARP_HRD_ETHER);\n\tarp_hdr->arp_pro = rte_cpu_to_be_16(ETHER_TYPE_IPv4);\n\tarp_hdr->arp_hln = ETHER_ADDR_LEN;\n\tarp_hdr->arp_pln = sizeof(uint32_t);\n\tarp_hdr->arp_op = rte_cpu_to_be_16(opcode);\n\tether_addr_copy(src_mac, &arp_hdr->arp_data.arp_sha);\n\tarp_hdr->arp_data.arp_sip = src_ip;\n\tether_addr_copy(dst_mac, &arp_hdr->arp_data.arp_tha);\n\tarp_hdr->arp_data.arp_tip = dst_ip;\n}\n\nuint16_t\ninitialize_udp_header(struct udp_hdr *udp_hdr, uint16_t src_port,\n\t\tuint16_t dst_port, uint16_t pkt_data_len)\n{\n\tuint16_t pkt_len;\n\n\tpkt_len = (uint16_t) (pkt_data_len + sizeof(struct udp_hdr));\n\n\tudp_hdr->src_port = rte_cpu_to_be_16(src_port);\n\tudp_hdr->dst_port = rte_cpu_to_be_16(dst_port);\n\tudp_hdr->dgram_len = rte_cpu_to_be_16(pkt_len);\n\tudp_hdr->dgram_cksum = 0; /* No UDP checksum. */\n\n\treturn pkt_len;\n}\n\n\nuint16_t\ninitialize_ipv6_header(struct ipv6_hdr *ip_hdr, uint8_t *src_addr,\n\t\tuint8_t *dst_addr, uint16_t pkt_data_len)\n{\n\tip_hdr->vtc_flow = 0;\n\tip_hdr->payload_len = pkt_data_len;\n\tip_hdr->proto = IPPROTO_UDP;\n\tip_hdr->hop_limits = IP_DEFTTL;\n\n\trte_memcpy(ip_hdr->src_addr, src_addr, sizeof(ip_hdr->src_addr));\n\trte_memcpy(ip_hdr->dst_addr, dst_addr, sizeof(ip_hdr->dst_addr));\n\n\treturn (uint16_t) (pkt_data_len + sizeof(struct ipv6_hdr));\n}\n\nuint16_t\ninitialize_ipv4_header(struct ipv4_hdr *ip_hdr, uint32_t src_addr,\n\t\tuint32_t dst_addr, uint16_t pkt_data_len)\n{\n\tuint16_t pkt_len;\n\tunaligned_uint16_t *ptr16;\n\tuint32_t ip_cksum;\n\n\t/*\n\t * Initialize IP header.\n\t */\n\tpkt_len = (uint16_t) (pkt_data_len + sizeof(struct ipv4_hdr));\n\n\tip_hdr->version_ihl = IP_VHL_DEF;\n\tip_hdr->type_of_service = 0;\n\tip_hdr->fragment_offset = 0;\n\tip_hdr->time_to_live = IP_DEFTTL;\n\tip_hdr->next_proto_id = IPPROTO_UDP;\n\tip_hdr->packet_id = 0;\n\tip_hdr->total_length = rte_cpu_to_be_16(pkt_len);\n\tip_hdr->src_addr = rte_cpu_to_be_32(src_addr);\n\tip_hdr->dst_addr = rte_cpu_to_be_32(dst_addr);\n\n\t/*\n\t * Compute IP header checksum.\n\t */\n\tptr16 = (unaligned_uint16_t *)ip_hdr;\n\tip_cksum = 0;\n\tip_cksum += ptr16[0]; ip_cksum += ptr16[1];\n\tip_cksum += ptr16[2]; ip_cksum += ptr16[3];\n\tip_cksum += ptr16[4];\n\tip_cksum += ptr16[6]; ip_cksum += ptr16[7];\n\tip_cksum += ptr16[8]; ip_cksum += ptr16[9];\n\n\t/*\n\t * Reduce 32 bit checksum to 16 bits and complement it.\n\t */\n\tip_cksum = ((ip_cksum & 0xFFFF0000) >> 16) +\n\t\t(ip_cksum & 0x0000FFFF);\n\tip_cksum %= 65536;\n\tip_cksum = (~ip_cksum) & 0x0000FFFF;\n\tif (ip_cksum == 0)\n\t\tip_cksum = 0xFFFF;\n\tip_hdr->hdr_checksum = (uint16_t) ip_cksum;\n\n\treturn pkt_len;\n}\n\n\n\n/*\n * The maximum number of segments per packet is used when creating\n * scattered transmit packets composed of a list of mbufs.\n */\n#define RTE_MAX_SEGS_PER_PKT 255 /**< pkt.nb_segs is a 8-bit unsigned char. */\n\n\nint\ngenerate_packet_burst(struct rte_mempool *mp, struct rte_mbuf **pkts_burst,\n\t\tstruct ether_hdr *eth_hdr, uint8_t vlan_enabled, void *ip_hdr,\n\t\tuint8_t ipv4, struct udp_hdr *udp_hdr, int nb_pkt_per_burst,\n\t\tuint8_t pkt_len, uint8_t nb_pkt_segs)\n{\n\tint i, nb_pkt = 0;\n\tsize_t eth_hdr_size;\n\n\tstruct rte_mbuf *pkt_seg;\n\tstruct rte_mbuf *pkt;\n\n\tfor (nb_pkt = 0; nb_pkt < nb_pkt_per_burst; nb_pkt++) {\n\t\tpkt = rte_pktmbuf_alloc(mp);\n\t\tif (pkt == NULL) {\nnomore_mbuf:\n\t\t\tif (nb_pkt == 0)\n\t\t\t\treturn -1;\n\t\t\tbreak;\n\t\t}\n\n\t\tpkt->data_len = pkt_len;\n\t\tpkt_seg = pkt;\n\t\tfor (i = 1; i < nb_pkt_segs; i++) {\n\t\t\tpkt_seg->next = rte_pktmbuf_alloc(mp);\n\t\t\tif (pkt_seg->next == NULL) {\n\t\t\t\tpkt->nb_segs = i;\n\t\t\t\trte_pktmbuf_free(pkt);\n\t\t\t\tgoto nomore_mbuf;\n\t\t\t}\n\t\t\tpkt_seg = pkt_seg->next;\n\t\t\tpkt_seg->data_len = pkt_len;\n\t\t}\n\t\tpkt_seg->next = NULL; /* Last segment of packet. */\n\n\t\t/*\n\t\t * Copy headers in first packet segment(s).\n\t\t */\n\t\tif (vlan_enabled)\n\t\t\teth_hdr_size = sizeof(struct ether_hdr) + sizeof(struct vlan_hdr);\n\t\telse\n\t\t\teth_hdr_size = sizeof(struct ether_hdr);\n\n\t\tcopy_buf_to_pkt(eth_hdr, eth_hdr_size, pkt, 0);\n\n\t\tif (ipv4) {\n\t\t\tcopy_buf_to_pkt(ip_hdr, sizeof(struct ipv4_hdr), pkt, eth_hdr_size);\n\t\t\tcopy_buf_to_pkt(udp_hdr, sizeof(*udp_hdr), pkt, eth_hdr_size +\n\t\t\t\t\tsizeof(struct ipv4_hdr));\n\t\t} else {\n\t\t\tcopy_buf_to_pkt(ip_hdr, sizeof(struct ipv6_hdr), pkt, eth_hdr_size);\n\t\t\tcopy_buf_to_pkt(udp_hdr, sizeof(*udp_hdr), pkt, eth_hdr_size +\n\t\t\t\t\tsizeof(struct ipv6_hdr));\n\t\t}\n\n\t\t/*\n\t\t * Complete first mbuf of packet and append it to the\n\t\t * burst of packets to be transmitted.\n\t\t */\n\t\tpkt->nb_segs = nb_pkt_segs;\n\t\tpkt->pkt_len = pkt_len;\n\t\tpkt->l2_len = eth_hdr_size;\n\n\t\tif (ipv4) {\n\t\t\tpkt->vlan_tci = ETHER_TYPE_IPv4;\n\t\t\tpkt->l3_len = sizeof(struct ipv4_hdr);\n#ifndef RTE_NEXT_ABI\n\t\t\tif (vlan_enabled)\n\t\t\t\tpkt->ol_flags = PKT_RX_IPV4_HDR | PKT_RX_VLAN_PKT;\n\t\t\telse\n\t\t\t\tpkt->ol_flags = PKT_RX_IPV4_HDR;\n#endif\n\t\t} else {\n\t\t\tpkt->vlan_tci = ETHER_TYPE_IPv6;\n\t\t\tpkt->l3_len = sizeof(struct ipv6_hdr);\n#ifndef RTE_NEXT_ABI\n\t\t\tif (vlan_enabled)\n\t\t\t\tpkt->ol_flags = PKT_RX_IPV6_HDR | PKT_RX_VLAN_PKT;\n\t\t\telse\n\t\t\t\tpkt->ol_flags = PKT_RX_IPV6_HDR;\n#endif\n\t\t}\n\n\t\tpkts_burst[nb_pkt] = pkt;\n\t}\n\n\treturn nb_pkt;\n}\n" }, { "path": "app/test/packet_burst_generator.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef PACKET_BURST_GENERATOR_H_\n#define PACKET_BURST_GENERATOR_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n#include \n#include \n#include \n\n\n#define IPV4_ADDR(a, b, c, d)(((a & 0xff) << 24) | ((b & 0xff) << 16) | \\\n\t\t((c & 0xff) << 8) | (d & 0xff))\n\n#define PACKET_BURST_GEN_PKT_LEN 60\n#define PACKET_BURST_GEN_PKT_LEN_128 128\n\nvoid\ninitialize_eth_header(struct ether_hdr *eth_hdr, struct ether_addr *src_mac,\n\t\tstruct ether_addr *dst_mac, uint16_t ether_type,\n\t\tuint8_t vlan_enabled, uint16_t van_id);\n\nvoid\ninitialize_arp_header(struct arp_hdr *arp_hdr, struct ether_addr *src_mac,\n\t\tstruct ether_addr *dst_mac, uint32_t src_ip, uint32_t dst_ip,\n\t\tuint32_t opcode);\n\nuint16_t\ninitialize_udp_header(struct udp_hdr *udp_hdr, uint16_t src_port,\n\t\tuint16_t dst_port, uint16_t pkt_data_len);\n\n\nuint16_t\ninitialize_ipv6_header(struct ipv6_hdr *ip_hdr, uint8_t *src_addr,\n\t\tuint8_t *dst_addr, uint16_t pkt_data_len);\n\nuint16_t\ninitialize_ipv4_header(struct ipv4_hdr *ip_hdr, uint32_t src_addr,\n\t\tuint32_t dst_addr, uint16_t pkt_data_len);\n\nint\ngenerate_packet_burst(struct rte_mempool *mp, struct rte_mbuf **pkts_burst,\n\t\tstruct ether_hdr *eth_hdr, uint8_t vlan_enabled, void *ip_hdr,\n\t\tuint8_t ipv4, struct udp_hdr *udp_hdr, int nb_pkt_per_burst,\n\t\tuint8_t pkt_len, uint8_t nb_pkt_segs);\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* PACKET_BURST_GENERATOR_H_ */\n" }, { "path": "app/test/process.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _PROCESS_H_\n#define _PROCESS_H_\n\n#ifdef RTE_EXEC_ENV_BSDAPP\n#define self \"curproc\"\n#define exe \"file\"\n#else\n#define self \"self\"\n#define exe \"exe\"\n#endif\n\n/*\n * launches a second copy of the test process using the given argv parameters,\n * which should include argv[0] as the process name. To identify in the\n * subprocess the source of the call, the env_value parameter is set in the\n * environment as $RTE_TEST\n */\nstatic inline int\nprocess_dup(const char *const argv[], int numargs, const char *env_value)\n{\n\tint num;\n#ifdef RTE_LIBRTE_XEN_DOM0\n\tchar *argv_cpy[numargs + 2];\n#else\n\tchar *argv_cpy[numargs + 1];\n#endif\n\tint i, fd, status;\n\tchar path[32];\n\n\tpid_t pid = fork();\n\tif (pid < 0)\n\t\treturn -1;\n\telse if (pid == 0) {\n\t\t/* make a copy of the arguments to be passed to exec */\n\t\tfor (i = 0; i < numargs; i++)\n\t\t\targv_cpy[i] = strdup(argv[i]);\n#ifdef RTE_LIBRTE_XEN_DOM0\n\t\targv_cpy[i] = strdup(\"--xen-dom0\");\n\t\targv_cpy[i + 1] = NULL;\n\t\tnum = numargs + 1;\n#else\n\t\targv_cpy[i] = NULL;\n\t\tnum = numargs;\n#endif\n\n\t\t/* close all open file descriptors, check /proc/self/fd to only\n\t\t * call close on open fds. Exclude fds 0, 1 and 2*/\n\t\tfor (fd = getdtablesize(); fd > 2; fd-- ) {\n\t\t\tsnprintf(path, sizeof(path), \"/proc/\" exe \"/fd/%d\", fd);\n\t\t\tif (access(path, F_OK) == 0)\n\t\t\t\tclose(fd);\n\t\t}\n\t\tprintf(\"Running binary with argv[]:\");\n\t\tfor (i = 0; i < num; i++)\n\t\t\tprintf(\"'%s' \", argv_cpy[i]);\n\t\tprintf(\"\\n\");\n\n\t\t/* set the environment variable */\n\t\tif (setenv(RECURSIVE_ENV_VAR, env_value, 1) != 0)\n\t\t\trte_panic(\"Cannot export environment variable\\n\");\n\t\tif (execv(\"/proc/\" self \"/\" exe, argv_cpy) < 0)\n\t\t\trte_panic(\"Cannot exec\\n\");\n\t}\n\t/* parent process does a wait */\n\twhile (wait(&status) != pid)\n\t\t;\n\treturn status;\n}\n\n#endif /* _PROCESS_H_ */\n" }, { "path": "app/test/test.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#ifdef RTE_LIBRTE_CMDLINE\n#include \n#include \n#include \n#include \nextern cmdline_parse_ctx_t main_ctx[];\n#endif\n\n#include \n#include \n#include \n#include \n#include \n#include \n#ifdef RTE_LIBRTE_TIMER\n#include \n#endif\n\n#include \"test.h\"\n\n#define RTE_LOGTYPE_APP RTE_LOGTYPE_USER1\n\nconst char *prgname; /* to be set to argv[0] */\n\nstatic const char *recursive_call; /* used in linuxapp for MP and other tests */\n\nstatic int\nno_action(void){ return 0; }\n\nstatic int\ndo_recursive_call(void)\n{\n\tunsigned i;\n\tstruct {\n\t\tconst char *env_var;\n\t\tint (*action_fn)(void);\n\t} actions[] = {\n\t\t\t{ \"run_secondary_instances\", test_mp_secondary },\n\t\t\t{ \"test_missing_c_flag\", no_action },\n\t\t\t{ \"test_master_lcore_flag\", no_action },\n\t\t\t{ \"test_missing_n_flag\", no_action },\n\t\t\t{ \"test_no_hpet_flag\", no_action },\n\t\t\t{ \"test_whitelist_flag\", no_action },\n\t\t\t{ \"test_invalid_b_flag\", no_action },\n\t\t\t{ \"test_invalid_vdev_flag\", no_action },\n\t\t\t{ \"test_invalid_r_flag\", no_action },\n#ifdef RTE_LIBRTE_XEN_DOM0\n\t\t\t{ \"test_dom0_misc_flags\", no_action },\n#else\n\t\t\t{ \"test_misc_flags\", no_action },\n#endif\n\t\t\t{ \"test_memory_flags\", no_action },\n\t\t\t{ \"test_file_prefix\", no_action },\n\t\t\t{ \"test_no_huge_flag\", no_action },\n#ifdef RTE_LIBRTE_IVSHMEM\n\t\t\t{ \"test_ivshmem\", test_ivshmem },\n#endif\n\t};\n\n\tif (recursive_call == NULL)\n\t\treturn -1;\n\tfor (i = 0; i < sizeof(actions)/sizeof(actions[0]); i++) {\n\t\tif (strcmp(actions[i].env_var, recursive_call) == 0)\n\t\t\treturn (actions[i].action_fn)();\n\t}\n\tprintf(\"ERROR - missing action to take for %s\\n\", recursive_call);\n\treturn -1;\n}\n\nint\nmain(int argc, char **argv)\n{\n#ifdef RTE_LIBRTE_CMDLINE\n\tstruct cmdline *cl;\n#endif\n\tint ret;\n\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\treturn -1;\n\n#ifdef RTE_LIBRTE_TIMER\n\trte_timer_subsystem_init();\n#endif\n\n\tif (commands_init() < 0)\n\t\treturn -1;\n\n\targv += ret;\n\n\tprgname = argv[0];\n\n\tif ((recursive_call = getenv(RECURSIVE_ENV_VAR)) != NULL)\n\t\treturn do_recursive_call();\n\n#ifdef RTE_LIBEAL_USE_HPET\n\tif (rte_eal_hpet_init(1) < 0)\n#endif\n\t\tRTE_LOG(INFO, APP,\n\t\t\t\t\"HPET is not enabled, using TSC as default timer\\n\");\n\n\n#ifdef RTE_LIBRTE_CMDLINE\n\tcl = cmdline_stdin_new(main_ctx, \"RTE>>\");\n\tif (cl == NULL) {\n\t\treturn -1;\n\t}\n\tcmdline_interact(cl);\n\tcmdline_stdin_exit(cl);\n#endif\n\n\treturn 0;\n}\n\n\nint\nunit_test_suite_runner(struct unit_test_suite *suite)\n{\n\tint retval, i = 0;\n\n\tif (suite->suite_name)\n\t\tprintf(\"Test Suite : %s\\n\", suite->suite_name);\n\n\tif (suite->setup)\n\t\tif (suite->setup() != 0)\n\t\t\treturn -1;\n\n\twhile (suite->unit_test_cases[i].testcase) {\n\t\t/* Run test case setup */\n\t\tif (suite->unit_test_cases[i].setup) {\n\t\t\tretval = suite->unit_test_cases[i].setup();\n\t\t\tif (retval != 0)\n\t\t\t\treturn retval;\n\t\t}\n\n\t\t/* Run test case */\n\t\tif (suite->unit_test_cases[i].testcase() == 0) {\n\t\t\tprintf(\"TestCase %2d: %s\\n\", i,\n\t\t\t\t\tsuite->unit_test_cases[i].success_msg ?\n\t\t\t\t\tsuite->unit_test_cases[i].success_msg :\n\t\t\t\t\t\"passed\");\n\t\t}\n\t\telse {\n\t\t\tprintf(\"TestCase %2d: %s\\n\", i, suite->unit_test_cases[i].fail_msg ?\n\t\t\t\t\tsuite->unit_test_cases[i].fail_msg :\n\t\t\t\t\t\"failed\");\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Run test case teardown */\n\t\tif (suite->unit_test_cases[i].teardown) {\n\t\t\tretval = suite->unit_test_cases[i].teardown();\n\t\t\tif (retval != 0)\n\t\t\t\treturn retval;\n\t\t}\n\n\t\ti++;\n\t}\n\n\t/* Run test suite teardown */\n\tif (suite->teardown)\n\t\tif (suite->teardown() != 0)\n\t\t\treturn -1;\n\n\treturn 0;\n}\n" }, { "path": "app/test/test.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _TEST_H_\n#define _TEST_H_\n\n#include \n\n#define TEST_SUCCESS (0)\n#define TEST_FAILED (-1)\n\n/* Before including test.h file you can define\n * TEST_TRACE_FAILURE(_file, _line, _func) macro to better trace/debug test\n * failures. Mostly useful in test development phase. */\n#ifndef TEST_TRACE_FAILURE\n# define TEST_TRACE_FAILURE(_file, _line, _func)\n#endif\n\n#define TEST_ASSERT(cond, msg, ...) do { \\\n\t\tif (!(cond)) { \\\n\t\t\tprintf(\"TestCase %s() line %d failed: \" \\\n\t\t\t\tmsg \"\\n\", __func__, __LINE__, ##__VA_ARGS__); \\\n\t\t\tTEST_TRACE_FAILURE(__FILE__, __LINE__, __func__); \\\n\t\t\treturn TEST_FAILED; \\\n\t\t} \\\n} while (0)\n\n#define TEST_ASSERT_EQUAL(a, b, msg, ...) do { \\\n\t\tif (!(a == b)) { \\\n\t\t\tprintf(\"TestCase %s() line %d failed: \" \\\n\t\t\t\tmsg \"\\n\", __func__, __LINE__, ##__VA_ARGS__); \\\n\t\t\tTEST_TRACE_FAILURE(__FILE__, __LINE__, __func__); \\\n\t\t\treturn TEST_FAILED; \\\n\t\t} \\\n} while (0)\n\n#define TEST_ASSERT_NOT_EQUAL(a, b, msg, ...) do { \\\n\t\tif (!(a != b)) { \\\n\t\t\tprintf(\"TestCase %s() line %d failed: \" \\\n\t\t\t\tmsg \"\\n\", __func__, __LINE__, ##__VA_ARGS__); \\\n\t\t\tTEST_TRACE_FAILURE(__FILE__, __LINE__, __func__); \\\n\t\t\treturn TEST_FAILED; \\\n\t\t} \\\n} while (0)\n\n#define TEST_ASSERT_SUCCESS(val, msg, ...) do { \\\n\t\ttypeof(val) _val = (val); \\\n\t\tif (!(_val == 0)) { \\\n\t\t\tprintf(\"TestCase %s() line %d failed (err %d): \" \\\n\t\t\t\tmsg \"\\n\", __func__, __LINE__, _val, \\\n\t\t\t\t##__VA_ARGS__); \\\n\t\t\tTEST_TRACE_FAILURE(__FILE__, __LINE__, __func__); \\\n\t\t\treturn TEST_FAILED; \\\n\t\t} \\\n} while (0)\n\n#define TEST_ASSERT_FAIL(val, msg, ...) do { \\\n\t\tif (!(val != 0)) { \\\n\t\t\tprintf(\"TestCase %s() line %d failed: \" \\\n\t\t\t\tmsg \"\\n\", __func__, __LINE__, ##__VA_ARGS__); \\\n\t\t\tTEST_TRACE_FAILURE(__FILE__, __LINE__, __func__); \\\n\t\t\treturn TEST_FAILED; \\\n\t\t} \\\n} while (0)\n\n#define TEST_ASSERT_NULL(val, msg, ...) do { \\\n\t\tif (!(val == NULL)) { \\\n\t\t\tprintf(\"TestCase %s() line %d failed: \" \\\n\t\t\t\tmsg \"\\n\", __func__, __LINE__, ##__VA_ARGS__); \\\n\t\t\tTEST_TRACE_FAILURE(__FILE__, __LINE__, __func__); \\\n\t\t\treturn TEST_FAILED; \\\n\t\t} \\\n} while (0)\n\n#define TEST_ASSERT_NOT_NULL(val, msg, ...) do { \\\n\t\tif (!(val != NULL)) { \\\n\t\t\tprintf(\"TestCase %s() line %d failed: \" \\\n\t\t\t\tmsg \"\\n\", __func__, __LINE__, ##__VA_ARGS__); \\\n\t\t\tTEST_TRACE_FAILURE(__FILE__, __LINE__, __func__); \\\n\t\t\treturn TEST_FAILED; \\\n\t\t} \\\n} while (0)\n\nstruct unit_test_case {\n\tint (*setup)(void);\n\tint (*teardown)(void);\n\tint (*testcase)(void);\n\tconst char *success_msg;\n\tconst char *fail_msg;\n};\n\n#define TEST_CASE(fn) { NULL, NULL, fn, #fn \" succeeded\", #fn \" failed\"}\n\n#define TEST_CASE_NAMED(name, fn) { NULL, NULL, fn, name \" succeeded\", \\\n\t\tname \" failed\"}\n\n#define TEST_CASE_ST(setup, teardown, testcase) \\\n\t\t{ setup, teardown, testcase, #testcase \" succeeded\", \\\n\t\t#testcase \" failed \"}\n\n#define TEST_CASES_END() { NULL, NULL, NULL, NULL, NULL }\n\nstruct unit_test_suite {\n\tconst char *suite_name;\n\tint (*setup)(void);\n\tint (*teardown)(void);\n\tstruct unit_test_case unit_test_cases[];\n};\n\nint unit_test_suite_runner(struct unit_test_suite *suite);\n\n#define RECURSIVE_ENV_VAR \"RTE_TEST_RECURSIVE\"\n\n#include \n#include \n\nextern const char *prgname;\n\nint commands_init(void);\n\nint test_pci(void);\nint test_pci_run;\n\nint test_mp_secondary(void);\n\nint test_ivshmem(void);\nint test_set_rxtx_conf(cmdline_fixed_string_t mode);\nint test_set_rxtx_anchor(cmdline_fixed_string_t type);\nint test_set_rxtx_sc(cmdline_fixed_string_t type);\n\ntypedef int (test_callback)(void);\nTAILQ_HEAD(test_commands_list, test_command);\nstruct test_command {\n\tTAILQ_ENTRY(test_command) next;\n\tconst char *command;\n\ttest_callback *callback;\n};\n\nvoid add_test_command(struct test_command *t);\n\n#define REGISTER_TEST_COMMAND(t) \\\nstatic void __attribute__((used)) testfn_##t(void);\\\nvoid __attribute__((constructor, used)) testfn_##t(void)\\\n{\\\n\tadd_test_command(&t);\\\n}\n\n#endif\n" }, { "path": "app/test/test_acl.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \"test.h\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test_acl.h\"\n\n#define LEN RTE_ACL_MAX_CATEGORIES\n\nRTE_ACL_RULE_DEF(acl_ipv4vlan_rule, RTE_ACL_IPV4VLAN_NUM_FIELDS);\n\nstruct rte_acl_param acl_param = {\n\t.name = \"acl_ctx\",\n\t.socket_id = SOCKET_ID_ANY,\n\t.rule_size = RTE_ACL_IPV4VLAN_RULE_SZ,\n\t.max_rule_num = 0x30000,\n};\n\nstruct rte_acl_ipv4vlan_rule acl_rule = {\n\t\t.data = { .priority = 1, .category_mask = 0xff },\n\t\t.src_port_low = 0,\n\t\t.src_port_high = UINT16_MAX,\n\t\t.dst_port_low = 0,\n\t\t.dst_port_high = UINT16_MAX,\n};\n\nconst uint32_t ipv4_7tuple_layout[RTE_ACL_IPV4VLAN_NUM] = {\n\toffsetof(struct ipv4_7tuple, proto),\n\toffsetof(struct ipv4_7tuple, vlan),\n\toffsetof(struct ipv4_7tuple, ip_src),\n\toffsetof(struct ipv4_7tuple, ip_dst),\n\toffsetof(struct ipv4_7tuple, port_src),\n};\n\n\n/* byteswap to cpu or network order */\nstatic void\nbswap_test_data(struct ipv4_7tuple *data, int len, int to_be)\n{\n\tint i;\n\n\tfor (i = 0; i < len; i++) {\n\n\t\tif (to_be) {\n\t\t\t/* swap all bytes so that they are in network order */\n\t\t\tdata[i].ip_dst = rte_cpu_to_be_32(data[i].ip_dst);\n\t\t\tdata[i].ip_src = rte_cpu_to_be_32(data[i].ip_src);\n\t\t\tdata[i].port_dst = rte_cpu_to_be_16(data[i].port_dst);\n\t\t\tdata[i].port_src = rte_cpu_to_be_16(data[i].port_src);\n\t\t\tdata[i].vlan = rte_cpu_to_be_16(data[i].vlan);\n\t\t\tdata[i].domain = rte_cpu_to_be_16(data[i].domain);\n\t\t} else {\n\t\t\tdata[i].ip_dst = rte_be_to_cpu_32(data[i].ip_dst);\n\t\t\tdata[i].ip_src = rte_be_to_cpu_32(data[i].ip_src);\n\t\t\tdata[i].port_dst = rte_be_to_cpu_16(data[i].port_dst);\n\t\t\tdata[i].port_src = rte_be_to_cpu_16(data[i].port_src);\n\t\t\tdata[i].vlan = rte_be_to_cpu_16(data[i].vlan);\n\t\t\tdata[i].domain = rte_be_to_cpu_16(data[i].domain);\n\t\t}\n\t}\n}\n\n/*\n * Test scalar and SSE ACL lookup.\n */\nstatic int\ntest_classify_run(struct rte_acl_ctx *acx)\n{\n\tint ret, i;\n\tuint32_t result, count;\n\tuint32_t results[RTE_DIM(acl_test_data) * RTE_ACL_MAX_CATEGORIES];\n\tconst uint8_t *data[RTE_DIM(acl_test_data)];\n\n\t/* swap all bytes in the data to network order */\n\tbswap_test_data(acl_test_data, RTE_DIM(acl_test_data), 1);\n\n\t/* store pointers to test data */\n\tfor (i = 0; i < (int) RTE_DIM(acl_test_data); i++)\n\t\tdata[i] = (uint8_t *)&acl_test_data[i];\n\n\t/**\n\t * these will run quite a few times, it's necessary to test code paths\n\t * from num=0 to num>8\n\t */\n\tfor (count = 0; count <= RTE_DIM(acl_test_data); count++) {\n\t\tret = rte_acl_classify(acx, data, results,\n\t\t\t\tcount, RTE_ACL_MAX_CATEGORIES);\n\t\tif (ret != 0) {\n\t\t\tprintf(\"Line %i: SSE classify failed!\\n\", __LINE__);\n\t\t\tgoto err;\n\t\t}\n\n\t\t/* check if we allow everything we should allow */\n\t\tfor (i = 0; i < (int) count; i++) {\n\t\t\tresult =\n\t\t\t\tresults[i * RTE_ACL_MAX_CATEGORIES + ACL_ALLOW];\n\t\t\tif (result != acl_test_data[i].allow) {\n\t\t\t\tprintf(\"Line %i: Error in allow results at %i \"\n\t\t\t\t\t\"(expected %\"PRIu32\" got %\"PRIu32\")!\\n\",\n\t\t\t\t\t__LINE__, i, acl_test_data[i].allow,\n\t\t\t\t\tresult);\n\t\t\t\tret = -EINVAL;\n\t\t\t\tgoto err;\n\t\t\t}\n\t\t}\n\n\t\t/* check if we deny everything we should deny */\n\t\tfor (i = 0; i < (int) count; i++) {\n\t\t\tresult = results[i * RTE_ACL_MAX_CATEGORIES + ACL_DENY];\n\t\t\tif (result != acl_test_data[i].deny) {\n\t\t\t\tprintf(\"Line %i: Error in deny results at %i \"\n\t\t\t\t\t\"(expected %\"PRIu32\" got %\"PRIu32\")!\\n\",\n\t\t\t\t\t__LINE__, i, acl_test_data[i].deny,\n\t\t\t\t\tresult);\n\t\t\t\tret = -EINVAL;\n\t\t\t\tgoto err;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* make a quick check for scalar */\n\tret = rte_acl_classify_alg(acx, data, results,\n\t\t\tRTE_DIM(acl_test_data), RTE_ACL_MAX_CATEGORIES,\n\t\t\tRTE_ACL_CLASSIFY_SCALAR);\n\tif (ret != 0) {\n\t\tprintf(\"Line %i: scalar classify failed!\\n\", __LINE__);\n\t\tgoto err;\n\t}\n\n\t/* check if we allow everything we should allow */\n\tfor (i = 0; i < (int) RTE_DIM(acl_test_data); i++) {\n\t\tresult = results[i * RTE_ACL_MAX_CATEGORIES + ACL_ALLOW];\n\t\tif (result != acl_test_data[i].allow) {\n\t\t\tprintf(\"Line %i: Error in allow results at %i \"\n\t\t\t\t\t\"(expected %\"PRIu32\" got %\"PRIu32\")!\\n\",\n\t\t\t\t\t__LINE__, i, acl_test_data[i].allow,\n\t\t\t\t\tresult);\n\t\t\tret = -EINVAL;\n\t\t\tgoto err;\n\t\t}\n\t}\n\n\t/* check if we deny everything we should deny */\n\tfor (i = 0; i < (int) RTE_DIM(acl_test_data); i++) {\n\t\tresult = results[i * RTE_ACL_MAX_CATEGORIES + ACL_DENY];\n\t\tif (result != acl_test_data[i].deny) {\n\t\t\tprintf(\"Line %i: Error in deny results at %i \"\n\t\t\t\t\t\"(expected %\"PRIu32\" got %\"PRIu32\")!\\n\",\n\t\t\t\t\t__LINE__, i, acl_test_data[i].deny,\n\t\t\t\t\tresult);\n\t\t\tret = -EINVAL;\n\t\t\tgoto err;\n\t\t}\n\t}\n\n\tret = 0;\n\nerr:\n\t/* swap data back to cpu order so that next time tests don't fail */\n\tbswap_test_data(acl_test_data, RTE_DIM(acl_test_data), 0);\n\treturn ret;\n}\n\nstatic int\ntest_classify_buid(struct rte_acl_ctx *acx,\n\tconst struct rte_acl_ipv4vlan_rule *rules, uint32_t num)\n{\n\tint ret;\n\n\t/* add rules to the context */\n\tret = rte_acl_ipv4vlan_add_rules(acx, rules, num);\n\tif (ret != 0) {\n\t\tprintf(\"Line %i: Adding rules to ACL context failed!\\n\",\n\t\t\t__LINE__);\n\t\treturn ret;\n\t}\n\n\t/* try building the context */\n\tret = rte_acl_ipv4vlan_build(acx, ipv4_7tuple_layout,\n\t\tRTE_ACL_MAX_CATEGORIES);\n\tif (ret != 0) {\n\t\tprintf(\"Line %i: Building ACL context failed!\\n\", __LINE__);\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\n#define\tTEST_CLASSIFY_ITER\t4\n\n/*\n * Test scalar and SSE ACL lookup.\n */\nstatic int\ntest_classify(void)\n{\n\tstruct rte_acl_ctx *acx;\n\tint i, ret;\n\n\tacx = rte_acl_create(&acl_param);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: Error creating ACL context!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\n\tret = 0;\n\tfor (i = 0; i != TEST_CLASSIFY_ITER; i++) {\n\n\t\tif ((i & 1) == 0)\n\t\t\trte_acl_reset(acx);\n\t\telse\n\t\t\trte_acl_reset_rules(acx);\n\n\t\tret = test_classify_buid(acx, acl_test_rules,\n\t\t\tRTE_DIM(acl_test_rules));\n\t\tif (ret != 0) {\n\t\t\tprintf(\"Line %i, iter: %d: \"\n\t\t\t\t\"Adding rules to ACL context failed!\\n\",\n\t\t\t\t__LINE__, i);\n\t\t\tbreak;\n\t\t}\n\n\t\tret = test_classify_run(acx);\n\t\tif (ret != 0) {\n\t\t\tprintf(\"Line %i, iter: %d: %s failed!\\n\",\n\t\t\t\t__LINE__, i, __func__);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* reset rules and make sure that classify still works ok. */\n\t\trte_acl_reset_rules(acx);\n\t\tret = test_classify_run(acx);\n\t\tif (ret != 0) {\n\t\t\tprintf(\"Line %i, iter: %d: %s failed!\\n\",\n\t\t\t\t__LINE__, i, __func__);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\trte_acl_free(acx);\n\treturn ret;\n}\n\nstatic int\ntest_build_ports_range(void)\n{\n\tstatic const struct rte_acl_ipv4vlan_rule test_rules[] = {\n\t\t{\n\t\t\t/* match all packets. */\n\t\t\t.data = {\n\t\t\t\t.userdata = 1,\n\t\t\t\t.category_mask = ACL_ALLOW_MASK,\n\t\t\t\t.priority = 101,\n\t\t\t},\n\t\t\t.src_port_low = 0,\n\t\t\t.src_port_high = UINT16_MAX,\n\t\t\t.dst_port_low = 0,\n\t\t\t.dst_port_high = UINT16_MAX,\n\t\t},\n\t\t{\n\t\t\t/* match all packets with dst ports [54-65280]. */\n\t\t\t.data = {\n\t\t\t\t.userdata = 2,\n\t\t\t\t.category_mask = ACL_ALLOW_MASK,\n\t\t\t\t.priority = 102,\n\t\t\t},\n\t\t\t.src_port_low = 0,\n\t\t\t.src_port_high = UINT16_MAX,\n\t\t\t.dst_port_low = 54,\n\t\t\t.dst_port_high = 65280,\n\t\t},\n\t\t{\n\t\t\t/* match all packets with dst ports [0-52]. */\n\t\t\t.data = {\n\t\t\t\t.userdata = 3,\n\t\t\t\t.category_mask = ACL_ALLOW_MASK,\n\t\t\t\t.priority = 103,\n\t\t\t},\n\t\t\t.src_port_low = 0,\n\t\t\t.src_port_high = UINT16_MAX,\n\t\t\t.dst_port_low = 0,\n\t\t\t.dst_port_high = 52,\n\t\t},\n\t\t{\n\t\t\t/* match all packets with dst ports [53]. */\n\t\t\t.data = {\n\t\t\t\t.userdata = 4,\n\t\t\t\t.category_mask = ACL_ALLOW_MASK,\n\t\t\t\t.priority = 99,\n\t\t\t},\n\t\t\t.src_port_low = 0,\n\t\t\t.src_port_high = UINT16_MAX,\n\t\t\t.dst_port_low = 53,\n\t\t\t.dst_port_high = 53,\n\t\t},\n\t\t{\n\t\t\t/* match all packets with dst ports [65279-65535]. */\n\t\t\t.data = {\n\t\t\t\t.userdata = 5,\n\t\t\t\t.category_mask = ACL_ALLOW_MASK,\n\t\t\t\t.priority = 98,\n\t\t\t},\n\t\t\t.src_port_low = 0,\n\t\t\t.src_port_high = UINT16_MAX,\n\t\t\t.dst_port_low = 65279,\n\t\t\t.dst_port_high = UINT16_MAX,\n\t\t},\n\t};\n\n\tstatic struct ipv4_7tuple test_data[] = {\n\t\t{\n\t\t\t.proto = 6,\n\t\t\t.ip_src = IPv4(10, 1, 1, 1),\n\t\t\t.ip_dst = IPv4(192, 168, 0, 33),\n\t\t\t.port_dst = 53,\n\t\t\t.allow = 1,\n\t\t},\n\t\t{\n\t\t\t.proto = 6,\n\t\t\t.ip_src = IPv4(127, 84, 33, 1),\n\t\t\t.ip_dst = IPv4(1, 2, 3, 4),\n\t\t\t.port_dst = 65281,\n\t\t\t.allow = 1,\n\t\t},\n\t};\n\n\tstruct rte_acl_ctx *acx;\n\tint32_t ret, i, j;\n\tuint32_t results[RTE_DIM(test_data)];\n\tconst uint8_t *data[RTE_DIM(test_data)];\n\n\tacx = rte_acl_create(&acl_param);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: Error creating ACL context!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\n\t/* swap all bytes in the data to network order */\n\tbswap_test_data(test_data, RTE_DIM(test_data), 1);\n\n\t/* store pointers to test data */\n\tfor (i = 0; i != RTE_DIM(test_data); i++)\n\t\tdata[i] = (uint8_t *)&test_data[i];\n\n\tfor (i = 0; i != RTE_DIM(test_rules); i++) {\n\t\trte_acl_reset(acx);\n\t\tret = test_classify_buid(acx, test_rules, i + 1);\n\t\tif (ret != 0) {\n\t\t\tprintf(\"Line %i, iter: %d: \"\n\t\t\t\t\"Adding rules to ACL context failed!\\n\",\n\t\t\t\t__LINE__, i);\n\t\t\tbreak;\n\t\t}\n\t\tret = rte_acl_classify(acx, data, results,\n\t\t\tRTE_DIM(data), 1);\n\t\tif (ret != 0) {\n\t\t\tprintf(\"Line %i, iter: %d: classify failed!\\n\",\n\t\t\t\t__LINE__, i);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* check results */\n\t\tfor (j = 0; j != RTE_DIM(results); j++) {\n\t\t\tif (results[j] != test_data[j].allow) {\n\t\t\t\tprintf(\"Line %i: Error in allow results at %i \"\n\t\t\t\t\t\"(expected %\"PRIu32\" got %\"PRIu32\")!\\n\",\n\t\t\t\t\t__LINE__, j, test_data[j].allow,\n\t\t\t\t\tresults[j]);\n\t\t\t\tret = -EINVAL;\n\t\t\t}\n\t\t}\n\t}\n\n\tbswap_test_data(test_data, RTE_DIM(test_data), 0);\n\n\trte_acl_free(acx);\n\treturn ret;\n}\n\nstatic void\nconvert_rule(const struct rte_acl_ipv4vlan_rule *ri,\n\tstruct acl_ipv4vlan_rule *ro)\n{\n\tro->data = ri->data;\n\n\tro->field[RTE_ACL_IPV4VLAN_PROTO_FIELD].value.u8 = ri->proto;\n\tro->field[RTE_ACL_IPV4VLAN_VLAN1_FIELD].value.u16 = ri->vlan;\n\tro->field[RTE_ACL_IPV4VLAN_VLAN2_FIELD].value.u16 = ri->domain;\n\tro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].value.u32 = ri->src_addr;\n\tro->field[RTE_ACL_IPV4VLAN_DST_FIELD].value.u32 = ri->dst_addr;\n\tro->field[RTE_ACL_IPV4VLAN_SRCP_FIELD].value.u16 = ri->src_port_low;\n\tro->field[RTE_ACL_IPV4VLAN_DSTP_FIELD].value.u16 = ri->dst_port_low;\n\n\tro->field[RTE_ACL_IPV4VLAN_PROTO_FIELD].mask_range.u8 = ri->proto_mask;\n\tro->field[RTE_ACL_IPV4VLAN_VLAN1_FIELD].mask_range.u16 = ri->vlan_mask;\n\tro->field[RTE_ACL_IPV4VLAN_VLAN2_FIELD].mask_range.u16 =\n\t\tri->domain_mask;\n\tro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].mask_range.u32 =\n\t\tri->src_mask_len;\n\tro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32 = ri->dst_mask_len;\n\tro->field[RTE_ACL_IPV4VLAN_SRCP_FIELD].mask_range.u16 =\n\t\tri->src_port_high;\n\tro->field[RTE_ACL_IPV4VLAN_DSTP_FIELD].mask_range.u16 =\n\t\tri->dst_port_high;\n}\n\n/*\n * Convert IPV4 source and destination from RTE_ACL_FIELD_TYPE_MASK to\n * RTE_ACL_FIELD_TYPE_BITMASK.\n */\nstatic void\nconvert_rule_1(const struct rte_acl_ipv4vlan_rule *ri,\n\tstruct acl_ipv4vlan_rule *ro)\n{\n\tuint32_t v;\n\n\tconvert_rule(ri, ro);\n\tv = ro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].mask_range.u32;\n\tro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].mask_range.u32 =\n\t\tRTE_ACL_MASKLEN_TO_BITMASK(v, sizeof(v));\n\tv = ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32;\n\tro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32 =\n\t\tRTE_ACL_MASKLEN_TO_BITMASK(v, sizeof(v));\n}\n\n/*\n * Convert IPV4 source and destination from RTE_ACL_FIELD_TYPE_MASK to\n * RTE_ACL_FIELD_TYPE_RANGE.\n */\nstatic void\nconvert_rule_2(const struct rte_acl_ipv4vlan_rule *ri,\n\tstruct acl_ipv4vlan_rule *ro)\n{\n\tuint32_t hi, lo, mask;\n\n\tconvert_rule(ri, ro);\n\n\tmask = ro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].mask_range.u32;\n\tmask = RTE_ACL_MASKLEN_TO_BITMASK(mask, sizeof(mask));\n\tlo = ro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].value.u32 & mask;\n\thi = lo + ~mask;\n\tro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].value.u32 = lo;\n\tro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].mask_range.u32 = hi;\n\n\tmask = ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32;\n\tmask = RTE_ACL_MASKLEN_TO_BITMASK(mask, sizeof(mask));\n\tlo = ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].value.u32 & mask;\n\thi = lo + ~mask;\n\tro->field[RTE_ACL_IPV4VLAN_DST_FIELD].value.u32 = lo;\n\tro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32 = hi;\n}\n\n/*\n * Convert rte_acl_ipv4vlan_rule: swap VLAN and PORTS rule fields.\n */\nstatic void\nconvert_rule_3(const struct rte_acl_ipv4vlan_rule *ri,\n\tstruct acl_ipv4vlan_rule *ro)\n{\n\tstruct rte_acl_field t1, t2;\n\n\tconvert_rule(ri, ro);\n\n\tt1 = ro->field[RTE_ACL_IPV4VLAN_VLAN1_FIELD];\n\tt2 = ro->field[RTE_ACL_IPV4VLAN_VLAN2_FIELD];\n\n\tro->field[RTE_ACL_IPV4VLAN_VLAN1_FIELD] =\n\t\tro->field[RTE_ACL_IPV4VLAN_SRCP_FIELD];\n\tro->field[RTE_ACL_IPV4VLAN_VLAN2_FIELD] =\n\t\tro->field[RTE_ACL_IPV4VLAN_DSTP_FIELD];\n\n\tro->field[RTE_ACL_IPV4VLAN_SRCP_FIELD] = t1;\n\tro->field[RTE_ACL_IPV4VLAN_DSTP_FIELD] = t2;\n}\n\n/*\n * Convert rte_acl_ipv4vlan_rule: swap SRC and DST IPv4 address rules.\n */\nstatic void\nconvert_rule_4(const struct rte_acl_ipv4vlan_rule *ri,\n\tstruct acl_ipv4vlan_rule *ro)\n{\n\tstruct rte_acl_field t;\n\n\tconvert_rule(ri, ro);\n\n\tt = ro->field[RTE_ACL_IPV4VLAN_SRC_FIELD];\n\tro->field[RTE_ACL_IPV4VLAN_SRC_FIELD] =\n\t\tro->field[RTE_ACL_IPV4VLAN_DST_FIELD];\n\n\tro->field[RTE_ACL_IPV4VLAN_DST_FIELD] = t;\n}\n\nstatic void\nipv4vlan_config(struct rte_acl_config *cfg,\n\tconst uint32_t layout[RTE_ACL_IPV4VLAN_NUM],\n\tuint32_t num_categories)\n{\n\tstatic const struct rte_acl_field_def\n\t\tipv4_defs[RTE_ACL_IPV4VLAN_NUM_FIELDS] = {\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t\t.size = sizeof(uint8_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_PROTO_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_PROTO,\n\t\t},\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t\t.size = sizeof(uint16_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_VLAN1_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_VLAN,\n\t\t},\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t\t.size = sizeof(uint16_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_VLAN2_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_VLAN,\n\t\t},\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t\t.size = sizeof(uint32_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_SRC_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_SRC,\n\t\t},\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t\t.size = sizeof(uint32_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_DST_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_DST,\n\t\t},\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t\t.size = sizeof(uint16_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_SRCP_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_PORTS,\n\t\t},\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t\t.size = sizeof(uint16_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_DSTP_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_PORTS,\n\t\t},\n\t};\n\n\tmemcpy(&cfg->defs, ipv4_defs, sizeof(ipv4_defs));\n\tcfg->num_fields = RTE_DIM(ipv4_defs);\n\n\tcfg->defs[RTE_ACL_IPV4VLAN_PROTO_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_PROTO];\n\tcfg->defs[RTE_ACL_IPV4VLAN_VLAN1_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_VLAN];\n\tcfg->defs[RTE_ACL_IPV4VLAN_VLAN2_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_VLAN] +\n\t\tcfg->defs[RTE_ACL_IPV4VLAN_VLAN1_FIELD].size;\n\tcfg->defs[RTE_ACL_IPV4VLAN_SRC_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_SRC];\n\tcfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_DST];\n\tcfg->defs[RTE_ACL_IPV4VLAN_SRCP_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_PORTS];\n\tcfg->defs[RTE_ACL_IPV4VLAN_DSTP_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_PORTS] +\n\t\tcfg->defs[RTE_ACL_IPV4VLAN_SRCP_FIELD].size;\n\n\tcfg->num_categories = num_categories;\n}\n\nstatic int\nconvert_rules(struct rte_acl_ctx *acx,\n\tvoid (*convert)(const struct rte_acl_ipv4vlan_rule *,\n\tstruct acl_ipv4vlan_rule *),\n\tconst struct rte_acl_ipv4vlan_rule *rules, uint32_t num)\n{\n\tint32_t rc;\n\tuint32_t i;\n\tstruct acl_ipv4vlan_rule r;\n\n\tfor (i = 0; i != num; i++) {\n\t\tconvert(rules + i, &r);\n\t\trc = rte_acl_add_rules(acx, (struct rte_acl_rule *)&r, 1);\n\t\tif (rc != 0) {\n\t\t\tprintf(\"Line %i: Adding rule %u to ACL context \"\n\t\t\t\t\"failed with error code: %d\\n\",\n\t\t\t__LINE__, i, rc);\n\t\t\treturn rc;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic void\nconvert_config(struct rte_acl_config *cfg)\n{\n\tipv4vlan_config(cfg, ipv4_7tuple_layout, RTE_ACL_MAX_CATEGORIES);\n}\n\n/*\n * Convert rte_acl_ipv4vlan_rule to use RTE_ACL_FIELD_TYPE_BITMASK.\n */\nstatic void\nconvert_config_1(struct rte_acl_config *cfg)\n{\n\tipv4vlan_config(cfg, ipv4_7tuple_layout, RTE_ACL_MAX_CATEGORIES);\n\tcfg->defs[RTE_ACL_IPV4VLAN_SRC_FIELD].type = RTE_ACL_FIELD_TYPE_BITMASK;\n\tcfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].type = RTE_ACL_FIELD_TYPE_BITMASK;\n}\n\n/*\n * Convert rte_acl_ipv4vlan_rule to use RTE_ACL_FIELD_TYPE_RANGE.\n */\nstatic void\nconvert_config_2(struct rte_acl_config *cfg)\n{\n\tipv4vlan_config(cfg, ipv4_7tuple_layout, RTE_ACL_MAX_CATEGORIES);\n\tcfg->defs[RTE_ACL_IPV4VLAN_SRC_FIELD].type = RTE_ACL_FIELD_TYPE_RANGE;\n\tcfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].type = RTE_ACL_FIELD_TYPE_RANGE;\n}\n\n/*\n * Convert rte_acl_ipv4vlan_rule: swap VLAN and PORTS rule definitions.\n */\nstatic void\nconvert_config_3(struct rte_acl_config *cfg)\n{\n\tstruct rte_acl_field_def t1, t2;\n\n\tipv4vlan_config(cfg, ipv4_7tuple_layout, RTE_ACL_MAX_CATEGORIES);\n\n\tt1 = cfg->defs[RTE_ACL_IPV4VLAN_VLAN1_FIELD];\n\tt2 = cfg->defs[RTE_ACL_IPV4VLAN_VLAN2_FIELD];\n\n\t/* swap VLAN1 and SRCP rule definition. */\n\tcfg->defs[RTE_ACL_IPV4VLAN_VLAN1_FIELD] =\n\t\tcfg->defs[RTE_ACL_IPV4VLAN_SRCP_FIELD];\n\tcfg->defs[RTE_ACL_IPV4VLAN_VLAN1_FIELD].field_index = t1.field_index;\n\tcfg->defs[RTE_ACL_IPV4VLAN_VLAN1_FIELD].input_index = t1.input_index;\n\n\t/* swap VLAN2 and DSTP rule definition. */\n\tcfg->defs[RTE_ACL_IPV4VLAN_VLAN2_FIELD] =\n\t\tcfg->defs[RTE_ACL_IPV4VLAN_DSTP_FIELD];\n\tcfg->defs[RTE_ACL_IPV4VLAN_VLAN2_FIELD].field_index = t2.field_index;\n\tcfg->defs[RTE_ACL_IPV4VLAN_VLAN2_FIELD].input_index = t2.input_index;\n\n\tcfg->defs[RTE_ACL_IPV4VLAN_SRCP_FIELD].type = t1.type;\n\tcfg->defs[RTE_ACL_IPV4VLAN_SRCP_FIELD].size = t1.size;\n\tcfg->defs[RTE_ACL_IPV4VLAN_SRCP_FIELD].offset = t1.offset;\n\n\tcfg->defs[RTE_ACL_IPV4VLAN_DSTP_FIELD].type = t2.type;\n\tcfg->defs[RTE_ACL_IPV4VLAN_DSTP_FIELD].size = t2.size;\n\tcfg->defs[RTE_ACL_IPV4VLAN_DSTP_FIELD].offset = t2.offset;\n}\n\n/*\n * Convert rte_acl_ipv4vlan_rule: swap SRC and DST ip address rule definitions.\n */\nstatic void\nconvert_config_4(struct rte_acl_config *cfg)\n{\n\tstruct rte_acl_field_def t;\n\n\tipv4vlan_config(cfg, ipv4_7tuple_layout, RTE_ACL_MAX_CATEGORIES);\n\n\tt = cfg->defs[RTE_ACL_IPV4VLAN_SRC_FIELD];\n\n\tcfg->defs[RTE_ACL_IPV4VLAN_SRC_FIELD] =\n\t\tcfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD];\n\tcfg->defs[RTE_ACL_IPV4VLAN_SRC_FIELD].field_index = t.field_index;\n\tcfg->defs[RTE_ACL_IPV4VLAN_SRC_FIELD].input_index = t.input_index;\n\n\tcfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].type = t.type;\n\tcfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].size = t.size;\n\tcfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].offset = t.offset;\n}\n\n\nstatic int\nbuild_convert_rules(struct rte_acl_ctx *acx,\n\tvoid (*config)(struct rte_acl_config *),\n\tsize_t max_size)\n{\n\tstruct rte_acl_config cfg;\n\n\tmemset(&cfg, 0, sizeof(cfg));\n\tconfig(&cfg);\n\tcfg.max_size = max_size;\n\treturn rte_acl_build(acx, &cfg);\n}\n\nstatic int\ntest_convert_rules(const char *desc,\n\tvoid (*config)(struct rte_acl_config *),\n\tvoid (*convert)(const struct rte_acl_ipv4vlan_rule *,\n\tstruct acl_ipv4vlan_rule *))\n{\n\tstruct rte_acl_ctx *acx;\n\tint32_t rc;\n\tuint32_t i;\n\tstatic const size_t mem_sizes[] = {0, -1};\n\n\tprintf(\"running %s(%s)\\n\", __func__, desc);\n\n\tacx = rte_acl_create(&acl_param);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: Error creating ACL context!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\n\trc = convert_rules(acx, convert, acl_test_rules,\n\t\tRTE_DIM(acl_test_rules));\n\tif (rc != 0)\n\t\tprintf(\"Line %i: Error converting ACL rules!\\n\", __LINE__);\n\n\tfor (i = 0; rc == 0 && i != RTE_DIM(mem_sizes); i++) {\n\n\t\trc = build_convert_rules(acx, config, mem_sizes[i]);\n\t\tif (rc != 0) {\n\t\t\tprintf(\"Line %i: Error @ build_convert_rules(%zu)!\\n\",\n\t\t\t\t__LINE__, mem_sizes[i]);\n\t\t\tbreak;\n\t\t}\n\n\t\trc = test_classify_run(acx);\n\t\tif (rc != 0)\n\t\t\tprintf(\"%s failed at line %i, max_size=%zu\\n\",\n\t\t\t\t__func__, __LINE__, mem_sizes[i]);\n\t}\n\n\trte_acl_free(acx);\n\treturn rc;\n}\n\nstatic int\ntest_convert(void)\n{\n\tstatic const struct {\n\t\tconst char *desc;\n\t\tvoid (*config)(struct rte_acl_config *);\n\t\tvoid (*convert)(const struct rte_acl_ipv4vlan_rule *,\n\t\t\tstruct acl_ipv4vlan_rule *);\n\t} convert_param[] = {\n\t\t{\n\t\t\t\"acl_ipv4vlan_tuple\",\n\t\t\tconvert_config,\n\t\t\tconvert_rule,\n\t\t},\n\t\t{\n\t\t\t\"acl_ipv4vlan_tuple, RTE_ACL_FIELD_TYPE_BITMASK type \"\n\t\t\t\"for IPv4\",\n\t\t\tconvert_config_1,\n\t\t\tconvert_rule_1,\n\t\t},\n\t\t{\n\t\t\t\"acl_ipv4vlan_tuple, RTE_ACL_FIELD_TYPE_RANGE type \"\n\t\t\t\"for IPv4\",\n\t\t\tconvert_config_2,\n\t\t\tconvert_rule_2,\n\t\t},\n\t\t{\n\t\t\t\"acl_ipv4vlan_tuple: swap VLAN and PORTs order\",\n\t\t\tconvert_config_3,\n\t\t\tconvert_rule_3,\n\t\t},\n\t\t{\n\t\t\t\"acl_ipv4vlan_tuple: swap SRC and DST IPv4 order\",\n\t\t\tconvert_config_4,\n\t\t\tconvert_rule_4,\n\t\t},\n\t};\n\n\tuint32_t i;\n\tint32_t rc;\n\n\tfor (i = 0; i != RTE_DIM(convert_param); i++) {\n\t\trc = test_convert_rules(convert_param[i].desc,\n\t\t\tconvert_param[i].config,\n\t\t\tconvert_param[i].convert);\n\t\tif (rc != 0) {\n\t\t\tprintf(\"%s for test-case: %s failed, error code: %d;\\n\",\n\t\t\t\t__func__, convert_param[i].desc, rc);\n\t\t\treturn rc;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/*\n * Test wrong layout behavior\n * This test supplies the ACL context with invalid layout, which results in\n * ACL matching the wrong stuff. However, it should match the wrong stuff\n * the right way. We switch around source and destination addresses,\n * source and destination ports, and protocol will point to first byte of\n * destination port.\n */\nstatic int\ntest_invalid_layout(void)\n{\n\tstruct rte_acl_ctx *acx;\n\tint ret, i;\n\n\tuint32_t results[RTE_DIM(invalid_layout_data)];\n\tconst uint8_t *data[RTE_DIM(invalid_layout_data)];\n\n\tconst uint32_t layout[RTE_ACL_IPV4VLAN_NUM] = {\n\t\t\t/* proto points to destination port's first byte */\n\t\t\toffsetof(struct ipv4_7tuple, port_dst),\n\n\t\t\t0, /* VLAN not used */\n\n\t\t\t/* src and dst addresses are swapped */\n\t\t\toffsetof(struct ipv4_7tuple, ip_dst),\n\t\t\toffsetof(struct ipv4_7tuple, ip_src),\n\n\t\t\t/*\n\t\t\t * we can't swap ports here, so we will swap\n\t\t\t * them in the data\n\t\t\t */\n\t\t\toffsetof(struct ipv4_7tuple, port_src),\n\t};\n\n\tacx = rte_acl_create(&acl_param);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: Error creating ACL context!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\n\t/* putting a lot of rules into the context results in greater\n\t * coverage numbers. it doesn't matter if they are identical */\n\tfor (i = 0; i < 1000; i++) {\n\t\t/* add rules to the context */\n\t\tret = rte_acl_ipv4vlan_add_rules(acx, invalid_layout_rules,\n\t\t\t\tRTE_DIM(invalid_layout_rules));\n\t\tif (ret != 0) {\n\t\t\tprintf(\"Line %i: Adding rules to ACL context failed!\\n\",\n\t\t\t\t__LINE__);\n\t\t\trte_acl_free(acx);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* try building the context */\n\tret = rte_acl_ipv4vlan_build(acx, layout, 1);\n\tif (ret != 0) {\n\t\tprintf(\"Line %i: Building ACL context failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* swap all bytes in the data to network order */\n\tbswap_test_data(invalid_layout_data, RTE_DIM(invalid_layout_data), 1);\n\n\t/* prepare data */\n\tfor (i = 0; i < (int) RTE_DIM(invalid_layout_data); i++) {\n\t\tdata[i] = (uint8_t *)&invalid_layout_data[i];\n\t}\n\n\t/* classify tuples */\n\tret = rte_acl_classify_alg(acx, data, results,\n\t\t\tRTE_DIM(results), 1, RTE_ACL_CLASSIFY_SCALAR);\n\tif (ret != 0) {\n\t\tprintf(\"Line %i: SSE classify failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < (int) RTE_DIM(results); i++) {\n\t\tif (results[i] != invalid_layout_data[i].allow) {\n\t\t\tprintf(\"Line %i: Wrong results at %i \"\n\t\t\t\t\"(result=%u, should be %u)!\\n\",\n\t\t\t\t__LINE__, i, results[i],\n\t\t\t\tinvalid_layout_data[i].allow);\n\t\t\tgoto err;\n\t\t}\n\t}\n\n\t/* classify tuples (scalar) */\n\tret = rte_acl_classify_alg(acx, data, results, RTE_DIM(results), 1,\n\t\tRTE_ACL_CLASSIFY_SCALAR);\n\n\tif (ret != 0) {\n\t\tprintf(\"Line %i: Scalar classify failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < (int) RTE_DIM(results); i++) {\n\t\tif (results[i] != invalid_layout_data[i].allow) {\n\t\t\tprintf(\"Line %i: Wrong results at %i \"\n\t\t\t\t\"(result=%u, should be %u)!\\n\",\n\t\t\t\t__LINE__, i, results[i],\n\t\t\t\tinvalid_layout_data[i].allow);\n\t\t\tgoto err;\n\t\t}\n\t}\n\n\trte_acl_free(acx);\n\n\t/* swap data back to cpu order so that next time tests don't fail */\n\tbswap_test_data(invalid_layout_data, RTE_DIM(invalid_layout_data), 0);\n\n\treturn 0;\nerr:\n\n\t/* swap data back to cpu order so that next time tests don't fail */\n\tbswap_test_data(invalid_layout_data, RTE_DIM(invalid_layout_data), 0);\n\n\trte_acl_free(acx);\n\n\treturn -1;\n}\n\n/*\n * Test creating and finding ACL contexts, and adding rules\n */\nstatic int\ntest_create_find_add(void)\n{\n\tstruct rte_acl_param param;\n\tstruct rte_acl_ctx *acx, *acx2, *tmp;\n\tstruct rte_acl_ipv4vlan_rule rules[LEN];\n\n\tconst uint32_t layout[RTE_ACL_IPV4VLAN_NUM] = {0};\n\n\tconst char *acx_name = \"acx\";\n\tconst char *acx2_name = \"acx2\";\n\tint i, ret;\n\n\t/* create two contexts */\n\tmemcpy(¶m, &acl_param, sizeof(param));\n\tparam.max_rule_num = 2;\n\n\tparam.name = acx_name;\n\tacx = rte_acl_create(¶m);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: Error creating %s!\\n\", __LINE__, acx_name);\n\t\treturn -1;\n\t}\n\n\tparam.name = acx2_name;\n\tacx2 = rte_acl_create(¶m);\n\tif (acx2 == NULL || acx2 == acx) {\n\t\tprintf(\"Line %i: Error creating %s!\\n\", __LINE__, acx2_name);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* try to create third one, with an existing name */\n\tparam.name = acx_name;\n\ttmp = rte_acl_create(¶m);\n\tif (tmp != acx) {\n\t\tprintf(\"Line %i: Creating context with existing name \"\n\t\t\t\"test failed!\\n\",\n\t\t\t__LINE__);\n\t\tif (tmp)\n\t\t\trte_acl_free(tmp);\n\t\tgoto err;\n\t}\n\n\tparam.name = acx2_name;\n\ttmp = rte_acl_create(¶m);\n\tif (tmp != acx2) {\n\t\tprintf(\"Line %i: Creating context with existing \"\n\t\t\t\"name test 2 failed!\\n\",\n\t\t\t__LINE__);\n\t\tif (tmp)\n\t\t\trte_acl_free(tmp);\n\t\tgoto err;\n\t}\n\n\t/* try to find existing ACL contexts */\n\ttmp = rte_acl_find_existing(acx_name);\n\tif (tmp != acx) {\n\t\tprintf(\"Line %i: Finding %s failed!\\n\", __LINE__, acx_name);\n\t\tif (tmp)\n\t\t\trte_acl_free(tmp);\n\t\tgoto err;\n\t}\n\n\ttmp = rte_acl_find_existing(acx2_name);\n\tif (tmp != acx2) {\n\t\tprintf(\"Line %i: Finding %s failed!\\n\", __LINE__, acx2_name);\n\t\tif (tmp)\n\t\t\trte_acl_free(tmp);\n\t\tgoto err;\n\t}\n\n\t/* try to find non-existing context */\n\ttmp = rte_acl_find_existing(\"invalid\");\n\tif (tmp != NULL) {\n\t\tprintf(\"Line %i: Non-existent ACL context found!\\n\", __LINE__);\n\t\tgoto err;\n\t}\n\n\t/* free context */\n\trte_acl_free(acx);\n\n\n\t/* create valid (but severely limited) acx */\n\tmemcpy(¶m, &acl_param, sizeof(param));\n\tparam.max_rule_num = LEN;\n\n\tacx = rte_acl_create(¶m);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: Error creating %s!\\n\", __LINE__, param.name);\n\t\tgoto err;\n\t}\n\n\t/* create dummy acl */\n\tfor (i = 0; i < LEN; i++) {\n\t\tmemcpy(&rules[i], &acl_rule,\n\t\t\tsizeof(struct rte_acl_ipv4vlan_rule));\n\t\t/* skip zero */\n\t\trules[i].data.userdata = i + 1;\n\t\t/* one rule per category */\n\t\trules[i].data.category_mask = 1 << i;\n\t}\n\n\t/* try filling up the context */\n\tret = rte_acl_ipv4vlan_add_rules(acx, rules, LEN);\n\tif (ret != 0) {\n\t\tprintf(\"Line %i: Adding %i rules to ACL context failed!\\n\",\n\t\t\t\t__LINE__, LEN);\n\t\tgoto err;\n\t}\n\n\t/* try adding to a (supposedly) full context */\n\tret = rte_acl_ipv4vlan_add_rules(acx, rules, 1);\n\tif (ret == 0) {\n\t\tprintf(\"Line %i: Adding rules to full ACL context should\"\n\t\t\t\t\"have failed!\\n\", __LINE__);\n\t\tgoto err;\n\t}\n\n\t/* try building the context */\n\tret = rte_acl_ipv4vlan_build(acx, layout, RTE_ACL_MAX_CATEGORIES);\n\tif (ret != 0) {\n\t\tprintf(\"Line %i: Building ACL context failed!\\n\", __LINE__);\n\t\tgoto err;\n\t}\n\n\trte_acl_free(acx);\n\trte_acl_free(acx2);\n\n\treturn 0;\nerr:\n\trte_acl_free(acx);\n\trte_acl_free(acx2);\n\treturn -1;\n}\n\n/*\n * test various invalid rules\n */\nstatic int\ntest_invalid_rules(void)\n{\n\tstruct rte_acl_ctx *acx;\n\tint ret;\n\n\tstruct rte_acl_ipv4vlan_rule rule;\n\n\tacx = rte_acl_create(&acl_param);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: Error creating ACL context!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\n\t/* test inverted high/low source and destination ports.\n\t * originally, there was a problem with memory consumption when using\n\t * such rules.\n\t */\n\t/* create dummy acl */\n\tmemcpy(&rule, &acl_rule, sizeof(struct rte_acl_ipv4vlan_rule));\n\trule.data.userdata = 1;\n\trule.dst_port_low = 0xfff0;\n\trule.dst_port_high = 0x0010;\n\n\t/* add rules to context and try to build it */\n\tret = rte_acl_ipv4vlan_add_rules(acx, &rule, 1);\n\tif (ret == 0) {\n\t\tprintf(\"Line %i: Adding rules to ACL context \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\tgoto err;\n\t}\n\n\trule.dst_port_low = 0x0;\n\trule.dst_port_high = 0xffff;\n\trule.src_port_low = 0xfff0;\n\trule.src_port_high = 0x0010;\n\n\t/* add rules to context and try to build it */\n\tret = rte_acl_ipv4vlan_add_rules(acx, &rule, 1);\n\tif (ret == 0) {\n\t\tprintf(\"Line %i: Adding rules to ACL context \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\tgoto err;\n\t}\n\n\trule.dst_port_low = 0x0;\n\trule.dst_port_high = 0xffff;\n\trule.src_port_low = 0x0;\n\trule.src_port_high = 0xffff;\n\n\trule.dst_mask_len = 33;\n\n\t/* add rules to context and try to build it */\n\tret = rte_acl_ipv4vlan_add_rules(acx, &rule, 1);\n\tif (ret == 0) {\n\t\tprintf(\"Line %i: Adding rules to ACL context \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\tgoto err;\n\t}\n\n\trule.dst_mask_len = 0;\n\trule.src_mask_len = 33;\n\n\t/* add rules to context and try to build it */\n\tret = rte_acl_ipv4vlan_add_rules(acx, &rule, 1);\n\tif (ret == 0) {\n\t\tprintf(\"Line %i: Adding rules to ACL context \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\tgoto err;\n\t}\n\n\trule.dst_mask_len = 0;\n\trule.src_mask_len = 0;\n\trule.data.userdata = 0;\n\n\t/* try adding this rule (it should fail because userdata is invalid) */\n\tret = rte_acl_ipv4vlan_add_rules(acx, &rule, 1);\n\tif (ret == 0) {\n\t\tprintf(\"Line %i: Adding a rule with invalid user data \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\trte_acl_free(acx);\n\n\treturn 0;\n\nerr:\n\trte_acl_free(acx);\n\n\treturn -1;\n}\n\n/*\n * test functions by passing invalid or\n * non-workable parameters.\n *\n * we do very limited testing of classify functions here\n * because those are performance-critical and\n * thus don't do much parameter checking.\n */\nstatic int\ntest_invalid_parameters(void)\n{\n\tstruct rte_acl_param param;\n\tstruct rte_acl_ctx *acx;\n\tstruct rte_acl_ipv4vlan_rule rule;\n\tint result;\n\n\tuint32_t layout[RTE_ACL_IPV4VLAN_NUM] = {0};\n\n\n\t/**\n\t * rte_ac_create()\n\t */\n\n\t/* NULL param */\n\tacx = rte_acl_create(NULL);\n\tif (acx != NULL) {\n\t\tprintf(\"Line %i: ACL context creation with NULL param \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* zero rule size */\n\tmemcpy(¶m, &acl_param, sizeof(param));\n\tparam.rule_size = 0;\n\n\tacx = rte_acl_create(¶m);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: ACL context creation with zero rule len \"\n\t\t\t\t\"failed!\\n\", __LINE__);\n\t\treturn -1;\n\t} else\n\t\trte_acl_free(acx);\n\n\t/* zero max rule num */\n\tmemcpy(¶m, &acl_param, sizeof(param));\n\tparam.max_rule_num = 0;\n\n\tacx = rte_acl_create(¶m);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: ACL context creation with zero rule num \"\n\t\t\t\t\"failed!\\n\", __LINE__);\n\t\treturn -1;\n\t} else\n\t\trte_acl_free(acx);\n\n\t/* invalid NUMA node */\n\tmemcpy(¶m, &acl_param, sizeof(param));\n\tparam.socket_id = RTE_MAX_NUMA_NODES + 1;\n\n\tacx = rte_acl_create(¶m);\n\tif (acx != NULL) {\n\t\tprintf(\"Line %i: ACL context creation with invalid NUMA \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* NULL name */\n\tmemcpy(¶m, &acl_param, sizeof(param));\n\tparam.name = NULL;\n\n\tacx = rte_acl_create(¶m);\n\tif (acx != NULL) {\n\t\tprintf(\"Line %i: ACL context creation with NULL name \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/**\n\t * rte_acl_find_existing\n\t */\n\n\tacx = rte_acl_find_existing(NULL);\n\tif (acx != NULL) {\n\t\tprintf(\"Line %i: NULL ACL context found!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/**\n\t * rte_acl_ipv4vlan_add_rules\n\t */\n\n\t/* initialize everything */\n\tmemcpy(¶m, &acl_param, sizeof(param));\n\tacx = rte_acl_create(¶m);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: ACL context creation failed!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\n\tmemcpy(&rule, &acl_rule, sizeof(rule));\n\n\t/* NULL context */\n\tresult = rte_acl_ipv4vlan_add_rules(NULL, &rule, 1);\n\tif (result == 0) {\n\t\tprintf(\"Line %i: Adding rules with NULL ACL context \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* NULL rule */\n\tresult = rte_acl_ipv4vlan_add_rules(acx, NULL, 1);\n\tif (result == 0) {\n\t\tprintf(\"Line %i: Adding NULL rule to ACL context \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* zero count (should succeed) */\n\tresult = rte_acl_ipv4vlan_add_rules(acx, &rule, 0);\n\tif (result != 0) {\n\t\tprintf(\"Line %i: Adding 0 rules to ACL context failed!\\n\",\n\t\t\t__LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* free ACL context */\n\trte_acl_free(acx);\n\n\t/* set wrong rule_size so that adding any rules would fail */\n\tparam.rule_size = RTE_ACL_IPV4VLAN_RULE_SZ + 4;\n\tacx = rte_acl_create(¶m);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: ACL context creation failed!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\n\t/* try adding a rule with size different from context rule_size */\n\tresult = rte_acl_ipv4vlan_add_rules(acx, &rule, 1);\n\tif (result == 0) {\n\t\tprintf(\"Line %i: Adding an invalid sized rule \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* free ACL context */\n\trte_acl_free(acx);\n\n\n\t/**\n\t * rte_acl_ipv4vlan_build\n\t */\n\n\t/* reinitialize context */\n\tmemcpy(¶m, &acl_param, sizeof(param));\n\tacx = rte_acl_create(¶m);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: ACL context creation failed!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\n\t/* NULL context */\n\tresult = rte_acl_ipv4vlan_build(NULL, layout, 1);\n\tif (result == 0) {\n\t\tprintf(\"Line %i: Building with NULL context \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* NULL layout */\n\tresult = rte_acl_ipv4vlan_build(acx, NULL, 1);\n\tif (result == 0) {\n\t\tprintf(\"Line %i: Building with NULL layout \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* zero categories (should not fail) */\n\tresult = rte_acl_ipv4vlan_build(acx, layout, 0);\n\tif (result == 0) {\n\t\tprintf(\"Line %i: Building with 0 categories should fail!\\n\",\n\t\t\t__LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* SSE classify test */\n\n\t/* cover zero categories in classify (should not fail) */\n\tresult = rte_acl_classify(acx, NULL, NULL, 0, 0);\n\tif (result != 0) {\n\t\tprintf(\"Line %i: SSE classify with zero categories \"\n\t\t\t\t\"failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* cover invalid but positive categories in classify */\n\tresult = rte_acl_classify(acx, NULL, NULL, 0, 3);\n\tif (result == 0) {\n\t\tprintf(\"Line %i: SSE classify with 3 categories \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* scalar classify test */\n\n\t/* cover zero categories in classify (should not fail) */\n\tresult = rte_acl_classify_alg(acx, NULL, NULL, 0, 0,\n\t\tRTE_ACL_CLASSIFY_SCALAR);\n\tif (result != 0) {\n\t\tprintf(\"Line %i: Scalar classify with zero categories \"\n\t\t\t\t\"failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* cover invalid but positive categories in classify */\n\tresult = rte_acl_classify(acx, NULL, NULL, 0, 3);\n\tif (result == 0) {\n\t\tprintf(\"Line %i: Scalar classify with 3 categories \"\n\t\t\t\t\"should have failed!\\n\", __LINE__);\n\t\trte_acl_free(acx);\n\t\treturn -1;\n\t}\n\n\t/* free ACL context */\n\trte_acl_free(acx);\n\n\n\t/**\n\t * make sure void functions don't crash with NULL parameters\n\t */\n\n\trte_acl_free(NULL);\n\n\trte_acl_dump(NULL);\n\n\treturn 0;\n}\n\n/**\n * Various tests that don't test much but improve coverage\n */\nstatic int\ntest_misc(void)\n{\n\tstruct rte_acl_param param;\n\tstruct rte_acl_ctx *acx;\n\n\t/* create context */\n\tmemcpy(¶m, &acl_param, sizeof(param));\n\n\tacx = rte_acl_create(¶m);\n\tif (acx == NULL) {\n\t\tprintf(\"Line %i: Error creating ACL context!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\n\t/* dump context with rules - useful for coverage */\n\trte_acl_list_dump();\n\n\trte_acl_dump(acx);\n\n\trte_acl_free(acx);\n\n\treturn 0;\n}\n\nstatic int\ntest_acl(void)\n{\n\tif (test_invalid_parameters() < 0)\n\t\treturn -1;\n\tif (test_invalid_rules() < 0)\n\t\treturn -1;\n\tif (test_create_find_add() < 0)\n\t\treturn -1;\n\tif (test_invalid_layout() < 0)\n\t\treturn -1;\n\tif (test_misc() < 0)\n\t\treturn -1;\n\tif (test_classify() < 0)\n\t\treturn -1;\n\tif (test_build_ports_range() < 0)\n\t\treturn -1;\n\tif (test_convert() < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic struct test_command acl_cmd = {\n\t.command = \"acl_autotest\",\n\t.callback = test_acl,\n};\nREGISTER_TEST_COMMAND(acl_cmd);\n" }, { "path": "app/test/test_acl.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef TEST_ACL_H_\n#define TEST_ACL_H_\n\nstruct ipv4_7tuple {\n\tuint16_t vlan;\n\tuint16_t domain;\n\tuint8_t proto;\n\tuint32_t ip_src;\n\tuint32_t ip_dst;\n\tuint16_t port_src;\n\tuint16_t port_dst;\n\tuint32_t allow;\n\tuint32_t deny;\n};\n\n/* rules for invalid layout test */\nstruct rte_acl_ipv4vlan_rule invalid_layout_rules[] = {\n\t\t/* test src and dst address */\n\t\t{\n\t\t\t\t.data = {.userdata = 1, .category_mask = 1},\n\t\t\t\t.src_addr = IPv4(10,0,0,0),\n\t\t\t\t.src_mask_len = 24,\n\t\t},\n\t\t{\n\t\t\t\t.data = {.userdata = 2, .category_mask = 1},\n\t\t\t\t.dst_addr = IPv4(10,0,0,0),\n\t\t\t\t.dst_mask_len = 24,\n\t\t},\n\t\t/* test src and dst ports */\n\t\t{\n\t\t\t\t.data = {.userdata = 3, .category_mask = 1},\n\t\t\t\t.dst_port_low = 100,\n\t\t\t\t.dst_port_high = 100,\n\t\t},\n\t\t{\n\t\t\t\t.data = {.userdata = 4, .category_mask = 1},\n\t\t\t\t.src_port_low = 100,\n\t\t\t\t.src_port_high = 100,\n\t\t},\n\t\t/* test proto */\n\t\t{\n\t\t\t\t.data = {.userdata = 5, .category_mask = 1},\n\t\t\t\t.proto = 0xf,\n\t\t\t\t.proto_mask = 0xf\n\t\t},\n\t\t{\n\t\t\t\t.data = {.userdata = 6, .category_mask = 1},\n\t\t\t\t.dst_port_low = 0xf,\n\t\t\t\t.dst_port_high = 0xf,\n\t\t}\n};\n\n/* these might look odd because they don't match up the rules. This is\n * intentional, as the invalid layout test presumes returning the correct\n * results using the wrong data layout.\n */\nstruct ipv4_7tuple invalid_layout_data[] = {\n\t\t{.ip_src = IPv4(10,0,1,0)}, /* should not match */\n\t\t{.ip_src = IPv4(10,0,0,1), .allow = 2}, /* should match 2 */\n\t\t{.port_src = 100, .allow = 4}, /* should match 4 */\n\t\t{.port_dst = 0xf, .allow = 6}, /* should match 6 */\n};\n\n#define ACL_ALLOW 0\n#define ACL_DENY 1\n#define ACL_ALLOW_MASK 0x1\n#define ACL_DENY_MASK 0x2\n\n/* ruleset for ACL unit test */\nstruct rte_acl_ipv4vlan_rule acl_test_rules[] = {\n/* destination IP addresses */\n\t\t/* matches all packets traveling to 192.168.0.0/16 */\n\t\t{\n\t\t\t\t.data = {.userdata = 1, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 230},\n\t\t\t\t.dst_addr = IPv4(192,168,0,0),\n\t\t\t\t.dst_mask_len = 16,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches all packets traveling to 192.168.1.0/24 */\n\t\t{\n\t\t\t\t.data = {.userdata = 2, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 330},\n\t\t\t\t.dst_addr = IPv4(192,168,1,0),\n\t\t\t\t.dst_mask_len = 24,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches all packets traveling to 192.168.1.50 */\n\t\t{\n\t\t\t\t.data = {.userdata = 3, .category_mask = ACL_DENY_MASK,\n\t\t\t\t\t\t.priority = 230},\n\t\t\t\t.dst_addr = IPv4(192,168,1,50),\n\t\t\t\t.dst_mask_len = 32,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\n/* source IP addresses */\n\t\t/* matches all packets traveling from 10.0.0.0/8 */\n\t\t{\n\t\t\t\t.data = {.userdata = 4, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 240},\n\t\t\t\t.src_addr = IPv4(10,0,0,0),\n\t\t\t\t.src_mask_len = 8,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches all packets traveling from 10.1.1.0/24 */\n\t\t{\n\t\t\t\t.data = {.userdata = 5, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 340},\n\t\t\t\t.src_addr = IPv4(10,1,1,0),\n\t\t\t\t.src_mask_len = 24,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches all packets traveling from 10.1.1.1 */\n\t\t{\n\t\t\t\t.data = {.userdata = 6, .category_mask = ACL_DENY_MASK,\n\t\t\t\t\t\t.priority = 240},\n\t\t\t\t.src_addr = IPv4(10,1,1,1),\n\t\t\t\t.src_mask_len = 32,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\n/* VLAN tag */\n\t\t/* matches all packets with lower 7 bytes of VLAN tag equal to 0x64 */\n\t\t{\n\t\t\t\t.data = {.userdata = 7, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 260},\n\t\t\t\t.vlan = 0x64,\n\t\t\t\t.vlan_mask = 0x7f,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches all packets with VLAN tags that have 0x5 in them */\n\t\t{\n\t\t\t\t.data = {.userdata = 8, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 260},\n\t\t\t\t.vlan = 0x5,\n\t\t\t\t.vlan_mask = 0x5,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches all packets with VLAN tag 5 */\n\t\t{\n\t\t\t\t.data = {.userdata = 9, .category_mask = ACL_DENY_MASK,\n\t\t\t\t\t\t.priority = 360},\n\t\t\t\t.vlan = 0x5,\n\t\t\t\t.vlan_mask = 0xffff,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\n/* VLAN domain */\n\t\t/* matches all packets with lower 7 bytes of domain equal to 0x64 */\n\t\t{\n\t\t\t\t.data = {.userdata = 10, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 250},\n\t\t\t\t.domain = 0x64,\n\t\t\t\t.domain_mask = 0x7f,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches all packets with domains that have 0x5 in them */\n\t\t{\n\t\t\t\t.data = {.userdata = 11, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 350},\n\t\t\t\t.domain = 0x5,\n\t\t\t\t.domain_mask = 0x5,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches all packets with domain 5 */\n\t\t{\n\t\t\t\t.data = {.userdata = 12, .category_mask = ACL_DENY_MASK,\n\t\t\t\t\t\t.priority = 350},\n\t\t\t\t.domain = 0x5,\n\t\t\t\t.domain_mask = 0xffff,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\n/* destination port */\n\t\t/* matches everything with dst port 80 */\n\t\t{\n\t\t\t\t.data = {.userdata = 13, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 310},\n\t\t\t\t.dst_port_low = 80,\n\t\t\t\t.dst_port_high = 80,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t},\n\t\t/* matches everything with dst port 22-1023 */\n\t\t{\n\t\t\t\t.data = {.userdata = 14, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 210},\n\t\t\t\t.dst_port_low = 22,\n\t\t\t\t.dst_port_high = 1023,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t},\n\t\t/* matches everything with dst port 1020 */\n\t\t{\n\t\t\t\t.data = {.userdata = 15, .category_mask = ACL_DENY_MASK,\n\t\t\t\t\t\t.priority = 310},\n\t\t\t\t.dst_port_low = 1020,\n\t\t\t\t.dst_port_high = 1020,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t},\n\t\t/* matches everything with dst portrange 1000-2000 */\n\t\t{\n\t\t\t\t.data = {.userdata = 16, .category_mask = ACL_DENY_MASK,\n\t\t\t\t\t\t.priority = 210},\n\t\t\t\t.dst_port_low = 1000,\n\t\t\t\t.dst_port_high = 2000,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t},\n\n/* source port */\n\t\t/* matches everything with src port 80 */\n\t\t{\n\t\t\t\t.data = {.userdata = 17, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 320},\n\t\t\t\t.src_port_low = 80,\n\t\t\t\t.src_port_high = 80,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches everything with src port 22-1023 */\n\t\t{\n\t\t\t\t.data = {.userdata = 18, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 220},\n\t\t\t\t.src_port_low = 22,\n\t\t\t\t.src_port_high = 1023,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches everything with src port 1020 */\n\t\t{\n\t\t\t\t.data = {.userdata = 19, .category_mask = ACL_DENY_MASK,\n\t\t\t\t\t\t.priority = 320},\n\t\t\t\t.src_port_low = 1020,\n\t\t\t\t.src_port_high = 1020,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches everything with src portrange 1000-2000 */\n\t\t{\n\t\t\t\t.data = {.userdata = 20, .category_mask = ACL_DENY_MASK,\n\t\t\t\t\t\t.priority = 220},\n\t\t\t\t.src_port_low = 1000,\n\t\t\t\t.src_port_high = 2000,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\n/* protocol number */\n\t\t/* matches all packets with protocol number either 0x64 or 0xE4 */\n\t\t{\n\t\t\t\t.data = {.userdata = 21, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 270},\n\t\t\t\t.proto = 0x64,\n\t\t\t\t.proto_mask = 0x7f,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches all packets with protocol that have 0x5 in them */\n\t\t{\n\t\t\t\t.data = {.userdata = 22, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 1},\n\t\t\t\t.proto = 0x5,\n\t\t\t\t.proto_mask = 0x5,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\t\t/* matches all packets with protocol 5 */\n\t\t{\n\t\t\t\t.data = {.userdata = 23, .category_mask = ACL_DENY_MASK,\n\t\t\t\t\t\t.priority = 370},\n\t\t\t\t.proto = 0x5,\n\t\t\t\t.proto_mask = 0xff,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 0,\n\t\t\t\t.dst_port_high = 0xffff,\n\t\t},\n\n/* rules combining various fields */\n\t\t{\n\t\t\t\t.data = {.userdata = 24, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 400},\n\t\t\t\t/** make sure that unmasked bytes don't fail! */\n\t\t\t\t.dst_addr = IPv4(1,2,3,4),\n\t\t\t\t.dst_mask_len = 16,\n\t\t\t\t.src_addr = IPv4(5,6,7,8),\n\t\t\t\t.src_mask_len = 24,\n\t\t\t\t.proto = 0x5,\n\t\t\t\t.proto_mask = 0xff,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 22,\n\t\t\t\t.dst_port_high = 1024,\n\t\t\t\t.vlan = 0x8100,\n\t\t\t\t.vlan_mask = 0xffff,\n\t\t\t\t.domain = 0x64,\n\t\t\t\t.domain_mask = 0xffff,\n\t\t},\n\t\t{\n\t\t\t\t.data = {.userdata = 25, .category_mask = ACL_DENY_MASK,\n\t\t\t\t\t\t.priority = 400},\n\t\t\t\t.dst_addr = IPv4(5,6,7,8),\n\t\t\t\t.dst_mask_len = 24,\n\t\t\t\t.src_addr = IPv4(1,2,3,4),\n\t\t\t\t.src_mask_len = 16,\n\t\t\t\t.proto = 0x5,\n\t\t\t\t.proto_mask = 0xff,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 22,\n\t\t\t\t.dst_port_high = 1024,\n\t\t\t\t.vlan = 0x8100,\n\t\t\t\t.vlan_mask = 0xffff,\n\t\t\t\t.domain = 0x64,\n\t\t\t\t.domain_mask = 0xffff,\n\t\t},\n\t\t{\n\t\t\t\t.data = {.userdata = 26, .category_mask = ACL_ALLOW_MASK,\n\t\t\t\t\t\t.priority = 500},\n\t\t\t\t.dst_addr = IPv4(1,2,3,4),\n\t\t\t\t.dst_mask_len = 8,\n\t\t\t\t.src_addr = IPv4(5,6,7,8),\n\t\t\t\t.src_mask_len = 32,\n\t\t\t\t.proto = 0x5,\n\t\t\t\t.proto_mask = 0xff,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 22,\n\t\t\t\t.dst_port_high = 1024,\n\t\t\t\t.vlan = 0x64,\n\t\t\t\t.vlan_mask = 0xffff,\n\t\t},\n\t\t{\n\t\t\t\t.data = {.userdata = 27, .category_mask = ACL_DENY_MASK,\n\t\t\t\t\t\t.priority = 500},\n\t\t\t\t.dst_addr = IPv4(5,6,7,8),\n\t\t\t\t.dst_mask_len = 32,\n\t\t\t\t.src_addr = IPv4(1,2,3,4),\n\t\t\t\t.src_mask_len = 8,\n\t\t\t\t.proto = 0x5,\n\t\t\t\t.proto_mask = 0xff,\n\t\t\t\t.src_port_low = 0,\n\t\t\t\t.src_port_high = 0xffff,\n\t\t\t\t.dst_port_low = 22,\n\t\t\t\t.dst_port_high = 1024,\n\t\t\t\t.vlan = 0x64,\n\t\t\t\t.vlan_mask = 0xffff,\n\t\t},\n};\n\n/* data for ACL unit test */\nstruct ipv4_7tuple acl_test_data[] = {\n/* testing single rule aspects */\n\t\t{.ip_src = IPv4(10,0,0,0), .allow = 4}, /* should match 4 */\n\t\t{.ip_src = IPv4(10,1,1,2), .allow = 5}, /* should match 5 */\n\t\t{.ip_src = IPv4(10,1,1,1), .allow = 5,\n\t\t\t\t.deny = 6}, /* should match 5, 6 */\n\t\t{.ip_dst = IPv4(10,0,0,0)}, /* should not match */\n\t\t{.ip_dst = IPv4(10,1,1,2)}, /* should not match */\n\t\t{.ip_dst = IPv4(10,1,1,1)}, /* should not match */\n\n\t\t{.ip_src = IPv4(192,168,2,50)}, /* should not match */\n\t\t{.ip_src = IPv4(192,168,1,2)}, /* should not match */\n\t\t{.ip_src = IPv4(192,168,1,50)}, /* should not match */\n\t\t{.ip_dst = IPv4(192,168,2,50), .allow = 1}, /* should match 1 */\n\t\t{.ip_dst = IPv4(192,168,1,49), .allow = 2}, /* should match 2 */\n\t\t{.ip_dst = IPv4(192,168,1,50), .allow = 2,\n\t\t\t\t.deny = 3}, /* should match 2, 3 */\n\n\t\t{.vlan = 0x64, .allow = 7}, /* should match 7 */\n\t\t{.vlan = 0xfE4, .allow = 7}, /* should match 7 */\n\t\t{.vlan = 0xE2}, /* should not match */\n\t\t{.vlan = 0xD, .allow = 8}, /* should match 8 */\n\t\t{.vlan = 0x6}, /* should not match */\n\t\t{.vlan = 0x5, .allow = 8, .deny = 9}, /* should match 8, 9 */\n\n\t\t{.domain = 0x64, .allow = 10}, /* should match 10 */\n\t\t{.domain = 0xfE4, .allow = 10}, /* should match 10 */\n\t\t{.domain = 0xE2}, /* should not match */\n\t\t{.domain = 0xD, .allow = 11}, /* should match 11 */\n\t\t{.domain = 0x6}, /* should not match */\n\t\t{.domain = 0x5, .allow = 11, .deny = 12}, /* should match 11, 12 */\n\n\t\t{.port_dst = 80, .allow = 13}, /* should match 13 */\n\t\t{.port_dst = 79, .allow = 14}, /* should match 14 */\n\t\t{.port_dst = 81, .allow = 14}, /* should match 14 */\n\t\t{.port_dst = 21}, /* should not match */\n\t\t{.port_dst = 1024, .deny = 16}, /* should match 16 */\n\t\t{.port_dst = 1020, .allow = 14, .deny = 15}, /* should match 14, 15 */\n\n\t\t{.port_src = 80, .allow = 17}, /* should match 17 */\n\t\t{.port_src = 79, .allow = 18}, /* should match 18 */\n\t\t{.port_src = 81, .allow = 18}, /* should match 18 */\n\t\t{.port_src = 21}, /* should not match */\n\t\t{.port_src = 1024, .deny = 20}, /* should match 20 */\n\t\t{.port_src = 1020, .allow = 18, .deny = 19}, /* should match 18, 19 */\n\n\t\t{.proto = 0x64, .allow = 21}, /* should match 21 */\n\t\t{.proto = 0xE4, .allow = 21}, /* should match 21 */\n\t\t{.proto = 0xE2}, /* should not match */\n\t\t{.proto = 0xD, .allow = 22}, /* should match 22 */\n\t\t{.proto = 0x6}, /* should not match */\n\t\t{.proto = 0x5, .allow = 22, .deny = 23}, /* should match 22, 23 */\n\n/* testing matching multiple rules at once */\n\t\t{.vlan = 0x5, .ip_src = IPv4(10,1,1,1),\n\t\t\t\t.allow = 5, .deny = 9}, /* should match 5, 9 */\n\t\t{.vlan = 0x5, .ip_src = IPv4(192,168,2,50),\n\t\t\t\t.allow = 8, .deny = 9}, /* should match 8, 9 */\n\t\t{.vlan = 0x55, .ip_src = IPv4(192,168,1,49),\n\t\t\t\t.allow = 8}, /* should match 8 */\n\t\t{.port_dst = 80, .port_src = 1024,\n\t\t\t\t.allow = 13, .deny = 20}, /* should match 13,20 */\n\t\t{.port_dst = 79, .port_src = 1024,\n\t\t\t\t.allow = 14, .deny = 20}, /* should match 14,20 */\n\t\t{.proto = 0x5, .ip_dst = IPv4(192,168,2,50),\n\t\t\t\t.allow = 1, .deny = 23}, /* should match 1, 23 */\n\n\t\t{.proto = 0x5, .ip_dst = IPv4(192,168,1,50),\n\t\t\t\t.allow = 2, .deny = 23}, /* should match 2, 23 */\n\t\t{.vlan = 0x64, .domain = 0x5,\n\t\t\t\t.allow = 11, .deny = 12}, /* should match 11, 12 */\n\t\t{.proto = 0x5, .port_src = 80,\n\t\t\t\t.allow = 17, .deny = 23}, /* should match 17, 23 */\n\t\t{.proto = 0x5, .port_dst = 80,\n\t\t\t\t.allow = 13, .deny = 23}, /* should match 13, 23 */\n\t\t{.proto = 0x51, .port_src = 5000}, /* should not match */\n\t\t{.ip_src = IPv4(192,168,1,50),\n\t\t\t\t.ip_dst = IPv4(10,0,0,0),\n\t\t\t\t.proto = 0x51,\n\t\t\t\t.port_src = 5000,\n\t\t\t\t.port_dst = 5000}, /* should not match */\n\n/* test full packet rules */\n\t\t{\n\t\t\t\t.ip_dst = IPv4(1,2,100,200),\n\t\t\t\t.ip_src = IPv4(5,6,7,254),\n\t\t\t\t.proto = 0x5,\n\t\t\t\t.vlan = 0x8100,\n\t\t\t\t.domain = 0x64,\n\t\t\t\t.port_src = 12345,\n\t\t\t\t.port_dst = 80,\n\t\t\t\t.allow = 24,\n\t\t\t\t.deny = 23\n\t\t}, /* should match 23, 24 */\n\t\t{\n\t\t\t\t.ip_dst = IPv4(5,6,7,254),\n\t\t\t\t.ip_src = IPv4(1,2,100,200),\n\t\t\t\t.proto = 0x5,\n\t\t\t\t.vlan = 0x8100,\n\t\t\t\t.domain = 0x64,\n\t\t\t\t.port_src = 12345,\n\t\t\t\t.port_dst = 80,\n\t\t\t\t.allow = 13,\n\t\t\t\t.deny = 25\n\t\t}, /* should match 13, 25 */\n\t\t{\n\t\t\t\t.ip_dst = IPv4(1,10,20,30),\n\t\t\t\t.ip_src = IPv4(5,6,7,8),\n\t\t\t\t.proto = 0x5,\n\t\t\t\t.vlan = 0x64,\n\t\t\t\t.port_src = 12345,\n\t\t\t\t.port_dst = 80,\n\t\t\t\t.allow = 26,\n\t\t\t\t.deny = 23\n\t\t}, /* should match 23, 26 */\n\t\t{\n\t\t\t\t.ip_dst = IPv4(5,6,7,8),\n\t\t\t\t.ip_src = IPv4(1,10,20,30),\n\t\t\t\t.proto = 0x5,\n\t\t\t\t.vlan = 0x64,\n\t\t\t\t.port_src = 12345,\n\t\t\t\t.port_dst = 80,\n\t\t\t\t.allow = 13,\n\t\t\t\t.deny = 27\n\t\t}, /* should match 13, 27 */\n\t\t{\n\t\t\t\t.ip_dst = IPv4(2,2,3,4),\n\t\t\t\t.ip_src = IPv4(4,6,7,8),\n\t\t\t\t.proto = 0x5,\n\t\t\t\t.vlan = 0x64,\n\t\t\t\t.port_src = 12345,\n\t\t\t\t.port_dst = 80,\n\t\t\t\t.allow = 13,\n\t\t\t\t.deny = 23\n\t\t}, /* should match 13, 23 */\n\t\t{\n\t\t\t\t.ip_dst = IPv4(1,2,3,4),\n\t\t\t\t.ip_src = IPv4(4,6,7,8),\n\t\t\t\t.proto = 0x5,\n\t\t\t\t.vlan = 0x64,\n\t\t\t\t.port_src = 12345,\n\t\t\t\t.port_dst = 80,\n\t\t\t\t.allow = 13,\n\t\t\t\t.deny = 23\n\t\t}, /* should match 13, 23 */\n\n\n/* visual separator! */\n\t\t{\n\t\t\t\t.ip_dst = IPv4(1,2,100,200),\n\t\t\t\t.ip_src = IPv4(5,6,7,254),\n\t\t\t\t.proto = 0x55,\n\t\t\t\t.vlan = 0x8000,\n\t\t\t\t.domain = 0x6464,\n\t\t\t\t.port_src = 12345,\n\t\t\t\t.port_dst = 8080,\n\t\t\t\t.allow = 10\n\t\t}, /* should match 10 */\n\t\t{\n\t\t\t\t.ip_dst = IPv4(5,6,7,254),\n\t\t\t\t.ip_src = IPv4(1,2,100,200),\n\t\t\t\t.proto = 0x55,\n\t\t\t\t.vlan = 0x8100,\n\t\t\t\t.domain = 0x6464,\n\t\t\t\t.port_src = 12345,\n\t\t\t\t.port_dst = 180,\n\t\t\t\t.allow = 10\n\t\t}, /* should match 10 */\n\t\t{\n\t\t\t\t.ip_dst = IPv4(1,10,20,30),\n\t\t\t\t.ip_src = IPv4(5,6,7,8),\n\t\t\t\t.proto = 0x55,\n\t\t\t\t.vlan = 0x64,\n\t\t\t\t.port_src = 12345,\n\t\t\t\t.port_dst = 180,\n\t\t\t\t.allow = 7\n\t\t}, /* should match 7 */\n\t\t{\n\t\t\t\t.ip_dst = IPv4(5,6,7,8),\n\t\t\t\t.ip_src = IPv4(1,10,20,30),\n\t\t\t\t.proto = 0x55,\n\t\t\t\t.vlan = 0x64,\n\t\t\t\t.port_src = 12345,\n\t\t\t\t.port_dst = 180,\n\t\t\t\t.allow = 7\n\t\t}, /* should match 7 */\n\t\t{\n\t\t\t\t.ip_dst = IPv4(2,2,3,4),\n\t\t\t\t.ip_src = IPv4(4,6,7,8),\n\t\t\t\t.proto = 0x55,\n\t\t\t\t.vlan = 0x64,\n\t\t\t\t.port_src = 12345,\n\t\t\t\t.port_dst = 180,\n\t\t\t\t.allow = 7\n\t\t}, /* should match 7 */\n\t\t{\n\t\t\t\t.ip_dst = IPv4(1,2,3,4),\n\t\t\t\t.ip_src = IPv4(4,6,7,8),\n\t\t\t\t.proto = 0x50,\n\t\t\t\t.vlan = 0x6466,\n\t\t\t\t.port_src = 12345,\n\t\t\t\t.port_dst = 12345,\n\t\t}, /* should not match */\n};\n\n#endif /* TEST_ACL_H_ */\n" }, { "path": "app/test/test_alarm.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#define US_PER_MS 1000\n\n#define RTE_TEST_ALARM_TIMEOUT 3000 /* ms */\n#define RTE_TEST_CHECK_PERIOD 1000 /* ms */\n\nstatic volatile int flag;\n\nstatic void\ntest_alarm_callback(void *cb_arg)\n{\n\tflag = 1;\n\tprintf(\"Callback setting flag - OK. [cb_arg = %p]\\n\", cb_arg);\n}\n\nstatic rte_atomic32_t cb_count;\n\nstatic void\ntest_multi_cb(void *arg)\n{\n\trte_atomic32_inc(&cb_count);\n\tprintf(\"In %s - arg = %p\\n\", __func__, arg);\n}\n\nstatic volatile int recursive_error = 0;\n\nstatic void\ntest_remove_in_callback(void *arg)\n{\n\tprintf(\"In %s - arg = %p\\n\", __func__, arg);\n\tif (rte_eal_alarm_cancel(test_remove_in_callback, arg) ||\n\t\t\trte_eal_alarm_cancel(test_remove_in_callback, (void *)-1)) {\n\t\tprintf(\"Error - cancelling callback from within function succeeded!\\n\");\n\t\trecursive_error = 1;\n\t}\n\tflag = (int)((uintptr_t)arg);\n}\n\nstatic volatile int flag_2;\n\nstatic void\ntest_remove_in_callback_2(void *arg)\n{\n\tif (rte_eal_alarm_cancel(test_remove_in_callback_2, arg) || rte_eal_alarm_cancel(test_remove_in_callback_2, (void *)-1)) {\n\t\tprintf(\"Error - cancelling callback of test_remove_in_callback_2\\n\");\n\t\treturn;\n\t}\n\tflag_2 = 1;\n}\n\nstatic int\ntest_multi_alarms(void)\n{\n\tint rm_count = 0;\n\tcb_count.cnt = 0;\n\n\tprintf(\"Expect 6 callbacks in order...\\n\");\n\t/* add two alarms in order */\n\trte_eal_alarm_set(1000 * US_PER_MS, test_multi_cb, (void *)1);\n\trte_eal_alarm_set(2000 * US_PER_MS, test_multi_cb, (void *)2);\n\n\t/* now add in reverse order */\n\trte_eal_alarm_set(6000 * US_PER_MS, test_multi_cb, (void *)6);\n\trte_eal_alarm_set(5000 * US_PER_MS, test_multi_cb, (void *)5);\n\trte_eal_alarm_set(4000 * US_PER_MS, test_multi_cb, (void *)4);\n\trte_eal_alarm_set(3000 * US_PER_MS, test_multi_cb, (void *)3);\n\n\t/* wait for expiry */\n\trte_delay_ms(6500);\n\tif (cb_count.cnt != 6) {\n\t\tprintf(\"Missing callbacks\\n\");\n\t\t/* remove any callbacks that might remain */\n\t\trte_eal_alarm_cancel(test_multi_cb, (void *)-1);\n\t\treturn -1;\n\t}\n\n\tcb_count.cnt = 0;\n\tprintf(\"Expect only callbacks with args 1 and 3...\\n\");\n\t/* Add 3 flags, then delete one */\n\trte_eal_alarm_set(3000 * US_PER_MS, test_multi_cb, (void *)3);\n\trte_eal_alarm_set(2000 * US_PER_MS, test_multi_cb, (void *)2);\n\trte_eal_alarm_set(1000 * US_PER_MS, test_multi_cb, (void *)1);\n\trm_count = rte_eal_alarm_cancel(test_multi_cb, (void *)2);\n\n\trte_delay_ms(3500);\n\tif (cb_count.cnt != 2 || rm_count != 1) {\n\t\tprintf(\"Error: invalid flags count or alarm removal failure\"\n\t\t\t\t\" - flags value = %d, expected = %d\\n\",\n\t\t\t\t(int)cb_count.cnt, 2);\n\t\t/* remove any callbacks that might remain */\n\t\trte_eal_alarm_cancel(test_multi_cb, (void *)-1);\n\t\treturn -1;\n\t}\n\n\tprintf(\"Testing adding and then removing multiple alarms\\n\");\n\t/* finally test that no callbacks are called if we delete them all*/\n\trte_eal_alarm_set(1000 * US_PER_MS, test_multi_cb, (void *)1);\n\trte_eal_alarm_set(1000 * US_PER_MS, test_multi_cb, (void *)2);\n\trte_eal_alarm_set(1000 * US_PER_MS, test_multi_cb, (void *)3);\n\trm_count = rte_eal_alarm_cancel(test_alarm_callback, (void *)-1);\n\tif (rm_count != 0) {\n\t\tprintf(\"Error removing non-existant alarm succeeded\\n\");\n\t\trte_eal_alarm_cancel(test_multi_cb, (void *) -1);\n\t\treturn -1;\n\t}\n\trm_count = rte_eal_alarm_cancel(test_multi_cb, (void *) -1);\n\tif (rm_count != 3) {\n\t\tprintf(\"Error removing all pending alarm callbacks\\n\");\n\t\treturn -1;\n\t}\n\n\t/* Test that we cannot cancel an alarm from within the callback itself\n\t * Also test that we can cancel head-of-line callbacks ok.*/\n\tflag = 0;\n\trecursive_error = 0;\n\trte_eal_alarm_set(1000 * US_PER_MS, test_remove_in_callback, (void *)1);\n\trte_eal_alarm_set(2000 * US_PER_MS, test_remove_in_callback, (void *)2);\n\trm_count = rte_eal_alarm_cancel(test_remove_in_callback, (void *)1);\n\tif (rm_count != 1) {\n\t\tprintf(\"Error cancelling head-of-list callback\\n\");\n\t\treturn -1;\n\t}\n\trte_delay_ms(1500);\n\tif (flag != 0) {\n\t\tprintf(\"Error, cancelling head-of-list leads to premature callback\\n\");\n\t\treturn -1;\n\t}\n\trte_delay_ms(1000);\n\tif (flag != 2) {\n\t\tprintf(\"Error - expected callback not called\\n\");\n\t\trte_eal_alarm_cancel(test_remove_in_callback, (void *)-1);\n\t\treturn -1;\n\t}\n\tif (recursive_error == 1)\n\t\treturn -1;\n\n\t/* Check if it can cancel all for the same callback */\n\tprintf(\"Testing canceling all for the same callback\\n\");\n\tflag_2 = 0;\n\trte_eal_alarm_set(1000 * US_PER_MS, test_remove_in_callback, (void *)1);\n\trte_eal_alarm_set(2000 * US_PER_MS, test_remove_in_callback_2, (void *)2);\n\trte_eal_alarm_set(3000 * US_PER_MS, test_remove_in_callback_2, (void *)3);\n\trte_eal_alarm_set(4000 * US_PER_MS, test_remove_in_callback, (void *)4);\n\trm_count = rte_eal_alarm_cancel(test_remove_in_callback_2, (void *)-1);\n\tif (rm_count != 2) {\n\t\tprintf(\"Error, cannot cancel all for the same callback\\n\");\n\t\treturn -1;\n\t}\n\trm_count = rte_eal_alarm_cancel(test_remove_in_callback, (void *)-1);\n\tif (rm_count != 2) {\n\t\tprintf(\"Error, cannot cancel all for the same callback\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntest_alarm(void)\n{\n\tint count = 0;\n\n\t/* check if the callback will be called */\n\tprintf(\"check if the callback will be called\\n\");\n\tflag = 0;\n\tif (rte_eal_alarm_set(RTE_TEST_ALARM_TIMEOUT * US_PER_MS,\n\t\t\ttest_alarm_callback, NULL) < 0) {\n\t\tprintf(\"fail to set alarm callback\\n\");\n\t\treturn -1;\n\t}\n\twhile (flag == 0 && count ++ < 6)\n\t\trte_delay_ms(RTE_TEST_CHECK_PERIOD);\n\n\tif (flag == 0){\n\t\tprintf(\"Callback not called\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check if it will fail to set alarm with wrong us value */\n\tprintf(\"check if it will fail to set alarm with wrong ms values\\n\");\n\tif (rte_eal_alarm_set(0, test_alarm_callback,\n\t\t\t\t\t\tNULL) >= 0) {\n\t\tprintf(\"should not be successful with 0 us value\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_eal_alarm_set(UINT64_MAX - 1, test_alarm_callback,\n\t\t\t\t\t\tNULL) >= 0) {\n\t\tprintf(\"should not be successful with (UINT64_MAX-1) us value\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check if it will fail to set alarm with null callback parameter */\n\tprintf(\"check if it will fail to set alarm with null callback parameter\\n\");\n\tif (rte_eal_alarm_set(RTE_TEST_ALARM_TIMEOUT, NULL, NULL) >= 0) {\n\t\tprintf(\"should not be successful to set alarm with null callback parameter\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check if it will fail to remove alarm with null callback parameter */\n\tprintf(\"check if it will fail to remove alarm with null callback parameter\\n\");\n\tif (rte_eal_alarm_cancel(NULL, NULL) == 0) {\n\t\tprintf(\"should not be successful to remove alarm with null callback parameter\");\n\t\treturn -1;\n\t}\n\n\tif (test_multi_alarms() != 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic struct test_command alarm_cmd = {\n\t.command = \"alarm_autotest\",\n\t.callback = test_alarm,\n};\nREGISTER_TEST_COMMAND(alarm_cmd);\n" }, { "path": "app/test/test_atomic.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n/*\n * Atomic Variables\n * ================\n *\n * - The main test function performs three subtests. The first test\n * checks that the usual inc/dec/add/sub functions are working\n * correctly:\n *\n * - Initialize 16-bit, 32-bit and 64-bit atomic variables to specific\n * values.\n *\n * - These variables are incremented and decremented on each core at\n * the same time in ``test_atomic_usual()``.\n *\n * - The function checks that once all lcores finish their function,\n * the value of the atomic variables are still the same.\n *\n * - The second test verifies the behavior of \"test and set\" functions.\n *\n * - Initialize 16-bit, 32-bit and 64-bit atomic variables to zero.\n *\n * - Invoke ``test_atomic_tas()`` on each lcore: before doing anything\n * else. The cores are waiting a synchro using ``while\n * (rte_atomic32_read(&val) == 0)`` which is triggered by the main test\n * function. Then all cores do a\n * ``rte_atomicXX_test_and_set()`` at the same time. If it is successful,\n * it increments another atomic counter.\n *\n * - The main function checks that the atomic counter was incremented\n * twice only (one for 16-bit, one for 32-bit and one for 64-bit values).\n *\n * - Test \"add/sub and return\"\n *\n * - Initialize 16-bit, 32-bit and 64-bit atomic variables to zero.\n *\n * - Invoke ``test_atomic_addsub_return()`` on each lcore. Before doing\n * anything else, the cores are waiting a synchro. Each lcore does\n * this operation several times::\n *\n * tmp = rte_atomicXX_add_return(&a, 1);\n * atomic_add(&count, tmp);\n * tmp = rte_atomicXX_sub_return(&a, 1);\n * atomic_sub(&count, tmp+1);\n *\n * - At the end of the test, the *count* value must be 0.\n */\n\n#define NUM_ATOMIC_TYPES 3\n\n#define N 10000\n\nstatic rte_atomic16_t a16;\nstatic rte_atomic32_t a32;\nstatic rte_atomic64_t a64;\nstatic rte_atomic64_t count;\nstatic rte_atomic32_t synchro;\n\nstatic int\ntest_atomic_usual(__attribute__((unused)) void *arg)\n{\n\tunsigned i;\n\n\twhile (rte_atomic32_read(&synchro) == 0)\n\t\t;\n\n\tfor (i = 0; i < N; i++)\n\t\trte_atomic16_inc(&a16);\n\tfor (i = 0; i < N; i++)\n\t\trte_atomic16_dec(&a16);\n\tfor (i = 0; i < (N / 5); i++)\n\t\trte_atomic16_add(&a16, 5);\n\tfor (i = 0; i < (N / 5); i++)\n\t\trte_atomic16_sub(&a16, 5);\n\n\tfor (i = 0; i < N; i++)\n\t\trte_atomic32_inc(&a32);\n\tfor (i = 0; i < N; i++)\n\t\trte_atomic32_dec(&a32);\n\tfor (i = 0; i < (N / 5); i++)\n\t\trte_atomic32_add(&a32, 5);\n\tfor (i = 0; i < (N / 5); i++)\n\t\trte_atomic32_sub(&a32, 5);\n\n\tfor (i = 0; i < N; i++)\n\t\trte_atomic64_inc(&a64);\n\tfor (i = 0; i < N; i++)\n\t\trte_atomic64_dec(&a64);\n\tfor (i = 0; i < (N / 5); i++)\n\t\trte_atomic64_add(&a64, 5);\n\tfor (i = 0; i < (N / 5); i++)\n\t\trte_atomic64_sub(&a64, 5);\n\n\treturn 0;\n}\n\nstatic int\ntest_atomic_tas(__attribute__((unused)) void *arg)\n{\n\twhile (rte_atomic32_read(&synchro) == 0)\n\t\t;\n\n\tif (rte_atomic16_test_and_set(&a16))\n\t\trte_atomic64_inc(&count);\n\tif (rte_atomic32_test_and_set(&a32))\n\t\trte_atomic64_inc(&count);\n\tif (rte_atomic64_test_and_set(&a64))\n\t\trte_atomic64_inc(&count);\n\n\treturn 0;\n}\n\nstatic int\ntest_atomic_addsub_and_return(__attribute__((unused)) void *arg)\n{\n\tuint32_t tmp16;\n\tuint32_t tmp32;\n\tuint64_t tmp64;\n\tunsigned i;\n\n\twhile (rte_atomic32_read(&synchro) == 0)\n\t\t;\n\n\tfor (i = 0; i < N; i++) {\n\t\ttmp16 = rte_atomic16_add_return(&a16, 1);\n\t\trte_atomic64_add(&count, tmp16);\n\n\t\ttmp16 = rte_atomic16_sub_return(&a16, 1);\n\t\trte_atomic64_sub(&count, tmp16+1);\n\n\t\ttmp32 = rte_atomic32_add_return(&a32, 1);\n\t\trte_atomic64_add(&count, tmp32);\n\n\t\ttmp32 = rte_atomic32_sub_return(&a32, 1);\n\t\trte_atomic64_sub(&count, tmp32+1);\n\n\t\ttmp64 = rte_atomic64_add_return(&a64, 1);\n\t\trte_atomic64_add(&count, tmp64);\n\n\t\ttmp64 = rte_atomic64_sub_return(&a64, 1);\n\t\trte_atomic64_sub(&count, tmp64+1);\n\t}\n\n\treturn 0;\n}\n\n/*\n * rte_atomic32_inc_and_test() would increase a 32 bits counter by one and then\n * test if that counter is equal to 0. It would return true if the counter is 0\n * and false if the counter is not 0. rte_atomic64_inc_and_test() could do the\n * same thing but for a 64 bits counter.\n * Here checks that if the 32/64 bits counter is equal to 0 after being atomically\n * increased by one. If it is, increase the variable of \"count\" by one which would\n * be checked as the result later.\n *\n */\nstatic int\ntest_atomic_inc_and_test(__attribute__((unused)) void *arg)\n{\n\twhile (rte_atomic32_read(&synchro) == 0)\n\t\t;\n\n\tif (rte_atomic16_inc_and_test(&a16)) {\n\t\trte_atomic64_inc(&count);\n\t}\n\tif (rte_atomic32_inc_and_test(&a32)) {\n\t\trte_atomic64_inc(&count);\n\t}\n\tif (rte_atomic64_inc_and_test(&a64)) {\n\t\trte_atomic64_inc(&count);\n\t}\n\n\treturn 0;\n}\n\n/*\n * rte_atomicXX_dec_and_test() should decrease a 32 bits counter by one and then\n * test if that counter is equal to 0. It should return true if the counter is 0\n * and false if the counter is not 0.\n * This test checks if the counter is equal to 0 after being atomically\n * decreased by one. If it is, increase the value of \"count\" by one which is to\n * be checked as the result later.\n */\nstatic int\ntest_atomic_dec_and_test(__attribute__((unused)) void *arg)\n{\n\twhile (rte_atomic32_read(&synchro) == 0)\n\t\t;\n\n\tif (rte_atomic16_dec_and_test(&a16))\n\t\trte_atomic64_inc(&count);\n\n\tif (rte_atomic32_dec_and_test(&a32))\n\t\trte_atomic64_inc(&count);\n\n\tif (rte_atomic64_dec_and_test(&a64))\n\t\trte_atomic64_inc(&count);\n\n\treturn 0;\n}\n\nstatic int\ntest_atomic(void)\n{\n\trte_atomic16_init(&a16);\n\trte_atomic32_init(&a32);\n\trte_atomic64_init(&a64);\n\trte_atomic64_init(&count);\n\trte_atomic32_init(&synchro);\n\n\trte_atomic16_set(&a16, 1UL << 10);\n\trte_atomic32_set(&a32, 1UL << 10);\n\trte_atomic64_set(&a64, 1ULL << 33);\n\n\tprintf(\"usual inc/dec/add/sub functions\\n\");\n\n\trte_eal_mp_remote_launch(test_atomic_usual, NULL, SKIP_MASTER);\n\trte_atomic32_set(&synchro, 1);\n\trte_eal_mp_wait_lcore();\n\trte_atomic32_set(&synchro, 0);\n\n\tif (rte_atomic16_read(&a16) != 1UL << 10) {\n\t\tprintf(\"Atomic16 usual functions failed\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_atomic32_read(&a32) != 1UL << 10) {\n\t\tprintf(\"Atomic32 usual functions failed\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_atomic64_read(&a64) != 1ULL << 33) {\n\t\tprintf(\"Atomic64 usual functions failed\\n\");\n\t\treturn -1;\n\t}\n\n\tprintf(\"test and set\\n\");\n\n\trte_atomic64_set(&a64, 0);\n\trte_atomic32_set(&a32, 0);\n\trte_atomic16_set(&a16, 0);\n\trte_atomic64_set(&count, 0);\n\trte_eal_mp_remote_launch(test_atomic_tas, NULL, SKIP_MASTER);\n\trte_atomic32_set(&synchro, 1);\n\trte_eal_mp_wait_lcore();\n\trte_atomic32_set(&synchro, 0);\n\n\tif (rte_atomic64_read(&count) != NUM_ATOMIC_TYPES) {\n\t\tprintf(\"Atomic test and set failed\\n\");\n\t\treturn -1;\n\t}\n\n\tprintf(\"add/sub and return\\n\");\n\n\trte_atomic64_set(&a64, 0);\n\trte_atomic32_set(&a32, 0);\n\trte_atomic16_set(&a16, 0);\n\trte_atomic64_set(&count, 0);\n\trte_eal_mp_remote_launch(test_atomic_addsub_and_return, NULL,\n\t\t\t\t SKIP_MASTER);\n\trte_atomic32_set(&synchro, 1);\n\trte_eal_mp_wait_lcore();\n\trte_atomic32_set(&synchro, 0);\n\n\tif (rte_atomic64_read(&count) != 0) {\n\t\tprintf(\"Atomic add/sub+return failed\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * Set a64, a32 and a16 with the same value of minus \"number of slave\n\t * lcores\", launch all slave lcores to atomically increase by one and\n\t * test them respectively.\n\t * Each lcore should have only one chance to increase a64 by one and\n\t * then check if it is equal to 0, but there should be only one lcore\n\t * that finds that it is 0. It is similar for a32 and a16.\n\t * Then a variable of \"count\", initialized to zero, is increased by\n\t * one if a64, a32 or a16 is 0 after being increased and tested\n\t * atomically.\n\t * We can check if \"count\" is finally equal to 3 to see if all slave\n\t * lcores performed \"atomic inc and test\" right.\n\t */\n\tprintf(\"inc and test\\n\");\n\n\trte_atomic64_clear(&a64);\n\trte_atomic32_clear(&a32);\n\trte_atomic16_clear(&a16);\n\trte_atomic32_clear(&synchro);\n\trte_atomic64_clear(&count);\n\n\trte_atomic64_set(&a64, (int64_t)(1 - (int64_t)rte_lcore_count()));\n\trte_atomic32_set(&a32, (int32_t)(1 - (int32_t)rte_lcore_count()));\n\trte_atomic16_set(&a16, (int16_t)(1 - (int16_t)rte_lcore_count()));\n\trte_eal_mp_remote_launch(test_atomic_inc_and_test, NULL, SKIP_MASTER);\n\trte_atomic32_set(&synchro, 1);\n\trte_eal_mp_wait_lcore();\n\trte_atomic32_clear(&synchro);\n\n\tif (rte_atomic64_read(&count) != NUM_ATOMIC_TYPES) {\n\t\tprintf(\"Atomic inc and test failed %d\\n\", (int)count.cnt);\n\t\treturn -1;\n\t}\n\n\t/*\n\t * Same as above, but this time we set the values to \"number of slave\n\t * lcores\", and decrement instead of increment.\n\t */\n\tprintf(\"dec and test\\n\");\n\n\trte_atomic32_clear(&synchro);\n\trte_atomic64_clear(&count);\n\n\trte_atomic64_set(&a64, (int64_t)(rte_lcore_count() - 1));\n\trte_atomic32_set(&a32, (int32_t)(rte_lcore_count() - 1));\n\trte_atomic16_set(&a16, (int16_t)(rte_lcore_count() - 1));\n\trte_eal_mp_remote_launch(test_atomic_dec_and_test, NULL, SKIP_MASTER);\n\trte_atomic32_set(&synchro, 1);\n\trte_eal_mp_wait_lcore();\n\trte_atomic32_clear(&synchro);\n\n\tif (rte_atomic64_read(&count) != NUM_ATOMIC_TYPES) {\n\t\tprintf(\"Atomic dec and test failed\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic struct test_command atomic_cmd = {\n\t.command = \"atomic_autotest\",\n\t.callback = test_atomic,\n};\nREGISTER_TEST_COMMAND(atomic_cmd);\n" }, { "path": "app/test/test_byteorder.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n\n#include \"test.h\"\n\nstatic volatile uint16_t u16 = 0x1337;\nstatic volatile uint32_t u32 = 0xdeadbeefUL;\nstatic volatile uint64_t u64 = 0xdeadcafebabefaceULL;\n\n/*\n * Byteorder functions\n * ===================\n *\n * - check that optimized byte swap functions are working for each\n * size (16, 32, 64 bits)\n */\n\nstatic int\ntest_byteorder(void)\n{\n\tuint16_t res_u16;\n\tuint32_t res_u32;\n\tuint64_t res_u64;\n\n\tres_u16 = rte_bswap16(u16);\n\tprintf(\"%\"PRIx16\" -> %\"PRIx16\"\\n\", u16, res_u16);\n\tif (res_u16 != 0x3713)\n\t\treturn -1;\n\n\tres_u32 = rte_bswap32(u32);\n\tprintf(\"%\"PRIx32\" -> %\"PRIx32\"\\n\", u32, res_u32);\n\tif (res_u32 != 0xefbeaddeUL)\n\t\treturn -1;\n\n\tres_u64 = rte_bswap64(u64);\n\tprintf(\"%\"PRIx64\" -> %\"PRIx64\"\\n\", u64, res_u64);\n\tif (res_u64 != 0xcefabebafecaaddeULL)\n\t\treturn -1;\n\n\tres_u16 = rte_bswap16(0x1337);\n\tprintf(\"const %\"PRIx16\" -> %\"PRIx16\"\\n\", 0x1337, res_u16);\n\tif (res_u16 != 0x3713)\n\t\treturn -1;\n\n\tres_u32 = rte_bswap32(0xdeadbeefUL);\n\tprintf(\"const %\"PRIx32\" -> %\"PRIx32\"\\n\", (uint32_t) 0xdeadbeef, res_u32);\n\tif (res_u32 != 0xefbeaddeUL)\n\t\treturn -1;\n\n\tres_u64 = rte_bswap64(0xdeadcafebabefaceULL);\n\tprintf(\"const %\"PRIx64\" -> %\"PRIx64\"\\n\", (uint64_t) 0xdeadcafebabefaceULL, res_u64);\n\tif (res_u64 != 0xcefabebafecaaddeULL)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic struct test_command byteorder_cmd = {\n\t.command = \"byteorder_autotest\",\n\t.callback = test_byteorder,\n};\nREGISTER_TEST_COMMAND(byteorder_cmd);\n" }, { "path": "app/test/test_cmdline.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \"test.h\"\n#include \"test_cmdline.h\"\n\nstatic int\ntest_cmdline(void)\n{\n\tprintf(\"Testind parsing ethernet addresses...\\n\");\n\tif (test_parse_etheraddr_valid() < 0)\n\t\treturn -1;\n\tif (test_parse_etheraddr_invalid_data() < 0)\n\t\treturn -1;\n\tif (test_parse_etheraddr_invalid_param() < 0)\n\t\treturn -1;\n\tprintf(\"Testind parsing port lists...\\n\");\n\tif (test_parse_portlist_valid() < 0)\n\t\treturn -1;\n\tif (test_parse_portlist_invalid_data() < 0)\n\t\treturn -1;\n\tif (test_parse_portlist_invalid_param() < 0)\n\t\treturn -1;\n\tprintf(\"Testind parsing numbers...\\n\");\n\tif (test_parse_num_valid() < 0)\n\t\treturn -1;\n\tif (test_parse_num_invalid_data() < 0)\n\t\treturn -1;\n\tif (test_parse_num_invalid_param() < 0)\n\t\treturn -1;\n\tprintf(\"Testing parsing IP addresses...\\n\");\n\tif (test_parse_ipaddr_valid() < 0)\n\t\treturn -1;\n\tif (test_parse_ipaddr_invalid_data() < 0)\n\t\treturn -1;\n\tif (test_parse_ipaddr_invalid_param() < 0)\n\t\treturn -1;\n\tprintf(\"Testing parsing strings...\\n\");\n\tif (test_parse_string_valid() < 0)\n\t\treturn -1;\n\tif (test_parse_string_invalid_data() < 0)\n\t\treturn -1;\n\tif (test_parse_string_invalid_param() < 0)\n\t\treturn -1;\n\tprintf(\"Testing circular buffer...\\n\");\n\tif (test_cirbuf_char() < 0)\n\t\treturn -1;\n\tif (test_cirbuf_string() < 0)\n\t\treturn -1;\n\tif (test_cirbuf_align() < 0)\n\t\treturn -1;\n\tif (test_cirbuf_invalid_param() < 0)\n\t\treturn -1;\n\tprintf(\"Testing library functions...\\n\");\n\tif (test_cmdline_lib() < 0)\n\t\treturn -1;\n\treturn 0;\n}\n\nstatic struct test_command cmdline_cmd = {\n\t.command = \"cmdline_autotest\",\n\t.callback = test_cmdline,\n};\nREGISTER_TEST_COMMAND(cmdline_cmd);\n" }, { "path": "app/test/test_cmdline.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef TEST_CMDLINE_H_\n#define TEST_CMDLINE_H_\n\n#define CMDLINE_TEST_BUFSIZE 64\n\n/* cmdline_parse_num tests */\nint test_parse_num_valid(void);\nint test_parse_num_invalid_data(void);\nint test_parse_num_invalid_param(void);\n\n/* cmdline_parse_etheraddr tests */\nint test_parse_etheraddr_valid(void);\nint test_parse_etheraddr_invalid_data(void);\nint test_parse_etheraddr_invalid_param(void);\n\n/* cmdline_parse_portlist tests */\nint test_parse_portlist_valid(void);\nint test_parse_portlist_invalid_data(void);\nint test_parse_portlist_invalid_param(void);\n\n/* cmdline_parse_ipaddr tests */\nint test_parse_ipaddr_valid(void);\nint test_parse_ipaddr_invalid_data(void);\nint test_parse_ipaddr_invalid_param(void);\n\n/* cmdline_parse_string tests */\nint test_parse_string_valid(void);\nint test_parse_string_invalid_data(void);\nint test_parse_string_invalid_param(void);\n\n/* cmdline_cirbuf tests */\nint test_cirbuf_invalid_param(void);\nint test_cirbuf_char(void);\nint test_cirbuf_string(void);\nint test_cirbuf_align(void);\n\n/* test the rest of the library */\nint test_cmdline_lib(void);\n\n#endif /* TEST_CMDLINE_H_ */\n" }, { "path": "app/test/test_cmdline_cirbuf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n\n#include \n\n#include \"test_cmdline.h\"\n\n/* different length strings */\n#define CIRBUF_STR_HEAD \" HEAD\"\n#define CIRBUF_STR_TAIL \"TAIL\"\n\n/* miscelaneous tests - they make bullseye happy */\nstatic int\ntest_cirbuf_string_misc(void)\n{\n\tstruct cirbuf cb;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tchar tmp[CMDLINE_TEST_BUFSIZE];\n\n\t/* initialize buffers */\n\tmemset(buf, 0, sizeof(buf));\n\tmemset(tmp, 0, sizeof(tmp));\n\n\t/*\n\t * initialize circular buffer\n\t */\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to initialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * add strings to head and tail, but read only tail\n\t * this results in read operation that does not transcend\n\t * from buffer end to buffer beginning (in other words,\n\t * strlen <= cb->maxlen - cb->end)\n\t */\n\n\t/* add string to head */\n\tif (cirbuf_add_buf_head(&cb, CIRBUF_STR_HEAD, sizeof(CIRBUF_STR_HEAD))\n\t\t\t!= (sizeof(CIRBUF_STR_HEAD))) {\n\t\tprintf(\"Error: failed to add string to head!\\n\");\n\t\treturn -1;\n\t}\n\t/* add string to tail */\n\tif (cirbuf_add_buf_tail(&cb, CIRBUF_STR_TAIL, sizeof(CIRBUF_STR_TAIL))\n\t\t\t!= (sizeof(CIRBUF_STR_TAIL))) {\n\t\tprintf(\"Error: failed to add string to head!\\n\");\n\t\treturn -1;\n\t}\n\t/* read string from tail */\n\tif (cirbuf_get_buf_tail(&cb, tmp, sizeof(CIRBUF_STR_TAIL))\n\t\t\t!= (sizeof(CIRBUF_STR_TAIL))) {\n\t\tprintf(\"Error: failed to get string from tail!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string */\n\tif (strncmp(tmp, CIRBUF_STR_TAIL, sizeof(CIRBUF_STR_TAIL)) != 0) {\n\t\tprintf(\"Error: tail strings do not match!\\n\");\n\t\treturn -1;\n\t}\n\t/* clear buffers */\n\tmemset(tmp, 0, sizeof(tmp));\n\tmemset(buf, 0, sizeof(buf));\n\n\n\n\t/*\n\t * add a string to buffer when start/end is at end of buffer\n\t */\n\n\t/*\n\t * reinitialize circular buffer with start at the end of cirbuf\n\t */\n\tif (cirbuf_init(&cb, buf, CMDLINE_TEST_BUFSIZE - 2, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\n\t/* add string to tail */\n\tif (cirbuf_add_buf_tail(&cb, CIRBUF_STR_TAIL, sizeof(CIRBUF_STR_TAIL))\n\t\t\t!= (sizeof(CIRBUF_STR_TAIL))) {\n\t\tprintf(\"Error: failed to add string to tail!\\n\");\n\t\treturn -1;\n\t}\n\t/* read string from tail */\n\tif (cirbuf_get_buf_tail(&cb, tmp, sizeof(CIRBUF_STR_TAIL))\n\t\t\t!= (sizeof(CIRBUF_STR_TAIL))) {\n\t\tprintf(\"Error: failed to get string from tail!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string */\n\tif (strncmp(tmp, CIRBUF_STR_TAIL, sizeof(CIRBUF_STR_TAIL)) != 0) {\n\t\tprintf(\"Error: tail strings do not match!\\n\");\n\t\treturn -1;\n\t}\n\t/* clear tmp buffer */\n\tmemset(tmp, 0, sizeof(tmp));\n\n\n\t/* add string to head */\n\tif (cirbuf_add_buf_head(&cb, CIRBUF_STR_HEAD, sizeof(CIRBUF_STR_HEAD))\n\t\t\t!= (sizeof(CIRBUF_STR_HEAD))) {\n\t\tprintf(\"Error: failed to add string to head!\\n\");\n\t\treturn -1;\n\t}\n\t/* read string from tail */\n\tif (cirbuf_get_buf_head(&cb, tmp, sizeof(CIRBUF_STR_HEAD))\n\t\t\t!= (sizeof(CIRBUF_STR_HEAD))) {\n\t\tprintf(\"Error: failed to get string from head!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string */\n\tif (strncmp(tmp, CIRBUF_STR_HEAD, sizeof(CIRBUF_STR_HEAD)) != 0) {\n\t\tprintf(\"Error: headstrings do not match!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* test adding and deleting strings */\nstatic int\ntest_cirbuf_string_add_del(void)\n{\n\tstruct cirbuf cb;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tchar tmp[CMDLINE_TEST_BUFSIZE];\n\n\t/* initialize buffers */\n\tmemset(buf, 0, sizeof(buf));\n\tmemset(tmp, 0, sizeof(tmp));\n\n\t/*\n\t * initialize circular buffer\n\t */\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to initialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* add string to head */\n\tif (cirbuf_add_buf_head(&cb, CIRBUF_STR_HEAD, sizeof(CIRBUF_STR_HEAD))\n\t\t\t!= (sizeof(CIRBUF_STR_HEAD))) {\n\t\tprintf(\"Error: failed to add string to head!\\n\");\n\t\treturn -1;\n\t}\n\t/* read string from head */\n\tif (cirbuf_get_buf_head(&cb, tmp, sizeof(CIRBUF_STR_HEAD))\n\t\t\t!= (sizeof(CIRBUF_STR_HEAD))) {\n\t\tprintf(\"Error: failed to get string from head!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string */\n\tif (strncmp(tmp, CIRBUF_STR_HEAD, sizeof(CIRBUF_STR_HEAD)) != 0) {\n\t\tprintf(\"Error: head strings do not match!\\n\");\n\t\treturn -1;\n\t}\n\t/* clear tmp buffer */\n\tmemset(tmp, 0, sizeof(tmp));\n\t/* read string from tail */\n\tif (cirbuf_get_buf_tail(&cb, tmp, sizeof(CIRBUF_STR_HEAD))\n\t\t\t!= (sizeof(CIRBUF_STR_HEAD))) {\n\t\tprintf(\"Error: failed to get string from head!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string */\n\tif (strncmp(tmp, CIRBUF_STR_HEAD, sizeof(CIRBUF_STR_HEAD)) != 0) {\n\t\tprintf(\"Error: head strings do not match!\\n\");\n\t\treturn -1;\n\t}\n\t/* delete string from head*/\n\tif (cirbuf_del_buf_head(&cb, sizeof(CIRBUF_STR_HEAD)) < 0) {\n\t\tprintf(\"Error: failed to delete string from head!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string was deleted */\n\tif (cirbuf_del_head_safe(&cb) == 0) {\n\t\tprintf(\"Error: buffer should have been empty!\\n\");\n\t\treturn -1;\n\t}\n\t/* clear tmp buffer */\n\tmemset(tmp, 0, sizeof(tmp));\n\n\n\n\t/*\n\t * reinitialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* add string to tail */\n\tif (cirbuf_add_buf_tail(&cb, CIRBUF_STR_TAIL, sizeof(CIRBUF_STR_TAIL))\n\t\t\t!= (sizeof(CIRBUF_STR_TAIL))) {\n\t\tprintf(\"Error: failed to add string to tail!\\n\");\n\t\treturn -1;\n\t}\n\t/* get string from tail */\n\tif (cirbuf_get_buf_tail(&cb, tmp, sizeof(CIRBUF_STR_TAIL))\n\t\t\t!= (sizeof(CIRBUF_STR_TAIL))) {\n\t\tprintf(\"Error: failed to get string from tail!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string */\n\tif (strncmp(tmp, CIRBUF_STR_TAIL, sizeof(CIRBUF_STR_TAIL)) != 0) {\n\t\tprintf(\"Error: tail strings do not match!\\n\");\n\t\treturn -1;\n\t}\n\t/* clear tmp buffer */\n\tmemset(tmp, 0, sizeof(tmp));\n\t/* get string from head */\n\tif (cirbuf_get_buf_head(&cb, tmp, sizeof(CIRBUF_STR_TAIL))\n\t\t\t!= (sizeof(CIRBUF_STR_TAIL))) {\n\t\tprintf(\"Error: failed to get string from tail!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string */\n\tif (strncmp(tmp, CIRBUF_STR_TAIL, sizeof(CIRBUF_STR_TAIL)) != 0) {\n\t\tprintf(\"Error: tail strings do not match!\\n\");\n\t\treturn -1;\n\t}\n\t/* delete string from tail */\n\tif (cirbuf_del_buf_tail(&cb, sizeof(CIRBUF_STR_TAIL)) < 0) {\n\t\tprintf(\"Error: failed to delete string from tail!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string was deleted */\n\tif (cirbuf_del_tail_safe(&cb) == 0) {\n\t\tprintf(\"Error: buffer should have been empty!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* test adding from head and deleting from tail, and vice versa */\nstatic int\ntest_cirbuf_string_add_del_reverse(void)\n{\n\tstruct cirbuf cb;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tchar tmp[CMDLINE_TEST_BUFSIZE];\n\n\t/* initialize buffers */\n\tmemset(buf, 0, sizeof(buf));\n\tmemset(tmp, 0, sizeof(tmp));\n\n\t/*\n\t * initialize circular buffer\n\t */\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to initialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* add string to head */\n\tif (cirbuf_add_buf_head(&cb, CIRBUF_STR_HEAD, sizeof(CIRBUF_STR_HEAD))\n\t\t\t!= (sizeof(CIRBUF_STR_HEAD))) {\n\t\tprintf(\"Error: failed to add string to head!\\n\");\n\t\treturn -1;\n\t}\n\t/* delete string from tail */\n\tif (cirbuf_del_buf_tail(&cb, sizeof(CIRBUF_STR_HEAD)) < 0) {\n\t\tprintf(\"Error: failed to delete string from tail!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string was deleted */\n\tif (cirbuf_del_tail_safe(&cb) == 0) {\n\t\tprintf(\"Error: buffer should have been empty!\\n\");\n\t\treturn -1;\n\t}\n\t/* clear tmp buffer */\n\tmemset(tmp, 0, sizeof(tmp));\n\n\t/*\n\t * reinitialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* add string to tail */\n\tif (cirbuf_add_buf_tail(&cb, CIRBUF_STR_TAIL, sizeof(CIRBUF_STR_TAIL))\n\t\t\t!= (sizeof(CIRBUF_STR_TAIL))) {\n\t\tprintf(\"Error: failed to add string to tail!\\n\");\n\t\treturn -1;\n\t}\n\t/* delete string from head */\n\tif (cirbuf_del_buf_head(&cb, sizeof(CIRBUF_STR_TAIL)) < 0) {\n\t\tprintf(\"Error: failed to delete string from head!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string was deleted */\n\tif (cirbuf_del_head_safe(&cb) == 0) {\n\t\tprintf(\"Error: buffer should have been empty!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* try to write more than available */\nstatic int\ntest_cirbuf_string_add_boundaries(void)\n{\n\tstruct cirbuf cb;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tunsigned i;\n\n\t/* initialize buffers */\n\tmemset(buf, 0, sizeof(buf));\n\n\t/*\n\t * initialize circular buffer\n\t */\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to initialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* fill the buffer from tail */\n\tfor (i = 0; i < CMDLINE_TEST_BUFSIZE - sizeof(CIRBUF_STR_TAIL) + 1; i++)\n\t\tcirbuf_add_tail_safe(&cb, 't');\n\n\t/* try adding a string to tail */\n\tif (cirbuf_add_buf_tail(&cb, CIRBUF_STR_TAIL, sizeof(CIRBUF_STR_TAIL))\n\t\t\t> 0) {\n\t\tprintf(\"Error: buffer should have been full!\\n\");\n\t\treturn -1;\n\t}\n\t/* try adding a string to head */\n\tif (cirbuf_add_buf_head(&cb, CIRBUF_STR_TAIL, sizeof(CIRBUF_STR_TAIL))\n\t\t\t> 0) {\n\t\tprintf(\"Error: buffer should have been full!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * reinitialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* fill the buffer from head */\n\tfor (i = 0; i < CMDLINE_TEST_BUFSIZE - sizeof(CIRBUF_STR_HEAD) + 1; i++)\n\t\tcirbuf_add_head_safe(&cb, 'h');\n\n\t/* try adding a string to head */\n\tif (cirbuf_add_buf_head(&cb, CIRBUF_STR_HEAD, sizeof(CIRBUF_STR_HEAD))\n\t\t\t> 0) {\n\t\tprintf(\"Error: buffer should have been full!\\n\");\n\t\treturn -1;\n\t}\n\t/* try adding a string to tail */\n\tif (cirbuf_add_buf_tail(&cb, CIRBUF_STR_HEAD, sizeof(CIRBUF_STR_HEAD))\n\t\t\t> 0) {\n\t\tprintf(\"Error: buffer should have been full!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* try to read/delete more than written */\nstatic int\ntest_cirbuf_string_get_del_boundaries(void)\n{\n\tstruct cirbuf cb;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tchar tmp[CMDLINE_TEST_BUFSIZE];\n\n\t/* initialize buffers */\n\tmemset(buf, 0, sizeof(buf));\n\tmemset(tmp, 0, sizeof(tmp));\n\n\t/*\n\t * initialize circular buffer\n\t */\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to initialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\n\t/* add string to head */\n\tif (cirbuf_add_buf_head(&cb, CIRBUF_STR_HEAD, sizeof(CIRBUF_STR_HEAD))\n\t\t\t\t!= (sizeof(CIRBUF_STR_HEAD))) {\n\t\tprintf(\"Error: failed to add string to head!\\n\");\n\t\treturn -1;\n\t}\n\t/* read more than written (head) */\n\tif (cirbuf_get_buf_head(&cb, tmp, sizeof(CIRBUF_STR_HEAD) + 1)\n\t\t\t!= sizeof(CIRBUF_STR_HEAD)) {\n\t\tprintf(\"Error: unexpected result when reading too much data!\\n\");\n\t\treturn -1;\n\t}\n\t/* read more than written (tail) */\n\tif (cirbuf_get_buf_tail(&cb, tmp, sizeof(CIRBUF_STR_HEAD) + 1)\n\t\t\t!= sizeof(CIRBUF_STR_HEAD)) {\n\t\tprintf(\"Error: unexpected result when reading too much data!\\n\");\n\t\treturn -1;\n\t}\n\t/* delete more than written (head) */\n\tif (cirbuf_del_buf_head(&cb, sizeof(CIRBUF_STR_HEAD) + 1) == 0) {\n\t\tprintf(\"Error: unexpected result when deleting too much data!\\n\");\n\t\treturn -1;\n\t}\n\t/* delete more than written (tail) */\n\tif (cirbuf_del_buf_tail(&cb, sizeof(CIRBUF_STR_HEAD) + 1) == 0) {\n\t\tprintf(\"Error: unexpected result when deleting too much data!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * reinitialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* add string to tail */\n\tif (cirbuf_add_buf_tail(&cb, CIRBUF_STR_TAIL, sizeof(CIRBUF_STR_TAIL))\n\t\t\t\t!= (sizeof(CIRBUF_STR_TAIL))) {\n\t\tprintf(\"Error: failed to add string to tail!\\n\");\n\t\treturn -1;\n\t}\n\t/* read more than written (tail) */\n\tif (cirbuf_get_buf_tail(&cb, tmp, sizeof(CIRBUF_STR_TAIL) + 1)\n\t\t\t!= sizeof(CIRBUF_STR_TAIL)) {\n\t\tprintf(\"Error: unexpected result when reading too much data!\\n\");\n\t\treturn -1;\n\t}\n\t/* read more than written (head) */\n\tif (cirbuf_get_buf_head(&cb, tmp, sizeof(CIRBUF_STR_TAIL) + 1)\n\t\t\t!= sizeof(CIRBUF_STR_TAIL)) {\n\t\tprintf(\"Error: unexpected result when reading too much data!\\n\");\n\t\treturn -1;\n\t}\n\t/* delete more than written (tail) */\n\tif (cirbuf_del_buf_tail(&cb, sizeof(CIRBUF_STR_TAIL) + 1) == 0) {\n\t\tprintf(\"Error: unexpected result when deleting too much data!\\n\");\n\t\treturn -1;\n\t}\n\t/* delete more than written (head) */\n\tif (cirbuf_del_buf_tail(&cb, sizeof(CIRBUF_STR_TAIL) + 1) == 0) {\n\t\tprintf(\"Error: unexpected result when deleting too much data!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* try to read/delete less than written */\nstatic int\ntest_cirbuf_string_get_del_partial(void)\n{\n\tstruct cirbuf cb;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tchar tmp[CMDLINE_TEST_BUFSIZE];\n\tchar tmp2[CMDLINE_TEST_BUFSIZE];\n\n\t/* initialize buffers */\n\tmemset(buf, 0, sizeof(buf));\n\tmemset(tmp, 0, sizeof(tmp));\n\tmemset(tmp2, 0, sizeof(tmp));\n\n\tsnprintf(tmp2, sizeof(tmp2), \"%s\", CIRBUF_STR_HEAD);\n\n\t/*\n\t * initialize circular buffer\n\t */\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to initialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* add string to head */\n\tif (cirbuf_add_buf_head(&cb, CIRBUF_STR_HEAD, sizeof(CIRBUF_STR_HEAD))\n\t\t\t\t!= (sizeof(CIRBUF_STR_HEAD))) {\n\t\tprintf(\"Error: failed to add string to head!\\n\");\n\t\treturn -1;\n\t}\n\t/* read less than written (head) */\n\tif (cirbuf_get_buf_head(&cb, tmp, sizeof(CIRBUF_STR_HEAD) - 1)\n\t\t\t!= sizeof(CIRBUF_STR_HEAD) - 1) {\n\t\tprintf(\"Error: unexpected result when reading from head!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string */\n\tif (strncmp(tmp, tmp2, sizeof(CIRBUF_STR_HEAD) - 1) != 0) {\n\t\tprintf(\"Error: strings mismatch!\\n\");\n\t\treturn -1;\n\t}\n\tmemset(tmp, 0, sizeof(tmp));\n\t/* read less than written (tail) */\n\tif (cirbuf_get_buf_tail(&cb, tmp, sizeof(CIRBUF_STR_HEAD) - 1)\n\t\t\t!= sizeof(CIRBUF_STR_HEAD) - 1) {\n\t\tprintf(\"Error: unexpected result when reading from tail!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string */\n\tif (strncmp(tmp, &tmp2[1], sizeof(CIRBUF_STR_HEAD) - 1) != 0) {\n\t\tprintf(\"Error: strings mismatch!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * verify correct deletion\n\t */\n\n\t/* clear buffer */\n\tmemset(tmp, 0, sizeof(tmp));\n\n\t/* delete less than written (head) */\n\tif (cirbuf_del_buf_head(&cb, 1) != 0) {\n\t\tprintf(\"Error: delete from head failed!\\n\");\n\t\treturn -1;\n\t}\n\t/* read from head */\n\tif (cirbuf_get_buf_head(&cb, tmp, sizeof(CIRBUF_STR_HEAD) - 1)\n\t\t\t!= sizeof(CIRBUF_STR_HEAD) - 1) {\n\t\tprintf(\"Error: unexpected result when reading from head!\\n\");\n\t\treturn -1;\n\t}\n\t/* since we deleted from head, first char should be deleted */\n\tif (strncmp(tmp, &tmp2[1], sizeof(CIRBUF_STR_HEAD) - 1) != 0) {\n\t\tprintf(\"Error: strings mismatch!\\n\");\n\t\treturn -1;\n\t}\n\t/* clear buffer */\n\tmemset(tmp, 0, sizeof(tmp));\n\n\t/* delete less than written (tail) */\n\tif (cirbuf_del_buf_tail(&cb, 1) != 0) {\n\t\tprintf(\"Error: delete from tail failed!\\n\");\n\t\treturn -1;\n\t}\n\t/* read from tail */\n\tif (cirbuf_get_buf_tail(&cb, tmp, sizeof(CIRBUF_STR_HEAD) - 2)\n\t\t\t!= sizeof(CIRBUF_STR_HEAD) - 2) {\n\t\tprintf(\"Error: unexpected result when reading from head!\\n\");\n\t\treturn -1;\n\t}\n\t/* since we deleted from tail, last char should be deleted */\n\tif (strncmp(tmp, &tmp2[1], sizeof(CIRBUF_STR_HEAD) - 2) != 0) {\n\t\tprintf(\"Error: strings mismatch!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* test cmdline_cirbuf char add/del functions */\nstatic int\ntest_cirbuf_char_add_del(void)\n{\n\tstruct cirbuf cb;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tchar tmp[CMDLINE_TEST_BUFSIZE];\n\n\t/* clear buffer */\n\tmemset(buf, 0, sizeof(buf));\n\tmemset(tmp, 0, sizeof(tmp));\n\n\t/*\n\t * initialize circular buffer\n\t */\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to initialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * try to delete something from cirbuf. since it's empty,\n\t * these should fail.\n\t */\n\tif (cirbuf_del_head_safe(&cb) == 0) {\n\t\tprintf(\"Error: deleting from empty cirbuf head succeeded!\\n\");\n\t\treturn -1;\n\t}\n\tif (cirbuf_del_tail_safe(&cb) == 0) {\n\t\tprintf(\"Error: deleting from empty cirbuf tail succeeded!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * add, verify and delete. these should pass.\n\t */\n\tif (cirbuf_add_head_safe(&cb,'h') < 0) {\n\t\tprintf(\"Error: adding to cirbuf head failed!\\n\");\n\t\treturn -1;\n\t}\n\tif (cirbuf_get_head(&cb) != 'h') {\n\t\tprintf(\"Error: wrong head content!\\n\");\n\t\treturn -1;\n\t}\n\tif (cirbuf_del_head_safe(&cb) < 0) {\n\t\tprintf(\"Error: deleting from cirbuf head failed!\\n\");\n\t\treturn -1;\n\t}\n\tif (cirbuf_add_tail_safe(&cb,'t') < 0) {\n\t\tprintf(\"Error: adding to cirbuf tail failed!\\n\");\n\t\treturn -1;\n\t}\n\tif (cirbuf_get_tail(&cb) != 't') {\n\t\tprintf(\"Error: wrong tail content!\\n\");\n\t\treturn -1;\n\t}\n\tif (cirbuf_del_tail_safe(&cb) < 0) {\n\t\tprintf(\"Error: deleting from cirbuf tail failed!\\n\");\n\t\treturn -1;\n\t}\n\t/* do the same for unsafe versions. those are void. */\n\tcirbuf_add_head(&cb,'h');\n\tif (cirbuf_get_head(&cb) != 'h') {\n\t\tprintf(\"Error: wrong head content!\\n\");\n\t\treturn -1;\n\t}\n\tcirbuf_del_head(&cb);\n\n\t/* test if char has been deleted. we can't call cirbuf_get_head\n\t * because it's unsafe, but we can call cirbuf_get_buf_head.\n\t */\n\tif (cirbuf_get_buf_head(&cb, tmp, 1) > 0) {\n\t\tprintf(\"Error: buffer should have been empty!\\n\");\n\t\treturn -1;\n\t}\n\n\tcirbuf_add_tail(&cb,'t');\n\tif (cirbuf_get_tail(&cb) != 't') {\n\t\tprintf(\"Error: wrong tail content!\\n\");\n\t\treturn -1;\n\t}\n\tcirbuf_del_tail(&cb);\n\n\t/* test if char has been deleted. we can't call cirbuf_get_tail\n\t * because it's unsafe, but we can call cirbuf_get_buf_tail.\n\t */\n\tif (cirbuf_get_buf_tail(&cb, tmp, 1) > 0) {\n\t\tprintf(\"Error: buffer should have been empty!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* test filling up buffer with chars */\nstatic int\ntest_cirbuf_char_fill(void)\n{\n\tstruct cirbuf cb;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tunsigned i;\n\n\t/* clear buffer */\n\tmemset(buf, 0, sizeof(buf));\n\n\t/*\n\t * initialize circular buffer\n\t */\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to initialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * fill the buffer from head or tail, verify contents, test boundaries\n\t * and clear the buffer\n\t */\n\n\t/* fill the buffer from tail */\n\tfor (i = 0; i < CMDLINE_TEST_BUFSIZE; i++)\n\t\tcirbuf_add_tail_safe(&cb, 't');\n\t/* verify that contents of the buffer are what they are supposed to be */\n\tfor (i = 0; i < sizeof(buf); i++) {\n\t\tif (buf[i] != 't') {\n\t\t\tprintf(\"Error: wrong content in buffer!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\t/* try to add to a full buffer from tail */\n\tif (cirbuf_add_tail_safe(&cb, 't') == 0) {\n\t\tprintf(\"Error: buffer should have been full!\\n\");\n\t\treturn -1;\n\t}\n\t/* try to add to a full buffer from head */\n\tif (cirbuf_add_head_safe(&cb, 'h') == 0) {\n\t\tprintf(\"Error: buffer should have been full!\\n\");\n\t\treturn -1;\n\t}\n\t/* delete buffer from tail */\n\tfor(i = 0; i < CMDLINE_TEST_BUFSIZE; i++)\n\t\tcirbuf_del_tail_safe(&cb);\n\t/* try to delete from an empty buffer */\n\tif (cirbuf_del_tail_safe(&cb) >= 0) {\n\t\tprintf(\"Error: buffer should have been empty!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* fill the buffer from head */\n\tfor (i = 0; i < CMDLINE_TEST_BUFSIZE; i++)\n\t\tcirbuf_add_head_safe(&cb, 'h');\n\t/* verify that contents of the buffer are what they are supposed to be */\n\tfor (i = 0; i < sizeof(buf); i++) {\n\t\tif (buf[i] != 'h') {\n\t\t\tprintf(\"Error: wrong content in buffer!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\t/* try to add to a full buffer from head */\n\tif (cirbuf_add_head_safe(&cb,'h') >= 0) {\n\t\tprintf(\"Error: buffer should have been full!\\n\");\n\t\treturn -1;\n\t}\n\t/* try to add to a full buffer from tail */\n\tif (cirbuf_add_tail_safe(&cb, 't') == 0) {\n\t\tprintf(\"Error: buffer should have been full!\\n\");\n\t\treturn -1;\n\t}\n\t/* delete buffer from head */\n\tfor(i = 0; i < CMDLINE_TEST_BUFSIZE; i++)\n\t\tcirbuf_del_head_safe(&cb);\n\t/* try to delete from an empty buffer */\n\tif (cirbuf_del_head_safe(&cb) >= 0) {\n\t\tprintf(\"Error: buffer should have been empty!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * fill the buffer from both head and tail, with alternating characters,\n\t * verify contents and clear the buffer\n\t */\n\n\t/* fill half of buffer from tail */\n\tfor (i = 0; i < CMDLINE_TEST_BUFSIZE / 2; i++)\n\t\tcirbuf_add_tail_safe(&cb, (char) (i % 2 ? 't' : 'T'));\n\t/* fill other half of the buffer from head */\n\tfor (i = 0; i < CMDLINE_TEST_BUFSIZE / 2; i++)\n\t\tcirbuf_add_head_safe(&cb, (char) (i % 2 ? 'H' : 'h')); /* added in reverse */\n\n\t/* verify that contents of the buffer are what they are supposed to be */\n\tfor (i = 0; i < sizeof(buf) / 2; i++) {\n\t\tif (buf[i] != (char) (i % 2 ? 't' : 'T')) {\n\t\t\tprintf(\"Error: wrong content in buffer at %u!\\n\", i);\n\t\t\treturn -1;\n\t\t}\n\t}\n\tfor (i = sizeof(buf) / 2; i < sizeof(buf); i++) {\n\t\tif (buf[i] != (char) (i % 2 ? 'h' : 'H')) {\n\t\t\tprintf(\"Error: wrong content in buffer %u!\\n\", i);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/* test left alignment */\nstatic int\ntest_cirbuf_align_left(void)\n{\n#define HALF_OFFSET CMDLINE_TEST_BUFSIZE / 2\n#define SMALL_OFFSET HALF_OFFSET / 2\n/* resulting buffer lengths for each of the test cases */\n#define LEN1 HALF_OFFSET - SMALL_OFFSET - 1\n#define LEN2 HALF_OFFSET + SMALL_OFFSET + 2\n#define LEN3 HALF_OFFSET - SMALL_OFFSET\n#define LEN4 HALF_OFFSET + SMALL_OFFSET - 1\n\n\tstruct cirbuf cb;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tchar tmp[CMDLINE_TEST_BUFSIZE];\n\tunsigned i;\n\n\t/*\n\t * align left when start < end and start in left half\n\t */\n\n\t/*\n\t * initialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to initialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* push end into left half */\n\tfor (i = 0; i < HALF_OFFSET - 1; i++)\n\t\tcirbuf_add_tail_safe(&cb, 't');\n\n\t/* push start into left half < end */\n\tfor (i = 0; i < SMALL_OFFSET; i++)\n\t\tcirbuf_del_head_safe(&cb);\n\n\t/* align */\n\tif (cirbuf_align_left(&cb) < 0) {\n\t\tprintf(\"Error: alignment failed!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* verify result */\n\tif (cb.start != 0 || cb.len != LEN1 || cb.end != cb.len - 1) {\n\t\tprintf(\"Error: buffer alignment is wrong!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * align left when start > end and start in left half\n\t */\n\n\t/*\n\t * reinitialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* push start into left half */\n\tfor (i = 0; i < HALF_OFFSET + 2; i++)\n\t\tcirbuf_add_head_safe(&cb, 'h');\n\n\t/* push end into left half > start */\n\tfor (i = 0; i < SMALL_OFFSET; i++)\n\t\tcirbuf_add_tail_safe(&cb, 't');\n\n\t/* align */\n\tif (cirbuf_align_left(&cb) < 0) {\n\t\tprintf(\"Error: alignment failed!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* verify result */\n\tif (cb.start != 0 || cb.len != LEN2 || cb.end != cb.len - 1) {\n\t\tprintf(\"Error: buffer alignment is wrong!\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * align left when start < end and start in right half\n\t */\n\n\t/*\n\t * reinitialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* push start into the right half */\n\tfor (i = 0; i < HALF_OFFSET; i++)\n\t\tcirbuf_add_head_safe(&cb, 'h');\n\n\t/* push end into left half > start */\n\tfor (i = 0; i < SMALL_OFFSET; i++)\n\t\tcirbuf_del_tail_safe(&cb);\n\n\t/* align */\n\tif (cirbuf_align_left(&cb) < 0) {\n\t\tprintf(\"Error: alignment failed!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* verify result */\n\tif (cb.start != 0 || cb.len != LEN3 || cb.end != cb.len - 1) {\n\t\tprintf(\"Error: buffer alignment is wrong!\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * align left when start > end and start in right half\n\t */\n\n\t/*\n\t * reinitialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* push start into the right half */\n\tfor (i = 0; i < HALF_OFFSET - 1; i++)\n\t\tcirbuf_add_head_safe(&cb, 'h');\n\n\t/* push end into left half < start */\n\tfor (i = 0; i < SMALL_OFFSET; i++)\n\t\tcirbuf_add_tail_safe(&cb, 't');\n\n\t/* align */\n\tif (cirbuf_align_left(&cb) < 0) {\n\t\tprintf(\"Error: alignment failed!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* verify result */\n\tif (cb.start != 0 || cb.len != LEN4 ||\n\t\t\tcb.end != cb.len - 1) {\n\t\tprintf(\"Error: buffer alignment is wrong!\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * Verify that alignment doesn't corrupt data\n\t */\n\n\t/*\n\t * reinitialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* add string to tail and head */\n\tif (cirbuf_add_buf_head(&cb, CIRBUF_STR_HEAD,\n\t\t\tsizeof(CIRBUF_STR_HEAD)) < 0 || cirbuf_add_buf_tail(&cb,\n\t\t\t\t\tCIRBUF_STR_TAIL, sizeof(CIRBUF_STR_TAIL)) < 0) {\n\t\tprintf(\"Error: failed to add strings!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* align */\n\tif (cirbuf_align_left(&cb) < 0) {\n\t\tprintf(\"Error: alignment failed!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* get string from head */\n\tif (cirbuf_get_buf_head(&cb, tmp,\n\t\t\tsizeof(CIRBUF_STR_HEAD) + sizeof(CIRBUF_STR_TAIL)) < 0) {\n\t\tprintf(\"Error: failed to read string from head!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* verify string */\n\tif (strncmp(tmp, CIRBUF_STR_HEAD \"\\0\" CIRBUF_STR_TAIL,\n\t\t\tsizeof(CIRBUF_STR_HEAD) + sizeof(CIRBUF_STR_TAIL)) != 0) {\n\t\tprintf(\"Error: strings mismatch!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* reset tmp buffer */\n\tmemset(tmp, 0, sizeof(tmp));\n\n\t/* get string from tail */\n\tif (cirbuf_get_buf_tail(&cb, tmp,\n\t\t\tsizeof(CIRBUF_STR_HEAD) + sizeof(CIRBUF_STR_TAIL)) < 0) {\n\t\tprintf(\"Error: failed to read string from head!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* verify string */\n\tif (strncmp(tmp, CIRBUF_STR_HEAD \"\\0\" CIRBUF_STR_TAIL,\n\t\t\tsizeof(CIRBUF_STR_HEAD) + sizeof(CIRBUF_STR_TAIL)) != 0) {\n\t\tprintf(\"Error: strings mismatch!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* test right alignment */\nstatic int\ntest_cirbuf_align_right(void)\n{\n#define END_OFFSET CMDLINE_TEST_BUFSIZE - 1\n\tstruct cirbuf cb;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tchar tmp[CMDLINE_TEST_BUFSIZE];\n\tunsigned i;\n\n\n\t/*\n\t * align right when start < end and start in left half\n\t */\n\n\t/*\n\t * initialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to initialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* push end into left half */\n\tfor (i = 0; i < HALF_OFFSET - 1; i++)\n\t\tcirbuf_add_tail_safe(&cb, 't');\n\n\t/* push start into left half < end */\n\tfor (i = 0; i < SMALL_OFFSET; i++)\n\t\tcirbuf_del_head_safe(&cb);\n\n\t/* align */\n\tcirbuf_align_right(&cb);\n\n\t/* verify result */\n\tif (cb.start != END_OFFSET || cb.len != LEN1 || cb.end != cb.len - 2) {\n\t\tprintf(\"Error: buffer alignment is wrong!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * align right when start > end and start in left half\n\t */\n\n\t/*\n\t * reinitialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* push start into left half */\n\tfor (i = 0; i < HALF_OFFSET + 2; i++)\n\t\tcirbuf_add_head_safe(&cb, 'h');\n\n\t/* push end into left half > start */\n\tfor (i = 0; i < SMALL_OFFSET; i++)\n\t\tcirbuf_add_tail_safe(&cb, 't');\n\n\t/* align */\n\tcirbuf_align_right(&cb);\n\n\t/* verify result */\n\tif (cb.start != END_OFFSET || cb.len != LEN2 || cb.end != cb.len - 2) {\n\t\tprintf(\"Error: buffer alignment is wrong!\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * align right when start < end and start in right half\n\t */\n\n\t/*\n\t * reinitialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* push start into the right half */\n\tfor (i = 0; i < HALF_OFFSET; i++)\n\t\tcirbuf_add_head_safe(&cb, 'h');\n\n\t/* push end into left half > start */\n\tfor (i = 0; i < SMALL_OFFSET; i++)\n\t\tcirbuf_del_tail_safe(&cb);\n\n\t/* align */\n\tcirbuf_align_right(&cb);\n\n\t/* verify result */\n\tif (cb.end != END_OFFSET || cb.len != LEN3 || cb.start != cb.end - cb.len + 1) {\n\t\tprintf(\"Error: buffer alignment is wrong!\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * align right when start > end and start in right half\n\t */\n\n\t/*\n\t * reinitialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* push start into the right half */\n\tfor (i = 0; i < HALF_OFFSET - 1; i++)\n\t\tcirbuf_add_head_safe(&cb, 'h');\n\n\t/* push end into left half < start */\n\tfor (i = 0; i < SMALL_OFFSET; i++)\n\t\tcirbuf_add_tail_safe(&cb, 't');\n\n\t/* align */\n\tcirbuf_align_right(&cb);\n\n\t/* verify result */\n\tif (cb.end != END_OFFSET || cb.len != LEN4 || cb.start != cb.end - cb.len + 1) {\n\t\tprintf(\"Error: buffer alignment is wrong!\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * Verify that alignment doesn't corrupt data\n\t */\n\n\t/*\n\t * reinitialize circular buffer\n\t */\n\tmemset(buf, 0, sizeof(buf));\n\tif (cirbuf_init(&cb, buf, 0, sizeof(buf)) < 0) {\n\t\tprintf(\"Error: failed to reinitialize circular buffer!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* add string to tail and head */\n\tif (cirbuf_add_buf_tail(&cb, CIRBUF_STR_TAIL,\n\t\t\tsizeof(CIRBUF_STR_TAIL)) < 0 || cirbuf_add_buf_head(&cb,\n\t\t\t\t\tCIRBUF_STR_HEAD, sizeof(CIRBUF_STR_HEAD)) < 0) {\n\t\tprintf(\"Error: failed to add strings!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* align */\n\tif (cirbuf_align_right(&cb) < 0) {\n\t\tprintf(\"Error: alignment failed!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* get string from head */\n\tif (cirbuf_get_buf_head(&cb, tmp,\n\t\t\tsizeof(CIRBUF_STR_HEAD) + sizeof(CIRBUF_STR_TAIL)) < 0) {\n\t\tprintf(\"Error: failed to read string from head!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* verify string */\n\tif (strncmp(tmp, CIRBUF_STR_HEAD \"\\0\" CIRBUF_STR_TAIL,\n\t\t\tsizeof(CIRBUF_STR_HEAD) + sizeof(CIRBUF_STR_TAIL)) != 0) {\n\t\tprintf(\"Error: strings mismatch!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* reset tmp buffer */\n\tmemset(tmp, 0, sizeof(tmp));\n\n\t/* get string from tail */\n\tif (cirbuf_get_buf_tail(&cb, tmp,\n\t\t\tsizeof(CIRBUF_STR_HEAD) + sizeof(CIRBUF_STR_TAIL)) < 0) {\n\t\tprintf(\"Error: failed to read string from head!\\n\");\n\t\treturn -1;\n\t}\n\t/* verify string */\n\tif (strncmp(tmp, CIRBUF_STR_HEAD \"\\0\" CIRBUF_STR_TAIL,\n\t\t\tsizeof(CIRBUF_STR_HEAD) + sizeof(CIRBUF_STR_TAIL)) != 0) {\n\t\tprintf(\"Error: strings mismatch!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* call functions with invalid parameters */\nint\ntest_cirbuf_invalid_param(void)\n{\n\tstruct cirbuf cb;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\n\t/* null cirbuf */\n\tif (cirbuf_init(0, buf, 0, sizeof(buf)) == 0)\n\t\treturn -1;\n\t/* null buffer */\n\tif (cirbuf_init(&cb, 0, 0, sizeof(buf)) == 0)\n\t\treturn -1;\n\t/* null cirbuf */\n\tif (cirbuf_add_head_safe(0, 'h') == 0)\n\t\treturn -1;\n\tif (cirbuf_add_tail_safe(0, 't') == 0)\n\t\treturn -1;\n\tif (cirbuf_del_head_safe(0) == 0)\n\t\treturn -1;\n\tif (cirbuf_del_tail_safe(0) == 0)\n\t\treturn -1;\n\t/* null buffer */\n\tif (cirbuf_add_buf_head(&cb, 0, 0) == 0)\n\t\treturn -1;\n\tif (cirbuf_add_buf_tail(&cb, 0, 0) == 0)\n\t\treturn -1;\n\t/* null cirbuf */\n\tif (cirbuf_add_buf_head(0, buf, 0) == 0)\n\t\treturn -1;\n\tif (cirbuf_add_buf_tail(0, buf, 0) == 0)\n\t\treturn -1;\n\t/* null size */\n\tif (cirbuf_add_buf_head(&cb, buf, 0) == 0)\n\t\treturn -1;\n\tif (cirbuf_add_buf_tail(&cb, buf, 0) == 0)\n\t\treturn -1;\n\t/* null cirbuf */\n\tif (cirbuf_del_buf_head(0, 0) == 0)\n\t\treturn -1;\n\tif (cirbuf_del_buf_tail(0, 0) == 0)\n\t\treturn -1;\n\t/* null size */\n\tif (cirbuf_del_buf_head(&cb, 0) == 0)\n\t\treturn -1;\n\tif (cirbuf_del_buf_tail(&cb, 0) == 0)\n\t\treturn -1;\n\t/* null cirbuf */\n\tif (cirbuf_get_buf_head(0, 0, 0) == 0)\n\t\treturn -1;\n\tif (cirbuf_get_buf_tail(0, 0, 0) == 0)\n\t\treturn -1;\n\t/* null buffer */\n\tif (cirbuf_get_buf_head(&cb, 0, 0) == 0)\n\t\treturn -1;\n\tif (cirbuf_get_buf_tail(&cb, 0, 0) == 0)\n\t\treturn -1;\n\t/* null size, this is valid but should return 0 */\n\tif (cirbuf_get_buf_head(&cb, buf, 0) != 0)\n\t\treturn -1;\n\tif (cirbuf_get_buf_tail(&cb, buf, 0) != 0)\n\t\treturn -1;\n\t/* null cirbuf */\n\tif (cirbuf_align_left(0) == 0)\n\t\treturn -1;\n\tif (cirbuf_align_right(0) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/* test cmdline_cirbuf char functions */\nint\ntest_cirbuf_char(void)\n{\n\tint ret;\n\n\tret = test_cirbuf_char_add_del();\n\tif (ret < 0)\n\t\treturn -1;\n\n\tret = test_cirbuf_char_fill();\n\tif (ret < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/* test cmdline_cirbuf string functions */\nint\ntest_cirbuf_string(void)\n{\n\tif (test_cirbuf_string_add_del() < 0)\n\t\treturn -1;\n\n\tif (test_cirbuf_string_add_del_reverse() < 0)\n\t\treturn -1;\n\n\tif (test_cirbuf_string_add_boundaries() < 0)\n\t\treturn -1;\n\n\tif (test_cirbuf_string_get_del_boundaries() < 0)\n\t\treturn -1;\n\n\tif (test_cirbuf_string_get_del_partial() < 0)\n\t\treturn -1;\n\n\tif (test_cirbuf_string_misc() < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/* test cmdline_cirbuf align functions */\nint\ntest_cirbuf_align(void)\n{\n\tif (test_cirbuf_align_left() < 0)\n\t\treturn -1;\n\tif (test_cirbuf_align_right() < 0)\n\t\treturn -1;\n\treturn 0;\n}\n" }, { "path": "app/test/test_cmdline_etheraddr.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n\n#include \n#include \n\n#include \"test_cmdline.h\"\n\nstruct ether_addr_str {\n\tconst char * str;\n\tuint64_t address;\n};\n\n/* valid strings */\nconst struct ether_addr_str ether_addr_valid_strs[] = {\n\t\t{\"01:23:45:67:89:AB\", 0xAB8967452301ULL},\n\t\t{\"4567:89AB:CDEF\", 0xEFCDAB896745ULL},\n};\n\n/* valid strings with various garbage at the end.\n * these strings are still valid because parser checks for\n * end of token, which is either space chars, null char or\n * a hash sign.\n */\nconst char * ether_addr_garbage_strs[] = {\n\t\t\"00:11:22:33:44:55\\0garbage\",\n\t\t\"00:11:22:33:44:55#garbage\",\n\t\t\"00:11:22:33:44:55 garbage\",\n\t\t\"00:11:22:33:44:55\\tgarbage\",\n\t\t\"00:11:22:33:44:55\\ngarbage\",\n\t\t\"00:11:22:33:44:55\\rgarbage\",\n\t\t\"00:11:22:33:44:55#\",\n\t\t\"00:11:22:33:44:55 \",\n\t\t\"00:11:22:33:44:55\\t\",\n\t\t\"00:11:22:33:44:55\\n\",\n\t\t\"00:11:22:33:44:55\\r\",\n};\n#define GARBAGE_ETHERADDR 0x554433221100ULL /* corresponding address */\n\n\nconst char * ether_addr_invalid_strs[] = {\n\t\t/* valid chars, invalid syntax */\n\t\t\"0123:45:67:89:AB\",\n\t\t\"01:23:4567:89:AB\",\n\t\t\"01:23:45:67:89AB\",\n\t\t\"012:345:678:9AB\",\n\t\t\"01:23:45:67:89:ABC\",\n\t\t\"01:23:45:67:89:A\",\n\t\t\"01:23:45:67:89\",\n\t\t\"01:23:45:67:89:AB:CD\",\n\t\t/* invalid chars, valid syntax */\n\t\t\"IN:VA:LI:DC:HA:RS\",\n\t\t\"INVA:LIDC:HARS\",\n\t\t/* misc */\n\t\t\"01 23 45 67 89 AB\",\n\t\t\"01.23.45.67.89.AB\",\n\t\t\"01,23,45,67,89,AB\",\n\t\t\"01:23:45\\0:67:89:AB\",\n\t\t\"01:23:45#:67:89:AB\",\n\t\t\"random invalid text\",\n\t\t\"random text\",\n\t\t\"\",\n\t\t\"\\0\",\n\t\t\" \",\n};\n\n#define ETHERADDR_VALID_STRS_SIZE \\\n\t(sizeof(ether_addr_valid_strs) / sizeof(ether_addr_valid_strs[0]))\n#define ETHERADDR_GARBAGE_STRS_SIZE \\\n\t(sizeof(ether_addr_garbage_strs) / sizeof(ether_addr_garbage_strs[0]))\n#define ETHERADDR_INVALID_STRS_SIZE \\\n\t(sizeof(ether_addr_invalid_strs) / sizeof(ether_addr_invalid_strs[0]))\n\n\n\nstatic int\nis_addr_different(const struct ether_addr addr, uint64_t num)\n{\n\tint i;\n\tfor (i = 0; i < ETHER_ADDR_LEN; i++, num >>= 8)\n\t\tif (addr.addr_bytes[i] != (num & 0xFF)) {\n\t\t\treturn 1;\n\t\t}\n\treturn 0;\n}\n\n/* test invalid parameters */\nint\ntest_parse_etheraddr_invalid_param(void)\n{\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tstruct ether_addr result;\n\tint ret = 0;\n\n\t/* try all null */\n\tret = cmdline_parse_etheraddr(NULL, NULL, NULL, 0);\n\tif (ret != -1) {\n\t\tprintf(\"Error: parser accepted null parameters!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* try null buf */\n\tret = cmdline_parse_etheraddr(NULL, NULL, (void*)&result,\n\t\tsizeof(result));\n\tif (ret != -1) {\n\t\tprintf(\"Error: parser accepted null string!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* try null result */\n\n\t/* copy string to buffer */\n\tsnprintf(buf, sizeof(buf), \"%s\",\n\t\t\tether_addr_valid_strs[0].str);\n\n\tret = cmdline_parse_etheraddr(NULL, buf, NULL, 0);\n\tif (ret == -1) {\n\t\tprintf(\"Error: parser rejected null result!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* token is not used in ether_parse anyway so there's no point in\n\t * testing it */\n\n\t/* test help function */\n\tmemset(&buf, 0, sizeof(buf));\n\n\t/* coverage! */\n\tret = cmdline_get_help_etheraddr(NULL, buf, sizeof(buf));\n\tif (ret < 0) {\n\t\tprintf(\"Error: help function failed with valid parameters!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* test valid parameters but invalid data */\nint\ntest_parse_etheraddr_invalid_data(void)\n{\n\tint ret = 0;\n\tunsigned i;\n\tstruct ether_addr result;\n\n\t/* test full strings */\n\tfor (i = 0; i < ETHERADDR_INVALID_STRS_SIZE; i++) {\n\n\t\tmemset(&result, 0, sizeof(struct ether_addr));\n\n\t\tret = cmdline_parse_etheraddr(NULL, ether_addr_invalid_strs[i],\n\t\t\t(void*)&result, sizeof(result));\n\t\tif (ret != -1) {\n\t\t\tprintf(\"Error: parsing %s succeeded!\\n\",\n\t\t\t\t\tether_addr_invalid_strs[i]);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/* test valid parameters and data */\nint\ntest_parse_etheraddr_valid(void)\n{\n\tint ret = 0;\n\tunsigned i;\n\tstruct ether_addr result;\n\n\t/* test full strings */\n\tfor (i = 0; i < ETHERADDR_VALID_STRS_SIZE; i++) {\n\n\t\tmemset(&result, 0, sizeof(struct ether_addr));\n\n\t\tret = cmdline_parse_etheraddr(NULL, ether_addr_valid_strs[i].str,\n\t\t\t(void*)&result, sizeof(result));\n\t\tif (ret < 0) {\n\t\t\tprintf(\"Error: parsing %s failed!\\n\",\n\t\t\t\t\tether_addr_valid_strs[i].str);\n\t\t\treturn -1;\n\t\t}\n\t\tif (is_addr_different(result, ether_addr_valid_strs[i].address)) {\n\t\t\tprintf(\"Error: parsing %s failed: address mismatch!\\n\",\n\t\t\t\t\tether_addr_valid_strs[i].str);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* test garbage strings */\n\tfor (i = 0; i < ETHERADDR_GARBAGE_STRS_SIZE; i++) {\n\n\t\tmemset(&result, 0, sizeof(struct ether_addr));\n\n\t\tret = cmdline_parse_etheraddr(NULL, ether_addr_garbage_strs[i],\n\t\t\t(void*)&result, sizeof(result));\n\t\tif (ret < 0) {\n\t\t\tprintf(\"Error: parsing %s failed!\\n\",\n\t\t\t\t\tether_addr_garbage_strs[i]);\n\t\t\treturn -1;\n\t\t}\n\t\tif (is_addr_different(result, GARBAGE_ETHERADDR)) {\n\t\t\tprintf(\"Error: parsing %s failed: address mismatch!\\n\",\n\t\t\t\t\tether_addr_garbage_strs[i]);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n" }, { "path": "app/test/test_cmdline_ipaddr.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#ifndef __linux__\n#ifndef __FreeBSD__\n#include \n#else\n#include \n#endif\n#endif\n\n#include \n\n#include \n#include \n\n#include \"test_cmdline.h\"\n\n#define IP4(a,b,c,d) {((uint32_t)(((a) & 0xff)) | \\\n\t\t\t\t\t (((b) & 0xff) << 8) | \\\n\t\t\t\t\t (((c) & 0xff) << 16) | \\\n\t\t\t\t\t ((d) & 0xff) << 24)}\n\n#define U16_SWAP(x) \\\n\t\t(((x & 0xFF) << 8) | ((x & 0xFF00) >> 8))\n\n/* create IPv6 address, swapping bytes where needed */\n#ifndef s6_addr16\n# define s6_addr16 __u6_addr.__u6_addr16\n#endif\n#define IP6(a,b,c,d,e,f,g,h) .ipv6 = \\\n\t\t{.s6_addr16 = \\\n\t\t{U16_SWAP(a),U16_SWAP(b),U16_SWAP(c),U16_SWAP(d),\\\n\t\t U16_SWAP(e),U16_SWAP(f),U16_SWAP(g),U16_SWAP(h)}}\n\n/** these are defined in netinet/in.h but not present in linux headers */\n#ifndef NIPQUAD\n\n#define NIPQUAD_FMT \"%u.%u.%u.%u\"\n#define NIPQUAD(addr)\t\t\t\t\\\n\t(unsigned)((unsigned char *)&addr)[0],\t\\\n\t(unsigned)((unsigned char *)&addr)[1],\t\\\n\t(unsigned)((unsigned char *)&addr)[2],\t\\\n\t(unsigned)((unsigned char *)&addr)[3]\n\n#define NIP6_FMT \"%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x\"\n#define NIP6(addr)\t\t\t\t\t\\\n\t(unsigned)((addr).s6_addr[0]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[1]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[2]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[3]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[4]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[5]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[6]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[7]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[8]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[9]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[10]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[11]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[12]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[13]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[14]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[15])\n\n#endif\n\n\n\nstruct ipaddr_str {\n\tconst char * str;\n\tcmdline_ipaddr_t addr;\n\tunsigned flags;\n};\n\nconst struct ipaddr_str ipaddr_valid_strs[] = {\n\t\t{\"0.0.0.0\", {AF_INET, {IP4(0,0,0,0)}, 0},\n\t\t\t\tCMDLINE_IPADDR_V4},\n\t\t{\"0.0.0.0/0\", {AF_INET, {IP4(0,0,0,0)}, 0},\n\t\t\t\tCMDLINE_IPADDR_V4 | CMDLINE_IPADDR_NETWORK},\n\t\t{\"0.0.0.0/24\", {AF_INET, {IP4(0,0,0,0)}, 24},\n\t\t\t\tCMDLINE_IPADDR_V4 | CMDLINE_IPADDR_NETWORK},\n\t\t{\"192.168.1.0/24\", {AF_INET, {IP4(192,168,1,0)}, 24},\n\t\t\t\tCMDLINE_IPADDR_V4 | CMDLINE_IPADDR_NETWORK},\n\t\t{\"012.34.56.78/24\", {AF_INET, {IP4(12,34,56,78)}, 24},\n\t\t\t\tCMDLINE_IPADDR_V4 | CMDLINE_IPADDR_NETWORK},\n\t\t{\"34.56.78.90/1\", {AF_INET, {IP4(34,56,78,90)}, 1},\n\t\t\t\tCMDLINE_IPADDR_V4 | CMDLINE_IPADDR_NETWORK},\n\t\t{\"::\", {AF_INET6, {IP6(0,0,0,0,0,0,0,0)}, 0},\n\t\t\t\t\tCMDLINE_IPADDR_V6},\n\t\t{\"::1\", {AF_INET6, {IP6(0,0,0,0,0,0,0,1)}, 0},\n\t\t\t\tCMDLINE_IPADDR_V6},\n\t\t{\"::1/32\", {AF_INET6, {IP6(0,0,0,0,0,0,0,1)}, 32},\n\t\t\t\tCMDLINE_IPADDR_V6 | CMDLINE_IPADDR_NETWORK},\n\t\t{\"::/32\", {AF_INET6, {IP6(0,0,0,0,0,0,0,0)}, 32},\n\t\t\t\t\tCMDLINE_IPADDR_V6 | CMDLINE_IPADDR_NETWORK},\n\t\t/* RFC5952 requests that only lowercase should be used */\n\t\t{\"1234:5678:90ab:cdef:4321:8765:BA09:FEDC\", {AF_INET6,\n\t\t\t\t{IP6(0x1234,0x5678,0x90AB,0xCDEF,0x4321,0x8765,0xBA09,0xFEDC)},\n\t\t\t\t0},\n\t\t\t\tCMDLINE_IPADDR_V6},\n\t\t{\"1234::1234/64\", {AF_INET6,\n\t\t\t\t{IP6(0x1234,0,0,0,0,0,0,0x1234)},\n\t\t\t\t64},\n\t\t\t\tCMDLINE_IPADDR_V6 | CMDLINE_IPADDR_NETWORK},\n\t\t{\"1234::/64\", {AF_INET6,\n\t\t\t\t{IP6(0x1234,0,0,0,0,0,0,0)},\n\t\t\t\t64},\n\t\t\t\tCMDLINE_IPADDR_V6 | CMDLINE_IPADDR_NETWORK},\n\t\t{\"1:1::1/32\", {AF_INET6,\n\t\t\t\t{IP6(1,1,0,0,0,0,0,1)},\n\t\t\t\t32},\n\t\t\t\tCMDLINE_IPADDR_V6 | CMDLINE_IPADDR_NETWORK},\n\t\t{\"1:2:3:4::/64\", {AF_INET6,\n\t\t\t\t{IP6(1,2,3,4,0,0,0,0)},\n\t\t\t\t64},\n\t\t\tCMDLINE_IPADDR_V6 | CMDLINE_IPADDR_NETWORK},\n\t\t{\"::ffff:192.168.1.0/64\", {AF_INET6,\n\t\t\t\t{IP6(0,0,0,0,0,0xFFFF,0xC0A8,0x100)},\n\t\t\t\t64},\n\t\t\tCMDLINE_IPADDR_V6 | CMDLINE_IPADDR_NETWORK},\n\t\t/* RFC5952 requests not using :: to skip one block of zeros*/\n\t\t{\"1::2:3:4:5:6:7\", {AF_INET6,\n\t\t\t\t{IP6(1,0,2,3,4,5,6,7)},\n\t\t\t\t0},\n\t\t\tCMDLINE_IPADDR_V6},\n};\n\nconst char * ipaddr_garbage_addr4_strs[] = {\n\t\t/* IPv4 */\n\t\t\"192.168.1.0 garbage\",\n\t\t\"192.168.1.0\\0garbage\",\n\t\t\"192.168.1.0#garbage\",\n\t\t\"192.168.1.0\\tgarbage\",\n\t\t\"192.168.1.0\\rgarbage\",\n\t\t\"192.168.1.0\\ngarbage\",\n};\n#define IPv4_GARBAGE_ADDR IP4(192,168,1,0)\n\nconst char * ipaddr_garbage_addr6_strs[] = {\n\t\t/* IPv6 */\n\t\t\"1:2:3:4::8 garbage\",\n\t\t\"1:2:3:4::8#garbage\",\n\t\t\"1:2:3:4::8\\0garbage\",\n\t\t\"1:2:3:4::8\\rgarbage\",\n\t\t\"1:2:3:4::8\\ngarbage\",\n\t\t\"1:2:3:4::8\\tgarbage\",\n};\n#define IPv6_GARBAGE_ADDR {IP6(1,2,3,4,0,0,0,8)}\n\nconst char * ipaddr_garbage_network4_strs[] = {\n\t\t/* IPv4 */\n\t\t\"192.168.1.0/24 garbage\",\n\t\t\"192.168.1.0/24\\0garbage\",\n\t\t\"192.168.1.0/24#garbage\",\n\t\t\"192.168.1.0/24\\tgarbage\",\n\t\t\"192.168.1.0/24\\rgarbage\",\n\t\t\"192.168.1.0/24\\ngarbage\",\n};\n#define IPv4_GARBAGE_PREFIX 24\n\nconst char * ipaddr_garbage_network6_strs[] = {\n\t\t/* IPv6 */\n\t\t\"1:2:3:4::8/64 garbage\",\n\t\t\"1:2:3:4::8/64#garbage\",\n\t\t\"1:2:3:4::8/64\\0garbage\",\n\t\t\"1:2:3:4::8/64\\rgarbage\",\n\t\t\"1:2:3:4::8/64\\ngarbage\",\n\t\t\"1:2:3:4::8/64\\tgarbage\",\n};\n#define IPv6_GARBAGE_PREFIX 64\n\n\n\nconst char * ipaddr_invalid_strs[] = {\n\t\t/** IPv4 **/\n\n\t\t/* invalid numbers */\n\t\t\"0.0.0.-1\",\n\t\t\"0.0.-1.0\",\n\t\t\"0.-1.0.0\",\n\t\t\"-1.0.0.0\",\n\t\t\"0.0.0.-1/24\",\n\t\t\"256.123.123.123\",\n\t\t\"255.256.123.123\",\n\t\t\"255.255.256.123\",\n\t\t\"255.255.255.256\",\n\t\t\"256.123.123.123/24\",\n\t\t\"255.256.123.123/24\",\n\t\t\"255.255.256.123/24\",\n\t\t\"255.255.255.256/24\",\n\t\t/* invalid network mask */\n\t\t\"1.2.3.4/33\",\n\t\t\"1.2.3.4/33231313\",\n\t\t\"1.2.3.4/-1\",\n\t\t\"1.2.3.4/24/33\",\n\t\t\"1.2.3.4/24/-1\",\n\t\t\"1.2.3.4/24/\",\n\t\t/* wrong format */\n\t\t\"1/24\"\n\t\t\"/24\"\n\t\t\"123.123.123\",\n\t\t\"123.123.123.\",\n\t\t\"123.123.123.123.\",\n\t\t\"123.123.123..123\",\n\t\t\"123.123.123.123.123\",\n\t\t\".123.123.123\",\n\t\t\".123.123.123.123\",\n\t\t\"123.123.123/24\",\n\t\t\"123.123.123./24\",\n\t\t\"123.123.123.123./24\",\n\t\t\"123.123.123..123/24\",\n\t\t\"123.123.123.123.123/24\",\n\t\t\".123.123.123/24\",\n\t\t\".123.123.123.123/24\",\n\t\t/* invalid characters */\n\t\t\"123.123.123.12F\",\n\t\t\"123.123.12F.123\",\n\t\t\"123.12F.123.123\",\n\t\t\"12F.123.123.123\",\n\t\t\"12J.123.123.123\",\n\t\t\"123,123,123,123\",\n\t\t\"123!123!123!12F\",\n\t\t\"123.123.123.123/4F\",\n\n\t\t/** IPv6 **/\n\n\t\t/* wrong format */\n\t\t\"::fffff\",\n\t\t\"ffff:\",\n\t\t\"1:2:3:4:5:6:7:192.168.1.1\",\n\t\t\"1234:192.168.1.1:ffff::\",\n\t\t\"1:2:3:4:5:6:7:890ab\",\n\t\t\"1:2:3:4:5:6:7890a:b\",\n\t\t\"1:2:3:4:5:67890:a:b\",\n\t\t\"1:2:3:4:56789:0:a:b\",\n\t\t\"1:2:3:45678:9:0:a:b\",\n\t\t\"1:2:34567:8:9:0:a:b\",\n\t\t\"1:23456:7:8:9:0:a:b\",\n\t\t\"12345:6:7:8:9:0:a:b\",\n\t\t\"1:::2\",\n\t\t\"1::::2\",\n\t\t\"::fffff/64\",\n\t\t\"1::2::3\",\n\t\t\"1::2::3/64\",\n\t\t\":1:2\",\n\t\t\":1:2/64\",\n\t\t\":1::2\",\n\t\t\":1::2/64\",\n\t\t\"1::2:3:4:5:6:7:8/64\",\n\n\t\t/* invalid network mask */\n\t\t\"1:2:3:4:5:6:7:8/129\",\n\t\t\"1:2:3:4:5:6:7:8/-1\",\n\n\t\t/* invalid characters */\n\t\t\"a:b:c:d:e:f:g::\",\n\n\t\t/** misc **/\n\n\t\t/* too long */\n\t\t\"1234:1234:1234:1234:1234:1234:1234:1234:1234:1234:1234\"\n\t\t\"random invalid text\",\n\t\t\"\",\n\t\t\"\\0\",\n\t\t\" \",\n};\n\n#define IPADDR_VALID_STRS_SIZE \\\n\t(sizeof(ipaddr_valid_strs) / sizeof(ipaddr_valid_strs[0]))\n#define IPADDR_GARBAGE_ADDR4_STRS_SIZE \\\n\t(sizeof(ipaddr_garbage_addr4_strs) / sizeof(ipaddr_garbage_addr4_strs[0]))\n#define IPADDR_GARBAGE_ADDR6_STRS_SIZE \\\n\t(sizeof(ipaddr_garbage_addr6_strs) / sizeof(ipaddr_garbage_addr6_strs[0]))\n#define IPADDR_GARBAGE_NETWORK4_STRS_SIZE \\\n\t(sizeof(ipaddr_garbage_network4_strs) / sizeof(ipaddr_garbage_network4_strs[0]))\n#define IPADDR_GARBAGE_NETWORK6_STRS_SIZE \\\n\t(sizeof(ipaddr_garbage_network6_strs) / sizeof(ipaddr_garbage_network6_strs[0]))\n#define IPADDR_INVALID_STRS_SIZE \\\n\t(sizeof(ipaddr_invalid_strs) / sizeof(ipaddr_invalid_strs[0]))\n\nstatic void\ndump_addr(cmdline_ipaddr_t addr)\n{\n\tswitch (addr.family) {\n\tcase AF_INET:\n\t{\n\t\tprintf(NIPQUAD_FMT \" prefixlen=%u\\n\",\n\t\t\t\tNIPQUAD(addr.addr.ipv4.s_addr), addr.prefixlen);\n\t\tbreak;\n\t}\n\tcase AF_INET6:\n\t{\n\t\tprintf(NIP6_FMT \" prefixlen=%u\\n\",\n\t\t\t\tNIP6(addr.addr.ipv6), addr.prefixlen);\n\t\tbreak;\n\t}\n\tdefault:\n\t\tprintf(\"Can't dump: unknown address family.\\n\");\n\t\treturn;\n\t}\n}\n\n\nstatic int\nis_addr_different(cmdline_ipaddr_t addr1, cmdline_ipaddr_t addr2)\n{\n\tif (addr1.family != addr2.family)\n\t\treturn 1;\n\n\tif (addr1.prefixlen != addr2.prefixlen)\n\t\treturn 1;\n\n\tswitch (addr1.family) {\n\t/* IPv4 */\n\tcase AF_INET:\n\t\tif (memcmp(&addr1.addr.ipv4, &addr2.addr.ipv4,\n\t\t\t\tsizeof(struct in_addr)) != 0)\n\t\t\treturn 1;\n\t\tbreak;\n\t/* IPv6 */\n\tcase AF_INET6:\n\t{\n\t\tif (memcmp(&addr1.addr.ipv6, &addr2.addr.ipv6,\n\t\t\t\tsizeof(struct in6_addr)) != 0)\n\t\t\treturn 1;\n\t\tbreak;\n\t}\n\t/* thing that should not be */\n\tdefault:\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic int\ncan_parse_addr(unsigned addr_flags, unsigned test_flags)\n{\n\tif ((test_flags & addr_flags) == addr_flags) {\n\t\t/* if we are not trying to parse network addresses */\n\t\tif (test_flags < CMDLINE_IPADDR_NETWORK)\n\t\t\treturn 1;\n\t\t/* if this is a network address */\n\t\telse if (addr_flags & CMDLINE_IPADDR_NETWORK)\n\t\t\treturn 1;\n\t}\n\treturn 0;\n}\n\nint\ntest_parse_ipaddr_valid(void)\n{\n\tcmdline_parse_token_ipaddr_t token;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tcmdline_ipaddr_t result;\n\tunsigned i;\n\tuint8_t flags;\n\tint ret;\n\n\t/* cover all cases in help */\n\tfor (flags = 0x1; flags < 0x8; flags++) {\n\t\ttoken.ipaddr_data.flags = flags;\n\n\t\tmemset(buf, 0, sizeof(buf));\n\n\t\tif (cmdline_get_help_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\tbuf, sizeof(buf)) == -1) {\n\t\t\tprintf(\"Error: help rejected valid parameters!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* test valid strings */\n\tfor (i = 0; i < IPADDR_VALID_STRS_SIZE; i++) {\n\n\t\t/* test each valid string against different flags */\n\t\tfor (flags = 1; flags < 0x8; flags++) {\n\n\t\t\t/* skip bad flag */\n\t\t\tif (flags == CMDLINE_IPADDR_NETWORK)\n\t\t\t\tcontinue;\n\n\t\t\t/* clear out everything */\n\t\t\tmemset(buf, 0, sizeof(buf));\n\t\t\tmemset(&result, 0, sizeof(result));\n\t\t\tmemset(&token, 0, sizeof(token));\n\n\t\t\ttoken.ipaddr_data.flags = flags;\n\n\t\t\tcmdline_get_help_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\t\t\t\tbuf, sizeof(buf));\n\n\t\t\tret = cmdline_parse_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\tipaddr_valid_strs[i].str, (void*)&result,\n\t\t\t\tsizeof(result));\n\n\t\t\t/* if should have passed, or should have failed */\n\t\t\tif ((ret < 0) ==\n\t\t\t\t\t(can_parse_addr(ipaddr_valid_strs[i].flags, flags))) {\n\t\t\t\tprintf(\"Error: unexpected behavior when parsing %s as %s!\\n\",\n\t\t\t\t\t\tipaddr_valid_strs[i].str, buf);\n\t\t\t\tprintf(\"Parsed result: \");\n\t\t\t\tdump_addr(result);\n\t\t\t\tprintf(\"Expected result: \");\n\t\t\t\tdump_addr(ipaddr_valid_strs[i].addr);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tif (ret != -1 &&\n\t\t\t\t\tis_addr_different(result, ipaddr_valid_strs[i].addr)) {\n\t\t\t\tprintf(\"Error: result mismatch when parsing %s as %s!\\n\",\n\t\t\t\t\t\tipaddr_valid_strs[i].str, buf);\n\t\t\t\tprintf(\"Parsed result: \");\n\t\t\t\tdump_addr(result);\n\t\t\t\tprintf(\"Expected result: \");\n\t\t\t\tdump_addr(ipaddr_valid_strs[i].addr);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* test garbage ipv4 address strings */\n\tfor (i = 0; i < IPADDR_GARBAGE_ADDR4_STRS_SIZE; i++) {\n\n\t\tstruct in_addr tmp = IPv4_GARBAGE_ADDR;\n\n\t\t/* test each valid string against different flags */\n\t\tfor (flags = 1; flags < 0x8; flags++) {\n\n\t\t\t/* skip bad flag */\n\t\t\tif (flags == CMDLINE_IPADDR_NETWORK)\n\t\t\t\tcontinue;\n\n\t\t\t/* clear out everything */\n\t\t\tmemset(buf, 0, sizeof(buf));\n\t\t\tmemset(&result, 0, sizeof(result));\n\t\t\tmemset(&token, 0, sizeof(token));\n\n\t\t\ttoken.ipaddr_data.flags = flags;\n\n\t\t\tcmdline_get_help_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\t\t\t\tbuf, sizeof(buf));\n\n\t\t\tret = cmdline_parse_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\tipaddr_garbage_addr4_strs[i], (void*)&result,\n\t\t\t\tsizeof(result));\n\n\t\t\t/* if should have passed, or should have failed */\n\t\t\tif ((ret < 0) ==\n\t\t\t\t\t(can_parse_addr(CMDLINE_IPADDR_V4, flags))) {\n\t\t\t\tprintf(\"Error: unexpected behavior when parsing %s as %s!\\n\",\n\t\t\t\t\t\tipaddr_garbage_addr4_strs[i], buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tif (ret != -1 &&\n\t\t\t\t\tmemcmp(&result.addr.ipv4, &tmp, sizeof(tmp))) {\n\t\t\t\tprintf(\"Error: result mismatch when parsing %s as %s!\\n\",\n\t\t\t\t\t\tipaddr_garbage_addr4_strs[i], buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* test garbage ipv6 address strings */\n\tfor (i = 0; i < IPADDR_GARBAGE_ADDR6_STRS_SIZE; i++) {\n\n\t\tcmdline_ipaddr_t tmp = {.addr = IPv6_GARBAGE_ADDR};\n\n\t\t/* test each valid string against different flags */\n\t\tfor (flags = 1; flags < 0x8; flags++) {\n\n\t\t\t/* skip bad flag */\n\t\t\tif (flags == CMDLINE_IPADDR_NETWORK)\n\t\t\t\tcontinue;\n\n\t\t\t/* clear out everything */\n\t\t\tmemset(buf, 0, sizeof(buf));\n\t\t\tmemset(&result, 0, sizeof(result));\n\t\t\tmemset(&token, 0, sizeof(token));\n\n\t\t\ttoken.ipaddr_data.flags = flags;\n\n\t\t\tcmdline_get_help_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\t\t\t\tbuf, sizeof(buf));\n\n\t\t\tret = cmdline_parse_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\tipaddr_garbage_addr6_strs[i], (void*)&result,\n\t\t\t\tsizeof(result));\n\n\t\t\t/* if should have passed, or should have failed */\n\t\t\tif ((ret < 0) ==\n\t\t\t\t\t(can_parse_addr(CMDLINE_IPADDR_V6, flags))) {\n\t\t\t\tprintf(\"Error: unexpected behavior when parsing %s as %s!\\n\",\n\t\t\t\t\t\tipaddr_garbage_addr6_strs[i], buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tif (ret != -1 &&\n\t\t\t\t\tmemcmp(&result.addr.ipv6, &tmp.addr.ipv6, sizeof(struct in6_addr))) {\n\t\t\t\tprintf(\"Error: result mismatch when parsing %s as %s!\\n\",\n\t\t\t\t\t\tipaddr_garbage_addr6_strs[i], buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\n\t/* test garbage ipv4 network strings */\n\tfor (i = 0; i < IPADDR_GARBAGE_NETWORK4_STRS_SIZE; i++) {\n\n\t\tstruct in_addr tmp = IPv4_GARBAGE_ADDR;\n\n\t\t/* test each valid string against different flags */\n\t\tfor (flags = 1; flags < 0x8; flags++) {\n\n\t\t\t/* skip bad flag */\n\t\t\tif (flags == CMDLINE_IPADDR_NETWORK)\n\t\t\t\tcontinue;\n\n\t\t\t/* clear out everything */\n\t\t\tmemset(buf, 0, sizeof(buf));\n\t\t\tmemset(&result, 0, sizeof(result));\n\t\t\tmemset(&token, 0, sizeof(token));\n\n\t\t\ttoken.ipaddr_data.flags = flags;\n\n\t\t\tcmdline_get_help_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\t\t\t\tbuf, sizeof(buf));\n\n\t\t\tret = cmdline_parse_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\tipaddr_garbage_network4_strs[i], (void*)&result,\n\t\t\t\tsizeof(result));\n\n\t\t\t/* if should have passed, or should have failed */\n\t\t\tif ((ret < 0) ==\n\t\t\t\t\t(can_parse_addr(CMDLINE_IPADDR_V4 | CMDLINE_IPADDR_NETWORK, flags))) {\n\t\t\t\tprintf(\"Error: unexpected behavior when parsing %s as %s!\\n\",\n\t\t\t\t\t\tipaddr_garbage_network4_strs[i], buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tif (ret != -1 &&\n\t\t\t\t\tmemcmp(&result.addr.ipv4, &tmp, sizeof(tmp))) {\n\t\t\t\tprintf(\"Error: result mismatch when parsing %s as %s!\\n\",\n\t\t\t\t\t\tipaddr_garbage_network4_strs[i], buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* test garbage ipv6 address strings */\n\tfor (i = 0; i < IPADDR_GARBAGE_NETWORK6_STRS_SIZE; i++) {\n\n\t\tcmdline_ipaddr_t tmp = {.addr = IPv6_GARBAGE_ADDR};\n\n\t\t/* test each valid string against different flags */\n\t\tfor (flags = 1; flags < 0x8; flags++) {\n\n\t\t\t/* skip bad flag */\n\t\t\tif (flags == CMDLINE_IPADDR_NETWORK)\n\t\t\t\tcontinue;\n\n\t\t\t/* clear out everything */\n\t\t\tmemset(buf, 0, sizeof(buf));\n\t\t\tmemset(&result, 0, sizeof(result));\n\t\t\tmemset(&token, 0, sizeof(token));\n\n\t\t\ttoken.ipaddr_data.flags = flags;\n\n\t\t\tcmdline_get_help_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\t\t\t\tbuf, sizeof(buf));\n\n\t\t\tret = cmdline_parse_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\tipaddr_garbage_network6_strs[i], (void*)&result,\n\t\t\t\tsizeof(result));\n\n\t\t\t/* if should have passed, or should have failed */\n\t\t\tif ((ret < 0) ==\n\t\t\t\t\t(can_parse_addr(CMDLINE_IPADDR_V6 | CMDLINE_IPADDR_NETWORK, flags))) {\n\t\t\t\tprintf(\"Error: unexpected behavior when parsing %s as %s!\\n\",\n\t\t\t\t\t\tipaddr_garbage_network6_strs[i], buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tif (ret != -1 &&\n\t\t\t\t\tmemcmp(&result.addr.ipv6, &tmp.addr.ipv6, sizeof(struct in6_addr))) {\n\t\t\t\tprintf(\"Error: result mismatch when parsing %s as %s!\\n\",\n\t\t\t\t\t\tipaddr_garbage_network6_strs[i], buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nint\ntest_parse_ipaddr_invalid_data(void)\n{\n\tcmdline_parse_token_ipaddr_t token;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tcmdline_ipaddr_t result;\n\tunsigned i;\n\tuint8_t flags;\n\tint ret;\n\n\tmemset(&result, 0, sizeof(result));\n\n\t/* test invalid strings */\n\tfor (i = 0; i < IPADDR_INVALID_STRS_SIZE; i++) {\n\n\t\t/* test each valid string against different flags */\n\t\tfor (flags = 1; flags < 0x8; flags++) {\n\n\t\t\t/* skip bad flag */\n\t\t\tif (flags == CMDLINE_IPADDR_NETWORK)\n\t\t\t\tcontinue;\n\n\t\t\t/* clear out everything */\n\t\t\tmemset(buf, 0, sizeof(buf));\n\t\t\tmemset(&token, 0, sizeof(token));\n\n\t\t\ttoken.ipaddr_data.flags = flags;\n\n\t\t\tcmdline_get_help_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\t\tbuf, sizeof(buf));\n\n\t\t\tret = cmdline_parse_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\tipaddr_invalid_strs[i], (void*)&result,\n\t\t\t\tsizeof(result));\n\n\t\t\tif (ret != -1) {\n\t\t\t\tprintf(\"Error: parsing %s as %s succeeded!\\n\",\n\t\t\t\t\t\tipaddr_invalid_strs[i], buf);\n\t\t\t\tprintf(\"Parsed result: \");\n\t\t\t\tdump_addr(result);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nint\ntest_parse_ipaddr_invalid_param(void)\n{\n\tcmdline_parse_token_ipaddr_t token;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tcmdline_ipaddr_t result;\n\n\tsnprintf(buf, sizeof(buf), \"1.2.3.4\");\n\ttoken.ipaddr_data.flags = CMDLINE_IPADDR_V4;\n\n\t/* null token */\n\tif (cmdline_parse_ipaddr(NULL, buf, (void*)&result,\n\t\t\tsizeof(result)) != -1) {\n\t\tprintf(\"Error: parser accepted invalid parameters!\\n\");\n\t\treturn -1;\n\t}\n\t/* null buffer */\n\tif (cmdline_parse_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\tNULL, (void*)&result, sizeof(result)) != -1) {\n\t\tprintf(\"Error: parser accepted invalid parameters!\\n\");\n\t\treturn -1;\n\t}\n\t/* empty buffer */\n\tif (cmdline_parse_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\"\", (void*)&result, sizeof(result)) != -1) {\n\t\tprintf(\"Error: parser accepted invalid parameters!\\n\");\n\t\treturn -1;\n\t}\n\t/* null result */\n\tif (cmdline_parse_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\tbuf, NULL, 0) == -1) {\n\t\tprintf(\"Error: parser rejected null result!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* null token */\n\tif (cmdline_get_help_ipaddr(NULL, buf, 0) != -1) {\n\t\tprintf(\"Error: help accepted invalid parameters!\\n\");\n\t\treturn -1;\n\t}\n\t/* null buffer */\n\tif (cmdline_get_help_ipaddr((cmdline_parse_token_hdr_t*)&token,\n\t\t\tNULL, 0) != -1) {\n\t\tprintf(\"Error: help accepted invalid parameters!\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n" }, { "path": "app/test/test_cmdline_lib.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"test_cmdline.h\"\n\n/****************************************************************/\n/* static functions required for some tests */\nstatic void\nvalid_buffer(__attribute__((unused))struct rdline *rdl,\n\t\t\t__attribute__((unused))const char *buf,\n\t\t\t__attribute__((unused)) unsigned int size)\n{\n}\n\nstatic int\ncomplete_buffer(__attribute__((unused)) struct rdline *rdl,\n\t\t\t__attribute__((unused)) const char *buf,\n\t\t\t__attribute__((unused)) char *dstbuf,\n\t\t\t__attribute__((unused)) unsigned int dstsize,\n\t\t\t__attribute__((unused)) int *state)\n{\n\treturn 0;\n}\n\n/****************************************************************/\n\nstatic int\ntest_cmdline_parse_fns(void)\n{\n\tstruct cmdline cl;\n\tint i = 0;\n\tchar dst[CMDLINE_TEST_BUFSIZE];\n\n\tif (cmdline_parse(NULL, \"buffer\") >= 0)\n\t\tgoto error;\n\tif (cmdline_parse(&cl, NULL) >= 0)\n\t\tgoto error;\n\n\tif (cmdline_complete(NULL, \"buffer\", &i, dst, sizeof(dst)) >= 0)\n\t\tgoto error;\n\tif (cmdline_complete(&cl, NULL, &i, dst, sizeof(dst)) >= 0)\n\t\tgoto error;\n\tif (cmdline_complete(&cl, \"buffer\", NULL, dst, sizeof(dst)) >= 0)\n\t\tgoto error;\n\tif (cmdline_complete(&cl, \"buffer\", &i, NULL, sizeof(dst)) >= 0)\n\t\tgoto error;\n\n\treturn 0;\n\nerror:\n\tprintf(\"Error: function accepted null parameter!\\n\");\n\treturn -1;\n}\n\nstatic int\ntest_cmdline_rdline_fns(void)\n{\n\tstruct rdline rdl;\n\trdline_write_char_t *wc = &cmdline_write_char;\n\trdline_validate_t *v = &valid_buffer;\n\trdline_complete_t *c = &complete_buffer;\n\n\tif (rdline_init(NULL, wc, v, c) >= 0)\n\t\tgoto error;\n\tif (rdline_init(&rdl, NULL, v, c) >= 0)\n\t\tgoto error;\n\tif (rdline_init(&rdl, wc, NULL, c) >= 0)\n\t\tgoto error;\n\tif (rdline_init(&rdl, wc, v, NULL) >= 0)\n\t\tgoto error;\n\tif (rdline_char_in(NULL, 0) >= 0)\n\t\tgoto error;\n\tif (rdline_get_buffer(NULL) != NULL)\n\t\tgoto error;\n\tif (rdline_add_history(NULL, \"history\") >= 0)\n\t\tgoto error;\n\tif (rdline_add_history(&rdl, NULL) >= 0)\n\t\tgoto error;\n\tif (rdline_get_history_item(NULL, 0) != NULL)\n\t\tgoto error;\n\n\t/* void functions */\n\trdline_newline(NULL, \"prompt\");\n\trdline_newline(&rdl, NULL);\n\trdline_stop(NULL);\n\trdline_quit(NULL);\n\trdline_restart(NULL);\n\trdline_redisplay(NULL);\n\trdline_reset(NULL);\n\trdline_clear_history(NULL);\n\n\treturn 0;\n\nerror:\n\tprintf(\"Error: function accepted null parameter!\\n\");\n\treturn -1;\n}\n\nstatic int\ntest_cmdline_vt100_fns(void)\n{\n\tif (vt100_parser(NULL, 0) >= 0) {\n\t\tprintf(\"Error: function accepted null parameter!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* void functions */\n\tvt100_init(NULL);\n\n\treturn 0;\n}\n\nstatic int\ntest_cmdline_socket_fns(void)\n{\n\tcmdline_parse_ctx_t ctx;\n\n\tif (cmdline_stdin_new(NULL, \"prompt\") != NULL)\n\t\tgoto error;\n\tif (cmdline_stdin_new(&ctx, NULL) != NULL)\n\t\tgoto error;\n\tif (cmdline_file_new(NULL, \"prompt\", \"/dev/null\") != NULL)\n\t\tgoto error;\n\tif (cmdline_file_new(&ctx, NULL, \"/dev/null\") != NULL)\n\t\tgoto error;\n\tif (cmdline_file_new(&ctx, \"prompt\", NULL) != NULL)\n\t\tgoto error;\n\tif (cmdline_file_new(&ctx, \"prompt\", \"-/invalid/~/path\") != NULL) {\n\t\tprintf(\"Error: succeeded in opening invalid file for reading!\");\n\t\treturn -1;\n\t}\n\tif (cmdline_file_new(&ctx, \"prompt\", \"/dev/null\") == NULL) {\n\t\tprintf(\"Error: failed to open /dev/null for reading!\");\n\t\treturn -1;\n\t}\n\n\t/* void functions */\n\tcmdline_stdin_exit(NULL);\n\n\treturn 0;\nerror:\n\tprintf(\"Error: function accepted null parameter!\\n\");\n\treturn -1;\n}\n\nstatic int\ntest_cmdline_fns(void)\n{\n\tcmdline_parse_ctx_t ctx;\n\tstruct cmdline cl, *tmp;\n\n\tmemset(&ctx, 0, sizeof(ctx));\n\ttmp = cmdline_new(&ctx, \"test\", -1, -1);\n\tif (tmp == NULL)\n\t\tgoto error;\n\n\tif (cmdline_new(NULL, \"prompt\", 0, 0) != NULL)\n\t\tgoto error;\n\tif (cmdline_new(&ctx, NULL, 0, 0) != NULL)\n\t\tgoto error;\n\tif (cmdline_in(NULL, \"buffer\", CMDLINE_TEST_BUFSIZE) >= 0)\n\t\tgoto error;\n\tif (cmdline_in(&cl, NULL, CMDLINE_TEST_BUFSIZE) >= 0)\n\t\tgoto error;\n\tif (cmdline_write_char(NULL, 0) >= 0)\n\t\tgoto error;\n\n\t/* void functions */\n\tcmdline_set_prompt(NULL, \"prompt\");\n\tcmdline_free(NULL);\n\tcmdline_printf(NULL, \"format\");\n\t/* this should fail as stream handles are invalid */\n\tcmdline_printf(tmp, \"format\");\n\tcmdline_interact(NULL);\n\tcmdline_quit(NULL);\n\n\t/* check if void calls change anything when they should fail */\n\tcl = *tmp;\n\n\tcmdline_printf(&cl, NULL);\n\tif (memcmp(&cl, tmp, sizeof(cl))) goto mismatch;\n\tcmdline_set_prompt(&cl, NULL);\n\tif (memcmp(&cl, tmp, sizeof(cl))) goto mismatch;\n\tcmdline_in(&cl, NULL, CMDLINE_TEST_BUFSIZE);\n\tif (memcmp(&cl, tmp, sizeof(cl))) goto mismatch;\n\n\tcmdline_free(tmp);\n\n\treturn 0;\n\nerror:\n\tprintf(\"Error: function accepted null parameter!\\n\");\n\treturn -1;\nmismatch:\n\tprintf(\"Error: data changed!\\n\");\n\treturn -1;\n}\n\n/* test library functions. the point of these tests is not so much to test\n * functions' behaviour as it is to make sure there are no segfaults if\n * they are called with invalid parameters.\n */\nint\ntest_cmdline_lib(void)\n{\n\tif (test_cmdline_parse_fns() < 0)\n\t\treturn -1;\n\tif (test_cmdline_rdline_fns() < 0)\n\t\treturn -1;\n\tif (test_cmdline_vt100_fns() < 0)\n\t\treturn -1;\n\tif (test_cmdline_socket_fns() < 0)\n\t\treturn -1;\n\tif (test_cmdline_fns() < 0)\n\t\treturn -1;\n\treturn 0;\n}\n" }, { "path": "app/test/test_cmdline_num.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n\n#include \n#include \n\n#include \"test_cmdline.h\"\n\nstruct num_unsigned_str {\n\tconst char * str;\n\tuint64_t result;\n};\n\nstruct num_signed_str {\n\tconst char * str;\n\tint64_t result;\n};\n\nconst struct num_unsigned_str num_valid_positive_strs[] = {\n\t\t/* decimal positive */\n\t\t{\"0\", 0 },\n\t\t{\"127\", INT8_MAX },\n\t\t{\"128\", INT8_MAX + 1 },\n\t\t{\"255\", UINT8_MAX },\n\t\t{\"256\", UINT8_MAX + 1 },\n\t\t{\"32767\", INT16_MAX },\n\t\t{\"32768\", INT16_MAX + 1 },\n\t\t{\"65535\", UINT16_MAX },\n\t\t{\"65536\", UINT16_MAX + 1 },\n\t\t{\"2147483647\", INT32_MAX },\n\t\t{\"2147483648\", INT32_MAX + 1U },\n\t\t{\"4294967295\", UINT32_MAX },\n\t\t{\"4294967296\", UINT32_MAX + 1ULL },\n\t\t{\"9223372036854775807\", INT64_MAX },\n\t\t{\"9223372036854775808\", INT64_MAX + 1ULL},\n\t\t{\"18446744073709551615\", UINT64_MAX },\n\t\t/* hexadecimal (no leading zeroes) */\n\t\t{\"0x0\", 0 },\n\t\t{\"0x7F\", INT8_MAX },\n\t\t{\"0x80\", INT8_MAX + 1 },\n\t\t{\"0xFF\", UINT8_MAX },\n\t\t{\"0x100\", UINT8_MAX + 1 },\n\t\t{\"0x7FFF\", INT16_MAX },\n\t\t{\"0x8000\", INT16_MAX + 1 },\n\t\t{\"0xFFFF\", UINT16_MAX },\n\t\t{\"0x10000\", UINT16_MAX + 1 },\n\t\t{\"0x7FFFFFFF\", INT32_MAX },\n\t\t{\"0x80000000\", INT32_MAX + 1U },\n\t\t{\"0xFFFFFFFF\", UINT32_MAX },\n\t\t{\"0x100000000\", UINT32_MAX + 1ULL },\n\t\t{\"0x7FFFFFFFFFFFFFFF\", INT64_MAX },\n\t\t{\"0x8000000000000000\", INT64_MAX + 1ULL},\n\t\t{\"0xFFFFFFFFFFFFFFFF\", UINT64_MAX },\n\t\t/* hexadecimal (with leading zeroes) */\n\t\t{\"0x00\", 0 },\n\t\t{\"0x7F\", INT8_MAX },\n\t\t{\"0x80\", INT8_MAX + 1 },\n\t\t{\"0xFF\", UINT8_MAX },\n\t\t{\"0x0100\", UINT8_MAX + 1 },\n\t\t{\"0x7FFF\", INT16_MAX },\n\t\t{\"0x8000\", INT16_MAX + 1 },\n\t\t{\"0xFFFF\", UINT16_MAX },\n\t\t{\"0x00010000\", UINT16_MAX + 1 },\n\t\t{\"0x7FFFFFFF\", INT32_MAX },\n\t\t{\"0x80000000\", INT32_MAX + 1U },\n\t\t{\"0xFFFFFFFF\", UINT32_MAX },\n\t\t{\"0x0000000100000000\", UINT32_MAX + 1ULL },\n\t\t{\"0x7FFFFFFFFFFFFFFF\", INT64_MAX },\n\t\t{\"0x8000000000000000\", INT64_MAX + 1ULL},\n\t\t{\"0xFFFFFFFFFFFFFFFF\", UINT64_MAX },\n\t\t/* check all characters */\n\t\t{\"0x1234567890ABCDEF\", 0x1234567890ABCDEFULL },\n\t\t{\"0x1234567890abcdef\", 0x1234567890ABCDEFULL },\n\t\t/* binary (no leading zeroes) */\n\t\t{\"0b0\", 0 },\n\t\t{\"0b1111111\", INT8_MAX },\n\t\t{\"0b10000000\", INT8_MAX + 1 },\n\t\t{\"0b11111111\", UINT8_MAX },\n\t\t{\"0b100000000\", UINT8_MAX + 1 },\n\t\t{\"0b111111111111111\", INT16_MAX },\n\t\t{\"0b1000000000000000\", INT16_MAX + 1 },\n\t\t{\"0b1111111111111111\", UINT16_MAX },\n\t\t{\"0b10000000000000000\", UINT16_MAX + 1 },\n\t\t{\"0b1111111111111111111111111111111\", INT32_MAX },\n\t\t{\"0b10000000000000000000000000000000\", INT32_MAX + 1U },\n\t\t{\"0b11111111111111111111111111111111\", UINT32_MAX },\n\t\t{\"0b100000000000000000000000000000000\", UINT32_MAX + 1ULL },\n\t\t{\"0b111111111111111111111111111111111111111111111111111111111111111\",\n\t\t\t\tINT64_MAX },\n\t\t{\"0b1000000000000000000000000000000000000000000000000000000000000000\",\n\t\t\t\tINT64_MAX + 1ULL},\n\t\t{\"0b1111111111111111111111111111111111111111111111111111111111111111\",\n\t\t\t\tUINT64_MAX },\n\t\t/* binary (with leading zeroes) */\n\t\t{\"0b01111111\", INT8_MAX },\n\t\t{\"0b0000000100000000\", UINT8_MAX + 1 },\n\t\t{\"0b0111111111111111\", INT16_MAX },\n\t\t{\"0b00000000000000010000000000000000\", UINT16_MAX + 1 },\n\t\t{\"0b01111111111111111111111111111111\", INT32_MAX },\n\t\t{\"0b0000000000000000000000000000000100000000000000000000000000000000\",\n\t\t\t\tUINT32_MAX + 1ULL },\n\t\t{\"0b0111111111111111111111111111111111111111111111111111111111111111\",\n\t\t\t\tINT64_MAX },\n\t\t/* octal */\n\t\t{\"00\", 0 },\n\t\t{\"0177\", INT8_MAX },\n\t\t{\"0200\", INT8_MAX + 1 },\n\t\t{\"0377\", UINT8_MAX },\n\t\t{\"0400\", UINT8_MAX + 1 },\n\t\t{\"077777\", INT16_MAX },\n\t\t{\"0100000\", INT16_MAX + 1 },\n\t\t{\"0177777\", UINT16_MAX },\n\t\t{\"0200000\", UINT16_MAX + 1 },\n\t\t{\"017777777777\", INT32_MAX },\n\t\t{\"020000000000\", INT32_MAX + 1U },\n\t\t{\"037777777777\", UINT32_MAX },\n\t\t{\"040000000000\", UINT32_MAX + 1ULL },\n\t\t{\"0777777777777777777777\", INT64_MAX },\n\t\t{\"01000000000000000000000\", INT64_MAX + 1ULL},\n\t\t{\"01777777777777777777777\", UINT64_MAX },\n\t\t/* check all numbers */\n\t\t{\"012345670\", 012345670 },\n\t\t{\"076543210\", 076543210 },\n};\n\nconst struct num_signed_str num_valid_negative_strs[] = {\n\t\t/* deciman negative */\n\t\t{\"-128\", INT8_MIN },\n\t\t{\"-129\", INT8_MIN - 1 },\n\t\t{\"-32768\", INT16_MIN },\n\t\t{\"-32769\", INT16_MIN - 1 },\n\t\t{\"-2147483648\", INT32_MIN },\n\t\t{\"-2147483649\", INT32_MIN - 1LL },\n\t\t{\"-9223372036854775808\", INT64_MIN },\n};\n\nconst struct num_unsigned_str num_garbage_positive_strs[] = {\n\t\t/* valid strings with garbage on the end, should still be valid */\n\t\t/* decimal */\n\t\t{\"9223372036854775807\\0garbage\", INT64_MAX },\n\t\t{\"9223372036854775807\\tgarbage\", INT64_MAX },\n\t\t{\"9223372036854775807\\rgarbage\", INT64_MAX },\n\t\t{\"9223372036854775807\\ngarbage\", INT64_MAX },\n\t\t{\"9223372036854775807#garbage\", INT64_MAX },\n\t\t{\"9223372036854775807 garbage\", INT64_MAX },\n\t\t/* hex */\n\t\t{\"0x7FFFFFFFFFFFFFFF\\0garbage\", INT64_MAX },\n\t\t{\"0x7FFFFFFFFFFFFFFF\\tgarbage\", INT64_MAX },\n\t\t{\"0x7FFFFFFFFFFFFFFF\\rgarbage\", INT64_MAX },\n\t\t{\"0x7FFFFFFFFFFFFFFF\\ngarbage\", INT64_MAX },\n\t\t{\"0x7FFFFFFFFFFFFFFF#garbage\", INT64_MAX },\n\t\t{\"0x7FFFFFFFFFFFFFFF garbage\", INT64_MAX },\n\t\t/* binary */\n\t\t{\"0b1111111111111111111111111111111\\0garbage\", INT32_MAX },\n\t\t{\"0b1111111111111111111111111111111\\rgarbage\", INT32_MAX },\n\t\t{\"0b1111111111111111111111111111111\\tgarbage\", INT32_MAX },\n\t\t{\"0b1111111111111111111111111111111\\ngarbage\", INT32_MAX },\n\t\t{\"0b1111111111111111111111111111111#garbage\", INT32_MAX },\n\t\t{\"0b1111111111111111111111111111111 garbage\", INT32_MAX },\n\t\t/* octal */\n\t\t{\"01777777777777777777777\\0garbage\", UINT64_MAX },\n\t\t{\"01777777777777777777777\\rgarbage\", UINT64_MAX },\n\t\t{\"01777777777777777777777\\tgarbage\", UINT64_MAX },\n\t\t{\"01777777777777777777777\\ngarbage\", UINT64_MAX },\n\t\t{\"01777777777777777777777#garbage\", UINT64_MAX },\n\t\t{\"01777777777777777777777 garbage\", UINT64_MAX },\n};\n\nconst struct num_signed_str num_garbage_negative_strs[] = {\n\t\t/* valid strings with garbage on the end, should still be valid */\n\t\t{\"-9223372036854775808\\0garbage\", INT64_MIN },\n\t\t{\"-9223372036854775808\\rgarbage\", INT64_MIN },\n\t\t{\"-9223372036854775808\\tgarbage\", INT64_MIN },\n\t\t{\"-9223372036854775808\\ngarbage\", INT64_MIN },\n\t\t{\"-9223372036854775808#garbage\", INT64_MIN },\n\t\t{\"-9223372036854775808 garbage\", INT64_MIN },\n};\n\nconst char * num_invalid_strs[] = {\n\t\t\"18446744073709551616\", /* out of range unsigned */\n\t\t\"-9223372036854775809\", /* out of range negative signed */\n\t\t\"0x10000000000000000\", /* out of range hex */\n\t\t/* out of range binary */\n\t\t\"0b10000000000000000000000000000000000000000000000000000000000000000\",\n\t\t\"020000000000000000000000\", /* out of range octal */\n\t\t/* wrong chars */\n\t\t\"0123456239\",\n\t\t\"0x1234580AGE\",\n\t\t\"0b0111010101g001\",\n\t\t\"0b01110101017001\",\n\t\t/* false negative numbers */\n\t\t\"-12345F623\",\n\t\t\"-0x1234580A\",\n\t\t\"-0b0111010101\",\n\t\t/* too long (128+ chars) */\n\t\t\"0b1111000011110000111100001111000011110000111100001111000011110000\"\n\t\t \"1111000011110000111100001111000011110000111100001111000011110000\",\n\t\t\"1E3\",\n\t\t\"0A\",\n\t\t\"-B\",\n\t\t\"+4\",\n\t\t\"1.23G\",\n\t\t\"\",\n\t\t\" \",\n\t\t\"#\",\n\t\t\"\\r\",\n\t\t\"\\t\",\n\t\t\"\\n\",\n\t\t\"\\0\",\n};\n\n#define NUM_POSITIVE_STRS_SIZE \\\n\t(sizeof(num_valid_positive_strs) / sizeof(num_valid_positive_strs[0]))\n#define NUM_NEGATIVE_STRS_SIZE \\\n\t(sizeof(num_valid_negative_strs) / sizeof(num_valid_negative_strs[0]))\n#define NUM_POSITIVE_GARBAGE_STRS_SIZE \\\n\t(sizeof(num_garbage_positive_strs) / sizeof(num_garbage_positive_strs[0]))\n#define NUM_NEGATIVE_GARBAGE_STRS_SIZE \\\n\t(sizeof(num_garbage_negative_strs) / sizeof(num_garbage_negative_strs[0]))\n#define NUM_INVALID_STRS_SIZE \\\n\t(sizeof(num_invalid_strs) / sizeof(num_invalid_strs[0]))\n\n\n\nstatic int\ncan_parse_unsigned(uint64_t expected_result, enum cmdline_numtype type)\n{\n\tswitch (type) {\n\tcase UINT8:\n\t\tif (expected_result > UINT8_MAX)\n\t\t\treturn 0;\n\t\tbreak;\n\tcase UINT16:\n\t\tif (expected_result > UINT16_MAX)\n\t\t\treturn 0;\n\t\tbreak;\n\tcase UINT32:\n\t\tif (expected_result > UINT32_MAX)\n\t\t\treturn 0;\n\t\tbreak;\n\tcase INT8:\n\t\tif (expected_result > INT8_MAX)\n\t\t\treturn 0;\n\t\tbreak;\n\tcase INT16:\n\t\tif (expected_result > INT16_MAX)\n\t\t\treturn 0;\n\t\tbreak;\n\tcase INT32:\n\t\tif (expected_result > INT32_MAX)\n\t\t\treturn 0;\n\t\tbreak;\n\tcase INT64:\n\t\tif (expected_result > INT64_MAX)\n\t\t\treturn 0;\n\t\tbreak;\n\tdefault:\n\t\treturn 1;\n\t}\n\treturn 1;\n}\n\nstatic int\ncan_parse_signed(int64_t expected_result, enum cmdline_numtype type)\n{\n\tswitch (type) {\n\tcase UINT8:\n\t\tif (expected_result > UINT8_MAX || expected_result < 0)\n\t\t\treturn 0;\n\t\tbreak;\n\tcase UINT16:\n\t\tif (expected_result > UINT16_MAX || expected_result < 0)\n\t\t\treturn 0;\n\t\tbreak;\n\tcase UINT32:\n\t\tif (expected_result > UINT32_MAX || expected_result < 0)\n\t\t\treturn 0;\n\t\tbreak;\n\tcase UINT64:\n\t\tif (expected_result < 0)\n\t\t\treturn 0;\n\tcase INT8:\n\t\tif (expected_result > INT8_MAX || expected_result < INT8_MIN)\n\t\t\treturn 0;\n\t\tbreak;\n\tcase INT16:\n\t\tif (expected_result > INT16_MAX || expected_result < INT16_MIN)\n\t\t\treturn 0;\n\t\tbreak;\n\tcase INT32:\n\t\tif (expected_result > INT32_MAX || expected_result < INT32_MIN)\n\t\t\treturn 0;\n\t\tbreak;\n\tdefault:\n\t\treturn 1;\n\t}\n\treturn 1;\n}\n\n/* test invalid parameters */\nint\ntest_parse_num_invalid_param(void)\n{\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tuint32_t result;\n\tcmdline_parse_token_num_t token;\n\tint ret = 0;\n\n\t/* set up a token */\n\ttoken.num_data.type = UINT32;\n\n\t/* copy string to buffer */\n\tsnprintf(buf, sizeof(buf), \"%s\",\n\t\t\tnum_valid_positive_strs[0].str);\n\n\t/* try all null */\n\tret = cmdline_parse_num(NULL, NULL, NULL, 0);\n\tif (ret != -1) {\n\t\tprintf(\"Error: parser accepted null parameters!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* try null token */\n\tret = cmdline_parse_num(NULL, buf, (void*)&result, sizeof(result));\n\tif (ret != -1) {\n\t\tprintf(\"Error: parser accepted null token!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* try null buf */\n\tret = cmdline_parse_num((cmdline_parse_token_hdr_t*)&token, NULL,\n\t\t(void*)&result, sizeof(result));\n\tif (ret != -1) {\n\t\tprintf(\"Error: parser accepted null string!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* try null result */\n\tret = cmdline_parse_num((cmdline_parse_token_hdr_t*)&token, buf,\n\t\tNULL, 0);\n\tif (ret == -1) {\n\t\tprintf(\"Error: parser rejected null result!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* test help function */\n\tmemset(&buf, 0, sizeof(buf));\n\n\t/* try all null */\n\tret = cmdline_get_help_num(NULL, NULL, 0);\n\tif (ret != -1) {\n\t\tprintf(\"Error: help function accepted null parameters!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* try null token */\n\tret = cmdline_get_help_num(NULL, buf, sizeof(buf));\n\tif (ret != -1) {\n\t\tprintf(\"Error: help function accepted null token!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* coverage! */\n\tret = cmdline_get_help_num((cmdline_parse_token_hdr_t*)&token, buf, sizeof(buf));\n\tif (ret < 0) {\n\t\tprintf(\"Error: help function failed with valid parameters!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n/* test valid parameters but invalid data */\nint\ntest_parse_num_invalid_data(void)\n{\n\tenum cmdline_numtype type;\n\tint ret = 0;\n\tunsigned i;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tuint64_t result; /* pick largest buffer */\n\tcmdline_parse_token_num_t token;\n\n\t/* cycle through all possible parsed types */\n\tfor (type = UINT8; type <= INT64; type++) {\n\t\ttoken.num_data.type = type;\n\n\t\t/* test full strings */\n\t\tfor (i = 0; i < NUM_INVALID_STRS_SIZE; i++) {\n\n\t\t\tmemset(&result, 0, sizeof(uint64_t));\n\t\t\tmemset(&buf, 0, sizeof(buf));\n\n\t\t\tret = cmdline_parse_num((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\tnum_invalid_strs[i], (void*)&result, sizeof(result));\n\t\t\tif (ret != -1) {\n\t\t\t\t/* get some info about what we are trying to parse */\n\t\t\t\tcmdline_get_help_num((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\t\t\tbuf, sizeof(buf));\n\n\t\t\t\tprintf(\"Error: parsing %s as %s succeeded!\\n\",\n\t\t\t\t\t\tnum_invalid_strs[i], buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\n/* test valid parameters and data */\nint\ntest_parse_num_valid(void)\n{\n\tint ret = 0;\n\tenum cmdline_numtype type;\n\tunsigned i;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tuint64_t result;\n\tcmdline_parse_token_num_t token;\n\n\t/** valid strings **/\n\n\t/* cycle through all possible parsed types */\n\tfor (type = UINT8; type <= INT64; type++) {\n\t\ttoken.num_data.type = type;\n\n\t\t/* test positive strings */\n\t\tfor (i = 0; i < NUM_POSITIVE_STRS_SIZE; i++) {\n\t\t\tresult = 0;\n\t\t\tmemset(&buf, 0, sizeof(buf));\n\n\t\t\tcmdline_get_help_num((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\t\tbuf, sizeof(buf));\n\n\t\t\tret = cmdline_parse_num((cmdline_parse_token_hdr_t*) &token,\n\t\t\t\tnum_valid_positive_strs[i].str,\n\t\t\t\t(void*)&result, sizeof(result));\n\n\t\t\t/* if it should have passed but didn't, or if it should have failed but didn't */\n\t\t\tif ((ret < 0) == (can_parse_unsigned(num_valid_positive_strs[i].result, type) > 0)) {\n\t\t\t\tprintf(\"Error: parser behaves unexpectedly when parsing %s as %s!\\n\",\n\t\t\t\t\t\tnum_valid_positive_strs[i].str, buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\t/* check if result matches what it should have matched\n\t\t\t * since unsigned numbers don't care about number of bits, we can just convert\n\t\t\t * everything to uint64_t without any worries. */\n\t\t\tif (ret > 0 && num_valid_positive_strs[i].result != result) {\n\t\t\t\tprintf(\"Error: parsing %s as %s failed: result mismatch!\\n\",\n\t\t\t\t\t\tnum_valid_positive_strs[i].str, buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\n\t\t/* test negative strings */\n\t\tfor (i = 0; i < NUM_NEGATIVE_STRS_SIZE; i++) {\n\t\t\tresult = 0;\n\t\t\tmemset(&buf, 0, sizeof(buf));\n\n\t\t\tcmdline_get_help_num((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\t\tbuf, sizeof(buf));\n\n\t\t\tret = cmdline_parse_num((cmdline_parse_token_hdr_t*) &token,\n\t\t\t\tnum_valid_negative_strs[i].str,\n\t\t\t\t(void*)&result, sizeof(result));\n\n\t\t\t/* if it should have passed but didn't, or if it should have failed but didn't */\n\t\t\tif ((ret < 0) == (can_parse_signed(num_valid_negative_strs[i].result, type) > 0)) {\n\t\t\t\tprintf(\"Error: parser behaves unexpectedly when parsing %s as %s!\\n\",\n\t\t\t\t\t\tnum_valid_negative_strs[i].str, buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\t/* check if result matches what it should have matched\n\t\t\t * the result is signed in this case, so we have to account for that */\n\t\t\tif (ret > 0) {\n\t\t\t\t/* detect negative */\n\t\t\t\tswitch (type) {\n\t\t\t\tcase INT8:\n\t\t\t\t\tresult = (int8_t) result;\n\t\t\t\t\tbreak;\n\t\t\t\tcase INT16:\n\t\t\t\t\tresult = (int16_t) result;\n\t\t\t\t\tbreak;\n\t\t\t\tcase INT32:\n\t\t\t\t\tresult = (int32_t) result;\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (num_valid_negative_strs[i].result == (int64_t) result)\n\t\t\t\t\tcontinue;\n\t\t\t\tprintf(\"Error: parsing %s as %s failed: result mismatch!\\n\",\n\t\t\t\t\t\tnum_valid_negative_strs[i].str, buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\t/** garbage strings **/\n\n\t/* cycle through all possible parsed types */\n\tfor (type = UINT8; type <= INT64; type++) {\n\t\ttoken.num_data.type = type;\n\n\t\t/* test positive garbage strings */\n\t\tfor (i = 0; i < NUM_POSITIVE_GARBAGE_STRS_SIZE; i++) {\n\t\t\tresult = 0;\n\t\t\tmemset(&buf, 0, sizeof(buf));\n\n\t\t\tcmdline_get_help_num((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\t\tbuf, sizeof(buf));\n\n\t\t\tret = cmdline_parse_num((cmdline_parse_token_hdr_t*) &token,\n\t\t\t\tnum_garbage_positive_strs[i].str,\n\t\t\t\t(void*)&result, sizeof(result));\n\n\t\t\t/* if it should have passed but didn't, or if it should have failed but didn't */\n\t\t\tif ((ret < 0) == (can_parse_unsigned(num_garbage_positive_strs[i].result, type) > 0)) {\n\t\t\t\tprintf(\"Error: parser behaves unexpectedly when parsing %s as %s!\\n\",\n\t\t\t\t\t\tnum_garbage_positive_strs[i].str, buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\t/* check if result matches what it should have matched\n\t\t\t * since unsigned numbers don't care about number of bits, we can just convert\n\t\t\t * everything to uint64_t without any worries. */\n\t\t\tif (ret > 0 && num_garbage_positive_strs[i].result != result) {\n\t\t\t\tprintf(\"Error: parsing %s as %s failed: result mismatch!\\n\",\n\t\t\t\t\t\tnum_garbage_positive_strs[i].str, buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\n\t\t/* test negative strings */\n\t\tfor (i = 0; i < NUM_NEGATIVE_GARBAGE_STRS_SIZE; i++) {\n\t\t\tresult = 0;\n\t\t\tmemset(&buf, 0, sizeof(buf));\n\n\t\t\tcmdline_get_help_num((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\t\tbuf, sizeof(buf));\n\n\t\t\tret = cmdline_parse_num((cmdline_parse_token_hdr_t*) &token,\n\t\t\t\tnum_garbage_negative_strs[i].str,\n\t\t\t\t(void*)&result, sizeof(result));\n\n\t\t\t/* if it should have passed but didn't, or if it should have failed but didn't */\n\t\t\tif ((ret < 0) == (can_parse_signed(num_garbage_negative_strs[i].result, type) > 0)) {\n\t\t\t\tprintf(\"Error: parser behaves unexpectedly when parsing %s as %s!\\n\",\n\t\t\t\t\t\tnum_garbage_negative_strs[i].str, buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\t/* check if result matches what it should have matched\n\t\t\t * the result is signed in this case, so we have to account for that */\n\t\t\tif (ret > 0) {\n\t\t\t\t/* detect negative */\n\t\t\t\tswitch (type) {\n\t\t\t\tcase INT8:\n\t\t\t\t\tif (result & (INT8_MAX + 1))\n\t\t\t\t\t\tresult |= 0xFFFFFFFFFFFFFF00ULL;\n\t\t\t\t\tbreak;\n\t\t\t\tcase INT16:\n\t\t\t\t\tif (result & (INT16_MAX + 1))\n\t\t\t\t\t\tresult |= 0xFFFFFFFFFFFF0000ULL;\n\t\t\t\t\tbreak;\n\t\t\t\tcase INT32:\n\t\t\t\t\tif (result & (INT32_MAX + 1ULL))\n\t\t\t\t\t\tresult |= 0xFFFFFFFF00000000ULL;\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (num_garbage_negative_strs[i].result == (int64_t) result)\n\t\t\t\t\tcontinue;\n\t\t\t\tprintf(\"Error: parsing %s as %s failed: result mismatch!\\n\",\n\t\t\t\t\t\tnum_garbage_negative_strs[i].str, buf);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\tmemset(&buf, 0, sizeof(buf));\n\n\t/* coverage! */\n\tcmdline_get_help_num((cmdline_parse_token_hdr_t*)&token,\n\t\t\tbuf, sizeof(buf));\n\n\treturn 0;\n}\n" }, { "path": "app/test/test_cmdline_portlist.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n\n#include \"test_cmdline.h\"\n\nstruct portlist_str {\n\tconst char * str;\n\tuint32_t portmap;\n};\n\n/* valid strings */\nconst struct portlist_str portlist_valid_strs[] = {\n\t\t{\"0\", 0x1U },\n\t\t{\"0-10\", 0x7FFU},\n\t\t{\"10-20\", 0x1FFC00U},\n\t\t{\"all\", UINT32_MAX},\n\t\t{\"0,1,2,3\", 0xFU},\n\t\t{\"0,1-5\", 0x3FU},\n\t\t{\"0,0,0\", 0x1U},\n\t\t{\"31,0-10,15\", 0x800087FFU},\n\t\t{\"0000\", 0x1U},\n\t\t{\"00,01,02,03\", 0xFU},\n\t\t{\"000,001,002,003\", 0xFU},\n};\n\n/* valid strings but with garbage at the end.\n * these strings should still be valid because parser checks\n * for end of token, which is either a space/tab, a newline/return,\n * or a hash sign.\n */\n\nconst char * portlist_garbage_strs[] = {\n\t\t\"0-31 garbage\",\n\t\t\"0-31#garbage\",\n\t\t\"0-31\\0garbage\",\n\t\t\"0-31\\ngarbage\",\n\t\t\"0-31\\rgarbage\",\n\t\t\"0-31\\tgarbage\",\n\t\t\"0,1,2,3-31 garbage\",\n\t\t\"0,1,2,3-31#garbage\",\n\t\t\"0,1,2,3-31\\0garbage\",\n\t\t\"0,1,2,3-31\\ngarbage\",\n\t\t\"0,1,2,3-31\\rgarbage\",\n\t\t\"0,1,2,3-31\\tgarbage\",\n\t\t\"all garbage\",\n\t\t\"all#garbage\",\n\t\t\"all\\0garbage\",\n\t\t\"all\\ngarbage\",\n\t\t\"all\\rgarbage\",\n\t\t\"all\\tgarbage\",\n};\n\n/* invalid strings */\nconst char * portlist_invalid_strs[] = {\n\t\t/* valid syntax, invalid chars */\n\t\t\"A-B\",\n\t\t\"0-S\",\n\t\t\"1,2,3,4,Q\",\n\t\t\"A-4,3-15\",\n\t\t\"0-31invalid\",\n\t\t/* valid chars, invalid syntax */\n\t\t\"1, 2\",\n\t\t\"1- 4\",\n\t\t\",2\",\n\t\t\",2 \",\n\t\t\"-1, 4\",\n\t\t\"5-1\",\n\t\t\"2-\",\n\t\t/* misc */\n\t\t\"-\"\n\t\t\"a\",\n\t\t\"A\",\n\t\t\",\",\n\t\t\"#\",\n\t\t\" \",\n\t\t\"\\0\",\n\t\t\"\",\n\t\t/* too long */\n\t\t\"0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,\"\n\t\t\"0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,2\",\n};\n\n#define PORTLIST_VALID_STRS_SIZE \\\n\t(sizeof(portlist_valid_strs) / sizeof(portlist_valid_strs[0]))\n#define PORTLIST_GARBAGE_STRS_SIZE \\\n\t(sizeof(portlist_garbage_strs) / sizeof(portlist_garbage_strs[0]))\n#define PORTLIST_INVALID_STRS_SIZE \\\n\t(sizeof(portlist_invalid_strs) / sizeof(portlist_invalid_strs[0]))\n\n\n\n\n/* test invalid parameters */\nint\ntest_parse_portlist_invalid_param(void)\n{\n\tcmdline_portlist_t result;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tint ret;\n\n\tmemset(&buf, 0, sizeof(buf));\n\tmemset(&result, 0, sizeof(cmdline_portlist_t));\n\n\t/* try all null */\n\tret = cmdline_parse_portlist(NULL, NULL, NULL, 0);\n\tif (ret != -1) {\n\t\tprintf(\"Error: parser accepted null parameters!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* try null buf */\n\tret = cmdline_parse_portlist(NULL, NULL, (void*)&result,\n\t\tsizeof(result));\n\tif (ret != -1) {\n\t\tprintf(\"Error: parser accepted null string!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* try null result */\n\tret = cmdline_parse_portlist(NULL, portlist_valid_strs[0].str, NULL, 0);\n\tif (ret == -1) {\n\t\tprintf(\"Error: parser rejected null result!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* token is not used in ether_parse anyway so there's no point in\n\t * testing it */\n\n\t/* test help function */\n\n\t/* coverage! */\n\tret = cmdline_get_help_portlist(NULL, buf, sizeof(buf));\n\tif (ret < 0) {\n\t\tprintf(\"Error: help function failed with valid parameters!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* test valid parameters but invalid data */\nint\ntest_parse_portlist_invalid_data(void)\n{\n\tint ret = 0;\n\tunsigned i;\n\tcmdline_portlist_t result;\n\n\t/* test invalid strings */\n\tfor (i = 0; i < PORTLIST_INVALID_STRS_SIZE; i++) {\n\n\t\tmemset(&result, 0, sizeof(cmdline_portlist_t));\n\n\t\tret = cmdline_parse_portlist(NULL, portlist_invalid_strs[i],\n\t\t\t(void*)&result, sizeof(result));\n\t\tif (ret != -1) {\n\t\t\tprintf(\"Error: parsing %s succeeded!\\n\",\n\t\t\t\t\tportlist_invalid_strs[i]);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/* test valid parameters and data */\nint\ntest_parse_portlist_valid(void)\n{\n\tint ret = 0;\n\tunsigned i;\n\tcmdline_portlist_t result;\n\n\t/* test full strings */\n\tfor (i = 0; i < PORTLIST_VALID_STRS_SIZE; i++) {\n\n\t\tmemset(&result, 0, sizeof(cmdline_portlist_t));\n\n\t\tret = cmdline_parse_portlist(NULL, portlist_valid_strs[i].str,\n\t\t\t(void*)&result, sizeof(result));\n\t\tif (ret < 0) {\n\t\t\tprintf(\"Error: parsing %s failed!\\n\",\n\t\t\t\t\tportlist_valid_strs[i].str);\n\t\t\treturn -1;\n\t\t}\n\t\tif (result.map != portlist_valid_strs[i].portmap) {\n\t\t\tprintf(\"Error: parsing %s failed: map mismatch!\\n\",\n\t\t\t\t\tportlist_valid_strs[i].str);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* test garbage strings */\n\tfor (i = 0; i < PORTLIST_GARBAGE_STRS_SIZE; i++) {\n\n\t\tmemset(&result, 0, sizeof(cmdline_portlist_t));\n\n\t\tret = cmdline_parse_portlist(NULL, portlist_garbage_strs[i],\n\t\t\t(void*)&result, sizeof(result));\n\t\tif (ret < 0) {\n\t\t\tprintf(\"Error: parsing %s failed!\\n\",\n\t\t\t\t\tportlist_garbage_strs[i]);\n\t\t\treturn -1;\n\t\t}\n\t\tif (result.map != UINT32_MAX) {\n\t\t\tprintf(\"Error: parsing %s failed: map mismatch!\\n\",\n\t\t\t\t\tportlist_garbage_strs[i]);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n" }, { "path": "app/test/test_cmdline_string.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n\n#include \n#include \n\n#include \"test_cmdline.h\"\n\n/* structures needed to run tests */\n\nstruct string_elt_str {\n\tconst char * str;\t/* parsed string */\n\tconst char * result;\t/* expected string */\n\tint idx;\t/* position at which result is expected to be */\n};\n\nstruct string_elt_str string_elt_strs[] = {\n\t\t{\"one#two#three\", \"three\", 2},\n\t\t{\"one#two with spaces#three\", \"three\", 2},\n\t\t{\"one#two\\twith\\ttabs#three\", \"three\", 2},\n\t\t{\"one#two\\rwith\\rreturns#three\", \"three\", 2},\n\t\t{\"one#two\\nwith\\nnewlines#three\", \"three\", 2},\n\t\t{\"one#two#three\", \"one\", 0},\n\t\t{\"one#two#three\", \"two\", 1},\n\t\t{\"one#two\\0three\", \"two\", 1},\n\t\t{\"one#two with spaces#three\", \"two with spaces\", 1},\n\t\t{\"one#two\\twith\\ttabs#three\", \"two\\twith\\ttabs\", 1},\n\t\t{\"one#two\\rwith\\rreturns#three\", \"two\\rwith\\rreturns\", 1},\n\t\t{\"one#two\\nwith\\nnewlines#three\", \"two\\nwith\\nnewlines\", 1},\n};\n\n#if CMDLINE_TEST_BUFSIZE < STR_TOKEN_SIZE\n#undef CMDLINE_TEST_BUFSIZE\n#define CMDLINE_TEST_BUFSIZE STR_TOKEN_SIZE\n#endif\n\nstruct string_nb_str {\n\tconst char * str;\t/* parsed string */\n\tint nb_strs;\t/* expected number of strings in str */\n};\n\nstruct string_nb_str string_nb_strs[] = {\n\t\t{\"one#two#three\", 3},\n\t\t{\"one\", 1},\n\t\t{\"one# \\t two \\r # three \\n #four\", 4},\n};\n\n\n\nstruct string_parse_str {\n\tconst char * str;\t/* parsed string */\n\tconst char * fixed_str;\t/* parsing mode (any, fixed or multi) */\n\tconst char * result;\t/* expected result */\n};\n\nstruct string_parse_str string_parse_strs[] = {\n\t\t{\"one\", NULL, \"one\"},\t/* any string */\n\t\t{\"two\", \"one#two#three\", \"two\"},\t/* multiple choice string */\n\t\t{\"three\", \"three\", \"three\"},\t/* fixed string */\n\t\t{\"three\", \"one#two with\\rgarbage\\tcharacters\\n#three\", \"three\"},\n\t\t{\"two with\\rgarbage\\tcharacters\\n\",\n\t\t\t\t\"one#two with\\rgarbage\\tcharacters\\n#three\",\n\t\t\t\t\"two with\\rgarbage\\tcharacters\\n\"},\n};\n\n\n\nstruct string_invalid_str {\n\tconst char * str;\t/* parsed string */\n\tconst char * fixed_str;\t/* parsing mode (any, fixed or multi) */\n};\n\nstruct string_invalid_str string_invalid_strs[] = {\n\t\t{\"invalid\", \"one\"},\t/* fixed string */\n\t\t{\"invalid\", \"one#two#three\"},\t/* multiple choice string */\n\t\t{\"invalid\", \"invalidone\"},\t/* string that starts the same */\n\t\t{\"invalidone\", \"invalid\"},\t/* string that starts the same */\n\t\t{\"toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!\"\n\t\t \"toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!\"\n\t\t \"toolong!!!\", NULL },\n\t\t{\"toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!\"\n\t\t \"toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!\"\n\t\t \"toolong!!!\", \"fixed\" },\n\t\t{\"toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!\"\n\t\t \"toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!\"\n\t\t \"toolong!!!\", \"multi#choice#string\" },\n\t\t{\"invalid\",\n\t\t \"toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!\"\n\t\t \"toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!toolong!!!\"\n\t\t \"toolong!!!\" },\n\t\t {\"invalid\", \"\"},\n\t\t {\"\", \"invalid\"}\n};\n\n\n\nconst char * string_help_strs[] = {\n\t\tNULL,\n\t\t\"fixed_str\",\n\t\t\"multi#str\",\n};\n\n\n\n#define STRING_PARSE_STRS_SIZE \\\n\t(sizeof(string_parse_strs) / sizeof(string_parse_strs[0]))\n#define STRING_HELP_STRS_SIZE \\\n\t(sizeof(string_help_strs) / sizeof(string_help_strs[0]))\n#define STRING_ELT_STRS_SIZE \\\n\t(sizeof(string_elt_strs) / sizeof(string_elt_strs[0]))\n#define STRING_NB_STRS_SIZE \\\n\t(sizeof(string_nb_strs) / sizeof(string_nb_strs[0]))\n#define STRING_INVALID_STRS_SIZE \\\n\t(sizeof(string_invalid_strs) / sizeof(string_invalid_strs[0]))\n\n#define SMALL_BUF 8\n\n/* test invalid parameters */\nint\ntest_parse_string_invalid_param(void)\n{\n\tcmdline_parse_token_string_t token;\n\tint result;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\n\tmemset(&token, 0, sizeof(token));\n\n\tsnprintf(buf, sizeof(buf), \"buffer\");\n\n\t/* test null token */\n\tif (cmdline_get_help_string(\n\t\tNULL, buf, 0) != -1) {\n\t\tprintf(\"Error: function accepted null token!\\n\");\n\t\treturn -1;\n\t}\n\tif (cmdline_complete_get_elt_string(\n\t\t\tNULL, 0, buf, 0) != -1) {\n\t\tprintf(\"Error: function accepted null token!\\n\");\n\t\treturn -1;\n\t}\n\tif (cmdline_complete_get_nb_string(NULL) != -1) {\n\t\tprintf(\"Error: function accepted null token!\\n\");\n\t\treturn -1;\n\t}\n\tif (cmdline_parse_string(NULL, buf, NULL, 0) != -1) {\n\t\tprintf(\"Error: function accepted null token!\\n\");\n\t\treturn -1;\n\t}\n\t/* test null buffer */\n\tif (cmdline_complete_get_elt_string(\n\t\t\t(cmdline_parse_token_hdr_t*)&token, 0, NULL, 0) != -1) {\n\t\tprintf(\"Error: function accepted null buffer!\\n\");\n\t\treturn -1;\n\t}\n\tif (cmdline_parse_string(\n\t\t\t(cmdline_parse_token_hdr_t*)&token, NULL,\n\t\t\t(void*)&result, sizeof(result)) != -1) {\n\t\tprintf(\"Error: function accepted null buffer!\\n\");\n\t\treturn -1;\n\t}\n\tif (cmdline_get_help_string(\n\t\t\t(cmdline_parse_token_hdr_t*)&token, NULL, 0) != -1) {\n\t\tprintf(\"Error: function accepted null buffer!\\n\");\n\t\treturn -1;\n\t}\n\t/* test null result */\n\tif (cmdline_parse_string(\n\t\t\t(cmdline_parse_token_hdr_t*)&token, buf, NULL, 0) == -1) {\n\t\tprintf(\"Error: function rejected null result!\\n\");\n\t\treturn -1;\n\t}\n\t/* test negative index */\n\tif (cmdline_complete_get_elt_string(\n\t\t\t(cmdline_parse_token_hdr_t*)&token, -1, buf, 0) != -1) {\n\t\tprintf(\"Error: function accepted negative index!\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/* test valid parameters but invalid data */\nint\ntest_parse_string_invalid_data(void)\n{\n\tcmdline_parse_token_string_t token;\n\tcmdline_parse_token_string_t help_token;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tchar help_str[CMDLINE_TEST_BUFSIZE];\n\tchar small_buf[SMALL_BUF];\n\tunsigned i;\n\n\t/* test parsing invalid strings */\n\tfor (i = 0; i < STRING_INVALID_STRS_SIZE; i++) {\n\t\tmemset(&token, 0, sizeof(token));\n\t\tmemset(buf, 0, sizeof(buf));\n\n\t\t/* prepare test token data */\n\t\ttoken.string_data.str = string_invalid_strs[i].fixed_str;\n\n\t\tif (cmdline_parse_string((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\tstring_invalid_strs[i].str, (void*)buf,\n\t\t\t\tsizeof(buf)) != -1) {\n\t\t\tmemset(help_str, 0, sizeof(help_str));\n\t\t\tmemset(&help_token, 0, sizeof(help_token));\n\n\t\t\thelp_token.string_data.str = string_invalid_strs[i].fixed_str;\n\n\t\t\t/* get parse type so we can give a good error message */\n\t\t\tcmdline_get_help_string((cmdline_parse_token_hdr_t*)&token, help_str,\n\t\t\t\t\tsizeof(help_str));\n\n\t\t\tprintf(\"Error: parsing %s as %s succeeded!\\n\",\n\t\t\t\t\tstring_invalid_strs[i].str, help_str);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* misc tests (big comments signify test cases) */\n\tmemset(&token, 0, sizeof(token));\n\tmemset(small_buf, 0, sizeof(small_buf));\n\n\t/*\n\t * try to get element from a null token\n\t */\n\ttoken.string_data.str = NULL;\n\tif (cmdline_complete_get_elt_string(\n\t\t\t(cmdline_parse_token_hdr_t*)&token, 1,\n\t\t\tbuf, sizeof(buf)) != -1) {\n\t\tprintf(\"Error: getting token from null token string!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * try to get element into a buffer that is too small\n\t */\n\ttoken.string_data.str = \"too_small_buffer\";\n\tif (cmdline_complete_get_elt_string(\n\t\t\t(cmdline_parse_token_hdr_t*)&token, 0,\n\t\t\tsmall_buf, sizeof(small_buf)) != -1) {\n\t\tprintf(\"Error: writing token into too small a buffer succeeded!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * get help string written into a buffer smaller than help string\n\t * truncation should occur\n\t */\n\ttoken.string_data.str = NULL;\n\tif (cmdline_get_help_string(\n\t\t\t(cmdline_parse_token_hdr_t*)&token,\n\t\t\tsmall_buf, sizeof(small_buf)) == -1) {\n\t\tprintf(\"Error: writing help string into too small a buffer failed!\\n\");\n\t\treturn -1;\n\t}\n\t/* get help string for \"any string\" so we can compare it with small_buf */\n\tcmdline_get_help_string((cmdline_parse_token_hdr_t*)&token, help_str,\n\t\t\tsizeof(help_str));\n\tif (strncmp(small_buf, help_str, sizeof(small_buf) - 1)) {\n\t\tprintf(\"Error: help string mismatch!\\n\");\n\t\treturn -1;\n\t}\n\t/* check null terminator */\n\tif (small_buf[sizeof(small_buf) - 1] != '\\0') {\n\t\tprintf(\"Error: small buffer doesn't have a null terminator!\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * try to count tokens in a null token\n\t */\n\ttoken.string_data.str = NULL;\n\tif (cmdline_complete_get_nb_string(\n\t\t\t(cmdline_parse_token_hdr_t*)&token) != 0) {\n\t\tprintf(\"Error: getting token count from null token succeeded!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* test valid parameters and data */\nint\ntest_parse_string_valid(void)\n{\n\tcmdline_parse_token_string_t token;\n\tcmdline_parse_token_string_t help_token;\n\tchar buf[CMDLINE_TEST_BUFSIZE];\n\tchar help_str[CMDLINE_TEST_BUFSIZE];\n\tunsigned i;\n\n\t/* test parsing strings */\n\tfor (i = 0; i < STRING_PARSE_STRS_SIZE; i++) {\n\t\tmemset(&token, 0, sizeof(token));\n\t\tmemset(buf, 0, sizeof(buf));\n\n\t\ttoken.string_data.str = string_parse_strs[i].fixed_str;\n\n\t\tif (cmdline_parse_string((cmdline_parse_token_hdr_t*)&token,\n\t\t\t\tstring_parse_strs[i].str, (void*)buf,\n\t\t\t\tsizeof(buf)) < 0) {\n\n\t\t\t/* clean help data */\n\t\t\tmemset(&help_token, 0, sizeof(help_token));\n\t\t\tmemset(help_str, 0, sizeof(help_str));\n\n\t\t\t/* prepare help token */\n\t\t\thelp_token.string_data.str = string_parse_strs[i].fixed_str;\n\n\t\t\t/* get help string so that we get an informative error message */\n\t\t\tcmdline_get_help_string((cmdline_parse_token_hdr_t*)&token, help_str,\n\t\t\t\t\tsizeof(help_str));\n\n\t\t\tprintf(\"Error: parsing %s as %s failed!\\n\",\n\t\t\t\t\tstring_parse_strs[i].str, help_str);\n\t\t\treturn -1;\n\t\t}\n\t\tif (strncmp(buf, string_parse_strs[i].result,\n\t\t\t\tsizeof(string_parse_strs[i].result) - 1) != 0) {\n\t\t\tprintf(\"Error: result mismatch!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* get number of string tokens and verify it's correct */\n\tfor (i = 0; i < STRING_NB_STRS_SIZE; i++) {\n\t\tmemset(&token, 0, sizeof(token));\n\n\t\ttoken.string_data.str = string_nb_strs[i].str;\n\n\t\tif (cmdline_complete_get_nb_string(\n\t\t\t\t(cmdline_parse_token_hdr_t*)&token) <\n\t\t\t\tstring_nb_strs[i].nb_strs) {\n\t\t\tprintf(\"Error: strings count mismatch!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* get token at specified position and verify it's correct */\n\tfor (i = 0; i < STRING_ELT_STRS_SIZE; i++) {\n\t\tmemset(&token, 0, sizeof(token));\n\t\tmemset(buf, 0, sizeof(buf));\n\n\t\ttoken.string_data.str = string_elt_strs[i].str;\n\n\t\tif (cmdline_complete_get_elt_string(\n\t\t\t\t(cmdline_parse_token_hdr_t*)&token, string_elt_strs[i].idx,\n\t\t\t\tbuf, sizeof(buf)) < 0) {\n\t\t\tprintf(\"Error: getting string element failed!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tif (strncmp(buf, string_elt_strs[i].result,\n\t\t\t\tsizeof(buf)) != 0) {\n\t\t\tprintf(\"Error: result mismatch!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* cover all cases with help strings */\n\tfor (i = 0; i < STRING_HELP_STRS_SIZE; i++) {\n\t\tmemset(&help_token, 0, sizeof(help_token));\n\t\tmemset(help_str, 0, sizeof(help_str));\n\t\thelp_token.string_data.str = string_help_strs[i];\n\t\tif (cmdline_get_help_string((cmdline_parse_token_hdr_t*)&help_token,\n\t\t\t\thelp_str, sizeof(help_str)) < 0) {\n\t\t\tprintf(\"Error: help operation failed!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n" }, { "path": "app/test/test_common.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#define MAX_NUM 1 << 20\n\n#define FAIL(x)\\\n\t{printf(x \"() test failed!\\n\");\\\n\treturn -1;}\n\n/* this is really a sanity check */\nstatic int\ntest_macros(int __rte_unused unused_parm)\n{\n#define SMALLER 0x1000U\n#define BIGGER 0x2000U\n#define PTR_DIFF BIGGER - SMALLER\n#define FAIL_MACRO(x)\\\n\t{printf(#x \"() test failed!\\n\");\\\n\treturn -1;}\n\n\tuintptr_t unused = 0;\n\n\tRTE_SET_USED(unused);\n\n\tif ((uintptr_t)RTE_PTR_ADD(SMALLER, PTR_DIFF) != BIGGER)\n\t\tFAIL_MACRO(RTE_PTR_ADD);\n\tif ((uintptr_t)RTE_PTR_SUB(BIGGER, PTR_DIFF) != SMALLER)\n\t\tFAIL_MACRO(RTE_PTR_SUB);\n\tif (RTE_PTR_DIFF(BIGGER, SMALLER) != PTR_DIFF)\n\t\tFAIL_MACRO(RTE_PTR_DIFF);\n\tif (RTE_MAX(SMALLER, BIGGER) != BIGGER)\n\t\tFAIL_MACRO(RTE_MAX);\n\tif (RTE_MIN(SMALLER, BIGGER) != SMALLER)\n\t\tFAIL_MACRO(RTE_MIN);\n\n\tif (strncmp(RTE_STR(test), \"test\", sizeof(\"test\")))\n\t\tFAIL_MACRO(RTE_STR);\n\n\treturn 0;\n}\n\nstatic int\ntest_misc(void)\n{\n\tchar memdump[] = \"memdump_test\";\n\tif (rte_bsf32(129))\n\t\tFAIL(\"rte_bsf32\");\n\n\trte_memdump(stdout, \"test\", memdump, sizeof(memdump));\n\trte_hexdump(stdout, \"test\", memdump, sizeof(memdump));\n\n\trte_pause();\n\n\treturn 0;\n}\n\nstatic int\ntest_align(void)\n{\n#define FAIL_ALIGN(x, i, p)\\\n\t{printf(x \"() test failed: %u %u\\n\", i, p);\\\n\treturn -1;}\n#define ERROR_FLOOR(res, i, pow) \\\n\t\t(res % pow) || \t\t\t\t\t\t/* check if not aligned */ \\\n\t\t((res / pow) != (i / pow)) \t\t/* check if correct alignment */\n#define ERROR_CEIL(res, i, pow) \\\n\t\t(res % pow) ||\t\t\t\t\t\t/* check if not aligned */ \\\n\t\t\t((i % pow) == 0 ?\t\t\t\t/* check if ceiling is invoked */ \\\n\t\t\tval / pow != i / pow :\t\t\t/* if aligned */ \\\n\t\t\tval / pow != (i / pow) + 1)\t\t/* if not aligned, hence +1 */\n\n\tuint32_t i, p, val;\n\n\tfor (i = 1, p = 1; i <= MAX_NUM; i ++) {\n\t\tif (rte_align32pow2(i) != p)\n\t\t\tFAIL_ALIGN(\"rte_align32pow2\", i, p);\n\t\tif (i == p)\n\t\t\tp <<= 1;\n\t}\n\n\tfor (p = 2; p <= MAX_NUM; p <<= 1) {\n\n\t\tif (!rte_is_power_of_2(p))\n\t\t\tFAIL(\"rte_is_power_of_2\");\n\n\t\tfor (i = 1; i <= MAX_NUM; i++) {\n\t\t\t/* align floor */\n\t\t\tif (RTE_ALIGN_FLOOR((uintptr_t)i, p) % p)\n\t\t\t\tFAIL_ALIGN(\"RTE_ALIGN_FLOOR\", i, p);\n\n\t\t\tval = RTE_PTR_ALIGN_FLOOR((uintptr_t) i, p);\n\t\t\tif (ERROR_FLOOR(val, i, p))\n\t\t\t\tFAIL_ALIGN(\"RTE_PTR_ALIGN_FLOOR\", i, p);\n\n\t\t\tval = RTE_ALIGN_FLOOR(i, p);\n\t\t\tif (ERROR_FLOOR(val, i, p))\n\t\t\t\tFAIL_ALIGN(\"RTE_ALIGN_FLOOR\", i, p);\n\n\t\t\t/* align ceiling */\n\t\t\tval = RTE_PTR_ALIGN((uintptr_t) i, p);\n\t\t\tif (ERROR_CEIL(val, i, p))\n\t\t\t\tFAIL_ALIGN(\"RTE_PTR_ALIGN\", i, p);\n\n\t\t\tval = RTE_ALIGN(i, p);\n\t\t\tif (ERROR_CEIL(val, i, p))\n\t\t\t\tFAIL_ALIGN(\"RTE_ALIGN\", i, p);\n\n\t\t\tval = RTE_ALIGN_CEIL(i, p);\n\t\t\tif (ERROR_CEIL(val, i, p))\n\t\t\t\tFAIL_ALIGN(\"RTE_ALIGN_CEIL\", i, p);\n\n\t\t\tval = RTE_PTR_ALIGN_CEIL((uintptr_t)i, p);\n\t\t\tif (ERROR_CEIL(val, i, p))\n\t\t\t\tFAIL_ALIGN(\"RTE_PTR_ALIGN_CEIL\", i, p);\n\n\t\t\t/* by this point we know that val is aligned to p */\n\t\t\tif (!rte_is_aligned((void*)(uintptr_t) val, p))\n\t\t\t\tFAIL(\"rte_is_aligned\");\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\ntest_common(void)\n{\n\tint ret = 0;\n\tret |= test_align();\n\tret |= test_macros(0);\n\tret |= test_misc();\n\n\treturn ret;\n}\n\nstatic struct test_command common_cmd = {\n\t.command = \"common_autotest\",\n\t.callback = test_common,\n};\nREGISTER_TEST_COMMAND(common_cmd);\n" }, { "path": "app/test/test_cpuflags.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n\n/* convenience define */\n#define CHECK_FOR_FLAG(x) \\\n\t\t\tresult = rte_cpu_get_flag_enabled(x); \\\n\t\t\tprintf(\"%s\\n\", cpu_flag_result(result)); \\\n\t\t\tif (result == -ENOENT) \\\n\t\t\t\treturn -1;\n\n/*\n * Helper function to display result\n */\nstatic inline const char *\ncpu_flag_result(int result)\n{\n\tswitch (result) {\n\tcase 0:\n\t\treturn \"NOT PRESENT\";\n\tcase 1:\n\t\treturn \"OK\";\n\tdefault:\n\t\treturn \"ERROR\";\n\t}\n}\n\n\n\n/*\n * CPUID test\n * ===========\n *\n * - Check flags from different registers with rte_cpu_get_flag_enabled()\n * - Check if register and CPUID functions fail properly\n */\n\nstatic int\ntest_cpuflags(void)\n{\n\tint result;\n\tprintf(\"\\nChecking for flags from different registers...\\n\");\n\n#ifdef RTE_ARCH_PPC_64\n\tprintf(\"Check for PPC64:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_PPC64);\n\n\tprintf(\"Check for PPC32:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_PPC32);\n\n\tprintf(\"Check for VSX:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_VSX);\n\n\tprintf(\"Check for DFP:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_DFP);\n\n\tprintf(\"Check for FPU:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_FPU);\n\n\tprintf(\"Check for SMT:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_SMT);\n\n\tprintf(\"Check for MMU:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_MMU);\n\n\tprintf(\"Check for ALTIVEC:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_ALTIVEC);\n\n\tprintf(\"Check for ARCH_2_06:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_ARCH_2_06);\n\n\tprintf(\"Check for ARCH_2_07:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_ARCH_2_07);\n\n\tprintf(\"Check for ICACHE_SNOOP:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_ICACHE_SNOOP);\n#endif\n\n#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686)\n\tprintf(\"Check for SSE:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_SSE);\n\n\tprintf(\"Check for SSE2:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_SSE2);\n\n\tprintf(\"Check for SSE3:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_SSE3);\n\n\tprintf(\"Check for SSE4.1:\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_SSE4_1);\n\n\tprintf(\"Check for SSE4.2:\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_SSE4_2);\n\n\tprintf(\"Check for AVX:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_AVX);\n\n\tprintf(\"Check for AVX2:\\t\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_AVX2);\n\n\tprintf(\"Check for TRBOBST:\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_TRBOBST);\n\n\tprintf(\"Check for ENERGY_EFF:\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_ENERGY_EFF);\n\n\tprintf(\"Check for LAHF_SAHF:\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_LAHF_SAHF);\n\n\tprintf(\"Check for 1GB_PG:\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_1GB_PG);\n\n\tprintf(\"Check for INVTSC:\\t\");\n\tCHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);\n#endif\n\n\t/*\n\t * Check if invalid data is handled properly\n\t */\n\tprintf(\"\\nCheck for invalid flag:\\t\");\n\tresult = rte_cpu_get_flag_enabled(RTE_CPUFLAG_NUMFLAGS);\n\tprintf(\"%s\\n\", cpu_flag_result(result));\n\tif (result != -ENOENT)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic struct test_command cpuflags_cmd = {\n\t.command = \"cpuflags_autotest\",\n\t.callback = test_cpuflags,\n};\nREGISTER_TEST_COMMAND(cpuflags_cmd);\n" }, { "path": "app/test/test_cycles.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n\n#include \"test.h\"\n\n#define N 10000\n\n/*\n * Cycles test\n * ===========\n *\n * - Loop N times and check that the timer always increments and\n * never decrements during this loop.\n *\n * - Wait one second using rte_usleep() and check that the increment\n * of cycles is correct with regard to the frequency of the timer.\n */\n\nstatic int\ntest_cycles(void)\n{\n\tunsigned i;\n\tuint64_t start_cycles, cycles, prev_cycles;\n\tuint64_t hz = rte_get_timer_hz();\n\tuint64_t max_inc = (hz / 100); /* 10 ms max between 2 reads */\n\n\t/* check that the timer is always incrementing */\n\tstart_cycles = rte_get_timer_cycles();\n\tprev_cycles = start_cycles;\n\tfor (i=0; i max_inc) {\n\t\t\tprintf(\"increment too high or going backwards\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tprev_cycles = cycles;\n\t}\n\n\t/* check that waiting 1 second is precise */\n\tprev_cycles = rte_get_timer_cycles();\n\trte_delay_us(1000000);\n\tcycles = rte_get_timer_cycles();\n\n\tif ((uint64_t)(cycles - prev_cycles) > (hz + max_inc)) {\n\t\tprintf(\"delay_us is not accurate: too long\\n\");\n\t\treturn -1;\n\t}\n\tif ((uint64_t)(cycles - prev_cycles) < (hz - max_inc)) {\n\t\tprintf(\"delay_us is not accurate: too short\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic struct test_command cycles_cmd = {\n\t.command = \"cycles_autotest\",\n\t.callback = test_cycles,\n};\nREGISTER_TEST_COMMAND(cycles_cmd);\n" }, { "path": "app/test/test_debug.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"test.h\"\n\n/*\n * Debug test\n * ==========\n */\n\n/* use fork() to test rte_panic() */\nstatic int\ntest_panic(void)\n{\n\tint pid;\n\tint status;\n\n\tpid = fork();\n\n\tif (pid == 0)\n\t\trte_panic(\"Test Debug\\n\");\n\telse if (pid < 0){\n\t\tprintf(\"Fork Failed\\n\");\n\t\treturn -1;\n\t}\n\twait(&status);\n\tif(status == 0){\n\t\tprintf(\"Child process terminated normally!\\n\");\n\t\treturn -1;\n\t} else\n\t\tprintf(\"Child process terminated as expected - Test passed!\\n\");\n\n\treturn 0;\n}\n\n/* use fork() to test rte_exit() */\nstatic int\ntest_exit_val(int exit_val)\n{\n\tint pid;\n\tint status;\n\n\tpid = fork();\n\n\tif (pid == 0)\n\t\trte_exit(exit_val, __func__);\n\telse if (pid < 0){\n\t\tprintf(\"Fork Failed\\n\");\n\t\treturn -1;\n\t}\n\twait(&status);\n\tprintf(\"Child process status: %d\\n\", status);\n#ifndef RTE_EAL_ALWAYS_PANIC_ON_ERROR\n\tif(!WIFEXITED(status) || WEXITSTATUS(status) != (uint8_t)exit_val){\n\t\tprintf(\"Child process terminated with incorrect status (expected = %d)!\\n\",\n\t\t\t\texit_val);\n\t\treturn -1;\n\t}\n#endif\n\treturn 0;\n}\n\nstatic int\ntest_exit(void)\n{\n\tint test_vals[] = { 0, 1, 2, 255, -1 };\n\tunsigned i;\n\tfor (i = 0; i < sizeof(test_vals) / sizeof(test_vals[0]); i++){\n\t\tif (test_exit_val(test_vals[i]) < 0)\n\t\t\treturn -1;\n\t}\n\tprintf(\"%s Passed\\n\", __func__);\n\treturn 0;\n}\n\nstatic void\ndummy_app_usage(const char *progname)\n{\n\tRTE_SET_USED(progname);\n}\n\nstatic int\ntest_usage(void)\n{\n\tif (rte_set_application_usage_hook(dummy_app_usage) != NULL) {\n\t\tprintf(\"Non-NULL value returned for initial usage hook\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_set_application_usage_hook(NULL) != dummy_app_usage) {\n\t\tprintf(\"Incorrect value returned for application usage hook\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic int\ntest_debug(void)\n{\n\trte_dump_stack();\n\trte_dump_registers();\n\tif (test_panic() < 0)\n\t\treturn -1;\n\tif (test_exit() < 0)\n\t\treturn -1;\n\tif (test_usage() < 0)\n\t\treturn -1;\n\treturn 0;\n}\n\nstatic struct test_command debug_cmd = {\n\t.command = \"debug_autotest\",\n\t.callback = test_debug,\n};\nREGISTER_TEST_COMMAND(debug_cmd);\n" }, { "path": "app/test/test_devargs.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright 2014 6WIND S.A.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A nor the names of its contributors\n * may be used to endorse or promote products derived from this\n * software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \"test.h\"\n\n/* clear devargs list that was modified by the test */\nstatic void free_devargs_list(void)\n{\n\tstruct rte_devargs *devargs;\n\n\twhile (!TAILQ_EMPTY(&devargs_list)) {\n\t\tdevargs = TAILQ_FIRST(&devargs_list);\n\t\tTAILQ_REMOVE(&devargs_list, devargs, next);\n\t\tif (devargs->args)\n\t\t\tfree(devargs->args);\n\t\tfree(devargs);\n\t}\n}\n\nstatic int\ntest_devargs(void)\n{\n\tstruct rte_devargs_list save_devargs_list;\n\tstruct rte_devargs *devargs;\n\n\t/* save the real devargs_list, it is restored at the end of the test */\n\tsave_devargs_list = devargs_list;\n\tTAILQ_INIT(&devargs_list);\n\n\t/* test valid cases */\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_WHITELISTED_PCI, \"08:00.1\") < 0)\n\t\tgoto fail;\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_WHITELISTED_PCI, \"0000:5:00.0\") < 0)\n\t\tgoto fail;\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_BLACKLISTED_PCI, \"04:00.0,arg=val\") < 0)\n\t\tgoto fail;\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_BLACKLISTED_PCI, \"0000:01:00.1\") < 0)\n\t\tgoto fail;\n\tif (rte_eal_devargs_type_count(RTE_DEVTYPE_WHITELISTED_PCI) != 2)\n\t\tgoto fail;\n\tif (rte_eal_devargs_type_count(RTE_DEVTYPE_BLACKLISTED_PCI) != 2)\n\t\tgoto fail;\n\tif (rte_eal_devargs_type_count(RTE_DEVTYPE_VIRTUAL) != 0)\n\t\tgoto fail;\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_VIRTUAL, \"eth_ring0\") < 0)\n\t\tgoto fail;\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_VIRTUAL, \"eth_ring1,key=val,k2=val2\") < 0)\n\t\tgoto fail;\n\tif (rte_eal_devargs_type_count(RTE_DEVTYPE_VIRTUAL) != 2)\n\t\tgoto fail;\n\tfree_devargs_list();\n\n\t/* check virtual device with argument parsing */\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_VIRTUAL, \"eth_ring1,k1=val,k2=val2\") < 0)\n\t\tgoto fail;\n\tdevargs = TAILQ_FIRST(&devargs_list);\n\tif (strncmp(devargs->virtual.drv_name, \"eth_ring1\",\n\t\t\tsizeof(devargs->virtual.drv_name)) != 0)\n\t\tgoto fail;\n\tif (!devargs->args || strcmp(devargs->args, \"k1=val,k2=val2\") != 0)\n\t\tgoto fail;\n\tfree_devargs_list();\n\n\t/* check PCI device with empty argument parsing */\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_WHITELISTED_PCI, \"04:00.1\") < 0)\n\t\tgoto fail;\n\tdevargs = TAILQ_FIRST(&devargs_list);\n\tif (devargs->pci.addr.domain != 0 ||\n\t\tdevargs->pci.addr.bus != 4 ||\n\t\tdevargs->pci.addr.devid != 0 ||\n\t\tdevargs->pci.addr.function != 1)\n\t\tgoto fail;\n\tif (!devargs->args || strcmp(devargs->args, \"\") != 0)\n\t\tgoto fail;\n\tfree_devargs_list();\n\n\t/* test error case: bad PCI address */\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_WHITELISTED_PCI, \"08:1\") == 0)\n\t\tgoto fail;\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_WHITELISTED_PCI, \"00.1\") == 0)\n\t\tgoto fail;\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_WHITELISTED_PCI, \"foo\") == 0)\n\t\tgoto fail;\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_WHITELISTED_PCI, \",\") == 0)\n\t\tgoto fail;\n\tif (rte_eal_devargs_add(RTE_DEVTYPE_WHITELISTED_PCI, \"000f:0:0\") == 0)\n\t\tgoto fail;\n\n\tdevargs_list = save_devargs_list;\n\treturn 0;\n\n fail:\n\tfree_devargs_list();\n\tdevargs_list = save_devargs_list;\n\treturn -1;\n}\n\nstatic struct test_command devargs_cmd = {\n\t.command = \"devargs_autotest\",\n\t.callback = test_devargs,\n};\nREGISTER_TEST_COMMAND(devargs_cmd);\n" }, { "path": "app/test/test_distributor.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"test.h\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define ITER_POWER 20 /* log 2 of how many iterations we do when timing. */\n#define BURST 32\n#define BIG_BATCH 1024\n\n/* statics - all zero-initialized by default */\nstatic volatile int quit; /**< general quit variable for all threads */\nstatic volatile int zero_quit; /**< var for when we just want thr0 to quit*/\nstatic volatile unsigned worker_idx;\n\nstruct worker_stats {\n\tvolatile unsigned handled_packets;\n} __rte_cache_aligned;\nstruct worker_stats worker_stats[RTE_MAX_LCORE];\n\n/* returns the total count of the number of packets handled by the worker\n * functions given below.\n */\nstatic inline unsigned\ntotal_packet_count(void)\n{\n\tunsigned i, count = 0;\n\tfor (i = 0; i < worker_idx; i++)\n\t\tcount += worker_stats[i].handled_packets;\n\treturn count;\n}\n\n/* resets the packet counts for a new test */\nstatic inline void\nclear_packet_count(void)\n{\n\tmemset(&worker_stats, 0, sizeof(worker_stats));\n}\n\n/* this is the basic worker function for sanity test\n * it does nothing but return packets and count them.\n */\nstatic int\nhandle_work(void *arg)\n{\n\tstruct rte_mbuf *pkt = NULL;\n\tstruct rte_distributor *d = arg;\n\tunsigned count = 0;\n\tunsigned id = __sync_fetch_and_add(&worker_idx, 1);\n\n\tpkt = rte_distributor_get_pkt(d, id, NULL);\n\twhile (!quit) {\n\t\tworker_stats[id].handled_packets++, count++;\n\t\tpkt = rte_distributor_get_pkt(d, id, pkt);\n\t}\n\tworker_stats[id].handled_packets++, count++;\n\trte_distributor_return_pkt(d, id, pkt);\n\treturn 0;\n}\n\n/* do basic sanity testing of the distributor. This test tests the following:\n * - send 32 packets through distributor with the same tag and ensure they\n * all go to the one worker\n * - send 32 packets throught the distributor with two different tags and\n * verify that they go equally to two different workers.\n * - send 32 packets with different tags through the distributors and\n * just verify we get all packets back.\n * - send 1024 packets through the distributor, gathering the returned packets\n * as we go. Then verify that we correctly got all 1024 pointers back again,\n * not necessarily in the same order (as different flows).\n */\nstatic int\nsanity_test(struct rte_distributor *d, struct rte_mempool *p)\n{\n\tstruct rte_mbuf *bufs[BURST];\n\tunsigned i;\n\n\tprintf(\"=== Basic distributor sanity tests ===\\n\");\n\tclear_packet_count();\n\tif (rte_mempool_get_bulk(p, (void *)bufs, BURST) != 0) {\n\t\tprintf(\"line %d: Error getting mbufs from pool\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\n\t/* now set all hash values in all buffers to zero, so all pkts go to the\n\t * one worker thread */\n\tfor (i = 0; i < BURST; i++)\n\t\tbufs[i]->hash.usr = 0;\n\n\trte_distributor_process(d, bufs, BURST);\n\trte_distributor_flush(d);\n\tif (total_packet_count() != BURST) {\n\t\tprintf(\"Line %d: Error, not all packets flushed. \"\n\t\t\t\t\"Expected %u, got %u\\n\",\n\t\t\t\t__LINE__, BURST, total_packet_count());\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < rte_lcore_count() - 1; i++)\n\t\tprintf(\"Worker %u handled %u packets\\n\", i,\n\t\t\t\tworker_stats[i].handled_packets);\n\tprintf(\"Sanity test with all zero hashes done.\\n\");\n\tif (worker_stats[0].handled_packets != BURST)\n\t\treturn -1;\n\n\t/* pick two flows and check they go correctly */\n\tif (rte_lcore_count() >= 3) {\n\t\tclear_packet_count();\n\t\tfor (i = 0; i < BURST; i++)\n\t\t\tbufs[i]->hash.usr = (i & 1) << 8;\n\n\t\trte_distributor_process(d, bufs, BURST);\n\t\trte_distributor_flush(d);\n\t\tif (total_packet_count() != BURST) {\n\t\t\tprintf(\"Line %d: Error, not all packets flushed. \"\n\t\t\t\t\t\"Expected %u, got %u\\n\",\n\t\t\t\t\t__LINE__, BURST, total_packet_count());\n\t\t\treturn -1;\n\t\t}\n\n\t\tfor (i = 0; i < rte_lcore_count() - 1; i++)\n\t\t\tprintf(\"Worker %u handled %u packets\\n\", i,\n\t\t\t\t\tworker_stats[i].handled_packets);\n\t\tprintf(\"Sanity test with two hash values done\\n\");\n\n\t\tif (worker_stats[0].handled_packets != 16 ||\n\t\t\t\tworker_stats[1].handled_packets != 16)\n\t\t\treturn -1;\n\t}\n\n\t/* give a different hash value to each packet,\n\t * so load gets distributed */\n\tclear_packet_count();\n\tfor (i = 0; i < BURST; i++)\n\t\tbufs[i]->hash.usr = i;\n\n\trte_distributor_process(d, bufs, BURST);\n\trte_distributor_flush(d);\n\tif (total_packet_count() != BURST) {\n\t\tprintf(\"Line %d: Error, not all packets flushed. \"\n\t\t\t\t\"Expected %u, got %u\\n\",\n\t\t\t\t__LINE__, BURST, total_packet_count());\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < rte_lcore_count() - 1; i++)\n\t\tprintf(\"Worker %u handled %u packets\\n\", i,\n\t\t\t\tworker_stats[i].handled_packets);\n\tprintf(\"Sanity test with non-zero hashes done\\n\");\n\n\trte_mempool_put_bulk(p, (void *)bufs, BURST);\n\n\t/* sanity test with BIG_BATCH packets to ensure they all arrived back\n\t * from the returned packets function */\n\tclear_packet_count();\n\tstruct rte_mbuf *many_bufs[BIG_BATCH], *return_bufs[BIG_BATCH];\n\tunsigned num_returned = 0;\n\n\t/* flush out any remaining packets */\n\trte_distributor_flush(d);\n\trte_distributor_clear_returns(d);\n\tif (rte_mempool_get_bulk(p, (void *)many_bufs, BIG_BATCH) != 0) {\n\t\tprintf(\"line %d: Error getting mbufs from pool\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\tfor (i = 0; i < BIG_BATCH; i++)\n\t\tmany_bufs[i]->hash.usr = i << 2;\n\n\tfor (i = 0; i < BIG_BATCH/BURST; i++) {\n\t\trte_distributor_process(d, &many_bufs[i*BURST], BURST);\n\t\tnum_returned += rte_distributor_returned_pkts(d,\n\t\t\t\t&return_bufs[num_returned],\n\t\t\t\tBIG_BATCH - num_returned);\n\t}\n\trte_distributor_flush(d);\n\tnum_returned += rte_distributor_returned_pkts(d,\n\t\t\t&return_bufs[num_returned], BIG_BATCH - num_returned);\n\n\tif (num_returned != BIG_BATCH) {\n\t\tprintf(\"line %d: Number returned is not the same as \"\n\t\t\t\t\"number sent\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\t/* big check - make sure all packets made it back!! */\n\tfor (i = 0; i < BIG_BATCH; i++) {\n\t\tunsigned j;\n\t\tstruct rte_mbuf *src = many_bufs[i];\n\t\tfor (j = 0; j < BIG_BATCH; j++)\n\t\t\tif (return_bufs[j] == src)\n\t\t\t\tbreak;\n\n\t\tif (j == BIG_BATCH) {\n\t\t\tprintf(\"Error: could not find source packet #%u\\n\", i);\n\t\t\treturn -1;\n\t\t}\n\t}\n\tprintf(\"Sanity test of returned packets done\\n\");\n\n\trte_mempool_put_bulk(p, (void *)many_bufs, BIG_BATCH);\n\n\tprintf(\"\\n\");\n\treturn 0;\n}\n\n\n/* to test that the distributor does not lose packets, we use this worker\n * function which frees mbufs when it gets them. The distributor thread does\n * the mbuf allocation. If distributor drops packets we'll eventually run out\n * of mbufs.\n */\nstatic int\nhandle_work_with_free_mbufs(void *arg)\n{\n\tstruct rte_mbuf *pkt = NULL;\n\tstruct rte_distributor *d = arg;\n\tunsigned count = 0;\n\tunsigned id = __sync_fetch_and_add(&worker_idx, 1);\n\n\tpkt = rte_distributor_get_pkt(d, id, NULL);\n\twhile (!quit) {\n\t\tworker_stats[id].handled_packets++, count++;\n\t\trte_pktmbuf_free(pkt);\n\t\tpkt = rte_distributor_get_pkt(d, id, pkt);\n\t}\n\tworker_stats[id].handled_packets++, count++;\n\trte_distributor_return_pkt(d, id, pkt);\n\treturn 0;\n}\n\n/* Perform a sanity test of the distributor with a large number of packets,\n * where we allocate a new set of mbufs for each burst. The workers then\n * free the mbufs. This ensures that we don't have any packet leaks in the\n * library.\n */\nstatic int\nsanity_test_with_mbuf_alloc(struct rte_distributor *d, struct rte_mempool *p)\n{\n\tunsigned i;\n\tstruct rte_mbuf *bufs[BURST];\n\n\tprintf(\"=== Sanity test with mbuf alloc/free ===\\n\");\n\tclear_packet_count();\n\tfor (i = 0; i < ((1<hash.usr = (i+j) << 1;\n\t\t\trte_mbuf_refcnt_set(bufs[j], 1);\n\t\t}\n\n\t\trte_distributor_process(d, bufs, BURST);\n\t}\n\n\trte_distributor_flush(d);\n\tif (total_packet_count() < (1<hash.usr = 0;\n\n\trte_distributor_process(d, bufs, BURST);\n\t/* at this point, we will have processed some packets and have a full\n\t * backlog for the other ones at worker 0.\n\t */\n\n\t/* get more buffers to queue up, again setting them to the same flow */\n\tif (rte_mempool_get_bulk(p, (void *)bufs, BURST) != 0) {\n\t\tprintf(\"line %d: Error getting mbufs from pool\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\tfor (i = 0; i < BURST; i++)\n\t\tbufs[i]->hash.usr = 0;\n\n\t/* get worker zero to quit */\n\tzero_quit = 1;\n\trte_distributor_process(d, bufs, BURST);\n\n\t/* flush the distributor */\n\trte_distributor_flush(d);\n\tif (total_packet_count() != BURST * 2) {\n\t\tprintf(\"Line %d: Error, not all packets flushed. \"\n\t\t\t\t\"Expected %u, got %u\\n\",\n\t\t\t\t__LINE__, BURST * 2, total_packet_count());\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < rte_lcore_count() - 1; i++)\n\t\tprintf(\"Worker %u handled %u packets\\n\", i,\n\t\t\t\tworker_stats[i].handled_packets);\n\n\tprintf(\"Sanity test with worker shutdown passed\\n\\n\");\n\treturn 0;\n}\n\n/* Test that the flush function is able to move packets between workers when\n * one worker shuts down..\n */\nstatic int\ntest_flush_with_worker_shutdown(struct rte_distributor *d,\n\t\tstruct rte_mempool *p)\n{\n\tstruct rte_mbuf *bufs[BURST];\n\tunsigned i;\n\n\tprintf(\"=== Test flush fn with worker shutdown ===\\n\");\n\n\tclear_packet_count();\n\tif (rte_mempool_get_bulk(p, (void *)bufs, BURST) != 0) {\n\t\tprintf(\"line %d: Error getting mbufs from pool\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\n\t/* now set all hash values in all buffers to zero, so all pkts go to the\n\t * one worker thread */\n\tfor (i = 0; i < BURST; i++)\n\t\tbufs[i]->hash.usr = 0;\n\n\trte_distributor_process(d, bufs, BURST);\n\t/* at this point, we will have processed some packets and have a full\n\t * backlog for the other ones at worker 0.\n\t */\n\n\t/* get worker zero to quit */\n\tzero_quit = 1;\n\n\t/* flush the distributor */\n\trte_distributor_flush(d);\n\n\tzero_quit = 0;\n\tif (total_packet_count() != BURST) {\n\t\tprintf(\"Line %d: Error, not all packets flushed. \"\n\t\t\t\t\"Expected %u, got %u\\n\",\n\t\t\t\t__LINE__, BURST, total_packet_count());\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < rte_lcore_count() - 1; i++)\n\t\tprintf(\"Worker %u handled %u packets\\n\", i,\n\t\t\t\tworker_stats[i].handled_packets);\n\n\tprintf(\"Flush test with worker shutdown passed\\n\\n\");\n\treturn 0;\n}\n\nstatic\nint test_error_distributor_create_name(void)\n{\n\tstruct rte_distributor *d = NULL;\n\tchar *name = NULL;\n\n\td = rte_distributor_create(name, rte_socket_id(),\n\t\t\trte_lcore_count() - 1);\n\tif (d != NULL || rte_errno != EINVAL) {\n\t\tprintf(\"ERROR: No error on create() with NULL name param\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n\nstatic\nint test_error_distributor_create_numworkers(void)\n{\n\tstruct rte_distributor *d = NULL;\n\td = rte_distributor_create(\"test_numworkers\", rte_socket_id(),\n\t\t\tRTE_MAX_LCORE + 10);\n\tif (d != NULL || rte_errno != EINVAL) {\n\t\tprintf(\"ERROR: No error on create() with num_workers > MAX\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n\n/* Useful function which ensures that all worker functions terminate */\nstatic void\nquit_workers(struct rte_distributor *d, struct rte_mempool *p)\n{\n\tconst unsigned num_workers = rte_lcore_count() - 1;\n\tunsigned i;\n\tstruct rte_mbuf *bufs[RTE_MAX_LCORE];\n\trte_mempool_get_bulk(p, (void *)bufs, num_workers);\n\n\tzero_quit = 0;\n\tquit = 1;\n\tfor (i = 0; i < num_workers; i++)\n\t\tbufs[i]->hash.usr = i << 1;\n\trte_distributor_process(d, bufs, num_workers);\n\n\trte_mempool_put_bulk(p, (void *)bufs, num_workers);\n\n\trte_distributor_process(d, NULL, 0);\n\trte_distributor_flush(d);\n\trte_eal_mp_wait_lcore();\n\tquit = 0;\n\tworker_idx = 0;\n}\n\nstatic int\ntest_distributor(void)\n{\n\tstatic struct rte_distributor *d;\n\tstatic struct rte_mempool *p;\n\n\tif (rte_lcore_count() < 2) {\n\t\tprintf(\"ERROR: not enough cores to test distributor\\n\");\n\t\treturn -1;\n\t}\n\n\tif (d == NULL) {\n\t\td = rte_distributor_create(\"Test_distributor\", rte_socket_id(),\n\t\t\t\trte_lcore_count() - 1);\n\t\tif (d == NULL) {\n\t\t\tprintf(\"Error creating distributor\\n\");\n\t\t\treturn -1;\n\t\t}\n\t} else {\n\t\trte_distributor_flush(d);\n\t\trte_distributor_clear_returns(d);\n\t}\n\n\tconst unsigned nb_bufs = (511 * rte_lcore_count()) < BIG_BATCH ?\n\t\t\t(BIG_BATCH * 2) - 1 : (511 * rte_lcore_count());\n\tif (p == NULL) {\n\t\tp = rte_pktmbuf_pool_create(\"DT_MBUF_POOL\", nb_bufs, BURST,\n\t\t\t0, RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\t\tif (p == NULL) {\n\t\t\tprintf(\"Error creating mempool\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\trte_eal_mp_remote_launch(handle_work, d, SKIP_MASTER);\n\tif (sanity_test(d, p) < 0)\n\t\tgoto err;\n\tquit_workers(d, p);\n\n\trte_eal_mp_remote_launch(handle_work_with_free_mbufs, d, SKIP_MASTER);\n\tif (sanity_test_with_mbuf_alloc(d, p) < 0)\n\t\tgoto err;\n\tquit_workers(d, p);\n\n\tif (rte_lcore_count() > 2) {\n\t\trte_eal_mp_remote_launch(handle_work_for_shutdown_test, d,\n\t\t\t\tSKIP_MASTER);\n\t\tif (sanity_test_with_worker_shutdown(d, p) < 0)\n\t\t\tgoto err;\n\t\tquit_workers(d, p);\n\n\t\trte_eal_mp_remote_launch(handle_work_for_shutdown_test, d,\n\t\t\t\tSKIP_MASTER);\n\t\tif (test_flush_with_worker_shutdown(d, p) < 0)\n\t\t\tgoto err;\n\t\tquit_workers(d, p);\n\n\t} else {\n\t\tprintf(\"Not enough cores to run tests for worker shutdown\\n\");\n\t}\n\n\tif (test_error_distributor_create_numworkers() == -1 ||\n\t\t\ttest_error_distributor_create_name() == -1) {\n\t\tprintf(\"rte_distributor_create parameter check tests failed\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n\nerr:\n\tquit_workers(d, p);\n\treturn -1;\n}\n\nstatic struct test_command distributor_cmd = {\n\t.command = \"distributor_autotest\",\n\t.callback = test_distributor,\n};\nREGISTER_TEST_COMMAND(distributor_cmd);\n" }, { "path": "app/test/test_distributor_perf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"test.h\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define ITER_POWER 20 /* log 2 of how many iterations we do when timing. */\n#define BURST 32\n#define BIG_BATCH 1024\n\n/* static vars - zero initialized by default */\nstatic volatile int quit;\nstatic volatile unsigned worker_idx;\n\nstruct worker_stats {\n\tvolatile unsigned handled_packets;\n} __rte_cache_aligned;\nstruct worker_stats worker_stats[RTE_MAX_LCORE];\n\n/* worker thread used for testing the time to do a round-trip of a cache\n * line between two cores and back again\n */\nstatic void\nflip_bit(volatile uint64_t *arg)\n{\n\tuint64_t old_val = 0;\n\twhile (old_val != 2) {\n\t\twhile (!*arg)\n\t\t\trte_pause();\n\t\told_val = *arg;\n\t\t*arg = 0;\n\t}\n}\n\n/* test case to time the number of cycles to round-trip a cache line between\n * two cores and back again.\n */\nstatic void\ntime_cache_line_switch(void)\n{\n\t/* allocate a full cache line for data, we use only first byte of it */\n\tuint64_t data[RTE_CACHE_LINE_SIZE*3 / sizeof(uint64_t)];\n\n\tunsigned i, slaveid = rte_get_next_lcore(rte_lcore_id(), 0, 0);\n\tvolatile uint64_t *pdata = &data[0];\n\t*pdata = 1;\n\trte_eal_remote_launch((lcore_function_t *)flip_bit, &data[0], slaveid);\n\twhile (*pdata)\n\t\trte_pause();\n\n\tconst uint64_t start_time = rte_rdtsc();\n\tfor (i = 0; i < (1 << ITER_POWER); i++) {\n\t\twhile (*pdata)\n\t\t\trte_pause();\n\t\t*pdata = 1;\n\t}\n\tconst uint64_t end_time = rte_rdtsc();\n\n\twhile (*pdata)\n\t\trte_pause();\n\t*pdata = 2;\n\trte_eal_wait_lcore(slaveid);\n\tprintf(\"==== Cache line switch test ===\\n\");\n\tprintf(\"Time for %u iterations = %\"PRIu64\" ticks\\n\", (1<> ITER_POWER);\n}\n\n/* returns the total count of the number of packets handled by the worker\n * functions given below.\n */\nstatic unsigned\ntotal_packet_count(void)\n{\n\tunsigned i, count = 0;\n\tfor (i = 0; i < worker_idx; i++)\n\t\tcount += worker_stats[i].handled_packets;\n\treturn count;\n}\n\n/* resets the packet counts for a new test */\nstatic void\nclear_packet_count(void)\n{\n\tmemset(&worker_stats, 0, sizeof(worker_stats));\n}\n\n/* this is the basic worker function for performance tests.\n * it does nothing but return packets and count them.\n */\nstatic int\nhandle_work(void *arg)\n{\n\tstruct rte_mbuf *pkt = NULL;\n\tstruct rte_distributor *d = arg;\n\tunsigned count = 0;\n\tunsigned id = __sync_fetch_and_add(&worker_idx, 1);\n\n\tpkt = rte_distributor_get_pkt(d, id, NULL);\n\twhile (!quit) {\n\t\tworker_stats[id].handled_packets++, count++;\n\t\tpkt = rte_distributor_get_pkt(d, id, pkt);\n\t}\n\tworker_stats[id].handled_packets++, count++;\n\trte_distributor_return_pkt(d, id, pkt);\n\treturn 0;\n}\n\n/* this basic performance test just repeatedly sends in 32 packets at a time\n * to the distributor and verifies at the end that we got them all in the worker\n * threads and finally how long per packet the processing took.\n */\nstatic inline int\nperf_test(struct rte_distributor *d, struct rte_mempool *p)\n{\n\tunsigned i;\n\tuint64_t start, end;\n\tstruct rte_mbuf *bufs[BURST];\n\n\tclear_packet_count();\n\tif (rte_mempool_get_bulk(p, (void *)bufs, BURST) != 0) {\n\t\tprintf(\"Error getting mbufs from pool\\n\");\n\t\treturn -1;\n\t}\n\t/* ensure we have different hash value for each pkt */\n\tfor (i = 0; i < BURST; i++)\n\t\tbufs[i]->hash.usr = i;\n\n\tstart = rte_rdtsc();\n\tfor (i = 0; i < (1<> ITER_POWER);\n\tprintf(\"Time per packet: %\"PRIu64\"\\n\\n\",\n\t\t\t((end - start) >> ITER_POWER)/BURST);\n\trte_mempool_put_bulk(p, (void *)bufs, BURST);\n\n\tfor (i = 0; i < rte_lcore_count() - 1; i++)\n\t\tprintf(\"Worker %u handled %u packets\\n\", i,\n\t\t\t\tworker_stats[i].handled_packets);\n\tprintf(\"Total packets: %u (%x)\\n\", total_packet_count(),\n\t\t\ttotal_packet_count());\n\tprintf(\"=== Perf test done ===\\n\\n\");\n\n\treturn 0;\n}\n\n/* Useful function which ensures that all worker functions terminate */\nstatic void\nquit_workers(struct rte_distributor *d, struct rte_mempool *p)\n{\n\tconst unsigned num_workers = rte_lcore_count() - 1;\n\tunsigned i;\n\tstruct rte_mbuf *bufs[RTE_MAX_LCORE];\n\trte_mempool_get_bulk(p, (void *)bufs, num_workers);\n\n\tquit = 1;\n\tfor (i = 0; i < num_workers; i++)\n\t\tbufs[i]->hash.usr = i << 1;\n\trte_distributor_process(d, bufs, num_workers);\n\n\trte_mempool_put_bulk(p, (void *)bufs, num_workers);\n\n\trte_distributor_process(d, NULL, 0);\n\trte_eal_mp_wait_lcore();\n\tquit = 0;\n\tworker_idx = 0;\n}\n\nstatic int\ntest_distributor_perf(void)\n{\n\tstatic struct rte_distributor *d;\n\tstatic struct rte_mempool *p;\n\n\tif (rte_lcore_count() < 2) {\n\t\tprintf(\"ERROR: not enough cores to test distributor\\n\");\n\t\treturn -1;\n\t}\n\n\t/* first time how long it takes to round-trip a cache line */\n\ttime_cache_line_switch();\n\n\tif (d == NULL) {\n\t\td = rte_distributor_create(\"Test_perf\", rte_socket_id(),\n\t\t\t\trte_lcore_count() - 1);\n\t\tif (d == NULL) {\n\t\t\tprintf(\"Error creating distributor\\n\");\n\t\t\treturn -1;\n\t\t}\n\t} else {\n\t\trte_distributor_flush(d);\n\t\trte_distributor_clear_returns(d);\n\t}\n\n\tconst unsigned nb_bufs = (511 * rte_lcore_count()) < BIG_BATCH ?\n\t\t\t(BIG_BATCH * 2) - 1 : (511 * rte_lcore_count());\n\tif (p == NULL) {\n\t\tp = rte_pktmbuf_pool_create(\"DPT_MBUF_POOL\", nb_bufs, BURST,\n\t\t\t0, RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\t\tif (p == NULL) {\n\t\t\tprintf(\"Error creating mempool\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\trte_eal_mp_remote_launch(handle_work, d, SKIP_MASTER);\n\tif (perf_test(d, p) < 0)\n\t\treturn -1;\n\tquit_workers(d, p);\n\n\treturn 0;\n}\n\nstatic struct test_command distributor_perf_cmd = {\n\t.command = \"distributor_perf_autotest\",\n\t.callback = test_distributor_perf,\n};\nREGISTER_TEST_COMMAND(distributor_perf_cmd);\n" }, { "path": "app/test/test_eal_flags.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n\n#include \"test.h\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \"process.h\"\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n#define DEFAULT_MEM_SIZE \"30\"\n#else\n#define DEFAULT_MEM_SIZE \"18\"\n#endif\n#define mp_flag \"--proc-type=secondary\"\n#define no_hpet \"--no-hpet\"\n#define no_huge \"--no-huge\"\n#define no_shconf \"--no-shconf\"\n#define pci_whitelist \"--pci-whitelist\"\n#define vdev \"--vdev\"\n#define memtest \"memtest\"\n#define memtest1 \"memtest1\"\n#define memtest2 \"memtest2\"\n#define SOCKET_MEM_STRLEN (RTE_MAX_NUMA_NODES * 10)\n#define launch_proc(ARGV) process_dup(ARGV, \\\n\t\tsizeof(ARGV)/(sizeof(ARGV[0])), __func__)\n\nenum hugepage_action {\n\tHUGEPAGE_CHECK_EXISTS = 0,\n\tHUGEPAGE_CHECK_LOCKED,\n\tHUGEPAGE_DELETE,\n\tHUGEPAGE_INVALID\n};\n\n/* if string contains a hugepage path */\nstatic int\nget_hugepage_path(char * src, int src_len, char * dst, int dst_len)\n{\n#define NUM_TOKENS 4\n\tchar *tokens[NUM_TOKENS];\n\n\t/* if we couldn't properly split the string */\n\tif (rte_strsplit(src, src_len, tokens, NUM_TOKENS, ' ') < NUM_TOKENS)\n\t\treturn 0;\n\n\tif (strncmp(tokens[2], \"hugetlbfs\", sizeof(\"hugetlbfs\")) == 0) {\n\t\tsnprintf(dst, dst_len, \"%s\", tokens[1]);\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\n/*\n * Cycles through hugepage directories and looks for hugepage\n * files associated with a given prefix. Depending on value of\n * action, the hugepages are checked if they exist, checked if\n * they can be locked, or are simply deleted.\n *\n * Returns 1 if it finds at least one hugepage matching the action\n * Returns 0 if no matching hugepages were found\n * Returns -1 if it encounters an error\n */\nstatic int\nprocess_hugefiles(const char * prefix, enum hugepage_action action)\n{\n\tFILE * hugedir_handle = NULL;\n\tDIR * hugepage_dir = NULL;\n\tstruct dirent *dirent = NULL;\n\n\tchar hugefile_prefix[PATH_MAX] = {0};\n\tchar hugedir[PATH_MAX] = {0};\n\tchar line[PATH_MAX] = {0};\n\n\tint fd, lck_result, result = 0;\n\n\tconst int prefix_len = snprintf(hugefile_prefix,\n\t\t\tsizeof(hugefile_prefix), \"%smap_\", prefix);\n\tif (prefix_len <= 0 || prefix_len >= (int)sizeof(hugefile_prefix)\n\t\t\t|| prefix_len >= (int)sizeof(dirent->d_name)) {\n\t\tprintf(\"Error creating hugefile filename prefix\\n\");\n\t\treturn -1;\n\t}\n\n\t/* get hugetlbfs mountpoints from /proc/mounts */\n\thugedir_handle = fopen(\"/proc/mounts\", \"r\");\n\n\tif (hugedir_handle == NULL) {\n\t\tprintf(\"Error parsing /proc/mounts!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* read and parse script output */\n\twhile (fgets(line, sizeof(line), hugedir_handle) != NULL) {\n\n\t\t/* check if we have a hugepage filesystem path */\n\t\tif (!get_hugepage_path(line, sizeof(line), hugedir, sizeof(hugedir)))\n\t\t\tcontinue;\n\n\t\t/* check if directory exists */\n\t\tif ((hugepage_dir = opendir(hugedir)) == NULL) {\n\t\t\tfclose(hugedir_handle);\n\t\t\tprintf(\"Error reading %s: %s\\n\", hugedir, strerror(errno));\n\t\t\treturn -1;\n\t\t}\n\n\t\twhile ((dirent = readdir(hugepage_dir)) != NULL) {\n\t\t\tif (memcmp(dirent->d_name, hugefile_prefix, prefix_len) != 0)\n\t\t\t\tcontinue;\n\n\t\t\tswitch (action) {\n\t\t\tcase HUGEPAGE_CHECK_EXISTS:\n\t\t\t\t{\n\t\t\t\t\t/* file exists, return */\n\t\t\t\t\tresult = 1;\n\t\t\t\t\tgoto end;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase HUGEPAGE_DELETE:\n\t\t\t\t{\n\t\t\t\t\tchar file_path[PATH_MAX] = {0};\n\n\t\t\t\t\tsnprintf(file_path, sizeof(file_path),\n\t\t\t\t\t\t\"%s/%s\", hugedir, dirent->d_name);\n\n\t\t\t\t\t/* remove file */\n\t\t\t\t\tif (remove(file_path) < 0) {\n\t\t\t\t\t\tprintf(\"Error deleting %s - %s!\\n\",\n\t\t\t\t\t\t\t\tdirent->d_name, strerror(errno));\n\t\t\t\t\t\tclosedir(hugepage_dir);\n\t\t\t\t\t\tresult = -1;\n\t\t\t\t\t\tgoto end;\n\t\t\t\t\t}\n\t\t\t\t\tresult = 1;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase HUGEPAGE_CHECK_LOCKED:\n\t\t\t\t{\n\t\t\t\t\t/* try and lock the file */\n\t\t\t\t\tfd = openat(dirfd(hugepage_dir), dirent->d_name, O_RDONLY);\n\n\t\t\t\t\t/* this shouldn't happen */\n\t\t\t\t\tif (fd == -1) {\n\t\t\t\t\t\tprintf(\"Error opening %s - %s!\\n\",\n\t\t\t\t\t\t\t\tdirent->d_name, strerror(errno));\n\t\t\t\t\t\tclosedir(hugepage_dir);\n\t\t\t\t\t\tresult = -1;\n\t\t\t\t\t\tgoto end;\n\t\t\t\t\t}\n\n\t\t\t\t\t/* non-blocking lock */\n\t\t\t\t\tlck_result = flock(fd, LOCK_EX | LOCK_NB);\n\n\t\t\t\t\t/* if lock succeeds, there's something wrong */\n\t\t\t\t\tif (lck_result != -1) {\n\t\t\t\t\t\tresult = 0;\n\n\t\t\t\t\t\t/* unlock the resulting lock */\n\t\t\t\t\t\tflock(fd, LOCK_UN);\n\t\t\t\t\t\tclose(fd);\n\t\t\t\t\t\tclosedir(hugepage_dir);\n\t\t\t\t\t\tgoto end;\n\t\t\t\t\t}\n\t\t\t\t\tresult = 1;\n\t\t\t\t\tclose(fd);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t\t/* shouldn't happen */\n\t\t\tdefault:\n\t\t\t\tgoto end;\n\t\t\t} /* switch */\n\n\t\t} /* read hugepage directory */\n\t\tclosedir(hugepage_dir);\n\t} /* read /proc/mounts */\nend:\n\tfclose(hugedir_handle);\n\treturn result;\n}\n\n#ifdef RTE_EXEC_ENV_LINUXAPP\n/*\n * count the number of \"node*\" files in /sys/devices/system/node/\n */\nstatic int\nget_number_of_sockets(void)\n{\n\tstruct dirent *dirent = NULL;\n\tconst char * nodedir = \"/sys/devices/system/node/\";\n\tDIR * dir = NULL;\n\tint result = 0;\n\n\t/* check if directory exists */\n\tif ((dir = opendir(nodedir)) == NULL) {\n\t\t/* if errno==ENOENT this means we don't have NUMA support */\n\t\tif (errno == ENOENT) {\n\t\t\tprintf(\"No NUMA nodes detected: assuming 1 available socket\\n\");\n\t\t\treturn 1;\n\t\t}\n\t\tprintf(\"Error opening %s: %s\\n\", nodedir, strerror(errno));\n\t\treturn -1;\n\t}\n\n\twhile ((dirent = readdir(dir)) != NULL)\n\t\tif (strncmp(dirent->d_name, \"node\", sizeof(\"node\") - 1) == 0)\n\t\t\tresult++;\n\n\tclosedir(dir);\n\treturn result;\n}\n#endif\n\nstatic char*\nget_current_prefix(char * prefix, int size)\n{\n\tchar path[PATH_MAX] = {0};\n\tchar buf[PATH_MAX] = {0};\n\n\t/* get file for config (fd is always 3) */\n\tsnprintf(path, sizeof(path), \"/proc/self/fd/%d\", 3);\n\n\t/* return NULL on error */\n\tif (readlink(path, buf, sizeof(buf)) == -1)\n\t\treturn NULL;\n\n\t/* get the basename */\n\tsnprintf(buf, sizeof(buf), \"%s\", basename(buf));\n\n\t/* copy string all the way from second char up to start of _config */\n\tsnprintf(prefix, size, \"%.*s\",\n\t\t\t(int)(strnlen(buf, sizeof(buf)) - sizeof(\"_config\")),\n\t\t\t&buf[1]);\n\n\treturn prefix;\n}\n\n/*\n * Test that the app doesn't run with invalid whitelist option.\n * Final tests ensures it does run with valid options as sanity check (one\n * test for with Domain+BDF, second for just with BDF)\n */\nstatic int\ntest_whitelist_flag(void)\n{\n\tunsigned i;\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD target doesn't support prefixes at this point */\n\tconst char * prefix = \"\";\n#else\n\tchar prefix[PATH_MAX], tmp[PATH_MAX];\n\tif (get_current_prefix(tmp, sizeof(tmp)) == NULL) {\n\t\tprintf(\"Error - unable to get current prefix!\\n\");\n\t\treturn -1;\n\t}\n\tsnprintf(prefix, sizeof(prefix), \"--file-prefix=%s\", tmp);\n#endif\n\n\tconst char *wlinval[][11] = {\n\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\",\n\t\t\t\tpci_whitelist, \"error\", \"\", \"\"},\n\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\",\n\t\t\t\tpci_whitelist, \"0:0:0\", \"\", \"\"},\n\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\",\n\t\t\t\tpci_whitelist, \"0:error:0.1\", \"\", \"\"},\n\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\",\n\t\t\t\tpci_whitelist, \"0:0:0.1error\", \"\", \"\"},\n\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\",\n\t\t\t\tpci_whitelist, \"error0:0:0.1\", \"\", \"\"},\n\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\",\n\t\t\t\tpci_whitelist, \"0:0:0.1.2\", \"\", \"\"},\n\t};\n\t/* Test with valid whitelist option */\n\tconst char *wlval1[] = {prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\",\n\t\t\tpci_whitelist, \"00FF:09:0B.3\"};\n\tconst char *wlval2[] = {prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\",\n\t\t\tpci_whitelist, \"09:0B.3\", pci_whitelist, \"0a:0b.1\"};\n\tconst char *wlval3[] = {prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\",\n\t\t\tpci_whitelist, \"09:0B.3,type=test\",\n\t\t\tpci_whitelist, \"08:00.1,type=normal\",\n\t};\n\n\tfor (i = 0; i < sizeof(wlinval) / sizeof(wlinval[0]); i++) {\n\t\tif (launch_proc(wlinval[i]) == 0) {\n\t\t\tprintf(\"Error - process did run ok with invalid \"\n\t\t\t \"whitelist parameter\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\tif (launch_proc(wlval1) != 0 ) {\n\t\tprintf(\"Error - process did not run ok with valid whitelist\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(wlval2) != 0 ) {\n\t\tprintf(\"Error - process did not run ok with valid whitelist value set\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(wlval3) != 0 ) {\n\t\tprintf(\"Error - process did not run ok with valid whitelist + args\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Test that the app doesn't run with invalid blacklist option.\n * Final test ensures it does run with valid options as sanity check\n */\nstatic int\ntest_invalid_b_flag(void)\n{\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD target doesn't support prefixes at this point */\n\tconst char * prefix = \"\";\n#else\n\tchar prefix[PATH_MAX], tmp[PATH_MAX];\n\tif (get_current_prefix(tmp, sizeof(tmp)) == NULL) {\n\t\tprintf(\"Error - unable to get current prefix!\\n\");\n\t\treturn -1;\n\t}\n\tsnprintf(prefix, sizeof(prefix), \"--file-prefix=%s\", tmp);\n#endif\n\n\tconst char *blinval[][9] = {\n\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\", \"-b\", \"error\"},\n\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\", \"-b\", \"0:0:0\"},\n\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\", \"-b\", \"0:error:0.1\"},\n\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\", \"-b\", \"0:0:0.1error\"},\n\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\", \"-b\", \"error0:0:0.1\"},\n\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\", \"-b\", \"0:0:0.1.2\"},\n\t};\n\t/* Test with valid blacklist option */\n\tconst char *blval[] = {prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\", \"-b\", \"FF:09:0B.3\"};\n\n\tint i;\n\n\tfor (i = 0; i != sizeof (blinval) / sizeof (blinval[0]); i++) {\n\t\tif (launch_proc(blinval[i]) == 0) {\n\t\t\tprintf(\"Error - process did run ok with invalid \"\n\t\t\t \"blacklist parameter\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\tif (launch_proc(blval) != 0) {\n\t\tprintf(\"Error - process did not run ok with valid blacklist value\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/*\n * Test that the app doesn't run with invalid vdev option.\n * Final test ensures it does run with valid options as sanity check\n */\n#ifdef RTE_LIBRTE_PMD_RING\nstatic int\ntest_invalid_vdev_flag(void)\n{\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD target doesn't support prefixes at this point, and we also need to\n\t * run another primary process here */\n\tconst char * prefix = no_shconf;\n#else\n\tconst char * prefix = \"--file-prefix=vdev\";\n#endif\n\n\t/* Test with invalid vdev option */\n\tconst char *vdevinval[] = {prgname, prefix, \"-n\", \"1\",\n\t\t\t\t\"-c\", \"1\", vdev, \"eth_dummy\"};\n\n\t/* Test with valid vdev option */\n\tconst char *vdevval1[] = {prgname, prefix, \"-n\", \"1\",\n\t\"-c\", \"1\", vdev, \"eth_ring0\"};\n\n\tconst char *vdevval2[] = {prgname, prefix, \"-n\", \"1\",\n\t\"-c\", \"1\", vdev, \"eth_ring0,args=test\"};\n\n\tconst char *vdevval3[] = {prgname, prefix, \"-n\", \"1\",\n\t\"-c\", \"1\", vdev, \"eth_ring0,nodeaction=r1:0:CREATE\"};\n\n\tif (launch_proc(vdevinval) == 0) {\n\t\tprintf(\"Error - process did run ok with invalid \"\n\t\t\t\"vdev parameter\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(vdevval1) != 0) {\n\t\tprintf(\"Error - process did not run ok with valid vdev value\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(vdevval2) != 0) {\n\t\tprintf(\"Error - process did not run ok with valid vdev value,\"\n\t\t\t\"with dummy args\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(vdevval3) != 0) {\n\t\tprintf(\"Error - process did not run ok with valid vdev value,\"\n\t\t\t\"with valid args\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n#endif\n\n/*\n * Test that the app doesn't run with invalid -r option.\n */\nstatic int\ntest_invalid_r_flag(void)\n{\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD target doesn't support prefixes at this point */\n\tconst char * prefix = \"\";\n#else\n\tchar prefix[PATH_MAX], tmp[PATH_MAX];\n\tif (get_current_prefix(tmp, sizeof(tmp)) == NULL) {\n\t\tprintf(\"Error - unable to get current prefix!\\n\");\n\t\treturn -1;\n\t}\n\tsnprintf(prefix, sizeof(prefix), \"--file-prefix=%s\", tmp);\n#endif\n\n\tconst char *rinval[][9] = {\n\t\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\", \"-r\", \"error\"},\n\t\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\", \"-r\", \"0\"},\n\t\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\", \"-r\", \"-1\"},\n\t\t\t{prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\", \"-r\", \"17\"},\n\t};\n\t/* Test with valid blacklist option */\n\tconst char *rval[] = {prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"1\", \"-r\", \"16\"};\n\n\tint i;\n\n\tfor (i = 0; i != sizeof (rinval) / sizeof (rinval[0]); i++) {\n\t\tif (launch_proc(rinval[i]) == 0) {\n\t\t\tprintf(\"Error - process did run ok with invalid \"\n\t\t\t \"-r (rank) parameter\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\tif (launch_proc(rval) != 0) {\n\t\tprintf(\"Error - process did not run ok with valid -r (rank) value\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/*\n * Test that the app doesn't run without the coremask/corelist flags. In all cases\n * should give an error and fail to run\n */\nstatic int\ntest_missing_c_flag(void)\n{\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD target doesn't support prefixes at this point */\n\tconst char * prefix = \"\";\n#else\n\tchar prefix[PATH_MAX], tmp[PATH_MAX];\n\tif (get_current_prefix(tmp, sizeof(tmp)) == NULL) {\n\t\tprintf(\"Error - unable to get current prefix!\\n\");\n\t\treturn -1;\n\t}\n\tsnprintf(prefix, sizeof(prefix), \"--file-prefix=%s\", tmp);\n#endif\n\n\t/* -c flag but no coremask value */\n\tconst char *argv1[] = { prgname, prefix, mp_flag, \"-n\", \"3\", \"-c\"};\n\t/* No -c, -l or --lcores flag at all */\n\tconst char *argv2[] = { prgname, prefix, mp_flag, \"-n\", \"3\"};\n\t/* bad coremask value */\n\tconst char *argv3[] = { prgname, prefix, mp_flag,\n\t\t\t\t\"-n\", \"3\", \"-c\", \"error\" };\n\t/* sanity check of tests - valid coremask value */\n\tconst char *argv4[] = { prgname, prefix, mp_flag,\n\t\t\t\t\"-n\", \"3\", \"-c\", \"1\" };\n\t/* -l flag but no corelist value */\n\tconst char *argv5[] = { prgname, prefix, mp_flag,\n\t\t\t\t\"-n\", \"3\", \"-l\"};\n\tconst char *argv6[] = { prgname, prefix, mp_flag,\n\t\t\t\t\"-n\", \"3\", \"-l\", \" \" };\n\t/* bad corelist values */\n\tconst char *argv7[] = { prgname, prefix, mp_flag,\n\t\t\t\t\"-n\", \"3\", \"-l\", \"error\" };\n\tconst char *argv8[] = { prgname, prefix, mp_flag,\n\t\t\t\t\"-n\", \"3\", \"-l\", \"1-\" };\n\tconst char *argv9[] = { prgname, prefix, mp_flag,\n\t\t\t\t\"-n\", \"3\", \"-l\", \"1,\" };\n\tconst char *argv10[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"-l\", \"1#2\" };\n\t/* sanity check test - valid corelist value */\n\tconst char *argv11[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"-l\", \"1-2,3\" };\n\n\t/* --lcores flag but no lcores value */\n\tconst char *argv12[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\" };\n\tconst char *argv13[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\", \" \" };\n\t/* bad lcores value */\n\tconst char *argv14[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\", \"1-3-5\" };\n\tconst char *argv15[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\", \"0-1,,2\" };\n\tconst char *argv16[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\", \"0-,1\" };\n\tconst char *argv17[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\", \"(0-,2-4)\" };\n\tconst char *argv18[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\", \"(-1,2)\" };\n\tconst char *argv19[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\", \"(2-4)@(2-4-6)\" };\n\tconst char *argv20[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\", \"(a,2)\" };\n\tconst char *argv21[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\", \"1-3@(1,3)\" };\n\tconst char *argv22[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\", \"3@((1,3)\" };\n\tconst char *argv23[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\", \"(4-7)=(1,3)\" };\n\tconst char *argv24[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\", \"[4-7]@(1,3)\" };\n\t/* sanity check of tests - valid lcores value */\n\tconst char *argv25[] = { prgname, prefix, mp_flag,\n\t\t\t\t \"-n\", \"3\", \"--lcores\",\n\t\t\t\t \"0-1,2@(5-7),(3-5)@(0,2),(0,6),7\"};\n\n\tif (launch_proc(argv1) == 0\n\t\t\t|| launch_proc(argv2) == 0\n\t\t\t|| launch_proc(argv3) == 0) {\n\t\tprintf(\"Error - \"\n\t\t \"process ran without error when missing -c flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv4) != 0) {\n\t\tprintf(\"Error - \"\n\t\t \"process did not run ok with valid coremask value\\n\");\n\t\treturn -1;\n\t}\n\n\t/* start -l test */\n\tif (launch_proc(argv5) == 0\n\t\t\t|| launch_proc(argv6) == 0\n\t\t\t|| launch_proc(argv7) == 0\n\t\t\t|| launch_proc(argv8) == 0\n\t\t\t|| launch_proc(argv9) == 0\n\t\t\t|| launch_proc(argv10) == 0) {\n\t\tprintf(\"Error - \"\n\t\t \"process ran without error with invalid -l flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv11) != 0) {\n\t\tprintf(\"Error - \"\n\t\t \"process did not run ok with valid corelist value\\n\");\n\t\treturn -1;\n\t}\n\n\t/* start --lcores tests */\n\tif (launch_proc(argv12) == 0 || launch_proc(argv13) == 0 ||\n\t launch_proc(argv14) == 0 || launch_proc(argv15) == 0 ||\n\t launch_proc(argv16) == 0 || launch_proc(argv17) == 0 ||\n\t launch_proc(argv18) == 0 || launch_proc(argv19) == 0 ||\n\t launch_proc(argv20) == 0 || launch_proc(argv21) == 0 ||\n\t launch_proc(argv21) == 0 || launch_proc(argv22) == 0 ||\n\t launch_proc(argv23) == 0 || launch_proc(argv24) == 0) {\n\t\tprintf(\"Error - \"\n\t\t \"process ran without error with invalid --lcore flag\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(argv25) != 0) {\n\t\tprintf(\"Error - \"\n\t\t \"process did not run ok with valid corelist value\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Test --master-lcore option with matching coremask\n */\nstatic int\ntest_master_lcore_flag(void)\n{\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD target doesn't support prefixes at this point */\n\tconst char *prefix = \"\";\n#else\n\tchar prefix[PATH_MAX], tmp[PATH_MAX];\n\tif (get_current_prefix(tmp, sizeof(tmp)) == NULL) {\n\t\tprintf(\"Error - unable to get current prefix!\\n\");\n\t\treturn -1;\n\t}\n\tsnprintf(prefix, sizeof(prefix), \"--file-prefix=%s\", tmp);\n#endif\n\n\t/* --master-lcore flag but no value */\n\tconst char *argv1[] = { prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"3\", \"--master-lcore\"};\n\t/* --master-lcore flag with invalid value */\n\tconst char *argv2[] = { prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"3\", \"--master-lcore\", \"-1\"};\n\tconst char *argv3[] = { prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"3\", \"--master-lcore\", \"X\"};\n\t/* master lcore not in coremask */\n\tconst char *argv4[] = { prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"3\", \"--master-lcore\", \"2\"};\n\t/* valid value */\n\tconst char *argv5[] = { prgname, prefix, mp_flag, \"-n\", \"1\", \"-c\", \"3\", \"--master-lcore\", \"1\"};\n\t/* valid value set before coremask */\n\tconst char *argv6[] = { prgname, prefix, mp_flag, \"-n\", \"1\", \"--master-lcore\", \"1\", \"-c\", \"3\"};\n\n\tif (launch_proc(argv1) == 0\n\t\t\t|| launch_proc(argv2) == 0\n\t\t\t|| launch_proc(argv3) == 0\n\t\t\t|| launch_proc(argv4) == 0) {\n\t\tprintf(\"Error - process ran without error with wrong --master-lcore\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv5) != 0\n\t\t\t|| launch_proc(argv6) != 0) {\n\t\tprintf(\"Error - process did not run ok with valid --master-lcore\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/*\n * Test that the app doesn't run without the -n flag. In all cases\n * should give an error and fail to run.\n * Since -n is not compulsory for MP, we instead use --no-huge and --no-shconf\n * flags.\n */\nstatic int\ntest_missing_n_flag(void)\n{\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD target doesn't support prefixes at this point */\n\tconst char * prefix = \"\";\n#else\n\tchar prefix[PATH_MAX], tmp[PATH_MAX];\n\tif (get_current_prefix(tmp, sizeof(tmp)) == NULL) {\n\t\tprintf(\"Error - unable to get current prefix!\\n\");\n\t\treturn -1;\n\t}\n\tsnprintf(prefix, sizeof(prefix), \"--file-prefix=%s\", tmp);\n#endif\n\n\t/* -n flag but no value */\n\tconst char *argv1[] = { prgname, prefix, no_huge, no_shconf, \"-c\", \"1\", \"-n\"};\n\t/* No -n flag at all */\n\tconst char *argv2[] = { prgname, prefix, no_huge, no_shconf, \"-c\", \"1\"};\n\t/* bad numeric value */\n\tconst char *argv3[] = { prgname, prefix, no_huge, no_shconf, \"-c\", \"1\", \"-n\", \"e\" };\n\t/* out-of-range value */\n\tconst char *argv4[] = { prgname, prefix, no_huge, no_shconf, \"-c\", \"1\", \"-n\", \"9\" };\n\t/* sanity test - check with good value */\n\tconst char *argv5[] = { prgname, prefix, no_huge, no_shconf, \"-c\", \"1\", \"-n\", \"2\" };\n\n\tif (launch_proc(argv1) == 0\n\t\t\t|| launch_proc(argv2) == 0\n\t\t\t|| launch_proc(argv3) == 0\n\t\t\t|| launch_proc(argv4) == 0) {\n\t\tprintf(\"Error - process ran without error when missing -n flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv5) != 0) {\n\t\tprintf(\"Error - process did not run ok with valid num-channel value\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/*\n * Test that the app runs with HPET, and without HPET\n */\nstatic int\ntest_no_hpet_flag(void)\n{\n\tchar prefix[PATH_MAX], tmp[PATH_MAX];\n\n#ifdef RTE_EXEC_ENV_BSDAPP\n\treturn 0;\n#endif\n\tif (get_current_prefix(tmp, sizeof(tmp)) == NULL) {\n\t\tprintf(\"Error - unable to get current prefix!\\n\");\n\t\treturn -1;\n\t}\n\tsnprintf(prefix, sizeof(prefix), \"--file-prefix=%s\", tmp);\n\n\t/* With --no-hpet */\n\tconst char *argv1[] = {prgname, prefix, mp_flag, no_hpet, \"-c\", \"1\", \"-n\", \"2\"};\n\t/* Without --no-hpet */\n\tconst char *argv2[] = {prgname, prefix, mp_flag, \"-c\", \"1\", \"-n\", \"2\"};\n\n\tif (launch_proc(argv1) != 0) {\n\t\tprintf(\"Error - process did not run ok with --no-hpet flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv2) != 0) {\n\t\tprintf(\"Error - process did not run ok without --no-hpet flag\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/*\n * Test that the app runs with --no-huge and doesn't run when --socket-mem are\n * specified with --no-huge.\n */\nstatic int\ntest_no_huge_flag(void)\n{\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD target doesn't support prefixes at this point, and we also need to\n\t * run another primary process here */\n\tconst char * prefix = no_shconf;\n#else\n\tconst char * prefix = \"--file-prefix=nohuge\";\n#endif\n\n\t/* With --no-huge */\n\tconst char *argv1[] = {prgname, prefix, no_huge, \"-c\", \"1\", \"-n\", \"2\"};\n\t/* With --no-huge and -m */\n\tconst char *argv2[] = {prgname, prefix, no_huge, \"-c\", \"1\", \"-n\", \"2\",\n\t\t\t\"-m\", DEFAULT_MEM_SIZE};\n\n\t/* With --no-huge and --socket-mem */\n\tconst char *argv3[] = {prgname, prefix, no_huge, \"-c\", \"1\", \"-n\", \"2\",\n\t\t\t\"--socket-mem=\" DEFAULT_MEM_SIZE};\n\t/* With --no-huge, -m and --socket-mem */\n\tconst char *argv4[] = {prgname, prefix, no_huge, \"-c\", \"1\", \"-n\", \"2\",\n\t\t\t\"-m\", DEFAULT_MEM_SIZE, \"--socket-mem=\" DEFAULT_MEM_SIZE};\n\tif (launch_proc(argv1) != 0) {\n\t\tprintf(\"Error - process did not run ok with --no-huge flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv2) != 0) {\n\t\tprintf(\"Error - process did not run ok with --no-huge and -m flags\\n\");\n\t\treturn -1;\n\t}\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD target does not support NUMA, hence no --socket-mem tests */\n\treturn 0;\n#endif\n\n\tif (launch_proc(argv3) == 0) {\n\t\tprintf(\"Error - process run ok with --no-huge and --socket-mem \"\n\t\t\t\t\"flags\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv4) == 0) {\n\t\tprintf(\"Error - process run ok with --no-huge, -m and \"\n\t\t\t\t\"--socket-mem flags\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n#ifdef RTE_LIBRTE_XEN_DOM0\nstatic int\ntest_dom0_misc_flags(void)\n{\n\tchar prefix[PATH_MAX], tmp[PATH_MAX];\n\n\tif (get_current_prefix(tmp, sizeof(tmp)) == NULL) {\n\t\tprintf(\"Error - unable to get current prefix!\\n\");\n\t\treturn -1;\n\t}\n\tsnprintf(prefix, sizeof(prefix), \"--file-prefix=%s\", tmp);\n\n\t/* check that some general flags don't prevent things from working.\n\t * All cases, apart from the first, app should run.\n\t * No futher testing of output done.\n\t */\n\t/* sanity check - failure with invalid option */\n\tconst char *argv0[] = {prgname, prefix, mp_flag, \"-c\", \"1\", \"--invalid-opt\"};\n\n\t/* With --no-pci */\n\tconst char *argv1[] = {prgname, prefix, mp_flag, \"-c\", \"1\", \"--no-pci\"};\n\t/* With -v */\n\tconst char *argv2[] = {prgname, prefix, mp_flag, \"-c\", \"1\", \"-v\"};\n\t/* With valid --syslog */\n\tconst char *argv3[] = {prgname, prefix, mp_flag, \"-c\", \"1\",\n\t\t\t\"--syslog\", \"syslog\"};\n\t/* With empty --syslog (should fail) */\n\tconst char *argv4[] = {prgname, prefix, mp_flag, \"-c\", \"1\", \"--syslog\"};\n\t/* With invalid --syslog */\n\tconst char *argv5[] = {prgname, prefix, mp_flag, \"-c\", \"1\", \"--syslog\", \"error\"};\n\t/* With no-sh-conf */\n\tconst char *argv6[] = {prgname, \"-c\", \"1\", \"-n\", \"2\", \"-m\", \"20\",\n\t\t\t\"--no-shconf\", \"--file-prefix=noshconf\" };\n\n\tif (launch_proc(argv0) == 0) {\n\t\tprintf(\"Error - process ran ok with invalid flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv1) != 0) {\n\t\tprintf(\"Error - process did not run ok with --no-pci flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv2) != 0) {\n\t\tprintf(\"Error - process did not run ok with -v flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv3) != 0) {\n\t\tprintf(\"Error - process did not run ok with --syslog flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv4) == 0) {\n\t\tprintf(\"Error - process run ok with empty --syslog flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv5) == 0) {\n\t\tprintf(\"Error - process run ok with invalid --syslog flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv6) != 0) {\n\t\tprintf(\"Error - process did not run ok with --no-shconf flag\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n#else\nstatic int\ntest_misc_flags(void)\n{\n\tchar hugepath[PATH_MAX] = {0};\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD target doesn't support prefixes at this point */\n\tconst char * prefix = \"\";\n\tconst char * nosh_prefix = \"\";\n#else\n\tchar prefix[PATH_MAX], tmp[PATH_MAX];\n\tconst char * nosh_prefix = \"--file-prefix=noshconf\";\n\tFILE * hugedir_handle = NULL;\n\tchar line[PATH_MAX] = {0};\n\tunsigned i, isempty = 1;\n\tif (get_current_prefix(tmp, sizeof(tmp)) == NULL) {\n\t\tprintf(\"Error - unable to get current prefix!\\n\");\n\t\treturn -1;\n\t}\n\tsnprintf(prefix, sizeof(prefix), \"--file-prefix=%s\", tmp);\n\n\t/*\n\t * get first valid hugepage path\n\t */\n\n\t/* get hugetlbfs mountpoints from /proc/mounts */\n\thugedir_handle = fopen(\"/proc/mounts\", \"r\");\n\n\tif (hugedir_handle == NULL) {\n\t\tprintf(\"Error opening /proc/mounts!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* read /proc/mounts */\n\twhile (fgets(line, sizeof(line), hugedir_handle) != NULL) {\n\n\t\t/* find first valid hugepath */\n\t\tif (get_hugepage_path(line, sizeof(line), hugepath, sizeof(hugepath)))\n\t\t\tbreak;\n\t}\n\n\tfclose(hugedir_handle);\n\n\t/* check if path is not empty */\n\tfor (i = 0; i < sizeof(hugepath); i++)\n\t\tif (hugepath[i] != '\\0')\n\t\t\tisempty = 0;\n\n\tif (isempty) {\n\t\tprintf(\"No mounted hugepage dir found!\\n\");\n\t\treturn -1;\n\t}\n#endif\n\n\n\t/* check that some general flags don't prevent things from working.\n\t * All cases, apart from the first, app should run.\n\t * No futher testing of output done.\n\t */\n\t/* sanity check - failure with invalid option */\n\tconst char *argv0[] = {prgname, prefix, mp_flag, \"-c\", \"1\", \"--invalid-opt\"};\n\n\t/* With --no-pci */\n\tconst char *argv1[] = {prgname, prefix, mp_flag, \"-c\", \"1\", \"--no-pci\"};\n\t/* With -v */\n\tconst char *argv2[] = {prgname, prefix, mp_flag, \"-c\", \"1\", \"-v\"};\n\t/* With valid --syslog */\n\tconst char *argv3[] = {prgname, prefix, mp_flag, \"-c\", \"1\",\n\t\t\t\"--syslog\", \"syslog\"};\n\t/* With empty --syslog (should fail) */\n\tconst char *argv4[] = {prgname, prefix, mp_flag, \"-c\", \"1\", \"--syslog\"};\n\t/* With invalid --syslog */\n\tconst char *argv5[] = {prgname, prefix, mp_flag, \"-c\", \"1\", \"--syslog\", \"error\"};\n\t/* With no-sh-conf */\n\tconst char *argv6[] = {prgname, \"-c\", \"1\", \"-n\", \"2\", \"-m\", DEFAULT_MEM_SIZE,\n\t\t\tno_shconf, nosh_prefix };\n\n#ifdef RTE_EXEC_ENV_BSDAPP\n\treturn 0;\n#endif\n\t/* With --huge-dir */\n\tconst char *argv7[] = {prgname, \"-c\", \"1\", \"-n\", \"2\", \"-m\", DEFAULT_MEM_SIZE,\n\t\t\t\"--file-prefix=hugedir\", \"--huge-dir\", hugepath};\n\t/* With empty --huge-dir (should fail) */\n\tconst char *argv8[] = {prgname, \"-c\", \"1\", \"-n\", \"2\", \"-m\", DEFAULT_MEM_SIZE,\n\t\t\t\"--file-prefix=hugedir\", \"--huge-dir\"};\n\t/* With invalid --huge-dir */\n\tconst char *argv9[] = {prgname, \"-c\", \"1\", \"-n\", \"2\", \"-m\", DEFAULT_MEM_SIZE,\n\t\t\t\"--file-prefix=hugedir\", \"--huge-dir\", \"invalid\"};\n\t/* Secondary process with invalid --huge-dir (should run as flag has no\n\t * effect on secondary processes) */\n\tconst char *argv10[] = {prgname, prefix, mp_flag, \"-c\", \"1\", \"--huge-dir\", \"invalid\"};\n\n\t/* try running with base-virtaddr param */\n\tconst char *argv11[] = {prgname, \"--file-prefix=virtaddr\",\n\t\t\t\"-c\", \"1\", \"-n\", \"2\", \"--base-virtaddr=0x12345678\"};\n\n\t/* try running with --vfio-intr INTx flag */\n\tconst char *argv12[] = {prgname, \"--file-prefix=intr\",\n\t\t\t\"-c\", \"1\", \"-n\", \"2\", \"--vfio-intr=legacy\"};\n\n\t/* try running with --vfio-intr MSI flag */\n\tconst char *argv13[] = {prgname, \"--file-prefix=intr\",\n\t\t\t\"-c\", \"1\", \"-n\", \"2\", \"--vfio-intr=msi\"};\n\n\t/* try running with --vfio-intr MSI-X flag */\n\tconst char *argv14[] = {prgname, \"--file-prefix=intr\",\n\t\t\t\"-c\", \"1\", \"-n\", \"2\", \"--vfio-intr=msix\"};\n\n\t/* try running with --vfio-intr invalid flag */\n\tconst char *argv15[] = {prgname, \"--file-prefix=intr\",\n\t\t\t\"-c\", \"1\", \"-n\", \"2\", \"--vfio-intr=invalid\"};\n\n\n\tif (launch_proc(argv0) == 0) {\n\t\tprintf(\"Error - process ran ok with invalid flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv1) != 0) {\n\t\tprintf(\"Error - process did not run ok with --no-pci flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv2) != 0) {\n\t\tprintf(\"Error - process did not run ok with -v flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv3) != 0) {\n\t\tprintf(\"Error - process did not run ok with --syslog flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv4) == 0) {\n\t\tprintf(\"Error - process run ok with empty --syslog flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv5) == 0) {\n\t\tprintf(\"Error - process run ok with invalid --syslog flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv6) != 0) {\n\t\tprintf(\"Error - process did not run ok with --no-shconf flag\\n\");\n\t\treturn -1;\n\t}\n#ifdef RTE_EXEC_ENV_BSDAPP\n\treturn 0;\n#endif\n\tif (launch_proc(argv7) != 0) {\n\t\tprintf(\"Error - process did not run ok with --huge-dir flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv8) == 0) {\n\t\tprintf(\"Error - process run ok with empty --huge-dir flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv9) == 0) {\n\t\tprintf(\"Error - process run ok with invalid --huge-dir flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv10) != 0) {\n\t\tprintf(\"Error - secondary process did not run ok with invalid --huge-dir flag\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv11) != 0) {\n\t\tprintf(\"Error - process did not run ok with --base-virtaddr parameter\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv12) != 0) {\n\t\tprintf(\"Error - process did not run ok with \"\n\t\t\t\t\"--vfio-intr INTx parameter\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv13) != 0) {\n\t\tprintf(\"Error - process did not run ok with \"\n\t\t\t\t\"--vfio-intr MSI parameter\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv14) != 0) {\n\t\tprintf(\"Error - process did not run ok with \"\n\t\t\t\t\"--vfio-intr MSI-X parameter\\n\");\n\t\treturn -1;\n\t}\n\tif (launch_proc(argv15) == 0) {\n\t\tprintf(\"Error - process run ok with \"\n\t\t\t\t\"--vfio-intr invalid parameter\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n#endif\n\nstatic int\ntest_file_prefix(void)\n{\n\t/*\n\t * 1. check if current process hugefiles are locked\n\t * 2. try to run secondary process without a corresponding primary process\n\t * (while failing to run, it will also remove any unused hugepage files)\n\t * 3. check if current process hugefiles are still in place and are locked\n\t * 4. run a primary process with memtest1 prefix\n\t * 5. check if memtest1 hugefiles are created\n\t * 6. run a primary process with memtest2 prefix\n\t * 7. check that only memtest2 hugefiles are present in the hugedir\n\t */\n\n#ifdef RTE_EXEC_ENV_BSDAPP\n\treturn 0;\n#endif\n\n\t/* this should fail unless the test itself is run with \"memtest\" prefix */\n\tconst char *argv0[] = {prgname, mp_flag, \"-c\", \"1\", \"-n\", \"2\", \"-m\", DEFAULT_MEM_SIZE,\n\t\t\t\"--file-prefix=\" memtest };\n\n\t/* primary process with memtest1 */\n\tconst char *argv1[] = {prgname, \"-c\", \"1\", \"-n\", \"2\", \"-m\", DEFAULT_MEM_SIZE,\n\t\t\t\t\"--file-prefix=\" memtest1 };\n\n\t/* primary process with memtest2 */\n\tconst char *argv2[] = {prgname, \"-c\", \"1\", \"-n\", \"2\", \"-m\", DEFAULT_MEM_SIZE,\n\t\t\t\t\"--file-prefix=\" memtest2 };\n\n\tchar prefix[32];\n\tif (get_current_prefix(prefix, sizeof(prefix)) == NULL) {\n\t\tprintf(\"Error - unable to get current prefix!\\n\");\n\t\treturn -1;\n\t}\n#ifdef RTE_LIBRTE_XEN_DOM0\n\treturn 0;\n#endif\n\n\t/* check if files for current prefix are present */\n\tif (process_hugefiles(prefix, HUGEPAGE_CHECK_EXISTS) != 1) {\n\t\tprintf(\"Error - hugepage files for %s were not created!\\n\", prefix);\n\t\treturn -1;\n\t}\n\n\t/* checks if files for current prefix are locked */\n\tif (process_hugefiles(prefix, HUGEPAGE_CHECK_LOCKED) != 1) {\n\t\tprintf(\"Error - hugepages for current process aren't locked!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check if files for secondary process are present */\n\tif (process_hugefiles(memtest, HUGEPAGE_CHECK_EXISTS) == 1) {\n\t\t/* check if they are not locked */\n\t\tif (process_hugefiles(memtest, HUGEPAGE_CHECK_LOCKED) == 1) {\n\t\t\tprintf(\"Error - hugepages for current process are locked!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\t/* they aren't locked, delete them */\n\t\telse {\n\t\t\tif (process_hugefiles(memtest, HUGEPAGE_DELETE) != 1) {\n\t\t\t\tprintf(\"Error - deleting hugepages failed!\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (launch_proc(argv0) == 0) {\n\t\tprintf(\"Error - secondary process ran ok without primary process\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check if files for current prefix are present */\n\tif (process_hugefiles(prefix, HUGEPAGE_CHECK_EXISTS) != 1) {\n\t\tprintf(\"Error - hugepage files for %s were not created!\\n\", prefix);\n\t\treturn -1;\n\t}\n\n\t/* checks if files for current prefix are locked */\n\tif (process_hugefiles(prefix, HUGEPAGE_CHECK_LOCKED) != 1) {\n\t\tprintf(\"Error - hugepages for current process aren't locked!\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(argv1) != 0) {\n\t\tprintf(\"Error - failed to run with --file-prefix=%s\\n\", memtest);\n\t\treturn -1;\n\t}\n\n\t/* check if memtest1_map0 is present */\n\tif (process_hugefiles(memtest1, HUGEPAGE_CHECK_EXISTS) != 1) {\n\t\tprintf(\"Error - hugepage files for %s were not created!\\n\", memtest1);\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(argv2) != 0) {\n\t\tprintf(\"Error - failed to run with --file-prefix=%s\\n\", memtest2);\n\t\treturn -1;\n\t}\n\n\t/* check if hugefiles for memtest2 are present */\n\tif (process_hugefiles(memtest2, HUGEPAGE_CHECK_EXISTS) != 1) {\n\t\tprintf(\"Error - hugepage files for %s were not created!\\n\", memtest2);\n\t\treturn -1;\n\t}\n\n\t/* check if hugefiles for memtest1 are present */\n\tif (process_hugefiles(memtest1, HUGEPAGE_CHECK_EXISTS) != 0) {\n\t\tprintf(\"Error - hugepage files for %s were not deleted!\\n\", memtest1);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Tests for correct handling of -m and --socket-mem flags\n */\nstatic int\ntest_memory_flags(void)\n{\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD target doesn't support prefixes at this point */\n\tconst char * prefix = \"\";\n#else\n\tchar prefix[PATH_MAX], tmp[PATH_MAX];\n\tif (get_current_prefix(tmp, sizeof(tmp)) == NULL) {\n\t\tprintf(\"Error - unable to get current prefix!\\n\");\n\t\treturn -1;\n\t}\n\tsnprintf(prefix, sizeof(prefix), \"--file-prefix=%s\", tmp);\n#endif\n\n\t/* valid -m flag and mp flag */\n\tconst char *argv0[] = {prgname, prefix, mp_flag, \"-c\", \"10\",\n\t\t\t\"-n\", \"2\", \"-m\", DEFAULT_MEM_SIZE};\n\n\t/* valid -m flag */\n\tconst char *argv1[] = {prgname, \"-c\", \"10\", \"-n\", \"2\",\n\t\t\t\"--file-prefix=\" memtest, \"-m\", DEFAULT_MEM_SIZE};\n\n\t/* invalid (zero) --socket-mem flag */\n\tconst char *argv2[] = {prgname, \"-c\", \"10\", \"-n\", \"2\",\n\t\t\t\"--file-prefix=\" memtest, \"--socket-mem=0,0,0,0\"};\n\n\t/* invalid (incomplete) --socket-mem flag */\n\tconst char *argv3[] = {prgname, \"-c\", \"10\", \"-n\", \"2\",\n\t\t\t\"--file-prefix=\" memtest, \"--socket-mem=2,2,\"};\n\n\t/* invalid (mixed with invalid data) --socket-mem flag */\n\tconst char *argv4[] = {prgname, \"-c\", \"10\", \"-n\", \"2\",\n\t\t\t\"--file-prefix=\" memtest, \"--socket-mem=2,2,Fred\"};\n\n\t/* invalid (with numeric value as last character) --socket-mem flag */\n\tconst char *argv5[] = {prgname, \"-c\", \"10\", \"-n\", \"2\",\n\t\t\t\"--file-prefix=\" memtest, \"--socket-mem=2,2,Fred0\"};\n\n\t/* invalid (with empty socket) --socket-mem flag */\n\tconst char *argv6[] = {prgname, \"-c\", \"10\", \"-n\", \"2\",\n\t\t\t\"--file-prefix=\" memtest, \"--socket-mem=2,,2\"};\n\n\t/* invalid (null) --socket-mem flag */\n\tconst char *argv7[] = {prgname, \"-c\", \"10\", \"-n\", \"2\",\n\t\t\t\"--file-prefix=\" memtest, \"--socket-mem=\"};\n\n\t/* valid --socket-mem specified together with -m flag */\n\tconst char *argv8[] = {prgname, \"-c\", \"10\", \"-n\", \"2\",\n\t\t\t\"--file-prefix=\" memtest, \"-m\", DEFAULT_MEM_SIZE, \"--socket-mem=2,2\"};\n\n\t/* construct an invalid socket mask with 2 megs on each socket plus\n\t * extra 2 megs on socket that doesn't exist on current system */\n\tchar invalid_socket_mem[SOCKET_MEM_STRLEN];\n\tchar buf[SOCKET_MEM_STRLEN];\t/* to avoid copying string onto itself */\n\n#ifdef RTE_EXEC_ENV_BSDAPP\n\tint i, num_sockets = 1;\n#else\n\tint i, num_sockets = get_number_of_sockets();\n#endif\n\n\tif (num_sockets <= 0 || num_sockets > RTE_MAX_NUMA_NODES) {\n\t\tprintf(\"Error - cannot get number of sockets!\\n\");\n\t\treturn -1;\n\t}\n\n\tsnprintf(invalid_socket_mem, sizeof(invalid_socket_mem), \"--socket-mem=\");\n\n\t/* add one extra socket */\n\tfor (i = 0; i < num_sockets + 1; i++) {\n\t\tsnprintf(buf, sizeof(buf), \"%s%s\", invalid_socket_mem, DEFAULT_MEM_SIZE);\n\t\tsnprintf(invalid_socket_mem, sizeof(invalid_socket_mem), \"%s\", buf);\n\n\t\tif (num_sockets + 1 - i > 1) {\n\t\t\tsnprintf(buf, sizeof(buf), \"%s,\", invalid_socket_mem);\n\t\t\tsnprintf(invalid_socket_mem, sizeof(invalid_socket_mem), \"%s\", buf);\n\t\t}\n\t}\n\n\t/* construct a valid socket mask with 2 megs on each existing socket */\n\tchar valid_socket_mem[SOCKET_MEM_STRLEN];\n\n\tsnprintf(valid_socket_mem, sizeof(valid_socket_mem), \"--socket-mem=\");\n\n\t/* add one extra socket */\n\tfor (i = 0; i < num_sockets; i++) {\n\t\tsnprintf(buf, sizeof(buf), \"%s%s\", valid_socket_mem, DEFAULT_MEM_SIZE);\n\t\tsnprintf(valid_socket_mem, sizeof(valid_socket_mem), \"%s\", buf);\n\n\t\tif (num_sockets - i > 1) {\n\t\t\tsnprintf(buf, sizeof(buf), \"%s,\", valid_socket_mem);\n\t\t\tsnprintf(valid_socket_mem, sizeof(valid_socket_mem), \"%s\", buf);\n\t\t}\n\t}\n\n\t/* invalid --socket-mem flag (with extra socket) */\n\tconst char *argv9[] = {prgname, \"-c\", \"10\", \"-n\", \"2\",\n\t\t\t\"--file-prefix=\" memtest, invalid_socket_mem};\n\n\t/* valid --socket-mem flag */\n\tconst char *argv10[] = {prgname, \"-c\", \"10\", \"-n\", \"2\",\n\t\t\t\"--file-prefix=\" memtest, valid_socket_mem};\n\n\tif (launch_proc(argv0) != 0) {\n\t\tprintf(\"Error - secondary process failed with valid -m flag !\\n\");\n\t\treturn -1;\n\t}\n\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* no other tests are applicable to BSD */\n\treturn 0;\n#endif\n\n\tif (launch_proc(argv1) != 0) {\n\t\tprintf(\"Error - process failed with valid -m flag!\\n\");\n\t\treturn -1;\n\t}\n#ifdef RTE_LIBRTE_XEN_DOM0\n\treturn 0;\n#endif\n\tif (launch_proc(argv2) == 0) {\n\t\tprintf(\"Error - process run ok with invalid (zero) --socket-mem!\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(argv3) == 0) {\n\t\tprintf(\"Error - process run ok with invalid \"\n\t\t\t\t\"(incomplete) --socket-mem!\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(argv4) == 0) {\n\t\tprintf(\"Error - process run ok with invalid \"\n\t\t\t\t\"(mixed with invalid input) --socket-mem!\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(argv5) == 0) {\n\t\tprintf(\"Error - process run ok with invalid \"\n\t\t\t\t\"(mixed with invalid input with a numeric value as \"\n\t\t\t\t\"last character) --socket-mem!\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(argv6) == 0) {\n\t\tprintf(\"Error - process run ok with invalid \"\n\t\t\t\t\"(with empty socket) --socket-mem!\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(argv7) == 0) {\n\t\tprintf(\"Error - process run ok with invalid (null) --socket-mem!\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(argv8) == 0) {\n\t\tprintf(\"Error - process run ok with --socket-mem and -m specified!\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(argv9) == 0) {\n\t\tprintf(\"Error - process run ok with extra socket in --socket-mem!\\n\");\n\t\treturn -1;\n\t}\n\n\tif (launch_proc(argv10) != 0) {\n\t\tprintf(\"Error - process failed with valid --socket-mem!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntest_eal_flags(void)\n{\n\tint ret = 0;\n\n\tret = test_missing_c_flag();\n\tif (ret < 0) {\n\t\tprintf(\"Error in test_missing_c_flag()\\n\");\n\t\treturn ret;\n\t}\n\n\tret = test_master_lcore_flag();\n\tif (ret < 0) {\n\t\tprintf(\"Error in test_master_lcore_flag()\\n\");\n\t\treturn ret;\n\t}\n\n\tret = test_missing_n_flag();\n\tif (ret < 0) {\n\t\tprintf(\"Error in test_missing_n_flag()\\n\");\n\t\treturn ret;\n\t}\n\n\tret = test_no_hpet_flag();\n\tif (ret < 0) {\n\t\tprintf(\"Error in test_no_hpet_flag()\\n\");\n\t\treturn ret;\n\t}\n\n\tret = test_no_huge_flag();\n\tif (ret < 0) {\n\t\tprintf(\"Error in test_no_huge_flag()\\n\");\n\t\treturn ret;\n\t}\n\n\tret = test_whitelist_flag();\n\tif (ret < 0) {\n\t\tprintf(\"Error in test_invalid_whitelist_flag()\\n\");\n\t\treturn ret;\n\t}\n\n\tret = test_invalid_b_flag();\n\tif (ret < 0) {\n\t\tprintf(\"Error in test_invalid_b_flag()\\n\");\n\t\treturn ret;\n\t}\n\n#ifdef RTE_LIBRTE_PMD_RING\n\tret = test_invalid_vdev_flag();\n\tif (ret < 0) {\n\t\tprintf(\"Error in test_invalid_vdev_flag()\\n\");\n\t\treturn ret;\n\t}\n#endif\n\tret = test_invalid_r_flag();\n\tif (ret < 0) {\n\t\tprintf(\"Error in test_invalid_r_flag()\\n\");\n\t\treturn ret;\n\t}\n\n\tret = test_memory_flags();\n\tif (ret < 0) {\n\t\tprintf(\"Error in test_memory_flags()\\n\");\n\t\treturn ret;\n\t}\n\n\tret = test_file_prefix();\n\tif (ret < 0) {\n\t\tprintf(\"Error in test_file_prefix()\\n\");\n\t\treturn ret;\n\t}\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n\tret = test_dom0_misc_flags();\n#else\n\tret = test_misc_flags();\n#endif\n\tif (ret < 0) {\n\t\tprintf(\"Error in test_misc_flags()\");\n\t\treturn ret;\n\t}\n\n\treturn ret;\n}\n\nstatic struct test_command eal_flags_cmd = {\n\t.command = \"eal_flags_autotest\",\n\t.callback = test_eal_flags,\n};\nREGISTER_TEST_COMMAND(eal_flags_cmd);\n" }, { "path": "app/test/test_eal_fs.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"test.h\"\n#include \n#include \n#include \n#include \n\n/* eal_filesystem.h is not a public header file, so use relative path */\n#include \"../../lib/librte_eal/common/eal_filesystem.h\"\n\nstatic int\ntest_parse_sysfs_value(void)\n{\n\tchar filename[PATH_MAX] = \"\";\n\tchar proc_path[PATH_MAX];\n\tchar file_template[] = \"/tmp/eal_test_XXXXXX\";\n\tint tmp_file_handle = -1;\n\tFILE *fd = NULL;\n\tunsigned valid_number;\n\tunsigned long retval = 0;\n\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD doesn't have /proc/pid/fd */\n\treturn 0;\n#endif\n\n\tprintf(\"Testing function eal_parse_sysfs_value()\\n\");\n\n\t/* get a temporary filename to use for all tests - create temp file handle and then\n\t * use /proc to get the actual file that we can open */\n\ttmp_file_handle = mkstemp(file_template);\n\tif (tmp_file_handle == -1) {\n\t\tperror(\"mkstemp() failure\");\n\t\tgoto error;\n\t}\n\tsnprintf(proc_path, sizeof(proc_path), \"/proc/self/fd/%d\", tmp_file_handle);\n\tif (readlink(proc_path, filename, sizeof(filename)) < 0) {\n\t\tperror(\"readlink() failure\");\n\t\tgoto error;\n\t}\n\tprintf(\"Temporary file is: %s\\n\", filename);\n\n\t/* test we get an error value if we use file before it's created */\n\tprintf(\"Test reading a missing file ...\\n\");\n\tif (eal_parse_sysfs_value(\"/dev/not-quite-null\", &retval) == 0) {\n\t\tprintf(\"Error with eal_parse_sysfs_value() - returned success on reading empty file\\n\");\n\t\tgoto error;\n\t}\n\tprintf(\"Confirmed return error when reading empty file\\n\");\n\n\t/* test reading a valid number value with \"\\n\" on the end */\n\tprintf(\"Test reading valid values ...\\n\");\n\tvalid_number = 15;\n\tfd = fopen(filename,\"w\");\n\tif (fd == NULL) {\n\t\tprintf(\"line %d, Error opening %s: %s\\n\", __LINE__, filename, strerror(errno));\n\t\tgoto error;\n\t}\n\tfprintf(fd,\"%u\\n\", valid_number);\n\tfclose(fd);\n\tfd = NULL;\n\tif (eal_parse_sysfs_value(filename, &retval) < 0) {\n\t\tprintf(\"eal_parse_sysfs_value() returned error - test failed\\n\");\n\t\tgoto error;\n\t}\n\tif (retval != valid_number) {\n\t\tprintf(\"Invalid value read by eal_parse_sysfs_value() - test failed\\n\");\n\t\tgoto error;\n\t}\n\tprintf(\"Read '%u\\\\n' ok\\n\", valid_number);\n\n\t/* test reading a valid hex number value with \"\\n\" on the end */\n\tvalid_number = 25;\n\tfd = fopen(filename,\"w\");\n\tif (fd == NULL) {\n\t\tprintf(\"line %d, Error opening %s: %s\\n\", __LINE__, filename, strerror(errno));\n\t\tgoto error;\n\t}\n\tfprintf(fd,\"0x%x\\n\", valid_number);\n\tfclose(fd);\n\tfd = NULL;\n\tif (eal_parse_sysfs_value(filename, &retval) < 0) {\n\t\tprintf(\"eal_parse_sysfs_value() returned error - test failed\\n\");\n\t\tgoto error;\n\t}\n\tif (retval != valid_number) {\n\t\tprintf(\"Invalid value read by eal_parse_sysfs_value() - test failed\\n\");\n\t\tgoto error;\n\t}\n\tprintf(\"Read '0x%x\\\\n' ok\\n\", valid_number);\n\n\tprintf(\"Test reading invalid values ...\\n\");\n\n\t/* test reading an empty file - expect failure!*/\n\tfd = fopen(filename,\"w\");\n\tif (fd == NULL) {\n\t\tprintf(\"line %d, Error opening %s: %s\\n\", __LINE__, filename, strerror(errno));\n\t\tgoto error;\n\t}\n\tfclose(fd);\n\tfd = NULL;\n\tif (eal_parse_sysfs_value(filename, &retval) == 0) {\n\t\tprintf(\"eal_parse_sysfs_value() read invalid value - test failed\\n\");\n\t\tgoto error;\n\t}\n\n\t/* test reading a valid number value *without* \"\\n\" on the end - expect failure!*/\n\tvalid_number = 3;\n\tfd = fopen(filename,\"w\");\n\tif (fd == NULL) {\n\t\tprintf(\"line %d, Error opening %s: %s\\n\", __LINE__, filename, strerror(errno));\n\t\tgoto error;\n\t}\n\tfprintf(fd,\"%u\", valid_number);\n\tfclose(fd);\n\tfd = NULL;\n\tif (eal_parse_sysfs_value(filename, &retval) == 0) {\n\t\tprintf(\"eal_parse_sysfs_value() read invalid value - test failed\\n\");\n\t\tgoto error;\n\t}\n\n\t/* test reading a valid number value followed by string - expect failure!*/\n\tvalid_number = 3;\n\tfd = fopen(filename,\"w\");\n\tif (fd == NULL) {\n\t\tprintf(\"line %d, Error opening %s: %s\\n\", __LINE__, filename, strerror(errno));\n\t\tgoto error;\n\t}\n\tfprintf(fd,\"%uJ\\n\", valid_number);\n\tfclose(fd);\n\tfd = NULL;\n\tif (eal_parse_sysfs_value(filename, &retval) == 0) {\n\t\tprintf(\"eal_parse_sysfs_value() read invalid value - test failed\\n\");\n\t\tgoto error;\n\t}\n\n\t/* test reading a non-numeric value - expect failure!*/\n\tfd = fopen(filename,\"w\");\n\tif (fd == NULL) {\n\t\tprintf(\"line %d, Error opening %s: %s\\n\", __LINE__, filename, strerror(errno));\n\t\tgoto error;\n\t}\n\tfprintf(fd,\"error\\n\");\n\tfclose(fd);\n\tfd = NULL;\n\tif (eal_parse_sysfs_value(filename, &retval) == 0) {\n\t\tprintf(\"eal_parse_sysfs_value() read invalid value - test failed\\n\");\n\t\tgoto error;\n\t}\n\n\tclose(tmp_file_handle);\n\tunlink(filename);\n\tprintf(\"eal_parse_sysfs_value() - OK\\n\");\n\treturn 0;\n\nerror:\n\tif (fd)\n\t\tfclose(fd);\n\tif (tmp_file_handle > 0)\n\t\tclose(tmp_file_handle);\n\tif (filename[0] != '\\0')\n\t\tunlink(filename);\n\treturn -1;\n}\n\nstatic int\ntest_eal_fs(void)\n{\n\tif (test_parse_sysfs_value() < 0)\n\t\treturn -1;\n\treturn 0;\n}\n\nstatic struct test_command eal_fs_cmd = {\n\t.command = \"eal_fs_autotest\",\n\t.callback = test_eal_fs,\n};\nREGISTER_TEST_COMMAND(eal_fs_cmd);\n" }, { "path": "app/test/test_errno.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\nstatic int\ntest_errno(void)\n{\n\tconst char *rte_retval;\n\tconst char *libc_retval;\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t/* BSD has a colon in the string, unlike linux */\n\tconst char unknown_code_result[] = \"Unknown error: %d\";\n#else\n\tconst char unknown_code_result[] = \"Unknown error %d\";\n#endif\n\tchar expected_libc_retval[sizeof(unknown_code_result)+3];\n\n\t/* use a small selection of standard errors for testing */\n\tint std_errs[] = {EAGAIN, EBADF, EACCES, EINTR, EINVAL};\n\t/* test ALL registered RTE error codes for overlap */\n\tint rte_errs[] = {E_RTE_SECONDARY, E_RTE_NO_CONFIG};\n\tunsigned i;\n\n\trte_errno = 0;\n\tif (rte_errno != 0)\n\t\treturn -1;\n\t/* check for standard errors we return the same as libc */\n\tfor (i = 0; i < sizeof(std_errs)/sizeof(std_errs[0]); i++){\n\t\trte_retval = rte_strerror(std_errs[i]);\n\t\tlibc_retval = strerror(std_errs[i]);\n\t\tprintf(\"rte_strerror: '%s', strerror: '%s'\\n\",\n\t\t\t\trte_retval, libc_retval);\n\t\tif (strcmp(rte_retval, libc_retval) != 0)\n\t\t\treturn -1;\n\t}\n\t/* for rte-specific errors ensure we return a different string\n\t * and that the string for libc is for an unknown error\n\t */\n\tfor (i = 0; i < sizeof(rte_errs)/sizeof(rte_errs[0]); i++){\n\t\trte_retval = rte_strerror(rte_errs[i]);\n\t\tlibc_retval = strerror(rte_errs[i]);\n\t\tprintf(\"rte_strerror: '%s', strerror: '%s'\\n\",\n\t\t\t\trte_retval, libc_retval);\n\t\tif (strcmp(rte_retval, libc_retval) == 0)\n\t\t\treturn -1;\n\t\t/* generate appropriate error string for unknown error number\n\t\t * and then check that this is what we got back. If not, we have\n\t\t * a duplicate error number that conflicts with errno.h */\n\t\tsnprintf(expected_libc_retval, sizeof(expected_libc_retval),\n\t\t\t\tunknown_code_result, rte_errs[i]);\n\t\tif ((strcmp(expected_libc_retval, libc_retval) != 0) &&\n\t\t\t\t(strcmp(\"\", libc_retval) != 0)){\n\t\t\tprintf(\"Error, duplicate error code %d\\n\", rte_errs[i]);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* ensure that beyond RTE_MAX_ERRNO, we always get an unknown code */\n\trte_retval = rte_strerror(RTE_MAX_ERRNO + 1);\n\tlibc_retval = strerror(RTE_MAX_ERRNO + 1);\n\tsnprintf(expected_libc_retval, sizeof(expected_libc_retval),\n\t\t\tunknown_code_result, RTE_MAX_ERRNO + 1);\n\tprintf(\"rte_strerror: '%s', strerror: '%s'\\n\",\n\t\t\trte_retval, libc_retval);\n\tif ((strcmp(rte_retval, libc_retval) != 0) ||\n\t\t\t(strcmp(expected_libc_retval, libc_retval) != 0)){\n\t\tif (strcmp(\"\", libc_retval) != 0){\n\t\t\tprintf(\"Failed test for RTE_MAX_ERRNO + 1 value\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic struct test_command errno_cmd = {\n\t.command = \"errno_autotest\",\n\t.callback = test_errno,\n};\nREGISTER_TEST_COMMAND(errno_cmd);\n" }, { "path": "app/test/test_func_reentrancy.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#ifdef RTE_LIBRTE_HASH\n#include \n#include \n#include \n#endif /* RTE_LIBRTE_HASH */\n\n#ifdef RTE_LIBRTE_LPM\n#include \n#endif /* RTE_LIBRTE_LPM */\n\n#include \n\n#include \"test.h\"\n\ntypedef int (*case_func_t)(void* arg);\ntypedef void (*case_clean_t)(unsigned lcore_id);\n\n#define MAX_STRING_SIZE (256)\n#define MAX_ITER_TIMES (16)\n#define MAX_LPM_ITER_TIMES (8)\n\n#define MEMPOOL_ELT_SIZE (0)\n#define MEMPOOL_SIZE (4)\n\n#define MAX_LCORES\tRTE_MAX_MEMZONE / (MAX_ITER_TIMES * 4U)\n\nstatic rte_atomic32_t synchro = RTE_ATOMIC32_INIT(0);\n\n#define WAIT_SYNCHRO_FOR_SLAVES() do{ \\\n\tif (lcore_self != rte_get_master_lcore()) \\\n\t\twhile (rte_atomic32_read(&synchro) == 0); \\\n} while(0)\n\n/*\n * rte_eal_init only init once\n */\nstatic int\ntest_eal_init_once(__attribute__((unused)) void *arg)\n{\n\tunsigned lcore_self = rte_lcore_id();\n\n\tWAIT_SYNCHRO_FOR_SLAVES();\n\n\tif (rte_eal_init(0, NULL) != -1)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * ring create/lookup reentrancy test\n */\nstatic int\nring_create_lookup(__attribute__((unused)) void *arg)\n{\n\tunsigned lcore_self = rte_lcore_id();\n\tstruct rte_ring * rp;\n\tchar ring_name[MAX_STRING_SIZE];\n\tint i;\n\n\tWAIT_SYNCHRO_FOR_SLAVES();\n\n\t/* create the same ring simultaneously on all threads */\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\trp = rte_ring_create(\"fr_test_once\", 4096, SOCKET_ID_ANY, 0);\n\t\tif ((NULL == rp) && (rte_ring_lookup(\"fr_test_once\") == NULL))\n\t\t\treturn -1;\n\t}\n\n\t/* create/lookup new ring several times */\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\tsnprintf(ring_name, sizeof(ring_name), \"fr_test_%d_%d\", lcore_self, i);\n\t\trp = rte_ring_create(ring_name, 4096, SOCKET_ID_ANY, 0);\n\t\tif (NULL == rp)\n\t\t\treturn -1;\n\t\tif (rte_ring_lookup(ring_name) != rp)\n\t\t\treturn -1;\n\t}\n\n\t/* verify all ring created sucessful */\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\tsnprintf(ring_name, sizeof(ring_name), \"fr_test_%d_%d\", lcore_self, i);\n\t\tif (rte_ring_lookup(ring_name) == NULL)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic void\nmy_obj_init(struct rte_mempool *mp, __attribute__((unused)) void *arg,\n\t void *obj, unsigned i)\n{\n\tuint32_t *objnum = obj;\n\tmemset(obj, 0, mp->elt_size);\n\t*objnum = i;\n}\n\nstatic int\nmempool_create_lookup(__attribute__((unused)) void *arg)\n{\n\tunsigned lcore_self = rte_lcore_id();\n\tstruct rte_mempool * mp;\n\tchar mempool_name[MAX_STRING_SIZE];\n\tint i;\n\n\tWAIT_SYNCHRO_FOR_SLAVES();\n\n\t/* create the same mempool simultaneously on all threads */\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\tmp = rte_mempool_create(\"fr_test_once\", MEMPOOL_SIZE,\n\t\t\t\t\tMEMPOOL_ELT_SIZE, 0, 0,\n\t\t\t\t\tNULL, NULL,\n\t\t\t\t\tmy_obj_init, NULL,\n\t\t\t\t\tSOCKET_ID_ANY, 0);\n\t\tif ((NULL == mp) && (rte_mempool_lookup(\"fr_test_once\") == NULL))\n\t\t\treturn -1;\n\t}\n\n\t/* create/lookup new ring several times */\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\tsnprintf(mempool_name, sizeof(mempool_name), \"fr_test_%d_%d\", lcore_self, i);\n\t\tmp = rte_mempool_create(mempool_name, MEMPOOL_SIZE,\n\t\t\t\t\t\tMEMPOOL_ELT_SIZE, 0, 0,\n\t\t\t\t\t\tNULL, NULL,\n\t\t\t\t\t\tmy_obj_init, NULL,\n\t\t\t\t\t\tSOCKET_ID_ANY, 0);\n\t\tif (NULL == mp)\n\t\t\treturn -1;\n\t\tif (rte_mempool_lookup(mempool_name) != mp)\n\t\t\treturn -1;\n\t}\n\n\t/* verify all ring created sucessful */\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\tsnprintf(mempool_name, sizeof(mempool_name), \"fr_test_%d_%d\", lcore_self, i);\n\t\tif (rte_mempool_lookup(mempool_name) == NULL)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n#ifdef RTE_LIBRTE_HASH\nstatic void\nhash_clean(unsigned lcore_id)\n{\n\tchar hash_name[MAX_STRING_SIZE];\n\tstruct rte_hash *handle;\n\tint i;\n\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\tsnprintf(hash_name, sizeof(hash_name), \"fr_test_%d_%d\", lcore_id, i);\n\n\t\tif ((handle = rte_hash_find_existing(hash_name)) != NULL)\n\t\t\trte_hash_free(handle);\n\t}\n}\n\nstatic int\nhash_create_free(__attribute__((unused)) void *arg)\n{\n\tunsigned lcore_self = rte_lcore_id();\n\tstruct rte_hash *handle;\n\tchar hash_name[MAX_STRING_SIZE];\n\tint i;\n\tstruct rte_hash_parameters hash_params = {\n\t\t.name = NULL,\n\t\t.entries = 16,\n\t\t.key_len = 4,\n\t\t.hash_func = (rte_hash_function)rte_jhash_32b,\n\t\t.hash_func_init_val = 0,\n\t\t.socket_id = 0,\n\t};\n\n\tWAIT_SYNCHRO_FOR_SLAVES();\n\n\t/* create the same hash simultaneously on all threads */\n\thash_params.name = \"fr_test_once\";\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\thandle = rte_hash_create(&hash_params);\n\t\tif ((NULL == handle) && (rte_hash_find_existing(\"fr_test_once\") == NULL))\n\t\t\treturn -1;\n\t}\n\n\t/* create mutiple times simultaneously */\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\tsnprintf(hash_name, sizeof(hash_name), \"fr_test_%d_%d\", lcore_self, i);\n\t\thash_params.name = hash_name;\n\n\t\thandle = rte_hash_create(&hash_params);\n\t\tif (NULL == handle)\n\t\t\treturn -1;\n\n\t\t/* verify correct existing and then free all */\n\t\tif (handle != rte_hash_find_existing(hash_name))\n\t\t\treturn -1;\n\n\t\trte_hash_free(handle);\n\t}\n\n\t/* verify free correct */\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\tsnprintf(hash_name, sizeof(hash_name), \"fr_test_%d_%d\", lcore_self, i);\n\n\t\tif (NULL != rte_hash_find_existing(hash_name))\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic void\nfbk_clean(unsigned lcore_id)\n{\n\tchar fbk_name[MAX_STRING_SIZE];\n\tstruct rte_fbk_hash_table *handle;\n\tint i;\n\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\tsnprintf(fbk_name, sizeof(fbk_name), \"fr_test_%d_%d\", lcore_id, i);\n\n\t\tif ((handle = rte_fbk_hash_find_existing(fbk_name)) != NULL)\n\t\t\trte_fbk_hash_free(handle);\n\t}\n}\n\nstatic int\nfbk_create_free(__attribute__((unused)) void *arg)\n{\n\tunsigned lcore_self = rte_lcore_id();\n\tstruct rte_fbk_hash_table *handle;\n\tchar fbk_name[MAX_STRING_SIZE];\n\tint i;\n\tstruct rte_fbk_hash_params fbk_params = {\n\t\t.name = NULL,\n\t\t.entries = 4,\n\t\t.entries_per_bucket = 4,\n\t\t.socket_id = 0,\n\t\t.hash_func = rte_jhash_1word,\n\t\t.init_val = RTE_FBK_HASH_INIT_VAL_DEFAULT,\n\t};\n\n\tWAIT_SYNCHRO_FOR_SLAVES();\n\n\t/* create the same fbk hash table simultaneously on all threads */\n\tfbk_params.name = \"fr_test_once\";\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\thandle = rte_fbk_hash_create(&fbk_params);\n\t\tif ((NULL == handle) && (rte_fbk_hash_find_existing(\"fr_test_once\") == NULL))\n\t\t\treturn -1;\n\t}\n\n\t/* create mutiple fbk tables simultaneously */\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\tsnprintf(fbk_name, sizeof(fbk_name), \"fr_test_%d_%d\", lcore_self, i);\n\t\tfbk_params.name = fbk_name;\n\n\t\thandle = rte_fbk_hash_create(&fbk_params);\n\t\tif (NULL == handle)\n\t\t\treturn -1;\n\n\t\t/* verify correct existing and then free all */\n\t\tif (handle != rte_fbk_hash_find_existing(fbk_name))\n\t\t\treturn -1;\n\n\t\trte_fbk_hash_free(handle);\n\t}\n\n\t/* verify free correct */\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\tsnprintf(fbk_name, sizeof(fbk_name), \"fr_test_%d_%d\", lcore_self, i);\n\n\t\tif (NULL != rte_fbk_hash_find_existing(fbk_name))\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n#endif /* RTE_LIBRTE_HASH */\n\n#ifdef RTE_LIBRTE_LPM\nstatic void\nlpm_clean(unsigned lcore_id)\n{\n\tchar lpm_name[MAX_STRING_SIZE];\n\tstruct rte_lpm *lpm;\n\tint i;\n\n\tfor (i = 0; i < MAX_LPM_ITER_TIMES; i++) {\n\t\tsnprintf(lpm_name, sizeof(lpm_name), \"fr_test_%d_%d\", lcore_id, i);\n\n\t\tif ((lpm = rte_lpm_find_existing(lpm_name)) != NULL)\n\t\t\trte_lpm_free(lpm);\n\t}\n}\n\nstatic int\nlpm_create_free(__attribute__((unused)) void *arg)\n{\n\tunsigned lcore_self = rte_lcore_id();\n\tstruct rte_lpm *lpm;\n\tchar lpm_name[MAX_STRING_SIZE];\n\tint i;\n\n\tWAIT_SYNCHRO_FOR_SLAVES();\n\n\t/* create the same lpm simultaneously on all threads */\n\tfor (i = 0; i < MAX_ITER_TIMES; i++) {\n\t\tlpm = rte_lpm_create(\"fr_test_once\", SOCKET_ID_ANY, 4, RTE_LPM_HEAP);\n\t\tif ((NULL == lpm) && (rte_lpm_find_existing(\"fr_test_once\") == NULL))\n\t\t\treturn -1;\n\t}\n\n\t/* create mutiple fbk tables simultaneously */\n\tfor (i = 0; i < MAX_LPM_ITER_TIMES; i++) {\n\t\tsnprintf(lpm_name, sizeof(lpm_name), \"fr_test_%d_%d\", lcore_self, i);\n\t\tlpm = rte_lpm_create(lpm_name, SOCKET_ID_ANY, 4, RTE_LPM_HEAP);\n\t\tif (NULL == lpm)\n\t\t\treturn -1;\n\n\t\t/* verify correct existing and then free all */\n\t\tif (lpm != rte_lpm_find_existing(lpm_name))\n\t\t\treturn -1;\n\n\t\trte_lpm_free(lpm);\n\t}\n\n\t/* verify free correct */\n\tfor (i = 0; i < MAX_LPM_ITER_TIMES; i++) {\n\t\tsnprintf(lpm_name, sizeof(lpm_name), \"fr_test_%d_%d\", lcore_self, i);\n\t\tif (NULL != rte_lpm_find_existing(lpm_name))\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n#endif /* RTE_LIBRTE_LPM */\n\nstruct test_case{\n\tcase_func_t func;\n\tvoid* arg;\n\tcase_clean_t clean;\n\tchar name[MAX_STRING_SIZE];\n};\n\n/* All test cases in the test suite */\nstruct test_case test_cases[] = {\n\t{ test_eal_init_once, NULL, NULL, \"eal init once\" },\n\t{ ring_create_lookup, NULL, NULL, \"ring create/lookup\" },\n\t{ mempool_create_lookup, NULL, NULL, \"mempool create/lookup\" },\n#ifdef RTE_LIBRTE_HASH\n\t{ hash_create_free, NULL, hash_clean, \"hash create/free\" },\n\t{ fbk_create_free, NULL, fbk_clean, \"fbk create/free\" },\n#endif /* RTE_LIBRTE_HASH */\n#ifdef RTE_LIBRTE_LPM\n\t{ lpm_create_free, NULL, lpm_clean, \"lpm create/free\" },\n#endif /* RTE_LIBRTE_LPM */\n};\n\n/**\n * launch test case in two separate thread\n */\nstatic int\nlaunch_test(struct test_case *pt_case)\n{\n\tint ret = 0;\n\tunsigned lcore_id;\n\tunsigned cores_save = rte_lcore_count();\n\tunsigned cores = RTE_MIN(cores_save, MAX_LCORES);\n\n\tif (pt_case->func == NULL)\n\t\treturn -1;\n\n\trte_atomic32_set(&synchro, 0);\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (cores == 1)\n\t\t\tbreak;\n\t\tcores--;\n\t\trte_eal_remote_launch(pt_case->func, pt_case->arg, lcore_id);\n\t}\n\n\trte_atomic32_set(&synchro, 1);\n\n\tif (pt_case->func(pt_case->arg) < 0)\n\t\tret = -1;\n\n\tcores = cores_save;\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (cores == 1)\n\t\t\tbreak;\n\t\tcores--;\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\tret = -1;\n\n\t\tif (pt_case->clean != NULL)\n\t\t\tpt_case->clean(lcore_id);\n\t}\n\n\treturn ret;\n}\n\n/**\n * Main entry of func_reentrancy test\n */\nstatic int\ntest_func_reentrancy(void)\n{\n\tuint32_t case_id;\n\tstruct test_case *pt_case = NULL;\n\n\tif (rte_lcore_count() <= 1) {\n\t\tprintf(\"Not enough lcore for testing\\n\");\n\t\treturn -1;\n\t}\n\telse if (rte_lcore_count() > MAX_LCORES)\n\t\tprintf(\"Too many lcores, some cores will be disabled\\n\");\n\n\tfor (case_id = 0; case_id < sizeof(test_cases)/sizeof(struct test_case); case_id ++) {\n\t\tpt_case = &test_cases[case_id];\n\t\tif (pt_case->func == NULL)\n\t\t\tcontinue;\n\n\t\tif (launch_test(pt_case) < 0) {\n\t\t\tprintf(\"Func-ReEnt CASE %\"PRIu32\": %s FAIL\\n\", case_id, pt_case->name);\n\t\t\treturn -1;\n\t\t}\n\t\tprintf(\"Func-ReEnt CASE %\"PRIu32\": %s PASS\\n\", case_id, pt_case->name);\n\t}\n\n\treturn 0;\n}\n\nstatic struct test_command func_reentrancy_cmd = {\n\t.command = \"func_reentrancy_autotest\",\n\t.callback = test_func_reentrancy,\n};\nREGISTER_TEST_COMMAND(func_reentrancy_cmd);\n" }, { "path": "app/test/test_hash.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#include \n#include \n#include \n#include \n\n/*******************************************************************************\n * Hash function performance test configuration section. Each performance test\n * will be performed HASHTEST_ITERATIONS times.\n *\n * The five arrays below control what tests are performed. Every combination\n * from the array entries is tested.\n */\nstatic rte_hash_function hashtest_funcs[] = {rte_jhash, rte_hash_crc};\nstatic uint32_t hashtest_initvals[] = {0};\nstatic uint32_t hashtest_key_lens[] = {0, 2, 4, 5, 6, 7, 8, 10, 11, 15, 16, 21, 31, 32, 33, 63, 64};\n/******************************************************************************/\n#define LOCAL_FBK_HASH_ENTRIES_MAX (1 << 15)\n\n/*\n * Check condition and return an error if true. Assumes that \"handle\" is the\n * name of the hash structure pointer to be freed.\n */\n#define RETURN_IF_ERROR(cond, str, ...) do {\t\t\t\t\\\n\tif (cond) {\t\t\t\t\t\t\t\\\n\t\tprintf(\"ERROR line %d: \" str \"\\n\", __LINE__, ##__VA_ARGS__); \\\n\t\tif (handle) rte_hash_free(handle);\t\t\t\\\n\t\treturn -1;\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n} while(0)\n\n#define RETURN_IF_ERROR_FBK(cond, str, ...) do {\t\t\t\t\\\n\tif (cond) {\t\t\t\t\t\t\t\\\n\t\tprintf(\"ERROR line %d: \" str \"\\n\", __LINE__, ##__VA_ARGS__); \\\n\t\tif (handle) rte_fbk_hash_free(handle);\t\t\t\\\n\t\treturn -1;\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n} while(0)\n\n/* 5-tuple key type */\nstruct flow_key {\n\tuint32_t ip_src;\n\tuint32_t ip_dst;\n\tuint16_t port_src;\n\tuint16_t port_dst;\n\tuint8_t proto;\n} __attribute__((packed));\n\n/*\n * Hash function that always returns the same value, to easily test what\n * happens when a bucket is full.\n */\nstatic uint32_t pseudo_hash(__attribute__((unused)) const void *keys,\n\t\t\t __attribute__((unused)) uint32_t key_len,\n\t\t\t __attribute__((unused)) uint32_t init_val)\n{\n\treturn 3;\n}\n\n/*\n * Print out result of unit test hash operation.\n */\n#if defined(UNIT_TEST_HASH_VERBOSE)\nstatic void print_key_info(const char *msg, const struct flow_key *key,\n\t\t\t\t\t\t\t\tint32_t pos)\n{\n\tuint8_t *p = (uint8_t *)key;\n\tunsigned i;\n\n\tprintf(\"%s key:0x\", msg);\n\tfor (i = 0; i < sizeof(struct flow_key); i++) {\n\t\tprintf(\"%02X\", p[i]);\n\t}\n\tprintf(\" @ pos %d\\n\", pos);\n}\n#else\nstatic void print_key_info(__attribute__((unused)) const char *msg,\n\t\t__attribute__((unused)) const struct flow_key *key,\n\t\t__attribute__((unused)) int32_t pos)\n{\n}\n#endif\n\n/* Keys used by unit test functions */\nstatic struct flow_key keys[5] = { {\n\t.ip_src = IPv4(0x03, 0x02, 0x01, 0x00),\n\t.ip_dst = IPv4(0x07, 0x06, 0x05, 0x04),\n\t.port_src = 0x0908,\n\t.port_dst = 0x0b0a,\n\t.proto = 0x0c,\n}, {\n\t.ip_src = IPv4(0x13, 0x12, 0x11, 0x10),\n\t.ip_dst = IPv4(0x17, 0x16, 0x15, 0x14),\n\t.port_src = 0x1918,\n\t.port_dst = 0x1b1a,\n\t.proto = 0x1c,\n}, {\n\t.ip_src = IPv4(0x23, 0x22, 0x21, 0x20),\n\t.ip_dst = IPv4(0x27, 0x26, 0x25, 0x24),\n\t.port_src = 0x2928,\n\t.port_dst = 0x2b2a,\n\t.proto = 0x2c,\n}, {\n\t.ip_src = IPv4(0x33, 0x32, 0x31, 0x30),\n\t.ip_dst = IPv4(0x37, 0x36, 0x35, 0x34),\n\t.port_src = 0x3938,\n\t.port_dst = 0x3b3a,\n\t.proto = 0x3c,\n}, {\n\t.ip_src = IPv4(0x43, 0x42, 0x41, 0x40),\n\t.ip_dst = IPv4(0x47, 0x46, 0x45, 0x44),\n\t.port_src = 0x4948,\n\t.port_dst = 0x4b4a,\n\t.proto = 0x4c,\n} };\n\n/* Parameters used for hash table in unit test functions. Name set later. */\nstatic struct rte_hash_parameters ut_params = {\n\t.entries = 64,\n\t.key_len = sizeof(struct flow_key), /* 13 */\n\t.hash_func = rte_jhash,\n\t.hash_func_init_val = 0,\n\t.socket_id = 0,\n};\n\n#define CRC32_ITERATIONS (1U << 20)\n#define CRC32_DWORDS (1U << 6)\n/*\n * Test if all CRC32 implementations yield the same hash value\n */\nstatic int\ntest_crc32_hash_alg_equiv(void)\n{\n\tuint32_t hash_val;\n\tuint32_t init_val;\n\tuint64_t data64[CRC32_DWORDS];\n\tunsigned i, j;\n\tsize_t data_len;\n\n\tprintf(\"\\n# CRC32 implementations equivalence test\\n\");\n\tfor (i = 0; i < CRC32_ITERATIONS; i++) {\n\t\t/* Randomizing data_len of data set */\n\t\tdata_len = (size_t) ((rte_rand() % sizeof(data64)) + 1);\n\t\tinit_val = (uint32_t) rte_rand();\n\n\t\t/* Fill the data set */\n\t\tfor (j = 0; j < CRC32_DWORDS; j++)\n\t\t\tdata64[j] = rte_rand();\n\n\t\t/* Calculate software CRC32 */\n\t\trte_hash_crc_set_alg(CRC32_SW);\n\t\thash_val = rte_hash_crc(data64, data_len, init_val);\n\n\t\t/* Check against 4-byte-operand sse4.2 CRC32 if available */\n\t\trte_hash_crc_set_alg(CRC32_SSE42);\n\t\tif (hash_val != rte_hash_crc(data64, data_len, init_val)) {\n\t\t\tprintf(\"Failed checking CRC32_SW against CRC32_SSE42\\n\");\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Check against 8-byte-operand sse4.2 CRC32 if available */\n\t\trte_hash_crc_set_alg(CRC32_SSE42_x64);\n\t\tif (hash_val != rte_hash_crc(data64, data_len, init_val)) {\n\t\t\tprintf(\"Failed checking CRC32_SW against CRC32_SSE42_x64\\n\");\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Resetting to best available algorithm */\n\trte_hash_crc_set_alg(CRC32_SSE42_x64);\n\n\tif (i == CRC32_ITERATIONS)\n\t\treturn 0;\n\n\tprintf(\"Failed test data (hex, %zu bytes total):\\n\", data_len);\n\tfor (j = 0; j < data_len; j++)\n\t\tprintf(\"%02X%c\", ((uint8_t *)data64)[j],\n\t\t\t\t((j+1) % 16 == 0 || j == data_len - 1) ? '\\n' : ' ');\n\n\treturn -1;\n}\n\n/*\n * Test a hash function.\n */\nstatic void run_hash_func_test(rte_hash_function f, uint32_t init_val,\n\t\tuint32_t key_len)\n{\n\tstatic uint8_t key[RTE_HASH_KEY_LENGTH_MAX];\n\tunsigned i;\n\n\n\tfor (i = 0; i < key_len; i++)\n\t\tkey[i] = (uint8_t) rte_rand();\n\n\t/* just to be on the safe side */\n\tif (!f)\n\t\treturn;\n\n\tf(key, key_len, init_val);\n}\n\n/*\n * Test all hash functions.\n */\nstatic void run_hash_func_tests(void)\n{\n\tunsigned i, j, k;\n\n\tfor (i = 0;\n\t i < sizeof(hashtest_funcs) / sizeof(rte_hash_function);\n\t i++) {\n\t\tfor (j = 0;\n\t\t j < sizeof(hashtest_initvals) / sizeof(uint32_t);\n\t\t j++) {\n\t\t\tfor (k = 0;\n\t\t\t k < sizeof(hashtest_key_lens) / sizeof(uint32_t);\n\t\t\t k++) {\n\t\t\t\trun_hash_func_test(hashtest_funcs[i],\n\t\t\t\t\t\thashtest_initvals[j],\n\t\t\t\t\t\thashtest_key_lens[k]);\n\t\t\t}\n\t\t}\n\t}\n}\n\n/*\n * Basic sequence of operations for a single key:\n *\t- add\n *\t- lookup (hit)\n *\t- delete\n *\t- lookup (miss)\n */\nstatic int test_add_delete(void)\n{\n\tstruct rte_hash *handle;\n\t/* test with standard add/lookup/delete functions */\n\tint pos0, expectedPos0;\n\n\tut_params.name = \"test1\";\n\thandle = rte_hash_create(&ut_params);\n\tRETURN_IF_ERROR(handle == NULL, \"hash creation failed\");\n\n\tpos0 = rte_hash_add_key(handle, &keys[0]);\n\tprint_key_info(\"Add\", &keys[0], pos0);\n\tRETURN_IF_ERROR(pos0 < 0, \"failed to add key (pos0=%d)\", pos0);\n\texpectedPos0 = pos0;\n\n\tpos0 = rte_hash_lookup(handle, &keys[0]);\n\tprint_key_info(\"Lkp\", &keys[0], pos0);\n\tRETURN_IF_ERROR(pos0 != expectedPos0,\n\t\t\t\"failed to find key (pos0=%d)\", pos0);\n\n\tpos0 = rte_hash_del_key(handle, &keys[0]);\n\tprint_key_info(\"Del\", &keys[0], pos0);\n\tRETURN_IF_ERROR(pos0 != expectedPos0,\n\t\t\t\"failed to delete key (pos0=%d)\", pos0);\n\n\tpos0 = rte_hash_lookup(handle, &keys[0]);\n\tprint_key_info(\"Lkp\", &keys[0], pos0);\n\tRETURN_IF_ERROR(pos0 != -ENOENT,\n\t\t\t\"fail: found key after deleting! (pos0=%d)\", pos0);\n\n\trte_hash_free(handle);\n\n\t/* repeat test with precomputed hash functions */\n\thash_sig_t hash_value;\n\tint pos1, expectedPos1;\n\n\thandle = rte_hash_create(&ut_params);\n\tRETURN_IF_ERROR(handle == NULL, \"hash creation failed\");\n\n\thash_value = rte_hash_hash(handle, &keys[0]);\n\tpos1 = rte_hash_add_key_with_hash(handle, &keys[0], hash_value);\n\tprint_key_info(\"Add\", &keys[0], pos1);\n\tRETURN_IF_ERROR(pos1 < 0, \"failed to add key (pos1=%d)\", pos1);\n\texpectedPos1 = pos1;\n\n\tpos1 = rte_hash_lookup_with_hash(handle, &keys[0], hash_value);\n\tprint_key_info(\"Lkp\", &keys[0], pos1);\n\tRETURN_IF_ERROR(pos1 != expectedPos1,\n\t\t\t\"failed to find key (pos1=%d)\", pos1);\n\n\tpos1 = rte_hash_del_key_with_hash(handle, &keys[0], hash_value);\n\tprint_key_info(\"Del\", &keys[0], pos1);\n\tRETURN_IF_ERROR(pos1 != expectedPos1,\n\t\t\t\"failed to delete key (pos1=%d)\", pos1);\n\n\tpos1 = rte_hash_lookup_with_hash(handle, &keys[0], hash_value);\n\tprint_key_info(\"Lkp\", &keys[0], pos1);\n\tRETURN_IF_ERROR(pos1 != -ENOENT,\n\t\t\t\"fail: found key after deleting! (pos1=%d)\", pos1);\n\n\trte_hash_free(handle);\n\n\treturn 0;\n}\n\n/*\n * Sequence of operations for a single key:\n *\t- delete: miss\n *\t- add\n *\t- lookup: hit\n *\t- add: update\n *\t- lookup: hit (updated data)\n *\t- delete: hit\n *\t- delete: miss\n *\t- lookup: miss\n */\nstatic int test_add_update_delete(void)\n{\n\tstruct rte_hash *handle;\n\tint pos0, expectedPos0;\n\n\tut_params.name = \"test2\";\n\thandle = rte_hash_create(&ut_params);\n\tRETURN_IF_ERROR(handle == NULL, \"hash creation failed\");\n\n\tpos0 = rte_hash_del_key(handle, &keys[0]);\n\tprint_key_info(\"Del\", &keys[0], pos0);\n\tRETURN_IF_ERROR(pos0 != -ENOENT,\n\t\t\t\"fail: found non-existent key (pos0=%d)\", pos0);\n\n\tpos0 = rte_hash_add_key(handle, &keys[0]);\n\tprint_key_info(\"Add\", &keys[0], pos0);\n\tRETURN_IF_ERROR(pos0 < 0, \"failed to add key (pos0=%d)\", pos0);\n\texpectedPos0 = pos0;\n\n\tpos0 = rte_hash_lookup(handle, &keys[0]);\n\tprint_key_info(\"Lkp\", &keys[0], pos0);\n\tRETURN_IF_ERROR(pos0 != expectedPos0,\n\t\t\t\"failed to find key (pos0=%d)\", pos0);\n\n\tpos0 = rte_hash_add_key(handle, &keys[0]);\n\tprint_key_info(\"Add\", &keys[0], pos0);\n\tRETURN_IF_ERROR(pos0 != expectedPos0,\n\t\t\t\"failed to re-add key (pos0=%d)\", pos0);\n\n\tpos0 = rte_hash_lookup(handle, &keys[0]);\n\tprint_key_info(\"Lkp\", &keys[0], pos0);\n\tRETURN_IF_ERROR(pos0 != expectedPos0,\n\t\t\t\"failed to find key (pos0=%d)\", pos0);\n\n\tpos0 = rte_hash_del_key(handle, &keys[0]);\n\tprint_key_info(\"Del\", &keys[0], pos0);\n\tRETURN_IF_ERROR(pos0 != expectedPos0,\n\t\t\t\"failed to delete key (pos0=%d)\", pos0);\n\n\tpos0 = rte_hash_del_key(handle, &keys[0]);\n\tprint_key_info(\"Del\", &keys[0], pos0);\n\tRETURN_IF_ERROR(pos0 != -ENOENT,\n\t\t\t\"fail: deleted already deleted key (pos0=%d)\", pos0);\n\n\tpos0 = rte_hash_lookup(handle, &keys[0]);\n\tprint_key_info(\"Lkp\", &keys[0], pos0);\n\tRETURN_IF_ERROR(pos0 != -ENOENT,\n\t\t\t\"fail: found key after deleting! (pos0=%d)\", pos0);\n\n\trte_hash_free(handle);\n\treturn 0;\n}\n\n/*\n * Sequence of operations for find existing hash table\n *\n * - create table\n * - find existing table: hit\n * - find non-existing table: miss\n *\n */\nstatic int test_hash_find_existing(void)\n{\n\tstruct rte_hash *handle = NULL, *result = NULL;\n\n\t/* Create hash table. */\n\tut_params.name = \"hash_find_existing\";\n\thandle = rte_hash_create(&ut_params);\n\tRETURN_IF_ERROR(handle == NULL, \"hash creation failed\");\n\n\t/* Try to find existing hash table */\n\tresult = rte_hash_find_existing(\"hash_find_existing\");\n\tRETURN_IF_ERROR(result != handle, \"could not find existing hash table\");\n\n\t/* Try to find non-existing hash table */\n\tresult = rte_hash_find_existing(\"hash_find_non_existing\");\n\tRETURN_IF_ERROR(!(result == NULL), \"found table that shouldn't exist\");\n\n\t/* Cleanup. */\n\trte_hash_free(handle);\n\n\treturn 0;\n}\n\n/*\n * Sequence of operations for 5 keys\n *\t- add keys\n *\t- lookup keys: hit\n *\t- add keys (update)\n *\t- lookup keys: hit (updated data)\n *\t- delete keys : hit\n *\t- lookup keys: miss\n */\nstatic int test_five_keys(void)\n{\n\tstruct rte_hash *handle;\n\tconst void *key_array[5] = {0};\n\tint pos[5];\n\tint expected_pos[5];\n\tunsigned i;\n\tint ret;\n\n\tut_params.name = \"test3\";\n\thandle = rte_hash_create(&ut_params);\n\tRETURN_IF_ERROR(handle == NULL, \"hash creation failed\");\n\n\t/* Add */\n\tfor (i = 0; i < 5; i++) {\n\t\tpos[i] = rte_hash_add_key(handle, &keys[i]);\n\t\tprint_key_info(\"Add\", &keys[i], pos[i]);\n\t\tRETURN_IF_ERROR(pos[i] < 0,\n\t\t\t\t\"failed to add key (pos[%u]=%d)\", i, pos[i]);\n\t\texpected_pos[i] = pos[i];\n\t}\n\n\t/* Lookup */\n\tfor(i = 0; i < 5; i++)\n\t\tkey_array[i] = &keys[i];\n\n\tret = rte_hash_lookup_multi(handle, &key_array[0], 5, (int32_t *)pos);\n\tif(ret == 0)\n\t\tfor(i = 0; i < 5; i++) {\n\t\t\tprint_key_info(\"Lkp\", key_array[i], pos[i]);\n\t\t\tRETURN_IF_ERROR(pos[i] != expected_pos[i],\n\t\t\t\t\t\"failed to find key (pos[%u]=%d)\", i, pos[i]);\n\t\t}\n\n\t/* Add - update */\n\tfor (i = 0; i < 5; i++) {\n\t\tpos[i] = rte_hash_add_key(handle, &keys[i]);\n\t\tprint_key_info(\"Add\", &keys[i], pos[i]);\n\t\tRETURN_IF_ERROR(pos[i] != expected_pos[i],\n\t\t\t\t\"failed to add key (pos[%u]=%d)\", i, pos[i]);\n\t}\n\n\t/* Lookup */\n\tfor (i = 0; i < 5; i++) {\n\t\tpos[i] = rte_hash_lookup(handle, &keys[i]);\n\t\tprint_key_info(\"Lkp\", &keys[i], pos[i]);\n\t\tRETURN_IF_ERROR(pos[i] != expected_pos[i],\n\t\t\t\t\"failed to find key (pos[%u]=%d)\", i, pos[i]);\n\t}\n\n\t/* Delete */\n\tfor (i = 0; i < 5; i++) {\n\t\tpos[i] = rte_hash_del_key(handle, &keys[i]);\n\t\tprint_key_info(\"Del\", &keys[i], pos[i]);\n\t\tRETURN_IF_ERROR(pos[i] != expected_pos[i],\n\t\t\t\t\"failed to delete key (pos[%u]=%d)\", i, pos[i]);\n\t}\n\n\t/* Lookup */\n\tfor (i = 0; i < 5; i++) {\n\t\tpos[i] = rte_hash_lookup(handle, &keys[i]);\n\t\tprint_key_info(\"Lkp\", &keys[i], pos[i]);\n\t\tRETURN_IF_ERROR(pos[i] != -ENOENT,\n\t\t\t\t\"found non-existent key (pos[%u]=%d)\", i, pos[i]);\n\t}\n\n\t/* Lookup multi */\n\tret = rte_hash_lookup_multi(handle, &key_array[0], 5, (int32_t *)pos);\n\tif (ret == 0)\n\t\tfor (i = 0; i < 5; i++) {\n\t\t\tprint_key_info(\"Lkp\", key_array[i], pos[i]);\n\t\t\tRETURN_IF_ERROR(pos[i] != -ENOENT,\n\t\t\t\t\t\"found not-existent key (pos[%u]=%d)\", i, pos[i]);\n\t\t}\n\n\trte_hash_free(handle);\n\n\treturn 0;\n}\n\n/*\n * Add keys to the same bucket until bucket full.\n *\t- add 5 keys to the same bucket (hash created with 4 keys per bucket):\n *\t first 4 successful, 5th successful, pushing existing item in bucket\n *\t- lookup the 5 keys: 5 hits\n *\t- add the 5 keys again: 5 OK\n *\t- lookup the 5 keys: 5 hits (updated data)\n *\t- delete the 5 keys: 5 OK\n *\t- lookup the 5 keys: 5 misses\n */\nstatic int test_full_bucket(void)\n{\n\tstruct rte_hash_parameters params_pseudo_hash = {\n\t\t.name = \"test4\",\n\t\t.entries = 64,\n\t\t.key_len = sizeof(struct flow_key), /* 13 */\n\t\t.hash_func = pseudo_hash,\n\t\t.hash_func_init_val = 0,\n\t\t.socket_id = 0,\n\t};\n\tstruct rte_hash *handle;\n\tint pos[5];\n\tint expected_pos[5];\n\tunsigned i;\n\n\thandle = rte_hash_create(¶ms_pseudo_hash);\n\tRETURN_IF_ERROR(handle == NULL, \"hash creation failed\");\n\n\t/* Fill bucket */\n\tfor (i = 0; i < 4; i++) {\n\t\tpos[i] = rte_hash_add_key(handle, &keys[i]);\n\t\tprint_key_info(\"Add\", &keys[i], pos[i]);\n\t\tRETURN_IF_ERROR(pos[i] < 0,\n\t\t\t\"failed to add key (pos[%u]=%d)\", i, pos[i]);\n\t\texpected_pos[i] = pos[i];\n\t}\n\t/*\n\t * This should work and will push one of the items\n\t * in the bucket because it is full\n\t */\n\tpos[4] = rte_hash_add_key(handle, &keys[4]);\n\tprint_key_info(\"Add\", &keys[4], pos[4]);\n\tRETURN_IF_ERROR(pos[4] < 0,\n\t\t\t\"failed to add key (pos[4]=%d)\", pos[4]);\n\texpected_pos[4] = pos[4];\n\n\t/* Lookup */\n\tfor (i = 0; i < 5; i++) {\n\t\tpos[i] = rte_hash_lookup(handle, &keys[i]);\n\t\tprint_key_info(\"Lkp\", &keys[i], pos[i]);\n\t\tRETURN_IF_ERROR(pos[i] != expected_pos[i],\n\t\t\t\"failed to find key (pos[%u]=%d)\", i, pos[i]);\n\t}\n\n\t/* Add - update */\n\tfor (i = 0; i < 5; i++) {\n\t\tpos[i] = rte_hash_add_key(handle, &keys[i]);\n\t\tprint_key_info(\"Add\", &keys[i], pos[i]);\n\t\tRETURN_IF_ERROR(pos[i] != expected_pos[i],\n\t\t\t\"failed to add key (pos[%u]=%d)\", i, pos[i]);\n\t}\n\n\t/* Lookup */\n\tfor (i = 0; i < 5; i++) {\n\t\tpos[i] = rte_hash_lookup(handle, &keys[i]);\n\t\tprint_key_info(\"Lkp\", &keys[i], pos[i]);\n\t\tRETURN_IF_ERROR(pos[i] != expected_pos[i],\n\t\t\t\"failed to find key (pos[%u]=%d)\", i, pos[i]);\n\t}\n\n\t/* Delete 1 key, check other keys are still found */\n\tpos[1] = rte_hash_del_key(handle, &keys[1]);\n\tprint_key_info(\"Del\", &keys[1], pos[1]);\n\tRETURN_IF_ERROR(pos[1] != expected_pos[1],\n\t\t\t\"failed to delete key (pos[1]=%d)\", pos[1]);\n\tpos[3] = rte_hash_lookup(handle, &keys[3]);\n\tprint_key_info(\"Lkp\", &keys[3], pos[3]);\n\tRETURN_IF_ERROR(pos[3] != expected_pos[3],\n\t\t\t\"failed lookup after deleting key from same bucket \"\n\t\t\t\"(pos[3]=%d)\", pos[3]);\n\n\t/* Go back to previous state */\n\tpos[1] = rte_hash_add_key(handle, &keys[1]);\n\tprint_key_info(\"Add\", &keys[1], pos[1]);\n\texpected_pos[1] = pos[1];\n\tRETURN_IF_ERROR(pos[1] < 0, \"failed to add key (pos[1]=%d)\", pos[1]);\n\n\t/* Delete */\n\tfor (i = 0; i < 5; i++) {\n\t\tpos[i] = rte_hash_del_key(handle, &keys[i]);\n\t\tprint_key_info(\"Del\", &keys[i], pos[i]);\n\t\tRETURN_IF_ERROR(pos[i] != expected_pos[i],\n\t\t\t\"failed to delete key (pos[%u]=%d)\", i, pos[i]);\n\t}\n\n\t/* Lookup */\n\tfor (i = 0; i < 5; i++) {\n\t\tpos[i] = rte_hash_lookup(handle, &keys[i]);\n\t\tprint_key_info(\"Lkp\", &keys[i], pos[i]);\n\t\tRETURN_IF_ERROR(pos[i] != -ENOENT,\n\t\t\t\"fail: found non-existent key (pos[%u]=%d)\", i, pos[i]);\n\t}\n\n\trte_hash_free(handle);\n\n\t/* Cover the NULL case. */\n\trte_hash_free(0);\n\treturn 0;\n}\n\n/******************************************************************************/\nstatic int\nfbk_hash_unit_test(void)\n{\n\tstruct rte_fbk_hash_params params = {\n\t\t.name = \"fbk_hash_test\",\n\t\t.entries = LOCAL_FBK_HASH_ENTRIES_MAX,\n\t\t.entries_per_bucket = 4,\n\t\t.socket_id = 0,\n\t};\n\n\tstruct rte_fbk_hash_params invalid_params_1 = {\n\t\t.name = \"invalid_1\",\n\t\t.entries = LOCAL_FBK_HASH_ENTRIES_MAX + 1, /* Not power of 2 */\n\t\t.entries_per_bucket = 4,\n\t\t.socket_id = 0,\n\t};\n\n\tstruct rte_fbk_hash_params invalid_params_2 = {\n\t\t.name = \"invalid_2\",\n\t\t.entries = 4,\n\t\t.entries_per_bucket = 3, /* Not power of 2 */\n\t\t.socket_id = 0,\n\t};\n\n\tstruct rte_fbk_hash_params invalid_params_3 = {\n\t\t.name = \"invalid_3\",\n\t\t.entries = 0, /* Entries is 0 */\n\t\t.entries_per_bucket = 4,\n\t\t.socket_id = 0,\n\t};\n\n\tstruct rte_fbk_hash_params invalid_params_4 = {\n\t\t.name = \"invalid_4\",\n\t\t.entries = LOCAL_FBK_HASH_ENTRIES_MAX,\n\t\t.entries_per_bucket = 0, /* Entries per bucket is 0 */\n\t\t.socket_id = 0,\n\t};\n\n\tstruct rte_fbk_hash_params invalid_params_5 = {\n\t\t.name = \"invalid_5\",\n\t\t.entries = 4,\n\t\t.entries_per_bucket = 8, /* Entries per bucket > entries */\n\t\t.socket_id = 0,\n\t};\n\n\tstruct rte_fbk_hash_params invalid_params_6 = {\n\t\t.name = \"invalid_6\",\n\t\t.entries = RTE_FBK_HASH_ENTRIES_MAX * 2, /* Entries > max allowed */\n\t\t.entries_per_bucket = 4,\n\t\t.socket_id = 0,\n\t};\n\n\tstruct rte_fbk_hash_params invalid_params_7 = {\n\t\t.name = \"invalid_7\",\n\t\t.entries = RTE_FBK_HASH_ENTRIES_MAX,\n\t\t.entries_per_bucket = RTE_FBK_HASH_ENTRIES_PER_BUCKET_MAX * 2,\t/* Entries > max allowed */\n\t\t.socket_id = 0,\n\t};\n\n\tstruct rte_fbk_hash_params invalid_params_8 = {\n\t\t.name = \"invalid_7\",\n\t\t.entries = RTE_FBK_HASH_ENTRIES_MAX,\n\t\t.entries_per_bucket = 4,\n\t\t.socket_id = RTE_MAX_NUMA_NODES + 1, /* invalid socket */\n\t};\n\n\t/* try to create two hashes with identical names\n\t * in this case, trying to create a second one will not\n\t * fail but will simply return pointer to the existing\n\t * hash with that name. sort of like a \"find hash by name\" :-)\n\t */\n\tstruct rte_fbk_hash_params invalid_params_same_name_1 = {\n\t\t.name = \"same_name\",\t\t\t\t/* hash with identical name */\n\t\t.entries = 4,\n\t\t.entries_per_bucket = 2,\n\t\t.socket_id = 0,\n\t};\n\n\t/* trying to create this hash should return a pointer to an existing hash */\n\tstruct rte_fbk_hash_params invalid_params_same_name_2 = {\n\t\t.name = \"same_name\",\t\t\t\t/* hash with identical name */\n\t\t.entries = RTE_FBK_HASH_ENTRIES_MAX,\n\t\t.entries_per_bucket = 4,\n\t\t.socket_id = 0,\n\t};\n\n\t/* this is a sanity check for \"same name\" test\n\t * creating this hash will check if we are actually able to create\n\t * multiple hashes with different names (instead of having just one).\n\t */\n\tstruct rte_fbk_hash_params different_name = {\n\t\t.name = \"different_name\",\t\t\t/* different name */\n\t\t.entries = RTE_FBK_HASH_ENTRIES_MAX,\n\t\t.entries_per_bucket = 4,\n\t\t.socket_id = 0,\n\t};\n\n\tstruct rte_fbk_hash_params params_jhash = {\n\t\t.name = \"valid\",\n\t\t.entries = LOCAL_FBK_HASH_ENTRIES_MAX,\n\t\t.entries_per_bucket = 4,\n\t\t.socket_id = 0,\n\t\t.hash_func = rte_jhash_1word, /* Tests for different hash_func */\n\t\t.init_val = RTE_FBK_HASH_INIT_VAL_DEFAULT,\n\t};\n\n\tstruct rte_fbk_hash_params params_nohash = {\n\t\t.name = \"valid nohash\",\n\t\t.entries = LOCAL_FBK_HASH_ENTRIES_MAX,\n\t\t.entries_per_bucket = 4,\n\t\t.socket_id = 0,\n\t\t.hash_func = NULL, /* Tests for null hash_func */\n\t\t.init_val = RTE_FBK_HASH_INIT_VAL_DEFAULT,\n\t};\n\n\tstruct rte_fbk_hash_table *handle, *tmp;\n\tuint32_t keys[5] =\n\t\t{0xc6e18639, 0xe67c201c, 0xd4c8cffd, 0x44728691, 0xd5430fa9};\n\tuint16_t vals[5] = {28108, 5699, 38490, 2166, 61571};\n\tint status;\n\tunsigned i;\n\tdouble used_entries;\n\n\t/* Try creating hashes with invalid parameters */\n\tprintf(\"# Testing hash creation with invalid parameters \"\n\t\t\t\"- expect error msgs\\n\");\n\thandle = rte_fbk_hash_create(&invalid_params_1);\n\tRETURN_IF_ERROR_FBK(handle != NULL, \"fbk hash creation should have failed\");\n\n\thandle = rte_fbk_hash_create(&invalid_params_2);\n\tRETURN_IF_ERROR_FBK(handle != NULL, \"fbk hash creation should have failed\");\n\n\thandle = rte_fbk_hash_create(&invalid_params_3);\n\tRETURN_IF_ERROR_FBK(handle != NULL, \"fbk hash creation should have failed\");\n\n\thandle = rte_fbk_hash_create(&invalid_params_4);\n\tRETURN_IF_ERROR_FBK(handle != NULL, \"fbk hash creation should have failed\");\n\n\thandle = rte_fbk_hash_create(&invalid_params_5);\n\tRETURN_IF_ERROR_FBK(handle != NULL, \"fbk hash creation should have failed\");\n\n\thandle = rte_fbk_hash_create(&invalid_params_6);\n\tRETURN_IF_ERROR_FBK(handle != NULL, \"fbk hash creation should have failed\");\n\n\thandle = rte_fbk_hash_create(&invalid_params_7);\n\tRETURN_IF_ERROR_FBK(handle != NULL, \"fbk hash creation should have failed\");\n\n\thandle = rte_fbk_hash_create(&invalid_params_8);\n\tRETURN_IF_ERROR_FBK(handle != NULL, \"fbk hash creation should have failed\");\n\n\thandle = rte_fbk_hash_create(&invalid_params_same_name_1);\n\tRETURN_IF_ERROR_FBK(handle == NULL, \"fbk hash creation should have succeeded\");\n\n\ttmp = rte_fbk_hash_create(&invalid_params_same_name_2);\n\tRETURN_IF_ERROR_FBK(tmp == NULL, \"fbk hash creation should have succeeded\");\n\tif (tmp != handle) {\n\t\t\tprintf(\"ERROR line %d: hashes should have been the same\\n\", __LINE__);\n\t\t\trte_fbk_hash_free(handle);\n\t\t\trte_fbk_hash_free(tmp);\n\t\t\treturn -1;\n\t}\n\n\t/* we are not freeing tmp or handle here because we need a hash list\n\t * to be not empty for the next test */\n\n\t/* create a hash in non-empty list - good for coverage */\n\ttmp = rte_fbk_hash_create(&different_name);\n\tRETURN_IF_ERROR_FBK(tmp == NULL, \"fbk hash creation should have succeeded\");\n\n\t/* free both hashes */\n\trte_fbk_hash_free(handle);\n\trte_fbk_hash_free(tmp);\n\n\t/* Create empty jhash hash. */\n\thandle = rte_fbk_hash_create(¶ms_jhash);\n\tRETURN_IF_ERROR_FBK(handle == NULL, \"fbk jhash hash creation failed\");\n\n\t/* Cleanup. */\n\trte_fbk_hash_free(handle);\n\n\t/* Create empty jhash hash. */\n\thandle = rte_fbk_hash_create(¶ms_nohash);\n\tRETURN_IF_ERROR_FBK(handle == NULL, \"fbk nohash hash creation failed\");\n\n\t/* Cleanup. */\n\trte_fbk_hash_free(handle);\n\n\t/* Create empty hash. */\n\thandle = rte_fbk_hash_create(¶ms);\n\tRETURN_IF_ERROR_FBK(handle == NULL, \"fbk hash creation failed\");\n\n\tused_entries = rte_fbk_hash_get_load_factor(handle) * LOCAL_FBK_HASH_ENTRIES_MAX;\n\tRETURN_IF_ERROR_FBK((unsigned)used_entries != 0, \\\n\t\t\t\t\"load factor right after creation is not zero but it should be\");\n\t/* Add keys. */\n\tfor (i = 0; i < 5; i++) {\n\t\tstatus = rte_fbk_hash_add_key(handle, keys[i], vals[i]);\n\t\tRETURN_IF_ERROR_FBK(status != 0, \"fbk hash add failed\");\n\t}\n\n\tused_entries = rte_fbk_hash_get_load_factor(handle) * LOCAL_FBK_HASH_ENTRIES_MAX;\n\tRETURN_IF_ERROR_FBK((unsigned)used_entries != (unsigned)((((double)5)/LOCAL_FBK_HASH_ENTRIES_MAX)*LOCAL_FBK_HASH_ENTRIES_MAX), \\\n\t\t\t\t\"load factor now is not as expected\");\n\t/* Find value of added keys. */\n\tfor (i = 0; i < 5; i++) {\n\t\tstatus = rte_fbk_hash_lookup(handle, keys[i]);\n\t\tRETURN_IF_ERROR_FBK(status != vals[i],\n\t\t\t\t\"fbk hash lookup failed\");\n\t}\n\n\t/* Change value of added keys. */\n\tfor (i = 0; i < 5; i++) {\n\t\tstatus = rte_fbk_hash_add_key(handle, keys[i], vals[4 - i]);\n\t\tRETURN_IF_ERROR_FBK(status != 0, \"fbk hash update failed\");\n\t}\n\n\t/* Find new values. */\n\tfor (i = 0; i < 5; i++) {\n\t\tstatus = rte_fbk_hash_lookup(handle, keys[i]);\n\t\tRETURN_IF_ERROR_FBK(status != vals[4-i],\n\t\t\t\t\"fbk hash lookup failed\");\n\t}\n\n\t/* Delete keys individually. */\n\tfor (i = 0; i < 5; i++) {\n\t\tstatus = rte_fbk_hash_delete_key(handle, keys[i]);\n\t\tRETURN_IF_ERROR_FBK(status != 0, \"fbk hash delete failed\");\n\t}\n\n\tused_entries = rte_fbk_hash_get_load_factor(handle) * LOCAL_FBK_HASH_ENTRIES_MAX;\n\tRETURN_IF_ERROR_FBK((unsigned)used_entries != 0, \\\n\t\t\t\t\"load factor right after deletion is not zero but it should be\");\n\t/* Lookup should now fail. */\n\tfor (i = 0; i < 5; i++) {\n\t\tstatus = rte_fbk_hash_lookup(handle, keys[i]);\n\t\tRETURN_IF_ERROR_FBK(status == 0,\n\t\t\t\t\"fbk hash lookup should have failed\");\n\t}\n\n\t/* Add keys again. */\n\tfor (i = 0; i < 5; i++) {\n\t\tstatus = rte_fbk_hash_add_key(handle, keys[i], vals[i]);\n\t\tRETURN_IF_ERROR_FBK(status != 0, \"fbk hash add failed\");\n\t}\n\n\t/* Make sure they were added. */\n\tfor (i = 0; i < 5; i++) {\n\t\tstatus = rte_fbk_hash_lookup(handle, keys[i]);\n\t\tRETURN_IF_ERROR_FBK(status != vals[i],\n\t\t\t\t\"fbk hash lookup failed\");\n\t}\n\n\t/* Clear all entries. */\n\trte_fbk_hash_clear_all(handle);\n\n\t/* Lookup should fail. */\n\tfor (i = 0; i < 5; i++) {\n\t\tstatus = rte_fbk_hash_lookup(handle, keys[i]);\n\t\tRETURN_IF_ERROR_FBK(status == 0,\n\t\t\t\t\"fbk hash lookup should have failed\");\n\t}\n\n\t/* coverage */\n\n\t/* fill up the hash_table */\n\tfor (i = 0; i < RTE_FBK_HASH_ENTRIES_MAX + 1; i++)\n\t\trte_fbk_hash_add_key(handle, i, (uint16_t) i);\n\n\t/* Find non-existent key in a full hashtable */\n\tstatus = rte_fbk_hash_lookup(handle, RTE_FBK_HASH_ENTRIES_MAX + 1);\n\tRETURN_IF_ERROR_FBK(status != -ENOENT,\n\t\t\t\"fbk hash lookup succeeded\");\n\n\t/* Delete non-existent key in a full hashtable */\n\tstatus = rte_fbk_hash_delete_key(handle, RTE_FBK_HASH_ENTRIES_MAX + 1);\n\tRETURN_IF_ERROR_FBK(status != -ENOENT,\n\t\t\t\"fbk hash delete succeeded\");\n\n\t/* Delete one key from a full hashtable */\n\tstatus = rte_fbk_hash_delete_key(handle, 1);\n\tRETURN_IF_ERROR_FBK(status != 0,\n\t\t\t\"fbk hash delete failed\");\n\n\t/* Clear all entries. */\n\trte_fbk_hash_clear_all(handle);\n\n\t/* Cleanup. */\n\trte_fbk_hash_free(handle);\n\n\t/* Cover the NULL case. */\n\trte_fbk_hash_free(0);\n\n\treturn 0;\n}\n\n/*\n * Sequence of operations for find existing fbk hash table\n *\n * - create table\n * - find existing table: hit\n * - find non-existing table: miss\n *\n */\nstatic int test_fbk_hash_find_existing(void)\n{\n\tstruct rte_fbk_hash_params params = {\n\t\t\t.name = \"fbk_hash_find_existing\",\n\t\t\t.entries = LOCAL_FBK_HASH_ENTRIES_MAX,\n\t\t\t.entries_per_bucket = 4,\n\t\t\t.socket_id = 0,\n\t};\n\tstruct rte_fbk_hash_table *handle = NULL, *result = NULL;\n\n\t/* Create hash table. */\n\thandle = rte_fbk_hash_create(¶ms);\n\tRETURN_IF_ERROR_FBK(handle == NULL, \"fbk hash creation failed\");\n\n\t/* Try to find existing fbk hash table */\n\tresult = rte_fbk_hash_find_existing(\"fbk_hash_find_existing\");\n\tRETURN_IF_ERROR_FBK(result != handle, \"could not find existing fbk hash table\");\n\n\t/* Try to find non-existing fbk hash table */\n\tresult = rte_fbk_hash_find_existing(\"fbk_hash_find_non_existing\");\n\tRETURN_IF_ERROR_FBK(!(result == NULL), \"found fbk table that shouldn't exist\");\n\n\t/* Cleanup. */\n\trte_fbk_hash_free(handle);\n\n\treturn 0;\n}\n\n#define BUCKET_ENTRIES 4\n/*\n * Do tests for hash creation with bad parameters.\n */\nstatic int test_hash_creation_with_bad_parameters(void)\n{\n\tstruct rte_hash *handle;\n\tstruct rte_hash_parameters params;\n\n\thandle = rte_hash_create(NULL);\n\tif (handle != NULL) {\n\t\trte_hash_free(handle);\n\t\tprintf(\"Impossible creating hash sucessfully without any parameter\\n\");\n\t\treturn -1;\n\t}\n\n\tmemcpy(¶ms, &ut_params, sizeof(params));\n\tparams.name = \"creation_with_bad_parameters_0\";\n\tparams.entries = RTE_HASH_ENTRIES_MAX + 1;\n\thandle = rte_hash_create(¶ms);\n\tif (handle != NULL) {\n\t\trte_hash_free(handle);\n\t\tprintf(\"Impossible creating hash sucessfully with entries in parameter exceeded\\n\");\n\t\treturn -1;\n\t}\n\n\tmemcpy(¶ms, &ut_params, sizeof(params));\n\tparams.name = \"creation_with_bad_parameters_2\";\n\tparams.entries = BUCKET_ENTRIES - 1;\n\thandle = rte_hash_create(¶ms);\n\tif (handle != NULL) {\n\t\trte_hash_free(handle);\n\t\tprintf(\"Impossible creating hash sucessfully if entries less than bucket_entries in parameter\\n\");\n\t\treturn -1;\n\t}\n\n\tmemcpy(¶ms, &ut_params, sizeof(params));\n\tparams.name = \"creation_with_bad_parameters_3\";\n\tparams.key_len = 0;\n\thandle = rte_hash_create(¶ms);\n\tif (handle != NULL) {\n\t\trte_hash_free(handle);\n\t\tprintf(\"Impossible creating hash sucessfully if key_len in parameter is zero\\n\");\n\t\treturn -1;\n\t}\n\n\tmemcpy(¶ms, &ut_params, sizeof(params));\n\tparams.name = \"creation_with_bad_parameters_4\";\n\tparams.socket_id = RTE_MAX_NUMA_NODES + 1;\n\thandle = rte_hash_create(¶ms);\n\tif (handle != NULL) {\n\t\trte_hash_free(handle);\n\t\tprintf(\"Impossible creating hash sucessfully with invalid socket\\n\");\n\t\treturn -1;\n\t}\n\n\trte_hash_free(handle);\n\tprintf(\"# Test successful. No more errors expected\\n\");\n\n\treturn 0;\n}\n\n/*\n * Do tests for hash creation with parameters that look incorrect\n * but are actually valid.\n */\nstatic int\ntest_hash_creation_with_good_parameters(void)\n{\n\tstruct rte_hash *handle, *tmp;\n\tstruct rte_hash_parameters params;\n\n\t/* create with null hash function - should choose DEFAULT_HASH_FUNC */\n\tmemcpy(¶ms, &ut_params, sizeof(params));\n\tparams.name = \"same_name\";\n\tparams.hash_func = NULL;\n\thandle = rte_hash_create(¶ms);\n\tif (handle == NULL) {\n\t\tprintf(\"Creating hash with null hash_func failed\\n\");\n\t\treturn -1;\n\t}\n\n\t/* this test is trying to create a hash with the same name as previous one.\n\t * this should return a pointer to the hash we previously created.\n\t * the previous hash isn't freed exactly for the purpose of it being in\n\t * the hash list.\n\t */\n\tmemcpy(¶ms, &ut_params, sizeof(params));\n\tparams.name = \"same_name\";\n\ttmp = rte_hash_create(¶ms);\n\n\t/* check if the returned handle is actually equal to the previous hash */\n\tif (handle != tmp) {\n\t\trte_hash_free(handle);\n\t\trte_hash_free(tmp);\n\t\tprintf(\"Creating hash with existing name was successful\\n\");\n\t\treturn -1;\n\t}\n\n\t/* try creating hash when there already are hashes in the list.\n\t * the previous hash is not freed to have a non-empty hash list.\n\t * the other hash that's in the list is still pointed to by \"handle\" var.\n\t */\n\tmemcpy(¶ms, &ut_params, sizeof(params));\n\tparams.name = \"different_name\";\n\ttmp = rte_hash_create(¶ms);\n\tif (tmp == NULL) {\n\t\trte_hash_free(handle);\n\t\tprintf(\"Creating hash with valid parameters failed\\n\");\n\t\treturn -1;\n\t}\n\n\trte_hash_free(tmp);\n\trte_hash_free(handle);\n\n\treturn 0;\n}\n\n#define ITERATIONS 50\n/*\n * Test to see the average table utilization (entries added/max entries)\n * before hitting a random entry that cannot be added\n */\nstatic int test_average_table_utilization(void)\n{\n\tstruct rte_hash *handle;\n\tuint8_t simple_key[RTE_HASH_KEY_LENGTH_MAX];\n\tunsigned i, j;\n\tunsigned added_keys, average_keys_added = 0;\n\tint ret;\n\n\tprintf(\"\\n# Running test to determine average utilization\"\n\t \"\\n before adding elements begins to fail\\n\");\n\tprintf(\"Measuring performance, please wait\");\n\tfflush(stdout);\n\tut_params.entries = 1 << 20;\n\tut_params.name = \"test_average_utilization\";\n\tut_params.hash_func = rte_jhash;\n\thandle = rte_hash_create(&ut_params);\n\tRETURN_IF_ERROR(handle == NULL, \"hash creation failed\");\n\n\tfor (j = 0; j < ITERATIONS; j++) {\n\t\tret = 0;\n\t\t/* Add random entries until key cannot be added */\n\t\tfor (added_keys = 0; ret >= 0; added_keys++) {\n\t\t\tfor (i = 0; i < ut_params.key_len; i++)\n\t\t\t\tsimple_key[i] = rte_rand() % 255;\n\t\t\tret = rte_hash_add_key(handle, simple_key);\n\t\t}\n\t\tif (ret != -ENOSPC) {\n\t\t\tprintf(\"Unexpected error when adding keys\\n\");\n\t\t\trte_hash_free(handle);\n\t\t\treturn -1;\n\t\t}\n\n\t\taverage_keys_added += added_keys;\n\n\t\t/* Reset the table */\n\t\trte_hash_reset(handle);\n\n\t\t/* Print a dot to show progress on operations */\n\t\tprintf(\".\");\n\t\tfflush(stdout);\n\t}\n\n\taverage_keys_added /= ITERATIONS;\n\n\tprintf(\"\\nAverage table utilization = %.2f%% (%u/%u)\\n\",\n\t\t((double) average_keys_added / ut_params.entries * 100),\n\t\taverage_keys_added, ut_params.entries);\n\trte_hash_free(handle);\n\n\treturn 0;\n}\n\n#define NUM_ENTRIES 1024\nstatic int test_hash_iteration(void)\n{\n\tstruct rte_hash *handle;\n\tunsigned i;\n\tuint8_t keys[NUM_ENTRIES][RTE_HASH_KEY_LENGTH_MAX];\n\tconst void *next_key;\n\tvoid *next_data;\n\tvoid *data[NUM_ENTRIES];\n\tunsigned added_keys;\n\tuint32_t iter = 0;\n\tint ret = 0;\n\n\tut_params.entries = NUM_ENTRIES;\n\tut_params.name = \"test_hash_iteration\";\n\tut_params.hash_func = rte_jhash;\n\tut_params.key_len = 16;\n\thandle = rte_hash_create(&ut_params);\n\tRETURN_IF_ERROR(handle == NULL, \"hash creation failed\");\n\n\t/* Add random entries until key cannot be added */\n\tfor (added_keys = 0; added_keys < NUM_ENTRIES; added_keys++) {\n\t\tdata[added_keys] = (void *) ((uintptr_t) rte_rand());\n\t\tfor (i = 0; i < ut_params.key_len; i++)\n\t\t\tkeys[added_keys][i] = rte_rand() % 255;\n\t\tret = rte_hash_add_key_data(handle, keys[added_keys], data[added_keys]);\n\t\tif (ret < 0)\n\t\t\tbreak;\n\t}\n\n\t/* Iterate through the hash table */\n\twhile (rte_hash_iterate(handle, &next_key, &next_data, &iter) >= 0) {\n\t\t/* Search for the key in the list of keys added */\n\t\tfor (i = 0; i < NUM_ENTRIES; i++) {\n\t\t\tif (memcmp(next_key, keys[i], ut_params.key_len) == 0) {\n\t\t\t\tif (next_data != data[i]) {\n\t\t\t\t\tprintf(\"Data found in the hash table is\"\n\t\t\t\t\t \"not the data added with the key\\n\");\n\t\t\t\t\tgoto err;\n\t\t\t\t}\n\t\t\t\tadded_keys--;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (i == NUM_ENTRIES) {\n\t\t\tprintf(\"Key found in the hash table was not added\\n\");\n\t\t\tgoto err;\n\t\t}\n\t}\n\n\t/* Check if all keys have been iterated */\n\tif (added_keys != 0) {\n\t\tprintf(\"There were still %u keys to iterate\\n\", added_keys);\n\t\tgoto err;\n\t}\n\n\trte_hash_free(handle);\n\treturn 0;\n\nerr:\n\trte_hash_free(handle);\n\treturn -1;\n}\n\nstatic uint8_t key[16] = {0x00, 0x01, 0x02, 0x03,\n\t\t\t0x04, 0x05, 0x06, 0x07,\n\t\t\t0x08, 0x09, 0x0a, 0x0b,\n\t\t\t0x0c, 0x0d, 0x0e, 0x0f};\nstatic struct rte_hash_parameters hash_params_ex = {\n\t.name = NULL,\n\t.entries = 64,\n\t.key_len = 0,\n\t.hash_func = NULL,\n\t.hash_func_init_val = 0,\n\t.socket_id = 0,\n};\n\n/*\n * add/delete key with jhash2\n */\nstatic int\ntest_hash_add_delete_jhash2(void)\n{\n\tint ret = -1;\n\tstruct rte_hash *handle;\n\tint32_t pos1, pos2;\n\n\thash_params_ex.name = \"hash_test_jhash2\";\n\thash_params_ex.key_len = 4;\n\thash_params_ex.hash_func = (rte_hash_function)rte_jhash_32b;\n\n\thandle = rte_hash_create(&hash_params_ex);\n\tif (handle == NULL) {\n\t\tprintf(\"test_hash_add_delete_jhash2 fail to create hash\\n\");\n\t\tgoto fail_jhash2;\n\t}\n\tpos1 = rte_hash_add_key(handle, (void *)&key[0]);\n\tif (pos1 < 0) {\n\t\tprintf(\"test_hash_add_delete_jhash2 fail to add hash key\\n\");\n\t\tgoto fail_jhash2;\n\t}\n\n\tpos2 = rte_hash_del_key(handle, (void *)&key[0]);\n\tif (pos2 < 0 || pos1 != pos2) {\n\t\tprintf(\"test_hash_add_delete_jhash2 delete different key from being added\\n\");\n\t\tgoto fail_jhash2;\n\t}\n\tret = 0;\n\nfail_jhash2:\n\tif (handle != NULL)\n\t\trte_hash_free(handle);\n\n\treturn ret;\n}\n\n/*\n * add/delete (2) key with jhash2\n */\nstatic int\ntest_hash_add_delete_2_jhash2(void)\n{\n\tint ret = -1;\n\tstruct rte_hash *handle;\n\tint32_t pos1, pos2;\n\n\thash_params_ex.name = \"hash_test_2_jhash2\";\n\thash_params_ex.key_len = 8;\n\thash_params_ex.hash_func = (rte_hash_function)rte_jhash_32b;\n\n\thandle = rte_hash_create(&hash_params_ex);\n\tif (handle == NULL)\n\t\tgoto fail_2_jhash2;\n\n\tpos1 = rte_hash_add_key(handle, (void *)&key[0]);\n\tif (pos1 < 0)\n\t\tgoto fail_2_jhash2;\n\n\tpos2 = rte_hash_del_key(handle, (void *)&key[0]);\n\tif (pos2 < 0 || pos1 != pos2)\n\t\tgoto fail_2_jhash2;\n\n\tret = 0;\n\nfail_2_jhash2:\n\tif (handle != NULL)\n\t\trte_hash_free(handle);\n\n\treturn ret;\n}\n\nstatic uint32_t\ntest_hash_jhash_1word(const void *key, uint32_t length, uint32_t initval)\n{\n\tconst uint32_t *k = key;\n\n\tRTE_SET_USED(length);\n\n\treturn rte_jhash_1word(k[0], initval);\n}\n\nstatic uint32_t\ntest_hash_jhash_2word(const void *key, uint32_t length, uint32_t initval)\n{\n\tconst uint32_t *k = key;\n\n\tRTE_SET_USED(length);\n\n\treturn rte_jhash_2words(k[0], k[1], initval);\n}\n\nstatic uint32_t\ntest_hash_jhash_3word(const void *key, uint32_t length, uint32_t initval)\n{\n\tconst uint32_t *k = key;\n\n\tRTE_SET_USED(length);\n\n\treturn rte_jhash_3words(k[0], k[1], k[2], initval);\n}\n\n/*\n * add/delete key with jhash 1word\n */\nstatic int\ntest_hash_add_delete_jhash_1word(void)\n{\n\tint ret = -1;\n\tstruct rte_hash *handle;\n\tint32_t pos1, pos2;\n\n\thash_params_ex.name = \"hash_test_jhash_1word\";\n\thash_params_ex.key_len = 4;\n\thash_params_ex.hash_func = test_hash_jhash_1word;\n\n\thandle = rte_hash_create(&hash_params_ex);\n\tif (handle == NULL)\n\t\tgoto fail_jhash_1word;\n\n\tpos1 = rte_hash_add_key(handle, (void *)&key[0]);\n\tif (pos1 < 0)\n\t\tgoto fail_jhash_1word;\n\n\tpos2 = rte_hash_del_key(handle, (void *)&key[0]);\n\tif (pos2 < 0 || pos1 != pos2)\n\t\tgoto fail_jhash_1word;\n\n\tret = 0;\n\nfail_jhash_1word:\n\tif (handle != NULL)\n\t\trte_hash_free(handle);\n\n\treturn ret;\n}\n\n/*\n * add/delete key with jhash 2word\n */\nstatic int\ntest_hash_add_delete_jhash_2word(void)\n{\n\tint ret = -1;\n\tstruct rte_hash *handle;\n\tint32_t pos1, pos2;\n\n\thash_params_ex.name = \"hash_test_jhash_2word\";\n\thash_params_ex.key_len = 8;\n\thash_params_ex.hash_func = test_hash_jhash_2word;\n\n\thandle = rte_hash_create(&hash_params_ex);\n\tif (handle == NULL)\n\t\tgoto fail_jhash_2word;\n\n\tpos1 = rte_hash_add_key(handle, (void *)&key[0]);\n\tif (pos1 < 0)\n\t\tgoto fail_jhash_2word;\n\n\tpos2 = rte_hash_del_key(handle, (void *)&key[0]);\n\tif (pos2 < 0 || pos1 != pos2)\n\t\tgoto fail_jhash_2word;\n\n\tret = 0;\n\nfail_jhash_2word:\n\tif (handle != NULL)\n\t\trte_hash_free(handle);\n\n\treturn ret;\n}\n\n/*\n * add/delete key with jhash 3word\n */\nstatic int\ntest_hash_add_delete_jhash_3word(void)\n{\n\tint ret = -1;\n\tstruct rte_hash *handle;\n\tint32_t pos1, pos2;\n\n\thash_params_ex.name = \"hash_test_jhash_3word\";\n\thash_params_ex.key_len = 12;\n\thash_params_ex.hash_func = test_hash_jhash_3word;\n\n\thandle = rte_hash_create(&hash_params_ex);\n\tif (handle == NULL)\n\t\tgoto fail_jhash_3word;\n\n\tpos1 = rte_hash_add_key(handle, (void *)&key[0]);\n\tif (pos1 < 0)\n\t\tgoto fail_jhash_3word;\n\n\tpos2 = rte_hash_del_key(handle, (void *)&key[0]);\n\tif (pos2 < 0 || pos1 != pos2)\n\t\tgoto fail_jhash_3word;\n\n\tret = 0;\n\nfail_jhash_3word:\n\tif (handle != NULL)\n\t\trte_hash_free(handle);\n\n\treturn ret;\n}\n\n/*\n * Do all unit and performance tests.\n */\nstatic int\ntest_hash(void)\n{\n\tif (test_add_delete() < 0)\n\t\treturn -1;\n\tif (test_hash_add_delete_jhash2() < 0)\n\t\treturn -1;\n\tif (test_hash_add_delete_2_jhash2() < 0)\n\t\treturn -1;\n\tif (test_hash_add_delete_jhash_1word() < 0)\n\t\treturn -1;\n\tif (test_hash_add_delete_jhash_2word() < 0)\n\t\treturn -1;\n\tif (test_hash_add_delete_jhash_3word() < 0)\n\t\treturn -1;\n\tif (test_hash_find_existing() < 0)\n\t\treturn -1;\n\tif (test_add_update_delete() < 0)\n\t\treturn -1;\n\tif (test_five_keys() < 0)\n\t\treturn -1;\n\tif (test_full_bucket() < 0)\n\t\treturn -1;\n\n\tif (test_fbk_hash_find_existing() < 0)\n\t\treturn -1;\n\tif (fbk_hash_unit_test() < 0)\n\t\treturn -1;\n\tif (test_hash_creation_with_bad_parameters() < 0)\n\t\treturn -1;\n\tif (test_hash_creation_with_good_parameters() < 0)\n\t\treturn -1;\n\tif (test_average_table_utilization() < 0)\n\t\treturn -1;\n\tif (test_hash_iteration() < 0)\n\t\treturn -1;\n\n\trun_hash_func_tests();\n\n\tif (test_crc32_hash_alg_equiv() < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic struct test_command hash_cmd = {\n\t.command = \"hash_autotest\",\n\t.callback = test_hash,\n};\nREGISTER_TEST_COMMAND(hash_cmd);\n" }, { "path": "app/test/test_hash_functions.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n/*\n * Hash values calculated for key sizes from array \"hashtest_key_lens\"\n * and for initial values from array \"hashtest_initvals.\n * Each key will be formed by increasing each byte by 1:\n * e.g.: key size = 4, key = 0x03020100\n * key size = 8, key = 0x0706050403020100\n */\nstatic uint32_t hash_values_jhash[2][10] = {{\n\t0xe4cf1d42, 0xd4ccb93c, 0x5e84eafc, 0x21362cfe,\n\t0x2f4775ab, 0x9ff036cc, 0xeca51474, 0xbc9d6816,\n\t0x12926a31, 0x1c9fa888\n},\n{\n\t0x8270ac65, 0x05fa6668, 0x762df861, 0xda088f2f,\n\t0x59614cd4, 0x7a94f690, 0xdc1e4993, 0x30825494,\n\t0x91d0e462, 0x768087fc\n}\n};\nstatic uint32_t hash_values_crc[2][10] = {{\n\t0x91545164, 0x06040eb1, 0x9bb99201, 0xcc4c4fe4,\n\t0x14a90993, 0xf8a5dd8c, 0xc62beb31, 0x32bf340e,\n\t0x72f9d22b, 0x4a11475e\n},\n{\n\t0x98cd4c70, 0xd52c702f, 0x41fc0e1c, 0x3905f65c,\n\t0x94bff47f, 0x1bab102d, 0xd2911ed7, 0xe8faa813,\n\t0x6bea184b, 0x53028d3e\n}\n};\n\n/*******************************************************************************\n * Hash function performance test configuration section. Each performance test\n * will be performed HASHTEST_ITERATIONS times.\n *\n * The three arrays below control what tests are performed. Every combination\n * from the array entries is tested.\n */\n#define HASHTEST_ITERATIONS 1000000\n\nstatic rte_hash_function hashtest_funcs[] = {rte_jhash, rte_hash_crc};\nstatic uint32_t hashtest_initvals[] = {0, 0xdeadbeef};\nstatic uint32_t hashtest_key_lens[] = {\n\t4, 8, 16, 32, 48, 64, /* standard key sizes */\n\t9, /* IPv4 SRC + DST + protocol, unpadded */\n\t13, /* IPv4 5-tuple, unpadded */\n\t37, /* IPv6 5-tuple, unpadded */\n\t40 /* IPv6 5-tuple, padded to 8-byte boundary */\n};\n/******************************************************************************/\n\n/*\n * To help print out name of hash functions.\n */\nstatic const char *\nget_hash_name(rte_hash_function f)\n{\n\tif (f == rte_jhash)\n\t\treturn \"jhash\";\n\n\tif (f == rte_hash_crc)\n\t\treturn \"rte_hash_crc\";\n\n\treturn \"UnknownHash\";\n}\n\n/*\n * Test a hash function.\n */\nstatic void\nrun_hash_func_perf_test(uint32_t key_len, uint32_t init_val,\n\t\trte_hash_function f)\n{\n\tstatic uint8_t key[HASHTEST_ITERATIONS][RTE_HASH_KEY_LENGTH_MAX];\n\tuint64_t ticks, start, end;\n\tunsigned i, j;\n\n\tfor (i = 0; i < HASHTEST_ITERATIONS; i++) {\n\t\tfor (j = 0; j < key_len; j++)\n\t\t\tkey[i][j] = (uint8_t) rte_rand();\n\t}\n\n\tstart = rte_rdtsc();\n\tfor (i = 0; i < HASHTEST_ITERATIONS; i++)\n\t\tf(key[i], key_len, init_val);\n\tend = rte_rdtsc();\n\tticks = end - start;\n\n\tprintf(\"%-12s, %-18u, %-13u, %.02f\\n\", get_hash_name(f), (unsigned) key_len,\n\t\t\t(unsigned) init_val, (double)ticks / HASHTEST_ITERATIONS);\n}\n\n/*\n * Test all hash functions.\n */\nstatic void\nrun_hash_func_perf_tests(void)\n{\n\tunsigned i, j, k;\n\n\tprintf(\" *** Hash function performance test results ***\\n\");\n\tprintf(\" Number of iterations for each test = %d\\n\",\n\t\t\tHASHTEST_ITERATIONS);\n\tprintf(\"Hash Func. , Key Length (bytes), Initial value, Ticks/Op.\\n\");\n\n\tfor (i = 0; i < RTE_DIM(hashtest_initvals); i++) {\n\t\tfor (j = 0; j < RTE_DIM(hashtest_key_lens); j++) {\n\t\t\tfor (k = 0; k < RTE_DIM(hashtest_funcs); k++) {\n\t\t\t\trun_hash_func_perf_test(hashtest_key_lens[j],\n\t\t\t\t\t\thashtest_initvals[i],\n\t\t\t\t\t\thashtest_funcs[k]);\n\t\t\t}\n\t\t}\n\t}\n}\n\n/*\n * Verify that hash functions return what they are expected to return\n * (using precalculated values stored above)\n */\nstatic int\nverify_precalculated_hash_func_tests(void)\n{\n\tunsigned i, j;\n\tuint8_t key[64];\n\tuint32_t hash;\n\n\tfor (i = 0; i < 64; i++)\n\t\tkey[i] = (uint8_t) i;\n\n\tfor (i = 0; i < sizeof(hashtest_key_lens) / sizeof(uint32_t); i++) {\n\t\tfor (j = 0; j < sizeof(hashtest_initvals) / sizeof(uint32_t); j++) {\n\t\t\thash = rte_jhash(key, hashtest_key_lens[i],\n\t\t\t\t\thashtest_initvals[j]);\n\t\t\tif (hash != hash_values_jhash[j][i]) {\n\t\t\t\tprintf(\"jhash for %u bytes with initial value 0x%x.\"\n\t\t\t\t \"Expected 0x%x, but got 0x%x\\n\",\n\t\t\t\t hashtest_key_lens[i], hashtest_initvals[j],\n\t\t\t\t hash_values_jhash[j][i], hash);\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\thash = rte_hash_crc(key, hashtest_key_lens[i],\n\t\t\t\t\thashtest_initvals[j]);\n\t\t\tif (hash != hash_values_crc[j][i]) {\n\t\t\t\tprintf(\"CRC for %u bytes with initial value 0x%x.\"\n\t\t\t\t \"Expected 0x%x, but got 0x%x\\n\",\n\t\t\t\t hashtest_key_lens[i], hashtest_initvals[j],\n\t\t\t\t hash_values_crc[j][i], hash);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/*\n * Verify that rte_jhash and rte_jhash_32b return the same\n */\nstatic int\nverify_jhash_32bits(void)\n{\n\tunsigned i, j;\n\tuint8_t key[64];\n\tuint32_t hash, hash32;\n\n\tfor (i = 0; i < 64; i++)\n\t\tkey[i] = rand() & 0xff;\n\n\tfor (i = 0; i < sizeof(hashtest_key_lens) / sizeof(uint32_t); i++) {\n\t\tfor (j = 0; j < sizeof(hashtest_initvals) / sizeof(uint32_t); j++) {\n\t\t\t/* Key size must be multiple of 4 (32 bits) */\n\t\t\tif ((hashtest_key_lens[i] & 0x3) == 0) {\n\t\t\t\thash = rte_jhash(key, hashtest_key_lens[i],\n\t\t\t\t\t\thashtest_initvals[j]);\n\t\t\t\t/* Divide key length by 4 in rte_jhash for 32 bits */\n\t\t\t\thash32 = rte_jhash_32b((const unaligned_uint32_t *)key,\n\t\t\t\t\t\thashtest_key_lens[i] >> 2,\n\t\t\t\t\t\thashtest_initvals[j]);\n\t\t\t\tif (hash != hash32) {\n\t\t\t\t\tprintf(\"rte_jhash returns different value (0x%x)\"\n\t\t\t\t\t \"than rte_jhash_32b (0x%x)\\n\",\n\t\t\t\t\t hash, hash32);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/*\n * Verify that rte_jhash and rte_jhash_1word, rte_jhash_2words\n * and rte_jhash_3words return the same\n */\nstatic int\nverify_jhash_words(void)\n{\n\tunsigned i;\n\tuint32_t key[3];\n\tuint32_t hash, hash_words;\n\n\tfor (i = 0; i < 3; i++)\n\t\tkey[i] = rand();\n\n\t/* Test rte_jhash_1word */\n\thash = rte_jhash(key, 4, 0);\n\thash_words = rte_jhash_1word(key[0], 0);\n\tif (hash != hash_words) {\n\t\tprintf(\"rte_jhash returns different value (0x%x)\"\n\t\t \"than rte_jhash_1word (0x%x)\\n\",\n\t\t hash, hash_words);\n\t\treturn -1;\n\t}\n\t/* Test rte_jhash_2words */\n\thash = rte_jhash(key, 8, 0);\n\thash_words = rte_jhash_2words(key[0], key[1], 0);\n\tif (hash != hash_words) {\n\t\tprintf(\"rte_jhash returns different value (0x%x)\"\n\t\t \"than rte_jhash_2words (0x%x)\\n\",\n\t\t hash, hash_words);\n\t\treturn -1;\n\t}\n\t/* Test rte_jhash_3words */\n\thash = rte_jhash(key, 12, 0);\n\thash_words = rte_jhash_3words(key[0], key[1], key[2], 0);\n\tif (hash != hash_words) {\n\t\tprintf(\"rte_jhash returns different value (0x%x)\"\n\t\t \"than rte_jhash_3words (0x%x)\\n\",\n\t\t hash, hash_words);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Run all functional tests for hash functions\n */\nstatic int\nrun_hash_func_tests(void)\n{\n\tif (verify_precalculated_hash_func_tests() != 0)\n\t\treturn -1;\n\n\tif (verify_jhash_32bits() != 0)\n\t\treturn -1;\n\n\tif (verify_jhash_words() != 0)\n\t\treturn -1;\n\n\treturn 0;\n\n}\n\nstatic int\ntest_hash_functions(void)\n{\n\tif (run_hash_func_tests() != 0)\n\t\treturn -1;\n\n\trun_hash_func_perf_tests();\n\n\treturn 0;\n}\n\nstatic struct test_command hash_functions_cmd = {\n\t.command = \"hash_functions_autotest\",\n\t.callback = test_hash_functions,\n};\nREGISTER_TEST_COMMAND(hash_functions_cmd);\n" }, { "path": "app/test/test_hash_perf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#define MAX_ENTRIES (1 << 19)\n#define KEYS_TO_ADD (MAX_ENTRIES * 3 / 4) /* 75% table utilization */\n#define NUM_LOOKUPS (KEYS_TO_ADD * 5) /* Loop among keys added, several times */\n#define BUCKET_SIZE 4\n#define NUM_BUCKETS (MAX_ENTRIES / BUCKET_SIZE)\n#define MAX_KEYSIZE 64\n#define NUM_KEYSIZES 10\n#define NUM_SHUFFLES 10\n#define BURST_SIZE 16\n\nenum operations {\n\tADD = 0,\n\tLOOKUP,\n\tLOOKUP_MULTI,\n\tDELETE,\n\tNUM_OPERATIONS\n};\n\nstatic uint32_t hashtest_key_lens[] = {\n\t/* standard key sizes */\n\t4, 8, 16, 32, 48, 64,\n\t/* IPv4 SRC + DST + protocol, unpadded */\n\t9,\n\t/* IPv4 5-tuple, unpadded */\n\t13,\n\t/* IPv6 5-tuple, unpadded */\n\t37,\n\t/* IPv6 5-tuple, padded to 8-byte boundary */\n\t40\n};\n\nstruct rte_hash *h[NUM_KEYSIZES];\n\n/* Array that stores if a slot is full */\nuint8_t slot_taken[MAX_ENTRIES];\n\n/* Array to store number of cycles per operation */\nuint64_t cycles[NUM_KEYSIZES][NUM_OPERATIONS][2][2];\n\n/* Array to store all input keys */\nuint8_t keys[KEYS_TO_ADD][MAX_KEYSIZE];\n\n/* Array to store the precomputed hash for 'keys' */\nhash_sig_t signatures[KEYS_TO_ADD];\n\n/* Array to store how many busy entries have each bucket */\nuint8_t buckets[NUM_BUCKETS];\n\n/* Array to store the positions where keys are added */\nint32_t positions[KEYS_TO_ADD];\n\n/* Parameters used for hash table in unit test functions. */\nstatic struct rte_hash_parameters ut_params = {\n\t.entries = MAX_ENTRIES,\n\t.hash_func = rte_jhash,\n\t.hash_func_init_val = 0,\n};\n\nstatic int\ncreate_table(unsigned with_data, unsigned table_index)\n{\n\tchar name[RTE_HASH_NAMESIZE];\n\n\tif (with_data)\n\t\t/* Table will store 8-byte data */\n\t\tsprintf(name, \"test_hash%d_data\", hashtest_key_lens[table_index]);\n\telse\n\t\tsprintf(name, \"test_hash%d\", hashtest_key_lens[table_index]);\n\n\tut_params.name = name;\n\tut_params.key_len = hashtest_key_lens[table_index];\n\tut_params.socket_id = rte_socket_id();\n\th[table_index] = rte_hash_find_existing(name);\n\tif (h[table_index] != NULL)\n\t\t/*\n\t\t * If table was already created, free it to create it again,\n\t\t * so we force it is empty\n\t\t */\n\t\trte_hash_free(h[table_index]);\n\th[table_index] = rte_hash_create(&ut_params);\n\tif (h[table_index] == NULL) {\n\t\tprintf(\"Error creating table\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n\n}\n\n/* Shuffle the keys that have been added, so lookups will be totally random */\nstatic void\nshuffle_input_keys(unsigned table_index)\n{\n\tunsigned i;\n\tuint32_t swap_idx;\n\tuint8_t temp_key[RTE_HASH_KEY_LENGTH_MAX];\n\thash_sig_t temp_signature;\n\tint32_t temp_position;\n\n\tfor (i = KEYS_TO_ADD - 1; i > 0; i--) {\n\t\tswap_idx = rte_rand() % i;\n\n\t\tmemcpy(temp_key, keys[i], hashtest_key_lens[table_index]);\n\t\ttemp_signature = signatures[i];\n\t\ttemp_position = positions[i];\n\n\t\tmemcpy(keys[i], keys[swap_idx], hashtest_key_lens[table_index]);\n\t\tsignatures[i] = signatures[swap_idx];\n\t\tpositions[i] = positions[swap_idx];\n\n\t\tmemcpy(keys[swap_idx], temp_key, hashtest_key_lens[table_index]);\n\t\tsignatures[swap_idx] = temp_signature;\n\t\tpositions[swap_idx] = temp_position;\n\t}\n}\n\n/*\n * Looks for random keys which\n * ALL can fit in hash table (no errors)\n */\nstatic int\nget_input_keys(unsigned with_pushes, unsigned table_index)\n{\n\tunsigned i, j;\n\tunsigned bucket_idx, incr, success = 1;\n\tuint8_t k = 0;\n\tint32_t ret;\n\tconst uint32_t bucket_bitmask = NUM_BUCKETS - 1;\n\n\t/* Reset all arrays */\n\tfor (i = 0; i < MAX_ENTRIES; i++)\n\t\tslot_taken[i] = 0;\n\n\tfor (i = 0; i < NUM_BUCKETS; i++)\n\t\tbuckets[i] = 0;\n\n\tfor (j = 0; j < hashtest_key_lens[table_index]; j++)\n\t\tkeys[0][j] = 0;\n\n\t/*\n\t * Add only entries that are not duplicated and that fits in the table\n\t * (cannot store more than BUCKET_SIZE entries in a bucket).\n\t * Regardless a key has been added correctly or not (success),\n\t * the next one to try will be increased by 1.\n\t */\n\tfor (i = 0; i < KEYS_TO_ADD;) {\n\t\tincr = 0;\n\t\tif (i != 0) {\n\t\t\tkeys[i][0] = ++k;\n\t\t\t/* Overflow, need to increment the next byte */\n\t\t\tif (keys[i][0] == 0)\n\t\t\t\tincr = 1;\n\t\t\tfor (j = 1; j < hashtest_key_lens[table_index]; j++) {\n\t\t\t\t/* Do not increase next byte */\n\t\t\t\tif (incr == 0)\n\t\t\t\t\tif (success == 1)\n\t\t\t\t\t\tkeys[i][j] = keys[i - 1][j];\n\t\t\t\t\telse\n\t\t\t\t\t\tkeys[i][j] = keys[i][j];\n\t\t\t\t/* Increase next byte by one */\n\t\t\t\telse {\n\t\t\t\t\tif (success == 1)\n\t\t\t\t\t\tkeys[i][j] = keys[i-1][j] + 1;\n\t\t\t\t\telse\n\t\t\t\t\t\tkeys[i][j] = keys[i][j] + 1;\n\t\t\t\t\tif (keys[i][j] == 0)\n\t\t\t\t\t\tincr = 1;\n\t\t\t\t\telse\n\t\t\t\t\t\tincr = 0;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tsuccess = 0;\n\t\tsignatures[i] = rte_hash_hash(h[table_index], keys[i]);\n\t\tbucket_idx = signatures[i] & bucket_bitmask;\n\t\t/*\n\t\t * If we are not inserting keys in secondary location,\n\t\t * when bucket is full, do not try to insert the key\n\t\t */\n\t\tif (with_pushes == 0)\n\t\t\tif (buckets[bucket_idx] == BUCKET_SIZE)\n\t\t\t\tcontinue;\n\n\t\t/* If key can be added, leave in successful key arrays \"keys\" */\n\t\tret = rte_hash_add_key_with_hash(h[table_index], keys[i],\n\t\t\t\t\t\tsignatures[i]);\n\t\tif (ret >= 0) {\n\t\t\t/* If key is already added, ignore the entry and do not store */\n\t\t\tif (slot_taken[ret])\n\t\t\t\tcontinue;\n\t\t\telse {\n\t\t\t\t/* Store the returned position and mark slot as taken */\n\t\t\t\tslot_taken[ret] = 1;\n\t\t\t\tpositions[i] = ret;\n\t\t\t\tbuckets[bucket_idx]++;\n\t\t\t\tsuccess = 1;\n\t\t\t\ti++;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Reset the table, so we can measure the time to add all the entries */\n\trte_hash_free(h[table_index]);\n\th[table_index] = rte_hash_create(&ut_params);\n\n\treturn 0;\n}\n\nstatic int\ntimed_adds(unsigned with_hash, unsigned with_data, unsigned table_index)\n{\n\tunsigned i;\n\tconst uint64_t start_tsc = rte_rdtsc();\n\tvoid *data;\n\tint32_t ret;\n\n\tfor (i = 0; i < KEYS_TO_ADD; i++) {\n\t\tdata = (void *) ((uintptr_t) signatures[i]);\n\t\tif (with_hash && with_data) {\n\t\t\tret = rte_hash_add_key_with_hash_data(h[table_index],\n\t\t\t\t\t\t(const void *) keys[i],\n\t\t\t\t\t\tsignatures[i], data);\n\t\t\tif (ret < 0) {\n\t\t\t\tprintf(\"Failed to add key number %u\\n\", ret);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t} else if (with_hash && !with_data) {\n\t\t\tret = rte_hash_add_key_with_hash(h[table_index],\n\t\t\t\t\t\t(const void *) keys[i],\n\t\t\t\t\t\tsignatures[i]);\n\t\t\tif (ret >= 0)\n\t\t\t\tpositions[i] = ret;\n\t\t\telse {\n\t\t\t\tprintf(\"Failed to add key number %u\\n\", ret);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t} else if (!with_hash && with_data) {\n\t\t\tret = rte_hash_add_key_data(h[table_index],\n\t\t\t\t\t\t(const void *) keys[i],\n\t\t\t\t\t\tdata);\n\t\t\tif (ret < 0) {\n\t\t\t\tprintf(\"Failed to add key number %u\\n\", ret);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t} else {\n\t\t\tret = rte_hash_add_key(h[table_index], keys[i]);\n\t\t\tif (ret >= 0)\n\t\t\t\tpositions[i] = ret;\n\t\t\telse {\n\t\t\t\tprintf(\"Failed to add key number %u\\n\", ret);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\tconst uint64_t end_tsc = rte_rdtsc();\n\tconst uint64_t time_taken = end_tsc - start_tsc;\n\n\tcycles[table_index][ADD][with_hash][with_data] = time_taken/KEYS_TO_ADD;\n\n\treturn 0;\n}\n\nstatic int\ntimed_lookups(unsigned with_hash, unsigned with_data, unsigned table_index)\n{\n\tunsigned i, j;\n\tconst uint64_t start_tsc = rte_rdtsc();\n\tvoid *ret_data;\n\tvoid *expected_data;\n\tint32_t ret;\n\n\tfor (i = 0; i < NUM_LOOKUPS/KEYS_TO_ADD; i++) {\n\t\tfor (j = 0; j < KEYS_TO_ADD; j++) {\n\t\t\tif (with_hash && with_data) {\n\t\t\t\tret = rte_hash_lookup_with_hash_data(h[table_index],\n\t\t\t\t\t\t\t(const void *) keys[j],\n\t\t\t\t\t\t\tsignatures[j], &ret_data);\n\t\t\t\tif (ret < 0) {\n\t\t\t\t\tprintf(\"Key number %u was not found\\n\", j);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t\texpected_data = (void *) ((uintptr_t) signatures[j]);\n\t\t\t\tif (ret_data != expected_data) {\n\t\t\t\t\tprintf(\"Data returned for key number %u is %p,\"\n\t\t\t\t\t \" but should be %p\\n\", j, ret_data,\n\t\t\t\t\t\texpected_data);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t} else if (with_hash && !with_data) {\n\t\t\t\tret = rte_hash_lookup_with_hash(h[table_index],\n\t\t\t\t\t\t\t(const void *) keys[j],\n\t\t\t\t\t\t\tsignatures[j]);\n\t\t\t\tif (ret < 0 || ret != positions[j]) {\n\t\t\t\t\tprintf(\"Key looked up in %d, should be in %d\\n\",\n\t\t\t\t\t\tret, positions[j]);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t} else if (!with_hash && with_data) {\n\t\t\t\tret = rte_hash_lookup_data(h[table_index],\n\t\t\t\t\t\t\t(const void *) keys[j], &ret_data);\n\t\t\t\tif (ret < 0) {\n\t\t\t\t\tprintf(\"Key number %u was not found\\n\", j);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t\texpected_data = (void *) ((uintptr_t) signatures[j]);\n\t\t\t\tif (ret_data != expected_data) {\n\t\t\t\t\tprintf(\"Data returned for key number %u is %p,\"\n\t\t\t\t\t \" but should be %p\\n\", j, ret_data,\n\t\t\t\t\t\texpected_data);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tret = rte_hash_lookup(h[table_index], keys[j]);\n\t\t\t\tif (ret < 0 || ret != positions[j]) {\n\t\t\t\t\tprintf(\"Key looked up in %d, should be in %d\\n\",\n\t\t\t\t\t\tret, positions[j]);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tconst uint64_t end_tsc = rte_rdtsc();\n\tconst uint64_t time_taken = end_tsc - start_tsc;\n\n\tcycles[table_index][LOOKUP][with_hash][with_data] = time_taken/NUM_LOOKUPS;\n\n\treturn 0;\n}\n\nstatic int\ntimed_lookups_multi(unsigned with_data, unsigned table_index)\n{\n\tunsigned i, j, k;\n\tint32_t positions_burst[BURST_SIZE];\n\tconst void *keys_burst[BURST_SIZE];\n\tvoid *expected_data[BURST_SIZE];\n\tvoid *ret_data[BURST_SIZE];\n\tuint64_t hit_mask;\n\tint ret;\n\n\tconst uint64_t start_tsc = rte_rdtsc();\n\n\tfor (i = 0; i < NUM_LOOKUPS/KEYS_TO_ADD; i++) {\n\t\tfor (j = 0; j < KEYS_TO_ADD/BURST_SIZE; j++) {\n\t\t\tfor (k = 0; k < BURST_SIZE; k++)\n\t\t\t\tkeys_burst[k] = keys[j * BURST_SIZE + k];\n\t\t\tif (with_data) {\n\t\t\t\tret = rte_hash_lookup_bulk_data(h[table_index],\n\t\t\t\t\t(const void **) keys_burst,\n\t\t\t\t\tBURST_SIZE,\n\t\t\t\t\t&hit_mask,\n\t\t\t\t\tret_data);\n\t\t\t\tif (ret != BURST_SIZE) {\n\t\t\t\t\tprintf(\"Expect to find %u keys,\"\n\t\t\t\t\t \" but found %d\\n\", BURST_SIZE, ret);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t\tfor (k = 0; k < BURST_SIZE; k++) {\n\t\t\t\t\tif ((hit_mask & (1ULL << k)) == 0) {\n\t\t\t\t\t\tprintf(\"Key number %u not found\\n\",\n\t\t\t\t\t\t\tj * BURST_SIZE + k);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\texpected_data[k] = (void *) ((uintptr_t) signatures[j * BURST_SIZE + k]);\n\t\t\t\t\tif (ret_data[k] != expected_data[k]) {\n\t\t\t\t\t\tprintf(\"Data returned for key number %u is %p,\"\n\t\t\t\t\t\t \" but should be %p\\n\", j * BURST_SIZE + k,\n\t\t\t\t\t\t\tret_data[k], expected_data[k]);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\trte_hash_lookup_bulk(h[table_index],\n\t\t\t\t\t\t(const void **) keys_burst,\n\t\t\t\t\t\tBURST_SIZE,\n\t\t\t\t\t\tpositions_burst);\n\t\t\t\tfor (k = 0; k < BURST_SIZE; k++) {\n\t\t\t\t\tif (positions_burst[k] != positions[j * BURST_SIZE + k]) {\n\t\t\t\t\t\tprintf(\"Key looked up in %d, should be in %d\\n\",\n\t\t\t\t\t\t\tpositions_burst[k],\n\t\t\t\t\t\t\tpositions[j * BURST_SIZE + k]);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tconst uint64_t end_tsc = rte_rdtsc();\n\tconst uint64_t time_taken = end_tsc - start_tsc;\n\n\tcycles[table_index][LOOKUP_MULTI][0][with_data] = time_taken/NUM_LOOKUPS;\n\n\treturn 0;\n}\n\nstatic int\ntimed_deletes(unsigned with_hash, unsigned with_data, unsigned table_index)\n{\n\tunsigned i;\n\tconst uint64_t start_tsc = rte_rdtsc();\n\tint32_t ret;\n\n\tfor (i = 0; i < KEYS_TO_ADD; i++) {\n\t\t/* There are no delete functions with data, so just call two functions */\n\t\tif (with_hash)\n\t\t\tret = rte_hash_del_key_with_hash(h[table_index],\n\t\t\t\t\t\t\t(const void *) keys[i],\n\t\t\t\t\t\t\tsignatures[i]);\n\t\telse\n\t\t\tret = rte_hash_del_key(h[table_index],\n\t\t\t\t\t\t\t(const void *) keys[i]);\n\t\tif (ret >= 0)\n\t\t\tpositions[i] = ret;\n\t\telse {\n\t\t\tprintf(\"Failed to add key number %u\\n\", ret);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tconst uint64_t end_tsc = rte_rdtsc();\n\tconst uint64_t time_taken = end_tsc - start_tsc;\n\n\tcycles[table_index][DELETE][with_hash][with_data] = time_taken/KEYS_TO_ADD;\n\n\treturn 0;\n}\n\nstatic void\nfree_table(unsigned table_index)\n{\n\trte_hash_free(h[table_index]);\n}\n\nstatic void\nreset_table(unsigned table_index)\n{\n\trte_hash_reset(h[table_index]);\n}\n\nstatic int\nrun_all_tbl_perf_tests(unsigned with_pushes)\n{\n\tunsigned i, j, with_data, with_hash;\n\n\tprintf(\"Measuring performance, please wait\");\n\tfflush(stdout);\n\n\tfor (with_data = 0; with_data <= 1; with_data++) {\n\t\tfor (i = 0; i < NUM_KEYSIZES; i++) {\n\t\t\tif (create_table(with_data, i) < 0)\n\t\t\t\treturn -1;\n\n\t\t\tif (get_input_keys(with_pushes, i) < 0)\n\t\t\t\treturn -1;\n\t\t\tfor (with_hash = 0; with_hash <= 1; with_hash++) {\n\t\t\t\tif (timed_adds(with_hash, with_data, i) < 0)\n\t\t\t\t\treturn -1;\n\n\t\t\t\tfor (j = 0; j < NUM_SHUFFLES; j++)\n\t\t\t\t\tshuffle_input_keys(i);\n\n\t\t\t\tif (timed_lookups(with_hash, with_data, i) < 0)\n\t\t\t\t\treturn -1;\n\n\t\t\t\tif (timed_lookups_multi(with_data, i) < 0)\n\t\t\t\t\treturn -1;\n\n\t\t\t\tif (timed_deletes(with_hash, with_data, i) < 0)\n\t\t\t\t\treturn -1;\n\n\t\t\t\t/* Print a dot to show progress on operations */\n\t\t\t\tprintf(\".\");\n\t\t\t\tfflush(stdout);\n\n\t\t\t\treset_table(i);\n\t\t\t}\n\t\t\tfree_table(i);\n\t\t}\n\t}\n\n\tprintf(\"\\nResults (in CPU cycles/operation)\\n\");\n\tprintf(\"-----------------------------------\\n\");\n\tfor (with_data = 0; with_data <= 1; with_data++) {\n\t\tif (with_data)\n\t\t\tprintf(\"\\n Operations with 8-byte data\\n\");\n\t\telse\n\t\t\tprintf(\"\\n Operations without data\\n\");\n\t\tfor (with_hash = 0; with_hash <= 1; with_hash++) {\n\t\t\tif (with_hash)\n\t\t\t\tprintf(\"\\nWith pre-computed hash values\\n\");\n\t\t\telse\n\t\t\t\tprintf(\"\\nWithout pre-computed hash values\\n\");\n\n\t\t\tprintf(\"\\n%-18s%-18s%-18s%-18s%-18s\\n\",\n\t\t\t\"Keysize\", \"Add\", \"Lookup\", \"Lookup_bulk\", \"Delete\");\n\t\t\tfor (i = 0; i < NUM_KEYSIZES; i++) {\n\t\t\t\tprintf(\"%-18d\", hashtest_key_lens[i]);\n\t\t\t\tfor (j = 0; j < NUM_OPERATIONS; j++)\n\t\t\t\t\tprintf(\"%-18\"PRIu64, cycles[i][j][with_hash][with_data]);\n\t\t\t\tprintf(\"\\n\");\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\n/* Control operation of performance testing of fbk hash. */\n#define LOAD_FACTOR 0.667\t/* How full to make the hash table. */\n#define TEST_SIZE 1000000\t/* How many operations to time. */\n#define TEST_ITERATIONS 30\t/* How many measurements to take. */\n#define ENTRIES (1 << 15)\t/* How many entries. */\n\nstatic int\nfbk_hash_perf_test(void)\n{\n\tstruct rte_fbk_hash_params params = {\n\t\t.name = \"fbk_hash_test\",\n\t\t.entries = ENTRIES,\n\t\t.entries_per_bucket = 4,\n\t\t.socket_id = rte_socket_id(),\n\t};\n\tstruct rte_fbk_hash_table *handle = NULL;\n\tuint32_t *keys = NULL;\n\tunsigned indexes[TEST_SIZE];\n\tuint64_t lookup_time = 0;\n\tunsigned added = 0;\n\tunsigned value = 0;\n\tuint32_t key;\n\tuint16_t val;\n\tunsigned i, j;\n\n\thandle = rte_fbk_hash_create(¶ms);\n\tif (handle == NULL) {\n\t\tprintf(\"Error creating table\\n\");\n\t\treturn -1;\n\t}\n\n\tkeys = rte_zmalloc(NULL, ENTRIES * sizeof(*keys), 0);\n\tif (keys == NULL) {\n\t\tprintf(\"fbk hash: memory allocation for key store failed\\n\");\n\t\treturn -1;\n\t}\n\n\t/* Generate random keys and values. */\n\tfor (i = 0; i < ENTRIES; i++) {\n\t\tkey = (uint32_t)rte_rand();\n\t\tkey = ((uint64_t)key << 32) | (uint64_t)rte_rand();\n\t\tval = (uint16_t)rte_rand();\n\n\t\tif (rte_fbk_hash_add_key(handle, key, val) == 0) {\n\t\t\tkeys[added] = key;\n\t\t\tadded++;\n\t\t}\n\t\tif (added > (LOAD_FACTOR * ENTRIES))\n\t\t\tbreak;\n\t}\n\n\tfor (i = 0; i < TEST_ITERATIONS; i++) {\n\t\tuint64_t begin;\n\t\tuint64_t end;\n\n\t\t/* Generate random indexes into keys[] array. */\n\t\tfor (j = 0; j < TEST_SIZE; j++)\n\t\t\tindexes[j] = rte_rand() % added;\n\n\t\tbegin = rte_rdtsc();\n\t\t/* Do lookups */\n\t\tfor (j = 0; j < TEST_SIZE; j++)\n\t\t\tvalue += rte_fbk_hash_lookup(handle, keys[indexes[j]]);\n\n\t\tend = rte_rdtsc();\n\t\tlookup_time += (double)(end - begin);\n\t}\n\n\tprintf(\"\\n\\n *** FBK Hash function performance test results ***\\n\");\n\t/*\n\t * The use of the 'value' variable ensures that the hash lookup is not\n\t * being optimised out by the compiler.\n\t */\n\tif (value != 0)\n\t\tprintf(\"Number of ticks per lookup = %g\\n\",\n\t\t\t(double)lookup_time /\n\t\t\t((double)TEST_ITERATIONS * (double)TEST_SIZE));\n\n\trte_fbk_hash_free(handle);\n\n\treturn 0;\n}\n\nstatic int\ntest_hash_perf(void)\n{\n\tunsigned with_pushes;\n\n\tfor (with_pushes = 0; with_pushes <= 1; with_pushes++) {\n\t\tif (with_pushes == 0)\n\t\t\tprintf(\"\\nALL ELEMENTS IN PRIMARY LOCATION\\n\");\n\t\telse\n\t\t\tprintf(\"\\nELEMENTS IN PRIMARY OR SECONDARY LOCATION\\n\");\n\t\tif (run_all_tbl_perf_tests(with_pushes) < 0)\n\t\t\treturn -1;\n\t}\n\tif (fbk_hash_perf_test() < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic struct test_command hash_perf_cmd = {\n\t\t.command = \"hash_perf_autotest\",\n\t\t.callback = test_hash_perf,\n};\nREGISTER_TEST_COMMAND(hash_perf_cmd);\n" }, { "path": "app/test/test_hash_scaling.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n/*\n * Check condition and return an error if true. Assumes that \"handle\" is the\n * name of the hash structure pointer to be freed.\n */\n#define RETURN_IF_ERROR(cond, str, ...) do {\t\t\t\t\\\n\tif (cond) {\t\t\t\t\t\t\t\\\n\t\tprintf(\"ERROR line %d: \" str \"\\n\", __LINE__,\t\t\\\n\t\t\t\t\t\t\t##__VA_ARGS__);\t\\\n\t\tif (handle)\t\t\t\t\t\t\\\n\t\t\trte_hash_free(handle);\t\t\t\t\\\n\t\treturn -1;\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n} while (0)\n\nenum locking_mode_t {\n\tNORMAL_LOCK,\n\tLOCK_ELISION,\n\tNULL_LOCK\n};\n\nstruct {\n\tuint32_t num_iterations;\n\tstruct rte_hash *h;\n\trte_spinlock_t *lock;\n\tint locking_mode;\n} tbl_scaling_test_params;\n\nstatic rte_atomic64_t gcycles;\n\nstatic int test_hash_scaling_worker(__attribute__((unused)) void *arg)\n{\n\tuint64_t i, key;\n\tuint32_t thr_id = rte_sys_gettid();\n\tuint64_t begin, cycles = 0;\n\n\tswitch (tbl_scaling_test_params.locking_mode) {\n\n\tcase NORMAL_LOCK:\n\n\t\tfor (i = 0; i < tbl_scaling_test_params.num_iterations; i++) {\n\t\t\t/*\tdifferent threads get different keys because\n\t\t\t\twe use the thread-id in the key computation\n\t\t\t */\n\t\t\tkey = rte_hash_crc(&i, sizeof(i), thr_id);\n\t\t\tbegin = rte_rdtsc_precise();\n\t\t\trte_spinlock_lock(tbl_scaling_test_params.lock);\n\t\t\trte_hash_add_key(tbl_scaling_test_params.h, &key);\n\t\t\trte_spinlock_unlock(tbl_scaling_test_params.lock);\n\t\t\tcycles += rte_rdtsc_precise() - begin;\n\t\t}\n\t\tbreak;\n\n\tcase LOCK_ELISION:\n\n\t\tfor (i = 0; i < tbl_scaling_test_params.num_iterations; i++) {\n\t\t\tkey = rte_hash_crc(&i, sizeof(i), thr_id);\n\t\t\tbegin = rte_rdtsc_precise();\n\t\t\trte_spinlock_lock_tm(tbl_scaling_test_params.lock);\n\t\t\trte_hash_add_key(tbl_scaling_test_params.h, &key);\n\t\t\trte_spinlock_unlock_tm(tbl_scaling_test_params.lock);\n\t\t\tcycles += rte_rdtsc_precise() - begin;\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\n\t\tfor (i = 0; i < tbl_scaling_test_params.num_iterations; i++) {\n\t\t\tkey = rte_hash_crc(&i, sizeof(i), thr_id);\n\t\t\tbegin = rte_rdtsc_precise();\n\t\t\trte_hash_add_key(tbl_scaling_test_params.h, &key);\n\t\t\tcycles += rte_rdtsc_precise() - begin;\n\t\t}\n\t}\n\n\trte_atomic64_add(&gcycles, cycles);\n\n\treturn 0;\n}\n\n/*\n * Do scalability perf tests.\n */\nstatic int\ntest_hash_scaling(int locking_mode)\n{\n\tstatic unsigned calledCount = 1;\n\tuint32_t num_iterations = 1024*1024;\n\tuint64_t i, key;\n\tstruct rte_hash_parameters hash_params = {\n\t\t.entries = num_iterations*2,\n\t\t.key_len = sizeof(key),\n\t\t.hash_func = rte_hash_crc,\n\t\t.hash_func_init_val = 0,\n\t\t.socket_id = rte_socket_id(),\n\t};\n\tstruct rte_hash *handle;\n\tchar name[RTE_HASH_NAMESIZE];\n\trte_spinlock_t lock;\n\n\trte_spinlock_init(&lock);\n\n\tsnprintf(name, 32, \"test%u\", calledCount++);\n\thash_params.name = name;\n\n\thandle = rte_hash_create(&hash_params);\n\tRETURN_IF_ERROR(handle == NULL, \"hash creation failed\");\n\n\ttbl_scaling_test_params.num_iterations =\n\t\tnum_iterations/rte_lcore_count();\n\ttbl_scaling_test_params.h = handle;\n\ttbl_scaling_test_params.lock = &lock;\n\ttbl_scaling_test_params.locking_mode = locking_mode;\n\n\trte_atomic64_init(&gcycles);\n\trte_atomic64_clear(&gcycles);\n\n\t/* fill up to initial size */\n\tfor (i = 0; i < num_iterations; i++) {\n\t\tkey = rte_hash_crc(&i, sizeof(i), 0xabcdabcd);\n\t\trte_hash_add_key(tbl_scaling_test_params.h, &key);\n\t}\n\n\trte_eal_mp_remote_launch(test_hash_scaling_worker, NULL, CALL_MASTER);\n\trte_eal_mp_wait_lcore();\n\n\tunsigned long long int cycles_per_operation =\n\t\trte_atomic64_read(&gcycles)/\n\t\t(tbl_scaling_test_params.num_iterations*rte_lcore_count());\n\tconst char *lock_name;\n\n\tswitch (locking_mode) {\n\tcase NORMAL_LOCK:\n\t\tlock_name = \"normal spinlock\";\n\t\tbreak;\n\tcase LOCK_ELISION:\n\t\tlock_name = \"lock elision\";\n\t\tbreak;\n\tdefault:\n\t\tlock_name = \"null lock\";\n\t}\n\tprintf(\"--------------------------------------------------------\\n\");\n\tprintf(\"Cores: %d; %s mode -> cycles per operation: %llu\\n\",\n\t\trte_lcore_count(), lock_name, cycles_per_operation);\n\tprintf(\"--------------------------------------------------------\\n\");\n\t/* CSV output */\n\tprintf(\">>>%d,%s,%llu\\n\", rte_lcore_count(), lock_name,\n\t\tcycles_per_operation);\n\n\trte_hash_free(handle);\n\treturn 0;\n}\n\nstatic int\ntest_hash_scaling_main(void)\n{\n\tint r = 0;\n\n\tif (rte_lcore_count() == 1)\n\t\tr = test_hash_scaling(NULL_LOCK);\n\n\tif (r == 0)\n\t\tr = test_hash_scaling(NORMAL_LOCK);\n\n\tif (!rte_tm_supported()) {\n\t\tprintf(\"Hardware transactional memory (lock elision) is NOT supported\\n\");\n\t\treturn r;\n\t}\n\tprintf(\"Hardware transactional memory (lock elision) is supported\\n\");\n\n\tif (r == 0)\n\t\tr = test_hash_scaling(LOCK_ELISION);\n\n\treturn r;\n}\n\n\nstatic struct test_command hash_scaling_cmd = {\n\t.command = \"hash_scaling_autotest\",\n\t.callback = test_hash_scaling_main,\n};\nREGISTER_TEST_COMMAND(hash_scaling_cmd);\n" }, { "path": "app/test/test_interrupts.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"test.h\"\n\n#define TEST_INTERRUPT_CHECK_INTERVAL 1000 /* ms */\n\n/* predefined interrupt handle types */\nenum test_interrupt_handle_type {\n\tTEST_INTERRUPT_HANDLE_INVALID,\n\tTEST_INTERRUPT_HANDLE_VALID,\n\tTEST_INTERRUPT_HANDLE_VALID_UIO,\n\tTEST_INTERRUPT_HANDLE_VALID_ALARM,\n\tTEST_INTERRUPT_HANDLE_CASE1,\n\tTEST_INTERRUPT_HANDLE_MAX\n};\n\n/* flag of if callback is called */\nstatic volatile int flag;\nstatic struct rte_intr_handle intr_handles[TEST_INTERRUPT_HANDLE_MAX];\nstatic enum test_interrupt_handle_type test_intr_type =\n\t\t\t\tTEST_INTERRUPT_HANDLE_MAX;\n\n#ifdef RTE_EXEC_ENV_LINUXAPP\nunion intr_pipefds{\n\tstruct {\n\t\tint pipefd[2];\n\t};\n\tstruct {\n\t\tint readfd;\n\t\tint writefd;\n\t};\n};\n\nstatic union intr_pipefds pfds;\n\n/**\n * Check if the interrupt handle is valid.\n */\nstatic inline int\ntest_interrupt_handle_sanity_check(struct rte_intr_handle *intr_handle)\n{\n\tif (!intr_handle || intr_handle->fd < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * Initialization for interrupt test.\n */\nstatic int\ntest_interrupt_init(void)\n{\n\tif (pipe(pfds.pipefd) < 0)\n\t\treturn -1;\n\n\tintr_handles[TEST_INTERRUPT_HANDLE_INVALID].fd = -1;\n\tintr_handles[TEST_INTERRUPT_HANDLE_INVALID].type =\n\t\t\t\t\tRTE_INTR_HANDLE_UNKNOWN;\n\n\tintr_handles[TEST_INTERRUPT_HANDLE_VALID].fd = pfds.readfd;\n\tintr_handles[TEST_INTERRUPT_HANDLE_VALID].type =\n\t\t\t\t\tRTE_INTR_HANDLE_UNKNOWN;\n\n\tintr_handles[TEST_INTERRUPT_HANDLE_VALID_UIO].fd = pfds.readfd;\n\tintr_handles[TEST_INTERRUPT_HANDLE_VALID_UIO].type =\n\t\t\t\t\tRTE_INTR_HANDLE_UIO;\n\n\tintr_handles[TEST_INTERRUPT_HANDLE_VALID_ALARM].fd = pfds.readfd;\n\tintr_handles[TEST_INTERRUPT_HANDLE_VALID_ALARM].type =\n\t\t\t\t\tRTE_INTR_HANDLE_ALARM;\n\n\tintr_handles[TEST_INTERRUPT_HANDLE_CASE1].fd = pfds.writefd;\n\tintr_handles[TEST_INTERRUPT_HANDLE_CASE1].type = RTE_INTR_HANDLE_UIO;\n\n\treturn 0;\n}\n\n/**\n * Deinitialization for interrupt test.\n */\nstatic int\ntest_interrupt_deinit(void)\n{\n\tclose(pfds.pipefd[0]);\n\tclose(pfds.pipefd[1]);\n\n\treturn 0;\n}\n\n/**\n * Write the pipe to simulate an interrupt.\n */\nstatic int\ntest_interrupt_trigger_interrupt(void)\n{\n\tif (write(pfds.writefd, \"1\", 1) < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * Check if two interrupt handles are the same.\n */\nstatic int\ntest_interrupt_handle_compare(struct rte_intr_handle *intr_handle_l,\n\t\t\t\tstruct rte_intr_handle *intr_handle_r)\n{\n\tif (!intr_handle_l || !intr_handle_r)\n\t\treturn -1;\n\n\tif (intr_handle_l->fd != intr_handle_r->fd ||\n\t\tintr_handle_l->type != intr_handle_r->type)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n#else\n/* to be implemented for bsd later */\nstatic inline int\ntest_interrupt_handle_sanity_check(struct rte_intr_handle *intr_handle)\n{\n\tRTE_SET_USED(intr_handle);\n\n\treturn 0;\n}\n\nstatic int\ntest_interrupt_init(void)\n{\n\treturn 0;\n}\n\nstatic int\ntest_interrupt_deinit(void)\n{\n\treturn 0;\n}\n\nstatic int\ntest_interrupt_trigger_interrupt(void)\n{\n\treturn 0;\n}\n\nstatic int\ntest_interrupt_handle_compare(struct rte_intr_handle *intr_handle_l,\n\t\t\t\tstruct rte_intr_handle *intr_handle_r)\n{\n\t(void)intr_handle_l;\n\t(void)intr_handle_r;\n\n\treturn 0;\n}\n#endif /* RTE_EXEC_ENV_LINUXAPP */\n\n/**\n * Callback for the test interrupt.\n */\nstatic void\ntest_interrupt_callback(struct rte_intr_handle *intr_handle, void *arg)\n{\n\tif (test_intr_type >= TEST_INTERRUPT_HANDLE_MAX) {\n\t\tprintf(\"invalid interrupt type\\n\");\n\t\tflag = -1;\n\t\treturn;\n\t}\n\n\tif (test_interrupt_handle_sanity_check(intr_handle) < 0) {\n\t\tprintf(\"null or invalid intr_handle for %s\\n\", __func__);\n\t\tflag = -1;\n\t\treturn;\n\t}\n\n\tif (rte_intr_callback_unregister(intr_handle,\n\t\t\ttest_interrupt_callback, arg) >= 0) {\n\t\tprintf(\"%s: unexpectedly able to unregister itself\\n\",\n\t\t\t__func__);\n\t\tflag = -1;\n\t\treturn;\n\t}\n\n\tif (test_interrupt_handle_compare(intr_handle,\n\t\t\t&(intr_handles[test_intr_type])) == 0)\n\t\tflag = 1;\n}\n\n/**\n * Callback for the test interrupt.\n */\nstatic void\ntest_interrupt_callback_1(struct rte_intr_handle *intr_handle,\n\t__attribute__((unused)) void *arg)\n{\n\tif (test_interrupt_handle_sanity_check(intr_handle) < 0) {\n\t\tprintf(\"null or invalid intr_handle for %s\\n\", __func__);\n\t\tflag = -1;\n\t\treturn;\n\t}\n}\n\n/**\n * Tests for rte_intr_enable().\n */\nstatic int\ntest_interrupt_enable(void)\n{\n\tstruct rte_intr_handle test_intr_handle;\n\n\t/* check with null intr_handle */\n\tif (rte_intr_enable(NULL) == 0) {\n\t\tprintf(\"unexpectedly enable null intr_handle successfully\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check with invalid intr_handle */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_INVALID];\n\tif (rte_intr_enable(&test_intr_handle) == 0) {\n\t\tprintf(\"unexpectedly enable invalid intr_handle \"\n\t\t\t\"successfully\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check with valid intr_handle */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_VALID];\n\tif (rte_intr_enable(&test_intr_handle) == 0) {\n\t\tprintf(\"unexpectedly enable a specific intr_handle \"\n\t\t\t\"successfully\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check with specific valid intr_handle */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_VALID_ALARM];\n\tif (rte_intr_enable(&test_intr_handle) == 0) {\n\t\tprintf(\"unexpectedly enable a specific intr_handle \"\n\t\t\t\"successfully\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check with valid handler and its type */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_CASE1];\n\tif (rte_intr_enable(&test_intr_handle) < 0) {\n\t\tprintf(\"fail to enable interrupt on a simulated handler\\n\");\n\t\treturn -1;\n\t}\n\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_VALID_UIO];\n\tif (rte_intr_enable(&test_intr_handle) == 0) {\n\t\tprintf(\"unexpectedly enable a specific intr_handle \"\n\t\t\t\"successfully\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/**\n * Tests for rte_intr_disable().\n */\nstatic int\ntest_interrupt_disable(void)\n{\n\tstruct rte_intr_handle test_intr_handle;\n\n\t/* check with null intr_handle */\n\tif (rte_intr_disable(NULL) == 0) {\n\t\tprintf(\"unexpectedly disable null intr_handle \"\n\t\t\t\"successfully\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check with invalid intr_handle */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_INVALID];\n\tif (rte_intr_disable(&test_intr_handle) == 0) {\n\t\tprintf(\"unexpectedly disable invalid intr_handle \"\n\t\t\t\"successfully\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check with valid intr_handle */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_VALID];\n\tif (rte_intr_disable(&test_intr_handle) == 0) {\n\t\tprintf(\"unexpectedly disable a specific intr_handle \"\n\t\t\t\"successfully\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check with specific valid intr_handle */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_VALID_ALARM];\n\tif (rte_intr_disable(&test_intr_handle) == 0) {\n\t\tprintf(\"unexpectedly disable a specific intr_handle \"\n\t\t\t\"successfully\\n\");\n\t\treturn -1;\n\t}\n\n\t/* check with valid handler and its type */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_CASE1];\n\tif (rte_intr_disable(&test_intr_handle) < 0) {\n\t\tprintf(\"fail to disable interrupt on a simulated handler\\n\");\n\t\treturn -1;\n\t}\n\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_VALID_UIO];\n\tif (rte_intr_disable(&test_intr_handle) == 0) {\n\t\tprintf(\"unexpectedly disable a specific intr_handle \"\n\t\t\t\"successfully\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/**\n * Check the full path of a specified type of interrupt simulated.\n */\nstatic int\ntest_interrupt_full_path_check(enum test_interrupt_handle_type intr_type)\n{\n\tint count;\n\tstruct rte_intr_handle test_intr_handle;\n\n\tflag = 0;\n\ttest_intr_handle = intr_handles[intr_type];\n\ttest_intr_type = intr_type;\n\tif (rte_intr_callback_register(&test_intr_handle,\n\t\t\ttest_interrupt_callback, NULL) < 0) {\n\t\tprintf(\"fail to register callback\\n\");\n\t\treturn -1;\n\t}\n\n\tif (test_interrupt_trigger_interrupt() < 0)\n\t\treturn -1;\n\n\t/* check flag in 3 seconds */\n\tfor (count = 0; flag == 0 && count < 3; count++)\n\t\trte_delay_ms(TEST_INTERRUPT_CHECK_INTERVAL);\n\n\trte_delay_ms(TEST_INTERRUPT_CHECK_INTERVAL);\n\tif (rte_intr_callback_unregister(&test_intr_handle,\n\t\t\ttest_interrupt_callback, NULL) < 0)\n\t\treturn -1;\n\n\tif (flag == 0) {\n\t\tprintf(\"callback has not been called\\n\");\n\t\treturn -1;\n\t} else if (flag < 0) {\n\t\tprintf(\"it has internal error in callback\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/**\n * Main function of testing interrupt.\n */\nstatic int\ntest_interrupt(void)\n{\n\tint ret = -1;\n\tstruct rte_intr_handle test_intr_handle;\n\n\tif (test_interrupt_init() < 0) {\n\t\tprintf(\"fail to initialize for testing interrupt\\n\");\n\t\treturn -1;\n\t}\n\n\tprintf(\"Check unknown valid interrupt full path\\n\");\n\tif (test_interrupt_full_path_check(TEST_INTERRUPT_HANDLE_VALID) < 0) {\n\t\tprintf(\"failure occured during checking unknown valid \"\n\t\t\t\t\t\t\"interrupt full path\\n\");\n\t\tgoto out;\n\t}\n\n\tprintf(\"Check valid UIO interrupt full path\\n\");\n\tif (test_interrupt_full_path_check(TEST_INTERRUPT_HANDLE_VALID_UIO)\n\t\t\t\t\t\t\t\t\t< 0) {\n\t\tprintf(\"failure occured during checking valid UIO interrupt \"\n\t\t\t\t\t\t\t\t\"full path\\n\");\n\t\tgoto out;\n\t}\n\n\tprintf(\"Check valid alarm interrupt full path\\n\");\n\tif (test_interrupt_full_path_check(TEST_INTERRUPT_HANDLE_VALID_ALARM)\n\t\t\t\t\t\t\t\t\t< 0) {\n\t\tprintf(\"failure occured during checking valid alarm \"\n\t\t\t\t\t\t\"interrupt full path\\n\");\n\t\tgoto out;\n\t}\n\n\tprintf(\"start register/unregister test\\n\");\n\t/* check if it will fail to register cb with intr_handle = NULL */\n\tif (rte_intr_callback_register(NULL, test_interrupt_callback,\n\t\t\t\t\t\t\tNULL) == 0) {\n\t\tprintf(\"unexpectedly register successfully with null \"\n\t\t\t\"intr_handle\\n\");\n\t\tgoto out;\n\t}\n\n\t/* check if it will fail to register cb with invalid intr_handle */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_INVALID];\n\tif (rte_intr_callback_register(&test_intr_handle,\n\t\t\ttest_interrupt_callback, NULL) == 0) {\n\t\tprintf(\"unexpectedly register successfully with invalid \"\n\t\t\t\"intr_handle\\n\");\n\t\tgoto out;\n\t}\n\n\t/* check if it will fail to register without callback */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_VALID];\n\tif (rte_intr_callback_register(&test_intr_handle, NULL, NULL) == 0) {\n\t\tprintf(\"unexpectedly register successfully with \"\n\t\t\t\"null callback\\n\");\n\t\tgoto out;\n\t}\n\n\t/* check if it will fail to unregister cb with intr_handle = NULL */\n\tif (rte_intr_callback_unregister(NULL,\n\t\t\ttest_interrupt_callback, NULL) > 0) {\n\t\tprintf(\"unexpectedly unregister successfully with \"\n\t\t\t\"null intr_handle\\n\");\n\t\tgoto out;\n\t}\n\n\t/* check if it will fail to unregister cb with invalid intr_handle */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_INVALID];\n\tif (rte_intr_callback_unregister(&test_intr_handle,\n\t\t\ttest_interrupt_callback, NULL) > 0) {\n\t\tprintf(\"unexpectedly unregister successfully with \"\n\t\t\t\"invalid intr_handle\\n\");\n\t\tgoto out;\n\t}\n\n\t/* check if it is ok to register the same intr_handle twice */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_VALID];\n\tif (rte_intr_callback_register(&test_intr_handle,\n\t\t\ttest_interrupt_callback, NULL) < 0) {\n\t\tprintf(\"it fails to register test_interrupt_callback\\n\");\n\t\tgoto out;\n\t}\n\tif (rte_intr_callback_register(&test_intr_handle,\n\t\t\ttest_interrupt_callback_1, NULL) < 0) {\n\t\tprintf(\"it fails to register test_interrupt_callback_1\\n\");\n\t\tgoto out;\n\t}\n\t/* check if it will fail to unregister with invalid parameter */\n\tif (rte_intr_callback_unregister(&test_intr_handle,\n\t\t\ttest_interrupt_callback, (void *)0xff) != 0) {\n\t\tprintf(\"unexpectedly unregisters successfully with \"\n\t\t\t\t\t\t\t\"invalid arg\\n\");\n\t\tgoto out;\n\t}\n\tif (rte_intr_callback_unregister(&test_intr_handle,\n\t\t\ttest_interrupt_callback, NULL) <= 0) {\n\t\tprintf(\"it fails to unregister test_interrupt_callback\\n\");\n\t\tgoto out;\n\t}\n\tif (rte_intr_callback_unregister(&test_intr_handle,\n\t\t\ttest_interrupt_callback_1, (void *)-1) <= 0) {\n\t\tprintf(\"it fails to unregister test_interrupt_callback_1 \"\n\t\t\t\"for all\\n\");\n\t\tgoto out;\n\t}\n\trte_delay_ms(TEST_INTERRUPT_CHECK_INTERVAL);\n\n\tprintf(\"start interrupt enable/disable test\\n\");\n\t/* check interrupt enable/disable functions */\n\tif (test_interrupt_enable() < 0) {\n\t\tprintf(\"fail to check interrupt enabling\\n\");\n\t\tgoto out;\n\t}\n\trte_delay_ms(TEST_INTERRUPT_CHECK_INTERVAL);\n\n\tif (test_interrupt_disable() < 0) {\n\t\tprintf(\"fail to check interrupt disabling\\n\");\n\t\tgoto out;\n\t}\n\trte_delay_ms(TEST_INTERRUPT_CHECK_INTERVAL);\n\n\tret = 0;\n\nout:\n\tprintf(\"Clearing for interrupt tests\\n\");\n\t/* clear registered callbacks */\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_VALID];\n\trte_intr_callback_unregister(&test_intr_handle,\n\t\t\ttest_interrupt_callback, (void *)-1);\n\trte_intr_callback_unregister(&test_intr_handle,\n\t\t\ttest_interrupt_callback_1, (void *)-1);\n\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_VALID_UIO];\n\trte_intr_callback_unregister(&test_intr_handle,\n\t\t\ttest_interrupt_callback, (void *)-1);\n\trte_intr_callback_unregister(&test_intr_handle,\n\t\t\ttest_interrupt_callback_1, (void *)-1);\n\n\ttest_intr_handle = intr_handles[TEST_INTERRUPT_HANDLE_VALID_ALARM];\n\trte_intr_callback_unregister(&test_intr_handle,\n\t\t\ttest_interrupt_callback, (void *)-1);\n\trte_intr_callback_unregister(&test_intr_handle,\n\t\t\ttest_interrupt_callback_1, (void *)-1);\n\n\trte_delay_ms(2 * TEST_INTERRUPT_CHECK_INTERVAL);\n\t/* deinit */\n\ttest_interrupt_deinit();\n\n\treturn ret;\n}\n\nstatic struct test_command interrupt_cmd = {\n\t.command = \"interrupt_autotest\",\n\t.callback = test_interrupt,\n};\nREGISTER_TEST_COMMAND(interrupt_cmd);\n" }, { "path": "app/test/test_ivshmem.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"test.h\"\n\n#include \n#include \n#include \n#include \"process.h\"\n\n#define DUPLICATE_METADATA \"duplicate\"\n#define METADATA_NAME \"metadata\"\n#define NONEXISTENT_METADATA \"nonexistent\"\n#define FIRST_TEST 'a'\n\n#define launch_proc(ARGV) process_dup(ARGV, \\\n\t\tsizeof(ARGV)/(sizeof(ARGV[0])), \"test_ivshmem\")\n\n#define ASSERT(cond,msg) do {\t\t\t\t\t\t\\\n\t\tif (!(cond)) {\t\t\t\t\t\t\t\t\\\n\t\t\tprintf(\"**** TEST %s() failed: %s\\n\",\t\\\n\t\t\t\t__func__, msg);\t\t\t\t\t\t\\\n\t\t\treturn -1;\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\\\n} while(0)\n\nstatic char*\nget_current_prefix(char * prefix, int size)\n{\n\tchar path[PATH_MAX] = {0};\n\tchar buf[PATH_MAX] = {0};\n\n\t/* get file for config (fd is always 3) */\n\tsnprintf(path, sizeof(path), \"/proc/self/fd/%d\", 3);\n\n\t/* return NULL on error */\n\tif (readlink(path, buf, sizeof(buf)) == -1)\n\t\treturn NULL;\n\n\t/* get the basename */\n\tsnprintf(buf, sizeof(buf), \"%s\", basename(buf));\n\n\t/* copy string all the way from second char up to start of _config */\n\tsnprintf(prefix, size, \"%.*s\",\n\t\t\t(int)(strnlen(buf, sizeof(buf)) - sizeof(\"_config\")),\n\t\t\t&buf[1]);\n\n\treturn prefix;\n}\n\nstatic struct rte_ivshmem_metadata*\nmmap_metadata(const char *name)\n{\n\tint fd;\n\tchar pathname[PATH_MAX];\n\tstruct rte_ivshmem_metadata *metadata;\n\n\tsnprintf(pathname, sizeof(pathname),\n\t\t\t\"/var/run/.dpdk_ivshmem_metadata_%s\", name);\n\n\tfd = open(pathname, O_RDWR, 0660);\n\tif (fd < 0)\n\t\treturn NULL;\n\n\tmetadata = (struct rte_ivshmem_metadata*) mmap(NULL,\n\t\t\tsizeof(struct rte_ivshmem_metadata), PROT_READ | PROT_WRITE,\n\t\t\tMAP_SHARED, fd, 0);\n\n\tif (metadata == MAP_FAILED)\n\t\treturn NULL;\n\n\tclose(fd);\n\n\treturn metadata;\n}\n\nstatic int\ncreate_duplicate(void)\n{\n\t/* create a metadata that another process will then try to overwrite */\n\tASSERT (rte_ivshmem_metadata_create(DUPLICATE_METADATA) == 0,\n\t\t\t\"Creating metadata failed\");\n\treturn 0;\n}\n\nstatic int\ntest_ivshmem_create_lots_of_memzones(void)\n{\n\tint i;\n\tchar name[IVSHMEM_NAME_LEN];\n\tconst struct rte_memzone *mz;\n\n\tASSERT(rte_ivshmem_metadata_create(METADATA_NAME) == 0,\n\t\t\t\"Failed to create metadata\");\n\n\tfor (i = 0; i < RTE_LIBRTE_IVSHMEM_MAX_ENTRIES; i++) {\n\t\tsnprintf(name, sizeof(name), \"mz_%i\", i);\n\n\t\tmz = rte_memzone_reserve(name, RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY, 0);\n\t\tASSERT(mz != NULL, \"Failed to reserve memzone\");\n\n\t\tASSERT(rte_ivshmem_metadata_add_memzone(mz, METADATA_NAME) == 0,\n\t\t\t\t\"Failed to add memzone\");\n\t}\n\tmz = rte_memzone_reserve(\"one too many\", RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY, 0);\n\tASSERT(mz != NULL, \"Failed to reserve memzone\");\n\n\tASSERT(rte_ivshmem_metadata_add_memzone(mz, METADATA_NAME) < 0,\n\t\t\"Metadata should have been full\");\n\n\treturn 0;\n}\n\nstatic int\ntest_ivshmem_create_duplicate_memzone(void)\n{\n\tconst struct rte_memzone *mz;\n\n\tASSERT(rte_ivshmem_metadata_create(METADATA_NAME) == 0,\n\t\t\t\"Failed to create metadata\");\n\n\tmz = rte_memzone_reserve(\"mz\", RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY, 0);\n\tASSERT(mz != NULL, \"Failed to reserve memzone\");\n\n\tASSERT(rte_ivshmem_metadata_add_memzone(mz, METADATA_NAME) == 0,\n\t\t\t\"Failed to add memzone\");\n\n\tASSERT(rte_ivshmem_metadata_add_memzone(mz, METADATA_NAME) < 0,\n\t\t\t\"Added the same memzone twice\");\n\n\treturn 0;\n}\n\nstatic int\ntest_ivshmem_api_test(void)\n{\n\tconst struct rte_memzone * mz;\n\tstruct rte_mempool * mp;\n\tstruct rte_ring * r;\n\tchar buf[BUFSIZ];\n\n\tmemset(buf, 0, sizeof(buf));\n\n\tr = rte_ring_create(\"ring\", 1, SOCKET_ID_ANY, 0);\n\tmp = rte_mempool_create(\"mempool\", 1, 1, 1, 1, NULL, NULL, NULL, NULL,\n\t\t\tSOCKET_ID_ANY, 0);\n\tmz = rte_memzone_reserve(\"memzone\", 64, SOCKET_ID_ANY, 0);\n\n\tASSERT(r != NULL, \"Failed to create ring\");\n\tASSERT(mp != NULL, \"Failed to create mempool\");\n\tASSERT(mz != NULL, \"Failed to reserve memzone\");\n\n\t/* try to create NULL metadata */\n\tASSERT(rte_ivshmem_metadata_create(NULL) < 0,\n\t\t\t\"Created metadata with NULL name\");\n\n\t/* create valid metadata to do tests on */\n\tASSERT(rte_ivshmem_metadata_create(METADATA_NAME) == 0,\n\t\t\t\"Failed to create metadata\");\n\n\t/* test adding memzone */\n\tASSERT(rte_ivshmem_metadata_add_memzone(NULL, NULL) < 0,\n\t\t\t\"Added NULL memzone to NULL metadata\");\n\tASSERT(rte_ivshmem_metadata_add_memzone(NULL, METADATA_NAME) < 0,\n\t\t\t\"Added NULL memzone\");\n\tASSERT(rte_ivshmem_metadata_add_memzone(mz, NULL) < 0,\n\t\t\t\"Added memzone to NULL metadata\");\n\tASSERT(rte_ivshmem_metadata_add_memzone(mz, NONEXISTENT_METADATA) < 0,\n\t\t\t\"Added memzone to nonexistent metadata\");\n\n\t/* test adding ring */\n\tASSERT(rte_ivshmem_metadata_add_ring(NULL, NULL) < 0,\n\t\t\t\"Added NULL ring to NULL metadata\");\n\tASSERT(rte_ivshmem_metadata_add_ring(NULL, METADATA_NAME) < 0,\n\t\t\t\"Added NULL ring\");\n\tASSERT(rte_ivshmem_metadata_add_ring(r, NULL) < 0,\n\t\t\t\"Added ring to NULL metadata\");\n\tASSERT(rte_ivshmem_metadata_add_ring(r, NONEXISTENT_METADATA) < 0,\n\t\t\t\"Added ring to nonexistent metadata\");\n\n\t/* test adding mempool */\n\tASSERT(rte_ivshmem_metadata_add_mempool(NULL, NULL) < 0,\n\t\t\t\"Added NULL mempool to NULL metadata\");\n\tASSERT(rte_ivshmem_metadata_add_mempool(NULL, METADATA_NAME) < 0,\n\t\t\t\"Added NULL mempool\");\n\tASSERT(rte_ivshmem_metadata_add_mempool(mp, NULL) < 0,\n\t\t\t\"Added mempool to NULL metadata\");\n\tASSERT(rte_ivshmem_metadata_add_mempool(mp, NONEXISTENT_METADATA) < 0,\n\t\t\t\"Added mempool to nonexistent metadata\");\n\n\t/* test creating command line */\n\tASSERT(rte_ivshmem_metadata_cmdline_generate(NULL, sizeof(buf), METADATA_NAME) < 0,\n\t\t\t\"Written command line into NULL buffer\");\n\tASSERT(strnlen(buf, sizeof(buf)) == 0, \"Buffer is not empty\");\n\n\tASSERT(rte_ivshmem_metadata_cmdline_generate(buf, 0, METADATA_NAME) < 0,\n\t\t\t\"Written command line into small buffer\");\n\tASSERT(strnlen(buf, sizeof(buf)) == 0, \"Buffer is not empty\");\n\n\tASSERT(rte_ivshmem_metadata_cmdline_generate(buf, sizeof(buf), NULL) < 0,\n\t\t\t\"Written command line for NULL metadata\");\n\tASSERT(strnlen(buf, sizeof(buf)) == 0, \"Buffer is not empty\");\n\n\tASSERT(rte_ivshmem_metadata_cmdline_generate(buf, sizeof(buf),\n\t\t\tNONEXISTENT_METADATA) < 0,\n\t\t\t\"Writen command line for nonexistent metadata\");\n\tASSERT(strnlen(buf, sizeof(buf)) == 0, \"Buffer is not empty\");\n\n\t/* add stuff to config */\n\tASSERT(rte_ivshmem_metadata_add_memzone(mz, METADATA_NAME) == 0,\n\t\t\t\"Failed to add memzone to valid config\");\n\tASSERT(rte_ivshmem_metadata_add_ring(r, METADATA_NAME) == 0,\n\t\t\t\"Failed to add ring to valid config\");\n\tASSERT(rte_ivshmem_metadata_add_mempool(mp, METADATA_NAME) == 0,\n\t\t\t\"Failed to add mempool to valid config\");\n\n\t/* create config */\n\tASSERT(rte_ivshmem_metadata_cmdline_generate(buf, sizeof(buf),\n\t\t\tMETADATA_NAME) == 0, \"Failed to write command-line\");\n\n\t/* check if something was written */\n\tASSERT(strnlen(buf, sizeof(buf)) != 0, \"Buffer is empty\");\n\n\t/* make sure we don't segfault */\n\trte_ivshmem_metadata_dump(stdout, NULL);\n\n\t/* dump our metadata */\n\trte_ivshmem_metadata_dump(stdout, METADATA_NAME);\n\n\treturn 0;\n}\n\nstatic int\ntest_ivshmem_create_duplicate_metadata(void)\n{\n\tASSERT(rte_ivshmem_metadata_create(DUPLICATE_METADATA) < 0,\n\t\t\t\"Creating duplicate metadata should have failed\");\n\n\treturn 0;\n}\n\nstatic int\ntest_ivshmem_create_metadata_config(void)\n{\n\tstruct rte_ivshmem_metadata *metadata;\n\n\trte_ivshmem_metadata_create(METADATA_NAME);\n\n\tmetadata = mmap_metadata(METADATA_NAME);\n\n\tASSERT(metadata != MAP_FAILED, \"Metadata mmaping failed\");\n\n\tASSERT(metadata->magic_number == IVSHMEM_MAGIC,\n\t\t\t\"Magic number is not that magic\");\n\n\tASSERT(strncmp(metadata->name, METADATA_NAME, sizeof(metadata->name)) == 0,\n\t\t\t\"Name has not been set up\");\n\n\tASSERT(metadata->entry[0].offset == 0, \"Offest is not initialized\");\n\tASSERT(metadata->entry[0].mz.addr == 0, \"mz.addr is not initialized\");\n\tASSERT(metadata->entry[0].mz.len == 0, \"mz.len is not initialized\");\n\n\treturn 0;\n}\n\nstatic int\ntest_ivshmem_create_multiple_metadata_configs(void)\n{\n\tint i;\n\tchar name[IVSHMEM_NAME_LEN];\n\tstruct rte_ivshmem_metadata *metadata;\n\n\tfor (i = 0; i < RTE_LIBRTE_IVSHMEM_MAX_METADATA_FILES / 2; i++) {\n\t\tsnprintf(name, sizeof(name), \"test_%d\", i);\n\t\trte_ivshmem_metadata_create(name);\n\t\tmetadata = mmap_metadata(name);\n\n\t\tASSERT(metadata->magic_number == IVSHMEM_MAGIC,\n\t\t\t\t\"Magic number is not that magic\");\n\n\t\tASSERT(strncmp(metadata->name, name, sizeof(metadata->name)) == 0,\n\t\t\t\t\"Name has not been set up\");\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntest_ivshmem_create_too_many_metadata_configs(void)\n{\n\tint i;\n\tchar name[IVSHMEM_NAME_LEN];\n\n\tfor (i = 0; i < RTE_LIBRTE_IVSHMEM_MAX_METADATA_FILES; i++) {\n\t\tsnprintf(name, sizeof(name), \"test_%d\", i);\n\t\tASSERT(rte_ivshmem_metadata_create(name) == 0,\n\t\t\t\t\"Create config file failed\");\n\t}\n\n\tASSERT(rte_ivshmem_metadata_create(name) < 0,\n\t\t\t\"Create config file didn't fail\");\n\n\treturn 0;\n}\n\nenum rte_ivshmem_tests {\n\t_test_ivshmem_api_test = 0,\n\t_test_ivshmem_create_metadata_config,\n\t_test_ivshmem_create_multiple_metadata_configs,\n\t_test_ivshmem_create_too_many_metadata_configs,\n\t_test_ivshmem_create_duplicate_metadata,\n\t_test_ivshmem_create_lots_of_memzones,\n\t_test_ivshmem_create_duplicate_memzone,\n\t_last_test,\n};\n\n#define RTE_IVSHMEM_TEST_ID \"RTE_IVSHMEM_TEST_ID\"\n\nstatic int\nlaunch_all_tests_on_secondary_processes(void)\n{\n\tint ret = 0;\n\tchar id;\n\tchar testid;\n\tchar tmp[PATH_MAX] = {0};\n\tchar prefix[PATH_MAX] = {0};\n\n\tget_current_prefix(tmp, sizeof(tmp));\n\n\tsnprintf(prefix, sizeof(prefix), \"--file-prefix=%s\", tmp);\n\n\tconst char *argv[] = { prgname, \"-c\", \"1\", \"-n\", \"3\",\n\t\t\t\"--proc-type=secondary\", prefix };\n\n\tfor (id = 0; id < _last_test; id++) {\n\t\ttestid = (char)(FIRST_TEST + id);\n\t\tsetenv(RTE_IVSHMEM_TEST_ID, &testid, 1);\n\t\tif (launch_proc(argv) != 0)\n\t\t\treturn -1;\n\t}\n\treturn ret;\n}\n\nint\ntest_ivshmem(void)\n{\n\tint testid;\n\n\t/* We want to have a clean execution for every test without exposing\n\t * private global data structures in rte_ivshmem so we launch each test\n\t * on a different secondary process. */\n\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n\n\t\t/* first, create metadata */\n\t\tASSERT(create_duplicate() == 0, \"Creating metadata failed\");\n\n\t\treturn launch_all_tests_on_secondary_processes();\n\t}\n\n\ttestid = *(getenv(RTE_IVSHMEM_TEST_ID)) - FIRST_TEST;\n\n\tprintf(\"Secondary process running test %d \\n\", testid);\n\n\tswitch (testid) {\n\tcase _test_ivshmem_api_test:\n\t\treturn test_ivshmem_api_test();\n\n\tcase _test_ivshmem_create_metadata_config:\n\t\treturn test_ivshmem_create_metadata_config();\n\n\tcase _test_ivshmem_create_multiple_metadata_configs:\n\t\treturn test_ivshmem_create_multiple_metadata_configs();\n\n\tcase _test_ivshmem_create_too_many_metadata_configs:\n\t\treturn test_ivshmem_create_too_many_metadata_configs();\n\n\tcase _test_ivshmem_create_duplicate_metadata:\n\t\treturn test_ivshmem_create_duplicate_metadata();\n\n\tcase _test_ivshmem_create_lots_of_memzones:\n\t\treturn test_ivshmem_create_lots_of_memzones();\n\n\tcase _test_ivshmem_create_duplicate_memzone:\n\t\treturn test_ivshmem_create_duplicate_memzone();\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn -1;\n}\n\nstatic struct test_command ivshmem_cmd = {\n\t.command = \"ivshmem_autotest\",\n\t.callback = test_ivshmem,\n};\nREGISTER_TEST_COMMAND(ivshmem_cmd);\n" }, { "path": "app/test/test_kni.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#include \n#include \n#include \n#include \n#include \n\n#define NB_MBUF 8192\n#define MAX_PACKET_SZ 2048\n#define MBUF_DATA_SZ (MAX_PACKET_SZ + RTE_PKTMBUF_HEADROOM)\n#define PKT_BURST_SZ 32\n#define MEMPOOL_CACHE_SZ PKT_BURST_SZ\n#define SOCKET 0\n#define NB_RXD 128\n#define NB_TXD 512\n#define KNI_TIMEOUT_MS 5000 /* ms */\n\n#define IFCONFIG \"/sbin/ifconfig \"\n#define TEST_KNI_PORT \"test_kni_port\"\n#define KNI_TEST_MAX_PORTS 4\n/* The threshold number of mbufs to be transmitted or received. */\n#define KNI_NUM_MBUF_THRESHOLD 100\nstatic int kni_pkt_mtu = 0;\n\nstruct test_kni_stats {\n\tvolatile uint64_t ingress;\n\tvolatile uint64_t egress;\n};\n\nstatic const struct rte_eth_rxconf rx_conf = {\n\t.rx_thresh = {\n\t\t.pthresh = 8,\n\t\t.hthresh = 8,\n\t\t.wthresh = 4,\n\t},\n\t.rx_free_thresh = 0,\n};\n\nstatic const struct rte_eth_txconf tx_conf = {\n\t.tx_thresh = {\n\t\t.pthresh = 36,\n\t\t.hthresh = 0,\n\t\t.wthresh = 0,\n\t},\n\t.tx_free_thresh = 0,\n\t.tx_rs_thresh = 0,\n};\n\nstatic const struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.header_split = 0,\n\t\t.hw_ip_checksum = 0,\n\t\t.hw_vlan_filter = 0,\n\t\t.jumbo_frame = 0,\n\t\t.hw_strip_crc = 0,\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_DCB_NONE,\n\t},\n};\n\nstatic struct rte_kni_ops kni_ops = {\n\t.change_mtu = NULL,\n\t.config_network_if = NULL,\n};\n\nstatic unsigned lcore_master, lcore_ingress, lcore_egress;\nstatic struct rte_kni *test_kni_ctx;\nstatic struct test_kni_stats stats;\n\nstatic volatile uint32_t test_kni_processing_flag;\n\nstatic struct rte_mempool *\ntest_kni_create_mempool(void)\n{\n\tstruct rte_mempool * mp;\n\n\tmp = rte_mempool_lookup(\"kni_mempool\");\n\tif (!mp)\n\t\tmp = rte_pktmbuf_pool_create(\"kni_mempool\",\n\t\t\t\tNB_MBUF,\n\t\t\t\tMEMPOOL_CACHE_SZ, 0, MBUF_DATA_SZ,\n\t\t\t\tSOCKET);\n\n\treturn mp;\n}\n\nstatic struct rte_mempool *\ntest_kni_lookup_mempool(void)\n{\n\treturn rte_mempool_lookup(\"kni_mempool\");\n}\n/* Callback for request of changing MTU */\nstatic int\nkni_change_mtu(uint8_t port_id, unsigned new_mtu)\n{\n\tprintf(\"Change MTU of port %d to %u\\n\", port_id, new_mtu);\n\tkni_pkt_mtu = new_mtu;\n\tprintf(\"Change MTU of port %d to %i successfully.\\n\",\n\t\t\t\t\t port_id, kni_pkt_mtu);\n\treturn 0;\n}\n/**\n * This loop fully tests the basic functions of KNI. e.g. transmitting,\n * receiving to, from kernel space, and kernel requests.\n *\n * This is the loop to transmit/receive mbufs to/from kernel interface with\n * supported by KNI kernel module. The ingress lcore will allocate mbufs and\n * transmit them to kernel space; while the egress lcore will receive the mbufs\n * from kernel space and free them.\n * On the master lcore, several commands will be run to check handling the\n * kernel requests. And it will finally set the flag to exit the KNI\n * transmitting/receiving to/from the kernel space.\n *\n * Note: To support this testing, the KNI kernel module needs to be insmodded\n * in one of its loopback modes.\n */\nstatic int\ntest_kni_loop(__rte_unused void *arg)\n{\n\tint ret = 0;\n\tunsigned nb_rx, nb_tx, num, i;\n\tconst unsigned lcore_id = rte_lcore_id();\n\tstruct rte_mbuf *pkts_burst[PKT_BURST_SZ];\n\n\tif (lcore_id == lcore_master) {\n\t\trte_delay_ms(KNI_TIMEOUT_MS);\n\t\t/* tests of handling kernel request */\n\t\tif (system(IFCONFIG TEST_KNI_PORT\" up\") == -1)\n\t\t\tret = -1;\n\t\tif (system(IFCONFIG TEST_KNI_PORT\" mtu 1400\") == -1)\n\t\t\tret = -1;\n\t\tif (system(IFCONFIG TEST_KNI_PORT\" down\") == -1)\n\t\t\tret = -1;\n\t\trte_delay_ms(KNI_TIMEOUT_MS);\n\t\ttest_kni_processing_flag = 1;\n\t} else if (lcore_id == lcore_ingress) {\n\t\tstruct rte_mempool *mp = test_kni_lookup_mempool();\n\n\t\tif (mp == NULL)\n\t\t\treturn -1;\n\n\t\twhile (1) {\n\t\t\tif (test_kni_processing_flag)\n\t\t\t\tbreak;\n\n\t\t\tfor (nb_rx = 0; nb_rx < PKT_BURST_SZ; nb_rx++) {\n\t\t\t\tpkts_burst[nb_rx] = rte_pktmbuf_alloc(mp);\n\t\t\t\tif (!pkts_burst[nb_rx])\n\t\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tnum = rte_kni_tx_burst(test_kni_ctx, pkts_burst,\n\t\t\t\t\t\t\t\tnb_rx);\n\t\t\tstats.ingress += num;\n\t\t\trte_kni_handle_request(test_kni_ctx);\n\t\t\tif (num < nb_rx) {\n\t\t\t\tfor (i = num; i < nb_rx; i++) {\n\t\t\t\t\trte_pktmbuf_free(pkts_burst[i]);\n\t\t\t\t}\n\t\t\t}\n\t\t\trte_delay_ms(10);\n\t\t}\n\t} else if (lcore_id == lcore_egress) {\n\t\twhile (1) {\n\t\t\tif (test_kni_processing_flag)\n\t\t\t\tbreak;\n\t\t\tnum = rte_kni_rx_burst(test_kni_ctx, pkts_burst,\n\t\t\t\t\t\t\tPKT_BURST_SZ);\n\t\t\tstats.egress += num;\n\t\t\tfor (nb_tx = 0; nb_tx < num; nb_tx++)\n\t\t\t\trte_pktmbuf_free(pkts_burst[nb_tx]);\n\t\t\trte_delay_ms(10);\n\t\t}\n\t}\n\n\treturn ret;\n}\n\nstatic int\ntest_kni_allocate_lcores(void)\n{\n\tunsigned i, count = 0;\n\n\tlcore_master = rte_get_master_lcore();\n\tprintf(\"master lcore: %u\\n\", lcore_master);\n\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n\t\tif (count >=2 )\n\t\t\tbreak;\n\t\tif (rte_lcore_is_enabled(i) && i != lcore_master) {\n\t\t\tcount ++;\n\t\t\tif (count == 1)\n\t\t\t\tlcore_ingress = i;\n\t\t\telse if (count == 2)\n\t\t\t\tlcore_egress = i;\n\t\t}\n\t}\n\tprintf(\"count: %u\\n\", count);\n\n\treturn (count == 2 ? 0 : -1);\n}\n\nstatic int\ntest_kni_register_handler_mp(void)\n{\n#define TEST_KNI_HANDLE_REQ_COUNT 10 /* 5s */\n#define TEST_KNI_HANDLE_REQ_INTERVAL 500 /* ms */\n#define TEST_KNI_MTU 1450\n#define TEST_KNI_MTU_STR \" 1450\"\n\tint pid;\n\n\tpid = fork();\n\tif (pid < 0) {\n\t\tprintf(\"Failed to fork a process\\n\");\n\t\treturn -1;\n\t} else if (pid == 0) {\n\t\tint i;\n\t\tstruct rte_kni *kni = rte_kni_get(TEST_KNI_PORT);\n\t\tstruct rte_kni_ops ops = {\n\t\t\t.change_mtu = kni_change_mtu,\n\t\t\t.config_network_if = NULL,\n\t\t};\n\n\t\tif (!kni) {\n\t\t\tprintf(\"Failed to get KNI named %s\\n\", TEST_KNI_PORT);\n\t\t\texit(-1);\n\t\t}\n\n\t\tkni_pkt_mtu = 0;\n\n\t\t/* Check with the invalid parameters */\n\t\tif (rte_kni_register_handlers(kni, NULL) == 0) {\n\t\t\tprintf(\"Unexpectedly register successuflly \"\n\t\t\t\t\t\"with NULL ops pointer\\n\");\n\t\t\texit(-1);\n\t\t}\n\t\tif (rte_kni_register_handlers(NULL, &ops) == 0) {\n\t\t\tprintf(\"Unexpectedly register successfully \"\n\t\t\t\t\t\"to NULL KNI device pointer\\n\");\n\t\t\texit(-1);\n\t\t}\n\n\t\tif (rte_kni_register_handlers(kni, &ops)) {\n\t\t\tprintf(\"Fail to register ops\\n\");\n\t\t\texit(-1);\n\t\t}\n\n\t\t/* Check registering again after it has been registered */\n\t\tif (rte_kni_register_handlers(kni, &ops) == 0) {\n\t\t\tprintf(\"Unexpectedly register successfully after \"\n\t\t\t\t\t\"it has already been registered\\n\");\n\t\t\texit(-1);\n\t\t}\n\n\t\t/**\n\t\t * Handle the request of setting MTU,\n\t\t * with registered handlers.\n\t\t */\n\t\tfor (i = 0; i < TEST_KNI_HANDLE_REQ_COUNT; i++) {\n\t\t\trte_kni_handle_request(kni);\n\t\t\tif (kni_pkt_mtu == TEST_KNI_MTU)\n\t\t\t\tbreak;\n\t\t\trte_delay_ms(TEST_KNI_HANDLE_REQ_INTERVAL);\n\t\t}\n\t\tif (i >= TEST_KNI_HANDLE_REQ_COUNT) {\n\t\t\tprintf(\"MTU has not been set\\n\");\n\t\t\texit(-1);\n\t\t}\n\n\t\tkni_pkt_mtu = 0;\n\t\tif (rte_kni_unregister_handlers(kni) < 0) {\n\t\t\tprintf(\"Fail to unregister ops\\n\");\n\t\t\texit(-1);\n\t\t}\n\n\t\t/* Check with invalid parameter */\n\t\tif (rte_kni_unregister_handlers(NULL) == 0) {\n\t\t\texit(-1);\n\t\t}\n\n\t\t/**\n\t\t * Handle the request of setting MTU,\n\t\t * without registered handlers.\n\t\t */\n\t\tfor (i = 0; i < TEST_KNI_HANDLE_REQ_COUNT; i++) {\n\t\t\trte_kni_handle_request(kni);\n\t\t\tif (kni_pkt_mtu != 0)\n\t\t\t\tbreak;\n\t\t\trte_delay_ms(TEST_KNI_HANDLE_REQ_INTERVAL);\n\t\t}\n\t\tif (kni_pkt_mtu != 0) {\n\t\t\tprintf(\"MTU shouldn't be set\\n\");\n\t\t\texit(-1);\n\t\t}\n\n\t\texit(0);\n\t} else {\n\t\tint p_ret, status;\n\n\t\trte_delay_ms(1000);\n\t\tif (system(IFCONFIG TEST_KNI_PORT \" mtu\" TEST_KNI_MTU_STR)\n\t\t\t\t\t\t\t\t== -1)\n\t\t\treturn -1;\n\n\t\trte_delay_ms(1000);\n\t\tif (system(IFCONFIG TEST_KNI_PORT \" mtu\" TEST_KNI_MTU_STR)\n\t\t\t\t\t\t\t\t== -1)\n\t\t\treturn -1;\n\n\t\tp_ret = wait(&status);\n\t\tif (!WIFEXITED(status)) {\n\t\t\tprintf(\"Child process (%d) exit abnormally\\n\", p_ret);\n\t\t\treturn -1;\n\t\t}\n\t\tif (WEXITSTATUS(status) != 0) {\n\t\t\tprintf(\"Child process exit with failure\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntest_kni_processing(uint8_t port_id, struct rte_mempool *mp)\n{\n\tint ret = 0;\n\tunsigned i;\n\tstruct rte_kni *kni;\n\tstruct rte_kni_conf conf;\n\tstruct rte_eth_dev_info info;\n\tstruct rte_kni_ops ops;\n\n\tif (!mp)\n\t\treturn -1;\n\n\tmemset(&conf, 0, sizeof(conf));\n\tmemset(&info, 0, sizeof(info));\n\tmemset(&ops, 0, sizeof(ops));\n\n\trte_eth_dev_info_get(port_id, &info);\n\tconf.addr = info.pci_dev->addr;\n\tconf.id = info.pci_dev->id;\n\tsnprintf(conf.name, sizeof(conf.name), TEST_KNI_PORT);\n\n\t/* core id 1 configured for kernel thread */\n\tconf.core_id = 1;\n\tconf.force_bind = 1;\n\tconf.mbuf_size = MAX_PACKET_SZ;\n\tconf.group_id = (uint16_t)port_id;\n\n\tops = kni_ops;\n\tops.port_id = port_id;\n\n\t/* basic test of kni processing */\n\tkni = rte_kni_alloc(mp, &conf, &ops);\n\tif (!kni) {\n\t\tprintf(\"fail to create kni\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_kni_get_port_id(kni) != port_id) {\n\t\tprintf(\"fail to get port id\\n\");\n\t\tret = -1;\n\t\tgoto fail_kni;\n\t}\n\n\tif (rte_kni_info_get(RTE_MAX_ETHPORTS)) {\n\t\tprintf(\"Unexpectedly get a KNI successfully\\n\");\n\t\tret = -1;\n\t\tgoto fail_kni;\n\t}\n\n\ttest_kni_ctx = kni;\n\ttest_kni_processing_flag = 0;\n\tstats.ingress = 0;\n\tstats.egress = 0;\n\n\t/**\n\t * Check multiple processes support on\n\t * registerring/unregisterring handlers.\n\t */\n\tif (test_kni_register_handler_mp() < 0) {\n\t\tprintf(\"fail to check multiple process support\\n\");\n\t\tret = -1;\n\t\tgoto fail_kni;\n\t}\n\n\trte_eal_mp_remote_launch(test_kni_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(i) {\n\t\tif (rte_eal_wait_lcore(i) < 0) {\n\t\t\tret = -1;\n\t\t\tgoto fail_kni;\n\t\t}\n\t}\n\t/**\n\t * Check if the number of mbufs received from kernel space is equal\n\t * to that of transmitted to kernel space\n\t */\n\tif (stats.ingress < KNI_NUM_MBUF_THRESHOLD ||\n\t\tstats.egress < KNI_NUM_MBUF_THRESHOLD) {\n\t\tprintf(\"The ingress/egress number should not be \"\n\t\t\t\"less than %u\\n\", (unsigned)KNI_NUM_MBUF_THRESHOLD);\n\t\tret = -1;\n\t\tgoto fail_kni;\n\t}\n\n\tif (rte_kni_release(kni) < 0) {\n\t\tprintf(\"fail to release kni\\n\");\n\t\treturn -1;\n\t}\n\ttest_kni_ctx = NULL;\n\n\t/* test of releasing a released kni device */\n\tif (rte_kni_release(kni) == 0) {\n\t\tprintf(\"should not release a released kni device\\n\");\n\t\treturn -1;\n\t}\n\n\t/* test of reusing memzone */\n\tkni = rte_kni_alloc(mp, &conf, &ops);\n\tif (!kni) {\n\t\tprintf(\"fail to create kni\\n\");\n\t\treturn -1;\n\t}\n\n\t/* Release the kni for following testing */\n\tif (rte_kni_release(kni) < 0) {\n\t\tprintf(\"fail to release kni\\n\");\n\t\treturn -1;\n\t}\n\n\treturn ret;\nfail_kni:\n\tif (rte_kni_release(kni) < 0) {\n\t\tprintf(\"fail to release kni\\n\");\n\t\tret = -1;\n\t}\n\n\treturn ret;\n}\n\nstatic int\ntest_kni(void)\n{\n\tint ret = -1;\n\tuint8_t nb_ports, port_id;\n\tstruct rte_kni *kni;\n\tstruct rte_mempool *mp;\n\tstruct rte_kni_conf conf;\n\tstruct rte_eth_dev_info info;\n\tstruct rte_kni_ops ops;\n\n\t/* Initialize KNI subsytem */\n\trte_kni_init(KNI_TEST_MAX_PORTS);\n\n\tif (test_kni_allocate_lcores() < 0) {\n\t\tprintf(\"No enough lcores for kni processing\\n\");\n\t\treturn -1;\n\t}\n\n\tmp = test_kni_create_mempool();\n\tif (!mp) {\n\t\tprintf(\"fail to create mempool for kni\\n\");\n\t\treturn -1;\n\t}\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports == 0) {\n\t\tprintf(\"no supported nic port found\\n\");\n\t\treturn -1;\n\t}\n\n\t/* configuring port 0 for the test is enough */\n\tport_id = 0;\n\tret = rte_eth_dev_configure(port_id, 1, 1, &port_conf);\n\tif (ret < 0) {\n\t\tprintf(\"fail to configure port %d\\n\", port_id);\n\t\treturn -1;\n\t}\n\n\tret = rte_eth_rx_queue_setup(port_id, 0, NB_RXD, SOCKET, &rx_conf, mp);\n\tif (ret < 0) {\n\t\tprintf(\"fail to setup rx queue for port %d\\n\", port_id);\n\t\treturn -1;\n\t}\n\n\tret = rte_eth_tx_queue_setup(port_id, 0, NB_TXD, SOCKET, &tx_conf);\n\tif (ret < 0) {\n\t\tprintf(\"fail to setup tx queue for port %d\\n\", port_id);\n\t\treturn -1;\n\t}\n\n\tret = rte_eth_dev_start(port_id);\n\tif (ret < 0) {\n\t\tprintf(\"fail to start port %d\\n\", port_id);\n\t\treturn -1;\n\t}\n\trte_eth_promiscuous_enable(port_id);\n\n\t/* basic test of kni processing */\n\tret = test_kni_processing(port_id, mp);\n\tif (ret < 0)\n\t\tgoto fail;\n\n\t/* test of allocating KNI with NULL mempool pointer */\n\tmemset(&info, 0, sizeof(info));\n\tmemset(&conf, 0, sizeof(conf));\n\tmemset(&ops, 0, sizeof(ops));\n\trte_eth_dev_info_get(port_id, &info);\n\tconf.addr = info.pci_dev->addr;\n\tconf.id = info.pci_dev->id;\n\tconf.group_id = (uint16_t)port_id;\n\tconf.mbuf_size = MAX_PACKET_SZ;\n\n\tops = kni_ops;\n\tops.port_id = port_id;\n\tkni = rte_kni_alloc(NULL, &conf, &ops);\n\tif (kni) {\n\t\tret = -1;\n\t\tprintf(\"unexpectedly creates kni successfully with NULL \"\n\t\t\t\t\t\t\t\"mempool pointer\\n\");\n\t\tgoto fail;\n\t}\n\n\t/* test of allocating KNI without configurations */\n\tkni = rte_kni_alloc(mp, NULL, NULL);\n\tif (kni) {\n\t\tret = -1;\n\t\tprintf(\"Unexpectedly allocate KNI device successfully \"\n\t\t\t\t\t\"without configurations\\n\");\n\t\tgoto fail;\n\t}\n\n\t/* test of allocating KNI without a name */\n\tmemset(&conf, 0, sizeof(conf));\n\tmemset(&info, 0, sizeof(info));\n\tmemset(&ops, 0, sizeof(ops));\n\trte_eth_dev_info_get(port_id, &info);\n\tconf.addr = info.pci_dev->addr;\n\tconf.id = info.pci_dev->id;\n\tconf.group_id = (uint16_t)port_id;\n\tconf.mbuf_size = MAX_PACKET_SZ;\n\n\tops = kni_ops;\n\tops.port_id = port_id;\n\tkni = rte_kni_alloc(mp, &conf, &ops);\n\tif (kni) {\n\t\tret = -1;\n\t\tprintf(\"Unexpectedly allocate a KNI device successfully \"\n\t\t\t\t\t\t\"without a name\\n\");\n\t\tgoto fail;\n\t}\n\n\t/* test of getting port id according to NULL kni context */\n\tif (rte_kni_get_port_id(NULL) < RTE_MAX_ETHPORTS) {\n\t\tret = -1;\n\t\tprintf(\"unexpectedly get port id successfully by NULL kni \"\n\t\t\t\t\t\t\t\t\"pointer\\n\");\n\t\tgoto fail;\n\t}\n\n\t/* test of releasing NULL kni context */\n\tret = rte_kni_release(NULL);\n\tif (ret == 0) {\n\t\tret = -1;\n\t\tprintf(\"unexpectedly release kni successfully\\n\");\n\t\tgoto fail;\n\t}\n\n\t/* test of handling request on NULL device pointer */\n\tret = rte_kni_handle_request(NULL);\n\tif (ret == 0) {\n\t\tret = -1;\n\t\tprintf(\"Unexpectedly handle request on NULL device pointer\\n\");\n\t\tgoto fail;\n\t}\n\n\t/* test of getting KNI device with pointer to NULL */\n\tkni = rte_kni_get(NULL);\n\tif (kni) {\n\t\tret = -1;\n\t\tprintf(\"Unexpectedly get a KNI device with \"\n\t\t\t\t\t\"NULL name pointer\\n\");\n\t\tgoto fail;\n\t}\n\n\t/* test of getting KNI device with an zero length name string */\n\tmemset(&conf, 0, sizeof(conf));\n\tkni = rte_kni_get(conf.name);\n\tif (kni) {\n\t\tret = -1;\n\t\tprintf(\"Unexpectedly get a KNI device with \"\n\t\t\t\t\"zero length name string\\n\");\n\t\tgoto fail;\n\t}\n\n\t/* test of getting KNI device with an invalid string name */\n\tmemset(&conf, 0, sizeof(conf));\n\tsnprintf(conf.name, sizeof(conf.name), \"testing\");\n\tkni = rte_kni_get(conf.name);\n\tif (kni) {\n\t\tret = -1;\n\t\tprintf(\"Unexpectedly get a KNI device with \"\n\t\t\t\t\"a never used name string\\n\");\n\t\tgoto fail;\n\t}\n\n\t/* test the interface of creating a KNI, for backward compatibility */\n\tmemset(&ops, 0, sizeof(ops));\n\tops = kni_ops;\n\tkni = rte_kni_create(port_id, MAX_PACKET_SZ, mp, &ops);\n\tif (!kni) {\n\t\tret = -1;\n\t\tprintf(\"Fail to create a KNI device for port %d\\n\", port_id);\n\t\tgoto fail;\n\t}\n\n\tret = rte_kni_release(kni);\n\tif (ret < 0) {\n\t\tprintf(\"Fail to release a KNI device\\n\");\n\t\tgoto fail;\n\t}\n\n\tret = 0;\n\nfail:\n\trte_eth_dev_stop(port_id);\n\n\treturn ret;\n}\n\nstatic struct test_command kni_cmd = {\n\t.command = \"kni_autotest\",\n\t.callback = test_kni,\n};\nREGISTER_TEST_COMMAND(kni_cmd);\n" }, { "path": "app/test/test_kvargs.c", "content": "/*\n * Copyright 2014 6WIND S.A.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * - Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * - Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * - Neither the name of 6WIND S.A. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n * OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n\n#include \"test.h\"\n\n/* incrementd in handler, to check it is properly called once per\n * key/value association */\nstatic unsigned count;\n\n/* this handler increment the \"count\" variable at each call and check\n * that the key is \"check\" and the value is \"value%d\" */\nstatic int check_handler(const char *key, const char *value,\n\t__rte_unused void *opaque)\n{\n\tchar buf[16];\n\n\t/* we check that the value is \"check\" */\n\tif (strcmp(key, \"check\"))\n\t\treturn -1;\n\n\t/* we check that the value is \"value$(count)\" */\n\tsnprintf(buf, sizeof(buf), \"value%d\", count);\n\tif (strncmp(buf, value, sizeof(buf)))\n\t\treturn -1;\n\n\tcount ++;\n\treturn 0;\n}\n\n/* test a valid case */\nstatic int test_valid_kvargs(void)\n{\n\tstruct rte_kvargs *kvlist;\n\tconst char *args;\n\tconst char *valid_keys_list[] = { \"foo\", \"check\", NULL };\n\tconst char **valid_keys;\n\n\t/* empty args is valid */\n\targs = \"\";\n\tvalid_keys = NULL;\n\tkvlist = rte_kvargs_parse(args, valid_keys);\n\tif (kvlist == NULL) {\n\t\tprintf(\"rte_kvargs_parse() error\");\n\t\tgoto fail;\n\t}\n\trte_kvargs_free(kvlist);\n\n\t/* first test without valid_keys */\n\targs = \"foo=1234,check=value0,check=value1\";\n\tvalid_keys = NULL;\n\tkvlist = rte_kvargs_parse(args, valid_keys);\n\tif (kvlist == NULL) {\n\t\tprintf(\"rte_kvargs_parse() error\");\n\t\tgoto fail;\n\t}\n\t/* call check_handler() for all entries with key=\"check\" */\n\tcount = 0;\n\tif (rte_kvargs_process(kvlist, \"check\", check_handler, NULL) < 0) {\n\t\tprintf(\"rte_kvargs_process() error\\n\");\n\t\trte_kvargs_free(kvlist);\n\t\tgoto fail;\n\t}\n\tif (count != 2) {\n\t\tprintf(\"invalid count value %d after rte_kvargs_process(check)\\n\",\n\t\t\tcount);\n\t\trte_kvargs_free(kvlist);\n\t\tgoto fail;\n\t}\n\tcount = 0;\n\t/* call check_handler() for all entries with key=\"unexistant_key\" */\n\tif (rte_kvargs_process(kvlist, \"unexistant_key\", check_handler, NULL) < 0) {\n\t\tprintf(\"rte_kvargs_process() error\\n\");\n\t\trte_kvargs_free(kvlist);\n\t\tgoto fail;\n\t}\n\tif (count != 0) {\n\t\tprintf(\"invalid count value %d after rte_kvargs_process(unexistant_key)\\n\",\n\t\t\tcount);\n\t\trte_kvargs_free(kvlist);\n\t\tgoto fail;\n\t}\n\t/* count all entries with key=\"foo\" */\n\tcount = rte_kvargs_count(kvlist, \"foo\");\n\tif (count != 1) {\n\t\tprintf(\"invalid count value %d after rte_kvargs_count(foo)\\n\",\n\t\t\tcount);\n\t\trte_kvargs_free(kvlist);\n\t\tgoto fail;\n\t}\n\t/* count all entries */\n\tcount = rte_kvargs_count(kvlist, NULL);\n\tif (count != 3) {\n\t\tprintf(\"invalid count value %d after rte_kvargs_count(NULL)\\n\",\n\t\t\tcount);\n\t\trte_kvargs_free(kvlist);\n\t\tgoto fail;\n\t}\n\t/* count all entries with key=\"unexistant_key\" */\n\tcount = rte_kvargs_count(kvlist, \"unexistant_key\");\n\tif (count != 0) {\n\t\tprintf(\"invalid count value %d after rte_kvargs_count(unexistant_key)\\n\",\n\t\t\tcount);\n\t\trte_kvargs_free(kvlist);\n\t\tgoto fail;\n\t}\n\trte_kvargs_free(kvlist);\n\n\t/* second test using valid_keys */\n\targs = \"foo=droids,check=value0,check=value1,check=wrong_value\";\n\tvalid_keys = valid_keys_list;\n\tkvlist = rte_kvargs_parse(args, valid_keys);\n\tif (kvlist == NULL) {\n\t\tprintf(\"rte_kvargs_parse() error\");\n\t\tgoto fail;\n\t}\n\t/* call check_handler() on all entries with key=\"check\", it\n\t * should fail as the value is not recognized by the handler */\n\tif (rte_kvargs_process(kvlist, \"check\", check_handler, NULL) == 0) {\n\t\tprintf(\"rte_kvargs_process() is success bu should not\\n\");\n\t\trte_kvargs_free(kvlist);\n\t\tgoto fail;\n\t}\n\tcount = rte_kvargs_count(kvlist, \"check\");\n\tif (count != 3) {\n\t\tprintf(\"invalid count value %d after rte_kvargs_count(check)\\n\",\n\t\t\tcount);\n\t\trte_kvargs_free(kvlist);\n\t\tgoto fail;\n\t}\n\trte_kvargs_free(kvlist);\n\n\treturn 0;\n\n fail:\n\tprintf(\"while processing <%s>\", args);\n\tif (valid_keys != NULL && *valid_keys != NULL) {\n\t\tprintf(\" using valid_keys=<%s\", *valid_keys);\n\t\twhile (*(++valid_keys) != NULL)\n\t\t\tprintf(\",%s\", *valid_keys);\n\t\tprintf(\">\");\n\t}\n\tprintf(\"\\n\");\n\treturn -1;\n}\n\n/* test several error cases */\nstatic int test_invalid_kvargs(void)\n{\n\tstruct rte_kvargs *kvlist;\n\t/* list of argument that should fail */\n\tconst char *args_list[] = {\n\t\t\"wrong-key=x\", /* key not in valid_keys_list */\n\t\t\"foo=1,foo=\", /* empty value */\n\t\t\"foo=1,,foo=2\", /* empty key/value */\n\t\t\"foo=1,foo\", /* no value */\n\t\t\"foo=1,=2\", /* no key */\n\t\t\",=\", /* also test with a smiley */\n\t\tNULL };\n\tconst char **args;\n\tconst char *valid_keys_list[] = { \"foo\", \"check\", NULL };\n\tconst char **valid_keys = valid_keys_list;\n\n\tfor (args = args_list; *args != NULL; args++) {\n\n\t\tkvlist = rte_kvargs_parse(*args, valid_keys);\n\t\tif (kvlist != NULL) {\n\t\t\tprintf(\"rte_kvargs_parse() returned 0 (but should not)\\n\");\n\t\t\trte_kvargs_free(kvlist);\n\t\t\tgoto fail;\n\t\t}\n\t\treturn 0;\n\t}\n\n fail:\n\tprintf(\"while processing <%s>\", *args);\n\tif (valid_keys != NULL && *valid_keys != NULL) {\n\t\tprintf(\" using valid_keys=<%s\", *valid_keys);\n\t\twhile (*(++valid_keys) != NULL)\n\t\t\tprintf(\",%s\", *valid_keys);\n\t\tprintf(\">\");\n\t}\n\tprintf(\"\\n\");\n\treturn -1;\n}\n\nstatic int\ntest_kvargs(void)\n{\n\tprintf(\"== test valid case ==\\n\");\n\tif (test_valid_kvargs() < 0)\n\t\treturn -1;\n\tprintf(\"== test invalid case ==\\n\");\n\tif (test_invalid_kvargs() < 0)\n\t\treturn -1;\n\treturn 0;\n}\n\nstatic struct test_command kvargs_cmd = {\n\t.command = \"kvargs_autotest\",\n\t.callback = test_kvargs,\n};\nREGISTER_TEST_COMMAND(kvargs_cmd);\n" }, { "path": "app/test/test_link_bonding.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"unistd.h\"\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"virtual_pmd.h\"\n#include \"packet_burst_generator.h\"\n\n#include \"test.h\"\n\n#define TEST_MAX_NUMBER_OF_PORTS (6)\n\n#define RX_RING_SIZE 128\n#define RX_FREE_THRESH 32\n#define RX_PTHRESH 8\n#define RX_HTHRESH 8\n#define RX_WTHRESH 0\n\n#define TX_RING_SIZE 512\n#define TX_FREE_THRESH 32\n#define TX_PTHRESH 32\n#define TX_HTHRESH 0\n#define TX_WTHRESH 0\n#define TX_RSBIT_THRESH 32\n#define TX_Q_FLAGS (ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOVLANOFFL |\\\n\tETH_TXQ_FLAGS_NOXSUMSCTP | ETH_TXQ_FLAGS_NOXSUMUDP | \\\n\tETH_TXQ_FLAGS_NOXSUMTCP)\n\n#define MBUF_CACHE_SIZE (250)\n#define BURST_SIZE (32)\n\n#define RTE_TEST_RX_DESC_MAX\t(2048)\n#define RTE_TEST_TX_DESC_MAX\t(2048)\n#define MAX_PKT_BURST\t\t\t(512)\n#define DEF_PKT_BURST\t\t\t(16)\n\n#define BONDED_DEV_NAME\t\t\t(\"unit_test_bonded_device\")\n\n#define INVALID_SOCKET_ID\t\t(-1)\n#define INVALID_PORT_ID\t\t\t(-1)\n#define INVALID_BONDING_MODE\t(-1)\n\n\nuint8_t slave_mac[] = {0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00 };\nuint8_t bonded_mac[] = {0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xFF };\n\nstruct link_bonding_unittest_params {\n\tint8_t bonded_port_id;\n\tint8_t slave_port_ids[TEST_MAX_NUMBER_OF_PORTS];\n\tuint8_t bonded_slave_count;\n\tuint8_t bonding_mode;\n\n\tuint16_t nb_rx_q;\n\tuint16_t nb_tx_q;\n\n\tstruct rte_mempool *mbuf_pool;\n\n\tstruct ether_addr *default_slave_mac;\n\tstruct ether_addr *default_bonded_mac;\n\n\t/* Packet Headers */\n\tstruct ether_hdr *pkt_eth_hdr;\n\tstruct ipv4_hdr *pkt_ipv4_hdr;\n\tstruct ipv6_hdr *pkt_ipv6_hdr;\n\tstruct udp_hdr *pkt_udp_hdr;\n\n};\n\nstatic struct ipv4_hdr pkt_ipv4_hdr;\nstatic struct ipv6_hdr pkt_ipv6_hdr;\nstatic struct udp_hdr pkt_udp_hdr;\n\nstatic struct link_bonding_unittest_params default_params = {\n\t.bonded_port_id = -1,\n\t.slave_port_ids = { -1 },\n\t.bonded_slave_count = 0,\n\t.bonding_mode = BONDING_MODE_ROUND_ROBIN,\n\n\t.nb_rx_q = 1,\n\t.nb_tx_q = 1,\n\n\t.mbuf_pool = NULL,\n\n\t.default_slave_mac = (struct ether_addr *)slave_mac,\n\t.default_bonded_mac = (struct ether_addr *)bonded_mac,\n\n\t.pkt_eth_hdr = NULL,\n\t.pkt_ipv4_hdr = &pkt_ipv4_hdr,\n\t.pkt_ipv6_hdr = &pkt_ipv6_hdr,\n\t.pkt_udp_hdr = &pkt_udp_hdr\n\n};\n\nstatic struct link_bonding_unittest_params *test_params = &default_params;\n\nstatic uint8_t src_mac[] = { 0xFF, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA };\nstatic uint8_t dst_mac_0[] = { 0xFF, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA };\nstatic uint8_t dst_mac_1[] = { 0xFF, 0xAA, 0xFF, 0xAA, 0xFF, 0xAB };\n\nstatic uint32_t src_addr = IPV4_ADDR(192, 168, 1, 98);\nstatic uint32_t dst_addr_0 = IPV4_ADDR(192, 168, 1, 98);\nstatic uint32_t dst_addr_1 = IPV4_ADDR(193, 166, 10, 97);\n\nstatic uint8_t src_ipv6_addr[] = { 0xFF, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xFF,\n\t\t0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA , 0xFF, 0xAA };\nstatic uint8_t dst_ipv6_addr_0[] = { 0xFF, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xFF,\n\t\t0xAA, 0xFF, 0xAA, 0xFF, 0xAA , 0xFF, 0xAA, 0xFF, 0xAA };\nstatic uint8_t dst_ipv6_addr_1[] = { 0xFF, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA, 0xFF,\n\t\t0xAA, 0xFF, 0xAA, 0xFF, 0xAA , 0xFF, 0xAA , 0xFF, 0xAB };\n\nstatic uint16_t src_port = 1024;\nstatic uint16_t dst_port_0 = 1024;\nstatic uint16_t dst_port_1 = 2024;\n\nstatic uint16_t vlan_id = 0x100;\n\nstruct rte_eth_rxmode rx_mode = {\n\t.max_rx_pkt_len = ETHER_MAX_LEN, /**< Default maximum frame length. */\n\t.split_hdr_size = 0,\n\t.header_split = 0, /**< Header Split disabled. */\n\t.hw_ip_checksum = 0, /**< IP checksum offload disabled. */\n\t.hw_vlan_filter = 1, /**< VLAN filtering enabled. */\n\t.hw_vlan_strip = 1, /**< VLAN strip enabled. */\n\t.hw_vlan_extend = 0, /**< Extended VLAN disabled. */\n\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled. */\n\t.hw_strip_crc = 0, /**< CRC stripping by hardware disabled. */\n};\n\nstruct rte_fdir_conf fdir_conf = {\n\t.mode = RTE_FDIR_MODE_NONE,\n\t.pballoc = RTE_FDIR_PBALLOC_64K,\n\t.status = RTE_FDIR_REPORT_STATUS,\n\t.drop_queue = 127,\n};\n\nstatic struct rte_eth_conf default_pmd_conf = {\n\t.rxmode = {\n\t\t.mq_mode = ETH_MQ_RX_NONE,\n\t\t.max_rx_pkt_len = ETHER_MAX_LEN,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n\t.lpbk_mode = 0,\n};\n\nstatic const struct rte_eth_rxconf rx_conf_default = {\n\t.rx_thresh = {\n\t\t.pthresh = RX_PTHRESH,\n\t\t.hthresh = RX_HTHRESH,\n\t\t.wthresh = RX_WTHRESH,\n\t},\n\t.rx_free_thresh = RX_FREE_THRESH,\n\t.rx_drop_en = 0,\n};\n\nstatic struct rte_eth_txconf tx_conf_default = {\n\t.tx_thresh = {\n\t\t.pthresh = TX_PTHRESH,\n\t\t.hthresh = TX_HTHRESH,\n\t\t.wthresh = TX_WTHRESH,\n\t},\n\t.tx_free_thresh = TX_FREE_THRESH,\n\t.tx_rs_thresh = TX_RSBIT_THRESH,\n\t.txq_flags = TX_Q_FLAGS\n\n};\n\nstatic int\nconfigure_ethdev(uint8_t port_id, uint8_t start, uint8_t en_isr)\n{\n\tint q_id;\n\n\tif (en_isr)\n\t\tdefault_pmd_conf.intr_conf.lsc = 1;\n\telse\n\t\tdefault_pmd_conf.intr_conf.lsc = 0;\n\n\tTEST_ASSERT_SUCCESS(rte_eth_dev_configure(port_id, test_params->nb_rx_q,\n\t\t\ttest_params->nb_tx_q, &default_pmd_conf),\n\t\t\t\"rte_eth_dev_configure for port %d failed\", port_id);\n\n\tfor (q_id = 0; q_id < test_params->nb_rx_q; q_id++)\n\t\tTEST_ASSERT_SUCCESS(rte_eth_rx_queue_setup(port_id, q_id, RX_RING_SIZE,\n\t\t\t\trte_eth_dev_socket_id(port_id), &rx_conf_default,\n\t\t\t\ttest_params->mbuf_pool) ,\n\t\t\t\t\"rte_eth_rx_queue_setup for port %d failed\", port_id);\n\n\tfor (q_id = 0; q_id < test_params->nb_tx_q; q_id++)\n\t\tTEST_ASSERT_SUCCESS(rte_eth_tx_queue_setup(port_id, q_id, TX_RING_SIZE,\n\t\t\t\trte_eth_dev_socket_id(port_id), &tx_conf_default),\n\t\t\t\t\"rte_eth_tx_queue_setup for port %d failed\", port_id);\n\n\tif (start)\n\t\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(port_id),\n\t\t\t\t\"rte_eth_dev_start for port %d failed\", port_id);\n\n\treturn 0;\n}\n\nstatic int slaves_initialized;\n\nstatic pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;\nstatic pthread_cond_t cvar = PTHREAD_COND_INITIALIZER;\n\n\nstatic int\ntest_setup(void)\n{\n\tint i, nb_mbuf_per_pool;\n\tstruct ether_addr *mac_addr = (struct ether_addr *)slave_mac;\n\n\t/* Allocate ethernet packet header with space for VLAN header */\n\tif (test_params->pkt_eth_hdr == NULL) {\n\t\ttest_params->pkt_eth_hdr = malloc(sizeof(struct ether_hdr) +\n\t\t\t\tsizeof(struct vlan_hdr));\n\n\t\tTEST_ASSERT_NOT_NULL(test_params->pkt_eth_hdr,\n\t\t\t\t\"Ethernet header struct allocation failed!\");\n\t}\n\n\tnb_mbuf_per_pool = RTE_TEST_RX_DESC_MAX + DEF_PKT_BURST +\n\t\t\tRTE_TEST_TX_DESC_MAX + MAX_PKT_BURST;\n\tif (test_params->mbuf_pool == NULL) {\n\t\ttest_params->mbuf_pool = rte_pktmbuf_pool_create(\"MBUF_POOL\",\n\t\t\tnb_mbuf_per_pool, MBUF_CACHE_SIZE, 0,\n\t\t\tRTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\t\tTEST_ASSERT_NOT_NULL(test_params->mbuf_pool,\n\t\t\t\t\"rte_mempool_create failed\");\n\t}\n\n\t/* Create / Initialize virtual eth devs */\n\tif (!slaves_initialized) {\n\t\tfor (i = 0; i < TEST_MAX_NUMBER_OF_PORTS; i++) {\n\t\t\tchar pmd_name[RTE_ETH_NAME_MAX_LEN];\n\n\t\t\tmac_addr->addr_bytes[ETHER_ADDR_LEN-1] = i;\n\n\t\t\tsnprintf(pmd_name, RTE_ETH_NAME_MAX_LEN, \"eth_virt_%d\", i);\n\n\t\t\ttest_params->slave_port_ids[i] = virtual_ethdev_create(pmd_name,\n\t\t\t\t\tmac_addr, rte_socket_id(), 1);\n\t\t\tTEST_ASSERT(test_params->slave_port_ids[i] >= 0,\n\t\t\t\t\t\"Failed to create virtual virtual ethdev %s\", pmd_name);\n\n\t\t\tTEST_ASSERT_SUCCESS(configure_ethdev(\n\t\t\t\t\ttest_params->slave_port_ids[i], 1, 0),\n\t\t\t\t\t\"Failed to configure virtual ethdev %s\", pmd_name);\n\t\t}\n\t\tslaves_initialized = 1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntest_create_bonded_device(void)\n{\n\tint current_slave_count;\n\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\t/* Don't try to recreate bonded device if re-running test suite*/\n\tif (test_params->bonded_port_id == -1) {\n\t\ttest_params->bonded_port_id = rte_eth_bond_create(BONDED_DEV_NAME,\n\t\t\t\ttest_params->bonding_mode, rte_socket_id());\n\n\t\tTEST_ASSERT(test_params->bonded_port_id >= 0,\n\t\t\t\t\"Failed to create bonded ethdev %s\", BONDED_DEV_NAME);\n\n\t\tTEST_ASSERT_SUCCESS(configure_ethdev(test_params->bonded_port_id, 0, 0),\n\t\t\t\t\"Failed to configure bonded ethdev %s\", BONDED_DEV_NAME);\n\t}\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_mode_set(test_params->bonded_port_id,\n\t\t\ttest_params->bonding_mode), \"Failed to set ethdev %d to mode %d\",\n\t\t\ttest_params->bonded_port_id, test_params->bonding_mode);\n\n\tcurrent_slave_count = rte_eth_bond_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\n\tTEST_ASSERT_EQUAL(current_slave_count, 0,\n\t\t\t\"Number of slaves %d is great than expected %d.\",\n\t\t\tcurrent_slave_count, 0);\n\n\tcurrent_slave_count = rte_eth_bond_active_slaves_get(\n\t\t\ttest_params->bonded_port_id, slaves, RTE_MAX_ETHPORTS);\n\n\tTEST_ASSERT_EQUAL(current_slave_count, 0,\n\t\t\t\"Number of active slaves %d is great than expected %d.\",\n\t\t\tcurrent_slave_count, 0);\n\n\treturn 0;\n}\n\n\nstatic int\ntest_create_bonded_device_with_invalid_params(void)\n{\n\tint port_id;\n\n\ttest_params->bonding_mode = BONDING_MODE_ROUND_ROBIN;\n\n\t/* Invalid name */\n\tport_id = rte_eth_bond_create(NULL, test_params->bonding_mode,\n\t\t\trte_socket_id());\n\tTEST_ASSERT(port_id < 0, \"Created bonded device unexpectedly\");\n\n\ttest_params->bonding_mode = INVALID_BONDING_MODE;\n\n\t/* Invalid bonding mode */\n\tport_id = rte_eth_bond_create(BONDED_DEV_NAME, test_params->bonding_mode,\n\t\t\trte_socket_id());\n\tTEST_ASSERT(port_id < 0, \"Created bonded device unexpectedly.\");\n\n\ttest_params->bonding_mode = BONDING_MODE_ROUND_ROBIN;\n\n\t/* Invalid socket id */\n\tport_id = rte_eth_bond_create(BONDED_DEV_NAME, test_params->bonding_mode,\n\t\t\tINVALID_SOCKET_ID);\n\tTEST_ASSERT(port_id < 0, \"Created bonded device unexpectedly.\");\n\n\treturn 0;\n}\n\nstatic int\ntest_add_slave_to_bonded_device(void)\n{\n\tint current_slave_count;\n\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_slave_add(test_params->bonded_port_id,\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count]),\n\t\t\t\"Failed to add slave (%d) to bonded port (%d).\",\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count],\n\t\t\ttest_params->bonded_port_id);\n\n\tcurrent_slave_count = rte_eth_bond_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(current_slave_count, test_params->bonded_slave_count + 1,\n\t\t\t\"Number of slaves (%d) is greater than expected (%d).\",\n\t\t\tcurrent_slave_count, test_params->bonded_slave_count + 1);\n\n\tcurrent_slave_count = rte_eth_bond_active_slaves_get(\n\t\t\ttest_params->bonded_port_id, slaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(current_slave_count, 0,\n\t\t\t\t\t\"Number of active slaves (%d) is not as expected (%d).\\n\",\n\t\t\t\t\tcurrent_slave_count, 0);\n\n\ttest_params->bonded_slave_count++;\n\n\treturn 0;\n}\n\nstatic int\ntest_add_slave_to_invalid_bonded_device(void)\n{\n\t/* Invalid port ID */\n\tTEST_ASSERT_FAIL(rte_eth_bond_slave_add(test_params->bonded_port_id + 5,\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count]),\n\t\t\t\"Expected call to failed as invalid port specified.\");\n\n\t/* Non bonded device */\n\tTEST_ASSERT_FAIL(rte_eth_bond_slave_add(test_params->slave_port_ids[0],\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count]),\n\t\t\t\"Expected call to failed as invalid port specified.\");\n\n\treturn 0;\n}\n\n\nstatic int\ntest_remove_slave_from_bonded_device(void)\n{\n\tint current_slave_count;\n\tstruct ether_addr read_mac_addr, *mac_addr;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_slave_remove(test_params->bonded_port_id,\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count-1]),\n\t\t\t\"Failed to remove slave %d from bonded port (%d).\",\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count-1],\n\t\t\ttest_params->bonded_port_id);\n\n\n\tcurrent_slave_count = rte_eth_bond_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\n\tTEST_ASSERT_EQUAL(current_slave_count, test_params->bonded_slave_count - 1,\n\t\t\t\"Number of slaves (%d) is great than expected (%d).\\n\",\n\t\t\tcurrent_slave_count, test_params->bonded_slave_count - 1);\n\n\n\tmac_addr = (struct ether_addr *)slave_mac;\n\tmac_addr->addr_bytes[ETHER_ADDR_LEN-1] =\n\t\t\ttest_params->bonded_slave_count-1;\n\n\trte_eth_macaddr_get(\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count-1],\n\t\t\t&read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(mac_addr, &read_mac_addr, sizeof(read_mac_addr)),\n\t\t\t\"bonded port mac address not set to that of primary port\\n\");\n\n\trte_eth_stats_reset(\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count-1]);\n\n\tvirtual_ethdev_simulate_link_status_interrupt(test_params->bonded_port_id,\n\t\t\t0);\n\n\ttest_params->bonded_slave_count--;\n\n\treturn 0;\n}\n\nstatic int\ntest_remove_slave_from_invalid_bonded_device(void)\n{\n\t/* Invalid port ID */\n\tTEST_ASSERT_FAIL(rte_eth_bond_slave_remove(\n\t\t\ttest_params->bonded_port_id + 5,\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count - 1]),\n\t\t\t\"Expected call to failed as invalid port specified.\");\n\n\t/* Non bonded device */\n\tTEST_ASSERT_FAIL(rte_eth_bond_slave_remove(\n\t\t\ttest_params->slave_port_ids[0],\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count - 1]),\n\t\t\t\"Expected call to failed as invalid port specified.\");\n\n\treturn 0;\n}\n\nstatic int bonded_id = 2;\n\nstatic int\ntest_add_already_bonded_slave_to_bonded_device(void)\n{\n\tint port_id, current_slave_count;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\tchar pmd_name[RTE_ETH_NAME_MAX_LEN];\n\n\ttest_add_slave_to_bonded_device();\n\n\tcurrent_slave_count = rte_eth_bond_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(current_slave_count, 1,\n\t\t\t\"Number of slaves (%d) is not that expected (%d).\",\n\t\t\tcurrent_slave_count, 1);\n\n\tsnprintf(pmd_name, RTE_ETH_NAME_MAX_LEN, \"%s_%d\", BONDED_DEV_NAME, ++bonded_id);\n\n\tport_id = rte_eth_bond_create(pmd_name, test_params->bonding_mode,\n\t\t\trte_socket_id());\n\tTEST_ASSERT(port_id >= 0, \"Failed to create bonded device.\");\n\n\tTEST_ASSERT(rte_eth_bond_slave_add(port_id,\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count - 1])\n\t\t\t< 0,\n\t\t\t\"Added slave (%d) to bonded port (%d) unexpectedly.\",\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count-1],\n\t\t\tport_id);\n\n\treturn test_remove_slave_from_bonded_device();\n}\n\n\nstatic int\ntest_get_slaves_from_bonded_device(void)\n{\n\tint current_slave_count;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tTEST_ASSERT_SUCCESS(test_add_slave_to_bonded_device(),\n\t\t\t\"Failed to add slave to bonded device\");\n\n\t/* Invalid port id */\n\tcurrent_slave_count = rte_eth_bond_slaves_get(INVALID_PORT_ID, slaves,\n\t\t\tRTE_MAX_ETHPORTS);\n\tTEST_ASSERT(current_slave_count < 0,\n\t\t\t\"Invalid port id unexpectedly succeeded\");\n\n\tcurrent_slave_count = rte_eth_bond_active_slaves_get(INVALID_PORT_ID,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT(current_slave_count < 0,\n\t\t\t\"Invalid port id unexpectedly succeeded\");\n\n\t/* Invalid slaves pointer */\n\tcurrent_slave_count = rte_eth_bond_slaves_get(test_params->bonded_port_id,\n\t\t\tNULL, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT(current_slave_count < 0,\n\t\t\t\"Invalid slave array unexpectedly succeeded\");\n\n\tcurrent_slave_count = rte_eth_bond_active_slaves_get(\n\t\t\ttest_params->bonded_port_id, NULL, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT(current_slave_count < 0,\n\t\t\t\"Invalid slave array unexpectedly succeeded\");\n\n\t/* non bonded device*/\n\tcurrent_slave_count = rte_eth_bond_slaves_get(\n\t\t\ttest_params->slave_port_ids[0], NULL, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT(current_slave_count < 0,\n\t\t\t\"Invalid port id unexpectedly succeeded\");\n\n\tcurrent_slave_count = rte_eth_bond_active_slaves_get(\n\t\t\ttest_params->slave_port_ids[0],\tNULL, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT(current_slave_count < 0,\n\t\t\t\"Invalid port id unexpectedly succeeded\");\n\n\tTEST_ASSERT_SUCCESS(test_remove_slave_from_bonded_device(),\n\t\t\t\"Failed to remove slaves from bonded device\");\n\n\treturn 0;\n}\n\n\nstatic int\ntest_add_remove_multiple_slaves_to_from_bonded_device(void)\n{\n\tint i;\n\n\tfor (i = 0; i < TEST_MAX_NUMBER_OF_PORTS; i++)\n\t\tTEST_ASSERT_SUCCESS(test_add_slave_to_bonded_device(),\n\t\t\t\t\"Failed to add slave to bonded device\");\n\n\tfor (i = 0; i < TEST_MAX_NUMBER_OF_PORTS; i++)\n\t\tTEST_ASSERT_SUCCESS(test_remove_slave_from_bonded_device(),\n\t\t\t\t\"Failed to remove slaves from bonded device\");\n\n\treturn 0;\n}\n\nstatic void\nenable_bonded_slaves(void)\n{\n\tint i;\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tvirtual_ethdev_tx_burst_fn_set_success(test_params->slave_port_ids[i],\n\t\t\t\t1);\n\n\t\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\t\ttest_params->slave_port_ids[i], 1);\n\t}\n}\n\nstatic int\ntest_start_bonded_device(void)\n{\n\tstruct rte_eth_link link_status;\n\n\tint current_slave_count, current_bonding_mode, primary_port;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\t/* Add slave to bonded device*/\n\tTEST_ASSERT_SUCCESS(test_add_slave_to_bonded_device(),\n\t\t\t\"Failed to add slave to bonded device\");\n\n\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(test_params->bonded_port_id),\n\t\t\"Failed to start bonded pmd eth device %d.\",\n\t\ttest_params->bonded_port_id);\n\n\t/* Change link status of virtual pmd so it will be added to the active\n\t * slave list of the bonded device*/\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count-1], 1);\n\n\tcurrent_slave_count = rte_eth_bond_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(current_slave_count, test_params->bonded_slave_count,\n\t\t\t\"Number of slaves (%d) is not expected value (%d).\",\n\t\t\tcurrent_slave_count, test_params->bonded_slave_count);\n\n\tcurrent_slave_count = rte_eth_bond_active_slaves_get(\n\t\t\ttest_params->bonded_port_id, slaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(current_slave_count, test_params->bonded_slave_count,\n\t\t\t\"Number of active slaves (%d) is not expected value (%d).\",\n\t\t\tcurrent_slave_count, test_params->bonded_slave_count);\n\n\tcurrent_bonding_mode = rte_eth_bond_mode_get(test_params->bonded_port_id);\n\tTEST_ASSERT_EQUAL(current_bonding_mode, test_params->bonding_mode,\n\t\t\t\"Bonded device mode (%d) is not expected value (%d).\\n\",\n\t\t\tcurrent_bonding_mode, test_params->bonding_mode);\n\n\tprimary_port = rte_eth_bond_primary_get(test_params->bonded_port_id);\n\tTEST_ASSERT_EQUAL(primary_port, test_params->slave_port_ids[0],\n\t\t\t\"Primary port (%d) is not expected value (%d).\",\n\t\t\tprimary_port, test_params->slave_port_ids[0]);\n\n\trte_eth_link_get(test_params->bonded_port_id, &link_status);\n\tTEST_ASSERT_EQUAL(link_status.link_status, 1,\n\t\t\t\"Bonded port (%d) status (%d) is not expected value (%d).\\n\",\n\t\t\ttest_params->bonded_port_id, link_status.link_status, 1);\n\n\treturn 0;\n}\n\nstatic int\ntest_stop_bonded_device(void)\n{\n\tint current_slave_count;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tstruct rte_eth_link link_status;\n\n\trte_eth_dev_stop(test_params->bonded_port_id);\n\n\trte_eth_link_get(test_params->bonded_port_id, &link_status);\n\tTEST_ASSERT_EQUAL(link_status.link_status, 0,\n\t\t\t\"Bonded port (%d) status (%d) is not expected value (%d).\",\n\t\t\ttest_params->bonded_port_id, link_status.link_status, 0);\n\n\tcurrent_slave_count = rte_eth_bond_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(current_slave_count, test_params->bonded_slave_count,\n\t\t\t\"Number of slaves (%d) is not expected value (%d).\",\n\t\t\tcurrent_slave_count, test_params->bonded_slave_count);\n\n\tcurrent_slave_count = rte_eth_bond_active_slaves_get(\n\t\t\ttest_params->bonded_port_id, slaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(current_slave_count, 0,\n\t\t\t\"Number of active slaves (%d) is not expected value (%d).\",\n\t\t\tcurrent_slave_count, 0);\n\n\treturn 0;\n}\n\nstatic int\nremove_slaves_and_stop_bonded_device(void)\n{\n\t/* Clean up and remove slaves from bonded device */\n\twhile (test_params->bonded_slave_count > 0)\n\t\tTEST_ASSERT_SUCCESS(test_remove_slave_from_bonded_device(),\n\t\t\t\t\"test_remove_slave_from_bonded_device failed\");\n\n\trte_eth_dev_stop(test_params->bonded_port_id);\n\trte_eth_stats_reset(test_params->bonded_port_id);\n\trte_eth_bond_mac_address_reset(test_params->bonded_port_id);\n\n\treturn 0;\n}\n\nstatic int\ntest_set_bonding_mode(void)\n{\n\tint i, bonding_mode;\n\n\tint bonding_modes[] = { BONDING_MODE_ROUND_ROBIN,\n\t\t\t\t\t\t\tBONDING_MODE_ACTIVE_BACKUP,\n\t\t\t\t\t\t\tBONDING_MODE_BALANCE,\n\t\t\t\t\t\t\tBONDING_MODE_BROADCAST\n\t\t\t\t\t\t\t};\n\n\t/* Test supported link bonding modes */\n\tfor (i = 0; i < (int)RTE_DIM(bonding_modes);\ti++) {\n\t\t/* Invalid port ID */\n\t\tTEST_ASSERT_FAIL(rte_eth_bond_mode_set(INVALID_PORT_ID,\n\t\t\t\tbonding_modes[i]),\n\t\t\t\t\"Expected call to failed as invalid port (%d) specified.\",\n\t\t\t\tINVALID_PORT_ID);\n\n\t\t/* Non bonded device */\n\t\tTEST_ASSERT_FAIL(rte_eth_bond_mode_set(test_params->slave_port_ids[0],\n\t\t\t\tbonding_modes[i]),\n\t\t\t\t\"Expected call to failed as invalid port (%d) specified.\",\n\t\t\t\ttest_params->slave_port_ids[0]);\n\n\t\tTEST_ASSERT_SUCCESS(rte_eth_bond_mode_set(test_params->bonded_port_id,\n\t\t\t\tbonding_modes[i]),\n\t\t\t\t\"Failed to set link bonding mode on port (%d) to (%d).\",\n\t\t\t\ttest_params->bonded_port_id, bonding_modes[i]);\n\n\t\tbonding_mode = rte_eth_bond_mode_get(test_params->bonded_port_id);\n\t\tTEST_ASSERT_EQUAL(bonding_mode, bonding_modes[i],\n\t\t\t\t\"Link bonding mode (%d) of port (%d) is not expected value (%d).\",\n\t\t\t\tbonding_mode, test_params->bonded_port_id,\n\t\t\t\tbonding_modes[i]);\n\n\t\t/* Invalid port ID */\n\t\tbonding_mode = rte_eth_bond_mode_get(INVALID_PORT_ID);\n\t\tTEST_ASSERT(bonding_mode < 0,\n\t\t\t\t\"Expected call to failed as invalid port (%d) specified.\",\n\t\t\t\tINVALID_PORT_ID);\n\n\t\t/* Non bonded device */\n\t\tbonding_mode = rte_eth_bond_mode_get(test_params->slave_port_ids[0]);\n\t\tTEST_ASSERT(bonding_mode < 0,\n\t\t\t\t\"Expected call to failed as invalid port (%d) specified.\",\n\t\t\t\ttest_params->slave_port_ids[0]);\n\t}\n\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_set_primary_slave(void)\n{\n\tint i, j, retval;\n\tstruct ether_addr read_mac_addr;\n\tstruct ether_addr *expected_mac_addr;\n\n\t/* Add 4 slaves to bonded device */\n\tfor (i = test_params->bonded_slave_count; i < 4; i++)\n\t\tTEST_ASSERT_SUCCESS(test_add_slave_to_bonded_device(),\n\t\t\t\t\"Failed to add slave to bonded device.\");\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_mode_set(test_params->bonded_port_id,\n\t\t\tBONDING_MODE_ROUND_ROBIN),\n\t\t\t\"Failed to set link bonding mode on port (%d) to (%d).\",\n\t\t\ttest_params->bonded_port_id, BONDING_MODE_ROUND_ROBIN);\n\n\t/* Invalid port ID */\n\tTEST_ASSERT_FAIL(rte_eth_bond_primary_set(INVALID_PORT_ID,\n\t\t\ttest_params->slave_port_ids[i]),\n\t\t\t\"Expected call to failed as invalid port specified.\");\n\n\t/* Non bonded device */\n\tTEST_ASSERT_FAIL(rte_eth_bond_primary_set(test_params->slave_port_ids[i],\n\t\t\ttest_params->slave_port_ids[i]),\n\t\t\t\"Expected call to failed as invalid port specified.\");\n\n\t/* Set slave as primary\n\t * Verify slave it is now primary slave\n\t * Verify that MAC address of bonded device is that of primary slave\n\t * Verify that MAC address of all bonded slaves are that of primary slave\n\t */\n\tfor (i = 0; i < 4; i++) {\n\t\tTEST_ASSERT_SUCCESS(rte_eth_bond_primary_set(test_params->bonded_port_id,\n\t\t\t\ttest_params->slave_port_ids[i]),\n\t\t\t\t\"Failed to set bonded port (%d) primary port to (%d)\",\n\t\t\t\ttest_params->bonded_port_id, test_params->slave_port_ids[i]);\n\n\t\tretval = rte_eth_bond_primary_get(test_params->bonded_port_id);\n\t\tTEST_ASSERT(retval >= 0,\n\t\t\t\t\"Failed to read primary port from bonded port (%d)\\n\",\n\t\t\t\t\ttest_params->bonded_port_id);\n\n\t\tTEST_ASSERT_EQUAL(retval, test_params->slave_port_ids[i],\n\t\t\t\t\"Bonded port (%d) primary port (%d) not expected value (%d)\\n\",\n\t\t\t\ttest_params->bonded_port_id, retval,\n\t\t\t\ttest_params->slave_port_ids[i]);\n\n\t\t/* stop/start bonded eth dev to apply new MAC */\n\t\trte_eth_dev_stop(test_params->bonded_port_id);\n\n\t\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(test_params->bonded_port_id),\n\t\t\t\t\"Failed to start bonded port %d\",\n\t\t\t\ttest_params->bonded_port_id);\n\n\t\texpected_mac_addr = (struct ether_addr *)&slave_mac;\n\t\texpected_mac_addr->addr_bytes[ETHER_ADDR_LEN-1] = i;\n\n\t\t/* Check primary slave MAC */\n\t\trte_eth_macaddr_get(test_params->slave_port_ids[i], &read_mac_addr);\n\t\tTEST_ASSERT_SUCCESS(memcmp(expected_mac_addr, &read_mac_addr,\n\t\t\t\tsizeof(read_mac_addr)),\n\t\t\t\t\"bonded port mac address not set to that of primary port\\n\");\n\n\t\t/* Check bonded MAC */\n\t\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\t\tTEST_ASSERT_SUCCESS(memcmp(&read_mac_addr, &read_mac_addr,\n\t\t\t\tsizeof(read_mac_addr)),\n\t\t\t\t\"bonded port mac address not set to that of primary port\\n\");\n\n\t\t/* Check other slaves MACs */\n\t\tfor (j = 0; j < 4; j++) {\n\t\t\tif (j != i) {\n\t\t\t\trte_eth_macaddr_get(test_params->slave_port_ids[j],\n\t\t\t\t\t\t&read_mac_addr);\n\t\t\t\tTEST_ASSERT_SUCCESS(memcmp(expected_mac_addr, &read_mac_addr,\n\t\t\t\t\t\tsizeof(read_mac_addr)),\n\t\t\t\t\t\t\"slave port mac address not set to that of primary \"\n\t\t\t\t\t\t\"port\");\n\t\t\t}\n\t\t}\n\t}\n\n\n\t/* Test with none existent port */\n\tTEST_ASSERT_FAIL(rte_eth_bond_primary_get(test_params->bonded_port_id + 10),\n\t\t\t\"read primary port from expectedly\");\n\n\t/* Test with slave port */\n\tTEST_ASSERT_FAIL(rte_eth_bond_primary_get(test_params->slave_port_ids[0]),\n\t\t\t\"read primary port from expectedly\\n\");\n\n\tTEST_ASSERT_SUCCESS(remove_slaves_and_stop_bonded_device(),\n\t\t\t\"Failed to stop and remove slaves from bonded device\");\n\n\t/* No slaves */\n\tTEST_ASSERT(rte_eth_bond_primary_get(test_params->bonded_port_id) < 0,\n\t\t\t\"read primary port from expectedly\\n\");\n\n\treturn 0;\n}\n\nstatic int\ntest_set_explicit_bonded_mac(void)\n{\n\tint i;\n\tstruct ether_addr read_mac_addr;\n\tstruct ether_addr *mac_addr;\n\n\tuint8_t explicit_bonded_mac[] = { 0xDE, 0xAD, 0xBE, 0xEF, 0x00, 0x01 };\n\n\tmac_addr = (struct ether_addr *)explicit_bonded_mac;\n\n\t/* Invalid port ID */\n\tTEST_ASSERT_FAIL(rte_eth_bond_mac_address_set(INVALID_PORT_ID, mac_addr),\n\t\t\t\"Expected call to failed as invalid port specified.\");\n\n\t/* Non bonded device */\n\tTEST_ASSERT_FAIL(rte_eth_bond_mac_address_set(\n\t\t\ttest_params->slave_port_ids[0],\tmac_addr),\n\t\t\t\"Expected call to failed as invalid port specified.\");\n\n\t/* NULL MAC address */\n\tTEST_ASSERT_FAIL(rte_eth_bond_mac_address_set(\n\t\t\ttest_params->bonded_port_id, NULL),\n\t\t\t\"Expected call to failed as NULL MAC specified\");\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_mac_address_set(\n\t\t\ttest_params->bonded_port_id, mac_addr),\n\t\t\t\"Failed to set MAC address on bonded port (%d)\",\n\t\t\ttest_params->bonded_port_id);\n\n\t/* Add 4 slaves to bonded device */\n\tfor (i = test_params->bonded_slave_count; i < 4; i++) {\n\t\tTEST_ASSERT_SUCCESS(test_add_slave_to_bonded_device(),\n\t\t\t\t\"Failed to add slave to bonded device.\\n\");\n\t}\n\n\t/* Check bonded MAC */\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(mac_addr, &read_mac_addr, sizeof(read_mac_addr)),\n\t\t\t\"bonded port mac address not set to that of primary port\");\n\n\t/* Check other slaves MACs */\n\tfor (i = 0; i < 4; i++) {\n\t\trte_eth_macaddr_get(test_params->slave_port_ids[i], &read_mac_addr);\n\t\tTEST_ASSERT_SUCCESS(memcmp(mac_addr, &read_mac_addr,\n\t\t\t\tsizeof(read_mac_addr)),\n\t\t\t\t\"slave port mac address not set to that of primary port\");\n\t}\n\n\t/* test resetting mac address on bonded device */\n\tTEST_ASSERT_SUCCESS(\n\t\t\trte_eth_bond_mac_address_reset(test_params->bonded_port_id),\n\t\t\t\"Failed to reset MAC address on bonded port (%d)\",\n\t\t\ttest_params->bonded_port_id);\n\n\tTEST_ASSERT_FAIL(\n\t\t\trte_eth_bond_mac_address_reset(test_params->slave_port_ids[0]),\n\t\t\t\"Reset MAC address on bonded port (%d) unexpectedly\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\t/* test resetting mac address on bonded device with no slaves */\n\tTEST_ASSERT_SUCCESS(remove_slaves_and_stop_bonded_device(),\n\t\t\t\"Failed to remove slaves and stop bonded device\");\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_mac_address_reset(test_params->bonded_port_id),\n\t\t\t\"Failed to reset MAC address on bonded port (%d)\",\n\t\t\t\ttest_params->bonded_port_id);\n\n\treturn 0;\n}\n\n#define BONDED_INIT_MAC_ASSIGNMENT_SLAVE_COUNT (3)\n\nstatic int\ntest_set_bonded_port_initialization_mac_assignment(void)\n{\n\tint i, slave_count, bonded_port_id;\n\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\tint slave_port_ids[BONDED_INIT_MAC_ASSIGNMENT_SLAVE_COUNT];\n\n\tstruct ether_addr slave_mac_addr, bonded_mac_addr, read_mac_addr;\n\n\t/* Initialize default values for MAC addresses */\n\tmemcpy(&slave_mac_addr, slave_mac, sizeof(struct ether_addr));\n\tmemcpy(&bonded_mac_addr, slave_mac, sizeof(struct ether_addr));\n\n\t/*\n\t * 1. a - Create / configure bonded / slave ethdevs\n\t */\n\tbonded_port_id = rte_eth_bond_create(\"ethdev_bond_mac_ass_test\",\n\t\t\tBONDING_MODE_ACTIVE_BACKUP, rte_socket_id());\n\tTEST_ASSERT(bonded_port_id > 0, \"failed to create bonded device\");\n\n\tTEST_ASSERT_SUCCESS(configure_ethdev(bonded_port_id, 0, 0),\n\t\t\t\t\"Failed to configure bonded ethdev\");\n\n\tfor (i = 0; i < BONDED_INIT_MAC_ASSIGNMENT_SLAVE_COUNT; i++) {\n\t\tchar pmd_name[RTE_ETH_NAME_MAX_LEN];\n\n\t\tslave_mac_addr.addr_bytes[ETHER_ADDR_LEN-1] = i + 100;\n\n\t\tsnprintf(pmd_name, RTE_ETH_NAME_MAX_LEN, \"eth_slave_%d\", i);\n\n\t\tslave_port_ids[i] = virtual_ethdev_create(pmd_name,\n\t\t\t\t&slave_mac_addr, rte_socket_id(), 1);\n\n\t\tTEST_ASSERT(slave_port_ids[i] >= 0,\n\t\t\t\t\"Failed to create slave ethdev %s\", pmd_name);\n\n\t\tTEST_ASSERT_SUCCESS(configure_ethdev(slave_port_ids[i], 1, 0),\n\t\t\t\t\"Failed to configure virtual ethdev %s\",\n\t\t\t\tpmd_name);\n\t}\n\n\n\t/*\n\t * 2. Add slave ethdevs to bonded device\n\t */\n\tfor (i = 0; i < BONDED_INIT_MAC_ASSIGNMENT_SLAVE_COUNT; i++) {\n\t\tTEST_ASSERT_SUCCESS(rte_eth_bond_slave_add(bonded_port_id,\n\t\t\t\tslave_port_ids[i]),\n\t\t\t\t\"Failed to add slave (%d) to bonded port (%d).\",\n\t\t\t\tslave_port_ids[i], bonded_port_id);\n\t}\n\n\tslave_count = rte_eth_bond_slaves_get(bonded_port_id, slaves,\n\t\t\tRTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(BONDED_INIT_MAC_ASSIGNMENT_SLAVE_COUNT, slave_count,\n\t\t\t\"Number of slaves (%d) is not as expected (%d)\",\n\t\t\tslave_count, BONDED_INIT_MAC_ASSIGNMENT_SLAVE_COUNT);\n\n\n\t/*\n\t * 3. Set explicit MAC address on bonded ethdev\n\t */\n\tbonded_mac_addr.addr_bytes[ETHER_ADDR_LEN-2] = 0xFF;\n\tbonded_mac_addr.addr_bytes[ETHER_ADDR_LEN-1] = 0xAA;\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_mac_address_set(\n\t\t\tbonded_port_id, &bonded_mac_addr),\n\t\t\t\"Failed to set MAC address on bonded port (%d)\",\n\t\t\tbonded_port_id);\n\n\n\t/* 4. a - Start bonded ethdev\n\t * b - Enable slave devices\n\t * c - Verify bonded/slaves ethdev MAC addresses\n\t */\n\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(bonded_port_id),\n\t\t\t\"Failed to start bonded pmd eth device %d.\",\n\t\t\tbonded_port_id);\n\n\tfor (i = 0; i < BONDED_INIT_MAC_ASSIGNMENT_SLAVE_COUNT; i++) {\n\t\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\t\tslave_port_ids[i], 1);\n\t}\n\n\trte_eth_macaddr_get(bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&bonded_mac_addr, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port mac address not as expected\");\n\n\trte_eth_macaddr_get(slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&bonded_mac_addr, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port 0 mac address not as expected\");\n\n\tslave_mac_addr.addr_bytes[ETHER_ADDR_LEN-1] = 1 + 100;\n\trte_eth_macaddr_get(slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&slave_mac_addr, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port 1 mac address not as expected\");\n\n\tslave_mac_addr.addr_bytes[ETHER_ADDR_LEN-1] = 2 + 100;\n\trte_eth_macaddr_get(slave_port_ids[2], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&slave_mac_addr, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port 2 mac address not as expected\");\n\n\n\t/* 7. a - Change primary port\n\t * b - Stop / Start bonded port\n\t * d - Verify slave ethdev MAC addresses\n\t */\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_primary_set(bonded_port_id,\n\t\t\tslave_port_ids[2]),\n\t\t\t\"failed to set primary port on bonded device.\");\n\n\trte_eth_dev_stop(bonded_port_id);\n\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(bonded_port_id),\n\t\t\t\t\"Failed to start bonded pmd eth device %d.\",\n\t\t\t\tbonded_port_id);\n\n\trte_eth_macaddr_get(bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&bonded_mac_addr, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port mac address not as expected\");\n\n\tslave_mac_addr.addr_bytes[ETHER_ADDR_LEN-1] = 0 + 100;\n\trte_eth_macaddr_get(slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&slave_mac_addr, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port 0 mac address not as expected\");\n\n\tslave_mac_addr.addr_bytes[ETHER_ADDR_LEN-1] = 1 + 100;\n\trte_eth_macaddr_get(slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&slave_mac_addr, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port 1 mac address not as expected\");\n\n\trte_eth_macaddr_get(slave_port_ids[2], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&bonded_mac_addr, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port 2 mac address not as expected\");\n\n\t/* 6. a - Stop bonded ethdev\n\t * b - remove slave ethdevs\n\t * c - Verify slave ethdevs MACs are restored\n\t */\n\trte_eth_dev_stop(bonded_port_id);\n\n\tfor (i = 0; i < BONDED_INIT_MAC_ASSIGNMENT_SLAVE_COUNT; i++) {\n\t\tTEST_ASSERT_SUCCESS(rte_eth_bond_slave_remove(bonded_port_id,\n\t\t\t\tslave_port_ids[i]),\n\t\t\t\t\"Failed to remove slave %d from bonded port (%d).\",\n\t\t\t\tslave_port_ids[i], bonded_port_id);\n\t}\n\n\tslave_count = rte_eth_bond_slaves_get(bonded_port_id, slaves,\n\t\t\tRTE_MAX_ETHPORTS);\n\n\tTEST_ASSERT_EQUAL(slave_count, 0,\n\t\t\t\"Number of slaves (%d) is great than expected (%d).\",\n\t\t\tslave_count, 0);\n\n\tslave_mac_addr.addr_bytes[ETHER_ADDR_LEN-1] = 0 + 100;\n\trte_eth_macaddr_get(slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&slave_mac_addr, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port 0 mac address not as expected\");\n\n\tslave_mac_addr.addr_bytes[ETHER_ADDR_LEN-1] = 1 + 100;\n\trte_eth_macaddr_get(slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&slave_mac_addr, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port 1 mac address not as expected\");\n\n\tslave_mac_addr.addr_bytes[ETHER_ADDR_LEN-1] = 2 + 100;\n\trte_eth_macaddr_get(slave_port_ids[2], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&slave_mac_addr, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port 2 mac address not as expected\");\n\n\treturn 0;\n}\n\n\nstatic int\ninitialize_bonded_device_with_slaves(uint8_t bonding_mode, uint8_t bond_en_isr,\n\t\tuint8_t number_of_slaves, uint8_t enable_slave)\n{\n\t/* Configure bonded device */\n\tTEST_ASSERT_SUCCESS(configure_ethdev(test_params->bonded_port_id, 0,\n\t\t\tbond_en_isr), \"Failed to configure bonding port (%d) in mode %d \"\n\t\t\t\"with (%d) slaves.\", test_params->bonded_port_id, bonding_mode,\n\t\t\tnumber_of_slaves);\n\n\t/* Add slaves to bonded device */\n\twhile (number_of_slaves > test_params->bonded_slave_count)\n\t\tTEST_ASSERT_SUCCESS(test_add_slave_to_bonded_device(),\n\t\t\t\t\"Failed to add slave (%d to bonding port (%d).\",\n\t\t\t\ttest_params->bonded_slave_count - 1,\n\t\t\t\ttest_params->bonded_port_id);\n\n\t/* Set link bonding mode */\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_mode_set(test_params->bonded_port_id,\n\t\t\tbonding_mode),\n\t\t\t\"Failed to set link bonding mode on port (%d) to (%d).\",\n\t\t\ttest_params->bonded_port_id, bonding_mode);\n\n\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(test_params->bonded_port_id),\n\t\t\"Failed to start bonded pmd eth device %d.\",\n\t\ttest_params->bonded_port_id);\n\n\tif (enable_slave)\n\t\tenable_bonded_slaves();\n\n\treturn 0;\n}\n\nstatic int\ntest_adding_slave_after_bonded_device_started(void)\n{\n\tint i;\n\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ROUND_ROBIN, 0, 4, 0),\n\t\t\t\"Failed to add slaves to bonded device\");\n\n\t/* Enabled slave devices */\n\tfor (i = 0; i < test_params->bonded_slave_count + 1; i++) {\n\t\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\t\ttest_params->slave_port_ids[i], 1);\n\t}\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_slave_add(test_params->bonded_port_id,\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count]),\n\t\t\t\"Failed to add slave to bonded port.\\n\");\n\n\trte_eth_stats_reset(\n\t\t\ttest_params->slave_port_ids[test_params->bonded_slave_count]);\n\n\ttest_params->bonded_slave_count++;\n\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n#define TEST_STATUS_INTERRUPT_SLAVE_COUNT\t4\n#define TEST_LSC_WAIT_TIMEOUT_MS\t500\n\nint test_lsc_interrupt_count;\n\n\nstatic void\ntest_bonding_lsc_event_callback(uint8_t port_id __rte_unused,\n\t\tenum rte_eth_event_type type __rte_unused, void *param __rte_unused)\n{\n\tpthread_mutex_lock(&mutex);\n\ttest_lsc_interrupt_count++;\n\n\tpthread_cond_signal(&cvar);\n\tpthread_mutex_unlock(&mutex);\n}\n\nstatic inline int\nlsc_timeout(int wait_us)\n{\n\tint retval = 0;\n\n\tstruct timespec ts;\n\tstruct timeval tp;\n\n\tgettimeofday(&tp, NULL);\n\n\t/* Convert from timeval to timespec */\n\tts.tv_sec = tp.tv_sec;\n\tts.tv_nsec = tp.tv_usec * 1000;\n\tts.tv_nsec += wait_us * 1000;\n\n\tpthread_mutex_lock(&mutex);\n\tif (test_lsc_interrupt_count < 1)\n\t\tretval = pthread_cond_timedwait(&cvar, &mutex, &ts);\n\n\tpthread_mutex_unlock(&mutex);\n\n\tif (retval == 0 && test_lsc_interrupt_count < 1)\n\t\treturn -1;\n\n\treturn retval;\n}\n\nstatic int\ntest_status_interrupt(void)\n{\n\tint slave_count;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\t/* initialized bonding device with T slaves */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ROUND_ROBIN, 1,\n\t\t\tTEST_STATUS_INTERRUPT_SLAVE_COUNT, 1),\n\t\t\t\"Failed to initialise bonded device\");\n\n\ttest_lsc_interrupt_count = 0;\n\n\t/* register link status change interrupt callback */\n\trte_eth_dev_callback_register(test_params->bonded_port_id,\n\t\t\tRTE_ETH_EVENT_INTR_LSC, test_bonding_lsc_event_callback,\n\t\t\t&test_params->bonded_port_id);\n\n\tslave_count = rte_eth_bond_active_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\n\tTEST_ASSERT_EQUAL(slave_count, TEST_STATUS_INTERRUPT_SLAVE_COUNT,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d)\",\n\t\t\tslave_count, TEST_STATUS_INTERRUPT_SLAVE_COUNT);\n\n\t/* Bring all 4 slaves link status to down and test that we have received a\n\t * lsc interrupts */\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[0], 0);\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[1], 0);\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[2], 0);\n\n\tTEST_ASSERT_EQUAL(test_lsc_interrupt_count, 0,\n\t\t\t\"Received a link status change interrupt unexpectedly\");\n\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[3], 0);\n\n\tTEST_ASSERT(lsc_timeout(TEST_LSC_WAIT_TIMEOUT_MS) == 0,\n\t\t\t\"timed out waiting for interrupt\");\n\n\tTEST_ASSERT(test_lsc_interrupt_count > 0,\n\t\t\t\"Did not receive link status change interrupt\");\n\n\tslave_count = rte_eth_bond_active_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\n\tTEST_ASSERT_EQUAL(slave_count, 0,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d)\",\n\t\t\tslave_count, 0);\n\n\t/* bring one slave port up so link status will change */\n\ttest_lsc_interrupt_count = 0;\n\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[0], 1);\n\n\tTEST_ASSERT(lsc_timeout(TEST_LSC_WAIT_TIMEOUT_MS) == 0,\n\t\t\t\"timed out waiting for interrupt\");\n\n\t/* test that we have received another lsc interrupt */\n\tTEST_ASSERT(test_lsc_interrupt_count > 0,\n\t\t\t\"Did not receive link status change interrupt\");\n\n\t/* Verify that calling the same slave lsc interrupt doesn't cause another\n\t * lsc interrupt from bonded device */\n\ttest_lsc_interrupt_count = 0;\n\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[0], 1);\n\n\tTEST_ASSERT(lsc_timeout(TEST_LSC_WAIT_TIMEOUT_MS) != 0,\n\t\t\t\"received unexpected interrupt\");\n\n\tTEST_ASSERT_EQUAL(test_lsc_interrupt_count, 0,\n\t\t\t\"Did not receive link status change interrupt\");\n\n\n\t/* unregister lsc callback before exiting */\n\trte_eth_dev_callback_unregister(test_params->bonded_port_id,\n\t\t\t\tRTE_ETH_EVENT_INTR_LSC, test_bonding_lsc_event_callback,\n\t\t\t\t&test_params->bonded_port_id);\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ngenerate_test_burst(struct rte_mbuf **pkts_burst, uint16_t burst_size,\n\t\tuint8_t vlan, uint8_t ipv4, uint8_t toggle_dst_mac,\n\t\tuint8_t toggle_ip_addr, uint8_t toggle_udp_port)\n{\n\tuint16_t pktlen, generated_burst_size, ether_type;\n\tvoid *ip_hdr;\n\n\tif (ipv4)\n\t\tether_type = ETHER_TYPE_IPv4;\n\telse\n\t\tether_type = ETHER_TYPE_IPv6;\n\n\tif (toggle_dst_mac)\n\t\tinitialize_eth_header(test_params->pkt_eth_hdr,\n\t\t\t\t(struct ether_addr *)src_mac, (struct ether_addr *)dst_mac_1,\n\t\t\t\tether_type, vlan, vlan_id);\n\telse\n\t\tinitialize_eth_header(test_params->pkt_eth_hdr,\n\t\t\t\t(struct ether_addr *)src_mac, (struct ether_addr *)dst_mac_0,\n\t\t\t\tether_type, vlan, vlan_id);\n\n\n\tif (toggle_udp_port)\n\t\tpktlen = initialize_udp_header(test_params->pkt_udp_hdr, src_port,\n\t\t\t\tdst_port_1, 64);\n\telse\n\t\tpktlen = initialize_udp_header(test_params->pkt_udp_hdr, src_port,\n\t\t\t\tdst_port_0, 64);\n\n\tif (ipv4) {\n\t\tif (toggle_ip_addr)\n\t\t\tpktlen = initialize_ipv4_header(test_params->pkt_ipv4_hdr, src_addr,\n\t\t\t\t\tdst_addr_1, pktlen);\n\t\telse\n\t\t\tpktlen = initialize_ipv4_header(test_params->pkt_ipv4_hdr, src_addr,\n\t\t\t\t\tdst_addr_0, pktlen);\n\n\t\tip_hdr = test_params->pkt_ipv4_hdr;\n\t} else {\n\t\tif (toggle_ip_addr)\n\t\t\tpktlen = initialize_ipv6_header(test_params->pkt_ipv6_hdr,\n\t\t\t\t\t(uint8_t *)src_ipv6_addr, (uint8_t *)dst_ipv6_addr_1,\n\t\t\t\t\tpktlen);\n\t\telse\n\t\t\tpktlen = initialize_ipv6_header(test_params->pkt_ipv6_hdr,\n\t\t\t\t\t(uint8_t *)src_ipv6_addr, (uint8_t *)dst_ipv6_addr_0,\n\t\t\t\t\tpktlen);\n\n\t\tip_hdr = test_params->pkt_ipv6_hdr;\n\t}\n\n\t/* Generate burst of packets to transmit */\n\tgenerated_burst_size = generate_packet_burst(test_params->mbuf_pool,\n\t\t\tpkts_burst,\ttest_params->pkt_eth_hdr, vlan, ip_hdr, ipv4,\n\t\t\ttest_params->pkt_udp_hdr, burst_size, PACKET_BURST_GEN_PKT_LEN_128,\n\t\t\t1);\n\tTEST_ASSERT_EQUAL(generated_burst_size, burst_size,\n\t\t\t\"Failed to generate packet burst\");\n\n\treturn generated_burst_size;\n}\n\n/** Round Robin Mode Tests */\n\nstatic int\ntest_roundrobin_tx_burst(void)\n{\n\tint i, burst_size;\n\tstruct rte_mbuf *pkt_burst[MAX_PKT_BURST];\n\tstruct rte_eth_stats port_stats;\n\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ROUND_ROBIN, 0, 2, 1),\n\t\t\t\"Failed to intialise bonded device\");\n\n\tburst_size = 20 * test_params->bonded_slave_count;\n\n\tTEST_ASSERT(burst_size <= MAX_PKT_BURST,\n\t\t\t\"Burst size specified is greater than supported.\");\n\n\t/* Generate test bursts of packets to transmit */\n\tTEST_ASSERT_EQUAL(generate_test_burst(pkt_burst, burst_size, 0, 1, 0, 0, 0),\n\t\t\tburst_size, \"failed to generate test burst\");\n\n\t/* Send burst on bonded port */\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(\n\t\t\ttest_params->bonded_port_id, 0, pkt_burst, burst_size), burst_size,\n\t\t\t\"tx burst failed\");\n\n\t/* Verify bonded port tx stats */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size,\n\t\t\t\"Bonded Port (%d) opackets value (%u) not as expected (%d)\\n\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.opackets,\n\t\t\tburst_size);\n\n\t/* Verify slave ports tx stats */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\trte_eth_stats_get(test_params->slave_port_ids[i], &port_stats);\n\t\tTEST_ASSERT_EQUAL(port_stats.opackets,\n\t\t\t\t(uint64_t)burst_size / test_params->bonded_slave_count,\n\t\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\\n\",\n\t\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.opackets,\n\t\t\t\tburst_size / test_params->bonded_slave_count);\n\t}\n\n\t/* Put all slaves down and try and transmit */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\t\ttest_params->slave_port_ids[i], 0);\n\t}\n\n\t/* Send burst on bonded port */\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(test_params->bonded_port_id, 0,\n\t\t\tpkt_burst, burst_size), 0,\n\t\t\t\"tx burst return unexpected value\");\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\nverify_mbufs_ref_count(struct rte_mbuf **mbufs, int nb_mbufs, int val)\n{\n\tint i, refcnt;\n\n\tfor (i = 0; i < nb_mbufs; i++) {\n\t\trefcnt = rte_mbuf_refcnt_read(mbufs[i]);\n\t\tTEST_ASSERT_EQUAL(refcnt, val,\n\t\t\t\"mbuf ref count (%d)is not the expected value (%d)\",\n\t\t\trefcnt, val);\n\t}\n\treturn 0;\n}\n\nstatic void\nfree_mbufs(struct rte_mbuf **mbufs, int nb_mbufs)\n{\n\tint i;\n\n\tfor (i = 0; i < nb_mbufs; i++)\n\t\trte_pktmbuf_free(mbufs[i]);\n}\n\n#define TEST_RR_SLAVE_TX_FAIL_SLAVE_COUNT\t\t(2)\n#define TEST_RR_SLAVE_TX_FAIL_BURST_SIZE\t\t(64)\n#define TEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT\t\t(22)\n#define TEST_RR_SLAVE_TX_FAIL_FAILING_SLAVE_IDX\t(1)\n\nstatic int\ntest_roundrobin_tx_burst_slave_tx_fail(void)\n{\n\tstruct rte_mbuf *pkt_burst[MAX_PKT_BURST];\n\tstruct rte_mbuf *expected_tx_fail_pkts[MAX_PKT_BURST];\n\n\tstruct rte_eth_stats port_stats;\n\n\tint i, first_fail_idx, tx_count;\n\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ROUND_ROBIN, 0,\n\t\t\tTEST_RR_SLAVE_TX_FAIL_SLAVE_COUNT, 1),\n\t\t\t\"Failed to intialise bonded device\");\n\n\t/* Generate test bursts of packets to transmit */\n\tTEST_ASSERT_EQUAL(generate_test_burst(pkt_burst,\n\t\t\tTEST_RR_SLAVE_TX_FAIL_BURST_SIZE, 0, 1, 0, 0, 0),\n\t\t\tTEST_RR_SLAVE_TX_FAIL_BURST_SIZE,\n\t\t\t\"Failed to generate test packet burst\");\n\n\t/* Copy references to packets which we expect not to be transmitted */\n\tfirst_fail_idx = (TEST_RR_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\t(TEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT *\n\t\t\tTEST_RR_SLAVE_TX_FAIL_SLAVE_COUNT)) +\n\t\t\tTEST_RR_SLAVE_TX_FAIL_FAILING_SLAVE_IDX;\n\n\tfor (i = 0; i < TEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT; i++) {\n\t\texpected_tx_fail_pkts[i] = pkt_burst[first_fail_idx +\n\t\t\t\t(i * TEST_RR_SLAVE_TX_FAIL_SLAVE_COUNT)];\n\t}\n\n\t/* Set virtual slave to only fail transmission of\n\t * TEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT packets in burst */\n\tvirtual_ethdev_tx_burst_fn_set_success(\n\t\t\ttest_params->slave_port_ids[TEST_RR_SLAVE_TX_FAIL_FAILING_SLAVE_IDX],\n\t\t\t0);\n\n\tvirtual_ethdev_tx_burst_fn_set_tx_pkt_fail_count(\n\t\t\ttest_params->slave_port_ids[TEST_RR_SLAVE_TX_FAIL_FAILING_SLAVE_IDX],\n\t\t\tTEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT);\n\n\ttx_count = rte_eth_tx_burst(test_params->bonded_port_id, 0, pkt_burst,\n\t\t\tTEST_RR_SLAVE_TX_FAIL_BURST_SIZE);\n\n\tTEST_ASSERT_EQUAL(tx_count, TEST_RR_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT,\n\t\t\t\"Transmitted (%d) an unexpected (%d) number of packets\", tx_count,\n\t\t\tTEST_RR_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT);\n\n\t/* Verify that failed packet are expected failed packets */\n\tfor (i = 0; i < TEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT; i++) {\n\t\tTEST_ASSERT_EQUAL(expected_tx_fail_pkts[i], pkt_burst[i + tx_count],\n\t\t\t\t\"expected mbuf (%d) pointer %p not expected pointer %p\",\n\t\t\t\ti, expected_tx_fail_pkts[i], pkt_burst[i + tx_count]);\n\t}\n\n\t/* Verify bonded port tx stats */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\n\tTEST_ASSERT_EQUAL(port_stats.opackets,\n\t\t\t(uint64_t)TEST_RR_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT,\n\t\t\t\"Bonded Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.opackets,\n\t\t\tTEST_RR_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT);\n\n\t/* Verify slave ports tx stats */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tint slave_expected_tx_count;\n\n\t\trte_eth_stats_get(test_params->slave_port_ids[i], &port_stats);\n\n\t\tslave_expected_tx_count = TEST_RR_SLAVE_TX_FAIL_BURST_SIZE /\n\t\t\t\ttest_params->bonded_slave_count;\n\n\t\tif (i == TEST_RR_SLAVE_TX_FAIL_FAILING_SLAVE_IDX)\n\t\t\tslave_expected_tx_count = slave_expected_tx_count -\n\t\t\t\t\tTEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT;\n\n\t\tTEST_ASSERT_EQUAL(port_stats.opackets,\n\t\t\t\t(uint64_t)slave_expected_tx_count,\n\t\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\t\ttest_params->slave_port_ids[i],\n\t\t\t\t(unsigned int)port_stats.opackets, slave_expected_tx_count);\n\t}\n\n\t/* Verify that all mbufs have a ref value of zero */\n\tTEST_ASSERT_SUCCESS(verify_mbufs_ref_count(&pkt_burst[tx_count],\n\t\t\tTEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT, 1),\n\t\t\t\"mbufs refcnts not as expected\");\n\tfree_mbufs(&pkt_burst[tx_count], TEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT);\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_roundrobin_rx_burst_on_single_slave(void)\n{\n\tstruct rte_mbuf *gen_pkt_burst[MAX_PKT_BURST] = { NULL };\n\tstruct rte_mbuf *rx_pkt_burst[MAX_PKT_BURST] = { NULL };\n\n\tstruct rte_eth_stats port_stats;\n\n\tint i, j, burst_size = 25;\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ROUND_ROBIN, 0, 4, 1),\n\t\t\t\"Failed to initialize bonded device with slaves\");\n\n\t/* Generate test bursts of packets to transmit */\n\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\tgen_pkt_burst, burst_size, 0, 1, 0, 0, 0), burst_size,\n\t\t\t\"burst generation failed\");\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\t/* Add rx data to slave */\n\t\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[i],\n\t\t\t\t&gen_pkt_burst[0], burst_size);\n\n\t\t/* Call rx burst on bonded device */\n\t\t/* Send burst on bonded port */\n\t\tTEST_ASSERT_EQUAL(rte_eth_rx_burst(\n\t\t\t\ttest_params->bonded_port_id, 0, rx_pkt_burst,\n\t\t\t\tMAX_PKT_BURST), burst_size,\n\t\t\t\t\"round-robin rx burst failed\");\n\n\t\t/* Verify bonded device rx count */\n\t\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\t\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size,\n\t\t\t\t\"Bonded Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\t\ttest_params->bonded_port_id,\n\t\t\t\t(unsigned int)port_stats.ipackets, burst_size);\n\n\n\n\t\t/* Verify bonded slave devices rx count */\n\t\t/* Verify slave ports tx stats */\n\t\tfor (j = 0; j < test_params->bonded_slave_count; j++) {\n\t\t\trte_eth_stats_get(test_params->slave_port_ids[j], &port_stats);\n\n\t\t\tif (i == j) {\n\t\t\t\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size,\n\t\t\t\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected\"\n\t\t\t\t\t\t\" (%d)\", test_params->slave_port_ids[i],\n\t\t\t\t\t\t(unsigned int)port_stats.ipackets, burst_size);\n\t\t\t} else {\n\t\t\t\tTEST_ASSERT_EQUAL(port_stats.ipackets, 0,\n\t\t\t\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected\"\n\t\t\t\t\t\t\" (%d)\", test_params->slave_port_ids[i],\n\t\t\t\t\t\t(unsigned int)port_stats.ipackets, 0);\n\t\t\t}\n\n\t\t\t/* Reset bonded slaves stats */\n\t\t\trte_eth_stats_reset(test_params->slave_port_ids[j]);\n\t\t}\n\t\t/* reset bonded device stats */\n\t\trte_eth_stats_reset(test_params->bonded_port_id);\n\t}\n\n\t/* free mbufs */\n\tfor (i = 0; i < MAX_PKT_BURST; i++) {\n\t\tif (gen_pkt_burst[i] != NULL)\n\t\t\trte_pktmbuf_free(gen_pkt_burst[i]);\n\n\t\tif (rx_pkt_burst[i] != NULL)\n\t\t\trte_pktmbuf_free(rx_pkt_burst[i]);\n\t}\n\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n#define TEST_ROUNDROBIN_TX_BURST_SLAVE_COUNT (3)\n\nstatic int\ntest_roundrobin_rx_burst_on_multiple_slaves(void)\n{\n\tstruct rte_mbuf *gen_pkt_burst[TEST_ROUNDROBIN_TX_BURST_SLAVE_COUNT][MAX_PKT_BURST];\n\n\tstruct rte_mbuf *rx_pkt_burst[MAX_PKT_BURST] = { NULL };\n\tstruct rte_eth_stats port_stats;\n\n\tint burst_size[TEST_ROUNDROBIN_TX_BURST_SLAVE_COUNT] = { 15, 13, 36 };\n\tint i, nb_rx;\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ROUND_ROBIN, 0, 4, 1),\n\t\t\t\"Failed to initialize bonded device with slaves\");\n\n\t/* Generate test bursts of packets to transmit */\n\tfor (i = 0; i < TEST_ROUNDROBIN_TX_BURST_SLAVE_COUNT; i++) {\n\t\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t\t&gen_pkt_burst[i][0], burst_size[i], 0, 1, 0, 0, 0),\n\t\t\t\tburst_size[i], \"burst generation failed\");\n\t}\n\n\t/* Add rx data to slaves */\n\tfor (i = 0; i < TEST_ROUNDROBIN_TX_BURST_SLAVE_COUNT; i++) {\n\t\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[i],\n\t\t\t\t&gen_pkt_burst[i][0], burst_size[i]);\n\t}\n\n\t/* Call rx burst on bonded device */\n\t/* Send burst on bonded port */\n\tnb_rx = rte_eth_rx_burst(test_params->bonded_port_id, 0, rx_pkt_burst,\n\t\t\tMAX_PKT_BURST);\n\tTEST_ASSERT_EQUAL(nb_rx , burst_size[0] + burst_size[1] + burst_size[2],\n\t\t\t\"round-robin rx burst failed (%d != %d)\\n\", nb_rx,\n\t\t\tburst_size[0] + burst_size[1] + burst_size[2]);\n\n\t/* Verify bonded device rx count */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets,\n\t\t\t(uint64_t)(burst_size[0] + burst_size[1] + burst_size[2]),\n\t\t\t\"Bonded Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.ipackets,\n\t\t\tburst_size[0] + burst_size[1] + burst_size[2]);\n\n\t/* Verify bonded slave devices rx counts */\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size[0],\n\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[0],\n\t\t\t(unsigned int)port_stats.ipackets, burst_size[0]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size[1],\n\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[1], (unsigned int)port_stats.ipackets,\n\t\t\tburst_size[1]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[2], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size[2],\n\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\t\ttest_params->slave_port_ids[2],\n\t\t\t\t(unsigned int)port_stats.ipackets, burst_size[2]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[3], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, 0,\n\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[3],\n\t\t\t(unsigned int)port_stats.ipackets, 0);\n\n\t/* free mbufs */\n\tfor (i = 0; i < MAX_PKT_BURST; i++) {\n\t\tif (rx_pkt_burst[i] != NULL)\n\t\t\trte_pktmbuf_free(rx_pkt_burst[i]);\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_roundrobin_verify_mac_assignment(void)\n{\n\tstruct ether_addr read_mac_addr, expected_mac_addr_0, expected_mac_addr_2;\n\n\tint i;\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &expected_mac_addr_0);\n\trte_eth_macaddr_get(test_params->slave_port_ids[2], &expected_mac_addr_2);\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\t\tBONDING_MODE_ROUND_ROBIN, 0, 4, 1),\n\t\t\t\t\"Failed to initialize bonded device with slaves\");\n\n\t/* Verify that all MACs are the same as first slave added to bonded dev */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\trte_eth_macaddr_get(test_params->slave_port_ids[i], &read_mac_addr);\n\t\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\t\tsizeof(read_mac_addr)),\n\t\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t}\n\n\t/* change primary and verify that MAC addresses haven't changed */\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_primary_set(test_params->bonded_port_id,\n\t\t\ttest_params->slave_port_ids[2]),\n\t\t\t\"Failed to set bonded port (%d) primary port to (%d)\",\n\t\t\ttest_params->bonded_port_id, test_params->slave_port_ids[i]);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\trte_eth_macaddr_get(test_params->slave_port_ids[i], &read_mac_addr);\n\t\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\t\tsizeof(read_mac_addr)),\n\t\t\t\t\"slave port (%d) mac address has changed to that of primary\"\n\t\t\t\t\" port without stop/start toggle of bonded device\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t}\n\n\t/* stop / start bonded device and verify that primary MAC address is\n\t * propagate to bonded device and slaves */\n\trte_eth_dev_stop(test_params->bonded_port_id);\n\n\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(test_params->bonded_port_id),\n\t\t\t\"Failed to start bonded device\");\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(\n\t\t\tmemcmp(&expected_mac_addr_2, &read_mac_addr, sizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of new primary port\",\n\t\t\ttest_params->slave_port_ids[i]);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\trte_eth_macaddr_get(test_params->slave_port_ids[i], &read_mac_addr);\n\t\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_2, &read_mac_addr,\n\t\t\t\tsizeof(read_mac_addr)),\n\t\t\t\t\"slave port (%d) mac address not set to that of new primary\"\n\t\t\t\t\" port\", test_params->slave_port_ids[i]);\n\t}\n\n\t/* Set explicit MAC address */\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_mac_address_set(\n\t\t\ttest_params->bonded_port_id, (struct ether_addr *)bonded_mac),\n\t\t\t\"Failed to set MAC\");\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(bonded_mac, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of new primary port\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\trte_eth_macaddr_get(test_params->slave_port_ids[i], &read_mac_addr);\n\t\tTEST_ASSERT_SUCCESS(memcmp(bonded_mac, &read_mac_addr,\n\t\t\t\tsizeof(read_mac_addr)), \"slave port (%d) mac address not set to\"\n\t\t\t\t\" that of new primary port\\n\", test_params->slave_port_ids[i]);\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_roundrobin_verify_promiscuous_enable_disable(void)\n{\n\tint i, promiscuous_en;\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ROUND_ROBIN, 0, 4, 1),\n\t\t\t\"Failed to initialize bonded device with slaves\");\n\n\trte_eth_promiscuous_enable(test_params->bonded_port_id);\n\n\tpromiscuous_en = rte_eth_promiscuous_get(test_params->bonded_port_id);\n\tTEST_ASSERT_EQUAL(promiscuous_en, 1,\n\t\t\t\"Port (%d) promiscuous mode not enabled\",\n\t\t\ttest_params->bonded_port_id);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tpromiscuous_en = rte_eth_promiscuous_get(\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t\tTEST_ASSERT_EQUAL(promiscuous_en, 1,\n\t\t\t\t\"slave port (%d) promiscuous mode not enabled\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t}\n\n\trte_eth_promiscuous_disable(test_params->bonded_port_id);\n\n\tpromiscuous_en = rte_eth_promiscuous_get(test_params->bonded_port_id);\n\tTEST_ASSERT_EQUAL(promiscuous_en, 0,\n\t\t\t\"Port (%d) promiscuous mode not disabled\\n\",\n\t\t\ttest_params->bonded_port_id);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tpromiscuous_en = rte_eth_promiscuous_get(\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t\tTEST_ASSERT_EQUAL(promiscuous_en, 0,\n\t\t\t\t\"Port (%d) promiscuous mode not disabled\\n\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n#define TEST_RR_LINK_STATUS_SLAVE_COUNT (4)\n#define TEST_RR_LINK_STATUS_EXPECTED_ACTIVE_SLAVE_COUNT (2)\n\nstatic int\ntest_roundrobin_verify_slave_link_status_change_behaviour(void)\n{\n\tstruct rte_mbuf *tx_pkt_burst[MAX_PKT_BURST] = { NULL };\n\tstruct rte_mbuf *gen_pkt_burst[TEST_RR_LINK_STATUS_SLAVE_COUNT][MAX_PKT_BURST];\n\tstruct rte_mbuf *rx_pkt_burst[MAX_PKT_BURST] = { NULL };\n\n\tstruct rte_eth_stats port_stats;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tint i, burst_size, slave_count;\n\n\t/* NULL all pointers in array to simplify cleanup */\n\tmemset(gen_pkt_burst, 0, sizeof(gen_pkt_burst));\n\n\t/* Initialize bonded device with TEST_RR_LINK_STATUS_SLAVE_COUNT slaves\n\t * in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ROUND_ROBIN, 0, TEST_RR_LINK_STATUS_SLAVE_COUNT, 1),\n\t\t\t\"Failed to initialize bonded device with slaves\");\n\n\t/* Verify Current Slaves Count /Active Slave Count is */\n\tslave_count = rte_eth_bond_slaves_get(test_params->bonded_port_id, slaves,\n\t\t\tRTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(slave_count, TEST_RR_LINK_STATUS_SLAVE_COUNT,\n\t\t\t\"Number of slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, TEST_RR_LINK_STATUS_SLAVE_COUNT);\n\n\tslave_count = rte_eth_bond_active_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(slave_count, TEST_RR_LINK_STATUS_SLAVE_COUNT,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, TEST_RR_LINK_STATUS_SLAVE_COUNT);\n\n\t/* Set 2 slaves eth_devs link status to down */\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[1], 0);\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[3], 0);\n\n\tslave_count = rte_eth_bond_active_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(slave_count,\n\t\t\tTEST_RR_LINK_STATUS_EXPECTED_ACTIVE_SLAVE_COUNT,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d).\\n\",\n\t\t\tslave_count, TEST_RR_LINK_STATUS_EXPECTED_ACTIVE_SLAVE_COUNT);\n\n\tburst_size = 20;\n\n\t/* Verify that pkts are not sent on slaves with link status down:\n\t *\n\t * 1. Generate test burst of traffic\n\t * 2. Transmit burst on bonded eth_dev\n\t * 3. Verify stats for bonded eth_dev (opackets = burst_size)\n\t * 4. Verify stats for slave eth_devs (s0 = 10, s1 = 0, s2 = 10, s3 = 0)\n\t */\n\tTEST_ASSERT_EQUAL(\n\t\t\tgenerate_test_burst(tx_pkt_burst, burst_size, 0, 1, 0, 0, 0),\n\t\t\tburst_size, \"generate_test_burst failed\");\n\n\trte_eth_stats_reset(test_params->bonded_port_id);\n\n\n\tTEST_ASSERT_EQUAL(\n\t\t\trte_eth_tx_burst(test_params->bonded_port_id, 0, tx_pkt_burst,\n\t\t\tburst_size), burst_size, \"rte_eth_tx_burst failed\");\n\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size,\n\t\t\t\"Port (%d) opackets stats (%d) not expected (%d) value\",\n\t\t\ttest_params->bonded_port_id, (int)port_stats.opackets,\n\t\t\tburst_size);\n\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)10,\n\t\t\t\"Port (%d) opackets stats (%d) not expected (%d) value\",\n\t\t\ttest_params->slave_port_ids[0], (int)port_stats.opackets, 10);\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)0,\n\t\t\t\"Port (%d) opackets stats (%d) not expected (%d) value\",\n\t\t\ttest_params->slave_port_ids[1], (int)port_stats.opackets, 0);\n\n\trte_eth_stats_get(test_params->slave_port_ids[2], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)10,\n\t\t\t\"Port (%d) opackets stats (%d) not expected (%d) value\",\n\t\t\ttest_params->slave_port_ids[2], (int)port_stats.opackets, 10);\n\n\trte_eth_stats_get(test_params->slave_port_ids[3], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)0,\n\t\t\t\"Port (%d) opackets stats (%d) not expected (%d) value\",\n\t\t\ttest_params->slave_port_ids[3], (int)port_stats.opackets, 0);\n\n\t/* Verify that pkts are not sent on slaves with link status down:\n\t *\n\t * 1. Generate test bursts of traffic\n\t * 2. Add bursts on to virtual eth_devs\n\t * 3. Rx burst on bonded eth_dev, expected (burst_ size *\n\t * TEST_RR_LINK_STATUS_EXPECTED_ACTIVE_SLAVE_COUNT) received\n\t * 4. Verify stats for bonded eth_dev\n\t * 6. Verify stats for slave eth_devs (s0 = 10, s1 = 0, s2 = 10, s3 = 0)\n\t */\n\tfor (i = 0; i < TEST_RR_LINK_STATUS_SLAVE_COUNT; i++) {\n\t\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t\t&gen_pkt_burst[i][0], burst_size, 0, 1, 0, 0, 0),\n\t\t\t\tburst_size, \"failed to generate packet burst\");\n\n\t\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[i],\n\t\t\t\t&gen_pkt_burst[i][0], burst_size);\n\t}\n\n\tTEST_ASSERT_EQUAL(rte_eth_rx_burst(\n\t\t\ttest_params->bonded_port_id, 0, rx_pkt_burst, MAX_PKT_BURST),\n\t\t\tburst_size + burst_size,\n\t\t\t\"rte_eth_rx_burst failed\");\n\n\t/* Verify bonded device rx count */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets , (uint64_t)(burst_size + burst_size),\n\t\t\t\"(%d) port_stats.ipackets not as expected\\n\",\n\t\t\ttest_params->bonded_port_id);\n\n\t/* free mbufs */\n\tfor (i = 0; i < MAX_PKT_BURST; i++) {\n\t\tif (rx_pkt_burst[i] != NULL)\n\t\t\trte_pktmbuf_free(rx_pkt_burst[i]);\n\n\t\tif (gen_pkt_burst[1][i] != NULL)\n\t\t\trte_pktmbuf_free(gen_pkt_burst[1][i]);\n\n\t\tif (gen_pkt_burst[3][i] != NULL)\n\t\t\trte_pktmbuf_free(gen_pkt_burst[1][i]);\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n#define TEST_RR_POLLING_LINK_STATUS_SLAVE_COUNT (2)\n\nuint8_t polling_slave_mac[] = {0xDE, 0xAD, 0xBE, 0xEF, 0x00, 0x00 };\n\n\nint polling_test_slaves[TEST_RR_POLLING_LINK_STATUS_SLAVE_COUNT] = { -1, -1 };\n\nstatic int\ntest_roundrobin_verfiy_polling_slave_link_status_change(void)\n{\n\tstruct ether_addr *mac_addr = (struct ether_addr *)polling_slave_mac;\n\tchar slave_name[RTE_ETH_NAME_MAX_LEN];\n\n\tint i;\n\n\tfor (i = 0; i < TEST_RR_POLLING_LINK_STATUS_SLAVE_COUNT; i++) {\n\t\t/* Generate slave name / MAC address */\n\t\tsnprintf(slave_name, RTE_ETH_NAME_MAX_LEN, \"eth_virt_poll_%d\", i);\n\t\tmac_addr->addr_bytes[ETHER_ADDR_LEN-1] = i;\n\n\t\t/* Create slave devices with no ISR Support */\n\t\tif (polling_test_slaves[i] == -1) {\n\t\t\tpolling_test_slaves[i] = virtual_ethdev_create(slave_name, mac_addr,\n\t\t\t\t\trte_socket_id(), 0);\n\t\t\tTEST_ASSERT(polling_test_slaves[i] >= 0,\n\t\t\t\t\t\"Failed to create virtual virtual ethdev %s\\n\", slave_name);\n\n\t\t\t/* Configure slave */\n\t\t\tTEST_ASSERT_SUCCESS(configure_ethdev(polling_test_slaves[i], 0, 0),\n\t\t\t\t\t\"Failed to configure virtual ethdev %s(%d)\", slave_name,\n\t\t\t\t\tpolling_test_slaves[i]);\n\t\t}\n\n\t\t/* Add slave to bonded device */\n\t\tTEST_ASSERT_SUCCESS(rte_eth_bond_slave_add(test_params->bonded_port_id,\n\t\t\t\tpolling_test_slaves[i]),\n\t\t\t\t\"Failed to add slave %s(%d) to bonded device %d\",\n\t\t\t\tslave_name, polling_test_slaves[i],\n\t\t\t\ttest_params->bonded_port_id);\n\t}\n\n\t/* Initialize bonded device */\n\tTEST_ASSERT_SUCCESS(configure_ethdev(test_params->bonded_port_id, 1, 1),\n\t\t\t\"Failed to configure bonded device %d\",\n\t\t\ttest_params->bonded_port_id);\n\n\n\t/* Register link status change interrupt callback */\n\trte_eth_dev_callback_register(test_params->bonded_port_id,\n\t\t\tRTE_ETH_EVENT_INTR_LSC, test_bonding_lsc_event_callback,\n\t\t\t&test_params->bonded_port_id);\n\n\t/* link status change callback for first slave link up */\n\ttest_lsc_interrupt_count = 0;\n\n\tvirtual_ethdev_set_link_status(polling_test_slaves[0], 1);\n\n\tTEST_ASSERT_SUCCESS(lsc_timeout(15000), \"timed out waiting for interrupt\");\n\n\n\t/* no link status change callback for second slave link up */\n\ttest_lsc_interrupt_count = 0;\n\n\tvirtual_ethdev_set_link_status(polling_test_slaves[1], 1);\n\n\tTEST_ASSERT_FAIL(lsc_timeout(15000), \"unexpectedly succeeded\");\n\n\t/* link status change callback for both slave links down */\n\ttest_lsc_interrupt_count = 0;\n\n\tvirtual_ethdev_set_link_status(polling_test_slaves[0], 0);\n\tvirtual_ethdev_set_link_status(polling_test_slaves[1], 0);\n\n\tTEST_ASSERT_SUCCESS(lsc_timeout(20000), \"timed out waiting for interrupt\");\n\n\t/* Un-Register link status change interrupt callback */\n\trte_eth_dev_callback_unregister(test_params->bonded_port_id,\n\t\t\tRTE_ETH_EVENT_INTR_LSC, test_bonding_lsc_event_callback,\n\t\t\t&test_params->bonded_port_id);\n\n\n\t/* Clean up and remove slaves from bonded device */\n\tfor (i = 0; i < TEST_RR_POLLING_LINK_STATUS_SLAVE_COUNT; i++) {\n\n\t\tTEST_ASSERT_SUCCESS(\n\t\t\t\trte_eth_bond_slave_remove(test_params->bonded_port_id,\n\t\t\t\t\t\tpolling_test_slaves[i]),\n\t\t\t\t\"Failed to remove slave %d from bonded port (%d)\",\n\t\t\t\tpolling_test_slaves[i], test_params->bonded_port_id);\n\t}\n\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n\n/** Active Backup Mode Tests */\n\nstatic int\ntest_activebackup_tx_burst(void)\n{\n\tint i, pktlen, primary_port, burst_size;\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_eth_stats port_stats;\n\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ACTIVE_BACKUP, 0, 1, 1),\n\t\t\t\"Failed to initialize bonded device with slaves\");\n\n\tinitialize_eth_header(test_params->pkt_eth_hdr,\n\t\t\t(struct ether_addr *)src_mac, (struct ether_addr *)dst_mac_0,\n\t\t\tETHER_TYPE_IPv4, 0, 0);\n\tpktlen = initialize_udp_header(test_params->pkt_udp_hdr, src_port,\n\t\t\tdst_port_0, 16);\n\tpktlen = initialize_ipv4_header(test_params->pkt_ipv4_hdr, src_addr,\n\t\t\tdst_addr_0, pktlen);\n\n\tburst_size = 20 * test_params->bonded_slave_count;\n\n\tTEST_ASSERT(burst_size < MAX_PKT_BURST,\n\t\t\t\"Burst size specified is greater than supported.\");\n\n\t/* Generate a burst of packets to transmit */\n\tTEST_ASSERT_EQUAL(generate_packet_burst(test_params->mbuf_pool, pkts_burst,\n\t\t\ttest_params->pkt_eth_hdr, 0, test_params->pkt_ipv4_hdr, 1,\n\t\t\ttest_params->pkt_udp_hdr, burst_size, PACKET_BURST_GEN_PKT_LEN, 1),\n\t\t\tburst_size,\t\"failed to generate burst correctly\");\n\n\t/* Send burst on bonded port */\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(test_params->bonded_port_id, 0, pkts_burst,\n\t\t\tburst_size), burst_size, \"tx burst failed\");\n\n\t/* Verify bonded port tx stats */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size,\n\t\t\t\"Bonded Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.opackets,\n\t\t\tburst_size);\n\n\tprimary_port = rte_eth_bond_primary_get(test_params->bonded_port_id);\n\n\t/* Verify slave ports tx stats */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\trte_eth_stats_get(test_params->slave_port_ids[i], &port_stats);\n\t\tif (test_params->slave_port_ids[i] == primary_port) {\n\t\t\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size,\n\t\t\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\t\t\ttest_params->bonded_port_id,\n\t\t\t\t\t(unsigned int)port_stats.opackets,\n\t\t\t\t\tburst_size / test_params->bonded_slave_count);\n\t\t} else {\n\t\t\tTEST_ASSERT_EQUAL(port_stats.opackets, 0,\n\t\t\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\t\t\ttest_params->bonded_port_id,\n\t\t\t\t\t(unsigned int)port_stats.opackets, 0);\n\t\t}\n\t}\n\n\t/* Put all slaves down and try and transmit */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\t\ttest_params->slave_port_ids[i], 0);\n\t}\n\n\t/* Send burst on bonded port */\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(test_params->bonded_port_id, 0,\n\t\t\tpkts_burst, burst_size), 0, \"Sending empty burst failed\");\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n#define TEST_ACTIVE_BACKUP_RX_BURST_SLAVE_COUNT (4)\n\nstatic int\ntest_activebackup_rx_burst(void)\n{\n\tstruct rte_mbuf *gen_pkt_burst[MAX_PKT_BURST] = { NULL };\n\tstruct rte_mbuf *rx_pkt_burst[MAX_PKT_BURST] = { NULL };\n\n\tstruct rte_eth_stats port_stats;\n\n\tint primary_port;\n\n\tint i, j, burst_size = 17;\n\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ACTIVE_BACKUP, 0,\n\t\t\tTEST_ACTIVE_BACKUP_RX_BURST_SLAVE_COUNT, 1),\n\t\t\t\"Failed to initialize bonded device with slaves\");\n\n\tprimary_port = rte_eth_bond_primary_get(test_params->bonded_port_id);\n\tTEST_ASSERT(primary_port >= 0,\n\t\t\t\"failed to get primary slave for bonded port (%d)\",\n\t\t\ttest_params->bonded_port_id);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\t/* Generate test bursts of packets to transmit */\n\t\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t\t&gen_pkt_burst[0], burst_size, 0, 1, 0, 0, 0),\n\t\t\t\tburst_size, \"burst generation failed\");\n\n\t\t/* Add rx data to slave */\n\t\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[i],\n\t\t\t\t&gen_pkt_burst[0], burst_size);\n\n\t\t/* Call rx burst on bonded device */\n\t\tTEST_ASSERT_EQUAL(rte_eth_rx_burst(test_params->bonded_port_id, 0,\n\t\t\t\t&rx_pkt_burst[0], MAX_PKT_BURST), burst_size,\n\t\t\t\t\"rte_eth_rx_burst failed\");\n\n\t\tif (test_params->slave_port_ids[i] == primary_port) {\n\t\t\t/* Verify bonded device rx count */\n\t\t\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\t\t\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size,\n\t\t\t\t\t\"Bonded Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\t\t\ttest_params->bonded_port_id,\n\t\t\t\t\t(unsigned int)port_stats.ipackets, burst_size);\n\n\t\t\t/* Verify bonded slave devices rx count */\n\t\t\tfor (j = 0; j < test_params->bonded_slave_count; j++) {\n\t\t\t\trte_eth_stats_get(test_params->slave_port_ids[j], &port_stats);\n\t\t\t\tif (i == j) {\n\t\t\t\t\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size,\n\t\t\t\t\t\t\t\"Slave Port (%d) ipackets value (%u) not as \"\n\t\t\t\t\t\t\t\"expected (%d)\", test_params->slave_port_ids[i],\n\t\t\t\t\t\t\t(unsigned int)port_stats.ipackets, burst_size);\n\t\t\t\t} else {\n\t\t\t\t\tTEST_ASSERT_EQUAL(port_stats.ipackets, 0,\n\t\t\t\t\t\t\t\"Slave Port (%d) ipackets value (%u) not as \"\n\t\t\t\t\t\t\t\"expected (%d)\\n\", test_params->slave_port_ids[i],\n\t\t\t\t\t\t\t(unsigned int)port_stats.ipackets, 0);\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tfor (j = 0; j < test_params->bonded_slave_count; j++) {\n\t\t\t\trte_eth_stats_get(test_params->slave_port_ids[j], &port_stats);\n\t\t\t\tTEST_ASSERT_EQUAL(port_stats.ipackets, 0,\n\t\t\t\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected \"\n\t\t\t\t\t\t\"(%d)\", test_params->slave_port_ids[i],\n\t\t\t\t\t\t(unsigned int)port_stats.ipackets, 0);\n\t\t\t}\n\t\t}\n\n\t\t/* free mbufs */\n\t\tfor (i = 0; i < MAX_PKT_BURST; i++) {\n\t\t\tif (rx_pkt_burst[i] != NULL) {\n\t\t\t\trte_pktmbuf_free(rx_pkt_burst[i]);\n\t\t\t\trx_pkt_burst[i] = NULL;\n\t\t\t}\n\t\t}\n\n\t\t/* reset bonded device stats */\n\t\trte_eth_stats_reset(test_params->bonded_port_id);\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_activebackup_verify_promiscuous_enable_disable(void)\n{\n\tint i, primary_port, promiscuous_en;\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ACTIVE_BACKUP, 0, 4, 1),\n\t\t\t\"Failed to initialize bonded device with slaves\");\n\n\tprimary_port = rte_eth_bond_primary_get(test_params->bonded_port_id);\n\tTEST_ASSERT(primary_port >= 0,\n\t\t\t\"failed to get primary slave for bonded port (%d)\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_promiscuous_enable(test_params->bonded_port_id);\n\n\tTEST_ASSERT_EQUAL(rte_eth_promiscuous_get(test_params->bonded_port_id), 1,\n\t\t\t\"Port (%d) promiscuous mode not enabled\",\n\t\t\ttest_params->bonded_port_id);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tpromiscuous_en = rte_eth_promiscuous_get(\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t\tif (primary_port == test_params->slave_port_ids[i]) {\n\t\t\tTEST_ASSERT_EQUAL(promiscuous_en, 1,\n\t\t\t\t\t\"slave port (%d) promiscuous mode not enabled\",\n\t\t\t\t\ttest_params->slave_port_ids[i]);\n\t\t} else {\n\t\t\tTEST_ASSERT_EQUAL(promiscuous_en, 0,\n\t\t\t\t\t\"slave port (%d) promiscuous mode enabled\",\n\t\t\t\t\ttest_params->slave_port_ids[i]);\n\t\t}\n\n\t}\n\n\trte_eth_promiscuous_disable(test_params->bonded_port_id);\n\n\tTEST_ASSERT_EQUAL(rte_eth_promiscuous_get(test_params->bonded_port_id), 0,\n\t\t\t\"Port (%d) promiscuous mode not disabled\\n\",\n\t\t\ttest_params->bonded_port_id);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tpromiscuous_en = rte_eth_promiscuous_get(\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t\tTEST_ASSERT_EQUAL(promiscuous_en, 0,\n\t\t\t\t\"slave port (%d) promiscuous mode not disabled\\n\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_activebackup_verify_mac_assignment(void)\n{\n\tstruct ether_addr read_mac_addr, expected_mac_addr_0, expected_mac_addr_1;\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &expected_mac_addr_0);\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &expected_mac_addr_1);\n\n\t/* Initialize bonded device with 2 slaves in active backup mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ACTIVE_BACKUP, 0, 2, 1),\n\t\t\t\"Failed to initialize bonded device with slaves\");\n\n\t/* Verify that bonded MACs is that of first slave and that the other slave\n\t * MAC hasn't been changed */\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not as expected\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\t/* change primary and verify that MAC addresses haven't changed */\n\tTEST_ASSERT_EQUAL(rte_eth_bond_primary_set(test_params->bonded_port_id,\n\t\t\ttest_params->slave_port_ids[1]), 0,\n\t\t\t\"Failed to set bonded port (%d) primary port to (%d)\",\n\t\t\ttest_params->bonded_port_id, test_params->slave_port_ids[1]);\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not as expected\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\t/* stop / start bonded device and verify that primary MAC address is\n\t * propagated to bonded device and slaves */\n\n\trte_eth_dev_stop(test_params->bonded_port_id);\n\n\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(test_params->bonded_port_id),\n\t\t\t\"Failed to start device\");\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not as expected\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\t/* Set explicit MAC address */\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_mac_address_set(\n\t\t\ttest_params->bonded_port_id, (struct ether_addr *)bonded_mac),\n\t\t\t\"failed to set MAC address\");\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&bonded_mac, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of bonded port\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not as expected\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&bonded_mac, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of bonded port\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_activebackup_verify_slave_link_status_change_failover(void)\n{\n\tstruct rte_mbuf *pkt_burst[TEST_ACTIVE_BACKUP_RX_BURST_SLAVE_COUNT][MAX_PKT_BURST];\n\tstruct rte_mbuf *rx_pkt_burst[MAX_PKT_BURST] = { NULL };\n\tstruct rte_eth_stats port_stats;\n\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tint i, j, burst_size, slave_count, primary_port;\n\n\tburst_size = 21;\n\n\tmemset(pkt_burst, 0, sizeof(pkt_burst));\n\n\t/* Generate packet burst for testing */\n\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t&pkt_burst[0][0], burst_size, 0, 1, 0, 0, 0), burst_size,\n\t\t\t\"generate_test_burst failed\");\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ACTIVE_BACKUP, 0,\n\t\t\tTEST_ACTIVE_BACKUP_RX_BURST_SLAVE_COUNT, 1),\n\t\t\t\"Failed to initialize bonded device with slaves\");\n\n\t/* Verify Current Slaves Count /Active Slave Count is */\n\tslave_count = rte_eth_bond_slaves_get(test_params->bonded_port_id, slaves,\n\t\t\tRTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(slave_count, 4,\n\t\t\t\"Number of slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, 4);\n\n\tslave_count = rte_eth_bond_active_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(slave_count, 4,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, 4);\n\n\tprimary_port = rte_eth_bond_primary_get(test_params->bonded_port_id);\n\tTEST_ASSERT_EQUAL(primary_port, test_params->slave_port_ids[0],\n\t\t\t\"Primary port not as expected\");\n\n\t/* Bring 2 slaves down and verify active slave count */\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[1], 0);\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[3], 0);\n\n\tTEST_ASSERT_EQUAL(rte_eth_bond_active_slaves_get(\n\t\t\ttest_params->bonded_port_id, slaves, RTE_MAX_ETHPORTS), 2,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, 2);\n\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[1], 1);\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[3], 1);\n\n\n\t/* Bring primary port down, verify that active slave count is 3 and primary\n\t * has changed */\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[0], 0);\n\n\tTEST_ASSERT_EQUAL(rte_eth_bond_active_slaves_get(\n\t\t\ttest_params->bonded_port_id, slaves, RTE_MAX_ETHPORTS),\n\t\t\t3,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, 3);\n\n\tprimary_port = rte_eth_bond_primary_get(test_params->bonded_port_id);\n\tTEST_ASSERT_EQUAL(primary_port, test_params->slave_port_ids[2],\n\t\t\t\"Primary port not as expected\");\n\n\t/* Verify that pkts are sent on new primary slave */\n\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(\n\t\t\ttest_params->bonded_port_id, 0, &pkt_burst[0][0],\n\t\t\tburst_size), burst_size, \"rte_eth_tx_burst failed\");\n\n\trte_eth_stats_get(test_params->slave_port_ids[2], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size,\n\t\t\t\"(%d) port_stats.opackets not as expected\",\n\t\t\ttest_params->slave_port_ids[2]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, 0,\n\t\t\t\"(%d) port_stats.opackets not as expected\\n\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, 0,\n\t\t\t\"(%d) port_stats.opackets not as expected\\n\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[3], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, 0,\n\t\t\t\"(%d) port_stats.opackets not as expected\\n\",\n\t\t\ttest_params->slave_port_ids[3]);\n\n\t/* Generate packet burst for testing */\n\n\tfor (i = 0; i < TEST_ACTIVE_BACKUP_RX_BURST_SLAVE_COUNT; i++) {\n\t\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t\t&pkt_burst[i][0], burst_size, 0, 1, 0, 0, 0), burst_size,\n\t\t\t\t\"generate_test_burst failed\");\n\n\t\tvirtual_ethdev_add_mbufs_to_rx_queue(\n\t\t\ttest_params->slave_port_ids[i], &pkt_burst[i][0], burst_size);\n\t}\n\n\tTEST_ASSERT_EQUAL(rte_eth_rx_burst(\n\t\t\ttest_params->bonded_port_id, 0, rx_pkt_burst, MAX_PKT_BURST),\n\t\t\tburst_size, \"rte_eth_rx_burst\\n\");\n\n\t/* Verify bonded device rx count */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size,\n\t\t\t\"(%d) port_stats.ipackets not as expected\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_stats_get(test_params->slave_port_ids[2], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size,\n\t\t\t\"(%d) port_stats.opackets not as expected\",\n\t\t\ttest_params->slave_port_ids[2]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, 0,\n\t\t\t\"(%d) port_stats.opackets not as expected\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, 0,\n\t\t\t\"(%d) port_stats.opackets not as expected\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[3], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, 0,\n\t\t\t\"(%d) port_stats.opackets not as expected\",\n\t\t\ttest_params->slave_port_ids[3]);\n\n\t/* free mbufs */\n\tfor (i = 0; i < TEST_ACTIVE_BACKUP_RX_BURST_SLAVE_COUNT; i++) {\n\t\tfor (j = 0; j < MAX_PKT_BURST; j++) {\n\t\t\tif (pkt_burst[i][j] != NULL) {\n\t\t\t\trte_pktmbuf_free(pkt_burst[i][j]);\n\t\t\t\tpkt_burst[i][j] = NULL;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n/** Balance Mode Tests */\n\nstatic int\ntest_balance_xmit_policy_configuration(void)\n{\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_ACTIVE_BACKUP, 0, 2, 1),\n\t\t\t\"Failed to initialize_bonded_device_with_slaves.\");\n\n\t/* Invalid port id */\n\tTEST_ASSERT_FAIL(rte_eth_bond_xmit_policy_set(\n\t\t\tINVALID_PORT_ID, BALANCE_XMIT_POLICY_LAYER2),\n\t\t\t\"Expected call to failed as invalid port specified.\");\n\n\t/* Set xmit policy on non bonded device */\n\tTEST_ASSERT_FAIL(rte_eth_bond_xmit_policy_set(\n\t\t\ttest_params->slave_port_ids[0],\tBALANCE_XMIT_POLICY_LAYER2),\n\t\t\t\"Expected call to failed as invalid port specified.\");\n\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_xmit_policy_set(\n\t\t\ttest_params->bonded_port_id, BALANCE_XMIT_POLICY_LAYER2),\n\t\t\t\"Failed to set balance xmit policy.\");\n\n\tTEST_ASSERT_EQUAL(rte_eth_bond_xmit_policy_get(test_params->bonded_port_id),\n\t\t\tBALANCE_XMIT_POLICY_LAYER2, \"balance xmit policy not as expected.\");\n\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_xmit_policy_set(\n\t\t\ttest_params->bonded_port_id, BALANCE_XMIT_POLICY_LAYER23),\n\t\t\t\"Failed to set balance xmit policy.\");\n\n\tTEST_ASSERT_EQUAL(rte_eth_bond_xmit_policy_get(test_params->bonded_port_id),\n\t\t\tBALANCE_XMIT_POLICY_LAYER23,\n\t\t\t\"balance xmit policy not as expected.\");\n\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_xmit_policy_set(\n\t\t\ttest_params->bonded_port_id, BALANCE_XMIT_POLICY_LAYER34),\n\t\t\t\"Failed to set balance xmit policy.\");\n\n\tTEST_ASSERT_EQUAL(rte_eth_bond_xmit_policy_get(test_params->bonded_port_id),\n\t\t\tBALANCE_XMIT_POLICY_LAYER34,\n\t\t\t\"balance xmit policy not as expected.\");\n\n\t/* Invalid port id */\n\tTEST_ASSERT_FAIL(rte_eth_bond_xmit_policy_get(INVALID_PORT_ID),\n\t\t\t\"Expected call to failed as invalid port specified.\");\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n#define TEST_BALANCE_L2_TX_BURST_SLAVE_COUNT (2)\n\nstatic int\ntest_balance_l2_tx_burst(void)\n{\n\tstruct rte_mbuf *pkts_burst[TEST_BALANCE_L2_TX_BURST_SLAVE_COUNT][MAX_PKT_BURST];\n\tint burst_size[TEST_BALANCE_L2_TX_BURST_SLAVE_COUNT] = { 10, 15 };\n\n\tuint16_t pktlen;\n\tint i;\n\tstruct rte_eth_stats port_stats;\n\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BALANCE, 0, TEST_BALANCE_L2_TX_BURST_SLAVE_COUNT, 1),\n\t\t\t\"Failed to initialize_bonded_device_with_slaves.\");\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_xmit_policy_set(\n\t\t\ttest_params->bonded_port_id, BALANCE_XMIT_POLICY_LAYER2),\n\t\t\t\"Failed to set balance xmit policy.\");\n\n\tinitialize_eth_header(test_params->pkt_eth_hdr,\n\t\t\t(struct ether_addr *)src_mac, (struct ether_addr *)dst_mac_0,\n\t\t\tETHER_TYPE_IPv4, 0, 0);\n\tpktlen = initialize_udp_header(test_params->pkt_udp_hdr, src_port,\n\t\t\tdst_port_0, 16);\n\tpktlen = initialize_ipv4_header(test_params->pkt_ipv4_hdr, src_addr,\n\t\t\tdst_addr_0, pktlen);\n\n\t/* Generate a burst 1 of packets to transmit */\n\tTEST_ASSERT_EQUAL(generate_packet_burst(test_params->mbuf_pool, &pkts_burst[0][0],\n\t\t\ttest_params->pkt_eth_hdr, 0, test_params->pkt_ipv4_hdr, 1,\n\t\t\ttest_params->pkt_udp_hdr, burst_size[0],\n\t\t\tPACKET_BURST_GEN_PKT_LEN, 1), burst_size[0],\n\t\t\t\"failed to generate packet burst\");\n\n\tinitialize_eth_header(test_params->pkt_eth_hdr,\n\t\t\t(struct ether_addr *)src_mac, (struct ether_addr *)dst_mac_1,\n\t\t\tETHER_TYPE_IPv4, 0, 0);\n\n\t/* Generate a burst 2 of packets to transmit */\n\tTEST_ASSERT_EQUAL(generate_packet_burst(test_params->mbuf_pool, &pkts_burst[1][0],\n\t\t\ttest_params->pkt_eth_hdr, 0, test_params->pkt_ipv4_hdr, 1,\n\t\t\ttest_params->pkt_udp_hdr, burst_size[1],\n\t\t\tPACKET_BURST_GEN_PKT_LEN, 1), burst_size[1],\n\t\t\t\"failed to generate packet burst\");\n\n\t/* Send burst 1 on bonded port */\n\tfor (i = 0; i < TEST_BALANCE_L2_TX_BURST_SLAVE_COUNT; i++) {\n\t\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(test_params->bonded_port_id, 0,\n\t\t\t\t&pkts_burst[i][0], burst_size[i]),\n\t\t\t\tburst_size[i], \"Failed to transmit packet burst\");\n\t}\n\n\t/* Verify bonded port tx stats */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets,\n\t\t\t(uint64_t)(burst_size[0] + burst_size[1]),\n\t\t\t\"Bonded Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.opackets,\n\t\t\tburst_size[0] + burst_size[1]);\n\n\n\t/* Verify slave ports tx stats */\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size[0],\n\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[0], (unsigned int)port_stats.opackets,\n\t\t\tburst_size[0]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size[1],\n\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\\n\",\n\t\t\ttest_params->slave_port_ids[1], (unsigned int)port_stats.opackets,\n\t\t\tburst_size[1]);\n\n\t/* Put all slaves down and try and transmit */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\n\t\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\t\ttest_params->slave_port_ids[i], 0);\n\t}\n\n\t/* Send burst on bonded port */\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(\n\t\t\ttest_params->bonded_port_id, 0, &pkts_burst[0][0], burst_size[0]),\n\t\t\t0, \"Expected zero packet\");\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\nbalance_l23_tx_burst(uint8_t vlan_enabled, uint8_t ipv4,\n\t\tuint8_t toggle_mac_addr, uint8_t toggle_ip_addr)\n{\n\tint i, burst_size_1, burst_size_2, nb_tx_1, nb_tx_2;\n\n\tstruct rte_mbuf *pkts_burst_1[MAX_PKT_BURST];\n\tstruct rte_mbuf *pkts_burst_2[MAX_PKT_BURST];\n\n\tstruct rte_eth_stats port_stats;\n\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BALANCE, 0, 2, 1),\n\t\t\t\"Failed to initialize_bonded_device_with_slaves.\");\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_xmit_policy_set(\n\t\t\ttest_params->bonded_port_id, BALANCE_XMIT_POLICY_LAYER23),\n\t\t\t\"Failed to set balance xmit policy.\");\n\n\tburst_size_1 = 20;\n\tburst_size_2 = 10;\n\n\tTEST_ASSERT(burst_size_1 < MAX_PKT_BURST || burst_size_2 < MAX_PKT_BURST,\n\t\t\t\"Burst size specified is greater than supported.\");\n\n\t/* Generate test bursts of packets to transmit */\n\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\tpkts_burst_1, burst_size_1, vlan_enabled, ipv4, 0, 0, 0),\n\t\t\tburst_size_1, \"failed to generate packet burst\");\n\n\tTEST_ASSERT_EQUAL(generate_test_burst(pkts_burst_2, burst_size_2, vlan_enabled, ipv4,\n\t\t\ttoggle_mac_addr, toggle_ip_addr, 0), burst_size_2,\n\t\t\t\"failed to generate packet burst\");\n\n\t/* Send burst 1 on bonded port */\n\tnb_tx_1 = rte_eth_tx_burst(test_params->bonded_port_id, 0, pkts_burst_1,\n\t\t\tburst_size_1);\n\tTEST_ASSERT_EQUAL(nb_tx_1, burst_size_1, \"tx burst failed\");\n\n\t/* Send burst 2 on bonded port */\n\tnb_tx_2 = rte_eth_tx_burst(test_params->bonded_port_id, 0, pkts_burst_2,\n\t\t\tburst_size_2);\n\tTEST_ASSERT_EQUAL(nb_tx_2, burst_size_2, \"tx burst failed\");\n\n\t/* Verify bonded port tx stats */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)(nb_tx_1 + nb_tx_2),\n\t\t\t\"Bonded Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.opackets,\n\t\t\tnb_tx_1 + nb_tx_2);\n\n\t/* Verify slave ports tx stats */\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)nb_tx_1,\n\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[0], (unsigned int)port_stats.opackets,\n\t\t\tnb_tx_1);\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)nb_tx_2,\n\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[1], (unsigned int)port_stats.opackets,\n\t\t\tnb_tx_2);\n\n\t/* Put all slaves down and try and transmit */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\n\t\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\t\ttest_params->slave_port_ids[i], 0);\n\t}\n\n\t/* Send burst on bonded port */\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(\n\t\t\ttest_params->bonded_port_id, 0, pkts_burst_1,\n\t\t\tburst_size_1), 0, \"Expected zero packet\");\n\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_balance_l23_tx_burst_ipv4_toggle_ip_addr(void)\n{\n\treturn balance_l23_tx_burst(0, 1, 1, 0);\n}\n\nstatic int\ntest_balance_l23_tx_burst_vlan_ipv4_toggle_ip_addr(void)\n{\n\treturn balance_l23_tx_burst(1, 1, 0, 1);\n}\n\nstatic int\ntest_balance_l23_tx_burst_ipv6_toggle_ip_addr(void)\n{\n\treturn balance_l23_tx_burst(0, 0, 0, 1);\n}\n\nstatic int\ntest_balance_l23_tx_burst_vlan_ipv6_toggle_ip_addr(void)\n{\n\treturn balance_l23_tx_burst(1, 0, 0, 1);\n}\n\nstatic int\ntest_balance_l23_tx_burst_toggle_mac_addr(void)\n{\n\treturn balance_l23_tx_burst(0, 0, 1, 0);\n}\n\nstatic int\nbalance_l34_tx_burst(uint8_t vlan_enabled, uint8_t ipv4,\n\t\tuint8_t toggle_mac_addr, uint8_t toggle_ip_addr,\n\t\tuint8_t toggle_udp_port)\n{\n\tint i, burst_size_1, burst_size_2, nb_tx_1, nb_tx_2;\n\n\tstruct rte_mbuf *pkts_burst_1[MAX_PKT_BURST];\n\tstruct rte_mbuf *pkts_burst_2[MAX_PKT_BURST];\n\n\tstruct rte_eth_stats port_stats;\n\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BALANCE, 0, 2, 1),\n\t\t\t\"Failed to initialize_bonded_device_with_slaves.\");\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_xmit_policy_set(\n\t\t\ttest_params->bonded_port_id, BALANCE_XMIT_POLICY_LAYER34),\n\t\t\t\"Failed to set balance xmit policy.\");\n\n\tburst_size_1 = 20;\n\tburst_size_2 = 10;\n\n\tTEST_ASSERT(burst_size_1 < MAX_PKT_BURST || burst_size_2 < MAX_PKT_BURST,\n\t\t\t\"Burst size specified is greater than supported.\");\n\n\t/* Generate test bursts of packets to transmit */\n\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\tpkts_burst_1, burst_size_1, vlan_enabled, ipv4, 0, 0, 0),\n\t\t\tburst_size_1, \"failed to generate burst\");\n\n\tTEST_ASSERT_EQUAL(generate_test_burst(pkts_burst_2, burst_size_2,\n\t\t\tvlan_enabled, ipv4, toggle_mac_addr, toggle_ip_addr,\n\t\t\ttoggle_udp_port), burst_size_2, \"failed to generate burst\");\n\n\t/* Send burst 1 on bonded port */\n\tnb_tx_1 = rte_eth_tx_burst(test_params->bonded_port_id, 0, pkts_burst_1,\n\t\t\tburst_size_1);\n\tTEST_ASSERT_EQUAL(nb_tx_1, burst_size_1, \"tx burst failed\");\n\n\t/* Send burst 2 on bonded port */\n\tnb_tx_2 = rte_eth_tx_burst(test_params->bonded_port_id, 0, pkts_burst_2,\n\t\t\tburst_size_2);\n\tTEST_ASSERT_EQUAL(nb_tx_2, burst_size_2, \"tx burst failed\");\n\n\n\t/* Verify bonded port tx stats */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)(nb_tx_1 + nb_tx_2),\n\t\t\t\"Bonded Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.opackets,\n\t\t\tnb_tx_1 + nb_tx_2);\n\n\t/* Verify slave ports tx stats */\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)nb_tx_1,\n\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[0], (unsigned int)port_stats.opackets,\n\t\t\tnb_tx_1);\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)nb_tx_2,\n\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[1], (unsigned int)port_stats.opackets,\n\t\t\tnb_tx_2);\n\n\t/* Put all slaves down and try and transmit */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\n\t\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\t\ttest_params->slave_port_ids[i], 0);\n\t}\n\n\t/* Send burst on bonded port */\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(\n\t\t\ttest_params->bonded_port_id, 0, pkts_burst_1,\n\t\t\tburst_size_1), 0, \"Expected zero packet\");\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_balance_l34_tx_burst_ipv4_toggle_ip_addr(void)\n{\n\treturn balance_l34_tx_burst(0, 1, 0, 1, 0);\n}\n\nstatic int\ntest_balance_l34_tx_burst_ipv4_toggle_udp_port(void)\n{\n\treturn balance_l34_tx_burst(0, 1, 0, 0, 1);\n}\n\nstatic int\ntest_balance_l34_tx_burst_vlan_ipv4_toggle_ip_addr(void)\n{\n\treturn balance_l34_tx_burst(1, 1, 0, 1, 0);\n}\n\nstatic int\ntest_balance_l34_tx_burst_ipv6_toggle_ip_addr(void)\n{\n\treturn balance_l34_tx_burst(0, 0, 0, 1, 0);\n}\n\nstatic int\ntest_balance_l34_tx_burst_vlan_ipv6_toggle_ip_addr(void)\n{\n\treturn balance_l34_tx_burst(1, 0, 0, 1, 0);\n}\n\nstatic int\ntest_balance_l34_tx_burst_ipv6_toggle_udp_port(void)\n{\n\treturn balance_l34_tx_burst(0, 0, 0, 0, 1);\n}\n\n#define TEST_BAL_SLAVE_TX_FAIL_SLAVE_COUNT\t\t\t(2)\n#define TEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_1\t\t\t(40)\n#define TEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_2\t\t\t(20)\n#define TEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT\t\t(25)\n#define TEST_BAL_SLAVE_TX_FAIL_FAILING_SLAVE_IDX\t(0)\n\nstatic int\ntest_balance_tx_burst_slave_tx_fail(void)\n{\n\tstruct rte_mbuf *pkts_burst_1[TEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_1];\n\tstruct rte_mbuf *pkts_burst_2[TEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_2];\n\n\tstruct rte_mbuf *expected_fail_pkts[TEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT];\n\n\tstruct rte_eth_stats port_stats;\n\n\tint i, first_tx_fail_idx, tx_count_1, tx_count_2;\n\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BALANCE, 0,\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_SLAVE_COUNT, 1),\n\t\t\t\"Failed to intialise bonded device\");\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_xmit_policy_set(\n\t\t\ttest_params->bonded_port_id, BALANCE_XMIT_POLICY_LAYER2),\n\t\t\t\"Failed to set balance xmit policy.\");\n\n\n\t/* Generate test bursts for transmission */\n\tTEST_ASSERT_EQUAL(generate_test_burst(pkts_burst_1,\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_1, 0, 0, 0, 0, 0),\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_1,\n\t\t\t\"Failed to generate test packet burst 1\");\n\n\tfirst_tx_fail_idx = TEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_1 -\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT;\n\n\t/* copy mbuf referneces for expected transmission failures */\n\tfor (i = 0; i < TEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT; i++)\n\t\texpected_fail_pkts[i] = pkts_burst_1[i + first_tx_fail_idx];\n\n\tTEST_ASSERT_EQUAL(generate_test_burst(pkts_burst_2,\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_2, 0, 0, 1, 0, 0),\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_2,\n\t\t\t\"Failed to generate test packet burst 2\");\n\n\n\t/* Set virtual slave TEST_BAL_SLAVE_TX_FAIL_FAILING_SLAVE_IDX to only fail\n\t * transmission of TEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT packets of burst */\n\tvirtual_ethdev_tx_burst_fn_set_success(\n\t\t\ttest_params->slave_port_ids[TEST_BAL_SLAVE_TX_FAIL_FAILING_SLAVE_IDX],\n\t\t\t0);\n\n\tvirtual_ethdev_tx_burst_fn_set_tx_pkt_fail_count(\n\t\t\ttest_params->slave_port_ids[TEST_BAL_SLAVE_TX_FAIL_FAILING_SLAVE_IDX],\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT);\n\n\n\t/* Transmit burst 1 */\n\ttx_count_1 = rte_eth_tx_burst(test_params->bonded_port_id, 0, pkts_burst_1,\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_1);\n\n\tTEST_ASSERT_EQUAL(tx_count_1, TEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_1 -\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT,\n\t\t\t\"Transmitted (%d) packets, expected to transmit (%d) packets\",\n\t\t\ttx_count_1, TEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_1 -\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT);\n\n\t/* Verify that failed packet are expected failed packets */\n\tfor (i = 0; i < TEST_RR_SLAVE_TX_FAIL_PACKETS_COUNT; i++) {\n\t\tTEST_ASSERT_EQUAL(expected_fail_pkts[i], pkts_burst_1[i + tx_count_1],\n\t\t\t\t\"expected mbuf (%d) pointer %p not expected pointer %p\",\n\t\t\t\ti, expected_fail_pkts[i], pkts_burst_1[i + tx_count_1]);\n\t}\n\n\t/* Transmit burst 2 */\n\ttx_count_2 = rte_eth_tx_burst(test_params->bonded_port_id, 0, pkts_burst_2,\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_2);\n\n\tTEST_ASSERT_EQUAL(tx_count_2, TEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_2,\n\t\t\t\"Transmitted (%d) packets, expected to transmit (%d) packets\",\n\t\t\ttx_count_2, TEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_2);\n\n\n\t/* Verify bonded port tx stats */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\n\tTEST_ASSERT_EQUAL(port_stats.opackets,\n\t\t\t(uint64_t)((TEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_1 -\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT) +\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_2),\n\t\t\t\"Bonded Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.opackets,\n\t\t\t(TEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_1 -\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT) +\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_2);\n\n\t/* Verify slave ports tx stats */\n\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)\n\t\t\t\tTEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_1 -\n\t\t\t\tTEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT,\n\t\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\t\ttest_params->slave_port_ids[0],\n\t\t\t\t(unsigned int)port_stats.opackets,\n\t\t\t\tTEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_1 -\n\t\t\t\tTEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT);\n\n\n\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\n\tTEST_ASSERT_EQUAL(port_stats.opackets,\n\t\t\t\t(uint64_t)TEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_2,\n\t\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\t\ttest_params->slave_port_ids[1],\n\t\t\t\t(unsigned int)port_stats.opackets,\n\t\t\t\tTEST_BAL_SLAVE_TX_FAIL_BURST_SIZE_2);\n\n\t/* Verify that all mbufs have a ref value of zero */\n\tTEST_ASSERT_SUCCESS(verify_mbufs_ref_count(&pkts_burst_1[tx_count_1],\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT, 1),\n\t\t\t\"mbufs refcnts not as expected\");\n\n\tfree_mbufs(&pkts_burst_1[tx_count_1],\n\t\t\tTEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT);\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n#define TEST_BALANCE_RX_BURST_SLAVE_COUNT (3)\n\nstatic int\ntest_balance_rx_burst(void)\n{\n\tstruct rte_mbuf *gen_pkt_burst[TEST_BALANCE_RX_BURST_SLAVE_COUNT][MAX_PKT_BURST];\n\n\tstruct rte_mbuf *rx_pkt_burst[MAX_PKT_BURST] = { NULL };\n\tstruct rte_eth_stats port_stats;\n\n\tint burst_size[TEST_BALANCE_RX_BURST_SLAVE_COUNT] = { 10, 5, 30 };\n\tint i, j;\n\n\tmemset(gen_pkt_burst, 0, sizeof(gen_pkt_burst));\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BALANCE, 0, 3, 1),\n\t\t\t\"Failed to intialise bonded device\");\n\n\t/* Generate test bursts of packets to transmit */\n\tfor (i = 0; i < TEST_BALANCE_RX_BURST_SLAVE_COUNT; i++) {\n\t\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t\t&gen_pkt_burst[i][0], burst_size[i], 0, 0, 1,\n\t\t\t\t0, 0), burst_size[i],\n\t\t\t\t\"failed to generate packet burst\");\n\t}\n\n\t/* Add rx data to slaves */\n\tfor (i = 0; i < TEST_BALANCE_RX_BURST_SLAVE_COUNT; i++) {\n\t\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[i],\n\t\t\t\t&gen_pkt_burst[i][0], burst_size[i]);\n\t}\n\n\t/* Call rx burst on bonded device */\n\t/* Send burst on bonded port */\n\tTEST_ASSERT_EQUAL(rte_eth_rx_burst(test_params->bonded_port_id, 0,\n\t\t\trx_pkt_burst, MAX_PKT_BURST),\n\t\t\tburst_size[0] + burst_size[1] + burst_size[2],\n\t\t\t\"balance rx burst failed\\n\");\n\n\t/* Verify bonded device rx count */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets,\n\t\t\t(uint64_t)(burst_size[0] + burst_size[1] + burst_size[2]),\n\t\t\t\"Bonded Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.ipackets,\n\t\t\tburst_size[0] + burst_size[1] + burst_size[2]);\n\n\n\t/* Verify bonded slave devices rx counts */\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size[0],\n\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\t\ttest_params->slave_port_ids[0],\n\t\t\t\t(unsigned int)port_stats.ipackets, burst_size[0]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size[1],\n\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[1], (unsigned int)port_stats.ipackets,\n\t\t\tburst_size[1]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[2], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size[2],\n\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[2], (unsigned int)port_stats.ipackets,\n\t\t\tburst_size[2]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[3], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, 0,\n\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[3],\t(unsigned int)port_stats.ipackets,\n\t\t\t0);\n\n\t/* free mbufs */\n\tfor (i = 0; i < TEST_BALANCE_RX_BURST_SLAVE_COUNT; i++) {\n\t\tfor (j = 0; j < MAX_PKT_BURST; j++) {\n\t\t\tif (gen_pkt_burst[i][j] != NULL) {\n\t\t\t\trte_pktmbuf_free(gen_pkt_burst[i][j]);\n\t\t\t\tgen_pkt_burst[i][j] = NULL;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_balance_verify_promiscuous_enable_disable(void)\n{\n\tint i;\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BALANCE, 0, 4, 1),\n\t\t\t\"Failed to intialise bonded device\");\n\n\trte_eth_promiscuous_enable(test_params->bonded_port_id);\n\n\tTEST_ASSERT_EQUAL(rte_eth_promiscuous_get(test_params->bonded_port_id), 1,\n\t\t\t\"Port (%d) promiscuous mode not enabled\",\n\t\t\ttest_params->bonded_port_id);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tTEST_ASSERT_EQUAL(rte_eth_promiscuous_get(\n\t\t\t\ttest_params->slave_port_ids[i]), 1,\n\t\t\t\t\"Port (%d) promiscuous mode not enabled\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t}\n\n\trte_eth_promiscuous_disable(test_params->bonded_port_id);\n\n\tTEST_ASSERT_EQUAL(rte_eth_promiscuous_get(test_params->bonded_port_id), 0,\n\t\t\t\"Port (%d) promiscuous mode not disabled\",\n\t\t\ttest_params->bonded_port_id);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tTEST_ASSERT_EQUAL(rte_eth_promiscuous_get(\n\t\t\t\ttest_params->slave_port_ids[i]), 0,\n\t\t\t\t\"Port (%d) promiscuous mode not disabled\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_balance_verify_mac_assignment(void)\n{\n\tstruct ether_addr read_mac_addr, expected_mac_addr_0, expected_mac_addr_1;\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &expected_mac_addr_0);\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &expected_mac_addr_1);\n\n\t/* Initialize bonded device with 2 slaves in active backup mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BALANCE, 0, 2, 1),\n\t\t\t\"Failed to intialise bonded device\");\n\n\t/* Verify that bonded MACs is that of first slave and that the other slave\n\t * MAC hasn't been changed */\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\t/* change primary and verify that MAC addresses haven't changed */\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_primary_set(test_params->bonded_port_id,\n\t\t\ttest_params->slave_port_ids[1]),\n\t\t\t\"Failed to set bonded port (%d) primary port to (%d)\\n\",\n\t\t\ttest_params->bonded_port_id, test_params->slave_port_ids[1]);\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\t/* stop / start bonded device and verify that primary MAC address is\n\t * propagated to bonded device and slaves */\n\n\trte_eth_dev_stop(test_params->bonded_port_id);\n\n\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(test_params->bonded_port_id),\n\t\t\t\"Failed to start bonded device\");\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\t/* Set explicit MAC address */\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_mac_address_set(\n\t\t\ttest_params->bonded_port_id, (struct ether_addr *)bonded_mac),\n\t\t\t\"failed to set MAC\");\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&bonded_mac, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of bonded port\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&bonded_mac, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not as expected\\n\",\n\t\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&bonded_mac, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of bonded port\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n#define TEST_BALANCE_LINK_STATUS_SLAVE_COUNT (4)\n\nstatic int\ntest_balance_verify_slave_link_status_change_behaviour(void)\n{\n\tstruct rte_mbuf *pkt_burst[TEST_BALANCE_LINK_STATUS_SLAVE_COUNT][MAX_PKT_BURST];\n\tstruct rte_mbuf *rx_pkt_burst[MAX_PKT_BURST] = { NULL };\n\tstruct rte_eth_stats port_stats;\n\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tint i, j, burst_size, slave_count;\n\n\tmemset(pkt_burst, 0, sizeof(pkt_burst));\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BALANCE, 0, TEST_BALANCE_LINK_STATUS_SLAVE_COUNT, 1),\n\t\t\t\"Failed to intialise bonded device\");\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_xmit_policy_set(\n\t\t\ttest_params->bonded_port_id, BALANCE_XMIT_POLICY_LAYER2),\n\t\t\t\"Failed to set balance xmit policy.\");\n\n\n\t/* Verify Current Slaves Count /Active Slave Count is */\n\tslave_count = rte_eth_bond_slaves_get(test_params->bonded_port_id, slaves,\n\t\t\tRTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(slave_count, TEST_BALANCE_LINK_STATUS_SLAVE_COUNT,\n\t\t\t\"Number of slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, TEST_BALANCE_LINK_STATUS_SLAVE_COUNT);\n\n\tslave_count = rte_eth_bond_active_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(slave_count, TEST_BALANCE_LINK_STATUS_SLAVE_COUNT,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, TEST_BALANCE_LINK_STATUS_SLAVE_COUNT);\n\n\t/* Set 2 slaves link status to down */\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[1], 0);\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[3], 0);\n\n\tTEST_ASSERT_EQUAL(rte_eth_bond_active_slaves_get(\n\t\t\ttest_params->bonded_port_id, slaves, RTE_MAX_ETHPORTS), 2,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, 2);\n\n\t/* Send to sets of packet burst and verify that they are balanced across\n\t * slaves */\n\tburst_size = 21;\n\n\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t&pkt_burst[0][0], burst_size, 0, 1, 0, 0, 0), burst_size,\n\t\t\t\"generate_test_burst failed\");\n\n\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t&pkt_burst[1][0], burst_size, 0, 1, 1, 0, 0), burst_size,\n\t\t\t\"generate_test_burst failed\");\n\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(\n\t\t\ttest_params->bonded_port_id, 0, &pkt_burst[0][0], burst_size),\n\t\t\tburst_size, \"rte_eth_tx_burst failed\");\n\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(\n\t\t\ttest_params->bonded_port_id, 0, &pkt_burst[1][0], burst_size),\n\t\t\tburst_size, \"rte_eth_tx_burst failed\");\n\n\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)(burst_size + burst_size),\n\t\t\t\"(%d) port_stats.opackets (%d) not as expected (%d).\",\n\t\t\ttest_params->bonded_port_id, (int)port_stats.opackets,\n\t\t\tburst_size + burst_size);\n\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size,\n\t\t\t\"(%d) port_stats.opackets (%d) not as expected (%d).\",\n\t\t\ttest_params->slave_port_ids[0], (int)port_stats.opackets,\n\t\t\tburst_size);\n\n\trte_eth_stats_get(test_params->slave_port_ids[2], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size,\n\t\t\t\"(%d) port_stats.opackets (%d) not as expected (%d).\",\n\t\t\ttest_params->slave_port_ids[2], (int)port_stats.opackets,\n\t\t\tburst_size);\n\n\t/* verify that all packets get send on primary slave when no other slaves\n\t * are available */\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[2], 0);\n\n\tTEST_ASSERT_EQUAL(rte_eth_bond_active_slaves_get(\n\t\t\ttest_params->bonded_port_id, slaves, RTE_MAX_ETHPORTS), 1,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, 1);\n\n\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t&pkt_burst[1][0], burst_size, 0, 1, 1, 0, 0), burst_size,\n\t\t\t\"generate_test_burst failed\");\n\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(\n\t\t\ttest_params->bonded_port_id, 0, &pkt_burst[1][0], burst_size),\n\t\t\tburst_size, \"rte_eth_tx_burst failed\");\n\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets,\n\t\t\t(uint64_t)(burst_size + burst_size + burst_size),\n\t\t\t\"(%d) port_stats.opackets (%d) not as expected (%d).\\n\",\n\t\t\ttest_params->bonded_port_id, (int)port_stats.opackets,\n\t\t\tburst_size + burst_size + burst_size);\n\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)(burst_size + burst_size),\n\t\t\t\"(%d) port_stats.opackets (%d) not as expected (%d).\",\n\t\t\ttest_params->slave_port_ids[0], (int)port_stats.opackets,\n\t\t\tburst_size + burst_size);\n\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[0], 0);\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[1], 1);\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[2], 1);\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[3], 1);\n\n\tfor (i = 0; i < TEST_BALANCE_LINK_STATUS_SLAVE_COUNT; i++) {\n\t\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t\t&pkt_burst[i][0], burst_size, 0, 1, 0, 0, 0), burst_size,\n\t\t\t\t\"Failed to generate packet burst\");\n\n\t\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[i],\n\t\t\t\t&pkt_burst[i][0], burst_size);\n\t}\n\n\t/* Verify that pkts are not received on slaves with link status down */\n\n\trte_eth_rx_burst(test_params->bonded_port_id, 0, rx_pkt_burst,\n\t\t\tMAX_PKT_BURST);\n\n\t/* Verify bonded device rx count */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)(burst_size * 3),\n\t\t\t\"(%d) port_stats.ipackets (%d) not as expected (%d)\\n\",\n\t\t\ttest_params->bonded_port_id, (int)port_stats.ipackets,\n\t\t\tburst_size * 3);\n\n\t/* free mbufs allocate for rx testing */\n\tfor (i = 0; i < TEST_BALANCE_RX_BURST_SLAVE_COUNT; i++) {\n\t\tfor (j = 0; j < MAX_PKT_BURST; j++) {\n\t\t\tif (pkt_burst[i][j] != NULL) {\n\t\t\t\trte_pktmbuf_free(pkt_burst[i][j]);\n\t\t\t\tpkt_burst[i][j] = NULL;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_broadcast_tx_burst(void)\n{\n\tint i, pktlen, burst_size;\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\n\tstruct rte_eth_stats port_stats;\n\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BROADCAST, 0, 2, 1),\n\t\t\t\"Failed to intialise bonded device\");\n\n\tinitialize_eth_header(test_params->pkt_eth_hdr,\n\t\t\t(struct ether_addr *)src_mac, (struct ether_addr *)dst_mac_0,\n\t\t\tETHER_TYPE_IPv4, 0, 0);\n\n\tpktlen = initialize_udp_header(test_params->pkt_udp_hdr, src_port,\n\t\t\tdst_port_0, 16);\n\tpktlen = initialize_ipv4_header(test_params->pkt_ipv4_hdr, src_addr,\n\t\t\tdst_addr_0, pktlen);\n\n\tburst_size = 20 * test_params->bonded_slave_count;\n\n\tTEST_ASSERT(burst_size < MAX_PKT_BURST,\n\t\t\t\"Burst size specified is greater than supported.\");\n\n\t/* Generate a burst of packets to transmit */\n\tTEST_ASSERT_EQUAL(generate_packet_burst(test_params->mbuf_pool,\n\t\t\tpkts_burst,\ttest_params->pkt_eth_hdr, 0, test_params->pkt_ipv4_hdr,\n\t\t\t1, test_params->pkt_udp_hdr, burst_size, PACKET_BURST_GEN_PKT_LEN,\n\t\t\t1), burst_size, \"Failed to generate packet burst\");\n\n\t/* Send burst on bonded port */\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(test_params->bonded_port_id, 0,\n\t\t\tpkts_burst, burst_size), burst_size,\n\t\t\t\"Bonded Port (%d) rx burst failed, packets transmitted value \"\n\t\t\t\"not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, burst_size);\n\n\t/* Verify bonded port tx stats */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets,\n\t\t\t(uint64_t)burst_size * test_params->bonded_slave_count,\n\t\t\t\"Bonded Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.opackets,\n\t\t\tburst_size);\n\n\t/* Verify slave ports tx stats */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\trte_eth_stats_get(test_params->slave_port_ids[i], &port_stats);\n\t\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size,\n\t\t\t\t\"Slave Port (%d) opackets value (%u) not as expected (%d)\\n\",\n\t\t\t\ttest_params->bonded_port_id,\n\t\t\t\t(unsigned int)port_stats.opackets, burst_size);\n\t}\n\n\t/* Put all slaves down and try and transmit */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\n\t\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\t\ttest_params->slave_port_ids[i], 0);\n\t}\n\n\t/* Send burst on bonded port */\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(\n\t\t\ttest_params->bonded_port_id, 0, pkts_burst, burst_size), 0,\n\t\t\t\"transmitted an unexpected number of packets\");\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n\n#define TEST_BCAST_SLAVE_TX_FAIL_SLAVE_COUNT\t\t(3)\n#define TEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE\t\t\t(40)\n#define TEST_BCAST_SLAVE_TX_FAIL_MAX_PACKETS_COUNT\t(15)\n#define TEST_BCAST_SLAVE_TX_FAIL_MIN_PACKETS_COUNT\t(10)\n\nstatic int\ntest_broadcast_tx_burst_slave_tx_fail(void)\n{\n\tstruct rte_mbuf *pkts_burst[TEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE];\n\tstruct rte_mbuf *expected_fail_pkts[TEST_BCAST_SLAVE_TX_FAIL_MIN_PACKETS_COUNT];\n\n\tstruct rte_eth_stats port_stats;\n\n\tint i, tx_count;\n\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BROADCAST, 0,\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_SLAVE_COUNT, 1),\n\t\t\t\"Failed to intialise bonded device\");\n\n\t/* Generate test bursts for transmission */\n\tTEST_ASSERT_EQUAL(generate_test_burst(pkts_burst,\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE, 0, 0, 0, 0, 0),\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE,\n\t\t\t\"Failed to generate test packet burst\");\n\n\tfor (i = 0; i < TEST_BCAST_SLAVE_TX_FAIL_MIN_PACKETS_COUNT; i++) {\n\t\texpected_fail_pkts[i] = pkts_burst[TEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MIN_PACKETS_COUNT + i];\n\t}\n\n\t/* Set virtual slave TEST_BAL_SLAVE_TX_FAIL_FAILING_SLAVE_IDX to only fail\n\t * transmission of TEST_BAL_SLAVE_TX_FAIL_PACKETS_COUNT packets of burst */\n\tvirtual_ethdev_tx_burst_fn_set_success(\n\t\t\ttest_params->slave_port_ids[0],\n\t\t\t0);\n\tvirtual_ethdev_tx_burst_fn_set_success(\n\t\t\ttest_params->slave_port_ids[1],\n\t\t\t0);\n\tvirtual_ethdev_tx_burst_fn_set_success(\n\t\t\ttest_params->slave_port_ids[2],\n\t\t\t0);\n\n\tvirtual_ethdev_tx_burst_fn_set_tx_pkt_fail_count(\n\t\t\ttest_params->slave_port_ids[0],\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MAX_PACKETS_COUNT);\n\n\tvirtual_ethdev_tx_burst_fn_set_tx_pkt_fail_count(\n\t\t\ttest_params->slave_port_ids[1],\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MIN_PACKETS_COUNT);\n\n\tvirtual_ethdev_tx_burst_fn_set_tx_pkt_fail_count(\n\t\t\ttest_params->slave_port_ids[2],\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MAX_PACKETS_COUNT);\n\n\t/* Transmit burst */\n\ttx_count = rte_eth_tx_burst(test_params->bonded_port_id, 0, pkts_burst,\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE);\n\n\tTEST_ASSERT_EQUAL(tx_count, TEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MIN_PACKETS_COUNT,\n\t\t\t\"Transmitted (%d) packets, expected to transmit (%d) packets\",\n\t\t\ttx_count, TEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MIN_PACKETS_COUNT);\n\n\t/* Verify that failed packet are expected failed packets */\n\tfor (i = 0; i < TEST_BCAST_SLAVE_TX_FAIL_MIN_PACKETS_COUNT; i++) {\n\t\tTEST_ASSERT_EQUAL(expected_fail_pkts[i], pkts_burst[i + tx_count],\n\t\t\t\t\"expected mbuf (%d) pointer %p not expected pointer %p\",\n\t\t\t\ti, expected_fail_pkts[i], pkts_burst[i + tx_count]);\n\t}\n\n\t/* Verify slave ports tx stats */\n\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\n\tTEST_ASSERT_EQUAL(port_stats.opackets,\n\t\t\t(uint64_t)TEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MAX_PACKETS_COUNT,\n\t\t\t\"Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.opackets,\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MAX_PACKETS_COUNT);\n\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\n\tTEST_ASSERT_EQUAL(port_stats.opackets,\n\t\t\t(uint64_t)TEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MIN_PACKETS_COUNT,\n\t\t\t\"Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.opackets,\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MIN_PACKETS_COUNT);\n\n\trte_eth_stats_get(test_params->slave_port_ids[2], &port_stats);\n\n\tTEST_ASSERT_EQUAL(port_stats.opackets,\n\t\t\t(uint64_t)TEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MAX_PACKETS_COUNT,\n\t\t\t\"Port (%d) opackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.opackets,\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_BURST_SIZE -\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MAX_PACKETS_COUNT);\n\n\n\t/* Verify that all mbufs who transmission failed have a ref value of one */\n\tTEST_ASSERT_SUCCESS(verify_mbufs_ref_count(&pkts_burst[tx_count],\n\t\t\tTEST_BCAST_SLAVE_TX_FAIL_MIN_PACKETS_COUNT, 1),\n\t\t\t\"mbufs refcnts not as expected\");\n\n\tfree_mbufs(&pkts_burst[tx_count],\n\t\tTEST_BCAST_SLAVE_TX_FAIL_MIN_PACKETS_COUNT);\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n#define BROADCAST_RX_BURST_NUM_OF_SLAVES (3)\n\nstatic int\ntest_broadcast_rx_burst(void)\n{\n\tstruct rte_mbuf *gen_pkt_burst[BROADCAST_RX_BURST_NUM_OF_SLAVES][MAX_PKT_BURST];\n\n\tstruct rte_mbuf *rx_pkt_burst[MAX_PKT_BURST] = { NULL };\n\tstruct rte_eth_stats port_stats;\n\n\tint burst_size[BROADCAST_RX_BURST_NUM_OF_SLAVES] = { 10, 5, 30 };\n\tint i, j;\n\n\tmemset(gen_pkt_burst, 0, sizeof(gen_pkt_burst));\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BROADCAST, 0, 3, 1),\n\t\t\t\"Failed to intialise bonded device\");\n\n\t/* Generate test bursts of packets to transmit */\n\tfor (i = 0; i < BROADCAST_RX_BURST_NUM_OF_SLAVES; i++) {\n\t\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t\t&gen_pkt_burst[i][0], burst_size[i], 0, 0, 1, 0, 0),\n\t\t\t\tburst_size[i], \"failed to generate packet burst\");\n\t}\n\n\t/* Add rx data to slave 0 */\n\tfor (i = 0; i < BROADCAST_RX_BURST_NUM_OF_SLAVES; i++) {\n\t\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[i],\n\t\t\t\t&gen_pkt_burst[i][0], burst_size[i]);\n\t}\n\n\n\t/* Call rx burst on bonded device */\n\t/* Send burst on bonded port */\n\tTEST_ASSERT_EQUAL(rte_eth_rx_burst(\n\t\t\ttest_params->bonded_port_id, 0, rx_pkt_burst, MAX_PKT_BURST),\n\t\t\tburst_size[0] + burst_size[1] + burst_size[2],\n\t\t\t\"rx burst failed\");\n\n\t/* Verify bonded device rx count */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets,\n\t\t\t(uint64_t)(burst_size[0] + burst_size[1] + burst_size[2]),\n\t\t\t\"Bonded Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats.ipackets,\n\t\t\tburst_size[0] + burst_size[1] + burst_size[2]);\n\n\n\t/* Verify bonded slave devices rx counts */\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size[0],\n\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[0], (unsigned int)port_stats.ipackets,\n\t\t\tburst_size[0]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size[1],\n\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[0], (unsigned int)port_stats.ipackets,\n\t\t\tburst_size[1]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[2], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size[2],\n\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[2], (unsigned int)port_stats.ipackets,\n\t\t\tburst_size[2]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[3], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, 0,\n\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\",\n\t\t\ttest_params->slave_port_ids[3], (unsigned int)port_stats.ipackets,\n\t\t\t0);\n\n\t/* free mbufs allocate for rx testing */\n\tfor (i = 0; i < BROADCAST_RX_BURST_NUM_OF_SLAVES; i++) {\n\t\tfor (j = 0; j < MAX_PKT_BURST; j++) {\n\t\t\tif (gen_pkt_burst[i][j] != NULL) {\n\t\t\t\trte_pktmbuf_free(gen_pkt_burst[i][j]);\n\t\t\t\tgen_pkt_burst[i][j] = NULL;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_broadcast_verify_promiscuous_enable_disable(void)\n{\n\tint i;\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BROADCAST, 0, 4, 1),\n\t\t\t\"Failed to intialise bonded device\");\n\n\trte_eth_promiscuous_enable(test_params->bonded_port_id);\n\n\n\tTEST_ASSERT_EQUAL(rte_eth_promiscuous_get(test_params->bonded_port_id), 1,\n\t\t\t\"Port (%d) promiscuous mode not enabled\",\n\t\t\ttest_params->bonded_port_id);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tTEST_ASSERT_EQUAL(rte_eth_promiscuous_get(\n\t\t\t\ttest_params->slave_port_ids[i]), 1,\n\t\t\t\t\"Port (%d) promiscuous mode not enabled\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t}\n\n\trte_eth_promiscuous_disable(test_params->bonded_port_id);\n\n\tTEST_ASSERT_EQUAL(rte_eth_promiscuous_get(test_params->bonded_port_id), 0,\n\t\t\t\"Port (%d) promiscuous mode not disabled\",\n\t\t\ttest_params->bonded_port_id);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tTEST_ASSERT_EQUAL(rte_eth_promiscuous_get(\n\t\t\t\ttest_params->slave_port_ids[i]), 0,\n\t\t\t\t\"Port (%d) promiscuous mode not disabled\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_broadcast_verify_mac_assignment(void)\n{\n\tstruct ether_addr read_mac_addr, expected_mac_addr_0, expected_mac_addr_1;\n\n\tint i;\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &expected_mac_addr_0);\n\trte_eth_macaddr_get(test_params->slave_port_ids[2], &expected_mac_addr_1);\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_BROADCAST, 0, 4, 1),\n\t\t\t\"Failed to intialise bonded device\");\n\n\t/* Verify that all MACs are the same as first slave added to bonded\n\t * device */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\trte_eth_macaddr_get(test_params->slave_port_ids[i], &read_mac_addr);\n\t\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\t\tsizeof(read_mac_addr)),\n\t\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t}\n\n\t/* change primary and verify that MAC addresses haven't changed */\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_primary_set(test_params->bonded_port_id,\n\t\t\ttest_params->slave_port_ids[2]),\n\t\t\t\"Failed to set bonded port (%d) primary port to (%d)\",\n\t\t\ttest_params->bonded_port_id, test_params->slave_port_ids[i]);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\trte_eth_macaddr_get(test_params->slave_port_ids[i], &read_mac_addr);\n\t\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\t\tsizeof(read_mac_addr)),\n\t\t\t\t\"slave port (%d) mac address has changed to that of primary \"\n\t\t\t\t\"port without stop/start toggle of bonded device\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t}\n\n\t/* stop / start bonded device and verify that primary MAC address is\n\t * propagated to bonded device and slaves */\n\n\trte_eth_dev_stop(test_params->bonded_port_id);\n\n\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(test_params->bonded_port_id),\n\t\t\t\"Failed to start bonded device\");\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of new primary port\",\n\t\t\ttest_params->slave_port_ids[i]);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\trte_eth_macaddr_get(test_params->slave_port_ids[i], &read_mac_addr);\n\t\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\t\tsizeof(read_mac_addr)),\n\t\t\t\t\"slave port (%d) mac address not set to that of new primary \"\n\t\t\t\t\"port\", test_params->slave_port_ids[i]);\n\t}\n\n\t/* Set explicit MAC address */\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_mac_address_set(\n\t\t\ttest_params->bonded_port_id, (struct ether_addr *)bonded_mac),\n\t\t\t\"Failed to set MAC address\");\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(bonded_mac, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of new primary port\",\n\t\t\ttest_params->slave_port_ids[i]);\n\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\trte_eth_macaddr_get(test_params->slave_port_ids[i], &read_mac_addr);\n\t\tTEST_ASSERT_SUCCESS(memcmp(bonded_mac, &read_mac_addr,\n\t\t\t\tsizeof(read_mac_addr)),\n\t\t\t\t\"slave port (%d) mac address not set to that of new primary \"\n\t\t\t\t\"port\", test_params->slave_port_ids[i]);\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n#define BROADCAST_LINK_STATUS_NUM_OF_SLAVES (4)\nstatic int\ntest_broadcast_verify_slave_link_status_change_behaviour(void)\n{\n\tstruct rte_mbuf *pkt_burst[BROADCAST_LINK_STATUS_NUM_OF_SLAVES][MAX_PKT_BURST];\n\tstruct rte_mbuf *rx_pkt_burst[MAX_PKT_BURST] = { NULL };\n\tstruct rte_eth_stats port_stats;\n\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tint i, j, burst_size, slave_count;\n\n\tmemset(pkt_burst, 0, sizeof(pkt_burst));\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\t\tBONDING_MODE_BROADCAST, 0, BROADCAST_LINK_STATUS_NUM_OF_SLAVES,\n\t\t\t\t1), \"Failed to intialise bonded device\");\n\n\t/* Verify Current Slaves Count /Active Slave Count is */\n\tslave_count = rte_eth_bond_slaves_get(test_params->bonded_port_id, slaves,\n\t\t\tRTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(slave_count, 4,\n\t\t\t\"Number of slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, 4);\n\n\tslave_count = rte_eth_bond_active_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(slave_count, 4,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, 4);\n\n\t/* Set 2 slaves link status to down */\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[1], 0);\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[3], 0);\n\n\tslave_count = rte_eth_bond_active_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(slave_count, 2,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, 2);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++)\n\t\trte_eth_stats_reset(test_params->slave_port_ids[i]);\n\n\t/* Verify that pkts are not sent on slaves with link status down */\n\tburst_size = 21;\n\n\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t&pkt_burst[0][0], burst_size, 0, 0, 1, 0, 0), burst_size,\n\t\t\t\"generate_test_burst failed\");\n\n\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(test_params->bonded_port_id, 0,\n\t\t\t&pkt_burst[0][0], burst_size), burst_size,\n\t\t\t\"rte_eth_tx_burst failed\\n\");\n\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)(burst_size * slave_count),\n\t\t\t\"(%d) port_stats.opackets (%d) not as expected (%d)\\n\",\n\t\t\ttest_params->bonded_port_id, (int)port_stats.opackets,\n\t\t\tburst_size * slave_count);\n\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size,\n\t\t\t\"(%d) port_stats.opackets not as expected\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, 0,\n\t\t\t\"(%d) port_stats.opackets not as expected\",\n\t\t\t\ttest_params->slave_port_ids[1]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[2], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (uint64_t)burst_size,\n\t\t\t\"(%d) port_stats.opackets not as expected\",\n\t\t\t\ttest_params->slave_port_ids[2]);\n\n\n\trte_eth_stats_get(test_params->slave_port_ids[3], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, 0,\n\t\t\t\"(%d) port_stats.opackets not as expected\",\n\t\t\ttest_params->slave_port_ids[3]);\n\n\n\tfor (i = 0; i < BROADCAST_LINK_STATUS_NUM_OF_SLAVES; i++) {\n\t\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t\t&pkt_burst[i][0], burst_size, 0, 0, 1, 0, 0),\n\t\t\t\tburst_size, \"failed to generate packet burst\");\n\n\t\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[i],\n\t\t\t\t&pkt_burst[i][0], burst_size);\n\t}\n\n\t/* Verify that pkts are not received on slaves with link status down */\n\tTEST_ASSERT_EQUAL(rte_eth_rx_burst(\n\t\t\ttest_params->bonded_port_id, 0, rx_pkt_burst, MAX_PKT_BURST),\n\t\t\tburst_size + burst_size, \"rte_eth_rx_burst failed\");\n\n\n\t/* Verify bonded device rx count */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)(burst_size + burst_size),\n\t\t\t\"(%d) port_stats.ipackets not as expected\\n\",\n\t\t\ttest_params->bonded_port_id);\n\n\t/* free mbufs allocate for rx testing */\n\tfor (i = 0; i < BROADCAST_LINK_STATUS_NUM_OF_SLAVES; i++) {\n\t\tfor (j = 0; j < MAX_PKT_BURST; j++) {\n\t\t\tif (pkt_burst[i][j] != NULL) {\n\t\t\t\trte_pktmbuf_free(pkt_burst[i][j]);\n\t\t\t\tpkt_burst[i][j] = NULL;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_reconfigure_bonded_device(void)\n{\n\ttest_params->nb_rx_q = 4;\n\ttest_params->nb_tx_q = 4;\n\n\tTEST_ASSERT_SUCCESS(configure_ethdev(test_params->bonded_port_id, 0, 0),\n\t\t\t\"failed to reconfigure bonded device\");\n\n\ttest_params->nb_rx_q = 2;\n\ttest_params->nb_tx_q = 2;\n\n\tTEST_ASSERT_SUCCESS(configure_ethdev(test_params->bonded_port_id, 0, 0),\n\t\t\t\"failed to reconfigure bonded device with less rx/tx queues\");\n\n\treturn 0;\n}\n\n\nstatic int\ntest_close_bonded_device(void)\n{\n\trte_eth_dev_close(test_params->bonded_port_id);\n\treturn 0;\n}\n\nstatic int\ntestsuite_teardown(void)\n{\n\tif (test_params->pkt_eth_hdr != NULL) {\n\t\tfree(test_params->pkt_eth_hdr);\n\t\ttest_params->pkt_eth_hdr = NULL;\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic void\nfree_virtualpmd_tx_queue(void)\n{\n\tint i, slave_port, to_free_cnt;\n\tstruct rte_mbuf *pkts_to_free[MAX_PKT_BURST];\n\n\t/* Free tx queue of virtual pmd */\n\tfor (slave_port = 0; slave_port < test_params->bonded_slave_count;\n\t\t\tslave_port++) {\n\t\tto_free_cnt = virtual_ethdev_get_mbufs_from_tx_queue(\n\t\t\t\ttest_params->slave_port_ids[slave_port],\n\t\t\t\tpkts_to_free, MAX_PKT_BURST);\n\t\tfor (i = 0; i < to_free_cnt; i++)\n\t\t\trte_pktmbuf_free(pkts_to_free[i]);\n\t}\n}\n\nstatic int\ntest_tlb_tx_burst(void)\n{\n\tint i, burst_size, nb_tx;\n\tuint64_t nb_tx2 = 0;\n\tstruct rte_mbuf *pkt_burst[MAX_PKT_BURST];\n\tstruct rte_eth_stats port_stats[32];\n\tuint64_t sum_ports_opackets = 0, all_bond_opackets = 0, all_bond_obytes = 0;\n\tuint16_t pktlen;\n\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves\n\t\t\t(BONDING_MODE_TLB, 1, 3, 1),\n\t\t\t\"Failed to initialise bonded device\");\n\n\tburst_size = 20 * test_params->bonded_slave_count;\n\n\tTEST_ASSERT(burst_size < MAX_PKT_BURST,\n\t\t\t\"Burst size specified is greater than supported.\\n\");\n\n\n\t/* Generate bursts of packets */\n\tfor (i = 0; i < 400000; i++) {\n\t\t/*test two types of mac src own(bonding) and others */\n\t\tif (i % 2 == 0) {\n\t\t\tinitialize_eth_header(test_params->pkt_eth_hdr,\n\t\t\t\t\t(struct ether_addr *)src_mac,\n\t\t\t\t\t(struct ether_addr *)dst_mac_0, ETHER_TYPE_IPv4, 0, 0);\n\t\t} else {\n\t\t\tinitialize_eth_header(test_params->pkt_eth_hdr,\n\t\t\t\t\t(struct ether_addr *)test_params->default_slave_mac,\n\t\t\t\t\t(struct ether_addr *)dst_mac_0, ETHER_TYPE_IPv4, 0, 0);\n\t\t}\n\t\tpktlen = initialize_udp_header(test_params->pkt_udp_hdr, src_port,\n\t\t\t\tdst_port_0, 16);\n\t\tpktlen = initialize_ipv4_header(test_params->pkt_ipv4_hdr, src_addr,\n\t\t\t\tdst_addr_0, pktlen);\n\t\tgenerate_packet_burst(test_params->mbuf_pool, pkt_burst,\n\t\t\t\ttest_params->pkt_eth_hdr, 0, test_params->pkt_ipv4_hdr,\n\t\t\t\t1, test_params->pkt_udp_hdr, burst_size, 60, 1);\n\t\t/* Send burst on bonded port */\n\t\tnb_tx = rte_eth_tx_burst(test_params->bonded_port_id, 0, pkt_burst,\n\t\t\t\tburst_size);\n\t\tnb_tx2 += nb_tx;\n\n\t\tfree_virtualpmd_tx_queue();\n\n\t\tTEST_ASSERT_EQUAL(nb_tx, burst_size,\n\t\t\t\t\"number of packet not equal burst size\");\n\n\t\trte_delay_us(5);\n\t}\n\n\n\t/* Verify bonded port tx stats */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats[0]);\n\n\tall_bond_opackets = port_stats[0].opackets;\n\tall_bond_obytes = port_stats[0].obytes;\n\n\tTEST_ASSERT_EQUAL(port_stats[0].opackets, (uint64_t)nb_tx2,\n\t\t\t\"Bonded Port (%d) opackets value (%u) not as expected (%d)\\n\",\n\t\t\ttest_params->bonded_port_id, (unsigned int)port_stats[0].opackets,\n\t\t\tburst_size);\n\n\n\t/* Verify slave ports tx stats */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\trte_eth_stats_get(test_params->slave_port_ids[i], &port_stats[i]);\n\t\tsum_ports_opackets += port_stats[i].opackets;\n\t}\n\n\tTEST_ASSERT_EQUAL(sum_ports_opackets, (uint64_t)all_bond_opackets,\n\t\t\t\"Total packets sent by slaves is not equal to packets sent by bond interface\");\n\n\t/* checking if distribution of packets is balanced over slaves */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tTEST_ASSERT(port_stats[i].obytes > 0 &&\n\t\t\t\tport_stats[i].obytes < all_bond_obytes,\n\t\t\t\t\t\t\"Packets are not balanced over slaves\");\n\t}\n\n\t/* Put all slaves down and try and transmit */\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\t\ttest_params->slave_port_ids[i], 0);\n\t}\n\n\t/* Send burst on bonded port */\n\tnb_tx = rte_eth_tx_burst(test_params->bonded_port_id, 0, pkt_burst,\n\t\t\tburst_size);\n\tTEST_ASSERT_EQUAL(nb_tx, 0, \" bad number of packet in burst\");\n\n\t/* Clean ugit checkout masterp and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n#define TEST_ADAPTIVE_TRANSMIT_LOAD_BALANCING_RX_BURST_SLAVE_COUNT (4)\n\nstatic int\ntest_tlb_rx_burst(void)\n{\n\tstruct rte_mbuf *gen_pkt_burst[MAX_PKT_BURST] = { NULL };\n\tstruct rte_mbuf *rx_pkt_burst[MAX_PKT_BURST] = { NULL };\n\n\tstruct rte_eth_stats port_stats;\n\n\tint primary_port;\n\n\tuint16_t i, j, nb_rx, burst_size = 17;\n\n\t/* Initialize bonded device with 4 slaves in transmit load balancing mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_TLB,\n\t\t\tTEST_ADAPTIVE_TRANSMIT_LOAD_BALANCING_RX_BURST_SLAVE_COUNT, 1, 1),\n\t\t\t\"Failed to initialize bonded device\");\n\n\n\tprimary_port = rte_eth_bond_primary_get(test_params->bonded_port_id);\n\tTEST_ASSERT(primary_port >= 0,\n\t\t\t\"failed to get primary slave for bonded port (%d)\",\n\t\t\ttest_params->bonded_port_id);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\t/* Generate test bursts of packets to transmit */\n\t\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t\t&gen_pkt_burst[0], burst_size, 0, 1, 0, 0, 0), burst_size,\n\t\t\t\t\"burst generation failed\");\n\n\t\t/* Add rx data to slave */\n\t\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[i],\n\t\t\t\t&gen_pkt_burst[0], burst_size);\n\n\t\t/* Call rx burst on bonded device */\n\t\tnb_rx = rte_eth_rx_burst(test_params->bonded_port_id, 0,\n\t\t\t\t&rx_pkt_burst[0], MAX_PKT_BURST);\n\n\t\tTEST_ASSERT_EQUAL(nb_rx, burst_size, \"rte_eth_rx_burst failed\\n\");\n\n\t\tif (test_params->slave_port_ids[i] == primary_port) {\n\t\t\t/* Verify bonded device rx count */\n\t\t\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\t\t\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size,\n\t\t\t\t\t\"Bonded Port (%d) ipackets value (%u) not as expected (%d)\\n\",\n\t\t\t\t\ttest_params->bonded_port_id,\n\t\t\t\t\t(unsigned int)port_stats.ipackets, burst_size);\n\n\t\t\t/* Verify bonded slave devices rx count */\n\t\t\tfor (j = 0; j < test_params->bonded_slave_count; j++) {\n\t\t\t\trte_eth_stats_get(test_params->slave_port_ids[j], &port_stats);\n\t\t\t\tif (i == j) {\n\t\t\t\t\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size,\n\t\t\t\t\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\\n\",\n\t\t\t\t\t\t\ttest_params->slave_port_ids[i],\n\t\t\t\t\t\t\t(unsigned int)port_stats.ipackets, burst_size);\n\t\t\t\t} else {\n\t\t\t\t\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)0,\n\t\t\t\t\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\\n\",\n\t\t\t\t\t\t\ttest_params->slave_port_ids[i],\n\t\t\t\t\t\t\t(unsigned int)port_stats.ipackets, 0);\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tfor (j = 0; j < test_params->bonded_slave_count; j++) {\n\t\t\t\trte_eth_stats_get(test_params->slave_port_ids[j], &port_stats);\n\t\t\t\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)0,\n\t\t\t\t\t\t\"Slave Port (%d) ipackets value (%u) not as expected (%d)\\n\",\n\t\t\t\t\t\ttest_params->slave_port_ids[i],\n\t\t\t\t\t\t(unsigned int)port_stats.ipackets, 0);\n\t\t\t}\n\t\t}\n\n\t\t/* free mbufs */\n\t\tfor (i = 0; i < burst_size; i++)\n\t\t\trte_pktmbuf_free(rx_pkt_burst[i]);\n\n\t\t/* reset bonded device stats */\n\t\trte_eth_stats_reset(test_params->bonded_port_id);\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_tlb_verify_promiscuous_enable_disable(void)\n{\n\tint i, primary_port, promiscuous_en;\n\n\t/* Initialize bonded device with 4 slaves in transmit load balancing mode */\n\tTEST_ASSERT_SUCCESS( initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_TLB, 0, 4, 1),\n\t\t\t\"Failed to initialize bonded device\");\n\n\tprimary_port = rte_eth_bond_primary_get(test_params->bonded_port_id);\n\tTEST_ASSERT(primary_port >= 0,\n\t\t\t\"failed to get primary slave for bonded port (%d)\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_promiscuous_enable(test_params->bonded_port_id);\n\n\tpromiscuous_en = rte_eth_promiscuous_get(test_params->bonded_port_id);\n\tTEST_ASSERT_EQUAL(promiscuous_en, (int)1,\n\t\t\t\"Port (%d) promiscuous mode not enabled\\n\",\n\t\t\ttest_params->bonded_port_id);\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tpromiscuous_en = rte_eth_promiscuous_get(\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t\tif (primary_port == test_params->slave_port_ids[i]) {\n\t\t\tTEST_ASSERT_EQUAL(promiscuous_en, (int)1,\n\t\t\t\t\t\"Port (%d) promiscuous mode not enabled\\n\",\n\t\t\t\t\ttest_params->bonded_port_id);\n\t\t} else {\n\t\t\tTEST_ASSERT_EQUAL(promiscuous_en, (int)0,\n\t\t\t\t\t\"Port (%d) promiscuous mode enabled\\n\",\n\t\t\t\t\ttest_params->bonded_port_id);\n\t\t}\n\n\t}\n\n\trte_eth_promiscuous_disable(test_params->bonded_port_id);\n\n\tpromiscuous_en = rte_eth_promiscuous_get(test_params->bonded_port_id);\n\tTEST_ASSERT_EQUAL(promiscuous_en, (int)0,\n\t\t\t\"Port (%d) promiscuous mode not disabled\\n\",\n\t\t\ttest_params->bonded_port_id);\n\n\tfor (i = 0; i < test_params->bonded_slave_count; i++) {\n\t\tpromiscuous_en = rte_eth_promiscuous_get(\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t\tTEST_ASSERT_EQUAL(promiscuous_en, (int)0,\n\t\t\t\t\"slave port (%d) promiscuous mode not disabled\\n\",\n\t\t\t\ttest_params->slave_port_ids[i]);\n\t}\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_tlb_verify_mac_assignment(void)\n{\n\tstruct ether_addr read_mac_addr, expected_mac_addr_0, expected_mac_addr_1;\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &expected_mac_addr_0);\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &expected_mac_addr_1);\n\n\t/* Initialize bonded device with 2 slaves in active backup mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_TLB, 0, 2, 1),\n\t\t\t\"Failed to initialize bonded device\");\n\n\t/* Verify that bonded MACs is that of first slave and that the other slave\n\t * MAC hasn't been changed */\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not as expected\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\t/* change primary and verify that MAC addresses haven't changed */\n\tTEST_ASSERT_EQUAL(rte_eth_bond_primary_set(test_params->bonded_port_id,\n\t\t\ttest_params->slave_port_ids[1]), 0,\n\t\t\t\"Failed to set bonded port (%d) primary port to (%d)\",\n\t\t\ttest_params->bonded_port_id, test_params->slave_port_ids[1]);\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not as expected\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\t/* stop / start bonded device and verify that primary MAC address is\n\t * propagated to bonded device and slaves */\n\n\trte_eth_dev_stop(test_params->bonded_port_id);\n\n\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(test_params->bonded_port_id),\n\t\t\t\"Failed to start device\");\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not as expected\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_1, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of primary port\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\n\t/* Set explicit MAC address */\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_mac_address_set(\n\t\t\ttest_params->bonded_port_id, (struct ether_addr *)bonded_mac),\n\t\t\t\"failed to set MAC addres\");\n\n\trte_eth_macaddr_get(test_params->bonded_port_id, &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&bonded_mac, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"bonded port (%d) mac address not set to that of bonded port\",\n\t\t\ttest_params->bonded_port_id);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[0], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&expected_mac_addr_0, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not as expected\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_macaddr_get(test_params->slave_port_ids[1], &read_mac_addr);\n\tTEST_ASSERT_SUCCESS(memcmp(&bonded_mac, &read_mac_addr,\n\t\t\tsizeof(read_mac_addr)),\n\t\t\t\"slave port (%d) mac address not set to that of bonded port\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic int\ntest_tlb_verify_slave_link_status_change_failover(void)\n{\n\tstruct rte_mbuf *pkt_burst[TEST_ADAPTIVE_TRANSMIT_LOAD_BALANCING_RX_BURST_SLAVE_COUNT][MAX_PKT_BURST];\n\tstruct rte_mbuf *rx_pkt_burst[MAX_PKT_BURST] = { NULL };\n\tstruct rte_eth_stats port_stats;\n\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tint i, j, burst_size, slave_count, primary_port;\n\n\tburst_size = 21;\n\n\tmemset(pkt_burst, 0, sizeof(pkt_burst));\n\n\n\n\t/* Initialize bonded device with 4 slaves in round robin mode */\n\tTEST_ASSERT_SUCCESS(initialize_bonded_device_with_slaves(\n\t\t\tBONDING_MODE_TLB, 0,\n\t\t\tTEST_ADAPTIVE_TRANSMIT_LOAD_BALANCING_RX_BURST_SLAVE_COUNT, 1),\n\t\t\t\"Failed to initialize bonded device with slaves\");\n\n\t/* Verify Current Slaves Count /Active Slave Count is */\n\tslave_count = rte_eth_bond_slaves_get(test_params->bonded_port_id, slaves,\n\t\t\tRTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(slave_count, 4,\n\t\t\t\"Number of slaves (%d) is not as expected (%d).\\n\",\n\t\t\tslave_count, 4);\n\n\tslave_count = rte_eth_bond_active_slaves_get(test_params->bonded_port_id,\n\t\t\tslaves, RTE_MAX_ETHPORTS);\n\tTEST_ASSERT_EQUAL(slave_count, (int)4,\n\t\t\t\"Number of slaves (%d) is not as expected (%d).\\n\",\n\t\t\tslave_count, 4);\n\n\tprimary_port = rte_eth_bond_primary_get(test_params->bonded_port_id);\n\tTEST_ASSERT_EQUAL(primary_port, test_params->slave_port_ids[0],\n\t\t\t\"Primary port not as expected\");\n\n\t/* Bring 2 slaves down and verify active slave count */\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[1], 0);\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[3], 0);\n\n\tTEST_ASSERT_EQUAL(rte_eth_bond_active_slaves_get(\n\t\t\ttest_params->bonded_port_id, slaves, RTE_MAX_ETHPORTS), 2,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, 2);\n\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[1], 1);\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[3], 1);\n\n\n\t/* Bring primary port down, verify that active slave count is 3 and primary\n\t * has changed */\n\tvirtual_ethdev_simulate_link_status_interrupt(\n\t\t\ttest_params->slave_port_ids[0], 0);\n\n\tTEST_ASSERT_EQUAL(rte_eth_bond_active_slaves_get(\n\t\t\ttest_params->bonded_port_id, slaves, RTE_MAX_ETHPORTS), 3,\n\t\t\t\"Number of active slaves (%d) is not as expected (%d).\",\n\t\t\tslave_count, 3);\n\n\tprimary_port = rte_eth_bond_primary_get(test_params->bonded_port_id);\n\tTEST_ASSERT_EQUAL(primary_port, test_params->slave_port_ids[2],\n\t\t\t\"Primary port not as expected\");\n\trte_delay_us(500000);\n\t/* Verify that pkts are sent on new primary slave */\n\tfor (i = 0; i < 4; i++) {\n\t\tTEST_ASSERT_EQUAL(generate_test_burst(\n\t\t\t\t&pkt_burst[0][0], burst_size, 0, 1, 0, 0, 0), burst_size,\n\t\t\t\t\"generate_test_burst failed\\n\");\n\t\tTEST_ASSERT_EQUAL(rte_eth_tx_burst(\n\t\t\t\ttest_params->bonded_port_id, 0, &pkt_burst[0][0], burst_size), burst_size,\n\t\t\t\t\"rte_eth_tx_burst failed\\n\");\n\t\trte_delay_us(11000);\n\t}\n\n\trte_eth_stats_get(test_params->slave_port_ids[0], &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.opackets, (int8_t)0,\n\t\t\t\"(%d) port_stats.opackets not as expected\\n\",\n\t\t\ttest_params->slave_port_ids[0]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[1], &port_stats);\n\tTEST_ASSERT_NOT_EQUAL(port_stats.opackets, (int8_t)0,\n\t\t\t\"(%d) port_stats.opackets not as expected\\n\",\n\t\t\ttest_params->slave_port_ids[1]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[2], &port_stats);\n\tTEST_ASSERT_NOT_EQUAL(port_stats.opackets, (int8_t)0,\n\t\t\t\"(%d) port_stats.opackets not as expected\\n\",\n\t\t\ttest_params->slave_port_ids[2]);\n\n\trte_eth_stats_get(test_params->slave_port_ids[3], &port_stats);\n\tTEST_ASSERT_NOT_EQUAL(port_stats.opackets, (int8_t)0,\n\t\t\t\"(%d) port_stats.opackets not as expected\\n\",\n\t\t\ttest_params->slave_port_ids[3]);\n\n\n\t/* Generate packet burst for testing */\n\n\tfor (i = 0; i < TEST_ADAPTIVE_TRANSMIT_LOAD_BALANCING_RX_BURST_SLAVE_COUNT; i++) {\n\t\tif (generate_test_burst(&pkt_burst[i][0], burst_size, 0, 1, 0, 0, 0) !=\n\t\t\t\tburst_size)\n\t\t\treturn -1;\n\n\t\tvirtual_ethdev_add_mbufs_to_rx_queue(\n\t\t\t\ttest_params->slave_port_ids[i], &pkt_burst[i][0], burst_size);\n\t}\n\n\tif (rte_eth_rx_burst(test_params->bonded_port_id, 0, rx_pkt_burst,\n\t\t\tMAX_PKT_BURST) != burst_size) {\n\t\tprintf(\"rte_eth_rx_burst\\n\");\n\t\treturn -1;\n\n\t}\n\n\t/* Verify bonded device rx count */\n\trte_eth_stats_get(test_params->bonded_port_id, &port_stats);\n\tTEST_ASSERT_EQUAL(port_stats.ipackets, (uint64_t)burst_size,\n\t\t\t\"(%d) port_stats.ipackets not as expected\\n\",\n\t\t\ttest_params->bonded_port_id);\n\n\t/* free mbufs */\n\n\tfor (i = 0; i < TEST_ADAPTIVE_TRANSMIT_LOAD_BALANCING_RX_BURST_SLAVE_COUNT; i++) {\n\t\tfor (j = 0; j < MAX_PKT_BURST; j++) {\n\t\t\tif (pkt_burst[i][j] != NULL) {\n\t\t\t\trte_pktmbuf_free(pkt_burst[i][j]);\n\t\t\t\tpkt_burst[i][j] = NULL;\n\t\t\t}\n\t\t}\n\t}\n\n\n\t/* Clean up and remove slaves from bonded device */\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\n#define TEST_ALB_SLAVE_COUNT\t2\n\nstatic uint8_t mac_client1[] = {0x00, 0xAA, 0x55, 0xFF, 0xCC, 1};\nstatic uint8_t mac_client2[] = {0x00, 0xAA, 0x55, 0xFF, 0xCC, 2};\nstatic uint8_t mac_client3[] = {0x00, 0xAA, 0x55, 0xFF, 0xCC, 3};\nstatic uint8_t mac_client4[] = {0x00, 0xAA, 0x55, 0xFF, 0xCC, 4};\n\nstatic uint32_t ip_host = IPV4_ADDR(192, 168, 0, 0);\nstatic uint32_t ip_client1 = IPV4_ADDR(192, 168, 0, 1);\nstatic uint32_t ip_client2 = IPV4_ADDR(192, 168, 0, 2);\nstatic uint32_t ip_client3 = IPV4_ADDR(192, 168, 0, 3);\nstatic uint32_t ip_client4 = IPV4_ADDR(192, 168, 0, 4);\n\nstatic int\ntest_alb_change_mac_in_reply_sent(void)\n{\n\tstruct rte_mbuf *pkt;\n\tstruct rte_mbuf *pkts_sent[MAX_PKT_BURST];\n\n\tstruct ether_hdr *eth_pkt;\n\tstruct arp_hdr *arp_pkt;\n\n\tint slave_idx, nb_pkts, pkt_idx;\n\tint retval = 0;\n\n\tstruct ether_addr bond_mac, client_mac;\n\tstruct ether_addr *slave_mac1, *slave_mac2;\n\n\tTEST_ASSERT_SUCCESS(\n\t\t\tinitialize_bonded_device_with_slaves(BONDING_MODE_ALB,\n\t\t\t\t\t0, TEST_ALB_SLAVE_COUNT, 1),\n\t\t\t\"Failed to initialize_bonded_device_with_slaves.\");\n\n\t/* Flush tx queue */\n\trte_eth_tx_burst(test_params->bonded_port_id, 0, NULL, 0);\n\tfor (slave_idx = 0; slave_idx < test_params->bonded_slave_count;\n\t\t\tslave_idx++) {\n\t\tnb_pkts = virtual_ethdev_get_mbufs_from_tx_queue(\n\t\t\t\ttest_params->slave_port_ids[slave_idx], pkts_sent,\n\t\t\t\tMAX_PKT_BURST);\n\t}\n\n\tether_addr_copy(\n\t\t\trte_eth_devices[test_params->bonded_port_id].data->mac_addrs,\n\t\t\t&bond_mac);\n\n\t/*\n\t * Generating four packets with different mac and ip addresses and sending\n\t * them through the bonding port.\n\t */\n\tpkt = rte_pktmbuf_alloc(test_params->mbuf_pool);\n\tmemcpy(client_mac.addr_bytes, mac_client1, ETHER_ADDR_LEN);\n\teth_pkt = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\tinitialize_eth_header(eth_pkt, &bond_mac, &client_mac, ETHER_TYPE_ARP, 0,\n\t\t\t0);\n\tarp_pkt = (struct arp_hdr *)((char *)eth_pkt + sizeof(struct ether_hdr));\n\tinitialize_arp_header(arp_pkt, &bond_mac, &client_mac, ip_host, ip_client1,\n\t\t\tARP_OP_REPLY);\n\trte_eth_tx_burst(test_params->bonded_port_id, 0, &pkt, 1);\n\n\tpkt = rte_pktmbuf_alloc(test_params->mbuf_pool);\n\tmemcpy(client_mac.addr_bytes, mac_client2, ETHER_ADDR_LEN);\n\teth_pkt = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\tinitialize_eth_header(eth_pkt, &bond_mac, &client_mac, ETHER_TYPE_ARP, 0,\n\t\t\t0);\n\tarp_pkt = (struct arp_hdr *)((char *)eth_pkt + sizeof(struct ether_hdr));\n\tinitialize_arp_header(arp_pkt, &bond_mac, &client_mac, ip_host, ip_client2,\n\t\t\tARP_OP_REPLY);\n\trte_eth_tx_burst(test_params->bonded_port_id, 0, &pkt, 1);\n\n\tpkt = rte_pktmbuf_alloc(test_params->mbuf_pool);\n\tmemcpy(client_mac.addr_bytes, mac_client3, ETHER_ADDR_LEN);\n\teth_pkt = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\tinitialize_eth_header(eth_pkt, &bond_mac, &client_mac, ETHER_TYPE_ARP, 0,\n\t\t\t0);\n\tarp_pkt = (struct arp_hdr *)((char *)eth_pkt + sizeof(struct ether_hdr));\n\tinitialize_arp_header(arp_pkt, &bond_mac, &client_mac, ip_host, ip_client3,\n\t\t\tARP_OP_REPLY);\n\trte_eth_tx_burst(test_params->bonded_port_id, 0, &pkt, 1);\n\n\tpkt = rte_pktmbuf_alloc(test_params->mbuf_pool);\n\tmemcpy(client_mac.addr_bytes, mac_client4, ETHER_ADDR_LEN);\n\teth_pkt = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\tinitialize_eth_header(eth_pkt, &bond_mac, &client_mac, ETHER_TYPE_ARP, 0,\n\t\t\t0);\n\tarp_pkt = (struct arp_hdr *)((char *)eth_pkt + sizeof(struct ether_hdr));\n\tinitialize_arp_header(arp_pkt, &bond_mac, &client_mac, ip_host, ip_client4,\n\t\t\tARP_OP_REPLY);\n\trte_eth_tx_burst(test_params->bonded_port_id, 0, &pkt, 1);\n\n\tslave_mac1 =\n\t\t\trte_eth_devices[test_params->slave_port_ids[0]].data->mac_addrs;\n\tslave_mac2 =\n\t\t\trte_eth_devices[test_params->slave_port_ids[1]].data->mac_addrs;\n\n\t/*\n\t * Checking if packets are properly distributed on bonding ports. Packets\n\t * 0 and 2 should be sent on port 0 and packets 1 and 3 on port 1.\n\t */\n\tfor (slave_idx = 0; slave_idx < test_params->bonded_slave_count; slave_idx++) {\n\t\tnb_pkts = virtual_ethdev_get_mbufs_from_tx_queue(\n\t\t\t\ttest_params->slave_port_ids[slave_idx], pkts_sent,\n\t\t\t\tMAX_PKT_BURST);\n\n\t\tfor (pkt_idx = 0; pkt_idx < nb_pkts; pkt_idx++) {\n\t\t\teth_pkt = rte_pktmbuf_mtod(pkts_sent[pkt_idx], struct ether_hdr *);\n\t\t\tarp_pkt = (struct arp_hdr *)((char *)eth_pkt + sizeof(struct ether_hdr));\n\n\t\t\tif (slave_idx%2 == 0) {\n\t\t\t\tif (!is_same_ether_addr(slave_mac1, &arp_pkt->arp_data.arp_sha)) {\n\t\t\t\t\tretval = -1;\n\t\t\t\t\tgoto test_end;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (!is_same_ether_addr(slave_mac2, &arp_pkt->arp_data.arp_sha)) {\n\t\t\t\t\tretval = -1;\n\t\t\t\t\tgoto test_end;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\ntest_end:\n\tretval += remove_slaves_and_stop_bonded_device();\n\treturn retval;\n}\n\nstatic int\ntest_alb_reply_from_client(void)\n{\n\tstruct ether_hdr *eth_pkt;\n\tstruct arp_hdr *arp_pkt;\n\n\tstruct rte_mbuf *pkt;\n\tstruct rte_mbuf *pkts_sent[MAX_PKT_BURST];\n\n\tint slave_idx, nb_pkts, pkt_idx, nb_pkts_sum = 0;\n\tint retval = 0;\n\n\tstruct ether_addr bond_mac, client_mac;\n\tstruct ether_addr *slave_mac1, *slave_mac2;\n\n\tTEST_ASSERT_SUCCESS(\n\t\t\tinitialize_bonded_device_with_slaves(BONDING_MODE_ALB,\n\t\t\t\t\t0, TEST_ALB_SLAVE_COUNT, 1),\n\t\t\t\"Failed to initialize_bonded_device_with_slaves.\");\n\n\t/* Flush tx queue */\n\trte_eth_tx_burst(test_params->bonded_port_id, 0, NULL, 0);\n\tfor (slave_idx = 0; slave_idx < test_params->bonded_slave_count; slave_idx++) {\n\t\tnb_pkts = virtual_ethdev_get_mbufs_from_tx_queue(\n\t\t\t\ttest_params->slave_port_ids[slave_idx], pkts_sent,\n\t\t\t\tMAX_PKT_BURST);\n\t}\n\n\tether_addr_copy(\n\t\t\trte_eth_devices[test_params->bonded_port_id].data->mac_addrs,\n\t\t\t&bond_mac);\n\n\t/*\n\t * Generating four packets with different mac and ip addresses and placing\n\t * them in the rx queue to be received by the bonding driver on rx_burst.\n\t */\n\tpkt = rte_pktmbuf_alloc(test_params->mbuf_pool);\n\tmemcpy(client_mac.addr_bytes, mac_client1, ETHER_ADDR_LEN);\n\teth_pkt = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\tinitialize_eth_header(eth_pkt, &bond_mac, &client_mac, ETHER_TYPE_ARP, 0,\n\t\t\t0);\n\tarp_pkt = (struct arp_hdr *)((char *)eth_pkt + sizeof(struct ether_hdr));\n\tinitialize_arp_header(arp_pkt, &client_mac, &bond_mac, ip_client1, ip_host,\n\t\t\tARP_OP_REPLY);\n\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[0], &pkt,\n\t\t\t1);\n\n\tpkt = rte_pktmbuf_alloc(test_params->mbuf_pool);\n\tmemcpy(client_mac.addr_bytes, mac_client2, ETHER_ADDR_LEN);\n\teth_pkt = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\tinitialize_eth_header(eth_pkt, &bond_mac, &client_mac, ETHER_TYPE_ARP, 0,\n\t\t\t0);\n\tarp_pkt = (struct arp_hdr *)((char *)eth_pkt + sizeof(struct ether_hdr));\n\tinitialize_arp_header(arp_pkt, &client_mac, &bond_mac, ip_client2, ip_host,\n\t\t\tARP_OP_REPLY);\n\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[0], &pkt,\n\t\t\t1);\n\n\tpkt = rte_pktmbuf_alloc(test_params->mbuf_pool);\n\tmemcpy(client_mac.addr_bytes, mac_client3, ETHER_ADDR_LEN);\n\teth_pkt = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\tinitialize_eth_header(eth_pkt, &bond_mac, &client_mac, ETHER_TYPE_ARP, 0,\n\t\t\t0);\n\tarp_pkt = (struct arp_hdr *)((char *)eth_pkt + sizeof(struct ether_hdr));\n\tinitialize_arp_header(arp_pkt, &client_mac, &bond_mac, ip_client3, ip_host,\n\t\t\tARP_OP_REPLY);\n\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[0], &pkt,\n\t\t\t1);\n\n\tpkt = rte_pktmbuf_alloc(test_params->mbuf_pool);\n\tmemcpy(client_mac.addr_bytes, mac_client4, ETHER_ADDR_LEN);\n\teth_pkt = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\tinitialize_eth_header(eth_pkt, &bond_mac, &client_mac, ETHER_TYPE_ARP, 0,\n\t\t\t0);\n\tarp_pkt = (struct arp_hdr *)((char *)eth_pkt + sizeof(struct ether_hdr));\n\tinitialize_arp_header(arp_pkt, &client_mac, &bond_mac, ip_client4, ip_host,\n\t\t\tARP_OP_REPLY);\n\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[0], &pkt,\n\t\t\t1);\n\n\t/*\n\t * Issue rx_burst and tx_burst to force bonding driver to send update ARP\n\t * packets to every client in alb table.\n\t */\n\trte_eth_rx_burst(test_params->bonded_port_id, 0, pkts_sent, MAX_PKT_BURST);\n\trte_eth_tx_burst(test_params->bonded_port_id, 0, NULL, 0);\n\n\tslave_mac1 = rte_eth_devices[test_params->slave_port_ids[0]].data->mac_addrs;\n\tslave_mac2 = rte_eth_devices[test_params->slave_port_ids[1]].data->mac_addrs;\n\n\t/*\n\t * Checking if update ARP packets were properly send on slave ports.\n\t */\n\tfor (slave_idx = 0; slave_idx < test_params->bonded_slave_count; slave_idx++) {\n\t\tnb_pkts = virtual_ethdev_get_mbufs_from_tx_queue(\n\t\t\t\ttest_params->slave_port_ids[slave_idx], pkts_sent, MAX_PKT_BURST);\n\t\tnb_pkts_sum += nb_pkts;\n\n\t\tfor (pkt_idx = 0; pkt_idx < nb_pkts; pkt_idx++) {\n\t\t\teth_pkt = rte_pktmbuf_mtod(pkts_sent[pkt_idx], struct ether_hdr *);\n\t\t\tarp_pkt = (struct arp_hdr *)((char *)eth_pkt + sizeof(struct ether_hdr));\n\n\t\t\tif (slave_idx%2 == 0) {\n\t\t\t\tif (!is_same_ether_addr(slave_mac1, &arp_pkt->arp_data.arp_sha)) {\n\t\t\t\t\tretval = -1;\n\t\t\t\t\tgoto test_end;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (!is_same_ether_addr(slave_mac2, &arp_pkt->arp_data.arp_sha)) {\n\t\t\t\t\tretval = -1;\n\t\t\t\t\tgoto test_end;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Check if proper number of packets was send */\n\tif (nb_pkts_sum < 4) {\n\t\tretval = -1;\n\t\tgoto test_end;\n\t}\n\ntest_end:\n\tretval += remove_slaves_and_stop_bonded_device();\n\treturn retval;\n}\n\nstatic int\ntest_alb_receive_vlan_reply(void)\n{\n\tstruct ether_hdr *eth_pkt;\n\tstruct vlan_hdr *vlan_pkt;\n\tstruct arp_hdr *arp_pkt;\n\n\tstruct rte_mbuf *pkt;\n\tstruct rte_mbuf *pkts_sent[MAX_PKT_BURST];\n\n\tint slave_idx, nb_pkts, pkt_idx;\n\tint retval = 0;\n\n\tstruct ether_addr bond_mac, client_mac;\n\n\tTEST_ASSERT_SUCCESS(\n\t\t\tinitialize_bonded_device_with_slaves(BONDING_MODE_ALB,\n\t\t\t\t\t0, TEST_ALB_SLAVE_COUNT, 1),\n\t\t\t\"Failed to initialize_bonded_device_with_slaves.\");\n\n\t/* Flush tx queue */\n\trte_eth_tx_burst(test_params->bonded_port_id, 0, NULL, 0);\n\tfor (slave_idx = 0; slave_idx < test_params->bonded_slave_count; slave_idx++) {\n\t\tnb_pkts = virtual_ethdev_get_mbufs_from_tx_queue(\n\t\t\t\ttest_params->slave_port_ids[slave_idx], pkts_sent,\n\t\t\t\tMAX_PKT_BURST);\n\t}\n\n\tether_addr_copy(\n\t\t\trte_eth_devices[test_params->bonded_port_id].data->mac_addrs,\n\t\t\t&bond_mac);\n\n\t/*\n\t * Generating packet with double VLAN header and placing it in the rx queue.\n\t */\n\tpkt = rte_pktmbuf_alloc(test_params->mbuf_pool);\n\tmemcpy(client_mac.addr_bytes, mac_client1, ETHER_ADDR_LEN);\n\teth_pkt = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\tinitialize_eth_header(eth_pkt, &bond_mac, &client_mac, ETHER_TYPE_VLAN, 0,\n\t\t\t0);\n\tvlan_pkt = (struct vlan_hdr *)((char *)(eth_pkt + 1));\n\tvlan_pkt->vlan_tci = rte_cpu_to_be_16(1);\n\tvlan_pkt->eth_proto = rte_cpu_to_be_16(ETHER_TYPE_VLAN);\n\tvlan_pkt = vlan_pkt+1;\n\tvlan_pkt->vlan_tci = rte_cpu_to_be_16(2);\n\tvlan_pkt->eth_proto = rte_cpu_to_be_16(ETHER_TYPE_ARP);\n\tarp_pkt = (struct arp_hdr *)((char *)(vlan_pkt + 1));\n\tinitialize_arp_header(arp_pkt, &client_mac, &bond_mac, ip_client1, ip_host,\n\t\t\tARP_OP_REPLY);\n\tvirtual_ethdev_add_mbufs_to_rx_queue(test_params->slave_port_ids[0], &pkt,\n\t\t\t1);\n\n\trte_eth_rx_burst(test_params->bonded_port_id, 0, pkts_sent, MAX_PKT_BURST);\n\trte_eth_tx_burst(test_params->bonded_port_id, 0, NULL, 0);\n\n\t/*\n\t * Checking if VLAN headers in generated ARP Update packet are correct.\n\t */\n\tfor (slave_idx = 0; slave_idx < test_params->bonded_slave_count; slave_idx++) {\n\t\tnb_pkts = virtual_ethdev_get_mbufs_from_tx_queue(\n\t\t\t\ttest_params->slave_port_ids[slave_idx], pkts_sent,\n\t\t\t\tMAX_PKT_BURST);\n\n\t\tfor (pkt_idx = 0; pkt_idx < nb_pkts; pkt_idx++) {\n\t\t\teth_pkt = rte_pktmbuf_mtod(pkts_sent[pkt_idx], struct ether_hdr *);\n\t\t\tvlan_pkt = (struct vlan_hdr *)((char *)(eth_pkt + 1));\n\t\t\tif (vlan_pkt->vlan_tci != rte_cpu_to_be_16(1)) {\n\t\t\t\tretval = -1;\n\t\t\t\tgoto test_end;\n\t\t\t}\n\t\t\tif (vlan_pkt->eth_proto != rte_cpu_to_be_16(ETHER_TYPE_VLAN)) {\n\t\t\t\tretval = -1;\n\t\t\t\tgoto test_end;\n\t\t\t}\n\t\t\tvlan_pkt = vlan_pkt+1;\n\t\t\tif (vlan_pkt->vlan_tci != rte_cpu_to_be_16(2)) {\n\t\t\t\tretval = -1;\n\t\t\t\tgoto test_end;\n\t\t\t}\n\t\t\tif (vlan_pkt->eth_proto != rte_cpu_to_be_16(ETHER_TYPE_ARP)) {\n\t\t\t\tretval = -1;\n\t\t\t\tgoto test_end;\n\t\t\t}\n\t\t}\n\t}\n\ntest_end:\n\tretval += remove_slaves_and_stop_bonded_device();\n\treturn retval;\n}\n\nstatic int\ntest_alb_ipv4_tx(void)\n{\n\tint burst_size, retval, pkts_send;\n\tstruct rte_mbuf *pkt_burst[MAX_PKT_BURST];\n\n\tretval = 0;\n\n\tTEST_ASSERT_SUCCESS(\n\t\t\tinitialize_bonded_device_with_slaves(BONDING_MODE_ALB,\n\t\t\t\t\t0, TEST_ALB_SLAVE_COUNT, 1),\n\t\t\t\"Failed to initialize_bonded_device_with_slaves.\");\n\n\tburst_size = 32;\n\n\t/* Generate test bursts of packets to transmit */\n\tif (generate_test_burst(pkt_burst, burst_size, 0, 1, 0, 0, 0) != burst_size) {\n\t\tretval = -1;\n\t\tgoto test_end;\n\t}\n\n\t/*\n\t * Checking if ipv4 traffic is transmitted via TLB policy.\n\t */\n\tpkts_send = rte_eth_tx_burst(\n\t\t\ttest_params->bonded_port_id, 0, pkt_burst, burst_size);\n\tif (pkts_send != burst_size) {\n\t\tretval = -1;\n\t\tgoto test_end;\n\t}\n\ntest_end:\n\tretval += remove_slaves_and_stop_bonded_device();\n\treturn retval;\n}\n\nstatic struct unit_test_suite link_bonding_test_suite = {\n\t.suite_name = \"Link Bonding Unit Test Suite\",\n\t.setup = test_setup,\n\t.teardown = testsuite_teardown,\n\t.unit_test_cases = {\n\t\tTEST_CASE(test_create_bonded_device),\n\t\tTEST_CASE(test_create_bonded_device_with_invalid_params),\n\t\tTEST_CASE(test_add_slave_to_bonded_device),\n\t\tTEST_CASE(test_add_slave_to_invalid_bonded_device),\n\t\tTEST_CASE(test_remove_slave_from_bonded_device),\n\t\tTEST_CASE(test_remove_slave_from_invalid_bonded_device),\n\t\tTEST_CASE(test_get_slaves_from_bonded_device),\n\t\tTEST_CASE(test_add_already_bonded_slave_to_bonded_device),\n\t\tTEST_CASE(test_add_remove_multiple_slaves_to_from_bonded_device),\n\t\tTEST_CASE(test_start_bonded_device),\n\t\tTEST_CASE(test_stop_bonded_device),\n\t\tTEST_CASE(test_set_bonding_mode),\n\t\tTEST_CASE(test_set_primary_slave),\n\t\tTEST_CASE(test_set_explicit_bonded_mac),\n\t\tTEST_CASE(test_set_bonded_port_initialization_mac_assignment),\n\t\tTEST_CASE(test_status_interrupt),\n\t\tTEST_CASE(test_adding_slave_after_bonded_device_started),\n\t\tTEST_CASE(test_roundrobin_tx_burst),\n\t\tTEST_CASE(test_roundrobin_tx_burst_slave_tx_fail),\n\t\tTEST_CASE(test_roundrobin_rx_burst_on_single_slave),\n\t\tTEST_CASE(test_roundrobin_rx_burst_on_multiple_slaves),\n\t\tTEST_CASE(test_roundrobin_verify_promiscuous_enable_disable),\n\t\tTEST_CASE(test_roundrobin_verify_mac_assignment),\n\t\tTEST_CASE(test_roundrobin_verify_slave_link_status_change_behaviour),\n\t\tTEST_CASE(test_roundrobin_verfiy_polling_slave_link_status_change),\n\t\tTEST_CASE(test_activebackup_tx_burst),\n\t\tTEST_CASE(test_activebackup_rx_burst),\n\t\tTEST_CASE(test_activebackup_verify_promiscuous_enable_disable),\n\t\tTEST_CASE(test_activebackup_verify_mac_assignment),\n\t\tTEST_CASE(test_activebackup_verify_slave_link_status_change_failover),\n\t\tTEST_CASE(test_balance_xmit_policy_configuration),\n\t\tTEST_CASE(test_balance_l2_tx_burst),\n\t\tTEST_CASE(test_balance_l23_tx_burst_ipv4_toggle_ip_addr),\n\t\tTEST_CASE(test_balance_l23_tx_burst_vlan_ipv4_toggle_ip_addr),\n\t\tTEST_CASE(test_balance_l23_tx_burst_ipv6_toggle_ip_addr),\n\t\tTEST_CASE(test_balance_l23_tx_burst_vlan_ipv6_toggle_ip_addr),\n\t\tTEST_CASE(test_balance_l23_tx_burst_toggle_mac_addr),\n\t\tTEST_CASE(test_balance_l34_tx_burst_ipv4_toggle_ip_addr),\n\t\tTEST_CASE(test_balance_l34_tx_burst_ipv4_toggle_udp_port),\n\t\tTEST_CASE(test_balance_l34_tx_burst_vlan_ipv4_toggle_ip_addr),\n\t\tTEST_CASE(test_balance_l34_tx_burst_ipv6_toggle_ip_addr),\n\t\tTEST_CASE(test_balance_l34_tx_burst_vlan_ipv6_toggle_ip_addr),\n\t\tTEST_CASE(test_balance_l34_tx_burst_ipv6_toggle_udp_port),\n\t\tTEST_CASE(test_balance_tx_burst_slave_tx_fail),\n\t\tTEST_CASE(test_balance_rx_burst),\n\t\tTEST_CASE(test_balance_verify_promiscuous_enable_disable),\n\t\tTEST_CASE(test_balance_verify_mac_assignment),\n\t\tTEST_CASE(test_balance_verify_slave_link_status_change_behaviour),\n\t\tTEST_CASE(test_tlb_tx_burst),\n\t\tTEST_CASE(test_tlb_rx_burst),\n\t\tTEST_CASE(test_tlb_verify_mac_assignment),\n\t\tTEST_CASE(test_tlb_verify_promiscuous_enable_disable),\n\t\tTEST_CASE(test_tlb_verify_slave_link_status_change_failover),\n\t\tTEST_CASE(test_alb_change_mac_in_reply_sent),\n\t\tTEST_CASE(test_alb_reply_from_client),\n\t\tTEST_CASE(test_alb_receive_vlan_reply),\n\t\tTEST_CASE(test_alb_ipv4_tx),\n\t\tTEST_CASE(test_broadcast_tx_burst),\n\t\tTEST_CASE(test_broadcast_tx_burst_slave_tx_fail),\n\t\tTEST_CASE(test_broadcast_rx_burst),\n\t\tTEST_CASE(test_broadcast_verify_promiscuous_enable_disable),\n\t\tTEST_CASE(test_broadcast_verify_mac_assignment),\n\t\tTEST_CASE(test_broadcast_verify_slave_link_status_change_behaviour),\n\t\tTEST_CASE(test_reconfigure_bonded_device),\n\t\tTEST_CASE(test_close_bonded_device),\n\n\t\t{ NULL, NULL, NULL, NULL, NULL } /**< NULL terminate unit test array */\n\t}\n};\n\n\nstatic int\ntest_link_bonding(void)\n{\n\treturn unit_test_suite_runner(&link_bonding_test_suite);\n}\n\nstatic struct test_command link_bonding_cmd = {\n\t.command = \"link_bonding_autotest\",\n\t.callback = test_link_bonding,\n};\nREGISTER_TEST_COMMAND(link_bonding_cmd);\n" }, { "path": "app/test/test_link_bonding_mode4.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \n#include \n#include \n#include \n\n#include \"packet_burst_generator.h\"\n\n#include \"test.h\"\n\n#define SLAVE_COUNT (4)\n\n#define RX_RING_SIZE 128\n#define TX_RING_SIZE 512\n\n#define MBUF_CACHE_SIZE (250)\n#define BURST_SIZE (32)\n\n#define TEST_RX_DESC_MAX (2048)\n#define TEST_TX_DESC_MAX (2048)\n#define MAX_PKT_BURST (32)\n#define DEF_PKT_BURST (16)\n\n#define BONDED_DEV_NAME (\"unit_test_mode4_bond_dev\")\n\n#define SLAVE_DEV_NAME_FMT (\"unit_test_mode4_slave_%d\")\n#define SLAVE_RX_QUEUE_FMT (\"unit_test_mode4_slave_%d_rx\")\n#define SLAVE_TX_QUEUE_FMT (\"unit_test_mode4_slave_%d_tx\")\n\n#define INVALID_SOCKET_ID (-1)\n#define INVALID_PORT_ID (0xFF)\n#define INVALID_BONDING_MODE (-1)\n\nstatic const struct ether_addr slave_mac_default = {\n\t{ 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00 }\n};\n\nstatic const struct ether_addr parnter_mac_default = {\n\t{ 0x22, 0xBB, 0xFF, 0xBB, 0x00, 0x00 }\n};\n\nstatic const struct ether_addr parnter_system = {\n\t{ 0x33, 0xFF, 0xBB, 0xFF, 0x00, 0x00 }\n};\n\nstatic const struct ether_addr slow_protocol_mac_addr = {\n\t{ 0x01, 0x80, 0xC2, 0x00, 0x00, 0x02 }\n};\n\nstruct slave_conf {\n\tstruct rte_ring *rx_queue;\n\tstruct rte_ring *tx_queue;\n\tuint8_t port_id;\n\tuint8_t bonded : 1;\n\n\tuint8_t lacp_parnter_state;\n};\n\nstruct ether_vlan_hdr {\n\tstruct ether_hdr pkt_eth_hdr;\n\tstruct vlan_hdr vlan_hdr;\n};\n\nstruct link_bonding_unittest_params {\n\tuint8_t bonded_port_id;\n\tstruct slave_conf slave_ports[SLAVE_COUNT];\n\n\tstruct rte_mempool *mbuf_pool;\n};\n\n#define TEST_DEFAULT_SLAVE_COUNT RTE_DIM(test_params.slave_ports)\n#define TEST_RX_SLAVE_COUT TEST_DEFAULT_SLAVE_COUNT\n#define TEST_TX_SLAVE_COUNT TEST_DEFAULT_SLAVE_COUNT\n#define TEST_MARKER_SLAVE_COUT TEST_DEFAULT_SLAVE_COUNT\n#define TEST_EXPIRED_SLAVE_COUNT TEST_DEFAULT_SLAVE_COUNT\n#define TEST_PROMISC_SLAVE_COUNT TEST_DEFAULT_SLAVE_COUNT\n\nstatic struct link_bonding_unittest_params test_params = {\n\t.bonded_port_id = INVALID_PORT_ID,\n\t.slave_ports = { [0 ... SLAVE_COUNT - 1] = { .port_id = INVALID_PORT_ID} },\n\n\t.mbuf_pool = NULL,\n};\n\nstatic struct rte_eth_conf default_pmd_conf = {\n\t.rxmode = {\n\t\t.mq_mode = ETH_MQ_RX_NONE,\n\t\t.max_rx_pkt_len = ETHER_MAX_LEN,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n\t.lpbk_mode = 0,\n};\n\n#define FOR_EACH(_i, _item, _array, _size) \\\n\tfor (_i = 0, _item = &_array[0]; _i < _size && (_item = &_array[_i]); _i++)\n\n/* Macro for iterating over every port that can be used as a slave\n * in this test.\n * _i variable used as an index in test_params->slave_ports\n * _slave pointer to &test_params->slave_ports[_idx]\n */\n#define FOR_EACH_PORT(_i, _port) \\\n\tFOR_EACH(_i, _port, test_params.slave_ports, \\\n\t\tRTE_DIM(test_params.slave_ports))\n\n/* Macro for iterating over every port that can be used as a slave\n * in this test and satisfy given condition.\n *\n * _i variable used as an index in test_params->slave_ports\n * _slave pointer to &test_params->slave_ports[_idx]\n * _condition condition that need to be checked\n */\n#define FOR_EACH_PORT_IF(_i, _port, _condition) FOR_EACH_PORT((_i), (_port)) \\\n\tif (!!(_condition))\n\n/* Macro for iterating over every port that is currently a slave of a bonded\n * device.\n * _i variable used as an index in test_params->slave_ports\n * _slave pointer to &test_params->slave_ports[_idx]\n * */\n#define FOR_EACH_SLAVE(_i, _slave) \\\n\tFOR_EACH_PORT_IF(_i, _slave, (_slave)->bonded != 0)\n\n/*\n * Returns packets from slaves TX queue.\n * slave slave port\n * buffer for packets\n * size size of buffer\n * return number of packets or negative error number\n */\nstatic int\nslave_get_pkts(struct slave_conf *slave, struct rte_mbuf **buf, uint16_t size)\n{\n\treturn rte_ring_dequeue_burst(slave->tx_queue, (void **)buf, size);\n}\n\n/*\n * Injects given packets into slaves RX queue.\n * slave slave port\n * buffer for packets\n * size number of packets to be injected\n * return number of queued packets or negative error number\n */\nstatic int\nslave_put_pkts(struct slave_conf *slave, struct rte_mbuf **buf, uint16_t size)\n{\n\treturn rte_ring_enqueue_burst(slave->rx_queue, (void **)buf, size);\n}\n\nstatic uint16_t\nbond_rx(struct rte_mbuf **buf, uint16_t size)\n{\n\treturn rte_eth_rx_burst(test_params.bonded_port_id, 0, buf, size);\n}\n\nstatic uint16_t\nbond_tx(struct rte_mbuf **buf, uint16_t size)\n{\n\treturn rte_eth_tx_burst(test_params.bonded_port_id, 0, buf, size);\n}\n\nstatic void\nfree_pkts(struct rte_mbuf **pkts, uint16_t count)\n{\n\tuint16_t i;\n\n\tfor (i = 0; i < count; i++) {\n\t\tif (pkts[i] != NULL)\n\t\t\trte_pktmbuf_free(pkts[i]);\n\t}\n}\n\nstatic int\nconfigure_ethdev(uint8_t port_id, uint8_t start)\n{\n\tTEST_ASSERT(rte_eth_dev_configure(port_id, 1, 1, &default_pmd_conf) == 0,\n\t\t\"Failed to configure device %u\", port_id);\n\n\tTEST_ASSERT(rte_eth_rx_queue_setup(port_id, 0, RX_RING_SIZE,\n\t\trte_eth_dev_socket_id(port_id), NULL, test_params.mbuf_pool) == 0,\n\t\t\"Failed to setup rx queue.\");\n\n\tTEST_ASSERT(rte_eth_tx_queue_setup(port_id, 0, TX_RING_SIZE,\n\t\trte_eth_dev_socket_id(port_id), NULL) == 0,\n\t\t\"Failed to setup tx queue.\");\n\n\tif (start) {\n\t\tTEST_ASSERT(rte_eth_dev_start(port_id) == 0,\n\t\t\"Failed to start device (%d).\", port_id);\n\t}\n\treturn 0;\n}\n\nstatic int\nadd_slave(struct slave_conf *slave, uint8_t start)\n{\n\tstruct ether_addr addr, addr_check;\n\n\t/* Some sanity check */\n\tRTE_VERIFY(test_params.slave_ports <= slave &&\n\t\tslave - test_params.slave_ports < (int)RTE_DIM(test_params.slave_ports));\n\tRTE_VERIFY(slave->bonded == 0);\n\tRTE_VERIFY(slave->port_id != INVALID_PORT_ID);\n\n\tether_addr_copy(&slave_mac_default, &addr);\n\taddr.addr_bytes[ETHER_ADDR_LEN - 1] = slave->port_id;\n\n\trte_eth_dev_mac_addr_remove(slave->port_id, &addr);\n\n\tTEST_ASSERT_SUCCESS(rte_eth_dev_mac_addr_add(slave->port_id, &addr, 0),\n\t\t\"Failed to set slave MAC address\");\n\n\tTEST_ASSERT_SUCCESS(rte_eth_bond_slave_add(test_params.bonded_port_id,\n\t\tslave->port_id),\n\t\t\t\"Failed to add slave (idx=%u, id=%u) to bonding (id=%u)\",\n\t\t\t(uint8_t)(slave - test_params.slave_ports), slave->port_id,\n\t\t\ttest_params.bonded_port_id);\n\n\tslave->bonded = 1;\n\tif (start) {\n\t\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(slave->port_id),\n\t\t\t\"Failed to start slave %u\", slave->port_id);\n\t}\n\n\trte_eth_macaddr_get(slave->port_id, &addr_check);\n\tTEST_ASSERT_EQUAL(is_same_ether_addr(&addr, &addr_check), 1,\n\t\t\t\"Slave MAC address is not as expected\");\n\n\tRTE_VERIFY(slave->lacp_parnter_state == 0);\n\treturn 0;\n}\n\nstatic int\nremove_slave(struct slave_conf *slave)\n{\n\tptrdiff_t slave_idx = slave - test_params.slave_ports;\n\n\tRTE_VERIFY(test_params.slave_ports <= slave &&\n\t\tslave_idx < (ptrdiff_t)RTE_DIM(test_params.slave_ports));\n\n\tRTE_VERIFY(slave->bonded == 1);\n\tRTE_VERIFY(slave->port_id != INVALID_PORT_ID);\n\n\tTEST_ASSERT_EQUAL(rte_ring_count(slave->rx_queue), 0,\n\t\t\"Slave %u tx queue not empty while removing from bonding.\",\n\t\tslave->port_id);\n\n\tTEST_ASSERT_EQUAL(rte_ring_count(slave->rx_queue), 0,\n\t\t\"Slave %u tx queue not empty while removing from bonding.\",\n\t\tslave->port_id);\n\n\tTEST_ASSERT_EQUAL(rte_eth_bond_slave_remove(test_params.bonded_port_id,\n\t\t\tslave->port_id), 0,\n\t\t\t\"Failed to remove slave (idx=%u, id=%u) from bonding (id=%u)\",\n\t\t\t(uint8_t)slave_idx, slave->port_id,\n\t\t\ttest_params.bonded_port_id);\n\n\tslave->bonded = 0;\n\tslave->lacp_parnter_state = 0;\n\treturn 0;\n}\n\nstatic int\ninitialize_bonded_device_with_slaves(uint8_t slave_count, uint8_t start)\n{\n\tuint8_t i;\n\n\tRTE_VERIFY(test_params.bonded_port_id != INVALID_PORT_ID);\n\n\tfor (i = 0; i < slave_count; i++) {\n\t\tTEST_ASSERT_SUCCESS(add_slave(&test_params.slave_ports[i], 1),\n\t\t\t\"Failed to add port %u to bonded device.\\n\",\n\t\t\ttest_params.slave_ports[i].port_id);\n\t}\n\n\t/* Reset mode 4 configuration */\n\trte_eth_bond_8023ad_setup(test_params.bonded_port_id, NULL);\n\trte_eth_promiscuous_disable(test_params.bonded_port_id);\n\n\tif (start)\n\t\tTEST_ASSERT_SUCCESS(rte_eth_dev_start(test_params.bonded_port_id),\n\t\t\t\"Failed to start bonded device\");\n\n\treturn TEST_SUCCESS;\n}\n\nstatic int\nremove_slaves_and_stop_bonded_device(void)\n{\n\tstruct slave_conf *slave;\n\tint retval;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\tuint8_t i;\n\n\trte_eth_dev_stop(test_params.bonded_port_id);\n\n\tFOR_EACH_SLAVE(i, slave)\n\t\tremove_slave(slave);\n\n\tretval = rte_eth_bond_slaves_get(test_params.bonded_port_id, slaves,\n\t\tRTE_DIM(slaves));\n\n\tTEST_ASSERT_EQUAL(retval, 0,\n\t\t\"Expected bonded device %u have 0 slaves but returned %d.\",\n\t\t\ttest_params.bonded_port_id, retval);\n\n\tFOR_EACH_PORT(i, slave) {\n\t\trte_eth_dev_stop(slave->port_id);\n\n\t\tTEST_ASSERT(slave->bonded == 0,\n\t\t\t\"Port id=%u is still marked as enslaved.\", slave->port_id);\n\t}\n\n\treturn TEST_SUCCESS;\n}\n\nstatic int\ntest_setup(void)\n{\n\tint retval, nb_mbuf_per_pool;\n\tchar name[RTE_ETH_NAME_MAX_LEN];\n\tstruct slave_conf *port;\n\tconst uint8_t socket_id = rte_socket_id();\n\tuint8_t i;\n\n\tif (test_params.mbuf_pool == NULL) {\n\t\tnb_mbuf_per_pool = TEST_RX_DESC_MAX + DEF_PKT_BURST +\n\t\t\t\t\tTEST_TX_DESC_MAX + MAX_PKT_BURST;\n\t\ttest_params.mbuf_pool = rte_pktmbuf_pool_create(\"TEST_MODE4\",\n\t\t\tnb_mbuf_per_pool, MBUF_CACHE_SIZE, 0,\n\t\t\tRTE_MBUF_DEFAULT_BUF_SIZE, socket_id);\n\n\t\tTEST_ASSERT(test_params.mbuf_pool != NULL,\n\t\t\t\"rte_mempool_create failed\\n\");\n\t}\n\n\t/* Create / initialize ring eth devs. */\n\tFOR_EACH_PORT(i, port) {\n\t\tport = &test_params.slave_ports[i];\n\n\t\tif (port->rx_queue == NULL) {\n\t\t\tretval = snprintf(name, RTE_DIM(name), SLAVE_RX_QUEUE_FMT, i);\n\t\t\tTEST_ASSERT(retval <= (int)RTE_DIM(name) - 1, \"Name too long\");\n\t\t\tport->rx_queue = rte_ring_create(name, RX_RING_SIZE, socket_id, 0);\n\t\t\tTEST_ASSERT(port->rx_queue != NULL,\n\t\t\t\t\"Failed to allocate rx ring '%s': %s\", name,\n\t\t\t\trte_strerror(rte_errno));\n\t\t}\n\n\t\tif (port->tx_queue == NULL) {\n\t\t\tretval = snprintf(name, RTE_DIM(name), SLAVE_TX_QUEUE_FMT, i);\n\t\t\tTEST_ASSERT(retval <= (int)RTE_DIM(name) - 1, \"Name too long\");\n\t\t\tport->tx_queue = rte_ring_create(name, TX_RING_SIZE, socket_id, 0);\n\t\t\tTEST_ASSERT_NOT_NULL(port->tx_queue,\n\t\t\t\t\"Failed to allocate tx ring '%s': %s\", name,\n\t\t\t\trte_strerror(rte_errno));\n\t\t}\n\n\t\tif (port->port_id == INVALID_PORT_ID) {\n\t\t\tretval = snprintf(name, RTE_DIM(name), SLAVE_DEV_NAME_FMT, i);\n\t\t\tTEST_ASSERT(retval < (int)RTE_DIM(name) - 1, \"Name too long\");\n\t\t\tretval = rte_eth_from_rings(name, &port->rx_queue, 1,\n\t\t\t\t\t&port->tx_queue, 1, socket_id);\n\t\t\tTEST_ASSERT(retval >= 0,\n\t\t\t\t\"Failed to create ring ethdev '%s'\\n\", name);\n\n\t\t\tport->port_id = rte_eth_dev_count() - 1;\n\t\t}\n\n\t\tretval = configure_ethdev(port->port_id, 1);\n\t\tTEST_ASSERT_SUCCESS(retval, \"Failed to configure virtual ethdev %s\\n\",\n\t\t\tname);\n\t}\n\n\tif (test_params.bonded_port_id == INVALID_PORT_ID) {\n\t\tretval = rte_eth_bond_create(BONDED_DEV_NAME, BONDING_MODE_8023AD,\n\t\t\t\tsocket_id);\n\n\t\tTEST_ASSERT(retval >= 0, \"Failed to create bonded ethdev %s\",\n\t\t\t\tBONDED_DEV_NAME);\n\n\t\ttest_params.bonded_port_id = retval;\n\t\tTEST_ASSERT_SUCCESS(configure_ethdev(test_params.bonded_port_id, 0),\n\t\t\t\t\"Failed to configure bonded ethdev %s\", BONDED_DEV_NAME);\n\t} else if (rte_eth_bond_mode_get(test_params.bonded_port_id) !=\n\t\t\tBONDING_MODE_8023AD) {\n\t\tTEST_ASSERT(rte_eth_bond_mode_set(test_params.bonded_port_id,\n\t\t\tBONDING_MODE_8023AD) == 0,\n\t\t\t\"Failed to set ethdev %d to mode %d\",\n\t\t\ttest_params.bonded_port_id, BONDING_MODE_8023AD);\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntestsuite_teardown(void)\n{\n\tstruct slave_conf *port;\n\tuint8_t i;\n\n\t/* Only stop ports.\n\t * Any cleanup/reset state is done when particular test is\n\t * started. */\n\n\trte_eth_dev_stop(test_params.bonded_port_id);\n\n\tFOR_EACH_PORT(i, port)\n\t\trte_eth_dev_stop(port->port_id);\n\n\treturn 0;\n}\n\n/*\n * Check if given LACP packet. If it is, make make replay packet to force\n * COLLECTING state.\n * return 0 when pkt is LACP frame, 1 if it is not slow frame, 2 if it is slow\n * frame but not LACP\n */\nstatic int\nmake_lacp_reply(struct slave_conf *slave, struct rte_mbuf *pkt)\n{\n\tstruct ether_hdr *hdr;\n\tstruct slow_protocol_frame *slow_hdr;\n\tstruct lacpdu *lacp;\n\n\t/* look for LACP */\n\thdr = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\tif (hdr->ether_type != rte_cpu_to_be_16(ETHER_TYPE_SLOW))\n\t\treturn 1;\n\n\tslow_hdr = rte_pktmbuf_mtod(pkt, struct slow_protocol_frame *);\n\t/* ignore packets of other types */\n\tif (slow_hdr->slow_protocol.subtype != SLOW_SUBTYPE_LACP)\n\t\treturn 2;\n\n\tslow_hdr = rte_pktmbuf_mtod(pkt, struct slow_protocol_frame *);\n\n\t/* Change source address to partner address */\n\tether_addr_copy(&parnter_mac_default, &slow_hdr->eth_hdr.s_addr);\n\tslow_hdr->eth_hdr.s_addr.addr_bytes[ETHER_ADDR_LEN - 1] = slave->port_id;\n\n\tlacp = (struct lacpdu *) &slow_hdr->slow_protocol;\n\t/* Save last received state */\n\tslave->lacp_parnter_state = lacp->actor.state;\n\t/* Change it into LACP replay by matching parameters. */\n\tmemcpy(&lacp->partner.port_params, &lacp->actor.port_params,\n\t\tsizeof(struct port_params));\n\n\tlacp->partner.state = lacp->actor.state;\n\n\tether_addr_copy(&parnter_system, &lacp->actor.port_params.system);\n\tlacp->actor.state = STATE_LACP_ACTIVE |\n\t\t\t\t\t\tSTATE_SYNCHRONIZATION |\n\t\t\t\t\t\tSTATE_AGGREGATION |\n\t\t\t\t\t\tSTATE_COLLECTING |\n\t\t\t\t\t\tSTATE_DISTRIBUTING;\n\n\treturn 0;\n}\n\n/*\n * Reads packets from given slave, search for LACP packet and reply them.\n *\n * Receives burst of packets from slave. Looks for LACP packet. Drops\n * all other packets. Prepares response LACP and sends it back.\n *\n * return number of LACP received and replied, -1 on error.\n */\nstatic int\nbond_handshake_reply(struct slave_conf *slave)\n{\n\tint retval;\n\tstruct rte_mbuf *rx_buf[MAX_PKT_BURST];\n\tstruct rte_mbuf *lacp_tx_buf[MAX_PKT_BURST];\n\tuint16_t lacp_tx_buf_cnt = 0, i;\n\n\tretval = slave_get_pkts(slave, rx_buf, RTE_DIM(rx_buf));\n\tTEST_ASSERT(retval >= 0, \"Getting slave %u packets failed.\",\n\t\t\tslave->port_id);\n\n\tfor (i = 0; i < (uint16_t)retval; i++) {\n\t\tif (make_lacp_reply(slave, rx_buf[i]) == 0) {\n\t\t\t/* reply with actor's LACP */\n\t\t\tlacp_tx_buf[lacp_tx_buf_cnt++] = rx_buf[i];\n\t\t} else\n\t\t\trte_pktmbuf_free(rx_buf[i]);\n\t}\n\n\tif (lacp_tx_buf_cnt == 0)\n\t\treturn 0;\n\n\tretval = slave_put_pkts(slave, lacp_tx_buf, lacp_tx_buf_cnt);\n\tif (retval <= lacp_tx_buf_cnt) {\n\t\t/* retval might be negative */\n\t\tfor (i = RTE_MAX(0, retval); retval < lacp_tx_buf_cnt; retval++)\n\t\t\trte_pktmbuf_free(lacp_tx_buf[i]);\n\t}\n\n\tTEST_ASSERT_EQUAL(retval, lacp_tx_buf_cnt,\n\t\t\"Failed to equeue lacp packets into slave %u tx queue.\",\n\t\tslave->port_id);\n\n\treturn lacp_tx_buf_cnt;\n}\n\n/*\n * Function check if given slave tx queue contains packets that make mode 4\n * handshake complete. It will drain slave queue.\n * return 0 if handshake not completed, 1 if handshake was complete,\n */\nstatic int\nbond_handshake_done(struct slave_conf *slave)\n{\n\tconst uint8_t expected_state = STATE_LACP_ACTIVE | STATE_SYNCHRONIZATION |\n\t\t\tSTATE_AGGREGATION | STATE_COLLECTING | STATE_DISTRIBUTING;\n\n\treturn slave->lacp_parnter_state == expected_state;\n}\n\nstatic unsigned\nbond_get_update_timeout_ms(void)\n{\n\tstruct rte_eth_bond_8023ad_conf conf;\n\n\trte_eth_bond_8023ad_conf_get(test_params.bonded_port_id, &conf);\n\treturn conf.update_timeout_ms;\n}\n\n/*\n * Exchanges LACP packets with partner to achieve dynamic port configuration.\n * return TEST_SUCCESS if initial handshake succeed, TEST_FAILED otherwise.\n */\nstatic int\nbond_handshake(void)\n{\n\tstruct slave_conf *slave;\n\tstruct rte_mbuf *buf[MAX_PKT_BURST];\n\tuint16_t nb_pkts;\n\tuint8_t all_slaves_done, i, j;\n\tuint8_t status[RTE_DIM(test_params.slave_ports)] = { 0 };\n\tconst unsigned delay = bond_get_update_timeout_ms();\n\n\t/* Exchange LACP frames */\n\tall_slaves_done = 0;\n\tfor (i = 0; i < 30 && all_slaves_done == 0; ++i) {\n\t\trte_delay_ms(delay);\n\n\t\tall_slaves_done = 1;\n\t\tFOR_EACH_SLAVE(j, slave) {\n\t\t\t/* If response already send, skip slave */\n\t\t\tif (status[j] != 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (bond_handshake_reply(slave) < 0) {\n\t\t\t\tall_slaves_done = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tstatus[j] = bond_handshake_done(slave);\n\t\t\tif (status[j] == 0)\n\t\t\t\tall_slaves_done = 0;\n\t\t}\n\n\t\tnb_pkts = bond_tx(NULL, 0);\n\t\tTEST_ASSERT_EQUAL(nb_pkts, 0, \"Packets transmitted unexpectedly\");\n\n\t\tnb_pkts = bond_rx(buf, RTE_DIM(buf));\n\t\tfree_pkts(buf, nb_pkts);\n\t\tTEST_ASSERT_EQUAL(nb_pkts, 0, \"Packets received unexpectedly\");\n\t}\n\t/* If response didn't send - report failure */\n\tTEST_ASSERT_EQUAL(all_slaves_done, 1, \"Bond handshake failed\\n\");\n\n\t/* If flags doesn't match - report failure */\n\treturn all_slaves_done = 1 ? TEST_SUCCESS : TEST_FAILED;\n}\n\n#define TEST_LACP_SLAVE_COUT RTE_DIM(test_params.slave_ports)\nstatic int\ntest_mode4_lacp(void)\n{\n\tint retval;\n\n\tretval = initialize_bonded_device_with_slaves(TEST_LACP_SLAVE_COUT, 1);\n\tTEST_ASSERT_SUCCESS(retval, \"Failed to initialize bonded device\");\n\n\t/* Test LACP handshake function */\n\tretval = bond_handshake();\n\tTEST_ASSERT_SUCCESS(retval, \"Initial handshake failed\");\n\n\tretval = remove_slaves_and_stop_bonded_device();\n\tTEST_ASSERT_SUCCESS(retval, \"Test cleanup failed.\");\n\n\treturn TEST_SUCCESS;\n}\n\nstatic int\ngenerate_packets(struct ether_addr *src_mac,\n\tstruct ether_addr *dst_mac, uint16_t count, struct rte_mbuf **buf)\n{\n\tuint16_t pktlen = PACKET_BURST_GEN_PKT_LEN;\n\tuint8_t vlan_enable = 0;\n\tuint16_t vlan_id = 0;\n\tuint8_t ip4_type = 1; /* 0 - ipv6 */\n\n\tuint16_t src_port = 10, dst_port = 20;\n\n\tuint32_t ip_src[4] = { [0 ... 2] = 0xDEADBEEF, [3] = IPv4(192, 168, 0, 1) };\n\tuint32_t ip_dst[4] = { [0 ... 2] = 0xFEEDFACE, [3] = IPv4(192, 168, 0, 2) };\n\n\tstruct ether_hdr pkt_eth_hdr;\n\tstruct udp_hdr pkt_udp_hdr;\n\tunion {\n\t\tstruct ipv4_hdr v4;\n\t\tstruct ipv6_hdr v6;\n\t} pkt_ip_hdr;\n\n\tint retval;\n\n\tinitialize_eth_header(&pkt_eth_hdr, src_mac, dst_mac, ip4_type,\n\t\t\tvlan_enable, vlan_id);\n\n\tif (ip4_type)\n\t\tinitialize_ipv4_header(&pkt_ip_hdr.v4, ip_src[3], ip_dst[3], pktlen);\n\telse\n\t\tinitialize_ipv6_header(&pkt_ip_hdr.v6, (uint8_t *)ip_src,\n\t\t\t(uint8_t *)&ip_dst, pktlen);\n\n\tinitialize_udp_header(&pkt_udp_hdr, src_port, dst_port, 16);\n\n\tretval = generate_packet_burst(test_params.mbuf_pool, buf,\n\t\t\t&pkt_eth_hdr, vlan_enable, &pkt_ip_hdr, 1, &pkt_udp_hdr,\n\t\t\tcount, pktlen, 1);\n\n\tif (retval > 0 && retval != count)\n\t\tfree_pkts(&buf[count - retval], retval);\n\n\tTEST_ASSERT_EQUAL(retval, count, \"Failed to generate %u packets\",\n\t\tcount);\n\n\treturn count;\n}\n\nstatic int\ngenerate_and_put_packets(struct slave_conf *slave, struct ether_addr *src_mac,\n\t\tstruct ether_addr *dst_mac, uint16_t count)\n{\n\tstruct rte_mbuf *pkts[MAX_PKT_BURST];\n\tint retval;\n\n\tretval = generate_packets(src_mac, dst_mac, count, pkts);\n\tif (retval != (int)count)\n\t\treturn retval;\n\n\tretval = slave_put_pkts(slave, pkts, count);\n\tif (retval > 0 && retval != count)\n\t\tfree_pkts(&pkts[retval], count - retval);\n\n\tTEST_ASSERT_EQUAL(retval, count,\n\t\t\"Failed to enqueue packets into slave %u RX queue\", slave->port_id);\n\n\treturn TEST_SUCCESS;\n}\n\nstatic int\ntest_mode4_rx(void)\n{\n\tstruct slave_conf *slave;\n\tuint16_t i, j;\n\n\tuint16_t expected_pkts_cnt;\n\tstruct rte_mbuf *pkts[MAX_PKT_BURST];\n\tint retval;\n\tunsigned delay;\n\n\tstruct ether_hdr *hdr;\n\n\tstruct ether_addr src_mac = { { 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00 } };\n\tstruct ether_addr dst_mac;\n\tstruct ether_addr bonded_mac;\n\n\tretval = initialize_bonded_device_with_slaves(TEST_PROMISC_SLAVE_COUNT, 1);\n\tTEST_ASSERT_SUCCESS(retval, \"Failed to initialize bonded device\");\n\n\tretval = bond_handshake();\n\tTEST_ASSERT_SUCCESS(retval, \"Initial handshake failed\");\n\n\trte_eth_macaddr_get(test_params.bonded_port_id, &bonded_mac);\n\tether_addr_copy(&bonded_mac, &dst_mac);\n\n\t/* Assert that dst address is not bonding address */\n\tdst_mac.addr_bytes[0]++;\n\n\t/* First try with promiscuous mode enabled.\n\t * Add 2 packets to each slave. First with bonding MAC address, second with\n\t * different. Check if we received all of them. */\n\trte_eth_promiscuous_enable(test_params.bonded_port_id);\n\n\texpected_pkts_cnt = 0;\n\tFOR_EACH_SLAVE(i, slave) {\n\t\tretval = generate_and_put_packets(slave, &src_mac, &bonded_mac, 1);\n\t\tTEST_ASSERT_SUCCESS(retval, \"Failed to enqueue packets to slave %u\",\n\t\t\tslave->port_id);\n\n\t\tretval = generate_and_put_packets(slave, &src_mac, &dst_mac, 1);\n\t\tTEST_ASSERT_SUCCESS(retval, \"Failed to enqueue packets to slave %u\",\n\t\t\tslave->port_id);\n\n\t\t/* Expect 2 packets per slave */\n\t\texpected_pkts_cnt += 2;\n\t}\n\n\tretval = rte_eth_rx_burst(test_params.bonded_port_id, 0, pkts,\n\t\tRTE_DIM(pkts));\n\n\tif (retval == expected_pkts_cnt) {\n\t\tint cnt[2] = { 0, 0 };\n\n\t\tfor (i = 0; i < expected_pkts_cnt; i++) {\n\t\t\thdr = rte_pktmbuf_mtod(pkts[i], struct ether_hdr *);\n\t\t\tcnt[is_same_ether_addr(&hdr->d_addr, &bonded_mac)]++;\n\t\t}\n\n\t\tfree_pkts(pkts, expected_pkts_cnt);\n\n\t\t/* For division by 2 expected_pkts_cnt must be even */\n\t\tRTE_VERIFY((expected_pkts_cnt & 1) == 0);\n\t\tTEST_ASSERT(cnt[0] == expected_pkts_cnt / 2 &&\n\t\t\tcnt[1] == expected_pkts_cnt / 2,\n\t\t\t\"Expected %u packets with the same MAC and %u with different but \"\n\t\t\t\"got %u with the same and %u with diffrent MAC\",\n\t\t\texpected_pkts_cnt / 2, expected_pkts_cnt / 2, cnt[1], cnt[0]);\n\t} else if (retval > 0)\n\t\tfree_pkts(pkts, retval);\n\n\tTEST_ASSERT_EQUAL(retval, expected_pkts_cnt,\n\t\t\"Expected %u packets but received only %d\", expected_pkts_cnt, retval);\n\n\t/* Now, disable promiscuous mode. When promiscuous mode is disabled we\n\t * expect to receive only packets that are directed to bonding port. */\n\trte_eth_promiscuous_disable(test_params.bonded_port_id);\n\n\texpected_pkts_cnt = 0;\n\tFOR_EACH_SLAVE(i, slave) {\n\t\tretval = generate_and_put_packets(slave, &src_mac, &bonded_mac, 1);\n\t\tTEST_ASSERT_SUCCESS(retval, \"Failed to enqueue packets to slave %u\",\n\t\t\tslave->port_id);\n\n\t\tretval = generate_and_put_packets(slave, &src_mac, &dst_mac, 1);\n\t\tTEST_ASSERT_SUCCESS(retval, \"Failed to enqueue packets to slave %u\",\n\t\t\tslave->port_id);\n\n\t\t/* Expect only one packet per slave */\n\t\texpected_pkts_cnt += 1;\n\t}\n\n\tretval = rte_eth_rx_burst(test_params.bonded_port_id, 0, pkts,\n\t\tRTE_DIM(pkts));\n\n\tif (retval == expected_pkts_cnt) {\n\t\tint eq_cnt = 0;\n\n\t\tfor (i = 0; i < expected_pkts_cnt; i++) {\n\t\t\thdr = rte_pktmbuf_mtod(pkts[i], struct ether_hdr *);\n\t\t\teq_cnt += is_same_ether_addr(&hdr->d_addr, &bonded_mac);\n\t\t}\n\n\t\tfree_pkts(pkts, expected_pkts_cnt);\n\t\tTEST_ASSERT_EQUAL(eq_cnt, expected_pkts_cnt, \"Packet address mismatch\");\n\t} else if (retval > 0)\n\t\tfree_pkts(pkts, retval);\n\n\tTEST_ASSERT_EQUAL(retval, expected_pkts_cnt,\n\t\t\"Expected %u packets but received only %d\", expected_pkts_cnt, retval);\n\n\t/* Link down test: simulate link down for first slave. */\n\tdelay = bond_get_update_timeout_ms();\n\n\tuint8_t slave_down_id = INVALID_PORT_ID;\n\n\t/* Find first slave and make link down on it*/\n\tFOR_EACH_SLAVE(i, slave) {\n\t\trte_eth_dev_set_link_down(slave->port_id);\n\t\tslave_down_id = slave->port_id;\n\t\tbreak;\n\t}\n\n\tRTE_VERIFY(slave_down_id != INVALID_PORT_ID);\n\n\t/* Give some time to rearrange bonding */\n\tfor (i = 0; i < 3; i++) {\n\t\trte_delay_ms(delay);\n\t\tbond_handshake();\n\t}\n\n\tTEST_ASSERT_SUCCESS(bond_handshake(), \"Handshake after link down failed\");\n\n\t/* Put packet to each slave */\n\tFOR_EACH_SLAVE(i, slave) {\n\t\tvoid *pkt = NULL;\n\n\t\tdst_mac.addr_bytes[ETHER_ADDR_LEN - 1] = slave->port_id;\n\t\tretval = generate_and_put_packets(slave, &src_mac, &dst_mac, 1);\n\t\tTEST_ASSERT_SUCCESS(retval, \"Failed to generate test packet burst.\");\n\n\t\tsrc_mac.addr_bytes[ETHER_ADDR_LEN - 1] = slave->port_id;\n\t\tretval = generate_and_put_packets(slave, &src_mac, &bonded_mac, 1);\n\t\tTEST_ASSERT_SUCCESS(retval, \"Failed to generate test packet burst.\");\n\n\t\tretval = bond_rx(pkts, RTE_DIM(pkts));\n\n\t\t/* Clean anything */\n\t\tif (retval > 0)\n\t\t\tfree_pkts(pkts, retval);\n\n\t\twhile (rte_ring_dequeue(slave->rx_queue, (void **)&pkt) == 0)\n\t\t\trte_pktmbuf_free(pkt);\n\n\t\tif (slave_down_id == slave->port_id)\n\t\t\tTEST_ASSERT_EQUAL(retval, 0, \"Packets received unexpectedly.\");\n\t\telse\n\t\t\tTEST_ASSERT_NOT_EQUAL(retval, 0,\n\t\t\t\t\"Expected to receive some packets on slave %u.\",\n\t\t\t\tslave->port_id);\n\t\trte_eth_dev_start(slave->port_id);\n\n\t\tfor (j = 0; j < 5; j++) {\n\t\t\tTEST_ASSERT(bond_handshake_reply(slave) >= 0,\n\t\t\t\t\"Handshake after link up\");\n\n\t\t\tif (bond_handshake_done(slave) == 1)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tTEST_ASSERT(j < 5, \"Failed to agregate slave after link up\");\n\t}\n\n\tremove_slaves_and_stop_bonded_device();\n\treturn TEST_SUCCESS;\n}\n\nstatic int\ntest_mode4_tx_burst(void)\n{\n\tstruct slave_conf *slave;\n\tuint16_t i, j;\n\n\tuint16_t exp_pkts_cnt, pkts_cnt = 0;\n\tstruct rte_mbuf *pkts[MAX_PKT_BURST];\n\tint retval;\n\tunsigned delay;\n\n\tstruct ether_addr dst_mac = { { 0x00, 0xFF, 0x00, 0xFF, 0x00, 0x00 } };\n\tstruct ether_addr bonded_mac;\n\n\tretval = initialize_bonded_device_with_slaves(TEST_TX_SLAVE_COUNT, 1);\n\tTEST_ASSERT_SUCCESS(retval, \"Failed to initialize bonded device\");\n\n\tretval = bond_handshake();\n\tTEST_ASSERT_SUCCESS(retval, \"Initial handshake failed\");\n\n\trte_eth_macaddr_get(test_params.bonded_port_id, &bonded_mac);\n\n\t/* Prepare burst */\n\tfor (pkts_cnt = 0; pkts_cnt < RTE_DIM(pkts); pkts_cnt++) {\n\t\tdst_mac.addr_bytes[ETHER_ADDR_LEN - 1] = pkts_cnt;\n\t\tretval = generate_packets(&bonded_mac, &dst_mac, 1, &pkts[pkts_cnt]);\n\n\t\tif (retval != 1)\n\t\t\tfree_pkts(pkts, pkts_cnt);\n\n\t\tTEST_ASSERT_EQUAL(retval, 1, \"Failed to generate packet %u\", pkts_cnt);\n\t}\n\texp_pkts_cnt = pkts_cnt;\n\n\t/* Transmit packets on bonded device */\n\tretval = bond_tx(pkts, pkts_cnt);\n\tif (retval > 0 && retval < pkts_cnt)\n\t\tfree_pkts(&pkts[retval], pkts_cnt - retval);\n\n\tTEST_ASSERT_EQUAL(retval, pkts_cnt, \"TX on bonded device failed\");\n\n\t/* Check if packets were transmitted properly. Every slave should have\n\t * at least one packet, and sum must match. Under normal operation\n\t * there should be no LACP nor MARKER frames. */\n\tpkts_cnt = 0;\n\tFOR_EACH_SLAVE(i, slave) {\n\t\tuint16_t normal_cnt, slow_cnt;\n\n\t\tretval = slave_get_pkts(slave, pkts, RTE_DIM(pkts));\n\t\tnormal_cnt = 0;\n\t\tslow_cnt = 0;\n\n\t\tfor (j = 0; j < retval; j++) {\n\t\t\tif (make_lacp_reply(slave, pkts[j]) == 1)\n\t\t\t\tnormal_cnt++;\n\t\t\telse\n\t\t\t\tslow_cnt++;\n\t\t}\n\n\t\tfree_pkts(pkts, normal_cnt + slow_cnt);\n\t\tTEST_ASSERT_EQUAL(slow_cnt, 0,\n\t\t\t\"slave %u unexpectedly transmitted %d SLOW packets\", slave->port_id,\n\t\t\tslow_cnt);\n\n\t\tTEST_ASSERT_NOT_EQUAL(normal_cnt, 0,\n\t\t\t\"slave %u did not transmitted any packets\", slave->port_id);\n\n\t\tpkts_cnt += normal_cnt;\n\t}\n\n\tTEST_ASSERT_EQUAL(exp_pkts_cnt, pkts_cnt,\n\t\t\"Expected %u packets but transmitted only %d\", exp_pkts_cnt, pkts_cnt);\n\n\t/* Link down test:\n\t * simulate link down for first slave. */\n\tdelay = bond_get_update_timeout_ms();\n\n\tuint8_t slave_down_id = INVALID_PORT_ID;\n\n\tFOR_EACH_SLAVE(i, slave) {\n\t\trte_eth_dev_set_link_down(slave->port_id);\n\t\tslave_down_id = slave->port_id;\n\t\tbreak;\n\t}\n\n\tRTE_VERIFY(slave_down_id != INVALID_PORT_ID);\n\n\t/* Give some time to rearrange bonding. */\n\tfor (i = 0; i < 3; i++) {\n\t\tbond_handshake();\n\t\trte_delay_ms(delay);\n\t}\n\n\tTEST_ASSERT_SUCCESS(bond_handshake(), \"Handshake after link down failed\");\n\n\t/* Prepare burst. */\n\tfor (pkts_cnt = 0; pkts_cnt < RTE_DIM(pkts); pkts_cnt++) {\n\t\tdst_mac.addr_bytes[ETHER_ADDR_LEN - 1] = pkts_cnt;\n\t\tretval = generate_packets(&bonded_mac, &dst_mac, 1, &pkts[pkts_cnt]);\n\n\t\tif (retval != 1)\n\t\t\tfree_pkts(pkts, pkts_cnt);\n\n\t\tTEST_ASSERT_EQUAL(retval, 1, \"Failed to generate test packet %u\",\n\t\t\tpkts_cnt);\n\t}\n\texp_pkts_cnt = pkts_cnt;\n\n\t/* Transmit packets on bonded device. */\n\tretval = bond_tx(pkts, pkts_cnt);\n\tif (retval > 0 && retval < pkts_cnt)\n\t\tfree_pkts(&pkts[retval], pkts_cnt - retval);\n\n\tTEST_ASSERT_EQUAL(retval, pkts_cnt, \"TX on bonded device failed\");\n\n\t/* Check if packets was transmitted properly. Every slave should have\n\t * at least one packet, and sum must match. Under normal operation\n\t * there should be no LACP nor MARKER frames. */\n\tpkts_cnt = 0;\n\tFOR_EACH_SLAVE(i, slave) {\n\t\tuint16_t normal_cnt, slow_cnt;\n\n\t\tretval = slave_get_pkts(slave, pkts, RTE_DIM(pkts));\n\t\tnormal_cnt = 0;\n\t\tslow_cnt = 0;\n\n\t\tfor (j = 0; j < retval; j++) {\n\t\t\tif (make_lacp_reply(slave, pkts[j]) == 1)\n\t\t\t\tnormal_cnt++;\n\t\t\telse\n\t\t\t\tslow_cnt++;\n\t\t}\n\n\t\tfree_pkts(pkts, normal_cnt + slow_cnt);\n\n\t\tif (slave_down_id == slave->port_id) {\n\t\t\tTEST_ASSERT_EQUAL(normal_cnt + slow_cnt, 0,\n\t\t\t\t\"slave %u enexpectedly transmitted %u packets\",\n\t\t\t\tnormal_cnt + slow_cnt, slave->port_id);\n\t\t} else {\n\t\t\tTEST_ASSERT_EQUAL(slow_cnt, 0,\n\t\t\t\t\"slave %u unexpectedly transmitted %d SLOW packets\",\n\t\t\t\tslave->port_id, slow_cnt);\n\n\t\t\tTEST_ASSERT_NOT_EQUAL(normal_cnt, 0,\n\t\t\t\t\"slave %u did not transmitted any packets\", slave->port_id);\n\t\t}\n\n\t\tpkts_cnt += normal_cnt;\n\t}\n\n\tTEST_ASSERT_EQUAL(exp_pkts_cnt, pkts_cnt,\n\t\t\"Expected %u packets but transmitted only %d\", exp_pkts_cnt, pkts_cnt);\n\n\treturn remove_slaves_and_stop_bonded_device();\n}\n\nstatic void\ninit_marker(struct rte_mbuf *pkt, struct slave_conf *slave)\n{\n\tstruct marker_header *marker_hdr = rte_pktmbuf_mtod(pkt,\n\t\t\tstruct marker_header *);\n\n\t/* Copy multicast destination address */\n\tether_addr_copy(&slow_protocol_mac_addr, &marker_hdr->eth_hdr.d_addr);\n\n\t/* Init source address */\n\tether_addr_copy(&parnter_mac_default, &marker_hdr->eth_hdr.s_addr);\n\tmarker_hdr->eth_hdr.s_addr.addr_bytes[ETHER_ADDR_LEN-1] = slave->port_id;\n\n\tmarker_hdr->eth_hdr.ether_type = rte_cpu_to_be_16(ETHER_TYPE_SLOW);\n\n\tmarker_hdr->marker.subtype = SLOW_SUBTYPE_MARKER;\n\tmarker_hdr->marker.version_number = 1;\n\tmarker_hdr->marker.tlv_type_marker = MARKER_TLV_TYPE_INFO;\n\tmarker_hdr->marker.info_length =\n\t\t\toffsetof(struct marker, reserved_90) -\n\t\t\toffsetof(struct marker, requester_port);\n\tRTE_VERIFY(marker_hdr->marker.info_length == 16);\n\tmarker_hdr->marker.requester_port = slave->port_id + 1;\n\tmarker_hdr->marker.tlv_type_terminator = TLV_TYPE_TERMINATOR_INFORMATION;\n\tmarker_hdr->marker.terminator_length = 0;\n}\n\nstatic int\ntest_mode4_marker(void)\n{\n\tstruct slave_conf *slave;\n\tstruct rte_mbuf *pkts[MAX_PKT_BURST];\n\tstruct rte_mbuf *marker_pkt;\n\tstruct marker_header *marker_hdr;\n\n\tunsigned delay;\n\tint retval;\n\tuint16_t nb_pkts;\n\tuint8_t i, j;\n\tconst uint16_t ethtype_slow_be = rte_be_to_cpu_16(ETHER_TYPE_SLOW);\n\n\tretval = initialize_bonded_device_with_slaves(TEST_MARKER_SLAVE_COUT, 1);\n\tTEST_ASSERT_SUCCESS(retval, \"Failed to initialize bonded device\");\n\n\t/* Test LACP handshake function */\n\tretval = bond_handshake();\n\tTEST_ASSERT_SUCCESS(retval, \"Initial handshake failed\");\n\n\tdelay = bond_get_update_timeout_ms();\n\tFOR_EACH_SLAVE(i, slave) {\n\t\tmarker_pkt = rte_pktmbuf_alloc(test_params.mbuf_pool);\n\t\tTEST_ASSERT_NOT_NULL(marker_pkt, \"Failed to allocate marker packet\");\n\t\tinit_marker(marker_pkt, slave);\n\n\t\tretval = slave_put_pkts(slave, &marker_pkt, 1);\n\t\tif (retval != 1)\n\t\t\trte_pktmbuf_free(marker_pkt);\n\n\t\tTEST_ASSERT_EQUAL(retval, 1,\n\t\t\t\"Failed to send marker packet to slave %u\", slave->port_id);\n\n\t\tfor (j = 0; j < 20; ++j) {\n\t\t\trte_delay_ms(delay);\n\t\t\tretval = rte_eth_rx_burst(test_params.bonded_port_id, 0, pkts,\n\t\t\t\tRTE_DIM(pkts));\n\n\t\t\tif (retval > 0)\n\t\t\t\tfree_pkts(pkts, retval);\n\n\t\t\tTEST_ASSERT_EQUAL(retval, 0, \"Received packets unexpectedly\");\n\n\t\t\tretval = rte_eth_tx_burst(test_params.bonded_port_id, 0, NULL, 0);\n\t\t\tTEST_ASSERT_EQUAL(retval, 0,\n\t\t\t\t\"Requested TX of 0 packets but %d transmitted\", retval);\n\n\t\t\t/* Check if LACP packet was send by state machines\n\t\t\t First and only packet must be a maker response */\n\t\t\tretval = slave_get_pkts(slave, pkts, MAX_PKT_BURST);\n\t\t\tif (retval == 0)\n\t\t\t\tcontinue;\n\t\t\tif (retval > 1)\n\t\t\t\tfree_pkts(pkts, retval);\n\n\t\t\tTEST_ASSERT_EQUAL(retval, 1, \"failed to get slave packets\");\n\t\t\tnb_pkts = retval;\n\n\t\t\tmarker_hdr = rte_pktmbuf_mtod(pkts[0], struct marker_header *);\n\t\t\t/* Check if it's slow packet*/\n\t\t\tif (marker_hdr->eth_hdr.ether_type != ethtype_slow_be)\n\t\t\t\tretval = -1;\n\t\t\t/* Check if it's marker packet */\n\t\t\telse if (marker_hdr->marker.subtype != SLOW_SUBTYPE_MARKER)\n\t\t\t\tretval = -2;\n\t\t\telse if (marker_hdr->marker.tlv_type_marker != MARKER_TLV_TYPE_RESP)\n\t\t\t\tretval = -3;\n\n\t\t\tfree_pkts(pkts, nb_pkts);\n\n\t\t\tTEST_ASSERT_NOT_EQUAL(retval, -1, \"Unexpected protocol type\");\n\t\t\tTEST_ASSERT_NOT_EQUAL(retval, -2, \"Unexpected sub protocol type\");\n\t\t\tTEST_ASSERT_NOT_EQUAL(retval, -3, \"Unexpected marker type\");\n\t\t\tbreak;\n\t\t}\n\n\t\tTEST_ASSERT(j < 20, \"Marker response not found\");\n\t}\n\n\tretval = remove_slaves_and_stop_bonded_device();\n\tTEST_ASSERT_SUCCESS(retval,\t\"Test cleanup failed.\");\n\n\treturn TEST_SUCCESS;\n}\n\nstatic int\ntest_mode4_expired(void)\n{\n\tstruct slave_conf *slave, *exp_slave = NULL;\n\tstruct rte_mbuf *pkts[MAX_PKT_BURST];\n\tint retval;\n\tuint32_t old_delay;\n\n\tuint8_t i;\n\tuint16_t j;\n\n\tstruct rte_eth_bond_8023ad_conf conf;\n\n\tretval = initialize_bonded_device_with_slaves(TEST_EXPIRED_SLAVE_COUNT, 1);\n\t/* Set custom timeouts to make test last shorter. */\n\trte_eth_bond_8023ad_conf_get(test_params.bonded_port_id, &conf);\n\tconf.fast_periodic_ms = 100;\n\tconf.slow_periodic_ms = 600;\n\tconf.short_timeout_ms = 300;\n\tconf.long_timeout_ms = 900;\n\tconf.aggregate_wait_timeout_ms = 200;\n\tconf.tx_period_ms = 100;\n\told_delay = conf.update_timeout_ms;\n\tconf.update_timeout_ms = 10;\n\trte_eth_bond_8023ad_setup(test_params.bonded_port_id, &conf);\n\n\t/* Wait for new settings to be applied. */\n\tfor (i = 0; i < old_delay/conf.update_timeout_ms * 2; i++) {\n\t\tFOR_EACH_SLAVE(j, slave)\n\t\t\tbond_handshake_reply(slave);\n\n\t\trte_delay_ms(conf.update_timeout_ms);\n\t}\n\n\tretval = bond_handshake();\n\tTEST_ASSERT_SUCCESS(retval, \"Initial handshake failed\");\n\n\t/* Find first slave */\n\tFOR_EACH_SLAVE(i, slave) {\n\t\texp_slave = slave;\n\t\tbreak;\n\t}\n\n\tRTE_VERIFY(exp_slave != NULL);\n\n\t/* When one of partners do not send or respond to LACP frame in\n\t * conf.long_timeout_ms time, internal state machines should detect this\n\t * and transit to expired state. */\n\tfor (j = 0; j < conf.long_timeout_ms/conf.update_timeout_ms + 2; j++) {\n\t\trte_delay_ms(conf.update_timeout_ms);\n\n\t\tretval = bond_tx(NULL, 0);\n\t\tTEST_ASSERT_EQUAL(retval, 0, \"Unexpectedly received %d packets\",\n\t\t\tretval);\n\n\t\tFOR_EACH_SLAVE(i, slave) {\n\t\t\tretval = bond_handshake_reply(slave);\n\t\t\tTEST_ASSERT(retval >= 0, \"Handshake failed\");\n\n\t\t\t/* Remove replay for slave that supose to be expired. */\n\t\t\tif (slave == exp_slave) {\n\t\t\t\twhile (rte_ring_count(slave->rx_queue) > 0) {\n\t\t\t\t\tvoid *pkt = NULL;\n\n\t\t\t\t\trte_ring_dequeue(slave->rx_queue, &pkt);\n\t\t\t\t\trte_pktmbuf_free(pkt);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tretval = bond_rx(pkts, RTE_DIM(pkts));\n\t\tif (retval > 0)\n\t\t\tfree_pkts(pkts, retval);\n\n\t\tTEST_ASSERT_EQUAL(retval, 0, \"Unexpectedly received %d packets\",\n\t\t\tretval);\n\t}\n\n\t/* After test only expected slave should be in EXPIRED state */\n\tFOR_EACH_SLAVE(i, slave) {\n\t\tif (slave == exp_slave)\n\t\t\tTEST_ASSERT(slave->lacp_parnter_state & STATE_EXPIRED,\n\t\t\t\t\"Slave %u should be in expired.\", slave->port_id);\n\t\telse\n\t\t\tTEST_ASSERT_EQUAL(bond_handshake_done(slave), 1,\n\t\t\t\t\"Slave %u should be operational.\", slave->port_id);\n\t}\n\n\tretval = remove_slaves_and_stop_bonded_device();\n\tTEST_ASSERT_SUCCESS(retval, \"Test cleanup failed.\");\n\n\treturn TEST_SUCCESS;\n}\n\nstatic int\ncheck_environment(void)\n{\n\tstruct slave_conf *port;\n\tuint8_t i, env_state;\n\tuint8_t slaves[RTE_DIM(test_params.slave_ports)];\n\tint slaves_count;\n\n\tenv_state = 0;\n\tFOR_EACH_PORT(i, port) {\n\t\tif (rte_ring_count(port->rx_queue) != 0)\n\t\t\tenv_state |= 0x01;\n\n\t\tif (rte_ring_count(port->tx_queue) != 0)\n\t\t\tenv_state |= 0x02;\n\n\t\tif (port->bonded != 0)\n\t\t\tenv_state |= 0x04;\n\n\t\tif (port->lacp_parnter_state != 0)\n\t\t\tenv_state |= 0x08;\n\n\t\tif (env_state != 0)\n\t\t\tbreak;\n\t}\n\n\tslaves_count = rte_eth_bond_slaves_get(test_params.bonded_port_id,\n\t\t\tslaves, RTE_DIM(slaves));\n\n\tif (slaves_count != 0)\n\t\tenv_state |= 0x10;\n\n\tTEST_ASSERT_EQUAL(env_state, 0,\n\t\t\"Environment not clean (port %u):%s%s%s%s%s\",\n\t\tport->port_id,\n\t\tenv_state & 0x01 ? \" slave rx queue not clean\" : \"\",\n\t\tenv_state & 0x02 ? \" slave tx queue not clean\" : \"\",\n\t\tenv_state & 0x04 ? \" port marked as enslaved\" : \"\",\n\t\tenv_state & 0x80 ? \" slave state is not reset\" : \"\",\n\t\tenv_state & 0x10 ? \" slave count not equal 0\" : \".\");\n\n\n\treturn TEST_SUCCESS;\n}\n\nstatic int\ntest_mode4_executor(int (*test_func)(void))\n{\n\tstruct slave_conf *port;\n\tint test_result;\n\tuint8_t i;\n\tvoid *pkt;\n\n\t/* Check if environment is clean. Fail to launch a test if there was\n\t * a critical error before that prevented to reset environment. */\n\tTEST_ASSERT_SUCCESS(check_environment(),\n\t\t\"Refusing to launch test in dirty environment.\");\n\n\tRTE_VERIFY(test_func != NULL);\n\ttest_result = (*test_func)();\n\n\t/* If test succeed check if environment wast left in good condition. */\n\tif (test_result == TEST_SUCCESS)\n\t\ttest_result = check_environment();\n\n\t/* Reset environment in case test failed to do that. */\n\tif (test_result != TEST_SUCCESS) {\n\t\tTEST_ASSERT_SUCCESS(remove_slaves_and_stop_bonded_device(),\n\t\t\t\"Failed to stop bonded device\");\n\n\t\tFOR_EACH_PORT(i, port) {\n\t\t\twhile (rte_ring_count(port->rx_queue) != 0) {\n\t\t\t\tif (rte_ring_dequeue(port->rx_queue, &pkt) == 0)\n\t\t\t\t\trte_pktmbuf_free(pkt);\n\t\t\t}\n\n\t\t\twhile (rte_ring_count(port->tx_queue) != 0) {\n\t\t\t\tif (rte_ring_dequeue(port->tx_queue, &pkt) == 0)\n\t\t\t\t\trte_pktmbuf_free(pkt);\n\t\t\t}\n\t\t}\n\t}\n\n\treturn test_result;\n}\n\nstatic int\ntest_mode4_lacp_wrapper(void)\n{\n\treturn test_mode4_executor(&test_mode4_lacp);\n}\n\nstatic int\ntest_mode4_marker_wrapper(void)\n{\n\treturn test_mode4_executor(&test_mode4_marker);\n}\n\nstatic int\ntest_mode4_rx_wrapper(void)\n{\n\treturn test_mode4_executor(&test_mode4_rx);\n}\n\nstatic int\ntest_mode4_tx_burst_wrapper(void)\n{\n\treturn test_mode4_executor(&test_mode4_tx_burst);\n}\n\nstatic int\ntest_mode4_expired_wrapper(void)\n{\n\treturn test_mode4_executor(&test_mode4_expired);\n}\n\nstatic struct unit_test_suite link_bonding_mode4_test_suite = {\n\t.suite_name = \"Link Bonding mode 4 Unit Test Suite\",\n\t.setup = test_setup,\n\t.teardown = testsuite_teardown,\n\t.unit_test_cases = {\n\t\tTEST_CASE_NAMED(\"test_mode4_lacp\", test_mode4_lacp_wrapper),\n\t\tTEST_CASE_NAMED(\"test_mode4_rx\", test_mode4_rx_wrapper),\n\t\tTEST_CASE_NAMED(\"test_mode4_tx_burst\", test_mode4_tx_burst_wrapper),\n\t\tTEST_CASE_NAMED(\"test_mode4_marker\", test_mode4_marker_wrapper),\n\t\tTEST_CASE_NAMED(\"test_mode4_expired\", test_mode4_expired_wrapper),\n\t\t{ NULL, NULL, NULL, NULL, NULL } /**< NULL terminate unit test array */\n\t}\n};\n\nstatic int\ntest_link_bonding_mode4(void)\n{\n\treturn unit_test_suite_runner(&link_bonding_mode4_test_suite);\n}\n\nstatic struct test_command link_bonding_cmd = {\n\t.command = \"link_bonding_mode4_autotest\",\n\t.callback = test_link_bonding_mode4,\n};\n\nREGISTER_TEST_COMMAND(link_bonding_cmd);\n" }, { "path": "app/test/test_logs.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#define RTE_LOGTYPE_TESTAPP1 RTE_LOGTYPE_USER1\n#define RTE_LOGTYPE_TESTAPP2 RTE_LOGTYPE_USER2\n\n/*\n * Logs\n * ====\n *\n * - Enable log types.\n * - Set log level.\n * - Send logs with different types and levels, some should not be displayed.\n */\n\nstatic int\ntest_logs(void)\n{\n\t/* enable these logs type */\n\trte_set_log_type(RTE_LOGTYPE_TESTAPP1, 1);\n\trte_set_log_type(RTE_LOGTYPE_TESTAPP2, 1);\n\n\t/* log in debug level */\n\trte_set_log_level(RTE_LOG_DEBUG);\n\tRTE_LOG(DEBUG, TESTAPP1, \"this is a debug level message\\n\");\n\tRTE_LOG(INFO, TESTAPP1, \"this is a info level message\\n\");\n\tRTE_LOG(WARNING, TESTAPP1, \"this is a warning level message\\n\");\n\n\t/* log in info level */\n\trte_set_log_level(RTE_LOG_INFO);\n\tRTE_LOG(DEBUG, TESTAPP2, \"debug level message (not displayed)\\n\");\n\tRTE_LOG(INFO, TESTAPP2, \"this is a info level message\\n\");\n\tRTE_LOG(WARNING, TESTAPP2, \"this is a warning level message\\n\");\n\n\t/* disable one log type */\n\trte_set_log_type(RTE_LOGTYPE_TESTAPP2, 0);\n\n\t/* log in debug level */\n\trte_set_log_level(RTE_LOG_DEBUG);\n\tRTE_LOG(DEBUG, TESTAPP1, \"this is a debug level message\\n\");\n\tRTE_LOG(DEBUG, TESTAPP2, \"debug level message (not displayed)\\n\");\n\n\trte_log_dump_history(stdout);\n\n\treturn 0;\n}\n\nstatic struct test_command logs_cmd = {\n\t.command = \"logs_autotest\",\n\t.callback = test_logs,\n};\nREGISTER_TEST_COMMAND(logs_cmd);\n" }, { "path": "app/test/test_lpm.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#include \"rte_lpm.h\"\n#include \"test_lpm_routes.h\"\n\n#define TEST_LPM_ASSERT(cond) do { \\\n\tif (!(cond)) { \\\n\t\tprintf(\"Error at line %d: \\n\", __LINE__); \\\n\t\treturn -1; \\\n\t} \\\n} while(0)\n\ntypedef int32_t (* rte_lpm_test)(void);\n\nstatic int32_t test0(void);\nstatic int32_t test1(void);\nstatic int32_t test2(void);\nstatic int32_t test3(void);\nstatic int32_t test4(void);\nstatic int32_t test5(void);\nstatic int32_t test6(void);\nstatic int32_t test7(void);\nstatic int32_t test8(void);\nstatic int32_t test9(void);\nstatic int32_t test10(void);\nstatic int32_t test11(void);\nstatic int32_t test12(void);\nstatic int32_t test13(void);\nstatic int32_t test14(void);\nstatic int32_t test15(void);\nstatic int32_t test16(void);\nstatic int32_t test17(void);\nstatic int32_t perf_test(void);\n\nrte_lpm_test tests[] = {\n/* Test Cases */\n\ttest0,\n\ttest1,\n\ttest2,\n\ttest3,\n\ttest4,\n\ttest5,\n\ttest6,\n\ttest7,\n\ttest8,\n\ttest9,\n\ttest10,\n\ttest11,\n\ttest12,\n\ttest13,\n\ttest14,\n\ttest15,\n\ttest16,\n\ttest17,\n\tperf_test,\n};\n\n#define NUM_LPM_TESTS (sizeof(tests)/sizeof(tests[0]))\n#define MAX_DEPTH 32\n#define MAX_RULES 256\n#define PASS 0\n\n/*\n * Check that rte_lpm_create fails gracefully for incorrect user input\n * arguments\n */\nint32_t\ntest0(void)\n{\n\tstruct rte_lpm *lpm = NULL;\n\n\t/* rte_lpm_create: lpm name == NULL */\n\tlpm = rte_lpm_create(NULL, SOCKET_ID_ANY, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm == NULL);\n\n\t/* rte_lpm_create: max_rules = 0 */\n\t/* Note: __func__ inserts the function name, in this case \"test0\". */\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, 0, 0);\n\tTEST_LPM_ASSERT(lpm == NULL);\n\n\t/* socket_id < -1 is invalid */\n\tlpm = rte_lpm_create(__func__, -2, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm == NULL);\n\n\treturn PASS;\n}\n\n/*\n * Create lpm table then delete lpm table 100 times\n * Use a slightly different rules size each time\n * */\nint32_t\ntest1(void)\n{\n\tstruct rte_lpm *lpm = NULL;\n\tint32_t i;\n\n\t/* rte_lpm_free: Free NULL */\n\tfor (i = 0; i < 100; i++) {\n\t\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES - i, 0);\n\t\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t\trte_lpm_free(lpm);\n\t}\n\n\t/* Can not test free so return success */\n\treturn PASS;\n}\n\n/*\n * Call rte_lpm_free for NULL pointer user input. Note: free has no return and\n * therefore it is impossible to check for failure but this test is added to\n * increase function coverage metrics and to validate that freeing null does\n * not crash.\n */\nint32_t\ntest2(void)\n{\n\tstruct rte_lpm *lpm = NULL;\n\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, RTE_LPM_HEAP);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\trte_lpm_free(lpm);\n\trte_lpm_free(NULL);\n\treturn PASS;\n}\n\n/*\n * Check that rte_lpm_add fails gracefully for incorrect user input arguments\n */\nint32_t\ntest3(void)\n{\n\tstruct rte_lpm *lpm = NULL;\n\tuint32_t ip = IPv4(0, 0, 0, 0);\n\tuint8_t depth = 24, next_hop = 100;\n\tint32_t status = 0;\n\n\t/* rte_lpm_add: lpm == NULL */\n\tstatus = rte_lpm_add(NULL, ip, depth, next_hop);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/*Create vaild lpm to use in rest of test. */\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* rte_lpm_add: depth < 1 */\n\tstatus = rte_lpm_add(lpm, ip, 0, next_hop);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/* rte_lpm_add: depth > MAX_DEPTH */\n\tstatus = rte_lpm_add(lpm, ip, (MAX_DEPTH + 1), next_hop);\n\tTEST_LPM_ASSERT(status < 0);\n\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Check that rte_lpm_delete fails gracefully for incorrect user input\n * arguments\n */\nint32_t\ntest4(void)\n{\n\tstruct rte_lpm *lpm = NULL;\n\tuint32_t ip = IPv4(0, 0, 0, 0);\n\tuint8_t depth = 24;\n\tint32_t status = 0;\n\n\t/* rte_lpm_delete: lpm == NULL */\n\tstatus = rte_lpm_delete(NULL, ip, depth);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/*Create vaild lpm to use in rest of test. */\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* rte_lpm_delete: depth < 1 */\n\tstatus = rte_lpm_delete(lpm, ip, 0);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/* rte_lpm_delete: depth > MAX_DEPTH */\n\tstatus = rte_lpm_delete(lpm, ip, (MAX_DEPTH + 1));\n\tTEST_LPM_ASSERT(status < 0);\n\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Check that rte_lpm_lookup fails gracefully for incorrect user input\n * arguments\n */\nint32_t\ntest5(void)\n{\n#if defined(RTE_LIBRTE_LPM_DEBUG)\n\tstruct rte_lpm *lpm = NULL;\n\tuint32_t ip = IPv4(0, 0, 0, 0);\n\tuint8_t next_hop_return = 0;\n\tint32_t status = 0;\n\n\t/* rte_lpm_lookup: lpm == NULL */\n\tstatus = rte_lpm_lookup(NULL, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/*Create vaild lpm to use in rest of test. */\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* rte_lpm_lookup: depth < 1 */\n\tstatus = rte_lpm_lookup(lpm, ip, NULL);\n\tTEST_LPM_ASSERT(status < 0);\n\n\trte_lpm_free(lpm);\n#endif\n\treturn PASS;\n}\n\n\n\n/*\n * Call add, lookup and delete for a single rule with depth <= 24\n */\nint32_t\ntest6(void)\n{\n\tstruct rte_lpm *lpm = NULL;\n\tuint32_t ip = IPv4(0, 0, 0, 0);\n\tuint8_t depth = 24, next_hop_add = 100, next_hop_return = 0;\n\tint32_t status = 0;\n\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Call add, lookup and delete for a single rule with depth > 24\n */\n\nint32_t\ntest7(void)\n{\n\t__m128i ipx4;\n\tuint16_t hop[4];\n\tstruct rte_lpm *lpm = NULL;\n\tuint32_t ip = IPv4(0, 0, 0, 0);\n\tuint8_t depth = 32, next_hop_add = 100, next_hop_return = 0;\n\tint32_t status = 0;\n\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tipx4 = _mm_set_epi32(ip, ip + 0x100, ip - 0x100, ip);\n\trte_lpm_lookupx4(lpm, ipx4, hop, UINT16_MAX);\n\tTEST_LPM_ASSERT(hop[0] == next_hop_add);\n\tTEST_LPM_ASSERT(hop[1] == UINT16_MAX);\n\tTEST_LPM_ASSERT(hop[2] == UINT16_MAX);\n\tTEST_LPM_ASSERT(hop[3] == next_hop_add);\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Use rte_lpm_add to add rules which effect only the second half of the lpm\n * table. Use all possible depths ranging from 1..32. Set the next hop = to the\n * depth. Check lookup hit for on every add and check for lookup miss on the\n * first half of the lpm table after each add. Finally delete all rules going\n * backwards (i.e. from depth = 32 ..1) and carry out a lookup after each\n * delete. The lookup should return the next_hop_add value related to the\n * previous depth value (i.e. depth -1).\n */\nint32_t\ntest8(void)\n{\n\t__m128i ipx4;\n\tuint16_t hop[4];\n\tstruct rte_lpm *lpm = NULL;\n\tuint32_t ip1 = IPv4(127, 255, 255, 255), ip2 = IPv4(128, 0, 0, 0);\n\tuint8_t depth, next_hop_add, next_hop_return;\n\tint32_t status = 0;\n\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* Loop with rte_lpm_add. */\n\tfor (depth = 1; depth <= 32; depth++) {\n\t\t/* Let the next_hop_add value = depth. Just for change. */\n\t\tnext_hop_add = depth;\n\n\t\tstatus = rte_lpm_add(lpm, ip2, depth, next_hop_add);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\t/* Check IP in first half of tbl24 which should be empty. */\n\t\tstatus = rte_lpm_lookup(lpm, ip1, &next_hop_return);\n\t\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\t\tstatus = rte_lpm_lookup(lpm, ip2, &next_hop_return);\n\t\tTEST_LPM_ASSERT((status == 0) &&\n\t\t\t(next_hop_return == next_hop_add));\n\n\t\tipx4 = _mm_set_epi32(ip2, ip1, ip2, ip1);\n\t\trte_lpm_lookupx4(lpm, ipx4, hop, UINT16_MAX);\n\t\tTEST_LPM_ASSERT(hop[0] == UINT16_MAX);\n\t\tTEST_LPM_ASSERT(hop[1] == next_hop_add);\n\t\tTEST_LPM_ASSERT(hop[2] == UINT16_MAX);\n\t\tTEST_LPM_ASSERT(hop[3] == next_hop_add);\n\t}\n\n\t/* Loop with rte_lpm_delete. */\n\tfor (depth = 32; depth >= 1; depth--) {\n\t\tnext_hop_add = (uint8_t) (depth - 1);\n\n\t\tstatus = rte_lpm_delete(lpm, ip2, depth);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\tstatus = rte_lpm_lookup(lpm, ip2, &next_hop_return);\n\n\t\tif (depth != 1) {\n\t\t\tTEST_LPM_ASSERT((status == 0) &&\n\t\t\t\t(next_hop_return == next_hop_add));\n\t\t}\n\t\telse {\n\t\t\tTEST_LPM_ASSERT(status == -ENOENT);\n\t\t}\n\n\t\tstatus = rte_lpm_lookup(lpm, ip1, &next_hop_return);\n\t\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\t\tipx4 = _mm_set_epi32(ip1, ip1, ip2, ip2);\n\t\trte_lpm_lookupx4(lpm, ipx4, hop, UINT16_MAX);\n\t\tif (depth != 1) {\n\t\t\tTEST_LPM_ASSERT(hop[0] == next_hop_add);\n\t\t\tTEST_LPM_ASSERT(hop[1] == next_hop_add);\n\t\t} else {\n\t\t\tTEST_LPM_ASSERT(hop[0] == UINT16_MAX);\n\t\t\tTEST_LPM_ASSERT(hop[1] == UINT16_MAX);\n\t\t}\n\t\tTEST_LPM_ASSERT(hop[2] == UINT16_MAX);\n\t\tTEST_LPM_ASSERT(hop[3] == UINT16_MAX);\n\t}\n\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * - Add & lookup to hit invalid TBL24 entry\n * - Add & lookup to hit valid TBL24 entry not extended\n * - Add & lookup to hit valid extended TBL24 entry with invalid TBL8 entry\n * - Add & lookup to hit valid extended TBL24 entry with valid TBL8 entry\n *\n */\nint32_t\ntest9(void)\n{\n\tstruct rte_lpm *lpm = NULL;\n\tuint32_t ip, ip_1, ip_2;\n\tuint8_t depth, depth_1, depth_2, next_hop_add, next_hop_add_1,\n\t\tnext_hop_add_2, next_hop_return;\n\tint32_t status = 0;\n\n\t/* Add & lookup to hit invalid TBL24 entry */\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 24;\n\tnext_hop_add = 100;\n\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_delete_all(lpm);\n\n\t/* Add & lookup to hit valid TBL24 entry not extended */\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 23;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tdepth = 24;\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tdepth = 24;\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tdepth = 23;\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_delete_all(lpm);\n\n\t/* Add & lookup to hit valid extended TBL24 entry with invalid TBL8\n\t * entry */\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 32;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tip = IPv4(128, 0, 0, 5);\n\tdepth = 32;\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 32;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_delete_all(lpm);\n\n\t/* Add & lookup to hit valid extended TBL24 entry with valid TBL8\n\t * entry */\n\tip_1 = IPv4(128, 0, 0, 0);\n\tdepth_1 = 25;\n\tnext_hop_add_1 = 101;\n\n\tip_2 = IPv4(128, 0, 0, 5);\n\tdepth_2 = 32;\n\tnext_hop_add_2 = 102;\n\n\tnext_hop_return = 0;\n\n\tstatus = rte_lpm_add(lpm, ip_1, depth_1, next_hop_add_1);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip_1, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add_1));\n\n\tstatus = rte_lpm_add(lpm, ip_2, depth_2, next_hop_add_2);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip_2, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add_2));\n\n\tstatus = rte_lpm_delete(lpm, ip_2, depth_2);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip_2, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add_1));\n\n\tstatus = rte_lpm_delete(lpm, ip_1, depth_1);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip_1, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n\n/*\n * - Add rule that covers a TBL24 range previously invalid & lookup (& delete &\n * lookup)\n * - Add rule that extends a TBL24 invalid entry & lookup (& delete & lookup)\n * - Add rule that extends a TBL24 valid entry & lookup for both rules (&\n * delete & lookup)\n * - Add rule that updates the next hop in TBL24 & lookup (& delete & lookup)\n * - Add rule that updates the next hop in TBL8 & lookup (& delete & lookup)\n * - Delete a rule that is not present in the TBL24 & lookup\n * - Delete a rule that is not present in the TBL8 & lookup\n *\n */\nint32_t\ntest10(void)\n{\n\n\tstruct rte_lpm *lpm = NULL;\n\tuint32_t ip;\n\tuint8_t depth, next_hop_add, next_hop_return;\n\tint32_t status = 0;\n\n\t/* Add rule that covers a TBL24 range previously invalid & lookup\n\t * (& delete & lookup) */\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, RTE_LPM_HEAP);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 16;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_delete_all(lpm);\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 25;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\trte_lpm_delete_all(lpm);\n\n\t/* Add rule that extends a TBL24 valid entry & lookup for both rules\n\t * (& delete & lookup) */\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 24;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tip = IPv4(128, 0, 0, 10);\n\tdepth = 32;\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tip = IPv4(128, 0, 0, 0);\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 24;\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\tip = IPv4(128, 0, 0, 10);\n\tdepth = 32;\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_delete_all(lpm);\n\n\t/* Add rule that updates the next hop in TBL24 & lookup\n\t * (& delete & lookup) */\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 24;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_delete_all(lpm);\n\n\t/* Add rule that updates the next hop in TBL8 & lookup\n\t * (& delete & lookup) */\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 32;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_delete_all(lpm);\n\n\t/* Delete a rule that is not present in the TBL24 & lookup */\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 24;\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status < 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_delete_all(lpm);\n\n\t/* Delete a rule that is not present in the TBL8 & lookup */\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 32;\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status < 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Add two rules, lookup to hit the more specific one, lookup to hit the less\n * specific one delete the less specific rule and lookup previous values again;\n * add a more specific rule than the existing rule, lookup again\n *\n * */\nint32_t\ntest11(void)\n{\n\n\tstruct rte_lpm *lpm = NULL;\n\tuint32_t ip;\n\tuint8_t depth, next_hop_add, next_hop_return;\n\tint32_t status = 0;\n\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 24;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tip = IPv4(128, 0, 0, 10);\n\tdepth = 32;\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tip = IPv4(128, 0, 0, 0);\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 24;\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\tip = IPv4(128, 0, 0, 10);\n\tdepth = 32;\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Add an extended rule (i.e. depth greater than 24, lookup (hit), delete,\n * lookup (miss) in a for loop of 1000 times. This will check tbl8 extension\n * and contraction.\n *\n * */\n\nint32_t\ntest12(void)\n{\n\t__m128i ipx4;\n\tuint16_t hop[4];\n\tstruct rte_lpm *lpm = NULL;\n\tuint32_t ip, i;\n\tuint8_t depth, next_hop_add, next_hop_return;\n\tint32_t status = 0;\n\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 32;\n\tnext_hop_add = 100;\n\n\tfor (i = 0; i < 1000; i++) {\n\t\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\t\tTEST_LPM_ASSERT((status == 0) &&\n\t\t\t\t(next_hop_return == next_hop_add));\n\n\t\tipx4 = _mm_set_epi32(ip, ip + 1, ip, ip - 1);\n\t\trte_lpm_lookupx4(lpm, ipx4, hop, UINT16_MAX);\n\t\tTEST_LPM_ASSERT(hop[0] == UINT16_MAX);\n\t\tTEST_LPM_ASSERT(hop[1] == next_hop_add);\n\t\tTEST_LPM_ASSERT(hop[2] == UINT16_MAX);\n\t\tTEST_LPM_ASSERT(hop[3] == next_hop_add);\n\n\t\tstatus = rte_lpm_delete(lpm, ip, depth);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\t\tTEST_LPM_ASSERT(status == -ENOENT);\n\t}\n\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Add a rule to tbl24, lookup (hit), then add a rule that will extend this\n * tbl24 entry, lookup (hit). delete the rule that caused the tbl24 extension,\n * lookup (miss) and repeat for loop of 1000 times. This will check tbl8\n * extension and contraction.\n *\n * */\n\nint32_t\ntest13(void)\n{\n\tstruct rte_lpm *lpm = NULL;\n\tuint32_t ip, i;\n\tuint8_t depth, next_hop_add_1, next_hop_add_2, next_hop_return;\n\tint32_t status = 0;\n\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tip = IPv4(128, 0, 0, 0);\n\tdepth = 24;\n\tnext_hop_add_1 = 100;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add_1);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add_1));\n\n\tdepth = 32;\n\tnext_hop_add_2 = 101;\n\n\tfor (i = 0; i < 1000; i++) {\n\t\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add_2);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\t\tTEST_LPM_ASSERT((status == 0) &&\n\t\t\t\t(next_hop_return == next_hop_add_2));\n\n\t\tstatus = rte_lpm_delete(lpm, ip, depth);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\t\tTEST_LPM_ASSERT((status == 0) &&\n\t\t\t\t(next_hop_return == next_hop_add_1));\n\t}\n\n\tdepth = 24;\n\n\tstatus = rte_lpm_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Fore TBL8 extension exhaustion. Add 256 rules that require a tbl8 extension.\n * No more tbl8 extensions will be allowed. Now add one more rule that required\n * a tbl8 extension and get fail.\n * */\nint32_t\ntest14(void)\n{\n\n\t/* We only use depth = 32 in the loop below so we must make sure\n\t * that we have enough storage for all rules at that depth*/\n\n\tstruct rte_lpm *lpm = NULL;\n\tuint32_t ip;\n\tuint8_t depth, next_hop_add, next_hop_return;\n\tint32_t status = 0;\n\n\t/* Add enough space for 256 rules for every depth */\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, 256 * 32, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tdepth = 32;\n\tnext_hop_add = 100;\n\tip = IPv4(0, 0, 0, 0);\n\n\t/* Add 256 rules that require a tbl8 extension */\n\tfor (; ip <= IPv4(0, 0, 255, 0); ip += 256) {\n\t\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\tstatus = rte_lpm_lookup(lpm, ip, &next_hop_return);\n\t\tTEST_LPM_ASSERT((status == 0) &&\n\t\t\t\t(next_hop_return == next_hop_add));\n\t}\n\n\t/* All tbl8 extensions have been used above. Try to add one more and\n\t * we get a fail */\n\tip = IPv4(1, 0, 0, 0);\n\tdepth = 32;\n\n\tstatus = rte_lpm_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status < 0);\n\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Sequence of operations for find existing lpm table\n *\n * - create table\n * - find existing table: hit\n * - find non-existing table: miss\n *\n */\nint32_t\ntest15(void)\n{\n\tstruct rte_lpm *lpm = NULL, *result = NULL;\n\n\t/* Create lpm */\n\tlpm = rte_lpm_create(\"lpm_find_existing\", SOCKET_ID_ANY, 256 * 32, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* Try to find existing lpm */\n\tresult = rte_lpm_find_existing(\"lpm_find_existing\");\n\tTEST_LPM_ASSERT(result == lpm);\n\n\t/* Try to find non-existing lpm */\n\tresult = rte_lpm_find_existing(\"lpm_find_non_existing\");\n\tTEST_LPM_ASSERT(result == NULL);\n\n\t/* Cleanup. */\n\trte_lpm_delete_all(lpm);\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * test failure condition of overloading the tbl8 so no more will fit\n * Check we get an error return value in that case\n */\nint32_t\ntest16(void)\n{\n\tuint32_t ip;\n\tstruct rte_lpm *lpm = rte_lpm_create(__func__, SOCKET_ID_ANY,\n\t\t\t256 * 32, 0);\n\n\t/* ip loops through all possibilities for top 24 bits of address */\n\tfor (ip = 0; ip < 0xFFFFFF; ip++){\n\t\t/* add an entry within a different tbl8 each time, since\n\t\t * depth >24 and the top 24 bits are different */\n\t\tif (rte_lpm_add(lpm, (ip << 8) + 0xF0, 30, 0) < 0)\n\t\t\tbreak;\n\t}\n\n\tif (ip != RTE_LPM_TBL8_NUM_GROUPS) {\n\t\tprintf(\"Error, unexpected failure with filling tbl8 groups\\n\");\n\t\tprintf(\"Failed after %u additions, expected after %u\\n\",\n\t\t\t\t(unsigned)ip, (unsigned)RTE_LPM_TBL8_NUM_GROUPS);\n\t}\n\n\trte_lpm_free(lpm);\n\treturn 0;\n}\n\n/*\n * Test for overwriting of tbl8:\n * - add rule /32 and lookup\n * - add new rule /24 and lookup\n *\t- add third rule /25 and lookup\n *\t- lookup /32 and /24 rule to ensure the table has not been overwritten.\n */\nint32_t\ntest17(void)\n{\n\tstruct rte_lpm *lpm = NULL;\n\tconst uint32_t ip_10_32 = IPv4(10, 10, 10, 2);\n\tconst uint32_t ip_10_24 = IPv4(10, 10, 10, 0);\n\tconst uint32_t ip_20_25 = IPv4(10, 10, 20, 2);\n\tconst uint8_t d_ip_10_32 = 32,\n\t\t\td_ip_10_24 = 24,\n\t\t\td_ip_20_25 = 25;\n\tconst uint8_t next_hop_ip_10_32 = 100,\n\t\t\tnext_hop_ip_10_24 = 105,\n\t\t\tnext_hop_ip_20_25 = 111;\n\tuint8_t next_hop_return = 0;\n\tint32_t status = 0;\n\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, MAX_RULES, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tif ((status = rte_lpm_add(lpm, ip_10_32, d_ip_10_32,\n\t\t\tnext_hop_ip_10_32)) < 0)\n\t\treturn -1;\n\n\tstatus = rte_lpm_lookup(lpm, ip_10_32, &next_hop_return);\n\tuint8_t test_hop_10_32 = next_hop_return;\n\tTEST_LPM_ASSERT(status == 0);\n\tTEST_LPM_ASSERT(next_hop_return == next_hop_ip_10_32);\n\n\tif ((status = rte_lpm_add(lpm, ip_10_24, d_ip_10_24,\n\t\t\tnext_hop_ip_10_24)) < 0)\n\t\t\treturn -1;\n\n\tstatus = rte_lpm_lookup(lpm, ip_10_24, &next_hop_return);\n\tuint8_t test_hop_10_24 = next_hop_return;\n\tTEST_LPM_ASSERT(status == 0);\n\tTEST_LPM_ASSERT(next_hop_return == next_hop_ip_10_24);\n\n\tif ((status = rte_lpm_add(lpm, ip_20_25, d_ip_20_25,\n\t\t\tnext_hop_ip_20_25)) < 0)\n\t\treturn -1;\n\n\tstatus = rte_lpm_lookup(lpm, ip_20_25, &next_hop_return);\n\tuint8_t test_hop_20_25 = next_hop_return;\n\tTEST_LPM_ASSERT(status == 0);\n\tTEST_LPM_ASSERT(next_hop_return == next_hop_ip_20_25);\n\n\tif (test_hop_10_32 == test_hop_10_24) {\n\t\tprintf(\"Next hop return equal\\n\");\n\t\treturn -1;\n\t}\n\n\tif (test_hop_10_24 == test_hop_20_25){\n\t\tprintf(\"Next hop return equal\\n\");\n\t\treturn -1;\n\t}\n\n\tstatus = rte_lpm_lookup(lpm, ip_10_32, &next_hop_return);\n\tTEST_LPM_ASSERT(status == 0);\n\tTEST_LPM_ASSERT(next_hop_return == next_hop_ip_10_32);\n\n\tstatus = rte_lpm_lookup(lpm, ip_10_24, &next_hop_return);\n\tTEST_LPM_ASSERT(status == 0);\n\tTEST_LPM_ASSERT(next_hop_return == next_hop_ip_10_24);\n\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Lookup performance test\n */\n\n#define ITERATIONS (1 << 10)\n#define BATCH_SIZE (1 << 12)\n#define BULK_SIZE 32\n\nstatic void\nprint_route_distribution(const struct route_rule *table, uint32_t n)\n{\n\tunsigned i, j;\n\n\tprintf(\"Route distribution per prefix width: \\n\");\n\tprintf(\"DEPTH QUANTITY (PERCENT)\\n\");\n\tprintf(\"--------------------------- \\n\");\n\n\t/* Count depths. */\n\tfor(i = 1; i <= 32; i++) {\n\t\tunsigned depth_counter = 0;\n\t\tdouble percent_hits;\n\n\t\tfor (j = 0; j < n; j++)\n\t\t\tif (table[j].depth == (uint8_t) i)\n\t\t\t\tdepth_counter++;\n\n\t\tpercent_hits = ((double)depth_counter)/((double)n) * 100;\n\t\tprintf(\"%.2u%15u (%.2f)\\n\", i, depth_counter, percent_hits);\n\t}\n\tprintf(\"\\n\");\n}\n\nint32_t\nperf_test(void)\n{\n\tstruct rte_lpm *lpm = NULL;\n\tuint64_t begin, total_time, lpm_used_entries = 0;\n\tunsigned i, j;\n\tuint8_t next_hop_add = 0xAA, next_hop_return = 0;\n\tint status = 0;\n\tuint64_t cache_line_counter = 0;\n\tint64_t count = 0;\n\n\trte_srand(rte_rdtsc());\n\n\tprintf(\"No. routes = %u\\n\", (unsigned) NUM_ROUTE_ENTRIES);\n\n\tprint_route_distribution(large_route_table, (uint32_t) NUM_ROUTE_ENTRIES);\n\n\tlpm = rte_lpm_create(__func__, SOCKET_ID_ANY, 1000000, 0);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* Measue add. */\n\tbegin = rte_rdtsc();\n\n\tfor (i = 0; i < NUM_ROUTE_ENTRIES; i++) {\n\t\tif (rte_lpm_add(lpm, large_route_table[i].ip,\n\t\t\t\tlarge_route_table[i].depth, next_hop_add) == 0)\n\t\t\tstatus++;\n\t}\n\t/* End Timer. */\n\ttotal_time = rte_rdtsc() - begin;\n\n\tprintf(\"Unique added entries = %d\\n\", status);\n\t/* Obtain add statistics. */\n\tfor (i = 0; i < RTE_LPM_TBL24_NUM_ENTRIES; i++) {\n\t\tif (lpm->tbl24[i].valid)\n\t\t\tlpm_used_entries++;\n\n\t\tif (i % 32 == 0){\n\t\t\tif ((uint64_t)count < lpm_used_entries) {\n\t\t\t\tcache_line_counter++;\n\t\t\t\tcount = lpm_used_entries;\n\t\t\t}\n\t\t}\n\t}\n\n\tprintf(\"Used table 24 entries = %u (%g%%)\\n\",\n\t\t\t(unsigned) lpm_used_entries,\n\t\t\t(lpm_used_entries * 100.0) / RTE_LPM_TBL24_NUM_ENTRIES);\n\tprintf(\"64 byte Cache entries used = %u (%u bytes)\\n\",\n\t\t\t(unsigned) cache_line_counter, (unsigned) cache_line_counter * 64);\n\n\tprintf(\"Average LPM Add: %g cycles\\n\", (double)total_time / NUM_ROUTE_ENTRIES);\n\n\t/* Measure single Lookup */\n\ttotal_time = 0;\n\tcount = 0;\n\n\tfor (i = 0; i < ITERATIONS; i ++) {\n\t\tstatic uint32_t ip_batch[BATCH_SIZE];\n\n\t\tfor (j = 0; j < BATCH_SIZE; j ++)\n\t\t\tip_batch[j] = rte_rand();\n\n\t\t/* Lookup per batch */\n\t\tbegin = rte_rdtsc();\n\n\t\tfor (j = 0; j < BATCH_SIZE; j ++) {\n\t\t\tif (rte_lpm_lookup(lpm, ip_batch[j], &next_hop_return) != 0)\n\t\t\t\tcount++;\n\t\t}\n\n\t\ttotal_time += rte_rdtsc() - begin;\n\n\t}\n\tprintf(\"Average LPM Lookup: %.1f cycles (fails = %.1f%%)\\n\",\n\t\t\t(double)total_time / ((double)ITERATIONS * BATCH_SIZE),\n\t\t\t(count * 100.0) / (double)(ITERATIONS * BATCH_SIZE));\n\n\t/* Measure bulk Lookup */\n\ttotal_time = 0;\n\tcount = 0;\n\tfor (i = 0; i < ITERATIONS; i ++) {\n\t\tstatic uint32_t ip_batch[BATCH_SIZE];\n\t\tuint16_t next_hops[BULK_SIZE];\n\n\t\t/* Create array of random IP addresses */\n\t\tfor (j = 0; j < BATCH_SIZE; j ++)\n\t\t\tip_batch[j] = rte_rand();\n\n\t\t/* Lookup per batch */\n\t\tbegin = rte_rdtsc();\n\t\tfor (j = 0; j < BATCH_SIZE; j += BULK_SIZE) {\n\t\t\tunsigned k;\n\t\t\trte_lpm_lookup_bulk(lpm, &ip_batch[j], next_hops, BULK_SIZE);\n\t\t\tfor (k = 0; k < BULK_SIZE; k++)\n\t\t\t\tif (unlikely(!(next_hops[k] & RTE_LPM_LOOKUP_SUCCESS)))\n\t\t\t\t\tcount++;\n\t\t}\n\n\t\ttotal_time += rte_rdtsc() - begin;\n\t}\n\tprintf(\"BULK LPM Lookup: %.1f cycles (fails = %.1f%%)\\n\",\n\t\t\t(double)total_time / ((double)ITERATIONS * BATCH_SIZE),\n\t\t\t(count * 100.0) / (double)(ITERATIONS * BATCH_SIZE));\n\n\t/* Measure LookupX4 */\n\ttotal_time = 0;\n\tcount = 0;\n\tfor (i = 0; i < ITERATIONS; i++) {\n\t\tstatic uint32_t ip_batch[BATCH_SIZE];\n\t\tuint16_t next_hops[4];\n\n\t\t/* Create array of random IP addresses */\n\t\tfor (j = 0; j < BATCH_SIZE; j++)\n\t\t\tip_batch[j] = rte_rand();\n\n\t\t/* Lookup per batch */\n\t\tbegin = rte_rdtsc();\n\t\tfor (j = 0; j < BATCH_SIZE; j += RTE_DIM(next_hops)) {\n\t\t\tunsigned k;\n\t\t\t__m128i ipx4;\n\n\t\t\tipx4 = _mm_loadu_si128((__m128i *)(ip_batch + j));\n\t\t\tipx4 = *(__m128i *)(ip_batch + j);\n\t\t\trte_lpm_lookupx4(lpm, ipx4, next_hops, UINT16_MAX);\n\t\t\tfor (k = 0; k < RTE_DIM(next_hops); k++)\n\t\t\t\tif (unlikely(next_hops[k] == UINT16_MAX))\n\t\t\t\t\tcount++;\n\t\t}\n\n\t\ttotal_time += rte_rdtsc() - begin;\n\t}\n\tprintf(\"LPM LookupX4: %.1f cycles (fails = %.1f%%)\\n\",\n\t\t\t(double)total_time / ((double)ITERATIONS * BATCH_SIZE),\n\t\t\t(count * 100.0) / (double)(ITERATIONS * BATCH_SIZE));\n\n\t/* Delete */\n\tstatus = 0;\n\tbegin = rte_rdtsc();\n\n\tfor (i = 0; i < NUM_ROUTE_ENTRIES; i++) {\n\t\t/* rte_lpm_delete(lpm, ip, depth) */\n\t\tstatus += rte_lpm_delete(lpm, large_route_table[i].ip,\n\t\t\t\tlarge_route_table[i].depth);\n\t}\n\n\ttotal_time += rte_rdtsc() - begin;\n\n\tprintf(\"Average LPM Delete: %g cycles\\n\",\n\t\t\t(double)total_time / NUM_ROUTE_ENTRIES);\n\n\trte_lpm_delete_all(lpm);\n\trte_lpm_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Do all unit and performance tests.\n */\n\nstatic int\ntest_lpm(void)\n{\n\tunsigned i;\n\tint status, global_status = 0;\n\n\tfor (i = 0; i < NUM_LPM_TESTS; i++) {\n\t\tstatus = tests[i]();\n\t\tif (status < 0) {\n\t\t\tprintf(\"ERROR: LPM Test %s: FAIL\\n\", RTE_STR(tests[i]));\n\t\t\tglobal_status = status;\n\t\t}\n\t}\n\n\treturn global_status;\n}\n\nstatic struct test_command lpm_cmd = {\n\t.command = \"lpm_autotest\",\n\t.callback = test_lpm,\n};\nREGISTER_TEST_COMMAND(lpm_cmd);\n" }, { "path": "app/test/test_lpm6.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"test.h\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_lpm6.h\"\n#include \"test_lpm6_routes.h\"\n\n#define TEST_LPM_ASSERT(cond) do { \\\n\tif (!(cond)) { \\\n\t\tprintf(\"Error at line %d: \\n\", __LINE__); \\\n\t\treturn -1; \\\n\t} \\\n} while(0)\n\ntypedef int32_t (* rte_lpm6_test)(void);\n\nstatic int32_t test0(void);\nstatic int32_t test1(void);\nstatic int32_t test2(void);\nstatic int32_t test3(void);\nstatic int32_t test4(void);\nstatic int32_t test5(void);\nstatic int32_t test6(void);\nstatic int32_t test7(void);\nstatic int32_t test8(void);\nstatic int32_t test9(void);\nstatic int32_t test10(void);\nstatic int32_t test11(void);\nstatic int32_t test12(void);\nstatic int32_t test13(void);\nstatic int32_t test14(void);\nstatic int32_t test15(void);\nstatic int32_t test16(void);\nstatic int32_t test17(void);\nstatic int32_t test18(void);\nstatic int32_t test19(void);\nstatic int32_t test20(void);\nstatic int32_t test21(void);\nstatic int32_t test22(void);\nstatic int32_t test23(void);\nstatic int32_t test24(void);\nstatic int32_t test25(void);\nstatic int32_t test26(void);\nstatic int32_t test27(void);\nstatic int32_t perf_test(void);\n\nrte_lpm6_test tests6[] = {\n/* Test Cases */\n\ttest0,\n\ttest1,\n\ttest2,\n\ttest3,\n\ttest4,\n\ttest5,\n\ttest6,\n\ttest7,\n\ttest8,\n\ttest9,\n\ttest10,\n\ttest11,\n\ttest12,\n\ttest13,\n\ttest14,\n\ttest15,\n\ttest16,\n\ttest17,\n\ttest18,\n\ttest19,\n\ttest20,\n\ttest21,\n\ttest22,\n\ttest23,\n\ttest24,\n\ttest25,\n\ttest26,\n\ttest27,\n\tperf_test,\n};\n\n#define NUM_LPM6_TESTS (sizeof(tests6)/sizeof(tests6[0]))\n#define RTE_LPM6_TBL24_NUM_ENTRIES (1 << 24)\n#define RTE_LPM6_LOOKUP_SUCCESS 0x04000000\n#define MAX_DEPTH 128\n#define MAX_RULES 1000000\n#define NUMBER_TBL8S (1 << 16)\n#define MAX_NUM_TBL8S (1 << 21)\n#define PASS 0\n\nstatic void\nIPv6(uint8_t *ip, uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4, uint8_t b5,\n\t\tuint8_t b6, uint8_t b7, uint8_t b8, uint8_t b9, uint8_t b10,\n\t\tuint8_t b11, uint8_t b12, uint8_t b13, uint8_t b14, uint8_t b15,\n\t\tuint8_t b16)\n{\n\tip[0] = b1;\n\tip[1] = b2;\n\tip[2] = b3;\n\tip[3] = b4;\n\tip[4] = b5;\n\tip[5] = b6;\n\tip[6] = b7;\n\tip[7] = b8;\n\tip[8] = b9;\n\tip[9] = b10;\n\tip[10] = b11;\n\tip[11] = b12;\n\tip[12] = b13;\n\tip[13] = b14;\n\tip[14] = b15;\n\tip[15] = b16;\n}\n\n/*\n * Check that rte_lpm6_create fails gracefully for incorrect user input\n * arguments\n */\nint32_t\ntest0(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\t/* rte_lpm6_create: lpm name == NULL */\n\tlpm = rte_lpm6_create(NULL, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm == NULL);\n\n\t/* rte_lpm6_create: max_rules = 0 */\n\t/* Note: __func__ inserts the function name, in this case \"test0\". */\n\tconfig.max_rules = 0;\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm == NULL);\n\n\t/* socket_id < -1 is invalid */\n\tconfig.max_rules = MAX_RULES;\n\tlpm = rte_lpm6_create(__func__, -2, &config);\n\tTEST_LPM_ASSERT(lpm == NULL);\n\n\t/* rte_lpm6_create: number_tbl8s is bigger than the maximum */\n\tconfig.number_tbl8s = MAX_NUM_TBL8S + 1;\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm == NULL);\n\n\t/* rte_lpm6_create: config = NULL */\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, NULL);\n\tTEST_LPM_ASSERT(lpm == NULL);\n\n\treturn PASS;\n}\n\n/*\n * Creates two different LPM tables. Tries to create a third one with the same\n * name as the first one and expects the create function to return the same\n * pointer.\n */\nint32_t\ntest1(void)\n{\n\tstruct rte_lpm6 *lpm1 = NULL, *lpm2 = NULL, *lpm3 = NULL;\n\tstruct rte_lpm6_config config;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\t/* rte_lpm6_create: lpm name == LPM1 */\n\tlpm1 = rte_lpm6_create(\"LPM1\", SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm1 != NULL);\n\n\t/* rte_lpm6_create: lpm name == LPM2 */\n\tlpm2 = rte_lpm6_create(\"LPM2\", SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm2 != NULL);\n\n\t/* rte_lpm6_create: lpm name == LPM2 */\n\tlpm3 = rte_lpm6_create(\"LPM1\", SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm3 == lpm1);\n\n\trte_lpm6_free(lpm1);\n\trte_lpm6_free(lpm2);\n\n\treturn PASS;\n}\n\n/*\n * Create lpm table then delete lpm table 100 times\n * Use a slightly different rules size each time\n */\nint32_t\ntest2(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tint32_t i;\n\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\t/* rte_lpm6_free: Free NULL */\n\tfor (i = 0; i < 100; i++) {\n\t\tconfig.max_rules = MAX_RULES - i;\n\t\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\t\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t\trte_lpm6_free(lpm);\n\t}\n\n\t/* Can not test free so return success */\n\treturn PASS;\n}\n\n/*\n * Call rte_lpm6_free for NULL pointer user input. Note: free has no return and\n * therefore it is impossible to check for failure but this test is added to\n * increase function coverage metrics and to validate that freeing null does\n * not crash.\n */\nint32_t\ntest3(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\trte_lpm6_free(lpm);\n\trte_lpm6_free(NULL);\n\treturn PASS;\n}\n\n/*\n * Check that rte_lpm6_add fails gracefully for incorrect user input arguments\n */\nint32_t\ntest4(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\n\tuint8_t ip[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n\tuint8_t depth = 24, next_hop = 100;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\t/* rte_lpm6_add: lpm == NULL */\n\tstatus = rte_lpm6_add(NULL, ip, depth, next_hop);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/*Create vaild lpm to use in rest of test. */\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* rte_lpm6_add: depth < 1 */\n\tstatus = rte_lpm6_add(lpm, ip, 0, next_hop);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/* rte_lpm6_add: depth > MAX_DEPTH */\n\tstatus = rte_lpm6_add(lpm, ip, (MAX_DEPTH + 1), next_hop);\n\tTEST_LPM_ASSERT(status < 0);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Check that rte_lpm6_delete fails gracefully for incorrect user input\n * arguments\n */\nint32_t\ntest5(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n\tuint8_t depth = 24;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\t/* rte_lpm_delete: lpm == NULL */\n\tstatus = rte_lpm6_delete(NULL, ip, depth);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/*Create vaild lpm to use in rest of test. */\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* rte_lpm_delete: depth < 1 */\n\tstatus = rte_lpm6_delete(lpm, ip, 0);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/* rte_lpm_delete: depth > MAX_DEPTH */\n\tstatus = rte_lpm6_delete(lpm, ip, (MAX_DEPTH + 1));\n\tTEST_LPM_ASSERT(status < 0);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Check that rte_lpm6_lookup fails gracefully for incorrect user input\n * arguments\n */\nint32_t\ntest6(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n\tuint8_t next_hop_return = 0;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\t/* rte_lpm6_lookup: lpm == NULL */\n\tstatus = rte_lpm6_lookup(NULL, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/*Create vaild lpm to use in rest of test. */\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* rte_lpm6_lookup: ip = NULL */\n\tstatus = rte_lpm6_lookup(lpm, NULL, &next_hop_return);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/* rte_lpm6_lookup: next_hop = NULL */\n\tstatus = rte_lpm6_lookup(lpm, ip, NULL);\n\tTEST_LPM_ASSERT(status < 0);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Checks that rte_lpm6_lookup_bulk_func fails gracefully for incorrect user\n * input arguments\n */\nint32_t\ntest7(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[10][16];\n\tint16_t next_hop_return[10];\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\t/* rte_lpm6_lookup: lpm == NULL */\n\tstatus = rte_lpm6_lookup_bulk_func(NULL, ip, next_hop_return, 10);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/*Create vaild lpm to use in rest of test. */\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* rte_lpm6_lookup: ip = NULL */\n\tstatus = rte_lpm6_lookup_bulk_func(lpm, NULL, next_hop_return, 10);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/* rte_lpm6_lookup: next_hop = NULL */\n\tstatus = rte_lpm6_lookup_bulk_func(lpm, ip, NULL, 10);\n\tTEST_LPM_ASSERT(status < 0);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Checks that rte_lpm6_delete_bulk_func fails gracefully for incorrect user\n * input arguments\n */\nint32_t\ntest8(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[10][16];\n\tuint8_t depth[10];\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\t/* rte_lpm6_delete: lpm == NULL */\n\tstatus = rte_lpm6_delete_bulk_func(NULL, ip, depth, 10);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/*Create vaild lpm to use in rest of test. */\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* rte_lpm6_delete: ip = NULL */\n\tstatus = rte_lpm6_delete_bulk_func(lpm, NULL, depth, 10);\n\tTEST_LPM_ASSERT(status < 0);\n\n\t/* rte_lpm6_delete: next_hop = NULL */\n\tstatus = rte_lpm6_delete_bulk_func(lpm, ip, NULL, 10);\n\tTEST_LPM_ASSERT(status < 0);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Call add, lookup and delete for a single rule with depth < 24.\n * Check all the combinations for the first three bytes that result in a hit.\n * Delete the rule and check that the same test returs a miss.\n */\nint32_t\ntest9(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n\tuint8_t depth = 16, next_hop_add = 100, next_hop_return = 0;\n\tint32_t status = 0;\n\tuint8_t i;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tfor (i = 0; i < UINT8_MAX; i++) {\n\t\tip[2] = i;\n\t\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\t\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\t}\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tfor (i = 0; i < UINT8_MAX; i++) {\n\t\tip[2] = i;\n\t\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\t\tTEST_LPM_ASSERT(status == -ENOENT);\n\t}\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Adds max_rules + 1 and expects a failure. Deletes a rule, then adds\n * another one and expects success.\n */\nint32_t\ntest10(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n\tuint8_t depth, next_hop_add = 100;\n\tint32_t status = 0;\n\tint i;\n\n\tconfig.max_rules = 127;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tfor (i = 1; i < 128; i++) {\n\t\tdepth = (uint8_t)i;\n\t\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\t\tTEST_LPM_ASSERT(status == 0);\n\t}\n\n\tdepth = 128;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == -ENOSPC);\n\n\tdepth = 127;\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tdepth = 128;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Creates an LPM table with a small number of tbl8s and exhaust them in the\n * middle of the process of creating a rule.\n */\nint32_t\ntest11(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n\tuint8_t depth, next_hop_add = 100;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = 16;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tdepth = 128;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tip[0] = 1;\n\tdepth = 25;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tdepth = 33;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tdepth = 41;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tdepth = 49;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == -ENOSPC);\n\n\tdepth = 41;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Creates an LPM table with a small number of tbl8s and exhaust them in the\n * middle of the process of adding a rule when there is already an existing rule\n * in that position and needs to be extended.\n */\nint32_t\ntest12(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n\tuint8_t depth, next_hop_add = 100;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = 16;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tdepth = 128;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tip[0] = 1;\n\tdepth = 41;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tdepth = 49;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == -ENOSPC);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Creates an LPM table with max_rules = 2 and tries to add 3 rules.\n * Delete one of the rules and tries to add the third one again.\n */\nint32_t\ntest13(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n\tuint8_t depth, next_hop_add = 100;\n\tint32_t status = 0;\n\n\tconfig.max_rules = 2;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tdepth = 1;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tdepth = 2;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tdepth = 3;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == -ENOSPC);\n\n\tdepth = 2;\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tdepth = 3;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Add 2^16 routes with different first 16 bits and depth 25.\n * Add one more route with the same depth and check that results in a failure.\n * After that delete the last rule and create the one that was attempted to be\n * created. This checks tbl8 exhaustion.\n */\nint32_t\ntest14(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n\tuint8_t depth = 25, next_hop_add = 100;\n\tint32_t status = 0;\n\tint i, j;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tfor (i = 0; i < 256; i++) {\n\t\tip[0] = (uint8_t)i;\n\t\tfor (j = 0; j < 256; j++) {\n\t\t\tip[1] = (uint8_t)j;\n\t\t\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\t\t\tTEST_LPM_ASSERT(status == 0);\n\t\t}\n\t}\n\n\tip[0] = 255;\n\tip[1] = 255;\n\tip[2] = 1;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == -ENOSPC);\n\n\tip[0] = 255;\n\tip[1] = 255;\n\tip[2] = 0;\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tip[0] = 255;\n\tip[1] = 255;\n\tip[2] = 1;\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Call add, lookup and delete for a single rule with depth = 24\n */\nint32_t\ntest15(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n\tuint8_t depth = 24, next_hop_add = 100, next_hop_return = 0;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Call add, lookup and delete for a single rule with depth > 24\n */\nint32_t\ntest16(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[] = {12,12,1,0,0,0,0,0,0,0,0,0,0,0,0,0};\n\tuint8_t depth = 128, next_hop_add = 100, next_hop_return = 0;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Use rte_lpm6_add to add rules which effect only the second half of the lpm\n * table. Use all possible depths ranging from 1..32. Set the next hop = to the\n * depth. Check lookup hit for on every add and check for lookup miss on the\n * first half of the lpm table after each add. Finally delete all rules going\n * backwards (i.e. from depth = 32 ..1) and carry out a lookup after each\n * delete. The lookup should return the next_hop_add value related to the\n * previous depth value (i.e. depth -1).\n */\nint32_t\ntest17(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip1[] = {127,255,255,255,255,255,255,255,255,\n\t\t\t255,255,255,255,255,255,255};\n\tuint8_t ip2[] = {128,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};\n\tuint8_t depth, next_hop_add, next_hop_return;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* Loop with rte_lpm6_add. */\n\tfor (depth = 1; depth <= 128; depth++) {\n\t\t/* Let the next_hop_add value = depth. Just for change. */\n\t\tnext_hop_add = depth;\n\n\t\tstatus = rte_lpm6_add(lpm, ip2, depth, next_hop_add);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\t/* Check IP in first half of tbl24 which should be empty. */\n\t\tstatus = rte_lpm6_lookup(lpm, ip1, &next_hop_return);\n\t\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\t\tstatus = rte_lpm6_lookup(lpm, ip2, &next_hop_return);\n\t\tTEST_LPM_ASSERT((status == 0) &&\n\t\t\t(next_hop_return == next_hop_add));\n\t}\n\n\t/* Loop with rte_lpm6_delete. */\n\tfor (depth = 128; depth >= 1; depth--) {\n\t\tnext_hop_add = (uint8_t) (depth - 1);\n\n\t\tstatus = rte_lpm6_delete(lpm, ip2, depth);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\tstatus = rte_lpm6_lookup(lpm, ip2, &next_hop_return);\n\n\t\tif (depth != 1) {\n\t\t\tTEST_LPM_ASSERT((status == 0) &&\n\t\t\t\t(next_hop_return == next_hop_add));\n\t\t}\n\t\telse {\n\t\t\tTEST_LPM_ASSERT(status == -ENOENT);\n\t\t}\n\n\t\tstatus = rte_lpm6_lookup(lpm, ip1, &next_hop_return);\n\t\tTEST_LPM_ASSERT(status == -ENOENT);\n\t}\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * - Add & lookup to hit invalid TBL24 entry\n * - Add & lookup to hit valid TBL24 entry not extended\n * - Add & lookup to hit valid extended TBL24 entry with invalid TBL8 entry\n * - Add & lookup to hit valid extended TBL24 entry with valid TBL8 entry\n */\nint32_t\ntest18(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[16], ip_1[16], ip_2[16];\n\tuint8_t depth, depth_1, depth_2, next_hop_add, next_hop_add_1,\n\t\tnext_hop_add_2, next_hop_return;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\t/* Add & lookup to hit invalid TBL24 entry */\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 24;\n\tnext_hop_add = 100;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_delete_all(lpm);\n\n\t/* Add & lookup to hit valid TBL24 entry not extended */\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 23;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tdepth = 24;\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tdepth = 24;\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tdepth = 23;\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_delete_all(lpm);\n\n\t/* Add & lookup to hit valid extended TBL24 entry with invalid TBL8\n\t * entry.\n\t */\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 32;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tIPv6(ip, 128, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 32;\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 32;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_delete_all(lpm);\n\n\t/* Add & lookup to hit valid extended TBL24 entry with valid TBL8\n\t * entry\n\t */\n\tIPv6(ip_1, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth_1 = 25;\n\tnext_hop_add_1 = 101;\n\n\tIPv6(ip_2, 128, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth_2 = 32;\n\tnext_hop_add_2 = 102;\n\n\tnext_hop_return = 0;\n\n\tstatus = rte_lpm6_add(lpm, ip_1, depth_1, next_hop_add_1);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip_1, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add_1));\n\n\tstatus = rte_lpm6_add(lpm, ip_2, depth_2, next_hop_add_2);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip_2, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add_2));\n\n\tstatus = rte_lpm6_delete(lpm, ip_2, depth_2);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip_2, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add_1));\n\n\tstatus = rte_lpm6_delete(lpm, ip_1, depth_1);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip_1, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * - Add rule that covers a TBL24 range previously invalid & lookup (& delete &\n * lookup)\n * - Add rule that extends a TBL24 invalid entry & lookup (& delete & lookup)\n * - Add rule that extends a TBL24 valid entry & lookup for both rules (&\n * delete & lookup)\n * - Add rule that updates the next hop in TBL24 & lookup (& delete & lookup)\n * - Add rule that updates the next hop in TBL8 & lookup (& delete & lookup)\n * - Delete a rule that is not present in the TBL24 & lookup\n * - Delete a rule that is not present in the TBL8 & lookup\n */\nint32_t\ntest19(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[16];\n\tuint8_t depth, next_hop_add, next_hop_return;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\t/* Add rule that covers a TBL24 range previously invalid & lookup\n\t * (& delete & lookup)\n\t */\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 16;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_delete_all(lpm);\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 25;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\trte_lpm6_delete_all(lpm);\n\n\t/*\n\t * Add rule that extends a TBL24 valid entry & lookup for both rules\n\t * (& delete & lookup)\n\t */\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 24;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tIPv6(ip, 128, 0, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 32;\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 24;\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\tIPv6(ip, 128, 0, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 32;\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_delete_all(lpm);\n\n\t/*\n\t * Add rule that updates the next hop in TBL24 & lookup\n\t * (& delete & lookup)\n\t */\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 24;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_delete_all(lpm);\n\n\t/*\n\t * Add rule that updates the next hop in TBL8 & lookup\n\t * (& delete & lookup)\n\t */\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 32;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_delete_all(lpm);\n\n\t/* Delete a rule that is not present in the TBL24 & lookup */\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 24;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status < 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_delete_all(lpm);\n\n\t/* Delete a rule that is not present in the TBL8 & lookup */\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 32;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status < 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Add two rules, lookup to hit the more specific one, lookup to hit the less\n * specific one delete the less specific rule and lookup previous values again;\n * add a more specific rule than the existing rule, lookup again\n */\nint32_t\ntest20(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[16];\n\tuint8_t depth, next_hop_add, next_hop_return;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 24;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10);\n\tdepth = 128;\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT((status == 0) && (next_hop_return == next_hop_add));\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 24;\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10);\n\tdepth = 128;\n\n\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\tTEST_LPM_ASSERT(status == -ENOENT);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Adds 3 rules and look them up through the lookup_bulk function.\n * Includes in the lookup a fourth IP address that won't match\n * and checks that the result is as expected.\n */\nint32_t\ntest21(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip_batch[4][16];\n\tuint8_t depth, next_hop_add;\n\tint16_t next_hop_return[4];\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tIPv6(ip_batch[0], 128, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 48;\n\tnext_hop_add = 100;\n\n\tstatus = rte_lpm6_add(lpm, ip_batch[0], depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tIPv6(ip_batch[1], 128, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 48;\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm6_add(lpm, ip_batch[1], depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tIPv6(ip_batch[2], 128, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 48;\n\tnext_hop_add = 102;\n\n\tstatus = rte_lpm6_add(lpm, ip_batch[2], depth, next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tIPv6(ip_batch[3], 128, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\n\tstatus = rte_lpm6_lookup_bulk_func(lpm, ip_batch,\n\t\t\tnext_hop_return, 4);\n\tTEST_LPM_ASSERT(status == 0 && next_hop_return[0] == 100\n\t\t\t&& next_hop_return[1] == 101 && next_hop_return[2] == 102\n\t\t\t&& next_hop_return[3] == -1);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Adds 5 rules and look them up.\n * Use the delete_bulk function to delete two of them. Lookup again.\n * Use the delete_bulk function to delete one more. Lookup again.\n * Use the delete_bulk function to delete two more, one invalid. Lookup again.\n * Use the delete_bulk function to delete the remaining one. Lookup again.\n */\nint32_t\ntest22(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip_batch[5][16];\n\tuint8_t depth[5], next_hop_add;\n\tint16_t next_hop_return[5];\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* Adds 5 rules and look them up */\n\n\tIPv6(ip_batch[0], 128, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth[0] = 48;\n\tnext_hop_add = 101;\n\n\tstatus = rte_lpm6_add(lpm, ip_batch[0], depth[0], next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tIPv6(ip_batch[1], 128, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth[1] = 48;\n\tnext_hop_add = 102;\n\n\tstatus = rte_lpm6_add(lpm, ip_batch[1], depth[1], next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tIPv6(ip_batch[2], 128, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth[2] = 48;\n\tnext_hop_add = 103;\n\n\tstatus = rte_lpm6_add(lpm, ip_batch[2], depth[2], next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tIPv6(ip_batch[3], 128, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth[3] = 48;\n\tnext_hop_add = 104;\n\n\tstatus = rte_lpm6_add(lpm, ip_batch[3], depth[3], next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tIPv6(ip_batch[4], 128, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth[4] = 48;\n\tnext_hop_add = 105;\n\n\tstatus = rte_lpm6_add(lpm, ip_batch[4], depth[4], next_hop_add);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup_bulk_func(lpm, ip_batch,\n\t\t\tnext_hop_return, 5);\n\tTEST_LPM_ASSERT(status == 0 && next_hop_return[0] == 101\n\t\t\t&& next_hop_return[1] == 102 && next_hop_return[2] == 103\n\t\t\t&& next_hop_return[3] == 104 && next_hop_return[4] == 105);\n\n\t/* Use the delete_bulk function to delete two of them. Lookup again */\n\n\tstatus = rte_lpm6_delete_bulk_func(lpm, &ip_batch[0], depth, 2);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup_bulk_func(lpm, ip_batch,\n\t\t\tnext_hop_return, 5);\n\tTEST_LPM_ASSERT(status == 0 && next_hop_return[0] == -1\n\t\t\t&& next_hop_return[1] == -1 && next_hop_return[2] == 103\n\t\t\t&& next_hop_return[3] == 104 && next_hop_return[4] == 105);\n\n\t/* Use the delete_bulk function to delete one more. Lookup again */\n\n\tstatus = rte_lpm6_delete_bulk_func(lpm, &ip_batch[2], depth, 1);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup_bulk_func(lpm, ip_batch,\n\t\t\tnext_hop_return, 5);\n\tTEST_LPM_ASSERT(status == 0 && next_hop_return[0] == -1\n\t\t\t&& next_hop_return[1] == -1 && next_hop_return[2] == -1\n\t\t\t&& next_hop_return[3] == 104 && next_hop_return[4] == 105);\n\n\t/* Use the delete_bulk function to delete two, one invalid. Lookup again */\n\n\tIPv6(ip_batch[4], 128, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tstatus = rte_lpm6_delete_bulk_func(lpm, &ip_batch[3], depth, 2);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tIPv6(ip_batch[4], 128, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tstatus = rte_lpm6_lookup_bulk_func(lpm, ip_batch,\n\t\t\tnext_hop_return, 5);\n\tTEST_LPM_ASSERT(status == 0 && next_hop_return[0] == -1\n\t\t\t&& next_hop_return[1] == -1 && next_hop_return[2] == -1\n\t\t\t&& next_hop_return[3] == -1 && next_hop_return[4] == 105);\n\n\t/* Use the delete_bulk function to delete the remaining one. Lookup again */\n\n\tstatus = rte_lpm6_delete_bulk_func(lpm, &ip_batch[4], depth, 1);\n\tTEST_LPM_ASSERT(status == 0);\n\n\tstatus = rte_lpm6_lookup_bulk_func(lpm, ip_batch,\n\t\t\tnext_hop_return, 5);\n\tTEST_LPM_ASSERT(status == 0 && next_hop_return[0] == -1\n\t\t\t&& next_hop_return[1] == -1 && next_hop_return[2] == -1\n\t\t\t&& next_hop_return[3] == -1 && next_hop_return[4] == -1);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Add an extended rule (i.e. depth greater than 24, lookup (hit), delete,\n * lookup (miss) in a for loop of 1000 times. This will check tbl8 extension\n * and contraction.\n */\nint32_t\ntest23(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint32_t i;\n\tuint8_t ip[16];\n\tuint8_t depth, next_hop_add, next_hop_return;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tIPv6(ip, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);\n\tdepth = 128;\n\tnext_hop_add = 100;\n\n\tfor (i = 0; i < 1000; i++) {\n\t\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\t\tTEST_LPM_ASSERT((status == 0) &&\n\t\t\t\t(next_hop_return == next_hop_add));\n\n\t\tstatus = rte_lpm6_delete(lpm, ip, depth);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\t\tTEST_LPM_ASSERT(status == -ENOENT);\n\t}\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Sequence of operations for find existing lpm table\n *\n * - create table\n * - find existing table: hit\n * - find non-existing table: miss\n */\nint32_t\ntest24(void)\n{\n\tstruct rte_lpm6 *lpm = NULL, *result = NULL;\n\tstruct rte_lpm6_config config;\n\n\tconfig.max_rules = 256 * 32;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\t/* Create lpm */\n\tlpm = rte_lpm6_create(\"lpm_find_existing\", SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* Try to find existing lpm */\n\tresult = rte_lpm6_find_existing(\"lpm_find_existing\");\n\tTEST_LPM_ASSERT(result == lpm);\n\n\t/* Try to find non-existing lpm */\n\tresult = rte_lpm6_find_existing(\"lpm_find_non_existing\");\n\tTEST_LPM_ASSERT(result == NULL);\n\n\t/* Cleanup. */\n\trte_lpm6_delete_all(lpm);\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Add a set of random routes with random depths.\n * Lookup different IP addresses that match the routes previously added.\n * Checks that the next hop is the expected one.\n * The routes, IP addresses and expected result for every case have been\n * precalculated by using a python script and stored in a .h file.\n */\nint32_t\ntest25(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip[16];\n\tuint32_t i;\n\tuint8_t depth, next_hop_add, next_hop_return, next_hop_expected;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tfor (i = 0; i < 1000; i++) {\n\t\tmemcpy(ip, large_route_table[i].ip, 16);\n\t\tdepth = large_route_table[i].depth;\n\t\tnext_hop_add = large_route_table[i].next_hop;\n\t\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\t\tTEST_LPM_ASSERT(status == 0);\n\t}\n\n\tfor (i = 0; i < 100000; i++) {\n\t\tmemcpy(ip, large_ips_table[i].ip, 16);\n\t\tnext_hop_expected = large_ips_table[i].next_hop;\n\n\t\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\t\tTEST_LPM_ASSERT((status == 0) &&\n\t\t\t\t(next_hop_return == next_hop_expected));\n\t}\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Test for overwriting of tbl8:\n * - add rule /32 and lookup\n * - add new rule /24 and lookup\n *\t- add third rule /25 and lookup\n *\t- lookup /32 and /24 rule to ensure the table has not been overwritten.\n */\nint32_t\ntest26(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint8_t ip_10_32[] = {10, 10, 10, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};\n\tuint8_t ip_10_24[] = {10, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};\n\tuint8_t ip_20_25[] = {10, 10, 20, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};\n\tuint8_t d_ip_10_32 = 32;\n\tuint8_t\td_ip_10_24 = 24;\n\tuint8_t\td_ip_20_25 = 25;\n\tuint8_t next_hop_ip_10_32 = 100;\n\tuint8_t\tnext_hop_ip_10_24 = 105;\n\tuint8_t\tnext_hop_ip_20_25 = 111;\n\tuint8_t next_hop_return = 0;\n\tint32_t status = 0;\n\n\tconfig.max_rules = MAX_RULES;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\tif ((status = rte_lpm6_add(lpm, ip_10_32, d_ip_10_32,\n\t\t\tnext_hop_ip_10_32)) < 0)\n\t\treturn -1;\n\n\tstatus = rte_lpm6_lookup(lpm, ip_10_32, &next_hop_return);\n\tuint8_t test_hop_10_32 = next_hop_return;\n\tTEST_LPM_ASSERT(status == 0);\n\tTEST_LPM_ASSERT(next_hop_return == next_hop_ip_10_32);\n\n\tif ((status = rte_lpm6_add(lpm, ip_10_24, d_ip_10_24,\n\t\t\tnext_hop_ip_10_24)) < 0)\n\t\t\treturn -1;\n\n\tstatus = rte_lpm6_lookup(lpm, ip_10_24, &next_hop_return);\n\tuint8_t test_hop_10_24 = next_hop_return;\n\tTEST_LPM_ASSERT(status == 0);\n\tTEST_LPM_ASSERT(next_hop_return == next_hop_ip_10_24);\n\n\tif ((status = rte_lpm6_add(lpm, ip_20_25, d_ip_20_25,\n\t\t\tnext_hop_ip_20_25)) < 0)\n\t\treturn -1;\n\n\tstatus = rte_lpm6_lookup(lpm, ip_20_25, &next_hop_return);\n\tuint8_t test_hop_20_25 = next_hop_return;\n\tTEST_LPM_ASSERT(status == 0);\n\tTEST_LPM_ASSERT(next_hop_return == next_hop_ip_20_25);\n\n\tif (test_hop_10_32 == test_hop_10_24) {\n\t\tprintf(\"Next hop return equal\\n\");\n\t\treturn -1;\n\t}\n\n\tif (test_hop_10_24 == test_hop_20_25){\n\t\tprintf(\"Next hop return equal\\n\");\n\t\treturn -1;\n\t}\n\n\tstatus = rte_lpm6_lookup(lpm, ip_10_32, &next_hop_return);\n\tTEST_LPM_ASSERT(status == 0);\n\tTEST_LPM_ASSERT(next_hop_return == next_hop_ip_10_32);\n\n\tstatus = rte_lpm6_lookup(lpm, ip_10_24, &next_hop_return);\n\tTEST_LPM_ASSERT(status == 0);\n\tTEST_LPM_ASSERT(next_hop_return == next_hop_ip_10_24);\n\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Add a rule that reaches the end of the tree.\n * Add a rule that is more generic than the first one.\n * Check every possible combination that produces a match for the second rule.\n * This tests tbl expansion.\n */\nint32_t\ntest27(void)\n{\n\t\tstruct rte_lpm6 *lpm = NULL;\n\t\tstruct rte_lpm6_config config;\n\t\tuint8_t ip[] = {128,128,128,128,128,128,128,128,128,128,128,128,128,128,0,0};\n\t\tuint8_t depth = 128, next_hop_add = 100, next_hop_return;\n\t\tint32_t status = 0;\n\t\tint i, j;\n\n\t\tconfig.max_rules = MAX_RULES;\n\t\tconfig.number_tbl8s = NUMBER_TBL8S;\n\t\tconfig.flags = 0;\n\n\t\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\t\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t\tdepth = 128;\n\t\tnext_hop_add = 128;\n\t\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\tdepth = 112;\n\t\tnext_hop_add = 112;\n\t\tstatus = rte_lpm6_add(lpm, ip, depth, next_hop_add);\n\t\tTEST_LPM_ASSERT(status == 0);\n\n\t\tfor (i = 0; i < 256; i++) {\n\t\t\tip[14] = (uint8_t)i;\n\t\t\tfor (j = 0; j < 256; j++) {\n\t\t\t\tip[15] = (uint8_t)j;\n\t\t\t\tstatus = rte_lpm6_lookup(lpm, ip, &next_hop_return);\n\t\t\t\tif (i == 0 && j == 0)\n\t\t\t\t\tTEST_LPM_ASSERT(status == 0 && next_hop_return == 128);\n\t\t\t\telse\n\t\t\t\t\tTEST_LPM_ASSERT(status == 0 && next_hop_return == 112);\n\t\t\t\t}\n\t\t}\n\n\t\trte_lpm6_free(lpm);\n\n\t\treturn PASS;\n}\n\n/*\n * Lookup performance test\n */\n\n#define ITERATIONS (1 << 10)\n#define BATCH_SIZE 100000\n\nstatic void\nprint_route_distribution(const struct rules_tbl_entry *table, uint32_t n)\n{\n\tunsigned i, j;\n\n\tprintf(\"Route distribution per prefix width: \\n\");\n\tprintf(\"DEPTH QUANTITY (PERCENT)\\n\");\n\tprintf(\"--------------------------- \\n\");\n\n\t/* Count depths. */\n\tfor(i = 1; i <= 128; i++) {\n\t\tunsigned depth_counter = 0;\n\t\tdouble percent_hits;\n\n\t\tfor (j = 0; j < n; j++)\n\t\t\tif (table[j].depth == (uint8_t) i)\n\t\t\t\tdepth_counter++;\n\n\t\tpercent_hits = ((double)depth_counter)/((double)n) * 100;\n\t\tprintf(\"%.2u%15u (%.2f)\\n\", i, depth_counter, percent_hits);\n\t}\n\tprintf(\"\\n\");\n}\n\nint32_t\nperf_test(void)\n{\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_lpm6_config config;\n\tuint64_t begin, total_time;\n\tunsigned i, j;\n\tuint8_t next_hop_add = 0xAA, next_hop_return = 0;\n\tint status = 0;\n\tint64_t count = 0;\n\n\tconfig.max_rules = 1000000;\n\tconfig.number_tbl8s = NUMBER_TBL8S;\n\tconfig.flags = 0;\n\n\trte_srand(rte_rdtsc());\n\n\tprintf(\"No. routes = %u\\n\", (unsigned) NUM_ROUTE_ENTRIES);\n\n\tprint_route_distribution(large_route_table, (uint32_t) NUM_ROUTE_ENTRIES);\n\n\tlpm = rte_lpm6_create(__func__, SOCKET_ID_ANY, &config);\n\tTEST_LPM_ASSERT(lpm != NULL);\n\n\t/* Measure add. */\n\tbegin = rte_rdtsc();\n\n\tfor (i = 0; i < NUM_ROUTE_ENTRIES; i++) {\n\t\tif (rte_lpm6_add(lpm, large_route_table[i].ip,\n\t\t\t\tlarge_route_table[i].depth, next_hop_add) == 0)\n\t\t\tstatus++;\n\t}\n\t/* End Timer. */\n\ttotal_time = rte_rdtsc() - begin;\n\n\tprintf(\"Unique added entries = %d\\n\", status);\n\tprintf(\"Average LPM Add: %g cycles\\n\",\n\t\t\t(double)total_time / NUM_ROUTE_ENTRIES);\n\n\t/* Measure single Lookup */\n\ttotal_time = 0;\n\tcount = 0;\n\n\tfor (i = 0; i < ITERATIONS; i ++) {\n\t\tbegin = rte_rdtsc();\n\n\t\tfor (j = 0; j < NUM_IPS_ENTRIES; j ++) {\n\t\t\tif (rte_lpm6_lookup(lpm, large_ips_table[j].ip,\n\t\t\t\t\t&next_hop_return) != 0)\n\t\t\t\tcount++;\n\t\t}\n\n\t\ttotal_time += rte_rdtsc() - begin;\n\n\t}\n\tprintf(\"Average LPM Lookup: %.1f cycles (fails = %.1f%%)\\n\",\n\t\t\t(double)total_time / ((double)ITERATIONS * BATCH_SIZE),\n\t\t\t(count * 100.0) / (double)(ITERATIONS * BATCH_SIZE));\n\n\t/* Measure bulk Lookup */\n\ttotal_time = 0;\n\tcount = 0;\n\n\tuint8_t ip_batch[NUM_IPS_ENTRIES][16];\n\tint16_t next_hops[NUM_IPS_ENTRIES];\n\n\tfor (i = 0; i < NUM_IPS_ENTRIES; i++)\n\t\tmemcpy(ip_batch[i], large_ips_table[i].ip, 16);\n\n\tfor (i = 0; i < ITERATIONS; i ++) {\n\n\t\t/* Lookup per batch */\n\t\tbegin = rte_rdtsc();\n\t\trte_lpm6_lookup_bulk_func(lpm, ip_batch, next_hops, NUM_IPS_ENTRIES);\n\t\ttotal_time += rte_rdtsc() - begin;\n\n\t\tfor (j = 0; j < NUM_IPS_ENTRIES; j++)\n\t\t\tif (next_hops[j] < 0)\n\t\t\t\tcount++;\n\t}\n\tprintf(\"BULK LPM Lookup: %.1f cycles (fails = %.1f%%)\\n\",\n\t\t\t(double)total_time / ((double)ITERATIONS * BATCH_SIZE),\n\t\t\t(count * 100.0) / (double)(ITERATIONS * BATCH_SIZE));\n\n\t/* Delete */\n\tstatus = 0;\n\tbegin = rte_rdtsc();\n\n\tfor (i = 0; i < NUM_ROUTE_ENTRIES; i++) {\n\t\t/* rte_lpm_delete(lpm, ip, depth) */\n\t\tstatus += rte_lpm6_delete(lpm, large_route_table[i].ip,\n\t\t\t\tlarge_route_table[i].depth);\n\t}\n\n\ttotal_time += rte_rdtsc() - begin;\n\n\tprintf(\"Average LPM Delete: %g cycles\\n\",\n\t\t\t(double)total_time / NUM_ROUTE_ENTRIES);\n\n\trte_lpm6_delete_all(lpm);\n\trte_lpm6_free(lpm);\n\n\treturn PASS;\n}\n\n/*\n * Do all unit and performance tests.\n */\nstatic int\ntest_lpm6(void)\n{\n\tunsigned i;\n\tint status = -1, global_status = 0;\n\n\tfor (i = 0; i < NUM_LPM6_TESTS; i++) {\n\t\tstatus = tests6[i]();\n\n\t\tif (status < 0) {\n\t\t\tprintf(\"ERROR: LPM Test %s: FAIL\\n\", RTE_STR(tests6[i]));\n\t\t\tglobal_status = status;\n\t\t}\n\t}\n\n\treturn global_status;\n}\n\nstatic struct test_command lpm6_cmd = {\n\t.command = \"lpm6_autotest\",\n\t.callback = test_lpm6,\n};\nREGISTER_TEST_COMMAND(lpm6_cmd);\n" }, { "path": "app/test/test_lpm6_routes.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef _TEST_LPM_ROUTES_H_\n#define _TEST_LPM_ROUTES_H_\n\nstruct rules_tbl_entry {\n\tuint8_t ip[16];\n\tuint8_t depth;\n\tuint8_t next_hop;\n};\n\nstruct ips_tbl_entry {\n\tuint8_t ip[16];\n\tuint8_t next_hop;\n};\n\nstatic struct rules_tbl_entry large_route_table[] =\n{\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 50, 146},\n\t{{107, 79, 18, 235, 142, 84, 80, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 54, 141},\n\t{{247, 132, 113, 1, 215, 247, 183, 239, 128, 0, 0, 0, 0, 0, 0, 0}, 67, 23},\n\t{{48, 19, 41, 12, 76, 101, 114, 160, 45, 103, 134, 146, 128, 0, 0, 0}, 97, 252},\n\t{{5, 70, 208, 170, 19, 0, 116, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 54, 6},\n\t{{1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 9, 137},\n\t{{12, 188, 26, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 31, 9},\n\t{{1, 235, 101, 202, 26, 92, 23, 22, 179, 223, 128, 0, 0, 0, 0, 0}, 82, 9},\n\t{{215, 19, 224, 102, 45, 133, 102, 249, 56, 20, 214, 219, 93, 125, 52, 0}, 120, 163},\n\t{{178, 183, 109, 64, 136, 84, 11, 53, 217, 102, 0, 0, 0, 0, 0, 0}, 79, 197},\n\t{{212, 39, 158, 71, 253, 98, 248, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 54, 249},\n\t{{92, 58, 159, 130, 105, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 47, 88},\n\t{{118, 140, 65, 198, 212, 93, 144, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 52, 104},\n\t{{86, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 10, 36},\n\t{{79, 135, 242, 193, 197, 11, 200, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 54, 239},\n\t{{163, 228, 239, 80, 41, 66, 176, 176, 0, 0, 0, 0, 0, 0, 0, 0}, 67, 201},\n\t{{31, 9, 231, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 33, 94},\n\t{{108, 144, 205, 39, 215, 26, 96, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 51, 241},\n\t{{247, 217, 172, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 24, 239},\n\t{{24, 186, 73, 182, 240, 251, 125, 165, 0, 0, 0, 0, 0, 0, 0, 0}, 66, 151},\n\t{{245, 112, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 12, 137},\n\t{{44, 94, 138, 224, 168, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 41, 231},\n\t{{184, 221, 109, 135, 225, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 44, 11},\n\t{{51, 179, 136, 184, 30, 118, 24, 16, 26, 161, 206, 101, 0, 0, 0, 0}, 96, 20},\n\t{{48, 46, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 15, 68},\n\t{{143, 235, 237, 220, 89, 119, 187, 143, 209, 94, 46, 58, 120, 0, 0, 0}, 101, 64},\n\t{{121, 190, 90, 177, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 33, 152},\n\t{{128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 6, 217},\n\t{{128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 2, 101},\n\t{{111, 214, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 15, 58},\n\t{{162, 23, 52, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 27, 254},\n\t{{76, 103, 44, 79, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 32, 148},\n\t{{80, 85, 219, 214, 12, 4, 65, 129, 162, 148, 208, 78, 39, 69, 94, 184}, 126, 126},\n\t{{80, 54, 251, 28, 152, 23, 244, 192, 151, 83, 6, 144, 223, 213, 224, 128}, 123, 76},\n\t{{39, 232, 237, 103, 191, 188, 36, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 54, 240},\n\t{{20, 231, 89, 210, 167, 173, 80, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 54, 33},\n\t{{125, 67, 198, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 25, 47},\n\t{{26, 239, 153, 5, 213, 121, 31, 114, 161, 46, 84, 15, 148, 160, 0, 0}, 109, 41},\n\t{{102, 212, 159, 118, 223, 115, 134, 172, 0, 0, 0, 0, 0, 0, 0, 0}, 62, 72},\n\t{{85, 181, 241, 127, 3, 44, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 46, 43},\n\t{{61, 199, 131, 226, 3, 230, 94, 119, 240, 0, 0, 0, 0, 0, 0, 0}, 68, 26},\n\t{{0, 143, 160, 184, 162, 192, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 42, 139},\n\t{{170, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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128, 137, 54, 170, 71, 238, 0, 0, 0, 0}, 96, 2},\n\t{{189, 190, 121, 135, 160, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 36, 193},\n\t{{143, 155, 216, 193, 239, 205, 204, 153, 143, 236, 69, 23, 200, 211, 0, 0}, 118, 151},\n\t{{32, 1, 115, 244, 33, 219, 96, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 51, 182},\n\t{{220, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 10, 148},\n\t{{206, 87, 135, 235, 116, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 42, 53},\n\t{{152, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 11, 87},\n\t{{58, 146, 188, 233, 230, 236, 192, 214, 168, 128, 0, 0, 0, 0, 0, 0}, 73, 235},\n\t{{84, 220, 82, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 23, 51},\n\t{{106, 145, 142, 42, 186, 186, 58, 1, 48, 98, 165, 131, 48, 156, 192, 0}, 116, 11},\n\t{{53, 219, 120, 242, 166, 214, 81, 130, 64, 0, 0, 0, 0, 0, 0, 0}, 68, 28},\n\t{{240, 120, 76, 163, 32, 197, 181, 251, 98, 220, 29, 226, 0, 0, 0, 0}, 96, 73},\n\t{{234, 197, 12, 160, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 28, 216},\n\t{{191, 94, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 16, 99},\n\t{{200, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 18, 35},\n\t{{29, 129, 47, 83, 19, 75, 158, 1, 28, 24, 26, 147, 82, 119, 140, 100}, 127, 195},\n\t{{241, 174, 26, 53, 152, 112, 200, 134, 84, 187, 177, 176, 42, 64, 0, 0}, 108, 176},\n\t{{77, 171, 145, 48, 195, 84, 190, 36, 122, 199, 18, 0, 0, 0, 0, 0}, 87, 217},\n\t{{105, 104, 135, 53, 226, 118, 238, 169, 9, 253, 132, 162, 217, 123, 191, 96}, 126, 244},\n\t{{160, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 3, 125},\n\t{{41, 85, 143, 128, 91, 137, 192, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 50, 219},\n\t{{116, 110, 192, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 18, 165},\n\t{{75, 213, 44, 16, 43, 157, 34, 171, 98, 117, 109, 151, 5, 60, 224, 0}, 117, 6},\n\t{{229, 23, 116, 61, 80, 139, 200, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 53, 47},\n\t{{83, 123, 74, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 23, 73},\n\t{{151, 243, 45, 217, 216, 158, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 47, 98},\n\t{{171, 184, 110, 211, 237, 114, 144, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 52, 21},\n\t{{7, 246, 199, 119, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 32, 142},\n\t{{103, 47, 70, 17, 31, 232, 44, 75, 145, 155, 100, 216, 0, 0, 0, 0}, 93, 34},\n\t{{65, 170, 169, 100, 167, 147, 142, 251, 20, 64, 0, 0, 0, 0, 0, 0}, 74, 41},\n\t{{235, 6, 229, 248, 151, 137, 36, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 55, 80},\n\t{{156, 39, 96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 22, 11},\n\t{{92, 188, 82, 192, 142, 249, 190, 128, 0, 0, 0, 0, 0, 0, 0, 0}, 58, 254},\n\t{{253, 218, 181, 46, 134, 144, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 45, 95},\n\t{{189, 19, 31, 244, 80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 40, 8},\n\t{{30, 116, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 14, 212},\n\t{{81, 226, 13, 173, 79, 123, 223, 124, 108, 80, 83, 238, 0, 0, 0, 0}, 95, 217},\n\t{{126, 211, 206, 82, 147, 215, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 57, 15},\n\t{{42, 229, 135, 197, 196, 243, 94, 181, 133, 34, 16, 0, 0, 0, 0, 0}, 84, 66},\n\t{{68, 210, 158, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 28, 122},\n\t{{183, 63, 223, 94, 81, 41, 203, 20, 236, 212, 220, 199, 0, 0, 0, 0}, 97, 12},\n\t{{131, 146, 2, 125, 174, 43, 231, 20, 194, 0, 0, 0, 0, 0, 0, 0}, 71, 171},\n\t{{31, 180, 246, 158, 28, 192, 236, 39, 237, 55, 74, 195, 171, 192, 0, 0}, 106, 42},\n\t{{179, 10, 70, 80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 28, 194},\n\t{{147, 51, 85, 185, 234, 209, 236, 87, 147, 17, 7, 68, 148, 32, 0, 0}, 107, 237},\n\t{{177, 178, 6, 40, 46, 166, 87, 198, 214, 234, 23, 224, 0, 0, 0, 0}, 93, 151},\n\t{{201, 53, 40, 20, 49, 4, 38, 139, 133, 217, 214, 134, 89, 200, 0, 0}, 109, 238},\n\t{{4, 26, 181, 37, 206, 129, 233, 32, 0, 0, 0, 0, 0, 0, 0, 0}, 59, 128},\n\t{{81, 58, 248, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 26, 227},\n\t{{18, 238, 250, 161, 57, 246, 208, 118, 14, 76, 73, 25, 65, 22, 152, 120}, 127, 138},\n\t{{31, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 10, 60},\n\t{{115, 195, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 18, 148},\n\t{{116, 22, 75, 33, 16, 129, 35, 124, 10, 112, 31, 213, 181, 108, 177, 46}, 128, 129},\n\t{{117, 214, 20, 80, 83, 51, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 49, 202},\n\t{{120, 75, 124, 149, 120, 123, 242, 151, 181, 164, 128, 0, 0, 0, 0, 0}, 81, 88},\n\t{{87, 238, 168, 62, 88, 166, 52, 104, 219, 169, 93, 128, 0, 0, 0, 0}, 90, 3},\n\t{{237, 44, 224, 146, 52, 85, 245, 192, 65, 137, 37, 95, 156, 176, 0, 0}, 108, 243},\n\t{{214, 241, 51, 63, 73, 61, 193, 165, 23, 108, 0, 0, 0, 0, 0, 0}, 80, 95},\n\t{{87, 242, 21, 157, 45, 188, 36, 62, 66, 243, 64, 0, 0, 0, 0, 0}, 87, 255},\n\t{{0, 97, 220, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 26, 48},\n\t{{227, 206, 189, 31, 222, 8, 192, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 50, 38},\n\t{{174, 27, 0, 16, 13, 150, 33, 122, 154, 59, 236, 35, 248, 178, 64, 0}, 115, 20},\n\t{{39, 20, 125, 69, 252, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 43, 41},\n\t{{141, 232, 1, 12, 125, 229, 168, 14, 125, 116, 180, 0, 0, 0, 0, 0}, 92, 133},\n\t{{93, 238, 40, 228, 254, 203, 251, 6, 60, 82, 243, 242, 0, 0, 0, 0}, 95, 189},\n\t{{44, 115, 200, 17, 146, 223, 115, 253, 126, 206, 152, 90, 0, 0, 0, 0}, 95, 151},\n\t{{213, 58, 235, 255, 6, 163, 61, 10, 224, 0, 0, 0, 0, 0, 0, 0}, 68, 100},\n\t{{25, 86, 139, 116, 190, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 49, 118},\n\t{{113, 40, 65, 141, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 34, 164},\n\t{{149, 205, 200, 186, 19, 126, 215, 199, 94, 37, 100, 32, 128, 0, 0, 0}, 98, 71},\n\t{{39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 9, 251},\n\t{{81, 87, 80, 173, 163, 166, 104, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 57, 51},\n\t{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 3, 185},\n\t{{140, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 10, 144},\n\t{{6, 42, 1, 178, 250, 53, 186, 178, 114, 121, 192, 0, 0, 0, 0, 0}, 84, 51},\n\t{{2, 17, 234, 51, 169, 5, 219, 149, 245, 237, 4, 0, 0, 0, 0, 0}, 87, 32},\n\t{{112, 187, 173, 17, 229, 171, 225, 170, 8, 0, 0, 0, 0, 0, 0, 0}, 70, 137},\n\t{{203, 71, 140, 237, 113, 96, 123, 16, 0, 0, 0, 0, 0, 0, 0, 0}, 60, 2},\n\t{{99, 138, 207, 2, 244, 25, 211, 98, 0, 0, 0, 0, 0, 0, 0, 0}, 63, 163},\n\t{{114, 42, 98, 246, 252, 48, 233, 118, 63, 226, 157, 226, 192, 0, 0, 0}, 100, 162},\n\t{{161, 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 10, 192},\n\t{{233, 70, 240, 45, 240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 36, 185},\n\t{{28, 123, 31, 176, 235, 229, 169, 192, 0, 0, 0, 0, 0, 0, 0, 0}, 59, 51},\n\t{{146, 197, 243, 235, 243, 56, 140, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 54, 93},\n\t{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 2, 159},\n\t{{141, 92, 13, 27, 87, 241, 171, 143, 220, 0, 0, 0, 0, 0, 0, 0}, 72, 189},\n\t{{164, 151, 192, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 21, 248},\n\t{{35, 188, 248, 79, 39, 151, 232, 215, 248, 245, 185, 144, 78, 102, 173, 128}, 123, 38},\n\t{{193, 232, 166, 60, 62, 80, 230, 225, 165, 240, 0, 0, 0, 0, 0, 0}, 76, 167},\n\t{{109, 229, 118, 155, 43, 154, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 51, 28},\n\t{{160, 62, 63, 212, 218, 138, 154, 108, 163, 127, 197, 237, 183, 44, 140, 192}, 125, 37},\n\t{{196, 37, 51, 146, 26, 85, 53, 31, 216, 141, 52, 218, 153, 32, 0, 0}, 107, 234},\n\t{{228, 128, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 9, 70},\n\t{{154, 248, 20, 242, 154, 244, 63, 17, 121, 52, 70, 84, 118, 208, 0, 0}, 108, 50},\n\t{{41, 100, 27, 84, 106, 112, 96, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 51, 171},\n\t{{81, 99, 197, 139, 30, 150, 230, 216, 81, 190, 84, 165, 29, 64, 128, 0}, 113, 236},\n\t{{112, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 4, 3},\n\t{{164, 119, 253, 126, 160, 249, 183, 191, 119, 111, 224, 0, 0, 0, 0, 0}, 86, 64},\n\t{{138, 58, 198, 254, 0, 197, 60, 91, 132, 199, 181, 251, 78, 160, 0, 0}, 108, 213},\n\t{{209, 89, 168, 236, 146, 169, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 54, 15},\n\t{{131, 210, 208, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 20, 145},\n\t{{165, 190, 157, 7, 131, 5, 147, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 57, 27},\n\t{{179, 226, 57, 204, 187, 70, 52, 81, 119, 162, 229, 42, 47, 185, 9, 162}, 127, 75},\n\t{{98, 235, 155, 51, 107, 167, 127, 137, 254, 246, 162, 171, 180, 13, 233, 0}, 123, 76},\n\t{{107, 79, 76, 90, 94, 151, 155, 31, 33, 115, 19, 204, 98, 115, 0, 0}, 113, 247},\n\t{{143, 46, 30, 175, 224, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 43, 121},\n\t{{155, 85, 217, 180, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 30, 214},\n\t{{58, 62, 156, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 26, 221},\n\t{{92, 155, 53, 3, 39, 108, 155, 200, 0, 0, 0, 0, 0, 0, 0, 0}, 63, 102},\n\t{{64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 2, 191},\n\t{{63, 134, 251, 59, 192, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 39, 197},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 79, 106},\n};\n\nstatic struct ips_tbl_entry large_ips_table[] =\n{\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 194, 147, 115, 142, 16, 127, 8}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 229, 23, 195, 4, 249, 2}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 84, 128, 8, 36, 26}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 0, 0, 0, 47}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 0, 203, 219, 206}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 136, 152, 202, 50}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 5, 152, 190, 60, 210, 175, 81, 101}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 72, 237, 205, 48, 61}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 0, 0, 0, 59}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 141, 41, 73, 9, 48, 30, 122, 18}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 43, 198, 176, 9, 240, 180}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 219, 60, 216, 227, 85, 97, 202, 243}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 185, 206, 43, 179, 129, 115, 166, 131, 102}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 0, 88, 13, 78}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 216, 146, 183, 156, 118, 54, 250, 238, 4}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 0, 0, 2, 79}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 61, 9, 147, 80}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 217, 179, 60, 30, 230, 203}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 86, 177, 17, 57, 191, 148}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 183, 12, 211, 118, 249, 169, 219}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 119, 197, 52, 238, 81, 191, 112}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 0, 100, 145, 120}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 0, 0, 230, 252}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 0, 0, 51, 116}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 69, 132, 25, 226}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 29, 50, 25, 251, 126, 167}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 105, 206, 38, 242, 19, 169}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 0, 0, 241, 65, 232, 169}, 146},\n\t{{66, 70, 154, 143, 197, 233, 0, 0, 0, 0, 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0, 32, 99, 143, 39, 85, 93, 244, 24, 29}, 197},\n\t{{63, 134, 251, 59, 192, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 139}, 197},\n\t{{63, 134, 251, 59, 192, 0, 0, 0, 0, 0, 0, 0, 67, 187, 159, 128}, 197},\n\t{{63, 134, 251, 59, 192, 0, 0, 0, 0, 0, 0, 0, 0, 191, 77, 116}, 197},\n\t{{63, 134, 251, 59, 192, 0, 0, 0, 0, 0, 0, 0, 0, 186, 254, 247}, 197},\n\t{{63, 134, 251, 59, 192, 0, 0, 0, 148, 252, 37, 39, 121, 213, 107, 56}, 197},\n\t{{63, 134, 251, 59, 192, 0, 0, 0, 0, 0, 0, 0, 0, 0, 155, 14}, 197},\n\t{{63, 134, 251, 59, 192, 0, 0, 0, 0, 0, 36, 64, 160, 91, 25, 89}, 197},\n\t{{63, 134, 251, 59, 192, 0, 0, 0, 0, 121, 86, 42, 100, 68, 46, 105}, 197},\n\t{{63, 134, 251, 59, 192, 0, 0, 0, 0, 0, 0, 0, 0, 247, 23, 77}, 197},\n\t{{63, 134, 251, 59, 192, 0, 0, 0, 0, 0, 0, 0, 98, 38, 76, 171}, 197},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 51}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 155, 179, 111, 96, 154}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 202}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 242, 251}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 36, 187, 75, 205}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 125, 115, 194}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 115, 155}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 197, 5, 83}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 174, 54}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 204}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 249}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 37, 192, 68, 19, 123}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 87, 194, 29, 200, 80}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 40, 172, 160, 87}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 150, 142, 124, 203}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 181, 132}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 239, 173, 81}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 219, 20}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 162, 107, 141, 163}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 196, 118, 101}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 60, 95, 22, 150, 23}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 120, 138, 174, 18, 9}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 148}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 115, 134, 121}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 51, 187, 230, 172, 206, 250}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 218, 229}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 102, 212, 38, 181}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 36}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 234, 76, 154, 56}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 128, 251, 236, 164}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 7, 48, 49}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 174, 53}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 41, 24}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 235, 90}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 133}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 182, 239, 200, 64}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 94, 213, 91, 211, 29}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 29, 133, 10, 19, 23}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 74, 27}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 59}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 6, 61, 51}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 64, 196, 243}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 246}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 241, 253}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 145, 248}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 16, 242, 166, 72, 55}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 23, 178, 196}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 145, 226, 171, 219}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 45, 128, 229}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 169, 117, 60, 67, 173}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 234, 203}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 99}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 113, 85, 171}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 197, 34, 254, 77, 70}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 77}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 177, 172, 23, 205, 62}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 67, 44, 60, 81}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 150}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 44, 29, 226, 4, 201}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 213, 190}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 24}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 229, 206}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 184}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 43, 29, 11}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 9, 97, 201, 254, 254}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 74}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 104, 138}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 174, 210, 47, 153, 105}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 125, 139, 43}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 84, 70, 193, 222, 160}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 50, 166, 16, 118, 249}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 13, 245}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 91}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 169, 25, 35, 19, 91}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 36, 38, 50}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 246, 178, 214}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 99}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 243, 231}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 192, 255, 23, 61, 18}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 181}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 66, 235}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 7, 158, 192}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 0, 0}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 0, 0, 0, 218, 13}, 106},\n\t{{234, 149, 220, 106, 0, 144, 214, 128, 35, 102, 0, 61, 44, 226, 224, 132}, 106},\n};\n\n#define NUM_ROUTE_ENTRIES (sizeof(large_route_table) / sizeof(large_route_table[0]))\n#define NUM_IPS_ENTRIES (sizeof(large_ips_table) / sizeof(large_ips_table[0]))\n\n#endif /* _TEST_LPM_ROUTES_H_ */\n" }, { "path": "app/test/test_malloc.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#define N 10000\n\n/*\n * Malloc\n * ======\n *\n * Allocate some dynamic memory from heap (3 areas). Check that areas\n * don't overlap and that alignment constraints match. This test is\n * done many times on different lcores simultaneously.\n */\n\n/* Test if memory overlaps: return 1 if true, or 0 if false. */\nstatic int\nis_memory_overlap(void *p1, size_t len1, void *p2, size_t len2)\n{\n\tunsigned long ptr1 = (unsigned long)p1;\n\tunsigned long ptr2 = (unsigned long)p2;\n\n\tif (ptr2 >= ptr1 && (ptr2 - ptr1) < len1)\n\t\treturn 1;\n\telse if (ptr2 < ptr1 && (ptr1 - ptr2) < len2)\n\t\treturn 1;\n\treturn 0;\n}\n\nstatic int\nis_aligned(void *p, int align)\n{\n\tunsigned long addr = (unsigned long)p;\n\tunsigned mask = align - 1;\n\n\tif (addr & mask)\n\t\treturn 0;\n\treturn 1;\n}\n\nstatic int\ntest_align_overlap_per_lcore(__attribute__((unused)) void *arg)\n{\n\tconst unsigned align1 = 8,\n\t\t\talign2 = 64,\n\t\t\talign3 = 2048;\n\tunsigned i,j;\n\tvoid *p1 = NULL, *p2 = NULL, *p3 = NULL;\n\tint ret = 0;\n\n\tfor (i = 0; i < N; i++) {\n\t\tp1 = rte_zmalloc(\"dummy\", 1000, align1);\n\t\tif (!p1){\n\t\t\tprintf(\"rte_zmalloc returned NULL (i=%u)\\n\", i);\n\t\t\tret = -1;\n\t\t\tbreak;\n\t\t}\n\t\tfor(j = 0; j < 1000 ; j++) {\n\t\t\tif( *(char *)p1 != 0) {\n\t\t\t\tprintf(\"rte_zmalloc didn't zero\"\n\t\t\t\t \"the allocated memory\\n\");\n\t\t\t\tret = -1;\n\t\t\t}\n\t\t}\n\t\tp2 = rte_malloc(\"dummy\", 1000, align2);\n\t\tif (!p2){\n\t\t\tprintf(\"rte_malloc returned NULL (i=%u)\\n\", i);\n\t\t\tret = -1;\n\t\t\trte_free(p1);\n\t\t\tbreak;\n\t\t}\n\t\tp3 = rte_malloc(\"dummy\", 1000, align3);\n\t\tif (!p3){\n\t\t\tprintf(\"rte_malloc returned NULL (i=%u)\\n\", i);\n\t\t\tret = -1;\n\t\t\trte_free(p1);\n\t\t\trte_free(p2);\n\t\t\tbreak;\n\t\t}\n\t\tif (is_memory_overlap(p1, 1000, p2, 1000)) {\n\t\t\tprintf(\"p1 and p2 overlaps\\n\");\n\t\t\tret = -1;\n\t\t}\n\t\tif (is_memory_overlap(p2, 1000, p3, 1000)) {\n\t\t\tprintf(\"p2 and p3 overlaps\\n\");\n\t\t\tret = -1;\n\t\t}\n\t\tif (is_memory_overlap(p1, 1000, p3, 1000)) {\n\t\t\tprintf(\"p1 and p3 overlaps\\n\");\n\t\t\tret = -1;\n\t\t}\n\t\tif (!is_aligned(p1, align1)) {\n\t\t\tprintf(\"p1 is not aligned\\n\");\n\t\t\tret = -1;\n\t\t}\n\t\tif (!is_aligned(p2, align2)) {\n\t\t\tprintf(\"p2 is not aligned\\n\");\n\t\t\tret = -1;\n\t\t}\n\t\tif (!is_aligned(p3, align3)) {\n\t\t\tprintf(\"p3 is not aligned\\n\");\n\t\t\tret = -1;\n\t\t}\n\t\trte_free(p1);\n\t\trte_free(p2);\n\t\trte_free(p3);\n\t}\n\trte_malloc_dump_stats(stdout, \"dummy\");\n\n\treturn ret;\n}\n\nstatic int\ntest_reordered_free_per_lcore(__attribute__((unused)) void *arg)\n{\n\tconst unsigned align1 = 8,\n\t\t\talign2 = 64,\n\t\t\talign3 = 2048;\n\tunsigned i,j;\n\tvoid *p1, *p2, *p3;\n\tint ret = 0;\n\n\tfor (i = 0; i < 30; i++) {\n\t\tp1 = rte_zmalloc(\"dummy\", 1000, align1);\n\t\tif (!p1){\n\t\t\tprintf(\"rte_zmalloc returned NULL (i=%u)\\n\", i);\n\t\t\tret = -1;\n\t\t\tbreak;\n\t\t}\n\t\tfor(j = 0; j < 1000 ; j++) {\n\t\t\tif( *(char *)p1 != 0) {\n\t\t\t\tprintf(\"rte_zmalloc didn't zero\"\n\t\t\t\t \"the allocated memory\\n\");\n\t\t\t\tret = -1;\n\t\t\t}\n\t\t}\n\t\t/* use calloc to allocate 1000 16-byte items this time */\n\t\tp2 = rte_calloc(\"dummy\", 1000, 16, align2);\n\t\t/* for third request use regular malloc again */\n\t\tp3 = rte_malloc(\"dummy\", 1000, align3);\n\t\tif (!p2 || !p3){\n\t\t\tprintf(\"rte_malloc returned NULL (i=%u)\\n\", i);\n\t\t\tret = -1;\n\t\t\tbreak;\n\t\t}\n\t\tif (is_memory_overlap(p1, 1000, p2, 1000)) {\n\t\t\tprintf(\"p1 and p2 overlaps\\n\");\n\t\t\tret = -1;\n\t\t}\n\t\tif (is_memory_overlap(p2, 1000, p3, 1000)) {\n\t\t\tprintf(\"p2 and p3 overlaps\\n\");\n\t\t\tret = -1;\n\t\t}\n\t\tif (is_memory_overlap(p1, 1000, p3, 1000)) {\n\t\t\tprintf(\"p1 and p3 overlaps\\n\");\n\t\t\tret = -1;\n\t\t}\n\t\tif (!is_aligned(p1, align1)) {\n\t\t\tprintf(\"p1 is not aligned\\n\");\n\t\t\tret = -1;\n\t\t}\n\t\tif (!is_aligned(p2, align2)) {\n\t\t\tprintf(\"p2 is not aligned\\n\");\n\t\t\tret = -1;\n\t\t}\n\t\tif (!is_aligned(p3, align3)) {\n\t\t\tprintf(\"p3 is not aligned\\n\");\n\t\t\tret = -1;\n\t\t}\n\t\t/* try freeing in every possible order */\n\t\tswitch (i%6){\n\t\tcase 0:\n\t\t\trte_free(p1);\n\t\t\trte_free(p2);\n\t\t\trte_free(p3);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\trte_free(p1);\n\t\t\trte_free(p3);\n\t\t\trte_free(p2);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\trte_free(p2);\n\t\t\trte_free(p1);\n\t\t\trte_free(p3);\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\trte_free(p2);\n\t\t\trte_free(p3);\n\t\t\trte_free(p1);\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\trte_free(p3);\n\t\t\trte_free(p1);\n\t\t\trte_free(p2);\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\trte_free(p3);\n\t\t\trte_free(p2);\n\t\t\trte_free(p1);\n\t\t\tbreak;\n\t\t}\n\t}\n\trte_malloc_dump_stats(stdout, \"dummy\");\n\n\treturn ret;\n}\n\n/* test function inside the malloc lib*/\nstatic int\ntest_str_to_size(void)\n{\n\tstruct {\n\t\tconst char *str;\n\t\tuint64_t value;\n\t} test_values[] =\n\t{{ \"5G\", (uint64_t)5 * 1024 * 1024 *1024 },\n\t\t\t{\"0x20g\", (uint64_t)0x20 * 1024 * 1024 *1024},\n\t\t\t{\"10M\", 10 * 1024 * 1024},\n\t\t\t{\"050m\", 050 * 1024 * 1024},\n\t\t\t{\"8K\", 8 * 1024},\n\t\t\t{\"15k\", 15 * 1024},\n\t\t\t{\"0200\", 0200},\n\t\t\t{\"0x103\", 0x103},\n\t\t\t{\"432\", 432},\n\t\t\t{\"-1\", 0}, /* negative values return 0 */\n\t\t\t{\" -2\", 0},\n\t\t\t{\" -3MB\", 0},\n\t\t\t{\"18446744073709551616\", 0} /* ULLONG_MAX + 1 == out of range*/\n\t};\n\tunsigned i;\n\tfor (i = 0; i < sizeof(test_values)/sizeof(test_values[0]); i++)\n\t\tif (rte_str_to_size(test_values[i].str) != test_values[i].value)\n\t\t\treturn -1;\n\treturn 0;\n}\n\nstatic int\ntest_multi_alloc_statistics(void)\n{\n\tint socket = 0;\n\tstruct rte_malloc_socket_stats pre_stats, post_stats ,first_stats, second_stats;\n\tsize_t size = 2048;\n\tint align = 1024;\n#ifndef RTE_LIBRTE_MALLOC_DEBUG\n\tint trailer_size = 0;\n#else\n\tint trailer_size = RTE_CACHE_LINE_SIZE;\n#endif\n\tint overhead = RTE_CACHE_LINE_SIZE + trailer_size;\n\n\trte_malloc_get_socket_stats(socket, &pre_stats);\n\n\tvoid *p1 = rte_malloc_socket(\"stats\", size , align, socket);\n\tif (!p1)\n\t\treturn -1;\n\trte_free(p1);\n\trte_malloc_dump_stats(stdout, \"stats\");\n\n\trte_malloc_get_socket_stats(socket,&post_stats);\n\t/* Check statistics reported are correct */\n\t/* All post stats should be equal to pre stats after alloc freed */\n\tif ((post_stats.heap_totalsz_bytes != pre_stats.heap_totalsz_bytes) &&\n\t\t\t(post_stats.heap_freesz_bytes!=pre_stats.heap_freesz_bytes) &&\n\t\t\t(post_stats.heap_allocsz_bytes!=pre_stats.heap_allocsz_bytes)&&\n\t\t\t(post_stats.alloc_count!=pre_stats.alloc_count)&&\n\t\t\t(post_stats.free_count!=pre_stats.free_count)) {\n\t\tprintf(\"Malloc statistics are incorrect - freed alloc\\n\");\n\t\treturn -1;\n\t}\n\t/* Check two consecutive allocations */\n\tsize = 1024;\n\talign = 0;\n\trte_malloc_get_socket_stats(socket,&pre_stats);\n\tvoid *p2 = rte_malloc_socket(\"add\", size ,align, socket);\n\tif (!p2)\n\t\treturn -1;\n\trte_malloc_get_socket_stats(socket,&first_stats);\n\n\tvoid *p3 = rte_malloc_socket(\"add2\", size,align, socket);\n\tif (!p3)\n\t\treturn -1;\n\n\trte_malloc_get_socket_stats(socket,&second_stats);\n\n\trte_free(p2);\n\trte_free(p3);\n\n\t/* After freeing both allocations check stats return to original */\n\trte_malloc_get_socket_stats(socket, &post_stats);\n\n\tif(second_stats.heap_totalsz_bytes != first_stats.heap_totalsz_bytes) {\n\t\tprintf(\"Incorrect heap statistics: Total size \\n\");\n\t\treturn -1;\n\t}\n\t/* Check allocated size is equal to two additions plus overhead */\n\tif(second_stats.heap_allocsz_bytes !=\n\t\t\tsize + overhead + first_stats.heap_allocsz_bytes) {\n\t\tprintf(\"Incorrect heap statistics: Allocated size \\n\");\n\t\treturn -1;\n\t}\n\t/* Check that allocation count increments correctly i.e. +1 */\n\tif (second_stats.alloc_count != first_stats.alloc_count + 1) {\n\t\tprintf(\"Incorrect heap statistics: Allocated count \\n\");\n\t\treturn -1;\n\t}\n\n\tif (second_stats.free_count != first_stats.free_count){\n\t\tprintf(\"Incorrect heap statistics: Free count \\n\");\n\t\treturn -1;\n\t}\n\n\t/* Make sure that we didn't touch our greatest chunk: 2 * 11M) */\n\tif (post_stats.greatest_free_size != pre_stats.greatest_free_size) {\n\t\tprintf(\"Incorrect heap statistics: Greatest free size \\n\");\n\t\treturn -1;\n\t}\n\t/* Free size must equal the original free size minus the new allocation*/\n\tif (first_stats.heap_freesz_bytes <= second_stats.heap_freesz_bytes) {\n\t\tprintf(\"Incorrect heap statistics: Free size \\n\");\n\t\treturn -1;\n\t}\n\n\tif ((post_stats.heap_totalsz_bytes != pre_stats.heap_totalsz_bytes) &&\n\t\t\t(post_stats.heap_freesz_bytes!=pre_stats.heap_freesz_bytes) &&\n\t\t\t(post_stats.heap_allocsz_bytes!=pre_stats.heap_allocsz_bytes)&&\n\t\t\t(post_stats.alloc_count!=pre_stats.alloc_count)&&\n\t\t\t(post_stats.free_count!=pre_stats.free_count)) {\n\t\tprintf(\"Malloc statistics are incorrect - freed alloc\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic int\ntest_rte_malloc_type_limits(void)\n{\n\t/* The type-limits functionality is not yet implemented,\n\t * so always return 0 no matter what the retval.\n\t */\n\tconst char *typename = \"limit_test\";\n\trte_malloc_set_limit(typename, 64 * 1024);\n\trte_malloc_dump_stats(stdout, typename);\n\treturn 0;\n}\n\nstatic int\ntest_realloc(void)\n{\n\tconst char hello_str[] = \"Hello, world!\";\n\tconst unsigned size1 = 1024;\n\tconst unsigned size2 = size1 + 1024;\n\tconst unsigned size3 = size2;\n\tconst unsigned size4 = size3 + 1024;\n\n\t/* test data is the same even if element is moved*/\n\tchar *ptr1 = rte_zmalloc(NULL, size1, RTE_CACHE_LINE_SIZE);\n\tif (!ptr1){\n\t\tprintf(\"NULL pointer returned from rte_zmalloc\\n\");\n\t\treturn -1;\n\t}\n\tsnprintf(ptr1, size1, \"%s\" ,hello_str);\n\tchar *ptr2 = rte_realloc(ptr1, size2, RTE_CACHE_LINE_SIZE);\n\tif (!ptr2){\n\t\trte_free(ptr1);\n\t\tprintf(\"NULL pointer returned from rte_realloc\\n\");\n\t\treturn -1;\n\t}\n\tif (ptr1 == ptr2){\n\t\tprintf(\"unexpected - ptr1 == ptr2\\n\");\n\t}\n\tif (strcmp(ptr2, hello_str) != 0){\n\t\tprintf(\"Error - lost data from pointed area\\n\");\n\t\trte_free(ptr2);\n\t\treturn -1;\n\t}\n\tunsigned i;\n\tfor (i = strnlen(hello_str, sizeof(hello_str)); i < size1; i++)\n\t\tif (ptr2[i] != 0){\n\t\t\tprintf(\"Bad data in realloc\\n\");\n\t\t\trte_free(ptr2);\n\t\t\treturn -1;\n\t\t}\n\t/* now allocate third element, free the second\n\t * and resize third. It should not move. (ptr1 is now invalid)\n\t */\n\tchar *ptr3 = rte_zmalloc(NULL, size3, RTE_CACHE_LINE_SIZE);\n\tif (!ptr3){\n\t\tprintf(\"NULL pointer returned from rte_zmalloc\\n\");\n\t\trte_free(ptr2);\n\t\treturn -1;\n\t}\n\tfor (i = 0; i < size3; i++)\n\t\tif (ptr3[i] != 0){\n\t\t\tprintf(\"Bad data in zmalloc\\n\");\n\t\t\trte_free(ptr3);\n\t\t\trte_free(ptr2);\n\t\t\treturn -1;\n\t\t}\n\trte_free(ptr2);\n\t/* first resize to half the size of the freed block */\n\tchar *ptr4 = rte_realloc(ptr3, size4, RTE_CACHE_LINE_SIZE);\n\tif (!ptr4){\n\t\tprintf(\"NULL pointer returned from rte_realloc\\n\");\n\t\trte_free(ptr3);\n\t\treturn -1;\n\t}\n\tif (ptr3 != ptr4){\n\t\tprintf(\"Unexpected - ptr4 != ptr3\\n\");\n\t\trte_free(ptr4);\n\t\treturn -1;\n\t}\n\t/* now resize again to the full size of the freed block */\n\tptr4 = rte_realloc(ptr3, size3 + size2 + size1, RTE_CACHE_LINE_SIZE);\n\tif (ptr3 != ptr4){\n\t\tprintf(\"Unexpected - ptr4 != ptr3 on second resize\\n\");\n\t\trte_free(ptr4);\n\t\treturn -1;\n\t}\n\trte_free(ptr4);\n\n\t/* now try a resize to a smaller size, see if it works */\n\tconst unsigned size5 = 1024;\n\tconst unsigned size6 = size5 / 2;\n\tchar *ptr5 = rte_malloc(NULL, size5, RTE_CACHE_LINE_SIZE);\n\tif (!ptr5){\n\t\tprintf(\"NULL pointer returned from rte_malloc\\n\");\n\t\treturn -1;\n\t}\n\tchar *ptr6 = rte_realloc(ptr5, size6, RTE_CACHE_LINE_SIZE);\n\tif (!ptr6){\n\t\tprintf(\"NULL pointer returned from rte_realloc\\n\");\n\t\trte_free(ptr5);\n\t\treturn -1;\n\t}\n\tif (ptr5 != ptr6){\n\t\tprintf(\"Error, resizing to a smaller size moved data\\n\");\n\t\trte_free(ptr6);\n\t\treturn -1;\n\t}\n\trte_free(ptr6);\n\n\t/* check for behaviour changing alignment */\n\tconst unsigned size7 = 1024;\n\tconst unsigned orig_align = RTE_CACHE_LINE_SIZE;\n\tunsigned new_align = RTE_CACHE_LINE_SIZE * 2;\n\tchar *ptr7 = rte_malloc(NULL, size7, orig_align);\n\tif (!ptr7){\n\t\tprintf(\"NULL pointer returned from rte_malloc\\n\");\n\t\treturn -1;\n\t}\n\t/* calc an alignment we don't already have */\n\twhile(RTE_PTR_ALIGN(ptr7, new_align) == ptr7)\n\t\tnew_align *= 2;\n\tchar *ptr8 = rte_realloc(ptr7, size7, new_align);\n\tif (!ptr8){\n\t\tprintf(\"NULL pointer returned from rte_realloc\\n\");\n\t\trte_free(ptr7);\n\t\treturn -1;\n\t}\n\tif (RTE_PTR_ALIGN(ptr8, new_align) != ptr8){\n\t\tprintf(\"Failure to re-align data\\n\");\n\t\trte_free(ptr8);\n\t\treturn -1;\n\t}\n\trte_free(ptr8);\n\n\t/* test behaviour when there is a free block after current one,\n\t * but its not big enough\n\t */\n\tunsigned size9 = 1024, size10 = 1024;\n\tunsigned size11 = size9 + size10 + 256;\n\tchar *ptr9 = rte_malloc(NULL, size9, RTE_CACHE_LINE_SIZE);\n\tif (!ptr9){\n\t\tprintf(\"NULL pointer returned from rte_malloc\\n\");\n\t\treturn -1;\n\t}\n\tchar *ptr10 = rte_malloc(NULL, size10, RTE_CACHE_LINE_SIZE);\n\tif (!ptr10){\n\t\tprintf(\"NULL pointer returned from rte_malloc\\n\");\n\t\treturn -1;\n\t}\n\trte_free(ptr9);\n\tchar *ptr11 = rte_realloc(ptr10, size11, RTE_CACHE_LINE_SIZE);\n\tif (!ptr11){\n\t\tprintf(\"NULL pointer returned from rte_realloc\\n\");\n\t\trte_free(ptr10);\n\t\treturn -1;\n\t}\n\tif (ptr11 == ptr10){\n\t\tprintf(\"Error, unexpected that realloc has not created new buffer\\n\");\n\t\trte_free(ptr11);\n\t\treturn -1;\n\t}\n\trte_free(ptr11);\n\n\t/* check we don't crash if we pass null to realloc\n\t * We should get a malloc of the size requested*/\n\tconst size_t size12 = 1024;\n\tsize_t size12_check;\n\tchar *ptr12 = rte_realloc(NULL, size12, RTE_CACHE_LINE_SIZE);\n\tif (!ptr12){\n\t\tprintf(\"NULL pointer returned from rte_realloc\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_malloc_validate(ptr12, &size12_check) < 0 ||\n\t\t\tsize12_check != size12){\n\t\trte_free(ptr12);\n\t\treturn -1;\n\t}\n\trte_free(ptr12);\n\treturn 0;\n}\n\nstatic int\ntest_random_alloc_free(void *_ __attribute__((unused)))\n{\n\tstruct mem_list {\n\t\tstruct mem_list *next;\n\t\tchar data[0];\n\t} *list_head = NULL;\n\tunsigned i;\n\tunsigned count = 0;\n\n\trte_srand((unsigned)rte_rdtsc());\n\n\tfor (i = 0; i < N; i++){\n\t\tunsigned free_mem = 0;\n\t\tsize_t allocated_size;\n\t\twhile (!free_mem){\n\t\t\tconst unsigned mem_size = sizeof(struct mem_list) + \\\n\t\t\t\t\trte_rand() % (64 * 1024);\n\t\t\tconst unsigned align = 1 << (rte_rand() % 12); /* up to 4k alignment */\n\t\t\tstruct mem_list *entry = rte_malloc(NULL,\n\t\t\t\t\tmem_size, align);\n\t\t\tif (entry == NULL)\n\t\t\t\treturn -1;\n\t\t\tif (RTE_PTR_ALIGN(entry, align)!= entry)\n\t\t\t\treturn -1;\n\t\t\tif (rte_malloc_validate(entry, &allocated_size) == -1\n\t\t\t\t\t|| allocated_size < mem_size)\n\t\t\t\treturn -1;\n\t\t\tmemset(entry->data, rte_lcore_id(),\n\t\t\t\t\tmem_size - sizeof(*entry));\n\t\t\tentry->next = list_head;\n\t\t\tif (rte_malloc_validate(entry, NULL) == -1)\n\t\t\t\treturn -1;\n\t\t\tlist_head = entry;\n\n\t\t\tcount++;\n\t\t\t/* switch to freeing the memory with a 20% probability */\n\t\t\tfree_mem = ((rte_rand() % 10) >= 8);\n\t\t}\n\t\twhile (list_head){\n\t\t\tstruct mem_list *entry = list_head;\n\t\t\tlist_head = list_head->next;\n\t\t\trte_free(entry);\n\t\t}\n\t}\n\tprintf(\"Lcore %u allocated/freed %u blocks\\n\", rte_lcore_id(), count);\n\treturn 0;\n}\n\n#define err_return() do { \\\n\tprintf(\"%s: %d - Error\\n\", __func__, __LINE__); \\\n\tgoto err_return; \\\n} while (0)\n\nstatic int\ntest_rte_malloc_validate(void)\n{\n\tconst size_t request_size = 1024;\n\tsize_t allocated_size;\n\tchar *data_ptr = rte_malloc(NULL, request_size, RTE_CACHE_LINE_SIZE);\n#ifdef RTE_LIBRTE_MALLOC_DEBUG\n\tint retval;\n\tchar *over_write_vals = NULL;\n#endif\n\n\tif (data_ptr == NULL) {\n\t\tprintf(\"%s: %d - Allocation error\\n\", __func__, __LINE__);\n\t\treturn -1;\n\t}\n\n\t/* check that a null input returns -1 */\n\tif (rte_malloc_validate(NULL, NULL) != -1)\n\t\terr_return();\n\n\t/* check that we get ok on a valid pointer */\n\tif (rte_malloc_validate(data_ptr, &allocated_size) < 0)\n\t\terr_return();\n\n\t/* check that the returned size is ok */\n\tif (allocated_size < request_size)\n\t\terr_return();\n\n#ifdef RTE_LIBRTE_MALLOC_DEBUG\n\n\t/****** change the header to be bad */\n\tchar save_buf[64];\n\tover_write_vals = (char *)((uintptr_t)data_ptr - sizeof(save_buf));\n\t/* first save the data as a backup before overwriting it */\n\tmemcpy(save_buf, over_write_vals, sizeof(save_buf));\n\tmemset(over_write_vals, 1, sizeof(save_buf));\n\t/* then run validate */\n\tretval = rte_malloc_validate(data_ptr, NULL);\n\t/* finally restore the data again */\n\tmemcpy(over_write_vals, save_buf, sizeof(save_buf));\n\t/* check we previously had an error */\n\tif (retval != -1)\n\t\terr_return();\n\n\t/* check all ok again */\n\tif (rte_malloc_validate(data_ptr, &allocated_size) < 0)\n\t\terr_return();\n\n\t/**** change the trailer to be bad */\n\tover_write_vals = (char *)((uintptr_t)data_ptr + allocated_size);\n\t/* first save the data as a backup before overwriting it */\n\tmemcpy(save_buf, over_write_vals, sizeof(save_buf));\n\tmemset(over_write_vals, 1, sizeof(save_buf));\n\t/* then run validate */\n\tretval = rte_malloc_validate(data_ptr, NULL);\n\t/* finally restore the data again */\n\tmemcpy(over_write_vals, save_buf, sizeof(save_buf));\n\tif (retval != -1)\n\t\terr_return();\n\n\t/* check all ok again */\n\tif (rte_malloc_validate(data_ptr, &allocated_size) < 0)\n\t\terr_return();\n#endif\n\n\trte_free(data_ptr);\n\treturn 0;\n\nerr_return:\n\t/*clean up */\n\trte_free(data_ptr);\n\treturn -1;\n}\n\nstatic int\ntest_zero_aligned_alloc(void)\n{\n\tchar *p1 = rte_malloc(NULL,1024, 0);\n\tif (!p1)\n\t\tgoto err_return;\n\tif (!rte_is_aligned(p1, RTE_CACHE_LINE_SIZE))\n\t\tgoto err_return;\n\trte_free(p1);\n\treturn 0;\n\nerr_return:\n\t/*clean up */\n\tif (p1) rte_free(p1);\n\treturn -1;\n}\n\nstatic int\ntest_malloc_bad_params(void)\n{\n\tconst char *type = NULL;\n\tsize_t size = 0;\n\tunsigned align = RTE_CACHE_LINE_SIZE;\n\n\t/* rte_malloc expected to return null with inappropriate size */\n\tchar *bad_ptr = rte_malloc(type, size, align);\n\tif (bad_ptr != NULL)\n\t\tgoto err_return;\n\n\t/* rte_malloc expected to return null with inappropriate alignment */\n\talign = 17;\n\tsize = 1024;\n\n\tbad_ptr = rte_malloc(type, size, align);\n\tif (bad_ptr != NULL)\n\t\tgoto err_return;\n\n\treturn 0;\n\nerr_return:\n\t/* clean up pointer */\n\tif (bad_ptr)\n\t\trte_free(bad_ptr);\n\treturn -1;\n}\n\n/* Check if memory is avilable on a specific socket */\nstatic int\nis_mem_on_socket(int32_t socket)\n{\n\tconst struct rte_memseg *ms = rte_eal_get_physmem_layout();\n\tunsigned i;\n\n\tfor (i = 0; i < RTE_MAX_MEMSEG; i++) {\n\t\tif (socket == ms[i].socket_id)\n\t\t\treturn 1;\n\t}\n\treturn 0;\n}\n\n/*\n * Find what socket a memory address is on. Only works for addresses within\n * memsegs, not heap or stack...\n */\nstatic int32_t\naddr_to_socket(void * addr)\n{\n\tconst struct rte_memseg *ms = rte_eal_get_physmem_layout();\n\tunsigned i;\n\n\tfor (i = 0; i < RTE_MAX_MEMSEG; i++) {\n\t\tif ((ms[i].addr <= addr) &&\n\t\t\t\t((uintptr_t)addr <\n\t\t\t\t((uintptr_t)ms[i].addr + (uintptr_t)ms[i].len)))\n\t\t\treturn ms[i].socket_id;\n\t}\n\treturn -1;\n}\n\n/* Test using rte_[c|m|zm]alloc_socket() on a specific socket */\nstatic int\ntest_alloc_single_socket(int32_t socket)\n{\n\tconst char *type = NULL;\n\tconst size_t size = 10;\n\tconst unsigned align = 0;\n\tchar *mem = NULL;\n\tint32_t desired_socket = (socket == SOCKET_ID_ANY) ?\n\t\t\t(int32_t)rte_socket_id() : socket;\n\n\t/* Test rte_calloc_socket() */\n\tmem = rte_calloc_socket(type, size, sizeof(char), align, socket);\n\tif (mem == NULL)\n\t\treturn -1;\n\tif (addr_to_socket(mem) != desired_socket) {\n\t\trte_free(mem);\n\t\treturn -1;\n\t}\n\trte_free(mem);\n\n\t/* Test rte_malloc_socket() */\n\tmem = rte_malloc_socket(type, size, align, socket);\n\tif (mem == NULL)\n\t\treturn -1;\n\tif (addr_to_socket(mem) != desired_socket) {\n\t\treturn -1;\n\t}\n\trte_free(mem);\n\n\t/* Test rte_zmalloc_socket() */\n\tmem = rte_zmalloc_socket(type, size, align, socket);\n\tif (mem == NULL)\n\t\treturn -1;\n\tif (addr_to_socket(mem) != desired_socket) {\n\t\trte_free(mem);\n\t\treturn -1;\n\t}\n\trte_free(mem);\n\n\treturn 0;\n}\n\nstatic int\ntest_alloc_socket(void)\n{\n\tunsigned socket_count = 0;\n\tunsigned i;\n\n\tif (test_alloc_single_socket(SOCKET_ID_ANY) < 0)\n\t\treturn -1;\n\n\tfor (i = 0; i < RTE_MAX_NUMA_NODES; i++) {\n\t\tif (is_mem_on_socket(i)) {\n\t\t\tsocket_count++;\n\t\t\tif (test_alloc_single_socket(i) < 0) {\n\t\t\t\tprintf(\"Fail: rte_malloc_socket(..., %u) did not succeed\\n\",\n\t\t\t\t\t\ti);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t\telse {\n\t\t\tif (test_alloc_single_socket(i) == 0) {\n\t\t\t\tprintf(\"Fail: rte_malloc_socket(..., %u) succeeded\\n\",\n\t\t\t\t\t\ti);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Print warnign if only a single socket, but don't fail the test */\n\tif (socket_count < 2) {\n\t\tprintf(\"WARNING: alloc_socket test needs memory on multiple sockets!\\n\");\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntest_malloc(void)\n{\n\tunsigned lcore_id;\n\tint ret = 0;\n\n\tif (test_str_to_size() < 0){\n\t\tprintf(\"test_str_to_size() failed\\n\");\n\t\treturn -1;\n\t}\n\telse printf(\"test_str_to_size() passed\\n\");\n\n\tif (test_zero_aligned_alloc() < 0){\n\t\tprintf(\"test_zero_aligned_alloc() failed\\n\");\n\t\treturn -1;\n\t}\n\telse printf(\"test_zero_aligned_alloc() passed\\n\");\n\n\tif (test_malloc_bad_params() < 0){\n\t\tprintf(\"test_malloc_bad_params() failed\\n\");\n\t\treturn -1;\n\t}\n\telse printf(\"test_malloc_bad_params() passed\\n\");\n\n\tif (test_realloc() < 0){\n\t\tprintf(\"test_realloc() failed\\n\");\n\t\treturn -1;\n\t}\n\telse printf(\"test_realloc() passed\\n\");\n\n\t/*----------------------------*/\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\trte_eal_remote_launch(test_align_overlap_per_lcore, NULL, lcore_id);\n\t}\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\tret = -1;\n\t}\n\tif (ret < 0){\n\t\tprintf(\"test_align_overlap_per_lcore() failed\\n\");\n\t\treturn ret;\n\t}\n\telse printf(\"test_align_overlap_per_lcore() passed\\n\");\n\n\t/*----------------------------*/\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\trte_eal_remote_launch(test_reordered_free_per_lcore, NULL, lcore_id);\n\t}\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\tret = -1;\n\t}\n\tif (ret < 0){\n\t\tprintf(\"test_reordered_free_per_lcore() failed\\n\");\n\t\treturn ret;\n\t}\n\telse printf(\"test_reordered_free_per_lcore() passed\\n\");\n\n\t/*----------------------------*/\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\trte_eal_remote_launch(test_random_alloc_free, NULL, lcore_id);\n\t}\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\tret = -1;\n\t}\n\tif (ret < 0){\n\t\tprintf(\"test_random_alloc_free() failed\\n\");\n\t\treturn ret;\n\t}\n\telse printf(\"test_random_alloc_free() passed\\n\");\n\n\t/*----------------------------*/\n\tret = test_rte_malloc_type_limits();\n\tif (ret < 0){\n\t\tprintf(\"test_rte_malloc_type_limits() failed\\n\");\n\t\treturn ret;\n\t}\n\t/* TODO: uncomment following line once type limits are valid */\n\t/*else printf(\"test_rte_malloc_type_limits() passed\\n\");*/\n\n\t/*----------------------------*/\n\tret = test_rte_malloc_validate();\n\tif (ret < 0){\n\t\tprintf(\"test_rte_malloc_validate() failed\\n\");\n\t\treturn ret;\n\t}\n\telse printf(\"test_rte_malloc_validate() passed\\n\");\n\n\tret = test_alloc_socket();\n\tif (ret < 0){\n\t\tprintf(\"test_alloc_socket() failed\\n\");\n\t\treturn ret;\n\t}\n\telse printf(\"test_alloc_socket() passed\\n\");\n\n\tret = test_multi_alloc_statistics();\n\tif (ret < 0) {\n\t\tprintf(\"test_multi_alloc_statistics() failed\\n\");\n\t\treturn ret;\n\t}\n\telse\n\t\tprintf(\"test_multi_alloc_statistics() passed\\n\");\n\n\treturn 0;\n}\n\nstatic struct test_command malloc_cmd = {\n\t.command = \"malloc_autotest\",\n\t.callback = test_malloc,\n};\nREGISTER_TEST_COMMAND(malloc_cmd);\n" }, { "path": "app/test/test_mbuf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#define MBUF_DATA_SIZE 2048\n#define NB_MBUF 128\n#define MBUF_TEST_DATA_LEN 1464\n#define MBUF_TEST_DATA_LEN2 50\n#define MBUF_TEST_HDR1_LEN 20\n#define MBUF_TEST_HDR2_LEN 30\n#define MBUF_TEST_ALL_HDRS_LEN (MBUF_TEST_HDR1_LEN+MBUF_TEST_HDR2_LEN)\n\n/* size of private data for mbuf in pktmbuf_pool2 */\n#define MBUF2_PRIV_SIZE 128\n\n#define REFCNT_MAX_ITER 64\n#define REFCNT_MAX_TIMEOUT 10\n#define REFCNT_MAX_REF (RTE_MAX_LCORE)\n#define REFCNT_MBUF_NUM 64\n#define REFCNT_RING_SIZE (REFCNT_MBUF_NUM * REFCNT_MAX_REF)\n\n#define MAGIC_DATA 0x42424242\n\n#define MAKE_STRING(x) # x\n\nstatic struct rte_mempool *pktmbuf_pool = NULL;\nstatic struct rte_mempool *pktmbuf_pool2 = NULL;\n\n#ifdef RTE_MBUF_REFCNT_ATOMIC\n\nstatic struct rte_mempool *refcnt_pool = NULL;\nstatic struct rte_ring *refcnt_mbuf_ring = NULL;\nstatic volatile uint32_t refcnt_stop_slaves;\nstatic unsigned refcnt_lcore[RTE_MAX_LCORE];\n\n#endif\n\n/*\n * MBUF\n * ====\n *\n * #. Allocate a mbuf pool.\n *\n * - The pool contains NB_MBUF elements, where each mbuf is MBUF_SIZE\n * bytes long.\n *\n * #. Test multiple allocations of mbufs from this pool.\n *\n * - Allocate NB_MBUF and store pointers in a table.\n * - If an allocation fails, return an error.\n * - Free all these mbufs.\n * - Repeat the same test to check that mbufs were freed correctly.\n *\n * #. Test data manipulation in pktmbuf.\n *\n * - Alloc an mbuf.\n * - Append data using rte_pktmbuf_append().\n * - Test for error in rte_pktmbuf_append() when len is too large.\n * - Trim data at the end of mbuf using rte_pktmbuf_trim().\n * - Test for error in rte_pktmbuf_trim() when len is too large.\n * - Prepend a header using rte_pktmbuf_prepend().\n * - Test for error in rte_pktmbuf_prepend() when len is too large.\n * - Remove data at the beginning of mbuf using rte_pktmbuf_adj().\n * - Test for error in rte_pktmbuf_adj() when len is too large.\n * - Check that appended data is not corrupt.\n * - Free the mbuf.\n * - Between all these tests, check data_len and pkt_len, and\n * that the mbuf is contiguous.\n * - Repeat the test to check that allocation operations\n * reinitialize the mbuf correctly.\n *\n * #. Test packet cloning\n * - Clone a mbuf and verify the data\n * - Clone the cloned mbuf and verify the data\n * - Attach a mbuf to another that does not have the same priv_size.\n */\n\n#define GOTO_FAIL(str, ...) do {\t\t\t\t\t\\\n\t\tprintf(\"mbuf test FAILED (l.%d): <\" str \">\\n\",\t\t\\\n\t\t __LINE__, ##__VA_ARGS__);\t\t\t\\\n\t\tgoto fail;\t\t\t\t\t\t\\\n} while(0)\n\n/*\n * test data manipulation in mbuf with non-ascii data\n */\nstatic int\ntest_pktmbuf_with_non_ascii_data(void)\n{\n\tstruct rte_mbuf *m = NULL;\n\tchar *data;\n\n\tm = rte_pktmbuf_alloc(pktmbuf_pool);\n\tif (m == NULL)\n\t\tGOTO_FAIL(\"Cannot allocate mbuf\");\n\tif (rte_pktmbuf_pkt_len(m) != 0)\n\t\tGOTO_FAIL(\"Bad length\");\n\n\tdata = rte_pktmbuf_append(m, MBUF_TEST_DATA_LEN);\n\tif (data == NULL)\n\t\tGOTO_FAIL(\"Cannot append data\");\n\tif (rte_pktmbuf_pkt_len(m) != MBUF_TEST_DATA_LEN)\n\t\tGOTO_FAIL(\"Bad pkt length\");\n\tif (rte_pktmbuf_data_len(m) != MBUF_TEST_DATA_LEN)\n\t\tGOTO_FAIL(\"Bad data length\");\n\tmemset(data, 0xff, rte_pktmbuf_pkt_len(m));\n\tif (!rte_pktmbuf_is_contiguous(m))\n\t\tGOTO_FAIL(\"Buffer should be continuous\");\n\trte_pktmbuf_dump(stdout, m, MBUF_TEST_DATA_LEN);\n\n\trte_pktmbuf_free(m);\n\n\treturn 0;\n\nfail:\n\tif(m) {\n\t\trte_pktmbuf_free(m);\n\t}\n\treturn -1;\n}\n\n/*\n * test data manipulation in mbuf\n */\nstatic int\ntest_one_pktmbuf(void)\n{\n\tstruct rte_mbuf *m = NULL;\n\tchar *data, *data2, *hdr;\n\tunsigned i;\n\n\tprintf(\"Test pktmbuf API\\n\");\n\n\t/* alloc a mbuf */\n\n\tm = rte_pktmbuf_alloc(pktmbuf_pool);\n\tif (m == NULL)\n\t\tGOTO_FAIL(\"Cannot allocate mbuf\");\n\tif (rte_pktmbuf_pkt_len(m) != 0)\n\t\tGOTO_FAIL(\"Bad length\");\n\n\trte_pktmbuf_dump(stdout, m, 0);\n\n\t/* append data */\n\n\tdata = rte_pktmbuf_append(m, MBUF_TEST_DATA_LEN);\n\tif (data == NULL)\n\t\tGOTO_FAIL(\"Cannot append data\");\n\tif (rte_pktmbuf_pkt_len(m) != MBUF_TEST_DATA_LEN)\n\t\tGOTO_FAIL(\"Bad pkt length\");\n\tif (rte_pktmbuf_data_len(m) != MBUF_TEST_DATA_LEN)\n\t\tGOTO_FAIL(\"Bad data length\");\n\tmemset(data, 0x66, rte_pktmbuf_pkt_len(m));\n\tif (!rte_pktmbuf_is_contiguous(m))\n\t\tGOTO_FAIL(\"Buffer should be continuous\");\n\trte_pktmbuf_dump(stdout, m, MBUF_TEST_DATA_LEN);\n\trte_pktmbuf_dump(stdout, m, 2*MBUF_TEST_DATA_LEN);\n\n\t/* this append should fail */\n\n\tdata2 = rte_pktmbuf_append(m, (uint16_t)(rte_pktmbuf_tailroom(m) + 1));\n\tif (data2 != NULL)\n\t\tGOTO_FAIL(\"Append should not succeed\");\n\n\t/* append some more data */\n\n\tdata2 = rte_pktmbuf_append(m, MBUF_TEST_DATA_LEN2);\n\tif (data2 == NULL)\n\t\tGOTO_FAIL(\"Cannot append data\");\n\tif (rte_pktmbuf_pkt_len(m) != MBUF_TEST_DATA_LEN + MBUF_TEST_DATA_LEN2)\n\t\tGOTO_FAIL(\"Bad pkt length\");\n\tif (rte_pktmbuf_data_len(m) != MBUF_TEST_DATA_LEN + MBUF_TEST_DATA_LEN2)\n\t\tGOTO_FAIL(\"Bad data length\");\n\tif (!rte_pktmbuf_is_contiguous(m))\n\t\tGOTO_FAIL(\"Buffer should be continuous\");\n\n\t/* trim data at the end of mbuf */\n\n\tif (rte_pktmbuf_trim(m, MBUF_TEST_DATA_LEN2) < 0)\n\t\tGOTO_FAIL(\"Cannot trim data\");\n\tif (rte_pktmbuf_pkt_len(m) != MBUF_TEST_DATA_LEN)\n\t\tGOTO_FAIL(\"Bad pkt length\");\n\tif (rte_pktmbuf_data_len(m) != MBUF_TEST_DATA_LEN)\n\t\tGOTO_FAIL(\"Bad data length\");\n\tif (!rte_pktmbuf_is_contiguous(m))\n\t\tGOTO_FAIL(\"Buffer should be continuous\");\n\n\t/* this trim should fail */\n\n\tif (rte_pktmbuf_trim(m, (uint16_t)(rte_pktmbuf_data_len(m) + 1)) == 0)\n\t\tGOTO_FAIL(\"trim should not succeed\");\n\n\t/* prepend one header */\n\n\thdr = rte_pktmbuf_prepend(m, MBUF_TEST_HDR1_LEN);\n\tif (hdr == NULL)\n\t\tGOTO_FAIL(\"Cannot prepend\");\n\tif (data - hdr != MBUF_TEST_HDR1_LEN)\n\t\tGOTO_FAIL(\"Prepend failed\");\n\tif (rte_pktmbuf_pkt_len(m) != MBUF_TEST_DATA_LEN + MBUF_TEST_HDR1_LEN)\n\t\tGOTO_FAIL(\"Bad pkt length\");\n\tif (rte_pktmbuf_data_len(m) != MBUF_TEST_DATA_LEN + MBUF_TEST_HDR1_LEN)\n\t\tGOTO_FAIL(\"Bad data length\");\n\tif (!rte_pktmbuf_is_contiguous(m))\n\t\tGOTO_FAIL(\"Buffer should be continuous\");\n\tmemset(hdr, 0x55, MBUF_TEST_HDR1_LEN);\n\n\t/* prepend another header */\n\n\thdr = rte_pktmbuf_prepend(m, MBUF_TEST_HDR2_LEN);\n\tif (hdr == NULL)\n\t\tGOTO_FAIL(\"Cannot prepend\");\n\tif (data - hdr != MBUF_TEST_ALL_HDRS_LEN)\n\t\tGOTO_FAIL(\"Prepend failed\");\n\tif (rte_pktmbuf_pkt_len(m) != MBUF_TEST_DATA_LEN + MBUF_TEST_ALL_HDRS_LEN)\n\t\tGOTO_FAIL(\"Bad pkt length\");\n\tif (rte_pktmbuf_data_len(m) != MBUF_TEST_DATA_LEN + MBUF_TEST_ALL_HDRS_LEN)\n\t\tGOTO_FAIL(\"Bad data length\");\n\tif (!rte_pktmbuf_is_contiguous(m))\n\t\tGOTO_FAIL(\"Buffer should be continuous\");\n\tmemset(hdr, 0x55, MBUF_TEST_HDR2_LEN);\n\n\trte_mbuf_sanity_check(m, 1);\n\trte_mbuf_sanity_check(m, 0);\n\trte_pktmbuf_dump(stdout, m, 0);\n\n\t/* this prepend should fail */\n\n\thdr = rte_pktmbuf_prepend(m, (uint16_t)(rte_pktmbuf_headroom(m) + 1));\n\tif (hdr != NULL)\n\t\tGOTO_FAIL(\"prepend should not succeed\");\n\n\t/* remove data at beginning of mbuf (adj) */\n\n\tif (data != rte_pktmbuf_adj(m, MBUF_TEST_ALL_HDRS_LEN))\n\t\tGOTO_FAIL(\"rte_pktmbuf_adj failed\");\n\tif (rte_pktmbuf_pkt_len(m) != MBUF_TEST_DATA_LEN)\n\t\tGOTO_FAIL(\"Bad pkt length\");\n\tif (rte_pktmbuf_data_len(m) != MBUF_TEST_DATA_LEN)\n\t\tGOTO_FAIL(\"Bad data length\");\n\tif (!rte_pktmbuf_is_contiguous(m))\n\t\tGOTO_FAIL(\"Buffer should be continuous\");\n\n\t/* this adj should fail */\n\n\tif (rte_pktmbuf_adj(m, (uint16_t)(rte_pktmbuf_data_len(m) + 1)) != NULL)\n\t\tGOTO_FAIL(\"rte_pktmbuf_adj should not succeed\");\n\n\t/* check data */\n\n\tif (!rte_pktmbuf_is_contiguous(m))\n\t\tGOTO_FAIL(\"Buffer should be continuous\");\n\n\tfor (i=0; inext = rte_pktmbuf_alloc(pktmbuf_pool);\n\tif (m->next == NULL)\n\t\tGOTO_FAIL(\"Next Pkt Null\\n\");\n\n\trte_pktmbuf_append(m->next, sizeof(uint32_t));\n\tdata = rte_pktmbuf_mtod(m->next, unaligned_uint32_t *);\n\t*data = MAGIC_DATA;\n\n\tclone = rte_pktmbuf_clone(m, pktmbuf_pool);\n\tif (clone == NULL)\n\t\tGOTO_FAIL(\"cannot clone data\\n\");\n\n\tdata = rte_pktmbuf_mtod(clone, unaligned_uint32_t *);\n\tif (*data != MAGIC_DATA)\n\t\tGOTO_FAIL(\"invalid data in clone\\n\");\n\n\tdata = rte_pktmbuf_mtod(clone->next, unaligned_uint32_t *);\n\tif (*data != MAGIC_DATA)\n\t\tGOTO_FAIL(\"invalid data in clone->next\\n\");\n\n\tif (rte_mbuf_refcnt_read(m) != 2)\n\t\tGOTO_FAIL(\"invalid refcnt in m\\n\");\n\n\tif (rte_mbuf_refcnt_read(m->next) != 2)\n\t\tGOTO_FAIL(\"invalid refcnt in m->next\\n\");\n\n\t/* try to clone the clone */\n\n\tclone2 = rte_pktmbuf_clone(clone, pktmbuf_pool);\n\tif (clone2 == NULL)\n\t\tGOTO_FAIL(\"cannot clone the clone\\n\");\n\n\tdata = rte_pktmbuf_mtod(clone2, unaligned_uint32_t *);\n\tif (*data != MAGIC_DATA)\n\t\tGOTO_FAIL(\"invalid data in clone2\\n\");\n\n\tdata = rte_pktmbuf_mtod(clone2->next, unaligned_uint32_t *);\n\tif (*data != MAGIC_DATA)\n\t\tGOTO_FAIL(\"invalid data in clone2->next\\n\");\n\n\tif (rte_mbuf_refcnt_read(m) != 3)\n\t\tGOTO_FAIL(\"invalid refcnt in m\\n\");\n\n\tif (rte_mbuf_refcnt_read(m->next) != 3)\n\t\tGOTO_FAIL(\"invalid refcnt in m->next\\n\");\n\n\t/* free mbuf */\n\trte_pktmbuf_free(m);\n\trte_pktmbuf_free(clone);\n\trte_pktmbuf_free(clone2);\n\n\tm = NULL;\n\tclone = NULL;\n\tclone2 = NULL;\n\tprintf(\"%s ok\\n\", __func__);\n\treturn 0;\n\nfail:\n\tif (m)\n\t\trte_pktmbuf_free(m);\n\tif (clone)\n\t\trte_pktmbuf_free(clone);\n\tif (clone2)\n\t\trte_pktmbuf_free(clone2);\n\treturn -1;\n}\n\nstatic int\ntest_attach_from_different_pool(void)\n{\n\tstruct rte_mbuf *m = NULL;\n\tstruct rte_mbuf *clone = NULL;\n\tstruct rte_mbuf *clone2 = NULL;\n\tchar *data, *c_data, *c_data2;\n\n\t/* alloc a mbuf */\n\tm = rte_pktmbuf_alloc(pktmbuf_pool);\n\tif (m == NULL)\n\t\tGOTO_FAIL(\"cannot allocate mbuf\");\n\n\tif (rte_pktmbuf_pkt_len(m) != 0)\n\t\tGOTO_FAIL(\"Bad length\");\n\n\tdata = rte_pktmbuf_mtod(m, char *);\n\n\t/* allocate a new mbuf from the second pool, and attach it to the first\n\t * mbuf */\n\tclone = rte_pktmbuf_alloc(pktmbuf_pool2);\n\tif (clone == NULL)\n\t\tGOTO_FAIL(\"cannot allocate mbuf from second pool\\n\");\n\n\t/* check data room size and priv size, and erase priv */\n\tif (rte_pktmbuf_data_room_size(clone->pool) != 0)\n\t\tGOTO_FAIL(\"data room size should be 0\\n\");\n\tif (rte_pktmbuf_priv_size(clone->pool) != MBUF2_PRIV_SIZE)\n\t\tGOTO_FAIL(\"data room size should be %d\\n\", MBUF2_PRIV_SIZE);\n\tmemset(clone + 1, 0, MBUF2_PRIV_SIZE);\n\n\t/* save data pointer to compare it after detach() */\n\tc_data = rte_pktmbuf_mtod(clone, char *);\n\tif (c_data != (char *)clone + sizeof(*clone) + MBUF2_PRIV_SIZE)\n\t\tGOTO_FAIL(\"bad data pointer in clone\");\n\tif (rte_pktmbuf_headroom(clone) != 0)\n\t\tGOTO_FAIL(\"bad headroom in clone\");\n\n\trte_pktmbuf_attach(clone, m);\n\n\tif (rte_pktmbuf_mtod(clone, char *) != data)\n\t\tGOTO_FAIL(\"clone was not attached properly\\n\");\n\tif (rte_pktmbuf_headroom(clone) != RTE_PKTMBUF_HEADROOM)\n\t\tGOTO_FAIL(\"bad headroom in clone after attach\");\n\tif (rte_mbuf_refcnt_read(m) != 2)\n\t\tGOTO_FAIL(\"invalid refcnt in m\\n\");\n\n\t/* allocate a new mbuf from the second pool, and attach it to the first\n\t * cloned mbuf */\n\tclone2 = rte_pktmbuf_alloc(pktmbuf_pool2);\n\tif (clone2 == NULL)\n\t\tGOTO_FAIL(\"cannot allocate clone2 from second pool\\n\");\n\n\t/* check data room size and priv size, and erase priv */\n\tif (rte_pktmbuf_data_room_size(clone2->pool) != 0)\n\t\tGOTO_FAIL(\"data room size should be 0\\n\");\n\tif (rte_pktmbuf_priv_size(clone2->pool) != MBUF2_PRIV_SIZE)\n\t\tGOTO_FAIL(\"data room size should be %d\\n\", MBUF2_PRIV_SIZE);\n\tmemset(clone2 + 1, 0, MBUF2_PRIV_SIZE);\n\n\t/* save data pointer to compare it after detach() */\n\tc_data2 = rte_pktmbuf_mtod(clone2, char *);\n\tif (c_data2 != (char *)clone2 + sizeof(*clone2) + MBUF2_PRIV_SIZE)\n\t\tGOTO_FAIL(\"bad data pointer in clone2\");\n\tif (rte_pktmbuf_headroom(clone2) != 0)\n\t\tGOTO_FAIL(\"bad headroom in clone2\");\n\n\trte_pktmbuf_attach(clone2, clone);\n\n\tif (rte_pktmbuf_mtod(clone2, char *) != data)\n\t\tGOTO_FAIL(\"clone2 was not attached properly\\n\");\n\tif (rte_pktmbuf_headroom(clone2) != RTE_PKTMBUF_HEADROOM)\n\t\tGOTO_FAIL(\"bad headroom in clone2 after attach\");\n\tif (rte_mbuf_refcnt_read(m) != 3)\n\t\tGOTO_FAIL(\"invalid refcnt in m\\n\");\n\n\t/* detach the clones */\n\trte_pktmbuf_detach(clone);\n\tif (c_data != rte_pktmbuf_mtod(clone, char *))\n\t\tGOTO_FAIL(\"clone was not detached properly\\n\");\n\n\trte_pktmbuf_detach(clone2);\n\tif (c_data2 != rte_pktmbuf_mtod(clone2, char *))\n\t\tGOTO_FAIL(\"clone2 was not detached properly\\n\");\n\n\t/* free the clones and the initial mbuf */\n\trte_pktmbuf_free(clone2);\n\trte_pktmbuf_free(clone);\n\trte_pktmbuf_free(m);\n\tprintf(\"%s ok\\n\", __func__);\n\treturn 0;\n\nfail:\n\tif (m)\n\t\trte_pktmbuf_free(m);\n\tif (clone)\n\t\trte_pktmbuf_free(clone);\n\tif (clone2)\n\t\trte_pktmbuf_free(clone2);\n\treturn -1;\n}\n#undef GOTO_FAIL\n\n/*\n * test allocation and free of mbufs\n */\nstatic int\ntest_pktmbuf_pool(void)\n{\n\tunsigned i;\n\tstruct rte_mbuf *m[NB_MBUF];\n\tint ret = 0;\n\n\tfor (i=0; idata_off += 64;\n\t}\n\n\t/* free them */\n\tfor (i=0; idata_off != RTE_PKTMBUF_HEADROOM) {\n\t\t\tprintf(\"invalid data_off\\n\");\n\t\t\tret = -1;\n\t\t}\n\t}\n\n\t/* free them */\n\tfor (i=0; inext;\n\t\t\t\trte_pktmbuf_free_seg(mt);\n\t\t\t}\n\t\t}\n\t}\n\n\treturn ret;\n}\n\n/*\n * Stress test for rte_mbuf atomic refcnt.\n * Implies that RTE_MBUF_REFCNT_ATOMIC is defined.\n * For more efficency, recomended to run with RTE_LIBRTE_MBUF_DEBUG defined.\n */\n\n#ifdef RTE_MBUF_REFCNT_ATOMIC\n\nstatic int\ntest_refcnt_slave(__attribute__((unused)) void *arg)\n{\n\tunsigned lcore, free;\n\tvoid *mp = 0;\n\n\tlcore = rte_lcore_id();\n\tprintf(\"%s started at lcore %u\\n\", __func__, lcore);\n\n\tfree = 0;\n\twhile (refcnt_stop_slaves == 0) {\n\t\tif (rte_ring_dequeue(refcnt_mbuf_ring, &mp) == 0) {\n\t\t\tfree++;\n\t\t\trte_pktmbuf_free((struct rte_mbuf *)mp);\n\t\t}\n\t}\n\n\trefcnt_lcore[lcore] += free;\n\tprintf(\"%s finished at lcore %u, \"\n\t \"number of freed mbufs: %u\\n\",\n\t __func__, lcore, free);\n\treturn (0);\n}\n\nstatic void\ntest_refcnt_iter(unsigned lcore, unsigned iter)\n{\n\tuint16_t ref;\n\tunsigned i, n, tref, wn;\n\tstruct rte_mbuf *m;\n\n\ttref = 0;\n\n\t/* For each mbuf in the pool:\n\t * - allocate mbuf,\n\t * - increment it's reference up to N+1,\n\t * - enqueue it N times into the ring for slave cores to free.\n\t */\n\tfor (i = 0, n = rte_mempool_count(refcnt_pool);\n\t i != n && (m = rte_pktmbuf_alloc(refcnt_pool)) != NULL;\n\t i++) {\n\t\tref = RTE_MAX(rte_rand() % REFCNT_MAX_REF, 1UL);\n\t\ttref += ref;\n\t\tif ((ref & 1) != 0) {\n\t\t\trte_pktmbuf_refcnt_update(m, ref);\n\t\t\twhile (ref-- != 0)\n\t\t\t\trte_ring_enqueue(refcnt_mbuf_ring, m);\n\t\t} else {\n\t\t\twhile (ref-- != 0) {\n\t\t\t\trte_pktmbuf_refcnt_update(m, 1);\n\t\t\t\trte_ring_enqueue(refcnt_mbuf_ring, m);\n\t\t\t}\n\t\t}\n\t\trte_pktmbuf_free(m);\n\t}\n\n\tif (i != n)\n\t\trte_panic(\"(lcore=%u, iter=%u): was able to allocate only \"\n\t\t \"%u from %u mbufs\\n\", lcore, iter, i, n);\n\n\t/* wait till slave lcores will consume all mbufs */\n\twhile (!rte_ring_empty(refcnt_mbuf_ring))\n\t\t;\n\n\t/* check that all mbufs are back into mempool by now */\n\tfor (wn = 0; wn != REFCNT_MAX_TIMEOUT; wn++) {\n\t\tif ((i = rte_mempool_count(refcnt_pool)) == n) {\n\t\t\trefcnt_lcore[lcore] += tref;\n\t\t\tprintf(\"%s(lcore=%u, iter=%u) completed, \"\n\t\t\t \"%u references processed\\n\",\n\t\t\t __func__, lcore, iter, tref);\n\t\t\treturn;\n\t\t}\n\t\trte_delay_ms(1000);\n\t}\n\n\trte_panic(\"(lcore=%u, iter=%u): after %us only \"\n\t \"%u of %u mbufs left free\\n\", lcore, iter, wn, i, n);\n}\n\nstatic int\ntest_refcnt_master(void)\n{\n\tunsigned i, lcore;\n\n\tlcore = rte_lcore_id();\n\tprintf(\"%s started at lcore %u\\n\", __func__, lcore);\n\n\tfor (i = 0; i != REFCNT_MAX_ITER; i++)\n\t\ttest_refcnt_iter(lcore, i);\n\n\trefcnt_stop_slaves = 1;\n\trte_wmb();\n\n\tprintf(\"%s finished at lcore %u\\n\", __func__, lcore);\n\treturn (0);\n}\n\n#endif\n\nstatic int\ntest_refcnt_mbuf(void)\n{\n#ifdef RTE_MBUF_REFCNT_ATOMIC\n\n\tunsigned lnum, master, slave, tref;\n\n\n\tif ((lnum = rte_lcore_count()) == 1) {\n\t\tprintf(\"skipping %s, number of lcores: %u is not enough\\n\",\n\t\t __func__, lnum);\n\t\treturn (0);\n\t}\n\n\tprintf(\"starting %s, at %u lcores\\n\", __func__, lnum);\n\n\t/* create refcnt pool & ring if they don't exist */\n\n\tif (refcnt_pool == NULL &&\n\t\t\t(refcnt_pool = rte_pktmbuf_pool_create(\n\t\t\t\tMAKE_STRING(refcnt_pool),\n\t\t\t\tREFCNT_MBUF_NUM, 0, 0, 0,\n\t\t\t\tSOCKET_ID_ANY)) == NULL) {\n\t\tprintf(\"%s: cannot allocate \" MAKE_STRING(refcnt_pool) \"\\n\",\n\t\t __func__);\n\t\treturn (-1);\n\t}\n\n\tif (refcnt_mbuf_ring == NULL &&\n\t\t\t(refcnt_mbuf_ring = rte_ring_create(\"refcnt_mbuf_ring\",\n\t\t\tREFCNT_RING_SIZE, SOCKET_ID_ANY,\n\t\t\tRING_F_SP_ENQ)) == NULL) {\n\t\tprintf(\"%s: cannot allocate \" MAKE_STRING(refcnt_mbuf_ring)\n\t\t \"\\n\", __func__);\n\t\treturn (-1);\n\t}\n\n\trefcnt_stop_slaves = 0;\n\tmemset(refcnt_lcore, 0, sizeof (refcnt_lcore));\n\n\trte_eal_mp_remote_launch(test_refcnt_slave, NULL, SKIP_MASTER);\n\n\ttest_refcnt_master();\n\n\trte_eal_mp_wait_lcore();\n\n\t/* check that we porcessed all references */\n\ttref = 0;\n\tmaster = rte_get_master_lcore();\n\n\tRTE_LCORE_FOREACH_SLAVE(slave)\n\t\ttref += refcnt_lcore[slave];\n\n\tif (tref != refcnt_lcore[master])\n\t\trte_panic(\"refernced mbufs: %u, freed mbufs: %u\\n\",\n\t\t tref, refcnt_lcore[master]);\n\n\trte_mempool_dump(stdout, refcnt_pool);\n\trte_ring_dump(stdout, refcnt_mbuf_ring);\n\n#endif\n\treturn (0);\n}\n\n#include \n#include \n\n/* use fork() to test mbuf errors panic */\nstatic int\nverify_mbuf_check_panics(struct rte_mbuf *buf)\n{\n\tint pid;\n\tint status;\n\n\tpid = fork();\n\n\tif (pid == 0) {\n\t\trte_mbuf_sanity_check(buf, 1); /* should panic */\n\t\texit(0); /* return normally if it doesn't panic */\n\t} else if (pid < 0){\n\t\tprintf(\"Fork Failed\\n\");\n\t\treturn -1;\n\t}\n\twait(&status);\n\tif(status == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic int\ntest_failing_mbuf_sanity_check(void)\n{\n\tstruct rte_mbuf *buf;\n\tstruct rte_mbuf badbuf;\n\n\tprintf(\"Checking rte_mbuf_sanity_check for failure conditions\\n\");\n\n\t/* get a good mbuf to use to make copies */\n\tbuf = rte_pktmbuf_alloc(pktmbuf_pool);\n\tif (buf == NULL)\n\t\treturn -1;\n\tprintf(\"Checking good mbuf initially\\n\");\n\tif (verify_mbuf_check_panics(buf) != -1)\n\t\treturn -1;\n\n\tprintf(\"Now checking for error conditions\\n\");\n\n\tif (verify_mbuf_check_panics(NULL)) {\n\t\tprintf(\"Error with NULL mbuf test\\n\");\n\t\treturn -1;\n\t}\n\n\tbadbuf = *buf;\n\tbadbuf.pool = NULL;\n\tif (verify_mbuf_check_panics(&badbuf)) {\n\t\tprintf(\"Error with bad-pool mbuf test\\n\");\n\t\treturn -1;\n\t}\n\n\tbadbuf = *buf;\n\tbadbuf.buf_physaddr = 0;\n\tif (verify_mbuf_check_panics(&badbuf)) {\n\t\tprintf(\"Error with bad-physaddr mbuf test\\n\");\n\t\treturn -1;\n\t}\n\n\tbadbuf = *buf;\n\tbadbuf.buf_addr = NULL;\n\tif (verify_mbuf_check_panics(&badbuf)) {\n\t\tprintf(\"Error with bad-addr mbuf test\\n\");\n\t\treturn -1;\n\t}\n\n\tbadbuf = *buf;\n\tbadbuf.refcnt = 0;\n\tif (verify_mbuf_check_panics(&badbuf)) {\n\t\tprintf(\"Error with bad-refcnt(0) mbuf test\\n\");\n\t\treturn -1;\n\t}\n\n\tbadbuf = *buf;\n\tbadbuf.refcnt = UINT16_MAX;\n\tif (verify_mbuf_check_panics(&badbuf)) {\n\t\tprintf(\"Error with bad-refcnt(MAX) mbuf test\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n\nstatic int\ntest_mbuf(void)\n{\n\tRTE_BUILD_BUG_ON(sizeof(struct rte_mbuf) != RTE_CACHE_LINE_SIZE * 2);\n\n\t/* create pktmbuf pool if it does not exist */\n\tif (pktmbuf_pool == NULL) {\n\t\tpktmbuf_pool = rte_pktmbuf_pool_create(\"test_pktmbuf_pool\",\n\t\t\tNB_MBUF, 32, 0, MBUF_DATA_SIZE, SOCKET_ID_ANY);\n\t}\n\n\tif (pktmbuf_pool == NULL) {\n\t\tprintf(\"cannot allocate mbuf pool\\n\");\n\t\treturn -1;\n\t}\n\n\t/* create a specific pktmbuf pool with a priv_size != 0 and no data\n\t * room size */\n\tif (pktmbuf_pool2 == NULL) {\n\t\tpktmbuf_pool2 = rte_pktmbuf_pool_create(\"test_pktmbuf_pool2\",\n\t\t\tNB_MBUF, 32, MBUF2_PRIV_SIZE, 0, SOCKET_ID_ANY);\n\t}\n\n\tif (pktmbuf_pool2 == NULL) {\n\t\tprintf(\"cannot allocate mbuf pool\\n\");\n\t\treturn -1;\n\t}\n\n\t/* test multiple mbuf alloc */\n\tif (test_pktmbuf_pool() < 0) {\n\t\tprintf(\"test_mbuf_pool() failed\\n\");\n\t\treturn -1;\n\t}\n\n\t/* do it another time to check that all mbufs were freed */\n\tif (test_pktmbuf_pool() < 0) {\n\t\tprintf(\"test_mbuf_pool() failed (2)\\n\");\n\t\treturn -1;\n\t}\n\n\t/* test that the pointer to the data on a packet mbuf is set properly */\n\tif (test_pktmbuf_pool_ptr() < 0) {\n\t\tprintf(\"test_pktmbuf_pool_ptr() failed\\n\");\n\t\treturn -1;\n\t}\n\n\t/* test data manipulation in mbuf */\n\tif (test_one_pktmbuf() < 0) {\n\t\tprintf(\"test_one_mbuf() failed\\n\");\n\t\treturn -1;\n\t}\n\n\n\t/*\n\t * do it another time, to check that allocation reinitialize\n\t * the mbuf correctly\n\t */\n\tif (test_one_pktmbuf() < 0) {\n\t\tprintf(\"test_one_mbuf() failed (2)\\n\");\n\t\treturn -1;\n\t}\n\n\tif (test_pktmbuf_with_non_ascii_data() < 0) {\n\t\tprintf(\"test_pktmbuf_with_non_ascii_data() failed\\n\");\n\t\treturn -1;\n\t}\n\n\t/* test free pktmbuf segment one by one */\n\tif (test_pktmbuf_free_segment() < 0) {\n\t\tprintf(\"test_pktmbuf_free_segment() failed.\\n\");\n\t\treturn -1;\n\t}\n\n\tif (testclone_testupdate_testdetach()<0){\n\t\tprintf(\"testclone_and_testupdate() failed \\n\");\n\t\treturn -1;\n\t}\n\n\tif (test_attach_from_different_pool() < 0) {\n\t\tprintf(\"test_attach_from_different_pool() failed\\n\");\n\t\treturn -1;\n\t}\n\n\tif (test_refcnt_mbuf()<0){\n\t\tprintf(\"test_refcnt_mbuf() failed \\n\");\n\t\treturn -1;\n\t}\n\n\tif (test_failing_mbuf_sanity_check() < 0) {\n\t\tprintf(\"test_failing_mbuf_sanity_check() failed\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic struct test_command mbuf_cmd = {\n\t.command = \"mbuf_autotest\",\n\t.callback = test_mbuf,\n};\nREGISTER_TEST_COMMAND(mbuf_cmd);\n" }, { "path": "app/test/test_memcpy.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \n\n#include \"test.h\"\n\n/*\n * Set this to the maximum buffer size you want to test. If it is 0, then the\n * values in the buf_sizes[] array below will be used.\n */\n#define TEST_VALUE_RANGE 0\n\n/* List of buffer sizes to test */\n#if TEST_VALUE_RANGE == 0\nstatic size_t buf_sizes[] = {\n\t0, 1, 7, 8, 9, 15, 16, 17, 31, 32, 33, 63, 64, 65, 127, 128, 129, 255,\n\t256, 257, 320, 384, 511, 512, 513, 1023, 1024, 1025, 1518, 1522, 1600,\n\t2048, 3072, 4096, 5120, 6144, 7168, 8192\n};\n/* MUST be as large as largest packet size above */\n#define SMALL_BUFFER_SIZE 8192\n#else /* TEST_VALUE_RANGE != 0 */\nstatic size_t buf_sizes[TEST_VALUE_RANGE];\n#define SMALL_BUFFER_SIZE TEST_VALUE_RANGE\n#endif /* TEST_VALUE_RANGE == 0 */\n\n\n/*\n * Arrays of this size are used for measuring uncached memory accesses by\n * picking a random location within the buffer. Make this smaller if there are\n * memory allocation errors.\n */\n#define LARGE_BUFFER_SIZE (100 * 1024 * 1024)\n\n/* How many times to run timing loop for performance tests */\n#define TEST_ITERATIONS 1000000\n#define TEST_BATCH_SIZE 100\n\n/* Data is aligned on this many bytes (power of 2) */\n#define ALIGNMENT_UNIT 32\n\n\n/*\n * Create two buffers, and initialise one with random values. These are copied\n * to the second buffer and then compared to see if the copy was successful.\n * The bytes outside the copied area are also checked to make sure they were not\n * changed.\n */\nstatic int\ntest_single_memcpy(unsigned int off_src, unsigned int off_dst, size_t size)\n{\n\tunsigned int i;\n\tuint8_t dest[SMALL_BUFFER_SIZE + ALIGNMENT_UNIT];\n\tuint8_t src[SMALL_BUFFER_SIZE + ALIGNMENT_UNIT];\n\tvoid * ret;\n\n\t/* Setup buffers */\n\tfor (i = 0; i < SMALL_BUFFER_SIZE + ALIGNMENT_UNIT; i++) {\n\t\tdest[i] = 0;\n\t\tsrc[i] = (uint8_t) rte_rand();\n\t}\n\n\t/* Do the copy */\n\tret = rte_memcpy(dest + off_dst, src + off_src, size);\n\tif (ret != (dest + off_dst)) {\n\t\tprintf(\"rte_memcpy() returned %p, not %p\\n\",\n\t\t ret, dest + off_dst);\n\t}\n\n\t/* Check nothing before offset is affected */\n\tfor (i = 0; i < off_dst; i++) {\n\t\tif (dest[i] != 0) {\n\t\t\tprintf(\"rte_memcpy() failed for %u bytes (offsets=%u,%u): \"\n\t\t\t \"[modified before start of dst].\\n\",\n\t\t\t (unsigned)size, off_src, off_dst);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* Check everything was copied */\n\tfor (i = 0; i < size; i++) {\n\t\tif (dest[i + off_dst] != src[i + off_src]) {\n\t\t\tprintf(\"rte_memcpy() failed for %u bytes (offsets=%u,%u): \"\n\t\t\t \"[didn't copy byte %u].\\n\",\n\t\t\t (unsigned)size, off_src, off_dst, i);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* Check nothing after copy was affected */\n\tfor (i = size; i < SMALL_BUFFER_SIZE; i++) {\n\t\tif (dest[i + off_dst] != 0) {\n\t\t\tprintf(\"rte_memcpy() failed for %u bytes (offsets=%u,%u): \"\n\t\t\t \"[copied too many].\\n\",\n\t\t\t (unsigned)size, off_src, off_dst);\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\n/*\n * Check functionality for various buffer sizes and data offsets/alignments.\n */\nstatic int\nfunc_test(void)\n{\n\tunsigned int off_src, off_dst, i;\n\tunsigned int num_buf_sizes = sizeof(buf_sizes) / sizeof(buf_sizes[0]);\n\tint ret;\n\n\tfor (off_src = 0; off_src < ALIGNMENT_UNIT; off_src++) {\n\t\tfor (off_dst = 0; off_dst < ALIGNMENT_UNIT; off_dst++) {\n\t\t\tfor (i = 0; i < num_buf_sizes; i++) {\n\t\t\t\tret = test_single_memcpy(off_src, off_dst,\n\t\t\t\t buf_sizes[i]);\n\t\t\t\tif (ret != 0)\n\t\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\ntest_memcpy(void)\n{\n\tint ret;\n\n\tret = func_test();\n\tif (ret != 0)\n\t\treturn -1;\n\treturn 0;\n}\n\nstatic struct test_command memcpy_cmd = {\n\t.command = \"memcpy_autotest\",\n\t.callback = test_memcpy,\n};\nREGISTER_TEST_COMMAND(memcpy_cmd);\n" }, { "path": "app/test/test_memcpy_perf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \n\n#include \"test.h\"\n\n/*\n * Set this to the maximum buffer size you want to test. If it is 0, then the\n * values in the buf_sizes[] array below will be used.\n */\n#define TEST_VALUE_RANGE 0\n\n/* List of buffer sizes to test */\n#if TEST_VALUE_RANGE == 0\nstatic size_t buf_sizes[] = {\n\t1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 16, 17, 31, 32, 33, 63, 64, 65, 127, 128,\n\t129, 191, 192, 193, 255, 256, 257, 319, 320, 321, 383, 384, 385, 447, 448,\n\t449, 511, 512, 513, 767, 768, 769, 1023, 1024, 1025, 1518, 1522, 1536, 1600,\n\t2048, 2560, 3072, 3584, 4096, 4608, 5120, 5632, 6144, 6656, 7168, 7680, 8192\n};\n/* MUST be as large as largest packet size above */\n#define SMALL_BUFFER_SIZE 8192\n#else /* TEST_VALUE_RANGE != 0 */\nstatic size_t buf_sizes[TEST_VALUE_RANGE];\n#define SMALL_BUFFER_SIZE TEST_VALUE_RANGE\n#endif /* TEST_VALUE_RANGE == 0 */\n\n\n/*\n * Arrays of this size are used for measuring uncached memory accesses by\n * picking a random location within the buffer. Make this smaller if there are\n * memory allocation errors.\n */\n#define LARGE_BUFFER_SIZE (100 * 1024 * 1024)\n\n/* How many times to run timing loop for performance tests */\n#define TEST_ITERATIONS 1000000\n#define TEST_BATCH_SIZE 100\n\n/* Data is aligned on this many bytes (power of 2) */\n#define ALIGNMENT_UNIT 32\n\n/*\n * Pointers used in performance tests. The two large buffers are for uncached\n * access where random addresses within the buffer are used for each\n * memcpy. The two small buffers are for cached access.\n */\nstatic uint8_t *large_buf_read, *large_buf_write;\nstatic uint8_t *small_buf_read, *small_buf_write;\n\n/* Initialise data buffers. */\nstatic int\ninit_buffers(void)\n{\n\tunsigned i;\n\n\tlarge_buf_read = rte_malloc(\"memcpy\", LARGE_BUFFER_SIZE + ALIGNMENT_UNIT, ALIGNMENT_UNIT);\n\tif (large_buf_read == NULL)\n\t\tgoto error_large_buf_read;\n\n\tlarge_buf_write = rte_malloc(\"memcpy\", LARGE_BUFFER_SIZE + ALIGNMENT_UNIT, ALIGNMENT_UNIT);\n\tif (large_buf_write == NULL)\n\t\tgoto error_large_buf_write;\n\n\tsmall_buf_read = rte_malloc(\"memcpy\", SMALL_BUFFER_SIZE + ALIGNMENT_UNIT, ALIGNMENT_UNIT);\n\tif (small_buf_read == NULL)\n\t\tgoto error_small_buf_read;\n\n\tsmall_buf_write = rte_malloc(\"memcpy\", SMALL_BUFFER_SIZE + ALIGNMENT_UNIT, ALIGNMENT_UNIT);\n\tif (small_buf_write == NULL)\n\t\tgoto error_small_buf_write;\n\n\tfor (i = 0; i < LARGE_BUFFER_SIZE; i++)\n\t\tlarge_buf_read[i] = rte_rand();\n\tfor (i = 0; i < SMALL_BUFFER_SIZE; i++)\n\t\tsmall_buf_read[i] = rte_rand();\n\n\treturn 0;\n\nerror_small_buf_write:\n\trte_free(small_buf_read);\nerror_small_buf_read:\n\trte_free(large_buf_write);\nerror_large_buf_write:\n\trte_free(large_buf_read);\nerror_large_buf_read:\n\tprintf(\"ERROR: not enough memory\\n\");\n\treturn -1;\n}\n\n/* Cleanup data buffers */\nstatic void\nfree_buffers(void)\n{\n\trte_free(large_buf_read);\n\trte_free(large_buf_write);\n\trte_free(small_buf_read);\n\trte_free(small_buf_write);\n}\n\n/*\n * Get a random offset into large array, with enough space needed to perform\n * max copy size. Offset is aligned, uoffset is used for unalignment setting.\n */\nstatic inline size_t\nget_rand_offset(size_t uoffset)\n{\n\treturn (((rte_rand() % (LARGE_BUFFER_SIZE - SMALL_BUFFER_SIZE)) &\n\t\t\t~(ALIGNMENT_UNIT - 1)) + uoffset);\n}\n\n/* Fill in source and destination addresses. */\nstatic inline void\nfill_addr_arrays(size_t *dst_addr, int is_dst_cached, size_t dst_uoffset,\n\t\t\t\t size_t *src_addr, int is_src_cached, size_t src_uoffset)\n{\n\tunsigned int i;\n\n\tfor (i = 0; i < TEST_BATCH_SIZE; i++) {\n\t\tdst_addr[i] = (is_dst_cached) ? dst_uoffset : get_rand_offset(dst_uoffset);\n\t\tsrc_addr[i] = (is_src_cached) ? src_uoffset : get_rand_offset(src_uoffset);\n\t}\n}\n\n/*\n * WORKAROUND: For some reason the first test doing an uncached write\n * takes a very long time (~25 times longer than is expected). So we do\n * it once without timing.\n */\nstatic void\ndo_uncached_write(uint8_t *dst, int is_dst_cached,\n\t\t\t\t const uint8_t *src, int is_src_cached, size_t size)\n{\n\tunsigned i, j;\n\tsize_t dst_addrs[TEST_BATCH_SIZE], src_addrs[TEST_BATCH_SIZE];\n\n\tfor (i = 0; i < (TEST_ITERATIONS / TEST_BATCH_SIZE); i++) {\n\t\tfill_addr_arrays(dst_addrs, is_dst_cached, 0,\n\t\t\t\t\t\t src_addrs, is_src_cached, 0);\n\t\tfor (j = 0; j < TEST_BATCH_SIZE; j++) {\n\t\t\trte_memcpy(dst+dst_addrs[j], src+src_addrs[j], size);\n\t\t}\n\t}\n}\n\n/*\n * Run a single memcpy performance test. This is a macro to ensure that if\n * the \"size\" parameter is a constant it won't be converted to a variable.\n */\n#define SINGLE_PERF_TEST(dst, is_dst_cached, dst_uoffset, \\\n src, is_src_cached, src_uoffset, size) \\\ndo { \\\n unsigned int iter, t; \\\n size_t dst_addrs[TEST_BATCH_SIZE], src_addrs[TEST_BATCH_SIZE]; \\\n uint64_t start_time, total_time = 0; \\\n uint64_t total_time2 = 0; \\\n for (iter = 0; iter < (TEST_ITERATIONS / TEST_BATCH_SIZE); iter++) { \\\n fill_addr_arrays(dst_addrs, is_dst_cached, dst_uoffset, \\\n src_addrs, is_src_cached, src_uoffset); \\\n start_time = rte_rdtsc(); \\\n for (t = 0; t < TEST_BATCH_SIZE; t++) \\\n rte_memcpy(dst+dst_addrs[t], src+src_addrs[t], size); \\\n total_time += rte_rdtsc() - start_time; \\\n } \\\n for (iter = 0; iter < (TEST_ITERATIONS / TEST_BATCH_SIZE); iter++) { \\\n fill_addr_arrays(dst_addrs, is_dst_cached, dst_uoffset, \\\n src_addrs, is_src_cached, src_uoffset); \\\n start_time = rte_rdtsc(); \\\n for (t = 0; t < TEST_BATCH_SIZE; t++) \\\n memcpy(dst+dst_addrs[t], src+src_addrs[t], size); \\\n total_time2 += rte_rdtsc() - start_time; \\\n } \\\n printf(\"%8.0f -\", (double)total_time /TEST_ITERATIONS); \\\n printf(\"%5.0f\", (double)total_time2 / TEST_ITERATIONS); \\\n} while (0)\n\n/* Run aligned memcpy tests for each cached/uncached permutation */\n#define ALL_PERF_TESTS_FOR_SIZE(n) \\\ndo { \\\n if (__builtin_constant_p(n)) \\\n printf(\"\\nC%6u\", (unsigned)n); \\\n else \\\n printf(\"\\n%7u\", (unsigned)n); \\\n SINGLE_PERF_TEST(small_buf_write, 1, 0, small_buf_read, 1, 0, n); \\\n SINGLE_PERF_TEST(large_buf_write, 0, 0, small_buf_read, 1, 0, n); \\\n SINGLE_PERF_TEST(small_buf_write, 1, 0, large_buf_read, 0, 0, n); \\\n SINGLE_PERF_TEST(large_buf_write, 0, 0, large_buf_read, 0, 0, n); \\\n} while (0)\n\n/* Run unaligned memcpy tests for each cached/uncached permutation */\n#define ALL_PERF_TESTS_FOR_SIZE_UNALIGNED(n) \\\ndo { \\\n if (__builtin_constant_p(n)) \\\n printf(\"\\nC%6u\", (unsigned)n); \\\n else \\\n printf(\"\\n%7u\", (unsigned)n); \\\n SINGLE_PERF_TEST(small_buf_write, 1, 1, small_buf_read, 1, 5, n); \\\n SINGLE_PERF_TEST(large_buf_write, 0, 1, small_buf_read, 1, 5, n); \\\n SINGLE_PERF_TEST(small_buf_write, 1, 1, large_buf_read, 0, 5, n); \\\n SINGLE_PERF_TEST(large_buf_write, 0, 1, large_buf_read, 0, 5, n); \\\n} while (0)\n\n/* Run memcpy tests for constant length */\n#define ALL_PERF_TEST_FOR_CONSTANT \\\ndo { \\\n TEST_CONSTANT(6U); TEST_CONSTANT(64U); TEST_CONSTANT(128U); \\\n TEST_CONSTANT(192U); TEST_CONSTANT(256U); TEST_CONSTANT(512U); \\\n TEST_CONSTANT(768U); TEST_CONSTANT(1024U); TEST_CONSTANT(1536U); \\\n} while (0)\n\n/* Run all memcpy tests for aligned constant cases */\nstatic inline void\nperf_test_constant_aligned(void)\n{\n#define TEST_CONSTANT ALL_PERF_TESTS_FOR_SIZE\n\tALL_PERF_TEST_FOR_CONSTANT;\n#undef TEST_CONSTANT\n}\n\n/* Run all memcpy tests for unaligned constant cases */\nstatic inline void\nperf_test_constant_unaligned(void)\n{\n#define TEST_CONSTANT ALL_PERF_TESTS_FOR_SIZE_UNALIGNED\n\tALL_PERF_TEST_FOR_CONSTANT;\n#undef TEST_CONSTANT\n}\n\n/* Run all memcpy tests for aligned variable cases */\nstatic inline void\nperf_test_variable_aligned(void)\n{\n\tunsigned n = sizeof(buf_sizes) / sizeof(buf_sizes[0]);\n\tunsigned i;\n\tfor (i = 0; i < n; i++) {\n\t\tALL_PERF_TESTS_FOR_SIZE((size_t)buf_sizes[i]);\n\t}\n}\n\n/* Run all memcpy tests for unaligned variable cases */\nstatic inline void\nperf_test_variable_unaligned(void)\n{\n\tunsigned n = sizeof(buf_sizes) / sizeof(buf_sizes[0]);\n\tunsigned i;\n\tfor (i = 0; i < n; i++) {\n\t\tALL_PERF_TESTS_FOR_SIZE_UNALIGNED((size_t)buf_sizes[i]);\n\t}\n}\n\n/* Run all memcpy tests */\nstatic int\nperf_test(void)\n{\n\tint ret;\n\n\tret = init_buffers();\n\tif (ret != 0)\n\t\treturn ret;\n\n#if TEST_VALUE_RANGE != 0\n\t/* Set up buf_sizes array, if required */\n\tunsigned i;\n\tfor (i = 0; i < TEST_VALUE_RANGE; i++)\n\t\tbuf_sizes[i] = i;\n#endif\n\n\t/* See function comment */\n\tdo_uncached_write(large_buf_write, 0, small_buf_read, 1, SMALL_BUFFER_SIZE);\n\n\tprintf(\"\\n** rte_memcpy() - memcpy perf. tests (C = compile-time constant) **\\n\"\n\t\t \"======= ============== ============== ============== ==============\\n\"\n\t\t \" Size Cache to cache Cache to mem Mem to cache Mem to mem\\n\"\n\t\t \"(bytes) (ticks) (ticks) (ticks) (ticks)\\n\"\n\t\t \"------- -------------- -------------- -------------- --------------\");\n\n\tprintf(\"\\n========================== %2dB aligned ============================\", ALIGNMENT_UNIT);\n\t/* Do aligned tests where size is a variable */\n\tperf_test_variable_aligned();\n\tprintf(\"\\n------- -------------- -------------- -------------- --------------\");\n\t/* Do aligned tests where size is a compile-time constant */\n\tperf_test_constant_aligned();\n\tprintf(\"\\n=========================== Unaligned =============================\");\n\t/* Do unaligned tests where size is a variable */\n\tperf_test_variable_unaligned();\n\tprintf(\"\\n------- -------------- -------------- -------------- --------------\");\n\t/* Do unaligned tests where size is a compile-time constant */\n\tperf_test_constant_unaligned();\n\tprintf(\"\\n======= ============== ============== ============== ==============\\n\\n\");\n\n\tfree_buffers();\n\n\treturn 0;\n}\n\nstatic int\ntest_memcpy_perf(void)\n{\n\tint ret;\n\n\tret = perf_test();\n\tif (ret != 0)\n\t\treturn -1;\n\treturn 0;\n}\n\nstatic struct test_command memcpy_perf_cmd = {\n\t.command = \"memcpy_perf_autotest\",\n\t.callback = test_memcpy_perf,\n};\nREGISTER_TEST_COMMAND(memcpy_perf_cmd);\n" }, { "path": "app/test/test_memory.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n\n#include \"test.h\"\n\n/*\n * Memory\n * ======\n *\n * - Dump the mapped memory. The python-expect script checks that at\n * least one line is dumped.\n *\n * - Check that memory size is different than 0.\n *\n * - Try to read all memory; it should not segfault.\n */\n\nstatic int\ntest_memory(void)\n{\n\tuint64_t s;\n\tunsigned i, j;\n\tconst struct rte_memseg *mem;\n\n\t/*\n\t * dump the mapped memory: the python-expect script checks\n\t * that at least one line is dumped\n\t */\n\tprintf(\"Dump memory layout\\n\");\n\trte_dump_physmem_layout(stdout);\n\n\t/* check that memory size is != 0 */\n\ts = rte_eal_get_physmem_size();\n\tif (s == 0) {\n\t\tprintf(\"No memory detected\\n\");\n\t\treturn -1;\n\t}\n\n\t/* try to read memory (should not segfault) */\n\tmem = rte_eal_get_physmem_layout();\n\tfor (i = 0; i < RTE_MAX_MEMSEG && mem[i].addr != NULL ; i++) {\n\n\t\t/* check memory */\n\t\tfor (j = 0; j\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n/*\n * Mempool\n * =======\n *\n * Basic tests: done on one core with and without cache:\n *\n * - Get one object, put one object\n * - Get two objects, put two objects\n * - Get all objects, test that their content is not modified and\n * put them back in the pool.\n */\n\n#define N 65536\n#define TIME_S 5\n#define MEMPOOL_ELT_SIZE 2048\n#define MAX_KEEP 128\n#define MEMPOOL_SIZE ((rte_lcore_count()*(MAX_KEEP+RTE_MEMPOOL_CACHE_MAX_SIZE))-1)\n\nstatic struct rte_mempool *mp;\nstatic struct rte_mempool *mp_cache, *mp_nocache;\n\nstatic rte_atomic32_t synchro;\n\n\n\n/*\n * save the object number in the first 4 bytes of object data. All\n * other bytes are set to 0.\n */\nstatic void\nmy_obj_init(struct rte_mempool *mp, __attribute__((unused)) void *arg,\n\t void *obj, unsigned i)\n{\n\tuint32_t *objnum = obj;\n\tmemset(obj, 0, mp->elt_size);\n\t*objnum = i;\n}\n\n/* basic tests (done on one core) */\nstatic int\ntest_mempool_basic(void)\n{\n\tuint32_t *objnum;\n\tvoid **objtable;\n\tvoid *obj, *obj2;\n\tchar *obj_data;\n\tint ret = 0;\n\tunsigned i, j;\n\n\t/* dump the mempool status */\n\trte_mempool_dump(stdout, mp);\n\n\tprintf(\"get an object\\n\");\n\tif (rte_mempool_get(mp, &obj) < 0)\n\t\treturn -1;\n\trte_mempool_dump(stdout, mp);\n\n\t/* tests that improve coverage */\n\tprintf(\"get object count\\n\");\n\tif (rte_mempool_count(mp) != MEMPOOL_SIZE - 1)\n\t\treturn -1;\n\n\tprintf(\"get private data\\n\");\n\tif (rte_mempool_get_priv(mp) !=\n\t\t\t(char*) mp + MEMPOOL_HEADER_SIZE(mp, mp->pg_num))\n\t\treturn -1;\n\n\tprintf(\"get physical address of an object\\n\");\n\tif (MEMPOOL_IS_CONTIG(mp) &&\n\t\t\trte_mempool_virt2phy(mp, obj) !=\n\t\t\t(phys_addr_t) (mp->phys_addr +\n\t\t\t(phys_addr_t) ((char*) obj - (char*) mp)))\n\t\treturn -1;\n\n\tprintf(\"put the object back\\n\");\n\trte_mempool_put(mp, obj);\n\trte_mempool_dump(stdout, mp);\n\n\tprintf(\"get 2 objects\\n\");\n\tif (rte_mempool_get(mp, &obj) < 0)\n\t\treturn -1;\n\tif (rte_mempool_get(mp, &obj2) < 0) {\n\t\trte_mempool_put(mp, obj);\n\t\treturn -1;\n\t}\n\trte_mempool_dump(stdout, mp);\n\n\tprintf(\"put the objects back\\n\");\n\trte_mempool_put(mp, obj);\n\trte_mempool_put(mp, obj2);\n\trte_mempool_dump(stdout, mp);\n\n\t/*\n\t * get many objects: we cannot get them all because the cache\n\t * on other cores may not be empty.\n\t */\n\tobjtable = malloc(MEMPOOL_SIZE * sizeof(void *));\n\tif (objtable == NULL) {\n\t\treturn -1;\n\t}\n\n\tfor (i=0; i MEMPOOL_SIZE) {\n\t\t\tprintf(\"bad object number\\n\");\n\t\t\tret = -1;\n\t\t\tbreak;\n\t\t}\n\t\tfor (j=sizeof(*objnum); jelt_size; j++) {\n\t\t\tif (obj_data[j] != 0)\n\t\t\t\tret = -1;\n\t\t}\n\n\t\trte_mempool_put(mp, objtable[i]);\n\t}\n\n\tfree(objtable);\n\tif (ret == -1)\n\t\tprintf(\"objects were modified!\\n\");\n\n\treturn ret;\n}\n\nstatic int test_mempool_creation_with_exceeded_cache_size(void)\n{\n\tstruct rte_mempool *mp_cov;\n\n\tmp_cov = rte_mempool_create(\"test_mempool_creation_with_exceeded_cache_size\", MEMPOOL_SIZE,\n\t\t\t\t\t MEMPOOL_ELT_SIZE,\n\t\t\t\t\t RTE_MEMPOOL_CACHE_MAX_SIZE + 32, 0,\n\t\t\t\t\t NULL, NULL,\n\t\t\t\t\t my_obj_init, NULL,\n\t\t\t\t\t SOCKET_ID_ANY, 0);\n\tif(NULL != mp_cov) {\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic struct rte_mempool *mp_spsc;\nstatic rte_spinlock_t scsp_spinlock;\nstatic void *scsp_obj_table[MAX_KEEP];\n\n/*\n * single producer function\n */\nstatic int test_mempool_single_producer(void)\n{\n\tunsigned int i;\n\tvoid *obj = NULL;\n\tuint64_t start_cycles, end_cycles;\n\tuint64_t duration = rte_get_timer_hz() * 8;\n\n\tstart_cycles = rte_get_timer_cycles();\n\twhile (1) {\n\t\tend_cycles = rte_get_timer_cycles();\n\t\t/* duration uses up, stop producing */\n\t\tif (start_cycles + duration < end_cycles)\n\t\t\tbreak;\n\t\trte_spinlock_lock(&scsp_spinlock);\n\t\tfor (i = 0; i < MAX_KEEP; i ++) {\n\t\t\tif (NULL != scsp_obj_table[i]) {\n\t\t\t\tobj = scsp_obj_table[i];\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\trte_spinlock_unlock(&scsp_spinlock);\n\t\tif (i >= MAX_KEEP) {\n\t\t\tcontinue;\n\t\t}\n\t\tif (rte_mempool_from_obj(obj) != mp_spsc) {\n\t\t\tprintf(\"test_mempool_single_producer there is an obj not owned by this mempool\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\trte_mempool_sp_put(mp_spsc, obj);\n\t\trte_spinlock_lock(&scsp_spinlock);\n\t\tscsp_obj_table[i] = NULL;\n\t\trte_spinlock_unlock(&scsp_spinlock);\n\t}\n\n\treturn 0;\n}\n\n/*\n * single consumer function\n */\nstatic int test_mempool_single_consumer(void)\n{\n\tunsigned int i;\n\tvoid * obj;\n\tuint64_t start_cycles, end_cycles;\n\tuint64_t duration = rte_get_timer_hz() * 5;\n\n\tstart_cycles = rte_get_timer_cycles();\n\twhile (1) {\n\t\tend_cycles = rte_get_timer_cycles();\n\t\t/* duration uses up, stop consuming */\n\t\tif (start_cycles + duration < end_cycles)\n\t\t\tbreak;\n\t\trte_spinlock_lock(&scsp_spinlock);\n\t\tfor (i = 0; i < MAX_KEEP; i ++) {\n\t\t\tif (NULL == scsp_obj_table[i])\n\t\t\t\tbreak;\n\t\t}\n\t\trte_spinlock_unlock(&scsp_spinlock);\n\t\tif (i >= MAX_KEEP)\n\t\t\tcontinue;\n\t\tif (rte_mempool_sc_get(mp_spsc, &obj) < 0)\n\t\t\tbreak;\n\t\trte_spinlock_lock(&scsp_spinlock);\n\t\tscsp_obj_table[i] = obj;\n\t\trte_spinlock_unlock(&scsp_spinlock);\n\t}\n\n\treturn 0;\n}\n\n/*\n * test function for mempool test based on singple consumer and single producer, can run on one lcore only\n */\nstatic int test_mempool_launch_single_consumer(__attribute__((unused)) void *arg)\n{\n\treturn test_mempool_single_consumer();\n}\n\nstatic void my_mp_init(struct rte_mempool * mp, __attribute__((unused)) void * arg)\n{\n\tprintf(\"mempool name is %s\\n\", mp->name);\n\t/* nothing to be implemented here*/\n\treturn ;\n}\n\n/*\n * it tests the mempool operations based on singple producer and single consumer\n */\nstatic int\ntest_mempool_sp_sc(void)\n{\n\tint ret = 0;\n\tunsigned lcore_id = rte_lcore_id();\n\tunsigned lcore_next;\n\n\t/* create a mempool with single producer/consumer ring */\n\tif (NULL == mp_spsc) {\n\t\tmp_spsc = rte_mempool_create(\"test_mempool_sp_sc\", MEMPOOL_SIZE,\n\t\t\t\t\t\tMEMPOOL_ELT_SIZE, 0, 0,\n\t\t\t\t\t\tmy_mp_init, NULL,\n\t\t\t\t\t\tmy_obj_init, NULL,\n\t\t\t\t\t\tSOCKET_ID_ANY, MEMPOOL_F_NO_CACHE_ALIGN | MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET);\n\t\tif (NULL == mp_spsc) {\n\t\t\treturn -1;\n\t\t}\n\t}\n\tif (rte_mempool_lookup(\"test_mempool_sp_sc\") != mp_spsc) {\n\t\tprintf(\"Cannot lookup mempool from its name\\n\");\n\t\treturn -1;\n\t}\n\tlcore_next = rte_get_next_lcore(lcore_id, 0, 1);\n\tif (RTE_MAX_LCORE <= lcore_next)\n\t\treturn -1;\n\tif (rte_eal_lcore_role(lcore_next) != ROLE_RTE)\n\t\treturn -1;\n\trte_spinlock_init(&scsp_spinlock);\n\tmemset(scsp_obj_table, 0, sizeof(scsp_obj_table));\n\trte_eal_remote_launch(test_mempool_launch_single_consumer, NULL, lcore_next);\n\tif(test_mempool_single_producer() < 0)\n\t\tret = -1;\n\n\tif(rte_eal_wait_lcore(lcore_next) < 0)\n\t\tret = -1;\n\n\treturn ret;\n}\n\n/*\n * it tests some more basic of mempool\n */\nstatic int\ntest_mempool_basic_ex(struct rte_mempool * mp)\n{\n\tunsigned i;\n\tvoid **obj;\n\tvoid *err_obj;\n\tint ret = -1;\n\n\tif (mp == NULL)\n\t\treturn ret;\n\n\tobj = rte_calloc(\"test_mempool_basic_ex\", MEMPOOL_SIZE , sizeof(void *), 0);\n\tif (obj == NULL) {\n\t\tprintf(\"test_mempool_basic_ex fail to rte_malloc\\n\");\n\t\treturn ret;\n\t}\n\tprintf(\"test_mempool_basic_ex now mempool (%s) has %u free entries\\n\", mp->name, rte_mempool_free_count(mp));\n\tif (rte_mempool_full(mp) != 1) {\n\t\tprintf(\"test_mempool_basic_ex the mempool is not full but it should be\\n\");\n\t\tgoto fail_mp_basic_ex;\n\t}\n\n\tfor (i = 0; i < MEMPOOL_SIZE; i ++) {\n\t\tif (rte_mempool_mc_get(mp, &obj[i]) < 0) {\n\t\t\tprintf(\"fail_mp_basic_ex fail to get mempool object for [%u]\\n\", i);\n\t\t\tgoto fail_mp_basic_ex;\n\t\t}\n\t}\n\tif (rte_mempool_mc_get(mp, &err_obj) == 0) {\n\t\tprintf(\"test_mempool_basic_ex get an impossible obj from mempool\\n\");\n\t\tgoto fail_mp_basic_ex;\n\t}\n\tprintf(\"number: %u\\n\", i);\n\tif (rte_mempool_empty(mp) != 1) {\n\t\tprintf(\"test_mempool_basic_ex the mempool is not empty but it should be\\n\");\n\t\tgoto fail_mp_basic_ex;\n\t}\n\n\tfor (i = 0; i < MEMPOOL_SIZE; i ++) {\n\t\trte_mempool_mp_put(mp, obj[i]);\n\t}\n\tif (rte_mempool_full(mp) != 1) {\n\t\tprintf(\"test_mempool_basic_ex the mempool is not full but it should be\\n\");\n\t\tgoto fail_mp_basic_ex;\n\t}\n\n\tret = 0;\n\nfail_mp_basic_ex:\n\tif (obj != NULL)\n\t\trte_free((void *)obj);\n\n\treturn ret;\n}\n\nstatic int\ntest_mempool_same_name_twice_creation(void)\n{\n\tstruct rte_mempool *mp_tc;\n\n\tmp_tc = rte_mempool_create(\"test_mempool_same_name_twice_creation\", MEMPOOL_SIZE,\n\t\t\t\t\t\tMEMPOOL_ELT_SIZE, 0, 0,\n\t\t\t\t\t\tNULL, NULL,\n\t\t\t\t\t\tNULL, NULL,\n\t\t\t\t\t\tSOCKET_ID_ANY, 0);\n\tif (NULL == mp_tc)\n\t\treturn -1;\n\n\tmp_tc = rte_mempool_create(\"test_mempool_same_name_twice_creation\", MEMPOOL_SIZE,\n\t\t\t\t\t\tMEMPOOL_ELT_SIZE, 0, 0,\n\t\t\t\t\t\tNULL, NULL,\n\t\t\t\t\t\tNULL, NULL,\n\t\t\t\t\t\tSOCKET_ID_ANY, 0);\n\tif (NULL != mp_tc)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * BAsic test for mempool_xmem functions.\n */\nstatic int\ntest_mempool_xmem_misc(void)\n{\n\tuint32_t elt_num, total_size;\n\tsize_t sz;\n\tssize_t usz;\n\n\telt_num = MAX_KEEP;\n\ttotal_size = rte_mempool_calc_obj_size(MEMPOOL_ELT_SIZE, 0, NULL);\n\tsz = rte_mempool_xmem_size(elt_num, total_size, MEMPOOL_PG_SHIFT_MAX);\n\n\tusz = rte_mempool_xmem_usage(NULL, elt_num, total_size, 0, 1,\n\t\tMEMPOOL_PG_SHIFT_MAX);\n\n\tif(sz != (size_t)usz) {\n\t\tprintf(\"failure @ %s: rte_mempool_xmem_usage(%u, %u) \"\n\t\t\t\"returns: %#zx, while expected: %#zx;\\n\",\n\t\t\t__func__, elt_num, total_size, sz, (size_t)usz);\n\t\treturn (-1);\n\t}\n\n\treturn (0);\n}\n\nstatic int\ntest_mempool(void)\n{\n\trte_atomic32_init(&synchro);\n\n\t/* create a mempool (without cache) */\n\tif (mp_nocache == NULL)\n\t\tmp_nocache = rte_mempool_create(\"test_nocache\", MEMPOOL_SIZE,\n\t\t\t\t\t\tMEMPOOL_ELT_SIZE, 0, 0,\n\t\t\t\t\t\tNULL, NULL,\n\t\t\t\t\t\tmy_obj_init, NULL,\n\t\t\t\t\t\tSOCKET_ID_ANY, 0);\n\tif (mp_nocache == NULL)\n\t\treturn -1;\n\n\t/* create a mempool (with cache) */\n\tif (mp_cache == NULL)\n\t\tmp_cache = rte_mempool_create(\"test_cache\", MEMPOOL_SIZE,\n\t\t\t\t\t MEMPOOL_ELT_SIZE,\n\t\t\t\t\t RTE_MEMPOOL_CACHE_MAX_SIZE, 0,\n\t\t\t\t\t NULL, NULL,\n\t\t\t\t\t my_obj_init, NULL,\n\t\t\t\t\t SOCKET_ID_ANY, 0);\n\tif (mp_cache == NULL)\n\t\treturn -1;\n\n\n\t/* retrieve the mempool from its name */\n\tif (rte_mempool_lookup(\"test_nocache\") != mp_nocache) {\n\t\tprintf(\"Cannot lookup mempool from its name\\n\");\n\t\treturn -1;\n\t}\n\n\trte_mempool_list_dump(stdout);\n\n\t/* basic tests without cache */\n\tmp = mp_nocache;\n\tif (test_mempool_basic() < 0)\n\t\treturn -1;\n\n\t/* basic tests with cache */\n\tmp = mp_cache;\n\tif (test_mempool_basic() < 0)\n\t\treturn -1;\n\n\t/* more basic tests without cache */\n\tif (test_mempool_basic_ex(mp_nocache) < 0)\n\t\treturn -1;\n\n\t/* mempool operation test based on single producer and single comsumer */\n\tif (test_mempool_sp_sc() < 0)\n\t\treturn -1;\n\n\tif (test_mempool_creation_with_exceeded_cache_size() < 0)\n\t\treturn -1;\n\n\tif (test_mempool_same_name_twice_creation() < 0)\n\t\treturn -1;\n\n\tif (test_mempool_xmem_misc() < 0)\n\t\treturn -1;\n\n\trte_mempool_list_dump(stdout);\n\n\treturn 0;\n}\n\nstatic struct test_command mempool_cmd = {\n\t.command = \"mempool_autotest\",\n\t.callback = test_mempool,\n};\nREGISTER_TEST_COMMAND(mempool_cmd);\n" }, { "path": "app/test/test_mempool_perf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n/*\n * Mempool performance\n * =======\n *\n * Each core get *n_keep* objects per bulk of *n_get_bulk*. Then,\n * objects are put back in the pool per bulk of *n_put_bulk*.\n *\n * This sequence is done during TIME_S seconds.\n *\n * This test is done on the following configurations:\n *\n * - Cores configuration (*cores*)\n *\n * - One core with cache\n * - Two cores with cache\n * - Max. cores with cache\n * - One core without cache\n * - Two cores without cache\n * - Max. cores without cache\n *\n * - Bulk size (*n_get_bulk*, *n_put_bulk*)\n *\n * - Bulk get from 1 to 32\n * - Bulk put from 1 to 32\n *\n * - Number of kept objects (*n_keep*)\n *\n * - 32\n * - 128\n */\n\n#define N 65536\n#define TIME_S 5\n#define MEMPOOL_ELT_SIZE 2048\n#define MAX_KEEP 128\n#define MEMPOOL_SIZE ((rte_lcore_count()*(MAX_KEEP+RTE_MEMPOOL_CACHE_MAX_SIZE))-1)\n\nstatic struct rte_mempool *mp;\nstatic struct rte_mempool *mp_cache, *mp_nocache;\n\nstatic rte_atomic32_t synchro;\n\n/* number of objects in one bulk operation (get or put) */\nstatic unsigned n_get_bulk;\nstatic unsigned n_put_bulk;\n\n/* number of objects retrived from mempool before putting them back */\nstatic unsigned n_keep;\n\n/* number of enqueues / dequeues */\nstruct mempool_test_stats {\n\tunsigned enq_count;\n} __rte_cache_aligned;\n\nstatic struct mempool_test_stats stats[RTE_MAX_LCORE];\n\n/*\n * save the object number in the first 4 bytes of object data. All\n * other bytes are set to 0.\n */\nstatic void\nmy_obj_init(struct rte_mempool *mp, __attribute__((unused)) void *arg,\n\t void *obj, unsigned i)\n{\n\tuint32_t *objnum = obj;\n\tmemset(obj, 0, mp->elt_size);\n\t*objnum = i;\n}\n\nstatic int\nper_lcore_mempool_test(__attribute__((unused)) void *arg)\n{\n\tvoid *obj_table[MAX_KEEP];\n\tunsigned i, idx;\n\tunsigned lcore_id = rte_lcore_id();\n\tint ret;\n\tuint64_t start_cycles, end_cycles;\n\tuint64_t time_diff = 0, hz = rte_get_timer_hz();\n\n\t/* n_get_bulk and n_put_bulk must be divisors of n_keep */\n\tif (((n_keep / n_get_bulk) * n_get_bulk) != n_keep)\n\t\treturn -1;\n\tif (((n_keep / n_put_bulk) * n_put_bulk) != n_keep)\n\t\treturn -1;\n\n\tstats[lcore_id].enq_count = 0;\n\n\t/* wait synchro for slaves */\n\tif (lcore_id != rte_get_master_lcore())\n\t\twhile (rte_atomic32_read(&synchro) == 0);\n\n\tstart_cycles = rte_get_timer_cycles();\n\n\twhile (time_diff/hz < TIME_S) {\n\t\tfor (i = 0; likely(i < (N/n_keep)); i++) {\n\t\t\t/* get n_keep objects by bulk of n_bulk */\n\t\t\tidx = 0;\n\t\t\twhile (idx < n_keep) {\n\t\t\t\tret = rte_mempool_get_bulk(mp, &obj_table[idx],\n\t\t\t\t\t\t\t n_get_bulk);\n\t\t\t\tif (unlikely(ret < 0)) {\n\t\t\t\t\trte_mempool_dump(stdout, mp);\n\t\t\t\t\trte_ring_dump(stdout, mp->ring);\n\t\t\t\t\t/* in this case, objects are lost... */\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t\tidx += n_get_bulk;\n\t\t\t}\n\n\t\t\t/* put the objects back */\n\t\t\tidx = 0;\n\t\t\twhile (idx < n_keep) {\n\t\t\t\trte_mempool_put_bulk(mp, &obj_table[idx],\n\t\t\t\t\t\t n_put_bulk);\n\t\t\t\tidx += n_put_bulk;\n\t\t\t}\n\t\t}\n\t\tend_cycles = rte_get_timer_cycles();\n\t\ttime_diff = end_cycles - start_cycles;\n\t\tstats[lcore_id].enq_count += N;\n\t}\n\n\treturn 0;\n}\n\n/* launch all the per-lcore test, and display the result */\nstatic int\nlaunch_cores(unsigned cores)\n{\n\tunsigned lcore_id;\n\tunsigned rate;\n\tint ret;\n\tunsigned cores_save = cores;\n\n\trte_atomic32_set(&synchro, 0);\n\n\t/* reset stats */\n\tmemset(stats, 0, sizeof(stats));\n\n\tprintf(\"mempool_autotest cache=%u cores=%u n_get_bulk=%u \"\n\t \"n_put_bulk=%u n_keep=%u \",\n\t (unsigned) mp->cache_size, cores, n_get_bulk, n_put_bulk, n_keep);\n\n\tif (rte_mempool_count(mp) != MEMPOOL_SIZE) {\n\t\tprintf(\"mempool is not full\\n\");\n\t\treturn -1;\n\t}\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (cores == 1)\n\t\t\tbreak;\n\t\tcores--;\n\t\trte_eal_remote_launch(per_lcore_mempool_test,\n\t\t\t\t NULL, lcore_id);\n\t}\n\n\t/* start synchro and launch test on master */\n\trte_atomic32_set(&synchro, 1);\n\n\tret = per_lcore_mempool_test(NULL);\n\n\tcores = cores_save;\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (cores == 1)\n\t\t\tbreak;\n\t\tcores--;\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\tret = -1;\n\t}\n\n\tif (ret < 0) {\n\t\tprintf(\"per-lcore test returned -1\\n\");\n\t\treturn -1;\n\t}\n\n\trate = 0;\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++)\n\t\trate += (stats[lcore_id].enq_count / TIME_S);\n\n\tprintf(\"rate_persec=%u\\n\", rate);\n\n\treturn 0;\n}\n\n/* for a given number of core, launch all test cases */\nstatic int\ndo_one_mempool_test(unsigned cores)\n{\n\tunsigned bulk_tab_get[] = { 1, 4, 32, 0 };\n\tunsigned bulk_tab_put[] = { 1, 4, 32, 0 };\n\tunsigned keep_tab[] = { 32, 128, 0 };\n\tunsigned *get_bulk_ptr;\n\tunsigned *put_bulk_ptr;\n\tunsigned *keep_ptr;\n\tint ret;\n\n\tfor (get_bulk_ptr = bulk_tab_get; *get_bulk_ptr; get_bulk_ptr++) {\n\t\tfor (put_bulk_ptr = bulk_tab_put; *put_bulk_ptr; put_bulk_ptr++) {\n\t\t\tfor (keep_ptr = keep_tab; *keep_ptr; keep_ptr++) {\n\n\t\t\t\tn_get_bulk = *get_bulk_ptr;\n\t\t\t\tn_put_bulk = *put_bulk_ptr;\n\t\t\t\tn_keep = *keep_ptr;\n\t\t\t\tret = launch_cores(cores);\n\n\t\t\t\tif (ret < 0)\n\t\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\ntest_mempool_perf(void)\n{\n\trte_atomic32_init(&synchro);\n\n\t/* create a mempool (without cache) */\n\tif (mp_nocache == NULL)\n\t\tmp_nocache = rte_mempool_create(\"perf_test_nocache\", MEMPOOL_SIZE,\n\t\t\t\t\t\tMEMPOOL_ELT_SIZE, 0, 0,\n\t\t\t\t\t\tNULL, NULL,\n\t\t\t\t\t\tmy_obj_init, NULL,\n\t\t\t\t\t\tSOCKET_ID_ANY, 0);\n\tif (mp_nocache == NULL)\n\t\treturn -1;\n\n\t/* create a mempool (with cache) */\n\tif (mp_cache == NULL)\n\t\tmp_cache = rte_mempool_create(\"perf_test_cache\", MEMPOOL_SIZE,\n\t\t\t\t\t MEMPOOL_ELT_SIZE,\n\t\t\t\t\t RTE_MEMPOOL_CACHE_MAX_SIZE, 0,\n\t\t\t\t\t NULL, NULL,\n\t\t\t\t\t my_obj_init, NULL,\n\t\t\t\t\t SOCKET_ID_ANY, 0);\n\tif (mp_cache == NULL)\n\t\treturn -1;\n\n\t/* performance test with 1, 2 and max cores */\n\tprintf(\"start performance test (without cache)\\n\");\n\tmp = mp_nocache;\n\n\tif (do_one_mempool_test(1) < 0)\n\t\treturn -1;\n\n\tif (do_one_mempool_test(2) < 0)\n\t\treturn -1;\n\n\tif (do_one_mempool_test(rte_lcore_count()) < 0)\n\t\treturn -1;\n\n\t/* performance test with 1, 2 and max cores */\n\tprintf(\"start performance test (with cache)\\n\");\n\tmp = mp_cache;\n\n\tif (do_one_mempool_test(1) < 0)\n\t\treturn -1;\n\n\tif (do_one_mempool_test(2) < 0)\n\t\treturn -1;\n\n\tif (do_one_mempool_test(rte_lcore_count()) < 0)\n\t\treturn -1;\n\n\trte_mempool_list_dump(stdout);\n\n\treturn 0;\n}\n\nstatic struct test_command mempool_perf_cmd = {\n\t.command = \"mempool_perf_autotest\",\n\t.callback = test_mempool_perf,\n};\nREGISTER_TEST_COMMAND(mempool_perf_cmd);\n" }, { "path": "app/test/test_memzone.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \"../../lib/librte_eal/common/malloc_elem.h\"\n\n#include \"test.h\"\n\n/*\n * Memzone\n * =======\n *\n * - Search for three reserved zones or reserve them if they do not exist:\n *\n * - One is on any socket id.\n * - The second is on socket 0.\n * - The last one is on socket 1 (if socket 1 exists).\n *\n * - Check that the zones exist.\n *\n * - Check that the zones are cache-aligned.\n *\n * - Check that zones do not overlap.\n *\n * - Check that the zones are on the correct socket id.\n *\n * - Check that a lookup of the first zone returns the same pointer.\n *\n * - Check that it is not possible to create another zone with the\n * same name as an existing zone.\n *\n * - Check flags for specific huge page size reservation\n */\n\n/* Test if memory overlaps: return 1 if true, or 0 if false. */\nstatic int\nis_memory_overlap(phys_addr_t ptr1, size_t len1, phys_addr_t ptr2, size_t len2)\n{\n\tif (ptr2 >= ptr1 && (ptr2 - ptr1) < len1)\n\t\treturn 1;\n\telse if (ptr2 < ptr1 && (ptr1 - ptr2) < len2)\n\t\treturn 1;\n\treturn 0;\n}\n\nstatic int\ntest_memzone_invalid_alignment(void)\n{\n\tconst struct rte_memzone * mz;\n\n\tmz = rte_memzone_lookup(\"invalid_alignment\");\n\tif (mz != NULL) {\n\t\tprintf(\"Zone with invalid alignment has been reserved\\n\");\n\t\treturn -1;\n\t}\n\n\tmz = rte_memzone_reserve_aligned(\"invalid_alignment\", 100,\n\t\t\tSOCKET_ID_ANY, 0, 100);\n\tif (mz != NULL) {\n\t\tprintf(\"Zone with invalid alignment has been reserved\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic int\ntest_memzone_reserving_zone_size_bigger_than_the_maximum(void)\n{\n\tconst struct rte_memzone * mz;\n\n\tmz = rte_memzone_lookup(\"zone_size_bigger_than_the_maximum\");\n\tif (mz != NULL) {\n\t\tprintf(\"zone_size_bigger_than_the_maximum has been reserved\\n\");\n\t\treturn -1;\n\t}\n\n\tmz = rte_memzone_reserve(\"zone_size_bigger_than_the_maximum\", (size_t)-1,\n\t\t\tSOCKET_ID_ANY, 0);\n\tif (mz != NULL) {\n\t\tprintf(\"It is impossible to reserve such big a memzone\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntest_memzone_reserve_flags(void)\n{\n\tconst struct rte_memzone *mz;\n\tconst struct rte_memseg *ms;\n\tint hugepage_2MB_avail = 0;\n\tint hugepage_1GB_avail = 0;\n\tint hugepage_16MB_avail = 0;\n\tint hugepage_16GB_avail = 0;\n\tconst size_t size = 100;\n\tint i = 0;\n\tms = rte_eal_get_physmem_layout();\n\tfor (i = 0; i < RTE_MAX_MEMSEG; i++) {\n\t\tif (ms[i].hugepage_sz == RTE_PGSIZE_2M)\n\t\t\thugepage_2MB_avail = 1;\n\t\tif (ms[i].hugepage_sz == RTE_PGSIZE_1G)\n\t\t\thugepage_1GB_avail = 1;\n\t\tif (ms[i].hugepage_sz == RTE_PGSIZE_16M)\n\t\t\thugepage_16MB_avail = 1;\n\t\tif (ms[i].hugepage_sz == RTE_PGSIZE_16G)\n\t\t\thugepage_16GB_avail = 1;\n\t}\n\t/* Display the availability of 2MB ,1GB, 16MB, 16GB pages */\n\tif (hugepage_2MB_avail)\n\t\tprintf(\"2MB Huge pages available\\n\");\n\tif (hugepage_1GB_avail)\n\t\tprintf(\"1GB Huge pages available\\n\");\n\tif (hugepage_16MB_avail)\n\t\tprintf(\"16MB Huge pages available\\n\");\n\tif (hugepage_16GB_avail)\n\t\tprintf(\"16GB Huge pages available\\n\");\n\t/*\n\t * If 2MB pages available, check that a small memzone is correctly\n\t * reserved from 2MB huge pages when requested by the RTE_MEMZONE_2MB flag.\n\t * Also check that RTE_MEMZONE_SIZE_HINT_ONLY flag only defaults to an\n\t * available page size (i.e 1GB ) when 2MB pages are unavailable.\n\t */\n\tif (hugepage_2MB_avail) {\n\t\tmz = rte_memzone_reserve(\"flag_zone_2M\", size, SOCKET_ID_ANY,\n\t\t\t\tRTE_MEMZONE_2MB);\n\t\tif (mz == NULL) {\n\t\t\tprintf(\"MEMZONE FLAG 2MB\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tif (mz->hugepage_sz != RTE_PGSIZE_2M) {\n\t\t\tprintf(\"hugepage_sz not equal 2M\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tmz = rte_memzone_reserve(\"flag_zone_2M_HINT\", size, SOCKET_ID_ANY,\n\t\t\t\tRTE_MEMZONE_2MB|RTE_MEMZONE_SIZE_HINT_ONLY);\n\t\tif (mz == NULL) {\n\t\t\tprintf(\"MEMZONE FLAG 2MB\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tif (mz->hugepage_sz != RTE_PGSIZE_2M) {\n\t\t\tprintf(\"hugepage_sz not equal 2M\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Check if 1GB huge pages are unavailable, that function fails unless\n\t\t * HINT flag is indicated\n\t\t */\n\t\tif (!hugepage_1GB_avail) {\n\t\t\tmz = rte_memzone_reserve(\"flag_zone_1G_HINT\", size, SOCKET_ID_ANY,\n\t\t\t\t\tRTE_MEMZONE_1GB|RTE_MEMZONE_SIZE_HINT_ONLY);\n\t\t\tif (mz == NULL) {\n\t\t\t\tprintf(\"MEMZONE FLAG 1GB & HINT\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tif (mz->hugepage_sz != RTE_PGSIZE_2M) {\n\t\t\t\tprintf(\"hugepage_sz not equal 2M\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tmz = rte_memzone_reserve(\"flag_zone_1G\", size, SOCKET_ID_ANY,\n\t\t\t\t\tRTE_MEMZONE_1GB);\n\t\t\tif (mz != NULL) {\n\t\t\t\tprintf(\"MEMZONE FLAG 1GB\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\t/*As with 2MB tests above for 1GB huge page requests*/\n\tif (hugepage_1GB_avail) {\n\t\tmz = rte_memzone_reserve(\"flag_zone_1G\", size, SOCKET_ID_ANY,\n\t\t\t\tRTE_MEMZONE_1GB);\n\t\tif (mz == NULL) {\n\t\t\tprintf(\"MEMZONE FLAG 1GB\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tif (mz->hugepage_sz != RTE_PGSIZE_1G) {\n\t\t\tprintf(\"hugepage_sz not equal 1G\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tmz = rte_memzone_reserve(\"flag_zone_1G_HINT\", size, SOCKET_ID_ANY,\n\t\t\t\tRTE_MEMZONE_1GB|RTE_MEMZONE_SIZE_HINT_ONLY);\n\t\tif (mz == NULL) {\n\t\t\tprintf(\"MEMZONE FLAG 1GB\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tif (mz->hugepage_sz != RTE_PGSIZE_1G) {\n\t\t\tprintf(\"hugepage_sz not equal 1G\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Check if 1GB huge pages are unavailable, that function fails unless\n\t\t * HINT flag is indicated\n\t\t */\n\t\tif (!hugepage_2MB_avail) {\n\t\t\tmz = rte_memzone_reserve(\"flag_zone_2M_HINT\", size, SOCKET_ID_ANY,\n\t\t\t\t\tRTE_MEMZONE_2MB|RTE_MEMZONE_SIZE_HINT_ONLY);\n\t\t\tif (mz == NULL){\n\t\t\t\tprintf(\"MEMZONE FLAG 2MB & HINT\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tif (mz->hugepage_sz != RTE_PGSIZE_1G) {\n\t\t\t\tprintf(\"hugepage_sz not equal 1G\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tmz = rte_memzone_reserve(\"flag_zone_2M\", size, SOCKET_ID_ANY,\n\t\t\t\t\tRTE_MEMZONE_2MB);\n\t\t\tif (mz != NULL) {\n\t\t\t\tprintf(\"MEMZONE FLAG 2MB\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\n\t\tif (hugepage_2MB_avail && hugepage_1GB_avail) {\n\t\t\tmz = rte_memzone_reserve(\"flag_zone_2M_HINT\", size, SOCKET_ID_ANY,\n\t\t\t\t\t\t\t\tRTE_MEMZONE_2MB|RTE_MEMZONE_1GB);\n\t\t\tif (mz != NULL) {\n\t\t\t\tprintf(\"BOTH SIZES SET\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\t/*\n\t * This option is for IBM Power. If 16MB pages available, check\n\t * that a small memzone is correctly reserved from 16MB huge pages\n\t * when requested by the RTE_MEMZONE_16MB flag. Also check that\n\t * RTE_MEMZONE_SIZE_HINT_ONLY flag only defaults to an available\n\t * page size (i.e 16GB ) when 16MB pages are unavailable.\n\t */\n\tif (hugepage_16MB_avail) {\n\t\tmz = rte_memzone_reserve(\"flag_zone_16M\", size, SOCKET_ID_ANY,\n\t\t\t\tRTE_MEMZONE_16MB);\n\t\tif (mz == NULL) {\n\t\t\tprintf(\"MEMZONE FLAG 16MB\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tif (mz->hugepage_sz != RTE_PGSIZE_16M) {\n\t\t\tprintf(\"hugepage_sz not equal 16M\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tmz = rte_memzone_reserve(\"flag_zone_16M_HINT\", size,\n\t\tSOCKET_ID_ANY, RTE_MEMZONE_16MB|RTE_MEMZONE_SIZE_HINT_ONLY);\n\t\tif (mz == NULL) {\n\t\t\tprintf(\"MEMZONE FLAG 2MB\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tif (mz->hugepage_sz != RTE_PGSIZE_16M) {\n\t\t\tprintf(\"hugepage_sz not equal 16M\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Check if 1GB huge pages are unavailable, that function fails\n\t\t * unless HINT flag is indicated\n\t\t */\n\t\tif (!hugepage_16GB_avail) {\n\t\t\tmz = rte_memzone_reserve(\"flag_zone_16G_HINT\", size,\n\t\t\t\tSOCKET_ID_ANY,\n\t\t\t\tRTE_MEMZONE_16GB|RTE_MEMZONE_SIZE_HINT_ONLY);\n\t\t\tif (mz == NULL) {\n\t\t\t\tprintf(\"MEMZONE FLAG 16GB & HINT\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tif (mz->hugepage_sz != RTE_PGSIZE_16M) {\n\t\t\t\tprintf(\"hugepage_sz not equal 16M\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tmz = rte_memzone_reserve(\"flag_zone_16G\", size,\n\t\t\t\tSOCKET_ID_ANY, RTE_MEMZONE_16GB);\n\t\t\tif (mz != NULL) {\n\t\t\t\tprintf(\"MEMZONE FLAG 16GB\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\t/*As with 16MB tests above for 16GB huge page requests*/\n\tif (hugepage_16GB_avail) {\n\t\tmz = rte_memzone_reserve(\"flag_zone_16G\", size, SOCKET_ID_ANY,\n\t\t\t\tRTE_MEMZONE_16GB);\n\t\tif (mz == NULL) {\n\t\t\tprintf(\"MEMZONE FLAG 16GB\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tif (mz->hugepage_sz != RTE_PGSIZE_16G) {\n\t\t\tprintf(\"hugepage_sz not equal 16G\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tmz = rte_memzone_reserve(\"flag_zone_16G_HINT\", size,\n\t\tSOCKET_ID_ANY, RTE_MEMZONE_16GB|RTE_MEMZONE_SIZE_HINT_ONLY);\n\t\tif (mz == NULL) {\n\t\t\tprintf(\"MEMZONE FLAG 16GB\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tif (mz->hugepage_sz != RTE_PGSIZE_16G) {\n\t\t\tprintf(\"hugepage_sz not equal 16G\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Check if 1GB huge pages are unavailable, that function fails\n\t\t * unless HINT flag is indicated\n\t\t */\n\t\tif (!hugepage_16MB_avail) {\n\t\t\tmz = rte_memzone_reserve(\"flag_zone_16M_HINT\", size,\n\t\t\t\tSOCKET_ID_ANY,\n\t\t\t\tRTE_MEMZONE_16MB|RTE_MEMZONE_SIZE_HINT_ONLY);\n\t\t\tif (mz == NULL) {\n\t\t\t\tprintf(\"MEMZONE FLAG 16MB & HINT\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tif (mz->hugepage_sz != RTE_PGSIZE_16G) {\n\t\t\t\tprintf(\"hugepage_sz not equal 16G\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tmz = rte_memzone_reserve(\"flag_zone_16M\", size,\n\t\t\t\tSOCKET_ID_ANY, RTE_MEMZONE_16MB);\n\t\t\tif (mz != NULL) {\n\t\t\t\tprintf(\"MEMZONE FLAG 16MB\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\n\t\tif (hugepage_16MB_avail && hugepage_16GB_avail) {\n\t\t\tmz = rte_memzone_reserve(\"flag_zone_16M_HINT\", size,\n\t\t\t\tSOCKET_ID_ANY,\n\t\t\t\tRTE_MEMZONE_16MB|RTE_MEMZONE_16GB);\n\t\t\tif (mz != NULL) {\n\t\t\t\tprintf(\"BOTH SIZES SET\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\n\n/* Find the heap with the greatest free block size */\nstatic size_t\nfind_max_block_free_size(const unsigned _align)\n{\n\tstruct rte_malloc_socket_stats stats;\n\tunsigned i, align = _align;\n\tsize_t len = 0;\n\n\tfor (i = 0; i < RTE_MAX_NUMA_NODES; i++) {\n\t\trte_malloc_get_socket_stats(i, &stats);\n\t\tif (stats.greatest_free_size > len)\n\t\t\tlen = stats.greatest_free_size;\n\t}\n\n\tif (align < RTE_CACHE_LINE_SIZE)\n\t\talign = RTE_CACHE_LINE_ROUNDUP(align+1);\n\n\tif (len <= MALLOC_ELEM_OVERHEAD + align)\n\t\treturn 0;\n\n\treturn len - MALLOC_ELEM_OVERHEAD - align;\n}\n\nstatic int\ntest_memzone_reserve_max(void)\n{\n\tconst struct rte_memzone *mz;\n\tsize_t maxlen;\n\n\tmaxlen = find_max_block_free_size(0);\n\n\tif (maxlen == 0) {\n\t\tprintf(\"There is no space left!\\n\");\n\t\treturn 0;\n\t}\n\n\tmz = rte_memzone_reserve(\"max_zone\", 0, SOCKET_ID_ANY, 0);\n\tif (mz == NULL){\n\t\tprintf(\"Failed to reserve a big chunk of memory - %s\\n\",\n\t\t\t\trte_strerror(rte_errno));\n\t\trte_dump_physmem_layout(stdout);\n\t\trte_memzone_dump(stdout);\n\t\treturn -1;\n\t}\n\n\tif (mz->len != maxlen) {\n\t\tprintf(\"Memzone reserve with 0 size did not return bigest block\\n\");\n\t\tprintf(\"Expected size = %zu, actual size = %zu\\n\", maxlen, mz->len);\n\t\trte_dump_physmem_layout(stdout);\n\t\trte_memzone_dump(stdout);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic int\ntest_memzone_reserve_max_aligned(void)\n{\n\tconst struct rte_memzone *mz;\n\tsize_t maxlen = 0;\n\n\t/* random alignment */\n\trte_srand((unsigned)rte_rdtsc());\n\tconst unsigned align = 1 << ((rte_rand() % 8) + 5); /* from 128 up to 4k alignment */\n\n\tmaxlen = find_max_block_free_size(align);\n\n\tif (maxlen == 0) {\n\t\tprintf(\"There is no space left for biggest %u-aligned memzone!\\n\", align);\n\t\treturn 0;\n\t}\n\n\tmz = rte_memzone_reserve_aligned(\"max_zone_aligned\", 0,\n\t\t\tSOCKET_ID_ANY, 0, align);\n\tif (mz == NULL){\n\t\tprintf(\"Failed to reserve a big chunk of memory - %s\\n\",\n\t\t\t\trte_strerror(rte_errno));\n\t\trte_dump_physmem_layout(stdout);\n\t\trte_memzone_dump(stdout);\n\t\treturn -1;\n\t}\n\n\tif (mz->len != maxlen) {\n\t\tprintf(\"Memzone reserve with 0 size and alignment %u did not return\"\n\t\t\t\t\" bigest block\\n\", align);\n\t\tprintf(\"Expected size = %zu, actual size = %zu\\n\",\n\t\t\t\tmaxlen, mz->len);\n\t\trte_dump_physmem_layout(stdout);\n\t\trte_memzone_dump(stdout);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic int\ntest_memzone_aligned(void)\n{\n\tconst struct rte_memzone *memzone_aligned_32;\n\tconst struct rte_memzone *memzone_aligned_128;\n\tconst struct rte_memzone *memzone_aligned_256;\n\tconst struct rte_memzone *memzone_aligned_512;\n\tconst struct rte_memzone *memzone_aligned_1024;\n\n\t/* memzone that should automatically be adjusted to align on 64 bytes */\n\tmemzone_aligned_32 = rte_memzone_reserve_aligned(\"aligned_32\", 100,\n\t\t\t\tSOCKET_ID_ANY, 0, 32);\n\n\t/* memzone that is supposed to be aligned on a 128 byte boundary */\n\tmemzone_aligned_128 = rte_memzone_reserve_aligned(\"aligned_128\", 100,\n\t\t\t\tSOCKET_ID_ANY, 0, 128);\n\n\t/* memzone that is supposed to be aligned on a 256 byte boundary */\n\tmemzone_aligned_256 = rte_memzone_reserve_aligned(\"aligned_256\", 100,\n\t\t\t\tSOCKET_ID_ANY, 0, 256);\n\n\t/* memzone that is supposed to be aligned on a 512 byte boundary */\n\tmemzone_aligned_512 = rte_memzone_reserve_aligned(\"aligned_512\", 100,\n\t\t\t\tSOCKET_ID_ANY, 0, 512);\n\n\t/* memzone that is supposed to be aligned on a 1024 byte boundary */\n\tmemzone_aligned_1024 = rte_memzone_reserve_aligned(\"aligned_1024\", 100,\n\t\t\t\tSOCKET_ID_ANY, 0, 1024);\n\n\tprintf(\"check alignments and lengths\\n\");\n\tif (memzone_aligned_32 == NULL) {\n\t\tprintf(\"Unable to reserve 64-byte aligned memzone!\\n\");\n\t\treturn -1;\n\t}\n\tif ((memzone_aligned_32->phys_addr & RTE_CACHE_LINE_MASK) != 0)\n\t\treturn -1;\n\tif (((uintptr_t) memzone_aligned_32->addr & RTE_CACHE_LINE_MASK) != 0)\n\t\treturn -1;\n\tif ((memzone_aligned_32->len & RTE_CACHE_LINE_MASK) != 0)\n\t\treturn -1;\n\n\tif (memzone_aligned_128 == NULL) {\n\t\tprintf(\"Unable to reserve 128-byte aligned memzone!\\n\");\n\t\treturn -1;\n\t}\n\tif ((memzone_aligned_128->phys_addr & 127) != 0)\n\t\treturn -1;\n\tif (((uintptr_t) memzone_aligned_128->addr & 127) != 0)\n\t\treturn -1;\n\tif ((memzone_aligned_128->len & RTE_CACHE_LINE_MASK) != 0)\n\t\treturn -1;\n\n\tif (memzone_aligned_256 == NULL) {\n\t\tprintf(\"Unable to reserve 256-byte aligned memzone!\\n\");\n\t\treturn -1;\n\t}\n\tif ((memzone_aligned_256->phys_addr & 255) != 0)\n\t\treturn -1;\n\tif (((uintptr_t) memzone_aligned_256->addr & 255) != 0)\n\t\treturn -1;\n\tif ((memzone_aligned_256->len & RTE_CACHE_LINE_MASK) != 0)\n\t\treturn -1;\n\n\tif (memzone_aligned_512 == NULL) {\n\t\tprintf(\"Unable to reserve 512-byte aligned memzone!\\n\");\n\t\treturn -1;\n\t}\n\tif ((memzone_aligned_512->phys_addr & 511) != 0)\n\t\treturn -1;\n\tif (((uintptr_t) memzone_aligned_512->addr & 511) != 0)\n\t\treturn -1;\n\tif ((memzone_aligned_512->len & RTE_CACHE_LINE_MASK) != 0)\n\t\treturn -1;\n\n\tif (memzone_aligned_1024 == NULL) {\n\t\tprintf(\"Unable to reserve 1024-byte aligned memzone!\\n\");\n\t\treturn -1;\n\t}\n\tif ((memzone_aligned_1024->phys_addr & 1023) != 0)\n\t\treturn -1;\n\tif (((uintptr_t) memzone_aligned_1024->addr & 1023) != 0)\n\t\treturn -1;\n\tif ((memzone_aligned_1024->len & RTE_CACHE_LINE_MASK) != 0)\n\t\treturn -1;\n\n\t/* check that zones don't overlap */\n\tprintf(\"check overlapping\\n\");\n\tif (is_memory_overlap(memzone_aligned_32->phys_addr, memzone_aligned_32->len,\n\t\t\t\t\tmemzone_aligned_128->phys_addr, memzone_aligned_128->len))\n\t\treturn -1;\n\tif (is_memory_overlap(memzone_aligned_32->phys_addr, memzone_aligned_32->len,\n\t\t\t\t\tmemzone_aligned_256->phys_addr, memzone_aligned_256->len))\n\t\treturn -1;\n\tif (is_memory_overlap(memzone_aligned_32->phys_addr, memzone_aligned_32->len,\n\t\t\t\t\tmemzone_aligned_512->phys_addr, memzone_aligned_512->len))\n\t\treturn -1;\n\tif (is_memory_overlap(memzone_aligned_32->phys_addr, memzone_aligned_32->len,\n\t\t\t\t\tmemzone_aligned_1024->phys_addr, memzone_aligned_1024->len))\n\t\treturn -1;\n\tif (is_memory_overlap(memzone_aligned_128->phys_addr, memzone_aligned_128->len,\n\t\t\t\t\tmemzone_aligned_256->phys_addr, memzone_aligned_256->len))\n\t\treturn -1;\n\tif (is_memory_overlap(memzone_aligned_128->phys_addr, memzone_aligned_128->len,\n\t\t\t\t\tmemzone_aligned_512->phys_addr, memzone_aligned_512->len))\n\t\treturn -1;\n\tif (is_memory_overlap(memzone_aligned_128->phys_addr, memzone_aligned_128->len,\n\t\t\t\t\tmemzone_aligned_1024->phys_addr, memzone_aligned_1024->len))\n\t\treturn -1;\n\tif (is_memory_overlap(memzone_aligned_256->phys_addr, memzone_aligned_256->len,\n\t\t\t\t\tmemzone_aligned_512->phys_addr, memzone_aligned_512->len))\n\t\treturn -1;\n\tif (is_memory_overlap(memzone_aligned_256->phys_addr, memzone_aligned_256->len,\n\t\t\t\t\tmemzone_aligned_1024->phys_addr, memzone_aligned_1024->len))\n\t\treturn -1;\n\tif (is_memory_overlap(memzone_aligned_512->phys_addr, memzone_aligned_512->len,\n\t\t\t\t\tmemzone_aligned_1024->phys_addr, memzone_aligned_1024->len))\n\t\treturn -1;\n\treturn 0;\n}\n\nstatic int\ncheck_memzone_bounded(const char *name, uint32_t len, uint32_t align,\n\tuint32_t bound)\n{\n\tconst struct rte_memzone *mz;\n\tphys_addr_t bmask;\n\n\tbmask = ~((phys_addr_t)bound - 1);\n\n\tif ((mz = rte_memzone_reserve_bounded(name, len, SOCKET_ID_ANY, 0,\n\t\t\talign, bound)) == NULL) {\n\t\tprintf(\"%s(%s): memzone creation failed\\n\",\n\t\t\t__func__, name);\n\t\treturn (-1);\n\t}\n\n\tif ((mz->phys_addr & ((phys_addr_t)align - 1)) != 0) {\n\t\tprintf(\"%s(%s): invalid phys addr alignment\\n\",\n\t\t\t__func__, mz->name);\n\t\treturn (-1);\n\t}\n\n\tif (((uintptr_t) mz->addr & ((uintptr_t)align - 1)) != 0) {\n\t\tprintf(\"%s(%s): invalid virtual addr alignment\\n\",\n\t\t\t__func__, mz->name);\n\t\treturn (-1);\n\t}\n\n\tif ((mz->len & RTE_CACHE_LINE_MASK) != 0 || mz->len < len ||\n\t\t\tmz->len < RTE_CACHE_LINE_SIZE) {\n\t\tprintf(\"%s(%s): invalid length\\n\",\n\t\t\t__func__, mz->name);\n\t\treturn (-1);\n\t}\n\n\tif ((mz->phys_addr & bmask) !=\n\t\t\t((mz->phys_addr + mz->len - 1) & bmask)) {\n\t\tprintf(\"%s(%s): invalid memzone boundary %u crossed\\n\",\n\t\t\t__func__, mz->name, bound);\n\t\treturn (-1);\n\t}\n\n\treturn (0);\n}\n\nstatic int\ntest_memzone_bounded(void)\n{\n\tconst struct rte_memzone *memzone_err;\n\tconst char *name;\n\tint rc;\n\n\t/* should fail as boundary is not power of two */\n\tname = \"bounded_error_31\";\n\tif ((memzone_err = rte_memzone_reserve_bounded(name,\n\t\t\t100, SOCKET_ID_ANY, 0, 32, UINT32_MAX)) != NULL) {\n\t\tprintf(\"%s(%s)created a memzone with invalid boundary \"\n\t\t\t\"conditions\\n\", __func__, memzone_err->name);\n\t\treturn (-1);\n\t}\n\n\t/* should fail as len is greater then boundary */\n\tname = \"bounded_error_32\";\n\tif ((memzone_err = rte_memzone_reserve_bounded(name,\n\t\t\t100, SOCKET_ID_ANY, 0, 32, 32)) != NULL) {\n\t\tprintf(\"%s(%s)created a memzone with invalid boundary \"\n\t\t\t\"conditions\\n\", __func__, memzone_err->name);\n\t\treturn (-1);\n\t}\n\n\tif ((rc = check_memzone_bounded(\"bounded_128\", 100, 128, 128)) != 0)\n\t\treturn (rc);\n\n\tif ((rc = check_memzone_bounded(\"bounded_256\", 100, 256, 128)) != 0)\n\t\treturn (rc);\n\n\tif ((rc = check_memzone_bounded(\"bounded_1K\", 100, 64, 1024)) != 0)\n\t\treturn (rc);\n\n\tif ((rc = check_memzone_bounded(\"bounded_1K_MAX\", 0, 64, 1024)) != 0)\n\t\treturn (rc);\n\n\treturn 0;\n}\n\nstatic int\ntest_memzone_free(void)\n{\n\tconst struct rte_memzone *mz[RTE_MAX_MEMZONE];\n\tint i;\n\tchar name[20];\n\n\tmz[0] = rte_memzone_reserve(\"tempzone0\", 2000, SOCKET_ID_ANY, 0);\n\tmz[1] = rte_memzone_reserve(\"tempzone1\", 4000, SOCKET_ID_ANY, 0);\n\n\tif (mz[0] > mz[1])\n\t\treturn -1;\n\tif (!rte_memzone_lookup(\"tempzone0\"))\n\t\treturn -1;\n\tif (!rte_memzone_lookup(\"tempzone1\"))\n\t\treturn -1;\n\n\tif (rte_memzone_free(mz[0])) {\n\t\tprintf(\"Fail memzone free - tempzone0\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_memzone_lookup(\"tempzone0\")) {\n\t\tprintf(\"Found previously free memzone - tempzone0\\n\");\n\t\treturn -1;\n\t}\n\tmz[2] = rte_memzone_reserve(\"tempzone2\", 2000, SOCKET_ID_ANY, 0);\n\n\tif (mz[2] > mz[1]) {\n\t\tprintf(\"tempzone2 should have gotten the free entry from tempzone0\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_memzone_free(mz[2])) {\n\t\tprintf(\"Fail memzone free - tempzone2\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_memzone_lookup(\"tempzone2\")) {\n\t\tprintf(\"Found previously free memzone - tempzone2\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_memzone_free(mz[1])) {\n\t\tprintf(\"Fail memzone free - tempzone1\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_memzone_lookup(\"tempzone1\")) {\n\t\tprintf(\"Found previously free memzone - tempzone1\\n\");\n\t\treturn -1;\n\t}\n\n\ti = 0;\n\tdo {\n\t\tsnprintf(name, sizeof(name), \"tempzone%u\", i);\n\t\tmz[i] = rte_memzone_reserve(name, 1, SOCKET_ID_ANY, 0);\n\t} while (mz[i++] != NULL);\n\n\tif (rte_memzone_free(mz[0])) {\n\t\tprintf(\"Fail memzone free - tempzone0\\n\");\n\t\treturn -1;\n\t}\n\tmz[0] = rte_memzone_reserve(\"tempzone0new\", 0, SOCKET_ID_ANY, 0);\n\n\tif (mz[0] == NULL) {\n\t\tprintf(\"Fail to create memzone - tempzone0new - when MAX memzones were \"\n\t\t\t\t\"created and one was free\\n\");\n\t\treturn -1;\n\t}\n\n\tfor (i = i - 2; i >= 0; i--) {\n\t\tif (rte_memzone_free(mz[i])) {\n\t\t\tprintf(\"Fail memzone free - tempzone%d\\n\", i);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntest_memzone(void)\n{\n\tconst struct rte_memzone *memzone1;\n\tconst struct rte_memzone *memzone2;\n\tconst struct rte_memzone *memzone3;\n\tconst struct rte_memzone *memzone4;\n\tconst struct rte_memzone *mz;\n\n\tmemzone1 = rte_memzone_reserve(\"testzone1\", 100,\n\t\t\t\tSOCKET_ID_ANY, 0);\n\n\tmemzone2 = rte_memzone_reserve(\"testzone2\", 1000,\n\t\t\t\t0, 0);\n\n\tmemzone3 = rte_memzone_reserve(\"testzone3\", 1000,\n\t\t\t\t1, 0);\n\n\tmemzone4 = rte_memzone_reserve(\"testzone4\", 1024,\n\t\t\t\tSOCKET_ID_ANY, 0);\n\n\t/* memzone3 may be NULL if we don't have NUMA */\n\tif (memzone1 == NULL || memzone2 == NULL || memzone4 == NULL)\n\t\treturn -1;\n\n\trte_memzone_dump(stdout);\n\n\t/* check cache-line alignments */\n\tprintf(\"check alignments and lengths\\n\");\n\n\tif ((memzone1->phys_addr & RTE_CACHE_LINE_MASK) != 0)\n\t\treturn -1;\n\tif ((memzone2->phys_addr & RTE_CACHE_LINE_MASK) != 0)\n\t\treturn -1;\n\tif (memzone3 != NULL && (memzone3->phys_addr & RTE_CACHE_LINE_MASK) != 0)\n\t\treturn -1;\n\tif ((memzone1->len & RTE_CACHE_LINE_MASK) != 0 || memzone1->len == 0)\n\t\treturn -1;\n\tif ((memzone2->len & RTE_CACHE_LINE_MASK) != 0 || memzone2->len == 0)\n\t\treturn -1;\n\tif (memzone3 != NULL && ((memzone3->len & RTE_CACHE_LINE_MASK) != 0 ||\n\t\t\tmemzone3->len == 0))\n\t\treturn -1;\n\tif (memzone4->len != 1024)\n\t\treturn -1;\n\n\t/* check that zones don't overlap */\n\tprintf(\"check overlapping\\n\");\n\n\tif (is_memory_overlap(memzone1->phys_addr, memzone1->len,\n\t\t\tmemzone2->phys_addr, memzone2->len))\n\t\treturn -1;\n\tif (memzone3 != NULL &&\n\t\t\tis_memory_overlap(memzone1->phys_addr, memzone1->len,\n\t\t\t\t\tmemzone3->phys_addr, memzone3->len))\n\t\treturn -1;\n\tif (memzone3 != NULL &&\n\t\t\tis_memory_overlap(memzone2->phys_addr, memzone2->len,\n\t\t\t\t\tmemzone3->phys_addr, memzone3->len))\n\t\treturn -1;\n\n\tprintf(\"check socket ID\\n\");\n\n\t/* memzone2 must be on socket id 0 and memzone3 on socket 1 */\n\tif (memzone2->socket_id != 0)\n\t\treturn -1;\n\tif (memzone3 != NULL && memzone3->socket_id != 1)\n\t\treturn -1;\n\n\tprintf(\"test zone lookup\\n\");\n\tmz = rte_memzone_lookup(\"testzone1\");\n\tif (mz != memzone1)\n\t\treturn -1;\n\n\tprintf(\"test duplcate zone name\\n\");\n\tmz = rte_memzone_reserve(\"testzone1\", 100,\n\t\t\tSOCKET_ID_ANY, 0);\n\tif (mz != NULL)\n\t\treturn -1;\n\n\tprintf(\"test free memzone\\n\");\n\tif (test_memzone_free() < 0)\n\t\treturn -1;\n\n\tprintf(\"test reserving memzone with bigger size than the maximum\\n\");\n\tif (test_memzone_reserving_zone_size_bigger_than_the_maximum() < 0)\n\t\treturn -1;\n\n\tprintf(\"test memzone_reserve flags\\n\");\n\tif (test_memzone_reserve_flags() < 0)\n\t\treturn -1;\n\n\tprintf(\"test alignment for memzone_reserve\\n\");\n\tif (test_memzone_aligned() < 0)\n\t\treturn -1;\n\n\tprintf(\"test boundary alignment for memzone_reserve\\n\");\n\tif (test_memzone_bounded() < 0)\n\t\treturn -1;\n\n\tprintf(\"test invalid alignment for memzone_reserve\\n\");\n\tif (test_memzone_invalid_alignment() < 0)\n\t\treturn -1;\n\n\tprintf(\"test reserving the largest size memzone possible\\n\");\n\tif (test_memzone_reserve_max() < 0)\n\t\treturn -1;\n\n\tprintf(\"test reserving the largest size aligned memzone possible\\n\");\n\tif (test_memzone_reserve_max_aligned() < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic struct test_command memzone_cmd = {\n\t.command = \"memzone_autotest\",\n\t.callback = test_memzone,\n};\nREGISTER_TEST_COMMAND(memzone_cmd);\n" }, { "path": "app/test/test_meter.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#include \n#include \n\n#define mlog(format, ...) do{\\\n\t\tprintf(\"Line %d:\",__LINE__);\\\n\t\tprintf(format, ##__VA_ARGS__);\\\n\t\tprintf(\"\\n\");\\\n\t}while(0);\n\n#define melog(format, ...) do{\\\n\t\tprintf(\"Line %d:\",__LINE__);\\\n\t\tprintf(format, ##__VA_ARGS__);\\\n\t\tprintf(\" failed!\\n\");\\\n\t\treturn -1;\\\n\t}while(0);\n\n#define TM_TEST_SRTCM_CIR_DF 46000000\n#define TM_TEST_SRTCM_CBS_DF 2048\n#define TM_TEST_SRTCM_EBS_DF 4096\n\n#define TM_TEST_TRTCM_CIR_DF 46000000\n#define TM_TEST_TRTCM_PIR_DF 69000000\n#define TM_TEST_TRTCM_CBS_DF 2048\n#define TM_TEST_TRTCM_PBS_DF 4096\n\nstatic struct rte_meter_srtcm_params sparams =\n\t\t\t\t{.cir = TM_TEST_SRTCM_CIR_DF,\n\t\t\t\t .cbs = TM_TEST_SRTCM_CBS_DF,\n\t\t\t\t .ebs = TM_TEST_SRTCM_EBS_DF,};\n\nstatic struct\trte_meter_trtcm_params tparams=\n\t\t\t\t{.cir = TM_TEST_TRTCM_CIR_DF,\n\t\t\t\t .pir = TM_TEST_TRTCM_PIR_DF,\n\t\t\t\t .cbs = TM_TEST_TRTCM_CBS_DF,\n\t\t\t\t .pbs = TM_TEST_TRTCM_PBS_DF,};\n\n/**\n * functional test for rte_meter_srtcm_config\n */\nstatic inline int\ntm_test_srtcm_config(void)\n{\n#define SRTCM_CFG_MSG \"srtcm_config\"\n\tstruct rte_meter_srtcm sm;\n\tstruct rte_meter_srtcm_params sparams1;\n\n\t/* invalid parameter test */\n\tif(rte_meter_srtcm_config(NULL, NULL) == 0)\n\t\tmelog(SRTCM_CFG_MSG);\n\tif(rte_meter_srtcm_config(&sm, NULL) == 0)\n\t\tmelog(SRTCM_CFG_MSG);\n\tif(rte_meter_srtcm_config(NULL, &sparams) == 0)\n\t\tmelog(SRTCM_CFG_MSG);\n\n\t/* cbs and ebs can't both be zero */\n\tsparams1 = sparams;\n\tsparams1.cbs = 0;\n\tsparams1.ebs = 0;\n\tif(rte_meter_srtcm_config(&sm, &sparams1) == 0)\n\t\tmelog(SRTCM_CFG_MSG);\n\n\t/* cir should never be 0 */\n\tsparams1 = sparams;\n\tsparams1.cir = 0;\n\tif(rte_meter_srtcm_config(&sm, &sparams1) == 0)\n\t\tmelog(SRTCM_CFG_MSG);\n\n\t/* one of ebs and cbs can be zero, should be successful */\n\tsparams1 = sparams;\n\tsparams1.ebs = 0;\n\tif(rte_meter_srtcm_config(&sm, &sparams1) != 0)\n\t\tmelog(SRTCM_CFG_MSG);\n\n\tsparams1 = sparams;\n\tsparams1.cbs = 0;\n\tif(rte_meter_srtcm_config(&sm, &sparams1) != 0)\n\t\tmelog(SRTCM_CFG_MSG);\n\n\t/* usual parameter, should be successful */\n\tif(rte_meter_srtcm_config(&sm, &sparams) != 0)\n\t\tmelog(SRTCM_CFG_MSG);\n\n\treturn 0;\n\n}\n\n/**\n * functional test for rte_meter_trtcm_config\n */\nstatic inline int\ntm_test_trtcm_config(void)\n{\n\tstruct rte_meter_trtcm tm;\n\tstruct rte_meter_trtcm_params tparams1;\n#define TRTCM_CFG_MSG \"trtcm_config\"\n\n\t/* invalid parameter test */\n\tif(rte_meter_trtcm_config(NULL, NULL) == 0)\n\t\tmelog(TRTCM_CFG_MSG);\n\tif(rte_meter_trtcm_config(&tm, NULL) == 0)\n\t\tmelog(TRTCM_CFG_MSG);\n\tif(rte_meter_trtcm_config(NULL, &tparams) == 0)\n\t\tmelog(TRTCM_CFG_MSG);\n\n\t/* cir, cbs, pir and pbs never be zero */\n\ttparams1 = tparams;\n\ttparams1.cir = 0;\n\tif(rte_meter_trtcm_config(&tm, &tparams1) == 0)\n\t\tmelog(TRTCM_CFG_MSG);\n\n\ttparams1 = tparams;\n\ttparams1.cbs = 0;\n\tif(rte_meter_trtcm_config(&tm, &tparams1) == 0)\n\t\tmelog(TRTCM_CFG_MSG);\n\n\ttparams1 = tparams;\n\ttparams1.pbs = 0;\n\tif(rte_meter_trtcm_config(&tm, &tparams1) == 0)\n\t\tmelog(TRTCM_CFG_MSG);\n\n\ttparams1 = tparams;\n\ttparams1.pir = 0;\n\tif(rte_meter_trtcm_config(&tm, &tparams1) == 0)\n\t\tmelog(TRTCM_CFG_MSG);\n\n\t/* pir should be greater or equal to cir */\n\ttparams1 = tparams;\n\ttparams1.pir = tparams1.cir - 1;\n\tif(rte_meter_trtcm_config(&tm, &tparams1) == 0)\n\t\tmelog(TRTCM_CFG_MSG\" pir < cir test\");\n\n\t/* usual parameter, should be successful */\n\tif(rte_meter_trtcm_config(&tm, &tparams) != 0)\n\t\tmelog(TRTCM_CFG_MSG);\n\n\treturn 0;\n}\n\n/**\n * functional test for rte_meter_srtcm_color_blind_check\n */\nstatic inline int\ntm_test_srtcm_color_blind_check(void)\n{\n#define SRTCM_BLIND_CHECK_MSG \"srtcm_blind_check\"\n\tstruct rte_meter_srtcm sm;\n\tuint64_t time;\n\tuint64_t hz = rte_get_tsc_hz();\n\n\t/* Test green */\n\tif(rte_meter_srtcm_config(&sm, &sparams) != 0)\n\t\tmelog(SRTCM_BLIND_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_srtcm_color_blind_check(\n\t\t&sm, time, TM_TEST_SRTCM_CBS_DF - 1)\n\t\t!= e_RTE_METER_GREEN)\n\t\tmelog(SRTCM_BLIND_CHECK_MSG\" GREEN\");\n\n\t/* Test yellow */\n\tif(rte_meter_srtcm_config(&sm, &sparams) != 0)\n\t\tmelog(SRTCM_BLIND_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_srtcm_color_blind_check(\n\t\t&sm, time, TM_TEST_SRTCM_CBS_DF + 1)\n\t\t!= e_RTE_METER_YELLOW)\n\t\tmelog(SRTCM_BLIND_CHECK_MSG\" YELLOW\");\n\n\tif(rte_meter_srtcm_config(&sm, &sparams) != 0)\n\t\tmelog(SRTCM_BLIND_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_srtcm_color_blind_check(\n\t\t&sm, time, (uint32_t)sm.ebs - 1) != e_RTE_METER_YELLOW)\n\t\tmelog(SRTCM_BLIND_CHECK_MSG\" YELLOW\");\n\n\t/* Test red */\n\tif(rte_meter_srtcm_config(&sm, &sparams) != 0)\n\t\tmelog(SRTCM_BLIND_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_srtcm_color_blind_check(\n\t\t&sm, time, TM_TEST_SRTCM_EBS_DF + 1)\n\t\t!= e_RTE_METER_RED)\n\t\tmelog(SRTCM_BLIND_CHECK_MSG\" RED\");\n\n\treturn 0;\n\n}\n\n/**\n * functional test for rte_meter_trtcm_color_blind_check\n */\nstatic inline int\ntm_test_trtcm_color_blind_check(void)\n{\n#define TRTCM_BLIND_CHECK_MSG \"trtcm_blind_check\"\n\n\tuint64_t time;\n\tstruct rte_meter_trtcm tm;\n\tuint64_t hz = rte_get_tsc_hz();\n\n\t/* Test green */\n\tif(rte_meter_trtcm_config(&tm, &tparams) != 0)\n\t\tmelog(TRTCM_BLIND_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_trtcm_color_blind_check(\n\t\t&tm, time, TM_TEST_TRTCM_CBS_DF - 1)\n\t\t!= e_RTE_METER_GREEN)\n\t\tmelog(TRTCM_BLIND_CHECK_MSG\" GREEN\");\n\n\t/* Test yellow */\n\tif(rte_meter_trtcm_config(&tm, &tparams) != 0)\n\t\tmelog(TRTCM_BLIND_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_trtcm_color_blind_check(\n\t\t&tm, time, TM_TEST_TRTCM_CBS_DF + 1)\n\t\t!= e_RTE_METER_YELLOW)\n\t\tmelog(TRTCM_BLIND_CHECK_MSG\" YELLOW\");\n\n\tif(rte_meter_trtcm_config(&tm, &tparams) != 0)\n\t\tmelog(TRTCM_BLIND_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_trtcm_color_blind_check(\n\t\t&tm, time, TM_TEST_TRTCM_PBS_DF - 1)\n\t\t!= e_RTE_METER_YELLOW)\n\t\tmelog(TRTCM_BLIND_CHECK_MSG\" YELLOW\");\n\n\t/* Test red */\n\tif(rte_meter_trtcm_config(&tm, &tparams) != 0)\n\t\tmelog(TRTCM_BLIND_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_trtcm_color_blind_check(\n\t\t&tm, time, TM_TEST_TRTCM_PBS_DF + 1)\n\t\t!= e_RTE_METER_RED)\n\t\tmelog(TRTCM_BLIND_CHECK_MSG\" RED\");\n\n\treturn 0;\n}\n\n\n/**\n * @in[4] : the flags packets carries.\n * @in[4] : the flags function expect to return.\n * It will do blind check at the time of 1 second from beginning.\n * At the time, it will use packets length of cbs -1, cbs + 1,\n * ebs -1 and ebs +1 with flag in[0], in[1], in[2] and in[3] to do\n * aware check, expect flag out[0], out[1], out[2] and out[3]\n */\n\nstatic inline int\ntm_test_srtcm_aware_check\n(enum rte_meter_color in[4], enum rte_meter_color out[4])\n{\n#define SRTCM_AWARE_CHECK_MSG \"srtcm_aware_check\"\n\tstruct rte_meter_srtcm sm;\n\tuint64_t time;\n\tuint64_t hz = rte_get_tsc_hz();\n\n\tif(rte_meter_srtcm_config(&sm, &sparams) != 0)\n\t\tmelog(SRTCM_AWARE_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_srtcm_color_aware_check(\n\t\t&sm, time, TM_TEST_SRTCM_CBS_DF - 1, in[0]) != out[0])\n\t\tmelog(SRTCM_AWARE_CHECK_MSG\" %u:%u\", in[0], out[0]);\n\n\tif(rte_meter_srtcm_config(&sm, &sparams) != 0)\n\t\tmelog(SRTCM_AWARE_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_srtcm_color_aware_check(\n\t\t&sm, time, TM_TEST_SRTCM_CBS_DF + 1, in[1]) != out[1])\n\t\tmelog(SRTCM_AWARE_CHECK_MSG\" %u:%u\", in[1], out[1]);\n\n\tif(rte_meter_srtcm_config(&sm, &sparams) != 0)\n\t\tmelog(SRTCM_AWARE_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_srtcm_color_aware_check(\n\t\t&sm, time, TM_TEST_SRTCM_EBS_DF - 1, in[2]) != out[2])\n\t\tmelog(SRTCM_AWARE_CHECK_MSG\" %u:%u\", in[2], out[2]);\n\n\tif(rte_meter_srtcm_config(&sm, &sparams) != 0)\n\t\tmelog(SRTCM_AWARE_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_srtcm_color_aware_check(\n\t\t&sm, time, TM_TEST_SRTCM_EBS_DF + 1, in[3]) != out[3])\n\t\tmelog(SRTCM_AWARE_CHECK_MSG\" %u:%u\", in[3], out[3]);\n\n\treturn 0;\n}\n\n\n/**\n * functional test for rte_meter_srtcm_color_aware_check\n */\nstatic inline int\ntm_test_srtcm_color_aware_check(void)\n{\n\tenum rte_meter_color in[4], out[4];\n\n\t/**\n\t * test 4 points that will produce green, yellow, yellow, red flag\n\t * if using blind check\n\t */\n\n\t/* previouly have a green, test points should keep unchanged */\n\tin[0] = in[1] = in[2] = in[3] = e_RTE_METER_GREEN;\n\tout[0] = e_RTE_METER_GREEN;\n\tout[1] = e_RTE_METER_YELLOW;\n\tout[2] = e_RTE_METER_YELLOW;\n\tout[3] = e_RTE_METER_RED;\n\tif(tm_test_srtcm_aware_check(in, out) != 0)\n\t\treturn -1;\n\n\t/**\n\t * previously have a yellow, green & yellow = yellow\n\t * yellow & red = red\n\t */\n\tin[0] = in[1] = in[2] = in[3] = e_RTE_METER_YELLOW;\n\tout[0] = e_RTE_METER_YELLOW;\n\tout[1] = e_RTE_METER_YELLOW;\n\tout[2] = e_RTE_METER_YELLOW;\n\tout[3] = e_RTE_METER_RED;\n\tif(tm_test_srtcm_aware_check(in, out) != 0)\n\t\treturn -1;\n\n\t/**\n\t * previously have a red, red & green = red\n\t * red & yellow = red\n\t */\n\tin[0] = in[1] = in[2] = in[3] = e_RTE_METER_RED;\n\tout[0] = e_RTE_METER_RED;\n\tout[1] = e_RTE_METER_RED;\n\tout[2] = e_RTE_METER_RED;\n\tout[3] = e_RTE_METER_RED;\n\tif(tm_test_srtcm_aware_check(in, out) != 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * @in[4] : the flags packets carries.\n * @in[4] : the flags function expect to return.\n * It will do blind check at the time of 1 second from beginning.\n * At the time, it will use packets length of cbs -1, cbs + 1,\n * ebs -1 and ebs +1 with flag in[0], in[1], in[2] and in[3] to do\n * aware check, expect flag out[0], out[1], out[2] and out[3]\n */\nstatic inline int\ntm_test_trtcm_aware_check\n(enum rte_meter_color in[4], enum rte_meter_color out[4])\n{\n#define TRTCM_AWARE_CHECK_MSG \"trtcm_aware_check\"\n\tstruct rte_meter_trtcm tm;\n\tuint64_t time;\n\tuint64_t hz = rte_get_tsc_hz();\n\n\tif(rte_meter_trtcm_config(&tm, &tparams) != 0)\n\t\tmelog(TRTCM_AWARE_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_trtcm_color_aware_check(\n\t\t&tm, time, TM_TEST_TRTCM_CBS_DF - 1, in[0]) != out[0])\n\t\tmelog(TRTCM_AWARE_CHECK_MSG\" %u:%u\", in[0], out[0]);\n\n\tif(rte_meter_trtcm_config(&tm, &tparams) != 0)\n\t\tmelog(TRTCM_AWARE_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_trtcm_color_aware_check(\n\t\t&tm, time, TM_TEST_TRTCM_CBS_DF + 1, in[1]) != out[1])\n\t\tmelog(TRTCM_AWARE_CHECK_MSG\" %u:%u\", in[1], out[1]);\n\n\tif(rte_meter_trtcm_config(&tm, &tparams) != 0)\n\t\tmelog(TRTCM_AWARE_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_trtcm_color_aware_check(\n\t\t&tm, time, TM_TEST_TRTCM_PBS_DF - 1, in[2]) != out[2])\n\t\tmelog(TRTCM_AWARE_CHECK_MSG\" %u:%u\", in[2], out[2]);\n\n\tif(rte_meter_trtcm_config(&tm, &tparams) != 0)\n\t\tmelog(TRTCM_AWARE_CHECK_MSG);\n\ttime = rte_get_tsc_cycles() + hz;\n\tif(rte_meter_trtcm_color_aware_check(\n\t\t&tm, time, TM_TEST_TRTCM_PBS_DF + 1, in[3]) != out[3])\n\t\tmelog(TRTCM_AWARE_CHECK_MSG\" %u:%u\", in[3], out[3]);\n\n\treturn 0;\n}\n\n\n/**\n * functional test for rte_meter_trtcm_color_aware_check\n */\n\nstatic inline int\ntm_test_trtcm_color_aware_check(void)\n{\n\tenum rte_meter_color in[4], out[4];\n\t/**\n\t * test 4 points that will produce green, yellow, yellow, red flag\n\t * if using blind check\n\t */\n\n\t/* previouly have a green, test points should keep unchanged */\n\tin[0] = in[1] = in[2] = in[3] = e_RTE_METER_GREEN;\n\tout[0] = e_RTE_METER_GREEN;\n\tout[1] = e_RTE_METER_YELLOW;\n\tout[2] = e_RTE_METER_YELLOW;\n\tout[3] = e_RTE_METER_RED;\n\tif(tm_test_trtcm_aware_check(in, out) != 0)\n\t\treturn -1;\n\n\tin[0] = in[1] = in[2] = in[3] = e_RTE_METER_YELLOW;\n\tout[0] = e_RTE_METER_YELLOW;\n\tout[1] = e_RTE_METER_YELLOW;\n\tout[2] = e_RTE_METER_YELLOW;\n\tout[3] = e_RTE_METER_RED;\n\tif(tm_test_trtcm_aware_check(in, out) != 0)\n\t\treturn -1;\n\n\tin[0] = in[1] = in[2] = in[3] = e_RTE_METER_RED;\n\tout[0] = e_RTE_METER_RED;\n\tout[1] = e_RTE_METER_RED;\n\tout[2] = e_RTE_METER_RED;\n\tout[3] = e_RTE_METER_RED;\n\tif(tm_test_trtcm_aware_check(in, out) != 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * test main entrance for library meter\n */\nstatic int\ntest_meter(void)\n{\n\tif(tm_test_srtcm_config() != 0 )\n\t\treturn -1;\n\n\tif(tm_test_trtcm_config() != 0 )\n\t\treturn -1;\n\n\tif(tm_test_srtcm_color_blind_check() != 0)\n\t\treturn -1;\n\n\tif(tm_test_trtcm_color_blind_check()!= 0)\n\t\treturn -1;\n\n\tif(tm_test_srtcm_color_aware_check()!= 0)\n\t\treturn -1;\n\n\tif(tm_test_trtcm_color_aware_check()!= 0)\n\t\treturn -1;\n\n\treturn 0;\n\n}\n\nstatic struct test_command meter_cmd = {\n\t.command = \"meter_autotest\",\n\t.callback = test_meter,\n};\nREGISTER_TEST_COMMAND(meter_cmd);\n" }, { "path": "app/test/test_mp_secondary.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \"test.h\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#ifdef RTE_LIBRTE_HASH\n#include \n#include \n#endif /* RTE_LIBRTE_HASH */\n\n#ifdef RTE_LIBRTE_LPM\n#include \n#endif /* RTE_LIBRTE_LPM */\n\n#include \n\n#include \"process.h\"\n\n#define launch_proc(ARGV) process_dup(ARGV, \\\n\t\tsizeof(ARGV)/(sizeof(ARGV[0])), __func__)\n\n#ifdef RTE_EXEC_ENV_LINUXAPP\nstatic char*\nget_current_prefix(char * prefix, int size)\n{\n\tchar path[PATH_MAX] = {0};\n\tchar buf[PATH_MAX] = {0};\n\n\t/* get file for config (fd is always 3) */\n\tsnprintf(path, sizeof(path), \"/proc/self/fd/%d\", 3);\n\n\t/* return NULL on error */\n\tif (readlink(path, buf, sizeof(buf)) == -1)\n\t\treturn NULL;\n\n\t/* get the basename */\n\tsnprintf(buf, sizeof(buf), \"%s\", basename(buf));\n\n\t/* copy string all the way from second char up to start of _config */\n\tsnprintf(prefix, size, \"%.*s\",\n\t\t\t(int)(strnlen(buf, sizeof(buf)) - sizeof(\"_config\")),\n\t\t\t&buf[1]);\n\n\treturn prefix;\n}\n#endif\n\n/*\n * This function is called in the primary i.e. main test, to spawn off secondary\n * processes to run actual mp tests. Uses fork() and exec pair\n */\nstatic int\nrun_secondary_instances(void)\n{\n\tint ret = 0;\n\tchar coremask[10];\n\n#ifdef RTE_EXEC_ENV_LINUXAPP\n\tchar tmp[PATH_MAX] = {0};\n\tchar prefix[PATH_MAX] = {0};\n\n\tget_current_prefix(tmp, sizeof(tmp));\n\n\tsnprintf(prefix, sizeof(prefix), \"--file-prefix=%s\", tmp);\n#else\n\tconst char *prefix = \"\";\n#endif\n\n\t/* good case, using secondary */\n\tconst char *argv1[] = {\n\t\t\tprgname, \"-c\", coremask, \"--proc-type=secondary\",\n\t\t\tprefix\n\t};\n\t/* good case, using auto */\n\tconst char *argv2[] = {\n\t\t\tprgname, \"-c\", coremask, \"--proc-type=auto\",\n\t\t\tprefix\n\t};\n\t/* bad case, using invalid type */\n\tconst char *argv3[] = {\n\t\t\tprgname, \"-c\", coremask, \"--proc-type=ERROR\",\n\t\t\tprefix\n\t};\n#ifdef RTE_EXEC_ENV_LINUXAPP\n\t/* bad case, using invalid file prefix */\n\tconst char *argv4[] = {\n\t\t\tprgname, \"-c\", coremask, \"--proc-type=secondary\",\n\t\t\t\t\t\"--file-prefix=ERROR\"\n\t};\n#endif\n\n\tsnprintf(coremask, sizeof(coremask), \"%x\", \\\n\t\t\t(1 << rte_get_master_lcore()));\n\n\tret |= launch_proc(argv1);\n\tret |= launch_proc(argv2);\n\n\tret |= !(launch_proc(argv3));\n#ifdef RTE_EXEC_ENV_LINUXAPP\n\tret |= !(launch_proc(argv4));\n#endif\n\n\treturn ret;\n}\n\n/*\n * This function is run in the secondary instance to test that creation of\n * objects fails in a secondary\n */\nstatic int\nrun_object_creation_tests(void)\n{\n\tconst unsigned flags = 0;\n\tconst unsigned size = 1024;\n\tconst unsigned elt_size = 64;\n\tconst unsigned cache_size = 64;\n\tconst unsigned priv_data_size = 32;\n\n\tprintf(\"### Testing object creation - expect lots of mz reserve errors!\\n\");\n\n\trte_errno = 0;\n\tif ((rte_memzone_reserve(\"test_mz\", size, rte_socket_id(),\n\t\t\t\t flags) == NULL) &&\n\t (rte_memzone_lookup(\"test_mz\") == NULL)) {\n\t\tprintf(\"Error: unexpected return value from rte_memzone_reserve\\n\");\n\t\treturn -1;\n\t}\n\tprintf(\"# Checked rte_memzone_reserve() OK\\n\");\n\n\trte_errno = 0;\n\tif ((rte_ring_create(\n\t\t \"test_ring\", size, rte_socket_id(), flags) == NULL) &&\n\t\t (rte_ring_lookup(\"test_ring\") == NULL)){\n\t\tprintf(\"Error: unexpected return value from rte_ring_create()\\n\");\n\t\treturn -1;\n\t}\n\tprintf(\"# Checked rte_ring_create() OK\\n\");\n\n\trte_errno = 0;\n\tif ((rte_mempool_create(\"test_mp\", size, elt_size, cache_size,\n\t\t\t\tpriv_data_size, NULL, NULL, NULL, NULL,\n\t\t\t\trte_socket_id(), flags) == NULL) &&\n\t (rte_mempool_lookup(\"test_mp\") == NULL)){\n\t\tprintf(\"Error: unexpected return value from rte_mempool_create()\\n\");\n\t\treturn -1;\n\t}\n\tprintf(\"# Checked rte_mempool_create() OK\\n\");\n\n#ifdef RTE_LIBRTE_HASH\n\tconst struct rte_hash_parameters hash_params = { .name = \"test_mp_hash\" };\n\trte_errno=0;\n\tif ((rte_hash_create(&hash_params) != NULL) &&\n\t (rte_hash_find_existing(hash_params.name) == NULL)){\n\t\tprintf(\"Error: unexpected return value from rte_hash_create()\\n\");\n\t\treturn -1;\n\t}\n\tprintf(\"# Checked rte_hash_create() OK\\n\");\n\n\tconst struct rte_fbk_hash_params fbk_params = { .name = \"test_fbk_mp_hash\" };\n\trte_errno=0;\n\tif ((rte_fbk_hash_create(&fbk_params) != NULL) &&\n\t (rte_fbk_hash_find_existing(fbk_params.name) == NULL)){\n\t\tprintf(\"Error: unexpected return value from rte_fbk_hash_create()\\n\");\n\t\treturn -1;\n\t}\n\tprintf(\"# Checked rte_fbk_hash_create() OK\\n\");\n#endif\n\n#ifdef RTE_LIBRTE_LPM\n\trte_errno=0;\n\tif ((rte_lpm_create(\"test_lpm\", size, rte_socket_id(), 0) != NULL) &&\n\t (rte_lpm_find_existing(\"test_lpm\") == NULL)){\n\t\tprintf(\"Error: unexpected return value from rte_lpm_create()\\n\");\n\t\treturn -1;\n\t}\n\tprintf(\"# Checked rte_lpm_create() OK\\n\");\n#endif\n\n\t/* Run a test_pci call */\n\tif (test_pci() != 0) {\n\t\tprintf(\"PCI scan failed in secondary\\n\");\n\t\tif (getuid() == 0) /* pci scans can fail as non-root */\n\t\t\treturn -1;\n\t} else\n\t\tprintf(\"PCI scan succeeded in secondary\\n\");\n\n\treturn 0;\n}\n\n/* if called in a primary process, just spawns off a secondary process to\n * run validation tests - which brings us right back here again...\n * if called in a secondary process, this runs a series of API tests to check\n * how things run in a secondary instance.\n */\nint\ntest_mp_secondary(void)\n{\n\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n\t\tif (!test_pci_run) {\n\t\t\tprintf(\"=== Running pre-requisite test of test_pci\\n\");\n\t\t\ttest_pci();\n\t\t\tprintf(\"=== Requisite test done\\n\");\n\t\t}\n\t\treturn run_secondary_instances();\n\t}\n\n\tprintf(\"IN SECONDARY PROCESS\\n\");\n\n\treturn run_object_creation_tests();\n}\n\nstatic struct test_command multiprocess_cmd = {\n\t.command = \"multiprocess_autotest\",\n\t.callback = test_mp_secondary,\n};\nREGISTER_TEST_COMMAND(multiprocess_cmd);\n" }, { "path": "app/test/test_pci.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n/* Generic maximum number of drivers to have room to allocate all drivers */\n#define NUM_MAX_DRIVERS 256\n\n/*\n * PCI test\n * ========\n *\n * - Register a driver with a ``devinit()`` function.\n *\n * - Dump all PCI devices.\n *\n * - Check that the ``devinit()`` function is called at least once.\n */\n\nint test_pci_run = 0; /* value checked by the multiprocess test */\nstatic unsigned pci_dev_count;\n\nstatic int my_driver_init(struct rte_pci_driver *dr,\n\t\t\t struct rte_pci_device *dev);\n\n/* IXGBE NICS */\nstruct rte_pci_id my_driver_id[] = {\n\n#define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \n\n{ .vendor_id = 0, /* sentinel */ },\n};\n\nstruct rte_pci_id my_driver_id2[] = {\n\n/* IGB & EM NICS */\n#define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \n\n{ .vendor_id = 0, /* sentinel */ },\n};\n\nstruct rte_pci_driver my_driver = {\n\t.name = \"test_driver\",\n\t.devinit = my_driver_init,\n\t.id_table = my_driver_id,\n\t.drv_flags = 0,\n};\n\nstruct rte_pci_driver my_driver2 = {\n\t.name = \"test_driver2\",\n\t.devinit = my_driver_init,\n\t.id_table = my_driver_id2,\n\t.drv_flags = 0,\n};\n\nstatic int\nmy_driver_init(__attribute__((unused)) struct rte_pci_driver *dr,\n\t struct rte_pci_device *dev)\n{\n\tprintf(\"My driver init called in %s\\n\", dr->name);\n\tprintf(\"%x:%x:%x.%d\", dev->addr.domain, dev->addr.bus,\n\t dev->addr.devid, dev->addr.function);\n\tprintf(\" - vendor:%x device:%x\\n\", dev->id.vendor_id, dev->id.device_id);\n\n\tpci_dev_count ++;\n\treturn 0;\n}\n\nstatic void\nblacklist_all_devices(void)\n{\n\tstruct rte_pci_device *dev = NULL;\n\tunsigned i = 0;\n\tchar pci_addr_str[16];\n\n\tTAILQ_FOREACH(dev, &pci_device_list, next) {\n\t\tsnprintf(pci_addr_str, sizeof(pci_addr_str), PCI_PRI_FMT,\n\t\t\tdev->addr.domain, dev->addr.bus, dev->addr.devid,\n\t\t\tdev->addr.function);\n\t\tif (rte_eal_devargs_add(RTE_DEVTYPE_BLACKLISTED_PCI,\n\t\t\t\tpci_addr_str) < 0) {\n\t\t\tprintf(\"Error: cannot blacklist <%s>\", pci_addr_str);\n\t\t\tbreak;\n\t\t}\n\t\ti++;\n\t}\n\tprintf(\"%u devices blacklisted\\n\", i);\n}\n\n/* clear devargs list that was modified by the test */\nstatic void free_devargs_list(void)\n{\n\tstruct rte_devargs *devargs;\n\n\twhile (!TAILQ_EMPTY(&devargs_list)) {\n\t\tdevargs = TAILQ_FIRST(&devargs_list);\n\t\tTAILQ_REMOVE(&devargs_list, devargs, next);\n\t\tif (devargs->args)\n\t\t\tfree(devargs->args);\n\t\tfree(devargs);\n\t}\n}\n\nint\ntest_pci(void)\n{\n\tstruct rte_devargs_list save_devargs_list;\n\tstruct rte_pci_driver *dr = NULL;\n\tstruct rte_pci_driver *save_pci_driver_list[NUM_MAX_DRIVERS];\n\tunsigned i, num_drivers = 0;\n\n\tprintf(\"Dump all devices\\n\");\n\trte_eal_pci_dump(stdout);\n\n\t/* Unregister all previous drivers */\n\tTAILQ_FOREACH(dr, &pci_driver_list, next) {\n\t\trte_eal_pci_unregister(dr);\n\t\tsave_pci_driver_list[num_drivers++] = dr;\n\t}\n\n\trte_eal_pci_register(&my_driver);\n\trte_eal_pci_register(&my_driver2);\n\n\tpci_dev_count = 0;\n\tprintf(\"Scan bus\\n\");\n\trte_eal_pci_probe();\n\n\tif (pci_dev_count == 0) {\n\t\tprintf(\"no device detected\\n\");\n\t\treturn -1;\n\t}\n\n\t/* save the real devargs_list */\n\tsave_devargs_list = devargs_list;\n\tTAILQ_INIT(&devargs_list);\n\n\tblacklist_all_devices();\n\n\tpci_dev_count = 0;\n\tprintf(\"Scan bus with all devices blacklisted\\n\");\n\trte_eal_pci_probe();\n\n\tfree_devargs_list();\n\tdevargs_list = save_devargs_list;\n\n\tif (pci_dev_count != 0) {\n\t\tprintf(\"not all devices are blacklisted\\n\");\n\t\treturn -1;\n\t}\n\n\ttest_pci_run = 1;\n\n\trte_eal_pci_unregister(&my_driver);\n\trte_eal_pci_unregister(&my_driver2);\n\n\t/* Restore original driver list */\n\tfor (i = 0; i < num_drivers; i++)\n\t\trte_eal_pci_register(save_pci_driver_list[i]);\n\n\treturn 0;\n}\n\nstatic struct test_command pci_cmd = {\n\t.command = \"pci_autotest\",\n\t.callback = test_pci,\n};\nREGISTER_TEST_COMMAND(pci_cmd);\n" }, { "path": "app/test/test_per_lcore.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n/*\n * Per-lcore variables and lcore launch\n * ====================================\n *\n * - Use ``rte_eal_mp_remote_launch()`` to call ``assign_vars()`` on\n * every available lcore. In this function, a per-lcore variable is\n * assigned to the lcore_id.\n *\n * - Use ``rte_eal_mp_remote_launch()`` to call ``display_vars()`` on\n * every available lcore. The function checks that the variable is\n * correctly set, or returns -1.\n *\n * - If at least one per-core variable was not correct, the test function\n * returns -1.\n */\n\nstatic RTE_DEFINE_PER_LCORE(unsigned, test) = 0x12345678;\n\nstatic int\nassign_vars(__attribute__((unused)) void *arg)\n{\n\tif (RTE_PER_LCORE(test) != 0x12345678)\n\t\treturn -1;\n\tRTE_PER_LCORE(test) = rte_lcore_id();\n\treturn 0;\n}\n\nstatic int\ndisplay_vars(__attribute__((unused)) void *arg)\n{\n\tunsigned lcore_id = rte_lcore_id();\n\tunsigned var = RTE_PER_LCORE(test);\n\tunsigned socket_id = rte_lcore_to_socket_id(lcore_id);\n\n\tprintf(\"on socket %u, on core %u, variable is %u\\n\", socket_id, lcore_id, var);\n\tif (lcore_id != var)\n\t\treturn -1;\n\n\tRTE_PER_LCORE(test) = 0x12345678;\n\treturn 0;\n}\n\nstatic int\ntest_per_lcore_delay(__attribute__((unused)) void *arg)\n{\n\trte_delay_ms(5000);\n\tprintf(\"wait 5000ms on lcore %u\\n\", rte_lcore_id());\n\n\treturn 0;\n}\n\nstatic int\ntest_per_lcore(void)\n{\n\tunsigned lcore_id;\n\tint ret;\n\n\trte_eal_mp_remote_launch(assign_vars, NULL, SKIP_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\trte_eal_mp_remote_launch(display_vars, NULL, SKIP_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\t/* test if it could do remote launch twice at the same time or not */\n\tret = rte_eal_mp_remote_launch(test_per_lcore_delay, NULL, SKIP_MASTER);\n\tif (ret < 0) {\n\t\tprintf(\"It fails to do remote launch but it should able to do\\n\");\n\t\treturn -1;\n\t}\n\t/* it should not be able to launch a lcore which is running */\n\tret = rte_eal_mp_remote_launch(test_per_lcore_delay, NULL, SKIP_MASTER);\n\tif (ret == 0) {\n\t\tprintf(\"It does remote launch successfully but it should not at this time\\n\");\n\t\treturn -1;\n\t}\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic struct test_command per_lcore_cmd = {\n\t.command = \"per_lcore_autotest\",\n\t.callback = test_per_lcore,\n};\nREGISTER_TEST_COMMAND(per_lcore_cmd);\n" }, { "path": "app/test/test_pmd_perf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \"packet_burst_generator.h\"\n#include \"test.h\"\n\n#define NB_ETHPORTS_USED (1)\n#define NB_SOCKETS (2)\n#define MEMPOOL_CACHE_SIZE 250\n#define MAX_PKT_BURST (32)\n#define RTE_TEST_RX_DESC_DEFAULT (128)\n#define RTE_TEST_TX_DESC_DEFAULT (512)\n#define RTE_PORT_ALL (~(uint8_t)0x0)\n\n/* how long test would take at full line rate */\n#define RTE_TEST_DURATION (2)\n\n/*\n * RX and TX Prefetch, Host, and Write-back threshold values should be\n * carefully set for optimal performance. Consult the network\n * controller's datasheet and supporting DPDK documentation for guidance\n * on how these parameters should be set.\n */\n#define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */\n#define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */\n#define RX_WTHRESH 0 /**< Default values of RX write-back threshold reg. */\n\n/*\n * These default values are optimized for use with the Intel(R) 82599 10 GbE\n * Controller and the DPDK ixgbe PMD. Consider using other values for other\n * network controllers and/or network drivers.\n */\n#define TX_PTHRESH 32 /**< Default values of TX prefetch threshold reg. */\n#define TX_HTHRESH 0 /**< Default values of TX host threshold reg. */\n#define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */\n\n#define MAX_TRAFFIC_BURST 2048\n\n#define NB_MBUF RTE_MAX(\t\t\t\t\t\t\\\n\t\t(unsigned)(nb_ports*nb_rx_queue*nb_rxd +\t\t\\\n\t\t\t nb_ports*nb_lcores*MAX_PKT_BURST +\t\t\\\n\t\t\t nb_ports*nb_tx_queue*nb_txd +\t\t\\\n\t\t\t nb_lcores*MEMPOOL_CACHE_SIZE +\t\t\\\n\t\t\t nb_ports*MAX_TRAFFIC_BURST),\t\t\t\\\n\t\t\t(unsigned)8192)\n\n\nstatic struct rte_mempool *mbufpool[NB_SOCKETS];\n/* ethernet addresses of ports */\nstatic struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];\n\nstatic struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.mq_mode = ETH_MQ_RX_NONE,\n\t\t.max_rx_pkt_len = ETHER_MAX_LEN,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.hw_vlan_strip = 0, /**< VLAN strip enabled. */\n\t\t.hw_vlan_extend = 0, /**< Extended VLAN disabled. */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t\t.enable_scatter = 0, /**< scatter rx disabled */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n\t.lpbk_mode = 1, /* enable loopback */\n};\n\nstatic struct rte_eth_rxconf rx_conf = {\n\t.rx_thresh = {\n\t\t.pthresh = RX_PTHRESH,\n\t\t.hthresh = RX_HTHRESH,\n\t\t.wthresh = RX_WTHRESH,\n\t},\n\t.rx_free_thresh = 32,\n};\n\nstatic struct rte_eth_txconf tx_conf = {\n\t.tx_thresh = {\n\t\t.pthresh = TX_PTHRESH,\n\t\t.hthresh = TX_HTHRESH,\n\t\t.wthresh = TX_WTHRESH,\n\t},\n\t.tx_free_thresh = 32, /* Use PMD default values */\n\t.tx_rs_thresh = 32, /* Use PMD default values */\n\t.txq_flags = (ETH_TXQ_FLAGS_NOMULTSEGS |\n\t\t ETH_TXQ_FLAGS_NOVLANOFFL |\n\t\t ETH_TXQ_FLAGS_NOXSUMSCTP |\n\t\t ETH_TXQ_FLAGS_NOXSUMUDP |\n\t\t ETH_TXQ_FLAGS_NOXSUMTCP)\n};\n\nenum {\n\tLCORE_INVALID = 0,\n\tLCORE_AVAIL,\n\tLCORE_USED,\n};\n\nstruct lcore_conf {\n\tuint8_t status;\n\tuint8_t socketid;\n\tuint16_t nb_ports;\n\tuint8_t portlist[RTE_MAX_ETHPORTS];\n} __rte_cache_aligned;\n\nstruct lcore_conf lcore_conf[RTE_MAX_LCORE];\n\nstatic uint64_t link_mbps;\n\nenum {\n\tSC_CONTINUOUS = 0,\n\tSC_BURST_POLL_FIRST,\n\tSC_BURST_XMIT_FIRST,\n};\n\nstatic uint32_t sc_flag;\n\n/* Check the link status of all ports in up to 3s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 30 /* 3s (30 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"Checking link statuses...\\n\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status) {\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\t\tif (link_mbps == 0)\n\t\t\t\t\t\tlink_mbps = link.link_speed;\n\t\t\t\t} else\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1))\n\t\t\tprint_flag = 1;\n\t}\n}\n\nstatic void\nprint_ethaddr(const char *name, const struct ether_addr *eth_addr)\n{\n\tchar buf[ETHER_ADDR_FMT_SIZE];\n\tether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);\n\tprintf(\"%s%s\", name, buf);\n}\n\nstatic int\ninit_traffic(struct rte_mempool *mp,\n\t struct rte_mbuf **pkts_burst, uint32_t burst_size)\n{\n\tstruct ether_hdr pkt_eth_hdr;\n\tstruct ipv4_hdr pkt_ipv4_hdr;\n\tstruct udp_hdr pkt_udp_hdr;\n\tuint32_t pktlen;\n\tstatic uint8_t src_mac[] = { 0x00, 0xFF, 0xAA, 0xFF, 0xAA, 0xFF };\n\tstatic uint8_t dst_mac[] = { 0x00, 0xAA, 0xFF, 0xAA, 0xFF, 0xAA };\n\n\n\tinitialize_eth_header(&pkt_eth_hdr,\n\t\t(struct ether_addr *)src_mac,\n\t\t(struct ether_addr *)dst_mac, ETHER_TYPE_IPv4, 0, 0);\n\n\tpktlen = initialize_ipv4_header(&pkt_ipv4_hdr,\n\t\t\t\t\tIPV4_ADDR(10, 0, 0, 1),\n\t\t\t\t\tIPV4_ADDR(10, 0, 0, 2), 26);\n\tprintf(\"IPv4 pktlen %u\\n\", pktlen);\n\n\tpktlen = initialize_udp_header(&pkt_udp_hdr, 0, 0, 18);\n\n\tprintf(\"UDP pktlen %u\\n\", pktlen);\n\n\treturn generate_packet_burst(mp, pkts_burst, &pkt_eth_hdr,\n\t\t\t\t 0, &pkt_ipv4_hdr, 1,\n\t\t\t\t &pkt_udp_hdr, burst_size,\n\t\t\t\t PACKET_BURST_GEN_PKT_LEN, 1);\n}\n\nstatic int\ninit_lcores(void)\n{\n\tunsigned lcore_id;\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tlcore_conf[lcore_id].socketid =\n\t\t\trte_lcore_to_socket_id(lcore_id);\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0) {\n\t\t\tlcore_conf[lcore_id].status = LCORE_INVALID;\n\t\t\tcontinue;\n\t\t} else\n\t\t\tlcore_conf[lcore_id].status = LCORE_AVAIL;\n\t}\n\treturn 0;\n}\n\nstatic int\ninit_mbufpool(unsigned nb_mbuf)\n{\n\tint socketid;\n\tunsigned lcore_id;\n\tchar s[64];\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\tcontinue;\n\n\t\tsocketid = rte_lcore_to_socket_id(lcore_id);\n\t\tif (socketid >= NB_SOCKETS) {\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"Socket %d of lcore %u is out of range %d\\n\",\n\t\t\t\tsocketid, lcore_id, NB_SOCKETS);\n\t\t}\n\t\tif (mbufpool[socketid] == NULL) {\n\t\t\tsnprintf(s, sizeof(s), \"mbuf_pool_%d\", socketid);\n\t\t\tmbufpool[socketid] =\n\t\t\t\trte_pktmbuf_pool_create(s, nb_mbuf,\n\t\t\t\t\tMEMPOOL_CACHE_SIZE, 0,\n\t\t\t\t\tRTE_MBUF_DEFAULT_BUF_SIZE, socketid);\n\t\t\tif (mbufpool[socketid] == NULL)\n\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\"Cannot init mbuf pool on socket %d\\n\",\n\t\t\t\t\tsocketid);\n\t\t\telse\n\t\t\t\tprintf(\"Allocated mbuf pool on socket %d\\n\",\n\t\t\t\t\tsocketid);\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic uint16_t\nalloc_lcore(uint16_t socketid)\n{\n\tunsigned lcore_id;\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tif (LCORE_AVAIL != lcore_conf[lcore_id].status ||\n\t\t lcore_conf[lcore_id].socketid != socketid ||\n\t\t lcore_id == rte_get_master_lcore())\n\t\t\tcontinue;\n\t\tlcore_conf[lcore_id].status = LCORE_USED;\n\t\tlcore_conf[lcore_id].nb_ports = 0;\n\t\treturn lcore_id;\n\t}\n\n\treturn (uint16_t)-1;\n}\n\nvolatile uint64_t stop;\nuint64_t count;\nuint64_t drop;\nuint64_t idle;\n\nstatic void\nreset_count(void)\n{\n\tcount = 0;\n\tdrop = 0;\n\tidle = 0;\n}\n\nstatic void\nstats_display(uint8_t port_id)\n{\n\tstruct rte_eth_stats stats;\n\trte_eth_stats_get(port_id, &stats);\n\n\tprintf(\" RX-packets: %-10\"PRIu64\" RX-missed: %-10\"PRIu64\" RX-bytes: \"\n\t \"%-\"PRIu64\"\\n\",\n\t stats.ipackets, stats.imissed, stats.ibytes);\n\tprintf(\" RX-badcrc: %-10\"PRIu64\" RX-badlen: %-10\"PRIu64\" RX-errors: \"\n\t \"%-\"PRIu64\"\\n\",\n\t stats.ibadcrc, stats.ibadlen, stats.ierrors);\n\tprintf(\" RX-nombuf: %-10\"PRIu64\"\\n\",\n\t stats.rx_nombuf);\n\tprintf(\" TX-packets: %-10\"PRIu64\" TX-errors: %-10\"PRIu64\" TX-bytes: \"\n\t \"%-\"PRIu64\"\\n\",\n\t stats.opackets, stats.oerrors, stats.obytes);\n}\n\nstatic void\nsignal_handler(int signum)\n{\n\t/* USR1 signal, stop testing */\n\tif (signum == SIGUSR1) {\n\t\tprintf(\"Force Stop!\\n\");\n\t\tstop = 1;\n\t}\n\n\t/* USR2 signal, print stats */\n\tif (signum == SIGUSR2)\n\t\tstats_display(0);\n}\n\nstruct rte_mbuf **tx_burst;\n\nuint64_t (*do_measure)(struct lcore_conf *conf,\n\t\t struct rte_mbuf *pkts_burst[],\n\t\t uint64_t total_pkts);\n\nstatic uint64_t\nmeasure_rxtx(struct lcore_conf *conf,\n\t struct rte_mbuf *pkts_burst[],\n\t uint64_t total_pkts)\n{\n\tunsigned i, portid, nb_rx, nb_tx;\n\tuint64_t prev_tsc, cur_tsc;\n\n\tprev_tsc = rte_rdtsc();\n\n\twhile (likely(!stop)) {\n\t\tfor (i = 0; i < conf->nb_ports; i++) {\n\t\t\tportid = conf->portlist[i];\n\t\t\tnb_rx = rte_eth_rx_burst((uint8_t) portid, 0,\n\t\t\t\t\t\t pkts_burst, MAX_PKT_BURST);\n\t\t\tif (unlikely(nb_rx == 0)) {\n\t\t\t\tidle++;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tcount += nb_rx;\n\t\t\tnb_tx = rte_eth_tx_burst(portid, 0, pkts_burst, nb_rx);\n\t\t\tif (unlikely(nb_tx < nb_rx)) {\n\t\t\t\tdrop += (nb_rx - nb_tx);\n\t\t\t\tdo {\n\t\t\t\t\trte_pktmbuf_free(pkts_burst[nb_tx]);\n\t\t\t\t} while (++nb_tx < nb_rx);\n\t\t\t}\n\t\t}\n\t\tif (unlikely(count >= total_pkts))\n\t\t\tbreak;\n\t}\n\n\tcur_tsc = rte_rdtsc();\n\n\treturn cur_tsc - prev_tsc;\n}\n\nstatic uint64_t\nmeasure_rxonly(struct lcore_conf *conf,\n\t struct rte_mbuf *pkts_burst[],\n\t uint64_t total_pkts)\n{\n\tunsigned i, portid, nb_rx, nb_tx;\n\tuint64_t diff_tsc, cur_tsc;\n\n\tdiff_tsc = 0;\n\twhile (likely(!stop)) {\n\t\tfor (i = 0; i < conf->nb_ports; i++) {\n\t\t\tportid = conf->portlist[i];\n\n\t\t\tcur_tsc = rte_rdtsc();\n\t\t\tnb_rx = rte_eth_rx_burst((uint8_t) portid, 0,\n\t\t\t\t\t\t pkts_burst, MAX_PKT_BURST);\n\t\t\tif (unlikely(nb_rx == 0)) {\n\t\t\t\tidle++;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tdiff_tsc += rte_rdtsc() - cur_tsc;\n\n\t\t\tcount += nb_rx;\n\t\t\tnb_tx = rte_eth_tx_burst(portid, 0, pkts_burst, nb_rx);\n\t\t\tif (unlikely(nb_tx < nb_rx)) {\n\t\t\t\tdrop += (nb_rx - nb_tx);\n\t\t\t\tdo {\n\t\t\t\t\trte_pktmbuf_free(pkts_burst[nb_tx]);\n\t\t\t\t} while (++nb_tx < nb_rx);\n\t\t\t}\n\t\t}\n\t\tif (unlikely(count >= total_pkts))\n\t\t\tbreak;\n\t}\n\n\treturn diff_tsc;\n}\n\nstatic uint64_t\nmeasure_txonly(struct lcore_conf *conf,\n\t struct rte_mbuf *pkts_burst[],\n\t uint64_t total_pkts)\n{\n\tunsigned i, portid, nb_rx, nb_tx;\n\tuint64_t diff_tsc, cur_tsc;\n\n\tprintf(\"do tx measure\\n\");\n\tdiff_tsc = 0;\n\twhile (likely(!stop)) {\n\t\tfor (i = 0; i < conf->nb_ports; i++) {\n\t\t\tportid = conf->portlist[i];\n\t\t\tnb_rx = rte_eth_rx_burst((uint8_t) portid, 0,\n\t\t\t\t\t\t pkts_burst, MAX_PKT_BURST);\n\t\t\tif (unlikely(nb_rx == 0)) {\n\t\t\t\tidle++;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tcount += nb_rx;\n\n\t\t\tcur_tsc = rte_rdtsc();\n\t\t\tnb_tx = rte_eth_tx_burst(portid, 0, pkts_burst, nb_rx);\n\t\t\tif (unlikely(nb_tx < nb_rx)) {\n\t\t\t\tdrop += (nb_rx - nb_tx);\n\t\t\t\tdo {\n\t\t\t\t\trte_pktmbuf_free(pkts_burst[nb_tx]);\n\t\t\t\t} while (++nb_tx < nb_rx);\n\t\t\t}\n\t\t\tdiff_tsc += rte_rdtsc() - cur_tsc;\n\t\t}\n\t\tif (unlikely(count >= total_pkts))\n\t\t\tbreak;\n\t}\n\n\treturn diff_tsc;\n}\n\n/* main processing loop */\nstatic int\nmain_loop(__rte_unused void *args)\n{\n#define PACKET_SIZE 64\n#define FRAME_GAP 12\n#define MAC_PREAMBLE 8\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tunsigned lcore_id;\n\tunsigned i, portid, nb_rx = 0, nb_tx = 0;\n\tstruct lcore_conf *conf;\n\tint pkt_per_port;\n\tuint64_t diff_tsc;\n\tuint64_t packets_per_second, total_packets;\n\n\tlcore_id = rte_lcore_id();\n\tconf = &lcore_conf[lcore_id];\n\tif (conf->status != LCORE_USED)\n\t\treturn 0;\n\n\tpkt_per_port = MAX_TRAFFIC_BURST;\n\n\tint idx = 0;\n\tfor (i = 0; i < conf->nb_ports; i++) {\n\t\tint num = pkt_per_port;\n\t\tportid = conf->portlist[i];\n\t\tprintf(\"inject %d packet to port %d\\n\", num, portid);\n\t\twhile (num) {\n\t\t\tnb_tx = RTE_MIN(MAX_PKT_BURST, num);\n\t\t\tnb_tx = rte_eth_tx_burst(portid, 0,\n\t\t\t\t\t\t&tx_burst[idx], nb_tx);\n\t\t\tnum -= nb_tx;\n\t\t\tidx += nb_tx;\n\t\t}\n\t}\n\tprintf(\"Total packets inject to prime ports = %u\\n\", idx);\n\n\tpackets_per_second = (link_mbps * 1000 * 1000) /\n\t\t((PACKET_SIZE + FRAME_GAP + MAC_PREAMBLE) * CHAR_BIT);\n\tprintf(\"Each port will do %\"PRIu64\" packets per second\\n\",\n\t packets_per_second);\n\n\ttotal_packets = RTE_TEST_DURATION * conf->nb_ports * packets_per_second;\n\tprintf(\"Test will stop after at least %\"PRIu64\" packets received\\n\",\n\t\t+ total_packets);\n\n\tdiff_tsc = do_measure(conf, pkts_burst, total_packets);\n\n\tfor (i = 0; i < conf->nb_ports; i++) {\n\t\tportid = conf->portlist[i];\n\t\tint nb_free = pkt_per_port;\n\t\tdo { /* dry out */\n\t\t\tnb_rx = rte_eth_rx_burst((uint8_t) portid, 0,\n\t\t\t\t\t\t pkts_burst, MAX_PKT_BURST);\n\t\t\tnb_tx = 0;\n\t\t\twhile (nb_tx < nb_rx)\n\t\t\t\trte_pktmbuf_free(pkts_burst[nb_tx++]);\n\t\t\tnb_free -= nb_rx;\n\t\t} while (nb_free != 0);\n\t\tprintf(\"free %d mbuf left in port %u\\n\", pkt_per_port, portid);\n\t}\n\n\tif (count == 0)\n\t\treturn -1;\n\n\tprintf(\"%\"PRIu64\" packet, %\"PRIu64\" drop, %\"PRIu64\" idle\\n\",\n\t count, drop, idle);\n\tprintf(\"Result: %\"PRIu64\" cycles per packet\\n\", diff_tsc / count);\n\n\treturn 0;\n}\n\nrte_atomic64_t start;\n\nstatic inline int\npoll_burst(void *args)\n{\n#define MAX_IDLE (10000)\n\tunsigned lcore_id;\n\tstruct rte_mbuf **pkts_burst;\n\tuint64_t diff_tsc, cur_tsc;\n\tuint16_t next[RTE_MAX_ETHPORTS];\n\tstruct lcore_conf *conf;\n\tuint32_t pkt_per_port = *((uint32_t *)args);\n\tunsigned i, portid, nb_rx = 0;\n\tuint64_t total;\n\tuint64_t timeout = MAX_IDLE;\n\n\tlcore_id = rte_lcore_id();\n\tconf = &lcore_conf[lcore_id];\n\tif (conf->status != LCORE_USED)\n\t\treturn 0;\n\n\ttotal = pkt_per_port * conf->nb_ports;\n\tprintf(\"start to receive total expect %\"PRIu64\"\\n\", total);\n\n\tpkts_burst = (struct rte_mbuf **)\n\t\trte_calloc_socket(\"poll_burst\",\n\t\t\t\t total, sizeof(void *),\n\t\t\t\t RTE_CACHE_LINE_SIZE, conf->socketid);\n\tif (!pkts_burst)\n\t\treturn -1;\n\n\tfor (i = 0; i < conf->nb_ports; i++) {\n\t\tportid = conf->portlist[i];\n\t\tnext[portid] = i * pkt_per_port;\n\t}\n\n\twhile (!rte_atomic64_read(&start))\n\t\t;\n\n\tcur_tsc = rte_rdtsc();\n\twhile (total) {\n\t\tfor (i = 0; i < conf->nb_ports; i++) {\n\t\t\tportid = conf->portlist[i];\n\t\t\tnb_rx = rte_eth_rx_burst((uint8_t) portid, 0,\n\t\t\t\t\t\t &pkts_burst[next[portid]],\n\t\t\t\t\t\t MAX_PKT_BURST);\n\t\t\tif (unlikely(nb_rx == 0)) {\n\t\t\t\ttimeout--;\n\t\t\t\tif (unlikely(timeout == 0))\n\t\t\t\t\tgoto timeout;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tnext[portid] += nb_rx;\n\t\t\ttotal -= nb_rx;\n\t\t}\n\t}\ntimeout:\n\tdiff_tsc = rte_rdtsc() - cur_tsc;\n\n\tprintf(\"%\"PRIu64\" packets lost, IDLE %\"PRIu64\" times\\n\",\n\t total, MAX_IDLE - timeout);\n\n\t/* clean up */\n\ttotal = pkt_per_port * conf->nb_ports - total;\n\tfor (i = 0; i < total; i++)\n\t\trte_pktmbuf_free(pkts_burst[i]);\n\n\trte_free(pkts_burst);\n\n\treturn diff_tsc / total;\n}\n\nstatic int\nexec_burst(uint32_t flags, int lcore)\n{\n\tunsigned i, portid, nb_tx = 0;\n\tstruct lcore_conf *conf;\n\tuint32_t pkt_per_port;\n\tint num, idx = 0;\n\tint diff_tsc;\n\n\tconf = &lcore_conf[lcore];\n\n\tpkt_per_port = MAX_TRAFFIC_BURST;\n\tnum = pkt_per_port;\n\n\trte_atomic64_init(&start);\n\n\t/* start polling thread, but not actually poll yet */\n\trte_eal_remote_launch(poll_burst,\n\t\t\t (void *)&pkt_per_port, lcore);\n\n\t/* Only when polling first */\n\tif (flags == SC_BURST_POLL_FIRST)\n\t\trte_atomic64_set(&start, 1);\n\n\t/* start xmit */\n\twhile (num) {\n\t\tnb_tx = RTE_MIN(MAX_PKT_BURST, num);\n\t\tfor (i = 0; i < conf->nb_ports; i++) {\n\t\t\tportid = conf->portlist[i];\n\t\t\trte_eth_tx_burst(portid, 0,\n\t\t\t\t\t &tx_burst[idx], nb_tx);\n\t\t\tidx += nb_tx;\n\t\t}\n\t\tnum -= nb_tx;\n\t}\n\n\tsleep(5);\n\n\t/* only when polling second */\n\tif (flags == SC_BURST_XMIT_FIRST)\n\t\trte_atomic64_set(&start, 1);\n\n\t/* wait for polling finished */\n\tdiff_tsc = rte_eal_wait_lcore(lcore);\n\tif (diff_tsc < 0)\n\t\treturn -1;\n\n\tprintf(\"Result: %d cycles per packet\\n\", diff_tsc);\n\n\treturn 0;\n}\n\nstatic int\ntest_pmd_perf(void)\n{\n\tuint16_t nb_ports, num, nb_lcores, slave_id = (uint16_t)-1;\n\tuint16_t nb_rxd = MAX_TRAFFIC_BURST;\n\tuint16_t nb_txd = MAX_TRAFFIC_BURST;\n\tuint16_t portid;\n\tuint16_t nb_rx_queue = 1, nb_tx_queue = 1;\n\tint socketid = -1;\n\tint ret;\n\n\tprintf(\"Start PMD RXTX cycles cost test.\\n\");\n\n\tsignal(SIGUSR1, signal_handler);\n\tsignal(SIGUSR2, signal_handler);\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports < NB_ETHPORTS_USED) {\n\t\tprintf(\"At least %u port(s) used for perf. test\\n\",\n\t\t NB_ETHPORTS_USED);\n\t\treturn -1;\n\t}\n\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\tnb_lcores = rte_lcore_count();\n\n\tmemset(lcore_conf, 0, sizeof(lcore_conf));\n\tinit_lcores();\n\n\tinit_mbufpool(NB_MBUF);\n\n\tif (sc_flag == SC_CONTINUOUS) {\n\t\tnb_rxd = RTE_TEST_RX_DESC_DEFAULT;\n\t\tnb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\t}\n\tprintf(\"CONFIG RXD=%d TXD=%d\\n\", nb_rxd, nb_txd);\n\n\treset_count();\n\tnum = 0;\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tif (socketid == -1) {\n\t\t\tsocketid = rte_eth_dev_socket_id(portid);\n\t\t\tslave_id = alloc_lcore(socketid);\n\t\t\tif (slave_id == (uint16_t)-1) {\n\t\t\t\tprintf(\"No avail lcore to run test\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tprintf(\"Performance test runs on lcore %u socket %u\\n\",\n\t\t\t slave_id, socketid);\n\t\t}\n\n\t\tif (socketid != rte_eth_dev_socket_id(portid)) {\n\t\t\tprintf(\"Skip port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* port configure */\n\t\tret = rte_eth_dev_configure(portid, nb_rx_queue,\n\t\t\t\t\t nb_tx_queue, &port_conf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"Cannot configure device: err=%d, port=%d\\n\",\n\t\t\t\t ret, portid);\n\n\t\trte_eth_macaddr_get(portid, &ports_eth_addr[portid]);\n\t\tprintf(\"Port %u \", portid);\n\t\tprint_ethaddr(\"Address:\", &ports_eth_addr[portid]);\n\t\tprintf(\"\\n\");\n\n\t\t/* tx queue setup */\n\t\tret = rte_eth_tx_queue_setup(portid, 0, nb_txd,\n\t\t\t\t\t socketid, &tx_conf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"rte_eth_tx_queue_setup: err=%d, \"\n\t\t\t\t\"port=%d\\n\", ret, portid);\n\n\t\t/* rx queue steup */\n\t\tret = rte_eth_rx_queue_setup(portid, 0, nb_rxd,\n\t\t\t\t\t\tsocketid, &rx_conf,\n\t\t\t\t\t\tmbufpool[socketid]);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup: err=%d,\"\n\t\t\t\t \"port=%d\\n\", ret, portid);\n\n\t\t/* Start device */\n\t\tstop = 0;\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"rte_eth_dev_start: err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\n\t\t/* always eanble promiscuous */\n\t\trte_eth_promiscuous_enable(portid);\n\n\t\tlcore_conf[slave_id].portlist[num++] = portid;\n\t\tlcore_conf[slave_id].nb_ports++;\n\t}\n\tcheck_all_ports_link_status(nb_ports, RTE_PORT_ALL);\n\n\tif (tx_burst == NULL) {\n\t\ttx_burst = (struct rte_mbuf **)\n\t\t\trte_calloc_socket(\"tx_buff\",\n\t\t\t\t\t MAX_TRAFFIC_BURST * nb_ports,\n\t\t\t\t\t sizeof(void *),\n\t\t\t\t\t RTE_CACHE_LINE_SIZE, socketid);\n\t\tif (!tx_burst)\n\t\t\treturn -1;\n\t}\n\n\tinit_traffic(mbufpool[socketid],\n\t\t tx_burst, MAX_TRAFFIC_BURST * nb_ports);\n\n\tprintf(\"Generate %d packets @socket %d\\n\",\n\t MAX_TRAFFIC_BURST * nb_ports, socketid);\n\n\tif (sc_flag == SC_CONTINUOUS) {\n\t\t/* do both rxtx by default */\n\t\tif (NULL == do_measure)\n\t\t\tdo_measure = measure_rxtx;\n\n\t\trte_eal_remote_launch(main_loop, NULL, slave_id);\n\n\t\tif (rte_eal_wait_lcore(slave_id) < 0)\n\t\t\treturn -1;\n\t} else if (sc_flag == SC_BURST_POLL_FIRST ||\n\t\t sc_flag == SC_BURST_XMIT_FIRST)\n\t\texec_burst(sc_flag, slave_id);\n\n\t/* port tear down */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tif (socketid != rte_eth_dev_socket_id(portid))\n\t\t\tcontinue;\n\n\t\trte_eth_dev_stop(portid);\n\t}\n\n\treturn 0;\n}\n\nint\ntest_set_rxtx_conf(cmdline_fixed_string_t mode)\n{\n\tprintf(\"mode switch to %s\\n\", mode);\n\n\tif (!strcmp(mode, \"vector\")) {\n\t\t/* vector rx, tx */\n\t\ttx_conf.txq_flags = 0xf01;\n\t\ttx_conf.tx_rs_thresh = 32;\n\t\ttx_conf.tx_free_thresh = 32;\n\t\tport_conf.rxmode.hw_ip_checksum = 0;\n\t\tport_conf.rxmode.enable_scatter = 0;\n\t\treturn 0;\n\t} else if (!strcmp(mode, \"scalar\")) {\n\t\t/* bulk alloc rx, simple tx */\n\t\ttx_conf.txq_flags = 0xf01;\n\t\ttx_conf.tx_rs_thresh = 128;\n\t\ttx_conf.tx_free_thresh = 128;\n\t\tport_conf.rxmode.hw_ip_checksum = 1;\n\t\tport_conf.rxmode.enable_scatter = 0;\n\t\treturn 0;\n\t} else if (!strcmp(mode, \"hybrid\")) {\n\t\t/* bulk alloc rx, vector tx\n\t\t * when vec macro not define,\n\t\t * using the same rx/tx as scalar\n\t\t */\n\t\ttx_conf.txq_flags = 0xf01;\n\t\ttx_conf.tx_rs_thresh = 32;\n\t\ttx_conf.tx_free_thresh = 32;\n\t\tport_conf.rxmode.hw_ip_checksum = 1;\n\t\tport_conf.rxmode.enable_scatter = 0;\n\t\treturn 0;\n\t} else if (!strcmp(mode, \"full\")) {\n\t\t/* full feature rx,tx pair */\n\t\ttx_conf.txq_flags = 0x0; /* must condition */\n\t\ttx_conf.tx_rs_thresh = 32;\n\t\ttx_conf.tx_free_thresh = 32;\n\t\tport_conf.rxmode.hw_ip_checksum = 0;\n\t\tport_conf.rxmode.enable_scatter = 1; /* must condition */\n\t\treturn 0;\n\t}\n\n\treturn -1;\n}\n\nint\ntest_set_rxtx_anchor(cmdline_fixed_string_t type)\n{\n\tprintf(\"type switch to %s\\n\", type);\n\n\tif (!strcmp(type, \"rxtx\")) {\n\t\tdo_measure = measure_rxtx;\n\t\treturn 0;\n\t} else if (!strcmp(type, \"rxonly\")) {\n\t\tdo_measure = measure_rxonly;\n\t\treturn 0;\n\t} else if (!strcmp(type, \"txonly\")) {\n\t\tdo_measure = measure_txonly;\n\t\treturn 0;\n\t}\n\n\treturn -1;\n}\n\nint\ntest_set_rxtx_sc(cmdline_fixed_string_t type)\n{\n\tprintf(\"stream control switch to %s\\n\", type);\n\n\tif (!strcmp(type, \"continuous\")) {\n\t\tsc_flag = SC_CONTINUOUS;\n\t\treturn 0;\n\t} else if (!strcmp(type, \"poll_before_xmit\")) {\n\t\tsc_flag = SC_BURST_POLL_FIRST;\n\t\treturn 0;\n\t} else if (!strcmp(type, \"poll_after_xmit\")) {\n\t\tsc_flag = SC_BURST_XMIT_FIRST;\n\t\treturn 0;\n\t}\n\n\treturn -1;\n}\n\nstatic struct test_command pmd_perf_cmd = {\n\t.command = \"pmd_perf_autotest\",\n\t.callback = test_pmd_perf,\n};\nREGISTER_TEST_COMMAND(pmd_perf_cmd);\n" }, { "path": "app/test/test_pmd_ring.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \"test.h\"\n\n#include \n\n#include \n#include \n\nstatic struct rte_mempool *mp;\n\n#define TX_PORT 0\n#define RX_PORT 1\n#define RXTX_PORT 2\n#define RXTX_PORT2 3\n#define RXTX_PORT3 4\n#define SOCKET0 0\n\n#define RING_SIZE 256\n\n#define NB_MBUF 512\n\nstatic int\ntest_ethdev_configure(void)\n{\n\tstruct rte_eth_conf null_conf;\n\tstruct rte_eth_link link;\n\n\tmemset(&null_conf, 0, sizeof(struct rte_eth_conf));\n\n\tif ((TX_PORT >= RTE_MAX_ETHPORTS) || (RX_PORT >= RTE_MAX_ETHPORTS)\\\n\t\t|| (RXTX_PORT >= RTE_MAX_ETHPORTS)) {\n\t\tprintf(\" TX/RX port exceed max eth ports\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_eth_dev_configure(TX_PORT, 1, 2, &null_conf) < 0) {\n\t\tprintf(\"Configure failed for TX port\\n\");\n\t\treturn -1;\n\t}\n\n\t/* Test queue release */\n\tif (rte_eth_dev_configure(TX_PORT, 1, 1, &null_conf) < 0) {\n\t\tprintf(\"Configure failed for TX port\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_eth_dev_configure(RX_PORT, 1, 1, &null_conf) < 0) {\n\t\tprintf(\"Configure failed for RX port\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_eth_dev_configure(RXTX_PORT, 1, 1, &null_conf) < 0) {\n\t\tprintf(\"Configure failed for RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_eth_tx_queue_setup(TX_PORT, 0, RING_SIZE, SOCKET0, NULL) < 0) {\n\t\tprintf(\"TX queue setup failed\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_eth_rx_queue_setup(RX_PORT, 0, RING_SIZE, SOCKET0,\n\t\t\tNULL, mp) < 0) {\n\t\tprintf(\"RX queue setup failed\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_eth_tx_queue_setup(RXTX_PORT, 0, RING_SIZE, SOCKET0, NULL) < 0) {\n\t\tprintf(\"TX queue setup failed\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_eth_rx_queue_setup(RXTX_PORT, 0, RING_SIZE, SOCKET0,\n\t\t\tNULL, mp) < 0) {\n\t\tprintf(\"RX queue setup failed\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_eth_dev_start(TX_PORT) < 0) {\n\t\tprintf(\"Error starting TX port\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_eth_dev_start(RX_PORT) < 0) {\n\t\tprintf(\"Error starting RX port\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_eth_dev_start(RXTX_PORT) < 0) {\n\t\tprintf(\"Error starting RX port\\n\");\n\t\treturn -1;\n\t}\n\n\trte_eth_link_get(TX_PORT, &link);\n\trte_eth_link_get(RX_PORT, &link);\n\trte_eth_link_get(RXTX_PORT, &link);\n\n\treturn 0;\n}\n\nstatic int\ntest_send_basic_packets(void)\n{\n\tstruct rte_mbuf bufs[RING_SIZE];\n\tstruct rte_mbuf *pbufs[RING_SIZE];\n\tint i;\n\n\tprintf(\"Testing ring pmd RX/TX\\n\");\n\n\tfor (i = 0; i < RING_SIZE/2; i++)\n\t\tpbufs[i] = &bufs[i];\n\n\tif (rte_eth_tx_burst(TX_PORT, 0, pbufs, RING_SIZE/2) < RING_SIZE/2) {\n\t\tprintf(\"Failed to transmit packet burst\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_eth_rx_burst(RX_PORT, 0, pbufs, RING_SIZE) != RING_SIZE/2) {\n\t\tprintf(\"Failed to receive packet burst\\n\");\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < RING_SIZE/2; i++)\n\t\tif (pbufs[i] != &bufs[i]) {\n\t\t\tprintf(\"Error: received data does not match that transmitted\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\treturn 0;\n}\n\nstatic int\ntest_get_stats(void)\n{\n\tstruct rte_eth_stats stats;\n\tstruct rte_mbuf buf, *pbuf = &buf;\n\n\tprintf(\"Testing ring PMD stats\\n\");\n\n\t/* check stats of RXTX port, should all be zero */\n\trte_eth_stats_get(RXTX_PORT, &stats);\n\tif (stats.ipackets != 0 || stats.opackets != 0 ||\n\t\t\tstats.ibytes != 0 || stats.obytes != 0 ||\n\t\t\tstats.ierrors != 0 || stats.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not zero\\n\");\n\t\treturn -1;\n\t}\n\n\t/* send and receive 1 packet and check for stats update */\n\tif (rte_eth_tx_burst(RXTX_PORT, 0, &pbuf, 1) != 1) {\n\t\tprintf(\"Error sending packet to RXTX port\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_eth_rx_burst(RXTX_PORT, 0, &pbuf, 1) != 1) {\n\t\tprintf(\"Error receiving packet from RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\trte_eth_stats_get(RXTX_PORT, &stats);\n\tif (stats.ipackets != 1 || stats.opackets != 1 ||\n\t\t\tstats.ibytes != 0 || stats.obytes != 0 ||\n\t\t\tstats.ierrors != 0 || stats.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not as expected\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic int\ntest_stats_reset(void)\n{\n\tstruct rte_eth_stats stats;\n\tstruct rte_mbuf buf, *pbuf = &buf;\n\n\tprintf(\"Testing ring PMD stats reset\\n\");\n\n\trte_eth_stats_reset(RXTX_PORT);\n\n\t/* check stats of RXTX port, should all be zero */\n\trte_eth_stats_get(RXTX_PORT, &stats);\n\tif (stats.ipackets != 0 || stats.opackets != 0 ||\n\t\t\tstats.ibytes != 0 || stats.obytes != 0 ||\n\t\t\tstats.ierrors != 0 || stats.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not zero\\n\");\n\t\treturn -1;\n\t}\n\n\t/* send and receive 1 packet and check for stats update */\n\tif (rte_eth_tx_burst(RXTX_PORT, 0, &pbuf, 1) != 1) {\n\t\tprintf(\"Error sending packet to RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_eth_rx_burst(RXTX_PORT, 0, &pbuf, 1) != 1) {\n\t\tprintf(\"Error receiving packet from RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\trte_eth_stats_get(RXTX_PORT, &stats);\n\tif (stats.ipackets != 1 || stats.opackets != 1 ||\n\t\t\tstats.ibytes != 0 || stats.obytes != 0 ||\n\t\t\tstats.ierrors != 0 || stats.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not as expected\\n\");\n\t\treturn -1;\n\t}\n\n\trte_eth_stats_reset(RXTX_PORT);\n\n\t/* check stats of RXTX port, should all be zero */\n\trte_eth_stats_get(RXTX_PORT, &stats);\n\tif (stats.ipackets != 0 || stats.opackets != 0 ||\n\t\t\tstats.ibytes != 0 || stats.obytes != 0 ||\n\t\t\tstats.ierrors != 0 || stats.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not zero\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntest_pmd_ring_pair_create_attach(void)\n{\n\tstruct rte_eth_stats stats, stats2;\n\tstruct rte_mbuf buf, *pbuf = &buf;\n\tstruct rte_eth_conf null_conf;\n\n\tif ((RXTX_PORT2 >= RTE_MAX_ETHPORTS) || (RXTX_PORT3 >= RTE_MAX_ETHPORTS)) {\n\t\tprintf(\" TX/RX port exceed max eth ports\\n\");\n\t\treturn -1;\n\t}\n\tif ((rte_eth_dev_configure(RXTX_PORT2, 1, 1, &null_conf) < 0)\n\t\t|| (rte_eth_dev_configure(RXTX_PORT3, 1, 1, &null_conf) < 0)) {\n\t\tprintf(\"Configure failed for RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\tif ((rte_eth_tx_queue_setup(RXTX_PORT2, 0, RING_SIZE, SOCKET0, NULL) < 0)\n\t\t|| (rte_eth_tx_queue_setup(RXTX_PORT3, 0, RING_SIZE, SOCKET0, NULL) < 0)) {\n\t\tprintf(\"TX queue setup failed\\n\");\n\t\treturn -1;\n\t}\n\n\tif ((rte_eth_rx_queue_setup(RXTX_PORT2, 0, RING_SIZE, SOCKET0, NULL, mp) < 0)\n\t\t|| (rte_eth_rx_queue_setup(RXTX_PORT3, 0, RING_SIZE, SOCKET0, NULL, mp) < 0)) {\n\t\tprintf(\"RX queue setup failed\\n\");\n\t\treturn -1;\n\t}\n\n\tif ((rte_eth_dev_start(RXTX_PORT2) < 0)\n\t\t|| (rte_eth_dev_start(RXTX_PORT3) < 0)) {\n\t\tprintf(\"Error starting RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * send and receive 1 packet (RXTX_PORT2 -> RXTX_PORT3)\n\t * and check for stats update\n\t */\n\tif (rte_eth_tx_burst(RXTX_PORT2, 0, &pbuf, 1) != 1) {\n\t\tprintf(\"Error sending packet to RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_eth_rx_burst(RXTX_PORT3, 0, &pbuf, 1) != 1) {\n\t\tprintf(\"Error receiving packet from RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\trte_eth_stats_get(RXTX_PORT2, &stats);\n\trte_eth_stats_get(RXTX_PORT3, &stats2);\n\tif (stats.ipackets != 0 || stats.opackets != 1 ||\n\t\t\tstats.ibytes != 0 || stats.obytes != 0 ||\n\t\t\tstats.ierrors != 0 || stats.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not as expected\\n\");\n\t\treturn -1;\n\t}\n\n\tif (stats2.ipackets != 1 || stats2.opackets != 0 ||\n\t\t\tstats2.ibytes != 0 || stats2.obytes != 0 ||\n\t\t\tstats2.ierrors != 0 || stats2.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not as expected\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * send and receive 1 packet (RXTX_PORT3 -> RXTX_PORT2)\n\t * and check for stats update\n\t */\n\tif (rte_eth_tx_burst(RXTX_PORT3, 0, &pbuf, 1) != 1) {\n\t\tprintf(\"Error sending packet to RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_eth_rx_burst(RXTX_PORT2, 0, &pbuf, 1) != 1) {\n\t\tprintf(\"Error receiving packet from RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\trte_eth_stats_get(RXTX_PORT2, &stats);\n\trte_eth_stats_get(RXTX_PORT3, &stats2);\n\tif (stats.ipackets != 1 || stats.opackets != 1 ||\n\t\t\tstats.ibytes != 0 || stats.obytes != 0 ||\n\t\t\tstats.ierrors != 0 || stats.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not as expected\\n\");\n\t\treturn -1;\n\t}\n\n\tif (stats2.ipackets != 1 || stats2.opackets != 1 ||\n\t\t\tstats2.ibytes != 0 || stats2.obytes != 0 ||\n\t\t\tstats2.ierrors != 0 || stats2.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not as expected\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * send and receive 1 packet (RXTX_PORT2 -> RXTX_PORT2)\n\t * and check for stats update\n\t */\n\tif (rte_eth_tx_burst(RXTX_PORT2, 0, &pbuf, 1) != 1) {\n\t\tprintf(\"Error sending packet to RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_eth_rx_burst(RXTX_PORT2, 0, &pbuf, 1) != 1) {\n\t\tprintf(\"Error receiving packet from RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\trte_eth_stats_get(RXTX_PORT2, &stats);\n\trte_eth_stats_get(RXTX_PORT3, &stats2);\n\tif (stats.ipackets != 2 || stats.opackets != 2 ||\n\t\t\tstats.ibytes != 0 || stats.obytes != 0 ||\n\t\t\tstats.ierrors != 0 || stats.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not as expected\\n\");\n\t\treturn -1;\n\t}\n\n\tif (stats2.ipackets != 1 || stats2.opackets != 1 ||\n\t\t\tstats2.ibytes != 0 || stats2.obytes != 0 ||\n\t\t\tstats2.ierrors != 0 || stats2.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not as expected\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * send and receive 1 packet (RXTX_PORT3 -> RXTX_PORT3)\n\t * and check for stats update\n\t */\n\tif (rte_eth_tx_burst(RXTX_PORT3, 0, &pbuf, 1) != 1) {\n\t\tprintf(\"Error sending packet to RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_eth_rx_burst(RXTX_PORT3, 0, &pbuf, 1) != 1) {\n\t\tprintf(\"Error receiving packet from RXTX port\\n\");\n\t\treturn -1;\n\t}\n\n\trte_eth_stats_get(RXTX_PORT2, &stats);\n\trte_eth_stats_get(RXTX_PORT3, &stats2);\n\tif (stats.ipackets != 2 || stats.opackets != 2 ||\n\t\t\tstats.ibytes != 0 || stats.obytes != 0 ||\n\t\t\tstats.ierrors != 0 || stats.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not as expected\\n\");\n\t\treturn -1;\n\t}\n\n\tif (stats2.ipackets != 2 || stats2.opackets != 2 ||\n\t\t\tstats2.ibytes != 0 || stats2.obytes != 0 ||\n\t\t\tstats2.ierrors != 0 || stats2.oerrors != 0) {\n\t\tprintf(\"Error: RXTX port stats are not as expected\\n\");\n\t\treturn -1;\n\t}\n\n\trte_eth_dev_stop(RXTX_PORT2);\n\trte_eth_dev_stop(RXTX_PORT3);\n\n\treturn 0;\n}\n\nstatic int\ntest_pmd_ring(void)\n{\n\tmp = rte_pktmbuf_pool_create(\"mbuf_pool\", NB_MBUF, 32,\n\t\t0, RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\tif (mp == NULL)\n\t\treturn -1;\n\n\tif ((TX_PORT >= RTE_MAX_ETHPORTS) || (RX_PORT >= RTE_MAX_ETHPORTS)\\\n\t\t|| (RXTX_PORT >= RTE_MAX_ETHPORTS)) {\n\t\tprintf(\" TX/RX port exceed max eth ports\\n\");\n\t\treturn -1;\n\t}\n\n\tif (test_ethdev_configure() < 0)\n\t\treturn -1;\n\n\tif (test_send_basic_packets() < 0)\n\t\treturn -1;\n\n\tif (test_get_stats() < 0)\n\t\treturn -1;\n\n\tif (test_stats_reset() < 0)\n\t\treturn -1;\n\n\trte_eth_dev_stop(RX_PORT);\n\trte_eth_dev_stop(TX_PORT);\n\trte_eth_dev_stop(RXTX_PORT);\n\n\tif (test_pmd_ring_pair_create_attach() < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic struct test_command ring_pmd_cmd = {\n\t.command = \"ring_pmd_autotest\",\n\t.callback = test_pmd_ring,\n};\nREGISTER_TEST_COMMAND(ring_pmd_cmd);\n" }, { "path": "app/test/test_power.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#include \n\nstatic int\ntest_power(void)\n{\n\tint ret = -1;\n\tenum power_management_env env;\n\n\t/* Test setting an invalid environment */\n\tret = rte_power_set_env(PM_ENV_NOT_SET);\n\tif (ret == 0) {\n\t\tprintf(\"Unexpectedly succeeded on setting an invalid environment\\n\");\n\t\treturn -1;\n\t}\n\n\t/* Test that the environment has not been set */\n\tenv = rte_power_get_env();\n\tif (env != PM_ENV_NOT_SET) {\n\t\tprintf(\"Unexpectedly got a valid environment configuration\\n\");\n\t\treturn -1;\n\t}\n\n\t/* verify that function pointers are NULL */\n\tif (rte_power_freqs != NULL) {\n\t\tprintf(\"rte_power_freqs should be NULL, environment has not been \"\n\t\t\t\t\"initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\tif (rte_power_get_freq != NULL) {\n\t\tprintf(\"rte_power_get_freq should be NULL, environment has not been \"\n\t\t\t\t\"initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\tif (rte_power_set_freq != NULL) {\n\t\tprintf(\"rte_power_set_freq should be NULL, environment has not been \"\n\t\t\t\t\"initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\tif (rte_power_freq_up != NULL) {\n\t\tprintf(\"rte_power_freq_up should be NULL, environment has not been \"\n\t\t\t\t\"initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\tif (rte_power_freq_down != NULL) {\n\t\tprintf(\"rte_power_freq_down should be NULL, environment has not been \"\n\t\t\t\t\"initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\tif (rte_power_freq_max != NULL) {\n\t\tprintf(\"rte_power_freq_max should be NULL, environment has not been \"\n\t\t\t\t\"initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\tif (rte_power_freq_min != NULL) {\n\t\tprintf(\"rte_power_freq_min should be NULL, environment has not been \"\n\t\t\t\t\"initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\trte_power_unset_env();\n\treturn 0;\nfail_all:\n\trte_power_unset_env();\n\treturn -1;\n}\n\nstatic struct test_command power_cmd = {\n\t.command = \"power_autotest\",\n\t.callback = test_power,\n};\nREGISTER_TEST_COMMAND(power_cmd);\n" }, { "path": "app/test/test_power_acpi_cpufreq.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#include \n\n#define TEST_POWER_LCORE_ID 2U\n#define TEST_POWER_LCORE_INVALID ((unsigned)RTE_MAX_LCORE)\n#define TEST_POWER_FREQS_NUM_MAX ((unsigned)RTE_MAX_LCORE_FREQS)\n\n#define TEST_POWER_SYSFILE_CUR_FREQ \\\n\t\"/sys/devices/system/cpu/cpu%u/cpufreq/scaling_cur_freq\"\n\nstatic uint32_t total_freq_num;\nstatic uint32_t freqs[TEST_POWER_FREQS_NUM_MAX];\n\nstatic int\ncheck_cur_freq(unsigned lcore_id, uint32_t idx)\n{\n#define TEST_POWER_CONVERT_TO_DECIMAL 10\n\tFILE *f;\n\tchar fullpath[PATH_MAX];\n\tchar buf[BUFSIZ];\n\tuint32_t cur_freq;\n\tint ret = -1;\n\n\tif (snprintf(fullpath, sizeof(fullpath),\n\t\tTEST_POWER_SYSFILE_CUR_FREQ, lcore_id) < 0) {\n\t\treturn 0;\n\t}\n\tf = fopen(fullpath, \"r\");\n\tif (f == NULL) {\n\t\treturn 0;\n\t}\n\tif (fgets(buf, sizeof(buf), f) == NULL) {\n\t\tgoto fail_get_cur_freq;\n\t}\n\tcur_freq = strtoul(buf, NULL, TEST_POWER_CONVERT_TO_DECIMAL);\n\tret = (freqs[idx] == cur_freq ? 0 : -1);\n\nfail_get_cur_freq:\n\tfclose(f);\n\n\treturn ret;\n}\n\n/* Check rte_power_freqs() */\nstatic int\ncheck_power_freqs(void)\n{\n\tuint32_t ret;\n\n\ttotal_freq_num = 0;\n\tmemset(freqs, 0, sizeof(freqs));\n\n\t/* test with an invalid lcore id */\n\tret = rte_power_freqs(TEST_POWER_LCORE_INVALID, freqs,\n\t\t\t\t\tTEST_POWER_FREQS_NUM_MAX);\n\tif (ret > 0) {\n\t\tprintf(\"Unexpectedly get available freqs successfully on \"\n\t\t\t\t\"lcore %u\\n\", TEST_POWER_LCORE_INVALID);\n\t\treturn -1;\n\t}\n\n\t/* test with NULL buffer to save available freqs */\n\tret = rte_power_freqs(TEST_POWER_LCORE_ID, NULL,\n\t\t\t\tTEST_POWER_FREQS_NUM_MAX);\n\tif (ret > 0) {\n\t\tprintf(\"Unexpectedly get available freqs successfully with \"\n\t\t\t\"NULL buffer on lcore %u\\n\", TEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* test of getting zero number of freqs */\n\tret = rte_power_freqs(TEST_POWER_LCORE_ID, freqs, 0);\n\tif (ret > 0) {\n\t\tprintf(\"Unexpectedly get available freqs successfully with \"\n\t\t\t\"zero buffer size on lcore %u\\n\", TEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* test with all valid input parameters */\n\tret = rte_power_freqs(TEST_POWER_LCORE_ID, freqs,\n\t\t\t\tTEST_POWER_FREQS_NUM_MAX);\n\tif (ret == 0 || ret > TEST_POWER_FREQS_NUM_MAX) {\n\t\tprintf(\"Fail to get available freqs on lcore %u\\n\",\n\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* Save the total number of available freqs */\n\ttotal_freq_num = ret;\n\n\treturn 0;\n}\n\n/* Check rte_power_get_freq() */\nstatic int\ncheck_power_get_freq(void)\n{\n\tint ret;\n\tuint32_t count;\n\n\t/* test with an invalid lcore id */\n\tcount = rte_power_get_freq(TEST_POWER_LCORE_INVALID);\n\tif (count < TEST_POWER_FREQS_NUM_MAX) {\n\t\tprintf(\"Unexpectedly get freq index successfully on \"\n\t\t\t\t\"lcore %u\\n\", TEST_POWER_LCORE_INVALID);\n\t\treturn -1;\n\t}\n\n\tcount = rte_power_get_freq(TEST_POWER_LCORE_ID);\n\tif (count >= TEST_POWER_FREQS_NUM_MAX) {\n\t\tprintf(\"Fail to get the freq index on lcore %u\\n\",\n\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* Check the current frequency */\n\tret = check_cur_freq(TEST_POWER_LCORE_ID, count);\n\tif (ret < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/* Check rte_power_set_freq() */\nstatic int\ncheck_power_set_freq(void)\n{\n\tint ret;\n\n\t/* test with an invalid lcore id */\n\tret = rte_power_set_freq(TEST_POWER_LCORE_INVALID, 0);\n\tif (ret >= 0) {\n\t\tprintf(\"Unexpectedly set freq index successfully on \"\n\t\t\t\t\"lcore %u\\n\", TEST_POWER_LCORE_INVALID);\n\t\treturn -1;\n\t}\n\n\t/* test with an invalid freq index */\n\tret = rte_power_set_freq(TEST_POWER_LCORE_ID,\n\t\t\t\tTEST_POWER_FREQS_NUM_MAX);\n\tif (ret >= 0) {\n\t\tprintf(\"Unexpectedly set an invalid freq index (%u)\"\n\t\t\t\"successfully on lcore %u\\n\", TEST_POWER_FREQS_NUM_MAX,\n\t\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/**\n\t * test with an invalid freq index which is right one bigger than\n\t * total number of freqs\n\t */\n\tret = rte_power_set_freq(TEST_POWER_LCORE_ID, total_freq_num);\n\tif (ret >= 0) {\n\t\tprintf(\"Unexpectedly set an invalid freq index (%u)\"\n\t\t\t\"successfully on lcore %u\\n\", total_freq_num,\n\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\tret = rte_power_set_freq(TEST_POWER_LCORE_ID, total_freq_num - 1);\n\tif (ret < 0) {\n\t\tprintf(\"Fail to set freq index on lcore %u\\n\",\n\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* Check the current frequency */\n\tret = check_cur_freq(TEST_POWER_LCORE_ID, total_freq_num - 1);\n\tif (ret < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/* Check rte_power_freq_down() */\nstatic int\ncheck_power_freq_down(void)\n{\n\tint ret;\n\n\t/* test with an invalid lcore id */\n\tret = rte_power_freq_down(TEST_POWER_LCORE_INVALID);\n\tif (ret >= 0) {\n\t\tprintf(\"Unexpectedly scale down successfully the freq on \"\n\t\t\t\t\"lcore %u\\n\", TEST_POWER_LCORE_INVALID);\n\t\treturn -1;\n\t}\n\n\t/* Scale down to min and then scale down one step */\n\tret = rte_power_freq_min(TEST_POWER_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Fail to scale down the freq to min on lcore %u\\n\",\n\t\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\tret = rte_power_freq_down(TEST_POWER_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Fail to scale down the freq on lcore %u\\n\",\n\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* Check the current frequency */\n\tret = check_cur_freq(TEST_POWER_LCORE_ID, total_freq_num - 1);\n\tif (ret < 0)\n\t\treturn -1;\n\n\t/* Scale up to max and then scale down one step */\n\tret = rte_power_freq_max(TEST_POWER_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Fail to scale up the freq to max on lcore %u\\n\",\n\t\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\tret = rte_power_freq_down(TEST_POWER_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Fail to scale down the freq on lcore %u\\n\",\n\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* Check the current frequency */\n\tret = check_cur_freq(TEST_POWER_LCORE_ID, 1);\n\tif (ret < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/* Check rte_power_freq_up() */\nstatic int\ncheck_power_freq_up(void)\n{\n\tint ret;\n\n\t/* test with an invalid lcore id */\n\tret = rte_power_freq_up(TEST_POWER_LCORE_INVALID);\n\tif (ret >= 0) {\n\t\tprintf(\"Unexpectedly scale up successfully the freq on %u\\n\",\n\t\t\t\t\t\tTEST_POWER_LCORE_INVALID);\n\t\treturn -1;\n\t}\n\n\t/* Scale down to min and then scale up one step */\n\tret = rte_power_freq_min(TEST_POWER_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Fail to scale down the freq to min on lcore %u\\n\",\n\t\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\tret = rte_power_freq_up(TEST_POWER_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Fail to scale up the freq on lcore %u\\n\",\n\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* Check the current frequency */\n\tret = check_cur_freq(TEST_POWER_LCORE_ID, total_freq_num - 2);\n\tif (ret < 0)\n\t\treturn -1;\n\n\t/* Scale up to max and then scale up one step */\n\tret = rte_power_freq_max(TEST_POWER_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Fail to scale up the freq to max on lcore %u\\n\",\n\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\tret = rte_power_freq_up(TEST_POWER_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Fail to scale up the freq on lcore %u\\n\",\n\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* Check the current frequency */\n\tret = check_cur_freq(TEST_POWER_LCORE_ID, 0);\n\tif (ret < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/* Check rte_power_freq_max() */\nstatic int\ncheck_power_freq_max(void)\n{\n\tint ret;\n\n\t/* test with an invalid lcore id */\n\tret = rte_power_freq_max(TEST_POWER_LCORE_INVALID);\n\tif (ret >= 0) {\n\t\tprintf(\"Unexpectedly scale up successfully the freq to max on \"\n\t\t\t\t\"lcore %u\\n\", TEST_POWER_LCORE_INVALID);\n\t\treturn -1;\n\t}\n\tret = rte_power_freq_max(TEST_POWER_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Fail to scale up the freq to max on lcore %u\\n\",\n\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* Check the current frequency */\n\tret = check_cur_freq(TEST_POWER_LCORE_ID, 0);\n\tif (ret < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/* Check rte_power_freq_min() */\nstatic int\ncheck_power_freq_min(void)\n{\n\tint ret;\n\n\t/* test with an invalid lcore id */\n\tret = rte_power_freq_min(TEST_POWER_LCORE_INVALID);\n\tif (ret >= 0) {\n\t\tprintf(\"Unexpectedly scale down successfully the freq to min \"\n\t\t\t\t\"on lcore %u\\n\", TEST_POWER_LCORE_INVALID);\n\t\treturn -1;\n\t}\n\tret = rte_power_freq_min(TEST_POWER_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Fail to scale down the freq to min on lcore %u\\n\",\n\t\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* Check the current frequency */\n\tret = check_cur_freq(TEST_POWER_LCORE_ID, total_freq_num - 1);\n\tif (ret < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic int\ntest_power_acpi_cpufreq(void)\n{\n\tint ret = -1;\n\tenum power_management_env env;\n\n\tret = rte_power_set_env(PM_ENV_ACPI_CPUFREQ);\n\tif (ret != 0) {\n\t\tprintf(\"Failed on setting environment to PM_ENV_ACPI_CPUFREQ, this \"\n\t\t\t\t\"may occur if environment is not configured correctly or \"\n\t\t\t\t\" operating in another valid Power management environment\\n\");\n\t\treturn -1;\n\t}\n\n\t/* Test environment configuration */\n\tenv = rte_power_get_env();\n\tif (env != PM_ENV_ACPI_CPUFREQ) {\n\t\tprintf(\"Unexpectedly got an environment other than ACPI cpufreq\\n\");\n\t\tgoto fail_all;\n\t}\n\n\t/* verify that function pointers are not NULL */\n\tif (rte_power_freqs == NULL) {\n\t\tprintf(\"rte_power_freqs should not be NULL, environment has not been \"\n\t\t\t\t\"initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\tif (rte_power_get_freq == NULL) {\n\t\tprintf(\"rte_power_get_freq should not be NULL, environment has not \"\n\t\t\t\t\"been initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\tif (rte_power_set_freq == NULL) {\n\t\tprintf(\"rte_power_set_freq should not be NULL, environment has not \"\n\t\t\t\t\"been initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\tif (rte_power_freq_up == NULL) {\n\t\tprintf(\"rte_power_freq_up should not be NULL, environment has not \"\n\t\t\t\t\"been initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\tif (rte_power_freq_down == NULL) {\n\t\tprintf(\"rte_power_freq_down should not be NULL, environment has not \"\n\t\t\t\t\"been initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\tif (rte_power_freq_max == NULL) {\n\t\tprintf(\"rte_power_freq_max should not be NULL, environment has not \"\n\t\t\t\t\"been initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\tif (rte_power_freq_min == NULL) {\n\t\tprintf(\"rte_power_freq_min should not be NULL, environment has not \"\n\t\t\t\t\"been initialised\\n\");\n\t\tgoto fail_all;\n\t}\n\n\t/* test of init power management for an invalid lcore */\n\tret = rte_power_init(TEST_POWER_LCORE_INVALID);\n\tif (ret == 0) {\n\t\tprintf(\"Unexpectedly initialise power management successfully \"\n\t\t\t\t\"for lcore %u\\n\", TEST_POWER_LCORE_INVALID);\n\t\trte_power_unset_env();\n\t\treturn -1;\n\t}\n\n\t/* Test initialisation of a valid lcore */\n\tret = rte_power_init(TEST_POWER_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Cannot initialise power management for lcore %u, this \"\n\t\t\t\t\"may occur if environment is not configured \"\n\t\t\t\t\"correctly(APCI cpufreq) or operating in another valid \"\n\t\t\t\t\"Power management environment\\n\", TEST_POWER_LCORE_ID);\n\t\trte_power_unset_env();\n\t\treturn -1;\n\t}\n\n\t/**\n\t * test of initialising power management for the lcore which has\n\t * been initialised\n\t */\n\tret = rte_power_init(TEST_POWER_LCORE_ID);\n\tif (ret == 0) {\n\t\tprintf(\"Unexpectedly init successfully power twice on \"\n\t\t\t\t\t\"lcore %u\\n\", TEST_POWER_LCORE_ID);\n\t\tgoto fail_all;\n\t}\n\n\tret = check_power_freqs();\n\tif (ret < 0)\n\t\tgoto fail_all;\n\n\tif (total_freq_num < 2) {\n\t\trte_power_exit(TEST_POWER_LCORE_ID);\n\t\tprintf(\"Frequency can not be changed due to CPU itself\\n\");\n\t\trte_power_unset_env();\n\t\treturn 0;\n\t}\n\n\tret = check_power_get_freq();\n\tif (ret < 0)\n\t\tgoto fail_all;\n\n\tret = check_power_set_freq();\n\tif (ret < 0)\n\t\tgoto fail_all;\n\n\tret = check_power_freq_down();\n\tif (ret < 0)\n\t\tgoto fail_all;\n\n\tret = check_power_freq_up();\n\tif (ret < 0)\n\t\tgoto fail_all;\n\n\tret = check_power_freq_max();\n\tif (ret < 0)\n\t\tgoto fail_all;\n\n\tret = check_power_freq_min();\n\tif (ret < 0)\n\t\tgoto fail_all;\n\n\tret = rte_power_exit(TEST_POWER_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Cannot exit power management for lcore %u\\n\",\n\t\t\t\t\t\tTEST_POWER_LCORE_ID);\n\t\trte_power_unset_env();\n\t\treturn -1;\n\t}\n\n\t/**\n\t * test of exiting power management for the lcore which has been exited\n\t */\n\tret = rte_power_exit(TEST_POWER_LCORE_ID);\n\tif (ret == 0) {\n\t\tprintf(\"Unexpectedly exit successfully power management twice \"\n\t\t\t\t\t\"on lcore %u\\n\", TEST_POWER_LCORE_ID);\n\t\trte_power_unset_env();\n\t\treturn -1;\n\t}\n\n\t/* test of exit power management for an invalid lcore */\n\tret = rte_power_exit(TEST_POWER_LCORE_INVALID);\n\tif (ret == 0) {\n\t\tprintf(\"Unpectedly exit power management successfully for \"\n\t\t\t\t\"lcore %u\\n\", TEST_POWER_LCORE_INVALID);\n\t\trte_power_unset_env();\n\t\treturn -1;\n\t}\n\trte_power_unset_env();\n\treturn 0;\n\nfail_all:\n\trte_power_exit(TEST_POWER_LCORE_ID);\n\trte_power_unset_env();\n\treturn -1;\n}\n\nstatic struct test_command power_acpi_cpufreq_cmd = {\n\t.command = \"power_acpi_cpufreq_autotest\",\n\t.callback = test_power_acpi_cpufreq,\n};\nREGISTER_TEST_COMMAND(power_acpi_cpufreq_cmd);\n" }, { "path": "app/test/test_power_kvm_vm.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#include \n#include \n\n#define TEST_POWER_VM_LCORE_ID 0U\n#define TEST_POWER_VM_LCORE_OUT_OF_BOUNDS (RTE_MAX_LCORE+1)\n#define TEST_POWER_VM_LCORE_INVALID 1U\n\nstatic int\ntest_power_kvm_vm(void)\n{\n\tint ret;\n\tenum power_management_env env;\n\n\tret = rte_power_set_env(PM_ENV_KVM_VM);\n\tif (ret != 0) {\n\t\tprintf(\"Failed on setting environment to PM_ENV_KVM_VM\\n\");\n\t\treturn -1;\n\t}\n\n\t/* Test environment configuration */\n\tenv = rte_power_get_env();\n\tif (env != PM_ENV_KVM_VM) {\n\t\tprintf(\"Unexpectedly got a Power Management environment other than \"\n\t\t\t\t\"KVM VM\\n\");\n\t\trte_power_unset_env();\n\t\treturn -1;\n\t}\n\n\t/* verify that function pointers are not NULL */\n\tif (rte_power_freqs == NULL) {\n\t\tprintf(\"rte_power_freqs should not be NULL, environment has not been \"\n\t\t\t\t\"initialised\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_power_get_freq == NULL) {\n\t\tprintf(\"rte_power_get_freq should not be NULL, environment has not \"\n\t\t\t\t\"been initialised\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_power_set_freq == NULL) {\n\t\tprintf(\"rte_power_set_freq should not be NULL, environment has not \"\n\t\t\t\t\"been initialised\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_power_freq_up == NULL) {\n\t\tprintf(\"rte_power_freq_up should not be NULL, environment has not \"\n\t\t\t\t\"been initialised\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_power_freq_down == NULL) {\n\t\tprintf(\"rte_power_freq_down should not be NULL, environment has not \"\n\t\t\t\t\"been initialised\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_power_freq_max == NULL) {\n\t\tprintf(\"rte_power_freq_max should not be NULL, environment has not \"\n\t\t\t\t\"been initialised\\n\");\n\t\treturn -1;\n\t}\n\tif (rte_power_freq_min == NULL) {\n\t\tprintf(\"rte_power_freq_min should not be NULL, environment has not \"\n\t\t\t\t\"been initialised\\n\");\n\t\treturn -1;\n\t}\n\t/* Test initialisation of an out of bounds lcore */\n\tret = rte_power_init(TEST_POWER_VM_LCORE_OUT_OF_BOUNDS);\n\tif (ret != -1) {\n\t\tprintf(\"rte_power_init unexpectedly succeeded on an invalid lcore %u\\n\",\n\t\t\t\tTEST_POWER_VM_LCORE_OUT_OF_BOUNDS);\n\t\trte_power_unset_env();\n\t\treturn -1;\n\t}\n\n\t/* Test initialisation of a valid lcore */\n\tret = rte_power_init(TEST_POWER_VM_LCORE_ID);\n\tif (ret < 0) {\n\t\tprintf(\"Cannot initialise power management for lcore %u, this \"\n\t\t\t\t\"may occur if environment is not configured \"\n\t\t\t\t\"correctly(KVM VM) or operating in another valid \"\n\t\t\t\t\"Power management environment\\n\", TEST_POWER_VM_LCORE_ID);\n\t\trte_power_unset_env();\n\t\treturn -1;\n\t}\n\n\t/* Test initialisation of previously initialised lcore */\n\tret = rte_power_init(TEST_POWER_VM_LCORE_ID);\n\tif (ret == 0) {\n\t\tprintf(\"rte_power_init unexpectedly succeeded on calling init twice on\"\n\t\t\t\t\" lcore %u\\n\", TEST_POWER_VM_LCORE_ID);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency up of invalid lcore */\n\tret = rte_power_freq_up(TEST_POWER_VM_LCORE_OUT_OF_BOUNDS);\n\tif (ret == 1) {\n\t\tprintf(\"rte_power_freq_up unexpectedly succeeded on invalid lcore %u\\n\",\n\t\t\t\tTEST_POWER_VM_LCORE_OUT_OF_BOUNDS);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency down of invalid lcore */\n\tret = rte_power_freq_down(TEST_POWER_VM_LCORE_OUT_OF_BOUNDS);\n\tif (ret == 1) {\n\t\tprintf(\"rte_power_freq_down unexpectedly succeeded on invalid lcore \"\n\t\t\t\t\"%u\\n\", TEST_POWER_VM_LCORE_OUT_OF_BOUNDS);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency min of invalid lcore */\n\tret = rte_power_freq_min(TEST_POWER_VM_LCORE_OUT_OF_BOUNDS);\n\tif (ret == 1) {\n\t\tprintf(\"rte_power_freq_min unexpectedly succeeded on invalid lcore \"\n\t\t\t\t\"%u\\n\", TEST_POWER_VM_LCORE_OUT_OF_BOUNDS);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency max of invalid lcore */\n\tret = rte_power_freq_max(TEST_POWER_VM_LCORE_OUT_OF_BOUNDS);\n\tif (ret == 1) {\n\t\tprintf(\"rte_power_freq_max unexpectedly succeeded on invalid lcore \"\n\t\t\t\t\"%u\\n\", TEST_POWER_VM_LCORE_OUT_OF_BOUNDS);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency up of valid but uninitialised lcore */\n\tret = rte_power_freq_up(TEST_POWER_VM_LCORE_INVALID);\n\tif (ret == 1) {\n\t\tprintf(\"rte_power_freq_up unexpectedly succeeded on invalid lcore %u\\n\",\n\t\t\t\tTEST_POWER_VM_LCORE_INVALID);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency down of valid but uninitialised lcore */\n\tret = rte_power_freq_down(TEST_POWER_VM_LCORE_INVALID);\n\tif (ret == 1) {\n\t\tprintf(\"rte_power_freq_down unexpectedly succeeded on invalid lcore \"\n\t\t\t\t\"%u\\n\", TEST_POWER_VM_LCORE_INVALID);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency min of valid but uninitialised lcore */\n\tret = rte_power_freq_min(TEST_POWER_VM_LCORE_INVALID);\n\tif (ret == 1) {\n\t\tprintf(\"rte_power_freq_min unexpectedly succeeded on invalid lcore \"\n\t\t\t\t\"%u\\n\", TEST_POWER_VM_LCORE_INVALID);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency max of valid but uninitialised lcore */\n\tret = rte_power_freq_max(TEST_POWER_VM_LCORE_INVALID);\n\tif (ret == 1) {\n\t\tprintf(\"rte_power_freq_max unexpectedly succeeded on invalid lcore \"\n\t\t\t\t\"%u\\n\", TEST_POWER_VM_LCORE_INVALID);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency up of valid lcore */\n\tret = rte_power_freq_up(TEST_POWER_VM_LCORE_ID);\n\tif (ret != 1) {\n\t\tprintf(\"rte_power_freq_up unexpectedly failed on valid lcore %u\\n\",\n\t\t\t\tTEST_POWER_VM_LCORE_ID);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency down of valid lcore */\n\tret = rte_power_freq_down(TEST_POWER_VM_LCORE_ID);\n\tif (ret != 1) {\n\t\tprintf(\"rte_power_freq_down unexpectedly failed on valid lcore \"\n\t\t\t\t\"%u\\n\", TEST_POWER_VM_LCORE_ID);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency min of valid lcore */\n\tret = rte_power_freq_min(TEST_POWER_VM_LCORE_ID);\n\tif (ret != 1) {\n\t\tprintf(\"rte_power_freq_min unexpectedly failed on valid lcore \"\n\t\t\t\t\"%u\\n\", TEST_POWER_VM_LCORE_ID);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency max of valid lcore */\n\tret = rte_power_freq_max(TEST_POWER_VM_LCORE_ID);\n\tif (ret != 1) {\n\t\tprintf(\"rte_power_freq_max unexpectedly failed on valid lcore \"\n\t\t\t\t\"%u\\n\", TEST_POWER_VM_LCORE_ID);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test unsupported rte_power_freqs */\n\tret = rte_power_freqs(TEST_POWER_VM_LCORE_ID, NULL, 0);\n\tif (ret != -ENOTSUP) {\n\t\tprintf(\"rte_power_freqs did not return the expected -ENOTSUP(%d) but \"\n\t\t\t\t\"returned %d\\n\", -ENOTSUP, ret);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test unsupported rte_power_get_freq */\n\tret = rte_power_get_freq(TEST_POWER_VM_LCORE_ID);\n\tif (ret != -ENOTSUP) {\n\t\tprintf(\"rte_power_get_freq did not return the expected -ENOTSUP(%d) but\"\n\t\t\t\t\" returned %d for lcore %u\\n\",\n\t\t\t\t-ENOTSUP, ret, TEST_POWER_VM_LCORE_ID);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test unsupported rte_power_set_freq */\n\tret = rte_power_set_freq(TEST_POWER_VM_LCORE_ID, 0);\n\tif (ret != -ENOTSUP) {\n\t\tprintf(\"rte_power_set_freq did not return the expected -ENOTSUP(%d) but\"\n\t\t\t\t\" returned %d for lcore %u\\n\",\n\t\t\t\t-ENOTSUP, ret, TEST_POWER_VM_LCORE_ID);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test removing of an lcore */\n\tret = rte_power_exit(TEST_POWER_VM_LCORE_ID);\n\tif (ret != 0) {\n\t\tprintf(\"rte_power_exit unexpectedly failed on valid lcore %u,\"\n\t\t\t\t\"please ensure that the environment has been configured \"\n\t\t\t\t\"correctly\\n\", TEST_POWER_VM_LCORE_ID);\n\t\tgoto fail_all;\n\t}\n\n\t/* Test frequency up of previously removed lcore */\n\tret = rte_power_freq_up(TEST_POWER_VM_LCORE_ID);\n\tif (ret == 0) {\n\t\tprintf(\"rte_power_freq_up unexpectedly succeeded on a removed \"\n\t\t\t\t\"lcore %u\\n\", TEST_POWER_VM_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* Test frequency down of previously removed lcore */\n\tret = rte_power_freq_down(TEST_POWER_VM_LCORE_ID);\n\tif (ret == 0) {\n\t\tprintf(\"rte_power_freq_down unexpectedly succeeded on a removed \"\n\t\t\t\t\"lcore %u\\n\", TEST_POWER_VM_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* Test frequency min of previously removed lcore */\n\tret = rte_power_freq_min(TEST_POWER_VM_LCORE_ID);\n\tif (ret == 0) {\n\t\tprintf(\"rte_power_freq_min unexpectedly succeeded on a removed \"\n\t\t\t\t\"lcore %u\\n\", TEST_POWER_VM_LCORE_ID);\n\t\treturn -1;\n\t}\n\n\t/* Test frequency max of previously removed lcore */\n\tret = rte_power_freq_max(TEST_POWER_VM_LCORE_ID);\n\tif (ret == 0) {\n\t\tprintf(\"rte_power_freq_max unexpectedly succeeded on a removed \"\n\t\t\t\t\"lcore %u\\n\", TEST_POWER_VM_LCORE_ID);\n\t\treturn -1;\n\t}\n\trte_power_unset_env();\n\treturn 0;\nfail_all:\n\trte_power_exit(TEST_POWER_VM_LCORE_ID);\n\trte_power_unset_env();\n\treturn -1;\n}\n\nstatic struct test_command power_kvm_vm_cmd = {\n\t.command = \"power_kvm_vm_autotest\",\n\t.callback = test_power_kvm_vm,\n};\nREGISTER_TEST_COMMAND(power_kvm_vm_cmd);\n" }, { "path": "app/test/test_prefetch.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n\n#include \"test.h\"\n\n/*\n * Prefetch test\n * =============\n *\n * - Just test that the macro can be called and validate the compilation.\n * The test always return success.\n */\n\nstatic int\ntest_prefetch(void)\n{\n\tint a;\n\n\trte_prefetch0(&a);\n\trte_prefetch1(&a);\n\trte_prefetch2(&a);\n\n\treturn 0;\n}\n\nstatic struct test_command prefetch_cmd = {\n\t.command = \"prefetch_autotest\",\n\t.callback = test_prefetch,\n};\nREGISTER_TEST_COMMAND(prefetch_cmd);\n" }, { "path": "app/test/test_red.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#include \n\n#ifdef __INTEL_COMPILER\n#pragma warning(disable:2259) /* conversion may lose significant bits */\n#pragma warning(disable:181) /* Arg incompatible with format string */\n#endif\n\n#define TEST_HZ_PER_KHZ 1000\n#define TEST_NSEC_MARGIN 500 /**< nanosecond margin when calculating clk freq */\n\n#define MAX_QEMPTY_TIME_MSEC 50000\n#define MSEC_PER_SEC 1000 /**< Milli-seconds per second */\n#define USEC_PER_MSEC 1000 /**< Micro-seconds per milli-second */\n#define USEC_PER_SEC 1000000 /**< Micro-seconds per second */\n\n/**< structures for testing rte_red performance and function */\nstruct test_rte_red_config { /**< Test structure for RTE_RED config */\n\tstruct rte_red_config *rconfig; /**< RTE_RED configuration parameters */\n\tuint8_t num_cfg; /**< Number of RTE_RED configs to test */\n\tuint8_t *wq_log2; /**< Test wq_log2 value to use */\n\tuint32_t min_th; /**< Queue minimum threshold */\n\tuint32_t max_th; /**< Queue maximum threshold */\n\tuint8_t *maxp_inv; /**< Inverse mark probability */\n};\n\nstruct test_queue { /**< Test structure for RTE_RED Queues */\n\tstruct rte_red *rdata; /**< RTE_RED runtime data */\n\tuint32_t num_queues; /**< Number of RTE_RED queues to test */\n\tuint32_t *qconfig; /**< Configuration of RTE_RED queues for test */\n\tuint32_t *q; /**< Queue size */\n\tuint32_t q_ramp_up; /**< Num of enqueues to ramp up the queue */\n\tuint32_t avg_ramp_up; /**< Average num of enqueues to ramp up the queue */\n\tuint32_t avg_tolerance; /**< Tolerance in queue average */\n\tdouble drop_tolerance; /**< Drop tolerance of packets not enqueued */\n};\n\nstruct test_var { /**< Test variables used for testing RTE_RED */\n\tuint32_t wait_usec; /**< Micro second wait interval */\n\tuint32_t num_iterations; /**< Number of test iterations */\n\tuint32_t num_ops; /**< Number of test operations */\n\tuint64_t clk_freq; /**< CPU clock frequency */\n\tuint32_t sleep_sec; /**< Seconds to sleep */\n\tuint32_t *dropped; /**< Test operations dropped */\n\tuint32_t *enqueued; /**< Test operations enqueued */\n};\n\nstruct test_config { /**< Master test structure for RTE_RED */\n\tconst char *ifname; /**< Interface name */\n\tconst char *msg; /**< Test message for display */\n\tconst char *htxt; /**< Header txt display for result output */\n\tstruct test_rte_red_config *tconfig; /**< Test structure for RTE_RED config */\n\tstruct test_queue *tqueue; /**< Test structure for RTE_RED Queues */\n\tstruct test_var *tvar; /**< Test variables used for testing RTE_RED */\n\tuint32_t *tlevel; /**< Queue levels */\n};\n\nenum test_result {\n\tFAIL = 0,\n\tPASS\n};\n\n/**< Test structure to define tests to run */\nstruct tests {\n\tstruct test_config *testcfg;\n\tenum test_result (*testfn)(struct test_config *);\n};\n\nstruct rdtsc_prof {\n\tuint64_t clk_start;\n\tuint64_t clk_min; /**< min clocks */\n\tuint64_t clk_max; /**< max clocks */\n\tuint64_t clk_avgc; /**< count to calc average */\n\tdouble clk_avg; /**< cumulative sum to calc average */\n\tconst char *name;\n};\n\nstatic const uint64_t port_speed_bytes = (10ULL*1000ULL*1000ULL*1000ULL)/8ULL;\nstatic double inv_cycles_per_byte = 0;\nstatic double pkt_time_usec = 0;\n\nstatic void init_port_ts(uint64_t cpu_clock)\n{\n\tdouble cycles_per_byte = (double)(cpu_clock) / (double)(port_speed_bytes);\n\tinv_cycles_per_byte = 1.0 / cycles_per_byte;\n\tpkt_time_usec = 1000000.0 / ((double)port_speed_bytes / (double)RTE_RED_S);\n}\n\nstatic uint64_t get_port_ts(void)\n{\n\treturn (uint64_t)((double)rte_rdtsc() * inv_cycles_per_byte);\n}\n\nstatic void rdtsc_prof_init(struct rdtsc_prof *p, const char *name)\n{\n\tp->clk_min = (uint64_t)(-1LL);\n\tp->clk_max = 0;\n\tp->clk_avg = 0;\n\tp->clk_avgc = 0;\n\tp->name = name;\n}\n\nstatic inline void rdtsc_prof_start(struct rdtsc_prof *p)\n{\n#ifdef __PIC__\n asm volatile (\n \"mov %%ebx, %%edi\\n\"\n \"cpuid\\n\"\n \"xchgl %%ebx, %%edi;\\n\"\n\t: : : \"%eax\", \"%edi\", \"%ecx\", \"%edx\" );\n#else\n\tasm( \"cpuid\" : : : \"%eax\", \"%ebx\", \"%ecx\", \"%edx\" );\n#endif\n\tp->clk_start = rte_rdtsc();\n}\n\nstatic inline void rdtsc_prof_end(struct rdtsc_prof *p)\n{\n\tuint64_t clk_start = rte_rdtsc() - p->clk_start;\n\n\tp->clk_avgc++;\n\tp->clk_avg += (double) clk_start;\n\n\tif (clk_start > p->clk_max)\n\t\tp->clk_max = clk_start;\n\tif (clk_start < p->clk_min)\n\t\tp->clk_min = clk_start;\n}\n\nstatic void rdtsc_prof_print(struct rdtsc_prof *p)\n{\n\tif (p->clk_avgc>0) {\n\t\tprintf(\"RDTSC stats for %s: n=%\" PRIu64 \", min=%\" PRIu64 \", max=%\" PRIu64 \", avg=%.1f\\n\",\n\t\t\tp->name,\n\t\t\tp->clk_avgc,\n\t\t\tp->clk_min,\n\t\t\tp->clk_max,\n\t\t\t(p->clk_avg / ((double) p->clk_avgc)));\n\t}\n}\n\nstatic uint32_t rte_red_get_avg_int(const struct rte_red_config *red_cfg,\n\t\t\t\t struct rte_red *red)\n{\n\t/**\n\t * scale by 1/n and convert from fixed-point to integer\n\t */\n\treturn red->avg >> (RTE_RED_SCALING + red_cfg->wq_log2);\n}\n\nstatic double rte_red_get_avg_float(const struct rte_red_config *red_cfg,\n\t\t\t\t struct rte_red *red)\n{\n\t/**\n\t * scale by 1/n and convert from fixed-point to floating-point\n\t */\n\treturn ldexp((double)red->avg, -(RTE_RED_SCALING + red_cfg->wq_log2));\n}\n\nstatic void rte_red_set_avg_int(const struct rte_red_config *red_cfg,\n\t\t\t\tstruct rte_red *red,\n\t\t\t\tuint32_t avg)\n{\n\t/**\n\t * scale by n and convert from integer to fixed-point\n\t */\n\tred->avg = avg << (RTE_RED_SCALING + red_cfg->wq_log2);\n}\n\nstatic double calc_exp_avg_on_empty(double avg, uint32_t n, uint32_t time_diff)\n{\n\treturn avg * pow((1.0 - 1.0 / (double)n), (double)time_diff / pkt_time_usec);\n}\n\nstatic double calc_drop_rate(uint32_t enqueued, uint32_t dropped)\n{\n\treturn (double)dropped / ((double)enqueued + (double)dropped);\n}\n\n/**\n * calculate the drop probability\n */\nstatic double calc_drop_prob(uint32_t min_th, uint32_t max_th,\n\t\t\t uint32_t maxp_inv, uint32_t avg)\n{\n\tdouble drop_prob = 0.0;\n\n\tif (avg < min_th) {\n\t\tdrop_prob = 0.0;\n\t} else if (avg < max_th) {\n\t\tdrop_prob = (1.0 / (double)maxp_inv)\n\t\t\t* ((double)(avg - min_th)\n\t\t\t / (double)(max_th - min_th));\n\t} else {\n\t\tdrop_prob = 1.0;\n\t}\n\treturn (drop_prob);\n}\n\n/**\n * check if drop rate matches drop probability within tolerance\n */\nstatic int check_drop_rate(double *diff, double drop_rate, double drop_prob, double tolerance)\n{\n\tdouble abs_diff = 0.0;\n\tint ret = 1;\n\n\tabs_diff = fabs(drop_rate - drop_prob);\n\tif ((int)abs_diff == 0) {\n\t *diff = 0.0;\n\t} else {\n\t *diff = (abs_diff / drop_prob) * 100.0;\n\t if (*diff > tolerance) {\n\t ret = 0;\n\t }\n }\n\treturn (ret);\n}\n\n/**\n * check if average queue size is within tolerance\n */\nstatic int check_avg(double *diff, double avg, double exp_avg, double tolerance)\n{\n\tdouble abs_diff = 0.0;\n\tint ret = 1;\n\n\tabs_diff = fabs(avg - exp_avg);\n\tif ((int)abs_diff == 0) {\n\t *diff = 0.0;\n\t} else {\n\t *diff = (abs_diff / exp_avg) * 100.0;\n\t if (*diff > tolerance) {\n\t ret = 0;\n }\n\t}\n\treturn (ret);\n}\n\n/**\n * get the clk frequency in Hz\n */\nstatic uint64_t get_machclk_freq(void)\n{\n\tuint64_t start = 0;\n\tuint64_t end = 0;\n\tuint64_t diff = 0;\n\tuint64_t clk_freq_hz = 0;\n\tstruct timespec tv_start = {0, 0}, tv_end = {0, 0};\n\tstruct timespec req = {0, 0};\n\n\treq.tv_sec = 1;\n\treq.tv_nsec = 0;\n\n\tclock_gettime(CLOCK_REALTIME, &tv_start);\n\tstart = rte_rdtsc();\n\n\tif (nanosleep(&req, NULL) != 0) {\n\t\tperror(\"get_machclk_freq()\");\n\t\texit(EXIT_FAILURE);\n\t}\n\n\tclock_gettime(CLOCK_REALTIME, &tv_end);\n\tend = rte_rdtsc();\n\n\tdiff = (uint64_t)(tv_end.tv_sec - tv_start.tv_sec) * USEC_PER_SEC\n\t\t+ ((tv_end.tv_nsec - tv_start.tv_nsec + TEST_NSEC_MARGIN) /\n\t\t USEC_PER_MSEC); /**< diff is in micro secs */\n\n\tif (diff == 0)\n\t\treturn(0);\n\n\tclk_freq_hz = ((end - start) * USEC_PER_SEC / diff);\n\treturn (clk_freq_hz);\n}\n\n/**\n * initialize the test rte_red config\n */\nstatic enum test_result\ntest_rte_red_init(struct test_config *tcfg)\n{\n\tunsigned i = 0;\n\n\ttcfg->tvar->clk_freq = get_machclk_freq();\n\tinit_port_ts( tcfg->tvar->clk_freq );\n\n\tfor (i = 0; i < tcfg->tconfig->num_cfg; i++) {\n\t\tif (rte_red_config_init(&tcfg->tconfig->rconfig[i],\n\t\t\t\t\t(uint16_t)tcfg->tconfig->wq_log2[i],\n\t\t\t\t\t(uint16_t)tcfg->tconfig->min_th,\n\t\t\t\t\t(uint16_t)tcfg->tconfig->max_th,\n\t\t\t\t\t(uint16_t)tcfg->tconfig->maxp_inv[i]) != 0) {\n\t\t\treturn(FAIL);\n\t\t}\n\t}\n\n\t*tcfg->tqueue->q = 0;\n\t*tcfg->tvar->dropped = 0;\n\t*tcfg->tvar->enqueued = 0;\n\treturn(PASS);\n}\n\n/**\n * enqueue until actual queue size reaches target level\n */\nstatic int\nincrease_actual_qsize(struct rte_red_config *red_cfg,\n struct rte_red *red,\n uint32_t *q,\n uint32_t level,\n uint32_t attempts)\n{\n uint32_t i = 0;\n\n for (i = 0; i < attempts; i++) {\n int ret = 0;\n\n /**\n * enqueue\n */\n ret = rte_red_enqueue(red_cfg, red, *q, get_port_ts() );\n if (ret == 0) {\n if (++(*q) >= level)\n break;\n }\n }\n /**\n * check if target actual queue size has been reached\n */\n if (*q != level)\n return (-1);\n /**\n * success\n */\n return (0);\n}\n\n/**\n * enqueue until average queue size reaches target level\n */\nstatic int\nincrease_average_qsize(struct rte_red_config *red_cfg,\n struct rte_red *red,\n uint32_t *q,\n uint32_t level,\n uint32_t num_ops)\n{\n uint32_t avg = 0;\n uint32_t i = 0;\n\n for (i = 0; i < num_ops; i++) {\n /**\n * enqueue\n */\n rte_red_enqueue(red_cfg, red, *q, get_port_ts());\n }\n /**\n * check if target average queue size has been reached\n */\n avg = rte_red_get_avg_int(red_cfg, red);\n if (avg != level)\n return (-1);\n /**\n * success\n */\n return (0);\n}\n\n/**\n * setup default values for the functional test structures\n */\nstatic struct rte_red_config ft_wrconfig[1];\nstatic struct rte_red ft_rtdata[1];\nstatic uint8_t ft_wq_log2[] = {9};\nstatic uint8_t ft_maxp_inv[] = {10};\nstatic uint32_t ft_qconfig[] = {0, 0, 1, 1};\nstatic uint32_t ft_q[] ={0};\nstatic uint32_t ft_dropped[] ={0};\nstatic uint32_t ft_enqueued[] ={0};\n\nstatic struct test_rte_red_config ft_tconfig = {\n\t.rconfig = ft_wrconfig,\n\t.num_cfg = RTE_DIM(ft_wrconfig),\n\t.wq_log2 = ft_wq_log2,\n\t.min_th = 32,\n\t.max_th = 128,\n\t.maxp_inv = ft_maxp_inv,\n};\n\nstatic struct test_queue ft_tqueue = {\n\t.rdata = ft_rtdata,\n\t.num_queues = RTE_DIM(ft_rtdata),\n\t.qconfig = ft_qconfig,\n\t.q = ft_q,\n\t.q_ramp_up = 1000000,\n\t.avg_ramp_up = 1000000,\n\t.avg_tolerance = 5, /* 5 percent */\n\t.drop_tolerance = 50, /* 50 percent */\n};\n\nstatic struct test_var ft_tvar = {\n\t.wait_usec = 250000,\n\t.num_iterations = 20,\n\t.num_ops = 10000,\n\t.clk_freq = 0,\n\t.dropped = ft_dropped,\n\t.enqueued = ft_enqueued,\n\t.sleep_sec = (MAX_QEMPTY_TIME_MSEC / MSEC_PER_SEC) + 2,\n};\n\n/**\n * functional test enqueue/dequeue packets\n */\nstatic void enqueue_dequeue_func(struct rte_red_config *red_cfg,\n struct rte_red *red,\n uint32_t *q,\n uint32_t num_ops,\n uint32_t *enqueued,\n uint32_t *dropped)\n{\n uint32_t i = 0;\n\n for (i = 0; i < num_ops; i++) {\n int ret = 0;\n\n /**\n * enqueue\n */\n ret = rte_red_enqueue(red_cfg, red, *q, get_port_ts());\n if (ret == 0)\n (*enqueued)++;\n else\n (*dropped)++;\n }\n}\n\n/**\n * Test F1: functional test 1\n */\nstatic uint32_t ft1_tlevels[] = {6, 12, 18, 24, 30, 36, 42, 48, 54, 60, 66, 72, 78, 84, 90, 96, 102, 108, 114, 120, 126, 132, 138, 144};\n\nstatic struct test_config func_test1_config = {\n\t.ifname = \"functional test 1 interface\",\n\t.msg = \"functional test 1 : use one rte_red configuration,\\n\"\n\t\"\t\t increase average queue size to various levels,\\n\"\n\t\"\t\t compare drop rate to drop probability\\n\\n\",\n\t.htxt = \" \"\n\t\"avg queue size \"\n\t\"enqueued \"\n\t\"dropped \"\n\t\"drop prob % \"\n\t\"drop rate % \"\n\t\"diff % \"\n\t\"tolerance % \"\n\t\"\\n\",\n\t.tconfig = &ft_tconfig,\n\t.tqueue = &ft_tqueue,\n\t.tvar = &ft_tvar,\n\t.tlevel = ft1_tlevels,\n};\n\nstatic enum test_result func_test1(struct test_config *tcfg)\n{\n\tenum test_result result = PASS;\n\tuint32_t i = 0;\n\n\tprintf(\"%s\", tcfg->msg);\n\n\tif (test_rte_red_init(tcfg) != PASS) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\tprintf(\"%s\", tcfg->htxt);\n\n\tfor (i = 0; i < RTE_DIM(ft1_tlevels); i++) {\n\t\tconst char *label = NULL;\n\t\tuint32_t avg = 0;\n\t\tdouble drop_rate = 0.0;\n\t\tdouble drop_prob = 0.0;\n\t\tdouble diff = 0.0;\n\n\t\t/**\n\t\t * reset rte_red run-time data\n\t\t */\n\t\trte_red_rt_data_init(tcfg->tqueue->rdata);\n\t\t*tcfg->tvar->enqueued = 0;\n\t\t*tcfg->tvar->dropped = 0;\n\n\t\tif (increase_actual_qsize(tcfg->tconfig->rconfig,\n\t\t\t\t\t tcfg->tqueue->rdata,\n\t\t\t\t\t tcfg->tqueue->q,\n\t\t\t\t\t tcfg->tlevel[i],\n\t\t\t\t\t tcfg->tqueue->q_ramp_up) != 0) {\n\t\t\tresult = FAIL;\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (increase_average_qsize(tcfg->tconfig->rconfig,\n\t\t\t\t\t tcfg->tqueue->rdata,\n\t\t\t\t\t tcfg->tqueue->q,\n\t\t\t\t\t tcfg->tlevel[i],\n\t\t\t\t\t tcfg->tqueue->avg_ramp_up) != 0) {\n\t\t\tresult = FAIL;\n\t\t\tgoto out;\n\t\t}\n\n\t\tenqueue_dequeue_func(tcfg->tconfig->rconfig,\n\t\t\t\t tcfg->tqueue->rdata,\n\t\t\t\t tcfg->tqueue->q,\n\t\t\t\t tcfg->tvar->num_ops,\n\t\t\t\t tcfg->tvar->enqueued,\n\t\t\t\t tcfg->tvar->dropped);\n\n\t\tavg = rte_red_get_avg_int(tcfg->tconfig->rconfig, tcfg->tqueue->rdata);\n\t\tif (avg != tcfg->tlevel[i]) {\n fprintf(stderr, \"Fail: avg != level\\n\");\n\t\t\tresult = FAIL;\n }\n\n\t\tdrop_rate = calc_drop_rate(*tcfg->tvar->enqueued, *tcfg->tvar->dropped);\n\t\tdrop_prob = calc_drop_prob(tcfg->tconfig->min_th, tcfg->tconfig->max_th,\n\t\t\t\t\t *tcfg->tconfig->maxp_inv, tcfg->tlevel[i]);\n\t\tif (!check_drop_rate(&diff, drop_rate, drop_prob, (double)tcfg->tqueue->drop_tolerance))\n\t\t result = FAIL;\n\n\t\tif (tcfg->tlevel[i] == tcfg->tconfig->min_th)\n\t\t\tlabel = \"min thresh: \";\n\t\telse if (tcfg->tlevel[i] == tcfg->tconfig->max_th)\n\t\t\tlabel = \"max thresh: \";\n\t\telse\n\t\t\tlabel = \" \";\n\t\tprintf(\"%s%-15u%-15u%-15u%-15.4lf%-15.4lf%-15.4lf%-15.4lf\\n\",\n\t\t label, avg, *tcfg->tvar->enqueued, *tcfg->tvar->dropped,\n\t\t drop_prob * 100.0, drop_rate * 100.0, diff,\n\t (double)tcfg->tqueue->drop_tolerance);\n\t}\nout:\n\treturn (result);\n}\n\n/**\n * Test F2: functional test 2\n */\nstatic uint32_t ft2_tlevel[] = {127};\nstatic uint8_t ft2_wq_log2[] = {9, 9, 9, 9, 9, 9, 9, 9, 9, 9};\nstatic uint8_t ft2_maxp_inv[] = {10, 20, 30, 40, 50, 60, 70, 80, 90, 100};\nstatic struct rte_red_config ft2_rconfig[10];\n\nstatic struct test_rte_red_config ft2_tconfig = {\n\t.rconfig = ft2_rconfig,\n\t.num_cfg = RTE_DIM(ft2_rconfig),\n\t.wq_log2 = ft2_wq_log2,\n\t.min_th = 32,\n\t.max_th = 128,\n\t.maxp_inv = ft2_maxp_inv,\n};\n\nstatic struct test_config func_test2_config = {\n\t.ifname = \"functional test 2 interface\",\n\t.msg = \"functional test 2 : use several RED configurations,\\n\"\n\t\"\t\t increase average queue size to just below maximum threshold,\\n\"\n\t\"\t\t compare drop rate to drop probability\\n\\n\",\n\t.htxt = \"RED config \"\n\t\"avg queue size \"\n\t\"min threshold \"\n\t\"max threshold \"\n\t\"drop prob % \"\n\t\"drop rate % \"\n\t\"diff % \"\n\t\"tolerance % \"\n\t\"\\n\",\n\t.tconfig = &ft2_tconfig,\n\t.tqueue = &ft_tqueue,\n\t.tvar = &ft_tvar,\n\t.tlevel = ft2_tlevel,\n};\n\nstatic enum test_result func_test2(struct test_config *tcfg)\n{\n\tenum test_result result = PASS;\n double prev_drop_rate = 1.0;\n\tuint32_t i = 0;\n\n\tprintf(\"%s\", tcfg->msg);\n\n\tif (test_rte_red_init(tcfg) != PASS) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\trte_red_rt_data_init(tcfg->tqueue->rdata);\n\n\tif (increase_actual_qsize(tcfg->tconfig->rconfig,\n\t\t\t\t tcfg->tqueue->rdata,\n\t\t\t\t tcfg->tqueue->q,\n\t\t\t\t *tcfg->tlevel,\n\t\t\t\t tcfg->tqueue->q_ramp_up) != 0) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\tif (increase_average_qsize(tcfg->tconfig->rconfig,\n\t\t\t\t tcfg->tqueue->rdata,\n\t\t\t\t tcfg->tqueue->q,\n\t\t\t\t *tcfg->tlevel,\n\t\t\t\t tcfg->tqueue->avg_ramp_up) != 0) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\tprintf(\"%s\", tcfg->htxt);\n\n\tfor (i = 0; i < tcfg->tconfig->num_cfg; i++) {\n\t\tuint32_t avg = 0;\n\t\tdouble drop_rate = 0.0;\n\t\tdouble drop_prob = 0.0;\n\t\tdouble diff = 0.0;\n\n\t\t*tcfg->tvar->dropped = 0;\n\t\t*tcfg->tvar->enqueued = 0;\n\n\t\tenqueue_dequeue_func(&tcfg->tconfig->rconfig[i],\n\t\t\t\t tcfg->tqueue->rdata,\n\t\t\t\t tcfg->tqueue->q,\n\t\t\t\t tcfg->tvar->num_ops,\n\t\t\t\t tcfg->tvar->enqueued,\n\t\t\t\t tcfg->tvar->dropped);\n\n\t\tavg = rte_red_get_avg_int(&tcfg->tconfig->rconfig[i], tcfg->tqueue->rdata);\n\t\tif (avg != *tcfg->tlevel)\n\t\t\tresult = FAIL;\n\n\t\tdrop_rate = calc_drop_rate(*tcfg->tvar->enqueued, *tcfg->tvar->dropped);\n\t\tdrop_prob = calc_drop_prob(tcfg->tconfig->min_th, tcfg->tconfig->max_th,\n\t\t\t\t\t tcfg->tconfig->maxp_inv[i], *tcfg->tlevel);\n\t\tif (!check_drop_rate(&diff, drop_rate, drop_prob, (double)tcfg->tqueue->drop_tolerance))\n\t\t result = FAIL;\n\t /**\n\t * drop rate should decrease as maxp_inv increases\n\t */\n\t if (drop_rate > prev_drop_rate)\n\t result = FAIL;\n\t prev_drop_rate = drop_rate;\n\n\t\tprintf(\"%-15u%-15u%-15u%-15u%-15.4lf%-15.4lf%-15.4lf%-15.4lf\\n\",\n\t\t i, avg, tcfg->tconfig->min_th, tcfg->tconfig->max_th,\n\t\t drop_prob * 100.0, drop_rate * 100.0, diff,\n\t (double)tcfg->tqueue->drop_tolerance);\n\t}\nout:\n\treturn (result);\n}\n\n/**\n * Test F3: functional test 3\n */\nstatic uint32_t ft3_tlevel[] = {1022};\n\nstatic struct test_rte_red_config ft3_tconfig = {\n\t.rconfig = ft_wrconfig,\n\t.num_cfg = RTE_DIM(ft_wrconfig),\n\t.wq_log2 = ft_wq_log2,\n\t.min_th = 32,\n\t.max_th = 1023,\n\t.maxp_inv = ft_maxp_inv,\n};\n\nstatic struct test_config func_test3_config = {\n\t.ifname = \"functional test 3 interface\",\n\t.msg = \"functional test 3 : use one RED configuration,\\n\"\n\t\"\t\t increase average queue size to target level,\\n\"\n\t\"\t\t dequeue all packets until queue is empty,\\n\"\n\t\"\t\t confirm that average queue size is computed correctly while queue is empty\\n\\n\",\n\t.htxt = \"q avg before \"\n\t\"q avg after \"\n\t\"expected \"\n\t\"difference % \"\n\t\"tolerance % \"\n\t\"result\t \"\n\t\"\\n\",\n\t.tconfig = &ft3_tconfig,\n\t.tqueue = &ft_tqueue,\n\t.tvar = &ft_tvar,\n\t.tlevel = ft3_tlevel,\n};\n\nstatic enum test_result func_test3(struct test_config *tcfg)\n{\n\tenum test_result result = PASS;\n\tuint32_t i = 0;\n\n\tprintf(\"%s\", tcfg->msg);\n\n\tif (test_rte_red_init(tcfg) != PASS) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\trte_red_rt_data_init(tcfg->tqueue->rdata);\n\n\tif (increase_actual_qsize(tcfg->tconfig->rconfig,\n\t\t\t\t tcfg->tqueue->rdata,\n\t\t\t\t tcfg->tqueue->q,\n\t\t\t\t *tcfg->tlevel,\n\t\t\t\t tcfg->tqueue->q_ramp_up) != 0) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\tif (increase_average_qsize(tcfg->tconfig->rconfig,\n\t\t\t\t tcfg->tqueue->rdata,\n\t\t\t\t tcfg->tqueue->q,\n\t\t\t\t *tcfg->tlevel,\n\t\t\t\t tcfg->tqueue->avg_ramp_up) != 0) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\tprintf(\"%s\", tcfg->htxt);\n\n\tfor (i = 0; i < tcfg->tvar->num_iterations; i++) {\n\t\tdouble avg_before = 0;\n\t\tdouble avg_after = 0;\n double exp_avg = 0;\n\t\tdouble diff = 0.0;\n\n\t\tavg_before = rte_red_get_avg_float(tcfg->tconfig->rconfig, tcfg->tqueue->rdata);\n\n\t\t/**\n\t\t* empty the queue\n\t\t*/\n\t\t*tcfg->tqueue->q = 0;\n\t\trte_red_mark_queue_empty(tcfg->tqueue->rdata, get_port_ts());\n\n\t\trte_delay_us(tcfg->tvar->wait_usec);\n\n\t\t/**\n\t\t * enqueue one packet to recalculate average queue size\n\t\t */\n\t\tif (rte_red_enqueue(tcfg->tconfig->rconfig,\n\t\t\t\t tcfg->tqueue->rdata,\n\t\t\t\t *tcfg->tqueue->q,\n\t\t\t\t get_port_ts()) == 0) {\n\t\t\t(*tcfg->tqueue->q)++;\n\t\t} else {\n\t\t\tprintf(\"%s:%d: packet enqueued on empty queue was dropped\\n\", __func__, __LINE__);\n\t\t\tresult = FAIL;\n\t\t}\n\n\t\texp_avg = calc_exp_avg_on_empty(avg_before,\n\t\t\t\t\t (1 << *tcfg->tconfig->wq_log2),\n\t\t\t\t\t tcfg->tvar->wait_usec);\n\t\tavg_after = rte_red_get_avg_float(tcfg->tconfig->rconfig,\n\t\t\t\t\t\t tcfg->tqueue->rdata);\n\t\tif (!check_avg(&diff, avg_after, exp_avg, (double)tcfg->tqueue->avg_tolerance))\n\t\t result = FAIL;\n\n\t\tprintf(\"%-15.4lf%-15.4lf%-15.4lf%-15.4lf%-15.4lf%-15s\\n\",\n\t\t avg_before, avg_after, exp_avg, diff,\n\t\t (double)tcfg->tqueue->avg_tolerance,\n\t\t diff <= (double)tcfg->tqueue->avg_tolerance ? \"pass\" : \"fail\");\n\t}\nout:\n\treturn (result);\n}\n\n/**\n * Test F4: functional test 4\n */\nstatic uint32_t ft4_tlevel[] = {1022};\nstatic uint8_t ft4_wq_log2[] = {11};\n\nstatic struct test_rte_red_config ft4_tconfig = {\n\t.rconfig = ft_wrconfig,\n\t.num_cfg = RTE_DIM(ft_wrconfig),\n\t.min_th = 32,\n\t.max_th = 1023,\n\t.wq_log2 = ft4_wq_log2,\n\t.maxp_inv = ft_maxp_inv,\n};\n\nstatic struct test_queue ft4_tqueue = {\n\t.rdata = ft_rtdata,\n\t.num_queues = RTE_DIM(ft_rtdata),\n\t.qconfig = ft_qconfig,\n\t.q = ft_q,\n\t.q_ramp_up = 1000000,\n\t.avg_ramp_up = 1000000,\n\t.avg_tolerance = 0, /* 0 percent */\n\t.drop_tolerance = 50, /* 50 percent */\n};\n\nstatic struct test_config func_test4_config = {\n\t.ifname = \"functional test 4 interface\",\n\t.msg = \"functional test 4 : use one RED configuration,\\n\"\n\t\"\t\t increase average queue size to target level,\\n\"\n\t\"\t\t dequeue all packets until queue is empty,\\n\"\n\t\"\t\t confirm that average queue size is computed correctly while\\n\"\n\t\"\t\t queue is empty for more than 50 sec,\\n\"\n\t\"\t\t (this test takes 52 sec to run)\\n\\n\",\n\t.htxt = \"q avg before \"\n\t\"q avg after \"\n\t\"expected \"\n\t\"difference % \"\n\t\"tolerance % \"\n\t\"result\t \"\n\t\"\\n\",\n\t.tconfig = &ft4_tconfig,\n\t.tqueue = &ft4_tqueue,\n\t.tvar = &ft_tvar,\n\t.tlevel = ft4_tlevel,\n};\n\nstatic enum test_result func_test4(struct test_config *tcfg)\n{\n\tenum test_result result = PASS;\n\tuint64_t time_diff = 0;\n\tuint64_t start = 0;\n\tdouble avg_before = 0.0;\n\tdouble avg_after = 0.0;\n double exp_avg = 0.0;\n double diff = 0.0;\n\n\tprintf(\"%s\", tcfg->msg);\n\n\tif (test_rte_red_init(tcfg) != PASS) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\trte_red_rt_data_init(tcfg->tqueue->rdata);\n\n\tif (increase_actual_qsize(tcfg->tconfig->rconfig,\n\t\t\t\t tcfg->tqueue->rdata,\n\t\t\t\t tcfg->tqueue->q,\n\t\t\t\t *tcfg->tlevel,\n\t\t\t\t tcfg->tqueue->q_ramp_up) != 0) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\tif (increase_average_qsize(tcfg->tconfig->rconfig,\n\t\t\t\t tcfg->tqueue->rdata,\n\t\t\t\t tcfg->tqueue->q,\n\t\t\t\t *tcfg->tlevel,\n\t\t\t\t tcfg->tqueue->avg_ramp_up) != 0) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\tprintf(\"%s\", tcfg->htxt);\n\n\tavg_before = rte_red_get_avg_float(tcfg->tconfig->rconfig, tcfg->tqueue->rdata);\n\n\t/**\n\t * empty the queue\n\t */\n\t*tcfg->tqueue->q = 0;\n\trte_red_mark_queue_empty(tcfg->tqueue->rdata, get_port_ts());\n\n\t/**\n\t * record empty time locally\n\t */\n\tstart = rte_rdtsc();\n\n\tsleep(tcfg->tvar->sleep_sec);\n\n\t/**\n\t * enqueue one packet to recalculate average queue size\n\t */\n\tif (rte_red_enqueue(tcfg->tconfig->rconfig,\n\t\t\t tcfg->tqueue->rdata,\n\t\t\t *tcfg->tqueue->q,\n\t\t\t get_port_ts()) != 0) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\t(*tcfg->tqueue->q)++;\n\n\t/**\n\t * calculate how long queue has been empty\n\t */\n\ttime_diff = ((rte_rdtsc() - start) / tcfg->tvar->clk_freq)\n\t\t * MSEC_PER_SEC;\n\tif (time_diff < MAX_QEMPTY_TIME_MSEC) {\n\t\t/**\n\t\t * this could happen if sleep was interrupted for some reason\n\t\t */\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\t/**\n\t * confirm that average queue size is now at expected level\n\t */\n exp_avg = 0.0;\n\tavg_after = rte_red_get_avg_float(tcfg->tconfig->rconfig, tcfg->tqueue->rdata);\n\tif (!check_avg(&diff, avg_after, exp_avg, (double)tcfg->tqueue->avg_tolerance))\n\t result = FAIL;\n\n\tprintf(\"%-15.4lf%-15.4lf%-15.4lf%-15.4lf%-15.4lf%-15s\\n\",\n\t avg_before, avg_after, exp_avg,\n\t diff, (double)tcfg->tqueue->avg_tolerance,\n\t diff <= (double)tcfg->tqueue->avg_tolerance ? \"pass\" : \"fail\");\nout:\n\treturn (result);\n}\n\n/**\n * Test F5: functional test 5\n */\nstatic uint32_t ft5_tlevel[] = {127};\nstatic uint8_t ft5_wq_log2[] = {9, 8};\nstatic uint8_t ft5_maxp_inv[] = {10, 20};\nstatic struct rte_red_config ft5_config[2];\nstatic struct rte_red ft5_data[4];\nstatic uint32_t ft5_q[4];\nstatic uint32_t ft5_dropped[] = {0, 0, 0, 0};\nstatic uint32_t ft5_enqueued[] = {0, 0, 0, 0};\n\nstatic struct test_rte_red_config ft5_tconfig = {\n\t.rconfig = ft5_config,\n\t.num_cfg = RTE_DIM(ft5_config),\n\t.min_th = 32,\n\t.max_th = 128,\n\t.wq_log2 = ft5_wq_log2,\n\t.maxp_inv = ft5_maxp_inv,\n};\n\nstatic struct test_queue ft5_tqueue = {\n\t.rdata = ft5_data,\n\t.num_queues = RTE_DIM(ft5_data),\n\t.qconfig = ft_qconfig,\n\t.q = ft5_q,\n\t.q_ramp_up = 1000000,\n\t.avg_ramp_up = 1000000,\n\t.avg_tolerance = 5, /* 10 percent */\n\t.drop_tolerance = 50, /* 50 percent */\n};\n\nstruct test_var ft5_tvar = {\n\t.wait_usec = 0,\n\t.num_iterations = 15,\n\t.num_ops = 10000,\n\t.clk_freq = 0,\n\t.dropped = ft5_dropped,\n\t.enqueued = ft5_enqueued,\n\t.sleep_sec = 0,\n};\n\nstatic struct test_config func_test5_config = {\n\t.ifname = \"functional test 5 interface\",\n\t.msg = \"functional test 5 : use several queues (each with its own run-time data),\\n\"\n\t\"\t\t use several RED configurations (such that each configuration is shared by multiple queues),\\n\"\n\t\"\t\t increase average queue size to just below maximum threshold,\\n\"\n\t\"\t\t compare drop rate to drop probability,\\n\"\n\t\"\t\t (this is a larger scale version of functional test 2)\\n\\n\",\n\t.htxt = \"queue \"\n\t\"config \"\n\t\"avg queue size \"\n\t\"min threshold \"\n\t\"max threshold \"\n\t\"drop prob % \"\n\t\"drop rate % \"\n\t\"diff % \"\n\t\"tolerance % \"\n\t\"\\n\",\n\t.tconfig = &ft5_tconfig,\n\t.tqueue = &ft5_tqueue,\n\t.tvar = &ft5_tvar,\n\t.tlevel = ft5_tlevel,\n};\n\nstatic enum test_result func_test5(struct test_config *tcfg)\n{\n\tenum test_result result = PASS;\n\tuint32_t j = 0;\n\n\tprintf(\"%s\", tcfg->msg);\n\n\tif (test_rte_red_init(tcfg) != PASS) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\tprintf(\"%s\", tcfg->htxt);\n\n\tfor (j = 0; j < tcfg->tqueue->num_queues; j++) {\n\t\trte_red_rt_data_init(&tcfg->tqueue->rdata[j]);\n\t\ttcfg->tqueue->q[j] = 0;\n\n\t\tif (increase_actual_qsize(&tcfg->tconfig->rconfig[tcfg->tqueue->qconfig[j]],\n\t\t\t\t\t &tcfg->tqueue->rdata[j],\n\t\t\t\t\t &tcfg->tqueue->q[j],\n\t\t\t\t\t *tcfg->tlevel,\n\t\t\t\t\t tcfg->tqueue->q_ramp_up) != 0) {\n\t\t\tresult = FAIL;\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (increase_average_qsize(&tcfg->tconfig->rconfig[tcfg->tqueue->qconfig[j]],\n\t\t\t\t\t &tcfg->tqueue->rdata[j],\n\t\t\t\t\t &tcfg->tqueue->q[j],\n\t\t\t\t\t *tcfg->tlevel,\n\t\t\t\t\t tcfg->tqueue->avg_ramp_up) != 0) {\n\t\t\tresult = FAIL;\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\tfor (j = 0; j < tcfg->tqueue->num_queues; j++) {\n\t\tuint32_t avg = 0;\n\t\tdouble drop_rate = 0.0;\n\t\tdouble drop_prob = 0.0;\n\t\tdouble diff = 0.0;\n\n\t\ttcfg->tvar->dropped[j] = 0;\n\t\ttcfg->tvar->enqueued[j] = 0;\n\n\t\tenqueue_dequeue_func(&tcfg->tconfig->rconfig[tcfg->tqueue->qconfig[j]],\n\t\t\t\t &tcfg->tqueue->rdata[j],\n\t\t\t\t &tcfg->tqueue->q[j],\n\t\t\t\t tcfg->tvar->num_ops,\n\t\t\t\t &tcfg->tvar->enqueued[j],\n\t\t\t\t &tcfg->tvar->dropped[j]);\n\n\t\tavg = rte_red_get_avg_int(&tcfg->tconfig->rconfig[tcfg->tqueue->qconfig[j]],\n\t\t\t\t\t &tcfg->tqueue->rdata[j]);\n\t\tif (avg != *tcfg->tlevel)\n\t\t\tresult = FAIL;\n\n\t\tdrop_rate = calc_drop_rate(tcfg->tvar->enqueued[j],tcfg->tvar->dropped[j]);\n\t\tdrop_prob = calc_drop_prob(tcfg->tconfig->min_th, tcfg->tconfig->max_th,\n\t\t\t\t\t tcfg->tconfig->maxp_inv[tcfg->tqueue->qconfig[j]],\n\t\t\t\t\t *tcfg->tlevel);\n\t\tif (!check_drop_rate(&diff, drop_rate, drop_prob, (double)tcfg->tqueue->drop_tolerance))\n\t\t result = FAIL;\n\n\t\tprintf(\"%-15u%-15u%-15u%-15u%-15u%-15.4lf%-15.4lf%-15.4lf%-15.4lf\\n\",\n\t\t j, tcfg->tqueue->qconfig[j], avg,\n\t\t tcfg->tconfig->min_th, tcfg->tconfig->max_th,\n\t\t drop_prob * 100.0, drop_rate * 100.0,\n\t\t diff, (double)tcfg->tqueue->drop_tolerance);\n\t}\nout:\n\treturn (result);\n}\n\n/**\n * Test F6: functional test 6\n */\nstatic uint32_t ft6_tlevel[] = {1022};\nstatic uint8_t ft6_wq_log2[] = {9, 8};\nstatic uint8_t ft6_maxp_inv[] = {10, 20};\nstatic struct rte_red_config ft6_config[2];\nstatic struct rte_red ft6_data[4];\nstatic uint32_t ft6_q[4];\n\nstatic struct test_rte_red_config ft6_tconfig = {\n\t.rconfig = ft6_config,\n\t.num_cfg = RTE_DIM(ft6_config),\n\t.min_th = 32,\n\t.max_th = 1023,\n\t.wq_log2 = ft6_wq_log2,\n\t.maxp_inv = ft6_maxp_inv,\n};\n\nstatic struct test_queue ft6_tqueue = {\n\t.rdata = ft6_data,\n\t.num_queues = RTE_DIM(ft6_data),\n\t.qconfig = ft_qconfig,\n\t.q = ft6_q,\n\t.q_ramp_up = 1000000,\n\t.avg_ramp_up = 1000000,\n\t.avg_tolerance = 5, /* 10 percent */\n\t.drop_tolerance = 50, /* 50 percent */\n};\n\nstatic struct test_config func_test6_config = {\n\t.ifname = \"functional test 6 interface\",\n\t.msg = \"functional test 6 : use several queues (each with its own run-time data),\\n\"\n\t\"\t\t use several RED configurations (such that each configuration is sharte_red by multiple queues),\\n\"\n\t\"\t\t increase average queue size to target level,\\n\"\n\t\"\t\t dequeue all packets until queue is empty,\\n\"\n\t\"\t\t confirm that average queue size is computed correctly while queue is empty\\n\"\n\t\"\t\t (this is a larger scale version of functional test 3)\\n\\n\",\n\t.htxt = \"queue \"\n\t\"config \"\n\t\"q avg before \"\n\t\"q avg after \"\n\t\"expected \"\n\t\"difference % \"\n\t\"tolerance % \"\n\t\"result\t \"\"\\n\",\n\t.tconfig = &ft6_tconfig,\n\t.tqueue = &ft6_tqueue,\n\t.tvar = &ft_tvar,\n\t.tlevel = ft6_tlevel,\n};\n\nstatic enum test_result func_test6(struct test_config *tcfg)\n{\n\tenum test_result result = PASS;\n\tuint32_t j = 0;\n\n\tprintf(\"%s\", tcfg->msg);\n\tif (test_rte_red_init(tcfg) != PASS) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\tprintf(\"%s\", tcfg->htxt);\n\n\tfor (j = 0; j < tcfg->tqueue->num_queues; j++) {\n\t\trte_red_rt_data_init(&tcfg->tqueue->rdata[j]);\n\t\ttcfg->tqueue->q[j] = 0;\n\n\t\tif (increase_actual_qsize(&tcfg->tconfig->rconfig[tcfg->tqueue->qconfig[j]],\n\t\t\t\t\t &tcfg->tqueue->rdata[j],\n\t\t\t\t\t &tcfg->tqueue->q[j],\n\t\t\t\t\t *tcfg->tlevel,\n\t\t\t\t\t tcfg->tqueue->q_ramp_up) != 0) {\n\t\t\tresult = FAIL;\n\t\t\tgoto out;\n\t\t}\n\t\tif (increase_average_qsize(&tcfg->tconfig->rconfig[tcfg->tqueue->qconfig[j]],\n\t\t\t\t\t &tcfg->tqueue->rdata[j],\n\t\t\t\t\t &tcfg->tqueue->q[j],\n\t\t\t\t\t *tcfg->tlevel,\n\t\t\t\t\t tcfg->tqueue->avg_ramp_up) != 0) {\n\t\t\tresult = FAIL;\n\t\t\tgoto out;\n\t\t}\n\t}\n\tfor (j = 0; j < tcfg->tqueue->num_queues; j++) {\n\t\tdouble avg_before = 0;\n\t\tdouble avg_after = 0;\n\t\tdouble exp_avg = 0;\n\t\tdouble diff = 0.0;\n\n\t\tavg_before = rte_red_get_avg_float(&tcfg->tconfig->rconfig[tcfg->tqueue->qconfig[j]],\n\t\t\t\t\t\t &tcfg->tqueue->rdata[j]);\n\n\t\t/**\n\t\t * empty the queue\n\t\t */\n\t\ttcfg->tqueue->q[j] = 0;\n\t\trte_red_mark_queue_empty(&tcfg->tqueue->rdata[j], get_port_ts());\n\t\trte_delay_us(tcfg->tvar->wait_usec);\n\n\t\t/**\n\t\t * enqueue one packet to recalculate average queue size\n\t\t */\n\t\tif (rte_red_enqueue(&tcfg->tconfig->rconfig[tcfg->tqueue->qconfig[j]],\n\t\t\t\t &tcfg->tqueue->rdata[j],\n\t\t\t\t tcfg->tqueue->q[j],\n\t\t\t\t get_port_ts()) == 0) {\n\t\t\ttcfg->tqueue->q[j]++;\n\t\t} else {\n\t\t\tprintf(\"%s:%d: packet enqueued on empty queue was dropped\\n\", __func__, __LINE__);\n\t\t\tresult = FAIL;\n\t\t}\n\n\t\texp_avg = calc_exp_avg_on_empty(avg_before,\n\t\t\t\t(1 << tcfg->tconfig->wq_log2[tcfg->tqueue->qconfig[j]]),\n\t\t\t\ttcfg->tvar->wait_usec);\n\t\tavg_after = rte_red_get_avg_float(&tcfg->tconfig->rconfig[tcfg->tqueue->qconfig[j]],\n\t\t\t\t\t\t&tcfg->tqueue->rdata[j]);\n\t\tif (!check_avg(&diff, avg_after, exp_avg, (double)tcfg->tqueue->avg_tolerance))\n\t\t result = FAIL;\n\n\t\tprintf(\"%-15u%-15u%-15.4lf%-15.4lf%-15.4lf%-15.4lf%-15.4lf%-15s\\n\",\n\t\t j, tcfg->tqueue->qconfig[j], avg_before, avg_after,\n\t\t exp_avg, diff, (double)tcfg->tqueue->avg_tolerance,\n\t\t diff <= tcfg->tqueue->avg_tolerance ? \"pass\" : \"fail\");\n\t}\nout:\n\treturn (result);\n}\n\n/**\n * setup default values for the performance test structures\n */\nstatic struct rte_red_config pt_wrconfig[1];\nstatic struct rte_red pt_rtdata[1];\nstatic uint8_t pt_wq_log2[] = {9};\nstatic uint8_t pt_maxp_inv[] = {10};\nstatic uint32_t pt_qconfig[] = {0};\nstatic uint32_t pt_q[] = {0};\nstatic uint32_t pt_dropped[] = {0};\nstatic uint32_t pt_enqueued[] = {0};\n\nstatic struct test_rte_red_config pt_tconfig = {\n\t.rconfig = pt_wrconfig,\n\t.num_cfg = RTE_DIM(pt_wrconfig),\n\t.wq_log2 = pt_wq_log2,\n\t.min_th = 32,\n\t.max_th = 128,\n\t.maxp_inv = pt_maxp_inv,\n};\n\nstatic struct test_queue pt_tqueue = {\n\t.rdata = pt_rtdata,\n\t.num_queues = RTE_DIM(pt_rtdata),\n\t.qconfig = pt_qconfig,\n\t.q = pt_q,\n\t.q_ramp_up = 1000000,\n\t.avg_ramp_up = 1000000,\n\t.avg_tolerance = 5, /* 10 percent */\n\t.drop_tolerance = 50, /* 50 percent */\n};\n\n/**\n * enqueue/dequeue packets\n */\nstatic void enqueue_dequeue_perf(struct rte_red_config *red_cfg,\n\t\t\t\t struct rte_red *red,\n\t\t\t\t uint32_t *q,\n\t\t\t\t uint32_t num_ops,\n\t\t\t\t uint32_t *enqueued,\n\t\t\t\t uint32_t *dropped,\n\t\t\t\t struct rdtsc_prof *prof)\n{\n\tuint32_t i = 0;\n\n\tfor (i = 0; i < num_ops; i++) {\n\t\tuint64_t ts = 0;\n\t\tint ret = 0;\n\t\t/**\n\t\t * enqueue\n\t\t */\n\t\tts = get_port_ts();\n\t\trdtsc_prof_start(prof);\n\t\tret = rte_red_enqueue(red_cfg, red, *q, ts );\n\t\trdtsc_prof_end(prof);\n\t\tif (ret == 0)\n\t\t\t(*enqueued)++;\n\t\telse\n\t\t\t(*dropped)++;\n\t}\n}\n\n/**\n * Setup test structures for tests P1, P2, P3\n * performance tests 1, 2 and 3\n */\nstatic uint32_t pt1_tlevel[] = {16};\nstatic uint32_t pt2_tlevel[] = {80};\nstatic uint32_t pt3_tlevel[] = {144};\n\nstatic struct test_var perf1_tvar = {\n\t.wait_usec = 0,\n\t.num_iterations = 15,\n\t.num_ops = 50000000,\n\t.clk_freq = 0,\n\t.dropped = pt_dropped,\n\t.enqueued = pt_enqueued,\n\t.sleep_sec = 0\n};\n\nstatic struct test_config perf1_test1_config = {\n\t.ifname = \"performance test 1 interface\",\n\t.msg = \"performance test 1 : use one RED configuration,\\n\"\n\t\"\t\t set actual and average queue sizes to level below min threshold,\\n\"\n\t\"\t\t measure enqueue performance\\n\\n\",\n\t.tconfig = &pt_tconfig,\n\t.tqueue = &pt_tqueue,\n\t.tvar = &perf1_tvar,\n\t.tlevel = pt1_tlevel,\n};\n\nstatic struct test_config perf1_test2_config = {\n\t.ifname = \"performance test 2 interface\",\n\t.msg = \"performance test 2 : use one RED configuration,\\n\"\n\t\"\t\t set actual and average queue sizes to level in between min and max thresholds,\\n\"\n\t\"\t\t measure enqueue performance\\n\\n\",\n\t.tconfig = &pt_tconfig,\n\t.tqueue = &pt_tqueue,\n\t.tvar = &perf1_tvar,\n\t.tlevel = pt2_tlevel,\n};\n\nstatic struct test_config perf1_test3_config = {\n\t.ifname = \"performance test 3 interface\",\n\t.msg = \"performance test 3 : use one RED configuration,\\n\"\n\t\"\t\t set actual and average queue sizes to level above max threshold,\\n\"\n\t\"\t\t measure enqueue performance\\n\\n\",\n\t.tconfig = &pt_tconfig,\n\t.tqueue = &pt_tqueue,\n\t.tvar = &perf1_tvar,\n\t.tlevel = pt3_tlevel,\n};\n\n/**\n * Performance test function to measure enqueue performance.\n * This runs performance tests 1, 2 and 3\n */\nstatic enum test_result perf1_test(struct test_config *tcfg)\n{\n\tenum test_result result = PASS;\n\tstruct rdtsc_prof prof = {0, 0, 0, 0, 0.0, NULL};\n\tuint32_t total = 0;\n\n\tprintf(\"%s\", tcfg->msg);\n\n\trdtsc_prof_init(&prof, \"enqueue\");\n\n\tif (test_rte_red_init(tcfg) != PASS) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\t/**\n\t * set average queue size to target level\n\t */\n\t*tcfg->tqueue->q = *tcfg->tlevel;\n\n\t/**\n\t * initialize the rte_red run time data structure\n\t */\n\trte_red_rt_data_init(tcfg->tqueue->rdata);\n\n\t/**\n\t * set the queue average\n\t */\n\trte_red_set_avg_int(tcfg->tconfig->rconfig, tcfg->tqueue->rdata, *tcfg->tlevel);\n\tif (rte_red_get_avg_int(tcfg->tconfig->rconfig, tcfg->tqueue->rdata)\n\t != *tcfg->tlevel) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\tenqueue_dequeue_perf(tcfg->tconfig->rconfig,\n\t\t\t tcfg->tqueue->rdata,\n\t\t\t tcfg->tqueue->q,\n\t\t\t tcfg->tvar->num_ops,\n\t\t\t tcfg->tvar->enqueued,\n\t\t\t tcfg->tvar->dropped,\n\t\t\t &prof);\n\n\ttotal = *tcfg->tvar->enqueued + *tcfg->tvar->dropped;\n\n\tprintf(\"\\ntotal: %u, enqueued: %u (%.2lf%%), dropped: %u (%.2lf%%)\\n\", total,\n\t *tcfg->tvar->enqueued, ((double)(*tcfg->tvar->enqueued) / (double)total) * 100.0,\n\t *tcfg->tvar->dropped, ((double)(*tcfg->tvar->dropped) / (double)total) * 100.0);\n\n\trdtsc_prof_print(&prof);\nout:\n\treturn (result);\n}\n\n/**\n * Setup test structures for tests P4, P5, P6\n * performance tests 4, 5 and 6\n */\nstatic uint32_t pt4_tlevel[] = {16};\nstatic uint32_t pt5_tlevel[] = {80};\nstatic uint32_t pt6_tlevel[] = {144};\n\nstatic struct test_var perf2_tvar = {\n\t.wait_usec = 500,\n\t.num_iterations = 10000,\n\t.num_ops = 10000,\n\t.dropped = pt_dropped,\n\t.enqueued = pt_enqueued,\n\t.sleep_sec = 0\n};\n\nstatic struct test_config perf2_test4_config = {\n\t.ifname = \"performance test 4 interface\",\n\t.msg = \"performance test 4 : use one RED configuration,\\n\"\n\t\"\t\t set actual and average queue sizes to level below min threshold,\\n\"\n\t\"\t\t dequeue all packets until queue is empty,\\n\"\n\t\"\t\t measure enqueue performance when queue is empty\\n\\n\",\n\t.htxt = \"iteration \"\n\t\"q avg before \"\n\t\"q avg after \"\n\t\"expected \"\n\t\"difference % \"\n\t\"tolerance % \"\n\t\"result\t \"\"\\n\",\n\t.tconfig = &pt_tconfig,\n\t.tqueue = &pt_tqueue,\n\t.tvar = &perf2_tvar,\n\t.tlevel = pt4_tlevel,\n};\n\nstatic struct test_config perf2_test5_config = {\n\t.ifname = \"performance test 5 interface\",\n\t.msg = \"performance test 5 : use one RED configuration,\\n\"\n\t\"\t\t set actual and average queue sizes to level in between min and max thresholds,\\n\"\n\t\"\t\t dequeue all packets until queue is empty,\\n\"\n\t\"\t\t measure enqueue performance when queue is empty\\n\\n\",\n\t.htxt = \"iteration \"\n\t\"q avg before \"\n\t\"q avg after \"\n\t\"expected \"\n\t\"difference \"\n\t\"tolerance \"\n\t\"result\t \"\"\\n\",\n\t.tconfig = &pt_tconfig,\n\t.tqueue = &pt_tqueue,\n\t.tvar = &perf2_tvar,\n\t.tlevel = pt5_tlevel,\n};\n\nstatic struct test_config perf2_test6_config = {\n\t.ifname = \"performance test 6 interface\",\n\t.msg = \"performance test 6 : use one RED configuration,\\n\"\n\t\"\t\t set actual and average queue sizes to level above max threshold,\\n\"\n\t\"\t\t dequeue all packets until queue is empty,\\n\"\n\t\"\t\t measure enqueue performance when queue is empty\\n\\n\",\n\t.htxt = \"iteration \"\n\t\"q avg before \"\n\t\"q avg after \"\n\t\"expected \"\n\t\"difference % \"\n\t\"tolerance % \"\n\t\"result\t \"\"\\n\",\n\t.tconfig = &pt_tconfig,\n\t.tqueue = &pt_tqueue,\n\t.tvar = &perf2_tvar,\n\t.tlevel = pt6_tlevel,\n};\n\n/**\n * Performance test function to measure enqueue performance when the\n * queue is empty. This runs performance tests 4, 5 and 6\n */\nstatic enum test_result perf2_test(struct test_config *tcfg)\n{\n\tenum test_result result = PASS;\n\tstruct rdtsc_prof prof = {0, 0, 0, 0, 0.0, NULL};\n\tuint32_t total = 0;\n\tuint32_t i = 0;\n\n\tprintf(\"%s\", tcfg->msg);\n\n\trdtsc_prof_init(&prof, \"enqueue\");\n\n\tif (test_rte_red_init(tcfg) != PASS) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\tprintf(\"%s\", tcfg->htxt);\n\n\tfor (i = 0; i < tcfg->tvar->num_iterations; i++) {\n\t\tuint32_t count = 0;\n\t\tuint64_t ts = 0;\n\t\tdouble avg_before = 0;\n\t\tint ret = 0;\n\n\t\t/**\n\t\t * set average queue size to target level\n\t\t */\n\t\t*tcfg->tqueue->q = *tcfg->tlevel;\n\t\tcount = (*tcfg->tqueue->rdata).count;\n\n\t\t/**\n\t\t * initialize the rte_red run time data structure\n\t\t */\n\t\trte_red_rt_data_init(tcfg->tqueue->rdata);\n\t\t(*tcfg->tqueue->rdata).count = count;\n\n\t\t/**\n\t\t * set the queue average\n\t\t */\n\t\trte_red_set_avg_int(tcfg->tconfig->rconfig, tcfg->tqueue->rdata, *tcfg->tlevel);\n\t\tavg_before = rte_red_get_avg_float(tcfg->tconfig->rconfig, tcfg->tqueue->rdata);\n\t\tif ((avg_before < *tcfg->tlevel) || (avg_before > *tcfg->tlevel)) {\n\t\t\tresult = FAIL;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/**\n\t\t * empty the queue\n\t\t */\n\t\t*tcfg->tqueue->q = 0;\n\t\trte_red_mark_queue_empty(tcfg->tqueue->rdata, get_port_ts());\n\n\t\t/**\n\t\t * wait for specified period of time\n\t\t */\n\t\trte_delay_us(tcfg->tvar->wait_usec);\n\n\t\t/**\n\t\t * measure performance of enqueue operation while queue is empty\n\t\t */\n\t\tts = get_port_ts();\n\t\trdtsc_prof_start(&prof);\n\t\tret = rte_red_enqueue(tcfg->tconfig->rconfig, tcfg->tqueue->rdata,\n\t\t\t\t *tcfg->tqueue->q, ts );\n\t\trdtsc_prof_end(&prof);\n\n\t\t/**\n\t\t * gather enqueued/dropped statistics\n\t\t */\n\t\tif (ret == 0)\n\t\t\t(*tcfg->tvar->enqueued)++;\n\t\telse\n\t\t\t(*tcfg->tvar->dropped)++;\n\n\t\t/**\n\t\t * on first and last iteration, confirm that\n\t\t * average queue size was computed correctly\n\t\t */\n\t\tif ((i == 0) || (i == tcfg->tvar->num_iterations - 1)) {\n\t\t\tdouble avg_after = 0;\n\t\t\tdouble exp_avg = 0;\n\t\t\tdouble diff = 0.0;\n\t\t\tint ok = 0;\n\n\t\t\tavg_after = rte_red_get_avg_float(tcfg->tconfig->rconfig, tcfg->tqueue->rdata);\n\t\t\texp_avg = calc_exp_avg_on_empty(avg_before,\n\t\t\t\t\t\t (1 << *tcfg->tconfig->wq_log2),\n\t\t\t\t\t\t tcfg->tvar->wait_usec);\n\t\t\tif (check_avg(&diff, avg_after, exp_avg, (double)tcfg->tqueue->avg_tolerance))\n\t\t \tok = 1;\n\t\t\tprintf(\"%-15u%-15.4lf%-15.4lf%-15.4lf%-15.4lf%-15.4lf%-15s\\n\",\n\t\t\t\ti, avg_before, avg_after, exp_avg, diff,\n\t\t\t\t(double)tcfg->tqueue->avg_tolerance, ok ? \"pass\" : \"fail\");\n\t\t\tif (!ok) {\n\t\t\t\tresult = FAIL;\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\t}\n\ttotal = *tcfg->tvar->enqueued + *tcfg->tvar->dropped;\n\tprintf(\"\\ntotal: %u, enqueued: %u (%.2lf%%), dropped: %u (%.2lf%%)\\n\", total,\n\t *tcfg->tvar->enqueued, ((double)(*tcfg->tvar->enqueued) / (double)total) * 100.0,\n\t *tcfg->tvar->dropped, ((double)(*tcfg->tvar->dropped) / (double)total) * 100.0);\n\n\trdtsc_prof_print(&prof);\nout:\n\treturn (result);\n}\n\n/**\n * setup default values for overflow test structures\n */\nstatic uint32_t avg_max = 0;\nstatic uint32_t avg_max_bits = 0;\n\nstatic struct rte_red_config ovfl_wrconfig[1];\nstatic struct rte_red ovfl_rtdata[1];\nstatic uint8_t ovfl_maxp_inv[] = {10};\nstatic uint32_t ovfl_qconfig[] = {0, 0, 1, 1};\nstatic uint32_t ovfl_q[] ={0};\nstatic uint32_t ovfl_dropped[] ={0};\nstatic uint32_t ovfl_enqueued[] ={0};\nstatic uint32_t ovfl_tlevel[] = {1023};\nstatic uint8_t ovfl_wq_log2[] = {12};\n\nstatic struct test_rte_red_config ovfl_tconfig = {\n\t.rconfig = ovfl_wrconfig,\n\t.num_cfg = RTE_DIM(ovfl_wrconfig),\n\t.wq_log2 = ovfl_wq_log2,\n\t.min_th = 32,\n\t.max_th = 1023,\n\t.maxp_inv = ovfl_maxp_inv,\n};\n\nstatic struct test_queue ovfl_tqueue = {\n\t.rdata = ovfl_rtdata,\n\t.num_queues = RTE_DIM(ovfl_rtdata),\n\t.qconfig = ovfl_qconfig,\n\t.q = ovfl_q,\n\t.q_ramp_up = 1000000,\n\t.avg_ramp_up = 1000000,\n\t.avg_tolerance = 5, /* 10 percent */\n\t.drop_tolerance = 50, /* 50 percent */\n};\n\nstatic struct test_var ovfl_tvar = {\n\t.wait_usec = 10000,\n\t.num_iterations = 1,\n\t.num_ops = 10000,\n\t.clk_freq = 0,\n\t.dropped = ovfl_dropped,\n\t.enqueued = ovfl_enqueued,\n\t.sleep_sec = 0\n};\n\nstatic void ovfl_check_avg(uint32_t avg)\n{\n\tif (avg > avg_max) {\n\t\tdouble avg_log = 0;\n\t\tuint32_t bits = 0;\n\t\tavg_max = avg;\n\t\tavg_log = log(((double)avg_max));\n\t\tavg_log = avg_log / log(2.0);\n\t\tbits = (uint32_t)ceil(avg_log);\n\t\tif (bits > avg_max_bits)\n\t\t\tavg_max_bits = bits;\n\t}\n}\n\nstatic struct test_config ovfl_test1_config = {\n\t.ifname = \"queue avergage overflow test interface\",\n\t.msg = \"overflow test 1 : use one RED configuration,\\n\"\n\t\"\t\t increase average queue size to target level,\\n\"\n\t\"\t\t check maximum number of bits requirte_red to represent avg_s\\n\\n\",\n\t.htxt = \"avg queue size \"\n\t\"wq_log2 \"\n\t\"fraction bits \"\n\t\"max queue avg \"\n\t\"num bits \"\n\t\"enqueued \"\n\t\"dropped \"\n\t\"drop prob % \"\n\t\"drop rate % \"\n\t\"\\n\",\n\t.tconfig = &ovfl_tconfig,\n\t.tqueue = &ovfl_tqueue,\n\t.tvar = &ovfl_tvar,\n\t.tlevel = ovfl_tlevel,\n};\n\nstatic enum test_result ovfl_test1(struct test_config *tcfg)\n{\n\tenum test_result result = PASS;\n\tuint32_t avg = 0;\n\tuint32_t i = 0;\n\tdouble drop_rate = 0.0;\n\tdouble drop_prob = 0.0;\n\tdouble diff = 0.0;\n\tint ret = 0;\n\n\tprintf(\"%s\", tcfg->msg);\n\n\tif (test_rte_red_init(tcfg) != PASS) {\n\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\t/**\n\t * reset rte_red run-time data\n\t */\n\trte_red_rt_data_init(tcfg->tqueue->rdata);\n\n\t/**\n\t * increase actual queue size\n\t */\n\tfor (i = 0; i < tcfg->tqueue->q_ramp_up; i++) {\n\t\tret = rte_red_enqueue(tcfg->tconfig->rconfig, tcfg->tqueue->rdata,\n\t\t\t\t *tcfg->tqueue->q, get_port_ts());\n\n\t\tif (ret == 0) {\n\t\t\tif (++(*tcfg->tqueue->q) >= *tcfg->tlevel)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\t/**\n\t * enqueue\n\t */\n\tfor (i = 0; i < tcfg->tqueue->avg_ramp_up; i++) {\n\t\tret = rte_red_enqueue(tcfg->tconfig->rconfig, tcfg->tqueue->rdata,\n\t\t\t\t *tcfg->tqueue->q, get_port_ts());\n\t\tovfl_check_avg((*tcfg->tqueue->rdata).avg);\n\t\tavg = rte_red_get_avg_int(tcfg->tconfig->rconfig, tcfg->tqueue->rdata);\n\t\tif (avg == *tcfg->tlevel) {\n\t\t\tif (ret == 0)\n\t\t\t\t(*tcfg->tvar->enqueued)++;\n\t\t\telse\n\t\t\t\t(*tcfg->tvar->dropped)++;\n\t\t}\n\t}\n\n\t/**\n\t * check if target average queue size has been reached\n\t */\n\tavg = rte_red_get_avg_int(tcfg->tconfig->rconfig, tcfg->tqueue->rdata);\n\tif (avg != *tcfg->tlevel) {\n\t\tresult = FAIL;\n\t\tgoto out;\n\t}\n\n\t/**\n\t * check drop rate against drop probability\n\t */\n\tdrop_rate = calc_drop_rate(*tcfg->tvar->enqueued, *tcfg->tvar->dropped);\n\tdrop_prob = calc_drop_prob(tcfg->tconfig->min_th,\n\t\t\t\t tcfg->tconfig->max_th,\n\t\t\t\t *tcfg->tconfig->maxp_inv,\n\t\t\t\t *tcfg->tlevel);\n\tif (!check_drop_rate(&diff, drop_rate, drop_prob, (double)tcfg->tqueue->drop_tolerance))\n\t result = FAIL;\n\n\tprintf(\"%s\", tcfg->htxt);\n\n\tprintf(\"%-16u%-9u%-15u0x%08x %-10u%-10u%-10u%-13.2lf%-13.2lf\\n\",\n\t avg, *tcfg->tconfig->wq_log2, RTE_RED_SCALING,\n\t avg_max, avg_max_bits,\n\t *tcfg->tvar->enqueued, *tcfg->tvar->dropped,\n\t drop_prob * 100.0, drop_rate * 100.0);\nout:\n\treturn (result);\n}\n\n/**\n * define the functional and performance tests to be executed\n */\nstruct tests func_tests[] = {\n\t{ &func_test1_config, func_test1 },\n\t{ &func_test2_config, func_test2 },\n\t{ &func_test3_config, func_test3 },\n\t{ &func_test4_config, func_test4 },\n\t{ &func_test5_config, func_test5 },\n\t{ &func_test6_config, func_test6 },\n\t{ &ovfl_test1_config, ovfl_test1 },\n};\n\nstruct tests perf_tests[] = {\n\t{ &perf1_test1_config, perf1_test },\n\t{ &perf1_test2_config, perf1_test },\n\t{ &perf1_test3_config, perf1_test },\n\t{ &perf2_test4_config, perf2_test },\n\t{ &perf2_test5_config, perf2_test },\n\t{ &perf2_test6_config, perf2_test },\n};\n\n/**\n * function to execute the required_red tests\n */\nstatic void run_tests(struct tests *test_type, uint32_t test_count, uint32_t *num_tests, uint32_t *num_pass)\n{\n\tenum test_result result = PASS;\n\tuint32_t i = 0;\n\n\tfor (i = 0; i < test_count; i++) {\n\t\tprintf(\"\\n--------------------------------------------------------------------------------\\n\");\n\t\tresult = test_type[i].testfn(test_type[i].testcfg);\n\t\t(*num_tests)++;\n\t\tif (result == PASS) {\n\t\t\t(*num_pass)++;\n\t\t\t\tprintf(\"--------------------------------------------------------------------------\\n\");\n\t\t} else {\n\t\t\tprintf(\"--------------------------------------------------------------------------\\n\");\n\t\t}\n\t}\n\treturn;\n}\n\n/**\n * check if functions accept invalid parameters\n *\n * First, all functions will be called without initialized RED\n * Then, all of them will be called with NULL/invalid parameters\n *\n * Some functions are not tested as they are performance-critical and thus\n * don't do any parameter checking.\n */\nstatic int\ntest_invalid_parameters(void)\n{\n\tstruct rte_red_config config;\n\n\tif (rte_red_rt_data_init(NULL) == 0) {\n\t\tprintf(\"rte_red_rt_data_init should have failed!\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_red_config_init(NULL, 0, 0, 0, 0) == 0) {\n\t\tprintf(\"rte_red_config_init should have failed!\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_red_rt_data_init(NULL) == 0) {\n\t\tprintf(\"rte_red_rt_data_init should have failed!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* NULL config */\n\tif (rte_red_config_init(NULL, 0, 0, 0, 0) == 0) {\n\t\tprintf(\"%i: rte_red_config_init should have failed!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\t/* min_treshold == max_treshold */\n\tif (rte_red_config_init(&config, 0, 1, 1, 0) == 0) {\n\t\tprintf(\"%i: rte_red_config_init should have failed!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\t/* min_treshold > max_treshold */\n\tif (rte_red_config_init(&config, 0, 2, 1, 0) == 0) {\n\t\tprintf(\"%i: rte_red_config_init should have failed!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\t/* wq_log2 > RTE_RED_WQ_LOG2_MAX */\n\tif (rte_red_config_init(&config,\n\t\t\tRTE_RED_WQ_LOG2_MAX + 1, 1, 2, 0) == 0) {\n\t\tprintf(\"%i: rte_red_config_init should have failed!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\t/* wq_log2 < RTE_RED_WQ_LOG2_MIN */\n\tif (rte_red_config_init(&config,\n\t\t\tRTE_RED_WQ_LOG2_MIN - 1, 1, 2, 0) == 0) {\n\t\tprintf(\"%i: rte_red_config_init should have failed!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\t/* maxp_inv > RTE_RED_MAXP_INV_MAX */\n\tif (rte_red_config_init(&config,\n\t\t\tRTE_RED_WQ_LOG2_MIN, 1, 2, RTE_RED_MAXP_INV_MAX + 1) == 0) {\n\t\tprintf(\"%i: rte_red_config_init should have failed!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\t/* maxp_inv < RTE_RED_MAXP_INV_MIN */\n\tif (rte_red_config_init(&config,\n\t\t\tRTE_RED_WQ_LOG2_MIN, 1, 2, RTE_RED_MAXP_INV_MIN - 1) == 0) {\n\t\tprintf(\"%i: rte_red_config_init should have failed!\\n\", __LINE__);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntest_red(void)\n{\n\tuint32_t num_tests = 0;\n\tuint32_t num_pass = 0;\n\tint ret = 0;\n\n\tif (test_invalid_parameters() < 0)\n\t\treturn -1;\n\n\trun_tests(func_tests, RTE_DIM(func_tests), &num_tests, &num_pass);\n\trun_tests(perf_tests, RTE_DIM(perf_tests), &num_tests, &num_pass);\n\n\tif (num_pass == num_tests) {\n\t\tprintf(\"[total: %u, pass: %u]\\n\", num_tests, num_pass);\n\t\tret = 0;\n\t} else {\n\t\tprintf(\"[total: %u, pass: %u, fail: %u]\\n\", num_tests, num_pass, num_tests - num_pass);\n\t\tret = -1;\n\t}\n\treturn (ret);\n}\n\nstatic struct test_command red_cmd = {\n\t.command = \"red_autotest\",\n\t.callback = test_red,\n};\nREGISTER_TEST_COMMAND(red_cmd);\n" }, { "path": "app/test/test_reorder.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"test.h\"\n#include \"stdio.h\"\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#define BURST 32\n#define REORDER_BUFFER_SIZE 16384\n#define NUM_MBUFS (2*REORDER_BUFFER_SIZE)\n#define REORDER_BUFFER_SIZE_INVALID 2049\n\nstruct reorder_unittest_params {\n\tstruct rte_mempool *p;\n\tstruct rte_reorder_buffer *b;\n};\n\nstatic struct reorder_unittest_params default_params = {\n\t.p = NULL,\n\t.b = NULL\n};\n\nstatic struct reorder_unittest_params *test_params = &default_params;\n\nstatic int\ntest_reorder_create(void)\n{\n\tstruct rte_reorder_buffer *b = NULL;\n\n\tb = rte_reorder_create(NULL, rte_socket_id(), REORDER_BUFFER_SIZE);\n\tTEST_ASSERT((b == NULL) && (rte_errno == EINVAL),\n\t\t\t\"No error on create() with NULL name\");\n\n\tb = rte_reorder_create(\"PKT\", rte_socket_id(), REORDER_BUFFER_SIZE_INVALID);\n\tTEST_ASSERT((b == NULL) && (rte_errno == EINVAL),\n\t\t\t\"No error on create() with invalid buffer size param.\");\n\n\tb = rte_reorder_create(\"PKT_RO1\", rte_socket_id(), REORDER_BUFFER_SIZE);\n\tprintf(\"DEBUG: b= %p, orig_b= %p\\n\", b, test_params->b);\n\tTEST_ASSERT_EQUAL(b, test_params->b,\n\t\t\t\"New reorder instance created with already existing name\");\n\n\treturn 0;\n}\n\nstatic int\ntest_reorder_init(void)\n{\n\tstruct rte_reorder_buffer *b = NULL;\n\tunsigned int size;\n\t/*\n\t * The minimum memory area size that should be passed to library is,\n\t * sizeof(struct rte_reorder_buffer) + (2 * size * sizeof(struct rte_mbuf *));\n\t * Otherwise error will be thrown\n\t */\n\n\tsize = 100;\n\tb = rte_reorder_init(b, size, \"PKT1\", REORDER_BUFFER_SIZE);\n\tTEST_ASSERT((b == NULL) && (rte_errno == EINVAL),\n\t\t\t\"No error on init with NULL buffer.\");\n\n\tb = rte_malloc(NULL, size, 0);\n\tb = rte_reorder_init(b, size, \"PKT1\", REORDER_BUFFER_SIZE);\n\tTEST_ASSERT((b == NULL) && (rte_errno == EINVAL),\n\t\t\t\"No error on init with invalid mem zone size.\");\n\trte_free(b);\n\n\tsize = 262336;\n\tb = rte_malloc(NULL, size, 0);\n\tb = rte_reorder_init(b, size, \"PKT1\", REORDER_BUFFER_SIZE_INVALID);\n\tTEST_ASSERT((b == NULL) && (rte_errno == EINVAL),\n\t\t\t\"No error on init with invalid buffer size param.\");\n\n\tb = rte_reorder_init(b, size, NULL, REORDER_BUFFER_SIZE);\n\tTEST_ASSERT((b == NULL) && (rte_errno == EINVAL),\n\t\t\t\"No error on init with invalid name.\");\n\trte_free(b);\n\n\treturn 0;\n}\n\nstatic int\ntest_reorder_find_existing(void)\n{\n\tstruct rte_reorder_buffer *b = NULL;\n\n\t/* Try to find existing reorder buffer instance */\n\tb = rte_reorder_find_existing(\"PKT_RO1\");\n\tTEST_ASSERT_EQUAL(b, test_params->b,\n\t\t\t\"existing reorder buffer instance not found\");\n\n\t/* Try to find non existing reorder buffer instance */\n\tb = rte_reorder_find_existing(\"ro_find_non_existing\");\n\tTEST_ASSERT((b == NULL) && (rte_errno == ENOENT),\n\t\t\t\"non existing reorder buffer instance found\");\n\n\treturn 0;\n}\n\nstatic int\ntest_reorder_free(void)\n{\n\tstruct rte_reorder_buffer *b1 = NULL, *b2 = NULL;\n\tconst char *name = \"test_free\";\n\n\tb1 = rte_reorder_create(name, rte_socket_id(), 8);\n\tTEST_ASSERT_NOT_NULL(b1, \"Failed to create reorder buffer.\");\n\n\tb2 = rte_reorder_find_existing(name);\n\tTEST_ASSERT_EQUAL(b1, b2, \"Failed to find existing reorder buffer\");\n\n\trte_reorder_free(b1);\n\n\tb2 = rte_reorder_find_existing(name);\n\tTEST_ASSERT((b2 == NULL) && (rte_errno == ENOENT),\n\t\t\t\"Found previously freed reorder buffer\");\n\n\treturn 0;\n}\n\nstatic int\ntest_reorder_insert(void)\n{\n\tstruct rte_reorder_buffer *b = NULL;\n\tstruct rte_mempool *p = test_params->p;\n\tconst unsigned int size = 4;\n\tconst unsigned int num_bufs = 6;\n\tstruct rte_mbuf *bufs[num_bufs];\n\tint ret = 0;\n\tunsigned i;\n\n\t/* This would create a reorder buffer instance consisting of:\n\t * reorder_seq = 0\n\t * ready_buf: RB[size] = {NULL, NULL, NULL, NULL}\n\t * order_buf: OB[size] = {NULL, NULL, NULL, NULL}\n\t */\n\tb = rte_reorder_create(\"test_insert\", rte_socket_id(), size);\n\tTEST_ASSERT_NOT_NULL(b, \"Failed to create reorder buffer\");\n\n\tret = rte_mempool_get_bulk(p, (void *)bufs, num_bufs);\n\tTEST_ASSERT_SUCCESS(ret, \"Error getting mbuf from pool\");\n\n\t/* late packet */\n\tbufs[0]->seqn = 3 * size;\n\tret = rte_reorder_insert(b, bufs[0]);\n\tif (!((ret == -1) && (rte_errno == ERANGE))) {\n\t\tprintf(\"%s:%d: No error inserting late packet with seqn:\"\n\t\t\t\t\" 3 * size\\n\", __func__, __LINE__);\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\tfor (i = 0; i < num_bufs; i++)\n\t\tbufs[i]->seqn = i;\n\n\t/* This should fill up order buffer:\n\t * reorder_seq = 0\n\t * RB[] = {NULL, NULL, NULL, NULL}\n\t * OB[] = {0, 1, 2, 3}\n\t */\n\tfor (i = 0; i < size; i++) {\n\t\tret = rte_reorder_insert(b, bufs[i]);\n\t\tif (ret != 0) {\n\t\t\tprintf(\"%s:%d: Error inserting packet with seqn less than size\\n\",\n\t\t\t\t\t__func__, __LINE__);\n\t\t\tret = -1;\n\t\t\tgoto exit;\n\t\t}\n\t}\n\n\t/* early packet - should move mbufs to ready buf and move sequence window\n\t * reorder_seq = 4\n\t * RB[] = {0, 1, 2, 3}\n\t * OB[] = {4, NULL, NULL, NULL}\n\t */\n\tret = rte_reorder_insert(b, bufs[4]);\n\tif (ret != 0) {\n\t\tprintf(\"%s:%d: Error inserting early packet with seqn: size\\n\",\n\t\t\t\t__func__, __LINE__);\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\t/* early packet from current sequence window - full ready buffer */\n\tbufs[5]->seqn = 2 * size;\n\tret = rte_reorder_insert(b, bufs[5]);\n\tif (!((ret == -1) && (rte_errno == ENOSPC))) {\n\t\tprintf(\"%s:%d: No error inserting early packet with full ready buffer\\n\",\n\t\t\t\t__func__, __LINE__);\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\tret = 0;\nexit:\n\trte_mempool_put_bulk(p, (void *)bufs, num_bufs);\n\trte_reorder_free(b);\n\treturn ret;\n}\n\nstatic int\ntest_reorder_drain(void)\n{\n\tstruct rte_reorder_buffer *b = NULL;\n\tstruct rte_mempool *p = test_params->p;\n\tconst unsigned int size = 4;\n\tconst unsigned int num_bufs = 10;\n\tstruct rte_mbuf *bufs[num_bufs];\n\tint ret = 0;\n\tunsigned i, cnt;\n\n\t/* This would create a reorder buffer instance consisting of:\n\t * reorder_seq = 0\n\t * ready_buf: RB[size] = {NULL, NULL, NULL, NULL}\n\t * order_buf: OB[size] = {NULL, NULL, NULL, NULL}\n\t */\n\tb = rte_reorder_create(\"test_insert\", rte_socket_id(), size);\n\tTEST_ASSERT_NOT_NULL(b, \"Failed to create reorder buffer\");\n\n\tret = rte_mempool_get_bulk(p, (void *)bufs, num_bufs);\n\tTEST_ASSERT_SUCCESS(ret, \"Error getting mbuf from pool\");\n\n\t/* Check no drained packets if reorder is empty */\n\tcnt = rte_reorder_drain(b, bufs, 1);\n\tif (cnt != 0) {\n\t\tprintf(\"%s:%d: drained packets from empty reorder buffer\\n\",\n\t\t\t\t__func__, __LINE__);\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\tfor (i = 0; i < num_bufs; i++)\n\t\tbufs[i]->seqn = i;\n\n\t/* Insert packet with seqn 1:\n\t * reorder_seq = 0\n\t * RB[] = {NULL, NULL, NULL, NULL}\n\t * OB[] = {NULL, 1, NULL, NULL}\n\t */\n\trte_reorder_insert(b, bufs[1]);\n\n\t/* Check no drained packets if no ready/order packets */\n\tcnt = rte_reorder_drain(b, bufs, 1);\n\tif (cnt != 0) {\n\t\tprintf(\"%s:%d: drained packets from empty reorder buffer\\n\",\n\t\t\t\t__func__, __LINE__);\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\t/* Insert more packets\n\t * RB[] = {NULL, NULL, NULL, NULL}\n\t * OB[] = {0, 1, NULL, 3}\n\t */\n\trte_reorder_insert(b, bufs[0]);\n\trte_reorder_insert(b, bufs[3]);\n\n\t/* drained expected packets */\n\tcnt = rte_reorder_drain(b, bufs, 4);\n\tif (cnt != 2) {\n\t\tprintf(\"%s:%d:%d: number of expected packets not drained\\n\",\n\t\t\t\t__func__, __LINE__, cnt);\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\t/*\n\t * RB[] = {NULL, NULL, NULL, NULL}\n\t * OB[] = {NULL, 3, NULL, NULL}\n\t */\n\n\trte_reorder_insert(b, bufs[4]);\n\trte_reorder_insert(b, bufs[7]);\n\n\t/*\n\t * RB[] = {3, 4, NULL, NULL}\n\t * OB[] = {NULL, NULL, 7, NULL}\n\t */\n\n\tcnt = rte_reorder_drain(b, bufs, 4);\n\tif (cnt != 2) {\n\t\tprintf(\"%s:%d:%d: number of expected packets not drained\\n\",\n\t\t\t\t__func__, __LINE__, cnt);\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\tret = 0;\nexit:\n\trte_mempool_put_bulk(p, (void *)bufs, num_bufs);\n\trte_reorder_free(b);\n\treturn ret;\n}\n\nstatic int\ntest_setup(void)\n{\n\t/* reorder buffer instance creation */\n\tif (test_params->b == NULL) {\n\t\ttest_params->b = rte_reorder_create(\"PKT_RO1\", rte_socket_id(),\n\t\t\t\t\t\t\tREORDER_BUFFER_SIZE);\n\t\tif (test_params->b == NULL) {\n\t\t\tprintf(\"%s: Error creating reorder buffer instance b\\n\",\n\t\t\t\t\t__func__);\n\t\t\treturn -1;\n\t\t}\n\t} else\n\t\trte_reorder_reset(test_params->b);\n\n\t/* mempool creation */\n\tif (test_params->p == NULL) {\n\t\ttest_params->p = rte_pktmbuf_pool_create(\"RO_MBUF_POOL\",\n\t\t\tNUM_MBUFS, BURST, 0, RTE_MBUF_DEFAULT_BUF_SIZE,\n\t\t\trte_socket_id());\n\t\tif (test_params->p == NULL) {\n\t\t\tprintf(\"%s: Error creating mempool\\n\", __func__);\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic struct unit_test_suite reorder_test_suite = {\n\n\t.setup = test_setup,\n\t.suite_name = \"Reorder Unit Test Suite\",\n\t.unit_test_cases = {\n\t\tTEST_CASE(test_reorder_create),\n\t\tTEST_CASE(test_reorder_init),\n\t\tTEST_CASE(test_reorder_find_existing),\n\t\tTEST_CASE(test_reorder_free),\n\t\tTEST_CASE(test_reorder_insert),\n\t\tTEST_CASE(test_reorder_drain),\n\t\tTEST_CASES_END()\n\t}\n};\n\nstatic int\ntest_reorder(void)\n{\n\treturn unit_test_suite_runner(&reorder_test_suite);\n}\n\nstatic struct test_command reorder_cmd = {\n\t.command = \"reorder_autotest\",\n\t.callback = test_reorder,\n};\nREGISTER_TEST_COMMAND(reorder_cmd);\n" }, { "path": "app/test/test_ring.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n/*\n * Ring\n * ====\n *\n * #. Basic tests: done on one core:\n *\n * - Using single producer/single consumer functions:\n *\n * - Enqueue one object, two objects, MAX_BULK objects\n * - Dequeue one object, two objects, MAX_BULK objects\n * - Check that dequeued pointers are correct\n *\n * - Using multi producers/multi consumers functions:\n *\n * - Enqueue one object, two objects, MAX_BULK objects\n * - Dequeue one object, two objects, MAX_BULK objects\n * - Check that dequeued pointers are correct\n *\n * - Test watermark and default bulk enqueue/dequeue:\n *\n * - Set watermark\n * - Set default bulk value\n * - Enqueue objects, check that -EDQUOT is returned when\n * watermark is exceeded\n * - Check that dequeued pointers are correct\n *\n * #. Check live watermark change\n *\n * - Start a loop on another lcore that will enqueue and dequeue\n * objects in a ring. It will monitor the value of watermark.\n * - At the same time, change the watermark on the master lcore.\n * - The slave lcore will check that watermark changes from 16 to 32.\n *\n * #. Performance tests.\n *\n * Tests done in test_ring_perf.c\n */\n\n#define RING_SIZE 4096\n#define MAX_BULK 32\n#define N 65536\n#define TIME_S 5\n\nstatic rte_atomic32_t synchro;\n\nstatic struct rte_ring *r;\n\n#define\tTEST_RING_VERIFY(exp)\t\t\t\t\t\t\\\n\tif (!(exp)) {\t\t\t\t\t\t\t\\\n\t\tprintf(\"error at %s:%d\\tcondition \" #exp \" failed\\n\",\t\\\n\t\t __func__, __LINE__);\t\t\t\t\\\n\t\trte_ring_dump(stdout, r);\t\t\t\t\\\n\t\treturn (-1);\t\t\t\t\t\t\\\n\t}\n\n#define\tTEST_RING_FULL_EMTPY_ITER\t8\n\nstatic int\ncheck_live_watermark_change(__attribute__((unused)) void *dummy)\n{\n\tuint64_t hz = rte_get_timer_hz();\n\tvoid *obj_table[MAX_BULK];\n\tunsigned watermark, watermark_old = 16;\n\tuint64_t cur_time, end_time;\n\tint64_t diff = 0;\n\tint i, ret;\n\tunsigned count = 4;\n\n\t/* init the object table */\n\tmemset(obj_table, 0, sizeof(obj_table));\n\tend_time = rte_get_timer_cycles() + (hz * 2);\n\n\t/* check that bulk and watermark are 4 and 32 (respectively) */\n\twhile (diff >= 0) {\n\n\t\t/* add in ring until we reach watermark */\n\t\tret = 0;\n\t\tfor (i = 0; i < 16; i ++) {\n\t\t\tif (ret != 0)\n\t\t\t\tbreak;\n\t\t\tret = rte_ring_enqueue_bulk(r, obj_table, count);\n\t\t}\n\n\t\tif (ret != -EDQUOT) {\n\t\t\tprintf(\"Cannot enqueue objects, or watermark not \"\n\t\t\t \"reached (ret=%d)\\n\", ret);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* read watermark, the only change allowed is from 16 to 32 */\n\t\twatermark = r->prod.watermark;\n\t\tif (watermark != watermark_old &&\n\t\t (watermark_old != 16 || watermark != 32)) {\n\t\t\tprintf(\"Bad watermark change %u -> %u\\n\", watermark_old,\n\t\t\t watermark);\n\t\t\treturn -1;\n\t\t}\n\t\twatermark_old = watermark;\n\n\t\t/* dequeue objects from ring */\n\t\twhile (i--) {\n\t\t\tret = rte_ring_dequeue_bulk(r, obj_table, count);\n\t\t\tif (ret != 0) {\n\t\t\t\tprintf(\"Cannot dequeue (ret=%d)\\n\", ret);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\n\t\tcur_time = rte_get_timer_cycles();\n\t\tdiff = end_time - cur_time;\n\t}\n\n\tif (watermark_old != 32 ) {\n\t\tprintf(\" watermark was not updated (wm=%u)\\n\",\n\t\t watermark_old);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntest_live_watermark_change(void)\n{\n\tunsigned lcore_id = rte_lcore_id();\n\tunsigned lcore_id2 = rte_get_next_lcore(lcore_id, 0, 1);\n\n\tprintf(\"Test watermark live modification\\n\");\n\trte_ring_set_water_mark(r, 16);\n\n\t/* launch a thread that will enqueue and dequeue, checking\n\t * watermark and quota */\n\trte_eal_remote_launch(check_live_watermark_change, NULL, lcore_id2);\n\n\trte_delay_ms(1000);\n\trte_ring_set_water_mark(r, 32);\n\trte_delay_ms(1000);\n\n\tif (rte_eal_wait_lcore(lcore_id2) < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/* Test for catch on invalid watermark values */\nstatic int\ntest_set_watermark( void ){\n\tunsigned count;\n\tint setwm;\n\n\tstruct rte_ring *r = rte_ring_lookup(\"test_ring_basic_ex\");\n\tif(r == NULL){\n\t\tprintf( \" ring lookup failed\\n\" );\n\t\tgoto error;\n\t}\n\tcount = r->prod.size*2;\n\tsetwm = rte_ring_set_water_mark(r, count);\n\tif (setwm != -EINVAL){\n\t\tprintf(\"Test failed to detect invalid watermark count value\\n\");\n\t\tgoto error;\n\t}\n\n\tcount = 0;\n\trte_ring_set_water_mark(r, count);\n\tif (r->prod.watermark != r->prod.size) {\n\t\tprintf(\"Test failed to detect invalid watermark count value\\n\");\n\t\tgoto error;\n\t}\n\treturn 0;\n\nerror:\n\treturn -1;\n}\n\n/*\n * helper routine for test_ring_basic\n */\nstatic int\ntest_ring_basic_full_empty(void * const src[], void *dst[])\n{\n\tunsigned i, rand;\n\tconst unsigned rsz = RING_SIZE - 1;\n\n\tprintf(\"Basic full/empty test\\n\");\n\n\tfor (i = 0; TEST_RING_FULL_EMTPY_ITER != i; i++) {\n\n\t\t/* random shift in the ring */\n\t\trand = RTE_MAX(rte_rand() % RING_SIZE, 1UL);\n\t\tprintf(\"%s: iteration %u, random shift: %u;\\n\",\n\t\t __func__, i, rand);\n\t\tTEST_RING_VERIFY(-ENOBUFS != rte_ring_enqueue_bulk(r, src,\n\t\t rand));\n\t\tTEST_RING_VERIFY(0 == rte_ring_dequeue_bulk(r, dst, rand));\n\n\t\t/* fill the ring */\n\t\tTEST_RING_VERIFY(-ENOBUFS != rte_ring_enqueue_bulk(r, src,\n\t\t rsz));\n\t\tTEST_RING_VERIFY(0 == rte_ring_free_count(r));\n\t\tTEST_RING_VERIFY(rsz == rte_ring_count(r));\n\t\tTEST_RING_VERIFY(rte_ring_full(r));\n\t\tTEST_RING_VERIFY(0 == rte_ring_empty(r));\n\n\t\t/* empty the ring */\n\t\tTEST_RING_VERIFY(0 == rte_ring_dequeue_bulk(r, dst, rsz));\n\t\tTEST_RING_VERIFY(rsz == rte_ring_free_count(r));\n\t\tTEST_RING_VERIFY(0 == rte_ring_count(r));\n\t\tTEST_RING_VERIFY(0 == rte_ring_full(r));\n\t\tTEST_RING_VERIFY(rte_ring_empty(r));\n\n\t\t/* check data */\n\t\tTEST_RING_VERIFY(0 == memcmp(src, dst, rsz));\n\t\trte_ring_dump(stdout, r);\n\t}\n\treturn (0);\n}\n\nstatic int\ntest_ring_basic(void)\n{\n\tvoid **src = NULL, **cur_src = NULL, **dst = NULL, **cur_dst = NULL;\n\tint ret;\n\tunsigned i, num_elems;\n\n\t/* alloc dummy object pointers */\n\tsrc = malloc(RING_SIZE*2*sizeof(void *));\n\tif (src == NULL)\n\t\tgoto fail;\n\n\tfor (i = 0; i < RING_SIZE*2 ; i++) {\n\t\tsrc[i] = (void *)(unsigned long)i;\n\t}\n\tcur_src = src;\n\n\t/* alloc some room for copied objects */\n\tdst = malloc(RING_SIZE*2*sizeof(void *));\n\tif (dst == NULL)\n\t\tgoto fail;\n\n\tmemset(dst, 0, RING_SIZE*2*sizeof(void *));\n\tcur_dst = dst;\n\n\tprintf(\"enqueue 1 obj\\n\");\n\tret = rte_ring_sp_enqueue_bulk(r, cur_src, 1);\n\tcur_src += 1;\n\tif (ret != 0)\n\t\tgoto fail;\n\n\tprintf(\"enqueue 2 objs\\n\");\n\tret = rte_ring_sp_enqueue_bulk(r, cur_src, 2);\n\tcur_src += 2;\n\tif (ret != 0)\n\t\tgoto fail;\n\n\tprintf(\"enqueue MAX_BULK objs\\n\");\n\tret = rte_ring_sp_enqueue_bulk(r, cur_src, MAX_BULK);\n\tcur_src += MAX_BULK;\n\tif (ret != 0)\n\t\tgoto fail;\n\n\tprintf(\"dequeue 1 obj\\n\");\n\tret = rte_ring_sc_dequeue_bulk(r, cur_dst, 1);\n\tcur_dst += 1;\n\tif (ret != 0)\n\t\tgoto fail;\n\n\tprintf(\"dequeue 2 objs\\n\");\n\tret = rte_ring_sc_dequeue_bulk(r, cur_dst, 2);\n\tcur_dst += 2;\n\tif (ret != 0)\n\t\tgoto fail;\n\n\tprintf(\"dequeue MAX_BULK objs\\n\");\n\tret = rte_ring_sc_dequeue_bulk(r, cur_dst, MAX_BULK);\n\tcur_dst += MAX_BULK;\n\tif (ret != 0)\n\t\tgoto fail;\n\n\t/* check data */\n\tif (memcmp(src, dst, cur_dst - dst)) {\n\t\trte_hexdump(stdout, \"src\", src, cur_src - src);\n\t\trte_hexdump(stdout, \"dst\", dst, cur_dst - dst);\n\t\tprintf(\"data after dequeue is not the same\\n\");\n\t\tgoto fail;\n\t}\n\tcur_src = src;\n\tcur_dst = dst;\n\n\tprintf(\"enqueue 1 obj\\n\");\n\tret = rte_ring_mp_enqueue_bulk(r, cur_src, 1);\n\tcur_src += 1;\n\tif (ret != 0)\n\t\tgoto fail;\n\n\tprintf(\"enqueue 2 objs\\n\");\n\tret = rte_ring_mp_enqueue_bulk(r, cur_src, 2);\n\tcur_src += 2;\n\tif (ret != 0)\n\t\tgoto fail;\n\n\tprintf(\"enqueue MAX_BULK objs\\n\");\n\tret = rte_ring_mp_enqueue_bulk(r, cur_src, MAX_BULK);\n\tcur_src += MAX_BULK;\n\tif (ret != 0)\n\t\tgoto fail;\n\n\tprintf(\"dequeue 1 obj\\n\");\n\tret = rte_ring_mc_dequeue_bulk(r, cur_dst, 1);\n\tcur_dst += 1;\n\tif (ret != 0)\n\t\tgoto fail;\n\n\tprintf(\"dequeue 2 objs\\n\");\n\tret = rte_ring_mc_dequeue_bulk(r, cur_dst, 2);\n\tcur_dst += 2;\n\tif (ret != 0)\n\t\tgoto fail;\n\n\tprintf(\"dequeue MAX_BULK objs\\n\");\n\tret = rte_ring_mc_dequeue_bulk(r, cur_dst, MAX_BULK);\n\tcur_dst += MAX_BULK;\n\tif (ret != 0)\n\t\tgoto fail;\n\n\t/* check data */\n\tif (memcmp(src, dst, cur_dst - dst)) {\n\t\trte_hexdump(stdout, \"src\", src, cur_src - src);\n\t\trte_hexdump(stdout, \"dst\", dst, cur_dst - dst);\n\t\tprintf(\"data after dequeue is not the same\\n\");\n\t\tgoto fail;\n\t}\n\tcur_src = src;\n\tcur_dst = dst;\n\n\tprintf(\"fill and empty the ring\\n\");\n\tfor (i = 0; istats[lcore_id];\n\n\tprintf(\"Test the ring stats.\\n\");\n\n\t/* Reset the watermark in case it was set in another test. */\n\trte_ring_set_water_mark(r, 0);\n\n\t/* Reset the ring stats. */\n\tmemset(&r->stats[lcore_id], 0, sizeof(r->stats[lcore_id]));\n\n\t/* Allocate some dummy object pointers. */\n\tsrc = malloc(RING_SIZE*2*sizeof(void *));\n\tif (src == NULL)\n\t\tgoto fail;\n\n\tfor (i = 0; i < RING_SIZE*2 ; i++) {\n\t\tsrc[i] = (void *)(unsigned long)i;\n\t}\n\n\t/* Allocate some memory for copied objects. */\n\tdst = malloc(RING_SIZE*2*sizeof(void *));\n\tif (dst == NULL)\n\t\tgoto fail;\n\n\tmemset(dst, 0, RING_SIZE*2*sizeof(void *));\n\n\t/* Set the head and tail pointers. */\n\tcur_src = src;\n\tcur_dst = dst;\n\n\t/* Do Enqueue tests. */\n\tprintf(\"Test the dequeue stats.\\n\");\n\n\t/* Fill the ring up to RING_SIZE -1. */\n\tprintf(\"Fill the ring.\\n\");\n\tfor (i = 0; i< (RING_SIZE/MAX_BULK); i++) {\n\t\trte_ring_sp_enqueue_burst(r, cur_src, MAX_BULK);\n\t\tcur_src += MAX_BULK;\n\t}\n\n\t/* Adjust for final enqueue = MAX_BULK -1. */\n\tcur_src--;\n\n\tprintf(\"Verify that the ring is full.\\n\");\n\tif (rte_ring_full(r) != 1)\n\t\tgoto fail;\n\n\n\tprintf(\"Verify the enqueue success stats.\\n\");\n\t/* Stats should match above enqueue operations to fill the ring. */\n\tif (ring_stats->enq_success_bulk != (RING_SIZE/MAX_BULK))\n\t\tgoto fail;\n\n\t/* Current max objects is RING_SIZE -1. */\n\tif (ring_stats->enq_success_objs != RING_SIZE -1)\n\t\tgoto fail;\n\n\t/* Shouldn't have any failures yet. */\n\tif (ring_stats->enq_fail_bulk != 0)\n\t\tgoto fail;\n\tif (ring_stats->enq_fail_objs != 0)\n\t\tgoto fail;\n\n\n\tprintf(\"Test stats for SP burst enqueue to a full ring.\\n\");\n\tnum_items = 2;\n\tret = rte_ring_sp_enqueue_burst(r, cur_src, num_items);\n\tif ((ret & RTE_RING_SZ_MASK) != 0)\n\t\tgoto fail;\n\n\tfailed_enqueue_ops += 1;\n\tfailed_enqueue_items += num_items;\n\n\t/* The enqueue should have failed. */\n\tif (ring_stats->enq_fail_bulk != failed_enqueue_ops)\n\t\tgoto fail;\n\tif (ring_stats->enq_fail_objs != failed_enqueue_items)\n\t\tgoto fail;\n\n\n\tprintf(\"Test stats for SP bulk enqueue to a full ring.\\n\");\n\tnum_items = 4;\n\tret = rte_ring_sp_enqueue_bulk(r, cur_src, num_items);\n\tif (ret != -ENOBUFS)\n\t\tgoto fail;\n\n\tfailed_enqueue_ops += 1;\n\tfailed_enqueue_items += num_items;\n\n\t/* The enqueue should have failed. */\n\tif (ring_stats->enq_fail_bulk != failed_enqueue_ops)\n\t\tgoto fail;\n\tif (ring_stats->enq_fail_objs != failed_enqueue_items)\n\t\tgoto fail;\n\n\n\tprintf(\"Test stats for MP burst enqueue to a full ring.\\n\");\n\tnum_items = 8;\n\tret = rte_ring_mp_enqueue_burst(r, cur_src, num_items);\n\tif ((ret & RTE_RING_SZ_MASK) != 0)\n\t\tgoto fail;\n\n\tfailed_enqueue_ops += 1;\n\tfailed_enqueue_items += num_items;\n\n\t/* The enqueue should have failed. */\n\tif (ring_stats->enq_fail_bulk != failed_enqueue_ops)\n\t\tgoto fail;\n\tif (ring_stats->enq_fail_objs != failed_enqueue_items)\n\t\tgoto fail;\n\n\n\tprintf(\"Test stats for MP bulk enqueue to a full ring.\\n\");\n\tnum_items = 16;\n\tret = rte_ring_mp_enqueue_bulk(r, cur_src, num_items);\n\tif (ret != -ENOBUFS)\n\t\tgoto fail;\n\n\tfailed_enqueue_ops += 1;\n\tfailed_enqueue_items += num_items;\n\n\t/* The enqueue should have failed. */\n\tif (ring_stats->enq_fail_bulk != failed_enqueue_ops)\n\t\tgoto fail;\n\tif (ring_stats->enq_fail_objs != failed_enqueue_items)\n\t\tgoto fail;\n\n\n\t/* Do Dequeue tests. */\n\tprintf(\"Test the dequeue stats.\\n\");\n\n\tprintf(\"Empty the ring.\\n\");\n\tfor (i = 0; ideq_success_bulk != (RING_SIZE/MAX_BULK))\n\t\tgoto fail;\n\n\t/* Objects dequeued is RING_SIZE -1. */\n\tif (ring_stats->deq_success_objs != RING_SIZE -1)\n\t\tgoto fail;\n\n\t/* Shouldn't have any dequeue failure stats yet. */\n\tif (ring_stats->deq_fail_bulk != 0)\n\t\tgoto fail;\n\n\tprintf(\"Test stats for SC burst dequeue with an empty ring.\\n\");\n\tnum_items = 2;\n\tret = rte_ring_sc_dequeue_burst(r, cur_dst, num_items);\n\tif ((ret & RTE_RING_SZ_MASK) != 0)\n\t\tgoto fail;\n\n\tfailed_dequeue_ops += 1;\n\tfailed_dequeue_items += num_items;\n\n\t/* The dequeue should have failed. */\n\tif (ring_stats->deq_fail_bulk != failed_dequeue_ops)\n\t\tgoto fail;\n\tif (ring_stats->deq_fail_objs != failed_dequeue_items)\n\t\tgoto fail;\n\n\n\tprintf(\"Test stats for SC bulk dequeue with an empty ring.\\n\");\n\tnum_items = 4;\n\tret = rte_ring_sc_dequeue_bulk(r, cur_dst, num_items);\n\tif (ret != -ENOENT)\n\t\tgoto fail;\n\n\tfailed_dequeue_ops += 1;\n\tfailed_dequeue_items += num_items;\n\n\t/* The dequeue should have failed. */\n\tif (ring_stats->deq_fail_bulk != failed_dequeue_ops)\n\t\tgoto fail;\n\tif (ring_stats->deq_fail_objs != failed_dequeue_items)\n\t\tgoto fail;\n\n\n\tprintf(\"Test stats for MC burst dequeue with an empty ring.\\n\");\n\tnum_items = 8;\n\tret = rte_ring_mc_dequeue_burst(r, cur_dst, num_items);\n\tif ((ret & RTE_RING_SZ_MASK) != 0)\n\t\tgoto fail;\n\tfailed_dequeue_ops += 1;\n\tfailed_dequeue_items += num_items;\n\n\t/* The dequeue should have failed. */\n\tif (ring_stats->deq_fail_bulk != failed_dequeue_ops)\n\t\tgoto fail;\n\tif (ring_stats->deq_fail_objs != failed_dequeue_items)\n\t\tgoto fail;\n\n\n\tprintf(\"Test stats for MC bulk dequeue with an empty ring.\\n\");\n\tnum_items = 16;\n\tret = rte_ring_mc_dequeue_bulk(r, cur_dst, num_items);\n\tif (ret != -ENOENT)\n\t\tgoto fail;\n\n\tfailed_dequeue_ops += 1;\n\tfailed_dequeue_items += num_items;\n\n\t/* The dequeue should have failed. */\n\tif (ring_stats->deq_fail_bulk != failed_dequeue_ops)\n\t\tgoto fail;\n\tif (ring_stats->deq_fail_objs != failed_dequeue_items)\n\t\tgoto fail;\n\n\n\tprintf(\"Test total enqueue/dequeue stats.\\n\");\n\t/* At this point the enqueue and dequeue stats should be the same. */\n\tif (ring_stats->enq_success_bulk != ring_stats->deq_success_bulk)\n\t\tgoto fail;\n\tif (ring_stats->enq_success_objs != ring_stats->deq_success_objs)\n\t\tgoto fail;\n\tif (ring_stats->enq_fail_bulk != ring_stats->deq_fail_bulk)\n\t\tgoto fail;\n\tif (ring_stats->enq_fail_objs != ring_stats->deq_fail_objs)\n\t\tgoto fail;\n\n\n\t/* Watermark Tests. */\n\tprintf(\"Test the watermark/quota stats.\\n\");\n\n\tprintf(\"Verify the initial watermark stats.\\n\");\n\t/* Watermark stats should be 0 since there is no watermark. */\n\tif (ring_stats->enq_quota_bulk != 0)\n\t\tgoto fail;\n\tif (ring_stats->enq_quota_objs != 0)\n\t\tgoto fail;\n\n\t/* Set a watermark. */\n\trte_ring_set_water_mark(r, 16);\n\n\t/* Reset pointers. */\n\tcur_src = src;\n\tcur_dst = dst;\n\n\tlast_enqueue_ops = ring_stats->enq_success_bulk;\n\tlast_enqueue_items = ring_stats->enq_success_objs;\n\n\n\tprintf(\"Test stats for SP burst enqueue below watermark.\\n\");\n\tnum_items = 8;\n\tret = rte_ring_sp_enqueue_burst(r, cur_src, num_items);\n\tif ((ret & RTE_RING_SZ_MASK) != num_items)\n\t\tgoto fail;\n\n\t/* Watermark stats should still be 0. */\n\tif (ring_stats->enq_quota_bulk != 0)\n\t\tgoto fail;\n\tif (ring_stats->enq_quota_objs != 0)\n\t\tgoto fail;\n\n\t/* Success stats should have increased. */\n\tif (ring_stats->enq_success_bulk != last_enqueue_ops + 1)\n\t\tgoto fail;\n\tif (ring_stats->enq_success_objs != last_enqueue_items + num_items)\n\t\tgoto fail;\n\n\tlast_enqueue_ops = ring_stats->enq_success_bulk;\n\tlast_enqueue_items = ring_stats->enq_success_objs;\n\n\n\tprintf(\"Test stats for SP burst enqueue at watermark.\\n\");\n\tnum_items = 8;\n\tret = rte_ring_sp_enqueue_burst(r, cur_src, num_items);\n\tif ((ret & RTE_RING_SZ_MASK) != num_items)\n\t\tgoto fail;\n\n\t/* Watermark stats should have changed. */\n\tif (ring_stats->enq_quota_bulk != 1)\n\t\tgoto fail;\n\tif (ring_stats->enq_quota_objs != num_items)\n\t\tgoto fail;\n\n\tlast_quota_ops = ring_stats->enq_quota_bulk;\n\tlast_quota_items = ring_stats->enq_quota_objs;\n\n\n\tprintf(\"Test stats for SP burst enqueue above watermark.\\n\");\n\tnum_items = 1;\n\tret = rte_ring_sp_enqueue_burst(r, cur_src, num_items);\n\tif ((ret & RTE_RING_SZ_MASK) != num_items)\n\t\tgoto fail;\n\n\t/* Watermark stats should have changed. */\n\tif (ring_stats->enq_quota_bulk != last_quota_ops +1)\n\t\tgoto fail;\n\tif (ring_stats->enq_quota_objs != last_quota_items + num_items)\n\t\tgoto fail;\n\n\tlast_quota_ops = ring_stats->enq_quota_bulk;\n\tlast_quota_items = ring_stats->enq_quota_objs;\n\n\n\tprintf(\"Test stats for MP burst enqueue above watermark.\\n\");\n\tnum_items = 2;\n\tret = rte_ring_mp_enqueue_burst(r, cur_src, num_items);\n\tif ((ret & RTE_RING_SZ_MASK) != num_items)\n\t\tgoto fail;\n\n\t/* Watermark stats should have changed. */\n\tif (ring_stats->enq_quota_bulk != last_quota_ops +1)\n\t\tgoto fail;\n\tif (ring_stats->enq_quota_objs != last_quota_items + num_items)\n\t\tgoto fail;\n\n\tlast_quota_ops = ring_stats->enq_quota_bulk;\n\tlast_quota_items = ring_stats->enq_quota_objs;\n\n\n\tprintf(\"Test stats for SP bulk enqueue above watermark.\\n\");\n\tnum_items = 4;\n\tret = rte_ring_sp_enqueue_bulk(r, cur_src, num_items);\n\tif (ret != -EDQUOT)\n\t\tgoto fail;\n\n\t/* Watermark stats should have changed. */\n\tif (ring_stats->enq_quota_bulk != last_quota_ops +1)\n\t\tgoto fail;\n\tif (ring_stats->enq_quota_objs != last_quota_items + num_items)\n\t\tgoto fail;\n\n\tlast_quota_ops = ring_stats->enq_quota_bulk;\n\tlast_quota_items = ring_stats->enq_quota_objs;\n\n\n\tprintf(\"Test stats for MP bulk enqueue above watermark.\\n\");\n\tnum_items = 8;\n\tret = rte_ring_mp_enqueue_bulk(r, cur_src, num_items);\n\tif (ret != -EDQUOT)\n\t\tgoto fail;\n\n\t/* Watermark stats should have changed. */\n\tif (ring_stats->enq_quota_bulk != last_quota_ops +1)\n\t\tgoto fail;\n\tif (ring_stats->enq_quota_objs != last_quota_items + num_items)\n\t\tgoto fail;\n\n\tprintf(\"Test watermark success stats.\\n\");\n\t/* Success stats should be same as last non-watermarked enqueue. */\n\tif (ring_stats->enq_success_bulk != last_enqueue_ops)\n\t\tgoto fail;\n\tif (ring_stats->enq_success_objs != last_enqueue_items)\n\t\tgoto fail;\n\n\n\t/* Cleanup. */\n\n\t/* Empty the ring. */\n\tfor (i = 0; istats[lcore_id], 0, sizeof(r->stats[lcore_id]));\n\n\t/* Free memory before test completed */\n\tif (src)\n\t\tfree(src);\n\tif (dst)\n\t\tfree(dst);\n\treturn 0;\n\nfail:\n\tif (src)\n\t\tfree(src);\n\tif (dst)\n\t\tfree(dst);\n\treturn -1;\n#endif\n}\n\n/*\n * it will always fail to create ring with a wrong ring size number in this function\n */\nstatic int\ntest_ring_creation_with_wrong_size(void)\n{\n\tstruct rte_ring * rp = NULL;\n\n\t/* Test if ring size is not power of 2 */\n\trp = rte_ring_create(\"test_bad_ring_size\", RING_SIZE + 1, SOCKET_ID_ANY, 0);\n\tif (NULL != rp) {\n\t\treturn -1;\n\t}\n\n\t/* Test if ring size is exceeding the limit */\n\trp = rte_ring_create(\"test_bad_ring_size\", (RTE_RING_SZ_MASK + 1), SOCKET_ID_ANY, 0);\n\tif (NULL != rp) {\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/*\n * it tests if it would always fail to create ring with an used ring name\n */\nstatic int\ntest_ring_creation_with_an_used_name(void)\n{\n\tstruct rte_ring * rp;\n\n\trp = rte_ring_create(\"test\", RING_SIZE, SOCKET_ID_ANY, 0);\n\tif (NULL != rp)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * Test to if a non-power of 2 count causes the create\n * function to fail correctly\n */\nstatic int\ntest_create_count_odd(void)\n{\n\tstruct rte_ring *r = rte_ring_create(\"test_ring_count\",\n\t\t\t4097, SOCKET_ID_ANY, 0 );\n\tif(r != NULL){\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic int\ntest_lookup_null(void)\n{\n\tstruct rte_ring *rlp = rte_ring_lookup(\"ring_not_found\");\n\tif (rlp ==NULL)\n\tif (rte_errno != ENOENT){\n\t\tprintf( \"test failed to returnn error on null pointer\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/*\n * it tests some more basic ring operations\n */\nstatic int\ntest_ring_basic_ex(void)\n{\n\tint ret = -1;\n\tunsigned i;\n\tstruct rte_ring * rp;\n\tvoid **obj = NULL;\n\n\tobj = rte_calloc(\"test_ring_basic_ex_malloc\", RING_SIZE, sizeof(void *), 0);\n\tif (obj == NULL) {\n\t\tprintf(\"test_ring_basic_ex fail to rte_malloc\\n\");\n\t\tgoto fail_test;\n\t}\n\n\trp = rte_ring_create(\"test_ring_basic_ex\", RING_SIZE, SOCKET_ID_ANY,\n\t\t\tRING_F_SP_ENQ | RING_F_SC_DEQ);\n\tif (rp == NULL) {\n\t\tprintf(\"test_ring_basic_ex fail to create ring\\n\");\n\t\tgoto fail_test;\n\t}\n\n\tif (rte_ring_lookup(\"test_ring_basic_ex\") != rp) {\n\t\tgoto fail_test;\n\t}\n\n\tif (rte_ring_empty(rp) != 1) {\n\t\tprintf(\"test_ring_basic_ex ring is not empty but it should be\\n\");\n\t\tgoto fail_test;\n\t}\n\n\tprintf(\"%u ring entries are now free\\n\", rte_ring_free_count(rp));\n\n\tfor (i = 0; i < RING_SIZE; i ++) {\n\t\trte_ring_enqueue(rp, obj[i]);\n\t}\n\n\tif (rte_ring_full(rp) != 1) {\n\t\tprintf(\"test_ring_basic_ex ring is not full but it should be\\n\");\n\t\tgoto fail_test;\n\t}\n\n\tfor (i = 0; i < RING_SIZE; i ++) {\n\t\trte_ring_dequeue(rp, &obj[i]);\n\t}\n\n\tif (rte_ring_empty(rp) != 1) {\n\t\tprintf(\"test_ring_basic_ex ring is not empty but it should be\\n\");\n\t\tgoto fail_test;\n\t}\n\n\t/* Covering the ring burst operation */\n\tret = rte_ring_enqueue_burst(rp, obj, 2);\n\tif ((ret & RTE_RING_SZ_MASK) != 2) {\n\t\tprintf(\"test_ring_basic_ex: rte_ring_enqueue_burst fails \\n\");\n\t\tgoto fail_test;\n\t}\n\n\tret = rte_ring_dequeue_burst(rp, obj, 2);\n\tif (ret != 2) {\n\t\tprintf(\"test_ring_basic_ex: rte_ring_dequeue_burst fails \\n\");\n\t\tgoto fail_test;\n\t}\n\n\tret = 0;\nfail_test:\n\tif (obj != NULL)\n\t\trte_free(obj);\n\n\treturn ret;\n}\n\nstatic int\ntest_ring(void)\n{\n\t/* some more basic operations */\n\tif (test_ring_basic_ex() < 0)\n\t\treturn -1;\n\n\trte_atomic32_init(&synchro);\n\n\tif (r == NULL)\n\t\tr = rte_ring_create(\"test\", RING_SIZE, SOCKET_ID_ANY, 0);\n\tif (r == NULL)\n\t\treturn -1;\n\n\t/* retrieve the ring from its name */\n\tif (rte_ring_lookup(\"test\") != r) {\n\t\tprintf(\"Cannot lookup ring from its name\\n\");\n\t\treturn -1;\n\t}\n\n\t/* burst operations */\n\tif (test_ring_burst_basic() < 0)\n\t\treturn -1;\n\n\t/* basic operations */\n\tif (test_ring_basic() < 0)\n\t\treturn -1;\n\n\t/* ring stats */\n\tif (test_ring_stats() < 0)\n\t\treturn -1;\n\n\t/* basic operations */\n\tif (test_live_watermark_change() < 0)\n\t\treturn -1;\n\n\tif ( test_set_watermark() < 0){\n\t\tprintf (\"Test failed to detect invalid parameter\\n\");\n\t\treturn -1;\n\t}\n\telse\n\t\tprintf ( \"Test detected forced bad watermark values\\n\");\n\n\tif ( test_create_count_odd() < 0){\n\t\t\tprintf (\"Test failed to detect odd count\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\telse\n\t\t\tprintf ( \"Test detected odd count\\n\");\n\n\tif ( test_lookup_null() < 0){\n\t\t\t\tprintf (\"Test failed to detect NULL ring lookup\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\telse\n\t\t\t\tprintf ( \"Test detected NULL ring lookup \\n\");\n\n\t/* test of creating ring with wrong size */\n\tif (test_ring_creation_with_wrong_size() < 0)\n\t\treturn -1;\n\n\t/* test of creation ring with an used name */\n\tif (test_ring_creation_with_an_used_name() < 0)\n\t\treturn -1;\n\n\t/* dump the ring status */\n\trte_ring_list_dump(stdout);\n\n\treturn 0;\n}\n\nstatic struct test_command ring_cmd = {\n\t.command = \"ring_autotest\",\n\t.callback = test_ring,\n};\nREGISTER_TEST_COMMAND(ring_cmd);\n" }, { "path": "app/test/test_ring_perf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n\n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n/*\n * Ring\n * ====\n *\n * Measures performance of various operations using rdtsc\n * * Empty ring dequeue\n * * Enqueue/dequeue of bursts in 1 threads\n * * Enqueue/dequeue of bursts in 2 threads\n */\n\n#define RING_NAME \"RING_PERF\"\n#define RING_SIZE 4096\n#define MAX_BURST 32\n\n/*\n * the sizes to enqueue and dequeue in testing\n * (marked volatile so they won't be seen as compile-time constants)\n */\nstatic const volatile unsigned bulk_sizes[] = { 8, 32 };\n\n/* The ring structure used for tests */\nstatic struct rte_ring *r;\n\nstruct lcore_pair {\n\tunsigned c1, c2;\n};\n\nstatic volatile unsigned lcore_count = 0;\n\n/**** Functions to analyse our core mask to get cores for different tests ***/\n\nstatic int\nget_two_hyperthreads(struct lcore_pair *lcp)\n{\n\tunsigned id1, id2;\n\tunsigned c1, c2, s1, s2;\n\tRTE_LCORE_FOREACH(id1) {\n\t\t/* inner loop just re-reads all id's. We could skip the first few\n\t\t * elements, but since number of cores is small there is little point\n\t\t */\n\t\tRTE_LCORE_FOREACH(id2) {\n\t\t\tif (id1 == id2)\n\t\t\t\tcontinue;\n\t\t\tc1 = lcore_config[id1].core_id;\n\t\t\tc2 = lcore_config[id2].core_id;\n\t\t\ts1 = lcore_config[id1].socket_id;\n\t\t\ts2 = lcore_config[id2].socket_id;\n\t\t\tif ((c1 == c2) && (s1 == s2)){\n\t\t\t\tlcp->c1 = id1;\n\t\t\t\tlcp->c2 = id2;\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\n\treturn 1;\n}\n\nstatic int\nget_two_cores(struct lcore_pair *lcp)\n{\n\tunsigned id1, id2;\n\tunsigned c1, c2, s1, s2;\n\tRTE_LCORE_FOREACH(id1) {\n\t\tRTE_LCORE_FOREACH(id2) {\n\t\t\tif (id1 == id2)\n\t\t\t\tcontinue;\n\t\t\tc1 = lcore_config[id1].core_id;\n\t\t\tc2 = lcore_config[id2].core_id;\n\t\t\ts1 = lcore_config[id1].socket_id;\n\t\t\ts2 = lcore_config[id2].socket_id;\n\t\t\tif ((c1 != c2) && (s1 == s2)){\n\t\t\t\tlcp->c1 = id1;\n\t\t\t\tlcp->c2 = id2;\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\n\treturn 1;\n}\n\nstatic int\nget_two_sockets(struct lcore_pair *lcp)\n{\n\tunsigned id1, id2;\n\tunsigned s1, s2;\n\tRTE_LCORE_FOREACH(id1) {\n\t\tRTE_LCORE_FOREACH(id2) {\n\t\t\tif (id1 == id2)\n\t\t\t\tcontinue;\n\t\t\ts1 = lcore_config[id1].socket_id;\n\t\t\ts2 = lcore_config[id2].socket_id;\n\t\t\tif (s1 != s2){\n\t\t\t\tlcp->c1 = id1;\n\t\t\t\tlcp->c2 = id2;\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\n\treturn 1;\n}\n\n/* Get cycle counts for dequeuing from an empty ring. Should be 2 or 3 cycles */\nstatic void\ntest_empty_dequeue(void)\n{\n\tconst unsigned iter_shift = 26;\n\tconst unsigned iterations = 1<size;\n\tunsigned i;\n\tvoid *burst[MAX_BURST] = {0};\n\n\tif ( __sync_add_and_fetch(&lcore_count, 1) != 2 )\n\t\twhile(lcore_count != 2)\n\t\t\trte_pause();\n\n\tconst uint64_t sp_start = rte_rdtsc();\n\tfor (i = 0; i < iterations; i++)\n\t\twhile (rte_ring_sp_enqueue_bulk(r, burst, size) != 0)\n\t\t\trte_pause();\n\tconst uint64_t sp_end = rte_rdtsc();\n\n\tconst uint64_t mp_start = rte_rdtsc();\n\tfor (i = 0; i < iterations; i++)\n\t\twhile (rte_ring_mp_enqueue_bulk(r, burst, size) != 0)\n\t\t\trte_pause();\n\tconst uint64_t mp_end = rte_rdtsc();\n\n\tparams->spsc = ((double)(sp_end - sp_start))/(iterations*size);\n\tparams->mpmc = ((double)(mp_end - mp_start))/(iterations*size);\n\treturn 0;\n}\n\n/*\n * Function that uses rdtsc to measure timing for ring dequeue. Needs pair\n * thread running enqueue_bulk function\n */\nstatic int\ndequeue_bulk(void *p)\n{\n\tconst unsigned iter_shift = 23;\n\tconst unsigned iterations = 1<size;\n\tunsigned i;\n\tvoid *burst[MAX_BURST] = {0};\n\n\tif ( __sync_add_and_fetch(&lcore_count, 1) != 2 )\n\t\twhile(lcore_count != 2)\n\t\t\trte_pause();\n\n\tconst uint64_t sc_start = rte_rdtsc();\n\tfor (i = 0; i < iterations; i++)\n\t\twhile (rte_ring_sc_dequeue_bulk(r, burst, size) != 0)\n\t\t\trte_pause();\n\tconst uint64_t sc_end = rte_rdtsc();\n\n\tconst uint64_t mc_start = rte_rdtsc();\n\tfor (i = 0; i < iterations; i++)\n\t\twhile (rte_ring_mc_dequeue_bulk(r, burst, size) != 0)\n\t\t\trte_pause();\n\tconst uint64_t mc_end = rte_rdtsc();\n\n\tparams->spsc = ((double)(sc_end - sc_start))/(iterations*size);\n\tparams->mpmc = ((double)(mc_end - mc_start))/(iterations*size);\n\treturn 0;\n}\n\n/*\n * Function that calls the enqueue and dequeue bulk functions on pairs of cores.\n * used to measure ring perf between hyperthreads, cores and sockets.\n */\nstatic void\nrun_on_core_pair(struct lcore_pair *cores,\n\t\tlcore_function_t f1, lcore_function_t f2)\n{\n\tstruct thread_params param1 = {0}, param2 = {0};\n\tunsigned i;\n\tfor (i = 0; i < sizeof(bulk_sizes)/sizeof(bulk_sizes[0]); i++) {\n\t\tlcore_count = 0;\n\t\tparam1.size = param2.size = bulk_sizes[i];\n\t\tif (cores->c1 == rte_get_master_lcore()) {\n\t\t\trte_eal_remote_launch(f2, ¶m2, cores->c2);\n\t\t\tf1(¶m1);\n\t\t\trte_eal_wait_lcore(cores->c2);\n\t\t} else {\n\t\t\trte_eal_remote_launch(f1, ¶m1, cores->c1);\n\t\t\trte_eal_remote_launch(f2, ¶m2, cores->c2);\n\t\t\trte_eal_wait_lcore(cores->c1);\n\t\t\trte_eal_wait_lcore(cores->c2);\n\t\t}\n\t\tprintf(\"SP/SC bulk enq/dequeue (size: %u): %.2F\\n\", bulk_sizes[i],\n\t\t\t\tparam1.spsc + param2.spsc);\n\t\tprintf(\"MP/MC bulk enq/dequeue (size: %u): %.2F\\n\", bulk_sizes[i],\n\t\t\t\tparam1.mpmc + param2.mpmc);\n\t}\n}\n\n/*\n * Test function that determines how long an enqueue + dequeue of a single item\n * takes on a single lcore. Result is for comparison with the bulk enq+deq.\n */\nstatic void\ntest_single_enqueue_dequeue(void)\n{\n\tconst unsigned iter_shift = 24;\n\tconst unsigned iterations = 1<> iter_shift);\n\tprintf(\"MP/MC single enq/dequeue: %\"PRIu64\"\\n\",\n\t\t\t(mc_end-mc_start) >> iter_shift);\n}\n\n/*\n * Test that does both enqueue and dequeue on a core using the burst() API calls\n * instead of the bulk() calls used in other tests. Results should be the same\n * as for the bulk function called on a single lcore.\n */\nstatic void\ntest_burst_enqueue_dequeue(void)\n{\n\tconst unsigned iter_shift = 23;\n\tconst unsigned iterations = 1<> iter_shift) / bulk_sizes[sz];\n\t\tuint64_t sc_avg = ((sc_end-sc_start) >> iter_shift) / bulk_sizes[sz];\n\n\t\tprintf(\"SP/SC burst enq/dequeue (size: %u): %\"PRIu64\"\\n\", bulk_sizes[sz],\n\t\t\t\tsc_avg);\n\t\tprintf(\"MP/MC burst enq/dequeue (size: %u): %\"PRIu64\"\\n\", bulk_sizes[sz],\n\t\t\t\tmc_avg);\n\t}\n}\n\n/* Times enqueue and dequeue on a single lcore */\nstatic void\ntest_bulk_enqueue_dequeue(void)\n{\n\tconst unsigned iter_shift = 23;\n\tconst unsigned iterations = 1<\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n/*\n * rwlock test\n * ===========\n *\n * - There is a global rwlock and a table of rwlocks (one per lcore).\n *\n * - The test function takes all of these locks and launches the\n * ``test_rwlock_per_core()`` function on each core (except the master).\n *\n * - The function takes the global write lock, display something,\n * then releases the global lock.\n * - Then, it takes the per-lcore write lock, display something, and\n * releases the per-core lock.\n * - Finally, a read lock is taken during 100 ms, then released.\n *\n * - The main function unlocks the per-lcore locks sequentially and\n * waits between each lock. This triggers the display of a message\n * for each core, in the correct order.\n *\n * Then, it tries to take the global write lock and display the last\n * message. The autotest script checks that the message order is correct.\n */\n\nstatic rte_rwlock_t sl;\nstatic rte_rwlock_t sl_tab[RTE_MAX_LCORE];\n\nstatic int\ntest_rwlock_per_core(__attribute__((unused)) void *arg)\n{\n\trte_rwlock_write_lock(&sl);\n\tprintf(\"Global write lock taken on core %u\\n\", rte_lcore_id());\n\trte_rwlock_write_unlock(&sl);\n\n\trte_rwlock_write_lock(&sl_tab[rte_lcore_id()]);\n\tprintf(\"Hello from core %u !\\n\", rte_lcore_id());\n\trte_rwlock_write_unlock(&sl_tab[rte_lcore_id()]);\n\n\trte_rwlock_read_lock(&sl);\n\tprintf(\"Global read lock taken on core %u\\n\", rte_lcore_id());\n\trte_delay_ms(100);\n\tprintf(\"Release global read lock on core %u\\n\", rte_lcore_id());\n\trte_rwlock_read_unlock(&sl);\n\n\treturn 0;\n}\n\nstatic int\ntest_rwlock(void)\n{\n\tint i;\n\n\trte_rwlock_init(&sl);\n\tfor (i=0; i\n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n#include \n#include \n#include \n#include \n#include \n\n\n#define SUBPORT 0\n#define PIPE 1\n#define TC 2\n#define QUEUE 3\n\nstatic struct rte_sched_subport_params subport_param[] = {\n\t{\n\t\t.tb_rate = 1250000000,\n\t\t.tb_size = 1000000,\n\n\t\t.tc_rate = {1250000000, 1250000000, 1250000000, 1250000000},\n\t\t.tc_period = 10,\n\t},\n};\n\nstatic struct rte_sched_pipe_params pipe_profile[] = {\n\t{ /* Profile #0 */\n\t\t.tb_rate = 305175,\n\t\t.tb_size = 1000000,\n\n\t\t.tc_rate = {305175, 305175, 305175, 305175},\n\t\t.tc_period = 40,\n\n\t\t.wrr_weights = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},\n\t},\n};\n\nstatic struct rte_sched_port_params port_param = {\n\t.socket = 0, /* computed */\n\t.rate = 0, /* computed */\n\t.mtu = 1522,\n\t.frame_overhead = RTE_SCHED_FRAME_OVERHEAD_DEFAULT,\n\t.n_subports_per_port = 1,\n\t.n_pipes_per_subport = 4096,\n\t.qsize = {64, 64, 64, 64},\n\t.pipe_profiles = pipe_profile,\n\t.n_pipe_profiles = 1,\n};\n\n#define NB_MBUF 32\n#define MBUF_DATA_SZ (2048 + RTE_PKTMBUF_HEADROOM)\n#define MEMPOOL_CACHE_SZ 0\n#define SOCKET 0\n\n\nstatic struct rte_mempool *\ncreate_mempool(void)\n{\n\tstruct rte_mempool * mp;\n\n\tmp = rte_mempool_lookup(\"test_sched\");\n\tif (!mp)\n\t\tmp = rte_pktmbuf_pool_create(\"test_sched\", NB_MBUF,\n\t\t\tMEMPOOL_CACHE_SZ, 0, MBUF_DATA_SZ, SOCKET);\n\n\treturn mp;\n}\n\nstatic void\nprepare_pkt(struct rte_mbuf *mbuf)\n{\n\tstruct ether_hdr *eth_hdr;\n\tstruct vlan_hdr *vlan1, *vlan2;\n\tstruct ipv4_hdr *ip_hdr;\n\n\t/* Simulate a classifier */\n\teth_hdr = rte_pktmbuf_mtod(mbuf, struct ether_hdr *);\n\tvlan1 = (struct vlan_hdr *)(ð_hdr->ether_type );\n\tvlan2 = (struct vlan_hdr *)((uintptr_t)ð_hdr->ether_type + sizeof(struct vlan_hdr));\n\teth_hdr = (struct ether_hdr *)((uintptr_t)ð_hdr->ether_type + 2 *sizeof(struct vlan_hdr));\n\tip_hdr = (struct ipv4_hdr *)((uintptr_t)eth_hdr + sizeof(eth_hdr->ether_type));\n\n\tvlan1->vlan_tci = rte_cpu_to_be_16(SUBPORT);\n\tvlan2->vlan_tci = rte_cpu_to_be_16(PIPE);\n\teth_hdr->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);\n\tip_hdr->dst_addr = IPv4(0,0,TC,QUEUE);\n\n\n\trte_sched_port_pkt_write(mbuf, SUBPORT, PIPE, TC, QUEUE, e_RTE_METER_YELLOW);\n\n\t/* 64 byte packet */\n\tmbuf->pkt_len = 60;\n\tmbuf->data_len = 60;\n}\n\n\n/**\n * test main entrance for library sched\n */\nstatic int\ntest_sched(void)\n{\n\tstruct rte_mempool *mp = NULL;\n\tstruct rte_sched_port *port = NULL;\n\tuint32_t pipe;\n\tstruct rte_mbuf *in_mbufs[10];\n\tstruct rte_mbuf *out_mbufs[10];\n\tint i;\n\n\tint err;\n\n\tmp = create_mempool();\n\tTEST_ASSERT_NOT_NULL(mp, \"Error creating mempool\\n\");\n\n\tport_param.socket = 0;\n\tport_param.rate = (uint64_t) 10000 * 1000 * 1000 / 8;\n\n\tport = rte_sched_port_config(&port_param);\n\tTEST_ASSERT_NOT_NULL(port, \"Error config sched port\\n\");\n\n\terr = rte_sched_subport_config(port, SUBPORT, subport_param);\n\tTEST_ASSERT_SUCCESS(err, \"Error config sched, err=%d\\n\", err);\n\n\tfor (pipe = 0; pipe < port_param.n_pipes_per_subport; pipe ++) {\n\t\terr = rte_sched_pipe_config(port, SUBPORT, pipe, 0);\n\t\tTEST_ASSERT_SUCCESS(err, \"Error config sched pipe %u, err=%d\\n\", pipe, err);\n\t}\n\n\tfor (i = 0; i < 10; i++) {\n\t\tin_mbufs[i] = rte_pktmbuf_alloc(mp);\n\t\tTEST_ASSERT_NOT_NULL(in_mbufs[i], \"Packet allocation failed\\n\");\n\t\tprepare_pkt(in_mbufs[i]);\n\t}\n\n\n\terr = rte_sched_port_enqueue(port, in_mbufs, 10);\n\tTEST_ASSERT_EQUAL(err, 10, \"Wrong enqueue, err=%d\\n\", err);\n\n\terr = rte_sched_port_dequeue(port, out_mbufs, 10);\n\tTEST_ASSERT_EQUAL(err, 10, \"Wrong dequeue, err=%d\\n\", err);\n\n\tfor (i = 0; i < 10; i++) {\n\t\tenum rte_meter_color color;\n\t\tuint32_t subport, traffic_class, queue;\n\n\t\tcolor = rte_sched_port_pkt_read_color(out_mbufs[i]);\n\t\tTEST_ASSERT_EQUAL(color, e_RTE_METER_YELLOW, \"Wrong color\\n\");\n\n\t\trte_sched_port_pkt_read_tree_path(out_mbufs[i],\n\t\t\t\t&subport, &pipe, &traffic_class, &queue);\n\n\t\tTEST_ASSERT_EQUAL(subport, SUBPORT, \"Wrong subport\\n\");\n\t\tTEST_ASSERT_EQUAL(pipe, PIPE, \"Wrong pipe\\n\");\n\t\tTEST_ASSERT_EQUAL(traffic_class, TC, \"Wrong traffic_class\\n\");\n\t\tTEST_ASSERT_EQUAL(queue, QUEUE, \"Wrong queue\\n\");\n\n\t}\n\n\n\tstruct rte_sched_subport_stats subport_stats;\n\tuint32_t tc_ov;\n\trte_sched_subport_read_stats(port, SUBPORT, &subport_stats, &tc_ov);\n#if 0\n\tTEST_ASSERT_EQUAL(subport_stats.n_pkts_tc[TC-1], 10, \"Wrong subport stats\\n\");\n#endif\n\tstruct rte_sched_queue_stats queue_stats;\n\tuint16_t qlen;\n\trte_sched_queue_read_stats(port, QUEUE, &queue_stats, &qlen);\n#if 0\n\tTEST_ASSERT_EQUAL(queue_stats.n_pkts, 10, \"Wrong queue stats\\n\");\n#endif\n\n\trte_sched_port_free(port);\n\n\treturn 0;\n}\n\nstatic struct test_command sched_cmd = {\n\t.command = \"sched_autotest\",\n\t.callback = test_sched,\n};\nREGISTER_TEST_COMMAND(sched_cmd);\n" }, { "path": "app/test/test_spinlock.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"test.h\"\n\n/*\n * Spinlock test\n * =============\n *\n * - There is a global spinlock and a table of spinlocks (one per lcore).\n *\n * - The test function takes all of these locks and launches the\n * ``test_spinlock_per_core()`` function on each core (except the master).\n *\n * - The function takes the global lock, display something, then releases\n * the global lock.\n * - The function takes the per-lcore lock, display something, then releases\n * the per-core lock.\n *\n * - The main function unlocks the per-lcore locks sequentially and\n * waits between each lock. This triggers the display of a message\n * for each core, in the correct order. The autotest script checks that\n * this order is correct.\n *\n * - A load test is carried out, with all cores attempting to lock a single lock\n * multiple times\n */\n\nstatic rte_spinlock_t sl, sl_try;\nstatic rte_spinlock_t sl_tab[RTE_MAX_LCORE];\nstatic rte_spinlock_recursive_t slr;\nstatic unsigned count = 0;\n\nstatic rte_atomic32_t synchro;\n\nstatic int\ntest_spinlock_per_core(__attribute__((unused)) void *arg)\n{\n\trte_spinlock_lock(&sl);\n\tprintf(\"Global lock taken on core %u\\n\", rte_lcore_id());\n\trte_spinlock_unlock(&sl);\n\n\trte_spinlock_lock(&sl_tab[rte_lcore_id()]);\n\tprintf(\"Hello from core %u !\\n\", rte_lcore_id());\n\trte_spinlock_unlock(&sl_tab[rte_lcore_id()]);\n\n\treturn 0;\n}\n\nstatic int\ntest_spinlock_recursive_per_core(__attribute__((unused)) void *arg)\n{\n\tunsigned id = rte_lcore_id();\n\n\trte_spinlock_recursive_lock(&slr);\n\tprintf(\"Global recursive lock taken on core %u - count = %d\\n\",\n\t id, slr.count);\n\trte_spinlock_recursive_lock(&slr);\n\tprintf(\"Global recursive lock taken on core %u - count = %d\\n\",\n\t id, slr.count);\n\trte_spinlock_recursive_lock(&slr);\n\tprintf(\"Global recursive lock taken on core %u - count = %d\\n\",\n\t id, slr.count);\n\n\tprintf(\"Hello from within recursive locks from core %u !\\n\", id);\n\n\trte_spinlock_recursive_unlock(&slr);\n\tprintf(\"Global recursive lock released on core %u - count = %d\\n\",\n\t id, slr.count);\n\trte_spinlock_recursive_unlock(&slr);\n\tprintf(\"Global recursive lock released on core %u - count = %d\\n\",\n\t id, slr.count);\n\trte_spinlock_recursive_unlock(&slr);\n\tprintf(\"Global recursive lock released on core %u - count = %d\\n\",\n\t id, slr.count);\n\n\treturn 0;\n}\n\nstatic rte_spinlock_t lk = RTE_SPINLOCK_INITIALIZER;\nstatic uint64_t lock_count[RTE_MAX_LCORE] = {0};\n\n#define TIME_S 5\n\nstatic int\nload_loop_fn(void *func_param)\n{\n\tuint64_t time_diff = 0, begin;\n\tuint64_t hz = rte_get_timer_hz();\n\tuint64_t lcount = 0;\n\tconst int use_lock = *(int*)func_param;\n\tconst unsigned lcore = rte_lcore_id();\n\n\t/* wait synchro for slaves */\n\tif (lcore != rte_get_master_lcore())\n\t\twhile (rte_atomic32_read(&synchro) == 0);\n\n\tbegin = rte_get_timer_cycles();\n\twhile (time_diff / hz < TIME_S) {\n\t\tif (use_lock)\n\t\t\trte_spinlock_lock(&lk);\n\t\tlcount++;\n\t\tif (use_lock)\n\t\t\trte_spinlock_unlock(&lk);\n\t\t/* delay to make lock duty cycle slighlty realistic */\n\t\trte_delay_us(1);\n\t\ttime_diff = rte_get_timer_cycles() - begin;\n\t}\n\tlock_count[lcore] = lcount;\n\treturn 0;\n}\n\nstatic int\ntest_spinlock_perf(void)\n{\n\tunsigned int i;\n\tuint64_t total = 0;\n\tint lock = 0;\n\tconst unsigned lcore = rte_lcore_id();\n\n\tprintf(\"\\nTest with no lock on single core...\\n\");\n\tload_loop_fn(&lock);\n\tprintf(\"Core [%u] count = %\"PRIu64\"\\n\", lcore, lock_count[lcore]);\n\tmemset(lock_count, 0, sizeof(lock_count));\n\n\tprintf(\"\\nTest with lock on single core...\\n\");\n\tlock = 1;\n\tload_loop_fn(&lock);\n\tprintf(\"Core [%u] count = %\"PRIu64\"\\n\", lcore, lock_count[lcore]);\n\tmemset(lock_count, 0, sizeof(lock_count));\n\n\tprintf(\"\\nTest with lock on %u cores...\\n\", rte_lcore_count());\n\n\t/* Clear synchro and start slaves */\n\trte_atomic32_set(&synchro, 0);\n\trte_eal_mp_remote_launch(load_loop_fn, &lock, SKIP_MASTER);\n\n\t/* start synchro and launch test on master */\n\trte_atomic32_set(&synchro, 1);\n\tload_loop_fn(&lock);\n\n\trte_eal_mp_wait_lcore();\n\n\tRTE_LCORE_FOREACH(i) {\n\t\tprintf(\"Core [%u] count = %\"PRIu64\"\\n\", i, lock_count[i]);\n\t\ttotal += lock_count[i];\n\t}\n\n\tprintf(\"Total count = %\"PRIu64\"\\n\", total);\n\n\treturn 0;\n}\n\n/*\n * Use rte_spinlock_trylock() to trylock a spinlock object,\n * If it could not lock the object sucessfully, it would\n * return immediately and the variable of \"count\" would be\n * increased by one per times. the value of \"count\" could be\n * checked as the result later.\n */\nstatic int\ntest_spinlock_try(__attribute__((unused)) void *arg)\n{\n\tif (rte_spinlock_trylock(&sl_try) == 0) {\n\t\trte_spinlock_lock(&sl);\n\t\tcount ++;\n\t\trte_spinlock_unlock(&sl);\n\t}\n\n\treturn 0;\n}\n\n\n/*\n * Test rte_eal_get_lcore_state() in addition to spinlocks\n * as we have \"waiting\" then \"running\" lcores.\n */\nstatic int\ntest_spinlock(void)\n{\n\tint ret = 0;\n\tint i;\n\n\t/* slave cores should be waiting: print it */\n\tRTE_LCORE_FOREACH_SLAVE(i) {\n\t\tprintf(\"lcore %d state: %d\\n\", i,\n\t\t (int) rte_eal_get_lcore_state(i));\n\t}\n\n\trte_spinlock_init(&sl);\n\trte_spinlock_init(&sl_try);\n\trte_spinlock_recursive_init(&slr);\n\tfor (i=0; i\n#include \n#include \n#include \n#include \n\n#include \n\n#include \"test.h\"\n\n#define LOG(...) do {\\\n\tfprintf(stderr, \"%s() ln %d: \", __func__, __LINE__); \\\n\tfprintf(stderr, __VA_ARGS__); \\\n} while(0)\n\n#define DATA_BYTE 'a'\n\nstatic int\ntest_rte_strsplit(void)\n{\n\tint i;\n\tdo {\n\t\t/* =======================================================\n\t\t * split a mac address correct number of splits requested\n\t\t * =======================================================*/\n\t\tchar test_string[] = \"54:65:76:87:98:90\";\n\t\tchar *splits[6];\n\n\t\tLOG(\"Source string: '%s', to split on ':'\\n\", test_string);\n\t\tif (rte_strsplit(test_string, sizeof(test_string),\n\t\t\t\tsplits, 6, ':') != 6) {\n\t\t\tLOG(\"Error splitting mac address\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tfor (i = 0; i < 6; i++)\n\t\t\tLOG(\"Token %d = %s\\n\", i + 1, splits[i]);\n\t} while (0);\n\n\n\tdo {\n\t\t/* =======================================================\n\t\t * split on spaces smaller number of splits requested\n\t\t * =======================================================*/\n\t\tchar test_string[] = \"54 65 76 87 98 90\";\n\t\tchar *splits[6];\n\n\t\tLOG(\"Source string: '%s', to split on ' '\\n\", test_string);\n\t\tif (rte_strsplit(test_string, sizeof(test_string),\n\t\t\t\tsplits, 3, ' ') != 3) {\n\t\t\tLOG(\"Error splitting mac address for max 2 splits\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tfor (i = 0; i < 3; i++)\n\t\t\tLOG(\"Token %d = %s\\n\", i + 1, splits[i]);\n\t} while (0);\n\n\tdo {\n\t\t/* =======================================================\n\t\t * split on commas - more splits than commas requested\n\t\t * =======================================================*/\n\t\tchar test_string[] = \"a,b,c,d\";\n\t\tchar *splits[6];\n\n\t\tLOG(\"Source string: '%s', to split on ','\\n\", test_string);\n\t\tif (rte_strsplit(test_string, sizeof(test_string),\n\t\t\t\tsplits, 6, ',') != 4) {\n\t\t\tLOG(\"Error splitting %s on ','\\n\", test_string);\n\t\t\treturn -1;\n\t\t}\n\t\tfor (i = 0; i < 4; i++)\n\t\t\tLOG(\"Token %d = %s\\n\", i + 1, splits[i]);\n\t} while(0);\n\n\tdo {\n\t\t/* =======================================================\n\t\t * Try splitting on non-existent character.\n\t\t * =======================================================*/\n\t\tchar test_string[] = \"a,b,c,d\";\n\t\tchar *splits[6];\n\n\t\tLOG(\"Source string: '%s', to split on ' '\\n\", test_string);\n\t\tif (rte_strsplit(test_string, sizeof(test_string),\n\t\t\t\tsplits, 6, ' ') != 1) {\n\t\t\tLOG(\"Error splitting %s on ' '\\n\", test_string);\n\t\t\treturn -1;\n\t\t}\n\t\tLOG(\"String not split\\n\");\n\t} while(0);\n\n\tdo {\n\t\t/* =======================================================\n\t\t * Invalid / edge case parameter checks\n\t\t * =======================================================*/\n\t\tchar test_string[] = \"a,b,c,d\";\n\t\tchar *splits[6];\n\n\t\tif (rte_strsplit(NULL, 0, splits, 6, ',') >= 0\n\t\t\t\t|| errno != EINVAL){\n\t\t\tLOG(\"Error: rte_strsplit accepted NULL string parameter\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (rte_strsplit(test_string, sizeof(test_string), NULL, 0, ',') >= 0\n\t\t\t\t|| errno != EINVAL){\n\t\t\tLOG(\"Error: rte_strsplit accepted NULL array parameter\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\terrno = 0;\n\t\tif (rte_strsplit(test_string, 0, splits, 6, ',') != 0 || errno != 0) {\n\t\t\tLOG(\"Error: rte_strsplit did not accept 0 length string\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (rte_strsplit(test_string, sizeof(test_string), splits, 0, ',') != 0\n\t\t\t\t|| errno != 0) {\n\t\t\tLOG(\"Error: rte_strsplit did not accept 0 length array\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tLOG(\"Parameter test cases passed\\n\");\n\t} while(0);\n\n\tLOG(\"%s - PASSED\\n\", __func__);\n\treturn 0;\n}\n\nstatic int\ntest_string_fns(void)\n{\n\tif (test_rte_strsplit() < 0)\n\t\treturn -1;\n\treturn 0;\n}\n\nstatic struct test_command string_cmd = {\n\t.command = \"string_autotest\",\n\t.callback = test_string_fns,\n};\nREGISTER_TEST_COMMAND(string_cmd);\n" }, { "path": "app/test/test_table.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \"test.h\"\n#include \"test_table.h\"\n#include \"test_table_pipeline.h\"\n#include \"test_table_ports.h\"\n#include \"test_table_tables.h\"\n#include \"test_table_combined.h\"\n#include \"test_table_acl.h\"\n\n/* Global variables */\nstruct rte_pipeline *p;\nstruct rte_ring *rings_rx[N_PORTS];\nstruct rte_ring *rings_tx[N_PORTS];\nstruct rte_mempool *pool = NULL;\n\nuint32_t port_in_id[N_PORTS];\nuint32_t port_out_id[N_PORTS];\nuint32_t port_out_id_type[3];\nuint32_t table_id[N_PORTS*2];\nuint64_t override_hit_mask = 0xFFFFFFFF;\nuint64_t override_miss_mask = 0xFFFFFFFF;\nuint64_t non_reserved_actions_hit = 0;\nuint64_t non_reserved_actions_miss = 0;\nuint8_t connect_miss_action_to_port_out = 0;\nuint8_t connect_miss_action_to_table = 0;\nuint32_t table_entry_default_action = RTE_PIPELINE_ACTION_DROP;\nuint32_t table_entry_hit_action = RTE_PIPELINE_ACTION_PORT;\nuint32_t table_entry_miss_action = RTE_PIPELINE_ACTION_DROP;\nrte_pipeline_port_in_action_handler port_in_action = NULL;\nrte_pipeline_port_out_action_handler port_out_action = NULL;\nrte_pipeline_table_action_handler_hit action_handler_hit = NULL;\nrte_pipeline_table_action_handler_miss action_handler_miss = NULL;\n\n/* Function prototypes */\nstatic void app_init_rings(void);\nstatic void app_init_mbuf_pools(void);\n\nuint64_t pipeline_test_hash(void *key,\n\t\t__attribute__((unused)) uint32_t key_size,\n\t\t__attribute__((unused)) uint64_t seed)\n{\n\tuint32_t *k32 = (uint32_t *) key;\n\tuint32_t ip_dst = rte_be_to_cpu_32(k32[0]);\n\tuint64_t signature = ip_dst;\n\n\treturn signature;\n}\n\nstatic void\napp_init_mbuf_pools(void)\n{\n\t/* Init the buffer pool */\n\tprintf(\"Getting/Creating the mempool ...\\n\");\n\tpool = rte_mempool_lookup(\"mempool\");\n\tif (!pool) {\n\t\tpool = rte_pktmbuf_pool_create(\n\t\t\t\"mempool\",\n\t\t\tPOOL_SIZE,\n\t\t\tPOOL_CACHE_SIZE, 0, POOL_BUFFER_SIZE,\n\t\t\t0);\n\t\tif (pool == NULL)\n\t\t\trte_panic(\"Cannot create mbuf pool\\n\");\n\t}\n}\n\nstatic void\napp_init_rings(void)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tchar name[32];\n\n\t\tsnprintf(name, sizeof(name), \"app_ring_rx_%u\", i);\n\t\trings_rx[i] = rte_ring_lookup(name);\n\t\tif (rings_rx[i] == NULL) {\n\t\t\trings_rx[i] = rte_ring_create(\n\t\t\t\tname,\n\t\t\t\tRING_RX_SIZE,\n\t\t\t\t0,\n\t\t\t\tRING_F_SP_ENQ | RING_F_SC_DEQ);\n\t\t}\n\t\tif (rings_rx[i] == NULL)\n\t\t\trte_panic(\"Cannot create RX ring %u\\n\", i);\n\t}\n\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tchar name[32];\n\n\t\tsnprintf(name, sizeof(name), \"app_ring_tx_%u\", i);\n\t\trings_tx[i] = rte_ring_lookup(name);\n\t\tif (rings_tx[i] == NULL) {\n\t\t\trings_tx[i] = rte_ring_create(\n\t\t\t\tname,\n\t\t\t\tRING_TX_SIZE,\n\t\t\t\t0,\n\t\t\t\tRING_F_SP_ENQ | RING_F_SC_DEQ);\n\t\t}\n\t\tif (rings_tx[i] == NULL)\n\t\t\trte_panic(\"Cannot create TX ring %u\\n\", i);\n\t}\n\n}\n\nstatic int\ntest_table(void)\n{\n\tint status, failures;\n\tunsigned i;\n\n\tfailures = 0;\n\n\tapp_init_rings();\n\tapp_init_mbuf_pools();\n\n\tprintf(\"\\n\\n\\n\\n************Pipeline tests************\\n\");\n\n\tif (test_table_pipeline() < 0)\n\t\treturn -1;\n\n\tprintf(\"\\n\\n\\n\\n************Port tests************\\n\");\n\tfor (i = 0; i < n_port_tests; i++) {\n\t\tstatus = port_tests[i]();\n\t\tif (status < 0) {\n\t\t\tprintf(\"\\nPort test number %d failed (%d).\\n\", i,\n\t\t\t\tstatus);\n\t\t\tfailures++;\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tprintf(\"\\n\\n\\n\\n************Table tests************\\n\");\n\tfor (i = 0; i < n_table_tests; i++) {\n\t\tstatus = table_tests[i]();\n\t\tif (status < 0) {\n\t\t\tprintf(\"\\nTable test number %d failed (%d).\\n\", i,\n\t\t\t\tstatus);\n\t\t\tfailures++;\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tprintf(\"\\n\\n\\n\\n************Table tests************\\n\");\n\tfor (i = 0; i < n_table_tests_combined; i++) {\n\t\tstatus = table_tests_combined[i]();\n\t\tif (status < 0) {\n\t\t\tprintf(\"\\nCombined table test number %d failed with \"\n\t\t\t\t\"reason number %d.\\n\", i, status);\n\t\t\tfailures++;\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (failures)\n\t\treturn -1;\n\n#ifdef RTE_LIBRTE_ACL\n\tprintf(\"\\n\\n\\n\\n************ACL tests************\\n\");\n\tif (test_table_ACL() < 0)\n\t\treturn -1;\n#endif\n\n\treturn 0;\n}\n\nstatic struct test_command table_cmd = {\n\t.command = \"table_autotest\",\n\t.callback = test_table,\n};\nREGISTER_TEST_COMMAND(table_cmd);\n" }, { "path": "app/test/test_table.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#ifdef RTE_LIBRTE_ACL\n#include \n#endif\n\n#include \n#include \n#include \n\n#ifndef TEST_TABLE_H_\n#define TEST_TABLE_H_\n\n#define RING_SIZE 4096\n#define MAX_BULK 32\n#define N 65536\n#define TIME_S 5\n#define TEST_RING_FULL_EMTPY_ITER 8\n#define N_PORTS 2\n#define N_PKTS 2\n#define N_PKTS_EXT 6\n#define RING_RX rings_rx[0]\n#define RING_RX_2 rings_rx[1]\n#define RING_TX rings_tx[0]\n#define RING_TX_2 rings_tx[1]\n#define PORT_RX_RING_SIZE 128\n#define PORT_TX_RING_SIZE 512\n#define RING_RX_SIZE 128\n#define RING_TX_SIZE 128\n#define POOL_BUFFER_SIZE RTE_MBUF_DEFAULT_BUF_SIZE\n#define POOL_SIZE (32 * 1024)\n#define POOL_CACHE_SIZE 256\n#define BURST_SIZE 8\n#define WORKER_TYPE 1\n#define MAX_DUMMY_PORTS 2\n#define MP_NAME \"dummy_port_mempool\"\n#define MBUF_COUNT (8000 * MAX_DUMMY_PORTS)\n#define MP_CACHE_SZ 256\n#define MP_SOCKET 0\n#define MP_FLAGS 0\n\n/* Macros */\n#define RING_ENQUEUE(ring, value) do {\t\t\t\t\t\\\n\tstruct rte_mbuf *m;\t\t\t\t\t\t\\\n\tuint32_t *k32, *signature;\t\t\t\t\t\\\n\tuint8_t *key;\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tm = rte_pktmbuf_alloc(pool);\t\t\t\t\t\\\n\tif (m == NULL)\t\t\t\t\t\t\t\\\n\t\treturn -1;\t\t\t\t\t\t\\\n\tsignature = RTE_MBUF_METADATA_UINT32_PTR(m, 0);\t\t\t\\\n\tkey = RTE_MBUF_METADATA_UINT8_PTR(m, 32);\t\t\t\\\n\tk32 = (uint32_t *) key;\t\t\t\t\t\t\\\n\tk32[0] = (value);\t\t\t\t\t\t\\\n\t*signature = pipeline_test_hash(key, 0, 0);\t\t\t\\\n\trte_ring_enqueue((ring), m);\t\t\t\t\t\\\n} while (0)\n\n#define RUN_PIPELINE(pipeline) do {\t\t\t\t\t\\\n\trte_pipeline_run((pipeline));\t\t\t\t\t\\\n\trte_pipeline_flush((pipeline));\t\t\t\t\t\\\n} while (0)\n\n#define VERIFY(var, value) do {\t\t\t\t\t\t\\\n\tif ((var) != -(value))\t\t\t\t\t\t\\\n\t\treturn var;\t\t\t\t\t\t\\\n} while (0)\n\n#define VERIFY_TRAFFIC(ring, sent, expected) do {\t\t\t\\\n\tunsigned i, n = 0;\t\t\t\t\t\t\\\n\tvoid *mbuf = NULL;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tfor (i = 0; i < (sent); i++) {\t\t\t\t\t\\\n\t\tif (!rte_ring_dequeue((ring), &mbuf)) {\t\t\t\\\n\t\t\tif (mbuf == NULL)\t\t\t\t\\\n\t\t\t\tcontinue;\t\t\t\t\\\n\t\t\tn++;\t\t\t\t\t\t\\\n\t\t\trte_pktmbuf_free((struct rte_mbuf *)mbuf);\t\\\n\t\t}\t\t\t\t\t\t\t\\\n\t\telse\t\t\t\t\t\t\t\\\n\t\t\tbreak;\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n\tprintf(\"Expected %d, got %d\\n\", expected, n);\t\t\t\\\n\tif (n != (expected)) {\t\t\t\t\t\t\\\n\t\treturn -21;\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n} while (0)\n\n/* Function definitions */\nuint64_t pipeline_test_hash(\n\tvoid *key,\n\t__attribute__((unused)) uint32_t key_size,\n\t__attribute__((unused)) uint64_t seed);\n\n/* Extern variables */\nextern struct rte_pipeline *p;\nextern struct rte_ring *rings_rx[N_PORTS];\nextern struct rte_ring *rings_tx[N_PORTS];\nextern struct rte_mempool *pool;\nextern uint32_t port_in_id[N_PORTS];\nextern uint32_t port_out_id[N_PORTS];\nextern uint32_t port_out_id_type[3];\nextern uint32_t table_id[N_PORTS*2];\nextern uint64_t override_hit_mask;\nextern uint64_t override_miss_mask;\nextern uint64_t non_reserved_actions_hit;\nextern uint64_t non_reserved_actions_miss;\nextern uint8_t connect_miss_action_to_port_out;\nextern uint8_t connect_miss_action_to_table;\nextern uint32_t table_entry_default_action;\nextern uint32_t table_entry_hit_action;\nextern uint32_t table_entry_miss_action;\nextern rte_pipeline_port_in_action_handler port_in_action;\nextern rte_pipeline_port_out_action_handler port_out_action;\nextern rte_pipeline_table_action_handler_hit action_handler_hit;\nextern rte_pipeline_table_action_handler_miss action_handler_miss;\n\n/* Global data types */\nstruct manage_ops {\n\tuint32_t op_id;\n\tvoid *op_data;\n\tint expected_result;\n};\n\n/* Internal pipeline structures */\nstruct rte_port_in {\n\tstruct rte_port_in_ops ops;\n\tuint32_t burst_size;\n\tuint32_t table_id;\n\tvoid *h_port;\n};\n\nstruct rte_port_out {\n\tstruct rte_port_out_ops ops;\n\tvoid *h_port;\n};\n\nstruct rte_table {\n\tstruct rte_table_ops ops;\n\trte_pipeline_table_action_handler_hit f_action;\n\tuint32_t table_next_id;\n\tuint32_t table_next_id_valid;\n\tuint8_t actions_lookup_miss[RTE_CACHE_LINE_SIZE];\n\tuint32_t action_data_size;\n\tvoid *h_table;\n};\n\n#define RTE_PIPELINE_MAX_NAME_SZ 124\n\nstruct rte_pipeline {\n\tchar name[RTE_PIPELINE_MAX_NAME_SZ];\n\tuint32_t socket_id;\n\tstruct rte_port_in ports_in[16];\n\tstruct rte_port_out ports_out[16];\n\tstruct rte_table tables[64];\n\tuint32_t num_ports_in;\n\tuint32_t num_ports_out;\n\tuint32_t num_tables;\n\tstruct rte_mbuf *pkts[RTE_PORT_IN_BURST_SIZE_MAX];\n\tstruct rte_table_entry *actions[RTE_PORT_IN_BURST_SIZE_MAX];\n\tuint64_t mask_action[64];\n\tuint32_t mask_actions;\n};\n#endif\n" }, { "path": "app/test/test_table_acl.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \"test_table.h\"\n#include \"test_table_acl.h\"\n\n#define IPv4(a, b, c, d) ((uint32_t)(((a) & 0xff) << 24) |\t\t\\\n\t(((b) & 0xff) << 16) |\t\t\t\t\t\t\\\n\t(((c) & 0xff) << 8) |\t\t\t\t\t\t\\\n\t((d) & 0xff))\n\n/*\n * Rule and trace formats definitions.\n **/\n\nstruct ipv4_5tuple {\n\tuint8_t proto;\n\tuint32_t ip_src;\n\tuint32_t ip_dst;\n\tuint16_t port_src;\n\tuint16_t port_dst;\n};\n\nenum {\n\tPROTO_FIELD_IPV4,\n\tSRC_FIELD_IPV4,\n\tDST_FIELD_IPV4,\n\tSRCP_FIELD_IPV4,\n\tDSTP_FIELD_IPV4,\n\tNUM_FIELDS_IPV4\n};\n\nstruct rte_acl_field_def ipv4_defs[NUM_FIELDS_IPV4] = {\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t.size = sizeof(uint8_t),\n\t\t.field_index = PROTO_FIELD_IPV4,\n\t\t.input_index = PROTO_FIELD_IPV4,\n\t\t.offset = offsetof(struct ipv4_5tuple, proto),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = SRC_FIELD_IPV4,\n\t\t.input_index = SRC_FIELD_IPV4,\n\t\t.offset = offsetof(struct ipv4_5tuple, ip_src),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = DST_FIELD_IPV4,\n\t\t.input_index = DST_FIELD_IPV4,\n\t\t.offset = offsetof(struct ipv4_5tuple, ip_dst),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = SRCP_FIELD_IPV4,\n\t\t.input_index = SRCP_FIELD_IPV4,\n\t\t.offset = offsetof(struct ipv4_5tuple, port_src),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = DSTP_FIELD_IPV4,\n\t\t.input_index = SRCP_FIELD_IPV4,\n\t\t.offset = offsetof(struct ipv4_5tuple, port_dst),\n\t},\n};\n\nstruct rte_table_acl_rule_add_params table_acl_IPv4_rule;\n\ntypedef int (*parse_5tuple)(char *text,\n\tstruct rte_table_acl_rule_add_params *rule);\n\n/*\n* The order of the fields in the rule string after the initial '@'\n*/\nenum {\n\tCB_FLD_SRC_ADDR,\n\tCB_FLD_DST_ADDR,\n\tCB_FLD_SRC_PORT_RANGE,\n\tCB_FLD_DST_PORT_RANGE,\n\tCB_FLD_PROTO,\n\tCB_FLD_NUM,\n};\n\n\n#define GET_CB_FIELD(in, fd, base, lim, dlm)\t\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\tunsigned long val;\t\t\t\t\t\t\\\n\tchar *end;\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\terrno = 0;\t\t\t\t\t\t\t\\\n\tval = strtoul((in), &end, (base));\t\t\t\t\\\n\tif (errno != 0 || end[0] != (dlm) || val > (lim))\t\t\\\n\t\treturn -EINVAL;\t\t\t\t\t\t\\\n\t(fd) = (typeof(fd)) val;\t\t\t\t\t\\\n\t(in) = end + 1;\t\t\t\t\t\t\t\\\n} while (0)\n\n\n\n\nstatic int\nparse_ipv4_net(const char *in, uint32_t *addr, uint32_t *mask_len)\n{\n\tuint8_t a, b, c, d, m;\n\n\tGET_CB_FIELD(in, a, 0, UINT8_MAX, '.');\n\tGET_CB_FIELD(in, b, 0, UINT8_MAX, '.');\n\tGET_CB_FIELD(in, c, 0, UINT8_MAX, '.');\n\tGET_CB_FIELD(in, d, 0, UINT8_MAX, '/');\n\tGET_CB_FIELD(in, m, 0, sizeof(uint32_t) * CHAR_BIT, 0);\n\n\taddr[0] = IPv4(a, b, c, d);\n\tmask_len[0] = m;\n\n\treturn 0;\n}\n\nstatic int\nparse_port_range(const char *in, uint16_t *port_low, uint16_t *port_high)\n{\n\tuint16_t a, b;\n\n\tGET_CB_FIELD(in, a, 0, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, b, 0, UINT16_MAX, 0);\n\n\tport_low[0] = a;\n\tport_high[0] = b;\n\n\treturn 0;\n}\n\nstatic int\nparse_cb_ipv4_rule(char *str, struct rte_table_acl_rule_add_params *v)\n{\n\tint i, rc;\n\tchar *s, *sp, *in[CB_FLD_NUM];\n\tstatic const char *dlm = \" \\t\\n\";\n\n\t/*\n\t** Skip leading '@'\n\t*/\n\tif (strchr(str, '@') != str)\n\t\treturn -EINVAL;\n\n\ts = str + 1;\n\n\t/*\n\t* Populate the 'in' array with the location of each\n\t* field in the string we're parsing\n\t*/\n\tfor (i = 0; i != DIM(in); i++) {\n\t\tin[i] = strtok_r(s, dlm, &sp);\n\t\tif (in[i] == NULL)\n\t\t\treturn -EINVAL;\n\t\ts = NULL;\n\t}\n\n\t/* Parse x.x.x.x/x */\n\trc = parse_ipv4_net(in[CB_FLD_SRC_ADDR],\n\t\t&v->field_value[SRC_FIELD_IPV4].value.u32,\n\t\t&v->field_value[SRC_FIELD_IPV4].mask_range.u32);\n\tif (rc != 0) {\n\t\tRTE_LOG(ERR, PIPELINE, \"failed to read src address/mask: %s\\n\",\n\t\t\tin[CB_FLD_SRC_ADDR]);\n\t\treturn rc;\n\t}\n\n\tprintf(\"V=%u, mask=%u\\n\", v->field_value[SRC_FIELD_IPV4].value.u32,\n\t\tv->field_value[SRC_FIELD_IPV4].mask_range.u32);\n\n\t/* Parse x.x.x.x/x */\n\trc = parse_ipv4_net(in[CB_FLD_DST_ADDR],\n\t\t&v->field_value[DST_FIELD_IPV4].value.u32,\n\t\t&v->field_value[DST_FIELD_IPV4].mask_range.u32);\n\tif (rc != 0) {\n\t\tRTE_LOG(ERR, PIPELINE, \"failed to read dest address/mask: %s\\n\",\n\t\t\tin[CB_FLD_DST_ADDR]);\n\t\treturn rc;\n\t}\n\n\tprintf(\"V=%u, mask=%u\\n\", v->field_value[DST_FIELD_IPV4].value.u32,\n\tv->field_value[DST_FIELD_IPV4].mask_range.u32);\n\t/* Parse n:n */\n\trc = parse_port_range(in[CB_FLD_SRC_PORT_RANGE],\n\t\t&v->field_value[SRCP_FIELD_IPV4].value.u16,\n\t\t&v->field_value[SRCP_FIELD_IPV4].mask_range.u16);\n\tif (rc != 0) {\n\t\tRTE_LOG(ERR, PIPELINE, \"failed to read source port range: %s\\n\",\n\t\t\tin[CB_FLD_SRC_PORT_RANGE]);\n\t\treturn rc;\n\t}\n\n\tprintf(\"V=%u, mask=%u\\n\", v->field_value[SRCP_FIELD_IPV4].value.u16,\n\t\tv->field_value[SRCP_FIELD_IPV4].mask_range.u16);\n\t/* Parse n:n */\n\trc = parse_port_range(in[CB_FLD_DST_PORT_RANGE],\n\t\t&v->field_value[DSTP_FIELD_IPV4].value.u16,\n\t\t&v->field_value[DSTP_FIELD_IPV4].mask_range.u16);\n\tif (rc != 0) {\n\t\tRTE_LOG(ERR, PIPELINE, \"failed to read dest port range: %s\\n\",\n\t\t\tin[CB_FLD_DST_PORT_RANGE]);\n\t\treturn rc;\n\t}\n\n\tprintf(\"V=%u, mask=%u\\n\", v->field_value[DSTP_FIELD_IPV4].value.u16,\n\t\tv->field_value[DSTP_FIELD_IPV4].mask_range.u16);\n\t/* parse 0/0xnn */\n\tGET_CB_FIELD(in[CB_FLD_PROTO],\n\t\tv->field_value[PROTO_FIELD_IPV4].value.u8,\n\t\t0, UINT8_MAX, '/');\n\tGET_CB_FIELD(in[CB_FLD_PROTO],\n\t\tv->field_value[PROTO_FIELD_IPV4].mask_range.u8,\n\t\t0, UINT8_MAX, 0);\n\n\tprintf(\"V=%u, mask=%u\\n\",\n\t\t(unsigned int)v->field_value[PROTO_FIELD_IPV4].value.u8,\n\t\tv->field_value[PROTO_FIELD_IPV4].mask_range.u8);\n\treturn 0;\n}\n\n\n/*\n * The format for these rules DO NOT need the port ranges to be\n * separated by ' : ', just ':'. It's a lot more readable and\n * cleaner, IMO.\n */\nchar lines[][128] = {\n\t\"@0.0.0.0/0 0.0.0.0/0 0:65535 0:65535 2/0xff\", /* Protocol check */\n\t\"@192.168.3.1/32 0.0.0.0/0 0:65535 0:65535 0/0\", /* Src IP checl */\n\t\"@0.0.0.0/0 10.4.4.1/32 0:65535 0:65535 0/0\", /* dst IP check */\n\t\"@0.0.0.0/0 0.0.0.0/0 105:105 0:65535 0/0\", /* src port check */\n\t\"@0.0.0.0/0 0.0.0.0/0 0:65535 206:206 0/0\", /* dst port check */\n};\n\nchar line[128];\n\n\nstatic int\nsetup_acl_pipeline(void)\n{\n\tint ret;\n\tint i;\n\tstruct rte_pipeline_params pipeline_params = {\n\t\t.name = \"PIPELINE\",\n\t\t.socket_id = 0,\n\t};\n\tuint32_t n;\n\tstruct rte_table_acl_rule_add_params rule_params;\n\tstruct rte_pipeline_table_acl_rule_delete_params *delete_params;\n\tparse_5tuple parser;\n\tchar acl_name[64];\n\n\t/* Pipeline configuration */\n\tp = rte_pipeline_create(&pipeline_params);\n\tif (p == NULL) {\n\t\tRTE_LOG(INFO, PIPELINE, \"%s: Failed to configure pipeline\\n\",\n\t\t\t__func__);\n\t\tgoto fail;\n\t}\n\n\t/* Input port configuration */\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tstruct rte_port_ring_reader_params port_ring_params = {\n\t\t\t.ring = rings_rx[i],\n\t\t};\n\n\t\tstruct rte_pipeline_port_in_params port_params = {\n\t\t\t.ops = &rte_port_ring_reader_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.burst_size = BURST_SIZE,\n\t\t};\n\n\t\t/* Put in action for some ports */\n\t\tif (i)\n\t\t\tport_params.f_action = port_in_action;\n\n\t\tret = rte_pipeline_port_in_create(p, &port_params,\n\t\t\t&port_in_id[i]);\n\t\tif (ret) {\n\t\t\trte_panic(\"Unable to configure input port %d, ret:%d\\n\",\n\t\t\t\ti, ret);\n\t\t\tgoto fail;\n\t\t}\n\t}\n\n\t/* output Port configuration */\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tstruct rte_port_ring_writer_params port_ring_params = {\n\t\t\t.ring = rings_tx[i],\n\t\t\t.tx_burst_sz = BURST_SIZE,\n\t\t};\n\n\t\tstruct rte_pipeline_port_out_params port_params = {\n\t\t\t.ops = &rte_port_ring_writer_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t};\n\n\n\t\tif (rte_pipeline_port_out_create(p, &port_params,\n\t\t\t&port_out_id[i])) {\n\t\t\trte_panic(\"Unable to configure output port %d\\n\", i);\n\t\t\tgoto fail;\n\t\t}\n\t}\n\n\t/* Table configuration */\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tstruct rte_pipeline_table_params table_params;\n\n\t\t/* Set up defaults for stub */\n\t\ttable_params.ops = &rte_table_stub_ops;\n\t\ttable_params.arg_create = NULL;\n\t\ttable_params.f_action_hit = action_handler_hit;\n\t\ttable_params.f_action_miss = NULL;\n\t\ttable_params.action_data_size = 0;\n\n\t\tRTE_LOG(INFO, PIPELINE, \"miss_action=%x\\n\",\n\t\t\ttable_entry_miss_action);\n\n\t\tprintf(\"RTE_ACL_RULE_SZ(%zu) = %zu\\n\", DIM(ipv4_defs),\n\t\t\tRTE_ACL_RULE_SZ(DIM(ipv4_defs)));\n\n\t\tstruct rte_table_acl_params acl_params;\n\n\t\tacl_params.n_rules = 1 << 5;\n\t\tacl_params.n_rule_fields = DIM(ipv4_defs);\n\t\tsnprintf(acl_name, sizeof(acl_name), \"ACL%d\", i);\n\t\tacl_params.name = acl_name;\n\t\tmemcpy(acl_params.field_format, ipv4_defs, sizeof(ipv4_defs));\n\n\t\ttable_params.ops = &rte_table_acl_ops;\n\t\ttable_params.arg_create = &acl_params;\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id[i])) {\n\t\t\trte_panic(\"Unable to configure table %u\\n\", i);\n\t\t\tgoto fail;\n\t\t}\n\n\t\tif (connect_miss_action_to_table) {\n\t\t\tif (rte_pipeline_table_create(p, &table_params,\n\t\t\t\t&table_id[i+2])) {\n\t\t\t\trte_panic(\"Unable to configure table %u\\n\", i);\n\t\t\t\tgoto fail;\n\t\t\t}\n\t\t}\n\t}\n\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tif (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],\n\t\t\ttable_id[i])) {\n\t\t\trte_panic(\"Unable to connect input port %u to \"\n\t\t\t\t\"table %u\\n\",\n\t\t\t\tport_in_id[i], table_id[i]);\n\t\t\tgoto fail;\n\t\t}\n\t}\n\n\t/* Add entries to tables */\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tstruct rte_pipeline_table_entry table_entry = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = port_out_id[i^1]},\n\t\t};\n\t\tint key_found;\n\t\tstruct rte_pipeline_table_entry *entry_ptr;\n\n\t\tmemset(&rule_params, 0, sizeof(rule_params));\n\t\tparser = parse_cb_ipv4_rule;\n\n\t\tfor (n = 1; n <= 5; n++) {\n\t\t\tsnprintf(line, sizeof(line), \"%s\", lines[n-1]);\n\t\t\tprintf(\"PARSING [%s]\\n\", line);\n\n\t\t\tret = parser(line, &rule_params);\n\t\t\tif (ret != 0) {\n\t\t\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\t\t\"line %u: parse_cb_ipv4vlan_rule\"\n\t\t\t\t\t\" failed, error code: %d (%s)\\n\",\n\t\t\t\t\tn, ret, strerror(-ret));\n\t\t\t\treturn ret;\n\t\t\t}\n\n\t\t\trule_params.priority = RTE_ACL_MAX_PRIORITY - n;\n\n\t\t\tret = rte_pipeline_table_entry_add(p, table_id[i],\n\t\t\t\t&rule_params,\n\t\t\t\t&table_entry, &key_found, &entry_ptr);\n\t\t\tif (ret < 0) {\n\t\t\t\trte_panic(\"Add entry to table %u failed (%d)\\n\",\n\t\t\t\t\ttable_id[i], ret);\n\t\t\t\tgoto fail;\n\t\t\t}\n\t\t}\n\n\t\t/* delete a few rules */\n\t\tfor (n = 2; n <= 3; n++) {\n\t\t\tsnprintf(line, sizeof(line), \"%s\", lines[n-1]);\n\t\t\tprintf(\"PARSING [%s]\\n\", line);\n\n\t\t\tret = parser(line, &rule_params);\n\t\t\tif (ret != 0) {\n\t\t\t\tRTE_LOG(ERR, PIPELINE, \"line %u: parse rule \"\n\t\t\t\t\t\" failed, error code: %d (%s)\\n\",\n\t\t\t\t\tn, ret, strerror(-ret));\n\t\t\t\treturn ret;\n\t\t\t}\n\n\t\t\tdelete_params = (struct\n\t\t\t\trte_pipeline_table_acl_rule_delete_params *)\n\t\t\t\t&(rule_params.field_value[0]);\n\t\t\tret = rte_pipeline_table_entry_delete(p, table_id[i],\n\t\t\t\tdelete_params, &key_found, NULL);\n\t\t\tif (ret < 0) {\n\t\t\t\trte_panic(\"Add entry to table %u failed (%d)\\n\",\n\t\t\t\t\ttable_id[i], ret);\n\t\t\t\tgoto fail;\n\t\t\t} else\n\t\t\t\tprintf(\"Deleted Rule.\\n\");\n\t\t}\n\n\n\t\t/* Try to add duplicates */\n\t\tfor (n = 1; n <= 5; n++) {\n\t\t\tsnprintf(line, sizeof(line), \"%s\", lines[n-1]);\n\t\t\tprintf(\"PARSING [%s]\\n\", line);\n\n\t\t\tret = parser(line, &rule_params);\n\t\t\tif (ret != 0) {\n\t\t\t\tRTE_LOG(ERR, PIPELINE, \"line %u: parse rule\"\n\t\t\t\t\t\" failed, error code: %d (%s)\\n\",\n\t\t\t\t\tn, ret, strerror(-ret));\n\t\t\t\treturn ret;\n\t\t\t}\n\n\t\t\trule_params.priority = RTE_ACL_MAX_PRIORITY - n;\n\n\t\t\tret = rte_pipeline_table_entry_add(p, table_id[i],\n\t\t\t\t&rule_params,\n\t\t\t\t&table_entry, &key_found, &entry_ptr);\n\t\t\tif (ret < 0) {\n\t\t\t\trte_panic(\"Add entry to table %u failed (%d)\\n\",\n\t\t\t\t\ttable_id[i], ret);\n\t\t\t\tgoto fail;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Enable input ports */\n\tfor (i = 0; i < N_PORTS ; i++)\n\t\tif (rte_pipeline_port_in_enable(p, port_in_id[i]))\n\t\t\trte_panic(\"Unable to enable input port %u\\n\",\n\t\t\t\tport_in_id[i]);\n\n\t/* Check pipeline consistency */\n\tif (rte_pipeline_check(p) < 0) {\n\t\trte_panic(\"Pipeline consistency check failed\\n\");\n\t\tgoto fail;\n\t}\n\n\treturn 0;\nfail:\n\n\treturn -1;\n}\n\nstatic int\ntest_pipeline_single_filter(int expected_count)\n{\n\tint i, j, ret, tx_count;\n\tstruct ipv4_5tuple five_tuple;\n\n\t/* Allocate a few mbufs and manually insert into the rings. */\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tfor (j = 0; j < 8; j++) {\n\t\t\tstruct rte_mbuf *mbuf;\n\n\t\t\tmbuf = rte_pktmbuf_alloc(pool);\n\t\t\tif (mbuf == NULL)\n\t\t\t\t/* this will cause test failure after cleanup\n\t\t\t\t * of already enqueued mbufs, as the mbuf\n\t\t\t\t * counts won't match */\n\t\t\t\tbreak;\n\t\t\tmemset(rte_pktmbuf_mtod(mbuf, char *), 0x00,\n\t\t\t\tsizeof(struct ipv4_5tuple));\n\n\t\t\tfive_tuple.proto = j;\n\t\t\tfive_tuple.ip_src = rte_bswap32(IPv4(192, 168, j, 1));\n\t\t\tfive_tuple.ip_dst = rte_bswap32(IPv4(10, 4, j, 1));\n\t\t\tfive_tuple.port_src = rte_bswap16(100 + j);\n\t\t\tfive_tuple.port_dst = rte_bswap16(200 + j);\n\n\t\t\tmemcpy(rte_pktmbuf_mtod(mbuf, char *), &five_tuple,\n\t\t\t\tsizeof(struct ipv4_5tuple));\n\t\t\tRTE_LOG(INFO, PIPELINE, \"%s: Enqueue onto ring %d\\n\",\n\t\t\t\t__func__, i);\n\t\t\trte_ring_enqueue(rings_rx[i], mbuf);\n\t\t}\n\t}\n\n\t/* Run pipeline once */\n\trte_pipeline_run(p);\n\n\trte_pipeline_flush(p);\n\n\ttx_count = 0;\n\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tvoid *objs[RING_TX_SIZE];\n\t\tstruct rte_mbuf *mbuf;\n\n\t\tret = rte_ring_sc_dequeue_burst(rings_tx[i], objs, 10);\n\t\tif (ret <= 0) {\n\t\t\tprintf(\"Got no objects from ring %d - error code %d\\n\",\n\t\t\t\ti, ret);\n\t\t} else {\n\t\t\tprintf(\"Got %d object(s) from ring %d!\\n\", ret, i);\n\t\t\tfor (j = 0; j < ret; j++) {\n\t\t\t\tmbuf = (struct rte_mbuf *)objs[j];\n\t\t\t\trte_hexdump(stdout, \"mbuf\",\n\t\t\t\t\trte_pktmbuf_mtod(mbuf, char *), 64);\n\t\t\t\trte_pktmbuf_free(mbuf);\n\t\t\t}\n\t\t\ttx_count += ret;\n\t\t}\n\t}\n\n\tif (tx_count != expected_count) {\n\t\tRTE_LOG(INFO, PIPELINE,\n\t\t\t\"%s: Unexpected packets for ACL test, \"\n\t\t\t\"expected %d, got %d\\n\",\n\t\t\t__func__, expected_count, tx_count);\n\t\tgoto fail;\n\t}\n\n\trte_pipeline_free(p);\n\n\treturn 0;\nfail:\n\treturn -1;\n\n}\n\nint\ntest_table_ACL(void)\n{\n\n\n\toverride_hit_mask = 0xFF; /* All packets are a hit */\n\n\tsetup_acl_pipeline();\n\tif (test_pipeline_single_filter(10) < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n" }, { "path": "app/test/test_table_acl.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/* Test prototypes */\nint test_table_ACL(void);\n" }, { "path": "app/test/test_table_combined.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \"test_table_combined.h\"\n#include \"test_table.h\"\n#include \n\n#define MAX_TEST_KEYS 128\n#define N_PACKETS 50\n\nenum check_table_result {\n\tCHECK_TABLE_OK,\n\tCHECK_TABLE_PORT_CONFIG,\n\tCHECK_TABLE_PORT_ENABLE,\n\tCHECK_TABLE_TABLE_CONFIG,\n\tCHECK_TABLE_ENTRY_ADD,\n\tCHECK_TABLE_DEFAULT_ENTRY_ADD,\n\tCHECK_TABLE_CONNECT,\n\tCHECK_TABLE_MANAGE_ERROR,\n\tCHECK_TABLE_CONSISTENCY,\n\tCHECK_TABLE_NO_TRAFFIC,\n\tCHECK_TABLE_INVALID_PARAMETER,\n};\n\nstruct table_packets {\n\tuint32_t hit_packet[MAX_TEST_KEYS];\n\tuint32_t miss_packet[MAX_TEST_KEYS];\n\tuint32_t n_hit_packets;\n\tuint32_t n_miss_packets;\n};\n\ncombined_table_test table_tests_combined[] = {\n\ttest_table_lpm_combined,\n\ttest_table_lpm_ipv6_combined,\n\ttest_table_hash8lru,\n\ttest_table_hash8ext,\n\ttest_table_hash16lru,\n\ttest_table_hash16ext,\n\ttest_table_hash32lru,\n\ttest_table_hash32ext,\n};\n\nunsigned n_table_tests_combined = RTE_DIM(table_tests_combined);\n\n/* Generic port tester function */\nstatic int\ntest_table_type(struct rte_table_ops *table_ops, void *table_args,\n\tvoid *key, struct table_packets *table_packets,\n\tstruct manage_ops *manage_ops, unsigned n_ops)\n{\n\tuint32_t ring_in_id, table_id, ring_out_id, ring_out_2_id;\n\tunsigned i;\n\n\tRTE_SET_USED(manage_ops);\n\tRTE_SET_USED(n_ops);\n\t/* Create pipeline */\n\tstruct rte_pipeline_params pipeline_params = {\n\t\t.name = \"pipeline\",\n\t\t.socket_id = 0,\n\t};\n\n\tstruct rte_pipeline *pipeline = rte_pipeline_create(&pipeline_params);\n\n\t/* Create input ring */\n\tstruct rte_port_ring_reader_params ring_params_rx = {\n\t\t.ring = RING_RX,\n\t};\n\n\tstruct rte_port_ring_writer_params ring_params_tx = {\n\t\t.ring = RING_RX,\n\t\t.tx_burst_sz = RTE_PORT_IN_BURST_SIZE_MAX,\n\t};\n\n\tstruct rte_pipeline_port_in_params ring_in_params = {\n\t\t.ops = &rte_port_ring_reader_ops,\n\t\t.arg_create = (void *)&ring_params_rx,\n\t\t.f_action = NULL,\n\t\t.burst_size = RTE_PORT_IN_BURST_SIZE_MAX,\n\t};\n\n\tif (rte_pipeline_port_in_create(pipeline, &ring_in_params,\n\t\t&ring_in_id) != 0)\n\t\treturn -CHECK_TABLE_PORT_CONFIG;\n\n\t/* Create table */\n\tstruct rte_pipeline_table_params table_params = {\n\t\t.ops = table_ops,\n\t\t.arg_create = table_args,\n\t\t.f_action_hit = NULL,\n\t\t.f_action_miss = NULL,\n\t\t.arg_ah = NULL,\n\t\t.action_data_size = 0,\n\t};\n\n\tif (rte_pipeline_table_create(pipeline, &table_params, &table_id) != 0)\n\t\treturn -CHECK_TABLE_TABLE_CONFIG;\n\n\t/* Create output ports */\n\tring_params_tx.ring = RING_TX;\n\n\tstruct rte_pipeline_port_out_params ring_out_params = {\n\t\t.ops = &rte_port_ring_writer_ops,\n\t\t.arg_create = (void *)&ring_params_tx,\n\t\t.f_action = NULL,\n\t};\n\n\tif (rte_pipeline_port_out_create(pipeline, &ring_out_params,\n\t\t&ring_out_id) != 0)\n\t\treturn -CHECK_TABLE_PORT_CONFIG;\n\n\tring_params_tx.ring = RING_TX_2;\n\n\tif (rte_pipeline_port_out_create(pipeline, &ring_out_params,\n\t\t&ring_out_2_id) != 0)\n\t\treturn -CHECK_TABLE_PORT_CONFIG;\n\n\t/* Add entry to the table */\n\tstruct rte_pipeline_table_entry default_entry = {\n\t\t.action = RTE_PIPELINE_ACTION_DROP,\n\t\t{.table_id = ring_out_id},\n\t};\n\n\tstruct rte_pipeline_table_entry table_entry = {\n\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t{.table_id = ring_out_id},\n\t};\n\n\tstruct rte_pipeline_table_entry *default_entry_ptr, *entry_ptr;\n\n\tint key_found;\n\n\tif (rte_pipeline_table_default_entry_add(pipeline, table_id,\n\t\t&default_entry, &default_entry_ptr) != 0)\n\t\treturn -CHECK_TABLE_DEFAULT_ENTRY_ADD;\n\n\tif (rte_pipeline_table_entry_add(pipeline, table_id,\n\t\tkey ? key : &table_entry, &table_entry, &key_found,\n\t\t\t&entry_ptr) != 0)\n\t\treturn -CHECK_TABLE_ENTRY_ADD;\n\n\t/* Create connections and check consistency */\n\tif (rte_pipeline_port_in_connect_to_table(pipeline, ring_in_id,\n\t\ttable_id) != 0)\n\t\treturn -CHECK_TABLE_CONNECT;\n\n\tif (rte_pipeline_port_in_enable(pipeline, ring_in_id) != 0)\n\t\treturn -CHECK_TABLE_PORT_ENABLE;\n\n\tif (rte_pipeline_check(pipeline) != 0)\n\t\treturn -CHECK_TABLE_CONSISTENCY;\n\n\n\n\t/* Flow test - All hits */\n\tif (table_packets->n_hit_packets) {\n\t\tfor (i = 0; i < table_packets->n_hit_packets; i++)\n\t\t\tRING_ENQUEUE(RING_RX, table_packets->hit_packet[i]);\n\n\t\tRUN_PIPELINE(pipeline);\n\n\t\tVERIFY_TRAFFIC(RING_TX, table_packets->n_hit_packets,\n\t\t\t\ttable_packets->n_hit_packets);\n\t}\n\n\t/* Flow test - All misses */\n\tif (table_packets->n_miss_packets) {\n\t\tfor (i = 0; i < table_packets->n_miss_packets; i++)\n\t\t\tRING_ENQUEUE(RING_RX, table_packets->miss_packet[i]);\n\n\t\tRUN_PIPELINE(pipeline);\n\n\t\tVERIFY_TRAFFIC(RING_TX, table_packets->n_miss_packets, 0);\n\t}\n\n\t/* Flow test - Half hits, half misses */\n\tif (table_packets->n_hit_packets && table_packets->n_miss_packets) {\n\t\tfor (i = 0; i < (table_packets->n_hit_packets) / 2; i++)\n\t\t\tRING_ENQUEUE(RING_RX, table_packets->hit_packet[i]);\n\n\t\tfor (i = 0; i < (table_packets->n_miss_packets) / 2; i++)\n\t\t\tRING_ENQUEUE(RING_RX, table_packets->miss_packet[i]);\n\n\t\tRUN_PIPELINE(pipeline);\n\t\tVERIFY_TRAFFIC(RING_TX, table_packets->n_hit_packets,\n\t\t\ttable_packets->n_hit_packets / 2);\n\t}\n\n\t/* Flow test - Single packet */\n\tif (table_packets->n_hit_packets) {\n\t\tRING_ENQUEUE(RING_RX, table_packets->hit_packet[0]);\n\t\tRUN_PIPELINE(pipeline);\n\t\tVERIFY_TRAFFIC(RING_TX, table_packets->n_hit_packets, 1);\n\t}\n\tif (table_packets->n_miss_packets) {\n\t\tRING_ENQUEUE(RING_RX, table_packets->miss_packet[0]);\n\t\tRUN_PIPELINE(pipeline);\n\t\tVERIFY_TRAFFIC(RING_TX, table_packets->n_miss_packets, 0);\n\t}\n\n\n\t/* Change table entry action */\n\tprintf(\"Change entry action\\n\");\n\ttable_entry.table_id = ring_out_2_id;\n\n\tif (rte_pipeline_table_default_entry_add(pipeline, table_id,\n\t\t&default_entry, &default_entry_ptr) != 0)\n\t\treturn -CHECK_TABLE_ENTRY_ADD;\n\n\tif (rte_pipeline_table_entry_add(pipeline, table_id,\n\t\tkey ? key : &table_entry, &table_entry, &key_found,\n\t\t\t&entry_ptr) != 0)\n\t\treturn -CHECK_TABLE_ENTRY_ADD;\n\n\t/* Check that traffic destination has changed */\n\tif (table_packets->n_hit_packets) {\n\t\tfor (i = 0; i < table_packets->n_hit_packets; i++)\n\t\t\tRING_ENQUEUE(RING_RX, table_packets->hit_packet[i]);\n\n\t\tRUN_PIPELINE(pipeline);\n\t\tVERIFY_TRAFFIC(RING_TX, table_packets->n_hit_packets, 0);\n\t\tVERIFY_TRAFFIC(RING_TX_2, table_packets->n_hit_packets,\n\t\t\ttable_packets->n_hit_packets);\n\t}\n\n\tprintf(\"delete entry\\n\");\n\t/* Delete table entry */\n\trte_pipeline_table_entry_delete(pipeline, table_id,\n\t\tkey ? key : &table_entry, &key_found, NULL);\n\n\trte_pipeline_free(pipeline);\n\n\treturn 0;\n}\n\n/* Table tests */\nint\ntest_table_stub_combined(void)\n{\n\tint status, i;\n\tstruct table_packets table_packets;\n\n\tprintf(\"--------------\\n\");\n\tprintf(\"RUNNING TEST - %s\\n\", __func__);\n\tprintf(\"--------------\\n\");\n\tfor (i = 0; i < N_PACKETS; i++)\n\t\ttable_packets.hit_packet[i] = i;\n\n\ttable_packets.n_hit_packets = N_PACKETS;\n\ttable_packets.n_miss_packets = 0;\n\n\tstatus = test_table_type(&rte_table_stub_ops, NULL, NULL,\n\t\t&table_packets, NULL, 1);\n\tVERIFY(status, CHECK_TABLE_OK);\n\n\treturn 0;\n}\n\nint\ntest_table_lpm_combined(void)\n{\n\tint status, i;\n\n\t/* Traffic flow */\n\tstruct rte_table_lpm_params lpm_params = {\n\t\t.n_rules = 1 << 16,\n\t\t.entry_unique_size = 8,\n\t\t.offset = 0,\n\t};\n\n\tstruct rte_table_lpm_key lpm_key = {\n\t\t.ip = 0xadadadad,\n\t\t.depth = 16,\n\t};\n\n\tstruct table_packets table_packets;\n\n\tprintf(\"--------------\\n\");\n\tprintf(\"RUNNING TEST - %s\\n\", __func__);\n\tprintf(\"--------------\\n\");\n\n\tfor (i = 0; i < N_PACKETS; i++)\n\t\ttable_packets.hit_packet[i] = 0xadadadad;\n\n\tfor (i = 0; i < N_PACKETS; i++)\n\t\ttable_packets.miss_packet[i] = 0xfefefefe;\n\n\ttable_packets.n_hit_packets = N_PACKETS;\n\ttable_packets.n_miss_packets = N_PACKETS;\n\n\tstatus = test_table_type(&rte_table_lpm_ops, (void *)&lpm_params,\n\t\t(void *)&lpm_key, &table_packets, NULL, 0);\n\tVERIFY(status, CHECK_TABLE_OK);\n\n\t/* Invalid parameters */\n\tlpm_params.n_rules = 0;\n\n\tstatus = test_table_type(&rte_table_lpm_ops, (void *)&lpm_params,\n\t\t(void *)&lpm_key, &table_packets, NULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\tlpm_params.n_rules = 1 << 24;\n\tlpm_key.depth = 0;\n\n\tstatus = test_table_type(&rte_table_lpm_ops, (void *)&lpm_params,\n\t\t(void *)&lpm_key, &table_packets, NULL, 0);\n\tVERIFY(status, CHECK_TABLE_ENTRY_ADD);\n\n\tlpm_key.depth = 33;\n\n\tstatus = test_table_type(&rte_table_lpm_ops, (void *)&lpm_params,\n\t\t(void *)&lpm_key, &table_packets, NULL, 0);\n\tVERIFY(status, CHECK_TABLE_ENTRY_ADD);\n\n\treturn 0;\n}\n\nint\ntest_table_lpm_ipv6_combined(void)\n{\n\tint status, i;\n\n\t/* Traffic flow */\n\tstruct rte_table_lpm_ipv6_params lpm_ipv6_params = {\n\t\t.n_rules = 1 << 16,\n\t\t.number_tbl8s = 1 << 13,\n\t\t.entry_unique_size = 8,\n\t\t.offset = 32,\n\t};\n\n\tstruct rte_table_lpm_ipv6_key lpm_ipv6_key = {\n\t\t.depth = 16,\n\t};\n\tmemset(lpm_ipv6_key.ip, 0xad, 16);\n\n\tstruct table_packets table_packets;\n\n\tprintf(\"--------------\\n\");\n\tprintf(\"RUNNING TEST - %s\\n\", __func__);\n\tprintf(\"--------------\\n\");\n\tfor (i = 0; i < N_PACKETS; i++)\n\t\ttable_packets.hit_packet[i] = 0xadadadad;\n\n\tfor (i = 0; i < N_PACKETS; i++)\n\t\ttable_packets.miss_packet[i] = 0xadadadab;\n\n\ttable_packets.n_hit_packets = N_PACKETS;\n\ttable_packets.n_miss_packets = N_PACKETS;\n\n\tstatus = test_table_type(&rte_table_lpm_ipv6_ops,\n\t\t(void *)&lpm_ipv6_params,\n\t\t(void *)&lpm_ipv6_key, &table_packets, NULL, 0);\n\tVERIFY(status, CHECK_TABLE_OK);\n\n\t/* Invalid parameters */\n\tlpm_ipv6_params.n_rules = 0;\n\n\tstatus = test_table_type(&rte_table_lpm_ipv6_ops,\n\t\t(void *)&lpm_ipv6_params,\n\t\t(void *)&lpm_ipv6_key, &table_packets, NULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\tlpm_ipv6_params.n_rules = 1 << 24;\n\tlpm_ipv6_key.depth = 0;\n\n\tstatus = test_table_type(&rte_table_lpm_ipv6_ops,\n\t\t(void *)&lpm_ipv6_params,\n\t\t(void *)&lpm_ipv6_key, &table_packets, NULL, 0);\n\tVERIFY(status, CHECK_TABLE_ENTRY_ADD);\n\n\tlpm_ipv6_key.depth = 129;\n\tstatus = test_table_type(&rte_table_lpm_ipv6_ops,\n\t\t(void *)&lpm_ipv6_params,\n\t\t(void *)&lpm_ipv6_key, &table_packets, NULL, 0);\n\tVERIFY(status, CHECK_TABLE_ENTRY_ADD);\n\n\treturn 0;\n}\n\nint\ntest_table_hash8lru(void)\n{\n\tint status, i;\n\n\t/* Traffic flow */\n\tstruct rte_table_hash_key8_lru_params key8lru_params = {\n\t\t.n_entries = 1<<24,\n\t\t.f_hash = pipeline_test_hash,\n\t\t.seed = 0,\n\t\t.signature_offset = 0,\n\t\t.key_offset = 32,\n\t};\n\n\tuint8_t key8lru[8];\n\tuint32_t *k8lru = (uint32_t *) key8lru;\n\n\tmemset(key8lru, 0, sizeof(key8lru));\n\tk8lru[0] = 0xadadadad;\n\n\tstruct table_packets table_packets;\n\n\tprintf(\"--------------\\n\");\n\tprintf(\"RUNNING TEST - %s\\n\", __func__);\n\tprintf(\"--------------\\n\");\n\tfor (i = 0; i < 50; i++)\n\t\ttable_packets.hit_packet[i] = 0xadadadad;\n\n\tfor (i = 0; i < 50; i++)\n\t\ttable_packets.miss_packet[i] = 0xfefefefe;\n\n\ttable_packets.n_hit_packets = 50;\n\ttable_packets.n_miss_packets = 50;\n\n\tstatus = test_table_type(&rte_table_hash_key8_lru_ops,\n\t\t(void *)&key8lru_params, (void *)key8lru, &table_packets,\n\t\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_OK);\n\n\t/* Invalid parameters */\n\tkey8lru_params.n_entries = 0;\n\n\tstatus = test_table_type(&rte_table_hash_key8_lru_ops,\n\t\t(void *)&key8lru_params, (void *)key8lru, &table_packets,\n\t\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\tkey8lru_params.n_entries = 1<<16;\n\tkey8lru_params.f_hash = NULL;\n\n\tstatus = test_table_type(&rte_table_hash_key8_lru_ops,\n\t\t(void *)&key8lru_params, (void *)key8lru, &table_packets,\n\t\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\treturn 0;\n}\n\nint\ntest_table_hash16lru(void)\n{\n\tint status, i;\n\n\t/* Traffic flow */\n\tstruct rte_table_hash_key16_lru_params key16lru_params = {\n\t\t.n_entries = 1<<16,\n\t\t.f_hash = pipeline_test_hash,\n\t\t.seed = 0,\n\t\t.signature_offset = 0,\n\t\t.key_offset = 32,\n\t};\n\n\tuint8_t key16lru[16];\n\tuint32_t *k16lru = (uint32_t *) key16lru;\n\n\tmemset(key16lru, 0, sizeof(key16lru));\n\tk16lru[0] = 0xadadadad;\n\n\tstruct table_packets table_packets;\n\n\tprintf(\"--------------\\n\");\n\tprintf(\"RUNNING TEST - %s\\n\", __func__);\n\tprintf(\"--------------\\n\");\n\tfor (i = 0; i < 50; i++)\n\t\ttable_packets.hit_packet[i] = 0xadadadad;\n\n\tfor (i = 0; i < 50; i++)\n\t\ttable_packets.miss_packet[i] = 0xfefefefe;\n\n\ttable_packets.n_hit_packets = 50;\n\ttable_packets.n_miss_packets = 50;\n\n\tstatus = test_table_type(&rte_table_hash_key16_lru_ops,\n\t\t(void *)&key16lru_params, (void *)key16lru, &table_packets,\n\t\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_OK);\n\n\t/* Invalid parameters */\n\tkey16lru_params.n_entries = 0;\n\n\tstatus = test_table_type(&rte_table_hash_key16_lru_ops,\n\t\t(void *)&key16lru_params, (void *)key16lru, &table_packets,\n\t\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\tkey16lru_params.n_entries = 1<<16;\n\tkey16lru_params.f_hash = NULL;\n\n\tstatus = test_table_type(&rte_table_hash_key16_lru_ops,\n\t\t(void *)&key16lru_params, (void *)key16lru, &table_packets,\n\t\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\treturn 0;\n}\n\nint\ntest_table_hash32lru(void)\n{\n\tint status, i;\n\n\t/* Traffic flow */\n\tstruct rte_table_hash_key32_lru_params key32lru_params = {\n\t\t.n_entries = 1<<16,\n\t\t.f_hash = pipeline_test_hash,\n\t\t.seed = 0,\n\t\t.signature_offset = 0,\n\t\t.key_offset = 32,\n\t};\n\n\tuint8_t key32lru[32];\n\tuint32_t *k32lru = (uint32_t *) key32lru;\n\n\tmemset(key32lru, 0, sizeof(key32lru));\n\tk32lru[0] = 0xadadadad;\n\n\tstruct table_packets table_packets;\n\n\tprintf(\"--------------\\n\");\n\tprintf(\"RUNNING TEST - %s\\n\", __func__);\n\tprintf(\"--------------\\n\");\n\tfor (i = 0; i < 50; i++)\n\t\ttable_packets.hit_packet[i] = 0xadadadad;\n\n\tfor (i = 0; i < 50; i++)\n\t\ttable_packets.miss_packet[i] = 0xbdadadad;\n\n\ttable_packets.n_hit_packets = 50;\n\ttable_packets.n_miss_packets = 50;\n\n\tstatus = test_table_type(&rte_table_hash_key32_lru_ops,\n\t\t(void *)&key32lru_params, (void *)key32lru, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_OK);\n\n\t/* Invalid parameters */\n\tkey32lru_params.n_entries = 0;\n\n\tstatus = test_table_type(&rte_table_hash_key32_lru_ops,\n\t\t(void *)&key32lru_params, (void *)key32lru, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\tkey32lru_params.n_entries = 1<<16;\n\tkey32lru_params.f_hash = NULL;\n\n\tstatus = test_table_type(&rte_table_hash_key32_lru_ops,\n\t\t(void *)&key32lru_params, (void *)key32lru, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\treturn 0;\n}\n\nint\ntest_table_hash8ext(void)\n{\n\tint status, i;\n\n\t/* Traffic flow */\n\tstruct rte_table_hash_key8_ext_params key8ext_params = {\n\t\t.n_entries = 1<<16,\n\t\t.n_entries_ext = 1<<15,\n\t\t.f_hash = pipeline_test_hash,\n\t\t.seed = 0,\n\t\t.signature_offset = 0,\n\t\t.key_offset = 32,\n\t};\n\n\tuint8_t key8ext[8];\n\tuint32_t *k8ext = (uint32_t *) key8ext;\n\n\tmemset(key8ext, 0, sizeof(key8ext));\n\tk8ext[0] = 0xadadadad;\n\n\tstruct table_packets table_packets;\n\n\tprintf(\"--------------\\n\");\n\tprintf(\"RUNNING TEST - %s\\n\", __func__);\n\tprintf(\"--------------\\n\");\n\tfor (i = 0; i < 50; i++)\n\t\ttable_packets.hit_packet[i] = 0xadadadad;\n\n\tfor (i = 0; i < 50; i++)\n\t\ttable_packets.miss_packet[i] = 0xbdadadad;\n\n\ttable_packets.n_hit_packets = 50;\n\ttable_packets.n_miss_packets = 50;\n\n\tstatus = test_table_type(&rte_table_hash_key8_ext_ops,\n\t\t(void *)&key8ext_params, (void *)key8ext, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_OK);\n\n\t/* Invalid parameters */\n\tkey8ext_params.n_entries = 0;\n\n\tstatus = test_table_type(&rte_table_hash_key8_ext_ops,\n\t\t(void *)&key8ext_params, (void *)key8ext, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\tkey8ext_params.n_entries = 1<<16;\n\tkey8ext_params.f_hash = NULL;\n\n\tstatus = test_table_type(&rte_table_hash_key8_ext_ops,\n\t\t(void *)&key8ext_params, (void *)key8ext, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\tkey8ext_params.f_hash = pipeline_test_hash;\n\tkey8ext_params.n_entries_ext = 0;\n\n\tstatus = test_table_type(&rte_table_hash_key8_ext_ops,\n\t(void *)&key8ext_params, (void *)key8ext, &table_packets, NULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\treturn 0;\n}\n\nint\ntest_table_hash16ext(void)\n{\n\tint status, i;\n\n\t/* Traffic flow */\n\tstruct rte_table_hash_key16_ext_params key16ext_params = {\n\t\t.n_entries = 1<<16,\n\t\t.n_entries_ext = 1<<15,\n\t\t.f_hash = pipeline_test_hash,\n\t\t.seed = 0,\n\t\t.signature_offset = 0,\n\t\t.key_offset = 32,\n\t};\n\n\tuint8_t key16ext[16];\n\tuint32_t *k16ext = (uint32_t *) key16ext;\n\n\tmemset(key16ext, 0, sizeof(key16ext));\n\tk16ext[0] = 0xadadadad;\n\n\tstruct table_packets table_packets;\n\n\tprintf(\"--------------\\n\");\n\tprintf(\"RUNNING TEST - %s\\n\", __func__);\n\tprintf(\"--------------\\n\");\n\tfor (i = 0; i < 50; i++)\n\t\ttable_packets.hit_packet[i] = 0xadadadad;\n\n\tfor (i = 0; i < 50; i++)\n\t\ttable_packets.miss_packet[i] = 0xbdadadad;\n\n\ttable_packets.n_hit_packets = 50;\n\ttable_packets.n_miss_packets = 50;\n\n\tstatus = test_table_type(&rte_table_hash_key16_ext_ops,\n\t\t(void *)&key16ext_params, (void *)key16ext, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_OK);\n\n\t/* Invalid parameters */\n\tkey16ext_params.n_entries = 0;\n\n\tstatus = test_table_type(&rte_table_hash_key16_ext_ops,\n\t\t(void *)&key16ext_params, (void *)key16ext, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\tkey16ext_params.n_entries = 1<<16;\n\tkey16ext_params.f_hash = NULL;\n\n\tstatus = test_table_type(&rte_table_hash_key16_ext_ops,\n\t\t(void *)&key16ext_params, (void *)key16ext, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\tkey16ext_params.f_hash = pipeline_test_hash;\n\tkey16ext_params.n_entries_ext = 0;\n\n\tstatus = test_table_type(&rte_table_hash_key16_ext_ops,\n\t(void *)&key16ext_params, (void *)key16ext, &table_packets, NULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\treturn 0;\n}\n\nint\ntest_table_hash32ext(void)\n{\n\tint status, i;\n\n\t/* Traffic flow */\n\tstruct rte_table_hash_key32_ext_params key32ext_params = {\n\t\t.n_entries = 1<<16,\n\t\t.n_entries_ext = 1<<15,\n\t\t.f_hash = pipeline_test_hash,\n\t\t.seed = 0,\n\t\t.signature_offset = 0,\n\t\t.key_offset = 32,\n\t};\n\n\tuint8_t key32ext[32];\n\tuint32_t *k32ext = (uint32_t *) key32ext;\n\n\tmemset(key32ext, 0, sizeof(key32ext));\n\tk32ext[0] = 0xadadadad;\n\n\tstruct table_packets table_packets;\n\n\tprintf(\"--------------\\n\");\n\tprintf(\"RUNNING TEST - %s\\n\", __func__);\n\tprintf(\"--------------\\n\");\n\tfor (i = 0; i < 50; i++)\n\t\ttable_packets.hit_packet[i] = 0xadadadad;\n\n\tfor (i = 0; i < 50; i++)\n\t\ttable_packets.miss_packet[i] = 0xbdadadad;\n\n\ttable_packets.n_hit_packets = 50;\n\ttable_packets.n_miss_packets = 50;\n\n\tstatus = test_table_type(&rte_table_hash_key32_ext_ops,\n\t\t(void *)&key32ext_params, (void *)key32ext, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_OK);\n\n\t/* Invalid parameters */\n\tkey32ext_params.n_entries = 0;\n\n\tstatus = test_table_type(&rte_table_hash_key32_ext_ops,\n\t\t(void *)&key32ext_params, (void *)key32ext, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\tkey32ext_params.n_entries = 1<<16;\n\tkey32ext_params.f_hash = NULL;\n\n\tstatus = test_table_type(&rte_table_hash_key32_ext_ops,\n\t\t(void *)&key32ext_params, (void *)key32ext, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\tkey32ext_params.f_hash = pipeline_test_hash;\n\tkey32ext_params.n_entries_ext = 0;\n\n\tstatus = test_table_type(&rte_table_hash_key32_ext_ops,\n\t\t(void *)&key32ext_params, (void *)key32ext, &table_packets,\n\t\tNULL, 0);\n\tVERIFY(status, CHECK_TABLE_TABLE_CONFIG);\n\n\treturn 0;\n}\n" }, { "path": "app/test/test_table_combined.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/* Test prototypes */\nint test_table_stub_combined(void);\nint test_table_lpm_combined(void);\nint test_table_lpm_ipv6_combined(void);\n#ifdef RTE_LIBRTE_ACL\nint test_table_acl(void);\n#endif\nint test_table_hash8unoptimized(void);\nint test_table_hash8lru(void);\nint test_table_hash8ext(void);\nint test_table_hash16unoptimized(void);\nint test_table_hash16lru(void);\nint test_table_hash16ext(void);\nint test_table_hash32unoptimized(void);\nint test_table_hash32lru(void);\nint test_table_hash32ext(void);\n\n/* Extern variables */\ntypedef int (*combined_table_test)(void);\n\nextern combined_table_test table_tests_combined[];\nextern unsigned n_table_tests_combined;\n" }, { "path": "app/test/test_table_pipeline.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \"test_table.h\"\n#include \"test_table_pipeline.h\"\n\n#if 0\n\nstatic rte_pipeline_port_out_action_handler port_action_0x00\n\t(struct rte_mbuf **pkts, uint32_t n, uint64_t *pkts_mask, void *arg);\nstatic rte_pipeline_port_out_action_handler port_action_0xFF\n\t(struct rte_mbuf **pkts, uint32_t n, uint64_t *pkts_mask, void *arg);\nstatic rte_pipeline_port_out_action_handler port_action_stub\n\t(struct rte_mbuf **pkts, uint32_t n, uint64_t *pkts_mask, void *arg);\n\n\nrte_pipeline_port_out_action_handler port_action_0x00(struct rte_mbuf **pkts,\n\tuint32_t n,\n\tuint64_t *pkts_mask,\n\tvoid *arg)\n{\n\tRTE_SET_USED(pkts);\n\tRTE_SET_USED(n);\n\tRTE_SET_USED(arg);\n\tprintf(\"Port Action 0x00\\n\");\n\t*pkts_mask = 0x00;\n\treturn 0;\n}\n\nrte_pipeline_port_out_action_handler port_action_0xFF(struct rte_mbuf **pkts,\n\tuint32_t n,\n\tuint64_t *pkts_mask,\n\tvoid *arg)\n{\n\tRTE_SET_USED(pkts);\n\tRTE_SET_USED(n);\n\tRTE_SET_USED(arg);\n\tprintf(\"Port Action 0xFF\\n\");\n\t*pkts_mask = 0xFF;\n\treturn 0;\n}\n\nrte_pipeline_port_out_action_handler port_action_stub(struct rte_mbuf **pkts,\n\tuint32_t n,\n\tuint64_t *pkts_mask,\n\tvoid *arg)\n{\n\tRTE_SET_USED(pkts);\n\tRTE_SET_USED(n);\n\tRTE_SET_USED(pkts_mask);\n\tRTE_SET_USED(arg);\n\tprintf(\"Port Action stub\\n\");\n\treturn 0;\n}\n\n#endif\n\nrte_pipeline_table_action_handler_hit\ntable_action_0x00(struct rte_mbuf **pkts, uint64_t *pkts_mask,\n\tstruct rte_pipeline_table_entry **actions, uint32_t action_mask);\n\nrte_pipeline_table_action_handler_hit\ntable_action_stub_hit(struct rte_mbuf **pkts, uint64_t *pkts_mask,\n\tstruct rte_pipeline_table_entry **actions, uint32_t action_mask);\n\nrte_pipeline_table_action_handler_miss\ntable_action_stub_miss(struct rte_mbuf **pkts, uint64_t *pkts_mask,\n\tstruct rte_pipeline_table_entry *action, uint32_t action_mask);\n\nrte_pipeline_table_action_handler_hit\ntable_action_0x00(__attribute__((unused)) struct rte_mbuf **pkts,\n\tuint64_t *pkts_mask,\n\t__attribute__((unused)) struct rte_pipeline_table_entry **actions,\n\t__attribute__((unused)) uint32_t action_mask)\n{\n\tprintf(\"Table Action, setting pkts_mask to 0x00\\n\");\n\t*pkts_mask = 0x00;\n\treturn 0;\n}\n\nrte_pipeline_table_action_handler_hit\ntable_action_stub_hit(__attribute__((unused)) struct rte_mbuf **pkts,\n\tuint64_t *pkts_mask,\n\t__attribute__((unused)) struct rte_pipeline_table_entry **actions,\n\t__attribute__((unused)) uint32_t action_mask)\n{\n\tprintf(\"STUB Table Action Hit - doing nothing\\n\");\n\tprintf(\"STUB Table Action Hit - setting mask to 0x%\"PRIx64\"\\n\",\n\t\toverride_hit_mask);\n\t*pkts_mask = override_hit_mask;\n\treturn 0;\n}\nrte_pipeline_table_action_handler_miss\ntable_action_stub_miss(__attribute__((unused)) struct rte_mbuf **pkts,\n\tuint64_t *pkts_mask,\n\t__attribute__((unused)) struct rte_pipeline_table_entry *action,\n\t__attribute__((unused)) uint32_t action_mask)\n{\n\tprintf(\"STUB Table Action Miss - setting mask to 0x%\"PRIx64\"\\n\",\n\t\toverride_miss_mask);\n\t*pkts_mask = override_miss_mask;\n\treturn 0;\n}\n\n\nenum e_test_type {\n\te_TEST_STUB = 0,\n\te_TEST_LPM,\n\te_TEST_LPM6,\n\te_TEST_HASH_LRU_8,\n\te_TEST_HASH_LRU_16,\n\te_TEST_HASH_LRU_32,\n\te_TEST_HASH_EXT_8,\n\te_TEST_HASH_EXT_16,\n\te_TEST_HASH_EXT_32\n};\n\nchar pipeline_test_names[][64] = {\n\t\"Stub\",\n\t\"LPM\",\n\t\"LPMv6\",\n\t\"8-bit LRU Hash\",\n\t\"16-bit LRU Hash\",\n\t\"32-bit LRU Hash\",\n\t\"16-bit Ext Hash\",\n\t\"8-bit Ext Hash\",\n\t\"32-bit Ext Hash\",\n\t\"\"\n};\n\n\nstatic int\ncleanup_pipeline(void)\n{\n\n\trte_pipeline_free(p);\n\n\treturn 0;\n}\n\n\nstatic int check_pipeline_invalid_params(void);\n\nstatic int\ncheck_pipeline_invalid_params(void)\n{\n\tstruct rte_pipeline_params pipeline_params_1 = {\n\t\t.name = NULL,\n\t\t.socket_id = 0,\n\t};\n\tstruct rte_pipeline_params pipeline_params_2 = {\n\t\t.name = \"PIPELINE\",\n\t\t.socket_id = -1,\n\t};\n\tstruct rte_pipeline_params pipeline_params_3 = {\n\t\t.name = \"PIPELINE\",\n\t\t.socket_id = 127,\n\t};\n\n\tp = rte_pipeline_create(NULL);\n\tif (p != NULL) {\n\t\tRTE_LOG(INFO, PIPELINE,\n\t\t\t\"%s: configured pipeline with null params\\n\",\n\t\t\t__func__);\n\t\tgoto fail;\n\t}\n\tp = rte_pipeline_create(&pipeline_params_1);\n\tif (p != NULL) {\n\t\tRTE_LOG(INFO, PIPELINE, \"%s: Configure pipeline with NULL \"\n\t\t\t\"name\\n\", __func__);\n\t\tgoto fail;\n\t}\n\n\tp = rte_pipeline_create(&pipeline_params_2);\n\tif (p != NULL) {\n\t\tRTE_LOG(INFO, PIPELINE, \"%s: Configure pipeline with invalid \"\n\t\t\t\"socket\\n\", __func__);\n\t\tgoto fail;\n\t}\n\n\tp = rte_pipeline_create(&pipeline_params_3);\n\tif (p != NULL) {\n\t\tRTE_LOG(INFO, PIPELINE, \"%s: Configure pipeline with invalid \"\n\t\t\t\"socket\\n\", __func__);\n\t\tgoto fail;\n\t}\n\n\t/* Check pipeline consistency */\n\tif (!rte_pipeline_check(p)) {\n\t\trte_panic(\"Pipeline consistency reported as OK\\n\");\n\t\tgoto fail;\n\t}\n\n\n\treturn 0;\nfail:\n\treturn -1;\n}\n\n\nstatic int\nsetup_pipeline(int test_type)\n{\n\tint ret;\n\tint i;\n\tstruct rte_pipeline_params pipeline_params = {\n\t\t.name = \"PIPELINE\",\n\t\t.socket_id = 0,\n\t};\n\n\tRTE_LOG(INFO, PIPELINE, \"%s: **** Setting up %s test\\n\",\n\t\t__func__, pipeline_test_names[test_type]);\n\n\t/* Pipeline configuration */\n\tp = rte_pipeline_create(&pipeline_params);\n\tif (p == NULL) {\n\t\tRTE_LOG(INFO, PIPELINE, \"%s: Failed to configure pipeline\\n\",\n\t\t\t__func__);\n\t\tgoto fail;\n\t}\n\n\tret = rte_pipeline_free(p);\n\tif (ret != 0) {\n\t\tRTE_LOG(INFO, PIPELINE, \"%s: Failed to free pipeline\\n\",\n\t\t\t__func__);\n\t\tgoto fail;\n\t}\n\n\t/* Pipeline configuration */\n\tp = rte_pipeline_create(&pipeline_params);\n\tif (p == NULL) {\n\t\tRTE_LOG(INFO, PIPELINE, \"%s: Failed to configure pipeline\\n\",\n\t\t\t__func__);\n\t\tgoto fail;\n\t}\n\n\n\t/* Input port configuration */\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tstruct rte_port_ring_reader_params port_ring_params = {\n\t\t\t.ring = rings_rx[i],\n\t\t};\n\n\t\tstruct rte_pipeline_port_in_params port_params = {\n\t\t\t.ops = &rte_port_ring_reader_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.burst_size = BURST_SIZE,\n\t\t};\n\n\t\t/* Put in action for some ports */\n\t\tif (i)\n\t\t\tport_params.f_action = NULL;\n\n\t\tret = rte_pipeline_port_in_create(p, &port_params,\n\t\t\t&port_in_id[i]);\n\t\tif (ret) {\n\t\t\trte_panic(\"Unable to configure input port %d, ret:%d\\n\",\n\t\t\t\ti, ret);\n\t\t\tgoto fail;\n\t\t}\n\t}\n\n\t/* output Port configuration */\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tstruct rte_port_ring_writer_params port_ring_params = {\n\t\t\t.ring = rings_tx[i],\n\t\t\t.tx_burst_sz = BURST_SIZE,\n\t\t};\n\n\t\tstruct rte_pipeline_port_out_params port_params = {\n\t\t\t.ops = &rte_port_ring_writer_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t};\n\n\t\tif (i)\n\t\t\tport_params.f_action = port_out_action;\n\n\t\tif (rte_pipeline_port_out_create(p, &port_params,\n\t\t\t&port_out_id[i])) {\n\t\t\trte_panic(\"Unable to configure output port %d\\n\", i);\n\t\t\tgoto fail;\n\t\t}\n\t}\n\n\t/* Table configuration */\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t\t.ops = &rte_table_stub_ops,\n\t\t\t\t.arg_create = NULL,\n\t\t\t\t.f_action_hit = action_handler_hit,\n\t\t\t\t.f_action_miss = action_handler_miss,\n\t\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id[i])) {\n\t\t\trte_panic(\"Unable to configure table %u\\n\", i);\n\t\t\tgoto fail;\n\t\t}\n\n\t\tif (connect_miss_action_to_table)\n\t\t\tif (rte_pipeline_table_create(p, &table_params,\n\t\t\t\t&table_id[i+2])) {\n\t\t\t\trte_panic(\"Unable to configure table %u\\n\", i);\n\t\t\t\tgoto fail;\n\t\t\t}\n\t}\n\n\tfor (i = 0; i < N_PORTS; i++)\n\t\tif (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],\n\t\t\ttable_id[i])) {\n\t\t\trte_panic(\"Unable to connect input port %u to \"\n\t\t\t\t\"table %u\\n\", port_in_id[i], table_id[i]);\n\t\t\tgoto fail;\n\t\t}\n\n\t/* Add entries to tables */\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tstruct rte_pipeline_table_entry default_entry = {\n\t\t\t.action = (enum rte_pipeline_action)\n\t\t\t\ttable_entry_default_action,\n\t\t\t{.port_id = port_out_id[i^1]},\n\t\t};\n\t\tstruct rte_pipeline_table_entry *default_entry_ptr;\n\n\t\tif (connect_miss_action_to_table) {\n\t\t\tprintf(\"Setting first table to output to next table\\n\");\n\t\t\tdefault_entry.action = RTE_PIPELINE_ACTION_TABLE;\n\t\t\tdefault_entry.table_id = table_id[i+2];\n\t\t}\n\n\t\t/* Add the default action for the table. */\n\t\tret = rte_pipeline_table_default_entry_add(p, table_id[i],\n\t\t\t&default_entry, &default_entry_ptr);\n\t\tif (ret < 0) {\n\t\t\trte_panic(\"Unable to add default entry to table %u \"\n\t\t\t\t\"code %d\\n\", table_id[i], ret);\n\t\t\tgoto fail;\n\t\t} else\n\t\t\tprintf(\"Added default entry to table id %d with \"\n\t\t\t\t\"action %x\\n\",\n\t\t\t\ttable_id[i], default_entry.action);\n\n\t\tif (connect_miss_action_to_table) {\n\t\t\t/* We create a second table so the first can pass\n\t\t\ttraffic into it */\n\t\t\tstruct rte_pipeline_table_entry default_entry = {\n\t\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t\t{.port_id = port_out_id[i^1]},\n\t\t\t};\n\t\t\tprintf(\"Setting secont table to output to port\\n\");\n\n\t\t\t/* Add the default action for the table. */\n\t\t\tret = rte_pipeline_table_default_entry_add(p,\n\t\t\t\ttable_id[i+2],\n\t\t\t\t&default_entry, &default_entry_ptr);\n\t\t\tif (ret < 0) {\n\t\t\t\trte_panic(\"Unable to add default entry to \"\n\t\t\t\t\t\"table %u code %d\\n\",\n\t\t\t\t\ttable_id[i], ret);\n\t\t\t\tgoto fail;\n\t\t\t} else\n\t\t\t\tprintf(\"Added default entry to table id %d \"\n\t\t\t\t\t\"with action %x\\n\",\n\t\t\t\t\ttable_id[i], default_entry.action);\n\t\t}\n\t}\n\n\t/* Enable input ports */\n\tfor (i = 0; i < N_PORTS ; i++)\n\t\tif (rte_pipeline_port_in_enable(p, port_in_id[i]))\n\t\t\trte_panic(\"Unable to enable input port %u\\n\",\n\t\t\t\tport_in_id[i]);\n\n\t/* Check pipeline consistency */\n\tif (rte_pipeline_check(p) < 0) {\n\t\trte_panic(\"Pipeline consistency check failed\\n\");\n\t\tgoto fail;\n\t} else\n\t\tprintf(\"Pipeline Consistency OK!\\n\");\n\n\treturn 0;\nfail:\n\n\treturn -1;\n}\n\nstatic int\ntest_pipeline_single_filter(int test_type, int expected_count)\n{\n\tint i;\n\tint j;\n\tint ret;\n\tint tx_count;\n\n\tRTE_LOG(INFO, PIPELINE, \"%s: **** Running %s test\\n\",\n\t\t__func__, pipeline_test_names[test_type]);\n\t/* Run pipeline once */\n\trte_pipeline_run(p);\n\n\n\tret = rte_pipeline_flush(NULL);\n\tif (ret != -EINVAL) {\n\t\tRTE_LOG(INFO, PIPELINE,\n\t\t\t\"%s: No pipeline flush error NULL pipeline (%d)\\n\",\n\t\t\t__func__, ret);\n\t\tgoto fail;\n\t}\n\n\t/*\n\t * Allocate a few mbufs and manually insert into the rings. */\n\tfor (i = 0; i < N_PORTS; i++)\n\t\tfor (j = 0; j < N_PORTS; j++) {\n\t\t\tstruct rte_mbuf *m;\n\t\t\tuint8_t *key;\n\t\t\tuint32_t *k32;\n\n\t\t\tm = rte_pktmbuf_alloc(pool);\n\t\t\tif (m == NULL) {\n\t\t\t\trte_panic(\"Failed to alloc mbuf from pool\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tkey = RTE_MBUF_METADATA_UINT8_PTR(m, 32);\n\n\t\t\tk32 = (uint32_t *) key;\n\t\t\tk32[0] = 0xadadadad >> (j % 2);\n\n\t\t\tRTE_LOG(INFO, PIPELINE, \"%s: Enqueue onto ring %d\\n\",\n\t\t\t\t__func__, i);\n\t\t\trte_ring_enqueue(rings_rx[i], m);\n\t\t}\n\n\t/* Run pipeline once */\n\trte_pipeline_run(p);\n\n /*\n\t* need to flush the pipeline, as there may be less hits than the burst\n\tsize and they will not have been flushed to the tx rings. */\n\trte_pipeline_flush(p);\n\n /*\n\t* Now we'll see what we got back on the tx rings. We should see whatever\n\t* packets we had hits on that were destined for the output ports.\n\t*/\n\ttx_count = 0;\n\n\tfor (i = 0; i < N_PORTS; i++) {\n\t\tvoid *objs[RING_TX_SIZE];\n\t\tstruct rte_mbuf *mbuf;\n\n\t\tret = rte_ring_sc_dequeue_burst(rings_tx[i], objs, 10);\n\t\tif (ret <= 0)\n\t\t\tprintf(\"Got no objects from ring %d - error code %d\\n\",\n\t\t\t\ti, ret);\n\t\telse {\n\t\t\tprintf(\"Got %d object(s) from ring %d!\\n\", ret, i);\n\t\t\tfor (j = 0; j < ret; j++) {\n\t\t\t\tmbuf = (struct rte_mbuf *)objs[j];\n\t\t\t\trte_hexdump(stdout, \"Object:\",\n\t\t\t\t\trte_pktmbuf_mtod(mbuf, char *),\n\t\t\t\t\tmbuf->data_len);\n\t\t\t\trte_pktmbuf_free(mbuf);\n\t\t\t}\n\t\t\ttx_count += ret;\n\t\t}\n\t}\n\n\tif (tx_count != expected_count) {\n\t\tRTE_LOG(INFO, PIPELINE,\n\t\t\t\"%s: Unexpected packets out for %s test, expected %d, \"\n\t\t\t\"got %d\\n\", __func__, pipeline_test_names[test_type],\n\t\t\texpected_count, tx_count);\n\t\tgoto fail;\n\t}\n\n\tcleanup_pipeline();\n\n\treturn 0;\nfail:\n\treturn -1;\n\n}\n\nint\ntest_table_pipeline(void)\n{\n\t/* TEST - All packets dropped */\n\taction_handler_hit = NULL;\n\taction_handler_miss = NULL;\n\ttable_entry_default_action = RTE_PIPELINE_ACTION_DROP;\n\tsetup_pipeline(e_TEST_STUB);\n\tif (test_pipeline_single_filter(e_TEST_STUB, 0) < 0)\n\t\treturn -1;\n\n\t/* TEST - All packets passed through */\n\ttable_entry_default_action = RTE_PIPELINE_ACTION_PORT;\n\tsetup_pipeline(e_TEST_STUB);\n\tif (test_pipeline_single_filter(e_TEST_STUB, 4) < 0)\n\t\treturn -1;\n\n\t/* TEST - one packet per port */\n\taction_handler_hit = NULL;\n\taction_handler_miss =\n\t\t(rte_pipeline_table_action_handler_miss) table_action_stub_miss;\n\ttable_entry_default_action = RTE_PIPELINE_ACTION_PORT;\n\toverride_miss_mask = 0x01; /* one packet per port */\n\tsetup_pipeline(e_TEST_STUB);\n\tif (test_pipeline_single_filter(e_TEST_STUB, 2) < 0)\n\t\treturn -1;\n\n\t/* TEST - one packet per port */\n\toverride_miss_mask = 0x02; /*all per port */\n\tsetup_pipeline(e_TEST_STUB);\n\tif (test_pipeline_single_filter(e_TEST_STUB, 2) < 0)\n\t\treturn -1;\n\n\t/* TEST - all packets per port */\n\toverride_miss_mask = 0x03; /*all per port */\n\tsetup_pipeline(e_TEST_STUB);\n\tif (test_pipeline_single_filter(e_TEST_STUB, 4) < 0)\n\t\treturn -1;\n\n /*\n\t* This test will set up two tables in the pipeline. the first table\n\t* will forward to another table on miss, and the second table will\n\t* forward to port.\n\t*/\n\tconnect_miss_action_to_table = 1;\n\ttable_entry_default_action = RTE_PIPELINE_ACTION_TABLE;\n\taction_handler_hit = NULL; /* not for stub, hitmask always zero */\n\taction_handler_miss = NULL;\n\tsetup_pipeline(e_TEST_STUB);\n\tif (test_pipeline_single_filter(e_TEST_STUB, 4) < 0)\n\t\treturn -1;\n\tconnect_miss_action_to_table = 0;\n\n\tprintf(\"TEST - two tables, hitmask override to 0x01\\n\");\n\tconnect_miss_action_to_table = 1;\n\taction_handler_miss =\n\t\t(rte_pipeline_table_action_handler_miss)table_action_stub_miss;\n\toverride_miss_mask = 0x01;\n\tsetup_pipeline(e_TEST_STUB);\n\tif (test_pipeline_single_filter(e_TEST_STUB, 2) < 0)\n\t\treturn -1;\n\tconnect_miss_action_to_table = 0;\n\n\tif (check_pipeline_invalid_params()) {\n\t\tRTE_LOG(INFO, PIPELINE, \"%s: Check pipeline invalid params \"\n\t\t\t\"failed.\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "app/test/test_table_pipeline.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/* Test prototypes */\nint test_table_pipeline(void);\n" }, { "path": "app/test/test_table_ports.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"test_table_ports.h\"\n#include \"test_table.h\"\n\nport_test port_tests[] = {\n\ttest_port_ring_reader,\n\ttest_port_ring_writer,\n};\n\nunsigned n_port_tests = RTE_DIM(port_tests);\n\n/* Port tests */\nint\ntest_port_ring_reader(void)\n{\n\tint status, i;\n\tstruct rte_port_ring_reader_params port_ring_reader_params;\n\tvoid *port;\n\n\t/* Invalid params */\n\tport = rte_port_ring_reader_ops.f_create(NULL, 0);\n\tif (port != NULL)\n\t\treturn -1;\n\n\tstatus = rte_port_ring_reader_ops.f_free(port);\n\tif (status >= 0)\n\t\treturn -2;\n\n\t/* Create and free */\n\tport_ring_reader_params.ring = RING_RX;\n\tport = rte_port_ring_reader_ops.f_create(&port_ring_reader_params, 0);\n\tif (port == NULL)\n\t\treturn -3;\n\n\tstatus = rte_port_ring_reader_ops.f_free(port);\n\tif (status != 0)\n\t\treturn -4;\n\n\t/* -- Traffic RX -- */\n\tint expected_pkts, received_pkts;\n\tstruct rte_mbuf *res_mbuf[RTE_PORT_IN_BURST_SIZE_MAX];\n\tvoid *mbuf[RTE_PORT_IN_BURST_SIZE_MAX];\n\n\tport_ring_reader_params.ring = RING_RX;\n\tport = rte_port_ring_reader_ops.f_create(&port_ring_reader_params, 0);\n\n\t/* Single packet */\n\tmbuf[0] = (void *)rte_pktmbuf_alloc(pool);\n\n\texpected_pkts = rte_ring_sp_enqueue_burst(port_ring_reader_params.ring,\n\t\tmbuf, 1);\n\treceived_pkts = rte_port_ring_reader_ops.f_rx(port, res_mbuf, 1);\n\n\tif (received_pkts < expected_pkts)\n\t\treturn -5;\n\n\trte_pktmbuf_free(res_mbuf[0]);\n\n\t/* Multiple packets */\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\tmbuf[i] = rte_pktmbuf_alloc(pool);\n\n\texpected_pkts = rte_ring_sp_enqueue_burst(port_ring_reader_params.ring,\n\t\t(void * const *) mbuf, RTE_PORT_IN_BURST_SIZE_MAX);\n\treceived_pkts = rte_port_ring_reader_ops.f_rx(port, res_mbuf,\n\t\tRTE_PORT_IN_BURST_SIZE_MAX);\n\n\tif (received_pkts < expected_pkts)\n\t\treturn -6;\n\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\trte_pktmbuf_free(res_mbuf[i]);\n\n\treturn 0;\n}\n\nint\ntest_port_ring_writer(void)\n{\n\tint status, i;\n\tstruct rte_port_ring_writer_params port_ring_writer_params;\n\tvoid *port;\n\n\t/* Invalid params */\n\tport = rte_port_ring_writer_ops.f_create(NULL, 0);\n\tif (port != NULL)\n\t\treturn -1;\n\n\tstatus = rte_port_ring_writer_ops.f_free(port);\n\tif (status >= 0)\n\t\treturn -2;\n\n\tport_ring_writer_params.ring = NULL;\n\n\tport = rte_port_ring_writer_ops.f_create(&port_ring_writer_params, 0);\n\tif (port != NULL)\n\t\treturn -3;\n\n\tport_ring_writer_params.ring = RING_TX;\n\tport_ring_writer_params.tx_burst_sz = RTE_PORT_IN_BURST_SIZE_MAX + 1;\n\n\tport = rte_port_ring_writer_ops.f_create(&port_ring_writer_params, 0);\n\tif (port != NULL)\n\t\treturn -4;\n\n\t/* Create and free */\n\tport_ring_writer_params.ring = RING_TX;\n\tport_ring_writer_params.tx_burst_sz = RTE_PORT_IN_BURST_SIZE_MAX;\n\n\tport = rte_port_ring_writer_ops.f_create(&port_ring_writer_params, 0);\n\tif (port == NULL)\n\t\treturn -5;\n\n\tstatus = rte_port_ring_writer_ops.f_free(port);\n\tif (status != 0)\n\t\treturn -6;\n\n\t/* -- Traffic TX -- */\n\tint expected_pkts, received_pkts;\n\tstruct rte_mbuf *mbuf[RTE_PORT_IN_BURST_SIZE_MAX];\n\tstruct rte_mbuf *res_mbuf[RTE_PORT_IN_BURST_SIZE_MAX];\n\n\tport_ring_writer_params.ring = RING_TX;\n\tport_ring_writer_params.tx_burst_sz = RTE_PORT_IN_BURST_SIZE_MAX;\n\tport = rte_port_ring_writer_ops.f_create(&port_ring_writer_params, 0);\n\n\t/* Single packet */\n\tmbuf[0] = rte_pktmbuf_alloc(pool);\n\n\trte_port_ring_writer_ops.f_tx(port, mbuf[0]);\n\trte_port_ring_writer_ops.f_flush(port);\n\texpected_pkts = 1;\n\treceived_pkts = rte_ring_sc_dequeue_burst(port_ring_writer_params.ring,\n\t\t(void **)res_mbuf, port_ring_writer_params.tx_burst_sz);\n\n\tif (received_pkts < expected_pkts)\n\t\treturn -7;\n\n\trte_pktmbuf_free(res_mbuf[0]);\n\n\t/* Multiple packets */\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++) {\n\t\tmbuf[i] = rte_pktmbuf_alloc(pool);\n\t\trte_port_ring_writer_ops.f_tx(port, mbuf[i]);\n\t}\n\n\texpected_pkts = RTE_PORT_IN_BURST_SIZE_MAX;\n\treceived_pkts = rte_ring_sc_dequeue_burst(port_ring_writer_params.ring,\n\t\t(void **)res_mbuf, port_ring_writer_params.tx_burst_sz);\n\n\tif (received_pkts < expected_pkts)\n\t\treturn -8;\n\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\trte_pktmbuf_free(res_mbuf[i]);\n\n\t/* TX Bulk */\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\tmbuf[i] = rte_pktmbuf_alloc(pool);\n\trte_port_ring_writer_ops.f_tx_bulk(port, mbuf, (uint64_t)-1);\n\n\texpected_pkts = RTE_PORT_IN_BURST_SIZE_MAX;\n\treceived_pkts = rte_ring_sc_dequeue_burst(port_ring_writer_params.ring,\n\t\t(void **)res_mbuf, port_ring_writer_params.tx_burst_sz);\n\n\tif (received_pkts < expected_pkts)\n\t\treturn -8;\n\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\trte_pktmbuf_free(res_mbuf[i]);\n\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\tmbuf[i] = rte_pktmbuf_alloc(pool);\n\trte_port_ring_writer_ops.f_tx_bulk(port, mbuf, (uint64_t)-3);\n\trte_port_ring_writer_ops.f_tx_bulk(port, mbuf, (uint64_t)2);\n\n\texpected_pkts = RTE_PORT_IN_BURST_SIZE_MAX;\n\treceived_pkts = rte_ring_sc_dequeue_burst(port_ring_writer_params.ring,\n\t\t(void **)res_mbuf, port_ring_writer_params.tx_burst_sz);\n\n\tif (received_pkts < expected_pkts)\n\t\treturn -9;\n\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\trte_pktmbuf_free(res_mbuf[i]);\n\n\treturn 0;\n}\n" }, { "path": "app/test/test_table_ports.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/* Test prototypes */\nint test_port_ring_reader(void);\nint test_port_ring_writer(void);\n\n/* Extern variables */\ntypedef int (*port_test)(void);\n\nextern port_test port_tests[];\nextern unsigned n_port_tests;\n" }, { "path": "app/test/test_table_tables.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \"test_table_tables.h\"\n#include \"test_table.h\"\n\ntable_test table_tests[] = {\n\ttest_table_stub,\n\ttest_table_array,\n\ttest_table_lpm,\n\ttest_table_lpm_ipv6,\n\ttest_table_hash_lru,\n\ttest_table_hash_ext,\n};\n\n#define PREPARE_PACKET(mbuf, value) do {\t\t\t\t\\\n\tuint32_t *k32, *signature;\t\t\t\t\t\\\n\tuint8_t *key;\t\t\t\t\t\t\t\\\n\tmbuf = rte_pktmbuf_alloc(pool);\t\t\t\t\t\\\n\tsignature = RTE_MBUF_METADATA_UINT32_PTR(mbuf, 0);\t\t\\\n\tkey = RTE_MBUF_METADATA_UINT8_PTR(mbuf, 32);\t\t\t\\\n\tmemset(key, 0, 32);\t\t\t\t\t\t\\\n\tk32 = (uint32_t *) key;\t\t\t\t\t\t\\\n\tk32[0] = (value);\t\t\t\t\t\t\\\n\t*signature = pipeline_test_hash(key, 0, 0);\t\t\t\\\n} while (0)\n\nunsigned n_table_tests = RTE_DIM(table_tests);\n\n/* Function prototypes */\nstatic int\ntest_table_hash_lru_generic(struct rte_table_ops *ops);\nstatic int\ntest_table_hash_ext_generic(struct rte_table_ops *ops);\n\nstruct rte_bucket_4_8 {\n\t/* Cache line 0 */\n\tuint64_t signature;\n\tuint64_t lru_list;\n\tstruct rte_bucket_4_8 *next;\n\tuint64_t next_valid;\n\tuint64_t key[4];\n\t/* Cache line 1 */\n\tuint8_t data[0];\n};\n\n#if RTE_TABLE_HASH_LRU_STRATEGY == 3\nuint64_t shuffles = 0xfffffffdfffbfff9ULL;\n#else\nuint64_t shuffles = 0x0003000200010000ULL;\n#endif\n\nstatic int test_lru_update(void)\n{\n\tstruct rte_bucket_4_8 b;\n\tstruct rte_bucket_4_8 *bucket;\n\tuint32_t i;\n\tuint64_t pos;\n\tuint64_t iterations;\n\tuint64_t j;\n\tint poss;\n\n\tprintf(\"---------------------------\\n\");\n\tprintf(\"Testing lru_update macro...\\n\");\n\tprintf(\"---------------------------\\n\");\n\tbucket = &b;\n\titerations = 10;\n#if RTE_TABLE_HASH_LRU_STRATEGY == 3\n\tbucket->lru_list = 0xFFFFFFFFFFFFFFFFULL;\n#else\n\tbucket->lru_list = 0x0000000100020003ULL;\n#endif\n\tposs = 0;\n\tfor (j = 0; j < iterations; j++)\n\t\tfor (i = 0; i < 9; i++) {\n\t\t\tuint32_t idx = i >> 1;\n\t\t\tlru_update(bucket, idx);\n\t\t\tpos = lru_pos(bucket);\n\t\t\tposs += pos;\n\t\t\tprintf(\"%s: %d lru_list=%016\"PRIx64\", upd=%d, \"\n\t\t\t\t\"pos=%\"PRIx64\"\\n\",\n\t\t\t\t__func__, i, bucket->lru_list, i>>1, pos);\n\t\t}\n\n\tif (bucket->lru_list != shuffles) {\n\t\tprintf(\"%s: ERROR: %d lru_list=%016\"PRIx64\", expected %016\"\n\t\t\tPRIx64\"\\n\",\n\t\t\t__func__, i, bucket->lru_list, shuffles);\n\t\treturn -1;\n\t}\n\tprintf(\"%s: output checksum of results =%d\\n\",\n\t\t__func__, poss);\n#if 0\n\tif (poss != 126) {\n\t\tprintf(\"%s: ERROR output checksum of results =%d expected %d\\n\",\n\t\t\t__func__, poss, 126);\n\t\treturn -1;\n\t}\n#endif\n\n\tfflush(stdout);\n\n\tuint64_t sc_start = rte_rdtsc();\n\titerations = 100000000;\n\tposs = 0;\n\tfor (j = 0; j < iterations; j++) {\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tlru_update(bucket, i);\n\t\t\tpos |= bucket->lru_list;\n\t\t}\n\t}\n\tuint64_t sc_end = rte_rdtsc();\n\n\tprintf(\"%s: output checksum of results =%llu\\n\",\n\t\t__func__, (long long unsigned int)pos);\n\tprintf(\"%s: start=%016\"PRIx64\", end=%016\"PRIx64\"\\n\",\n\t\t__func__, sc_start, sc_end);\n\tprintf(\"\\nlru_update: %lu cycles per loop iteration.\\n\\n\",\n\t\t(long unsigned int)((sc_end-sc_start)/(iterations*4)));\n\n\treturn 0;\n}\n\n/* Table tests */\nint\ntest_table_stub(void)\n{\n\tint i;\n\tuint64_t expected_mask = 0, result_mask;\n\tstruct rte_mbuf *mbufs[RTE_PORT_IN_BURST_SIZE_MAX];\n\tvoid *table;\n\tchar *entries[RTE_PORT_IN_BURST_SIZE_MAX];\n\n\t/* Create */\n\ttable = rte_table_stub_ops.f_create(NULL, 0, 1);\n\tif (table == NULL)\n\t\treturn -1;\n\n\t/* Traffic flow */\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\tif (i % 2 == 0)\n\t\t\tPREPARE_PACKET(mbufs[i], 0xadadadad);\n\t\telse\n\t\t\tPREPARE_PACKET(mbufs[i], 0xadadadab);\n\n\texpected_mask = 0;\n\trte_table_stub_ops.f_lookup(table, mbufs, -1,\n\t\t&result_mask, (void **)entries);\n\tif (result_mask != expected_mask)\n\t\treturn -2;\n\n\t/* Free resources */\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\trte_pktmbuf_free(mbufs[i]);\n\n\treturn 0;\n}\n\nint\ntest_table_array(void)\n{\n\tint status, i;\n\tuint64_t result_mask;\n\tstruct rte_mbuf *mbufs[RTE_PORT_IN_BURST_SIZE_MAX];\n\tvoid *table;\n\tchar *entries[RTE_PORT_IN_BURST_SIZE_MAX];\n\tchar entry1, entry2;\n\tvoid *entry_ptr;\n\tint key_found;\n\n\t/* Initialize params and create tables */\n\tstruct rte_table_array_params array_params = {\n\t\t.n_entries = 7,\n\t\t.offset = 1\n\t};\n\n\ttable = rte_table_array_ops.f_create(NULL, 0, 1);\n\tif (table != NULL)\n\t\treturn -1;\n\n\tarray_params.n_entries = 0;\n\n\ttable = rte_table_array_ops.f_create(&array_params, 0, 1);\n\tif (table != NULL)\n\t\treturn -2;\n\n\tarray_params.n_entries = 7;\n\n\ttable = rte_table_array_ops.f_create(&array_params, 0, 1);\n\tif (table != NULL)\n\t\treturn -3;\n\n\tarray_params.n_entries = 1 << 24;\n\tarray_params.offset = 1;\n\n\ttable = rte_table_array_ops.f_create(&array_params, 0, 1);\n\tif (table == NULL)\n\t\treturn -4;\n\n\tarray_params.offset = 32;\n\n\ttable = rte_table_array_ops.f_create(&array_params, 0, 1);\n\tif (table == NULL)\n\t\treturn -5;\n\n\t/* Free */\n\tstatus = rte_table_array_ops.f_free(table);\n\tif (status < 0)\n\t\treturn -6;\n\n\tstatus = rte_table_array_ops.f_free(NULL);\n\tif (status == 0)\n\t\treturn -7;\n\n\t/* Add */\n\tstruct rte_table_array_key array_key_1 = {\n\t\t.pos = 10,\n\t};\n\tstruct rte_table_array_key array_key_2 = {\n\t\t.pos = 20,\n\t};\n\tentry1 = 'A';\n\tentry2 = 'B';\n\n\ttable = rte_table_array_ops.f_create(&array_params, 0, 1);\n\tif (table == NULL)\n\t\treturn -8;\n\n\tstatus = rte_table_array_ops.f_add(NULL, (void *) &array_key_1, &entry1,\n\t\t&key_found, &entry_ptr);\n\tif (status == 0)\n\t\treturn -9;\n\n\tstatus = rte_table_array_ops.f_add(table, (void *) &array_key_1, NULL,\n\t\t&key_found, &entry_ptr);\n\tif (status == 0)\n\t\treturn -10;\n\n\tstatus = rte_table_array_ops.f_add(table, (void *) &array_key_1,\n\t\t&entry1, &key_found, &entry_ptr);\n\tif (status != 0)\n\t\treturn -11;\n\n\t/* Traffic flow */\n\tstatus = rte_table_array_ops.f_add(table, (void *) &array_key_2,\n\t\t&entry2, &key_found, &entry_ptr);\n\tif (status != 0)\n\t\treturn -12;\n\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\tif (i % 2 == 0)\n\t\t\tPREPARE_PACKET(mbufs[i], 10);\n\t\telse\n\t\t\tPREPARE_PACKET(mbufs[i], 20);\n\n\trte_table_array_ops.f_lookup(table, mbufs, -1,\n\t\t&result_mask, (void **)entries);\n\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\tif (i % 2 == 0 && *entries[i] != 'A')\n\t\t\treturn -13;\n\t\telse\n\t\t\tif (i % 2 == 1 && *entries[i] != 'B')\n\t\t\t\treturn -13;\n\n\t/* Free resources */\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\trte_pktmbuf_free(mbufs[i]);\n\n\tstatus = rte_table_array_ops.f_free(table);\n\n\treturn 0;\n}\n\nint\ntest_table_lpm(void)\n{\n\tint status, i;\n\tuint64_t expected_mask = 0, result_mask;\n\tstruct rte_mbuf *mbufs[RTE_PORT_IN_BURST_SIZE_MAX];\n\tvoid *table;\n\tchar *entries[RTE_PORT_IN_BURST_SIZE_MAX];\n\tchar entry;\n\tvoid *entry_ptr;\n\tint key_found;\n\tuint32_t entry_size = 1;\n\n\t/* Initialize params and create tables */\n\tstruct rte_table_lpm_params lpm_params = {\n\t\t.n_rules = 1 << 24,\n\t\t.entry_unique_size = entry_size,\n\t\t.offset = 1\n\t};\n\n\ttable = rte_table_lpm_ops.f_create(NULL, 0, entry_size);\n\tif (table != NULL)\n\t\treturn -1;\n\n\tlpm_params.n_rules = 0;\n\n\ttable = rte_table_lpm_ops.f_create(&lpm_params, 0, entry_size);\n\tif (table != NULL)\n\t\treturn -2;\n\n\tlpm_params.n_rules = 1 << 24;\n\tlpm_params.offset = 32;\n\tlpm_params.entry_unique_size = 0;\n\n\ttable = rte_table_lpm_ops.f_create(&lpm_params, 0, entry_size);\n\tif (table != NULL)\n\t\treturn -3;\n\n\tlpm_params.entry_unique_size = entry_size + 1;\n\n\ttable = rte_table_lpm_ops.f_create(&lpm_params, 0, entry_size);\n\tif (table != NULL)\n\t\treturn -4;\n\n\tlpm_params.entry_unique_size = entry_size;\n\n\ttable = rte_table_lpm_ops.f_create(&lpm_params, 0, entry_size);\n\tif (table == NULL)\n\t\treturn -5;\n\n\t/* Free */\n\tstatus = rte_table_lpm_ops.f_free(table);\n\tif (status < 0)\n\t\treturn -6;\n\n\tstatus = rte_table_lpm_ops.f_free(NULL);\n\tif (status == 0)\n\t\treturn -7;\n\n\t/* Add */\n\tstruct rte_table_lpm_key lpm_key;\n\tlpm_key.ip = 0xadadadad;\n\n\ttable = rte_table_lpm_ops.f_create(&lpm_params, 0, 1);\n\tif (table == NULL)\n\t\treturn -8;\n\n\tstatus = rte_table_lpm_ops.f_add(NULL, &lpm_key, &entry, &key_found,\n\t\t&entry_ptr);\n\tif (status == 0)\n\t\treturn -9;\n\n\tstatus = rte_table_lpm_ops.f_add(table, NULL, &entry, &key_found,\n\t\t&entry_ptr);\n\tif (status == 0)\n\t\treturn -10;\n\n\tstatus = rte_table_lpm_ops.f_add(table, &lpm_key, NULL, &key_found,\n\t\t&entry_ptr);\n\tif (status == 0)\n\t\treturn -11;\n\n\tlpm_key.depth = 0;\n\tstatus = rte_table_lpm_ops.f_add(table, &lpm_key, &entry, &key_found,\n\t\t&entry_ptr);\n\tif (status == 0)\n\t\treturn -12;\n\n\tlpm_key.depth = 33;\n\tstatus = rte_table_lpm_ops.f_add(table, &lpm_key, &entry, &key_found,\n\t\t&entry_ptr);\n\tif (status == 0)\n\t\treturn -13;\n\n\tlpm_key.depth = 16;\n\tstatus = rte_table_lpm_ops.f_add(table, &lpm_key, &entry, &key_found,\n\t\t&entry_ptr);\n\tif (status != 0)\n\t\treturn -14;\n\n\t/* Delete */\n\tstatus = rte_table_lpm_ops.f_delete(NULL, &lpm_key, &key_found, NULL);\n\tif (status == 0)\n\t\treturn -15;\n\n\tstatus = rte_table_lpm_ops.f_delete(table, NULL, &key_found, NULL);\n\tif (status == 0)\n\t\treturn -16;\n\n\tlpm_key.depth = 0;\n\tstatus = rte_table_lpm_ops.f_delete(table, &lpm_key, &key_found, NULL);\n\tif (status == 0)\n\t\treturn -17;\n\n\tlpm_key.depth = 33;\n\tstatus = rte_table_lpm_ops.f_delete(table, &lpm_key, &key_found, NULL);\n\tif (status == 0)\n\t\treturn -18;\n\n\tlpm_key.depth = 16;\n\tstatus = rte_table_lpm_ops.f_delete(table, &lpm_key, &key_found, NULL);\n\tif (status != 0)\n\t\treturn -19;\n\n\tstatus = rte_table_lpm_ops.f_delete(table, &lpm_key, &key_found, NULL);\n\tif (status != 0)\n\t\treturn -20;\n\n\t/* Traffic flow */\n\tentry = 'A';\n\tstatus = rte_table_lpm_ops.f_add(table, &lpm_key, &entry, &key_found,\n\t\t&entry_ptr);\n\tif (status < 0)\n\t\treturn -21;\n\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\tif (i % 2 == 0) {\n\t\t\texpected_mask |= (uint64_t)1 << i;\n\t\t\tPREPARE_PACKET(mbufs[i], 0xadadadad);\n\t\t} else\n\t\t\tPREPARE_PACKET(mbufs[i], 0xadadadab);\n\n\trte_table_lpm_ops.f_lookup(table, mbufs, -1,\n\t\t&result_mask, (void **)entries);\n\tif (result_mask != expected_mask)\n\t\treturn -22;\n\n\t/* Free resources */\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\trte_pktmbuf_free(mbufs[i]);\n\n\tstatus = rte_table_lpm_ops.f_free(table);\n\n\treturn 0;\n}\n\nint\ntest_table_lpm_ipv6(void)\n{\n\tint status, i;\n\tuint64_t expected_mask = 0, result_mask;\n\tstruct rte_mbuf *mbufs[RTE_PORT_IN_BURST_SIZE_MAX];\n\tvoid *table;\n\tchar *entries[RTE_PORT_IN_BURST_SIZE_MAX];\n\tchar entry;\n\tvoid *entry_ptr;\n\tint key_found;\n\tuint32_t entry_size = 1;\n\n\t/* Initialize params and create tables */\n\tstruct rte_table_lpm_ipv6_params lpm_params = {\n\t\t.n_rules = 1 << 24,\n\t\t.number_tbl8s = 1 << 21,\n\t\t.entry_unique_size = entry_size,\n\t\t.offset = 32\n\t};\n\n\ttable = rte_table_lpm_ipv6_ops.f_create(NULL, 0, entry_size);\n\tif (table != NULL)\n\t\treturn -1;\n\n\tlpm_params.n_rules = 0;\n\n\ttable = rte_table_lpm_ipv6_ops.f_create(&lpm_params, 0, entry_size);\n\tif (table != NULL)\n\t\treturn -2;\n\n\tlpm_params.n_rules = 1 << 24;\n\tlpm_params.number_tbl8s = 0;\n\ttable = rte_table_lpm_ipv6_ops.f_create(&lpm_params, 0, entry_size);\n\tif (table != NULL)\n\t\treturn -2;\n\n\tlpm_params.number_tbl8s = 1 << 21;\n\tlpm_params.entry_unique_size = 0;\n\ttable = rte_table_lpm_ipv6_ops.f_create(&lpm_params, 0, entry_size);\n\tif (table != NULL)\n\t\treturn -2;\n\n\tlpm_params.entry_unique_size = entry_size + 1;\n\ttable = rte_table_lpm_ipv6_ops.f_create(&lpm_params, 0, entry_size);\n\tif (table != NULL)\n\t\treturn -2;\n\n\tlpm_params.entry_unique_size = entry_size;\n\tlpm_params.offset = 32;\n\n\ttable = rte_table_lpm_ipv6_ops.f_create(&lpm_params, 0, entry_size);\n\tif (table == NULL)\n\t\treturn -3;\n\n\t/* Free */\n\tstatus = rte_table_lpm_ipv6_ops.f_free(table);\n\tif (status < 0)\n\t\treturn -4;\n\n\tstatus = rte_table_lpm_ipv6_ops.f_free(NULL);\n\tif (status == 0)\n\t\treturn -5;\n\n\t/* Add */\n\tstruct rte_table_lpm_ipv6_key lpm_key;\n\n\tlpm_key.ip[0] = 0xad;\n\tlpm_key.ip[1] = 0xad;\n\tlpm_key.ip[2] = 0xad;\n\tlpm_key.ip[3] = 0xad;\n\n\ttable = rte_table_lpm_ipv6_ops.f_create(&lpm_params, 0, entry_size);\n\tif (table == NULL)\n\t\treturn -6;\n\n\tstatus = rte_table_lpm_ipv6_ops.f_add(NULL, &lpm_key, &entry,\n\t\t&key_found, &entry_ptr);\n\tif (status == 0)\n\t\treturn -7;\n\n\tstatus = rte_table_lpm_ipv6_ops.f_add(table, NULL, &entry, &key_found,\n\t\t&entry_ptr);\n\tif (status == 0)\n\t\treturn -8;\n\n\tstatus = rte_table_lpm_ipv6_ops.f_add(table, &lpm_key, NULL, &key_found,\n\t\t&entry_ptr);\n\tif (status == 0)\n\t\treturn -9;\n\n\tlpm_key.depth = 0;\n\tstatus = rte_table_lpm_ipv6_ops.f_add(table, &lpm_key, &entry,\n\t\t&key_found, &entry_ptr);\n\tif (status == 0)\n\t\treturn -10;\n\n\tlpm_key.depth = 129;\n\tstatus = rte_table_lpm_ipv6_ops.f_add(table, &lpm_key, &entry,\n\t\t&key_found, &entry_ptr);\n\tif (status == 0)\n\t\treturn -11;\n\n\tlpm_key.depth = 16;\n\tstatus = rte_table_lpm_ipv6_ops.f_add(table, &lpm_key, &entry,\n\t\t&key_found, &entry_ptr);\n\tif (status != 0)\n\t\treturn -12;\n\n\t/* Delete */\n\tstatus = rte_table_lpm_ipv6_ops.f_delete(NULL, &lpm_key, &key_found,\n\t\tNULL);\n\tif (status == 0)\n\t\treturn -13;\n\n\tstatus = rte_table_lpm_ipv6_ops.f_delete(table, NULL, &key_found, NULL);\n\tif (status == 0)\n\t\treturn -14;\n\n\tlpm_key.depth = 0;\n\tstatus = rte_table_lpm_ipv6_ops.f_delete(table, &lpm_key, &key_found,\n\t\tNULL);\n\tif (status == 0)\n\t\treturn -15;\n\n\tlpm_key.depth = 129;\n\tstatus = rte_table_lpm_ipv6_ops.f_delete(table, &lpm_key, &key_found,\n\t\tNULL);\n\tif (status == 0)\n\t\treturn -16;\n\n\tlpm_key.depth = 16;\n\tstatus = rte_table_lpm_ipv6_ops.f_delete(table, &lpm_key, &key_found,\n\t\tNULL);\n\tif (status != 0)\n\t\treturn -17;\n\n\tstatus = rte_table_lpm_ipv6_ops.f_delete(table, &lpm_key, &key_found,\n\t\tNULL);\n\tif (status != 0)\n\t\treturn -18;\n\n\t/* Traffic flow */\n\tentry = 'A';\n\tstatus = rte_table_lpm_ipv6_ops.f_add(table, &lpm_key, &entry,\n\t\t&key_found, &entry_ptr);\n\tif (status < 0)\n\t\treturn -19;\n\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\tif (i % 2 == 0) {\n\t\t\texpected_mask |= (uint64_t)1 << i;\n\t\t\tPREPARE_PACKET(mbufs[i], 0xadadadad);\n\t\t} else\n\t\t\tPREPARE_PACKET(mbufs[i], 0xadadadab);\n\n\trte_table_lpm_ipv6_ops.f_lookup(table, mbufs, -1,\n\t\t&result_mask, (void **)entries);\n\tif (result_mask != expected_mask)\n\t\treturn -20;\n\n\t/* Free resources */\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\trte_pktmbuf_free(mbufs[i]);\n\n\tstatus = rte_table_lpm_ipv6_ops.f_free(table);\n\n\treturn 0;\n}\n\nstatic int\ntest_table_hash_lru_generic(struct rte_table_ops *ops)\n{\n\tint status, i;\n\tuint64_t expected_mask = 0, result_mask;\n\tstruct rte_mbuf *mbufs[RTE_PORT_IN_BURST_SIZE_MAX];\n\tvoid *table;\n\tchar *entries[RTE_PORT_IN_BURST_SIZE_MAX];\n\tchar entry;\n\tvoid *entry_ptr;\n\tint key_found;\n\n\t/* Initialize params and create tables */\n\tstruct rte_table_hash_key8_lru_params hash_params = {\n\t\t.n_entries = 1 << 10,\n\t\t.f_hash = pipeline_test_hash,\n\t\t.seed = 0,\n\t\t.signature_offset = 1,\n\t\t.key_offset = 32\n\t};\n\n\thash_params.n_entries = 0;\n\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table != NULL)\n\t\treturn -1;\n\n\thash_params.n_entries = 1 << 10;\n\thash_params.signature_offset = 1;\n\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table == NULL)\n\t\treturn -2;\n\n\thash_params.signature_offset = 0;\n\thash_params.key_offset = 1;\n\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table == NULL)\n\t\treturn -3;\n\n\thash_params.key_offset = 32;\n\thash_params.f_hash = NULL;\n\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table != NULL)\n\t\treturn -4;\n\n\thash_params.f_hash = pipeline_test_hash;\n\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table == NULL)\n\t\treturn -5;\n\n\t/* Free */\n\tstatus = ops->f_free(table);\n\tif (status < 0)\n\t\treturn -6;\n\n\tstatus = ops->f_free(NULL);\n\tif (status == 0)\n\t\treturn -7;\n\n\t/* Add */\n\tuint8_t key[32];\n\tuint32_t *k32 = (uint32_t *) &key;\n\n\tmemset(key, 0, 32);\n\tk32[0] = rte_be_to_cpu_32(0xadadadad);\n\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table == NULL)\n\t\treturn -8;\n\n\tentry = 'A';\n\tstatus = ops->f_add(table, &key, &entry, &key_found, &entry_ptr);\n\tif (status != 0)\n\t\treturn -9;\n\n\t/* Delete */\n\tstatus = ops->f_delete(table, &key, &key_found, NULL);\n\tif (status != 0)\n\t\treturn -10;\n\n\tstatus = ops->f_delete(table, &key, &key_found, NULL);\n\tif (status != 0)\n\t\treturn -11;\n\n\t/* Traffic flow */\n\tentry = 'A';\n\tstatus = ops->f_add(table, &key, &entry, &key_found, &entry_ptr);\n\tif (status < 0)\n\t\treturn -12;\n\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\tif (i % 2 == 0) {\n\t\t\texpected_mask |= (uint64_t)1 << i;\n\t\t\tPREPARE_PACKET(mbufs[i], 0xadadadad);\n\t\t} else\n\t\t\tPREPARE_PACKET(mbufs[i], 0xadadadab);\n\n\tops->f_lookup(table, mbufs, -1, &result_mask, (void **)entries);\n\tif (result_mask != expected_mask)\n\t\treturn -13;\n\n\t/* Free resources */\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\trte_pktmbuf_free(mbufs[i]);\n\n\tstatus = ops->f_free(table);\n\n\treturn 0;\n}\n\nstatic int\ntest_table_hash_ext_generic(struct rte_table_ops *ops)\n{\n\tint status, i;\n\tuint64_t expected_mask = 0, result_mask;\n\tstruct rte_mbuf *mbufs[RTE_PORT_IN_BURST_SIZE_MAX];\n\tvoid *table;\n\tchar *entries[RTE_PORT_IN_BURST_SIZE_MAX];\n\tchar entry;\n\tint key_found;\n\tvoid *entry_ptr;\n\n\t/* Initialize params and create tables */\n\tstruct rte_table_hash_key8_ext_params hash_params = {\n\t\t.n_entries = 1 << 10,\n\t\t.n_entries_ext = 1 << 4,\n\t\t.f_hash = pipeline_test_hash,\n\t\t.seed = 0,\n\t\t.signature_offset = 1,\n\t\t.key_offset = 32\n\t};\n\n\thash_params.n_entries = 0;\n\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table != NULL)\n\t\treturn -1;\n\n\thash_params.n_entries = 1 << 10;\n\thash_params.n_entries_ext = 0;\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table != NULL)\n\t\treturn -2;\n\n\thash_params.n_entries_ext = 1 << 4;\n\thash_params.signature_offset = 1;\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table == NULL)\n\t\treturn -2;\n\n\thash_params.signature_offset = 0;\n\thash_params.key_offset = 1;\n\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table == NULL)\n\t\treturn -3;\n\n\thash_params.key_offset = 32;\n\thash_params.f_hash = NULL;\n\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table != NULL)\n\t\treturn -4;\n\n\thash_params.f_hash = pipeline_test_hash;\n\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table == NULL)\n\t\treturn -5;\n\n\t/* Free */\n\tstatus = ops->f_free(table);\n\tif (status < 0)\n\t\treturn -6;\n\n\tstatus = ops->f_free(NULL);\n\tif (status == 0)\n\t\treturn -7;\n\n\t/* Add */\n\tuint8_t key[32];\n\tuint32_t *k32 = (uint32_t *) &key;\n\n\tmemset(key, 0, 32);\n\tk32[0] = rte_be_to_cpu_32(0xadadadad);\n\n\ttable = ops->f_create(&hash_params, 0, 1);\n\tif (table == NULL)\n\t\treturn -8;\n\n\tentry = 'A';\n\tstatus = ops->f_add(table, &key, &entry, &key_found, &entry_ptr);\n\tif (status != 0)\n\t\treturn -9;\n\n\t/* Delete */\n\tstatus = ops->f_delete(table, &key, &key_found, NULL);\n\tif (status != 0)\n\t\treturn -10;\n\n\tstatus = ops->f_delete(table, &key, &key_found, NULL);\n\tif (status != 0)\n\t\treturn -11;\n\n\t/* Traffic flow */\n\tentry = 'A';\n\tstatus = ops->f_add(table, &key, &entry, &key_found, &entry_ptr);\n\tif (status < 0)\n\t\treturn -12;\n\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\tif (i % 2 == 0) {\n\t\t\texpected_mask |= (uint64_t)1 << i;\n\t\t\tPREPARE_PACKET(mbufs[i], 0xadadadad);\n\t\t} else\n\t\t\tPREPARE_PACKET(mbufs[i], 0xadadadab);\n\n\tops->f_lookup(table, mbufs, -1, &result_mask, (void **)entries);\n\tif (result_mask != expected_mask)\n\t\treturn -13;\n\n\t/* Free resources */\n\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++)\n\t\trte_pktmbuf_free(mbufs[i]);\n\n\tstatus = ops->f_free(table);\n\n\treturn 0;\n}\n\nint\ntest_table_hash_lru(void)\n{\n\tint status;\n\n\tstatus = test_table_hash_lru_generic(&rte_table_hash_key8_lru_ops);\n\tif (status < 0)\n\t\treturn status;\n\n\tstatus = test_table_hash_lru_generic(\n\t\t&rte_table_hash_key8_lru_dosig_ops);\n\tif (status < 0)\n\t\treturn status;\n\n\tstatus = test_table_hash_lru_generic(&rte_table_hash_key16_lru_ops);\n\tif (status < 0)\n\t\treturn status;\n\n\tstatus = test_table_hash_lru_generic(&rte_table_hash_key32_lru_ops);\n\tif (status < 0)\n\t\treturn status;\n\n\tstatus = test_lru_update();\n\tif (status < 0)\n\t\treturn status;\n\n\treturn 0;\n}\n\nint\ntest_table_hash_ext(void)\n{\n\tint status;\n\n\tstatus = test_table_hash_ext_generic(&rte_table_hash_key8_ext_ops);\n\tif (status < 0)\n\t\treturn status;\n\n\tstatus = test_table_hash_ext_generic(\n\t\t&rte_table_hash_key8_ext_dosig_ops);\n\tif (status < 0)\n\t\treturn status;\n\n\tstatus = test_table_hash_ext_generic(&rte_table_hash_key16_ext_ops);\n\tif (status < 0)\n\t\treturn status;\n\n\tstatus = test_table_hash_ext_generic(&rte_table_hash_key32_ext_ops);\n\tif (status < 0)\n\t\treturn status;\n\n\treturn 0;\n}\n" }, { "path": "app/test/test_table_tables.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/* Test prototypes */\nint test_table_lpm(void);\nint test_table_lpm_ipv6(void);\nint test_table_array(void);\n#ifdef RTE_LIBRTE_ACL\nint test_table_acl(void);\n#endif\nint test_table_hash_unoptimized(void);\nint test_table_hash_lru(void);\nint test_table_hash_ext(void);\nint test_table_stub(void);\n\n/* Extern variables */\ntypedef int (*table_test)(void);\n\nextern table_test table_tests[];\nextern unsigned n_table_tests;\n" }, { "path": "app/test/test_tailq.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"test.h\"\n\n#define do_return(...) do { \\\n\tprintf(\"Error at %s, line %d: \", __func__, __LINE__); \\\n\tprintf(__VA_ARGS__); \\\n\treturn 1; \\\n} while (0)\n\nstatic struct rte_tailq_elem rte_dummy_tailq = {\n\t.name = \"dummy\",\n};\nEAL_REGISTER_TAILQ(rte_dummy_tailq)\n\nstatic struct rte_tailq_elem rte_dummy_dyn_tailq = {\n\t.name = \"dummy_dyn\",\n};\nstatic struct rte_tailq_elem rte_dummy_dyn2_tailq = {\n\t.name = \"dummy_dyn\",\n};\n\nstatic struct rte_tailq_entry d_elem;\nstatic struct rte_tailq_entry d_dyn_elem;\n\nstatic int\ntest_tailq_early(void)\n{\n\tstruct rte_tailq_entry_head *d_head;\n\n\td_head = RTE_TAILQ_CAST(rte_dummy_tailq.head, rte_tailq_entry_head);\n\tif (d_head == NULL)\n\t\tdo_return(\"Error %s has not been initialised\\n\",\n\t\t\t rte_dummy_tailq.name);\n\n\t/* check we can add an item to it */\n\tTAILQ_INSERT_TAIL(d_head, &d_elem, next);\n\n\treturn 0;\n}\n\nstatic int\ntest_tailq_create(void)\n{\n\tstruct rte_tailq_entry_head *d_head;\n\n\t/* create a tailq and check its non-null (since we are post-eal init) */\n\tif ((rte_eal_tailq_register(&rte_dummy_dyn_tailq) < 0) ||\n\t (rte_dummy_dyn_tailq.head == NULL))\n\t\tdo_return(\"Error allocating %s\\n\", rte_dummy_dyn_tailq.name);\n\n\td_head = RTE_TAILQ_CAST(rte_dummy_dyn_tailq.head, rte_tailq_entry_head);\n\n\t/* check we can add an item to it */\n\tTAILQ_INSERT_TAIL(d_head, &d_dyn_elem, next);\n\n\tif (strcmp(rte_dummy_dyn2_tailq.name, rte_dummy_dyn_tailq.name))\n\t\tdo_return(\"Error, something is wrong in the tailq test\\n\");\n\n\t/* try allocating again, and check for failure */\n\tif (!rte_eal_tailq_register(&rte_dummy_dyn2_tailq))\n\t\tdo_return(\"Error, registering the same tailq %s did not fail\\n\",\n\t\t\t rte_dummy_dyn2_tailq.name);\n\n\treturn 0;\n}\n\nstatic int\ntest_tailq_lookup(void)\n{\n\t/* run successful test - check result is found */\n\tstruct rte_tailq_entry_head *d_head;\n\tstruct rte_tailq_entry *d_ptr;\n\n\td_head = RTE_TAILQ_LOOKUP(rte_dummy_tailq.name, rte_tailq_entry_head);\n\t/* rte_dummy_tailq has been registered by EAL_REGISTER_TAILQ */\n\tif (d_head == NULL ||\n\t d_head != RTE_TAILQ_CAST(rte_dummy_tailq.head, rte_tailq_entry_head))\n\t\tdo_return(\"Error with tailq lookup\\n\");\n\n\tTAILQ_FOREACH(d_ptr, d_head, next)\n\t\tif (d_ptr != &d_elem)\n\t\t\tdo_return(\"Error with tailq returned from lookup - \"\n\t\t\t\t\t\"expected element not found\\n\");\n\n\td_head = RTE_TAILQ_LOOKUP(rte_dummy_dyn_tailq.name, rte_tailq_entry_head);\n\t/* rte_dummy_dyn_tailq has been registered by test_tailq_create */\n\tif (d_head == NULL ||\n\t d_head != RTE_TAILQ_CAST(rte_dummy_dyn_tailq.head, rte_tailq_entry_head))\n\t\tdo_return(\"Error with tailq lookup\\n\");\n\n\tTAILQ_FOREACH(d_ptr, d_head, next)\n\t\tif (d_ptr != &d_dyn_elem)\n\t\t\tdo_return(\"Error with tailq returned from lookup - \"\n\t\t\t\t\t\"expected element not found\\n\");\n\n\t/* now try a bad/error lookup */\n\td_head = RTE_TAILQ_LOOKUP(\"coucou\", rte_tailq_entry_head);\n\tif (d_head != NULL)\n\t\tdo_return(\"Error, lookup does not return NULL for bad tailq name\\n\");\n\n\treturn 0;\n}\n\nstatic int\ntest_tailq(void)\n{\n\tint ret = 0;\n\tret |= test_tailq_early();\n\tret |= test_tailq_create();\n\tret |= test_tailq_lookup();\n\treturn ret;\n}\n\nstatic struct test_command tailq_cmd = {\n\t.command = \"tailq_autotest\",\n\t.callback = test_tailq,\n};\nREGISTER_TEST_COMMAND(tailq_cmd);\n" }, { "path": "app/test/test_thash.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 Vladimir Medvedkin \n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \"test.h\"\n\n#include \n\nstruct test_thash_v4 {\n\tuint32_t\tdst_ip;\n\tuint32_t\tsrc_ip;\n\tuint16_t\tdst_port;\n\tuint16_t\tsrc_port;\n\tuint32_t\thash_l3;\n\tuint32_t\thash_l3l4;\n};\n\nstruct test_thash_v6 {\n\tuint8_t\t\tdst_ip[16];\n\tuint8_t\t\tsrc_ip[16];\n\tuint16_t\tdst_port;\n\tuint16_t\tsrc_port;\n\tuint32_t\thash_l3;\n\tuint32_t\thash_l3l4;\n};\n\n/*From 82599 Datasheet 7.1.2.8.3 RSS Verification Suite*/\nstruct test_thash_v4 v4_tbl[] = {\n{IPv4(161, 142, 100, 80), IPv4(66, 9, 149, 187),\n\t1766, 2794, 0x323e8fc2, 0x51ccc178},\n{IPv4(65, 69, 140, 83), IPv4(199, 92, 111, 2),\n\t4739, 14230, 0xd718262a, 0xc626b0ea},\n{IPv4(12, 22, 207, 184), IPv4(24, 19, 198, 95),\n\t38024, 12898, 0xd2d0a5de, 0x5c2b394a},\n{IPv4(209, 142, 163, 6), IPv4(38, 27, 205, 30),\n\t2217, 48228, 0x82989176, 0xafc7327f},\n{IPv4(202, 188, 127, 2), IPv4(153, 39, 163, 191),\n\t1303, 44251, 0x5d1809c5, 0x10e828a2},\n};\n\nstruct test_thash_v6 v6_tbl[] = {\n/*3ffe:2501:200:3::1*/\n{{0x3f, 0xfe, 0x25, 0x01, 0x02, 0x00, 0x00, 0x03,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,},\n/*3ffe:2501:200:1fff::7*/\n{0x3f, 0xfe, 0x25, 0x01, 0x02, 0x00, 0x1f, 0xff,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,},\n1766, 2794, 0x2cc18cd5, 0x40207d3d},\n/*ff02::1*/\n{{0xff, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,},\n/*3ffe:501:8::260:97ff:fe40:efab*/\n{0x3f, 0xfe, 0x05, 0x01, 0x00, 0x08, 0x00, 0x00,\n0x02, 0x60, 0x97, 0xff, 0xfe, 0x40, 0xef, 0xab,},\n4739, 14230, 0x0f0c461c, 0xdde51bbf},\n/*fe80::200:f8ff:fe21:67cf*/\n{{0xfe, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n0x02, 0x00, 0xf8, 0xff, 0xfe, 0x21, 0x67, 0xcf,},\n/*3ffe:1900:4545:3:200:f8ff:fe21:67cf*/\n{0x3f, 0xfe, 0x19, 0x00, 0x45, 0x45, 0x00, 0x03,\n0x02, 0x00, 0xf8, 0xff, 0xfe, 0x21, 0x67, 0xcf,},\n38024, 44251, 0x4b61e985, 0x02d1feef},\n};\n\nuint8_t default_rss_key[] = {\n0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,\n0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0,\n0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4,\n0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c,\n0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa,\n};\n\nstatic int\ntest_thash(void)\n{\n\tuint32_t i, j;\n\tunion rte_thash_tuple tuple;\n\tuint32_t rss_l3, rss_l3l4;\n\tuint8_t rss_key_be[RTE_DIM(default_rss_key)];\n\tstruct ipv6_hdr ipv6_hdr;\n\n\t/* Convert RSS key*/\n\trte_convert_rss_key((uint32_t *)&default_rss_key,\n\t\t(uint32_t *)rss_key_be, RTE_DIM(default_rss_key));\n\n\n\tfor (i = 0; i < RTE_DIM(v4_tbl); i++) {\n\t\ttuple.v4.src_addr = v4_tbl[i].src_ip;\n\t\ttuple.v4.dst_addr = v4_tbl[i].dst_ip;\n\t\ttuple.v4.sport = v4_tbl[i].src_port;\n\t\ttuple.v4.dport = v4_tbl[i].dst_port;\n\t\t/*Calculate hash with original key*/\n\t\trss_l3 = rte_softrss((uint32_t *)&tuple,\n\t\t\t\tRTE_THASH_V4_L3_LEN, default_rss_key);\n\t\trss_l3l4 = rte_softrss((uint32_t *)&tuple,\n\t\t\t\tRTE_THASH_V4_L4_LEN, default_rss_key);\n\t\tif ((rss_l3 != v4_tbl[i].hash_l3) ||\n\t\t\t\t(rss_l3l4 != v4_tbl[i].hash_l3l4))\n\t\t\treturn -1;\n\t\t/*Calculate hash with converted key*/\n\t\trss_l3 = rte_softrss_be((uint32_t *)&tuple,\n\t\t\t\tRTE_THASH_V4_L3_LEN, rss_key_be);\n\t\trss_l3l4 = rte_softrss_be((uint32_t *)&tuple,\n\t\t\t\tRTE_THASH_V4_L4_LEN, rss_key_be);\n\t\tif ((rss_l3 != v4_tbl[i].hash_l3) ||\n\t\t\t\t(rss_l3l4 != v4_tbl[i].hash_l3l4))\n\t\t\treturn -1;\n\t}\n\tfor (i = 0; i < RTE_DIM(v6_tbl); i++) {\n\t\t/*Fill ipv6 hdr*/\n\t\tfor (j = 0; j < RTE_DIM(ipv6_hdr.src_addr); j++)\n\t\t\tipv6_hdr.src_addr[j] = v6_tbl[i].src_ip[j];\n\t\tfor (j = 0; j < RTE_DIM(ipv6_hdr.dst_addr); j++)\n\t\t\tipv6_hdr.dst_addr[j] = v6_tbl[i].dst_ip[j];\n\t\t/*Load and convert ipv6 address into tuple*/\n\t\trte_thash_load_v6_addrs(&ipv6_hdr, &tuple);\n\t\ttuple.v6.sport = v6_tbl[i].src_port;\n\t\ttuple.v6.dport = v6_tbl[i].dst_port;\n\t\t/*Calculate hash with original key*/\n\t\trss_l3 = rte_softrss((uint32_t *)&tuple,\n\t\t\t\tRTE_THASH_V6_L3_LEN, default_rss_key);\n\t\trss_l3l4 = rte_softrss((uint32_t *)&tuple,\n\t\t\t\tRTE_THASH_V6_L4_LEN, default_rss_key);\n\t\tif ((rss_l3 != v6_tbl[i].hash_l3) ||\n\t\t\t\t(rss_l3l4 != v6_tbl[i].hash_l3l4))\n\t\t\treturn -1;\n\t\t/*Calculate hash with converted key*/\n\t\trss_l3 = rte_softrss_be((uint32_t *)&tuple,\n\t\t\t\tRTE_THASH_V6_L3_LEN, rss_key_be);\n\t\trss_l3l4 = rte_softrss_be((uint32_t *)&tuple,\n\t\t\t\tRTE_THASH_V6_L4_LEN, rss_key_be);\n\t\tif ((rss_l3 != v6_tbl[i].hash_l3) ||\n\t\t\t\t(rss_l3l4 != v6_tbl[i].hash_l3l4))\n\t\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic struct test_command thash_cmd = {\n\t.command = \"thash_autotest\",\n\t.callback = test_thash,\n};\nREGISTER_TEST_COMMAND(thash_cmd);\n" }, { "path": "app/test/test_timer.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"test.h\"\n\n/*\n * Timer\n * =====\n *\n * #. Stress test 1.\n *\n * The objective of the timer stress tests is to check that there are no\n * race conditions in list and status management. This test launches,\n * resets and stops the timer very often on many cores at the same\n * time.\n *\n * - Only one timer is used for this test.\n * - On each core, the rte_timer_manage() function is called from the main\n * loop every 3 microseconds.\n * - In the main loop, the timer may be reset (randomly, with a\n * probability of 0.5 %) 100 microseconds later on a random core, or\n * stopped (with a probability of 0.5 % also).\n * - In callback, the timer is can be reset (randomly, with a\n * probability of 0.5 %) 100 microseconds later on the same core or\n * on another core (same probability), or stopped (same\n * probability).\n *\n * # Stress test 2.\n *\n * The objective of this test is similar to the first in that it attempts\n * to find if there are any race conditions in the timer library. However,\n * it is less complex in terms of operations performed and duration, as it\n * is designed to have a predictable outcome that can be tested.\n *\n * - A set of timers is initialized for use by the test\n * - All cores then simultaneously are set to schedule all the timers at\n * the same time, so conflicts should occur.\n * - Then there is a delay while we wait for the timers to expire\n * - Then the master lcore calls timer_manage() and we check that all\n * timers have had their callbacks called exactly once - no more no less.\n * - Then we repeat the process, except after setting up the timers, we have\n * all cores randomly reschedule them.\n * - Again we check that the expected number of callbacks has occurred when\n * we call timer-manage.\n *\n * #. Basic test.\n *\n * This test performs basic functional checks of the timers. The test\n * uses four different timers that are loaded and stopped under\n * specific conditions in specific contexts.\n *\n * - Four timers are used for this test.\n * - On each core, the rte_timer_manage() function is called from main loop\n * every 3 microseconds.\n *\n * The autotest python script checks that the behavior is correct:\n *\n * - timer0\n *\n * - At initialization, timer0 is loaded by the master core, on master core\n * in \"single\" mode (time = 1 second).\n * - In the first 19 callbacks, timer0 is reloaded on the same core,\n * then, it is explicitly stopped at the 20th call.\n * - At t=25s, timer0 is reloaded once by timer2.\n *\n * - timer1\n *\n * - At initialization, timer1 is loaded by the master core, on the\n * master core in \"single\" mode (time = 2 seconds).\n * - In the first 9 callbacks, timer1 is reloaded on another\n * core. After the 10th callback, timer1 is not reloaded anymore.\n *\n * - timer2\n *\n * - At initialization, timer2 is loaded by the master core, on the\n * master core in \"periodical\" mode (time = 1 second).\n * - In the callback, when t=25s, it stops timer3 and reloads timer0\n * on the current core.\n *\n * - timer3\n *\n * - At initialization, timer3 is loaded by the master core, on\n * another core in \"periodical\" mode (time = 1 second).\n * - It is stopped at t=25s by timer2.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define TEST_DURATION_S 20 /* in seconds */\n#define NB_TIMER 4\n\n#define RTE_LOGTYPE_TESTTIMER RTE_LOGTYPE_USER3\n\nstatic volatile uint64_t end_time;\nstatic volatile int test_failed;\n\nstruct mytimerinfo {\n\tstruct rte_timer tim;\n\tunsigned id;\n\tunsigned count;\n};\n\nstatic struct mytimerinfo mytiminfo[NB_TIMER];\n\nstatic void timer_basic_cb(struct rte_timer *tim, void *arg);\n\nstatic void\nmytimer_reset(struct mytimerinfo *timinfo, uint64_t ticks,\n\t enum rte_timer_type type, unsigned tim_lcore,\n\t rte_timer_cb_t fct)\n{\n\trte_timer_reset_sync(&timinfo->tim, ticks, type, tim_lcore,\n\t\t\t fct, timinfo);\n}\n\n/* timer callback for stress tests */\nstatic void\ntimer_stress_cb(__attribute__((unused)) struct rte_timer *tim,\n\t\t__attribute__((unused)) void *arg)\n{\n\tlong r;\n\tunsigned lcore_id = rte_lcore_id();\n\tuint64_t hz = rte_get_timer_hz();\n\n\tif (rte_timer_pending(tim))\n\t\treturn;\n\n\tr = rte_rand();\n\tif ((r & 0xff) == 0) {\n\t\tmytimer_reset(&mytiminfo[0], hz, SINGLE, lcore_id,\n\t\t\t timer_stress_cb);\n\t}\n\telse if ((r & 0xff) == 1) {\n\t\tmytimer_reset(&mytiminfo[0], hz, SINGLE,\n\t\t\t rte_get_next_lcore(lcore_id, 0, 1),\n\t\t\t timer_stress_cb);\n\t}\n\telse if ((r & 0xff) == 2) {\n\t\trte_timer_stop(&mytiminfo[0].tim);\n\t}\n}\n\nstatic int\ntimer_stress_main_loop(__attribute__((unused)) void *arg)\n{\n\tuint64_t hz = rte_get_timer_hz();\n\tunsigned lcore_id = rte_lcore_id();\n\tuint64_t cur_time;\n\tint64_t diff = 0;\n\tlong r;\n\n\twhile (diff >= 0) {\n\n\t\t/* call the timer handler on each core */\n\t\trte_timer_manage();\n\n\t\t/* simulate the processing of a packet\n\t\t * (1 us = 2000 cycles at 2 Ghz) */\n\t\trte_delay_us(1);\n\n\t\t/* randomly stop or reset timer */\n\t\tr = rte_rand();\n\t\tlcore_id = rte_get_next_lcore(lcore_id, 0, 1);\n\t\tif ((r & 0xff) == 0) {\n\t\t\t/* 100 us */\n\t\t\tmytimer_reset(&mytiminfo[0], hz/10000, SINGLE, lcore_id,\n\t\t\t\t timer_stress_cb);\n\t\t}\n\t\telse if ((r & 0xff) == 1) {\n\t\t\trte_timer_stop_sync(&mytiminfo[0].tim);\n\t\t}\n\t\tcur_time = rte_get_timer_cycles();\n\t\tdiff = end_time - cur_time;\n\t}\n\n\tlcore_id = rte_lcore_id();\n\tRTE_LOG(INFO, TESTTIMER, \"core %u finished\\n\", lcore_id);\n\n\treturn 0;\n}\n\n/* Need to synchronize slave lcores through multiple steps. */\nenum { SLAVE_WAITING = 1, SLAVE_RUN_SIGNAL, SLAVE_RUNNING, SLAVE_FINISHED };\nstatic rte_atomic16_t slave_state[RTE_MAX_LCORE];\n\nstatic void\nmaster_init_slaves(void)\n{\n\tunsigned i;\n\n\tRTE_LCORE_FOREACH_SLAVE(i) {\n\t\trte_atomic16_set(&slave_state[i], SLAVE_WAITING);\n\t}\n}\n\nstatic void\nmaster_start_slaves(void)\n{\n\tunsigned i;\n\n\tRTE_LCORE_FOREACH_SLAVE(i) {\n\t\trte_atomic16_set(&slave_state[i], SLAVE_RUN_SIGNAL);\n\t}\n\tRTE_LCORE_FOREACH_SLAVE(i) {\n\t\twhile (rte_atomic16_read(&slave_state[i]) != SLAVE_RUNNING)\n\t\t\trte_pause();\n\t}\n}\n\nstatic void\nmaster_wait_for_slaves(void)\n{\n\tunsigned i;\n\n\tRTE_LCORE_FOREACH_SLAVE(i) {\n\t\twhile (rte_atomic16_read(&slave_state[i]) != SLAVE_FINISHED)\n\t\t\trte_pause();\n\t}\n}\n\nstatic void\nslave_wait_to_start(void)\n{\n\tunsigned lcore_id = rte_lcore_id();\n\n\twhile (rte_atomic16_read(&slave_state[lcore_id]) != SLAVE_RUN_SIGNAL)\n\t\trte_pause();\n\trte_atomic16_set(&slave_state[lcore_id], SLAVE_RUNNING);\n}\n\nstatic void\nslave_finish(void)\n{\n\tunsigned lcore_id = rte_lcore_id();\n\n\trte_atomic16_set(&slave_state[lcore_id], SLAVE_FINISHED);\n}\n\n\nstatic volatile int cb_count = 0;\n\n/* callback for second stress test. will only be called\n * on master lcore */\nstatic void\ntimer_stress2_cb(struct rte_timer *tim __rte_unused, void *arg __rte_unused)\n{\n\tcb_count++;\n}\n\n#define NB_STRESS2_TIMERS 8192\n\nstatic int\ntimer_stress2_main_loop(__attribute__((unused)) void *arg)\n{\n\tstatic struct rte_timer *timers;\n\tint i, ret;\n\tuint64_t delay = rte_get_timer_hz() / 4;\n\tunsigned lcore_id = rte_lcore_id();\n\tunsigned master = rte_get_master_lcore();\n\tint32_t my_collisions = 0;\n\tstatic rte_atomic32_t collisions;\n\n\tif (lcore_id == master) {\n\t\tcb_count = 0;\n\t\ttest_failed = 0;\n\t\trte_atomic32_set(&collisions, 0);\n\t\tmaster_init_slaves();\n\t\ttimers = rte_malloc(NULL, sizeof(*timers) * NB_STRESS2_TIMERS, 0);\n\t\tif (timers == NULL) {\n\t\t\tprintf(\"Test Failed\\n\");\n\t\t\tprintf(\"- Cannot allocate memory for timers\\n\" );\n\t\t\ttest_failed = 1;\n\t\t\tmaster_start_slaves();\n\t\t\tgoto cleanup;\n\t\t}\n\t\tfor (i = 0; i < NB_STRESS2_TIMERS; i++)\n\t\t\trte_timer_init(&timers[i]);\n\t\tmaster_start_slaves();\n\t} else {\n\t\tslave_wait_to_start();\n\t\tif (test_failed)\n\t\t\tgoto cleanup;\n\t}\n\n\t/* have all cores schedule all timers on master lcore */\n\tfor (i = 0; i < NB_STRESS2_TIMERS; i++) {\n\t\tret = rte_timer_reset(&timers[i], delay, SINGLE, master,\n\t\t\t\ttimer_stress2_cb, NULL);\n\t\t/* there will be collisions when multiple cores simultaneously\n\t\t * configure the same timers */\n\t\tif (ret != 0)\n\t\t\tmy_collisions++;\n\t}\n\tif (my_collisions != 0)\n\t\trte_atomic32_add(&collisions, my_collisions);\n\n\t/* wait long enough for timers to expire */\n\trte_delay_ms(500);\n\n\t/* all cores rendezvous */\n\tif (lcore_id == master) {\n\t\tmaster_wait_for_slaves();\n\t} else {\n\t\tslave_finish();\n\t}\n\n\t/* now check that we get the right number of callbacks */\n\tif (lcore_id == master) {\n\t\tmy_collisions = rte_atomic32_read(&collisions);\n\t\tif (my_collisions != 0)\n\t\t\tprintf(\"- %d timer reset collisions (OK)\\n\", my_collisions);\n\t\trte_timer_manage();\n\t\tif (cb_count != NB_STRESS2_TIMERS) {\n\t\t\tprintf(\"Test Failed\\n\");\n\t\t\tprintf(\"- Stress test 2, part 1 failed\\n\");\n\t\t\tprintf(\"- Expected %d callbacks, got %d\\n\", NB_STRESS2_TIMERS,\n\t\t\t\t\tcb_count);\n\t\t\ttest_failed = 1;\n\t\t\tmaster_start_slaves();\n\t\t\tgoto cleanup;\n\t\t}\n\t\tcb_count = 0;\n\n\t\t/* proceed */\n\t\tmaster_start_slaves();\n\t} else {\n\t\t/* proceed */\n\t\tslave_wait_to_start();\n\t\tif (test_failed)\n\t\t\tgoto cleanup;\n\t}\n\n\t/* now test again, just stop and restart timers at random after init*/\n\tfor (i = 0; i < NB_STRESS2_TIMERS; i++)\n\t\trte_timer_reset(&timers[i], delay, SINGLE, master,\n\t\t\t\ttimer_stress2_cb, NULL);\n\n\t/* pick random timer to reset, stopping them first half the time */\n\tfor (i = 0; i < 100000; i++) {\n\t\tint r = rand() % NB_STRESS2_TIMERS;\n\t\tif (i % 2)\n\t\t\trte_timer_stop(&timers[r]);\n\t\trte_timer_reset(&timers[r], delay, SINGLE, master,\n\t\t\t\ttimer_stress2_cb, NULL);\n\t}\n\n\t/* wait long enough for timers to expire */\n\trte_delay_ms(500);\n\n\t/* now check that we get the right number of callbacks */\n\tif (lcore_id == master) {\n\t\tmaster_wait_for_slaves();\n\n\t\trte_timer_manage();\n\t\tif (cb_count != NB_STRESS2_TIMERS) {\n\t\t\tprintf(\"Test Failed\\n\");\n\t\t\tprintf(\"- Stress test 2, part 2 failed\\n\");\n\t\t\tprintf(\"- Expected %d callbacks, got %d\\n\", NB_STRESS2_TIMERS,\n\t\t\t\t\tcb_count);\n\t\t\ttest_failed = 1;\n\t\t} else {\n\t\t\tprintf(\"Test OK\\n\");\n\t\t}\n\t}\n\ncleanup:\n\tif (lcore_id == master) {\n\t\tmaster_wait_for_slaves();\n\t\tif (timers != NULL) {\n\t\t\trte_free(timers);\n\t\t\ttimers = NULL;\n\t\t}\n\t} else {\n\t\tslave_finish();\n\t}\n\n\treturn 0;\n}\n\n/* timer callback for basic tests */\nstatic void\ntimer_basic_cb(struct rte_timer *tim, void *arg)\n{\n\tstruct mytimerinfo *timinfo = arg;\n\tuint64_t hz = rte_get_timer_hz();\n\tunsigned lcore_id = rte_lcore_id();\n\tuint64_t cur_time = rte_get_timer_cycles();\n\n\tif (rte_timer_pending(tim))\n\t\treturn;\n\n\ttiminfo->count ++;\n\n\tRTE_LOG(INFO, TESTTIMER,\n\t\t\"%\"PRIu64\": callback id=%u count=%u on core %u\\n\",\n\t\tcur_time, timinfo->id, timinfo->count, lcore_id);\n\n\t/* reload timer 0 on same core */\n\tif (timinfo->id == 0 && timinfo->count < 20) {\n\t\tmytimer_reset(timinfo, hz, SINGLE, lcore_id, timer_basic_cb);\n\t\treturn;\n\t}\n\n\t/* reload timer 1 on next core */\n\tif (timinfo->id == 1 && timinfo->count < 10) {\n\t\tmytimer_reset(timinfo, hz*2, SINGLE,\n\t\t\t rte_get_next_lcore(lcore_id, 0, 1),\n\t\t\t timer_basic_cb);\n\t\treturn;\n\t}\n\n\t/* Explicitelly stop timer 0. Once stop() called, we can even\n\t * erase the content of the structure: it is not referenced\n\t * anymore by any code (in case of dynamic structure, it can\n\t * be freed) */\n\tif (timinfo->id == 0 && timinfo->count == 20) {\n\n\t\t/* stop_sync() is not needed, because we know that the\n\t\t * status of timer is only modified by this core */\n\t\trte_timer_stop(tim);\n\t\tmemset(tim, 0xAA, sizeof(struct rte_timer));\n\t\treturn;\n\t}\n\n\t/* stop timer3, and restart a new timer0 (it was removed 5\n\t * seconds ago) for a single shot */\n\tif (timinfo->id == 2 && timinfo->count == 25) {\n\t\trte_timer_stop_sync(&mytiminfo[3].tim);\n\n\t\t/* need to reinit because structure was erased with 0xAA */\n\t\trte_timer_init(&mytiminfo[0].tim);\n\t\tmytimer_reset(&mytiminfo[0], hz, SINGLE, lcore_id,\n\t\t\t timer_basic_cb);\n\t}\n}\n\nstatic int\ntimer_basic_main_loop(__attribute__((unused)) void *arg)\n{\n\tuint64_t hz = rte_get_timer_hz();\n\tunsigned lcore_id = rte_lcore_id();\n\tuint64_t cur_time;\n\tint64_t diff = 0;\n\n\t/* launch all timers on core 0 */\n\tif (lcore_id == rte_get_master_lcore()) {\n\t\tmytimer_reset(&mytiminfo[0], hz, SINGLE, lcore_id,\n\t\t\t timer_basic_cb);\n\t\tmytimer_reset(&mytiminfo[1], hz*2, SINGLE, lcore_id,\n\t\t\t timer_basic_cb);\n\t\tmytimer_reset(&mytiminfo[2], hz, PERIODICAL, lcore_id,\n\t\t\t timer_basic_cb);\n\t\tmytimer_reset(&mytiminfo[3], hz, PERIODICAL,\n\t\t\t rte_get_next_lcore(lcore_id, 0, 1),\n\t\t\t timer_basic_cb);\n\t}\n\n\twhile (diff >= 0) {\n\n\t\t/* call the timer handler on each core */\n\t\trte_timer_manage();\n\n\t\t/* simulate the processing of a packet\n\t\t * (3 us = 6000 cycles at 2 Ghz) */\n\t\trte_delay_us(3);\n\n\t\tcur_time = rte_get_timer_cycles();\n\t\tdiff = end_time - cur_time;\n\t}\n\tRTE_LOG(INFO, TESTTIMER, \"core %u finished\\n\", lcore_id);\n\n\treturn 0;\n}\n\nstatic int\ntimer_sanity_check(void)\n{\n#ifdef RTE_LIBEAL_USE_HPET\n\tif (eal_timer_source != EAL_TIMER_HPET) {\n\t\tprintf(\"Not using HPET, can't sanity check timer sources\\n\");\n\t\treturn 0;\n\t}\n\n\tconst uint64_t t_hz = rte_get_tsc_hz();\n\tconst uint64_t h_hz = rte_get_hpet_hz();\n\tprintf(\"Hertz values: TSC = %\"PRIu64\", HPET = %\"PRIu64\"\\n\", t_hz, h_hz);\n\n\tconst uint64_t tsc_start = rte_get_tsc_cycles();\n\tconst uint64_t hpet_start = rte_get_hpet_cycles();\n\trte_delay_ms(100); /* delay 1/10 second */\n\tconst uint64_t tsc_end = rte_get_tsc_cycles();\n\tconst uint64_t hpet_end = rte_get_hpet_cycles();\n\tprintf(\"Measured cycles: TSC = %\"PRIu64\", HPET = %\"PRIu64\"\\n\",\n\t\t\ttsc_end-tsc_start, hpet_end-hpet_start);\n\n\tconst double tsc_time = (double)(tsc_end - tsc_start)/t_hz;\n\tconst double hpet_time = (double)(hpet_end - hpet_start)/h_hz;\n\t/* get the percentage that the times differ by */\n\tconst double time_diff = fabs(tsc_time - hpet_time)*100/tsc_time;\n\tprintf(\"Measured time: TSC = %.4f, HPET = %.4f\\n\", tsc_time, hpet_time);\n\n\tprintf(\"Elapsed time measured by TSC and HPET differ by %f%%\\n\",\n\t\t\ttime_diff);\n\tif (time_diff > 0.1) {\n\t\tprintf(\"Error times differ by >0.1%%\");\n\t\treturn -1;\n\t}\n#endif\n\treturn 0;\n}\n\nstatic int\ntest_timer(void)\n{\n\tunsigned i;\n\tuint64_t cur_time;\n\tuint64_t hz;\n\n\t/* sanity check our timer sources and timer config values */\n\tif (timer_sanity_check() < 0) {\n\t\tprintf(\"Timer sanity checks failed\\n\");\n\t\treturn TEST_FAILED;\n\t}\n\n\tif (rte_lcore_count() < 2) {\n\t\tprintf(\"not enough lcores for this test\\n\");\n\t\treturn TEST_FAILED;\n\t}\n\n\t/* init timer */\n\tfor (i=0; i\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define MAX_ITERATIONS 1000000\n\nint outstanding_count = 0;\n\nstatic void\ntimer_cb(struct rte_timer *t __rte_unused, void *param __rte_unused)\n{\n\toutstanding_count--;\n}\n\n#define DELAY_SECONDS 1\n\n#ifdef RTE_EXEC_ENV_LINUXAPP\n#define do_delay() usleep(10)\n#else\n#define do_delay() rte_pause()\n#endif\n\nstatic int\ntest_timer_perf(void)\n{\n\tunsigned iterations = 100;\n\tunsigned i;\n\tstruct rte_timer *tms;\n\tuint64_t start_tsc, end_tsc, delay_start;\n\tunsigned lcore_id = rte_lcore_id();\n\n\ttms = rte_malloc(NULL, sizeof(*tms) * MAX_ITERATIONS, 0);\n\n\tfor (i = 0; i < MAX_ITERATIONS; i++)\n\t\trte_timer_init(&tms[i]);\n\n\tconst uint64_t ticks = rte_get_timer_hz() * DELAY_SECONDS;\n\tconst uint64_t ticks_per_ms = rte_get_tsc_hz()/1000;\n\tconst uint64_t ticks_per_us = ticks_per_ms/1000;\n\n\twhile (iterations <= MAX_ITERATIONS) {\n\n\t\tprintf(\"Appending %u timers\\n\", iterations);\n\t\tstart_tsc = rte_rdtsc();\n\t\tfor (i = 0; i < iterations; i++)\n\t\t\trte_timer_reset(&tms[i], ticks, SINGLE, lcore_id,\n\t\t\t\t\ttimer_cb, NULL);\n\t\tend_tsc = rte_rdtsc();\n\t\tprintf(\"Time for %u timers: %\"PRIu64\" (%\"PRIu64\"ms), \", iterations,\n\t\t\t\tend_tsc-start_tsc, (end_tsc-start_tsc+ticks_per_ms/2)/(ticks_per_ms));\n\t\tprintf(\"Time per timer: %\"PRIu64\" (%\"PRIu64\"us)\\n\",\n\t\t\t\t(end_tsc-start_tsc)/iterations,\n\t\t\t\t((end_tsc-start_tsc)/iterations+ticks_per_us/2)/(ticks_per_us));\n\t\toutstanding_count = iterations;\n\t\tdelay_start = rte_get_timer_cycles();\n\t\twhile (rte_get_timer_cycles() < delay_start + ticks)\n\t\t\tdo_delay();\n\n\t\tstart_tsc = rte_rdtsc();\n\t\twhile (outstanding_count)\n\t\t\trte_timer_manage();\n\t\tend_tsc = rte_rdtsc();\n\t\tprintf(\"Time for %u callbacks: %\"PRIu64\" (%\"PRIu64\"ms), \", iterations,\n\t\t\t\tend_tsc-start_tsc, (end_tsc-start_tsc+ticks_per_ms/2)/(ticks_per_ms));\n\t\tprintf(\"Time per callback: %\"PRIu64\" (%\"PRIu64\"us)\\n\",\n\t\t\t\t(end_tsc-start_tsc)/iterations,\n\t\t\t\t((end_tsc-start_tsc)/iterations+ticks_per_us/2)/(ticks_per_us));\n\n\t\tprintf(\"Resetting %u timers\\n\", iterations);\n\t\tstart_tsc = rte_rdtsc();\n\t\tfor (i = 0; i < iterations; i++)\n\t\t\trte_timer_reset(&tms[i], rte_rand() % ticks, SINGLE, lcore_id,\n\t\t\t\t\ttimer_cb, NULL);\n\t\tend_tsc = rte_rdtsc();\n\t\tprintf(\"Time for %u timers: %\"PRIu64\" (%\"PRIu64\"ms), \", iterations,\n\t\t\t\tend_tsc-start_tsc, (end_tsc-start_tsc+ticks_per_ms/2)/(ticks_per_ms));\n\t\tprintf(\"Time per timer: %\"PRIu64\" (%\"PRIu64\"us)\\n\",\n\t\t\t\t(end_tsc-start_tsc)/iterations,\n\t\t\t\t((end_tsc-start_tsc)/iterations+ticks_per_us/2)/(ticks_per_us));\n\t\toutstanding_count = iterations;\n\n\t\tdelay_start = rte_get_timer_cycles();\n\t\twhile (rte_get_timer_cycles() < delay_start + ticks)\n\t\t\tdo_delay();\n\n\t\trte_timer_manage();\n\t\tif (outstanding_count != 0) {\n\t\t\tprintf(\"Error: outstanding callback count = %d\\n\", outstanding_count);\n\t\t\treturn -1;\n\t\t}\n\n\t\titerations *= 10;\n\t\tprintf(\"\\n\");\n\t}\n\n\tprintf(\"All timers processed ok\\n\");\n\n\t/* measure time to poll an empty timer list */\n\tstart_tsc = rte_rdtsc();\n\tfor (i = 0; i < iterations; i++)\n\t\trte_timer_manage();\n\tend_tsc = rte_rdtsc();\n\tprintf(\"\\nTime per rte_timer_manage with zero timers: %\"PRIu64\" cycles\\n\",\n\t\t\t(end_tsc - start_tsc + iterations/2) / iterations);\n\n\t/* measure time to poll a timer list with timers, but without\n\t * calling any callbacks */\n\trte_timer_reset(&tms[0], ticks * 100, SINGLE, lcore_id,\n\t\t\ttimer_cb, NULL);\n\tstart_tsc = rte_rdtsc();\n\tfor (i = 0; i < iterations; i++)\n\t\trte_timer_manage();\n\tend_tsc = rte_rdtsc();\n\tprintf(\"Time per rte_timer_manage with zero callbacks: %\"PRIu64\" cycles\\n\",\n\t\t\t(end_tsc - start_tsc + iterations/2) / iterations);\n\n\treturn 0;\n}\n\nstatic struct test_command timer_perf_cmd = {\n\t.command = \"timer_perf_autotest\",\n\t.callback = test_timer_perf,\n};\nREGISTER_TEST_COMMAND(timer_perf_cmd);\n" }, { "path": "app/test/test_timer_racecond.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 Akamai Technologies.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"test.h\"\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#undef TEST_TIMER_RACECOND_VERBOSE\n\n#ifdef RTE_EXEC_ENV_LINUXAPP\n#define usec_delay(us) usleep(us)\n#else\n#define usec_delay(us) rte_delay_us(us)\n#endif\n\n#define BILLION (1UL << 30)\n\n#define TEST_DURATION_S 20 /* in seconds */\n#define N_TIMERS 50\n\nstatic struct rte_timer timer[N_TIMERS];\nstatic unsigned timer_lcore_id[N_TIMERS];\n\nstatic unsigned master;\nstatic volatile unsigned stop_slaves;\n\nstatic int reload_timer(struct rte_timer *tim);\n\nstatic void\ntimer_cb(struct rte_timer *tim, void *arg __rte_unused)\n{\n\t/* Simulate slow callback function, 100 us. */\n\trte_delay_us(100);\n\n#ifdef TEST_TIMER_RACECOND_VERBOSE\n\tif (tim == &timer[0])\n\t\tprintf(\"------------------------------------------------\\n\");\n\tprintf(\"timer_cb: core %u timer %lu\\n\",\n\t\trte_lcore_id(), tim - timer);\n#endif\n\t(void)reload_timer(tim);\n}\n\nRTE_DEFINE_PER_LCORE(unsigned, n_reset_collisions);\n\nstatic int\nreload_timer(struct rte_timer *tim)\n{\n\t/* Make timer expire roughly when the TSC hits the next BILLION\n\t * multiple. Add in timer's index to make them expire in nearly\n\t * sorted order. This makes all timers somewhat synchronized,\n\t * firing ~2-3 times per second, assuming 2-3 GHz TSCs.\n\t */\n\tuint64_t ticks = BILLION - (rte_get_timer_cycles() % BILLION) +\n\t (tim - timer);\n\tint ret;\n\n\tret = rte_timer_reset(tim, ticks, PERIODICAL, master, timer_cb, NULL);\n\tif (ret != 0) {\n#ifdef TEST_TIMER_RACECOND_VERBOSE\n\t\tprintf(\"- core %u failed to reset timer %lu (OK)\\n\",\n\t\t\trte_lcore_id(), tim - timer);\n#endif\n\t\tRTE_PER_LCORE(n_reset_collisions) += 1;\n\t}\n\treturn ret;\n}\n\nstatic int\nslave_main_loop(__attribute__((unused)) void *arg)\n{\n\tunsigned lcore_id = rte_lcore_id();\n\tunsigned i;\n\n\tRTE_PER_LCORE(n_reset_collisions) = 0;\n\n\tprintf(\"Starting main loop on core %u\\n\", lcore_id);\n\n\twhile (!stop_slaves) {\n\t\t/* Wait until the timer manager is running.\n\t\t * We know it's running when we see timer[0] NOT pending.\n\t\t */\n\t\tif (rte_timer_pending(&timer[0])) {\n\t\t\trte_pause();\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Now, go cause some havoc!\n\t\t * Reload our timers.\n\t\t */\n\t\tfor (i = 0; i < N_TIMERS; i++) {\n\t\t\tif (timer_lcore_id[i] == lcore_id)\n\t\t\t\t(void)reload_timer(&timer[i]);\n\t\t}\n\t\tusec_delay(100*1000); /* sleep 100 ms */\n\t}\n\n\tif (RTE_PER_LCORE(n_reset_collisions) != 0) {\n\t\tprintf(\"- core %u, %u reset collisions (OK)\\n\",\n\t\t\tlcore_id, RTE_PER_LCORE(n_reset_collisions));\n\t}\n\treturn 0;\n}\n\nstatic int\ntest_timer_racecond(void)\n{\n\tint ret;\n\tuint64_t hz;\n\tuint64_t cur_time;\n\tuint64_t end_time;\n\tint64_t diff = 0;\n\tunsigned lcore_id;\n\tunsigned i;\n\n\tmaster = lcore_id = rte_lcore_id();\n\thz = rte_get_timer_hz();\n\n\t/* init and start timers */\n\tfor (i = 0; i < N_TIMERS; i++) {\n\t\trte_timer_init(&timer[i]);\n\t\tret = reload_timer(&timer[i]);\n\t\tTEST_ASSERT(ret == 0, \"reload_timer failed\");\n\n\t\t/* Distribute timers to slaves.\n\t\t * Note that we assign timer[0] to the master.\n\t\t */\n\t\ttimer_lcore_id[i] = lcore_id;\n\t\tlcore_id = rte_get_next_lcore(lcore_id, 1, 1);\n\t}\n\n\t/* calculate the \"end of test\" time */\n\tcur_time = rte_get_timer_cycles();\n\tend_time = cur_time + (hz * TEST_DURATION_S);\n\n\t/* start slave cores */\n\tstop_slaves = 0;\n\tprintf(\"Start timer manage race condition test (%u seconds)\\n\",\n\t\t\tTEST_DURATION_S);\n\trte_eal_mp_remote_launch(slave_main_loop, NULL, SKIP_MASTER);\n\n\twhile (diff >= 0) {\n\t\t/* run the timers */\n\t\trte_timer_manage();\n\n\t\t/* wait 100 ms */\n\t\tusec_delay(100*1000);\n\n\t\tcur_time = rte_get_timer_cycles();\n\t\tdiff = end_time - cur_time;\n\t}\n\n\t/* stop slave cores */\n\tprintf(\"Stopping timer manage race condition test\\n\");\n\tstop_slaves = 1;\n\trte_eal_mp_wait_lcore();\n\n\t/* stop timers */\n\tfor (i = 0; i < N_TIMERS; i++) {\n\t\tret = rte_timer_stop(&timer[i]);\n\t\tTEST_ASSERT(ret == 0, \"rte_timer_stop failed\");\n\t}\n\n\treturn TEST_SUCCESS;\n}\n\nstatic struct test_command timer_racecond_cmd = {\n\t.command = \"timer_racecond_autotest\",\n\t.callback = test_timer_racecond,\n};\nREGISTER_TEST_COMMAND(timer_racecond_cmd);\n" }, { "path": "app/test/test_version.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n\n#include \"test.h\"\n\n\nstatic int\ntest_version(void)\n{\n\tconst char *version = rte_version();\n\tif (version == NULL)\n\t\treturn -1;\n\tprintf(\"Version string: '%s'\\n\", version);\n\tif (*version == '\\0' ||\n\t\t\tstrncmp(version, RTE_VER_PREFIX, sizeof(RTE_VER_PREFIX)-1) != 0)\n\t\treturn -1;\n\treturn 0;\n}\n\nstatic struct test_command version_cmd = {\n\t.command = \"version_autotest\",\n\t.callback = test_version,\n};\nREGISTER_TEST_COMMAND(version_cmd);\n" }, { "path": "app/test/virtual_pmd.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"virtual_pmd.h\"\n\n#define MAX_PKT_BURST 512\n\nstatic const char *virtual_ethdev_driver_name = \"Virtual PMD\";\n\nstruct virtual_ethdev_private {\n\tstruct eth_dev_ops dev_ops;\n\tstruct rte_eth_stats eth_stats;\n\n\tstruct rte_ring *rx_queue;\n\tstruct rte_ring *tx_queue;\n\n\tint tx_burst_fail_count;\n};\n\nstruct virtual_ethdev_queue {\n\tint port_id;\n\tint queue_id;\n};\n\nstatic int\nvirtual_ethdev_start_success(struct rte_eth_dev *eth_dev __rte_unused)\n{\n\teth_dev->data->dev_started = 1;\n\n\treturn 0;\n}\n\nstatic int\nvirtual_ethdev_start_fail(struct rte_eth_dev *eth_dev __rte_unused)\n{\n\teth_dev->data->dev_started = 0;\n\n\treturn -1;\n}\nstatic void virtual_ethdev_stop(struct rte_eth_dev *eth_dev __rte_unused)\n{\n\tvoid *pkt = NULL;\n\tstruct virtual_ethdev_private *prv = eth_dev->data->dev_private;\n\n\teth_dev->data->dev_link.link_status = 0;\n\teth_dev->data->dev_started = 0;\n\twhile (rte_ring_dequeue(prv->rx_queue, &pkt) != -ENOENT)\n\t\trte_pktmbuf_free(pkt);\n\n\twhile (rte_ring_dequeue(prv->tx_queue, &pkt) != -ENOENT)\n\t\trte_pktmbuf_free(pkt);\n}\n\nstatic void\nvirtual_ethdev_close(struct rte_eth_dev *dev __rte_unused)\n{}\n\nstatic int\nvirtual_ethdev_configure_success(struct rte_eth_dev *dev __rte_unused)\n{\n\treturn 0;\n}\n\nstatic int\nvirtual_ethdev_configure_fail(struct rte_eth_dev *dev __rte_unused)\n{\n\treturn -1;\n}\n\nstatic void\nvirtual_ethdev_info_get(struct rte_eth_dev *dev __rte_unused,\n\t\tstruct rte_eth_dev_info *dev_info)\n{\n\tdev_info->driver_name = virtual_ethdev_driver_name;\n\tdev_info->max_mac_addrs = 1;\n\n\tdev_info->max_rx_pktlen = (uint32_t)2048;\n\n\tdev_info->max_rx_queues = (uint16_t)128;\n\tdev_info->max_tx_queues = (uint16_t)512;\n\n\tdev_info->min_rx_bufsize = 0;\n\tdev_info->pci_dev = NULL;\n}\n\nstatic int\nvirtual_ethdev_rx_queue_setup_success(struct rte_eth_dev *dev,\n\t\tuint16_t rx_queue_id, uint16_t nb_rx_desc __rte_unused,\n\t\tunsigned int socket_id,\n\t\tconst struct rte_eth_rxconf *rx_conf __rte_unused,\n\t\tstruct rte_mempool *mb_pool __rte_unused)\n{\n\tstruct virtual_ethdev_queue *rx_q;\n\n\trx_q = (struct virtual_ethdev_queue *)rte_zmalloc_socket(NULL,\n\t\t\tsizeof(struct virtual_ethdev_queue), 0, socket_id);\n\n\tif (rx_q == NULL)\n\t\treturn -1;\n\n\trx_q->port_id = dev->data->port_id;\n\trx_q->queue_id = rx_queue_id;\n\n\tdev->data->rx_queues[rx_queue_id] = rx_q;\n\n\treturn 0;\n}\n\nstatic int\nvirtual_ethdev_rx_queue_setup_fail(struct rte_eth_dev *dev __rte_unused,\n\t\tuint16_t rx_queue_id __rte_unused, uint16_t nb_rx_desc __rte_unused,\n\t\tunsigned int socket_id __rte_unused,\n\t\tconst struct rte_eth_rxconf *rx_conf __rte_unused,\n\t\tstruct rte_mempool *mb_pool __rte_unused)\n{\n\treturn -1;\n}\n\nstatic int\nvirtual_ethdev_tx_queue_setup_success(struct rte_eth_dev *dev,\n\t\tuint16_t tx_queue_id, uint16_t nb_tx_desc __rte_unused,\n\t\tunsigned int socket_id,\n\t\tconst struct rte_eth_txconf *tx_conf __rte_unused)\n{\n\tstruct virtual_ethdev_queue *tx_q;\n\n\ttx_q = (struct virtual_ethdev_queue *)rte_zmalloc_socket(NULL,\n\t\t\tsizeof(struct virtual_ethdev_queue), 0, socket_id);\n\n\tif (tx_q == NULL)\n\t\treturn -1;\n\n\ttx_q->port_id = dev->data->port_id;\n\ttx_q->queue_id = tx_queue_id;\n\n\tdev->data->tx_queues[tx_queue_id] = tx_q;\n\n\treturn 0;\n}\n\nstatic int\nvirtual_ethdev_tx_queue_setup_fail(struct rte_eth_dev *dev __rte_unused,\n\t\tuint16_t tx_queue_id __rte_unused, uint16_t nb_tx_desc __rte_unused,\n\t\tunsigned int socket_id __rte_unused,\n\t\tconst struct rte_eth_txconf *tx_conf __rte_unused)\n{\n\treturn -1;\n}\n\nstatic void\nvirtual_ethdev_rx_queue_release(void *q __rte_unused)\n{\n}\n\nstatic void\nvirtual_ethdev_tx_queue_release(void *q __rte_unused)\n{\n}\n\nstatic int\nvirtual_ethdev_link_update_success(struct rte_eth_dev *bonded_eth_dev,\n\t\tint wait_to_complete __rte_unused)\n{\n\tif (!bonded_eth_dev->data->dev_started)\n\t\tbonded_eth_dev->data->dev_link.link_status = 0;\n\n\treturn 0;\n}\n\nstatic int\nvirtual_ethdev_link_update_fail(struct rte_eth_dev *bonded_eth_dev __rte_unused,\n\t\tint wait_to_complete __rte_unused)\n{\n\treturn -1;\n}\n\nstatic void\nvirtual_ethdev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tstruct virtual_ethdev_private *dev_private = dev->data->dev_private;\n\n\tif (stats)\n\t\trte_memcpy(stats, &dev_private->eth_stats, sizeof(*stats));\n}\n\nstatic void\nvirtual_ethdev_stats_reset(struct rte_eth_dev *dev)\n{\n\tstruct virtual_ethdev_private *dev_private = dev->data->dev_private;\n\tvoid *pkt = NULL;\n\n\twhile (rte_ring_dequeue(dev_private->tx_queue, &pkt) == -ENOBUFS)\n\t\t\trte_pktmbuf_free(pkt);\n\n\t/* Reset internal statistics */\n\tmemset(&dev_private->eth_stats, 0, sizeof(dev_private->eth_stats));\n}\n\nstatic void\nvirtual_ethdev_promiscuous_mode_enable(struct rte_eth_dev *dev __rte_unused)\n{}\n\nstatic void\nvirtual_ethdev_promiscuous_mode_disable(struct rte_eth_dev *dev __rte_unused)\n{}\n\n\nstatic const struct eth_dev_ops virtual_ethdev_default_dev_ops = {\n\t.dev_configure = virtual_ethdev_configure_success,\n\t.dev_start = virtual_ethdev_start_success,\n\t.dev_stop = virtual_ethdev_stop,\n\t.dev_close = virtual_ethdev_close,\n\t.dev_infos_get = virtual_ethdev_info_get,\n\t.rx_queue_setup = virtual_ethdev_rx_queue_setup_success,\n\t.tx_queue_setup = virtual_ethdev_tx_queue_setup_success,\n\t.rx_queue_release = virtual_ethdev_rx_queue_release,\n\t.tx_queue_release = virtual_ethdev_tx_queue_release,\n\t.link_update = virtual_ethdev_link_update_success,\n\t.stats_get = virtual_ethdev_stats_get,\n\t.stats_reset = virtual_ethdev_stats_reset,\n\t.promiscuous_enable = virtual_ethdev_promiscuous_mode_enable,\n\t.promiscuous_disable = virtual_ethdev_promiscuous_mode_disable\n};\n\n\nvoid\nvirtual_ethdev_start_fn_set_success(uint8_t port_id, uint8_t success)\n{\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\tstruct virtual_ethdev_private *dev_private = dev->data->dev_private;\n\tstruct eth_dev_ops *dev_ops = &dev_private->dev_ops;\n\n\tif (success)\n\t\tdev_ops->dev_start = virtual_ethdev_start_success;\n\telse\n\t\tdev_ops->dev_start = virtual_ethdev_start_fail;\n\n}\n\nvoid\nvirtual_ethdev_configure_fn_set_success(uint8_t port_id, uint8_t success)\n{\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\tstruct virtual_ethdev_private *dev_private = dev->data->dev_private;\n\tstruct eth_dev_ops *dev_ops = &dev_private->dev_ops;\n\n\tif (success)\n\t\tdev_ops->dev_configure = virtual_ethdev_configure_success;\n\telse\n\t\tdev_ops->dev_configure = virtual_ethdev_configure_fail;\n}\n\nvoid\nvirtual_ethdev_rx_queue_setup_fn_set_success(uint8_t port_id, uint8_t success)\n{\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\tstruct virtual_ethdev_private *dev_private = dev->data->dev_private;\n\tstruct eth_dev_ops *dev_ops = &dev_private->dev_ops;\n\n\tif (success)\n\t\tdev_ops->rx_queue_setup = virtual_ethdev_rx_queue_setup_success;\n\telse\n\t\tdev_ops->rx_queue_setup = virtual_ethdev_rx_queue_setup_fail;\n}\n\nvoid\nvirtual_ethdev_tx_queue_setup_fn_set_success(uint8_t port_id, uint8_t success)\n{\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\tstruct virtual_ethdev_private *dev_private = dev->data->dev_private;\n\tstruct eth_dev_ops *dev_ops = &dev_private->dev_ops;\n\n\tif (success)\n\t\tdev_ops->tx_queue_setup = virtual_ethdev_tx_queue_setup_success;\n\telse\n\t\tdev_ops->tx_queue_setup = virtual_ethdev_tx_queue_setup_fail;\n}\n\nvoid\nvirtual_ethdev_link_update_fn_set_success(uint8_t port_id, uint8_t success)\n{\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\tstruct virtual_ethdev_private *dev_private = dev->data->dev_private;\n\tstruct eth_dev_ops *dev_ops = &dev_private->dev_ops;\n\n\tif (success)\n\t\tdev_ops->link_update = virtual_ethdev_link_update_success;\n\telse\n\t\tdev_ops->link_update = virtual_ethdev_link_update_fail;\n}\n\n\nstatic uint16_t\nvirtual_ethdev_rx_burst_success(void *queue __rte_unused,\n\t\t\t\t\t\t\t struct rte_mbuf **bufs,\n\t\t\t\t\t\t\t uint16_t nb_pkts)\n{\n\tstruct rte_eth_dev *vrtl_eth_dev;\n\tstruct virtual_ethdev_queue *pq_map;\n\tstruct virtual_ethdev_private *dev_private;\n\n\tint rx_count, i;\n\n\tpq_map = (struct virtual_ethdev_queue *)queue;\n\tvrtl_eth_dev = &rte_eth_devices[pq_map->port_id];\n\tdev_private = vrtl_eth_dev->data->dev_private;\n\n\trx_count = rte_ring_dequeue_burst(dev_private->rx_queue, (void **) bufs,\n\t\t\tnb_pkts);\n\n\t/* increments ipackets count */\n\tdev_private->eth_stats.ipackets += rx_count;\n\n\t/* increments ibytes count */\n\tfor (i = 0; i < rx_count; i++)\n\t\tdev_private->eth_stats.ibytes += rte_pktmbuf_pkt_len(bufs[i]);\n\n\treturn rx_count;\n}\n\nstatic uint16_t\nvirtual_ethdev_rx_burst_fail(void *queue __rte_unused,\n\t\t\t\t\t\t\t struct rte_mbuf **bufs __rte_unused,\n\t\t\t\t\t\t\t uint16_t nb_pkts __rte_unused)\n{\n\treturn 0;\n}\n\nstatic uint16_t\nvirtual_ethdev_tx_burst_success(void *queue, struct rte_mbuf **bufs,\n\t\tuint16_t nb_pkts)\n{\n\tstruct virtual_ethdev_queue *tx_q = (struct virtual_ethdev_queue *)queue;\n\n\tstruct rte_eth_dev *vrtl_eth_dev;\n\tstruct virtual_ethdev_private *dev_private;\n\n\tint i;\n\n\tvrtl_eth_dev = &rte_eth_devices[tx_q->port_id];\n\tdev_private = vrtl_eth_dev->data->dev_private;\n\n\tif (!vrtl_eth_dev->data->dev_link.link_status)\n\t\tnb_pkts = 0;\n\telse\n\t\tnb_pkts = rte_ring_enqueue_burst(dev_private->tx_queue, (void **)bufs,\n\t\t\t\tnb_pkts);\n\n\t/* increment opacket count */\n\tdev_private->eth_stats.opackets += nb_pkts;\n\n\t/* increment obytes count */\n\tfor (i = 0; i < nb_pkts; i++)\n\t\tdev_private->eth_stats.obytes += rte_pktmbuf_pkt_len(bufs[i]);\n\n\treturn nb_pkts;\n}\n\nstatic uint16_t\nvirtual_ethdev_tx_burst_fail(void *queue, struct rte_mbuf **bufs,\n\t\tuint16_t nb_pkts)\n{\n\tstruct rte_eth_dev *vrtl_eth_dev = NULL;\n\tstruct virtual_ethdev_queue *tx_q = NULL;\n\tstruct virtual_ethdev_private *dev_private = NULL;\n\n\tint i;\n\n\ttx_q = (struct virtual_ethdev_queue *)queue;\n\tvrtl_eth_dev = &rte_eth_devices[tx_q->port_id];\n\tdev_private = vrtl_eth_dev->data->dev_private;\n\n\tif (dev_private->tx_burst_fail_count < nb_pkts) {\n\t\tint successfully_txd = nb_pkts - dev_private->tx_burst_fail_count;\n\n\t\t/* increment opacket count */\n\t\tdev_private->eth_stats.opackets += successfully_txd;\n\n\t\t/* free packets in burst */\n\t\tfor (i = 0; i < successfully_txd; i++) {\n\t\t\t/* free packets in burst */\n\t\t\tif (bufs[i] != NULL)\n\t\t\t\trte_pktmbuf_free(bufs[i]);\n\n\t\t\tbufs[i] = NULL;\n\t\t}\n\n\t\treturn successfully_txd;\n\t}\n\n\treturn 0;\n}\n\n\nvoid\nvirtual_ethdev_rx_burst_fn_set_success(uint8_t port_id, uint8_t success)\n{\n\tstruct rte_eth_dev *vrtl_eth_dev = &rte_eth_devices[port_id];\n\n\tif (success)\n\t\tvrtl_eth_dev->rx_pkt_burst = virtual_ethdev_rx_burst_success;\n\telse\n\t\tvrtl_eth_dev->rx_pkt_burst = virtual_ethdev_rx_burst_fail;\n}\n\n\nvoid\nvirtual_ethdev_tx_burst_fn_set_success(uint8_t port_id, uint8_t success)\n{\n\tstruct virtual_ethdev_private *dev_private = NULL;\n\tstruct rte_eth_dev *vrtl_eth_dev = &rte_eth_devices[port_id];\n\n\tdev_private = vrtl_eth_dev->data->dev_private;\n\n\tif (success)\n\t\tvrtl_eth_dev->tx_pkt_burst = virtual_ethdev_tx_burst_success;\n\telse\n\t\tvrtl_eth_dev->tx_pkt_burst = virtual_ethdev_tx_burst_fail;\n\n\tdev_private->tx_burst_fail_count = 0;\n}\n\nvoid\nvirtual_ethdev_tx_burst_fn_set_tx_pkt_fail_count(uint8_t port_id,\n\t\tuint8_t packet_fail_count)\n{\n\tstruct virtual_ethdev_private *dev_private = NULL;\n\tstruct rte_eth_dev *vrtl_eth_dev = &rte_eth_devices[port_id];\n\n\n\tdev_private = vrtl_eth_dev->data->dev_private;\n\tdev_private->tx_burst_fail_count = packet_fail_count;\n}\n\nvoid\nvirtual_ethdev_set_link_status(uint8_t port_id, uint8_t link_status)\n{\n\tstruct rte_eth_dev *vrtl_eth_dev = &rte_eth_devices[port_id];\n\n\tvrtl_eth_dev->data->dev_link.link_status = link_status;\n}\n\nvoid\nvirtual_ethdev_simulate_link_status_interrupt(uint8_t port_id,\n\t\tuint8_t link_status)\n{\n\tstruct rte_eth_dev *vrtl_eth_dev = &rte_eth_devices[port_id];\n\n\tvrtl_eth_dev->data->dev_link.link_status = link_status;\n\n\t_rte_eth_dev_callback_process(vrtl_eth_dev, RTE_ETH_EVENT_INTR_LSC);\n}\n\nint\nvirtual_ethdev_add_mbufs_to_rx_queue(uint8_t port_id,\n\t\tstruct rte_mbuf **pkt_burst, int burst_length)\n{\n\tstruct rte_eth_dev *vrtl_eth_dev = &rte_eth_devices[port_id];\n\tstruct virtual_ethdev_private *dev_private =\n\t\t\tvrtl_eth_dev->data->dev_private;\n\n\treturn rte_ring_enqueue_burst(dev_private->rx_queue, (void **)pkt_burst,\n\t\t\tburst_length);\n}\n\nint\nvirtual_ethdev_get_mbufs_from_tx_queue(uint8_t port_id,\n\t\tstruct rte_mbuf **pkt_burst, int burst_length)\n{\n\tstruct virtual_ethdev_private *dev_private;\n\tstruct rte_eth_dev *vrtl_eth_dev = &rte_eth_devices[port_id];\n\n\tdev_private = vrtl_eth_dev->data->dev_private;\n\treturn rte_ring_dequeue_burst(dev_private->tx_queue, (void **)pkt_burst,\n\t\tburst_length);\n}\n\nstatic uint8_t\nget_number_of_sockets(void)\n{\n\tint sockets = 0;\n\tint i;\n\tconst struct rte_memseg *ms = rte_eal_get_physmem_layout();\n\n\tfor (i = 0; i < RTE_MAX_MEMSEG && ms[i].addr != NULL; i++) {\n\t\tif (sockets < ms[i].socket_id)\n\t\t\tsockets = ms[i].socket_id;\n\t}\n\t/* Number of sockets = maximum socket_id + 1 */\n\treturn ++sockets;\n}\n\nint\nvirtual_ethdev_create(const char *name, struct ether_addr *mac_addr,\n\t\tuint8_t socket_id, uint8_t isr_support)\n{\n\tstruct rte_pci_device *pci_dev = NULL;\n\tstruct rte_eth_dev *eth_dev = NULL;\n\tstruct eth_driver *eth_drv = NULL;\n\tstruct rte_pci_driver *pci_drv = NULL;\n\tstruct rte_pci_id *id_table = NULL;\n\tstruct virtual_ethdev_private *dev_private = NULL;\n\tchar name_buf[RTE_RING_NAMESIZE];\n\n\n\t/* now do all data allocation - for eth_dev structure, dummy pci driver\n\t * and internal (dev_private) data\n\t */\n\n\tif (socket_id >= get_number_of_sockets())\n\t\tgoto err;\n\n\tpci_dev = rte_zmalloc_socket(name, sizeof(*pci_dev), 0, socket_id);\n\tif (pci_dev == NULL)\n\t\tgoto err;\n\n\teth_drv = rte_zmalloc_socket(name, sizeof(*eth_drv), 0, socket_id);\n\tif (eth_drv == NULL)\n\t\tgoto err;\n\n\tpci_drv = rte_zmalloc_socket(name, sizeof(*pci_drv), 0, socket_id);\n\tif (pci_drv == NULL)\n\t\tgoto err;\n\n\tid_table = rte_zmalloc_socket(name, sizeof(*id_table), 0, socket_id);\n\tif (id_table == NULL)\n\t\tgoto err;\n\tid_table->device_id = 0xBEEF;\n\n\tdev_private = rte_zmalloc_socket(name, sizeof(*dev_private), 0, socket_id);\n\tif (dev_private == NULL)\n\t\tgoto err;\n\n\tsnprintf(name_buf, sizeof(name_buf), \"%s_rxQ\", name);\n\tdev_private->rx_queue = rte_ring_create(name_buf, MAX_PKT_BURST, socket_id,\n\t\t\t0);\n\tif (dev_private->rx_queue == NULL)\n\t\tgoto err;\n\n\tsnprintf(name_buf, sizeof(name_buf), \"%s_txQ\", name);\n\tdev_private->tx_queue = rte_ring_create(name_buf, MAX_PKT_BURST, socket_id,\n\t\t\t0);\n\tif (dev_private->tx_queue == NULL)\n\t\tgoto err;\n\n\t/* reserve an ethdev entry */\n\teth_dev = rte_eth_dev_allocate(name, RTE_ETH_DEV_PCI);\n\tif (eth_dev == NULL)\n\t\tgoto err;\n\n\tpci_dev->numa_node = socket_id;\n\tpci_drv->name = virtual_ethdev_driver_name;\n\tpci_drv->id_table = id_table;\n\n\tif (isr_support)\n\t\tpci_drv->drv_flags |= RTE_PCI_DRV_INTR_LSC;\n\telse\n\t\tpci_drv->drv_flags &= ~RTE_PCI_DRV_INTR_LSC;\n\n\n\teth_drv->pci_drv = (struct rte_pci_driver)(*pci_drv);\n\teth_dev->driver = eth_drv;\n\n\teth_dev->data->nb_rx_queues = (uint16_t)1;\n\teth_dev->data->nb_tx_queues = (uint16_t)1;\n\n\tTAILQ_INIT(&(eth_dev->link_intr_cbs));\n\n\teth_dev->data->dev_link.link_status = 0;\n\teth_dev->data->dev_link.link_speed = ETH_LINK_SPEED_10000;\n\teth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;\n\n\teth_dev->data->mac_addrs = rte_zmalloc(name, ETHER_ADDR_LEN, 0);\n\tif (eth_dev->data->mac_addrs == NULL)\n\t\tgoto err;\n\n\tmemcpy(eth_dev->data->mac_addrs, mac_addr,\n\t\t\tsizeof(*eth_dev->data->mac_addrs));\n\n\teth_dev->data->dev_started = 0;\n\teth_dev->data->promiscuous = 0;\n\teth_dev->data->scattered_rx = 0;\n\teth_dev->data->all_multicast = 0;\n\n\teth_dev->data->dev_private = dev_private;\n\n\t/* Copy default device operation functions */\n\tdev_private->dev_ops = virtual_ethdev_default_dev_ops;\n\teth_dev->dev_ops = &dev_private->dev_ops;\n\n\teth_dev->pci_dev = pci_dev;\n\teth_dev->pci_dev->driver = ð_drv->pci_drv;\n\n\teth_dev->rx_pkt_burst = virtual_ethdev_rx_burst_success;\n\teth_dev->tx_pkt_burst = virtual_ethdev_tx_burst_success;\n\n\treturn eth_dev->data->port_id;\n\nerr:\n\trte_free(pci_dev);\n\trte_free(pci_drv);\n\trte_free(eth_drv);\n\trte_free(id_table);\n\trte_free(dev_private);\n\n\treturn -1;\n}\n" }, { "path": "app/test/virtual_pmd.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __VIRTUAL_ETHDEV_H_\n#define __VIRTUAL_ETHDEV_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\nint\nvirtual_ethdev_init(void);\n\nint\nvirtual_ethdev_create(const char *name, struct ether_addr *mac_addr,\n\t\tuint8_t socket_id, uint8_t isr_support);\n\nvoid\nvirtual_ethdev_set_link_status(uint8_t port_id, uint8_t link_status);\n\nvoid\nvirtual_ethdev_simulate_link_status_interrupt(uint8_t port_id,\n\t\tuint8_t link_status);\n\nint\nvirtual_ethdev_add_mbufs_to_rx_queue(uint8_t port_id,\n\t\tstruct rte_mbuf **pkts_burst, int burst_length);\n\nint\nvirtual_ethdev_get_mbufs_from_tx_queue(uint8_t port_id,\n\t\tstruct rte_mbuf **pkt_burst, int burst_length);\n\n/** Control methods for the dev_ops functions pointer to control the behavior\n * of the Virtual PMD */\n\nvoid\nvirtual_ethdev_start_fn_set_success(uint8_t port_id, uint8_t success);\n\nvoid\nvirtual_ethdev_stop_fn_set_success(uint8_t port_id, uint8_t success);\n\nvoid\nvirtual_ethdev_configure_fn_set_success(uint8_t port_id, uint8_t success);\n\nvoid\nvirtual_ethdev_rx_queue_setup_fn_set_success(uint8_t port_id, uint8_t success);\n\nvoid\nvirtual_ethdev_tx_queue_setup_fn_set_success(uint8_t port_id, uint8_t success);\n\nvoid\nvirtual_ethdev_link_update_fn_set_success(uint8_t port_id, uint8_t success);\n\nvoid\nvirtual_ethdev_rx_burst_fn_set_success(uint8_t port_id, uint8_t success);\n\nvoid\nvirtual_ethdev_tx_burst_fn_set_success(uint8_t port_id, uint8_t success);\n\n/* if a value greater than zero is set for packet_fail_count then virtual\n * device tx burst function will fail that many packet from burst or all\n * packets if packet_fail_count is greater than the number of packets in the\n * burst */\nvoid\nvirtual_ethdev_tx_burst_fn_set_tx_pkt_fail_count(uint8_t port_id,\n\t\tuint8_t packet_fail_count);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __VIRTUAL_ETHDEV_H_ */\n" }, { "path": "app/test-acl/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifeq ($(CONFIG_RTE_LIBRTE_ACL),y)\n\nAPP = testacl\n\nCFLAGS += $(WERROR_FLAGS)\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\n# this application needs libraries first\nDEPDIRS-y += lib\n\ninclude $(RTE_SDK)/mk/rte.app.mk\n\nendif\n" }, { "path": "app/test-acl/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#define\tPRINT_USAGE_START\t\"%s [EAL options]\\n\"\n\n#define\tRTE_LOGTYPE_TESTACL\tRTE_LOGTYPE_USER1\n\n#define\tAPP_NAME\t\"TESTACL\"\n\n#define GET_CB_FIELD(in, fd, base, lim, dlm)\tdo { \\\n\tunsigned long val; \\\n\tchar *end_fld; \\\n\terrno = 0; \\\n\tval = strtoul((in), &end_fld, (base)); \\\n\tif (errno != 0 || end_fld[0] != (dlm) || val > (lim)) \\\n\t\treturn -EINVAL; \\\n\t(fd) = (typeof(fd))val; \\\n\t(in) = end_fld + 1; \\\n} while (0)\n\n#define\tOPT_RULE_FILE\t\t\"rulesf\"\n#define\tOPT_TRACE_FILE\t\t\"tracef\"\n#define\tOPT_RULE_NUM\t\t\"rulenum\"\n#define\tOPT_TRACE_NUM\t\t\"tracenum\"\n#define\tOPT_TRACE_STEP\t\t\"tracestep\"\n#define\tOPT_SEARCH_ALG\t\t\"alg\"\n#define\tOPT_BLD_CATEGORIES\t\"bldcat\"\n#define\tOPT_RUN_CATEGORIES\t\"runcat\"\n#define\tOPT_MAX_SIZE\t\t\"maxsize\"\n#define\tOPT_ITER_NUM\t\t\"iter\"\n#define\tOPT_VERBOSE\t\t\"verbose\"\n#define\tOPT_IPV6\t\t\"ipv6\"\n\n#define\tTRACE_DEFAULT_NUM\t0x10000\n#define\tTRACE_STEP_MAX\t\t0x1000\n#define\tTRACE_STEP_DEF\t\t0x100\n\n#define\tRULE_NUM\t\t0x10000\n\nenum {\n\tDUMP_NONE,\n\tDUMP_SEARCH,\n\tDUMP_PKT,\n\tDUMP_MAX\n};\n\nstruct acl_alg {\n\tconst char *name;\n\tenum rte_acl_classify_alg alg;\n};\n\nstatic const struct acl_alg acl_alg[] = {\n\t{\n\t\t.name = \"scalar\",\n\t\t.alg = RTE_ACL_CLASSIFY_SCALAR,\n\t},\n\t{\n\t\t.name = \"sse\",\n\t\t.alg = RTE_ACL_CLASSIFY_SSE,\n\t},\n\t{\n\t\t.name = \"avx2\",\n\t\t.alg = RTE_ACL_CLASSIFY_AVX2,\n\t},\n};\n\nstatic struct {\n\tconst char *prgname;\n\tconst char *rule_file;\n\tconst char *trace_file;\n\tsize_t max_size;\n\tuint32_t bld_categories;\n\tuint32_t run_categories;\n\tuint32_t nb_rules;\n\tuint32_t nb_traces;\n\tuint32_t trace_step;\n\tuint32_t trace_sz;\n\tuint32_t iter_num;\n\tuint32_t verbose;\n\tuint32_t ipv6;\n\tstruct acl_alg alg;\n\tuint32_t used_traces;\n\tvoid *traces;\n\tstruct rte_acl_ctx *acx;\n} config = {\n\t.bld_categories = 3,\n\t.run_categories = 1,\n\t.nb_rules = RULE_NUM,\n\t.nb_traces = TRACE_DEFAULT_NUM,\n\t.trace_step = TRACE_STEP_DEF,\n\t.iter_num = 1,\n\t.verbose = DUMP_MAX,\n\t.alg = {\n\t\t.name = \"default\",\n\t\t.alg = RTE_ACL_CLASSIFY_DEFAULT,\n\t},\n\t.ipv6 = 0\n};\n\nstatic struct rte_acl_param prm = {\n\t.name = APP_NAME,\n\t.socket_id = SOCKET_ID_ANY,\n};\n\n/*\n * Rule and trace formats definitions.\n */\n\nstruct ipv4_5tuple {\n\tuint8_t proto;\n\tuint32_t ip_src;\n\tuint32_t ip_dst;\n\tuint16_t port_src;\n\tuint16_t port_dst;\n};\n\nenum {\n\tPROTO_FIELD_IPV4,\n\tSRC_FIELD_IPV4,\n\tDST_FIELD_IPV4,\n\tSRCP_FIELD_IPV4,\n\tDSTP_FIELD_IPV4,\n\tNUM_FIELDS_IPV4\n};\n\nstruct rte_acl_field_def ipv4_defs[NUM_FIELDS_IPV4] = {\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t.size = sizeof(uint8_t),\n\t\t.field_index = PROTO_FIELD_IPV4,\n\t\t.input_index = RTE_ACL_IPV4VLAN_PROTO,\n\t\t.offset = offsetof(struct ipv4_5tuple, proto),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = SRC_FIELD_IPV4,\n\t\t.input_index = RTE_ACL_IPV4VLAN_SRC,\n\t\t.offset = offsetof(struct ipv4_5tuple, ip_src),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = DST_FIELD_IPV4,\n\t\t.input_index = RTE_ACL_IPV4VLAN_DST,\n\t\t.offset = offsetof(struct ipv4_5tuple, ip_dst),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = SRCP_FIELD_IPV4,\n\t\t.input_index = RTE_ACL_IPV4VLAN_PORTS,\n\t\t.offset = offsetof(struct ipv4_5tuple, port_src),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = DSTP_FIELD_IPV4,\n\t\t.input_index = RTE_ACL_IPV4VLAN_PORTS,\n\t\t.offset = offsetof(struct ipv4_5tuple, port_dst),\n\t},\n};\n\n#define\tIPV6_ADDR_LEN\t16\n#define\tIPV6_ADDR_U16\t(IPV6_ADDR_LEN / sizeof(uint16_t))\n#define\tIPV6_ADDR_U32\t(IPV6_ADDR_LEN / sizeof(uint32_t))\n\nstruct ipv6_5tuple {\n\tuint8_t proto;\n\tuint32_t ip_src[IPV6_ADDR_U32];\n\tuint32_t ip_dst[IPV6_ADDR_U32];\n\tuint16_t port_src;\n\tuint16_t port_dst;\n};\n\nenum {\n\tPROTO_FIELD_IPV6,\n\tSRC1_FIELD_IPV6,\n\tSRC2_FIELD_IPV6,\n\tSRC3_FIELD_IPV6,\n\tSRC4_FIELD_IPV6,\n\tDST1_FIELD_IPV6,\n\tDST2_FIELD_IPV6,\n\tDST3_FIELD_IPV6,\n\tDST4_FIELD_IPV6,\n\tSRCP_FIELD_IPV6,\n\tDSTP_FIELD_IPV6,\n\tNUM_FIELDS_IPV6\n};\n\nstruct rte_acl_field_def ipv6_defs[NUM_FIELDS_IPV6] = {\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t.size = sizeof(uint8_t),\n\t\t.field_index = PROTO_FIELD_IPV6,\n\t\t.input_index = PROTO_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_5tuple, proto),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = SRC1_FIELD_IPV6,\n\t\t.input_index = SRC1_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_5tuple, ip_src[0]),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = SRC2_FIELD_IPV6,\n\t\t.input_index = SRC2_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_5tuple, ip_src[1]),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = SRC3_FIELD_IPV6,\n\t\t.input_index = SRC3_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_5tuple, ip_src[2]),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = SRC4_FIELD_IPV6,\n\t\t.input_index = SRC4_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_5tuple, ip_src[3]),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = DST1_FIELD_IPV6,\n\t\t.input_index = DST1_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_5tuple, ip_dst[0]),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = DST2_FIELD_IPV6,\n\t\t.input_index = DST2_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_5tuple, ip_dst[1]),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = DST3_FIELD_IPV6,\n\t\t.input_index = DST3_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_5tuple, ip_dst[2]),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = DST4_FIELD_IPV6,\n\t\t.input_index = DST4_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_5tuple, ip_dst[3]),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = SRCP_FIELD_IPV6,\n\t\t.input_index = SRCP_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_5tuple, port_src),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = DSTP_FIELD_IPV6,\n\t\t.input_index = SRCP_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_5tuple, port_dst),\n\t},\n};\n\n\nenum {\n\tCB_FLD_SRC_ADDR,\n\tCB_FLD_DST_ADDR,\n\tCB_FLD_SRC_PORT_LOW,\n\tCB_FLD_SRC_PORT_DLM,\n\tCB_FLD_SRC_PORT_HIGH,\n\tCB_FLD_DST_PORT_LOW,\n\tCB_FLD_DST_PORT_DLM,\n\tCB_FLD_DST_PORT_HIGH,\n\tCB_FLD_PROTO,\n\tCB_FLD_NUM,\n};\n\nenum {\n\tCB_TRC_SRC_ADDR,\n\tCB_TRC_DST_ADDR,\n\tCB_TRC_SRC_PORT,\n\tCB_TRC_DST_PORT,\n\tCB_TRC_PROTO,\n\tCB_TRC_NUM,\n};\n\nRTE_ACL_RULE_DEF(acl_rule, RTE_ACL_MAX_FIELDS);\n\nstatic const char cb_port_delim[] = \":\";\n\nstatic char line[LINE_MAX];\n\n#define\tdump_verbose(lvl, fh, fmt, args...)\tdo { \\\n\tif ((lvl) <= (int32_t)config.verbose) \\\n\t\tfprintf(fh, fmt, ##args); \\\n} while (0)\n\n\n/*\n * Parse ClassBench input trace (test vectors and expected results) file.\n * Expected format:\n * \\\n * \n */\nstatic int\nparse_cb_ipv4_trace(char *str, struct ipv4_5tuple *v)\n{\n\tint i;\n\tchar *s, *sp, *in[CB_TRC_NUM];\n\tstatic const char *dlm = \" \\t\\n\";\n\n\ts = str;\n\tfor (i = 0; i != RTE_DIM(in); i++) {\n\t\tin[i] = strtok_r(s, dlm, &sp);\n\t\tif (in[i] == NULL)\n\t\t\treturn -EINVAL;\n\t\ts = NULL;\n\t}\n\n\tGET_CB_FIELD(in[CB_TRC_SRC_ADDR], v->ip_src, 0, UINT32_MAX, 0);\n\tGET_CB_FIELD(in[CB_TRC_DST_ADDR], v->ip_dst, 0, UINT32_MAX, 0);\n\tGET_CB_FIELD(in[CB_TRC_SRC_PORT], v->port_src, 0, UINT16_MAX, 0);\n\tGET_CB_FIELD(in[CB_TRC_DST_PORT], v->port_dst, 0, UINT16_MAX, 0);\n\tGET_CB_FIELD(in[CB_TRC_PROTO], v->proto, 0, UINT8_MAX, 0);\n\n\t/* convert to network byte order. */\n\tv->ip_src = rte_cpu_to_be_32(v->ip_src);\n\tv->ip_dst = rte_cpu_to_be_32(v->ip_dst);\n\tv->port_src = rte_cpu_to_be_16(v->port_src);\n\tv->port_dst = rte_cpu_to_be_16(v->port_dst);\n\n\treturn 0;\n}\n\n/*\n * Parses IPV6 address, exepcts the following format:\n * XXXX:XXXX:XXXX:XXXX:XXXX:XXXX:XXXX:XXXX (where X - is a hexedecimal digit).\n */\nstatic int\nparse_ipv6_addr(const char *in, const char **end, uint32_t v[IPV6_ADDR_U32],\n\tchar dlm)\n{\n\tuint32_t addr[IPV6_ADDR_U16];\n\n\tGET_CB_FIELD(in, addr[0], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[1], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[2], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[3], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[4], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[5], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[6], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[7], 16, UINT16_MAX, dlm);\n\n\t*end = in;\n\n\tv[0] = (addr[0] << 16) + addr[1];\n\tv[1] = (addr[2] << 16) + addr[3];\n\tv[2] = (addr[4] << 16) + addr[5];\n\tv[3] = (addr[6] << 16) + addr[7];\n\n\treturn 0;\n}\n\nstatic int\nparse_cb_ipv6_addr_trace(const char *in, uint32_t v[IPV6_ADDR_U32])\n{\n\tint32_t rc;\n\tconst char *end;\n\n\trc = parse_ipv6_addr(in, &end, v, 0);\n\tif (rc != 0)\n\t\treturn rc;\n\n\tv[0] = rte_cpu_to_be_32(v[0]);\n\tv[1] = rte_cpu_to_be_32(v[1]);\n\tv[2] = rte_cpu_to_be_32(v[2]);\n\tv[3] = rte_cpu_to_be_32(v[3]);\n\n\treturn 0;\n}\n\n/*\n * Parse ClassBench input trace (test vectors and expected results) file.\n * Expected format:\n * \\\n * \n */\nstatic int\nparse_cb_ipv6_trace(char *str, struct ipv6_5tuple *v)\n{\n\tint32_t i, rc;\n\tchar *s, *sp, *in[CB_TRC_NUM];\n\tstatic const char *dlm = \" \\t\\n\";\n\n\ts = str;\n\tfor (i = 0; i != RTE_DIM(in); i++) {\n\t\tin[i] = strtok_r(s, dlm, &sp);\n\t\tif (in[i] == NULL)\n\t\t\treturn -EINVAL;\n\t\ts = NULL;\n\t}\n\n\t/* get ip6 src address. */\n\trc = parse_cb_ipv6_addr_trace(in[CB_TRC_SRC_ADDR], v->ip_src);\n\tif (rc != 0)\n\t\treturn rc;\n\n\t/* get ip6 dst address. */\n\trc = parse_cb_ipv6_addr_trace(in[CB_TRC_DST_ADDR], v->ip_dst);\n\tif (rc != 0)\n\t\treturn rc;\n\n\tGET_CB_FIELD(in[CB_TRC_SRC_PORT], v->port_src, 0, UINT16_MAX, 0);\n\tGET_CB_FIELD(in[CB_TRC_DST_PORT], v->port_dst, 0, UINT16_MAX, 0);\n\tGET_CB_FIELD(in[CB_TRC_PROTO], v->proto, 0, UINT8_MAX, 0);\n\n\t/* convert to network byte order. */\n\tv->port_src = rte_cpu_to_be_16(v->port_src);\n\tv->port_dst = rte_cpu_to_be_16(v->port_dst);\n\n\treturn 0;\n}\n\nstatic void\ntracef_init(void)\n{\n\tstatic const char name[] = APP_NAME;\n\tFILE *f;\n\tsize_t sz;\n\tuint32_t n;\n\tstruct ipv4_5tuple *v;\n\tstruct ipv6_5tuple *w;\n\n\tsz = config.nb_traces * (config.ipv6 ? sizeof(*w) : sizeof(*v));\n\tconfig.traces = rte_zmalloc_socket(name, sz, RTE_CACHE_LINE_SIZE,\n\t\t\tSOCKET_ID_ANY);\n\tif (config.traces == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot allocate %zu bytes for \"\n\t\t\t\"requested %u number of trace records\\n\",\n\t\t\tsz, config.nb_traces);\n\n\tf = fopen(config.trace_file, \"r\");\n\tif (f == NULL)\n\t\trte_exit(-EINVAL, \"failed to open file: %s\\n\",\n\t\t\tconfig.trace_file);\n\n\tv = config.traces;\n\tw = config.traces;\n\tfor (n = 0; n != config.nb_traces; n++) {\n\n\t\tif (fgets(line, sizeof(line), f) == NULL)\n\t\t\tbreak;\n\n\t\tif (config.ipv6) {\n\t\t\tif (parse_cb_ipv6_trace(line, w + n) != 0)\n\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\"%s: failed to parse ipv6 trace \"\n\t\t\t\t\t\"record at line %u\\n\",\n\t\t\t\t\tconfig.trace_file, n + 1);\n\t\t} else {\n\t\t\tif (parse_cb_ipv4_trace(line, v + n) != 0)\n\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\"%s: failed to parse ipv4 trace \"\n\t\t\t\t\t\"record at line %u\\n\",\n\t\t\t\t\tconfig.trace_file, n + 1);\n\t\t}\n\t}\n\n\tconfig.used_traces = n;\n\tfclose(f);\n}\n\nstatic int\nparse_ipv6_net(const char *in, struct rte_acl_field field[4])\n{\n\tint32_t rc;\n\tconst char *mp;\n\tuint32_t i, m, v[4];\n\tconst uint32_t nbu32 = sizeof(uint32_t) * CHAR_BIT;\n\n\t/* get address. */\n\trc = parse_ipv6_addr(in, &mp, v, '/');\n\tif (rc != 0)\n\t\treturn rc;\n\n\t/* get mask. */\n\tGET_CB_FIELD(mp, m, 0, CHAR_BIT * sizeof(v), 0);\n\n\t/* put all together. */\n\tfor (i = 0; i != RTE_DIM(v); i++) {\n\t\tif (m >= (i + 1) * nbu32)\n\t\t\tfield[i].mask_range.u32 = nbu32;\n\t\telse\n\t\t\tfield[i].mask_range.u32 = m > (i * nbu32) ?\n\t\t\t\tm - (i * 32) : 0;\n\n\t\tfield[i].value.u32 = v[i];\n\t}\n\n\treturn 0;\n}\n\n\nstatic int\nparse_cb_ipv6_rule(char *str, struct acl_rule *v)\n{\n\tint i, rc;\n\tchar *s, *sp, *in[CB_FLD_NUM];\n\tstatic const char *dlm = \" \\t\\n\";\n\n\t/*\n\t * Skip leading '@'\n\t */\n\tif (strchr(str, '@') != str)\n\t\treturn -EINVAL;\n\n\ts = str + 1;\n\n\tfor (i = 0; i != RTE_DIM(in); i++) {\n\t\tin[i] = strtok_r(s, dlm, &sp);\n\t\tif (in[i] == NULL)\n\t\t\treturn -EINVAL;\n\t\ts = NULL;\n\t}\n\n\trc = parse_ipv6_net(in[CB_FLD_SRC_ADDR], v->field + SRC1_FIELD_IPV6);\n\tif (rc != 0) {\n\t\tRTE_LOG(ERR, TESTACL,\n\t\t\t\"failed to read source address/mask: %s\\n\",\n\t\t\tin[CB_FLD_SRC_ADDR]);\n\t\treturn rc;\n\t}\n\n\trc = parse_ipv6_net(in[CB_FLD_DST_ADDR], v->field + DST1_FIELD_IPV6);\n\tif (rc != 0) {\n\t\tRTE_LOG(ERR, TESTACL,\n\t\t\t\"failed to read destination address/mask: %s\\n\",\n\t\t\tin[CB_FLD_DST_ADDR]);\n\t\treturn rc;\n\t}\n\n\t/* source port. */\n\tGET_CB_FIELD(in[CB_FLD_SRC_PORT_LOW],\n\t\tv->field[SRCP_FIELD_IPV6].value.u16,\n\t\t0, UINT16_MAX, 0);\n\tGET_CB_FIELD(in[CB_FLD_SRC_PORT_HIGH],\n\t\tv->field[SRCP_FIELD_IPV6].mask_range.u16,\n\t\t0, UINT16_MAX, 0);\n\n\tif (strncmp(in[CB_FLD_SRC_PORT_DLM], cb_port_delim,\n\t\t\tsizeof(cb_port_delim)) != 0)\n\t\treturn -EINVAL;\n\n\t/* destination port. */\n\tGET_CB_FIELD(in[CB_FLD_DST_PORT_LOW],\n\t\tv->field[DSTP_FIELD_IPV6].value.u16,\n\t\t0, UINT16_MAX, 0);\n\tGET_CB_FIELD(in[CB_FLD_DST_PORT_HIGH],\n\t\tv->field[DSTP_FIELD_IPV6].mask_range.u16,\n\t\t0, UINT16_MAX, 0);\n\n\tif (strncmp(in[CB_FLD_DST_PORT_DLM], cb_port_delim,\n\t\t\tsizeof(cb_port_delim)) != 0)\n\t\treturn -EINVAL;\n\n\tGET_CB_FIELD(in[CB_FLD_PROTO], v->field[PROTO_FIELD_IPV6].value.u8,\n\t\t0, UINT8_MAX, '/');\n\tGET_CB_FIELD(in[CB_FLD_PROTO], v->field[PROTO_FIELD_IPV6].mask_range.u8,\n\t\t0, UINT8_MAX, 0);\n\n\treturn 0;\n}\n\nstatic int\nparse_ipv4_net(const char *in, uint32_t *addr, uint32_t *mask_len)\n{\n\tuint8_t a, b, c, d, m;\n\n\tGET_CB_FIELD(in, a, 0, UINT8_MAX, '.');\n\tGET_CB_FIELD(in, b, 0, UINT8_MAX, '.');\n\tGET_CB_FIELD(in, c, 0, UINT8_MAX, '.');\n\tGET_CB_FIELD(in, d, 0, UINT8_MAX, '/');\n\tGET_CB_FIELD(in, m, 0, sizeof(uint32_t) * CHAR_BIT, 0);\n\n\taddr[0] = IPv4(a, b, c, d);\n\tmask_len[0] = m;\n\n\treturn 0;\n}\n/*\n * Parse ClassBench rules file.\n * Expected format:\n * '@''/' \\\n * '/' \\\n * \":\" \\\n * \":\" \\\n * '/'\n */\nstatic int\nparse_cb_ipv4_rule(char *str, struct acl_rule *v)\n{\n\tint i, rc;\n\tchar *s, *sp, *in[CB_FLD_NUM];\n\tstatic const char *dlm = \" \\t\\n\";\n\n\t/*\n\t * Skip leading '@'\n\t */\n\tif (strchr(str, '@') != str)\n\t\treturn -EINVAL;\n\n\ts = str + 1;\n\n\tfor (i = 0; i != RTE_DIM(in); i++) {\n\t\tin[i] = strtok_r(s, dlm, &sp);\n\t\tif (in[i] == NULL)\n\t\t\treturn -EINVAL;\n\t\ts = NULL;\n\t}\n\n\trc = parse_ipv4_net(in[CB_FLD_SRC_ADDR],\n\t\t\t&v->field[SRC_FIELD_IPV4].value.u32,\n\t\t\t&v->field[SRC_FIELD_IPV4].mask_range.u32);\n\tif (rc != 0) {\n\t\tRTE_LOG(ERR, TESTACL,\n\t\t\t\"failed to read source address/mask: %s\\n\",\n\t\t\tin[CB_FLD_SRC_ADDR]);\n\t\treturn rc;\n\t}\n\n\trc = parse_ipv4_net(in[CB_FLD_DST_ADDR],\n\t\t\t&v->field[DST_FIELD_IPV4].value.u32,\n\t\t\t&v->field[DST_FIELD_IPV4].mask_range.u32);\n\tif (rc != 0) {\n\t\tRTE_LOG(ERR, TESTACL,\n\t\t\t\"failed to read destination address/mask: %s\\n\",\n\t\t\tin[CB_FLD_DST_ADDR]);\n\t\treturn rc;\n\t}\n\n\t/* source port. */\n\tGET_CB_FIELD(in[CB_FLD_SRC_PORT_LOW],\n\t\tv->field[SRCP_FIELD_IPV4].value.u16,\n\t\t0, UINT16_MAX, 0);\n\tGET_CB_FIELD(in[CB_FLD_SRC_PORT_HIGH],\n\t\tv->field[SRCP_FIELD_IPV4].mask_range.u16,\n\t\t0, UINT16_MAX, 0);\n\n\tif (strncmp(in[CB_FLD_SRC_PORT_DLM], cb_port_delim,\n\t\t\tsizeof(cb_port_delim)) != 0)\n\t\treturn -EINVAL;\n\n\t/* destination port. */\n\tGET_CB_FIELD(in[CB_FLD_DST_PORT_LOW],\n\t\tv->field[DSTP_FIELD_IPV4].value.u16,\n\t\t0, UINT16_MAX, 0);\n\tGET_CB_FIELD(in[CB_FLD_DST_PORT_HIGH],\n\t\tv->field[DSTP_FIELD_IPV4].mask_range.u16,\n\t\t0, UINT16_MAX, 0);\n\n\tif (strncmp(in[CB_FLD_DST_PORT_DLM], cb_port_delim,\n\t\t\tsizeof(cb_port_delim)) != 0)\n\t\treturn -EINVAL;\n\n\tGET_CB_FIELD(in[CB_FLD_PROTO], v->field[PROTO_FIELD_IPV4].value.u8,\n\t\t0, UINT8_MAX, '/');\n\tGET_CB_FIELD(in[CB_FLD_PROTO], v->field[PROTO_FIELD_IPV4].mask_range.u8,\n\t\t0, UINT8_MAX, 0);\n\n\treturn 0;\n}\n\ntypedef int (*parse_5tuple)(char *text, struct acl_rule *rule);\n\nstatic int\nadd_cb_rules(FILE *f, struct rte_acl_ctx *ctx)\n{\n\tint rc;\n\tuint32_t n;\n\tstruct acl_rule v;\n\tparse_5tuple parser;\n\n\tmemset(&v, 0, sizeof(v));\n\tparser = (config.ipv6 != 0) ? parse_cb_ipv6_rule : parse_cb_ipv4_rule;\n\n\tfor (n = 1; fgets(line, sizeof(line), f) != NULL; n++) {\n\n\t\trc = parser(line, &v);\n\t\tif (rc != 0) {\n\t\t\tRTE_LOG(ERR, TESTACL, \"line %u: parse_cb_ipv4vlan_rule\"\n\t\t\t\t\" failed, error code: %d (%s)\\n\",\n\t\t\t\tn, rc, strerror(-rc));\n\t\t\treturn rc;\n\t\t}\n\n\t\tv.data.category_mask = RTE_LEN2MASK(RTE_ACL_MAX_CATEGORIES,\n\t\t\ttypeof(v.data.category_mask));\n\t\tv.data.priority = RTE_ACL_MAX_PRIORITY - n;\n\t\tv.data.userdata = n;\n\n\t\trc = rte_acl_add_rules(ctx, (struct rte_acl_rule *)&v, 1);\n\t\tif (rc != 0) {\n\t\t\tRTE_LOG(ERR, TESTACL, \"line %u: failed to add rules \"\n\t\t\t\t\"into ACL context, error code: %d (%s)\\n\",\n\t\t\t\tn, rc, strerror(-rc));\n\t\t\treturn rc;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic void\nacx_init(void)\n{\n\tint ret;\n\tFILE *f;\n\tstruct rte_acl_config cfg;\n\n\tmemset(&cfg, 0, sizeof(cfg));\n\n\t/* setup ACL build config. */\n\tif (config.ipv6) {\n\t\tcfg.num_fields = RTE_DIM(ipv6_defs);\n\t\tmemcpy(&cfg.defs, ipv6_defs, sizeof(ipv6_defs));\n\t} else {\n\t\tcfg.num_fields = RTE_DIM(ipv4_defs);\n\t\tmemcpy(&cfg.defs, ipv4_defs, sizeof(ipv4_defs));\n\t}\n\tcfg.num_categories = config.bld_categories;\n\tcfg.max_size = config.max_size;\n\n\t/* setup ACL creation parameters. */\n\tprm.rule_size = RTE_ACL_RULE_SZ(cfg.num_fields);\n\tprm.max_rule_num = config.nb_rules;\n\n\tconfig.acx = rte_acl_create(&prm);\n\tif (config.acx == NULL)\n\t\trte_exit(rte_errno, \"failed to create ACL context\\n\");\n\n\t/* set default classify method for this context. */\n\tif (config.alg.alg != RTE_ACL_CLASSIFY_DEFAULT) {\n\t\tret = rte_acl_set_ctx_classify(config.acx, config.alg.alg);\n\t\tif (ret != 0)\n\t\t\trte_exit(ret, \"failed to setup %s method \"\n\t\t\t\t\"for ACL context\\n\", config.alg.name);\n\t}\n\n\t/* add ACL rules. */\n\tf = fopen(config.rule_file, \"r\");\n\tif (f == NULL)\n\t\trte_exit(-EINVAL, \"failed to open file %s\\n\",\n\t\t\tconfig.rule_file);\n\n\tret = add_cb_rules(f, config.acx);\n\tif (ret != 0)\n\t\trte_exit(ret, \"failed to add rules into ACL context\\n\");\n\n\tfclose(f);\n\n\t/* perform build. */\n\tret = rte_acl_build(config.acx, &cfg);\n\n\tdump_verbose(DUMP_NONE, stdout,\n\t\t\"rte_acl_build(%u) finished with %d\\n\",\n\t\tconfig.bld_categories, ret);\n\n\trte_acl_dump(config.acx);\n\n\tif (ret != 0)\n\t\trte_exit(ret, \"failed to build search context\\n\");\n}\n\nstatic uint32_t\nsearch_ip5tuples_once(uint32_t categories, uint32_t step, const char *alg)\n{\n\tint ret;\n\tuint32_t i, j, k, n, r;\n\tconst uint8_t *data[step], *v;\n\tuint32_t results[step * categories];\n\n\tv = config.traces;\n\tfor (i = 0; i != config.used_traces; i += n) {\n\n\t\tn = RTE_MIN(step, config.used_traces - i);\n\n\t\tfor (j = 0; j != n; j++) {\n\t\t\tdata[j] = v;\n\t\t\tv += config.trace_sz;\n\t\t}\n\n\t\tret = rte_acl_classify(config.acx, data, results,\n\t\t\tn, categories);\n\n\t\tif (ret != 0)\n\t\t\trte_exit(ret, \"classify for ipv%c_5tuples returns %d\\n\",\n\t\t\t\tconfig.ipv6 ? '6' : '4', ret);\n\n\t\tfor (r = 0, j = 0; j != n; j++) {\n\t\t\tfor (k = 0; k != categories; k++, r++) {\n\t\t\t\tdump_verbose(DUMP_PKT, stdout,\n\t\t\t\t\t\"ipv%c_5tuple: %u, category: %u, \"\n\t\t\t\t\t\"result: %u\\n\",\n\t\t\t\t\tconfig.ipv6 ? '6' : '4',\n\t\t\t\t\ti + j + 1, k, results[r] - 1);\n\t\t\t}\n\n\t\t}\n\t}\n\n\tdump_verbose(DUMP_SEARCH, stdout,\n\t\t\"%s(%u, %u, %s) returns %u\\n\", __func__,\n\t\tcategories, step, alg, i);\n\treturn i;\n}\n\nstatic int\nsearch_ip5tuples(__attribute__((unused)) void *arg)\n{\n\tuint64_t pkt, start, tm;\n\tuint32_t i, lcore;\n\n\tlcore = rte_lcore_id();\n\tstart = rte_rdtsc();\n\tpkt = 0;\n\n\tfor (i = 0; i != config.iter_num; i++) {\n\t\tpkt += search_ip5tuples_once(config.run_categories,\n\t\t\tconfig.trace_step, config.alg.name);\n\t}\n\n\ttm = rte_rdtsc() - start;\n\tdump_verbose(DUMP_NONE, stdout,\n\t\t\"%s @lcore %u: %\" PRIu32 \" iterations, %\" PRIu64 \" pkts, %\"\n\t\tPRIu32 \" categories, %\" PRIu64 \" cycles, %#Lf cycles/pkt\\n\",\n\t\t__func__, lcore, i, pkt, config.run_categories,\n\t\ttm, (long double)tm / pkt);\n\n\treturn 0;\n}\n\nstatic unsigned long\nget_ulong_opt(const char *opt, const char *name, size_t min, size_t max)\n{\n\tunsigned long val;\n\tchar *end;\n\n\terrno = 0;\n\tval = strtoul(opt, &end, 0);\n\tif (errno != 0 || end[0] != 0 || val > max || val < min)\n\t\trte_exit(-EINVAL, \"invalid value: \\\"%s\\\" for option: %s\\n\",\n\t\t\topt, name);\n\treturn val;\n}\n\nstatic void\nget_alg_opt(const char *opt, const char *name)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i != RTE_DIM(acl_alg); i++) {\n\t\tif (strcmp(opt, acl_alg[i].name) == 0) {\n\t\t\tconfig.alg = acl_alg[i];\n\t\t\treturn;\n\t\t}\n\t}\n\n\trte_exit(-EINVAL, \"invalid value: \\\"%s\\\" for option: %s\\n\",\n\t\topt, name);\n}\n\nstatic void\nprint_usage(const char *prgname)\n{\n\tuint32_t i, n, rc;\n\tchar buf[PATH_MAX];\n\n\tn = 0;\n\tbuf[0] = 0;\n\n\tfor (i = 0; i < RTE_DIM(acl_alg) - 1; i++) {\n\t\trc = snprintf(buf + n, sizeof(buf) - n, \"%s|\",\n\t\t\tacl_alg[i].name);\n\t\tif (rc > sizeof(buf) - n)\n\t\t\tbreak;\n\t\tn += rc;\n\t}\n\n\tsnprintf(buf + n, sizeof(buf) - n, \"%s\", acl_alg[i].name);\n\n\tfprintf(stdout,\n\t\tPRINT_USAGE_START\n\t\t\"--\" OPT_RULE_FILE \"=\\n\"\n\t\t\"[--\" OPT_TRACE_FILE \"=]\\n\"\n\t\t\"[--\" OPT_RULE_NUM\n\t\t\t\"=]\\n\"\n\t\t\"[--\" OPT_TRACE_NUM\n\t\t\t\"=]\\n\"\n\t\t\"[--\" OPT_TRACE_STEP\n\t\t\t\"=]\\n\"\n\t\t\"[--\" OPT_BLD_CATEGORIES\n\t\t\t\"=]\\n\"\n\t\t\"[--\" OPT_RUN_CATEGORIES\n\t\t\t\"= \"\n\t\t\t\"should be either 1 or multiple of %zu, \"\n\t\t\t\"but not greater then %u]\\n\"\n\t\t\"[--\" OPT_MAX_SIZE\n\t\t\t\"= \"\n\t\t\t\"leave 0 for default behaviour]\\n\"\n\t\t\"[--\" OPT_ITER_NUM \"=]\\n\"\n\t\t\"[--\" OPT_VERBOSE \"=]\\n\"\n\t\t\"[--\" OPT_SEARCH_ALG \"=%s]\\n\"\n\t\t\"[--\" OPT_IPV6 \"=]\\n\",\n\t\tprgname, RTE_ACL_RESULTS_MULTIPLIER,\n\t\t(uint32_t)RTE_ACL_MAX_CATEGORIES,\n\t\tbuf);\n}\n\nstatic void\ndump_config(FILE *f)\n{\n\tfprintf(f, \"%s:\\n\", __func__);\n\tfprintf(f, \"%s:%s\\n\", OPT_RULE_FILE, config.rule_file);\n\tfprintf(f, \"%s:%s\\n\", OPT_TRACE_FILE, config.trace_file);\n\tfprintf(f, \"%s:%u\\n\", OPT_RULE_NUM, config.nb_rules);\n\tfprintf(f, \"%s:%u\\n\", OPT_TRACE_NUM, config.nb_traces);\n\tfprintf(f, \"%s:%u\\n\", OPT_TRACE_STEP, config.trace_step);\n\tfprintf(f, \"%s:%u\\n\", OPT_BLD_CATEGORIES, config.bld_categories);\n\tfprintf(f, \"%s:%u\\n\", OPT_RUN_CATEGORIES, config.run_categories);\n\tfprintf(f, \"%s:%zu\\n\", OPT_MAX_SIZE, config.max_size);\n\tfprintf(f, \"%s:%u\\n\", OPT_ITER_NUM, config.iter_num);\n\tfprintf(f, \"%s:%u\\n\", OPT_VERBOSE, config.verbose);\n\tfprintf(f, \"%s:%u(%s)\\n\", OPT_SEARCH_ALG, config.alg.alg,\n\t\tconfig.alg.name);\n\tfprintf(f, \"%s:%u\\n\", OPT_IPV6, config.ipv6);\n}\n\nstatic void\ncheck_config(void)\n{\n\tif (config.rule_file == NULL) {\n\t\tprint_usage(config.prgname);\n\t\trte_exit(-EINVAL, \"mandatory option %s is not specified\\n\",\n\t\t\tOPT_RULE_FILE);\n\t}\n}\n\n\nstatic void\nget_input_opts(int argc, char **argv)\n{\n\tstatic struct option lgopts[] = {\n\t\t{OPT_RULE_FILE, 1, 0, 0},\n\t\t{OPT_TRACE_FILE, 1, 0, 0},\n\t\t{OPT_TRACE_NUM, 1, 0, 0},\n\t\t{OPT_RULE_NUM, 1, 0, 0},\n\t\t{OPT_MAX_SIZE, 1, 0, 0},\n\t\t{OPT_TRACE_STEP, 1, 0, 0},\n\t\t{OPT_BLD_CATEGORIES, 1, 0, 0},\n\t\t{OPT_RUN_CATEGORIES, 1, 0, 0},\n\t\t{OPT_ITER_NUM, 1, 0, 0},\n\t\t{OPT_VERBOSE, 1, 0, 0},\n\t\t{OPT_SEARCH_ALG, 1, 0, 0},\n\t\t{OPT_IPV6, 0, 0, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\tint opt, opt_idx;\n\n\twhile ((opt = getopt_long(argc, argv, \"\", lgopts, &opt_idx)) != EOF) {\n\n\t\tif (opt != 0) {\n\t\t\tprint_usage(config.prgname);\n\t\t\trte_exit(-EINVAL, \"unknown option: %c\", opt);\n\t\t}\n\n\t\tif (strcmp(lgopts[opt_idx].name, OPT_RULE_FILE) == 0) {\n\t\t\tconfig.rule_file = optarg;\n\t\t} else if (strcmp(lgopts[opt_idx].name, OPT_TRACE_FILE) == 0) {\n\t\t\tconfig.trace_file = optarg;\n\t\t} else if (strcmp(lgopts[opt_idx].name, OPT_RULE_NUM) == 0) {\n\t\t\tconfig.nb_rules = get_ulong_opt(optarg,\n\t\t\t\tlgopts[opt_idx].name, 1, RTE_ACL_MAX_INDEX + 1);\n\t\t} else if (strcmp(lgopts[opt_idx].name, OPT_MAX_SIZE) == 0) {\n\t\t\tconfig.max_size = get_ulong_opt(optarg,\n\t\t\t\tlgopts[opt_idx].name, 0, SIZE_MAX);\n\t\t} else if (strcmp(lgopts[opt_idx].name, OPT_TRACE_NUM) == 0) {\n\t\t\tconfig.nb_traces = get_ulong_opt(optarg,\n\t\t\t\tlgopts[opt_idx].name, 1, UINT32_MAX);\n\t\t} else if (strcmp(lgopts[opt_idx].name, OPT_TRACE_STEP) == 0) {\n\t\t\tconfig.trace_step = get_ulong_opt(optarg,\n\t\t\t\tlgopts[opt_idx].name, 1, TRACE_STEP_MAX);\n\t\t} else if (strcmp(lgopts[opt_idx].name,\n\t\t\t\tOPT_BLD_CATEGORIES) == 0) {\n\t\t\tconfig.bld_categories = get_ulong_opt(optarg,\n\t\t\t\tlgopts[opt_idx].name, 1,\n\t\t\t\tRTE_ACL_MAX_CATEGORIES);\n\t\t} else if (strcmp(lgopts[opt_idx].name,\n\t\t\t\tOPT_RUN_CATEGORIES) == 0) {\n\t\t\tconfig.run_categories = get_ulong_opt(optarg,\n\t\t\t\tlgopts[opt_idx].name, 1,\n\t\t\t\tRTE_ACL_MAX_CATEGORIES);\n\t\t} else if (strcmp(lgopts[opt_idx].name, OPT_ITER_NUM) == 0) {\n\t\t\tconfig.iter_num = get_ulong_opt(optarg,\n\t\t\t\tlgopts[opt_idx].name, 1, INT32_MAX);\n\t\t} else if (strcmp(lgopts[opt_idx].name, OPT_VERBOSE) == 0) {\n\t\t\tconfig.verbose = get_ulong_opt(optarg,\n\t\t\t\tlgopts[opt_idx].name, DUMP_NONE, DUMP_MAX);\n\t\t} else if (strcmp(lgopts[opt_idx].name,\n\t\t\t\tOPT_SEARCH_ALG) == 0) {\n\t\t\tget_alg_opt(optarg, lgopts[opt_idx].name);\n\t\t} else if (strcmp(lgopts[opt_idx].name, OPT_IPV6) == 0) {\n\t\t\tconfig.ipv6 = 1;\n\t\t}\n\t}\n\tconfig.trace_sz = config.ipv6 ? sizeof(struct ipv6_5tuple) :\n\t\t\t\t\t\tsizeof(struct ipv4_5tuple);\n\n}\n\nint\nmain(int argc, char **argv)\n{\n\tint ret;\n\tuint32_t lcore;\n\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_panic(\"Cannot init EAL\\n\");\n\n\targc -= ret;\n\targv += ret;\n\n\tconfig.prgname = argv[0];\n\n\tget_input_opts(argc, argv);\n\tdump_config(stdout);\n\tcheck_config();\n\n\tacx_init();\n\n\tif (config.trace_file != NULL)\n\t\ttracef_init();\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore)\n\t\t rte_eal_remote_launch(search_ip5tuples, NULL, lcore);\n\n\tsearch_ip5tuples(NULL);\n\n\trte_eal_mp_wait_lcore();\n\n\trte_acl_free(config.acx);\n\treturn 0;\n}\n" }, { "path": "app/test-pipeline/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifeq ($(CONFIG_RTE_LIBRTE_PIPELINE),y)\n\n#\n# library name\n#\nAPP = testpipeline\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-y := main.c\nSRCS-y += config.c\nSRCS-y += init.c\nSRCS-y += runtime.c\nSRCS-y += pipeline_stub.c\nSRCS-y += pipeline_hash.c\nSRCS-y += pipeline_lpm.c\nSRCS-y += pipeline_lpm_ipv6.c\n\n# include ACL lib if available\nSRCS-$(CONFIG_RTE_LIBRTE_ACL) += pipeline_acl.c\n\n# this application needs libraries first\nDEPDIRS-y += lib drivers\n\ninclude $(RTE_SDK)/mk/rte.app.mk\n\nendif\n" }, { "path": "app/test-pipeline/config.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\nstruct app_params app;\n\nstatic const char usage[] = \"\\n\";\n\nvoid\napp_print_usage(void)\n{\n\tprintf(usage);\n}\n\nstatic int\napp_parse_port_mask(const char *arg)\n{\n\tchar *end = NULL;\n\tuint64_t port_mask;\n\tuint32_t i;\n\n\tif (arg[0] == '\\0')\n\t\treturn -1;\n\n\tport_mask = strtoul(arg, &end, 16);\n\tif ((end == NULL) || (*end != '\\0'))\n\t\treturn -2;\n\n\tif (port_mask == 0)\n\t\treturn -3;\n\n\tapp.n_ports = 0;\n\tfor (i = 0; i < 64; i++) {\n\t\tif ((port_mask & (1LLU << i)) == 0)\n\t\t\tcontinue;\n\n\t\tif (app.n_ports >= APP_MAX_PORTS)\n\t\t\treturn -4;\n\n\t\tapp.ports[app.n_ports] = i;\n\t\tapp.n_ports++;\n\t}\n\n\tif (!rte_is_power_of_2(app.n_ports))\n\t\treturn -5;\n\n\treturn 0;\n}\n\nstruct {\n\tconst char *name;\n\tuint32_t value;\n} app_args_table[] = {\n\t{\"none\", e_APP_PIPELINE_NONE},\n\t{\"stub\", e_APP_PIPELINE_STUB},\n\t{\"hash-8-ext\", e_APP_PIPELINE_HASH_KEY8_EXT},\n\t{\"hash-8-lru\", e_APP_PIPELINE_HASH_KEY8_LRU},\n\t{\"hash-16-ext\", e_APP_PIPELINE_HASH_KEY16_EXT},\n\t{\"hash-16-lru\", e_APP_PIPELINE_HASH_KEY16_LRU},\n\t{\"hash-32-ext\", e_APP_PIPELINE_HASH_KEY32_EXT},\n\t{\"hash-32-lru\", e_APP_PIPELINE_HASH_KEY32_LRU},\n\t{\"hash-spec-8-ext\", e_APP_PIPELINE_HASH_SPEC_KEY8_EXT},\n\t{\"hash-spec-8-lru\", e_APP_PIPELINE_HASH_SPEC_KEY8_LRU},\n\t{\"hash-spec-16-ext\", e_APP_PIPELINE_HASH_SPEC_KEY16_EXT},\n\t{\"hash-spec-16-lru\", e_APP_PIPELINE_HASH_SPEC_KEY16_LRU},\n\t{\"hash-spec-32-ext\", e_APP_PIPELINE_HASH_SPEC_KEY32_EXT},\n\t{\"hash-spec-32-lru\", e_APP_PIPELINE_HASH_SPEC_KEY32_LRU},\n\t{\"acl\", e_APP_PIPELINE_ACL},\n\t{\"lpm\", e_APP_PIPELINE_LPM},\n\t{\"lpm-ipv6\", e_APP_PIPELINE_LPM_IPV6},\n};\n\nint\napp_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{\"none\", 0, 0, 0},\n\t\t{\"stub\", 0, 0, 0},\n\t\t{\"hash-8-ext\", 0, 0, 0},\n\t\t{\"hash-8-lru\", 0, 0, 0},\n\t\t{\"hash-16-ext\", 0, 0, 0},\n\t\t{\"hash-16-lru\", 0, 0, 0},\n\t\t{\"hash-32-ext\", 0, 0, 0},\n\t\t{\"hash-32-lru\", 0, 0, 0},\n\t\t{\"hash-spec-8-ext\", 0, 0, 0},\n\t\t{\"hash-spec-8-lru\", 0, 0, 0},\n\t\t{\"hash-spec-16-ext\", 0, 0, 0},\n\t\t{\"hash-spec-16-lru\", 0, 0, 0},\n\t\t{\"hash-spec-32-ext\", 0, 0, 0},\n\t\t{\"hash-spec-32-lru\", 0, 0, 0},\n\t\t{\"acl\", 0, 0, 0},\n\t\t{\"lpm\", 0, 0, 0},\n\t\t{\"lpm-ipv6\", 0, 0, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\tuint32_t lcores[3], n_lcores, lcore_id, pipeline_type_provided;\n\n\t/* EAL args */\n\tn_lcores = 0;\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\tcontinue;\n\n\t\tif (n_lcores >= 3) {\n\t\t\tRTE_LOG(ERR, USER1, \"Number of cores must be 3\\n\");\n\t\t\tapp_print_usage();\n\t\t\treturn -1;\n\t\t}\n\n\t\tlcores[n_lcores] = lcore_id;\n\t\tn_lcores++;\n\t}\n\n\tif (n_lcores != 3) {\n\t\tRTE_LOG(ERR, USER1, \"Number of cores must be 3\\n\");\n\t\tapp_print_usage();\n\t\treturn -1;\n\t}\n\n\tapp.core_rx = lcores[0];\n\tapp.core_worker = lcores[1];\n\tapp.core_tx = lcores[2];\n\n\t/* Non-EAL args */\n\targvopt = argv;\n\n\tapp.pipeline_type = e_APP_PIPELINE_HASH_KEY16_LRU;\n\tpipeline_type_provided = 0;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:\",\n\t\t\tlgopts, &option_index)) != EOF) {\n\t\tswitch (opt) {\n\t\tcase 'p':\n\t\t\tif (app_parse_port_mask(optarg) < 0) {\n\t\t\t\tapp_print_usage();\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase 0: /* long options */\n\t\t\tif (!pipeline_type_provided) {\n\t\t\t\tuint32_t i;\n\n\t\t\t\tfor (i = 0; i < e_APP_PIPELINES; i++) {\n\t\t\t\t\tif (!strcmp(lgopts[option_index].name,\n\t\t\t\t\t\tapp_args_table[i].name)) {\n\t\t\t\t\t\tapp.pipeline_type =\n\t\t\t\t\t\t\tapp_args_table[i].value;\n\t\t\t\t\t\tpipeline_type_provided = 1;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tapp_print_usage();\n\t\t\treturn -1;\n\n\t\tdefault:\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind - 1] = prgname;\n\n\tret = optind - 1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n" }, { "path": "app/test-pipeline/init.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\nstruct app_params app = {\n\t/* Ports*/\n\t.n_ports = APP_MAX_PORTS,\n\t.port_rx_ring_size = 128,\n\t.port_tx_ring_size = 512,\n\n\t/* Rings */\n\t.ring_rx_size = 128,\n\t.ring_tx_size = 128,\n\n\t/* Buffer pool */\n\t.pool_buffer_size = 2048 + RTE_PKTMBUF_HEADROOM,\n\t.pool_size = 32 * 1024,\n\t.pool_cache_size = 256,\n\n\t/* Burst sizes */\n\t.burst_size_rx_read = 64,\n\t.burst_size_rx_write = 64,\n\t.burst_size_worker_read = 64,\n\t.burst_size_worker_write = 64,\n\t.burst_size_tx_read = 64,\n\t.burst_size_tx_write = 64,\n};\n\nstatic struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /* Header Split disabled */\n\t\t.hw_ip_checksum = 1, /* IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /* VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /* Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /* CRC stripped by hardware */\n\t},\n\t.rx_adv_conf = {\n\t\t.rss_conf = {\n\t\t\t.rss_key = NULL,\n\t\t\t.rss_hf = ETH_RSS_IP,\n\t\t},\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\nstatic struct rte_eth_rxconf rx_conf = {\n\t.rx_thresh = {\n\t\t.pthresh = 8,\n\t\t.hthresh = 8,\n\t\t.wthresh = 4,\n\t},\n\t.rx_free_thresh = 64,\n\t.rx_drop_en = 0,\n};\n\nstatic struct rte_eth_txconf tx_conf = {\n\t.tx_thresh = {\n\t\t.pthresh = 36,\n\t\t.hthresh = 0,\n\t\t.wthresh = 0,\n\t},\n\t.tx_free_thresh = 0,\n\t.tx_rs_thresh = 0,\n};\n\nstatic void\napp_init_mbuf_pools(void)\n{\n\t/* Init the buffer pool */\n\tRTE_LOG(INFO, USER1, \"Creating the mbuf pool ...\\n\");\n\tapp.pool = rte_pktmbuf_pool_create(\"mempool\", app.pool_size,\n\t\tapp.pool_cache_size, 0, app.pool_buffer_size, rte_socket_id());\n\tif (app.pool == NULL)\n\t\trte_panic(\"Cannot create mbuf pool\\n\");\n}\n\nstatic void\napp_init_rings(void)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tchar name[32];\n\n\t\tsnprintf(name, sizeof(name), \"app_ring_rx_%u\", i);\n\n\t\tapp.rings_rx[i] = rte_ring_create(\n\t\t\tname,\n\t\t\tapp.ring_rx_size,\n\t\t\trte_socket_id(),\n\t\t\tRING_F_SP_ENQ | RING_F_SC_DEQ);\n\n\t\tif (app.rings_rx[i] == NULL)\n\t\t\trte_panic(\"Cannot create RX ring %u\\n\", i);\n\t}\n\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tchar name[32];\n\n\t\tsnprintf(name, sizeof(name), \"app_ring_tx_%u\", i);\n\n\t\tapp.rings_tx[i] = rte_ring_create(\n\t\t\tname,\n\t\t\tapp.ring_tx_size,\n\t\t\trte_socket_id(),\n\t\t\tRING_F_SP_ENQ | RING_F_SC_DEQ);\n\n\t\tif (app.rings_tx[i] == NULL)\n\t\t\trte_panic(\"Cannot create TX ring %u\\n\", i);\n\t}\n\n}\n\nstatic void\napp_ports_check_link(void)\n{\n\tuint32_t all_ports_up, i;\n\n\tall_ports_up = 1;\n\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_eth_link link;\n\t\tuint8_t port;\n\n\t\tport = (uint8_t) app.ports[i];\n\t\tmemset(&link, 0, sizeof(link));\n\t\trte_eth_link_get_nowait(port, &link);\n\t\tRTE_LOG(INFO, USER1, \"Port %u (%u Gbps) %s\\n\",\n\t\t\tport,\n\t\t\tlink.link_speed / 1000,\n\t\t\tlink.link_status ? \"UP\" : \"DOWN\");\n\n\t\tif (link.link_status == 0)\n\t\t\tall_ports_up = 0;\n\t}\n\n\tif (all_ports_up == 0)\n\t\trte_panic(\"Some NIC ports are DOWN\\n\");\n}\n\nstatic void\napp_init_ports(void)\n{\n\tuint32_t i;\n\n\t/* Init NIC ports, then start the ports */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tuint8_t port;\n\t\tint ret;\n\n\t\tport = (uint8_t) app.ports[i];\n\t\tRTE_LOG(INFO, USER1, \"Initializing NIC port %u ...\\n\", port);\n\n\t\t/* Init port */\n\t\tret = rte_eth_dev_configure(\n\t\t\tport,\n\t\t\t1,\n\t\t\t1,\n\t\t\t&port_conf);\n\t\tif (ret < 0)\n\t\t\trte_panic(\"Cannot init NIC port %u (%d)\\n\", port, ret);\n\n\t\trte_eth_promiscuous_enable(port);\n\n\t\t/* Init RX queues */\n\t\tret = rte_eth_rx_queue_setup(\n\t\t\tport,\n\t\t\t0,\n\t\t\tapp.port_rx_ring_size,\n\t\t\trte_eth_dev_socket_id(port),\n\t\t\t&rx_conf,\n\t\t\tapp.pool);\n\t\tif (ret < 0)\n\t\t\trte_panic(\"Cannot init RX for port %u (%d)\\n\",\n\t\t\t\t(uint32_t) port, ret);\n\n\t\t/* Init TX queues */\n\t\tret = rte_eth_tx_queue_setup(\n\t\t\tport,\n\t\t\t0,\n\t\t\tapp.port_tx_ring_size,\n\t\t\trte_eth_dev_socket_id(port),\n\t\t\t&tx_conf);\n\t\tif (ret < 0)\n\t\t\trte_panic(\"Cannot init TX for port %u (%d)\\n\",\n\t\t\t\t(uint32_t) port, ret);\n\n\t\t/* Start port */\n\t\tret = rte_eth_dev_start(port);\n\t\tif (ret < 0)\n\t\t\trte_panic(\"Cannot start port %u (%d)\\n\", port, ret);\n\t}\n\n\tapp_ports_check_link();\n}\n\nvoid\napp_init(void)\n{\n\tapp_init_mbuf_pools();\n\tapp_init_rings();\n\tapp_init_ports();\n\n\tRTE_LOG(INFO, USER1, \"Initialization completed\\n\");\n}\n" }, { "path": "app/test-pipeline/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\nint\nmain(int argc, char **argv)\n{\n\tuint32_t lcore;\n\tint ret;\n\n\t/* Init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\treturn -1;\n\targc -= ret;\n\targv += ret;\n\n\t/* Parse application arguments (after the EAL ones) */\n\tret = app_parse_args(argc, argv);\n\tif (ret < 0) {\n\t\tapp_print_usage();\n\t\treturn -1;\n\t}\n\n\t/* Init */\n\tapp_init();\n\n\t/* Launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(app_lcore_main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\tif (rte_eal_wait_lcore(lcore) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nint\napp_lcore_main_loop(__attribute__((unused)) void *arg)\n{\n\tunsigned lcore;\n\n\tlcore = rte_lcore_id();\n\n\tif (lcore == app.core_rx) {\n\t\tswitch (app.pipeline_type) {\n\t\tcase e_APP_PIPELINE_ACL:\n\t\t\tapp_main_loop_rx();\n\t\t\treturn 0;\n\n\t\tdefault:\n\t\t\tapp_main_loop_rx_metadata();\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\tif (lcore == app.core_worker) {\n\t\tswitch (app.pipeline_type) {\n\t\tcase e_APP_PIPELINE_STUB:\n\t\t\tapp_main_loop_worker_pipeline_stub();\n\t\t\treturn 0;\n\n\t\tcase e_APP_PIPELINE_HASH_KEY8_EXT:\n\t\tcase e_APP_PIPELINE_HASH_KEY8_LRU:\n\t\tcase e_APP_PIPELINE_HASH_KEY16_EXT:\n\t\tcase e_APP_PIPELINE_HASH_KEY16_LRU:\n\t\tcase e_APP_PIPELINE_HASH_KEY32_EXT:\n\t\tcase e_APP_PIPELINE_HASH_KEY32_LRU:\n\t\tcase e_APP_PIPELINE_HASH_SPEC_KEY8_EXT:\n\t\tcase e_APP_PIPELINE_HASH_SPEC_KEY8_LRU:\n\t\tcase e_APP_PIPELINE_HASH_SPEC_KEY16_EXT:\n\t\tcase e_APP_PIPELINE_HASH_SPEC_KEY16_LRU:\n\t\tcase e_APP_PIPELINE_HASH_SPEC_KEY32_EXT:\n\t\tcase e_APP_PIPELINE_HASH_SPEC_KEY32_LRU:\n\t\t\tapp_main_loop_worker_pipeline_hash();\n\t\t\treturn 0;\n\n\t\tcase e_APP_PIPELINE_ACL:\n#ifndef RTE_LIBRTE_ACL\n\t\t\trte_exit(EXIT_FAILURE, \"ACL not present in build\\n\");\n#else\n\t\t\tapp_main_loop_worker_pipeline_acl();\n\t\t\treturn 0;\n#endif\n\n\t\tcase e_APP_PIPELINE_LPM:\n\t\t\tapp_main_loop_worker_pipeline_lpm();\n\t\t\treturn 0;\n\n\t\tcase e_APP_PIPELINE_LPM_IPV6:\n\t\t\tapp_main_loop_worker_pipeline_lpm_ipv6();\n\t\t\treturn 0;\n\n\t\tcase e_APP_PIPELINE_NONE:\n\t\tdefault:\n\t\t\tapp_main_loop_worker();\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\tif (lcore == app.core_tx) {\n\t\tapp_main_loop_tx();\n\t\treturn 0;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "app/test-pipeline/main.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _MAIN_H_\n#define _MAIN_H_\n\n#ifndef APP_MBUF_ARRAY_SIZE\n#define APP_MBUF_ARRAY_SIZE 256\n#endif\n\nstruct app_mbuf_array {\n\tstruct rte_mbuf *array[APP_MBUF_ARRAY_SIZE];\n\tuint16_t n_mbufs;\n};\n\n#ifndef APP_MAX_PORTS\n#define APP_MAX_PORTS 4\n#endif\n\nstruct app_params {\n\t/* CPU cores */\n\tuint32_t core_rx;\n\tuint32_t core_worker;\n\tuint32_t core_tx;\n\n\t/* Ports*/\n\tuint32_t ports[APP_MAX_PORTS];\n\tuint32_t n_ports;\n\tuint32_t port_rx_ring_size;\n\tuint32_t port_tx_ring_size;\n\n\t/* Rings */\n\tstruct rte_ring *rings_rx[APP_MAX_PORTS];\n\tstruct rte_ring *rings_tx[APP_MAX_PORTS];\n\tuint32_t ring_rx_size;\n\tuint32_t ring_tx_size;\n\n\t/* Internal buffers */\n\tstruct app_mbuf_array mbuf_rx;\n\tstruct app_mbuf_array mbuf_tx[APP_MAX_PORTS];\n\n\t/* Buffer pool */\n\tstruct rte_mempool *pool;\n\tuint32_t pool_buffer_size;\n\tuint32_t pool_size;\n\tuint32_t pool_cache_size;\n\n\t/* Burst sizes */\n\tuint32_t burst_size_rx_read;\n\tuint32_t burst_size_rx_write;\n\tuint32_t burst_size_worker_read;\n\tuint32_t burst_size_worker_write;\n\tuint32_t burst_size_tx_read;\n\tuint32_t burst_size_tx_write;\n\n\t/* App behavior */\n\tuint32_t pipeline_type;\n} __rte_cache_aligned;\n\nextern struct app_params app;\n\nint app_parse_args(int argc, char **argv);\nvoid app_print_usage(void);\nvoid app_init(void);\nint app_lcore_main_loop(void *arg);\n\n/* Pipeline */\nenum {\n\te_APP_PIPELINE_NONE = 0,\n\te_APP_PIPELINE_STUB,\n\n\te_APP_PIPELINE_HASH_KEY8_EXT,\n\te_APP_PIPELINE_HASH_KEY8_LRU,\n\te_APP_PIPELINE_HASH_KEY16_EXT,\n\te_APP_PIPELINE_HASH_KEY16_LRU,\n\te_APP_PIPELINE_HASH_KEY32_EXT,\n\te_APP_PIPELINE_HASH_KEY32_LRU,\n\n\te_APP_PIPELINE_HASH_SPEC_KEY8_EXT,\n\te_APP_PIPELINE_HASH_SPEC_KEY8_LRU,\n\te_APP_PIPELINE_HASH_SPEC_KEY16_EXT,\n\te_APP_PIPELINE_HASH_SPEC_KEY16_LRU,\n\te_APP_PIPELINE_HASH_SPEC_KEY32_EXT,\n\te_APP_PIPELINE_HASH_SPEC_KEY32_LRU,\n\n\te_APP_PIPELINE_ACL,\n\te_APP_PIPELINE_LPM,\n\te_APP_PIPELINE_LPM_IPV6,\n\te_APP_PIPELINES\n};\n\nvoid app_main_loop_rx(void);\nvoid app_main_loop_rx_metadata(void);\nuint64_t test_hash(void *key, uint32_t key_size, uint64_t seed);\n\nvoid app_main_loop_worker(void);\nvoid app_main_loop_worker_pipeline_stub(void);\nvoid app_main_loop_worker_pipeline_hash(void);\nvoid app_main_loop_worker_pipeline_acl(void);\nvoid app_main_loop_worker_pipeline_lpm(void);\nvoid app_main_loop_worker_pipeline_lpm_ipv6(void);\n\nvoid app_main_loop_tx(void);\n\n#define APP_FLUSH 0\n#ifndef APP_FLUSH\n#define APP_FLUSH 0x3FF\n#endif\n\n#endif /* _MAIN_H_ */\n" }, { "path": "app/test-pipeline/pipeline_acl.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"main.h\"\n\nenum {\n\tPROTO_FIELD_IPV4,\n\tSRC_FIELD_IPV4,\n\tDST_FIELD_IPV4,\n\tSRCP_FIELD_IPV4,\n\tDSTP_FIELD_IPV4,\n\tNUM_FIELDS_IPV4\n};\n\n/*\n * Here we define the 'shape' of the data we're searching for,\n * by defining the meta-data of the ACL rules.\n * in this case, we're defining 5 tuples. IP addresses, ports,\n * and protocol.\n */\nstruct rte_acl_field_def ipv4_field_formats[NUM_FIELDS_IPV4] = {\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t.size = sizeof(uint8_t),\n\t\t.field_index = PROTO_FIELD_IPV4,\n\t\t.input_index = PROTO_FIELD_IPV4,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\toffsetof(struct ipv4_hdr, next_proto_id),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = SRC_FIELD_IPV4,\n\t\t.input_index = SRC_FIELD_IPV4,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\toffsetof(struct ipv4_hdr, src_addr),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = DST_FIELD_IPV4,\n\t\t.input_index = DST_FIELD_IPV4,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\toffsetof(struct ipv4_hdr, dst_addr),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = SRCP_FIELD_IPV4,\n\t\t.input_index = SRCP_FIELD_IPV4,\n\t\t.offset = sizeof(struct ether_hdr) + sizeof(struct ipv4_hdr),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = DSTP_FIELD_IPV4,\n\t\t.input_index = SRCP_FIELD_IPV4,\n\t\t.offset = sizeof(struct ether_hdr) + sizeof(struct ipv4_hdr) +\n\t\t\tsizeof(uint16_t),\n\t},\n};\n\n\n\nvoid\napp_main_loop_worker_pipeline_acl(void) {\n\tstruct rte_pipeline_params pipeline_params = {\n\t\t.name = \"pipeline\",\n\t\t.socket_id = rte_socket_id(),\n\t};\n\n\tstruct rte_pipeline *p;\n\tuint32_t port_in_id[APP_MAX_PORTS];\n\tuint32_t port_out_id[APP_MAX_PORTS];\n\tuint32_t table_id;\n\tuint32_t i;\n\n\tRTE_LOG(INFO, USER1,\n\t\t\"Core %u is doing work (pipeline with ACL table)\\n\",\n\t\trte_lcore_id());\n\n\t/* Pipeline configuration */\n\tp = rte_pipeline_create(&pipeline_params);\n\tif (p == NULL)\n\t\trte_panic(\"Unable to configure the pipeline\\n\");\n\n\t/* Input port configuration */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_port_ring_reader_params port_ring_params = {\n\t\t\t.ring = app.rings_rx[i],\n\t\t};\n\n\t\tstruct rte_pipeline_port_in_params port_params = {\n\t\t\t.ops = &rte_port_ring_reader_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.burst_size = app.burst_size_worker_read,\n\t\t};\n\n\t\tif (rte_pipeline_port_in_create(p, &port_params,\n\t\t\t&port_in_id[i]))\n\t\t\trte_panic(\"Unable to configure input port for \"\n\t\t\t\t\"ring %d\\n\", i);\n\t}\n\n\t/* Output port configuration */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_port_ring_writer_params port_ring_params = {\n\t\t\t.ring = app.rings_tx[i],\n\t\t\t.tx_burst_sz = app.burst_size_worker_write,\n\t\t};\n\n\t\tstruct rte_pipeline_port_out_params port_params = {\n\t\t\t.ops = &rte_port_ring_writer_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.f_action_bulk = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t};\n\n\t\tif (rte_pipeline_port_out_create(p, &port_params,\n\t\t\t&port_out_id[i]))\n\t\t\trte_panic(\"Unable to configure output port for \"\n\t\t\t\t\"ring %d\\n\", i);\n\t}\n\n\t/* Table configuration */\n\t{\n\t\tstruct rte_table_acl_params table_acl_params = {\n\t\t\t.name = \"test\", /* unique identifier for acl contexts */\n\t\t\t.n_rules = 1 << 5,\n\t\t\t.n_rule_fields = DIM(ipv4_field_formats),\n\t\t};\n\n\t\t/* Copy in the rule meta-data defined above into the params */\n\t\tmemcpy(table_acl_params.field_format, ipv4_field_formats,\n\t\t\tsizeof(ipv4_field_formats));\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_acl_ops,\n\t\t\t.arg_create = &table_acl_params,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id))\n\t\t\trte_panic(\"Unable to configure the ACL table\\n\");\n\t}\n\n\t/* Interconnecting ports and tables */\n\tfor (i = 0; i < app.n_ports; i++)\n\t\tif (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],\n\t\t\ttable_id))\n\t\t\trte_panic(\"Unable to connect input port %u to \"\n\t\t\t\t\"table %u\\n\", port_in_id[i], table_id);\n\n\t/* Add entries to tables */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_pipeline_table_entry table_entry = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = port_out_id[i & (app.n_ports - 1)]},\n\t\t};\n\t\tstruct rte_table_acl_rule_add_params rule_params;\n\t\tstruct rte_pipeline_table_entry *entry_ptr;\n\t\tint key_found, ret;\n\n\t\tmemset(&rule_params, 0, sizeof(rule_params));\n\n\t\t/* Set the rule values */\n\t\trule_params.field_value[SRC_FIELD_IPV4].value.u32 = 0;\n\t\trule_params.field_value[SRC_FIELD_IPV4].mask_range.u32 = 0;\n\t\trule_params.field_value[DST_FIELD_IPV4].value.u32 =\n\t\t\ti << (24 - __builtin_popcount(app.n_ports - 1));\n\t\trule_params.field_value[DST_FIELD_IPV4].mask_range.u32 =\n\t\t\t8 + __builtin_popcount(app.n_ports - 1);\n\t\trule_params.field_value[SRCP_FIELD_IPV4].value.u16 = 0;\n\t\trule_params.field_value[SRCP_FIELD_IPV4].mask_range.u16 =\n\t\t\tUINT16_MAX;\n\t\trule_params.field_value[DSTP_FIELD_IPV4].value.u16 = 0;\n\t\trule_params.field_value[DSTP_FIELD_IPV4].mask_range.u16 =\n\t\t\tUINT16_MAX;\n\t\trule_params.field_value[PROTO_FIELD_IPV4].value.u8 = 0;\n\t\trule_params.field_value[PROTO_FIELD_IPV4].mask_range.u8 = 0;\n\n\t\trule_params.priority = 0;\n\n\t\tuint32_t dst_addr = rule_params.field_value[DST_FIELD_IPV4].\n\t\t\tvalue.u32;\n\t\tuint32_t dst_mask =\n\t\t\trule_params.field_value[DST_FIELD_IPV4].mask_range.u32;\n\n\t\tprintf(\"Adding rule to ACL table (IPv4 destination = \"\n\t\t\t\"%u.%u.%u.%u/%u => port out = %u)\\n\",\n\t\t\t(dst_addr & 0xFF000000) >> 24,\n\t\t\t(dst_addr & 0x00FF0000) >> 16,\n\t\t\t(dst_addr & 0x0000FF00) >> 8,\n\t\t\tdst_addr & 0x000000FF,\n\t\t\tdst_mask,\n\t\t\ttable_entry.port_id);\n\n\t\t/* For ACL, add needs an rte_table_acl_rule_add_params struct */\n\t\tret = rte_pipeline_table_entry_add(p, table_id, &rule_params,\n\t\t\t&table_entry, &key_found, &entry_ptr);\n\t\tif (ret < 0)\n\t\t\trte_panic(\"Unable to add entry to table %u (%d)\\n\",\n\t\t\t\ttable_id, ret);\n\t}\n\n\t/* Enable input ports */\n\tfor (i = 0; i < app.n_ports; i++)\n\t\tif (rte_pipeline_port_in_enable(p, port_in_id[i]))\n\t\t\trte_panic(\"Unable to enable input port %u\\n\",\n\t\t\t\tport_in_id[i]);\n\n\t/* Check pipeline consistency */\n\tif (rte_pipeline_check(p) < 0)\n\t\trte_panic(\"Pipeline consistency check failed\\n\");\n\n\t/* Run-time */\n#if APP_FLUSH == 0\n\tfor ( ; ; )\n\t\trte_pipeline_run(p);\n#else\n\tfor (i = 0; ; i++) {\n\t\trte_pipeline_run(p);\n\n\t\tif ((i & APP_FLUSH) == 0)\n\t\t\trte_pipeline_flush(p);\n\t}\n#endif\n}\n" }, { "path": "app/test-pipeline/pipeline_hash.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"main.h\"\n\nstatic void\ntranslate_options(uint32_t *special, uint32_t *ext, uint32_t *key_size)\n{\n\tswitch (app.pipeline_type) {\n\tcase e_APP_PIPELINE_HASH_KEY8_EXT:\n\t\t*special = 0; *ext = 1; *key_size = 8; return;\n\tcase e_APP_PIPELINE_HASH_KEY8_LRU:\n\t\t*special = 0; *ext = 0; *key_size = 8; return;\n\tcase e_APP_PIPELINE_HASH_KEY16_EXT:\n\t\t*special = 0; *ext = 1; *key_size = 16; return;\n\tcase e_APP_PIPELINE_HASH_KEY16_LRU:\n\t\t*special = 0; *ext = 0; *key_size = 16; return;\n\tcase e_APP_PIPELINE_HASH_KEY32_EXT:\n\t\t*special = 0; *ext = 1; *key_size = 32; return;\n\tcase e_APP_PIPELINE_HASH_KEY32_LRU:\n\t\t*special = 0; *ext = 0; *key_size = 32; return;\n\n\tcase e_APP_PIPELINE_HASH_SPEC_KEY8_EXT:\n\t\t*special = 1; *ext = 1; *key_size = 8; return;\n\tcase e_APP_PIPELINE_HASH_SPEC_KEY8_LRU:\n\t\t*special = 1; *ext = 0; *key_size = 8; return;\n\tcase e_APP_PIPELINE_HASH_SPEC_KEY16_EXT:\n\t\t*special = 1; *ext = 1; *key_size = 16; return;\n\tcase e_APP_PIPELINE_HASH_SPEC_KEY16_LRU:\n\t\t*special = 1; *ext = 0; *key_size = 16; return;\n\tcase e_APP_PIPELINE_HASH_SPEC_KEY32_EXT:\n\t\t*special = 1; *ext = 1; *key_size = 32; return;\n\tcase e_APP_PIPELINE_HASH_SPEC_KEY32_LRU:\n\t\t*special = 1; *ext = 0; *key_size = 32; return;\n\n\tdefault:\n\t\trte_panic(\"Invalid hash table type or key size\\n\");\n\t}\n}\nvoid\napp_main_loop_worker_pipeline_hash(void) {\n\tstruct rte_pipeline_params pipeline_params = {\n\t\t.name = \"pipeline\",\n\t\t.socket_id = rte_socket_id(),\n\t};\n\n\tstruct rte_pipeline *p;\n\tuint32_t port_in_id[APP_MAX_PORTS];\n\tuint32_t port_out_id[APP_MAX_PORTS];\n\tuint32_t table_id;\n\tuint32_t i;\n\tuint32_t special, ext, key_size;\n\n\ttranslate_options(&special, &ext, &key_size);\n\n\tRTE_LOG(INFO, USER1, \"Core %u is doing work \"\n\t\t\"(pipeline with hash table, %s, %s, %d-byte key)\\n\",\n\t\trte_lcore_id(),\n\t\tspecial ? \"specialized\" : \"non-specialized\",\n\t\text ? \"extendible bucket\" : \"LRU\",\n\t\tkey_size);\n\n\t/* Pipeline configuration */\n\tp = rte_pipeline_create(&pipeline_params);\n\tif (p == NULL)\n\t\trte_panic(\"Unable to configure the pipeline\\n\");\n\n\t/* Input port configuration */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_port_ring_reader_params port_ring_params = {\n\t\t\t.ring = app.rings_rx[i],\n\t\t};\n\n\t\tstruct rte_pipeline_port_in_params port_params = {\n\t\t\t.ops = &rte_port_ring_reader_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.burst_size = app.burst_size_worker_read,\n\t\t};\n\n\t\tif (rte_pipeline_port_in_create(p, &port_params,\n\t\t\t&port_in_id[i]))\n\t\t\trte_panic(\"Unable to configure input port for \"\n\t\t\t\t\"ring %d\\n\", i);\n\t}\n\n\t/* Output port configuration */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_port_ring_writer_params port_ring_params = {\n\t\t\t.ring = app.rings_tx[i],\n\t\t\t.tx_burst_sz = app.burst_size_worker_write,\n\t\t};\n\n\t\tstruct rte_pipeline_port_out_params port_params = {\n\t\t\t.ops = &rte_port_ring_writer_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.f_action_bulk = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t};\n\n\t\tif (rte_pipeline_port_out_create(p, &port_params,\n\t\t\t&port_out_id[i]))\n\t\t\trte_panic(\"Unable to configure output port for \"\n\t\t\t\t\"ring %d\\n\", i);\n\t}\n\n\t/* Table configuration */\n\tswitch (app.pipeline_type) {\n\tcase e_APP_PIPELINE_HASH_KEY8_EXT:\n\tcase e_APP_PIPELINE_HASH_KEY16_EXT:\n\tcase e_APP_PIPELINE_HASH_KEY32_EXT:\n\t{\n\t\tstruct rte_table_hash_ext_params table_hash_params = {\n\t\t\t.key_size = key_size,\n\t\t\t.n_keys = 1 << 24,\n\t\t\t.n_buckets = 1 << 22,\n\t\t\t.n_buckets_ext = 1 << 21,\n\t\t\t.f_hash = test_hash,\n\t\t\t.seed = 0,\n\t\t\t.signature_offset = 0,\n\t\t\t.key_offset = 32,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_hash_ext_ops,\n\t\t\t.arg_create = &table_hash_params,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id))\n\t\t\trte_panic(\"Unable to configure the hash table\\n\");\n\t}\n\tbreak;\n\n\tcase e_APP_PIPELINE_HASH_KEY8_LRU:\n\tcase e_APP_PIPELINE_HASH_KEY16_LRU:\n\tcase e_APP_PIPELINE_HASH_KEY32_LRU:\n\t{\n\t\tstruct rte_table_hash_lru_params table_hash_params = {\n\t\t\t.key_size = key_size,\n\t\t\t.n_keys = 1 << 24,\n\t\t\t.n_buckets = 1 << 22,\n\t\t\t.f_hash = test_hash,\n\t\t\t.seed = 0,\n\t\t\t.signature_offset = 0,\n\t\t\t.key_offset = 32,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_hash_lru_ops,\n\t\t\t.arg_create = &table_hash_params,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id))\n\t\t\trte_panic(\"Unable to configure the hash table\\n\");\n\t}\n\tbreak;\n\n\tcase e_APP_PIPELINE_HASH_SPEC_KEY8_EXT:\n\t{\n\t\tstruct rte_table_hash_key8_ext_params table_hash_params = {\n\t\t\t.n_entries = 1 << 24,\n\t\t\t.n_entries_ext = 1 << 23,\n\t\t\t.signature_offset = 0,\n\t\t\t.key_offset = 32,\n\t\t\t.f_hash = test_hash,\n\t\t\t.seed = 0,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_hash_key8_ext_ops,\n\t\t\t.arg_create = &table_hash_params,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id))\n\t\t\trte_panic(\"Unable to configure the hash table\\n\");\n\t}\n\tbreak;\n\n\tcase e_APP_PIPELINE_HASH_SPEC_KEY8_LRU:\n\t{\n\t\tstruct rte_table_hash_key8_lru_params table_hash_params = {\n\t\t\t.n_entries = 1 << 24,\n\t\t\t.signature_offset = 0,\n\t\t\t.key_offset = 32,\n\t\t\t.f_hash = test_hash,\n\t\t\t.seed = 0,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_hash_key8_lru_ops,\n\t\t\t.arg_create = &table_hash_params,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id))\n\t\t\trte_panic(\"Unable to configure the hash table\\n\");\n\t}\n\tbreak;\n\n\tcase e_APP_PIPELINE_HASH_SPEC_KEY16_EXT:\n\t{\n\t\tstruct rte_table_hash_key16_ext_params table_hash_params = {\n\t\t\t.n_entries = 1 << 24,\n\t\t\t.n_entries_ext = 1 << 23,\n\t\t\t.signature_offset = 0,\n\t\t\t.key_offset = 32,\n\t\t\t.f_hash = test_hash,\n\t\t\t.seed = 0,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_hash_key16_ext_ops,\n\t\t\t.arg_create = &table_hash_params,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id))\n\t\t\trte_panic(\"Unable to configure the hash table)\\n\");\n\t}\n\tbreak;\n\n\tcase e_APP_PIPELINE_HASH_SPEC_KEY16_LRU:\n\t{\n\t\tstruct rte_table_hash_key16_lru_params table_hash_params = {\n\t\t\t.n_entries = 1 << 24,\n\t\t\t.signature_offset = 0,\n\t\t\t.key_offset = 32,\n\t\t\t.f_hash = test_hash,\n\t\t\t.seed = 0,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_hash_key16_lru_ops,\n\t\t\t.arg_create = &table_hash_params,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id))\n\t\t\trte_panic(\"Unable to configure the hash table\\n\");\n\t}\n\tbreak;\n\n\tcase e_APP_PIPELINE_HASH_SPEC_KEY32_EXT:\n\t{\n\t\tstruct rte_table_hash_key32_ext_params table_hash_params = {\n\t\t\t.n_entries = 1 << 24,\n\t\t\t.n_entries_ext = 1 << 23,\n\t\t\t.signature_offset = 0,\n\t\t\t.key_offset = 32,\n\t\t\t.f_hash = test_hash,\n\t\t\t.seed = 0,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_hash_key32_ext_ops,\n\t\t\t.arg_create = &table_hash_params,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id))\n\t\t\trte_panic(\"Unable to configure the hash table\\n\");\n\t}\n\tbreak;\n\n\n\tcase e_APP_PIPELINE_HASH_SPEC_KEY32_LRU:\n\t{\n\t\tstruct rte_table_hash_key32_lru_params table_hash_params = {\n\t\t\t.n_entries = 1 << 24,\n\t\t\t.signature_offset = 0,\n\t\t\t.key_offset = 32,\n\t\t\t.f_hash = test_hash,\n\t\t\t.seed = 0,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_hash_key32_lru_ops,\n\t\t\t.arg_create = &table_hash_params,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id))\n\t\t\trte_panic(\"Unable to configure the hash table\\n\");\n\t}\n\tbreak;\n\n\tdefault:\n\t\trte_panic(\"Invalid hash table type or key size\\n\");\n\t}\n\n\t/* Interconnecting ports and tables */\n\tfor (i = 0; i < app.n_ports; i++)\n\t\tif (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],\n\t\t\ttable_id))\n\t\t\trte_panic(\"Unable to connect input port %u to \"\n\t\t\t\t\"table %u\\n\", port_in_id[i], table_id);\n\n\t/* Add entries to tables */\n\tfor (i = 0; i < (1 << 24); i++) {\n\t\tstruct rte_pipeline_table_entry entry = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = port_out_id[i & (app.n_ports - 1)]},\n\t\t};\n\t\tstruct rte_pipeline_table_entry *entry_ptr;\n\t\tuint8_t key[32];\n\t\tuint32_t *k32 = (uint32_t *) key;\n\t\tint key_found, status;\n\n\t\tmemset(key, 0, sizeof(key));\n\t\tk32[0] = rte_be_to_cpu_32(i);\n\n\t\tstatus = rte_pipeline_table_entry_add(p, table_id, key, &entry,\n\t\t\t&key_found, &entry_ptr);\n\t\tif (status < 0)\n\t\t\trte_panic(\"Unable to add entry to table %u (%d)\\n\",\n\t\t\t\ttable_id, status);\n\t}\n\n\t/* Enable input ports */\n\tfor (i = 0; i < app.n_ports; i++)\n\t\tif (rte_pipeline_port_in_enable(p, port_in_id[i]))\n\t\t\trte_panic(\"Unable to enable input port %u\\n\",\n\t\t\t\tport_in_id[i]);\n\n\t/* Check pipeline consistency */\n\tif (rte_pipeline_check(p) < 0)\n\t\trte_panic(\"Pipeline consistency check failed\\n\");\n\n\t/* Run-time */\n#if APP_FLUSH == 0\n\tfor ( ; ; )\n\t\trte_pipeline_run(p);\n#else\n\tfor (i = 0; ; i++) {\n\t\trte_pipeline_run(p);\n\n\t\tif ((i & APP_FLUSH) == 0)\n\t\t\trte_pipeline_flush(p);\n\t}\n#endif\n}\n\nuint64_t test_hash(\n\tvoid *key,\n\t__attribute__((unused)) uint32_t key_size,\n\t__attribute__((unused)) uint64_t seed)\n{\n\tuint32_t *k32 = (uint32_t *) key;\n\tuint32_t ip_dst = rte_be_to_cpu_32(k32[0]);\n\tuint64_t signature = (ip_dst >> 2) | ((ip_dst & 0x3) << 30);\n\n\treturn signature;\n}\n\nvoid\napp_main_loop_rx_metadata(void) {\n\tuint32_t i, j;\n\tint ret;\n\n\tRTE_LOG(INFO, USER1, \"Core %u is doing RX (with meta-data)\\n\",\n\t\trte_lcore_id());\n\n\tfor (i = 0; ; i = ((i + 1) & (app.n_ports - 1))) {\n\t\tuint16_t n_mbufs;\n\n\t\tn_mbufs = rte_eth_rx_burst(\n\t\t\tapp.ports[i],\n\t\t\t0,\n\t\t\tapp.mbuf_rx.array,\n\t\t\tapp.burst_size_rx_read);\n\n\t\tif (n_mbufs == 0)\n\t\t\tcontinue;\n\n\t\tfor (j = 0; j < n_mbufs; j++) {\n\t\t\tstruct rte_mbuf *m;\n\t\t\tuint8_t *m_data, *key;\n\t\t\tstruct ipv4_hdr *ip_hdr;\n\t\t\tstruct ipv6_hdr *ipv6_hdr;\n\t\t\tuint32_t ip_dst;\n\t\t\tuint8_t *ipv6_dst;\n\t\t\tuint32_t *signature, *k32;\n\n\t\t\tm = app.mbuf_rx.array[j];\n\t\t\tm_data = rte_pktmbuf_mtod(m, uint8_t *);\n\t\t\tsignature = RTE_MBUF_METADATA_UINT32_PTR(m, 0);\n\t\t\tkey = RTE_MBUF_METADATA_UINT8_PTR(m, 32);\n\n#ifdef RTE_NEXT_ABI\n\t\t\tif (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {\n#else\n\t\t\tif (m->ol_flags & PKT_RX_IPV4_HDR) {\n#endif\n\t\t\t\tip_hdr = (struct ipv4_hdr *)\n\t\t\t\t\t&m_data[sizeof(struct ether_hdr)];\n\t\t\t\tip_dst = ip_hdr->dst_addr;\n\n\t\t\t\tk32 = (uint32_t *) key;\n\t\t\t\tk32[0] = ip_dst & 0xFFFFFF00;\n#ifdef RTE_NEXT_ABI\n\t\t\t} else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {\n#else\n\t\t\t} else {\n#endif\n\t\t\t\tipv6_hdr = (struct ipv6_hdr *)\n\t\t\t\t\t&m_data[sizeof(struct ether_hdr)];\n\t\t\t\tipv6_dst = ipv6_hdr->dst_addr;\n\n\t\t\t\tmemcpy(key, ipv6_dst, 16);\n#ifdef RTE_NEXT_ABI\n\t\t\t} else\n\t\t\t\tcontinue;\n#else\n\t\t\t}\n#endif\n\n\t\t\t*signature = test_hash(key, 0, 0);\n\t\t}\n\n\t\tdo {\n\t\t\tret = rte_ring_sp_enqueue_bulk(\n\t\t\t\tapp.rings_rx[i],\n\t\t\t\t(void **) app.mbuf_rx.array,\n\t\t\t\tn_mbufs);\n\t\t} while (ret < 0);\n\t}\n}\n" }, { "path": "app/test-pipeline/pipeline_lpm.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"main.h\"\n\nvoid\napp_main_loop_worker_pipeline_lpm(void) {\n\tstruct rte_pipeline_params pipeline_params = {\n\t\t.name = \"pipeline\",\n\t\t.socket_id = rte_socket_id(),\n\t};\n\n\tstruct rte_pipeline *p;\n\tuint32_t port_in_id[APP_MAX_PORTS];\n\tuint32_t port_out_id[APP_MAX_PORTS];\n\tuint32_t table_id;\n\tuint32_t i;\n\n\tRTE_LOG(INFO, USER1, \"Core %u is doing work (pipeline with \"\n\t\t\"LPM table)\\n\", rte_lcore_id());\n\n\t/* Pipeline configuration */\n\tp = rte_pipeline_create(&pipeline_params);\n\tif (p == NULL)\n\t\trte_panic(\"Unable to configure the pipeline\\n\");\n\n\t/* Input port configuration */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_port_ring_reader_params port_ring_params = {\n\t\t\t.ring = app.rings_rx[i],\n\t\t};\n\n\t\tstruct rte_pipeline_port_in_params port_params = {\n\t\t\t.ops = &rte_port_ring_reader_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.burst_size = app.burst_size_worker_read,\n\t\t};\n\n\t\tif (rte_pipeline_port_in_create(p, &port_params,\n\t\t\t&port_in_id[i]))\n\t\t\trte_panic(\"Unable to configure input port for \"\n\t\t\t\t\"ring %d\\n\", i);\n\t}\n\n\t/* Output port configuration */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_port_ring_writer_params port_ring_params = {\n\t\t\t.ring = app.rings_tx[i],\n\t\t\t.tx_burst_sz = app.burst_size_worker_write,\n\t\t};\n\n\t\tstruct rte_pipeline_port_out_params port_params = {\n\t\t\t.ops = &rte_port_ring_writer_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.f_action_bulk = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t};\n\n\t\tif (rte_pipeline_port_out_create(p, &port_params,\n\t\t\t&port_out_id[i]))\n\t\t\trte_panic(\"Unable to configure output port for \"\n\t\t\t\t\"ring %d\\n\", i);\n\t}\n\n\t/* Table configuration */\n\t{\n\t\tstruct rte_table_lpm_params table_lpm_params = {\n\t\t\t.n_rules = 1 << 24,\n\t\t\t.entry_unique_size =\n\t\t\t\tsizeof(struct rte_pipeline_table_entry),\n\t\t\t.offset = 32,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_lpm_ops,\n\t\t\t.arg_create = &table_lpm_params,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id))\n\t\t\trte_panic(\"Unable to configure the LPM table\\n\");\n\t}\n\n\t/* Interconnecting ports and tables */\n\tfor (i = 0; i < app.n_ports; i++)\n\t\tif (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],\n\t\t\ttable_id))\n\t\t\trte_panic(\"Unable to connect input port %u to \"\n\t\t\t\t\"table %u\\n\", port_in_id[i], table_id);\n\n\t/* Add entries to tables */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_pipeline_table_entry entry = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = port_out_id[i & (app.n_ports - 1)]},\n\t\t};\n\n\t\tstruct rte_table_lpm_key key = {\n\t\t\t.ip = i << (24 - __builtin_popcount(app.n_ports - 1)),\n\t\t\t.depth = 8 + __builtin_popcount(app.n_ports - 1),\n\t\t};\n\n\t\tstruct rte_pipeline_table_entry *entry_ptr;\n\n\t\tint key_found, status;\n\n\t\tprintf(\"Adding rule to LPM table (IPv4 destination = %\"\n\t\t\tPRIu32 \".%\" PRIu32 \".%\" PRIu32 \".%\" PRIu32 \"/%\" PRIu8\n\t\t\t\" => port out = %\" PRIu32 \")\\n\",\n\t\t\t(key.ip & 0xFF000000) >> 24,\n\t\t\t(key.ip & 0x00FF0000) >> 16,\n\t\t\t(key.ip & 0x0000FF00) >> 8,\n\t\t\tkey.ip & 0x000000FF,\n\t\t\tkey.depth,\n\t\t\ti);\n\n\t\tstatus = rte_pipeline_table_entry_add(p, table_id, &key, &entry,\n\t\t\t&key_found, &entry_ptr);\n\t\tif (status < 0)\n\t\t\trte_panic(\"Unable to add entry to table %u (%d)\\n\",\n\t\t\t\ttable_id, status);\n\t}\n\n\t/* Enable input ports */\n\tfor (i = 0; i < app.n_ports; i++)\n\t\tif (rte_pipeline_port_in_enable(p, port_in_id[i]))\n\t\t\trte_panic(\"Unable to enable input port %u\\n\",\n\t\t\t\tport_in_id[i]);\n\n\t/* Check pipeline consistency */\n\tif (rte_pipeline_check(p) < 0)\n\t\trte_panic(\"Pipeline consistency check failed\\n\");\n\n\t/* Run-time */\n#if APP_FLUSH == 0\n\tfor ( ; ; )\n\t\trte_pipeline_run(p);\n#else\n\tfor (i = 0; ; i++) {\n\t\trte_pipeline_run(p);\n\n\t\tif ((i & APP_FLUSH) == 0)\n\t\t\trte_pipeline_flush(p);\n\t}\n#endif\n}\n" }, { "path": "app/test-pipeline/pipeline_lpm_ipv6.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"main.h\"\n\nvoid\napp_main_loop_worker_pipeline_lpm_ipv6(void) {\n\tstruct rte_pipeline_params pipeline_params = {\n\t\t.name = \"pipeline\",\n\t\t.socket_id = rte_socket_id(),\n\t};\n\n\tstruct rte_pipeline *p;\n\tuint32_t port_in_id[APP_MAX_PORTS];\n\tuint32_t port_out_id[APP_MAX_PORTS];\n\tuint32_t table_id;\n\tuint32_t i;\n\n\tRTE_LOG(INFO, USER1,\n\t\t\"Core %u is doing work (pipeline with IPv6 LPM table)\\n\",\n\t\trte_lcore_id());\n\n\t/* Pipeline configuration */\n\tp = rte_pipeline_create(&pipeline_params);\n\tif (p == NULL)\n\t\trte_panic(\"Unable to configure the pipeline\\n\");\n\n\t/* Input port configuration */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_port_ring_reader_params port_ring_params = {\n\t\t\t.ring = app.rings_rx[i],\n\t\t};\n\n\t\tstruct rte_pipeline_port_in_params port_params = {\n\t\t\t.ops = &rte_port_ring_reader_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.burst_size = app.burst_size_worker_read,\n\t\t};\n\n\t\tif (rte_pipeline_port_in_create(p, &port_params,\n\t\t\t&port_in_id[i]))\n\t\t\trte_panic(\"Unable to configure input port for \"\n\t\t\t\t\"ring %d\\n\", i);\n\t}\n\n\t/* Output port configuration */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_port_ring_writer_params port_ring_params = {\n\t\t\t.ring = app.rings_tx[i],\n\t\t\t.tx_burst_sz = app.burst_size_worker_write,\n\t\t};\n\n\t\tstruct rte_pipeline_port_out_params port_params = {\n\t\t\t.ops = &rte_port_ring_writer_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.f_action_bulk = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t};\n\n\t\tif (rte_pipeline_port_out_create(p, &port_params,\n\t\t\t&port_out_id[i]))\n\t\t\trte_panic(\"Unable to configure output port for \"\n\t\t\t\t\"ring %d\\n\", i);\n\t}\n\n\t/* Table configuration */\n\t{\n\t\tstruct rte_table_lpm_ipv6_params table_lpm_ipv6_params = {\n\t\t\t.n_rules = 1 << 24,\n\t\t\t.number_tbl8s = 1 << 21,\n\t\t\t.entry_unique_size =\n\t\t\t\tsizeof(struct rte_pipeline_table_entry),\n\t\t\t.offset = 32,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_lpm_ipv6_ops,\n\t\t\t.arg_create = &table_lpm_ipv6_params,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id))\n\t\t\trte_panic(\"Unable to configure the IPv6 LPM table\\n\");\n\t}\n\n\t/* Interconnecting ports and tables */\n\tfor (i = 0; i < app.n_ports; i++)\n\t\tif (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],\n\t\t\ttable_id))\n\t\t\trte_panic(\"Unable to connect input port %u to \"\n\t\t\t\t\"table %u\\n\", port_in_id[i], table_id);\n\n\t/* Add entries to tables */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_pipeline_table_entry entry = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = port_out_id[i & (app.n_ports - 1)]},\n\t\t};\n\n\t\tstruct rte_table_lpm_ipv6_key key;\n\t\tstruct rte_pipeline_table_entry *entry_ptr;\n\t\tuint32_t ip;\n\t\tint key_found, status;\n\n\t\tkey.depth = 8 + __builtin_popcount(app.n_ports - 1);\n\n\t\tip = rte_bswap32(i << (24 -\n\t\t\t__builtin_popcount(app.n_ports - 1)));\n\t\tmemcpy(key.ip, &ip, sizeof(uint32_t));\n\n\t\tprintf(\"Adding rule to IPv6 LPM table (IPv6 destination = \"\n\t\t\t\"%.2x%.2x:%.2x%.2x:%.2x%.2x:%.2x%.2x:\"\n\t\t\t\"%.2x%.2x:%.2x%.2x:%.2x%.2x:%.2x%.2x/%u => \"\n\t\t\t\"port out = %u)\\n\",\n\t\t\tkey.ip[0], key.ip[1], key.ip[2], key.ip[3],\n\t\t\tkey.ip[4], key.ip[5], key.ip[6], key.ip[7],\n\t\t\tkey.ip[8], key.ip[9], key.ip[10], key.ip[11],\n\t\t\tkey.ip[12], key.ip[13], key.ip[14], key.ip[15],\n\t\t\tkey.depth, i);\n\n\t\tstatus = rte_pipeline_table_entry_add(p, table_id, &key, &entry,\n\t\t\t&key_found, &entry_ptr);\n\t\tif (status < 0)\n\t\t\trte_panic(\"Unable to add entry to table %u (%d)\\n\",\n\t\t\t\ttable_id, status);\n\t}\n\n\t/* Enable input ports */\n\tfor (i = 0; i < app.n_ports; i++)\n\t\tif (rte_pipeline_port_in_enable(p, port_in_id[i]))\n\t\t\trte_panic(\"Unable to enable input port %u\\n\",\n\t\t\t\tport_in_id[i]);\n\n\t/* Check pipeline consistency */\n\tif (rte_pipeline_check(p) < 0)\n\t\trte_panic(\"Pipeline consistency check failed\\n\");\n\n\t/* Run-time */\n#if APP_FLUSH == 0\n\tfor ( ; ; )\n\t\trte_pipeline_run(p);\n#else\n\tfor (i = 0; ; i++) {\n\t\trte_pipeline_run(p);\n\n\t\tif ((i & APP_FLUSH) == 0)\n\t\t\trte_pipeline_flush(p);\n\t}\n#endif\n}\n" }, { "path": "app/test-pipeline/pipeline_stub.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\nvoid\napp_main_loop_worker_pipeline_stub(void) {\n\tstruct rte_pipeline_params pipeline_params = {\n\t\t.name = \"pipeline\",\n\t\t.socket_id = rte_socket_id(),\n\t};\n\n\tstruct rte_pipeline *p;\n\tuint32_t port_in_id[APP_MAX_PORTS];\n\tuint32_t port_out_id[APP_MAX_PORTS];\n\tuint32_t table_id[APP_MAX_PORTS];\n\tuint32_t i;\n\n\tRTE_LOG(INFO, USER1, \"Core %u is doing work (pipeline with stub \"\n\t\t\"tables)\\n\", rte_lcore_id());\n\n\t/* Pipeline configuration */\n\tp = rte_pipeline_create(&pipeline_params);\n\tif (p == NULL)\n\t\trte_panic(\"Unable to configure the pipeline\\n\");\n\n\t/* Input port configuration */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_port_ring_reader_params port_ring_params = {\n\t\t\t.ring = app.rings_rx[i],\n\t\t};\n\n\t\tstruct rte_pipeline_port_in_params port_params = {\n\t\t\t.ops = &rte_port_ring_reader_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.burst_size = app.burst_size_worker_read,\n\t\t};\n\n\t\tif (rte_pipeline_port_in_create(p, &port_params,\n\t\t\t&port_in_id[i]))\n\t\t\trte_panic(\"Unable to configure input port for \"\n\t\t\t\t\"ring %d\\n\", i);\n\t}\n\n\t/* Output port configuration */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_port_ring_writer_params port_ring_params = {\n\t\t\t.ring = app.rings_tx[i],\n\t\t\t.tx_burst_sz = app.burst_size_worker_write,\n\t\t};\n\n\t\tstruct rte_pipeline_port_out_params port_params = {\n\t\t\t.ops = &rte_port_ring_writer_ops,\n\t\t\t.arg_create = (void *) &port_ring_params,\n\t\t\t.f_action = NULL,\n\t\t\t.f_action_bulk = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t};\n\n\t\tif (rte_pipeline_port_out_create(p, &port_params,\n\t\t\t&port_out_id[i]))\n\t\t\trte_panic(\"Unable to configure output port for \"\n\t\t\t\t\"ring %d\\n\", i);\n\t}\n\n\t/* Table configuration */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_stub_ops,\n\t\t\t.arg_create = NULL,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tif (rte_pipeline_table_create(p, &table_params, &table_id[i]))\n\t\t\trte_panic(\"Unable to configure table %u\\n\", i);\n\t}\n\n\t/* Interconnecting ports and tables */\n\tfor (i = 0; i < app.n_ports; i++)\n\t\tif (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],\n\t\t\t\ttable_id[i]))\n\t\t\trte_panic(\"Unable to connect input port %u to \"\n\t\t\t\t\"table %u\\n\", port_in_id[i], table_id[i]);\n\n\t/* Add entries to tables */\n\tfor (i = 0; i < app.n_ports; i++) {\n\t\tstruct rte_pipeline_table_entry entry = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = port_out_id[i ^ 1]},\n\t\t};\n\t\tstruct rte_pipeline_table_entry *default_entry_ptr;\n\n\t\tif (rte_pipeline_table_default_entry_add(p, table_id[i], &entry,\n\t\t\t&default_entry_ptr))\n\t\t\trte_panic(\"Unable to add default entry to table %u\\n\",\n\t\t\t\ttable_id[i]);\n\t}\n\n\t/* Enable input ports */\n\tfor (i = 0; i < app.n_ports; i++)\n\t\tif (rte_pipeline_port_in_enable(p, port_in_id[i]))\n\t\t\trte_panic(\"Unable to enable input port %u\\n\",\n\t\t\t\tport_in_id[i]);\n\n\t/* Check pipeline consistency */\n\tif (rte_pipeline_check(p) < 0)\n\t\trte_panic(\"Pipeline consistency check failed\\n\");\n\n\t/* Run-time */\n#if APP_FLUSH == 0\n\tfor ( ; ; )\n\t\trte_pipeline_run(p);\n#else\n\tfor (i = 0; ; i++) {\n\t\trte_pipeline_run(p);\n\n\t\tif ((i & APP_FLUSH) == 0)\n\t\t\trte_pipeline_flush(p);\n\t}\n#endif\n}\n" }, { "path": "app/test-pipeline/runtime.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\nvoid\napp_main_loop_rx(void) {\n\tuint32_t i;\n\tint ret;\n\n\tRTE_LOG(INFO, USER1, \"Core %u is doing RX\\n\", rte_lcore_id());\n\n\tfor (i = 0; ; i = ((i + 1) & (app.n_ports - 1))) {\n\t\tuint16_t n_mbufs;\n\n\t\tn_mbufs = rte_eth_rx_burst(\n\t\t\tapp.ports[i],\n\t\t\t0,\n\t\t\tapp.mbuf_rx.array,\n\t\t\tapp.burst_size_rx_read);\n\n\t\tif (n_mbufs == 0)\n\t\t\tcontinue;\n\n\t\tdo {\n\t\t\tret = rte_ring_sp_enqueue_bulk(\n\t\t\t\tapp.rings_rx[i],\n\t\t\t\t(void **) app.mbuf_rx.array,\n\t\t\t\tn_mbufs);\n\t\t} while (ret < 0);\n\t}\n}\n\nvoid\napp_main_loop_worker(void) {\n\tstruct app_mbuf_array *worker_mbuf;\n\tuint32_t i;\n\n\tRTE_LOG(INFO, USER1, \"Core %u is doing work (no pipeline)\\n\",\n\t\trte_lcore_id());\n\n\tworker_mbuf = rte_malloc_socket(NULL, sizeof(struct app_mbuf_array),\n\t\t\tRTE_CACHE_LINE_SIZE, rte_socket_id());\n\tif (worker_mbuf == NULL)\n\t\trte_panic(\"Worker thread: cannot allocate buffer space\\n\");\n\n\tfor (i = 0; ; i = ((i + 1) & (app.n_ports - 1))) {\n\t\tint ret;\n\n\t\tret = rte_ring_sc_dequeue_bulk(\n\t\t\tapp.rings_rx[i],\n\t\t\t(void **) worker_mbuf->array,\n\t\t\tapp.burst_size_worker_read);\n\n\t\tif (ret == -ENOENT)\n\t\t\tcontinue;\n\n\t\tdo {\n\t\t\tret = rte_ring_sp_enqueue_bulk(\n\t\t\t\tapp.rings_tx[i ^ 1],\n\t\t\t\t(void **) worker_mbuf->array,\n\t\t\t\tapp.burst_size_worker_write);\n\t\t} while (ret < 0);\n\t}\n}\n\nvoid\napp_main_loop_tx(void) {\n\tuint32_t i;\n\n\tRTE_LOG(INFO, USER1, \"Core %u is doing TX\\n\", rte_lcore_id());\n\n\tfor (i = 0; ; i = ((i + 1) & (app.n_ports - 1))) {\n\t\tuint16_t n_mbufs, n_pkts;\n\t\tint ret;\n\n\t\tn_mbufs = app.mbuf_tx[i].n_mbufs;\n\n\t\tret = rte_ring_sc_dequeue_bulk(\n\t\t\tapp.rings_tx[i],\n\t\t\t(void **) &app.mbuf_tx[i].array[n_mbufs],\n\t\t\tapp.burst_size_tx_read);\n\n\t\tif (ret == -ENOENT)\n\t\t\tcontinue;\n\n\t\tn_mbufs += app.burst_size_tx_read;\n\n\t\tif (n_mbufs < app.burst_size_tx_write) {\n\t\t\tapp.mbuf_tx[i].n_mbufs = n_mbufs;\n\t\t\tcontinue;\n\t\t}\n\n\t\tn_pkts = rte_eth_tx_burst(\n\t\t\tapp.ports[i],\n\t\t\t0,\n\t\t\tapp.mbuf_tx[i].array,\n\t\t\tn_mbufs);\n\n\t\tif (n_pkts < n_mbufs) {\n\t\t\tuint16_t k;\n\n\t\t\tfor (k = n_pkts; k < n_mbufs; k++) {\n\t\t\t\tstruct rte_mbuf *pkt_to_free;\n\n\t\t\t\tpkt_to_free = app.mbuf_tx[i].array[k];\n\t\t\t\trte_pktmbuf_free(pkt_to_free);\n\t\t\t}\n\t\t}\n\n\t\tapp.mbuf_tx[i].n_mbufs = 0;\n\t}\n}\n" }, { "path": "app/test-pmd/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifeq ($(CONFIG_RTE_TEST_PMD),y)\n\n#\n# library name\n#\nAPP = testpmd\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-y := testpmd.c\nSRCS-y += parameters.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += cmdline.c\nSRCS-y += config.c\nSRCS-y += iofwd.c\nSRCS-y += macfwd.c\nSRCS-y += macfwd-retry.c\nSRCS-y += macswap.c\nSRCS-y += flowgen.c\nSRCS-y += rxonly.c\nSRCS-y += txonly.c\nSRCS-y += csumonly.c\nSRCS-y += icmpecho.c\nSRCS-$(CONFIG_RTE_LIBRTE_IEEE1588) += ieee1588fwd.c\nSRCS-y += mempool_anon.c\n\nifeq ($(CONFIG_RTE_EXEC_ENV_LINUXAPP),y)\nCFLAGS_mempool_anon.o := -D_GNU_SOURCE\nendif\nCFLAGS_cmdline.o := -D_GNU_SOURCE\n\n# this application needs libraries first\nDEPDIRS-y += lib drivers\n\ninclude $(RTE_SDK)/mk/rte.app.mk\n\nendif\n" }, { "path": "app/test-pmd/cmdline.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * Copyright(c) 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#ifndef __linux__\n#ifndef __FreeBSD__\n#include \n#else\n#include \n#endif\n#endif\n#include \n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#ifdef RTE_LIBRTE_PMD_BOND\n#include \n#endif\n\n#include \"testpmd.h\"\n\nstatic void cmd_reconfig_device_queue(portid_t id, uint8_t dev, uint8_t queue);\n\n#ifdef RTE_NIC_BYPASS\nuint8_t bypass_is_supported(portid_t port_id);\n#endif\n\n/* *** Help command with introduction. *** */\nstruct cmd_help_brief_result {\n\tcmdline_fixed_string_t help;\n};\n\nstatic void cmd_help_brief_parsed(__attribute__((unused)) void *parsed_result,\n struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n\tcmdline_printf(\n\t\tcl,\n\t\t\"\\n\"\n\t\t\"Help is available for the following sections:\\n\\n\"\n\t\t\" help control : Start and stop forwarding.\\n\"\n\t\t\" help display : Displaying port, stats and config \"\n\t\t\"information.\\n\"\n\t\t\" help config : Configuration information.\\n\"\n\t\t\" help ports : Configuring ports.\\n\"\n\t\t\" help registers : Reading and setting port registers.\\n\"\n\t\t\" help filters : Filters configuration help.\\n\"\n\t\t\" help all : All of the above sections.\\n\\n\"\n\t);\n\n}\n\ncmdline_parse_token_string_t cmd_help_brief_help =\n\tTOKEN_STRING_INITIALIZER(struct cmd_help_brief_result, help, \"help\");\n\ncmdline_parse_inst_t cmd_help_brief = {\n\t.f = cmd_help_brief_parsed,\n\t.data = NULL,\n\t.help_str = \"show help\",\n\t.tokens = {\n\t\t(void *)&cmd_help_brief_help,\n\t\tNULL,\n\t},\n};\n\n/* *** Help command with help sections. *** */\nstruct cmd_help_long_result {\n\tcmdline_fixed_string_t help;\n\tcmdline_fixed_string_t section;\n};\n\nstatic void cmd_help_long_parsed(void *parsed_result,\n struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n\tint show_all = 0;\n\tstruct cmd_help_long_result *res = parsed_result;\n\n\tif (!strcmp(res->section, \"all\"))\n\t\tshow_all = 1;\n\n\tif (show_all || !strcmp(res->section, \"control\")) {\n\n\t\tcmdline_printf(\n\t\t\tcl,\n\t\t\t\"\\n\"\n\t\t\t\"Control forwarding:\\n\"\n\t\t\t\"-------------------\\n\\n\"\n\n\t\t\t\"start\\n\"\n\t\t\t\" Start packet forwarding with current configuration.\\n\\n\"\n\n\t\t\t\"start tx_first\\n\"\n\t\t\t\" Start packet forwarding with current config\"\n\t\t\t\" after sending one burst of packets.\\n\\n\"\n\n\t\t\t\"stop\\n\"\n\t\t\t\" Stop packet forwarding, and display accumulated\"\n\t\t\t\" statistics.\\n\\n\"\n\n\t\t\t\"quit\\n\"\n\t\t\t\" Quit to prompt.\\n\\n\"\n\t\t);\n\t}\n\n\tif (show_all || !strcmp(res->section, \"display\")) {\n\n\t\tcmdline_printf(\n\t\t\tcl,\n\t\t\t\"\\n\"\n\t\t\t\"Display:\\n\"\n\t\t\t\"--------\\n\\n\"\n\n\t\t\t\"show port (info|stats|xstats|fdir|stat_qmap) (port_id|all)\\n\"\n\t\t\t\" Display information for port_id, or all.\\n\\n\"\n\n\t\t\t\"show port X rss reta (size) (mask0,mask1,...)\\n\"\n\t\t\t\" Display the rss redirection table entry indicated\"\n\t\t\t\" by masks on port X. size is used to indicate the\"\n\t\t\t\" hardware supported reta size\\n\\n\"\n\n\t\t\t\"show port rss-hash [key]\\n\"\n\t\t\t\" Display the RSS hash functions and RSS hash key\"\n\t\t\t\" of port X\\n\\n\"\n\n\t\t\t\"clear port (info|stats|xstats|fdir|stat_qmap) (port_id|all)\\n\"\n\t\t\t\" Clear information for port_id, or all.\\n\\n\"\n\n\t\t\t\"show config (rxtx|cores|fwd)\\n\"\n\t\t\t\" Display the given configuration.\\n\\n\"\n\n\t\t\t\"read rxd (port_id) (queue_id) (rxd_id)\\n\"\n\t\t\t\" Display an RX descriptor of a port RX queue.\\n\\n\"\n\n\t\t\t\"read txd (port_id) (queue_id) (txd_id)\\n\"\n\t\t\t\" Display a TX descriptor of a port TX queue.\\n\\n\"\n\t\t);\n\t}\n\n\tif (show_all || !strcmp(res->section, \"config\")) {\n\t\tcmdline_printf(\n\t\t\tcl,\n\t\t\t\"\\n\"\n\t\t\t\"Configuration:\\n\"\n\t\t\t\"--------------\\n\"\n\t\t\t\"Configuration changes only become active when\"\n\t\t\t\" forwarding is started/restarted.\\n\\n\"\n\n\t\t\t\"set default\\n\"\n\t\t\t\" Reset forwarding to the default configuration.\\n\\n\"\n\n\t\t\t\"set verbose (level)\\n\"\n\t\t\t\" Set the debug verbosity level X.\\n\\n\"\n\n\t\t\t\"set nbport (num)\\n\"\n\t\t\t\" Set number of ports.\\n\\n\"\n\n\t\t\t\"set nbcore (num)\\n\"\n\t\t\t\" Set number of cores.\\n\\n\"\n\n\t\t\t\"set coremask (mask)\\n\"\n\t\t\t\" Set the forwarding cores hexadecimal mask.\\n\\n\"\n\n\t\t\t\"set portmask (mask)\\n\"\n\t\t\t\" Set the forwarding ports hexadecimal mask.\\n\\n\"\n\n\t\t\t\"set burst (num)\\n\"\n\t\t\t\" Set number of packets per burst.\\n\\n\"\n\n\t\t\t\"set burst tx delay (microseconds) retry (num)\\n\"\n\t\t\t\" Set the transmit delay time and number of retries\"\n\t\t\t\" in mac_retry forwarding mode.\\n\\n\"\n\n\t\t\t\"set txpkts (x[,y]*)\\n\"\n\t\t\t\" Set the length of each segment of TXONLY\"\n\t\t\t\" packets.\\n\\n\"\n\n\t\t\t\"set corelist (x[,y]*)\\n\"\n\t\t\t\" Set the list of forwarding cores.\\n\\n\"\n\n\t\t\t\"set portlist (x[,y]*)\\n\"\n\t\t\t\" Set the list of forwarding ports.\\n\\n\"\n\n\t\t\t\"vlan set strip (on|off) (port_id)\\n\"\n\t\t\t\" Set the VLAN strip on a port.\\n\\n\"\n\n\t\t\t\"vlan set stripq (on|off) (port_id,queue_id)\\n\"\n\t\t\t\" Set the VLAN strip for a queue on a port.\\n\\n\"\n\n\t\t\t\"vlan set filter (on|off) (port_id)\\n\"\n\t\t\t\" Set the VLAN filter on a port.\\n\\n\"\n\n\t\t\t\"vlan set qinq (on|off) (port_id)\\n\"\n\t\t\t\" Set the VLAN QinQ (extended queue in queue)\"\n\t\t\t\" on a port.\\n\\n\"\n\n\t\t\t\"vlan set tpid (value) (port_id)\\n\"\n\t\t\t\" Set the outer VLAN TPID for Packet Filtering on\"\n\t\t\t\" a port\\n\\n\"\n\n\t\t\t\"rx_vlan add (vlan_id|all) (port_id)\\n\"\n\t\t\t\" Add a vlan_id, or all identifiers, to the set\"\n\t\t\t\" of VLAN identifiers filtered by port_id.\\n\\n\"\n\n\t\t\t\"rx_vlan rm (vlan_id|all) (port_id)\\n\"\n\t\t\t\" Remove a vlan_id, or all identifiers, from the set\"\n\t\t\t\" of VLAN identifiers filtered by port_id.\\n\\n\"\n\n\t\t\t\"rx_vlan add (vlan_id) port (port_id) vf (vf_mask)\\n\"\n\t\t\t\" Add a vlan_id, to the set of VLAN identifiers\"\n\t\t\t\"filtered for VF(s) from port_id.\\n\\n\"\n\n\t\t\t\"rx_vlan rm (vlan_id) port (port_id) vf (vf_mask)\\n\"\n\t\t\t\" Remove a vlan_id, to the set of VLAN identifiers\"\n\t\t\t\"filtered for VF(s) from port_id.\\n\\n\"\n\n\t\t\t\"rx_vlan set tpid (value) (port_id)\\n\"\n\t\t\t\" Set the outer VLAN TPID for Packet Filtering on\"\n\t\t\t\" a port\\n\\n\"\n\n\t\t\t\"tunnel_filter add (port_id) (outer_mac) (inner_mac) (ip_addr) \"\n\t\t\t\"(inner_vlan) (vxlan|nvgre) (filter_type) (tenant_id) (queue_id)\\n\"\n\t\t\t\" add a tunnel filter of a port.\\n\\n\"\n\n\t\t\t\"tunnel_filter rm (port_id) (outer_mac) (inner_mac) (ip_addr) \"\n\t\t\t\"(inner_vlan) (vxlan|nvgre) (filter_type) (tenant_id) (queue_id)\\n\"\n\t\t\t\" remove a tunnel filter of a port.\\n\\n\"\n\n\t\t\t\"rx_vxlan_port add (udp_port) (port_id)\\n\"\n\t\t\t\" Add an UDP port for VXLAN packet filter on a port\\n\\n\"\n\n\t\t\t\"rx_vxlan_port rm (udp_port) (port_id)\\n\"\n\t\t\t\" Remove an UDP port for VXLAN packet filter on a port\\n\\n\"\n\n\t\t\t\"tx_vlan set (port_id) vlan_id[, vlan_id_outer]\\n\"\n\t\t\t\" Set hardware insertion of VLAN IDs (single or double VLAN \"\n\t\t\t\"depends on the number of VLAN IDs) in packets sent on a port.\\n\\n\"\n\n\t\t\t\"tx_vlan set pvid port_id vlan_id (on|off)\\n\"\n\t\t\t\" Set port based TX VLAN insertion.\\n\\n\"\n\n\t\t\t\"tx_vlan reset (port_id)\\n\"\n\t\t\t\" Disable hardware insertion of a VLAN header in\"\n\t\t\t\" packets sent on a port.\\n\\n\"\n\n\t\t\t\"csum set (ip|udp|tcp|sctp|outer-ip) (hw|sw) (port_id)\\n\"\n\t\t\t\" Select hardware or software calculation of the\"\n\t\t\t\" checksum when transmitting a packet using the\"\n\t\t\t\" csum forward engine.\\n\"\n\t\t\t\" ip|udp|tcp|sctp always concern the inner layer.\\n\"\n\t\t\t\" outer-ip concerns the outer IP layer in\"\n\t\t\t\" case the packet is recognized as a tunnel packet by\"\n\t\t\t\" the forward engine (vxlan, gre and ipip are supported)\\n\"\n\t\t\t\" Please check the NIC datasheet for HW limits.\\n\\n\"\n\n\t\t\t\"csum parse-tunnel (on|off) (tx_port_id)\\n\"\n\t\t\t\" If disabled, treat tunnel packets as non-tunneled\"\n\t\t\t\" packets (treat inner headers as payload). The port\\n\"\n\t\t\t\" argument is the port used for TX in csum forward\"\n\t\t\t\" engine.\\n\\n\"\n\n\t\t\t\"csum show (port_id)\\n\"\n\t\t\t\" Display tx checksum offload configuration\\n\\n\"\n\n\t\t\t\"tso set (segsize) (portid)\\n\"\n\t\t\t\" Enable TCP Segmentation Offload in csum forward\"\n\t\t\t\" engine.\\n\"\n\t\t\t\" Please check the NIC datasheet for HW limits.\\n\\n\"\n\n\t\t\t\"tso show (portid)\"\n\t\t\t\" Display the status of TCP Segmentation Offload.\\n\\n\"\n\n\t\t\t\"set fwd (%s)\\n\"\n\t\t\t\" Set packet forwarding mode.\\n\\n\"\n\n\t\t\t\"mac_addr add (port_id) (XX:XX:XX:XX:XX:XX)\\n\"\n\t\t\t\" Add a MAC address on port_id.\\n\\n\"\n\n\t\t\t\"mac_addr remove (port_id) (XX:XX:XX:XX:XX:XX)\\n\"\n\t\t\t\" Remove a MAC address from port_id.\\n\\n\"\n\n\t\t\t\"mac_addr add port (port_id) vf (vf_id) (mac_address)\\n\"\n\t\t\t\" Add a MAC address for a VF on the port.\\n\\n\"\n\n\t\t\t\"set port (port_id) uta (mac_address|all) (on|off)\\n\"\n\t\t\t\" Add/Remove a or all unicast hash filter(s)\"\n\t\t\t\"from port X.\\n\\n\"\n\n\t\t\t\"set promisc (port_id|all) (on|off)\\n\"\n\t\t\t\" Set the promiscuous mode on port_id, or all.\\n\\n\"\n\n\t\t\t\"set allmulti (port_id|all) (on|off)\\n\"\n\t\t\t\" Set the allmulti mode on port_id, or all.\\n\\n\"\n\n\t\t\t\"set flow_ctrl rx (on|off) tx (on|off) (high_water)\"\n\t\t\t\" (low_water) (pause_time) (send_xon) mac_ctrl_frame_fwd\"\n\t\t\t\" (on|off) autoneg (on|off) (port_id)\\n\"\n\t\t\t\"set flow_ctrl rx (on|off) (portid)\\n\"\n\t\t\t\"set flow_ctrl tx (on|off) (portid)\\n\"\n\t\t\t\"set flow_ctrl high_water (high_water) (portid)\\n\"\n\t\t\t\"set flow_ctrl low_water (low_water) (portid)\\n\"\n\t\t\t\"set flow_ctrl pause_time (pause_time) (portid)\\n\"\n\t\t\t\"set flow_ctrl send_xon (send_xon) (portid)\\n\"\n\t\t\t\"set flow_ctrl mac_ctrl_frame_fwd (on|off) (portid)\\n\"\n\t\t\t\"set flow_ctrl autoneg (on|off) (port_id)\\n\"\n\t\t\t\" Set the link flow control parameter on a port.\\n\\n\"\n\n\t\t\t\"set pfc_ctrl rx (on|off) tx (on|off) (high_water)\"\n\t\t\t\" (low_water) (pause_time) (priority) (port_id)\\n\"\n\t\t\t\" Set the priority flow control parameter on a\"\n\t\t\t\" port.\\n\\n\"\n\n\t\t\t\"set stat_qmap (tx|rx) (port_id) (queue_id) (qmapping)\\n\"\n\t\t\t\" Set statistics mapping (qmapping 0..15) for RX/TX\"\n\t\t\t\" queue on port.\\n\"\n\t\t\t\" e.g., 'set stat_qmap rx 0 2 5' sets rx queue 2\"\n\t\t\t\" on port 0 to mapping 5.\\n\\n\"\n\n\t\t\t\"set port (port_id) vf (vf_id) rx|tx on|off\\n\"\n\t\t\t\" Enable/Disable a VF receive/tranmit from a port\\n\\n\"\n\n\t\t\t\"set port (port_id) vf (vf_id) (mac_addr)\"\n\t\t\t\" (exact-mac#exact-mac-vlan#hashmac|hashmac-vlan) on|off\\n\"\n\t\t\t\" Add/Remove unicast or multicast MAC addr filter\"\n\t\t\t\" for a VF.\\n\\n\"\n\n\t\t\t\"set port (port_id) vf (vf_id) rxmode (AUPE|ROPE|BAM\"\n\t\t\t\"|MPE) (on|off)\\n\"\n\t\t\t\" AUPE:accepts untagged VLAN;\"\n\t\t\t\"ROPE:accept unicast hash\\n\\n\"\n\t\t\t\" BAM:accepts broadcast packets;\"\n\t\t\t\"MPE:accepts all multicast packets\\n\\n\"\n\t\t\t\" Enable/Disable a VF receive mode of a port\\n\\n\"\n\n\t\t\t\"set port (port_id) queue (queue_id) rate (rate_num)\\n\"\n\t\t\t\" Set rate limit for a queue of a port\\n\\n\"\n\n\t\t\t\"set port (port_id) vf (vf_id) rate (rate_num) \"\n\t\t\t\"queue_mask (queue_mask_value)\\n\"\n\t\t\t\" Set rate limit for queues in VF of a port\\n\\n\"\n\n\t\t\t\"set port (port_id) mirror-rule (rule_id)\"\n\t\t\t\" (pool-mirror-up|pool-mirror-down|vlan-mirror)\"\n\t\t\t\" (poolmask|vlanid[,vlanid]*) dst-pool (pool_id) (on|off)\\n\"\n\t\t\t\" Set pool or vlan type mirror rule on a port.\\n\"\n\t\t\t\" e.g., 'set port 0 mirror-rule 0 vlan-mirror 0,1\"\n\t\t\t\" dst-pool 0 on' enable mirror traffic with vlan 0,1\"\n\t\t\t\" to pool 0.\\n\\n\"\n\n\t\t\t\"set port (port_id) mirror-rule (rule_id)\"\n\t\t\t\" (uplink-mirror|downlink-mirror) dst-pool\"\n\t\t\t\" (pool_id) (on|off)\\n\"\n\t\t\t\" Set uplink or downlink type mirror rule on a port.\\n\"\n\t\t\t\" e.g., 'set port 0 mirror-rule 0 uplink-mirror dst-pool\"\n\t\t\t\" 0 on' enable mirror income traffic to pool 0.\\n\\n\"\n\n\t\t\t\"reset port (port_id) mirror-rule (rule_id)\\n\"\n\t\t\t\" Reset a mirror rule.\\n\\n\"\n\n\t\t\t\"set flush_rx (on|off)\\n\"\n\t\t\t\" Flush (default) or don't flush RX streams before\"\n\t\t\t\" forwarding. Mainly used with PCAP drivers.\\n\\n\"\n\n\t\t\t#ifdef RTE_NIC_BYPASS\n\t\t\t\"set bypass mode (normal|bypass|isolate) (port_id)\\n\"\n\t\t\t\" Set the bypass mode for the lowest port on bypass enabled\"\n\t\t\t\" NIC.\\n\\n\"\n\n\t\t\t\"set bypass event (timeout|os_on|os_off|power_on|power_off) \"\n\t\t\t\"mode (normal|bypass|isolate) (port_id)\\n\"\n\t\t\t\" Set the event required to initiate specified bypass mode for\"\n\t\t\t\" the lowest port on a bypass enabled NIC where:\\n\"\n\t\t\t\" timeout = enable bypass after watchdog timeout.\\n\"\n\t\t\t\" os_on = enable bypass when OS/board is powered on.\\n\"\n\t\t\t\" os_off = enable bypass when OS/board is powered off.\\n\"\n\t\t\t\" power_on = enable bypass when power supply is turned on.\\n\"\n\t\t\t\" power_off = enable bypass when power supply is turned off.\"\n\t\t\t\"\\n\\n\"\n\n\t\t\t\"set bypass timeout (0|1.5|2|3|4|8|16|32)\\n\"\n\t\t\t\" Set the bypass watchdog timeout to 'n' seconds\"\n\t\t\t\" where 0 = instant.\\n\\n\"\n\n\t\t\t\"show bypass config (port_id)\\n\"\n\t\t\t\" Show the bypass configuration for a bypass enabled NIC\"\n\t\t\t\" using the lowest port on the NIC.\\n\\n\"\n#endif\n#ifdef RTE_LIBRTE_PMD_BOND\n\t\t\t\"create bonded device (mode) (socket)\\n\"\n\t\t\t\"\tCreate a new bonded device with specific bonding mode and socket.\\n\\n\"\n\n\t\t\t\"add bonding slave (slave_id) (port_id)\\n\"\n\t\t\t\"\tAdd a slave device to a bonded device.\\n\\n\"\n\n\t\t\t\"remove bonding slave (slave_id) (port_id)\\n\"\n\t\t\t\"\tRemove a slave device from a bonded device.\\n\\n\"\n\n\t\t\t\"set bonding mode (value) (port_id)\\n\"\n\t\t\t\"\tSet the bonding mode on a bonded device.\\n\\n\"\n\n\t\t\t\"set bonding primary (slave_id) (port_id)\\n\"\n\t\t\t\"\tSet the primary slave for a bonded device.\\n\\n\"\n\n\t\t\t\"show bonding config (port_id)\\n\"\n\t\t\t\"\tShow the bonding config for port_id.\\n\\n\"\n\n\t\t\t\"set bonding mac_addr (port_id) (address)\\n\"\n\t\t\t\"\tSet the MAC address of a bonded device.\\n\\n\"\n\n\t\t\t\"set bonding xmit_balance_policy (port_id) (l2|l23|l34)\\n\"\n\t\t\t\"\tSet the transmit balance policy for bonded device running in balance mode.\\n\\n\"\n\n\t\t\t\"set bonding mon_period (port_id) (value)\\n\"\n\t\t\t\"\tSet the bonding link status monitoring polling period in ms.\\n\\n\"\n#endif\n\t\t\t\"set link-up port (port_id)\\n\"\n\t\t\t\"\tSet link up for a port.\\n\\n\"\n\n\t\t\t\"set link-down port (port_id)\\n\"\n\t\t\t\"\tSet link down for a port.\\n\\n\"\n\n\t\t\t, list_pkt_forwarding_modes()\n\t\t);\n\t}\n\n\tif (show_all || !strcmp(res->section, \"ports\")) {\n\n\t\tcmdline_printf(\n\t\t\tcl,\n\t\t\t\"\\n\"\n\t\t\t\"Port Operations:\\n\"\n\t\t\t\"----------------\\n\\n\"\n\n\t\t\t\"port start (port_id|all)\\n\"\n\t\t\t\" Start all ports or port_id.\\n\\n\"\n\n\t\t\t\"port stop (port_id|all)\\n\"\n\t\t\t\" Stop all ports or port_id.\\n\\n\"\n\n\t\t\t\"port close (port_id|all)\\n\"\n\t\t\t\" Close all ports or port_id.\\n\\n\"\n\n\t\t\t\"port attach (ident)\\n\"\n\t\t\t\" Attach physical or virtual dev by pci address or virtual device name\\n\\n\"\n\n\t\t\t\"port detach (port_id)\\n\"\n\t\t\t\" Detach physical or virtual dev by port_id\\n\\n\"\n\n\t\t\t\"port config (port_id|all)\"\n\t\t\t\" speed (10|100|1000|10000|40000|auto)\"\n\t\t\t\" duplex (half|full|auto)\\n\"\n\t\t\t\" Set speed and duplex for all ports or port_id\\n\\n\"\n\n\t\t\t\"port config all (rxq|txq|rxd|txd) (value)\\n\"\n\t\t\t\" Set number for rxq/txq/rxd/txd.\\n\\n\"\n\n\t\t\t\"port config all max-pkt-len (value)\\n\"\n\t\t\t\" Set the max packet length.\\n\\n\"\n\n\t\t\t\"port config all (crc-strip|rx-cksum|hw-vlan|hw-vlan-filter|\"\n\t\t\t\"hw-vlan-strip|hw-vlan-extend|drop-en)\"\n\t\t\t\" (on|off)\\n\"\n\t\t\t\" Set crc-strip/rx-checksum/hardware-vlan/drop_en\"\n\t\t\t\" for ports.\\n\\n\"\n\n\t\t\t\"port config all rss (all|ip|tcp|udp|sctp|ether|none)\\n\"\n\t\t\t\" Set the RSS mode.\\n\\n\"\n\n\t\t\t\"port config port-id rss reta (hash,queue)[,(hash,queue)]\\n\"\n\t\t\t\" Set the RSS redirection table.\\n\\n\"\n\n\t\t\t\"port config (port_id) dcb vt (on|off) (traffic_class)\"\n\t\t\t\" pfc (on|off)\\n\"\n\t\t\t\" Set the DCB mode.\\n\\n\"\n\n\t\t\t\"port config all burst (value)\\n\"\n\t\t\t\" Set the number of packets per burst.\\n\\n\"\n\n\t\t\t\"port config all (txpt|txht|txwt|rxpt|rxht|rxwt)\"\n\t\t\t\" (value)\\n\"\n\t\t\t\" Set the ring prefetch/host/writeback threshold\"\n\t\t\t\" for tx/rx queue.\\n\\n\"\n\n\t\t\t\"port config all (txfreet|txrst|rxfreet) (value)\\n\"\n\t\t\t\" Set free threshold for rx/tx, or set\"\n\t\t\t\" tx rs bit threshold.\\n\\n\"\n\t\t\t\"port config mtu X value\\n\"\n\t\t\t\" Set the MTU of port X to a given value\\n\\n\"\n\n\t\t\t\"port (port_id) (rxq|txq) (queue_id) (start|stop)\\n\"\n\t\t\t\" Start/stop a rx/tx queue of port X. Only take effect\"\n\t\t\t\" when port X is started\\n\"\n\t\t);\n\t}\n\n\tif (show_all || !strcmp(res->section, \"registers\")) {\n\n\t\tcmdline_printf(\n\t\t\tcl,\n\t\t\t\"\\n\"\n\t\t\t\"Registers:\\n\"\n\t\t\t\"----------\\n\\n\"\n\n\t\t\t\"read reg (port_id) (address)\\n\"\n\t\t\t\" Display value of a port register.\\n\\n\"\n\n\t\t\t\"read regfield (port_id) (address) (bit_x) (bit_y)\\n\"\n\t\t\t\" Display a port register bit field.\\n\\n\"\n\n\t\t\t\"read regbit (port_id) (address) (bit_x)\\n\"\n\t\t\t\" Display a single port register bit.\\n\\n\"\n\n\t\t\t\"write reg (port_id) (address) (value)\\n\"\n\t\t\t\" Set value of a port register.\\n\\n\"\n\n\t\t\t\"write regfield (port_id) (address) (bit_x) (bit_y)\"\n\t\t\t\" (value)\\n\"\n\t\t\t\" Set bit field of a port register.\\n\\n\"\n\n\t\t\t\"write regbit (port_id) (address) (bit_x) (value)\\n\"\n\t\t\t\" Set single bit value of a port register.\\n\\n\"\n\t\t);\n\t}\n\tif (show_all || !strcmp(res->section, \"filters\")) {\n\n\t\tcmdline_printf(\n\t\t\tcl,\n\t\t\t\"\\n\"\n\t\t\t\"filters:\\n\"\n\t\t\t\"--------\\n\\n\"\n\n\t\t\t\"ethertype_filter (port_id) (add|del)\"\n\t\t\t\" (mac_addr|mac_ignr) (mac_address) ethertype\"\n\t\t\t\" (ether_type) (drop|fwd) queue (queue_id)\\n\"\n\t\t\t\" Add/Del an ethertype filter.\\n\\n\"\n\n\t\t\t\"2tuple_filter (port_id) (add|del)\"\n\t\t\t\" dst_port (dst_port_value) protocol (protocol_value)\"\n\t\t\t\" mask (mask_value) tcp_flags (tcp_flags_value)\"\n\t\t\t\" priority (prio_value) queue (queue_id)\\n\"\n\t\t\t\" Add/Del a 2tuple filter.\\n\\n\"\n\n\t\t\t\"5tuple_filter (port_id) (add|del)\"\n\t\t\t\" dst_ip (dst_address) src_ip (src_address)\"\n\t\t\t\" dst_port (dst_port_value) src_port (src_port_value)\"\n\t\t\t\" protocol (protocol_value)\"\n\t\t\t\" mask (mask_value) tcp_flags (tcp_flags_value)\"\n\t\t\t\" priority (prio_value) queue (queue_id)\\n\"\n\t\t\t\" Add/Del a 5tuple filter.\\n\\n\"\n\n\t\t\t\"syn_filter (port_id) (add|del) priority (high|low) queue (queue_id)\"\n\t\t\t\" Add/Del syn filter.\\n\\n\"\n\n\t\t\t\"flex_filter (port_id) (add|del) len (len_value)\"\n\t\t\t\" bytes (bytes_value) mask (mask_value)\"\n\t\t\t\" priority (prio_value) queue (queue_id)\\n\"\n\t\t\t\" Add/Del a flex filter.\\n\\n\"\n\n\t\t\t\"flow_director_filter (port_id) (add|del|update)\"\n\t\t\t\" flow (ipv4-other|ipv4-frag|ipv6-other|ipv6-frag)\"\n\t\t\t\" src (src_ip_address) dst (dst_ip_address)\"\n\t\t\t\" vlan (vlan_value) flexbytes (flexbytes_value)\"\n\t\t\t\" (drop|fwd) queue (queue_id) fd_id (fd_id_value)\\n\"\n\t\t\t\" Add/Del an IP type flow director filter.\\n\\n\"\n\n\t\t\t\"flow_director_filter (port_id) (add|del|update)\"\n\t\t\t\" flow (ipv4-tcp|ipv4-udp|ipv6-tcp|ipv6-udp)\"\n\t\t\t\" src (src_ip_address) (src_port)\"\n\t\t\t\" dst (dst_ip_address) (dst_port)\"\n\t\t\t\" vlan (vlan_value) flexbytes (flexbytes_value)\"\n\t\t\t\" (drop|fwd) queue (queue_id) fd_id (fd_id_value)\\n\"\n\t\t\t\" Add/Del an UDP/TCP type flow director filter.\\n\\n\"\n\n\t\t\t\"flow_director_filter (port_id) (add|del|update)\"\n\t\t\t\" flow (ipv4-sctp|ipv6-sctp)\"\n\t\t\t\" src (src_ip_address) (src_port)\"\n\t\t\t\" dst (dst_ip_address) (dst_port)\"\n\t\t\t\" tag (verification_tag) vlan (vlan_value)\"\n\t\t\t\" flexbytes (flexbytes_value) (drop|fwd)\"\n\t\t\t\" queue (queue_id) fd_id (fd_id_value)\\n\"\n\t\t\t\" Add/Del a SCTP type flow director filter.\\n\\n\"\n\n\t\t\t\"flow_director_filter (port_id) (add|del|update)\"\n\t\t\t\" flow l2_payload ether (ethertype)\"\n\t\t\t\" flexbytes (flexbytes_value) (drop|fwd)\"\n\t\t\t\" queue (queue_id) fd_id (fd_id_value)\\n\"\n\t\t\t\" Add/Del a l2 payload type flow director filter.\\n\\n\"\n\n\t\t\t\"flush_flow_director (port_id)\\n\"\n\t\t\t\" Flush all flow director entries of a device.\\n\\n\"\n\n\t\t\t\"flow_director_mask (port_id) vlan (vlan_value)\"\n\t\t\t\" src_mask (ipv4_src) (ipv6_src) (src_port)\"\n\t\t\t\" dst_mask (ipv4_dst) (ipv6_dst) (dst_port)\\n\"\n\t\t\t\" Set flow director mask.\\n\\n\"\n\n\t\t\t\"flow_director_flex_mask (port_id)\"\n\t\t\t\" flow (none|ipv4-other|ipv4-frag|ipv4-tcp|ipv4-udp|ipv4-sctp|\"\n\t\t\t\"ipv6-other|ipv6-frag|ipv6-tcp|ipv6-udp|ipv6-sctp|l2_payload|all)\"\n\t\t\t\" (mask)\\n\"\n\t\t\t\" Configure mask of flex payload.\\n\\n\"\n\n\t\t\t\"flow_director_flex_payload (port_id)\"\n\t\t\t\" (raw|l2|l3|l4) (config)\\n\"\n\t\t\t\" Configure flex payload selection.\\n\\n\"\n\n\t\t\t\"get_sym_hash_ena_per_port (port_id)\\n\"\n\t\t\t\" get symmetric hash enable configuration per port.\\n\\n\"\n\n\t\t\t\"set_sym_hash_ena_per_port (port_id) (enable|disable)\\n\"\n\t\t\t\" set symmetric hash enable configuration per port\"\n\t\t\t\" to enable or disable.\\n\\n\"\n\n\t\t\t\"get_hash_global_config (port_id)\\n\"\n\t\t\t\" Get the global configurations of hash filters.\\n\\n\"\n\n\t\t\t\"set_hash_global_config (port_id) (toeplitz|simple_xor|default)\"\n\t\t\t\" (ipv4|ipv4-frag|ipv4-tcp|ipv4-udp|ipv4-sctp|ipv4-other|ipv6|\"\n\t\t\t\"ipv6-frag|ipv6-tcp|ipv6-udp|ipv6-sctp|ipv6-other|l2_payload)\"\n\t\t\t\" (enable|disable)\\n\"\n\t\t\t\" Set the global configurations of hash filters.\\n\\n\"\n\t\t);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_help_long_help =\n\tTOKEN_STRING_INITIALIZER(struct cmd_help_long_result, help, \"help\");\n\ncmdline_parse_token_string_t cmd_help_long_section =\n\tTOKEN_STRING_INITIALIZER(struct cmd_help_long_result, section,\n\t\t\t\"all#control#display#config#\"\n\t\t\t\"ports#registers#filters\");\n\ncmdline_parse_inst_t cmd_help_long = {\n\t.f = cmd_help_long_parsed,\n\t.data = NULL,\n\t.help_str = \"show help\",\n\t.tokens = {\n\t\t(void *)&cmd_help_long_help,\n\t\t(void *)&cmd_help_long_section,\n\t\tNULL,\n\t},\n};\n\n\n/* *** start/stop/close all ports *** */\nstruct cmd_operate_port_result {\n\tcmdline_fixed_string_t keyword;\n\tcmdline_fixed_string_t name;\n\tcmdline_fixed_string_t value;\n};\n\nstatic void cmd_operate_port_parsed(void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_operate_port_result *res = parsed_result;\n\n\tif (!strcmp(res->name, \"start\"))\n\t\tstart_port(RTE_PORT_ALL);\n\telse if (!strcmp(res->name, \"stop\"))\n\t\tstop_port(RTE_PORT_ALL);\n\telse if (!strcmp(res->name, \"close\"))\n\t\tclose_port(RTE_PORT_ALL);\n\telse\n\t\tprintf(\"Unknown parameter\\n\");\n}\n\ncmdline_parse_token_string_t cmd_operate_port_all_cmd =\n\tTOKEN_STRING_INITIALIZER(struct cmd_operate_port_result, keyword,\n\t\t\t\t\t\t\t\t\"port\");\ncmdline_parse_token_string_t cmd_operate_port_all_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_operate_port_result, name,\n\t\t\t\t\t\t\"start#stop#close\");\ncmdline_parse_token_string_t cmd_operate_port_all_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_operate_port_result, value, \"all\");\n\ncmdline_parse_inst_t cmd_operate_port = {\n\t.f = cmd_operate_port_parsed,\n\t.data = NULL,\n\t.help_str = \"port start|stop|close all: start/stop/close all ports\",\n\t.tokens = {\n\t\t(void *)&cmd_operate_port_all_cmd,\n\t\t(void *)&cmd_operate_port_all_port,\n\t\t(void *)&cmd_operate_port_all_all,\n\t\tNULL,\n\t},\n};\n\n/* *** start/stop/close specific port *** */\nstruct cmd_operate_specific_port_result {\n\tcmdline_fixed_string_t keyword;\n\tcmdline_fixed_string_t name;\n\tuint8_t value;\n};\n\nstatic void cmd_operate_specific_port_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_operate_specific_port_result *res = parsed_result;\n\n\tif (!strcmp(res->name, \"start\"))\n\t\tstart_port(res->value);\n\telse if (!strcmp(res->name, \"stop\"))\n\t\tstop_port(res->value);\n\telse if (!strcmp(res->name, \"close\"))\n\t\tclose_port(res->value);\n\telse\n\t\tprintf(\"Unknown parameter\\n\");\n}\n\ncmdline_parse_token_string_t cmd_operate_specific_port_cmd =\n\tTOKEN_STRING_INITIALIZER(struct cmd_operate_specific_port_result,\n\t\t\t\t\t\t\tkeyword, \"port\");\ncmdline_parse_token_string_t cmd_operate_specific_port_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_operate_specific_port_result,\n\t\t\t\t\t\tname, \"start#stop#close\");\ncmdline_parse_token_num_t cmd_operate_specific_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_operate_specific_port_result,\n\t\t\t\t\t\t\tvalue, UINT8);\n\ncmdline_parse_inst_t cmd_operate_specific_port = {\n\t.f = cmd_operate_specific_port_parsed,\n\t.data = NULL,\n\t.help_str = \"port start|stop|close X: start/stop/close port X\",\n\t.tokens = {\n\t\t(void *)&cmd_operate_specific_port_cmd,\n\t\t(void *)&cmd_operate_specific_port_port,\n\t\t(void *)&cmd_operate_specific_port_id,\n\t\tNULL,\n\t},\n};\n\n/* *** attach a specified port *** */\nstruct cmd_operate_attach_port_result {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tcmdline_fixed_string_t identifier;\n};\n\nstatic void cmd_operate_attach_port_parsed(void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_operate_attach_port_result *res = parsed_result;\n\n\tif (!strcmp(res->keyword, \"attach\"))\n\t\tattach_port(res->identifier);\n\telse\n\t\tprintf(\"Unknown parameter\\n\");\n}\n\ncmdline_parse_token_string_t cmd_operate_attach_port_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_operate_attach_port_result,\n\t\t\tport, \"port\");\ncmdline_parse_token_string_t cmd_operate_attach_port_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_operate_attach_port_result,\n\t\t\tkeyword, \"attach\");\ncmdline_parse_token_string_t cmd_operate_attach_port_identifier =\n\tTOKEN_STRING_INITIALIZER(struct cmd_operate_attach_port_result,\n\t\t\tidentifier, NULL);\n\ncmdline_parse_inst_t cmd_operate_attach_port = {\n\t.f = cmd_operate_attach_port_parsed,\n\t.data = NULL,\n\t.help_str = \"port attach identifier, \"\n\t\t\"identifier: pci address or virtual dev name\",\n\t.tokens = {\n\t\t(void *)&cmd_operate_attach_port_port,\n\t\t(void *)&cmd_operate_attach_port_keyword,\n\t\t(void *)&cmd_operate_attach_port_identifier,\n\t\tNULL,\n\t},\n};\n\n/* *** detach a specified port *** */\nstruct cmd_operate_detach_port_result {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tuint8_t port_id;\n};\n\nstatic void cmd_operate_detach_port_parsed(void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_operate_detach_port_result *res = parsed_result;\n\n\tif (!strcmp(res->keyword, \"detach\"))\n\t\tdetach_port(res->port_id);\n\telse\n\t\tprintf(\"Unknown parameter\\n\");\n}\n\ncmdline_parse_token_string_t cmd_operate_detach_port_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_operate_detach_port_result,\n\t\t\tport, \"port\");\ncmdline_parse_token_string_t cmd_operate_detach_port_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_operate_detach_port_result,\n\t\t\tkeyword, \"detach\");\ncmdline_parse_token_num_t cmd_operate_detach_port_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_operate_detach_port_result,\n\t\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_operate_detach_port = {\n\t.f = cmd_operate_detach_port_parsed,\n\t.data = NULL,\n\t.help_str = \"port detach port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_operate_detach_port_port,\n\t\t(void *)&cmd_operate_detach_port_keyword,\n\t\t(void *)&cmd_operate_detach_port_port_id,\n\t\tNULL,\n\t},\n};\n\n/* *** configure speed for all ports *** */\nstruct cmd_config_speed_all {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tcmdline_fixed_string_t all;\n\tcmdline_fixed_string_t item1;\n\tcmdline_fixed_string_t item2;\n\tcmdline_fixed_string_t value1;\n\tcmdline_fixed_string_t value2;\n};\n\nstatic void\ncmd_config_speed_all_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_config_speed_all *res = parsed_result;\n\tuint16_t link_speed = ETH_LINK_SPEED_AUTONEG;\n\tuint16_t link_duplex = 0;\n\tportid_t pid;\n\n\tif (!all_ports_stopped()) {\n\t\tprintf(\"Please stop all ports first\\n\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->value1, \"10\"))\n\t\tlink_speed = ETH_LINK_SPEED_10;\n\telse if (!strcmp(res->value1, \"100\"))\n\t\tlink_speed = ETH_LINK_SPEED_100;\n\telse if (!strcmp(res->value1, \"1000\"))\n\t\tlink_speed = ETH_LINK_SPEED_1000;\n\telse if (!strcmp(res->value1, \"10000\"))\n\t\tlink_speed = ETH_LINK_SPEED_10G;\n\telse if (!strcmp(res->value1, \"40000\"))\n\t\tlink_speed = ETH_LINK_SPEED_40G;\n\telse if (!strcmp(res->value1, \"auto\"))\n\t\tlink_speed = ETH_LINK_SPEED_AUTONEG;\n\telse {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->value2, \"half\"))\n\t\tlink_duplex = ETH_LINK_HALF_DUPLEX;\n\telse if (!strcmp(res->value2, \"full\"))\n\t\tlink_duplex = ETH_LINK_FULL_DUPLEX;\n\telse if (!strcmp(res->value2, \"auto\"))\n\t\tlink_duplex = ETH_LINK_AUTONEG_DUPLEX;\n\telse {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\n\tFOREACH_PORT(pid, ports) {\n\t\tports[pid].dev_conf.link_speed = link_speed;\n\t\tports[pid].dev_conf.link_duplex = link_duplex;\n\t}\n\n\tcmd_reconfig_device_queue(RTE_PORT_ALL, 1, 1);\n}\n\ncmdline_parse_token_string_t cmd_config_speed_all_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, port, \"port\");\ncmdline_parse_token_string_t cmd_config_speed_all_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, keyword,\n\t\t\t\t\t\t\t\"config\");\ncmdline_parse_token_string_t cmd_config_speed_all_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, all, \"all\");\ncmdline_parse_token_string_t cmd_config_speed_all_item1 =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, item1, \"speed\");\ncmdline_parse_token_string_t cmd_config_speed_all_value1 =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, value1,\n\t\t\t\t\t\t\"10#100#1000#10000#40000#auto\");\ncmdline_parse_token_string_t cmd_config_speed_all_item2 =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, item2, \"duplex\");\ncmdline_parse_token_string_t cmd_config_speed_all_value2 =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_all, value2,\n\t\t\t\t\t\t\"half#full#auto\");\n\ncmdline_parse_inst_t cmd_config_speed_all = {\n\t.f = cmd_config_speed_all_parsed,\n\t.data = NULL,\n\t.help_str = \"port config all speed 10|100|1000|10000|40000|auto duplex \"\n\t\t\t\t\t\t\t\"half|full|auto\",\n\t.tokens = {\n\t\t(void *)&cmd_config_speed_all_port,\n\t\t(void *)&cmd_config_speed_all_keyword,\n\t\t(void *)&cmd_config_speed_all_all,\n\t\t(void *)&cmd_config_speed_all_item1,\n\t\t(void *)&cmd_config_speed_all_value1,\n\t\t(void *)&cmd_config_speed_all_item2,\n\t\t(void *)&cmd_config_speed_all_value2,\n\t\tNULL,\n\t},\n};\n\n/* *** configure speed for specific port *** */\nstruct cmd_config_speed_specific {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tuint8_t id;\n\tcmdline_fixed_string_t item1;\n\tcmdline_fixed_string_t item2;\n\tcmdline_fixed_string_t value1;\n\tcmdline_fixed_string_t value2;\n};\n\nstatic void\ncmd_config_speed_specific_parsed(void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_config_speed_specific *res = parsed_result;\n\tuint16_t link_speed = ETH_LINK_SPEED_AUTONEG;\n\tuint16_t link_duplex = 0;\n\n\tif (!all_ports_stopped()) {\n\t\tprintf(\"Please stop all ports first\\n\");\n\t\treturn;\n\t}\n\n\tif (port_id_is_invalid(res->id, ENABLED_WARN))\n\t\treturn;\n\n\tif (!strcmp(res->value1, \"10\"))\n\t\tlink_speed = ETH_LINK_SPEED_10;\n\telse if (!strcmp(res->value1, \"100\"))\n\t\tlink_speed = ETH_LINK_SPEED_100;\n\telse if (!strcmp(res->value1, \"1000\"))\n\t\tlink_speed = ETH_LINK_SPEED_1000;\n\telse if (!strcmp(res->value1, \"10000\"))\n\t\tlink_speed = ETH_LINK_SPEED_10000;\n\telse if (!strcmp(res->value1, \"40000\"))\n\t\tlink_speed = ETH_LINK_SPEED_40G;\n\telse if (!strcmp(res->value1, \"auto\"))\n\t\tlink_speed = ETH_LINK_SPEED_AUTONEG;\n\telse {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->value2, \"half\"))\n\t\tlink_duplex = ETH_LINK_HALF_DUPLEX;\n\telse if (!strcmp(res->value2, \"full\"))\n\t\tlink_duplex = ETH_LINK_FULL_DUPLEX;\n\telse if (!strcmp(res->value2, \"auto\"))\n\t\tlink_duplex = ETH_LINK_AUTONEG_DUPLEX;\n\telse {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\n\tports[res->id].dev_conf.link_speed = link_speed;\n\tports[res->id].dev_conf.link_duplex = link_duplex;\n\n\tcmd_reconfig_device_queue(RTE_PORT_ALL, 1, 1);\n}\n\n\ncmdline_parse_token_string_t cmd_config_speed_specific_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, port,\n\t\t\t\t\t\t\t\t\"port\");\ncmdline_parse_token_string_t cmd_config_speed_specific_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, keyword,\n\t\t\t\t\t\t\t\t\"config\");\ncmdline_parse_token_num_t cmd_config_speed_specific_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_config_speed_specific, id, UINT8);\ncmdline_parse_token_string_t cmd_config_speed_specific_item1 =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, item1,\n\t\t\t\t\t\t\t\t\"speed\");\ncmdline_parse_token_string_t cmd_config_speed_specific_value1 =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, value1,\n\t\t\t\t\t\t\"10#100#1000#10000#40000#auto\");\ncmdline_parse_token_string_t cmd_config_speed_specific_item2 =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, item2,\n\t\t\t\t\t\t\t\t\"duplex\");\ncmdline_parse_token_string_t cmd_config_speed_specific_value2 =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_speed_specific, value2,\n\t\t\t\t\t\t\t\"half#full#auto\");\n\ncmdline_parse_inst_t cmd_config_speed_specific = {\n\t.f = cmd_config_speed_specific_parsed,\n\t.data = NULL,\n\t.help_str = \"port config X speed 10|100|1000|10000|40000|auto duplex \"\n\t\t\t\t\t\t\t\"half|full|auto\",\n\t.tokens = {\n\t\t(void *)&cmd_config_speed_specific_port,\n\t\t(void *)&cmd_config_speed_specific_keyword,\n\t\t(void *)&cmd_config_speed_specific_id,\n\t\t(void *)&cmd_config_speed_specific_item1,\n\t\t(void *)&cmd_config_speed_specific_value1,\n\t\t(void *)&cmd_config_speed_specific_item2,\n\t\t(void *)&cmd_config_speed_specific_value2,\n\t\tNULL,\n\t},\n};\n\n/* *** configure txq/rxq, txd/rxd *** */\nstruct cmd_config_rx_tx {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tcmdline_fixed_string_t all;\n\tcmdline_fixed_string_t name;\n\tuint16_t value;\n};\n\nstatic void\ncmd_config_rx_tx_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_config_rx_tx *res = parsed_result;\n\n\tif (!all_ports_stopped()) {\n\t\tprintf(\"Please stop all ports first\\n\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->name, \"rxq\")) {\n\t\tif (res->value <= 0) {\n\t\t\tprintf(\"rxq %d invalid - must be > 0\\n\", res->value);\n\t\t\treturn;\n\t\t}\n\t\tnb_rxq = res->value;\n\t}\n\telse if (!strcmp(res->name, \"txq\")) {\n\t\tif (res->value <= 0) {\n\t\t\tprintf(\"txq %d invalid - must be > 0\\n\", res->value);\n\t\t\treturn;\n\t\t}\n\t\tnb_txq = res->value;\n\t}\n\telse if (!strcmp(res->name, \"rxd\")) {\n\t\tif (res->value <= 0 || res->value > RTE_TEST_RX_DESC_MAX) {\n\t\t\tprintf(\"rxd %d invalid - must be > 0 && <= %d\\n\",\n\t\t\t\t\tres->value, RTE_TEST_RX_DESC_MAX);\n\t\t\treturn;\n\t\t}\n\t\tnb_rxd = res->value;\n\t} else if (!strcmp(res->name, \"txd\")) {\n\t\tif (res->value <= 0 || res->value > RTE_TEST_TX_DESC_MAX) {\n\t\t\tprintf(\"txd %d invalid - must be > 0 && <= %d\\n\",\n\t\t\t\t\tres->value, RTE_TEST_TX_DESC_MAX);\n\t\t\treturn;\n\t\t}\n\t\tnb_txd = res->value;\n\t} else {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\n\tinit_port_config();\n\n\tcmd_reconfig_device_queue(RTE_PORT_ALL, 1, 1);\n}\n\ncmdline_parse_token_string_t cmd_config_rx_tx_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rx_tx, port, \"port\");\ncmdline_parse_token_string_t cmd_config_rx_tx_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rx_tx, keyword, \"config\");\ncmdline_parse_token_string_t cmd_config_rx_tx_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rx_tx, all, \"all\");\ncmdline_parse_token_string_t cmd_config_rx_tx_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rx_tx, name,\n\t\t\t\t\t\t\"rxq#txq#rxd#txd\");\ncmdline_parse_token_num_t cmd_config_rx_tx_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_config_rx_tx, value, UINT16);\n\ncmdline_parse_inst_t cmd_config_rx_tx = {\n\t.f = cmd_config_rx_tx_parsed,\n\t.data = NULL,\n\t.help_str = \"port config all rxq|txq|rxd|txd value\",\n\t.tokens = {\n\t\t(void *)&cmd_config_rx_tx_port,\n\t\t(void *)&cmd_config_rx_tx_keyword,\n\t\t(void *)&cmd_config_rx_tx_all,\n\t\t(void *)&cmd_config_rx_tx_name,\n\t\t(void *)&cmd_config_rx_tx_value,\n\t\tNULL,\n\t},\n};\n\n/* *** config max packet length *** */\nstruct cmd_config_max_pkt_len_result {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tcmdline_fixed_string_t all;\n\tcmdline_fixed_string_t name;\n\tuint32_t value;\n};\n\nstatic void\ncmd_config_max_pkt_len_parsed(void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_config_max_pkt_len_result *res = parsed_result;\n\n\tif (!all_ports_stopped()) {\n\t\tprintf(\"Please stop all ports first\\n\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->name, \"max-pkt-len\")) {\n\t\tif (res->value < ETHER_MIN_LEN) {\n\t\t\tprintf(\"max-pkt-len can not be less than %d\\n\",\n\t\t\t\t\t\t\tETHER_MIN_LEN);\n\t\t\treturn;\n\t\t}\n\t\tif (res->value == rx_mode.max_rx_pkt_len)\n\t\t\treturn;\n\n\t\trx_mode.max_rx_pkt_len = res->value;\n\t\tif (res->value > ETHER_MAX_LEN)\n\t\t\trx_mode.jumbo_frame = 1;\n\t\telse\n\t\t\trx_mode.jumbo_frame = 0;\n\t} else {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\n\tinit_port_config();\n\n\tcmd_reconfig_device_queue(RTE_PORT_ALL, 1, 1);\n}\n\ncmdline_parse_token_string_t cmd_config_max_pkt_len_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_max_pkt_len_result, port,\n\t\t\t\t\t\t\t\t\"port\");\ncmdline_parse_token_string_t cmd_config_max_pkt_len_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_max_pkt_len_result, keyword,\n\t\t\t\t\t\t\t\t\"config\");\ncmdline_parse_token_string_t cmd_config_max_pkt_len_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_max_pkt_len_result, all,\n\t\t\t\t\t\t\t\t\"all\");\ncmdline_parse_token_string_t cmd_config_max_pkt_len_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_max_pkt_len_result, name,\n\t\t\t\t\t\t\t\t\"max-pkt-len\");\ncmdline_parse_token_num_t cmd_config_max_pkt_len_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_config_max_pkt_len_result, value,\n\t\t\t\t\t\t\t\tUINT32);\n\ncmdline_parse_inst_t cmd_config_max_pkt_len = {\n\t.f = cmd_config_max_pkt_len_parsed,\n\t.data = NULL,\n\t.help_str = \"port config all max-pkt-len value\",\n\t.tokens = {\n\t\t(void *)&cmd_config_max_pkt_len_port,\n\t\t(void *)&cmd_config_max_pkt_len_keyword,\n\t\t(void *)&cmd_config_max_pkt_len_all,\n\t\t(void *)&cmd_config_max_pkt_len_name,\n\t\t(void *)&cmd_config_max_pkt_len_value,\n\t\tNULL,\n\t},\n};\n\n/* *** configure port MTU *** */\nstruct cmd_config_mtu_result {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tcmdline_fixed_string_t mtu;\n\tuint8_t port_id;\n\tuint16_t value;\n};\n\nstatic void\ncmd_config_mtu_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_config_mtu_result *res = parsed_result;\n\n\tif (res->value < ETHER_MIN_LEN) {\n\t\tprintf(\"mtu cannot be less than %d\\n\", ETHER_MIN_LEN);\n\t\treturn;\n\t}\n\tport_mtu_set(res->port_id, res->value);\n}\n\ncmdline_parse_token_string_t cmd_config_mtu_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_mtu_result, port,\n\t\t\t\t \"port\");\ncmdline_parse_token_string_t cmd_config_mtu_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_mtu_result, keyword,\n\t\t\t\t \"config\");\ncmdline_parse_token_string_t cmd_config_mtu_mtu =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_mtu_result, keyword,\n\t\t\t\t \"mtu\");\ncmdline_parse_token_num_t cmd_config_mtu_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_config_mtu_result, port_id, UINT8);\ncmdline_parse_token_num_t cmd_config_mtu_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_config_mtu_result, value, UINT16);\n\ncmdline_parse_inst_t cmd_config_mtu = {\n\t.f = cmd_config_mtu_parsed,\n\t.data = NULL,\n\t.help_str = \"port config mtu value\",\n\t.tokens = {\n\t\t(void *)&cmd_config_mtu_port,\n\t\t(void *)&cmd_config_mtu_keyword,\n\t\t(void *)&cmd_config_mtu_mtu,\n\t\t(void *)&cmd_config_mtu_port_id,\n\t\t(void *)&cmd_config_mtu_value,\n\t\tNULL,\n\t},\n};\n\n/* *** configure rx mode *** */\nstruct cmd_config_rx_mode_flag {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tcmdline_fixed_string_t all;\n\tcmdline_fixed_string_t name;\n\tcmdline_fixed_string_t value;\n};\n\nstatic void\ncmd_config_rx_mode_flag_parsed(void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_config_rx_mode_flag *res = parsed_result;\n\n\tif (!all_ports_stopped()) {\n\t\tprintf(\"Please stop all ports first\\n\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->name, \"crc-strip\")) {\n\t\tif (!strcmp(res->value, \"on\"))\n\t\t\trx_mode.hw_strip_crc = 1;\n\t\telse if (!strcmp(res->value, \"off\"))\n\t\t\trx_mode.hw_strip_crc = 0;\n\t\telse {\n\t\t\tprintf(\"Unknown parameter\\n\");\n\t\t\treturn;\n\t\t}\n\t} else if (!strcmp(res->name, \"rx-cksum\")) {\n\t\tif (!strcmp(res->value, \"on\"))\n\t\t\trx_mode.hw_ip_checksum = 1;\n\t\telse if (!strcmp(res->value, \"off\"))\n\t\t\trx_mode.hw_ip_checksum = 0;\n\t\telse {\n\t\t\tprintf(\"Unknown parameter\\n\");\n\t\t\treturn;\n\t\t}\n\t} else if (!strcmp(res->name, \"hw-vlan\")) {\n\t\tif (!strcmp(res->value, \"on\")) {\n\t\t\trx_mode.hw_vlan_filter = 1;\n\t\t\trx_mode.hw_vlan_strip = 1;\n\t\t}\n\t\telse if (!strcmp(res->value, \"off\")) {\n\t\t\trx_mode.hw_vlan_filter = 0;\n\t\t\trx_mode.hw_vlan_strip = 0;\n\t\t}\n\t\telse {\n\t\t\tprintf(\"Unknown parameter\\n\");\n\t\t\treturn;\n\t\t}\n\t} else if (!strcmp(res->name, \"hw-vlan-filter\")) {\n\t\tif (!strcmp(res->value, \"on\"))\n\t\t\trx_mode.hw_vlan_filter = 1;\n\t\telse if (!strcmp(res->value, \"off\"))\n\t\t\trx_mode.hw_vlan_filter = 0;\n\t\telse {\n\t\t\tprintf(\"Unknown parameter\\n\");\n\t\t\treturn;\n\t\t}\n\t} else if (!strcmp(res->name, \"hw-vlan-strip\")) {\n\t\tif (!strcmp(res->value, \"on\"))\n\t\t\trx_mode.hw_vlan_strip = 1;\n\t\telse if (!strcmp(res->value, \"off\"))\n\t\t\trx_mode.hw_vlan_strip = 0;\n\t\telse {\n\t\t\tprintf(\"Unknown parameter\\n\");\n\t\t\treturn;\n\t\t}\n\t} else if (!strcmp(res->name, \"hw-vlan-extend\")) {\n\t\tif (!strcmp(res->value, \"on\"))\n\t\t\trx_mode.hw_vlan_extend = 1;\n\t\telse if (!strcmp(res->value, \"off\"))\n\t\t\trx_mode.hw_vlan_extend = 0;\n\t\telse {\n\t\t\tprintf(\"Unknown parameter\\n\");\n\t\t\treturn;\n\t\t}\n\t} else if (!strcmp(res->name, \"drop-en\")) {\n\t\tif (!strcmp(res->value, \"on\"))\n\t\t\trx_drop_en = 1;\n\t\telse if (!strcmp(res->value, \"off\"))\n\t\t\trx_drop_en = 0;\n\t\telse {\n\t\t\tprintf(\"Unknown parameter\\n\");\n\t\t\treturn;\n\t\t}\n\t} else {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\n\tinit_port_config();\n\n\tcmd_reconfig_device_queue(RTE_PORT_ALL, 1, 1);\n}\n\ncmdline_parse_token_string_t cmd_config_rx_mode_flag_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rx_mode_flag, port, \"port\");\ncmdline_parse_token_string_t cmd_config_rx_mode_flag_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rx_mode_flag, keyword,\n\t\t\t\t\t\t\t\t\"config\");\ncmdline_parse_token_string_t cmd_config_rx_mode_flag_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rx_mode_flag, all, \"all\");\ncmdline_parse_token_string_t cmd_config_rx_mode_flag_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rx_mode_flag, name,\n\t\t\t\t\t\"crc-strip#rx-cksum#hw-vlan#\"\n\t\t\t\t\t\"hw-vlan-filter#hw-vlan-strip#hw-vlan-extend\");\ncmdline_parse_token_string_t cmd_config_rx_mode_flag_value =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rx_mode_flag, value,\n\t\t\t\t\t\t\t\"on#off\");\n\ncmdline_parse_inst_t cmd_config_rx_mode_flag = {\n\t.f = cmd_config_rx_mode_flag_parsed,\n\t.data = NULL,\n\t.help_str = \"port config all crc-strip|rx-cksum|hw-vlan|\"\n\t\t\"hw-vlan-filter|hw-vlan-strip|hw-vlan-extend on|off\",\n\t.tokens = {\n\t\t(void *)&cmd_config_rx_mode_flag_port,\n\t\t(void *)&cmd_config_rx_mode_flag_keyword,\n\t\t(void *)&cmd_config_rx_mode_flag_all,\n\t\t(void *)&cmd_config_rx_mode_flag_name,\n\t\t(void *)&cmd_config_rx_mode_flag_value,\n\t\tNULL,\n\t},\n};\n\n/* *** configure rss *** */\nstruct cmd_config_rss {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tcmdline_fixed_string_t all;\n\tcmdline_fixed_string_t name;\n\tcmdline_fixed_string_t value;\n};\n\nstatic void\ncmd_config_rss_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_config_rss *res = parsed_result;\n\tstruct rte_eth_rss_conf rss_conf;\n\tuint8_t i;\n\n\tif (!strcmp(res->value, \"all\"))\n\t\trss_conf.rss_hf = ETH_RSS_IP | ETH_RSS_TCP |\n\t\t\t\tETH_RSS_UDP | ETH_RSS_SCTP |\n\t\t\t\t\tETH_RSS_L2_PAYLOAD;\n\telse if (!strcmp(res->value, \"ip\"))\n\t\trss_conf.rss_hf = ETH_RSS_IP;\n\telse if (!strcmp(res->value, \"udp\"))\n\t\trss_conf.rss_hf = ETH_RSS_UDP;\n\telse if (!strcmp(res->value, \"tcp\"))\n\t\trss_conf.rss_hf = ETH_RSS_TCP;\n\telse if (!strcmp(res->value, \"sctp\"))\n\t\trss_conf.rss_hf = ETH_RSS_SCTP;\n\telse if (!strcmp(res->value, \"ether\"))\n\t\trss_conf.rss_hf = ETH_RSS_L2_PAYLOAD;\n\telse if (!strcmp(res->value, \"none\"))\n\t\trss_conf.rss_hf = 0;\n\telse {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\trss_conf.rss_key = NULL;\n\tfor (i = 0; i < rte_eth_dev_count(); i++)\n\t\trte_eth_dev_rss_hash_update(i, &rss_conf);\n}\n\ncmdline_parse_token_string_t cmd_config_rss_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss, port, \"port\");\ncmdline_parse_token_string_t cmd_config_rss_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss, keyword, \"config\");\ncmdline_parse_token_string_t cmd_config_rss_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss, all, \"all\");\ncmdline_parse_token_string_t cmd_config_rss_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss, name, \"rss\");\ncmdline_parse_token_string_t cmd_config_rss_value =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss, value,\n\t\t\"all#ip#tcp#udp#sctp#ether#none\");\n\ncmdline_parse_inst_t cmd_config_rss = {\n\t.f = cmd_config_rss_parsed,\n\t.data = NULL,\n\t.help_str = \"port config all rss all|ip|tcp|udp|sctp|ether|none\",\n\t.tokens = {\n\t\t(void *)&cmd_config_rss_port,\n\t\t(void *)&cmd_config_rss_keyword,\n\t\t(void *)&cmd_config_rss_all,\n\t\t(void *)&cmd_config_rss_name,\n\t\t(void *)&cmd_config_rss_value,\n\t\tNULL,\n\t},\n};\n\n/* *** configure rss hash key *** */\nstruct cmd_config_rss_hash_key {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t config;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t rss_hash_key;\n\tcmdline_fixed_string_t key;\n};\n\n#define RSS_HASH_KEY_LENGTH 40\nstatic uint8_t\nhexa_digit_to_value(char hexa_digit)\n{\n\tif ((hexa_digit >= '0') && (hexa_digit <= '9'))\n\t\treturn (uint8_t) (hexa_digit - '0');\n\tif ((hexa_digit >= 'a') && (hexa_digit <= 'f'))\n\t\treturn (uint8_t) ((hexa_digit - 'a') + 10);\n\tif ((hexa_digit >= 'A') && (hexa_digit <= 'F'))\n\t\treturn (uint8_t) ((hexa_digit - 'A') + 10);\n\t/* Invalid hexa digit */\n\treturn 0xFF;\n}\n\nstatic uint8_t\nparse_and_check_key_hexa_digit(char *key, int idx)\n{\n\tuint8_t hexa_v;\n\n\thexa_v = hexa_digit_to_value(key[idx]);\n\tif (hexa_v == 0xFF)\n\t\tprintf(\"invalid key: character %c at position %d is not a \"\n\t\t \"valid hexa digit\\n\", key[idx], idx);\n\treturn hexa_v;\n}\n\nstatic void\ncmd_config_rss_hash_key_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_config_rss_hash_key *res = parsed_result;\n\tuint8_t hash_key[RSS_HASH_KEY_LENGTH];\n\tuint8_t xdgt0;\n\tuint8_t xdgt1;\n\tint i;\n\n\t/* Check the length of the RSS hash key */\n\tif (strlen(res->key) != (RSS_HASH_KEY_LENGTH * 2)) {\n\t\tprintf(\"key length: %d invalid - key must be a string of %d\"\n\t\t \"hexa-decimal numbers\\n\", (int) strlen(res->key),\n\t\t RSS_HASH_KEY_LENGTH * 2);\n\t\treturn;\n\t}\n\t/* Translate RSS hash key into binary representation */\n\tfor (i = 0; i < RSS_HASH_KEY_LENGTH; i++) {\n\t\txdgt0 = parse_and_check_key_hexa_digit(res->key, (i * 2));\n\t\tif (xdgt0 == 0xFF)\n\t\t\treturn;\n\t\txdgt1 = parse_and_check_key_hexa_digit(res->key, (i * 2) + 1);\n\t\tif (xdgt1 == 0xFF)\n\t\t\treturn;\n\t\thash_key[i] = (uint8_t) ((xdgt0 * 16) + xdgt1);\n\t}\n\tport_rss_hash_key_update(res->port_id, hash_key);\n}\n\ncmdline_parse_token_string_t cmd_config_rss_hash_key_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss_hash_key, port, \"port\");\ncmdline_parse_token_string_t cmd_config_rss_hash_key_config =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss_hash_key, config,\n\t\t\t\t \"config\");\ncmdline_parse_token_num_t cmd_config_rss_hash_key_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_config_rss_hash_key, port_id, UINT8);\ncmdline_parse_token_string_t cmd_config_rss_hash_key_rss_hash_key =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss_hash_key,\n\t\t\t\t rss_hash_key, \"rss-hash-key\");\ncmdline_parse_token_string_t cmd_config_rss_hash_key_value =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss_hash_key, key, NULL);\n\ncmdline_parse_inst_t cmd_config_rss_hash_key = {\n\t.f = cmd_config_rss_hash_key_parsed,\n\t.data = NULL,\n\t.help_str = \"port config X rss-hash-key 80 hexa digits\",\n\t.tokens = {\n\t\t(void *)&cmd_config_rss_hash_key_port,\n\t\t(void *)&cmd_config_rss_hash_key_config,\n\t\t(void *)&cmd_config_rss_hash_key_port_id,\n\t\t(void *)&cmd_config_rss_hash_key_rss_hash_key,\n\t\t(void *)&cmd_config_rss_hash_key_value,\n\t\tNULL,\n\t},\n};\n\n/* *** configure port rxq/txq start/stop *** */\nstruct cmd_config_rxtx_queue {\n\tcmdline_fixed_string_t port;\n\tuint8_t portid;\n\tcmdline_fixed_string_t rxtxq;\n\tuint16_t qid;\n\tcmdline_fixed_string_t opname;\n};\n\nstatic void\ncmd_config_rxtx_queue_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_config_rxtx_queue *res = parsed_result;\n\tuint8_t isrx;\n\tuint8_t isstart;\n\tint ret = 0;\n\n\tif (test_done == 0) {\n\t\tprintf(\"Please stop forwarding first\\n\");\n\t\treturn;\n\t}\n\n\tif (port_id_is_invalid(res->portid, ENABLED_WARN))\n\t\treturn;\n\n\tif (port_is_started(res->portid) != 1) {\n\t\tprintf(\"Please start port %u first\\n\", res->portid);\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->rxtxq, \"rxq\"))\n\t\tisrx = 1;\n\telse if (!strcmp(res->rxtxq, \"txq\"))\n\t\tisrx = 0;\n\telse {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\n\tif (isrx && rx_queue_id_is_invalid(res->qid))\n\t\treturn;\n\telse if (!isrx && tx_queue_id_is_invalid(res->qid))\n\t\treturn;\n\n\tif (!strcmp(res->opname, \"start\"))\n\t\tisstart = 1;\n\telse if (!strcmp(res->opname, \"stop\"))\n\t\tisstart = 0;\n\telse {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\n\tif (isstart && isrx)\n\t\tret = rte_eth_dev_rx_queue_start(res->portid, res->qid);\n\telse if (!isstart && isrx)\n\t\tret = rte_eth_dev_rx_queue_stop(res->portid, res->qid);\n\telse if (isstart && !isrx)\n\t\tret = rte_eth_dev_tx_queue_start(res->portid, res->qid);\n\telse\n\t\tret = rte_eth_dev_tx_queue_stop(res->portid, res->qid);\n\n\tif (ret == -ENOTSUP)\n\t\tprintf(\"Function not supported in PMD driver\\n\");\n}\n\ncmdline_parse_token_string_t cmd_config_rxtx_queue_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rxtx_queue, port, \"port\");\ncmdline_parse_token_num_t cmd_config_rxtx_queue_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_config_rxtx_queue, portid, UINT8);\ncmdline_parse_token_string_t cmd_config_rxtx_queue_rxtxq =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rxtx_queue, rxtxq, \"rxq#txq\");\ncmdline_parse_token_num_t cmd_config_rxtx_queue_qid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_config_rxtx_queue, qid, UINT16);\ncmdline_parse_token_string_t cmd_config_rxtx_queue_opname =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rxtx_queue, opname,\n\t\t\t\t\t\t\"start#stop\");\n\ncmdline_parse_inst_t cmd_config_rxtx_queue = {\n\t.f = cmd_config_rxtx_queue_parsed,\n\t.data = NULL,\n\t.help_str = \"port X rxq|txq ID start|stop\",\n\t.tokens = {\n\t\t(void *)&cmd_config_speed_all_port,\n\t\t(void *)&cmd_config_rxtx_queue_portid,\n\t\t(void *)&cmd_config_rxtx_queue_rxtxq,\n\t\t(void *)&cmd_config_rxtx_queue_qid,\n\t\t(void *)&cmd_config_rxtx_queue_opname,\n\t\tNULL,\n\t},\n};\n\n/* *** Configure RSS RETA *** */\nstruct cmd_config_rss_reta {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t name;\n\tcmdline_fixed_string_t list_name;\n\tcmdline_fixed_string_t list_of_items;\n};\n\nstatic int\nparse_reta_config(const char *str,\n\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t uint16_t nb_entries)\n{\n\tint i;\n\tunsigned size;\n\tuint16_t hash_index, idx, shift;\n\tuint8_t nb_queue;\n\tchar s[256];\n\tconst char *p, *p0 = str;\n\tchar *end;\n\tenum fieldnames {\n\t\tFLD_HASH_INDEX = 0,\n\t\tFLD_QUEUE,\n\t\t_NUM_FLD\n\t};\n\tunsigned long int_fld[_NUM_FLD];\n\tchar *str_fld[_NUM_FLD];\n\n\twhile ((p = strchr(p0,'(')) != NULL) {\n\t\t++p;\n\t\tif((p0 = strchr(p,')')) == NULL)\n\t\t\treturn -1;\n\n\t\tsize = p0 - p;\n\t\tif(size >= sizeof(s))\n\t\t\treturn -1;\n\n\t\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\t\tif (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') != _NUM_FLD)\n\t\t\treturn -1;\n\t\tfor (i = 0; i < _NUM_FLD; i++) {\n\t\t\terrno = 0;\n\t\t\tint_fld[i] = strtoul(str_fld[i], &end, 0);\n\t\t\tif (errno != 0 || end == str_fld[i] ||\n\t\t\t\t\tint_fld[i] > 65535)\n\t\t\t\treturn -1;\n\t\t}\n\n\t\thash_index = (uint16_t)int_fld[FLD_HASH_INDEX];\n\t\tnb_queue = (uint8_t)int_fld[FLD_QUEUE];\n\n\t\tif (hash_index >= nb_entries) {\n\t\t\tprintf(\"Invalid RETA hash index=%d\\n\", hash_index);\n\t\t\treturn -1;\n\t\t}\n\n\t\tidx = hash_index / RTE_RETA_GROUP_SIZE;\n\t\tshift = hash_index % RTE_RETA_GROUP_SIZE;\n\t\treta_conf[idx].mask |= (1ULL << shift);\n\t\treta_conf[idx].reta[shift] = nb_queue;\n\t}\n\n\treturn 0;\n}\n\nstatic void\ncmd_set_rss_reta_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tint ret;\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_rss_reta_entry64 reta_conf[8];\n\tstruct cmd_config_rss_reta *res = parsed_result;\n\n\tmemset(&dev_info, 0, sizeof(dev_info));\n\trte_eth_dev_info_get(res->port_id, &dev_info);\n\tif (dev_info.reta_size == 0) {\n\t\tprintf(\"Redirection table size is 0 which is \"\n\t\t\t\t\t\"invalid for RSS\\n\");\n\t\treturn;\n\t} else\n\t\tprintf(\"The reta size of port %d is %u\\n\",\n\t\t\tres->port_id, dev_info.reta_size);\n\tif (dev_info.reta_size > ETH_RSS_RETA_SIZE_512) {\n\t\tprintf(\"Currently do not support more than %u entries of \"\n\t\t\t\"redirection table\\n\", ETH_RSS_RETA_SIZE_512);\n\t\treturn;\n\t}\n\n\tmemset(reta_conf, 0, sizeof(reta_conf));\n\tif (!strcmp(res->list_name, \"reta\")) {\n\t\tif (parse_reta_config(res->list_of_items, reta_conf,\n\t\t\t\t\t\tdev_info.reta_size)) {\n\t\t\tprintf(\"Invalid RSS Redirection Table \"\n\t\t\t\t\t\"config entered\\n\");\n\t\t\treturn;\n\t\t}\n\t\tret = rte_eth_dev_rss_reta_update(res->port_id,\n\t\t\t\treta_conf, dev_info.reta_size);\n\t\tif (ret != 0)\n\t\t\tprintf(\"Bad redirection table parameter, \"\n\t\t\t\t\t\"return code = %d \\n\", ret);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_config_rss_reta_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss_reta, port, \"port\");\ncmdline_parse_token_string_t cmd_config_rss_reta_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss_reta, keyword, \"config\");\ncmdline_parse_token_num_t cmd_config_rss_reta_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_config_rss_reta, port_id, UINT8);\ncmdline_parse_token_string_t cmd_config_rss_reta_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss_reta, name, \"rss\");\ncmdline_parse_token_string_t cmd_config_rss_reta_list_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_rss_reta, list_name, \"reta\");\ncmdline_parse_token_string_t cmd_config_rss_reta_list_of_items =\n TOKEN_STRING_INITIALIZER(struct cmd_config_rss_reta, list_of_items,\n NULL);\ncmdline_parse_inst_t cmd_config_rss_reta = {\n\t.f = cmd_set_rss_reta_parsed,\n\t.data = NULL,\n\t.help_str = \"port config X rss reta (hash,queue)[,(hash,queue)]\",\n\t.tokens = {\n\t\t(void *)&cmd_config_rss_reta_port,\n\t\t(void *)&cmd_config_rss_reta_keyword,\n\t\t(void *)&cmd_config_rss_reta_port_id,\n\t\t(void *)&cmd_config_rss_reta_name,\n\t\t(void *)&cmd_config_rss_reta_list_name,\n\t\t(void *)&cmd_config_rss_reta_list_of_items,\n\t\tNULL,\n\t},\n};\n\n/* *** SHOW PORT RETA INFO *** */\nstruct cmd_showport_reta {\n\tcmdline_fixed_string_t show;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t rss;\n\tcmdline_fixed_string_t reta;\n\tuint16_t size;\n\tcmdline_fixed_string_t list_of_items;\n};\n\nstatic int\nshowport_parse_reta_config(struct rte_eth_rss_reta_entry64 *conf,\n\t\t\t uint16_t nb_entries,\n\t\t\t char *str)\n{\n\tuint32_t size;\n\tconst char *p, *p0 = str;\n\tchar s[256];\n\tchar *end;\n\tchar *str_fld[8];\n\tuint16_t i, num = nb_entries / RTE_RETA_GROUP_SIZE;\n\tint ret;\n\n\tp = strchr(p0, '(');\n\tif (p == NULL)\n\t\treturn -1;\n\tp++;\n\tp0 = strchr(p, ')');\n\tif (p0 == NULL)\n\t\treturn -1;\n\tsize = p0 - p;\n\tif (size >= sizeof(s)) {\n\t\tprintf(\"The string size exceeds the internal buffer size\\n\");\n\t\treturn -1;\n\t}\n\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\tret = rte_strsplit(s, sizeof(s), str_fld, num, ',');\n\tif (ret <= 0 || ret != num) {\n\t\tprintf(\"The bits of masks do not match the number of \"\n\t\t\t\t\t\"reta entries: %u\\n\", num);\n\t\treturn -1;\n\t}\n\tfor (i = 0; i < ret; i++)\n\t\tconf[i].mask = (uint64_t)strtoul(str_fld[i], &end, 0);\n\n\treturn 0;\n}\n\nstatic void\ncmd_showport_reta_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_showport_reta *res = parsed_result;\n\tstruct rte_eth_rss_reta_entry64 reta_conf[8];\n\tstruct rte_eth_dev_info dev_info;\n\n\tmemset(&dev_info, 0, sizeof(dev_info));\n\trte_eth_dev_info_get(res->port_id, &dev_info);\n\tif (dev_info.reta_size == 0 || res->size != dev_info.reta_size ||\n\t\t\t\tres->size > ETH_RSS_RETA_SIZE_512) {\n\t\tprintf(\"Invalid redirection table size: %u\\n\", res->size);\n\t\treturn;\n\t}\n\n\tmemset(reta_conf, 0, sizeof(reta_conf));\n\tif (showport_parse_reta_config(reta_conf, res->size,\n\t\t\t\tres->list_of_items) < 0) {\n\t\tprintf(\"Invalid string: %s for reta masks\\n\",\n\t\t\t\t\tres->list_of_items);\n\t\treturn;\n\t}\n\tport_rss_reta_info(res->port_id, reta_conf, res->size);\n}\n\ncmdline_parse_token_string_t cmd_showport_reta_show =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showport_reta, show, \"show\");\ncmdline_parse_token_string_t cmd_showport_reta_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showport_reta, port, \"port\");\ncmdline_parse_token_num_t cmd_showport_reta_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_showport_reta, port_id, UINT8);\ncmdline_parse_token_string_t cmd_showport_reta_rss =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showport_reta, rss, \"rss\");\ncmdline_parse_token_string_t cmd_showport_reta_reta =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showport_reta, reta, \"reta\");\ncmdline_parse_token_num_t cmd_showport_reta_size =\n\tTOKEN_NUM_INITIALIZER(struct cmd_showport_reta, size, UINT16);\ncmdline_parse_token_string_t cmd_showport_reta_list_of_items =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showport_reta,\n\t\t\t\t\tlist_of_items, NULL);\n\ncmdline_parse_inst_t cmd_showport_reta = {\n\t.f = cmd_showport_reta_parsed,\n\t.data = NULL,\n\t.help_str = \"show port X rss reta (size) (mask0,mask1,...)\",\n\t.tokens = {\n\t\t(void *)&cmd_showport_reta_show,\n\t\t(void *)&cmd_showport_reta_port,\n\t\t(void *)&cmd_showport_reta_port_id,\n\t\t(void *)&cmd_showport_reta_rss,\n\t\t(void *)&cmd_showport_reta_reta,\n\t\t(void *)&cmd_showport_reta_size,\n\t\t(void *)&cmd_showport_reta_list_of_items,\n\t\tNULL,\n\t},\n};\n\n/* *** Show RSS hash configuration *** */\nstruct cmd_showport_rss_hash {\n\tcmdline_fixed_string_t show;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t rss_hash;\n\tcmdline_fixed_string_t key; /* optional argument */\n};\n\nstatic void cmd_showport_rss_hash_parsed(void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\tvoid *show_rss_key)\n{\n\tstruct cmd_showport_rss_hash *res = parsed_result;\n\n\tport_rss_hash_conf_show(res->port_id, show_rss_key != NULL);\n}\n\ncmdline_parse_token_string_t cmd_showport_rss_hash_show =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showport_rss_hash, show, \"show\");\ncmdline_parse_token_string_t cmd_showport_rss_hash_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showport_rss_hash, port, \"port\");\ncmdline_parse_token_num_t cmd_showport_rss_hash_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_showport_rss_hash, port_id, UINT8);\ncmdline_parse_token_string_t cmd_showport_rss_hash_rss_hash =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showport_rss_hash, rss_hash,\n\t\t\t\t \"rss-hash\");\ncmdline_parse_token_string_t cmd_showport_rss_hash_rss_key =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showport_rss_hash, key, \"key\");\n\ncmdline_parse_inst_t cmd_showport_rss_hash = {\n\t.f = cmd_showport_rss_hash_parsed,\n\t.data = NULL,\n\t.help_str = \"show port X rss-hash (X = port number)\\n\",\n\t.tokens = {\n\t\t(void *)&cmd_showport_rss_hash_show,\n\t\t(void *)&cmd_showport_rss_hash_port,\n\t\t(void *)&cmd_showport_rss_hash_port_id,\n\t\t(void *)&cmd_showport_rss_hash_rss_hash,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_showport_rss_hash_key = {\n\t.f = cmd_showport_rss_hash_parsed,\n\t.data = (void *)1,\n\t.help_str = \"show port X rss-hash key (X = port number)\\n\",\n\t.tokens = {\n\t\t(void *)&cmd_showport_rss_hash_show,\n\t\t(void *)&cmd_showport_rss_hash_port,\n\t\t(void *)&cmd_showport_rss_hash_port_id,\n\t\t(void *)&cmd_showport_rss_hash_rss_hash,\n\t\t(void *)&cmd_showport_rss_hash_rss_key,\n\t\tNULL,\n\t},\n};\n\n/* *** Configure DCB *** */\nstruct cmd_config_dcb {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t config;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t dcb;\n\tcmdline_fixed_string_t vt;\n\tcmdline_fixed_string_t vt_en;\n\tuint8_t num_tcs;\n\tcmdline_fixed_string_t pfc;\n\tcmdline_fixed_string_t pfc_en;\n};\n\nstatic void\ncmd_config_dcb_parsed(void *parsed_result,\n __attribute__((unused)) struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n\tstruct cmd_config_dcb *res = parsed_result;\n\tstruct dcb_config dcb_conf;\n\tportid_t port_id = res->port_id;\n\tstruct rte_port *port;\n\n\tport = &ports[port_id];\n\t/** Check if the port is not started **/\n\tif (port->port_status != RTE_PORT_STOPPED) {\n\t\tprintf(\"Please stop port %d first\\n\",port_id);\n\t\treturn;\n\t}\n\n\tdcb_conf.num_tcs = (enum rte_eth_nb_tcs) res->num_tcs;\n\tif ((dcb_conf.num_tcs != ETH_4_TCS) && (dcb_conf.num_tcs != ETH_8_TCS)){\n\t\tprintf(\"The invalid number of traffic class,only 4 or 8 allowed\\n\");\n\t\treturn;\n\t}\n\n\t/* DCB in VT mode */\n\tif (!strncmp(res->vt_en, \"on\",2))\n\t\tdcb_conf.dcb_mode = DCB_VT_ENABLED;\n\telse\n\t\tdcb_conf.dcb_mode = DCB_ENABLED;\n\n\tif (!strncmp(res->pfc_en, \"on\",2)) {\n\t\tdcb_conf.pfc_en = 1;\n\t}\n\telse\n\t\tdcb_conf.pfc_en = 0;\n\n\tif (init_port_dcb_config(port_id,&dcb_conf) != 0) {\n\t\tprintf(\"Cannot initialize network ports\\n\");\n\t\treturn;\n\t}\n\n\tcmd_reconfig_device_queue(port_id, 1, 1);\n}\n\ncmdline_parse_token_string_t cmd_config_dcb_port =\n TOKEN_STRING_INITIALIZER(struct cmd_config_dcb, port, \"port\");\ncmdline_parse_token_string_t cmd_config_dcb_config =\n TOKEN_STRING_INITIALIZER(struct cmd_config_dcb, config, \"config\");\ncmdline_parse_token_num_t cmd_config_dcb_port_id =\n TOKEN_NUM_INITIALIZER(struct cmd_config_dcb, port_id, UINT8);\ncmdline_parse_token_string_t cmd_config_dcb_dcb =\n TOKEN_STRING_INITIALIZER(struct cmd_config_dcb, dcb, \"dcb\");\ncmdline_parse_token_string_t cmd_config_dcb_vt =\n TOKEN_STRING_INITIALIZER(struct cmd_config_dcb, vt, \"vt\");\ncmdline_parse_token_string_t cmd_config_dcb_vt_en =\n TOKEN_STRING_INITIALIZER(struct cmd_config_dcb, vt_en, \"on#off\");\ncmdline_parse_token_num_t cmd_config_dcb_num_tcs =\n TOKEN_NUM_INITIALIZER(struct cmd_config_dcb, num_tcs, UINT8);\ncmdline_parse_token_string_t cmd_config_dcb_pfc=\n TOKEN_STRING_INITIALIZER(struct cmd_config_dcb, pfc, \"pfc\");\ncmdline_parse_token_string_t cmd_config_dcb_pfc_en =\n TOKEN_STRING_INITIALIZER(struct cmd_config_dcb, pfc_en, \"on#off\");\n\ncmdline_parse_inst_t cmd_config_dcb = {\n .f = cmd_config_dcb_parsed,\n .data = NULL,\n .help_str = \"port config port-id dcb vt on|off nb-tcs pfc on|off\",\n .tokens = {\n\t\t(void *)&cmd_config_dcb_port,\n\t\t(void *)&cmd_config_dcb_config,\n\t\t(void *)&cmd_config_dcb_port_id,\n\t\t(void *)&cmd_config_dcb_dcb,\n\t\t(void *)&cmd_config_dcb_vt,\n\t\t(void *)&cmd_config_dcb_vt_en,\n\t\t(void *)&cmd_config_dcb_num_tcs,\n\t\t(void *)&cmd_config_dcb_pfc,\n\t\t(void *)&cmd_config_dcb_pfc_en,\n NULL,\n },\n};\n\n/* *** configure number of packets per burst *** */\nstruct cmd_config_burst {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tcmdline_fixed_string_t all;\n\tcmdline_fixed_string_t name;\n\tuint16_t value;\n};\n\nstatic void\ncmd_config_burst_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_config_burst *res = parsed_result;\n\n\tif (!all_ports_stopped()) {\n\t\tprintf(\"Please stop all ports first\\n\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->name, \"burst\")) {\n\t\tif (res->value < 1 || res->value > MAX_PKT_BURST) {\n\t\t\tprintf(\"burst must be >= 1 && <= %d\\n\", MAX_PKT_BURST);\n\t\t\treturn;\n\t\t}\n\t\tnb_pkt_per_burst = res->value;\n\t} else {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\n\tinit_port_config();\n\n\tcmd_reconfig_device_queue(RTE_PORT_ALL, 1, 1);\n}\n\ncmdline_parse_token_string_t cmd_config_burst_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_burst, port, \"port\");\ncmdline_parse_token_string_t cmd_config_burst_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_burst, keyword, \"config\");\ncmdline_parse_token_string_t cmd_config_burst_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_burst, all, \"all\");\ncmdline_parse_token_string_t cmd_config_burst_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_burst, name, \"burst\");\ncmdline_parse_token_num_t cmd_config_burst_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_config_burst, value, UINT16);\n\ncmdline_parse_inst_t cmd_config_burst = {\n\t.f = cmd_config_burst_parsed,\n\t.data = NULL,\n\t.help_str = \"port config all burst value\",\n\t.tokens = {\n\t\t(void *)&cmd_config_burst_port,\n\t\t(void *)&cmd_config_burst_keyword,\n\t\t(void *)&cmd_config_burst_all,\n\t\t(void *)&cmd_config_burst_name,\n\t\t(void *)&cmd_config_burst_value,\n\t\tNULL,\n\t},\n};\n\n/* *** configure rx/tx queues *** */\nstruct cmd_config_thresh {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tcmdline_fixed_string_t all;\n\tcmdline_fixed_string_t name;\n\tuint8_t value;\n};\n\nstatic void\ncmd_config_thresh_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_config_thresh *res = parsed_result;\n\n\tif (!all_ports_stopped()) {\n\t\tprintf(\"Please stop all ports first\\n\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->name, \"txpt\"))\n\t\ttx_pthresh = res->value;\n\telse if(!strcmp(res->name, \"txht\"))\n\t\ttx_hthresh = res->value;\n\telse if(!strcmp(res->name, \"txwt\"))\n\t\ttx_wthresh = res->value;\n\telse if(!strcmp(res->name, \"rxpt\"))\n\t\trx_pthresh = res->value;\n\telse if(!strcmp(res->name, \"rxht\"))\n\t\trx_hthresh = res->value;\n\telse if(!strcmp(res->name, \"rxwt\"))\n\t\trx_wthresh = res->value;\n\telse {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\n\tinit_port_config();\n\n\tcmd_reconfig_device_queue(RTE_PORT_ALL, 1, 1);\n}\n\ncmdline_parse_token_string_t cmd_config_thresh_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_thresh, port, \"port\");\ncmdline_parse_token_string_t cmd_config_thresh_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_thresh, keyword, \"config\");\ncmdline_parse_token_string_t cmd_config_thresh_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_thresh, all, \"all\");\ncmdline_parse_token_string_t cmd_config_thresh_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_thresh, name,\n\t\t\t\t\"txpt#txht#txwt#rxpt#rxht#rxwt\");\ncmdline_parse_token_num_t cmd_config_thresh_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_config_thresh, value, UINT8);\n\ncmdline_parse_inst_t cmd_config_thresh = {\n\t.f = cmd_config_thresh_parsed,\n\t.data = NULL,\n\t.help_str = \"port config all txpt|txht|txwt|rxpt|rxht|rxwt value\",\n\t.tokens = {\n\t\t(void *)&cmd_config_thresh_port,\n\t\t(void *)&cmd_config_thresh_keyword,\n\t\t(void *)&cmd_config_thresh_all,\n\t\t(void *)&cmd_config_thresh_name,\n\t\t(void *)&cmd_config_thresh_value,\n\t\tNULL,\n\t},\n};\n\n/* *** configure free/rs threshold *** */\nstruct cmd_config_threshold {\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t keyword;\n\tcmdline_fixed_string_t all;\n\tcmdline_fixed_string_t name;\n\tuint16_t value;\n};\n\nstatic void\ncmd_config_threshold_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_config_threshold *res = parsed_result;\n\n\tif (!all_ports_stopped()) {\n\t\tprintf(\"Please stop all ports first\\n\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->name, \"txfreet\"))\n\t\ttx_free_thresh = res->value;\n\telse if (!strcmp(res->name, \"txrst\"))\n\t\ttx_rs_thresh = res->value;\n\telse if (!strcmp(res->name, \"rxfreet\"))\n\t\trx_free_thresh = res->value;\n\telse {\n\t\tprintf(\"Unknown parameter\\n\");\n\t\treturn;\n\t}\n\n\tinit_port_config();\n\n\tcmd_reconfig_device_queue(RTE_PORT_ALL, 1, 1);\n}\n\ncmdline_parse_token_string_t cmd_config_threshold_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_threshold, port, \"port\");\ncmdline_parse_token_string_t cmd_config_threshold_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_threshold, keyword,\n\t\t\t\t\t\t\t\t\"config\");\ncmdline_parse_token_string_t cmd_config_threshold_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_threshold, all, \"all\");\ncmdline_parse_token_string_t cmd_config_threshold_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_config_threshold, name,\n\t\t\t\t\t\t\"txfreet#txrst#rxfreet\");\ncmdline_parse_token_num_t cmd_config_threshold_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_config_threshold, value, UINT16);\n\ncmdline_parse_inst_t cmd_config_threshold = {\n\t.f = cmd_config_threshold_parsed,\n\t.data = NULL,\n\t.help_str = \"port config all txfreet|txrst|rxfreet value\",\n\t.tokens = {\n\t\t(void *)&cmd_config_threshold_port,\n\t\t(void *)&cmd_config_threshold_keyword,\n\t\t(void *)&cmd_config_threshold_all,\n\t\t(void *)&cmd_config_threshold_name,\n\t\t(void *)&cmd_config_threshold_value,\n\t\tNULL,\n\t},\n};\n\n/* *** stop *** */\nstruct cmd_stop_result {\n\tcmdline_fixed_string_t stop;\n};\n\nstatic void cmd_stop_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstop_packet_forwarding();\n}\n\ncmdline_parse_token_string_t cmd_stop_stop =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stop_result, stop, \"stop\");\n\ncmdline_parse_inst_t cmd_stop = {\n\t.f = cmd_stop_parsed,\n\t.data = NULL,\n\t.help_str = \"stop - stop packet forwarding\",\n\t.tokens = {\n\t\t(void *)&cmd_stop_stop,\n\t\tNULL,\n\t},\n};\n\n/* *** SET CORELIST and PORTLIST CONFIGURATION *** */\n\nunsigned int\nparse_item_list(char* str, const char* item_name, unsigned int max_items,\n\t\tunsigned int *parsed_items, int check_unique_values)\n{\n\tunsigned int nb_item;\n\tunsigned int value;\n\tunsigned int i;\n\tunsigned int j;\n\tint value_ok;\n\tchar c;\n\n\t/*\n\t * First parse all items in the list and store their value.\n\t */\n\tvalue = 0;\n\tnb_item = 0;\n\tvalue_ok = 0;\n\tfor (i = 0; i < strnlen(str, STR_TOKEN_SIZE); i++) {\n\t\tc = str[i];\n\t\tif ((c >= '0') && (c <= '9')) {\n\t\t\tvalue = (unsigned int) (value * 10 + (c - '0'));\n\t\t\tvalue_ok = 1;\n\t\t\tcontinue;\n\t\t}\n\t\tif (c != ',') {\n\t\t\tprintf(\"character %c is not a decimal digit\\n\", c);\n\t\t\treturn (0);\n\t\t}\n\t\tif (! value_ok) {\n\t\t\tprintf(\"No valid value before comma\\n\");\n\t\t\treturn (0);\n\t\t}\n\t\tif (nb_item < max_items) {\n\t\t\tparsed_items[nb_item] = value;\n\t\t\tvalue_ok = 0;\n\t\t\tvalue = 0;\n\t\t}\n\t\tnb_item++;\n\t}\n\tif (nb_item >= max_items) {\n\t\tprintf(\"Number of %s = %u > %u (maximum items)\\n\",\n\t\t item_name, nb_item + 1, max_items);\n\t\treturn (0);\n\t}\n\tparsed_items[nb_item++] = value;\n\tif (! check_unique_values)\n\t\treturn (nb_item);\n\n\t/*\n\t * Then, check that all values in the list are differents.\n\t * No optimization here...\n\t */\n\tfor (i = 0; i < nb_item; i++) {\n\t\tfor (j = i + 1; j < nb_item; j++) {\n\t\t\tif (parsed_items[j] == parsed_items[i]) {\n\t\t\t\tprintf(\"duplicated %s %u at index %u and %u\\n\",\n\t\t\t\t item_name, parsed_items[i], i, j);\n\t\t\t\treturn (0);\n\t\t\t}\n\t\t}\n\t}\n\treturn (nb_item);\n}\n\nstruct cmd_set_list_result {\n\tcmdline_fixed_string_t cmd_keyword;\n\tcmdline_fixed_string_t list_name;\n\tcmdline_fixed_string_t list_of_items;\n};\n\nstatic void cmd_set_list_parsed(void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_list_result *res;\n\tunion {\n\t\tunsigned int lcorelist[RTE_MAX_LCORE];\n\t\tunsigned int portlist[RTE_MAX_ETHPORTS];\n\t} parsed_items;\n\tunsigned int nb_item;\n\n\tif (test_done == 0) {\n\t\tprintf(\"Please stop forwarding first\\n\");\n\t\treturn;\n\t}\n\n\tres = parsed_result;\n\tif (!strcmp(res->list_name, \"corelist\")) {\n\t\tnb_item = parse_item_list(res->list_of_items, \"core\",\n\t\t\t\t\t RTE_MAX_LCORE,\n\t\t\t\t\t parsed_items.lcorelist, 1);\n\t\tif (nb_item > 0)\n\t\t\tset_fwd_lcores_list(parsed_items.lcorelist, nb_item);\n\t\treturn;\n\t}\n\tif (!strcmp(res->list_name, \"portlist\")) {\n\t\tnb_item = parse_item_list(res->list_of_items, \"port\",\n\t\t\t\t\t RTE_MAX_ETHPORTS,\n\t\t\t\t\t parsed_items.portlist, 1);\n\t\tif (nb_item > 0)\n\t\t\tset_fwd_ports_list(parsed_items.portlist, nb_item);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_set_list_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_list_result, cmd_keyword,\n\t\t\t\t \"set\");\ncmdline_parse_token_string_t cmd_set_list_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_list_result, list_name,\n\t\t\t\t \"corelist#portlist\");\ncmdline_parse_token_string_t cmd_set_list_of_items =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_list_result, list_of_items,\n\t\t\t\t NULL);\n\ncmdline_parse_inst_t cmd_set_fwd_list = {\n\t.f = cmd_set_list_parsed,\n\t.data = NULL,\n\t.help_str = \"set corelist|portlist x[,y]*\",\n\t.tokens = {\n\t\t(void *)&cmd_set_list_keyword,\n\t\t(void *)&cmd_set_list_name,\n\t\t(void *)&cmd_set_list_of_items,\n\t\tNULL,\n\t},\n};\n\n/* *** SET COREMASK and PORTMASK CONFIGURATION *** */\n\nstruct cmd_setmask_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t mask;\n\tuint64_t hexavalue;\n};\n\nstatic void cmd_set_mask_parsed(void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_setmask_result *res = parsed_result;\n\n\tif (test_done == 0) {\n\t\tprintf(\"Please stop forwarding first\\n\");\n\t\treturn;\n\t}\n\tif (!strcmp(res->mask, \"coremask\"))\n\t\tset_fwd_lcores_mask(res->hexavalue);\n\telse if (!strcmp(res->mask, \"portmask\"))\n\t\tset_fwd_ports_mask(res->hexavalue);\n}\n\ncmdline_parse_token_string_t cmd_setmask_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_setmask_result, set, \"set\");\ncmdline_parse_token_string_t cmd_setmask_mask =\n\tTOKEN_STRING_INITIALIZER(struct cmd_setmask_result, mask,\n\t\t\t\t \"coremask#portmask\");\ncmdline_parse_token_num_t cmd_setmask_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_setmask_result, hexavalue, UINT64);\n\ncmdline_parse_inst_t cmd_set_fwd_mask = {\n\t.f = cmd_set_mask_parsed,\n\t.data = NULL,\n\t.help_str = \"set coremask|portmask hexadecimal value\",\n\t.tokens = {\n\t\t(void *)&cmd_setmask_set,\n\t\t(void *)&cmd_setmask_mask,\n\t\t(void *)&cmd_setmask_value,\n\t\tNULL,\n\t},\n};\n\n/*\n * SET NBPORT, NBCORE, PACKET BURST, and VERBOSE LEVEL CONFIGURATION\n */\nstruct cmd_set_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t what;\n\tuint16_t value;\n};\n\nstatic void cmd_set_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_set_result *res = parsed_result;\n\tif (!strcmp(res->what, \"nbport\"))\n\t\tset_fwd_ports_number(res->value);\n\telse if (!strcmp(res->what, \"nbcore\"))\n\t\tset_fwd_lcores_number(res->value);\n\telse if (!strcmp(res->what, \"burst\"))\n\t\tset_nb_pkt_per_burst(res->value);\n\telse if (!strcmp(res->what, \"verbose\"))\n\t\tset_verbose_level(res->value);\n}\n\ncmdline_parse_token_string_t cmd_set_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_result, set, \"set\");\ncmdline_parse_token_string_t cmd_set_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_result, what,\n\t\t\t\t \"nbport#nbcore#burst#verbose\");\ncmdline_parse_token_num_t cmd_set_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_result, value, UINT16);\n\ncmdline_parse_inst_t cmd_set_numbers = {\n\t.f = cmd_set_parsed,\n\t.data = NULL,\n\t.help_str = \"set nbport|nbcore|burst|verbose value\",\n\t.tokens = {\n\t\t(void *)&cmd_set_set,\n\t\t(void *)&cmd_set_what,\n\t\t(void *)&cmd_set_value,\n\t\tNULL,\n\t},\n};\n\n/* *** SET SEGMENT LENGTHS OF TXONLY PACKETS *** */\n\nstruct cmd_set_txpkts_result {\n\tcmdline_fixed_string_t cmd_keyword;\n\tcmdline_fixed_string_t txpkts;\n\tcmdline_fixed_string_t seg_lengths;\n};\n\nstatic void\ncmd_set_txpkts_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_set_txpkts_result *res;\n\tunsigned seg_lengths[RTE_MAX_SEGS_PER_PKT];\n\tunsigned int nb_segs;\n\n\tres = parsed_result;\n\tnb_segs = parse_item_list(res->seg_lengths, \"segment lengths\",\n\t\t\t\t RTE_MAX_SEGS_PER_PKT, seg_lengths, 0);\n\tif (nb_segs > 0)\n\t\tset_tx_pkt_segments(seg_lengths, nb_segs);\n}\n\ncmdline_parse_token_string_t cmd_set_txpkts_keyword =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_txpkts_result,\n\t\t\t\t cmd_keyword, \"set\");\ncmdline_parse_token_string_t cmd_set_txpkts_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_txpkts_result,\n\t\t\t\t txpkts, \"txpkts\");\ncmdline_parse_token_string_t cmd_set_txpkts_lengths =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_txpkts_result,\n\t\t\t\t seg_lengths, NULL);\n\ncmdline_parse_inst_t cmd_set_txpkts = {\n\t.f = cmd_set_txpkts_parsed,\n\t.data = NULL,\n\t.help_str = \"set txpkts x[,y]*\",\n\t.tokens = {\n\t\t(void *)&cmd_set_txpkts_keyword,\n\t\t(void *)&cmd_set_txpkts_name,\n\t\t(void *)&cmd_set_txpkts_lengths,\n\t\tNULL,\n\t},\n};\n\n/* *** ADD/REMOVE ALL VLAN IDENTIFIERS TO/FROM A PORT VLAN RX FILTER *** */\nstruct cmd_rx_vlan_filter_all_result {\n\tcmdline_fixed_string_t rx_vlan;\n\tcmdline_fixed_string_t what;\n\tcmdline_fixed_string_t all;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_rx_vlan_filter_all_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_rx_vlan_filter_all_result *res = parsed_result;\n\n\tif (!strcmp(res->what, \"add\"))\n\t\trx_vlan_all_filter_set(res->port_id, 1);\n\telse\n\t\trx_vlan_all_filter_set(res->port_id, 0);\n}\n\ncmdline_parse_token_string_t cmd_rx_vlan_filter_all_rx_vlan =\n\tTOKEN_STRING_INITIALIZER(struct cmd_rx_vlan_filter_all_result,\n\t\t\t\t rx_vlan, \"rx_vlan\");\ncmdline_parse_token_string_t cmd_rx_vlan_filter_all_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_rx_vlan_filter_all_result,\n\t\t\t\t what, \"add#rm\");\ncmdline_parse_token_string_t cmd_rx_vlan_filter_all_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_rx_vlan_filter_all_result,\n\t\t\t\t all, \"all\");\ncmdline_parse_token_num_t cmd_rx_vlan_filter_all_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_rx_vlan_filter_all_result,\n\t\t\t port_id, UINT8);\n\ncmdline_parse_inst_t cmd_rx_vlan_filter_all = {\n\t.f = cmd_rx_vlan_filter_all_parsed,\n\t.data = NULL,\n\t.help_str = \"add/remove all identifiers to/from the set of VLAN \"\n\t\"Identifiers filtered by a port\",\n\t.tokens = {\n\t\t(void *)&cmd_rx_vlan_filter_all_rx_vlan,\n\t\t(void *)&cmd_rx_vlan_filter_all_what,\n\t\t(void *)&cmd_rx_vlan_filter_all_all,\n\t\t(void *)&cmd_rx_vlan_filter_all_portid,\n\t\tNULL,\n\t},\n};\n\n/* *** VLAN OFFLOAD SET ON A PORT *** */\nstruct cmd_vlan_offload_result {\n\tcmdline_fixed_string_t vlan;\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t what;\n\tcmdline_fixed_string_t on;\n\tcmdline_fixed_string_t port_id;\n};\n\nstatic void\ncmd_vlan_offload_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tint on;\n\tstruct cmd_vlan_offload_result *res = parsed_result;\n\tchar *str;\n\tint i, len = 0;\n\tportid_t port_id = 0;\n\tunsigned int tmp;\n\n\tstr = res->port_id;\n\tlen = strnlen(str, STR_TOKEN_SIZE);\n\ti = 0;\n\t/* Get port_id first */\n\twhile(i < len){\n\t\tif(str[i] == ',')\n\t\t\tbreak;\n\n\t\ti++;\n\t}\n\tstr[i]='\\0';\n\ttmp = strtoul(str, NULL, 0);\n\t/* If port_id greater that what portid_t can represent, return */\n\tif(tmp >= RTE_MAX_ETHPORTS)\n\t\treturn;\n\tport_id = (portid_t)tmp;\n\n\tif (!strcmp(res->on, \"on\"))\n\t\ton = 1;\n\telse\n\t\ton = 0;\n\n\tif (!strcmp(res->what, \"strip\"))\n\t\trx_vlan_strip_set(port_id, on);\n\telse if(!strcmp(res->what, \"stripq\")){\n\t\tuint16_t queue_id = 0;\n\n\t\t/* No queue_id, return */\n\t\tif(i + 1 >= len) {\n\t\t\tprintf(\"must specify (port,queue_id)\\n\");\n\t\t\treturn;\n\t\t}\n\t\ttmp = strtoul(str + i + 1, NULL, 0);\n\t\t/* If queue_id greater that what 16-bits can represent, return */\n\t\tif(tmp > 0xffff)\n\t\t\treturn;\n\n\t\tqueue_id = (uint16_t)tmp;\n\t\trx_vlan_strip_set_on_queue(port_id, queue_id, on);\n\t}\n\telse if (!strcmp(res->what, \"filter\"))\n\t\trx_vlan_filter_set(port_id, on);\n\telse\n\t\tvlan_extend_set(port_id, on);\n\n\treturn;\n}\n\ncmdline_parse_token_string_t cmd_vlan_offload_vlan =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vlan_offload_result,\n\t\t\t\t vlan, \"vlan\");\ncmdline_parse_token_string_t cmd_vlan_offload_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vlan_offload_result,\n\t\t\t\t set, \"set\");\ncmdline_parse_token_string_t cmd_vlan_offload_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vlan_offload_result,\n\t\t\t\t what, \"strip#filter#qinq#stripq\");\ncmdline_parse_token_string_t cmd_vlan_offload_on =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vlan_offload_result,\n\t\t\t on, \"on#off\");\ncmdline_parse_token_string_t cmd_vlan_offload_portid =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vlan_offload_result,\n\t\t\t port_id, NULL);\n\ncmdline_parse_inst_t cmd_vlan_offload = {\n\t.f = cmd_vlan_offload_parsed,\n\t.data = NULL,\n\t.help_str = \"set strip|filter|qinq|stripq on|off port_id[,queue_id], filter/strip for rx side\"\n\t\" qinq(extended) for both rx/tx sides \",\n\t.tokens = {\n\t\t(void *)&cmd_vlan_offload_vlan,\n\t\t(void *)&cmd_vlan_offload_set,\n\t\t(void *)&cmd_vlan_offload_what,\n\t\t(void *)&cmd_vlan_offload_on,\n\t\t(void *)&cmd_vlan_offload_portid,\n\t\tNULL,\n\t},\n};\n\n/* *** VLAN TPID SET ON A PORT *** */\nstruct cmd_vlan_tpid_result {\n\tcmdline_fixed_string_t vlan;\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t what;\n\tuint16_t tp_id;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_vlan_tpid_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_vlan_tpid_result *res = parsed_result;\n\tvlan_tpid_set(res->port_id, res->tp_id);\n\treturn;\n}\n\ncmdline_parse_token_string_t cmd_vlan_tpid_vlan =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vlan_tpid_result,\n\t\t\t\t vlan, \"vlan\");\ncmdline_parse_token_string_t cmd_vlan_tpid_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vlan_tpid_result,\n\t\t\t\t set, \"set\");\ncmdline_parse_token_string_t cmd_vlan_tpid_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vlan_tpid_result,\n\t\t\t\t what, \"tpid\");\ncmdline_parse_token_num_t cmd_vlan_tpid_tpid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_vlan_tpid_result,\n\t\t\t tp_id, UINT16);\ncmdline_parse_token_num_t cmd_vlan_tpid_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_vlan_tpid_result,\n\t\t\t port_id, UINT8);\n\ncmdline_parse_inst_t cmd_vlan_tpid = {\n\t.f = cmd_vlan_tpid_parsed,\n\t.data = NULL,\n\t.help_str = \"set tpid tp_id port_id, set the Outer VLAN Ether type\",\n\t.tokens = {\n\t\t(void *)&cmd_vlan_tpid_vlan,\n\t\t(void *)&cmd_vlan_tpid_set,\n\t\t(void *)&cmd_vlan_tpid_what,\n\t\t(void *)&cmd_vlan_tpid_tpid,\n\t\t(void *)&cmd_vlan_tpid_portid,\n\t\tNULL,\n\t},\n};\n\n/* *** ADD/REMOVE A VLAN IDENTIFIER TO/FROM A PORT VLAN RX FILTER *** */\nstruct cmd_rx_vlan_filter_result {\n\tcmdline_fixed_string_t rx_vlan;\n\tcmdline_fixed_string_t what;\n\tuint16_t vlan_id;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_rx_vlan_filter_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_rx_vlan_filter_result *res = parsed_result;\n\n\tif (!strcmp(res->what, \"add\"))\n\t\trx_vft_set(res->port_id, res->vlan_id, 1);\n\telse\n\t\trx_vft_set(res->port_id, res->vlan_id, 0);\n}\n\ncmdline_parse_token_string_t cmd_rx_vlan_filter_rx_vlan =\n\tTOKEN_STRING_INITIALIZER(struct cmd_rx_vlan_filter_result,\n\t\t\t\t rx_vlan, \"rx_vlan\");\ncmdline_parse_token_string_t cmd_rx_vlan_filter_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_rx_vlan_filter_result,\n\t\t\t\t what, \"add#rm\");\ncmdline_parse_token_num_t cmd_rx_vlan_filter_vlanid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_rx_vlan_filter_result,\n\t\t\t vlan_id, UINT16);\ncmdline_parse_token_num_t cmd_rx_vlan_filter_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_rx_vlan_filter_result,\n\t\t\t port_id, UINT8);\n\ncmdline_parse_inst_t cmd_rx_vlan_filter = {\n\t.f = cmd_rx_vlan_filter_parsed,\n\t.data = NULL,\n\t.help_str = \"add/remove a VLAN identifier to/from the set of VLAN \"\n\t\"Identifiers filtered by a port\",\n\t.tokens = {\n\t\t(void *)&cmd_rx_vlan_filter_rx_vlan,\n\t\t(void *)&cmd_rx_vlan_filter_what,\n\t\t(void *)&cmd_rx_vlan_filter_vlanid,\n\t\t(void *)&cmd_rx_vlan_filter_portid,\n\t\tNULL,\n\t},\n};\n\n/* *** ENABLE HARDWARE INSERTION OF VLAN HEADER IN TX PACKETS *** */\nstruct cmd_tx_vlan_set_result {\n\tcmdline_fixed_string_t tx_vlan;\n\tcmdline_fixed_string_t set;\n\tuint8_t port_id;\n\tuint16_t vlan_id;\n};\n\nstatic void\ncmd_tx_vlan_set_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_tx_vlan_set_result *res = parsed_result;\n\tint vlan_offload = rte_eth_dev_get_vlan_offload(res->port_id);\n\n\tif (vlan_offload & ETH_VLAN_EXTEND_OFFLOAD) {\n\t\tprintf(\"Error, as QinQ has been enabled.\\n\");\n\t\treturn;\n\t}\n\n\ttx_vlan_set(res->port_id, res->vlan_id);\n}\n\ncmdline_parse_token_string_t cmd_tx_vlan_set_tx_vlan =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tx_vlan_set_result,\n\t\t\t\t tx_vlan, \"tx_vlan\");\ncmdline_parse_token_string_t cmd_tx_vlan_set_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tx_vlan_set_result,\n\t\t\t\t set, \"set\");\ncmdline_parse_token_num_t cmd_tx_vlan_set_vlanid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tx_vlan_set_result,\n\t\t\t vlan_id, UINT16);\ncmdline_parse_token_num_t cmd_tx_vlan_set_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tx_vlan_set_result,\n\t\t\t port_id, UINT8);\n\ncmdline_parse_inst_t cmd_tx_vlan_set = {\n\t.f = cmd_tx_vlan_set_parsed,\n\t.data = NULL,\n\t.help_str = \"enable hardware insertion of a single VLAN header \"\n\t\t\"with a given TAG Identifier in packets sent on a port\",\n\t.tokens = {\n\t\t(void *)&cmd_tx_vlan_set_tx_vlan,\n\t\t(void *)&cmd_tx_vlan_set_set,\n\t\t(void *)&cmd_tx_vlan_set_portid,\n\t\t(void *)&cmd_tx_vlan_set_vlanid,\n\t\tNULL,\n\t},\n};\n\n/* *** ENABLE HARDWARE INSERTION OF Double VLAN HEADER IN TX PACKETS *** */\nstruct cmd_tx_vlan_set_qinq_result {\n\tcmdline_fixed_string_t tx_vlan;\n\tcmdline_fixed_string_t set;\n\tuint8_t port_id;\n\tuint16_t vlan_id;\n\tuint16_t vlan_id_outer;\n};\n\nstatic void\ncmd_tx_vlan_set_qinq_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_tx_vlan_set_qinq_result *res = parsed_result;\n\tint vlan_offload = rte_eth_dev_get_vlan_offload(res->port_id);\n\n\tif (!(vlan_offload & ETH_VLAN_EXTEND_OFFLOAD)) {\n\t\tprintf(\"Error, as QinQ hasn't been enabled.\\n\");\n\t\treturn;\n\t}\n\n\ttx_qinq_set(res->port_id, res->vlan_id, res->vlan_id_outer);\n}\n\ncmdline_parse_token_string_t cmd_tx_vlan_set_qinq_tx_vlan =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tx_vlan_set_qinq_result,\n\t\ttx_vlan, \"tx_vlan\");\ncmdline_parse_token_string_t cmd_tx_vlan_set_qinq_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tx_vlan_set_qinq_result,\n\t\tset, \"set\");\ncmdline_parse_token_num_t cmd_tx_vlan_set_qinq_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tx_vlan_set_qinq_result,\n\t\tport_id, UINT8);\ncmdline_parse_token_num_t cmd_tx_vlan_set_qinq_vlanid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tx_vlan_set_qinq_result,\n\t\tvlan_id, UINT16);\ncmdline_parse_token_num_t cmd_tx_vlan_set_qinq_vlanid_outer =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tx_vlan_set_qinq_result,\n\t\tvlan_id_outer, UINT16);\n\ncmdline_parse_inst_t cmd_tx_vlan_set_qinq = {\n\t.f = cmd_tx_vlan_set_qinq_parsed,\n\t.data = NULL,\n\t.help_str = \"enable hardware insertion of double VLAN header \"\n\t\t\"with given TAG Identifiers in packets sent on a port\",\n\t.tokens = {\n\t\t(void *)&cmd_tx_vlan_set_qinq_tx_vlan,\n\t\t(void *)&cmd_tx_vlan_set_qinq_set,\n\t\t(void *)&cmd_tx_vlan_set_qinq_portid,\n\t\t(void *)&cmd_tx_vlan_set_qinq_vlanid,\n\t\t(void *)&cmd_tx_vlan_set_qinq_vlanid_outer,\n\t\tNULL,\n\t},\n};\n\n/* *** ENABLE/DISABLE PORT BASED TX VLAN INSERTION *** */\nstruct cmd_tx_vlan_set_pvid_result {\n\tcmdline_fixed_string_t tx_vlan;\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t pvid;\n\tuint8_t port_id;\n\tuint16_t vlan_id;\n\tcmdline_fixed_string_t mode;\n};\n\nstatic void\ncmd_tx_vlan_set_pvid_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_tx_vlan_set_pvid_result *res = parsed_result;\n\n\tif (strcmp(res->mode, \"on\") == 0)\n\t\ttx_vlan_pvid_set(res->port_id, res->vlan_id, 1);\n\telse\n\t\ttx_vlan_pvid_set(res->port_id, res->vlan_id, 0);\n}\n\ncmdline_parse_token_string_t cmd_tx_vlan_set_pvid_tx_vlan =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tx_vlan_set_pvid_result,\n\t\t\t\t tx_vlan, \"tx_vlan\");\ncmdline_parse_token_string_t cmd_tx_vlan_set_pvid_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tx_vlan_set_pvid_result,\n\t\t\t\t set, \"set\");\ncmdline_parse_token_string_t cmd_tx_vlan_set_pvid_pvid =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tx_vlan_set_pvid_result,\n\t\t\t\t pvid, \"pvid\");\ncmdline_parse_token_num_t cmd_tx_vlan_set_pvid_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tx_vlan_set_pvid_result,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_num_t cmd_tx_vlan_set_pvid_vlan_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tx_vlan_set_pvid_result,\n\t\t\t vlan_id, UINT16);\ncmdline_parse_token_string_t cmd_tx_vlan_set_pvid_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tx_vlan_set_pvid_result,\n\t\t\t\t mode, \"on#off\");\n\ncmdline_parse_inst_t cmd_tx_vlan_set_pvid = {\n\t.f = cmd_tx_vlan_set_pvid_parsed,\n\t.data = NULL,\n\t.help_str = \"tx_vlan set pvid port_id vlan_id (on|off)\",\n\t.tokens = {\n\t\t(void *)&cmd_tx_vlan_set_pvid_tx_vlan,\n\t\t(void *)&cmd_tx_vlan_set_pvid_set,\n\t\t(void *)&cmd_tx_vlan_set_pvid_pvid,\n\t\t(void *)&cmd_tx_vlan_set_pvid_port_id,\n\t\t(void *)&cmd_tx_vlan_set_pvid_vlan_id,\n\t\t(void *)&cmd_tx_vlan_set_pvid_mode,\n\t\tNULL,\n\t},\n};\n\n/* *** DISABLE HARDWARE INSERTION OF VLAN HEADER IN TX PACKETS *** */\nstruct cmd_tx_vlan_reset_result {\n\tcmdline_fixed_string_t tx_vlan;\n\tcmdline_fixed_string_t reset;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_tx_vlan_reset_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_tx_vlan_reset_result *res = parsed_result;\n\n\ttx_vlan_reset(res->port_id);\n}\n\ncmdline_parse_token_string_t cmd_tx_vlan_reset_tx_vlan =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tx_vlan_reset_result,\n\t\t\t\t tx_vlan, \"tx_vlan\");\ncmdline_parse_token_string_t cmd_tx_vlan_reset_reset =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tx_vlan_reset_result,\n\t\t\t\t reset, \"reset\");\ncmdline_parse_token_num_t cmd_tx_vlan_reset_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tx_vlan_reset_result,\n\t\t\t port_id, UINT8);\n\ncmdline_parse_inst_t cmd_tx_vlan_reset = {\n\t.f = cmd_tx_vlan_reset_parsed,\n\t.data = NULL,\n\t.help_str = \"disable hardware insertion of a VLAN header in packets \"\n\t\"sent on a port\",\n\t.tokens = {\n\t\t(void *)&cmd_tx_vlan_reset_tx_vlan,\n\t\t(void *)&cmd_tx_vlan_reset_reset,\n\t\t(void *)&cmd_tx_vlan_reset_portid,\n\t\tNULL,\n\t},\n};\n\n\n/* *** ENABLE HARDWARE INSERTION OF CHECKSUM IN TX PACKETS *** */\nstruct cmd_csum_result {\n\tcmdline_fixed_string_t csum;\n\tcmdline_fixed_string_t mode;\n\tcmdline_fixed_string_t proto;\n\tcmdline_fixed_string_t hwsw;\n\tuint8_t port_id;\n};\n\nstatic void\ncsum_show(int port_id)\n{\n\tstruct rte_eth_dev_info dev_info;\n\tuint16_t ol_flags;\n\n\tol_flags = ports[port_id].tx_ol_flags;\n\tprintf(\"Parse tunnel is %s\\n\",\n\t\t(ol_flags & TESTPMD_TX_OFFLOAD_PARSE_TUNNEL) ? \"on\" : \"off\");\n\tprintf(\"IP checksum offload is %s\\n\",\n\t\t(ol_flags & TESTPMD_TX_OFFLOAD_IP_CKSUM) ? \"hw\" : \"sw\");\n\tprintf(\"UDP checksum offload is %s\\n\",\n\t\t(ol_flags & TESTPMD_TX_OFFLOAD_UDP_CKSUM) ? \"hw\" : \"sw\");\n\tprintf(\"TCP checksum offload is %s\\n\",\n\t\t(ol_flags & TESTPMD_TX_OFFLOAD_TCP_CKSUM) ? \"hw\" : \"sw\");\n\tprintf(\"SCTP checksum offload is %s\\n\",\n\t\t(ol_flags & TESTPMD_TX_OFFLOAD_SCTP_CKSUM) ? \"hw\" : \"sw\");\n\tprintf(\"Outer-Ip checksum offload is %s\\n\",\n\t\t(ol_flags & TESTPMD_TX_OFFLOAD_OUTER_IP_CKSUM) ? \"hw\" : \"sw\");\n\n\t/* display warnings if configuration is not supported by the NIC */\n\trte_eth_dev_info_get(port_id, &dev_info);\n\tif ((ol_flags & TESTPMD_TX_OFFLOAD_IP_CKSUM) &&\n\t\t(dev_info.tx_offload_capa & DEV_TX_OFFLOAD_IPV4_CKSUM) == 0) {\n\t\tprintf(\"Warning: hardware IP checksum enabled but not \"\n\t\t\t\"supported by port %d\\n\", port_id);\n\t}\n\tif ((ol_flags & TESTPMD_TX_OFFLOAD_UDP_CKSUM) &&\n\t\t(dev_info.tx_offload_capa & DEV_TX_OFFLOAD_UDP_CKSUM) == 0) {\n\t\tprintf(\"Warning: hardware UDP checksum enabled but not \"\n\t\t\t\"supported by port %d\\n\", port_id);\n\t}\n\tif ((ol_flags & TESTPMD_TX_OFFLOAD_TCP_CKSUM) &&\n\t\t(dev_info.tx_offload_capa & DEV_TX_OFFLOAD_TCP_CKSUM) == 0) {\n\t\tprintf(\"Warning: hardware TCP checksum enabled but not \"\n\t\t\t\"supported by port %d\\n\", port_id);\n\t}\n\tif ((ol_flags & TESTPMD_TX_OFFLOAD_SCTP_CKSUM) &&\n\t\t(dev_info.tx_offload_capa & DEV_TX_OFFLOAD_SCTP_CKSUM) == 0) {\n\t\tprintf(\"Warning: hardware SCTP checksum enabled but not \"\n\t\t\t\"supported by port %d\\n\", port_id);\n\t}\n\tif ((ol_flags & TESTPMD_TX_OFFLOAD_OUTER_IP_CKSUM) &&\n\t\t(dev_info.tx_offload_capa & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) == 0) {\n\t\tprintf(\"Warning: hardware outer IP checksum enabled but not \"\n\t\t\t\"supported by port %d\\n\", port_id);\n\t}\n}\n\nstatic void\ncmd_csum_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_csum_result *res = parsed_result;\n\tint hw = 0;\n\tuint16_t mask = 0;\n\n\tif (port_id_is_invalid(res->port_id, ENABLED_WARN)) {\n\t\tprintf(\"invalid port %d\\n\", res->port_id);\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->mode, \"set\")) {\n\n\t\tif (!strcmp(res->hwsw, \"hw\"))\n\t\t\thw = 1;\n\n\t\tif (!strcmp(res->proto, \"ip\")) {\n\t\t\tmask = TESTPMD_TX_OFFLOAD_IP_CKSUM;\n\t\t} else if (!strcmp(res->proto, \"udp\")) {\n\t\t\tmask = TESTPMD_TX_OFFLOAD_UDP_CKSUM;\n\t\t} else if (!strcmp(res->proto, \"tcp\")) {\n\t\t\tmask = TESTPMD_TX_OFFLOAD_TCP_CKSUM;\n\t\t} else if (!strcmp(res->proto, \"sctp\")) {\n\t\t\tmask = TESTPMD_TX_OFFLOAD_SCTP_CKSUM;\n\t\t} else if (!strcmp(res->proto, \"outer-ip\")) {\n\t\t\tmask = TESTPMD_TX_OFFLOAD_OUTER_IP_CKSUM;\n\t\t}\n\n\t\tif (hw)\n\t\t\tports[res->port_id].tx_ol_flags |= mask;\n\t\telse\n\t\t\tports[res->port_id].tx_ol_flags &= (~mask);\n\t}\n\tcsum_show(res->port_id);\n}\n\ncmdline_parse_token_string_t cmd_csum_csum =\n\tTOKEN_STRING_INITIALIZER(struct cmd_csum_result,\n\t\t\t\tcsum, \"csum\");\ncmdline_parse_token_string_t cmd_csum_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_csum_result,\n\t\t\t\tmode, \"set\");\ncmdline_parse_token_string_t cmd_csum_proto =\n\tTOKEN_STRING_INITIALIZER(struct cmd_csum_result,\n\t\t\t\tproto, \"ip#tcp#udp#sctp#outer-ip\");\ncmdline_parse_token_string_t cmd_csum_hwsw =\n\tTOKEN_STRING_INITIALIZER(struct cmd_csum_result,\n\t\t\t\thwsw, \"hw#sw\");\ncmdline_parse_token_num_t cmd_csum_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_csum_result,\n\t\t\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_csum_set = {\n\t.f = cmd_csum_parsed,\n\t.data = NULL,\n\t.help_str = \"enable/disable hardware calculation of L3/L4 checksum when \"\n\t\t\"using csum forward engine: csum set ip|tcp|udp|sctp|outer-ip hw|sw \",\n\t.tokens = {\n\t\t(void *)&cmd_csum_csum,\n\t\t(void *)&cmd_csum_mode,\n\t\t(void *)&cmd_csum_proto,\n\t\t(void *)&cmd_csum_hwsw,\n\t\t(void *)&cmd_csum_portid,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_token_string_t cmd_csum_mode_show =\n\tTOKEN_STRING_INITIALIZER(struct cmd_csum_result,\n\t\t\t\tmode, \"show\");\n\ncmdline_parse_inst_t cmd_csum_show = {\n\t.f = cmd_csum_parsed,\n\t.data = NULL,\n\t.help_str = \"show checksum offload configuration: csum show \",\n\t.tokens = {\n\t\t(void *)&cmd_csum_csum,\n\t\t(void *)&cmd_csum_mode_show,\n\t\t(void *)&cmd_csum_portid,\n\t\tNULL,\n\t},\n};\n\n/* Enable/disable tunnel parsing */\nstruct cmd_csum_tunnel_result {\n\tcmdline_fixed_string_t csum;\n\tcmdline_fixed_string_t parse;\n\tcmdline_fixed_string_t onoff;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_csum_tunnel_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_csum_tunnel_result *res = parsed_result;\n\n\tif (port_id_is_invalid(res->port_id, ENABLED_WARN))\n\t\treturn;\n\n\tif (!strcmp(res->onoff, \"on\"))\n\t\tports[res->port_id].tx_ol_flags |=\n\t\t\tTESTPMD_TX_OFFLOAD_PARSE_TUNNEL;\n\telse\n\t\tports[res->port_id].tx_ol_flags &=\n\t\t\t(~TESTPMD_TX_OFFLOAD_PARSE_TUNNEL);\n\n\tcsum_show(res->port_id);\n}\n\ncmdline_parse_token_string_t cmd_csum_tunnel_csum =\n\tTOKEN_STRING_INITIALIZER(struct cmd_csum_tunnel_result,\n\t\t\t\tcsum, \"csum\");\ncmdline_parse_token_string_t cmd_csum_tunnel_parse =\n\tTOKEN_STRING_INITIALIZER(struct cmd_csum_tunnel_result,\n\t\t\t\tparse, \"parse_tunnel\");\ncmdline_parse_token_string_t cmd_csum_tunnel_onoff =\n\tTOKEN_STRING_INITIALIZER(struct cmd_csum_tunnel_result,\n\t\t\t\tonoff, \"on#off\");\ncmdline_parse_token_num_t cmd_csum_tunnel_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_csum_tunnel_result,\n\t\t\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_csum_tunnel = {\n\t.f = cmd_csum_tunnel_parsed,\n\t.data = NULL,\n\t.help_str = \"enable/disable parsing of tunnels for csum engine: \"\n\t\"csum parse_tunnel on|off \",\n\t.tokens = {\n\t\t(void *)&cmd_csum_tunnel_csum,\n\t\t(void *)&cmd_csum_tunnel_parse,\n\t\t(void *)&cmd_csum_tunnel_onoff,\n\t\t(void *)&cmd_csum_tunnel_portid,\n\t\tNULL,\n\t},\n};\n\n/* *** ENABLE HARDWARE SEGMENTATION IN TX PACKETS *** */\nstruct cmd_tso_set_result {\n\tcmdline_fixed_string_t tso;\n\tcmdline_fixed_string_t mode;\n\tuint16_t tso_segsz;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_tso_set_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_tso_set_result *res = parsed_result;\n\tstruct rte_eth_dev_info dev_info;\n\n\tif (port_id_is_invalid(res->port_id, ENABLED_WARN))\n\t\treturn;\n\n\tif (!strcmp(res->mode, \"set\"))\n\t\tports[res->port_id].tso_segsz = res->tso_segsz;\n\n\tif (ports[res->port_id].tso_segsz == 0)\n\t\tprintf(\"TSO is disabled\\n\");\n\telse\n\t\tprintf(\"TSO segment size is %d\\n\",\n\t\t\tports[res->port_id].tso_segsz);\n\n\t/* display warnings if configuration is not supported by the NIC */\n\trte_eth_dev_info_get(res->port_id, &dev_info);\n\tif ((ports[res->port_id].tso_segsz != 0) &&\n\t\t(dev_info.tx_offload_capa & DEV_TX_OFFLOAD_TCP_TSO) == 0) {\n\t\tprintf(\"Warning: TSO enabled but not \"\n\t\t\t\"supported by port %d\\n\", res->port_id);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_tso_set_tso =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tso_set_result,\n\t\t\t\ttso, \"tso\");\ncmdline_parse_token_string_t cmd_tso_set_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tso_set_result,\n\t\t\t\tmode, \"set\");\ncmdline_parse_token_num_t cmd_tso_set_tso_segsz =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tso_set_result,\n\t\t\t\ttso_segsz, UINT16);\ncmdline_parse_token_num_t cmd_tso_set_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tso_set_result,\n\t\t\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_tso_set = {\n\t.f = cmd_tso_set_parsed,\n\t.data = NULL,\n\t.help_str = \"Set TSO segment size for csum engine (0 to disable): \"\n\t\"tso set \",\n\t.tokens = {\n\t\t(void *)&cmd_tso_set_tso,\n\t\t(void *)&cmd_tso_set_mode,\n\t\t(void *)&cmd_tso_set_tso_segsz,\n\t\t(void *)&cmd_tso_set_portid,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_token_string_t cmd_tso_show_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tso_set_result,\n\t\t\t\tmode, \"show\");\n\n\ncmdline_parse_inst_t cmd_tso_show = {\n\t.f = cmd_tso_set_parsed,\n\t.data = NULL,\n\t.help_str = \"Show TSO segment size for csum engine: \"\n\t\"tso show \",\n\t.tokens = {\n\t\t(void *)&cmd_tso_set_tso,\n\t\t(void *)&cmd_tso_show_mode,\n\t\t(void *)&cmd_tso_set_portid,\n\t\tNULL,\n\t},\n};\n\n/* *** ENABLE/DISABLE FLUSH ON RX STREAMS *** */\nstruct cmd_set_flush_rx {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t flush_rx;\n\tcmdline_fixed_string_t mode;\n};\n\nstatic void\ncmd_set_flush_rx_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_flush_rx *res = parsed_result;\n\tno_flush_rx = (uint8_t)((strcmp(res->mode, \"on\") == 0) ? 0 : 1);\n}\n\ncmdline_parse_token_string_t cmd_setflushrx_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_flush_rx,\n\t\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_setflushrx_flush_rx =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_flush_rx,\n\t\t\tflush_rx, \"flush_rx\");\ncmdline_parse_token_string_t cmd_setflushrx_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_flush_rx,\n\t\t\tmode, \"on#off\");\n\n\ncmdline_parse_inst_t cmd_set_flush_rx = {\n\t.f = cmd_set_flush_rx_parsed,\n\t.help_str = \"set flush_rx on|off: enable/disable flush on rx streams\",\n\t.data = NULL,\n\t.tokens = {\n\t\t(void *)&cmd_setflushrx_set,\n\t\t(void *)&cmd_setflushrx_flush_rx,\n\t\t(void *)&cmd_setflushrx_mode,\n\t\tNULL,\n\t},\n};\n\n/* *** ENABLE/DISABLE LINK STATUS CHECK *** */\nstruct cmd_set_link_check {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t link_check;\n\tcmdline_fixed_string_t mode;\n};\n\nstatic void\ncmd_set_link_check_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_link_check *res = parsed_result;\n\tno_link_check = (uint8_t)((strcmp(res->mode, \"on\") == 0) ? 0 : 1);\n}\n\ncmdline_parse_token_string_t cmd_setlinkcheck_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_link_check,\n\t\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_setlinkcheck_link_check =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_link_check,\n\t\t\tlink_check, \"link_check\");\ncmdline_parse_token_string_t cmd_setlinkcheck_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_link_check,\n\t\t\tmode, \"on#off\");\n\n\ncmdline_parse_inst_t cmd_set_link_check = {\n\t.f = cmd_set_link_check_parsed,\n\t.help_str = \"set link_check on|off: enable/disable link status check \"\n\t \"when starting/stopping a port\",\n\t.data = NULL,\n\t.tokens = {\n\t\t(void *)&cmd_setlinkcheck_set,\n\t\t(void *)&cmd_setlinkcheck_link_check,\n\t\t(void *)&cmd_setlinkcheck_mode,\n\t\tNULL,\n\t},\n};\n\n#ifdef RTE_NIC_BYPASS\n/* *** SET NIC BYPASS MODE *** */\nstruct cmd_set_bypass_mode_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t bypass;\n\tcmdline_fixed_string_t mode;\n\tcmdline_fixed_string_t value;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_set_bypass_mode_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_bypass_mode_result *res = parsed_result;\n\tportid_t port_id = res->port_id;\n\tuint32_t bypass_mode = RTE_BYPASS_MODE_NORMAL;\n\n\tif (!bypass_is_supported(port_id))\n\t\treturn;\n\n\tif (!strcmp(res->value, \"bypass\"))\n\t\tbypass_mode = RTE_BYPASS_MODE_BYPASS;\n\telse if (!strcmp(res->value, \"isolate\"))\n\t\tbypass_mode = RTE_BYPASS_MODE_ISOLATE;\n\telse\n\t\tbypass_mode = RTE_BYPASS_MODE_NORMAL;\n\n\t/* Set the bypass mode for the relevant port. */\n\tif (0 != rte_eth_dev_bypass_state_set(port_id, &bypass_mode)) {\n\t\tprintf(\"\\t Failed to set bypass mode for port = %d.\\n\", port_id);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_setbypass_mode_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_mode_result,\n\t\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_setbypass_mode_bypass =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_mode_result,\n\t\t\tbypass, \"bypass\");\ncmdline_parse_token_string_t cmd_setbypass_mode_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_mode_result,\n\t\t\tmode, \"mode\");\ncmdline_parse_token_string_t cmd_setbypass_mode_value =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_mode_result,\n\t\t\tvalue, \"normal#bypass#isolate\");\ncmdline_parse_token_num_t cmd_setbypass_mode_port =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_bypass_mode_result,\n\t\t\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_set_bypass_mode = {\n\t.f = cmd_set_bypass_mode_parsed,\n\t.help_str = \"set bypass mode (normal|bypass|isolate) (port_id): \"\n\t \"Set the NIC bypass mode for port_id\",\n\t.data = NULL,\n\t.tokens = {\n\t\t(void *)&cmd_setbypass_mode_set,\n\t\t(void *)&cmd_setbypass_mode_bypass,\n\t\t(void *)&cmd_setbypass_mode_mode,\n\t\t(void *)&cmd_setbypass_mode_value,\n\t\t(void *)&cmd_setbypass_mode_port,\n\t\tNULL,\n\t},\n};\n\n/* *** SET NIC BYPASS EVENT *** */\nstruct cmd_set_bypass_event_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t bypass;\n\tcmdline_fixed_string_t event;\n\tcmdline_fixed_string_t event_value;\n\tcmdline_fixed_string_t mode;\n\tcmdline_fixed_string_t mode_value;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_set_bypass_event_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tint32_t rc;\n\tstruct cmd_set_bypass_event_result *res = parsed_result;\n\tportid_t port_id = res->port_id;\n\tuint32_t bypass_event = RTE_BYPASS_EVENT_NONE;\n\tuint32_t bypass_mode = RTE_BYPASS_MODE_NORMAL;\n\n\tif (!bypass_is_supported(port_id))\n\t\treturn;\n\n\tif (!strcmp(res->event_value, \"timeout\"))\n\t\tbypass_event = RTE_BYPASS_EVENT_TIMEOUT;\n\telse if (!strcmp(res->event_value, \"os_on\"))\n\t\tbypass_event = RTE_BYPASS_EVENT_OS_ON;\n\telse if (!strcmp(res->event_value, \"os_off\"))\n\t\tbypass_event = RTE_BYPASS_EVENT_OS_OFF;\n\telse if (!strcmp(res->event_value, \"power_on\"))\n\t\tbypass_event = RTE_BYPASS_EVENT_POWER_ON;\n\telse if (!strcmp(res->event_value, \"power_off\"))\n\t\tbypass_event = RTE_BYPASS_EVENT_POWER_OFF;\n\telse\n\t\tbypass_event = RTE_BYPASS_EVENT_NONE;\n\n\tif (!strcmp(res->mode_value, \"bypass\"))\n\t\tbypass_mode = RTE_BYPASS_MODE_BYPASS;\n\telse if (!strcmp(res->mode_value, \"isolate\"))\n\t\tbypass_mode = RTE_BYPASS_MODE_ISOLATE;\n\telse\n\t\tbypass_mode = RTE_BYPASS_MODE_NORMAL;\n\n\t/* Set the watchdog timeout. */\n\tif (bypass_event == RTE_BYPASS_EVENT_TIMEOUT) {\n\n\t\trc = -EINVAL;\n\t\tif (!RTE_BYPASS_TMT_VALID(bypass_timeout) ||\n\t\t\t\t(rc = rte_eth_dev_wd_timeout_store(port_id,\n\t\t\t\tbypass_timeout)) != 0) {\n\t\t\tprintf(\"Failed to set timeout value %u \"\n\t\t\t\t\"for port %d, errto code: %d.\\n\",\n\t\t\t\tbypass_timeout, port_id, rc);\n\t\t}\n\t}\n\n\t/* Set the bypass event to transition to bypass mode. */\n\tif (0 != rte_eth_dev_bypass_event_store(port_id,\n\t\t\tbypass_event, bypass_mode)) {\n\t\tprintf(\"\\t Failed to set bypass event for port = %d.\\n\", port_id);\n\t}\n\n}\n\ncmdline_parse_token_string_t cmd_setbypass_event_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_event_result,\n\t\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_setbypass_event_bypass =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_event_result,\n\t\t\tbypass, \"bypass\");\ncmdline_parse_token_string_t cmd_setbypass_event_event =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_event_result,\n\t\t\tevent, \"event\");\ncmdline_parse_token_string_t cmd_setbypass_event_event_value =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_event_result,\n\t\t\tevent_value, \"none#timeout#os_off#os_on#power_on#power_off\");\ncmdline_parse_token_string_t cmd_setbypass_event_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_event_result,\n\t\t\tmode, \"mode\");\ncmdline_parse_token_string_t cmd_setbypass_event_mode_value =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_event_result,\n\t\t\tmode_value, \"normal#bypass#isolate\");\ncmdline_parse_token_num_t cmd_setbypass_event_port =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_bypass_event_result,\n\t\t\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_set_bypass_event = {\n\t.f = cmd_set_bypass_event_parsed,\n\t.help_str = \"set bypass event (timeout|os_on|os_off|power_on|power_off) \"\n\t \"mode (normal|bypass|isolate) (port_id): \"\n\t \"Set the NIC bypass event mode for port_id\",\n\t.data = NULL,\n\t.tokens = {\n\t\t(void *)&cmd_setbypass_event_set,\n\t\t(void *)&cmd_setbypass_event_bypass,\n\t\t(void *)&cmd_setbypass_event_event,\n\t\t(void *)&cmd_setbypass_event_event_value,\n\t\t(void *)&cmd_setbypass_event_mode,\n\t\t(void *)&cmd_setbypass_event_mode_value,\n\t\t(void *)&cmd_setbypass_event_port,\n\t\tNULL,\n\t},\n};\n\n\n/* *** SET NIC BYPASS TIMEOUT *** */\nstruct cmd_set_bypass_timeout_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t bypass;\n\tcmdline_fixed_string_t timeout;\n\tcmdline_fixed_string_t value;\n};\n\nstatic void\ncmd_set_bypass_timeout_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_bypass_timeout_result *res = parsed_result;\n\n\tif (!strcmp(res->value, \"1.5\"))\n\t\tbypass_timeout = RTE_BYPASS_TMT_1_5_SEC;\n\telse if (!strcmp(res->value, \"2\"))\n\t\tbypass_timeout = RTE_BYPASS_TMT_2_SEC;\n\telse if (!strcmp(res->value, \"3\"))\n\t\tbypass_timeout = RTE_BYPASS_TMT_3_SEC;\n\telse if (!strcmp(res->value, \"4\"))\n\t\tbypass_timeout = RTE_BYPASS_TMT_4_SEC;\n\telse if (!strcmp(res->value, \"8\"))\n\t\tbypass_timeout = RTE_BYPASS_TMT_8_SEC;\n\telse if (!strcmp(res->value, \"16\"))\n\t\tbypass_timeout = RTE_BYPASS_TMT_16_SEC;\n\telse if (!strcmp(res->value, \"32\"))\n\t\tbypass_timeout = RTE_BYPASS_TMT_32_SEC;\n\telse\n\t\tbypass_timeout = RTE_BYPASS_TMT_OFF;\n}\n\ncmdline_parse_token_string_t cmd_setbypass_timeout_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_timeout_result,\n\t\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_setbypass_timeout_bypass =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_timeout_result,\n\t\t\tbypass, \"bypass\");\ncmdline_parse_token_string_t cmd_setbypass_timeout_timeout =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_timeout_result,\n\t\t\ttimeout, \"timeout\");\ncmdline_parse_token_string_t cmd_setbypass_timeout_value =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_bypass_timeout_result,\n\t\t\tvalue, \"0#1.5#2#3#4#8#16#32\");\n\ncmdline_parse_inst_t cmd_set_bypass_timeout = {\n\t.f = cmd_set_bypass_timeout_parsed,\n\t.help_str = \"set bypass timeout (0|1.5|2|3|4|8|16|32) seconds: \"\n\t \"Set the NIC bypass watchdog timeout\",\n\t.data = NULL,\n\t.tokens = {\n\t\t(void *)&cmd_setbypass_timeout_set,\n\t\t(void *)&cmd_setbypass_timeout_bypass,\n\t\t(void *)&cmd_setbypass_timeout_timeout,\n\t\t(void *)&cmd_setbypass_timeout_value,\n\t\tNULL,\n\t},\n};\n\n/* *** SHOW NIC BYPASS MODE *** */\nstruct cmd_show_bypass_config_result {\n\tcmdline_fixed_string_t show;\n\tcmdline_fixed_string_t bypass;\n\tcmdline_fixed_string_t config;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_show_bypass_config_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_show_bypass_config_result *res = parsed_result;\n\tuint32_t event_mode;\n\tuint32_t bypass_mode;\n\tportid_t port_id = res->port_id;\n\tuint32_t timeout = bypass_timeout;\n\tint i;\n\n\tstatic const char * const timeouts[RTE_BYPASS_TMT_NUM] =\n\t\t{\"off\", \"1.5\", \"2\", \"3\", \"4\", \"8\", \"16\", \"32\"};\n\tstatic const char * const modes[RTE_BYPASS_MODE_NUM] =\n\t\t{\"UNKNOWN\", \"normal\", \"bypass\", \"isolate\"};\n\tstatic const char * const events[RTE_BYPASS_EVENT_NUM] = {\n\t\t\"NONE\",\n\t\t\"OS/board on\",\n\t\t\"power supply on\",\n\t\t\"OS/board off\",\n\t\t\"power supply off\",\n\t\t\"timeout\"};\n\tint num_events = (sizeof events) / (sizeof events[0]);\n\n\tif (!bypass_is_supported(port_id))\n\t\treturn;\n\n\t/* Display the bypass mode.*/\n\tif (0 != rte_eth_dev_bypass_state_show(port_id, &bypass_mode)) {\n\t\tprintf(\"\\tFailed to get bypass mode for port = %d\\n\", port_id);\n\t\treturn;\n\t}\n\telse {\n\t\tif (!RTE_BYPASS_MODE_VALID(bypass_mode))\n\t\t\tbypass_mode = RTE_BYPASS_MODE_NONE;\n\n\t\tprintf(\"\\tbypass mode = %s\\n\", modes[bypass_mode]);\n\t}\n\n\t/* Display the bypass timeout.*/\n\tif (!RTE_BYPASS_TMT_VALID(timeout))\n\t\ttimeout = RTE_BYPASS_TMT_OFF;\n\n\tprintf(\"\\tbypass timeout = %s\\n\", timeouts[timeout]);\n\n\t/* Display the bypass events and associated modes. */\n\tfor (i = RTE_BYPASS_EVENT_START; i < num_events; i++) {\n\n\t\tif (0 != rte_eth_dev_bypass_event_show(port_id, i, &event_mode)) {\n\t\t\tprintf(\"\\tFailed to get bypass mode for event = %s\\n\",\n\t\t\t\tevents[i]);\n\t\t} else {\n\t\t\tif (!RTE_BYPASS_MODE_VALID(event_mode))\n\t\t\t\tevent_mode = RTE_BYPASS_MODE_NONE;\n\n\t\t\tprintf(\"\\tbypass event: %-16s = %s\\n\", events[i],\n\t\t\t\tmodes[event_mode]);\n\t\t}\n\t}\n}\n\ncmdline_parse_token_string_t cmd_showbypass_config_show =\n\tTOKEN_STRING_INITIALIZER(struct cmd_show_bypass_config_result,\n\t\t\tshow, \"show\");\ncmdline_parse_token_string_t cmd_showbypass_config_bypass =\n\tTOKEN_STRING_INITIALIZER(struct cmd_show_bypass_config_result,\n\t\t\tbypass, \"bypass\");\ncmdline_parse_token_string_t cmd_showbypass_config_config =\n\tTOKEN_STRING_INITIALIZER(struct cmd_show_bypass_config_result,\n\t\t\tconfig, \"config\");\ncmdline_parse_token_num_t cmd_showbypass_config_port =\n\tTOKEN_NUM_INITIALIZER(struct cmd_show_bypass_config_result,\n\t\t\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_show_bypass_config = {\n\t.f = cmd_show_bypass_config_parsed,\n\t.help_str = \"show bypass config (port_id): \"\n\t \"Show the NIC bypass config for port_id\",\n\t.data = NULL,\n\t.tokens = {\n\t\t(void *)&cmd_showbypass_config_show,\n\t\t(void *)&cmd_showbypass_config_bypass,\n\t\t(void *)&cmd_showbypass_config_config,\n\t\t(void *)&cmd_showbypass_config_port,\n\t\tNULL,\n\t},\n};\n#endif\n\n#ifdef RTE_LIBRTE_PMD_BOND\n/* *** SET BONDING MODE *** */\nstruct cmd_set_bonding_mode_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t bonding;\n\tcmdline_fixed_string_t mode;\n\tuint8_t value;\n\tuint8_t port_id;\n};\n\nstatic void cmd_set_bonding_mode_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_bonding_mode_result *res = parsed_result;\n\tportid_t port_id = res->port_id;\n\n\t/* Set the bonding mode for the relevant port. */\n\tif (0 != rte_eth_bond_mode_set(port_id, res->value))\n\t\tprintf(\"\\t Failed to set bonding mode for port = %d.\\n\", port_id);\n}\n\ncmdline_parse_token_string_t cmd_setbonding_mode_set =\nTOKEN_STRING_INITIALIZER(struct cmd_set_bonding_mode_result,\n\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_setbonding_mode_bonding =\nTOKEN_STRING_INITIALIZER(struct cmd_set_bonding_mode_result,\n\t\tbonding, \"bonding\");\ncmdline_parse_token_string_t cmd_setbonding_mode_mode =\nTOKEN_STRING_INITIALIZER(struct cmd_set_bonding_mode_result,\n\t\tmode, \"mode\");\ncmdline_parse_token_num_t cmd_setbonding_mode_value =\nTOKEN_NUM_INITIALIZER(struct cmd_set_bonding_mode_result,\n\t\tvalue, UINT8);\ncmdline_parse_token_num_t cmd_setbonding_mode_port =\nTOKEN_NUM_INITIALIZER(struct cmd_set_bonding_mode_result,\n\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_set_bonding_mode = {\n\t\t.f = cmd_set_bonding_mode_parsed,\n\t\t.help_str = \"set bonding mode (mode_value) (port_id): Set the bonding mode for port_id\",\n\t\t.data = NULL,\n\t\t.tokens = {\n\t\t\t\t(void *) &cmd_setbonding_mode_set,\n\t\t\t\t(void *) &cmd_setbonding_mode_bonding,\n\t\t\t\t(void *) &cmd_setbonding_mode_mode,\n\t\t\t\t(void *) &cmd_setbonding_mode_value,\n\t\t\t\t(void *) &cmd_setbonding_mode_port,\n\t\t\t\tNULL\n\t\t}\n};\n\n/* *** SET BALANCE XMIT POLICY *** */\nstruct cmd_set_bonding_balance_xmit_policy_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t bonding;\n\tcmdline_fixed_string_t balance_xmit_policy;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t policy;\n};\n\nstatic void cmd_set_bonding_balance_xmit_policy_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_bonding_balance_xmit_policy_result *res = parsed_result;\n\tportid_t port_id = res->port_id;\n\tuint8_t policy;\n\n\tif (!strcmp(res->policy, \"l2\")) {\n\t\tpolicy = BALANCE_XMIT_POLICY_LAYER2;\n\t} else if (!strcmp(res->policy, \"l23\")) {\n\t\tpolicy = BALANCE_XMIT_POLICY_LAYER23;\n\t} else if (!strcmp(res->policy, \"l34\")) {\n\t\tpolicy = BALANCE_XMIT_POLICY_LAYER34;\n\t} else {\n\t\tprintf(\"\\t Invalid xmit policy selection\");\n\t\treturn;\n\t}\n\n\t/* Set the bonding mode for the relevant port. */\n\tif (0 != rte_eth_bond_xmit_policy_set(port_id, policy)) {\n\t\tprintf(\"\\t Failed to set bonding balance xmit policy for port = %d.\\n\",\n\t\t\t\tport_id);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_setbonding_balance_xmit_policy_set =\nTOKEN_STRING_INITIALIZER(struct cmd_set_bonding_balance_xmit_policy_result,\n\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_setbonding_balance_xmit_policy_bonding =\nTOKEN_STRING_INITIALIZER(struct cmd_set_bonding_balance_xmit_policy_result,\n\t\tbonding, \"bonding\");\ncmdline_parse_token_string_t cmd_setbonding_balance_xmit_policy_balance_xmit_policy =\nTOKEN_STRING_INITIALIZER(struct cmd_set_bonding_balance_xmit_policy_result,\n\t\tbalance_xmit_policy, \"balance_xmit_policy\");\ncmdline_parse_token_num_t cmd_setbonding_balance_xmit_policy_port =\nTOKEN_NUM_INITIALIZER(struct cmd_set_bonding_balance_xmit_policy_result,\n\t\tport_id, UINT8);\ncmdline_parse_token_string_t cmd_setbonding_balance_xmit_policy_policy =\nTOKEN_STRING_INITIALIZER(struct cmd_set_bonding_balance_xmit_policy_result,\n\t\tpolicy, \"l2#l23#l34\");\n\ncmdline_parse_inst_t cmd_set_balance_xmit_policy = {\n\t\t.f = cmd_set_bonding_balance_xmit_policy_parsed,\n\t\t.help_str = \"set bonding balance_xmit_policy (port_id) (policy_value): Set the bonding balance_xmit_policy for port_id\",\n\t\t.data = NULL,\n\t\t.tokens = {\n\t\t\t\t(void *)&cmd_setbonding_balance_xmit_policy_set,\n\t\t\t\t(void *)&cmd_setbonding_balance_xmit_policy_bonding,\n\t\t\t\t(void *)&cmd_setbonding_balance_xmit_policy_balance_xmit_policy,\n\t\t\t\t(void *)&cmd_setbonding_balance_xmit_policy_port,\n\t\t\t\t(void *)&cmd_setbonding_balance_xmit_policy_policy,\n\t\t\t\tNULL\n\t\t}\n};\n\n/* *** SHOW NIC BONDING CONFIGURATION *** */\nstruct cmd_show_bonding_config_result {\n\tcmdline_fixed_string_t show;\n\tcmdline_fixed_string_t bonding;\n\tcmdline_fixed_string_t config;\n\tuint8_t port_id;\n};\n\nstatic void cmd_show_bonding_config_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_show_bonding_config_result *res = parsed_result;\n\tint bonding_mode;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\tint num_slaves, num_active_slaves;\n\tint primary_id;\n\tint i;\n\tportid_t port_id = res->port_id;\n\n\t/* Display the bonding mode.*/\n\tbonding_mode = rte_eth_bond_mode_get(port_id);\n\tif (bonding_mode < 0) {\n\t\tprintf(\"\\tFailed to get bonding mode for port = %d\\n\", port_id);\n\t\treturn;\n\t} else\n\t\tprintf(\"\\tBonding mode: %d\\n\", bonding_mode);\n\n\tif (bonding_mode == BONDING_MODE_BALANCE) {\n\t\tint balance_xmit_policy;\n\n\t\tbalance_xmit_policy = rte_eth_bond_xmit_policy_get(port_id);\n\t\tif (balance_xmit_policy < 0) {\n\t\t\tprintf(\"\\tFailed to get balance xmit policy for port = %d\\n\",\n\t\t\t\t\tport_id);\n\t\t\treturn;\n\t\t} else {\n\t\t\tprintf(\"\\tBalance Xmit Policy: \");\n\n\t\t\tswitch (balance_xmit_policy) {\n\t\t\tcase BALANCE_XMIT_POLICY_LAYER2:\n\t\t\t\tprintf(\"BALANCE_XMIT_POLICY_LAYER2\");\n\t\t\t\tbreak;\n\t\t\tcase BALANCE_XMIT_POLICY_LAYER23:\n\t\t\t\tprintf(\"BALANCE_XMIT_POLICY_LAYER23\");\n\t\t\t\tbreak;\n\t\t\tcase BALANCE_XMIT_POLICY_LAYER34:\n\t\t\t\tprintf(\"BALANCE_XMIT_POLICY_LAYER34\");\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tprintf(\"\\n\");\n\t\t}\n\t}\n\n\tnum_slaves = rte_eth_bond_slaves_get(port_id, slaves, RTE_MAX_ETHPORTS);\n\n\tif (num_slaves < 0) {\n\t\tprintf(\"\\tFailed to get slave list for port = %d\\n\", port_id);\n\t\treturn;\n\t}\n\tif (num_slaves > 0) {\n\t\tprintf(\"\\tSlaves (%d): [\", num_slaves);\n\t\tfor (i = 0; i < num_slaves - 1; i++)\n\t\t\tprintf(\"%d \", slaves[i]);\n\n\t\tprintf(\"%d]\\n\", slaves[num_slaves - 1]);\n\t} else {\n\t\tprintf(\"\\tSlaves: []\\n\");\n\n\t}\n\n\tnum_active_slaves = rte_eth_bond_active_slaves_get(port_id, slaves,\n\t\t\tRTE_MAX_ETHPORTS);\n\n\tif (num_active_slaves < 0) {\n\t\tprintf(\"\\tFailed to get active slave list for port = %d\\n\", port_id);\n\t\treturn;\n\t}\n\tif (num_active_slaves > 0) {\n\t\tprintf(\"\\tActive Slaves (%d): [\", num_active_slaves);\n\t\tfor (i = 0; i < num_active_slaves - 1; i++)\n\t\t\tprintf(\"%d \", slaves[i]);\n\n\t\tprintf(\"%d]\\n\", slaves[num_active_slaves - 1]);\n\n\t} else {\n\t\tprintf(\"\\tActive Slaves: []\\n\");\n\n\t}\n\n\tprimary_id = rte_eth_bond_primary_get(port_id);\n\tif (primary_id < 0) {\n\t\tprintf(\"\\tFailed to get primary slave for port = %d\\n\", port_id);\n\t\treturn;\n\t} else\n\t\tprintf(\"\\tPrimary: [%d]\\n\", primary_id);\n\n}\n\ncmdline_parse_token_string_t cmd_showbonding_config_show =\nTOKEN_STRING_INITIALIZER(struct cmd_show_bonding_config_result,\n\t\tshow, \"show\");\ncmdline_parse_token_string_t cmd_showbonding_config_bonding =\nTOKEN_STRING_INITIALIZER(struct cmd_show_bonding_config_result,\n\t\tbonding, \"bonding\");\ncmdline_parse_token_string_t cmd_showbonding_config_config =\nTOKEN_STRING_INITIALIZER(struct cmd_show_bonding_config_result,\n\t\tconfig, \"config\");\ncmdline_parse_token_num_t cmd_showbonding_config_port =\nTOKEN_NUM_INITIALIZER(struct cmd_show_bonding_config_result,\n\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_show_bonding_config = {\n\t\t.f = cmd_show_bonding_config_parsed,\n\t\t.help_str =\t\"show bonding config (port_id): Show the bonding config for port_id\",\n\t\t.data = NULL,\n\t\t.tokens = {\n\t\t\t\t(void *)&cmd_showbonding_config_show,\n\t\t\t\t(void *)&cmd_showbonding_config_bonding,\n\t\t\t\t(void *)&cmd_showbonding_config_config,\n\t\t\t\t(void *)&cmd_showbonding_config_port,\n\t\t\t\tNULL\n\t\t}\n};\n\n/* *** SET BONDING PRIMARY *** */\nstruct cmd_set_bonding_primary_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t bonding;\n\tcmdline_fixed_string_t primary;\n\tuint8_t slave_id;\n\tuint8_t port_id;\n};\n\nstatic void cmd_set_bonding_primary_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_bonding_primary_result *res = parsed_result;\n\tportid_t master_port_id = res->port_id;\n\tportid_t slave_port_id = res->slave_id;\n\n\t/* Set the primary slave for a bonded device. */\n\tif (0 != rte_eth_bond_primary_set(master_port_id, slave_port_id)) {\n\t\tprintf(\"\\t Failed to set primary slave for port = %d.\\n\",\n\t\t\t\tmaster_port_id);\n\t\treturn;\n\t}\n\tinit_port_config();\n}\n\ncmdline_parse_token_string_t cmd_setbonding_primary_set =\nTOKEN_STRING_INITIALIZER(struct cmd_set_bonding_primary_result,\n\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_setbonding_primary_bonding =\nTOKEN_STRING_INITIALIZER(struct cmd_set_bonding_primary_result,\n\t\tbonding, \"bonding\");\ncmdline_parse_token_string_t cmd_setbonding_primary_primary =\nTOKEN_STRING_INITIALIZER(struct cmd_set_bonding_primary_result,\n\t\tprimary, \"primary\");\ncmdline_parse_token_num_t cmd_setbonding_primary_slave =\nTOKEN_NUM_INITIALIZER(struct cmd_set_bonding_primary_result,\n\t\tslave_id, UINT8);\ncmdline_parse_token_num_t cmd_setbonding_primary_port =\nTOKEN_NUM_INITIALIZER(struct cmd_set_bonding_primary_result,\n\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_set_bonding_primary = {\n\t\t.f = cmd_set_bonding_primary_parsed,\n\t\t.help_str = \"set bonding primary (slave_id) (port_id): Set the primary slave for port_id\",\n\t\t.data = NULL,\n\t\t.tokens = {\n\t\t\t\t(void *)&cmd_setbonding_primary_set,\n\t\t\t\t(void *)&cmd_setbonding_primary_bonding,\n\t\t\t\t(void *)&cmd_setbonding_primary_primary,\n\t\t\t\t(void *)&cmd_setbonding_primary_slave,\n\t\t\t\t(void *)&cmd_setbonding_primary_port,\n\t\t\t\tNULL\n\t\t}\n};\n\n/* *** ADD SLAVE *** */\nstruct cmd_add_bonding_slave_result {\n\tcmdline_fixed_string_t add;\n\tcmdline_fixed_string_t bonding;\n\tcmdline_fixed_string_t slave;\n\tuint8_t slave_id;\n\tuint8_t port_id;\n};\n\nstatic void cmd_add_bonding_slave_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_add_bonding_slave_result *res = parsed_result;\n\tportid_t master_port_id = res->port_id;\n\tportid_t slave_port_id = res->slave_id;\n\n\t/* Set the primary slave for a bonded device. */\n\tif (0 != rte_eth_bond_slave_add(master_port_id, slave_port_id)) {\n\t\tprintf(\"\\t Failed to add slave %d to master port = %d.\\n\",\n\t\t\t\tslave_port_id, master_port_id);\n\t\treturn;\n\t}\n\tinit_port_config();\n\tset_port_slave_flag(slave_port_id);\n}\n\ncmdline_parse_token_string_t cmd_addbonding_slave_add =\nTOKEN_STRING_INITIALIZER(struct cmd_add_bonding_slave_result,\n\t\tadd, \"add\");\ncmdline_parse_token_string_t cmd_addbonding_slave_bonding =\nTOKEN_STRING_INITIALIZER(struct cmd_add_bonding_slave_result,\n\t\tbonding, \"bonding\");\ncmdline_parse_token_string_t cmd_addbonding_slave_slave =\nTOKEN_STRING_INITIALIZER(struct cmd_add_bonding_slave_result,\n\t\tslave, \"slave\");\ncmdline_parse_token_num_t cmd_addbonding_slave_slaveid =\nTOKEN_NUM_INITIALIZER(struct cmd_add_bonding_slave_result,\n\t\tslave_id, UINT8);\ncmdline_parse_token_num_t cmd_addbonding_slave_port =\nTOKEN_NUM_INITIALIZER(struct cmd_add_bonding_slave_result,\n\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_add_bonding_slave = {\n\t\t.f = cmd_add_bonding_slave_parsed,\n\t\t.help_str = \"add bonding slave (slave_id) (port_id): Add a slave device to a bonded device\",\n\t\t.data = NULL,\n\t\t.tokens = {\n\t\t\t\t(void *)&cmd_addbonding_slave_add,\n\t\t\t\t(void *)&cmd_addbonding_slave_bonding,\n\t\t\t\t(void *)&cmd_addbonding_slave_slave,\n\t\t\t\t(void *)&cmd_addbonding_slave_slaveid,\n\t\t\t\t(void *)&cmd_addbonding_slave_port,\n\t\t\t\tNULL\n\t\t}\n};\n\n/* *** REMOVE SLAVE *** */\nstruct cmd_remove_bonding_slave_result {\n\tcmdline_fixed_string_t remove;\n\tcmdline_fixed_string_t bonding;\n\tcmdline_fixed_string_t slave;\n\tuint8_t slave_id;\n\tuint8_t port_id;\n};\n\nstatic void cmd_remove_bonding_slave_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_remove_bonding_slave_result *res = parsed_result;\n\tportid_t master_port_id = res->port_id;\n\tportid_t slave_port_id = res->slave_id;\n\n\t/* Set the primary slave for a bonded device. */\n\tif (0 != rte_eth_bond_slave_remove(master_port_id, slave_port_id)) {\n\t\tprintf(\"\\t Failed to remove slave %d from master port = %d.\\n\",\n\t\t\t\tslave_port_id, master_port_id);\n\t\treturn;\n\t}\n\tinit_port_config();\n\tclear_port_slave_flag(slave_port_id);\n}\n\ncmdline_parse_token_string_t cmd_removebonding_slave_remove =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_remove_bonding_slave_result,\n\t\t\t\tremove, \"remove\");\ncmdline_parse_token_string_t cmd_removebonding_slave_bonding =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_remove_bonding_slave_result,\n\t\t\t\tbonding, \"bonding\");\ncmdline_parse_token_string_t cmd_removebonding_slave_slave =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_remove_bonding_slave_result,\n\t\t\t\tslave, \"slave\");\ncmdline_parse_token_num_t cmd_removebonding_slave_slaveid =\n\t\tTOKEN_NUM_INITIALIZER(struct cmd_remove_bonding_slave_result,\n\t\t\t\tslave_id, UINT8);\ncmdline_parse_token_num_t cmd_removebonding_slave_port =\n\t\tTOKEN_NUM_INITIALIZER(struct cmd_remove_bonding_slave_result,\n\t\t\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_remove_bonding_slave = {\n\t\t.f = cmd_remove_bonding_slave_parsed,\n\t\t.help_str = \"remove bonding slave (slave_id) (port_id): Remove a slave device from a bonded device\",\n\t\t.data = NULL,\n\t\t.tokens = {\n\t\t\t\t(void *)&cmd_removebonding_slave_remove,\n\t\t\t\t(void *)&cmd_removebonding_slave_bonding,\n\t\t\t\t(void *)&cmd_removebonding_slave_slave,\n\t\t\t\t(void *)&cmd_removebonding_slave_slaveid,\n\t\t\t\t(void *)&cmd_removebonding_slave_port,\n\t\t\t\tNULL\n\t\t}\n};\n\n/* *** CREATE BONDED DEVICE *** */\nstruct cmd_create_bonded_device_result {\n\tcmdline_fixed_string_t create;\n\tcmdline_fixed_string_t bonded;\n\tcmdline_fixed_string_t device;\n\tuint8_t mode;\n\tuint8_t socket;\n};\n\nstatic int bond_dev_num = 0;\n\nstatic void cmd_create_bonded_device_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_create_bonded_device_result *res = parsed_result;\n\tchar ethdev_name[RTE_ETH_NAME_MAX_LEN];\n\tint port_id;\n\n\tif (test_done == 0) {\n\t\tprintf(\"Please stop forwarding first\\n\");\n\t\treturn;\n\t}\n\n\tsnprintf(ethdev_name, RTE_ETH_NAME_MAX_LEN, \"eth_bond_testpmd_%d\",\n\t\t\tbond_dev_num++);\n\n\t/* Create a new bonded device. */\n\tport_id = rte_eth_bond_create(ethdev_name, res->mode, res->socket);\n\tif (port_id < 0) {\n\t\tprintf(\"\\t Failed to create bonded device.\\n\");\n\t\treturn;\n\t} else {\n\t\tprintf(\"Created new bonded device %s on (port %d).\\n\", ethdev_name,\n\t\t\t\tport_id);\n\n\t\t/* Update number of ports */\n\t\tnb_ports = rte_eth_dev_count();\n\t\treconfig(port_id, res->socket);\n\t\trte_eth_promiscuous_enable(port_id);\n\t\tports[port_id].enabled = 1;\n\t}\n\n}\n\ncmdline_parse_token_string_t cmd_createbonded_device_create =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_create_bonded_device_result,\n\t\t\t\tcreate, \"create\");\ncmdline_parse_token_string_t cmd_createbonded_device_bonded =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_create_bonded_device_result,\n\t\t\t\tbonded, \"bonded\");\ncmdline_parse_token_string_t cmd_createbonded_device_device =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_create_bonded_device_result,\n\t\t\t\tdevice, \"device\");\ncmdline_parse_token_num_t cmd_createbonded_device_mode =\n\t\tTOKEN_NUM_INITIALIZER(struct cmd_create_bonded_device_result,\n\t\t\t\tmode, UINT8);\ncmdline_parse_token_num_t cmd_createbonded_device_socket =\n\t\tTOKEN_NUM_INITIALIZER(struct cmd_create_bonded_device_result,\n\t\t\t\tsocket, UINT8);\n\ncmdline_parse_inst_t cmd_create_bonded_device = {\n\t\t.f = cmd_create_bonded_device_parsed,\n\t\t.help_str = \"create bonded device (mode) (socket): Create a new bonded device with specific bonding mode and socket\",\n\t\t.data = NULL,\n\t\t.tokens = {\n\t\t\t\t(void *)&cmd_createbonded_device_create,\n\t\t\t\t(void *)&cmd_createbonded_device_bonded,\n\t\t\t\t(void *)&cmd_createbonded_device_device,\n\t\t\t\t(void *)&cmd_createbonded_device_mode,\n\t\t\t\t(void *)&cmd_createbonded_device_socket,\n\t\t\t\tNULL\n\t\t}\n};\n\n/* *** SET MAC ADDRESS IN BONDED DEVICE *** */\nstruct cmd_set_bond_mac_addr_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t bonding;\n\tcmdline_fixed_string_t mac_addr;\n\tuint8_t port_num;\n\tstruct ether_addr address;\n};\n\nstatic void cmd_set_bond_mac_addr_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_bond_mac_addr_result *res = parsed_result;\n\tint ret;\n\n\tif (port_id_is_invalid(res->port_num, ENABLED_WARN))\n\t\treturn;\n\n\tret = rte_eth_bond_mac_address_set(res->port_num, &res->address);\n\n\t/* check the return value and print it if is < 0 */\n\tif (ret < 0)\n\t\tprintf(\"set_bond_mac_addr error: (%s)\\n\", strerror(-ret));\n}\n\ncmdline_parse_token_string_t cmd_set_bond_mac_addr_set =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_set_bond_mac_addr_result, set, \"set\");\ncmdline_parse_token_string_t cmd_set_bond_mac_addr_bonding =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_set_bond_mac_addr_result, bonding,\n\t\t\t\t\"bonding\");\ncmdline_parse_token_string_t cmd_set_bond_mac_addr_mac =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_set_bond_mac_addr_result, mac_addr,\n\t\t\t\t\"mac_addr\");\ncmdline_parse_token_num_t cmd_set_bond_mac_addr_portnum =\n\t\tTOKEN_NUM_INITIALIZER(struct cmd_set_bond_mac_addr_result, port_num, UINT8);\ncmdline_parse_token_etheraddr_t cmd_set_bond_mac_addr_addr =\n\t\tTOKEN_ETHERADDR_INITIALIZER(struct cmd_set_bond_mac_addr_result, address);\n\ncmdline_parse_inst_t cmd_set_bond_mac_addr = {\n\t\t.f = cmd_set_bond_mac_addr_parsed,\n\t\t.data = (void *) 0,\n\t\t.help_str = \"set bonding mac_addr (port_id) (address): \",\n\t\t.tokens = {\n\t\t\t\t(void *)&cmd_set_bond_mac_addr_set,\n\t\t\t\t(void *)&cmd_set_bond_mac_addr_bonding,\n\t\t\t\t(void *)&cmd_set_bond_mac_addr_mac,\n\t\t\t\t(void *)&cmd_set_bond_mac_addr_portnum,\n\t\t\t\t(void *)&cmd_set_bond_mac_addr_addr,\n\t\t\t\tNULL\n\t\t}\n};\n\n\n/* *** SET LINK STATUS MONITORING POLLING PERIOD ON BONDED DEVICE *** */\nstruct cmd_set_bond_mon_period_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t bonding;\n\tcmdline_fixed_string_t mon_period;\n\tuint8_t port_num;\n\tuint32_t period_ms;\n};\n\nstatic void cmd_set_bond_mon_period_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_bond_mon_period_result *res = parsed_result;\n\tint ret;\n\n\tif (res->port_num >= nb_ports) {\n\t\tprintf(\"Port id %d must be less than %d\\n\", res->port_num, nb_ports);\n\t\treturn;\n\t}\n\n\tret = rte_eth_bond_link_monitoring_set(res->port_num, res->period_ms);\n\n\t/* check the return value and print it if is < 0 */\n\tif (ret < 0)\n\t\tprintf(\"set_bond_mac_addr error: (%s)\\n\", strerror(-ret));\n}\n\ncmdline_parse_token_string_t cmd_set_bond_mon_period_set =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_set_bond_mon_period_result,\n\t\t\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_set_bond_mon_period_bonding =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_set_bond_mon_period_result,\n\t\t\t\tbonding, \"bonding\");\ncmdline_parse_token_string_t cmd_set_bond_mon_period_mon_period =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_set_bond_mon_period_result,\n\t\t\t\tmon_period,\t\"mon_period\");\ncmdline_parse_token_num_t cmd_set_bond_mon_period_portnum =\n\t\tTOKEN_NUM_INITIALIZER(struct cmd_set_bond_mon_period_result,\n\t\t\t\tport_num, UINT8);\ncmdline_parse_token_num_t cmd_set_bond_mon_period_period_ms =\n\t\tTOKEN_NUM_INITIALIZER(struct cmd_set_bond_mon_period_result,\n\t\t\t\tperiod_ms, UINT32);\n\ncmdline_parse_inst_t cmd_set_bond_mon_period = {\n\t\t.f = cmd_set_bond_mon_period_parsed,\n\t\t.data = (void *) 0,\n\t\t.help_str = \"set bonding mon_period (port_id) (period_ms): \",\n\t\t.tokens = {\n\t\t\t\t(void *)&cmd_set_bond_mon_period_set,\n\t\t\t\t(void *)&cmd_set_bond_mon_period_bonding,\n\t\t\t\t(void *)&cmd_set_bond_mon_period_mon_period,\n\t\t\t\t(void *)&cmd_set_bond_mon_period_portnum,\n\t\t\t\t(void *)&cmd_set_bond_mon_period_period_ms,\n\t\t\t\tNULL\n\t\t}\n};\n\n#endif /* RTE_LIBRTE_PMD_BOND */\n\n/* *** SET FORWARDING MODE *** */\nstruct cmd_set_fwd_mode_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t fwd;\n\tcmdline_fixed_string_t mode;\n};\n\nstatic void cmd_set_fwd_mode_parsed(void *parsed_result,\n\t\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_set_fwd_mode_result *res = parsed_result;\n\n\tset_pkt_forwarding_mode(res->mode);\n}\n\ncmdline_parse_token_string_t cmd_setfwd_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_fwd_mode_result, set, \"set\");\ncmdline_parse_token_string_t cmd_setfwd_fwd =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_fwd_mode_result, fwd, \"fwd\");\ncmdline_parse_token_string_t cmd_setfwd_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_fwd_mode_result, mode,\n\t\t\"\" /* defined at init */);\n\ncmdline_parse_inst_t cmd_set_fwd_mode = {\n\t.f = cmd_set_fwd_mode_parsed,\n\t.data = NULL,\n\t.help_str = NULL, /* defined at init */\n\t.tokens = {\n\t\t(void *)&cmd_setfwd_set,\n\t\t(void *)&cmd_setfwd_fwd,\n\t\t(void *)&cmd_setfwd_mode,\n\t\tNULL,\n\t},\n};\n\nstatic void cmd_set_fwd_mode_init(void)\n{\n\tchar *modes, *c;\n\tstatic char token[128];\n\tstatic char help[256];\n\tcmdline_parse_token_string_t *token_struct;\n\n\tmodes = list_pkt_forwarding_modes();\n\tsnprintf(help, sizeof help, \"set fwd %s - \"\n\t\t\"set packet forwarding mode\", modes);\n\tcmd_set_fwd_mode.help_str = help;\n\n\t/* string token separator is # */\n\tfor (c = token; *modes != '\\0'; modes++)\n\t\tif (*modes == '|')\n\t\t\t*c++ = '#';\n\t\telse\n\t\t\t*c++ = *modes;\n\ttoken_struct = (cmdline_parse_token_string_t*)cmd_set_fwd_mode.tokens[2];\n\ttoken_struct->string_data.str = token;\n}\n\n/* *** SET BURST TX DELAY TIME RETRY NUMBER *** */\nstruct cmd_set_burst_tx_retry_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t burst;\n\tcmdline_fixed_string_t tx;\n\tcmdline_fixed_string_t delay;\n\tuint32_t time;\n\tcmdline_fixed_string_t retry;\n\tuint32_t retry_num;\n};\n\nstatic void cmd_set_burst_tx_retry_parsed(void *parsed_result,\n\t\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_burst_tx_retry_result *res = parsed_result;\n\n\tif (!strcmp(res->set, \"set\") && !strcmp(res->burst, \"burst\")\n\t\t&& !strcmp(res->tx, \"tx\")) {\n\t\tif (!strcmp(res->delay, \"delay\"))\n\t\t\tburst_tx_delay_time = res->time;\n\t\tif (!strcmp(res->retry, \"retry\"))\n\t\t\tburst_tx_retry_num = res->retry_num;\n\t}\n\n}\n\ncmdline_parse_token_string_t cmd_set_burst_tx_retry_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_burst_tx_retry_result, set, \"set\");\ncmdline_parse_token_string_t cmd_set_burst_tx_retry_burst =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_burst_tx_retry_result, burst,\n\t\t\t\t \"burst\");\ncmdline_parse_token_string_t cmd_set_burst_tx_retry_tx =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_burst_tx_retry_result, tx, \"tx\");\ncmdline_parse_token_string_t cmd_set_burst_tx_retry_delay =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_burst_tx_retry_result, delay, \"delay\");\ncmdline_parse_token_num_t cmd_set_burst_tx_retry_time =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_burst_tx_retry_result, time, UINT32);\ncmdline_parse_token_string_t cmd_set_burst_tx_retry_retry =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_burst_tx_retry_result, retry, \"retry\");\ncmdline_parse_token_num_t cmd_set_burst_tx_retry_retry_num =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_burst_tx_retry_result, retry_num, UINT32);\n\ncmdline_parse_inst_t cmd_set_burst_tx_retry = {\n\t.f = cmd_set_burst_tx_retry_parsed,\n\t.help_str = \"set burst tx delay (time_by_useconds) retry (retry_num)\",\n\t.tokens = {\n\t\t(void *)&cmd_set_burst_tx_retry_set,\n\t\t(void *)&cmd_set_burst_tx_retry_burst,\n\t\t(void *)&cmd_set_burst_tx_retry_tx,\n\t\t(void *)&cmd_set_burst_tx_retry_delay,\n\t\t(void *)&cmd_set_burst_tx_retry_time,\n\t\t(void *)&cmd_set_burst_tx_retry_retry,\n\t\t(void *)&cmd_set_burst_tx_retry_retry_num,\n\t\tNULL,\n\t},\n};\n\n/* *** SET PROMISC MODE *** */\nstruct cmd_set_promisc_mode_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t promisc;\n\tcmdline_fixed_string_t port_all; /* valid if \"allports\" argument == 1 */\n\tuint8_t port_num; /* valid if \"allports\" argument == 0 */\n\tcmdline_fixed_string_t mode;\n};\n\nstatic void cmd_set_promisc_mode_parsed(void *parsed_result,\n\t\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t\tvoid *allports)\n{\n\tstruct cmd_set_promisc_mode_result *res = parsed_result;\n\tint enable;\n\tportid_t i;\n\n\tif (!strcmp(res->mode, \"on\"))\n\t\tenable = 1;\n\telse\n\t\tenable = 0;\n\n\t/* all ports */\n\tif (allports) {\n\t\tFOREACH_PORT(i, ports) {\n\t\t\tif (enable)\n\t\t\t\trte_eth_promiscuous_enable(i);\n\t\t\telse\n\t\t\t\trte_eth_promiscuous_disable(i);\n\t\t}\n\t}\n\telse {\n\t\tif (enable)\n\t\t\trte_eth_promiscuous_enable(res->port_num);\n\t\telse\n\t\t\trte_eth_promiscuous_disable(res->port_num);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_setpromisc_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_promisc_mode_result, set, \"set\");\ncmdline_parse_token_string_t cmd_setpromisc_promisc =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_promisc_mode_result, promisc,\n\t\t\t\t \"promisc\");\ncmdline_parse_token_string_t cmd_setpromisc_portall =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_promisc_mode_result, port_all,\n\t\t\t\t \"all\");\ncmdline_parse_token_num_t cmd_setpromisc_portnum =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_promisc_mode_result, port_num,\n\t\t\t UINT8);\ncmdline_parse_token_string_t cmd_setpromisc_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_promisc_mode_result, mode,\n\t\t\t\t \"on#off\");\n\ncmdline_parse_inst_t cmd_set_promisc_mode_all = {\n\t.f = cmd_set_promisc_mode_parsed,\n\t.data = (void *)1,\n\t.help_str = \"set promisc all on|off: set promisc mode for all ports\",\n\t.tokens = {\n\t\t(void *)&cmd_setpromisc_set,\n\t\t(void *)&cmd_setpromisc_promisc,\n\t\t(void *)&cmd_setpromisc_portall,\n\t\t(void *)&cmd_setpromisc_mode,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_set_promisc_mode_one = {\n\t.f = cmd_set_promisc_mode_parsed,\n\t.data = (void *)0,\n\t.help_str = \"set promisc X on|off: set promisc mode on port X\",\n\t.tokens = {\n\t\t(void *)&cmd_setpromisc_set,\n\t\t(void *)&cmd_setpromisc_promisc,\n\t\t(void *)&cmd_setpromisc_portnum,\n\t\t(void *)&cmd_setpromisc_mode,\n\t\tNULL,\n\t},\n};\n\n/* *** SET ALLMULTI MODE *** */\nstruct cmd_set_allmulti_mode_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t allmulti;\n\tcmdline_fixed_string_t port_all; /* valid if \"allports\" argument == 1 */\n\tuint8_t port_num; /* valid if \"allports\" argument == 0 */\n\tcmdline_fixed_string_t mode;\n};\n\nstatic void cmd_set_allmulti_mode_parsed(void *parsed_result,\n\t\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t\tvoid *allports)\n{\n\tstruct cmd_set_allmulti_mode_result *res = parsed_result;\n\tint enable;\n\tportid_t i;\n\n\tif (!strcmp(res->mode, \"on\"))\n\t\tenable = 1;\n\telse\n\t\tenable = 0;\n\n\t/* all ports */\n\tif (allports) {\n\t\tFOREACH_PORT(i, ports) {\n\t\t\tif (enable)\n\t\t\t\trte_eth_allmulticast_enable(i);\n\t\t\telse\n\t\t\t\trte_eth_allmulticast_disable(i);\n\t\t}\n\t}\n\telse {\n\t\tif (enable)\n\t\t\trte_eth_allmulticast_enable(res->port_num);\n\t\telse\n\t\t\trte_eth_allmulticast_disable(res->port_num);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_setallmulti_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_allmulti_mode_result, set, \"set\");\ncmdline_parse_token_string_t cmd_setallmulti_allmulti =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_allmulti_mode_result, allmulti,\n\t\t\t\t \"allmulti\");\ncmdline_parse_token_string_t cmd_setallmulti_portall =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_allmulti_mode_result, port_all,\n\t\t\t\t \"all\");\ncmdline_parse_token_num_t cmd_setallmulti_portnum =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_allmulti_mode_result, port_num,\n\t\t\t UINT8);\ncmdline_parse_token_string_t cmd_setallmulti_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_allmulti_mode_result, mode,\n\t\t\t\t \"on#off\");\n\ncmdline_parse_inst_t cmd_set_allmulti_mode_all = {\n\t.f = cmd_set_allmulti_mode_parsed,\n\t.data = (void *)1,\n\t.help_str = \"set allmulti all on|off: set allmulti mode for all ports\",\n\t.tokens = {\n\t\t(void *)&cmd_setallmulti_set,\n\t\t(void *)&cmd_setallmulti_allmulti,\n\t\t(void *)&cmd_setallmulti_portall,\n\t\t(void *)&cmd_setallmulti_mode,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_set_allmulti_mode_one = {\n\t.f = cmd_set_allmulti_mode_parsed,\n\t.data = (void *)0,\n\t.help_str = \"set allmulti X on|off: set allmulti mode on port X\",\n\t.tokens = {\n\t\t(void *)&cmd_setallmulti_set,\n\t\t(void *)&cmd_setallmulti_allmulti,\n\t\t(void *)&cmd_setallmulti_portnum,\n\t\t(void *)&cmd_setallmulti_mode,\n\t\tNULL,\n\t},\n};\n\n/* *** SETUP ETHERNET LINK FLOW CONTROL *** */\nstruct cmd_link_flow_ctrl_set_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t flow_ctrl;\n\tcmdline_fixed_string_t rx;\n\tcmdline_fixed_string_t rx_lfc_mode;\n\tcmdline_fixed_string_t tx;\n\tcmdline_fixed_string_t tx_lfc_mode;\n\tcmdline_fixed_string_t mac_ctrl_frame_fwd;\n\tcmdline_fixed_string_t mac_ctrl_frame_fwd_mode;\n\tcmdline_fixed_string_t autoneg_str;\n\tcmdline_fixed_string_t autoneg;\n\tcmdline_fixed_string_t hw_str;\n\tuint32_t high_water;\n\tcmdline_fixed_string_t lw_str;\n\tuint32_t low_water;\n\tcmdline_fixed_string_t pt_str;\n\tuint16_t pause_time;\n\tcmdline_fixed_string_t xon_str;\n\tuint16_t send_xon;\n\tuint8_t port_id;\n};\n\ncmdline_parse_token_string_t cmd_lfc_set_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_lfc_set_flow_ctrl =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\tflow_ctrl, \"flow_ctrl\");\ncmdline_parse_token_string_t cmd_lfc_set_rx =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\trx, \"rx\");\ncmdline_parse_token_string_t cmd_lfc_set_rx_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\trx_lfc_mode, \"on#off\");\ncmdline_parse_token_string_t cmd_lfc_set_tx =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\ttx, \"tx\");\ncmdline_parse_token_string_t cmd_lfc_set_tx_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\ttx_lfc_mode, \"on#off\");\ncmdline_parse_token_string_t cmd_lfc_set_high_water_str =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\thw_str, \"high_water\");\ncmdline_parse_token_num_t cmd_lfc_set_high_water =\n\tTOKEN_NUM_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\thigh_water, UINT32);\ncmdline_parse_token_string_t cmd_lfc_set_low_water_str =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\tlw_str, \"low_water\");\ncmdline_parse_token_num_t cmd_lfc_set_low_water =\n\tTOKEN_NUM_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\tlow_water, UINT32);\ncmdline_parse_token_string_t cmd_lfc_set_pause_time_str =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\tpt_str, \"pause_time\");\ncmdline_parse_token_num_t cmd_lfc_set_pause_time =\n\tTOKEN_NUM_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\tpause_time, UINT16);\ncmdline_parse_token_string_t cmd_lfc_set_send_xon_str =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\txon_str, \"send_xon\");\ncmdline_parse_token_num_t cmd_lfc_set_send_xon =\n\tTOKEN_NUM_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\tsend_xon, UINT16);\ncmdline_parse_token_string_t cmd_lfc_set_mac_ctrl_frame_fwd_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\tmac_ctrl_frame_fwd, \"mac_ctrl_frame_fwd\");\ncmdline_parse_token_string_t cmd_lfc_set_mac_ctrl_frame_fwd =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\tmac_ctrl_frame_fwd_mode, \"on#off\");\ncmdline_parse_token_string_t cmd_lfc_set_autoneg_str =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\tautoneg_str, \"autoneg\");\ncmdline_parse_token_string_t cmd_lfc_set_autoneg =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\tautoneg, \"on#off\");\ncmdline_parse_token_num_t cmd_lfc_set_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_link_flow_ctrl_set_result,\n\t\t\t\tport_id, UINT8);\n\n/* forward declaration */\nstatic void\ncmd_link_flow_ctrl_set_parsed(void *parsed_result, struct cmdline *cl,\n\t\t\t void *data);\n\ncmdline_parse_inst_t cmd_link_flow_control_set = {\n\t.f = cmd_link_flow_ctrl_set_parsed,\n\t.data = NULL,\n\t.help_str = \"Configure the Ethernet flow control: set flow_ctrl rx on|off \\\ntx on|off high_water low_water pause_time send_xon mac_ctrl_frame_fwd on|off \\\nautoneg on|off port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_lfc_set_set,\n\t\t(void *)&cmd_lfc_set_flow_ctrl,\n\t\t(void *)&cmd_lfc_set_rx,\n\t\t(void *)&cmd_lfc_set_rx_mode,\n\t\t(void *)&cmd_lfc_set_tx,\n\t\t(void *)&cmd_lfc_set_tx_mode,\n\t\t(void *)&cmd_lfc_set_high_water,\n\t\t(void *)&cmd_lfc_set_low_water,\n\t\t(void *)&cmd_lfc_set_pause_time,\n\t\t(void *)&cmd_lfc_set_send_xon,\n\t\t(void *)&cmd_lfc_set_mac_ctrl_frame_fwd_mode,\n\t\t(void *)&cmd_lfc_set_mac_ctrl_frame_fwd,\n\t\t(void *)&cmd_lfc_set_autoneg_str,\n\t\t(void *)&cmd_lfc_set_autoneg,\n\t\t(void *)&cmd_lfc_set_portid,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_link_flow_control_set_rx = {\n\t.f = cmd_link_flow_ctrl_set_parsed,\n\t.data = (void *)&cmd_link_flow_control_set_rx,\n\t.help_str = \"Change rx flow control parameter: set flow_ctrl \"\n\t\t \"rx on|off port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_lfc_set_set,\n\t\t(void *)&cmd_lfc_set_flow_ctrl,\n\t\t(void *)&cmd_lfc_set_rx,\n\t\t(void *)&cmd_lfc_set_rx_mode,\n\t\t(void *)&cmd_lfc_set_portid,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_link_flow_control_set_tx = {\n\t.f = cmd_link_flow_ctrl_set_parsed,\n\t.data = (void *)&cmd_link_flow_control_set_tx,\n\t.help_str = \"Change tx flow control parameter: set flow_ctrl \"\n\t\t \"tx on|off port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_lfc_set_set,\n\t\t(void *)&cmd_lfc_set_flow_ctrl,\n\t\t(void *)&cmd_lfc_set_tx,\n\t\t(void *)&cmd_lfc_set_tx_mode,\n\t\t(void *)&cmd_lfc_set_portid,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_link_flow_control_set_hw = {\n\t.f = cmd_link_flow_ctrl_set_parsed,\n\t.data = (void *)&cmd_link_flow_control_set_hw,\n\t.help_str = \"Change high water flow control parameter: set flow_ctrl \"\n\t\t \"high_water value port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_lfc_set_set,\n\t\t(void *)&cmd_lfc_set_flow_ctrl,\n\t\t(void *)&cmd_lfc_set_high_water_str,\n\t\t(void *)&cmd_lfc_set_high_water,\n\t\t(void *)&cmd_lfc_set_portid,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_link_flow_control_set_lw = {\n\t.f = cmd_link_flow_ctrl_set_parsed,\n\t.data = (void *)&cmd_link_flow_control_set_lw,\n\t.help_str = \"Change low water flow control parameter: set flow_ctrl \"\n\t\t \"low_water value port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_lfc_set_set,\n\t\t(void *)&cmd_lfc_set_flow_ctrl,\n\t\t(void *)&cmd_lfc_set_low_water_str,\n\t\t(void *)&cmd_lfc_set_low_water,\n\t\t(void *)&cmd_lfc_set_portid,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_link_flow_control_set_pt = {\n\t.f = cmd_link_flow_ctrl_set_parsed,\n\t.data = (void *)&cmd_link_flow_control_set_pt,\n\t.help_str = \"Change pause time flow control parameter: set flow_ctrl \"\n\t\t \"pause_time value port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_lfc_set_set,\n\t\t(void *)&cmd_lfc_set_flow_ctrl,\n\t\t(void *)&cmd_lfc_set_pause_time_str,\n\t\t(void *)&cmd_lfc_set_pause_time,\n\t\t(void *)&cmd_lfc_set_portid,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_link_flow_control_set_xon = {\n\t.f = cmd_link_flow_ctrl_set_parsed,\n\t.data = (void *)&cmd_link_flow_control_set_xon,\n\t.help_str = \"Change send_xon flow control parameter: set flow_ctrl \"\n\t\t \"send_xon value port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_lfc_set_set,\n\t\t(void *)&cmd_lfc_set_flow_ctrl,\n\t\t(void *)&cmd_lfc_set_send_xon_str,\n\t\t(void *)&cmd_lfc_set_send_xon,\n\t\t(void *)&cmd_lfc_set_portid,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_link_flow_control_set_macfwd = {\n\t.f = cmd_link_flow_ctrl_set_parsed,\n\t.data = (void *)&cmd_link_flow_control_set_macfwd,\n\t.help_str = \"Change mac ctrl fwd flow control parameter: set flow_ctrl \"\n\t\t \"mac_ctrl_frame_fwd on|off port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_lfc_set_set,\n\t\t(void *)&cmd_lfc_set_flow_ctrl,\n\t\t(void *)&cmd_lfc_set_mac_ctrl_frame_fwd_mode,\n\t\t(void *)&cmd_lfc_set_mac_ctrl_frame_fwd,\n\t\t(void *)&cmd_lfc_set_portid,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_link_flow_control_set_autoneg = {\n\t.f = cmd_link_flow_ctrl_set_parsed,\n\t.data = (void *)&cmd_link_flow_control_set_autoneg,\n\t.help_str = \"Change autoneg flow control parameter: set flow_ctrl \"\n\t\t \"autoneg on|off port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_lfc_set_set,\n\t\t(void *)&cmd_lfc_set_flow_ctrl,\n\t\t(void *)&cmd_lfc_set_autoneg_str,\n\t\t(void *)&cmd_lfc_set_autoneg,\n\t\t(void *)&cmd_lfc_set_portid,\n\t\tNULL,\n\t},\n};\n\nstatic void\ncmd_link_flow_ctrl_set_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t void *data)\n{\n\tstruct cmd_link_flow_ctrl_set_result *res = parsed_result;\n\tcmdline_parse_inst_t *cmd = data;\n\tstruct rte_eth_fc_conf fc_conf;\n\tint rx_fc_en = 0;\n\tint tx_fc_en = 0;\n\tint ret;\n\n\t/*\n\t * Rx on/off, flow control is enabled/disabled on RX side. This can indicate\n\t * the RTE_FC_TX_PAUSE, Transmit pause frame at the Rx side.\n\t * Tx on/off, flow control is enabled/disabled on TX side. This can indicate\n\t * the RTE_FC_RX_PAUSE, Respond to the pause frame at the Tx side.\n\t */\n\tstatic enum rte_eth_fc_mode rx_tx_onoff_2_lfc_mode[2][2] = {\n\t\t\t{RTE_FC_NONE, RTE_FC_TX_PAUSE}, {RTE_FC_RX_PAUSE, RTE_FC_FULL}\n\t};\n\n\t/* Partial command line, retrieve current configuration */\n\tif (cmd) {\n\t\tret = rte_eth_dev_flow_ctrl_get(res->port_id, &fc_conf);\n\t\tif (ret != 0) {\n\t\t\tprintf(\"cannot get current flow ctrl parameters, return\"\n\t\t\t \"code = %d\\n\", ret);\n\t\t\treturn;\n\t\t}\n\n\t\tif ((fc_conf.mode == RTE_FC_RX_PAUSE) ||\n\t\t (fc_conf.mode == RTE_FC_FULL))\n\t\t\trx_fc_en = 1;\n\t\tif ((fc_conf.mode == RTE_FC_TX_PAUSE) ||\n\t\t (fc_conf.mode == RTE_FC_FULL))\n\t\t\ttx_fc_en = 1;\n\t}\n\n\tif (!cmd || cmd == &cmd_link_flow_control_set_rx)\n\t\trx_fc_en = (!strcmp(res->rx_lfc_mode, \"on\")) ? 1 : 0;\n\n\tif (!cmd || cmd == &cmd_link_flow_control_set_tx)\n\t\ttx_fc_en = (!strcmp(res->tx_lfc_mode, \"on\")) ? 1 : 0;\n\n\tfc_conf.mode = rx_tx_onoff_2_lfc_mode[rx_fc_en][tx_fc_en];\n\n\tif (!cmd || cmd == &cmd_link_flow_control_set_hw)\n\t\tfc_conf.high_water = res->high_water;\n\n\tif (!cmd || cmd == &cmd_link_flow_control_set_lw)\n\t\tfc_conf.low_water = res->low_water;\n\n\tif (!cmd || cmd == &cmd_link_flow_control_set_pt)\n\t\tfc_conf.pause_time = res->pause_time;\n\n\tif (!cmd || cmd == &cmd_link_flow_control_set_xon)\n\t\tfc_conf.send_xon = res->send_xon;\n\n\tif (!cmd || cmd == &cmd_link_flow_control_set_macfwd) {\n\t\tif (!strcmp(res->mac_ctrl_frame_fwd_mode, \"on\"))\n\t\t\tfc_conf.mac_ctrl_frame_fwd = 1;\n\t\telse\n\t\t\tfc_conf.mac_ctrl_frame_fwd = 0;\n\t}\n\n\tif (!cmd || cmd == &cmd_link_flow_control_set_autoneg)\n\t\tfc_conf.autoneg = (!strcmp(res->autoneg, \"on\")) ? 1 : 0;\n\n\tret = rte_eth_dev_flow_ctrl_set(res->port_id, &fc_conf);\n\tif (ret != 0)\n\t\tprintf(\"bad flow contrl parameter, return code = %d \\n\", ret);\n}\n\n/* *** SETUP ETHERNET PIRORITY FLOW CONTROL *** */\nstruct cmd_priority_flow_ctrl_set_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t pfc_ctrl;\n\tcmdline_fixed_string_t rx;\n\tcmdline_fixed_string_t rx_pfc_mode;\n\tcmdline_fixed_string_t tx;\n\tcmdline_fixed_string_t tx_pfc_mode;\n\tuint32_t high_water;\n\tuint32_t low_water;\n\tuint16_t pause_time;\n\tuint8_t priority;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_priority_flow_ctrl_set_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_priority_flow_ctrl_set_result *res = parsed_result;\n\tstruct rte_eth_pfc_conf pfc_conf;\n\tint rx_fc_enable, tx_fc_enable;\n\tint ret;\n\n\t/*\n\t * Rx on/off, flow control is enabled/disabled on RX side. This can indicate\n\t * the RTE_FC_TX_PAUSE, Transmit pause frame at the Rx side.\n\t * Tx on/off, flow control is enabled/disabled on TX side. This can indicate\n\t * the RTE_FC_RX_PAUSE, Respond to the pause frame at the Tx side.\n\t */\n\tstatic enum rte_eth_fc_mode rx_tx_onoff_2_pfc_mode[2][2] = {\n\t\t\t{RTE_FC_NONE, RTE_FC_RX_PAUSE}, {RTE_FC_TX_PAUSE, RTE_FC_FULL}\n\t};\n\n\trx_fc_enable = (!strncmp(res->rx_pfc_mode, \"on\",2)) ? 1 : 0;\n\ttx_fc_enable = (!strncmp(res->tx_pfc_mode, \"on\",2)) ? 1 : 0;\n\tpfc_conf.fc.mode = rx_tx_onoff_2_pfc_mode[rx_fc_enable][tx_fc_enable];\n\tpfc_conf.fc.high_water = res->high_water;\n\tpfc_conf.fc.low_water = res->low_water;\n\tpfc_conf.fc.pause_time = res->pause_time;\n\tpfc_conf.priority = res->priority;\n\n\tret = rte_eth_dev_priority_flow_ctrl_set(res->port_id, &pfc_conf);\n\tif (ret != 0)\n\t\tprintf(\"bad priority flow contrl parameter, return code = %d \\n\", ret);\n}\n\ncmdline_parse_token_string_t cmd_pfc_set_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_priority_flow_ctrl_set_result,\n\t\t\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_pfc_set_flow_ctrl =\n\tTOKEN_STRING_INITIALIZER(struct cmd_priority_flow_ctrl_set_result,\n\t\t\t\tpfc_ctrl, \"pfc_ctrl\");\ncmdline_parse_token_string_t cmd_pfc_set_rx =\n\tTOKEN_STRING_INITIALIZER(struct cmd_priority_flow_ctrl_set_result,\n\t\t\t\trx, \"rx\");\ncmdline_parse_token_string_t cmd_pfc_set_rx_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_priority_flow_ctrl_set_result,\n\t\t\t\trx_pfc_mode, \"on#off\");\ncmdline_parse_token_string_t cmd_pfc_set_tx =\n\tTOKEN_STRING_INITIALIZER(struct cmd_priority_flow_ctrl_set_result,\n\t\t\t\ttx, \"tx\");\ncmdline_parse_token_string_t cmd_pfc_set_tx_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_priority_flow_ctrl_set_result,\n\t\t\t\ttx_pfc_mode, \"on#off\");\ncmdline_parse_token_num_t cmd_pfc_set_high_water =\n\tTOKEN_NUM_INITIALIZER(struct cmd_priority_flow_ctrl_set_result,\n\t\t\t\thigh_water, UINT32);\ncmdline_parse_token_num_t cmd_pfc_set_low_water =\n\tTOKEN_NUM_INITIALIZER(struct cmd_priority_flow_ctrl_set_result,\n\t\t\t\tlow_water, UINT32);\ncmdline_parse_token_num_t cmd_pfc_set_pause_time =\n\tTOKEN_NUM_INITIALIZER(struct cmd_priority_flow_ctrl_set_result,\n\t\t\t\tpause_time, UINT16);\ncmdline_parse_token_num_t cmd_pfc_set_priority =\n\tTOKEN_NUM_INITIALIZER(struct cmd_priority_flow_ctrl_set_result,\n\t\t\t\tpriority, UINT8);\ncmdline_parse_token_num_t cmd_pfc_set_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_priority_flow_ctrl_set_result,\n\t\t\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_priority_flow_control_set = {\n\t.f = cmd_priority_flow_ctrl_set_parsed,\n\t.data = NULL,\n\t.help_str = \"Configure the Ethernet priority flow control: set pfc_ctrl rx on|off\\n\\\n\t\t\ttx on|off high_water low_water pause_time priority port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_pfc_set_set,\n\t\t(void *)&cmd_pfc_set_flow_ctrl,\n\t\t(void *)&cmd_pfc_set_rx,\n\t\t(void *)&cmd_pfc_set_rx_mode,\n\t\t(void *)&cmd_pfc_set_tx,\n\t\t(void *)&cmd_pfc_set_tx_mode,\n\t\t(void *)&cmd_pfc_set_high_water,\n\t\t(void *)&cmd_pfc_set_low_water,\n\t\t(void *)&cmd_pfc_set_pause_time,\n\t\t(void *)&cmd_pfc_set_priority,\n\t\t(void *)&cmd_pfc_set_portid,\n\t\tNULL,\n\t},\n};\n\n/* *** RESET CONFIGURATION *** */\nstruct cmd_reset_result {\n\tcmdline_fixed_string_t reset;\n\tcmdline_fixed_string_t def;\n};\n\nstatic void cmd_reset_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tcmdline_printf(cl, \"Reset to default forwarding configuration...\\n\");\n\tset_def_fwd_config();\n}\n\ncmdline_parse_token_string_t cmd_reset_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_reset_result, reset, \"set\");\ncmdline_parse_token_string_t cmd_reset_def =\n\tTOKEN_STRING_INITIALIZER(struct cmd_reset_result, def,\n\t\t\t\t \"default\");\n\ncmdline_parse_inst_t cmd_reset = {\n\t.f = cmd_reset_parsed,\n\t.data = NULL,\n\t.help_str = \"set default: reset default forwarding configuration\",\n\t.tokens = {\n\t\t(void *)&cmd_reset_set,\n\t\t(void *)&cmd_reset_def,\n\t\tNULL,\n\t},\n};\n\n/* *** START FORWARDING *** */\nstruct cmd_start_result {\n\tcmdline_fixed_string_t start;\n};\n\ncmdline_parse_token_string_t cmd_start_start =\n\tTOKEN_STRING_INITIALIZER(struct cmd_start_result, start, \"start\");\n\nstatic void cmd_start_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstart_packet_forwarding(0);\n}\n\ncmdline_parse_inst_t cmd_start = {\n\t.f = cmd_start_parsed,\n\t.data = NULL,\n\t.help_str = \"start packet forwarding\",\n\t.tokens = {\n\t\t(void *)&cmd_start_start,\n\t\tNULL,\n\t},\n};\n\n/* *** START FORWARDING WITH ONE TX BURST FIRST *** */\nstruct cmd_start_tx_first_result {\n\tcmdline_fixed_string_t start;\n\tcmdline_fixed_string_t tx_first;\n};\n\nstatic void\ncmd_start_tx_first_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstart_packet_forwarding(1);\n}\n\ncmdline_parse_token_string_t cmd_start_tx_first_start =\n\tTOKEN_STRING_INITIALIZER(struct cmd_start_tx_first_result, start,\n\t\t\t\t \"start\");\ncmdline_parse_token_string_t cmd_start_tx_first_tx_first =\n\tTOKEN_STRING_INITIALIZER(struct cmd_start_tx_first_result,\n\t\t\t\t tx_first, \"tx_first\");\n\ncmdline_parse_inst_t cmd_start_tx_first = {\n\t.f = cmd_start_tx_first_parsed,\n\t.data = NULL,\n\t.help_str = \"start packet forwarding, after sending 1 burst of packets\",\n\t.tokens = {\n\t\t(void *)&cmd_start_tx_first_start,\n\t\t(void *)&cmd_start_tx_first_tx_first,\n\t\tNULL,\n\t},\n};\n\n/* *** SET LINK UP *** */\nstruct cmd_set_link_up_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t link_up;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n};\n\ncmdline_parse_token_string_t cmd_set_link_up_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_link_up_result, set, \"set\");\ncmdline_parse_token_string_t cmd_set_link_up_link_up =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_link_up_result, link_up,\n\t\t\t\t\"link-up\");\ncmdline_parse_token_string_t cmd_set_link_up_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_link_up_result, port, \"port\");\ncmdline_parse_token_num_t cmd_set_link_up_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_link_up_result, port_id, UINT8);\n\nstatic void cmd_set_link_up_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_set_link_up_result *res = parsed_result;\n\tdev_set_link_up(res->port_id);\n}\n\ncmdline_parse_inst_t cmd_set_link_up = {\n\t.f = cmd_set_link_up_parsed,\n\t.data = NULL,\n\t.help_str = \"set link-up port (port id)\",\n\t.tokens = {\n\t\t(void *)&cmd_set_link_up_set,\n\t\t(void *)&cmd_set_link_up_link_up,\n\t\t(void *)&cmd_set_link_up_port,\n\t\t(void *)&cmd_set_link_up_port_id,\n\t\tNULL,\n\t},\n};\n\n/* *** SET LINK DOWN *** */\nstruct cmd_set_link_down_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t link_down;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n};\n\ncmdline_parse_token_string_t cmd_set_link_down_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_link_down_result, set, \"set\");\ncmdline_parse_token_string_t cmd_set_link_down_link_down =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_link_down_result, link_down,\n\t\t\t\t\"link-down\");\ncmdline_parse_token_string_t cmd_set_link_down_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_link_down_result, port, \"port\");\ncmdline_parse_token_num_t cmd_set_link_down_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_link_down_result, port_id, UINT8);\n\nstatic void cmd_set_link_down_parsed(\n\t\t\t\t__attribute__((unused)) void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_link_down_result *res = parsed_result;\n\tdev_set_link_down(res->port_id);\n}\n\ncmdline_parse_inst_t cmd_set_link_down = {\n\t.f = cmd_set_link_down_parsed,\n\t.data = NULL,\n\t.help_str = \"set link-down port (port id)\",\n\t.tokens = {\n\t\t(void *)&cmd_set_link_down_set,\n\t\t(void *)&cmd_set_link_down_link_down,\n\t\t(void *)&cmd_set_link_down_port,\n\t\t(void *)&cmd_set_link_down_port_id,\n\t\tNULL,\n\t},\n};\n\n/* *** SHOW CFG *** */\nstruct cmd_showcfg_result {\n\tcmdline_fixed_string_t show;\n\tcmdline_fixed_string_t cfg;\n\tcmdline_fixed_string_t what;\n};\n\nstatic void cmd_showcfg_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_showcfg_result *res = parsed_result;\n\tif (!strcmp(res->what, \"rxtx\"))\n\t\trxtx_config_display();\n\telse if (!strcmp(res->what, \"cores\"))\n\t\tfwd_lcores_config_display();\n\telse if (!strcmp(res->what, \"fwd\"))\n\t\tfwd_config_display();\n}\n\ncmdline_parse_token_string_t cmd_showcfg_show =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showcfg_result, show, \"show\");\ncmdline_parse_token_string_t cmd_showcfg_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showcfg_result, cfg, \"config\");\ncmdline_parse_token_string_t cmd_showcfg_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showcfg_result, what,\n\t\t\t\t \"rxtx#cores#fwd\");\n\ncmdline_parse_inst_t cmd_showcfg = {\n\t.f = cmd_showcfg_parsed,\n\t.data = NULL,\n\t.help_str = \"show config rxtx|cores|fwd\",\n\t.tokens = {\n\t\t(void *)&cmd_showcfg_show,\n\t\t(void *)&cmd_showcfg_port,\n\t\t(void *)&cmd_showcfg_what,\n\t\tNULL,\n\t},\n};\n\n/* *** SHOW ALL PORT INFO *** */\nstruct cmd_showportall_result {\n\tcmdline_fixed_string_t show;\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t what;\n\tcmdline_fixed_string_t all;\n};\n\nstatic void cmd_showportall_parsed(void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tportid_t i;\n\n\tstruct cmd_showportall_result *res = parsed_result;\n\tif (!strcmp(res->show, \"clear\")) {\n\t\tif (!strcmp(res->what, \"stats\"))\n\t\t\tFOREACH_PORT(i, ports)\n\t\t\t\tnic_stats_clear(i);\n\t\telse if (!strcmp(res->what, \"xstats\"))\n\t\t\tFOREACH_PORT(i, ports)\n\t\t\t\tnic_xstats_clear(i);\n\t} else if (!strcmp(res->what, \"info\"))\n\t\tFOREACH_PORT(i, ports)\n\t\t\tport_infos_display(i);\n\telse if (!strcmp(res->what, \"stats\"))\n\t\tFOREACH_PORT(i, ports)\n\t\t\tnic_stats_display(i);\n\telse if (!strcmp(res->what, \"xstats\"))\n\t\tFOREACH_PORT(i, ports)\n\t\t\tnic_xstats_display(i);\n\telse if (!strcmp(res->what, \"fdir\"))\n\t\tFOREACH_PORT(i, ports)\n\t\t\tfdir_get_infos(i);\n\telse if (!strcmp(res->what, \"stat_qmap\"))\n\t\tFOREACH_PORT(i, ports)\n\t\t\tnic_stats_mapping_display(i);\n}\n\ncmdline_parse_token_string_t cmd_showportall_show =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showportall_result, show,\n\t\t\t\t \"show#clear\");\ncmdline_parse_token_string_t cmd_showportall_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showportall_result, port, \"port\");\ncmdline_parse_token_string_t cmd_showportall_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showportall_result, what,\n\t\t\t\t \"info#stats#xstats#fdir#stat_qmap\");\ncmdline_parse_token_string_t cmd_showportall_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showportall_result, all, \"all\");\ncmdline_parse_inst_t cmd_showportall = {\n\t.f = cmd_showportall_parsed,\n\t.data = NULL,\n\t.help_str = \"show|clear port info|stats|xstats|fdir|stat_qmap all\",\n\t.tokens = {\n\t\t(void *)&cmd_showportall_show,\n\t\t(void *)&cmd_showportall_port,\n\t\t(void *)&cmd_showportall_what,\n\t\t(void *)&cmd_showportall_all,\n\t\tNULL,\n\t},\n};\n\n/* *** SHOW PORT INFO *** */\nstruct cmd_showport_result {\n\tcmdline_fixed_string_t show;\n\tcmdline_fixed_string_t port;\n\tcmdline_fixed_string_t what;\n\tuint8_t portnum;\n};\n\nstatic void cmd_showport_parsed(void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_showport_result *res = parsed_result;\n\tif (!strcmp(res->show, \"clear\")) {\n\t\tif (!strcmp(res->what, \"stats\"))\n\t\t\tnic_stats_clear(res->portnum);\n\t\telse if (!strcmp(res->what, \"xstats\"))\n\t\t\tnic_xstats_clear(res->portnum);\n\t} else if (!strcmp(res->what, \"info\"))\n\t\tport_infos_display(res->portnum);\n\telse if (!strcmp(res->what, \"stats\"))\n\t\tnic_stats_display(res->portnum);\n\telse if (!strcmp(res->what, \"xstats\"))\n\t\tnic_xstats_display(res->portnum);\n\telse if (!strcmp(res->what, \"fdir\"))\n\t\t fdir_get_infos(res->portnum);\n\telse if (!strcmp(res->what, \"stat_qmap\"))\n\t\tnic_stats_mapping_display(res->portnum);\n}\n\ncmdline_parse_token_string_t cmd_showport_show =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showport_result, show,\n\t\t\t\t \"show#clear\");\ncmdline_parse_token_string_t cmd_showport_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showport_result, port, \"port\");\ncmdline_parse_token_string_t cmd_showport_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_showport_result, what,\n\t\t\t\t \"info#stats#xstats#fdir#stat_qmap\");\ncmdline_parse_token_num_t cmd_showport_portnum =\n\tTOKEN_NUM_INITIALIZER(struct cmd_showport_result, portnum, UINT8);\n\ncmdline_parse_inst_t cmd_showport = {\n\t.f = cmd_showport_parsed,\n\t.data = NULL,\n\t.help_str = \"show|clear port info|stats|xstats|fdir|stat_qmap X (X = port number)\",\n\t.tokens = {\n\t\t(void *)&cmd_showport_show,\n\t\t(void *)&cmd_showport_port,\n\t\t(void *)&cmd_showport_what,\n\t\t(void *)&cmd_showport_portnum,\n\t\tNULL,\n\t},\n};\n\n/* *** READ PORT REGISTER *** */\nstruct cmd_read_reg_result {\n\tcmdline_fixed_string_t read;\n\tcmdline_fixed_string_t reg;\n\tuint8_t port_id;\n\tuint32_t reg_off;\n};\n\nstatic void\ncmd_read_reg_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_read_reg_result *res = parsed_result;\n\tport_reg_display(res->port_id, res->reg_off);\n}\n\ncmdline_parse_token_string_t cmd_read_reg_read =\n\tTOKEN_STRING_INITIALIZER(struct cmd_read_reg_result, read, \"read\");\ncmdline_parse_token_string_t cmd_read_reg_reg =\n\tTOKEN_STRING_INITIALIZER(struct cmd_read_reg_result, reg, \"reg\");\ncmdline_parse_token_num_t cmd_read_reg_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_read_reg_result, port_id, UINT8);\ncmdline_parse_token_num_t cmd_read_reg_reg_off =\n\tTOKEN_NUM_INITIALIZER(struct cmd_read_reg_result, reg_off, UINT32);\n\ncmdline_parse_inst_t cmd_read_reg = {\n\t.f = cmd_read_reg_parsed,\n\t.data = NULL,\n\t.help_str = \"read reg port_id reg_off\",\n\t.tokens = {\n\t\t(void *)&cmd_read_reg_read,\n\t\t(void *)&cmd_read_reg_reg,\n\t\t(void *)&cmd_read_reg_port_id,\n\t\t(void *)&cmd_read_reg_reg_off,\n\t\tNULL,\n\t},\n};\n\n/* *** READ PORT REGISTER BIT FIELD *** */\nstruct cmd_read_reg_bit_field_result {\n\tcmdline_fixed_string_t read;\n\tcmdline_fixed_string_t regfield;\n\tuint8_t port_id;\n\tuint32_t reg_off;\n\tuint8_t bit1_pos;\n\tuint8_t bit2_pos;\n};\n\nstatic void\ncmd_read_reg_bit_field_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_read_reg_bit_field_result *res = parsed_result;\n\tport_reg_bit_field_display(res->port_id, res->reg_off,\n\t\t\t\t res->bit1_pos, res->bit2_pos);\n}\n\ncmdline_parse_token_string_t cmd_read_reg_bit_field_read =\n\tTOKEN_STRING_INITIALIZER(struct cmd_read_reg_bit_field_result, read,\n\t\t\t\t \"read\");\ncmdline_parse_token_string_t cmd_read_reg_bit_field_regfield =\n\tTOKEN_STRING_INITIALIZER(struct cmd_read_reg_bit_field_result,\n\t\t\t\t regfield, \"regfield\");\ncmdline_parse_token_num_t cmd_read_reg_bit_field_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_read_reg_bit_field_result, port_id,\n\t\t\t UINT8);\ncmdline_parse_token_num_t cmd_read_reg_bit_field_reg_off =\n\tTOKEN_NUM_INITIALIZER(struct cmd_read_reg_bit_field_result, reg_off,\n\t\t\t UINT32);\ncmdline_parse_token_num_t cmd_read_reg_bit_field_bit1_pos =\n\tTOKEN_NUM_INITIALIZER(struct cmd_read_reg_bit_field_result, bit1_pos,\n\t\t\t UINT8);\ncmdline_parse_token_num_t cmd_read_reg_bit_field_bit2_pos =\n\tTOKEN_NUM_INITIALIZER(struct cmd_read_reg_bit_field_result, bit2_pos,\n\t\t\t UINT8);\n\ncmdline_parse_inst_t cmd_read_reg_bit_field = {\n\t.f = cmd_read_reg_bit_field_parsed,\n\t.data = NULL,\n\t.help_str = \"read regfield port_id reg_off bit_x bit_y \"\n\t\"(read register bit field between bit_x and bit_y included)\",\n\t.tokens = {\n\t\t(void *)&cmd_read_reg_bit_field_read,\n\t\t(void *)&cmd_read_reg_bit_field_regfield,\n\t\t(void *)&cmd_read_reg_bit_field_port_id,\n\t\t(void *)&cmd_read_reg_bit_field_reg_off,\n\t\t(void *)&cmd_read_reg_bit_field_bit1_pos,\n\t\t(void *)&cmd_read_reg_bit_field_bit2_pos,\n\t\tNULL,\n\t},\n};\n\n/* *** READ PORT REGISTER BIT *** */\nstruct cmd_read_reg_bit_result {\n\tcmdline_fixed_string_t read;\n\tcmdline_fixed_string_t regbit;\n\tuint8_t port_id;\n\tuint32_t reg_off;\n\tuint8_t bit_pos;\n};\n\nstatic void\ncmd_read_reg_bit_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_read_reg_bit_result *res = parsed_result;\n\tport_reg_bit_display(res->port_id, res->reg_off, res->bit_pos);\n}\n\ncmdline_parse_token_string_t cmd_read_reg_bit_read =\n\tTOKEN_STRING_INITIALIZER(struct cmd_read_reg_bit_result, read, \"read\");\ncmdline_parse_token_string_t cmd_read_reg_bit_regbit =\n\tTOKEN_STRING_INITIALIZER(struct cmd_read_reg_bit_result,\n\t\t\t\t regbit, \"regbit\");\ncmdline_parse_token_num_t cmd_read_reg_bit_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_read_reg_bit_result, port_id, UINT8);\ncmdline_parse_token_num_t cmd_read_reg_bit_reg_off =\n\tTOKEN_NUM_INITIALIZER(struct cmd_read_reg_bit_result, reg_off, UINT32);\ncmdline_parse_token_num_t cmd_read_reg_bit_bit_pos =\n\tTOKEN_NUM_INITIALIZER(struct cmd_read_reg_bit_result, bit_pos, UINT8);\n\ncmdline_parse_inst_t cmd_read_reg_bit = {\n\t.f = cmd_read_reg_bit_parsed,\n\t.data = NULL,\n\t.help_str = \"read regbit port_id reg_off bit_x (0 <= bit_x <= 31)\",\n\t.tokens = {\n\t\t(void *)&cmd_read_reg_bit_read,\n\t\t(void *)&cmd_read_reg_bit_regbit,\n\t\t(void *)&cmd_read_reg_bit_port_id,\n\t\t(void *)&cmd_read_reg_bit_reg_off,\n\t\t(void *)&cmd_read_reg_bit_bit_pos,\n\t\tNULL,\n\t},\n};\n\n/* *** WRITE PORT REGISTER *** */\nstruct cmd_write_reg_result {\n\tcmdline_fixed_string_t write;\n\tcmdline_fixed_string_t reg;\n\tuint8_t port_id;\n\tuint32_t reg_off;\n\tuint32_t value;\n};\n\nstatic void\ncmd_write_reg_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_write_reg_result *res = parsed_result;\n\tport_reg_set(res->port_id, res->reg_off, res->value);\n}\n\ncmdline_parse_token_string_t cmd_write_reg_write =\n\tTOKEN_STRING_INITIALIZER(struct cmd_write_reg_result, write, \"write\");\ncmdline_parse_token_string_t cmd_write_reg_reg =\n\tTOKEN_STRING_INITIALIZER(struct cmd_write_reg_result, reg, \"reg\");\ncmdline_parse_token_num_t cmd_write_reg_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_write_reg_result, port_id, UINT8);\ncmdline_parse_token_num_t cmd_write_reg_reg_off =\n\tTOKEN_NUM_INITIALIZER(struct cmd_write_reg_result, reg_off, UINT32);\ncmdline_parse_token_num_t cmd_write_reg_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_write_reg_result, value, UINT32);\n\ncmdline_parse_inst_t cmd_write_reg = {\n\t.f = cmd_write_reg_parsed,\n\t.data = NULL,\n\t.help_str = \"write reg port_id reg_off reg_value\",\n\t.tokens = {\n\t\t(void *)&cmd_write_reg_write,\n\t\t(void *)&cmd_write_reg_reg,\n\t\t(void *)&cmd_write_reg_port_id,\n\t\t(void *)&cmd_write_reg_reg_off,\n\t\t(void *)&cmd_write_reg_value,\n\t\tNULL,\n\t},\n};\n\n/* *** WRITE PORT REGISTER BIT FIELD *** */\nstruct cmd_write_reg_bit_field_result {\n\tcmdline_fixed_string_t write;\n\tcmdline_fixed_string_t regfield;\n\tuint8_t port_id;\n\tuint32_t reg_off;\n\tuint8_t bit1_pos;\n\tuint8_t bit2_pos;\n\tuint32_t value;\n};\n\nstatic void\ncmd_write_reg_bit_field_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_write_reg_bit_field_result *res = parsed_result;\n\tport_reg_bit_field_set(res->port_id, res->reg_off,\n\t\t\t res->bit1_pos, res->bit2_pos, res->value);\n}\n\ncmdline_parse_token_string_t cmd_write_reg_bit_field_write =\n\tTOKEN_STRING_INITIALIZER(struct cmd_write_reg_bit_field_result, write,\n\t\t\t\t \"write\");\ncmdline_parse_token_string_t cmd_write_reg_bit_field_regfield =\n\tTOKEN_STRING_INITIALIZER(struct cmd_write_reg_bit_field_result,\n\t\t\t\t regfield, \"regfield\");\ncmdline_parse_token_num_t cmd_write_reg_bit_field_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_write_reg_bit_field_result, port_id,\n\t\t\t UINT8);\ncmdline_parse_token_num_t cmd_write_reg_bit_field_reg_off =\n\tTOKEN_NUM_INITIALIZER(struct cmd_write_reg_bit_field_result, reg_off,\n\t\t\t UINT32);\ncmdline_parse_token_num_t cmd_write_reg_bit_field_bit1_pos =\n\tTOKEN_NUM_INITIALIZER(struct cmd_write_reg_bit_field_result, bit1_pos,\n\t\t\t UINT8);\ncmdline_parse_token_num_t cmd_write_reg_bit_field_bit2_pos =\n\tTOKEN_NUM_INITIALIZER(struct cmd_write_reg_bit_field_result, bit2_pos,\n\t\t\t UINT8);\ncmdline_parse_token_num_t cmd_write_reg_bit_field_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_write_reg_bit_field_result, value,\n\t\t\t UINT32);\n\ncmdline_parse_inst_t cmd_write_reg_bit_field = {\n\t.f = cmd_write_reg_bit_field_parsed,\n\t.data = NULL,\n\t.help_str = \"write regfield port_id reg_off bit_x bit_y reg_value\"\n\t\"(set register bit field between bit_x and bit_y included)\",\n\t.tokens = {\n\t\t(void *)&cmd_write_reg_bit_field_write,\n\t\t(void *)&cmd_write_reg_bit_field_regfield,\n\t\t(void *)&cmd_write_reg_bit_field_port_id,\n\t\t(void *)&cmd_write_reg_bit_field_reg_off,\n\t\t(void *)&cmd_write_reg_bit_field_bit1_pos,\n\t\t(void *)&cmd_write_reg_bit_field_bit2_pos,\n\t\t(void *)&cmd_write_reg_bit_field_value,\n\t\tNULL,\n\t},\n};\n\n/* *** WRITE PORT REGISTER BIT *** */\nstruct cmd_write_reg_bit_result {\n\tcmdline_fixed_string_t write;\n\tcmdline_fixed_string_t regbit;\n\tuint8_t port_id;\n\tuint32_t reg_off;\n\tuint8_t bit_pos;\n\tuint8_t value;\n};\n\nstatic void\ncmd_write_reg_bit_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_write_reg_bit_result *res = parsed_result;\n\tport_reg_bit_set(res->port_id, res->reg_off, res->bit_pos, res->value);\n}\n\ncmdline_parse_token_string_t cmd_write_reg_bit_write =\n\tTOKEN_STRING_INITIALIZER(struct cmd_write_reg_bit_result, write,\n\t\t\t\t \"write\");\ncmdline_parse_token_string_t cmd_write_reg_bit_regbit =\n\tTOKEN_STRING_INITIALIZER(struct cmd_write_reg_bit_result,\n\t\t\t\t regbit, \"regbit\");\ncmdline_parse_token_num_t cmd_write_reg_bit_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_write_reg_bit_result, port_id, UINT8);\ncmdline_parse_token_num_t cmd_write_reg_bit_reg_off =\n\tTOKEN_NUM_INITIALIZER(struct cmd_write_reg_bit_result, reg_off, UINT32);\ncmdline_parse_token_num_t cmd_write_reg_bit_bit_pos =\n\tTOKEN_NUM_INITIALIZER(struct cmd_write_reg_bit_result, bit_pos, UINT8);\ncmdline_parse_token_num_t cmd_write_reg_bit_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_write_reg_bit_result, value, UINT8);\n\ncmdline_parse_inst_t cmd_write_reg_bit = {\n\t.f = cmd_write_reg_bit_parsed,\n\t.data = NULL,\n\t.help_str = \"write regbit port_id reg_off bit_x 0/1 (0 <= bit_x <= 31)\",\n\t.tokens = {\n\t\t(void *)&cmd_write_reg_bit_write,\n\t\t(void *)&cmd_write_reg_bit_regbit,\n\t\t(void *)&cmd_write_reg_bit_port_id,\n\t\t(void *)&cmd_write_reg_bit_reg_off,\n\t\t(void *)&cmd_write_reg_bit_bit_pos,\n\t\t(void *)&cmd_write_reg_bit_value,\n\t\tNULL,\n\t},\n};\n\n/* *** READ A RING DESCRIPTOR OF A PORT RX/TX QUEUE *** */\nstruct cmd_read_rxd_txd_result {\n\tcmdline_fixed_string_t read;\n\tcmdline_fixed_string_t rxd_txd;\n\tuint8_t port_id;\n\tuint16_t queue_id;\n\tuint16_t desc_id;\n};\n\nstatic void\ncmd_read_rxd_txd_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_read_rxd_txd_result *res = parsed_result;\n\n\tif (!strcmp(res->rxd_txd, \"rxd\"))\n\t\trx_ring_desc_display(res->port_id, res->queue_id, res->desc_id);\n\telse if (!strcmp(res->rxd_txd, \"txd\"))\n\t\ttx_ring_desc_display(res->port_id, res->queue_id, res->desc_id);\n}\n\ncmdline_parse_token_string_t cmd_read_rxd_txd_read =\n\tTOKEN_STRING_INITIALIZER(struct cmd_read_rxd_txd_result, read, \"read\");\ncmdline_parse_token_string_t cmd_read_rxd_txd_rxd_txd =\n\tTOKEN_STRING_INITIALIZER(struct cmd_read_rxd_txd_result, rxd_txd,\n\t\t\t\t \"rxd#txd\");\ncmdline_parse_token_num_t cmd_read_rxd_txd_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_read_rxd_txd_result, port_id, UINT8);\ncmdline_parse_token_num_t cmd_read_rxd_txd_queue_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_read_rxd_txd_result, queue_id, UINT16);\ncmdline_parse_token_num_t cmd_read_rxd_txd_desc_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_read_rxd_txd_result, desc_id, UINT16);\n\ncmdline_parse_inst_t cmd_read_rxd_txd = {\n\t.f = cmd_read_rxd_txd_parsed,\n\t.data = NULL,\n\t.help_str = \"read rxd|txd port_id queue_id rxd_id\",\n\t.tokens = {\n\t\t(void *)&cmd_read_rxd_txd_read,\n\t\t(void *)&cmd_read_rxd_txd_rxd_txd,\n\t\t(void *)&cmd_read_rxd_txd_port_id,\n\t\t(void *)&cmd_read_rxd_txd_queue_id,\n\t\t(void *)&cmd_read_rxd_txd_desc_id,\n\t\tNULL,\n\t},\n};\n\n/* *** QUIT *** */\nstruct cmd_quit_result {\n\tcmdline_fixed_string_t quit;\n};\n\nstatic void cmd_quit_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tpmd_test_exit();\n\tcmdline_quit(cl);\n}\n\ncmdline_parse_token_string_t cmd_quit_quit =\n\tTOKEN_STRING_INITIALIZER(struct cmd_quit_result, quit, \"quit\");\n\ncmdline_parse_inst_t cmd_quit = {\n\t.f = cmd_quit_parsed,\n\t.data = NULL,\n\t.help_str = \"exit application\",\n\t.tokens = {\n\t\t(void *)&cmd_quit_quit,\n\t\tNULL,\n\t},\n};\n\n/* *** ADD/REMOVE MAC ADDRESS FROM A PORT *** */\nstruct cmd_mac_addr_result {\n\tcmdline_fixed_string_t mac_addr_cmd;\n\tcmdline_fixed_string_t what;\n\tuint8_t port_num;\n\tstruct ether_addr address;\n};\n\nstatic void cmd_mac_addr_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_mac_addr_result *res = parsed_result;\n\tint ret;\n\n\tif (strcmp(res->what, \"add\") == 0)\n\t\tret = rte_eth_dev_mac_addr_add(res->port_num, &res->address, 0);\n\telse\n\t\tret = rte_eth_dev_mac_addr_remove(res->port_num, &res->address);\n\n\t/* check the return value and print it if is < 0 */\n\tif(ret < 0)\n\t\tprintf(\"mac_addr_cmd error: (%s)\\n\", strerror(-ret));\n\n}\n\ncmdline_parse_token_string_t cmd_mac_addr_cmd =\n\tTOKEN_STRING_INITIALIZER(struct cmd_mac_addr_result, mac_addr_cmd,\n\t\t\t\t\"mac_addr\");\ncmdline_parse_token_string_t cmd_mac_addr_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_mac_addr_result, what,\n\t\t\t\t\"add#remove\");\ncmdline_parse_token_num_t cmd_mac_addr_portnum =\n\t\tTOKEN_NUM_INITIALIZER(struct cmd_mac_addr_result, port_num, UINT8);\ncmdline_parse_token_etheraddr_t cmd_mac_addr_addr =\n\t\tTOKEN_ETHERADDR_INITIALIZER(struct cmd_mac_addr_result, address);\n\ncmdline_parse_inst_t cmd_mac_addr = {\n\t.f = cmd_mac_addr_parsed,\n\t.data = (void *)0,\n\t.help_str = \"mac_addr add|remove X
: \"\n\t\t\t\"add/remove MAC address on port X\",\n\t.tokens = {\n\t\t(void *)&cmd_mac_addr_cmd,\n\t\t(void *)&cmd_mac_addr_what,\n\t\t(void *)&cmd_mac_addr_portnum,\n\t\t(void *)&cmd_mac_addr_addr,\n\t\tNULL,\n\t},\n};\n\n\n/* *** CONFIGURE QUEUE STATS COUNTER MAPPINGS *** */\nstruct cmd_set_qmap_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t qmap;\n\tcmdline_fixed_string_t what;\n\tuint8_t port_id;\n\tuint16_t queue_id;\n\tuint8_t map_value;\n};\n\nstatic void\ncmd_set_qmap_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_set_qmap_result *res = parsed_result;\n\tint is_rx = (strcmp(res->what, \"tx\") == 0) ? 0 : 1;\n\n\tset_qmap(res->port_id, (uint8_t)is_rx, res->queue_id, res->map_value);\n}\n\ncmdline_parse_token_string_t cmd_setqmap_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_qmap_result,\n\t\t\t\t set, \"set\");\ncmdline_parse_token_string_t cmd_setqmap_qmap =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_qmap_result,\n\t\t\t\t qmap, \"stat_qmap\");\ncmdline_parse_token_string_t cmd_setqmap_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_qmap_result,\n\t\t\t\t what, \"tx#rx\");\ncmdline_parse_token_num_t cmd_setqmap_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_qmap_result,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_num_t cmd_setqmap_queueid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_qmap_result,\n\t\t\t queue_id, UINT16);\ncmdline_parse_token_num_t cmd_setqmap_mapvalue =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_qmap_result,\n\t\t\t map_value, UINT8);\n\ncmdline_parse_inst_t cmd_set_qmap = {\n\t.f = cmd_set_qmap_parsed,\n\t.data = NULL,\n\t.help_str = \"Set statistics mapping value on tx|rx queue_id of port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_setqmap_set,\n\t\t(void *)&cmd_setqmap_qmap,\n\t\t(void *)&cmd_setqmap_what,\n\t\t(void *)&cmd_setqmap_portid,\n\t\t(void *)&cmd_setqmap_queueid,\n\t\t(void *)&cmd_setqmap_mapvalue,\n\t\tNULL,\n\t},\n};\n\n/* *** CONFIGURE UNICAST HASH TABLE *** */\nstruct cmd_set_uc_hash_table {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t what;\n\tstruct ether_addr address;\n\tcmdline_fixed_string_t mode;\n};\n\nstatic void\ncmd_set_uc_hash_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tint ret=0;\n\tstruct cmd_set_uc_hash_table *res = parsed_result;\n\n\tint is_on = (strcmp(res->mode, \"on\") == 0) ? 1 : 0;\n\n\tif (strcmp(res->what, \"uta\") == 0)\n\t\tret = rte_eth_dev_uc_hash_table_set(res->port_id,\n\t\t\t\t\t\t&res->address,(uint8_t)is_on);\n\tif (ret < 0)\n\t\tprintf(\"bad unicast hash table parameter, return code = %d \\n\", ret);\n\n}\n\ncmdline_parse_token_string_t cmd_set_uc_hash_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_uc_hash_table,\n\t\t\t\t set, \"set\");\ncmdline_parse_token_string_t cmd_set_uc_hash_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_uc_hash_table,\n\t\t\t\t port, \"port\");\ncmdline_parse_token_num_t cmd_set_uc_hash_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_uc_hash_table,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_string_t cmd_set_uc_hash_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_uc_hash_table,\n\t\t\t\t what, \"uta\");\ncmdline_parse_token_etheraddr_t cmd_set_uc_hash_mac =\n\tTOKEN_ETHERADDR_INITIALIZER(struct cmd_set_uc_hash_table,\n\t\t\t\taddress);\ncmdline_parse_token_string_t cmd_set_uc_hash_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_uc_hash_table,\n\t\t\t\t mode, \"on#off\");\n\ncmdline_parse_inst_t cmd_set_uc_hash_filter = {\n\t.f = cmd_set_uc_hash_parsed,\n\t.data = NULL,\n\t.help_str = \"set port X uta Y on|off(X = port number,Y = MAC address)\",\n\t.tokens = {\n\t\t(void *)&cmd_set_uc_hash_set,\n\t\t(void *)&cmd_set_uc_hash_port,\n\t\t(void *)&cmd_set_uc_hash_portid,\n\t\t(void *)&cmd_set_uc_hash_what,\n\t\t(void *)&cmd_set_uc_hash_mac,\n\t\t(void *)&cmd_set_uc_hash_mode,\n\t\tNULL,\n\t},\n};\n\nstruct cmd_set_uc_all_hash_table {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t what;\n\tcmdline_fixed_string_t value;\n\tcmdline_fixed_string_t mode;\n};\n\nstatic void\ncmd_set_uc_all_hash_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tint ret=0;\n\tstruct cmd_set_uc_all_hash_table *res = parsed_result;\n\n\tint is_on = (strcmp(res->mode, \"on\") == 0) ? 1 : 0;\n\n\tif ((strcmp(res->what, \"uta\") == 0) &&\n\t\t(strcmp(res->value, \"all\") == 0))\n\t\tret = rte_eth_dev_uc_all_hash_table_set(res->port_id,(uint8_t) is_on);\n\tif (ret < 0)\n\t\tprintf(\"bad unicast hash table parameter,\"\n\t\t\t\"return code = %d \\n\", ret);\n}\n\ncmdline_parse_token_string_t cmd_set_uc_all_hash_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_uc_all_hash_table,\n\t\t\t\t set, \"set\");\ncmdline_parse_token_string_t cmd_set_uc_all_hash_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_uc_all_hash_table,\n\t\t\t\t port, \"port\");\ncmdline_parse_token_num_t cmd_set_uc_all_hash_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_uc_all_hash_table,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_string_t cmd_set_uc_all_hash_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_uc_all_hash_table,\n\t\t\t\t what, \"uta\");\ncmdline_parse_token_string_t cmd_set_uc_all_hash_value =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_uc_all_hash_table,\n\t\t\t\tvalue,\"all\");\ncmdline_parse_token_string_t cmd_set_uc_all_hash_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_uc_all_hash_table,\n\t\t\t\t mode, \"on#off\");\n\ncmdline_parse_inst_t cmd_set_uc_all_hash_filter = {\n\t.f = cmd_set_uc_all_hash_parsed,\n\t.data = NULL,\n\t.help_str = \"set port X uta all on|off (X = port number)\",\n\t.tokens = {\n\t\t(void *)&cmd_set_uc_all_hash_set,\n\t\t(void *)&cmd_set_uc_all_hash_port,\n\t\t(void *)&cmd_set_uc_all_hash_portid,\n\t\t(void *)&cmd_set_uc_all_hash_what,\n\t\t(void *)&cmd_set_uc_all_hash_value,\n\t\t(void *)&cmd_set_uc_all_hash_mode,\n\t\tNULL,\n\t},\n};\n\n/* *** CONFIGURE MACVLAN FILTER FOR VF(s) *** */\nstruct cmd_set_vf_macvlan_filter {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t vf;\n\tuint8_t vf_id;\n\tstruct ether_addr address;\n\tcmdline_fixed_string_t filter_type;\n\tcmdline_fixed_string_t mode;\n};\n\nstatic void\ncmd_set_vf_macvlan_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tint is_on, ret = 0;\n\tstruct cmd_set_vf_macvlan_filter *res = parsed_result;\n\tstruct rte_eth_mac_filter filter;\n\n\tmemset(&filter, 0, sizeof(struct rte_eth_mac_filter));\n\n\t(void)rte_memcpy(&filter.mac_addr, &res->address, ETHER_ADDR_LEN);\n\n\t/* set VF MAC filter */\n\tfilter.is_vf = 1;\n\n\t/* set VF ID */\n\tfilter.dst_id = res->vf_id;\n\n\tif (!strcmp(res->filter_type, \"exact-mac\"))\n\t\tfilter.filter_type = RTE_MAC_PERFECT_MATCH;\n\telse if (!strcmp(res->filter_type, \"exact-mac-vlan\"))\n\t\tfilter.filter_type = RTE_MACVLAN_PERFECT_MATCH;\n\telse if (!strcmp(res->filter_type, \"hashmac\"))\n\t\tfilter.filter_type = RTE_MAC_HASH_MATCH;\n\telse if (!strcmp(res->filter_type, \"hashmac-vlan\"))\n\t\tfilter.filter_type = RTE_MACVLAN_HASH_MATCH;\n\n\tis_on = (strcmp(res->mode, \"on\") == 0) ? 1 : 0;\n\n\tif (is_on)\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\t\tRTE_ETH_FILTER_MACVLAN,\n\t\t\t\t\tRTE_ETH_FILTER_ADD,\n\t\t\t\t\t &filter);\n\telse\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\t\tRTE_ETH_FILTER_MACVLAN,\n\t\t\t\t\tRTE_ETH_FILTER_DELETE,\n\t\t\t\t\t&filter);\n\n\tif (ret < 0)\n\t\tprintf(\"bad set MAC hash parameter, return code = %d\\n\", ret);\n\n}\n\ncmdline_parse_token_string_t cmd_set_vf_macvlan_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_macvlan_filter,\n\t\t\t\t set, \"set\");\ncmdline_parse_token_string_t cmd_set_vf_macvlan_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_macvlan_filter,\n\t\t\t\t port, \"port\");\ncmdline_parse_token_num_t cmd_set_vf_macvlan_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_vf_macvlan_filter,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_string_t cmd_set_vf_macvlan_vf =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_macvlan_filter,\n\t\t\t\t vf, \"vf\");\ncmdline_parse_token_num_t cmd_set_vf_macvlan_vf_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_vf_macvlan_filter,\n\t\t\t\tvf_id, UINT8);\ncmdline_parse_token_etheraddr_t cmd_set_vf_macvlan_mac =\n\tTOKEN_ETHERADDR_INITIALIZER(struct cmd_set_vf_macvlan_filter,\n\t\t\t\taddress);\ncmdline_parse_token_string_t cmd_set_vf_macvlan_filter_type =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_macvlan_filter,\n\t\t\t\tfilter_type, \"exact-mac#exact-mac-vlan\"\n\t\t\t\t\"#hashmac#hashmac-vlan\");\ncmdline_parse_token_string_t cmd_set_vf_macvlan_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_macvlan_filter,\n\t\t\t\t mode, \"on#off\");\n\ncmdline_parse_inst_t cmd_set_vf_macvlan_filter = {\n\t.f = cmd_set_vf_macvlan_parsed,\n\t.data = NULL,\n\t.help_str = \"set port (portid) vf (vfid) (mac-addr) \"\n\t\t\t\"(exact-mac|exact-mac-vlan|hashmac|hashmac-vlan) \"\n\t\t\t\"on|off\\n\"\n\t\t\t\"exact match rule:exact match of MAC or MAC and VLAN; \"\n\t\t\t\"hash match rule: hash match of MAC and exact match \"\n\t\t\t\"of VLAN\",\n\t.tokens = {\n\t\t(void *)&cmd_set_vf_macvlan_set,\n\t\t(void *)&cmd_set_vf_macvlan_port,\n\t\t(void *)&cmd_set_vf_macvlan_portid,\n\t\t(void *)&cmd_set_vf_macvlan_vf,\n\t\t(void *)&cmd_set_vf_macvlan_vf_id,\n\t\t(void *)&cmd_set_vf_macvlan_mac,\n\t\t(void *)&cmd_set_vf_macvlan_filter_type,\n\t\t(void *)&cmd_set_vf_macvlan_mode,\n\t\tNULL,\n\t},\n};\n\n/* *** CONFIGURE VF TRAFFIC CONTROL *** */\nstruct cmd_set_vf_traffic {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t vf;\n\tuint8_t vf_id;\n\tcmdline_fixed_string_t what;\n\tcmdline_fixed_string_t mode;\n};\n\nstatic void\ncmd_set_vf_traffic_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_set_vf_traffic *res = parsed_result;\n\tint is_rx = (strcmp(res->what, \"rx\") == 0) ? 1 : 0;\n\tint is_on = (strcmp(res->mode, \"on\") == 0) ? 1 : 0;\n\n\tset_vf_traffic(res->port_id, (uint8_t)is_rx, res->vf_id,(uint8_t) is_on);\n}\n\ncmdline_parse_token_string_t cmd_setvf_traffic_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_traffic,\n\t\t\t\t set, \"set\");\ncmdline_parse_token_string_t cmd_setvf_traffic_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_traffic,\n\t\t\t\t port, \"port\");\ncmdline_parse_token_num_t cmd_setvf_traffic_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_vf_traffic,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_string_t cmd_setvf_traffic_vf =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_traffic,\n\t\t\t\t vf, \"vf\");\ncmdline_parse_token_num_t cmd_setvf_traffic_vfid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_vf_traffic,\n\t\t\t vf_id, UINT8);\ncmdline_parse_token_string_t cmd_setvf_traffic_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_traffic,\n\t\t\t\t what, \"tx#rx\");\ncmdline_parse_token_string_t cmd_setvf_traffic_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_traffic,\n\t\t\t\t mode, \"on#off\");\n\ncmdline_parse_inst_t cmd_set_vf_traffic = {\n\t.f = cmd_set_vf_traffic_parsed,\n\t.data = NULL,\n\t.help_str = \"set port X vf Y rx|tx on|off\"\n\t\t\t\"(X = port number,Y = vf id)\",\n\t.tokens = {\n\t\t(void *)&cmd_setvf_traffic_set,\n\t\t(void *)&cmd_setvf_traffic_port,\n\t\t(void *)&cmd_setvf_traffic_portid,\n\t\t(void *)&cmd_setvf_traffic_vf,\n\t\t(void *)&cmd_setvf_traffic_vfid,\n\t\t(void *)&cmd_setvf_traffic_what,\n\t\t(void *)&cmd_setvf_traffic_mode,\n\t\tNULL,\n\t},\n};\n\n/* *** CONFIGURE VF RECEIVE MODE *** */\nstruct cmd_set_vf_rxmode {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t vf;\n\tuint8_t vf_id;\n\tcmdline_fixed_string_t what;\n\tcmdline_fixed_string_t mode;\n\tcmdline_fixed_string_t on;\n};\n\nstatic void\ncmd_set_vf_rxmode_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tint ret;\n\tuint16_t rx_mode = 0;\n\tstruct cmd_set_vf_rxmode *res = parsed_result;\n\n\tint is_on = (strcmp(res->on, \"on\") == 0) ? 1 : 0;\n\tif (!strcmp(res->what,\"rxmode\")) {\n\t\tif (!strcmp(res->mode, \"AUPE\"))\n\t\t\trx_mode |= ETH_VMDQ_ACCEPT_UNTAG;\n\t\telse if (!strcmp(res->mode, \"ROPE\"))\n\t\t\trx_mode |= ETH_VMDQ_ACCEPT_HASH_UC;\n\t\telse if (!strcmp(res->mode, \"BAM\"))\n\t\t\trx_mode |= ETH_VMDQ_ACCEPT_BROADCAST;\n\t\telse if (!strncmp(res->mode, \"MPE\",3))\n\t\t\trx_mode |= ETH_VMDQ_ACCEPT_MULTICAST;\n\t}\n\n\tret = rte_eth_dev_set_vf_rxmode(res->port_id,res->vf_id,rx_mode,(uint8_t)is_on);\n\tif (ret < 0)\n\t\tprintf(\"bad VF receive mode parameter, return code = %d \\n\",\n\t\tret);\n}\n\ncmdline_parse_token_string_t cmd_set_vf_rxmode_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_rxmode,\n\t\t\t\t set, \"set\");\ncmdline_parse_token_string_t cmd_set_vf_rxmode_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_rxmode,\n\t\t\t\t port, \"port\");\ncmdline_parse_token_num_t cmd_set_vf_rxmode_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_vf_rxmode,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_string_t cmd_set_vf_rxmode_vf =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_rxmode,\n\t\t\t\t vf, \"vf\");\ncmdline_parse_token_num_t cmd_set_vf_rxmode_vfid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_vf_rxmode,\n\t\t\t vf_id, UINT8);\ncmdline_parse_token_string_t cmd_set_vf_rxmode_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_rxmode,\n\t\t\t\t what, \"rxmode\");\ncmdline_parse_token_string_t cmd_set_vf_rxmode_mode =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_rxmode,\n\t\t\t\t mode, \"AUPE#ROPE#BAM#MPE\");\ncmdline_parse_token_string_t cmd_set_vf_rxmode_on =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_vf_rxmode,\n\t\t\t\t on, \"on#off\");\n\ncmdline_parse_inst_t cmd_set_vf_rxmode = {\n\t.f = cmd_set_vf_rxmode_parsed,\n\t.data = NULL,\n\t.help_str = \"set port X vf Y rxmode AUPE|ROPE|BAM|MPE on|off\",\n\t.tokens = {\n\t\t(void *)&cmd_set_vf_rxmode_set,\n\t\t(void *)&cmd_set_vf_rxmode_port,\n\t\t(void *)&cmd_set_vf_rxmode_portid,\n\t\t(void *)&cmd_set_vf_rxmode_vf,\n\t\t(void *)&cmd_set_vf_rxmode_vfid,\n\t\t(void *)&cmd_set_vf_rxmode_what,\n\t\t(void *)&cmd_set_vf_rxmode_mode,\n\t\t(void *)&cmd_set_vf_rxmode_on,\n\t\tNULL,\n\t},\n};\n\n/* *** ADD MAC ADDRESS FILTER FOR A VF OF A PORT *** */\nstruct cmd_vf_mac_addr_result {\n\tcmdline_fixed_string_t mac_addr_cmd;\n\tcmdline_fixed_string_t what;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_num;\n\tcmdline_fixed_string_t vf;\n\tuint8_t vf_num;\n\tstruct ether_addr address;\n};\n\nstatic void cmd_vf_mac_addr_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_vf_mac_addr_result *res = parsed_result;\n\tint ret = 0;\n\n\tif (strcmp(res->what, \"add\") == 0)\n\t\tret = rte_eth_dev_mac_addr_add(res->port_num,\n\t\t\t\t\t&res->address, res->vf_num);\n\tif(ret < 0)\n\t\tprintf(\"vf_mac_addr_cmd error: (%s)\\n\", strerror(-ret));\n\n}\n\ncmdline_parse_token_string_t cmd_vf_mac_addr_cmd =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_mac_addr_result,\n\t\t\t\tmac_addr_cmd,\"mac_addr\");\ncmdline_parse_token_string_t cmd_vf_mac_addr_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_mac_addr_result,\n\t\t\t\twhat,\"add\");\ncmdline_parse_token_string_t cmd_vf_mac_addr_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_mac_addr_result,\n\t\t\t\tport,\"port\");\ncmdline_parse_token_num_t cmd_vf_mac_addr_portnum =\n\tTOKEN_NUM_INITIALIZER(struct cmd_vf_mac_addr_result,\n\t\t\t\tport_num, UINT8);\ncmdline_parse_token_string_t cmd_vf_mac_addr_vf =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_mac_addr_result,\n\t\t\t\tvf,\"vf\");\ncmdline_parse_token_num_t cmd_vf_mac_addr_vfnum =\n\tTOKEN_NUM_INITIALIZER(struct cmd_vf_mac_addr_result,\n\t\t\t\tvf_num, UINT8);\ncmdline_parse_token_etheraddr_t cmd_vf_mac_addr_addr =\n\tTOKEN_ETHERADDR_INITIALIZER(struct cmd_vf_mac_addr_result,\n\t\t\t\taddress);\n\ncmdline_parse_inst_t cmd_vf_mac_addr_filter = {\n\t.f = cmd_vf_mac_addr_parsed,\n\t.data = (void *)0,\n\t.help_str = \"mac_addr add port X vf Y ethaddr:(X = port number,\"\n\t\"Y = VF number)add MAC address filtering for a VF on port X\",\n\t.tokens = {\n\t\t(void *)&cmd_vf_mac_addr_cmd,\n\t\t(void *)&cmd_vf_mac_addr_what,\n\t\t(void *)&cmd_vf_mac_addr_port,\n\t\t(void *)&cmd_vf_mac_addr_portnum,\n\t\t(void *)&cmd_vf_mac_addr_vf,\n\t\t(void *)&cmd_vf_mac_addr_vfnum,\n\t\t(void *)&cmd_vf_mac_addr_addr,\n\t\tNULL,\n\t},\n};\n\n/* *** ADD/REMOVE A VLAN IDENTIFIER TO/FROM A PORT VLAN RX FILTER *** */\nstruct cmd_vf_rx_vlan_filter {\n\tcmdline_fixed_string_t rx_vlan;\n\tcmdline_fixed_string_t what;\n\tuint16_t vlan_id;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t vf;\n\tuint64_t vf_mask;\n};\n\nstatic void\ncmd_vf_rx_vlan_filter_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_vf_rx_vlan_filter *res = parsed_result;\n\n\tif (!strcmp(res->what, \"add\"))\n\t\tset_vf_rx_vlan(res->port_id, res->vlan_id,res->vf_mask, 1);\n\telse\n\t\tset_vf_rx_vlan(res->port_id, res->vlan_id,res->vf_mask, 0);\n}\n\ncmdline_parse_token_string_t cmd_vf_rx_vlan_filter_rx_vlan =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_rx_vlan_filter,\n\t\t\t\t rx_vlan, \"rx_vlan\");\ncmdline_parse_token_string_t cmd_vf_rx_vlan_filter_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_rx_vlan_filter,\n\t\t\t\t what, \"add#rm\");\ncmdline_parse_token_num_t cmd_vf_rx_vlan_filter_vlanid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_vf_rx_vlan_filter,\n\t\t\t vlan_id, UINT16);\ncmdline_parse_token_string_t cmd_vf_rx_vlan_filter_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_rx_vlan_filter,\n\t\t\t\t port, \"port\");\ncmdline_parse_token_num_t cmd_vf_rx_vlan_filter_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_vf_rx_vlan_filter,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_string_t cmd_vf_rx_vlan_filter_vf =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_rx_vlan_filter,\n\t\t\t\t vf, \"vf\");\ncmdline_parse_token_num_t cmd_vf_rx_vlan_filter_vf_mask =\n\tTOKEN_NUM_INITIALIZER(struct cmd_vf_rx_vlan_filter,\n\t\t\t vf_mask, UINT64);\n\ncmdline_parse_inst_t cmd_vf_rxvlan_filter = {\n\t.f = cmd_vf_rx_vlan_filter_parsed,\n\t.data = NULL,\n\t.help_str = \"rx_vlan add|rm X port Y vf Z (X = VLAN ID,\"\n\t\t\"Y = port number,Z = hexadecimal VF mask)\",\n\t.tokens = {\n\t\t(void *)&cmd_vf_rx_vlan_filter_rx_vlan,\n\t\t(void *)&cmd_vf_rx_vlan_filter_what,\n\t\t(void *)&cmd_vf_rx_vlan_filter_vlanid,\n\t\t(void *)&cmd_vf_rx_vlan_filter_port,\n\t\t(void *)&cmd_vf_rx_vlan_filter_portid,\n\t\t(void *)&cmd_vf_rx_vlan_filter_vf,\n\t\t(void *)&cmd_vf_rx_vlan_filter_vf_mask,\n\t\tNULL,\n\t},\n};\n\n/* *** SET RATE LIMIT FOR A QUEUE OF A PORT *** */\nstruct cmd_queue_rate_limit_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_num;\n\tcmdline_fixed_string_t queue;\n\tuint8_t queue_num;\n\tcmdline_fixed_string_t rate;\n\tuint16_t rate_num;\n};\n\nstatic void cmd_queue_rate_limit_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_queue_rate_limit_result *res = parsed_result;\n\tint ret = 0;\n\n\tif ((strcmp(res->set, \"set\") == 0) && (strcmp(res->port, \"port\") == 0)\n\t\t&& (strcmp(res->queue, \"queue\") == 0)\n\t\t&& (strcmp(res->rate, \"rate\") == 0))\n\t\tret = set_queue_rate_limit(res->port_num, res->queue_num,\n\t\t\t\t\tres->rate_num);\n\tif (ret < 0)\n\t\tprintf(\"queue_rate_limit_cmd error: (%s)\\n\", strerror(-ret));\n\n}\n\ncmdline_parse_token_string_t cmd_queue_rate_limit_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_queue_rate_limit_result,\n\t\t\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_queue_rate_limit_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_queue_rate_limit_result,\n\t\t\t\tport, \"port\");\ncmdline_parse_token_num_t cmd_queue_rate_limit_portnum =\n\tTOKEN_NUM_INITIALIZER(struct cmd_queue_rate_limit_result,\n\t\t\t\tport_num, UINT8);\ncmdline_parse_token_string_t cmd_queue_rate_limit_queue =\n\tTOKEN_STRING_INITIALIZER(struct cmd_queue_rate_limit_result,\n\t\t\t\tqueue, \"queue\");\ncmdline_parse_token_num_t cmd_queue_rate_limit_queuenum =\n\tTOKEN_NUM_INITIALIZER(struct cmd_queue_rate_limit_result,\n\t\t\t\tqueue_num, UINT8);\ncmdline_parse_token_string_t cmd_queue_rate_limit_rate =\n\tTOKEN_STRING_INITIALIZER(struct cmd_queue_rate_limit_result,\n\t\t\t\trate, \"rate\");\ncmdline_parse_token_num_t cmd_queue_rate_limit_ratenum =\n\tTOKEN_NUM_INITIALIZER(struct cmd_queue_rate_limit_result,\n\t\t\t\trate_num, UINT16);\n\ncmdline_parse_inst_t cmd_queue_rate_limit = {\n\t.f = cmd_queue_rate_limit_parsed,\n\t.data = (void *)0,\n\t.help_str = \"set port X queue Y rate Z:(X = port number,\"\n\t\"Y = queue number,Z = rate number)set rate limit for a queue on port X\",\n\t.tokens = {\n\t\t(void *)&cmd_queue_rate_limit_set,\n\t\t(void *)&cmd_queue_rate_limit_port,\n\t\t(void *)&cmd_queue_rate_limit_portnum,\n\t\t(void *)&cmd_queue_rate_limit_queue,\n\t\t(void *)&cmd_queue_rate_limit_queuenum,\n\t\t(void *)&cmd_queue_rate_limit_rate,\n\t\t(void *)&cmd_queue_rate_limit_ratenum,\n\t\tNULL,\n\t},\n};\n\n/* *** SET RATE LIMIT FOR A VF OF A PORT *** */\nstruct cmd_vf_rate_limit_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_num;\n\tcmdline_fixed_string_t vf;\n\tuint8_t vf_num;\n\tcmdline_fixed_string_t rate;\n\tuint16_t rate_num;\n\tcmdline_fixed_string_t q_msk;\n\tuint64_t q_msk_val;\n};\n\nstatic void cmd_vf_rate_limit_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_vf_rate_limit_result *res = parsed_result;\n\tint ret = 0;\n\n\tif ((strcmp(res->set, \"set\") == 0) && (strcmp(res->port, \"port\") == 0)\n\t\t&& (strcmp(res->vf, \"vf\") == 0)\n\t\t&& (strcmp(res->rate, \"rate\") == 0)\n\t\t&& (strcmp(res->q_msk, \"queue_mask\") == 0))\n\t\tret = set_vf_rate_limit(res->port_num, res->vf_num,\n\t\t\t\t\tres->rate_num, res->q_msk_val);\n\tif (ret < 0)\n\t\tprintf(\"vf_rate_limit_cmd error: (%s)\\n\", strerror(-ret));\n\n}\n\ncmdline_parse_token_string_t cmd_vf_rate_limit_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_rate_limit_result,\n\t\t\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_vf_rate_limit_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_rate_limit_result,\n\t\t\t\tport, \"port\");\ncmdline_parse_token_num_t cmd_vf_rate_limit_portnum =\n\tTOKEN_NUM_INITIALIZER(struct cmd_vf_rate_limit_result,\n\t\t\t\tport_num, UINT8);\ncmdline_parse_token_string_t cmd_vf_rate_limit_vf =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_rate_limit_result,\n\t\t\t\tvf, \"vf\");\ncmdline_parse_token_num_t cmd_vf_rate_limit_vfnum =\n\tTOKEN_NUM_INITIALIZER(struct cmd_vf_rate_limit_result,\n\t\t\t\tvf_num, UINT8);\ncmdline_parse_token_string_t cmd_vf_rate_limit_rate =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_rate_limit_result,\n\t\t\t\trate, \"rate\");\ncmdline_parse_token_num_t cmd_vf_rate_limit_ratenum =\n\tTOKEN_NUM_INITIALIZER(struct cmd_vf_rate_limit_result,\n\t\t\t\trate_num, UINT16);\ncmdline_parse_token_string_t cmd_vf_rate_limit_q_msk =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vf_rate_limit_result,\n\t\t\t\tq_msk, \"queue_mask\");\ncmdline_parse_token_num_t cmd_vf_rate_limit_q_msk_val =\n\tTOKEN_NUM_INITIALIZER(struct cmd_vf_rate_limit_result,\n\t\t\t\tq_msk_val, UINT64);\n\ncmdline_parse_inst_t cmd_vf_rate_limit = {\n\t.f = cmd_vf_rate_limit_parsed,\n\t.data = (void *)0,\n\t.help_str = \"set port X vf Y rate Z queue_mask V:(X = port number,\"\n\t\"Y = VF number,Z = rate number, V = queue mask value)set rate limit \"\n\t\"for queues of VF on port X\",\n\t.tokens = {\n\t\t(void *)&cmd_vf_rate_limit_set,\n\t\t(void *)&cmd_vf_rate_limit_port,\n\t\t(void *)&cmd_vf_rate_limit_portnum,\n\t\t(void *)&cmd_vf_rate_limit_vf,\n\t\t(void *)&cmd_vf_rate_limit_vfnum,\n\t\t(void *)&cmd_vf_rate_limit_rate,\n\t\t(void *)&cmd_vf_rate_limit_ratenum,\n\t\t(void *)&cmd_vf_rate_limit_q_msk,\n\t\t(void *)&cmd_vf_rate_limit_q_msk_val,\n\t\tNULL,\n\t},\n};\n\n/* *** ADD TUNNEL FILTER OF A PORT *** */\nstruct cmd_tunnel_filter_result {\n\tcmdline_fixed_string_t cmd;\n\tcmdline_fixed_string_t what;\n\tuint8_t port_id;\n\tstruct ether_addr outer_mac;\n\tstruct ether_addr inner_mac;\n\tcmdline_ipaddr_t ip_value;\n\tuint16_t inner_vlan;\n\tcmdline_fixed_string_t tunnel_type;\n\tcmdline_fixed_string_t filter_type;\n\tuint32_t tenant_id;\n\tuint16_t queue_num;\n};\n\nstatic void\ncmd_tunnel_filter_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_tunnel_filter_result *res = parsed_result;\n\tstruct rte_eth_tunnel_filter_conf tunnel_filter_conf;\n\tint ret = 0;\n\n\ttunnel_filter_conf.outer_mac = &res->outer_mac;\n\ttunnel_filter_conf.inner_mac = &res->inner_mac;\n\ttunnel_filter_conf.inner_vlan = res->inner_vlan;\n\n\tif (res->ip_value.family == AF_INET) {\n\t\ttunnel_filter_conf.ip_addr.ipv4_addr =\n\t\t\tres->ip_value.addr.ipv4.s_addr;\n\t\ttunnel_filter_conf.ip_type = RTE_TUNNEL_IPTYPE_IPV4;\n\t} else {\n\t\tmemcpy(&(tunnel_filter_conf.ip_addr.ipv6_addr),\n\t\t\t&(res->ip_value.addr.ipv6),\n\t\t\tsizeof(struct in6_addr));\n\t\ttunnel_filter_conf.ip_type = RTE_TUNNEL_IPTYPE_IPV6;\n\t}\n\n\tif (!strcmp(res->filter_type, \"imac-ivlan\"))\n\t\ttunnel_filter_conf.filter_type = RTE_TUNNEL_FILTER_IMAC_IVLAN;\n\telse if (!strcmp(res->filter_type, \"imac-ivlan-tenid\"))\n\t\ttunnel_filter_conf.filter_type =\n\t\t\tRTE_TUNNEL_FILTER_IMAC_IVLAN_TENID;\n\telse if (!strcmp(res->filter_type, \"imac-tenid\"))\n\t\ttunnel_filter_conf.filter_type = RTE_TUNNEL_FILTER_IMAC_TENID;\n\telse if (!strcmp(res->filter_type, \"imac\"))\n\t\ttunnel_filter_conf.filter_type = ETH_TUNNEL_FILTER_IMAC;\n\telse if (!strcmp(res->filter_type, \"omac-imac-tenid\"))\n\t\ttunnel_filter_conf.filter_type =\n\t\t\tRTE_TUNNEL_FILTER_OMAC_TENID_IMAC;\n\telse {\n\t\tprintf(\"The filter type is not supported\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->tunnel_type, \"vxlan\"))\n\t\ttunnel_filter_conf.tunnel_type = RTE_TUNNEL_TYPE_VXLAN;\n\telse if (!strcmp(res->tunnel_type, \"nvgre\"))\n\t\ttunnel_filter_conf.tunnel_type = RTE_TUNNEL_TYPE_NVGRE;\n\telse {\n\t\tprintf(\"The tunnel type %s not supported.\\n\", res->tunnel_type);\n\t\treturn;\n\t}\n\n\ttunnel_filter_conf.tenant_id = res->tenant_id;\n\ttunnel_filter_conf.queue_id = res->queue_num;\n\tif (!strcmp(res->what, \"add\"))\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\t\tRTE_ETH_FILTER_TUNNEL,\n\t\t\t\t\tRTE_ETH_FILTER_ADD,\n\t\t\t\t\t&tunnel_filter_conf);\n\telse\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\t\tRTE_ETH_FILTER_TUNNEL,\n\t\t\t\t\tRTE_ETH_FILTER_DELETE,\n\t\t\t\t\t&tunnel_filter_conf);\n\tif (ret < 0)\n\t\tprintf(\"cmd_tunnel_filter_parsed error: (%s)\\n\",\n\t\t\t\tstrerror(-ret));\n\n}\ncmdline_parse_token_string_t cmd_tunnel_filter_cmd =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tunnel_filter_result,\n\tcmd, \"tunnel_filter\");\ncmdline_parse_token_string_t cmd_tunnel_filter_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tunnel_filter_result,\n\twhat, \"add#rm\");\ncmdline_parse_token_num_t cmd_tunnel_filter_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tunnel_filter_result,\n\tport_id, UINT8);\ncmdline_parse_token_etheraddr_t cmd_tunnel_filter_outer_mac =\n\tTOKEN_ETHERADDR_INITIALIZER(struct cmd_tunnel_filter_result,\n\touter_mac);\ncmdline_parse_token_etheraddr_t cmd_tunnel_filter_inner_mac =\n\tTOKEN_ETHERADDR_INITIALIZER(struct cmd_tunnel_filter_result,\n\tinner_mac);\ncmdline_parse_token_num_t cmd_tunnel_filter_innner_vlan =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tunnel_filter_result,\n\tinner_vlan, UINT16);\ncmdline_parse_token_ipaddr_t cmd_tunnel_filter_ip_value =\n\tTOKEN_IPADDR_INITIALIZER(struct cmd_tunnel_filter_result,\n\tip_value);\ncmdline_parse_token_string_t cmd_tunnel_filter_tunnel_type =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tunnel_filter_result,\n\ttunnel_type, \"vxlan#nvgre\");\n\ncmdline_parse_token_string_t cmd_tunnel_filter_filter_type =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tunnel_filter_result,\n\tfilter_type, \"imac-ivlan#imac-ivlan-tenid#imac-tenid#\"\n\t\t\"imac#omac-imac-tenid\");\ncmdline_parse_token_num_t cmd_tunnel_filter_tenant_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tunnel_filter_result,\n\ttenant_id, UINT32);\ncmdline_parse_token_num_t cmd_tunnel_filter_queue_num =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tunnel_filter_result,\n\tqueue_num, UINT16);\n\ncmdline_parse_inst_t cmd_tunnel_filter = {\n\t.f = cmd_tunnel_filter_parsed,\n\t.data = (void *)0,\n\t.help_str = \"add/rm tunnel filter of a port: \"\n\t\t\t\"tunnel_filter add port_id outer_mac inner_mac ip \"\n\t\t\t\"inner_vlan tunnel_type(vxlan|nvgre) filter_type \"\n\t\t\t\"(imac-ivlan|imac-ivlan-tenid|imac-tenid|\"\n\t\t\t\"imac|omac-imac-tenid) \"\n\t\t\t\"tenant_id queue_num\",\n\t.tokens = {\n\t\t(void *)&cmd_tunnel_filter_cmd,\n\t\t(void *)&cmd_tunnel_filter_what,\n\t\t(void *)&cmd_tunnel_filter_port_id,\n\t\t(void *)&cmd_tunnel_filter_outer_mac,\n\t\t(void *)&cmd_tunnel_filter_inner_mac,\n\t\t(void *)&cmd_tunnel_filter_ip_value,\n\t\t(void *)&cmd_tunnel_filter_innner_vlan,\n\t\t(void *)&cmd_tunnel_filter_tunnel_type,\n\t\t(void *)&cmd_tunnel_filter_filter_type,\n\t\t(void *)&cmd_tunnel_filter_tenant_id,\n\t\t(void *)&cmd_tunnel_filter_queue_num,\n\t\tNULL,\n\t},\n};\n\n/* *** CONFIGURE TUNNEL UDP PORT *** */\nstruct cmd_tunnel_udp_config {\n\tcmdline_fixed_string_t cmd;\n\tcmdline_fixed_string_t what;\n\tuint16_t udp_port;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_tunnel_udp_config_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_tunnel_udp_config *res = parsed_result;\n\tstruct rte_eth_udp_tunnel tunnel_udp;\n\tint ret;\n\n\ttunnel_udp.udp_port = res->udp_port;\n\n\tif (!strcmp(res->cmd, \"rx_vxlan_port\"))\n\t\ttunnel_udp.prot_type = RTE_TUNNEL_TYPE_VXLAN;\n\n\tif (!strcmp(res->what, \"add\"))\n\t\tret = rte_eth_dev_udp_tunnel_add(res->port_id, &tunnel_udp);\n\telse\n\t\tret = rte_eth_dev_udp_tunnel_delete(res->port_id, &tunnel_udp);\n\n\tif (ret < 0)\n\t\tprintf(\"udp tunneling add error: (%s)\\n\", strerror(-ret));\n}\n\ncmdline_parse_token_string_t cmd_tunnel_udp_config_cmd =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tunnel_udp_config,\n\t\t\t\tcmd, \"rx_vxlan_port\");\ncmdline_parse_token_string_t cmd_tunnel_udp_config_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_tunnel_udp_config,\n\t\t\t\twhat, \"add#rm\");\ncmdline_parse_token_num_t cmd_tunnel_udp_config_udp_port =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tunnel_udp_config,\n\t\t\t\tudp_port, UINT16);\ncmdline_parse_token_num_t cmd_tunnel_udp_config_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_tunnel_udp_config,\n\t\t\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_tunnel_udp_config = {\n\t.f = cmd_tunnel_udp_config_parsed,\n\t.data = (void *)0,\n\t.help_str = \"add/rm an tunneling UDP port filter: \"\n\t\t\t\"rx_vxlan_port add udp_port port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_tunnel_udp_config_cmd,\n\t\t(void *)&cmd_tunnel_udp_config_what,\n\t\t(void *)&cmd_tunnel_udp_config_udp_port,\n\t\t(void *)&cmd_tunnel_udp_config_port_id,\n\t\tNULL,\n\t},\n};\n\n/* *** CONFIGURE VM MIRROR VLAN/POOL RULE *** */\nstruct cmd_set_mirror_mask_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t mirror;\n\tuint8_t rule_id;\n\tcmdline_fixed_string_t what;\n\tcmdline_fixed_string_t value;\n\tcmdline_fixed_string_t dstpool;\n\tuint8_t dstpool_id;\n\tcmdline_fixed_string_t on;\n};\n\ncmdline_parse_token_string_t cmd_mirror_mask_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_mask_result,\n\t\t\t\tset, \"set\");\ncmdline_parse_token_string_t cmd_mirror_mask_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_mask_result,\n\t\t\t\tport, \"port\");\ncmdline_parse_token_num_t cmd_mirror_mask_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_mirror_mask_result,\n\t\t\t\tport_id, UINT8);\ncmdline_parse_token_string_t cmd_mirror_mask_mirror =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_mask_result,\n\t\t\t\tmirror, \"mirror-rule\");\ncmdline_parse_token_num_t cmd_mirror_mask_ruleid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_mirror_mask_result,\n\t\t\t\trule_id, UINT8);\ncmdline_parse_token_string_t cmd_mirror_mask_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_mask_result,\n\t\t\t\twhat, \"pool-mirror-up#pool-mirror-down\"\n\t\t\t\t \"#vlan-mirror\");\ncmdline_parse_token_string_t cmd_mirror_mask_value =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_mask_result,\n\t\t\t\tvalue, NULL);\ncmdline_parse_token_string_t cmd_mirror_mask_dstpool =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_mask_result,\n\t\t\t\tdstpool, \"dst-pool\");\ncmdline_parse_token_num_t cmd_mirror_mask_poolid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_mirror_mask_result,\n\t\t\t\tdstpool_id, UINT8);\ncmdline_parse_token_string_t cmd_mirror_mask_on =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_mask_result,\n\t\t\t\ton, \"on#off\");\n\nstatic void\ncmd_set_mirror_mask_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tint ret,nb_item,i;\n\tstruct cmd_set_mirror_mask_result *res = parsed_result;\n\tstruct rte_eth_mirror_conf mr_conf;\n\n\tmemset(&mr_conf, 0, sizeof(struct rte_eth_mirror_conf));\n\n\tunsigned int vlan_list[ETH_MIRROR_MAX_VLANS];\n\n\tmr_conf.dst_pool = res->dstpool_id;\n\n\tif (!strcmp(res->what, \"pool-mirror-up\")) {\n\t\tmr_conf.pool_mask = strtoull(res->value, NULL, 16);\n\t\tmr_conf.rule_type = ETH_MIRROR_VIRTUAL_POOL_UP;\n\t} else if (!strcmp(res->what, \"pool-mirror-down\")) {\n\t\tmr_conf.pool_mask = strtoull(res->value, NULL, 16);\n\t\tmr_conf.rule_type = ETH_MIRROR_VIRTUAL_POOL_DOWN;\n\t} else if (!strcmp(res->what, \"vlan-mirror\")) {\n\t\tmr_conf.rule_type = ETH_MIRROR_VLAN;\n\t\tnb_item = parse_item_list(res->value, \"vlan\",\n\t\t\t\tETH_MIRROR_MAX_VLANS, vlan_list, 1);\n\t\tif (nb_item <= 0)\n\t\t\treturn;\n\n\t\tfor (i = 0; i < nb_item; i++) {\n\t\t\tif (vlan_list[i] > ETHER_MAX_VLAN_ID) {\n\t\t\t\tprintf(\"Invalid vlan_id: must be < 4096\\n\");\n\t\t\t\treturn;\n\t\t\t}\n\n\t\t\tmr_conf.vlan.vlan_id[i] = (uint16_t)vlan_list[i];\n\t\t\tmr_conf.vlan.vlan_mask |= 1ULL << i;\n\t\t}\n\t}\n\n\tif (!strcmp(res->on, \"on\"))\n\t\tret = rte_eth_mirror_rule_set(res->port_id, &mr_conf,\n\t\t\t\t\t\tres->rule_id, 1);\n\telse\n\t\tret = rte_eth_mirror_rule_set(res->port_id, &mr_conf,\n\t\t\t\t\t\tres->rule_id, 0);\n\tif (ret < 0)\n\t\tprintf(\"mirror rule add error: (%s)\\n\", strerror(-ret));\n}\n\ncmdline_parse_inst_t cmd_set_mirror_mask = {\n\t\t.f = cmd_set_mirror_mask_parsed,\n\t\t.data = NULL,\n\t\t.help_str = \"set port X mirror-rule Y pool-mirror-up|pool-mirror-down|vlan-mirror\"\n\t\t\t \" pool_mask|vlan_id[,vlan_id]* dst-pool Z on|off\",\n\t\t.tokens = {\n\t\t\t(void *)&cmd_mirror_mask_set,\n\t\t\t(void *)&cmd_mirror_mask_port,\n\t\t\t(void *)&cmd_mirror_mask_portid,\n\t\t\t(void *)&cmd_mirror_mask_mirror,\n\t\t\t(void *)&cmd_mirror_mask_ruleid,\n\t\t\t(void *)&cmd_mirror_mask_what,\n\t\t\t(void *)&cmd_mirror_mask_value,\n\t\t\t(void *)&cmd_mirror_mask_dstpool,\n\t\t\t(void *)&cmd_mirror_mask_poolid,\n\t\t\t(void *)&cmd_mirror_mask_on,\n\t\t\tNULL,\n\t\t},\n};\n\n/* *** CONFIGURE VM MIRROR UDLINK/DOWNLINK RULE *** */\nstruct cmd_set_mirror_link_result {\n\tcmdline_fixed_string_t set;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t mirror;\n\tuint8_t rule_id;\n\tcmdline_fixed_string_t what;\n\tcmdline_fixed_string_t dstpool;\n\tuint8_t dstpool_id;\n\tcmdline_fixed_string_t on;\n};\n\ncmdline_parse_token_string_t cmd_mirror_link_set =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_link_result,\n\t\t\t\t set, \"set\");\ncmdline_parse_token_string_t cmd_mirror_link_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_link_result,\n\t\t\t\tport, \"port\");\ncmdline_parse_token_num_t cmd_mirror_link_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_mirror_link_result,\n\t\t\t\tport_id, UINT8);\ncmdline_parse_token_string_t cmd_mirror_link_mirror =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_link_result,\n\t\t\t\tmirror, \"mirror-rule\");\ncmdline_parse_token_num_t cmd_mirror_link_ruleid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_mirror_link_result,\n\t\t\t rule_id, UINT8);\ncmdline_parse_token_string_t cmd_mirror_link_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_link_result,\n\t\t\t\twhat, \"uplink-mirror#downlink-mirror\");\ncmdline_parse_token_string_t cmd_mirror_link_dstpool =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_link_result,\n\t\t\t\tdstpool, \"dst-pool\");\ncmdline_parse_token_num_t cmd_mirror_link_poolid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_mirror_link_result,\n\t\t\t\tdstpool_id, UINT8);\ncmdline_parse_token_string_t cmd_mirror_link_on =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_mirror_link_result,\n\t\t\t\ton, \"on#off\");\n\nstatic void\ncmd_set_mirror_link_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tint ret;\n\tstruct cmd_set_mirror_link_result *res = parsed_result;\n\tstruct rte_eth_mirror_conf mr_conf;\n\n\tmemset(&mr_conf, 0, sizeof(struct rte_eth_mirror_conf));\n\tif (!strcmp(res->what, \"uplink-mirror\"))\n\t\tmr_conf.rule_type = ETH_MIRROR_UPLINK_PORT;\n\telse\n\t\tmr_conf.rule_type = ETH_MIRROR_DOWNLINK_PORT;\n\n\tmr_conf.dst_pool = res->dstpool_id;\n\n\tif (!strcmp(res->on, \"on\"))\n\t\tret = rte_eth_mirror_rule_set(res->port_id, &mr_conf,\n\t\t\t\t\t\tres->rule_id, 1);\n\telse\n\t\tret = rte_eth_mirror_rule_set(res->port_id, &mr_conf,\n\t\t\t\t\t\tres->rule_id, 0);\n\n\t/* check the return value and print it if is < 0 */\n\tif (ret < 0)\n\t\tprintf(\"mirror rule add error: (%s)\\n\", strerror(-ret));\n\n}\n\ncmdline_parse_inst_t cmd_set_mirror_link = {\n\t\t.f = cmd_set_mirror_link_parsed,\n\t\t.data = NULL,\n\t\t.help_str = \"set port X mirror-rule Y uplink-mirror|\"\n\t\t\t\"downlink-mirror dst-pool Z on|off\",\n\t\t.tokens = {\n\t\t\t(void *)&cmd_mirror_link_set,\n\t\t\t(void *)&cmd_mirror_link_port,\n\t\t\t(void *)&cmd_mirror_link_portid,\n\t\t\t(void *)&cmd_mirror_link_mirror,\n\t\t\t(void *)&cmd_mirror_link_ruleid,\n\t\t\t(void *)&cmd_mirror_link_what,\n\t\t\t(void *)&cmd_mirror_link_dstpool,\n\t\t\t(void *)&cmd_mirror_link_poolid,\n\t\t\t(void *)&cmd_mirror_link_on,\n\t\t\tNULL,\n\t\t},\n};\n\n/* *** RESET VM MIRROR RULE *** */\nstruct cmd_rm_mirror_rule_result {\n\tcmdline_fixed_string_t reset;\n\tcmdline_fixed_string_t port;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t mirror;\n\tuint8_t rule_id;\n};\n\ncmdline_parse_token_string_t cmd_rm_mirror_rule_reset =\n\tTOKEN_STRING_INITIALIZER(struct cmd_rm_mirror_rule_result,\n\t\t\t\t reset, \"reset\");\ncmdline_parse_token_string_t cmd_rm_mirror_rule_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_rm_mirror_rule_result,\n\t\t\t\tport, \"port\");\ncmdline_parse_token_num_t cmd_rm_mirror_rule_portid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_rm_mirror_rule_result,\n\t\t\t\tport_id, UINT8);\ncmdline_parse_token_string_t cmd_rm_mirror_rule_mirror =\n\tTOKEN_STRING_INITIALIZER(struct cmd_rm_mirror_rule_result,\n\t\t\t\tmirror, \"mirror-rule\");\ncmdline_parse_token_num_t cmd_rm_mirror_rule_ruleid =\n\tTOKEN_NUM_INITIALIZER(struct cmd_rm_mirror_rule_result,\n\t\t\t\trule_id, UINT8);\n\nstatic void\ncmd_reset_mirror_rule_parsed(void *parsed_result,\n\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tint ret;\n\tstruct cmd_set_mirror_link_result *res = parsed_result;\n /* check rule_id */\n\tret = rte_eth_mirror_rule_reset(res->port_id,res->rule_id);\n\tif(ret < 0)\n\t\tprintf(\"mirror rule remove error: (%s)\\n\", strerror(-ret));\n}\n\ncmdline_parse_inst_t cmd_reset_mirror_rule = {\n\t\t.f = cmd_reset_mirror_rule_parsed,\n\t\t.data = NULL,\n\t\t.help_str = \"reset port X mirror-rule Y\",\n\t\t.tokens = {\n\t\t\t(void *)&cmd_rm_mirror_rule_reset,\n\t\t\t(void *)&cmd_rm_mirror_rule_port,\n\t\t\t(void *)&cmd_rm_mirror_rule_portid,\n\t\t\t(void *)&cmd_rm_mirror_rule_mirror,\n\t\t\t(void *)&cmd_rm_mirror_rule_ruleid,\n\t\t\tNULL,\n\t\t},\n};\n\n/* ******************************************************************************** */\n\nstruct cmd_dump_result {\n\tcmdline_fixed_string_t dump;\n};\n\nstatic void\ndump_struct_sizes(void)\n{\n#define DUMP_SIZE(t) printf(\"sizeof(\" #t \") = %u\\n\", (unsigned)sizeof(t));\n\tDUMP_SIZE(struct rte_mbuf);\n\tDUMP_SIZE(struct rte_mempool);\n\tDUMP_SIZE(struct rte_ring);\n#undef DUMP_SIZE\n}\n\nstatic void cmd_dump_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_dump_result *res = parsed_result;\n\n\tif (!strcmp(res->dump, \"dump_physmem\"))\n\t\trte_dump_physmem_layout(stdout);\n\telse if (!strcmp(res->dump, \"dump_memzone\"))\n\t\trte_memzone_dump(stdout);\n\telse if (!strcmp(res->dump, \"dump_log_history\"))\n\t\trte_log_dump_history(stdout);\n\telse if (!strcmp(res->dump, \"dump_struct_sizes\"))\n\t\tdump_struct_sizes();\n\telse if (!strcmp(res->dump, \"dump_ring\"))\n\t\trte_ring_list_dump(stdout);\n\telse if (!strcmp(res->dump, \"dump_mempool\"))\n\t\trte_mempool_list_dump(stdout);\n\telse if (!strcmp(res->dump, \"dump_devargs\"))\n\t\trte_eal_devargs_dump(stdout);\n}\n\ncmdline_parse_token_string_t cmd_dump_dump =\n\tTOKEN_STRING_INITIALIZER(struct cmd_dump_result, dump,\n\t\t\"dump_physmem#\"\n\t\t\"dump_memzone#\"\n\t\t\"dump_log_history#\"\n\t\t\"dump_struct_sizes#\"\n\t\t\"dump_ring#\"\n\t\t\"dump_mempool#\"\n\t\t\"dump_devargs\");\n\ncmdline_parse_inst_t cmd_dump = {\n\t.f = cmd_dump_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"dump status\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_dump_dump,\n\t\tNULL,\n\t},\n};\n\n/* ******************************************************************************** */\n\nstruct cmd_dump_one_result {\n\tcmdline_fixed_string_t dump;\n\tcmdline_fixed_string_t name;\n};\n\nstatic void cmd_dump_one_parsed(void *parsed_result, struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_dump_one_result *res = parsed_result;\n\n\tif (!strcmp(res->dump, \"dump_ring\")) {\n\t\tstruct rte_ring *r;\n\t\tr = rte_ring_lookup(res->name);\n\t\tif (r == NULL) {\n\t\t\tcmdline_printf(cl, \"Cannot find ring\\n\");\n\t\t\treturn;\n\t\t}\n\t\trte_ring_dump(stdout, r);\n\t} else if (!strcmp(res->dump, \"dump_mempool\")) {\n\t\tstruct rte_mempool *mp;\n\t\tmp = rte_mempool_lookup(res->name);\n\t\tif (mp == NULL) {\n\t\t\tcmdline_printf(cl, \"Cannot find mempool\\n\");\n\t\t\treturn;\n\t\t}\n\t\trte_mempool_dump(stdout, mp);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_dump_one_dump =\n\tTOKEN_STRING_INITIALIZER(struct cmd_dump_one_result, dump,\n\t\t\t\t \"dump_ring#dump_mempool\");\n\ncmdline_parse_token_string_t cmd_dump_one_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_dump_one_result, name, NULL);\n\ncmdline_parse_inst_t cmd_dump_one = {\n\t.f = cmd_dump_one_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"dump one ring/mempool: dump_ring|dump_mempool \",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_dump_one_dump,\n\t\t(void *)&cmd_dump_one_name,\n\t\tNULL,\n\t},\n};\n\n/* *** Add/Del syn filter *** */\nstruct cmd_syn_filter_result {\n\tcmdline_fixed_string_t filter;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t ops;\n\tcmdline_fixed_string_t priority;\n\tcmdline_fixed_string_t high;\n\tcmdline_fixed_string_t queue;\n\tuint16_t queue_id;\n};\n\nstatic void\ncmd_syn_filter_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_syn_filter_result *res = parsed_result;\n\tstruct rte_eth_syn_filter syn_filter;\n\tint ret = 0;\n\n\tret = rte_eth_dev_filter_supported(res->port_id,\n\t\t\t\t\tRTE_ETH_FILTER_SYN);\n\tif (ret < 0) {\n\t\tprintf(\"syn filter is not supported on port %u.\\n\",\n\t\t\t\tres->port_id);\n\t\treturn;\n\t}\n\n\tmemset(&syn_filter, 0, sizeof(syn_filter));\n\n\tif (!strcmp(res->ops, \"add\")) {\n\t\tif (!strcmp(res->high, \"high\"))\n\t\t\tsyn_filter.hig_pri = 1;\n\t\telse\n\t\t\tsyn_filter.hig_pri = 0;\n\n\t\tsyn_filter.queue = res->queue_id;\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\t\t\tRTE_ETH_FILTER_SYN,\n\t\t\t\t\t\tRTE_ETH_FILTER_ADD,\n\t\t\t\t\t\t&syn_filter);\n\t} else\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\t\t\tRTE_ETH_FILTER_SYN,\n\t\t\t\t\t\tRTE_ETH_FILTER_DELETE,\n\t\t\t\t\t\t&syn_filter);\n\n\tif (ret < 0)\n\t\tprintf(\"syn filter programming error: (%s)\\n\",\n\t\t\t\tstrerror(-ret));\n}\n\ncmdline_parse_token_string_t cmd_syn_filter_filter =\n\tTOKEN_STRING_INITIALIZER(struct cmd_syn_filter_result,\n\tfilter, \"syn_filter\");\ncmdline_parse_token_num_t cmd_syn_filter_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_syn_filter_result,\n\tport_id, UINT8);\ncmdline_parse_token_string_t cmd_syn_filter_ops =\n\tTOKEN_STRING_INITIALIZER(struct cmd_syn_filter_result,\n\tops, \"add#del\");\ncmdline_parse_token_string_t cmd_syn_filter_priority =\n\tTOKEN_STRING_INITIALIZER(struct cmd_syn_filter_result,\n\t\t\t\tpriority, \"priority\");\ncmdline_parse_token_string_t cmd_syn_filter_high =\n\tTOKEN_STRING_INITIALIZER(struct cmd_syn_filter_result,\n\t\t\t\thigh, \"high#low\");\ncmdline_parse_token_string_t cmd_syn_filter_queue =\n\tTOKEN_STRING_INITIALIZER(struct cmd_syn_filter_result,\n\t\t\t\tqueue, \"queue\");\ncmdline_parse_token_num_t cmd_syn_filter_queue_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_syn_filter_result,\n\t\t\t\tqueue_id, UINT16);\n\ncmdline_parse_inst_t cmd_syn_filter = {\n\t.f = cmd_syn_filter_parsed,\n\t.data = NULL,\n\t.help_str = \"add/delete syn filter\",\n\t.tokens = {\n\t\t(void *)&cmd_syn_filter_filter,\n\t\t(void *)&cmd_syn_filter_port_id,\n\t\t(void *)&cmd_syn_filter_ops,\n\t\t(void *)&cmd_syn_filter_priority,\n\t\t(void *)&cmd_syn_filter_high,\n\t\t(void *)&cmd_syn_filter_queue,\n\t\t(void *)&cmd_syn_filter_queue_id,\n\t\tNULL,\n\t},\n};\n\n/* *** ADD/REMOVE A 2tuple FILTER *** */\nstruct cmd_2tuple_filter_result {\n\tcmdline_fixed_string_t filter;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t ops;\n\tcmdline_fixed_string_t dst_port;\n\tuint16_t dst_port_value;\n\tcmdline_fixed_string_t protocol;\n\tuint8_t protocol_value;\n\tcmdline_fixed_string_t mask;\n\tuint8_t mask_value;\n\tcmdline_fixed_string_t tcp_flags;\n\tuint8_t tcp_flags_value;\n\tcmdline_fixed_string_t priority;\n\tuint8_t priority_value;\n\tcmdline_fixed_string_t queue;\n\tuint16_t queue_id;\n};\n\nstatic void\ncmd_2tuple_filter_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct rte_eth_ntuple_filter filter;\n\tstruct cmd_2tuple_filter_result *res = parsed_result;\n\tint ret = 0;\n\n\tret = rte_eth_dev_filter_supported(res->port_id, RTE_ETH_FILTER_NTUPLE);\n\tif (ret < 0) {\n\t\tprintf(\"ntuple filter is not supported on port %u.\\n\",\n\t\t\tres->port_id);\n\t\treturn;\n\t}\n\n\tmemset(&filter, 0, sizeof(struct rte_eth_ntuple_filter));\n\n\tfilter.flags = RTE_2TUPLE_FLAGS;\n\tfilter.dst_port_mask = (res->mask_value & 0x02) ? UINT16_MAX : 0;\n\tfilter.proto_mask = (res->mask_value & 0x01) ? UINT8_MAX : 0;\n\tfilter.proto = res->protocol_value;\n\tfilter.priority = res->priority_value;\n\tif (res->tcp_flags_value != 0 && filter.proto != IPPROTO_TCP) {\n\t\tprintf(\"nonzero tcp_flags is only meaningful\"\n\t\t\t\" when protocol is TCP.\\n\");\n\t\treturn;\n\t}\n\tif (res->tcp_flags_value > TCP_FLAG_ALL) {\n\t\tprintf(\"invalid TCP flags.\\n\");\n\t\treturn;\n\t}\n\n\tif (res->tcp_flags_value != 0) {\n\t\tfilter.flags |= RTE_NTUPLE_FLAGS_TCP_FLAG;\n\t\tfilter.tcp_flags = res->tcp_flags_value;\n\t}\n\n\t/* need convert to big endian. */\n\tfilter.dst_port = rte_cpu_to_be_16(res->dst_port_value);\n\tfilter.queue = res->queue_id;\n\n\tif (!strcmp(res->ops, \"add\"))\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\tRTE_ETH_FILTER_NTUPLE,\n\t\t\t\tRTE_ETH_FILTER_ADD,\n\t\t\t\t&filter);\n\telse\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\tRTE_ETH_FILTER_NTUPLE,\n\t\t\t\tRTE_ETH_FILTER_DELETE,\n\t\t\t\t&filter);\n\tif (ret < 0)\n\t\tprintf(\"2tuple filter programming error: (%s)\\n\",\n\t\t\tstrerror(-ret));\n\n}\n\ncmdline_parse_token_string_t cmd_2tuple_filter_filter =\n\tTOKEN_STRING_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\t filter, \"2tuple_filter\");\ncmdline_parse_token_num_t cmd_2tuple_filter_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\tport_id, UINT8);\ncmdline_parse_token_string_t cmd_2tuple_filter_ops =\n\tTOKEN_STRING_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\t ops, \"add#del\");\ncmdline_parse_token_string_t cmd_2tuple_filter_dst_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\tdst_port, \"dst_port\");\ncmdline_parse_token_num_t cmd_2tuple_filter_dst_port_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\tdst_port_value, UINT16);\ncmdline_parse_token_string_t cmd_2tuple_filter_protocol =\n\tTOKEN_STRING_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\tprotocol, \"protocol\");\ncmdline_parse_token_num_t cmd_2tuple_filter_protocol_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\tprotocol_value, UINT8);\ncmdline_parse_token_string_t cmd_2tuple_filter_mask =\n\tTOKEN_STRING_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\tmask, \"mask\");\ncmdline_parse_token_num_t cmd_2tuple_filter_mask_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\tmask_value, INT8);\ncmdline_parse_token_string_t cmd_2tuple_filter_tcp_flags =\n\tTOKEN_STRING_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\ttcp_flags, \"tcp_flags\");\ncmdline_parse_token_num_t cmd_2tuple_filter_tcp_flags_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\ttcp_flags_value, UINT8);\ncmdline_parse_token_string_t cmd_2tuple_filter_priority =\n\tTOKEN_STRING_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\tpriority, \"priority\");\ncmdline_parse_token_num_t cmd_2tuple_filter_priority_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\tpriority_value, UINT8);\ncmdline_parse_token_string_t cmd_2tuple_filter_queue =\n\tTOKEN_STRING_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\tqueue, \"queue\");\ncmdline_parse_token_num_t cmd_2tuple_filter_queue_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_2tuple_filter_result,\n\t\t\t\tqueue_id, UINT16);\n\ncmdline_parse_inst_t cmd_2tuple_filter = {\n\t.f = cmd_2tuple_filter_parsed,\n\t.data = NULL,\n\t.help_str = \"add a 2tuple filter\",\n\t.tokens = {\n\t\t(void *)&cmd_2tuple_filter_filter,\n\t\t(void *)&cmd_2tuple_filter_port_id,\n\t\t(void *)&cmd_2tuple_filter_ops,\n\t\t(void *)&cmd_2tuple_filter_dst_port,\n\t\t(void *)&cmd_2tuple_filter_dst_port_value,\n\t\t(void *)&cmd_2tuple_filter_protocol,\n\t\t(void *)&cmd_2tuple_filter_protocol_value,\n\t\t(void *)&cmd_2tuple_filter_mask,\n\t\t(void *)&cmd_2tuple_filter_mask_value,\n\t\t(void *)&cmd_2tuple_filter_tcp_flags,\n\t\t(void *)&cmd_2tuple_filter_tcp_flags_value,\n\t\t(void *)&cmd_2tuple_filter_priority,\n\t\t(void *)&cmd_2tuple_filter_priority_value,\n\t\t(void *)&cmd_2tuple_filter_queue,\n\t\t(void *)&cmd_2tuple_filter_queue_id,\n\t\tNULL,\n\t},\n};\n\n/* *** ADD/REMOVE A 5tuple FILTER *** */\nstruct cmd_5tuple_filter_result {\n\tcmdline_fixed_string_t filter;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t ops;\n\tcmdline_fixed_string_t dst_ip;\n\tcmdline_ipaddr_t dst_ip_value;\n\tcmdline_fixed_string_t src_ip;\n\tcmdline_ipaddr_t src_ip_value;\n\tcmdline_fixed_string_t dst_port;\n\tuint16_t dst_port_value;\n\tcmdline_fixed_string_t src_port;\n\tuint16_t src_port_value;\n\tcmdline_fixed_string_t protocol;\n\tuint8_t protocol_value;\n\tcmdline_fixed_string_t mask;\n\tuint8_t mask_value;\n\tcmdline_fixed_string_t tcp_flags;\n\tuint8_t tcp_flags_value;\n\tcmdline_fixed_string_t priority;\n\tuint8_t priority_value;\n\tcmdline_fixed_string_t queue;\n\tuint16_t queue_id;\n};\n\nstatic void\ncmd_5tuple_filter_parsed(void *parsed_result,\n\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct rte_eth_ntuple_filter filter;\n\tstruct cmd_5tuple_filter_result *res = parsed_result;\n\tint ret = 0;\n\n\tret = rte_eth_dev_filter_supported(res->port_id, RTE_ETH_FILTER_NTUPLE);\n\tif (ret < 0) {\n\t\tprintf(\"ntuple filter is not supported on port %u.\\n\",\n\t\t\tres->port_id);\n\t\treturn;\n\t}\n\n\tmemset(&filter, 0, sizeof(struct rte_eth_ntuple_filter));\n\n\tfilter.flags = RTE_5TUPLE_FLAGS;\n\tfilter.dst_ip_mask = (res->mask_value & 0x10) ? UINT32_MAX : 0;\n\tfilter.src_ip_mask = (res->mask_value & 0x08) ? UINT32_MAX : 0;\n\tfilter.dst_port_mask = (res->mask_value & 0x04) ? UINT16_MAX : 0;\n\tfilter.src_port_mask = (res->mask_value & 0x02) ? UINT16_MAX : 0;\n\tfilter.proto_mask = (res->mask_value & 0x01) ? UINT8_MAX : 0;\n\tfilter.proto = res->protocol_value;\n\tfilter.priority = res->priority_value;\n\tif (res->tcp_flags_value != 0 && filter.proto != IPPROTO_TCP) {\n\t\tprintf(\"nonzero tcp_flags is only meaningful\"\n\t\t\t\" when protocol is TCP.\\n\");\n\t\treturn;\n\t}\n\tif (res->tcp_flags_value > TCP_FLAG_ALL) {\n\t\tprintf(\"invalid TCP flags.\\n\");\n\t\treturn;\n\t}\n\n\tif (res->tcp_flags_value != 0) {\n\t\tfilter.flags |= RTE_NTUPLE_FLAGS_TCP_FLAG;\n\t\tfilter.tcp_flags = res->tcp_flags_value;\n\t}\n\n\tif (res->dst_ip_value.family == AF_INET)\n\t\t/* no need to convert, already big endian. */\n\t\tfilter.dst_ip = res->dst_ip_value.addr.ipv4.s_addr;\n\telse {\n\t\tif (filter.dst_ip_mask == 0) {\n\t\t\tprintf(\"can not support ipv6 involved compare.\\n\");\n\t\t\treturn;\n\t\t}\n\t\tfilter.dst_ip = 0;\n\t}\n\n\tif (res->src_ip_value.family == AF_INET)\n\t\t/* no need to convert, already big endian. */\n\t\tfilter.src_ip = res->src_ip_value.addr.ipv4.s_addr;\n\telse {\n\t\tif (filter.src_ip_mask == 0) {\n\t\t\tprintf(\"can not support ipv6 involved compare.\\n\");\n\t\t\treturn;\n\t\t}\n\t\tfilter.src_ip = 0;\n\t}\n\t/* need convert to big endian. */\n\tfilter.dst_port = rte_cpu_to_be_16(res->dst_port_value);\n\tfilter.src_port = rte_cpu_to_be_16(res->src_port_value);\n\tfilter.queue = res->queue_id;\n\n\tif (!strcmp(res->ops, \"add\"))\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\tRTE_ETH_FILTER_NTUPLE,\n\t\t\t\tRTE_ETH_FILTER_ADD,\n\t\t\t\t&filter);\n\telse\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\tRTE_ETH_FILTER_NTUPLE,\n\t\t\t\tRTE_ETH_FILTER_DELETE,\n\t\t\t\t&filter);\n\tif (ret < 0)\n\t\tprintf(\"5tuple filter programming error: (%s)\\n\",\n\t\t\tstrerror(-ret));\n}\n\ncmdline_parse_token_string_t cmd_5tuple_filter_filter =\n\tTOKEN_STRING_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\t filter, \"5tuple_filter\");\ncmdline_parse_token_num_t cmd_5tuple_filter_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tport_id, UINT8);\ncmdline_parse_token_string_t cmd_5tuple_filter_ops =\n\tTOKEN_STRING_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\t ops, \"add#del\");\ncmdline_parse_token_string_t cmd_5tuple_filter_dst_ip =\n\tTOKEN_STRING_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tdst_ip, \"dst_ip\");\ncmdline_parse_token_ipaddr_t cmd_5tuple_filter_dst_ip_value =\n\tTOKEN_IPADDR_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tdst_ip_value);\ncmdline_parse_token_string_t cmd_5tuple_filter_src_ip =\n\tTOKEN_STRING_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tsrc_ip, \"src_ip\");\ncmdline_parse_token_ipaddr_t cmd_5tuple_filter_src_ip_value =\n\tTOKEN_IPADDR_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tsrc_ip_value);\ncmdline_parse_token_string_t cmd_5tuple_filter_dst_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tdst_port, \"dst_port\");\ncmdline_parse_token_num_t cmd_5tuple_filter_dst_port_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tdst_port_value, UINT16);\ncmdline_parse_token_string_t cmd_5tuple_filter_src_port =\n\tTOKEN_STRING_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tsrc_port, \"src_port\");\ncmdline_parse_token_num_t cmd_5tuple_filter_src_port_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tsrc_port_value, UINT16);\ncmdline_parse_token_string_t cmd_5tuple_filter_protocol =\n\tTOKEN_STRING_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tprotocol, \"protocol\");\ncmdline_parse_token_num_t cmd_5tuple_filter_protocol_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tprotocol_value, UINT8);\ncmdline_parse_token_string_t cmd_5tuple_filter_mask =\n\tTOKEN_STRING_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tmask, \"mask\");\ncmdline_parse_token_num_t cmd_5tuple_filter_mask_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tmask_value, INT8);\ncmdline_parse_token_string_t cmd_5tuple_filter_tcp_flags =\n\tTOKEN_STRING_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\ttcp_flags, \"tcp_flags\");\ncmdline_parse_token_num_t cmd_5tuple_filter_tcp_flags_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\ttcp_flags_value, UINT8);\ncmdline_parse_token_string_t cmd_5tuple_filter_priority =\n\tTOKEN_STRING_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tpriority, \"priority\");\ncmdline_parse_token_num_t cmd_5tuple_filter_priority_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tpriority_value, UINT8);\ncmdline_parse_token_string_t cmd_5tuple_filter_queue =\n\tTOKEN_STRING_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tqueue, \"queue\");\ncmdline_parse_token_num_t cmd_5tuple_filter_queue_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_5tuple_filter_result,\n\t\t\t\tqueue_id, UINT16);\n\ncmdline_parse_inst_t cmd_5tuple_filter = {\n\t.f = cmd_5tuple_filter_parsed,\n\t.data = NULL,\n\t.help_str = \"add/del a 5tuple filter\",\n\t.tokens = {\n\t\t(void *)&cmd_5tuple_filter_filter,\n\t\t(void *)&cmd_5tuple_filter_port_id,\n\t\t(void *)&cmd_5tuple_filter_ops,\n\t\t(void *)&cmd_5tuple_filter_dst_ip,\n\t\t(void *)&cmd_5tuple_filter_dst_ip_value,\n\t\t(void *)&cmd_5tuple_filter_src_ip,\n\t\t(void *)&cmd_5tuple_filter_src_ip_value,\n\t\t(void *)&cmd_5tuple_filter_dst_port,\n\t\t(void *)&cmd_5tuple_filter_dst_port_value,\n\t\t(void *)&cmd_5tuple_filter_src_port,\n\t\t(void *)&cmd_5tuple_filter_src_port_value,\n\t\t(void *)&cmd_5tuple_filter_protocol,\n\t\t(void *)&cmd_5tuple_filter_protocol_value,\n\t\t(void *)&cmd_5tuple_filter_mask,\n\t\t(void *)&cmd_5tuple_filter_mask_value,\n\t\t(void *)&cmd_5tuple_filter_tcp_flags,\n\t\t(void *)&cmd_5tuple_filter_tcp_flags_value,\n\t\t(void *)&cmd_5tuple_filter_priority,\n\t\t(void *)&cmd_5tuple_filter_priority_value,\n\t\t(void *)&cmd_5tuple_filter_queue,\n\t\t(void *)&cmd_5tuple_filter_queue_id,\n\t\tNULL,\n\t},\n};\n\n/* *** ADD/REMOVE A flex FILTER *** */\nstruct cmd_flex_filter_result {\n\tcmdline_fixed_string_t filter;\n\tcmdline_fixed_string_t ops;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t len;\n\tuint8_t len_value;\n\tcmdline_fixed_string_t bytes;\n\tcmdline_fixed_string_t bytes_value;\n\tcmdline_fixed_string_t mask;\n\tcmdline_fixed_string_t mask_value;\n\tcmdline_fixed_string_t priority;\n\tuint8_t priority_value;\n\tcmdline_fixed_string_t queue;\n\tuint16_t queue_id;\n};\n\nstatic int xdigit2val(unsigned char c)\n{\n\tint val;\n\tif (isdigit(c))\n\t\tval = c - '0';\n\telse if (isupper(c))\n\t\tval = c - 'A' + 10;\n\telse\n\t\tval = c - 'a' + 10;\n\treturn val;\n}\n\nstatic void\ncmd_flex_filter_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tint ret = 0;\n\tstruct rte_eth_flex_filter filter;\n\tstruct cmd_flex_filter_result *res = parsed_result;\n\tchar *bytes_ptr, *mask_ptr;\n\tuint16_t len, i, j = 0;\n\tchar c;\n\tint val;\n\tuint8_t byte = 0;\n\n\tif (res->len_value > RTE_FLEX_FILTER_MAXLEN) {\n\t\tprintf(\"the len exceed the max length 128\\n\");\n\t\treturn;\n\t}\n\tmemset(&filter, 0, sizeof(struct rte_eth_flex_filter));\n\tfilter.len = res->len_value;\n\tfilter.priority = res->priority_value;\n\tfilter.queue = res->queue_id;\n\tbytes_ptr = res->bytes_value;\n\tmask_ptr = res->mask_value;\n\n\t /* translate bytes string to array. */\n\tif (bytes_ptr[0] == '0' && ((bytes_ptr[1] == 'x') ||\n\t\t(bytes_ptr[1] == 'X')))\n\t\tbytes_ptr += 2;\n\tlen = strnlen(bytes_ptr, res->len_value * 2);\n\tif (len == 0 || (len % 8 != 0)) {\n\t\tprintf(\"please check len and bytes input\\n\");\n\t\treturn;\n\t}\n\tfor (i = 0; i < len; i++) {\n\t\tc = bytes_ptr[i];\n\t\tif (isxdigit(c) == 0) {\n\t\t\t/* invalid characters. */\n\t\t\tprintf(\"invalid input\\n\");\n\t\t\treturn;\n\t\t}\n\t\tval = xdigit2val(c);\n\t\tif (i % 2) {\n\t\t\tbyte |= val;\n\t\t\tfilter.bytes[j] = byte;\n\t\t\tprintf(\"bytes[%d]:%02x \", j, filter.bytes[j]);\n\t\t\tj++;\n\t\t\tbyte = 0;\n\t\t} else\n\t\t\tbyte |= val << 4;\n\t}\n\tprintf(\"\\n\");\n\t /* translate mask string to uint8_t array. */\n\tif (mask_ptr[0] == '0' && ((mask_ptr[1] == 'x') ||\n\t\t(mask_ptr[1] == 'X')))\n\t\tmask_ptr += 2;\n\tlen = strnlen(mask_ptr, (res->len_value + 3) / 4);\n\tif (len == 0) {\n\t\tprintf(\"invalid input\\n\");\n\t\treturn;\n\t}\n\tj = 0;\n\tbyte = 0;\n\tfor (i = 0; i < len; i++) {\n\t\tc = mask_ptr[i];\n\t\tif (isxdigit(c) == 0) {\n\t\t\t/* invalid characters. */\n\t\t\tprintf(\"invalid input\\n\");\n\t\t\treturn;\n\t\t}\n\t\tval = xdigit2val(c);\n\t\tif (i % 2) {\n\t\t\tbyte |= val;\n\t\t\tfilter.mask[j] = byte;\n\t\t\tprintf(\"mask[%d]:%02x \", j, filter.mask[j]);\n\t\t\tj++;\n\t\t\tbyte = 0;\n\t\t} else\n\t\t\tbyte |= val << 4;\n\t}\n\tprintf(\"\\n\");\n\n\tif (!strcmp(res->ops, \"add\"))\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\tRTE_ETH_FILTER_FLEXIBLE,\n\t\t\t\tRTE_ETH_FILTER_ADD,\n\t\t\t\t&filter);\n\telse\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\tRTE_ETH_FILTER_FLEXIBLE,\n\t\t\t\tRTE_ETH_FILTER_DELETE,\n\t\t\t\t&filter);\n\n\tif (ret < 0)\n\t\tprintf(\"flex filter setting error: (%s)\\n\", strerror(-ret));\n}\n\ncmdline_parse_token_string_t cmd_flex_filter_filter =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tfilter, \"flex_filter\");\ncmdline_parse_token_num_t cmd_flex_filter_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tport_id, UINT8);\ncmdline_parse_token_string_t cmd_flex_filter_ops =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tops, \"add#del\");\ncmdline_parse_token_string_t cmd_flex_filter_len =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tlen, \"len\");\ncmdline_parse_token_num_t cmd_flex_filter_len_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tlen_value, UINT8);\ncmdline_parse_token_string_t cmd_flex_filter_bytes =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tbytes, \"bytes\");\ncmdline_parse_token_string_t cmd_flex_filter_bytes_value =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tbytes_value, NULL);\ncmdline_parse_token_string_t cmd_flex_filter_mask =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tmask, \"mask\");\ncmdline_parse_token_string_t cmd_flex_filter_mask_value =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tmask_value, NULL);\ncmdline_parse_token_string_t cmd_flex_filter_priority =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tpriority, \"priority\");\ncmdline_parse_token_num_t cmd_flex_filter_priority_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tpriority_value, UINT8);\ncmdline_parse_token_string_t cmd_flex_filter_queue =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tqueue, \"queue\");\ncmdline_parse_token_num_t cmd_flex_filter_queue_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flex_filter_result,\n\t\t\t\tqueue_id, UINT16);\ncmdline_parse_inst_t cmd_flex_filter = {\n\t.f = cmd_flex_filter_parsed,\n\t.data = NULL,\n\t.help_str = \"add/del a flex filter\",\n\t.tokens = {\n\t\t(void *)&cmd_flex_filter_filter,\n\t\t(void *)&cmd_flex_filter_port_id,\n\t\t(void *)&cmd_flex_filter_ops,\n\t\t(void *)&cmd_flex_filter_len,\n\t\t(void *)&cmd_flex_filter_len_value,\n\t\t(void *)&cmd_flex_filter_bytes,\n\t\t(void *)&cmd_flex_filter_bytes_value,\n\t\t(void *)&cmd_flex_filter_mask,\n\t\t(void *)&cmd_flex_filter_mask_value,\n\t\t(void *)&cmd_flex_filter_priority,\n\t\t(void *)&cmd_flex_filter_priority_value,\n\t\t(void *)&cmd_flex_filter_queue,\n\t\t(void *)&cmd_flex_filter_queue_id,\n\t\tNULL,\n\t},\n};\n\n/* *** Filters Control *** */\n\n/* *** deal with ethertype filter *** */\nstruct cmd_ethertype_filter_result {\n\tcmdline_fixed_string_t filter;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t ops;\n\tcmdline_fixed_string_t mac;\n\tstruct ether_addr mac_addr;\n\tcmdline_fixed_string_t ethertype;\n\tuint16_t ethertype_value;\n\tcmdline_fixed_string_t drop;\n\tcmdline_fixed_string_t queue;\n\tuint16_t queue_id;\n};\n\ncmdline_parse_token_string_t cmd_ethertype_filter_filter =\n\tTOKEN_STRING_INITIALIZER(struct cmd_ethertype_filter_result,\n\t\t\t\t filter, \"ethertype_filter\");\ncmdline_parse_token_num_t cmd_ethertype_filter_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_ethertype_filter_result,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_string_t cmd_ethertype_filter_ops =\n\tTOKEN_STRING_INITIALIZER(struct cmd_ethertype_filter_result,\n\t\t\t\t ops, \"add#del\");\ncmdline_parse_token_string_t cmd_ethertype_filter_mac =\n\tTOKEN_STRING_INITIALIZER(struct cmd_ethertype_filter_result,\n\t\t\t\t mac, \"mac_addr#mac_ignr\");\ncmdline_parse_token_etheraddr_t cmd_ethertype_filter_mac_addr =\n\tTOKEN_ETHERADDR_INITIALIZER(struct cmd_ethertype_filter_result,\n\t\t\t\t mac_addr);\ncmdline_parse_token_string_t cmd_ethertype_filter_ethertype =\n\tTOKEN_STRING_INITIALIZER(struct cmd_ethertype_filter_result,\n\t\t\t\t ethertype, \"ethertype\");\ncmdline_parse_token_num_t cmd_ethertype_filter_ethertype_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_ethertype_filter_result,\n\t\t\t ethertype_value, UINT16);\ncmdline_parse_token_string_t cmd_ethertype_filter_drop =\n\tTOKEN_STRING_INITIALIZER(struct cmd_ethertype_filter_result,\n\t\t\t\t drop, \"drop#fwd\");\ncmdline_parse_token_string_t cmd_ethertype_filter_queue =\n\tTOKEN_STRING_INITIALIZER(struct cmd_ethertype_filter_result,\n\t\t\t\t queue, \"queue\");\ncmdline_parse_token_num_t cmd_ethertype_filter_queue_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_ethertype_filter_result,\n\t\t\t queue_id, UINT16);\n\nstatic void\ncmd_ethertype_filter_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_ethertype_filter_result *res = parsed_result;\n\tstruct rte_eth_ethertype_filter filter;\n\tint ret = 0;\n\n\tret = rte_eth_dev_filter_supported(res->port_id,\n\t\t\tRTE_ETH_FILTER_ETHERTYPE);\n\tif (ret < 0) {\n\t\tprintf(\"ethertype filter is not supported on port %u.\\n\",\n\t\t\tres->port_id);\n\t\treturn;\n\t}\n\n\tmemset(&filter, 0, sizeof(filter));\n\tif (!strcmp(res->mac, \"mac_addr\")) {\n\t\tfilter.flags |= RTE_ETHTYPE_FLAGS_MAC;\n\t\t(void)rte_memcpy(&filter.mac_addr, &res->mac_addr,\n\t\t\tsizeof(struct ether_addr));\n\t}\n\tif (!strcmp(res->drop, \"drop\"))\n\t\tfilter.flags |= RTE_ETHTYPE_FLAGS_DROP;\n\tfilter.ether_type = res->ethertype_value;\n\tfilter.queue = res->queue_id;\n\n\tif (!strcmp(res->ops, \"add\"))\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\tRTE_ETH_FILTER_ETHERTYPE,\n\t\t\t\tRTE_ETH_FILTER_ADD,\n\t\t\t\t&filter);\n\telse\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id,\n\t\t\t\tRTE_ETH_FILTER_ETHERTYPE,\n\t\t\t\tRTE_ETH_FILTER_DELETE,\n\t\t\t\t&filter);\n\tif (ret < 0)\n\t\tprintf(\"ethertype filter programming error: (%s)\\n\",\n\t\t\tstrerror(-ret));\n}\n\ncmdline_parse_inst_t cmd_ethertype_filter = {\n\t.f = cmd_ethertype_filter_parsed,\n\t.data = NULL,\n\t.help_str = \"add or delete an ethertype filter entry\",\n\t.tokens = {\n\t\t(void *)&cmd_ethertype_filter_filter,\n\t\t(void *)&cmd_ethertype_filter_port_id,\n\t\t(void *)&cmd_ethertype_filter_ops,\n\t\t(void *)&cmd_ethertype_filter_mac,\n\t\t(void *)&cmd_ethertype_filter_mac_addr,\n\t\t(void *)&cmd_ethertype_filter_ethertype,\n\t\t(void *)&cmd_ethertype_filter_ethertype_value,\n\t\t(void *)&cmd_ethertype_filter_drop,\n\t\t(void *)&cmd_ethertype_filter_queue,\n\t\t(void *)&cmd_ethertype_filter_queue_id,\n\t\tNULL,\n\t},\n};\n\n/* *** deal with flow director filter *** */\nstruct cmd_flow_director_result {\n\tcmdline_fixed_string_t flow_director_filter;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t ops;\n\tcmdline_fixed_string_t flow;\n\tcmdline_fixed_string_t flow_type;\n\tcmdline_fixed_string_t ether;\n\tuint16_t ether_type;\n\tcmdline_fixed_string_t src;\n\tcmdline_ipaddr_t ip_src;\n\tuint16_t port_src;\n\tcmdline_fixed_string_t dst;\n\tcmdline_ipaddr_t ip_dst;\n\tuint16_t port_dst;\n\tcmdline_fixed_string_t verify_tag;\n\tuint32_t verify_tag_value;\n\tcmdline_fixed_string_t vlan;\n\tuint16_t vlan_value;\n\tcmdline_fixed_string_t flexbytes;\n\tcmdline_fixed_string_t flexbytes_value;\n\tcmdline_fixed_string_t drop;\n\tcmdline_fixed_string_t queue;\n\tuint16_t queue_id;\n\tcmdline_fixed_string_t fd_id;\n\tuint32_t fd_id_value;\n};\n\nstatic inline int\nparse_flexbytes(const char *q_arg, uint8_t *flexbytes, uint16_t max_num)\n{\n\tchar s[256];\n\tconst char *p, *p0 = q_arg;\n\tchar *end;\n\tunsigned long int_fld;\n\tchar *str_fld[max_num];\n\tint i;\n\tunsigned size;\n\tint ret = -1;\n\n\tp = strchr(p0, '(');\n\tif (p == NULL)\n\t\treturn -1;\n\t++p;\n\tp0 = strchr(p, ')');\n\tif (p0 == NULL)\n\t\treturn -1;\n\n\tsize = p0 - p;\n\tif (size >= sizeof(s))\n\t\treturn -1;\n\n\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\tret = rte_strsplit(s, sizeof(s), str_fld, max_num, ',');\n\tif (ret < 0 || ret > max_num)\n\t\treturn -1;\n\tfor (i = 0; i < ret; i++) {\n\t\terrno = 0;\n\t\tint_fld = strtoul(str_fld[i], &end, 0);\n\t\tif (errno != 0 || *end != '\\0' || int_fld > UINT8_MAX)\n\t\t\treturn -1;\n\t\tflexbytes[i] = (uint8_t)int_fld;\n\t}\n\treturn ret;\n}\n\nstatic uint16_t\nstr2flowtype(char *string)\n{\n\tuint8_t i = 0;\n\tstatic const struct {\n\t\tchar str[32];\n\t\tuint16_t type;\n\t} flowtype_str[] = {\n\t\t{\"raw\", RTE_ETH_FLOW_RAW},\n\t\t{\"ipv4\", RTE_ETH_FLOW_IPV4},\n\t\t{\"ipv4-frag\", RTE_ETH_FLOW_FRAG_IPV4},\n\t\t{\"ipv4-tcp\", RTE_ETH_FLOW_NONFRAG_IPV4_TCP},\n\t\t{\"ipv4-udp\", RTE_ETH_FLOW_NONFRAG_IPV4_UDP},\n\t\t{\"ipv4-sctp\", RTE_ETH_FLOW_NONFRAG_IPV4_SCTP},\n\t\t{\"ipv4-other\", RTE_ETH_FLOW_NONFRAG_IPV4_OTHER},\n\t\t{\"ipv6\", RTE_ETH_FLOW_IPV6},\n\t\t{\"ipv6-frag\", RTE_ETH_FLOW_FRAG_IPV6},\n\t\t{\"ipv6-tcp\", RTE_ETH_FLOW_NONFRAG_IPV6_TCP},\n\t\t{\"ipv6-udp\", RTE_ETH_FLOW_NONFRAG_IPV6_UDP},\n\t\t{\"ipv6-sctp\", RTE_ETH_FLOW_NONFRAG_IPV6_SCTP},\n\t\t{\"ipv6-other\", RTE_ETH_FLOW_NONFRAG_IPV6_OTHER},\n\t\t{\"l2_payload\", RTE_ETH_FLOW_L2_PAYLOAD},\n\t};\n\n\tfor (i = 0; i < RTE_DIM(flowtype_str); i++) {\n\t\tif (!strcmp(flowtype_str[i].str, string))\n\t\t\treturn flowtype_str[i].type;\n\t}\n\treturn RTE_ETH_FLOW_UNKNOWN;\n}\n\n#define IPV4_ADDR_TO_UINT(ip_addr, ip) \\\ndo { \\\n\tif ((ip_addr).family == AF_INET) \\\n\t\t(ip) = (ip_addr).addr.ipv4.s_addr; \\\n\telse { \\\n\t\tprintf(\"invalid parameter.\\n\"); \\\n\t\treturn; \\\n\t} \\\n} while (0)\n\n#define IPV6_ADDR_TO_ARRAY(ip_addr, ip) \\\ndo { \\\n\tif ((ip_addr).family == AF_INET6) \\\n\t\t(void)rte_memcpy(&(ip), \\\n\t\t\t\t &((ip_addr).addr.ipv6), \\\n\t\t\t\t sizeof(struct in6_addr)); \\\n\telse { \\\n\t\tprintf(\"invalid parameter.\\n\"); \\\n\t\treturn; \\\n\t} \\\n} while (0)\n\nstatic void\ncmd_flow_director_filter_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_flow_director_result *res = parsed_result;\n\tstruct rte_eth_fdir_filter entry;\n\tuint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];\n\tint ret = 0;\n\n\tret = rte_eth_dev_filter_supported(res->port_id, RTE_ETH_FILTER_FDIR);\n\tif (ret < 0) {\n\t\tprintf(\"flow director is not supported on port %u.\\n\",\n\t\t\tres->port_id);\n\t\treturn;\n\t}\n\tmemset(flexbytes, 0, sizeof(flexbytes));\n\tmemset(&entry, 0, sizeof(struct rte_eth_fdir_filter));\n\tret = parse_flexbytes(res->flexbytes_value,\n\t\t\t\t\tflexbytes,\n\t\t\t\t\tRTE_ETH_FDIR_MAX_FLEXLEN);\n\tif (ret < 0) {\n\t\tprintf(\"error: Cannot parse flexbytes input.\\n\");\n\t\treturn;\n\t}\n\n\tentry.input.flow_type = str2flowtype(res->flow_type);\n\tswitch (entry.input.flow_type) {\n\tcase RTE_ETH_FLOW_FRAG_IPV4:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_UDP:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_TCP:\n\t\tIPV4_ADDR_TO_UINT(res->ip_dst,\n\t\t\tentry.input.flow.ip4_flow.dst_ip);\n\t\tIPV4_ADDR_TO_UINT(res->ip_src,\n\t\t\tentry.input.flow.ip4_flow.src_ip);\n\t\t/* need convert to big endian. */\n\t\tentry.input.flow.udp4_flow.dst_port =\n\t\t\t\trte_cpu_to_be_16(res->port_dst);\n\t\tentry.input.flow.udp4_flow.src_port =\n\t\t\t\trte_cpu_to_be_16(res->port_src);\n\t\tbreak;\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:\n\t\tIPV4_ADDR_TO_UINT(res->ip_dst,\n\t\t\tentry.input.flow.sctp4_flow.ip.dst_ip);\n\t\tIPV4_ADDR_TO_UINT(res->ip_src,\n\t\t\tentry.input.flow.sctp4_flow.ip.src_ip);\n\t\t/* need convert to big endian. */\n#ifdef RTE_NEXT_ABI\n\t\tentry.input.flow.sctp4_flow.dst_port =\n\t\t\t\trte_cpu_to_be_16(res->port_dst);\n\t\tentry.input.flow.sctp4_flow.src_port =\n\t\t\t\trte_cpu_to_be_16(res->port_src);\n#endif\n\t\tentry.input.flow.sctp4_flow.verify_tag =\n\t\t\t\trte_cpu_to_be_32(res->verify_tag_value);\n\t\tbreak;\n\tcase RTE_ETH_FLOW_FRAG_IPV6:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_UDP:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_TCP:\n\t\tIPV6_ADDR_TO_ARRAY(res->ip_dst,\n\t\t\tentry.input.flow.ipv6_flow.dst_ip);\n\t\tIPV6_ADDR_TO_ARRAY(res->ip_src,\n\t\t\tentry.input.flow.ipv6_flow.src_ip);\n\t\t/* need convert to big endian. */\n\t\tentry.input.flow.udp6_flow.dst_port =\n\t\t\t\trte_cpu_to_be_16(res->port_dst);\n\t\tentry.input.flow.udp6_flow.src_port =\n\t\t\t\trte_cpu_to_be_16(res->port_src);\n\t\tbreak;\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:\n\t\tIPV6_ADDR_TO_ARRAY(res->ip_dst,\n\t\t\tentry.input.flow.sctp6_flow.ip.dst_ip);\n\t\tIPV6_ADDR_TO_ARRAY(res->ip_src,\n\t\t\tentry.input.flow.sctp6_flow.ip.src_ip);\n\t\t/* need convert to big endian. */\n#ifdef RTE_NEXT_ABI\n\t\tentry.input.flow.sctp6_flow.dst_port =\n\t\t\t\trte_cpu_to_be_16(res->port_dst);\n\t\tentry.input.flow.sctp6_flow.src_port =\n\t\t\t\trte_cpu_to_be_16(res->port_src);\n#endif\n\t\tentry.input.flow.sctp6_flow.verify_tag =\n\t\t\t\trte_cpu_to_be_32(res->verify_tag_value);\n\t\tbreak;\n\tcase RTE_ETH_FLOW_L2_PAYLOAD:\n\t\tentry.input.flow.l2_flow.ether_type =\n\t\t\trte_cpu_to_be_16(res->ether_type);\n\t\tbreak;\n\tdefault:\n\t\tprintf(\"invalid parameter.\\n\");\n\t\treturn;\n\t}\n\t(void)rte_memcpy(entry.input.flow_ext.flexbytes,\n\t\t flexbytes,\n\t\t RTE_ETH_FDIR_MAX_FLEXLEN);\n\n\tentry.input.flow_ext.vlan_tci = rte_cpu_to_be_16(res->vlan_value);\n\n\tentry.action.flex_off = 0; /*use 0 by default */\n\tif (!strcmp(res->drop, \"drop\"))\n\t\tentry.action.behavior = RTE_ETH_FDIR_REJECT;\n\telse\n\t\tentry.action.behavior = RTE_ETH_FDIR_ACCEPT;\n\t/* set to report FD ID by default */\n\tentry.action.report_status = RTE_ETH_FDIR_REPORT_ID;\n\tentry.action.rx_queue = res->queue_id;\n\tentry.soft_id = res->fd_id_value;\n\tif (!strcmp(res->ops, \"add\"))\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id, RTE_ETH_FILTER_FDIR,\n\t\t\t\t\t RTE_ETH_FILTER_ADD, &entry);\n\telse if (!strcmp(res->ops, \"del\"))\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id, RTE_ETH_FILTER_FDIR,\n\t\t\t\t\t RTE_ETH_FILTER_DELETE, &entry);\n\telse\n\t\tret = rte_eth_dev_filter_ctrl(res->port_id, RTE_ETH_FILTER_FDIR,\n\t\t\t\t\t RTE_ETH_FILTER_UPDATE, &entry);\n\tif (ret < 0)\n\t\tprintf(\"flow director programming error: (%s)\\n\",\n\t\t\tstrerror(-ret));\n}\n\ncmdline_parse_token_string_t cmd_flow_director_filter =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t flow_director_filter, \"flow_director_filter\");\ncmdline_parse_token_num_t cmd_flow_director_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_string_t cmd_flow_director_ops =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t ops, \"add#del#update\");\ncmdline_parse_token_string_t cmd_flow_director_flow =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t flow, \"flow\");\ncmdline_parse_token_string_t cmd_flow_director_flow_type =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\tflow_type, \"ipv4-other#ipv4-frag#ipv4-tcp#ipv4-udp#ipv4-sctp#\"\n\t\t\"ipv6-other#ipv6-frag#ipv6-tcp#ipv6-udp#ipv6-sctp#l2_payload\");\ncmdline_parse_token_string_t cmd_flow_director_ether =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t ether, \"ether\");\ncmdline_parse_token_num_t cmd_flow_director_ether_type =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t ether_type, UINT16);\ncmdline_parse_token_string_t cmd_flow_director_src =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t src, \"src\");\ncmdline_parse_token_ipaddr_t cmd_flow_director_ip_src =\n\tTOKEN_IPADDR_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t ip_src);\ncmdline_parse_token_num_t cmd_flow_director_port_src =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t port_src, UINT16);\ncmdline_parse_token_string_t cmd_flow_director_dst =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t dst, \"dst\");\ncmdline_parse_token_ipaddr_t cmd_flow_director_ip_dst =\n\tTOKEN_IPADDR_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t ip_dst);\ncmdline_parse_token_num_t cmd_flow_director_port_dst =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t port_dst, UINT16);\ncmdline_parse_token_string_t cmd_flow_director_verify_tag =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t verify_tag, \"verify_tag\");\ncmdline_parse_token_num_t cmd_flow_director_verify_tag_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t verify_tag_value, UINT32);\ncmdline_parse_token_string_t cmd_flow_director_vlan =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t vlan, \"vlan\");\ncmdline_parse_token_num_t cmd_flow_director_vlan_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t vlan_value, UINT16);\ncmdline_parse_token_string_t cmd_flow_director_flexbytes =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t flexbytes, \"flexbytes\");\ncmdline_parse_token_string_t cmd_flow_director_flexbytes_value =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t flexbytes_value, NULL);\ncmdline_parse_token_string_t cmd_flow_director_drop =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t drop, \"drop#fwd\");\ncmdline_parse_token_string_t cmd_flow_director_queue =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t queue, \"queue\");\ncmdline_parse_token_num_t cmd_flow_director_queue_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t queue_id, UINT16);\ncmdline_parse_token_string_t cmd_flow_director_fd_id =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t\t fd_id, \"fd_id\");\ncmdline_parse_token_num_t cmd_flow_director_fd_id_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_result,\n\t\t\t fd_id_value, UINT32);\n\ncmdline_parse_inst_t cmd_add_del_ip_flow_director = {\n\t.f = cmd_flow_director_filter_parsed,\n\t.data = NULL,\n\t.help_str = \"add or delete an ip flow director entry on NIC\",\n\t.tokens = {\n\t\t(void *)&cmd_flow_director_filter,\n\t\t(void *)&cmd_flow_director_port_id,\n\t\t(void *)&cmd_flow_director_ops,\n\t\t(void *)&cmd_flow_director_flow,\n\t\t(void *)&cmd_flow_director_flow_type,\n\t\t(void *)&cmd_flow_director_src,\n\t\t(void *)&cmd_flow_director_ip_src,\n\t\t(void *)&cmd_flow_director_dst,\n\t\t(void *)&cmd_flow_director_ip_dst,\n\t\t(void *)&cmd_flow_director_vlan,\n\t\t(void *)&cmd_flow_director_vlan_value,\n\t\t(void *)&cmd_flow_director_flexbytes,\n\t\t(void *)&cmd_flow_director_flexbytes_value,\n\t\t(void *)&cmd_flow_director_drop,\n\t\t(void *)&cmd_flow_director_queue,\n\t\t(void *)&cmd_flow_director_queue_id,\n\t\t(void *)&cmd_flow_director_fd_id,\n\t\t(void *)&cmd_flow_director_fd_id_value,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_add_del_udp_flow_director = {\n\t.f = cmd_flow_director_filter_parsed,\n\t.data = NULL,\n\t.help_str = \"add or delete an udp/tcp flow director entry on NIC\",\n\t.tokens = {\n\t\t(void *)&cmd_flow_director_filter,\n\t\t(void *)&cmd_flow_director_port_id,\n\t\t(void *)&cmd_flow_director_ops,\n\t\t(void *)&cmd_flow_director_flow,\n\t\t(void *)&cmd_flow_director_flow_type,\n\t\t(void *)&cmd_flow_director_src,\n\t\t(void *)&cmd_flow_director_ip_src,\n\t\t(void *)&cmd_flow_director_port_src,\n\t\t(void *)&cmd_flow_director_dst,\n\t\t(void *)&cmd_flow_director_ip_dst,\n\t\t(void *)&cmd_flow_director_port_dst,\n\t\t(void *)&cmd_flow_director_vlan,\n\t\t(void *)&cmd_flow_director_vlan_value,\n\t\t(void *)&cmd_flow_director_flexbytes,\n\t\t(void *)&cmd_flow_director_flexbytes_value,\n\t\t(void *)&cmd_flow_director_drop,\n\t\t(void *)&cmd_flow_director_queue,\n\t\t(void *)&cmd_flow_director_queue_id,\n\t\t(void *)&cmd_flow_director_fd_id,\n\t\t(void *)&cmd_flow_director_fd_id_value,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_add_del_sctp_flow_director = {\n\t.f = cmd_flow_director_filter_parsed,\n\t.data = NULL,\n\t.help_str = \"add or delete a sctp flow director entry on NIC\",\n\t.tokens = {\n\t\t(void *)&cmd_flow_director_filter,\n\t\t(void *)&cmd_flow_director_port_id,\n\t\t(void *)&cmd_flow_director_ops,\n\t\t(void *)&cmd_flow_director_flow,\n\t\t(void *)&cmd_flow_director_flow_type,\n\t\t(void *)&cmd_flow_director_src,\n\t\t(void *)&cmd_flow_director_ip_src,\n\t\t(void *)&cmd_flow_director_port_dst,\n\t\t(void *)&cmd_flow_director_dst,\n\t\t(void *)&cmd_flow_director_ip_dst,\n\t\t(void *)&cmd_flow_director_port_dst,\n\t\t(void *)&cmd_flow_director_verify_tag,\n\t\t(void *)&cmd_flow_director_verify_tag_value,\n\t\t(void *)&cmd_flow_director_vlan,\n\t\t(void *)&cmd_flow_director_vlan_value,\n\t\t(void *)&cmd_flow_director_flexbytes,\n\t\t(void *)&cmd_flow_director_flexbytes_value,\n\t\t(void *)&cmd_flow_director_drop,\n\t\t(void *)&cmd_flow_director_queue,\n\t\t(void *)&cmd_flow_director_queue_id,\n\t\t(void *)&cmd_flow_director_fd_id,\n\t\t(void *)&cmd_flow_director_fd_id_value,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_inst_t cmd_add_del_l2_flow_director = {\n\t.f = cmd_flow_director_filter_parsed,\n\t.data = NULL,\n\t.help_str = \"add or delete a L2 flow director entry on NIC\",\n\t.tokens = {\n\t\t(void *)&cmd_flow_director_filter,\n\t\t(void *)&cmd_flow_director_port_id,\n\t\t(void *)&cmd_flow_director_ops,\n\t\t(void *)&cmd_flow_director_flow,\n\t\t(void *)&cmd_flow_director_flow_type,\n\t\t(void *)&cmd_flow_director_ether,\n\t\t(void *)&cmd_flow_director_ether_type,\n\t\t(void *)&cmd_flow_director_flexbytes,\n\t\t(void *)&cmd_flow_director_flexbytes_value,\n\t\t(void *)&cmd_flow_director_drop,\n\t\t(void *)&cmd_flow_director_queue,\n\t\t(void *)&cmd_flow_director_queue_id,\n\t\t(void *)&cmd_flow_director_fd_id,\n\t\t(void *)&cmd_flow_director_fd_id_value,\n\t\tNULL,\n\t},\n};\n\nstruct cmd_flush_flow_director_result {\n\tcmdline_fixed_string_t flush_flow_director;\n\tuint8_t port_id;\n};\n\ncmdline_parse_token_string_t cmd_flush_flow_director_flush =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flush_flow_director_result,\n\t\t\t\t flush_flow_director, \"flush_flow_director\");\ncmdline_parse_token_num_t cmd_flush_flow_director_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flush_flow_director_result,\n\t\t\t port_id, UINT8);\n\nstatic void\ncmd_flush_flow_director_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_flow_director_result *res = parsed_result;\n\tint ret = 0;\n\n\tret = rte_eth_dev_filter_supported(res->port_id, RTE_ETH_FILTER_FDIR);\n\tif (ret < 0) {\n\t\tprintf(\"flow director is not supported on port %u.\\n\",\n\t\t\tres->port_id);\n\t\treturn;\n\t}\n\n\tret = rte_eth_dev_filter_ctrl(res->port_id, RTE_ETH_FILTER_FDIR,\n\t\t\tRTE_ETH_FILTER_FLUSH, NULL);\n\tif (ret < 0)\n\t\tprintf(\"flow director table flushing error: (%s)\\n\",\n\t\t\tstrerror(-ret));\n}\n\ncmdline_parse_inst_t cmd_flush_flow_director = {\n\t.f = cmd_flush_flow_director_parsed,\n\t.data = NULL,\n\t.help_str = \"flush all flow director entries of a device on NIC\",\n\t.tokens = {\n\t\t(void *)&cmd_flush_flow_director_flush,\n\t\t(void *)&cmd_flush_flow_director_port_id,\n\t\tNULL,\n\t},\n};\n\n/* *** deal with flow director mask *** */\nstruct cmd_flow_director_mask_result {\n\tcmdline_fixed_string_t flow_director_mask;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t vlan;\n\tuint16_t vlan_value;\n\tcmdline_fixed_string_t src_mask;\n\tcmdline_ipaddr_t ipv4_src;\n\tcmdline_ipaddr_t ipv6_src;\n\tuint16_t port_src;\n\tcmdline_fixed_string_t dst_mask;\n\tcmdline_ipaddr_t ipv4_dst;\n\tcmdline_ipaddr_t ipv6_dst;\n\tuint16_t port_dst;\n};\n\nstatic void\ncmd_flow_director_mask_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_flow_director_mask_result *res = parsed_result;\n\tstruct rte_eth_fdir_masks *mask;\n\tstruct rte_port *port;\n\n\tif (res->port_id > nb_ports) {\n\t\tprintf(\"Invalid port, range is [0, %d]\\n\", nb_ports - 1);\n\t\treturn;\n\t}\n\n\tport = &ports[res->port_id];\n\t/** Check if the port is not started **/\n\tif (port->port_status != RTE_PORT_STOPPED) {\n\t\tprintf(\"Please stop port %d first\\n\", res->port_id);\n\t\treturn;\n\t}\n\tmask = &port->dev_conf.fdir_conf.mask;\n\n\tmask->vlan_tci_mask = res->vlan_value;\n\tIPV4_ADDR_TO_UINT(res->ipv4_src, mask->ipv4_mask.src_ip);\n\tIPV4_ADDR_TO_UINT(res->ipv4_dst, mask->ipv4_mask.dst_ip);\n\tIPV6_ADDR_TO_ARRAY(res->ipv6_src, mask->ipv6_mask.src_ip);\n\tIPV6_ADDR_TO_ARRAY(res->ipv6_dst, mask->ipv6_mask.dst_ip);\n\tmask->src_port_mask = res->port_src;\n\tmask->dst_port_mask = res->port_dst;\n\n\tcmd_reconfig_device_queue(res->port_id, 1, 1);\n}\n\ncmdline_parse_token_string_t cmd_flow_director_mask =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_mask_result,\n\t\t\t\t flow_director_mask, \"flow_director_mask\");\ncmdline_parse_token_num_t cmd_flow_director_mask_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_mask_result,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_string_t cmd_flow_director_mask_vlan =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_mask_result,\n\t\t\t\t vlan, \"vlan\");\ncmdline_parse_token_num_t cmd_flow_director_mask_vlan_value =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_mask_result,\n\t\t\t vlan_value, UINT16);\ncmdline_parse_token_string_t cmd_flow_director_mask_src =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_mask_result,\n\t\t\t\t src_mask, \"src_mask\");\ncmdline_parse_token_ipaddr_t cmd_flow_director_mask_ipv4_src =\n\tTOKEN_IPADDR_INITIALIZER(struct cmd_flow_director_mask_result,\n\t\t\t\t ipv4_src);\ncmdline_parse_token_ipaddr_t cmd_flow_director_mask_ipv6_src =\n\tTOKEN_IPADDR_INITIALIZER(struct cmd_flow_director_mask_result,\n\t\t\t\t ipv6_src);\ncmdline_parse_token_num_t cmd_flow_director_mask_port_src =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_mask_result,\n\t\t\t port_src, UINT16);\ncmdline_parse_token_string_t cmd_flow_director_mask_dst =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_mask_result,\n\t\t\t\t dst_mask, \"dst_mask\");\ncmdline_parse_token_ipaddr_t cmd_flow_director_mask_ipv4_dst =\n\tTOKEN_IPADDR_INITIALIZER(struct cmd_flow_director_mask_result,\n\t\t\t\t ipv4_dst);\ncmdline_parse_token_ipaddr_t cmd_flow_director_mask_ipv6_dst =\n\tTOKEN_IPADDR_INITIALIZER(struct cmd_flow_director_mask_result,\n\t\t\t\t ipv6_dst);\ncmdline_parse_token_num_t cmd_flow_director_mask_port_dst =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_mask_result,\n\t\t\t port_dst, UINT16);\ncmdline_parse_inst_t cmd_set_flow_director_mask = {\n\t.f = cmd_flow_director_mask_parsed,\n\t.data = NULL,\n\t.help_str = \"set flow director's mask on NIC\",\n\t.tokens = {\n\t\t(void *)&cmd_flow_director_mask,\n\t\t(void *)&cmd_flow_director_mask_port_id,\n\t\t(void *)&cmd_flow_director_mask_vlan,\n\t\t(void *)&cmd_flow_director_mask_vlan_value,\n\t\t(void *)&cmd_flow_director_mask_src,\n\t\t(void *)&cmd_flow_director_mask_ipv4_src,\n\t\t(void *)&cmd_flow_director_mask_ipv6_src,\n\t\t(void *)&cmd_flow_director_mask_port_src,\n\t\t(void *)&cmd_flow_director_mask_dst,\n\t\t(void *)&cmd_flow_director_mask_ipv4_dst,\n\t\t(void *)&cmd_flow_director_mask_ipv6_dst,\n\t\t(void *)&cmd_flow_director_mask_port_dst,\n\t\tNULL,\n\t},\n};\n\n/* *** deal with flow director mask on flexible payload *** */\nstruct cmd_flow_director_flex_mask_result {\n\tcmdline_fixed_string_t flow_director_flexmask;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t flow;\n\tcmdline_fixed_string_t flow_type;\n\tcmdline_fixed_string_t mask;\n};\n\nstatic void\ncmd_flow_director_flex_mask_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_flow_director_flex_mask_result *res = parsed_result;\n\tstruct rte_eth_fdir_info fdir_info;\n\tstruct rte_eth_fdir_flex_mask flex_mask;\n\tstruct rte_port *port;\n\tuint32_t flow_type_mask;\n\tuint16_t i;\n\tint ret;\n\n\tif (res->port_id > nb_ports) {\n\t\tprintf(\"Invalid port, range is [0, %d]\\n\", nb_ports - 1);\n\t\treturn;\n\t}\n\n\tport = &ports[res->port_id];\n\t/** Check if the port is not started **/\n\tif (port->port_status != RTE_PORT_STOPPED) {\n\t\tprintf(\"Please stop port %d first\\n\", res->port_id);\n\t\treturn;\n\t}\n\n\tmemset(&flex_mask, 0, sizeof(struct rte_eth_fdir_flex_mask));\n\tret = parse_flexbytes(res->mask,\n\t\t\tflex_mask.mask,\n\t\t\tRTE_ETH_FDIR_MAX_FLEXLEN);\n\tif (ret < 0) {\n\t\tprintf(\"error: Cannot parse mask input.\\n\");\n\t\treturn;\n\t}\n\n\tmemset(&fdir_info, 0, sizeof(fdir_info));\n\tret = rte_eth_dev_filter_ctrl(res->port_id, RTE_ETH_FILTER_FDIR,\n\t\t\t\tRTE_ETH_FILTER_INFO, &fdir_info);\n\tif (ret < 0) {\n\t\tprintf(\"Cannot get FDir filter info\\n\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(res->flow_type, \"none\")) {\n\t\t/* means don't specify the flow type */\n\t\tflex_mask.flow_type = RTE_ETH_FLOW_UNKNOWN;\n\t\tfor (i = 0; i < RTE_ETH_FLOW_MAX; i++)\n\t\t\tmemset(&port->dev_conf.fdir_conf.flex_conf.flex_mask[i],\n\t\t\t 0, sizeof(struct rte_eth_fdir_flex_mask));\n\t\tport->dev_conf.fdir_conf.flex_conf.nb_flexmasks = 1;\n\t\t(void)rte_memcpy(&port->dev_conf.fdir_conf.flex_conf.flex_mask[0],\n\t\t\t\t &flex_mask,\n\t\t\t\t sizeof(struct rte_eth_fdir_flex_mask));\n\t\tcmd_reconfig_device_queue(res->port_id, 1, 1);\n\t\treturn;\n\t}\n\tflow_type_mask = fdir_info.flow_types_mask[0];\n\tif (!strcmp(res->flow_type, \"all\")) {\n\t\tif (!flow_type_mask) {\n\t\t\tprintf(\"No flow type supported\\n\");\n\t\t\treturn;\n\t\t}\n\t\tfor (i = RTE_ETH_FLOW_UNKNOWN; i < RTE_ETH_FLOW_MAX; i++) {\n\t\t\tif (flow_type_mask & (1 << i)) {\n\t\t\t\tflex_mask.flow_type = i;\n\t\t\t\tfdir_set_flex_mask(res->port_id, &flex_mask);\n\t\t\t}\n\t\t}\n\t\tcmd_reconfig_device_queue(res->port_id, 1, 1);\n\t\treturn;\n\t}\n\tflex_mask.flow_type = str2flowtype(res->flow_type);\n\tif (!(flow_type_mask & (1 << flex_mask.flow_type))) {\n\t\tprintf(\"Flow type %s not supported on port %d\\n\",\n\t\t\t\tres->flow_type, res->port_id);\n\t\treturn;\n\t}\n\tfdir_set_flex_mask(res->port_id, &flex_mask);\n\tcmd_reconfig_device_queue(res->port_id, 1, 1);\n}\n\ncmdline_parse_token_string_t cmd_flow_director_flexmask =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_flex_mask_result,\n\t\t\t\t flow_director_flexmask,\n\t\t\t\t \"flow_director_flex_mask\");\ncmdline_parse_token_num_t cmd_flow_director_flexmask_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_flex_mask_result,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_string_t cmd_flow_director_flexmask_flow =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_flex_mask_result,\n\t\t\t\t flow, \"flow\");\ncmdline_parse_token_string_t cmd_flow_director_flexmask_flow_type =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_flex_mask_result,\n\t\tflow_type, \"none#ipv4-other#ipv4-frag#ipv4-tcp#ipv4-udp#ipv4-sctp#\"\n\t\t\"ipv6-other#ipv6-frag#ipv6-tcp#ipv6-udp#ipv6-sctp#l2_payload#all\");\ncmdline_parse_token_string_t cmd_flow_director_flexmask_mask =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_flex_mask_result,\n\t\t\t\t mask, NULL);\n\ncmdline_parse_inst_t cmd_set_flow_director_flex_mask = {\n\t.f = cmd_flow_director_flex_mask_parsed,\n\t.data = NULL,\n\t.help_str = \"set flow director's flex mask on NIC\",\n\t.tokens = {\n\t\t(void *)&cmd_flow_director_flexmask,\n\t\t(void *)&cmd_flow_director_flexmask_port_id,\n\t\t(void *)&cmd_flow_director_flexmask_flow,\n\t\t(void *)&cmd_flow_director_flexmask_flow_type,\n\t\t(void *)&cmd_flow_director_flexmask_mask,\n\t\tNULL,\n\t},\n};\n\n/* *** deal with flow director flexible payload configuration *** */\nstruct cmd_flow_director_flexpayload_result {\n\tcmdline_fixed_string_t flow_director_flexpayload;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t payload_layer;\n\tcmdline_fixed_string_t payload_cfg;\n};\n\nstatic inline int\nparse_offsets(const char *q_arg, uint16_t *offsets, uint16_t max_num)\n{\n\tchar s[256];\n\tconst char *p, *p0 = q_arg;\n\tchar *end;\n\tunsigned long int_fld;\n\tchar *str_fld[max_num];\n\tint i;\n\tunsigned size;\n\tint ret = -1;\n\n\tp = strchr(p0, '(');\n\tif (p == NULL)\n\t\treturn -1;\n\t++p;\n\tp0 = strchr(p, ')');\n\tif (p0 == NULL)\n\t\treturn -1;\n\n\tsize = p0 - p;\n\tif (size >= sizeof(s))\n\t\treturn -1;\n\n\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\tret = rte_strsplit(s, sizeof(s), str_fld, max_num, ',');\n\tif (ret < 0 || ret > max_num)\n\t\treturn -1;\n\tfor (i = 0; i < ret; i++) {\n\t\terrno = 0;\n\t\tint_fld = strtoul(str_fld[i], &end, 0);\n\t\tif (errno != 0 || *end != '\\0' || int_fld > UINT16_MAX)\n\t\t\treturn -1;\n\t\toffsets[i] = (uint16_t)int_fld;\n\t}\n\treturn ret;\n}\n\nstatic void\ncmd_flow_director_flxpld_parsed(void *parsed_result,\n\t\t\t __attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_flow_director_flexpayload_result *res = parsed_result;\n\tstruct rte_eth_flex_payload_cfg flex_cfg;\n\tstruct rte_port *port;\n\tint ret = 0;\n\n\tif (res->port_id > nb_ports) {\n\t\tprintf(\"Invalid port, range is [0, %d]\\n\", nb_ports - 1);\n\t\treturn;\n\t}\n\n\tport = &ports[res->port_id];\n\t/** Check if the port is not started **/\n\tif (port->port_status != RTE_PORT_STOPPED) {\n\t\tprintf(\"Please stop port %d first\\n\", res->port_id);\n\t\treturn;\n\t}\n\n\tmemset(&flex_cfg, 0, sizeof(struct rte_eth_flex_payload_cfg));\n\n\tif (!strcmp(res->payload_layer, \"raw\"))\n\t\tflex_cfg.type = RTE_ETH_RAW_PAYLOAD;\n\telse if (!strcmp(res->payload_layer, \"l2\"))\n\t\tflex_cfg.type = RTE_ETH_L2_PAYLOAD;\n\telse if (!strcmp(res->payload_layer, \"l3\"))\n\t\tflex_cfg.type = RTE_ETH_L3_PAYLOAD;\n\telse if (!strcmp(res->payload_layer, \"l4\"))\n\t\tflex_cfg.type = RTE_ETH_L4_PAYLOAD;\n\n\tret = parse_offsets(res->payload_cfg, flex_cfg.src_offset,\n\t\t\t RTE_ETH_FDIR_MAX_FLEXLEN);\n\tif (ret < 0) {\n\t\tprintf(\"error: Cannot parse flex payload input.\\n\");\n\t\treturn;\n\t}\n\n\tfdir_set_flex_payload(res->port_id, &flex_cfg);\n\tcmd_reconfig_device_queue(res->port_id, 1, 1);\n}\n\ncmdline_parse_token_string_t cmd_flow_director_flexpayload =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_flexpayload_result,\n\t\t\t\t flow_director_flexpayload,\n\t\t\t\t \"flow_director_flex_payload\");\ncmdline_parse_token_num_t cmd_flow_director_flexpayload_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_flow_director_flexpayload_result,\n\t\t\t port_id, UINT8);\ncmdline_parse_token_string_t cmd_flow_director_flexpayload_payload_layer =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_flexpayload_result,\n\t\t\t\t payload_layer, \"raw#l2#l3#l4\");\ncmdline_parse_token_string_t cmd_flow_director_flexpayload_payload_cfg =\n\tTOKEN_STRING_INITIALIZER(struct cmd_flow_director_flexpayload_result,\n\t\t\t\t payload_cfg, NULL);\n\ncmdline_parse_inst_t cmd_set_flow_director_flex_payload = {\n\t.f = cmd_flow_director_flxpld_parsed,\n\t.data = NULL,\n\t.help_str = \"set flow director's flex payload on NIC\",\n\t.tokens = {\n\t\t(void *)&cmd_flow_director_flexpayload,\n\t\t(void *)&cmd_flow_director_flexpayload_port_id,\n\t\t(void *)&cmd_flow_director_flexpayload_payload_layer,\n\t\t(void *)&cmd_flow_director_flexpayload_payload_cfg,\n\t\tNULL,\n\t},\n};\n\n/* *** Classification Filters Control *** */\n/* *** Get symmetric hash enable per port *** */\nstruct cmd_get_sym_hash_ena_per_port_result {\n\tcmdline_fixed_string_t get_sym_hash_ena_per_port;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_get_sym_hash_per_port_parsed(void *parsed_result,\n\t\t\t\t __rte_unused struct cmdline *cl,\n\t\t\t\t __rte_unused void *data)\n{\n\tstruct cmd_get_sym_hash_ena_per_port_result *res = parsed_result;\n\tstruct rte_eth_hash_filter_info info;\n\tint ret;\n\n\tif (rte_eth_dev_filter_supported(res->port_id,\n\t\t\t\tRTE_ETH_FILTER_HASH) < 0) {\n\t\tprintf(\"RTE_ETH_FILTER_HASH not supported on port: %d\\n\",\n\t\t\t\t\t\t\tres->port_id);\n\t\treturn;\n\t}\n\n\tmemset(&info, 0, sizeof(info));\n\tinfo.info_type = RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT;\n\tret = rte_eth_dev_filter_ctrl(res->port_id, RTE_ETH_FILTER_HASH,\n\t\t\t\t\t\tRTE_ETH_FILTER_GET, &info);\n\n\tif (ret < 0) {\n\t\tprintf(\"Cannot get symmetric hash enable per port \"\n\t\t\t\t\t\"on port %u\\n\", res->port_id);\n\t\treturn;\n\t}\n\n\tprintf(\"Symmetric hash is %s on port %u\\n\", info.info.enable ?\n\t\t\t\t\"enabled\" : \"disabled\", res->port_id);\n}\n\ncmdline_parse_token_string_t cmd_get_sym_hash_ena_per_port_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_get_sym_hash_ena_per_port_result,\n\t\tget_sym_hash_ena_per_port, \"get_sym_hash_ena_per_port\");\ncmdline_parse_token_num_t cmd_get_sym_hash_ena_per_port_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_get_sym_hash_ena_per_port_result,\n\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_get_sym_hash_ena_per_port = {\n\t.f = cmd_get_sym_hash_per_port_parsed,\n\t.data = NULL,\n\t.help_str = \"get_sym_hash_ena_per_port port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_get_sym_hash_ena_per_port_all,\n\t\t(void *)&cmd_get_sym_hash_ena_per_port_port_id,\n\t\tNULL,\n\t},\n};\n\n/* *** Set symmetric hash enable per port *** */\nstruct cmd_set_sym_hash_ena_per_port_result {\n\tcmdline_fixed_string_t set_sym_hash_ena_per_port;\n\tcmdline_fixed_string_t enable;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_set_sym_hash_per_port_parsed(void *parsed_result,\n\t\t\t\t __rte_unused struct cmdline *cl,\n\t\t\t\t __rte_unused void *data)\n{\n\tstruct cmd_set_sym_hash_ena_per_port_result *res = parsed_result;\n\tstruct rte_eth_hash_filter_info info;\n\tint ret;\n\n\tif (rte_eth_dev_filter_supported(res->port_id,\n\t\t\t\tRTE_ETH_FILTER_HASH) < 0) {\n\t\tprintf(\"RTE_ETH_FILTER_HASH not supported on port: %d\\n\",\n\t\t\t\t\t\t\tres->port_id);\n\t\treturn;\n\t}\n\n\tmemset(&info, 0, sizeof(info));\n\tinfo.info_type = RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT;\n\tif (!strcmp(res->enable, \"enable\"))\n\t\tinfo.info.enable = 1;\n\tret = rte_eth_dev_filter_ctrl(res->port_id, RTE_ETH_FILTER_HASH,\n\t\t\t\t\tRTE_ETH_FILTER_SET, &info);\n\tif (ret < 0) {\n\t\tprintf(\"Cannot set symmetric hash enable per port on \"\n\t\t\t\t\t\"port %u\\n\", res->port_id);\n\t\treturn;\n\t}\n\tprintf(\"Symmetric hash has been set to %s on port %u\\n\",\n\t\t\t\t\tres->enable, res->port_id);\n}\n\ncmdline_parse_token_string_t cmd_set_sym_hash_ena_per_port_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_sym_hash_ena_per_port_result,\n\t\tset_sym_hash_ena_per_port, \"set_sym_hash_ena_per_port\");\ncmdline_parse_token_num_t cmd_set_sym_hash_ena_per_port_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_sym_hash_ena_per_port_result,\n\t\tport_id, UINT8);\ncmdline_parse_token_string_t cmd_set_sym_hash_ena_per_port_enable =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_sym_hash_ena_per_port_result,\n\t\tenable, \"enable#disable\");\n\ncmdline_parse_inst_t cmd_set_sym_hash_ena_per_port = {\n\t.f = cmd_set_sym_hash_per_port_parsed,\n\t.data = NULL,\n\t.help_str = \"set_sym_hash_ena_per_port port_id enable|disable\",\n\t.tokens = {\n\t\t(void *)&cmd_set_sym_hash_ena_per_port_all,\n\t\t(void *)&cmd_set_sym_hash_ena_per_port_port_id,\n\t\t(void *)&cmd_set_sym_hash_ena_per_port_enable,\n\t\tNULL,\n\t},\n};\n\n/* Get global config of hash function */\nstruct cmd_get_hash_global_config_result {\n\tcmdline_fixed_string_t get_hash_global_config;\n\tuint8_t port_id;\n};\n\nstatic char *\nflowtype_to_str(uint16_t ftype)\n{\n\tuint16_t i;\n\tstatic struct {\n\t\tchar str[16];\n\t\tuint16_t ftype;\n\t} ftype_table[] = {\n\t\t{\"ipv4\", RTE_ETH_FLOW_IPV4},\n\t\t{\"ipv4-frag\", RTE_ETH_FLOW_FRAG_IPV4},\n\t\t{\"ipv4-tcp\", RTE_ETH_FLOW_NONFRAG_IPV4_TCP},\n\t\t{\"ipv4-udp\", RTE_ETH_FLOW_NONFRAG_IPV4_UDP},\n\t\t{\"ipv4-sctp\", RTE_ETH_FLOW_NONFRAG_IPV4_SCTP},\n\t\t{\"ipv4-other\", RTE_ETH_FLOW_NONFRAG_IPV4_OTHER},\n\t\t{\"ipv6\", RTE_ETH_FLOW_IPV6},\n\t\t{\"ipv6-frag\", RTE_ETH_FLOW_FRAG_IPV6},\n\t\t{\"ipv6-tcp\", RTE_ETH_FLOW_NONFRAG_IPV6_TCP},\n\t\t{\"ipv6-udp\", RTE_ETH_FLOW_NONFRAG_IPV6_UDP},\n\t\t{\"ipv6-sctp\", RTE_ETH_FLOW_NONFRAG_IPV6_SCTP},\n\t\t{\"ipv6-other\", RTE_ETH_FLOW_NONFRAG_IPV6_OTHER},\n\t\t{\"l2_payload\", RTE_ETH_FLOW_L2_PAYLOAD},\n\t};\n\n\tfor (i = 0; i < RTE_DIM(ftype_table); i++) {\n\t\tif (ftype_table[i].ftype == ftype)\n\t\t\treturn ftype_table[i].str;\n\t}\n\n\treturn NULL;\n}\n\nstatic void\ncmd_get_hash_global_config_parsed(void *parsed_result,\n\t\t\t\t __rte_unused struct cmdline *cl,\n\t\t\t\t __rte_unused void *data)\n{\n\tstruct cmd_get_hash_global_config_result *res = parsed_result;\n\tstruct rte_eth_hash_filter_info info;\n\tuint32_t idx, offset;\n\tuint16_t i;\n\tchar *str;\n\tint ret;\n\n\tif (rte_eth_dev_filter_supported(res->port_id,\n\t\t\tRTE_ETH_FILTER_HASH) < 0) {\n\t\tprintf(\"RTE_ETH_FILTER_HASH not supported on port %d\\n\",\n\t\t\t\t\t\t\tres->port_id);\n\t\treturn;\n\t}\n\n\tmemset(&info, 0, sizeof(info));\n\tinfo.info_type = RTE_ETH_HASH_FILTER_GLOBAL_CONFIG;\n\tret = rte_eth_dev_filter_ctrl(res->port_id, RTE_ETH_FILTER_HASH,\n\t\t\t\t\tRTE_ETH_FILTER_GET, &info);\n\tif (ret < 0) {\n\t\tprintf(\"Cannot get hash global configurations by port %d\\n\",\n\t\t\t\t\t\t\tres->port_id);\n\t\treturn;\n\t}\n\n\tswitch (info.info.global_conf.hash_func) {\n\tcase RTE_ETH_HASH_FUNCTION_TOEPLITZ:\n\t\tprintf(\"Hash function is Toeplitz\\n\");\n\t\tbreak;\n\tcase RTE_ETH_HASH_FUNCTION_SIMPLE_XOR:\n\t\tprintf(\"Hash function is Simple XOR\\n\");\n\t\tbreak;\n\tdefault:\n\t\tprintf(\"Unknown hash function\\n\");\n\t\tbreak;\n\t}\n\n\tfor (i = 0; i < RTE_ETH_FLOW_MAX; i++) {\n\t\tidx = i / UINT32_BIT;\n\t\toffset = i % UINT32_BIT;\n\t\tif (!(info.info.global_conf.valid_bit_mask[idx] &\n\t\t\t\t\t\t(1UL << offset)))\n\t\t\tcontinue;\n\t\tstr = flowtype_to_str(i);\n\t\tif (!str)\n\t\t\tcontinue;\n\t\tprintf(\"Symmetric hash is %s globally for flow type %s \"\n\t\t\t\t\t\t\t\"by port %d\\n\",\n\t\t\t((info.info.global_conf.sym_hash_enable_mask[idx] &\n\t\t\t(1UL << offset)) ? \"enabled\" : \"disabled\"), str,\n\t\t\t\t\t\t\tres->port_id);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_get_hash_global_config_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_get_hash_global_config_result,\n\t\tget_hash_global_config, \"get_hash_global_config\");\ncmdline_parse_token_num_t cmd_get_hash_global_config_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_get_hash_global_config_result,\n\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_get_hash_global_config = {\n\t.f = cmd_get_hash_global_config_parsed,\n\t.data = NULL,\n\t.help_str = \"get_hash_global_config port_id\",\n\t.tokens = {\n\t\t(void *)&cmd_get_hash_global_config_all,\n\t\t(void *)&cmd_get_hash_global_config_port_id,\n\t\tNULL,\n\t},\n};\n\n/* Set global config of hash function */\nstruct cmd_set_hash_global_config_result {\n\tcmdline_fixed_string_t set_hash_global_config;\n\tuint8_t port_id;\n\tcmdline_fixed_string_t hash_func;\n\tcmdline_fixed_string_t flow_type;\n\tcmdline_fixed_string_t enable;\n};\n\nstatic void\ncmd_set_hash_global_config_parsed(void *parsed_result,\n\t\t\t\t __rte_unused struct cmdline *cl,\n\t\t\t\t __rte_unused void *data)\n{\n\tstruct cmd_set_hash_global_config_result *res = parsed_result;\n\tstruct rte_eth_hash_filter_info info;\n\tuint32_t ftype, idx, offset;\n\tint ret;\n\n\tif (rte_eth_dev_filter_supported(res->port_id,\n\t\t\t\tRTE_ETH_FILTER_HASH) < 0) {\n\t\tprintf(\"RTE_ETH_FILTER_HASH not supported on port %d\\n\",\n\t\t\t\t\t\t\tres->port_id);\n\t\treturn;\n\t}\n\tmemset(&info, 0, sizeof(info));\n\tinfo.info_type = RTE_ETH_HASH_FILTER_GLOBAL_CONFIG;\n\tif (!strcmp(res->hash_func, \"toeplitz\"))\n\t\tinfo.info.global_conf.hash_func =\n\t\t\tRTE_ETH_HASH_FUNCTION_TOEPLITZ;\n\telse if (!strcmp(res->hash_func, \"simple_xor\"))\n\t\tinfo.info.global_conf.hash_func =\n\t\t\tRTE_ETH_HASH_FUNCTION_SIMPLE_XOR;\n\telse if (!strcmp(res->hash_func, \"default\"))\n\t\tinfo.info.global_conf.hash_func =\n\t\t\tRTE_ETH_HASH_FUNCTION_DEFAULT;\n\n\tftype = str2flowtype(res->flow_type);\n\tidx = ftype / (CHAR_BIT * sizeof(uint32_t));\n\toffset = ftype % (CHAR_BIT * sizeof(uint32_t));\n\tinfo.info.global_conf.valid_bit_mask[idx] |= (1UL << offset);\n\tif (!strcmp(res->enable, \"enable\"))\n\t\tinfo.info.global_conf.sym_hash_enable_mask[idx] |=\n\t\t\t\t\t\t(1UL << offset);\n\tret = rte_eth_dev_filter_ctrl(res->port_id, RTE_ETH_FILTER_HASH,\n\t\t\t\t\tRTE_ETH_FILTER_SET, &info);\n\tif (ret < 0)\n\t\tprintf(\"Cannot set global hash configurations by port %d\\n\",\n\t\t\t\t\t\t\tres->port_id);\n\telse\n\t\tprintf(\"Global hash configurations have been set \"\n\t\t\t\"succcessfully by port %d\\n\", res->port_id);\n}\n\ncmdline_parse_token_string_t cmd_set_hash_global_config_all =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_hash_global_config_result,\n\t\tset_hash_global_config, \"set_hash_global_config\");\ncmdline_parse_token_num_t cmd_set_hash_global_config_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_hash_global_config_result,\n\t\tport_id, UINT8);\ncmdline_parse_token_string_t cmd_set_hash_global_config_hash_func =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_hash_global_config_result,\n\t\thash_func, \"toeplitz#simple_xor#default\");\ncmdline_parse_token_string_t cmd_set_hash_global_config_flow_type =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_hash_global_config_result,\n\t\tflow_type,\n\t\t\"ipv4#ipv4-frag#ipv4-tcp#ipv4-udp#ipv4-sctp#ipv4-other#ipv6#\"\n\t\t\"ipv6-frag#ipv6-tcp#ipv6-udp#ipv6-sctp#ipv6-other#l2_payload\");\ncmdline_parse_token_string_t cmd_set_hash_global_config_enable =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_hash_global_config_result,\n\t\tenable, \"enable#disable\");\n\ncmdline_parse_inst_t cmd_set_hash_global_config = {\n\t.f = cmd_set_hash_global_config_parsed,\n\t.data = NULL,\n\t.help_str = \"set_hash_global_config port_id \"\n\t\t\"toeplitz|simple_xor|default \"\n\t\t\"ipv4|ipv4-frag|ipv4-tcp|ipv4-udp|ipv4-sctp|ipv4-other|ipv6|\"\n\t\t\"ipv6-frag|ipv6-tcp|ipv6-udp|ipv6-sctp|ipv6-other|l2_payload \"\n\t\t\"enable|disable\",\n\t.tokens = {\n\t\t(void *)&cmd_set_hash_global_config_all,\n\t\t(void *)&cmd_set_hash_global_config_port_id,\n\t\t(void *)&cmd_set_hash_global_config_hash_func,\n\t\t(void *)&cmd_set_hash_global_config_flow_type,\n\t\t(void *)&cmd_set_hash_global_config_enable,\n\t\tNULL,\n\t},\n};\n\n/* *** ADD/REMOVE A MULTICAST MAC ADDRESS TO/FROM A PORT *** */\nstruct cmd_mcast_addr_result {\n\tcmdline_fixed_string_t mcast_addr_cmd;\n\tcmdline_fixed_string_t what;\n\tuint8_t port_num;\n\tstruct ether_addr mc_addr;\n};\n\nstatic void cmd_mcast_addr_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_mcast_addr_result *res = parsed_result;\n\n\tif (!is_multicast_ether_addr(&res->mc_addr)) {\n\t\tprintf(\"Invalid multicast addr %02X:%02X:%02X:%02X:%02X:%02X\\n\",\n\t\t res->mc_addr.addr_bytes[0], res->mc_addr.addr_bytes[1],\n\t\t res->mc_addr.addr_bytes[2], res->mc_addr.addr_bytes[3],\n\t\t res->mc_addr.addr_bytes[4], res->mc_addr.addr_bytes[5]);\n\t\treturn;\n\t}\n\tif (strcmp(res->what, \"add\") == 0)\n\t\tmcast_addr_add(res->port_num, &res->mc_addr);\n\telse\n\t\tmcast_addr_remove(res->port_num, &res->mc_addr);\n}\n\ncmdline_parse_token_string_t cmd_mcast_addr_cmd =\n\tTOKEN_STRING_INITIALIZER(struct cmd_mcast_addr_result,\n\t\t\t\t mcast_addr_cmd, \"mcast_addr\");\ncmdline_parse_token_string_t cmd_mcast_addr_what =\n\tTOKEN_STRING_INITIALIZER(struct cmd_mcast_addr_result, what,\n\t\t\t\t \"add#remove\");\ncmdline_parse_token_num_t cmd_mcast_addr_portnum =\n\tTOKEN_NUM_INITIALIZER(struct cmd_mcast_addr_result, port_num, UINT8);\ncmdline_parse_token_etheraddr_t cmd_mcast_addr_addr =\n\tTOKEN_ETHERADDR_INITIALIZER(struct cmd_mac_addr_result, address);\n\ncmdline_parse_inst_t cmd_mcast_addr = {\n\t.f = cmd_mcast_addr_parsed,\n\t.data = (void *)0,\n\t.help_str = \"mcast_addr add|remove X : add/remove multicast MAC address on port X\",\n\t.tokens = {\n\t\t(void *)&cmd_mcast_addr_cmd,\n\t\t(void *)&cmd_mcast_addr_what,\n\t\t(void *)&cmd_mcast_addr_portnum,\n\t\t(void *)&cmd_mcast_addr_addr,\n\t\tNULL,\n\t},\n};\n\n/* ******************************************************************************** */\n\n/* list of instructions */\ncmdline_parse_ctx_t main_ctx[] = {\n\t(cmdline_parse_inst_t *)&cmd_help_brief,\n\t(cmdline_parse_inst_t *)&cmd_help_long,\n\t(cmdline_parse_inst_t *)&cmd_quit,\n\t(cmdline_parse_inst_t *)&cmd_showport,\n\t(cmdline_parse_inst_t *)&cmd_showportall,\n\t(cmdline_parse_inst_t *)&cmd_showcfg,\n\t(cmdline_parse_inst_t *)&cmd_start,\n\t(cmdline_parse_inst_t *)&cmd_start_tx_first,\n\t(cmdline_parse_inst_t *)&cmd_set_link_up,\n\t(cmdline_parse_inst_t *)&cmd_set_link_down,\n\t(cmdline_parse_inst_t *)&cmd_reset,\n\t(cmdline_parse_inst_t *)&cmd_set_numbers,\n\t(cmdline_parse_inst_t *)&cmd_set_txpkts,\n\t(cmdline_parse_inst_t *)&cmd_set_fwd_list,\n\t(cmdline_parse_inst_t *)&cmd_set_fwd_mask,\n\t(cmdline_parse_inst_t *)&cmd_set_fwd_mode,\n\t(cmdline_parse_inst_t *)&cmd_set_burst_tx_retry,\n\t(cmdline_parse_inst_t *)&cmd_set_promisc_mode_one,\n\t(cmdline_parse_inst_t *)&cmd_set_promisc_mode_all,\n\t(cmdline_parse_inst_t *)&cmd_set_allmulti_mode_one,\n\t(cmdline_parse_inst_t *)&cmd_set_allmulti_mode_all,\n\t(cmdline_parse_inst_t *)&cmd_set_flush_rx,\n\t(cmdline_parse_inst_t *)&cmd_set_link_check,\n#ifdef RTE_NIC_BYPASS\n\t(cmdline_parse_inst_t *)&cmd_set_bypass_mode,\n\t(cmdline_parse_inst_t *)&cmd_set_bypass_event,\n\t(cmdline_parse_inst_t *)&cmd_set_bypass_timeout,\n\t(cmdline_parse_inst_t *)&cmd_show_bypass_config,\n#endif\n#ifdef RTE_LIBRTE_PMD_BOND\n\t(cmdline_parse_inst_t *) &cmd_set_bonding_mode,\n\t(cmdline_parse_inst_t *) &cmd_show_bonding_config,\n\t(cmdline_parse_inst_t *) &cmd_set_bonding_primary,\n\t(cmdline_parse_inst_t *) &cmd_add_bonding_slave,\n\t(cmdline_parse_inst_t *) &cmd_remove_bonding_slave,\n\t(cmdline_parse_inst_t *) &cmd_create_bonded_device,\n\t(cmdline_parse_inst_t *) &cmd_set_bond_mac_addr,\n\t(cmdline_parse_inst_t *) &cmd_set_balance_xmit_policy,\n\t(cmdline_parse_inst_t *) &cmd_set_bond_mon_period,\n#endif\n\t(cmdline_parse_inst_t *)&cmd_vlan_offload,\n\t(cmdline_parse_inst_t *)&cmd_vlan_tpid,\n\t(cmdline_parse_inst_t *)&cmd_rx_vlan_filter_all,\n\t(cmdline_parse_inst_t *)&cmd_rx_vlan_filter,\n\t(cmdline_parse_inst_t *)&cmd_tx_vlan_set,\n\t(cmdline_parse_inst_t *)&cmd_tx_vlan_set_qinq,\n\t(cmdline_parse_inst_t *)&cmd_tx_vlan_reset,\n\t(cmdline_parse_inst_t *)&cmd_tx_vlan_set_pvid,\n\t(cmdline_parse_inst_t *)&cmd_csum_set,\n\t(cmdline_parse_inst_t *)&cmd_csum_show,\n\t(cmdline_parse_inst_t *)&cmd_csum_tunnel,\n\t(cmdline_parse_inst_t *)&cmd_tso_set,\n\t(cmdline_parse_inst_t *)&cmd_tso_show,\n\t(cmdline_parse_inst_t *)&cmd_link_flow_control_set,\n\t(cmdline_parse_inst_t *)&cmd_link_flow_control_set_rx,\n\t(cmdline_parse_inst_t *)&cmd_link_flow_control_set_tx,\n\t(cmdline_parse_inst_t *)&cmd_link_flow_control_set_hw,\n\t(cmdline_parse_inst_t *)&cmd_link_flow_control_set_lw,\n\t(cmdline_parse_inst_t *)&cmd_link_flow_control_set_pt,\n\t(cmdline_parse_inst_t *)&cmd_link_flow_control_set_xon,\n\t(cmdline_parse_inst_t *)&cmd_link_flow_control_set_macfwd,\n\t(cmdline_parse_inst_t *)&cmd_link_flow_control_set_autoneg,\n\t(cmdline_parse_inst_t *)&cmd_priority_flow_control_set,\n\t(cmdline_parse_inst_t *)&cmd_config_dcb,\n\t(cmdline_parse_inst_t *)&cmd_read_reg,\n\t(cmdline_parse_inst_t *)&cmd_read_reg_bit_field,\n\t(cmdline_parse_inst_t *)&cmd_read_reg_bit,\n\t(cmdline_parse_inst_t *)&cmd_write_reg,\n\t(cmdline_parse_inst_t *)&cmd_write_reg_bit_field,\n\t(cmdline_parse_inst_t *)&cmd_write_reg_bit,\n\t(cmdline_parse_inst_t *)&cmd_read_rxd_txd,\n\t(cmdline_parse_inst_t *)&cmd_stop,\n\t(cmdline_parse_inst_t *)&cmd_mac_addr,\n\t(cmdline_parse_inst_t *)&cmd_set_qmap,\n\t(cmdline_parse_inst_t *)&cmd_operate_port,\n\t(cmdline_parse_inst_t *)&cmd_operate_specific_port,\n\t(cmdline_parse_inst_t *)&cmd_operate_attach_port,\n\t(cmdline_parse_inst_t *)&cmd_operate_detach_port,\n\t(cmdline_parse_inst_t *)&cmd_config_speed_all,\n\t(cmdline_parse_inst_t *)&cmd_config_speed_specific,\n\t(cmdline_parse_inst_t *)&cmd_config_rx_tx,\n\t(cmdline_parse_inst_t *)&cmd_config_mtu,\n\t(cmdline_parse_inst_t *)&cmd_config_max_pkt_len,\n\t(cmdline_parse_inst_t *)&cmd_config_rx_mode_flag,\n\t(cmdline_parse_inst_t *)&cmd_config_rss,\n\t(cmdline_parse_inst_t *)&cmd_config_rxtx_queue,\n\t(cmdline_parse_inst_t *)&cmd_config_rss_reta,\n\t(cmdline_parse_inst_t *)&cmd_showport_reta,\n\t(cmdline_parse_inst_t *)&cmd_config_burst,\n\t(cmdline_parse_inst_t *)&cmd_config_thresh,\n\t(cmdline_parse_inst_t *)&cmd_config_threshold,\n\t(cmdline_parse_inst_t *)&cmd_set_vf_rxmode,\n\t(cmdline_parse_inst_t *)&cmd_set_uc_hash_filter,\n\t(cmdline_parse_inst_t *)&cmd_set_uc_all_hash_filter,\n\t(cmdline_parse_inst_t *)&cmd_vf_mac_addr_filter,\n\t(cmdline_parse_inst_t *)&cmd_set_vf_macvlan_filter,\n\t(cmdline_parse_inst_t *)&cmd_set_vf_traffic,\n\t(cmdline_parse_inst_t *)&cmd_vf_rxvlan_filter,\n\t(cmdline_parse_inst_t *)&cmd_queue_rate_limit,\n\t(cmdline_parse_inst_t *)&cmd_vf_rate_limit,\n\t(cmdline_parse_inst_t *)&cmd_tunnel_filter,\n\t(cmdline_parse_inst_t *)&cmd_tunnel_udp_config,\n\t(cmdline_parse_inst_t *)&cmd_set_mirror_mask,\n\t(cmdline_parse_inst_t *)&cmd_set_mirror_link,\n\t(cmdline_parse_inst_t *)&cmd_reset_mirror_rule,\n\t(cmdline_parse_inst_t *)&cmd_showport_rss_hash,\n\t(cmdline_parse_inst_t *)&cmd_showport_rss_hash_key,\n\t(cmdline_parse_inst_t *)&cmd_config_rss_hash_key,\n\t(cmdline_parse_inst_t *)&cmd_dump,\n\t(cmdline_parse_inst_t *)&cmd_dump_one,\n\t(cmdline_parse_inst_t *)&cmd_ethertype_filter,\n\t(cmdline_parse_inst_t *)&cmd_syn_filter,\n\t(cmdline_parse_inst_t *)&cmd_2tuple_filter,\n\t(cmdline_parse_inst_t *)&cmd_5tuple_filter,\n\t(cmdline_parse_inst_t *)&cmd_flex_filter,\n\t(cmdline_parse_inst_t *)&cmd_add_del_ip_flow_director,\n\t(cmdline_parse_inst_t *)&cmd_add_del_udp_flow_director,\n\t(cmdline_parse_inst_t *)&cmd_add_del_sctp_flow_director,\n\t(cmdline_parse_inst_t *)&cmd_add_del_l2_flow_director,\n\t(cmdline_parse_inst_t *)&cmd_flush_flow_director,\n\t(cmdline_parse_inst_t *)&cmd_set_flow_director_mask,\n\t(cmdline_parse_inst_t *)&cmd_set_flow_director_flex_mask,\n\t(cmdline_parse_inst_t *)&cmd_set_flow_director_flex_payload,\n\t(cmdline_parse_inst_t *)&cmd_get_sym_hash_ena_per_port,\n\t(cmdline_parse_inst_t *)&cmd_set_sym_hash_ena_per_port,\n\t(cmdline_parse_inst_t *)&cmd_get_hash_global_config,\n\t(cmdline_parse_inst_t *)&cmd_set_hash_global_config,\n\t(cmdline_parse_inst_t *)&cmd_mcast_addr,\n\tNULL,\n};\n\n/* prompt function, called from main on MASTER lcore */\nvoid\nprompt(void)\n{\n\tstruct cmdline *cl;\n\n\t/* initialize non-constant commands */\n\tcmd_set_fwd_mode_init();\n\n\tcl = cmdline_stdin_new(main_ctx, \"testpmd> \");\n\tif (cl == NULL) {\n\t\treturn;\n\t}\n\tcmdline_interact(cl);\n\tcmdline_stdin_exit(cl);\n}\n\nstatic void\ncmd_reconfig_device_queue(portid_t id, uint8_t dev, uint8_t queue)\n{\n\tif (id == (portid_t)RTE_PORT_ALL) {\n\t\tportid_t pid;\n\n\t\tFOREACH_PORT(pid, ports) {\n\t\t\t/* check if need_reconfig has been set to 1 */\n\t\t\tif (ports[pid].need_reconfig == 0)\n\t\t\t\tports[pid].need_reconfig = dev;\n\t\t\t/* check if need_reconfig_queues has been set to 1 */\n\t\t\tif (ports[pid].need_reconfig_queues == 0)\n\t\t\t\tports[pid].need_reconfig_queues = queue;\n\t\t}\n\t} else if (!port_id_is_invalid(id, DISABLED_WARN)) {\n\t\t/* check if need_reconfig has been set to 1 */\n\t\tif (ports[id].need_reconfig == 0)\n\t\t\tports[id].need_reconfig = dev;\n\t\t/* check if need_reconfig_queues has been set to 1 */\n\t\tif (ports[id].need_reconfig_queues == 0)\n\t\t\tports[id].need_reconfig_queues = queue;\n\t}\n}\n\n#ifdef RTE_NIC_BYPASS\n#include \nuint8_t\nbypass_is_supported(portid_t port_id)\n{\n\tstruct rte_port *port;\n\tstruct rte_pci_id *pci_id;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn 0;\n\n\t/* Get the device id. */\n\tport = &ports[port_id];\n\tpci_id = &port->dev_info.pci_dev->id;\n\n\t/* Check if NIC supports bypass. */\n\tif (pci_id->device_id == IXGBE_DEV_ID_82599_BYPASS) {\n\t\treturn 1;\n\t}\n\telse {\n\t\tprintf(\"\\tBypass not supported for port_id = %d.\\n\", port_id);\n\t\treturn 0;\n\t}\n}\n#endif\n" }, { "path": "app/test-pmd/config.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n/* BSD LICENSE\n *\n * Copyright 2013-2014 6WIND S.A.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"testpmd.h\"\n\nstatic char *flowtype_to_str(uint16_t flow_type);\n\nstatic void\nprint_ethaddr(const char *name, struct ether_addr *eth_addr)\n{\n\tchar buf[ETHER_ADDR_FMT_SIZE];\n\tether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);\n\tprintf(\"%s%s\", name, buf);\n}\n\nvoid\nnic_stats_display(portid_t port_id)\n{\n\tstruct rte_eth_stats stats;\n\tstruct rte_port *port = &ports[port_id];\n\tuint8_t i;\n\tportid_t pid;\n\n\tstatic const char *nic_stats_border = \"########################\";\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN)) {\n\t\tprintf(\"Valid port range is [0\");\n\t\tFOREACH_PORT(pid, ports)\n\t\t\tprintf(\", %d\", pid);\n\t\tprintf(\"]\\n\");\n\t\treturn;\n\t}\n\trte_eth_stats_get(port_id, &stats);\n\tprintf(\"\\n %s NIC statistics for port %-2d %s\\n\",\n\t nic_stats_border, port_id, nic_stats_border);\n\n\tif ((!port->rx_queue_stats_mapping_enabled) && (!port->tx_queue_stats_mapping_enabled)) {\n\t\tprintf(\" RX-packets: %-10\"PRIu64\" RX-missed: %-10\"PRIu64\" RX-bytes: \"\n\t\t \"%-\"PRIu64\"\\n\",\n\t\t stats.ipackets, stats.imissed, stats.ibytes);\n\t\tprintf(\" RX-badcrc: %-10\"PRIu64\" RX-badlen: %-10\"PRIu64\" RX-errors: \"\n\t\t \"%-\"PRIu64\"\\n\",\n\t\t stats.ibadcrc, stats.ibadlen, stats.ierrors);\n\t\tprintf(\" RX-nombuf: %-10\"PRIu64\"\\n\",\n\t\t stats.rx_nombuf);\n\t\tprintf(\" TX-packets: %-10\"PRIu64\" TX-errors: %-10\"PRIu64\" TX-bytes: \"\n\t\t \"%-\"PRIu64\"\\n\",\n\t\t stats.opackets, stats.oerrors, stats.obytes);\n\t}\n\telse {\n\t\tprintf(\" RX-packets: %10\"PRIu64\" RX-errors: %10\"PRIu64\n\t\t \" RX-bytes: %10\"PRIu64\"\\n\",\n\t\t stats.ipackets, stats.ierrors, stats.ibytes);\n\t\tprintf(\" RX-badcrc: %10\"PRIu64\" RX-badlen: %10\"PRIu64\n\t\t \" RX-errors: %10\"PRIu64\"\\n\",\n\t\t stats.ibadcrc, stats.ibadlen, stats.ierrors);\n\t\tprintf(\" RX-nombuf: %10\"PRIu64\"\\n\",\n\t\t stats.rx_nombuf);\n\t\tprintf(\" TX-packets: %10\"PRIu64\" TX-errors: %10\"PRIu64\n\t\t \" TX-bytes: %10\"PRIu64\"\\n\",\n\t\t stats.opackets, stats.oerrors, stats.obytes);\n\t}\n\n\t/* stats fdir */\n\tif (fdir_conf.mode != RTE_FDIR_MODE_NONE)\n\t\tprintf(\" Fdirmiss: %-10\"PRIu64\" Fdirmatch: %-10\"PRIu64\"\\n\",\n\t\t stats.fdirmiss,\n\t\t stats.fdirmatch);\n\n\tif (port->rx_queue_stats_mapping_enabled) {\n\t\tprintf(\"\\n\");\n\t\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) {\n\t\t\tprintf(\" Stats reg %2d RX-packets: %10\"PRIu64\n\t\t\t \" RX-errors: %10\"PRIu64\n\t\t\t \" RX-bytes: %10\"PRIu64\"\\n\",\n\t\t\t i, stats.q_ipackets[i], stats.q_errors[i], stats.q_ibytes[i]);\n\t\t}\n\t}\n\tif (port->tx_queue_stats_mapping_enabled) {\n\t\tprintf(\"\\n\");\n\t\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) {\n\t\t\tprintf(\" Stats reg %2d TX-packets: %10\"PRIu64\n\t\t\t \" TX-bytes: %10\"PRIu64\"\\n\",\n\t\t\t i, stats.q_opackets[i], stats.q_obytes[i]);\n\t\t}\n\t}\n\n\t/* Display statistics of XON/XOFF pause frames, if any. */\n\tif ((stats.tx_pause_xon | stats.rx_pause_xon |\n\t stats.tx_pause_xoff | stats.rx_pause_xoff) > 0) {\n\t\tprintf(\" RX-XOFF: %-10\"PRIu64\" RX-XON: %-10\"PRIu64\"\\n\",\n\t\t stats.rx_pause_xoff, stats.rx_pause_xon);\n\t\tprintf(\" TX-XOFF: %-10\"PRIu64\" TX-XON: %-10\"PRIu64\"\\n\",\n\t\t stats.tx_pause_xoff, stats.tx_pause_xon);\n\t}\n\tprintf(\" %s############################%s\\n\",\n\t nic_stats_border, nic_stats_border);\n}\n\nvoid\nnic_stats_clear(portid_t port_id)\n{\n\tportid_t pid;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN)) {\n\t\tprintf(\"Valid port range is [0\");\n\t\tFOREACH_PORT(pid, ports)\n\t\t\tprintf(\", %d\", pid);\n\t\tprintf(\"]\\n\");\n\t\treturn;\n\t}\n\trte_eth_stats_reset(port_id);\n\tprintf(\"\\n NIC statistics for port %d cleared\\n\", port_id);\n}\n\nvoid\nnic_xstats_display(portid_t port_id)\n{\n\tstruct rte_eth_xstats *xstats;\n\tint len, ret, i;\n\n\tprintf(\"###### NIC extended statistics for port %-2d\\n\", port_id);\n\n\tlen = rte_eth_xstats_get(port_id, NULL, 0);\n\tif (len < 0) {\n\t\tprintf(\"Cannot get xstats count\\n\");\n\t\treturn;\n\t}\n\txstats = malloc(sizeof(xstats[0]) * len);\n\tif (xstats == NULL) {\n\t\tprintf(\"Cannot allocate memory for xstats\\n\");\n\t\treturn;\n\t}\n\tret = rte_eth_xstats_get(port_id, xstats, len);\n\tif (ret < 0 || ret > len) {\n\t\tprintf(\"Cannot get xstats\\n\");\n\t\tfree(xstats);\n\t\treturn;\n\t}\n\tfor (i = 0; i < len; i++)\n\t\tprintf(\"%s: %\"PRIu64\"\\n\", xstats[i].name, xstats[i].value);\n\tfree(xstats);\n}\n\nvoid\nnic_xstats_clear(portid_t port_id)\n{\n\trte_eth_xstats_reset(port_id);\n}\n\nvoid\nnic_stats_mapping_display(portid_t port_id)\n{\n\tstruct rte_port *port = &ports[port_id];\n\tuint16_t i;\n\tportid_t pid;\n\n\tstatic const char *nic_stats_mapping_border = \"########################\";\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN)) {\n\t\tprintf(\"Valid port range is [0\");\n\t\tFOREACH_PORT(pid, ports)\n\t\t\tprintf(\", %d\", pid);\n\t\tprintf(\"]\\n\");\n\t\treturn;\n\t}\n\n\tif ((!port->rx_queue_stats_mapping_enabled) && (!port->tx_queue_stats_mapping_enabled)) {\n\t\tprintf(\"Port id %d - either does not support queue statistic mapping or\"\n\t\t \" no queue statistic mapping set\\n\", port_id);\n\t\treturn;\n\t}\n\n\tprintf(\"\\n %s NIC statistics mapping for port %-2d %s\\n\",\n\t nic_stats_mapping_border, port_id, nic_stats_mapping_border);\n\n\tif (port->rx_queue_stats_mapping_enabled) {\n\t\tfor (i = 0; i < nb_rx_queue_stats_mappings; i++) {\n\t\t\tif (rx_queue_stats_mappings[i].port_id == port_id) {\n\t\t\t\tprintf(\" RX-queue %2d mapped to Stats Reg %2d\\n\",\n\t\t\t\t rx_queue_stats_mappings[i].queue_id,\n\t\t\t\t rx_queue_stats_mappings[i].stats_counter_id);\n\t\t\t}\n\t\t}\n\t\tprintf(\"\\n\");\n\t}\n\n\n\tif (port->tx_queue_stats_mapping_enabled) {\n\t\tfor (i = 0; i < nb_tx_queue_stats_mappings; i++) {\n\t\t\tif (tx_queue_stats_mappings[i].port_id == port_id) {\n\t\t\t\tprintf(\" TX-queue %2d mapped to Stats Reg %2d\\n\",\n\t\t\t\t tx_queue_stats_mappings[i].queue_id,\n\t\t\t\t tx_queue_stats_mappings[i].stats_counter_id);\n\t\t\t}\n\t\t}\n\t}\n\n\tprintf(\" %s####################################%s\\n\",\n\t nic_stats_mapping_border, nic_stats_mapping_border);\n}\n\nvoid\nport_infos_display(portid_t port_id)\n{\n\tstruct rte_port *port;\n\tstruct ether_addr mac_addr;\n\tstruct rte_eth_link link;\n\tstruct rte_eth_dev_info dev_info;\n\tint vlan_offload;\n\tstruct rte_mempool * mp;\n\tstatic const char *info_border = \"*********************\";\n\tportid_t pid;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN)) {\n\t\tprintf(\"Valid port range is [0\");\n\t\tFOREACH_PORT(pid, ports)\n\t\t\tprintf(\", %d\", pid);\n\t\tprintf(\"]\\n\");\n\t\treturn;\n\t}\n\tport = &ports[port_id];\n\trte_eth_link_get_nowait(port_id, &link);\n\tprintf(\"\\n%s Infos for port %-2d %s\\n\",\n\t info_border, port_id, info_border);\n\trte_eth_macaddr_get(port_id, &mac_addr);\n\tprint_ethaddr(\"MAC address: \", &mac_addr);\n\tprintf(\"\\nConnect to socket: %u\", port->socket_id);\n\n\tif (port_numa[port_id] != NUMA_NO_CONFIG) {\n\t\tmp = mbuf_pool_find(port_numa[port_id]);\n\t\tif (mp)\n\t\t\tprintf(\"\\nmemory allocation on the socket: %d\",\n\t\t\t\t\t\t\tport_numa[port_id]);\n\t} else\n\t\tprintf(\"\\nmemory allocation on the socket: %u\",port->socket_id);\n\n\tprintf(\"\\nLink status: %s\\n\", (link.link_status) ? (\"up\") : (\"down\"));\n\tprintf(\"Link speed: %u Mbps\\n\", (unsigned) link.link_speed);\n\tprintf(\"Link duplex: %s\\n\", (link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t (\"full-duplex\") : (\"half-duplex\"));\n\tprintf(\"Promiscuous mode: %s\\n\",\n\t rte_eth_promiscuous_get(port_id) ? \"enabled\" : \"disabled\");\n\tprintf(\"Allmulticast mode: %s\\n\",\n\t rte_eth_allmulticast_get(port_id) ? \"enabled\" : \"disabled\");\n\tprintf(\"Maximum number of MAC addresses: %u\\n\",\n\t (unsigned int)(port->dev_info.max_mac_addrs));\n\tprintf(\"Maximum number of MAC addresses of hash filtering: %u\\n\",\n\t (unsigned int)(port->dev_info.max_hash_mac_addrs));\n\n\tvlan_offload = rte_eth_dev_get_vlan_offload(port_id);\n\tif (vlan_offload >= 0){\n\t\tprintf(\"VLAN offload: \\n\");\n\t\tif (vlan_offload & ETH_VLAN_STRIP_OFFLOAD)\n\t\t\tprintf(\" strip on \\n\");\n\t\telse\n\t\t\tprintf(\" strip off \\n\");\n\n\t\tif (vlan_offload & ETH_VLAN_FILTER_OFFLOAD)\n\t\t\tprintf(\" filter on \\n\");\n\t\telse\n\t\t\tprintf(\" filter off \\n\");\n\n\t\tif (vlan_offload & ETH_VLAN_EXTEND_OFFLOAD)\n\t\t\tprintf(\" qinq(extend) on \\n\");\n\t\telse\n\t\t\tprintf(\" qinq(extend) off \\n\");\n\t}\n\n\tmemset(&dev_info, 0, sizeof(dev_info));\n\trte_eth_dev_info_get(port_id, &dev_info);\n\tif (dev_info.hash_key_size > 0)\n\t\tprintf(\"Hash key size in bytes: %u\\n\", dev_info.hash_key_size);\n\tif (dev_info.reta_size > 0)\n\t\tprintf(\"Redirection table size: %u\\n\", dev_info.reta_size);\n\tif (!dev_info.flow_type_rss_offloads)\n\t\tprintf(\"No flow type is supported.\\n\");\n\telse {\n\t\tuint16_t i;\n\t\tchar *p;\n\n\t\tprintf(\"Supported flow types:\\n\");\n\t\tfor (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX;\n\t\t\t\t\t\t\t\ti++) {\n\t\t\tif (!(dev_info.flow_type_rss_offloads & (1ULL << i)))\n\t\t\t\tcontinue;\n\t\t\tp = flowtype_to_str(i);\n\t\t\tprintf(\" %s\\n\", (p ? p : \"unknown\"));\n\t\t}\n\t}\n}\n\nint\nport_id_is_invalid(portid_t port_id, enum print_warning warning)\n{\n\tif (port_id == (portid_t)RTE_PORT_ALL)\n\t\treturn 0;\n\n\tif (port_id < RTE_MAX_ETHPORTS && ports[port_id].enabled)\n\t\treturn 0;\n\n\tif (warning == ENABLED_WARN)\n\t\tprintf(\"Invalid port %d\\n\", port_id);\n\n\treturn 1;\n}\n\nstatic int\nvlan_id_is_invalid(uint16_t vlan_id)\n{\n\tif (vlan_id < 4096)\n\t\treturn 0;\n\tprintf(\"Invalid vlan_id %d (must be < 4096)\\n\", vlan_id);\n\treturn 1;\n}\n\nstatic int\nport_reg_off_is_invalid(portid_t port_id, uint32_t reg_off)\n{\n\tuint64_t pci_len;\n\n\tif (reg_off & 0x3) {\n\t\tprintf(\"Port register offset 0x%X not aligned on a 4-byte \"\n\t\t \"boundary\\n\",\n\t\t (unsigned)reg_off);\n\t\treturn 1;\n\t}\n\tpci_len = ports[port_id].dev_info.pci_dev->mem_resource[0].len;\n\tif (reg_off >= pci_len) {\n\t\tprintf(\"Port %d: register offset %u (0x%X) out of port PCI \"\n\t\t \"resource (length=%\"PRIu64\")\\n\",\n\t\t port_id, (unsigned)reg_off, (unsigned)reg_off, pci_len);\n\t\treturn 1;\n\t}\n\treturn 0;\n}\n\nstatic int\nreg_bit_pos_is_invalid(uint8_t bit_pos)\n{\n\tif (bit_pos <= 31)\n\t\treturn 0;\n\tprintf(\"Invalid bit position %d (must be <= 31)\\n\", bit_pos);\n\treturn 1;\n}\n\n#define display_port_and_reg_off(port_id, reg_off) \\\n\tprintf(\"port %d PCI register at offset 0x%X: \", (port_id), (reg_off))\n\nstatic inline void\ndisplay_port_reg_value(portid_t port_id, uint32_t reg_off, uint32_t reg_v)\n{\n\tdisplay_port_and_reg_off(port_id, (unsigned)reg_off);\n\tprintf(\"0x%08X (%u)\\n\", (unsigned)reg_v, (unsigned)reg_v);\n}\n\nvoid\nport_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_x)\n{\n\tuint32_t reg_v;\n\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tif (port_reg_off_is_invalid(port_id, reg_off))\n\t\treturn;\n\tif (reg_bit_pos_is_invalid(bit_x))\n\t\treturn;\n\treg_v = port_id_pci_reg_read(port_id, reg_off);\n\tdisplay_port_and_reg_off(port_id, (unsigned)reg_off);\n\tprintf(\"bit %d=%d\\n\", bit_x, (int) ((reg_v & (1 << bit_x)) >> bit_x));\n}\n\nvoid\nport_reg_bit_field_display(portid_t port_id, uint32_t reg_off,\n\t\t\t uint8_t bit1_pos, uint8_t bit2_pos)\n{\n\tuint32_t reg_v;\n\tuint8_t l_bit;\n\tuint8_t h_bit;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tif (port_reg_off_is_invalid(port_id, reg_off))\n\t\treturn;\n\tif (reg_bit_pos_is_invalid(bit1_pos))\n\t\treturn;\n\tif (reg_bit_pos_is_invalid(bit2_pos))\n\t\treturn;\n\tif (bit1_pos > bit2_pos)\n\t\tl_bit = bit2_pos, h_bit = bit1_pos;\n\telse\n\t\tl_bit = bit1_pos, h_bit = bit2_pos;\n\n\treg_v = port_id_pci_reg_read(port_id, reg_off);\n\treg_v >>= l_bit;\n\tif (h_bit < 31)\n\t\treg_v &= ((1 << (h_bit - l_bit + 1)) - 1);\n\tdisplay_port_and_reg_off(port_id, (unsigned)reg_off);\n\tprintf(\"bits[%d, %d]=0x%0*X (%u)\\n\", l_bit, h_bit,\n\t ((h_bit - l_bit) / 4) + 1, (unsigned)reg_v, (unsigned)reg_v);\n}\n\nvoid\nport_reg_display(portid_t port_id, uint32_t reg_off)\n{\n\tuint32_t reg_v;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tif (port_reg_off_is_invalid(port_id, reg_off))\n\t\treturn;\n\treg_v = port_id_pci_reg_read(port_id, reg_off);\n\tdisplay_port_reg_value(port_id, reg_off, reg_v);\n}\n\nvoid\nport_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos,\n\t\t uint8_t bit_v)\n{\n\tuint32_t reg_v;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tif (port_reg_off_is_invalid(port_id, reg_off))\n\t\treturn;\n\tif (reg_bit_pos_is_invalid(bit_pos))\n\t\treturn;\n\tif (bit_v > 1) {\n\t\tprintf(\"Invalid bit value %d (must be 0 or 1)\\n\", (int) bit_v);\n\t\treturn;\n\t}\n\treg_v = port_id_pci_reg_read(port_id, reg_off);\n\tif (bit_v == 0)\n\t\treg_v &= ~(1 << bit_pos);\n\telse\n\t\treg_v |= (1 << bit_pos);\n\tport_id_pci_reg_write(port_id, reg_off, reg_v);\n\tdisplay_port_reg_value(port_id, reg_off, reg_v);\n}\n\nvoid\nport_reg_bit_field_set(portid_t port_id, uint32_t reg_off,\n\t\t uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value)\n{\n\tuint32_t max_v;\n\tuint32_t reg_v;\n\tuint8_t l_bit;\n\tuint8_t h_bit;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tif (port_reg_off_is_invalid(port_id, reg_off))\n\t\treturn;\n\tif (reg_bit_pos_is_invalid(bit1_pos))\n\t\treturn;\n\tif (reg_bit_pos_is_invalid(bit2_pos))\n\t\treturn;\n\tif (bit1_pos > bit2_pos)\n\t\tl_bit = bit2_pos, h_bit = bit1_pos;\n\telse\n\t\tl_bit = bit1_pos, h_bit = bit2_pos;\n\n\tif ((h_bit - l_bit) < 31)\n\t\tmax_v = (1 << (h_bit - l_bit + 1)) - 1;\n\telse\n\t\tmax_v = 0xFFFFFFFF;\n\n\tif (value > max_v) {\n\t\tprintf(\"Invalid value %u (0x%x) must be < %u (0x%x)\\n\",\n\t\t\t\t(unsigned)value, (unsigned)value,\n\t\t\t\t(unsigned)max_v, (unsigned)max_v);\n\t\treturn;\n\t}\n\treg_v = port_id_pci_reg_read(port_id, reg_off);\n\treg_v &= ~(max_v << l_bit); /* Keep unchanged bits */\n\treg_v |= (value << l_bit); /* Set changed bits */\n\tport_id_pci_reg_write(port_id, reg_off, reg_v);\n\tdisplay_port_reg_value(port_id, reg_off, reg_v);\n}\n\nvoid\nport_reg_set(portid_t port_id, uint32_t reg_off, uint32_t reg_v)\n{\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tif (port_reg_off_is_invalid(port_id, reg_off))\n\t\treturn;\n\tport_id_pci_reg_write(port_id, reg_off, reg_v);\n\tdisplay_port_reg_value(port_id, reg_off, reg_v);\n}\n\nvoid\nport_mtu_set(portid_t port_id, uint16_t mtu)\n{\n\tint diag;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tdiag = rte_eth_dev_set_mtu(port_id, mtu);\n\tif (diag == 0)\n\t\treturn;\n\tprintf(\"Set MTU failed. diag=%d\\n\", diag);\n}\n\n/*\n * RX/TX ring descriptors display functions.\n */\nint\nrx_queue_id_is_invalid(queueid_t rxq_id)\n{\n\tif (rxq_id < nb_rxq)\n\t\treturn 0;\n\tprintf(\"Invalid RX queue %d (must be < nb_rxq=%d)\\n\", rxq_id, nb_rxq);\n\treturn 1;\n}\n\nint\ntx_queue_id_is_invalid(queueid_t txq_id)\n{\n\tif (txq_id < nb_txq)\n\t\treturn 0;\n\tprintf(\"Invalid TX queue %d (must be < nb_rxq=%d)\\n\", txq_id, nb_txq);\n\treturn 1;\n}\n\nstatic int\nrx_desc_id_is_invalid(uint16_t rxdesc_id)\n{\n\tif (rxdesc_id < nb_rxd)\n\t\treturn 0;\n\tprintf(\"Invalid RX descriptor %d (must be < nb_rxd=%d)\\n\",\n\t rxdesc_id, nb_rxd);\n\treturn 1;\n}\n\nstatic int\ntx_desc_id_is_invalid(uint16_t txdesc_id)\n{\n\tif (txdesc_id < nb_txd)\n\t\treturn 0;\n\tprintf(\"Invalid TX descriptor %d (must be < nb_txd=%d)\\n\",\n\t txdesc_id, nb_txd);\n\treturn 1;\n}\n\nstatic const struct rte_memzone *\nring_dma_zone_lookup(const char *ring_name, uint8_t port_id, uint16_t q_id)\n{\n\tchar mz_name[RTE_MEMZONE_NAMESIZE];\n\tconst struct rte_memzone *mz;\n\n\tsnprintf(mz_name, sizeof(mz_name), \"%s_%s_%d_%d\",\n\t\t ports[port_id].dev_info.driver_name, ring_name, port_id, q_id);\n\tmz = rte_memzone_lookup(mz_name);\n\tif (mz == NULL)\n\t\tprintf(\"%s ring memory zoneof (port %d, queue %d) not\"\n\t\t \"found (zone name = %s\\n\",\n\t\t ring_name, port_id, q_id, mz_name);\n\treturn (mz);\n}\n\nunion igb_ring_dword {\n\tuint64_t dword;\n\tstruct {\n#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n\t\tuint32_t lo;\n\t\tuint32_t hi;\n#else\n\t\tuint32_t hi;\n\t\tuint32_t lo;\n#endif\n\t} words;\n};\n\nstruct igb_ring_desc_32_bytes {\n\tunion igb_ring_dword lo_dword;\n\tunion igb_ring_dword hi_dword;\n\tunion igb_ring_dword resv1;\n\tunion igb_ring_dword resv2;\n};\n\nstruct igb_ring_desc_16_bytes {\n\tunion igb_ring_dword lo_dword;\n\tunion igb_ring_dword hi_dword;\n};\n\nstatic void\nring_rxd_display_dword(union igb_ring_dword dword)\n{\n\tprintf(\" 0x%08X - 0x%08X\\n\", (unsigned)dword.words.lo,\n\t\t\t\t\t(unsigned)dword.words.hi);\n}\n\nstatic void\nring_rx_descriptor_display(const struct rte_memzone *ring_mz,\n#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n\t\t\t uint8_t port_id,\n#else\n\t\t\t __rte_unused uint8_t port_id,\n#endif\n\t\t\t uint16_t desc_id)\n{\n\tstruct igb_ring_desc_16_bytes *ring =\n\t\t(struct igb_ring_desc_16_bytes *)ring_mz->addr;\n#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n\tstruct rte_eth_dev_info dev_info;\n\n\tmemset(&dev_info, 0, sizeof(dev_info));\n\trte_eth_dev_info_get(port_id, &dev_info);\n\tif (strstr(dev_info.driver_name, \"i40e\") != NULL) {\n\t\t/* 32 bytes RX descriptor, i40e only */\n\t\tstruct igb_ring_desc_32_bytes *ring =\n\t\t\t(struct igb_ring_desc_32_bytes *)ring_mz->addr;\n\t\tring[desc_id].lo_dword.dword =\n\t\t\trte_le_to_cpu_64(ring[desc_id].lo_dword.dword);\n\t\tring_rxd_display_dword(ring[desc_id].lo_dword);\n\t\tring[desc_id].hi_dword.dword =\n\t\t\trte_le_to_cpu_64(ring[desc_id].hi_dword.dword);\n\t\tring_rxd_display_dword(ring[desc_id].hi_dword);\n\t\tring[desc_id].resv1.dword =\n\t\t\trte_le_to_cpu_64(ring[desc_id].resv1.dword);\n\t\tring_rxd_display_dword(ring[desc_id].resv1);\n\t\tring[desc_id].resv2.dword =\n\t\t\trte_le_to_cpu_64(ring[desc_id].resv2.dword);\n\t\tring_rxd_display_dword(ring[desc_id].resv2);\n\n\t\treturn;\n\t}\n#endif\n\t/* 16 bytes RX descriptor */\n\tring[desc_id].lo_dword.dword =\n\t\trte_le_to_cpu_64(ring[desc_id].lo_dword.dword);\n\tring_rxd_display_dword(ring[desc_id].lo_dword);\n\tring[desc_id].hi_dword.dword =\n\t\trte_le_to_cpu_64(ring[desc_id].hi_dword.dword);\n\tring_rxd_display_dword(ring[desc_id].hi_dword);\n}\n\nstatic void\nring_tx_descriptor_display(const struct rte_memzone *ring_mz, uint16_t desc_id)\n{\n\tstruct igb_ring_desc_16_bytes *ring;\n\tstruct igb_ring_desc_16_bytes txd;\n\n\tring = (struct igb_ring_desc_16_bytes *)ring_mz->addr;\n\ttxd.lo_dword.dword = rte_le_to_cpu_64(ring[desc_id].lo_dword.dword);\n\ttxd.hi_dword.dword = rte_le_to_cpu_64(ring[desc_id].hi_dword.dword);\n\tprintf(\" 0x%08X - 0x%08X / 0x%08X - 0x%08X\\n\",\n\t\t\t(unsigned)txd.lo_dword.words.lo,\n\t\t\t(unsigned)txd.lo_dword.words.hi,\n\t\t\t(unsigned)txd.hi_dword.words.lo,\n\t\t\t(unsigned)txd.hi_dword.words.hi);\n}\n\nvoid\nrx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id)\n{\n\tconst struct rte_memzone *rx_mz;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tif (rx_queue_id_is_invalid(rxq_id))\n\t\treturn;\n\tif (rx_desc_id_is_invalid(rxd_id))\n\t\treturn;\n\trx_mz = ring_dma_zone_lookup(\"rx_ring\", port_id, rxq_id);\n\tif (rx_mz == NULL)\n\t\treturn;\n\tring_rx_descriptor_display(rx_mz, port_id, rxd_id);\n}\n\nvoid\ntx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id)\n{\n\tconst struct rte_memzone *tx_mz;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tif (tx_queue_id_is_invalid(txq_id))\n\t\treturn;\n\tif (tx_desc_id_is_invalid(txd_id))\n\t\treturn;\n\ttx_mz = ring_dma_zone_lookup(\"tx_ring\", port_id, txq_id);\n\tif (tx_mz == NULL)\n\t\treturn;\n\tring_tx_descriptor_display(tx_mz, txd_id);\n}\n\nvoid\nfwd_lcores_config_display(void)\n{\n\tlcoreid_t lc_id;\n\n\tprintf(\"List of forwarding lcores:\");\n\tfor (lc_id = 0; lc_id < nb_cfg_lcores; lc_id++)\n\t\tprintf(\" %2u\", fwd_lcores_cpuids[lc_id]);\n\tprintf(\"\\n\");\n}\nvoid\nrxtx_config_display(void)\n{\n\tprintf(\" %s packet forwarding - CRC stripping %s - \"\n\t \"packets/burst=%d\\n\", cur_fwd_eng->fwd_mode_name,\n\t rx_mode.hw_strip_crc ? \"enabled\" : \"disabled\",\n\t nb_pkt_per_burst);\n\n\tif (cur_fwd_eng == &tx_only_engine)\n\t\tprintf(\" packet len=%u - nb packet segments=%d\\n\",\n\t\t\t\t(unsigned)tx_pkt_length, (int) tx_pkt_nb_segs);\n\n\tstruct rte_eth_rxconf *rx_conf = &ports[0].rx_conf;\n\tstruct rte_eth_txconf *tx_conf = &ports[0].tx_conf;\n\n\tprintf(\" nb forwarding cores=%d - nb forwarding ports=%d\\n\",\n\t nb_fwd_lcores, nb_fwd_ports);\n\tprintf(\" RX queues=%d - RX desc=%d - RX free threshold=%d\\n\",\n\t nb_rxq, nb_rxd, rx_conf->rx_free_thresh);\n\tprintf(\" RX threshold registers: pthresh=%d hthresh=%d wthresh=%d\\n\",\n\t rx_conf->rx_thresh.pthresh, rx_conf->rx_thresh.hthresh,\n\t rx_conf->rx_thresh.wthresh);\n\tprintf(\" TX queues=%d - TX desc=%d - TX free threshold=%d\\n\",\n\t nb_txq, nb_txd, tx_conf->tx_free_thresh);\n\tprintf(\" TX threshold registers: pthresh=%d hthresh=%d wthresh=%d\\n\",\n\t tx_conf->tx_thresh.pthresh, tx_conf->tx_thresh.hthresh,\n\t tx_conf->tx_thresh.wthresh);\n\tprintf(\" TX RS bit threshold=%d - TXQ flags=0x%\"PRIx32\"\\n\",\n\t tx_conf->tx_rs_thresh, tx_conf->txq_flags);\n}\n\nvoid\nport_rss_reta_info(portid_t port_id,\n\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t uint16_t nb_entries)\n{\n\tuint16_t i, idx, shift;\n\tint ret;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\n\tret = rte_eth_dev_rss_reta_query(port_id, reta_conf, nb_entries);\n\tif (ret != 0) {\n\t\tprintf(\"Failed to get RSS RETA info, return code = %d\\n\", ret);\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < nb_entries; i++) {\n\t\tidx = i / RTE_RETA_GROUP_SIZE;\n\t\tshift = i % RTE_RETA_GROUP_SIZE;\n\t\tif (!(reta_conf[idx].mask & (1ULL << shift)))\n\t\t\tcontinue;\n\t\tprintf(\"RSS RETA configuration: hash index=%u, queue=%u\\n\",\n\t\t\t\t\ti, reta_conf[idx].reta[shift]);\n\t}\n}\n\n/*\n * Displays the RSS hash functions of a port, and, optionaly, the RSS hash\n * key of the port.\n */\nvoid\nport_rss_hash_conf_show(portid_t port_id, int show_rss_key)\n{\n\tstruct rss_type_info {\n\t\tchar str[32];\n\t\tuint64_t rss_type;\n\t};\n\tstatic const struct rss_type_info rss_type_table[] = {\n\t\t{\"ipv4\", ETH_RSS_IPV4},\n\t\t{\"ipv4-frag\", ETH_RSS_FRAG_IPV4},\n\t\t{\"ipv4-tcp\", ETH_RSS_NONFRAG_IPV4_TCP},\n\t\t{\"ipv4-udp\", ETH_RSS_NONFRAG_IPV4_UDP},\n\t\t{\"ipv4-sctp\", ETH_RSS_NONFRAG_IPV4_SCTP},\n\t\t{\"ipv4-other\", ETH_RSS_NONFRAG_IPV4_OTHER},\n\t\t{\"ipv6\", ETH_RSS_IPV6},\n\t\t{\"ipv6-frag\", ETH_RSS_FRAG_IPV6},\n\t\t{\"ipv6-tcp\", ETH_RSS_NONFRAG_IPV6_TCP},\n\t\t{\"ipv6-udp\", ETH_RSS_NONFRAG_IPV6_UDP},\n\t\t{\"ipv6-sctp\", ETH_RSS_NONFRAG_IPV6_SCTP},\n\t\t{\"ipv6-other\", ETH_RSS_NONFRAG_IPV6_OTHER},\n\t\t{\"l2-payload\", ETH_RSS_L2_PAYLOAD},\n\t\t{\"ipv6-ex\", ETH_RSS_IPV6_EX},\n\t\t{\"ipv6-tcp-ex\", ETH_RSS_IPV6_TCP_EX},\n\t\t{\"ipv6-udp-ex\", ETH_RSS_IPV6_UDP_EX},\n\t};\n\n\tstruct rte_eth_rss_conf rss_conf;\n\tuint8_t rss_key[10 * 4];\n\tuint64_t rss_hf;\n\tuint8_t i;\n\tint diag;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\t/* Get RSS hash key if asked to display it */\n\trss_conf.rss_key = (show_rss_key) ? rss_key : NULL;\n\tdiag = rte_eth_dev_rss_hash_conf_get(port_id, &rss_conf);\n\tif (diag != 0) {\n\t\tswitch (diag) {\n\t\tcase -ENODEV:\n\t\t\tprintf(\"port index %d invalid\\n\", port_id);\n\t\t\tbreak;\n\t\tcase -ENOTSUP:\n\t\t\tprintf(\"operation not supported by device\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"operation failed - diag=%d\\n\", diag);\n\t\t\tbreak;\n\t\t}\n\t\treturn;\n\t}\n\trss_hf = rss_conf.rss_hf;\n\tif (rss_hf == 0) {\n\t\tprintf(\"RSS disabled\\n\");\n\t\treturn;\n\t}\n\tprintf(\"RSS functions:\\n \");\n\tfor (i = 0; i < RTE_DIM(rss_type_table); i++) {\n\t\tif (rss_hf & rss_type_table[i].rss_type)\n\t\t\tprintf(\"%s \", rss_type_table[i].str);\n\t}\n\tprintf(\"\\n\");\n\tif (!show_rss_key)\n\t\treturn;\n\tprintf(\"RSS key:\\n\");\n\tfor (i = 0; i < sizeof(rss_key); i++)\n\t\tprintf(\"%02X\", rss_key[i]);\n\tprintf(\"\\n\");\n}\n\nvoid\nport_rss_hash_key_update(portid_t port_id, uint8_t *hash_key)\n{\n\tstruct rte_eth_rss_conf rss_conf;\n\tint diag;\n\n\trss_conf.rss_key = NULL;\n\tdiag = rte_eth_dev_rss_hash_conf_get(port_id, &rss_conf);\n\tif (diag == 0) {\n\t\trss_conf.rss_key = hash_key;\n\t\tdiag = rte_eth_dev_rss_hash_update(port_id, &rss_conf);\n\t}\n\tif (diag == 0)\n\t\treturn;\n\n\tswitch (diag) {\n\tcase -ENODEV:\n\t\tprintf(\"port index %d invalid\\n\", port_id);\n\t\tbreak;\n\tcase -ENOTSUP:\n\t\tprintf(\"operation not supported by device\\n\");\n\t\tbreak;\n\tdefault:\n\t\tprintf(\"operation failed - diag=%d\\n\", diag);\n\t\tbreak;\n\t}\n}\n\n/*\n * Setup forwarding configuration for each logical core.\n */\nstatic void\nsetup_fwd_config_of_each_lcore(struct fwd_config *cfg)\n{\n\tstreamid_t nb_fs_per_lcore;\n\tstreamid_t nb_fs;\n\tstreamid_t sm_id;\n\tlcoreid_t nb_extra;\n\tlcoreid_t nb_fc;\n\tlcoreid_t nb_lc;\n\tlcoreid_t lc_id;\n\n\tnb_fs = cfg->nb_fwd_streams;\n\tnb_fc = cfg->nb_fwd_lcores;\n\tif (nb_fs <= nb_fc) {\n\t\tnb_fs_per_lcore = 1;\n\t\tnb_extra = 0;\n\t} else {\n\t\tnb_fs_per_lcore = (streamid_t) (nb_fs / nb_fc);\n\t\tnb_extra = (lcoreid_t) (nb_fs % nb_fc);\n\t}\n\n\tnb_lc = (lcoreid_t) (nb_fc - nb_extra);\n\tsm_id = 0;\n\tfor (lc_id = 0; lc_id < nb_lc; lc_id++) {\n\t\tfwd_lcores[lc_id]->stream_idx = sm_id;\n\t\tfwd_lcores[lc_id]->stream_nb = nb_fs_per_lcore;\n\t\tsm_id = (streamid_t) (sm_id + nb_fs_per_lcore);\n\t}\n\n\t/*\n\t * Assign extra remaining streams, if any.\n\t */\n\tnb_fs_per_lcore = (streamid_t) (nb_fs_per_lcore + 1);\n\tfor (lc_id = 0; lc_id < nb_extra; lc_id++) {\n\t\tfwd_lcores[nb_lc + lc_id]->stream_idx = sm_id;\n\t\tfwd_lcores[nb_lc + lc_id]->stream_nb = nb_fs_per_lcore;\n\t\tsm_id = (streamid_t) (sm_id + nb_fs_per_lcore);\n\t}\n}\n\nstatic void\nsimple_fwd_config_setup(void)\n{\n\tportid_t i;\n\tportid_t j;\n\tportid_t inc = 2;\n\n\tif (port_topology == PORT_TOPOLOGY_CHAINED ||\n\t port_topology == PORT_TOPOLOGY_LOOP) {\n\t\tinc = 1;\n\t} else if (nb_fwd_ports % 2) {\n\t\tprintf(\"\\nWarning! Cannot handle an odd number of ports \"\n\t\t \"with the current port topology. Configuration \"\n\t\t \"must be changed to have an even number of ports, \"\n\t\t \"or relaunch application with \"\n\t\t \"--port-topology=chained\\n\\n\");\n\t}\n\n\tcur_fwd_config.nb_fwd_ports = (portid_t) nb_fwd_ports;\n\tcur_fwd_config.nb_fwd_streams =\n\t\t(streamid_t) cur_fwd_config.nb_fwd_ports;\n\n\t/* reinitialize forwarding streams */\n\tinit_fwd_streams();\n\n\t/*\n\t * In the simple forwarding test, the number of forwarding cores\n\t * must be lower or equal to the number of forwarding ports.\n\t */\n\tcur_fwd_config.nb_fwd_lcores = (lcoreid_t) nb_fwd_lcores;\n\tif (cur_fwd_config.nb_fwd_lcores > cur_fwd_config.nb_fwd_ports)\n\t\tcur_fwd_config.nb_fwd_lcores =\n\t\t\t(lcoreid_t) cur_fwd_config.nb_fwd_ports;\n\tsetup_fwd_config_of_each_lcore(&cur_fwd_config);\n\n\tfor (i = 0; i < cur_fwd_config.nb_fwd_ports; i = (portid_t) (i + inc)) {\n\t\tif (port_topology != PORT_TOPOLOGY_LOOP)\n\t\t\tj = (portid_t) ((i + 1) % cur_fwd_config.nb_fwd_ports);\n\t\telse\n\t\t\tj = i;\n\t\tfwd_streams[i]->rx_port = fwd_ports_ids[i];\n\t\tfwd_streams[i]->rx_queue = 0;\n\t\tfwd_streams[i]->tx_port = fwd_ports_ids[j];\n\t\tfwd_streams[i]->tx_queue = 0;\n\t\tfwd_streams[i]->peer_addr = j;\n\n\t\tif (port_topology == PORT_TOPOLOGY_PAIRED) {\n\t\t\tfwd_streams[j]->rx_port = fwd_ports_ids[j];\n\t\t\tfwd_streams[j]->rx_queue = 0;\n\t\t\tfwd_streams[j]->tx_port = fwd_ports_ids[i];\n\t\t\tfwd_streams[j]->tx_queue = 0;\n\t\t\tfwd_streams[j]->peer_addr = i;\n\t\t}\n\t}\n}\n\n/**\n * For the RSS forwarding test, each core is assigned on every port a transmit\n * queue whose index is the index of the core itself. This approach limits the\n * maximumm number of processing cores of the RSS test to the maximum number of\n * TX queues supported by the devices.\n *\n * Each core is assigned a single stream, each stream being composed of\n * a RX queue to poll on a RX port for input messages, associated with\n * a TX queue of a TX port where to send forwarded packets.\n * All packets received on the RX queue of index \"RxQj\" of the RX port \"RxPi\"\n * are sent on the TX queue \"TxQl\" of the TX port \"TxPk\" according to the two\n * following rules:\n * - TxPk = (RxPi + 1) if RxPi is even, (RxPi - 1) if RxPi is odd\n * - TxQl = RxQj\n */\nstatic void\nrss_fwd_config_setup(void)\n{\n\tportid_t rxp;\n\tportid_t txp;\n\tqueueid_t rxq;\n\tqueueid_t nb_q;\n\tlcoreid_t lc_id;\n\n\tnb_q = nb_rxq;\n\tif (nb_q > nb_txq)\n\t\tnb_q = nb_txq;\n\tcur_fwd_config.nb_fwd_lcores = (lcoreid_t) nb_fwd_lcores;\n\tcur_fwd_config.nb_fwd_ports = nb_fwd_ports;\n\tcur_fwd_config.nb_fwd_streams =\n\t\t(streamid_t) (nb_q * cur_fwd_config.nb_fwd_ports);\n\tif (cur_fwd_config.nb_fwd_streams > cur_fwd_config.nb_fwd_lcores)\n\t\tcur_fwd_config.nb_fwd_streams =\n\t\t\t(streamid_t)cur_fwd_config.nb_fwd_lcores;\n\telse\n\t\tcur_fwd_config.nb_fwd_lcores =\n\t\t\t(lcoreid_t)cur_fwd_config.nb_fwd_streams;\n\n\t/* reinitialize forwarding streams */\n\tinit_fwd_streams();\n\n\tsetup_fwd_config_of_each_lcore(&cur_fwd_config);\n\trxp = 0; rxq = 0;\n\tfor (lc_id = 0; lc_id < cur_fwd_config.nb_fwd_lcores; lc_id++) {\n\t\tstruct fwd_stream *fs;\n\n\t\tfs = fwd_streams[lc_id];\n\n\t\tif ((rxp & 0x1) == 0)\n\t\t\ttxp = (portid_t) (rxp + 1);\n\t\telse\n\t\t\ttxp = (portid_t) (rxp - 1);\n\t\t/*\n\t\t * if we are in loopback, simply send stuff out through the\n\t\t * ingress port\n\t\t */\n\t\tif (port_topology == PORT_TOPOLOGY_LOOP)\n\t\t\ttxp = rxp;\n\n\t\tfs->rx_port = fwd_ports_ids[rxp];\n\t\tfs->rx_queue = rxq;\n\t\tfs->tx_port = fwd_ports_ids[txp];\n\t\tfs->tx_queue = rxq;\n\t\tfs->peer_addr = fs->tx_port;\n\t\trxq = (queueid_t) (rxq + 1);\n\t\tif (rxq < nb_q)\n\t\t\tcontinue;\n\t\t/*\n\t\t * rxq == nb_q\n\t\t * Restart from RX queue 0 on next RX port\n\t\t */\n\t\trxq = 0;\n\t\tif (numa_support && (nb_fwd_ports <= (nb_ports >> 1)))\n\t\t\trxp = (portid_t)\n\t\t\t\t(rxp + ((nb_ports >> 1) / nb_fwd_ports));\n\t\telse\n\t\t\trxp = (portid_t) (rxp + 1);\n\t}\n}\n\n/*\n * In DCB and VT on,the mapping of 128 receive queues to 128 transmit queues.\n */\nstatic void\ndcb_rxq_2_txq_mapping(queueid_t rxq, queueid_t *txq)\n{\n\tif(dcb_q_mapping == DCB_4_TCS_Q_MAPPING) {\n\n\t\tif (rxq < 32)\n\t\t\t/* tc0: 0-31 */\n\t\t\t*txq = rxq;\n\t\telse if (rxq < 64) {\n\t\t\t/* tc1: 64-95 */\n\t\t\t*txq = (uint16_t)(rxq + 32);\n\t\t}\n\t\telse {\n\t\t\t/* tc2: 96-111;tc3:112-127 */\n\t\t\t*txq = (uint16_t)(rxq/2 + 64);\n\t\t}\n\t}\n\telse {\n\t\tif (rxq < 16)\n\t\t\t/* tc0 mapping*/\n\t\t\t*txq = rxq;\n\t\telse if (rxq < 32) {\n\t\t\t/* tc1 mapping*/\n\t\t\t *txq = (uint16_t)(rxq + 16);\n\t\t}\n\t\telse if (rxq < 64) {\n\t\t\t/*tc2,tc3 mapping */\n\t\t\t*txq = (uint16_t)(rxq + 32);\n\t\t}\n\t\telse {\n\t\t\t/* tc4,tc5,tc6 and tc7 mapping */\n\t\t\t*txq = (uint16_t)(rxq/2 + 64);\n\t\t}\n\t}\n}\n\n/**\n * For the DCB forwarding test, each core is assigned on every port multi-transmit\n * queue.\n *\n * Each core is assigned a multi-stream, each stream being composed of\n * a RX queue to poll on a RX port for input messages, associated with\n * a TX queue of a TX port where to send forwarded packets.\n * All packets received on the RX queue of index \"RxQj\" of the RX port \"RxPi\"\n * are sent on the TX queue \"TxQl\" of the TX port \"TxPk\" according to the two\n * following rules:\n * In VT mode,\n * - TxPk = (RxPi + 1) if RxPi is even, (RxPi - 1) if RxPi is odd\n * - TxQl = RxQj\n * In non-VT mode,\n * - TxPk = (RxPi + 1) if RxPi is even, (RxPi - 1) if RxPi is odd\n * There is a mapping of RxQj to TxQl to be required,and the mapping was implemented\n * in dcb_rxq_2_txq_mapping function.\n */\nstatic void\ndcb_fwd_config_setup(void)\n{\n\tportid_t rxp;\n\tportid_t txp;\n\tqueueid_t rxq;\n\tqueueid_t nb_q;\n\tlcoreid_t lc_id;\n\tuint16_t sm_id;\n\n\tnb_q = nb_rxq;\n\n\tcur_fwd_config.nb_fwd_lcores = (lcoreid_t) nb_fwd_lcores;\n\tcur_fwd_config.nb_fwd_ports = nb_fwd_ports;\n\tcur_fwd_config.nb_fwd_streams =\n\t\t(streamid_t) (nb_q * cur_fwd_config.nb_fwd_ports);\n\n\t/* reinitialize forwarding streams */\n\tinit_fwd_streams();\n\n\tsetup_fwd_config_of_each_lcore(&cur_fwd_config);\n\trxp = 0; rxq = 0;\n\tfor (lc_id = 0; lc_id < cur_fwd_config.nb_fwd_lcores; lc_id++) {\n\t\t/* a fwd core can run multi-streams */\n\t\tfor (sm_id = 0; sm_id < fwd_lcores[lc_id]->stream_nb; sm_id++)\n\t\t{\n\t\t\tstruct fwd_stream *fs;\n\t\t\tfs = fwd_streams[fwd_lcores[lc_id]->stream_idx + sm_id];\n\t\t\tif ((rxp & 0x1) == 0)\n\t\t\t\ttxp = (portid_t) (rxp + 1);\n\t\t\telse\n\t\t\t\ttxp = (portid_t) (rxp - 1);\n\t\t\tfs->rx_port = fwd_ports_ids[rxp];\n\t\t\tfs->rx_queue = rxq;\n\t\t\tfs->tx_port = fwd_ports_ids[txp];\n\t\t\tif (dcb_q_mapping == DCB_VT_Q_MAPPING)\n\t\t\t\tfs->tx_queue = rxq;\n\t\t\telse\n\t\t\t\tdcb_rxq_2_txq_mapping(rxq, &fs->tx_queue);\n\t\t\tfs->peer_addr = fs->tx_port;\n\t\t\trxq = (queueid_t) (rxq + 1);\n\t\t\tif (rxq < nb_q)\n\t\t\t\tcontinue;\n\t\t\trxq = 0;\n\t\t\tif (numa_support && (nb_fwd_ports <= (nb_ports >> 1)))\n\t\t\t\trxp = (portid_t)\n\t\t\t\t\t(rxp + ((nb_ports >> 1) / nb_fwd_ports));\n\t\t\telse\n\t\t\t\trxp = (portid_t) (rxp + 1);\n\t\t}\n\t}\n}\n\nstatic void\nicmp_echo_config_setup(void)\n{\n\tportid_t rxp;\n\tqueueid_t rxq;\n\tlcoreid_t lc_id;\n\tuint16_t sm_id;\n\n\tif ((nb_txq * nb_fwd_ports) < nb_fwd_lcores)\n\t\tcur_fwd_config.nb_fwd_lcores = (lcoreid_t)\n\t\t\t(nb_txq * nb_fwd_ports);\n\telse\n\t\tcur_fwd_config.nb_fwd_lcores = (lcoreid_t) nb_fwd_lcores;\n\tcur_fwd_config.nb_fwd_ports = nb_fwd_ports;\n\tcur_fwd_config.nb_fwd_streams =\n\t\t(streamid_t) (nb_rxq * cur_fwd_config.nb_fwd_ports);\n\tif (cur_fwd_config.nb_fwd_streams < cur_fwd_config.nb_fwd_lcores)\n\t\tcur_fwd_config.nb_fwd_lcores =\n\t\t\t(lcoreid_t)cur_fwd_config.nb_fwd_streams;\n\tif (verbose_level > 0) {\n\t\tprintf(\"%s fwd_cores=%d fwd_ports=%d fwd_streams=%d\\n\",\n\t\t __FUNCTION__,\n\t\t cur_fwd_config.nb_fwd_lcores,\n\t\t cur_fwd_config.nb_fwd_ports,\n\t\t cur_fwd_config.nb_fwd_streams);\n\t}\n\n\t/* reinitialize forwarding streams */\n\tinit_fwd_streams();\n\tsetup_fwd_config_of_each_lcore(&cur_fwd_config);\n\trxp = 0; rxq = 0;\n\tfor (lc_id = 0; lc_id < cur_fwd_config.nb_fwd_lcores; lc_id++) {\n\t\tif (verbose_level > 0)\n\t\t\tprintf(\" core=%d: \\n\", lc_id);\n\t\tfor (sm_id = 0; sm_id < fwd_lcores[lc_id]->stream_nb; sm_id++) {\n\t\t\tstruct fwd_stream *fs;\n\t\t\tfs = fwd_streams[fwd_lcores[lc_id]->stream_idx + sm_id];\n\t\t\tfs->rx_port = fwd_ports_ids[rxp];\n\t\t\tfs->rx_queue = rxq;\n\t\t\tfs->tx_port = fs->rx_port;\n\t\t\tfs->tx_queue = lc_id;\n\t\t\tfs->peer_addr = fs->tx_port;\n\t\t\tif (verbose_level > 0)\n\t\t\t\tprintf(\" stream=%d port=%d rxq=%d txq=%d\\n\",\n\t\t\t\t sm_id, fs->rx_port, fs->rx_queue,\n\t\t\t\t fs->tx_queue);\n\t\t\trxq = (queueid_t) (rxq + 1);\n\t\t\tif (rxq == nb_rxq) {\n\t\t\t\trxq = 0;\n\t\t\t\trxp = (portid_t) (rxp + 1);\n\t\t\t}\n\t\t}\n\t}\n}\n\nvoid\nfwd_config_setup(void)\n{\n\tcur_fwd_config.fwd_eng = cur_fwd_eng;\n\tif (strcmp(cur_fwd_eng->fwd_mode_name, \"icmpecho\") == 0) {\n\t\ticmp_echo_config_setup();\n\t\treturn;\n\t}\n\tif ((nb_rxq > 1) && (nb_txq > 1)){\n\t\tif (dcb_config)\n\t\t\tdcb_fwd_config_setup();\n\t\telse\n\t\t\trss_fwd_config_setup();\n\t}\n\telse\n\t\tsimple_fwd_config_setup();\n}\n\nstatic void\npkt_fwd_config_display(struct fwd_config *cfg)\n{\n\tstruct fwd_stream *fs;\n\tlcoreid_t lc_id;\n\tstreamid_t sm_id;\n\n\tprintf(\"%s packet forwarding - ports=%d - cores=%d - streams=%d - \"\n\t\t\"NUMA support %s, MP over anonymous pages %s\\n\",\n\t\tcfg->fwd_eng->fwd_mode_name,\n\t\tcfg->nb_fwd_ports, cfg->nb_fwd_lcores, cfg->nb_fwd_streams,\n\t\tnuma_support == 1 ? \"enabled\" : \"disabled\",\n\t\tmp_anon != 0 ? \"enabled\" : \"disabled\");\n\n\tif (strcmp(cfg->fwd_eng->fwd_mode_name, \"mac_retry\") == 0)\n\t\tprintf(\"TX retry num: %u, delay between TX retries: %uus\\n\",\n\t\t\tburst_tx_retry_num, burst_tx_delay_time);\n\tfor (lc_id = 0; lc_id < cfg->nb_fwd_lcores; lc_id++) {\n\t\tprintf(\"Logical Core %u (socket %u) forwards packets on \"\n\t\t \"%d streams:\",\n\t\t fwd_lcores_cpuids[lc_id],\n\t\t rte_lcore_to_socket_id(fwd_lcores_cpuids[lc_id]),\n\t\t fwd_lcores[lc_id]->stream_nb);\n\t\tfor (sm_id = 0; sm_id < fwd_lcores[lc_id]->stream_nb; sm_id++) {\n\t\t\tfs = fwd_streams[fwd_lcores[lc_id]->stream_idx + sm_id];\n\t\t\tprintf(\"\\n RX P=%d/Q=%d (socket %u) -> TX \"\n\t\t\t \"P=%d/Q=%d (socket %u) \",\n\t\t\t fs->rx_port, fs->rx_queue,\n\t\t\t ports[fs->rx_port].socket_id,\n\t\t\t fs->tx_port, fs->tx_queue,\n\t\t\t ports[fs->tx_port].socket_id);\n\t\t\tprint_ethaddr(\"peer=\",\n\t\t\t\t &peer_eth_addrs[fs->peer_addr]);\n\t\t}\n\t\tprintf(\"\\n\");\n\t}\n\tprintf(\"\\n\");\n}\n\n\nvoid\nfwd_config_display(void)\n{\n\tif((dcb_config) && (nb_fwd_lcores == 1)) {\n\t\tprintf(\"In DCB mode,the nb forwarding cores should be larger than 1\\n\");\n\t\treturn;\n\t}\n\tfwd_config_setup();\n\tpkt_fwd_config_display(&cur_fwd_config);\n}\n\nint\nset_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc)\n{\n\tunsigned int i;\n\tunsigned int lcore_cpuid;\n\tint record_now;\n\n\trecord_now = 0;\n again:\n\tfor (i = 0; i < nb_lc; i++) {\n\t\tlcore_cpuid = lcorelist[i];\n\t\tif (! rte_lcore_is_enabled(lcore_cpuid)) {\n\t\t\tprintf(\"lcore %u not enabled\\n\", lcore_cpuid);\n\t\t\treturn -1;\n\t\t}\n\t\tif (lcore_cpuid == rte_get_master_lcore()) {\n\t\t\tprintf(\"lcore %u cannot be masked on for running \"\n\t\t\t \"packet forwarding, which is the master lcore \"\n\t\t\t \"and reserved for command line parsing only\\n\",\n\t\t\t lcore_cpuid);\n\t\t\treturn -1;\n\t\t}\n\t\tif (record_now)\n\t\t\tfwd_lcores_cpuids[i] = lcore_cpuid;\n\t}\n\tif (record_now == 0) {\n\t\trecord_now = 1;\n\t\tgoto again;\n\t}\n\tnb_cfg_lcores = (lcoreid_t) nb_lc;\n\tif (nb_fwd_lcores != (lcoreid_t) nb_lc) {\n\t\tprintf(\"previous number of forwarding cores %u - changed to \"\n\t\t \"number of configured cores %u\\n\",\n\t\t (unsigned int) nb_fwd_lcores, nb_lc);\n\t\tnb_fwd_lcores = (lcoreid_t) nb_lc;\n\t}\n\n\treturn 0;\n}\n\nint\nset_fwd_lcores_mask(uint64_t lcoremask)\n{\n\tunsigned int lcorelist[64];\n\tunsigned int nb_lc;\n\tunsigned int i;\n\n\tif (lcoremask == 0) {\n\t\tprintf(\"Invalid NULL mask of cores\\n\");\n\t\treturn -1;\n\t}\n\tnb_lc = 0;\n\tfor (i = 0; i < 64; i++) {\n\t\tif (! ((uint64_t)(1ULL << i) & lcoremask))\n\t\t\tcontinue;\n\t\tlcorelist[nb_lc++] = i;\n\t}\n\treturn set_fwd_lcores_list(lcorelist, nb_lc);\n}\n\nvoid\nset_fwd_lcores_number(uint16_t nb_lc)\n{\n\tif (nb_lc > nb_cfg_lcores) {\n\t\tprintf(\"nb fwd cores %u > %u (max. number of configured \"\n\t\t \"lcores) - ignored\\n\",\n\t\t (unsigned int) nb_lc, (unsigned int) nb_cfg_lcores);\n\t\treturn;\n\t}\n\tnb_fwd_lcores = (lcoreid_t) nb_lc;\n\tprintf(\"Number of forwarding cores set to %u\\n\",\n\t (unsigned int) nb_fwd_lcores);\n}\n\nvoid\nset_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt)\n{\n\tunsigned int i;\n\tportid_t port_id;\n\tint record_now;\n\n\trecord_now = 0;\n again:\n\tfor (i = 0; i < nb_pt; i++) {\n\t\tport_id = (portid_t) portlist[i];\n\t\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\t\treturn;\n\t\tif (record_now)\n\t\t\tfwd_ports_ids[i] = port_id;\n\t}\n\tif (record_now == 0) {\n\t\trecord_now = 1;\n\t\tgoto again;\n\t}\n\tnb_cfg_ports = (portid_t) nb_pt;\n\tif (nb_fwd_ports != (portid_t) nb_pt) {\n\t\tprintf(\"previous number of forwarding ports %u - changed to \"\n\t\t \"number of configured ports %u\\n\",\n\t\t (unsigned int) nb_fwd_ports, nb_pt);\n\t\tnb_fwd_ports = (portid_t) nb_pt;\n\t}\n}\n\nvoid\nset_fwd_ports_mask(uint64_t portmask)\n{\n\tunsigned int portlist[64];\n\tunsigned int nb_pt;\n\tunsigned int i;\n\n\tif (portmask == 0) {\n\t\tprintf(\"Invalid NULL mask of ports\\n\");\n\t\treturn;\n\t}\n\tnb_pt = 0;\n\tfor (i = 0; i < (unsigned)RTE_MIN(64, RTE_MAX_ETHPORTS); i++) {\n\t\tif (! ((uint64_t)(1ULL << i) & portmask))\n\t\t\tcontinue;\n\t\tportlist[nb_pt++] = i;\n\t}\n\tset_fwd_ports_list(portlist, nb_pt);\n}\n\nvoid\nset_fwd_ports_number(uint16_t nb_pt)\n{\n\tif (nb_pt > nb_cfg_ports) {\n\t\tprintf(\"nb fwd ports %u > %u (number of configured \"\n\t\t \"ports) - ignored\\n\",\n\t\t (unsigned int) nb_pt, (unsigned int) nb_cfg_ports);\n\t\treturn;\n\t}\n\tnb_fwd_ports = (portid_t) nb_pt;\n\tprintf(\"Number of forwarding ports set to %u\\n\",\n\t (unsigned int) nb_fwd_ports);\n}\n\nvoid\nset_nb_pkt_per_burst(uint16_t nb)\n{\n\tif (nb > MAX_PKT_BURST) {\n\t\tprintf(\"nb pkt per burst: %u > %u (maximum packet per burst) \"\n\t\t \" ignored\\n\",\n\t\t (unsigned int) nb, (unsigned int) MAX_PKT_BURST);\n\t\treturn;\n\t}\n\tnb_pkt_per_burst = nb;\n\tprintf(\"Number of packets per burst set to %u\\n\",\n\t (unsigned int) nb_pkt_per_burst);\n}\n\nvoid\nset_tx_pkt_segments(unsigned *seg_lengths, unsigned nb_segs)\n{\n\tuint16_t tx_pkt_len;\n\tunsigned i;\n\n\tif (nb_segs >= (unsigned) nb_txd) {\n\t\tprintf(\"nb segments per TX packets=%u >= nb_txd=%u - ignored\\n\",\n\t\t nb_segs, (unsigned int) nb_txd);\n\t\treturn;\n\t}\n\n\t/*\n\t * Check that each segment length is greater or equal than\n\t * the mbuf data sise.\n\t * Check also that the total packet length is greater or equal than the\n\t * size of an empty UDP/IP packet (sizeof(struct ether_hdr) + 20 + 8).\n\t */\n\ttx_pkt_len = 0;\n\tfor (i = 0; i < nb_segs; i++) {\n\t\tif (seg_lengths[i] > (unsigned) mbuf_data_size) {\n\t\t\tprintf(\"length[%u]=%u > mbuf_data_size=%u - give up\\n\",\n\t\t\t i, seg_lengths[i], (unsigned) mbuf_data_size);\n\t\t\treturn;\n\t\t}\n\t\ttx_pkt_len = (uint16_t)(tx_pkt_len + seg_lengths[i]);\n\t}\n\tif (tx_pkt_len < (sizeof(struct ether_hdr) + 20 + 8)) {\n\t\tprintf(\"total packet length=%u < %d - give up\\n\",\n\t\t\t\t(unsigned) tx_pkt_len,\n\t\t\t\t(int)(sizeof(struct ether_hdr) + 20 + 8));\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < nb_segs; i++)\n\t\ttx_pkt_seg_lengths[i] = (uint16_t) seg_lengths[i];\n\n\ttx_pkt_length = tx_pkt_len;\n\ttx_pkt_nb_segs = (uint8_t) nb_segs;\n}\n\nchar*\nlist_pkt_forwarding_modes(void)\n{\n\tstatic char fwd_modes[128] = \"\";\n\tconst char *separator = \"|\";\n\tstruct fwd_engine *fwd_eng;\n\tunsigned i = 0;\n\n\tif (strlen (fwd_modes) == 0) {\n\t\twhile ((fwd_eng = fwd_engines[i++]) != NULL) {\n\t\t\tstrcat(fwd_modes, fwd_eng->fwd_mode_name);\n\t\t\tstrcat(fwd_modes, separator);\n\t\t}\n\t\tfwd_modes[strlen(fwd_modes) - strlen(separator)] = '\\0';\n\t}\n\n\treturn fwd_modes;\n}\n\nvoid\nset_pkt_forwarding_mode(const char *fwd_mode_name)\n{\n\tstruct fwd_engine *fwd_eng;\n\tunsigned i;\n\n\ti = 0;\n\twhile ((fwd_eng = fwd_engines[i]) != NULL) {\n\t\tif (! strcmp(fwd_eng->fwd_mode_name, fwd_mode_name)) {\n\t\t\tprintf(\"Set %s packet forwarding mode\\n\",\n\t\t\t fwd_mode_name);\n\t\t\tcur_fwd_eng = fwd_eng;\n\t\t\treturn;\n\t\t}\n\t\ti++;\n\t}\n\tprintf(\"Invalid %s packet forwarding mode\\n\", fwd_mode_name);\n}\n\nvoid\nset_verbose_level(uint16_t vb_level)\n{\n\tprintf(\"Change verbose level from %u to %u\\n\",\n\t (unsigned int) verbose_level, (unsigned int) vb_level);\n\tverbose_level = vb_level;\n}\n\nvoid\nvlan_extend_set(portid_t port_id, int on)\n{\n\tint diag;\n\tint vlan_offload;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\n\tvlan_offload = rte_eth_dev_get_vlan_offload(port_id);\n\n\tif (on)\n\t\tvlan_offload |= ETH_VLAN_EXTEND_OFFLOAD;\n\telse\n\t\tvlan_offload &= ~ETH_VLAN_EXTEND_OFFLOAD;\n\n\tdiag = rte_eth_dev_set_vlan_offload(port_id, vlan_offload);\n\tif (diag < 0)\n\t\tprintf(\"rx_vlan_extend_set(port_pi=%d, on=%d) failed \"\n\t \"diag=%d\\n\", port_id, on, diag);\n}\n\nvoid\nrx_vlan_strip_set(portid_t port_id, int on)\n{\n\tint diag;\n\tint vlan_offload;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\n\tvlan_offload = rte_eth_dev_get_vlan_offload(port_id);\n\n\tif (on)\n\t\tvlan_offload |= ETH_VLAN_STRIP_OFFLOAD;\n\telse\n\t\tvlan_offload &= ~ETH_VLAN_STRIP_OFFLOAD;\n\n\tdiag = rte_eth_dev_set_vlan_offload(port_id, vlan_offload);\n\tif (diag < 0)\n\t\tprintf(\"rx_vlan_strip_set(port_pi=%d, on=%d) failed \"\n\t \"diag=%d\\n\", port_id, on, diag);\n}\n\nvoid\nrx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on)\n{\n\tint diag;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\n\tdiag = rte_eth_dev_set_vlan_strip_on_queue(port_id, queue_id, on);\n\tif (diag < 0)\n\t\tprintf(\"rx_vlan_strip_set_on_queue(port_pi=%d, queue_id=%d, on=%d) failed \"\n\t \"diag=%d\\n\", port_id, queue_id, on, diag);\n}\n\nvoid\nrx_vlan_filter_set(portid_t port_id, int on)\n{\n\tint diag;\n\tint vlan_offload;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\n\tvlan_offload = rte_eth_dev_get_vlan_offload(port_id);\n\n\tif (on)\n\t\tvlan_offload |= ETH_VLAN_FILTER_OFFLOAD;\n\telse\n\t\tvlan_offload &= ~ETH_VLAN_FILTER_OFFLOAD;\n\n\tdiag = rte_eth_dev_set_vlan_offload(port_id, vlan_offload);\n\tif (diag < 0)\n\t\tprintf(\"rx_vlan_filter_set(port_pi=%d, on=%d) failed \"\n\t \"diag=%d\\n\", port_id, on, diag);\n}\n\nint\nrx_vft_set(portid_t port_id, uint16_t vlan_id, int on)\n{\n\tint diag;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn 1;\n\tif (vlan_id_is_invalid(vlan_id))\n\t\treturn 1;\n\tdiag = rte_eth_dev_vlan_filter(port_id, vlan_id, on);\n\tif (diag == 0)\n\t\treturn 0;\n\tprintf(\"rte_eth_dev_vlan_filter(port_pi=%d, vlan_id=%d, on=%d) failed \"\n\t \"diag=%d\\n\",\n\t port_id, vlan_id, on, diag);\n\treturn -1;\n}\n\nvoid\nrx_vlan_all_filter_set(portid_t port_id, int on)\n{\n\tuint16_t vlan_id;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tfor (vlan_id = 0; vlan_id < 4096; vlan_id++) {\n\t\tif (rx_vft_set(port_id, vlan_id, on))\n\t\t\tbreak;\n\t}\n}\n\nvoid\nvlan_tpid_set(portid_t port_id, uint16_t tp_id)\n{\n\tint diag;\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\n\tdiag = rte_eth_dev_set_vlan_ether_type(port_id, tp_id);\n\tif (diag == 0)\n\t\treturn;\n\n\tprintf(\"tx_vlan_tpid_set(port_pi=%d, tpid=%d) failed \"\n\t \"diag=%d\\n\",\n\t port_id, tp_id, diag);\n}\n\nvoid\ntx_vlan_set(portid_t port_id, uint16_t vlan_id)\n{\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tif (vlan_id_is_invalid(vlan_id))\n\t\treturn;\n\ttx_vlan_reset(port_id);\n\tports[port_id].tx_ol_flags |= TESTPMD_TX_OFFLOAD_INSERT_VLAN;\n\tports[port_id].tx_vlan_id = vlan_id;\n}\n\nvoid\ntx_qinq_set(portid_t port_id, uint16_t vlan_id, uint16_t vlan_id_outer)\n{\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tif (vlan_id_is_invalid(vlan_id))\n\t\treturn;\n\tif (vlan_id_is_invalid(vlan_id_outer))\n\t\treturn;\n\ttx_vlan_reset(port_id);\n\tports[port_id].tx_ol_flags |= TESTPMD_TX_OFFLOAD_INSERT_QINQ;\n\tports[port_id].tx_vlan_id = vlan_id;\n\tports[port_id].tx_vlan_id_outer = vlan_id_outer;\n}\n\nvoid\ntx_vlan_reset(portid_t port_id)\n{\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tports[port_id].tx_ol_flags &= ~(TESTPMD_TX_OFFLOAD_INSERT_VLAN |\n\t\t\t\tTESTPMD_TX_OFFLOAD_INSERT_QINQ);\n\tports[port_id].tx_vlan_id = 0;\n\tports[port_id].tx_vlan_id_outer = 0;\n}\n\nvoid\ntx_vlan_pvid_set(portid_t port_id, uint16_t vlan_id, int on)\n{\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\n\trte_eth_dev_set_vlan_pvid(port_id, vlan_id, on);\n}\n\nvoid\nset_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value)\n{\n\tuint16_t i;\n\tuint8_t existing_mapping_found = 0;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\n\tif (is_rx ? (rx_queue_id_is_invalid(queue_id)) : (tx_queue_id_is_invalid(queue_id)))\n\t\treturn;\n\n\tif (map_value >= RTE_ETHDEV_QUEUE_STAT_CNTRS) {\n\t\tprintf(\"map_value not in required range 0..%d\\n\",\n\t\t\t\tRTE_ETHDEV_QUEUE_STAT_CNTRS - 1);\n\t\treturn;\n\t}\n\n\tif (!is_rx) { /*then tx*/\n\t\tfor (i = 0; i < nb_tx_queue_stats_mappings; i++) {\n\t\t\tif ((tx_queue_stats_mappings[i].port_id == port_id) &&\n\t\t\t (tx_queue_stats_mappings[i].queue_id == queue_id)) {\n\t\t\t\ttx_queue_stats_mappings[i].stats_counter_id = map_value;\n\t\t\t\texisting_mapping_found = 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (!existing_mapping_found) { /* A new additional mapping... */\n\t\t\ttx_queue_stats_mappings[nb_tx_queue_stats_mappings].port_id = port_id;\n\t\t\ttx_queue_stats_mappings[nb_tx_queue_stats_mappings].queue_id = queue_id;\n\t\t\ttx_queue_stats_mappings[nb_tx_queue_stats_mappings].stats_counter_id = map_value;\n\t\t\tnb_tx_queue_stats_mappings++;\n\t\t}\n\t}\n\telse { /*rx*/\n\t\tfor (i = 0; i < nb_rx_queue_stats_mappings; i++) {\n\t\t\tif ((rx_queue_stats_mappings[i].port_id == port_id) &&\n\t\t\t (rx_queue_stats_mappings[i].queue_id == queue_id)) {\n\t\t\t\trx_queue_stats_mappings[i].stats_counter_id = map_value;\n\t\t\t\texisting_mapping_found = 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (!existing_mapping_found) { /* A new additional mapping... */\n\t\t\trx_queue_stats_mappings[nb_rx_queue_stats_mappings].port_id = port_id;\n\t\t\trx_queue_stats_mappings[nb_rx_queue_stats_mappings].queue_id = queue_id;\n\t\t\trx_queue_stats_mappings[nb_rx_queue_stats_mappings].stats_counter_id = map_value;\n\t\t\tnb_rx_queue_stats_mappings++;\n\t\t}\n\t}\n}\n\nstatic inline void\nprint_fdir_mask(struct rte_eth_fdir_masks *mask)\n{\n\tprintf(\"\\n vlan_tci: 0x%04x, src_ipv4: 0x%08x, dst_ipv4: 0x%08x,\"\n\t\t \" src_port: 0x%04x, dst_port: 0x%04x\",\n\t\tmask->vlan_tci_mask, mask->ipv4_mask.src_ip,\n\t\tmask->ipv4_mask.dst_ip,\n\t\tmask->src_port_mask, mask->dst_port_mask);\n\n\tprintf(\"\\n src_ipv6: 0x%08x,0x%08x,0x%08x,0x%08x,\"\n\t\t \" dst_ipv6: 0x%08x,0x%08x,0x%08x,0x%08x\",\n\t\tmask->ipv6_mask.src_ip[0], mask->ipv6_mask.src_ip[1],\n\t\tmask->ipv6_mask.src_ip[2], mask->ipv6_mask.src_ip[3],\n\t\tmask->ipv6_mask.dst_ip[0], mask->ipv6_mask.dst_ip[1],\n\t\tmask->ipv6_mask.dst_ip[2], mask->ipv6_mask.dst_ip[3]);\n\tprintf(\"\\n\");\n}\n\nstatic inline void\nprint_fdir_flex_payload(struct rte_eth_fdir_flex_conf *flex_conf, uint32_t num)\n{\n\tstruct rte_eth_flex_payload_cfg *cfg;\n\tuint32_t i, j;\n\n\tfor (i = 0; i < flex_conf->nb_payloads; i++) {\n\t\tcfg = &flex_conf->flex_set[i];\n\t\tif (cfg->type == RTE_ETH_RAW_PAYLOAD)\n\t\t\tprintf(\"\\n RAW: \");\n\t\telse if (cfg->type == RTE_ETH_L2_PAYLOAD)\n\t\t\tprintf(\"\\n L2_PAYLOAD: \");\n\t\telse if (cfg->type == RTE_ETH_L3_PAYLOAD)\n\t\t\tprintf(\"\\n L3_PAYLOAD: \");\n\t\telse if (cfg->type == RTE_ETH_L4_PAYLOAD)\n\t\t\tprintf(\"\\n L4_PAYLOAD: \");\n\t\telse\n\t\t\tprintf(\"\\n UNKNOWN PAYLOAD(%u): \", cfg->type);\n\t\tfor (j = 0; j < num; j++)\n\t\t\tprintf(\" %-5u\", cfg->src_offset[j]);\n\t}\n\tprintf(\"\\n\");\n}\n\nstatic char *\nflowtype_to_str(uint16_t flow_type)\n{\n\tstruct flow_type_info {\n\t\tchar str[32];\n\t\tuint16_t ftype;\n\t};\n\n\tuint8_t i;\n\tstatic struct flow_type_info flowtype_str_table[] = {\n\t\t{\"raw\", RTE_ETH_FLOW_RAW},\n\t\t{\"ipv4\", RTE_ETH_FLOW_IPV4},\n\t\t{\"ipv4-frag\", RTE_ETH_FLOW_FRAG_IPV4},\n\t\t{\"ipv4-tcp\", RTE_ETH_FLOW_NONFRAG_IPV4_TCP},\n\t\t{\"ipv4-udp\", RTE_ETH_FLOW_NONFRAG_IPV4_UDP},\n\t\t{\"ipv4-sctp\", RTE_ETH_FLOW_NONFRAG_IPV4_SCTP},\n\t\t{\"ipv4-other\", RTE_ETH_FLOW_NONFRAG_IPV4_OTHER},\n\t\t{\"ipv6\", RTE_ETH_FLOW_IPV6},\n\t\t{\"ipv6-frag\", RTE_ETH_FLOW_FRAG_IPV6},\n\t\t{\"ipv6-tcp\", RTE_ETH_FLOW_NONFRAG_IPV6_TCP},\n\t\t{\"ipv6-udp\", RTE_ETH_FLOW_NONFRAG_IPV6_UDP},\n\t\t{\"ipv6-sctp\", RTE_ETH_FLOW_NONFRAG_IPV6_SCTP},\n\t\t{\"ipv6-other\", RTE_ETH_FLOW_NONFRAG_IPV6_OTHER},\n\t\t{\"l2_payload\", RTE_ETH_FLOW_L2_PAYLOAD},\n\t};\n\n\tfor (i = 0; i < RTE_DIM(flowtype_str_table); i++) {\n\t\tif (flowtype_str_table[i].ftype == flow_type)\n\t\t\treturn flowtype_str_table[i].str;\n\t}\n\n\treturn NULL;\n}\n\nstatic inline void\nprint_fdir_flex_mask(struct rte_eth_fdir_flex_conf *flex_conf, uint32_t num)\n{\n\tstruct rte_eth_fdir_flex_mask *mask;\n\tuint32_t i, j;\n\tchar *p;\n\n\tfor (i = 0; i < flex_conf->nb_flexmasks; i++) {\n\t\tmask = &flex_conf->flex_mask[i];\n\t\tp = flowtype_to_str(mask->flow_type);\n\t\tprintf(\"\\n %s:\\t\", p ? p : \"unknown\");\n\t\tfor (j = 0; j < num; j++)\n\t\t\tprintf(\" %02x\", mask->mask[j]);\n\t}\n\tprintf(\"\\n\");\n}\n\nstatic inline void\nprint_fdir_flow_type(uint32_t flow_types_mask)\n{\n\tint i;\n\tchar *p;\n\n\tfor (i = RTE_ETH_FLOW_UNKNOWN; i < RTE_ETH_FLOW_MAX; i++) {\n\t\tif (!(flow_types_mask & (1 << i)))\n\t\t\tcontinue;\n\t\tp = flowtype_to_str(i);\n\t\tif (p)\n\t\t\tprintf(\" %s\", p);\n\t\telse\n\t\t\tprintf(\" unknown\");\n\t}\n\tprintf(\"\\n\");\n}\n\nvoid\nfdir_get_infos(portid_t port_id)\n{\n\tstruct rte_eth_fdir_stats fdir_stat;\n\tstruct rte_eth_fdir_info fdir_info;\n\tint ret;\n\n\tstatic const char *fdir_stats_border = \"########################\";\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tret = rte_eth_dev_filter_supported(port_id, RTE_ETH_FILTER_FDIR);\n\tif (ret < 0) {\n\t\tprintf(\"\\n FDIR is not supported on port %-2d\\n\",\n\t\t\tport_id);\n\t\treturn;\n\t}\n\n\tmemset(&fdir_info, 0, sizeof(fdir_info));\n\trte_eth_dev_filter_ctrl(port_id, RTE_ETH_FILTER_FDIR,\n\t\t\t RTE_ETH_FILTER_INFO, &fdir_info);\n\tmemset(&fdir_stat, 0, sizeof(fdir_stat));\n\trte_eth_dev_filter_ctrl(port_id, RTE_ETH_FILTER_FDIR,\n\t\t\t RTE_ETH_FILTER_STATS, &fdir_stat);\n\tprintf(\"\\n %s FDIR infos for port %-2d %s\\n\",\n\t fdir_stats_border, port_id, fdir_stats_border);\n\tprintf(\" MODE: \");\n\tif (fdir_info.mode == RTE_FDIR_MODE_PERFECT)\n\t\tprintf(\" PERFECT\\n\");\n\telse if (fdir_info.mode == RTE_FDIR_MODE_SIGNATURE)\n\t\tprintf(\" SIGNATURE\\n\");\n\telse\n\t\tprintf(\" DISABLE\\n\");\n\tprintf(\" SUPPORTED FLOW TYPE: \");\n\tprint_fdir_flow_type(fdir_info.flow_types_mask[0]);\n\tprintf(\" FLEX PAYLOAD INFO:\\n\");\n\tprintf(\" max_len: %-10\"PRIu32\" payload_limit: %-10\"PRIu32\"\\n\"\n\t \" payload_unit: %-10\"PRIu32\" payload_seg: %-10\"PRIu32\"\\n\"\n\t \" bitmask_unit: %-10\"PRIu32\" bitmask_num: %-10\"PRIu32\"\\n\",\n\t\tfdir_info.max_flexpayload, fdir_info.flex_payload_limit,\n\t\tfdir_info.flex_payload_unit,\n\t\tfdir_info.max_flex_payload_segment_num,\n\t\tfdir_info.flex_bitmask_unit, fdir_info.max_flex_bitmask_num);\n\tprintf(\" MASK: \");\n\tprint_fdir_mask(&fdir_info.mask);\n\tif (fdir_info.flex_conf.nb_payloads > 0) {\n\t\tprintf(\" FLEX PAYLOAD SRC OFFSET:\");\n\t\tprint_fdir_flex_payload(&fdir_info.flex_conf, fdir_info.max_flexpayload);\n\t}\n\tif (fdir_info.flex_conf.nb_flexmasks > 0) {\n\t\tprintf(\" FLEX MASK CFG:\");\n\t\tprint_fdir_flex_mask(&fdir_info.flex_conf, fdir_info.max_flexpayload);\n\t}\n\tprintf(\" guarant_count: %-10\"PRIu32\" best_count: %\"PRIu32\"\\n\",\n\t fdir_stat.guarant_cnt, fdir_stat.best_cnt);\n\tprintf(\" guarant_space: %-10\"PRIu32\" best_space: %\"PRIu32\"\\n\",\n\t fdir_info.guarant_spc, fdir_info.best_spc);\n\tprintf(\" collision: %-10\"PRIu32\" free: %\"PRIu32\"\\n\"\n\t \" maxhash: %-10\"PRIu32\" maxlen: %\"PRIu32\"\\n\"\n\t \" add:\t %-10\"PRIu64\" remove: %\"PRIu64\"\\n\"\n\t \" f_add: %-10\"PRIu64\" f_remove: %\"PRIu64\"\\n\",\n\t fdir_stat.collision, fdir_stat.free,\n\t fdir_stat.maxhash, fdir_stat.maxlen,\n\t fdir_stat.add, fdir_stat.remove,\n\t fdir_stat.f_add, fdir_stat.f_remove);\n\tprintf(\" %s############################%s\\n\",\n\t fdir_stats_border, fdir_stats_border);\n}\n\nvoid\nfdir_set_flex_mask(portid_t port_id, struct rte_eth_fdir_flex_mask *cfg)\n{\n\tstruct rte_port *port;\n\tstruct rte_eth_fdir_flex_conf *flex_conf;\n\tint i, idx = 0;\n\n\tport = &ports[port_id];\n\tflex_conf = &port->dev_conf.fdir_conf.flex_conf;\n\tfor (i = 0; i < RTE_ETH_FLOW_MAX; i++) {\n\t\tif (cfg->flow_type == flex_conf->flex_mask[i].flow_type) {\n\t\t\tidx = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (i >= RTE_ETH_FLOW_MAX) {\n\t\tif (flex_conf->nb_flexmasks < RTE_DIM(flex_conf->flex_mask)) {\n\t\t\tidx = flex_conf->nb_flexmasks;\n\t\t\tflex_conf->nb_flexmasks++;\n\t\t} else {\n\t\t\tprintf(\"The flex mask table is full. Can not set flex\"\n\t\t\t\t\" mask for flow_type(%u).\", cfg->flow_type);\n\t\t\treturn;\n\t\t}\n\t}\n\t(void)rte_memcpy(&flex_conf->flex_mask[idx],\n\t\t\t cfg,\n\t\t\t sizeof(struct rte_eth_fdir_flex_mask));\n}\n\nvoid\nfdir_set_flex_payload(portid_t port_id, struct rte_eth_flex_payload_cfg *cfg)\n{\n\tstruct rte_port *port;\n\tstruct rte_eth_fdir_flex_conf *flex_conf;\n\tint i, idx = 0;\n\n\tport = &ports[port_id];\n\tflex_conf = &port->dev_conf.fdir_conf.flex_conf;\n\tfor (i = 0; i < RTE_ETH_PAYLOAD_MAX; i++) {\n\t\tif (cfg->type == flex_conf->flex_set[i].type) {\n\t\t\tidx = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (i >= RTE_ETH_PAYLOAD_MAX) {\n\t\tif (flex_conf->nb_payloads < RTE_DIM(flex_conf->flex_set)) {\n\t\t\tidx = flex_conf->nb_payloads;\n\t\t\tflex_conf->nb_payloads++;\n\t\t} else {\n\t\t\tprintf(\"The flex payload table is full. Can not set\"\n\t\t\t\t\" flex payload for type(%u).\", cfg->type);\n\t\t\treturn;\n\t\t}\n\t}\n\t(void)rte_memcpy(&flex_conf->flex_set[idx],\n\t\t\t cfg,\n\t\t\t sizeof(struct rte_eth_flex_payload_cfg));\n\n}\n\nvoid\nset_vf_traffic(portid_t port_id, uint8_t is_rx, uint16_t vf, uint8_t on)\n{\n\tint diag;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tif (is_rx)\n\t\tdiag = rte_eth_dev_set_vf_rx(port_id,vf,on);\n\telse\n\t\tdiag = rte_eth_dev_set_vf_tx(port_id,vf,on);\n\tif (diag == 0)\n\t\treturn;\n\tif(is_rx)\n\t\tprintf(\"rte_eth_dev_set_vf_rx for port_id=%d failed \"\n\t \t\t\"diag=%d\\n\", port_id, diag);\n\telse\n\t\tprintf(\"rte_eth_dev_set_vf_tx for port_id=%d failed \"\n\t \t\t\"diag=%d\\n\", port_id, diag);\n\n}\n\nvoid\nset_vf_rx_vlan(portid_t port_id, uint16_t vlan_id, uint64_t vf_mask, uint8_t on)\n{\n\tint diag;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\tif (vlan_id_is_invalid(vlan_id))\n\t\treturn;\n\tdiag = rte_eth_dev_set_vf_vlan_filter(port_id, vlan_id, vf_mask, on);\n\tif (diag == 0)\n\t\treturn;\n\tprintf(\"rte_eth_dev_set_vf_vlan_filter for port_id=%d failed \"\n\t \"diag=%d\\n\", port_id, diag);\n}\n\nint\nset_queue_rate_limit(portid_t port_id, uint16_t queue_idx, uint16_t rate)\n{\n\tint diag;\n\tstruct rte_eth_link link;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn 1;\n\trte_eth_link_get_nowait(port_id, &link);\n\tif (rate > link.link_speed) {\n\t\tprintf(\"Invalid rate value:%u bigger than link speed: %u\\n\",\n\t\t\trate, link.link_speed);\n\t\treturn 1;\n\t}\n\tdiag = rte_eth_set_queue_rate_limit(port_id, queue_idx, rate);\n\tif (diag == 0)\n\t\treturn diag;\n\tprintf(\"rte_eth_set_queue_rate_limit for port_id=%d failed diag=%d\\n\",\n\t\tport_id, diag);\n\treturn diag;\n}\n\nint\nset_vf_rate_limit(portid_t port_id, uint16_t vf, uint16_t rate, uint64_t q_msk)\n{\n\tint diag;\n\tstruct rte_eth_link link;\n\n\tif (q_msk == 0)\n\t\treturn 0;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn 1;\n\trte_eth_link_get_nowait(port_id, &link);\n\tif (rate > link.link_speed) {\n\t\tprintf(\"Invalid rate value:%u bigger than link speed: %u\\n\",\n\t\t\trate, link.link_speed);\n\t\treturn 1;\n\t}\n\tdiag = rte_eth_set_vf_rate_limit(port_id, vf, rate, q_msk);\n\tif (diag == 0)\n\t\treturn diag;\n\tprintf(\"rte_eth_set_vf_rate_limit for port_id=%d failed diag=%d\\n\",\n\t\tport_id, diag);\n\treturn diag;\n}\n\n/*\n * Functions to manage the set of filtered Multicast MAC addresses.\n *\n * A pool of filtered multicast MAC addresses is associated with each port.\n * The pool is allocated in chunks of MCAST_POOL_INC multicast addresses.\n * The address of the pool and the number of valid multicast MAC addresses\n * recorded in the pool are stored in the fields \"mc_addr_pool\" and\n * \"mc_addr_nb\" of the \"rte_port\" data structure.\n *\n * The function \"rte_eth_dev_set_mc_addr_list\" of the PMDs API imposes\n * to be supplied a contiguous array of multicast MAC addresses.\n * To comply with this constraint, the set of multicast addresses recorded\n * into the pool are systematically compacted at the beginning of the pool.\n * Hence, when a multicast address is removed from the pool, all following\n * addresses, if any, are copied back to keep the set contiguous.\n */\n#define MCAST_POOL_INC 32\n\nstatic int\nmcast_addr_pool_extend(struct rte_port *port)\n{\n\tstruct ether_addr *mc_pool;\n\tsize_t mc_pool_size;\n\n\t/*\n\t * If a free entry is available at the end of the pool, just\n\t * increment the number of recorded multicast addresses.\n\t */\n\tif ((port->mc_addr_nb % MCAST_POOL_INC) != 0) {\n\t\tport->mc_addr_nb++;\n\t\treturn 0;\n\t}\n\n\t/*\n\t * [re]allocate a pool with MCAST_POOL_INC more entries.\n\t * The previous test guarantees that port->mc_addr_nb is a multiple\n\t * of MCAST_POOL_INC.\n\t */\n\tmc_pool_size = sizeof(struct ether_addr) * (port->mc_addr_nb +\n\t\t\t\t\t\t MCAST_POOL_INC);\n\tmc_pool = (struct ether_addr *) realloc(port->mc_addr_pool,\n\t\t\t\t\t\tmc_pool_size);\n\tif (mc_pool == NULL) {\n\t\tprintf(\"allocation of pool of %u multicast addresses failed\\n\",\n\t\t port->mc_addr_nb + MCAST_POOL_INC);\n\t\treturn -ENOMEM;\n\t}\n\n\tport->mc_addr_pool = mc_pool;\n\tport->mc_addr_nb++;\n\treturn 0;\n\n}\n\nstatic void\nmcast_addr_pool_remove(struct rte_port *port, uint32_t addr_idx)\n{\n\tport->mc_addr_nb--;\n\tif (addr_idx == port->mc_addr_nb) {\n\t\t/* No need to recompact the set of multicast addressses. */\n\t\tif (port->mc_addr_nb == 0) {\n\t\t\t/* free the pool of multicast addresses. */\n\t\t\tfree(port->mc_addr_pool);\n\t\t\tport->mc_addr_pool = NULL;\n\t\t}\n\t\treturn;\n\t}\n\tmemmove(&port->mc_addr_pool[addr_idx],\n\t\t&port->mc_addr_pool[addr_idx + 1],\n\t\tsizeof(struct ether_addr) * (port->mc_addr_nb - addr_idx));\n}\n\nstatic void\neth_port_multicast_addr_list_set(uint8_t port_id)\n{\n\tstruct rte_port *port;\n\tint diag;\n\n\tport = &ports[port_id];\n\tdiag = rte_eth_dev_set_mc_addr_list(port_id, port->mc_addr_pool,\n\t\t\t\t\t port->mc_addr_nb);\n\tif (diag == 0)\n\t\treturn;\n\tprintf(\"rte_eth_dev_set_mc_addr_list(port=%d, nb=%u) failed. diag=%d\\n\",\n\t port->mc_addr_nb, port_id, -diag);\n}\n\nvoid\nmcast_addr_add(uint8_t port_id, struct ether_addr *mc_addr)\n{\n\tstruct rte_port *port;\n\tuint32_t i;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\n\tport = &ports[port_id];\n\n\t/*\n\t * Check that the added multicast MAC address is not already recorded\n\t * in the pool of multicast addresses.\n\t */\n\tfor (i = 0; i < port->mc_addr_nb; i++) {\n\t\tif (is_same_ether_addr(mc_addr, &port->mc_addr_pool[i])) {\n\t\t\tprintf(\"multicast address already filtered by port\\n\");\n\t\t\treturn;\n\t\t}\n\t}\n\n\tif (mcast_addr_pool_extend(port) != 0)\n\t\treturn;\n\tether_addr_copy(mc_addr, &port->mc_addr_pool[i]);\n\teth_port_multicast_addr_list_set(port_id);\n}\n\nvoid\nmcast_addr_remove(uint8_t port_id, struct ether_addr *mc_addr)\n{\n\tstruct rte_port *port;\n\tuint32_t i;\n\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn;\n\n\tport = &ports[port_id];\n\n\t/*\n\t * Search the pool of multicast MAC addresses for the removed address.\n\t */\n\tfor (i = 0; i < port->mc_addr_nb; i++) {\n\t\tif (is_same_ether_addr(mc_addr, &port->mc_addr_pool[i]))\n\t\t\tbreak;\n\t}\n\tif (i == port->mc_addr_nb) {\n\t\tprintf(\"multicast address not filtered by port %d\\n\", port_id);\n\t\treturn;\n\t}\n\n\tmcast_addr_pool_remove(port, i);\n\teth_port_multicast_addr_list_set(port_id);\n}\n" }, { "path": "app/test-pmd/csumonly.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \"testpmd.h\"\n\n#define IP_DEFTTL 64 /* from RFC 1340. */\n#define IP_VERSION 0x40\n#define IP_HDRLEN 0x05 /* default IP header length == five 32-bits words. */\n#define IP_VHL_DEF (IP_VERSION | IP_HDRLEN)\n\n#define GRE_KEY_PRESENT 0x2000\n#define GRE_KEY_LEN 4\n#define GRE_SUPPORTED_FIELDS GRE_KEY_PRESENT\n\n/* We cannot use rte_cpu_to_be_16() on a constant in a switch/case */\n#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n#define _htons(x) ((uint16_t)((((x) & 0x00ffU) << 8) | (((x) & 0xff00U) >> 8)))\n#else\n#define _htons(x) (x)\n#endif\n\n/* structure that caches offload info for the current packet */\nstruct testpmd_offload_info {\n\tuint16_t ethertype;\n\tuint16_t l2_len;\n\tuint16_t l3_len;\n\tuint16_t l4_len;\n\tuint8_t l4_proto;\n\tuint8_t is_tunnel;\n\tuint16_t outer_ethertype;\n\tuint16_t outer_l2_len;\n\tuint16_t outer_l3_len;\n\tuint8_t outer_l4_proto;\n\tuint16_t tso_segsz;\n};\n\n/* simplified GRE header */\nstruct simple_gre_hdr {\n\tuint16_t flags;\n\tuint16_t proto;\n} __attribute__((__packed__));\n\nstatic uint16_t\nget_psd_sum(void *l3_hdr, uint16_t ethertype, uint64_t ol_flags)\n{\n\tif (ethertype == _htons(ETHER_TYPE_IPv4))\n\t\treturn rte_ipv4_phdr_cksum(l3_hdr, ol_flags);\n\telse /* assume ethertype == ETHER_TYPE_IPv6 */\n\t\treturn rte_ipv6_phdr_cksum(l3_hdr, ol_flags);\n}\n\nstatic uint16_t\nget_udptcp_checksum(void *l3_hdr, void *l4_hdr, uint16_t ethertype)\n{\n\tif (ethertype == _htons(ETHER_TYPE_IPv4))\n\t\treturn rte_ipv4_udptcp_cksum(l3_hdr, l4_hdr);\n\telse /* assume ethertype == ETHER_TYPE_IPv6 */\n\t\treturn rte_ipv6_udptcp_cksum(l3_hdr, l4_hdr);\n}\n\n/* Parse an IPv4 header to fill l3_len, l4_len, and l4_proto */\nstatic void\nparse_ipv4(struct ipv4_hdr *ipv4_hdr, struct testpmd_offload_info *info)\n{\n\tstruct tcp_hdr *tcp_hdr;\n\n\tinfo->l3_len = (ipv4_hdr->version_ihl & 0x0f) * 4;\n\tinfo->l4_proto = ipv4_hdr->next_proto_id;\n\n\t/* only fill l4_len for TCP, it's useful for TSO */\n\tif (info->l4_proto == IPPROTO_TCP) {\n\t\ttcp_hdr = (struct tcp_hdr *)((char *)ipv4_hdr + info->l3_len);\n\t\tinfo->l4_len = (tcp_hdr->data_off & 0xf0) >> 2;\n\t} else\n\t\tinfo->l4_len = 0;\n}\n\n/* Parse an IPv6 header to fill l3_len, l4_len, and l4_proto */\nstatic void\nparse_ipv6(struct ipv6_hdr *ipv6_hdr, struct testpmd_offload_info *info)\n{\n\tstruct tcp_hdr *tcp_hdr;\n\n\tinfo->l3_len = sizeof(struct ipv6_hdr);\n\tinfo->l4_proto = ipv6_hdr->proto;\n\n\t/* only fill l4_len for TCP, it's useful for TSO */\n\tif (info->l4_proto == IPPROTO_TCP) {\n\t\ttcp_hdr = (struct tcp_hdr *)((char *)ipv6_hdr + info->l3_len);\n\t\tinfo->l4_len = (tcp_hdr->data_off & 0xf0) >> 2;\n\t} else\n\t\tinfo->l4_len = 0;\n}\n\n/*\n * Parse an ethernet header to fill the ethertype, l2_len, l3_len and\n * ipproto. This function is able to recognize IPv4/IPv6 with one optional vlan\n * header. The l4_len argument is only set in case of TCP (useful for TSO).\n */\nstatic void\nparse_ethernet(struct ether_hdr *eth_hdr, struct testpmd_offload_info *info)\n{\n\tstruct ipv4_hdr *ipv4_hdr;\n\tstruct ipv6_hdr *ipv6_hdr;\n\n\tinfo->l2_len = sizeof(struct ether_hdr);\n\tinfo->ethertype = eth_hdr->ether_type;\n\n\tif (info->ethertype == _htons(ETHER_TYPE_VLAN)) {\n\t\tstruct vlan_hdr *vlan_hdr = (struct vlan_hdr *)(eth_hdr + 1);\n\n\t\tinfo->l2_len += sizeof(struct vlan_hdr);\n\t\tinfo->ethertype = vlan_hdr->eth_proto;\n\t}\n\n\tswitch (info->ethertype) {\n\tcase _htons(ETHER_TYPE_IPv4):\n\t\tipv4_hdr = (struct ipv4_hdr *) ((char *)eth_hdr + info->l2_len);\n\t\tparse_ipv4(ipv4_hdr, info);\n\t\tbreak;\n\tcase _htons(ETHER_TYPE_IPv6):\n\t\tipv6_hdr = (struct ipv6_hdr *) ((char *)eth_hdr + info->l2_len);\n\t\tparse_ipv6(ipv6_hdr, info);\n\t\tbreak;\n\tdefault:\n\t\tinfo->l4_len = 0;\n\t\tinfo->l3_len = 0;\n\t\tinfo->l4_proto = 0;\n\t\tbreak;\n\t}\n}\n\n/* Parse a vxlan header */\nstatic void\n#ifdef RTE_NEXT_ABI\nparse_vxlan(struct udp_hdr *udp_hdr,\n\t struct testpmd_offload_info *info,\n\t uint32_t pkt_type)\n#else\nparse_vxlan(struct udp_hdr *udp_hdr, struct testpmd_offload_info *info,\n\tuint64_t mbuf_olflags)\n#endif\n{\n\tstruct ether_hdr *eth_hdr;\n\n\t/* check udp destination port, 4789 is the default vxlan port\n\t * (rfc7348) or that the rx offload flag is set (i40e only\n\t * currently) */\n\tif (udp_hdr->dst_port != _htons(4789) &&\n#ifdef RTE_NEXT_ABI\n\t\tRTE_ETH_IS_TUNNEL_PKT(pkt_type) == 0)\n#else\n\t\t(mbuf_olflags & (PKT_RX_TUNNEL_IPV4_HDR |\n\t\t\tPKT_RX_TUNNEL_IPV6_HDR)) == 0)\n#endif\n\t\treturn;\n\n\tinfo->is_tunnel = 1;\n\tinfo->outer_ethertype = info->ethertype;\n\tinfo->outer_l2_len = info->l2_len;\n\tinfo->outer_l3_len = info->l3_len;\n\tinfo->outer_l4_proto = info->l4_proto;\n\n\teth_hdr = (struct ether_hdr *)((char *)udp_hdr +\n\t\tsizeof(struct udp_hdr) +\n\t\tsizeof(struct vxlan_hdr));\n\n\tparse_ethernet(eth_hdr, info);\n\tinfo->l2_len += ETHER_VXLAN_HLEN; /* add udp + vxlan */\n}\n\n/* Parse a gre header */\nstatic void\nparse_gre(struct simple_gre_hdr *gre_hdr, struct testpmd_offload_info *info)\n{\n\tstruct ether_hdr *eth_hdr;\n\tstruct ipv4_hdr *ipv4_hdr;\n\tstruct ipv6_hdr *ipv6_hdr;\n\tuint8_t gre_len = 0;\n\n\t/* check which fields are supported */\n\tif ((gre_hdr->flags & _htons(~GRE_SUPPORTED_FIELDS)) != 0)\n\t\treturn;\n\n\tgre_len += sizeof(struct simple_gre_hdr);\n\n\tif (gre_hdr->flags & _htons(GRE_KEY_PRESENT))\n\t\tgre_len += GRE_KEY_LEN;\n\n\tif (gre_hdr->proto == _htons(ETHER_TYPE_IPv4)) {\n\t\tinfo->is_tunnel = 1;\n\t\tinfo->outer_ethertype = info->ethertype;\n\t\tinfo->outer_l2_len = info->l2_len;\n\t\tinfo->outer_l3_len = info->l3_len;\n\t\tinfo->outer_l4_proto = info->l4_proto;\n\n\t\tipv4_hdr = (struct ipv4_hdr *)((char *)gre_hdr + gre_len);\n\n\t\tparse_ipv4(ipv4_hdr, info);\n\t\tinfo->ethertype = _htons(ETHER_TYPE_IPv4);\n\t\tinfo->l2_len = 0;\n\n\t} else if (gre_hdr->proto == _htons(ETHER_TYPE_IPv6)) {\n\t\tinfo->is_tunnel = 1;\n\t\tinfo->outer_ethertype = info->ethertype;\n\t\tinfo->outer_l2_len = info->l2_len;\n\t\tinfo->outer_l3_len = info->l3_len;\n\t\tinfo->outer_l4_proto = info->l4_proto;\n\n\t\tipv6_hdr = (struct ipv6_hdr *)((char *)gre_hdr + gre_len);\n\n\t\tinfo->ethertype = _htons(ETHER_TYPE_IPv6);\n\t\tparse_ipv6(ipv6_hdr, info);\n\t\tinfo->l2_len = 0;\n\n\t} else if (gre_hdr->proto == _htons(ETHER_TYPE_TEB)) {\n\t\tinfo->is_tunnel = 1;\n\t\tinfo->outer_ethertype = info->ethertype;\n\t\tinfo->outer_l2_len = info->l2_len;\n\t\tinfo->outer_l3_len = info->l3_len;\n\t\tinfo->outer_l4_proto = info->l4_proto;\n\n\t\teth_hdr = (struct ether_hdr *)((char *)gre_hdr + gre_len);\n\n\t\tparse_ethernet(eth_hdr, info);\n\t} else\n\t\treturn;\n\n\tinfo->l2_len += gre_len;\n}\n\n\n/* Parse an encapsulated ip or ipv6 header */\nstatic void\nparse_encap_ip(void *encap_ip, struct testpmd_offload_info *info)\n{\n\tstruct ipv4_hdr *ipv4_hdr = encap_ip;\n\tstruct ipv6_hdr *ipv6_hdr = encap_ip;\n\tuint8_t ip_version;\n\n\tip_version = (ipv4_hdr->version_ihl & 0xf0) >> 4;\n\n\tif (ip_version != 4 && ip_version != 6)\n\t\treturn;\n\n\tinfo->is_tunnel = 1;\n\tinfo->outer_ethertype = info->ethertype;\n\tinfo->outer_l2_len = info->l2_len;\n\tinfo->outer_l3_len = info->l3_len;\n\n\tif (ip_version == 4) {\n\t\tparse_ipv4(ipv4_hdr, info);\n\t\tinfo->ethertype = _htons(ETHER_TYPE_IPv4);\n\t} else {\n\t\tparse_ipv6(ipv6_hdr, info);\n\t\tinfo->ethertype = _htons(ETHER_TYPE_IPv6);\n\t}\n\tinfo->l2_len = 0;\n}\n\n/* modify the IPv4 or IPv4 source address of a packet */\nstatic void\nchange_ip_addresses(void *l3_hdr, uint16_t ethertype)\n{\n\tstruct ipv4_hdr *ipv4_hdr = l3_hdr;\n\tstruct ipv6_hdr *ipv6_hdr = l3_hdr;\n\n\tif (ethertype == _htons(ETHER_TYPE_IPv4)) {\n\t\tipv4_hdr->src_addr =\n\t\t\trte_cpu_to_be_32(rte_be_to_cpu_32(ipv4_hdr->src_addr) + 1);\n\t} else if (ethertype == _htons(ETHER_TYPE_IPv6)) {\n\t\tipv6_hdr->src_addr[15] = ipv6_hdr->src_addr[15] + 1;\n\t}\n}\n\n/* if possible, calculate the checksum of a packet in hw or sw,\n * depending on the testpmd command line configuration */\nstatic uint64_t\nprocess_inner_cksums(void *l3_hdr, const struct testpmd_offload_info *info,\n\tuint16_t testpmd_ol_flags)\n{\n\tstruct ipv4_hdr *ipv4_hdr = l3_hdr;\n\tstruct udp_hdr *udp_hdr;\n\tstruct tcp_hdr *tcp_hdr;\n\tstruct sctp_hdr *sctp_hdr;\n\tuint64_t ol_flags = 0;\n\n\tif (info->ethertype == _htons(ETHER_TYPE_IPv4)) {\n\t\tipv4_hdr = l3_hdr;\n\t\tipv4_hdr->hdr_checksum = 0;\n\n\t\tol_flags |= PKT_TX_IPV4;\n\t\tif (info->tso_segsz != 0 && info->l4_proto == IPPROTO_TCP) {\n\t\t\tol_flags |= PKT_TX_IP_CKSUM;\n\t\t} else {\n\t\t\tif (testpmd_ol_flags & TESTPMD_TX_OFFLOAD_IP_CKSUM)\n\t\t\t\tol_flags |= PKT_TX_IP_CKSUM;\n\t\t\telse\n\t\t\t\tipv4_hdr->hdr_checksum =\n\t\t\t\t\trte_ipv4_cksum(ipv4_hdr);\n\t\t}\n\t} else if (info->ethertype == _htons(ETHER_TYPE_IPv6))\n\t\tol_flags |= PKT_TX_IPV6;\n\telse\n\t\treturn 0; /* packet type not supported, nothing to do */\n\n\tif (info->l4_proto == IPPROTO_UDP) {\n\t\tudp_hdr = (struct udp_hdr *)((char *)l3_hdr + info->l3_len);\n\t\t/* do not recalculate udp cksum if it was 0 */\n\t\tif (udp_hdr->dgram_cksum != 0) {\n\t\t\tudp_hdr->dgram_cksum = 0;\n\t\t\tif (testpmd_ol_flags & TESTPMD_TX_OFFLOAD_UDP_CKSUM) {\n\t\t\t\tol_flags |= PKT_TX_UDP_CKSUM;\n\t\t\t\tudp_hdr->dgram_cksum = get_psd_sum(l3_hdr,\n\t\t\t\t\tinfo->ethertype, ol_flags);\n\t\t\t} else {\n\t\t\t\tudp_hdr->dgram_cksum =\n\t\t\t\t\tget_udptcp_checksum(l3_hdr, udp_hdr,\n\t\t\t\t\t\tinfo->ethertype);\n\t\t\t}\n\t\t}\n\t} else if (info->l4_proto == IPPROTO_TCP) {\n\t\ttcp_hdr = (struct tcp_hdr *)((char *)l3_hdr + info->l3_len);\n\t\ttcp_hdr->cksum = 0;\n\t\tif (info->tso_segsz != 0) {\n\t\t\tol_flags |= PKT_TX_TCP_SEG;\n\t\t\ttcp_hdr->cksum = get_psd_sum(l3_hdr, info->ethertype,\n\t\t\t\tol_flags);\n\t\t} else if (testpmd_ol_flags & TESTPMD_TX_OFFLOAD_TCP_CKSUM) {\n\t\t\tol_flags |= PKT_TX_TCP_CKSUM;\n\t\t\ttcp_hdr->cksum = get_psd_sum(l3_hdr, info->ethertype,\n\t\t\t\tol_flags);\n\t\t} else {\n\t\t\ttcp_hdr->cksum =\n\t\t\t\tget_udptcp_checksum(l3_hdr, tcp_hdr,\n\t\t\t\t\tinfo->ethertype);\n\t\t}\n\t} else if (info->l4_proto == IPPROTO_SCTP) {\n\t\tsctp_hdr = (struct sctp_hdr *)((char *)l3_hdr + info->l3_len);\n\t\tsctp_hdr->cksum = 0;\n\t\t/* sctp payload must be a multiple of 4 to be\n\t\t * offloaded */\n\t\tif ((testpmd_ol_flags & TESTPMD_TX_OFFLOAD_SCTP_CKSUM) &&\n\t\t\t((ipv4_hdr->total_length & 0x3) == 0)) {\n\t\t\tol_flags |= PKT_TX_SCTP_CKSUM;\n\t\t} else {\n\t\t\t/* XXX implement CRC32c, example available in\n\t\t\t * RFC3309 */\n\t\t}\n\t}\n\n\treturn ol_flags;\n}\n\n/* Calculate the checksum of outer header (only vxlan is supported,\n * meaning IP + UDP). The caller already checked that it's a vxlan\n * packet */\nstatic uint64_t\nprocess_outer_cksums(void *outer_l3_hdr, struct testpmd_offload_info *info,\n\tuint16_t testpmd_ol_flags)\n{\n\tstruct ipv4_hdr *ipv4_hdr = outer_l3_hdr;\n\tstruct ipv6_hdr *ipv6_hdr = outer_l3_hdr;\n\tstruct udp_hdr *udp_hdr;\n\tuint64_t ol_flags = 0;\n\n\tif (info->outer_ethertype == _htons(ETHER_TYPE_IPv4)) {\n\t\tipv4_hdr->hdr_checksum = 0;\n\t\tol_flags |= PKT_TX_OUTER_IPV4;\n\n\t\tif (testpmd_ol_flags & TESTPMD_TX_OFFLOAD_OUTER_IP_CKSUM)\n\t\t\tol_flags |= PKT_TX_OUTER_IP_CKSUM;\n\t\telse\n\t\t\tipv4_hdr->hdr_checksum = rte_ipv4_cksum(ipv4_hdr);\n\t} else if (testpmd_ol_flags & TESTPMD_TX_OFFLOAD_OUTER_IP_CKSUM)\n\t\tol_flags |= PKT_TX_OUTER_IPV6;\n\n\tif (info->outer_l4_proto != IPPROTO_UDP)\n\t\treturn ol_flags;\n\n\t/* outer UDP checksum is always done in software as we have no\n\t * hardware supporting it today, and no API for it. */\n\n\tudp_hdr = (struct udp_hdr *)((char *)outer_l3_hdr + info->outer_l3_len);\n\t/* do not recalculate udp cksum if it was 0 */\n\tif (udp_hdr->dgram_cksum != 0) {\n\t\tudp_hdr->dgram_cksum = 0;\n\t\tif (info->outer_ethertype == _htons(ETHER_TYPE_IPv4))\n\t\t\tudp_hdr->dgram_cksum =\n\t\t\t\trte_ipv4_udptcp_cksum(ipv4_hdr, udp_hdr);\n\t\telse\n\t\t\tudp_hdr->dgram_cksum =\n\t\t\t\trte_ipv6_udptcp_cksum(ipv6_hdr, udp_hdr);\n\t}\n\n\treturn ol_flags;\n}\n\n/*\n * Receive a burst of packets, and for each packet:\n * - parse packet, and try to recognize a supported packet type (1)\n * - if it's not a supported packet type, don't touch the packet, else:\n * - modify the IPs in inner headers and in outer headers if any\n * - reprocess the checksum of all supported layers. This is done in SW\n * or HW, depending on testpmd command line configuration\n * - if TSO is enabled in testpmd command line, also flag the mbuf for TCP\n * segmentation offload (this implies HW TCP checksum)\n * Then transmit packets on the output port.\n *\n * (1) Supported packets are:\n * Ether / (vlan) / IP|IP6 / UDP|TCP|SCTP .\n * Ether / (vlan) / outer IP|IP6 / outer UDP / VxLAN / Ether / IP|IP6 /\n * UDP|TCP|SCTP\n * Ether / (vlan) / outer IP|IP6 / GRE / Ether / IP|IP6 / UDP|TCP|SCTP\n * Ether / (vlan) / outer IP|IP6 / GRE / IP|IP6 / UDP|TCP|SCTP\n * Ether / (vlan) / outer IP|IP6 / IP|IP6 / UDP|TCP|SCTP\n *\n * The testpmd command line for this forward engine sets the flags\n * TESTPMD_TX_OFFLOAD_* in ports[tx_port].tx_ol_flags. They control\n * wether a checksum must be calculated in software or in hardware. The\n * IP, UDP, TCP and SCTP flags always concern the inner layer. The\n * OUTER_IP is only useful for tunnel packets.\n */\nstatic void\npkt_burst_checksum_forward(struct fwd_stream *fs)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_port *txp;\n\tstruct rte_mbuf *m;\n\tstruct ether_hdr *eth_hdr;\n\tvoid *l3_hdr = NULL, *outer_l3_hdr = NULL; /* can be IPv4 or IPv6 */\n\tuint16_t nb_rx;\n\tuint16_t nb_tx;\n\tuint16_t i;\n\tuint64_t ol_flags;\n\tuint16_t testpmd_ol_flags;\n\tuint32_t rx_bad_ip_csum;\n\tuint32_t rx_bad_l4_csum;\n\tstruct testpmd_offload_info info;\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tuint64_t start_tsc;\n\tuint64_t end_tsc;\n\tuint64_t core_cycles;\n#endif\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tstart_tsc = rte_rdtsc();\n#endif\n\n\t/* receive a burst of packet */\n\tnb_rx = rte_eth_rx_burst(fs->rx_port, fs->rx_queue, pkts_burst,\n\t\t\t\t nb_pkt_per_burst);\n\tif (unlikely(nb_rx == 0))\n\t\treturn;\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->rx_burst_stats.pkt_burst_spread[nb_rx]++;\n#endif\n\tfs->rx_packets += nb_rx;\n\trx_bad_ip_csum = 0;\n\trx_bad_l4_csum = 0;\n\n\ttxp = &ports[fs->tx_port];\n\ttestpmd_ol_flags = txp->tx_ol_flags;\n\tmemset(&info, 0, sizeof(info));\n\tinfo.tso_segsz = txp->tso_segsz;\n\n\tfor (i = 0; i < nb_rx; i++) {\n\n\t\tol_flags = 0;\n\t\tinfo.is_tunnel = 0;\n\t\tm = pkts_burst[i];\n\n\t\t/* Update the L3/L4 checksum error packet statistics */\n\t\trx_bad_ip_csum += ((m->ol_flags & PKT_RX_IP_CKSUM_BAD) != 0);\n\t\trx_bad_l4_csum += ((m->ol_flags & PKT_RX_L4_CKSUM_BAD) != 0);\n\n\t\t/* step 1: dissect packet, parsing optional vlan, ip4/ip6, vxlan\n\t\t * and inner headers */\n\n\t\teth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\t\tparse_ethernet(eth_hdr, &info);\n\t\tl3_hdr = (char *)eth_hdr + info.l2_len;\n\n\t\t/* check if it's a supported tunnel */\n\t\tif (testpmd_ol_flags & TESTPMD_TX_OFFLOAD_PARSE_TUNNEL) {\n\t\t\tif (info.l4_proto == IPPROTO_UDP) {\n\t\t\t\tstruct udp_hdr *udp_hdr;\n\t\t\t\tudp_hdr = (struct udp_hdr *)((char *)l3_hdr +\n\t\t\t\t\tinfo.l3_len);\n#ifdef RTE_NEXT_ABI\n\t\t\t\tparse_vxlan(udp_hdr, &info, m->packet_type);\n#else\n\t\t\t\tparse_vxlan(udp_hdr, &info, m->ol_flags);\n#endif\n\t\t\t} else if (info.l4_proto == IPPROTO_GRE) {\n\t\t\t\tstruct simple_gre_hdr *gre_hdr;\n\t\t\t\tgre_hdr = (struct simple_gre_hdr *)\n\t\t\t\t\t((char *)l3_hdr + info.l3_len);\n\t\t\t\tparse_gre(gre_hdr, &info);\n\t\t\t} else if (info.l4_proto == IPPROTO_IPIP) {\n\t\t\t\tvoid *encap_ip_hdr;\n\t\t\t\tencap_ip_hdr = (char *)l3_hdr + info.l3_len;\n\t\t\t\tparse_encap_ip(encap_ip_hdr, &info);\n\t\t\t}\n\t\t}\n\n\t\t/* update l3_hdr and outer_l3_hdr if a tunnel was parsed */\n\t\tif (info.is_tunnel) {\n\t\t\touter_l3_hdr = l3_hdr;\n\t\t\tl3_hdr = (char *)l3_hdr + info.outer_l3_len + info.l2_len;\n\t\t}\n\n\t\t/* step 2: change all source IPs (v4 or v6) so we need\n\t\t * to recompute the chksums even if they were correct */\n\n\t\tchange_ip_addresses(l3_hdr, info.ethertype);\n\t\tif (info.is_tunnel == 1)\n\t\t\tchange_ip_addresses(outer_l3_hdr, info.outer_ethertype);\n\n\t\t/* step 3: depending on user command line configuration,\n\t\t * recompute checksum either in software or flag the\n\t\t * mbuf to offload the calculation to the NIC. If TSO\n\t\t * is configured, prepare the mbuf for TCP segmentation. */\n\n\t\t/* process checksums of inner headers first */\n\t\tol_flags |= process_inner_cksums(l3_hdr, &info, testpmd_ol_flags);\n\n\t\t/* Then process outer headers if any. Note that the software\n\t\t * checksum will be wrong if one of the inner checksums is\n\t\t * processed in hardware. */\n\t\tif (info.is_tunnel == 1) {\n\t\t\tol_flags |= process_outer_cksums(outer_l3_hdr, &info,\n\t\t\t\ttestpmd_ol_flags);\n\t\t}\n\n\t\t/* step 4: fill the mbuf meta data (flags and header lengths) */\n\n\t\tif (info.is_tunnel == 1) {\n\t\t\tif (testpmd_ol_flags & TESTPMD_TX_OFFLOAD_OUTER_IP_CKSUM) {\n\t\t\t\tm->outer_l2_len = info.outer_l2_len;\n\t\t\t\tm->outer_l3_len = info.outer_l3_len;\n\t\t\t\tm->l2_len = info.l2_len;\n\t\t\t\tm->l3_len = info.l3_len;\n\t\t\t\tm->l4_len = info.l4_len;\n\t\t\t}\n\t\t\telse {\n\t\t\t\t/* if there is a outer UDP cksum\n\t\t\t\t processed in sw and the inner in hw,\n\t\t\t\t the outer checksum will be wrong as\n\t\t\t\t the payload will be modified by the\n\t\t\t\t hardware */\n\t\t\t\tm->l2_len = info.outer_l2_len +\n\t\t\t\t\tinfo.outer_l3_len + info.l2_len;\n\t\t\t\tm->l3_len = info.l3_len;\n\t\t\t\tm->l4_len = info.l4_len;\n\t\t\t}\n\t\t} else {\n\t\t\t/* this is only useful if an offload flag is\n\t\t\t * set, but it does not hurt to fill it in any\n\t\t\t * case */\n\t\t\tm->l2_len = info.l2_len;\n\t\t\tm->l3_len = info.l3_len;\n\t\t\tm->l4_len = info.l4_len;\n\t\t}\n\t\tm->tso_segsz = info.tso_segsz;\n\t\tm->ol_flags = ol_flags;\n\n\t\t/* if verbose mode is enabled, dump debug info */\n\t\tif (verbose_level > 0) {\n\t\t\tstruct {\n\t\t\t\tuint64_t flag;\n\t\t\t\tuint64_t mask;\n\t\t\t} tx_flags[] = {\n\t\t\t\t{ PKT_TX_IP_CKSUM, PKT_TX_IP_CKSUM },\n\t\t\t\t{ PKT_TX_UDP_CKSUM, PKT_TX_L4_MASK },\n\t\t\t\t{ PKT_TX_TCP_CKSUM, PKT_TX_L4_MASK },\n\t\t\t\t{ PKT_TX_SCTP_CKSUM, PKT_TX_L4_MASK },\n\t\t\t\t{ PKT_TX_IPV4, PKT_TX_IPV4 },\n\t\t\t\t{ PKT_TX_IPV6, PKT_TX_IPV6 },\n\t\t\t\t{ PKT_TX_OUTER_IP_CKSUM, PKT_TX_OUTER_IP_CKSUM },\n\t\t\t\t{ PKT_TX_OUTER_IPV4, PKT_TX_OUTER_IPV4 },\n\t\t\t\t{ PKT_TX_OUTER_IPV6, PKT_TX_OUTER_IPV6 },\n\t\t\t\t{ PKT_TX_TCP_SEG, PKT_TX_TCP_SEG },\n\t\t\t};\n\t\t\tunsigned j;\n\t\t\tconst char *name;\n\n\t\t\tprintf(\"-----------------\\n\");\n\t\t\t/* dump rx parsed packet info */\n\t\t\tprintf(\"rx: l2_len=%d ethertype=%x l3_len=%d \"\n\t\t\t\t\"l4_proto=%d l4_len=%d\\n\",\n\t\t\t\tinfo.l2_len, rte_be_to_cpu_16(info.ethertype),\n\t\t\t\tinfo.l3_len, info.l4_proto, info.l4_len);\n\t\t\tif (info.is_tunnel == 1)\n\t\t\t\tprintf(\"rx: outer_l2_len=%d outer_ethertype=%x \"\n\t\t\t\t\t\"outer_l3_len=%d\\n\", info.outer_l2_len,\n\t\t\t\t\trte_be_to_cpu_16(info.outer_ethertype),\n\t\t\t\t\tinfo.outer_l3_len);\n\t\t\t/* dump tx packet info */\n\t\t\tif ((testpmd_ol_flags & (TESTPMD_TX_OFFLOAD_IP_CKSUM |\n\t\t\t\t\t\tTESTPMD_TX_OFFLOAD_UDP_CKSUM |\n\t\t\t\t\t\tTESTPMD_TX_OFFLOAD_TCP_CKSUM |\n\t\t\t\t\t\tTESTPMD_TX_OFFLOAD_SCTP_CKSUM)) ||\n\t\t\t\tinfo.tso_segsz != 0)\n\t\t\t\tprintf(\"tx: m->l2_len=%d m->l3_len=%d \"\n\t\t\t\t\t\"m->l4_len=%d\\n\",\n\t\t\t\t\tm->l2_len, m->l3_len, m->l4_len);\n\t\t\tif ((info.is_tunnel == 1) &&\n\t\t\t\t(testpmd_ol_flags & TESTPMD_TX_OFFLOAD_OUTER_IP_CKSUM))\n\t\t\t\tprintf(\"tx: m->outer_l2_len=%d m->outer_l3_len=%d\\n\",\n\t\t\t\t\tm->outer_l2_len, m->outer_l3_len);\n\t\t\tif (info.tso_segsz != 0)\n\t\t\t\tprintf(\"tx: m->tso_segsz=%d\\n\", m->tso_segsz);\n\t\t\tprintf(\"tx: flags=\");\n\t\t\tfor (j = 0; j < sizeof(tx_flags)/sizeof(*tx_flags); j++) {\n\t\t\t\tname = rte_get_tx_ol_flag_name(tx_flags[j].flag);\n\t\t\t\tif ((m->ol_flags & tx_flags[j].mask) ==\n\t\t\t\t\ttx_flags[j].flag)\n\t\t\t\t\tprintf(\"%s \", name);\n\t\t\t}\n\t\t\tprintf(\"\\n\");\n\t\t}\n\t}\n\tnb_tx = rte_eth_tx_burst(fs->tx_port, fs->tx_queue, pkts_burst, nb_rx);\n\tfs->tx_packets += nb_tx;\n\tfs->rx_bad_ip_csum += rx_bad_ip_csum;\n\tfs->rx_bad_l4_csum += rx_bad_l4_csum;\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->tx_burst_stats.pkt_burst_spread[nb_tx]++;\n#endif\n\tif (unlikely(nb_tx < nb_rx)) {\n\t\tfs->fwd_dropped += (nb_rx - nb_tx);\n\t\tdo {\n\t\t\trte_pktmbuf_free(pkts_burst[nb_tx]);\n\t\t} while (++nb_tx < nb_rx);\n\t}\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tend_tsc = rte_rdtsc();\n\tcore_cycles = (end_tsc - start_tsc);\n\tfs->core_cycles = (uint64_t) (fs->core_cycles + core_cycles);\n#endif\n}\n\nstruct fwd_engine csum_fwd_engine = {\n\t.fwd_mode_name = \"csum\",\n\t.port_fwd_begin = NULL,\n\t.port_fwd_end = NULL,\n\t.packet_fwd = pkt_burst_checksum_forward,\n};\n" }, { "path": "app/test-pmd/flowgen.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2013 Tilera Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Tilera Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"testpmd.h\"\n\n/* hardcoded configuration (for now) */\nstatic unsigned cfg_n_flows\t= 1024;\nstatic unsigned cfg_pkt_size\t= 300;\nstatic uint32_t cfg_ip_src\t= IPv4(10, 254, 0, 0);\nstatic uint32_t cfg_ip_dst\t= IPv4(10, 253, 0, 0);\nstatic uint16_t cfg_udp_src\t= 1000;\nstatic uint16_t cfg_udp_dst\t= 1001;\nstatic struct ether_addr cfg_ether_src\t=\n\t{{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x00 }};\nstatic struct ether_addr cfg_ether_dst\t=\n\t{{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x01 }};\n\n#define IP_DEFTTL 64 /* from RFC 1340. */\n#define IP_VERSION 0x40\n#define IP_HDRLEN 0x05 /* default IP header length == five 32-bits words. */\n#define IP_VHL_DEF (IP_VERSION | IP_HDRLEN)\n\nstatic inline struct rte_mbuf *\ntx_mbuf_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\n\tm = __rte_mbuf_raw_alloc(mp);\n\t__rte_mbuf_sanity_check_raw(m, 0);\n\treturn (m);\n}\n\n\nstatic inline uint16_t\nip_sum(const unaligned_uint16_t *hdr, int hdr_len)\n{\n\tuint32_t sum = 0;\n\n\twhile (hdr_len > 1)\n\t{\n\t\tsum += *hdr++;\n\t\tif (sum & 0x80000000)\n\t\t\tsum = (sum & 0xFFFF) + (sum >> 16);\n\t\thdr_len -= 2;\n\t}\n\n\twhile (sum >> 16)\n\t\tsum = (sum & 0xFFFF) + (sum >> 16);\n\n\treturn ~sum;\n}\n\n/*\n * Multi-flow generation mode.\n *\n * We originate a bunch of flows (varying destination IP addresses), and\n * terminate receive traffic. Received traffic is simply discarded, but we\n * still do so in order to maintain traffic statistics.\n */\nstatic void\npkt_burst_flow_gen(struct fwd_stream *fs)\n{\n\tunsigned pkt_size = cfg_pkt_size - 4;\t/* Adjust FCS */\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_mempool *mbp;\n\tstruct rte_mbuf *pkt;\n\tstruct ether_hdr *eth_hdr;\n\tstruct ipv4_hdr *ip_hdr;\n\tstruct udp_hdr *udp_hdr;\n\tuint16_t vlan_tci, vlan_tci_outer;\n\tuint16_t ol_flags;\n\tuint16_t nb_rx;\n\tuint16_t nb_tx;\n\tuint16_t nb_pkt;\n\tuint16_t i;\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tuint64_t start_tsc;\n\tuint64_t end_tsc;\n\tuint64_t core_cycles;\n#endif\n\tstatic int next_flow = 0;\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tstart_tsc = rte_rdtsc();\n#endif\n\n\t/* Receive a burst of packets and discard them. */\n\tnb_rx = rte_eth_rx_burst(fs->rx_port, fs->rx_queue, pkts_burst,\n\t\t\t\t nb_pkt_per_burst);\n\tfs->rx_packets += nb_rx;\n\n\tfor (i = 0; i < nb_rx; i++)\n\t\trte_pktmbuf_free(pkts_burst[i]);\n\n\tmbp = current_fwd_lcore()->mbp;\n\tvlan_tci = ports[fs->tx_port].tx_vlan_id;\n\tvlan_tci_outer = ports[fs->tx_port].tx_vlan_id_outer;\n\tol_flags = ports[fs->tx_port].tx_ol_flags;\n\n\tfor (nb_pkt = 0; nb_pkt < nb_pkt_per_burst; nb_pkt++) {\n\t\tpkt = tx_mbuf_alloc(mbp);\n\t\tif (!pkt)\n\t\t\tbreak;\n\n\t\tpkt->data_len = pkt_size;\n\t\tpkt->next = NULL;\n\n\t\t/* Initialize Ethernet header. */\n\t\teth_hdr = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\t\tether_addr_copy(&cfg_ether_dst, ð_hdr->d_addr);\n\t\tether_addr_copy(&cfg_ether_src, ð_hdr->s_addr);\n\t\teth_hdr->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);\n\n\t\t/* Initialize IP header. */\n\t\tip_hdr = (struct ipv4_hdr *)(eth_hdr + 1);\n\t\tmemset(ip_hdr, 0, sizeof(*ip_hdr));\n\t\tip_hdr->version_ihl\t= IP_VHL_DEF;\n\t\tip_hdr->type_of_service\t= 0;\n\t\tip_hdr->fragment_offset\t= 0;\n\t\tip_hdr->time_to_live\t= IP_DEFTTL;\n\t\tip_hdr->next_proto_id\t= IPPROTO_UDP;\n\t\tip_hdr->packet_id\t= 0;\n\t\tip_hdr->src_addr\t= rte_cpu_to_be_32(cfg_ip_src);\n\t\tip_hdr->dst_addr\t= rte_cpu_to_be_32(cfg_ip_dst +\n\t\t\t\t\t\t\t next_flow);\n\t\tip_hdr->total_length\t= RTE_CPU_TO_BE_16(pkt_size -\n\t\t\t\t\t\t\t sizeof(*eth_hdr));\n\t\tip_hdr->hdr_checksum\t= ip_sum((unaligned_uint16_t *)ip_hdr,\n\t\t\t\t\t\t sizeof(*ip_hdr));\n\n\t\t/* Initialize UDP header. */\n\t\tudp_hdr = (struct udp_hdr *)(ip_hdr + 1);\n\t\tudp_hdr->src_port\t= rte_cpu_to_be_16(cfg_udp_src);\n\t\tudp_hdr->dst_port\t= rte_cpu_to_be_16(cfg_udp_dst);\n\t\tudp_hdr->dgram_cksum\t= 0; /* No UDP checksum. */\n\t\tudp_hdr->dgram_len\t= RTE_CPU_TO_BE_16(pkt_size -\n\t\t\t\t\t\t\t sizeof(*eth_hdr) -\n\t\t\t\t\t\t\t sizeof(*ip_hdr));\n\t\tpkt->nb_segs\t\t= 1;\n\t\tpkt->pkt_len\t\t= pkt_size;\n\t\tpkt->ol_flags\t\t= ol_flags;\n\t\tpkt->vlan_tci\t\t= vlan_tci;\n\t\tpkt->vlan_tci_outer\t= vlan_tci_outer;\n\t\tpkt->l2_len\t\t= sizeof(struct ether_hdr);\n\t\tpkt->l3_len\t\t= sizeof(struct ipv4_hdr);\n\t\tpkts_burst[nb_pkt]\t= pkt;\n\n\t\tnext_flow = (next_flow + 1) % cfg_n_flows;\n\t}\n\n\tnb_tx = rte_eth_tx_burst(fs->tx_port, fs->tx_queue, pkts_burst, nb_pkt);\n\tfs->tx_packets += nb_tx;\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->tx_burst_stats.pkt_burst_spread[nb_tx]++;\n#endif\n\tif (unlikely(nb_tx < nb_pkt)) {\n\t\t/* Back out the flow counter. */\n\t\tnext_flow -= (nb_pkt - nb_tx);\n\t\twhile (next_flow < 0)\n\t\t\tnext_flow += cfg_n_flows;\n\n\t\tdo {\n\t\t\trte_pktmbuf_free(pkts_burst[nb_tx]);\n\t\t} while (++nb_tx < nb_pkt);\n\t}\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tend_tsc = rte_rdtsc();\n\tcore_cycles = (end_tsc - start_tsc);\n\tfs->core_cycles = (uint64_t) (fs->core_cycles + core_cycles);\n#endif\n}\n\nstruct fwd_engine flow_gen_engine = {\n\t.fwd_mode_name = \"flowgen\",\n\t.port_fwd_begin = NULL,\n\t.port_fwd_end = NULL,\n\t.packet_fwd = pkt_burst_flow_gen,\n};\n" }, { "path": "app/test-pmd/icmpecho.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2013 6WIND\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"testpmd.h\"\n\nstatic const char *\narp_op_name(uint16_t arp_op)\n{\n\tswitch (arp_op ) {\n\tcase ARP_OP_REQUEST:\n\t\treturn \"ARP Request\";\n\tcase ARP_OP_REPLY:\n\t\treturn \"ARP Reply\";\n\tcase ARP_OP_REVREQUEST:\n\t\treturn \"Reverse ARP Request\";\n\tcase ARP_OP_REVREPLY:\n\t\treturn \"Reverse ARP Reply\";\n\tcase ARP_OP_INVREQUEST:\n\t\treturn \"Peer Identify Request\";\n\tcase ARP_OP_INVREPLY:\n\t\treturn \"Peer Identify Reply\";\n\tdefault:\n\t\tbreak;\n\t}\n\treturn \"Unkwown ARP op\";\n}\n\nstatic const char *\nip_proto_name(uint16_t ip_proto)\n{\n\tstatic const char * ip_proto_names[] = {\n\t\t\"IP6HOPOPTS\", /**< IP6 hop-by-hop options */\n\t\t\"ICMP\", /**< control message protocol */\n\t\t\"IGMP\", /**< group mgmt protocol */\n\t\t\"GGP\", /**< gateway^2 (deprecated) */\n\t\t\"IPv4\", /**< IPv4 encapsulation */\n\n\t\t\"UNASSIGNED\",\n\t\t\"TCP\", /**< transport control protocol */\n\t\t\"ST\", /**< Stream protocol II */\n\t\t\"EGP\", /**< exterior gateway protocol */\n\t\t\"PIGP\", /**< private interior gateway */\n\n\t\t\"RCC_MON\", /**< BBN RCC Monitoring */\n\t\t\"NVPII\", /**< network voice protocol*/\n\t\t\"PUP\", /**< pup */\n\t\t\"ARGUS\", /**< Argus */\n\t\t\"EMCON\", /**< EMCON */\n\n\t\t\"XNET\", /**< Cross Net Debugger */\n\t\t\"CHAOS\", /**< Chaos*/\n\t\t\"UDP\", /**< user datagram protocol */\n\t\t\"MUX\", /**< Multiplexing */\n\t\t\"DCN_MEAS\", /**< DCN Measurement Subsystems */\n\n\t\t\"HMP\", /**< Host Monitoring */\n\t\t\"PRM\", /**< Packet Radio Measurement */\n\t\t\"XNS_IDP\", /**< xns idp */\n\t\t\"TRUNK1\", /**< Trunk-1 */\n\t\t\"TRUNK2\", /**< Trunk-2 */\n\n\t\t\"LEAF1\", /**< Leaf-1 */\n\t\t\"LEAF2\", /**< Leaf-2 */\n\t\t\"RDP\", /**< Reliable Data */\n\t\t\"IRTP\", /**< Reliable Transaction */\n\t\t\"TP4\", /**< tp-4 w/ class negotiation */\n\n\t\t\"BLT\", /**< Bulk Data Transfer */\n\t\t\"NSP\", /**< Network Services */\n\t\t\"INP\", /**< Merit Internodal */\n\t\t\"SEP\", /**< Sequential Exchange */\n\t\t\"3PC\", /**< Third Party Connect */\n\n\t\t\"IDPR\", /**< InterDomain Policy Routing */\n\t\t\"XTP\", /**< XTP */\n\t\t\"DDP\", /**< Datagram Delivery */\n\t\t\"CMTP\", /**< Control Message Transport */\n\t\t\"TPXX\", /**< TP++ Transport */\n\n\t\t\"ILTP\", /**< IL transport protocol */\n\t\t\"IPv6_HDR\", /**< IP6 header */\n\t\t\"SDRP\", /**< Source Demand Routing */\n\t\t\"IPv6_RTG\", /**< IP6 routing header */\n\t\t\"IPv6_FRAG\", /**< IP6 fragmentation header */\n\n\t\t\"IDRP\", /**< InterDomain Routing*/\n\t\t\"RSVP\", /**< resource reservation */\n\t\t\"GRE\", /**< General Routing Encap. */\n\t\t\"MHRP\", /**< Mobile Host Routing */\n\t\t\"BHA\", /**< BHA */\n\n\t\t\"ESP\", /**< IP6 Encap Sec. Payload */\n\t\t\"AH\", /**< IP6 Auth Header */\n\t\t\"INLSP\", /**< Integ. Net Layer Security */\n\t\t\"SWIPE\", /**< IP with encryption */\n\t\t\"NHRP\", /**< Next Hop Resolution */\n\n\t\t\"UNASSIGNED\",\n\t\t\"UNASSIGNED\",\n\t\t\"UNASSIGNED\",\n\t\t\"ICMPv6\", /**< ICMP6 */\n\t\t\"IPv6NONEXT\", /**< IP6 no next header */\n\n\t\t\"Ipv6DSTOPTS\",/**< IP6 destination option */\n\t\t\"AHIP\", /**< any host internal protocol */\n\t\t\"CFTP\", /**< CFTP */\n\t\t\"HELLO\", /**< \"hello\" routing protocol */\n\t\t\"SATEXPAK\", /**< SATNET/Backroom EXPAK */\n\n\t\t\"KRYPTOLAN\", /**< Kryptolan */\n\t\t\"RVD\", /**< Remote Virtual Disk */\n\t\t\"IPPC\", /**< Pluribus Packet Core */\n\t\t\"ADFS\", /**< Any distributed FS */\n\t\t\"SATMON\", /**< Satnet Monitoring */\n\n\t\t\"VISA\", /**< VISA Protocol */\n\t\t\"IPCV\", /**< Packet Core Utility */\n\t\t\"CPNX\", /**< Comp. Prot. Net. Executive */\n\t\t\"CPHB\", /**< Comp. Prot. HeartBeat */\n\t\t\"WSN\", /**< Wang Span Network */\n\n\t\t\"PVP\", /**< Packet Video Protocol */\n\t\t\"BRSATMON\", /**< BackRoom SATNET Monitoring */\n\t\t\"ND\", /**< Sun net disk proto (temp.) */\n\t\t\"WBMON\", /**< WIDEBAND Monitoring */\n\t\t\"WBEXPAK\", /**< WIDEBAND EXPAK */\n\n\t\t\"EON\", /**< ISO cnlp */\n\t\t\"VMTP\", /**< VMTP */\n\t\t\"SVMTP\", /**< Secure VMTP */\n\t\t\"VINES\", /**< Banyon VINES */\n\t\t\"TTP\", /**< TTP */\n\n\t\t\"IGP\", /**< NSFNET-IGP */\n\t\t\"DGP\", /**< dissimilar gateway prot. */\n\t\t\"TCF\", /**< TCF */\n\t\t\"IGRP\", /**< Cisco/GXS IGRP */\n\t\t\"OSPFIGP\", /**< OSPFIGP */\n\n\t\t\"SRPC\", /**< Strite RPC protocol */\n\t\t\"LARP\", /**< Locus Address Resoloution */\n\t\t\"MTP\", /**< Multicast Transport */\n\t\t\"AX25\", /**< AX.25 Frames */\n\t\t\"4IN4\", /**< IP encapsulated in IP */\n\n\t\t\"MICP\", /**< Mobile Int.ing control */\n\t\t\"SCCSP\", /**< Semaphore Comm. security */\n\t\t\"ETHERIP\", /**< Ethernet IP encapsulation */\n\t\t\"ENCAP\", /**< encapsulation header */\n\t\t\"AES\", /**< any private encr. scheme */\n\n\t\t\"GMTP\", /**< GMTP */\n\t\t\"IPCOMP\", /**< payload compression (IPComp) */\n\t\t\"UNASSIGNED\",\n\t\t\"UNASSIGNED\",\n\t\t\"PIM\", /**< Protocol Independent Mcast */\n\t};\n\n\tif (ip_proto < sizeof(ip_proto_names) / sizeof(ip_proto_names[0]))\n\t\treturn ip_proto_names[ip_proto];\n\tswitch (ip_proto) {\n#ifdef IPPROTO_PGM\n\tcase IPPROTO_PGM: /**< PGM */\n\t\treturn \"PGM\";\n#endif\n\tcase IPPROTO_SCTP: /**< Stream Control Transport Protocol */\n\t\treturn \"SCTP\";\n#ifdef IPPROTO_DIVERT\n\tcase IPPROTO_DIVERT: /**< divert pseudo-protocol */\n\t\treturn \"DIVERT\";\n#endif\n\tcase IPPROTO_RAW: /**< raw IP packet */\n\t\treturn \"RAW\";\n\tdefault:\n\t\tbreak;\n\t}\n\treturn \"UNASSIGNED\";\n}\n\nstatic void\nipv4_addr_to_dot(uint32_t be_ipv4_addr, char *buf)\n{\n\tuint32_t ipv4_addr;\n\n\tipv4_addr = rte_be_to_cpu_32(be_ipv4_addr);\n\tsprintf(buf, \"%d.%d.%d.%d\", (ipv4_addr >> 24) & 0xFF,\n\t\t(ipv4_addr >> 16) & 0xFF, (ipv4_addr >> 8) & 0xFF,\n\t\tipv4_addr & 0xFF);\n}\n\nstatic void\nether_addr_dump(const char *what, const struct ether_addr *ea)\n{\n\tchar buf[ETHER_ADDR_FMT_SIZE];\n\n\tether_format_addr(buf, ETHER_ADDR_FMT_SIZE, ea);\n\tif (what)\n\t\tprintf(\"%s\", what);\n\tprintf(\"%s\", buf);\n}\n\nstatic void\nipv4_addr_dump(const char *what, uint32_t be_ipv4_addr)\n{\n\tchar buf[16];\n\n\tipv4_addr_to_dot(be_ipv4_addr, buf);\n\tif (what)\n\t\tprintf(\"%s\", what);\n\tprintf(\"%s\", buf);\n}\n\nstatic uint16_t\nipv4_hdr_cksum(struct ipv4_hdr *ip_h)\n{\n\tuint16_t *v16_h;\n\tuint32_t ip_cksum;\n\n\t/*\n\t * Compute the sum of successive 16-bit words of the IPv4 header,\n\t * skipping the checksum field of the header.\n\t */\n\tv16_h = (unaligned_uint16_t *) ip_h;\n\tip_cksum = v16_h[0] + v16_h[1] + v16_h[2] + v16_h[3] +\n\t\tv16_h[4] + v16_h[6] + v16_h[7] + v16_h[8] + v16_h[9];\n\n\t/* reduce 32 bit checksum to 16 bits and complement it */\n\tip_cksum = (ip_cksum & 0xffff) + (ip_cksum >> 16);\n\tip_cksum = (ip_cksum & 0xffff) + (ip_cksum >> 16);\n\tip_cksum = (~ip_cksum) & 0x0000FFFF;\n\treturn (ip_cksum == 0) ? 0xFFFF : (uint16_t) ip_cksum;\n}\n\n#define is_multicast_ipv4_addr(ipv4_addr) \\\n\t(((rte_be_to_cpu_32((ipv4_addr)) >> 24) & 0x000000FF) == 0xE0)\n\n/*\n * Receive a burst of packets, lookup for ICMP echo requets, and, if any,\n * send back ICMP echo replies.\n */\nstatic void\nreply_to_icmp_echo_rqsts(struct fwd_stream *fs)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_mbuf *pkt;\n\tstruct ether_hdr *eth_h;\n\tstruct vlan_hdr *vlan_h;\n\tstruct arp_hdr *arp_h;\n\tstruct ipv4_hdr *ip_h;\n\tstruct icmp_hdr *icmp_h;\n\tstruct ether_addr eth_addr;\n\tuint32_t ip_addr;\n\tuint16_t nb_rx;\n\tuint16_t nb_tx;\n\tuint16_t nb_replies;\n\tuint16_t eth_type;\n\tuint16_t vlan_id;\n\tuint16_t arp_op;\n\tuint16_t arp_pro;\n\tuint32_t cksum;\n\tuint8_t i;\n\tint l2_len;\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tuint64_t start_tsc;\n\tuint64_t end_tsc;\n\tuint64_t core_cycles;\n#endif\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tstart_tsc = rte_rdtsc();\n#endif\n\n\t/*\n\t * First, receive a burst of packets.\n\t */\n\tnb_rx = rte_eth_rx_burst(fs->rx_port, fs->rx_queue, pkts_burst,\n\t\t\t\t nb_pkt_per_burst);\n\tif (unlikely(nb_rx == 0))\n\t\treturn;\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->rx_burst_stats.pkt_burst_spread[nb_rx]++;\n#endif\n\tfs->rx_packets += nb_rx;\n\tnb_replies = 0;\n\tfor (i = 0; i < nb_rx; i++) {\n\t\tpkt = pkts_burst[i];\n\t\teth_h = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\t\teth_type = RTE_BE_TO_CPU_16(eth_h->ether_type);\n\t\tl2_len = sizeof(struct ether_hdr);\n\t\tif (verbose_level > 0) {\n\t\t\tprintf(\"\\nPort %d pkt-len=%u nb-segs=%u\\n\",\n\t\t\t fs->rx_port, pkt->pkt_len, pkt->nb_segs);\n\t\t\tether_addr_dump(\" ETH: src=\", ð_h->s_addr);\n\t\t\tether_addr_dump(\" dst=\", ð_h->d_addr);\n\t\t}\n\t\tif (eth_type == ETHER_TYPE_VLAN) {\n\t\t\tvlan_h = (struct vlan_hdr *)\n\t\t\t\t((char *)eth_h + sizeof(struct ether_hdr));\n\t\t\tl2_len += sizeof(struct vlan_hdr);\n\t\t\teth_type = rte_be_to_cpu_16(vlan_h->eth_proto);\n\t\t\tif (verbose_level > 0) {\n\t\t\t\tvlan_id = rte_be_to_cpu_16(vlan_h->vlan_tci)\n\t\t\t\t\t& 0xFFF;\n\t\t\t\tprintf(\" [vlan id=%u]\", vlan_id);\n\t\t\t}\n\t\t}\n\t\tif (verbose_level > 0) {\n\t\t\tprintf(\" type=0x%04x\\n\", eth_type);\n\t\t}\n\n\t\t/* Reply to ARP requests */\n\t\tif (eth_type == ETHER_TYPE_ARP) {\n\t\t\tarp_h = (struct arp_hdr *) ((char *)eth_h + l2_len);\n\t\t\tarp_op = RTE_BE_TO_CPU_16(arp_h->arp_op);\n\t\t\tarp_pro = RTE_BE_TO_CPU_16(arp_h->arp_pro);\n\t\t\tif (verbose_level > 0) {\n\t\t\t\tprintf(\" ARP: hrd=%d proto=0x%04x hln=%d \"\n\t\t\t\t \"pln=%d op=%u (%s)\\n\",\n\t\t\t\t RTE_BE_TO_CPU_16(arp_h->arp_hrd),\n\t\t\t\t arp_pro, arp_h->arp_hln,\n\t\t\t\t arp_h->arp_pln, arp_op,\n\t\t\t\t arp_op_name(arp_op));\n\t\t\t}\n\t\t\tif ((RTE_BE_TO_CPU_16(arp_h->arp_hrd) !=\n\t\t\t ARP_HRD_ETHER) ||\n\t\t\t (arp_pro != ETHER_TYPE_IPv4) ||\n\t\t\t (arp_h->arp_hln != 6) ||\n\t\t\t (arp_h->arp_pln != 4)\n\t\t\t ) {\n\t\t\t\trte_pktmbuf_free(pkt);\n\t\t\t\tif (verbose_level > 0)\n\t\t\t\t\tprintf(\"\\n\");\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (verbose_level > 0) {\n\t\t\t\tether_addr_copy(&arp_h->arp_data.arp_sha, ð_addr);\n\t\t\t\tether_addr_dump(\" sha=\", ð_addr);\n\t\t\t\tip_addr = arp_h->arp_data.arp_sip;\n\t\t\t\tipv4_addr_dump(\" sip=\", ip_addr);\n\t\t\t\tprintf(\"\\n\");\n\t\t\t\tether_addr_copy(&arp_h->arp_data.arp_tha, ð_addr);\n\t\t\t\tether_addr_dump(\" tha=\", ð_addr);\n\t\t\t\tip_addr = arp_h->arp_data.arp_tip;\n\t\t\t\tipv4_addr_dump(\" tip=\", ip_addr);\n\t\t\t\tprintf(\"\\n\");\n\t\t\t}\n\t\t\tif (arp_op != ARP_OP_REQUEST) {\n\t\t\t\trte_pktmbuf_free(pkt);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Build ARP reply.\n\t\t\t */\n\n\t\t\t/* Use source MAC address as destination MAC address. */\n\t\t\tether_addr_copy(ð_h->s_addr, ð_h->d_addr);\n\t\t\t/* Set source MAC address with MAC address of TX port */\n\t\t\tether_addr_copy(&ports[fs->tx_port].eth_addr,\n\t\t\t\t\tð_h->s_addr);\n\n\t\t\tarp_h->arp_op = rte_cpu_to_be_16(ARP_OP_REPLY);\n\t\t\tether_addr_copy(&arp_h->arp_data.arp_tha, ð_addr);\n\t\t\tether_addr_copy(&arp_h->arp_data.arp_sha, &arp_h->arp_data.arp_tha);\n\t\t\tether_addr_copy(ð_h->s_addr, &arp_h->arp_data.arp_sha);\n\n\t\t\t/* Swap IP addresses in ARP payload */\n\t\t\tip_addr = arp_h->arp_data.arp_sip;\n\t\t\tarp_h->arp_data.arp_sip = arp_h->arp_data.arp_tip;\n\t\t\tarp_h->arp_data.arp_tip = ip_addr;\n\t\t\tpkts_burst[nb_replies++] = pkt;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (eth_type != ETHER_TYPE_IPv4) {\n\t\t\trte_pktmbuf_free(pkt);\n\t\t\tcontinue;\n\t\t}\n\t\tip_h = (struct ipv4_hdr *) ((char *)eth_h + l2_len);\n\t\tif (verbose_level > 0) {\n\t\t\tipv4_addr_dump(\" IPV4: src=\", ip_h->src_addr);\n\t\t\tipv4_addr_dump(\" dst=\", ip_h->dst_addr);\n\t\t\tprintf(\" proto=%d (%s)\\n\",\n\t\t\t ip_h->next_proto_id,\n\t\t\t ip_proto_name(ip_h->next_proto_id));\n\t\t}\n\n\t\t/*\n\t\t * Check if packet is a ICMP echo request.\n\t\t */\n\t\ticmp_h = (struct icmp_hdr *) ((char *)ip_h +\n\t\t\t\t\t sizeof(struct ipv4_hdr));\n\t\tif (! ((ip_h->next_proto_id == IPPROTO_ICMP) &&\n\t\t (icmp_h->icmp_type == IP_ICMP_ECHO_REQUEST) &&\n\t\t (icmp_h->icmp_code == 0))) {\n\t\t\trte_pktmbuf_free(pkt);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (verbose_level > 0)\n\t\t\tprintf(\" ICMP: echo request seq id=%d\\n\",\n\t\t\t rte_be_to_cpu_16(icmp_h->icmp_seq_nb));\n\n\t\t/*\n\t\t * Prepare ICMP echo reply to be sent back.\n\t\t * - switch ethernet source and destinations addresses,\n\t\t * - use the request IP source address as the reply IP\n\t\t * destination address,\n\t\t * - if the request IP destination address is a multicast\n\t\t * address:\n\t\t * - choose a reply IP source address different from the\n\t\t * request IP source address,\n\t\t * - re-compute the IP header checksum.\n\t\t * Otherwise:\n\t\t * - switch the request IP source and destination\n\t\t * addresses in the reply IP header,\n\t\t * - keep the IP header checksum unchanged.\n\t\t * - set IP_ICMP_ECHO_REPLY in ICMP header.\n\t\t * ICMP checksum is computed by assuming it is valid in the\n\t\t * echo request and not verified.\n\t\t */\n\t\tether_addr_copy(ð_h->s_addr, ð_addr);\n\t\tether_addr_copy(ð_h->d_addr, ð_h->s_addr);\n\t\tether_addr_copy(ð_addr, ð_h->d_addr);\n\t\tip_addr = ip_h->src_addr;\n\t\tif (is_multicast_ipv4_addr(ip_h->dst_addr)) {\n\t\t\tuint32_t ip_src;\n\n\t\t\tip_src = rte_be_to_cpu_32(ip_addr);\n\t\t\tif ((ip_src & 0x00000003) == 1)\n\t\t\t\tip_src = (ip_src & 0xFFFFFFFC) | 0x00000002;\n\t\t\telse\n\t\t\t\tip_src = (ip_src & 0xFFFFFFFC) | 0x00000001;\n\t\t\tip_h->src_addr = rte_cpu_to_be_32(ip_src);\n\t\t\tip_h->dst_addr = ip_addr;\n\t\t\tip_h->hdr_checksum = ipv4_hdr_cksum(ip_h);\n\t\t} else {\n\t\t\tip_h->src_addr = ip_h->dst_addr;\n\t\t\tip_h->dst_addr = ip_addr;\n\t\t}\n\t\ticmp_h->icmp_type = IP_ICMP_ECHO_REPLY;\n\t\tcksum = ~icmp_h->icmp_cksum & 0xffff;\n\t\tcksum += ~htons(IP_ICMP_ECHO_REQUEST << 8) & 0xffff;\n\t\tcksum += htons(IP_ICMP_ECHO_REPLY << 8);\n\t\tcksum = (cksum & 0xffff) + (cksum >> 16);\n\t\tcksum = (cksum & 0xffff) + (cksum >> 16);\n\t\ticmp_h->icmp_cksum = ~cksum;\n\t\tpkts_burst[nb_replies++] = pkt;\n\t}\n\n\t/* Send back ICMP echo replies, if any. */\n\tif (nb_replies > 0) {\n\t\tnb_tx = rte_eth_tx_burst(fs->tx_port, fs->tx_queue, pkts_burst,\n\t\t\t\t\t nb_replies);\n\t\tfs->tx_packets += nb_tx;\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\t\tfs->tx_burst_stats.pkt_burst_spread[nb_tx]++;\n#endif\n\t\tif (unlikely(nb_tx < nb_replies)) {\n\t\t\tfs->fwd_dropped += (nb_replies - nb_tx);\n\t\t\tdo {\n\t\t\t\trte_pktmbuf_free(pkts_burst[nb_tx]);\n\t\t\t} while (++nb_tx < nb_replies);\n\t\t}\n\t}\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tend_tsc = rte_rdtsc();\n\tcore_cycles = (end_tsc - start_tsc);\n\tfs->core_cycles = (uint64_t) (fs->core_cycles + core_cycles);\n#endif\n}\n\nstruct fwd_engine icmp_echo_engine = {\n\t.fwd_mode_name = \"icmpecho\",\n\t.port_fwd_begin = NULL,\n\t.port_fwd_end = NULL,\n\t.packet_fwd = reply_to_icmp_echo_rqsts,\n};\n" }, { "path": "app/test-pmd/ieee1588fwd.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n\n#include \n#include \n\n#include \"testpmd.h\"\n\n/**\n * The structure of a PTP V2 packet.\n *\n * Only the minimum fields used by the ieee1588 test are represented.\n */\nstruct ptpv2_msg {\n\tuint8_t msg_id;\n\tuint8_t version; /**< must be 0x02 */\n\tuint8_t unused[34];\n};\n\n#define PTP_SYNC_MESSAGE 0x0\n#define PTP_DELAY_REQ_MESSAGE 0x1\n#define PTP_PATH_DELAY_REQ_MESSAGE 0x2\n#define PTP_PATH_DELAY_RESP_MESSAGE 0x3\n#define PTP_FOLLOWUP_MESSAGE 0x8\n#define PTP_DELAY_RESP_MESSAGE 0x9\n#define PTP_PATH_DELAY_FOLLOWUP_MESSAGE 0xA\n#define PTP_ANNOUNCE_MESSAGE 0xB\n#define PTP_SIGNALLING_MESSAGE 0xC\n#define PTP_MANAGEMENT_MESSAGE 0xD\n\n/*\n * Forwarding of IEEE1588 Precise Time Protocol (PTP) packets.\n *\n * In this mode, packets are received one by one and are expected to be\n * PTP V2 L2 Ethernet frames (with the specific Ethernet type \"0x88F7\")\n * containing PTP \"sync\" messages (version 2 at offset 1, and message ID\n * 0 at offset 0).\n *\n * Check that each received packet is a IEEE1588 PTP V2 packet of type\n * PTP_SYNC_MESSAGE, and that it has been identified and timestamped\n * by the hardware.\n * Check that the value of the last RX timestamp recorded by the controller\n * is greater than the previous one.\n *\n * If everything is OK, send the received packet back on the same port,\n * requesting for it to be timestamped by the hardware.\n * Check that the value of the last TX timestamp recorded by the controller\n * is greater than the previous one.\n */\n\nstatic void\nport_ieee1588_rx_timestamp_check(portid_t pi, uint32_t index)\n{\n\tstruct timespec timestamp = {0, 0};\n\n\tif (rte_eth_timesync_read_rx_timestamp(pi, ×tamp, index) < 0) {\n\t\tprintf(\"Port %u RX timestamp registers not valid\\n\",\n\t\t (unsigned) pi);\n\t\treturn;\n\t}\n\tprintf(\"Port %u RX timestamp value %lu\\n\",\n\t (unsigned) pi, timestamp.tv_sec);\n}\n\n#define MAX_TX_TMST_WAIT_MICROSECS 1000 /**< 1 milli-second */\n\nstatic void\nport_ieee1588_tx_timestamp_check(portid_t pi)\n{\n\tstruct timespec timestamp = {0, 0};\n\tunsigned wait_us = 0;\n\n\twhile ((rte_eth_timesync_read_tx_timestamp(pi, ×tamp) < 0) &&\n\t (wait_us < MAX_TX_TMST_WAIT_MICROSECS)) {\n\t\trte_delay_us(1);\n\t\twait_us++;\n\t}\n\tif (wait_us >= MAX_TX_TMST_WAIT_MICROSECS) {\n\t\tprintf(\"Port %u TX timestamp registers not valid after \"\n\t\t \"%u micro-seconds\\n\",\n\t\t (unsigned) pi, (unsigned) MAX_TX_TMST_WAIT_MICROSECS);\n\t\treturn;\n\t}\n\tprintf(\"Port %u TX timestamp value %lu validated after \"\n\t \"%u micro-second%s\\n\",\n\t (unsigned) pi, timestamp.tv_sec, wait_us,\n\t (wait_us == 1) ? \"\" : \"s\");\n}\n\nstatic void\nieee1588_packet_fwd(struct fwd_stream *fs)\n{\n\tstruct rte_mbuf *mb;\n\tstruct ether_hdr *eth_hdr;\n\tstruct ptpv2_msg *ptp_hdr;\n\tuint16_t eth_type;\n\tuint32_t timesync_index;\n\n\t/*\n\t * Receive 1 packet at a time.\n\t */\n\tif (rte_eth_rx_burst(fs->rx_port, fs->rx_queue, &mb, 1) == 0)\n\t\treturn;\n\n\tfs->rx_packets += 1;\n\n\t/*\n\t * Check that the received packet is a PTP packet that was detected\n\t * by the hardware.\n\t */\n\teth_hdr = rte_pktmbuf_mtod(mb, struct ether_hdr *);\n\teth_type = rte_be_to_cpu_16(eth_hdr->ether_type);\n\n\tif (! (mb->ol_flags & PKT_RX_IEEE1588_PTP)) {\n\t\tif (eth_type == ETHER_TYPE_1588) {\n\t\t\tprintf(\"Port %u Received PTP packet not filtered\"\n\t\t\t \" by hardware\\n\",\n\t\t\t (unsigned) fs->rx_port);\n\t\t} else {\n\t\t\tprintf(\"Port %u Received non PTP packet type=0x%4x \"\n\t\t\t \"len=%u\\n\",\n\t\t\t (unsigned) fs->rx_port, eth_type,\n\t\t\t (unsigned) mb->pkt_len);\n\t\t}\n\t\trte_pktmbuf_free(mb);\n\t\treturn;\n\t}\n\tif (eth_type != ETHER_TYPE_1588) {\n\t\tprintf(\"Port %u Received NON PTP packet incorrectly\"\n\t\t \" detected by hardware\\n\",\n\t\t (unsigned) fs->rx_port);\n\t\trte_pktmbuf_free(mb);\n\t\treturn;\n\t}\n\n\t/*\n\t * Check that the received PTP packet is a PTP V2 packet of type\n\t * PTP_SYNC_MESSAGE.\n\t */\n\tptp_hdr = (struct ptpv2_msg *) (rte_pktmbuf_mtod(mb, char *) +\n\t\t\t\t\tsizeof(struct ether_hdr));\n\tif (ptp_hdr->version != 0x02) {\n\t\tprintf(\"Port %u Received PTP V2 Ethernet frame with wrong PTP\"\n\t\t \" protocol version 0x%x (should be 0x02)\\n\",\n\t\t (unsigned) fs->rx_port, ptp_hdr->version);\n\t\trte_pktmbuf_free(mb);\n\t\treturn;\n\t}\n\tif (ptp_hdr->msg_id != PTP_SYNC_MESSAGE) {\n\t\tprintf(\"Port %u Received PTP V2 Ethernet frame with unexpected\"\n\t\t \" message ID 0x%x (expected 0x0 - PTP_SYNC_MESSAGE)\\n\",\n\t\t (unsigned) fs->rx_port, ptp_hdr->msg_id);\n\t\trte_pktmbuf_free(mb);\n\t\treturn;\n\t}\n\tprintf(\"Port %u IEEE1588 PTP V2 SYNC Message filtered by hardware\\n\",\n\t (unsigned) fs->rx_port);\n\n\t/*\n\t * Check that the received PTP packet has been timestamped by the\n\t * hardware.\n\t */\n\tif (! (mb->ol_flags & PKT_RX_IEEE1588_TMST)) {\n\t\tprintf(\"Port %u Received PTP packet not timestamped\"\n\t\t \" by hardware\\n\",\n\t\t (unsigned) fs->rx_port);\n\t\trte_pktmbuf_free(mb);\n\t\treturn;\n\t}\n\n\t/* For i40e we need the timesync register index. It is ignored for the\n\t * other PMDs. */\n\ttimesync_index = mb->timesync & 0x3;\n\t/* Read and check the RX timestamp. */\n\tport_ieee1588_rx_timestamp_check(fs->rx_port, timesync_index);\n\n\t/* Forward PTP packet with hardware TX timestamp */\n\tmb->ol_flags |= PKT_TX_IEEE1588_TMST;\n\tfs->tx_packets += 1;\n\tif (rte_eth_tx_burst(fs->rx_port, fs->tx_queue, &mb, 1) == 0) {\n\t\tprintf(\"Port %u sent PTP packet dropped\\n\",\n\t\t (unsigned) fs->rx_port);\n\t\tfs->fwd_dropped += 1;\n\t\trte_pktmbuf_free(mb);\n\t\treturn;\n\t}\n\n\t/*\n\t * Check the TX timestamp.\n\t */\n\tport_ieee1588_tx_timestamp_check(fs->rx_port);\n}\n\nstatic void\nport_ieee1588_fwd_begin(portid_t pi)\n{\n\trte_eth_timesync_enable(pi);\n}\n\nstatic void\nport_ieee1588_fwd_end(portid_t pi)\n{\n\trte_eth_timesync_disable(pi);\n}\n\nstruct fwd_engine ieee1588_fwd_engine = {\n\t.fwd_mode_name = \"ieee1588\",\n\t.port_fwd_begin = port_ieee1588_fwd_begin,\n\t.port_fwd_end = port_ieee1588_fwd_end,\n\t.packet_fwd = ieee1588_packet_fwd,\n};\n" }, { "path": "app/test-pmd/iofwd.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"testpmd.h\"\n\n/*\n * Forwarding of packets in I/O mode.\n * Forward packets \"as-is\".\n * This is the fastest possible forwarding operation, as it does not access\n * to packets data.\n */\nstatic void\npkt_burst_io_forward(struct fwd_stream *fs)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tuint16_t nb_rx;\n\tuint16_t nb_tx;\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tuint64_t start_tsc;\n\tuint64_t end_tsc;\n\tuint64_t core_cycles;\n#endif\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tstart_tsc = rte_rdtsc();\n#endif\n\n\t/*\n\t * Receive a burst of packets and forward them.\n\t */\n\tnb_rx = rte_eth_rx_burst(fs->rx_port, fs->rx_queue, pkts_burst,\n\t\t\t\t nb_pkt_per_burst);\n\tif (unlikely(nb_rx == 0))\n\t\treturn;\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->rx_burst_stats.pkt_burst_spread[nb_rx]++;\n#endif\n\tfs->rx_packets += nb_rx;\n\tnb_tx = rte_eth_tx_burst(fs->tx_port, fs->tx_queue, pkts_burst, nb_rx);\n\tfs->tx_packets += nb_tx;\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->tx_burst_stats.pkt_burst_spread[nb_tx]++;\n#endif\n\tif (unlikely(nb_tx < nb_rx)) {\n\t\tfs->fwd_dropped += (nb_rx - nb_tx);\n\t\tdo {\n\t\t\trte_pktmbuf_free(pkts_burst[nb_tx]);\n\t\t} while (++nb_tx < nb_rx);\n\t}\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tend_tsc = rte_rdtsc();\n\tcore_cycles = (end_tsc - start_tsc);\n\tfs->core_cycles = (uint64_t) (fs->core_cycles + core_cycles);\n#endif\n}\n\nstruct fwd_engine io_fwd_engine = {\n\t.fwd_mode_name = \"io\",\n\t.port_fwd_begin = NULL,\n\t.port_fwd_end = NULL,\n\t.packet_fwd = pkt_burst_io_forward,\n};\n" }, { "path": "app/test-pmd/macfwd-retry.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"testpmd.h\"\n\n#define BURST_TX_WAIT_US 10\n#define BURST_TX_RETRIES 5\n\n/*\n * Global variables that control number of retires and\n * timeout (in us) between retires.\n */\nuint32_t burst_tx_delay_time = BURST_TX_WAIT_US;\nuint32_t burst_tx_retry_num = BURST_TX_RETRIES;\n\n/*\n * Forwarding of packets in MAC mode with a wait and retry on TX to reduce packet loss.\n * Change the source and the destination Ethernet addressed of packets\n * before forwarding them.\n */\nstatic void\npkt_burst_mac_retry_forward(struct fwd_stream *fs)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_mbuf *mb;\n\tstruct ether_hdr *eth_hdr;\n\tuint32_t retry;\n\tuint16_t nb_rx;\n\tuint16_t nb_tx;\n\tuint16_t i;\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tuint64_t start_tsc;\n\tuint64_t end_tsc;\n\tuint64_t core_cycles;\n#endif\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tstart_tsc = rte_rdtsc();\n#endif\n\n\t/*\n\t * Receive a burst of packets and forward them.\n\t */\n\tnb_rx = rte_eth_rx_burst(fs->rx_port, fs->rx_queue, pkts_burst,\n\t\t\t\t nb_pkt_per_burst);\n\tif (unlikely(nb_rx == 0))\n\t\treturn;\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->rx_burst_stats.pkt_burst_spread[nb_rx]++;\n#endif\n\tfs->rx_packets += nb_rx;\n\tfor (i = 0; i < nb_rx; i++) {\n\t\tmb = pkts_burst[i];\n\t\teth_hdr = rte_pktmbuf_mtod(mb, struct ether_hdr *);\n\t\tether_addr_copy(&peer_eth_addrs[fs->peer_addr],\n\t\t\t\tð_hdr->d_addr);\n\t\tether_addr_copy(&ports[fs->tx_port].eth_addr,\n\t\t\t\tð_hdr->s_addr);\n\t}\n\tnb_tx = rte_eth_tx_burst(fs->tx_port, fs->tx_queue, pkts_burst, nb_rx);\n\n\t/*\n\t * If not all packets have been TX'd then wait and retry.\n\t */\n\tif (unlikely(nb_tx < nb_rx)) {\n\t\tfor (retry = 0; retry < burst_tx_retry_num; retry++) {\n\t\t\trte_delay_us(burst_tx_delay_time);\n\t\t\tnb_tx += rte_eth_tx_burst(fs->tx_port, fs->tx_queue,\n\t\t\t\t&pkts_burst[nb_tx], nb_rx - nb_tx);\n\t\t\tif (nb_tx == nb_rx)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\tfs->tx_packets += nb_tx;\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->tx_burst_stats.pkt_burst_spread[nb_tx]++;\n#endif\n\tif (unlikely(nb_tx < nb_rx)) {\n\t\tfs->fwd_dropped += (nb_rx - nb_tx);\n\t\tdo {\n\t\t\trte_pktmbuf_free(pkts_burst[nb_tx]);\n\t\t} while (++nb_tx < nb_rx);\n\t}\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tend_tsc = rte_rdtsc();\n\tcore_cycles = (end_tsc - start_tsc);\n\tfs->core_cycles = (uint64_t) (fs->core_cycles + core_cycles);\n#endif\n}\n\nstruct fwd_engine mac_retry_fwd_engine = {\n\t.fwd_mode_name = \"mac_retry\",\n\t.port_fwd_begin = NULL,\n\t.port_fwd_end = NULL,\n\t.packet_fwd = pkt_burst_mac_retry_forward,\n};\n" }, { "path": "app/test-pmd/macfwd.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"testpmd.h\"\n\n/*\n * Forwarding of packets in MAC mode.\n * Change the source and the destination Ethernet addressed of packets\n * before forwarding them.\n */\nstatic void\npkt_burst_mac_forward(struct fwd_stream *fs)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_port *txp;\n\tstruct rte_mbuf *mb;\n\tstruct ether_hdr *eth_hdr;\n\tuint16_t nb_rx;\n\tuint16_t nb_tx;\n\tuint16_t i;\n\tuint64_t ol_flags = 0;\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tuint64_t start_tsc;\n\tuint64_t end_tsc;\n\tuint64_t core_cycles;\n#endif\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tstart_tsc = rte_rdtsc();\n#endif\n\n\t/*\n\t * Receive a burst of packets and forward them.\n\t */\n\tnb_rx = rte_eth_rx_burst(fs->rx_port, fs->rx_queue, pkts_burst,\n\t\t\t\t nb_pkt_per_burst);\n\tif (unlikely(nb_rx == 0))\n\t\treturn;\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->rx_burst_stats.pkt_burst_spread[nb_rx]++;\n#endif\n\tfs->rx_packets += nb_rx;\n\ttxp = &ports[fs->tx_port];\n\tif (txp->tx_ol_flags & TESTPMD_TX_OFFLOAD_INSERT_VLAN)\n\t\tol_flags = PKT_TX_VLAN_PKT;\n\tif (txp->tx_ol_flags & TESTPMD_TX_OFFLOAD_INSERT_QINQ)\n\t\tol_flags |= PKT_TX_QINQ_PKT;\n\tfor (i = 0; i < nb_rx; i++) {\n\t\tmb = pkts_burst[i];\n\t\teth_hdr = rte_pktmbuf_mtod(mb, struct ether_hdr *);\n\t\tether_addr_copy(&peer_eth_addrs[fs->peer_addr],\n\t\t\t\tð_hdr->d_addr);\n\t\tether_addr_copy(&ports[fs->tx_port].eth_addr,\n\t\t\t\tð_hdr->s_addr);\n\t\tmb->ol_flags = ol_flags;\n\t\tmb->l2_len = sizeof(struct ether_hdr);\n\t\tmb->l3_len = sizeof(struct ipv4_hdr);\n\t\tmb->vlan_tci = txp->tx_vlan_id;\n\t\tmb->vlan_tci_outer = txp->tx_vlan_id_outer;\n\t}\n\tnb_tx = rte_eth_tx_burst(fs->tx_port, fs->tx_queue, pkts_burst, nb_rx);\n\tfs->tx_packets += nb_tx;\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->tx_burst_stats.pkt_burst_spread[nb_tx]++;\n#endif\n\tif (unlikely(nb_tx < nb_rx)) {\n\t\tfs->fwd_dropped += (nb_rx - nb_tx);\n\t\tdo {\n\t\t\trte_pktmbuf_free(pkts_burst[nb_tx]);\n\t\t} while (++nb_tx < nb_rx);\n\t}\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tend_tsc = rte_rdtsc();\n\tcore_cycles = (end_tsc - start_tsc);\n\tfs->core_cycles = (uint64_t) (fs->core_cycles + core_cycles);\n#endif\n}\n\nstruct fwd_engine mac_fwd_engine = {\n\t.fwd_mode_name = \"mac\",\n\t.port_fwd_begin = NULL,\n\t.port_fwd_end = NULL,\n\t.packet_fwd = pkt_burst_mac_forward,\n};\n" }, { "path": "app/test-pmd/macswap.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014 Tilera Corporation. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Tilera Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"testpmd.h\"\n\n/*\n * MAC swap forwarding mode: Swap the source and the destination Ethernet\n * addresses of packets before forwarding them.\n */\nstatic void\npkt_burst_mac_swap(struct fwd_stream *fs)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_port *txp;\n\tstruct rte_mbuf *mb;\n\tstruct ether_hdr *eth_hdr;\n\tstruct ether_addr addr;\n\tuint16_t nb_rx;\n\tuint16_t nb_tx;\n\tuint16_t i;\n\tuint64_t ol_flags = 0;\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tuint64_t start_tsc;\n\tuint64_t end_tsc;\n\tuint64_t core_cycles;\n#endif\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tstart_tsc = rte_rdtsc();\n#endif\n\n\t/*\n\t * Receive a burst of packets and forward them.\n\t */\n\tnb_rx = rte_eth_rx_burst(fs->rx_port, fs->rx_queue, pkts_burst,\n\t\t\t\t nb_pkt_per_burst);\n\tif (unlikely(nb_rx == 0))\n\t\treturn;\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->rx_burst_stats.pkt_burst_spread[nb_rx]++;\n#endif\n\tfs->rx_packets += nb_rx;\n\ttxp = &ports[fs->tx_port];\n\tif (txp->tx_ol_flags & TESTPMD_TX_OFFLOAD_INSERT_VLAN)\n\t\tol_flags = PKT_TX_VLAN_PKT;\n\tif (txp->tx_ol_flags & TESTPMD_TX_OFFLOAD_INSERT_QINQ)\n\t\tol_flags |= PKT_TX_QINQ_PKT;\n\tfor (i = 0; i < nb_rx; i++) {\n\t\tmb = pkts_burst[i];\n\t\teth_hdr = rte_pktmbuf_mtod(mb, struct ether_hdr *);\n\n\t\t/* Swap dest and src mac addresses. */\n\t\tether_addr_copy(ð_hdr->d_addr, &addr);\n\t\tether_addr_copy(ð_hdr->s_addr, ð_hdr->d_addr);\n\t\tether_addr_copy(&addr, ð_hdr->s_addr);\n\n\t\tmb->ol_flags = ol_flags;\n\t\tmb->l2_len = sizeof(struct ether_hdr);\n\t\tmb->l3_len = sizeof(struct ipv4_hdr);\n\t\tmb->vlan_tci = txp->tx_vlan_id;\n\t\tmb->vlan_tci_outer = txp->tx_vlan_id_outer;\n\t}\n\tnb_tx = rte_eth_tx_burst(fs->tx_port, fs->tx_queue, pkts_burst, nb_rx);\n\tfs->tx_packets += nb_tx;\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->tx_burst_stats.pkt_burst_spread[nb_tx]++;\n#endif\n\tif (unlikely(nb_tx < nb_rx)) {\n\t\tfs->fwd_dropped += (nb_rx - nb_tx);\n\t\tdo {\n\t\t\trte_pktmbuf_free(pkts_burst[nb_tx]);\n\t\t} while (++nb_tx < nb_rx);\n\t}\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tend_tsc = rte_rdtsc();\n\tcore_cycles = (end_tsc - start_tsc);\n\tfs->core_cycles = (uint64_t) (fs->core_cycles + core_cycles);\n#endif\n}\n\nstruct fwd_engine mac_swap_engine = {\n\t.fwd_mode_name = \"macswap\",\n\t.port_fwd_begin = NULL,\n\t.port_fwd_end = NULL,\n\t.packet_fwd = pkt_burst_mac_swap,\n};\n" }, { "path": "app/test-pmd/mempool_anon.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \"mempool_osdep.h\"\n#include \n\n#ifdef RTE_EXEC_ENV_LINUXAPP\n\n#include \n#include \n#include \n\n\n#define\tPAGEMAP_FNAME\t\t\"/proc/self/pagemap\"\n\n/*\n * the pfn (page frame number) are bits 0-54 (see pagemap.txt in linux\n * Documentation).\n */\n#define\tPAGEMAP_PFN_BITS\t54\n#define\tPAGEMAP_PFN_MASK\tRTE_LEN2MASK(PAGEMAP_PFN_BITS, phys_addr_t)\n\n\nstatic int\nget_phys_map(void *va, phys_addr_t pa[], uint32_t pg_num, uint32_t pg_sz)\n{\n\tint32_t fd, rc;\n\tuint32_t i, nb;\n\toff_t ofs;\n\n\tofs = (uintptr_t)va / pg_sz * sizeof(*pa);\n\tnb = pg_num * sizeof(*pa);\n\n\tif ((fd = open(PAGEMAP_FNAME, O_RDONLY)) < 0)\n\t\treturn (ENOENT);\n\n\tif ((rc = pread(fd, pa, nb, ofs)) < 0 || (rc -= nb) != 0) {\n\n\t\tRTE_LOG(ERR, USER1, \"failed read of %u bytes from \\'%s\\' \"\n\t\t\t\"at offset %zu, error code: %d\\n\",\n\t\t\tnb, PAGEMAP_FNAME, (size_t)ofs, errno);\n\t\trc = ENOENT;\n\t}\n\n\tclose(fd);\n\n\tfor (i = 0; i != pg_num; i++)\n\t\tpa[i] = (pa[i] & PAGEMAP_PFN_MASK) * pg_sz;\n\n\treturn (rc);\n}\n\nstruct rte_mempool *\nmempool_anon_create(const char *name, unsigned elt_num, unsigned elt_size,\n\t\t unsigned cache_size, unsigned private_data_size,\n\t\t rte_mempool_ctor_t *mp_init, void *mp_init_arg,\n\t\t rte_mempool_obj_ctor_t *obj_init, void *obj_init_arg,\n\t\t int socket_id, unsigned flags)\n{\n\tstruct rte_mempool *mp;\n\tphys_addr_t *pa;\n\tchar *va, *uv;\n\tuint32_t n, pg_num, pg_shift, pg_sz, total_size;\n\tsize_t sz;\n\tssize_t usz;\n\tint32_t rc;\n\n\trc = ENOMEM;\n\tmp = NULL;\n\n\tpg_sz = getpagesize();\n\tif (rte_is_power_of_2(pg_sz) == 0) {\n\t\trte_errno = EINVAL;\n\t\treturn (mp);\n\t}\n\n\tpg_shift = rte_bsf32(pg_sz);\n\n\ttotal_size = rte_mempool_calc_obj_size(elt_size, flags, NULL);\n\n\t/* calc max memory size and max number of pages needed. */\n\tsz = rte_mempool_xmem_size(elt_num, total_size, pg_shift);\n\tpg_num = sz >> pg_shift;\n\n\t/* get chunk of virtually continuos memory.*/\n\tif ((va = mmap(NULL, sz, PROT_READ | PROT_WRITE,\n\t\t\tMAP_SHARED | MAP_ANONYMOUS | MAP_LOCKED,\n\t\t\t-1, 0)) == MAP_FAILED) {\n\t\tRTE_LOG(ERR, USER1, \"%s(%s) failed mmap of %zu bytes, \"\n\t\t\t\"error code: %d\\n\",\n\t\t\t__func__, name, sz, errno);\n\t\trte_errno = rc;\n\t\treturn (mp);\n\t}\n\n\t/* extract physical mappings of the allocated memory. */\n\tif ((pa = calloc(pg_num, sizeof (*pa))) != NULL &&\n\t\t\t(rc = get_phys_map(va, pa, pg_num, pg_sz)) == 0) {\n\n\t\t/*\n\t\t * Check that allocated size is big enough to hold elt_num\n\t\t * objects and a calcualte how many bytes are actually required.\n\t\t */\n\n\t\tif ((usz = rte_mempool_xmem_usage(va, elt_num, total_size, pa,\n\t\t\t\tpg_num, pg_shift)) < 0) {\n\n\t\t\tn = -usz;\n\t\t\trc = ENOENT;\n\t\t\tRTE_LOG(ERR, USER1, \"%s(%s) only %u objects from %u \"\n\t\t\t\t\"requested can be created over \"\n\t\t\t\t\"mmaped region %p of %zu bytes\\n\",\n\t\t\t\t__func__, name, n, elt_num, va, sz);\n\t\t} else {\n\n\t\t\t/* unmap unused pages if any */\n\t\t\tif ((size_t)usz < sz) {\n\n\t\t\t\tuv = va + usz;\n\t\t\t\tusz = sz - usz;\n\n\t\t\t\tRTE_LOG(INFO, USER1,\n\t\t\t\t\t\"%s(%s): unmap unused %zu of %zu \"\n\t\t\t\t\t\"mmaped bytes @%p\\n\",\n\t\t\t\t\t__func__, name, (size_t)usz, sz, uv);\n\t\t\t\tmunmap(uv, usz);\n\t\t\t\tsz -= usz;\n\t\t\t\tpg_num = sz >> pg_shift;\n\t\t\t}\n\n\t\t\tif ((mp = rte_mempool_xmem_create(name, elt_num,\n\t\t\t\t\telt_size, cache_size, private_data_size,\n\t\t\t\t\tmp_init, mp_init_arg,\n\t\t\t\t\tobj_init, obj_init_arg,\n\t\t\t\t\tsocket_id, flags, va, pa, pg_num,\n\t\t\t\t\tpg_shift)) != NULL)\n\n\t\t\t\tRTE_VERIFY(elt_num == mp->size);\n\t\t}\n\t}\n\n\tif (mp == NULL) {\n\t\tmunmap(va, sz);\n\t\trte_errno = rc;\n\t}\n\n\tfree(pa);\n\treturn (mp);\n}\n\n#else /* RTE_EXEC_ENV_LINUXAPP */\n\n\nstruct rte_mempool *\nmempool_anon_create(__rte_unused const char *name,\n\t__rte_unused unsigned elt_num, __rte_unused unsigned elt_size,\n\t__rte_unused unsigned cache_size,\n\t__rte_unused unsigned private_data_size,\n\t__rte_unused rte_mempool_ctor_t *mp_init,\n\t__rte_unused void *mp_init_arg,\n\t__rte_unused rte_mempool_obj_ctor_t *obj_init,\n\t__rte_unused void *obj_init_arg,\n\t__rte_unused int socket_id, __rte_unused unsigned flags)\n{\n\trte_errno = ENOTSUP;\n\treturn (NULL);\n}\n\n#endif /* RTE_EXEC_ENV_LINUXAPP */\n" }, { "path": "app/test-pmd/mempool_osdep.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _MEMPOOL_OSDEP_H_\n#define _MEMPOOL_OSDEP_H_\n\n#include \n\n/**\n * @file\n * mempool OS specific header.\n */\n\n/*\n * Create mempool over objects from mmap(..., MAP_ANONYMOUS, ...).\n */\nstruct rte_mempool *\nmempool_anon_create(const char *name, unsigned n, unsigned elt_size,\n\tunsigned cache_size, unsigned private_data_size,\n\trte_mempool_ctor_t *mp_init, void *mp_init_arg,\n\trte_mempool_obj_ctor_t *obj_init, void *obj_init_arg,\n\tint socket_id, unsigned flags);\n\n#endif /*_RTE_MEMPOOL_OSDEP_H_ */\n" }, { "path": "app/test-pmd/parameters.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#ifdef RTE_LIBRTE_CMDLINE\n#include \n#include \n#endif\n#ifdef RTE_LIBRTE_PMD_BOND\n#include \n#endif\n\n#include \"testpmd.h\"\n\nstatic void\nusage(char* progname)\n{\n\tprintf(\"usage: %s \"\n#ifdef RTE_LIBRTE_CMDLINE\n\t \"[--interactive|-i] \"\n#endif\n\t \"[--help|-h] | [--auto-start|-a] | [\"\n\t \"--coremask=COREMASK --portmask=PORTMASK --numa \"\n\t \"--mbuf-size= | --total-num-mbufs= | \"\n\t \"--nb-cores= | --nb-ports= | \"\n#ifdef RTE_LIBRTE_CMDLINE\n\t \"--eth-peers-configfile= | \"\n\t \"--eth-peer=X,M:M:M:M:M:M | \"\n#endif\n\t \"--pkt-filter-mode= |\"\n\t \"--rss-ip | --rss-udp | \"\n\t \"--rxpt= | --rxht= | --rxwt= | --rxfreet= | \"\n\t \"--txpt= | --txht= | --txwt= | --txfreet= | \"\n\t \"--txrst= | --txqflags= ]\\n\",\n\t progname);\n#ifdef RTE_LIBRTE_CMDLINE\n\tprintf(\" --interactive: run in interactive mode.\\n\");\n#endif\n\tprintf(\" --auto-start: start forwarding on init \"\n\t \"[always when non-interactive].\\n\");\n\tprintf(\" --help: display this message and quit.\\n\");\n\tprintf(\" --nb-cores=N: set the number of forwarding cores \"\n\t \"(1 <= N <= %d).\\n\", nb_lcores);\n\tprintf(\" --nb-ports=N: set the number of forwarding ports \"\n\t \"(1 <= N <= %d).\\n\", nb_ports);\n\tprintf(\" --coremask=COREMASK: hexadecimal bitmask of cores running \"\n\t \"the packet forwarding test. The master lcore is reserved for \"\n\t \"command line parsing only, and cannot be masked on for \"\n\t \"packet forwarding.\\n\");\n\tprintf(\" --portmask=PORTMASK: hexadecimal bitmask of ports used \"\n\t \"by the packet forwarding test.\\n\");\n\tprintf(\" --numa: enable NUMA-aware allocation of RX/TX rings and of \"\n\t \"RX memory buffers (mbufs).\\n\");\n\tprintf(\" --port-numa-config=(port,socket)[,(port,socket)]: \"\n\t \"specify the socket on which the memory pool \"\n\t \"used by the port will be allocated.\\n\");\n\tprintf(\" --ring-numa-config=(port,flag,socket)[,(port,flag,socket)]: \"\n\t \"specify the socket on which the TX/RX rings for \"\n\t \"the port will be allocated \"\n\t \"(flag: 1 for RX; 2 for TX; 3 for RX and TX).\\n\");\n\tprintf(\" --socket-num=N: set socket from which all memory is allocated \"\n\t \"in NUMA mode.\\n\");\n\tprintf(\" --mbuf-size=N: set the data size of mbuf to N bytes.\\n\");\n\tprintf(\" --total-num-mbufs=N: set the number of mbufs to be allocated \"\n\t \"in mbuf pools.\\n\");\n\tprintf(\" --max-pkt-len=N: set the maximum size of packet to N bytes.\\n\");\n#ifdef RTE_LIBRTE_CMDLINE\n\tprintf(\" --eth-peers-configfile=name: config file with ethernet addresses \"\n\t \"of peer ports.\\n\");\n\tprintf(\" --eth-peer=X,M:M:M:M:M:M: set the MAC address of the X peer \"\n\t \"port (0 <= X < %d).\\n\", RTE_MAX_ETHPORTS);\n#endif\n\tprintf(\" --pkt-filter-mode=N: set Flow Director mode \"\n\t \"(N: none (default mode) or signature or perfect).\\n\");\n\tprintf(\" --pkt-filter-report-hash=N: set Flow Director report mode \"\n\t \"(N: none or match (default) or always).\\n\");\n\tprintf(\" --pkt-filter-size=N: set Flow Director mode \"\n\t \"(N: 64K (default mode) or 128K or 256K).\\n\");\n\tprintf(\" --pkt-filter-drop-queue=N: set drop-queue. \"\n\t \"In perfect mode, when you add a rule with queue = -1 \"\n\t \"the packet will be enqueued into the rx drop-queue. \"\n\t \"If the drop-queue doesn't exist, the packet is dropped. \"\n\t \"By default drop-queue=127.\\n\");\n\tprintf(\" --crc-strip: enable CRC stripping by hardware.\\n\");\n\tprintf(\" --enable-rx-cksum: enable rx hardware checksum offload.\\n\");\n\tprintf(\" --disable-hw-vlan: disable hardware vlan.\\n\");\n\tprintf(\" --disable-hw-vlan-filter: disable hardware vlan filter.\\n\");\n\tprintf(\" --disable-hw-vlan-strip: disable hardware vlan strip.\\n\");\n\tprintf(\" --disable-hw-vlan-extend: disable hardware vlan extend.\\n\");\n\tprintf(\" --enable-drop-en: enable per queue packet drop.\\n\");\n\tprintf(\" --disable-rss: disable rss.\\n\");\n\tprintf(\" --port-topology=N: set port topology (N: paired (default) or \"\n\t \"chained).\\n\");\n\tprintf(\" --forward-mode=N: set forwarding mode (N: %s).\\n\",\n\t list_pkt_forwarding_modes());\n\tprintf(\" --rss-ip: set RSS functions to IPv4/IPv6 only .\\n\");\n\tprintf(\" --rss-udp: set RSS functions to IPv4/IPv6 + UDP.\\n\");\n\tprintf(\" --rxq=N: set the number of RX queues per port to N.\\n\");\n\tprintf(\" --rxd=N: set the number of descriptors in RX rings to N.\\n\");\n\tprintf(\" --txq=N: set the number of TX queues per port to N.\\n\");\n\tprintf(\" --txd=N: set the number of descriptors in TX rings to N.\\n\");\n\tprintf(\" --burst=N: set the number of packets per burst to N.\\n\");\n\tprintf(\" --mbcache=N: set the cache of mbuf memory pool to N.\\n\");\n\tprintf(\" --rxpt=N: set prefetch threshold register of RX rings to N.\\n\");\n\tprintf(\" --rxht=N: set the host threshold register of RX rings to N.\\n\");\n\tprintf(\" --rxfreet=N: set the free threshold of RX descriptors to N \"\n\t \"(0 <= N < value of rxd).\\n\");\n\tprintf(\" --rxwt=N: set the write-back threshold register of RX rings to N.\\n\");\n\tprintf(\" --txpt=N: set the prefetch threshold register of TX rings to N.\\n\");\n\tprintf(\" --txht=N: set the nhost threshold register of TX rings to N.\\n\");\n\tprintf(\" --txwt=N: set the write-back threshold register of TX rings to N.\\n\");\n\tprintf(\" --txfreet=N: set the transmit free threshold of TX rings to N \"\n\t \"(0 <= N <= value of txd).\\n\");\n\tprintf(\" --txrst=N: set the transmit RS bit threshold of TX rings to N \"\n\t \"(0 <= N <= value of txd).\\n\");\n\tprintf(\" --txqflags=0xXXXXXXXX: hexadecimal bitmask of TX queue flags \"\n\t \"(0 <= N <= 0x7FFFFFFF).\\n\");\n\tprintf(\" --tx-queue-stats-mapping=(port,queue,mapping)[,(port,queue,mapping]: \"\n\t \"tx queues statistics counters mapping \"\n\t \"(0 <= mapping <= %d).\\n\", RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);\n\tprintf(\" --rx-queue-stats-mapping=(port,queue,mapping)[,(port,queue,mapping]: \"\n\t \"rx queues statistics counters mapping \"\n\t \"(0 <= mapping <= %d).\\n\", RTE_ETHDEV_QUEUE_STAT_CNTRS - 1);\n\tprintf(\" --no-flush-rx: Don't flush RX streams before forwarding.\"\n\t \" Used mainly with PCAP drivers.\\n\");\n\tprintf(\" --txpkts=X[,Y]*: set TX segment sizes.\\n\");\n\tprintf(\" --disable-link-check: disable check on link status when \"\n\t \"starting/stopping ports.\\n\");\n}\n\n#ifdef RTE_LIBRTE_CMDLINE\nstatic int\ninit_peer_eth_addrs(char *config_filename)\n{\n\tFILE *config_file;\n\tportid_t i;\n\tchar buf[50];\n\n\tconfig_file = fopen(config_filename, \"r\");\n\tif (config_file == NULL) {\n\t\tperror(\"Failed to open eth config file\\n\");\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\n\t\tif (fgets(buf, sizeof(buf), config_file) == NULL)\n\t\t\tbreak;\n\n\t\tif (cmdline_parse_etheraddr(NULL, buf, &peer_eth_addrs[i],\n\t\t\t\tsizeof(peer_eth_addrs[i])) < 0) {\n\t\t\tprintf(\"Bad MAC address format on line %d\\n\", i+1);\n\t\t\tfclose(config_file);\n\t\t\treturn -1;\n\t\t}\n\t}\n\tfclose(config_file);\n\tnb_peer_eth_addrs = (portid_t) i;\n\treturn 0;\n}\n#endif\n\n/*\n * Parse the coremask given as argument (hexadecimal string) and set\n * the global configuration of forwarding cores.\n */\nstatic void\nparse_fwd_coremask(const char *coremask)\n{\n\tchar *end;\n\tunsigned long long int cm;\n\n\t/* parse hexadecimal string */\n\tend = NULL;\n\tcm = strtoull(coremask, &end, 16);\n\tif ((coremask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\trte_exit(EXIT_FAILURE, \"Invalid fwd core mask\\n\");\n\telse if (set_fwd_lcores_mask((uint64_t) cm) < 0)\n\t\trte_exit(EXIT_FAILURE, \"coremask is not valid\\n\");\n}\n\n/*\n * Parse the coremask given as argument (hexadecimal string) and set\n * the global configuration of forwarding cores.\n */\nstatic void\nparse_fwd_portmask(const char *portmask)\n{\n\tchar *end;\n\tunsigned long long int pm;\n\n\t/* parse hexadecimal string */\n\tend = NULL;\n\tpm = strtoull(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\trte_exit(EXIT_FAILURE, \"Invalid fwd port mask\\n\");\n\telse\n\t\tset_fwd_ports_mask((uint64_t) pm);\n}\n\n\nstatic int\nparse_queue_stats_mapping_config(const char *q_arg, int is_rx)\n{\n\tchar s[256];\n\tconst char *p, *p0 = q_arg;\n\tchar *end;\n\tenum fieldnames {\n\t\tFLD_PORT = 0,\n\t\tFLD_QUEUE,\n\t\tFLD_STATS_COUNTER,\n\t\t_NUM_FLD\n\t};\n\tunsigned long int_fld[_NUM_FLD];\n\tchar *str_fld[_NUM_FLD];\n\tint i;\n\tunsigned size;\n\n\t/* reset from value set at definition */\n\tis_rx ? (nb_rx_queue_stats_mappings = 0) : (nb_tx_queue_stats_mappings = 0);\n\n\twhile ((p = strchr(p0,'(')) != NULL) {\n\t\t++p;\n\t\tif((p0 = strchr(p,')')) == NULL)\n\t\t\treturn -1;\n\n\t\tsize = p0 - p;\n\t\tif(size >= sizeof(s))\n\t\t\treturn -1;\n\n\t\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\t\tif (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') != _NUM_FLD)\n\t\t\treturn -1;\n\t\tfor (i = 0; i < _NUM_FLD; i++){\n\t\t\terrno = 0;\n\t\t\tint_fld[i] = strtoul(str_fld[i], &end, 0);\n\t\t\tif (errno != 0 || end == str_fld[i] || int_fld[i] > 255)\n\t\t\t\treturn -1;\n\t\t}\n\t\t/* Check mapping field is in correct range (0..RTE_ETHDEV_QUEUE_STAT_CNTRS-1) */\n\t\tif (int_fld[FLD_STATS_COUNTER] >= RTE_ETHDEV_QUEUE_STAT_CNTRS) {\n\t\t\tprintf(\"Stats counter not in the correct range 0..%d\\n\",\n\t\t\t\t\tRTE_ETHDEV_QUEUE_STAT_CNTRS - 1);\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (!is_rx) {\n\t\t\tif ((nb_tx_queue_stats_mappings >=\n\t\t\t\t\t\tMAX_TX_QUEUE_STATS_MAPPINGS)) {\n\t\t\t\tprintf(\"exceeded max number of TX queue \"\n\t\t\t\t\t\t\"statistics mappings: %hu\\n\",\n\t\t\t\t\t\tnb_tx_queue_stats_mappings);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\ttx_queue_stats_mappings_array[nb_tx_queue_stats_mappings].port_id =\n\t\t\t\t(uint8_t)int_fld[FLD_PORT];\n\t\t\ttx_queue_stats_mappings_array[nb_tx_queue_stats_mappings].queue_id =\n\t\t\t\t(uint8_t)int_fld[FLD_QUEUE];\n\t\t\ttx_queue_stats_mappings_array[nb_tx_queue_stats_mappings].stats_counter_id =\n\t\t\t\t(uint8_t)int_fld[FLD_STATS_COUNTER];\n\t\t\t++nb_tx_queue_stats_mappings;\n\t\t}\n\t\telse {\n\t\t\tif ((nb_rx_queue_stats_mappings >=\n\t\t\t\t\t\tMAX_RX_QUEUE_STATS_MAPPINGS)) {\n\t\t\t\tprintf(\"exceeded max number of RX queue \"\n\t\t\t\t\t\t\"statistics mappings: %hu\\n\",\n\t\t\t\t\t\tnb_rx_queue_stats_mappings);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\trx_queue_stats_mappings_array[nb_rx_queue_stats_mappings].port_id =\n\t\t\t\t(uint8_t)int_fld[FLD_PORT];\n\t\t\trx_queue_stats_mappings_array[nb_rx_queue_stats_mappings].queue_id =\n\t\t\t\t(uint8_t)int_fld[FLD_QUEUE];\n\t\t\trx_queue_stats_mappings_array[nb_rx_queue_stats_mappings].stats_counter_id =\n\t\t\t\t(uint8_t)int_fld[FLD_STATS_COUNTER];\n\t\t\t++nb_rx_queue_stats_mappings;\n\t\t}\n\n\t}\n/* Reassign the rx/tx_queue_stats_mappings pointer to point to this newly populated array rather */\n/* than to the default array (that was set at its definition) */\n\tis_rx ? (rx_queue_stats_mappings = rx_queue_stats_mappings_array) :\n\t\t(tx_queue_stats_mappings = tx_queue_stats_mappings_array);\n\treturn 0;\n}\n\nstatic int\nparse_portnuma_config(const char *q_arg)\n{\n\tchar s[256];\n\tconst char *p, *p0 = q_arg;\n\tchar *end;\n\tuint8_t i,port_id,socket_id;\n\tunsigned size;\n\tenum fieldnames {\n\t\tFLD_PORT = 0,\n\t\tFLD_SOCKET,\n\t\t_NUM_FLD\n\t};\n\tunsigned long int_fld[_NUM_FLD];\n\tchar *str_fld[_NUM_FLD];\n\tportid_t pid;\n\n\t/* reset from value set at definition */\n\twhile ((p = strchr(p0,'(')) != NULL) {\n\t\t++p;\n\t\tif((p0 = strchr(p,')')) == NULL)\n\t\t\treturn -1;\n\n\t\tsize = p0 - p;\n\t\tif(size >= sizeof(s))\n\t\t\treturn -1;\n\n\t\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\t\tif (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') != _NUM_FLD)\n\t\t\treturn -1;\n\t\tfor (i = 0; i < _NUM_FLD; i++) {\n\t\t\terrno = 0;\n\t\t\tint_fld[i] = strtoul(str_fld[i], &end, 0);\n\t\t\tif (errno != 0 || end == str_fld[i] || int_fld[i] > 255)\n\t\t\t\treturn -1;\n\t\t}\n\t\tport_id = (uint8_t)int_fld[FLD_PORT];\n\t\tif (port_id_is_invalid(port_id, ENABLED_WARN)) {\n\t\t\tprintf(\"Valid port range is [0\");\n\t\t\tFOREACH_PORT(pid, ports)\n\t\t\t\tprintf(\", %d\", pid);\n\t\t\tprintf(\"]\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tsocket_id = (uint8_t)int_fld[FLD_SOCKET];\n\t\tif(socket_id >= MAX_SOCKET) {\n\t\t\tprintf(\"Invalid socket id, range is [0, %d]\\n\",\n\t\t\t\t MAX_SOCKET - 1);\n\t\t\treturn -1;\n\t\t}\n\t\tport_numa[port_id] = socket_id;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nparse_ringnuma_config(const char *q_arg)\n{\n\tchar s[256];\n\tconst char *p, *p0 = q_arg;\n\tchar *end;\n\tuint8_t i,port_id,ring_flag,socket_id;\n\tunsigned size;\n\tenum fieldnames {\n\t\tFLD_PORT = 0,\n\t\tFLD_FLAG,\n\t\tFLD_SOCKET,\n\t\t_NUM_FLD\n\t};\n\tunsigned long int_fld[_NUM_FLD];\n\tchar *str_fld[_NUM_FLD];\n\tportid_t pid;\n\t#define RX_RING_ONLY 0x1\n\t#define TX_RING_ONLY 0x2\n\t#define RXTX_RING 0x3\n\n\t/* reset from value set at definition */\n\twhile ((p = strchr(p0,'(')) != NULL) {\n\t\t++p;\n\t\tif((p0 = strchr(p,')')) == NULL)\n\t\t\treturn -1;\n\n\t\tsize = p0 - p;\n\t\tif(size >= sizeof(s))\n\t\t\treturn -1;\n\n\t\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\t\tif (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') != _NUM_FLD)\n\t\t\treturn -1;\n\t\tfor (i = 0; i < _NUM_FLD; i++) {\n\t\t\terrno = 0;\n\t\t\tint_fld[i] = strtoul(str_fld[i], &end, 0);\n\t\t\tif (errno != 0 || end == str_fld[i] || int_fld[i] > 255)\n\t\t\t\treturn -1;\n\t\t}\n\t\tport_id = (uint8_t)int_fld[FLD_PORT];\n\t\tif (port_id_is_invalid(port_id, ENABLED_WARN)) {\n\t\t\tprintf(\"Valid port range is [0\");\n\t\t\tFOREACH_PORT(pid, ports)\n\t\t\t\tprintf(\", %d\", pid);\n\t\t\tprintf(\"]\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tsocket_id = (uint8_t)int_fld[FLD_SOCKET];\n\t\tif (socket_id >= MAX_SOCKET) {\n\t\t\tprintf(\"Invalid socket id, range is [0, %d]\\n\",\n\t\t\t\tMAX_SOCKET - 1);\n\t\t\treturn -1;\n\t\t}\n\t\tring_flag = (uint8_t)int_fld[FLD_FLAG];\n\t\tif ((ring_flag < RX_RING_ONLY) || (ring_flag > RXTX_RING)) {\n\t\t\tprintf(\"Invalid ring-flag=%d config for port =%d\\n\",\n\t\t\t\tring_flag,port_id);\n\t\t\treturn -1;\n\t\t}\n\n\t\tswitch (ring_flag & RXTX_RING) {\n\t\tcase RX_RING_ONLY:\n\t\t\trxring_numa[port_id] = socket_id;\n\t\t\tbreak;\n\t\tcase TX_RING_ONLY:\n\t\t\ttxring_numa[port_id] = socket_id;\n\t\t\tbreak;\n\t\tcase RXTX_RING:\n\t\t\trxring_numa[port_id] = socket_id;\n\t\t\ttxring_numa[port_id] = socket_id;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintf(\"Invalid ring-flag=%d config for port=%d\\n\",\n\t\t\t\tring_flag,port_id);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nvoid\nlaunch_args_parse(int argc, char** argv)\n{\n\tint n, opt;\n\tchar **argvopt;\n\tint opt_idx;\n\tenum { TX, RX };\n\n\tstatic struct option lgopts[] = {\n\t\t{ \"help\",\t\t\t0, 0, 0 },\n#ifdef RTE_LIBRTE_CMDLINE\n\t\t{ \"interactive\",\t\t0, 0, 0 },\n\t\t{ \"auto-start\",\t\t\t0, 0, 0 },\n\t\t{ \"eth-peers-configfile\",\t1, 0, 0 },\n\t\t{ \"eth-peer\",\t\t\t1, 0, 0 },\n#endif\n\t\t{ \"ports\",\t\t\t1, 0, 0 },\n\t\t{ \"nb-cores\",\t\t\t1, 0, 0 },\n\t\t{ \"nb-ports\",\t\t\t1, 0, 0 },\n\t\t{ \"coremask\",\t\t\t1, 0, 0 },\n\t\t{ \"portmask\",\t\t\t1, 0, 0 },\n\t\t{ \"numa\",\t\t\t0, 0, 0 },\n\t\t{ \"mp-anon\",\t\t\t0, 0, 0 },\n\t\t{ \"port-numa-config\", 1, 0, 0 },\n\t\t{ \"ring-numa-config\", 1, 0, 0 },\n\t\t{ \"socket-num\",\t\t\t1, 0, 0 },\n\t\t{ \"mbuf-size\",\t\t\t1, 0, 0 },\n\t\t{ \"total-num-mbufs\",\t\t1, 0, 0 },\n\t\t{ \"max-pkt-len\",\t\t1, 0, 0 },\n\t\t{ \"pkt-filter-mode\", 1, 0, 0 },\n\t\t{ \"pkt-filter-report-hash\", 1, 0, 0 },\n\t\t{ \"pkt-filter-size\", 1, 0, 0 },\n\t\t{ \"pkt-filter-drop-queue\", 1, 0, 0 },\n\t\t{ \"crc-strip\", 0, 0, 0 },\n\t\t{ \"enable-rx-cksum\", 0, 0, 0 },\n\t\t{ \"disable-hw-vlan\", 0, 0, 0 },\n\t\t{ \"disable-hw-vlan-filter\", 0, 0, 0 },\n\t\t{ \"disable-hw-vlan-strip\", 0, 0, 0 },\n\t\t{ \"disable-hw-vlan-extend\", 0, 0, 0 },\n\t\t{ \"enable-drop-en\", 0, 0, 0 },\n\t\t{ \"disable-rss\", 0, 0, 0 },\n\t\t{ \"port-topology\", 1, 0, 0 },\n\t\t{ \"forward-mode\", 1, 0, 0 },\n\t\t{ \"rss-ip\",\t\t\t0, 0, 0 },\n\t\t{ \"rss-udp\",\t\t\t0, 0, 0 },\n\t\t{ \"rxq\",\t\t\t1, 0, 0 },\n\t\t{ \"txq\",\t\t\t1, 0, 0 },\n\t\t{ \"rxd\",\t\t\t1, 0, 0 },\n\t\t{ \"txd\",\t\t\t1, 0, 0 },\n\t\t{ \"burst\",\t\t\t1, 0, 0 },\n\t\t{ \"mbcache\",\t\t\t1, 0, 0 },\n\t\t{ \"txpt\",\t\t\t1, 0, 0 },\n\t\t{ \"txht\",\t\t\t1, 0, 0 },\n\t\t{ \"txwt\",\t\t\t1, 0, 0 },\n\t\t{ \"txfreet\",\t\t\t1, 0, 0 },\n\t\t{ \"txrst\",\t\t\t1, 0, 0 },\n\t\t{ \"txqflags\",\t\t\t1, 0, 0 },\n\t\t{ \"rxpt\",\t\t\t1, 0, 0 },\n\t\t{ \"rxht\",\t\t\t1, 0, 0 },\n\t\t{ \"rxwt\",\t\t\t1, 0, 0 },\n\t\t{ \"rxfreet\", 1, 0, 0 },\n\t\t{ \"tx-queue-stats-mapping\",\t1, 0, 0 },\n\t\t{ \"rx-queue-stats-mapping\",\t1, 0, 0 },\n\t\t{ \"no-flush-rx\",\t0, 0, 0 },\n\t\t{ \"txpkts\",\t\t\t1, 0, 0 },\n\t\t{ \"disable-link-check\",\t\t0, 0, 0 },\n\t\t{ 0, 0, 0, 0 },\n\t};\n\n\targvopt = argv;\n\n#ifdef RTE_LIBRTE_CMDLINE\n#define SHORTOPTS \"i\"\n#else\n#define SHORTOPTS \"\"\n#endif\n\twhile ((opt = getopt_long(argc, argvopt, SHORTOPTS \"ah\",\n\t\t\t\t lgopts, &opt_idx)) != EOF) {\n\t\tswitch (opt) {\n#ifdef RTE_LIBRTE_CMDLINE\n\t\tcase 'i':\n\t\t\tprintf(\"Interactive-mode selected\\n\");\n\t\t\tinteractive = 1;\n\t\t\tbreak;\n#endif\n\t\tcase 'a':\n\t\t\tprintf(\"Auto-start selected\\n\");\n\t\t\tauto_start = 1;\n\t\t\tbreak;\n\n\t\tcase 0: /*long options */\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"help\")) {\n\t\t\t\tusage(argv[0]);\n\t\t\t\trte_exit(EXIT_SUCCESS, \"Displayed help\\n\");\n\t\t\t}\n#ifdef RTE_LIBRTE_CMDLINE\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"interactive\")) {\n\t\t\t\tprintf(\"Interactive-mode selected\\n\");\n\t\t\t\tinteractive = 1;\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"auto-start\")) {\n\t\t\t\tprintf(\"Auto-start selected\\n\");\n\t\t\t\tauto_start = 1;\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name,\n\t\t\t\t \"eth-peers-configfile\")) {\n\t\t\t\tif (init_peer_eth_addrs(optarg) != 0)\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"Cannot open logfile\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"eth-peer\")) {\n\t\t\t\tchar *port_end;\n\t\t\t\tuint8_t c, peer_addr[6];\n\n\t\t\t\terrno = 0;\n\t\t\t\tn = strtoul(optarg, &port_end, 10);\n\t\t\t\tif (errno != 0 || port_end == optarg || *port_end++ != ',')\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"Invalid eth-peer: %s\", optarg);\n\t\t\t\tif (n >= RTE_MAX_ETHPORTS)\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"eth-peer: port %d >= RTE_MAX_ETHPORTS(%d)\\n\",\n\t\t\t\t\t\t n, RTE_MAX_ETHPORTS);\n\n\t\t\t\tif (cmdline_parse_etheraddr(NULL, port_end,\n\t\t\t\t\t\t&peer_addr, sizeof(peer_addr)) < 0)\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"Invalid ethernet address: %s\\n\",\n\t\t\t\t\t\t port_end);\n\t\t\t\tfor (c = 0; c < 6; c++)\n\t\t\t\t\tpeer_eth_addrs[n].addr_bytes[c] =\n\t\t\t\t\t\tpeer_addr[c];\n\t\t\t\tnb_peer_eth_addrs++;\n\t\t\t}\n#endif\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"nb-ports\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n > 0 && n <= nb_ports)\n\t\t\t\t\tnb_fwd_ports = (uint8_t) n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"Invalid port %d\\n\", n);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"nb-cores\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n > 0 && n <= nb_lcores)\n\t\t\t\t\tnb_fwd_lcores = (uint8_t) n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"nb-cores should be > 0 and <= %d\\n\",\n\t\t\t\t\t\t nb_lcores);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"coremask\"))\n\t\t\t\tparse_fwd_coremask(optarg);\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"portmask\"))\n\t\t\t\tparse_fwd_portmask(optarg);\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"numa\")) {\n\t\t\t\tnuma_support = 1;\n\t\t\t\tmemset(port_numa,NUMA_NO_CONFIG,RTE_MAX_ETHPORTS);\n\t\t\t\tmemset(rxring_numa,NUMA_NO_CONFIG,RTE_MAX_ETHPORTS);\n\t\t\t\tmemset(txring_numa,NUMA_NO_CONFIG,RTE_MAX_ETHPORTS);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"mp-anon\")) {\n\t\t\t\tmp_anon = 1;\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"port-numa-config\")) {\n\t\t\t\tif (parse_portnuma_config(optarg))\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t \"invalid port-numa configuration\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"ring-numa-config\"))\n\t\t\t\tif (parse_ringnuma_config(optarg))\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t \"invalid ring-numa configuration\\n\");\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"socket-num\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif(n < MAX_SOCKET)\n\t\t\t\t\tsocket_num = (uint8_t)n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t\"The socket number should be < %d\\n\",\n\t\t\t\t\t\tMAX_SOCKET);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"mbuf-size\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n > 0 && n <= 0xFFFF)\n\t\t\t\t\tmbuf_data_size = (uint16_t) n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"mbuf-size should be > 0 and < 65536\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"total-num-mbufs\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n > 1024)\n\t\t\t\t\tparam_total_num_mbufs = (unsigned)n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"total-num-mbufs should be > 1024\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"max-pkt-len\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= ETHER_MIN_LEN) {\n\t\t\t\t\trx_mode.max_rx_pkt_len = (uint32_t) n;\n\t\t\t\t\tif (n > ETHER_MAX_LEN)\n\t\t\t\t\t rx_mode.jumbo_frame = 1;\n\t\t\t\t} else\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"Invalid max-pkt-len=%d - should be > %d\\n\",\n\t\t\t\t\t\t n, ETHER_MIN_LEN);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"pkt-filter-mode\")) {\n\t\t\t\tif (!strcmp(optarg, \"signature\"))\n\t\t\t\t\tfdir_conf.mode =\n\t\t\t\t\t\tRTE_FDIR_MODE_SIGNATURE;\n\t\t\t\telse if (!strcmp(optarg, \"perfect\"))\n\t\t\t\t\tfdir_conf.mode = RTE_FDIR_MODE_PERFECT;\n\t\t\t\telse if (!strcmp(optarg, \"none\"))\n\t\t\t\t\tfdir_conf.mode = RTE_FDIR_MODE_NONE;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"pkt-mode-invalid %s invalid - must be: \"\n\t\t\t\t\t\t \"none, signature or perfect\\n\",\n\t\t\t\t\t\t optarg);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name,\n\t\t\t\t \"pkt-filter-report-hash\")) {\n\t\t\t\tif (!strcmp(optarg, \"none\"))\n\t\t\t\t\tfdir_conf.status =\n\t\t\t\t\t\tRTE_FDIR_NO_REPORT_STATUS;\n\t\t\t\telse if (!strcmp(optarg, \"match\"))\n\t\t\t\t\tfdir_conf.status =\n\t\t\t\t\t\tRTE_FDIR_REPORT_STATUS;\n\t\t\t\telse if (!strcmp(optarg, \"always\"))\n\t\t\t\t\tfdir_conf.status =\n\t\t\t\t\t\tRTE_FDIR_REPORT_STATUS_ALWAYS;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"pkt-filter-report-hash %s invalid \"\n\t\t\t\t\t\t \"- must be: none or match or always\\n\",\n\t\t\t\t\t\t optarg);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"pkt-filter-size\")) {\n\t\t\t\tif (!strcmp(optarg, \"64K\"))\n\t\t\t\t\tfdir_conf.pballoc =\n\t\t\t\t\t\tRTE_FDIR_PBALLOC_64K;\n\t\t\t\telse if (!strcmp(optarg, \"128K\"))\n\t\t\t\t\tfdir_conf.pballoc =\n\t\t\t\t\t\tRTE_FDIR_PBALLOC_128K;\n\t\t\t\telse if (!strcmp(optarg, \"256K\"))\n\t\t\t\t\tfdir_conf.pballoc =\n\t\t\t\t\t\tRTE_FDIR_PBALLOC_256K;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"pkt-filter-size %s invalid -\"\n\t\t\t\t\t\t \" must be: 64K or 128K or 256K\\n\",\n\t\t\t\t\t\t optarg);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name,\n\t\t\t\t \"pkt-filter-drop-queue\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= 0)\n\t\t\t\t\tfdir_conf.drop_queue = (uint8_t) n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"drop queue %d invalid - must\"\n\t\t\t\t\t\t \"be >= 0 \\n\", n);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"crc-strip\"))\n\t\t\t\trx_mode.hw_strip_crc = 1;\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"enable-rx-cksum\"))\n\t\t\t\trx_mode.hw_ip_checksum = 1;\n\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"disable-hw-vlan\")) {\n\t\t\t\trx_mode.hw_vlan_filter = 0;\n\t\t\t\trx_mode.hw_vlan_strip = 0;\n\t\t\t\trx_mode.hw_vlan_extend = 0;\n\t\t\t}\n\n\t\t\tif (!strcmp(lgopts[opt_idx].name,\n\t\t\t\t\t\"disable-hw-vlan-filter\"))\n\t\t\t\trx_mode.hw_vlan_filter = 0;\n\n\t\t\tif (!strcmp(lgopts[opt_idx].name,\n\t\t\t\t\t\"disable-hw-vlan-strip\"))\n\t\t\t\trx_mode.hw_vlan_strip = 0;\n\n\t\t\tif (!strcmp(lgopts[opt_idx].name,\n\t\t\t\t\t\"disable-hw-vlan-extend\"))\n\t\t\t\trx_mode.hw_vlan_extend = 0;\n\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"enable-drop-en\"))\n\t\t\t\trx_drop_en = 1;\n\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"disable-rss\"))\n\t\t\t\trss_hf = 0;\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"port-topology\")) {\n\t\t\t\tif (!strcmp(optarg, \"paired\"))\n\t\t\t\t\tport_topology = PORT_TOPOLOGY_PAIRED;\n\t\t\t\telse if (!strcmp(optarg, \"chained\"))\n\t\t\t\t\tport_topology = PORT_TOPOLOGY_CHAINED;\n\t\t\t\telse if (!strcmp(optarg, \"loop\"))\n\t\t\t\t\tport_topology = PORT_TOPOLOGY_LOOP;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"port-topology %s invalid -\"\n\t\t\t\t\t\t \" must be: paired or chained \\n\",\n\t\t\t\t\t\t optarg);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"forward-mode\"))\n\t\t\t\tset_pkt_forwarding_mode(optarg);\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"rss-ip\"))\n\t\t\t\trss_hf = ETH_RSS_IP;\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"rss-udp\"))\n\t\t\t\trss_hf = ETH_RSS_UDP;\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"rxq\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= 1 && n <= (int) MAX_QUEUE_ID)\n\t\t\t\t\tnb_rxq = (queueid_t) n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"rxq %d invalid - must be\"\n\t\t\t\t\t\t \" >= 1 && <= %d\\n\", n,\n\t\t\t\t\t\t (int) MAX_QUEUE_ID);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"txq\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= 1 && n <= (int) MAX_QUEUE_ID)\n\t\t\t\t\tnb_txq = (queueid_t) n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"txq %d invalid - must be\"\n\t\t\t\t\t\t \" >= 1 && <= %d\\n\", n,\n\t\t\t\t\t\t (int) MAX_QUEUE_ID);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"burst\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif ((n >= 1) && (n <= MAX_PKT_BURST))\n\t\t\t\t\tnb_pkt_per_burst = (uint16_t) n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"burst must >= 1 and <= %d]\",\n\t\t\t\t\t\t MAX_PKT_BURST);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"mbcache\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif ((n >= 0) &&\n\t\t\t\t (n <= RTE_MEMPOOL_CACHE_MAX_SIZE))\n\t\t\t\t\tmb_mempool_cache = (uint16_t) n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"mbcache must be >= 0 and <= %d\\n\",\n\t\t\t\t\t\t RTE_MEMPOOL_CACHE_MAX_SIZE);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"txfreet\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= 0)\n\t\t\t\t\ttx_free_thresh = (int16_t)n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"txfreet must be >= 0\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"txrst\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= 0)\n\t\t\t\t\ttx_rs_thresh = (int16_t)n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"txrst must be >= 0\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"txqflags\")) {\n\t\t\t\tchar *end = NULL;\n\t\t\t\tn = strtoul(optarg, &end, 16);\n\t\t\t\tif (n >= 0)\n\t\t\t\t\ttxq_flags = (int32_t)n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"txqflags must be >= 0\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"rxd\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n > 0) {\n\t\t\t\t\tif (rx_free_thresh >= n)\n\t\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t\t \"rxd must be > \"\n\t\t\t\t\t\t\t \"rx_free_thresh(%d)\\n\",\n\t\t\t\t\t\t\t (int)rx_free_thresh);\n\t\t\t\t\telse\n\t\t\t\t\t\tnb_rxd = (uint16_t) n;\n\t\t\t\t} else\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"rxd(%d) invalid - must be > 0\\n\",\n\t\t\t\t\t\t n);\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"txd\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n > 0)\n\t\t\t\t\tnb_txd = (uint16_t) n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"txd must be in > 0\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"txpt\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= 0)\n\t\t\t\t\ttx_pthresh = (int8_t)n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"txpt must be >= 0\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"txht\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= 0)\n\t\t\t\t\ttx_hthresh = (int8_t)n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"txht must be >= 0\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"txwt\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= 0)\n\t\t\t\t\ttx_wthresh = (int8_t)n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"txwt must be >= 0\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"rxpt\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= 0)\n\t\t\t\t\trx_pthresh = (int8_t)n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"rxpt must be >= 0\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"rxht\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= 0)\n\t\t\t\t\trx_hthresh = (int8_t)n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"rxht must be >= 0\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"rxwt\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= 0)\n\t\t\t\t\trx_wthresh = (int8_t)n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"rxwt must be >= 0\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"rxfreet\")) {\n\t\t\t\tn = atoi(optarg);\n\t\t\t\tif (n >= 0)\n\t\t\t\t\trx_free_thresh = (int16_t)n;\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"rxfreet must be >= 0\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"tx-queue-stats-mapping\")) {\n\t\t\t\tif (parse_queue_stats_mapping_config(optarg, TX)) {\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"invalid TX queue statistics mapping config entered\\n\");\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"rx-queue-stats-mapping\")) {\n\t\t\t\tif (parse_queue_stats_mapping_config(optarg, RX)) {\n\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t \"invalid RX queue statistics mapping config entered\\n\");\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"txpkts\")) {\n\t\t\t\tunsigned seg_lengths[RTE_MAX_SEGS_PER_PKT];\n\t\t\t\tunsigned int nb_segs;\n\n\t\t\t\tnb_segs = parse_item_list(optarg, \"txpkt segments\",\n\t\t\t\t\t\tRTE_MAX_SEGS_PER_PKT, seg_lengths, 0);\n\t\t\t\tif (nb_segs > 0)\n\t\t\t\t\tset_tx_pkt_segments(seg_lengths, nb_segs);\n\t\t\t\telse\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"bad txpkts\\n\");\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"no-flush-rx\"))\n\t\t\t\tno_flush_rx = 1;\n\t\t\tif (!strcmp(lgopts[opt_idx].name, \"disable-link-check\"))\n\t\t\t\tno_link_check = 1;\n\n\t\t\tbreak;\n\t\tcase 'h':\n\t\t\tusage(argv[0]);\n\t\t\trte_exit(EXIT_SUCCESS, \"Displayed help\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tusage(argv[0]);\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t \"Command line is incomplete or incorrect\\n\");\n\t\t\tbreak;\n\t\t}\n\t}\n}\n" }, { "path": "app/test-pmd/rxonly.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"testpmd.h\"\n\nstatic inline void\nprint_ether_addr(const char *what, struct ether_addr *eth_addr)\n{\n\tchar buf[ETHER_ADDR_FMT_SIZE];\n\tether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);\n\tprintf(\"%s%s\", what, buf);\n}\n\n/*\n * Received a burst of packets.\n */\nstatic void\npkt_burst_receive(struct fwd_stream *fs)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_mbuf *mb;\n\tstruct ether_hdr *eth_hdr;\n\tuint16_t eth_type;\n\tuint64_t ol_flags;\n\tuint16_t nb_rx;\n\tuint16_t i, packet_type;\n#ifdef RTE_NEXT_ABI\n\tuint16_t is_encapsulation;\n#else\n\tuint64_t is_encapsulation;\n#endif\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tuint64_t start_tsc;\n\tuint64_t end_tsc;\n\tuint64_t core_cycles;\n#endif\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tstart_tsc = rte_rdtsc();\n#endif\n\n\t/*\n\t * Receive a burst of packets.\n\t */\n\tnb_rx = rte_eth_rx_burst(fs->rx_port, fs->rx_queue, pkts_burst,\n\t\t\t\t nb_pkt_per_burst);\n\tif (unlikely(nb_rx == 0))\n\t\treturn;\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->rx_burst_stats.pkt_burst_spread[nb_rx]++;\n#endif\n\tfs->rx_packets += nb_rx;\n\n\t/*\n\t * Dump each received packet if verbose_level > 0.\n\t */\n\tif (verbose_level > 0)\n\t\tprintf(\"port %u/queue %u: received %u packets\\n\",\n\t\t (unsigned) fs->rx_port,\n\t\t (unsigned) fs->rx_queue,\n\t\t (unsigned) nb_rx);\n\tfor (i = 0; i < nb_rx; i++) {\n\t\tmb = pkts_burst[i];\n\t\tif (verbose_level == 0) {\n\t\t\trte_pktmbuf_free(mb);\n\t\t\tcontinue;\n\t\t}\n\t\teth_hdr = rte_pktmbuf_mtod(mb, struct ether_hdr *);\n\t\teth_type = RTE_BE_TO_CPU_16(eth_hdr->ether_type);\n\t\tol_flags = mb->ol_flags;\n\t\tpacket_type = mb->packet_type;\n\n#ifdef RTE_NEXT_ABI\n\t\tis_encapsulation = RTE_ETH_IS_TUNNEL_PKT(packet_type);\n#else\n\t\tis_encapsulation = ol_flags & (PKT_RX_TUNNEL_IPV4_HDR |\n\t\t\t\tPKT_RX_TUNNEL_IPV6_HDR);\n#endif\n\n\t\tprint_ether_addr(\" src=\", ð_hdr->s_addr);\n\t\tprint_ether_addr(\" - dst=\", ð_hdr->d_addr);\n\t\tprintf(\" - type=0x%04x - length=%u - nb_segs=%d\",\n\t\t eth_type, (unsigned) mb->pkt_len,\n\t\t (int)mb->nb_segs);\n\t\tif (ol_flags & PKT_RX_RSS_HASH) {\n\t\t\tprintf(\" - RSS hash=0x%x\", (unsigned) mb->hash.rss);\n\t\t\tprintf(\" - RSS queue=0x%x\",(unsigned) fs->rx_queue);\n\t\t} else if (ol_flags & PKT_RX_FDIR) {\n\t\t\tprintf(\" - FDIR matched \");\n\t\t\tif (ol_flags & PKT_RX_FDIR_ID)\n\t\t\t\tprintf(\"ID=0x%x\",\n\t\t\t\t mb->hash.fdir.hi);\n\t\t\telse if (ol_flags & PKT_RX_FDIR_FLX)\n\t\t\t\tprintf(\"flex bytes=0x%08x %08x\",\n\t\t\t\t mb->hash.fdir.hi, mb->hash.fdir.lo);\n\t\t\telse\n\t\t\t\tprintf(\"hash=0x%x ID=0x%x \",\n\t\t\t\t mb->hash.fdir.hash, mb->hash.fdir.id);\n\t\t}\n\t\tif (ol_flags & PKT_RX_VLAN_PKT)\n\t\t\tprintf(\" - VLAN tci=0x%x\", mb->vlan_tci);\n\t\tif (ol_flags & PKT_RX_QINQ_PKT)\n\t\t\tprintf(\" - QinQ VLAN tci=0x%x, VLAN tci outer=0x%x\",\n\t\t\t\t\tmb->vlan_tci, mb->vlan_tci_outer);\n#ifdef RTE_NEXT_ABI\n\t\tif (mb->packet_type) {\n\t\t\tuint32_t ptype;\n\n\t\t\t/* (outer) L2 packet type */\n\t\t\tptype = mb->packet_type & RTE_PTYPE_L2_MASK;\n\t\t\tswitch (ptype) {\n\t\t\tcase RTE_PTYPE_L2_ETHER:\n\t\t\t\tprintf(\" - (outer) L2 type: ETHER\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L2_ETHER_TIMESYNC:\n\t\t\t\tprintf(\" - (outer) L2 type: ETHER_Timesync\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L2_ETHER_ARP:\n\t\t\t\tprintf(\" - (outer) L2 type: ETHER_ARP\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L2_ETHER_LLDP:\n\t\t\t\tprintf(\" - (outer) L2 type: ETHER_LLDP\");\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tprintf(\" - (outer) L2 type: Unknown\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* (outer) L3 packet type */\n\t\t\tptype = mb->packet_type & RTE_PTYPE_L3_MASK;\n\t\t\tswitch (ptype) {\n\t\t\tcase RTE_PTYPE_L3_IPV4:\n\t\t\t\tprintf(\" - (outer) L3 type: IPV4\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L3_IPV4_EXT:\n\t\t\t\tprintf(\" - (outer) L3 type: IPV4_EXT\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L3_IPV6:\n\t\t\t\tprintf(\" - (outer) L3 type: IPV6\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L3_IPV4_EXT_UNKNOWN:\n\t\t\t\tprintf(\" - (outer) L3 type: IPV4_EXT_UNKNOWN\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L3_IPV6_EXT:\n\t\t\t\tprintf(\" - (outer) L3 type: IPV6_EXT\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L3_IPV6_EXT_UNKNOWN:\n\t\t\t\tprintf(\" - (outer) L3 type: IPV6_EXT_UNKNOWN\");\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tprintf(\" - (outer) L3 type: Unknown\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* (outer) L4 packet type */\n\t\t\tptype = mb->packet_type & RTE_PTYPE_L4_MASK;\n\t\t\tswitch (ptype) {\n\t\t\tcase RTE_PTYPE_L4_TCP:\n\t\t\t\tprintf(\" - (outer) L4 type: TCP\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L4_UDP:\n\t\t\t\tprintf(\" - (outer) L4 type: UDP\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L4_FRAG:\n\t\t\t\tprintf(\" - (outer) L4 type: L4_FRAG\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L4_SCTP:\n\t\t\t\tprintf(\" - (outer) L4 type: SCTP\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L4_ICMP:\n\t\t\t\tprintf(\" - (outer) L4 type: ICMP\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_L4_NONFRAG:\n\t\t\t\tprintf(\" - (outer) L4 type: L4_NONFRAG\");\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tprintf(\" - (outer) L4 type: Unknown\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* packet tunnel type */\n\t\t\tptype = mb->packet_type & RTE_PTYPE_TUNNEL_MASK;\n\t\t\tswitch (ptype) {\n\t\t\tcase RTE_PTYPE_TUNNEL_IP:\n\t\t\t\tprintf(\" - Tunnel type: IP\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_TUNNEL_GRE:\n\t\t\t\tprintf(\" - Tunnel type: GRE\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_TUNNEL_VXLAN:\n\t\t\t\tprintf(\" - Tunnel type: VXLAN\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_TUNNEL_NVGRE:\n\t\t\t\tprintf(\" - Tunnel type: NVGRE\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_TUNNEL_GENEVE:\n\t\t\t\tprintf(\" - Tunnel type: GENEVE\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_TUNNEL_GRENAT:\n\t\t\t\tprintf(\" - Tunnel type: GRENAT\");\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tprintf(\" - Tunnel type: Unknown\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* inner L2 packet type */\n\t\t\tptype = mb->packet_type & RTE_PTYPE_INNER_L2_MASK;\n\t\t\tswitch (ptype) {\n\t\t\tcase RTE_PTYPE_INNER_L2_ETHER:\n\t\t\t\tprintf(\" - Inner L2 type: ETHER\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_INNER_L2_ETHER_VLAN:\n\t\t\t\tprintf(\" - Inner L2 type: ETHER_VLAN\");\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tprintf(\" - Inner L2 type: Unknown\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* inner L3 packet type */\n\t\t\tptype = mb->packet_type & RTE_PTYPE_INNER_L3_MASK;\n\t\t\tswitch (ptype) {\n\t\t\tcase RTE_PTYPE_INNER_L3_IPV4:\n\t\t\t\tprintf(\" - Inner L3 type: IPV4\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_INNER_L3_IPV4_EXT:\n\t\t\t\tprintf(\" - Inner L3 type: IPV4_EXT\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_INNER_L3_IPV6:\n\t\t\t\tprintf(\" - Inner L3 type: IPV6\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN:\n\t\t\t\tprintf(\" - Inner L3 type: IPV4_EXT_UNKNOWN\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_INNER_L3_IPV6_EXT:\n\t\t\t\tprintf(\" - Inner L3 type: IPV6_EXT\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN:\n\t\t\t\tprintf(\" - Inner L3 type: IPV6_EXT_UNKNOWN\");\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tprintf(\" - Inner L3 type: Unknown\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* inner L4 packet type */\n\t\t\tptype = mb->packet_type & RTE_PTYPE_INNER_L4_MASK;\n\t\t\tswitch (ptype) {\n\t\t\tcase RTE_PTYPE_INNER_L4_TCP:\n\t\t\t\tprintf(\" - Inner L4 type: TCP\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_INNER_L4_UDP:\n\t\t\t\tprintf(\" - Inner L4 type: UDP\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_INNER_L4_FRAG:\n\t\t\t\tprintf(\" - Inner L4 type: L4_FRAG\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_INNER_L4_SCTP:\n\t\t\t\tprintf(\" - Inner L4 type: SCTP\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_INNER_L4_ICMP:\n\t\t\t\tprintf(\" - Inner L4 type: ICMP\");\n\t\t\t\tbreak;\n\t\t\tcase RTE_PTYPE_INNER_L4_NONFRAG:\n\t\t\t\tprintf(\" - Inner L4 type: L4_NONFRAG\");\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tprintf(\" - Inner L4 type: Unknown\");\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tprintf(\"\\n\");\n\t\t} else\n\t\t\tprintf(\"Unknown packet type\\n\");\n#endif /* RTE_NEXT_ABI */\n\t\tif (is_encapsulation) {\n\t\t\tstruct ipv4_hdr *ipv4_hdr;\n\t\t\tstruct ipv6_hdr *ipv6_hdr;\n\t\t\tstruct udp_hdr *udp_hdr;\n\t\t\tuint8_t l2_len;\n\t\t\tuint8_t l3_len;\n\t\t\tuint8_t l4_len;\n\t\t\tuint8_t l4_proto;\n\t\t\tstruct vxlan_hdr *vxlan_hdr;\n\n\t\t\tl2_len = sizeof(struct ether_hdr);\n\n\t\t\t /* Do not support ipv4 option field */\n#ifdef RTE_NEXT_ABI\n\t\t\tif (RTE_ETH_IS_IPV4_HDR(packet_type)) {\n#else\n\t\t\tif (ol_flags & PKT_RX_TUNNEL_IPV4_HDR) {\n#endif\n\t\t\t\tl3_len = sizeof(struct ipv4_hdr);\n\t\t\t\tipv4_hdr = rte_pktmbuf_mtod_offset(mb,\n\t\t\t\t\t\t\t\t struct ipv4_hdr *,\n\t\t\t\t\t\t\t\t l2_len);\n\t\t\t\tl4_proto = ipv4_hdr->next_proto_id;\n\t\t\t} else {\n\t\t\t\tl3_len = sizeof(struct ipv6_hdr);\n\t\t\t\tipv6_hdr = rte_pktmbuf_mtod_offset(mb,\n\t\t\t\t\t\t\t\t struct ipv6_hdr *,\n\t\t\t\t\t\t\t\t l2_len);\n\t\t\t\tl4_proto = ipv6_hdr->proto;\n\t\t\t}\n\t\t\tif (l4_proto == IPPROTO_UDP) {\n\t\t\t\tudp_hdr = rte_pktmbuf_mtod_offset(mb,\n\t\t\t\t\t\t\t\t struct udp_hdr *,\n\t\t\t\t\t\t\t\t l2_len + l3_len);\n\t\t\t\tl4_len = sizeof(struct udp_hdr);\n\t\t\t\tvxlan_hdr = rte_pktmbuf_mtod_offset(mb,\n\t\t\t\t\t\t\t\t struct vxlan_hdr *,\n\t\t\t\t\t\t\t\t l2_len + l3_len + l4_len);\n\n\t\t\t\tprintf(\" - VXLAN packet: packet type =%d, \"\n\t\t\t\t\t\"Destination UDP port =%d, VNI = %d\",\n\t\t\t\t\tpacket_type, RTE_BE_TO_CPU_16(udp_hdr->dst_port),\n\t\t\t\t\trte_be_to_cpu_32(vxlan_hdr->vx_vni) >> 8);\n\t\t\t}\n\t\t}\n\t\tprintf(\" - Receive queue=0x%x\", (unsigned) fs->rx_queue);\n\t\tprintf(\"\\n\");\n\t\tif (ol_flags != 0) {\n\t\t\tunsigned rxf;\n\t\t\tconst char *name;\n\n\t\t\tfor (rxf = 0; rxf < sizeof(mb->ol_flags) * 8; rxf++) {\n\t\t\t\tif ((ol_flags & (1ULL << rxf)) == 0)\n\t\t\t\t\tcontinue;\n\t\t\t\tname = rte_get_rx_ol_flag_name(1ULL << rxf);\n\t\t\t\tif (name == NULL)\n\t\t\t\t\tcontinue;\n\t\t\t\tprintf(\" %s\\n\", name);\n\t\t\t}\n\t\t}\n\t\trte_pktmbuf_free(mb);\n\t}\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tend_tsc = rte_rdtsc();\n\tcore_cycles = (end_tsc - start_tsc);\n\tfs->core_cycles = (uint64_t) (fs->core_cycles + core_cycles);\n#endif\n}\n\nstruct fwd_engine rx_only_engine = {\n\t.fwd_mode_name = \"rxonly\",\n\t.port_fwd_begin = NULL,\n\t.port_fwd_end = NULL,\n\t.packet_fwd = pkt_burst_receive,\n};\n" }, { "path": "app/test-pmd/testpmd.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#ifdef RTE_LIBRTE_PMD_XENVIRT\n#include \n#endif\n\n#include \"testpmd.h\"\n#include \"mempool_osdep.h\"\n\nuint16_t verbose_level = 0; /**< Silent by default. */\n\n/* use master core for command line ? */\nuint8_t interactive = 0;\nuint8_t auto_start = 0;\n\n/*\n * NUMA support configuration.\n * When set, the NUMA support attempts to dispatch the allocation of the\n * RX and TX memory rings, and of the DMA memory buffers (mbufs) for the\n * probed ports among the CPU sockets 0 and 1.\n * Otherwise, all memory is allocated from CPU socket 0.\n */\nuint8_t numa_support = 0; /**< No numa support by default */\n\n/*\n * In UMA mode,all memory is allocated from socket 0 if --socket-num is\n * not configured.\n */\nuint8_t socket_num = UMA_NO_CONFIG;\n\n/*\n * Use ANONYMOUS mapped memory (might be not physically continuous) for mbufs.\n */\nuint8_t mp_anon = 0;\n\n/*\n * Record the Ethernet address of peer target ports to which packets are\n * forwarded.\n * Must be instanciated with the ethernet addresses of peer traffic generator\n * ports.\n */\nstruct ether_addr peer_eth_addrs[RTE_MAX_ETHPORTS];\nportid_t nb_peer_eth_addrs = 0;\n\n/*\n * Probed Target Environment.\n */\nstruct rte_port *ports;\t /**< For all probed ethernet ports. */\nportid_t nb_ports; /**< Number of probed ethernet ports. */\nstruct fwd_lcore **fwd_lcores; /**< For all probed logical cores. */\nlcoreid_t nb_lcores; /**< Number of probed logical cores. */\n\n/*\n * Test Forwarding Configuration.\n * nb_fwd_lcores <= nb_cfg_lcores <= nb_lcores\n * nb_fwd_ports <= nb_cfg_ports <= nb_ports\n */\nlcoreid_t nb_cfg_lcores; /**< Number of configured logical cores. */\nlcoreid_t nb_fwd_lcores; /**< Number of forwarding logical cores. */\nportid_t nb_cfg_ports; /**< Number of configured ports. */\nportid_t nb_fwd_ports; /**< Number of forwarding ports. */\n\nunsigned int fwd_lcores_cpuids[RTE_MAX_LCORE]; /**< CPU ids configuration. */\nportid_t fwd_ports_ids[RTE_MAX_ETHPORTS]; /**< Port ids configuration. */\n\nstruct fwd_stream **fwd_streams; /**< For each RX queue of each port. */\nstreamid_t nb_fwd_streams; /**< Is equal to (nb_ports * nb_rxq). */\n\n/*\n * Forwarding engines.\n */\nstruct fwd_engine * fwd_engines[] = {\n\t&io_fwd_engine,\n\t&mac_fwd_engine,\n\t&mac_retry_fwd_engine,\n\t&mac_swap_engine,\n\t&flow_gen_engine,\n\t&rx_only_engine,\n\t&tx_only_engine,\n\t&csum_fwd_engine,\n\t&icmp_echo_engine,\n#ifdef RTE_LIBRTE_IEEE1588\n\t&ieee1588_fwd_engine,\n#endif\n\tNULL,\n};\n\nstruct fwd_config cur_fwd_config;\nstruct fwd_engine *cur_fwd_eng = &io_fwd_engine; /**< IO mode by default. */\n\nuint16_t mbuf_data_size = DEFAULT_MBUF_DATA_SIZE; /**< Mbuf data space size. */\nuint32_t param_total_num_mbufs = 0; /**< number of mbufs in all pools - if\n * specified on command-line. */\n\n/*\n * Configuration of packet segments used by the \"txonly\" processing engine.\n */\nuint16_t tx_pkt_length = TXONLY_DEF_PACKET_LEN; /**< TXONLY packet length. */\nuint16_t tx_pkt_seg_lengths[RTE_MAX_SEGS_PER_PKT] = {\n\tTXONLY_DEF_PACKET_LEN,\n};\nuint8_t tx_pkt_nb_segs = 1; /**< Number of segments in TXONLY packets */\n\nuint16_t nb_pkt_per_burst = DEF_PKT_BURST; /**< Number of packets per burst. */\nuint16_t mb_mempool_cache = DEF_MBUF_CACHE; /**< Size of mbuf mempool cache. */\n\n/* current configuration is in DCB or not,0 means it is not in DCB mode */\nuint8_t dcb_config = 0;\n\n/* Whether the dcb is in testing status */\nuint8_t dcb_test = 0;\n\n/* DCB on and VT on mapping is default */\nenum dcb_queue_mapping_mode dcb_q_mapping = DCB_VT_Q_MAPPING;\n\n/*\n * Configurable number of RX/TX queues.\n */\nqueueid_t nb_rxq = 1; /**< Number of RX queues per port. */\nqueueid_t nb_txq = 1; /**< Number of TX queues per port. */\n\n/*\n * Configurable number of RX/TX ring descriptors.\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nuint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT; /**< Number of RX descriptors. */\nuint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT; /**< Number of TX descriptors. */\n\n#define RTE_PMD_PARAM_UNSET -1\n/*\n * Configurable values of RX and TX ring threshold registers.\n */\n\nint8_t rx_pthresh = RTE_PMD_PARAM_UNSET;\nint8_t rx_hthresh = RTE_PMD_PARAM_UNSET;\nint8_t rx_wthresh = RTE_PMD_PARAM_UNSET;\n\nint8_t tx_pthresh = RTE_PMD_PARAM_UNSET;\nint8_t tx_hthresh = RTE_PMD_PARAM_UNSET;\nint8_t tx_wthresh = RTE_PMD_PARAM_UNSET;\n\n/*\n * Configurable value of RX free threshold.\n */\nint16_t rx_free_thresh = RTE_PMD_PARAM_UNSET;\n\n/*\n * Configurable value of RX drop enable.\n */\nint8_t rx_drop_en = RTE_PMD_PARAM_UNSET;\n\n/*\n * Configurable value of TX free threshold.\n */\nint16_t tx_free_thresh = RTE_PMD_PARAM_UNSET;\n\n/*\n * Configurable value of TX RS bit threshold.\n */\nint16_t tx_rs_thresh = RTE_PMD_PARAM_UNSET;\n\n/*\n * Configurable value of TX queue flags.\n */\nint32_t txq_flags = RTE_PMD_PARAM_UNSET;\n\n/*\n * Receive Side Scaling (RSS) configuration.\n */\nuint64_t rss_hf = ETH_RSS_IP; /* RSS IP by default. */\n\n/*\n * Port topology configuration\n */\nuint16_t port_topology = PORT_TOPOLOGY_PAIRED; /* Ports are paired by default */\n\n/*\n * Avoids to flush all the RX streams before starts forwarding.\n */\nuint8_t no_flush_rx = 0; /* flush by default */\n\n/*\n * Avoids to check link status when starting/stopping a port.\n */\nuint8_t no_link_check = 0; /* check by default */\n\n/*\n * NIC bypass mode configuration options.\n */\n#ifdef RTE_NIC_BYPASS\n\n/* The NIC bypass watchdog timeout. */\nuint32_t bypass_timeout = RTE_BYPASS_TMT_OFF;\n\n#endif\n\n/*\n * Ethernet device configuration.\n */\nstruct rte_eth_rxmode rx_mode = {\n\t.max_rx_pkt_len = ETHER_MAX_LEN, /**< Default maximum frame length. */\n\t.split_hdr_size = 0,\n\t.header_split = 0, /**< Header Split disabled. */\n\t.hw_ip_checksum = 0, /**< IP checksum offload disabled. */\n\t.hw_vlan_filter = 1, /**< VLAN filtering enabled. */\n\t.hw_vlan_strip = 1, /**< VLAN strip enabled. */\n\t.hw_vlan_extend = 0, /**< Extended VLAN disabled. */\n\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled. */\n\t.hw_strip_crc = 0, /**< CRC stripping by hardware disabled. */\n};\n\nstruct rte_fdir_conf fdir_conf = {\n\t.mode = RTE_FDIR_MODE_NONE,\n\t.pballoc = RTE_FDIR_PBALLOC_64K,\n\t.status = RTE_FDIR_REPORT_STATUS,\n\t.mask = {\n\t\t.vlan_tci_mask = 0x0,\n\t\t.ipv4_mask = {\n\t\t\t.src_ip = 0xFFFFFFFF,\n\t\t\t.dst_ip = 0xFFFFFFFF,\n\t\t},\n\t\t.ipv6_mask = {\n\t\t\t.src_ip = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},\n\t\t\t.dst_ip = {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},\n\t\t},\n\t\t.src_port_mask = 0xFFFF,\n\t\t.dst_port_mask = 0xFFFF,\n\t},\n\t.drop_queue = 127,\n};\n\nvolatile int test_done = 1; /* stop packet forwarding when set to 1. */\n\nstruct queue_stats_mappings tx_queue_stats_mappings_array[MAX_TX_QUEUE_STATS_MAPPINGS];\nstruct queue_stats_mappings rx_queue_stats_mappings_array[MAX_RX_QUEUE_STATS_MAPPINGS];\n\nstruct queue_stats_mappings *tx_queue_stats_mappings = tx_queue_stats_mappings_array;\nstruct queue_stats_mappings *rx_queue_stats_mappings = rx_queue_stats_mappings_array;\n\nuint16_t nb_tx_queue_stats_mappings = 0;\nuint16_t nb_rx_queue_stats_mappings = 0;\n\n/* Forward function declarations */\nstatic void map_port_queue_stats_mapping_registers(uint8_t pi, struct rte_port *port);\nstatic void check_all_ports_link_status(uint32_t port_mask);\n\n/*\n * Check if all the ports are started.\n * If yes, return positive value. If not, return zero.\n */\nstatic int all_ports_started(void);\n\n/*\n * Find next enabled port\n */\nportid_t\nfind_next_port(portid_t p, struct rte_port *ports, int size)\n{\n\tif (ports == NULL)\n\t\trte_exit(-EINVAL, \"failed to find a next port id\\n\");\n\n\twhile ((p < size) && (ports[p].enabled == 0))\n\t\tp++;\n\treturn p;\n}\n\n/*\n * Setup default configuration.\n */\nstatic void\nset_default_fwd_lcores_config(void)\n{\n\tunsigned int i;\n\tunsigned int nb_lc;\n\n\tnb_lc = 0;\n\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n\t\tif (! rte_lcore_is_enabled(i))\n\t\t\tcontinue;\n\t\tif (i == rte_get_master_lcore())\n\t\t\tcontinue;\n\t\tfwd_lcores_cpuids[nb_lc++] = i;\n\t}\n\tnb_lcores = (lcoreid_t) nb_lc;\n\tnb_cfg_lcores = nb_lcores;\n\tnb_fwd_lcores = 1;\n}\n\nstatic void\nset_def_peer_eth_addrs(void)\n{\n\tportid_t i;\n\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tpeer_eth_addrs[i].addr_bytes[0] = ETHER_LOCAL_ADMIN_ADDR;\n\t\tpeer_eth_addrs[i].addr_bytes[5] = i;\n\t}\n}\n\nstatic void\nset_default_fwd_ports_config(void)\n{\n\tportid_t pt_id;\n\n\tfor (pt_id = 0; pt_id < nb_ports; pt_id++)\n\t\tfwd_ports_ids[pt_id] = pt_id;\n\n\tnb_cfg_ports = nb_ports;\n\tnb_fwd_ports = nb_ports;\n}\n\nvoid\nset_def_fwd_config(void)\n{\n\tset_default_fwd_lcores_config();\n\tset_def_peer_eth_addrs();\n\tset_default_fwd_ports_config();\n}\n\n/*\n * Configuration initialisation done once at init time.\n */\nstatic void\nmbuf_pool_create(uint16_t mbuf_seg_size, unsigned nb_mbuf,\n\t\t unsigned int socket_id)\n{\n\tchar pool_name[RTE_MEMPOOL_NAMESIZE];\n\tstruct rte_mempool *rte_mp;\n\tuint32_t mb_size;\n\n\tmb_size = sizeof(struct rte_mbuf) + mbuf_seg_size;\n\tmbuf_poolname_build(socket_id, pool_name, sizeof(pool_name));\n\n#ifdef RTE_LIBRTE_PMD_XENVIRT\n\trte_mp = rte_mempool_gntalloc_create(pool_name, nb_mbuf, mb_size,\n\t\t(unsigned) mb_mempool_cache,\n\t\tsizeof(struct rte_pktmbuf_pool_private),\n\t\trte_pktmbuf_pool_init, NULL,\n\t\trte_pktmbuf_init, NULL,\n\t\tsocket_id, 0);\n\n\n\n#else\n\tif (mp_anon != 0)\n\t\trte_mp = mempool_anon_create(pool_name, nb_mbuf, mb_size,\n\t\t\t\t (unsigned) mb_mempool_cache,\n\t\t\t\t sizeof(struct rte_pktmbuf_pool_private),\n\t\t\t\t rte_pktmbuf_pool_init, NULL,\n\t\t\t\t rte_pktmbuf_init, NULL,\n\t\t\t\t socket_id, 0);\n\telse\n\t\t/* wrapper to rte_mempool_create() */\n\t\trte_mp = rte_pktmbuf_pool_create(pool_name, nb_mbuf,\n\t\t\tmb_mempool_cache, 0, mbuf_seg_size, socket_id);\n\n#endif\n\n\tif (rte_mp == NULL) {\n\t\trte_exit(EXIT_FAILURE, \"Creation of mbuf pool for socket %u \"\n\t\t\t\t\t\t\"failed\\n\", socket_id);\n\t} else if (verbose_level > 0) {\n\t\trte_mempool_dump(stdout, rte_mp);\n\t}\n}\n\n/*\n * Check given socket id is valid or not with NUMA mode,\n * if valid, return 0, else return -1\n */\nstatic int\ncheck_socket_id(const unsigned int socket_id)\n{\n\tstatic int warning_once = 0;\n\n\tif (socket_id >= MAX_SOCKET) {\n\t\tif (!warning_once && numa_support)\n\t\t\tprintf(\"Warning: NUMA should be configured manually by\"\n\t\t\t \" using --port-numa-config and\"\n\t\t\t \" --ring-numa-config parameters along with\"\n\t\t\t \" --numa.\\n\");\n\t\twarning_once = 1;\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic void\ninit_config(void)\n{\n\tportid_t pid;\n\tstruct rte_port *port;\n\tstruct rte_mempool *mbp;\n\tunsigned int nb_mbuf_per_pool;\n\tlcoreid_t lc_id;\n\tuint8_t port_per_socket[MAX_SOCKET];\n\n\tmemset(port_per_socket,0,MAX_SOCKET);\n\t/* Configuration of logical cores. */\n\tfwd_lcores = rte_zmalloc(\"testpmd: fwd_lcores\",\n\t\t\t\tsizeof(struct fwd_lcore *) * nb_lcores,\n\t\t\t\tRTE_CACHE_LINE_SIZE);\n\tif (fwd_lcores == NULL) {\n\t\trte_exit(EXIT_FAILURE, \"rte_zmalloc(%d (struct fwd_lcore *)) \"\n\t\t\t\t\t\t\t\"failed\\n\", nb_lcores);\n\t}\n\tfor (lc_id = 0; lc_id < nb_lcores; lc_id++) {\n\t\tfwd_lcores[lc_id] = rte_zmalloc(\"testpmd: struct fwd_lcore\",\n\t\t\t\t\t sizeof(struct fwd_lcore),\n\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n\t\tif (fwd_lcores[lc_id] == NULL) {\n\t\t\trte_exit(EXIT_FAILURE, \"rte_zmalloc(struct fwd_lcore) \"\n\t\t\t\t\t\t\t\t\"failed\\n\");\n\t\t}\n\t\tfwd_lcores[lc_id]->cpuid_idx = lc_id;\n\t}\n\n\t/*\n\t * Create pools of mbuf.\n\t * If NUMA support is disabled, create a single pool of mbuf in\n\t * socket 0 memory by default.\n\t * Otherwise, create a pool of mbuf in the memory of sockets 0 and 1.\n\t *\n\t * Use the maximum value of nb_rxd and nb_txd here, then nb_rxd and\n\t * nb_txd can be configured at run time.\n\t */\n\tif (param_total_num_mbufs)\n\t\tnb_mbuf_per_pool = param_total_num_mbufs;\n\telse {\n\t\tnb_mbuf_per_pool = RTE_TEST_RX_DESC_MAX + (nb_lcores * mb_mempool_cache)\n\t\t\t\t+ RTE_TEST_TX_DESC_MAX + MAX_PKT_BURST;\n\n\t\tif (!numa_support)\n\t\t\tnb_mbuf_per_pool =\n\t\t\t\t(nb_mbuf_per_pool * RTE_MAX_ETHPORTS);\n\t}\n\n\tif (!numa_support) {\n\t\tif (socket_num == UMA_NO_CONFIG)\n\t\t\tmbuf_pool_create(mbuf_data_size, nb_mbuf_per_pool, 0);\n\t\telse\n\t\t\tmbuf_pool_create(mbuf_data_size, nb_mbuf_per_pool,\n\t\t\t\t\t\t socket_num);\n\t}\n\n\tFOREACH_PORT(pid, ports) {\n\t\tport = &ports[pid];\n\t\trte_eth_dev_info_get(pid, &port->dev_info);\n\n\t\tif (numa_support) {\n\t\t\tif (port_numa[pid] != NUMA_NO_CONFIG)\n\t\t\t\tport_per_socket[port_numa[pid]]++;\n\t\t\telse {\n\t\t\t\tuint32_t socket_id = rte_eth_dev_socket_id(pid);\n\n\t\t\t\t/* if socket_id is invalid, set to 0 */\n\t\t\t\tif (check_socket_id(socket_id) < 0)\n\t\t\t\t\tsocket_id = 0;\n\t\t\t\tport_per_socket[socket_id]++;\n\t\t\t}\n\t\t}\n\n\t\t/* set flag to initialize port/queue */\n\t\tport->need_reconfig = 1;\n\t\tport->need_reconfig_queues = 1;\n\t}\n\n\tif (numa_support) {\n\t\tuint8_t i;\n\t\tunsigned int nb_mbuf;\n\n\t\tif (param_total_num_mbufs)\n\t\t\tnb_mbuf_per_pool = nb_mbuf_per_pool/nb_ports;\n\n\t\tfor (i = 0; i < MAX_SOCKET; i++) {\n\t\t\tnb_mbuf = (nb_mbuf_per_pool * RTE_MAX_ETHPORTS);\n\t\t\tif (nb_mbuf)\n\t\t\t\tmbuf_pool_create(mbuf_data_size,\n\t\t\t\t\t\tnb_mbuf,i);\n\t\t}\n\t}\n\tinit_port_config();\n\n\t/*\n\t * Records which Mbuf pool to use by each logical core, if needed.\n\t */\n\tfor (lc_id = 0; lc_id < nb_lcores; lc_id++) {\n\t\tmbp = mbuf_pool_find(\n\t\t\trte_lcore_to_socket_id(fwd_lcores_cpuids[lc_id]));\n\n\t\tif (mbp == NULL)\n\t\t\tmbp = mbuf_pool_find(0);\n\t\tfwd_lcores[lc_id]->mbp = mbp;\n\t}\n\n\t/* Configuration of packet forwarding streams. */\n\tif (init_fwd_streams() < 0)\n\t\trte_exit(EXIT_FAILURE, \"FAIL from init_fwd_streams()\\n\");\n}\n\n\nvoid\nreconfig(portid_t new_port_id, unsigned socket_id)\n{\n\tstruct rte_port *port;\n\n\t/* Reconfiguration of Ethernet ports. */\n\tport = &ports[new_port_id];\n\trte_eth_dev_info_get(new_port_id, &port->dev_info);\n\n\t/* set flag to initialize port/queue */\n\tport->need_reconfig = 1;\n\tport->need_reconfig_queues = 1;\n\tport->socket_id = socket_id;\n\n\tinit_port_config();\n}\n\n\nint\ninit_fwd_streams(void)\n{\n\tportid_t pid;\n\tstruct rte_port *port;\n\tstreamid_t sm_id, nb_fwd_streams_new;\n\n\t/* set socket id according to numa or not */\n\tFOREACH_PORT(pid, ports) {\n\t\tport = &ports[pid];\n\t\tif (nb_rxq > port->dev_info.max_rx_queues) {\n\t\t\tprintf(\"Fail: nb_rxq(%d) is greater than \"\n\t\t\t\t\"max_rx_queues(%d)\\n\", nb_rxq,\n\t\t\t\tport->dev_info.max_rx_queues);\n\t\t\treturn -1;\n\t\t}\n\t\tif (nb_txq > port->dev_info.max_tx_queues) {\n\t\t\tprintf(\"Fail: nb_txq(%d) is greater than \"\n\t\t\t\t\"max_tx_queues(%d)\\n\", nb_txq,\n\t\t\t\tport->dev_info.max_tx_queues);\n\t\t\treturn -1;\n\t\t}\n\t\tif (numa_support) {\n\t\t\tif (port_numa[pid] != NUMA_NO_CONFIG)\n\t\t\t\tport->socket_id = port_numa[pid];\n\t\t\telse {\n\t\t\t\tport->socket_id = rte_eth_dev_socket_id(pid);\n\n\t\t\t\t/* if socket_id is invalid, set to 0 */\n\t\t\t\tif (check_socket_id(port->socket_id) < 0)\n\t\t\t\t\tport->socket_id = 0;\n\t\t\t}\n\t\t}\n\t\telse {\n\t\t\tif (socket_num == UMA_NO_CONFIG)\n\t\t\t\tport->socket_id = 0;\n\t\t\telse\n\t\t\t\tport->socket_id = socket_num;\n\t\t}\n\t}\n\n\tnb_fwd_streams_new = (streamid_t)(nb_ports * nb_rxq);\n\tif (nb_fwd_streams_new == nb_fwd_streams)\n\t\treturn 0;\n\t/* clear the old */\n\tif (fwd_streams != NULL) {\n\t\tfor (sm_id = 0; sm_id < nb_fwd_streams; sm_id++) {\n\t\t\tif (fwd_streams[sm_id] == NULL)\n\t\t\t\tcontinue;\n\t\t\trte_free(fwd_streams[sm_id]);\n\t\t\tfwd_streams[sm_id] = NULL;\n\t\t}\n\t\trte_free(fwd_streams);\n\t\tfwd_streams = NULL;\n\t}\n\n\t/* init new */\n\tnb_fwd_streams = nb_fwd_streams_new;\n\tfwd_streams = rte_zmalloc(\"testpmd: fwd_streams\",\n\t\tsizeof(struct fwd_stream *) * nb_fwd_streams, RTE_CACHE_LINE_SIZE);\n\tif (fwd_streams == NULL)\n\t\trte_exit(EXIT_FAILURE, \"rte_zmalloc(%d (struct fwd_stream *)) \"\n\t\t\t\t\t\t\"failed\\n\", nb_fwd_streams);\n\n\tfor (sm_id = 0; sm_id < nb_fwd_streams; sm_id++) {\n\t\tfwd_streams[sm_id] = rte_zmalloc(\"testpmd: struct fwd_stream\",\n\t\t\t\tsizeof(struct fwd_stream), RTE_CACHE_LINE_SIZE);\n\t\tif (fwd_streams[sm_id] == NULL)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_zmalloc(struct fwd_stream)\"\n\t\t\t\t\t\t\t\t\" failed\\n\");\n\t}\n\n\treturn 0;\n}\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\nstatic void\npkt_burst_stats_display(const char *rx_tx, struct pkt_burst_stats *pbs)\n{\n\tunsigned int total_burst;\n\tunsigned int nb_burst;\n\tunsigned int burst_stats[3];\n\tuint16_t pktnb_stats[3];\n\tuint16_t nb_pkt;\n\tint burst_percent[3];\n\n\t/*\n\t * First compute the total number of packet bursts and the\n\t * two highest numbers of bursts of the same number of packets.\n\t */\n\ttotal_burst = 0;\n\tburst_stats[0] = burst_stats[1] = burst_stats[2] = 0;\n\tpktnb_stats[0] = pktnb_stats[1] = pktnb_stats[2] = 0;\n\tfor (nb_pkt = 0; nb_pkt < MAX_PKT_BURST; nb_pkt++) {\n\t\tnb_burst = pbs->pkt_burst_spread[nb_pkt];\n\t\tif (nb_burst == 0)\n\t\t\tcontinue;\n\t\ttotal_burst += nb_burst;\n\t\tif (nb_burst > burst_stats[0]) {\n\t\t\tburst_stats[1] = burst_stats[0];\n\t\t\tpktnb_stats[1] = pktnb_stats[0];\n\t\t\tburst_stats[0] = nb_burst;\n\t\t\tpktnb_stats[0] = nb_pkt;\n\t\t}\n\t}\n\tif (total_burst == 0)\n\t\treturn;\n\tburst_percent[0] = (burst_stats[0] * 100) / total_burst;\n\tprintf(\" %s-bursts : %u [%d%% of %d pkts\", rx_tx, total_burst,\n\t burst_percent[0], (int) pktnb_stats[0]);\n\tif (burst_stats[0] == total_burst) {\n\t\tprintf(\"]\\n\");\n\t\treturn;\n\t}\n\tif (burst_stats[0] + burst_stats[1] == total_burst) {\n\t\tprintf(\" + %d%% of %d pkts]\\n\",\n\t\t 100 - burst_percent[0], pktnb_stats[1]);\n\t\treturn;\n\t}\n\tburst_percent[1] = (burst_stats[1] * 100) / total_burst;\n\tburst_percent[2] = 100 - (burst_percent[0] + burst_percent[1]);\n\tif ((burst_percent[1] == 0) || (burst_percent[2] == 0)) {\n\t\tprintf(\" + %d%% of others]\\n\", 100 - burst_percent[0]);\n\t\treturn;\n\t}\n\tprintf(\" + %d%% of %d pkts + %d%% of others]\\n\",\n\t burst_percent[1], (int) pktnb_stats[1], burst_percent[2]);\n}\n#endif /* RTE_TEST_PMD_RECORD_BURST_STATS */\n\nstatic void\nfwd_port_stats_display(portid_t port_id, struct rte_eth_stats *stats)\n{\n\tstruct rte_port *port;\n\tuint8_t i;\n\n\tstatic const char *fwd_stats_border = \"----------------------\";\n\n\tport = &ports[port_id];\n\tprintf(\"\\n %s Forward statistics for port %-2d %s\\n\",\n\t fwd_stats_border, port_id, fwd_stats_border);\n\n\tif ((!port->rx_queue_stats_mapping_enabled) && (!port->tx_queue_stats_mapping_enabled)) {\n\t\tprintf(\" RX-packets: %-14\"PRIu64\" RX-dropped: %-14\"PRIu64\"RX-total: \"\n\t\t \"%-\"PRIu64\"\\n\",\n\t\t stats->ipackets, stats->imissed,\n\t\t (uint64_t) (stats->ipackets + stats->imissed));\n\n\t\tif (cur_fwd_eng == &csum_fwd_engine)\n\t\t\tprintf(\" Bad-ipcsum: %-14\"PRIu64\" Bad-l4csum: %-14\"PRIu64\" \\n\",\n\t\t\t port->rx_bad_ip_csum, port->rx_bad_l4_csum);\n\t\tif (((stats->ierrors - stats->imissed) + stats->rx_nombuf) > 0) {\n\t\t\tprintf(\" RX-badcrc: %-14\"PRIu64\" RX-badlen: %-14\"PRIu64\n\t\t\t \"RX-error: %-\"PRIu64\"\\n\",\n\t\t\t stats->ibadcrc, stats->ibadlen, stats->ierrors);\n\t\t\tprintf(\" RX-nombufs: %-14\"PRIu64\"\\n\", stats->rx_nombuf);\n\t\t}\n\n\t\tprintf(\" TX-packets: %-14\"PRIu64\" TX-dropped: %-14\"PRIu64\"TX-total: \"\n\t\t \"%-\"PRIu64\"\\n\",\n\t\t stats->opackets, port->tx_dropped,\n\t\t (uint64_t) (stats->opackets + port->tx_dropped));\n\t}\n\telse {\n\t\tprintf(\" RX-packets: %14\"PRIu64\" RX-dropped:%14\"PRIu64\" RX-total:\"\n\t\t \"%14\"PRIu64\"\\n\",\n\t\t stats->ipackets, stats->imissed,\n\t\t (uint64_t) (stats->ipackets + stats->imissed));\n\n\t\tif (cur_fwd_eng == &csum_fwd_engine)\n\t\t\tprintf(\" Bad-ipcsum:%14\"PRIu64\" Bad-l4csum:%14\"PRIu64\"\\n\",\n\t\t\t port->rx_bad_ip_csum, port->rx_bad_l4_csum);\n\t\tif (((stats->ierrors - stats->imissed) + stats->rx_nombuf) > 0) {\n\t\t\tprintf(\" RX-badcrc: %14\"PRIu64\" RX-badlen: %14\"PRIu64\n\t\t\t \" RX-error:%\"PRIu64\"\\n\",\n\t\t\t stats->ibadcrc, stats->ibadlen, stats->ierrors);\n\t\t\tprintf(\" RX-nombufs: %14\"PRIu64\"\\n\",\n\t\t\t stats->rx_nombuf);\n\t\t}\n\n\t\tprintf(\" TX-packets: %14\"PRIu64\" TX-dropped:%14\"PRIu64\" TX-total:\"\n\t\t \"%14\"PRIu64\"\\n\",\n\t\t stats->opackets, port->tx_dropped,\n\t\t (uint64_t) (stats->opackets + port->tx_dropped));\n\t}\n\n\t/* Display statistics of XON/XOFF pause frames, if any. */\n\tif ((stats->tx_pause_xon | stats->rx_pause_xon |\n\t stats->tx_pause_xoff | stats->rx_pause_xoff) > 0) {\n\t\tprintf(\" RX-XOFF: %-14\"PRIu64\" RX-XON: %-14\"PRIu64\"\\n\",\n\t\t stats->rx_pause_xoff, stats->rx_pause_xon);\n\t\tprintf(\" TX-XOFF: %-14\"PRIu64\" TX-XON: %-14\"PRIu64\"\\n\",\n\t\t stats->tx_pause_xoff, stats->tx_pause_xon);\n\t}\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tif (port->rx_stream)\n\t\tpkt_burst_stats_display(\"RX\",\n\t\t\t&port->rx_stream->rx_burst_stats);\n\tif (port->tx_stream)\n\t\tpkt_burst_stats_display(\"TX\",\n\t\t\t&port->tx_stream->tx_burst_stats);\n#endif\n\t/* stats fdir */\n\tif (fdir_conf.mode != RTE_FDIR_MODE_NONE)\n\t\tprintf(\" Fdirmiss:%14\"PRIu64\"\t Fdirmatch:%14\"PRIu64\"\\n\",\n\t\t stats->fdirmiss,\n\t\t stats->fdirmatch);\n\n\tif (port->rx_queue_stats_mapping_enabled) {\n\t\tprintf(\"\\n\");\n\t\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) {\n\t\t\tprintf(\" Stats reg %2d RX-packets:%14\"PRIu64\n\t\t\t \" RX-errors:%14\"PRIu64\n\t\t\t \" RX-bytes:%14\"PRIu64\"\\n\",\n\t\t\t i, stats->q_ipackets[i], stats->q_errors[i], stats->q_ibytes[i]);\n\t\t}\n\t\tprintf(\"\\n\");\n\t}\n\tif (port->tx_queue_stats_mapping_enabled) {\n\t\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) {\n\t\t\tprintf(\" Stats reg %2d TX-packets:%14\"PRIu64\n\t\t\t \" TX-bytes:%14\"PRIu64\"\\n\",\n\t\t\t i, stats->q_opackets[i], stats->q_obytes[i]);\n\t\t}\n\t}\n\n\tprintf(\" %s--------------------------------%s\\n\",\n\t fwd_stats_border, fwd_stats_border);\n}\n\nstatic void\nfwd_stream_stats_display(streamid_t stream_id)\n{\n\tstruct fwd_stream *fs;\n\tstatic const char *fwd_top_stats_border = \"-------\";\n\n\tfs = fwd_streams[stream_id];\n\tif ((fs->rx_packets == 0) && (fs->tx_packets == 0) &&\n\t (fs->fwd_dropped == 0))\n\t\treturn;\n\tprintf(\"\\n %s Forward Stats for RX Port=%2d/Queue=%2d -> \"\n\t \"TX Port=%2d/Queue=%2d %s\\n\",\n\t fwd_top_stats_border, fs->rx_port, fs->rx_queue,\n\t fs->tx_port, fs->tx_queue, fwd_top_stats_border);\n\tprintf(\" RX-packets: %-14u TX-packets: %-14u TX-dropped: %-14u\",\n\t fs->rx_packets, fs->tx_packets, fs->fwd_dropped);\n\n\t/* if checksum mode */\n\tif (cur_fwd_eng == &csum_fwd_engine) {\n\t printf(\" RX- bad IP checksum: %-14u Rx- bad L4 checksum: \"\n\t\t\t\"%-14u\\n\", fs->rx_bad_ip_csum, fs->rx_bad_l4_csum);\n\t}\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tpkt_burst_stats_display(\"RX\", &fs->rx_burst_stats);\n\tpkt_burst_stats_display(\"TX\", &fs->tx_burst_stats);\n#endif\n}\n\nstatic void\nflush_fwd_rx_queues(void)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tportid_t rxp;\n\tportid_t port_id;\n\tqueueid_t rxq;\n\tuint16_t nb_rx;\n\tuint16_t i;\n\tuint8_t j;\n\n\tfor (j = 0; j < 2; j++) {\n\t\tfor (rxp = 0; rxp < cur_fwd_config.nb_fwd_ports; rxp++) {\n\t\t\tfor (rxq = 0; rxq < nb_rxq; rxq++) {\n\t\t\t\tport_id = fwd_ports_ids[rxp];\n\t\t\t\tdo {\n\t\t\t\t\tnb_rx = rte_eth_rx_burst(port_id, rxq,\n\t\t\t\t\t\tpkts_burst, MAX_PKT_BURST);\n\t\t\t\t\tfor (i = 0; i < nb_rx; i++)\n\t\t\t\t\t\trte_pktmbuf_free(pkts_burst[i]);\n\t\t\t\t} while (nb_rx > 0);\n\t\t\t}\n\t\t}\n\t\trte_delay_ms(10); /* wait 10 milli-seconds before retrying */\n\t}\n}\n\nstatic void\nrun_pkt_fwd_on_lcore(struct fwd_lcore *fc, packet_fwd_t pkt_fwd)\n{\n\tstruct fwd_stream **fsm;\n\tstreamid_t nb_fs;\n\tstreamid_t sm_id;\n\n\tfsm = &fwd_streams[fc->stream_idx];\n\tnb_fs = fc->stream_nb;\n\tdo {\n\t\tfor (sm_id = 0; sm_id < nb_fs; sm_id++)\n\t\t\t(*pkt_fwd)(fsm[sm_id]);\n\t} while (! fc->stopped);\n}\n\nstatic int\nstart_pkt_forward_on_core(void *fwd_arg)\n{\n\trun_pkt_fwd_on_lcore((struct fwd_lcore *) fwd_arg,\n\t\t\t cur_fwd_config.fwd_eng->packet_fwd);\n\treturn 0;\n}\n\n/*\n * Run the TXONLY packet forwarding engine to send a single burst of packets.\n * Used to start communication flows in network loopback test configurations.\n */\nstatic int\nrun_one_txonly_burst_on_core(void *fwd_arg)\n{\n\tstruct fwd_lcore *fwd_lc;\n\tstruct fwd_lcore tmp_lcore;\n\n\tfwd_lc = (struct fwd_lcore *) fwd_arg;\n\ttmp_lcore = *fwd_lc;\n\ttmp_lcore.stopped = 1;\n\trun_pkt_fwd_on_lcore(&tmp_lcore, tx_only_engine.packet_fwd);\n\treturn 0;\n}\n\n/*\n * Launch packet forwarding:\n * - Setup per-port forwarding context.\n * - launch logical cores with their forwarding configuration.\n */\nstatic void\nlaunch_packet_forwarding(lcore_function_t *pkt_fwd_on_lcore)\n{\n\tport_fwd_begin_t port_fwd_begin;\n\tunsigned int i;\n\tunsigned int lc_id;\n\tint diag;\n\n\tport_fwd_begin = cur_fwd_config.fwd_eng->port_fwd_begin;\n\tif (port_fwd_begin != NULL) {\n\t\tfor (i = 0; i < cur_fwd_config.nb_fwd_ports; i++)\n\t\t\t(*port_fwd_begin)(fwd_ports_ids[i]);\n\t}\n\tfor (i = 0; i < cur_fwd_config.nb_fwd_lcores; i++) {\n\t\tlc_id = fwd_lcores_cpuids[i];\n\t\tif ((interactive == 0) || (lc_id != rte_lcore_id())) {\n\t\t\tfwd_lcores[i]->stopped = 0;\n\t\t\tdiag = rte_eal_remote_launch(pkt_fwd_on_lcore,\n\t\t\t\t\t\t fwd_lcores[i], lc_id);\n\t\t\tif (diag != 0)\n\t\t\t\tprintf(\"launch lcore %u failed - diag=%d\\n\",\n\t\t\t\t lc_id, diag);\n\t\t}\n\t}\n}\n\n/*\n * Launch packet forwarding configuration.\n */\nvoid\nstart_packet_forwarding(int with_tx_first)\n{\n\tport_fwd_begin_t port_fwd_begin;\n\tport_fwd_end_t port_fwd_end;\n\tstruct rte_port *port;\n\tunsigned int i;\n\tportid_t pt_id;\n\tstreamid_t sm_id;\n\n\tif (all_ports_started() == 0) {\n\t\tprintf(\"Not all ports were started\\n\");\n\t\treturn;\n\t}\n\tif (test_done == 0) {\n\t\tprintf(\"Packet forwarding already started\\n\");\n\t\treturn;\n\t}\n\tif(dcb_test) {\n\t\tfor (i = 0; i < nb_fwd_ports; i++) {\n\t\t\tpt_id = fwd_ports_ids[i];\n\t\t\tport = &ports[pt_id];\n\t\t\tif (!port->dcb_flag) {\n\t\t\t\tprintf(\"In DCB mode, all forwarding ports must \"\n \"be configured in this mode.\\n\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\t\tif (nb_fwd_lcores == 1) {\n\t\t\tprintf(\"In DCB mode,the nb forwarding cores \"\n \"should be larger than 1.\\n\");\n\t\t\treturn;\n\t\t}\n\t}\n\ttest_done = 0;\n\n\tif(!no_flush_rx)\n\t\tflush_fwd_rx_queues();\n\n\tfwd_config_setup();\n\trxtx_config_display();\n\n\tfor (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) {\n\t\tpt_id = fwd_ports_ids[i];\n\t\tport = &ports[pt_id];\n\t\trte_eth_stats_get(pt_id, &port->stats);\n\t\tport->tx_dropped = 0;\n\n\t\tmap_port_queue_stats_mapping_registers(pt_id, port);\n\t}\n\tfor (sm_id = 0; sm_id < cur_fwd_config.nb_fwd_streams; sm_id++) {\n\t\tfwd_streams[sm_id]->rx_packets = 0;\n\t\tfwd_streams[sm_id]->tx_packets = 0;\n\t\tfwd_streams[sm_id]->fwd_dropped = 0;\n\t\tfwd_streams[sm_id]->rx_bad_ip_csum = 0;\n\t\tfwd_streams[sm_id]->rx_bad_l4_csum = 0;\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\t\tmemset(&fwd_streams[sm_id]->rx_burst_stats, 0,\n\t\t sizeof(fwd_streams[sm_id]->rx_burst_stats));\n\t\tmemset(&fwd_streams[sm_id]->tx_burst_stats, 0,\n\t\t sizeof(fwd_streams[sm_id]->tx_burst_stats));\n#endif\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\t\tfwd_streams[sm_id]->core_cycles = 0;\n#endif\n\t}\n\tif (with_tx_first) {\n\t\tport_fwd_begin = tx_only_engine.port_fwd_begin;\n\t\tif (port_fwd_begin != NULL) {\n\t\t\tfor (i = 0; i < cur_fwd_config.nb_fwd_ports; i++)\n\t\t\t\t(*port_fwd_begin)(fwd_ports_ids[i]);\n\t\t}\n\t\tlaunch_packet_forwarding(run_one_txonly_burst_on_core);\n\t\trte_eal_mp_wait_lcore();\n\t\tport_fwd_end = tx_only_engine.port_fwd_end;\n\t\tif (port_fwd_end != NULL) {\n\t\t\tfor (i = 0; i < cur_fwd_config.nb_fwd_ports; i++)\n\t\t\t\t(*port_fwd_end)(fwd_ports_ids[i]);\n\t\t}\n\t}\n\tlaunch_packet_forwarding(start_pkt_forward_on_core);\n}\n\nvoid\nstop_packet_forwarding(void)\n{\n\tstruct rte_eth_stats stats;\n\tstruct rte_port *port;\n\tport_fwd_end_t port_fwd_end;\n\tint i;\n\tportid_t pt_id;\n\tstreamid_t sm_id;\n\tlcoreid_t lc_id;\n\tuint64_t total_recv;\n\tuint64_t total_xmit;\n\tuint64_t total_rx_dropped;\n\tuint64_t total_tx_dropped;\n\tuint64_t total_rx_nombuf;\n\tuint64_t tx_dropped;\n\tuint64_t rx_bad_ip_csum;\n\tuint64_t rx_bad_l4_csum;\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tuint64_t fwd_cycles;\n#endif\n\tstatic const char *acc_stats_border = \"+++++++++++++++\";\n\n\tif (all_ports_started() == 0) {\n\t\tprintf(\"Not all ports were started\\n\");\n\t\treturn;\n\t}\n\tif (test_done) {\n\t\tprintf(\"Packet forwarding not started\\n\");\n\t\treturn;\n\t}\n\tprintf(\"Telling cores to stop...\");\n\tfor (lc_id = 0; lc_id < cur_fwd_config.nb_fwd_lcores; lc_id++)\n\t\tfwd_lcores[lc_id]->stopped = 1;\n\tprintf(\"\\nWaiting for lcores to finish...\\n\");\n\trte_eal_mp_wait_lcore();\n\tport_fwd_end = cur_fwd_config.fwd_eng->port_fwd_end;\n\tif (port_fwd_end != NULL) {\n\t\tfor (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) {\n\t\t\tpt_id = fwd_ports_ids[i];\n\t\t\t(*port_fwd_end)(pt_id);\n\t\t}\n\t}\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tfwd_cycles = 0;\n#endif\n\tfor (sm_id = 0; sm_id < cur_fwd_config.nb_fwd_streams; sm_id++) {\n\t\tif (cur_fwd_config.nb_fwd_streams >\n\t\t cur_fwd_config.nb_fwd_ports) {\n\t\t\tfwd_stream_stats_display(sm_id);\n\t\t\tports[fwd_streams[sm_id]->tx_port].tx_stream = NULL;\n\t\t\tports[fwd_streams[sm_id]->rx_port].rx_stream = NULL;\n\t\t} else {\n\t\t\tports[fwd_streams[sm_id]->tx_port].tx_stream =\n\t\t\t\tfwd_streams[sm_id];\n\t\t\tports[fwd_streams[sm_id]->rx_port].rx_stream =\n\t\t\t\tfwd_streams[sm_id];\n\t\t}\n\t\ttx_dropped = ports[fwd_streams[sm_id]->tx_port].tx_dropped;\n\t\ttx_dropped = (uint64_t) (tx_dropped +\n\t\t\t\t\t fwd_streams[sm_id]->fwd_dropped);\n\t\tports[fwd_streams[sm_id]->tx_port].tx_dropped = tx_dropped;\n\n\t\trx_bad_ip_csum =\n\t\t\tports[fwd_streams[sm_id]->rx_port].rx_bad_ip_csum;\n\t\trx_bad_ip_csum = (uint64_t) (rx_bad_ip_csum +\n\t\t\t\t\t fwd_streams[sm_id]->rx_bad_ip_csum);\n\t\tports[fwd_streams[sm_id]->rx_port].rx_bad_ip_csum =\n\t\t\t\t\t\t\trx_bad_ip_csum;\n\n\t\trx_bad_l4_csum =\n\t\t\tports[fwd_streams[sm_id]->rx_port].rx_bad_l4_csum;\n\t\trx_bad_l4_csum = (uint64_t) (rx_bad_l4_csum +\n\t\t\t\t\t fwd_streams[sm_id]->rx_bad_l4_csum);\n\t\tports[fwd_streams[sm_id]->rx_port].rx_bad_l4_csum =\n\t\t\t\t\t\t\trx_bad_l4_csum;\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\t\tfwd_cycles = (uint64_t) (fwd_cycles +\n\t\t\t\t\t fwd_streams[sm_id]->core_cycles);\n#endif\n\t}\n\ttotal_recv = 0;\n\ttotal_xmit = 0;\n\ttotal_rx_dropped = 0;\n\ttotal_tx_dropped = 0;\n\ttotal_rx_nombuf = 0;\n\tfor (i = 0; i < cur_fwd_config.nb_fwd_ports; i++) {\n\t\tpt_id = fwd_ports_ids[i];\n\n\t\tport = &ports[pt_id];\n\t\trte_eth_stats_get(pt_id, &stats);\n\t\tstats.ipackets -= port->stats.ipackets;\n\t\tport->stats.ipackets = 0;\n\t\tstats.opackets -= port->stats.opackets;\n\t\tport->stats.opackets = 0;\n\t\tstats.ibytes -= port->stats.ibytes;\n\t\tport->stats.ibytes = 0;\n\t\tstats.obytes -= port->stats.obytes;\n\t\tport->stats.obytes = 0;\n\t\tstats.imissed -= port->stats.imissed;\n\t\tport->stats.imissed = 0;\n\t\tstats.oerrors -= port->stats.oerrors;\n\t\tport->stats.oerrors = 0;\n\t\tstats.rx_nombuf -= port->stats.rx_nombuf;\n\t\tport->stats.rx_nombuf = 0;\n\t\tstats.fdirmatch -= port->stats.fdirmatch;\n\t\tport->stats.rx_nombuf = 0;\n\t\tstats.fdirmiss -= port->stats.fdirmiss;\n\t\tport->stats.rx_nombuf = 0;\n\n\t\ttotal_recv += stats.ipackets;\n\t\ttotal_xmit += stats.opackets;\n\t\ttotal_rx_dropped += stats.imissed;\n\t\ttotal_tx_dropped += port->tx_dropped;\n\t\ttotal_rx_nombuf += stats.rx_nombuf;\n\n\t\tfwd_port_stats_display(pt_id, &stats);\n\t}\n\tprintf(\"\\n %s Accumulated forward statistics for all ports\"\n\t \"%s\\n\",\n\t acc_stats_border, acc_stats_border);\n\tprintf(\" RX-packets: %-14\"PRIu64\" RX-dropped: %-14\"PRIu64\"RX-total: \"\n\t \"%-\"PRIu64\"\\n\"\n\t \" TX-packets: %-14\"PRIu64\" TX-dropped: %-14\"PRIu64\"TX-total: \"\n\t \"%-\"PRIu64\"\\n\",\n\t total_recv, total_rx_dropped, total_recv + total_rx_dropped,\n\t total_xmit, total_tx_dropped, total_xmit + total_tx_dropped);\n\tif (total_rx_nombuf > 0)\n\t\tprintf(\" RX-nombufs: %-14\"PRIu64\"\\n\", total_rx_nombuf);\n\tprintf(\" %s++++++++++++++++++++++++++++++++++++++++++++++\"\n\t \"%s\\n\",\n\t acc_stats_border, acc_stats_border);\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tif (total_recv > 0)\n\t\tprintf(\"\\n CPU cycles/packet=%u (total cycles=\"\n\t\t \"%\"PRIu64\" / total RX packets=%\"PRIu64\")\\n\",\n\t\t (unsigned int)(fwd_cycles / total_recv),\n\t\t fwd_cycles, total_recv);\n#endif\n\tprintf(\"\\nDone.\\n\");\n\ttest_done = 1;\n}\n\nvoid\ndev_set_link_up(portid_t pid)\n{\n\tif (rte_eth_dev_set_link_up((uint8_t)pid) < 0)\n\t\tprintf(\"\\nSet link up fail.\\n\");\n}\n\nvoid\ndev_set_link_down(portid_t pid)\n{\n\tif (rte_eth_dev_set_link_down((uint8_t)pid) < 0)\n\t\tprintf(\"\\nSet link down fail.\\n\");\n}\n\nstatic int\nall_ports_started(void)\n{\n\tportid_t pi;\n\tstruct rte_port *port;\n\n\tFOREACH_PORT(pi, ports) {\n\t\tport = &ports[pi];\n\t\t/* Check if there is a port which is not started */\n\t\tif ((port->port_status != RTE_PORT_STARTED) &&\n\t\t\t(port->slave_flag == 0))\n\t\t\treturn 0;\n\t}\n\n\t/* No port is not started */\n\treturn 1;\n}\n\nint\nall_ports_stopped(void)\n{\n\tportid_t pi;\n\tstruct rte_port *port;\n\n\tFOREACH_PORT(pi, ports) {\n\t\tport = &ports[pi];\n\t\tif ((port->port_status != RTE_PORT_STOPPED) &&\n\t\t\t(port->slave_flag == 0))\n\t\t\treturn 0;\n\t}\n\n\treturn 1;\n}\n\nint\nport_is_started(portid_t port_id)\n{\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn 0;\n\n\tif (ports[port_id].port_status != RTE_PORT_STARTED)\n\t\treturn 0;\n\n\treturn 1;\n}\n\nstatic int\nport_is_closed(portid_t port_id)\n{\n\tif (port_id_is_invalid(port_id, ENABLED_WARN))\n\t\treturn 0;\n\n\tif (ports[port_id].port_status != RTE_PORT_CLOSED)\n\t\treturn 0;\n\n\treturn 1;\n}\n\nint\nstart_port(portid_t pid)\n{\n\tint diag, need_check_link_status = -1;\n\tportid_t pi;\n\tqueueid_t qi;\n\tstruct rte_port *port;\n\tstruct ether_addr mac_addr;\n\n\tif (test_done == 0) {\n\t\tprintf(\"Please stop forwarding first\\n\");\n\t\treturn -1;\n\t}\n\n\tif (port_id_is_invalid(pid, ENABLED_WARN))\n\t\treturn 0;\n\n\tif (init_fwd_streams() < 0) {\n\t\tprintf(\"Fail from init_fwd_streams()\\n\");\n\t\treturn -1;\n\t}\n\n\tif(dcb_config)\n\t\tdcb_test = 1;\n\tFOREACH_PORT(pi, ports) {\n\t\tif (pid != pi && pid != (portid_t)RTE_PORT_ALL)\n\t\t\tcontinue;\n\n\t\tneed_check_link_status = 0;\n\t\tport = &ports[pi];\n\t\tif (rte_atomic16_cmpset(&(port->port_status), RTE_PORT_STOPPED,\n\t\t\t\t\t\t RTE_PORT_HANDLING) == 0) {\n\t\t\tprintf(\"Port %d is now not stopped\\n\", pi);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (port->need_reconfig > 0) {\n\t\t\tport->need_reconfig = 0;\n\n\t\t\tprintf(\"Configuring Port %d (socket %u)\\n\", pi,\n\t\t\t\t\tport->socket_id);\n\t\t\t/* configure port */\n\t\t\tdiag = rte_eth_dev_configure(pi, nb_rxq, nb_txq,\n\t\t\t\t\t\t&(port->dev_conf));\n\t\t\tif (diag != 0) {\n\t\t\t\tif (rte_atomic16_cmpset(&(port->port_status),\n\t\t\t\tRTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0)\n\t\t\t\t\tprintf(\"Port %d can not be set back \"\n\t\t\t\t\t\t\t\"to stopped\\n\", pi);\n\t\t\t\tprintf(\"Fail to configure port %d\\n\", pi);\n\t\t\t\t/* try to reconfigure port next time */\n\t\t\t\tport->need_reconfig = 1;\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t\tif (port->need_reconfig_queues > 0) {\n\t\t\tport->need_reconfig_queues = 0;\n\t\t\t/* setup tx queues */\n\t\t\tfor (qi = 0; qi < nb_txq; qi++) {\n\t\t\t\tif ((numa_support) &&\n\t\t\t\t\t(txring_numa[pi] != NUMA_NO_CONFIG))\n\t\t\t\t\tdiag = rte_eth_tx_queue_setup(pi, qi,\n\t\t\t\t\t\tnb_txd,txring_numa[pi],\n\t\t\t\t\t\t&(port->tx_conf));\n\t\t\t\telse\n\t\t\t\t\tdiag = rte_eth_tx_queue_setup(pi, qi,\n\t\t\t\t\t\tnb_txd,port->socket_id,\n\t\t\t\t\t\t&(port->tx_conf));\n\n\t\t\t\tif (diag == 0)\n\t\t\t\t\tcontinue;\n\n\t\t\t\t/* Fail to setup tx queue, return */\n\t\t\t\tif (rte_atomic16_cmpset(&(port->port_status),\n\t\t\t\t\t\t\tRTE_PORT_HANDLING,\n\t\t\t\t\t\t\tRTE_PORT_STOPPED) == 0)\n\t\t\t\t\tprintf(\"Port %d can not be set back \"\n\t\t\t\t\t\t\t\"to stopped\\n\", pi);\n\t\t\t\tprintf(\"Fail to configure port %d tx queues\\n\", pi);\n\t\t\t\t/* try to reconfigure queues next time */\n\t\t\t\tport->need_reconfig_queues = 1;\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\t/* setup rx queues */\n\t\t\tfor (qi = 0; qi < nb_rxq; qi++) {\n\t\t\t\tif ((numa_support) &&\n\t\t\t\t\t(rxring_numa[pi] != NUMA_NO_CONFIG)) {\n\t\t\t\t\tstruct rte_mempool * mp =\n\t\t\t\t\t\tmbuf_pool_find(rxring_numa[pi]);\n\t\t\t\t\tif (mp == NULL) {\n\t\t\t\t\t\tprintf(\"Failed to setup RX queue:\"\n\t\t\t\t\t\t\t\"No mempool allocation\"\n\t\t\t\t\t\t\t\"on the socket %d\\n\",\n\t\t\t\t\t\t\trxring_numa[pi]);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\n\t\t\t\t\tdiag = rte_eth_rx_queue_setup(pi, qi,\n\t\t\t\t\t nb_rxd,rxring_numa[pi],\n\t\t\t\t\t &(port->rx_conf),mp);\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t\tdiag = rte_eth_rx_queue_setup(pi, qi,\n\t\t\t\t\t nb_rxd,port->socket_id,\n\t\t\t\t\t &(port->rx_conf),\n\t\t\t\t mbuf_pool_find(port->socket_id));\n\n\t\t\t\tif (diag == 0)\n\t\t\t\t\tcontinue;\n\n\n\t\t\t\t/* Fail to setup rx queue, return */\n\t\t\t\tif (rte_atomic16_cmpset(&(port->port_status),\n\t\t\t\t\t\t\tRTE_PORT_HANDLING,\n\t\t\t\t\t\t\tRTE_PORT_STOPPED) == 0)\n\t\t\t\t\tprintf(\"Port %d can not be set back \"\n\t\t\t\t\t\t\t\"to stopped\\n\", pi);\n\t\t\t\tprintf(\"Fail to configure port %d rx queues\\n\", pi);\n\t\t\t\t/* try to reconfigure queues next time */\n\t\t\t\tport->need_reconfig_queues = 1;\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t\t/* start port */\n\t\tif (rte_eth_dev_start(pi) < 0) {\n\t\t\tprintf(\"Fail to start port %d\\n\", pi);\n\n\t\t\t/* Fail to setup rx queue, return */\n\t\t\tif (rte_atomic16_cmpset(&(port->port_status),\n\t\t\t\tRTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0)\n\t\t\t\tprintf(\"Port %d can not be set back to \"\n\t\t\t\t\t\t\t\"stopped\\n\", pi);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (rte_atomic16_cmpset(&(port->port_status),\n\t\t\tRTE_PORT_HANDLING, RTE_PORT_STARTED) == 0)\n\t\t\tprintf(\"Port %d can not be set into started\\n\", pi);\n\n\t\trte_eth_macaddr_get(pi, &mac_addr);\n\t\tprintf(\"Port %d: %02X:%02X:%02X:%02X:%02X:%02X\\n\", pi,\n\t\t\t\tmac_addr.addr_bytes[0], mac_addr.addr_bytes[1],\n\t\t\t\tmac_addr.addr_bytes[2], mac_addr.addr_bytes[3],\n\t\t\t\tmac_addr.addr_bytes[4], mac_addr.addr_bytes[5]);\n\n\t\t/* at least one port started, need checking link status */\n\t\tneed_check_link_status = 1;\n\t}\n\n\tif (need_check_link_status == 1 && !no_link_check)\n\t\tcheck_all_ports_link_status(RTE_PORT_ALL);\n\telse if (need_check_link_status == 0)\n\t\tprintf(\"Please stop the ports first\\n\");\n\n\tprintf(\"Done\\n\");\n\treturn 0;\n}\n\nvoid\nstop_port(portid_t pid)\n{\n\tportid_t pi;\n\tstruct rte_port *port;\n\tint need_check_link_status = 0;\n\n\tif (test_done == 0) {\n\t\tprintf(\"Please stop forwarding first\\n\");\n\t\treturn;\n\t}\n\tif (dcb_test) {\n\t\tdcb_test = 0;\n\t\tdcb_config = 0;\n\t}\n\n\tif (port_id_is_invalid(pid, ENABLED_WARN))\n\t\treturn;\n\n\tprintf(\"Stopping ports...\\n\");\n\n\tFOREACH_PORT(pi, ports) {\n\t\tif (pid != pi && pid != (portid_t)RTE_PORT_ALL)\n\t\t\tcontinue;\n\n\t\tport = &ports[pi];\n\t\tif (rte_atomic16_cmpset(&(port->port_status), RTE_PORT_STARTED,\n\t\t\t\t\t\tRTE_PORT_HANDLING) == 0)\n\t\t\tcontinue;\n\n\t\trte_eth_dev_stop(pi);\n\n\t\tif (rte_atomic16_cmpset(&(port->port_status),\n\t\t\tRTE_PORT_HANDLING, RTE_PORT_STOPPED) == 0)\n\t\t\tprintf(\"Port %d can not be set into stopped\\n\", pi);\n\t\tneed_check_link_status = 1;\n\t}\n\tif (need_check_link_status && !no_link_check)\n\t\tcheck_all_ports_link_status(RTE_PORT_ALL);\n\n\tprintf(\"Done\\n\");\n}\n\nvoid\nclose_port(portid_t pid)\n{\n\tportid_t pi;\n\tstruct rte_port *port;\n\n\tif (test_done == 0) {\n\t\tprintf(\"Please stop forwarding first\\n\");\n\t\treturn;\n\t}\n\n\tif (port_id_is_invalid(pid, ENABLED_WARN))\n\t\treturn;\n\n\tprintf(\"Closing ports...\\n\");\n\n\tFOREACH_PORT(pi, ports) {\n\t\tif (pid != pi && pid != (portid_t)RTE_PORT_ALL)\n\t\t\tcontinue;\n\n\t\tport = &ports[pi];\n\t\tif (rte_atomic16_cmpset(&(port->port_status),\n\t\t\tRTE_PORT_CLOSED, RTE_PORT_CLOSED) == 1) {\n\t\t\tprintf(\"Port %d is already closed\\n\", pi);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (rte_atomic16_cmpset(&(port->port_status),\n\t\t\tRTE_PORT_STOPPED, RTE_PORT_HANDLING) == 0) {\n\t\t\tprintf(\"Port %d is now not stopped\\n\", pi);\n\t\t\tcontinue;\n\t\t}\n\n\t\trte_eth_dev_close(pi);\n\n\t\tif (rte_atomic16_cmpset(&(port->port_status),\n\t\t\tRTE_PORT_HANDLING, RTE_PORT_CLOSED) == 0)\n\t\t\tprintf(\"Port %d can not be set into stopped\\n\", pi);\n\t}\n\n\tprintf(\"Done\\n\");\n}\n\nvoid\nattach_port(char *identifier)\n{\n\tportid_t i, j, pi = 0;\n\n\tprintf(\"Attaching a new port...\\n\");\n\n\tif (identifier == NULL) {\n\t\tprintf(\"Invalid parameters are specified\\n\");\n\t\treturn;\n\t}\n\n\tif (test_done == 0) {\n\t\tprintf(\"Please stop forwarding first\\n\");\n\t\treturn;\n\t}\n\n\tif (rte_eth_dev_attach(identifier, &pi))\n\t\treturn;\n\n\tports[pi].enabled = 1;\n\treconfig(pi, rte_eth_dev_socket_id(pi));\n\trte_eth_promiscuous_enable(pi);\n\n\tnb_ports = rte_eth_dev_count();\n\n\t/* set_default_fwd_ports_config(); */\n\tbzero(fwd_ports_ids, sizeof(fwd_ports_ids));\n\ti = 0;\n\tFOREACH_PORT(j, ports) {\n\t\tfwd_ports_ids[i] = j;\n\t\ti++;\n\t}\n\tnb_cfg_ports = nb_ports;\n\tnb_fwd_ports++;\n\n\tports[pi].port_status = RTE_PORT_STOPPED;\n\n\tprintf(\"Port %d is attached. Now total ports is %d\\n\", pi, nb_ports);\n\tprintf(\"Done\\n\");\n}\n\nvoid\ndetach_port(uint8_t port_id)\n{\n\tportid_t i, pi = 0;\n\tchar name[RTE_ETH_NAME_MAX_LEN];\n\n\tprintf(\"Detaching a port...\\n\");\n\n\tif (!port_is_closed(port_id)) {\n\t\tprintf(\"Please close port first\\n\");\n\t\treturn;\n\t}\n\n\tif (rte_eth_dev_detach(port_id, name))\n\t\treturn;\n\n\tports[port_id].enabled = 0;\n\tnb_ports = rte_eth_dev_count();\n\n\t/* set_default_fwd_ports_config(); */\n\tbzero(fwd_ports_ids, sizeof(fwd_ports_ids));\n\ti = 0;\n\tFOREACH_PORT(pi, ports) {\n\t\tfwd_ports_ids[i] = pi;\n\t\ti++;\n\t}\n\tnb_cfg_ports = nb_ports;\n\tnb_fwd_ports--;\n\n\tprintf(\"Port '%s' is detached. Now total ports is %d\\n\",\n\t\t\tname, nb_ports);\n\tprintf(\"Done\\n\");\n\treturn;\n}\n\nvoid\npmd_test_exit(void)\n{\n\tportid_t pt_id;\n\n\tif (test_done == 0)\n\t\tstop_packet_forwarding();\n\n\tFOREACH_PORT(pt_id, ports) {\n\t\tprintf(\"Stopping port %d...\", pt_id);\n\t\tfflush(stdout);\n\t\trte_eth_dev_close(pt_id);\n\t\tprintf(\"done\\n\");\n\t}\n\tprintf(\"bye...\\n\");\n}\n\ntypedef void (*cmd_func_t)(void);\nstruct pmd_test_command {\n\tconst char *cmd_name;\n\tcmd_func_t cmd_func;\n};\n\n#define PMD_TEST_CMD_NB (sizeof(pmd_test_menu) / sizeof(pmd_test_menu[0]))\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"Checking link statuses...\\n\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tFOREACH_PORT(portid, ports) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t}\n\t}\n}\n\nstatic int\nset_tx_queue_stats_mapping_registers(uint8_t port_id, struct rte_port *port)\n{\n\tuint16_t i;\n\tint diag;\n\tuint8_t mapping_found = 0;\n\n\tfor (i = 0; i < nb_tx_queue_stats_mappings; i++) {\n\t\tif ((tx_queue_stats_mappings[i].port_id == port_id) &&\n\t\t\t\t(tx_queue_stats_mappings[i].queue_id < nb_txq )) {\n\t\t\tdiag = rte_eth_dev_set_tx_queue_stats_mapping(port_id,\n\t\t\t\t\ttx_queue_stats_mappings[i].queue_id,\n\t\t\t\t\ttx_queue_stats_mappings[i].stats_counter_id);\n\t\t\tif (diag != 0)\n\t\t\t\treturn diag;\n\t\t\tmapping_found = 1;\n\t\t}\n\t}\n\tif (mapping_found)\n\t\tport->tx_queue_stats_mapping_enabled = 1;\n\treturn 0;\n}\n\nstatic int\nset_rx_queue_stats_mapping_registers(uint8_t port_id, struct rte_port *port)\n{\n\tuint16_t i;\n\tint diag;\n\tuint8_t mapping_found = 0;\n\n\tfor (i = 0; i < nb_rx_queue_stats_mappings; i++) {\n\t\tif ((rx_queue_stats_mappings[i].port_id == port_id) &&\n\t\t\t\t(rx_queue_stats_mappings[i].queue_id < nb_rxq )) {\n\t\t\tdiag = rte_eth_dev_set_rx_queue_stats_mapping(port_id,\n\t\t\t\t\trx_queue_stats_mappings[i].queue_id,\n\t\t\t\t\trx_queue_stats_mappings[i].stats_counter_id);\n\t\t\tif (diag != 0)\n\t\t\t\treturn diag;\n\t\t\tmapping_found = 1;\n\t\t}\n\t}\n\tif (mapping_found)\n\t\tport->rx_queue_stats_mapping_enabled = 1;\n\treturn 0;\n}\n\nstatic void\nmap_port_queue_stats_mapping_registers(uint8_t pi, struct rte_port *port)\n{\n\tint diag = 0;\n\n\tdiag = set_tx_queue_stats_mapping_registers(pi, port);\n\tif (diag != 0) {\n\t\tif (diag == -ENOTSUP) {\n\t\t\tport->tx_queue_stats_mapping_enabled = 0;\n\t\t\tprintf(\"TX queue stats mapping not supported port id=%d\\n\", pi);\n\t\t}\n\t\telse\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\"set_tx_queue_stats_mapping_registers \"\n\t\t\t\t\t\"failed for port id=%d diag=%d\\n\",\n\t\t\t\t\tpi, diag);\n\t}\n\n\tdiag = set_rx_queue_stats_mapping_registers(pi, port);\n\tif (diag != 0) {\n\t\tif (diag == -ENOTSUP) {\n\t\t\tport->rx_queue_stats_mapping_enabled = 0;\n\t\t\tprintf(\"RX queue stats mapping not supported port id=%d\\n\", pi);\n\t\t}\n\t\telse\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\"set_rx_queue_stats_mapping_registers \"\n\t\t\t\t\t\"failed for port id=%d diag=%d\\n\",\n\t\t\t\t\tpi, diag);\n\t}\n}\n\nstatic void\nrxtx_port_config(struct rte_port *port)\n{\n\tport->rx_conf = port->dev_info.default_rxconf;\n\tport->tx_conf = port->dev_info.default_txconf;\n\n\t/* Check if any RX/TX parameters have been passed */\n\tif (rx_pthresh != RTE_PMD_PARAM_UNSET)\n\t\tport->rx_conf.rx_thresh.pthresh = rx_pthresh;\n\n\tif (rx_hthresh != RTE_PMD_PARAM_UNSET)\n\t\tport->rx_conf.rx_thresh.hthresh = rx_hthresh;\n\n\tif (rx_wthresh != RTE_PMD_PARAM_UNSET)\n\t\tport->rx_conf.rx_thresh.wthresh = rx_wthresh;\n\n\tif (rx_free_thresh != RTE_PMD_PARAM_UNSET)\n\t\tport->rx_conf.rx_free_thresh = rx_free_thresh;\n\n\tif (rx_drop_en != RTE_PMD_PARAM_UNSET)\n\t\tport->rx_conf.rx_drop_en = rx_drop_en;\n\n\tif (tx_pthresh != RTE_PMD_PARAM_UNSET)\n\t\tport->tx_conf.tx_thresh.pthresh = tx_pthresh;\n\n\tif (tx_hthresh != RTE_PMD_PARAM_UNSET)\n\t\tport->tx_conf.tx_thresh.hthresh = tx_hthresh;\n\n\tif (tx_wthresh != RTE_PMD_PARAM_UNSET)\n\t\tport->tx_conf.tx_thresh.wthresh = tx_wthresh;\n\n\tif (tx_rs_thresh != RTE_PMD_PARAM_UNSET)\n\t\tport->tx_conf.tx_rs_thresh = tx_rs_thresh;\n\n\tif (tx_free_thresh != RTE_PMD_PARAM_UNSET)\n\t\tport->tx_conf.tx_free_thresh = tx_free_thresh;\n\n\tif (txq_flags != RTE_PMD_PARAM_UNSET)\n\t\tport->tx_conf.txq_flags = txq_flags;\n}\n\nvoid\ninit_port_config(void)\n{\n\tportid_t pid;\n\tstruct rte_port *port;\n\n\tFOREACH_PORT(pid, ports) {\n\t\tport = &ports[pid];\n\t\tport->dev_conf.rxmode = rx_mode;\n\t\tport->dev_conf.fdir_conf = fdir_conf;\n\t\tif (nb_rxq > 1) {\n\t\t\tport->dev_conf.rx_adv_conf.rss_conf.rss_key = NULL;\n\t\t\tport->dev_conf.rx_adv_conf.rss_conf.rss_hf = rss_hf;\n\t\t} else {\n\t\t\tport->dev_conf.rx_adv_conf.rss_conf.rss_key = NULL;\n\t\t\tport->dev_conf.rx_adv_conf.rss_conf.rss_hf = 0;\n\t\t}\n\n\t\tif (port->dcb_flag == 0 && port->dev_info.max_vfs == 0) {\n\t\t\tif( port->dev_conf.rx_adv_conf.rss_conf.rss_hf != 0)\n\t\t\t\tport->dev_conf.rxmode.mq_mode = ETH_MQ_RX_RSS;\n\t\t\telse\n\t\t\t\tport->dev_conf.rxmode.mq_mode = ETH_MQ_RX_NONE;\n\t\t}\n\n\t\tif (port->dev_info.max_vfs != 0) {\n\t\t\tif (port->dev_conf.rx_adv_conf.rss_conf.rss_hf != 0)\n\t\t\t\tport->dev_conf.rxmode.mq_mode =\n\t\t\t\t\tETH_MQ_RX_VMDQ_RSS;\n\t\t\telse\n\t\t\t\tport->dev_conf.rxmode.mq_mode =\n\t\t\t\t\tETH_MQ_RX_NONE;\n\n\t\t\tport->dev_conf.txmode.mq_mode = ETH_MQ_TX_NONE;\n\t\t}\n\n\t\trxtx_port_config(port);\n\n\t\trte_eth_macaddr_get(pid, &port->eth_addr);\n\n\t\tmap_port_queue_stats_mapping_registers(pid, port);\n#ifdef RTE_NIC_BYPASS\n\t\trte_eth_dev_bypass_init(pid);\n#endif\n\t}\n}\n\nvoid set_port_slave_flag(portid_t slave_pid)\n{\n\tstruct rte_port *port;\n\n\tport = &ports[slave_pid];\n\tport->slave_flag = 1;\n}\n\nvoid clear_port_slave_flag(portid_t slave_pid)\n{\n\tstruct rte_port *port;\n\n\tport = &ports[slave_pid];\n\tport->slave_flag = 0;\n}\n\nconst uint16_t vlan_tags[] = {\n\t\t0, 1, 2, 3, 4, 5, 6, 7,\n\t\t8, 9, 10, 11, 12, 13, 14, 15,\n\t\t16, 17, 18, 19, 20, 21, 22, 23,\n\t\t24, 25, 26, 27, 28, 29, 30, 31\n};\n\nstatic int\nget_eth_dcb_conf(struct rte_eth_conf *eth_conf, struct dcb_config *dcb_conf)\n{\n uint8_t i;\n\n\t/*\n\t * Builds up the correct configuration for dcb+vt based on the vlan tags array\n\t * given above, and the number of traffic classes available for use.\n\t */\n\tif (dcb_conf->dcb_mode == DCB_VT_ENABLED) {\n\t\tstruct rte_eth_vmdq_dcb_conf vmdq_rx_conf;\n\t\tstruct rte_eth_vmdq_dcb_tx_conf vmdq_tx_conf;\n\n\t\t/* VMDQ+DCB RX and TX configrations */\n\t\tvmdq_rx_conf.enable_default_pool = 0;\n\t\tvmdq_rx_conf.default_pool = 0;\n\t\tvmdq_rx_conf.nb_queue_pools =\n\t\t\t(dcb_conf->num_tcs == ETH_4_TCS ? ETH_32_POOLS : ETH_16_POOLS);\n\t\tvmdq_tx_conf.nb_queue_pools =\n\t\t\t(dcb_conf->num_tcs == ETH_4_TCS ? ETH_32_POOLS : ETH_16_POOLS);\n\n\t\tvmdq_rx_conf.nb_pool_maps = sizeof( vlan_tags )/sizeof( vlan_tags[ 0 ]);\n\t\tfor (i = 0; i < vmdq_rx_conf.nb_pool_maps; i++) {\n\t\t\tvmdq_rx_conf.pool_map[i].vlan_id = vlan_tags[ i ];\n\t\t\tvmdq_rx_conf.pool_map[i].pools = 1 << (i % vmdq_rx_conf.nb_queue_pools);\n\t\t}\n\t\tfor (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {\n\t\t\tvmdq_rx_conf.dcb_queue[i] = i;\n\t\t\tvmdq_tx_conf.dcb_queue[i] = i;\n\t\t}\n\n\t\t/*set DCB mode of RX and TX of multiple queues*/\n\t\teth_conf->rxmode.mq_mode = ETH_MQ_RX_VMDQ_DCB;\n\t\teth_conf->txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;\n\t\tif (dcb_conf->pfc_en)\n\t\t\teth_conf->dcb_capability_en = ETH_DCB_PG_SUPPORT|ETH_DCB_PFC_SUPPORT;\n\t\telse\n\t\t\teth_conf->dcb_capability_en = ETH_DCB_PG_SUPPORT;\n\n\t\t(void)(rte_memcpy(ð_conf->rx_adv_conf.vmdq_dcb_conf, &vmdq_rx_conf,\n sizeof(struct rte_eth_vmdq_dcb_conf)));\n\t\t(void)(rte_memcpy(ð_conf->tx_adv_conf.vmdq_dcb_tx_conf, &vmdq_tx_conf,\n sizeof(struct rte_eth_vmdq_dcb_tx_conf)));\n\t}\n\telse {\n\t\tstruct rte_eth_dcb_rx_conf rx_conf;\n\t\tstruct rte_eth_dcb_tx_conf tx_conf;\n\n\t\t/* queue mapping configuration of DCB RX and TX */\n\t\tif (dcb_conf->num_tcs == ETH_4_TCS)\n\t\t\tdcb_q_mapping = DCB_4_TCS_Q_MAPPING;\n\t\telse\n\t\t\tdcb_q_mapping = DCB_8_TCS_Q_MAPPING;\n\n\t\trx_conf.nb_tcs = dcb_conf->num_tcs;\n\t\ttx_conf.nb_tcs = dcb_conf->num_tcs;\n\n\t\tfor (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++){\n\t\t\trx_conf.dcb_queue[i] = i;\n\t\t\ttx_conf.dcb_queue[i] = i;\n\t\t}\n\t\teth_conf->rxmode.mq_mode = ETH_MQ_RX_DCB;\n\t\teth_conf->txmode.mq_mode = ETH_MQ_TX_DCB;\n\t\tif (dcb_conf->pfc_en)\n\t\t\teth_conf->dcb_capability_en = ETH_DCB_PG_SUPPORT|ETH_DCB_PFC_SUPPORT;\n\t\telse\n\t\t\teth_conf->dcb_capability_en = ETH_DCB_PG_SUPPORT;\n\n\t\t(void)(rte_memcpy(ð_conf->rx_adv_conf.dcb_rx_conf, &rx_conf,\n sizeof(struct rte_eth_dcb_rx_conf)));\n\t\t(void)(rte_memcpy(ð_conf->tx_adv_conf.dcb_tx_conf, &tx_conf,\n sizeof(struct rte_eth_dcb_tx_conf)));\n\t}\n\n\treturn 0;\n}\n\nint\ninit_port_dcb_config(portid_t pid,struct dcb_config *dcb_conf)\n{\n\tstruct rte_eth_conf port_conf;\n\tstruct rte_port *rte_port;\n\tint retval;\n\tuint16_t nb_vlan;\n\tuint16_t i;\n\n\t/* rxq and txq configuration in dcb mode */\n\tnb_rxq = 128;\n\tnb_txq = 128;\n\trx_free_thresh = 64;\n\n\tmemset(&port_conf,0,sizeof(struct rte_eth_conf));\n\t/* Enter DCB configuration status */\n\tdcb_config = 1;\n\n\tnb_vlan = sizeof( vlan_tags )/sizeof( vlan_tags[ 0 ]);\n\t/*set configuration of DCB in vt mode and DCB in non-vt mode*/\n\tretval = get_eth_dcb_conf(&port_conf, dcb_conf);\n\tif (retval < 0)\n\t\treturn retval;\n\n\trte_port = &ports[pid];\n\tmemcpy(&rte_port->dev_conf, &port_conf,sizeof(struct rte_eth_conf));\n\n\trxtx_port_config(rte_port);\n\t/* VLAN filter */\n\trte_port->dev_conf.rxmode.hw_vlan_filter = 1;\n\tfor (i = 0; i < nb_vlan; i++){\n\t\trx_vft_set(pid, vlan_tags[i], 1);\n\t}\n\n\trte_eth_macaddr_get(pid, &rte_port->eth_addr);\n\tmap_port_queue_stats_mapping_registers(pid, rte_port);\n\n\trte_port->dcb_flag = 1;\n\n\treturn 0;\n}\n\nstatic void\ninit_port(void)\n{\n\tportid_t pid;\n\n\t/* Configuration of Ethernet ports. */\n\tports = rte_zmalloc(\"testpmd: ports\",\n\t\t\t sizeof(struct rte_port) * RTE_MAX_ETHPORTS,\n\t\t\t RTE_CACHE_LINE_SIZE);\n\tif (ports == NULL) {\n\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"rte_zmalloc(%d struct rte_port) failed\\n\",\n\t\t\t\tRTE_MAX_ETHPORTS);\n\t}\n\n\t/* enabled allocated ports */\n\tfor (pid = 0; pid < nb_ports; pid++)\n\t\tports[pid].enabled = 1;\n}\n\nint\nmain(int argc, char** argv)\n{\n\tint diag;\n\tuint8_t port_id;\n\n\tdiag = rte_eal_init(argc, argv);\n\tif (diag < 0)\n\t\trte_panic(\"Cannot init EAL\\n\");\n\n\tnb_ports = (portid_t) rte_eth_dev_count();\n\tif (nb_ports == 0)\n\t\tRTE_LOG(WARNING, EAL, \"No probed ethernet devices\\n\");\n\n\t/* allocate port structures, and init them */\n\tinit_port();\n\n\tset_def_fwd_config();\n\tif (nb_lcores == 0)\n\t\trte_panic(\"Empty set of forwarding logical cores - check the \"\n\t\t\t \"core mask supplied in the command parameters\\n\");\n\n\targc -= diag;\n\targv += diag;\n\tif (argc > 1)\n\t\tlaunch_args_parse(argc, argv);\n\n\tif (nb_rxq > nb_txq)\n\t\tprintf(\"Warning: nb_rxq=%d enables RSS configuration, \"\n\t\t \"but nb_txq=%d will prevent to fully test it.\\n\",\n\t\t nb_rxq, nb_txq);\n\n\tinit_config();\n\tif (start_port(RTE_PORT_ALL) != 0)\n\t\trte_exit(EXIT_FAILURE, \"Start ports failed\\n\");\n\n\t/* set all ports to promiscuous mode by default */\n\tFOREACH_PORT(port_id, ports)\n\t\trte_eth_promiscuous_enable(port_id);\n\n#ifdef RTE_LIBRTE_CMDLINE\n\tif (interactive == 1) {\n\t\tif (auto_start) {\n\t\t\tprintf(\"Start automatic packet forwarding\\n\");\n\t\t\tstart_packet_forwarding(0);\n\t\t}\n\t\tprompt();\n\t} else\n#endif\n\t{\n\t\tchar c;\n\t\tint rc;\n\n\t\tprintf(\"No commandline core given, start packet forwarding\\n\");\n\t\tstart_packet_forwarding(0);\n\t\tprintf(\"Press enter to exit\\n\");\n\t\trc = read(0, &c, 1);\n\t\tif (rc < 0)\n\t\t\treturn 1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "app/test-pmd/testpmd.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _TESTPMD_H_\n#define _TESTPMD_H_\n\n#define RTE_PORT_ALL (~(portid_t)0x0)\n\n#define RTE_TEST_RX_DESC_MAX 2048\n#define RTE_TEST_TX_DESC_MAX 2048\n\n#define RTE_PORT_STOPPED (uint16_t)0\n#define RTE_PORT_STARTED (uint16_t)1\n#define RTE_PORT_CLOSED (uint16_t)2\n#define RTE_PORT_HANDLING (uint16_t)3\n\n/*\n * Default size of the mbuf data buffer to receive standard 1518-byte\n * Ethernet frames in a mono-segment memory buffer.\n */\n#define DEFAULT_MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE\n/**< Default size of mbuf data buffer. */\n\n/*\n * The maximum number of segments per packet is used when creating\n * scattered transmit packets composed of a list of mbufs.\n */\n#define RTE_MAX_SEGS_PER_PKT 255 /**< nb_segs is a 8-bit unsigned char. */\n\n#define MAX_PKT_BURST 512\n#define DEF_PKT_BURST 32\n\n#define DEF_MBUF_CACHE 250\n\n#define RTE_CACHE_LINE_SIZE_ROUNDUP(size) \\\n\t(RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))\n\n#define NUMA_NO_CONFIG 0xFF\n#define UMA_NO_CONFIG 0xFF\n\ntypedef uint8_t lcoreid_t;\ntypedef uint8_t portid_t;\ntypedef uint16_t queueid_t;\ntypedef uint16_t streamid_t;\n\n#define MAX_QUEUE_ID ((1 << (sizeof(queueid_t) * 8)) - 1)\n\nenum {\n\tPORT_TOPOLOGY_PAIRED,\n\tPORT_TOPOLOGY_CHAINED,\n\tPORT_TOPOLOGY_LOOP,\n};\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n/**\n * The data structure associated with RX and TX packet burst statistics\n * that are recorded for each forwarding stream.\n */\nstruct pkt_burst_stats {\n\tunsigned int pkt_burst_spread[MAX_PKT_BURST];\n};\n#endif\n\n/**\n * The data structure associated with a forwarding stream between a receive\n * port/queue and a transmit port/queue.\n */\nstruct fwd_stream {\n\t/* \"read-only\" data */\n\tportid_t rx_port; /**< port to poll for received packets */\n\tqueueid_t rx_queue; /**< RX queue to poll on \"rx_port\" */\n\tportid_t tx_port; /**< forwarding port of received packets */\n\tqueueid_t tx_queue; /**< TX queue to send forwarded packets */\n\tstreamid_t peer_addr; /**< index of peer ethernet address of packets */\n\n\t/* \"read-write\" results */\n\tunsigned int rx_packets; /**< received packets */\n\tunsigned int tx_packets; /**< received packets transmitted */\n\tunsigned int fwd_dropped; /**< received packets not forwarded */\n\tunsigned int rx_bad_ip_csum ; /**< received packets has bad ip checksum */\n\tunsigned int rx_bad_l4_csum ; /**< received packets has bad l4 checksum */\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tuint64_t core_cycles; /**< used for RX and TX processing */\n#endif\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tstruct pkt_burst_stats rx_burst_stats;\n\tstruct pkt_burst_stats tx_burst_stats;\n#endif\n};\n\n/** Offload IP checksum in csum forward engine */\n#define TESTPMD_TX_OFFLOAD_IP_CKSUM 0x0001\n/** Offload UDP checksum in csum forward engine */\n#define TESTPMD_TX_OFFLOAD_UDP_CKSUM 0x0002\n/** Offload TCP checksum in csum forward engine */\n#define TESTPMD_TX_OFFLOAD_TCP_CKSUM 0x0004\n/** Offload SCTP checksum in csum forward engine */\n#define TESTPMD_TX_OFFLOAD_SCTP_CKSUM 0x0008\n/** Offload outer IP checksum in csum forward engine for recognized tunnels */\n#define TESTPMD_TX_OFFLOAD_OUTER_IP_CKSUM 0x0010\n/** Parse tunnel in csum forward engine. If set, dissect tunnel headers\n * of rx packets. If not set, treat inner headers as payload. */\n#define TESTPMD_TX_OFFLOAD_PARSE_TUNNEL 0x0020\n/** Insert VLAN header in forward engine */\n#define TESTPMD_TX_OFFLOAD_INSERT_VLAN 0x0040\n/** Insert double VLAN header in forward engine */\n#define TESTPMD_TX_OFFLOAD_INSERT_QINQ 0x0080\n\n/**\n * The data structure associated with each port.\n */\nstruct rte_port {\n\tuint8_t enabled; /**< Port enabled or not */\n\tstruct rte_eth_dev_info dev_info; /**< PCI info + driver name */\n\tstruct rte_eth_conf dev_conf; /**< Port configuration. */\n\tstruct ether_addr eth_addr; /**< Port ethernet address */\n\tstruct rte_eth_stats stats; /**< Last port statistics */\n\tuint64_t tx_dropped; /**< If no descriptor in TX ring */\n\tstruct fwd_stream *rx_stream; /**< Port RX stream, if unique */\n\tstruct fwd_stream *tx_stream; /**< Port TX stream, if unique */\n\tunsigned int socket_id; /**< For NUMA support */\n\tuint16_t tx_ol_flags;/**< TX Offload Flags (TESTPMD_TX_OFFLOAD...). */\n\tuint16_t tso_segsz; /**< MSS for segmentation offload. */\n\tuint16_t tx_vlan_id;/**< The tag ID */\n\tuint16_t tx_vlan_id_outer;/**< The outer tag ID */\n\tvoid *fwd_ctx; /**< Forwarding mode context */\n\tuint64_t rx_bad_ip_csum; /**< rx pkts with bad ip checksum */\n\tuint64_t rx_bad_l4_csum; /**< rx pkts with bad l4 checksum */\n\tuint8_t tx_queue_stats_mapping_enabled;\n\tuint8_t rx_queue_stats_mapping_enabled;\n\tvolatile uint16_t port_status; /**< port started or not */\n\tuint8_t need_reconfig; /**< need reconfiguring port or not */\n\tuint8_t need_reconfig_queues; /**< need reconfiguring queues or not */\n\tuint8_t rss_flag; /**< enable rss or not */\n\tuint8_t dcb_flag; /**< enable dcb */\n\tstruct rte_eth_rxconf rx_conf; /**< rx configuration */\n\tstruct rte_eth_txconf tx_conf; /**< tx configuration */\n\tstruct ether_addr *mc_addr_pool; /**< pool of multicast addrs */\n\tuint32_t mc_addr_nb; /**< nb. of addr. in mc_addr_pool */\n\tuint8_t slave_flag; /**< bonding slave port */\n};\n\nextern portid_t __rte_unused\nfind_next_port(portid_t p, struct rte_port *ports, int size);\n\n#define FOREACH_PORT(p, ports) \\\n\tfor (p = find_next_port(0, ports, RTE_MAX_ETHPORTS); \\\n\t p < RTE_MAX_ETHPORTS; \\\n\t p = find_next_port(p + 1, ports, RTE_MAX_ETHPORTS))\n\n/**\n * The data structure associated with each forwarding logical core.\n * The logical cores are internally numbered by a core index from 0 to\n * the maximum number of logical cores - 1.\n * The system CPU identifier of all logical cores are setup in a global\n * CPU id. configuration table.\n */\nstruct fwd_lcore {\n\tstruct rte_mempool *mbp; /**< The mbuf pool to use by this core */\n\tstreamid_t stream_idx; /**< index of 1st stream in \"fwd_streams\" */\n\tstreamid_t stream_nb; /**< number of streams in \"fwd_streams\" */\n\tlcoreid_t cpuid_idx; /**< index of logical core in CPU id table */\n\tqueueid_t tx_queue; /**< TX queue to send forwarded packets */\n\tvolatile char stopped; /**< stop forwarding when set */\n};\n\n/*\n * Forwarding mode operations:\n * - IO forwarding mode (default mode)\n * Forwards packets unchanged.\n *\n * - MAC forwarding mode\n * Set the source and the destination Ethernet addresses of packets\n * before forwarding them.\n *\n * - IEEE1588 forwarding mode\n * Check that received IEEE1588 Precise Time Protocol (PTP) packets are\n * filtered and timestamped by the hardware.\n * Forwards packets unchanged on the same port.\n * Check that sent IEEE1588 PTP packets are timestamped by the hardware.\n */\ntypedef void (*port_fwd_begin_t)(portid_t pi);\ntypedef void (*port_fwd_end_t)(portid_t pi);\ntypedef void (*packet_fwd_t)(struct fwd_stream *fs);\n\nstruct fwd_engine {\n\tconst char *fwd_mode_name; /**< Forwarding mode name. */\n\tport_fwd_begin_t port_fwd_begin; /**< NULL if nothing special to do. */\n\tport_fwd_end_t port_fwd_end; /**< NULL if nothing special to do. */\n\tpacket_fwd_t packet_fwd; /**< Mandatory. */\n};\n\nextern struct fwd_engine io_fwd_engine;\nextern struct fwd_engine mac_fwd_engine;\nextern struct fwd_engine mac_retry_fwd_engine;\nextern struct fwd_engine mac_swap_engine;\nextern struct fwd_engine flow_gen_engine;\nextern struct fwd_engine rx_only_engine;\nextern struct fwd_engine tx_only_engine;\nextern struct fwd_engine csum_fwd_engine;\nextern struct fwd_engine icmp_echo_engine;\n#ifdef RTE_LIBRTE_IEEE1588\nextern struct fwd_engine ieee1588_fwd_engine;\n#endif\n\nextern struct fwd_engine * fwd_engines[]; /**< NULL terminated array. */\n\n/**\n * Forwarding Configuration\n *\n */\nstruct fwd_config {\n\tstruct fwd_engine *fwd_eng; /**< Packet forwarding mode. */\n\tstreamid_t nb_fwd_streams; /**< Nb. of forward streams to process. */\n\tlcoreid_t nb_fwd_lcores; /**< Nb. of logical cores to launch. */\n\tportid_t nb_fwd_ports; /**< Nb. of ports involved. */\n};\n\n/**\n * DCB mode enable\n */\nenum dcb_mode_enable\n{\n\tDCB_VT_ENABLED,\n\tDCB_ENABLED\n};\n\n/*\n * DCB general config info\n */\nstruct dcb_config {\n\tenum dcb_mode_enable dcb_mode;\n\tuint8_t vt_en;\n\tenum rte_eth_nb_tcs num_tcs;\n\tuint8_t pfc_en;\n};\n\n/*\n * In DCB io FWD mode, 128 RX queue to 128 TX queue mapping\n */\nenum dcb_queue_mapping_mode {\n\tDCB_VT_Q_MAPPING = 0,\n\tDCB_4_TCS_Q_MAPPING,\n\tDCB_8_TCS_Q_MAPPING\n};\n\n#define MAX_TX_QUEUE_STATS_MAPPINGS 1024 /* MAX_PORT of 32 @ 32 tx_queues/port */\n#define MAX_RX_QUEUE_STATS_MAPPINGS 4096 /* MAX_PORT of 32 @ 128 rx_queues/port */\n\nstruct queue_stats_mappings {\n\tuint8_t port_id;\n\tuint16_t queue_id;\n\tuint8_t stats_counter_id;\n} __rte_cache_aligned;\n\nextern struct queue_stats_mappings tx_queue_stats_mappings_array[];\nextern struct queue_stats_mappings rx_queue_stats_mappings_array[];\n\n/* Assign both tx and rx queue stats mappings to the same default values */\nextern struct queue_stats_mappings *tx_queue_stats_mappings;\nextern struct queue_stats_mappings *rx_queue_stats_mappings;\n\nextern uint16_t nb_tx_queue_stats_mappings;\nextern uint16_t nb_rx_queue_stats_mappings;\n\n/* globals used for configuration */\nextern uint16_t verbose_level; /**< Drives messages being displayed, if any. */\nextern uint8_t interactive;\nextern uint8_t auto_start;\nextern uint8_t numa_support; /**< set by \"--numa\" parameter */\nextern uint16_t port_topology; /**< set by \"--port-topology\" parameter */\nextern uint8_t no_flush_rx; /**dev_info.pci_dev->mem_resource[0].addr +\n\t\t\treg_off);\n\treg_v = *((volatile uint32_t *)reg_addr);\n\treturn rte_le_to_cpu_32(reg_v);\n}\n\n#define port_id_pci_reg_read(pt_id, reg_off) \\\n\tport_pci_reg_read(&ports[(pt_id)], (reg_off))\n\nstatic inline void\nport_pci_reg_write(struct rte_port *port, uint32_t reg_off, uint32_t reg_v)\n{\n\tvoid *reg_addr;\n\n\treg_addr = (void *)\n\t\t((char *)port->dev_info.pci_dev->mem_resource[0].addr +\n\t\t\treg_off);\n\t*((volatile uint32_t *)reg_addr) = rte_cpu_to_le_32(reg_v);\n}\n\n#define port_id_pci_reg_write(pt_id, reg_off, reg_value) \\\n\tport_pci_reg_write(&ports[(pt_id)], (reg_off), (reg_value))\n\n/* Prototypes */\nunsigned int parse_item_list(char* str, const char* item_name,\n\t\t\tunsigned int max_items,\n\t\t\tunsigned int *parsed_items, int check_unique_values);\nvoid launch_args_parse(int argc, char** argv);\nvoid prompt(void);\nvoid nic_stats_display(portid_t port_id);\nvoid nic_stats_clear(portid_t port_id);\nvoid nic_xstats_display(portid_t port_id);\nvoid nic_xstats_clear(portid_t port_id);\nvoid nic_stats_mapping_display(portid_t port_id);\nvoid port_infos_display(portid_t port_id);\nvoid fwd_lcores_config_display(void);\nvoid fwd_config_display(void);\nvoid rxtx_config_display(void);\nvoid fwd_config_setup(void);\nvoid set_def_fwd_config(void);\nvoid reconfig(portid_t new_port_id, unsigned socket_id);\nint init_fwd_streams(void);\n\nvoid port_mtu_set(portid_t port_id, uint16_t mtu);\nvoid port_reg_bit_display(portid_t port_id, uint32_t reg_off, uint8_t bit_pos);\nvoid port_reg_bit_set(portid_t port_id, uint32_t reg_off, uint8_t bit_pos,\n\t\t uint8_t bit_v);\nvoid port_reg_bit_field_display(portid_t port_id, uint32_t reg_off,\n\t\t\t\tuint8_t bit1_pos, uint8_t bit2_pos);\nvoid port_reg_bit_field_set(portid_t port_id, uint32_t reg_off,\n\t\t\t uint8_t bit1_pos, uint8_t bit2_pos, uint32_t value);\nvoid port_reg_display(portid_t port_id, uint32_t reg_off);\nvoid port_reg_set(portid_t port_id, uint32_t reg_off, uint32_t value);\n\nvoid rx_ring_desc_display(portid_t port_id, queueid_t rxq_id, uint16_t rxd_id);\nvoid tx_ring_desc_display(portid_t port_id, queueid_t txq_id, uint16_t txd_id);\n\nint set_fwd_lcores_list(unsigned int *lcorelist, unsigned int nb_lc);\nint set_fwd_lcores_mask(uint64_t lcoremask);\nvoid set_fwd_lcores_number(uint16_t nb_lc);\n\nvoid set_fwd_ports_list(unsigned int *portlist, unsigned int nb_pt);\nvoid set_fwd_ports_mask(uint64_t portmask);\nvoid set_fwd_ports_number(uint16_t nb_pt);\n\nvoid rx_vlan_strip_set(portid_t port_id, int on);\nvoid rx_vlan_strip_set_on_queue(portid_t port_id, uint16_t queue_id, int on);\n\nvoid rx_vlan_filter_set(portid_t port_id, int on);\nvoid rx_vlan_all_filter_set(portid_t port_id, int on);\nint rx_vft_set(portid_t port_id, uint16_t vlan_id, int on);\nvoid vlan_extend_set(portid_t port_id, int on);\nvoid vlan_tpid_set(portid_t port_id, uint16_t tp_id);\nvoid tx_vlan_set(portid_t port_id, uint16_t vlan_id);\nvoid tx_qinq_set(portid_t port_id, uint16_t vlan_id, uint16_t vlan_id_outer);\nvoid tx_vlan_reset(portid_t port_id);\nvoid tx_vlan_pvid_set(portid_t port_id, uint16_t vlan_id, int on);\n\nvoid set_qmap(portid_t port_id, uint8_t is_rx, uint16_t queue_id, uint8_t map_value);\n\nvoid set_verbose_level(uint16_t vb_level);\nvoid set_tx_pkt_segments(unsigned *seg_lengths, unsigned nb_segs);\nvoid set_nb_pkt_per_burst(uint16_t pkt_burst);\nchar *list_pkt_forwarding_modes(void);\nvoid set_pkt_forwarding_mode(const char *fwd_mode);\nvoid start_packet_forwarding(int with_tx_first);\nvoid stop_packet_forwarding(void);\nvoid dev_set_link_up(portid_t pid);\nvoid dev_set_link_down(portid_t pid);\nvoid init_port_config(void);\nvoid set_port_slave_flag(portid_t slave_pid);\nvoid clear_port_slave_flag(portid_t slave_pid);\nint init_port_dcb_config(portid_t pid,struct dcb_config *dcb_conf);\nint start_port(portid_t pid);\nvoid stop_port(portid_t pid);\nvoid close_port(portid_t pid);\nvoid attach_port(char *identifier);\nvoid detach_port(uint8_t port_id);\nint all_ports_stopped(void);\nint port_is_started(portid_t port_id);\nvoid pmd_test_exit(void);\nvoid fdir_get_infos(portid_t port_id);\nvoid fdir_set_flex_mask(portid_t port_id,\n\t\t\t struct rte_eth_fdir_flex_mask *cfg);\nvoid fdir_set_flex_payload(portid_t port_id,\n\t\t\t struct rte_eth_flex_payload_cfg *cfg);\nvoid port_rss_reta_info(portid_t port_id,\n\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\tuint16_t nb_entries);\n\nvoid set_vf_traffic(portid_t port_id, uint8_t is_rx, uint16_t vf, uint8_t on);\nvoid set_vf_rx_vlan(portid_t port_id, uint16_t vlan_id,\n\t\tuint64_t vf_mask, uint8_t on);\n\nint set_queue_rate_limit(portid_t port_id, uint16_t queue_idx, uint16_t rate);\nint set_vf_rate_limit(portid_t port_id, uint16_t vf, uint16_t rate,\n\t\t\t\tuint64_t q_msk);\n\nvoid port_rss_hash_conf_show(portid_t port_id, int show_rss_key);\nvoid port_rss_hash_key_update(portid_t port_id, uint8_t *hash_key);\nvoid get_syn_filter(uint8_t port_id);\nvoid get_ethertype_filter(uint8_t port_id, uint16_t index);\nvoid get_2tuple_filter(uint8_t port_id, uint16_t index);\nvoid get_5tuple_filter(uint8_t port_id, uint16_t index);\nint rx_queue_id_is_invalid(queueid_t rxq_id);\nint tx_queue_id_is_invalid(queueid_t txq_id);\n\n/* Functions to manage the set of filtered Multicast MAC addresses */\nvoid mcast_addr_add(uint8_t port_id, struct ether_addr *mc_addr);\nvoid mcast_addr_remove(uint8_t port_id, struct ether_addr *mc_addr);\n\nenum print_warning {\n\tENABLED_WARN = 0,\n\tDISABLED_WARN\n};\nint port_id_is_invalid(portid_t port_id, enum print_warning warning);\n\n/*\n * Work-around of a compilation error with ICC on invocations of the\n * rte_be_to_cpu_16() function.\n */\n#ifdef __GCC__\n#define RTE_BE_TO_CPU_16(be_16_v) rte_be_to_cpu_16((be_16_v))\n#define RTE_CPU_TO_BE_16(cpu_16_v) rte_cpu_to_be_16((cpu_16_v))\n#else\n#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n#define RTE_BE_TO_CPU_16(be_16_v) (be_16_v)\n#define RTE_CPU_TO_BE_16(cpu_16_v) (cpu_16_v)\n#else\n#define RTE_BE_TO_CPU_16(be_16_v) \\\n\t(uint16_t) ((((be_16_v) & 0xFF) << 8) | ((be_16_v) >> 8))\n#define RTE_CPU_TO_BE_16(cpu_16_v) \\\n\t(uint16_t) ((((cpu_16_v) & 0xFF) << 8) | ((cpu_16_v) >> 8))\n#endif\n#endif /* __GCC__ */\n\n#endif /* _TESTPMD_H_ */\n" }, { "path": "app/test-pmd/txonly.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"testpmd.h\"\n\n#define UDP_SRC_PORT 1024\n#define UDP_DST_PORT 1024\n\n#define IP_SRC_ADDR ((192U << 24) | (168 << 16) | (0 << 8) | 1)\n#define IP_DST_ADDR ((192U << 24) | (168 << 16) | (0 << 8) | 2)\n\n#define IP_DEFTTL 64 /* from RFC 1340. */\n#define IP_VERSION 0x40\n#define IP_HDRLEN 0x05 /* default IP header length == five 32-bits words. */\n#define IP_VHL_DEF (IP_VERSION | IP_HDRLEN)\n\nstatic struct ipv4_hdr pkt_ip_hdr; /**< IP header of transmitted packets. */\nstatic struct udp_hdr pkt_udp_hdr; /**< UDP header of transmitted packets. */\n\nstatic inline struct rte_mbuf *\ntx_mbuf_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\n\tm = __rte_mbuf_raw_alloc(mp);\n\t__rte_mbuf_sanity_check_raw(m, 0);\n\treturn (m);\n}\n\nstatic void\ncopy_buf_to_pkt_segs(void* buf, unsigned len, struct rte_mbuf *pkt,\n\t\t unsigned offset)\n{\n\tstruct rte_mbuf *seg;\n\tvoid *seg_buf;\n\tunsigned copy_len;\n\n\tseg = pkt;\n\twhile (offset >= seg->data_len) {\n\t\toffset -= seg->data_len;\n\t\tseg = seg->next;\n\t}\n\tcopy_len = seg->data_len - offset;\n\tseg_buf = rte_pktmbuf_mtod_offset(seg, char *, offset);\n\twhile (len > copy_len) {\n\t\trte_memcpy(seg_buf, buf, (size_t) copy_len);\n\t\tlen -= copy_len;\n\t\tbuf = ((char*) buf + copy_len);\n\t\tseg = seg->next;\n\t\tseg_buf = rte_pktmbuf_mtod(seg, char *);\n\t}\n\trte_memcpy(seg_buf, buf, (size_t) len);\n}\n\nstatic inline void\ncopy_buf_to_pkt(void* buf, unsigned len, struct rte_mbuf *pkt, unsigned offset)\n{\n\tif (offset + len <= pkt->data_len) {\n\t\trte_memcpy(rte_pktmbuf_mtod_offset(pkt, char *, offset),\n\t\t\tbuf, (size_t) len);\n\t\treturn;\n\t}\n\tcopy_buf_to_pkt_segs(buf, len, pkt, offset);\n}\n\nstatic void\nsetup_pkt_udp_ip_headers(struct ipv4_hdr *ip_hdr,\n\t\t\t struct udp_hdr *udp_hdr,\n\t\t\t uint16_t pkt_data_len)\n{\n\tuint16_t *ptr16;\n\tuint32_t ip_cksum;\n\tuint16_t pkt_len;\n\n\t/*\n\t * Initialize UDP header.\n\t */\n\tpkt_len = (uint16_t) (pkt_data_len + sizeof(struct udp_hdr));\n\tudp_hdr->src_port = rte_cpu_to_be_16(UDP_SRC_PORT);\n\tudp_hdr->dst_port = rte_cpu_to_be_16(UDP_DST_PORT);\n\tudp_hdr->dgram_len = RTE_CPU_TO_BE_16(pkt_len);\n\tudp_hdr->dgram_cksum = 0; /* No UDP checksum. */\n\n\t/*\n\t * Initialize IP header.\n\t */\n\tpkt_len = (uint16_t) (pkt_len + sizeof(struct ipv4_hdr));\n\tip_hdr->version_ihl = IP_VHL_DEF;\n\tip_hdr->type_of_service = 0;\n\tip_hdr->fragment_offset = 0;\n\tip_hdr->time_to_live = IP_DEFTTL;\n\tip_hdr->next_proto_id = IPPROTO_UDP;\n\tip_hdr->packet_id = 0;\n\tip_hdr->total_length = RTE_CPU_TO_BE_16(pkt_len);\n\tip_hdr->src_addr = rte_cpu_to_be_32(IP_SRC_ADDR);\n\tip_hdr->dst_addr = rte_cpu_to_be_32(IP_DST_ADDR);\n\n\t/*\n\t * Compute IP header checksum.\n\t */\n\tptr16 = (unaligned_uint16_t*) ip_hdr;\n\tip_cksum = 0;\n\tip_cksum += ptr16[0]; ip_cksum += ptr16[1];\n\tip_cksum += ptr16[2]; ip_cksum += ptr16[3];\n\tip_cksum += ptr16[4];\n\tip_cksum += ptr16[6]; ip_cksum += ptr16[7];\n\tip_cksum += ptr16[8]; ip_cksum += ptr16[9];\n\n\t/*\n\t * Reduce 32 bit checksum to 16 bits and complement it.\n\t */\n\tip_cksum = ((ip_cksum & 0xFFFF0000) >> 16) +\n\t\t(ip_cksum & 0x0000FFFF);\n\tif (ip_cksum > 65535)\n\t\tip_cksum -= 65535;\n\tip_cksum = (~ip_cksum) & 0x0000FFFF;\n\tif (ip_cksum == 0)\n\t\tip_cksum = 0xFFFF;\n\tip_hdr->hdr_checksum = (uint16_t) ip_cksum;\n}\n\n/*\n * Transmit a burst of multi-segments packets.\n */\nstatic void\npkt_burst_transmit(struct fwd_stream *fs)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_port *txp;\n\tstruct rte_mbuf *pkt;\n\tstruct rte_mbuf *pkt_seg;\n\tstruct rte_mempool *mbp;\n\tstruct ether_hdr eth_hdr;\n\tuint16_t nb_tx;\n\tuint16_t nb_pkt;\n\tuint16_t vlan_tci, vlan_tci_outer;\n\tuint64_t ol_flags = 0;\n\tuint8_t i;\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tuint64_t start_tsc;\n\tuint64_t end_tsc;\n\tuint64_t core_cycles;\n#endif\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tstart_tsc = rte_rdtsc();\n#endif\n\n\tmbp = current_fwd_lcore()->mbp;\n\ttxp = &ports[fs->tx_port];\n\tvlan_tci = txp->tx_vlan_id;\n\tvlan_tci_outer = txp->tx_vlan_id_outer;\n\tif (txp->tx_ol_flags & TESTPMD_TX_OFFLOAD_INSERT_VLAN)\n\t\tol_flags = PKT_TX_VLAN_PKT;\n\tif (txp->tx_ol_flags & TESTPMD_TX_OFFLOAD_INSERT_QINQ)\n\t\tol_flags |= PKT_TX_QINQ_PKT;\n\tfor (nb_pkt = 0; nb_pkt < nb_pkt_per_burst; nb_pkt++) {\n\t\tpkt = tx_mbuf_alloc(mbp);\n\t\tif (pkt == NULL) {\n\t\tnomore_mbuf:\n\t\t\tif (nb_pkt == 0)\n\t\t\t\treturn;\n\t\t\tbreak;\n\t\t}\n\t\tpkt->data_len = tx_pkt_seg_lengths[0];\n\t\tpkt_seg = pkt;\n\t\tfor (i = 1; i < tx_pkt_nb_segs; i++) {\n\t\t\tpkt_seg->next = tx_mbuf_alloc(mbp);\n\t\t\tif (pkt_seg->next == NULL) {\n\t\t\t\tpkt->nb_segs = i;\n\t\t\t\trte_pktmbuf_free(pkt);\n\t\t\t\tgoto nomore_mbuf;\n\t\t\t}\n\t\t\tpkt_seg = pkt_seg->next;\n\t\t\tpkt_seg->data_len = tx_pkt_seg_lengths[i];\n\t\t}\n\t\tpkt_seg->next = NULL; /* Last segment of packet. */\n\n\t\t/*\n\t\t * Initialize Ethernet header.\n\t\t */\n\t\tether_addr_copy(&peer_eth_addrs[fs->peer_addr],ð_hdr.d_addr);\n\t\tether_addr_copy(&ports[fs->tx_port].eth_addr, ð_hdr.s_addr);\n\t\teth_hdr.ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);\n\n\t\t/*\n\t\t * Copy headers in first packet segment(s).\n\t\t */\n\t\tcopy_buf_to_pkt(ð_hdr, sizeof(eth_hdr), pkt, 0);\n\t\tcopy_buf_to_pkt(&pkt_ip_hdr, sizeof(pkt_ip_hdr), pkt,\n\t\t\t\tsizeof(struct ether_hdr));\n\t\tcopy_buf_to_pkt(&pkt_udp_hdr, sizeof(pkt_udp_hdr), pkt,\n\t\t\t\tsizeof(struct ether_hdr) +\n\t\t\t\tsizeof(struct ipv4_hdr));\n\n\t\t/*\n\t\t * Complete first mbuf of packet and append it to the\n\t\t * burst of packets to be transmitted.\n\t\t */\n\t\tpkt->nb_segs = tx_pkt_nb_segs;\n\t\tpkt->pkt_len = tx_pkt_length;\n\t\tpkt->ol_flags = ol_flags;\n\t\tpkt->vlan_tci = vlan_tci;\n\t\tpkt->vlan_tci_outer = vlan_tci_outer;\n\t\tpkt->l2_len = sizeof(struct ether_hdr);\n\t\tpkt->l3_len = sizeof(struct ipv4_hdr);\n\t\tpkts_burst[nb_pkt] = pkt;\n\t}\n\tnb_tx = rte_eth_tx_burst(fs->tx_port, fs->tx_queue, pkts_burst, nb_pkt);\n\tfs->tx_packets += nb_tx;\n\n#ifdef RTE_TEST_PMD_RECORD_BURST_STATS\n\tfs->tx_burst_stats.pkt_burst_spread[nb_tx]++;\n#endif\n\tif (unlikely(nb_tx < nb_pkt)) {\n\t\tif (verbose_level > 0 && fs->fwd_dropped == 0)\n\t\t\tprintf(\"port %d tx_queue %d - drop \"\n\t\t\t \"(nb_pkt:%u - nb_tx:%u)=%u packets\\n\",\n\t\t\t fs->tx_port, fs->tx_queue,\n\t\t\t (unsigned) nb_pkt, (unsigned) nb_tx,\n\t\t\t (unsigned) (nb_pkt - nb_tx));\n\t\tfs->fwd_dropped += (nb_pkt - nb_tx);\n\t\tdo {\n\t\t\trte_pktmbuf_free(pkts_burst[nb_tx]);\n\t\t} while (++nb_tx < nb_pkt);\n\t}\n\n#ifdef RTE_TEST_PMD_RECORD_CORE_CYCLES\n\tend_tsc = rte_rdtsc();\n\tcore_cycles = (end_tsc - start_tsc);\n\tfs->core_cycles = (uint64_t) (fs->core_cycles + core_cycles);\n#endif\n}\n\nstatic void\ntx_only_begin(__attribute__((unused)) portid_t pi)\n{\n\tuint16_t pkt_data_len;\n\n\tpkt_data_len = (uint16_t) (tx_pkt_length - (sizeof(struct ether_hdr) +\n\t\t\t\t\t\t sizeof(struct ipv4_hdr) +\n\t\t\t\t\t\t sizeof(struct udp_hdr)));\n\tsetup_pkt_udp_ip_headers(&pkt_ip_hdr, &pkt_udp_hdr, pkt_data_len);\n}\n\nstruct fwd_engine tx_only_engine = {\n\t.fwd_mode_name = \"txonly\",\n\t.port_fwd_begin = tx_only_begin,\n\t.port_fwd_end = NULL,\n\t.packet_fwd = pkt_burst_transmit,\n};\n" }, { "path": "config/common_bsdapp", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\n#\n# define executive environment\n#\n# CONFIG_RTE_EXEC_ENV can be linuxapp, bsdapp\n#\nCONFIG_RTE_EXEC_ENV=\"bsdapp\"\nCONFIG_RTE_EXEC_ENV_BSDAPP=y\n\n##\n## machine can define specific variables or action for a specific board\n## RTE_MACHINE can be:\n## default nothing specific\n## native current machine\n## atm Intel® Atom™ microarchitecture\n## nhm Intel® microarchitecture code name Nehalem\n## wsm Intel® microarchitecture code name Westmere\n## snb Intel® microarchitecture code name Sandy Bridge\n## ivb Intel® microarchitecture code name Ivy Bridge\n##\n## Note: if your compiler does not support the relevant -march options,\n## it will be compiled with whatever latest processor the compiler supports!\n##\n#CONFIG_RTE_MACHINE=\"native\"\n#\n##\n## define the architecture we compile for.\n## CONFIG_RTE_ARCH can be i686, x86_64, x86_64_32\n##\n#CONFIG_RTE_ARCH=\"x86_64\"\n#CONFIG_RTE_ARCH_X86_64=y\n#\n##\n## The compiler we use.\n## Can be gcc, icc or clang.\n##\n#CONFIG_RTE_TOOLCHAIN=\"gcc\"\n#CONFIG_RTE_TOOLCHAIN_GCC=y\n\n#\n# Use intrinsics or assembly code for key routines\n#\nCONFIG_RTE_FORCE_INTRINSICS=n\n\n#\n# Machine forces strict alignment constraints.\n#\nCONFIG_RTE_ARCH_STRICT_ALIGN=n\n\n#\n# Compile to share library\n#\nCONFIG_RTE_BUILD_SHARED_LIB=n\n\n#\n# Combine to one single library\n#\nCONFIG_RTE_BUILD_COMBINE_LIBS=n\n\n#\n# Use newest code breaking previous ABI\n#\nCONFIG_RTE_NEXT_ABI=y\n\n#\n# Compile Environment Abstraction Layer\n#\nCONFIG_RTE_LIBRTE_EAL=y\nCONFIG_RTE_MAX_LCORE=128\nCONFIG_RTE_MAX_NUMA_NODES=8\nCONFIG_RTE_MAX_MEMSEG=256\nCONFIG_RTE_MAX_MEMZONE=2560\nCONFIG_RTE_MAX_TAILQ=32\nCONFIG_RTE_LOG_LEVEL=8\nCONFIG_RTE_LOG_HISTORY=256\nCONFIG_RTE_EAL_ALLOW_INV_SOCKET_ID=n\nCONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=n\nCONFIG_RTE_MALLOC_DEBUG=n\n\n#\n# FreeBSD contiguous memory driver settings\n#\nCONFIG_RTE_CONTIGMEM_MAX_NUM_BUFS=64\nCONFIG_RTE_CONTIGMEM_DEFAULT_NUM_BUFS=2\nCONFIG_RTE_CONTIGMEM_DEFAULT_BUF_SIZE=1024*1024*1024\n\n#\n# Compile Environment Abstraction Layer for BSD\n#\nCONFIG_RTE_LIBRTE_EAL_BSDAPP=y\n\n#\n# Compile Environment Abstraction Layer for linux\n#\nCONFIG_RTE_LIBRTE_EAL_LINUXAPP=n\n\n#\n# Compile Environment Abstraction Layer to support Vmware TSC map\n#\nCONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=y\n\n#\n# Compile the argument parser library\n#\nCONFIG_RTE_LIBRTE_KVARGS=y\n\n#\n# Compile generic ethernet library\n#\nCONFIG_RTE_LIBRTE_ETHER=y\nCONFIG_RTE_LIBRTE_ETHDEV_DEBUG=n\nCONFIG_RTE_MAX_ETHPORTS=32\nCONFIG_RTE_MAX_QUEUES_PER_PORT=256\nCONFIG_RTE_LIBRTE_IEEE1588=n\nCONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS=16\nCONFIG_RTE_ETHDEV_RXTX_CALLBACKS=y\n\n#\n# Support NIC bypass logic\n#\nCONFIG_RTE_NIC_BYPASS=n\n\n#\n# Compile burst-oriented IGB & EM PMD drivers\n#\nCONFIG_RTE_LIBRTE_EM_PMD=y\nCONFIG_RTE_LIBRTE_IGB_PMD=y\nCONFIG_RTE_LIBRTE_E1000_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_E1000_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_E1000_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_E1000_DEBUG_TX_FREE=n\nCONFIG_RTE_LIBRTE_E1000_DEBUG_DRIVER=n\nCONFIG_RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC=n\n\n#\n# Compile burst-oriented IXGBE PMD driver\n#\nCONFIG_RTE_LIBRTE_IXGBE_PMD=y\nCONFIG_RTE_LIBRTE_IXGBE_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_IXGBE_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_IXGBE_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_IXGBE_DEBUG_TX_FREE=n\nCONFIG_RTE_LIBRTE_IXGBE_DEBUG_DRIVER=n\nCONFIG_RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC=n\nCONFIG_RTE_IXGBE_INC_VECTOR=y\nCONFIG_RTE_IXGBE_RX_OLFLAGS_ENABLE=y\n\n#\n# Compile burst-oriented I40E PMD driver\n#\nCONFIG_RTE_LIBRTE_I40E_PMD=y\nCONFIG_RTE_LIBRTE_I40E_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_I40E_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_I40E_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_I40E_DEBUG_TX_FREE=n\nCONFIG_RTE_LIBRTE_I40E_DEBUG_DRIVER=n\nCONFIG_RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC=y\nCONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=n\nCONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF=4\nCONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM=4\n# interval up to 8160 us, aligned to 2 (or default value)\nCONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL=-1\n\n#\n# Compile burst-oriented FM10K PMD\n#\nCONFIG_RTE_LIBRTE_FM10K_PMD=y\nCONFIG_RTE_LIBRTE_FM10K_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_FM10K_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_FM10K_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_FM10K_DEBUG_TX_FREE=n\nCONFIG_RTE_LIBRTE_FM10K_DEBUG_DRIVER=n\nCONFIG_RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE=y\n\n#\n# Compile burst-oriented Mellanox ConnectX-3 (MLX4) PMD\n#\nCONFIG_RTE_LIBRTE_MLX4_PMD=n\nCONFIG_RTE_LIBRTE_MLX4_DEBUG=n\nCONFIG_RTE_LIBRTE_MLX4_SGE_WR_N=4\nCONFIG_RTE_LIBRTE_MLX4_MAX_INLINE=0\nCONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE=8\nCONFIG_RTE_LIBRTE_MLX4_SOFT_COUNTERS=1\n\n#\n# Compile burst-oriented Broadcom PMD driver\n#\nCONFIG_RTE_LIBRTE_BNX2X_PMD=n\nCONFIG_RTE_LIBRTE_BNX2X_DEBUG=n\nCONFIG_RTE_LIBRTE_BNX2X_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_BNX2X_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_BNX2X_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_BNX2X_MF_SUPPORT=n\n\n#\n# Compile burst-oriented Chelsio Terminator 10GbE/40GbE (CXGBE) PMD\n#\nCONFIG_RTE_LIBRTE_CXGBE_PMD=y\nCONFIG_RTE_LIBRTE_CXGBE_DEBUG=n\nCONFIG_RTE_LIBRTE_CXGBE_DEBUG_REG=n\nCONFIG_RTE_LIBRTE_CXGBE_DEBUG_MBOX=n\nCONFIG_RTE_LIBRTE_CXGBE_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_CXGBE_DEBUG_RX=n\n\n#\n# Compile burst-oriented Cisco ENIC PMD driver\n#\nCONFIG_RTE_LIBRTE_ENIC_PMD=y\nCONFIG_RTE_LIBRTE_ENIC_DEBUG=n\n\n#\n# Compile burst-oriented VIRTIO PMD driver\n#\nCONFIG_RTE_LIBRTE_VIRTIO_PMD=y\nCONFIG_RTE_LIBRTE_VIRTIO_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_VIRTIO_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_VIRTIO_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_VIRTIO_DEBUG_DRIVER=n\nCONFIG_RTE_LIBRTE_VIRTIO_DEBUG_DUMP=n\n\n#\n# Compile burst-oriented VMXNET3 PMD driver\n#\nCONFIG_RTE_LIBRTE_VMXNET3_PMD=y\nCONFIG_RTE_LIBRTE_VMXNET3_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_VMXNET3_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_VMXNET3_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_VMXNET3_DEBUG_TX_FREE=n\nCONFIG_RTE_LIBRTE_VMXNET3_DEBUG_DRIVER=n\n\n#\n# Compile example software rings based PMD\n#\nCONFIG_RTE_LIBRTE_PMD_RING=y\nCONFIG_RTE_PMD_RING_MAX_RX_RINGS=16\nCONFIG_RTE_PMD_RING_MAX_TX_RINGS=16\n\n#\n# Compile software PMD backed by PCAP files\n#\nCONFIG_RTE_LIBRTE_PMD_PCAP=y\n\n#\n# Compile link bonding PMD library\n#\nCONFIG_RTE_LIBRTE_PMD_BOND=y\nCONFIG_RTE_LIBRTE_BOND_DEBUG_ALB=n\nCONFIG_RTE_LIBRTE_BOND_DEBUG_ALB_L1=n\n\n#\n# Compile null PMD\n#\nCONFIG_RTE_LIBRTE_PMD_NULL=y\n\n#\n# Do prefetch of packet data within PMD driver receive function\n#\nCONFIG_RTE_PMD_PACKET_PREFETCH=y\n\n#\n# Compile librte_ring\n#\nCONFIG_RTE_LIBRTE_RING=y\nCONFIG_RTE_LIBRTE_RING_DEBUG=n\nCONFIG_RTE_RING_SPLIT_PROD_CONS=n\nCONFIG_RTE_RING_PAUSE_REP_COUNT=0\n\n#\n# Compile librte_mempool\n#\nCONFIG_RTE_LIBRTE_MEMPOOL=y\nCONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE=512\nCONFIG_RTE_LIBRTE_MEMPOOL_DEBUG=n\n\n#\n# Compile librte_mbuf\n#\nCONFIG_RTE_LIBRTE_MBUF=y\nCONFIG_RTE_LIBRTE_MBUF_DEBUG=n\nCONFIG_RTE_MBUF_REFCNT_ATOMIC=y\nCONFIG_RTE_PKTMBUF_HEADROOM=128\n\n#\n# Compile librte_timer\n#\nCONFIG_RTE_LIBRTE_TIMER=y\nCONFIG_RTE_LIBRTE_TIMER_DEBUG=n\n\n#\n# Compile librte_cfgfile\n#\nCONFIG_RTE_LIBRTE_CFGFILE=y\n\n#\n# Compile librte_cmdline\n#\nCONFIG_RTE_LIBRTE_CMDLINE=y\nCONFIG_RTE_LIBRTE_CMDLINE_DEBUG=n\n\n#\n# Compile librte_hash\n#\nCONFIG_RTE_LIBRTE_HASH=y\nCONFIG_RTE_LIBRTE_HASH_DEBUG=n\n\n#\n# Compile librte_jobstats\n#\nCONFIG_RTE_LIBRTE_JOBSTATS=y\n\n#\n# Compile librte_lpm\n#\nCONFIG_RTE_LIBRTE_LPM=y\nCONFIG_RTE_LIBRTE_LPM_DEBUG=n\n\n#\n# Compile librte_acl\n#\nCONFIG_RTE_LIBRTE_ACL=y\nCONFIG_RTE_LIBRTE_ACL_DEBUG=n\n\n#\n# Compile librte_power\n#\nCONFIG_RTE_LIBRTE_POWER=n\nCONFIG_RTE_LIBRTE_POWER_DEBUG=n\nCONFIG_RTE_MAX_LCORE_FREQS=64\n\n#\n# Compile librte_net\n#\nCONFIG_RTE_LIBRTE_NET=y\n\n#\n# Compile librte_ip_frag\n#\nCONFIG_RTE_LIBRTE_IP_FRAG=y\nCONFIG_RTE_LIBRTE_IP_FRAG_DEBUG=n\nCONFIG_RTE_LIBRTE_IP_FRAG_MAX_FRAG=4\nCONFIG_RTE_LIBRTE_IP_FRAG_TBL_STAT=n\n\n#\n# Compile librte_meter\n#\nCONFIG_RTE_LIBRTE_METER=y\n\n#\n# Compile librte_sched\n#\nCONFIG_RTE_LIBRTE_SCHED=y\nCONFIG_RTE_SCHED_RED=n\nCONFIG_RTE_SCHED_COLLECT_STATS=n\nCONFIG_RTE_SCHED_SUBPORT_TC_OV=n\nCONFIG_RTE_SCHED_PORT_N_GRINDERS=8\n\n#\n# Compile the distributor library\n#\nCONFIG_RTE_LIBRTE_DISTRIBUTOR=y\n\n#\n# Compile the reorder library\n#\nCONFIG_RTE_LIBRTE_REORDER=y\n\n#\n# Compile librte_port\n#\nCONFIG_RTE_LIBRTE_PORT=y\nCONFIG_RTE_PORT_STATS_COLLECT=n\n\n#\n# Compile librte_table\n#\nCONFIG_RTE_LIBRTE_TABLE=y\nCONFIG_RTE_TABLE_STATS_COLLECT=n\n\n#\n# Compile librte_pipeline\n#\nCONFIG_RTE_LIBRTE_PIPELINE=y\nCONFIG_RTE_PIPELINE_STATS_COLLECT=n\n\n#\n# Enable warning directives\n#\nCONFIG_RTE_INSECURE_FUNCTION_WARNING=n\n\n#\n# Compile the test application\n#\nCONFIG_RTE_APP_TEST=y\n\n#\n# Compile the PMD test application\n#\nCONFIG_RTE_TEST_PMD=y\nCONFIG_RTE_TEST_PMD_RECORD_CORE_CYCLES=n\nCONFIG_RTE_TEST_PMD_RECORD_BURST_STATS=n\n" }, { "path": "config/common_linuxapp", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\n#\n# define executive environment\n#\n# CONFIG_RTE_EXEC_ENV can be linuxapp, bsdapp\n#\nCONFIG_RTE_EXEC_ENV=\"linuxapp\"\nCONFIG_RTE_EXEC_ENV_LINUXAPP=y\n\n##\n## machine can define specific variables or action for a specific board\n## RTE_MACHINE can be:\n## default nothing specific\n## native current machine\n## atm Intel® Atom™ microarchitecture\n## nhm Intel® microarchitecture code name Nehalem\n## wsm Intel® microarchitecture code name Westmere\n## snb Intel® microarchitecture code name Sandy Bridge\n## ivb Intel® microarchitecture code name Ivy Bridge\n##\n## Note: if your compiler does not support the relevant -march options,\n## it will be compiled with whatever latest processor the compiler supports!\n##\n#CONFIG_RTE_MACHINE=\"native\"\n#\n##\n## define the architecture we compile for.\n## CONFIG_RTE_ARCH can be i686, x86_64, x86_64_32\n##\n#CONFIG_RTE_ARCH=\"x86_64\"\n#CONFIG_RTE_ARCH_X86_64=y\n#\n##\n## The compiler we use.\n## Can be gcc, icc or clang.\n##\n#CONFIG_RTE_TOOLCHAIN=\"gcc\"\n#CONFIG_RTE_TOOLCHAIN_GCC=y\n\n#\n# Use intrinsics or assembly code for key routines\n#\nCONFIG_RTE_FORCE_INTRINSICS=n\n\n#\n# Machine forces strict alignment constraints.\n#\nCONFIG_RTE_ARCH_STRICT_ALIGN=n\n\n#\n# Compile to share library\n#\nCONFIG_RTE_BUILD_SHARED_LIB=n\n\n#\n# Combine to one single library\n#\nCONFIG_RTE_BUILD_COMBINE_LIBS=n\n\n#\n# Use newest code breaking previous ABI\n#\nCONFIG_RTE_NEXT_ABI=y\n\n#\n# Compile Environment Abstraction Layer\n#\nCONFIG_RTE_LIBRTE_EAL=y\nCONFIG_RTE_MAX_LCORE=128\nCONFIG_RTE_MAX_NUMA_NODES=8\nCONFIG_RTE_MAX_MEMSEG=256\nCONFIG_RTE_MAX_MEMZONE=2560\nCONFIG_RTE_MAX_TAILQ=32\nCONFIG_RTE_LOG_LEVEL=8\nCONFIG_RTE_LOG_HISTORY=256\nCONFIG_RTE_LIBEAL_USE_HPET=n\nCONFIG_RTE_EAL_ALLOW_INV_SOCKET_ID=n\nCONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=n\nCONFIG_RTE_EAL_IGB_UIO=y\nCONFIG_RTE_EAL_VFIO=y\nCONFIG_RTE_MALLOC_DEBUG=n\n\n#\n# Special configurations in PCI Config Space for high performance\n#\nCONFIG_RTE_PCI_CONFIG=n\nCONFIG_RTE_PCI_EXTENDED_TAG=\"\"\nCONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE=0\n\n#\n# Compile Environment Abstraction Layer for linux\n#\nCONFIG_RTE_LIBRTE_EAL_LINUXAPP=y\n\n#\n# Compile Environment Abstraction Layer to support Vmware TSC map\n#\nCONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=y\n\n#\n# Compile the argument parser library\n#\nCONFIG_RTE_LIBRTE_KVARGS=y\n\n#\n# Compile generic ethernet library\n#\nCONFIG_RTE_LIBRTE_ETHER=y\nCONFIG_RTE_LIBRTE_ETHDEV_DEBUG=n\nCONFIG_RTE_MAX_ETHPORTS=32\nCONFIG_RTE_MAX_QUEUES_PER_PORT=256\nCONFIG_RTE_LIBRTE_IEEE1588=n\nCONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS=16\nCONFIG_RTE_ETHDEV_RXTX_CALLBACKS=y\n\n#\n# Support NIC bypass logic\n#\nCONFIG_RTE_NIC_BYPASS=n\n\n#\n# Compile burst-oriented IGB & EM PMD drivers\n#\nCONFIG_RTE_LIBRTE_EM_PMD=y\nCONFIG_RTE_LIBRTE_IGB_PMD=y\nCONFIG_RTE_LIBRTE_E1000_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_E1000_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_E1000_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_E1000_DEBUG_TX_FREE=n\nCONFIG_RTE_LIBRTE_E1000_DEBUG_DRIVER=n\nCONFIG_RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC=n\n\n#\n# Compile burst-oriented IXGBE PMD driver\n#\nCONFIG_RTE_LIBRTE_IXGBE_PMD=y\nCONFIG_RTE_LIBRTE_IXGBE_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_IXGBE_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_IXGBE_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_IXGBE_DEBUG_TX_FREE=n\nCONFIG_RTE_LIBRTE_IXGBE_DEBUG_DRIVER=n\nCONFIG_RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC=n\nCONFIG_RTE_IXGBE_INC_VECTOR=y\nCONFIG_RTE_IXGBE_RX_OLFLAGS_ENABLE=y\n\n#\n# Compile burst-oriented I40E PMD driver\n#\nCONFIG_RTE_LIBRTE_I40E_PMD=y\nCONFIG_RTE_LIBRTE_I40E_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_I40E_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_I40E_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_I40E_DEBUG_TX_FREE=n\nCONFIG_RTE_LIBRTE_I40E_DEBUG_DRIVER=n\nCONFIG_RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC=y\nCONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=n\nCONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF=4\nCONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM=4\n# interval up to 8160 us, aligned to 2 (or default value)\nCONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL=-1\n\n#\n# Compile burst-oriented FM10K PMD\n#\nCONFIG_RTE_LIBRTE_FM10K_PMD=y\nCONFIG_RTE_LIBRTE_FM10K_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_FM10K_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_FM10K_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_FM10K_DEBUG_TX_FREE=n\nCONFIG_RTE_LIBRTE_FM10K_DEBUG_DRIVER=n\nCONFIG_RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE=y\n\n#\n# Compile burst-oriented Mellanox ConnectX-3 (MLX4) PMD\n#\nCONFIG_RTE_LIBRTE_MLX4_PMD=n\nCONFIG_RTE_LIBRTE_MLX4_DEBUG=n\nCONFIG_RTE_LIBRTE_MLX4_SGE_WR_N=4\nCONFIG_RTE_LIBRTE_MLX4_MAX_INLINE=0\nCONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE=8\nCONFIG_RTE_LIBRTE_MLX4_SOFT_COUNTERS=1\n\n#\n# Compile burst-oriented Broadcom PMD driver\n#\nCONFIG_RTE_LIBRTE_BNX2X_PMD=n\nCONFIG_RTE_LIBRTE_BNX2X_DEBUG=n\nCONFIG_RTE_LIBRTE_BNX2X_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_BNX2X_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_BNX2X_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_BNX2X_MF_SUPPORT=n\n\n#\n# Compile burst-oriented Chelsio Terminator 10GbE/40GbE (CXGBE) PMD\n#\nCONFIG_RTE_LIBRTE_CXGBE_PMD=y\nCONFIG_RTE_LIBRTE_CXGBE_DEBUG=n\nCONFIG_RTE_LIBRTE_CXGBE_DEBUG_REG=n\nCONFIG_RTE_LIBRTE_CXGBE_DEBUG_MBOX=n\nCONFIG_RTE_LIBRTE_CXGBE_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_CXGBE_DEBUG_RX=n\n\n#\n# Compile burst-oriented Cisco ENIC PMD driver\n#\nCONFIG_RTE_LIBRTE_ENIC_PMD=y\nCONFIG_RTE_LIBRTE_ENIC_DEBUG=n\n\n#\n# Compile burst-oriented VIRTIO PMD driver\n#\nCONFIG_RTE_LIBRTE_VIRTIO_PMD=y\nCONFIG_RTE_LIBRTE_VIRTIO_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_VIRTIO_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_VIRTIO_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_VIRTIO_DEBUG_DRIVER=n\nCONFIG_RTE_LIBRTE_VIRTIO_DEBUG_DUMP=n\n\n#\n# Compile burst-oriented VMXNET3 PMD driver\n#\nCONFIG_RTE_LIBRTE_VMXNET3_PMD=y\nCONFIG_RTE_LIBRTE_VMXNET3_DEBUG_INIT=n\nCONFIG_RTE_LIBRTE_VMXNET3_DEBUG_RX=n\nCONFIG_RTE_LIBRTE_VMXNET3_DEBUG_TX=n\nCONFIG_RTE_LIBRTE_VMXNET3_DEBUG_TX_FREE=n\nCONFIG_RTE_LIBRTE_VMXNET3_DEBUG_DRIVER=n\n\n#\n# Compile example software rings based PMD\n#\nCONFIG_RTE_LIBRTE_PMD_RING=y\nCONFIG_RTE_PMD_RING_MAX_RX_RINGS=16\nCONFIG_RTE_PMD_RING_MAX_TX_RINGS=16\n\n#\n# Compile software PMD backed by PCAP files\n#\nCONFIG_RTE_LIBRTE_PMD_PCAP=n\n\n#\n# Compile link bonding PMD library\n#\nCONFIG_RTE_LIBRTE_PMD_BOND=y\nCONFIG_RTE_LIBRTE_BOND_DEBUG_ALB=n\nCONFIG_RTE_LIBRTE_BOND_DEBUG_ALB_L1=n\n\n#\n# Compile software PMD backed by AF_PACKET sockets (Linux only)\n#\nCONFIG_RTE_LIBRTE_PMD_AF_PACKET=y\n\n#\n# Compile Xen PMD\n#\nCONFIG_RTE_LIBRTE_PMD_XENVIRT=n\n\n#\n# Compile null PMD\n#\nCONFIG_RTE_LIBRTE_PMD_NULL=y\n\n#\n# Do prefetch of packet data within PMD driver receive function\n#\nCONFIG_RTE_PMD_PACKET_PREFETCH=y\n\n#\n# Compile librte_ring\n#\nCONFIG_RTE_LIBRTE_RING=y\nCONFIG_RTE_LIBRTE_RING_DEBUG=n\nCONFIG_RTE_RING_SPLIT_PROD_CONS=n\nCONFIG_RTE_RING_PAUSE_REP_COUNT=0\n\n#\n# Compile librte_mempool\n#\nCONFIG_RTE_LIBRTE_MEMPOOL=y\nCONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE=512\nCONFIG_RTE_LIBRTE_MEMPOOL_DEBUG=n\n\n#\n# Compile librte_mbuf\n#\nCONFIG_RTE_LIBRTE_MBUF=y\nCONFIG_RTE_LIBRTE_MBUF_DEBUG=n\nCONFIG_RTE_MBUF_REFCNT_ATOMIC=y\nCONFIG_RTE_PKTMBUF_HEADROOM=128\n\n#\n# Compile librte_timer\n#\nCONFIG_RTE_LIBRTE_TIMER=y\nCONFIG_RTE_LIBRTE_TIMER_DEBUG=n\n\n#\n# Compile librte_cfgfile\n#\nCONFIG_RTE_LIBRTE_CFGFILE=y\n\n#\n# Compile librte_cmdline\n#\nCONFIG_RTE_LIBRTE_CMDLINE=y\nCONFIG_RTE_LIBRTE_CMDLINE_DEBUG=n\n\n#\n# Compile librte_hash\n#\nCONFIG_RTE_LIBRTE_HASH=y\nCONFIG_RTE_LIBRTE_HASH_DEBUG=n\n\n#\n# Compile librte_jobstats\n#\nCONFIG_RTE_LIBRTE_JOBSTATS=y\n\n#\n# Compile librte_lpm\n#\nCONFIG_RTE_LIBRTE_LPM=y\nCONFIG_RTE_LIBRTE_LPM_DEBUG=n\n\n#\n# Compile librte_acl\n#\nCONFIG_RTE_LIBRTE_ACL=y\nCONFIG_RTE_LIBRTE_ACL_DEBUG=n\n\n#\n# Compile librte_power\n#\nCONFIG_RTE_LIBRTE_POWER=y\nCONFIG_RTE_LIBRTE_POWER_DEBUG=n\nCONFIG_RTE_MAX_LCORE_FREQS=64\n\n#\n# Compile librte_net\n#\nCONFIG_RTE_LIBRTE_NET=y\n\n#\n# Compile librte_ip_frag\n#\nCONFIG_RTE_LIBRTE_IP_FRAG=y\nCONFIG_RTE_LIBRTE_IP_FRAG_DEBUG=n\nCONFIG_RTE_LIBRTE_IP_FRAG_MAX_FRAG=4\nCONFIG_RTE_LIBRTE_IP_FRAG_TBL_STAT=n\n\n#\n# Compile librte_meter\n#\nCONFIG_RTE_LIBRTE_METER=y\n\n#\n# Compile librte_sched\n#\nCONFIG_RTE_LIBRTE_SCHED=y\nCONFIG_RTE_SCHED_RED=n\nCONFIG_RTE_SCHED_COLLECT_STATS=n\nCONFIG_RTE_SCHED_SUBPORT_TC_OV=n\nCONFIG_RTE_SCHED_PORT_N_GRINDERS=8\n\n#\n# Compile the distributor library\n#\nCONFIG_RTE_LIBRTE_DISTRIBUTOR=y\n\n#\n# Compile the reorder library\n#\nCONFIG_RTE_LIBRTE_REORDER=y\n\n#\n# Compile librte_port\n#\nCONFIG_RTE_LIBRTE_PORT=y\nCONFIG_RTE_PORT_STATS_COLLECT=n\n\n#\n# Compile librte_table\n#\nCONFIG_RTE_LIBRTE_TABLE=y\nCONFIG_RTE_TABLE_STATS_COLLECT=n\n\n#\n# Compile librte_pipeline\n#\nCONFIG_RTE_LIBRTE_PIPELINE=y\nCONFIG_RTE_PIPELINE_STATS_COLLECT=n\n\n#\n# Compile librte_kni\n#\nCONFIG_RTE_LIBRTE_KNI=y\nCONFIG_RTE_KNI_KMOD=y\nCONFIG_RTE_KNI_PREEMPT_DEFAULT=y\nCONFIG_RTE_KNI_KO_DEBUG=n\nCONFIG_RTE_KNI_VHOST=n\nCONFIG_RTE_KNI_VHOST_MAX_CACHE_SIZE=1024\nCONFIG_RTE_KNI_VHOST_VNET_HDR_EN=n\nCONFIG_RTE_KNI_VHOST_DEBUG_RX=n\nCONFIG_RTE_KNI_VHOST_DEBUG_TX=n\n\n#\n# Compile vhost library\n# fuse-devel is needed to run vhost-cuse.\n# fuse-devel enables user space char driver development\n# vhost-user is turned on by default.\n#\nCONFIG_RTE_LIBRTE_VHOST=y\nCONFIG_RTE_LIBRTE_VHOST_USER=y\nCONFIG_RTE_LIBRTE_VHOST_NUMA=n\nCONFIG_RTE_LIBRTE_VHOST_DEBUG=n\n\n#\n#Compile Xen domain0 support\n#\nCONFIG_RTE_LIBRTE_XEN_DOM0=n\n\n#\n# Enable warning directives\n#\nCONFIG_RTE_INSECURE_FUNCTION_WARNING=n\n\n#\n# Compile the test application\n#\nCONFIG_RTE_APP_TEST=y\n\n#\n# Compile the PMD test application\n#\nCONFIG_RTE_TEST_PMD=y\nCONFIG_RTE_TEST_PMD_RECORD_CORE_CYCLES=n\nCONFIG_RTE_TEST_PMD_RECORD_BURST_STATS=n\n" }, { "path": "config/defconfig_i686-native-linuxapp-gcc", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\n#include \"common_linuxapp\"\n\nCONFIG_RTE_MACHINE=\"native\"\n\nCONFIG_RTE_ARCH=\"i686\"\nCONFIG_RTE_ARCH_I686=y\n\nCONFIG_RTE_TOOLCHAIN=\"gcc\"\nCONFIG_RTE_TOOLCHAIN_GCC=y\n\n#\n# KNI is not supported on 32-bit\n#\nCONFIG_RTE_LIBRTE_KNI=n\n\n#\n# Vectorized PMD is not supported on 32-bit\n#\nCONFIG_RTE_IXGBE_INC_VECTOR=n\n" }, { "path": "config/defconfig_i686-native-linuxapp-icc", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\n#include \"common_linuxapp\"\n\nCONFIG_RTE_MACHINE=\"native\"\n\nCONFIG_RTE_ARCH=\"i686\"\nCONFIG_RTE_ARCH_I686=y\n\nCONFIG_RTE_TOOLCHAIN=\"icc\"\nCONFIG_RTE_TOOLCHAIN_ICC=y\n\n#\n# KNI is not supported on 32-bit\n#\nCONFIG_RTE_LIBRTE_KNI=n\n\n#\n# Vectorized PMD is not supported on 32-bit\n#\nCONFIG_RTE_IXGBE_INC_VECTOR=n\n" }, { "path": "config/defconfig_ppc_64-power8-linuxapp-gcc", "content": "# BSD LICENSE\n#\n# Copyright (C) IBM Corporation 2014.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of IBM Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#include \"common_linuxapp\"\n\nCONFIG_RTE_MACHINE=\"power8\"\n\nCONFIG_RTE_ARCH=\"ppc_64\"\nCONFIG_RTE_ARCH_PPC_64=y\nCONFIG_RTE_ARCH_64=y\n\nCONFIG_RTE_TOOLCHAIN=\"gcc\"\nCONFIG_RTE_TOOLCHAIN_GCC=y\n\n# Note: Power doesn't have this support\nCONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n\n\n# Note: Initially, all of the PMD drivers compilation are turned off on Power\n# Will turn on them only after the successful testing on Power\nCONFIG_RTE_LIBRTE_IXGBE_PMD=n\nCONFIG_RTE_LIBRTE_I40E_PMD=n\nCONFIG_RTE_LIBRTE_VIRTIO_PMD=n\nCONFIG_RTE_LIBRTE_VMXNET3_PMD=n\nCONFIG_RTE_LIBRTE_PMD_BOND=n\nCONFIG_RTE_LIBRTE_ENIC_PMD=n\n\n# This following libraries are not available on Power. So they're turned off.\nCONFIG_RTE_LIBRTE_LPM=n\nCONFIG_RTE_LIBRTE_ACL=n\nCONFIG_RTE_LIBRTE_SCHED=n\nCONFIG_RTE_LIBRTE_PORT=n\nCONFIG_RTE_LIBRTE_TABLE=n\nCONFIG_RTE_LIBRTE_PIPELINE=n\n" }, { "path": "config/defconfig_tile-tilegx-linuxapp-gcc", "content": "# BSD LICENSE\n#\n# Copyright (C) EZchip Semiconductor 2015.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of EZchip Semiconductor nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#include \"common_linuxapp\"\n\nCONFIG_RTE_MACHINE=\"tilegx\"\n\nCONFIG_RTE_ARCH=\"tile\"\nCONFIG_RTE_ARCH_TILE=y\nCONFIG_RTE_ARCH_64=y\nCONFIG_RTE_ARCH_STRICT_ALIGN=y\nCONFIG_RTE_FORCE_INTRINSICS=y\n\nCONFIG_RTE_TOOLCHAIN=\"gcc\"\nCONFIG_RTE_TOOLCHAIN_GCC=y\n\nCONFIG_RTE_MEMPOOL_ALIGN=128\n\nCONFIG_RTE_LIBRTE_MPIPE_PMD=y\nCONFIG_RTE_LIBRTE_MPIPE_PMD_DEBUG=n\n\n# Disable things that we don't support or need\nCONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n\nCONFIG_RTE_EAL_IGB_UIO=n\nCONFIG_RTE_EAL_VFIO=n\nCONFIG_RTE_LIBRTE_KNI=n\nCONFIG_RTE_LIBRTE_XEN_DOM0=n\nCONFIG_RTE_LIBRTE_IGB_PMD=n\nCONFIG_RTE_LIBRTE_EM_PMD=n\nCONFIG_RTE_LIBRTE_IXGBE_PMD=n\nCONFIG_RTE_LIBRTE_I40E_PMD=n\nCONFIG_RTE_LIBRTE_FM10K_PMD=n\nCONFIG_RTE_LIBRTE_VIRTIO_PMD=n\nCONFIG_RTE_LIBRTE_VMXNET3_PMD=n\nCONFIG_RTE_LIBRTE_ENIC_PMD=n\n\n# This following libraries are not available on the tile architecture.\n# So they're turned off.\nCONFIG_RTE_LIBRTE_LPM=n\nCONFIG_RTE_LIBRTE_ACL=n\nCONFIG_RTE_LIBRTE_SCHED=n\nCONFIG_RTE_LIBRTE_PORT=n\nCONFIG_RTE_LIBRTE_TABLE=n\nCONFIG_RTE_LIBRTE_PIPELINE=n\n" }, { "path": "config/defconfig_x86_64-ivshmem-linuxapp-gcc", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\n#\n# use default config\n#\n\n#include \"defconfig_x86_64-native-linuxapp-gcc\"\n\n#\n# Compile IVSHMEM library\n#\nCONFIG_RTE_LIBRTE_IVSHMEM=y\nCONFIG_RTE_LIBRTE_IVSHMEM_DEBUG=n\nCONFIG_RTE_LIBRTE_IVSHMEM_MAX_PCI_DEVS=4\nCONFIG_RTE_LIBRTE_IVSHMEM_MAX_ENTRIES=128\nCONFIG_RTE_LIBRTE_IVSHMEM_MAX_METADATA_FILES=32\n\n# Set EAL to single file segments\nCONFIG_RTE_EAL_SINGLE_FILE_SEGMENTS=y" }, { "path": "config/defconfig_x86_64-ivshmem-linuxapp-icc", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\n#\n# use default config\n#\n\n#include \"defconfig_x86_64-native-linuxapp-icc\"\n\n#\n# Compile IVSHMEM library\n#\nCONFIG_RTE_LIBRTE_IVSHMEM=y\nCONFIG_RTE_LIBRTE_IVSHMEM_DEBUG=n\nCONFIG_RTE_LIBRTE_IVSHMEM_MAX_PCI_DEVS=4\nCONFIG_RTE_LIBRTE_IVSHMEM_MAX_ENTRIES=128\nCONFIG_RTE_LIBRTE_IVSHMEM_MAX_METADATA_FILES=32\n\n# Set EAL to single file segments\nCONFIG_RTE_EAL_SINGLE_FILE_SEGMENTS=y\n" }, { "path": "config/defconfig_x86_64-native-bsdapp-clang", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\n#include \"common_bsdapp\"\n\nCONFIG_RTE_MACHINE=\"native\"\n\nCONFIG_RTE_ARCH=\"x86_64\"\nCONFIG_RTE_ARCH_X86_64=y\n\nCONFIG_RTE_TOOLCHAIN=\"clang\"\nCONFIG_RTE_TOOLCHAIN_CLANG=y\n" }, { "path": "config/defconfig_x86_64-native-bsdapp-gcc", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\n#include \"common_bsdapp\"\n\nCONFIG_RTE_MACHINE=\"native\"\n\nCONFIG_RTE_ARCH=\"x86_64\"\nCONFIG_RTE_ARCH_X86_64=y\n\nCONFIG_RTE_TOOLCHAIN=\"gcc\"\nCONFIG_RTE_TOOLCHAIN_GCC=y\n" }, { "path": "config/defconfig_x86_64-native-linuxapp-clang", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\n#include \"common_linuxapp\"\n\nCONFIG_RTE_MACHINE=\"native\"\n\nCONFIG_RTE_ARCH=\"x86_64\"\nCONFIG_RTE_ARCH_X86_64=y\nCONFIG_RTE_ARCH_64=y\n\nCONFIG_RTE_TOOLCHAIN=\"clang\"\nCONFIG_RTE_TOOLCHAIN_CLANG=y\n" }, { "path": "config/defconfig_x86_64-native-linuxapp-gcc", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\n#include \"common_linuxapp\"\n\nCONFIG_RTE_MACHINE=\"native\"\n\nCONFIG_RTE_ARCH=\"x86_64\"\nCONFIG_RTE_ARCH_X86_64=y\nCONFIG_RTE_ARCH_64=y\n\nCONFIG_RTE_TOOLCHAIN=\"gcc\"\nCONFIG_RTE_TOOLCHAIN_GCC=y\n" }, { "path": "config/defconfig_x86_64-native-linuxapp-icc", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\n#include \"common_linuxapp\"\n\nCONFIG_RTE_MACHINE=\"native\"\n\nCONFIG_RTE_ARCH=\"x86_64\"\nCONFIG_RTE_ARCH_X86_64=y\nCONFIG_RTE_ARCH_64=y\n\nCONFIG_RTE_TOOLCHAIN=\"icc\"\nCONFIG_RTE_TOOLCHAIN_ICC=y\n" }, { "path": "config/defconfig_x86_x32-native-linuxapp-gcc", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\n#include \"common_linuxapp\"\n\nCONFIG_RTE_MACHINE=\"native\"\n\nCONFIG_RTE_ARCH=\"x86_x32\"\nCONFIG_RTE_ARCH_X86_X32=y\n\nCONFIG_RTE_TOOLCHAIN=\"gcc\"\nCONFIG_RTE_TOOLCHAIN_GCC=y\n\n#\n# KNI is not supported on 32-bit\n#\nCONFIG_RTE_LIBRTE_KNI=n\n" }, { "path": "doc/api/doxy-api-index.md", "content": "API {#index}\n===\n\n\n\nThere are many libraries, so their headers may be grouped by topics:\n\n- **device**:\n [dev] (@ref rte_dev.h),\n [ethdev] (@ref rte_ethdev.h),\n [ethctrl] (@ref rte_eth_ctrl.h),\n [devargs] (@ref rte_devargs.h),\n [bond] (@ref rte_eth_bond.h),\n [vhost] (@ref rte_virtio_net.h),\n [KNI] (@ref rte_kni.h),\n [PCI] (@ref rte_pci.h),\n [PCI IDs] (@ref rte_pci_dev_ids.h)\n\n- **memory**:\n [memseg] (@ref rte_memory.h),\n [memzone] (@ref rte_memzone.h),\n [mempool] (@ref rte_mempool.h),\n [malloc] (@ref rte_malloc.h),\n [memcpy] (@ref rte_memcpy.h)\n\n- **timers**:\n [cycles] (@ref rte_cycles.h),\n [timer] (@ref rte_timer.h),\n [alarm] (@ref rte_alarm.h)\n\n- **locks**:\n [atomic] (@ref rte_atomic.h),\n [rwlock] (@ref rte_rwlock.h),\n [spinlock] (@ref rte_spinlock.h)\n\n- **CPU arch**:\n [branch prediction] (@ref rte_branch_prediction.h),\n [cache prefetch] (@ref rte_prefetch.h),\n [byte order] (@ref rte_byteorder.h),\n [CPU flags] (@ref rte_cpuflags.h)\n\n- **CPU multicore**:\n [interrupts] (@ref rte_interrupts.h),\n [launch] (@ref rte_launch.h),\n [lcore] (@ref rte_lcore.h),\n [per-lcore] (@ref rte_per_lcore.h),\n [power/freq] (@ref rte_power.h)\n\n- **layers**:\n [ethernet] (@ref rte_ether.h),\n [ARP] (@ref rte_arp.h),\n [ICMP] (@ref rte_icmp.h),\n [IP] (@ref rte_ip.h),\n [SCTP] (@ref rte_sctp.h),\n [TCP] (@ref rte_tcp.h),\n [UDP] (@ref rte_udp.h),\n [frag/reass] (@ref rte_ip_frag.h),\n [LPM IPv4 route] (@ref rte_lpm.h),\n [LPM IPv6 route] (@ref rte_lpm6.h),\n [ACL] (@ref rte_acl.h)\n\n- **QoS**:\n [metering] (@ref rte_meter.h),\n [scheduler] (@ref rte_sched.h),\n [RED congestion] (@ref rte_red.h)\n\n- **hashes**:\n [hash] (@ref rte_hash.h),\n [jhash] (@ref rte_jhash.h),\n [thash] (@ref rte_thash.h),\n [FBK hash] (@ref rte_fbk_hash.h),\n [CRC hash] (@ref rte_hash_crc.h)\n\n- **containers**:\n [mbuf] (@ref rte_mbuf.h),\n [ring] (@ref rte_ring.h),\n [distributor] (@ref rte_distributor.h),\n [reorder] (@ref rte_reorder.h),\n [tailq] (@ref rte_tailq.h),\n [bitmap] (@ref rte_bitmap.h),\n [ivshmem] (@ref rte_ivshmem.h)\n\n- **packet framework**:\n * [port] (@ref rte_port.h):\n [ethdev] (@ref rte_port_ethdev.h),\n [ring] (@ref rte_port_ring.h),\n [frag] (@ref rte_port_frag.h),\n [reass] (@ref rte_port_ras.h),\n [sched] (@ref rte_port_sched.h),\n [src/sink] (@ref rte_port_source_sink.h)\n * [table] (@ref rte_table.h):\n [lpm IPv4] (@ref rte_table_lpm.h),\n [lpm IPv6] (@ref rte_table_lpm_ipv6.h),\n [ACL] (@ref rte_table_acl.h),\n [hash] (@ref rte_table_hash.h),\n [array] (@ref rte_table_array.h),\n [stub] (@ref rte_table_stub.h)\n * [pipeline] (@ref rte_pipeline.h)\n\n- **basic**:\n [approx fraction] (@ref rte_approx.h),\n [random] (@ref rte_random.h),\n [config file] (@ref rte_cfgfile.h),\n [key/value args] (@ref rte_kvargs.h),\n [string] (@ref rte_string_fns.h)\n\n- **debug**:\n [jobstats] (@ref rte_jobstats.h),\n [hexdump] (@ref rte_hexdump.h),\n [debug] (@ref rte_debug.h),\n [log] (@ref rte_log.h),\n [warnings] (@ref rte_warnings.h),\n [errno] (@ref rte_errno.h)\n\n- **misc**:\n [EAL config] (@ref rte_eal.h),\n [common] (@ref rte_common.h),\n [ABI compat] (@ref rte_compat.h),\n [version] (@ref rte_version.h)\n" }, { "path": "doc/api/doxy-api.conf", "content": "# BSD LICENSE\n#\n# Copyright 2013 6WIND S.A.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nPROJECT_NAME = DPDK\nINPUT = doc/api/doxy-api-index.md \\\n drivers/net/bonding \\\n lib/librte_eal/common/include \\\n lib/librte_eal/common/include/generic \\\n lib/librte_acl \\\n lib/librte_cfgfile \\\n lib/librte_cmdline \\\n lib/librte_compat \\\n lib/librte_distributor \\\n lib/librte_ether \\\n lib/librte_hash \\\n lib/librte_ip_frag \\\n lib/librte_ivshmem \\\n lib/librte_jobstats \\\n lib/librte_kni \\\n lib/librte_kvargs \\\n lib/librte_lpm \\\n lib/librte_mbuf \\\n lib/librte_mempool \\\n lib/librte_meter \\\n lib/librte_net \\\n lib/librte_pipeline \\\n lib/librte_port \\\n lib/librte_power \\\n lib/librte_reorder \\\n lib/librte_ring \\\n lib/librte_sched \\\n lib/librte_table \\\n lib/librte_timer \\\n lib/librte_vhost\nFILE_PATTERNS = rte_*.h \\\n cmdline.h\nPREDEFINED = __DOXYGEN__ \\\n __attribute__(x)=\n\nOPTIMIZE_OUTPUT_FOR_C = YES\nENABLE_PREPROCESSING = YES\nMACRO_EXPANSION = YES\nEXPAND_ONLY_PREDEF = YES\nEXTRACT_STATIC = YES\nDISTRIBUTE_GROUP_DOC = YES\nHIDE_UNDOC_MEMBERS = YES\nHIDE_UNDOC_CLASSES = YES\nHIDE_SCOPE_NAMES = YES\nGENERATE_DEPRECATEDLIST = NO\nVERBATIM_HEADERS = NO\nALPHABETICAL_INDEX = NO\n\nHTML_TIMESTAMP = NO\nHTML_DYNAMIC_SECTIONS = YES\nSEARCHENGINE = NO\nSORT_MEMBER_DOCS = NO\nSOURCE_BROWSER = YES\n" }, { "path": "doc/api/doxy-html-custom.sh", "content": "#! /bin/sh -e\n\n# BSD LICENSE\n#\n# Copyright 2013 6WIND S.A.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nCSS=$1\n\n# space between item and its comment\necho 'dd td:first-child {padding-right: 2em;}' >> $CSS\n" }, { "path": "doc/build-sdk-quick.txt", "content": "Basic build\n\tmake config T=x86_64-native-linuxapp-gcc && make\nBuild commands\n\tconfig get configuration from target template (T=)\n\tall same as build (default rule)\n\tbuild build in a configured directory\n\tclean remove files but keep configuration\n\tinstall build many targets (wildcard allowed) and install in DESTDIR\n\tuninstall remove all installed targets\n\texamples build examples for given targets (T=)\n\texamples_clean clean examples for given targets (T=)\nBuild variables\n\tEXTRA_CPPFLAGS preprocessor options\n\tEXTRA_CFLAGS compiler options\n\tEXTRA_LDFLAGS linker options\n\tEXTRA_LDLIBS linker library options\n\tRTE_KERNELDIR linux headers path\n\tCROSS toolchain prefix\n\tV verbose\n\tD debug dependencies\n\tO build directory (default: build/ - install default: ./)\n\tDESTDIR second-stage install directory\n\tT target template (install default: *) - used with config or install\n\t\t\tformat: \n\t\t\ttemplates in config/defconfig_*\n" }, { "path": "doc/guides/conf.py", "content": "# BSD LICENSE\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nimport subprocess\nfrom docutils import nodes\nfrom distutils.version import LooseVersion\nfrom sphinx import __version__ as sphinx_version\nfrom sphinx.highlighting import PygmentsBridge\nfrom pygments.formatters.latex import LatexFormatter\n\nproject = 'DPDK'\n\nhtml_show_copyright = False\nhighlight_language = 'none'\n\nversion = subprocess.check_output(['make', '-sRrC', '../../', 'showversion']).decode('utf-8')\nrelease = version\n\nmaster_doc = 'index'\n\n# Figures, tables and code-blocks automatically numbered if they have caption\nnumfig = True\n\nlatex_documents = [\n ('index',\n 'doc.tex',\n '',\n '',\n 'manual')\n]\n\n# Latex directives to be included directly in the latex/pdf docs.\nlatex_preamble = r\"\"\"\n\\usepackage[utf8]{inputenc}\n\\usepackage{DejaVuSansMono}\n\\usepackage[T1]{fontenc}\n\\usepackage{helvet}\n\\renewcommand{\\familydefault}{\\sfdefault}\n\\RecustomVerbatimEnvironment{Verbatim}{Verbatim}{xleftmargin=5mm}\n\"\"\"\n\n# Configuration for the latex/pdf docs.\nlatex_elements = {\n 'papersize': 'a4paper',\n 'pointsize': '11pt',\n # remove blank pages\n 'classoptions': ',openany,oneside',\n 'babel': '\\\\usepackage[english]{babel}',\n # customize Latex formatting\n 'preamble': latex_preamble\n}\n\n# Override the default Latex formatter in order to modify the\n# code/verbatim blocks.\nclass CustomLatexFormatter(LatexFormatter):\n def __init__(self, **options):\n super(CustomLatexFormatter, self).__init__(**options)\n # Use the second smallest font size for code/verbatim blocks.\n self.verboptions = r'formatcom=\\footnotesize'\n\n# Replace the default latex formatter.\nPygmentsBridge.latex_formatter = CustomLatexFormatter\n\n######## :numref: fallback ########\n# The following hook functions add some simple handling for the :numref:\n# directive for Sphinx versions prior to 1.3.1. The functions replace the\n# :numref: reference with a link to the target (for all Sphinx doc types).\n# It doesn't try to label figures/tables.\n\ndef numref_role(reftype, rawtext, text, lineno, inliner):\n \"\"\"\n Add a Sphinx role to handle numref references. Note, we can't convert\n the link here because the doctree isn't build and the target information\n isn't available.\n \"\"\"\n # Add an identifier to distinguish numref from other references.\n newnode = nodes.reference('',\n '',\n refuri='_local_numref_#%s' % text,\n internal=True)\n return [newnode], []\n\ndef process_numref(app, doctree, from_docname):\n \"\"\"\n Process the numref nodes once the doctree has been built and prior to\n writing the files. The processing involves replacing the numref with a\n link plus text to indicate if it is a Figure or Table link.\n \"\"\"\n\n # Iterate over the reference nodes in the doctree.\n for node in doctree.traverse(nodes.reference):\n target = node.get('refuri', '')\n\n # Look for numref nodes.\n if target.startswith('_local_numref_#'):\n target = target.replace('_local_numref_#', '')\n\n # Get the target label and link information from the Sphinx env.\n data = app.builder.env.domains['std'].data\n docname, label, _ = data['labels'].get(target, ('', '', ''))\n relative_url = app.builder.get_relative_uri(from_docname, docname)\n\n # Add a text label to the link.\n if target.startswith('figure'):\n caption = 'Figure'\n elif target.startswith('table'):\n caption = 'Table'\n else:\n caption = 'Link'\n\n # New reference node with the updated link information.\n newnode = nodes.reference('',\n caption,\n refuri='%s#%s' % (relative_url, label),\n internal=True)\n node.replace_self(newnode)\n\ndef setup(app):\n if LooseVersion(sphinx_version) < LooseVersion('1.3.1'):\n print('Upgrade sphinx to version >= 1.3.1 for '\n 'improved Figure/Table number handling.')\n # Add a role to handle :numref: references.\n app.add_role('numref', numref_role)\n # Process the numref references once the doctree has been created.\n app.connect('doctree-resolved', process_numref)\n" }, { "path": "doc/guides/contributing/coding_style.rst", "content": ".. _coding_style:\n\nDPDK Coding Style\n=================\n\nDescription\n-----------\n\nThis document specifies the preferred style for source files in the DPDK source tree.\nIt is based on the Linux Kernel coding guidelines and the FreeBSD 7.2 Kernel Developer's Manual (see man style(9)), but was heavily modified for the needs of the DPDK.\n\nGeneral Guidelines\n------------------\n\nThe rules and guidelines given in this document cannot cover every situation, so the following general guidelines should be used as a fallback:\n\n* The code style should be consistent within each individual file.\n* In the case of creating new files, the style should be consistent within each file in a given directory or module.\n* The primary reason for coding standards is to increase code readability and comprehensibility, therefore always use whatever option will make the code easiest to read.\n\nLine length is recommended to be not more than 80 characters, including comments.\n[Tab stop size should be assumed to be 8-characters wide].\n\n.. note::\n\n\tThe above is recommendation, and not a hard limit.\n\tHowever, it is expected that the recommendations should be followed in all but the rarest situations.\n\nC Comment Style\n---------------\n\nUsual Comments\n~~~~~~~~~~~~~~\n\nThese comments should be used in normal cases.\nTo document a public API, a doxygen-like format must be used: refer to :ref:`doxygen_guidelines`.\n\n.. code-block:: c\n\n /*\n * VERY important single-line comments look like this.\n */\n\n /* Most single-line comments look like this. */\n\n /*\n * Multi-line comments look like this. Make them real sentences. Fill\n * them so they look like real paragraphs.\n */\n\nLicense Header\n~~~~~~~~~~~~~~\n\nEach file should begin with a special comment containing the appropriate copyright and license for the file.\nGenerally this is the BSD License, except for code for Linux Kernel modules.\nAfter any copyright header, a blank line should be left before any other contents, e.g. include statements in a C file.\n\nC Preprocessor Directives\n-------------------------\n\nHeader Includes\n~~~~~~~~~~~~~~~\n\nIn DPDK sources, the include files should be ordered as following:\n\n#. libc includes (system includes first)\n#. DPDK EAL includes\n#. DPDK misc libraries includes\n#. application-specific includes\n\nInclude files from the local application directory are included using quotes, while includes from other paths are included using angle brackets: \"<>\".\n\nExample:\n\n.. code-block:: c\n\n #include \n #include \n\n #include \n\n #include \n #include \n\n #include \"application.h\"\n\nHeader File Guards\n~~~~~~~~~~~~~~~~~~\n\nHeaders should be protected against multiple inclusion with the usual:\n\n.. code-block:: c\n\n #ifndef _FILE_H_\n #define _FILE_H_\n\n /* Code */\n\n #endif /* _FILE_H_ */\n\n\nMacros\n~~~~~~\n\nDo not ``#define`` or declare names except with the standard DPDK prefix: ``RTE_``.\nThis is to ensure there are no collisions with definitions in the application itself.\n\nThe names of \"unsafe\" macros (ones that have side effects), and the names of macros for manifest constants, are all in uppercase.\n\nThe expansions of expression-like macros are either a single token or have outer parentheses.\nIf a macro is an inline expansion of a function, the function name is all in lowercase and the macro has the same name all in uppercase.\nIf the macro encapsulates a compound statement, enclose it in a do-while loop, so that it can be used safely in if statements.\nAny final statement-terminating semicolon should be supplied by the macro invocation rather than the macro, to make parsing easier for pretty-printers and editors.\n\nFor example:\n\n.. code-block:: c\n\n #define MACRO(x, y) do { \\\n variable = (x) + (y); \\\n (y) += 2; \\\n } while(0)\n\n.. note::\n\n Wherever possible, enums and inline functions should be preferred to macros, since they provide additional degrees of type-safety and can allow compilers to emit extra warnings about unsafe code.\n\nConditional Compilation\n~~~~~~~~~~~~~~~~~~~~~~~\n\n* When code is conditionally compiled using ``#ifdef`` or ``#if``, a comment may be added following the matching\n ``#endif`` or ``#else`` to permit the reader to easily discern where conditionally compiled code regions end.\n* This comment should be used only for (subjectively) long regions, regions greater than 20 lines, or where a series of nested ``#ifdef``'s may be confusing to the reader.\n Exceptions may be made for cases where code is conditionally not compiled for the purposes of lint(1), or other tools, even though the uncompiled region may be small.\n* The comment should be separated from the ``#endif`` or ``#else`` by a single space.\n* For short conditionally compiled regions, a closing comment should not be used.\n* The comment for ``#endif`` should match the expression used in the corresponding ``#if`` or ``#ifdef``.\n* The comment for ``#else`` and ``#elif`` should match the inverse of the expression(s) used in the preceding ``#if`` and/or ``#elif`` statements.\n* In the comments, the subexpression ``defined(FOO)`` is abbreviated as \"FOO\".\n For the purposes of comments, ``#ifndef FOO`` is treated as ``#if !defined(FOO)``.\n\n.. code-block:: c\n\n #ifdef KTRACE\n #include \n #endif\n\n #ifdef COMPAT_43\n /* A large region here, or other conditional code. */\n #else /* !COMPAT_43 */\n /* Or here. */\n #endif /* COMPAT_43 */\n\n #ifndef COMPAT_43\n /* Yet another large region here, or other conditional code. */\n #else /* COMPAT_43 */\n /* Or here. */\n #endif /* !COMPAT_43 */\n\n.. note::\n\n Conditional compilation should be used only when absolutely necessary, as it increases the number of target binaries that need to be built and tested.\n\nC Types\n-------\n\nIntegers\n~~~~~~~~\n\nFor fixed/minimum-size integer values, the project uses the form uintXX_t (from stdint.h) instead of older BSD-style integer identifiers of the form u_intXX_t.\n\nEnumerations\n~~~~~~~~~~~~\n\n* Enumeration values are all uppercase.\n\n.. code-block:: c\n\n enum enumtype { ONE, TWO } et;\n\n* Enum types should be used in preference to macros #defining a set of (sequential) values.\n* Enum types should be prefixed with ``rte_`` and the elements by a suitable prefix [generally starting ``RTE__`` - where is a shortname for the enum type] to avoid namespace collisions.\n\nBitfields\n~~~~~~~~~\n\nThe developer should group bitfields that are included in the same integer, as follows:\n\n.. code-block:: c\n\n struct grehdr {\n uint16_t rec:3,\n srr:1,\n seq:1,\n key:1,\n routing:1,\n csum:1,\n version:3,\n reserved:4,\n ack:1;\n /* ... */\n }\n\nVariable Declarations\n~~~~~~~~~~~~~~~~~~~~~\n\nIn declarations, do not put any whitespace between asterisks and adjacent tokens, except for tokens that are identifiers related to types.\n(These identifiers are the names of basic types, type qualifiers, and typedef-names other than the one being declared.)\nSeparate these identifiers from asterisks using a single space.\n\nFor example:\n\n.. code-block:: c\n\n int *x; /* no space after asterisk */\n int * const x; /* space after asterisk when using a type qualifier */\n\n* All externally-visible variables should have an ``rte_`` prefix in the name to avoid namespace collisions.\n* Do not use uppercase letters - either in the form of ALL_UPPERCASE, or CamelCase - in variable names.\n Lower-case letters and underscores only.\n\nStructure Declarations\n~~~~~~~~~~~~~~~~~~~~~~\n\n* In general, when declaring variables in new structures, declare them sorted by use, then by size (largest to smallest), and then in alphabetical order.\n Sorting by use means that commonly used variables are used together and that the structure layout makes logical sense.\n Ordering by size then ensures that as little padding is added to the structure as possible.\n* For existing structures, additions to structures should be added to the end so for backward compatibility reasons.\n* Each structure element gets its own line.\n* Try to make the structure readable by aligning the member names using spaces as shown below.\n* Names following extremely long types, which therefore cannot be easily aligned with the rest, should be separated by a single space.\n\n.. code-block:: c\n\n struct foo {\n struct foo *next; /* List of active foo. */\n struct mumble amumble; /* Comment for mumble. */\n int bar; /* Try to align the comments. */\n struct verylongtypename *baz; /* Won't fit with other members */\n };\n\n\n* Major structures should be declared at the top of the file in which they are used, or in separate header files if they are used in multiple source files.\n* Use of the structures should be by separate variable declarations and those declarations must be extern if they are declared in a header file.\n* Externally visible structure definitions should have the structure name prefixed by ``rte_`` to avoid namespace collisions.\n\nQueues\n~~~~~~\n\nUse queue(3) macros rather than rolling your own lists, whenever possible.\nThus, the previous example would be better written:\n\n.. code-block:: c\n\n #include \n\n struct foo {\n LIST_ENTRY(foo) link; /* Use queue macros for foo lists. */\n struct mumble amumble; /* Comment for mumble. */\n int bar; /* Try to align the comments. */\n struct verylongtypename *baz; /* Won't fit with other members */\n };\n LIST_HEAD(, foo) foohead; /* Head of global foo list. */\n\n\nDPDK also provides an optimized way to store elements in lockless rings.\nThis should be used in all data-path code, when there are several consumer and/or producers to avoid locking for concurrent access.\n\nTypedefs\n~~~~~~~~\n\nAvoid using typedefs for structure types.\n\nFor example, use:\n\n.. code-block:: c\n\n struct my_struct_type {\n /* ... */\n };\n\n struct my_struct_type my_var;\n\n\nrather than:\n\n.. code-block:: c\n\n typedef struct my_struct_type {\n /* ... */\n } my_struct_type;\n\n my_struct_type my_var\n\n\nTypedefs are problematic because they do not properly hide their underlying type;\nfor example, you need to know if the typedef is the structure itself, as shown above, or a pointer to the structure.\nIn addition, they must be declared exactly once, whereas an incomplete structure type can be mentioned as many times as necessary.\nTypedefs are difficult to use in stand-alone header files.\nThe header that defines the typedef must be included before the header that uses it, or by the header that uses it (which causes namespace pollution),\nor there must be a back-door mechanism for obtaining the typedef.\n\nNote that #defines used instead of typedefs also are problematic (since they do not propagate the pointer type correctly due to direct text replacement).\nFor example, ``#define pint int *`` does not work as expected, while ``typedef int *pint`` does work.\nAs stated when discussing macros, typedefs should be preferred to macros in cases like this.\n\nWhen convention requires a typedef; make its name match the struct tag.\nAvoid typedefs ending in ``_t``, except as specified in Standard C or by POSIX.\n\n.. note::\n\n\tIt is recommended to use typedefs to define function pointer types, for reasons of code readability.\n\tThis is especially true when the function type is used as a parameter to another function.\n\nFor example:\n\n.. code-block:: c\n\n\t/**\n\t * Definition of a remote launch function.\n\t */\n\ttypedef int (lcore_function_t)(void *);\n\n\t/* launch a function of lcore_function_t type */\n\tint rte_eal_remote_launch(lcore_function_t *f, void *arg, unsigned slave_id);\n\n\nC Indentation\n-------------\n\nGeneral\n~~~~~~~\n\n* Indentation is a hard tab, that is, a tab character, not a sequence of spaces,\n\n.. note::\n\n\tGlobal whitespace rule in DPDK, use tabs for indentation, spaces for alignment.\n\n* Do not put any spaces before a tab for indentation.\n* If you have to wrap a long statement, put the operator at the end of the line, and indent again.\n* For control statements (if, while, etc.), continuation it is recommended that the next line be indented by two tabs, rather than one,\n to prevent confusion as to whether the second line of the control statement forms part of the statement body or not.\n Alternatively, the line continuation may use additional spaces to line up to an appropriately point on the preceding line, for example, to align to an opening brace.\n\n.. note::\n\n\tAs with all style guidelines, code should match style already in use in an existing file.\n\n.. code-block:: c\n\n while (really_long_variable_name_1 == really_long_variable_name_2 &&\n var3 == var4){ /* confusing to read as */\n x = y + z; /* control stmt body lines up with second line of */\n a = b + c; /* control statement itself if single indent used */\n }\n\n if (really_long_variable_name_1 == really_long_variable_name_2 &&\n var3 == var4){ /* two tabs used */\n x = y + z; /* statement body no longer lines up */\n a = b + c;\n }\n\n z = a + really + long + statement + that + needs +\n two + lines + gets + indented + on + the +\n second + and + subsequent + lines;\n\n\n* Do not add whitespace at the end of a line.\n\n* Do not add whitespace or a blank line at the end of a file.\n\n\nControl Statements and Loops\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n* Include a space after keywords (if, while, for, return, switch).\n* Do not use braces (``{`` and ``}``) for control statements with zero or just a single statement, unless that statement is more than a single line in which case the braces are permitted.\n\n.. code-block:: c\n\n for (p = buf; *p != '\\0'; ++p)\n ; /* nothing */\n for (;;)\n stmt;\n for (;;) {\n z = a + really + long + statement + that + needs +\n two + lines + gets + indented + on + the +\n second + and + subsequent + lines;\n }\n for (;;) {\n if (cond)\n stmt;\n }\n if (val != NULL)\n val = realloc(val, newsize);\n\n\n* Parts of a for loop may be left empty.\n\n.. code-block:: c\n\n for (; cnt < 15; cnt++) {\n stmt1;\n stmt2;\n }\n\n* Closing and opening braces go on the same line as the else keyword.\n* Braces that are not necessary should be left out.\n\n.. code-block:: c\n\n if (test)\n stmt;\n else if (bar) {\n stmt;\n stmt;\n } else\n stmt;\n\n\nFunction Calls\n~~~~~~~~~~~~~~\n\n* Do not use spaces after function names.\n* Commas should have a space after them.\n* No spaces after ``(`` or ``[`` or preceding the ``]`` or ``)`` characters.\n\n.. code-block:: c\n\n\terror = function(a1, a2);\n\tif (error != 0)\n\t\texit(error);\n\n\nOperators\n~~~~~~~~~\n\n* Unary operators do not require spaces, binary operators do.\n* Do not use parentheses unless they are required for precedence or unless the statement is confusing without them.\n However, remember that other people may be more easily confused than you.\n\nExit\n~~~~\n\nExits should be 0 on success, or 1 on failure.\n\n.. code-block:: c\n\n exit(0); /*\n * Avoid obvious comments such as\n * \"Exit 0 on success.\"\n */\n }\n\nLocal Variables\n~~~~~~~~~~~~~~~\n\n* Variables should be declared at the start of a block of code rather than in the middle.\n The exception to this is when the variable is ``const`` in which case the declaration must be at the point of first use/assignment.\n* When declaring variables in functions, multiple variables per line are OK.\n However, if multiple declarations would cause the line to exceed a reasonable line length, begin a new set of declarations on the next line rather than using a line continuation.\n* Be careful to not obfuscate the code by initializing variables in the declarations, only the last variable on a line should be initialized.\n If multiple variables are to be initialised when defined, put one per line.\n* Do not use function calls in initializers, except for ``const`` variables.\n\n.. code-block:: c\n\n int i = 0, j = 0, k = 0; /* bad, too many initializer */\n\n char a = 0; /* OK, one variable per line with initializer */\n char b = 0;\n\n float x, y = 0.0; /* OK, only last variable has initializer */\n\n\nCasts and sizeof\n~~~~~~~~~~~~~~~~\n\n* Casts and sizeof statements are not followed by a space.\n* Always write sizeof statements with parenthesis.\n The redundant parenthesis rules do not apply to sizeof(var) instances.\n\nC Function Definition, Declaration and Use\n-------------------------------------------\n\nPrototypes\n~~~~~~~~~~\n\n* It is recommended (and generally required by the compiler) that all non-static functions are prototyped somewhere.\n* Functions local to one source module should be declared static, and should not be prototyped unless absolutely necessary.\n* Functions used from other parts of code (external API) must be prototyped in the relevant include file.\n* Function prototypes should be listed in a logical order, preferably alphabetical unless there is a compelling reason to use a different ordering.\n* Functions that are used locally in more than one module go into a separate header file, for example, \"extern.h\".\n* Do not use the ``__P`` macro.\n* Functions that are part of an external API should be documented using Doxygen-like comments above declarations. See :ref:`doxygen_guidelines` for details.\n* Functions that are part of the external API must have an ``rte_`` prefix on the function name.\n* Do not use uppercase letters - either in the form of ALL_UPPERCASE, or CamelCase - in function names. Lower-case letters and underscores only.\n* When prototyping functions, associate names with parameter types, for example:\n\n.. code-block:: c\n\n void function1(int fd); /* good */\n void function2(int); /* bad */\n\n* Short function prototypes should be contained on a single line.\n Longer prototypes, e.g. those with many parameters, can be split across multiple lines.\n The second and subsequent lines should be further indented as for line statement continuations as described in the previous section.\n\n.. code-block:: c\n\n static char *function1(int _arg, const char *_arg2,\n struct foo *_arg3,\n struct bar *_arg4,\n struct baz *_arg5);\n static void usage(void);\n\n.. note::\n\n\tUnlike function definitions, the function prototypes do not need to place the function return type on a separate line.\n\nDefinitions\n~~~~~~~~~~~\n\n* The function type should be on a line by itself preceding the function.\n* The opening brace of the function body should be on a line by itself.\n\n.. code-block:: c\n\n static char *\n function(int a1, int a2, float fl, int a4)\n {\n\n\n* Do not declare functions inside other functions.\n ANSI C states that such declarations have file scope regardless of the nesting of the declaration.\n Hiding file declarations in what appears to be a local scope is undesirable and will elicit complaints from a good compiler.\n* Old-style (K&R) function declaration should not be used, use ANSI function declarations instead as shown below.\n* Long argument lists should be wrapped as described above in the function prototypes section.\n\n.. code-block:: c\n\n /*\n * All major routines should have a comment briefly describing what\n * they do. The comment before the \"main\" routine should describe\n * what the program does.\n */\n int\n main(int argc, char *argv[])\n {\n char *ep;\n long num;\n int ch;\n\nC Statement Style and Conventions\n---------------------------------\n\nNULL Pointers\n~~~~~~~~~~~~~\n\n* NULL is the preferred null pointer constant.\n Use NULL instead of ``(type *)0`` or ``(type *)NULL``, except where the compiler does not know the destination type e.g. for variadic args to a function.\n* Test pointers against NULL, for example, use:\n\n.. code-block:: c\n\n if (p == NULL) /* Good, compare pointer to NULL */\n\n if (!p) /* Bad, using ! on pointer */\n\n\n* Do not use ! for tests unless it is a boolean, for example, use:\n\n.. code-block:: c\n\n\tif (*p == '\\0') /* check character against (char)0 */\n\nReturn Value\n~~~~~~~~~~~~\n\n* Functions which create objects, or allocate memory, should return pointer types, and NULL on error.\n The error type should be indicated may setting the variable ``rte_errno`` appropriately.\n* Functions which work on bursts of packets, such as RX-like or TX-like functions, should return the number of packets handled.\n* Other functions returning int should generally behave like system calls:\n returning 0 on success and -1 on error, setting ``rte_errno`` to indicate the specific type of error.\n* Where already standard in a given library, the alternative error approach may be used where the negative value is not -1 but is instead ``-errno`` if relevant, for example, ``-EINVAL``.\n Note, however, to allow consistency across functions returning integer or pointer types, the previous approach is preferred for any new libraries.\n* For functions where no error is possible, the function type should be ``void`` not ``int``.\n* Routines returning ``void *`` should not have their return values cast to any pointer type.\n (Typecasting can prevent the compiler from warning about missing prototypes as any implicit definition of a function returns int,\n which, unlike ``void *``, needs a typecast to assign to a pointer variable.)\n\n.. note::\n\n\tThe above rule about not typecasting ``void *`` applies to malloc, as well as to DPDK functions.\n\n* Values in return statements should not be enclosed in parentheses.\n\nLogging and Errors\n~~~~~~~~~~~~~~~~~~\n\nIn the DPDK environment, use the logging interface provided:\n\n.. code-block:: c\n\n #define RTE_LOGTYPE_TESTAPP1 RTE_LOGTYPE_USER1\n #define RTE_LOGTYPE_TESTAPP2 RTE_LOGTYPE_USER2\n\n /* enable these logs type */\n rte_set_log_type(RTE_LOGTYPE_TESTAPP1, 1);\n rte_set_log_type(RTE_LOGTYPE_TESTAPP2, 1);\n\n /* log in debug level */\n rte_set_log_level(RTE_LOG_DEBUG);\n RTE_LOG(DEBUG, TESTAPP1, \"this is is a debug level message\\n\");\n RTE_LOG(INFO, TESTAPP1, \"this is is a info level message\\n\");\n RTE_LOG(WARNING, TESTAPP1, \"this is is a warning level message\\n\");\n\n /* log in info level */\n rte_set_log_level(RTE_LOG_INFO);\n RTE_LOG(DEBUG, TESTAPP2, \"debug level message (not displayed)\\n\");\n\nBranch Prediction\n~~~~~~~~~~~~~~~~~\n\n* When a test is done in a critical zone (called often or in a data path) the code can use the ``likely()`` and ``unlikely()`` macros to indicate the expected, or preferred fast path.\n They are expanded as a compiler builtin and allow the developer to indicate if the branch is likely to be taken or not. Example:\n\n.. code-block:: c\n\n #include \n if (likely(x > 1))\n do_stuff();\n\n.. note::\n\n\tThe use of ``likely()`` and ``unlikely()`` should only be done in performance critical paths,\n\tand only when there is a clearly preferred path, or a measured performance increase gained from doing so.\n\tThese macros should be avoided in non-performance-critical code.\n\nStatic Variables and Functions\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n* All functions and variables that are local to a file must be declared as ``static`` because it can often help the compiler to do some optimizations (such as, inlining the code).\n* Functions that should be inlined should to be declared as ``static inline`` and can be defined in a .c or a .h file.\n\n.. note::\n\tStatic functions defined in a header file must be declared as ``static inline`` in order to prevent compiler warnings about the function being unused.\n\nConst Attribute\n~~~~~~~~~~~~~~~\n\nThe ``const`` attribute should be used as often as possible when a variable is read-only.\n\nInline ASM in C code\n~~~~~~~~~~~~~~~~~~~~\n\nThe ``asm`` and ``volatile`` keywords do not have underscores. The AT&T syntax should be used.\nInput and output operands should be named to avoid confusion, as shown in the following example:\n\n.. code-block:: c\n\n\tasm volatile(\"outb %[val], %[port]\"\n\t\t: :\n\t\t[port] \"dN\" (port),\n\t\t[val] \"a\" (val));\n\nControl Statements\n~~~~~~~~~~~~~~~~~~\n\n* Forever loops are done with for statements, not while statements.\n* Elements in a switch statement that cascade should have a FALLTHROUGH comment. For example:\n\n.. code-block:: c\n\n switch (ch) { /* Indent the switch. */\n case 'a': /* Don't indent the case. */\n aflag = 1; /* Indent case body one tab. */\n /* FALLTHROUGH */\n case 'b':\n bflag = 1;\n break;\n case '?':\n default:\n usage();\n /* NOTREACHED */\n }\n" }, { "path": "doc/guides/contributing/design.rst", "content": "Design\n======\n\nEnvironment or Architecture-specific Sources\n--------------------------------------------\n\nIn DPDK and DPDK applications, some code is specific to an architecture (i686, x86_64) or to an executive environment (bsdapp or linuxapp) and so on.\nAs far as is possible, all such instances of architecture or env-specific code should be provided via standard APIs in the EAL.\n\nBy convention, a file is common if it is not located in a directory indicating that it is specific.\nFor instance, a file located in a subdir of \"x86_64\" directory is specific to this architecture.\nA file located in a subdir of \"linuxapp\" is specific to this execution environment.\n\n.. note::\n\n\tCode in DPDK libraries and applications should be generic.\n\tThe correct location for architecture or executive environment specific code is in the EAL.\n\nWhen absolutely necessary, there are several ways to handle specific code:\n\n* Use a ``#ifdef`` with the CONFIG option in the C code.\n This can be done when the differences are small and they can be embedded in the same C file:\n\n.. code-block: console\n\n #ifdef RTE_ARCH_I686\n toto();\n #else\n titi();\n #endif\n\n* Use the CONFIG option in the Makefile. This is done when the differences are more significant.\n In this case, the code is split into two separate files that are architecture or environment specific. This should only apply inside the EAL library.\n\n.. note:\n\n\tAs in the linux kernel, the \"CONFIG_\" prefix is not used in C code.\n\tThis is only needed in Makefiles or shell scripts.\n\nPer Architecture Sources\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe following config options can be used:\n\n* CONFIG_RTE_ARCH is a string that contains the name of the architecture.\n* CONFIG_RTE_ARCH_I686, CONFIG_RTE_ARCH_X86_64, CONFIG_RTE_ARCH_X86_64_32 or CONFIG_RTE_ARCH_PPC_64 are defined only if we are building for those architectures.\n\nPer Execution Environment Sources\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe following config options can be used:\n\n* CONFIG_RTE_EXEC_ENV is a string that contains the name of the executive environment.\n* CONFIG_RTE_EXEC_ENV_BSDAPP or CONFIG_RTE_EXEC_ENV_LINUXAPP are defined only if we are building for this execution environment.\n\nLibrary Statistics\n------------------\n\nDescription\n~~~~~~~~~~~\n\nThis document describes the guidelines for DPDK library-level statistics counter\nsupport. This includes guidelines for turning library statistics on and off and\nrequirements for preventing ABI changes when implementing statistics.\n\n\nMechanism to allow the application to turn library statistics on and off\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nEach library that maintains statistics counters should provide a single build\ntime flag that decides whether the statistics counter collection is enabled or\nnot. This flag should be exposed as a variable within the DPDK configuration\nfile. When this flag is set, all the counters supported by current library are\ncollected for all the instances of every object type provided by the library.\nWhen this flag is cleared, none of the counters supported by the current library\nare collected for any instance of any object type provided by the library:\n\n.. code-block:: console\n\n\t# DPDK file config/common_linuxapp, config/common_bsdapp, etc.\n\tCONFIG_RTE__STATS_COLLECT=y/n\n\nThe default value for this DPDK configuration file variable (either \"yes\" or\n\"no\") is decided by each library.\n\n\nPrevention of ABI changes due to library statistics support\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe layout of data structures and prototype of functions that are part of the\nlibrary API should not be affected by whether the collection of statistics\ncounters is turned on or off for the current library. In practical terms, this\nmeans that space should always be allocated in the API data structures for\nstatistics counters and the statistics related API functions are always built\ninto the code, regardless of whether the statistics counter collection is turned\non or off for the current library.\n\nWhen the collection of statistics counters for the current library is turned\noff, the counters retrieved through the statistics related API functions should\nhave a default value of zero.\n\n\nMotivation to allow the application to turn library statistics on and off\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nIt is highly recommended that each library provides statistics counters to allow\nan application to monitor the library-level run-time events. Typical counters\nare: number of packets received/dropped/transmitted, number of buffers\nallocated/freed, number of occurrences for specific events, etc.\n\nHowever, the resources consumed for library-level statistics counter collection\nhave to be spent out of the application budget and the counters collected by\nsome libraries might not be relevant to the current application. In order to\navoid any unwanted waste of resources and/or performance impacts, the\napplication should decide at build time whether the collection of library-level\nstatistics counters should be turned on or off for each library individually.\n\nLibrary-level statistics counters can be relevant or not for specific\napplications:\n\n* For Application A, counters maintained by Library X are always relevant and\n the application needs to use them to implement certain features, such as traffic\n accounting, logging, application-level statistics, etc. In this case,\n the application requires that collection of statistics counters for Library X is\n always turned on.\n\n* For Application B, counters maintained by Library X are only useful during the\n application debug stage and are not relevant once debug phase is over. In this\n case, the application may decide to turn on the collection of Library X\n statistics counters during the debug phase and at a later stage turn them off.\n\n* For Application C, counters maintained by Library X are not relevant at all.\n It might be that the application maintains its own set of statistics counters\n that monitor a different set of run-time events (e.g. number of connection\n requests, number of active users, etc). It might also be that the application\n uses multiple libraries (Library X, Library Y, etc) and it is interested in the\n statistics counters of Library Y, but not in those of Library X. In this case,\n the application may decide to turn the collection of statistics counters off for\n Library X and on for Library Y.\n\nThe statistics collection consumes a certain amount of CPU resources (cycles,\ncache bandwidth, memory bandwidth, etc) that depends on:\n\n* Number of libraries used by the current application that have statistics\n counters collection turned on.\n\n* Number of statistics counters maintained by each library per object type\n instance (e.g. per port, table, pipeline, thread, etc).\n\n* Number of instances created for each object type supported by each library.\n\n* Complexity of the statistics logic collection for each counter: when only\n some occurrences of a specific event are valid, additional logic is typically\n needed to decide whether the current occurrence of the event should be counted\n or not. For example, in the event of packet reception, when only TCP packets\n with destination port within a certain range should be recorded, conditional\n branches are usually required. When processing a burst of packets that have been\n validated for header integrity, counting the number of bits set in a bitmask\n might be needed.\n" }, { "path": "doc/guides/contributing/documentation.rst", "content": ".. doc_guidelines:\n\nDPDK Documentation Guidelines\n=============================\n\nThis document outlines the guidelines for writing the DPDK Guides and API documentation in RST and Doxygen format.\n\nIt also explains the structure of the DPDK documentation and shows how to build the Html and PDF versions of the documents.\n\n\nStructure of the Documentation\n------------------------------\n\nThe DPDK source code repository contains input files to build the API documentation and User Guides.\n\nThe main directories that contain files related to documentation are shown below::\n\n lib\n |-- librte_acl\n |-- librte_cfgfile\n |-- librte_cmdline\n |-- librte_compat\n |-- librte_eal\n | |-- ...\n ...\n doc\n |-- api\n +-- guides\n |-- freebsd_gsg\n |-- linux_gsg\n |-- prog_guide\n |-- sample_app_ug\n |-- guidelines\n |-- testpmd_app_ug\n |-- rel_notes\n |-- nics\n |-- xen\n |-- ...\n\n\nThe API documentation is built from `Doxygen `_ comments in the header files.\nThese files are mainly in the ``lib/librte_*`` directories although some of the Poll Mode Drivers in ``drivers/net``\nare also documented with Doxygen.\n\nThe configuration files that are used to control the Doxygen output are in the ``doc/api`` directory.\n\nThe user guides such as *The Programmers Guide* and the *FreeBSD* and *Linux Getting Started* Guides are generated\nfrom RST markup text files using the `Sphinx `_ Documentation Generator.\n\nThese files are included in the ``doc/guides/`` directory.\nThe output is controlled by the ``doc/guides/conf.py`` file.\n\n\nRole of the Documentation\n-------------------------\n\nThe following items outline the roles of the different parts of the documentation and when they need to be updated or\nadded to by the developer.\n\n* **Release Notes**\n\n The Release Notes document which features have been added in the current and previous releases of DPDK and highlight\n any known issues.\n The Releases Notes also contain notifications of features that will change ABI compatibility in the next major release.\n\n Developers should update the Release Notes to add a short description of new or updated features.\n Developers should also update the Release Notes to add ABI announcements if necessary,\n (see :doc:`/contributing/versioning` for details).\n\n* **API documentation**\n\n The API documentation explains how to use the public DPDK functions.\n The `API index page `_ shows the generated API documentation with related groups of functions.\n\n The API documentation should be updated via Doxygen comments when new functions are added.\n\n* **Getting Started Guides**\n\n The Getting Started Guides show how to install and configure DPDK and how to run DPDK based applications on different OSes.\n\n A Getting Started Guide should be added when DPDK is ported to a new OS.\n\n* **The Programmers Guide**\n\n The Programmers Guide explains how the API components of DPDK such as the EAL, Memzone, Rings and the Hash Library work.\n It also explains how some higher level functionality such as Packet Distributor, Packet Framework and KNI work.\n It also shows the build system and explains how to add applications.\n\n The Programmers Guide should be expanded when new functionality is added to DPDK.\n\n* **App Guides**\n\n The app guides document the DPDK applications in the ``app`` directory such as ``testpmd``.\n\n The app guides should be updated if functionality is changed or added.\n\n* **Sample App Guides**\n\n The sample app guides document the DPDK example applications in the examples directory.\n Generally they demonstrate a major feature such as L2 or L3 Forwarding, Multi Process or Power Management.\n They explain the purpose of the sample application, how to run it and step through some of the code to explain the\n major functionality.\n\n A new sample application should be accompanied by a new sample app guide.\n The guide for the Skeleton Forwarding app is a good starting reference.\n\n* **Network Interface Controller Drivers**\n\n The NIC Drivers document explains the features of the individual Poll Mode Drivers, such as software requirements,\n configuration and initialization.\n\n New documentation should be added for new Poll Mode Drivers.\n\n* **Guidelines**\n\n The guideline documents record community process, expectations and design directions.\n\n They can be extended, amended or discussed by submitting a patch and getting community approval.\n\n\nBuilding the Documentation\n--------------------------\n\nDependencies\n~~~~~~~~~~~~\n\n\nThe following dependencies must be installed to build the documentation:\n\n* Doxygen.\n\n* Sphinx (also called python-sphinx).\n\n* TexLive (at least TexLive-core, extra Latex support and extra fonts).\n\n* Inkscape.\n\n`Doxygen`_ generates documentation from commented source code.\nIt can be installed as follows:\n\n.. code-block:: console\n\n # Ubuntu/Debian.\n sudo apt-get -y install doxygen\n\n # Red Hat/Fedora.\n sudo yum -y install doxygen\n\n`Sphinx`_ is a Python documentation tool for converting RST files to Html or to PDF (via LaTeX).\nIt can be installed as follows:\n\n.. code-block:: console\n\n # Ubuntu/Debian.\n sudo apt-get -y install python-sphinx\n\n # Red Hat/Fedora.\n sudo yum -y install python-sphinx\n\n # Or, on any system with Python installed.\n sudo easy_install -U sphinx\n\nFor further information on getting started with Sphinx see the `Sphinx Tutorial `_.\n\n.. Note::\n\n To get full support for Figure and Table numbering it is best to install Sphinx 1.3.1 or later.\n\n\n`Inkscape`_ is a vector based graphics program which is used to create SVG images and also to convert SVG images to PDF images.\nIt can be installed as follows:\n\n.. code-block:: console\n\n # Ubuntu/Debian.\n sudo apt-get -y install inkscape\n\n # Red Hat/Fedora.\n sudo yum -y install inkscape\n\n`TexLive `_ is an installation package for Tex/LaTeX.\nIt is used to generate the PDF versions of the documentation.\nThe main required packages can be installed as follows:\n\n.. code-block:: console\n\n # Ubuntu/Debian.\n sudo apt-get -y install texlive-latex-extra texlive-fonts-extra \\\n texlive-fonts-recommended\n\n\n # Red Hat/Fedora, selective install.\n sudo yum -y install texlive-collection-latexextra \\\n texlive-collection-fontsextra\n\n\nBuild commands\n~~~~~~~~~~~~~~\n\nThe documentation is built using the standard DPDK build system.\nSome examples are shown below:\n\n* Generate all the documentation targets::\n\n make doc\n\n* Generate the Doxygen API documentation in Html::\n\n make doc-api-html\n\n* Generate the guides documentation in Html::\n\n make doc-guides-html\n\n* Generate the guides documentation in Pdf::\n\n make doc-guides-pdf\n\nThe output of these commands is generated in the ``build`` directory::\n\n build/doc\n |-- html\n | |-- api\n | +-- guides\n |\n +-- pdf\n +-- guides\n\n\n.. Note::\n\n Make sure to fix any Sphinx or Doxygen warnings when adding or updating documentation.\n\nThe documentation output files can be removed as follows::\n\n make doc-clean\n\n\nDocument Guidelines\n-------------------\n\nHere are some guidelines in relation to the style of the documentation:\n\n* Document the obvious as well as the obscure since it won't always be obvious to the reader.\n For example an instruction like \"Set up 64 2MB Hugepages\" is better when followed by a sample commandline or a link to\n the appropriate section of the documentation.\n\n* Use American English spellings throughout.\n This can be checked using the ``aspell`` utility::\n\n aspell --lang=en_US --check doc/guides/sample_app_ug/mydoc.rst\n\n\nRST Guidelines\n--------------\n\nThe RST (reStructuredText) format is a plain text markup format that can be converted to Html, PDF or other formats.\nIt is most closely associated with Python but it can be used to document any language.\nIt is used in DPDK to document everything apart from the API.\n\nThe Sphinx documentation contains a very useful `RST Primer `_ which is a\ngood place to learn the minimal set of syntax required to format a document.\n\nThe official `reStructuredText `_ website contains the specification for the\nRST format and also examples of how to use it.\nHowever, for most developers the RST Primer is a better resource.\n\nThe most common guidelines for writing RST text are detailed in the\n`Documenting Python `_ guidelines.\nThe additional guidelines below reiterate or expand upon those guidelines.\n\n\nLine Length\n~~~~~~~~~~~\n\n* The recommended style for the DPDK documentation is to put sentences on separate lines.\n This allows for easier reviewing of patches.\n Multiple sentences which are not separated by a blank line are joined automatically into paragraphs, for example::\n\n Here is an example sentence.\n Long sentences over the limit shown below can be wrapped onto\n a new line.\n These three sentences will be joined into the same paragraph.\n\n This is a new paragraph, since it is separated from the\n previous paragraph by a blank line.\n\n This would be rendered as follows:\n\n *Here is an example sentence.\n Long sentences over the limit shown below can be wrapped onto\n a new line.\n These three sentences will be joined into the same paragraph.*\n\n *This is a new paragraph, since it is separated from the\n previous paragraph by a blank line.*\n\n\n* Long sentences should be wrapped at 120 characters +/- 10 characters. They should be wrapped at words.\n\n* Lines in literal blocks must by less than 80 characters since they aren't wrapped by the document formatters\n and can exceed the page width in PDF documents.\n\n\nWhitespace\n~~~~~~~~~~\n\n* Standard RST indentation is 3 spaces.\n Code can be indented 4 spaces, especially if it is copied from source files.\n\n* No tabs.\n Convert tabs in embedded code to 4 or 8 spaces.\n\n* No trailing whitespace.\n\n* Add 2 blank lines before each section header.\n\n* Add 1 blank line after each section header.\n\n* Add 1 blank line between each line of a list.\n\n\nSection Headers\n~~~~~~~~~~~~~~~\n\n* Section headers should use the use the following underline formats::\n\n Level 1 Heading\n ===============\n\n\n Level 2 Heading\n ---------------\n\n\n Level 3 Heading\n ~~~~~~~~~~~~~~~\n\n\n Level 4 Heading\n ^^^^^^^^^^^^^^^\n\n\n* Level 4 headings should be used sparingly.\n\n* The underlines should match the length of the text.\n\n* In general, the heading should be less than 80 characters, for conciseness.\n\n* As noted above:\n\n * Add 2 blank lines before each section header.\n\n * Add 1 blank line after each section header.\n\n\nLists\n~~~~~\n\n* Bullet lists should be formatted with a leading ``*`` as follows::\n\n * Item one.\n\n * Item two is a long line that is wrapped and then indented to match\n the start of the previous line.\n\n * One space character between the bullet and the text is preferred.\n\n* Numbered lists can be formatted with a leading number but the preference is to use ``#.`` which will give automatic numbering.\n This is more convenient when adding or removing items::\n\n #. Item one.\n\n #. Item two is a long line that is wrapped and then indented\n to match the start of the e first line.\n\n #. Item two is a long line that is wrapped and then indented to match\n the start of the previous line.\n\n* Definition lists can be written with or without a bullet::\n\n * Item one.\n\n Some text about item one.\n\n * Item two.\n\n Some text about item two.\n\n* All lists, and sub-lists, must be separated from the preceding text by a blank line.\n This is a syntax requirement.\n\n* All list items should be separated by a blank line for readability.\n\n\nCode and Literal block sections\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n* Inline text that is required to be rendered with a fixed width font should be enclosed in backquotes like this:\n \\`\\`text\\`\\`, so that it appears like this: ``text``.\n\n* Fixed width, literal blocks of texts should be indented at least 3 spaces and prefixed with ``::`` like this::\n\n Here is some fixed width text::\n\n 0x0001 0x0001 0x00FF 0x00FF\n\n* It is also possible to specify an encoding for a literal block using the ``.. code-block::`` directive so that syntax\n highlighting can be applied.\n Examples of supported highlighting are::\n\n .. code-block:: console\n .. code-block:: c\n .. code-block:: python\n .. code-block:: diff\n .. code-block:: none\n\n That can be applied as follows::\n\n .. code-block:: c\n\n #include\n\n int main() {\n\n printf(\"Hello World\\n\");\n\n return 0;\n }\n\n Which would be rendered as:\n\n .. code-block:: c\n\n #include\n\n int main() {\n\n printf(\"Hello World\\n\");\n\n return 0;\n }\n\n\n* The default encoding for a literal block using the simplified ``::``\n directive is ``none``.\n\n* Lines in literal blocks must be less than 80 characters since they can exceed the page width when converted to PDF documentation.\n For long literal lines that exceed that limit try to wrap the text at sensible locations.\n For example a long command line could be documented like this and still work if copied directly from the docs::\n\n build/app/testpmd -c7 -n3 --vdev=eth_pcap0,iface=eth0 \\\n --vdev=eth_pcap1,iface=eth1 \\\n -- -i --nb-cores=2 --nb-ports=2 \\\n --total-num-mbufs=2048\n\n* Long lines that cannot be wrapped, such as application output, should be truncated to be less than 80 characters.\n\n\nImages\n~~~~~~\n\n* All images should be in SVG scalar graphics format.\n They should be true SVG XML files and should not include binary formats embedded in a SVG wrapper.\n\n* The DPDK documentation contains some legacy images in PNG format.\n These will be converted to SVG in time.\n\n* `Inkscape `_ is the recommended graphics editor for creating the images.\n Use some of the older images in ``doc/guides/prog_guide/img/`` as a template, for example ``mbuf1.svg``\n or ``ring-enqueue.svg``.\n\n* The SVG images should include a copyright notice, as an XML comment.\n\n* Images in the documentation should be formatted as follows:\n\n * The image should be preceded by a label in the format ``.. _figure_XXXX:`` with a leading underscore and\n where ``XXXX`` is a unique descriptive name.\n\n * Images should be included using the ``.. figure::`` directive and the file type should be set to ``*`` (not ``.svg``).\n This allows the format of the image to be changed if required, without updating the documentation.\n\n * Images must have a caption as part of the ``.. figure::`` directive.\n\n* Here is an example of the previous three guidelines::\n\n .. _figure_mempool:\n\n .. figure:: img/mempool.*\n\n A mempool in memory with its associated ring.\n\n.. _mock_label:\n\n* Images can then be linked to using the ``:numref:`` directive::\n\n The mempool layout is shown in :numref:`figure_mempool`.\n\n This would be rendered as: *The mempool layout is shown in* :ref:`Fig 6.3 `.\n\n **Note**: The ``:numref:`` directive requires Sphinx 1.3.1 or later.\n With earlier versions it will still be rendered as a link but won't have an automatically generated number.\n\n* The caption of the image can be generated, with a link, using the ``:ref:`` directive::\n\n :ref:`figure_mempool`\n\n This would be rendered as: *A mempool in memory with its associated ring.*\n\nTables\n~~~~~~\n\n* RST tables should be used sparingly.\n They are hard to format and to edit, they are often rendered incorrectly in PDF format, and the same information\n can usually be shown just as clearly with a definition or bullet list.\n\n* Tables in the documentation should be formatted as follows:\n\n * The table should be preceded by a label in the format ``.. _table_XXXX:`` with a leading underscore and where\n ``XXXX`` is a unique descriptive name.\n\n * Tables should be included using the ``.. table::`` directive and must have a caption.\n\n* Here is an example of the previous two guidelines::\n\n .. _table_qos_pipes:\n\n .. table:: Sample configuration for QOS pipes.\n\n +----------+----------+----------+\n | Header 1 | Header 2 | Header 3 |\n | | | |\n +==========+==========+==========+\n | Text | Text | Text |\n +----------+----------+----------+\n | ... | ... | ... |\n +----------+----------+----------+\n\n* Tables can be linked to using the ``:numref:`` and ``:ref:`` directives, as shown in the previous section for images.\n For example::\n\n The QOS configuration is shown in :numref:`table_qos_pipes`.\n\n* Tables should not include merged cells since they are not supported by the PDF renderer.\n\n\n.. _links:\n\nHyperlinks\n~~~~~~~~~~\n\n* Links to external websites can be plain URLs.\n The following is rendered as http://dpdk.org::\n\n http://dpdk.org\n\n* They can contain alternative text.\n The following is rendered as `Check out DPDK `_::\n\n `Check out DPDK `_\n\n* An internal link can be generated by placing labels in the document with the format ``.. _label_name``.\n\n* The following links to the top of this section: :ref:`links`::\n\n .. _links:\n\n Hyperlinks\n ~~~~~~~~~~\n\n * The following links to the top of this section: :ref:`links`:\n\n.. Note::\n\n The label must have a leading underscore but the reference to it must omit it.\n This is a frequent cause of errors and warnings.\n\n* The use of a label is preferred since it works across files and will still work if the header text changes.\n\n\n.. _doxygen_guidelines:\n\nDoxygen Guidelines\n------------------\n\nThe DPDK API is documented using Doxygen comment annotations in the header files.\nDoxygen is a very powerful tool, it is extremely configurable and with a little effort can be used to create expressive documents.\nSee the `Doxygen website `_ for full details on how to use it.\n\nThe following are some guidelines for use of Doxygen in the DPDK API documentation:\n\n* New libraries that are documented with Doxygen should be added to the Doxygen configuration file: ``doc/api/doxy-api.conf``.\n It is only required to add the directory that contains the files.\n It isn't necessary to explicitly name each file since the configuration matches all ``rte_*.h`` files in the directory.\n\n* Use proper capitalization and punctuation in the Doxygen comments since they will become sentences in the documentation.\n This in particular applies to single line comments, which is the case the is most often forgotten.\n\n* Use ``@`` style Doxygen commands instead of ``\\`` style commands.\n\n* Add a general description of each library at the head of the main header files:\n\n .. code-block:: c\n\n /**\n * @file\n * RTE Mempool.\n *\n * A memory pool is an allocator of fixed-size object. It is\n * identified by its name, and uses a ring to store free objects.\n * ...\n */\n\n* Document the purpose of a function, the parameters used and the return\n value:\n\n .. code-block:: c\n\n /**\n * Attach a new Ethernet device specified by arguments.\n *\n * @param devargs\n * A pointer to a strings array describing the new device\n * to be attached. The strings should be a pci address like\n * `0000:01:00.0` or **virtual** device name like `eth_pcap0`.\n * @param port_id\n * A pointer to a port identifier actually attached.\n *\n * @return\n * 0 on success and port_id is filled, negative on error.\n */\n int rte_eth_dev_attach(const char *devargs, uint8_t *port_id);\n\n* Doxygen supports Markdown style syntax such as bold, italics, fixed width text and lists.\n For example the second line in the ``devargs`` parameter in the previous example will be rendered as:\n\n The strings should be a pci address like ``0000:01:00.0`` or **virtual** device name like ``eth_pcap0``.\n\n* Use ``-`` instead of ``*`` for lists within the Doxygen comment since the latter can get confused with the comment delimiter.\n\n* Add an empty line between the function description, the ``@params`` and ``@return`` for readability.\n\n* Place the ``@params`` description on separate line and indent it by 2 spaces.\n (It would be better to use no indentation since this is more common and also because checkpatch complains about leading\n whitespace in comments.\n However this is the convention used in the existing DPDK code.)\n\n* Documented functions can be linked to simply by adding ``()`` to the function name:\n\n .. code-block:: c\n\n /**\n * The functions exported by the application Ethernet API to setup\n * a device designated by its port identifier must be invoked in\n * the following order:\n * - rte_eth_dev_configure()\n * - rte_eth_tx_queue_setup()\n * - rte_eth_rx_queue_setup()\n * - rte_eth_dev_start()\n */\n\n In the API documentation the functions will be rendered as links, see the\n `online section of the rte_ethdev.h docs `_ that contains the above text.\n\n* The ``@see`` keyword can be used to create a *see also* link to another file or library.\n This directive should be placed on one line at the bottom of the documentation section.\n\n .. code-block:: c\n\n /**\n * ...\n *\n * Some text that references mempools.\n *\n * @see eal_memzone.c\n */\n\n* Doxygen supports two types of comments for documenting variables, constants and members: prefix and postfix:\n\n .. code-block:: c\n\n /** This is a prefix comment. */\n #define RTE_FOO_ERROR 0x023.\n\n #define RTE_BAR_ERROR 0x024. /**< This is a postfix comment. */\n\n* Postfix comments are preferred for struct members and constants if they can be documented in the same way:\n\n .. code-block:: c\n\n struct rte_eth_stats {\n uint64_t ipackets; /**< Total number of received packets. */\n uint64_t opackets; /**< Total number of transmitted packets.*/\n uint64_t ibytes; /**< Total number of received bytes. */\n uint64_t obytes; /**< Total number of transmitted bytes. */\n uint64_t imissed; /**< Total of RX missed packets. */\n uint64_t ibadcrc; /**< Total of RX packets with CRC error. */\n uint64_t ibadlen; /**< Total of RX packets with bad length. */\n }\n\n Note: postfix comments should be aligned with spaces not tabs in accordance\n with the :ref:`coding_style`.\n\n* If a single comment type can't be used, due to line length limitations then\n prefix comments should be preferred.\n For example this section of the code contains prefix comments, postfix comments on the same line and postfix\n comments on a separate line:\n\n .. code-block:: c\n\n /** Number of elements in the elt_pa array. */\n uint32_t pg_num __rte_cache_aligned;\n uint32_t pg_shift; /**< LOG2 of the physical pages. */\n uintptr_t pg_mask; /**< Physical page mask value. */\n uintptr_t elt_va_start;\n /**< Virtual address of the first mempool object. */\n uintptr_t elt_va_end;\n /**< Virtual address of the mempool object. */\n phys_addr_t elt_pa[MEMPOOL_PG_NUM_DEFAULT];\n /**< Array of physical page addresses for the mempool buffer. */\n\n This doesn't have an effect on the rendered documentation but it is confusing for the developer reading the code.\n It this case it would be clearer to use prefix comments throughout:\n\n .. code-block:: c\n\n /** Number of elements in the elt_pa array. */\n uint32_t pg_num __rte_cache_aligned;\n /** LOG2 of the physical pages. */\n uint32_t pg_shift;\n /** Physical page mask value. */\n uintptr_t pg_mask;\n /** Virtual address of the first mempool object. */\n uintptr_t elt_va_start;\n /** Virtual address of the mempool object. */\n uintptr_t elt_va_end;\n /** Array of physical page addresses for the mempool buffer. */\n phys_addr_t elt_pa[MEMPOOL_PG_NUM_DEFAULT];\n\n* Check for Doxygen warnings in new code by checking the API documentation build::\n\n make doc-api-html >/dev/null\n\n* Read the rendered section of the documentation that you have added for correctness, clarity and consistency\n with the surrounding text.\n" }, { "path": "doc/guides/contributing/index.rst", "content": "Contributor's Guidelines\n========================\n\n.. toctree::\n :maxdepth: 2\n :numbered:\n\n coding_style\n design\n versioning\n documentation\n" }, { "path": "doc/guides/contributing/versioning.rst", "content": "Managing ABI updates\n====================\n\nDescription\n-----------\n\nThis document details some methods for handling ABI management in the DPDK.\nNote this document is not exhaustive, in that C library versioning is flexible\nallowing multiple methods to achieve various goals, but it will provide the user\nwith some introductory methods\n\nGeneral Guidelines\n------------------\n\n#. Whenever possible, ABI should be preserved\n#. The addition of symbols is generally not problematic\n#. The modification of symbols can generally be managed with versioning\n#. The removal of symbols generally is an ABI break and requires bumping of the\n LIBABIVER macro\n\nWhat is an ABI\n--------------\n\nAn ABI (Application Binary Interface) is the set of runtime interfaces exposed\nby a library. It is similar to an API (Application Programming Interface) but\nis the result of compilation. It is also effectively cloned when applications\nlink to dynamic libraries. That is to say when an application is compiled to\nlink against dynamic libraries, it is assumed that the ABI remains constant\nbetween the time the application is compiled/linked, and the time that it runs.\nTherefore, in the case of dynamic linking, it is critical that an ABI is\npreserved, or (when modified), done in such a way that the application is unable\nto behave improperly or in an unexpected fashion.\n\nThe DPDK ABI policy\n-------------------\n\nABI versions are set at the time of major release labeling, and the ABI may\nchange multiple times, without warning, between the last release label and the\nHEAD label of the git tree.\n\nABI versions, once released, are available until such time as their\ndeprecation has been noted in the Release Notes for at least one major release\ncycle. For example consider the case where the ABI for DPDK 2.0 has been\nshipped and then a decision is made to modify it during the development of\nDPDK 2.1. The decision will be recorded in the Release Notes for the DPDK 2.1\nrelease and the modification will be made available in the DPDK 2.2 release.\n\nABI versions may be deprecated in whole or in part as needed by a given\nupdate.\n\nSome ABI changes may be too significant to reasonably maintain multiple\nversions. In those cases ABI's may be updated without backward compatibility\nbeing provided. The requirements for doing so are:\n\n#. At least 3 acknowledgments of the need to do so must be made on the\n dpdk.org mailing list.\n\n#. The changes (including an alternative map file) must be gated with\n the ``RTE_NEXT_ABI`` option, and provided with a deprecation notice at the\n same time.\n It will become the default ABI in the next release.\n\n#. A full deprecation cycle, as explained above, must be made to offer\n downstream consumers sufficient warning of the change.\n\n#. At the beginning of the next release cycle, every ``RTE_NEXT_ABI``\n conditions will be removed, the ``LIBABIVER`` variable in the makefile(s)\n where the ABI is changed will be incremented, and the map files will\n be updated.\n\nNote that the above process for ABI deprecation should not be undertaken\nlightly. ABI stability is extremely important for downstream consumers of the\nDPDK, especially when distributed in shared object form. Every effort should\nbe made to preserve the ABI whenever possible. The ABI should only be changed\nfor significant reasons, such as performance enhancements. ABI breakage due to\nchanges such as reorganizing public structure fields for aesthetic or\nreadability purposes should be avoided.\n\nExamples of Deprecation Notices\n-------------------------------\n\nThe following are some examples of ABI deprecation notices which would be\nadded to the Release Notes:\n\n* The Macro ``#RTE_FOO`` is deprecated and will be removed with version 2.0,\n to be replaced with the inline function ``rte_foo()``.\n\n* The function ``rte_mbuf_grok()`` has been updated to include a new parameter\n in version 2.0. Backwards compatibility will be maintained for this function\n until the release of version 2.1\n\n* The members of ``struct rte_foo`` have been reorganized in release 2.0 for\n performance reasons. Existing binary applications will have backwards\n compatibility in release 2.0, while newly built binaries will need to\n reference the new structure variant ``struct rte_foo2``. Compatibility will\n be removed in release 2.2, and all applications will require updating and\n rebuilding to the new structure at that time, which will be renamed to the\n original ``struct rte_foo``.\n\n* Significant ABI changes are planned for the ``librte_dostuff`` library. The\n upcoming release 2.0 will not contain these changes, but release 2.1 will,\n and no backwards compatibility is planned due to the extensive nature of\n these changes. Binaries using this library built prior to version 2.1 will\n require updating and recompilation.\n\nVersioning Macros\n-----------------\n\nWhen a symbol is exported from a library to provide an API, it also provides a\ncalling convention (ABI) that is embodied in its name, return type and\narguments. Occasionally that function may need to change to accommodate new\nfunctionality or behavior. When that occurs, it is desirable to allow for\nbackward compatibility for a time with older binaries that are dynamically\nlinked to the DPDK.\n\nTo support backward compatibility the ``lib/librte_compat/rte_compat.h``\nheader file provides macros to use when updating exported functions. These\nmacros are used in conjunction with the ``rte__version.map`` file for\na given library to allow multiple versions of a symbol to exist in a shared\nlibrary so that older binaries need not be immediately recompiled.\n\nThe macros exported are:\n\n* ``VERSION_SYMBOL(b, e, n)``: Creates a symbol version table entry binding\n versioned symbol ``b@DPDK_n`` to the internal function ``b_e``.\n\n* ``BIND_DEFAULT_SYMBOL(b, e, n)``: Creates a symbol version entry instructing\n the linker to bind references to symbol ``b`` to the internal symbol\n ``b_e``.\n\n* ``MAP_STATIC_SYMBOL(f, p)``: Declare the prototype ``f``, and map it to the\n fully qualified function ``p``, so that if a symbol becomes versioned, it\n can still be mapped back to the public symbol name.\n\nExamples of ABI Macro use\n-------------------------\n\nUpdating a public API\n~~~~~~~~~~~~~~~~~~~~~\n\nAssume we have a function as follows\n\n.. code-block:: c\n\n /*\n * Create an acl context object for apps to\n * manipulate\n */\n struct rte_acl_ctx *\n rte_acl_create(const struct rte_acl_param *param)\n {\n ...\n }\n\n\nAssume that struct rte_acl_ctx is a private structure, and that a developer\nwishes to enhance the acl api so that a debugging flag can be enabled on a\nper-context basis. This requires an addition to the structure (which, being\nprivate, is safe), but it also requires modifying the code as follows\n\n.. code-block:: c\n\n /*\n * Create an acl context object for apps to\n * manipulate\n */\n struct rte_acl_ctx *\n rte_acl_create(const struct rte_acl_param *param, int debug)\n {\n ...\n }\n\n\nNote also that, being a public function, the header file prototype must also be\nchanged, as must all the call sites, to reflect the new ABI footprint. We will\nmaintain previous ABI versions that are accessible only to previously compiled\nbinaries\n\nThe addition of a parameter to the function is ABI breaking as the function is\npublic, and existing application may use it in its current form. However, the\ncompatibility macros in DPDK allow a developer to use symbol versioning so that\nmultiple functions can be mapped to the same public symbol based on when an\napplication was linked to it. To see how this is done, we start with the\nrequisite libraries version map file. Initially the version map file for the\nacl library looks like this\n\n.. code-block:: none\n\n DPDK_2.0 {\n global:\n\n rte_acl_add_rules;\n rte_acl_build;\n rte_acl_classify;\n rte_acl_classify_alg;\n rte_acl_classify_scalar;\n rte_acl_create;\n rte_acl_dump;\n rte_acl_find_existing;\n rte_acl_free;\n rte_acl_ipv4vlan_add_rules;\n rte_acl_ipv4vlan_build;\n rte_acl_list_dump;\n rte_acl_reset;\n rte_acl_reset_rules;\n rte_acl_set_ctx_classify;\n\n local: *;\n };\n\nThis file needs to be modified as follows\n\n.. code-block:: none\n\n DPDK_2.0 {\n global:\n\n rte_acl_add_rules;\n rte_acl_build;\n rte_acl_classify;\n rte_acl_classify_alg;\n rte_acl_classify_scalar;\n rte_acl_create;\n rte_acl_dump;\n rte_acl_find_existing;\n rte_acl_free;\n rte_acl_ipv4vlan_add_rules;\n rte_acl_ipv4vlan_build;\n rte_acl_list_dump;\n rte_acl_reset;\n rte_acl_reset_rules;\n rte_acl_set_ctx_classify;\n\n local: *;\n };\n\n DPDK_2.1 {\n global:\n rte_acl_create;\n\n } DPDK_2.0;\n\nThe addition of the new block tells the linker that a new version node is\navailable (DPDK_2.1), which contains the symbol rte_acl_create, and inherits the\nsymbols from the DPDK_2.0 node. This list is directly translated into a list of\nexported symbols when DPDK is compiled as a shared library\n\nNext, we need to specify in the code which function map to the rte_acl_create\nsymbol at which versions. First, at the site of the initial symbol definition,\nwe need to update the function so that it is uniquely named, and not in conflict\nwith the public symbol name\n\n.. code-block:: c\n\n struct rte_acl_ctx *\n -rte_acl_create(const struct rte_acl_param *param)\n +rte_acl_create_v20(const struct rte_acl_param *param)\n {\n size_t sz;\n struct rte_acl_ctx *ctx;\n ...\n\nNote that the base name of the symbol was kept intact, as this is condusive to\nthe macros used for versioning symbols. That is our next step, mapping this new\nsymbol name to the initial symbol name at version node 2.0. Immediately after\nthe function, we add this line of code\n\n.. code-block:: c\n\n VERSION_SYMBOL(rte_acl_create, _v20, 2.0);\n\nRemembering to also add the rte_compat.h header to the requisite c file where\nthese changes are being made. The above macro instructs the linker to create a\nnew symbol ``rte_acl_create@DPDK_2.0``, which matches the symbol created in older\nbuilds, but now points to the above newly named function. We have now mapped\nthe original rte_acl_create symbol to the original function (but with a new\nname)\n\nNext, we need to create the 2.1 version of the symbol. We create a new function\nname, with a different suffix, and implement it appropriately\n\n.. code-block:: c\n\n struct rte_acl_ctx *\n rte_acl_create_v21(const struct rte_acl_param *param, int debug);\n {\n struct rte_acl_ctx *ctx = rte_acl_create_v20(param);\n\n ctx->debug = debug;\n\n return ctx;\n }\n\nThis code serves as our new API call. Its the same as our old call, but adds\nthe new parameter in place. Next we need to map this function to the symbol\n``rte_acl_create@DPDK_2.1``. To do this, we modify the public prototype of the call\nin the header file, adding the macro there to inform all including applications,\nthat on re-link, the default rte_acl_create symbol should point to this\nfunction. Note that we could do this by simply naming the function above\nrte_acl_create, and the linker would chose the most recent version tag to apply\nin the version script, but we can also do this in the header file\n\n.. code-block:: c\n\n struct rte_acl_ctx *\n -rte_acl_create(const struct rte_acl_param *param);\n +rte_acl_create(const struct rte_acl_param *param, int debug);\n +BIND_DEFAULT_SYMBOL(rte_acl_create, _v21, 2.1);\n\nThe BIND_DEFAULT_SYMBOL macro explicitly tells applications that include this\nheader, to link to the rte_acl_create_v21 function and apply the DPDK_2.1\nversion node to it. This method is more explicit and flexible than just\nre-implementing the exact symbol name, and allows for other features (such as\nlinking to the old symbol version by default, when the new ABI is to be opt-in\nfor a period.\n\nOne last thing we need to do. Note that we've taken what was a public symbol,\nand duplicated it into two uniquely and differently named symbols. We've then\nmapped each of those back to the public symbol ``rte_acl_create`` with different\nversion tags. This only applies to dynamic linking, as static linking has no\nnotion of versioning. That leaves this code in a position of no longer having a\nsymbol simply named ``rte_acl_create`` and a static build will fail on that\nmissing symbol.\n\nTo correct this, we can simply map a function of our choosing back to the public\nsymbol in the static build with the ``MAP_STATIC_SYMBOL`` macro. Generally the\nassumption is that the most recent version of the symbol is the one you want to\nmap. So, back in the C file where, immediately after ``rte_acl_create_v21`` is\ndefined, we add this\n\n.. code-block:: c\n\n struct rte_acl_create_v21(const struct rte_acl_param *param, int debug)\n {\n ...\n }\n MAP_STATIC_SYMBOL(struct rte_acl_create(const struct rte_acl_param *param, int debug), rte_acl_create_v21);\n\nThat tells the compiler that, when building a static library, any calls to the\nsymbol ``rte_acl_create`` should be linked to ``rte_acl_create_v21``\n\nThat's it, on the next shared library rebuild, there will be two versions of\nrte_acl_create, an old DPDK_2.0 version, used by previously built applications,\nand a new DPDK_2.1 version, used by future built applications.\n\n\nDeprecating part of a public API\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nLets assume that you've done the above update, and after a few releases have\npassed you decide you would like to retire the old version of the function.\nAfter having gone through the ABI deprecation announcement process, removal is\neasy. Start by removing the symbol from the requisite version map file:\n\n.. code-block:: none\n\n DPDK_2.0 {\n global:\n\n rte_acl_add_rules;\n rte_acl_build;\n rte_acl_classify;\n rte_acl_classify_alg;\n rte_acl_classify_scalar;\n rte_acl_dump;\n - rte_acl_create\n rte_acl_find_existing;\n rte_acl_free;\n rte_acl_ipv4vlan_add_rules;\n rte_acl_ipv4vlan_build;\n rte_acl_list_dump;\n rte_acl_reset;\n rte_acl_reset_rules;\n rte_acl_set_ctx_classify;\n\n local: *;\n };\n\n DPDK_2.1 {\n global:\n rte_acl_create;\n } DPDK_2.0;\n\n\nNext remove the corresponding versioned export\n.. code-block:: c\n\n -VERSION_SYMBOL(rte_acl_create, _v20, 2.0);\n\n\nNote that the internal function definition could also be removed, but its used\nin our example by the newer version _v21, so we leave it in place. This is a\ncoding style choice.\n\nLastly, we need to bump the LIBABIVER number for this library in the Makefile to\nindicate to applications doing dynamic linking that this is a later, and\npossibly incompatible library version:\n\n.. code-block:: c\n\n -LIBABIVER := 1\n +LIBABIVER := 2\n\nDeprecating an entire ABI version\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nWhile removing a symbol from and ABI may be useful, it is often more practical\nto remove an entire version node at once. If a version node completely\nspecifies an API, then removing part of it, typically makes it incomplete. In\nthose cases it is better to remove the entire node\n\nTo do this, start by modifying the version map file, such that all symbols from\nthe node to be removed are merged into the next node in the map\n\nIn the case of our map above, it would transform to look as follows\n\n.. code-block:: none\n\n DPDK_2.1 {\n global:\n\n rte_acl_add_rules;\n rte_acl_build;\n rte_acl_classify;\n rte_acl_classify_alg;\n rte_acl_classify_scalar;\n rte_acl_dump;\n rte_acl_create\n rte_acl_find_existing;\n rte_acl_free;\n rte_acl_ipv4vlan_add_rules;\n rte_acl_ipv4vlan_build;\n rte_acl_list_dump;\n rte_acl_reset;\n rte_acl_reset_rules;\n rte_acl_set_ctx_classify;\n\n local: *;\n };\n\nThen any uses of BIND_DEFAULT_SYMBOL that pointed to the old node should be\nupdated to point to the new version node in any header files for all affected\nsymbols.\n\n.. code-block:: c\n\n -BIND_DEFAULT_SYMBOL(rte_acl_create, _v20, 2.0);\n +BIND_DEFAULT_SYMBOL(rte_acl_create, _v21, 2.1);\n\nLastly, any VERSION_SYMBOL macros that point to the old version node should be\nremoved, taking care to keep, where need old code in place to support newer\nversions of the symbol.\n\nRunning the ABI Validator\n-------------------------\n\nThe ``scripts`` directory in the DPDK source tree contains a utility program,\n``validate-abi.sh``, for validating the DPDK ABI based on the Linux `ABI\nCompliance Checker\n`_.\n\nThis has a dependency on the ``abi-compliance-checker`` and ``and abi-dumper``\nutilities which can be installed via a package manager. For example::\n\n sudo yum install abi-compliance-checker\n sudo yum install abi-dumper\n\nThe syntax of the ``validate-abi.sh`` utility is::\n\n ./scripts/validate-abi.sh \n\nWhere ``TAG1`` and ``TAG2`` are valid git tags on the local repo and target is\nthe usual DPDK compilation target.\n\nFor example to test the current committed HEAD against a previous release tag\nwe could add a temporary tag and run the utility as follows::\n\n git tag MY_TEMP_TAG\n ./scripts/validate-abi.sh v2.0.0 MY_TEMP_TAG x86_64-native-linuxapp-gcc\n\nAfter the validation script completes (it can take a while since it need to\ncompile both tags) it will create compatibility reports in the\n``./compat_report`` directory. Listed incompatibilities can be found as\nfollows::\n\n grep -lr Incompatible compat_reports/\n" }, { "path": "doc/guides/faq/faq.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nWhat does \"EAL: map_all_hugepages(): open failed: Permission denied Cannot init memory\" mean?\n---------------------------------------------------------------------------------------------\n\nThis is most likely due to the test application not being run with sudo to promote the user to a superuser.\nAlternatively, applications can also be run as regular user.\nFor more information, please refer to :ref:`DPDK Getting Started Guide `.\n\n\nIf I want to change the number of TLB Hugepages allocated, how do I remove the original pages allocated?\n--------------------------------------------------------------------------------------------------------\n\nThe number of pages allocated can be seen by executing the following command::\n\n grep Huge /proc/meminfo\n\nOnce all the pages are mmapped by an application, they stay that way.\nIf you start a test application with less than the maximum, then you have free pages.\nWhen you stop and restart the test application, it looks to see if the pages are available in the ``/dev/huge`` directory and mmaps them.\nIf you look in the directory, you will see ``n`` number of 2M pages files. If you specified 1024, you will see 1024 page files.\nThese are then placed in memory segments to get contiguous memory.\n\nIf you need to change the number of pages, it is easier to first remove the pages. The tools/setup.sh script provides an option to do this.\nSee the \"Quick Start Setup Script\" section in the :ref:`DPDK Getting Started Guide ` for more information.\n\n\nIf I execute \"l2fwd -c f -m 64 -n 3 -- -p 3\", I get the following output, indicating that there are no socket 0 hugepages to allocate the mbuf and ring structures to?\n----------------------------------------------------------------------------------------------------------------------------------------------------------------------\n\nI have set up a total of 1024 Hugepages (that is, allocated 512 2M pages to each NUMA node).\n\nThe -m command line parameter does not guarantee that huge pages will be reserved on specific sockets. Therefore, allocated huge pages may not be on socket 0.\nTo request memory to be reserved on a specific socket, please use the --socket-mem command-line parameter instead of -m.\n\n\nI am running a 32-bit DPDK application on a NUMA system, and sometimes the application initializes fine but cannot allocate memory. Why is that happening?\n----------------------------------------------------------------------------------------------------------------------------------------------------------\n\n32-bit applications have limitations in terms of how much virtual memory is available, hence the number of hugepages they are able to allocate is also limited (1 GB per page size).\nIf your system has a lot (>1 GB per page size) of hugepage memory, not all of it will be allocated.\nDue to hugepages typically being allocated on a local NUMA node, the hugepages allocation the application gets during the initialization depends on which\nNUMA node it is running on (the EAL does not affinitize cores until much later in the initialization process).\nSometimes, the Linux OS runs the DPDK application on a core that is located on a different NUMA node from DPDK master core and\ntherefore all the hugepages are allocated on the wrong socket.\n\nTo avoid this scenario, either lower the amount of hugepage memory available to 1 GB per page size (or less), or run the application with taskset\naffinitizing the application to a would-be master core.\n\nFor example, if your EAL coremask is 0xff0, the master core will usually be the first core in the coremask (0x10); this is what you have to supply to taskset::\n\n taskset 0x10 ./l2fwd -c 0xff0 -n 2\n\nIn this way, the hugepages have a greater chance of being allocated to the correct socket.\nAdditionally, a ``--socket-mem`` option could be used to ensure the availability of memory for each socket, so that if hugepages were allocated on\nthe wrong socket, the application simply will not start.\n\n\nOn application startup, there is a lot of EAL information printed. Is there any way to reduce this?\n---------------------------------------------------------------------------------------------------\n\nYes, each EAL has a configuration file that is located in the /config directory. Within each configuration file, you will find CONFIG_RTE_LOG_LEVEL=8.\nYou can change this to a lower value, such as 6 to reduce this printout of debug information. The following is a list of LOG levels that can be found in the rte_log.h file.\nYou must remove, then rebuild, the EAL directory for the change to become effective as the configuration file creates the rte_config.h file in the EAL directory.\n\n.. code-block:: c\n\n #define RTE_LOG_EMERG 1U /* System is unusable. */\n #define RTE_LOG_ALERT 2U /* Action must be taken immediately. */\n #define RTE_LOG_CRIT 3U /* Critical conditions. */\n #define RTE_LOG_ERR 4U /* Error conditions. */\n #define RTE_LOG_WARNING 5U /* Warning conditions. */\n #define RTE_LOG_NOTICE 6U /* Normal but significant condition. */\n #define RTE_LOG_INFO 7U /* Informational. */\n #define RTE_LOG_DEBUG 8U /* Debug-level messages. */\n\n\nHow can I tune my network application to achieve lower latency?\n---------------------------------------------------------------\n\nTraditionally, there is a trade-off between throughput and latency. An application can be tuned to achieve a high throughput,\nbut the end-to-end latency of an average packet typically increases as a result.\nSimilarly, the application can be tuned to have, on average, a low end-to-end latency at the cost of lower throughput.\n\nTo achieve higher throughput, the DPDK attempts to aggregate the cost of processing each packet individually by processing packets in bursts.\nUsing the testpmd application as an example, the \"burst\" size can be set on the command line to a value of 16 (also the default value).\nThis allows the application to request 16 packets at a time from the PMD.\nThe testpmd application then immediately attempts to transmit all the packets that were received, in this case, all 16 packets.\nThe packets are not transmitted until the tail pointer is updated on the corresponding TX queue of the network port.\nThis behavior is desirable when tuning for high throughput because the cost of tail pointer updates to both the RX and TX queues\ncan be spread across 16 packets, effectively hiding the relatively slow MMIO cost of writing to the PCIe* device.\n\nHowever, this is not very desirable when tuning for low latency, because the first packet that was received must also wait for the other 15 packets to be received.\nIt cannot be transmitted until the other 15 packets have also been processed because the NIC will not know to transmit the packets until the TX tail pointer has been updated,\nwhich is not done until all 16 packets have been processed for transmission.\n\nTo consistently achieve low latency even under heavy system load, the application developer should avoid processing packets in bunches.\nThe testpmd application can be configured from the command line to use a burst value of 1.\nThis allows a single packet to be processed at a time, providing lower latency, but with the added cost of lower throughput.\n\n\nWithout NUMA enabled, my network throughput is low, why?\n--------------------------------------------------------\n\nI have a dual Intel® Xeon® E5645 processors 2.40 GHz with four Intel® 82599 10 Gigabit Ethernet NICs.\nUsing eight logical cores on each processor with RSS set to distribute network load from two 10 GbE interfaces to the cores on each processor.\n\nWithout NUMA enabled, memory is allocated from both sockets, since memory is interleaved.\nTherefore, each 64B chunk is interleaved across both memory domains.\n\nThe first 64B chunk is mapped to node 0, the second 64B chunk is mapped to node 1, the third to node 0, the fourth to node 1.\nIf you allocated 256B, you would get memory that looks like this:\n\n.. code-block:: console\n\n 256B buffer\n Offset 0x00 - Node 0\n Offset 0x40 - Node 1\n Offset 0x80 - Node 0\n Offset 0xc0 - Node 1\n\nTherefore, packet buffers and descriptor rings are allocated from both memory domains, thus incurring QPI bandwidth accessing the other memory and much higher latency.\nFor best performance with NUMA disabled, only one socket should be populated.\n\n\nI am getting errors about not being able to open files. Why?\n------------------------------------------------------------\n\nAs the DPDK operates, it opens a lot of files, which can result in reaching the open files limits, which is set using the ulimit command or in the limits.conf file.\nThis is especially true when using a large number (>512) of 2 MB huge pages. Please increase the open file limit if your application is not able to open files.\nThis can be done either by issuing a ulimit command or editing the limits.conf file. Please consult Linux* manpages for usage information.\n\n\nDoes my kernel require patching to run the DPDK?\n------------------------------------------------\n\nAny kernel greater than version 2.6.33 can be used without any patches applied. The following kernels may require patches to provide hugepage support:\n\n* Kernel version 2.6.32 requires the following patches applied:\n\n * `mm: hugetlb: add hugepage support to pagemap `_\n\n * `mm: hugetlb: fix hugepage memory leak in walk_page_range() `_\n\n * `hugetlb: add nodemask arg to huge page alloc, free and surplus adjust functions `_\n (not mandatory, but recommended on a NUMA system to support per-NUMA node hugepages allocation)\n\n* Kernel version 2.6.31, requires the above patches plus the following:\n\n * `UIO: Add name attributes for mappings and port regions `_\n\n\nVF driver for IXGBE devices cannot be initialized\n-------------------------------------------------\n\nSome versions of Linux* IXGBE driver do not assign a random MAC address to VF devices at initialization.\nIn this case, this has to be done manually on the VM host, using the following command:\n\n.. code-block:: console\n\n ip link set vf mac \n\nwhere being the interface providing the virtual functions for example, eth0, being the virtual function number, for example 0,\nand being the desired MAC address.\n\n\nIs it safe to add an entry to the hash table while running?\n------------------------------------------------------------\nCurrently the table implementation is not a thread safe implementation and assumes that locking between threads and processes is handled by the user's application.\nThis is likely to be supported in future releases.\n\n\nWhat is the purpose of setting iommu=pt?\n----------------------------------------\nDPDK uses a 1:1 mapping and does not support IOMMU. IOMMU allows for simpler VM physical address translation.\nThe second role of IOMMU is to allow protection from unwanted memory access by an unsafe device that has DMA privileges.\nUnfortunately, the protection comes with an extremely high performance cost for high speed NICs.\n\nSetting ``iommu=pt`` disables IOMMU support for the hypervisor.\n\n\nWhen trying to send packets from an application to itself, meaning smac==dmac, using Intel(R) 82599 VF packets are lost.\n------------------------------------------------------------------------------------------------------------------------\n\nCheck on register ``LLE(PFVMTXSSW[n])``, which allows an individual pool to send traffic and have it looped back to itself.\n\n\nCan I split packet RX to use DPDK and have an application's higher order functions continue using Linux* pthread?\n-----------------------------------------------------------------------------------------------------------------\n\nThe DPDK's lcore threads are Linux* pthreads bound onto specific cores. Configure the DPDK to do work on the same\ncores and run the application's other work on other cores using the DPDK's \"coremask\" setting to specify which\ncores it should launch itself on.\n\n\nIs it possible to exchange data between DPDK processes and regular userspace processes via some shared memory or IPC mechanism?\n-------------------------------------------------------------------------------------------------------------------------------\n\nYes - DPDK processes are regular Linux/BSD processes, and can use all OS provided IPC mechanisms.\n\n\nCan the multiple queues in Intel(R) I350 be used with DPDK?\n-----------------------------------------------------------\n\nI350 has RSS support and 8 queue pairs can be used in RSS mode. It should work with multi-queue DPDK applications using RSS.\n\n\nHow can hugepage-backed memory be shared among multiple processes?\n------------------------------------------------------------------\n\nSee the Primary and Secondary examples in the :ref:`multi-process sample application `.\n" }, { "path": "doc/guides/faq/index.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nDPDK FAQ\n========\n\nThis document contains some Frequently Asked Questions that arise when working with DPDK.\n\nContents\n\n.. toctree::\n :maxdepth: 2\n :numbered:\n\n faq\n" }, { "path": "doc/guides/freebsd_gsg/build_dpdk.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _building_from_source:\n\nCompiling the DPDK Target from Source\n=====================================\n\n.. note::\n\n Testing has been performed using FreeBSD* 10.0-RELEASE (x86_64) and requires the\n installation of the kernel sources, which should be included during the\n installation of FreeBSD*. The DPDK also requires the use of FreeBSD*\n ports to compile and function.\n\nSystem Requirements\n-------------------\n\nThe DPDK and its applications require the GNU make system (gmake)\nto build on FreeBSD*. Optionally, gcc may also be used in place of clang\nto build the DPDK, in which case it too must be installed prior to\ncompiling the DPDK. The installation of these tools is covered in this\nsection.\n\nCompiling the DPDK requires the FreeBSD kernel sources, which should be\nincluded during the installation of FreeBSD* on the development platform.\nThe DPDK also requires the use of FreeBSD* ports to compile and function.\n\nTo use the FreeBSD* ports system, it is required to update and extract the FreeBSD*\nports tree by issuing the following commands:\n\n.. code-block:: console\n\n root@host:~ # portsnap fetch\n root@host:~ # portsnap extract\n\nIf the environment requires proxies for external communication, these can be set\nusing:\n\n.. code-block:: console\n\n root@host:~ # setenv http_proxy :\n root@host:~ # setenv ftp_proxy :\n\nThe FreeBSD* ports below need to be installed prior to building the DPDK.\nIn general these can be installed using the following set of commands:\n\n#. cd /usr/ports/\n\n#. make config-recursive\n\n#. make install\n\n#. make clean\n\nEach port location can be found using:\n\n.. code-block:: console\n\n user@host:~ # whereis \n\nThe ports required and their locations are as follows:\n\ndialog4ports\n /usr/ports/ports-mgmt/dialog4ports\n\nGNU make(gmake)\n /usr/ports/devel/gmake\n\ncoreutils\n /usr/ports/sysutils/coreutils\n\nFor compiling and using the DPDK with gcc, it too must be installed\nfrom the ports collection:\n\ngcc: version 4.8 is recommended\n /usr/ports/lang/gcc48\n (Ensure that CPU_OPTS is selected (default is OFF))\n\nWhen running the make config-recursive command, a dialog may be presented to the\nuser. For the installation of the DPDK, the default options were used.\n\n.. note::\n\n To avoid multiple dialogs being presented to the user during make install,\n it is advisable before running the make install command to re-run the\n make config -recursive command until no more dialogs are seen.\n\n\nInstall the DPDK and Browse Sources\n-----------------------------------\n\nFirst, uncompress the archive and move to the DPDK source directory:\n\n.. code-block:: console\n\n user@host:~ # unzip DPDK-zip\n user@host:~ # cd DPDK-\n user@host:~/DPDK # ls\n app/ config/ examples/ lib/ LICENSE.GPL LICENSE.LGPL Makefile mk/ scripts/ tools/\n\nThe DPDK is composed of several directories:\n\n* lib: Source code of DPDK libraries\n\n* app: Source code of DPDK applications (automatic tests)\n\n* examples: Source code of DPDK applications\n\n* config, tools, scripts, mk: Framework-related makefiles, scripts and configuration\n\nInstallation of the DPDK Target Environments\n--------------------------------------------\n\nThe format of a DPDK target is:\n\nARCH-MACHINE-EXECENV-TOOLCHAIN\n\nWhere:\n\n* ARCH is: x86_64\n\n* MACHINE is: native\n\n* EXECENV is: bsdapp\n\n* TOOLCHAIN is: gcc | clang\n\nThe configuration files for the DPDK targets can be found in the DPDK/config\ndirectory in the form of:\n\n::\n\n defconfig_ARCH-MACHINE-EXECENV-TOOLCHAIN\n\n.. note::\n\n Configuration files are provided with the RTE_MACHINE optimization level set.\n Within the configuration files, the RTE_MACHINE configuration value is set\n to native, which means that the compiled software is tuned for the platform\n on which it is built. For more information on this setting, and its\n possible values, see the *DPDK Programmers Guide*.\n\nTo install and make the target, use \"gmake install T=\".\n\nFor example to compile for FreeBSD* use:\n\n.. code-block:: console\n\n gmake install T=x86_64-native-bsdapp-clang\n\n.. note::\n\n\tIf the compiler binary to be used does not correspond to that given in the\n\tTOOLCHAIN part of the target, the compiler command may need to be explicitly\n\tspecified. For example, if compiling for gcc, where the gcc binary is called\n\tgcc4.8, the command would need to be \"gmake install T= CC=gcc4.8\".\n\nBrowsing the Installed DPDK Environment Target\n----------------------------------------------\n\nOnce a target is created, it contains all the libraries and header files for the\nDPDK environment that are required to build customer applications.\nIn addition, the test and testpmd applications are built under the build/app\ndirectory, which may be used for testing. A kmod directory is also present that\ncontains the kernel modules to install:\n\n.. code-block:: console\n\n user@host:~/DPDK # ls x86_64-native-bsdapp-gcc\n app build hostapp include kmod lib Makefile\n\n\n.. _loading_contigmem:\n\nLoading the DPDK contigmem Module\n---------------------------------\n\nTo run a DPDK application, physically contiguous memory is required.\nIn the absence of non-transparent superpages, the included sources for the\ncontigmem kernel module provides the ability to present contiguous blocks of\nmemory for the DPDK to use. The contigmem module must be loaded into the\nrunning kernel before any DPDK is run. The module is found in the kmod\nsub-directory of the DPDK target directory.\n\nThe amount of physically contiguous memory along with the number of physically\ncontiguous blocks to be reserved by the module can be set at runtime prior to\nmodule loading using:\n\n.. code-block:: console\n\n root@host:~ # kenv hw.contigmem.num_buffers=n\n root@host:~ # kenv hw.contigmem.buffer_size=m\n\nThe kernel environment variables can also be specified during boot by placing the\nfollowing in /boot/loader.conf:\n\n::\n\n hw.contigmem.num_buffers=n hw.contigmem.buffer_size=m\n\nThe variables can be inspected using the following command:\n\n.. code-block:: console\n\n root@host:~ # sysctl -a hw.contigmem\n\nWhere n is the number of blocks and m is the size in bytes of each area of\ncontiguous memory. A default of two buffers of size 1073741824 bytes (1 Gigabyte)\neach is set during module load if they are not specified in the environment.\n\nThe module can then be loaded using kldload (assuming that the current directory\nis the DPDK target directory):\n\n.. code-block:: console\n\n kldload ./kmod/contigmem.ko\n\nIt is advisable to include the loading of the contigmem module during the boot\nprocess to avoid issues with potential memory fragmentation during later system\nup time. This can be achieved by copying the module to the /boot/kernel/\ndirectory and placing the following into /boot/loader.conf:\n\n::\n\n contigmem_load=\"YES\"\n\n.. note::\n\n The contigmem_load directive should be placed after any definitions of\n hw.contigmem.num_buffers and hw.contigmem.buffer_size if the default values\n are not to be used.\n\nAn error such as:\n\n.. code-block:: console\n\n kldload: can't load ./x86_64-native-bsdapp-gcc/kmod/contigmem.ko: Exec format error\n\nis generally attributed to not having enough contiguous memory\navailable and can be verified via dmesg or /var/log/messages:\n\n.. code-block:: console\n\n kernel: contigmalloc failed for buffer \n\nTo avoid this error, reduce the number of buffers or the buffer size.\n\n.. _loading_nic_uio:\n\nLoading the DPDK nic_uio Module\n-------------------------------\n\nAfter loading the contigmem module, the nic_uio must also be loaded into the\nrunning kernel prior to running any DPDK application. This module must\nbe loaded using the kldload command as shown below (assuming that the current\ndirectory is the DPDK target directory).\n\n.. code-block:: console\n\n kldload ./kmod/nic_uio.ko\n\n.. note::\n\n If the ports to be used are currently bound to a existing kernel driver\n then the hw.nic_uio.bdfs sysctl value will need to be set before loading the\n module. Setting this value is described in the next section below.\n\nCurrently loaded modules can be seen by using the \"kldstat\" command and a module\ncan be removed from the running kernel by using \"kldunload \".\n\nTo load the module during boot, copy the nic_uio module to /boot/kernel\nand place the following into /boot/loader.conf:\n\n::\n\n nic_uio_load=\"YES\"\n\n.. note::\n\n nic_uio_load=\"YES\" must appear after the contigmem_load directive, if it exists.\n\nBy default, the nic_uio module will take ownership of network ports if they are\nrecognized DPDK devices and are not owned by another module. However, since\nthe FreeBSD kernel includes support, either built-in, or via a separate driver\nmodule, for most network card devices, it is likely that the ports to be used are\nalready bound to a driver other than nic_uio. The following sub-section describe\nhow to query and modify the device ownership of the ports to be used by\nDPDK applications.\n\n.. _binding_network_ports:\n\nBinding Network Ports to the nic_uio Module\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nDevice ownership can be viewed using the pciconf -l command. The example below shows\nfour Intel® 82599 network ports under \"if_ixgbe\" module ownership.\n\n.. code-block:: console\n\n user@host:~ # pciconf -l\n ix0@pci0:1:0:0: class=0x020000 card=0x00038086 chip=0x10fb8086 rev=0x01 hdr=0x00\n ix1@pci0:1:0:1: class=0x020000 card=0x00038086 chip=0x10fb8086 rev=0x01 hdr=0x00\n ix2@pci0:2:0:0: class=0x020000 card=0x00038086 chip=0x10fb8086 rev=0x01 hdr=0x00\n ix3@pci0:2:0:1: class=0x020000 card=0x00038086 chip=0x10fb8086 rev=0x01 hdr=0x00\n\nThe first column constitutes three components:\n\n#. Device name: ixN\n\n#. Unit name: pci0\n\n#. Selector (Bus:Device:Function): 1:0:0\n\nWhere no driver is associated with a device, the device name will be none.\n\nBy default, the FreeBSD* kernel will include built-in drivers for the most common\ndevices; a kernel rebuild would normally be required to either remove the drivers\nor configure them as loadable modules.\n\nTo avoid building a custom kernel, the nic_uio module can detach a network port\nfrom its current device driver. This is achieved by setting the hw.nic_uio.bdfs\nkernel environment variable prior to loading nic_uio, as follows:\n\n::\n\n hw.nic_uio.bdfs=\"b:d:f,b:d:f,...\"\n\nWhere a comma separated list of selectors is set, the list must not contain any\nwhitespace.\n\nFor example to re-bind \"ix2\\@pci0:2:0:0\" and \"ix3\\@pci0:2:0:1\" to the nic_uio module\nupon loading, use the following command:\n\n.. code-block:: console\n\n kenv hw.nic_uio.bdfs=\"2:0:0,2:0:1\"\n\nThe variable can also be specified during boot by placing the following into\n\"/boot/loader.conf\", before the previously-described \"nic_uio_load\" line - as\nshown.\n\n::\n\n hw.nic_uio.bdfs=\"2:0:0,2:0:1\"\n nic_uio_load=\"YES\"\n\nBinding Network Ports Back to their Original Kernel Driver\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nIf the original driver for a network port has been compiled into the kernel,\nit is necessary to reboot FreeBSD* to restore the original device binding. Before\ndoing so, update or remove the \"hw.nic_uio.bdfs\" in \"/boot/loader.conf\".\n\nIf rebinding to a driver that is a loadable module, the network port binding can\nbe reset without rebooting. To do so, unload both the target kernel module and the\nnic_uio module, modify or clear the \"hw.nic_uio.bdfs\" kernel environment (kenv)\nvalue, and reload the two drivers - first the original kernel driver, and then\nthe nic_uio driver. [The latter does not need to be reloaded unless there are\nports that are still to be bound to it].\n\nExample commands to perform these steps are shown below:\n\n.. code-block:: console\n\n kldunload nic_uio\n kldunload \n\n kenv -u hw.nic_uio.bdfs # to clear the value completely\n\n kenv hw.nic_uio.bdfs=\"b:d:f,b:d:f,...\" # to update the list of ports to bind\n\n kldload \n\n kldload nic_uio # optional\n" }, { "path": "doc/guides/freebsd_gsg/build_sample_apps.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _compiling_sample_apps:\n\nCompiling and Running Sample Applications\n=========================================\n\nThe chapter describes how to compile and run applications in a DPDK\nenvironment. It also provides a pointer to where sample applications are stored.\n\nCompiling a Sample Application\n------------------------------\n\nOnce a DPDK target environment directory has been created (such as\nx86_64-native-bsdapp-clang), it contains all libraries and header files required\nto build an application.\n\nWhen compiling an application in the FreeBSD* environment on the DPDK,\nthe following variables must be exported:\n\n* RTE_SDK - Points to the DPDK installation directory.\n\n* RTE_TARGET - Points to the DPDK target environment directory.\n For FreeBSD*, this is the x86_64-native-bsdapp-clang or\n x86_64-native-bsdapp-gcc directory.\n\nThe following is an example of creating the helloworld application, which runs\nin the DPDK FreeBSD* environment. While the example demonstrates compiling\nusing gcc version 4.8, compiling with clang will be similar, except that the \"CC=\"\nparameter can probably be omitted. The \"helloworld\" example may be found in the\n${RTE_SDK}/examples directory.\n\nThe directory contains the main.c file. This file, when combined with the\nlibraries in the DPDK target environment, calls the various functions to\ninitialize the DPDK environment, then launches an entry point (dispatch\napplication) for each core to be utilized. By default, the binary is generated\nin the build directory.\n\n.. code-block:: console\n\n user@host:~/DPDK$ cd examples/helloworld/\n user@host:~/DPDK/examples/helloworld$ setenv RTE_SDK $HOME/DPDK\n user@host:~/DPDK/examples/helloworld$ setenv RTE_TARGET x86_64-native-bsdapp-gcc\n user@host:~/DPDK/examples/helloworld$ gmake CC=gcc48\n CC main.o\n LD helloworld\n INSTALL-APP helloworld\n INSTALL-MAP helloworld.map\n user@host:~/DPDK/examples/helloworld$ ls build/app\n helloworld helloworld.map\n\n.. note::\n\n In the above example, helloworld was in the directory structure of the\n DPDK. However, it could have been located outside the directory\n structure to keep the DPDK structure intact. In the following case,\n the helloworld application is copied to a new directory as a new starting\n point.\n\n.. code-block:: console\n\n user@host:~$ setenv RTE_SDK /home/user/DPDK\n user@host:~$ cp -r $(RTE_SDK)/examples/helloworld my_rte_app\n user@host:~$ cd my_rte_app/\n user@host:~$ setenv RTE_TARGET x86_64-native-bsdapp-gcc\n user@host:~/my_rte_app$ gmake CC=gcc48\n CC main.o\n LD helloworld\n INSTALL-APP helloworld\n INSTALL-MAP helloworld.map\n\n.. _running_sample_app:\n\nRunning a Sample Application\n----------------------------\n\n#. The contigmem and nic_uio modules must be set up prior to running an application.\n\n#. Any ports to be used by the application must be already bound to the nic_uio module,\n as described in section :ref:`binding_network_ports`, prior to running the application.\n The application is linked with the DPDK target environment's Environment\n Abstraction Layer (EAL) library, which provides some options that are generic\n to every DPDK application.\n\nThe following is the list of options that can be given to the EAL:\n\n.. code-block:: console\n\n ./rte-app -c COREMASK -n NUM [-b ] [-r NUM] [-v] [--proc-type ]\n\n.. note::\n\n EAL has a common interface between all operating systems and is based on the\n Linux* notation for PCI devices. For example, a FreeBSD* device selector of\n pci0:2:0:1 is referred to as 02:00.1 in EAL.\n\nThe EAL options for FreeBSD* are as follows:\n\n* -c COREMASK\n : A hexadecimal bit mask of the cores to run on. Note that core numbering\n can change between platforms and should be determined beforehand.\n\n* -n NUM\n : Number of memory channels per processor socket.\n\n* -b \n : blacklisting of ports; prevent EAL from using specified PCI device\n (multiple -b options are allowed).\n\n* --use-device\n : use the specified Ethernet device(s) only. Use comma-separate\n <[domain:]bus:devid.func> values. Cannot be used with -b option.\n\n* -r NUM\n : Number of memory ranks.\n\n* -v\n : Display version information on startup.\n\n* --proc-type\n : The type of process instance.\n\nOther options, specific to Linux* and are not supported under FreeBSD* are as follows:\n\n* socket-mem\n : Memory to allocate from hugepages on specific sockets.\n\n* --huge-dir\n : The directory where hugetlbfs is mounted.\n\n* --file-prefix\n : The prefix text used for hugepage filenames.\n\n* -m MB\n : Memory to allocate from hugepages, regardless of processor socket.\n It is recommended that --socket-mem be used instead of this option.\n\nThe -c and the -n options are mandatory; the others are optional.\n\nCopy the DPDK application binary to your target, then run the application\nas follows (assuming the platform has four memory channels, and that cores 0-3\nare present and are to be used for running the application):\n\n.. code-block:: console\n\n root@target:~$ ./helloworld -c f -n 4\n\n.. note::\n\n The --proc-type and --file-prefix EAL options are used for running multiple\n DPDK processes. See the “Multi-process Sample Application” chapter\n in the *DPDK Sample Applications User Guide and the DPDK\n Programmers Guide* for more details.\n\n.. _running_non_root:\n\nRunning DPDK Applications Without Root Privileges\n-------------------------------------------------\n\nAlthough applications using the DPDK use network ports and other hardware\nresources directly, with a number of small permission adjustments, it is possible\nto run these applications as a user other than “root”. To do so, the ownership,\nor permissions, on the following file system objects should be adjusted to ensure\nthat the user account being used to run the DPDK application has access\nto them:\n\n* The userspace-io device files in /dev, for example, /dev/uio0, /dev/uio1, and so on\n\n* The userspace contiguous memory device: /dev/contigmem\n\n.. note::\n\n Please refer to the DPDK Release Notes for supported applications.\n" }, { "path": "doc/guides/freebsd_gsg/index.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _freebsd_gsg:\n\nGetting Started Guide for FreeBSD\n=================================\n\n|today|\n\n**Contents**\n\n.. toctree::\n :maxdepth: 2\n :numbered:\n\n intro\n install_from_ports\n build_dpdk\n build_sample_apps\n" }, { "path": "doc/guides/freebsd_gsg/install_from_ports.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _install_from_ports:\n\nInstalling DPDK from the Ports Collection\n=========================================\n\nThe easiest way to get up and running with the DPDK on FreeBSD is to\ninstall it from the ports collection. Details of getting and using the ports\ncollection are documented in the FreeBSD Handbook at:\n\n\thttps://www.freebsd.org/doc/handbook/ports-using.html\n\n.. note::\n\n Testing has been performed using FreeBSD* 10.0-RELEASE (x86_64) and requires the\n installation of the kernel sources, which should be included during the\n installation of FreeBSD*.\n\nInstalling the DPDK FreeBSD Port\n--------------------------------\n\nOn a system with the ports collection installed in /usr/ports, the DPDK\ncan be installed using the commands:\n\n.. code-block:: console\n\n root@host:~ # cd /usr/ports/net/dpdk\n\n root@host:~ # make install\n\nAfter the installation of the DPDK port, instructions will be printed on\nhow to install the kernel modules required to use the DPDK. A more\ncomplete version of these instructions can be found in the sections\n:ref:`loading_contigmem` and :ref:`loading_nic_uio`. Normally, lines like\nthose below would be added to the file \"/boot/loader.conf\".\n\n.. code-block:: console\n\n # reserve 2 x 1G blocks of contiguous memory using contigmem driver\n hw.contigmem.num_buffers=2\n hw.contigmem.buffer_size=1073741824\n contigmem_load=\"YES\"\n # identify NIC devices for DPDK apps to use and load nic_uio driver\n hw.nic_uio.bdfs=\"2:0:0,2:0:1\"\n nic_uio_load=\"YES\"\n\nCompiling and Running the Example Applications\n----------------------------------------------\n\nWhen the DPDK has been installed from the ports collection it installs\nits example applications in \"/usr/local/share/dpdk/examples\" - also accessible via\nsymlink as \"/usr/local/share/examples/dpdk\". These examples can be compiled and\nrun as described in :ref:`compiling_sample_apps`. In this case, the required\nenvironmental variables should be set as below:\n\n* RTE_SDK=/usr/local/share/dpdk\n\n* RTE_TARGET=x86_64-native-bsdapp-clang\n\n.. note::\n\n\tTo install a copy of the DPDK compiled using gcc, please download the\n\tofficial DPDK package from http://dpdk.org/ and install manually using\n\tthe instructions given in the next chapter, :ref:`building_from_source`\n\nAn example application can therefore be copied to a user's home directory and\ncompiled and run as below:\n\n.. code-block:: console\n\n user@host:~$ export RTE_SDK=/usr/local/share/dpdk\n\n user@host:~$ export RTE_TARGET=x86_64-native-bsdapp-clang\n\n user@host:~$ cp -r /usr/local/share/dpdk/examples/helloworld .\n\n user@host:~$ cd helloworld/\n\n user@host:~/helloworld$ gmake\n CC main.o\n LD helloworld\n INSTALL-APP helloworld\n INSTALL-MAP helloworld.map\n\n user@host:~/helloworld$ sudo ./build/helloworld -c F -n 2\n EAL: Contigmem driver has 2 buffers, each of size 1GB\n EAL: Sysctl reports 8 cpus\n EAL: Detected lcore 0\n EAL: Detected lcore 1\n EAL: Detected lcore 2\n EAL: Detected lcore 3\n EAL: Support maximum 64 logical core(s) by configuration.\n EAL: Detected 4 lcore(s)\n EAL: Setting up physically contiguous memory...\n EAL: Mapped memory segment 1 @ 0x802400000: physaddr:0x40000000, len 1073741824\n EAL: Mapped memory segment 2 @ 0x842400000: physaddr:0x100000000, len 1073741824\n EAL: WARNING: clock_gettime cannot use CLOCK_MONOTONIC_RAW and HPET is not available - clock timings may be less accurate.\n EAL: TSC frequency is ~3569023 KHz\n EAL: PCI scan found 24 devices\n EAL: Master core 0 is ready (tid=0x802006400)\n EAL: Core 1 is ready (tid=0x802006800)\n EAL: Core 3 is ready (tid=0x802007000)\n EAL: Core 2 is ready (tid=0x802006c00)\n EAL: PCI device 0000:01:00.0 on NUMA socket 0\n EAL: probe driver: 8086:10fb rte_ixgbe_pmd\n EAL: PCI memory mapped at 0x80074a000\n EAL: PCI memory mapped at 0x8007ca000\n EAL: PCI device 0000:01:00.1 on NUMA socket 0\n EAL: probe driver: 8086:10fb rte_ixgbe_pmd\n EAL: PCI memory mapped at 0x8007ce000\n EAL: PCI memory mapped at 0x80084e000\n EAL: PCI device 0000:02:00.0 on NUMA socket 0\n EAL: probe driver: 8086:10fb rte_ixgbe_pmd\n EAL: PCI memory mapped at 0x800852000\n EAL: PCI memory mapped at 0x8008d2000\n EAL: PCI device 0000:02:00.1 on NUMA socket 0\n EAL: probe driver: 8086:10fb rte_ixgbe_pmd\n EAL: PCI memory mapped at 0x801b3f000\n EAL: PCI memory mapped at 0x8008d6000\n hello from core 1\n hello from core 2\n hello from core 3\n hello from core 0\n\n.. note::\n\n\tTo run a DPDK process as a non-root user, adjust the permissions on\n\tthe /dev/contigmem and /dev/uio device nodes as described in section\n\t:ref:`running_non_root`\n\n.. note::\n\tFor an explanation of the command-line parameters that can be passed to an\n\tDPDK application, see section :ref:`running_sample_app`.\n" }, { "path": "doc/guides/freebsd_gsg/intro.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIntroduction\n============\n\nThis document contains instructions for installing and configuring the\nData Plane Development Kit (DPDK) software. It is designed to get customers\nup and running quickly and describes how to compile and run a\nDPDK application in a FreeBSD* application (bsdapp) environment, without going\ndeeply into detail.\n\nFor a comprehensive guide to installing and using FreeBSD*, the following\nhandbook is available from the FreeBSD* Documentation Project:\n\n`http://www.freebsd.org/doc/en_US.ISO8859-1/books/handbook/index.html `_\n\n.. note::\n\n\tThe DPDK is now available as part of the FreeBSD ports collection.\n\tInstalling via the ports collection infrastructure is now the recommended\n\tway to install the DPDK on FreeBSD, and is documented in the\n\tnext chapter, :ref:`install_from_ports`.\n\nDocumentation Roadmap\n---------------------\n\nThe following is a list of DPDK documents in the suggested reading order:\n\n* **Release Notes** : Provides release-specific information, including supported\n features, limitations, fixed issues, known issues and so on. Also, provides the\n answers to frequently asked questions in FAQ format.\n\n* **Getting Started Guide** (this document): Describes how to install and\n configure the DPDK; designed to get users up and running quickly with the\n software.\n\n* **Programmer's Guide**: Describes:\n\n * The software architecture and how to use it (through examples),\n specifically in a Linux* application (linuxapp) environment\n\n * The content of the DPDK, the build system (including the commands\n that can be used in the root DPDK Makefile to build the development\n kit and an application) and guidelines for porting an application\n\n * Optimizations used in the software and those that should be considered\n for new development\n\n A glossary of terms is also provided.\n\n* **API Reference**: Provides detailed information about DPDK functions,\n data structures and other programming constructs.\n\n* **Sample Applications User Guide**: Describes a set of sample applications.\n Each chapter describes a sample application that showcases specific functionality\n and provides instructions on how to compile, run and use the sample application.\n\n.. note::\n\n These documents are available for download as a separate documentation\n package at the same location as the DPDK code package.\n" }, { "path": "doc/guides/index.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nDPDK documentation\n==================\n\nContents:\n\n.. toctree::\n :maxdepth: 1\n :titlesonly:\n\n linux_gsg/index\n freebsd_gsg/index\n xen/index\n prog_guide/index\n nics/index\n sample_app_ug/index\n testpmd_app_ug/index\n faq/index\n rel_notes/index\n contributing/index\n" }, { "path": "doc/guides/linux_gsg/build_dpdk.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nCompiling the DPDK Target from Source\n=====================================\n\n.. note::\n\n Parts of this process can also be done using the setup script described in Chapter 6 of this document.\n\nInstall the DPDK and Browse Sources\n-----------------------------------\n\nFirst, uncompress the archive and move to the uncompressed DPDK source directory:\n\n.. code-block:: console\n\n user@host:~$ unzip DPDK-.zip\n user@host:~$ cd DPDK-\n user@host:~/DPDK-$ ls\n app/ config/ drivers/ examples/ lib/ LICENSE.GPL LICENSE.LGPL Makefile mk/ scripts/ tools/\n\nThe DPDK is composed of several directories:\n\n* lib: Source code of DPDK libraries\n\n* drivers: Source code of DPDK poll-mode drivers\n\n* app: Source code of DPDK applications (automatic tests)\n\n* examples: Source code of DPDK application examples\n\n* config, tools, scripts, mk: Framework-related makefiles, scripts and configuration\n\nInstallation of DPDK Target Environments\n----------------------------------------\n\nThe format of a DPDK target is:\n\n ARCH-MACHINE-EXECENV-TOOLCHAIN\n\nwhere:\n\n* ARCH can be: i686, x86_64, ppc_64\n\n* MACHINE can be: native, ivshmem, power8\n\n* EXECENV can be: linuxapp, bsdapp\n\n* TOOLCHAIN can be: gcc, icc\n\nThe targets to be installed depend on the 32-bit and/or 64-bit packages and compilers installed on the host.\nAvailable targets can be found in the DPDK/config directory.\nThe defconfig\\_ prefix should not be used.\n\n.. note::\n\n Configuration files are provided with the RTE_MACHINE optimization level set.\n Within the configuration files, the RTE_MACHINE configuration value is set to native,\n which means that the compiled software is tuned for the platform on which it is built.\n For more information on this setting, and its possible values, see the *DPDK Programmers Guide*.\n\nWhen using the Intel® C++ Compiler (icc), one of the following commands should be invoked for 64-bit or 32-bit use respectively.\nNotice that the shell scripts update the $PATH variable and therefore should not be performed in the same session.\nAlso, verify the compiler's installation directory since the path may be different:\n\n.. code-block:: console\n\n source /opt/intel/bin/iccvars.sh intel64\n source /opt/intel/bin/iccvars.sh ia32\n\nTo install and make targets, use the make install T= command in the top-level DPDK directory.\n\nFor example, to compile a 64-bit target using icc, run:\n\n.. code-block:: console\n\n make install T=x86_64-native-linuxapp-icc\n\nTo compile a 32-bit build using gcc, the make command should be:\n\n.. code-block:: console\n\n make install T=i686-native-linuxapp-gcc\n\nTo compile all 64-bit targets using gcc, use:\n\n.. code-block:: console\n\n make install T=x86_64*gcc\n\nTo compile all 64-bit targets using both gcc and icc, use:\n\n.. code-block:: console\n\n make install T=x86_64-*\n\n.. note::\n\n The wildcard operator (*) can be used to create multiple targets at the same time.\n\nTo prepare a target without building it, for example, if the configuration changes need to be made before compilation,\nuse the make config T= command:\n\n.. code-block:: console\n\n make config T=x86_64-native-linuxapp-gcc\n\n.. warning::\n\n Any kernel modules to be used, e.g. igb_uio, kni, must be compiled with the\n same kernel as the one running on the target.\n If the DPDK is not being built on the target machine,\n the RTE_KERNELDIR environment variable should be used to point the compilation at a copy of the kernel version to be used on the target machine.\n\nOnce the target environment is created, the user may move to the target environment directory and continue to make code changes and re-compile.\nThe user may also make modifications to the compile-time DPDK configuration by editing the .config file in the build directory.\n(This is a build-local copy of the defconfig file from the top- level config directory).\n\n.. code-block:: console\n\n cd x86_64-native-linuxapp-gcc\n vi .config\n make\n\nIn addition, the make clean command can be used to remove any existing compiled files for a subsequent full, clean rebuild of the code.\n\nBrowsing the Installed DPDK Environment Target\n----------------------------------------------\n\nOnce a target is created it contains all libraries, including poll-mode drivers, and header files for the DPDK environment that are required to build customer applications.\nIn addition, the test and testpmd applications are built under the build/app directory, which may be used for testing.\nA kmod directory is also present that contains kernel modules which may be loaded if needed.\n\n.. code-block:: console\n\n $ ls x86_64-native-linuxapp-gcc\n app build hostapp include kmod lib Makefile\n\nLoading Modules to Enable Userspace IO for DPDK\n-----------------------------------------------\n\nTo run any DPDK application, a suitable uio module can be loaded into the running kernel.\nIn many cases, the standard uio_pci_generic module included in the Linux kernel\ncan provide the uio capability. This module can be loaded using the command\n\n.. code-block:: console\n\n sudo modprobe uio_pci_generic\n\nAs an alternative to the uio_pci_generic, the DPDK also includes the igb_uio\nmodule which can be found in the kmod subdirectory referred to above. It can\nbe loaded as shown below:\n\n.. code-block:: console\n\n sudo modprobe uio\n sudo insmod kmod/igb_uio.ko\n\n.. note::\n\n For some devices which lack support for legacy interrupts, e.g. virtual function\n (VF) devices, the igb_uio module may be needed in place of uio_pci_generic.\n\nSince DPDK release 1.7 onward provides VFIO support, use of UIO is optional\nfor platforms that support using VFIO.\n\nLoading VFIO Module\n-------------------\n\nTo run an DPDK application and make use of VFIO, the vfio-pci module must be loaded:\n\n.. code-block:: console\n\n sudo modprobe vfio-pci\n\nNote that in order to use VFIO, your kernel must support it.\nVFIO kernel modules have been included in the Linux kernel since version 3.6.0 and are usually present by default,\nhowever please consult your distributions documentation to make sure that is the case.\n\nAlso, to use VFIO, both kernel and BIOS must support and be configured to use IO virtualization (such as Intel® VT-d).\n\nFor proper operation of VFIO when running DPDK applications as a non-privileged user, correct permissions should also be set up.\nThis can be done by using the DPDK setup script (called setup.sh and located in the tools directory).\n\nBinding and Unbinding Network Ports to/from the Kernel Modules\n----------------------------------------------------------------------\n\nAs of release 1.4, DPDK applications no longer automatically unbind all supported network ports from the kernel driver in use.\nInstead, all ports that are to be used by an DPDK application must be bound to the\nuio_pci_generic, igb_uio or vfio-pci module before the application is run.\nAny network ports under Linux* control will be ignored by the DPDK poll-mode drivers and cannot be used by the application.\n\n.. warning::\n\n The DPDK will, by default, no longer automatically unbind network ports from the kernel driver at startup.\n Any ports to be used by an DPDK application must be unbound from Linux* control and\n bound to the uio_pci_generic, igb_uio or vfio-pci module before the application is run.\n\nTo bind ports to the uio_pci_generic, igb_uio or vfio-pci module for DPDK use,\nand then subsequently return ports to Linux* control,\na utility script called dpdk_nic _bind.py is provided in the tools subdirectory.\nThis utility can be used to provide a view of the current state of the network ports on the system,\nand to bind and unbind those ports from the different kernel modules, including the uio and vfio modules.\nThe following are some examples of how the script can be used.\nA full description of the script and its parameters can be obtained by calling the script with the --help or --usage options.\nNote that the uio or vfio kernel modules to be used, should be loaded into the kernel before\nrunning the dpdk_nic_bind.py script.\n\n.. warning::\n\n Due to the way VFIO works, there are certain limitations to which devices can be used with VFIO.\n Mainly it comes down to how IOMMU groups work.\n Any Virtual Function device can be used with VFIO on its own, but physical devices will require either all ports bound to VFIO,\n or some of them bound to VFIO while others not being bound to anything at all.\n\n If your device is behind a PCI-to-PCI bridge, the bridge will then be part of the IOMMU group in which your device is in.\n Therefore, the bridge driver should also be unbound from the bridge PCI device for VFIO to work with devices behind the bridge.\n\n.. warning::\n\n While any user can run the dpdk_nic_bind.py script to view the status of the network ports,\n binding or unbinding network ports requires root privileges.\n\nTo see the status of all network ports on the system:\n\n.. code-block:: console\n\n root@host:DPDK# ./tools/dpdk_nic_bind.py --status\n\n Network devices using DPDK-compatible driver\n ============================================\n 0000:82:00.0 '82599EB 10-Gigabit SFI/SFP+ Network Connection' drv=uio_pci_generic unused=ixgbe\n 0000:82:00.1 '82599EB 10-Gigabit SFI/SFP+ Network Connection' drv=uio_pci_generic unused=ixgbe\n\n Network devices using kernel driver\n ===================================\n 0000:04:00.0 'I350 Gigabit Network Connection' if=em0 drv=igb unused=uio_pci_generic *Active*\n 0000:04:00.1 'I350 Gigabit Network Connection' if=eth1 drv=igb unused=uio_pci_generic\n 0000:04:00.2 'I350 Gigabit Network Connection' if=eth2 drv=igb unused=uio_pci_generic\n 0000:04:00.3 'I350 Gigabit Network Connection' if=eth3 drv=igb unused=uio_pci_generic\n\n Other network devices\n =====================\n \n\nTo bind device eth1, 04:00.1, to the uio_pci_generic driver:\n\n.. code-block:: console\n\n root@host:DPDK# ./tools/dpdk_nic_bind.py --bind=uio_pci_generic 04:00.1\n\nor, alternatively,\n\n.. code-block:: console\n\n root@host:DPDK# ./tools/dpdk_nic_bind.py --bind=uio_pci_generic eth1\n\nTo restore device 82:00.0 to its original kernel binding:\n\n.. code-block:: console\n\n root@host:DPDK# ./tools/dpdk_nic_bind.py --bind=ixgbe 82:00.0\n" }, { "path": "doc/guides/linux_gsg/build_sample_apps.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nCompiling and Running Sample Applications\n=========================================\n\nThe chapter describes how to compile and run applications in an DPDK environment.\nIt also provides a pointer to where sample applications are stored.\n\n.. note::\n\n Parts of this process can also be done using the setup script described in **Chapter 6** of this document.\n\nCompiling a Sample Application\n------------------------------\n\nOnce an DPDK target environment directory has been created (such as x86_64-native-linuxapp-gcc),\nit contains all libraries and header files required to build an application.\n\nWhen compiling an application in the Linux* environment on the DPDK, the following variables must be exported:\n\n* RTE_SDK - Points to the DPDK installation directory.\n\n* RTE_TARGET - Points to the DPDK target environment directory.\n\nThe following is an example of creating the helloworld application, which runs in the DPDK Linux environment.\nThis example may be found in the ${RTE_SDK}/examples directory.\n\nThe directory contains the main.c file. This file, when combined with the libraries in the DPDK target environment,\ncalls the various functions to initialize the DPDK environment,\nthen launches an entry point (dispatch application) for each core to be utilized.\nBy default, the binary is generated in the build directory.\n\n.. code-block:: console\n\n user@host:~/DPDK$ cd examples/helloworld/\n user@host:~/DPDK/examples/helloworld$ export RTE_SDK=$HOME/DPDK\n user@host:~/DPDK/examples/helloworld$ export RTE_TARGET=x86_64-native-linuxapp-gcc\n user@host:~/DPDK/examples/helloworld$ make\n CC main.o\n LD helloworld\n INSTALL-APP helloworld\n INSTALL-MAP helloworld.map\n\n user@host:~/DPDK/examples/helloworld$ ls build/app\n helloworld helloworld.map\n\n.. note::\n\n In the above example, helloworld was in the directory structure of the DPDK.\n However, it could have been located outside the directory structure to keep the DPDK structure intact.\n In the following case, the helloworld application is copied to a new directory as a new starting point.\n\n .. code-block:: console\n\n user@host:~$ export RTE_SDK=/home/user/DPDK\n user@host:~$ cp -r $(RTE_SDK)/examples/helloworld my_rte_app\n user@host:~$ cd my_rte_app/\n user@host:~$ export RTE_TARGET=x86_64-native-linuxapp-gcc\n user@host:~/my_rte_app$ make\n CC main.o\n LD helloworld\n INSTALL-APP helloworld\n INSTALL-MAP helloworld.map\n\nRunning a Sample Application\n----------------------------\n\n.. warning::\n\n The UIO drivers and hugepages must be setup prior to running an application.\n\n.. warning::\n\n Any ports to be used by the application must be already bound to an appropriate kernel\n module, as described in Section 3.5, prior to running the application.\n\nThe application is linked with the DPDK target environment's Environmental Abstraction Layer (EAL) library,\nwhich provides some options that are generic to every DPDK application.\n\nThe following is the list of options that can be given to the EAL:\n\n.. code-block:: console\n\n ./rte-app -c COREMASK -n NUM [-b ] [--socket-mem=MB,...] [-m MB] [-r NUM] [-v] [--file-prefix] [--proc-type ] [-- xen-dom0]\n\nThe EAL options are as follows:\n\n* -c COREMASK: An hexadecimal bit mask of the cores to run on. Note that core numbering can change between platforms and should be determined beforehand.\n\n* -n NUM: Number of memory channels per processor socket\n\n* -b : blacklisting of ports; prevent EAL from using specified PCI device (multiple -b options are allowed)\n\n* --use-device: use the specified Ethernet device(s) only. Use comma-separate <[domain:]bus:devid.func> values. Cannot be used with -b option\n\n* --socket-mem: Memory to allocate from hugepages on specific sockets\n\n* -m MB: Memory to allocate from hugepages, regardless of processor socket. It is recommended that --socket-mem be used instead of this option.\n\n* -r NUM: Number of memory ranks\n\n* -v: Display version information on startup\n\n* --huge-dir: The directory where hugetlbfs is mounted\n\n* --file-prefix: The prefix text used for hugepage filenames\n\n* --proc-type: The type of process instance\n\n* --xen-dom0: Support application running on Xen Domain0 without hugetlbfs\n\n* --vmware-tsc-map: use VMware TSC map instead of native RDTSC\n\n* --base-virtaddr: specify base virtual address\n\n* --vfio-intr: specify interrupt type to be used by VFIO (has no effect if VFIO is not used)\n\nThe -c and the -n options are mandatory; the others are optional.\n\nCopy the DPDK application binary to your target, then run the application as follows\n(assuming the platform has four memory channels per processor socket,\nand that cores 0-3 are present and are to be used for running the application):\n\n.. code-block:: console\n\n user@target:~$ ./helloworld -c f -n 4\n\n.. note::\n\n The --proc-type and --file-prefix EAL options are used for running multiple DPDK processes.\n See the “Multi-process Sample Application” chapter in the *DPDK Sample Applications User Guide* and\n the *DPDK Programmers Guide* for more details.\n\nLogical Core Use by Applications\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe coremask parameter is always mandatory for DPDK applications.\nEach bit of the mask corresponds to the equivalent logical core number as reported by Linux.\nSince these logical core numbers, and their mapping to specific cores on specific NUMA sockets, can vary from platform to platform,\nit is recommended that the core layout for each platform be considered when choosing the coremask to use in each case.\n\nOn initialization of the EAL layer by an DPDK application, the logical cores to be used and their socket location are displayed.\nThis information can also be determined for all cores on the system by examining the /proc/cpuinfo file, for example, by running cat /proc/cpuinfo.\nThe physical id attribute listed for each processor indicates the CPU socket to which it belongs.\nThis can be useful when using other processors to understand the mapping of the logical cores to the sockets.\n\n.. note::\n\n A more graphical view of the logical core layout may be obtained using the lstopo Linux utility.\n On Fedora* Linux, this may be installed and run using the following command:\n\n.. code-block:: console\n\n sudo yum install hwloc\n ./lstopo\n\n.. warning::\n\n The logical core layout can change between different board layouts and should be checked before selecting an application coremask.\n\nHugepage Memory Use by Applications\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nWhen running an application, it is recommended to use the same amount of memory as that allocated for hugepages.\nThis is done automatically by the DPDK application at startup,\nif no -m or --socket-mem parameter is passed to it when run.\n\nIf more memory is requested by explicitly passing a -m or --socket-mem value, the application fails.\nHowever, the application itself can also fail if the user requests less memory than the reserved amount of hugepage-memory, particularly if using the -m option.\nThe reason is as follows.\nSuppose the system has 1024 reserved 2 MB pages in socket 0 and 1024 in socket 1.\nIf the user requests 128 MB of memory, the 64 pages may not match the constraints:\n\n* The hugepage memory by be given to the application by the kernel in socket 1 only.\n In this case, if the application attempts to create an object, such as a ring or memory pool in socket 0, it fails.\n To avoid this issue, it is recommended that the -- socket-mem option be used instead of the -m option.\n\n* These pages can be located anywhere in physical memory, and, although the DPDK EAL will attempt to allocate memory in contiguous blocks,\n it is possible that the pages will not be contiguous. In this case, the application is not able to allocate big memory pools.\n\nThe socket-mem option can be used to request specific amounts of memory for specific sockets.\nThis is accomplished by supplying the --socket-mem flag followed by amounts of memory requested on each socket,\nfor example, supply --socket-mem=0,512 to try and reserve 512 MB for socket 1 only.\nSimilarly, on a four socket system, to allocate 1 GB memory on each of sockets 0 and 2 only, the parameter --socket-mem=1024,0,1024 can be used.\nNo memory will be reserved on any CPU socket that is not explicitly referenced, for example, socket 3 in this case.\nIf the DPDK cannot allocate enough memory on each socket, the EAL initialization fails.\n\nAdditional Sample Applications\n------------------------------\n\nAdditional sample applications are included in the ${RTE_SDK}/examples directory.\nThese sample applications may be built and run in a manner similar to that described in earlier sections in this manual.\nIn addition, see the *DPDK Sample Applications User Guide* for a description of the application,\nspecific instructions on compilation and execution and some explanation of the code.\n\nAdditional Test Applications\n----------------------------\n\nIn addition, there are two other applications that are built when the libraries are created.\nThe source files for these are in the DPDK/app directory and are called test and testpmd.\nOnce the libraries are created, they can be found in the build/app directory.\n\n* The test application provides a variety of specific tests for the various functions in the DPDK.\n\n* The testpmd application provides a number of different packet throughput tests and\n examples of features such as how to use the Flow Director found in the Intel® 82599 10 Gigabit Ethernet Controller.\n" }, { "path": "doc/guides/linux_gsg/enable_func.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Enabling_Additional_Functionality:\n\nEnabling Additional Functionality\n=================================\n\n.. _High_Precision_Event_Timer:\n\nHigh Precision Event Timer HPET) Functionality\n----------------------------------------------\n\nBIOS Support\n~~~~~~~~~~~~\n\nThe High Precision Timer (HPET) must be enabled in the platform BIOS if the HPET is to be used.\nOtherwise, the Time Stamp Counter (TSC) is used by default.\nThe BIOS is typically accessed by pressing F2 while the platform is starting up.\nThe user can then navigate to the HPET option. On the Crystal Forest platform BIOS, the path is:\n**Advanced -> PCH-IO Configuration -> High Precision Timer ->** (Change from Disabled to Enabled if necessary).\n\nOn a system that has already booted, the following command can be issued to check if HPET is enabled:\n\n.. code-block:: console\n\n # grep hpet /proc/timer_list\n\nIf no entries are returned, HPET must be enabled in the BIOS (as per the instructions above) and the system rebooted.\n\nLinux Kernel Support\n~~~~~~~~~~~~~~~~~~~~\n\nThe DPDK makes use of the platform HPET timer by mapping the timer counter into the process address space, and as such,\nrequires that the HPET_MMAP kernel configuration option be enabled.\n\n.. warning::\n\n On Fedora*, and other common distributions such as Ubuntu*, the HPET_MMAP kernel option is not enabled by default.\n To recompile the Linux kernel with this option enabled, please consult the distributions documentation for the relevant instructions.\n\nEnabling HPET in the DPDK\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nBy default, HPET support is disabled in the DPDK build configuration files.\nTo use HPET, the CONFIG_RTE_LIBEAL_USE_HPET setting should be changed to “y”, which will enable the HPET settings at compile time.\n\nFor an application to use the rte_get_hpet_cycles() and rte_get_hpet_hz() API calls,\nand optionally to make the HPET the default time source for the rte_timer library,\nthe new rte_eal_hpet_init() API call should be called at application initialization.\nThis API call will ensure that the HPET is accessible, returning an error to the application if it is not,\nfor example, if HPET_MMAP is not enabled in the kernel.\nThe application can then determine what action to take, if any, if the HPET is not available at run-time.\n\n.. note::\n\n For applications that require timing APIs, but not the HPET timer specifically,\n it is recommended that the rte_get_timer_cycles() and rte_get_timer_hz() API calls be used instead of the HPET-specific APIs.\n These generic APIs can work with either TSC or HPET time sources, depending on what is requested by an application call to rte_eal_hpet_init(),\n if any, and on what is available on the system at runtime.\n\nRunning DPDK Applications Without Root Privileges\n--------------------------------------------------------\n\nAlthough applications using the DPDK use network ports and other hardware resources directly,\nwith a number of small permission adjustments it is possible to run these applications as a user other than “root”.\nTo do so, the ownership, or permissions, on the following Linux file system objects should be adjusted to ensure that\nthe Linux user account being used to run the DPDK application has access to them:\n\n* All directories which serve as hugepage mount points, for example, /mnt/huge\n\n* The userspace-io device files in /dev, for example, /dev/uio0, /dev/uio1, and so on\n\n* The userspace-io sysfs config and resource files, for example for uio0: /sys/class/uio/uio0/device/config /sys/class/uio/uio0/device/resource*\n\n* If the HPET is to be used, /dev/hpet\n\n.. note::\n\n On some Linux installations, /dev/hugepages is also a hugepage mount point created by default.\n\nPower Management and Power Saving Functionality\n-----------------------------------------------\n\nEnhanced Intel SpeedStep® Technology must be enabled in the platform BIOS if the power management feature of DPDK is to be used.\nOtherwise, the sys file folder /sys/devices/system/cpu/cpu0/cpufreq will not exist, and the CPU frequency- based power management cannot be used.\nConsult the relevant BIOS documentation to determine how these settings can be accessed.\n\nFor example, on some Intel reference platform BIOS variants, the path to Enhanced Intel SpeedStep® Technology is:\n\n**Advanced->Processor Configuration->Enhanced Intel SpeedStep® Tech**\n\nIn addition, C3 and C6 should be enabled as well for power management. The path of C3 and C6 on the same platform BIOS is:\n\n**Advanced->Processor Configuration->Processor C3 Advanced->Processor Configuration-> Processor C6**\n\nUsing Linux* Core Isolation to Reduce Context Switches\n------------------------------------------------------\n\nWhile the threads used by an DPDK application are pinned to logical cores on the system,\nit is possible for the Linux scheduler to run other tasks on those cores also.\nTo help prevent additional workloads from running on those cores,\nit is possible to use the isolcpus Linux* kernel parameter to isolate them from the general Linux scheduler.\n\nFor example, if DPDK applications are to run on logical cores 2, 4 and 6,\nthe following should be added to the kernel parameter list:\n\n.. code-block:: console\n\n isolcpus=2,4,6\n\nLoading the DPDK KNI Kernel Module\n-----------------------------------------\n\nTo run the DPDK Kernel NIC Interface (KNI) sample application, an extra kernel module (the kni module) must be loaded into the running kernel.\nThe module is found in the kmod sub-directory of the DPDK target directory.\nSimilar to the loading of the igb_uio module, this module should be loaded using the insmod command as shown below\n(assuming that the current directory is the DPDK target directory):\n\n.. code-block:: console\n\n #insmod kmod/rte_kni.ko\n\n.. note::\n\n See the “Kernel NIC Interface Sample Application” chapter in the *DPDK Sample Applications User Guide* for more details.\n\nUsing Linux IOMMU Pass-Through to Run DPDK with Intel® VT-d\n-----------------------------------------------------------\n\nTo enable Intel® VT-d in a Linux kernel, a number of kernel configuration options must be set. These include:\n\n* IOMMU_SUPPORT\n\n* IOMMU_API\n\n* INTEL_IOMMU\n\nIn addition, to run the DPDK with Intel® VT-d, the iommu=pt kernel parameter must be used when using igb_uio driver.\nThis results in pass-through of the DMAR (DMA Remapping) lookup in the host.\nAlso, if INTEL_IOMMU_DEFAULT_ON is not set in the kernel, the intel_iommu=on kernel parameter must be used too.\nThis ensures that the Intel IOMMU is being initialized as expected.\n\nPlease note that while using iommu=pt is compulsory for igb_uio driver, the vfio-pci driver can actually work with both iommu=pt and iommu=on.\n\nHigh Performance of Small Packets on 40G NIC\n--------------------------------------------\n\nAs there might be firmware fixes for performance enhancement in latest version\nof firmware image, the firmware update might be needed for getting high performance.\nCheck with the local Intel's Network Division application engineers for firmware updates.\nThe base driver to support firmware version of FVL3E will be integrated in the next\nDPDK release, so currently the validated firmware version is 4.2.6.\n\nEnabling Extended Tag and Setting Max Read Request Size\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nPCI configurations of extended_tag and max _read_requ st_size have big impacts on performance of small packets on 40G NIC.\nEnabling extended_tag and setting max _read_requ st_size to small size such as 128 bytes provide great helps to high performance of small packets.\n\n* These can be done in some BIOS implementations.\n\n* For other BIOS implementations, PCI configurations can be changed by using command of setpci, or special configurations in DPDK config file of common_linux.\n\n * Bits 7:5 at address of 0xA8 of each PCI device is used for setting the max_read_request_size,\n and bit 8 of 0xA8 of each PCI device is used for enabling/disabling the extended_tag.\n lspci and setpci can be used to read the values of 0xA8 and then write it back after being changed.\n\n * In config file of common_linux, below three configurations can be changed for the same purpose.\n\n CONFIG_RTE_PCI_CONFIG\n\n CONFIG_RTE_PCI_EXTENDED_TAG\n\n CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE\n\nUse 16 Bytes RX Descriptor Size\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nAs i40e PMD supports both 16 and 32 bytes RX descriptor sizes, and 16 bytes size can provide helps to high performance of small packets.\nConfiguration of CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC in config files can be changed to use 16 bytes size RX descriptors.\n\nHigh Performance and per Packet Latency Tradeoff\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nDue to the hardware design, the interrupt signal inside NIC is needed for per\npacket descriptor write-back. The minimum interval of interrupts could be set\nat compile time by CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL in configuration files.\nThough there is a default configuration, the interval could be tuned by the\nusers with that configuration item depends on what the user cares about more,\nperformance or per packet latency.\n" }, { "path": "doc/guides/linux_gsg/index.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _linux_gsg:\n\nGetting Started Guide for Linux\n===============================\n\n|today|\n\nContents\n\n.. toctree::\n :maxdepth: 2\n :numbered:\n\n intro\n sys_reqs\n build_dpdk\n build_sample_apps\n enable_func\n quick_start\n" }, { "path": "doc/guides/linux_gsg/intro.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIntroduction\n============\n\nThis document contains instructions for installing and configuring the Intel® Data Plane Development Kit (DPDK) software.\nIt is designed to get customers up and running quickly.\nThe document describes how to compile and run a DPDK application in a Linux* application (linuxapp) environment,\nwithout going deeply into detail.\n\nDocumentation Roadmap\n---------------------\n\nThe following is a list of DPDK documents in the suggested reading order:\n\n* Release Notes: Provides release-specific information, including supported features, limitations, fixed issues, known issues and so on.\n Also, provides the answers to frequently asked questions in FAQ format.\n\n* Getting Started Guide (this document): Describes how to install and configure the DPDK; designed to get users up and running quickly with the software.\n\n* Programmer's Guide: Describes:\n\n * The software architecture and how to use it (through examples), specifically in a Linux* application (linuxapp) environment\n\n * The content of the DPDK, the build system (including the commands that can be used in the root DPDK Makefile to build the development kit and\n an application) and guidelines for porting an application\n\n * Optimizations used in the software and those that should be considered for new development\n\n A glossary of terms is also provided.\n\n* API Reference: Provides detailed information about DPDK functions, data structures and other programming constructs.\n\n* Sample Applications User Guide: Describes a set of sample applications.\n Each chapter describes a sample application that showcases specific functionality and provides instructions on how to compile, run and use the sample application.\n\n.. note::\n\n These documents are available for download as a separate documentation package at the same location as the DPDK code package.\n" }, { "path": "doc/guides/linux_gsg/quick_start.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nQuick Start Setup Script\n========================\n\nThe setup.sh script, found in the tools subdirectory, allows the user to perform the following tasks:\n\n* Build the DPDK libraries\n\n* Insert and remove the DPDK IGB_UIO kernel module\n\n* Insert and remove VFIO kernel modules\n\n* Insert and remove the DPDK KNI kernel module\n\n* Create and delete hugepages for NUMA and non-NUMA cases\n\n* View network port status and reserve ports for DPDK application use\n\n* Set up permissions for using VFIO as a non-privileged user\n\n* Run the test and testpmd applications\n\n* Look at hugepages in the meminfo\n\n* List hugepages in /mnt/huge\n\n* Remove built DPDK libraries\n\nOnce these steps have been completed for one of the EAL targets,\nthe user may compile their own application that links in the EAL libraries to create the DPDK image.\n\nScript Organization\n-------------------\n\nThe setup.sh script is logically organized into a series of steps that a user performs in sequence.\nEach step provides a number of options that guide the user to completing the desired task.\nThe following is a brief synopsis of each step.\n\n**Step 1: Build DPDK Libraries**\n\nInitially, the user must select a DPDK target to choose the correct target type and compiler options to use when building the libraries.\n\nThe user must have all libraries, modules, updates and compilers installed in the system prior to this,\nas described in the earlier chapters in this Getting Started Guide.\n\n**Step 2: Setup Environment**\n\nThe user configures the Linux* environment to support the running of DPDK applications.\nHugepages can be set up for NUMA or non-NUMA systems. Any existing hugepages will be removed.\nThe DPDK kernel module that is needed can also be inserted in this step,\nand network ports may be bound to this module for DPDK application use.\n\n**Step 3: Run an Application**\n\nThe user may run the test application once the other steps have been performed.\nThe test application allows the user to run a series of functional tests for the DPDK.\nThe testpmd application, which supports the receiving and sending of packets, can also be run.\n\n**Step 4: Examining the System**\n\nThis step provides some tools for examining the status of hugepage mappings.\n\n**Step 5: System Cleanup**\n\nThe final step has options for restoring the system to its original state.\n\nUse Cases\n---------\n\nThe following are some example of how to use the setup.sh script.\nThe script should be run using the source command.\nSome options in the script prompt the user for further data before proceeding.\n\n.. warning::\n\n The setup.sh script should be run with root privileges.\n\n.. code-block:: console\n\n user@host:~/rte$ source tools/setup.sh\n\n ------------------------------------------------------------------------\n\n RTE_SDK exported as /home/user/rte\n\n ------------------------------------------------------------------------\n\n Step 1: Select the DPDK environment to build\n\n ------------------------------------------------------------------------\n\n [1] i686-native-linuxapp-gcc\n\n [2] i686-native-linuxapp-icc\n\n [3] ppc_64-power8-linuxapp-gcc\n\n [4] x86_64-ivshmem-linuxapp-gcc\n\n [5] x86_64-ivshmem-linuxapp-icc\n\n [6] x86_64-native-bsdapp-clang\n\n [7] x86_64-native-bsdapp-gcc\n\n [8] x86_64-native-linuxapp-clang\n\n [9] x86_64-native-linuxapp-gcc\n\n [10] x86_64-native-linuxapp-icc\n\n ------------------------------------------------------------------------\n\n Step 2: Setup linuxapp environment\n\n ------------------------------------------------------------------------\n\n [11] Insert IGB UIO module\n\n [12] Insert VFIO module\n\n [13] Insert KNI module\n\n [14] Setup hugepage mappings for non-NUMA systems\n\n [15] Setup hugepage mappings for NUMA systems\n\n [16] Display current Ethernet device settings\n\n [17] Bind Ethernet device to IGB UIO module\n\n [18] Bind Ethernet device to VFIO module\n\n [19] Setup VFIO permissions\n\n ------------------------------------------------------------------------\n\n Step 3: Run test application for linuxapp environment\n\n ------------------------------------------------------------------------\n\n [20] Run test application ($RTE_TARGET/app/test)\n\n [21] Run testpmd application in interactive mode ($RTE_TARGET/app/testpmd)\n\n ------------------------------------------------------------------------\n\n Step 4: Other tools\n\n ------------------------------------------------------------------------\n\n [22] List hugepage info from /proc/meminfo\n\n ------------------------------------------------------------------------\n\n Step 5: Uninstall and system cleanup\n\n ------------------------------------------------------------------------\n\n [23] Uninstall all targets\n\n [24] Unbind NICs from IGB UIO driver\n\n [25] Remove IGB UIO module\n\n [26] Remove VFIO module\n\n [27] Remove KNI module\n\n [28] Remove hugepage mappings\n\n [29] Exit Script\n\nOption:\n\nThe following selection demonstrates the creation of the x86_64-native-linuxapp-gcc DPDK library.\n\n.. code-block:: console\n\n Option: 9\n\n ================== Installing x86_64-native-linuxapp-gcc\n\n Configuration done\n == Build lib\n ...\n Build complete\n RTE_TARGET exported as x86_64-native -linuxapp-gcc\n\nThe following selection demonstrates the starting of the DPDK UIO driver.\n\n.. code-block:: console\n\n Option: 25\n\n Unloading any existing DPDK UIO module\n Loading DPDK UIO module\n\nThe following selection demonstrates the creation of hugepages in a NUMA system.\n1024 2 MByte pages are assigned to each node.\nThe result is that the application should use -m 4096 for starting the application to access both memory areas\n(this is done automatically if the -m option is not provided).\n\n.. note::\n\n If prompts are displayed to remove temporary files, type 'y'.\n\n.. code-block:: console\n\n Option: 15\n\n Removing currently reserved hugepages\n mounting /mnt/huge and removing directory\n Input the number of 2MB pages for each node\n Example: to have 128MB of hugepages available per node,\n enter '64' to reserve 64 * 2MB pages on each node\n Number of pages for node0: 1024\n Number of pages for node1: 1024\n Reserving hugepages\n Creating /mnt/huge and mounting as hugetlbfs\n\nThe following selection demonstrates the launch of the test application to run on a single core.\n\n.. code-block:: console\n\n Option: 20\n\n Enter hex bitmask of cores to execute test app on\n Example: to execute app on cores 0 to 7, enter 0xff\n bitmask: 0x01\n Launching app\n EAL: coremask set to 1\n EAL: Detected lcore 0 on socket 0\n ...\n EAL: Master core 0 is ready (tid=1b2ad720)\n RTE>>\n\nApplications\n------------\n\nOnce the user has run the setup.sh script, built one of the EAL targets and set up hugepages (if using one of the Linux EAL targets),\nthe user can then move on to building and running their application or one of the examples provided.\n\nThe examples in the /examples directory provide a good starting point to gain an understanding of the operation of the DPDK.\nThe following command sequence shows how the helloworld sample application is built and run.\nAs recommended in Section 4.2.1 , \"Logical Core Use by Applications\",\nthe logical core layout of the platform should be determined when selecting a core mask to use for an application.\n\n.. code-block:: console\n\n rte@rte-desktop:~/rte/examples$ cd helloworld/\n rte@rte-desktop:~/rte/examples/helloworld$ make\n CC main.o\n LD helloworld\n INSTALL-APP helloworld\n INSTALL-MAP helloworld.map\n\n rte@rte-desktop:~/rte/examples/helloworld$ sudo ./build/app/helloworld -c 0xf -n 3\n [sudo] password for rte:\n EAL: coremask set to f\n EAL: Detected lcore 0 as core 0 on socket 0\n EAL: Detected lcore 1 as core 0 on socket 1\n EAL: Detected lcore 2 as core 1 on socket 0\n EAL: Detected lcore 3 as core 1 on socket 1\n EAL: Setting up hugepage memory...\n EAL: Ask a virtual area of 0x200000 bytes\n EAL: Virtual area found at 0x7f0add800000 (size = 0x200000)\n EAL: Ask a virtual area of 0x3d400000 bytes\n EAL: Virtual area found at 0x7f0aa0200000 (size = 0x3d400000)\n EAL: Ask a virtual area of 0x400000 bytes\n EAL: Virtual area found at 0x7f0a9fc00000 (size = 0x400000)\n EAL: Ask a virtual area of 0x400000 bytes\n EAL: Virtual area found at 0x7f0a9f600000 (size = 0x400000)\n EAL: Ask a virtual area of 0x400000 bytes\n EAL: Virtual area found at 0x7f0a9f000000 (size = 0x400000)\n EAL: Ask a virtual area of 0x800000 bytes\n EAL: Virtual area found at 0x7f0a9e600000 (size = 0x800000)\n EAL: Ask a virtual area of 0x800000 bytes\n EAL: Virtual area found at 0x7f0a9dc00000 (size = 0x800000)\n EAL: Ask a virtual area of 0x400000 bytes\n EAL: Virtual area found at 0x7f0a9d600000 (size = 0x400000)\n EAL: Ask a virtual area of 0x400000 bytes\n EAL: Virtual area found at 0x7f0a9d000000 (size = 0x400000)\n EAL: Ask a virtual area of 0x400000 bytes\n EAL: Virtual area found at 0x7f0a9ca00000 (size = 0x400000)\n EAL: Ask a virtual area of 0x200000 bytes\n EAL: Virtual area found at 0x7f0a9c600000 (size = 0x200000)\n EAL: Ask a virtual area of 0x200000 bytes\n EAL: Virtual area found at 0x7f0a9c200000 (size = 0x200000)\n EAL: Ask a virtual area of 0x3fc00000 bytes\n EAL: Virtual area found at 0x7f0a5c400000 (size = 0x3fc00000)\n EAL: Ask a virtual area of 0x200000 bytes\n EAL: Virtual area found at 0x7f0a5c000000 (size = 0x200000)\n EAL: Requesting 1024 pages of size 2MB from socket 0\n EAL: Requesting 1024 pages of size 2MB from socket 1\n EAL: Master core 0 is ready (tid=de25b700)\n EAL: Core 1 is ready (tid=5b7fe700)\n EAL: Core 3 is ready (tid=5a7fc700)\n EAL: Core 2 is ready (tid=5affd700)\n hello from core 1\n hello from core 2\n hello from core 3\n hello from core 0\n" }, { "path": "doc/guides/linux_gsg/sys_reqs.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nSystem Requirements\n===================\n\nThis chapter describes the packages required to compile the DPDK.\n\n.. note::\n\n If the DPDK is being used on an Intel® Communications Chipset 89xx Series platform,\n please consult the *Intel® Communications Chipset 89xx Series Software for Linux* Getting Started Guide*.\n\nBIOS Setting Prerequisite on x86\n--------------------------------\n\nFor the majority of platforms, no special BIOS settings are needed to use basic DPDK functionality.\nHowever, for additional HPET timer and power management functionality,\nand high performance of small packets on 40G NIC, BIOS setting changes may be needed.\nConsult :ref:`Chapter 5. Enabling Additional Functionality `\nfor more information on the required changes.\n\nCompilation of the DPDK\n-----------------------\n\n**Required Tools:**\n\n.. note::\n\n Testing has been performed using Fedora* 18. The setup commands and installed packages needed on other systems may be different.\n For details on other Linux distributions and the versions tested, please consult the DPDK Release Notes.\n\n* GNU make\n\n* coreutils: cmp, sed, grep, arch\n\n* gcc: versions 4.5.x or later is recommended for i686/x86_64. versions 4.8.x or later is recommended\n for ppc_64 and x86_x32 ABI. On some distributions, some specific compiler flags and linker flags are enabled by\n default and affect performance (- fstack-protector, for example). Please refer to the documentation\n of your distribution and to gcc -dumpspecs.\n\n* libc headers (glibc-devel.i686 / libc6-dev-i386; glibc-devel.x86_64 for 64-bit compilation on Intel\n architecture; glibc-devel.ppc64 for 64 bit IBM Power architecture;)\n\n* Linux kernel headers or sources required to build kernel modules. (kernel - devel.x86_64;\n kernel - devel.ppc64)\n\n* Additional packages required for 32-bit compilation on 64-bit systems are:\n\n glibc.i686, libgcc.i686, libstdc++.i686 and glibc-devel.i686 for Intel i686/x86_64;\n\n glibc.ppc64, libgcc.ppc64, libstdc++.ppc64 and glibc-devel.ppc64 for IBM ppc_64;\n\n.. note::\n\n x86_x32 ABI is currently supported with distribution packages only on Ubuntu\n higher than 13.10 or recent Debian distribution. The only supported compiler is gcc 4.8+.\n\n.. note::\n\n Python, version 2.6 or 2.7, to use various helper scripts included in the DPDK package\n\n\n**Optional Tools:**\n\n* Intel® C++ Compiler (icc). For installation, additional libraries may be required.\n See the icc Installation Guide found in the Documentation directory under the compiler installation.\n This release has been tested using version 12.1.\n\n* IBM® Advance ToolChain for Powerlinux. This is a set of open source development tools and runtime libraries\n which allows users to take leading edge advantage of IBM's latest POWER hardware features on Linux. To install\n it, see the IBM official installation document.\n\n* libpcap headers and libraries (libpcap-devel) to compile and use the libpcap-based poll-mode driver.\n This driver is disabled by default and can be enabled by setting CONFIG_RTE_LIBRTE_PMD_PCAP=y in the build time config file.\n\nRunning DPDK Applications\n-------------------------\n\nTo run an DPDK application, some customization may be required on the target machine.\n\nSystem Software\n~~~~~~~~~~~~~~~\n\n**Required:**\n\n* Kernel version >= 2.6.33\n\n The kernel version in use can be checked using the command:\n\n .. code-block:: console\n\n uname -r\n\nFor details of the patches needed to use the DPDK with earlier kernel versions,\nsee the DPDK FAQ included in the *DPDK Release Notes*.\nNote also that Red hat* Linux* 6.2 and 6.3 uses a 2.6.32 kernel that already has all the necessary patches applied.\n\n* glibc >= 2.7 (for features related to cpuset)\n\n The version can be checked using the ldd --version command. A sample output is shown below:\n\n .. code-block:: console\n\n # ldd --version\n\n ldd (GNU libc) 2.14.90\n Copyright (C) 2011 Free Software Foundation, Inc.\n This is free software; see the source for copying conditions. There is NO\n warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\n Written by Roland McGrath and Ulrich Drepper.\n\n* Kernel configuration\n\n In the Fedora* OS and other common distributions, such as Ubuntu*, or Red Hat Enterprise Linux*,\n the vendor supplied kernel configurations can be used to run most DPDK applications.\n\n For other kernel builds, options which should be enabled for DPDK include:\n\n * UIO support\n\n * HUGETLBFS\n\n * PROC_PAGE_MONITOR support\n\n * HPET and HPET_MMAP configuration options should also be enabled if HPET support is required.\n See :ref:`Section 5.1 High Precision Event Timer (HPET) Functionality ` for more details.\n\nUse of Hugepages in the Linux* Environment\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nHugepage support is required for the large memory pool allocation used for packet buffers\n(the HUGETLBFS option must be enabled in the running kernel as indicated in Section 2.3).\nBy using hugepage allocations, performance is increased since fewer pages are needed,\nand therefore less Translation Lookaside Buffers (TLBs, high speed translation caches),\nwhich reduce the time it takes to translate a virtual page address to a physical page address.\nWithout hugepages, high TLB miss rates would occur with the standard 4k page size, slowing performance.\n\nReserving Hugepages for DPDK Use\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe allocation of hugepages should be done at boot time or as soon as possible after system boot\nto prevent memory from being fragmented in physical memory.\nTo reserve hugepages at boot time, a parameter is passed to the Linux* kernel on the kernel command line.\n\nFor 2 MB pages, just pass the hugepages option to the kernel. For example, to reserve 1024 pages of 2 MB, use:\n\n.. code-block:: console\n\n hugepages=1024\n\nFor other hugepage sizes, for example 1G pages, the size must be specified explicitly and\ncan also be optionally set as the default hugepage size for the system.\nFor example, to reserve 4G of hugepage memory in the form of four 1G pages, the following options should be passed to the kernel:\n\n.. code-block:: console\n\n default_hugepagesz=1G hugepagesz=1G hugepages=4\n\n.. note::\n\n The hugepage sizes that a CPU supports can be determined from the CPU flags on Intel architecture.\n If pse exists, 2M hugepages are supported; if pdpe1gb exists, 1G hugepages are supported.\n On IBM Power architecture, the supported hugepage sizes are 16MB and 16GB.\n\n.. note::\n\n For 64-bit applications, it is recommended to use 1 GB hugepages if the platform supports them.\n\nIn the case of a dual-socket NUMA system,\nthe number of hugepages reserved at boot time is generally divided equally between the two sockets\n(on the assumption that sufficient memory is present on both sockets).\n\nSee the Documentation/kernel-parameters.txt file in your Linux* source tree for further details of these and other kernel options.\n\n**Alternative:**\n\nFor 2 MB pages, there is also the option of allocating hugepages after the system has booted.\nThis is done by echoing the number of hugepages required to a nr_hugepages file in the /sys/devices/ directory.\nFor a single-node system, the command to use is as follows (assuming that 1024 pages are required):\n\n.. code-block:: console\n\n echo 1024 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages\n\nOn a NUMA machine, pages should be allocated explicitly on separate nodes:\n\n.. code-block:: console\n\n echo 1024 > /sys/devices/system/node/node0/hugepages/hugepages-2048kB/nr_hugepages\n echo 1024 > /sys/devices/system/node/node1/hugepages/hugepages-2048kB/nr_hugepages\n\n.. note::\n\n For 1G pages, it is not possible to reserve the hugepage memory after the system has booted.\n\nUsing Hugepages with the DPDK\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nOnce the hugepage memory is reserved, to make the memory available for DPDK use, perform the following steps:\n\n.. code-block:: console\n\n mkdir /mnt/huge\n mount -t hugetlbfs nodev /mnt/huge\n\nThe mount point can be made permanent across reboots, by adding the following line to the /etc/fstab file:\n\n.. code-block:: console\n\n nodev /mnt/huge hugetlbfs defaults 0 0\n\nFor 1GB pages, the page size must be specified as a mount option:\n\n.. code-block:: console\n\n nodev /mnt/huge_1GB hugetlbfs pagesize=1GB 0 0\n\nXen Domain0 Support in the Linux* Environment\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe existing memory management implementation is based on the Linux* kernel hugepage mechanism.\nOn the Xen hypervisor, hugepage support for DomainU (DomU) Guests means that DPDK applications work as normal for guests.\n\nHowever, Domain0 (Dom0) does not support hugepages.\nTo work around this limitation, a new kernel module rte_dom0_mm is added to facilitate the allocation and mapping of memory via\n**IOCTL** (allocation) and **MMAP** (mapping).\n\nEnabling Xen Dom0 Mode in the DPDK\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nBy default, Xen Dom0 mode is disabled in the DPDK build configuration files.\nTo support Xen Dom0, the CONFIG_RTE_LIBRTE_XEN_DOM0 setting should be changed to “y”, which enables the Xen Dom0 mode at compile time.\n\nFurthermore, the CONFIG_RTE_EAL_ALLOW_INV_SOCKET_ID setting should also be changed to “y” in the case of the wrong socket ID being received.\n\nLoading the DPDK rte_dom0_mm Module\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nTo run any DPDK application on Xen Dom0, the rte_dom0_mm module must be loaded into the running kernel with rsv_memsize option.\nThe module is found in the kmod sub-directory of the DPDK target directory.\nThis module should be loaded using the insmod command as shown below (assuming that the current directory is the DPDK target directory):\n\n.. code-block:: console\n\n sudo insmod kmod/rte_dom0_mm.ko rsv_memsize=X\n\nThe value X cannot be greater than 4096(MB).\n\nConfiguring Memory for DPDK Use\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nAfter the rte_dom0_mm.ko kernel module has been loaded, the user must configure the memory size for DPDK usage.\nThis is done by echoing the memory size to a memsize file in the /sys/devices/ directory.\nUse the following command (assuming that 2048 MB is required):\n\n.. code-block:: console\n\n echo 2048 > /sys/kernel/mm/dom0-mm/memsize-mB/memsize\n\nThe user can also check how much memory has already been used:\n\n.. code-block:: console\n\n cat /sys/kernel/mm/dom0-mm/memsize-mB/memsize_rsvd\n\nXen Domain0 does not support NUMA configuration, as a result the --socket-mem command line option is invalid for Xen Domain0.\n\n.. note::\n\n The memsize value cannot be greater than the rsv_memsize value.\n\nRunning the DPDK Application on Xen Domain0\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nTo run the DPDK application on Xen Domain0, an extra command line option --xen-dom0 is required.\n" }, { "path": "doc/guides/nics/cxgbe.rst", "content": ".. BSD LICENSE\n Copyright 2015 Chelsio Communications.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Chelsio Communications nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nCXGBE Poll Mode Driver\n======================\n\nThe CXGBE PMD (**librte_pmd_cxgbe**) provides poll mode driver support\nfor **Chelsio T5** 10/40 Gbps family of adapters. CXGBE PMD has support\nfor the latest Linux and FreeBSD operating systems.\n\nMore information can be found at `Chelsio Communications Official Website\n`_.\n\nFeatures\n--------\n\nCXGBE PMD has support for:\n\n- Multiple queues for TX and RX\n- Receiver Side Steering (RSS)\n- VLAN filtering\n- Checksum offload\n- Promiscuous mode\n- All multicast mode\n- Port hardware statistics\n\nLimitations\n-----------\n\nThe Chelsio T5 devices provide two/four ports but expose a single PCI bus\naddress, thus, librte_pmd_cxgbe registers itself as a\nPCI driver that allocates one Ethernet device per detected port.\n\nFor this reason, one cannot whitelist/blacklist a single port without\nwhitelisting/blacklisting the other ports on the same device.\n\nSupported Chelsio T5 NICs\n-------------------------\n\n- 1G NICs: T502-BT\n- 10G NICs: T520-BT, T520-CR, T520-LL-CR, T520-SO-CR, T540-CR\n- 40G NICs: T580-CR, T580-LP-CR, T580-SO-CR\n- Other T5 NICs: T522-CR\n\nPrerequisites\n-------------\n\n- Requires firmware version **1.13.32.0** and higher. Visit\n `Chelsio Download Center `_ to get latest firmware\n bundled with the latest Chelsio Unified Wire package.\n\n For Linux, installing and loading the latest cxgb4 kernel driver from the\n Chelsio Unified Wire package should get you the latest firmware. More\n information can be obtained from the User Guide that is bundled with the\n Chelsio Unified Wire package.\n\n For FreeBSD, the latest firmware obtained from the Chelsio Unified Wire\n package must be manually flashed via cxgbetool available in FreeBSD source\n repository.\n\n Instructions on how to manually flash the firmware are given in section\n :ref:`linux-installation` for Linux and section :ref:`freebsd-installation`\n for FreeBSD.\n\nPre-Installation Configuration\n------------------------------\n\nConfig File Options\n~~~~~~~~~~~~~~~~~~~\n\nThe following options can be modified in the ``.config`` file. Please note that\nenabling debugging options may affect system performance.\n\n- ``CONFIG_RTE_LIBRTE_CXGBE_PMD`` (default **y**)\n\n Toggle compilation of librte_pmd_cxgbe driver.\n\n- ``CONFIG_RTE_LIBRTE_CXGBE_DEBUG`` (default **n**)\n\n Toggle display of generic debugging messages.\n\n- ``CONFIG_RTE_LIBRTE_CXGBE_DEBUG_REG`` (default **n**)\n\n Toggle display of registers related run-time check messages.\n\n- ``CONFIG_RTE_LIBRTE_CXGBE_DEBUG_MBOX`` (default **n**)\n\n Toggle display of firmware mailbox related run-time check messages.\n\n- ``CONFIG_RTE_LIBRTE_CXGBE_DEBUG_TX`` (default **n**)\n\n Toggle display of transmission data path run-time check messages.\n\n- ``CONFIG_RTE_LIBRTE_CXGBE_DEBUG_RX`` (default **n**)\n\n Toggle display of receiving data path run-time check messages.\n\n.. _driver-compilation:\n\nDriver Compilation\n~~~~~~~~~~~~~~~~~~\n\nTo compile CXGBE PMD for Linux x86_64 gcc target, run the following \"make\"\ncommand:\n\n.. code-block:: console\n\n cd \n make config T=x86_64-native-linuxapp-gcc install\n\nTo compile CXGBE PMD for FreeBSD x86_64 clang target, run the following \"gmake\"\ncommand:\n\n.. code-block:: console\n\n cd \n gmake config T=x86_64-native-bsdapp-clang install\n\nLinux\n-----\n\n.. _linux-installation:\n\nLinux Installation\n~~~~~~~~~~~~~~~~~~\n\nSteps to manually install the latest firmware from the downloaded Chelsio\nUnified Wire package for Linux operating system are as follows:\n\n#. Load the kernel module:\n\n .. code-block:: console\n\n modprobe cxgb4\n\n#. Use ifconfig to get the interface name assigned to Chelsio card:\n\n .. code-block:: console\n\n ifconfig -a | grep \"00:07:43\"\n\n Example output:\n\n .. code-block:: console\n\n p1p1 Link encap:Ethernet HWaddr 00:07:43:2D:EA:C0\n p1p2 Link encap:Ethernet HWaddr 00:07:43:2D:EA:C8\n\n#. Install cxgbtool:\n\n .. code-block:: console\n\n cd /tools/cxgbtool\n make install\n\n#. Use cxgbtool to load the firmware config file onto the card:\n\n .. code-block:: console\n\n cxgbtool p1p1 loadcfg /src/network/firmware/t5-config.txt\n\n#. Use cxgbtool to load the firmware image onto the card:\n\n .. code-block:: console\n\n cxgbtool p1p1 loadfw /src/network/firmware/t5fw-*.bin\n\n#. Unload and reload the kernel module:\n\n .. code-block:: console\n\n modprobe -r cxgb4\n modprobe cxgb4\n\n#. Verify with ethtool:\n\n .. code-block:: console\n\n ethtool -i p1p1 | grep \"firmware\"\n\n Example output:\n\n .. code-block:: console\n\n firmware-version: 1.13.32.0, TP 0.1.4.8\n\nSample Application Notes\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nThis section demonstrates how to launch **testpmd** with Chelsio T5\ndevices managed by librte_pmd_cxgbe in Linux operating system.\n\n#. Change to DPDK source directory where the target has been compiled in\n section :ref:`driver-compilation`:\n\n .. code-block:: console\n\n cd \n\n#. Load the kernel module:\n\n .. code-block:: console\n\n modprobe cxgb4\n\n#. Get the PCI bus addresses of the interfaces bound to cxgb4 driver:\n\n .. code-block:: console\n\n dmesg | tail -2\n\n Example output:\n\n .. code-block:: console\n\n cxgb4 0000:02:00.4 p1p1: renamed from eth0\n cxgb4 0000:02:00.4 p1p2: renamed from eth1\n\n .. note::\n\n Both the interfaces of a Chelsio T5 2-port adapter are bound to the\n same PCI bus address.\n\n#. Unload the kernel module:\n\n .. code-block:: console\n\n modprobe -ar cxgb4 csiostor\n\n#. Request huge pages:\n\n .. code-block:: console\n\n echo 1024 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages/nr_hugepages\n\n#. Load igb_uio or vfio-pci driver:\n\n .. code-block:: console\n\n insmod ./x86_64-native-linuxapp-gcc/kmod/igb_uio.ko\n\n or\n\n .. code-block:: console\n\n modprobe vfio-pci\n\n#. Bind the Chelsio T5 adapters to igb_uio or vfio-pci loaded in the previous\n step:\n\n .. code-block:: console\n\n ./tools/dpdk_nic_bind.py --bind igb_uio 0000:02:00.4\n\n or\n\n Setup VFIO permissions for regular users and then bind to vfio-pci:\n\n .. code-block:: console\n\n sudo chmod a+x /dev/vfio\n\n sudo chmod 0666 /dev/vfio/*\n\n ./tools/dpdk_nic_bind.py --bind vfio-pci 0000:02:00.4\n\n .. note::\n\n Currently, CXGBE PMD only supports the binding of PF4 for Chelsio T5 NICs.\n\n#. Start testpmd with basic parameters:\n\n .. code-block:: console\n\n ./x86_64-native-linuxapp-gcc/app/testpmd -c 0xf -n 4 -w 0000:02:00.4 -- -i\n\n Example output:\n\n .. code-block:: console\n\n [...]\n EAL: PCI device 0000:02:00.4 on NUMA socket -1\n EAL: probe driver: 1425:5401 rte_cxgbe_pmd\n EAL: PCI memory mapped at 0x7fd7c0200000\n EAL: PCI memory mapped at 0x7fd77cdfd000\n EAL: PCI memory mapped at 0x7fd7c10b7000\n PMD: rte_cxgbe_pmd: fw: 1.13.32.0, TP: 0.1.4.8\n PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter\n Interactive-mode selected\n Configuring Port 0 (socket 0)\n Port 0: 00:07:43:2D:EA:C0\n Configuring Port 1 (socket 0)\n Port 1: 00:07:43:2D:EA:C8\n Checking link statuses...\n PMD: rte_cxgbe_pmd: Port0: passive DA port module inserted\n PMD: rte_cxgbe_pmd: Port1: passive DA port module inserted\n Port 0 Link Up - speed 10000 Mbps - full-duplex\n Port 1 Link Up - speed 10000 Mbps - full-duplex\n Done\n testpmd>\n\n.. note::\n\n Flow control pause TX/RX is disabled by default and can be enabled via\n testpmd as follows:\n\n .. code-block:: console\n\n testpmd> set flow_ctrl rx on tx on 0 0 0 0 mac_ctrl_frame_fwd off autoneg on 0\n testpmd> set flow_ctrl rx on tx on 0 0 0 0 mac_ctrl_frame_fwd off autoneg on 1\n\n To disable again, use:\n\n .. code-block:: console\n\n testpmd> set flow_ctrl rx off tx off 0 0 0 0 mac_ctrl_frame_fwd off autoneg off 0\n testpmd> set flow_ctrl rx off tx off 0 0 0 0 mac_ctrl_frame_fwd off autoneg off 1\n\nFreeBSD\n-------\n\n.. _freebsd-installation:\n\nFreeBSD Installation\n~~~~~~~~~~~~~~~~~~~~\n\nSteps to manually install the latest firmware from the downloaded Chelsio\nUnified Wire package for FreeBSD operating system are as follows:\n\n#. Load the kernel module:\n\n .. code-block:: console\n\n kldload if_cxgbe\n\n#. Use dmesg to get the t5nex instance assigned to the Chelsio card:\n\n .. code-block:: console\n\n dmesg | grep \"t5nex\"\n\n Example output:\n\n .. code-block:: console\n\n t5nex0: irq 16 at device 0.4 on pci2\n cxl0: on t5nex0\n cxl1: on t5nex0\n t5nex0: PCIe x8, 2 ports, 14 MSI-X interrupts, 31 eq, 13 iq\n\n In the example above, a Chelsio T520-CR card is bound to a t5nex0 instance.\n\n#. Install cxgbetool from FreeBSD source repository:\n\n .. code-block:: console\n\n cd /tools/tools/cxgbetool/\n make && make install\n\n#. Use cxgbetool to load the firmware image onto the card:\n\n .. code-block:: console\n\n cxgbetool t5nex0 loadfw /src/network/firmware/t5fw-*.bin\n\n#. Unload and reload the kernel module:\n\n .. code-block:: console\n\n kldunload if_cxgbe\n kldload if_cxgbe\n\n#. Verify with sysctl:\n\n .. code-block:: console\n\n sysctl -a | grep \"t5nex\" | grep \"firmware\"\n\n Example output:\n\n .. code-block:: console\n\n dev.t5nex.0.firmware_version: 1.13.32.0\n\nSample Application Notes\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nThis section demonstrates how to launch **testpmd** with Chelsio T5\ndevices managed by librte_pmd_cxgbe in FreeBSD operating system.\n\n#. Change to DPDK source directory where the target has been compiled in\n section :ref:`driver-compilation`:\n\n .. code-block:: console\n\n cd \n\n#. Copy the contigmem kernel module to /boot/kernel directory:\n\n .. code-block:: console\n\n cp x86_64-native-bsdapp-clang/kmod/contigmem.ko /boot/kernel/\n\n#. Add the following lines to /boot/loader.conf:\n\n .. code-block:: console\n\n # reserve 2 x 1G blocks of contiguous memory using contigmem driver\n hw.contigmem.num_buffers=2\n hw.contigmem.buffer_size=1073741824\n # load contigmem module during boot process\n contigmem_load=\"YES\"\n\n The above lines load the contigmem kernel module during boot process and\n allocate 2 x 1G blocks of contiguous memory to be used for DPDK later on.\n This is to avoid issues with potential memory fragmentation during later\n system up time, which may result in failure of allocating the contiguous\n memory required for the contigmem kernel module.\n\n#. Restart the system and ensure the contigmem module is loaded successfully:\n\n .. code-block:: console\n\n reboot\n kldstat | grep \"contigmem\"\n\n Example output:\n\n .. code-block:: console\n\n 2 1 0xffffffff817f1000 3118 contigmem.ko\n\n#. Repeat step 1 to ensure that you are in the DPDK source directory.\n\n#. Load the cxgbe kernel module:\n\n .. code-block:: console\n\n kldload if_cxgbe\n\n#. Get the PCI bus addresses of the interfaces bound to t5nex driver:\n\n .. code-block:: console\n\n pciconf -l | grep \"t5nex\"\n\n Example output:\n\n .. code-block:: console\n\n t5nex0@pci0:2:0:4: class=0x020000 card=0x00001425 chip=0x54011425 rev=0x00\n\n In the above example, the t5nex0 is bound to 2:0:4 bus address.\n\n .. note::\n\n Both the interfaces of a Chelsio T5 2-port adapter are bound to the\n same PCI bus address.\n\n#. Unload the kernel module:\n\n .. code-block:: console\n\n kldunload if_cxgbe\n\n#. Set the PCI bus addresses to hw.nic_uio.bdfs kernel environment parameter:\n\n .. code-block:: console\n\n kenv hw.nic_uio.bdfs=\"2:0:4\"\n\n This automatically binds 2:0:4 to nic_uio kernel driver when it is loaded in\n the next step.\n\n .. note::\n\n Currently, CXGBE PMD only supports the binding of PF4 for Chelsio T5 NICs.\n\n#. Load nic_uio kernel driver:\n\n .. code-block:: console\n\n kldload ./x86_64-native-bsdapp-clang/kmod/nic_uio.ko\n\n#. Start testpmd with basic parameters:\n\n .. code-block:: console\n\n ./x86_64-native-bsdapp-clang/app/testpmd -c 0xf -n 4 -w 0000:02:00.4 -- -i\n\n Example output:\n\n .. code-block:: console\n\n [...]\n EAL: PCI device 0000:02:00.4 on NUMA socket 0\n EAL: probe driver: 1425:5401 rte_cxgbe_pmd\n EAL: PCI memory mapped at 0x8007ec000\n EAL: PCI memory mapped at 0x842800000\n EAL: PCI memory mapped at 0x80086c000\n PMD: rte_cxgbe_pmd: fw: 1.13.32.0, TP: 0.1.4.8\n PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter\n Interactive-mode selected\n Configuring Port 0 (socket 0)\n Port 0: 00:07:43:2D:EA:C0\n Configuring Port 1 (socket 0)\n Port 1: 00:07:43:2D:EA:C8\n Checking link statuses...\n PMD: rte_cxgbe_pmd: Port0: passive DA port module inserted\n PMD: rte_cxgbe_pmd: Port1: passive DA port module inserted\n Port 0 Link Up - speed 10000 Mbps - full-duplex\n Port 1 Link Up - speed 10000 Mbps - full-duplex\n Done\n testpmd>\n\n.. note::\n\n Flow control pause TX/RX is disabled by default and can be enabled via\n testpmd as follows:\n\n .. code-block:: console\n\n testpmd> set flow_ctrl rx on tx on 0 0 0 0 mac_ctrl_frame_fwd off autoneg on 0\n testpmd> set flow_ctrl rx on tx on 0 0 0 0 mac_ctrl_frame_fwd off autoneg on 1\n\n To disable again, use:\n\n .. code-block:: console\n\n testpmd> set flow_ctrl rx off tx off 0 0 0 0 mac_ctrl_frame_fwd off autoneg off 0\n testpmd> set flow_ctrl rx off tx off 0 0 0 0 mac_ctrl_frame_fwd off autoneg off 1\n" }, { "path": "doc/guides/nics/e1000em.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nDriver for VM Emulated Devices\n==============================\n\nThe DPDK EM poll mode driver supports the following emulated devices:\n\n* qemu-kvm emulated Intel® 82540EM Gigabit Ethernet Controller (qemu e1000 device)\n\n* VMware* emulated Intel® 82545EM Gigabit Ethernet Controller\n\n* VMware emulated Intel® 8274L Gigabit Ethernet Controller.\n\nValidated Hypervisors\n---------------------\n\nThe validated hypervisors are:\n\n* KVM (Kernel Virtual Machine) with Qemu, version 0.14.0\n\n* KVM (Kernel Virtual Machine) with Qemu, version 0.15.1\n\n* VMware ESXi 5.0, Update 1\n\nRecommended Guest Operating System in Virtual Machine\n-----------------------------------------------------\n\nThe recommended guest operating system in a virtualized environment is:\n\n* Fedora* 18 (64-bit)\n\nFor supported kernel versions, refer to the *DPDK Release Notes*.\n\nSetting Up a KVM Virtual Machine\n--------------------------------\n\nThe following describes a target environment:\n\n* Host Operating System: Fedora 14\n\n* Hypervisor: KVM (Kernel Virtual Machine) with Qemu version, 0.14.0\n\n* Guest Operating System: Fedora 14\n\n* Linux Kernel Version: Refer to the DPDK Getting Started Guide\n\n* Target Applications: testpmd\n\nThe setup procedure is as follows:\n\n#. Download qemu-kvm-0.14.0 from\n `http://sourceforge.net/projects/kvm/files/qemu-kvm/ `_\n and install it in the Host OS using the following steps:\n\n When using a recent kernel (2.6.25+) with kvm modules included:\n\n .. code-block:: console\n\n tar xzf qemu-kvm-release.tar.gz cd qemu-kvm-release\n ./configure --prefix=/usr/local/kvm\n make\n sudo make install\n sudo /sbin/modprobe kvm-intel\n\n When using an older kernel or a kernel from a distribution without the kvm modules,\n you must download (from the same link), compile and install the modules yourself:\n\n .. code-block:: console\n\n tar xjf kvm-kmod-release.tar.bz2\n cd kvm-kmod-release\n ./configure\n make\n sudo make install\n sudo /sbin/modprobe kvm-intel\n\n Note that qemu-kvm installs in the /usr/local/bin directory.\n\n For more details about KVM configuration and usage, please refer to:\n `http://www.linux-kvm.org/page/HOWTO1 `_.\n\n#. Create a Virtual Machine and install Fedora 14 on the Virtual Machine.\n This is referred to as the Guest Operating System (Guest OS).\n\n#. Start the Virtual Machine with at least one emulated e1000 device.\n\n .. note::\n\n The Qemu provides several choices for the emulated network device backend.\n Most commonly used is a TAP networking backend that uses a TAP networking device in the host.\n For more information about Qemu supported networking backends and different options for configuring networking at Qemu,\n please refer to:\n\n — `http://www.linux-kvm.org/page/Networking `_\n\n — `http://wiki.qemu.org/Documentation/Networking `_\n\n — `http://qemu.weilnetz.de/qemu-doc.html `_\n\n For example, to start a VM with two emulated e1000 devices, issue the following command:\n\n .. code-block:: console\n\n /usr/local/kvm/bin/qemu-system-x86_64 -cpu host -smp 4 -hda qemu1.raw -m 1024\n -net nic,model=e1000,vlan=1,macaddr=DE:AD:1E:00:00:01\n -net tap,vlan=1,ifname=tapvm01,script=no,downscript=no\n -net nic,model=e1000,vlan=2,macaddr=DE:AD:1E:00:00:02\n -net tap,vlan=2,ifname=tapvm02,script=no,downscript=no\n\n where:\n\n — -m = memory to assign\n\n — -smp = number of smp cores\n\n — -hda = virtual disk image\n\n This command starts a new virtual machine with two emulated 82540EM devices,\n backed up with two TAP networking host interfaces, tapvm01 and tapvm02.\n\n .. code-block:: console\n\n # ip tuntap show\n tapvm01: tap\n tapvm02: tap\n\n#. Configure your TAP networking interfaces using ip/ifconfig tools.\n\n#. Log in to the guest OS and check that the expected emulated devices exist:\n\n .. code-block:: console\n\n # lspci -d 8086:100e\n 00:04.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)\n 00:05.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)\n\n#. Install the DPDK and run testpmd.\n\nKnown Limitations of Emulated Devices\n-------------------------------------\n\nThe following are known limitations:\n\n#. The Qemu e1000 RX path does not support multiple descriptors/buffers per packet.\n Therefore, rte_mbuf should be big enough to hold the whole packet.\n For example, to allow testpmd to receive jumbo frames, use the following:\n\n testpmd [options] -- --mbuf-size=\n\n#. Qemu e1000 does not validate the checksum of incoming packets.\n" }, { "path": "doc/guides/nics/index.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nNetwork Interface Controller Drivers\n====================================\n\n|today|\n\n\n**Contents**\n\n.. toctree::\n :maxdepth: 3\n :numbered:\n\n cxgbe\n e1000em\n ixgbe\n intel_vf\n mlx4\n virtio\n vmxnet3\n pcap_ring\n\n**Figures**\n\n:numref:`figure_single_port_nic` :ref:`figure_single_port_nic`\n\n:numref:`figure_perf_benchmark` :ref:`figure_perf_benchmark`\n\n:numref:`figure_fast_pkt_proc` :ref:`figure_fast_pkt_proc`\n\n:numref:`figure_inter_vm_comms` :ref:`figure_inter_vm_comms`\n\n:numref:`figure_host_vm_comms` :ref:`figure_host_vm_comms`\n\n:numref:`figure_host_vm_comms_qemu` :ref:`figure_host_vm_comms_qemu`\n\n:numref:`figure_vmxnet3_int` :ref:`figure_vmxnet3_int`\n\n:numref:`figure_vswitch_vm` :ref:`figure_vswitch_vm`\n\n:numref:`figure_vm_vm_comms` :ref:`figure_vm_vm_comms`\n" }, { "path": "doc/guides/nics/intel_vf.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nI40E/IXGBE/IGB Virtual Function Driver\n======================================\n\nSupported Intel® Ethernet Controllers (see the *DPDK Release Notes* for details)\nsupport the following modes of operation in a virtualized environment:\n\n* **SR-IOV mode**: Involves direct assignment of part of the port resources to different guest operating systems\n using the PCI-SIG Single Root I/O Virtualization (SR IOV) standard,\n also known as \"native mode\" or \"pass-through\" mode.\n In this chapter, this mode is referred to as IOV mode.\n\n* **VMDq mode**: Involves central management of the networking resources by an IO Virtual Machine (IOVM) or\n a Virtual Machine Monitor (VMM), also known as software switch acceleration mode.\n In this chapter, this mode is referred to as the Next Generation VMDq mode.\n\nSR-IOV Mode Utilization in a DPDK Environment\n---------------------------------------------\n\nThe DPDK uses the SR-IOV feature for hardware-based I/O sharing in IOV mode.\nTherefore, it is possible to partition SR-IOV capability on Ethernet controller NIC resources logically and\nexpose them to a virtual machine as a separate PCI function called a \"Virtual Function\".\nRefer to :numref:`figure_single_port_nic`.\n\nTherefore, a NIC is logically distributed among multiple virtual machines (as shown in :numref:`figure_single_port_nic`),\nwhile still having global data in common to share with the Physical Function and other Virtual Functions.\nThe DPDK fm10kvf, i40evf, igbvf or ixgbevf as a Poll Mode Driver (PMD) serves for the Intel® 82576 Gigabit Ethernet Controller,\nIntel® Ethernet Controller I350 family, Intel® 82599 10 Gigabit Ethernet Controller NIC,\nIntel® Fortville 10/40 Gigabit Ethernet Controller NIC's virtual PCI function, or PCIe host-interface of the Intel Ethernet Switch\nFM10000 Series.\nMeanwhile the DPDK Poll Mode Driver (PMD) also supports \"Physical Function\" of such NIC's on the host.\n\nThe DPDK PF/VF Poll Mode Driver (PMD) supports the Layer 2 switch on Intel® 82576 Gigabit Ethernet Controller,\nIntel® Ethernet Controller I350 family, Intel® 82599 10 Gigabit Ethernet Controller,\nand Intel® Fortville 10/40 Gigabit Ethernet Controller NICs so that guest can choose it for inter virtual machine traffic in SR-IOV mode.\n\nFor more detail on SR-IOV, please refer to the following documents:\n\n* `SR-IOV provides hardware based I/O sharing `_\n\n* `PCI-SIG-Single Root I/O Virtualization Support on IA\n `_\n\n* `Scalable I/O Virtualized Servers `_\n\n.. _figure_single_port_nic:\n\n.. figure:: img/single_port_nic.*\n\n Virtualization for a Single Port NIC in SR-IOV Mode\n\n\nPhysical and Virtual Function Infrastructure\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe following describes the Physical Function and Virtual Functions infrastructure for the supported Ethernet Controller NICs.\n\nVirtual Functions operate under the respective Physical Function on the same NIC Port and therefore have no access\nto the global NIC resources that are shared between other functions for the same NIC port.\n\nA Virtual Function has basic access to the queue resources and control structures of the queues assigned to it.\nFor global resource access, a Virtual Function has to send a request to the Physical Function for that port,\nand the Physical Function operates on the global resources on behalf of the Virtual Function.\nFor this out-of-band communication, an SR-IOV enabled NIC provides a memory buffer for each Virtual Function,\nwhich is called a \"Mailbox\".\n\nThe PCIE host-interface of Intel Ethernet Switch FM10000 Series VF infrastructure\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nIn a virtualized environment, the programmer can enable a maximum of *64 Virtual Functions (VF)*\nglobally per PCIE host-interface of the Intel Ethernet Switch FM10000 Series device.\nEach VF can have a maximum of 16 queue pairs.\nThe Physical Function in host could be only configured by the Linux* fm10k driver\n(in the case of the Linux Kernel-based Virtual Machine [KVM]), DPDK PMD PF driver doesn't support it yet.\n\nFor example,\n\n* Using Linux* fm10k driver:\n\n .. code-block:: console\n\n rmmod fm10k (To remove the fm10k module)\n insmod fm0k.ko max_vfs=2,2 (To enable two Virtual Functions per port)\n\nVirtual Function enumeration is performed in the following sequence by the Linux* pci driver for a dual-port NIC.\nWhen you enable the four Virtual Functions with the above command, the four enabled functions have a Function#\nrepresented by (Bus#, Device#, Function#) in sequence starting from 0 to 3.\nHowever:\n\n* Virtual Functions 0 and 2 belong to Physical Function 0\n\n* Virtual Functions 1 and 3 belong to Physical Function 1\n\n.. note::\n\n The above is an important consideration to take into account when targeting specific packets to a selected port.\n\nIntel® Fortville 10/40 Gigabit Ethernet Controller VF Infrastructure\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nIn a virtualized environment, the programmer can enable a maximum of *128 Virtual Functions (VF)*\nglobally per Intel® Fortville 10/40 Gigabit Ethernet Controller NIC device.\nEach VF can have a maximum of 16 queue pairs.\nThe Physical Function in host could be either configured by the Linux* i40e driver\n(in the case of the Linux Kernel-based Virtual Machine [KVM]) or by DPDK PMD PF driver.\nWhen using both DPDK PMD PF/VF drivers, the whole NIC will be taken over by DPDK based application.\n\nFor example,\n\n* Using Linux* i40e driver:\n\n .. code-block:: console\n\n rmmod i40e (To remove the i40e module)\n insmod i40e.ko max_vfs=2,2 (To enable two Virtual Functions per port)\n\n* Using the DPDK PMD PF i40e driver:\n\n Kernel Params: iommu=pt, intel_iommu=on\n\n .. code-block:: console\n\n modprobe uio\n insmod igb_uio\n ./dpdk_nic_bind.py -b igb_uio bb:ss.f\n echo 2 > /sys/bus/pci/devices/0000\\:bb\\:ss.f/max_vfs (To enable two VFs on a specific PCI device)\n\n Launch the DPDK testpmd/example or your own host daemon application using the DPDK PMD library.\n\n* Using the DPDK PMD PF ixgbe driver to enable VF RSS:\n\n Same steps as above to install the modules of uio, igb_uio, specify max_vfs for PCI device, and\n launch the DPDK testpmd/example or your own host daemon application using the DPDK PMD library.\n\n The available queue number(at most 4) per VF depends on the total number of pool, which is\n determined by the max number of VF at PF initialization stage and the number of queue specified\n in config:\n\n * If the max number of VF is set in the range of 1 to 32:\n\n If the number of rxq is specified as 4(e.g. '--rxq 4' in testpmd), then there are totally 32\n pools(ETH_32_POOLS), and each VF could have 4 or less(e.g. 2) queues;\n\n If the number of rxq is specified as 2(e.g. '--rxq 2' in testpmd), then there are totally 32\n pools(ETH_32_POOLS), and each VF could have 2 queues;\n\n * If the max number of VF is in the range of 33 to 64:\n\n If the number of rxq is 4 ('--rxq 4' in testpmd), then error message is expected as rxq is not\n correct at this case;\n\n If the number of rxq is 2 ('--rxq 2' in testpmd), then there is totally 64 pools(ETH_64_POOLS),\n and each VF have 2 queues;\n\n On host, to enable VF RSS functionality, rx mq mode should be set as ETH_MQ_RX_VMDQ_RSS\n or ETH_MQ_RX_RSS mode, and SRIOV mode should be activated(max_vfs >= 1).\n It also needs config VF RSS information like hash function, RSS key, RSS key length.\n\n .. code-block:: console\n\n testpmd -c 0xffff -n 4 -- --coremask= --rxq=4 --txq=4 -i\n\n The limitation for VF RSS on Intel® 82599 10 Gigabit Ethernet Controller is:\n The hash and key are shared among PF and all VF, the RETA table with 128 entries is also shared\n among PF and all VF; So it could not to provide a method to query the hash and reta content per\n VF on guest, while, if possible, please query them on host(PF) for the shared RETA information.\n\nVirtual Function enumeration is performed in the following sequence by the Linux* pci driver for a dual-port NIC.\nWhen you enable the four Virtual Functions with the above command, the four enabled functions have a Function#\nrepresented by (Bus#, Device#, Function#) in sequence starting from 0 to 3.\nHowever:\n\n* Virtual Functions 0 and 2 belong to Physical Function 0\n\n* Virtual Functions 1 and 3 belong to Physical Function 1\n\n.. note::\n\n The above is an important consideration to take into account when targeting specific packets to a selected port.\n\nIntel® 82599 10 Gigabit Ethernet Controller VF Infrastructure\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe programmer can enable a maximum of *63 Virtual Functions* and there must be *one Physical Function* per Intel® 82599\n10 Gigabit Ethernet Controller NIC port.\nThe reason for this is that the device allows for a maximum of 128 queues per port and a virtual/physical function has to\nhave at least one queue pair (RX/TX).\nThe current implementation of the DPDK ixgbevf driver supports a single queue pair (RX/TX) per Virtual Function.\nThe Physical Function in host could be either configured by the Linux* ixgbe driver\n(in the case of the Linux Kernel-based Virtual Machine [KVM]) or by DPDK PMD PF driver.\nWhen using both DPDK PMD PF/VF drivers, the whole NIC will be taken over by DPDK based application.\n\nFor example,\n\n* Using Linux* ixgbe driver:\n\n .. code-block:: console\n\n rmmod ixgbe (To remove the ixgbe module)\n insmod ixgbe max_vfs=2,2 (To enable two Virtual Functions per port)\n\n* Using the DPDK PMD PF ixgbe driver:\n\n Kernel Params: iommu=pt, intel_iommu=on\n\n .. code-block:: console\n\n modprobe uio\n insmod igb_uio\n ./dpdk_nic_bind.py -b igb_uio bb:ss.f\n echo 2 > /sys/bus/pci/devices/0000\\:bb\\:ss.f/max_vfs (To enable two VFs on a specific PCI device)\n\n Launch the DPDK testpmd/example or your own host daemon application using the DPDK PMD library.\n\nVirtual Function enumeration is performed in the following sequence by the Linux* pci driver for a dual-port NIC.\nWhen you enable the four Virtual Functions with the above command, the four enabled functions have a Function#\nrepresented by (Bus#, Device#, Function#) in sequence starting from 0 to 3.\nHowever:\n\n* Virtual Functions 0 and 2 belong to Physical Function 0\n\n* Virtual Functions 1 and 3 belong to Physical Function 1\n\n.. note::\n\n The above is an important consideration to take into account when targeting specific packets to a selected port.\n\nIntel® 82576 Gigabit Ethernet Controller and Intel® Ethernet Controller I350 Family VF Infrastructure\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nIn a virtualized environment, an Intel® 82576 Gigabit Ethernet Controller serves up to eight virtual machines (VMs).\nThe controller has 16 TX and 16 RX queues.\nThey are generally referred to (or thought of) as queue pairs (one TX and one RX queue).\nThis gives the controller 16 queue pairs.\n\nA pool is a group of queue pairs for assignment to the same VF, used for transmit and receive operations.\nThe controller has eight pools, with each pool containing two queue pairs, that is, two TX and two RX queues assigned to each VF.\n\nIn a virtualized environment, an Intel® Ethernet Controller I350 family device serves up to eight virtual machines (VMs) per port.\nThe eight queues can be accessed by eight different VMs if configured correctly (the i350 has 4x1GbE ports each with 8T X and 8 RX queues),\nthat means, one Transmit and one Receive queue assigned to each VF.\n\nFor example,\n\n* Using Linux* igb driver:\n\n .. code-block:: console\n\n rmmod igb (To remove the igb module)\n insmod igb max_vfs=2,2 (To enable two Virtual Functions per port)\n\n* Using Intel® DPDK PMD PF igb driver:\n\n Kernel Params: iommu=pt, intel_iommu=on modprobe uio\n\n .. code-block:: console\n\n insmod igb_uio\n ./dpdk_nic_bind.py -b igb_uio bb:ss.f\n echo 2 > /sys/bus/pci/devices/0000\\:bb\\:ss.f/max_vfs (To enable two VFs on a specific pci device)\n\n Launch DPDK testpmd/example or your own host daemon application using the DPDK PMD library.\n\nVirtual Function enumeration is performed in the following sequence by the Linux* pci driver for a four-port NIC.\nWhen you enable the four Virtual Functions with the above command, the four enabled functions have a Function#\nrepresented by (Bus#, Device#, Function#) in sequence, starting from 0 to 7.\nHowever:\n\n* Virtual Functions 0 and 4 belong to Physical Function 0\n\n* Virtual Functions 1 and 5 belong to Physical Function 1\n\n* Virtual Functions 2 and 6 belong to Physical Function 2\n\n* Virtual Functions 3 and 7 belong to Physical Function 3\n\n.. note::\n\n The above is an important consideration to take into account when targeting specific packets to a selected port.\n\nValidated Hypervisors\n~~~~~~~~~~~~~~~~~~~~~\n\nThe validated hypervisor is:\n\n* KVM (Kernel Virtual Machine) with Qemu, version 0.14.0\n\nHowever, the hypervisor is bypassed to configure the Virtual Function devices using the Mailbox interface,\nthe solution is hypervisor-agnostic.\nXen* and VMware* (when SR- IOV is supported) will also be able to support the DPDK with Virtual Function driver support.\n\nExpected Guest Operating System in Virtual Machine\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe expected guest operating systems in a virtualized environment are:\n\n* Fedora* 14 (64-bit)\n\n* Ubuntu* 10.04 (64-bit)\n\nFor supported kernel versions, refer to the *DPDK Release Notes*.\n\nSetting Up a KVM Virtual Machine Monitor\n----------------------------------------\n\nThe following describes a target environment:\n\n* Host Operating System: Fedora 14\n\n* Hypervisor: KVM (Kernel Virtual Machine) with Qemu version 0.14.0\n\n* Guest Operating System: Fedora 14\n\n* Linux Kernel Version: Refer to the *DPDK Getting Started Guide*\n\n* Target Applications: l2fwd, l3fwd-vf\n\nThe setup procedure is as follows:\n\n#. Before booting the Host OS, open **BIOS setup** and enable **Intel® VT features**.\n\n#. While booting the Host OS kernel, pass the intel_iommu=on kernel command line argument using GRUB.\n When using DPDK PF driver on host, pass the iommu=pt kernel command line argument in GRUB.\n\n#. Download qemu-kvm-0.14.0 from\n `http://sourceforge.net/projects/kvm/files/qemu-kvm/ `_\n and install it in the Host OS using the following steps:\n\n When using a recent kernel (2.6.25+) with kvm modules included:\n\n .. code-block:: console\n\n tar xzf qemu-kvm-release.tar.gz\n cd qemu-kvm-release\n ./configure --prefix=/usr/local/kvm\n make\n sudo make install\n sudo /sbin/modprobe kvm-intel\n\n When using an older kernel, or a kernel from a distribution without the kvm modules,\n you must download (from the same link), compile and install the modules yourself:\n\n .. code-block:: console\n\n tar xjf kvm-kmod-release.tar.bz2\n cd kvm-kmod-release\n ./configure\n make\n sudo make install\n sudo /sbin/modprobe kvm-intel\n\n qemu-kvm installs in the /usr/local/bin directory.\n\n For more details about KVM configuration and usage, please refer to:\n\n `http://www.linux-kvm.org/page/HOWTO1 `_.\n\n#. Create a Virtual Machine and install Fedora 14 on the Virtual Machine.\n This is referred to as the Guest Operating System (Guest OS).\n\n#. Download and install the latest ixgbe driver from:\n\n `http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=14687 `_\n\n#. In the Host OS\n\n When using Linux kernel ixgbe driver, unload the Linux ixgbe driver and reload it with the max_vfs=2,2 argument:\n\n .. code-block:: console\n\n rmmod ixgbe\n modprobe ixgbe max_vfs=2,2\n\n When using DPDK PMD PF driver, insert DPDK kernel module igb_uio and set the number of VF by sysfs max_vfs:\n\n .. code-block:: console\n\n modprobe uio\n insmod igb_uio\n ./dpdk_nic_bind.py -b igb_uio 02:00.0 02:00.1 0e:00.0 0e:00.1\n echo 2 > /sys/bus/pci/devices/0000\\:02\\:00.0/max_vfs\n echo 2 > /sys/bus/pci/devices/0000\\:02\\:00.1/max_vfs\n echo 2 > /sys/bus/pci/devices/0000\\:0e\\:00.0/max_vfs\n echo 2 > /sys/bus/pci/devices/0000\\:0e\\:00.1/max_vfs\n\n .. note::\n\n You need to explicitly specify number of vfs for each port, for example,\n in the command above, it creates two vfs for the first two ixgbe ports.\n\n Let say we have a machine with four physical ixgbe ports:\n\n\n 0000:02:00.0\n\n 0000:02:00.1\n\n 0000:0e:00.0\n\n 0000:0e:00.1\n\n The command above creates two vfs for device 0000:02:00.0:\n\n .. code-block:: console\n\n ls -alrt /sys/bus/pci/devices/0000\\:02\\:00.0/virt*\n lrwxrwxrwx. 1 root root 0 Apr 13 05:40 /sys/bus/pci/devices/0000:02:00.0/virtfn1 -> ../0000:02:10.2\n lrwxrwxrwx. 1 root root 0 Apr 13 05:40 /sys/bus/pci/devices/0000:02:00.0/virtfn0 -> ../0000:02:10.0\n\n It also creates two vfs for device 0000:02:00.1:\n\n .. code-block:: console\n\n ls -alrt /sys/bus/pci/devices/0000\\:02\\:00.1/virt*\n lrwxrwxrwx. 1 root root 0 Apr 13 05:51 /sys/bus/pci/devices/0000:02:00.1/virtfn1 -> ../0000:02:10.3\n lrwxrwxrwx. 1 root root 0 Apr 13 05:51 /sys/bus/pci/devices/0000:02:00.1/virtfn0 -> ../0000:02:10.1\n\n#. List the PCI devices connected and notice that the Host OS shows two Physical Functions (traditional ports)\n and four Virtual Functions (two for each port).\n This is the result of the previous step.\n\n#. Insert the pci_stub module to hold the PCI devices that are freed from the default driver using the following command\n (see http://www.linux-kvm.org/page/How_to_assign_devices_with_VT-d_in_KVM Section 4 for more information):\n\n .. code-block:: console\n\n sudo /sbin/modprobe pci-stub\n\n Unbind the default driver from the PCI devices representing the Virtual Functions.\n A script to perform this action is as follows:\n\n .. code-block:: console\n\n echo \"8086 10ed\" > /sys/bus/pci/drivers/pci-stub/new_id\n echo 0000:08:10.0 > /sys/bus/pci/devices/0000:08:10.0/driver/unbind\n echo 0000:08:10.0 > /sys/bus/pci/drivers/pci-stub/bind\n\n where, 0000:08:10.0 belongs to the Virtual Function visible in the Host OS.\n\n#. Now, start the Virtual Machine by running the following command:\n\n .. code-block:: console\n\n /usr/local/kvm/bin/qemu-system-x86_64 -m 4096 -smp 4 -boot c -hda lucid.qcow2 -device pci-assign,host=08:10.0\n\n where:\n\n — -m = memory to assign\n\n — -smp = number of smp cores\n\n — -boot = boot option\n\n — -hda = virtual disk image\n\n — -device = device to attach\n\n .. note::\n\n — The pci-assign,host=08:10.0 alue indicates that you want to attach a PCI device\n to a Virtual Machine and the respective (Bus:Device.Function)\n numbers should be passed for the Virtual Function to be attached.\n\n — qemu-kvm-0.14.0 allows a maximum of four PCI devices assigned to a VM,\n but this is qemu-kvm version dependent since qemu-kvm-0.14.1 allows a maximum of five PCI devices.\n\n — qemu-system-x86_64 also has a -cpu command line option that is used to select the cpu_model\n to emulate in a Virtual Machine. Therefore, it can be used as:\n\n .. code-block:: console\n\n /usr/local/kvm/bin/qemu-system-x86_64 -cpu ?\n\n (to list all available cpu_models)\n\n /usr/local/kvm/bin/qemu-system-x86_64 -m 4096 -cpu host -smp 4 -boot c -hda lucid.qcow2 -device pci-assign,host=08:10.0\n\n (to use the same cpu_model equivalent to the host cpu)\n\n For more information, please refer to: `http://wiki.qemu.org/Features/CPUModels `_.\n\n#. Install and run DPDK host app to take over the Physical Function. Eg.\n\n .. code-block:: console\n\n make install T=x86_64-native-linuxapp-gcc\n ./x86_64-native-linuxapp-gcc/app/testpmd -c f -n 4 -- -i\n\n#. Finally, access the Guest OS using vncviewer with the localhost:5900 port and check the lspci command output in the Guest OS.\n The virtual functions will be listed as available for use.\n\n#. Configure and install the DPDK with an x86_64-native-linuxapp-gcc configuration on the Guest OS as normal,\n that is, there is no change to the normal installation procedure.\n\n .. code-block:: console\n\n make config T=x86_64-native-linuxapp-gcc O=x86_64-native-linuxapp-gcc\n cd x86_64-native-linuxapp-gcc\n make\n\n.. note::\n\n If you are unable to compile the DPDK and you are getting \"error: CPU you selected does not support x86-64 instruction set\",\n power off the Guest OS and start the virtual machine with the correct -cpu option in the qemu- system-x86_64 command as shown in step 9.\n You must select the best x86_64 cpu_model to emulate or you can select host option if available.\n\n.. note::\n\n Run the DPDK l2fwd sample application in the Guest OS with Hugepages enabled.\n For the expected benchmark performance, you must pin the cores from the Guest OS to the Host OS (taskset can be used to do this) and\n you must also look at the PCI Bus layout on the board to ensure you are not running the traffic over the QPI Interface.\n\n.. note::\n\n * The Virtual Machine Manager (the Fedora package name is virt-manager) is a utility for virtual machine management\n that can also be used to create, start, stop and delete virtual machines.\n If this option is used, step 2 and 6 in the instructions provided will be different.\n\n * virsh, a command line utility for virtual machine management,\n can also be used to bind and unbind devices to a virtual machine in Ubuntu.\n If this option is used, step 6 in the instructions provided will be different.\n\n * The Virtual Machine Monitor (see :numref:`figure_perf_benchmark`) is equivalent to a Host OS with KVM installed as described in the instructions.\n\n.. _figure_perf_benchmark:\n\n.. figure:: img/perf_benchmark.*\n\n Performance Benchmark Setup\n\n\nDPDK SR-IOV PMD PF/VF Driver Usage Model\n----------------------------------------\n\nFast Host-based Packet Processing\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSoftware Defined Network (SDN) trends are demanding fast host-based packet handling.\nIn a virtualization environment,\nthe DPDK VF PMD driver performs the same throughput result as a non-VT native environment.\n\nWith such host instance fast packet processing, lots of services such as filtering, QoS,\nDPI can be offloaded on the host fast path.\n\n:numref:`figure_fast_pkt_proc` shows the scenario where some VMs directly communicate externally via a VFs,\nwhile others connect to a virtual switch and share the same uplink bandwidth.\n\n.. _figure_fast_pkt_proc:\n\n.. figure:: img/fast_pkt_proc.*\n\n Fast Host-based Packet Processing\n\n\nSR-IOV (PF/VF) Approach for Inter-VM Communication\n--------------------------------------------------\n\nInter-VM data communication is one of the traffic bottle necks in virtualization platforms.\nSR-IOV device assignment helps a VM to attach the real device, taking advantage of the bridge in the NIC.\nSo VF-to-VF traffic within the same physical port (VM0<->VM1) have hardware acceleration.\nHowever, when VF crosses physical ports (VM0<->VM2), there is no such hardware bridge.\nIn this case, the DPDK PMD PF driver provides host forwarding between such VMs.\n\n:numref:`figure_inter_vm_comms` shows an example.\nIn this case an update of the MAC address lookup tables in both the NIC and host DPDK application is required.\n\nIn the NIC, writing the destination of a MAC address belongs to another cross device VM to the PF specific pool.\nSo when a packet comes in, its destination MAC address will match and forward to the host DPDK PMD application.\n\nIn the host DPDK application, the behavior is similar to L2 forwarding,\nthat is, the packet is forwarded to the correct PF pool.\nThe SR-IOV NIC switch forwards the packet to a specific VM according to the MAC destination address\nwhich belongs to the destination VF on the VM.\n\n.. _figure_inter_vm_comms:\n\n.. figure:: img/inter_vm_comms.*\n\n Inter-VM Communication\n" }, { "path": "doc/guides/nics/ixgbe.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIXGBE Driver\n============\n\nVector PMD for IXGBE\n--------------------\n\nVector PMD uses Intel® SIMD instructions to optimize packet I/O.\nIt improves load/store bandwidth efficiency of L1 data cache by using a wider SSE/AVX register 1 (1).\nThe wider register gives space to hold multiple packet buffers so as to save instruction number when processing bulk of packets.\n\nThere is no change to PMD API. The RX/TX handler are the only two entries for vPMD packet I/O.\nThey are transparently registered at runtime RX/TX execution if all condition checks pass.\n\n1. To date, only an SSE version of IX GBE vPMD is available.\n To ensure that vPMD is in the binary code, ensure that the option CONFIG_RTE_IXGBE_INC_VECTOR=y is in the configure file.\n\nSome constraints apply as pre-conditions for specific optimizations on bulk packet transfers.\nThe following sections explain RX and TX constraints in the vPMD.\n\nRX Constraints\n~~~~~~~~~~~~~~\n\nPrerequisites and Pre-conditions\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe following prerequisites apply:\n\n* To enable vPMD to work for RX, bulk allocation for Rx must be allowed.\n\nEnsure that the following pre-conditions are satisfied:\n\n* rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST\n\n* rxq->rx_free_thresh < rxq->nb_rx_desc\n\n* (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0\n\n* rxq->nb_rx_desc < (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST)\n\nThese conditions are checked in the code.\n\nScattered packets are not supported in this mode.\nIf an incoming packet is greater than the maximum acceptable length of one \"mbuf\" data size (by default, the size is 2 KB),\nvPMD for RX would be disabled.\n\nBy default, IXGBE_MAX_RING_DESC is set to 4096 and RTE_PMD_IXGBE_RX_MAX_BURST is set to 32.\n\nFeature not Supported by RX Vector PMD\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nSome features are not supported when trying to increase the throughput in vPMD.\nThey are:\n\n* IEEE1588\n\n* FDIR\n\n* Header split\n\n* RX checksum off load\n\nOther features are supported using optional MACRO configuration. They include:\n\n* HW VLAN strip\n\n* HW extend dual VLAN\n\n* Enabled by RX_OLFLAGS (RTE_IXGBE_RX_OLFLAGS_ENABLE=y)\n\n\nTo guarantee the constraint, configuration flags in dev_conf.rxmode will be checked:\n\n* hw_vlan_strip\n\n* hw_vlan_extend\n\n* hw_ip_checksum\n\n* header_split\n\n* dev_conf\n\nfdir_conf->mode will also be checked.\n\nRX Burst Size\n^^^^^^^^^^^^^\n\nAs vPMD is focused on high throughput, it assumes that the RX burst size is equal to or greater than 32 per burst.\nIt returns zero if using nb_pkt < 32 as the expected packet number in the receive handler.\n\nTX Constraint\n~~~~~~~~~~~~~\n\nPrerequisite\n^^^^^^^^^^^^\n\nThe only prerequisite is related to tx_rs_thresh.\nThe tx_rs_thresh value must be greater than or equal to RTE_PMD_IXGBE_TX_MAX_BURST,\nbut less or equal to RTE_IXGBE_TX_MAX_FREE_BUF_SZ.\nConsequently, by default the tx_rs_thresh value is in the range 32 to 64.\n\nFeature not Supported by RX Vector PMD\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nTX vPMD only works when txq_flags is set to IXGBE_SIMPLE_FLAGS.\n\nThis means that it does not support TX multi-segment, VLAN offload and TX csum offload.\nThe following MACROs are used for these three features:\n\n* ETH_TXQ_FLAGS_NOMULTSEGS\n\n* ETH_TXQ_FLAGS_NOVLANOFFL\n\n* ETH_TXQ_FLAGS_NOXSUMSCTP\n\n* ETH_TXQ_FLAGS_NOXSUMUDP\n\n* ETH_TXQ_FLAGS_NOXSUMTCP\n\n\nSample Application Notes\n~~~~~~~~~~~~~~~~~~~~~~~~\n\ntestpmd\n^^^^^^^\n\nBy default, using CONFIG_RTE_IXGBE_RX_OLFLAGS_ENABLE=y:\n\n.. code-block:: console\n\n ./x86_64-native-linuxapp-gcc/app/testpmd -c 300 -n 4 -- -i --burst=32 --rxfreet=32 --mbcache=250 --txpt=32 --rxht=8 --rxwt=0 --txfreet=32 --txrst=32 --txqflags=0xf01\n\nWhen CONFIG_RTE_IXGBE_RX_OLFLAGS_ENABLE=n, better performance can be achieved:\n\n.. code-block:: console\n\n ./x86_64-native-linuxapp-gcc/app/testpmd -c 300 -n 4 -- -i --burst=32 --rxfreet=32 --mbcache=250 --txpt=32 --rxht=8 --rxwt=0 --txfreet=32 --txrst=32 --txqflags=0xf01 --disable-hw-vlan\n\nl3fwd\n^^^^^\n\nWhen running l3fwd with vPMD, there is one thing to note.\nIn the configuration, ensure that port_conf.rxmode.hw_ip_checksum=0.\nOtherwise, by default, RX vPMD is disabled.\n\nload_balancer\n^^^^^^^^^^^^^\n\nAs in the case of l3fwd, set configure port_conf.rxmode.hw_ip_checksum=0 to enable vPMD.\nIn addition, for improved performance, use -bsz \"(32,32),(64,64),(32,32)\" in load_balancer to avoid using the default burst size of 144.\n" }, { "path": "doc/guides/nics/mlx4.rst", "content": ".. BSD LICENSE\n Copyright 2012-2015 6WIND S.A.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of 6WIND S.A. nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nMLX4 poll mode driver library\n=============================\n\nThe MLX4 poll mode driver library (**librte_pmd_mlx4**) implements support\nfor **Mellanox ConnectX-3 EN** 10/40 Gbps adapters as well as their virtual\nfunctions (VF) in SR-IOV context.\n\nInformation and documentation about this family of adapters can be found on\nthe `Mellanox website `_. Help is also provided by\nthe `Mellanox community `_.\n\nThere is also a `section dedicated to this poll mode driver\n`_.\n\n.. note::\n\n Due to external dependencies, this driver is disabled by default. It must\n be enabled manually by setting ``CONFIG_RTE_LIBRTE_MLX4_PMD=y`` and\n recompiling DPDK.\n\n.. warning::\n\n ``CONFIG_RTE_BUILD_COMBINE_LIBS`` with ``CONFIG_RTE_BUILD_SHARED_LIB``\n is not supported and thus the compilation will fail with this configuration.\n\nImplementation details\n----------------------\n\nMost Mellanox ConnectX-3 devices provide two ports but expose a single PCI\nbus address, thus unlike most drivers, librte_pmd_mlx4 registers itself as a\nPCI driver that allocates one Ethernet device per detected port.\n\nFor this reason, one cannot white/blacklist a single port without also\nwhite/blacklisting the others on the same device.\n\nBesides its dependency on libibverbs (that implies libmlx4 and associated\nkernel support), librte_pmd_mlx4 relies heavily on system calls for control\noperations such as querying/updating the MTU and flow control parameters.\n\nFor security reasons and robustness, this driver only deals with virtual\nmemory addresses. The way resources allocations are handled by the kernel\ncombined with hardware specifications that allow it to handle virtual memory\naddresses directly ensure that DPDK applications cannot access random\nphysical memory (or memory that does not belong to the current process).\n\nThis capability allows the PMD to coexist with kernel network interfaces\nwhich remain functional, although they stop receiving unicast packets as\nlong as they share the same MAC address.\n\nCompiling librte_pmd_mlx4 causes DPDK to be linked against libibverbs.\n\nFeatures and limitations\n------------------------\n\n- RSS, also known as RCA, is supported. In this mode the number of\n configured RX queues must be a power of two.\n- VLAN filtering is supported.\n- Link state information is provided.\n- Promiscuous mode is supported.\n- All multicast mode is supported.\n- Multiple MAC addresses (unicast, multicast) can be configured.\n- Scattered packets are supported for TX and RX.\n- Inner L3/L4 (IP, TCP and UDP) TX/RX checksum offloading and validation.\n- Outer L3 (IP) TX/RX checksum offloading and validation for VXLAN frames.\n\n.. break\n\n- RSS hash key cannot be modified.\n- Hardware counters are not implemented (they are software counters).\n\nConfiguration\n-------------\n\nCompilation options\n~~~~~~~~~~~~~~~~~~~\n\nThese options can be modified in the ``.config`` file.\n\n- ``CONFIG_RTE_LIBRTE_MLX4_PMD`` (default **n**)\n\n Toggle compilation of librte_pmd_mlx4 itself.\n\n- ``CONFIG_RTE_LIBRTE_MLX4_DEBUG`` (default **n**)\n\n Toggle debugging code and stricter compilation flags. Enabling this option\n adds additional run-time checks and debugging messages at the cost of\n lower performance.\n\n- ``CONFIG_RTE_LIBRTE_MLX4_SGE_WR_N`` (default **4**)\n\n Number of scatter/gather elements (SGEs) per work request (WR). Lowering\n this number improves performance but also limits the ability to receive\n scattered packets (packets that do not fit a single mbuf). The default\n value is a safe tradeoff.\n\n- ``CONFIG_RTE_LIBRTE_MLX4_MAX_INLINE`` (default **0**)\n\n Amount of data to be inlined during TX operations. Improves latency but\n lowers throughput.\n\n- ``CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE`` (default **8**)\n\n Maximum number of cached memory pools (MPs) per TX queue. Each MP from\n which buffers are to be transmitted must be associated to memory regions\n (MRs). This is a slow operation that must be cached.\n\n This value is always 1 for RX queues since they use a single MP.\n\n- ``CONFIG_RTE_LIBRTE_MLX4_SOFT_COUNTERS`` (default **1**)\n\n Toggle software counters. No counters are available if this option is\n disabled since hardware counters are not supported.\n\nEnvironment variables\n~~~~~~~~~~~~~~~~~~~~~\n\n- ``MLX4_INLINE_RECV_SIZE``\n\n A nonzero value enables inline receive for packets up to that size. May\n significantly improve performance in some cases but lower it in\n others. Requires careful testing.\n\nRun-time configuration\n~~~~~~~~~~~~~~~~~~~~~~\n\n- The only constraint when RSS mode is requested is to make sure the number\n of RX queues is a power of two. This is a hardware requirement.\n\n- librte_pmd_mlx4 brings kernel network interfaces up during initialization\n because it is affected by their state. Forcing them down prevents packets\n reception.\n\n- **ethtool** operations on related kernel interfaces also affect the PMD.\n\nKernel module parameters\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe **mlx4_core** kernel module has several parameters that affect the\nbehavior and/or the performance of librte_pmd_mlx4. Some of them are described\nbelow.\n\n- **num_vfs** (integer or triplet, optionally prefixed by device address\n strings)\n\n Create the given number of VFs on the specified devices.\n\n- **log_num_mgm_entry_size** (integer)\n\n Device-managed flow steering (DMFS) is required by DPDK applications. It is\n enabled by using a negative value, the last four bits of which have a\n special meaning.\n\n - **-1**: force device-managed flow steering (DMFS).\n - **-7**: configure optimized steering mode to improve performance with the\n following limitation: VLAN filtering is not supported with this mode.\n This is the recommended mode in case VLAN filter is not needed.\n\nPrerequisites\n-------------\n\nThis driver relies on external libraries and kernel drivers for resources\nallocations and initialization. The following dependencies are not part of\nDPDK and must be installed separately:\n\n- **libibverbs**\n\n User space verbs framework used by librte_pmd_mlx4. This library provides\n a generic interface between the kernel and low-level user space drivers\n such as libmlx4.\n\n It allows slow and privileged operations (context initialization, hardware\n resources allocations) to be managed by the kernel and fast operations to\n never leave user space.\n\n- **libmlx4**\n\n Low-level user space driver library for Mellanox ConnectX-3 devices,\n it is automatically loaded by libibverbs.\n\n This library basically implements send/receive calls to the hardware\n queues.\n\n- **Kernel modules** (mlnx-ofed-kernel)\n\n They provide the kernel-side verbs API and low level device drivers that\n manage actual hardware initialization and resources sharing with user\n space processes.\n\n Unlike most other PMDs, these modules must remain loaded and bound to\n their devices:\n\n - mlx4_core: hardware driver managing Mellanox ConnectX-3 devices.\n - mlx4_en: Ethernet device driver that provides kernel network interfaces.\n - mlx4_ib: InifiniBand device driver.\n - ib_uverbs: user space driver for verbs (entry point for libibverbs).\n\n- **Firmware update**\n\n Mellanox OFED releases include firmware updates for ConnectX-3 adapters.\n\n Because each release provides new features, these updates must be applied to\n match the kernel modules and libraries they come with.\n\n.. note::\n\n Both libraries are BSD and GPL licensed. Linux kernel modules are GPL\n licensed.\n\nCurrently supported by DPDK:\n\n- Mellanox OFED **3.0**.\n- Firmware version **2.34.5000** and higher.\n\nGetting Mellanox OFED\n~~~~~~~~~~~~~~~~~~~~~\n\nWhile these libraries and kernel modules are available on OpenFabrics\nAlliance's `website `_ and provided by package\nmanagers on most distributions, this PMD requires Ethernet extensions that\nmay not be supported at the moment (this is a work in progress).\n\n`Mellanox OFED\n`_\nincludes the necessary support and should be used in the meantime. For DPDK,\nonly libibverbs, libmlx4, mlnx-ofed-kernel packages and firmware updates are\nrequired from that distribution.\n\n.. note::\n\n Several versions of Mellanox OFED are available. Installing the version\n this DPDK release was developed and tested against is strongly\n recommended. Please check the `prerequisites`_.\n\nUsage example\n-------------\n\nThis section demonstrates how to launch **testpmd** with Mellanox ConnectX-3\ndevices managed by librte_pmd_mlx4.\n\n#. Load the kernel modules:\n\n .. code-block:: console\n\n modprobe -a ib_uverbs mlx4_en mlx4_core mlx4_ib\n\n .. note::\n\n User space I/O kernel modules (uio and igb_uio) are not used and do\n not have to be loaded.\n\n#. Make sure Ethernet interfaces are in working order and linked to kernel\n verbs. Related sysfs entries should be present:\n\n .. code-block:: console\n\n ls -d /sys/class/net/*/device/infiniband_verbs/uverbs* | cut -d / -f 5\n\n Example output:\n\n .. code-block:: console\n\n eth2\n eth3\n eth4\n eth5\n\n#. Optionally, retrieve their PCI bus addresses for whitelisting:\n\n .. code-block:: console\n\n {\n for intf in eth2 eth3 eth4 eth5;\n do\n (cd \"/sys/class/net/${intf}/device/\" && pwd -P);\n done;\n } |\n sed -n 's,.*/\\(.*\\),-w \\1,p'\n\n Example output:\n\n .. code-block:: console\n\n -w 0000:83:00.0\n -w 0000:83:00.0\n -w 0000:84:00.0\n -w 0000:84:00.0\n\n .. note::\n\n There are only two distinct PCI bus addresses because the Mellanox\n ConnectX-3 adapters installed on this system are dual port.\n\n#. Request huge pages:\n\n .. code-block:: console\n\n echo 1024 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages/nr_hugepages\n\n#. Start testpmd with basic parameters:\n\n .. code-block:: console\n\n testpmd -c 0xff00 -n 4 -w 0000:83:00.0 -w 0000:84:00.0 -- --rxq=2 --txq=2 -i\n\n Example output:\n\n .. code-block:: console\n\n [...]\n EAL: PCI device 0000:83:00.0 on NUMA socket 1\n EAL: probe driver: 15b3:1007 librte_pmd_mlx4\n PMD: librte_pmd_mlx4: PCI information matches, using device \"mlx4_0\" (VF: false)\n PMD: librte_pmd_mlx4: 2 port(s) detected\n PMD: librte_pmd_mlx4: port 1 MAC address is 00:02:c9:b5:b7:50\n PMD: librte_pmd_mlx4: port 2 MAC address is 00:02:c9:b5:b7:51\n EAL: PCI device 0000:84:00.0 on NUMA socket 1\n EAL: probe driver: 15b3:1007 librte_pmd_mlx4\n PMD: librte_pmd_mlx4: PCI information matches, using device \"mlx4_1\" (VF: false)\n PMD: librte_pmd_mlx4: 2 port(s) detected\n PMD: librte_pmd_mlx4: port 1 MAC address is 00:02:c9:b5:ba:b0\n PMD: librte_pmd_mlx4: port 2 MAC address is 00:02:c9:b5:ba:b1\n Interactive-mode selected\n Configuring Port 0 (socket 0)\n PMD: librte_pmd_mlx4: 0x867d60: TX queues number update: 0 -> 2\n PMD: librte_pmd_mlx4: 0x867d60: RX queues number update: 0 -> 2\n Port 0: 00:02:C9:B5:B7:50\n Configuring Port 1 (socket 0)\n PMD: librte_pmd_mlx4: 0x867da0: TX queues number update: 0 -> 2\n PMD: librte_pmd_mlx4: 0x867da0: RX queues number update: 0 -> 2\n Port 1: 00:02:C9:B5:B7:51\n Configuring Port 2 (socket 0)\n PMD: librte_pmd_mlx4: 0x867de0: TX queues number update: 0 -> 2\n PMD: librte_pmd_mlx4: 0x867de0: RX queues number update: 0 -> 2\n Port 2: 00:02:C9:B5:BA:B0\n Configuring Port 3 (socket 0)\n PMD: librte_pmd_mlx4: 0x867e20: TX queues number update: 0 -> 2\n PMD: librte_pmd_mlx4: 0x867e20: RX queues number update: 0 -> 2\n Port 3: 00:02:C9:B5:BA:B1\n Checking link statuses...\n Port 0 Link Up - speed 10000 Mbps - full-duplex\n Port 1 Link Up - speed 40000 Mbps - full-duplex\n Port 2 Link Up - speed 10000 Mbps - full-duplex\n Port 3 Link Up - speed 40000 Mbps - full-duplex\n Done\n testpmd>\n" }, { "path": "doc/guides/nics/pcap_ring.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nLibpcap and Ring Based Poll Mode Drivers\n========================================\n\nIn addition to Poll Mode Drivers (PMDs) for physical and virtual hardware,\nthe DPDK also includes two pure-software PMDs. These two drivers are:\n\n* A libpcap -based PMD (librte_pmd_pcap) that reads and writes packets using libpcap,\n - both from files on disk, as well as from physical NIC devices using standard Linux kernel drivers.\n\n* A ring-based PMD (librte_pmd_ring) that allows a set of software FIFOs (that is, rte_ring)\n to be accessed using the PMD APIs, as though they were physical NICs.\n\n.. note::\n\n The libpcap -based PMD is disabled by default in the build configuration files,\n owing to an external dependency on the libpcap development files which must be installed on the board.\n Once the libpcap development files are installed,\n the library can be enabled by setting CONFIG_RTE_LIBRTE_PMD_PCAP=y and recompiling the Intel® DPDK.\n\nUsing the Drivers from the EAL Command Line\n-------------------------------------------\n\nFor ease of use, the DPDK EAL also has been extended to allow pseudo-Ethernet devices,\nusing one or more of these drivers,\nto be created at application startup time during EAL initialization.\n\nTo do so, the --vdev= parameter must be passed to the EAL.\nThis takes take options to allow ring and pcap-based Ethernet to be allocated and used transparently by the application.\nThis can be used, for example, for testing on a virtual machine where there are no Ethernet ports.\n\nLibpcap-based PMD\n~~~~~~~~~~~~~~~~~\n\nPcap-based devices can be created using the virtual device --vdev option.\nThe device name must start with the eth_pcap prefix followed by numbers or letters.\nThe name is unique for each device. Each device can have multiple stream options and multiple devices can be used.\nMultiple device definitions can be arranged using multiple --vdev.\nDevice name and stream options must be separated by commas as shown below:\n\n.. code-block:: console\n\n $RTE_TARGET/app/testpmd -c f -n 4 --vdev 'eth_pcap0,stream_opt0=..,stream_opt1=..' --vdev='eth_pcap1,stream_opt0=..'\n\nDevice Streams\n^^^^^^^^^^^^^^\n\nMultiple ways of stream definitions can be assessed and combined as long as the following two rules are respected:\n\n* A device is provided with two different streams - reception and transmission.\n\n* A device is provided with one network interface name used for reading and writing packets.\n\nThe different stream types are:\n\n* rx_pcap: Defines a reception stream based on a pcap file.\n The driver reads each packet within the given pcap file as if it was receiving it from the wire.\n The value is a path to a valid pcap file.\n\n rx_pcap=/path/to/file.pcap\n\n* tx_pcap: Defines a transmission stream based on a pcap file.\n The driver writes each received packet to the given pcap file.\n The value is a path to a pcap file.\n The file is overwritten if it already exists and it is created if it does not.\n\n tx_pcap=/path/to/file.pcap\n\n* rx_iface: Defines a reception stream based on a network interface name.\n The driver reads packets coming from the given interface using the Linux kernel driver for that interface.\n The value is an interface name.\n\n rx_iface=eth0\n\n* tx_iface: Defines a transmission stream based on a network interface name.\n The driver sends packets to the given interface using the Linux kernel driver for that interface.\n The value is an interface name.\n\n tx_iface=eth0\n\n* iface: Defines a device mapping a network interface.\n The driver both reads and writes packets from and to the given interface.\n The value is an interface name.\n\n iface=eth0\n\nExamples of Usage\n^^^^^^^^^^^^^^^^^\n\nRead packets from one pcap file and write them to another:\n\n.. code-block:: console\n\n $RTE_TARGET/app/testpmd -c '0xf' -n 4 --vdev 'eth_pcap0,rx_pcap=/path/to/ file_rx.pcap,tx_pcap=/path/to/file_tx.pcap' -- --port-topology=chained\n\nRead packets from a network interface and write them to a pcap file:\n\n.. code-block:: console\n\n $RTE_TARGET/app/testpmd -c '0xf' -n 4 --vdev 'eth_pcap0,rx_iface=eth0,tx_pcap=/path/to/file_tx.pcap' -- --port-topology=chained\n\nRead packets from a pcap file and write them to a network interface:\n\n.. code-block:: console\n\n $RTE_TARGET/app/testpmd -c '0xf' -n 4 --vdev 'eth_pcap0,rx_pcap=/path/to/ file_rx.pcap,tx_iface=eth1' -- --port-topology=chained\n\nForward packets through two network interfaces:\n\n.. code-block:: console\n\n $RTE_TARGET/app/testpmd -c '0xf' -n 4 --vdev 'eth_pcap0,iface=eth0' --vdev='eth_pcap1;iface=eth1'\n\nUsing libpcap-based PMD with the testpmd Application\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nOne of the first things that testpmd does before starting to forward packets is to flush the RX streams\nby reading the first 512 packets on every RX stream and discarding them.\nWhen using a libpcap-based PMD this behavior can be turned off using the following command line option:\n\n.. code-block:: console\n\n --no-flush-rx\n\nIt is also available in the runtime command line:\n\n.. code-block:: console\n\n set flush_rx on/off\n\nIt is useful for the case where the rx_pcap is being used and no packets are meant to be discarded.\nOtherwise, the first 512 packets from the input pcap file will be discarded by the RX flushing operation.\n\n.. code-block:: console\n\n $RTE_TARGET/app/testpmd -c '0xf' -n 4 --vdev 'eth_pcap0,rx_pcap=/path/to/ file_rx.pcap,tx_pcap=/path/to/file_tx.pcap' -- --port-topology=chained --no-flush-rx\n\n\nRings-based PMD\n~~~~~~~~~~~~~~~\n\nTo run a DPDK application on a machine without any Ethernet devices, a pair of ring-based rte_ethdevs can be used as below.\nThe device names passed to the --vdev option must start with eth_ring and take no additional parameters.\nMultiple devices may be specified, separated by commas.\n\n.. code-block:: console\n\n ./testpmd -c E -n 4 --vdev=eth_ring0 --vdev=eth_ring1 -- -i\n EAL: Detected lcore 1 as core 1 on socket 0\n ...\n\n Interactive-mode selected\n Configuring Port 0 (socket 0)\n Configuring Port 1 (socket 0)\n Checking link statuses...\n Port 0 Link Up - speed 10000 Mbps - full-duplex\n Port 1 Link Up - speed 10000 Mbps - full-duplex\n Done\n\n testpmd> start tx_first\n io packet forwarding - CRC stripping disabled - packets/burst=16\n nb forwarding cores=1 - nb forwarding ports=2\n RX queues=1 - RX desc=128 - RX free threshold=0\n RX threshold registers: pthresh=8 hthresh=8 wthresh=4\n TX queues=1 - TX desc=512 - TX free threshold=0\n TX threshold registers: pthresh=36 hthresh=0 wthresh=0\n TX RS bit threshold=0 - TXQ flags=0x0\n\n testpmd> stop\n Telling cores to stop...\n Waiting for lcores to finish...\n\n.. image:: img/forward_stats.*\n\n.. code-block:: console\n\n +++++++++++++++ Accumulated forward statistics for allports++++++++++\n RX-packets: 462384736 RX-dropped: 0 RX-total: 462384736\n TX-packets: 462384768 TX-dropped: 0 TX-total: 462384768\n +++++++++++++++++++++++++++++++++++++++++++++++++++++\n\n Done.\n\n\nUsing the Poll Mode Driver from an Application\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nBoth drivers can provide similar APIs to allow the user to create a PMD, that is,\nrte_ethdev structure, instances at run-time in the end-application,\nfor example, using rte_eth_from_rings() or rte_eth_from_pcaps() APIs.\nFor the rings- based PMD, this functionality could be used, for example,\nto allow data exchange between cores using rings to be done in exactly the\nsame way as sending or receiving packets from an Ethernet device.\nFor the libpcap-based PMD, it allows an application to open one or more pcap files\nand use these as a source of packet input to the application.\n\nUsage Examples\n^^^^^^^^^^^^^^\n\nTo create two pseudo-Ethernet ports where all traffic sent to a port is looped back\nfor reception on the same port (error handling omitted for clarity):\n\n.. code-block:: c\n\n struct rte_ring *r1, *r2;\n int port1, port2;\n\n r1 = rte_ring_create(\"R1\", 256, SOCKET0,RING_F_SP_ENQ|RING_F_SC_DEQ);\n r2 = rte_ring_create(\"R2\", 256, SOCKET0, RING_F_SP_ENQ|RING_F_SC_DEQ);\n\n /* create an ethdev where RX and TX are done to/from r1, and * another from r2 */\n\n port1 = rte_eth_from_rings(r1, 1, r1, 1, SOCKET0);\n port2 = rte_eth_from_rings(r2, 1, r2, 1, SOCKET0);\n\n\nTo create two pseudo-Ethernet ports where the traffic is switched between them,\nthat is, traffic sent to port 1 is read back from port 2 and vice-versa,\nthe final two lines could be changed as below:\n\n.. code-block:: c\n\n port1 = rte_eth_from_rings(r1, 1, r2, 1, SOCKET0);\n port2 = rte_eth_from_rings(r2, 1, r1, 1, SOCKET0);\n\nThis type of configuration could be useful in a pipeline model, for example,\nwhere one may want to have inter-core communication using pseudo Ethernet devices rather than raw rings,\nfor reasons of API consistency.\n\nEnqueuing and dequeuing items from an rte_ring using the rings-based PMD may be slower than using the native rings API.\nThis is because DPDK Ethernet drivers make use of function pointers to call the appropriate enqueue or dequeue functions,\nwhile the rte_ring specific functions are direct function calls in the code and are often inlined by the compiler.\n\n Once an ethdev has been created, for either a ring or a pcap-based PMD,\n it should be configured and started in the same way as a regular Ethernet device, that is,\n by calling rte_eth_dev_configure() to set the number of receive and transmit queues,\n then calling rte_eth_rx_queue_setup() / tx_queue_setup() for each of those queues and\n finally calling rte_eth_dev_start() to allow transmission and reception of packets to begin.\n" }, { "path": "doc/guides/nics/virtio.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nPoll Mode Driver for Emulated Virtio NIC\n========================================\n\nVirtio is a para-virtualization framework initiated by IBM, and supported by KVM hypervisor.\nIn the Data Plane Development Kit (DPDK),\nwe provide a virtio Poll Mode Driver (PMD) as a software solution, comparing to SRIOV hardware solution,\nfor fast guest VM to guest VM communication and guest VM to host communication.\n\nVhost is a kernel acceleration module for virtio qemu backend.\nThe DPDK extends kni to support vhost raw socket interface,\nwhich enables vhost to directly read/ write packets from/to a physical port.\nWith this enhancement, virtio could achieve quite promising performance.\n\nIn future release, we will also make enhancement to vhost backend,\nreleasing peak performance of virtio PMD driver.\n\nFor basic qemu-KVM installation and other Intel EM poll mode driver in guest VM,\nplease refer to Chapter \"Driver for VM Emulated Devices\".\n\nIn this chapter, we will demonstrate usage of virtio PMD driver with two backends,\nstandard qemu vhost back end and vhost kni back end.\n\nVirtio Implementation in DPDK\n-----------------------------\n\nFor details about the virtio spec, refer to Virtio PCI Card Specification written by Rusty Russell.\n\nAs a PMD, virtio provides packet reception and transmission callbacks virtio_recv_pkts and virtio_xmit_pkts.\n\nIn virtio_recv_pkts, index in range [vq->vq_used_cons_idx , vq->vq_ring.used->idx) in vring is available for virtio to burst out.\n\nIn virtio_xmit_pkts, same index range in vring is available for virtio to clean.\nVirtio will enqueue to be transmitted packets into vring, advance the vq->vq_ring.avail->idx,\nand then notify the host back end if necessary.\n\nFeatures and Limitations of virtio PMD\n--------------------------------------\n\nIn this release, the virtio PMD driver provides the basic functionality of packet reception and transmission.\n\n* It supports merge-able buffers per packet when receiving packets and scattered buffer per packet\n when transmitting packets. The packet size supported is from 64 to 1518.\n\n* It supports multicast packets and promiscuous mode.\n\n* The descriptor number for the RX/TX queue is hard-coded to be 256 by qemu.\n If given a different descriptor number by the upper application,\n the virtio PMD generates a warning and fall back to the hard-coded value.\n\n* Features of mac/vlan filter are supported, negotiation with vhost/backend are needed to support them.\n When backend can't support vlan filter, virtio app on guest should disable vlan filter to make sure\n the virtio port is configured correctly. E.g. specify '--disable-hw-vlan' in testpmd command line.\n\n* RTE_PKTMBUF_HEADROOM should be defined larger than sizeof(struct virtio_net_hdr), which is 10 bytes.\n\n* Virtio does not support runtime configuration.\n\n* Virtio supports Link State interrupt.\n\n* Virtio supports software vlan stripping and inserting.\n\n* Virtio supports using port IO to get PCI resource when uio/igb_uio module is not available.\n\nPrerequisites\n-------------\n\nThe following prerequisites apply:\n\n* In the BIOS, turn VT-x and VT-d on\n\n* Linux kernel with KVM module; vhost module loaded and ioeventfd supported.\n Qemu standard backend without vhost support isn't tested, and probably isn't supported.\n\nVirtio with kni vhost Back End\n------------------------------\n\nThis section demonstrates kni vhost back end example setup for Phy-VM Communication.\n\n.. _figure_host_vm_comms:\n\n.. figure:: img/host_vm_comms.*\n\n Host2VM Communication Example Using kni vhost Back End\n\n\nHost2VM communication example\n\n#. Load the kni kernel module:\n\n .. code-block:: console\n\n insmod rte_kni.ko\n\n Other basic DPDK preparations like hugepage enabling, uio port binding are not listed here.\n Please refer to the *DPDK Getting Started Guide* for detailed instructions.\n\n#. Launch the kni user application:\n\n .. code-block:: console\n\n examples/kni/build/app/kni -c 0xf -n 4 -- -p 0x1 -P --config=\"(0,1,3)\"\n\n This command generates one network device vEth0 for physical port.\n If specify more physical ports, the generated network device will be vEth1, vEth2, and so on.\n\n For each physical port, kni creates two user threads.\n One thread loops to fetch packets from the physical NIC port into the kni receive queue.\n The other user thread loops to send packets in the kni transmit queue.\n\n For each physical port, kni also creates a kernel thread that retrieves packets from the kni receive queue,\n place them onto kni's raw socket's queue and wake up the vhost kernel thread to exchange packets with the virtio virt queue.\n\n For more details about kni, please refer to Chapter 24 \"Kernel NIC Interface\".\n\n#. Enable the kni raw socket functionality for the specified physical NIC port,\n get the generated file descriptor and set it in the qemu command line parameter.\n Always remember to set ioeventfd_on and vhost_on.\n\n Example:\n\n .. code-block:: console\n\n echo 1 > /sys/class/net/vEth0/sock_en\n fd=`cat /sys/class/net/vEth0/sock_fd`\n exec qemu-system-x86_64 -enable-kvm -cpu host \\\n -m 2048 -smp 4 -name dpdk-test1-vm1 \\\n -drive file=/data/DPDKVMS/dpdk-vm.img \\\n -netdev tap, fd=$fd,id=mynet_kni, script=no,vhost=on \\\n -device virtio-net-pci,netdev=mynet_kni,bus=pci.0,addr=0x3,ioeventfd=on \\\n -vnc:1 -daemonize\n\n In the above example, virtio port 0 in the guest VM will be associated with vEth0, which in turns corresponds to a physical port,\n which means received packets come from vEth0, and transmitted packets is sent to vEth0.\n\n#. In the guest, bind the virtio device to the uio_pci_generic kernel module and start the forwarding application.\n When the virtio port in guest bursts rx, it is getting packets from the raw socket's receive queue.\n When the virtio port bursts tx, it is sending packet to the tx_q.\n\n .. code-block:: console\n\n modprobe uio\n echo 512 > /sys/devices/system/node/node0/hugepages/hugepages-2048kB/nr_hugepages\n modprobe uio_pci_generic\n python tools/dpdk_nic_bind.py -b uio_pci_generic 00:03.0\n\n We use testpmd as the forwarding application in this example.\n\n .. figure:: img/console.*\n\n Running testpmd\n\n#. Use IXIA packet generator to inject a packet stream into the KNI physical port.\n\n The packet reception and transmission flow path is:\n\n IXIA packet generator->82599 PF->KNI rx queue->KNI raw socket queue->Guest VM virtio port 0 rx burst->Guest VM virtio port 0 tx burst-> KNI tx queue->82599 PF-> IXIA packet generator\n\nVirtio with qemu virtio Back End\n--------------------------------\n\n.. _figure_host_vm_comms_qemu:\n\n.. figure:: img/host_vm_comms_qemu.*\n\n Host2VM Communication Example Using qemu vhost Back End\n\n\n.. code-block:: console\n\n qemu-system-x86_64 -enable-kvm -cpu host -m 2048 -smp 2 -mem-path /dev/\n hugepages -mem-prealloc\n -drive file=/data/DPDKVMS/dpdk-vm1\n -netdev tap,id=vm1_p1,ifname=tap0,script=no,vhost=on\n -device virtio-net-pci,netdev=vm1_p1,bus=pci.0,addr=0x3,ioeventfd=on\n -device pci-assign,host=04:10.1 \\\n\nIn this example, the packet reception flow path is:\n\n IXIA packet generator->82599 PF->Linux Bridge->TAP0's socket queue-> Guest VM virtio port 0 rx burst-> Guest VM 82599 VF port1 tx burst-> IXIA packet generator\n\nThe packet transmission flow is:\n\n IXIA packet generator-> Guest VM 82599 VF port1 rx burst-> Guest VM virtio port 0 tx burst-> tap -> Linux Bridge->82599 PF-> IXIA packet generator\n" }, { "path": "doc/guides/nics/vmxnet3.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nPoll Mode Driver for Paravirtual VMXNET3 NIC\n============================================\n\nThe VMXNET3 adapter is the next generation of a paravirtualized NIC, introduced by VMware* ESXi.\nIt is designed for performance and is not related to VMXNET or VMXENET2.\nIt offers all the features available in VMXNET2, and adds several new features such as,\nmulti-queue support (also known as Receive Side Scaling, RSS),\nIPv6 offloads, and MSI/MSI-X interrupt delivery.\nBecause operating system vendors do not provide built-in drivers for this card,\nVMware Tools must be installed to have a driver for the VMXNET3 network adapter available.\nOne can use the same device in a DPDK application with VMXNET3 PMD introduced in DPDK API.\n\nCurrently, the driver provides basic support for using the device in a DPDK application running on a guest OS.\nOptimization is needed on the backend, that is, the VMware* ESXi vmkernel switch, to achieve optimal performance end-to-end.\n\nIn this chapter, two setups with the use of the VMXNET3 PMD are demonstrated:\n\n#. Vmxnet3 with a native NIC connected to a vSwitch\n\n#. Vmxnet3 chaining VMs connected to a vSwitch\n\nVMXNET3 Implementation in the DPDK\n----------------------------------\n\nFor details on the VMXNET3 device, refer to the VMXNET3 driver's vmxnet3 directory and support manual from VMware*.\n\nFor performance details, refer to the following link from VMware:\n\n`http://www.vmware.com/pdf/vsp_4_vmxnet3_perf.pdf `_\n\nAs a PMD, the VMXNET3 driver provides the packet reception and transmission callbacks, vmxnet3_recv_pkts and vmxnet3_xmit_pkts.\nIt does not support scattered packet reception as part of vmxnet3_recv_pkts and vmxnet3_xmit_pkts.\nAlso, it does not support scattered packet reception as part of the device operations supported.\n\nThe VMXNET3 PMD handles all the packet buffer memory allocation and resides in guest address space\nand it is solely responsible to free that memory when not needed.\nThe packet buffers and features to be supported are made available to hypervisor via VMXNET3 PCI configuration space BARs.\nDuring RX/TX, the packet buffers are exchanged by their GPAs,\nand the hypervisor loads the buffers with packets in the RX case and sends packets to vSwitch in the TX case.\n\nThe VMXNET3 PMD is compiled with vmxnet3 device headers.\nThe interface is similar to that of the other PMDs available in the DPDK API.\nThe driver pre-allocates the packet buffers and loads the command ring descriptors in advance.\nThe hypervisor fills those packet buffers on packet arrival and write completion ring descriptors,\nwhich are eventually pulled by the PMD.\nAfter reception, the DPDK application frees the descriptors and loads new packet buffers for the coming packets.\nThe interrupts are disabled and there is no notification required.\nThis keeps performance up on the RX side, even though the device provides a notification feature.\n\nIn the transmit routine, the DPDK application fills packet buffer pointers in the descriptors of the command ring\nand notifies the hypervisor.\nIn response the hypervisor takes packets and passes them to the vSwitch. It writes into the completion descriptors ring.\nThe rings are read by the PMD in the next transmit routine call and the buffers and descriptors are freed from memory.\n\nFeatures and Limitations of VMXNET3 PMD\n---------------------------------------\n\nIn release 1.6.0, the VMXNET3 PMD provides the basic functionality of packet reception and transmission.\nThere are several options available for filtering packets at VMXNET3 device level including:\n\n#. MAC Address based filtering:\n\n * Unicast, Broadcast, All Multicast modes - SUPPORTED BY DEFAULT\n\n * Multicast with Multicast Filter table - NOT SUPPORTED\n\n * Promiscuous mode - SUPPORTED\n\n * RSS based load balancing between queues - SUPPORTED\n\n#. VLAN filtering:\n\n * VLAN tag based filtering without load balancing - SUPPORTED\n\n.. note::\n\n\n * Release 1.6.0 does not support separate headers and body receive cmd_ring and hence,\n multiple segment buffers are not supported.\n Only cmd_ring_0 is used for packet buffers, one for each descriptor.\n\n * Receive and transmit of scattered packets is not supported.\n\n * Multicast with Multicast Filter table is not supported.\n\nPrerequisites\n-------------\n\nThe following prerequisites apply:\n\n* Before starting a VM, a VMXNET3 interface to a VM through VMware vSphere Client must be assigned.\n This is shown in the figure below.\n\n.. _figure_vmxnet3_int:\n\n.. figure:: img/vmxnet3_int.*\n\n Assigning a VMXNET3 interface to a VM using VMware vSphere Client\n\n.. note::\n\n Depending on the Virtual Machine type, the VMware vSphere Client shows Ethernet adaptors while adding an Ethernet device.\n Ensure that the VM type used offers a VMXNET3 device. Refer to the VMware documentation for a listed of VMs.\n\n.. note::\n\n Follow the *DPDK Getting Started Guide* to setup the basic DPDK environment.\n\n.. note::\n\n Follow the *DPDK Sample Application's User Guide*, L2 Forwarding/L3 Forwarding and\n TestPMD for instructions on how to run a DPDK application using an assigned VMXNET3 device.\n\nVMXNET3 with a Native NIC Connected to a vSwitch\n------------------------------------------------\n\nThis section describes an example setup for Phy-vSwitch-VM-Phy communication.\n\n.. _figure_vswitch_vm:\n\n.. figure:: img/vswitch_vm.*\n\n VMXNET3 with a Native NIC Connected to a vSwitch\n\n.. note::\n\n Other instructions on preparing to use DPDK such as, hugepage enabling, uio port binding are not listed here.\n Please refer to *DPDK Getting Started Guide and DPDK Sample Application's User Guide* for detailed instructions.\n\nThe packet reception and transmission flow path is::\n\n Packet generator -> 82576\n -> VMware ESXi vSwitch\n -> VMXNET3 device\n -> Guest VM VMXNET3 port 0 rx burst\n -> Guest VM 82599 VF port 0 tx burst\n -> 82599 VF\n -> Packet generator\n\nVMXNET3 Chaining VMs Connected to a vSwitch\n-------------------------------------------\n\nThe following figure shows an example VM-to-VM communication over a Phy-VM-vSwitch-VM-Phy communication channel.\n\n.. _figure_vm_vm_comms:\n\n.. figure:: img/vm_vm_comms.*\n\n VMXNET3 Chaining VMs Connected to a vSwitch\n\n.. note::\n\n When using the L2 Forwarding or L3 Forwarding applications,\n a destination MAC address needs to be written in packets to hit the other VM's VMXNET3 interface.\n\nIn this example, the packet flow path is::\n\n Packet generator -> 82599 VF\n -> Guest VM 82599 port 0 rx burst\n -> Guest VM VMXNET3 port 1 tx burst\n -> VMXNET3 device\n -> VMware ESXi vSwitch\n -> VMXNET3 device\n -> Guest VM VMXNET3 port 0 rx burst\n -> Guest VM 82599 VF port 1 tx burst\n -> 82599 VF\n -> Packet generator\n" }, { "path": "doc/guides/prog_guide/build_app.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Building_Your_Own_Application:\n\nBuilding Your Own Application\n=============================\n\nCompiling a Sample Application in the Development Kit Directory\n---------------------------------------------------------------\n\nWhen compiling a sample application (for example, hello world), the following variables must be exported:\nRTE_SDK and RTE_TARGET.\n\n.. code-block:: console\n\n ~/DPDK$ cd examples/helloworld/\n ~/DPDK/examples/helloworld$ export RTE_SDK=/home/user/DPDK\n ~/DPDK/examples/helloworld$ export RTE_TARGET=x86_64-native-linuxapp-gcc\n ~/DPDK/examples/helloworld$ make\n CC main.o\n LD helloworld\n INSTALL-APP helloworld\n INSTALL-MAP helloworld.map\n\nThe binary is generated in the build directory by default:\n\n.. code-block:: console\n\n ~/DPDK/examples/helloworld$ ls build/app\n helloworld helloworld.map\n\nBuild Your Own Application Outside the Development Kit\n------------------------------------------------------\n\nThe sample application (Hello World) can be duplicated in a new directory as a starting point for your development:\n\n.. code-block:: console\n\n ~$ cp -r DPDK/examples/helloworld my_rte_app\n ~$ cd my_rte_app/\n ~/my_rte_app$ export RTE_SDK=/home/user/DPDK\n ~/my_rte_app$ export RTE_TARGET=x86_64-native-linuxapp-gcc\n ~/my_rte_app$ make\n CC main.o\n LD helloworld\n INSTALL-APP helloworld\n INSTALL-MAP helloworld.map\n\nCustomizing Makefiles\n---------------------\n\nApplication Makefile\n~~~~~~~~~~~~~~~~~~~~\n\nThe default makefile provided with the Hello World sample application is a good starting point. It includes:\n\n* $(RTE_SDK)/mk/rte.vars.mk at the beginning\n\n* $(RTE_SDK)/mk/rte.extapp.mk at the end\n\nThe user must define several variables:\n\n* APP: Contains the name of the application.\n\n* SRCS-y: List of source files (\\*.c, \\*.S).\n\nLibrary Makefile\n~~~~~~~~~~~~~~~~\n\nIt is also possible to build a library in the same way:\n\n* Include $(RTE_SDK)/mk/rte.vars.mk at the beginning.\n\n* Include $(RTE_SDK)/mk/rte.extlib.mk at the end.\n\nThe only difference is that APP should be replaced by LIB, which contains the name of the library. For example, libfoo.a.\n\nCustomize Makefile Actions\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSome variables can be defined to customize Makefile actions. The most common are listed below. Refer to\n:ref:`Makefile Description ` section in\n:ref:`Development Kit Build System `\n\nchapter for details.\n\n* VPATH: The path list where the build system will search for sources. By default,\n RTE_SRCDIR will be included in VPATH.\n\n* CFLAGS_my_file.o: The specific flags to add for C compilation of my_file.c.\n\n* CFLAGS: The flags to use for C compilation.\n\n* LDFLAGS: The flags to use for linking.\n\n* CPPFLAGS: The flags to use to provide flags to the C preprocessor (only useful when assembling .S files)\n\n* LDLIBS: A list of libraries to link with (for example, -L /path/to/libfoo - lfoo)\n" }, { "path": "doc/guides/prog_guide/dev_kit_build_system.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Development_Kit_Build_System:\n\nDevelopment Kit Build System\n============================\n\nThe DPDK requires a build system for compilation activities and so on.\nThis section describes the constraints and the mechanisms used in the DPDK framework.\n\nThere are two use-cases for the framework:\n\n* Compilation of the DPDK libraries and sample applications;\n the framework generates specific binary libraries,\n include files and sample applications\n\n* Compilation of an external application or library, using an installed binary DPDK\n\nBuilding the Development Kit Binary\n-----------------------------------\n\nThe following provides details on how to build the DPDK binary.\n\nBuild Directory Concept\n~~~~~~~~~~~~~~~~~~~~~~~\n\nAfter installation, a build directory structure is created.\nEach build directory contains include files, libraries, and applications:\n\n.. code-block:: console\n\n ~/DPDK$ ls\n app MAINTAINERS\n config Makefile\n COPYRIGHT mk\n doc scripts\n examples lib\n tools x86_64-native-linuxapp-gcc\n x86_64-native-linuxapp-icc i686-native-linuxapp-gcc\n i686-native-linuxapp-icc\n\n ...\n ~/DEV/DPDK$ ls i686-native-linuxapp-gcc\n\n app build hostapp include kmod lib Makefile\n\n\n ~/DEV/DPDK$ ls i686-native-linuxapp-gcc/app/\n cmdline_test dump_cfg test testpmd\n cmdline_test.map dump_cfg.map test.map\n\t testpmd.map\n\n\n ~/DEV/DPDK$ ls i686-native-linuxapp-gcc/lib/\n\n libethdev.a librte_hash.a librte_mbuf.a librte_pmd_ixgbe.a\n\n librte_cmdline.a librte_lpm.a librte_mempool.a librte_ring.a\n\n librte_eal.a librte_malloc.a librte_pmd_e1000.a librte_timer.a\n\n\n ~/DEV/DPDK$ ls i686-native-linuxapp-gcc/include/\n arch rte_cpuflags.h rte_memcpy.h\n cmdline_cirbuf.h rte_cycles.h rte_memory.h\n cmdline.h rte_debug.h rte_mempool.h\n cmdline_parse_etheraddr.h rte_eal.h rte_memzone.h\n cmdline_parse.h rte_errno.h rte_pci_dev_ids.h\n cmdline_parse_ipaddr.h rte_ethdev.h rte_pci.h\n cmdline_parse_num.h rte_ether.h rte_per_lcore.h\n cmdline_parse_portlist.h rte_fbk_hash.h rte_prefetch.h\n cmdline_parse_string.h rte_hash_crc.h rte_random.h\n cmdline_rdline.h rte_hash.h rte_ring.h\n cmdline_socket.h rte_interrupts.h rte_rwlock.h\n cmdline_vt100.h rte_ip.h rte_sctp.h\n exec-env rte_jhash.h rte_spinlock.h\n rte_alarm.h rte_launch.h rte_string_fns.h\n rte_atomic.h rte_lcore.h rte_tailq.h\n rte_branch_prediction.h rte_log.h rte_tcp.h\n rte_byteorder.h rte_lpm.h rte_timer.h\n rte_common.h rte_malloc.h rte_udp.h\n rte_config.h rte_mbuf.h\n\n\nA build directory is specific to a configuration that includes architecture + execution environment + toolchain.\nIt is possible to have several build directories sharing the same sources with different configurations.\n\nFor instance, to create a new build directory called my_sdk_build_dir using the default configuration template config/defconfig_x86_64-linuxapp,\nwe use:\n\n.. code-block:: console\n\n cd ${RTE_SDK}\n make config T=x86_64-native-linuxapp-gcc O=my_sdk_build_dir\n\nThis creates a new my_sdk_build_dir directory. After that, we can compile by doing:\n\n.. code-block:: console\n\n cd my_sdk_build_dir\n make\n\nwhich is equivalent to:\n\n.. code-block:: console\n\n make O=my_sdk_build_dir\n\nThe content of the my_sdk_build_dir is then:\n\n::\n\n -- .config # used configuration\n\n -- Makefile # wrapper that calls head Makefile\n # with $PWD as build directory\n\n\n -- build #All temporary files used during build\n +--app # process, including . o, .d, and .cmd files.\n | +-- test # For libraries, we have the .a file.\n | +-- test.o # For applications, we have the elf file.\n | `-- ...\n +-- lib\n +-- librte_eal\n | `-- ...\n +-- librte_mempool\n | +-- mempool-file1.o\n | +-- .mempool-file1.o.cmd\n | +-- .mempool-file1.o.d\n | +-- mempool-file2.o\n | +-- .mempool-file2.o.cmd\n | +-- .mempool-file2.o.d\n | `-- mempool.a\n `-- ...\n\n -- include # All include files installed by libraries\n +-- librte_mempool.h # and applications are located in this\n +-- rte_eal.h # directory. The installed files can depend\n +-- rte_spinlock.h # on configuration if needed (environment,\n +-- rte_atomic.h # architecture, ..)\n `-- \\*.h ...\n\n -- lib # all compiled libraries are copied in this\n +-- librte_eal.a # directory\n +-- librte_mempool.a\n `-- \\*.a ...\n\n -- app # All compiled applications are installed\n + --test # here. It includes the binary in elf format\n\nRefer to\n:ref:`Development Kit Root Makefile Help `\nfor details about make commands that can be used from the root of DPDK.\n\nBuilding External Applications\n------------------------------\n\nSince DPDK is in essence a development kit, the first objective of end users will be to create an application using this SDK.\nTo compile an application, the user must set the RTE_SDK and RTE_TARGET environment variables.\n\n.. code-block:: console\n\n export RTE_SDK=/opt/DPDK\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n cd /path/to/my_app\n\nFor a new application, the user must create their own Makefile that includes some .mk files, such as\n${RTE_SDK}/mk/rte.vars.mk, and ${RTE_SDK}/mk/ rte.app.mk.\nThis is described in\n:ref:`Building Your Own Application `.\n\nDepending on the chosen target (architecture, machine, executive environment, toolchain) defined in the Makefile or as an environment variable,\nthe applications and libraries will compile using the appropriate .h files and will link with the appropriate .a files.\nThese files are located in ${RTE_SDK}/arch-machine-execenv-toolchain, which is referenced internally by ${RTE_BIN_SDK}.\n\nTo compile their application, the user just has to call make.\nThe compilation result will be located in /path/to/my_app/build directory.\n\nSample applications are provided in the examples directory.\n\n.. _Makefile_Description:\n\nMakefile Description\n--------------------\n\nGeneral Rules For DPDK Makefiles\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nIn the DPDK, Makefiles always follow the same scheme:\n\n#. Include $(RTE_SDK)/mk/rte.vars.mk at the beginning.\n\n#. Define specific variables for RTE build system.\n\n#. Include a specific $(RTE_SDK)/mk/rte.XYZ.mk, where XYZ can be app, lib, extapp, extlib, obj, gnuconfigure,\n and so on, depending on what kind of object you want to build.\n :ref:`See Makefile Types ` below.\n\n#. Include user-defined rules and variables.\n\n The following is a very simple example of an external application Makefile:\n\n .. code-block:: make\n\n include $(RTE_SDK)/mk/rte.vars.mk\n\n # binary name\n APP = helloworld\n\n # all source are stored in SRCS-y\n SRCS-y := main.c\n\n CFLAGS += -O3\n CFLAGS += $(WERROR_FLAGS)\n\n include $(RTE_SDK)/mk/rte.extapp.mk\n\n.. _Makefile_Types:\n\nMakefile Types\n~~~~~~~~~~~~~~\n\nDepending on the .mk file which is included at the end of the user Makefile, the Makefile will have a different role.\nNote that it is not possible to build a library and an application in the same Makefile.\nFor that, the user must create two separate Makefiles, possibly in two different directories.\n\nIn any case, the rte.vars.mk file must be included in the user Makefile as soon as possible.\n\nApplication\n^^^^^^^^^^^\n\nThese Makefiles generate a binary application.\n\n* rte.app.mk: Application in the development kit framework\n\n* rte.extapp.mk: External application\n\n* rte.hostapp.mk: Host application in the development kit framework\n\nLibrary\n^^^^^^^\n\nGenerate a .a library.\n\n* rte.lib.mk: Library in the development kit framework\n\n* rte.extlib.mk: external library\n\n* rte.hostlib.mk: host library in the development kit framework\n\nInstall\n^^^^^^^\n\n* rte.install.mk: Does not build anything, it is only used to create links or copy files to the installation directory.\n This is useful for including files in the development kit framework.\n\nKernel Module\n^^^^^^^^^^^^^\n\n* rte.module.mk: Build a kernel module in the development kit framework.\n\nObjects\n^^^^^^^\n\n* rte.obj.mk: Object aggregation (merge several .o in one) in the development kit framework.\n\n* rte.extobj.mk: Object aggregation (merge several .o in one) outside the development kit framework.\n\nMisc\n^^^^\n\n* rte.doc.mk: Documentation in the development kit framework\n\n* rte.gnuconfigure.mk: Build an application that is configure-based.\n\n* rte.subdir.mk: Build several directories in the development kit framework.\n\n.. _Useful_Variables_Provided_by_the_Build_System:\n\nUseful Variables Provided by the Build System\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n* RTE_SDK: The absolute path to the DPDK sources.\n When compiling the development kit, this variable is automatically set by the framework.\n It has to be defined by the user as an environment variable if compiling an external application.\n\n* RTE_SRCDIR: The path to the root of the sources. When compiling the development kit, RTE_SRCDIR = RTE_SDK.\n When compiling an external application, the variable points to the root of external application sources.\n\n* RTE_OUTPUT: The path to which output files are written.\n Typically, it is $(RTE_SRCDIR)/build, but it can be overridden by the O= option in the make command line.\n\n* RTE_TARGET: A string identifying the target for which we are building.\n The format is arch-machine-execenv-toolchain.\n When compiling the SDK, the target is deduced by the build system from the configuration (.config).\n When building an external application, it must be specified by the user in the Makefile or as an environment variable.\n\n* RTE_SDK_BIN: References $(RTE_SDK)/$(RTE_TARGET).\n\n* RTE_ARCH: Defines the architecture (i686, x86_64).\n It is the same value as CONFIG_RTE_ARCH but without the double-quotes around the string.\n\n* RTE_MACHINE: Defines the machine.\n It is the same value as CONFIG_RTE_MACHINE but without the double-quotes around the string.\n\n* RTE_TOOLCHAIN: Defines the toolchain (gcc , icc).\n It is the same value as CONFIG_RTE_TOOLCHAIN but without the double-quotes around the string.\n\n* RTE_EXEC_ENV: Defines the executive environment (linuxapp).\n It is the same value as CONFIG_RTE_EXEC_ENV but without the double-quotes around the string.\n\n* RTE_KERNELDIR: This variable contains the absolute path to the kernel sources that will be used to compile the kernel modules.\n The kernel headers must be the same as the ones that will be used on the target machine (the machine that will run the application).\n By default, the variable is set to /lib/modules/$(shell uname -r)/build,\n which is correct when the target machine is also the build machine.\n\nVariables that Can be Set/Overridden in a Makefile Only\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n* VPATH: The path list that the build system will search for sources. By default, RTE_SRCDIR will be included in VPATH.\n\n* CFLAGS: Flags to use for C compilation. The user should use += to append data in this variable.\n\n* LDFLAGS: Flags to use for linking. The user should use += to append data in this variable.\n\n* ASFLAGS: Flags to use for assembly. The user should use += to append data in this variable.\n\n* CPPFLAGS: Flags to use to give flags to C preprocessor (only useful when assembling .S files).\n The user should use += to append data in this variable.\n\n* LDLIBS: In an application, the list of libraries to link with (for example, -L /path/to/libfoo -lfoo ).\n The user should use += to append data in this variable.\n\n* SRC-y: A list of source files (.c, .S, or .o if the source is a binary) in case of application, library or object Makefiles.\n The sources must be available from VPATH.\n\n* INSTALL-y-$(INSTPATH): A list of files to be installed in $(INSTPATH).\n The files must be available from VPATH and will be copied in $(RTE_OUTPUT)/$(INSTPATH). Can be used in almost any RTE Makefile.\n\n* SYMLINK-y-$(INSTPATH): A list of files to be installed in $(INSTPATH).\n The files must be available from VPATH and will be linked (symbolically) in $(RTE_OUTPUT)/$(INSTPATH).\n This variable can be used in almost any DPDK Makefile.\n\n* PREBUILD: A list of prerequisite actions to be taken before building. The user should use += to append data in this variable.\n\n* POSTBUILD: A list of actions to be taken after the main build. The user should use += to append data in this variable.\n\n* PREINSTALL: A list of prerequisite actions to be taken before installing. The user should use += to append data in this variable.\n\n* POSTINSTALL: A list of actions to be taken after installing. The user should use += to append data in this variable.\n\n* PRECLEAN: A list of prerequisite actions to be taken before cleaning. The user should use += to append data in this variable.\n\n* POSTCLEAN: A list of actions to be taken after cleaning. The user should use += to append data in this variable.\n\n* DEPDIR-y: Only used in the development kit framework to specify if the build of the current directory depends on build of another one.\n This is needed to support parallel builds correctly.\n\nVariables that can be Set/Overridden by the User on the Command Line Only\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSome variables can be used to configure the build system behavior. They are documented in\n:ref:`Development Kit Root Makefile Help ` and\n:ref:`External Application/Library Makefile Help `\n\n * WERROR_CFLAGS: By default, this is set to a specific value that depends on the compiler.\n Users are encouraged to use this variable as follows:\n\n CFLAGS += $(WERROR_CFLAGS)\n\nThis avoids the use of different cases depending on the compiler (icc or gcc).\nAlso, this variable can be overridden from the command line, which allows bypassing of the flags for testing purposes.\n\nVariables that Can be Set/Overridden by the User in a Makefile or Command Line\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n* CFLAGS_my_file.o: Specific flags to add for C compilation of my_file.c.\n\n* LDFLAGS_my_app: Specific flags to add when linking my_app.\n\n* EXTRA_CFLAGS: The content of this variable is appended after CFLAGS when compiling.\n\n* EXTRA_LDFLAGS: The content of this variable is appended after LDFLAGS when linking.\n\n* EXTRA_LDLIBS: The content of this variable is appended after LDLIBS when linking.\n\n* EXTRA_ASFLAGS: The content of this variable is appended after ASFLAGS when assembling.\n\n* EXTRA_CPPFLAGS: The content of this variable is appended after CPPFLAGS when using a C preprocessor on assembly files.\n" }, { "path": "doc/guides/prog_guide/dev_kit_root_make_help.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Development_Kit_Root_Makefile_Help:\n\nDevelopment Kit Root Makefile Help\n==================================\n\nThe DPDK provides a root level Makefile with targets for configuration, building, cleaning, testing, installation and others.\nThese targets are explained in the following sections.\n\nConfiguration Targets\n---------------------\n\nThe configuration target requires the name of the target, which is specified using T=mytarget and it is mandatory.\nThe list of available targets are in $(RTE_SDK)/config (remove the defconfig _ prefix).\n\nConfiguration targets also support the specification of the name of the output directory, using O=mybuilddir.\nThis is an optional parameter, the default output directory is build.\n\n* Config\n\n This will create a build directory, and generates a configuration from a template.\n A Makefile is also created in the new build directory.\n\n Example:\n\n .. code-block:: console\n\n make config O=mybuild T=x86_64-native-linuxapp-gcc\n\nBuild Targets\n-------------\n\nBuild targets support the optional specification of the name of the output directory, using O=mybuilddir.\nThe default output directory is build.\n\n* all, build or just make\n\n Build the DPDK in the output directory previously created by a make config.\n\n Example:\n\n .. code-block:: console\n\n make O=mybuild\n\n* clean\n\n Clean all objects created using make build.\n\n Example:\n\n .. code-block:: console\n\n make clean O=mybuild\n\n* %_sub\n\n Build a subdirectory only, without managing dependencies on other directories.\n\n Example:\n\n .. code-block:: console\n\n make lib/librte_eal_sub O=mybuild\n\n* %_clean\n\n Clean a subdirectory only.\n\n Example:\n\n .. code-block:: console\n\n make lib/librte_eal_clean O=mybuild\n\nInstall Targets\n---------------\n\n* Install\n\n Build the DPDK binary.\n Actually, this builds each supported target in a separate directory.\n The name of each directory is the name of the target.\n The name of the targets to install can be optionally specified using T=mytarget.\n The target name can contain wildcard \\* characters.\n The list of available targets are in $(RTE_SDK)/config (remove the defconfig\\_ prefix).\n\n Example:\n\n .. code-block:: console\n\n make install T=x86_64-*\n\n* Uninstall\n\n Remove installed target directories.\n\nTest Targets\n------------\n\n* test\n\n Launch automatic tests for a build directory specified using O=mybuilddir.\n It is optional, the default output directory is build.\n\n Example:\n\n .. code-block:: console\n\n make test O=mybuild\n\n* testall\n\n Launch automatic tests for all installed target directories (after a make install).\n The name of the targets to test can be optionally specified using T=mytarget.\n The target name can contain wildcard (\\*) characters.\n The list of available targets are in $(RTE_SDK)/config (remove the defconfig\\_ prefix).\n\n Examples:\n\n .. code-block:: console\n\n make testall, make testall T=x86_64-*\n\nDocumentation Targets\n---------------------\n\n* doc\n\n Generate the Doxygen documentation (API, html and pdf).\n\n* doc-api-html\n\n Generate the Doxygen API documentation in html.\n\n* doc-guides-html\n\n Generate the guides documentation in html.\n\n* doc-guides-pdf\n\n Generate the guides documentation in pdf.\n\n\nDeps Targets\n------------\n\n* depdirs\n\n This target is implicitly called by make config.\n Typically, there is no need for a user to call it,\n except if DEPDIRS-y variables have been updated in Makefiles.\n It will generate the file $(RTE_OUTPUT)/.depdirs.\n\n Example:\n\n .. code-block:: console\n\n make depdirs O=mybuild\n\n* depgraph\n\n This command generates a dot graph of dependencies.\n It can be displayed to debug circular dependency issues, or just to understand the dependencies.\n\n Example:\n\n .. code-block:: console\n\n make depgraph O=mybuild > /tmp/graph.dot && dotty /tmp/ graph.dot\n\nMisc Targets\n------------\n\n* help\n\n Show this help.\n\nOther Useful Command-line Variables\n-----------------------------------\n\nThe following variables can be specified on the command line:\n\n* V=\n\n Enable verbose build (show full compilation command line, and some intermediate commands).\n\n* D=\n\n Enable dependency debugging. This provides some useful information about why a target is built or not.\n\n* EXTRA_CFLAGS=, EXTRA_LDFLAGS=, EXTRA_LDLIBS=, EXTRA_ASFLAGS=, EXTRA_CPPFLAGS=\n\n Append specific compilation, link or asm flags.\n\n* CROSS=\n\n Specify a cross toolchain header that will prefix all gcc/binutils applications. This only works when using gcc.\n\nMake in a Build Directory\n-------------------------\n\nAll targets described above are called from the SDK root $(RTE_SDK).\nIt is possible to run the same Makefile targets inside the build directory.\nFor instance, the following command:\n\n.. code-block:: console\n\n cd $(RTE_SDK)\n make config O=mybuild T=x86_64-native-linuxapp-gcc\n make O=mybuild\n\nis equivalent to:\n\n.. code-block:: console\n\n cd $(RTE_SDK)\n make config O=mybuild T=x86_64-native-linuxapp-gcc\n cd mybuild\n\n # no need to specify O= now\n make\n\nCompiling for Debug\n-------------------\n\nTo compile the DPDK and sample applications with debugging information included and the optimization level set to 0,\nthe EXTRA_CFLAGS environment variable should be set before compiling as follows:\n\n.. code-block:: console\n\n export EXTRA_CFLAGS='-O0 -g'\n\nThe DPDK and any user or sample applications can then be compiled in the usual way.\nFor example:\n\n.. code-block:: console\n\n make install T=x86_64-native-linuxapp-gcc make -C examples/\n" }, { "path": "doc/guides/prog_guide/env_abstraction_layer.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Environment_Abstraction_Layer:\n\nEnvironment Abstraction Layer\n=============================\n\nThe Environment Abstraction Layer (EAL) is responsible for gaining access to low-level resources such as hardware and memory space.\nIt provides a generic interface that hides the environment specifics from the applications and libraries.\nIt is the responsibility of the initialization routine to decide how to allocate these resources\n(that is, memory space, PCI devices, timers, consoles, and so on).\n\nTypical services expected from the EAL are:\n\n* DPDK Loading and Launching:\n The DPDK and its application are linked as a single application and must be loaded by some means.\n\n* Core Affinity/Assignment Procedures:\n The EAL provides mechanisms for assigning execution units to specific cores as well as creating execution instances.\n\n* System Memory Reservation:\n The EAL facilitates the reservation of different memory zones, for example, physical memory areas for device interactions.\n\n* PCI Address Abstraction: The EAL provides an interface to access PCI address space.\n\n* Trace and Debug Functions: Logs, dump_stack, panic and so on.\n\n* Utility Functions: Spinlocks and atomic counters that are not provided in libc.\n\n* CPU Feature Identification: Determine at runtime if a particular feature, for example, Intel® AVX is supported.\n Determine if the current CPU supports the feature set that the binary was compiled for.\n\n* Interrupt Handling: Interfaces to register/unregister callbacks to specific interrupt sources.\n\n* Alarm Functions: Interfaces to set/remove callbacks to be run at a specific time.\n\nEAL in a Linux-userland Execution Environment\n---------------------------------------------\n\nIn a Linux user space environment, the DPDK application runs as a user-space application using the pthread library.\nPCI information about devices and address space is discovered through the /sys kernel interface and through kernel modules such as uio_pci_generic, or igb_uio.\nRefer to the UIO: User-space drivers documentation in the Linux kernel. This memory is mmap'd in the application.\n\nThe EAL performs physical memory allocation using mmap() in hugetlbfs (using huge page sizes to increase performance).\nThis memory is exposed to DPDK service layers such as the :ref:`Mempool Library `.\n\nAt this point, the DPDK services layer will be initialized, then through pthread setaffinity calls,\neach execution unit will be assigned to a specific logical core to run as a user-level thread.\n\nThe time reference is provided by the CPU Time-Stamp Counter (TSC) or by the HPET kernel API through a mmap() call.\n\nInitialization and Core Launching\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nPart of the initialization is done by the start function of glibc.\nA check is also performed at initialization time to ensure that the micro architecture type chosen in the config file is supported by the CPU.\nThen, the main() function is called. The core initialization and launch is done in rte_eal_init() (see the API documentation).\nIt consist of calls to the pthread library (more specifically, pthread_self(), pthread_create(), and pthread_setaffinity_np()).\n\n.. _figure_linuxapp_launch:\n\n.. figure:: img/linuxapp_launch.*\n\n EAL Initialization in a Linux Application Environment\n\n\n.. note::\n\n Initialization of objects, such as memory zones, rings, memory pools, lpm tables and hash tables,\n should be done as part of the overall application initialization on the master lcore.\n The creation and initialization functions for these objects are not multi-thread safe.\n However, once initialized, the objects themselves can safely be used in multiple threads simultaneously.\n\nMulti-process Support\n~~~~~~~~~~~~~~~~~~~~~\n\nThe Linuxapp EAL allows a multi-process as well as a multi-threaded (pthread) deployment model.\nSee chapter 2.20\n:ref:`Multi-process Support ` for more details.\n\nMemory Mapping Discovery and Memory Reservation\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe allocation of large contiguous physical memory is done using the hugetlbfs kernel filesystem.\nThe EAL provides an API to reserve named memory zones in this contiguous memory.\nThe physical address of the reserved memory for that memory zone is also returned to the user by the memory zone reservation API.\n\n.. note::\n\n Memory reservations done using the APIs provided by the rte_malloc library are also backed by pages from the hugetlbfs filesystem.\n\nXen Dom0 support without hugetbls\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe existing memory management implementation is based on the Linux kernel hugepage mechanism.\nHowever, Xen Dom0 does not support hugepages, so a new Linux kernel module rte_dom0_mm is added to workaround this limitation.\n\nThe EAL uses IOCTL interface to notify the Linux kernel module rte_dom0_mm to allocate memory of specified size,\nand get all memory segments information from the module,\nand the EAL uses MMAP interface to map the allocated memory.\nFor each memory segment, the physical addresses are contiguous within it but actual hardware addresses are contiguous within 2MB.\n\nPCI Access\n~~~~~~~~~~\n\nThe EAL uses the /sys/bus/pci utilities provided by the kernel to scan the content on the PCI bus.\nTo access PCI memory, a kernel module called uio_pci_generic provides a /dev/uioX device file\nand resource files in /sys\nthat can be mmap'd to obtain access to PCI address space from the application.\nThe DPDK-specific igb_uio module can also be used for this. Both drivers use the uio kernel feature (userland driver).\n\nPer-lcore and Shared Variables\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n.. note::\n\n lcore refers to a logical execution unit of the processor, sometimes called a hardware *thread*.\n\nShared variables are the default behavior.\nPer-lcore variables are implemented using *Thread Local Storage* (TLS) to provide per-thread local storage.\n\nLogs\n~~~~\n\nA logging API is provided by EAL.\nBy default, in a Linux application, logs are sent to syslog and also to the console.\nHowever, the log function can be overridden by the user to use a different logging mechanism.\n\nTrace and Debug Functions\n^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThere are some debug functions to dump the stack in glibc.\nThe rte_panic() function can voluntarily provoke a SIG_ABORT,\nwhich can trigger the generation of a core file, readable by gdb.\n\nCPU Feature Identification\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe EAL can query the CPU at runtime (using the rte_cpu_get_feature() function) to determine which CPU features are available.\n\nUser Space Interrupt Event\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n+ User Space Interrupt and Alarm Handling in Host Thread\n\nThe EAL creates a host thread to poll the UIO device file descriptors to detect the interrupts.\nCallbacks can be registered or unregistered by the EAL functions for a specific interrupt event\nand are called in the host thread asynchronously.\nThe EAL also allows timed callbacks to be used in the same way as for NIC interrupts.\n\n.. note::\n\n In DPDK PMD, the only interrupts handled by the dedicated host thread are those for link status change,\n i.e. link up and link down notification.\n\n\n+ RX Interrupt Event\n\nThe receive and transmit routines provided by each PMD don't limit themselves to execute in polling thread mode.\nTo ease the idle polling with tiny throughput, it's useful to pause the polling and wait until the wake-up event happens.\nThe RX interrupt is the first choice to be such kind of wake-up event, but probably won't be the only one.\n\nEAL provides the event APIs for this event-driven thread mode.\nTaking linuxapp as an example, the implementation relies on epoll. Each thread can monitor an epoll instance\nin which all the wake-up events' file descriptors are added. The event file descriptors are created and mapped to\nthe interrupt vectors according to the UIO/VFIO spec.\nFrom bsdapp's perspective, kqueue is the alternative way, but not implemented yet.\n\nEAL initializes the mapping between event file descriptors and interrupt vectors, while each device initializes the mapping\nbetween interrupt vectors and queues. In this way, EAL actually is unaware of the interrupt cause on the specific vector.\nThe eth_dev driver takes responsibility to program the latter mapping.\n\n.. note::\n\n Per queue RX interrupt event is only allowed in VFIO which supports multiple MSI-X vector. In UIO, the RX interrupt\n together with other interrupt causes shares the same vector. In this case, when RX interrupt and LSC(link status change)\n interrupt are both enabled(intr_conf.lsc == 1 && intr_conf.rxq == 1), only the former is capable.\n\nThe RX interrupt are controlled/enabled/disabled by ethdev APIs - 'rte_eth_dev_rx_intr_*'. They return failure if the PMD\nhasn't support them yet. The intr_conf.rxq flag is used to turn on the capability of RX interrupt per device.\n\nBlacklisting\n~~~~~~~~~~~~\n\nThe EAL PCI device blacklist functionality can be used to mark certain NIC ports as blacklisted,\nso they are ignored by the DPDK.\nThe ports to be blacklisted are identified using the PCIe* description (Domain:Bus:Device.Function).\n\nMisc Functions\n~~~~~~~~~~~~~~\n\nLocks and atomic operations are per-architecture (i686 and x86_64).\n\nMemory Segments and Memory Zones (memzone)\n------------------------------------------\n\nThe mapping of physical memory is provided by this feature in the EAL.\nAs physical memory can have gaps, the memory is described in a table of descriptors,\nand each descriptor (called rte_memseg ) describes a contiguous portion of memory.\n\nOn top of this, the memzone allocator's role is to reserve contiguous portions of physical memory.\nThese zones are identified by a unique name when the memory is reserved.\n\nThe rte_memzone descriptors are also located in the configuration structure.\nThis structure is accessed using rte_eal_get_configuration().\nThe lookup (by name) of a memory zone returns a descriptor containing the physical address of the memory zone.\n\nMemory zones can be reserved with specific start address alignment by supplying the align parameter\n(by default, they are aligned to cache line size).\nThe alignment value should be a power of two and not less than the cache line size (64 bytes).\nMemory zones can also be reserved from either 2 MB or 1 GB hugepages, provided that both are available on the system.\n\n\nMultiple pthread\n----------------\n\nDPDK usually pins one pthread per core to avoid the overhead of task switching.\nThis allows for significant performance gains, but lacks flexibility and is not always efficient.\n\nPower management helps to improve the CPU efficiency by limiting the CPU runtime frequency.\nHowever, alternately it is possible to utilize the idle cycles available to take advantage of\nthe full capability of the CPU.\n\nBy taking advantage of cgroup, the CPU utilization quota can be simply assigned.\nThis gives another way to improve the CPU efficiency, however, there is a prerequisite;\nDPDK must handle the context switching between multiple pthreads per core.\n\nFor further flexibility, it is useful to set pthread affinity not only to a CPU but to a CPU set.\n\nEAL pthread and lcore Affinity\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe term \"lcore\" refers to an EAL thread, which is really a Linux/FreeBSD pthread.\n\"EAL pthreads\" are created and managed by EAL and execute the tasks issued by *remote_launch*.\nIn each EAL pthread, there is a TLS (Thread Local Storage) called *_lcore_id* for unique identification.\nAs EAL pthreads usually bind 1:1 to the physical CPU, the *_lcore_id* is typically equal to the CPU ID.\n\nWhen using multiple pthreads, however, the binding is no longer always 1:1 between an EAL pthread and a specified physical CPU.\nThe EAL pthread may have affinity to a CPU set, and as such the *_lcore_id* will not be the same as the CPU ID.\nFor this reason, there is an EAL long option '--lcores' defined to assign the CPU affinity of lcores.\nFor a specified lcore ID or ID group, the option allows setting the CPU set for that EAL pthread.\n\nThe format pattern:\n\t--lcores='[@cpu_set][,[@cpu_set],...]'\n\n'lcore_set' and 'cpu_set' can be a single number, range or a group.\n\nA number is a \"digit([0-9]+)\"; a range is \"-\"; a group is \"([,,...])\".\n\nIf a '\\@cpu_set' value is not supplied, the value of 'cpu_set' will default to the value of 'lcore_set'.\n\n ::\n\n \tFor example, \"--lcores='1,2@(5-7),(3-5)@(0,2),(0,6),7-8'\" which means start 9 EAL thread;\n \t lcore 0 runs on cpuset 0x41 (cpu 0,6);\n \t lcore 1 runs on cpuset 0x2 (cpu 1);\n \t lcore 2 runs on cpuset 0xe0 (cpu 5,6,7);\n \t lcore 3,4,5 runs on cpuset 0x5 (cpu 0,2);\n \t lcore 6 runs on cpuset 0x41 (cpu 0,6);\n \t lcore 7 runs on cpuset 0x80 (cpu 7);\n \t lcore 8 runs on cpuset 0x100 (cpu 8).\n\nUsing this option, for each given lcore ID, the associated CPUs can be assigned.\nIt's also compatible with the pattern of corelist('-l') option.\n\nnon-EAL pthread support\n~~~~~~~~~~~~~~~~~~~~~~~\n\nIt is possible to use the DPDK execution context with any user pthread (aka. Non-EAL pthreads).\nIn a non-EAL pthread, the *_lcore_id* is always LCORE_ID_ANY which identifies that it is not an EAL thread with a valid, unique, *_lcore_id*.\nSome libraries will use an alternative unique ID (e.g. TID), some will not be impacted at all, and some will work but with limitations (e.g. timer and mempool libraries).\n\nAll these impacts are mentioned in :ref:`known_issue_label` section.\n\nPublic Thread API\n~~~~~~~~~~~~~~~~~\n\nThere are two public APIs ``rte_thread_set_affinity()`` and ``rte_pthread_get_affinity()`` introduced for threads.\nWhen they're used in any pthread context, the Thread Local Storage(TLS) will be set/get.\n\nThose TLS include *_cpuset* and *_socket_id*:\n\n*\t*_cpuset* stores the CPUs bitmap to which the pthread is affinitized.\n\n*\t*_socket_id* stores the NUMA node of the CPU set. If the CPUs in CPU set belong to different NUMA node, the *_socket_id* will be set to SOCKET_ID_ANY.\n\n\n.. _known_issue_label:\n\nKnown Issues\n~~~~~~~~~~~~\n\n+ rte_mempool\n\n The rte_mempool uses a per-lcore cache inside the mempool.\n For non-EAL pthreads, ``rte_lcore_id()`` will not return a valid number.\n So for now, when rte_mempool is used with non-EAL pthreads, the put/get operations will bypass the mempool cache and there is a performance penalty because of this bypass.\n Support for non-EAL mempool cache is currently being enabled.\n\n+ rte_ring\n\n rte_ring supports multi-producer enqueue and multi-consumer dequeue.\n However, it is non-preemptive, this has a knock on effect of making rte_mempool non-preemptable.\n\n .. note::\n\n The \"non-preemptive\" constraint means:\n\n - a pthread doing multi-producers enqueues on a given ring must not\n be preempted by another pthread doing a multi-producer enqueue on\n the same ring.\n - a pthread doing multi-consumers dequeues on a given ring must not\n be preempted by another pthread doing a multi-consumer dequeue on\n the same ring.\n\n Bypassing this constraint it may cause the 2nd pthread to spin until the 1st one is scheduled again.\n Moreover, if the 1st pthread is preempted by a context that has an higher priority, it may even cause a dead lock.\n\n This does not mean it cannot be used, simply, there is a need to narrow down the situation when it is used by multi-pthread on the same core.\n\n 1. It CAN be used for any single-producer or single-consumer situation.\n\n 2. It MAY be used by multi-producer/consumer pthread whose scheduling policy are all SCHED_OTHER(cfs). User SHOULD be aware of the performance penalty before using it.\n\n 3. It MUST not be used by multi-producer/consumer pthreads, whose scheduling policies are SCHED_FIFO or SCHED_RR.\n\n ``RTE_RING_PAUSE_REP_COUNT`` is defined for rte_ring to reduce contention. It's mainly for case 2, a yield is issued after number of times pause repeat.\n\n It adds a sched_yield() syscall if the thread spins for too long while waiting on the other thread to finish its operations on the ring.\n This gives the preempted thread a chance to proceed and finish with the ring enqueue/dequeue operation.\n\n+ rte_timer\n\n Running ``rte_timer_manager()`` on a non-EAL pthread is not allowed. However, resetting/stopping the timer from a non-EAL pthread is allowed.\n\n+ rte_log\n\n In non-EAL pthreads, there is no per thread loglevel and logtype, global loglevels are used.\n\n+ misc\n\n The debug statistics of rte_ring, rte_mempool and rte_timer are not supported in a non-EAL pthread.\n\ncgroup control\n~~~~~~~~~~~~~~\n\nThe following is a simple example of cgroup control usage, there are two pthreads(t0 and t1) doing packet I/O on the same core ($CPU).\nWe expect only 50% of CPU spend on packet IO.\n\n .. code-block:: console\n\n mkdir /sys/fs/cgroup/cpu/pkt_io\n mkdir /sys/fs/cgroup/cpuset/pkt_io\n\n echo $cpu > /sys/fs/cgroup/cpuset/cpuset.cpus\n\n echo $t0 > /sys/fs/cgroup/cpu/pkt_io/tasks\n echo $t0 > /sys/fs/cgroup/cpuset/pkt_io/tasks\n\n echo $t1 > /sys/fs/cgroup/cpu/pkt_io/tasks\n echo $t1 > /sys/fs/cgroup/cpuset/pkt_io/tasks\n\n cd /sys/fs/cgroup/cpu/pkt_io\n echo 100000 > pkt_io/cpu.cfs_period_us\n echo 50000 > pkt_io/cpu.cfs_quota_us\n\n\nMalloc\n------\n\nThe EAL provides a malloc API to allocate any-sized memory.\n\nThe objective of this API is to provide malloc-like functions to allow\nallocation from hugepage memory and to facilitate application porting.\nThe *DPDK API Reference* manual describes the available functions.\n\nTypically, these kinds of allocations should not be done in data plane\nprocessing because they are slower than pool-based allocation and make\nuse of locks within the allocation and free paths.\nHowever, they can be used in configuration code.\n\nRefer to the rte_malloc() function description in the *DPDK API Reference*\nmanual for more information.\n\nCookies\n~~~~~~~\n\nWhen CONFIG_RTE_MALLOC_DEBUG is enabled, the allocated memory contains\noverwrite protection fields to help identify buffer overflows.\n\nAlignment and NUMA Constraints\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe rte_malloc() takes an align argument that can be used to request a memory\narea that is aligned on a multiple of this value (which must be a power of two).\n\nOn systems with NUMA support, a call to the rte_malloc() function will return\nmemory that has been allocated on the NUMA socket of the core which made the call.\nA set of APIs is also provided, to allow memory to be explicitly allocated on a\nNUMA socket directly, or by allocated on the NUMA socket where another core is\nlocated, in the case where the memory is to be used by a logical core other than\non the one doing the memory allocation.\n\nUse Cases\n~~~~~~~~~\n\nThis API is meant to be used by an application that requires malloc-like\nfunctions at initialization time.\n\nFor allocating/freeing data at runtime, in the fast-path of an application,\nthe memory pool library should be used instead.\n\nInternal Implementation\n~~~~~~~~~~~~~~~~~~~~~~~\n\nData Structures\n^^^^^^^^^^^^^^^\n\nThere are two data structure types used internally in the malloc library:\n\n* struct malloc_heap - used to track free space on a per-socket basis\n\n* struct malloc_elem - the basic element of allocation and free-space\n tracking inside the library.\n\nStructure: malloc_heap\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThe malloc_heap structure is used to manage free space on a per-socket basis.\nInternally, there is one heap structure per NUMA node, which allows us to\nallocate memory to a thread based on the NUMA node on which this thread runs.\nWhile this does not guarantee that the memory will be used on that NUMA node,\nit is no worse than a scheme where the memory is always allocated on a fixed\nor random node.\n\nThe key fields of the heap structure and their function are described below\n(see also diagram above):\n\n* lock - the lock field is needed to synchronize access to the heap.\n Given that the free space in the heap is tracked using a linked list,\n we need a lock to prevent two threads manipulating the list at the same time.\n\n* free_head - this points to the first element in the list of free nodes for\n this malloc heap.\n\n.. note::\n\n The malloc_heap structure does not keep track of in-use blocks of memory,\n since these are never touched except when they are to be freed again -\n at which point the pointer to the block is an input to the free() function.\n\n.. _figure_malloc_heap:\n\n.. figure:: img/malloc_heap.*\n\n Example of a malloc heap and malloc elements within the malloc library\n\n\n.. _malloc_elem:\n\nStructure: malloc_elem\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThe malloc_elem structure is used as a generic header structure for various\nblocks of memory.\nIt is used in three different ways - all shown in the diagram above:\n\n#. As a header on a block of free or allocated memory - normal case\n\n#. As a padding header inside a block of memory\n\n#. As an end-of-memseg marker\n\nThe most important fields in the structure and how they are used are described below.\n\n.. note::\n\n If the usage of a particular field in one of the above three usages is not\n described, the field can be assumed to have an undefined value in that\n situation, for example, for padding headers only the \"state\" and \"pad\"\n fields have valid values.\n\n* heap - this pointer is a reference back to the heap structure from which\n this block was allocated.\n It is used for normal memory blocks when they are being freed, to add the\n newly-freed block to the heap's free-list.\n\n* prev - this pointer points to the header element/block in the memseg\n immediately behind the current one. When freeing a block, this pointer is\n used to reference the previous block to check if that block is also free.\n If so, then the two free blocks are merged to form a single larger block.\n\n* next_free - this pointer is used to chain the free-list of unallocated\n memory blocks together.\n It is only used in normal memory blocks; on ``malloc()`` to find a suitable\n free block to allocate and on ``free()`` to add the newly freed element to\n the free-list.\n\n* state - This field can have one of three values: ``FREE``, ``BUSY`` or\n ``PAD``.\n The former two are to indicate the allocation state of a normal memory block\n and the latter is to indicate that the element structure is a dummy structure\n at the end of the start-of-block padding, i.e. where the start of the data\n within a block is not at the start of the block itself, due to alignment\n constraints.\n In that case, the pad header is used to locate the actual malloc element\n header for the block.\n For the end-of-memseg structure, this is always a ``BUSY`` value, which\n ensures that no element, on being freed, searches beyond the end of the\n memseg for other blocks to merge with into a larger free area.\n\n* pad - this holds the length of the padding present at the start of the block.\n In the case of a normal block header, it is added to the address of the end\n of the header to give the address of the start of the data area, i.e. the\n value passed back to the application on a malloc.\n Within a dummy header inside the padding, this same value is stored, and is\n subtracted from the address of the dummy header to yield the address of the\n actual block header.\n\n* size - the size of the data block, including the header itself.\n For end-of-memseg structures, this size is given as zero, though it is never\n actually checked.\n For normal blocks which are being freed, this size value is used in place of\n a \"next\" pointer to identify the location of the next block of memory that\n in the case of being ``FREE``, the two free blocks can be merged into one.\n\nMemory Allocation\n^^^^^^^^^^^^^^^^^\n\nOn EAL initialisation, all memsegs are setup as part of the malloc heap.\nThis setup involves placing a dummy structure at the end with ``BUSY`` state,\nwhich may contain a sentinel value if ``CONFIG_RTE_MALLOC_DEBUG`` is enabled,\nand a proper :ref:`element header` with ``FREE`` at the start\nfor each memseg.\nThe ``FREE`` element is then added to the ``free_list`` for the malloc heap.\n\nWhen an application makes a call to a malloc-like function, the malloc function\nwill first index the ``lcore_config`` structure for the calling thread, and\ndetermine the NUMA node of that thread.\nThe NUMA node is used to index the array of ``malloc_heap`` structures which is\npassed as a parameter to the ``heap_alloc()`` function, along with the\nrequested size, type, alignment and boundary parameters.\n\nThe ``heap_alloc()`` function will scan the free_list of the heap, and attempt\nto find a free block suitable for storing data of the requested size, with the\nrequested alignment and boundary constraints.\n\nWhen a suitable free element has been identified, the pointer to be returned\nto the user is calculated.\nThe cache-line of memory immediately preceding this pointer is filled with a\nstruct malloc_elem header.\nBecause of alignment and boundary constraints, there could be free space at\nthe start and/or end of the element, resulting in the following behavior:\n\n#. Check for trailing space.\n If the trailing space is big enough, i.e. > 128 bytes, then the free element\n is split.\n If it is not, then we just ignore it (wasted space).\n\n#. Check for space at the start of the element.\n If the space at the start is small, i.e. <=128 bytes, then a pad header is\n used, and the remaining space is wasted.\n If, however, the remaining space is greater, then the free element is split.\n\nThe advantage of allocating the memory from the end of the existing element is\nthat no adjustment of the free list needs to take place - the existing element\non the free list just has its size pointer adjusted, and the following element\nhas its \"prev\" pointer redirected to the newly created element.\n\nFreeing Memory\n^^^^^^^^^^^^^^\n\nTo free an area of memory, the pointer to the start of the data area is passed\nto the free function.\nThe size of the ``malloc_elem`` structure is subtracted from this pointer to get\nthe element header for the block.\nIf this header is of type ``PAD`` then the pad length is further subtracted from\nthe pointer to get the proper element header for the entire block.\n\nFrom this element header, we get pointers to the heap from which the block was\nallocated and to where it must be freed, as well as the pointer to the previous\nelement, and via the size field, we can calculate the pointer to the next element.\nThese next and previous elements are then checked to see if they are also\n``FREE``, and if so, they are merged with the current element.\nThis means that we can never have two ``FREE`` memory blocks adjacent to one\nanother, as they are always merged into a single block.\n" }, { "path": "doc/guides/prog_guide/ext_app_lib_make_help.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _External_Application/Library_Makefile_help:\n\nExternal Application/Library Makefile help\n==========================================\n\nExternal applications or libraries should include specific Makefiles from RTE_SDK, located in mk directory.\nThese Makefiles are:\n\n* ${RTE_SDK}/mk/rte.extapp.mk: Build an application\n\n* ${RTE_SDK}/mk/rte.extlib.mk: Build a static library\n\n* ${RTE_SDK}/mk/rte.extobj.mk: Build objects (.o)\n\nPrerequisites\n-------------\n\nThe following variables must be defined:\n\n* ${RTE_SDK}: Points to the root directory of the DPDK.\n\n* ${RTE_TARGET}: Reference the target to be used for compilation (for example, x86_64-native-linuxapp-gcc).\n\nBuild Targets\n-------------\n\nBuild targets support the specification of the name of the output directory, using O=mybuilddir.\nThis is optional; the default output directory is build.\n\n* all, \"nothing\" (meaning just make)\n\n Build the application or the library in the specified output directory.\n\n Example:\n\n .. code-block:: console\n\n make O=mybuild\n\n* clean\n\n Clean all objects created using make build.\n\n Example:\n\n .. code-block:: console\n\n make clean O=mybuild\n\nHelp Targets\n------------\n\n* help\n\n Show this help.\n\nOther Useful Command-line Variables\n-----------------------------------\n\nThe following variables can be specified at the command line:\n\n* S=\n\n Specify the directory in which the sources are located. By default, it is the current directory.\n\n* M=\n\n Specify the Makefile to call once the output directory is created. By default, it uses $(S)/Makefile.\n\n* V=\n\n Enable verbose build (show full compilation command line and some intermediate commands).\n\n* D=\n\n Enable dependency debugging. This provides some useful information about why a target must be rebuilt or not.\n\n* EXTRA_CFLAGS=, EXTRA_LDFLAGS=, EXTRA_ASFLAGS=, EXTRA_CPPFLAGS=\n\n Append specific compilation, link or asm flags.\n\n* CROSS=\n\n Specify a cross-toolchain header that will prefix all gcc/binutils applications. This only works when using gcc.\n\nMake from Another Directory\n---------------------------\n\nIt is possible to run the Makefile from another directory, by specifying the output and the source dir. For example:\n\n.. code-block:: console\n\n export RTE_SDK=/path/to/DPDK\n export RTE_TARGET=x86_64-native-linuxapp-icc\n make -f /path/to/my_app/Makefile S=/path/to/my_app O=/path/to/build_dir\n" }, { "path": "doc/guides/prog_guide/extend_intel_dpdk.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nExtending the DPDK\n=========================\n\nThis chapter describes how a developer can extend the DPDK to provide a new library,\na new target, or support a new target.\n\nExample: Adding a New Library libfoo\n------------------------------------\n\nTo add a new library to the DPDK, proceed as follows:\n\n#. Add a new configuration option:\n\n .. code-block:: bash\n\n for f in config/\\*; do \\\n echo CONFIG_RTE_LIBFOO=y >> $f; done\n\n#. Create a new directory with sources:\n\n .. code-block:: console\n\n mkdir ${RTE_SDK}/lib/libfoo\n touch ${RTE_SDK}/lib/libfoo/foo.c\n touch ${RTE_SDK}/lib/libfoo/foo.h\n\n#. Add a foo() function in libfoo.\n\n Definition is in foo.c:\n\n .. code-block:: c\n\n void foo(void)\n {\n }\n\n Declaration is in foo.h:\n\n .. code-block:: c\n\n extern void foo(void);\n\n\n#. Update lib/Makefile:\n\n .. code-block:: console\n\n vi ${RTE_SDK}/lib/Makefile\n # add:\n # DIRS-$(CONFIG_RTE_LIBFOO) += libfoo\n\n#. Create a new Makefile for this library, for example, derived from mempool Makefile:\n\n .. code-block:: console\n\n cp ${RTE_SDK}/lib/librte_mempool/Makefile ${RTE_SDK}/lib/libfoo/\n\n vi ${RTE_SDK}/lib/libfoo/Makefile\n # replace:\n # librte_mempool -> libfoo\n # rte_mempool -> foo\n\n\n#. Update mk/DPDK.app.mk, and add -lfoo in LDLIBS variable when the option is enabled.\n This will automatically add this flag when linking a DPDK application.\n\n\n#. Build the DPDK with the new library (we only show a specific target here):\n\n .. code-block:: console\n\n cd ${RTE_SDK}\n make config T=x86_64-native-linuxapp-gcc\n make\n\n\n#. Check that the library is installed:\n\n .. code-block:: console\n\n ls build/lib\n ls build/include\n\nExample: Using libfoo in the Test Application\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe test application is used to validate all functionality of the DPDK.\nOnce you have added a library, a new test case should be added in the test application.\n\n* A new test_foo.c file should be added, that includes foo.h and calls the foo() function from test_foo().\n When the test passes, the test_foo() function should return 0.\n\n* Makefile, test.h and commands.c must be updated also, to handle the new test case.\n\n* Test report generation: autotest.py is a script that is used to generate the test report that is available in the\n ${RTE_SDK}/doc/rst/test_report/autotests directory. This script must be updated also.\n If libfoo is in a new test family, the links in ${RTE_SDK}/doc/rst/test_report/test_report.rst must be updated.\n\n* Build the DPDK with the updated test application (we only show a specific target here):\n\n\n .. code-block:: console\n\n cd ${RTE_SDK}\n make config T=x86_64-native-linuxapp-gcc\n make\n" }, { "path": "doc/guides/prog_guide/glossary.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nGlossary\n========\n\n\nACL\n Access Control List\n\nAPI\n Application Programming Interface\n\nASLR\n Linux* kernel Address-Space Layout Randomization\n\nBSD\n Berkeley Software Distribution\n\nClr\n Clear\n\nCIDR\n Classless Inter-Domain Routing\n\nControl Plane\n The control plane is concerned with the routing of packets and with\n providing a start or end point.\n\nCore\n A core may include several lcores or threads if the processor supports\n hyperthreading.\n\nCore Components\n A set of libraries provided by the DPDK, including eal, ring, mempool,\n mbuf, timers, and so on.\n\nCPU\n Central Processing Unit\n\nCRC\n Cyclic Redundancy Check\n\nctrlmbuf\n An *mbuf* carrying control data.\n\nData Plane\n In contrast to the control plane, the data plane in a network architecture\n are the layers involved when forwarding packets. These layers must be\n highly optimized to achieve good performance.\n\nDIMM\n Dual In-line Memory Module\n\nDoxygen\n A documentation generator used in the DPDK to generate the API reference.\n\nDPDK\n Data Plane Development Kit\n\nDRAM\n Dynamic Random Access Memory\n\nEAL\n The Environment Abstraction Layer (EAL) provides a generic interface that\n hides the environment specifics from the applications and libraries. The\n services expected from the EAL are: development kit loading and launching,\n core affinity/ assignment procedures, system memory allocation/description,\n PCI bus access, inter-partition communication.\n\nFIFO\n First In First Out\n\nFPGA\n Field Programmable Gate Array\n\nGbE\n Gigabit Ethernet\n\nHW\n Hardware\n\nHPET\n High Precision Event Timer; a hardware timer that provides a precise time\n reference on x86 platforms.\n\nID\n Identifier\n\nIOCTL\n Input/Output Control\n\nI/O\n Input/Output\n\nIP\n Internet Protocol\n\nIPv4\n Internet Protocol version 4\n\nIPv6\n Internet Protocol version 6\n\nlcore\n A logical execution unit of the processor, sometimes called a *hardware\n thread*.\n\nKNI\n Kernel Network Interface\n\nL1\n Layer 1\n\nL2\n Layer 2\n\nL3\n Layer 3\n\nL4\n Layer 4\n\nLAN\n Local Area Network\n\nLPM\n Longest Prefix Match\n\nmaster lcore\n The execution unit that executes the main() function and that launches\n other lcores.\n\nmbuf\n An mbuf is a data structure used internally to carry messages (mainly\n network packets). The name is derived from BSD stacks. To understand the\n concepts of packet buffers or mbuf, refer to *TCP/IP Illustrated, Volume 2:\n The Implementation*.\n\nMESI\n Modified Exclusive Shared Invalid (CPU cache coherency protocol)\n\nMTU\n Maximum Transfer Unit\n\nNIC\n Network Interface Card\n\nOOO\n Out Of Order (execution of instructions within the CPU pipeline)\n\nNUMA\n Non-uniform Memory Access\n\nPCI\n Peripheral Connect Interface\n\nPHY\n An abbreviation for the physical layer of the OSI model.\n\npktmbuf\n An *mbuf* carrying a network packet.\n\nPMD\n Poll Mode Driver\n\nQoS\n Quality of Service\n\nRCU\n Read-Copy-Update algorithm, an alternative to simple rwlocks.\n\nRd\n Read\n\nRED\n Random Early Detection\n\nRSS\n Receive Side Scaling\n\nRTE\n Run Time Environment. Provides a fast and simple framework for fast packet\n processing, in a lightweight environment as a Linux* application and using\n Poll Mode Drivers (PMDs) to increase speed.\n\nRx\n Reception\n\nSlave lcore\n Any *lcore* that is not the *master lcore*.\n\nSocket\n A physical CPU, that includes several *cores*.\n\nSLA\n Service Level Agreement\n\nsrTCM\n Single Rate Three Color Marking\n\nSRTD\n Scheduler Round Trip Delay\n\nSW\n Software\n\nTarget\n In the DPDK, the target is a combination of architecture, machine,\n executive environment and toolchain. For example:\n i686-native-linuxapp-gcc.\n\nTCP\n Transmission Control Protocol\n\nTC\n Traffic Class\n\nTLB\n Translation Lookaside Buffer\n\nTLS\n Thread Local Storage\n\ntrTCM\n Two Rate Three Color Marking\n\nTSC\n Time Stamp Counter\n\nTx\n Transmission\n\nTUN/TAP\n TUN and TAP are virtual network kernel devices.\n\nVLAN\n Virtual Local Area Network\n\nWr\n Write\n\nWRED\n Weighted Random Early Detection\n\nWRR\n Weighted Round Robin\n" }, { "path": "doc/guides/prog_guide/hash_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Hash_Library:\n\nHash Library\n============\n\nThe DPDK provides a Hash Library for creating hash table for fast lookup.\nThe hash table is a data structure optimized for searching through a set of entries that are each identified by a unique key.\nFor increased performance the DPDK Hash requires that all the keys have the same number of bytes which is set at the hash creation time.\n\nHash API Overview\n-----------------\n\nThe main configuration parameters for the hash are:\n\n* Total number of hash entries\n\n* Size of the key in bytes\n\nThe hash also allows the configuration of some low-level implementation related parameters such as:\n\n* Hash function to translate the key into a bucket index\n\nThe main methods exported by the hash are:\n\n* Add entry with key: The key is provided as input. If a new entry is successfully added to the hash for the specified key,\n or there is already an entry in the hash for the specified key, then the position of the entry is returned.\n If the operation was not successful, for example due to lack of free entries in the hash, then a negative value is returned;\n\n* Delete entry with key: The key is provided as input. If an entry with the specified key is found in the hash,\n then the entry is removed from the hash and the position where the entry was found in the hash is returned.\n If no entry with the specified key exists in the hash, then a negative value is returned\n\n* Lookup for entry with key: The key is provided as input. If an entry with the specified key is found in the hash (lookup hit),\n then the position of the entry is returned, otherwise (lookup miss) a negative value is returned.\n\nApart from these method explained above, the API allows the user three more options:\n\n* Add / lookup / delete with key and precomputed hash: Both the key and its precomputed hash are provided as input. This allows\n the user to perform these operations faster, as hash is already computed.\n\n* Add / lookup with key and data: A pair of key-value is provided as input. This allows the user to store\n not only the key, but also data which may be either a 8-byte integer or a pointer to external data (if data size is more than 8 bytes).\n\n* Combination of the two options above: User can provide key, precomputed hash and data.\n\nAlso, the API contains a method to allow the user to look up entries in bursts, achieving higher performance\nthan looking up individual entries, as the function prefetches next entries at the time it is operating\nwith the first ones, which reduces significantly the impact of the necessary memory accesses.\nNotice that this method uses a pipeline of 8 entries (4 stages of 2 entries), so it is highly recommended\nto use at least 8 entries per burst.\n\nThe actual data associated with each key can be either managed by the user using a separate table that\nmirrors the hash in terms of number of entries and position of each entry,\nas shown in the Flow Classification use case describes in the following sections,\nor stored in the hash table itself.\n\nThe example hash tables in the L2/L3 Forwarding sample applications defines which port to forward a packet to based on a packet flow identified by the five-tuple lookup.\nHowever, this table could also be used for more sophisticated features and provide many other functions and actions that could be performed on the packets and flows.\n\nImplementation Details\n----------------------\n\nThe hash table has two main tables:\n\n* First table is an array of entries which is further divided into buckets,\n with the same number of consecutive array entries in each bucket. Each entry contains the computed primary\n and secondary hashes of a given key (explained below), and an index to the second table.\n\n* The second table is an array of all the keys stored in the hash table and its data associated to each key.\n\nThe hash library uses the cuckoo hash method to resolve collisions.\nFor any input key, there are two possible buckets (primary and secondary/alternative location)\nwhere that key can be stored in the hash, therefore only the entries within those bucket need to be examined\nwhen the key is looked up.\nThe lookup speed is achieved by reducing the number of entries to be scanned from the total\nnumber of hash entries down to the number of entries in the two hash buckets,\nas opposed to the basic method of linearly scanning all the entries in the array.\nThe hash uses a hash function (configurable) to translate the input key into a 4-byte key signature.\nThe bucket index is the key signature modulo the number of hash buckets.\n\nOnce the buckets are identified, the scope of the hash add,\ndelete and lookup operations is reduced to the entries in those buckets (it is very likely that entries are in the primary bucket).\n\nTo speed up the search logic within the bucket, each hash entry stores the 4-byte key signature together with the full key for each hash entry.\nFor large key sizes, comparing the input key against a key from the bucket can take significantly more time than\ncomparing the 4-byte signature of the input key against the signature of a key from the bucket.\nTherefore, the signature comparison is done first and the full key comparison done only when the signatures matches.\nThe full key comparison is still necessary, as two input keys from the same bucket can still potentially have the same 4-byte hash signature,\nalthough this event is relatively rare for hash functions providing good uniform distributions for the set of input keys.\n\nExample of lookup:\n\nFirst of all, the primary bucket is identified and entry is likely to be stored there.\nIf signature was stored there, we compare its key against the one provided and return the position\nwhere it was stored and/or the data associated to that key if there is a match.\nIf signature is not in the primary bucket, the secondary bucket is looked up, where same procedure\nis carried out. If there is no match there either, key is considered not to be in the table.\n\nExample of addition:\n\nLike lookup, the primary and secondary buckets are indentified. If there is an empty slot in\nthe primary bucket, primary and secondary signatures are stored in that slot, key and data (if any) are added to\nthe second table and an index to the position in the second table is stored in the slot of the first table.\nIf there is no space in the primary bucket, one of the entries on that bucket is pushed to its alternative location,\nand the key to be added is inserted in its position.\nTo know where the alternative bucket of the evicted entry is, the secondary signature is looked up and alternative bucket index\nis calculated from doing the modulo, as seen above. If there is room in the alternative bucket, the evicted entry\nis stored in it. If not, same process is repeated (one of the entries gets pushed) until a non full bucket is found.\nNotice that despite all the entry movement in the first table, the second table is not touched, which would impact\ngreatly in performance.\n\nIn the very unlikely event that table enters in a loop where same entries are being evicted indefinitely,\nkey is considered not able to be stored.\nWith random keys, this method allows the user to get around 90% of the table utilization, without\nhaving to drop any stored entry (LRU) or allocate more memory (extended buckets).\n\nEntry distribution in hash table\n--------------------------------\n\nAs mentioned above, Cuckoo hash implementation pushes elements out of their bucket,\nif there is a new entry to be added which primary location coincides with their current bucket,\nbeing pushed to their alternative location.\nTherefore, as user adds more entries to the hash table, distribution of the hash values\nin the buckets will change, being most of them in their primary location and a few in\ntheir secondary location, which the later will increase, as table gets busier.\nThis information is quite useful, as performance may be lower as more entries\nare evicted to their secondary location.\n\nSee the tables below showing example entry distribution as table utilization increases.\n\n.. _table_hash_lib_1:\n\n.. table:: Entry distribution measured with an example table with 1024 random entries using jhash algorithm\n\n +--------------+-----------------------+-------------------------+\n | % Table used | % In Primary location | % In Secondary location |\n +==============+=======================+=========================+\n | 25 | 100 | 0 |\n +--------------+-----------------------+-------------------------+\n | 50 | 96.1 | 3.9 |\n +--------------+-----------------------+-------------------------+\n | 75 | 88.2 | 11.8 |\n +--------------+-----------------------+-------------------------+\n | 80 | 86.3 | 13.7 |\n +--------------+-----------------------+-------------------------+\n | 85 | 83.1 | 16.9 |\n +--------------+-----------------------+-------------------------+\n | 90 | 77.3 | 22.7 |\n +--------------+-----------------------+-------------------------+\n | 95.8 | 64.5 | 35.5 |\n +--------------+-----------------------+-------------------------+\n\n|\n\n.. _table_hash_lib_2:\n\n.. table:: Entry distribution measured with an example table with 1 million random entries using jhash algorithm\n\n +--------------+-----------------------+-------------------------+\n | % Table used | % In Primary location | % In Secondary location |\n +==============+=======================+=========================+\n | 50 | 96 | 4 |\n +--------------+-----------------------+-------------------------+\n | 75 | 86.9 | 13.1 |\n +--------------+-----------------------+-------------------------+\n | 80 | 83.9 | 16.1 |\n +--------------+-----------------------+-------------------------+\n | 85 | 80.1 | 19.9 |\n +--------------+-----------------------+-------------------------+\n | 90 | 74.8 | 25.2 |\n +--------------+-----------------------+-------------------------+\n | 94.5 | 67.4 | 32.6 |\n +--------------+-----------------------+-------------------------+\n\n.. note::\n\n Last values on the tables above are the average maximum table\n utilization with random keys and using Jenkins hash function.\n\nUse Case: Flow Classification\n-----------------------------\n\nFlow classification is used to map each input packet to the connection/flow it belongs to.\nThis operation is necessary as the processing of each input packet is usually done in the context of their connection,\nso the same set of operations is applied to all the packets from the same flow.\n\nApplications using flow classification typically have a flow table to manage, with each separate flow having an entry associated with it in this table.\nThe size of the flow table entry is application specific, with typical values of 4, 16, 32 or 64 bytes.\n\nEach application using flow classification typically has a mechanism defined to uniquely identify a flow based on\na number of fields read from the input packet that make up the flow key.\nOne example is to use the DiffServ 5-tuple made up of the following fields of the IP and transport layer packet headers:\nSource IP Address, Destination IP Address, Protocol, Source Port, Destination Port.\n\nThe DPDK hash provides a generic method to implement an application specific flow classification mechanism.\nGiven a flow table implemented as an array, the application should create a hash object with the same number of entries as the flow table and\nwith the hash key size set to the number of bytes in the selected flow key.\n\nThe flow table operations on the application side are described below:\n\n* Add flow: Add the flow key to hash.\n If the returned position is valid, use it to access the flow entry in the flow table for adding a new flow or\n updating the information associated with an existing flow.\n Otherwise, the flow addition failed, for example due to lack of free entries for storing new flows.\n\n* Delete flow: Delete the flow key from the hash. If the returned position is valid,\n use it to access the flow entry in the flow table to invalidate the information associated with the flow.\n\n* Lookup flow: Lookup for the flow key in the hash.\n If the returned position is valid (flow lookup hit), use the returned position to access the flow entry in the flow table.\n Otherwise (flow lookup miss) there is no flow registered for the current packet.\n\nReferences\n----------\n\n* Donald E. Knuth, The Art of Computer Programming, Volume 3: Sorting and Searching (2nd Edition), 1998, Addison-Wesley Professional\n" }, { "path": "doc/guides/prog_guide/index.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nProgrammer's Guide\n==================\n\n|today|\n\n\n**Contents**\n\n.. toctree::\n :maxdepth: 3\n :numbered:\n\n intro\n overview\n env_abstraction_layer\n ring_lib\n mempool_lib\n mbuf_lib\n poll_mode_drv\n ivshmem_lib\n link_bonding_poll_mode_drv_lib\n timer_lib\n hash_lib\n lpm_lib\n lpm6_lib\n packet_distrib_lib\n reorder_lib\n ip_fragment_reassembly_lib\n multi_proc_support\n kernel_nic_interface\n thread_safety_intel_dpdk_functions\n qos_framework\n power_man\n packet_classif_access_ctrl\n packet_framework\n vhost_lib\n port_hotplug_framework\n source_org\n dev_kit_build_system\n dev_kit_root_make_help\n extend_intel_dpdk\n build_app\n ext_app_lib_make_help\n perf_opt_guidelines\n writing_efficient_code\n profile_app\n glossary\n\n\n**Figures**\n\n:numref:`figure_architecture-overview` :ref:`figure_architecture-overview`\n\n:numref:`figure_linuxapp_launch` :ref:`figure_linuxapp_launch`\n\n:numref:`figure_malloc_heap` :ref:`figure_malloc_heap`\n\n:numref:`figure_ring1` :ref:`figure_ring1`\n\n:numref:`figure_ring-enqueue1` :ref:`figure_ring-enqueue1`\n\n:numref:`figure_ring-enqueue2` :ref:`figure_ring-enqueue2`\n\n:numref:`figure_ring-enqueue3` :ref:`figure_ring-enqueue3`\n\n:numref:`figure_ring-dequeue1` :ref:`figure_ring-dequeue1`\n\n:numref:`figure_ring-dequeue2` :ref:`figure_ring-dequeue2`\n\n:numref:`figure_ring-dequeue3` :ref:`figure_ring-dequeue3`\n\n:numref:`figure_ring-mp-enqueue1` :ref:`figure_ring-mp-enqueue1`\n\n:numref:`figure_ring-mp-enqueue2` :ref:`figure_ring-mp-enqueue2`\n\n:numref:`figure_ring-mp-enqueue3` :ref:`figure_ring-mp-enqueue3`\n\n:numref:`figure_ring-mp-enqueue4` :ref:`figure_ring-mp-enqueue4`\n\n:numref:`figure_ring-mp-enqueue5` :ref:`figure_ring-mp-enqueue5`\n\n:numref:`figure_ring-modulo1` :ref:`figure_ring-modulo1`\n\n:numref:`figure_ring-modulo2` :ref:`figure_ring-modulo2`\n\n:numref:`figure_memory-management` :ref:`figure_memory-management`\n\n:numref:`figure_memory-management2` :ref:`figure_memory-management2`\n\n:numref:`figure_mempool` :ref:`figure_mempool`\n\n:numref:`figure_mbuf1` :ref:`figure_mbuf1`\n\n:numref:`figure_mbuf2` :ref:`figure_mbuf2`\n\n:numref:`figure_multi_process_memory` :ref:`figure_multi_process_memory`\n\n:numref:`figure_kernel_nic_intf` :ref:`figure_kernel_nic_intf`\n\n:numref:`figure_pkt_flow_kni` :ref:`figure_pkt_flow_kni`\n\n:numref:`figure_vhost_net_arch2` :ref:`figure_vhost_net_arch2`\n\n:numref:`figure_kni_traffic_flow` :ref:`figure_kni_traffic_flow`\n\n\n:numref:`figure_pkt_proc_pipeline_qos` :ref:`figure_pkt_proc_pipeline_qos`\n\n:numref:`figure_hier_sched_blk` :ref:`figure_hier_sched_blk`\n\n:numref:`figure_sched_hier_per_port` :ref:`figure_sched_hier_per_port`\n\n:numref:`figure_data_struct_per_port` :ref:`figure_data_struct_per_port`\n\n:numref:`figure_prefetch_pipeline` :ref:`figure_prefetch_pipeline`\n\n:numref:`figure_pipe_prefetch_sm` :ref:`figure_pipe_prefetch_sm`\n\n:numref:`figure_blk_diag_dropper` :ref:`figure_blk_diag_dropper`\n\n:numref:`figure_flow_tru_droppper` :ref:`figure_flow_tru_droppper`\n\n:numref:`figure_ex_data_flow_tru_dropper` :ref:`figure_ex_data_flow_tru_dropper`\n\n:numref:`figure_pkt_drop_probability` :ref:`figure_pkt_drop_probability`\n\n:numref:`figure_drop_probability_graph` :ref:`figure_drop_probability_graph`\n\n:numref:`figure_figure32` :ref:`figure_figure32`\n\n:numref:`figure_figure33` :ref:`figure_figure33`\n\n:numref:`figure_figure34` :ref:`figure_figure34`\n\n:numref:`figure_figure35` :ref:`figure_figure35`\n\n:numref:`figure_figure37` :ref:`figure_figure37`\n\n:numref:`figure_figure38` :ref:`figure_figure38`\n\n:numref:`figure_figure39` :ref:`figure_figure39`\n\n\n**Tables**\n\n:numref:`table_qos_1` :ref:`table_qos_1`\n\n:numref:`table_qos_2` :ref:`table_qos_2`\n\n:numref:`table_qos_3` :ref:`table_qos_3`\n\n:numref:`table_qos_4` :ref:`table_qos_4`\n\n:numref:`table_qos_5` :ref:`table_qos_5`\n\n:numref:`table_qos_6` :ref:`table_qos_6`\n\n:numref:`table_qos_7` :ref:`table_qos_7`\n\n:numref:`table_qos_8` :ref:`table_qos_8`\n\n:numref:`table_qos_9` :ref:`table_qos_9`\n\n:numref:`table_qos_10` :ref:`table_qos_10`\n\n:numref:`table_qos_11` :ref:`table_qos_11`\n\n:numref:`table_qos_12` :ref:`table_qos_12`\n\n:numref:`table_qos_13` :ref:`table_qos_13`\n\n:numref:`table_qos_14` :ref:`table_qos_14`\n\n:numref:`table_qos_15` :ref:`table_qos_15`\n\n:numref:`table_qos_16` :ref:`table_qos_16`\n\n:numref:`table_qos_17` :ref:`table_qos_17`\n\n:numref:`table_qos_18` :ref:`table_qos_18`\n\n:numref:`table_qos_19` :ref:`table_qos_19`\n\n:numref:`table_qos_20` :ref:`table_qos_20`\n\n:numref:`table_qos_21` :ref:`table_qos_21`\n\n:numref:`table_qos_22` :ref:`table_qos_22`\n\n:numref:`table_qos_23` :ref:`table_qos_23`\n\n:numref:`table_qos_24` :ref:`table_qos_24`\n\n:numref:`table_qos_25` :ref:`table_qos_25`\n\n:numref:`table_qos_26` :ref:`table_qos_26`\n\n:numref:`table_qos_27` :ref:`table_qos_27`\n\n:numref:`table_qos_28` :ref:`table_qos_28`\n\n:numref:`table_qos_29` :ref:`table_qos_29`\n\n:numref:`table_qos_30` :ref:`table_qos_30`\n\n:numref:`table_qos_31` :ref:`table_qos_31`\n\n:numref:`table_qos_32` :ref:`table_qos_32`\n\n:numref:`table_qos_33` :ref:`table_qos_33`\n\n:numref:`table_qos_34` :ref:`table_qos_34`\n\n:numref:`table_hash_lib_1` :ref:`table_hash_lib_1`\n\n:numref:`table_hash_lib_2` :ref:`table_hash_lib_2`\n" }, { "path": "doc/guides/prog_guide/intro.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIntroduction\n============\n\nThis document provides software architecture information,\ndevelopment environment information and optimization guidelines.\n\nFor programming examples and for instructions on compiling and running each sample application,\nsee the *DPDK Sample Applications User Guide* for details.\n\nFor general information on compiling and running applications, see the *DPDK Getting Started Guide*.\n\nDocumentation Roadmap\n---------------------\n\nThe following is a list of DPDK documents in the suggested reading order:\n\n* **Release Notes** (this document): Provides release-specific information, including supported features,\n limitations, fixed issues, known issues and so on.\n Also, provides the answers to frequently asked questions in FAQ format.\n\n* **Getting Started Guide** : Describes how to install and configure the DPDK software;\n designed to get users up and running quickly with the software.\n\n* **FreeBSD* Getting Started Guide** : A document describing the use of the DPDK with FreeBSD*\n has been added in DPDK Release 1.6.0.\n Refer to this guide for installation and configuration instructions to get started using the DPDK with FreeBSD*.\n\n* **Programmer's Guide** (this document): Describes:\n\n * The software architecture and how to use it (through examples),\n specifically in a Linux* application (linuxapp) environment\n\n * The content of the DPDK, the build system\n (including the commands that can be used in the root DPDK Makefile to build the development kit and an application)\n and guidelines for porting an application\n\n * Optimizations used in the software and those that should be considered for new development\n\n A glossary of terms is also provided.\n\n* **API Reference** : Provides detailed information about DPDK functions,\n data structures and other programming constructs.\n\n* **Sample Applications User Guide**: Describes a set of sample applications.\n Each chapter describes a sample application that showcases specific functionality\n and provides instructions on how to compile, run and use the sample application.\n\nRelated Publications\n--------------------\n\nThe following documents provide information that is relevant to the development of applications using the DPDK:\n\n* Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide\n" }, { "path": "doc/guides/prog_guide/ip_fragment_reassembly_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIP Fragmentation and Reassembly Library\n=======================================\n\nThe IP Fragmentation and Reassembly Library implements IPv4 and IPv6 packet fragmentation and reassembly.\n\nPacket fragmentation\n--------------------\n\nPacket fragmentation routines divide input packet into number of fragments.\nBoth rte_ipv4_fragment_packet() and rte_ipv6_fragment_packet() functions assume that input mbuf data\npoints to the start of the IP header of the packet (i.e. L2 header is already stripped out).\nTo avoid copying of the actual packet's data zero-copy technique is used (rte_pktmbuf_attach).\nFor each fragment two new mbufs are created:\n\n* Direct mbuf -- mbuf that will contain L3 header of the new fragment.\n\n* Indirect mbuf -- mbuf that is attached to the mbuf with the original packet.\n It's data field points to the start of the original packets data plus fragment offset.\n\nThen L3 header is copied from the original mbuf into the 'direct' mbuf and updated to reflect new fragmented status.\nNote that for IPv4, header checksum is not recalculated and is set to zero.\n\nFinally 'direct' and 'indirect' mbufs for each fragment are linked together via mbuf's next filed to compose a packet for the new fragment.\n\nThe caller has an ability to explicitly specify which mempools should be used to allocate 'direct' and 'indirect' mbufs from.\n\nFor more information about direct and indirect mbufs, refer to the *DPDK Programmers guide 7.7 Direct and Indirect Buffers.*\n\nPacket reassembly\n-----------------\n\nIP Fragment Table\n~~~~~~~~~~~~~~~~~\n\nFragment table maintains information about already received fragments of the packet.\n\nEach IP packet is uniquely identified by triple , , .\n\nNote that all update/lookup operations on Fragment Table are not thread safe.\nSo if different execution contexts (threads/processes) will access the same table simultaneously,\nthen some external syncing mechanism have to be provided.\n\nEach table entry can hold information about packets consisting of up to RTE_LIBRTE_IP_FRAG_MAX (by default: 4) fragments.\n\nCode example, that demonstrates creation of a new Fragment table:\n\n.. code-block:: c\n\n frag_cycles = (rte_get_tsc_hz() + MS_PER_S - 1) / MS_PER_S * max_flow_ttl;\n bucket_num = max_flow_num + max_flow_num / 4;\n frag_tbl = rte_ip_frag_table_create(max_flow_num, bucket_entries, max_flow_num, frag_cycles, socket_id);\n\nInternally Fragment table is a simple hash table.\nThe basic idea is to use two hash functions and \\* associativity.\nThis provides 2 \\* possible locations in the hash table for each key.\nWhen the collision occurs and all 2 \\* are occupied,\ninstead of reinserting existing keys into alternative locations, ip_frag_tbl_add() just returns a failure.\n\nAlso, entries that resides in the table longer then are considered as invalid,\nand could be removed/replaced by the new ones.\n\nNote that reassembly demands a lot of mbuf's to be allocated.\nAt any given time up to (2 \\* bucket_entries \\* RTE_LIBRTE_IP_FRAG_MAX \\* )\ncan be stored inside Fragment Table waiting for remaining fragments.\n\nPacket Reassembly\n~~~~~~~~~~~~~~~~~\n\nFragmented packets processing and reassembly is done by the rte_ipv4_frag_reassemble_packet()/rte_ipv6_frag_reassemble_packet.\nFunctions. They either return a pointer to valid mbuf that contains reassembled packet,\nor NULL (if the packet can't be reassembled for some reason).\n\nThese functions are responsible for:\n\n#. Search the Fragment Table for entry with packet's .\n\n#. If the entry is found, then check if that entry already timed-out.\n If yes, then free all previously received fragments, and remove information about them from the entry.\n\n#. If no entry with such key is found, then try to create a new one by one of two ways:\n\n a) Use as empty entry.\n\n b) Delete a timed-out entry, free mbufs associated with it mbufs and store a new entry with specified key in it.\n\n#. Update the entry with new fragment information and check if a packet can be reassembled\n (the packet's entry contains all fragments).\n\n a) If yes, then, reassemble the packet, mark table's entry as empty and return the reassembled mbuf to the caller.\n\n b) If no, then return a NULL to the caller.\n\nIf at any stage of packet processing an error is encountered\n(e.g: can't insert new entry into the Fragment Table, or invalid/timed-out fragment),\nthen the function will free all associated with the packet fragments,\nmark the table entry as invalid and return NULL to the caller.\n\nDebug logging and Statistics Collection\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe RTE_LIBRTE_IP_FRAG_TBL_STAT config macro controls statistics collection for the Fragment Table.\nThis macro is not enabled by default.\n\nThe RTE_LIBRTE_IP_FRAG_DEBUG controls debug logging of IP fragments processing and reassembling.\nThis macro is disabled by default.\nNote that while logging contains a lot of detailed information,\nit slows down packet processing and might cause the loss of a lot of packets.\n" }, { "path": "doc/guides/prog_guide/ivshmem_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIVSHMEM Library\n===============\n\nThe DPDK IVSHMEM library facilitates fast zero-copy data sharing among virtual machines\n(host-to-guest or guest-to-guest) by means of QEMU's IVSHMEM mechanism.\n\nThe library works by providing a command line for QEMU to map several hugepages into a single IVSHMEM device.\nFor the guest to know what is inside any given IVSHMEM device\n(and to distinguish between DPDK and non-DPDK IVSHMEM devices),\na metadata file is also mapped into the IVSHMEM segment.\nNo work needs to be done by the guest application to map IVSHMEM devices into memory;\nthey are automatically recognized by the DPDK Environment Abstraction Layer (EAL).\n\nA typical DPDK IVSHMEM use case looks like the following.\n\n\n.. figure:: img/ivshmem.*\n\n Typical Ivshmem use case\n\n\nThe same could work with several virtual machines, providing host-to-VM or VM-to-VM communication.\nThe maximum number of metadata files is 32 (by default) and each metadata file can contain different (or even the same) hugepages.\nThe only constraint is that each VM has to have access to the memory it is sharing with other entities (be it host or another VM).\nFor example, if the user wants to share the same memzone across two VMs, each VM must have that memzone in its metadata file.\n\nIVHSHMEM Library API Overview\n-----------------------------\n\nThe following is a simple guide to using the IVSHMEM Library API:\n\n* Call rte_ivshmem_metadata_create() to create a new metadata file.\n The metadata name is used to distinguish between multiple metadata files.\n\n* Populate each metadata file with DPDK data structures.\n This can be done using the following API calls:\n\n * rte_ivhshmem_metadata_add_memzone() to add rte_memzone to metadata file\n\n * rte_ivshmem_metadata_add_ring() to add rte_ring to metadata file\n\n * rte_ivshmem_metadata_add_mempool() to add rte_mempool to metadata file\n\n* Finally, call rte_ivshmem_metadata_cmdline_generate() to generate the command line for QEMU.\n Multiple metadata files (and thus multiple command lines) can be supplied to a single VM.\n\n.. note::\n\n Only data structures fully residing in DPDK hugepage memory work correctly.\n Supported data structures created by malloc(), mmap()\n or otherwise using non-DPDK memory cause undefined behavior and even a segmentation fault.\n\nIVSHMEM Environment Configuration\n---------------------------------\n\nThe steps needed to successfully run IVSHMEM applications are the following:\n\n* Compile a special version of QEMU from sources.\n\n The source code can be found on the QEMU website (currently, version 1.4.x is supported, but version 1.5.x is known to work also),\n however, the source code will need to be patched to support using regular files as the IVSHMEM memory backend.\n The patch is not included in the DPDK package,\n but is available on the `Intel®DPDK-vswitch project webpage `_\n (either separately or in a DPDK vSwitch package).\n\n* Enable IVSHMEM library in the DPDK build configuration.\n\n In the default configuration, IVSHMEM library is not compiled. To compile the IVSHMEM library,\n one has to either use one of the provided IVSHMEM targets\n (for example, x86_64-ivshmem-linuxapp-gcc),\n or set CONFIG_RTE_LIBRTE_IVSHMEM to \"y\" in the build configuration.\n\n* Set up hugepage memory on the virtual machine.\n\n The guest applications run as regular DPDK (primary) processes and thus need their own hugepage memory set up inside the VM.\n The process is identical to the one described in the *DPDK Getting Started Guide*.\n\nBest Practices for Writing IVSHMEM Applications\n-----------------------------------------------\n\nWhen considering the use of IVSHMEM for sharing memory, security implications need to be carefully evaluated.\nIVSHMEM is not suitable for untrusted guests, as IVSHMEM is essentially a window into the host process memory.\nThis also has implications for the multiple VM scenarios.\nWhile the IVSHMEM library tries to share as little memory as possible,\nit is quite probable that data designated for one VM might also be present in an IVSMHMEM device designated for another VM.\nConsequently, any shared memory corruption will affect both host and all VMs sharing that particular memory.\n\nIVSHMEM applications essentially behave like multi-process applications,\nso it is important to implement access serialization to data and thread safety.\nDPDK ring structures are already thread-safe, however,\nany custom data structures that the user might need would have to be thread-safe also.\n\nSimilar to regular DPDK multi-process applications,\nit is not recommended to use function pointers as functions might have different memory addresses in different processes.\n\nIt is best to avoid freeing the rte_mbuf structure on a different machine from where it was allocated,\nthat is, if the mbuf was allocated on the host, the host should free it.\nConsequently, any packet transmission and reception should also happen on the same machine (whether virtual or physical).\nFailing to do so may lead to data corruption in the mempool cache.\n\nDespite the IVSHMEM mechanism being zero-copy and having good performance,\nit is still desirable to do processing in batches and follow other procedures described in\n:ref:`Performance Optimization `.\n\nBest Practices for Running IVSHMEM Applications\n-----------------------------------------------\n\nFor performance reasons,\nit is best to pin host processes and QEMU processes to different cores so that they do not interfere with each other.\nIf NUMA support is enabled, it is also desirable to keep host process' hugepage memory and QEMU process on the same NUMA node.\n\nFor the best performance across all NUMA nodes, each QEMU core should be pinned to host CPU core on the appropriate NUMA node.\nQEMU's virtual NUMA nodes should also be set up to correspond to physical NUMA nodes.\nMore on how to set up DPDK and QEMU NUMA support can be found in *DPDK Getting Started Guide* and\n`QEMU documentation `_ respectively.\nA script called cpu_layout.py is provided with the DPDK package (in the tools directory)\nthat can be used to identify which CPU cores correspond to which NUMA node.\n\nThe QEMU IVSHMEM command line creation should be considered the last step before starting the virtual machine.\nCurrently, there is no hot plug support for QEMU IVSHMEM devices,\nso one cannot add additional memory to an IVSHMEM device once it has been created.\nTherefore, the correct sequence to run an IVSHMEM application is to run host application first,\nobtain the command lines for each IVSHMEM device and then run all QEMU instances with guest applications afterwards.\n\nIt is important to note that once QEMU is started, it holds on to the hugepages it uses for IVSHMEM devices.\nAs a result, if the user wishes to shut down or restart the IVSHMEM host application,\nit is not enough to simply shut the application down.\nThe virtual machine must also be shut down (if not, it will hold onto outdated host data).\n" }, { "path": "doc/guides/prog_guide/kernel_nic_interface.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nKernel NIC Interface\n====================\n\nThe DPDK Kernel NIC Interface (KNI) allows userspace applications access to the Linux* control plane.\n\nThe benefits of using the DPDK KNI are:\n\n* Faster than existing Linux TUN/TAP interfaces\n (by eliminating system calls and copy_to_user()/copy_from_user() operations.\n\n* Allows management of DPDK ports using standard Linux net tools such as ethtool, ifconfig and tcpdump.\n\n* Allows an interface with the kernel network stack.\n\nThe components of an application using the DPDK Kernel NIC Interface are shown in :numref:`figure_kernel_nic_intf`.\n\n.. _figure_kernel_nic_intf:\n\n.. figure:: img/kernel_nic_intf.*\n\n Components of a DPDK KNI Application\n\n\nThe DPDK KNI Kernel Module\n--------------------------\n\nThe KNI kernel loadable module provides support for two types of devices:\n\n* A Miscellaneous device (/dev/kni) that:\n\n * Creates net devices (via ioctl calls).\n\n * Maintains a kernel thread context shared by all KNI instances\n (simulating the RX side of the net driver).\n\n * For single kernel thread mode, maintains a kernel thread context shared by all KNI instances\n (simulating the RX side of the net driver).\n\n * For multiple kernel thread mode, maintains a kernel thread context for each KNI instance\n (simulating the RX side of the new driver).\n\n* Net device:\n\n * Net functionality provided by implementing several operations such as netdev_ops,\n header_ops, ethtool_ops that are defined by struct net_device,\n including support for DPDK mbufs and FIFOs.\n\n * The interface name is provided from userspace.\n\n * The MAC address can be the real NIC MAC address or random.\n\nKNI Creation and Deletion\n-------------------------\n\nThe KNI interfaces are created by a DPDK application dynamically.\nThe interface name and FIFO details are provided by the application through an ioctl call\nusing the rte_kni_device_info struct which contains:\n\n* The interface name.\n\n* Physical addresses of the corresponding memzones for the relevant FIFOs.\n\n* Mbuf mempool details, both physical and virtual (to calculate the offset for mbuf pointers).\n\n* PCI information.\n\n* Core affinity.\n\nRefer to rte_kni_common.h in the DPDK source code for more details.\n\nThe physical addresses will be re-mapped into the kernel address space and stored in separate KNI contexts.\n\nOnce KNI interfaces are created, the KNI context information can be queried by calling the rte_kni_info_get() function.\n\nThe KNI interfaces can be deleted by a DPDK application dynamically after being created.\nFurthermore, all those KNI interfaces not deleted will be deleted on the release operation\nof the miscellaneous device (when the DPDK application is closed).\n\nDPDK mbuf Flow\n--------------\n\nTo minimize the amount of DPDK code running in kernel space, the mbuf mempool is managed in userspace only.\nThe kernel module will be aware of mbufs,\nbut all mbuf allocation and free operations will be handled by the DPDK application only.\n\n:numref:`figure_pkt_flow_kni` shows a typical scenario with packets sent in both directions.\n\n.. _figure_pkt_flow_kni:\n\n.. figure:: img/pkt_flow_kni.*\n\n Packet Flow via mbufs in the DPDK KNI\n\n\nUse Case: Ingress\n-----------------\n\nOn the DPDK RX side, the mbuf is allocated by the PMD in the RX thread context.\nThis thread will enqueue the mbuf in the rx_q FIFO.\nThe KNI thread will poll all KNI active devices for the rx_q.\nIf an mbuf is dequeued, it will be converted to a sk_buff and sent to the net stack via netif_rx().\nThe dequeued mbuf must be freed, so the same pointer is sent back in the free_q FIFO.\n\nThe RX thread, in the same main loop, polls this FIFO and frees the mbuf after dequeuing it.\n\nUse Case: Egress\n----------------\n\nFor packet egress the DPDK application must first enqueue several mbufs to create an mbuf cache on the kernel side.\n\nThe packet is received from the Linux net stack, by calling the kni_net_tx() callback.\nThe mbuf is dequeued (without waiting due the cache) and filled with data from sk_buff.\nThe sk_buff is then freed and the mbuf sent in the tx_q FIFO.\n\nThe DPDK TX thread dequeues the mbuf and sends it to the PMD (via rte_eth_tx_burst()).\nIt then puts the mbuf back in the cache.\n\nEthtool\n-------\n\nEthtool is a Linux-specific tool with corresponding support in the kernel\nwhere each net device must register its own callbacks for the supported operations.\nThe current implementation uses the igb/ixgbe modified Linux drivers for ethtool support.\nEthtool is not supported in i40e and VMs (VF or EM devices).\n\nLink state and MTU change\n-------------------------\n\nLink state and MTU change are network interface specific operations usually done via ifconfig.\nThe request is initiated from the kernel side (in the context of the ifconfig process)\nand handled by the user space DPDK application.\nThe application polls the request, calls the application handler and returns the response back into the kernel space.\n\nThe application handlers can be registered upon interface creation or explicitly registered/unregistered in runtime.\nThis provides flexibility in multiprocess scenarios\n(where the KNI is created in the primary process but the callbacks are handled in the secondary one).\nThe constraint is that a single process can register and handle the requests.\n\nKNI Working as a Kernel vHost Backend\n-------------------------------------\n\nvHost is a kernel module usually working as the backend of virtio (a para- virtualization driver framework)\nto accelerate the traffic from the guest to the host.\nThe DPDK Kernel NIC interface provides the ability to hookup vHost traffic into userspace DPDK application.\nTogether with the DPDK PMD virtio, it significantly improves the throughput between guest and host.\nIn the scenario where DPDK is running as fast path in the host, kni-vhost is an efficient path for the traffic.\n\nOverview\n~~~~~~~~\n\nvHost-net has three kinds of real backend implementations. They are: 1) tap, 2) macvtap and 3) RAW socket.\nThe main idea behind kni-vhost is making the KNI work as a RAW socket, attaching it as the backend instance of vHost-net.\nIt is using the existing interface with vHost-net, so it does not require any kernel hacking,\nand is fully-compatible with the kernel vhost module.\nAs vHost is still taking responsibility for communicating with the front-end virtio,\nit naturally supports both legacy virtio -net and the DPDK PMD virtio.\nThere is a little penalty that comes from the non-polling mode of vhost.\nHowever, it scales throughput well when using KNI in multi-thread mode.\n\n.. _figure_vhost_net_arch2:\n\n.. figure:: img/vhost_net_arch.*\n\n vHost-net Architecture Overview\n\n\nPacket Flow\n~~~~~~~~~~~\n\nThere is only a minor difference from the original KNI traffic flows.\nOn transmit side, vhost kthread calls the RAW socket's ops sendmsg and it puts the packets into the KNI transmit FIFO.\nOn the receive side, the kni kthread gets packets from the KNI receive FIFO, puts them into the queue of the raw socket,\nand wakes up the task in vhost kthread to begin receiving.\nAll the packet copying, irrespective of whether it is on the transmit or receive side,\nhappens in the context of vhost kthread.\nEvery vhost-net device is exposed to a front end virtio device in the guest.\n\n.. _figure_kni_traffic_flow:\n\n.. figure:: img/kni_traffic_flow.*\n\n KNI Traffic Flow\n\n\nSample Usage\n~~~~~~~~~~~~\n\nBefore starting to use KNI as the backend of vhost, the CONFIG_RTE_KNI_VHOST configuration option must be turned on.\nOtherwise, by default, KNI will not enable its backend support capability.\n\nOf course, as a prerequisite, the vhost/vhost-net kernel CONFIG should be chosen before compiling the kernel.\n\n#. Compile the DPDK and insert uio_pci_generic/igb_uio kernel modules as normal.\n\n#. Insert the KNI kernel module:\n\n .. code-block:: console\n\n insmod ./rte_kni.ko\n\n If using KNI in multi-thread mode, use the following command line:\n\n .. code-block:: console\n\n insmod ./rte_kni.ko kthread_mode=multiple\n\n#. Running the KNI sample application:\n\n .. code-block:: console\n\n examples/kni/build/app/kni -c -0xf0 -n 4 -- -p 0x3 -P --config=\"(0,4,6),(1,5,7)\"\n\n This command runs the kni sample application with two physical ports.\n Each port pins two forwarding cores (ingress/egress) in user space.\n\n#. Assign a raw socket to vhost-net during qemu-kvm startup.\n The DPDK does not provide a script to do this since it is easy for the user to customize.\n The following shows the key steps to launch qemu-kvm with kni-vhost:\n\n .. code-block:: bash\n\n #!/bin/bash\n echo 1 > /sys/class/net/vEth0/sock_en\n fd=`cat /sys/class/net/vEth0/sock_fd`\n qemu-kvm \\\n -name vm1 -cpu host -m 2048 -smp 1 -hda /opt/vm-fc16.img \\\n -netdev tap,fd=$fd,id=hostnet1,vhost=on \\\n -device virti-net-pci,netdev=hostnet1,id=net1,bus=pci.0,addr=0x4\n\nIt is simple to enable raw socket using sysfs sock_en and get raw socket fd using sock_fd under the KNI device node.\n\nThen, using the qemu-kvm command with the -netdev option to assign such raw socket fd as vhost's backend.\n\n.. note::\n\n The key word tap must exist as qemu-kvm now only supports vhost with a tap backend, so here we cheat qemu-kvm by an existing fd.\n\nCompatibility Configure Option\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThere is a CONFIG_RTE_KNI_VHOST_VNET_HDR_EN configuration option in DPDK configuration file.\nBy default, it set to n, which means do not turn on the virtio net header,\nwhich is used to support additional features (such as, csum offload, vlan offload, generic-segmentation and so on),\nsince the kni-vhost does not yet support those features.\n\nEven if the option is turned on, kni-vhost will ignore the information that the header contains.\nWhen working with legacy virtio on the guest, it is better to turn off unsupported offload features using ethtool -K.\nOtherwise, there may be problems such as an incorrect L4 checksum error.\n" }, { "path": "doc/guides/prog_guide/link_bonding_poll_mode_drv_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nLink Bonding Poll Mode Driver Library\n=====================================\n\nIn addition to Poll Mode Drivers (PMDs) for physical and virtual hardware,\nDPDK also includes a pure-software library that\nallows physical PMD's to be bonded together to create a single logical PMD.\n\n.. figure:: img/bond-overview.*\n\n Bonded PMDs\n\n\nThe Link Bonding PMD library(librte_pmd_bond) supports bonding of groups of\n``rte_eth_dev`` ports of the same speed and duplex to provide\nsimilar the capabilities to that found in Linux bonding driver to allow the\naggregation of multiple (slave) NICs into a single logical interface between a\nserver and a switch. The new bonded PMD will then process these interfaces\nbased on the mode of operation specified to provide support for features such\nas redundant links, fault tolerance and/or load balancing.\n\nThe librte_pmd_bond library exports a C API which provides an API for the\ncreation of bonded devices as well as the configuration and management of the\nbonded device and its slave devices.\n\n.. note::\n\n The Link Bonding PMD Library is enabled by default in the build\n configuration files, the library can be disabled by setting\n ``CONFIG_RTE_LIBRTE_PMD_BOND=n`` and recompiling the DPDK.\n\nLink Bonding Modes Overview\n---------------------------\n\nCurrently the Link Bonding PMD library supports 4 modes of operation:\n\n* **Round-Robin (Mode 0):**\n\n.. figure:: img/bond-mode-0.*\n\n Round-Robin (Mode 0)\n\n\n This mode provides load balancing and fault tolerance by transmission of\n packets in sequential order from the first available slave device through\n the last. Packets are bulk dequeued from devices then serviced in a\n round-robin manner. This mode does not guarantee in order reception of\n packets and down stream should be able to handle out of order packets.\n\n* **Active Backup (Mode 1):**\n\n.. figure:: img/bond-mode-1.*\n\n Active Backup (Mode 1)\n\n\n In this mode only one slave in the bond is active at any time, a different\n slave becomes active if, and only if, the primary active slave fails,\n thereby providing fault tolerance to slave failure. The single logical\n bonded interface's MAC address is externally visible on only one NIC (port)\n to avoid confusing the network switch.\n\n* **Balance XOR (Mode 2):**\n\n.. figure:: img/bond-mode-2.*\n\n Balance XOR (Mode 2)\n\n\n This mode provides transmit load balancing (based on the selected\n transmission policy) and fault tolerance. The default policy (layer2) uses\n a simple calculation based on the packet flow source and destination MAC\n addresses as well as the number of active slaves available to the bonded\n device to classify the packet to a specific slave to transmit on. Alternate\n transmission policies supported are layer 2+3, this takes the IP source and\n destination addresses into the calculation of the transmit slave port and\n the final supported policy is layer 3+4, this uses IP source and\n destination addresses as well as the TCP/UDP source and destination port.\n\n.. note::\n The coloring differences of the packets are used to identify different flow\n classification calculated by the selected transmit policy\n\n\n* **Broadcast (Mode 3):**\n\n.. figure:: img/bond-mode-3.*\n\n Broadcast (Mode 3)\n\n\n This mode provides fault tolerance by transmission of packets on all slave\n ports.\n\n* **Link Aggregation 802.3AD (Mode 4):**\n\n.. figure:: img/bond-mode-4.*\n\n Link Aggregation 802.3AD (Mode 4)\n\n\n This mode provides dynamic link aggregation according to the 802.3ad\n specification. It negotiates and monitors aggregation groups that share the\n same speed and duplex settings using the selected balance transmit policy\n for balancing outgoing traffic.\n\n DPDK implementation of this mode provide some additional requirements of\n the application.\n\n #. It needs to call ``rte_eth_tx_burst`` and ``rte_eth_rx_burst`` with\n intervals period of less than 100ms.\n\n #. Calls to ``rte_eth_tx_burst`` must have a buffer size of at least 2xN,\n where N is the number of slaves. This is a space required for LACP\n frames. Additionally LACP packets are included in the statistics, but\n they are not returned to the application.\n\n* **Transmit Load Balancing (Mode 5):**\n\n.. figure:: img/bond-mode-5.*\n\n Transmit Load Balancing (Mode 5)\n\n\n This mode provides an adaptive transmit load balancing. It dynamically\n changes the transmitting slave, according to the computed load. Statistics\n are collected in 100ms intervals and scheduled every 10ms.\n\n\nImplementation Details\n----------------------\n\nThe librte_pmd_bond bonded device are compatible with the Ethernet device API\nexported by the Ethernet PMDs described in the *DPDK API Reference*.\n\nThe Link Bonding Library supports the creation of bonded devices at application\nstartup time during EAL initialization using the ``--vdev`` option as well as\nprogrammatically via the C API ``rte_eth_bond_create`` function.\n\nBonded devices support the dynamical addition and removal of slave devices using\nthe ``rte_eth_bond_slave_add`` / ``rte_eth_bond_slave_remove`` APIs.\n\nAfter a slave device is added to a bonded device slave is stopped using\n``rte_eth_dev_stop`` and then reconfigured using ``rte_eth_dev_configure``\nthe RX and TX queues are also reconfigured using ``rte_eth_tx_queue_setup`` /\n``rte_eth_rx_queue_setup`` with the parameters use to configure the bonding\ndevice.\n\nLink Status Change Interrupts / Polling\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nLink bonding devices support the registration of a link status change callback,\nusing the ``rte_eth_dev_callback_register`` API, this will be called when the\nstatus of the bonding device changes. For example in the case of a bonding\ndevice which has 3 slaves, the link status will change to up when one slave\nbecomes active or change to down when all slaves become inactive. There is no\ncallback notification when a single slave changes state and the previous\nconditions are not met. If a user wishes to monitor individual slaves then they\nmust register callbacks with that slave directly.\n\nThe link bonding library also supports devices which do not implement link\nstatus change interrupts, this is achieve by polling the devices link status at\na defined period which is set using the ``rte_eth_bond_link_monitoring_set``\nAPI, the default polling interval is 10ms. When a device is added as a slave to\na bonding device it is determined using the ``RTE_PCI_DRV_INTR_LSC`` flag\nwhether the device supports interrupts or whether the link status should be\nmonitored by polling it.\n\nRequirements / Limitations\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe current implementation only supports devices that support the same speed\nand duplex to be added as a slaves to the same bonded device. The bonded device\ninherits these attributes from the first active slave added to the bonded\ndevice and then all further slaves added to the bonded device must support\nthese parameters.\n\nA bonding device must have a minimum of one slave before the bonding device\nitself can be started.\n\nLike all other PMD, all functions exported by a PMD are lock-free functions\nthat are assumed not to be invoked in parallel on different logical cores to\nwork on the same target object.\n\nIt should also be noted that the PMD receive function should not be invoked\ndirectly on a slave devices after they have been to a bonded device since\npackets read directly from the slave device will no longer be available to the\nbonded device to read.\n\nConfiguration\n~~~~~~~~~~~~~\n\nLink bonding devices are created using the ``rte_eth_bond_create`` API\nwhich requires a unique device name, the bonding mode,\nand the socket Id to allocate the bonding device's resources on.\nThe other configurable parameters for a bonded device are its slave devices,\nits primary slave, a user defined MAC address and transmission policy to use if\nthe device is in balance XOR mode.\n\nSlave Devices\n^^^^^^^^^^^^^\n\nBonding devices support up to a maximum of ``RTE_MAX_ETHPORTS`` slave devices\nof the same speed and duplex. Ethernet devices can be added as a slave to a\nmaximum of one bonded device. Slave devices are reconfigured with the\nconfiguration of the bonded device on being added to a bonded device.\n\nThe bonded also guarantees to return the MAC address of the slave device to its\noriginal value of removal of a slave from it.\n\nPrimary Slave\n^^^^^^^^^^^^^\n\nThe primary slave is used to define the default port to use when a bonded\ndevice is in active backup mode. A different port will only be used if, and\nonly if, the current primary port goes down. If the user does not specify a\nprimary port it will default to being the first port added to the bonded device.\n\nMAC Address\n^^^^^^^^^^^\n\nThe bonded device can be configured with a user specified MAC address, this\naddress will be inherited by the some/all slave devices depending on the\noperating mode. If the device is in active backup mode then only the primary\ndevice will have the user specified MAC, all other slaves will retain their\noriginal MAC address. In mode 0, 2, 3, 4 all slaves devices are configure with\nthe bonded devices MAC address.\n\nIf a user defined MAC address is not defined then the bonded device will\ndefault to using the primary slaves MAC address.\n\nBalance XOR Transmit Policies\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThere are 3 supported transmission policies for bonded device running in\nBalance XOR mode. Layer 2, Layer 2+3, Layer 3+4.\n\n* **Layer 2:** Ethernet MAC address based balancing is the default\n transmission policy for Balance XOR bonding mode. It uses a simple XOR\n calculation on the source MAC address and destination MAC address of the\n packet and then calculate the modulus of this value to calculate the slave\n device to transmit the packet on.\n\n* **Layer 2 + 3:** Ethernet MAC address & IP Address based balancing uses a\n combination of source/destination MAC addresses and the source/destination\n IP addresses of the data packet to decide which slave port the packet will\n be transmitted on.\n\n* **Layer 3 + 4:** IP Address & UDP Port based balancing uses a combination\n of source/destination IP Address and the source/destination UDP ports of\n the packet of the data packet to decide which slave port the packet will be\n transmitted on.\n\nAll these policies support 802.1Q VLAN Ethernet packets, as well as IPv4, IPv6\nand UDP protocols for load balancing.\n\nUsing Link Bonding Devices\n--------------------------\n\nThe librte_pmd_bond library support two modes of device creation, the libraries\nexport full C API or using the EAL command line to statically configure link\nbonding devices at application startup. Using the EAL option it is possible to\nuse link bonding functionality transparently without specific knowledge of the\nlibraries API, this can be used, for example, to add bonding functionality,\nsuch as active backup, to an existing application which has no knowledge of\nthe link bonding C API.\n\nUsing the Poll Mode Driver from an Application\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nUsing the librte_pmd_bond libraries API it is possible to dynamically create\nand manage link bonding device from within any application. Link bonding\ndevice are created using the ``rte_eth_bond_create`` API which requires a\nunique device name, the link bonding mode to initial the device in and finally\nthe socket Id which to allocate the devices resources onto. After successful\ncreation of a bonding device it must be configured using the generic Ethernet\ndevice configure API ``rte_eth_dev_configure`` and then the RX and TX queues\nwhich will be used must be setup using ``rte_eth_tx_queue_setup`` /\n``rte_eth_rx_queue_setup``.\n\nSlave devices can be dynamically added and removed from a link bonding device\nusing the ``rte_eth_bond_slave_add`` / ``rte_eth_bond_slave_remove``\nAPIs but at least one slave device must be added to the link bonding device\nbefore it can be started using ``rte_eth_dev_start``.\n\nThe link status of a bonded device is dictated by that of its slaves, if all\nslave device link status are down or if all slaves are removed from the link\nbonding device then the link status of the bonding device will go down.\n\nIt is also possible to configure / query the configuration of the control\nparameters of a bonded device using the provided APIs\n``rte_eth_bond_mode_set/ get``, ``rte_eth_bond_primary_set/get``,\n``rte_eth_bond_mac_set/reset`` and ``rte_eth_bond_xmit_policy_set/get``.\n\nUsing Link Bonding Devices from the EAL Command Line\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nLink bonding devices can be created at application startup time using the\n``--vdev`` EAL command line option. The device name must start with the\neth_bond prefix followed by numbers or letters. The name must be unique for\neach device. Each device can have multiple options arranged in a comma\nseparated list. Multiple devices definitions can be arranged by calling the\n``--vdev`` option multiple times.\n\nDevice names and bonding options must be separated by commas as shown below:\n\n.. code-block:: console\n\n $RTE_TARGET/app/testpmd -c f -n 4 --vdev 'eth_bond0,bond_opt0=..,bond opt1=..'--vdev 'eth_bond1,bond _opt0=..,bond_opt1=..'\n\nLink Bonding EAL Options\n^^^^^^^^^^^^^^^^^^^^^^^^\n\nThere are multiple ways of definitions that can be assessed and combined as\nlong as the following two rules are respected:\n\n* A unique device name, in the format of eth_bondX is provided,\n where X can be any combination of numbers and/or letters,\n and the name is no greater than 32 characters long.\n\n* A least one slave device is provided with for each bonded device definition.\n\n* The operation mode of the bonded device being created is provided.\n\nThe different options are:\n\n* mode: Integer value defining the bonding mode of the device.\n Currently supports modes 0,1,2,3,4,5 (round-robin, active backup, balance,\n broadcast, link aggregation, transmit load balancing).\n\n.. code-block:: console\n\n mode=2\n\n* slave: Defines the PMD device which will be added as slave to the bonded\n device. This option can be selected multiple time, for each device to be\n added as a slave. Physical devices should be specified using their PCI\n address, in the format domain:bus:devid.function\n\n.. code-block:: console\n\n slave=0000:0a:00.0,slave=0000:0a:00.1\n\n* primary: Optional parameter which defines the primary slave port,\n is used in active backup mode to select the primary slave for data TX/RX if\n it is available. The primary port also is used to select the MAC address to\n use when it is not defined by the user. This defaults to the first slave\n added to the device if it is specified. The primary device must be a slave\n of the bonded device.\n\n.. code-block:: console\n\n primary=0000:0a:00.0\n\n* socket_id: Optional parameter used to select which socket on a NUMA device\n the bonded devices resources will be allocated on.\n\n.. code-block:: console\n\n socket_id=0\n\n* mac: Optional parameter to select a MAC address for link bonding device,\n this overrides the value of the primary slave device.\n\n.. code-block:: console\n\n mac=00:1e:67:1d:fd:1d\n\n* xmit_policy: Optional parameter which defines the transmission policy when\n the bonded device is in balance mode. If not user specified this defaults\n to l2 (layer 2) forwarding, the other transmission policies available are\n l23 (layer 2+3) and l34 (layer 3+4)\n\n.. code-block:: console\n\n xmit_policy=l23\n\n* lsc_poll_period_ms: Optional parameter which defines the polling interval\n in milli-seconds at which devices which don't support lsc interrupts are\n checked for a change in the devices link status\n\n.. code-block:: console\n\n lsc_poll_period_ms=100\n\n* up_delay: Optional parameter which adds a delay in milli-seconds to the\n propagation of a devices link status changing to up, by default this\n parameter is zero.\n\n.. code-block:: console\n\n up_delay=10\n\n* down_delay: Optional parameter which adds a delay in milli-seconds to the\n propagation of a devices link status changing to down, by default this\n parameter is zero.\n\n.. code-block:: console\n\n down_delay=50\n\nExamples of Usage\n^^^^^^^^^^^^^^^^^\n\nCreate a bonded device in round robin mode with two slaves specified by their PCI address:\n\n.. code-block:: console\n\n $RTE_TARGET/app/testpmd -c '0xf' -n 4 --vdev 'eth_bond0,mode=0, slave=0000:00a:00.01,slave=0000:004:00.00' -- --port-topology=chained\n\nCreate a bonded device in round robin mode with two slaves specified by their PCI address and an overriding MAC address:\n\n.. code-block:: console\n\n $RTE_TARGET/app/testpmd -c '0xf' -n 4 --vdev 'eth_bond0,mode=0, slave=0000:00a:00.01,slave=0000:004:00.00,mac=00:1e:67:1d:fd:1d' -- --port-topology=chained\n\nCreate a bonded device in active backup mode with two slaves specified, and a primary slave specified by their PCI addresses:\n\n.. code-block:: console\n\n $RTE_TARGET/app/testpmd -c '0xf' -n 4 --vdev 'eth_bond0,mode=1, slave=0000:00a:00.01,slave=0000:004:00.00,primary=0000:00a:00.01' -- --port-topology=chained\n\nCreate a bonded device in balance mode with two slaves specified by their PCI addresses, and a transmission policy of layer 3 + 4 forwarding:\n\n.. code-block:: console\n\n $RTE_TARGET/app/testpmd -c '0xf' -n 4 --vdev 'eth_bond0,mode=2, slave=0000:00a:00.01,slave=0000:004:00.00,xmit_policy=l34' -- --port-topology=chained\n" }, { "path": "doc/guides/prog_guide/lpm6_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nLPM6 Library\n============\n\nThe LPM6 (LPM for IPv6) library component implements the Longest Prefix Match (LPM) table search method for 128-bit keys\nthat is typically used to find the best match route in IPv6 forwarding applications.\n\nLPM6 API Overview\n-----------------\n\nThe main configuration parameters for the LPM6 library are:\n\n* Maximum number of rules: This defines the size of the table that holds the rules,\n and therefore the maximum number of rules that can be added.\n\n* Number of tbl8s: A tbl8 is a node of the trie that the LPM6 algorithm is based on.\n\nThis parameter is related to the number of rules you can have,\nbut there is no way to accurately predict the number needed to hold a specific number of rules,\nsince it strongly depends on the depth and IP address of every rule.\nOne tbl8 consumes 1 kb of memory. As a recommendation, 65536 tbl8s should be sufficient to store\nseveral thousand IPv6 rules, but the number can vary depending on the case.\n\nAn LPM prefix is represented by a pair of parameters (128-bit key, depth), with depth in the range of 1 to 128.\nAn LPM rule is represented by an LPM prefix and some user data associated with the prefix.\nThe prefix serves as the unique identifier for the LPM rule.\nIn this implementation, the user data is 1-byte long and is called \"next hop\",\nwhich corresponds to its main use of storing the ID of the next hop in a routing table entry.\n\nThe main methods exported for the LPM component are:\n\n* Add LPM rule: The LPM rule is provided as input.\n If there is no rule with the same prefix present in the table, then the new rule is added to the LPM table.\n If a rule with the same prefix is already present in the table, the next hop of the rule is updated.\n An error is returned when there is no available space left.\n\n* Delete LPM rule: The prefix of the LPM rule is provided as input.\n If a rule with the specified prefix is present in the LPM table, then it is removed.\n\n* Lookup LPM key: The 128-bit key is provided as input.\n The algorithm selects the rule that represents the best match for the given key and returns the next hop of that rule.\n In the case that there are multiple rules present in the LPM table that have the same 128-bit value,\n the algorithm picks the rule with the highest depth as the best match rule,\n which means the rule has the highest number of most significant bits matching between the input key and the rule key.\n\nImplementation Details\n~~~~~~~~~~~~~~~~~~~~~~\n\nThis is a modification of the algorithm used for IPv4 (see Section 19.2 \"Implementation Details\").\nIn this case, instead of using two levels, one with a tbl24 and a second with a tbl8, 14 levels are used.\n\nThe implementation can be seen as a multi-bit trie where the *stride*\nor number of bits inspected on each level varies from level to level.\nSpecifically, 24 bits are inspected on the root node, and the remaining 104 bits are inspected in groups of 8 bits.\nThis effectively means that the trie has 14 levels at the most, depending on the rules that are added to the table.\n\nThe algorithm allows the lookup operation to be performed with a number of memory accesses\nthat directly depends on the length of the rule and\nwhether there are other rules with bigger depths and the same key in the data structure.\nIt can vary from 1 to 14 memory accesses, with 5 being the average value for the lengths\nthat are most commonly used in IPv6.\n\nThe main data structure is built using the following elements:\n\n* A table with 224 entries\n\n* A number of tables, configurable by the user through the API, with 28 entries\n\nThe first table, called tbl24, is indexed using the first 24 bits of the IP address be looked up,\nwhile the rest of the tables, called tbl8s,\nare indexed using the rest of the bytes of the IP address, in chunks of 8 bits.\nThis means that depending on the outcome of trying to match the IP address of an incoming packet to the rule stored in the tbl24\nor the subsequent tbl8s we might need to continue the lookup process in deeper levels of the tree.\n\nSimilar to the limitation presented in the algorithm for IPv4,\nto store every possible IPv6 rule, we would need a table with 2^128 entries.\nThis is not feasible due to resource restrictions.\n\nBy splitting the process in different tables/levels and limiting the number of tbl8s,\nwe can greatly reduce memory consumption while maintaining a very good lookup speed (one memory access per level).\n\n\n.. figure:: img/tbl24_tbl8_tbl8.*\n\n Table split into different levels\n\n\nAn entry in a table contains the following fields:\n\n* next hop / index to the tbl8\n\n* depth of the rule (length)\n\n* valid flag\n\n* valid group flag\n\n* external entry flag\n\nThe first field can either contain a number indicating the tbl8 in which the lookup process should continue\nor the next hop itself if the longest prefix match has already been found.\nThe depth or length of the rule is the number of bits of the rule that is stored in a specific entry.\nThe flags are used to determine whether the entry/table is valid or not\nand whether the search process have finished or not respectively.\n\nBoth types of tables share the same structure.\n\nThe other main data structure is a table containing the main information about the rules (IP, next hop and depth).\nThis is a higher level table, used for different things:\n\n* Check whether a rule already exists or not, prior to addition or deletion,\n without having to actually perform a lookup.\n\nWhen deleting, to check whether there is a rule containing the one that is to be deleted.\nThis is important, since the main data structure will have to be updated accordingly.\n\nAddition\n~~~~~~~~\n\nWhen adding a rule, there are different possibilities.\nIf the rule's depth is exactly 24 bits, then:\n\n* Use the rule (IP address) as an index to the tbl24.\n\n* If the entry is invalid (i.e. it doesn't already contain a rule) then set its next hop to its value,\n the valid flag to 1 (meaning this entry is in use),\n and the external entry flag to 0 (meaning the lookup process ends at this point,\n since this is the longest prefix that matches).\n\nIf the rule's depth is bigger than 24 bits but a multiple of 8, then:\n\n* Use the first 24 bits of the rule as an index to the tbl24.\n\n* If the entry is invalid (i.e. it doesn't already contain a rule) then look for a free tbl8,\n set the index to the tbl8 to this value,\n the valid flag to 1 (meaning this entry is in use),\n and the external entry flag to 1\n (meaning the lookup process must continue since the rule hasn't been explored completely).\n\n* Use the following 8 bits of the rule as an index to the next tbl8.\n\n* Repeat the process until the tbl8 at the right level (depending on the depth) has been reached\n and fill it with the next hop, setting the next entry flag to 0.\n\nIf the rule's depth is any other value, prefix expansion must be performed.\nThis means the rule is copied to all the entries (as long as they are not in use) which would also cause a match.\n\nAs a simple example, let's assume the depth is 20 bits.\nThis means that there are 2^(24-20) = 16 different combinations of the first 24 bits of an IP address that would cause a match.\nHence, in this case, we copy the exact same entry to every position indexed by one of these combinations.\n\nBy doing this we ensure that during the lookup process, if a rule matching the IP address exists,\nit is found in, at the most, 14 memory accesses,\ndepending on how many times we need to move to the next table.\nPrefix expansion is one of the keys of this algorithm, since it improves the speed dramatically by adding redundancy.\n\nPrefix expansion can be performed at any level.\nSo, for example, is the depth is 34 bits, it will be performed in the third level (second tbl8-based level).\n\nLookup\n~~~~~~\n\nThe lookup process is much simpler and quicker. In this case:\n\n* Use the first 24 bits of the IP address as an index to the tbl24.\n If the entry is not in use, then it means we don't have a rule matching this IP.\n If it is valid and the external entry flag is set to 0, then the next hop is returned.\n\n* If it is valid and the external entry flag is set to 1, then we use the tbl8 index to find out the tbl8 to be checked,\n and the next 8 bits of the IP address as an index to this table.\n Similarly, if the entry is not in use, then we don't have a rule matching this IP address.\n If it is valid then check the external entry flag for a new tbl8 to be inspected.\n\n* Repeat the process until either we find an invalid entry (lookup miss) or a valid entry with the external entry flag set to 0.\n Return the next hop in the latter case.\n\nLimitations in the Number of Rules\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThere are different things that limit the number of rules that can be added.\nThe first one is the maximum number of rules, which is a parameter passed through the API.\nOnce this number is reached, it is not possible to add any more rules to the routing table unless one or more are removed.\n\nThe second limitation is in the number of tbl8s available.\nIf we exhaust tbl8s, we won't be able to add any more rules.\nHow to know how many of them are necessary for a specific routing table is hard to determine in advance.\n\nIn this algorithm, the maximum number of tbl8s a single rule can consume is 13,\nwhich is the number of levels minus one, since the first three bytes are resolved in the tbl24. However:\n\n* Typically, on IPv6, routes are not longer than 48 bits, which means rules usually take up to 3 tbl8s.\n\nAs explained in the LPM for IPv4 algorithm, it is possible and very likely that several rules will share one or more tbl8s,\ndepending on what their first bytes are.\nIf they share the same first 24 bits, for instance, the tbl8 at the second level will be shared.\nThis might happen again in deeper levels, so, effectively,\ntwo 48 bit-long rules may use the same three tbl8s if the only difference is in their last byte.\n\nThe number of tbl8s is a parameter exposed to the user through the API in this version of the algorithm,\ndue to its impact in memory consumption and the number or rules that can be added to the LPM table.\nOne tbl8 consumes 1 kilobyte of memory.\n\nUse Case: IPv6 Forwarding\n-------------------------\n\nThe LPM algorithm is used to implement the Classless Inter-Domain Routing (CIDR) strategy used by routers implementing IP forwarding.\n" }, { "path": "doc/guides/prog_guide/lpm_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _LPM_Library:\n\nLPM Library\n===========\n\nThe DPDK LPM library component implements the Longest Prefix Match (LPM) table search method for 32-bit keys\nthat is typically used to find the best route match in IP forwarding applications.\n\nLPM API Overview\n----------------\n\nThe main configuration parameter for LPM component instances is the maximum number of rules to support.\nAn LPM prefix is represented by a pair of parameters (32- bit key, depth), with depth in the range of 1 to 32.\nAn LPM rule is represented by an LPM prefix and some user data associated with the prefix.\nThe prefix serves as the unique identifier of the LPM rule.\nIn this implementation, the user data is 1-byte long and is called next hop,\nin correlation with its main use of storing the ID of the next hop in a routing table entry.\n\nThe main methods exported by the LPM component are:\n\n* Add LPM rule: The LPM rule is provided as input.\n If there is no rule with the same prefix present in the table, then the new rule is added to the LPM table.\n If a rule with the same prefix is already present in the table, the next hop of the rule is updated.\n An error is returned when there is no available rule space left.\n\n* Delete LPM rule: The prefix of the LPM rule is provided as input.\n If a rule with the specified prefix is present in the LPM table, then it is removed.\n\n* Lookup LPM key: The 32-bit key is provided as input.\n The algorithm selects the rule that represents the best match for the given key and returns the next hop of that rule.\n In the case that there are multiple rules present in the LPM table that have the same 32-bit key,\n the algorithm picks the rule with the highest depth as the best match rule,\n which means that the rule has the highest number of most significant bits matching between the input key and the rule key.\n\nImplementation Details\n----------------------\n\nThe current implementation uses a variation of the DIR-24-8 algorithm that trades memory usage for improved LPM lookup speed.\nThe algorithm allows the lookup operation to be performed with typically a single memory read access.\nIn the statistically rare case when the best match rule is having a depth bigger than 24,\nthe lookup operation requires two memory read accesses.\nTherefore, the performance of the LPM lookup operation is greatly influenced by\nwhether the specific memory location is present in the processor cache or not.\n\nThe main data structure is built using the following elements:\n\n* A table with 2^24 entries.\n\n* A number of tables (RTE_LPM_TBL8_NUM_GROUPS) with 2^8 entries.\n\nThe first table, called tbl24, is indexed using the first 24 bits of the IP address to be looked up,\nwhile the second table(s), called tbl8, is indexed using the last 8 bits of the IP address.\nThis means that depending on the outcome of trying to match the IP address of an incoming packet to the rule stored in the tbl24\nwe might need to continue the lookup process in the second level.\n\nSince every entry of the tbl24 can potentially point to a tbl8, ideally, we would have 2^24 tbl8s,\nwhich would be the same as having a single table with 2^32 entries.\nThis is not feasible due to resource restrictions.\nInstead, this approach takes advantage of the fact that rules longer than 24 bits are very rare.\nBy splitting the process in two different tables/levels and limiting the number of tbl8s,\nwe can greatly reduce memory consumption while maintaining a very good lookup speed (one memory access, most of the times).\n\n\n.. figure:: img/tbl24_tbl8.*\n\n Table split into different levels\n\n\nAn entry in tbl24 contains the following fields:\n\n* next hop / index to the tbl8\n\n* valid flag\n\n* external entry flag\n\n* depth of the rule (length)\n\nThe first field can either contain a number indicating the tbl8 in which the lookup process should continue\nor the next hop itself if the longest prefix match has already been found.\nThe two flags are used to determine whether the entry is valid or not and\nwhether the search process have finished or not respectively.\nThe depth or length of the rule is the number of bits of the rule that is stored in a specific entry.\n\nAn entry in a tbl8 contains the following fields:\n\n* next hop\n\n* valid\n\n* valid group\n\n* depth\n\nNext hop and depth contain the same information as in the tbl24.\nThe two flags show whether the entry and the table are valid respectively.\n\nThe other main data structure is a table containing the main information about the rules (IP and next hop).\nThis is a higher level table, used for different things:\n\n* Check whether a rule already exists or not, prior to addition or deletion,\n without having to actually perform a lookup.\n\n* When deleting, to check whether there is a rule containing the one that is to be deleted.\n This is important, since the main data structure will have to be updated accordingly.\n\nAddition\n~~~~~~~~\n\nWhen adding a rule, there are different possibilities.\nIf the rule's depth is exactly 24 bits, then:\n\n* Use the rule (IP address) as an index to the tbl24.\n\n* If the entry is invalid (i.e. it doesn't already contain a rule) then set its next hop to its value,\n the valid flag to 1 (meaning this entry is in use),\n and the external entry flag to 0\n (meaning the lookup process ends at this point, since this is the longest prefix that matches).\n\nIf the rule's depth is exactly 32 bits, then:\n\n* Use the first 24 bits of the rule as an index to the tbl24.\n\n* If the entry is invalid (i.e. it doesn't already contain a rule) then look for a free tbl8,\n set the index to the tbl8 to this value,\n the valid flag to 1 (meaning this entry is in use), and the external entry flag to 1\n (meaning the lookup process must continue since the rule hasn't been explored completely).\n\nIf the rule's depth is any other value, prefix expansion must be performed.\nThis means the rule is copied to all the entries (as long as they are not in use) which would also cause a match.\n\nAs a simple example, let's assume the depth is 20 bits.\nThis means that there are 2^(24 - 20) = 16 different combinations of the first 24 bits of an IP address that\nwould cause a match.\nHence, in this case, we copy the exact same entry to every position indexed by one of these combinations.\n\nBy doing this we ensure that during the lookup process, if a rule matching the IP address exists,\nit is found in either one or two memory accesses,\ndepending on whether we need to move to the next table or not.\nPrefix expansion is one of the keys of this algorithm,\nsince it improves the speed dramatically by adding redundancy.\n\nLookup\n~~~~~~\n\nThe lookup process is much simpler and quicker. In this case:\n\n* Use the first 24 bits of the IP address as an index to the tbl24.\n If the entry is not in use, then it means we don't have a rule matching this IP.\n If it is valid and the external entry flag is set to 0, then the next hop is returned.\n\n* If it is valid and the external entry flag is set to 1,\n then we use the tbl8 index to find out the tbl8 to be checked,\n and the last 8 bits of the IP address as an index to this table.\n Similarly, if the entry is not in use, then we don't have a rule matching this IP address.\n If it is valid then the next hop is returned.\n\nLimitations in the Number of Rules\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThere are different things that limit the number of rules that can be added.\nThe first one is the maximum number of rules, which is a parameter passed through the API.\nOnce this number is reached,\nit is not possible to add any more rules to the routing table unless one or more are removed.\n\nThe second reason is an intrinsic limitation of the algorithm.\nAs explained before, to avoid high memory consumption, the number of tbl8s is limited in compilation time\n(this value is by default 256).\nIf we exhaust tbl8s, we won't be able to add any more rules.\nHow many of them are necessary for a specific routing table is hard to determine in advance.\n\nA tbl8 is consumed whenever we have a new rule with depth bigger than 24,\nand the first 24 bits of this rule are not the same as the first 24 bits of a rule previously added.\nIf they are, then the new rule will share the same tbl8 than the previous one,\nsince the only difference between the two rules is within the last byte.\n\nWith the default value of 256, we can have up to 256 rules longer than 24 bits that differ on their first three bytes.\nSince routes longer than 24 bits are unlikely, this shouldn't be a problem in most setups.\nEven if it is, however, the number of tbl8s can be modified.\n\nUse Case: IPv4 Forwarding\n~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe LPM algorithm is used to implement Classless Inter-Domain Routing (CIDR) strategy used by routers implementing IPv4 forwarding.\n\nReferences\n~~~~~~~~~~\n\n* RFC1519 Classless Inter-Domain Routing (CIDR): an Address Assignment and Aggregation Strategy,\n `http://www.ietf.org/rfc/rfc1519 `_\n\n* Pankaj Gupta, Algorithms for Routing Lookups and Packet Classification, PhD Thesis, Stanford University,\n 2000 (`http://klamath.stanford.edu/~pankaj/thesis/ thesis_1sided.pdf `_ )\n" }, { "path": "doc/guides/prog_guide/mbuf_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Mbuf_Library:\n\nMbuf Library\n============\n\nThe mbuf library provides the ability to allocate and free buffers (mbufs)\nthat may be used by the DPDK application to store message buffers.\nThe message buffers are stored in a mempool, using the :ref:`Mempool Library `.\n\nA rte_mbuf struct can carry network packet buffers\nor generic control buffers (indicated by the CTRL_MBUF_FLAG).\nThis can be extended to other types.\nThe rte_mbuf header structure is kept as small as possible and currently uses\njust two cache lines, with the most frequently used fields being on the first\nof the two cache lines.\n\nDesign of Packet Buffers\n------------------------\n\nFor the storage of the packet data (including protocol headers), two approaches were considered:\n\n#. Embed metadata within a single memory buffer the structure followed by a fixed size area for the packet data.\n\n#. Use separate memory buffers for the metadata structure and for the packet data.\n\nThe advantage of the first method is that it only needs one operation to allocate/free the whole memory representation of a packet.\nOn the other hand, the second method is more flexible and allows\nthe complete separation of the allocation of metadata structures from the allocation of packet data buffers.\n\nThe first method was chosen for the DPDK.\nThe metadata contains control information such as message type, length,\noffset to the start of the data and a pointer for additional mbuf structures allowing buffer chaining.\n\nMessage buffers that are used to carry network packets can handle buffer chaining\nwhere multiple buffers are required to hold the complete packet.\nThis is the case for jumbo frames that are composed of many mbufs linked together through their next field.\n\nFor a newly allocated mbuf, the area at which the data begins in the message buffer is\nRTE_PKTMBUF_HEADROOM bytes after the beginning of the buffer, which is cache aligned.\nMessage buffers may be used to carry control information, packets, events,\nand so on between different entities in the system.\nMessage buffers may also use their buffer pointers to point to other message buffer data sections or other structures.\n\n:numref:`figure_mbuf1` and :numref:`figure_mbuf2` show some of these scenarios.\n\n.. _figure_mbuf1:\n\n.. figure:: img/mbuf1.*\n\n An mbuf with One Segment\n\n\n.. _figure_mbuf2:\n\n.. figure:: img/mbuf2.*\n\n An mbuf with Three Segments\n\n\nThe Buffer Manager implements a fairly standard set of buffer access functions to manipulate network packets.\n\nBuffers Stored in Memory Pools\n------------------------------\n\nThe Buffer Manager uses the :ref:`Mempool Library ` to allocate buffers.\nTherefore, it ensures that the packet header is interleaved optimally across the channels and ranks for L3 processing.\nAn mbuf contains a field indicating the pool that it originated from.\nWhen calling rte_ctrlmbuf_free(m) or rte_pktmbuf_free(m), the mbuf returns to its original pool.\n\nConstructors\n------------\n\nPacket and control mbuf constructors are provided by the API.\nThe rte_pktmbuf_init() and rte_ctrlmbuf_init() functions initialize some fields in the mbuf structure that\nare not modified by the user once created (mbuf type, origin pool, buffer start address, and so on).\nThis function is given as a callback function to the rte_mempool_create() function at pool creation time.\n\nAllocating and Freeing mbufs\n----------------------------\n\nAllocating a new mbuf requires the user to specify the mempool from which the mbuf should be taken.\nFor any newly-allocated mbuf, it contains one segment, with a length of 0.\nThe offset to data is initialized to have some bytes of headroom in the buffer (RTE_PKTMBUF_HEADROOM).\n\nFreeing a mbuf means returning it into its original mempool.\nThe content of an mbuf is not modified when it is stored in a pool (as a free mbuf).\nFields initialized by the constructor do not need to be re-initialized at mbuf allocation.\n\nWhen freeing a packet mbuf that contains several segments, all of them are freed and returned to their original mempool.\n\nManipulating mbufs\n------------------\n\nThis library provides some functions for manipulating the data in a packet mbuf. For instance:\n\n * Get data length\n\n * Get a pointer to the start of data\n\n * Prepend data before data\n\n * Append data after data\n\n * Remove data at the beginning of the buffer (rte_pktmbuf_adj())\n\n * Remove data at the end of the buffer (rte_pktmbuf_trim()) Refer to the *DPDK API Reference* for details.\n\nMeta Information\n----------------\n\nSome information is retrieved by the network driver and stored in an mbuf to make processing easier.\nFor instance, the VLAN, the RSS hash result (see :ref:`Poll Mode Driver `)\nand a flag indicating that the checksum was computed by hardware.\n\nAn mbuf also contains the input port (where it comes from), and the number of segment mbufs in the chain.\n\nFor chained buffers, only the first mbuf of the chain stores this meta information.\n\nFor instance, this is the case on RX side for the IEEE1588 packet\ntimestamp mechanism, the VLAN tagging and the IP checksum computation.\n\nOn TX side, it is also possible for an application to delegate some\nprocessing to the hardware if it supports it. For instance, the\nPKT_TX_IP_CKSUM flag allows to offload the computation of the IPv4\nchecksum.\n\nThe following examples explain how to configure different TX offloads on\na vxlan-encapsulated tcp packet:\n``out_eth/out_ip/out_udp/vxlan/in_eth/in_ip/in_tcp/payload``\n\n- calculate checksum of out_ip::\n\n mb->l2_len = len(out_eth)\n mb->l3_len = len(out_ip)\n mb->ol_flags |= PKT_TX_IPV4 | PKT_TX_IP_CSUM\n set out_ip checksum to 0 in the packet\n\n This is supported on hardware advertising DEV_TX_OFFLOAD_IPV4_CKSUM.\n\n- calculate checksum of out_ip and out_udp::\n\n mb->l2_len = len(out_eth)\n mb->l3_len = len(out_ip)\n mb->ol_flags |= PKT_TX_IPV4 | PKT_TX_IP_CSUM | PKT_TX_UDP_CKSUM\n set out_ip checksum to 0 in the packet\n set out_udp checksum to pseudo header using rte_ipv4_phdr_cksum()\n\n This is supported on hardware advertising DEV_TX_OFFLOAD_IPV4_CKSUM\n and DEV_TX_OFFLOAD_UDP_CKSUM.\n\n- calculate checksum of in_ip::\n\n mb->l2_len = len(out_eth + out_ip + out_udp + vxlan + in_eth)\n mb->l3_len = len(in_ip)\n mb->ol_flags |= PKT_TX_IPV4 | PKT_TX_IP_CSUM\n set in_ip checksum to 0 in the packet\n\n This is similar to case 1), but l2_len is different. It is supported\n on hardware advertising DEV_TX_OFFLOAD_IPV4_CKSUM.\n Note that it can only work if outer L4 checksum is 0.\n\n- calculate checksum of in_ip and in_tcp::\n\n mb->l2_len = len(out_eth + out_ip + out_udp + vxlan + in_eth)\n mb->l3_len = len(in_ip)\n mb->ol_flags |= PKT_TX_IPV4 | PKT_TX_IP_CSUM | PKT_TX_TCP_CKSUM\n set in_ip checksum to 0 in the packet\n set in_tcp checksum to pseudo header using rte_ipv4_phdr_cksum()\n\n This is similar to case 2), but l2_len is different. It is supported\n on hardware advertising DEV_TX_OFFLOAD_IPV4_CKSUM and\n DEV_TX_OFFLOAD_TCP_CKSUM.\n Note that it can only work if outer L4 checksum is 0.\n\n- segment inner TCP::\n\n mb->l2_len = len(out_eth + out_ip + out_udp + vxlan + in_eth)\n mb->l3_len = len(in_ip)\n mb->l4_len = len(in_tcp)\n mb->ol_flags |= PKT_TX_IPV4 | PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM |\n PKT_TX_TCP_SEG;\n set in_ip checksum to 0 in the packet\n set in_tcp checksum to pseudo header without including the IP\n payload length using rte_ipv4_phdr_cksum()\n\n This is supported on hardware advertising DEV_TX_OFFLOAD_TCP_TSO.\n Note that it can only work if outer L4 checksum is 0.\n\n- calculate checksum of out_ip, in_ip, in_tcp::\n\n mb->outer_l2_len = len(out_eth)\n mb->outer_l3_len = len(out_ip)\n mb->l2_len = len(out_udp + vxlan + in_eth)\n mb->l3_len = len(in_ip)\n mb->ol_flags |= PKT_TX_OUTER_IPV4 | PKT_TX_OUTER_IP_CKSUM | \\\n PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM;\n set out_ip checksum to 0 in the packet\n set in_ip checksum to 0 in the packet\n set in_tcp checksum to pseudo header using rte_ipv4_phdr_cksum()\n\n This is supported on hardware advertising DEV_TX_OFFLOAD_IPV4_CKSUM,\n DEV_TX_OFFLOAD_UDP_CKSUM and DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM.\n\nThe list of flags and their precise meaning is described in the mbuf API\ndocumentation (rte_mbuf.h). Also refer to the testpmd source code\n(specifically the csumonly.c file) for details.\n\nDirect and Indirect Buffers\n---------------------------\n\nA direct buffer is a buffer that is completely separate and self-contained.\nAn indirect buffer behaves like a direct buffer but for the fact that the buffer pointer and\ndata offset in it refer to data in another direct buffer.\nThis is useful in situations where packets need to be duplicated or fragmented,\nsince indirect buffers provide the means to reuse the same packet data across multiple buffers.\n\nA buffer becomes indirect when it is \"attached\" to a direct buffer using the rte_pktmbuf_attach() function.\nEach buffer has a reference counter field and whenever an indirect buffer is attached to the direct buffer,\nthe reference counter on the direct buffer is incremented.\nSimilarly, whenever the indirect buffer is detached, the reference counter on the direct buffer is decremented.\nIf the resulting reference counter is equal to 0, the direct buffer is freed since it is no longer in use.\n\nThere are a few things to remember when dealing with indirect buffers.\nFirst of all, it is not possible to attach an indirect buffer to another indirect buffer.\nSecondly, for a buffer to become indirect, its reference counter must be equal to 1,\nthat is, it must not be already referenced by another indirect buffer.\nFinally, it is not possible to reattach an indirect buffer to the direct buffer (unless it is detached first).\n\nWhile the attach/detach operations can be invoked directly using the recommended rte_pktmbuf_attach() and rte_pktmbuf_detach() functions,\nit is suggested to use the higher-level rte_pktmbuf_clone() function,\nwhich takes care of the correct initialization of an indirect buffer and can clone buffers with multiple segments.\n\nSince indirect buffers are not supposed to actually hold any data,\nthe memory pool for indirect buffers should be configured to indicate the reduced memory consumption.\nExamples of the initialization of a memory pool for indirect buffers (as well as use case examples for indirect buffers)\ncan be found in several of the sample applications, for example, the IPv4 Multicast sample application.\n\nDebug\n-----\n\nIn debug mode (CONFIG_RTE_MBUF_DEBUG is enabled),\nthe functions of the mbuf library perform sanity checks before any operation (such as, buffer corruption, bad type, and so on).\n\nUse Cases\n---------\n\nAll networking application should use mbufs to transport network packets.\n" }, { "path": "doc/guides/prog_guide/mempool_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Mempool_Library:\n\nMempool Library\n===============\n\nA memory pool is an allocator of a fixed-sized object.\nIn the DPDK, it is identified by name and uses a ring to store free objects.\nIt provides some other optional services such as a per-core object cache and\nan alignment helper to ensure that objects are padded to spread them equally on all DRAM or DDR3 channels.\n\nThis library is used by the\n:ref:`Mbuf Library ` and the\n:ref:`Environment Abstraction Layer ` (for logging history).\n\nCookies\n-------\n\nIn debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled), cookies are added at the beginning and end of allocated blocks.\nThe allocated objects then contain overwrite protection fields to help debugging buffer overflows.\n\nStats\n-----\n\nIn debug mode (CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG is enabled),\nstatistics about get from/put in the pool are stored in the mempool structure.\nStatistics are per-lcore to avoid concurrent access to statistics counters.\n\nMemory Alignment Constraints\n----------------------------\n\nDepending on hardware memory configuration, performance can be greatly improved by adding a specific padding between objects.\nThe objective is to ensure that the beginning of each object starts on a different channel and rank in memory so that all channels are equally loaded.\n\nThis is particularly true for packet buffers when doing L3 forwarding or flow classification.\nOnly the first 64 bytes are accessed, so performance can be increased by spreading the start addresses of objects among the different channels.\n\nThe number of ranks on any DIMM is the number of independent sets of DRAMs that can be accessed for the full data bit-width of the DIMM.\nThe ranks cannot be accessed simultaneously since they share the same data path.\nThe physical layout of the DRAM chips on the DIMM itself does not necessarily relate to the number of ranks.\n\nWhen running an application, the EAL command line options provide the ability to add the number of memory channels and ranks.\n\n.. note::\n\n The command line must always have the number of memory channels specified for the processor.\n\nExamples of alignment for different DIMM architectures are shown in\n:numref:`figure_memory-management` and :numref:`figure_memory-management2`.\n\n.. _figure_memory-management:\n\n.. figure:: img/memory-management.*\n\n Two Channels and Quad-ranked DIMM Example\n\n\nIn this case, the assumption is that a packet is 16 blocks of 64 bytes, which is not true.\n\nThe Intel® 5520 chipset has three channels, so in most cases,\nno padding is required between objects (except for objects whose size are n x 3 x 64 bytes blocks).\n\n.. _figure_memory-management2:\n\n.. figure:: img/memory-management2.*\n\n Three Channels and Two Dual-ranked DIMM Example\n\n\nWhen creating a new pool, the user can specify to use this feature or not.\n\nLocal Cache\n-----------\n\nIn terms of CPU usage, the cost of multiple cores accessing a memory pool's ring of free buffers may be high\nsince each access requires a compare-and-set (CAS) operation.\nTo avoid having too many access requests to the memory pool's ring,\nthe memory pool allocator can maintain a per-core cache and do bulk requests to the memory pool's ring,\nvia the cache with many fewer locks on the actual memory pool structure.\nIn this way, each core has full access to its own cache (with locks) of free objects and\nonly when the cache fills does the core need to shuffle some of the free objects back to the pools ring or\nobtain more objects when the cache is empty.\n\nWhile this may mean a number of buffers may sit idle on some core's cache,\nthe speed at which a core can access its own cache for a specific memory pool without locks provides performance gains.\n\nThe cache is composed of a small, per-core table of pointers and its length (used as a stack).\nThis cache can be enabled or disabled at creation of the pool.\n\nThe maximum size of the cache is static and is defined at compilation time (CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE).\n\n:numref:`figure_mempool` shows a cache in operation.\n\n.. _figure_mempool:\n\n.. figure:: img/mempool.*\n\n A mempool in Memory with its Associated Ring\n\n\nUse Cases\n---------\n\nAll allocations that require a high level of performance should use a pool-based memory allocator.\nBelow are some examples:\n\n* :ref:`Mbuf Library `\n\n* :ref:`Environment Abstraction Layer ` , for logging service\n\n* Any application that needs to allocate fixed-sized objects in the data plane and that will be continuously utilized by the system.\n" }, { "path": "doc/guides/prog_guide/multi_proc_support.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Multi-process_Support:\n\nMulti-process Support\n=====================\n\nIn the DPDK, multi-process support is designed to allow a group of DPDK processes\nto work together in a simple transparent manner to perform packet processing,\nor other workloads, on Intel® architecture hardware.\nTo support this functionality,\na number of additions have been made to the core DPDK Environment Abstraction Layer (EAL).\n\nThe EAL has been modified to allow different types of DPDK processes to be spawned,\neach with different permissions on the hugepage memory used by the applications.\nFor now, there are two types of process specified:\n\n* primary processes, which can initialize and which have full permissions on shared memory\n\n* secondary processes, which cannot initialize shared memory,\n but can attach to pre- initialized shared memory and create objects in it.\n\nStandalone DPDK processes are primary processes,\nwhile secondary processes can only run alongside a primary process or\nafter a primary process has already configured the hugepage shared memory for them.\n\nTo support these two process types, and other multi-process setups described later,\ntwo additional command-line parameters are available to the EAL:\n\n* --proc-type: for specifying a given process instance as the primary or secondary DPDK instance\n\n* --file-prefix: to allow processes that do not want to co-operate to have different memory regions\n\nA number of example applications are provided that demonstrate how multiple DPDK processes can be used together.\nThese are more fully documented in the \"Multi- process Sample Application\" chapter\nin the *DPDK Sample Application's User Guide*.\n\nMemory Sharing\n--------------\n\nThe key element in getting a multi-process application working using the DPDK is to ensure that\nmemory resources are properly shared among the processes making up the multi-process application.\nOnce there are blocks of shared memory available that can be accessed by multiple processes,\nthen issues such as inter-process communication (IPC) becomes much simpler.\n\nOn application start-up in a primary or standalone process,\nthe DPDK records to memory-mapped files the details of the memory configuration it is using - hugepages in use,\nthe virtual addresses they are mapped at, the number of memory channels present, etc.\nWhen a secondary process is started, these files are read and the EAL recreates the same memory configuration\nin the secondary process so that all memory zones are shared between processes and all pointers to that memory are valid,\nand point to the same objects, in both processes.\n\n.. note::\n\n Refer to Section 23.3 \"Multi-process Limitations\" for details of\n how Linux kernel Address-Space Layout Randomization (ASLR) can affect memory sharing.\n\n.. _figure_multi_process_memory:\n\n.. figure:: img/multi_process_memory.*\n\n Memory Sharing in the DPDK Multi-process Sample Application\n\n\nThe EAL also supports an auto-detection mode (set by EAL --proc-type=auto flag ),\nwhereby an DPDK process is started as a secondary instance if a primary instance is already running.\n\nDeployment Models\n-----------------\n\nSymmetric/Peer Processes\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nDPDK multi-process support can be used to create a set of peer processes where each process performs the same workload.\nThis model is equivalent to having multiple threads each running the same main-loop function,\nas is done in most of the supplied DPDK sample applications.\nIn this model, the first of the processes spawned should be spawned using the --proc-type=primary EAL flag,\nwhile all subsequent instances should be spawned using the --proc-type=secondary flag.\n\nThe simple_mp and symmetric_mp sample applications demonstrate this usage model.\nThey are described in the \"Multi-process Sample Application\" chapter in the *DPDK Sample Application's User Guide*.\n\nAsymmetric/Non-Peer Processes\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nAn alternative deployment model that can be used for multi-process applications\nis to have a single primary process instance that acts as a load-balancer or\nserver distributing received packets among worker or client threads, which are run as secondary processes.\nIn this case, extensive use of rte_ring objects is made, which are located in shared hugepage memory.\n\nThe client_server_mp sample application shows this usage model.\nIt is described in the \"Multi-process Sample Application\" chapter in the *DPDK Sample Application's User Guide*.\n\nRunning Multiple Independent DPDK Applications\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nIn addition to the above scenarios involving multiple DPDK processes working together,\nit is possible to run multiple DPDK processes side-by-side,\nwhere those processes are all working independently.\nSupport for this usage scenario is provided using the --file-prefix parameter to the EAL.\n\nBy default, the EAL creates hugepage files on each hugetlbfs filesystem using the rtemap_X filename,\nwhere X is in the range 0 to the maximum number of hugepages -1.\nSimilarly, it creates shared configuration files, memory mapped in each process, using the /var/run/.rte_config filename,\nwhen run as root (or $HOME/.rte_config when run as a non-root user;\nif filesystem and device permissions are set up to allow this).\nThe rte part of the filenames of each of the above is configurable using the file-prefix parameter.\n\nIn addition to specifying the file-prefix parameter,\nany DPDK applications that are to be run side-by-side must explicitly limit their memory use.\nThis is done by passing the -m flag to each process to specify how much hugepage memory, in megabytes,\neach process can use (or passing --socket-mem to specify how much hugepage memory on each socket each process can use).\n\n.. note::\n\n Independent DPDK instances running side-by-side on a single machine cannot share any network ports.\n Any network ports being used by one process should be blacklisted in every other process.\n\nRunning Multiple Independent Groups of DPDK Applications\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nIn the same way that it is possible to run independent DPDK applications side- by-side on a single system,\nthis can be trivially extended to multi-process groups of DPDK applications running side-by-side.\nIn this case, the secondary processes must use the same --file-prefix parameter\nas the primary process whose shared memory they are connecting to.\n\n.. note::\n\n All restrictions and issues with multiple independent DPDK processes running side-by-side\n apply in this usage scenario also.\n\nMulti-process Limitations\n-------------------------\n\nThere are a number of limitations to what can be done when running DPDK multi-process applications.\nSome of these are documented below:\n\n* The multi-process feature requires that the exact same hugepage memory mappings be present in all applications.\n The Linux security feature - Address-Space Layout Randomization (ASLR) can interfere with this mapping,\n so it may be necessary to disable this feature in order to reliably run multi-process applications.\n\n.. warning::\n\n Disabling Address-Space Layout Randomization (ASLR) may have security implications,\n so it is recommended that it be disabled only when absolutely necessary,\n and only when the implications of this change have been understood.\n\n* All DPDK processes running as a single application and using shared memory must have distinct coremask arguments.\n It is not possible to have a primary and secondary instance, or two secondary instances,\n using any of the same logical cores.\n Attempting to do so can cause corruption of memory pool caches, among other issues.\n\n* The delivery of interrupts, such as Ethernet* device link status interrupts, do not work in secondary processes.\n All interrupts are triggered inside the primary process only.\n Any application needing interrupt notification in multiple processes should provide its own mechanism\n to transfer the interrupt information from the primary process to any secondary process that needs the information.\n\n* The use of function pointers between multiple processes running based of different compiled binaries is not supported,\n since the location of a given function in one process may be different to its location in a second.\n This prevents the librte_hash library from behaving properly as in a multi-threaded instance,\n since it uses a pointer to the hash function internally.\n\nTo work around this issue, it is recommended that multi-process applications perform the hash calculations by directly calling\nthe hashing function from the code and then using the rte_hash_add_with_hash()/rte_hash_lookup_with_hash() functions\ninstead of the functions which do the hashing internally, such as rte_hash_add()/rte_hash_lookup().\n\n* Depending upon the hardware in use, and the number of DPDK processes used,\n it may not be possible to have HPET timers available in each DPDK instance.\n The minimum number of HPET comparators available to Linux* userspace can be just a single comparator,\n which means that only the first, primary DPDK process instance can open and mmap /dev/hpet.\n If the number of required DPDK processes exceeds that of the number of available HPET comparators,\n the TSC (which is the default timer in this release) must be used as a time source across all processes instead of the HPET.\n" }, { "path": "doc/guides/prog_guide/overview.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n**Part 1: Architecture Overview**\n\nOverview\n========\n\nThis section gives a global overview of the architecture of Data Plane Development Kit (DPDK).\n\nThe main goal of the DPDK is to provide a simple,\ncomplete framework for fast packet processing in data plane applications.\nUsers may use the code to understand some of the techniques employed,\nto build upon for prototyping or to add their own protocol stacks.\nAlternative ecosystem options that use the DPDK are available.\n\nThe framework creates a set of libraries for specific environments\nthrough the creation of an Environment Abstraction Layer (EAL),\nwhich may be specific to a mode of the Intel® architecture (32-bit or 64-bit),\nLinux* user space compilers or a specific platform.\nThese environments are created through the use of make files and configuration files.\nOnce the EAL library is created, the user may link with the library to create their own applications.\nOther libraries, outside of EAL, including the Hash,\nLongest Prefix Match (LPM) and rings libraries are also provided.\nSample applications are provided to help show the user how to use various features of the DPDK.\n\nThe DPDK implements a run to completion model for packet processing,\nwhere all resources must be allocated prior to calling Data Plane applications,\nrunning as execution units on logical processing cores.\nThe model does not support a scheduler and all devices are accessed by polling.\nThe primary reason for not using interrupts is the performance overhead imposed by interrupt processing.\n\nIn addition to the run-to-completion model,\na pipeline model may also be used by passing packets or messages between cores via the rings.\nThis allows work to be performed in stages and may allow more efficient use of code on cores.\n\nDevelopment Environment\n-----------------------\n\nThe DPDK project installation requires Linux and the associated toolchain,\nsuch as one or more compilers, assembler, make utility,\neditor and various libraries to create the DPDK components and libraries.\n\nOnce these libraries are created for the specific environment and architecture,\nthey may then be used to create the user's data plane application.\n\nWhen creating applications for the Linux user space, the glibc library is used.\nFor DPDK applications, two environmental variables (RTE_SDK and RTE_TARGET)\nmust be configured before compiling the applications.\nThe following are examples of how the variables can be set:\n\n.. code-block:: console\n\n export RTE_SDK=/home/user/DPDK\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\nSee the *DPDK Getting Started Guide* for information on setting up the development environment.\n\nEnvironment Abstraction Layer\n-----------------------------\n\nThe Environment Abstraction Layer (EAL) provides a generic interface\nthat hides the environment specifics from the applications and libraries.\nThe services provided by the EAL are:\n\n* DPDK loading and launching\n\n* Support for multi-process and multi-thread execution types\n\n* Core affinity/assignment procedures\n\n* System memory allocation/de-allocation\n\n* Atomic/lock operations\n\n* Time reference\n\n* PCI bus access\n\n* Trace and debug functions\n\n* CPU feature identification\n\n* Interrupt handling\n\n* Alarm operations\n\n* Memory managenent (malloc)\n\nThe EAL is fully described in :ref:`Environment Abstraction Layer `.\n\nCore Components\n---------------\n\nThe *core components* are a set of libraries that provide all the elements needed\nfor high-performance packet processing applications.\n\n.. _figure_architecture-overview:\n\n.. figure:: img/architecture-overview.*\n\n Core Components Architecture\n\n\nRing Manager (librte_ring)\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe ring structure provides a lockless multi-producer, multi-consumer FIFO API in a finite size table.\nIt has some advantages over lockless queues; easier to implement, adapted to bulk operations and faster.\nA ring is used by the :ref:`Memory Pool Manager (librte_mempool) `\nand may be used as a general communication mechanism between cores\nand/or execution blocks connected together on a logical core.\n\nThis ring buffer and its usage are fully described in :ref:`Ring Library `.\n\nMemory Pool Manager (librte_mempool)\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe Memory Pool Manager is responsible for allocating pools of objects in memory.\nA pool is identified by name and uses a ring to store free objects.\nIt provides some other optional services,\nsuch as a per-core object cache and an alignment helper to ensure that objects are padded to spread them equally on all RAM channels.\n\nThis memory pool allocator is described in :ref:`Mempool Library `.\n\nNetwork Packet Buffer Management (librte_mbuf)\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe mbuf library provides the facility to create and destroy buffers\nthat may be used by the DPDK application to store message buffers.\nThe message buffers are created at startup time and stored in a mempool, using the DPDK mempool library.\n\nThis library provide an API to allocate/free mbufs, manipulate control message buffers (ctrlmbuf) which are generic message buffers,\nand packet buffers (pktmbuf) which are used to carry network packets.\n\nNetwork Packet Buffer Management is described in :ref:`Mbuf Library `.\n\nTimer Manager (librte_timer)\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThis library provides a timer service to DPDK execution units,\nproviding the ability to execute a function asynchronously.\nIt can be periodic function calls, or just a one-shot call.\nIt uses the timer interface provided by the Environment Abstraction Layer (EAL)\nto get a precise time reference and can be initiated on a per-core basis as required.\n\nThe library documentation is available in :ref:`Timer Library `.\n\nEthernet* Poll Mode Driver Architecture\n---------------------------------------\n\nThe DPDK includes Poll Mode Drivers (PMDs) for 1 GbE, 10 GbE and 40GbE, and para virtualized virtio\nEthernet controllers which are designed to work without asynchronous, interrupt-based signaling mechanisms.\n\nSee :ref:`Poll Mode Driver `.\n\nPacket Forwarding Algorithm Support\n-----------------------------------\n\nThe DPDK includes Hash (librte_hash) and Longest Prefix Match (LPM,librte_lpm)\nlibraries to support the corresponding packet forwarding algorithms.\n\nSee :ref:`Hash Library ` and :ref:`LPM Library ` for more information.\n\nlibrte_net\n----------\n\nThe librte_net library is a collection of IP protocol definitions and convenience macros.\nIt is based on code from the FreeBSD* IP stack and contains protocol numbers (for use in IP headers),\nIP-related macros, IPv4/IPv6 header structures and TCP, UDP and SCTP header structures.\n" }, { "path": "doc/guides/prog_guide/packet_classif_access_ctrl.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nPacket Classification and Access Control\n========================================\n\nThe DPDK provides an Access Control library that gives the ability\nto classify an input packet based on a set of classification rules.\n\nThe ACL library is used to perform an N-tuple search over a set of rules with multiple categories\nand find the best match (highest priority) for each category.\nThe library API provides the following basic operations:\n\n* Create a new Access Control (AC) context.\n\n* Add rules into the context.\n\n* For all rules in the context, build the runtime structures necessary to perform packet classification.\n\n* Perform input packet classifications.\n\n* Destroy an AC context and its runtime structures and free the associated memory.\n\nOverview\n--------\n\nRule definition\n~~~~~~~~~~~~~~~\n\nThe current implementation allows the user for each AC context to specify its own rule (set of fields)\nover which packet classification will be performed.\nThough there are few restrictions on the rule fields layout:\n\n* First field in the rule definition has to be one byte long.\n* All subsequent fields has to be grouped into sets of 4 consecutive bytes.\n\nThis is done mainly for performance reasons - search function processes the first input byte as part of the flow setup and then the inner loop of the search function is unrolled to process four input bytes at a time.\n\nTo define each field inside an AC rule, the following structure is used:\n\n.. code-block:: c\n\n struct rte_acl_field_def {\n uint8_t type; /*< type - ACL_FIELD_TYPE. */\n uint8_t size; /*< size of field 1,2,4, or 8. */\n uint8_t field_index; /*< index of field inside the rule. */\n uint8_t input_index; /*< 0-N input index. */\n uint32_t offset; /*< offset to start of field. */\n };\n\n* type\n The field type is one of three choices:\n\n * _MASK - for fields such as IP addresses that have a value and a mask defining the number of relevant bits.\n\n * _RANGE - for fields such as ports that have a lower and upper value for the field.\n\n * _BITMASK - for fields such as protocol identifiers that have a value and a bit mask.\n\n* size\n The size parameter defines the length of the field in bytes. Allowable values are 1, 2, 4, or 8 bytes.\n Note that due to the grouping of input bytes, 1 or 2 byte fields must be defined as consecutive fields\n that make up 4 consecutive input bytes.\n Also, it is best to define fields of 8 or more bytes as 4 byte fields so that\n the build processes can eliminate fields that are all wild.\n\n* field_index\n A zero-based value that represents the position of the field inside the rule; 0 to N-1 for N fields.\n\n* input_index\n As mentioned above, all input fields, except the very first one, must be in groups of 4 consecutive bytes.\n The input index specifies to which input group that field belongs to.\n\n* offset\n The offset field defines the offset for the field.\n This is the offset from the beginning of the buffer parameter for the search.\n\nFor example, to define classification for the following IPv4 5-tuple structure:\n\n.. code-block:: c\n\n struct ipv4_5tuple {\n uint8_t proto;\n uint32_t ip_src;\n uint32_t ip_dst;\n uint16_t port_src;\n uint16_t port_dst;\n };\n\nThe following array of field definitions can be used:\n\n.. code-block:: c\n\n struct rte_acl_field_def ipv4_defs[5] = {\n /* first input field - always one byte long. */\n {\n .type = RTE_ACL_FIELD_TYPE_BITMASK,\n .size = sizeof (uint8_t),\n .field_index = 0,\n .input_index = 0,\n .offset = offsetof (struct ipv4_5tuple, proto),\n },\n\n /* next input field (IPv4 source address) - 4 consecutive bytes. */\n {\n .type = RTE_ACL_FIELD_TYPE_MASK,\n .size = sizeof (uint32_t),\n .field_index = 1,\n .input_index = 1,\n .offset = offsetof (struct ipv4_5tuple, ip_src),\n },\n\n /* next input field (IPv4 destination address) - 4 consecutive bytes. */\n {\n .type = RTE_ACL_FIELD_TYPE_MASK,\n .size = sizeof (uint32_t),\n .field_index = 2,\n .input_index = 2,\n .offset = offsetof (struct ipv4_5tuple, ip_dst),\n },\n\n /*\n * Next 2 fields (src & dst ports) form 4 consecutive bytes.\n * They share the same input index.\n */\n {\n .type = RTE_ACL_FIELD_TYPE_RANGE,\n .size = sizeof (uint16_t),\n .field_index = 3,\n .input_index = 3,\n .offset = offsetof (struct ipv4_5tuple, port_src),\n },\n\n {\n .type = RTE_ACL_FIELD_TYPE_RANGE,\n .size = sizeof (uint16_t),\n .field_index = 4,\n .input_index = 3,\n .offset = offsetof (struct ipv4_5tuple, port_dst),\n },\n };\n\nA typical example of such an IPv4 5-tuple rule is a follows:\n\n::\n\n source addr/mask destination addr/mask source ports dest ports protocol/mask\n 192.168.1.0/24 192.168.2.31/32 0:65535 1234:1234 17/0xff\n\nAny IPv4 packets with protocol ID 17 (UDP), source address 192.168.1.[0-255], destination address 192.168.2.31,\nsource port [0-65535] and destination port 1234 matches the above rule.\n\nTo define classification for the IPv6 2-tuple: over the following IPv6 header structure:\n\n.. code-block:: c\n\n struct struct ipv6_hdr {\n uint32_t vtc_flow; /* IP version, traffic class & flow label. */\n uint16_t payload_len; /* IP packet length - includes sizeof(ip_header). */\n uint8_t proto; /* Protocol, next header. */\n uint8_t hop_limits; /* Hop limits. */\n uint8_t src_addr[16]; /* IP address of source host. */\n uint8_t dst_addr[16]; /* IP address of destination host(s). */\n } __attribute__((__packed__));\n\nThe following array of field definitions can be used:\n\n.. code-block:: c\n\n struct struct rte_acl_field_def ipv6_2tuple_defs[5] = {\n {\n .type = RTE_ACL_FIELD_TYPE_BITMASK,\n .size = sizeof (uint8_t),\n .field_index = 0,\n .input_index = 0,\n .offset = offsetof (struct ipv6_hdr, proto),\n },\n\n {\n .type = RTE_ACL_FIELD_TYPE_MASK,\n .size = sizeof (uint32_t),\n .field_index = 1,\n .input_index = 1,\n .offset = offsetof (struct ipv6_hdr, src_addr[0]),\n },\n\n {\n .type = RTE_ACL_FIELD_TYPE_MASK,\n .size = sizeof (uint32_t),\n .field_index = 2,\n .input_index = 2,\n .offset = offsetof (struct ipv6_hdr, src_addr[4]),\n },\n\n {\n .type = RTE_ACL_FIELD_TYPE_MASK,\n .size = sizeof (uint32_t),\n .field_index = 3,\n .input_index = 3,\n .offset = offsetof (struct ipv6_hdr, src_addr[8]),\n },\n\n {\n .type = RTE_ACL_FIELD_TYPE_MASK,\n .size = sizeof (uint32_t),\n .field_index = 4,\n .input_index = 4,\n .offset = offsetof (struct ipv6_hdr, src_addr[12]),\n },\n };\n\nA typical example of such an IPv6 2-tuple rule is a follows:\n\n::\n\n source addr/mask protocol/mask\n 2001:db8:1234:0000:0000:0000:0000:0000/48 6/0xff\n\nAny IPv6 packets with protocol ID 6 (TCP), and source address inside the range\n[2001:db8:1234:0000:0000:0000:0000:0000 - 2001:db8:1234:ffff:ffff:ffff:ffff:ffff] matches the above rule.\n\nWhen creating a set of rules, for each rule, additional information must be supplied also:\n\n* **priority**: A weight to measure the priority of the rules (higher is better).\n If the input tuple matches more than one rule, then the rule with the higher priority is returned.\n Note that if the input tuple matches more than one rule and these rules have equal priority,\n it is undefined which rule is returned as a match.\n It is recommended to assign a unique priority for each rule.\n\n* **category_mask**: Each rule uses a bit mask value to select the relevant category(s) for the rule.\n When a lookup is performed, the result for each category is returned.\n This effectively provides a \"parallel lookup\" by enabling a single search to return multiple results if,\n for example, there were four different sets of ACL rules, one for access control, one for routing, and so on.\n Each set could be assigned its own category and by combining them into a single database,\n one lookup returns a result for each of the four sets.\n\n* **userdata**: A user-defined field that could be any value except zero.\n For each category, a successful match returns the userdata field of the highest priority matched rule.\n\n.. note::\n\n When adding new rules into an ACL context, all fields must be in host byte order (LSB).\n When the search is performed for an input tuple, all fields in that tuple must be in network byte order (MSB).\n\nRT memory size limit\n~~~~~~~~~~~~~~~~~~~~\n\nBuild phase (rte_acl_build()) creates for a given set of rules internal structure for further run-time traversal.\nWith current implementation it is a set of multi-bit tries (with stride == 8).\nDepending on the rules set, that could consume significant amount of memory.\nIn attempt to conserve some space ACL build process tries to split the given\nrule-set into several non-intersecting subsets and construct a separate trie\nfor each of them.\nDepending on the rule-set, it might reduce RT memory requirements but might\nincrease classification time.\nThere is a possibility at build-time to specify maximum memory limit for internal RT structures for given AC context.\nIt could be done via **max_size** field of the **rte_acl_config** structure.\nSetting it to the value greater than zero, instructs rte_acl_build() to:\n\n* attempt to minimize number of tries in the RT table, but\n* make sure that size of RT table wouldn't exceed given value.\n\nSetting it to zero makes rte_acl_build() to use the default behavior:\ntry to minimize size of the RT structures, but doesn't expose any hard limit on it.\n\nThat gives the user the ability to decisions about performance/space trade-off.\nFor example:\n\n.. code-block:: c\n\n struct rte_acl_ctx * acx;\n struct rte_acl_config cfg;\n int ret;\n\n /*\n * assuming that acx points to already created and\n * populated with rules AC context and cfg filled properly.\n */\n\n /* try to build AC context, with RT structures less then 8MB. */\n cfg.max_size = 0x800000;\n ret = rte_acl_build(acx, &cfg);\n\n /*\n * RT structures can't fit into 8MB for given context.\n * Try to build without exposing any hard limit.\n */\n if (ret == -ERANGE) {\n cfg.max_size = 0;\n ret = rte_acl_build(acx, &cfg);\n }\n\n\n\nClassification methods\n~~~~~~~~~~~~~~~~~~~~~~\n\nAfter rte_acl_build() over given AC context has finished successfully, it can be used to perform classification - search for a rule with highest priority over the input data.\nThere are several implementations of classify algorithm:\n\n* **RTE_ACL_CLASSIFY_SCALAR**: generic implementation, doesn't require any specific HW support.\n\n* **RTE_ACL_CLASSIFY_SSE**: vector implementation, can process up to 8 flows in parallel. Requires SSE 4.1 support.\n\n* **RTE_ACL_CLASSIFY_AVX2**: vector implementation, can process up to 16 flows in parallel. Requires AVX2 support.\n\nIt is purely a runtime decision which method to choose, there is no build-time difference.\nAll implementations operates over the same internal RT structures and use similar principles. The main difference is that vector implementations can manually exploit IA SIMD instructions and process several input data flows in parallel.\nAt startup ACL library determines the highest available classify method for the given platform and sets it as default one. Though the user has an ability to override the default classifier function for a given ACL context or perform particular search using non-default classify method. In that case it is user responsibility to make sure that given platform supports selected classify implementation.\n\nApplication Programming Interface (API) Usage\n---------------------------------------------\n\n.. note::\n\n For more details about the Access Control API, please refer to the *DPDK API Reference*.\n\nThe following example demonstrates IPv4, 5-tuple classification for rules defined above\nwith multiple categories in more detail.\n\nClassify with Multiple Categories\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n.. code-block:: c\n\n struct rte_acl_ctx * acx;\n struct rte_acl_config cfg;\n int ret;\n\n /* define a structure for the rule with up to 5 fields. */\n\n RTE_ACL_RULE_DEF(acl_ipv4_rule, RTE_DIM(ipv4_defs));\n\n /* AC context creation parameters. */\n\n struct rte_acl_param prm = {\n .name = \"ACL_example\",\n .socket_id = SOCKET_ID_ANY,\n .rule_size = RTE_ACL_RULE_SZ(RTE_DIM(ipv4_defs)),\n\n /* number of fields per rule. */\n\n .max_rule_num = 8, /* maximum number of rules in the AC context. */\n };\n\n struct acl_ipv4_rule acl_rules[] = {\n\n /* matches all packets traveling to 192.168.0.0/16, applies for categories: 0,1 */\n {\n .data = {.userdata = 1, .category_mask = 3, .priority = 1},\n\n /* destination IPv4 */\n .field[2] = {.value.u32 = IPv4(192,168,0,0),. mask_range.u32 = 16,},\n\n /* source port */\n .field[3] = {.value.u16 = 0, .mask_range.u16 = 0xffff,},\n\n /* destination port */\n .field[4] = {.value.u16 = 0, .mask_range.u16 = 0xffff,},\n },\n\n /* matches all packets traveling to 192.168.1.0/24, applies for categories: 0 */\n {\n .data = {.userdata = 2, .category_mask = 1, .priority = 2},\n\n /* destination IPv4 */\n .field[2] = {.value.u32 = IPv4(192,168,1,0),. mask_range.u32 = 24,},\n\n /* source port */\n .field[3] = {.value.u16 = 0, .mask_range.u16 = 0xffff,},\n\n /* destination port */\n .field[4] = {.value.u16 = 0, .mask_range.u16 = 0xffff,},\n },\n\n /* matches all packets traveling from 10.1.1.1, applies for categories: 1 */\n {\n .data = {.userdata = 3, .category_mask = 2, .priority = 3},\n\n /* source IPv4 */\n .field[1] = {.value.u32 = IPv4(10,1,1,1),. mask_range.u32 = 32,},\n\n /* source port */\n .field[3] = {.value.u16 = 0, .mask_range.u16 = 0xffff,},\n\n /* destination port */\n .field[4] = {.value.u16 = 0, .mask_range.u16 = 0xffff,},\n },\n\n };\n\n\n /* create an empty AC context */\n\n if ((acx = rte_acl_create(&prm)) == NULL) {\n\n /* handle context create failure. */\n\n }\n\n /* add rules to the context */\n\n ret = rte_acl_add_rules(acx, acl_rules, RTE_DIM(acl_rules));\n if (ret != 0) {\n /* handle error at adding ACL rules. */\n }\n\n /* prepare AC build config. */\n\n cfg.num_categories = 2;\n cfg.num_fields = RTE_DIM(ipv4_defs);\n\n memcpy(cfg.defs, ipv4_defs, sizeof (ipv4_defs));\n\n /* build the runtime structures for added rules, with 2 categories. */\n\n ret = rte_acl_build(acx, &cfg);\n if (ret != 0) {\n /* handle error at build runtime structures for ACL context. */\n }\n\nFor a tuple with source IP address: 10.1.1.1 and destination IP address: 192.168.1.15,\nonce the following lines are executed:\n\n.. code-block:: c\n\n uint32_t results[4]; /* make classify for 4 categories. */\n\n rte_acl_classify(acx, data, results, 1, 4);\n\nthen the results[] array contains:\n\n.. code-block:: c\n\n results[4] = {2, 3, 0, 0};\n\n* For category 0, both rules 1 and 2 match, but rule 2 has higher priority,\n therefore results[0] contains the userdata for rule 2.\n\n* For category 1, both rules 1 and 3 match, but rule 3 has higher priority,\n therefore results[1] contains the userdata for rule 3.\n\n* For categories 2 and 3, there are no matches, so results[2] and results[3] contain zero,\n which indicates that no matches were found for those categories.\n\nFor a tuple with source IP address: 192.168.1.1 and destination IP address: 192.168.2.11,\nonce the following lines are executed:\n\n.. code-block:: c\n\n uint32_t results[4]; /* make classify by 4 categories. */\n\n rte_acl_classify(acx, data, results, 1, 4);\n\nthe results[] array contains:\n\n.. code-block:: c\n\n results[4] = {1, 1, 0, 0};\n\n* For categories 0 and 1, only rule 1 matches.\n\n* For categories 2 and 3, there are no matches.\n\nFor a tuple with source IP address: 10.1.1.1 and destination IP address: 201.212.111.12,\nonce the following lines are executed:\n\n.. code-block:: c\n\n uint32_t results[4]; /* make classify by 4 categories. */\n rte_acl_classify(acx, data, results, 1, 4);\n\nthe results[] array contains:\n\n.. code-block:: c\n\n results[4] = {0, 3, 0, 0};\n\n* For category 1, only rule 3 matches.\n\n* For categories 0, 2 and 3, there are no matches.\n" }, { "path": "doc/guides/prog_guide/packet_distrib_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nPacket Distributor Library\n==========================\n\nThe DPDK Packet Distributor library is a library designed to be used for dynamic load balancing of traffic\nwhile supporting single packet at a time operation.\nWhen using this library, the logical cores in use are to be considered in two roles: firstly a distributor lcore,\nwhich is responsible for load balancing or distributing packets,\nand a set of worker lcores which are responsible for receiving the packets from the distributor and operating on them.\nThe model of operation is shown in the diagram below.\n\n.. figure:: img/packet_distributor1.*\n\n Packet Distributor mode of operation\n\n\nDistributor Core Operation\n--------------------------\n\nThe distributor core does the majority of the processing for ensuring that packets are fairly shared among workers.\nThe operation of the distributor is as follows:\n\n#. Packets are passed to the distributor component by having the distributor lcore thread call the \"rte_distributor_process()\" API\n\n#. The worker lcores all share a single cache line with the distributor core in order to pass messages and packets to and from the worker.\n The process API call will poll all the worker cache lines to see what workers are requesting packets.\n\n#. As workers request packets, the distributor takes packets from the set of packets passed in and distributes them to the workers.\n As it does so, it examines the \"tag\" -- stored in the RSS hash field in the mbuf -- for each packet\n and records what tags are being processed by each worker.\n\n#. If the next packet in the input set has a tag which is already being processed by a worker,\n then that packet will be queued up for processing by that worker\n and given to it in preference to other packets when that work next makes a request for work.\n This ensures that no two packets with the same tag are processed in parallel,\n and that all packets with the same tag are processed in input order.\n\n#. Once all input packets passed to the process API have either been distributed to workers\n or been queued up for a worker which is processing a given tag,\n then the process API returns to the caller.\n\nOther functions which are available to the distributor lcore are:\n\n* rte_distributor_returned_pkts()\n\n* rte_distributor_flush()\n\n* rte_distributor_clear_returns()\n\nOf these the most important API call is \"rte_distributor_returned_pkts()\"\nwhich should only be called on the lcore which also calls the process API.\nIt returns to the caller all packets which have finished processing by all worker cores.\nWithin this set of returned packets, all packets sharing the same tag will be returned in their original order.\n\n**NOTE:**\nIf worker lcores buffer up packets internally for transmission in bulk afterwards,\nthe packets sharing a tag will likely get out of order.\nOnce a worker lcore requests a new packet, the distributor assumes that it has completely finished with the previous packet and\ntherefore that additional packets with the same tag can safely be distributed to other workers --\nwho may then flush their buffered packets sooner and cause packets to get out of order.\n\n**NOTE:**\nNo packet ordering guarantees are made about packets which do not share a common packet tag.\n\nUsing the process and returned_pkts API, the following application workflow can be used,\nwhile allowing packet order within a packet flow -- identified by a tag -- to be maintained.\n\n\n.. figure:: img/packet_distributor2.*\n\n Application workflow\n\n\nThe flush and clear_returns API calls, mentioned previously,\nare likely of less use that the process and returned_pkts APIS, and are principally provided to aid in unit testing of the library.\nDescriptions of these functions and their use can be found in the DPDK API Reference document.\n\nWorker Operation\n----------------\n\nWorker cores are the cores which do the actual manipulation of the packets distributed by the packet distributor.\nEach worker calls \"rte_distributor_get_pkt()\" API to request a new packet when it has finished processing the previous one.\n[The previous packet should be returned to the distributor component by passing it as the final parameter to this API call.]\n\nSince it may be desirable to vary the number of worker cores, depending on the traffic load\ni.e. to save power at times of lighter load,\nit is possible to have a worker stop processing packets by calling \"rte_distributor_return_pkt()\" to indicate that\nit has finished the current packet and does not want a new one.\n" }, { "path": "doc/guides/prog_guide/packet_framework.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nPacket Framework\n================\n\nDesign Objectives\n-----------------\n\nThe main design objectives for the DPDK Packet Framework are:\n\n* Provide standard methodology to build complex packet processing pipelines.\n Provide reusable and extensible templates for the commonly used pipeline functional blocks;\n\n* Provide capability to switch between pure software and hardware-accelerated implementations for the same pipeline functional block;\n\n* Provide the best trade-off between flexibility and performance.\n Hardcoded pipelines usually provide the best performance, but are not flexible,\n while developing flexible frameworks is never a problem, but performance is usually low;\n\n* Provide a framework that is logically similar to Open Flow.\n\nOverview\n--------\n\nPacket processing applications are frequently structured as pipelines of multiple stages,\nwith the logic of each stage glued around a lookup table.\nFor each incoming packet, the table defines the set of actions to be applied to the packet,\nas well as the next stage to send the packet to.\n\nThe DPDK Packet Framework minimizes the development effort required to build packet processing pipelines\nby defining a standard methodology for pipeline development,\nas well as providing libraries of reusable templates for the commonly used pipeline blocks.\n\nThe pipeline is constructed by connecting the set of input ports with the set of output ports\nthrough the set of tables in a tree-like topology.\nAs result of lookup operation for the current packet in the current table,\none of the table entries (on lookup hit) or the default table entry (on lookup miss)\nprovides the set of actions to be applied on the current packet,\nas well as the next hop for the packet, which can be either another table, an output port or packet drop.\n\nAn example of packet processing pipeline is presented in :numref:`figure_figure32`:\n\n.. _figure_figure32:\n\n.. figure:: img/figure32.*\n\n Example of Packet Processing Pipeline where Input Ports 0 and 1\n are Connected with Output Ports 0, 1 and 2 through Tables 0 and 1\n\n\nPort Library Design\n-------------------\n\nPort Types\n~~~~~~~~~~\n\n:numref:`table_qos_19` is a non-exhaustive list of ports that can be implemented with the Packet Framework.\n\n.. _table_qos_19:\n\n.. table:: Port Types\n\n +---+------------------+---------------------------------------------------------------------------------------+\n | # | Port type | Description |\n | | | |\n +===+==================+=======================================================================================+\n | 1 | SW ring | SW circular buffer used for message passing between the application threads. Uses |\n | | | the DPDK rte_ring primitive. Expected to be the most commonly used type of |\n | | | port. |\n | | | |\n +---+------------------+---------------------------------------------------------------------------------------+\n | 2 | HW ring | Queue of buffer descriptors used to interact with NIC, switch or accelerator ports. |\n | | | For NIC ports, it uses the DPDK rte_eth_rx_queue or rte_eth_tx_queue |\n | | | primitives. |\n | | | |\n +---+------------------+---------------------------------------------------------------------------------------+\n | 3 | IP reassembly | Input packets are either IP fragments or complete IP datagrams. Output packets are |\n | | | complete IP datagrams. |\n | | | |\n +---+------------------+---------------------------------------------------------------------------------------+\n | 4 | IP fragmentation | Input packets are jumbo (IP datagrams with length bigger than MTU) or non-jumbo |\n | | | packets. Output packets are non-jumbo packets. |\n | | | |\n +---+------------------+---------------------------------------------------------------------------------------+\n | 5 | Traffic manager | Traffic manager attached to a specific NIC output port, performing congestion |\n | | | management and hierarchical scheduling according to pre-defined SLAs. |\n | | | |\n +---+------------------+---------------------------------------------------------------------------------------+\n | 6 | KNI | Send/receive packets to/from Linux kernel space. |\n | | | |\n +---+------------------+---------------------------------------------------------------------------------------+\n | 7 | Source | Input port used as packet generator. Similar to Linux kernel /dev/zero character |\n | | | device. |\n | | | |\n +---+------------------+---------------------------------------------------------------------------------------+\n | 8 | Sink | Output port used to drop all input packets. Similar to Linux kernel /dev/null |\n | | | character device. |\n | | | |\n +---+------------------+---------------------------------------------------------------------------------------+\n\nPort Interface\n~~~~~~~~~~~~~~\n\nEach port is unidirectional, i.e. either input port or output port.\nEach input/output port is required to implement an abstract interface that\ndefines the initialization and run-time operation of the port.\nThe port abstract interface is described in.\n\n.. _table_qos_20:\n\n.. table:: 20 Port Abstract Interface\n\n +---+----------------+-----------------------------------------------------------------------------------------+\n | # | Port Operation | Description |\n | | | |\n +===+================+=========================================================================================+\n | 1 | Create | Create the low-level port object (e.g. queue). Can internally allocate memory. |\n | | | |\n +---+----------------+-----------------------------------------------------------------------------------------+\n | 2 | Free | Free the resources (e.g. memory) used by the low-level port object. |\n | | | |\n +---+----------------+-----------------------------------------------------------------------------------------+\n | 3 | RX | Read a burst of input packets. Non-blocking operation. Only defined for input ports. |\n | | | |\n +---+----------------+-----------------------------------------------------------------------------------------+\n | 4 | TX | Write a burst of input packets. Non-blocking operation. Only defined for output ports. |\n | | | |\n +---+----------------+-----------------------------------------------------------------------------------------+\n | 5 | Flush | Flush the output buffer. Only defined for output ports. |\n | | | |\n +---+----------------+-----------------------------------------------------------------------------------------+\n\nTable Library Design\n--------------------\n\nTable Types\n~~~~~~~~~~~\n\n:numref:`table_qos_21` is a non-exhaustive list of types of tables that can be implemented with the Packet Framework.\n\n.. _table_qos_21:\n\n.. table:: Table Types\n\n +---+----------------------------+-----------------------------------------------------------------------------+\n | # | Table Type | Description |\n | | | |\n +===+============================+=============================================================================+\n | 1 | Hash table | Lookup key is n-tuple based. |\n | | | |\n | | | Typically, the lookup key is hashed to produce a signature that is used to |\n | | | identify a bucket of entries where the lookup key is searched next. |\n | | | |\n | | | The signature associated with the lookup key of each input packet is either |\n | | | read from the packet descriptor (pre-computed signature) or computed at |\n | | | table lookup time. |\n | | | |\n | | | The table lookup, add entry and delete entry operations, as well as any |\n | | | other pipeline block that pre-computes the signature all have to use the |\n | | | same hashing algorithm to generate the signature. |\n | | | |\n | | | Typically used to implement flow classification tables, ARP caches, routing |\n | | | table for tunnelling protocols, etc. |\n | | | |\n +---+----------------------------+-----------------------------------------------------------------------------+\n | 2 | Longest Prefix Match (LPM) | Lookup key is the IP address. |\n | | | |\n | | | Each table entries has an associated IP prefix (IP and depth). |\n | | | |\n | | | The table lookup operation selects the IP prefix that is matched by the |\n | | | lookup key; in case of multiple matches, the entry with the longest prefix |\n | | | depth wins. |\n | | | |\n | | | Typically used to implement IP routing tables. |\n | | | |\n +---+----------------------------+-----------------------------------------------------------------------------+\n | 3 | Access Control List (ACLs) | Lookup key is 7-tuple of two VLAN/MPLS labels, IP destination address, |\n | | | IP source addresses, L4 protocol, L4 destination port, L4 source port. |\n | | | |\n | | | Each table entry has an associated ACL and priority. The ACL contains bit |\n | | | masks for the VLAN/MPLS labels, IP prefix for IP destination address, IP |\n | | | prefix for IP source addresses, L4 protocol and bitmask, L4 destination |\n | | | port and bit mask, L4 source port and bit mask. |\n | | | |\n | | | The table lookup operation selects the ACL that is matched by the lookup |\n | | | key; in case of multiple matches, the entry with the highest priority wins. |\n | | | |\n | | | Typically used to implement rule databases for firewalls, etc. |\n | | | |\n +---+----------------------------+-----------------------------------------------------------------------------+\n | 4 | Pattern matching search | Lookup key is the packet payload. |\n | | | |\n | | | Table is a database of patterns, with each pattern having a priority |\n | | | assigned. |\n | | | |\n | | | The table lookup operation selects the patterns that is matched by the |\n | | | input packet; in case of multiple matches, the matching pattern with the |\n | | | highest priority wins. |\n | | | |\n +---+----------------------------+-----------------------------------------------------------------------------+\n | 5 | Array | Lookup key is the table entry index itself. |\n | | | |\n +---+----------------------------+-----------------------------------------------------------------------------+\n\nTable Interface\n~~~~~~~~~~~~~~~\n\nEach table is required to implement an abstract interface that defines the initialization\nand run-time operation of the table.\nThe table abstract interface is described in :numref:`table_qos_29_1`.\n\n.. _table_qos_29_1:\n\n.. table:: Table Abstract Interface\n\n +---+-----------------+----------------------------------------------------------------------------------------+\n | # | Table operation | Description |\n | | | |\n +===+=================+========================================================================================+\n | 1 | Create | Create the low-level data structures of the lookup table. Can internally allocate |\n | | | memory. |\n | | | |\n +---+-----------------+----------------------------------------------------------------------------------------+\n | 2 | Free | Free up all the resources used by the lookup table. |\n | | | |\n +---+-----------------+----------------------------------------------------------------------------------------+\n | 3 | Add entry | Add new entry to the lookup table. |\n | | | |\n +---+-----------------+----------------------------------------------------------------------------------------+\n | 4 | Delete entry | Delete specific entry from the lookup table. |\n | | | |\n +---+-----------------+----------------------------------------------------------------------------------------+\n | 5 | Lookup | Look up a burst of input packets and return a bit mask specifying the result of the |\n | | | lookup operation for each packet: a set bit signifies lookup hit for the corresponding |\n | | | packet, while a cleared bit a lookup miss. |\n | | | |\n | | | For each lookup hit packet, the lookup operation also returns a pointer to the table |\n | | | entry that was hit, which contains the actions to be applied on the packet and any |\n | | | associated metadata. |\n | | | |\n | | | For each lookup miss packet, the actions to be applied on the packet and any |\n | | | associated metadata are specified by the default table entry preconfigured for lookup |\n | | | miss. |\n | | | |\n +---+-----------------+----------------------------------------------------------------------------------------+\n\n\nHash Table Design\n~~~~~~~~~~~~~~~~~\n\nHash Table Overview\n^^^^^^^^^^^^^^^^^^^\n\nHash tables are important because the key lookup operation is optimized for speed:\ninstead of having to linearly search the lookup key through all the keys in the table,\nthe search is limited to only the keys stored in a single table bucket.\n\n**Associative Arrays**\n\nAn associative array is a function that can be specified as a set of (key, value) pairs,\nwith each key from the possible set of input keys present at most once.\nFor a given associative array, the possible operations are:\n\n#. *add (key, value)*: When no value is currently associated with *key*, then the (key, *value* ) association is created.\n When *key* is already associated value *value0*, then the association (*key*, *value0*) is removed\n and association *(key, value)* is created;\n\n#. *delete key*: When no value is currently associated with *key*, this operation has no effect.\n When *key* is already associated *value*, then association *(key, value)* is removed;\n\n#. *lookup key*: When no value is currently associated with *key*, then this operation returns void value (lookup miss).\n When *key* is associated with *value*, then this operation returns *value*.\n The *(key, value)* association is not changed.\n\nThe matching criterion used to compare the input key against the keys in the associative array is *exact match*,\nas the key size (number of bytes) and the key value (array of bytes) have to match exactly for the two keys under comparison.\n\n**Hash Function**\n\nA hash function deterministically maps data of variable length (key) to data of fixed size (hash value or key signature).\nTypically, the size of the key is bigger than the size of the key signature.\nThe hash function basically compresses a long key into a short signature.\nSeveral keys can share the same signature (collisions).\n\nHigh quality hash functions have uniform distribution.\nFor large number of keys, when dividing the space of signature values into a fixed number of equal intervals (buckets),\nit is desirable to have the key signatures evenly distributed across these intervals (uniform distribution),\nas opposed to most of the signatures going into only a few of the intervals\nand the rest of the intervals being largely unused (non-uniform distribution).\n\n**Hash Table**\n\nA hash table is an associative array that uses a hash function for its operation.\nThe reason for using a hash function is to optimize the performance of the lookup operation\nby minimizing the number of table keys that have to be compared against the input key.\n\nInstead of storing the (key, value) pairs in a single list, the hash table maintains multiple lists (buckets).\nFor any given key, there is a single bucket where that key might exist, and this bucket is uniquely identified based on the key signature.\nOnce the key signature is computed and the hash table bucket identified,\nthe key is either located in this bucket or it is not present in the hash table at all,\nso the key search can be narrowed down from the full set of keys currently in the table\nto just the set of keys currently in the identified table bucket.\n\nThe performance of the hash table lookup operation is greatly improved,\nprovided that the table keys are evenly distributed among the hash table buckets,\nwhich can be achieved by using a hash function with uniform distribution.\nThe rule to map a key to its bucket can simply be to use the key signature (modulo the number of table buckets) as the table bucket ID:\n\n *bucket_id = f_hash(key) % n_buckets;*\n\nBy selecting the number of buckets to be a power of two, the modulo operator can be replaced by a bitwise AND logical operation:\n\n *bucket_id = f_hash(key) & (n_buckets - 1);*\n\nconsidering *n_bits* as the number of bits set in *bucket_mask = n_buckets - 1*,\nthis means that all the keys that end up in the same hash table bucket have the lower *n_bits* of their signature identical.\nIn order to reduce the number of keys in the same bucket (collisions), the number of hash table buckets needs to be increased.\n\nIn packet processing context, the sequence of operations involved in hash table operations is described in :numref:`figure_figure33`:\n\n.. _figure_figure33:\n\n.. figure:: img/figure33.*\n\n Sequence of Steps for Hash Table Operations in a Packet Processing Context\n\n\n\nHash Table Use Cases\n^^^^^^^^^^^^^^^^^^^^\n\n**Flow Classification**\n\n*Description:* The flow classification is executed at least once for each input packet.\nThis operation maps each incoming packet against one of the known traffic flows in the flow database that typically contains millions of flows.\n\n*Hash table name:* Flow classification table\n\n*Number of keys:* Millions\n\n*Key format:* n-tuple of packet fields that uniquely identify a traffic flow/connection.\nExample: DiffServ 5-tuple of (Source IP address, Destination IP address, L4 protocol, L4 protocol source port, L4 protocol destination port).\nFor IPv4 protocol and L4 protocols like TCP, UDP or SCTP, the size of the DiffServ 5-tuple is 13 bytes, while for IPv6 it is 37 bytes.\n\n*Key value (key data):* actions and action meta-data describing what processing to be applied for the packets of the current flow.\nThe size of the data associated with each traffic flow can vary from 8 bytes to kilobytes.\n\n**Address Resolution Protocol (ARP)**\n\n*Description:* Once a route has been identified for an IP packet (so the output interface and the IP address of the next hop station are known),\nthe MAC address of the next hop station is needed in order to send this packet onto the next leg of the journey\ntowards its destination (as identified by its destination IP address).\nThe MAC address of the next hop station becomes the destination MAC address of the outgoing Ethernet frame.\n\n*Hash table name:* ARP table\n\n*Number of keys:* Thousands\n\n*Key format:* The pair of (Output interface, Next Hop IP address), which is typically 5 bytes for IPv4 and 17 bytes for IPv6.\n\n*Key value (key data):* MAC address of the next hop station (6 bytes).\n\nHash Table Types\n^^^^^^^^^^^^^^^^\n\n:numref:`table_qos_22` lists the hash table configuration parameters shared by all different hash table types.\n\n.. _table_qos_22:\n\n.. table:: Configuration Parameters Common for All Hash Table Types\n\n +---+---------------------------+------------------------------------------------------------------------------+\n | # | Parameter | Details |\n | | | |\n +===+===========================+==============================================================================+\n | 1 | Key size | Measured as number of bytes. All keys have the same size. |\n | | | |\n +---+---------------------------+------------------------------------------------------------------------------+\n | 2 | Key value (key data) size | Measured as number of bytes. |\n | | | |\n +---+---------------------------+------------------------------------------------------------------------------+\n | 3 | Number of buckets | Needs to be a power of two. |\n | | | |\n +---+---------------------------+------------------------------------------------------------------------------+\n | 4 | Maximum number of keys | Needs to be a power of two. |\n | | | |\n +---+---------------------------+------------------------------------------------------------------------------+\n | 5 | Hash function | Examples: jhash, CRC hash, etc. |\n | | | |\n +---+---------------------------+------------------------------------------------------------------------------+\n | 6 | Hash function seed | Parameter to be passed to the hash function. |\n | | | |\n +---+---------------------------+------------------------------------------------------------------------------+\n | 7 | Key offset | Offset of the lookup key byte array within the packet meta-data stored in |\n | | | the packet buffer. |\n | | | |\n +---+---------------------------+------------------------------------------------------------------------------+\n\nBucket Full Problem\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nOn initialization, each hash table bucket is allocated space for exactly 4 keys.\nAs keys are added to the table, it can happen that a given bucket already has 4 keys when a new key has to be added to this bucket.\nThe possible options are:\n\n#. **Least Recently Used (LRU) Hash Table.**\n One of the existing keys in the bucket is deleted and the new key is added in its place.\n The number of keys in each bucket never grows bigger than 4. The logic to pick the key to be dropped from the bucket is LRU.\n The hash table lookup operation maintains the order in which the keys in the same bucket are hit, so every time a key is hit,\n it becomes the new Most Recently Used (MRU) key, i.e. the last candidate for drop.\n When a key is added to the bucket, it also becomes the new MRU key.\n When a key needs to be picked and dropped, the first candidate for drop, i.e. the current LRU key, is always picked.\n The LRU logic requires maintaining specific data structures per each bucket.\n\n#. **Extendable Bucket Hash Table.**\n The bucket is extended with space for 4 more keys.\n This is done by allocating additional memory at table initialization time,\n which is used to create a pool of free keys (the size of this pool is configurable and always a multiple of 4).\n On key add operation, the allocation of a group of 4 keys only happens successfully within the limit of free keys,\n otherwise the key add operation fails.\n On key delete operation, a group of 4 keys is freed back to the pool of free keys\n when the key to be deleted is the only key that was used within its group of 4 keys at that time.\n On key lookup operation, if the current bucket is in extended state and a match is not found in the first group of 4 keys,\n the search continues beyond the first group of 4 keys, potentially until all keys in this bucket are examined.\n The extendable bucket logic requires maintaining specific data structures per table and per each bucket.\n\n.. _table_qos_23:\n\n.. table:: Configuration Parameters Specific to Extendible Bucket Hash Table\n\n +---+---------------------------+--------------------------------------------------+\n | # | Parameter | Details |\n | | | |\n +===+===========================+==================================================+\n | 1 | Number of additional keys | Needs to be a power of two, at least equal to 4. |\n | | | |\n +---+---------------------------+--------------------------------------------------+\n\n\nSignature Computation\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThe possible options for key signature computation are:\n\n#. **Pre-computed key signature.**\n The key lookup operation is split between two CPU cores.\n The first CPU core (typically the CPU core that performs packet RX) extracts the key from the input packet,\n computes the key signature and saves both the key and the key signature in the packet buffer as packet meta-data.\n The second CPU core reads both the key and the key signature from the packet meta-data\n and performs the bucket search step of the key lookup operation.\n\n#. **Key signature computed on lookup (\"do-sig\" version).**\n The same CPU core reads the key from the packet meta-data, uses it to compute the key signature\n and also performs the bucket search step of the key lookup operation.\n\n.. _table_qos_24:\n\n.. table:: Configuration Parameters Specific to Pre-computed Key Signature Hash Table\n\n +---+------------------+-----------------------------------------------------------------------+\n | # | Parameter | Details |\n | | | |\n +===+==================+=======================================================================+\n | 1 | Signature offset | Offset of the pre-computed key signature within the packet meta-data. |\n | | | |\n +---+------------------+-----------------------------------------------------------------------+\n\nKey Size Optimized Hash Tables\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nFor specific key sizes, the data structures and algorithm of key lookup operation can be specially handcrafted for further performance improvements,\nso following options are possible:\n\n#. **Implementation supporting configurable key size.**\n\n#. **Implementation supporting a single key size.**\n Typical key sizes are 8 bytes and 16 bytes.\n\nBucket Search Logic for Configurable Key Size Hash Tables\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe performance of the bucket search logic is one of the main factors influencing the performance of the key lookup operation.\nThe data structures and algorithm are designed to make the best use of Intel CPU architecture resources like:\ncache memory space, cache memory bandwidth, external memory bandwidth, multiple execution units working in parallel,\nout of order instruction execution, special CPU instructions, etc.\n\nThe bucket search logic handles multiple input packets in parallel.\nIt is built as a pipeline of several stages (3 or 4), with each pipeline stage handling two different packets from the burst of input packets.\nOn each pipeline iteration, the packets are pushed to the next pipeline stage: for the 4-stage pipeline,\ntwo packets (that just completed stage 3) exit the pipeline,\ntwo packets (that just completed stage 2) are now executing stage 3, two packets (that just completed stage 1) are now executing stage 2,\ntwo packets (that just completed stage 0) are now executing stage 1 and two packets (next two packets to read from the burst of input packets)\nare entering the pipeline to execute stage 0.\nThe pipeline iterations continue until all packets from the burst of input packets execute the last stage of the pipeline.\n\nThe bucket search logic is broken into pipeline stages at the boundary of the next memory access.\nEach pipeline stage uses data structures that are stored (with high probability) into the L1 or L2 cache memory of the current CPU core and\nbreaks just before the next memory access required by the algorithm.\nThe current pipeline stage finalizes by prefetching the data structures required by the next pipeline stage,\nso given enough time for the prefetch to complete,\nwhen the next pipeline stage eventually gets executed for the same packets,\nit will read the data structures it needs from L1 or L2 cache memory and thus avoid the significant penalty incurred by L2 or L3 cache memory miss.\n\nBy prefetching the data structures required by the next pipeline stage in advance (before they are used)\nand switching to executing another pipeline stage for different packets,\nthe number of L2 or L3 cache memory misses is greatly reduced, hence one of the main reasons for improved performance.\nThis is because the cost of L2/L3 cache memory miss on memory read accesses is high, as usually due to data dependency between instructions,\nthe CPU execution units have to stall until the read operation is completed from L3 cache memory or external DRAM memory.\nBy using prefetch instructions, the latency of memory read accesses is hidden,\nprovided that it is preformed early enough before the respective data structure is actually used.\n\nBy splitting the processing into several stages that are executed on different packets (the packets from the input burst are interlaced),\nenough work is created to allow the prefetch instructions to complete successfully (before the prefetched data structures are actually accessed) and\nalso the data dependency between instructions is loosened.\nFor example, for the 4-stage pipeline, stage 0 is executed on packets 0 and 1 and then,\nbefore same packets 0 and 1 are used (i.e. before stage 1 is executed on packets 0 and 1),\ndifferent packets are used: packets 2 and 3 (executing stage 1), packets 4 and 5 (executing stage 2) and packets 6 and 7 (executing stage 3).\nBy executing useful work while the data structures are brought into the L1 or L2 cache memory, the latency of the read memory accesses is hidden.\nBy increasing the gap between two consecutive accesses to the same data structure, the data dependency between instructions is loosened;\nthis allows making the best use of the super-scalar and out-of-order execution CPU architecture,\nas the number of CPU core execution units that are active (rather than idle or stalled due to data dependency constraints between instructions) is maximized.\n\nThe bucket search logic is also implemented without using any branch instructions.\nThis avoids the important cost associated with flushing the CPU core execution pipeline on every instance of branch misprediction.\n\nConfigurable Key Size Hash Table\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\n:numref:`figure_figure34`, :numref:`table_qos_25` and :numref:`table_qos_26` detail the main data structures used to implement configurable key size hash tables (either LRU or extendable bucket,\neither with pre-computed signature or \"do-sig\").\n\n.. _figure_figure34:\n\n.. figure:: img/figure34.*\n\n Data Structures for Configurable Key Size Hash Tables\n\n\n.. _table_qos_25:\n\n.. table:: Main Large Data Structures (Arrays) used for Configurable Key Size Hash Tables\n\n +---+-------------------------+------------------------------+---------------------------+-------------------------------+\n | # | Array name | Number of entries | Entry size (bytes) | Description |\n | | | | | |\n +===+=========================+==============================+===========================+===============================+\n | 1 | Bucket array | n_buckets (configurable) | 32 | Buckets of the hash table. |\n | | | | | |\n +---+-------------------------+------------------------------+---------------------------+-------------------------------+\n | 2 | Bucket extensions array | n_buckets_ext (configurable) | 32 | This array is only created |\n | | | | | for extendible bucket tables. |\n | | | | | |\n +---+-------------------------+------------------------------+---------------------------+-------------------------------+\n | 3 | Key array | n_keys | key_size (configurable) | Keys added to the hash table. |\n | | | | | |\n +---+-------------------------+------------------------------+---------------------------+-------------------------------+\n | 4 | Data array | n_keys | entry_size (configurable) | Key values (key data) |\n | | | | | associated with the hash |\n | | | | | table keys. |\n | | | | | |\n +---+-------------------------+------------------------------+---------------------------+-------------------------------+\n\n.. _table_qos_26:\n\n.. table:: Field Description for Bucket Array Entry (Configurable Key Size Hash Tables)\n\n +---+------------------+--------------------+------------------------------------------------------------------+\n | # | Field name | Field size (bytes) | Description |\n | | | | |\n +===+==================+====================+==================================================================+\n | 1 | Next Ptr/LRU | 8 | For LRU tables, this fields represents the LRU list for the |\n | | | | current bucket stored as array of 4 entries of 2 bytes each. |\n | | | | Entry 0 stores the index (0 .. 3) of the MRU key, while entry 3 |\n | | | | stores the index of the LRU key. |\n | | | | |\n | | | | For extendible bucket tables, this field represents the next |\n | | | | pointer (i.e. the pointer to the next group of 4 keys linked to |\n | | | | the current bucket). The next pointer is not NULL if the bucket |\n | | | | is currently extended or NULL otherwise. |\n | | | | To help the branchless implementation, bit 0 (least significant |\n | | | | bit) of this field is set to 1 if the next pointer is not NULL |\n | | | | and to 0 otherwise. |\n | | | | |\n +---+------------------+--------------------+------------------------------------------------------------------+\n | 2 | Sig[0 .. 3] | 4 x 2 | If key X (X = 0 .. 3) is valid, then sig X bits 15 .. 1 store |\n | | | | the most significant 15 bits of key X signature and sig X bit 0 |\n | | | | is set to 1. |\n | | | | |\n | | | | If key X is not valid, then sig X is set to zero. |\n | | | | |\n +---+------------------+--------------------+------------------------------------------------------------------+\n | 3 | Key Pos [0 .. 3] | 4 x 4 | If key X is valid (X = 0 .. 3), then Key Pos X represents the |\n | | | | index into the key array where key X is stored, as well as the |\n | | | | index into the data array where the value associated with key X |\n | | | | is stored. |\n | | | | |\n | | | | If key X is not valid, then the value of Key Pos X is undefined. |\n | | | | |\n +---+------------------+--------------------+------------------------------------------------------------------+\n\n\n:numref:`figure_figure35` and :numref:`table_qos_27` detail the bucket search pipeline stages (either LRU or extendable bucket,\neither with pre-computed signature or \"do-sig\").\nFor each pipeline stage, the described operations are applied to each of the two packets handled by that stage.\n\n.. _figure_figure35:\n\n.. figure:: img/figure35.*\n\n Bucket Search Pipeline for Key Lookup Operation (Configurable Key Size Hash\n Tables)\n\n\n.. _table_qos_27:\n\n.. table:: Description of the Bucket Search Pipeline Stages (Configurable Key Size Hash Tables)\n\n +---+---------------------------+------------------------------------------------------------------------------+\n | # | Stage name | Description |\n | | | |\n +===+===========================+==============================================================================+\n | 0 | Prefetch packet meta-data | Select next two packets from the burst of input packets. |\n | | | |\n | | | Prefetch packet meta-data containing the key and key signature. |\n | | | |\n +---+---------------------------+------------------------------------------------------------------------------+\n | 1 | Prefetch table bucket | Read the key signature from the packet meta-data (for extendable bucket hash |\n | | | tables) or read the key from the packet meta-data and compute key signature |\n | | | (for LRU tables). |\n | | | |\n | | | Identify the bucket ID using the key signature. |\n | | | |\n | | | Set bit 0 of the signature to 1 (to match only signatures of valid keys from |\n | | | the table). |\n | | | |\n | | | Prefetch the bucket. |\n | | | |\n +---+---------------------------+------------------------------------------------------------------------------+\n | 2 | Prefetch table key | Read the key signatures from the bucket. |\n | | | |\n | | | Compare the signature of the input key against the 4 key signatures from the |\n | | | packet. As result, the following is obtained: |\n | | | |\n | | | *match* |\n | | | = equal to TRUE if there was at least one signature match and to FALSE in |\n | | | the case of no signature match; |\n | | | |\n | | | *match_many* |\n | | | = equal to TRUE is there were more than one signature matches (can be up to |\n | | | 4 signature matches in the worst case scenario) and to FALSE otherwise; |\n | | | |\n | | | *match_pos* |\n | | | = the index of the first key that produced signature match (only valid if |\n | | | match is true). |\n | | | |\n | | | For extendable bucket hash tables only, set |\n | | | *match_many* |\n | | | to TRUE if next pointer is valid. |\n | | | |\n | | | Prefetch the bucket key indicated by |\n | | | *match_pos* |\n | | | (even if |\n | | | *match_pos* |\n | | | does not point to valid key valid). |\n | | | |\n +---+---------------------------+------------------------------------------------------------------------------+\n | 3 | Prefetch table data | Read the bucket key indicated by |\n | | | *match_pos*. |\n | | | |\n | | | Compare the bucket key against the input key. As result, the following is |\n | | | obtained: |\n | | | *match_key* |\n | | | = equal to TRUE if the two keys match and to FALSE otherwise. |\n | | | |\n | | | Report input key as lookup hit only when both |\n | | | *match* |\n | | | and |\n | | | *match_key* |\n | | | are equal to TRUE and as lookup miss otherwise. |\n | | | |\n | | | For LRU tables only, use branchless logic to update the bucket LRU list |\n | | | (the current key becomes the new MRU) only on lookup hit. |\n | | | |\n | | | Prefetch the key value (key data) associated with the current key (to avoid |\n | | | branches, this is done on both lookup hit and miss). |\n | | | |\n +---+---------------------------+------------------------------------------------------------------------------+\n\n\nAdditional notes:\n\n#. The pipelined version of the bucket search algorithm is executed only if there are at least 7 packets in the burst of input packets.\n If there are less than 7 packets in the burst of input packets,\n a non-optimized implementation of the bucket search algorithm is executed.\n\n#. Once the pipelined version of the bucket search algorithm has been executed for all the packets in the burst of input packets,\n the non-optimized implementation of the bucket search algorithm is also executed for any packets that did not produce a lookup hit,\n but have the *match_many* flag set.\n As result of executing the non-optimized version, some of these packets may produce a lookup hit or lookup miss.\n This does not impact the performance of the key lookup operation,\n as the probability of matching more than one signature in the same group of 4 keys or of having the bucket in extended state\n (for extendable bucket hash tables only) is relatively small.\n\n**Key Signature Comparison Logic**\n\nThe key signature comparison logic is described in :numref:`table_qos_28`.\n\n.. _table_qos_28:\n\n.. table:: Lookup Tables for Match, Match_Many and Match_Pos\n\n +----+------+---------------+--------------------+--------------------+\n | # | mask | match (1 bit) | match_many (1 bit) | match_pos (2 bits) |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 0 | 0000 | 0 | 0 | 00 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 1 | 0001 | 1 | 0 | 00 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 2 | 0010 | 1 | 0 | 01 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 3 | 0011 | 1 | 1 | 00 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 4 | 0100 | 1 | 0 | 10 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 5 | 0101 | 1 | 1 | 00 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 6 | 0110 | 1 | 1 | 01 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 7 | 0111 | 1 | 1 | 00 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 8 | 1000 | 1 | 0 | 11 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 9 | 1001 | 1 | 1 | 00 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 10 | 1010 | 1 | 1 | 01 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 11 | 1011 | 1 | 1 | 00 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 12 | 1100 | 1 | 1 | 10 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 13 | 1101 | 1 | 1 | 00 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 14 | 1110 | 1 | 1 | 01 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n | 15 | 1111 | 1 | 1 | 00 |\n | | | | | |\n +----+------+---------------+--------------------+--------------------+\n\nThe input *mask* hash bit X (X = 0 .. 3) set to 1 if input signature is equal to bucket signature X and set to 0 otherwise.\nThe outputs *match*, *match_many* and *match_pos* are 1 bit, 1 bit and 2 bits in size respectively and their meaning has been explained above.\n\nAs displayed in :numref:`table_qos_29`, the lookup tables for *match* and *match_many* can be collapsed into a single 32-bit value and the lookup table for\n*match_pos* can be collapsed into a 64-bit value.\nGiven the input *mask*, the values for *match*, *match_many* and *match_pos* can be obtained by indexing their respective bit array to extract 1 bit,\n1 bit and 2 bits respectively with branchless logic.\n\n.. _table_qos_29:\n\n.. table:: Collapsed Lookup Tables for Match, Match_Many and Match_Pos\n\n +------------+------------------------------------------+-------------------+\n | | Bit array | Hexadecimal value |\n | | | |\n +------------+------------------------------------------+-------------------+\n | match | 1111_1111_1111_1110 | 0xFFFELLU |\n | | | |\n +------------+------------------------------------------+-------------------+\n | match_many | 1111_1110_1110_1000 | 0xFEE8LLU |\n | | | |\n +------------+------------------------------------------+-------------------+\n | match_pos | 0001_0010_0001_0011__0001_0010_0001_0000 | 0x12131210LLU |\n | | | |\n +------------+------------------------------------------+-------------------+\n\n\nThe pseudo-code for match, match_many and match_pos is::\n\n match = (0xFFFELLU >> mask) & 1;\n\n match_many = (0xFEE8LLU >> mask) & 1;\n\n match_pos = (0x12131210LLU >> (mask << 1)) & 3;\n\nSingle Key Size Hash Tables\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\n:numref:`figure_figure37`, :numref:`figure_figure38`, :numref:`table_qos_30` and :numref:`table_qos_31` detail the main data structures used to implement 8-byte and 16-byte key hash tables\n(either LRU or extendable bucket, either with pre-computed signature or \"do-sig\").\n\n.. _figure_figure37:\n\n.. figure:: img/figure37.*\n\n Data Structures for 8-byte Key Hash Tables\n\n\n.. _figure_figure38:\n\n.. figure:: img/figure38.*\n\n Data Structures for 16-byte Key Hash Tables\n\n\n.. _table_qos_30:\n\n.. table:: Main Large Data Structures (Arrays) used for 8-byte and 16-byte Key Size Hash Tables\n\n +---+-------------------------+------------------------------+----------------------+------------------------------------+\n | # | Array name | Number of entries | Entry size (bytes) | Description |\n | | | | | |\n +===+=========================+==============================+======================+====================================+\n | 1 | Bucket array | n_buckets (configurable) | *8-byte key size:* | Buckets of the hash table. |\n | | | | | |\n | | | | 64 + 4 x entry_size | |\n | | | | | |\n | | | | | |\n | | | | *16-byte key size:* | |\n | | | | | |\n | | | | 128 + 4 x entry_size | |\n | | | | | |\n +---+-------------------------+------------------------------+----------------------+------------------------------------+\n | 2 | Bucket extensions array | n_buckets_ext (configurable) | *8-byte key size:* | This array is only created for |\n | | | | | extendible bucket tables. |\n | | | | | |\n | | | | 64 + 4 x entry_size | |\n | | | | | |\n | | | | | |\n | | | | *16-byte key size:* | |\n | | | | | |\n | | | | 128 + 4 x entry_size | |\n | | | | | |\n +---+-------------------------+------------------------------+----------------------+------------------------------------+\n\n.. _table_qos_31:\n\n.. table:: Field Description for Bucket Array Entry (8-byte and 16-byte Key Hash Tables)\n\n +---+---------------+--------------------+-------------------------------------------------------------------------------+\n | # | Field name | Field size (bytes) | Description |\n | | | | |\n +===+===============+====================+===============================================================================+\n | 1 | Valid | 8 | Bit X (X = 0 .. 3) is set to 1 if key X is valid or to 0 otherwise. |\n | | | | |\n | | | | Bit 4 is only used for extendible bucket tables to help with the |\n | | | | implementation of the branchless logic. In this case, bit 4 is set to 1 if |\n | | | | next pointer is valid (not NULL) or to 0 otherwise. |\n | | | | |\n +---+---------------+--------------------+-------------------------------------------------------------------------------+\n | 2 | Next Ptr/LRU | 8 | For LRU tables, this fields represents the LRU list for the current bucket |\n | | | | stored as array of 4 entries of 2 bytes each. Entry 0 stores the index |\n | | | | (0 .. 3) of the MRU key, while entry 3 stores the index of the LRU key. |\n | | | | |\n | | | | For extendible bucket tables, this field represents the next pointer (i.e. |\n | | | | the pointer to the next group of 4 keys linked to the current bucket). The |\n | | | | next pointer is not NULL if the bucket is currently extended or NULL |\n | | | | otherwise. |\n | | | | |\n +---+---------------+--------------------+-------------------------------------------------------------------------------+\n | 3 | Key [0 .. 3] | 4 x key_size | Full keys. |\n | | | | |\n +---+---------------+--------------------+-------------------------------------------------------------------------------+\n | 4 | Data [0 .. 3] | 4 x entry_size | Full key values (key data) associated with keys 0 .. 3. |\n | | | | |\n +---+---------------+--------------------+-------------------------------------------------------------------------------+\n\nand detail the bucket search pipeline used to implement 8-byte and 16-byte key hash tables (either LRU or extendable bucket,\neither with pre-computed signature or \"do-sig\").\nFor each pipeline stage, the described operations are applied to each of the two packets handled by that stage.\n\n.. _figure_figure39:\n\n.. figure:: img/figure39.*\n\n Bucket Search Pipeline for Key Lookup Operation (Single Key Size Hash\n Tables)\n\n\n.. _table_qos_32:\n\n.. table:: Description of the Bucket Search Pipeline Stages (8-byte and 16-byte Key Hash Tables)\n\n +---+---------------------------+-----------------------------------------------------------------------------+\n | # | Stage name | Description |\n | | | |\n +===+===========================+=============================================================================+\n | 0 | Prefetch packet meta-data | #. Select next two packets from the burst of input packets. |\n | | | |\n | | | #. Prefetch packet meta-data containing the key and key signature. |\n | | | |\n +---+---------------------------+-----------------------------------------------------------------------------+\n | 1 | Prefetch table bucket | #. Read the key signature from the packet meta-data (for extendable bucket |\n | | | hash tables) or read the key from the packet meta-data and compute key |\n | | | signature (for LRU tables). |\n | | | |\n | | | #. Identify the bucket ID using the key signature. |\n | | | |\n | | | #. Prefetch the bucket. |\n | | | |\n +---+---------------------------+-----------------------------------------------------------------------------+\n | 2 | Prefetch table data | #. Read the bucket. |\n | | | |\n | | | #. Compare all 4 bucket keys against the input key. |\n | | | |\n | | | #. Report input key as lookup hit only when a match is identified (more |\n | | | than one key match is not possible) |\n | | | |\n | | | #. For LRU tables only, use branchless logic to update the bucket LRU list |\n | | | (the current key becomes the new MRU) only on lookup hit. |\n | | | |\n | | | #. Prefetch the key value (key data) associated with the matched key (to |\n | | | avoid branches, this is done on both lookup hit and miss). |\n | | | |\n +---+---------------------------+-----------------------------------------------------------------------------+\n\nAdditional notes:\n\n#. The pipelined version of the bucket search algorithm is executed only if there are at least 5 packets in the burst of input packets.\n If there are less than 5 packets in the burst of input packets, a non-optimized implementation of the bucket search algorithm is executed.\n\n#. For extendable bucket hash tables only,\n once the pipelined version of the bucket search algorithm has been executed for all the packets in the burst of input packets,\n the non-optimized implementation of the bucket search algorithm is also executed for any packets that did not produce a lookup hit,\n but have the bucket in extended state.\n As result of executing the non-optimized version, some of these packets may produce a lookup hit or lookup miss.\n This does not impact the performance of the key lookup operation,\n as the probability of having the bucket in extended state is relatively small.\n\nPipeline Library Design\n-----------------------\n\nA pipeline is defined by:\n\n#. The set of input ports;\n\n#. The set of output ports;\n\n#. The set of tables;\n\n#. The set of actions.\n\nThe input ports are connected with the output ports through tree-like topologies of interconnected tables.\nThe table entries contain the actions defining the operations to be executed on the input packets and the packet flow within the pipeline.\n\nConnectivity of Ports and Tables\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nTo avoid any dependencies on the order in which pipeline elements are created,\nthe connectivity of pipeline elements is defined after all the pipeline input ports,\noutput ports and tables have been created.\n\nGeneral connectivity rules:\n\n#. Each input port is connected to a single table. No input port should be left unconnected;\n\n#. The table connectivity to other tables or to output ports is regulated by the next hop actions of each table entry and the default table entry.\n The table connectivity is fluid, as the table entries and the default table entry can be updated during run-time.\n\n * A table can have multiple entries (including the default entry) connected to the same output port.\n A table can have different entries connected to different output ports.\n Different tables can have entries (including default table entry) connected to the same output port.\n\n * A table can have multiple entries (including the default entry) connected to another table,\n in which case all these entries have to point to the same table.\n This constraint is enforced by the API and prevents tree-like topologies from being created (allowing table chaining only),\n with the purpose of simplifying the implementation of the pipeline run-time execution engine.\n\nPort Actions\n~~~~~~~~~~~~\n\nPort Action Handler\n^^^^^^^^^^^^^^^^^^^\n\nAn action handler can be assigned to each input/output port to define actions to be executed on each input packet that is received by the port.\nDefining the action handler for a specific input/output port is optional (i.e. the action handler can be disabled).\n\nFor input ports, the action handler is executed after RX function. For output ports, the action handler is executed before the TX function.\n\nThe action handler can decide to drop packets.\n\nTable Actions\n~~~~~~~~~~~~~\n\nTable Action Handler\n^^^^^^^^^^^^^^^^^^^^\n\nAn action handler to be executed on each input packet can be assigned to each table.\nDefining the action handler for a specific table is optional (i.e. the action handler can be disabled).\n\nThe action handler is executed after the table lookup operation is performed and the table entry associated with each input packet is identified.\nThe action handler can only handle the user-defined actions, while the reserved actions (e.g. the next hop actions) are handled by the Packet Framework.\nThe action handler can decide to drop the input packet.\n\nReserved Actions\n^^^^^^^^^^^^^^^^\n\nThe reserved actions are handled directly by the Packet Framework without the user being able to change their meaning\nthrough the table action handler configuration.\nA special category of the reserved actions is represented by the next hop actions, which regulate the packet flow between input ports,\ntables and output ports through the pipeline.\n:numref:`table_qos_33` lists the next hop actions.\n\n.. _table_qos_33:\n\n.. table:: Next Hop Actions (Reserved)\n\n +---+---------------------+-----------------------------------------------------------------------------------+\n | # | Next hop action | Description |\n | | | |\n +===+=====================+===================================================================================+\n | 1 | Drop | Drop the current packet. |\n | | | |\n +---+---------------------+-----------------------------------------------------------------------------------+\n | 2 | Send to output port | Send the current packet to specified output port. The output port ID is metadata |\n | | | stored in the same table entry. |\n | | | |\n +---+---------------------+-----------------------------------------------------------------------------------+\n | 3 | Send to table | Send the current packet to specified table. The table ID is metadata stored in |\n | | | the same table entry. |\n | | | |\n +---+---------------------+-----------------------------------------------------------------------------------+\n\nUser Actions\n^^^^^^^^^^^^\n\nFor each table, the meaning of user actions is defined through the configuration of the table action handler.\nDifferent tables can be configured with different action handlers, therefore the meaning of the user actions\nand their associated meta-data is private to each table.\nWithin the same table, all the table entries (including the table default entry) share the same definition\nfor the user actions and their associated meta-data,\nwith each table entry having its own set of enabled user actions and its own copy of the action meta-data.\n:numref:`table_qos_34` contains a non-exhaustive list of user action examples.\n\n.. _table_qos_34:\n\n.. table:: User Action Examples\n\n +---+-----------------------------------+---------------------------------------------------------------------+\n | # | User action | Description |\n | | | |\n +===+===================================+=====================================================================+\n | 1 | Metering | Per flow traffic metering using the srTCM and trTCM algorithms. |\n | | | |\n +---+-----------------------------------+---------------------------------------------------------------------+\n | 2 | Statistics | Update the statistics counters maintained per flow. |\n | | | |\n +---+-----------------------------------+---------------------------------------------------------------------+\n | 3 | App ID | Per flow state machine fed by variable length sequence of packets |\n | | | at the flow initialization with the purpose of identifying the |\n | | | traffic type and application. |\n | | | |\n +---+-----------------------------------+---------------------------------------------------------------------+\n | 4 | Push/pop labels | Push/pop VLAN/MPLS labels to/from the current packet. |\n | | | |\n +---+-----------------------------------+---------------------------------------------------------------------+\n | 5 | Network Address Translation (NAT) | Translate between the internal (LAN) and external (WAN) IP |\n | | | destination/source address and/or L4 protocol destination/source |\n | | | port. |\n | | | |\n +---+-----------------------------------+---------------------------------------------------------------------+\n | 6 | TTL update | Decrement IP TTL and, in case of IPv4 packets, update the IP |\n | | | checksum. |\n | | | |\n +---+-----------------------------------+---------------------------------------------------------------------+\n\nMulticore Scaling\n-----------------\n\nA complex application is typically split across multiple cores, with cores communicating through SW queues.\nThere is usually a performance limit on the number of table lookups\nand actions that can be fitted on the same CPU core due to HW constraints like:\navailable CPU cycles, cache memory size, cache transfer BW, memory transfer BW, etc.\n\nAs the application is split across multiple CPU cores, the Packet Framework facilitates the creation of several pipelines,\nthe assignment of each such pipeline to a different CPU core\nand the interconnection of all CPU core-level pipelines into a single application-level complex pipeline.\nFor example, if CPU core A is assigned to run pipeline P1 and CPU core B pipeline P2,\nthen the interconnection of P1 with P2 could be achieved by having the same set of SW queues act like output ports\nfor P1 and input ports for P2.\n\nThis approach enables the application development using the pipeline, run-to-completion (clustered) or hybrid (mixed) models.\n\nIt is allowed for the same core to run several pipelines, but it is not allowed for several cores to run the same pipeline.\n\nShared Data Structures\n~~~~~~~~~~~~~~~~~~~~~~\n\nThe threads performing table lookup are actually table writers rather than just readers.\nEven if the specific table lookup algorithm is thread-safe for multiple readers\n(e. g. read-only access of the search algorithm data structures is enough to conduct the lookup operation),\nonce the table entry for the current packet is identified, the thread is typically expected to update the action meta-data stored in the table entry\n(e.g. increment the counter tracking the number of packets that hit this table entry), and thus modify the table entry.\nDuring the time this thread is accessing this table entry (either writing or reading; duration is application specific),\nfor data consistency reasons, no other threads (threads performing table lookup or entry add/delete operations) are allowed to modify this table entry.\n\nMechanisms to share the same table between multiple threads:\n\n#. **Multiple writer threads.**\n Threads need to use synchronization primitives like semaphores (distinct semaphore per table entry) or atomic instructions.\n The cost of semaphores is usually high, even when the semaphore is free.\n The cost of atomic instructions is normally higher than the cost of regular instructions.\n\n#. **Multiple writer threads, with single thread performing table lookup operations and multiple threads performing table entry add/delete operations.**\n The threads performing table entry add/delete operations send table update requests to the reader (typically through message passing queues),\n which does the actual table updates and then sends the response back to the request initiator.\n\n#. **Single writer thread performing table entry add/delete operations and multiple reader threads that perform table lookup operations with read-only access to the table entries.**\n The reader threads use the main table copy while the writer is updating the mirror copy.\n Once the writer update is done, the writer can signal to the readers and busy wait until all readers swaps between the mirror copy (which now becomes the main copy) and\n the mirror copy (which now becomes the main copy).\n\nInterfacing with Accelerators\n-----------------------------\n\nThe presence of accelerators is usually detected during the initialization phase by inspecting the HW devices that are part of the system (e.g. by PCI bus enumeration).\nTypical devices with acceleration capabilities are:\n\n* Inline accelerators: NICs, switches, FPGAs, etc;\n\n* Look-aside accelerators: chipsets, FPGAs, etc.\n\nUsually, to support a specific functional block, specific implementation of Packet Framework tables and/or ports and/or actions has to be provided for each accelerator,\nwith all the implementations sharing the same API: pure SW implementation (no acceleration), implementation using accelerator A, implementation using accelerator B, etc.\nThe selection between these implementations could be done at build time or at run-time (recommended), based on which accelerators are present in the system,\nwith no application changes required.\n" }, { "path": "doc/guides/prog_guide/perf_opt_guidelines.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Performance_Optimization:\n\n**Part 3: Performance Optimization**\n\nPerformance Optimization Guidelines\n===================================\n\nIntroduction\n------------\n\nThe following sections describe optimizations used in the DPDK and optimizations that should be considered for a new applications.\n\nThey also highlight the performance-impacting coding techniques that should,\nand should not be, used when developing an application using the DPDK.\n\nAnd finally, they give an introduction to application profiling using a Performance Analyzer from Intel to optimize the software.\n" }, { "path": "doc/guides/prog_guide/poll_mode_drv.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Poll_Mode_Driver:\n\nPoll Mode Driver\n================\n\nThe DPDK includes 1 Gigabit, 10 Gigabit and 40 Gigabit and para virtualized virtio Poll Mode Drivers.\n\nA Poll Mode Driver (PMD) consists of APIs, provided through the BSD driver running in user space,\nto configure the devices and their respective queues.\nIn addition, a PMD accesses the RX and TX descriptors directly without any interrupts\n(with the exception of Link Status Change interrupts) to quickly receive,\nprocess and deliver packets in the user's application.\nThis section describes the requirements of the PMDs,\ntheir global design principles and proposes a high-level architecture and a generic external API for the Ethernet PMDs.\n\nRequirements and Assumptions\n----------------------------\n\nThe DPDK environment for packet processing applications allows for two models, run-to-completion and pipe-line:\n\n* In the *run-to-completion* model, a specific port's RX descriptor ring is polled for packets through an API.\n Packets are then processed on the same core and placed on a port's TX descriptor ring through an API for transmission.\n\n* In the *pipe-line* model, one core polls one or more port's RX descriptor ring through an API.\n Packets are received and passed to another core via a ring.\n The other core continues to process the packet which then may be placed on a port's TX descriptor ring through an API for transmission.\n\nIn a synchronous run-to-completion model,\neach logical core assigned to the DPDK executes a packet processing loop that includes the following steps:\n\n* Retrieve input packets through the PMD receive API\n\n* Process each received packet one at a time, up to its forwarding\n\n* Send pending output packets through the PMD transmit API\n\nConversely, in an asynchronous pipe-line model, some logical cores may be dedicated to the retrieval of received packets and\nother logical cores to the processing of previously received packets.\nReceived packets are exchanged between logical cores through rings.\nThe loop for packet retrieval includes the following steps:\n\n* Retrieve input packets through the PMD receive API\n\n* Provide received packets to processing lcores through packet queues\n\nThe loop for packet processing includes the following steps:\n\n* Retrieve the received packet from the packet queue\n\n* Process the received packet, up to its retransmission if forwarded\n\nTo avoid any unnecessary interrupt processing overhead, the execution environment must not use any asynchronous notification mechanisms.\nWhenever needed and appropriate, asynchronous communication should be introduced as much as possible through the use of rings.\n\nAvoiding lock contention is a key issue in a multi-core environment.\nTo address this issue, PMDs are designed to work with per-core private resources as much as possible.\nFor example, a PMD maintains a separate transmit queue per-core, per-port.\nIn the same way, every receive queue of a port is assigned to and polled by a single logical core (lcore).\n\nTo comply with Non-Uniform Memory Access (NUMA), memory management is designed to assign to each logical core\na private buffer pool in local memory to minimize remote memory access.\nThe configuration of packet buffer pools should take into account the underlying physical memory architecture in terms of DIMMS,\nchannels and ranks.\nThe application must ensure that appropriate parameters are given at memory pool creation time.\nSee :ref:`Mempool Library `.\n\nDesign Principles\n-----------------\n\nThe API and architecture of the Ethernet* PMDs are designed with the following guidelines in mind.\n\nPMDs must help global policy-oriented decisions to be enforced at the upper application level.\nConversely, NIC PMD functions should not impede the benefits expected by upper-level global policies,\nor worse prevent such policies from being applied.\n\nFor instance, both the receive and transmit functions of a PMD have a maximum number of packets/descriptors to poll.\nThis allows a run-to-completion processing stack to statically fix or\nto dynamically adapt its overall behavior through different global loop policies, such as:\n\n* Receive, process immediately and transmit packets one at a time in a piecemeal fashion.\n\n* Receive as many packets as possible, then process all received packets, transmitting them immediately.\n\n* Receive a given maximum number of packets, process the received packets, accumulate them and finally send all accumulated packets to transmit.\n\nTo achieve optimal performance, overall software design choices and pure software optimization techniques must be considered and\nbalanced against available low-level hardware-based optimization features (CPU cache properties, bus speed, NIC PCI bandwidth, and so on).\nThe case of packet transmission is an example of this software/hardware tradeoff issue when optimizing burst-oriented network packet processing engines.\nIn the initial case, the PMD could export only an rte_eth_tx_one function to transmit one packet at a time on a given queue.\nOn top of that, one can easily build an rte_eth_tx_burst function that loops invoking the rte_eth_tx_one function to transmit several packets at a time.\nHowever, an rte_eth_tx_burst function is effectively implemented by the PMD to minimize the driver-level transmit cost per packet through the following optimizations:\n\n* Share among multiple packets the un-amortized cost of invoking the rte_eth_tx_one function.\n\n* Enable the rte_eth_tx_burst function to take advantage of burst-oriented hardware features (prefetch data in cache, use of NIC head/tail registers)\n to minimize the number of CPU cycles per packet, for example by avoiding unnecessary read memory accesses to ring transmit descriptors,\n or by systematically using arrays of pointers that exactly fit cache line boundaries and sizes.\n\n* Apply burst-oriented software optimization techniques to remove operations that would otherwise be unavoidable, such as ring index wrap back management.\n\nBurst-oriented functions are also introduced via the API for services that are intensively used by the PMD.\nThis applies in particular to buffer allocators used to populate NIC rings, which provide functions to allocate/free several buffers at a time.\nFor example, an mbuf_multiple_alloc function returning an array of pointers to rte_mbuf buffers which speeds up the receive poll function of the PMD when\nreplenishing multiple descriptors of the receive ring.\n\nLogical Cores, Memory and NIC Queues Relationships\n--------------------------------------------------\n\nThe DPDK supports NUMA allowing for better performance when a processor's logical cores and interfaces utilize its local memory.\nTherefore, mbuf allocation associated with local PCIe* interfaces should be allocated from memory pools created in the local memory.\nThe buffers should, if possible, remain on the local processor to obtain the best performance results and RX and TX buffer descriptors\nshould be populated with mbufs allocated from a mempool allocated from local memory.\n\nThe run-to-completion model also performs better if packet or data manipulation is in local memory instead of a remote processors memory.\nThis is also true for the pipe-line model provided all logical cores used are located on the same processor.\n\nMultiple logical cores should never share receive or transmit queues for interfaces since this would require global locks and hinder performance.\n\nDevice Identification and Configuration\n---------------------------------------\n\nDevice Identification\n~~~~~~~~~~~~~~~~~~~~~\n\nEach NIC port is uniquely designated by its (bus/bridge, device, function) PCI\nidentifiers assigned by the PCI probing/enumeration function executed at DPDK initialization.\nBased on their PCI identifier, NIC ports are assigned two other identifiers:\n\n* A port index used to designate the NIC port in all functions exported by the PMD API.\n\n* A port name used to designate the port in console messages, for administration or debugging purposes.\n For ease of use, the port name includes the port index.\n\nDevice Configuration\n~~~~~~~~~~~~~~~~~~~~\n\nThe configuration of each NIC port includes the following operations:\n\n* Allocate PCI resources\n\n* Reset the hardware (issue a Global Reset) to a well-known default state\n\n* Set up the PHY and the link\n\n* Initialize statistics counters\n\nThe PMD API must also export functions to start/stop the all-multicast feature of a port and functions to set/unset the port in promiscuous mode.\n\nSome hardware offload features must be individually configured at port initialization through specific configuration parameters.\nThis is the case for the Receive Side Scaling (RSS) and Data Center Bridging (DCB) features for example.\n\nOn-the-Fly Configuration\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nAll device features that can be started or stopped \"on the fly\" (that is, without stopping the device) do not require the PMD API to export dedicated functions for this purpose.\n\nAll that is required is the mapping address of the device PCI registers to implement the configuration of these features in specific functions outside of the drivers.\n\nFor this purpose,\nthe PMD API exports a function that provides all the information associated with a device that can be used to set up a given device feature outside of the driver.\nThis includes the PCI vendor identifier, the PCI device identifier, the mapping address of the PCI device registers, and the name of the driver.\n\nThe main advantage of this approach is that it gives complete freedom on the choice of the API used to configure, to start, and to stop such features.\n\nAs an example, refer to the configuration of the IEEE1588 feature for the Intel® 82576 Gigabit Ethernet Controller and\nthe Intel® 82599 10 Gigabit Ethernet Controller controllers in the testpmd application.\n\nOther features such as the L3/L4 5-Tuple packet filtering feature of a port can be configured in the same way.\nEthernet* flow control (pause frame) can be configured on the individual port.\nRefer to the testpmd source code for details.\nAlso, L4 (UDP/TCP/ SCTP) checksum offload by the NIC can be enabled for an individual packet as long as the packet mbuf is set up correctly. See `Hardware Offload`_ for details.\n\nConfiguration of Transmit and Receive Queues\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nEach transmit queue is independently configured with the following information:\n\n* The number of descriptors of the transmit ring\n\n* The socket identifier used to identify the appropriate DMA memory zone from which to allocate the transmit ring in NUMA architectures\n\n* The values of the Prefetch, Host and Write-Back threshold registers of the transmit queue\n\n* The *minimum* transmit packets to free threshold (tx_free_thresh).\n When the number of descriptors used to transmit packets exceeds this threshold, the network adaptor should be checked to see if it has written back descriptors.\n A value of 0 can be passed during the TX queue configuration to indicate the default value should be used.\n The default value for tx_free_thresh is 32.\n This ensures that the PMD does not search for completed descriptors until at least 32 have been processed by the NIC for this queue.\n\n* The *minimum* RS bit threshold. The minimum number of transmit descriptors to use before setting the Report Status (RS) bit in the transmit descriptor.\n Note that this parameter may only be valid for Intel 10 GbE network adapters.\n The RS bit is set on the last descriptor used to transmit a packet if the number of descriptors used since the last RS bit setting,\n up to the first descriptor used to transmit the packet, exceeds the transmit RS bit threshold (tx_rs_thresh).\n In short, this parameter controls which transmit descriptors are written back to host memory by the network adapter.\n A value of 0 can be passed during the TX queue configuration to indicate that the default value should be used.\n The default value for tx_rs_thresh is 32.\n This ensures that at least 32 descriptors are used before the network adapter writes back the most recently used descriptor.\n This saves upstream PCIe* bandwidth resulting from TX descriptor write-backs.\n It is important to note that the TX Write-back threshold (TX wthresh) should be set to 0 when tx_rs_thresh is greater than 1.\n Refer to the Intel® 82599 10 Gigabit Ethernet Controller Datasheet for more details.\n\nThe following constraints must be satisfied for tx_free_thresh and tx_rs_thresh:\n\n* tx_rs_thresh must be greater than 0.\n\n* tx_rs_thresh must be less than the size of the ring minus 2.\n\n* tx_rs_thresh must be less than or equal to tx_free_thresh.\n\n* tx_free_thresh must be greater than 0.\n\n* tx_free_thresh must be less than the size of the ring minus 3.\n\n* For optimal performance, TX wthresh should be set to 0 when tx_rs_thresh is greater than 1.\n\nOne descriptor in the TX ring is used as a sentinel to avoid a hardware race condition, hence the maximum threshold constraints.\n\n.. note::\n\n When configuring for DCB operation, at port initialization, both the number of transmit queues and the number of receive queues must be set to 128.\n\nHardware Offload\n~~~~~~~~~~~~~~~~\n\nDepending on driver capabilities advertised by\n``rte_eth_dev_info_get()``, the PMD may support hardware offloading\nfeature like checksumming, TCP segmentation or VLAN insertion.\n\nThe support of these offload features implies the addition of dedicated\nstatus bit(s) and value field(s) into the rte_mbuf data structure, along\nwith their appropriate handling by the receive/transmit functions\nexported by each PMD. The list of flags and their precise meaning is\ndescribed in the mbuf API documentation and in the in :ref:`Mbuf Library\n`, section \"Meta Information\".\n\nPoll Mode Driver API\n--------------------\n\nGeneralities\n~~~~~~~~~~~~\n\nBy default, all functions exported by a PMD are lock-free functions that are assumed\nnot to be invoked in parallel on different logical cores to work on the same target object.\nFor instance, a PMD receive function cannot be invoked in parallel on two logical cores to poll the same RX queue of the same port.\nOf course, this function can be invoked in parallel by different logical cores on different RX queues.\nIt is the responsibility of the upper-level application to enforce this rule.\n\nIf needed, parallel accesses by multiple logical cores to shared queues can be explicitly protected by dedicated inline lock-aware functions\nbuilt on top of their corresponding lock-free functions of the PMD API.\n\nGeneric Packet Representation\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nA packet is represented by an rte_mbuf structure, which is a generic metadata structure containing all necessary housekeeping information.\nThis includes fields and status bits corresponding to offload hardware features, such as checksum computation of IP headers or VLAN tags.\n\nThe rte_mbuf data structure includes specific fields to represent, in a generic way, the offload features provided by network controllers.\nFor an input packet, most fields of the rte_mbuf structure are filled in by the PMD receive function with the information contained in the receive descriptor.\nConversely, for output packets, most fields of rte_mbuf structures are used by the PMD transmit function to initialize transmit descriptors.\n\nThe mbuf structure is fully described in the :ref:`Mbuf Library ` chapter.\n\nEthernet Device API\n~~~~~~~~~~~~~~~~~~~\n\nThe Ethernet device API exported by the Ethernet PMDs is described in the *DPDK API Reference*.\n" }, { "path": "doc/guides/prog_guide/port_hotplug_framework.rst", "content": ".. BSD LICENSE\n Copyright(c) 2015 IGEL Co.,Ltd. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of IGEL Co.,Ltd. nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nPort Hotplug Framework\n======================\n\nThe Port Hotplug Framework provides DPDK applications with the ability to\nattach and detach ports at runtime. Because the framework depends on PMD\nimplementation, the ports that PMDs cannot handle are out of scope of this\nframework. Furthermore, after detaching a port from a DPDK application, the\nframework doesn't provide a way for removing the devices from the system.\nFor the ports backed by a physical NIC, the kernel will need to support PCI\nHotplug feature.\n\nOverview\n--------\n\nThe basic requirements of the Port Hotplug Framework are:\n\n* DPDK applications that use the Port Hotplug Framework must manage their\n own ports.\n\n The Port Hotplug Framework is implemented to allow DPDK applications to\n manage ports. For example, when DPDK applications call the port attach\n function, the attached port number is returned. DPDK applications can\n also detach the port by port number.\n\n* Kernel support is needed for attaching or detaching physical device\n ports.\n\n To attach new physical device ports, the device will be recognized by\n userspace driver I/O framework in kernel at first. Then DPDK\n applications can call the Port Hotplug functions to attach the ports.\n For detaching, steps are vice versa.\n\n* Before detaching, they must be stopped and closed.\n\n DPDK applications must call \"rte_eth_dev_stop()\" and\n \"rte_eth_dev_close()\" APIs before detaching ports. These functions will\n start finalization sequence of the PMDs.\n\n* The framework doesn't affect legacy DPDK applications behavior.\n\n If the Port Hotplug functions aren't called, all legacy DPDK apps can\n still work without modifications.\n\nPort Hotplug API overview\n-------------------------\n\n* Attaching a port\n\n \"rte_eth_dev_attach()\" API attaches a port to DPDK application, and\n returns the attached port number. Before calling the API, the device\n should be recognized by an userspace driver I/O framework. The API\n receives a pci address like \"0000:01:00.0\" or a virtual device name\n like \"eth_pcap0,iface=eth0\". In the case of virtual device name, the\n format is the same as the general \"--vdev\" option of DPDK.\n\n* Detaching a port\n\n \"rte_eth_dev_detach()\" API detaches a port from DPDK application, and\n returns a pci address of the detached device or a virtual device name\n of the device.\n\nReference\n---------\n\n \"testpmd\" supports the Port Hotplug Framework.\n\nLimitations\n-----------\n\n* The Port Hotplug APIs are not thread safe.\n\n* The framework can only be enabled with Linux. BSD is not supported.\n\n* To detach a port, the port should be backed by a device that igb_uio\n manages. VFIO is not supported.\n\n* Not all PMDs support detaching feature.\n To know whether a PMD can support detaching, search for the\n \"RTE_PCI_DRV_DETACHABLE\" flag in PMD implementation. If the flag is\n defined in the PMD, detaching is supported.\n" }, { "path": "doc/guides/prog_guide/power_man.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nPower Management\n================\n\nThe DPDK Power Management feature allows users space applications to save power\nby dynamically adjusting CPU frequency or entering into different C-States.\n\n* Adjusting the CPU frequency dynamically according to the utilization of RX queue.\n\n* Entering into different deeper C-States according to the adaptive algorithms to speculate\n brief periods of time suspending the application if no packets are received.\n\nThe interfaces for adjusting the operating CPU frequency are in the power management library.\nC-State control is implemented in applications according to the different use cases.\n\nCPU Frequency Scaling\n---------------------\n\nThe Linux kernel provides a cpufreq module for CPU frequency scaling for each lcore.\nFor example, for cpuX, /sys/devices/system/cpu/cpuX/cpufreq/ has the following sys files for frequency scaling:\n\n* affected_cpus\n\n* bios_limit\n\n* cpuinfo_cur_freq\n\n* cpuinfo_max_freq\n\n* cpuinfo_min_freq\n\n* cpuinfo_transition_latency\n\n* related_cpus\n\n* scaling_available_frequencies\n\n* scaling_available_governors\n\n* scaling_cur_freq\n\n* scaling_driver\n\n* scaling_governor\n\n* scaling_max_freq\n\n* scaling_min_freq\n\n* scaling_setspeed\n\nIn the DPDK, scaling_governor is configured in user space.\nThen, a user space application can prompt the kernel by writing scaling_setspeed to adjust the CPU frequency\naccording to the strategies defined by the user space application.\n\nCore-load Throttling through C-States\n-------------------------------------\n\nCore state can be altered by speculative sleeps whenever the specified lcore has nothing to do.\nIn the DPDK, if no packet is received after polling,\nspeculative sleeps can be triggered according the strategies defined by the user space application.\n\nAPI Overview of the Power Library\n---------------------------------\n\nThe main methods exported by power library are for CPU frequency scaling and include the following:\n\n* **Freq up**: Prompt the kernel to scale up the frequency of the specific lcore.\n\n* **Freq down**: Prompt the kernel to scale down the frequency of the specific lcore.\n\n* **Freq max**: Prompt the kernel to scale up the frequency of the specific lcore to the maximum.\n\n* **Freq min**: Prompt the kernel to scale down the frequency of the specific lcore to the minimum.\n\n* **Get available freqs**: Read the available frequencies of the specific lcore from the sys file.\n\n* **Freq get**: Get the current frequency of the specific lcore.\n\n* **Freq set**: Prompt the kernel to set the frequency for the specific lcore.\n\nUser Cases\n----------\n\nThe power management mechanism is used to save power when performing L3 forwarding.\n\nReferences\n----------\n\n* l3fwd-power: The sample application in DPDK that performs L3 forwarding with power management.\n\n* The \"L3 Forwarding with Power Management Sample Application\" chapter in the *DPDK Sample Application's User Guide*.\n" }, { "path": "doc/guides/prog_guide/profile_app.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nProfile Your Application\n========================\n\nIntel processors provide performance counters to monitor events.\nSome tools provided by Intel can be used to profile and benchmark an application.\nSee the *VTune Performance Analyzer Essentials* publication from Intel Press for more information.\n\nFor a DPDK application, this can be done in a Linux* application environment only.\n\nThe main situations that should be monitored through event counters are:\n\n* Cache misses\n\n* Branch mis-predicts\n\n* DTLB misses\n\n* Long latency instructions and exceptions\n\nRefer to the\n`Intel Performance Analysis Guide `_\nfor details about application profiling.\n" }, { "path": "doc/guides/prog_guide/qos_framework.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nQuality of Service (QoS) Framework\n==================================\n\nThis chapter describes the DPDK Quality of Service (QoS) framework.\n\nPacket Pipeline with QoS Support\n--------------------------------\n\nAn example of a complex packet processing pipeline with QoS support is shown in the following figure.\n\n.. _figure_pkt_proc_pipeline_qos:\n\n.. figure:: img/pkt_proc_pipeline_qos.*\n\n Complex Packet Processing Pipeline with QoS Support\n\n\nThis pipeline can be built using reusable DPDK software libraries.\nThe main blocks implementing QoS in this pipeline are: the policer, the dropper and the scheduler.\nA functional description of each block is provided in the following table.\n\n.. _table_qos_1:\n\n.. table:: Packet Processing Pipeline Implementing QoS\n\n +---+------------------------+--------------------------------------------------------------------------------+\n | # | Block | Functional Description |\n | | | |\n +===+========================+================================================================================+\n | 1 | Packet I/O RX & TX | Packet reception/ transmission from/to multiple NIC ports. Poll mode drivers |\n | | | (PMDs) for Intel 1 GbE/10 GbE NICs. |\n | | | |\n +---+------------------------+--------------------------------------------------------------------------------+\n | 2 | Packet parser | Identify the protocol stack of the input packet. Check the integrity of the |\n | | | packet headers. |\n | | | |\n +---+------------------------+--------------------------------------------------------------------------------+\n | 3 | Flow classification | Map the input packet to one of the known traffic flows. Exact match table |\n | | | lookup using configurable hash function (jhash, CRC and so on) and bucket |\n | | | logic to handle collisions. |\n | | | |\n +---+------------------------+--------------------------------------------------------------------------------+\n | 4 | Policer | Packet metering using srTCM (RFC 2697) or trTCM (RFC2698) algorithms. |\n | | | |\n +---+------------------------+--------------------------------------------------------------------------------+\n | 5 | Load Balancer | Distribute the input packets to the application workers. Provide uniform load |\n | | | to each worker. Preserve the affinity of traffic flows to workers and the |\n | | | packet order within each flow. |\n | | | |\n +---+------------------------+--------------------------------------------------------------------------------+\n | 6 | Worker threads | Placeholders for the customer specific application workload (for example, IP |\n | | | stack and so on). |\n | | | |\n +---+------------------------+--------------------------------------------------------------------------------+\n | 7 | Dropper | Congestion management using the Random Early Detection (RED) algorithm |\n | | | (specified by the Sally Floyd - Van Jacobson paper) or Weighted RED (WRED). |\n | | | Drop packets based on the current scheduler queue load level and packet |\n | | | priority. When congestion is experienced, lower priority packets are dropped |\n | | | first. |\n | | | |\n +---+------------------------+--------------------------------------------------------------------------------+\n | 8 | Hierarchical Scheduler | 5-level hierarchical scheduler (levels are: output port, subport, pipe, |\n | | | traffic class and queue) with thousands (typically 64K) leaf nodes (queues). |\n | | | Implements traffic shaping (for subport and pipe levels), strict priority |\n | | | (for traffic class level) and Weighted Round Robin (WRR) (for queues within |\n | | | each pipe traffic class). |\n | | | |\n +---+------------------------+--------------------------------------------------------------------------------+\n\nThe infrastructure blocks used throughout the packet processing pipeline are listed in the following table.\n\n.. _table_qos_2:\n\n.. table:: Infrastructure Blocks Used by the Packet Processing Pipeline\n\n +---+-----------------------+-----------------------------------------------------------------------+\n | # | Block | Functional Description |\n | | | |\n +===+=======================+=======================================================================+\n | 1 | Buffer manager | Support for global buffer pools and private per-thread buffer caches. |\n | | | |\n +---+-----------------------+-----------------------------------------------------------------------+\n | 2 | Queue manager | Support for message passing between pipeline blocks. |\n | | | |\n +---+-----------------------+-----------------------------------------------------------------------+\n | 3 | Power saving | Support for power saving during low activity periods. |\n | | | |\n +---+-----------------------+-----------------------------------------------------------------------+\n\nThe mapping of pipeline blocks to CPU cores is configurable based on the performance level required by each specific application\nand the set of features enabled for each block.\nSome blocks might consume more than one CPU core (with each CPU core running a different instance of the same block on different input packets),\nwhile several other blocks could be mapped to the same CPU core.\n\nHierarchical Scheduler\n----------------------\n\nThe hierarchical scheduler block, when present, usually sits on the TX side just before the transmission stage.\nIts purpose is to prioritize the transmission of packets from different users and different traffic classes\naccording to the policy specified by the Service Level Agreements (SLAs) of each network node.\n\nOverview\n~~~~~~~~\n\nThe hierarchical scheduler block is similar to the traffic manager block used by network processors\nthat typically implement per flow (or per group of flows) packet queuing and scheduling.\nIt typically acts like a buffer that is able to temporarily store a large number of packets just before their transmission (enqueue operation);\nas the NIC TX is requesting more packets for transmission,\nthese packets are later on removed and handed over to the NIC TX with the packet selection logic observing the predefined SLAs (dequeue operation).\n\n.. _figure_hier_sched_blk:\n\n.. figure:: img/hier_sched_blk.*\n\n Hierarchical Scheduler Block Internal Diagram\n\n\nThe hierarchical scheduler is optimized for a large number of packet queues.\nWhen only a small number of queues are needed, message passing queues should be used instead of this block.\nSee Section 26.2.5 \"Worst Case Scenarios for Performance\" for a more detailed discussion.\n\nScheduling Hierarchy\n~~~~~~~~~~~~~~~~~~~~\n\nThe scheduling hierarchy is shown in :numref:`figure_sched_hier_per_port`.\nThe first level of the hierarchy is the Ethernet TX port 1/10/40 GbE,\nwith subsequent hierarchy levels defined as subport, pipe, traffic class and queue.\n\nTypically, each subport represents a predefined group of users, while each pipe represents an individual user/subscriber.\nEach traffic class is the representation of a different traffic type with specific loss rate,\ndelay and jitter requirements, such as voice, video or data transfers.\nEach queue hosts packets from one or multiple connections of the same type belonging to the same user.\n\n.. _figure_sched_hier_per_port:\n\n.. figure:: img/sched_hier_per_port.*\n\n Scheduling Hierarchy per Port\n\n\nThe functionality of each hierarchical level is detailed in the following table.\n\n.. _table_qos_3:\n\n.. table:: Port Scheduling Hierarchy\n\n +---+--------------------+----------------------------+---------------------------------------------------------------+\n | # | Level | Siblings per Parent | Functional Description |\n | | | | |\n +===+====================+============================+===============================================================+\n | 1 | Port | - | #. Output Ethernet port 1/10/40 GbE. |\n | | | | |\n | | | | #. Multiple ports are scheduled in round robin order with |\n | | | | all ports having equal priority. |\n | | | | |\n +---+--------------------+----------------------------+---------------------------------------------------------------+\n | 2 | Subport | Configurable (default: 8) | #. Traffic shaping using token bucket algorithm (one token |\n | | | | bucket per subport). |\n | | | | |\n | | | | #. Upper limit enforced per Traffic Class (TC) at the |\n | | | | subport level. |\n | | | | |\n | | | | #. Lower priority TCs able to reuse subport bandwidth |\n | | | | currently unused by higher priority TCs. |\n | | | | |\n +---+--------------------+----------------------------+---------------------------------------------------------------+\n | 3 | Pipe | Configurable (default: 4K) | #. Traffic shaping using the token bucket algorithm (one |\n | | | | token bucket per pipe. |\n | | | | |\n +---+--------------------+----------------------------+---------------------------------------------------------------+\n | 4 | Traffic Class (TC) | 4 | #. TCs of the same pipe handled in strict priority order. |\n | | | | |\n | | | | #. Upper limit enforced per TC at the pipe level. |\n | | | | |\n | | | | #. Lower priority TCs able to reuse pipe bandwidth currently |\n | | | | unused by higher priority TCs. |\n | | | | |\n | | | | #. When subport TC is oversubscribed (configuration time |\n | | | | event), pipe TC upper limit is capped to a dynamically |\n | | | | adjusted value that is shared by all the subport pipes. |\n | | | | |\n +---+--------------------+----------------------------+---------------------------------------------------------------+\n | 5 | Queue | 4 | #. Queues of the same TC are serviced using Weighted Round |\n | | | | Robin (WRR) according to predefined weights. |\n | | | | |\n +---+--------------------+----------------------------+---------------------------------------------------------------+\n\nApplication Programming Interface (API)\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nPort Scheduler Configuration API\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe rte_sched.h file contains configuration functions for port, subport and pipe.\n\nPort Scheduler Enqueue API\n^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe port scheduler enqueue API is very similar to the API of the DPDK PMD TX function.\n\n.. code-block:: c\n\n int rte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts);\n\nPort Scheduler Dequeue API\n^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe port scheduler dequeue API is very similar to the API of the DPDK PMD RX function.\n\n.. code-block:: c\n\n int rte_sched_port_dequeue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts);\n\nUsage Example\n^^^^^^^^^^^^^\n\n.. code-block:: c\n\n /* File \"application.c\" */\n\n #define N_PKTS_RX 64\n #define N_PKTS_TX 48\n #define NIC_RX_PORT 0\n #define NIC_RX_QUEUE 0\n #define NIC_TX_PORT 1\n #define NIC_TX_QUEUE 0\n\n struct rte_sched_port *port = NULL;\n struct rte_mbuf *pkts_rx[N_PKTS_RX], *pkts_tx[N_PKTS_TX];\n uint32_t n_pkts_rx, n_pkts_tx;\n\n /* Initialization */\n\n \n\n /* Runtime */\n while (1) {\n /* Read packets from NIC RX queue */\n\n n_pkts_rx = rte_eth_rx_burst(NIC_RX_PORT, NIC_RX_QUEUE, pkts_rx, N_PKTS_RX);\n\n /* Hierarchical scheduler enqueue */\n\n rte_sched_port_enqueue(port, pkts_rx, n_pkts_rx);\n\n /* Hierarchical scheduler dequeue */\n\n n_pkts_tx = rte_sched_port_dequeue(port, pkts_tx, N_PKTS_TX);\n\n /* Write packets to NIC TX queue */\n\n rte_eth_tx_burst(NIC_TX_PORT, NIC_TX_QUEUE, pkts_tx, n_pkts_tx);\n }\n\nImplementation\n~~~~~~~~~~~~~~\n\nInternal Data Structures per Port\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nA schematic of the internal data structures in shown in with details in.\n\n.. _figure_data_struct_per_port:\n\n.. figure:: img/data_struct_per_port.*\n\n Internal Data Structures per Port\n\n\n.. _table_qos_4:\n\n.. table:: Scheduler Internal Data Structures per Port\n\n +---+----------------------+-------------------------+---------------------+------------------------------+---------------------------------------------------+\n | # | Data structure | Size (bytes) | # per port | Access type | Description |\n | | | | | | |\n | | | | +-------------+----------------+---------------------------------------------------+\n | | | | | Enq | Deq | |\n | | | | | | | |\n +===+======================+=========================+=====================+=============+================+===================================================+\n | 1 | Subport table entry | 64 | # subports per port | - | Rd, Wr | Persistent subport data (credits, etc). |\n | | | | | | | |\n +---+----------------------+-------------------------+---------------------+-------------+----------------+---------------------------------------------------+\n | 2 | Pipe table entry | 64 | # pipes per port | - | Rd, Wr | Persistent data for pipe, its TCs and its queues |\n | | | | | | | (credits, etc) that is updated during run-time. |\n | | | | | | | |\n | | | | | | | The pipe configuration parameters do not change |\n | | | | | | | during run-time. The same pipe configuration |\n | | | | | | | parameters are shared by multiple pipes, |\n | | | | | | | therefore they are not part of pipe table entry. |\n | | | | | | | |\n +---+----------------------+-------------------------+---------------------+-------------+----------------+---------------------------------------------------+\n | 3 | Queue table entry | 4 | #queues per port | Rd, Wr | Rd, Wr | Persistent queue data (read and write pointers). |\n | | | | | | | The queue size is the same per TC for all queues, |\n | | | | | | | allowing the queue base address to be computed |\n | | | | | | | using a fast formula, so these two parameters are |\n | | | | | | | not part of queue table entry. |\n | | | | | | | |\n | | | | | | | The queue table entries for any given pipe are |\n | | | | | | | stored in the same cache line. |\n | | | | | | | |\n +---+----------------------+-------------------------+---------------------+-------------+----------------+---------------------------------------------------+\n | 4 | Queue storage area | Config (default: 64 x8) | # queues per port | Wr | Rd | Array of elements per queue; each element is 8 |\n | | | | | | | byte in size (mbuf pointer). |\n | | | | | | | |\n +---+----------------------+-------------------------+---------------------+-------------+----------------+---------------------------------------------------+\n | 5 | Active queues bitmap | 1 bit per queue | 1 | Wr (Set) | Rd, Wr (Clear) | The bitmap maintains one status bit per queue: |\n | | | | | | | queue not active (queue is empty) or queue active |\n | | | | | | | (queue is not empty). |\n | | | | | | | |\n | | | | | | | Queue bit is set by the scheduler enqueue and |\n | | | | | | | cleared by the scheduler dequeue when queue |\n | | | | | | | becomes empty. |\n | | | | | | | |\n | | | | | | | Bitmap scan operation returns the next non-empty |\n | | | | | | | pipe and its status (16-bit mask of active queue |\n | | | | | | | in the pipe). |\n | | | | | | | |\n +---+----------------------+-------------------------+---------------------+-------------+----------------+---------------------------------------------------+\n | 6 | Grinder | ~128 | Config (default: 8) | - | Rd, Wr | Short list of active pipes currently under |\n | | | | | | | processing. The grinder contains temporary data |\n | | | | | | | during pipe processing. |\n | | | | | | | |\n | | | | | | | Once the current pipe exhausts packets or |\n | | | | | | | credits, it is replaced with another active pipe |\n | | | | | | | from the bitmap. |\n | | | | | | | |\n +---+----------------------+-------------------------+---------------------+-------------+----------------+---------------------------------------------------+\n\nMulticore Scaling Strategy\n^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe multicore scaling strategy is:\n\n#. Running different physical ports on different threads. The enqueue and dequeue of the same port are run by the same thread.\n\n#. Splitting the same physical port to different threads by running different sets of subports of the same physical port (virtual ports) on different threads.\n Similarly, a subport can be split into multiple subports that are each run by a different thread.\n The enqueue and dequeue of the same port are run by the same thread.\n This is only required if, for performance reasons, it is not possible to handle a full port with a single core.\n\nEnqueue and Dequeue for the Same Output Port\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nRunning enqueue and dequeue operations for the same output port from different cores is likely to cause significant impact on scheduler's performance\nand it is therefore not recommended.\n\nThe port enqueue and dequeue operations share access to the following data structures:\n\n#. Packet descriptors\n\n#. Queue table\n\n#. Queue storage area\n\n#. Bitmap of active queues\n\nThe expected drop in performance is due to:\n\n#. Need to make the queue and bitmap operations thread safe,\n which requires either using locking primitives for access serialization (for example, spinlocks/ semaphores) or\n using atomic primitives for lockless access (for example, Test and Set, Compare And Swap, an so on).\n The impact is much higher in the former case.\n\n#. Ping-pong of cache lines storing the shared data structures between the cache hierarchies of the two cores\n (done transparently by the MESI protocol cache coherency CPU hardware).\n\nTherefore, the scheduler enqueue and dequeue operations have to be run from the same thread,\nwhich allows the queues and the bitmap operations to be non-thread safe and\nkeeps the scheduler data structures internal to the same core.\n\nPerformance Scaling\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nScaling up the number of NIC ports simply requires a proportional increase in the number of CPU cores to be used for traffic scheduling.\n\nEnqueue Pipeline\n^^^^^^^^^^^^^^^^\n\nThe sequence of steps per packet:\n\n#. *Access* the mbuf to read the data fields required to identify the destination queue for the packet.\n These fields are: port, subport, traffic class and queue within traffic class, and are typically set by the classification stage.\n\n#. *Access* the queue structure to identify the write location in the queue array.\n If the queue is full, then the packet is discarded.\n\n#. *Access* the queue array location to store the packet (i.e. write the mbuf pointer).\n\nIt should be noted the strong data dependency between these steps, as steps 2 and 3 cannot start before the result from steps 1 and 2 becomes available,\nwhich prevents the processor out of order execution engine to provide any significant performance optimizations.\n\nGiven the high rate of input packets and the large amount of queues,\nit is expected that the data structures accessed to enqueue the current packet are not present\nin the L1 or L2 data cache of the current core, thus the above 3 memory accesses would result (on average) in L1 and L2 data cache misses.\nA number of 3 L1/L2 cache misses per packet is not acceptable for performance reasons.\n\nThe workaround is to prefetch the required data structures in advance. The prefetch operation has an execution latency during which\nthe processor should not attempt to access the data structure currently under prefetch, so the processor should execute other work.\nThe only other work available is to execute different stages of the enqueue sequence of operations on other input packets,\nthus resulting in a pipelined implementation for the enqueue operation.\n\n:numref:`figure_prefetch_pipeline` illustrates a pipelined implementation for the enqueue operation with 4 pipeline stages and each stage executing 2 different input packets.\nNo input packet can be part of more than one pipeline stage at a given time.\n\n.. _figure_prefetch_pipeline:\n\n.. figure:: img/prefetch_pipeline.*\n\n Prefetch Pipeline for the Hierarchical Scheduler Enqueue Operation\n\n\nThe congestion management scheme implemented by the enqueue pipeline described above is very basic:\npackets are enqueued until a specific queue becomes full,\nthen all the packets destined to the same queue are dropped until packets are consumed (by the dequeue operation).\nThis can be improved by enabling RED/WRED as part of the enqueue pipeline which looks at the queue occupancy and\npacket priority in order to yield the enqueue/drop decision for a specific packet\n(as opposed to enqueuing all packets / dropping all packets indiscriminately).\n\nDequeue State Machine\n^^^^^^^^^^^^^^^^^^^^^\n\nThe sequence of steps to schedule the next packet from the current pipe is:\n\n#. Identify the next active pipe using the bitmap scan operation, *prefetch* pipe.\n\n#. *Read* pipe data structure. Update the credits for the current pipe and its subport.\n Identify the first active traffic class within the current pipe, select the next queue using WRR,\n *prefetch* queue pointers for all the 16 queues of the current pipe.\n\n#. *Read* next element from the current WRR queue and *prefetch* its packet descriptor.\n\n#. *Read* the packet length from the packet descriptor (mbuf structure).\n Based on the packet length and the available credits (of current pipe, pipe traffic class, subport and subport traffic class),\n take the go/no go scheduling decision for the current packet.\n\nTo avoid the cache misses, the above data structures (pipe, queue, queue array, mbufs) are prefetched in advance of being accessed.\nThe strategy of hiding the latency of the prefetch operations is to switch from the current pipe (in grinder A) to another pipe\n(in grinder B) immediately after a prefetch is issued for the current pipe.\nThis gives enough time to the prefetch operation to complete before the execution switches back to this pipe (in grinder A).\n\nThe dequeue pipe state machine exploits the data presence into the processor cache,\ntherefore it tries to send as many packets from the same pipe TC and pipe as possible (up to the available packets and credits) before\nmoving to the next active TC from the same pipe (if any) or to another active pipe.\n\n.. _figure_pipe_prefetch_sm:\n\n.. figure:: img/pipe_prefetch_sm.*\n\n Pipe Prefetch State Machine for the Hierarchical Scheduler Dequeue\n Operation\n\n\nTiming and Synchronization\n^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe output port is modeled as a conveyor belt of byte slots that need to be filled by the scheduler with data for transmission.\nFor 10 GbE, there are 1.25 billion byte slots that need to be filled by the port scheduler every second.\nIf the scheduler is not fast enough to fill the slots, provided that enough packets and credits exist,\nthen some slots will be left unused and bandwidth will be wasted.\n\nIn principle, the hierarchical scheduler dequeue operation should be triggered by NIC TX.\nUsually, once the occupancy of the NIC TX input queue drops below a predefined threshold,\nthe port scheduler is woken up (interrupt based or polling based,\nby continuously monitoring the queue occupancy) to push more packets into the queue.\n\nInternal Time Reference\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThe scheduler needs to keep track of time advancement for the credit logic,\nwhich requires credit updates based on time (for example, subport and pipe traffic shaping, traffic class upper limit enforcement, and so on).\n\nEvery time the scheduler decides to send a packet out to the NIC TX for transmission, the scheduler will increment its internal time reference accordingly.\nTherefore, it is convenient to keep the internal time reference in units of bytes,\nwhere a byte signifies the time duration required by the physical interface to send out a byte on the transmission medium.\nThis way, as a packet is scheduled for transmission, the time is incremented with (n + h),\nwhere n is the packet length in bytes and h is the number of framing overhead bytes per packet.\n\nInternal Time Reference Re-synchronization\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThe scheduler needs to align its internal time reference to the pace of the port conveyor belt.\nThe reason is to make sure that the scheduler does not feed the NIC TX with more bytes than the line rate of the physical medium in order to prevent packet drop\n(by the scheduler, due to the NIC TX input queue being full, or later on, internally by the NIC TX).\n\nThe scheduler reads the current time on every dequeue invocation.\nThe CPU time stamp can be obtained by reading either the Time Stamp Counter (TSC) register or the High Precision Event Timer (HPET) register.\nThe current CPU time stamp is converted from number of CPU clocks to number of bytes:\n*time_bytes = time_cycles / cycles_per_byte, where cycles_per_byte*\nis the amount of CPU cycles that is equivalent to the transmission time for one byte on the wire\n(e.g. for a CPU frequency of 2 GHz and a 10GbE port,*cycles_per_byte = 1.6*).\n\nThe scheduler maintains an internal time reference of the NIC time.\nWhenever a packet is scheduled, the NIC time is incremented with the packet length (including framing overhead).\nOn every dequeue invocation, the scheduler checks its internal reference of the NIC time against the current time:\n\n#. If NIC time is in the future (NIC time >= current time), no adjustment of NIC time is needed.\n This means that scheduler is able to schedule NIC packets before the NIC actually needs those packets, so the NIC TX is well supplied with packets;\n\n#. If NIC time is in the past (NIC time < current time), then NIC time should be adjusted by setting it to the current time.\n This means that the scheduler is not able to keep up with the speed of the NIC byte conveyor belt,\n so NIC bandwidth is wasted due to poor packet supply to the NIC TX.\n\nScheduler Accuracy and Granularity\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThe scheduler round trip delay (SRTD) is the time (number of CPU cycles) between two consecutive examinations of the same pipe by the scheduler.\n\nTo keep up with the output port (that is, avoid bandwidth loss),\nthe scheduler should be able to schedule n packets faster than the same n packets are transmitted by NIC TX.\n\nThe scheduler needs to keep up with the rate of each individual pipe,\nas configured for the pipe token bucket, assuming that no port oversubscription is taking place.\nThis means that the size of the pipe token bucket should be set high enough to prevent it from overflowing due to big SRTD,\nas this would result in credit loss (and therefore bandwidth loss) for the pipe.\n\nCredit Logic\n^^^^^^^^^^^^\n\nScheduling Decision\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThe scheduling decision to send next packet from (subport S, pipe P, traffic class TC, queue Q) is favorable (packet is sent)\nwhen all the conditions below are met:\n\n* Pipe P of subport S is currently selected by one of the port grinders;\n\n* Traffic class TC is the highest priority active traffic class of pipe P;\n\n* Queue Q is the next queue selected by WRR within traffic class TC of pipe P;\n\n* Subport S has enough credits to send the packet;\n\n* Subport S has enough credits for traffic class TC to send the packet;\n\n* Pipe P has enough credits to send the packet;\n\n* Pipe P has enough credits for traffic class TC to send the packet.\n\nIf all the above conditions are met,\nthen the packet is selected for transmission and the necessary credits are subtracted from subport S,\nsubport S traffic class TC, pipe P, pipe P traffic class TC.\n\nFraming Overhead\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nAs the greatest common divisor for all packet lengths is one byte, the unit of credit is selected as one byte.\nThe number of credits required for the transmission of a packet of n bytes is equal to (n+h),\nwhere h is equal to the number of framing overhead bytes per packet.\n\n.. _table_qos_5:\n\n.. table:: Ethernet Frame Overhead Fields\n\n +---+--------------------------------+----------------+---------------------------------------------------------------------------+\n | # | Packet field | Length (bytes) | Comments |\n | | | | |\n +===+================================+================+===========================================================================+\n | 1 | Preamble | 7 | |\n | | | | |\n +---+--------------------------------+----------------+---------------------------------------------------------------------------+\n | 2 | Start of Frame Delimiter (SFD) | 1 | |\n | | | | |\n +---+--------------------------------+----------------+---------------------------------------------------------------------------+\n | 3 | Frame Check Sequence (FCS) | 4 | Considered overhead only if not included in the mbuf packet length field. |\n | | | | |\n +---+--------------------------------+----------------+---------------------------------------------------------------------------+\n | 4 | Inter Frame Gap (IFG) | 12 | |\n | | | | |\n +---+--------------------------------+----------------+---------------------------------------------------------------------------+\n | 5 | Total | 24 | |\n | | | | |\n +---+--------------------------------+----------------+---------------------------------------------------------------------------+\n\nTraffic Shaping\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThe traffic shaping for subport and pipe is implemented using a token bucket per subport/per pipe.\nEach token bucket is implemented using one saturated counter that keeps track of the number of available credits.\n\nThe token bucket generic parameters and operations are presented in :numref:`table_qos_6` and :numref:`table_qos_7`.\n\n.. _table_qos_6:\n\n.. table:: Token Bucket Generic Operations\n\n +---+------------------------+--------------------+---------------------------------------------------------+\n | # | Token Bucket Parameter | Unit | Description |\n | | | | |\n +===+========================+====================+=========================================================+\n | 1 | bucket_rate | Credits per second | Rate of adding credits to the bucket. |\n | | | | |\n +---+------------------------+--------------------+---------------------------------------------------------+\n | 2 | bucket_size | Credits | Max number of credits that can be stored in the bucket. |\n | | | | |\n +---+------------------------+--------------------+---------------------------------------------------------+\n\n.. _table_qos_7:\n\n.. table:: Token Bucket Generic Parameters\n\n +---+------------------------+------------------------------------------------------------------------------+\n | # | Token Bucket Operation | Description |\n | | | |\n +===+========================+==============================================================================+\n | 1 | Initialization | Bucket set to a predefined value, e.g. zero or half of the bucket size. |\n | | | |\n +---+------------------------+------------------------------------------------------------------------------+\n | 2 | Credit update | Credits are added to the bucket on top of existing ones, either periodically |\n | | | or on demand, based on the bucket_rate. Credits cannot exceed the upper |\n | | | limit defined by the bucket_size, so any credits to be added to the bucket |\n | | | while the bucket is full are dropped. |\n | | | |\n +---+------------------------+------------------------------------------------------------------------------+\n | 3 | Credit consumption | As result of packet scheduling, the necessary number of credits is removed |\n | | | from the bucket. The packet can only be sent if enough credits are in the |\n | | | bucket to send the full packet (packet bytes and framing overhead for the |\n | | | packet). |\n | | | |\n +---+------------------------+------------------------------------------------------------------------------+\n\nTo implement the token bucket generic operations described above,\nthe current design uses the persistent data structure presented in :numref:`table_qos_8`,\nwhile the implementation of the token bucket operations is described in :numref:`table_qos_9`.\n\n.. _table_qos_8:\n\n.. table:: Token Bucket Persistent Data Structure\n\n +---+------------------------+-------+----------------------------------------------------------------------+\n | # | Token bucket field | Unit | Description |\n | | | | |\n +===+========================+=======+======================================================================+\n | 1 | tb_time | Bytes | Time of the last credit update. Measured in bytes instead of seconds |\n | | | | or CPU cycles for ease of credit consumption operation |\n | | | | (as the current time is also maintained in bytes). |\n | | | | |\n | | | | See Section 26.2.4.5.1 \"Internal Time Reference\" for an |\n | | | | explanation of why the time is maintained in byte units. |\n | | | | |\n +---+------------------------+-------+----------------------------------------------------------------------+\n | 2 | tb_period | Bytes | Time period that should elapse since the last credit update in order |\n | | | | for the bucket to be awarded tb_credits_per_period worth or credits. |\n | | | | |\n +---+------------------------+-------+----------------------------------------------------------------------+\n | 3 | tb_credits_per_period | Bytes | Credit allowance per tb_period. |\n | | | | |\n +---+------------------------+-------+----------------------------------------------------------------------+\n | 4 | tb_size | Bytes | Bucket size, i.e. upper limit for the tb_credits. |\n | | | | |\n +---+------------------------+-------+----------------------------------------------------------------------+\n | 5 | tb_credits | Bytes | Number of credits currently in the bucket. |\n | | | | |\n +---+------------------------+-------+----------------------------------------------------------------------+\n\nThe bucket rate (in bytes per second) can be computed with the following formula:\n\n*bucket_rate = (tb_credits_per_period / tb_period) * r*\n\nwhere, r = port line rate (in bytes per second).\n\n.. _table_qos_9:\n\n.. table:: Token Bucket Operations\n\n +---+-------------------------+-----------------------------------------------------------------------------+\n | # | Token bucket operation | Description |\n | | | |\n +===+=========================+=============================================================================+\n | 1 | Initialization | *tb_credits = 0; or tb_credits = tb_size / 2;* |\n | | | |\n +---+-------------------------+-----------------------------------------------------------------------------+\n | 2 | Credit update | Credit update options: |\n | | | |\n | | | * Every time a packet is sent for a port, update the credits of all the |\n | | | the subports and pipes of that port. Not feasible. |\n | | | |\n | | | * Every time a packet is sent, update the credits for the pipe and |\n | | | subport. Very accurate, but not needed (a lot of calculations). |\n | | | |\n | | | * Every time a pipe is selected (that is, picked by one |\n | | | of the grinders), update the credits for the pipe and its subport. |\n | | | |\n | | | The current implementation is using option 3. According to Section |\n | | | 26.2.4.4 \"Dequeue State Machine\", the pipe and subport credits are |\n | | | updated every time a pipe is selected by the dequeue process before the |\n | | | pipe and subport credits are actually used. |\n | | | |\n | | | The implementation uses a tradeoff between accuracy and speed by updating |\n | | | the bucket credits only when at least a full *tb_period* has elapsed since |\n | | | the last update. |\n | | | |\n | | | * Full accuracy can be achieved by selecting the value for *tb_period* |\n | | | for which *tb_credits_per_period = 1*. |\n | | | |\n | | | * When full accuracy is not required, better performance is achieved by |\n | | | setting *tb_credits* to a larger value. |\n | | | |\n | | | Update operations: |\n | | | |\n | | | * n_periods = (time - tb_time) / tb_period; |\n | | | |\n | | | * tb_credits += n_periods * tb_credits_per_period; |\n | | | |\n | | | * tb_credits = min(tb_credits, tb_size); |\n | | | |\n | | | * tb_time += n_periods * tb_period; |\n | | | |\n +---+-------------------------+-----------------------------------------------------------------------------+\n | 3 | Credit consumption | As result of packet scheduling, the necessary number of credits is removed |\n | | (on packet scheduling) | from the bucket. The packet can only be sent if enough credits are in the |\n | | | bucket to send the full packet (packet bytes and framing overhead for the |\n | | | packet). |\n | | | |\n | | | Scheduling operations: |\n | | | |\n | | | pkt_credits = pkt_len + frame_overhead; |\n | | | if (tb_credits >= pkt_credits){tb_credits -= pkt_credits;} |\n | | | |\n +---+-------------------------+-----------------------------------------------------------------------------+\n\nTraffic Classes\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nImplementation of Strict Priority Scheduling\n''''''''''''''''''''''''''''''''''''''''''''\n\nStrict priority scheduling of traffic classes within the same pipe is implemented by the pipe dequeue state machine,\nwhich selects the queues in ascending order.\nTherefore, queues 0..3 (associated with TC 0, highest priority TC) are handled before\nqueues 4..7 (TC 1, lower priority than TC 0),\nwhich are handled before queues 8..11 (TC 2),\nwhich are handled before queues 12..15 (TC 3, lowest priority TC).\n\nUpper Limit Enforcement\n'''''''''''''''''''''''\n\nThe traffic classes at the pipe and subport levels are not traffic shaped,\nso there is no token bucket maintained in this context.\nThe upper limit for the traffic classes at the subport and\npipe levels is enforced by periodically refilling the subport / pipe traffic class credit counter,\nout of which credits are consumed every time a packet is scheduled for that subport / pipe,\nas described in :numref:`table_qos_10` and :numref:`table_qos_11`.\n\n.. _table_qos_10:\n\n.. table:: Subport/Pipe Traffic Class Upper Limit Enforcement Persistent Data Structure\n\n +---+-----------------------+-------+-----------------------------------------------------------------------+\n | # | Subport or pipe field | Unit | Description |\n | | | | |\n +===+=======================+=======+=======================================================================+\n | 1 | tc_time | Bytes | Time of the next update (upper limit refill) for the 4 TCs of the |\n | | | | current subport / pipe. |\n | | | | |\n | | | | See Section 26.2.4.5.1, \"Internal Time Reference\" for the |\n | | | | explanation of why the time is maintained in byte units. |\n | | | | |\n +---+-----------------------+-------+-----------------------------------------------------------------------+\n | 2 | tc_period | Bytes | Time between two consecutive updates for the 4 TCs of the current |\n | | | | subport / pipe. This is expected to be many times bigger than the |\n | | | | typical value of the token bucket tb_period. |\n | | | | |\n +---+-----------------------+-------+-----------------------------------------------------------------------+\n | 3 | tc_credits_per_period | Bytes | Upper limit for the number of credits allowed to be consumed by the |\n | | | | current TC during each enforcement period tc_period. |\n | | | | |\n +---+-----------------------+-------+-----------------------------------------------------------------------+\n | 4 | tc_credits | Bytes | Current upper limit for the number of credits that can be consumed by |\n | | | | the current traffic class for the remainder of the current |\n | | | | enforcement period. |\n | | | | |\n +---+-----------------------+-------+-----------------------------------------------------------------------+\n\n.. _table_qos_11:\n\n.. table:: Subport/Pipe Traffic Class Upper Limit Enforcement Operations\n\n +---+--------------------------+----------------------------------------------------------------------------+\n | # | Traffic Class Operation | Description |\n | | | |\n +===+==========================+============================================================================+\n | 1 | Initialization | tc_credits = tc_credits_per_period; |\n | | | |\n | | | tc_time = tc_period; |\n | | | |\n +---+--------------------------+----------------------------------------------------------------------------+\n | 2 | Credit update | Update operations: |\n | | | |\n | | | if (time >= tc_time) { |\n | | | |\n | | | tc_credits = tc_credits_per_period; |\n | | | |\n | | | tc_time = time + tc_period; |\n | | | |\n | | | } |\n | | | |\n +---+--------------------------+----------------------------------------------------------------------------+\n | 3 | Credit consumption | As result of packet scheduling, the TC limit is decreased with the |\n | | (on packet scheduling) | necessary number of credits. The packet can only be sent if enough credits |\n | | | are currently available in the TC limit to send the full packet |\n | | | (packet bytes and framing overhead for the packet). |\n | | | |\n | | | Scheduling operations: |\n | | | |\n | | | pkt_credits = pk_len + frame_overhead; |\n | | | |\n | | | if (tc_credits >= pkt_credits) {tc_credits -= pkt_credits;} |\n | | | |\n +---+--------------------------+----------------------------------------------------------------------------+\n\nWeighted Round Robin (WRR)\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThe evolution of the WRR design solution from simple to complex is shown in :numref:`table_qos_12`.\n\n.. _table_qos_12:\n\n.. table:: Weighted Round Robin (WRR)\n\n +---+------------+-----------------+-------------+----------------------------------------------------------+\n | # | All Queues | Equal Weights | All Packets | Strategy |\n | | Active? | for All Queues? | Equal? | |\n +===+============+=================+=============+==========================================================+\n | 1 | Yes | Yes | Yes | **Byte level round robin** |\n | | | | | |\n | | | | | *Next queue* queue #i, i = *(i + 1) % n* |\n | | | | | |\n +---+------------+-----------------+-------------+----------------------------------------------------------+\n | 2 | Yes | Yes | No | **Packet level round robin** |\n | | | | | |\n | | | | | Consuming one byte from queue #i requires consuming |\n | | | | | exactly one token for queue #i. |\n | | | | | |\n | | | | | T(i) = Accumulated number of tokens previously consumed |\n | | | | | from queue #i. Every time a packet is consumed from |\n | | | | | queue #i, T(i) is updated as: T(i) += *pkt_len*. |\n | | | | | |\n | | | | | *Next queue* : queue with the smallest T. |\n | | | | | |\n | | | | | |\n +---+------------+-----------------+-------------+----------------------------------------------------------+\n | 3 | Yes | No | No | **Packet level weighted round robin** |\n | | | | | |\n | | | | | This case can be reduced to the previous case by |\n | | | | | introducing a cost per byte that is different for each |\n | | | | | queue. Queues with lower weights have a higher cost per |\n | | | | | byte. This way, it is still meaningful to compare the |\n | | | | | consumption amongst different queues in order to select |\n | | | | | the next queue. |\n | | | | | |\n | | | | | w(i) = Weight of queue #i |\n | | | | | |\n | | | | | t(i) = Tokens per byte for queue #i, defined as the |\n | | | | | inverse weight of queue #i. |\n | | | | | For example, if w[0..3] = [1:2:4:8], |\n | | | | | then t[0..3] = [8:4:2:1]; if w[0..3] = [1:4:15:20], |\n | | | | | then t[0..3] = [60:15:4:3]. |\n | | | | | Consuming one byte from queue #i requires consuming t(i) |\n | | | | | tokens for queue #i. |\n | | | | | |\n | | | | | T(i) = Accumulated number of tokens previously consumed |\n | | | | | from queue #i. Every time a packet is consumed from |\n | | | | | queue #i, T(i) is updated as: *T(i) += pkt_len * t(i)*. |\n | | | | | *Next queue* : queue with the smallest T. |\n | | | | | |\n +---+------------+-----------------+-------------+----------------------------------------------------------+\n | 4 | No | No | No | **Packet level weighted round robin with variable queue |\n | | | | | status** |\n | | | | | |\n | | | | | Reduce this case to the previous case by setting the |\n | | | | | consumption of inactive queues to a high number, so that |\n | | | | | the inactive queues will never be selected by the |\n | | | | | smallest T logic. |\n | | | | | |\n | | | | | To prevent T from overflowing as result of successive |\n | | | | | accumulations, T(i) is truncated after each packet |\n | | | | | consumption for all queues. |\n | | | | | For example, T[0..3] = [1000, 1100, 1200, 1300] |\n | | | | | is truncated to T[0..3] = [0, 100, 200, 300] |\n | | | | | by subtracting the min T from T(i), i = 0..n. |\n | | | | | |\n | | | | | This requires having at least one active queue in the |\n | | | | | set of input queues, which is guaranteed by the dequeue |\n | | | | | state machine never selecting an inactive traffic class. |\n | | | | | |\n | | | | | *mask(i) = Saturation mask for queue #i, defined as:* |\n | | | | | |\n | | | | | mask(i) = (queue #i is active)? 0 : 0xFFFFFFFF; |\n | | | | | |\n | | | | | w(i) = Weight of queue #i |\n | | | | | |\n | | | | | t(i) = Tokens per byte for queue #i, defined as the |\n | | | | | inverse weight of queue #i. |\n | | | | | |\n | | | | | T(i) = Accumulated numbers of tokens previously consumed |\n | | | | | from queue #i. |\n | | | | | |\n | | | | | *Next queue* : queue with smallest T. |\n | | | | | |\n | | | | | Before packet consumption from queue #i: |\n | | | | | |\n | | | | | *T(i) |= mask(i)* |\n | | | | | |\n | | | | | After packet consumption from queue #i: |\n | | | | | |\n | | | | | T(j) -= T(i), j != i |\n | | | | | |\n | | | | | T(i) = pkt_len * t(i) |\n | | | | | |\n | | | | | Note: T(j) uses the T(i) value before T(i) is updated. |\n | | | | | |\n +---+------------+-----------------+-------------+----------------------------------------------------------+\n\nSubport Traffic Class Oversubscription\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nProblem Statement\n'''''''''''''''''\n\nOversubscription for subport traffic class X is a configuration-time event that occurs when\nmore bandwidth is allocated for traffic class X at the level of subport member pipes than\nallocated for the same traffic class at the parent subport level.\n\nThe existence of the oversubscription for a specific subport and\ntraffic class is solely the result of pipe and\nsubport-level configuration as opposed to being created due\nto dynamic evolution of the traffic load at run-time (as congestion is).\n\nWhen the overall demand for traffic class X for the current subport is low,\nthe existence of the oversubscription condition does not represent a problem,\nas demand for traffic class X is completely satisfied for all member pipes.\nHowever, this can no longer be achieved when the aggregated demand for traffic class X\nfor all subport member pipes exceeds the limit configured at the subport level.\n\nSolution Space\n''''''''''''''\n\nsummarizes some of the possible approaches for handling this problem,\nwith the third approach selected for implementation.\n\n.. _table_qos_13:\n\n.. table:: Subport Traffic Class Oversubscription\n\n +-----+---------------------------+-------------------------------------------------------------------------+\n | No. | Approach | Description |\n | | | |\n +=====+===========================+=========================================================================+\n | 1 | Don't care | First come, first served. |\n | | | |\n | | | This approach is not fair amongst subport member pipes, as pipes that |\n | | | are served first will use up as much bandwidth for TC X as they need, |\n | | | while pipes that are served later will receive poor service due to |\n | | | bandwidth for TC X at the subport level being scarce. |\n | | | |\n +-----+---------------------------+-------------------------------------------------------------------------+\n | 2 | Scale down all pipes | All pipes within the subport have their bandwidth limit for TC X scaled |\n | | | down by the same factor. |\n | | | |\n | | | This approach is not fair among subport member pipes, as the low end |\n | | | pipes (that is, pipes configured with low bandwidth) can potentially |\n | | | experience severe service degradation that might render their service |\n | | | unusable (if available bandwidth for these pipes drops below the |\n | | | minimum requirements for a workable service), while the service |\n | | | degradation for high end pipes might not be noticeable at all. |\n | | | |\n +-----+---------------------------+-------------------------------------------------------------------------+\n | 3 | Cap the high demand pipes | Each subport member pipe receives an equal share of the bandwidth |\n | | | available at run-time for TC X at the subport level. Any bandwidth left |\n | | | unused by the low-demand pipes is redistributed in equal portions to |\n | | | the high-demand pipes. This way, the high-demand pipes are truncated |\n | | | while the low-demand pipes are not impacted. |\n | | | |\n +-----+---------------------------+-------------------------------------------------------------------------+\n\nTypically, the subport TC oversubscription feature is enabled only for the lowest priority traffic class (TC 3),\nwhich is typically used for best effort traffic,\nwith the management plane preventing this condition from occurring for the other (higher priority) traffic classes.\n\nTo ease implementation, it is also assumed that the upper limit for subport TC 3 is set to 100% of the subport rate,\nand that the upper limit for pipe TC 3 is set to 100% of pipe rate for all subport member pipes.\n\nImplementation Overview\n'''''''''''''''''''''''\n\nThe algorithm computes a watermark, which is periodically updated based on the current demand experienced by the subport member pipes,\nwhose purpose is to limit the amount of traffic that each pipe is allowed to send for TC 3.\nThe watermark is computed at the subport level at the beginning of each traffic class upper limit enforcement period and\nthe same value is used by all the subport member pipes throughout the current enforcement period.\nillustrates how the watermark computed as subport level at the beginning of each period is propagated to all subport member pipes.\n\nAt the beginning of the current enforcement period (which coincides with the end of the previous enforcement period),\nthe value of the watermark is adjusted based on the amount of bandwidth allocated to TC 3 at the beginning of the previous period that\nwas not left unused by the subport member pipes at the end of the previous period.\n\nIf there was subport TC 3 bandwidth left unused,\nthe value of the watermark for the current period is increased to encourage the subport member pipes to consume more bandwidth.\nOtherwise, the value of the watermark is decreased to enforce equality of bandwidth consumption among subport member pipes for TC 3.\n\nThe increase or decrease in the watermark value is done in small increments,\nso several enforcement periods might be required to reach the equilibrium state.\nThis state can change at any moment due to variations in the demand experienced by the subport member pipes for TC 3, for example,\nas a result of demand increase (when the watermark needs to be lowered) or demand decrease (when the watermark needs to be increased).\n\nWhen demand is low, the watermark is set high to prevent it from impeding the subport member pipes from consuming more bandwidth.\nThe highest value for the watermark is picked as the highest rate configured for a subport member pipe.\n:numref:`table_qos_14` and :numref:`table_qos_15` illustrates the watermark operation.\n\n.. _table_qos_14:\n\n.. table:: Watermark Propagation from Subport Level to Member Pipes at the Beginning of Each Traffic Class Upper Limit Enforcement Period\n\n +-----+---------------------------------+----------------------------------------------------+\n | No. | Subport Traffic Class Operation | Description |\n | | | |\n +=====+=================================+====================================================+\n | 1 | Initialization | **Subport level**: subport_period_id= 0 |\n | | | |\n | | | **Pipe level**: pipe_period_id = 0 |\n | | | |\n +-----+---------------------------------+----------------------------------------------------+\n | 2 | Credit update | **Subport Level**: |\n | | | |\n | | | if (time>=subport_tc_time) |\n | | | |\n | | | { |\n | | | subport_wm = water_mark_update(); |\n | | | |\n | | | subport_tc_time = time + subport_tc_period; |\n | | | |\n | | | subport_period_id++; |\n | | | |\n | | | } |\n | | | |\n | | | **Pipelevel:** |\n | | | |\n | | | if(pipe_period_id != subport_period_id) |\n | | | |\n | | | { |\n | | | |\n | | | pipe_ov_credits = subport_wm \\* pipe_weight; |\n | | | |\n | | | pipe_period_id = subport_period_id; |\n | | | |\n | | | } |\n | | | |\n +-----+---------------------------------+----------------------------------------------------+\n | 3 | Credit consumption | **Pipe level:** |\n | | (on packet scheduling) | |\n | | | pkt_credits = pk_len + frame_overhead; |\n | | | |\n | | | if(pipe_ov_credits >= pkt_credits{ |\n | | | |\n | | | pipe_ov_credits -= pkt_credits; |\n | | | |\n | | | } |\n | | | |\n +-----+---------------------------------+----------------------------------------------------+\n\n.. _table_qos_15:\n\n.. table:: Watermark Calculation\n\n +-----+------------------+----------------------------------------------------------------------------------+\n | No. | Subport Traffic | Description |\n | | Class Operation | |\n +=====+==================+==================================================================================+\n | 1 | Initialization | **Subport level:** |\n | | | |\n | | | wm = WM_MAX |\n | | | |\n +-----+------------------+----------------------------------------------------------------------------------+\n | 2 | Credit update | **Subport level (water_mark_update):** |\n | | | |\n | | | tc0_cons = subport_tc0_credits_per_period - subport_tc0_credits; |\n | | | |\n | | | tc1_cons = subport_tc1_credits_per_period - subport_tc1_credits; |\n | | | |\n | | | tc2_cons = subport_tc2_credits_per_period - subport_tc2_credits; |\n | | | |\n | | | tc3_cons = subport_tc3_credits_per_period - subport_tc3_credits; |\n | | | |\n | | | tc3_cons_max = subport_tc3_credits_per_period - (tc0_cons + tc1_cons + |\n | | | tc2_cons); |\n | | | |\n | | | if(tc3_consumption > (tc3_consumption_max - MTU)){ |\n | | | |\n | | | wm -= wm >> 7; |\n | | | |\n | | | if(wm < WM_MIN) wm = WM_MIN; |\n | | | |\n | | | } else { |\n | | | |\n | | | wm += (wm >> 7) + 1; |\n | | | |\n | | | if(wm > WM_MAX) wm = WM_MAX; |\n | | | |\n | | | } |\n | | | |\n +-----+------------------+----------------------------------------------------------------------------------+\n\nWorst Case Scenarios for Performance\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nLots of Active Queues with Not Enough Credits\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe more queues the scheduler has to examine for packets and credits in order to select one packet,\nthe lower the performance of the scheduler is.\n\nThe scheduler maintains the bitmap of active queues, which skips the non-active queues,\nbut in order to detect whether a specific pipe has enough credits,\nthe pipe has to be drilled down using the pipe dequeue state machine,\nwhich consumes cycles regardless of the scheduling result\n(no packets are produced or at least one packet is produced).\n\nThis scenario stresses the importance of the policer for the scheduler performance:\nif the pipe does not have enough credits,\nits packets should be dropped as soon as possible (before they reach the hierarchical scheduler),\nthus rendering the pipe queues as not active,\nwhich allows the dequeue side to skip that pipe with no cycles being spent on investigating the pipe credits\nthat would result in a \"not enough credits\" status.\n\nSingle Queue with 100% Line Rate\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe port scheduler performance is optimized for a large number of queues.\nIf the number of queues is small,\nthen the performance of the port scheduler for the same level of active traffic is expected to be worse than\nthe performance of a small set of message passing queues.\n\n.. _Dropper:\n\nDropper\n-------\n\nThe purpose of the DPDK dropper is to drop packets arriving at a packet scheduler to avoid congestion.\nThe dropper supports the Random Early Detection (RED),\nWeighted Random Early Detection (WRED) and tail drop algorithms.\n:numref:`figure_blk_diag_dropper` illustrates how the dropper integrates with the scheduler.\nThe DPDK currently does not support congestion management\nso the dropper provides the only method for congestion avoidance.\n\n.. _figure_blk_diag_dropper:\n\n.. figure:: img/blk_diag_dropper.*\n\n High-level Block Diagram of the DPDK Dropper\n\n\nThe dropper uses the Random Early Detection (RED) congestion avoidance algorithm as documented in the reference publication.\nThe purpose of the RED algorithm is to monitor a packet queue,\ndetermine the current congestion level in the queue and decide whether an arriving packet should be enqueued or dropped.\nThe RED algorithm uses an Exponential Weighted Moving Average (EWMA) filter to compute average queue size which\ngives an indication of the current congestion level in the queue.\n\nFor each enqueue operation, the RED algorithm compares the average queue size to minimum and maximum thresholds.\nDepending on whether the average queue size is below, above or in between these thresholds,\nthe RED algorithm calculates the probability that an arriving packet should be dropped and\nmakes a random decision based on this probability.\n\nThe dropper also supports Weighted Random Early Detection (WRED) by allowing the scheduler to select\ndifferent RED configurations for the same packet queue at run-time.\nIn the case of severe congestion, the dropper resorts to tail drop.\nThis occurs when a packet queue has reached maximum capacity and cannot store any more packets.\nIn this situation, all arriving packets are dropped.\n\nThe flow through the dropper is illustrated in :numref:`figure_flow_tru_droppper`.\nThe RED/WRED algorithm is exercised first and tail drop second.\n\n.. _figure_flow_tru_droppper:\n\n.. figure:: img/flow_tru_droppper.*\n\n Flow Through the Dropper\n\n\nThe use cases supported by the dropper are:\n\n* * Initialize configuration data\n\n* * Initialize run-time data\n\n* * Enqueue (make a decision to enqueue or drop an arriving packet)\n\n* * Mark empty (record the time at which a packet queue becomes empty)\n\nThe configuration use case is explained in :ref:`Section2.23.3.1 `,\nthe enqueue operation is explained in :ref:`Section 2.23.3.2 `\nand the mark empty operation is explained in :ref:`Section 2.23.3.3 `.\n\n.. _Configuration:\n\nConfiguration\n~~~~~~~~~~~~~\n\nA RED configuration contains the parameters given in :numref:`table_qos_16`.\n\n.. _table_qos_16:\n\n.. table:: RED Configuration Parameters\n\n +--------------------------+---------+---------+------------------+\n | Parameter | Minimum | Maximum | Typical |\n | | | | |\n +==========================+=========+=========+==================+\n | Minimum Threshold | 0 | 1022 | 1/4 x queue size |\n | | | | |\n +--------------------------+---------+---------+------------------+\n | Maximum Threshold | 1 | 1023 | 1/2 x queue size |\n | | | | |\n +--------------------------+---------+---------+------------------+\n | Inverse Mark Probability | 1 | 255 | 10 |\n | | | | |\n +--------------------------+---------+---------+------------------+\n | EWMA Filter Weight | 1 | 12 | 9 |\n | | | | |\n +--------------------------+---------+---------+------------------+\n\nThe meaning of these parameters is explained in more detail in the following sections.\nThe format of these parameters as specified to the dropper module API\ncorresponds to the format used by Cisco* in their RED implementation.\nThe minimum and maximum threshold parameters are specified to the dropper module in terms of number of packets.\nThe mark probability parameter is specified as an inverse value, for example,\nan inverse mark probability parameter value of 10 corresponds\nto a mark probability of 1/10 (that is, 1 in 10 packets will be dropped).\nThe EWMA filter weight parameter is specified as an inverse log value,\nfor example, a filter weight parameter value of 9 corresponds to a filter weight of 1/29.\n\n.. _Enqueue_Operation:\n\nEnqueue Operation\n~~~~~~~~~~~~~~~~~\n\nIn the example shown in :numref:`figure_ex_data_flow_tru_dropper`, q (actual queue size) is the input value,\navg (average queue size) and count (number of packets since the last drop) are run-time values,\ndecision is the output value and the remaining values are configuration parameters.\n\n.. _figure_ex_data_flow_tru_dropper:\n\n.. figure:: img/ex_data_flow_tru_dropper.*\n\n Example Data Flow Through Dropper\n\n\nEWMA Filter Microblock\n^^^^^^^^^^^^^^^^^^^^^^\n\nThe purpose of the EWMA Filter microblock is to filter queue size values to smooth out transient changes\nthat result from \"bursty\" traffic.\nThe output value is the average queue size which gives a more stable view of the current congestion level in the queue.\n\nThe EWMA filter has one configuration parameter, filter weight, which determines how quickly\nor slowly the average queue size output responds to changes in the actual queue size input.\nHigher values of filter weight mean that the average queue size responds more quickly to changes in actual queue size.\n\nAverage Queue Size Calculation when the Queue is not Empty\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThe definition of the EWMA filter is given in the following equation.\n\n.. image:: img/ewma_filter_eq_1.*\n\nWhere:\n\n* *avg* = average queue size\n\n* *wq* = filter weight\n\n* *q* = actual queue size\n\n.. note::\n\n The filter weight, wq = 1/2^n, where n is the filter weight parameter value passed to the dropper module\n\ton configuration (see :ref:`Section2.23.3.1 ` ).\n\nAverage Queue Size Calculation when the Queue is Empty\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe EWMA filter does not read time stamps and instead assumes that enqueue operations will happen quite regularly.\nSpecial handling is required when the queue becomes empty as the queue could be empty for a short time or a long time.\nWhen the queue becomes empty, average queue size should decay gradually to zero instead of dropping suddenly to zero\nor remaining stagnant at the last computed value.\nWhen a packet is enqueued on an empty queue, the average queue size is computed using the following formula:\n\n.. image:: img/ewma_filter_eq_2.*\n\nWhere:\n\n* *m* = the number of enqueue operations that could have occurred on this queue while the queue was empty\n\nIn the dropper module, *m* is defined as:\n\n.. image:: img/m_definition.*\n\nWhere:\n\n* *time* = current time\n\n* *qtime* = time the queue became empty\n\n* *s* = typical time between successive enqueue operations on this queue\n\nThe time reference is in units of bytes,\nwhere a byte signifies the time duration required by the physical interface to send out a byte on the transmission medium\n(see Section 26.2.4.5.1 \"Internal Time Reference\").\nThe parameter s is defined in the dropper module as a constant with the value: s=2^22.\nThis corresponds to the time required by every leaf node in a hierarchy with 64K leaf nodes\nto transmit one 64-byte packet onto the wire and represents the worst case scenario.\nFor much smaller scheduler hierarchies,\nit may be necessary to reduce the parameter s, which is defined in the red header source file (rte_red.h) as:\n\n.. code-block:: c\n\n #define RTE_RED_S\n\nSince the time reference is in bytes, the port speed is implied in the expression: *time-qtime*.\nThe dropper does not have to be configured with the actual port speed.\nIt adjusts automatically to low speed and high speed links.\n\nImplementation\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nA numerical method is used to compute the factor (1-wq)^m that appears in Equation 2.\n\nThis method is based on the following identity:\n\n.. image:: img/eq2_factor.*\n\n\nThis allows us to express the following:\n\n.. image:: img/eq2_expression.*\n\n\nIn the dropper module, a look-up table is used to compute log2(1-wq) for each value of wq supported by the dropper module.\nThe factor (1-wq)^m can then be obtained by multiplying the table value by *m* and applying shift operations.\nTo avoid overflow in the multiplication, the value, *m*, and the look-up table values are limited to 16 bits.\nThe total size of the look-up table is 56 bytes.\nOnce the factor (1-wq)^m is obtained using this method, the average queue size can be calculated from Equation 2.\n\nAlternative Approaches\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nOther methods for calculating the factor (1-wq)^m in the expression for computing average queue size\nwhen the queue is empty (Equation 2) were considered.\nThese approaches include:\n\n* Floating-point evaluation\n\n* Fixed-point evaluation using a small look-up table (512B) and up to 16 multiplications\n (this is the approach used in the FreeBSD* ALTQ RED implementation)\n\n* Fixed-point evaluation using a small look-up table (512B) and 16 SSE multiplications\n (SSE optimized version of the approach used in the FreeBSD* ALTQ RED implementation)\n\n* Large look-up table (76 KB)\n\nThe method that was finally selected (described above in Section 26.3.2.2.1) out performs all of these approaches\nin terms of run-time performance and memory requirements and\nalso achieves accuracy comparable to floating-point evaluation.\n:numref:`table_qos_17` lists the performance of each of these alternative approaches relative to the method that is used in the dropper.\nAs can be seen, the floating-point implementation achieved the worst performance.\n\n.. _table_qos_17:\n\n.. table:: Relative Performance of Alternative Approaches\n\n +------------------------------------------------------------------------------------+----------------------+\n | Method | Relative Performance |\n | | |\n +====================================================================================+======================+\n | Current dropper method (see :ref:`Section 23.3.2.1.3 `) | 100% |\n | | |\n +------------------------------------------------------------------------------------+----------------------+\n | Fixed-point method with small (512B) look-up table | 148% |\n | | |\n +------------------------------------------------------------------------------------+----------------------+\n | SSE method with small (512B) look-up table | 114% |\n | | |\n +------------------------------------------------------------------------------------+----------------------+\n | Large (76KB) look-up table | 118% |\n | | |\n +------------------------------------------------------------------------------------+----------------------+\n | Floating-point | 595% |\n | | |\n +------------------------------------------------------------------------------------+----------------------+\n | **Note**: In this case, since performance is expressed as time spent executing the operation in a |\n | specific condition, any relative performance value above 100% runs slower than the reference method. |\n | |\n +-----------------------------------------------------------------------------------------------------------+\n\nDrop Decision Block\n^^^^^^^^^^^^^^^^^^^\n\nThe Drop Decision block:\n\n* Compares the average queue size with the minimum and maximum thresholds\n\n* Calculates a packet drop probability\n\n* Makes a random decision to enqueue or drop an arriving packet\n\nThe calculation of the drop probability occurs in two stages.\nAn initial drop probability is calculated based on the average queue size,\nthe minimum and maximum thresholds and the mark probability.\nAn actual drop probability is then computed from the initial drop probability.\nThe actual drop probability takes the count run-time value into consideration\nso that the actual drop probability increases as more packets arrive to the packet queue\nsince the last packet was dropped.\n\nInitial Packet Drop Probability\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThe initial drop probability is calculated using the following equation.\n\n.. image:: img/drop_probability_eq3.*\n\nWhere:\n\n* *maxp* = mark probability\n\n* *avg* = average queue size\n\n* *minth* = minimum threshold\n\n* *maxth* = maximum threshold\n\nThe calculation of the packet drop probability using Equation 3 is illustrated in :numref:`figure_pkt_drop_probability`.\nIf the average queue size is below the minimum threshold, an arriving packet is enqueued.\nIf the average queue size is at or above the maximum threshold, an arriving packet is dropped.\nIf the average queue size is between the minimum and maximum thresholds,\na drop probability is calculated to determine if the packet should be enqueued or dropped.\n\n.. _figure_pkt_drop_probability:\n\n.. figure:: img/pkt_drop_probability.*\n\n Packet Drop Probability for a Given RED Configuration\n\n\nActual Drop Probability\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nIf the average queue size is between the minimum and maximum thresholds,\nthen the actual drop probability is calculated from the following equation.\n\n.. image:: img/drop_probability_eq4.*\n\nWhere:\n\n* *Pb* = initial drop probability (from Equation 3)\n\n* *count* = number of packets that have arrived since the last drop\n\nThe constant 2, in Equation 4 is the only deviation from the drop probability formulae\ngiven in the reference document where a value of 1 is used instead.\nIt should be noted that the value pa computed from can be negative or greater than 1.\nIf this is the case, then a value of 1 should be used instead.\n\nThe initial and actual drop probabilities are shown in :numref:`figure_drop_probability_graph`.\nThe actual drop probability is shown for the case where\nthe formula given in the reference document1 is used (blue curve)\nand also for the case where the formula implemented in the dropper module,\nis used (red curve).\nThe formula in the reference document results in a significantly higher drop rate\ncompared to the mark probability configuration parameter specified by the user.\nThe choice to deviate from the reference document is simply a design decision and\none that has been taken by other RED implementations, for example, FreeBSD* ALTQ RED.\n\n.. _figure_drop_probability_graph:\n\n.. figure:: img/drop_probability_graph.*\n\n Initial Drop Probability (pb), Actual Drop probability (pa) Computed Using\n a Factor 1 (Blue Curve) and a Factor 2 (Red Curve)\n\n\n.. _Queue_Empty_Operation:\n\nQueue Empty Operation\n~~~~~~~~~~~~~~~~~~~~~\n\nThe time at which a packet queue becomes empty must be recorded and saved with the RED run-time data\nso that the EWMA filter block can calculate the average queue size on the next enqueue operation.\nIt is the responsibility of the calling application to inform the dropper module\nthrough the API that a queue has become empty.\n\nSource Files Location\n~~~~~~~~~~~~~~~~~~~~~\n\nThe source files for the DPDK dropper are located at:\n\n* DPDK/lib/librte_sched/rte_red.h\n\n* DPDK/lib/librte_sched/rte_red.c\n\nIntegration with the DPDK QoS Scheduler\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nRED functionality in the DPDK QoS scheduler is disabled by default.\nTo enable it, use the DPDK configuration parameter:\n\n::\n\n CONFIG_RTE_SCHED_RED=y\n\nThis parameter must be set to y.\nThe parameter is found in the build configuration files in the DPDK/config directory,\nfor example, DPDK/config/common_linuxapp.\nRED configuration parameters are specified in the rte_red_params structure within the rte_sched_port_params structure\nthat is passed to the scheduler on initialization.\nRED parameters are specified separately for four traffic classes and three packet colors (green, yellow and red)\nallowing the scheduler to implement Weighted Random Early Detection (WRED).\n\nIntegration with the DPDK QoS Scheduler Sample Application\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe DPDK QoS Scheduler Application reads a configuration file on start-up.\nThe configuration file includes a section containing RED parameters.\nThe format of these parameters is described in :ref:`Section2.23.3.1 `.\nA sample RED configuration is shown below. In this example, the queue size is 64 packets.\n\n.. note::\n\n For correct operation, the same EWMA filter weight parameter (wred weight) should be used\n for each packet color (green, yellow, red) in the same traffic class (tc).\n\n::\n\n ; RED params per traffic class and color (Green / Yellow / Red)\n\n [red]\n tc 0 wred min = 28 22 16\n tc 0 wred max = 32 32 32\n tc 0 wred inv prob = 10 10 10\n tc 0 wred weight = 9 9 9\n\n tc 1 wred min = 28 22 16\n tc 1 wred max = 32 32 32\n tc 1 wred inv prob = 10 10 10\n tc 1 wred weight = 9 9 9\n\n tc 2 wred min = 28 22 16\n tc 2 wred max = 32 32 32\n tc 2 wred inv prob = 10 10 10\n tc 2 wred weight = 9 9 9\n\n tc 3 wred min = 28 22 16\n tc 3 wred max = 32 32 32\n tc 3 wred inv prob = 10 10 10\n tc 3 wred weight = 9 9 9\n\nWith this configuration file, the RED configuration that applies to green,\nyellow and red packets in traffic class 0 is shown in :numref:`table_qos_18`.\n\n.. _table_qos_18:\n\n.. table:: RED Configuration Corresponding to RED Configuration File\n\n +--------------------+--------------------+-------+--------+-----+\n | RED Parameter | Configuration Name | Green | Yellow | Red |\n | | | | | |\n +====================+====================+=======+========+=====+\n | Minimum Threshold | tc 0 wred min | 28 | 22 | 16 |\n | | | | | |\n +--------------------+--------------------+-------+--------+-----+\n | Maximum Threshold | tc 0 wred max | 32 | 32 | 32 |\n | | | | | |\n +--------------------+--------------------+-------+--------+-----+\n | Mark Probability | tc 0 wred inv prob | 10 | 10 | 10 |\n | | | | | |\n +--------------------+--------------------+-------+--------+-----+\n | EWMA Filter Weight | tc 0 wred weight | 9 | 9 | 9 |\n | | | | | |\n +--------------------+--------------------+-------+--------+-----+\n\nApplication Programming Interface (API)\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nEnqueue API\n^^^^^^^^^^^\n\nThe syntax of the enqueue API is as follows:\n\n.. code-block:: c\n\n int rte_red_enqueue(const struct rte_red_config *red_cfg, struct rte_red *red, const unsigned q, const uint64_t time)\n\n\nThe arguments passed to the enqueue API are configuration data, run-time data,\nthe current size of the packet queue (in packets) and a value representing the current time.\nThe time reference is in units of bytes,\nwhere a byte signifies the time duration required by the physical interface to send out a byte on the transmission medium\n(see Section 26.2.4.5.1 \"Internal Time Reference\" ).\nThe dropper reuses the scheduler time stamps for performance reasons.\n\nEmpty API\n^^^^^^^^^\n\nThe syntax of the empty API is as follows:\n\n.. code-block:: c\n\n void rte_red_mark_queue_empty(struct rte_red *red, const uint64_t time)\n\nThe arguments passed to the empty API are run-time data and the current time in bytes.\n\nTraffic Metering\n----------------\n\nThe traffic metering component implements the Single Rate Three Color Marker (srTCM) and\nTwo Rate Three Color Marker (trTCM) algorithms, as defined by IETF RFC 2697 and 2698 respectively.\nThese algorithms meter the stream of incoming packets based on the allowance defined in advance for each traffic flow.\nAs result, each incoming packet is tagged as green,\nyellow or red based on the monitored consumption of the flow the packet belongs to.\n\nFunctional Overview\n~~~~~~~~~~~~~~~~~~~\n\nThe srTCM algorithm defines two token buckets for each traffic flow,\nwith the two buckets sharing the same token update rate:\n\n* Committed (C) bucket: fed with tokens at the rate defined by the Committed Information Rate (CIR) parameter\n (measured in IP packet bytes per second).\n The size of the C bucket is defined by the Committed Burst Size (CBS) parameter (measured in bytes);\n\n* Excess (E) bucket: fed with tokens at the same rate as the C bucket.\n The size of the E bucket is defined by the Excess Burst Size (EBS) parameter (measured in bytes).\n\nThe trTCM algorithm defines two token buckets for each traffic flow,\nwith the two buckets being updated with tokens at independent rates:\n\n* Committed (C) bucket: fed with tokens at the rate defined by the Committed Information Rate (CIR) parameter\n (measured in bytes of IP packet per second).\n The size of the C bucket is defined by the Committed Burst Size (CBS) parameter (measured in bytes);\n\n* Peak (P) bucket: fed with tokens at the rate defined by the Peak Information Rate (PIR) parameter\n (measured in IP packet bytes per second).\n The size of the P bucket is defined by the Peak Burst Size (PBS) parameter (measured in bytes).\n\nPlease refer to RFC 2697 (for srTCM) and RFC 2698 (for trTCM) for details on how tokens are consumed\nfrom the buckets and how the packet color is determined.\n\nColor Blind and Color Aware Modes\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nFor both algorithms, the color blind mode is functionally equivalent to the color aware mode with input color set as green.\nFor color aware mode, a packet with red input color can only get the red output color,\nwhile a packet with yellow input color can only get the yellow or red output colors.\n\nThe reason why the color blind mode is still implemented distinctly than the color aware mode is\nthat color blind mode can be implemented with fewer operations than the color aware mode.\n\nImplementation Overview\n~~~~~~~~~~~~~~~~~~~~~~~\n\nFor each input packet, the steps for the srTCM / trTCM algorithms are:\n\n* Update the C and E / P token buckets. This is done by reading the current time (from the CPU timestamp counter),\n identifying the amount of time since the last bucket update and computing the associated number of tokens\n (according to the pre-configured bucket rate).\n The number of tokens in the bucket is limited by the pre-configured bucket size;\n\n* Identify the output color for the current packet based on the size of the IP packet\n and the amount of tokens currently available in the C and E / P buckets; for color aware mode only,\n the input color of the packet is also considered.\n When the output color is not red, a number of tokens equal to the length of the IP packet are\n subtracted from the C or E /P or both buckets, depending on the algorithm and the output color of the packet.\n" }, { "path": "doc/guides/prog_guide/reorder_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Reorder_Library:\n\nReorder Library\n=================\n\nThe Reorder Library provides a mechanism for reordering mbufs based on their\nsequence number.\n\nOperation\n----------\n\nThe reorder library is essentially a buffer that reorders mbufs.\nThe user inserts out of order mbufs into the reorder buffer and pulls in-order\nmbufs from it.\n\nAt a given time, the reorder buffer contains mbufs whose sequence number are\ninside the sequence window. The sequence window is determined by the minimum\nsequence number and the number of entries that the buffer was configured to hold.\nFor example, given a reorder buffer with 200 entries and a minimum sequence\nnumber of 350, the sequence window has low and high limits of 350 and 550\nrespectively.\n\nWhen inserting mbufs, the reorder library differentiates between valid, early\nand late mbufs depending on the sequence number of the inserted mbuf:\n\n* valid: the sequence number is inside the window.\n* late: the sequence number is outside the window and less than the low limit.\n* early: the sequence number is outside the window and greater than the high\n limit.\n\nThe reorder buffer directly returns late mbufs and tries to accommodate early\nmbufs.\n\n\nImplementation Details\n-------------------------\n\nThe reorder library is implemented as a pair of buffers, which referred to as\nthe *Order* buffer and the *Ready* buffer.\n\nOn an insert call, valid mbufs are inserted directly into the Order buffer and\nlate mbufs are returned to the user with an error.\n\nIn the case of early mbufs, the reorder buffer will try to move the window\n(incrementing the minimum sequence number) so that the mbuf becomes a valid one.\nTo that end, mbufs in the Order buffer are moved into the Ready buffer.\nAny mbufs that have not arrived yet are ignored and therefore will become\nlate mbufs.\nThis means that as long as there is room in the Ready buffer, the window will\nbe moved to accommodate early mbufs that would otherwise be outside the\nreordering window.\n\nFor example, assuming that we have a buffer of 200 entries with a 350 minimum\nsequence number, and we need to insert an early mbuf with 565 sequence number.\nThat means that we would need to move the windows at least 15 positions to\naccommodate the mbuf.\nThe reorder buffer would try to move mbufs from at least the next 15 slots in\nthe Order buffer to the Ready buffer, as long as there is room in the Ready buffer.\nAny gaps in the Order buffer at that point are skipped, and those packet will\nbe reported as late packets when they arrive. The process of moving packets\nto the Ready buffer continues beyond the minimum required until a gap,\ni.e. missing mbuf, in the Order buffer is encountered.\n\nWhen draining mbufs, the reorder buffer would return mbufs in the Ready\nbuffer first and then from the Order buffer until a gap is found (mbufs that\nhave not arrived yet).\n\nUse Case: Packet Distributor\n-------------------------------\n\nAn application using the DPDK packet distributor could make use of the reorder\nlibrary to transmit packets in the same order they were received.\n\nA basic packet distributor use case would consist of a distributor with\nmultiple workers cores.\nThe processing of packets by the workers is not guaranteed to be in order,\nhence a reorder buffer can be used to order as many packets as possible.\n\nIn such a scenario, the distributor assigns a sequence number to mbufs before\ndelivering them to the workers.\nAs the workers finish processing the packets, the distributor inserts those\nmbufs into the reorder buffer and finally transmit drained mbufs.\n\nNOTE: Currently the reorder buffer is not thread safe so the same thread is\nresponsible for inserting and draining mbufs.\n" }, { "path": "doc/guides/prog_guide/ring_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Ring_Library:\n\nRing Library\n============\n\nThe ring allows the management of queues.\nInstead of having a linked list of infinite size, the rte_ring has the following properties:\n\n* FIFO\n\n* Maximum size is fixed, the pointers are stored in a table\n\n* Lockless implementation\n\n* Multi-consumer or single-consumer dequeue\n\n* Multi-producer or single-producer enqueue\n\n* Bulk dequeue - Dequeues the specified count of objects if successful; otherwise fails\n\n* Bulk enqueue - Enqueues the specified count of objects if successful; otherwise fails\n\n* Burst dequeue - Dequeue the maximum available objects if the specified count cannot be fulfilled\n\n* Burst enqueue - Enqueue the maximum available objects if the specified count cannot be fulfilled\n\nThe advantages of this data structure over a linked list queue are as follows:\n\n* Faster; only requires a single Compare-And-Swap instruction of sizeof(void \\*) instead of several double-Compare-And-Swap instructions.\n\n* Simpler than a full lockless queue.\n\n* Adapted to bulk enqueue/dequeue operations.\n As pointers are stored in a table, a dequeue of several objects will not produce as many cache misses as in a linked queue.\n Also, a bulk dequeue of many objects does not cost more than a dequeue of a simple object.\n\nThe disadvantages:\n\n* Size is fixed\n\n* Having many rings costs more in terms of memory than a linked list queue. An empty ring contains at least N pointers.\n\nA simplified representation of a Ring is shown in with consumer and producer head and tail pointers to objects stored in the data structure.\n\n.. _figure_ring1:\n\n.. figure:: img/ring1.*\n\n Ring Structure\n\n\nReferences for Ring Implementation in FreeBSD*\n----------------------------------------------\n\nThe following code was added in FreeBSD 8.0, and is used in some network device drivers (at least in Intel drivers):\n\n * `bufring.h in FreeBSD `_\n\n * `bufring.c in FreeBSD `_\n\nLockless Ring Buffer in Linux*\n------------------------------\n\nThe following is a link describing the `Linux Lockless Ring Buffer Design `_.\n\nAdditional Features\n-------------------\n\nName\n~~~~\n\nA ring is identified by a unique name.\nIt is not possible to create two rings with the same name (rte_ring_create() returns NULL if this is attempted).\n\nWater Marking\n~~~~~~~~~~~~~\n\nThe ring can have a high water mark (threshold).\nOnce an enqueue operation reaches the high water mark, the producer is notified, if the water mark is configured.\n\nThis mechanism can be used, for example, to exert a back pressure on I/O to inform the LAN to PAUSE.\n\nDebug\n~~~~~\n\nWhen debug is enabled (CONFIG_RTE_LIBRTE_RING_DEBUG is set),\nthe library stores some per-ring statistic counters about the number of enqueues/dequeues.\nThese statistics are per-core to avoid concurrent accesses or atomic operations.\n\nUse Cases\n---------\n\nUse cases for the Ring library include:\n\n * Communication between applications in the DPDK\n\n * Used by memory pool allocator\n\nAnatomy of a Ring Buffer\n------------------------\n\nThis section explains how a ring buffer operates.\nThe ring structure is composed of two head and tail couples; one is used by producers and one is used by the consumers.\nThe figures of the following sections refer to them as prod_head, prod_tail, cons_head and cons_tail.\n\nEach figure represents a simplified state of the ring, which is a circular buffer.\nThe content of the function local variables is represented on the top of the figure,\nand the content of ring structure is represented on the bottom of the figure.\n\nSingle Producer Enqueue\n~~~~~~~~~~~~~~~~~~~~~~~\n\nThis section explains what occurs when a producer adds an object to the ring.\nIn this example, only the producer head and tail (prod_head and prod_tail) are modified,\nand there is only one producer.\n\nThe initial state is to have a prod_head and prod_tail pointing at the same location.\n\nEnqueue First Step\n^^^^^^^^^^^^^^^^^^\n\nFirst, *ring->prod_head* and ring->cons_tail are copied in local variables.\nThe prod_next local variable points to the next element of the table, or several elements after in case of bulk enqueue.\n\nIf there is not enough room in the ring (this is detected by checking cons_tail), it returns an error.\n\n\n.. _figure_ring-enqueue1:\n\n.. figure:: img/ring-enqueue1.*\n\n Enqueue first step\n\n\nEnqueue Second Step\n^^^^^^^^^^^^^^^^^^^\n\nThe second step is to modify *ring->prod_head* in ring structure to point to the same location as prod_next.\n\nA pointer to the added object is copied in the ring (obj4).\n\n\n.. _figure_ring-enqueue2:\n\n.. figure:: img/ring-enqueue2.*\n\n Enqueue second step\n\n\nEnqueue Last Step\n^^^^^^^^^^^^^^^^^\n\nOnce the object is added in the ring, ring->prod_tail in the ring structure is modified to point to the same location as *ring->prod_head*.\nThe enqueue operation is finished.\n\n\n.. _figure_ring-enqueue3:\n\n.. figure:: img/ring-enqueue3.*\n\n Enqueue last step\n\n\nSingle Consumer Dequeue\n~~~~~~~~~~~~~~~~~~~~~~~\n\nThis section explains what occurs when a consumer dequeues an object from the ring.\nIn this example, only the consumer head and tail (cons_head and cons_tail) are modified and there is only one consumer.\n\nThe initial state is to have a cons_head and cons_tail pointing at the same location.\n\nDequeue First Step\n^^^^^^^^^^^^^^^^^^\n\nFirst, ring->cons_head and ring->prod_tail are copied in local variables.\nThe cons_next local variable points to the next element of the table, or several elements after in the case of bulk dequeue.\n\nIf there are not enough objects in the ring (this is detected by checking prod_tail), it returns an error.\n\n\n.. _figure_ring-dequeue1:\n\n.. figure:: img/ring-dequeue1.*\n\n Dequeue last step\n\n\nDequeue Second Step\n^^^^^^^^^^^^^^^^^^^\n\nThe second step is to modify ring->cons_head in the ring structure to point to the same location as cons_next.\n\nThe pointer to the dequeued object (obj1) is copied in the pointer given by the user.\n\n\n.. _figure_ring-dequeue2:\n\n.. figure:: img/ring-dequeue2.*\n\n Dequeue second step\n\n\nDequeue Last Step\n^^^^^^^^^^^^^^^^^\n\nFinally, ring->cons_tail in the ring structure is modified to point to the same location as ring->cons_head.\nThe dequeue operation is finished.\n\n\n.. _figure_ring-dequeue3:\n\n.. figure:: img/ring-dequeue3.*\n\n Dequeue last step\n\n\nMultiple Producers Enqueue\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThis section explains what occurs when two producers concurrently add an object to the ring.\nIn this example, only the producer head and tail (prod_head and prod_tail) are modified.\n\nThe initial state is to have a prod_head and prod_tail pointing at the same location.\n\nMultiple Consumer Enqueue First Step\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nOn both cores, *ring->prod_head* and ring->cons_tail are copied in local variables.\nThe prod_next local variable points to the next element of the table,\nor several elements after in the case of bulk enqueue.\n\nIf there is not enough room in the ring (this is detected by checking cons_tail), it returns an error.\n\n\n.. _figure_ring-mp-enqueue1:\n\n.. figure:: img/ring-mp-enqueue1.*\n\n Multiple consumer enqueue first step\n\n\nMultiple Consumer Enqueue Second Step\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe second step is to modify ring->prod_head in the ring structure to point to the same location as prod_next.\nThis operation is done using a Compare And Swap (CAS) instruction, which does the following operations atomically:\n\n* If ring->prod_head is different to local variable prod_head,\n the CAS operation fails, and the code restarts at first step.\n\n* Otherwise, ring->prod_head is set to local prod_next,\n the CAS operation is successful, and processing continues.\n\nIn the figure, the operation succeeded on core 1, and step one restarted on core 2.\n\n\n.. _figure_ring-mp-enqueue2:\n\n.. figure:: img/ring-mp-enqueue2.*\n\n Multiple consumer enqueue second step\n\n\nMultiple Consumer Enqueue Third Step\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe CAS operation is retried on core 2 with success.\n\nThe core 1 updates one element of the ring(obj4), and the core 2 updates another one (obj5).\n\n\n.. _figure_ring-mp-enqueue3:\n\n.. figure:: img/ring-mp-enqueue3.*\n\n Multiple consumer enqueue third step\n\n\nMultiple Consumer Enqueue Fourth Step\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nEach core now wants to update ring->prod_tail.\nA core can only update it if ring->prod_tail is equal to the prod_head local variable.\nThis is only true on core 1. The operation is finished on core 1.\n\n\n.. _figure_ring-mp-enqueue4:\n\n.. figure:: img/ring-mp-enqueue4.*\n\n Multiple consumer enqueue fourth step\n\n\nMultiple Consumer Enqueue Last Step\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nOnce ring->prod_tail is updated by core 1, core 2 is allowed to update it too.\nThe operation is also finished on core 2.\n\n\n.. _figure_ring-mp-enqueue5:\n\n.. figure:: img/ring-mp-enqueue5.*\n\n Multiple consumer enqueue last step\n\n\nModulo 32-bit Indexes\n~~~~~~~~~~~~~~~~~~~~~\n\nIn the preceding figures, the prod_head, prod_tail, cons_head and cons_tail indexes are represented by arrows.\nIn the actual implementation, these values are not between 0 and size(ring)-1 as would be assumed.\nThe indexes are between 0 and 2^32 -1, and we mask their value when we access the pointer table (the ring itself).\n32-bit modulo also implies that operations on indexes (such as, add/subtract) will automatically do 2^32 modulo\nif the result overflows the 32-bit number range.\n\nThe following are two examples that help to explain how indexes are used in a ring.\n\n.. note::\n\n To simplify the explanation, operations with modulo 16-bit are used instead of modulo 32-bit.\n In addition, the four indexes are defined as unsigned 16-bit integers,\n as opposed to unsigned 32-bit integers in the more realistic case.\n\n\n.. _figure_ring-modulo1:\n\n.. figure:: img/ring-modulo1.*\n\n Modulo 32-bit indexes - Example 1\n\n\nThis ring contains 11000 entries.\n\n\n.. _figure_ring-modulo2:\n\n.. figure:: img/ring-modulo2.*\n\n Modulo 32-bit indexes - Example 2\n\n\nThis ring contains 12536 entries.\n\n.. note::\n\n For ease of understanding, we use modulo 65536 operations in the above examples.\n In real execution cases, this is redundant for low efficiency, but is done automatically when the result overflows.\n\nThe code always maintains a distance between producer and consumer between 0 and size(ring)-1.\nThanks to this property, we can do subtractions between 2 index values in a modulo-32bit base:\nthat's why the overflow of the indexes is not a problem.\n\nAt any time, entries and free_entries are between 0 and size(ring)-1,\neven if only the first term of subtraction has overflowed:\n\n.. code-block:: c\n\n uint32_t entries = (prod_tail - cons_head);\n uint32_t free_entries = (mask + cons_tail -prod_head);\n\nReferences\n----------\n\n * `bufring.h in FreeBSD `_ (version 8)\n\n * `bufring.c in FreeBSD `_ (version 8)\n\n * `Linux Lockless Ring Buffer Design `_\n" }, { "path": "doc/guides/prog_guide/source_org.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n**Part 2: Development Environment**\n\nSource Organization\n===================\n\nThis section describes the organization of sources in the DPDK framework.\n\nMakefiles and Config\n--------------------\n\n.. note::\n\n In the following descriptions,\n ``RTE_SDK`` is the environment variable that points to the base directory into which the tarball was extracted.\n See\n :ref:`Useful_Variables_Provided_by_the_Build_System`\n for descriptions of other variables.\n\nMakefiles that are provided by the DPDK libraries and applications are located in ``$(RTE_SDK)/mk``.\n\nConfig templates are located in ``$(RTE_SDK)/config``. The templates describe the options that are enabled for each target.\nThe config file also contains items that can be enabled and disabled for many of the DPDK libraries,\nincluding debug options.\nThe user should look at the config file and become familiar with these options.\nThe config file is also used to create a header file, which will be located in the new build directory.\n\nLibraries\n---------\n\nLibraries are located in subdirectories of ``$(RTE_SDK)/lib``.\nBy convention a library refers to any code that provides an API to an application.\nTypically, it generates an archive file (``.a``), but a kernel module would also go in the same directory.\n\nThe lib directory contains::\n\n lib\n +-- librte_cmdline # Command line interface helper\n +-- librte_distributor # Packet distributor\n +-- librte_eal # Environment abstraction layer\n +-- librte_ether # Generic interface to poll mode driver\n +-- librte_hash # Hash library\n +-- librte_ip_frag # IP fragmentation library\n +-- librte_ivshmem # QEMU IVSHMEM library\n +-- librte_kni # Kernel NIC interface\n +-- librte_kvargs # Argument parsing library\n +-- librte_lpm # Longest prefix match library\n +-- librte_malloc # Malloc-like functions\n +-- librte_mbuf # Packet and control mbuf manipulation\n +-- librte_mempool # Memory pool manager (fixed sized objects)\n +-- librte_meter # QoS metering library\n +-- librte_net # Various IP-related headers\n +-- librte_power # Power management library\n +-- librte_ring # Software rings (act as lockless FIFOs)\n +-- librte_sched # QoS scheduler and dropper library\n +-- librte_timer # Timer library\n\nDrivers\n-------\n\nDrivers are special libraries which provide poll-mode driver implementations for\ndevices: either hardware devices or pseudo/virtual devices. They are contained\nin the *drivers* subdirectory, classified by type, and each compiles to a\nlibrary with the format ``librte_pmd_X.a`` where ``X`` is the driver name.\n\nThe drivers directory has a *net* subdirectory which contains::\n\n drivers/net\n +-- af_packet # Poll mode driver based on Linux af_packet\n +-- bonding # Bonding poll mode driver\n +-- cxgbe # Chelsio Terminator 10GbE/40GbE poll mode driver\n +-- e1000 # 1GbE poll mode drivers (igb and em)\n +-- enic # Cisco VIC Ethernet NIC Poll-mode Driver\n +-- fm10k # Host interface PMD driver for FM10000 Series\n +-- i40e # 40GbE poll mode driver\n +-- ixgbe # 10GbE poll mode driver\n +-- mlx4 # Mellanox ConnectX-3 poll mode driver\n +-- null # NULL poll mode driver for testing\n +-- pcap # PCAP poll mode driver\n +-- ring # Ring poll mode driver\n +-- virtio # Virtio poll mode driver\n +-- vmxnet3 # VMXNET3 poll mode driver\n +-- xenvirt # Xen virtio poll mode driver\n\n.. note::\n\n Several of the ``driver/net`` directories contain a ``base``\n sub-directory. The ``base`` directory generally contains code the shouldn't\n be modified directly by the user. Any enhancements should be done via the\n ``X_osdep.c`` and/or ``X_osdep.h`` files in that directory. Refer to the\n local README in the base directories for driver specific instructions.\n\n\nApplications\n------------\n\nApplications are source files that contain a ``main()`` function.\nThey are located in the ``$(RTE_SDK)/app`` and ``$(RTE_SDK)/examples`` directories.\n\nThe app directory contains sample applications that are used to test DPDK (such as autotests)\nor the Poll Mode Drivers (test-pmd)::\n\n app\n +-- chkincs # Test program to check include dependencies\n +-- cmdline_test # Test the commandline library\n +-- test # Autotests to validate DPDK features\n +-- test-acl # Test the ACL library\n +-- test-pipeline # Test the IP Pipeline framework\n +-- test-pmd # Test and benchmark poll mode drivers\n\nThe examples directory contains sample applications that show how libraries can be used::\n\n examples\n +-- cmdline # Example of using the cmdline library\n +-- dpdk_qat # Sample integration with Intel QuickAssist\n +-- exception_path # Sending packets to and from Linux TAP device\n +-- helloworld # Basic Hello World example\n +-- ip_reassembly # Example showing IP reassembly\n +-- ip_fragmentation # Example showing IPv4 fragmentation\n +-- ipv4_multicast # Example showing IPv4 multicast\n +-- kni # Kernel NIC Interface (KNI) example\n +-- l2fwd # L2 forwarding with and without SR-IOV\n +-- l3fwd # L3 forwarding example\n +-- l3fwd-power # L3 forwarding example with power management\n +-- l3fwd-vf # L3 forwarding example with SR-IOV\n +-- link_status_interrupt # Link status change interrupt example\n +-- load_balancer # Load balancing across multiple cores/sockets\n +-- multi_process # Example apps using multiple DPDK processes\n +-- qos_meter # QoS metering example\n +-- qos_sched # QoS scheduler and dropper example\n +-- timer # Example of using librte_timer library\n +-- vmdq_dcb # Example of VMDQ and DCB receiving\n +-- vmdq # Example of VMDQ receiving\n +-- vhost # Example of userspace vhost and switch\n\n.. note::\n\n The actual examples directory may contain additional sample applications to those shown above.\n Check the latest DPDK source files for details.\n" }, { "path": "doc/guides/prog_guide/thread_safety_intel_dpdk_functions.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nThread Safety of DPDK Functions\n===============================\n\nThe DPDK is comprised of several libraries.\nSome of the functions in these libraries can be safely called from multiple threads simultaneously, while others cannot.\nThis section allows the developer to take these issues into account when building their own application.\n\nThe run-time environment of the DPDK is typically a single thread per logical core.\nIn some cases, it is not only multi-threaded, but multi-process.\nTypically, it is best to avoid sharing data structures between threads and/or processes where possible.\nWhere this is not possible, then the execution blocks must access the data in a thread- safe manner.\nMechanisms such as atomics or locking can be used that will allow execution blocks to operate serially.\nHowever, this can have an effect on the performance of the application.\n\nFast-Path APIs\n--------------\n\nApplications operating in the data plane are performance sensitive but\ncertain functions within those libraries may not be safe to call from multiple threads simultaneously.\nThe hash, LPM and mempool libraries and RX/TX in the PMD are examples of this.\n\nThe hash and LPM libraries are, by design, thread unsafe in order to maintain performance.\nHowever, if required the developer can add layers on top of these libraries to provide thread safety.\nLocking is not needed in all situations, and in both the hash and LPM libraries,\nlookups of values can be performed in parallel in multiple threads.\nAdding, removing or modifying values, however,\ncannot be done in multiple threads without using locking when a single hash or LPM table is accessed.\nAnother alternative to locking would be to create multiple instances of these tables allowing each thread its own copy.\n\nThe RX and TX of the PMD are the most critical aspects of a DPDK application\nand it is recommended that no locking be used as it will impact performance.\nNote, however, that these functions can safely be used from multiple threads\nwhen each thread is performing I/O on a different NIC queue.\nIf multiple threads are to use the same hardware queue on the same NIC port,\nthen locking, or some other form of mutual exclusion, is necessary.\n\nThe ring library is based on a lockless ring-buffer algorithm that maintains its original design for thread safety.\nMoreover, it provides high performance for either multi- or single-consumer/producer enqueue/dequeue operations.\nThe mempool library is based on the DPDK lockless ring library and therefore is also multi-thread safe.\n\nPerformance Insensitive API\n---------------------------\n\nOutside of the performance sensitive areas described in Section 25.1,\nthe DPDK provides a thread-safe API for most other libraries.\nFor example, malloc(librte_malloc) and memzone functions are safe for use in multi-threaded and multi-process environments.\n\nThe setup and configuration of the PMD is not performance sensitive, but is not thread safe either.\nIt is possible that the multiple read/writes during PMD setup and configuration could be corrupted in a multi-thread environment.\nSince this is not performance sensitive, the developer can choose to add their own layer to provide thread-safe setup and configuration.\nIt is expected that, in most applications, the initial configuration of the network ports would be done by a single thread at startup.\n\nLibrary Initialization\n----------------------\n\nIt is recommended that DPDK libraries are initialized in the main thread at application startup\nrather than subsequently in the forwarding threads.\nHowever, the DPDK performs checks to ensure that libraries are only initialized once.\nIf initialization is attempted more than once, an error is returned.\n\nIn the multi-process case, the configuration information of shared memory will only be initialized by the master process.\nThereafter, both master and secondary processes can allocate/release any objects of memory that finally rely on rte_malloc or memzones.\n\nInterrupt Thread\n----------------\n\nThe DPDK works almost entirely in Linux user space in polling mode.\nFor certain infrequent operations, such as receiving a PMD link status change notification,\ncallbacks may be called in an additional thread outside the main DPDK processing threads.\nThese function callbacks should avoid manipulating DPDK objects that are also managed by the normal DPDK threads,\nand if they need to do so,\nit is up to the application to provide the appropriate locking or mutual exclusion restrictions around those objects.\n" }, { "path": "doc/guides/prog_guide/timer_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _Timer_Library:\n\nTimer Library\n=============\n\nThe Timer library provides a timer service to DPDK execution units to enable execution of callback functions asynchronously.\nFeatures of the library are:\n\n* Timers can be periodic (multi-shot) or single (one-shot).\n\n* Timers can be loaded from one core and executed on another. It has to be specified in the call to rte_timer_reset().\n\n* Timers provide high precision (depends on the call frequency to rte_timer_manage() that checks timer expiration for the local core).\n\n* If not required in the application, timers can be disabled at compilation time by not calling the rte_timer_manage() to increase performance.\n\nThe timer library uses the rte_get_timer_cycles() function that uses the High Precision Event Timer (HPET)\nor the CPUs Time Stamp Counter (TSC) to provide a reliable time reference.\n\nThis library provides an interface to add, delete and restart a timer. The API is based on BSD callout() with a few differences.\nRefer to the `callout manual `_.\n\nImplementation Details\n----------------------\n\nTimers are tracked on a per-lcore basis,\nwith all pending timers for a core being maintained in order of timer expiry in a skiplist data structure.\nThe skiplist used has ten levels and each entry in the table appears in each level with probability ¼^level.\nThis means that all entries are present in level 0, 1 in every 4 entries is present at level 1,\none in every 16 at level 2 and so on up to level 9.\nThis means that adding and removing entries from the timer list for a core can be done in log(n) time,\nup to 4^10 entries, that is, approximately 1,000,000 timers per lcore.\n\nA timer structure contains a special field called status,\nwhich is a union of a timer state (stopped, pending, running, config) and an owner (lcore id).\nDepending on the timer state, we know if a timer is present in a list or not:\n\n* STOPPED: no owner, not in a list\n\n* CONFIG: owned by a core, must not be modified by another core, maybe in a list or not, depending on previous state\n\n* PENDING: owned by a core, present in a list\n\n* RUNNING: owned by a core, must not be modified by another core, present in a list\n\nResetting or stopping a timer while it is in a CONFIG or RUNNING state is not allowed.\nWhen modifying the state of a timer,\na Compare And Swap instruction should be used to guarantee that the status (state+owner) is modified atomically.\n\nInside the rte_timer_manage() function,\nthe skiplist is used as a regular list by iterating along the level 0 list, which contains all timer entries,\nuntil an entry which has not yet expired has been encountered.\nTo improve performance in the case where there are entries in the timer list but none of those timers have yet expired,\nthe expiry time of the first list entry is maintained within the per-core timer list structure itself.\nOn 64-bit platforms, this value can be checked without the need to take a lock on the overall structure.\n(Since expiry times are maintained as 64-bit values,\na check on the value cannot be done on 32-bit platforms without using either a compare-and-swap (CAS) instruction or using a lock,\nso this additional check is skipped in favor of checking as normal once the lock has been taken.)\nOn both 64-bit and 32-bit platforms,\na call to rte_timer_manage() returns without taking a lock in the case where the timer list for the calling core is empty.\n\nUse Cases\n---------\n\nThe timer library is used for periodic calls, such as garbage collectors, or some state machines (ARP, bridging, and so on).\n\nReferences\n----------\n\n* `callout manual `_\n - The callout facility that provides timers with a mechanism to execute a function at a given time.\n\n* `HPET `_\n - Information about the High Precision Event Timer (HPET).\n" }, { "path": "doc/guides/prog_guide/vhost_lib.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nVhost Library\n=============\n\nThe vhost library implements a user space vhost driver. It supports both vhost-cuse\n(cuse: user space character device) and vhost-user(user space socket server).\nIt also creates, manages and destroys vhost devices for corresponding virtio\ndevices in the guest. Vhost supported vSwitch could register callbacks to this\nlibrary, which will be called when a vhost device is activated or deactivated\nby guest virtual machine.\n\nVhost API Overview\n------------------\n\n* Vhost driver registration\n\n rte_vhost_driver_register registers the vhost driver into the system.\n For vhost-cuse, character device file will be created under the /dev directory.\n Character device name is specified as the parameter.\n For vhost-user, a Unix domain socket server will be created with the parameter as\n the local socket path.\n\n* Vhost session start\n\n rte_vhost_driver_session_start starts the vhost session loop.\n Vhost session is an infinite blocking loop.\n Put the session in a dedicate DPDK thread.\n\n* Callback register\n\n Vhost supported vSwitch could call rte_vhost_driver_callback_register to\n register two callbacks, new_destory and destroy_device.\n When virtio device is activated or deactivated by guest virtual machine,\n the callback will be called, then vSwitch could put the device onto data\n core or remove the device from data core by setting or unsetting\n VIRTIO_DEV_RUNNING on the device flags.\n\n* Read/write packets from/to guest virtual machine\n\n rte_vhost_enqueue_burst transmit host packets to guest.\n rte_vhost_dequeue_burst receives packets from guest.\n\n* Feature enable/disable\n\n Now one negotiate-able feature in vhost is merge-able.\n vSwitch could enable/disable this feature for performance consideration.\n\nVhost Implementation\n--------------------\n\nVhost cuse implementation\n~~~~~~~~~~~~~~~~~~~~~~~~~\nWhen vSwitch registers the vhost driver, it will register a cuse device driver\ninto the system and creates a character device file. This cuse driver will\nreceive vhost open/release/IOCTL message from QEMU simulator.\n\nWhen the open call is received, vhost driver will create a vhost device for the\nvirtio device in the guest.\n\nWhen VHOST_SET_MEM_TABLE IOCTL is received, vhost searches the memory region\nto find the starting user space virtual address that maps the memory of guest\nvirtual machine. Through this virtual address and the QEMU pid, vhost could\nfind the file QEMU uses to map the guest memory. Vhost maps this file into its\naddress space, in this way vhost could fully access the guest physical memory,\nwhich means vhost could access the shared virtio ring and the guest physical\naddress specified in the entry of the ring.\n\nThe guest virtual machine tells the vhost whether the virtio device is ready\nfor processing or is de-activated through VHOST_NET_SET_BACKEND message.\nThe registered callback from vSwitch will be called.\n\nWhen the release call is released, vhost will destroy the device.\n\nVhost user implementation\n~~~~~~~~~~~~~~~~~~~~~~~~~\nWhen vSwitch registers a vhost driver, it will create a Unix domain socket server\ninto the system. This server will listen for a connection and process the vhost message from\nQEMU simulator.\n\nWhen there is a new socket connection, it means a new virtio device has been created in\nthe guest virtual machine, and the vhost driver will create a vhost device for this virtio device.\n\nFor messages with a file descriptor, the file descriptor could be directly used in the vhost\nprocess as it is already installed by Unix domain socket.\n\n * VHOST_SET_MEM_TABLE\n * VHOST_SET_VRING_KICK\n * VHOST_SET_VRING_CALL\n * VHOST_SET_LOG_FD\n * VHOST_SET_VRING_ERR\n\nFor VHOST_SET_MEM_TABLE message, QEMU will send us information for each memory region and its\nfile descriptor in the ancillary data of the message. The fd is used to map that region.\n\nThere is no VHOST_NET_SET_BACKEND message as in vhost cuse to signal us whether virtio device\nis ready or should be stopped.\nVHOST_SET_VRING_KICK is used as the signal to put the vhost device onto data plane.\nVHOST_GET_VRING_BASE is used as the signal to remove vhost device from data plane.\n\nWhen the socket connection is closed, vhost will destroy the device.\n\nVhost supported vSwitch reference\n---------------------------------\n\nFor more vhost details and how to support vhost in vSwitch, please refer to vhost example in the\nDPDK Sample Applications Guide.\n" }, { "path": "doc/guides/prog_guide/writing_efficient_code.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nWriting Efficient Code\n======================\n\nThis chapter provides some tips for developing efficient code using the DPDK.\nFor additional and more general information,\nplease refer to the *Intel® 64 and IA-32 Architectures Optimization Reference Manual*\nwhich is a valuable reference to writing efficient code.\n\nMemory\n------\n\nThis section describes some key memory considerations when developing applications in the DPDK environment.\n\nMemory Copy: Do not Use libc in the Data Plane\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nMany libc functions are available in the DPDK, via the Linux* application environment.\nThis can ease the porting of applications and the development of the configuration plane.\nHowever, many of these functions are not designed for performance.\nFunctions such as memcpy() or strcpy() should not be used in the data plane.\nTo copy small structures, the preference is for a simpler technique that can be optimized by the compiler.\nRefer to the *VTune™ Performance Analyzer Essentials* publication from Intel Press for recommendations.\n\nFor specific functions that are called often,\nit is also a good idea to provide a self-made optimized function, which should be declared as static inline.\n\nThe DPDK API provides an optimized rte_memcpy() function.\n\nMemory Allocation\n~~~~~~~~~~~~~~~~~\n\nOther functions of libc, such as malloc(), provide a flexible way to allocate and free memory.\nIn some cases, using dynamic allocation is necessary,\nbut it is really not advised to use malloc-like functions in the data plane because\nmanaging a fragmented heap can be costly and the allocator may not be optimized for parallel allocation.\n\nIf you really need dynamic allocation in the data plane, it is better to use a memory pool of fixed-size objects.\nThis API is provided by librte_mempool.\nThis data structure provides several services that increase performance, such as memory alignment of objects,\nlockless access to objects, NUMA awareness, bulk get/put and per-lcore cache.\nThe rte_malloc () function uses a similar concept to mempools.\n\nConcurrent Access to the Same Memory Area\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nRead-Write (RW) access operations by several lcores to the same memory area can generate a lot of data cache misses,\nwhich are very costly.\nIt is often possible to use per-lcore variables, for example, in the case of statistics.\nThere are at least two solutions for this:\n\n* Use RTE_PER_LCORE variables. Note that in this case, data on lcore X is not available to lcore Y.\n\n* Use a table of structures (one per lcore). In this case, each structure must be cache-aligned.\n\nRead-mostly variables can be shared among lcores without performance losses if there are no RW variables in the same cache line.\n\nNUMA\n~~~~\n\nOn a NUMA system, it is preferable to access local memory since remote memory access is slower.\nIn the DPDK, the memzone, ring, rte_malloc and mempool APIs provide a way to create a pool on a specific socket.\n\nSometimes, it can be a good idea to duplicate data to optimize speed.\nFor read-mostly variables that are often accessed,\nit should not be a problem to keep them in one socket only, since data will be present in cache.\n\nDistribution Across Memory Channels\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nModern memory controllers have several memory channels that can load or store data in parallel.\nDepending on the memory controller and its configuration,\nthe number of channels and the way the memory is distributed across the channels varies.\nEach channel has a bandwidth limit,\nmeaning that if all memory access operations are done on the first channel only, there is a potential bottleneck.\n\nBy default, the :ref:`Mempool Library ` spreads the addresses of objects among memory channels.\n\nCommunication Between lcores\n----------------------------\n\nTo provide a message-based communication between lcores,\nit is advised to use the DPDK ring API, which provides a lockless ring implementation.\n\nThe ring supports bulk and burst access,\nmeaning that it is possible to read several elements from the ring with only one costly atomic operation\n(see Chapter 5 \"Ring Library\").\nPerformance is greatly improved when using bulk access operations.\n\nThe code algorithm that dequeues messages may be something similar to the following:\n\n.. code-block:: c\n\n #define MAX_BULK 32\n\n while (1) {\n /* Process as many elements as can be dequeued. */\n count = rte_ring_dequeue_burst(ring, obj_table, MAX_BULK);\n if (unlikely(count == 0))\n continue;\n\n my_process_bulk(obj_table, count);\n }\n\nPMD Driver\n----------\n\nThe DPDK Poll Mode Driver (PMD) is also able to work in bulk/burst mode,\nallowing the factorization of some code for each call in the send or receive function.\n\nAvoid partial writes.\nWhen PCI devices write to system memory through DMA,\nit costs less if the write operation is on a full cache line as opposed to part of it.\nIn the PMD code, actions have been taken to avoid partial writes as much as possible.\n\nLower Packet Latency\n~~~~~~~~~~~~~~~~~~~~\n\nTraditionally, there is a trade-off between throughput and latency.\nAn application can be tuned to achieve a high throughput,\nbut the end-to-end latency of an average packet will typically increase as a result.\nSimilarly, the application can be tuned to have, on average,\na low end-to-end latency, at the cost of lower throughput.\n\nIn order to achieve higher throughput,\nthe DPDK attempts to aggregate the cost of processing each packet individually by processing packets in bursts.\n\nUsing the testpmd application as an example,\nthe burst size can be set on the command line to a value of 16 (also the default value).\nThis allows the application to request 16 packets at a time from the PMD.\nThe testpmd application then immediately attempts to transmit all the packets that were received,\nin this case, all 16 packets.\n\nThe packets are not transmitted until the tail pointer is updated on the corresponding TX queue of the network port.\nThis behavior is desirable when tuning for high throughput because\nthe cost of tail pointer updates to both the RX and TX queues can be spread across 16 packets,\neffectively hiding the relatively slow MMIO cost of writing to the PCIe* device.\nHowever, this is not very desirable when tuning for low latency because\nthe first packet that was received must also wait for another 15 packets to be received.\nIt cannot be transmitted until the other 15 packets have also been processed because\nthe NIC will not know to transmit the packets until the TX tail pointer has been updated,\nwhich is not done until all 16 packets have been processed for transmission.\n\nTo consistently achieve low latency, even under heavy system load,\nthe application developer should avoid processing packets in bunches.\nThe testpmd application can be configured from the command line to use a burst value of 1.\nThis will allow a single packet to be processed at a time, providing lower latency,\nbut with the added cost of lower throughput.\n\nLocks and Atomic Operations\n---------------------------\n\nAtomic operations imply a lock prefix before the instruction,\ncausing the processor's LOCK# signal to be asserted during execution of the following instruction.\nThis has a big impact on performance in a multicore environment.\n\nPerformance can be improved by avoiding lock mechanisms in the data plane.\nIt can often be replaced by other solutions like per-lcore variables.\nAlso, some locking techniques are more efficient than others.\nFor instance, the Read-Copy-Update (RCU) algorithm can frequently replace simple rwlocks.\n\nCoding Considerations\n---------------------\n\nInline Functions\n~~~~~~~~~~~~~~~~\n\nSmall functions can be declared as static inline in the header file.\nThis avoids the cost of a call instruction (and the associated context saving).\nHowever, this technique is not always efficient; it depends on many factors including the compiler.\n\nBranch Prediction\n~~~~~~~~~~~~~~~~~\n\nThe Intel® C/C++ Compiler (icc)/gcc built-in helper functions likely() and unlikely()\nallow the developer to indicate if a code branch is likely to be taken or not.\nFor instance:\n\n.. code-block:: c\n\n if (likely(x > 1))\n do_stuff();\n\nSetting the Target CPU Type\n---------------------------\n\nThe DPDK supports CPU microarchitecture-specific optimizations by means of CONFIG_RTE_MACHINE option\nin the DPDK configuration file.\nThe degree of optimization depends on the compiler's ability to optimize for a specific microarchitecture,\ntherefore it is preferable to use the latest compiler versions whenever possible.\n\nIf the compiler version does not support the specific feature set (for example, the Intel® AVX instruction set),\nthe build process gracefully degrades to whatever latest feature set is supported by the compiler.\n\nSince the build and runtime targets may not be the same,\nthe resulting binary also contains a platform check that runs before the\nmain() function and checks if the current machine is suitable for running the binary.\n\nAlong with compiler optimizations,\na set of preprocessor defines are automatically added to the build process (regardless of the compiler version).\nThese defines correspond to the instruction sets that the target CPU should be able to support.\nFor example, a binary compiled for any SSE4.2-capable processor will have RTE_MACHINE_CPUFLAG_SSE4_2 defined,\nthus enabling compile-time code path selection for different platforms.\n" }, { "path": "doc/guides/rel_notes/deprecation.rst", "content": "ABI and API Deprecation\n=======================\n\nSee the :doc:`guidelines document for details of the ABI policy `.\nAPI and ABI deprecation notices are to be posted here.\n\n\nDeprecation Notices\n-------------------\n\n* Significant ABI changes are planned for struct rte_eth_dev to support up to\n 1024 queues per port. This change will be in release 2.2.\n There is no backward compatibility planned from release 2.2.\n All binaries will need to be rebuilt from release 2.2.\n\n* ABI changes are planned for struct rte_intr_handle, struct rte_eth_conf\n and struct eth_dev_ops to support interrupt mode feature from release 2.1.\n Those changes may be enabled in the release 2.1 with CONFIG_RTE_NEXT_ABI.\n\n* The EAL function rte_eal_pci_close_one is deprecated because renamed to\n rte_eal_pci_detach.\n\n* The Macros RTE_HASH_BUCKET_ENTRIES_MAX and RTE_HASH_KEY_LENGTH_MAX are\n deprecated and will be removed with version 2.2.\n\n* The function rte_jhash2 is deprecated and should be removed.\n\n* The field mem_location of the rte_lpm structure is deprecated and should be\n removed as well as the macros RTE_LPM_HEAP and RTE_LPM_MEMZONE.\n\n* Significant ABI changes are planned for struct rte_mbuf, struct rte_kni_mbuf,\n and several ``PKT_RX_`` flags will be removed, to support unified packet type\n from release 2.1. Those changes may be enabled in the upcoming release 2.1\n with CONFIG_RTE_NEXT_ABI.\n\n* librte_malloc library has been integrated into librte_eal. The 2.1 release\n creates a dummy/empty malloc library to fulfill binaries with dynamic linking\n dependencies on librte_malloc.so. Such dummy library will not be created from\n release 2.2 so binaries will need to be rebuilt.\n\n* The following fields have been deprecated in rte_eth_stats:\n imissed, ibadcrc, ibadlen, imcasts, fdirmatch, fdirmiss,\n tx_pause_xon, rx_pause_xon, tx_pause_xoff, rx_pause_xoff\n\n* API for flow director filters has been replaced by rte_eth_dev_filter_ctrl.\n Following old API is deprecated and will be removed with version 2.2 without\n backward compatibility.\n Functions: rte_eth_dev_fdir_*.\n Structures: rte_fdir_*, rte_eth_fdir.\n Enums: rte_l4type, rte_iptype.\n\n* ABI changes are planned for struct rte_eth_fdir_flow_ext in order to support\n flow director filtering in VF. The release 2.1 does not contain these ABI\n changes, but release 2.2 will, and no backwards compatibility is planned.\n\n* ABI change is planned to extend the SCTP flow's key input from release 2.1.\n The change may be enabled in the release 2.1 with CONFIG_RTE_NEXT_ABI.\n\n* ABI changes are planned for struct rte_eth_fdir_filter and\n rte_eth_fdir_masks in order to support new flow director modes,\n MAC VLAN and Cloud, on x550. The MAC VLAN mode means the MAC and\n VLAN are monitored. The Cloud mode is for VxLAN and NVGRE, and\n the tunnel type, TNI/VNI, inner MAC and inner VLAN are monitored.\n The release 2.2 will contain these changes without backwards compatibility.\n\n* librte_kni: Functions based on port id are deprecated for a long time and\n should be removed (rte_kni_create, rte_kni_get_port_id and rte_kni_info_get).\n\n* librte_pmd_ring: The deprecated functions rte_eth_ring_pair_create and\n rte_eth_ring_pair_attach should be removed.\n\n* ABI changes are planned for struct virtio_net in order to support vhost-user\n multiple queues feature.\n It should be integrated in release 2.2 without backward compatibility.\n\n* The scheduler hierarchy structure (rte_sched_port_hierarchy) will change to\n allow for a larger number of subport entries.\n The number of available traffic_classes and queues may also change.\n The mbuf structure element for sched hierarchy will also change from a single\n 32 bit to a 64 bit structure.\n\n* The scheduler statistics structure will change to allow keeping track of\n RED actions.\n\n* librte_acl: The structure rte_acl_ipv4vlan_rule is deprecated and should\n be removed as well as the associated functions rte_acl_ipv4vlan_add_rules\n and rte_acl_ipv4vlan_build.\n\n* librte_cfgfile: In order to allow for longer names and values,\n the value of macros CFG_NAME_LEN and CFG_NAME_VAL will be increased.\n Most likely, the new values will be 64 and 256, respectively.\n\n* librte_port: Macros to access the packet meta-data stored within the\n packet buffer will be adjusted to cover the packet mbuf structure as well,\n as currently they are able to access any packet buffer location except the\n packet mbuf structure.\n\n* librte_table LPM: A new parameter to hold the table name will be added to\n the LPM table parameter structure.\n\n* librte_table: New functions for table entry bulk add/delete will be added\n to the table operations structure.\n\n* librte_table hash: Key mask parameter will be added to the hash table\n parameter structure for 8-byte key and 16-byte key extendible bucket and\n LRU tables.\n\n* librte_pipeline: The prototype for the pipeline input port, output port\n and table action handlers will be updated:\n the pipeline parameter will be added, the packets mask parameter will be\n either removed (for input port action handler) or made input-only.\n" }, { "path": "doc/guides/rel_notes/index.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nDPDK Release Notes\n==================\n\n|today|\n\nContents\n\n.. toctree::\n :maxdepth: 1\n :numbered:\n\n rel_description\n release_2_1\n release_2_0\n release_1_8\n supported_os\n known_issues\n deprecation\n" }, { "path": "doc/guides/rel_notes/known_issues.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nKnown Issues and Limitations in Legacy Releases\n===============================================\n\nThis section describes known issues with the DPDK software that aren't covered in the version specific release\nnotes sections.\n\n\nUnit Test for Link Bonding may fail at test_tlb_tx_burst()\n----------------------------------------------------------\n\n**Description**:\n Unit tests will fail in ``test_tlb_tx_burst()`` function with error for uneven distribution of packets.\n\n**Implication**:\n Unit test link_bonding_autotest will fail.\n\n**Resolution/Workaround**:\n There is no workaround available.\n\n**Affected Environment/Platform**:\n Fedora 20.\n\n**Driver/Module**:\n Link Bonding.\n\n\nPause Frame Forwarding does not work properly on igb\n----------------------------------------------------\n\n**Description**:\n For igb devices rte_eth_flow_ctrl_set does not work as expected.\n Pause frames are always forwarded on igb, regardless of the ``RFCE``, ``MPMCF`` and ``DPF`` registers.\n\n**Implication**:\n Pause frames will never be rejected by the host on 1G NICs and they will always be forwarded.\n\n**Resolution/Workaround**:\n There is no workaround available.\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n Poll Mode Driver (PMD).\n\n\nIn packets provided by the PMD, some flags are missing\n------------------------------------------------------\n\n**Description**:\n In packets provided by the PMD, some flags are missing.\n The application does not have access to information provided by the hardware\n (packet is broadcast, packet is multicast, packet is IPv4 and so on).\n\n**Implication**:\n The ``ol_flags`` field in the ``rte_mbuf`` structure is not correct and should not be used.\n\n**Resolution/Workaround**:\n The application has to parse the Ethernet header itself to get the information, which is slower.\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n Poll Mode Driver (PMD).\n\nThe rte_malloc library is not fully implemented\n-----------------------------------------------\n\n**Description**:\n The ``rte_malloc`` library is not fully implemented.\n\n**Implication**:\n All debugging features of rte_malloc library described in architecture documentation are not yet implemented.\n\n**Resolution/Workaround**:\n No workaround available.\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n ``rte_malloc``.\n\n\nHPET reading is slow\n--------------------\n\n**Description**:\n Reading the HPET chip is slow.\n\n**Implication**:\n An application that calls ``rte_get_hpet_cycles()`` or ``rte_timer_manage()`` runs slower.\n\n**Resolution/Workaround**:\n The application should not call these functions too often in the main loop.\n An alternative is to use the TSC register through ``rte_rdtsc()`` which is faster,\n but specific to an lcore and is a cycle reference, not a time reference.\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n Environment Abstraction Layer (EAL).\n\n\nHPET timers do not work on the Osage customer reference platform\n----------------------------------------------------------------\n\n**Description**:\n HPET timers do not work on the Osage customer reference platform which includes an Intel® Xeon® processor 5500\n series processor) using the released BIOS from Intel.\n\n**Implication**:\n On Osage boards, the implementation of the ``rte_delay_us()`` function must be changed to not use the HPET timer.\n\n**Resolution/Workaround**:\n This can be addressed by building the system with the ``CONFIG_RTE_LIBEAL_USE_HPET=n``\n configuration option or by using the ``--no-hpet`` EAL option.\n\n**Affected Environment/Platform**:\n The Osage customer reference platform.\n Other vendor platforms with Intel® Xeon® processor 5500 series processors should\n work correctly, provided the BIOS supports HPET.\n\n**Driver/Module**:\n ``lib/librte_eal/common/include/rte_cycles.h``\n\n\nNot all variants of supported NIC types have been used in testing\n-----------------------------------------------------------------\n\n**Description**:\n The supported network interface cards can come in a number of variants with different device ID's.\n Not all of these variants have been tested with the Intel® DPDK.\n\n The NIC device identifiers used during testing:\n\n * Intel® Ethernet Controller XL710 for 40GbE QSFP+ [8086:1584]\n * Intel® Ethernet Controller XL710 for 40GbE QSFP+ [8086:1583]\n * Intel® Ethernet Controller X710 for 10GbE SFP+ [8086:1572]\n * Intel® 82576 Gigabit Ethernet Controller [8086:10c9]\n * Intel® 82576 Quad Copper Gigabit Ethernet Controller [8086:10e8]\n * Intel® 82580 Dual Copper Gigabit Ethernet Controller [8086:150e]\n * Intel® I350 Quad Copper Gigabit Ethernet Controller [8086:1521]\n * Intel® 82599 Dual Fibre 10 Gigabit Ethernet Controller [8086:10fb]\n * Intel® Ethernet Server Adapter X520-T2 [8086: 151c]\n * Intel® Ethernet Controller X540-T2 [8086:1528]\n * Intel® 82574L Gigabit Network Connection [8086:10d3]\n * Emulated Intel® 82540EM Gigabit Ethernet Controller [8086:100e]\n * Emulated Intel® 82545EM Gigabit Ethernet Controller [8086:100f]\n * Intel® Ethernet Server Adapter X520-4 [8086:154a]\n * Intel® Ethernet Controller I210 [8086:1533]\n\n**Implication**:\n Risk of issues with untested variants.\n\n**Resolution/Workaround**:\n Use tested NIC variants. For those supported Ethernet controllers, additional device\n IDs may be added to the software if required.\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n Poll-mode drivers\n\n\nMulti-process sample app requires exact memory mapping\n------------------------------------------------------\n\n**Description**:\n The multi-process example application assumes that\n it is possible to map the hugepage memory to the same virtual addresses in client and server applications.\n Occasionally, very rarely with 64-bit, this does not occur and a client application will fail on startup.\n The Linux \"address-space layout randomization\" security feature can sometimes cause this to occur.\n\n**Implication**:\n A multi-process client application fails to initialize.\n\n**Resolution/Workaround**:\n See the \"Multi-process Limitations\" section in the Intel® DPDK Programmer's Guide for more information.\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n Multi-process example application\n\n\nPackets are not sent by the 1 GbE/10 GbE SR-IOV driver when the source MAC is not the MAC assigned to the VF NIC\n----------------------------------------------------------------------------------------------------------------\n\n**Description**:\n The 1 GbE/10 GbE SR-IOV driver can only send packets when the Ethernet header's source MAC address is the same as\n that of the VF NIC.\n The reason for this is that the Linux ``ixgbe`` driver module in the host OS has its anti-spoofing feature enabled.\n\n**Implication**:\n Packets sent using the 1 GbE/10 GbE SR-IOV driver must have the source MAC address correctly set to that of the VF NIC.\n Packets with other source address values are dropped by the NIC if the application attempts to transmit them.\n\n**Resolution/Workaround**:\n Configure the Ethernet source address in each packet to match that of the VF NIC.\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n 1 GbE/10 GbE VF Poll Mode Driver (PMD).\n\n\nSR-IOV drivers do not fully implement the rte_ethdev API\n--------------------------------------------------------\n\n**Description**:\n The SR-IOV drivers only supports the following rte_ethdev API functions:\n\n * rte_eth_dev_configure()\n * rte_eth_tx_queue_setup()\n * rte_eth_rx_queue_setup()\n * rte_eth_dev_info_get()\n * rte_eth_dev_start()\n * rte_eth_tx_burst()\n * rte_eth_rx_burst()\n * rte_eth_dev_stop()\n * rte_eth_stats_get()\n * rte_eth_stats_reset()\n * rte_eth_link_get()\n * rte_eth_link_get_no_wait()\n\n**Implication**:\n Calling an unsupported function will result in an application error.\n\n**Resolution/Workaround**:\n Do not use other rte_ethdev API functions in applications that use the SR-IOV drivers.\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n VF Poll Mode Driver (PMD).\n\n\nPMD does not work with --no-huge EAL command line parameter\n-----------------------------------------------------------\n\n**Description**:\n Currently, the DPDK does not store any information about memory allocated by ``malloc()` (for example, NUMA node,\n physical address), hence PMD drivers do not work when the ``--no-huge`` command line parameter is supplied to EAL.\n\n**Implication**:\n Sending and receiving data with PMD will not work.\n\n**Resolution/Workaround**:\n Use huge page memory or use VFIO to map devices.\n\n**Affected Environment/Platform**:\n Systems running the DPDK on Linux\n\n**Driver/Module**:\n Poll Mode Driver (PMD).\n\n\nSome hardware off-load functions are not supported by the VF Driver\n-------------------------------------------------------------------\n\n**Description**:\n Currently, configuration of the following items is not supported by the VF driver:\n\n * IP/UDP/TCP checksum offload\n * Jumbo Frame Receipt\n * HW Strip CRC\n\n**Implication**:\n Any configuration for these items in the VF register will be ignored.\n The behavior is dependent on the current PF setting.\n\n**Resolution/Workaround**:\n For the PF (Physical Function) status on which the VF driver depends, there is an option item under PMD in the\n config file.\n For others, the VF will keep the same behavior as PF setting.\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n VF (SR-IOV) Poll Mode Driver (PMD).\n\n\nKernel crash on IGB port unbinding\n----------------------------------\n\n**Description**:\n Kernel crash may occur when unbinding 1G ports from the igb_uio driver, on 2.6.3x kernels such as shipped\n with Fedora 14.\n\n**Implication**:\n Kernel crash occurs.\n\n**Resolution/Workaround**:\n Use newer kernels or do not unbind ports.\n\n**Affected Environment/Platform**:\n 2.6.3x kernels such as shipped with Fedora 14\n\n**Driver/Module**:\n IGB Poll Mode Driver (PMD).\n\n\nTwinpond and Ironpond NICs do not report link status correctly\n--------------------------------------------------------------\n\n**Description**:\n Twin Pond/Iron Pond NICs do not bring the physical link down when shutting down the port.\n\n**Implication**:\n The link is reported as up even after issuing ``shutdown`` command unless the cable is physically disconnected.\n\n**Resolution/Workaround**:\n None.\n\n**Affected Environment/Platform**:\n Twin Pond and Iron Pond NICs\n\n**Driver/Module**:\n Poll Mode Driver (PMD).\n\n\nDiscrepancies between statistics reported by different NICs\n-----------------------------------------------------------\n\n**Description**:\n Gigabit Ethernet devices from Intel include CRC bytes when calculating packet reception statistics regardless\n of hardware CRC stripping state, while 10-Gigabit Ethernet devices from Intel do so only when hardware CRC\n stripping is disabled.\n\n**Implication**:\n There may be a discrepancy in how different NICs display packet reception statistics.\n\n**Resolution/Workaround**:\n None\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n Poll Mode Driver (PMD).\n\n\nError reported opening files on DPDK initialization\n---------------------------------------------------\n\n**Description**:\n On DPDK application startup, errors may be reported when opening files as part of the initialization process.\n This occurs if a large number, for example, 500 or more, or if hugepages are used, due to the per-process\n limit on the number of open files.\n\n**Implication**:\n The DPDK application may fail to run.\n\n**Resolution/Workaround**:\n If using 2 MB hugepages, consider switching to a fewer number of 1 GB pages.\n Alternatively, use the ``ulimit`` command to increase the number of files which can be opened by a process.\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n Environment Abstraction Layer (EAL).\n\n\nIntel® QuickAssist Technology sample application does not work on a 32-bit OS on Shumway\n----------------------------------------------------------------------------------------\n\n**Description**:\n The Intel® Communications Chipset 89xx Series device does not fully support NUMA on a 32-bit OS.\n Consequently, the sample application cannot work properly on Shumway, since it requires NUMA on both nodes.\n\n**Implication**:\n The sample application cannot work in 32-bit mode with emulated NUMA, on multi-socket boards.\n\n**Resolution/Workaround**:\n There is no workaround available.\n\n**Affected Environment/Platform**:\n Shumway\n\n**Driver/Module**:\n All.\n\n\nIEEE1588 support possibly not working with an Intel® Ethernet Controller I210 NIC\n---------------------------------------------------------------------------------\n\n**Description**:\n IEEE1588 support is not working with an Intel® Ethernet Controller I210 NIC.\n\n**Implication**:\n IEEE1588 packets are not forwarded correctly by the Intel® Ethernet Controller I210 NIC.\n\n**Resolution/Workaround**:\n There is no workaround available.\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n IGB Poll Mode Driver\n\n\nDifferences in how different Intel NICs handle maximum packet length for jumbo frame\n------------------------------------------------------------------------------------\n\n**Description**:\n 10 Gigabit Ethernet devices from Intel do not take VLAN tags into account when calculating packet size\n while Gigabit Ethernet devices do so for jumbo frames.\n\n**Implication**:\n When receiving packets with VLAN tags, the actual maximum size of useful payload that Intel Gigabit Ethernet\n devices are able to receive is 4 bytes (or 8 bytes in the case of packets with extended VLAN tags) less than\n that of Intel 10 Gigabit Ethernet devices.\n\n**Resolution/Workaround**:\n Increase the configured maximum packet size when using Intel Gigabit Ethernet devices.\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n Poll Mode Driver (PMD).\n\n\nBinding PCI devices to igb_uio fails on Linux kernel 3.9 when more than one device is used\n------------------------------------------------------------------------------------------\n\n**Description**:\n A known bug in the uio driver included in Linux kernel version 3.9 prevents more than one PCI device to be\n bound to the igb_uio driver.\n\n**Implication**:\n The Poll Mode Driver (PMD) will crash on initialization.\n\n**Resolution/Workaround**:\n Use earlier or later kernel versions, or apply the following\n `patch `_.\n\n**Affected Environment/Platform**:\n Linux systems with kernel version 3.9\n\n**Driver/Module**:\n igb_uio module\n\n\nGCC might generate Intel® AVX instructions for processors without Intel® AVX support\n------------------------------------------------------------------------------------\n\n**Description**:\n When compiling Intel® DPDK (and any DPDK app), gcc may generate Intel® AVX instructions, even when the\n processor does not support Intel® AVX.\n\n**Implication**:\n Any DPDK app might crash while starting up.\n\n**Resolution/Workaround**:\n Either compile using icc or set ``EXTRA_CFLAGS='-O3'`` prior to compilation.\n\n**Affected Environment/Platform**:\n Platforms which processor does not support Intel® AVX.\n\n**Driver/Module**:\n Environment Abstraction Layer (EAL).\n\nEthertype filter could receive other packets (non-assigned) in Niantic\n----------------------------------------------------------------------\n\n**Description**:\n On Intel® Ethernet Controller 82599EB When Ethertype filter (priority enable) was set, unmatched packets also\n could be received on the assigned queue, such as ARP packets without 802.1q tags or with the user priority not\n equal to set value.\n Launch the testpmd by disabling RSS and with multiply queues, then add the ethertype filter like the following\n and then start forwarding::\n\n add_ethertype_filter 0 ethertype 0x0806 priority enable 3 queue 2 index 1\n\n When sending ARP packets without 802.1q tag and with user priority as non-3 by tester, all the ARP packets can\n be received on the assigned queue.\n\n**Implication**:\n The user priority comparing in Ethertype filter cannot work probably.\n It is a NIC's issue due to the following: \"In fact, ETQF.UP is not functional, and the information will\n be added in errata of 82599 and X540.\"\n\n**Resolution/Workaround**:\n None\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n Poll Mode Driver (PMD).\n\n\nCannot set link speed on Intel® 40G Ethernet controller\n-------------------------------------------------------\n\n**Description**:\n On Intel® 40G Ethernet Controller you cannot set the link to specific speed.\n\n**Implication**:\n The link speed cannot be changed forcibly, though it can be configured by application.\n\n**Resolution/Workaround**:\n None\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n Poll Mode Driver (PMD).\n\n\nStopping the port does not down the link on Intel® 40G Ethernet controller\n--------------------------------------------------------------------------\n\n**Description**:\n On Intel® 40G Ethernet Controller stopping the port does not really down the port link.\n\n**Implication**:\n The port link will be still up after stopping the port.\n\n**Resolution/Workaround**:\n None\n\n**Affected Environment/Platform**:\n All.\n\n**Driver/Module**:\n Poll Mode Driver (PMD).\n\n\nDevices bound to igb_uio with VT-d enabled do not work on Linux kernel 3.15-3.17\n--------------------------------------------------------------------------------\n\n**Description**:\n When VT-d is enabled (``iommu=pt intel_iommu=on``), devices are 1:1 mapped.\n In the Linux kernel unbinding devices from drivers removes that mapping which result in IOMMU errors.\n Introduced in Linux `kernel 3.15 commit\n `_,\n solved in Linux `kernel 3.18 commit\n `_.\n\n**Implication**:\n Devices will not be allowed to access memory, resulting in following kernel errors::\n\n dmar: DRHD: handling fault status reg 2\n dmar: DMAR:[DMA Read] Request device [02:00.0] fault addr a0c58000\n DMAR:[fault reason 02] Present bit in context entry is clear\n\n**Resolution/Workaround**:\n Use earlier or later kernel versions, or avoid driver binding on boot by blacklisting the driver modules.\n I.e., in the case of ``ixgbe``, we can pass the kernel command line option: ``modprobe.blacklist=ixgbe``.\n This way we do not need to unbind the device to bind it to igb_uio.\n\n**Affected Environment/Platform**:\n Linux systems with kernel versions 3.15 to 3.17.\n\n**Driver/Module**:\n ``igb_uio`` module.\n\n\nVM power manager may not work on systems with more than 64 cores\n----------------------------------------------------------------\n\n**Description**:\n When using VM power manager on a system with more than 64 cores, VM(s) should not use cores 64 or higher.\n\n**Implication**:\n VM power manager should not be used with VM(s) that are using cores 64 or above.\n\n**Resolution/Workaround**:\n Do not use cores 64 or above.\n\n**Affected Environment/Platform**:\n Platforms with more than 64 cores.\n\n**Driver/Module**:\n VM power manager application.\n" }, { "path": "doc/guides/rel_notes/rel_description.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nDescription of Release\n======================\n\nThis document contains the release notes for Data Plane Development Kit (DPDK)\nrelease version |release| and previous releases.\n\nIt lists new features, fixed bugs, API and ABI changes and known issues.\n\nFor instructions on compiling and running the release, see the :ref:`DPDK Getting Started Guide `.\n" }, { "path": "doc/guides/rel_notes/release_1_8.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nDPDK Release 1.8\n================\n\nNew Features\n------------\n\n* Link Bonding\n\n * Support for 802.3ad link aggregation (mode 4) and transmit load balancing (mode 5) to the link bonding library.\n\n * Support for registration of link status change callbacks with link bonding devices.\n\n * Support for slaves devices which do not support link status change interrupts in the link bonding library via a link status polling mechanism.\n\n* Poll Mode Driver - 40 GbE Controllers (librte_pmd_i40e)\n\n * Support for Flow Director\n\n * Support for ethertype filter\n\n * Support RSS in VF\n\n * Support configuring redirection table with different size from 1GbE and 10 GbE\n\n - 128/512 entries of 40GbE PF\n\n - 64 entries of 40GbE VF\n\n * Support configuring hash functions\n\n * Support for VXLAN packet on Intel® 40GbE Controllers\n\n* Packet Distributor Sample Application\n" }, { "path": "doc/guides/rel_notes/release_2_0.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nDPDK Release 2.0\n================\n\n\nNew Features\n------------\n\n* Poll-mode driver support for an early release of the PCIE host interface of the Intel(R) Ethernet Switch FM10000.\n\n * Basic Rx/Tx functions for PF/VF\n\n * Interrupt handling support for PF/VF\n\n * Per queue start/stop functions for PF/VF\n\n * Support Mailbox handling between PF/VF and PF/Switch Manager\n\n * Receive Side Scaling (RSS) for PF/VF\n\n * Scatter receive function for PF/VF\n\n * Reta update/query for PF/VF\n\n * VLAN filter set for PF\n\n * Link status query for PF/VF\n\n.. note:: The software is intended to run on pre-release hardware and may contain unknown or unresolved defects or\n issues related to functionality and performance.\n The poll mode driver is also pre-release and will be updated to a released version post hardware and base driver release.\n Should the official hardware release be made between DPDK releases an updated poll-mode driver will be made available.\n\n* Link Bonding\n\n * Support for adaptive load balancing (mode 6) to the link bonding library.\n\n * Support for registration of link status change callbacks with link bonding devices.\n\n * Support for slaves devices which do not support link status change interrupts in the link bonding library via a link status polling mechanism.\n\n* PCI Hotplug with NULL PMD sample application\n\n* ABI versioning\n\n* x32 ABI\n\n* Non-EAL Thread Support\n\n* Multi-pthread Support\n\n* Re-order Library\n\n* ACL for AVX2\n\n* Architecture Independent CRC Hash\n\n* uio_pci_generic Support\n\n* KNI Optimizations\n\n* Vhost-user support\n\n* Virtio (link, vlan, mac, port IO, perf)\n\n* IXGBE-VF RSS\n\n* RX/TX Callbacks\n\n* Unified Flow Types\n\n* Indirect Attached MBUF Flag\n\n* Use default port configuration in TestPMD\n\n* Tunnel offloading in TestPMD\n\n* Poll Mode Driver - 40 GbE Controllers (librte_pmd_i40e)\n\n * Support for Flow Director\n\n * Support for ethertype filter\n\n * Support RSS in VF\n\n * Support configuring redirection table with different size from 1GbE and 10 GbE\n\n - 128/512 entries of 40GbE PF\n\n - 64 entries of 40GbE VF\n\n * Support configuring hash functions\n\n * Support for VXLAN packet on Intel® 40GbE Controllers\n\n* Poll Mode Driver for Mellanox ConnectX-3 EN adapters (mlx4)\n\n.. note:: This PMD is only available for Linux and is disabled by default\n due to external dependencies (libibverbs and libmlx4). Please\n refer to the NIC drivers guide for more information.\n\n* Packet Distributor Sample Application\n\n* Job Stats library and Sample Application.\n\n* Enhanced Jenkins hash (jhash) library\n\n.. note:: The hash values returned by the new jhash library are different\n from the ones returned by the previous library.\n" }, { "path": "doc/guides/rel_notes/release_2_1.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nDPDK Release 2.1\n================\n\n\nNew Features\n------------\n\n* **Enabled cloning of indirect mbufs.**\n\n This feature removes a limitation of ``rte_pktmbuf_attach()`` which\n generated the warning: \"mbuf we're attaching to must be direct\".\n\n Now, when attaching to an indirect mbuf it is possible to:\n\n * Copy all relevant fields (address, length, offload, ...) as before.\n\n * Get the pointer to the mbuf that embeds the data buffer (direct mbuf),\n and increase the reference counter.\n\n When detaching the mbuf, we can now retrieve this direct mbuf as the\n pointer is determined from the buffer address.\n\n\n* **Extended packet type support.**\n\n In previous releases mbuf packet types were indicated by 6 bits in the\n ``ol_flags``. This was not enough for some supported NICs. For example i40e\n hardware can recognize more than 150 packet types. Not being able to\n identify these additional packet types limits access to hardware offload\n capabilities\n\n So an extended \"unified\" packet type was added to support all possible\n PMDs. The 16 bit packet_type in the mbuf structure was changed to 32 bits\n and used for this purpose.\n\n To avoid breaking ABI compatibility, the code changes for this feature are\n enclosed in a ``RTE_NEXT_ABI`` ifdef. This is enabled by default but can be\n turned off for ABI compatibility with DPDK R2.0.\n\n\n* **Reworked memzone to be allocated by malloc and also support freeing.**\n\n In the memory hierarchy, memsegs are groups of physically contiguous\n hugepages, memzones are slices of memsegs, and malloc slices memzones\n into smaller memory chunks.\n\n This feature modifies ``malloc()`` so it partitions memsegs instead of\n memzones. Now memzones allocate their memory from the malloc heap.\n\n Backward compatibility with API and ABI are maintained.\n\n This allow memzones, and any other structure based on memzones, for example\n mempools, to be freed. Currently only the API from freeing memzones is\n supported.\n\n\n* **Interrupt mode PMD.**\n\n This feature introduces a low-latency one-shot RX interrupt into DPDK. It\n also adds a polling and interrupt mode switch control example.\n\n DPDK userspace interrupt notification and handling mechanism is based on\n UIO/VFIO with the following limitations:\n\n * Per queue RX interrupt events are only allowed in VFIO which supports\n multiple MSI-X vectors.\n * In UIO, the RX interrupt shares the same vector with other\n interrupts. When the RX interrupt and LSC interrupt are both enabled, only\n the former is available.\n * RX interrupt is only implemented for the linuxapp target.\n * The feature is only currently enabled for tow PMDs: ixgbe and igb.\n\n\n* **Packet Framework enhancements.**\n\n Several enhancements were made to the Packet Framework:\n\n * A new configuration file syntax has been introduced for IP pipeline\n applications. Parsing of the configuration file is changed.\n * Implementation of the IP pipeline application is modified to make it more\n structured and user friendly.\n * Implementation of the command line interface (CLI) for each pipeline type\n has been moved to the separate compilation unit. Syntax of pipeline CLI\n commands has been changed.\n * Initialization of IP pipeline is modified to match the new parameters\n structure.\n * New implementation of pass-through pipeline, firewall pipeline, routing\n pipeline, and flow classification has been added.\n * Master pipeline with CLI interface has been added.\n * Added extended documentation of the IP Pipeline.\n\n\n* **Added API for IEEE1588 timestamping.**\n\n This feature adds an ethdev API to enable, disable and read IEEE1588/802.1AS\n PTP timestamps from devices that support it. The following functions were\n added:\n\n * ``rte_eth_timesync_enable()``\n * ``rte_eth_timesync_disable()``\n * ``rte_eth_timesync_read_rx_timestamp()``\n * ``rte_eth_timesync_read_tx_timestamp()``\n\n The \"ieee1588\" forwarding mode in testpmd was also refactored to demonstrate\n the new API.\n\n\n* **Added multicast address filtering.**\n\n Added multicast address filtering via a new ethdev function\n ``set_mc_addr_list()``.\n\n This overcomes a limitation in previous releases where the receipt of\n multicast packets on a given port could only be enabled by invoking the\n ``rte_eth_allmulticast_enable()`` function. This method did not work for VFs\n in SR-IOV architectures when the host PF driver does not allow these\n operation on VFs. In such cases, joined multicast addresses had to be added\n individually to the set of multicast addresses that are filtered by the [VF]\n port.\n\n\n* **Added Flow Director extensions.**\n\n Several Flow Director extensions were added such as:\n\n * Support for RSS and Flow Director hashes in vector RX.\n * Added Flow Director for L2 payload.\n\n\n* **Added RSS hash key size query per port.**\n\n This feature supports querying the RSS hash key size of each port. A new\n field ``hash_key_size`` has been added in the ``rte_eth_dev_info`` struct\n for storing hash key size in bytes.\n\n\n* **Added userspace ethtool support.**\n\n Added userspace ethtool support to provide a familiar interface for\n applications that manage devices via kernel-space ``ethtool_op`` and\n ``net_device_op``.\n\n The initial implementation focuses on operations that can be implemented\n through existing ``netdev`` APIs. More operations will be supported in later\n releases.\n\n\n* **Updated the ixgbe base driver.**\n\n The ixgbe base driver was updated with several changes including the\n following:\n\n * Added a new 82599 device id.\n * Added new X550 PHY ids.\n * Added SFP+ dual-speed support.\n * Added wait helper for X550 IOSF accesses.\n * Added X550em features.\n * Added X557 PHY LEDs support.\n * Commands for flow director.\n * Issue firmware command when resetting X550em.\n\n See the git log for full details of the ixgbe/base changes.\n\n\n* **Added additional hotplug support.**\n\n Port hotplug support was added to the following PMDs:\n\n * e1000/igb.\n * ixgbe.\n * i40e.\n * fm10k.\n * ring.\n * bonding.\n * virtio.\n\n Port hotplug support was added to BSD.\n\n\n* **Added ixgbe LRO support.**\n\n Added LRO support for x540 and 82599 devices.\n\n\n* **Added extended statistics for ixgbe.**\n\n Implemented ``xstats_get()`` and ``xstats_reset()`` in dev_ops for\n ixgbe to expose detailed error statistics to DPDK applications.\n\n These will be implemented for other PMDs in later releases.\n\n\n* **Added proc_info application.**\n\n Created a new ``proc_info`` application, by refactoring the existing\n ``dump_cfg`` application, to demonstrate the usage of retrieving statistics,\n and the new extended statistics (see above), for DPDK interfaces.\n\n\n* **Updated the i40e base driver.**\n\n The i40e base driver was updated with several changes including the\n following:\n\n * Support for building both PF and VF driver together.\n * Support for CEE DCBX on recent firmware versions.\n * Replacement of ``i40e_debug_read_register()``.\n * Rework of ``i40e_hmc_get_object_va``.\n * Update of shadow RAM read/write functions.\n * Enhancement of polling NVM semaphore.\n * Enhancements on adminq init and sending asq command.\n * Update of get/set LED functions.\n * Addition of AOC phy types to case statement in get_media_type.\n * Support for iSCSI capability.\n * Setting of FLAG_RD when sending driver version to FW.\n\n See the git log for full details of the i40e/base changes.\n\n\n* **Added support for port mirroring in i40e.**\n\n Enabled mirror functionality in the i40e driver.\n\n\n* **Added support for i40e double VLAN, QinQ, stripping and insertion.**\n\n Added support to the i40e driver for offloading double VLAN (QinQ) tags to\n the mbuf header, and inserting double vlan tags by hardware to the packets\n to be transmitted. Added a new field ``vlan_tci_outer`` in the ``rte_mbuf``\n struct, and new flags in ``ol_flags`` to support this feature.\n\n\n\n* **Added fm10k promiscuous mode support.**\n\n Added support for promiscuous/allmulticast enable and disable in the fm10k PF\n function. VF is not supported yet.\n\n\n* **Added fm10k jumbo frame support.**\n\n Added support for jumbo frame less than 15K in both VF and PF functions in the\n fm10k pmd.\n\n\n* **Added fm10k mac vlan filtering support.**\n\n Added support for the fm10k MAC filter, only available in PF. Updated the\n VLAN filter to add/delete one static entry in the MAC table for each\n combination of VLAN and MAC address.\n\n\n* **Added support for the Broadcom bnx2x driver.**\n\n Added support for the Broadcom NetXtreme II bnx2x driver.\n It is supported only on Linux 64-bit and disabled by default.\n\n\n* **Added support for the Chelsio CXGBE driver.**\n\n Added support for the CXGBE Poll Mode Driver for the Chelsio Terminator 5\n series of 10G/40G adapters.\n\n\n* **Enhanced support for Mellanox ConnectX-3 driver (mlx4).**\n\n * Support Mellanox OFED 3.0.\n * Improved performance for both RX and TX operations.\n * Better link status information.\n * Outer L3/L4 checksum offload support.\n * Inner L3/L4 checksum offload support for VXLAN.\n\n\n* **Enabled VMXNET3 vlan filtering.**\n\n Added support for the VLAN filter functionality of the VMXNET3 interface.\n\n\n* **Added support for vhost live migration.**\n\n Added support to allow live migration of vhost. Without this feature, qemu\n will report the following error: \"migrate: Migration disabled: vhost lacks\n VHOST_F_LOG_ALL feature\".\n\n\n* **Added support for pcap jumbo frames.**\n\n Extended the PCAP PMD to support jumbo frames for RX and TX.\n\n\n* **Added support for the TILE-Gx architecture.**\n\n Added support for the EZchip TILE-Gx family of SoCs.\n\n\n* **Added hardware memory transactions/lock elision for x86.**\n\n Added the use of hardware memory transactions (HTM) on fast-path for rwlock\n and spinlock (a.k.a. lock elision). The methods are implemented for x86\n using Restricted Transactional Memory instructions (Intel(r) Transactional\n Synchronization Extensions). The implementation fall-backs to the normal\n rwlock if HTM is not available or memory transactions fail. This is not a\n replacement for all rwlock usages since not all critical sections protected\n by locks are friendly to HTM. For example, an attempt to perform a HW I/O\n operation inside a hardware memory transaction always aborts the transaction\n since the CPU is not able to roll-back should the transaction\n fail. Therefore, hardware transactional locks are not advised to be used\n around ``rte_eth_rx_burst()`` and ``rte_eth_tx_burst()`` calls.\n\n\n* **Updated Jenkins Hash function**\n\n Updated the version of the Jenkins Hash (jhash) function used in DPDK from\n the 1996 version to the 2006 version. This gives up to 35% better\n performance, compared to the original one.\n\n Note, the hashes generated by the updated version differ from the hashes\n generated by the previous version.\n\n\n* **Added software implementation of the Toeplitz RSS hash**\n\n Added a software implementation of the Toeplitz hash function used by RSS. It\n can be used either for packet distribution on a single queue NIC or for\n simulating RSS computation on a specific NIC (for example after GRE header\n de-encapsulation).\n\n\n* **Replaced the existing hash library with a Cuckoo hash implementation.**\n\n Replaced the existing hash library with another approach, using the Cuckoo\n Hash method to resolve collisions (open addressing). This method pushes\n items from a full bucket when a new entry must be added to it, storing the\n evicted entry in an alternative location, using a secondary hash function.\n\n This gives the user the ability to store more entries when a bucket is full,\n in comparison with the previous implementation.\n\n The API has not been changed, although new fields have been added in the\n ``rte_hash`` structure, which has been changed to internal use only.\n\n The main change when creating a new table is that the number of entries per\n bucket is now fixed, so its parameter is ignored now (it is still there to\n maintain the same parameters structure).\n\n Also, the maximum burst size in lookup_burst function hash been increased to\n 64, to improve performance.\n\n\n* **Optimized KNI RX burst size computation.**\n\n Optimized KNI RX burst size computation by avoiding checking how many\n entries are in ``kni->rx_q`` prior to actually pulling them from the fifo.\n\n\n* **Added KNI multicast.**\n\n Enabled adding multicast addresses to KNI interfaces by adding an empty\n callback for ``set_rx_mode`` (typically used for setting up hardware) so\n that the ioctl succeeds. This is the same thing as the Linux tap interface\n does.\n\n\n* **Added cmdline polling mode.**\n\n Added the ability to process console input in the same thread as packet\n processing by using the ``poll()`` function.\n\n* **Added VXLAN Tunnel End point sample application.**\n\n Added a Tunnel End point (TEP) sample application that simulates a VXLAN\n Tunnel Endpoint (VTEP) termination in DPDK. It is used to demonstrate the\n offload and filtering capabilities of Intel XL710 10/40 GbE NICsfor VXLAN\n packets.\n\n\n* **Enabled combining of the ``-m`` and ``--no-huge`` EAL options.**\n\n Added option to allow combining of the ``-m`` and ``--no-huge`` EAL command\n line options.\n\n This allows user application to run as non-root but with higher memory\n allocations, and removes a constraint on ``--no-huge`` mode being limited to\n 64M.\n\n\n\nResolved Issues\n---------------\n\n* **acl: Fix ambiguity between test rules.**\n\n Some test rules had equal priority for the same category. That could cause\n an ambiguity in building the trie and test results.\n\n\n* **acl: Fix invalid rule wildness calculation for bitmask field type.**\n\n\n* **acl: Fix matching rule.**\n\n\n* **acl: Fix unneeded trie splitting for subset of rules.**\n\n When rebuilding a trie for limited rule-set, don't try to split the rule-set\n even further.\n\n\n* **app/testpmd: Fix crash when port id out of bound.**\n\n Fixed issues in testpmd where using a port greater than 32 would cause a seg\n fault.\n\n Fixes: edab33b1c01d (\"app/testpmd: support port hotplug\")\n\n\n* **app/testpmd: Fix reply to a multicast ICMP request.**\n\n Set the IP source and destination addresses in the IP header of the ICMP\n reply.\n\n\n* **app/testpmd: fix MAC address in ARP reply.**\n\n Fixed issue where in the ``icmpecho`` forwarding mode, ARP replies from\n testpmd contain invalid zero-filled MAC addresses.\n\n Fixes: 31db4d38de72 (\"net: change arp header struct declaration\")\n\n\n* **app/testpmd: fix default flow control values.**\n\n Fixes: 422a20a4e62d (\"app/testpmd: fix uninitialized flow control variables\")\n\n\n* **bonding: Fix crash when stopping inactive slave.**\n\n\n* **bonding: Fix device initialization error handling.**\n\n\n* **bonding: Fix initial link status of slave.**\n\n On Fortville NIC, link status change interrupt callback was not executed\n when slave in bonding was (re-)started.\n\n\n* **bonding: Fix socket id for LACP slave.**\n\n Fixes: 46fb43683679 (\"bond: add mode 4\")\n\n\n* **bonding: Fix device initialization error handling.**\n\n\n* **cmdline: Fix small memory leak.**\n\n A function in ``cmdline.c`` had a return that did not free the buf properly.\n\n\n* **config: Enable same drivers options for Linux and BSD.**\n\n Enabled vector ixgbe and i40e bulk alloc for BSD as it is already done for\n Linux.\n\n Fixes: 304caba12643 (\"config: fix bsd options\")\n Fixes: 0ff3324da2eb (\"ixgbe: rework vector pmd following mbuf changes\")\n\n\n* **devargs: Fix crash on failure.**\n\n This problem occurred when passing an invalid PCI id to the blacklist API in\n devargs.\n\n\n* **e1000/i40e: Fix descriptor done flag with odd address.**\n\n\n* **e1000/igb: fix ieee1588 timestamping initialization.**\n\n Fixed issue with e1000 ieee1588 timestamp initialization. On initialization\n the IEEE1588 functions read the system time to set their timestamp. However,\n on some 1G NICs, for example, i350, system time is disabled by default and\n the IEEE1588 timestamp was always 0.\n\n\n* **eal/bsd: Fix inappropriate header guards.**\n\n\n* **eal/bsd: Fix virtio on FreeBSD.**\n\n Closing the ``/dev/io`` fd caused a SIGBUS in inb/outb instructions as the\n process lost the IOPL privileges once the fd is closed.\n\n Fixes: 8a312224bcde (\"eal/bsd: fix fd leak\")\n\n\n* **eal/linux: Fix comments on vfio MSI.**\n\n\n* **eal/linux: Fix irq handling with igb_uio.**\n\n Fixed an issue where the the introduction of ``uio_pci_generic`` broke\n interrupt handling with igb_uio.\n\n Fixes: c112df6875a5 (\"eal/linux: toggle interrupt for uio_pci_generic\")\n\n\n* **eal/linux: Fix numa node detection.**\n\n\n* **eal/linux: Fix socket value for undetermined numa node.**\n\n Sets zero as the default value of pci device numa_node if the socket could\n not be determined. This provides the same default value as FreeBSD which has\n no NUMA support, and makes the return value of ``rte_eth_dev_socket_id()``\n be consistent with the API description.\n\n\n* **eal/ppc: Fix cpu cycle count for little endian.**\n\n On IBM POWER8 PPC64 little endian architecture, the definition of tsc union\n will be different. This fix enables the right output from ``rte_rdtsc()``.\n\n\n* **ethdev: Fix check of threshold for TX freeing.**\n\n Fixed issue where the parameter to ``tx_free_thresh`` was not consistent\n between the drivers.\n\n\n* **ethdev: Fix crash if malloc of user callback fails.**\n\n If ``rte_zmalloc()`` failed in ``rte_eth_dev_callback_register`` then the\n NULL pointer would be dereferenced.\n\n\n* **ethdev: Fix illegal port access.**\n\n To obtain a detachable flag, ``pci_drv`` is accessed in\n ``rte_eth_dev_is_detachable()``. However ``pci_drv`` is only valid if port\n is enabled. Fixed by checking ``rte_eth_dev_is_valid_port()`` first.\n\n\n* **ethdev: Make tables const.**\n\n\n* **ethdev: Rename and extend the mirror type.**\n\n\n* **examples/distributor: Fix debug macro.**\n\n The macro to turn on additional debug output when the app was compiled with\n ``-DDEBUG`` was broken.\n\n Fixes: 07db4a975094 (\"examples/distributor: new sample app\")\n\n\n* **examples/kni: Fix crash on exit.**\n\n\n* **examples/vhost: Fix build with debug enabled.**\n\n Fixes: 72ec8d77ac68 (\"examples/vhost: rework duplicated code\")\n\n\n* **fm10k: Fix RETA table initialization.**\n\n The fm10k driver has 128 RETA entries in 32 registers, but it only\n initialized the first 32 when doing multiple RX queue configurations. This\n fix initializes all 128 entries.\n\n\n* **fm10k: Fix RX buffer size.**\n\n\n* **fm10k: Fix TX multi-segment frame.**\n\n\n* **fm10k: Fix TX queue cleaning after start error.**\n\n\n* **fm10k: Fix Tx queue cleaning after start error.**\n\n\n* **fm10k: Fix default mac/vlan in switch.**\n\n\n* **fm10k: Fix interrupt fault handling.**\n\n\n* **fm10k: Fix jumbo frame issue.**\n\n\n* **fm10k: Fix mac/vlan filtering.**\n\n\n* **fm10k: Fix maximum VF number.**\n\n\n* **fm10k: Fix maximum queue number for VF.**\n\n Both PF and VF shared code in function ``fm10k_stats_get()``. The function\n worked with PF, but had problems with VF since it has less queues than PF.\n\n Fixes: a6061d9e7075 (\"fm10k: register PF driver\")\n\n\n* **fm10k: Fix queue disabling.**\n\n\n* **fm10k: Fix switch synchronization.**\n\n\n* **i40e/base: Fix error handling of NVM state update.**\n\n\n* **i40e/base: Fix hardware port number for pass-through.**\n\n\n* **i40e/base: Rework virtual address retrieval for lan queue.**\n\n\n* **i40e/base: Update LED blinking.**\n\n\n* **i40e/base: Workaround for PHY type with firmware < 4.4.**\n\n\n* **i40e: Disable setting of PHY configuration.**\n\n\n* **i40e: Fix SCTP flow director.**\n\n\n* **i40e: Fix check of descriptor done flag.**\n\n Fixes: 4861cde46116 (\"i40e: new poll mode driver\")\n Fixes: 05999aab4ca6 (\"i40e: add or delete flow director\")\n\n\n* **i40e: Fix condition to get VMDQ info.**\n\n\n* **i40e: Fix registers access from big endian CPU.**\n\n\n* **i40evf: Clear command when error occurs.**\n\n\n* **i40evf: Fix RSS with less RX queues than TX queues.**\n\n\n* **i40evf: Fix crash when setup TX queues.**\n\n\n* **i40evf: Fix jumbo frame support.**\n\n\n* **i40evf: Fix offload capability flags.**\n\n Added checksum offload capability flags which have already been supported\n for a long time.\n\n\n* **ivshmem: Fix crash in corner case.**\n\n Fixed issues where depending on the configured segments it was possible to\n hit a segmentation fault as a result of decrementing an unsigned index with\n value 0.\n\n\n Fixes: 40b966a211ab (\"ivshmem: library changes for mmaping using ivshmem\")\n\n\n* **ixgbe/base: Fix SFP probing.**\n\n\n* **ixgbe/base: Fix TX pending clearing.**\n\n\n* **ixgbe/base: Fix X550 CS4227 address.**\n\n\n* **ixgbe/base: Fix X550 PCIe master disabling.**\n\n\n* **ixgbe/base: Fix X550 check.**\n\n\n* **ixgbe/base: Fix X550 init early return.**\n\n\n* **ixgbe/base: Fix X550 link speed.**\n\n\n* **ixgbe/base: Fix X550em CS4227 speed mode.**\n\n\n* **ixgbe/base: Fix X550em SFP+ link stability.**\n\n\n* **ixgbe/base: Fix X550em UniPHY link configuration.**\n\n\n* **ixgbe/base: Fix X550em flow control for KR backplane.**\n\n\n* **ixgbe/base: Fix X550em flow control to be KR only.**\n\n\n* **ixgbe/base: Fix X550em link setup without SFP.**\n\n\n* **ixgbe/base: Fix X550em mux after MAC reset.**\n\n Fixes: d2e72774e58c (\"ixgbe/base: support X550\")\n\n\n* **ixgbe/base: Fix bus type overwrite.**\n\n\n* **ixgbe/base: Fix init handling of X550em link down.**\n\n\n* **ixgbe/base: Fix lan id before first i2c access.**\n\n\n* **ixgbe/base: Fix mac type checks.**\n\n\n* **ixgbe/base: Fix tunneled UDP and TCP frames in flow director.**\n\n\n* **ixgbe: Check mbuf refcnt when clearing a ring.**\n\n The function to clear the TX ring when a port was being closed, e.g. on exit\n in testpmd, was not checking the mbuf refcnt before freeing it. Since the\n function in the vector driver to clear the ring after TX does not setting\n the pointer to NULL post-free, this caused crashes if mbuf debugging was\n turned on.\n\n\n* **ixgbe: Fix RX with buffer address not word aligned.**\n\n Niantic HW expects the Header Buffer Address in the RXD must be word\n aligned.\n\n\n* **ixgbe: Fix RX with buffer address not word aligned.**\n\n\n* **ixgbe: Fix Rx queue reset.**\n\n Fix to reset vector related RX queue fields to their initial values.\n\n Fixes: c95584dc2b18 (\"ixgbe: new vectorized functions for Rx/Tx\")\n\n\n* **ixgbe: Fix TSO in IPv6.**\n\n When TSO was used with IPv6, the generated frames were incorrect. The L4\n frame was OK, but the length field of IPv6 header was not populated\n correctly.\n\n\n* **ixgbe: Fix X550 flow director check.**\n\n\n* **ixgbe: Fix check for split packets.**\n\n The check for split packets to be reassembled in the vector ixgbe PMD was\n incorrectly only checking the first 16 elements of the array instead of\n all 32.\n\n Fixes: cf4b4708a88a (\"ixgbe: improve slow-path perf with vector scattered Rx\")\n\n\n* **ixgbe: Fix data access on big endian cpu.**\n\n\n* **ixgbe: Fix flow director flexbytes offset.**\n\n\n Fixes: d54a9888267c (\"ixgbe: support flexpayload configuration of flow director\")\n\n\n* **ixgbe: Fix number of segments with vector scattered Rx.**\n\n Fixes: cf4b4708a88a (ixgbe: improve slow-path perf with vector scattered Rx)\n\n\n* **ixgbe: Fix offload config option name.**\n\n The RX_OLFLAGS option was renamed from DISABLE to ENABLE in the driver code\n and Linux config. It is now renamed also in the BSD config and\n documentation.\n\n Fixes: 359f106a69a9 (\"ixgbe: prefer enabling olflags rather than not disabling\")\n\n\n* **ixgbe: Fix release queue mbufs.**\n\n The calculations of what mbufs were valid in the RX and TX queues were\n incorrect when freeing the mbufs for the vector PMD. This led to crashes due\n to invalid reference counts when mbuf debugging was turned on, and possibly\n other more subtle problems (such as mbufs being freed when in use) in other\n cases.\n\n\n Fixes: c95584dc2b18 (\"ixgbe: new vectorized functions for Rx/Tx\")\n\n\n* **ixgbe: Move PMD specific fields out of base driver.**\n\n Move ``rx_bulk_alloc_allowed`` and ``rx_vec_allowed`` from ``ixgbe_hw`` to\n ``ixgbe_adapter``.\n\n Fixes: 01fa1d6215fa (\"ixgbe: unify Rx setup\")\n\n\n* **ixgbe: Rename TX queue release function.**\n\n\n* **ixgbevf: Fix RX function selection.**\n\n The logic to select ixgbe the VF RX function is different than the PF.\n\n\n* **ixgbevf: Fix link status for PF up/down events.**\n\n\n* **kni: Fix RX loop limit.**\n\n Loop processing packets dequeued from rx_q was using the number of packets\n requested, not how many it actually received.\n\n\n* **kni: Fix ioctl in containers, like Docker.**\n\n\n* **kni: Fix multicast ioctl handling.**\n\n\n* **log: Fix crash after log_history dump.**\n\n\n* **lpm: Fix big endian support.**\n\n\n* **lpm: Fix depth small entry add.**\n\n\n* **mbuf: Fix cloning with private mbuf data.**\n\n Added a new ``priv_size`` field in mbuf structure that should be initialized\n at mbuf pool creation. This field contains the size of the application\n private data in mbufs.\n\n Introduced new static inline functions ``rte_mbuf_from_indirect()`` and\n ``rte_mbuf_to_baddr()`` to replace the existing macros, which take the\n private size into account when attaching and detaching mbufs.\n\n\n* **mbuf: Fix data room size calculation in pool init.**\n\n Deduct the mbuf data room size from ``mempool->elt_size`` and ``priv_size``,\n instead of using an hardcoded value that is not related to the real buffer\n size.\n\n To use ``rte_pktmbuf_pool_init()``, the user can either:\n\n * Give a NULL parameter to rte_pktmbuf_pool_init(): in this case, the\n private size is assumed to be 0, and the room size is ``mp->elt_size`` -\n ``sizeof(struct rte_mbuf)``.\n * Give the ``rte_pktmbuf_pool_private`` filled with appropriate\n data_room_size and priv_size values.\n\n\n* **mbuf: Fix init when private size is not zero.**\n\n Allow the user to use the default ``rte_pktmbuf_init()`` function even if\n the mbuf private size is not 0.\n\n\n* **mempool: Add structure for object headers.**\n\n Each object stored in mempools are prefixed by a header, allowing for\n instance to retrieve the mempool pointer from the object. When debug is\n enabled, a cookie is also added in this header that helps to detect\n corruptions and double-frees.\n\n Introduced a structure that materializes the content of this header,\n and will simplify future patches adding things in this header.\n\n\n* **mempool: Fix pages computation to determine number of objects.**\n\n\n* **mempool: Fix returned value after counting objects.**\n\n Fixes: 148f963fb532 (\"xen: core library changes\")\n\n\n* **mlx4: Avoid requesting TX completion events to improve performance.**\n\n Instead of requesting a completion event for each TX burst, request it on a\n fixed schedule once every MLX4_PMD_TX_PER_COMP_REQ (currently 64) packets to\n improve performance.\n\n\n* **mlx4: Fix compilation as a shared library and on 32 bit platforms.**\n\n\n* **mlx4: Fix possible crash on scattered mbuf allocation failure.**\n\n Fixes issue where failing to allocate a segment, ``mlx4_rx_burst_sp()``\n could call ``rte_pktmbuf_free()`` on an incomplete scattered mbuf whose next\n pointer in the last segment is not set.\n\n\n* **mlx4: Fix support for multiple vlan filters.**\n\n This fixes the \"Multiple RX VLAN filters can be configured, but only the\n first one works\" bug.\n\n\n* **pcap: Fix storage of name and type in queues.**\n\n pcap_rx_queue/pcap_tx_queue should store it's own copy of name/type values,\n not the pointer to temporary allocated space.\n\n\n* **pci: Fix memory leaks and needless increment of map address.**\n\n\n* **pci: Fix uio mapping differences between linux and bsd.**\n\n\n* **port: Fix unaligned access to metadata.**\n\n Fix RTE_MBUF_METADATA macros to allow for unaligned accesses to meta-data\n fields.\n\n\n* **ring: Fix return of new port id on creation.**\n\n\n* **timer: Fix race condition.**\n\n Eliminate problematic race condition in ``rte_timer_manage()`` that can lead\n to corruption of per-lcore pending-lists (implemented as skip-lists).\n\n\n* **vfio: Fix overflow of BAR region offset and size.**\n\n Fixes: 90a1633b2347 (\"eal/Linux: allow to map BARs with MSI-X tables\")\n\n\n* **vhost: Fix enqueue/dequeue to handle chained vring descriptors.**\n\n\n* **vhost: Fix race for connection fd.**\n\n\n* **vhost: Fix virtio freeze due to missed interrupt.**\n\n\n* **virtio: Fix crash if CQ is not negotiated.**\n\n Fix NULL dereference if virtio control queue is not negotiated.\n\n\n* **virtio: Fix ring size negotiation.**\n\n Negotiate the virtio ring size. The host may allow for very large rings but\n application may only want a smaller ring. Conversely, if the number of\n descriptors requested exceeds the virtio host queue size, then just silently\n use the smaller host size.\n\n This fixes issues with virtio in non-QEMU environments. For example Google\n Compute Engine allows up to 16K elements in ring.\n\n\n* **vmxnet3: Fix link state handling.**\n\n\nKnown Issues\n------------\n\n* When running the ``vmdq`` sample or ``vhost`` sample applications with the\n Intel(R) XL710 (i40e) NIC, the configuration option\n ``CONFIG_RTE_MAX_QUEUES_PER_PORT`` should be increased from 256 to 1024.\n\n\n* VM power manager may not work on systems with more than 64 cores.\n\n\nAPI Changes\n-----------\n\n* The order that user supplied RX and TX callbacks are called in has been\n changed to the order that they were added (fifo) in line with end-user\n expectations. The previous calling order was the reverse of this (lifo) and\n was counter intuitive for users. The actual API is unchanged.\n\n\nABI Changes\n-----------\n\n* The ``rte_hash`` structure has been changed to internal use only.\n" }, { "path": "doc/guides/rel_notes/supported_os.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nSupported Operating Systems\n===========================\n\nThe following Linux distributions were successfully used to compiler or run DPDK.\n\n* FreeBSD 10\n\n* Fedora release 20\n\n* Ubuntu 14.04 LTS\n\n* Wind River Linux 6\n\n* Red Hat Enterprise Linux 6.5\n\n* SUSE Enterprise Linux 11 SP3\n\nThese distributions may need additional packages that are not installed by default, or a specific kernel.\nRefer to the :ref:`Linux guide ` and :ref:`FreeBSD guide ` for details.\n" }, { "path": "doc/guides/sample_app_ug/cmd_line.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nCommand Line Sample Application\n===============================\n\nThis chapter describes the Command Line sample application that\nis part of the Data Plane Development Kit (DPDK).\n\nOverview\n--------\n\nThe Command Line sample application is a simple application that\ndemonstrates the use of the command line interface in the DPDK.\nThis application is a readline-like interface that can be used\nto debug a DPDK application, in a Linux* application environment.\n\n.. note::\n\n The rte_cmdline library should not be used in production code since\n it is not validated to the same standard as other Intel® DPDK libraries.\n See also the \"rte_cmdline library should not be used in production code due to limited testing\" item\n in the \"Known Issues\" section of the Release Notes.\n\nThe Command Line sample application supports some of the features of the GNU readline library such as, completion,\ncut/paste and some other special bindings that make configuration and debug faster and easier.\n\nThe application shows how the rte_cmdline application can be extended to handle a list of objects.\nThere are three simple commands:\n\n* add obj_name IP: Add a new object with an IP/IPv6 address associated to it.\n\n* del obj_name: Delete the specified object.\n\n* show obj_name: Show the IP associated with the specified object.\n\n.. note::\n\n To terminate the application, use **Ctrl-d**.\n\nCompiling the Application\n-------------------------\n\n#. Go to example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/cmdline\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n Refer to the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nTo run the application in linuxapp environment, issue the following command:\n\n.. code-block:: console\n\n $ ./build/cmdline -c f -n 4\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications\nand the Environment Abstraction Layer (EAL) options.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of the code.\n\nEAL Initialization and cmdline Start\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe first task is the initialization of the Environment Abstraction Layer (EAL).\nThis is achieved as follows:\n\n.. code-block:: c\n\n int main(int argc, char **argv)\n {\n ret = rte_eal_init(argc, argv);\n if (ret < 0)\n rte_panic(\"Cannot init EAL\\n\");\n\nThen, a new command line object is created and started to interact with the user through the console:\n\n.. code-block:: c\n\n cl = cmdline_stdin_new(main_ctx, \"example> \");\n cmdline_interact(cl);\n cmdline_stdin_exit(cl);\n\nThe cmd line_interact() function returns when the user types **Ctrl-d** and in this case,\nthe application exits.\n\nDefining a cmdline Context\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nA cmdline context is a list of commands that are listed in a NULL-terminated table, for example:\n\n.. code-block:: c\n\n cmdline_parse_ctx_t main_ctx[] = {\n (cmdline_parse_inst_t *) &cmd_obj_del_show,\n (cmdline_parse_inst_t *) &cmd_obj_add,\n (cmdline_parse_inst_t *) &cmd_help,\n NULL,\n };\n\nEach command (of type cmdline_parse_inst_t) is defined statically.\nIt contains a pointer to a callback function that is executed when the command is parsed,\nan opaque pointer, a help string and a list of tokens in a NULL-terminated table.\n\nThe rte_cmdline application provides a list of pre-defined token types:\n\n* String Token: Match a static string, a list of static strings or any string.\n\n* Number Token: Match a number that can be signed or unsigned, from 8-bit to 32-bit.\n\n* IP Address Token: Match an IPv4 or IPv6 address or network.\n\n* Ethernet* Address Token: Match a MAC address.\n\nIn this example, a new token type obj_list is defined and implemented\nin the parse_obj_list.c and parse_obj_list.h files.\n\nFor example, the cmd_obj_del_show command is defined as shown below:\n\n.. code-block:: c\n\n struct cmd_obj_add_result {\n cmdline_fixed_string_t action;\n cmdline_fixed_string_t name;\n struct object *obj;\n };\n\n static void cmd_obj_del_show_parsed(void *parsed_result, struct cmdline *cl, attribute ((unused)) void *data)\n {\n /* ... */\n }\n\n cmdline_parse_token_string_t cmd_obj_action = TOKEN_STRING_INITIALIZER(struct cmd_obj_del_show_result, action, \"show#del\");\n\n parse_token_obj_list_t cmd_obj_obj = TOKEN_OBJ_LIST_INITIALIZER(struct cmd_obj_del_show_result, obj, &global_obj_list);\n\n cmdline_parse_inst_t cmd_obj_del_show = {\n .f = cmd_obj_del_show_parsed, /* function to call */\n .data = NULL, /* 2nd arg of func */\n .help_str = \"Show/del an object\",\n .tokens = { /* token list, NULL terminated */\n (void *)&cmd_obj_action,\n (void *)&cmd_obj_obj,\n NULL,\n },\n };\n\nThis command is composed of two tokens:\n\n* The first token is a string token that can be show or del.\n\n* The second token is an object that was previously added using the add command in the global_obj_list variable.\n\nOnce the command is parsed, the rte_cmdline application fills a cmd_obj_del_show_result structure.\nA pointer to this structure is given as an argument to the callback function and can be used in the body of this function.\n" }, { "path": "doc/guides/sample_app_ug/dist_app.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nDistributor Sample Application\n==============================\n\nThe distributor sample application is a simple example of packet distribution\nto cores using the Data Plane Development Kit (DPDK).\n\nOverview\n--------\n\nThe distributor application performs the distribution of packets that are received\non an RX_PORT to different cores. When processed by the cores, the destination\nport of a packet is the port from the enabled port mask adjacent to the one on\nwhich the packet was received, that is, if the first four ports are enabled\n(port mask 0xf), ports 0 and 1 RX/TX into each other, and ports 2 and 3 RX/TX\ninto each other.\n\nThis application can be used to benchmark performance using the traffic\ngenerator as shown in the figure below.\n\n.. _figure_dist_perf:\n\n.. figure:: img/dist_perf.*\n\n Performance Benchmarking Setup (Basic Environment)\n\n\nCompiling the Application\n-------------------------\n\n#. Go to the sample application directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/distributor\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the DPDK Getting Started Guide for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\n#. The application has a number of command line options:\n\n .. code-block:: console\n\n ./build/distributor_app [EAL options] -- -p PORTMASK\n\n where,\n\n * -p PORTMASK: Hexadecimal bitmask of ports to configure\n\n#. To run the application in linuxapp environment with 10 lcores, 4 ports,\n issue the command:\n\n .. code-block:: console\n\n $ ./build/distributor_app -c 0x4003fe -n 4 -- -p f\n\n#. Refer to the DPDK Getting Started Guide for general information on running\n applications and the Environment Abstraction Layer (EAL) options.\n\nExplanation\n-----------\n\nThe distributor application consists of three types of threads: a receive\nthread (lcore_rx()), a set of worker threads(lcore_worker())\nand a transmit thread(lcore_tx()). How these threads work together is shown\nin :numref:`figure_dist_app` below. The main() function launches threads of these three types.\nEach thread has a while loop which will be doing processing and which is\nterminated only upon SIGINT or ctrl+C. The receive and transmit threads\ncommunicate using a software ring (rte_ring structure).\n\nThe receive thread receives the packets using rte_eth_rx_burst() and gives\nthem to the distributor (using rte_distributor_process() API) which will\nbe called in context of the receive thread itself. The distributor distributes\nthe packets to workers threads based on the tagging of the packet -\nindicated by the hash field in the mbuf. For IP traffic, this field is\nautomatically filled by the NIC with the \"usr\" hash value for the packet,\nwhich works as a per-flow tag.\n\nMore than one worker thread can exist as part of the application, and these\nworker threads do simple packet processing by requesting packets from\nthe distributor, doing a simple XOR operation on the input port mbuf field\n(to indicate the output port which will be used later for packet transmission)\nand then finally returning the packets back to the distributor in the RX thread.\n\nMeanwhile, the receive thread will call the distributor api\nrte_distributor_returned_pkts() to get the packets processed, and will enqueue\nthem to a ring for transfer to the TX thread for transmission on the output port.\nThe transmit thread will dequeue the packets from the ring and transmit them on\nthe output port specified in packet mbuf.\n\nUsers who wish to terminate the running of the application have to press ctrl+C\n(or send SIGINT to the app). Upon this signal, a signal handler provided\nin the application will terminate all running threads gracefully and print\nfinal statistics to the user.\n\n.. _figure_dist_app:\n\n.. figure:: img/dist_app.*\n\n Distributor Sample Application Layout\n\n\nDebug Logging Support\n---------------------\n\nDebug logging is provided as part of the application; the user needs to uncomment\nthe line \"#define DEBUG\" defined in start of the application in main.c to enable debug logs.\n\nStatistics\n----------\n\nUpon SIGINT (or) ctrl+C, the print_stats() function displays the count of packets\nprocessed at the different stages in the application.\n\nApplication Initialization\n--------------------------\n\nCommand line parsing is done in the same way as it is done in the L2 Forwarding Sample\nApplication. See Section 9.4.1, \"Command Line Arguments\".\n\nMbuf pool initialization is done in the same way as it is done in the L2 Forwarding\nSample Application. See Section 9.4.2, \"Mbuf Pool Initialization\".\n\nDriver Initialization is done in same way as it is done in the L2 Forwarding Sample\nApplication. See Section 9.4.3, \"Driver Initialization\".\n\nRX queue initialization is done in the same way as it is done in the L2 Forwarding\nSample Application. See Section 9.4.4, \"RX Queue Initialization\".\n\nTX queue initialization is done in the same way as it is done in the L2 Forwarding\nSample Application. See Section 9.4.5, \"TX Queue Initialization\".\n" }, { "path": "doc/guides/sample_app_ug/exception_path.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nException Path Sample Application\n=================================\n\nThe Exception Path sample application is a simple example that demonstrates the use of the DPDK\nto set up an exception path for packets to go through the Linux* kernel.\nThis is done by using virtual TAP network interfaces.\nThese can be read from and written to by the DPDK application and\nappear to the kernel as a standard network interface.\n\nOverview\n--------\n\nThe application creates two threads for each NIC port being used.\nOne thread reads from the port and writes the data unmodified to a thread-specific TAP interface.\nThe second thread reads from a TAP interface and writes the data unmodified to the NIC port.\n\nThe packet flow through the exception path application is as shown in the following figure.\n\n.. _figure_exception_path_example:\n\n.. figure:: img/exception_path_example.*\n\n Packet Flow\n\n\nTo make throughput measurements, kernel bridges must be setup to forward data between the bridges appropriately.\n\nCompiling the Application\n-------------------------\n\n#. Go to example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/exception_path\n\n#. Set the target (a default target will be used if not specified).\n For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\nThis application is intended as a linuxapp only.\nSee the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nThe application requires a number of command line options:\n\n.. code-block:: console\n\n .build/exception_path [EAL options] -- -p PORTMASK -i IN_CORES -o OUT_CORES\n\nwhere:\n\n* -p PORTMASK: A hex bitmask of ports to use\n\n* -i IN_CORES: A hex bitmask of cores which read from NIC\n\n* -o OUT_CORES: A hex bitmask of cores which write to NIC\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications\nand the Environment Abstraction Layer (EAL) options.\n\nThe number of bits set in each bitmask must be the same.\nThe coremask -c parameter of the EAL options should include IN_CORES and OUT_CORES.\nThe same bit must not be set in IN_CORES and OUT_CORES.\nThe affinities between ports and cores are set beginning with the least significant bit of each mask, that is,\nthe port represented by the lowest bit in PORTMASK is read from by the core represented by the lowest bit in IN_CORES,\nand written to by the core represented by the lowest bit in OUT_CORES.\n\nFor example to run the application with two ports and four cores:\n\n.. code-block:: console\n\n ./build/exception_path -c f -n 4 -- -p 3 -i 3 -o c\n\nGetting Statistics\n~~~~~~~~~~~~~~~~~~\n\nWhile the application is running, statistics on packets sent and\nreceived can be displayed by sending the SIGUSR1 signal to the application from another terminal:\n\n.. code-block:: console\n\n killall -USR1 exception_path\n\nThe statistics can be reset by sending a SIGUSR2 signal in a similar way.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of the code.\n\nInitialization\n~~~~~~~~~~~~~~\n\nSetup of the mbuf pool, driver and queues is similar to the setup done in the L2 Forwarding sample application\n(see Chapter 9 \"L2 forwarding Sample Application (in Real and Virtualized Environments\" for details).\nIn addition, the TAP interfaces must also be created.\nA TAP interface is created for each lcore that is being used.\nThe code for creating the TAP interface is as follows:\n\n.. code-block:: c\n\n /*\n * Create a tap network interface, or use existing one with same name.\n * If name[0]='\\0' then a name is automatically assigned and returned in name.\n */\n\n static int tap_create(char *name)\n {\n struct ifreq ifr;\n int fd, ret;\n\n fd = open(\"/dev/net/tun\", O_RDWR);\n if (fd < 0)\n return fd;\n\n memset(&ifr, 0, sizeof(ifr));\n\n /* TAP device without packet information */\n\n ifr.ifr_flags = IFF_TAP | IFF_NO_PI;\n if (name && *name)\n rte_snprinf(ifr.ifr_name, IFNAMSIZ, name);\n\n ret = ioctl(fd, TUNSETIFF, (void *) &ifr);\n\n if (ret < 0) {\n close(fd);\n return ret;\n\n }\n\n if (name)\n rte_snprintf(name, IFNAMSIZ, ifr.ifr_name);\n\n return fd;\n }\n\nThe other step in the initialization process that is unique to this sample application\nis the association of each port with two cores:\n\n* One core to read from the port and write to a TAP interface\n\n* A second core to read from a TAP interface and write to the port\n\nThis is done using an array called port_ids[], which is indexed by the lcore IDs.\nThe population of this array is shown below:\n\n.. code-block:: c\n\n tx_port = 0;\n rx_port = 0;\n\n RTE_LCORE_FOREACH(i) {\n if (input_cores_mask & (1ULL << i)) {\n /* Skip ports that are not enabled */\n while ((ports_mask & (1 << rx_port)) == 0) {\n rx_port++;\n if (rx_port > (sizeof(ports_mask) * 8))\n goto fail; /* not enough ports */\n }\n port_ids[i] = rx_port++;\n } else if (output_cores_mask & (1ULL << i)) {\n /* Skip ports that are not enabled */\n while ((ports_mask & (1 << tx_port)) == 0) {\n tx_port++;\n if (tx_port > (sizeof(ports_mask) * 8))\n goto fail; /* not enough ports */\n }\n port_ids[i] = tx_port++;\n }\n }\n\nPacket Forwarding\n~~~~~~~~~~~~~~~~~\n\nAfter the initialization steps are complete, the main_loop() function is run on each lcore.\nThis function first checks the lcore_id against the user provided input_cores_mask and output_cores_mask to see\nif this core is reading from or writing to a TAP interface.\n\nFor the case that reads from a NIC port, the packet reception is the same as in the L2 Forwarding sample application\n(see Section 9.4.6, \"Receive, Process and Transmit Packets\").\nThe packet transmission is done by calling write() with the file descriptor of the appropriate TAP interface\nand then explicitly freeing the mbuf back to the pool.\n\n.. code-block:: c\n\n /* Loop forever reading from NIC and writing to tap */\n\n for (;;) {\n struct rte_mbuf *pkts_burst[PKT_BURST_SZ];\n unsigned i;\n\n const unsigned nb_rx = rte_eth_rx_burst(port_ids[lcore_id], 0, pkts_burst, PKT_BURST_SZ);\n\n lcore_stats[lcore_id].rx += nb_rx;\n\n for (i = 0; likely(i < nb_rx); i++) {\n struct rte_mbuf *m = pkts_burst[i];\n int ret = write(tap_fd, rte_pktmbuf_mtod(m, void*),\n\n rte_pktmbuf_data_len(m));\n rte_pktmbuf_free(m);\n if (unlikely(ret<0))\n lcore_stats[lcore_id].dropped++;\n else\n lcore_stats[lcore_id].tx++;\n }\n }\n\nFor the other case that reads from a TAP interface and writes to a NIC port,\npackets are retrieved by doing a read() from the file descriptor of the appropriate TAP interface.\nThis fills in the data into the mbuf, then other fields are set manually.\nThe packet can then be transmitted as normal.\n\n.. code-block:: c\n\n /* Loop forever reading from tap and writing to NIC */\n\n for (;;) {\n int ret;\n struct rte_mbuf *m = rte_pktmbuf_alloc(pktmbuf_pool);\n\n if (m == NULL)\n continue;\n\n ret = read(tap_fd, m->pkt.data, MAX_PACKET_SZ); lcore_stats[lcore_id].rx++;\n if (unlikely(ret < 0)) {\n FATAL_ERROR(\"Reading from %s interface failed\", tap_name);\n }\n\n m->pkt.nb_segs = 1;\n m->pkt.next = NULL;\n m->pkt.data_len = (uint16_t)ret;\n\n ret = rte_eth_tx_burst(port_ids[lcore_id], 0, &m, 1);\n if (unlikely(ret < 1)) {\n rte_pktmuf_free(m);\n lcore_stats[lcore_id].dropped++;\n }\n else {\n lcore_stats[lcore_id].tx++;\n }\n }\n\nTo set up loops for measuring throughput, TAP interfaces can be connected using bridging.\nThe steps to do this are described in the section that follows.\n\nManaging TAP Interfaces and Bridges\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe Exception Path sample application creates TAP interfaces with names of the format tap_dpdk_nn,\nwhere nn is the lcore ID. These TAP interfaces need to be configured for use:\n\n.. code-block:: console\n\n ifconfig tap_dpdk_00 up\n\nTo set up a bridge between two interfaces so that packets sent to one interface can be read from another,\nuse the brctl tool:\n\n.. code-block:: console\n\n brctl addbr \"br0\"\n brctl addif br0 tap_dpdk_00\n brctl addif br0 tap_dpdk_03\n ifconfig br0 up\n\nThe TAP interfaces created by this application exist only when the application is running,\nso the steps above need to be repeated each time the application is run.\nTo avoid this, persistent TAP interfaces can be created using openvpn:\n\n.. code-block:: console\n\n openvpn --mktun --dev tap_dpdk_00\n\nIf this method is used, then the steps above have to be done only once and\nthe same TAP interfaces can be reused each time the application is run.\nTo remove bridges and persistent TAP interfaces, the following commands are used:\n\n.. code-block:: console\n\n ifconfig br0 down\n brctl delbr br0\n openvpn --rmtun --dev tap_dpdk_00\n\n" }, { "path": "doc/guides/sample_app_ug/hello_world.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nHello World Sample Application\n==============================\n\nThe Hello World sample application is an example of the simplest DPDK application that can be written.\nThe application simply prints an \"helloworld\" message on every enabled lcore.\n\nCompiling the Application\n-------------------------\n\n#. Go to the example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/helloworld\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the *DPDK Getting Started* Guide for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nTo run the example in a linuxapp environment:\n\n.. code-block:: console\n\n $ ./build/helloworld -c f -n 4\n\nRefer to *DPDK Getting Started Guide* for general information on running applications\nand the Environment Abstraction Layer (EAL) options.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of code.\n\nEAL Initialization\n~~~~~~~~~~~~~~~~~~\n\nThe first task is to initialize the Environment Abstraction Layer (EAL).\nThis is done in the main() function using the following code:\n\n.. code-block:: c\n\n int\n\n main(int argc, char **argv)\n\n {\n ret = rte_eal_init(argc, argv);\n if (ret < 0)\n rte_panic(\"Cannot init EAL\\n\");\n\nThis call finishes the initialization process that was started before main() is called (in case of a Linuxapp environment).\nThe argc and argv arguments are provided to the rte_eal_init() function.\nThe value returned is the number of parsed arguments.\n\nStarting Application Unit Lcores\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nOnce the EAL is initialized, the application is ready to launch a function on an lcore.\nIn this example, lcore_hello() is called on every available lcore.\nThe following is the definition of the function:\n\n.. code-block:: c\n\n static int\n lcore_hello( attribute ((unused)) void *arg)\n {\n unsigned lcore_id;\n\n lcore_id = rte_lcore_id();\n printf(\"hello from core %u\\n\", lcore_id);\n return 0;\n }\n\nThe code that launches the function on each lcore is as follows:\n\n.. code-block:: c\n\n /* call lcore_hello() on every slave lcore */\n\n RTE_LCORE_FOREACH_SLAVE(lcore_id) {\n rte_eal_remote_launch(lcore_hello, NULL, lcore_id);\n }\n\n /* call it on master lcore too */\n\n lcore_hello(NULL);\n\nThe following code is equivalent and simpler:\n\n.. code-block:: c\n\n rte_eal_mp_remote_launch(lcore_hello, NULL, CALL_MASTER);\n\nRefer to the *DPDK API Reference* for detailed information on the rte_eal_mp_remote_launch() function.\n" }, { "path": "doc/guides/sample_app_ug/index.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nSample Applications User Guide\n==============================\n\n|today|\n\n**Contents**\n\n.. toctree::\n :maxdepth: 2\n :numbered:\n\n intro\n cmd_line\n exception_path\n hello_world\n skeleton\n rxtx_callbacks\n ip_frag\n ipv4_multicast\n ip_reassembly\n kernel_nic_interface\n l2_forward_job_stats\n l2_forward_real_virtual\n l3_forward\n l3_forward_power_man\n l3_forward_access_ctrl\n l3_forward_virtual\n link_status_intr\n load_balancer\n multi_process\n qos_metering\n qos_scheduler\n intel_quickassist\n quota_watermark\n timer\n packet_ordering\n vmdq_dcb_forwarding\n vhost\n netmap_compatibility\n ip_pipeline\n test_pipeline\n dist_app\n vm_power_management\n tep_termination\n proc_info\n\n**Figures**\n\n:numref:`figure_exception_path_example` :ref:`figure_exception_path_example`\n\n:numref:`figure_kernel_nic` :ref:`figure_kernel_nic`\n\n:numref:`figure_l2_fwd_benchmark_setup_jobstats` :ref:`figure_l2_fwd_benchmark_setup_jobstats`\n\n:numref:`figure_l2_fwd_virtenv_benchmark_setup_jobstats` :ref:`figure_l2_fwd_virtenv_benchmark_setup_jobstats`\n\n:numref:`figure_l2_fwd_benchmark_setup` :ref:`figure_l2_fwd_benchmark_setup`\n\n:numref:`figure_l2_fwd_virtenv_benchmark_setup` :ref:`figure_l2_fwd_virtenv_benchmark_setup`\n\n:numref:`figure_ipv4_acl_rule` :ref:`figure_ipv4_acl_rule`\n\n:numref:`figure_example_rules` :ref:`figure_example_rules`\n\n:numref:`figure_load_bal_app_arch` :ref:`figure_load_bal_app_arch`\n\n:numref:`figure_sym_multi_proc_app` :ref:`figure_sym_multi_proc_app`\n\n:numref:`figure_client_svr_sym_multi_proc_app` :ref:`figure_client_svr_sym_multi_proc_app`\n\n:numref:`figure_master_slave_proc` :ref:`figure_master_slave_proc`\n\n:numref:`figure_slave_proc_recov` :ref:`figure_slave_proc_recov`\n\n:numref:`figure_qos_sched_app_arch` :ref:`figure_qos_sched_app_arch`\n\n:numref:`figure_quickassist_block_diagram` :ref:`figure_quickassist_block_diagram`\n\n:numref:`figure_pipeline_overview` :ref:`figure_pipeline_overview`\n\n:numref:`figure_ring_pipeline_perf_setup` :ref:`figure_ring_pipeline_perf_setup`\n\n:numref:`figure_threads_pipelines` :ref:`figure_threads_pipelines`\n\n:numref:`figure_vmdq_dcb_example` :ref:`figure_vmdq_dcb_example`\n\n:numref:`figure_qemu_virtio_net` :ref:`figure_qemu_virtio_net`\n\n:numref:`figure_virtio_linux_vhost` :ref:`figure_virtio_linux_vhost`\n\n:numref:`figure_vhost_net_arch` :ref:`figure_vhost_net_arch`\n\n:numref:`figure_vhost_net_sample_app` :ref:`figure_vhost_net_sample_app`\n\n:numref:`figure_tx_dpdk_testpmd` :ref:`figure_tx_dpdk_testpmd`\n\n:numref:`figure_test_pipeline_app` :ref:`figure_test_pipeline_app`\n\n:numref:`figure_dist_perf` :ref:`figure_dist_perf`\n\n:numref:`figure_dist_app` :ref:`figure_dist_app`\n\n:numref:`figure_vm_power_mgr_highlevel` :ref:`figure_vm_power_mgr_highlevel`\n\n:numref:`figure_vm_power_mgr_vm_request_seq` :ref:`figure_vm_power_mgr_vm_request_seq`\n:numref:`figure_overlay_networking` :ref:`figure_overlay_networking`\n:numref:`figure_tep_termination_arch` :ref:`figure_tep_termination_arch`\n\n**Tables**\n\n:numref:`table_qos_metering_1` :ref:`table_qos_metering_1`\n\n:numref:`table_qos_scheduler_1` :ref:`table_qos_scheduler_1`\n\n:numref:`table_test_pipeline_1` :ref:`table_test_pipeline_1`\n" }, { "path": "doc/guides/sample_app_ug/intel_quickassist.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIntel® QuickAssist Technology Sample Application\n================================================\n\nThis sample application demonstrates the use of the cryptographic operations provided\nby the Intel® QuickAssist Technology from within the DPDK environment.\nTherefore, building and running this application requires having both the DPDK and\nthe QuickAssist Technology Software Library installed, as well as at least one\nIntel® QuickAssist Technology hardware device present in the system.\n\nFor this sample application, there is a dependency on either of:\n\n* Intel® Communications Chipset 8900 to 8920 Series Software for Linux* package\n\n* Intel® Communications Chipset 8925 to 8955 Series Software for Linux* package\n\nOverview\n--------\n\nAn overview of the application is provided in :numref:`figure_quickassist_block_diagram`.\nFor simplicity, only two NIC ports and one Intel® QuickAssist Technology device are shown in this diagram,\nalthough the number of NIC ports and Intel® QuickAssist Technology devices can be different.\n\n.. _figure_quickassist_block_diagram:\n\n.. figure:: img/quickassist_block_diagram.*\n\n Intel® QuickAssist Technology Application Block Diagram\n\n\nThe application allows the configuration of the following items:\n\n* Number of NIC ports\n\n* Number of logical cores (lcores)\n\n* Mapping of NIC RX queues to logical cores\n\nEach lcore communicates with every cryptographic acceleration engine in the system through a pair of dedicated input - output queues.\nEach lcore has a dedicated NIC TX queue with every NIC port in the system.\nTherefore, each lcore reads packets from its NIC RX queues and cryptographic accelerator output queues and\nwrites packets to its NIC TX queues and cryptographic accelerator input queues.\n\nEach incoming packet that is read from a NIC RX queue is either directly forwarded to its destination NIC TX port (forwarding path)\nor first sent to one of the Intel® QuickAssist Technology devices for either encryption or decryption\nbefore being sent out on its destination NIC TX port (cryptographic path).\n\nThe application supports IPv4 input packets only.\nFor each input packet, the decision between the forwarding path and\nthe cryptographic path is taken at the classification stage based on the value of the IP source address field read from the input packet.\nAssuming that the IP source address is A.B.C.D, then if:\n\n* D = 0: the forwarding path is selected (the packet is forwarded out directly)\n\n* D = 1: the cryptographic path for encryption is selected (the packet is first encrypted and then forwarded out)\n\n* D = 2: the cryptographic path for decryption is selected (the packet is first decrypted and then forwarded out)\n\nFor the cryptographic path cases (D = 1 or D = 2), byte C specifies the cipher algorithm and\nbyte B the cryptographic hash algorithm to be used for the current packet.\nByte A is not used and can be any value.\nThe cipher and cryptographic hash algorithms supported by this application are listed in the crypto.h header file.\n\nFor each input packet, the destination NIC TX port is decided at the forwarding stage (executed after the cryptographic stage,\nif enabled for the packet) by looking at the RX port index of the dst_ports[ ] array,\nwhich was initialized at startup, being the outport the adjacent enabled port.\nFor example, if ports 1,3,5 and 6 are enabled, for input port 1, outport port will be 3 and vice versa,\nand for input port 5, output port will be 6 and vice versa.\n\nFor the cryptographic path, it is the payload of the IPv4 packet that is encrypted or decrypted.\n\nSetup\n~~~~~\n\nBuilding and running this application requires having both the DPDK package and\nthe QuickAssist Technology Software Library installed,\nas well as at least one Intel® QuickAssist Technology hardware device present in the system.\n\nFor more details on how to build and run DPDK and Intel® QuickAssist Technology applications,\nplease refer to the following documents:\n\n* *DPDK Getting Started Guide*\n\n* Intel® Communications Chipset 8900 to 8920 Series Software for Linux* Getting Started Guide (440005)\n\n* Intel® Communications Chipset 8925 to 8955 Series Software for Linux* Getting Started Guide (523128)\n\nFor more details on the actual platforms used to validate this application, as well as performance numbers,\nplease refer to the Test Report, which is accessible by contacting your Intel representative.\n\nBuilding the Application\n------------------------\n\nSteps to build the application:\n\n#. Set up the following environment variables:\n\n .. code-block:: console\n\n export RTE_SDK=\n export ICP_ROOT=\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n Refer to the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n cd ${RTE_SDK}/examples/dpdk_qat\n make\n\nRunning the Application\n-----------------------\n\nIntel® QuickAssist Technology Configuration Files\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe Intel® QuickAssist Technology configuration files used by the application are located in the config_files folder in the application folder.\nThere following sets of configuration files are included in the DPDK package:\n\n* Stargo CRB (single CPU socket): located in the stargo folder\n\n * dh89xxcc_qa_dev0.conf\n\n* Shumway CRB (dual CPU socket): located in the shumway folder\n\n * dh89xxcc_qa_dev0.conf\n\n * dh89xxcc_qa_dev1.conf\n\n* Coleto Creek: located in the coleto folder\n\n * dh895xcc_qa_dev0.conf\n\nThe relevant configuration file(s) must be copied to the /etc/ directory.\n\nPlease note that any change to these configuration files requires restarting the Intel®\nQuickAssist Technology driver using the following command:\n\n.. code-block:: console\n\n # service qat_service restart\n\nRefer to the following documents for information on the Intel® QuickAssist Technology configuration files:\n\n* Intel® Communications Chipset 8900 to 8920 Series Software Programmer's Guide\n\n* Intel® Communications Chipset 8925 to 8955 Series Software Programmer's Guide\n\n* Intel® Communications Chipset 8900 to 8920 Series Software for Linux* Getting Started Guide.\n\n* Intel® Communications Chipset 8925 to 8955 Series Software for Linux* Getting Started Guide.\n\nTraffic Generator Setup and Application Startup\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe application has a number of command line options:\n\n dpdk_qat [EAL options] -- -p PORTMASK [--no-promisc] [--config '(port,queue,lcore)[,(port,queue,lcore)]']\n\nwhere,\n\n* -p PORTMASK: Hexadecimal bitmask of ports to configure\n\n* --no-promisc: Disables promiscuous mode for all ports,\n so that only packets with the Ethernet MAC destination address set to the Ethernet address of the port are accepted.\n By default promiscuous mode is enabled so that packets are accepted regardless of the packet's Ethernet MAC destination address.\n\n* --config'(port,queue,lcore)[,(port,queue,lcore)]': determines which queues from which ports are mapped to which cores.\n\nRefer to Chapter 10 , \"L3 Forwarding Sample Application\" for more detailed descriptions of the --config command line option.\n\nAs an example, to run the application with two ports and two cores,\nwhich are using different Intel® QuickAssist Technology execution engines,\nperforming AES-CBC-128 encryption with AES-XCBC-MAC-96 hash, the following settings can be used:\n\n* Traffic generator source IP address: 0.9.6.1\n\n* Command line:\n\n .. code-block:: console\n\n ./build/dpdk_qat -c 0xff -n 2 -- -p 0x3 --config '(0,0,1),(1,0,2)'\n\nRefer to the *DPDK Test Report* for more examples of traffic generator setup and the application startup command lines.\nIf no errors are generated in response to the startup commands, the application is running correctly.\n" }, { "path": "doc/guides/sample_app_ug/intro.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIntroduction\n============\n\nThis document describes the sample applications that are included in the Data Plane Development Kit (DPDK).\nEach chapter describes a sample application that showcases specific functionality and\nprovides instructions on how to compile, run and use the sample application.\n\nDocumentation Roadmap\n---------------------\n\nThe following is a list of DPDK documents in suggested reading order:\n\n* **Release Notes** : Provides release-specific information, including supported features,\n limitations, fixed issues, known issues and so on.\n Also, provides the answers to frequently asked questions in FAQ format.\n\n* **Getting Started Guides** : Describes how to install and\n configure the DPDK software for your operating system;\n designed to get users up and running quickly with the software.\n\n* **Programmer's Guide:** Describes:\n\n * The software architecture and how to use it (through examples),\n specifically in a Linux* application (linuxapp) environment.\n\n * The content of the DPDK, the build system\n (including the commands that can be used in the root DPDK Makefile to build the development kit and an application)\n \tand guidelines for porting an application.\n\n * Optimizations used in the software and those that should be considered for new development\n\nA glossary of terms is also provided.\n\n* **API Reference** : Provides detailed information about DPDK functions,\n data structures and other programming constructs.\n\n* **Sample Applications User Guide** : Describes a set of sample applications.\n Each chapter describes a sample application that showcases specific functionality and\n provides instructions on how to compile, run and use the sample application.\n" }, { "path": "doc/guides/sample_app_ug/ip_frag.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIP Fragmentation Sample Application\n===================================\n\nThe IPv4 Fragmentation application is a simple example of packet processing\nusing the Data Plane Development Kit (DPDK).\nThe application does L3 forwarding with IPv4 and IPv6 packet fragmentation.\n\nOverview\n--------\n\nThe application demonstrates the use of zero-copy buffers for packet fragmentation.\nThe initialization and run-time paths are very similar to those of the L2 forwarding application\n(see Chapter 9 \"L2 Forwarding Simple Application (in Real and Virtualized Environments)\" for more information).\nThis guide highlights the differences between the two applications.\n\nThere are three key differences from the L2 Forwarding sample application:\n\n* The first difference is that the IP Fragmentation sample application makes use of indirect buffers.\n\n* The second difference is that the forwarding decision is taken\n based on information read from the input packet's IP header.\n\n* The third difference is that the application differentiates between\n IP and non-IP traffic by means of offload flags.\n\nThe Longest Prefix Match (LPM for IPv4, LPM6 for IPv6) table is used to store/lookup an outgoing port number,\nassociated with that IP address.\nAny unmatched packets are forwarded to the originating port.\n\nBy default, input frame sizes up to 9.5 KB are supported.\nBefore forwarding, the input IP packet is fragmented to fit into the \"standard\" Ethernet* v2 MTU (1500 bytes).\n\nBuilding the Application\n------------------------\n\nTo build the application:\n\n#. Go to the sample application directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/ip_fragmentation\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\nSee the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nThe LPM object is created and loaded with the pre-configured entries read from\nglobal l3fwd_ipv4_route_array and l3fwd_ipv6_route_array tables.\nFor each input packet, the packet forwarding decision\n(that is, the identification of the output interface for the packet) is taken as a result of LPM lookup.\nIf the IP packet size is greater than default output MTU,\nthen the input packet is fragmented and several fragments are sent via the output interface.\n\nApplication usage:\n\n.. code-block:: console\n\n ./build/ip_fragmentation [EAL options] -- -p PORTMASK [-q NQ]\n\nwhere:\n\n* -p PORTMASK is a hexadecimal bitmask of ports to configure\n\n* -q NQ is the number of queue (=ports) per lcore (the default is 1)\n\nTo run the example in linuxapp environment with 2 lcores (2,4) over 2 ports(0,2) with 1 RX queue per lcore:\n\n.. code-block:: console\n\n ./build/ip_fragmentation -c 0x14 -n 3 -- -p 5\n EAL: coremask set to 14\n EAL: Detected lcore 0 on socket 0\n EAL: Detected lcore 1 on socket 1\n EAL: Detected lcore 2 on socket 0\n EAL: Detected lcore 3 on socket 1\n EAL: Detected lcore 4 on socket 0\n ...\n\n Initializing port 0 on lcore 2... Address:00:1B:21:76:FA:2C, rxq=0 txq=2,0 txq=4,1\n done: Link Up - speed 10000 Mbps - full-duplex\n Skipping disabled port 1\n Initializing port 2 on lcore 4... Address:00:1B:21:5C:FF:54, rxq=0 txq=2,0 txq=4,1\n done: Link Up - speed 10000 Mbps - full-duplex\n Skipping disabled port 3IP_FRAG: Socket 0: adding route 100.10.0.0/16 (port 0)\n IP_FRAG: Socket 0: adding route 100.20.0.0/16 (port 1)\n ...\n IP_FRAG: Socket 0: adding route 0101:0101:0101:0101:0101:0101:0101:0101/48 (port 0)\n IP_FRAG: Socket 0: adding route 0201:0101:0101:0101:0101:0101:0101:0101/48 (port 1)\n ...\n IP_FRAG: entering main loop on lcore 4\n IP_FRAG: -- lcoreid=4 portid=2\n IP_FRAG: entering main loop on lcore 2\n IP_FRAG: -- lcoreid=2 portid=0\n\nTo run the example in linuxapp environment with 1 lcore (4) over 2 ports(0,2) with 2 RX queues per lcore:\n\n.. code-block:: console\n\n ./build/ip_fragmentation -c 0x10 -n 3 -- -p 5 -q 2\n\nTo test the application, flows should be set up in the flow generator that match the values in the\nl3fwd_ipv4_route_array and/or l3fwd_ipv6_route_array table.\n\nThe default l3fwd_ipv4_route_array table is:\n\n.. code-block:: c\n\n struct l3fwd_ipv4_route l3fwd_ipv4_route_array[] = {\n {IPv4(100, 10, 0, 0), 16, 0},\n {IPv4(100, 20, 0, 0), 16, 1},\n {IPv4(100, 30, 0, 0), 16, 2},\n {IPv4(100, 40, 0, 0), 16, 3},\n {IPv4(100, 50, 0, 0), 16, 4},\n {IPv4(100, 60, 0, 0), 16, 5},\n {IPv4(100, 70, 0, 0), 16, 6},\n {IPv4(100, 80, 0, 0), 16, 7},\n };\n\nThe default l3fwd_ipv6_route_array table is:\n\n.. code-block:: c\n\n struct l3fwd_ipv6_route l3fwd_ipv6_route_array[] = {\n {{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 0},\n {{2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 1},\n {{3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 2},\n {{4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 3},\n {{5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 4},\n {{6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 5},\n {{7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 6},\n {{8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 7},\n };\n\nFor example, for the input IPv4 packet with destination address: 100.10.1.1 and packet length 9198 bytes,\nseven IPv4 packets will be sent out from port #0 to the destination address 100.10.1.1:\nsix of those packets will have length 1500 bytes and one packet will have length 318 bytes.\nIP Fragmentation sample application provides basic NUMA support\nin that all the memory structures are allocated on all sockets that have active lcores on them.\n\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications\nand the Environment Abstraction Layer (EAL) options.\n" }, { "path": "doc/guides/sample_app_ug/ip_pipeline.rst", "content": ".. BSD LICENSE\n Copyright(c) 2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nInternet Protocol (IP) Pipeline Application\n===========================================\n\nApplication overview\n--------------------\n\nThe *Internet Protocol (IP) Pipeline* application is intended to be a vehicle for rapid development of packet processing\napplications running on multi-core CPUs.\n\nThe application provides a library of reusable functional blocks called pipelines.\nThese pipelines can be seen as prefabricated blocks that can be instantiated and inter-connected through packet queues\nto create complete applications (super-pipelines).\n\nPipelines are created and inter-connected through the application configuration file.\nBy using different configuration files, different applications are effectively created, therefore this application\ncan be seen as an application generator.\nThe configuration of each pipeline can be updated at run-time through the application Command Line Interface (CLI).\n\nMain application components are:\n\n**A Library of reusable pipelines**\n\n * Each pipeline represents a functional block, e.g. flow classification, firewall, routing, master, etc.\n\n * Each pipeline type can be instantiated several times in the same application, which each instance configured\n separately and mapped to a single CPU core.\n Each CPU core can run one or several pipeline instances, which can be of same or different type.\n\n * Pipeline instances are inter-connected through packet queues (for packet processing) and message queues\n (for run-time configuration).\n\n * Pipelines are implemented using DPDK Packet Framework.\n\n * More pipeline types can always be built and added to the existing pipeline types.\n\n**The Configuration file**\n\n * The configuration file defines the application structure.\n By using different configuration files, different applications are created.\n\n * All the application resources are created and configured through the application configuration file:\n pipeline instances, buffer pools, links (i.e. network interfaces), hardware device RX/TX queues,\n software queues, traffic manager devices, EAL startup arguments, etc.\n\n * The configuration file syntax is “define by reference”, meaning that resources are defined as they are referenced.\n First time a resource name is detected, it is registered with default parameters.\n Optionally, the resource parameters can be further refined through a configuration file section dedicated to\n that resource.\n\n * Command Line Interface (CLI)\n\n**Global CLI commands: link configuration, etc.**\n\n * Common pipeline CLI commands: ping (keep-alive), statistics, etc.\n\n * Pipeline type specific CLI commands: used to configure instances of specific pipeline type.\n These commands are registered with the application when the pipeline type is registered.\n For example, the commands for routing pipeline instances include: route add, route delete, route list, etc.\n\n * CLI commands can be grouped into scripts that can be invoked at initialization and at runtime.\n\n\nDesign goals\n------------\n\n\nRapid development\n~~~~~~~~~~~~~~~~~\n\nThis application enables rapid development through quick connectivity of standard components called pipelines.\nThese components are built using DPDK Packet Framework and encapsulate packet processing features at different levels:\nports, tables, actions, pipelines and complete applications.\n\nPipeline instances are instantiated, configured and inter-connected through low complexity configuration files loaded\nduring application initialization.\nEach pipeline instance is mapped to a single CPU core, with each CPU core able to run one or multiple pipeline\ninstances of same or different types. By loading a different configuration file, a different application is\neffectively started.\n\n\nFlexibility\n~~~~~~~~~~~\n\nEach packet processing application is typically represented as a chain of functional stages which is often called\nthe functional pipeline of the application.\nThese stages are mapped to CPU cores to create chains of CPU cores (pipeline model), clusters of CPU cores\n(run-to-completion model) or chains of clusters of CPU cores (hybrid model).\n\nThis application allows all the above programming models.\nBy applying changes to the configuration file, the application provides the flexibility to reshuffle its\nbuilding blocks in different ways until the configuration providing the best performance is identified.\n\n\nMove pipelines around\n^^^^^^^^^^^^^^^^^^^^^\n\nThe mapping of pipeline instances to CPU cores can be reshuffled through the configuration file.\nOne or several pipeline instances can be mapped to the same CPU core.\n\n.. _figure_ip_pipelines_1:\n\n.. figure:: img/ip_pipelines_1.*\n\n Example of moving pipeline instances across different CPU cores\n\n\nMove tables around\n^^^^^^^^^^^^^^^^^^\n\nThere is some degree of flexibility for moving tables from one pipeline instance to another.\nBased on the configuration arguments passed to each pipeline instance in the configuration file, specific tables\ncan be enabled or disabled.\nThis way, a specific table can be “moved” from pipeline instance A to pipeline instance B by simply disabling its\nassociated functionality for pipeline instance A while enabling it for pipeline instance B.\n\nDue to requirement to have simple syntax for the configuration file, moving tables across different pipeline\ninstances is not as flexible as the mapping of pipeline instances to CPU cores, or mapping actions to pipeline tables.\nComplete flexibility in moving tables from one pipeline to another could be achieved through a complex pipeline\ndescription language that would detail the structural elements of the pipeline (ports, tables and actions) and\ntheir connectivity, resulting in complex syntax for the configuration file, which is not acceptable.\nGood configuration file readability through simple syntax is preferred.\n\n*Example*: the IP routing pipeline can run the routing function only (with ARP function run by a different\npipeline instance), or it can run both the routing and ARP functions as part of the same pipeline instance.\n\n\n.. _figure_ip_pipelines_2:\n\n.. figure:: img/ip_pipelines_2.*\n\n Example of moving tables across different pipeline instances\n\n\nMove actions around\n^^^^^^^^^^^^^^^^^^^\n\nWhen it makes sense, packet processing actions can be moved from one pipeline instance to another.\nBased on the configuration arguments passed to each pipeline instance in the configuration file, specific actions\ncan be enabled or disabled.\nThis way, a specific action can be \"moved\" from pipeline instance A to pipeline instance B by simply disabling its\nassociated functionality for pipeline instance A while enabling it for pipeline instance B.\n\n*Example*: The flow actions of accounting, traffic metering, application identification, NAT, etc can be run as part\nof the flow classification pipeline instance or split across several flow actions pipeline instances, depending on\nthe number of flow instances and their compute requirements.\n\n\n.. _figure_ip_pipelines_3:\n\n.. figure:: img/ip_pipelines_3.*\n\n Example of moving actions across different tables and pipeline instances\n\n\nPerformance\n~~~~~~~~~~~\n\nPerformance of the application is the highest priority requirement.\nFlexibility is not provided at the expense of performance.\n\nThe purpose of flexibility is to provide an incremental development methodology that allows monitoring the\nperformance evolution:\n\n* Apply incremental changes in the configuration (e.g. mapping on pipeline instances to CPU cores)\n in order to identify the configuration providing the best performance for a given application;\n\n* Add more processing incrementally (e.g. by enabling more actions for specific pipeline instances) until\n the application is feature complete while checking the performance impact at each step.\n\n\nDebug capabilities\n~~~~~~~~~~~~~~~~~~\n\nThe application provides a significant set of debug capabilities:\n\n* Command Line Interface (CLI) support for statistics polling: pipeline instance ping (keep-alive checks),\n pipeline instance statistics per input port/output port/table, link statistics, etc;\n\n* Logging: Turn on/off application log messages based on priority level;\n\nRunning the application\n-----------------------\n\nThe application startup command line is::\n\n ip_pipeline [-f CONFIG_FILE] [-s SCRIPT_FILE] -p PORT_MASK [-l LOG_LEVEL]\n\nThe application startup arguments are:\n\n``-f CONFIG_FILE``\n\n * Optional: Yes\n\n * Default: ``./config/ip_pipeline.cfg``\n\n * Argument: Path to the configuration file to be loaded by the application.\n Please refer to the :ref:`ip_pipeline_configuration_file` for details on how to write the configuration file.\n\n``-s SCRIPT_FILE``\n\n * Optional: Yes\n\n * Default: Not present\n\n * Argument: Path to the CLI script file to be run by the master pipeline at application startup.\n No CLI script file will be run at startup of this argument is not present.\n\n``-p PORT_MASK``\n\n * Optional: No\n\n * Default: N/A\n\n * Argument: Hexadecimal mask of NIC port IDs to be used by the application.\n First port enabled in this mask will be referenced as LINK0 as part of the application configuration file,\n next port as LINK1, etc.\n\n``-l LOG_LEVEL``\n\n * Optional: Yes\n\n * Default: 1 (High priority)\n\n * Argument: Log level to determine which application messages are to be printed to standard output.\n Available log levels are: 0 (None), 1 (High priority), 2 (Low priority).\n Only application messages whose priority is higher than or equal to the application log level will be printed.\n\n\nApplication stages\n------------------\n\n\nConfiguration\n~~~~~~~~~~~~~\n\nDuring this stage, the application configuration file is parsed and its content is loaded into the application data\nstructures.\nIn case of any configuration file parse error, an error message is displayed and the application is terminated.\nPlease refer to the :ref:`ip_pipeline_configuration_file` for a description of the application configuration file format.\n\n\nConfiguration checking\n~~~~~~~~~~~~~~~~~~~~~~\n\nIn the absence of any parse errors, the loaded content of application data structures is checked for overall consistency.\nIn case of any configuration check error, an error message is displayed and the application is terminated.\n\n\nInitialization\n~~~~~~~~~~~~~~\n\nDuring this stage, the application resources are initialized and the handles to access them are saved into the\napplication data structures.\nIn case of any initialization error, an error message is displayed and the application is terminated.\n\nThe typical resources to be initialized are: pipeline instances, buffer pools, links (i.e. network interfaces),\nhardware device RX/TX queues, software queues, traffic management devices, etc.\n\n\n.. _ip_pipeline_runtime:\n\nRun-time\n~~~~~~~~\n\nEach CPU core runs the pipeline instances assigned to it in time sharing mode and in round robin order:\n\n1. *Packet processing task*: The pipeline run-time code is typically a packet *processing* task built on top of\n DPDK Packet Framework rte_pipeline library, which reads bursts of packets from the pipeline input ports,\n performs table lookups and executes the identified actions for all tables in the pipeline, with packet\n eventually written to pipeline output ports or dropped.\n\n2. *Message handling task*: Each CPU core will also periodically execute the *message handling* code of each\n of the pipelines mapped to it.\n The pipeline message handling code is processing the messages that are pending in the pipeline input message\n queues, which are typically sent by the master CPU core for the on-the-fly pipeline configuration: check\n that pipeline is still alive (ping), add/delete entries in the pipeline tables, get statistics, etc.\n The frequency of executing the message handling code is usually much smaller than the frequency of executing\n the packet processing work.\n\nPlease refer to the :ref:`ip_pipeline_pipeline_section` for more details about the application pipeline module encapsulation.\n\n.. _ip_pipeline_configuration_file:\n\nConfiguration file syntax\n-------------------------\n\nSyntax overview\n~~~~~~~~~~~~~~~\n\nThe syntax of the configuration file is designed to be simple, which favors readability.\nThe configuration file is parsed using the DPDK library librte_cfgfile, which supports simple\n`INI file format `__ for configuration files.\n\nAs result, the configuration file is split into several sections, with each section containing one or more entries.\nThe scope of each entry is its section, and each entry specifies a variable that is assigned a specific value.\nAny text after the ``;`` character is considered a comment and is therefore ignored.\n\nThe following are application specific: number of sections, name of each section, number of entries of each section,\nname of the variables used for each section entry, the value format (e.g. signed/unsigned integer, string, etc)\nand range of each section entry variable.\n\nGeneric example of configuration file section:\n\n.. code-block:: ini\n\n []\n\n = \n\n ...\n\n = \n\n\nApplication resources present in the configuration file\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n.. _table_ip_pipelines_resource_name:\n\n.. tabularcolumns:: |p{4cm}|p{6cm}|p{6cm}|\n\n.. table:: Application resource names in the configuration file\n\n +--------------------------+-----------------------------+-------------------------------------------------+\n | Resource type | Format | Examples |\n +==========================+=============================+=================================================+\n | Pipeline | ``PIPELINE`` | ``PIPELINE0``, ``PIPELINE1`` |\n +--------------------------+-----------------------------+-------------------------------------------------+\n | Mempool | ``MEMPOOL`` | ``MEMPOOL0``, ``MEMPOOL1`` |\n +--------------------------+-----------------------------+-------------------------------------------------+\n | Link (network interface) | ``LINK`` | ``LINK0``, ``LINK1`` |\n +--------------------------+-----------------------------+-------------------------------------------------+\n | Link RX queue | ``RXQ.`` | ``RXQ0.0``, ``RXQ1.5`` |\n +--------------------------+-----------------------------+-------------------------------------------------+\n | Link TX queue | ``TXQ.`` | ``TXQ0.0``, ``TXQ1.5`` |\n +--------------------------+-----------------------------+-------------------------------------------------+\n | Software queue | ``SWQ`` | ``SWQ0``, ``SWQ1`` |\n +--------------------------+-----------------------------+-------------------------------------------------+\n | Traffic Manager | ``TM`` | ``TM0``, ``TM1`` |\n +--------------------------+-----------------------------+-------------------------------------------------+\n | Source | ``SOURCE`` | ``SOURCE0``, ``SOURCE1`` |\n +--------------------------+-----------------------------+-------------------------------------------------+\n | Sink | ``SINK`` | ``SINK0``, ``SINK1`` |\n +--------------------------+-----------------------------+-------------------------------------------------+\n | Message queue | ``MSGQ`` | ``MSGQ0``, ``MSGQ1``, |\n | | ``MSGQ-REQ-PIPELINE`` | ``MSGQ-REQ-PIPELINE2``, ``MSGQ-RSP-PIPELINE2,`` |\n | | ``MSGQ-RSP-PIPELINE`` | ``MSGQ-REQ-CORE-s0c1``, ``MSGQ-RSP-CORE-s0c1`` |\n | | ``MSGQ-REQ-CORE-`` | |\n | | ``MSGQ-RSP-CORE-`` | |\n +--------------------------+-----------------------------+-------------------------------------------------+\n\n``LINK`` instances are created implicitly based on the ``PORT_MASK`` application startup argument.\n``LINK0`` is the first port enabled in the ``PORT_MASK``, port 1 is the next one, etc.\nThe LINK ID is different than the DPDK PMD-level NIC port ID, which is the actual position in the bitmask mentioned above.\nFor example, if bit 5 is the first bit set in the bitmask, then ``LINK0`` is having the PMD ID of 5.\nThis mechanism creates a contiguous LINK ID space and isolates the configuration file against changes in the board\nPCIe slots where NICs are plugged in.\n\n``RXQ``, ``TXQ`` and ``TM`` instances have the LINK ID as part of their name.\nFor example, ``RXQ2.1``, ``TXQ2.1`` and ``TM2`` are all associated with ``LINK2``.\n\n\nRules to parse the configuration file\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe main rules used to parse the configuration file are:\n\n1. Application resource name determines the type of resource based on the name prefix.\n\n *Example*: all software queues need to start with ``SWQ`` prefix, so ``SWQ0`` and ``SWQ5`` are valid software\n queue names.\n\n2. An application resource is defined by creating a configuration file section with its name.\n The configuration file section allows fine tuning on any of the resource parameters.\n Some resource parameters are mandatory, in which case it is required to have them specified as part of the\n section, while some others are optional, in which case they get assigned their default value when not present.\n\n *Example*: section ``SWQ0`` defines a software queue named SWQ0, whose parameters are detailed as part of this section.\n\n3. An application resource can also be defined by referencing it.\n Referencing a resource takes place by simply using its name as part of the value assigned to a variable in any\n configuration file section.\n In this case, the resource is registered with all its parameters having their default values.\n Optionally, a section with the resource name can be added to the configuration file to fine tune some or all\n of the resource parameters.\n\n *Example*: in section ``PIPELINE3``, variable ``pktq_in`` includes ``SWQ5`` as part of its list, which results\n in defining a software queue named ``SWQ5``; when there is no ``SWQ5`` section present in the configuration file,\n ``SWQ5`` gets registered with default parameters.\n\n\n.. _ip_pipeline_pipeline_section:\n\nPIPELINE section\n~~~~~~~~~~~~~~~~\n\n.. _table_ip_pipelines_pipeline_section_1:\n\n.. tabularcolumns:: |p{2.5cm}|p{7cm}|p{1.5cm}|p{1.5cm}|p{1.5cm}|\n\n.. table:: Configuration file PIPELINE section (1/2)\n\n +---------------+-----------------------------------------------------------+---------------+------------------------+----------------+\n | Section | Description | Optional | Range | Default value |\n +===============+===========================================================+===============+========================+================+\n | type | Pipeline type. Defines the functionality to be | NO | See \"List | N/A |\n | | executed. | | of pipeline types\" | |\n +---------------+-----------------------------------------------------------+---------------+------------------------+----------------+\n | core | CPU core to run the current pipeline. | YES | See \"CPU Core | CPU socket 0, |\n | | | | notation\" | core 0, |\n | | | | | hyper-thread 0 |\n +---------------+-----------------------------------------------------------+---------------+------------------------+----------------+\n | pktq_in | Packet queues to serve as input ports for the | YES | List of input | Empty list |\n | | current pipeline instance. The acceptable packet | | packet queue IDs | |\n | | queue types are: ``RXQ``, ``SWQ``, ``TM`` and ``SOURCE``. | | | |\n | | First device in this list is used as pipeline input port | | | |\n | | 0, second as pipeline input port 1, etc. | | | |\n +---------------+-----------------------------------------------------------+---------------+------------------------+----------------+\n | pktq_out | Packet queues to serve as output ports for the | YES | List of output | Empty list |\n | | current pipeline instance. The acceptable packet | | packet queue IDs. | |\n | | queue types are: ``TXQ``, ``SWQ``, ``TM`` and ``SINK``. | | | |\n | | First device in this list is used as pipeline output | | | |\n | | port 0, second as pipeline output port 1, etc. | | | |\n +---------------+-----------------------------------------------------------+---------------+------------------------+----------------+\n\n.. _table_ip_pipelines_pipeline_section_2:\n\n.. tabularcolumns:: |p{2.5cm}|p{7cm}|p{1.5cm}|p{1.5cm}|p{1.5cm}|\n\n.. table:: Configuration file PIPELINE section (2/2)\n\n +---------------+-----------------------------------------------------------+---------------+------------------------+----------------+\n | Section | Description | Optional | Range | Default value |\n +===============+===========================================================+===============+========================+================+\n | msgq_in | Input message queues. These queues contain | YES | List of message | Empty list |\n | | request messages that need to be handled by the | | queue IDs | |\n | | current pipeline instance. The type and format of | | | |\n | | request messages is defined by the pipeline type. | | | |\n | | For each pipeline instance, there is an input | | | |\n | | message queue defined implicitly, whose name is: | | | |\n | | ``MSGQ-REQ-``. This message queue | | | |\n | | should not be mentioned as part of msgq_in list. | | | |\n +---------------+-----------------------------------------------------------+---------------+------------------------+----------------+\n | msgq_out | Output message queues. These queues are used by | YES | List of message | Empty list |\n | | the current pipeline instance to write response | | queue IDs | |\n | | messages as result of request messages being | | | |\n | | handled. The type and format of response | | | |\n | | messages is defined by the pipeline type. | | | |\n | | For each pipeline instance, there is an output | | | |\n | | message queue defined implicitly, whose name is: | | | |\n | | ``MSGQ-RSP-``. This message queue | | | |\n | | should not be mentioned as part of msgq_out list. | | | |\n +---------------+-----------------------------------------------------------+---------------+------------------------+----------------+\n | timer_period | Time period, measured in milliseconds, | YES | milliseconds | 1 ms |\n | | for handling the input message queues. | | | |\n +---------------+-----------------------------------------------------------+---------------+------------------------+----------------+\n | | Arguments to be passed to the current pipeline | Depends on | Depends on | Depends on |\n | | instance. Format of the arguments, their type, | pipeline type | pipeline type | pipeline type |\n | | whether each argument is optional or mandatory | | | |\n | | and its default value (when optional) are defined | | | |\n | | by the pipeline type. | | | |\n | | The value of the arguments is applicable to the | | | |\n | | current pipeline instance only. | | | |\n +---------------+-----------------------------------------------------------+---------------+------------------------+----------------+\n\n\nCPU core notation\n^^^^^^^^^^^^^^^^^\n\nThe CPU Core notation is::\n\n ::= [s|S][c|C][h|H]\n\nFor example::\n\n CPU socket 0, core 0, hyper-thread 0: 0, c0, s0c0\n\n CPU socket 0, core 0, hyper-thread 1: 0h, c0h, s0c0h\n\n CPU socket 3, core 9, hyper-thread 1: s3c9h\n\n\nMEMPOOL section\n~~~~~~~~~~~~~~~\n\n.. _table_ip_pipelines_mempool_section:\n\n.. tabularcolumns:: |p{2.5cm}|p{6cm}|p{1.5cm}|p{1.5cm}|p{3cm}|\n\n.. table:: Configuration file MEMPOOL section\n\n +---------------+-----------------------------------------------+----------+----------+---------------------------+\n | Section | Description | Optional | Type | Default value |\n +===============+===============================================+==========+==========+===========================+\n | buffer_size | Buffer size (in bytes) for the current | YES | uint32_t | 2048 |\n | | buffer pool. | | | + sizeof(struct rte_mbuf) |\n | | | | | + HEADROOM |\n +---------------+-----------------------------------------------+----------+----------+---------------------------+\n | pool_size | Number of buffers in the current buffer pool. | YES | uint32_t | 32K |\n +---------------+-----------------------------------------------+----------+----------+---------------------------+\n | cache_size | Per CPU thread cache size (in number of | YES | uint32_t | 256 |\n | | buffers) for the current buffer pool. | | | |\n +---------------+-----------------------------------------------+----------+----------+---------------------------+\n | cpu | CPU socket ID where to allocate memory for | YES | uint32_t | 0 |\n | | the current buffer pool. | | | |\n +---------------+-----------------------------------------------+----------+----------+---------------------------+\n\n\nLINK section\n~~~~~~~~~~~~\n\n.. _table_ip_pipelines_link_section:\n\n.. tabularcolumns:: |p{3cm}|p{7cm}|p{1.5cm}|p{1.5cm}|p{2cm}|\n\n.. table:: Configuration file LINK section\n\n +-----------------+----------------------------------------------+----------+----------+-------------------+\n | Section entry | Description | Optional | Type | Default value |\n +=================+==============================================+==========+==========+===================+\n | arp_q | NIC RX queue where ARP packets should | YES | 0 .. 127 | 0 (default queue) |\n | | be filtered. | | | |\n +-----------------+----------------------------------------------+----------+----------+-------------------+\n | tcp_syn_local_q | NIC RX queue where TCP packets with SYN | YES | 0 .. 127 | 0 (default queue) |\n | | flag should be filtered. | | | |\n +-----------------+----------------------------------------------+----------+----------+-------------------+\n | ip_local_q | NIC RX queue where IP packets with local | YES | 0 .. 127 | 0 (default queue) |\n | | destination should be filtered. | | | |\n | | When TCP, UDP and SCTP local queues are | | | |\n | | defined, they take higher priority than this | | | |\n | | queue. | | | |\n +-----------------+----------------------------------------------+----------+----------+-------------------+\n | tcp_local_q | NIC RX queue where TCP packets with local | YES | 0 .. 127 | 0 (default queue) |\n | | destination should be filtered. | | | |\n +-----------------+----------------------------------------------+----------+----------+-------------------+\n | udp_local_q | NIC RX queue where TCP packets with local | YES | 0 .. 127 | 0 (default queue) |\n | | destination should be filtered. | | | |\n +-----------------+----------------------------------------------+----------+----------+-------------------+\n | sctp_local_q | NIC RX queue where TCP packets with local | YES | 0 .. 127 | 0 (default queue) |\n | | destination should be filtered. | | | |\n +-----------------+----------------------------------------------+----------+----------+-------------------+\n | promisc | Indicates whether current link should be | YES | YES/NO | YES |\n | | started in promiscuous mode. | | | |\n +-----------------+----------------------------------------------+----------+----------+-------------------+\n\n\nRXQ section\n~~~~~~~~~~~\n\n.. _table_ip_pipelines_rxq_section:\n\n.. tabularcolumns:: |p{3cm}|p{7cm}|p{1.5cm}|p{1.5cm}|p{2cm}|\n\n.. table:: Configuration file RXQ section\n\n +---------------+--------------------------------------------+----------+----------+---------------+\n | Section | Description | Optional | Type | Default value |\n +===============+============================================+==========+==========+===============+\n | mempool | Mempool to use for buffer allocation for | YES | uint32_t | MEMPOOL0 |\n | | current NIC RX queue. The mempool ID has | | | |\n | | to be associated with a valid instance | | | |\n | | defined in the mempool entry of the global | | | |\n | | section. | | | |\n +---------------+--------------------------------------------+----------+----------+---------------+\n | Size | NIC RX queue size (number of descriptors) | YES | uint32_t | 128 |\n +---------------+--------------------------------------------+----------+----------+---------------+\n | burst | Read burst size (number of descriptors) | YES | uint32_t | 32 |\n +---------------+--------------------------------------------+----------+----------+---------------+\n\n\nTXQ section\n~~~~~~~~~~~\n\n.. _table_ip_pipelines_txq_section:\n\n.. tabularcolumns:: |p{2.5cm}|p{7cm}|p{1.5cm}|p{2cm}|p{1.5cm}|\n\n.. table:: Configuration file TXQ section\n\n +---------------+----------------------------------------------+----------+------------------+---------------+\n | Section | Description | Optional | Type | Default value |\n +===============+==============================================+==========+==================+===============+\n | size | NIC TX queue size (number of descriptors) | YES | uint32_t | 512 |\n | | | | power of 2 | |\n | | | | > 0 | |\n +---------------+----------------------------------------------+----------+------------------+---------------+\n | burst | Write burst size (number of descriptors) | YES | uint32_t | 32 |\n | | | | power of 2 | |\n | | | | 0 < burst < size | |\n +---------------+----------------------------------------------+----------+------------------+---------------+\n | dropless | When dropless is set to NO, packets can be | YES | YES/NO | NO |\n | | dropped if not enough free slots are | | | |\n | | currently available in the queue, so the | | | |\n | | write operation to the queue is non- | | | |\n | | blocking. | | | |\n | | When dropless is set to YES, packets cannot | | | |\n | | be dropped if not enough free slots are | | | |\n | | currently available in the queue, so the | | | |\n | | write operation to the queue is blocking, as | | | |\n | | the write operation is retried until enough | | | |\n | | free slots become available and all the | | | |\n | | packets are successfully written to the | | | |\n | | queue. | | | |\n +---------------+----------------------------------------------+----------+------------------+---------------+\n | n_retries | Number of retries. Valid only when dropless | YES | uint32_t | 0 |\n | | is set to YES. When set to 0, it indicates | | | |\n | | unlimited number of retries. | | | |\n +---------------+----------------------------------------------+----------+------------------+---------------+\n\n\nSWQ section\n~~~~~~~~~~~\n\n.. _table_ip_pipelines_swq_section:\n\n.. tabularcolumns:: |p{2.5cm}|p{7cm}|p{1.5cm}|p{1.5cm}|p{1.5cm}|\n\n.. table:: Configuration file SWQ section\n\n +---------------+----------------------------------------------+----------+------------------+---------------+\n | Section | Description | Optional | Type | Default value |\n +===============+==============================================+==========+==================+===============+\n | size | Queue size (number of packets) | YES | uint32_t | 256 |\n | | | | power of 2 | |\n +---------------+----------------------------------------------+----------+------------------+---------------+\n | burst_read | Read burst size (number of packets) | YES | uint32_t | 32 |\n | | | | power of 2 | |\n | | | | 0 < burst < size | |\n +---------------+----------------------------------------------+----------+------------------+---------------+\n | burst_write | Write burst size (number of packets) | YES | uint32_t | 32 |\n | | | | power of 2 | |\n | | | | 0 < burst < size | |\n +---------------+----------------------------------------------+----------+------------------+---------------+\n | dropless | When dropless is set to NO, packets can be | YES | YES/NO | NO |\n | | dropped if not enough free slots are | | | |\n | | currently available in the queue, so the | | | |\n | | write operation to the queue is non- | | | |\n | | blocking. | | | |\n | | When dropless is set to YES, packets cannot | | | |\n | | be dropped if not enough free slots are | | | |\n | | currently available in the queue, so the | | | |\n | | write operation to the queue is blocking, as | | | |\n | | the write operation is retried until enough | | | |\n | | free slots become available and all the | | | |\n | | packets are successfully written to the | | | |\n | | queue. | | | |\n +---------------+----------------------------------------------+----------+------------------+---------------+\n | n_retries | Number of retries. Valid only when dropless | YES | uint32_t | 0 |\n | | is set to YES. When set to 0, it indicates | | | |\n | | unlimited number of retries. | | | |\n +---------------+----------------------------------------------+----------+------------------+---------------+\n | cpu | CPU socket ID where to allocate memory | YES | uint32_t | 0 |\n | | for this SWQ. | | | |\n +---------------+----------------------------------------------+----------+------------------+---------------+\n\n\nTM section\n~~~~~~~~~~\n\n.. _table_ip_pipelines_tm_section:\n\n.. tabularcolumns:: |p{2.5cm}|p{7cm}|p{1.5cm}|p{1.5cm}|p{1.5cm}|\n\n.. table:: Configuration file TM section\n\n +---------------+---------------------------------------------+----------+----------+---------------+\n | Section | Description | Optional | Type | Default value |\n +===============+=============================================+==========+==========+===============+\n | Cfg | File name to parse for the TM configuration | YES | string | tm_profile |\n | | to be applied. The syntax of this file is | | | |\n | | described in the examples/qos_sched DPDK | | | |\n | | application documentation. | | | |\n +---------------+---------------------------------------------+----------+----------+---------------+\n | burst_read | Read burst size (number of packets) | YES | uint32_t | 64 |\n +---------------+---------------------------------------------+----------+----------+---------------+\n | burst_write | Write burst size (number of packets) | YES | uint32_t | 32 |\n +---------------+---------------------------------------------+----------+----------+---------------+\n\n\nSOURCE section\n~~~~~~~~~~~~~~\n\n.. _table_ip_pipelines_source_section:\n\n.. tabularcolumns:: |p{2.5cm}|p{7cm}|p{1.5cm}|p{1.5cm}|p{2cm}|\n\n.. table:: Configuration file SOURCE section\n\n +---------------+---------------------------------------+----------+----------+---------------+\n | Section | Description | Optional | Type | Default value |\n +===============+=======================================+==========+==========+===============+\n | Mempool | Mempool to use for buffer allocation. | YES | uint32_t | MEMPOOL0 |\n +---------------+---------------------------------------+----------+----------+---------------+\n | Burst | Read burst size (number of packets) | | uint32_t | 32 |\n +---------------+---------------------------------------+----------+----------+---------------+\n\n\nSINK section\n~~~~~~~~~~~~\n\nCurrently, there are no parameters to be passed to a sink device, so\nSINK section is not allowed.\n\nMSGQ section\n~~~~~~~~~~~~\n\n.. _table_ip_pipelines_msgq_section:\n\n.. tabularcolumns:: |p{2.5cm}|p{7cm}|p{1.5cm}|p{1.5cm}|p{1.5cm}|\n\n.. table:: Configuration file MSGQ section\n\n +---------+--------------------------------------------+----------+------------+---------------+\n | Section | Description | Optional | Type | Default value |\n +=========+============================================+==========+============+===============+\n | size | Queue size (number of packets) | YES | uint32_t | 64 |\n | | | | != 0 | |\n | | | | power of 2 | |\n +---------+--------------------------------------------+----------+------------+---------------+\n | cpu | CPU socket ID where to allocate memory for | YES | uint32_t | 0 |\n | | the current queue. | | | |\n +---------+--------------------------------------------+----------+------------+---------------+\n\n\nEAL section\n~~~~~~~~~~~\n\nThe application generates the EAL parameters rather than reading them from the command line.\n\nThe CPU core mask parameter is generated based on the core entry of all PIPELINE sections.\nAll the other EAL parameters can be set from this section of the application configuration file.\n\n\nLibrary of pipeline types\n-------------------------\n\nPipeline module\n~~~~~~~~~~~~~~~\n\nA pipeline is a self-contained module that implements a packet processing function and is typically implemented on\ntop of the DPDK Packet Framework *librte_pipeline* library.\nThe application provides a run-time mechanism to register different pipeline types.\n\nDepending on the required configuration, each registered pipeline type (pipeline class) is instantiated one or\nseveral times, with each pipeline instance (pipeline object) assigned to one of the available CPU cores.\nEach CPU core can run one or more pipeline instances, which might be of same or different types.\nFor more information of the CPU core threading model, please refer to the :ref:`ip_pipeline_runtime` section.\n\n\nPipeline type\n^^^^^^^^^^^^^\n\nEach pipeline type is made up of a back-end and a front-end. The back-end represents the packet processing engine\nof the pipeline, typically implemented using the DPDK Packet Framework libraries, which reads packets from the\ninput packet queues, handles them and eventually writes them to the output packet queues or drops them.\nThe front-end represents the run-time configuration interface of the pipeline, which is exposed as CLI commands.\nThe front-end communicates with the back-end through message queues.\n\n.. _table_ip_pipelines_back_end:\n\n.. tabularcolumns:: |p{1cm}|p{2cm}|p{12cm}|\n\n.. table:: Pipeline back-end\n\n +------------+------------------+--------------------------------------------------------------------+\n | Field name | Field type | Description |\n +============+==================+====================================================================+\n | f_init | Function pointer | Function to initialize the back-end of the current pipeline |\n | | | instance. Typical work implemented by this function for the |\n | | | current pipeline instance: |\n | | | Memory allocation; |\n | | | Parse the pipeline type specific arguments; |\n | | | Initialize the pipeline input ports, output ports and tables, |\n | | | interconnect input ports to tables; |\n | | | Set the message handlers. |\n +------------+------------------+--------------------------------------------------------------------+\n | f_free | Function pointer | Function to free the resources allocated by the back-end of the |\n | | | current pipeline instance. |\n +------------+------------------+--------------------------------------------------------------------+\n | f_run | Function pointer | Set to NULL for pipelines implemented using the DPDK library |\n | | | librte_pipeline (typical case), and to non-NULL otherwise. This |\n | | | mechanism is made available to support quick integration of |\n | | | legacy code. |\n | | | This function is expected to provide the packet processing |\n | | | related code to be called as part of the CPU thread dispatch |\n | | | loop, so this function is not allowed to contain an infinite loop. |\n +------------+------------------+--------------------------------------------------------------------+\n | f_timer | Function pointer | Function to read the pipeline input message queues, handle |\n | | | the request messages, create response messages and write |\n | | | the response queues. The format of request and response |\n | | | messages is defined by each pipeline type, with the exception |\n | | | of some requests which are mandatory for all pipelines (e.g. |\n | | | ping, statistics). |\n +------------+------------------+--------------------------------------------------------------------+\n | f_track | Function pointer | See section Tracking pipeline output port to physical link |\n +------------+------------------+--------------------------------------------------------------------+\n\n\n.. _table_ip_pipelines_front_end:\n\n.. tabularcolumns:: |p{1cm}|p{2cm}|p{12cm}|\n\n.. table:: Pipeline front-end\n\n +------------+-----------------------+-------------------------------------------------------------------+\n | Field name | Field type | Description |\n +============+=======================+===================================================================+\n | f_init | Function pointer | Function to initialize the front-end of the current pipeline |\n | | | instance. |\n +------------+-----------------------+-------------------------------------------------------------------+\n | f_free | Function pointer | Function to free the resources allocated by the front-end of |\n | | | the current pipeline instance. |\n +------------+-----------------------+-------------------------------------------------------------------+\n | cmds | Array of CLI commands | Array of CLI commands to be registered to the application CLI |\n | | | for the current pipeline type. Even though the CLI is executed |\n | | | by a different pipeline (typically, this is the master pipeline), |\n | | | from modularity perspective is more efficient to keep the |\n | | | message client side (part of the front-end) together with the |\n | | | message server side (part of the back-end). |\n +------------+-----------------------+-------------------------------------------------------------------+\n\n\nTracking pipeline output port to physical link\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nEach pipeline instance is a standalone block that does not have visibility into the other pipeline instances or\nthe application-level pipeline inter-connectivity.\nIn some cases, it is useful for a pipeline instance to get application level information related to pipeline\nconnectivity, such as to identify the output link (e.g. physical NIC port) where one of its output ports connected,\neither directly or indirectly by traversing other pipeline instances.\n\nTracking can be successful or unsuccessful.\nTypically, tracking for a specific pipeline instance is successful when each one of its input ports can be mapped\nto a single output port, meaning that all packets read from the current input port can only go out on a single\noutput port.\nDepending on the pipeline type, some exceptions may be allowed: a small portion of the packets, considered exception\npackets, are sent out on an output port that is pre-configured for this purpose.\n\nFor pass-through pipeline type, the tracking is always successful.\nFor pipeline types as flow classification, firewall or routing, the tracking is only successful when the number of\noutput ports for the current pipeline instance is 1.\n\nThis feature is used by the IP routing pipeline for adding/removing implicit routes every time a link is brought\nup/down.\n\n\nTable copies\n^^^^^^^^^^^^\n\nFast table copy: pipeline table used by pipeline for the packet processing task, updated through messages, table\ndata structures are optimized for lookup operation.\n\nSlow table copy: used by the configuration layer, typically updated through CLI commands, kept in sync with the fast\ncopy (its update triggers the fast copy update).\nRequired for executing advanced table queries without impacting the packet processing task, therefore the slow copy\nis typically organized using different criteria than the fast copy.\n\nExamples:\n\n* Flow classification: Search through current set of flows (e.g. list all flows with a specific source IP address);\n\n* Firewall: List rules in descending order of priority;\n\n* Routing table: List routes sorted by prefix depth and their type (local, remote, default);\n\n* ARP: List entries sorted per output interface.\n\n\nPacket meta-data\n^^^^^^^^^^^^^^^^\n\nPacket meta-data field offsets provided as argument to pipeline instances are essentially defining the data structure\nfor the packet meta-data used by the current application use-case.\nIt is very useful to put it in the configuration file as a comment in order to facilitate the readability of the\nconfiguration file.\n\nThe reason to use field offsets for defining the data structure for the packet meta-data is due to the C language\nlimitation of not being able to define data structures at run-time.\nFeature to consider: have the configuration file parser automatically generate and print the data structure defining\nthe packet meta-data for the current application use-case.\n\nPacket meta-data typically contains:\n\n1. Pure meta-data: intermediate data per packet that is computed internally, passed between different tables of\n the same pipeline instance (e.g. lookup key for the ARP table is obtained from the routing table), or between\n different pipeline instances (e.g. flow ID, traffic metering color, etc);\n\n2. Packet fields: typically, packet header fields that are read directly from the packet, or read from the packet\n and saved (duplicated) as a working copy at a different location within the packet meta-data (e.g. Diffserv\n 5-tuple, IP destination address, etc).\n\nSeveral strategies are used to design the packet meta-data, as described in the next subsections.\n\n\nStore packet meta-data in a different cache line as the packet headers\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThis approach is able to support protocols with variable header length, like MPLS, where the offset of IP header\nfrom the start of the packet (and, implicitly, the offset of the IP header in the packet buffer) is not fixed.\nSince the pipelines typically require the specification of a fixed offset to the packet fields (e.g. Diffserv\n5-tuple, used by the flow classification pipeline, or the IP destination address, used by the IP routing pipeline),\nthe workaround is to have the packet RX pipeline copy these fields at fixed offsets within the packet meta-data.\n\nAs this approach duplicates some of the packet fields, it requires accessing more cache lines per packet for filling\nin selected packet meta-data fields (on RX), as well as flushing selected packet meta-data fields into the\npacket (on TX).\n\nExample:\n\n.. code-block:: ini\n\n\n ; struct app_pkt_metadata {\n ;\tuint32_t ip_da;\n ; uint32_t hash;\n ; uint32_t flow_id;\n ; uint32_t color;\n ; } __attribute__((__packed__));\n ;\n\n [PIPELINE1]\n ; Packet meta-data offsets\n ip_da_offset = 0; Used by: routing\n hash_offset = 4; Used by: RX, flow classification\n flow_id_offset = 8; Used by: flow classification, flow actions\n color_offset = 12; Used by: flow actions, routing\n\n\nOverlay the packet meta-data in the same cache line with the packet headers\n\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\n\nThis approach is minimizing the number of cache line accessed per packet by storing the packet metadata in the\nsame cache line with the packet headers.\nTo enable this strategy, either some headroom is reserved for meta-data at the beginning of the packet headers\ncache line (e.g. if 16 bytes are needed for meta-data, then the packet headroom can be set to 128+16 bytes, so\nthat NIC writes the first byte of the packet at offset 16 from the start of the first packet cache line),\nor meta-data is reusing the space of some packet headers that are discarded from the packet (e.g. input Ethernet\nheader).\n\nExample:\n\n.. code-block:: ini\n\n ; struct app_pkt_metadata {\n ; uint8_t headroom[RTE_PKTMBUF_HEADROOM]; /* 128 bytes (default) */\n ; union {\n ; struct {\n ; struct ether_hdr ether; /* 14 bytes */\n ; struct qinq_hdr qinq; /* 8 bytes */\n ; };\n ; struct {\n ; uint32_t hash;\n ; uint32_t flow_id;\n ; uint32_t color;\n ; };\n ; };\n ; struct ipv4_hdr ip; /* 20 bytes */\n ; } __attribute__((__packed__));\n ;\n [PIPELINE2]\n ; Packet meta-data offsets\n qinq_offset = 142; Used by: RX, flow classification\n ip_da_offset = 166; Used by: routing\n hash_offset = 128; Used by: RX, flow classification\n flow_id_offset = 132; Used by: flow classification, flow actions\n color_offset = 136; Used by: flow actions, routing\n\n\nList of pipeline types\n~~~~~~~~~~~~~~~~~~~~~~\n\n.. _table_ip_pipelines_types:\n\n.. tabularcolumns:: |p{3cm}|p{5cm}|p{4cm}|p{4cm}|\n\n.. table:: List of pipeline types provided with the application\n\n +-----------------------+-----------------------------+-----------------------+------------------------------------------+\n | Name | Table(s) | Actions | Messages |\n +=======================+=============================+=======================+==========================================+\n | Pass-through | Passthrough | 1. Pkt metadata build | 1. Ping |\n | | | 2. Flow hash | 2. Stats |\n | Note: depending on | | 3. Pkt checks | |\n | port type, can be | | 4. Load balancing | |\n | used for RX, TX, IP | | | |\n | fragmentation, IP | | | |\n | reassembly or Traffic | | | |\n | Management | | | |\n +-----------------------+-----------------------------+-----------------------+------------------------------------------+\n | Flow classification | Exact match | 1. Flow ID | 1. Ping |\n | | | | |\n | | * Key = byte array | 2. Flow stats | 2. Stats |\n | | (source: pkt metadata) | 3. Metering | 3. Flow stats |\n | | * Data = action dependent | 4. Network Address | 4. Action stats |\n | | | 5. Translation (NAT) | 5. Flow add/ update/ delete |\n | | | | 6. Default flow add/ update/ delete |\n | | | | 7. Action update |\n +-----------------------+-----------------------------+-----------------------+------------------------------------------+\n | Flow actions | Array | 1. Flow stats | 1. Ping |\n | | | | |\n | | * Key = Flow ID | 2. Metering | 2. Stats |\n | | (source: pkt metadata) | 3. Network Address | 3. Action stats |\n | | * Data = action dependent | 4. Translation (NAT) | 4. Action update |\n +-----------------------+-----------------------------+-----------------------+------------------------------------------+\n | Firewall | ACL | 1. Allow/Drop | 1. Ping |\n | | | | |\n | | * Key = n-tuple | | 2. Stats |\n | | (source: pkt headers) | | 3. Rule add/ update/ delete |\n | | * Data = none | | 4. Default rule add/ update/ delete |\n +-----------------------+-----------------------------+-----------------------+------------------------------------------+\n | IP routing | LPM (IPv4 or IPv6, | 1. TTL decrement and | 1. Ping |\n | | depending on pipeline type) | 2. IPv4 checksum | 2. Stats |\n | | | | |\n | | * Key = IP destination | 3. update | 3. Route add/ update/ delete |\n | | (source: pkt metadata) | 4. Header | 4. Default route add/ update/ delete |\n | | * Data = Dependent on | 5. encapsulation | 5. ARP entry add/ update/ delete |\n | | actions and next hop | 6. (based on next hop | 6. Default ARP entry add/ update/ delete |\n | | type | 7. type) | |\n | | | | |\n | | Hash table (for ARP, only | | |\n | | | | |\n | | when ARP is enabled) | | |\n | | | | |\n | | * Key = (Port ID, | | |\n | | next hop IP address) | | |\n | | (source: pkt meta-data) | | |\n | | * Data: MAC address | | |\n +-----------------------+-----------------------------+-----------------------+------------------------------------------+\n\n\n\nCommand Line Interface (CLI)\n----------------------------\n\nGlobal CLI commands\n~~~~~~~~~~~~~~~~~~~\n\n.. _table_ip_pipelines_cli_commands:\n\n.. tabularcolumns:: |p{3cm}|p{6cm}|p{6cm}|\n\n.. table:: Global CLI commands\n\n +---------+---------------------------------------+--------------------------------------------+\n | Command | Description | Syntax |\n +=========+=======================================+============================================+\n | run | Run CLI commands script file. | run |\n | | | = path to file with CLI commands to |\n | | | execute |\n +---------+---------------------------------------+--------------------------------------------+\n | quit | Gracefully terminate the application. | quit |\n +---------+---------------------------------------+--------------------------------------------+\n\n\nCLI commands for link configuration\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n.. _table_ip_pipelines_runtime_config:\n\n.. tabularcolumns:: |p{3cm}|p{6cm}|p{6cm}|\n\n.. table:: List of run-time configuration commands for link configuration\n\n +-------------+--------------------+--------------------------------------------+\n | Command | Description | Syntax |\n +=============+====================+============================================+\n | link config | Link configuration | link config |\n +-------------+--------------------+--------------------------------------------+\n | link up | Link up | link up |\n +-------------+--------------------+--------------------------------------------+\n | link down | Link down | link down |\n +-------------+--------------------+--------------------------------------------+\n | link ls | Link list | link ls |\n +-------------+--------------------+--------------------------------------------+\n\n\nCLI commands common for all pipeline types\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n.. _table_ip_pipelines_mandatory:\n\n.. tabularcolumns:: |p{3cm}|p{6cm}|p{6cm}|\n\n.. table:: CLI commands mandatory for all pipelines\n\n +--------------------+------------------------------------------------------+----------------------------------------------+\n | Command | Description | Syntax |\n +====================+======================================================+==============================================+\n | ping | Check whether specific pipeline instance is alive. | p ping |\n | | The master pipeline sends a ping request | |\n | | message to given pipeline instance and waits for | |\n | | a response message back. | |\n | | Timeout message is displayed when the response | |\n | | message is not received before the timer | |\n | | expires. | |\n +--------------------+------------------------------------------------------+----------------------------------------------+\n | stats | Display statistics for specific pipeline input port, | p stats port in |\n | | output port or table. | p stats port out |\n | | | p stats table |\n +--------------------+------------------------------------------------------+----------------------------------------------+\n | input port enable | Enable given input port for specific pipeline | p port in enable |\n | | instance. | |\n +--------------------+------------------------------------------------------+----------------------------------------------+\n | input port disable | Disable given input port for specific pipeline | p port in disable |\n | | instance. | |\n +--------------------+------------------------------------------------------+----------------------------------------------+\n\nPipeline type specific CLI commands\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe pipeline specific CLI commands are part of the pipeline type front-end.\n" }, { "path": "doc/guides/sample_app_ug/ip_reassembly.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIP Reassembly Sample Application\n================================\n\nThe L3 Forwarding application is a simple example of packet processing using the DPDK.\nThe application performs L3 forwarding with reassembly for fragmented IPv4 and IPv6 packets.\n\nOverview\n--------\n\nThe application demonstrates the use of the DPDK libraries to implement packet forwarding\nwith reassembly for IPv4 and IPv6 fragmented packets.\nThe initialization and run- time paths are very similar to those of the L2 forwarding application\n(see Chapter 9 \"L2 Forwarding Sample Application\" for more information).\nThe main difference from the L2 Forwarding sample application is that\nit reassembles fragmented IPv4 and IPv6 packets before forwarding.\nThe maximum allowed size of reassembled packet is 9.5 KB.\n\nThere are two key differences from the L2 Forwarding sample application:\n\n* The first difference is that the forwarding decision is taken based on information read from the input packet's IP header.\n\n* The second difference is that the application differentiates between IP and non-IP traffic by means of offload flags.\n\nThe Longest Prefix Match (LPM for IPv4, LPM6 for IPv6) table is used to store/lookup an outgoing port number, associated with that IPv4 address. Any unmatched packets are forwarded to the originating port.Compiling the Application\n--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------\n\nTo compile the application:\n\n#. Go to the sample application directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/ip_reassembly\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\nSee the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nThe application has a number of command line options:\n\n.. code-block:: console\n\n ./build/ip_reassembly [EAL options] -- -p PORTMASK [-q NQ] [--maxflows=FLOWS>] [--flowttl=TTL[(s|ms)]]\n\nwhere:\n\n* -p PORTMASK: Hexadecimal bitmask of ports to configure\n\n* -q NQ: Number of RX queues per lcore\n\n* --maxflows=FLOWS: determines maximum number of active fragmented flows (1-65535). Default value: 4096.\n\n* --flowttl=TTL[(s|ms)]: determines maximum Time To Live for fragmented packet.\n If all fragments of the packet wouldn't appear within given time-out,\n then they are considered as invalid and will be dropped.\n Valid range is 1ms - 3600s. Default value: 1s.\n\nTo run the example in linuxapp environment with 2 lcores (2,4) over 2 ports(0,2) with 1 RX queue per lcore:\n\n.. code-block:: console\n\n ./build/ip_reassembly -c 0x14 -n 3 -- -p 5\n EAL: coremask set to 14\n EAL: Detected lcore 0 on socket 0\n EAL: Detected lcore 1 on socket 1\n EAL: Detected lcore 2 on socket 0\n EAL: Detected lcore 3 on socket 1\n EAL: Detected lcore 4 on socket 0\n ...\n\n Initializing port 0 on lcore 2... Address:00:1B:21:76:FA:2C, rxq=0 txq=2,0 txq=4,1\n done: Link Up - speed 10000 Mbps - full-duplex\n Skipping disabled port 1\n Initializing port 2 on lcore 4... Address:00:1B:21:5C:FF:54, rxq=0 txq=2,0 txq=4,1\n done: Link Up - speed 10000 Mbps - full-duplex\n Skipping disabled port 3IP_FRAG: Socket 0: adding route 100.10.0.0/16 (port 0)\n IP_RSMBL: Socket 0: adding route 100.20.0.0/16 (port 1)\n ...\n\n IP_RSMBL: Socket 0: adding route 0101:0101:0101:0101:0101:0101:0101:0101/48 (port 0)\n IP_RSMBL: Socket 0: adding route 0201:0101:0101:0101:0101:0101:0101:0101/48 (port 1)\n ...\n\n IP_RSMBL: entering main loop on lcore 4\n IP_RSMBL: -- lcoreid=4 portid=2\n IP_RSMBL: entering main loop on lcore 2\n IP_RSMBL: -- lcoreid=2 portid=0\n\nTo run the example in linuxapp environment with 1 lcore (4) over 2 ports(0,2) with 2 RX queues per lcore:\n\n.. code-block:: console\n\n ./build/ip_reassembly -c 0x10 -n 3 -- -p 5 -q 2\n\nTo test the application, flows should be set up in the flow generator that match the values in the\nl3fwd_ipv4_route_array and/or l3fwd_ipv6_route_array table.\n\nPlease note that in order to test this application,\nthe traffic generator should be generating valid fragmented IP packets.\nFor IPv6, the only supported case is when no other extension headers other than\nfragment extension header are present in the packet.\n\nThe default l3fwd_ipv4_route_array table is:\n\n.. code-block:: c\n\n struct l3fwd_ipv4_route l3fwd_ipv4_route_array[] = {\n {IPv4(100, 10, 0, 0), 16, 0},\n {IPv4(100, 20, 0, 0), 16, 1},\n {IPv4(100, 30, 0, 0), 16, 2},\n {IPv4(100, 40, 0, 0), 16, 3},\n {IPv4(100, 50, 0, 0), 16, 4},\n {IPv4(100, 60, 0, 0), 16, 5},\n {IPv4(100, 70, 0, 0), 16, 6},\n {IPv4(100, 80, 0, 0), 16, 7},\n };\n\nThe default l3fwd_ipv6_route_array table is:\n\n.. code-block:: c\n\n struct l3fwd_ipv6_route l3fwd_ipv6_route_array[] = {\n {{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 0},\n {{2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 1},\n {{3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 2},\n {{4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 3},\n {{5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 4},\n {{6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 5},\n {{7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 6},\n {{8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, 48, 7},\n };\n\nFor example, for the fragmented input IPv4 packet with destination address: 100.10.1.1,\na reassembled IPv4 packet be sent out from port #0 to the destination address 100.10.1.1\nonce all the fragments are collected.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of the sample application code.\nAs mentioned in the overview section, the initialization and run-time paths are very similar to those of the L2 forwarding application\n(see Chapter 9 \"L2 Forwarding Sample Application\" for more information).\nThe following sections describe aspects that are specific to the IP reassemble sample application.\n\nIPv4 Fragment Table Initialization\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThis application uses the rte_ip_frag library. Please refer to Programmer's Guide for more detailed explanation of how to use this library.\nFragment table maintains information about already received fragments of the packet.\nEach IP packet is uniquely identified by triple , , .\nTo avoid lock contention, each RX queue has its own Fragment Table,\ne.g. the application can't handle the situation when different fragments of the same packet arrive through different RX queues.\nEach table entry can hold information about packet consisting of up to RTE_LIBRTE_IP_FRAG_MAX_FRAGS fragments.\n\n.. code-block:: c\n\n frag_cycles = (rte_get_tsc_hz() + MS_PER_S - 1) / MS_PER_S * max_flow_ttl;\n\n if ((qconf->frag_tbl[queue] = rte_ip_frag_tbl_create(max_flow_num, IPV4_FRAG_TBL_BUCKET_ENTRIES, max_flow_num, frag_cycles, socket)) == NULL)\n {\n RTE_LOG(ERR, IP_RSMBL, \"ip_frag_tbl_create(%u) on \" \"lcore: %u for queue: %u failed\\n\", max_flow_num, lcore, queue);\n return -1;\n }\n\nMempools Initialization\n~~~~~~~~~~~~~~~~~~~~~~~\n\nThe reassembly application demands a lot of mbuf's to be allocated.\nAt any given time up to (2 \\* max_flow_num \\* RTE_LIBRTE_IP_FRAG_MAX_FRAGS \\* )\ncan be stored inside Fragment Table waiting for remaining fragments.\nTo keep mempool size under reasonable limits and to avoid situation when one RX queue can starve other queues,\neach RX queue uses its own mempool.\n\n.. code-block:: c\n\n nb_mbuf = RTE_MAX(max_flow_num, 2UL * MAX_PKT_BURST) * RTE_LIBRTE_IP_FRAG_MAX_FRAGS;\n nb_mbuf *= (port_conf.rxmode.max_rx_pkt_len + BUF_SIZE - 1) / BUF_SIZE;\n nb_mbuf *= 2; /* ipv4 and ipv6 */\n nb_mbuf += RTE_TEST_RX_DESC_DEFAULT + RTE_TEST_TX_DESC_DEFAULT;\n nb_mbuf = RTE_MAX(nb_mbuf, (uint32_t)NB_MBUF);\n\n rte_snprintf(buf, sizeof(buf), \"mbuf_pool_%u_%u\", lcore, queue);\n\n if ((rxq->pool = rte_mempool_create(buf, nb_mbuf, MBUF_SIZE, 0, sizeof(struct rte_pktmbuf_pool_private), rte_pktmbuf_pool_init, NULL,\n rte_pktmbuf_init, NULL, socket, MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET)) == NULL) {\n\n RTE_LOG(ERR, IP_RSMBL, \"mempool_create(%s) failed\", buf);\n return -1;\n }\n\nPacket Reassembly and Forwarding\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nFor each input packet, the packet forwarding operation is done by the l3fwd_simple_forward() function.\nIf the packet is an IPv4 or IPv6 fragment, then it calls rte_ipv4_reassemble_packet() for IPv4 packets,\nor rte_ipv6_reassemble_packet() for IPv6 packets.\nThese functions either return a pointer to valid mbuf that contains reassembled packet,\nor NULL (if the packet can't be reassembled for some reason).\nThen l3fwd_simple_forward() continues with the code for the packet forwarding decision\n(that is, the identification of the output interface for the packet) and\nactual transmit of the packet.\n\nThe rte_ipv4_reassemble_packet() or rte_ipv6_reassemble_packet() are responsible for:\n\n#. Searching the Fragment Table for entry with packet's \n\n#. If the entry is found, then check if that entry already timed-out.\n If yes, then free all previously received fragments,\n and remove information about them from the entry.\n\n#. If no entry with such key is found, then try to create a new one by one of two ways:\n\n #. Use as empty entry\n\n #. Delete a timed-out entry, free mbufs associated with it mbufs and store a new entry with specified key in it.\n\n#. Update the entry with new fragment information and check\n if a packet can be reassembled (the packet's entry contains all fragments).\n\n #. If yes, then, reassemble the packet, mark table's entry as empty and return the reassembled mbuf to the caller.\n\n #. If no, then just return a NULL to the caller.\n\nIf at any stage of packet processing a reassembly function encounters an error\n(can't insert new entry into the Fragment table, or invalid/timed-out fragment),\nthen it will free all associated with the packet fragments,\nmark the table entry as invalid and return NULL to the caller.\n\nDebug logging and Statistics Collection\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe RTE_LIBRTE_IP_FRAG_TBL_STAT controls statistics collection for the IP Fragment Table.\nThis macro is disabled by default.\nTo make ip_reassembly print the statistics to the standard output,\nthe user must send either an USR1, INT or TERM signal to the process.\nFor all of these signals, the ip_reassembly process prints Fragment table statistics for each RX queue,\nplus the INT and TERM will cause process termination as usual.\n" }, { "path": "doc/guides/sample_app_ug/ipv4_multicast.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIPv4 Multicast Sample Application\n=================================\n\nThe IPv4 Multicast application is a simple example of packet processing\nusing the Data Plane Development Kit (DPDK).\nThe application performs L3 multicasting.\n\nOverview\n--------\n\nThe application demonstrates the use of zero-copy buffers for packet forwarding.\nThe initialization and run-time paths are very similar to those of the L2 forwarding application\n(see Chapter 9 \"L2 Forwarding Sample Application (in Real and Virtualized Environments)\" for details more information).\nThis guide highlights the differences between the two applications.\nThere are two key differences from the L2 Forwarding sample application:\n\n* The IPv4 Multicast sample application makes use of indirect buffers.\n\n* The forwarding decision is taken based on information read from the input packet's IPv4 header.\n\nThe lookup method is the Four-byte Key (FBK) hash-based method.\nThe lookup table is composed of pairs of destination IPv4 address (the FBK)\nand a port mask associated with that IPv4 address.\n\nFor convenience and simplicity, this sample application does not take IANA-assigned multicast addresses into account,\nbut instead equates the last four bytes of the multicast group (that is, the last four bytes of the destination IP address)\nwith the mask of ports to multicast packets to.\nAlso, the application does not consider the Ethernet addresses;\nit looks only at the IPv4 destination address for any given packet.\n\nBuilding the Application\n------------------------\n\nTo compile the application:\n\n#. Go to the sample application directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/ipv4_multicast\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\nSee the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\n.. note::\n\n The compiled application is written to the build subdirectory.\n To have the application written to a different location,\n the O=/path/to/build/directory option may be specified in the make command.\n\nRunning the Application\n-----------------------\n\nThe application has a number of command line options:\n\n.. code-block:: console\n\n ./build/ipv4_multicast [EAL options] -- -p PORTMASK [-q NQ]\n\nwhere,\n\n* -p PORTMASK: Hexadecimal bitmask of ports to configure\n\n* -q NQ: determines the number of queues per lcore\n\n.. note::\n\n Unlike the basic L2/L3 Forwarding sample applications,\n NUMA support is not provided in the IPv4 Multicast sample application.\n\nTypically, to run the IPv4 Multicast sample application, issue the following command (as root):\n\n.. code-block:: console\n\n ./build/ipv4_multicast -c 0x00f -n 3 -- -p 0x3 -q 1\n\nIn this command:\n\n* The -c option enables cores 0, 1, 2 and 3\n\n* The -n option specifies 3 memory channels\n\n* The -p option enables ports 0 and 1\n\n* The -q option assigns 1 queue to each lcore\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications\nand the Environment Abstraction Layer (EAL) options.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of the code.\nAs mentioned in the overview section,\nthe initialization and run-time paths are very similar to those of the L2 Forwarding sample application\n(see Chapter 9 \"L2 Forwarding Sample Application in Real and Virtualized Environments\" for more information).\nThe following sections describe aspects that are specific to the IPv4 Multicast sample application.\n\nMemory Pool Initialization\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe IPv4 Multicast sample application uses three memory pools.\nTwo of the pools are for indirect buffers used for packet duplication purposes.\nMemory pools for indirect buffers are initialized differently from the memory pool for direct buffers:\n\n.. code-block:: c\n\n packet_pool = rte_mempool_create(\"packet_pool\", NB_PKT_MBUF, PKT_MBUF_SIZE, 32, sizeof(struct rte_pktmbuf_pool_private),\n rte_pktmbuf_pool_init, NULL, rte_pktmbuf_init, NULL, rte_socket_id(), 0);\n\n header_pool = rte_mempool_create(\"header_pool\", NB_HDR_MBUF, HDR_MBUF_SIZE, 32, 0, NULL, NULL, rte_pktmbuf_init, NULL, rte_socket_id(), 0);\n clone_pool = rte_mempool_create(\"clone_pool\", NB_CLONE_MBUF,\n CLONE_MBUF_SIZE, 32, 0, NULL, NULL, rte_pktmbuf_init, NULL, rte_socket_id(), 0);\n\nThe reason for this is because indirect buffers are not supposed to hold any packet data and\ntherefore can be initialized with lower amount of reserved memory for each buffer.\n\nHash Initialization\n~~~~~~~~~~~~~~~~~~~\n\nThe hash object is created and loaded with the pre-configured entries read from a global array:\n\n.. code-block:: c\n\n static int\n\n init_mcast_hash(void)\n {\n uint32_t i;\n mcast_hash_params.socket_id = rte_socket_id();\n\n mcast_hash = rte_fbk_hash_create(&mcast_hash_params);\n if (mcast_hash == NULL){\n return -1;\n }\n\n for (i = 0; i < N_MCAST_GROUPS; i ++){\n if (rte_fbk_hash_add_key(mcast_hash, mcast_group_table[i].ip, mcast_group_table[i].port_mask) < 0) {\n\t\t return -1;\n }\n }\n return 0;\n }\n\nForwarding\n~~~~~~~~~~\n\nAll forwarding is done inside the mcast_forward() function.\nFirstly, the Ethernet* header is removed from the packet and the IPv4 address is extracted from the IPv4 header:\n\n.. code-block:: c\n\n /* Remove the Ethernet header from the input packet */\n\n iphdr = (struct ipv4_hdr *)rte_pktmbuf_adj(m, sizeof(struct ether_hdr));\n RTE_MBUF_ASSERT(iphdr != NULL);\n dest_addr = rte_be_to_cpu_32(iphdr->dst_addr);\n\nThen, the packet is checked to see if it has a multicast destination address and\nif the routing table has any ports assigned to the destination address:\n\n.. code-block:: c\n\n if (!IS_IPV4_MCAST(dest_addr) ||\n (hash = rte_fbk_hash_lookup(mcast_hash, dest_addr)) <= 0 ||\n (port_mask = hash & enabled_port_mask) == 0) {\n rte_pktmbuf_free(m);\n return;\n }\n\nThen, the number of ports in the destination portmask is calculated with the help of the bitcnt() function:\n\n.. code-block:: c\n\n /* Get number of bits set. */\n\n static inline uint32_t bitcnt(uint32_t v)\n {\n uint32_t n;\n\n for (n = 0; v != 0; v &= v - 1, n++)\n ;\n return (n);\n }\n\nThis is done to determine which forwarding algorithm to use.\nThis is explained in more detail in the next section.\n\nThereafter, a destination Ethernet address is constructed:\n\n.. code-block:: c\n\n /* construct destination Ethernet address */\n\n dst_eth_addr = ETHER_ADDR_FOR_IPV4_MCAST(dest_addr);\n\nSince Ethernet addresses are also part of the multicast process, each outgoing packet carries the same destination Ethernet address.\nThe destination Ethernet address is constructed from the lower 23 bits of the multicast group OR-ed\nwith the Ethernet address 01:00:5e:00:00:00, as per RFC 1112:\n\n.. code-block:: c\n\n #define ETHER_ADDR_FOR_IPV4_MCAST(x) \\\n (rte_cpu_to_be_64(0x01005e000000ULL | ((x) & 0x7fffff)) >> 16)\n\nThen, packets are dispatched to the destination ports according to the portmask associated with a multicast group:\n\n.. code-block:: c\n\n for (port = 0; use_clone != port_mask; port_mask >>= 1, port++) {\n /* Prepare output packet and send it out. */\n\n if ((port_mask & 1) != 0) {\n if (likely ((mc = mcast_out_pkt(m, use_clone)) != NULL))\n mcast_send_pkt(mc, &dst_eth_addr.as_addr, qconf, port);\n else if (use_clone == 0)\n rte_pktmbuf_free(m);\n }\n }\n\nThe actual packet transmission is done in the mcast_send_pkt() function:\n\n.. code-block:: c\n\n static inline void mcast_send_pkt(struct rte_mbuf *pkt, struct ether_addr *dest_addr, struct lcore_queue_conf *qconf, uint8_t port)\n {\n struct ether_hdr *ethdr;\n uint16_t len;\n\n /* Construct Ethernet header. */\n\n ethdr = (struct ether_hdr *)rte_pktmbuf_prepend(pkt, (uint16_t) sizeof(*ethdr));\n\n RTE_MBUF_ASSERT(ethdr != NULL);\n\n ether_addr_copy(dest_addr, ðdr->d_addr);\n ether_addr_copy(&ports_eth_addr[port], ðdr->s_addr);\n ethdr->ether_type = rte_be_to_cpu_16(ETHER_TYPE_IPv4);\n\n /* Put new packet into the output queue */\n\n len = qconf->tx_mbufs[port].len;\n qconf->tx_mbufs[port].m_table[len] = pkt;\n qconf->tx_mbufs[port].len = ++len;\n\n /* Transmit packets */\n\n if (unlikely(MAX_PKT_BURST == len))\n send_burst(qconf, port);\n }\n\nBuffer Cloning\n~~~~~~~~~~~~~~\n\nThis is the most important part of the application since it demonstrates the use of zero- copy buffer cloning.\nThere are two approaches for creating the outgoing packet and although both are based on the data zero-copy idea,\nthere are some differences in the detail.\n\nThe first approach creates a clone of the input packet, for example,\nwalk though all segments of the input packet and for each of segment,\ncreate a new buffer and attach that new buffer to the segment\n(refer to rte_pktmbuf_clone() in the rte_mbuf library for more details).\nA new buffer is then allocated for the packet header and is prepended to the cloned buffer.\n\nThe second approach does not make a clone, it just increments the reference counter for all input packet segment,\nallocates a new buffer for the packet header and prepends it to the input packet.\n\nBasically, the first approach reuses only the input packet's data, but creates its own copy of packet's metadata.\nThe second approach reuses both input packet's data and metadata.\n\nThe advantage of first approach is that each outgoing packet has its own copy of the metadata,\nso we can safely modify the data pointer of the input packet.\nThat allows us to skip creation if the output packet is for the last destination port\nand instead modify input packet's header in place.\nFor example, for N destination ports, we need to invoke mcast_out_pkt() (N-1) times.\n\nThe advantage of the second approach is that there is less work to be done for each outgoing packet,\nthat is, the \"clone\" operation is skipped completely.\nHowever, there is a price to pay.\nThe input packet's metadata must remain intact, so for N destination ports,\nwe need to invoke mcast_out_pkt() (N) times.\n\nTherefore, for a small number of outgoing ports (and segments in the input packet),\nfirst approach is faster.\nAs the number of outgoing ports (and/or input segments) grows, the second approach becomes more preferable.\n\nDepending on the number of segments or the number of ports in the outgoing portmask,\neither the first (with cloning) or the second (without cloning) approach is taken:\n\n.. code-block:: c\n\n use_clone = (port_num <= MCAST_CLONE_PORTS && m->pkt.nb_segs <= MCAST_CLONE_SEGS);\n\nIt is the mcast_out_pkt() function that performs the packet duplication (either with or without actually cloning the buffers):\n\n.. code-block:: c\n\n static inline struct rte_mbuf *mcast_out_pkt(struct rte_mbuf *pkt, int use_clone)\n {\n struct rte_mbuf *hdr;\n\n /* Create new mbuf for the header. */\n\n if (unlikely ((hdr = rte_pktmbuf_alloc(header_pool)) == NULL))\n return (NULL);\n\n /* If requested, then make a new clone packet. */\n\n if (use_clone != 0 && unlikely ((pkt = rte_pktmbuf_clone(pkt, clone_pool)) == NULL)) {\n rte_pktmbuf_free(hdr);\n return (NULL);\n }\n\n /* prepend new header */\n\n hdr->pkt.next = pkt;\n\n /* update header's fields */\n\n hdr->pkt.pkt_len = (uint16_t)(hdr->pkt.data_len + pkt->pkt.pkt_len);\n hdr->pkt.nb_segs = (uint8_t)(pkt->pkt.nb_segs + 1);\n\n /* copy metadata from source packet */\n\n hdr->pkt.in_port = pkt->pkt.in_port;\n hdr->pkt.vlan_macip = pkt->pkt.vlan_macip;\n hdr->pkt.hash = pkt->pkt.hash;\n hdr->ol_flags = pkt->ol_flags;\n rte_mbuf_sanity_check(hdr, RTE_MBUF_PKT, 1);\n\n return (hdr);\n }\n" }, { "path": "doc/guides/sample_app_ug/kernel_nic_interface.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nKernel NIC Interface Sample Application\n=======================================\n\nThe Kernel NIC Interface (KNI) is a DPDK control plane solution that\nallows userspace applications to exchange packets with the kernel networking stack.\nTo accomplish this, DPDK userspace applications use an IOCTL call\nto request the creation of a KNI virtual device in the Linux* kernel.\nThe IOCTL call provides interface information and the DPDK's physical address space,\nwhich is re-mapped into the kernel address space by the KNI kernel loadable module\nthat saves the information to a virtual device context.\nThe DPDK creates FIFO queues for packet ingress and egress\nto the kernel module for each device allocated.\n\nThe KNI kernel loadable module is a standard net driver,\nwhich upon receiving the IOCTL call access the DPDK's FIFO queue to\nreceive/transmit packets from/to the DPDK userspace application.\nThe FIFO queues contain pointers to data packets in the DPDK. This:\n\n* Provides a faster mechanism to interface with the kernel net stack and eliminates system calls\n\n* Facilitates the DPDK using standard Linux* userspace net tools (tcpdump, ftp, and so on)\n\n* Eliminate the copy_to_user and copy_from_user operations on packets.\n\nThe Kernel NIC Interface sample application is a simple example that demonstrates the use\nof the DPDK to create a path for packets to go through the Linux* kernel.\nThis is done by creating one or more kernel net devices for each of the DPDK ports.\nThe application allows the use of standard Linux tools (ethtool, ifconfig, tcpdump) with the DPDK ports and\nalso the exchange of packets between the DPDK application and the Linux* kernel.\n\nOverview\n--------\n\nThe Kernel NIC Interface sample application uses two threads in user space for each physical NIC port being used,\nand allocates one or more KNI device for each physical NIC port with kernel module's support.\nFor a physical NIC port, one thread reads from the port and writes to KNI devices,\nand another thread reads from KNI devices and writes the data unmodified to the physical NIC port.\nIt is recommended to configure one KNI device for each physical NIC port.\nIf configured with more than one KNI devices for a physical NIC port,\nit is just for performance testing, or it can work together with VMDq support in future.\n\nThe packet flow through the Kernel NIC Interface application is as shown in the following figure.\n\n.. _figure_kernel_nic:\n\n.. figure:: img/kernel_nic.*\n\n Kernel NIC Application Packet Flow\n\n\nCompiling the Application\n-------------------------\n\nCompile the application as follows:\n\n#. Go to the example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk cd\n ${RTE_SDK}/examples/kni\n\n#. Set the target (a default target is used if not specified)\n\n .. note::\n\n This application is intended as a linuxapp only.\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nLoading the Kernel Module\n-------------------------\n\nLoading the KNI kernel module without any parameter is the typical way a DPDK application\ngets packets into and out of the kernel net stack.\nThis way, only one kernel thread is created for all KNI devices for packet receiving in kernel side:\n\n.. code-block:: console\n\n #insmod rte_kni.ko\n\nPinning the kernel thread to a specific core can be done using a taskset command such as following:\n\n.. code-block:: console\n\n #taskset -p 100000 `pgrep --fl kni_thread | awk '{print $1}'`\n\nThis command line tries to pin the specific kni_thread on the 20th lcore (lcore numbering starts at 0),\nwhich means it needs to check if that lcore is available on the board.\nThis command must be sent after the application has been launched, as insmod does not start the kni thread.\n\nFor optimum performance,\nthe lcore in the mask must be selected to be on the same socket as the lcores used in the KNI application.\n\nTo provide flexibility of performance, the kernel module of the KNI,\nlocated in the kmod sub-directory of the DPDK target directory,\ncan be loaded with parameter of kthread_mode as follows:\n\n* #insmod rte_kni.ko kthread_mode=single\n\n This mode will create only one kernel thread for all KNI devices for packet receiving in kernel side.\n By default, it is in this single kernel thread mode.\n It can set core affinity for this kernel thread by using Linux command taskset.\n\n* #insmod rte_kni.ko kthread_mode =multiple\n\n This mode will create a kernel thread for each KNI device for packet receiving in kernel side.\n The core affinity of each kernel thread is set when creating the KNI device.\n The lcore ID for each kernel thread is provided in the command line of launching the application.\n Multiple kernel thread mode can provide scalable higher performance.\n\nTo measure the throughput in a loopback mode, the kernel module of the KNI,\nlocated in the kmod sub-directory of the DPDK target directory,\ncan be loaded with parameters as follows:\n\n* #insmod rte_kni.ko lo_mode=lo_mode_fifo\n\n This loopback mode will involve ring enqueue/dequeue operations in kernel space.\n\n* #insmod rte_kni.ko lo_mode=lo_mode_fifo_skb\n\n This loopback mode will involve ring enqueue/dequeue operations and sk buffer copies in kernel space.\n\nRunning the Application\n-----------------------\n\nThe application requires a number of command line options:\n\n.. code-block:: console\n\n kni [EAL options] -- -P -p PORTMASK --config=\"(port,lcore_rx,lcore_tx[,lcore_kthread,...])[,port,lcore_rx,lcore_tx[,lcore_kthread,...]]\"\n\nWhere:\n\n* -P: Set all ports to promiscuous mode so that packets are accepted regardless of the packet's Ethernet MAC destination address.\n Without this option, only packets with the Ethernet MAC destination address set to the Ethernet address of the port are accepted.\n\n* -p PORTMASK: Hexadecimal bitmask of ports to configure.\n\n* --config=\"(port,lcore_rx, lcore_tx[,lcore_kthread, ...]) [, port,lcore_rx, lcore_tx[,lcore_kthread, ...]]\":\n Determines which lcores of RX, TX, kernel thread are mapped to which ports.\n\nRefer to *DPDK Getting Started Guide* for general information on running applications and the Environment Abstraction Layer (EAL) options.\n\nThe -c coremask parameter of the EAL options should include the lcores indicated by the lcore_rx and lcore_tx,\nbut does not need to include lcores indicated by lcore_kthread as they are used to pin the kernel thread on.\nThe -p PORTMASK parameter should include the ports indicated by the port in --config, neither more nor less.\n\nThe lcore_kthread in --config can be configured none, one or more lcore IDs.\nIn multiple kernel thread mode, if configured none, a KNI device will be allocated for each port,\nwhile no specific lcore affinity will be set for its kernel thread.\nIf configured one or more lcore IDs, one or more KNI devices will be allocated for each port,\nwhile specific lcore affinity will be set for its kernel thread.\nIn single kernel thread mode, if configured none, a KNI device will be allocated for each port.\nIf configured one or more lcore IDs,\none or more KNI devices will be allocated for each port while\nno lcore affinity will be set as there is only one kernel thread for all KNI devices.\n\nFor example, to run the application with two ports served by six lcores, one lcore of RX, one lcore of TX,\nand one lcore of kernel thread for each port:\n\n.. code-block:: console\n\n ./build/kni -c 0xf0 -n 4 -- -P -p 0x3 -config=\"(0,4,6,8),(1,5,7,9)\"\n\nKNI Operations\n--------------\n\nOnce the KNI application is started, one can use different Linux* commands to manage the net interfaces.\nIf more than one KNI devices configured for a physical port,\nonly the first KNI device will be paired to the physical device.\nOperations on other KNI devices will not affect the physical port handled in user space application.\n\nAssigning an IP address:\n\n.. code-block:: console\n\n #ifconfig vEth0_0 192.168.0.1\n\nDisplaying the NIC registers:\n\n.. code-block:: console\n\n #ethtool -d vEth0_0\n\nDumping the network traffic:\n\n.. code-block:: console\n\n #tcpdump -i vEth0_0\n\nWhen the DPDK userspace application is closed, all the KNI devices are deleted from Linux*.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of code.\n\nInitialization\n~~~~~~~~~~~~~~\n\nSetup of mbuf pool, driver and queues is similar to the setup done in the L2 Forwarding sample application\n(see Chapter 9 \"L2 Forwarding Sample Application (in Real and Virtualized Environments\" for details).\nIn addition, one or more kernel NIC interfaces are allocated for each\nof the configured ports according to the command line parameters.\n\nThe code for creating the kernel NIC interface for a specific port is as follows:\n\n.. code-block:: c\n\n kni = rte_kni_create(port, MAX_PACKET_SZ, pktmbuf_pool, &kni_ops);\n if (kni == NULL)\n rte_exit(EXIT_FAILURE, \"Fail to create kni dev \"\n \"for port: %d\\n\", port);\n\nThe code for allocating the kernel NIC interfaces for a specific port is as follows:\n\n.. code-block:: c\n\n static int\n kni_alloc(uint8_t port_id)\n {\n uint8_t i;\n struct rte_kni *kni;\n struct rte_kni_conf conf;\n struct kni_port_params **params = kni_port_params_array;\n\n if (port_id >= RTE_MAX_ETHPORTS || !params[port_id])\n return -1;\n\n params[port_id]->nb_kni = params[port_id]->nb_lcore_k ? params[port_id]->nb_lcore_k : 1;\n\n for (i = 0; i < params[port_id]->nb_kni; i++) {\n\n /* Clear conf at first */\n\n memset(&conf, 0, sizeof(conf));\n if (params[port_id]->nb_lcore_k) {\n rte_snprintf(conf.name, RTE_KNI_NAMESIZE, \"vEth%u_%u\", port_id, i);\n conf.core_id = params[port_id]->lcore_k[i];\n conf.force_bind = 1;\n } else\n rte_snprintf(conf.name, RTE_KNI_NAMESIZE, \"vEth%u\", port_id);\n conf.group_id = (uint16_t)port_id;\n conf.mbuf_size = MAX_PACKET_SZ;\n\n /*\n * The first KNI device associated to a port\n * is the master, for multiple kernel thread\n * environment.\n */\n\n if (i == 0) {\n struct rte_kni_ops ops;\n struct rte_eth_dev_info dev_info;\n\n memset(&dev_info, 0, sizeof(dev_info)); rte_eth_dev_info_get(port_id, &dev_info);\n\n conf.addr = dev_info.pci_dev->addr;\n conf.id = dev_info.pci_dev->id;\n\n memset(&ops, 0, sizeof(ops));\n\n ops.port_id = port_id;\n ops.change_mtu = kni_change_mtu;\n ops.config_network_if = kni_config_network_interface;\n\n kni = rte_kni_alloc(pktmbuf_pool, &conf, &ops);\n } else\n kni = rte_kni_alloc(pktmbuf_pool, &conf, NULL);\n\n if (!kni)\n rte_exit(EXIT_FAILURE, \"Fail to create kni for \"\n \"port: %d\\n\", port_id);\n\n params[port_id]->kni[i] = kni;\n }\n return 0;\n }\n\nThe other step in the initialization process that is unique to this sample application\nis the association of each port with lcores for RX, TX and kernel threads.\n\n* One lcore to read from the port and write to the associated one or more KNI devices\n\n* Another lcore to read from one or more KNI devices and write to the port\n\n* Other lcores for pinning the kernel threads on one by one\n\nThis is done by using the`kni_port_params_array[]` array, which is indexed by the port ID.\nThe code is as follows:\n\n.. code-block:: console\n\n static int\n parse_config(const char *arg)\n {\n const char *p, *p0 = arg;\n char s[256], *end;\n unsigned size;\n enum fieldnames {\n FLD_PORT = 0,\n FLD_LCORE_RX,\n FLD_LCORE_TX,\n _NUM_FLD = KNI_MAX_KTHREAD + 3,\n };\n int i, j, nb_token;\n char *str_fld[_NUM_FLD];\n unsigned long int_fld[_NUM_FLD];\n uint8_t port_id, nb_kni_port_params = 0;\n\n memset(&kni_port_params_array, 0, sizeof(kni_port_params_array));\n\n while (((p = strchr(p0, '(')) != NULL) && nb_kni_port_params < RTE_MAX_ETHPORTS) {\n p++;\n if ((p0 = strchr(p, ')')) == NULL)\n goto fail;\n\n size = p0 - p;\n\n if (size >= sizeof(s)) {\n printf(\"Invalid config parameters\\n\");\n goto fail;\n }\n\n rte_snprintf(s, sizeof(s), \"%.*s\", size, p);\n nb_token = rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',');\n\n if (nb_token <= FLD_LCORE_TX) {\n printf(\"Invalid config parameters\\n\");\n goto fail;\n }\n\n for (i = 0; i < nb_token; i++) {\n errno = 0;\n int_fld[i] = strtoul(str_fld[i], &end, 0);\n if (errno != 0 || end == str_fld[i]) {\n printf(\"Invalid config parameters\\n\");\n goto fail;\n }\n }\n\n i = 0;\n port_id = (uint8_t)int_fld[i++];\n\n if (port_id >= RTE_MAX_ETHPORTS) {\n printf(\"Port ID %u could not exceed the maximum %u\\n\", port_id, RTE_MAX_ETHPORTS);\n goto fail;\n }\n\n if (kni_port_params_array[port_id]) {\n printf(\"Port %u has been configured\\n\", port_id);\n goto fail;\n }\n\n kni_port_params_array[port_id] = (struct kni_port_params*)rte_zmalloc(\"KNI_port_params\", sizeof(struct kni_port_params), RTE_CACHE_LINE_SIZE);\n kni_port_params_array[port_id]->port_id = port_id;\n kni_port_params_array[port_id]->lcore_rx = (uint8_t)int_fld[i++];\n kni_port_params_array[port_id]->lcore_tx = (uint8_t)int_fld[i++];\n\n if (kni_port_params_array[port_id]->lcore_rx >= RTE_MAX_LCORE || kni_port_params_array[port_id]->lcore_tx >= RTE_MAX_LCORE) {\n printf(\"lcore_rx %u or lcore_tx %u ID could not \"\n \"exceed the maximum %u\\n\",\n kni_port_params_array[port_id]->lcore_rx, kni_port_params_array[port_id]->lcore_tx, RTE_MAX_LCORE);\n goto fail;\n }\n\n for (j = 0; i < nb_token && j < KNI_MAX_KTHREAD; i++, j++)\n kni_port_params_array[port_id]->lcore_k[j] = (uint8_t)int_fld[i];\n kni_port_params_array[port_id]->nb_lcore_k = j;\n }\n\n print_config();\n\n return 0;\n\n fail:\n\n for (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n if (kni_port_params_array[i]) {\n rte_free(kni_port_params_array[i]);\n kni_port_params_array[i] = NULL;\n }\n }\n\n return -1;\n\n }\n\nPacket Forwarding\n~~~~~~~~~~~~~~~~~\n\nAfter the initialization steps are completed, the main_loop() function is run on each lcore.\nThis function first checks the lcore_id against the user provided lcore_rx and lcore_tx\nto see if this lcore is reading from or writing to kernel NIC interfaces.\n\nFor the case that reads from a NIC port and writes to the kernel NIC interfaces,\nthe packet reception is the same as in L2 Forwarding sample application\n(see Section 9.4.6 \"Receive, Process and Transmit Packets\").\nThe packet transmission is done by sending mbufs into the kernel NIC interfaces by rte_kni_tx_burst().\nThe KNI library automatically frees the mbufs after the kernel successfully copied the mbufs.\n\n.. code-block:: c\n\n /**\n * Interface to burst rx and enqueue mbufs into rx_q\n */\n\n static void\n kni_ingress(struct kni_port_params *p)\n {\n uint8_t i, nb_kni, port_id;\n unsigned nb_rx, num;\n struct rte_mbuf *pkts_burst[PKT_BURST_SZ];\n\n if (p == NULL)\n return;\n\n nb_kni = p->nb_kni;\n port_id = p->port_id;\n\n for (i = 0; i < nb_kni; i++) {\n /* Burst rx from eth */\n nb_rx = rte_eth_rx_burst(port_id, 0, pkts_burst, PKT_BURST_SZ);\n if (unlikely(nb_rx > PKT_BURST_SZ)) {\n RTE_LOG(ERR, APP, \"Error receiving from eth\\n\");\n return;\n }\n\n /* Burst tx to kni */\n num = rte_kni_tx_burst(p->kni[i], pkts_burst, nb_rx);\n kni_stats[port_id].rx_packets += num;\n rte_kni_handle_request(p->kni[i]);\n\n if (unlikely(num < nb_rx)) {\n /* Free mbufs not tx to kni interface */\n kni_burst_free_mbufs(&pkts_burst[num], nb_rx - num);\n kni_stats[port_id].rx_dropped += nb_rx - num;\n }\n }\n }\n\nFor the other case that reads from kernel NIC interfaces and writes to a physical NIC port, packets are retrieved by reading\nmbufs from kernel NIC interfaces by `rte_kni_rx_burst()`.\nThe packet transmission is the same as in the L2 Forwarding sample application\n(see Section 9.4.6 \"Receive, Process and Transmit Packet's\").\n\n.. code-block:: c\n\n /**\n * Interface to dequeue mbufs from tx_q and burst tx\n */\n\n static void\n\n kni_egress(struct kni_port_params *p)\n {\n uint8_t i, nb_kni, port_id;\n unsigned nb_tx, num;\n struct rte_mbuf *pkts_burst[PKT_BURST_SZ];\n\n if (p == NULL)\n return;\n\n nb_kni = p->nb_kni;\n port_id = p->port_id;\n\n for (i = 0; i < nb_kni; i++) {\n /* Burst rx from kni */\n num = rte_kni_rx_burst(p->kni[i], pkts_burst, PKT_BURST_SZ);\n if (unlikely(num > PKT_BURST_SZ)) {\n RTE_LOG(ERR, APP, \"Error receiving from KNI\\n\");\n return;\n }\n\n /* Burst tx to eth */\n\n nb_tx = rte_eth_tx_burst(port_id, 0, pkts_burst, (uint16_t)num);\n\n kni_stats[port_id].tx_packets += nb_tx;\n\n if (unlikely(nb_tx < num)) {\n /* Free mbufs not tx to NIC */\n kni_burst_free_mbufs(&pkts_burst[nb_tx], num - nb_tx);\n kni_stats[port_id].tx_dropped += num - nb_tx;\n }\n }\n }\n\nCallbacks for Kernel Requests\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nTo execute specific PMD operations in user space requested by some Linux* commands,\ncallbacks must be implemented and filled in the struct rte_kni_ops structure.\nCurrently, setting a new MTU and configuring the network interface (up/ down) are supported.\n\n.. code-block:: c\n\n static struct rte_kni_ops kni_ops = {\n .change_mtu = kni_change_mtu,\n .config_network_if = kni_config_network_interface,\n };\n\n /* Callback for request of changing MTU */\n\n static int\n kni_change_mtu(uint8_t port_id, unsigned new_mtu)\n {\n int ret;\n struct rte_eth_conf conf;\n\n if (port_id >= rte_eth_dev_count()) {\n RTE_LOG(ERR, APP, \"Invalid port id %d\\n\", port_id);\n return -EINVAL;\n }\n\n RTE_LOG(INFO, APP, \"Change MTU of port %d to %u\\n\", port_id, new_mtu);\n\n /* Stop specific port */\n\n rte_eth_dev_stop(port_id);\n\n memcpy(&conf, &port_conf, sizeof(conf));\n\n /* Set new MTU */\n\n if (new_mtu > ETHER_MAX_LEN)\n conf.rxmode.jumbo_frame = 1;\n else\n conf.rxmode.jumbo_frame = 0;\n\n /* mtu + length of header + length of FCS = max pkt length */\n\n conf.rxmode.max_rx_pkt_len = new_mtu + KNI_ENET_HEADER_SIZE + KNI_ENET_FCS_SIZE;\n\n ret = rte_eth_dev_configure(port_id, 1, 1, &conf);\n if (ret < 0) {\n RTE_LOG(ERR, APP, \"Fail to reconfigure port %d\\n\", port_id);\n return ret;\n }\n\n /* Restart specific port */\n\n ret = rte_eth_dev_start(port_id);\n if (ret < 0) {\n RTE_LOG(ERR, APP, \"Fail to restart port %d\\n\", port_id);\n return ret;\n }\n\n return 0;\n }\n\n /* Callback for request of configuring network interface up/down */\n\n static int\n kni_config_network_interface(uint8_t port_id, uint8_t if_up)\n {\n int ret = 0;\n\n if (port_id >= rte_eth_dev_count() || port_id >= RTE_MAX_ETHPORTS) {\n RTE_LOG(ERR, APP, \"Invalid port id %d\\n\", port_id);\n return -EINVAL;\n }\n\n RTE_LOG(INFO, APP, \"Configure network interface of %d %s\\n\",\n\n port_id, if_up ? \"up\" : \"down\");\n\n if (if_up != 0) {\n /* Configure network interface up */\n rte_eth_dev_stop(port_id);\n ret = rte_eth_dev_start(port_id);\n } else /* Configure network interface down */\n rte_eth_dev_stop(port_id);\n\n if (ret < 0)\n RTE_LOG(ERR, APP, \"Failed to start port %d\\n\", port_id);\n return ret;\n }\n" }, { "path": "doc/guides/sample_app_ug/l2_forward_job_stats.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nL2 Forwarding Sample Application (in Real and Virtualized Environments) with core load statistics.\n==================================================================================================\n\nThe L2 Forwarding sample application is a simple example of packet processing using\nthe Data Plane Development Kit (DPDK) which\nalso takes advantage of Single Root I/O Virtualization (SR-IOV) features in a virtualized environment.\n\n.. note::\n\n This application is a variation of L2 Forwarding sample application. It demonstrate possible\n scheme of job stats library usage therefore some parts of this document is identical with original\n L2 forwarding application.\n\nOverview\n--------\n\nThe L2 Forwarding sample application, which can operate in real and virtualized environments,\nperforms L2 forwarding for each packet that is received.\nThe destination port is the adjacent port from the enabled portmask, that is,\nif the first four ports are enabled (portmask 0xf),\nports 1 and 2 forward into each other, and ports 3 and 4 forward into each other.\nAlso, the MAC addresses are affected as follows:\n\n* The source MAC address is replaced by the TX port MAC address\n\n* The destination MAC address is replaced by 02:00:00:00:00:TX_PORT_ID\n\nThis application can be used to benchmark performance using a traffic-generator, as shown in the :numref:`figure_l2_fwd_benchmark_setup_jobstats`.\n\nThe application can also be used in a virtualized environment as shown in :numref:`figure_l2_fwd_virtenv_benchmark_setup_jobstats`.\n\nThe L2 Forwarding application can also be used as a starting point for developing a new application based on the DPDK.\n\n.. _figure_l2_fwd_benchmark_setup_jobstats:\n\n.. figure:: img/l2_fwd_benchmark_setup.*\n\n Performance Benchmark Setup (Basic Environment)\n\n.. _figure_l2_fwd_virtenv_benchmark_setup_jobstats:\n\n.. figure:: img/l2_fwd_virtenv_benchmark_setup.*\n\n Performance Benchmark Setup (Virtualized Environment)\n\n\nVirtual Function Setup Instructions\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThis application can use the virtual function available in the system and\ntherefore can be used in a virtual machine without passing through\nthe whole Network Device into a guest machine in a virtualized scenario.\nThe virtual functions can be enabled in the host machine or the hypervisor with the respective physical function driver.\n\nFor example, in a Linux* host machine, it is possible to enable a virtual function using the following command:\n\n.. code-block:: console\n\n modprobe ixgbe max_vfs=2,2\n\nThis command enables two Virtual Functions on each of Physical Function of the NIC,\nwith two physical ports in the PCI configuration space.\nIt is important to note that enabled Virtual Function 0 and 2 would belong to Physical Function 0\nand Virtual Function 1 and 3 would belong to Physical Function 1,\nin this case enabling a total of four Virtual Functions.\n\nCompiling the Application\n-------------------------\n\n#. Go to the example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk cd ${RTE_SDK}/examples/l2fwd-jobstats\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n *See the DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nThe application requires a number of command line options:\n\n.. code-block:: console\n\n ./build/l2fwd-jobstats [EAL options] -- -p PORTMASK [-q NQ] [-l]\n\nwhere,\n\n* p PORTMASK: A hexadecimal bitmask of the ports to configure\n\n* q NQ: A number of queues (=ports) per lcore (default is 1)\n\n* l: Use locale thousands separator when formatting big numbers.\n\nTo run the application in linuxapp environment with 4 lcores, 16 ports, 8 RX queues per lcore and\nthousands separator printing, issue the command:\n\n.. code-block:: console\n\n $ ./build/l2fwd-jobstats -c f -n 4 -- -q 8 -p ffff -l\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications\nand the Environment Abstraction Layer (EAL) options.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of the code.\n\nCommand Line Arguments\n~~~~~~~~~~~~~~~~~~~~~~\n\nThe L2 Forwarding sample application takes specific parameters,\nin addition to Environment Abstraction Layer (EAL) arguments (see Section 9.3).\nThe preferred way to parse parameters is to use the getopt() function,\nsince it is part of a well-defined and portable library.\n\nThe parsing of arguments is done in the l2fwd_parse_args() function.\nThe method of argument parsing is not described here.\nRefer to the *glibc getopt(3)* man page for details.\n\nEAL arguments are parsed first, then application-specific arguments.\nThis is done at the beginning of the main() function:\n\n.. code-block:: c\n\n /* init EAL */\n\n ret = rte_eal_init(argc, argv);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Invalid EAL arguments\\n\");\n\n argc -= ret;\n argv += ret;\n\n /* parse application arguments (after the EAL ones) */\n\n ret = l2fwd_parse_args(argc, argv);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Invalid L2FWD arguments\\n\");\n\nMbuf Pool Initialization\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nOnce the arguments are parsed, the mbuf pool is created.\nThe mbuf pool contains a set of mbuf objects that will be used by the driver\nand the application to store network packet data:\n\n.. code-block:: c\n\n /* create the mbuf pool */\n l2fwd_pktmbuf_pool =\n rte_mempool_create(\"mbuf_pool\", NB_MBUF,\n MBUF_SIZE, 32,\n sizeof(struct rte_pktmbuf_pool_private),\n rte_pktmbuf_pool_init, NULL,\n rte_pktmbuf_init, NULL,\n rte_socket_id(), 0);\n\n if (l2fwd_pktmbuf_pool == NULL)\n rte_exit(EXIT_FAILURE, \"Cannot init mbuf pool\\n\");\n\nThe rte_mempool is a generic structure used to handle pools of objects.\nIn this case, it is necessary to create a pool that will be used by the driver,\nwhich expects to have some reserved space in the mempool structure,\nsizeof(struct rte_pktmbuf_pool_private) bytes.\nThe number of allocated pkt mbufs is NB_MBUF, with a size of MBUF_SIZE each.\nA per-lcore cache of 32 mbufs is kept.\nThe memory is allocated in rte_socket_id() socket,\nbut it is possible to extend this code to allocate one mbuf pool per socket.\n\nTwo callback pointers are also given to the rte_mempool_create() function:\n\n* The first callback pointer is to rte_pktmbuf_pool_init() and is used\n to initialize the private data of the mempool, which is needed by the driver.\n This function is provided by the mbuf API, but can be copied and extended by the developer.\n\n* The second callback pointer given to rte_mempool_create() is the mbuf initializer.\n The default is used, that is, rte_pktmbuf_init(), which is provided in the rte_mbuf library.\n If a more complex application wants to extend the rte_pktmbuf structure for its own needs,\n a new function derived from rte_pktmbuf_init( ) can be created.\n\nDriver Initialization\n~~~~~~~~~~~~~~~~~~~~~\n\nThe main part of the code in the main() function relates to the initialization of the driver.\nTo fully understand this code, it is recommended to study the chapters that related to the Poll Mode Driver\nin the *DPDK Programmer's Guide* and the *DPDK API Reference*.\n\n.. code-block:: c\n\n nb_ports = rte_eth_dev_count();\n\n if (nb_ports == 0)\n rte_exit(EXIT_FAILURE, \"No Ethernet ports - bye\\n\");\n\n if (nb_ports > RTE_MAX_ETHPORTS)\n nb_ports = RTE_MAX_ETHPORTS;\n\n /* reset l2fwd_dst_ports */\n\n for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++)\n l2fwd_dst_ports[portid] = 0;\n\n last_port = 0;\n\n /*\n * Each logical core is assigned a dedicated TX queue on each port.\n */\n for (portid = 0; portid < nb_ports; portid++) {\n /* skip ports that are not enabled */\n if ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n continue;\n\n if (nb_ports_in_mask % 2) {\n l2fwd_dst_ports[portid] = last_port;\n l2fwd_dst_ports[last_port] = portid;\n }\n else\n last_port = portid;\n\n nb_ports_in_mask++;\n\n rte_eth_dev_info_get((uint8_t) portid, &dev_info);\n }\n\nThe next step is to configure the RX and TX queues.\nFor each port, there is only one RX queue (only one lcore is able to poll a given port).\nThe number of TX queues depends on the number of available lcores.\nThe rte_eth_dev_configure() function is used to configure the number of queues for a port:\n\n.. code-block:: c\n\n ret = rte_eth_dev_configure((uint8_t)portid, 1, 1, &port_conf);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Cannot configure device: \"\n \"err=%d, port=%u\\n\",\n ret, portid);\n\nThe global configuration is stored in a static structure:\n\n.. code-block:: c\n\n static const struct rte_eth_conf port_conf = {\n .rxmode = {\n .split_hdr_size = 0,\n .header_split = 0, /**< Header Split disabled */\n .hw_ip_checksum = 0, /**< IP checksum offload disabled */\n .hw_vlan_filter = 0, /**< VLAN filtering disabled */\n .jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n .hw_strip_crc= 0, /**< CRC stripped by hardware */\n },\n\n .txmode = {\n .mq_mode = ETH_DCB_NONE\n },\n };\n\nRX Queue Initialization\n~~~~~~~~~~~~~~~~~~~~~~~\n\nThe application uses one lcore to poll one or several ports, depending on the -q option,\nwhich specifies the number of queues per lcore.\n\nFor example, if the user specifies -q 4, the application is able to poll four ports with one lcore.\nIf there are 16 ports on the target (and if the portmask argument is -p ffff ),\nthe application will need four lcores to poll all the ports.\n\n.. code-block:: c\n\n ret = rte_eth_rx_queue_setup(portid, 0, nb_rxd,\n rte_eth_dev_socket_id(portid),\n NULL,\n l2fwd_pktmbuf_pool);\n\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup:err=%d, port=%u\\n\",\n ret, (unsigned) portid);\n\nThe list of queues that must be polled for a given lcore is stored in a private structure called struct lcore_queue_conf.\n\n.. code-block:: c\n\n struct lcore_queue_conf {\n unsigned n_rx_port;\n unsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE];\n truct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];\n\n struct rte_timer rx_timers[MAX_RX_QUEUE_PER_LCORE];\n struct rte_jobstats port_fwd_jobs[MAX_RX_QUEUE_PER_LCORE];\n\n struct rte_timer flush_timer;\n struct rte_jobstats flush_job;\n struct rte_jobstats idle_job;\n struct rte_jobstats_context jobs_context;\n\n rte_atomic16_t stats_read_pending;\n rte_spinlock_t lock;\n } __rte_cache_aligned;\n\nValues of struct lcore_queue_conf:\n\n* n_rx_port and rx_port_list[] are used in the main packet processing loop\n (see Section 9.4.6 \"Receive, Process and Transmit Packets\" later in this chapter).\n\n* rx_timers and flush_timer are used to ensure forced TX on low packet rate.\n\n* flush_job, idle_job and jobs_context are librte_jobstats objects used for managing l2fwd jobs.\n\n* stats_read_pending and lock are used during job stats read phase.\n\nTX Queue Initialization\n~~~~~~~~~~~~~~~~~~~~~~~\n\nEach lcore should be able to transmit on any port. For every port, a single TX queue is initialized.\n\n.. code-block:: c\n\n /* init one TX queue on each port */\n\n fflush(stdout);\n ret = rte_eth_tx_queue_setup(portid, 0, nb_txd,\n rte_eth_dev_socket_id(portid),\n NULL);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup:err=%d, port=%u\\n\",\n ret, (unsigned) portid);\n\nJobs statistics initialization\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\nThere are several statistics objects available:\n\n* Flush job statistics\n\n.. code-block:: c\n\n rte_jobstats_init(&qconf->flush_job, \"flush\", drain_tsc, drain_tsc,\n drain_tsc, 0);\n\n rte_timer_init(&qconf->flush_timer);\n ret = rte_timer_reset(&qconf->flush_timer, drain_tsc, PERIODICAL,\n lcore_id, &l2fwd_flush_job, NULL);\n\n if (ret < 0) {\n rte_exit(1, \"Failed to reset flush job timer for lcore %u: %s\",\n lcore_id, rte_strerror(-ret));\n }\n\n* Statistics per RX port\n\n.. code-block:: c\n\n rte_jobstats_init(job, name, 0, drain_tsc, 0, MAX_PKT_BURST);\n rte_jobstats_set_update_period_function(job, l2fwd_job_update_cb);\n\n rte_timer_init(&qconf->rx_timers[i]);\n ret = rte_timer_reset(&qconf->rx_timers[i], 0, PERIODICAL, lcore_id,\n l2fwd_fwd_job, (void *)(uintptr_t)i);\n\n if (ret < 0) {\n rte_exit(1, \"Failed to reset lcore %u port %u job timer: %s\",\n lcore_id, qconf->rx_port_list[i], rte_strerror(-ret));\n }\n\nFollowing parameters are passed to rte_jobstats_init():\n\n* 0 as minimal poll period\n\n* drain_tsc as maximum poll period\n\n* MAX_PKT_BURST as desired target value (RX burst size)\n\nMain loop\n~~~~~~~~~\n\nThe forwarding path is reworked comparing to original L2 Forwarding application.\nIn the l2fwd_main_loop() function three loops are placed.\n\n.. code-block:: c\n\n for (;;) {\n rte_spinlock_lock(&qconf->lock);\n\n do {\n rte_jobstats_context_start(&qconf->jobs_context);\n\n /* Do the Idle job:\n * - Read stats_read_pending flag\n * - check if some real job need to be executed\n */\n rte_jobstats_start(&qconf->jobs_context, &qconf->idle_job);\n\n do {\n uint8_t i;\n uint64_t now = rte_get_timer_cycles();\n\n need_manage = qconf->flush_timer.expire < now;\n /* Check if we was esked to give a stats. */\n stats_read_pending =\n rte_atomic16_read(&qconf->stats_read_pending);\n need_manage |= stats_read_pending;\n\n for (i = 0; i < qconf->n_rx_port && !need_manage; i++)\n need_manage = qconf->rx_timers[i].expire < now;\n\n } while (!need_manage);\n rte_jobstats_finish(&qconf->idle_job, qconf->idle_job.target);\n\n rte_timer_manage();\n rte_jobstats_context_finish(&qconf->jobs_context);\n } while (likely(stats_read_pending == 0));\n\n rte_spinlock_unlock(&qconf->lock);\n rte_pause();\n }\n\nFirst infinite for loop is to minimize impact of stats reading. Lock is only locked/unlocked when asked.\n\nSecond inner while loop do the whole jobs management. When any job is ready, the use rte_timer_manage() is used to call the job handler.\nIn this place functions l2fwd_fwd_job() and l2fwd_flush_job() are called when needed.\nThen rte_jobstats_context_finish() is called to mark loop end - no other jobs are ready to execute. By this time stats are ready to be read\nand if stats_read_pending is set, loop breaks allowing stats to be read.\n\nThird do-while loop is the idle job (idle stats counter). Its only purpose is monitoring if any job is ready or stats job read is pending\nfor this lcore. Statistics from this part of code is considered as the headroom available for additional processing.\n\nReceive, Process and Transmit Packets\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe main task of l2fwd_fwd_job() function is to read ingress packets from the RX queue of particular port and forward it.\nThis is done using the following code:\n\n.. code-block:: c\n\n total_nb_rx = rte_eth_rx_burst((uint8_t) portid, 0, pkts_burst,\n MAX_PKT_BURST);\n\n for (j = 0; j < total_nb_rx; j++) {\n m = pkts_burst[j];\n rte_prefetch0(rte_pktmbuf_mtod(m, void *));\n l2fwd_simple_forward(m, portid);\n }\n\nPackets are read in a burst of size MAX_PKT_BURST.\nThen, each mbuf in the table is processed by the l2fwd_simple_forward() function.\nThe processing is very simple: process the TX port from the RX port, then replace the source and destination MAC addresses.\n\nThe rte_eth_rx_burst() function writes the mbuf pointers in a local table and returns the number of available mbufs in the table.\n\nAfter first read second try is issued.\n\n.. code-block:: c\n\n if (total_nb_rx == MAX_PKT_BURST) {\n const uint16_t nb_rx = rte_eth_rx_burst((uint8_t) portid, 0, pkts_burst,\n MAX_PKT_BURST);\n\n total_nb_rx += nb_rx;\n for (j = 0; j < nb_rx; j++) {\n m = pkts_burst[j];\n rte_prefetch0(rte_pktmbuf_mtod(m, void *));\n l2fwd_simple_forward(m, portid);\n }\n }\n\nThis second read is important to give job stats library a feedback how many packets was processed.\n\n.. code-block:: c\n\n /* Adjust period time in which we are running here. */\n if (rte_jobstats_finish(job, total_nb_rx) != 0) {\n rte_timer_reset(&qconf->rx_timers[port_idx], job->period, PERIODICAL,\n lcore_id, l2fwd_fwd_job, arg);\n }\n\nTo maximize performance exactly MAX_PKT_BURST is expected (the target value) to be read for each l2fwd_fwd_job() call.\nIf total_nb_rx is smaller than target value job->period will be increased. If it is greater the period will be decreased.\n\n.. note::\n\n In the following code, one line for getting the output port requires some explanation.\n\nDuring the initialization process, a static array of destination ports (l2fwd_dst_ports[]) is filled such that for each source port,\na destination port is assigned that is either the next or previous enabled port from the portmask.\nNaturally, the number of ports in the portmask must be even, otherwise, the application exits.\n\n.. code-block:: c\n\n static void\n l2fwd_simple_forward(struct rte_mbuf *m, unsigned portid)\n {\n struct ether_hdr *eth;\n void *tmp;\n unsigned dst_port;\n\n dst_port = l2fwd_dst_ports[portid];\n\n eth = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n /* 02:00:00:00:00:xx */\n\n tmp = ð->d_addr.addr_bytes[0];\n\n *((uint64_t *)tmp) = 0x000000000002 + ((uint64_t) dst_port << 40);\n\n /* src addr */\n\n ether_addr_copy(&l2fwd_ports_eth_addr[dst_port], ð->s_addr);\n\n l2fwd_send_packet(m, (uint8_t) dst_port);\n }\n\nThen, the packet is sent using the l2fwd_send_packet (m, dst_port) function.\nFor this test application, the processing is exactly the same for all packets arriving on the same RX port.\nTherefore, it would have been possible to call the l2fwd_send_burst() function directly from the main loop\nto send all the received packets on the same TX port,\nusing the burst-oriented send function, which is more efficient.\n\nHowever, in real-life applications (such as, L3 routing),\npacket N is not necessarily forwarded on the same port as packet N-1.\nThe application is implemented to illustrate that, so the same approach can be reused in a more complex application.\n\nThe l2fwd_send_packet() function stores the packet in a per-lcore and per-txport table.\nIf the table is full, the whole packets table is transmitted using the l2fwd_send_burst() function:\n\n.. code-block:: c\n\n /* Send the packet on an output interface */\n\n static int\n l2fwd_send_packet(struct rte_mbuf *m, uint8_t port)\n {\n unsigned lcore_id, len;\n struct lcore_queue_conf *qconf;\n\n lcore_id = rte_lcore_id();\n qconf = &lcore_queue_conf[lcore_id];\n len = qconf->tx_mbufs[port].len;\n qconf->tx_mbufs[port].m_table[len] = m;\n len++;\n\n /* enough pkts to be sent */\n\n if (unlikely(len == MAX_PKT_BURST)) {\n l2fwd_send_burst(qconf, MAX_PKT_BURST, port);\n len = 0;\n }\n\n qconf->tx_mbufs[port].len = len; return 0;\n }\n\nTo ensure that no packets remain in the tables, the flush job exists. The l2fwd_flush_job()\nis called periodically to for each lcore draining TX queue of each port.\nThis technique introduces some latency when there are not many packets to send,\nhowever it improves performance:\n\n.. code-block:: c\n\n static void\n l2fwd_flush_job(__rte_unused struct rte_timer *timer, __rte_unused void *arg)\n {\n uint64_t now;\n unsigned lcore_id;\n struct lcore_queue_conf *qconf;\n struct mbuf_table *m_table;\n uint8_t portid;\n\n lcore_id = rte_lcore_id();\n qconf = &lcore_queue_conf[lcore_id];\n\n rte_jobstats_start(&qconf->jobs_context, &qconf->flush_job);\n\n now = rte_get_timer_cycles();\n lcore_id = rte_lcore_id();\n qconf = &lcore_queue_conf[lcore_id];\n for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n m_table = &qconf->tx_mbufs[portid];\n if (m_table->len == 0 || m_table->next_flush_time <= now)\n continue;\n\n l2fwd_send_burst(qconf, portid);\n }\n\n\n /* Pass target to indicate that this job is happy of time interval\n * in which it was called. */\n rte_jobstats_finish(&qconf->flush_job, qconf->flush_job.target);\n }\n" }, { "path": "doc/guides/sample_app_ug/l2_forward_real_virtual.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nL2 Forwarding Sample Application (in Real and Virtualized Environments)\n=======================================================================\n\nThe L2 Forwarding sample application is a simple example of packet processing using\nthe Data Plane Development Kit (DPDK) which\nalso takes advantage of Single Root I/O Virtualization (SR-IOV) features in a virtualized environment.\n\n.. note::\n\n Please note that previously a separate L2 Forwarding in Virtualized Environments sample application was used,\n however, in later DPDK versions these sample applications have been merged.\n\nOverview\n--------\n\nThe L2 Forwarding sample application, which can operate in real and virtualized environments,\nperforms L2 forwarding for each packet that is received on an RX_PORT.\nThe destination port is the adjacent port from the enabled portmask, that is,\nif the first four ports are enabled (portmask 0xf),\nports 1 and 2 forward into each other, and ports 3 and 4 forward into each other.\nAlso, the MAC addresses are affected as follows:\n\n* The source MAC address is replaced by the TX_PORT MAC address\n\n* The destination MAC address is replaced by 02:00:00:00:00:TX_PORT_ID\n\nThis application can be used to benchmark performance using a traffic-generator, as shown in the :numref:`figure_l2_fwd_benchmark_setup`.\n\nThe application can also be used in a virtualized environment as shown in :numref:`figure_l2_fwd_virtenv_benchmark_setup`.\n\nThe L2 Forwarding application can also be used as a starting point for developing a new application based on the DPDK.\n\n.. _figure_l2_fwd_benchmark_setup:\n\n.. figure:: img/l2_fwd_benchmark_setup.*\n\n Performance Benchmark Setup (Basic Environment)\n\n\n.. _figure_l2_fwd_virtenv_benchmark_setup:\n\n.. figure:: img/l2_fwd_virtenv_benchmark_setup.*\n\n Performance Benchmark Setup (Virtualized Environment)\n\n\nVirtual Function Setup Instructions\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThis application can use the virtual function available in the system and\ntherefore can be used in a virtual machine without passing through\nthe whole Network Device into a guest machine in a virtualized scenario.\nThe virtual functions can be enabled in the host machine or the hypervisor with the respective physical function driver.\n\nFor example, in a Linux* host machine, it is possible to enable a virtual function using the following command:\n\n.. code-block:: console\n\n modprobe ixgbe max_vfs=2,2\n\nThis command enables two Virtual Functions on each of Physical Function of the NIC,\nwith two physical ports in the PCI configuration space.\nIt is important to note that enabled Virtual Function 0 and 2 would belong to Physical Function 0\nand Virtual Function 1 and 3 would belong to Physical Function 1,\nin this case enabling a total of four Virtual Functions.\n\nCompiling the Application\n-------------------------\n\n#. Go to the example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk cd ${RTE_SDK}/examples/l2fwd\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n *See the DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nThe application requires a number of command line options:\n\n.. code-block:: console\n\n ./build/l2fwd [EAL options] -- -p PORTMASK [-q NQ]\n\nwhere,\n\n* p PORTMASK: A hexadecimal bitmask of the ports to configure\n\n* q NQ: A number of queues (=ports) per lcore (default is 1)\n\nTo run the application in linuxapp environment with 4 lcores, 16 ports and 8 RX queues per lcore, issue the command:\n\n.. code-block:: console\n\n $ ./build/l2fwd -c f -n 4 -- -q 8 -p ffff\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications\nand the Environment Abstraction Layer (EAL) options.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of the code.\n\nCommand Line Arguments\n~~~~~~~~~~~~~~~~~~~~~~\n\nThe L2 Forwarding sample application takes specific parameters,\nin addition to Environment Abstraction Layer (EAL) arguments (see Section 9.3).\nThe preferred way to parse parameters is to use the getopt() function,\nsince it is part of a well-defined and portable library.\n\nThe parsing of arguments is done in the l2fwd_parse_args() function.\nThe method of argument parsing is not described here.\nRefer to the *glibc getopt(3)* man page for details.\n\nEAL arguments are parsed first, then application-specific arguments.\nThis is done at the beginning of the main() function:\n\n.. code-block:: c\n\n /* init EAL */\n\n ret = rte_eal_init(argc, argv);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Invalid EAL arguments\\n\");\n\n argc -= ret;\n argv += ret;\n\n /* parse application arguments (after the EAL ones) */\n\n ret = l2fwd_parse_args(argc, argv);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Invalid L2FWD arguments\\n\");\n\nMbuf Pool Initialization\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nOnce the arguments are parsed, the mbuf pool is created.\nThe mbuf pool contains a set of mbuf objects that will be used by the driver\nand the application to store network packet data:\n\n.. code-block:: c\n\n /* create the mbuf pool */\n\n l2fwd_pktmbuf_pool = rte_mempool_create(\"mbuf_pool\", NB_MBUF, MBUF_SIZE, 32, sizeof(struct rte_pktmbuf_pool_private),\n rte_pktmbuf_pool_init, NULL, rte_pktmbuf_init, NULL, SOCKET0, 0);\n\n if (l2fwd_pktmbuf_pool == NULL)\n rte_panic(\"Cannot init mbuf pool\\n\");\n\nThe rte_mempool is a generic structure used to handle pools of objects.\nIn this case, it is necessary to create a pool that will be used by the driver,\nwhich expects to have some reserved space in the mempool structure,\nsizeof(struct rte_pktmbuf_pool_private) bytes.\nThe number of allocated pkt mbufs is NB_MBUF, with a size of MBUF_SIZE each.\nA per-lcore cache of 32 mbufs is kept.\nThe memory is allocated in NUMA socket 0,\nbut it is possible to extend this code to allocate one mbuf pool per socket.\n\nTwo callback pointers are also given to the rte_mempool_create() function:\n\n* The first callback pointer is to rte_pktmbuf_pool_init() and is used\n to initialize the private data of the mempool, which is needed by the driver.\n This function is provided by the mbuf API, but can be copied and extended by the developer.\n\n* The second callback pointer given to rte_mempool_create() is the mbuf initializer.\n The default is used, that is, rte_pktmbuf_init(), which is provided in the rte_mbuf library.\n If a more complex application wants to extend the rte_pktmbuf structure for its own needs,\n a new function derived from rte_pktmbuf_init( ) can be created.\n\nDriver Initialization\n~~~~~~~~~~~~~~~~~~~~~\n\nThe main part of the code in the main() function relates to the initialization of the driver.\nTo fully understand this code, it is recommended to study the chapters that related to the Poll Mode Driver\nin the *DPDK Programmer's Guide* - Rel 1.4 EAR and the *DPDK API Reference*.\n\n.. code-block:: c\n\n if (rte_eal_pci_probe() < 0)\n rte_exit(EXIT_FAILURE, \"Cannot probe PCI\\n\");\n\n nb_ports = rte_eth_dev_count();\n\n if (nb_ports == 0)\n rte_exit(EXIT_FAILURE, \"No Ethernet ports - bye\\n\");\n\n if (nb_ports > RTE_MAX_ETHPORTS)\n nb_ports = RTE_MAX_ETHPORTS;\n\n /* reset l2fwd_dst_ports */\n\n for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++)\n l2fwd_dst_ports[portid] = 0;\n\n last_port = 0;\n\n /*\n * Each logical core is assigned a dedicated TX queue on each port.\n */\n\n for (portid = 0; portid < nb_ports; portid++) {\n /* skip ports that are not enabled */\n\n if ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n continue;\n\n if (nb_ports_in_mask % 2) {\n l2fwd_dst_ports[portid] = last_port;\n l2fwd_dst_ports[last_port] = portid;\n }\n else\n last_port = portid;\n\n nb_ports_in_mask++;\n\n rte_eth_dev_info_get((uint8_t) portid, &dev_info);\n }\n\nObserve that:\n\n* rte_igb_pmd_init_all() simultaneously registers the driver as a PCI driver and as an Ethernet* Poll Mode Driver.\n\n* rte_eal_pci_probe() parses the devices on the PCI bus and initializes recognized devices.\n\nThe next step is to configure the RX and TX queues.\nFor each port, there is only one RX queue (only one lcore is able to poll a given port).\nThe number of TX queues depends on the number of available lcores.\nThe rte_eth_dev_configure() function is used to configure the number of queues for a port:\n\n.. code-block:: c\n\n ret = rte_eth_dev_configure((uint8_t)portid, 1, 1, &port_conf);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Cannot configure device: \"\n \"err=%d, port=%u\\n\",\n ret, portid);\n\nThe global configuration is stored in a static structure:\n\n.. code-block:: c\n\n static const struct rte_eth_conf port_conf = {\n .rxmode = {\n .split_hdr_size = 0,\n .header_split = 0, /**< Header Split disabled */\n .hw_ip_checksum = 0, /**< IP checksum offload disabled */\n .hw_vlan_filter = 0, /**< VLAN filtering disabled */\n .jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n .hw_strip_crc= 0, /**< CRC stripped by hardware */\n },\n\n .txmode = {\n .mq_mode = ETH_DCB_NONE\n },\n };\n\nRX Queue Initialization\n~~~~~~~~~~~~~~~~~~~~~~~\n\nThe application uses one lcore to poll one or several ports, depending on the -q option,\nwhich specifies the number of queues per lcore.\n\nFor example, if the user specifies -q 4, the application is able to poll four ports with one lcore.\nIf there are 16 ports on the target (and if the portmask argument is -p ffff ),\nthe application will need four lcores to poll all the ports.\n\n.. code-block:: c\n\n ret = rte_eth_rx_queue_setup((uint8_t) portid, 0, nb_rxd, SOCKET0, &rx_conf, l2fwd_pktmbuf_pool);\n if (ret < 0)\n\n rte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup: \"\n \"err=%d, port=%u\\n\",\n ret, portid);\n\nThe list of queues that must be polled for a given lcore is stored in a private structure called struct lcore_queue_conf.\n\n.. code-block:: c\n\n struct lcore_queue_conf {\n unsigned n_rx_port;\n unsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE];\n struct mbuf_table tx_mbufs[L2FWD_MAX_PORTS];\n } rte_cache_aligned;\n\n struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];\n\nThe values n_rx_port and rx_port_list[] are used in the main packet processing loop\n(see Section 9.4.6 \"Receive, Process and Transmit Packets\" later in this chapter).\n\nThe global configuration for the RX queues is stored in a static structure:\n\n.. code-block:: c\n\n static const struct rte_eth_rxconf rx_conf = {\n .rx_thresh = {\n .pthresh = RX_PTHRESH,\n .hthresh = RX_HTHRESH,\n .wthresh = RX_WTHRESH,\n },\n };\n\nTX Queue Initialization\n~~~~~~~~~~~~~~~~~~~~~~~\n\nEach lcore should be able to transmit on any port. For every port, a single TX queue is initialized.\n\n.. code-block:: c\n\n /* init one TX queue on each port */\n\n fflush(stdout);\n\n ret = rte_eth_tx_queue_setup((uint8_t) portid, 0, nb_txd, rte_eth_dev_socket_id(portid), &tx_conf);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup:err=%d, port=%u\\n\", ret, (unsigned) portid);\n\nThe global configuration for TX queues is stored in a static structure:\n\n.. code-block:: c\n\n static const struct rte_eth_txconf tx_conf = {\n .tx_thresh = {\n .pthresh = TX_PTHRESH,\n .hthresh = TX_HTHRESH,\n .wthresh = TX_WTHRESH,\n },\n .tx_free_thresh = RTE_TEST_TX_DESC_DEFAULT + 1, /* disable feature */\n };\n\nReceive, Process and Transmit Packets\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nIn the l2fwd_main_loop() function, the main task is to read ingress packets from the RX queues.\nThis is done using the following code:\n\n.. code-block:: c\n\n /*\n * Read packet from RX queues\n */\n\n for (i = 0; i < qconf->n_rx_port; i++) {\n portid = qconf->rx_port_list[i];\n nb_rx = rte_eth_rx_burst((uint8_t) portid, 0, pkts_burst, MAX_PKT_BURST);\n\n for (j = 0; j < nb_rx; j++) {\n m = pkts_burst[j];\n rte_prefetch0[rte_pktmbuf_mtod(m, void *)); l2fwd_simple_forward(m, portid);\n }\n }\n\nPackets are read in a burst of size MAX_PKT_BURST.\nThe rte_eth_rx_burst() function writes the mbuf pointers in a local table and returns the number of available mbufs in the table.\n\nThen, each mbuf in the table is processed by the l2fwd_simple_forward() function.\nThe processing is very simple: process the TX port from the RX port, then replace the source and destination MAC addresses.\n\n.. note::\n\n In the following code, one line for getting the output port requires some explanation.\n\nDuring the initialization process, a static array of destination ports (l2fwd_dst_ports[]) is filled such that for each source port,\na destination port is assigned that is either the next or previous enabled port from the portmask.\nNaturally, the number of ports in the portmask must be even, otherwise, the application exits.\n\n.. code-block:: c\n\n static void\n l2fwd_simple_forward(struct rte_mbuf *m, unsigned portid)\n {\n struct ether_hdr *eth;\n void *tmp;\n unsigned dst_port;\n\n dst_port = l2fwd_dst_ports[portid];\n\n eth = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n /* 02:00:00:00:00:xx */\n\n tmp = ð->d_addr.addr_bytes[0];\n\n *((uint64_t *)tmp) = 0x000000000002 + ((uint64_t) dst_port << 40);\n\n /* src addr */\n\n ether_addr_copy(&l2fwd_ports_eth_addr[dst_port], ð->s_addr);\n\n l2fwd_send_packet(m, (uint8_t) dst_port);\n }\n\nThen, the packet is sent using the l2fwd_send_packet (m, dst_port) function.\nFor this test application, the processing is exactly the same for all packets arriving on the same RX port.\nTherefore, it would have been possible to call the l2fwd_send_burst() function directly from the main loop\nto send all the received packets on the same TX port,\nusing the burst-oriented send function, which is more efficient.\n\nHowever, in real-life applications (such as, L3 routing),\npacket N is not necessarily forwarded on the same port as packet N-1.\nThe application is implemented to illustrate that, so the same approach can be reused in a more complex application.\n\nThe l2fwd_send_packet() function stores the packet in a per-lcore and per-txport table.\nIf the table is full, the whole packets table is transmitted using the l2fwd_send_burst() function:\n\n.. code-block:: c\n\n /* Send the packet on an output interface */\n\n static int\n l2fwd_send_packet(struct rte_mbuf *m, uint8_t port)\n {\n unsigned lcore_id, len;\n struct lcore_queue_conf \\*qconf;\n\n lcore_id = rte_lcore_id();\n qconf = &lcore_queue_conf[lcore_id];\n len = qconf->tx_mbufs[port].len;\n qconf->tx_mbufs[port].m_table[len] = m;\n len++;\n\n /* enough pkts to be sent */\n\n if (unlikely(len == MAX_PKT_BURST)) {\n l2fwd_send_burst(qconf, MAX_PKT_BURST, port);\n len = 0;\n }\n\n qconf->tx_mbufs[port].len = len; return 0;\n }\n\nTo ensure that no packets remain in the tables, each lcore does a draining of TX queue in its main loop.\nThis technique introduces some latency when there are not many packets to send,\nhowever it improves performance:\n\n.. code-block:: c\n\n cur_tsc = rte_rdtsc();\n\n /*\n * TX burst queue drain\n */\n\n diff_tsc = cur_tsc - prev_tsc;\n\n if (unlikely(diff_tsc > drain_tsc)) {\n for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n if (qconf->tx_mbufs[portid].len == 0)\n continue;\n\n l2fwd_send_burst(&lcore_queue_conf[lcore_id], qconf->tx_mbufs[portid].len, (uint8_t) portid);\n\n qconf->tx_mbufs[portid].len = 0;\n }\n\n /* if timer is enabled */\n\n if (timer_period > 0) {\n /* advance the timer */\n\n timer_tsc += diff_tsc;\n\n /* if timer has reached its timeout */\n\n if (unlikely(timer_tsc >= (uint64_t) timer_period)) {\n /* do this only on master core */\n\n if (lcore_id == rte_get_master_lcore()) {\n print_stats();\n\n /* reset the timer */\n timer_tsc = 0;\n }\n }\n }\n\n prev_tsc = cur_tsc;\n }\n" }, { "path": "doc/guides/sample_app_ug/l3_forward.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nL3 Forwarding Sample Application\n================================\n\nThe L3 Forwarding application is a simple example of packet processing using the DPDK.\nThe application performs L3 forwarding.\n\nOverview\n--------\n\nThe application demonstrates the use of the hash and LPM libraries in the DPDK to implement packet forwarding.\nThe initialization and run-time paths are very similar to those of the L2 forwarding application\n(see Chapter 9 \"L2 Forwarding Sample Application (in Real and Virtualized Environments)\" for more information).\nThe main difference from the L2 Forwarding sample application is that the forwarding decision\nis made based on information read from the input packet.\n\nThe lookup method is either hash-based or LPM-based and is selected at compile time. When the selected lookup method is hash-based,\na hash object is used to emulate the flow classification stage.\nThe hash object is used in correlation with a flow table to map each input packet to its flow at runtime.\n\nThe hash lookup key is represented by a DiffServ 5-tuple composed of the following fields read from the input packet:\nSource IP Address, Destination IP Address, Protocol, Source Port and Destination Port.\nThe ID of the output interface for the input packet is read from the identified flow table entry.\nThe set of flows used by the application is statically configured and loaded into the hash at initialization time.\nWhen the selected lookup method is LPM based, an LPM object is used to emulate the forwarding stage for IPv4 packets.\nThe LPM object is used as the routing table to identify the next hop for each input packet at runtime.\n\nThe LPM lookup key is represented by the Destination IP Address field read from the input packet.\nThe ID of the output interface for the input packet is the next hop returned by the LPM lookup.\nThe set of LPM rules used by the application is statically configured and loaded into the LPM object at initialization time.\n\nIn the sample application, hash-based forwarding supports IPv4 and IPv6. LPM-based forwarding supports IPv4 only.\n\nCompiling the Application\n-------------------------\n\nTo compile the application:\n\n#. Go to the sample application directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk cd ${RTE_SDK}/examples/l3fwd\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nThe application has a number of command line options:\n\n.. code-block:: console\n\n ./build/l3fwd [EAL options] -- -p PORTMASK [-P] --config(port,queue,lcore)[,(port,queue,lcore)] [--enable-jumbo [--max-pkt-len PKTLEN]] [--no-numa][--hash-entry-num][--ipv6]\n\nwhere,\n\n* -p PORTMASK: Hexadecimal bitmask of ports to configure\n\n* -P: optional, sets all ports to promiscuous mode so that packets are accepted regardless of the packet's Ethernet MAC destination address.\n Without this option, only packets with the Ethernet MAC destination address set to the Ethernet address of the port are accepted.\n\n* --config (port,queue,lcore)[,(port,queue,lcore)]: determines which queues from which ports are mapped to which cores\n\n* --enable-jumbo: optional, enables jumbo frames\n\n* --max-pkt-len: optional, maximum packet length in decimal (64-9600)\n\n* --no-numa: optional, disables numa awareness\n\n* --hash-entry-num: optional, specifies the hash entry number in hexadecimal to be setup\n\n* --ipv6: optional, set it if running ipv6 packets\n\nFor example, consider a dual processor socket platform where cores 0-7 and 16-23 appear on socket 0, while cores 8-15 and 24-31 appear on socket 1.\nLet's say that the programmer wants to use memory from both NUMA nodes, the platform has only two ports, one connected to each NUMA node,\nand the programmer wants to use two cores from each processor socket to do the packet processing.\n\nTo enable L3 forwarding between two ports, using two cores, cores 1 and 2, from each processor,\nwhile also taking advantage of local memory access by optimizing around NUMA, the programmer must enable two queues from each port,\npin to the appropriate cores and allocate memory from the appropriate NUMA node. This is achieved using the following command:\n\n.. code-block:: console\n\n ./build/l3fwd -c 606 -n 4 -- -p 0x3 --config=\"(0,0,1),(0,1,2),(1,0,9),(1,1,10)\"\n\nIn this command:\n\n* The -c option enables cores 0, 1, 2, 3\n\n* The -p option enables ports 0 and 1\n\n* The --config option enables two queues on each port and maps each (port,queue) pair to a specific core.\n Logic to enable multiple RX queues using RSS and to allocate memory from the correct NUMA nodes\n is included in the application and is done transparently.\n The following table shows the mapping in this example:\n\n+----------+-----------+-----------+-------------------------------------+\n| **Port** | **Queue** | **lcore** | **Description** |\n| | | | |\n+----------+-----------+-----------+-------------------------------------+\n| 0 | 0 | 0 | Map queue 0 from port 0 to lcore 0. |\n| | | | |\n+----------+-----------+-----------+-------------------------------------+\n| 0 | 1 | 2 | Map queue 1 from port 0 to lcore 2. |\n| | | | |\n+----------+-----------+-----------+-------------------------------------+\n| 1 | 0 | 1 | Map queue 0 from port 1 to lcore 1. |\n| | | | |\n+----------+-----------+-----------+-------------------------------------+\n| 1 | 1 | 3 | Map queue 1 from port 1 to lcore 3. |\n| | | | |\n+----------+-----------+-----------+-------------------------------------+\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications and\nthe Environment Abstraction Layer (EAL) options.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of the sample application code. As mentioned in the overview section,\nthe initialization and run-time paths are very similar to those of the L2 forwarding application\n(see Chapter 9 \"L2 Forwarding Sample Application (in Real and Virtualized Environments)\" for more information).\nThe following sections describe aspects that are specific to the L3 Forwarding sample application.\n\nHash Initialization\n~~~~~~~~~~~~~~~~~~~\n\nThe hash object is created and loaded with the pre-configured entries read from a global array,\nand then generate the expected 5-tuple as key to keep consistence with those of real flow\nfor the convenience to execute hash performance test on 4M/8M/16M flows.\n\n.. note::\n\n The Hash initialization will setup both ipv4 and ipv6 hash table,\n and populate the either table depending on the value of variable ipv6.\n To support the hash performance test with up to 8M single direction flows/16M bi-direction flows,\n populate_ipv4_many_flow_into_table() function will populate the hash table with specified hash table entry number(default 4M).\n\n.. note::\n\n Value of global variable ipv6 can be specified with --ipv6 in the command line.\n Value of global variable hash_entry_number,\n which is used to specify the total hash entry number for all used ports in hash performance test,\n can be specified with --hash-entry-num VALUE in command line, being its default value 4.\n\n.. code-block:: c\n\n #if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n\n static void\n setup_hash(int socketid)\n {\n // ...\n\n if (hash_entry_number != HASH_ENTRY_NUMBER_DEFAULT) {\n if (ipv6 == 0) {\n /* populate the ipv4 hash */\n populate_ipv4_many_flow_into_table(ipv4_l3fwd_lookup_struct[socketid], hash_entry_number);\n } else {\n /* populate the ipv6 hash */\n populate_ipv6_many_flow_into_table( ipv6_l3fwd_lookup_struct[socketid], hash_entry_number);\n }\n } else\n if (ipv6 == 0) {\n /* populate the ipv4 hash */\n populate_ipv4_few_flow_into_table(ipv4_l3fwd_lookup_struct[socketid]);\n } else {\n /* populate the ipv6 hash */\n populate_ipv6_few_flow_into_table(ipv6_l3fwd_lookup_struct[socketid]);\n }\n }\n }\n #endif\n\nLPM Initialization\n~~~~~~~~~~~~~~~~~~\n\nThe LPM object is created and loaded with the pre-configured entries read from a global array.\n\n.. code-block:: c\n\n #if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\n\n static void\n setup_lpm(int socketid)\n {\n unsigned i;\n int ret;\n char s[64];\n\n /* create the LPM table */\n\n rte_snprintf(s, sizeof(s), \"IPV4_L3FWD_LPM_%d\", socketid);\n\n ipv4_l3fwd_lookup_struct[socketid] = rte_lpm_create(s, socketid, IPV4_L3FWD_LPM_MAX_RULES, 0);\n\n if (ipv4_l3fwd_lookup_struct[socketid] == NULL)\n rte_exit(EXIT_FAILURE, \"Unable to create the l3fwd LPM table\"\n \" on socket %d\\n\", socketid);\n\n /* populate the LPM table */\n\n for (i = 0; i < IPV4_L3FWD_NUM_ROUTES; i++) {\n /* skip unused ports */\n\n if ((1 << ipv4_l3fwd_route_array[i].if_out & enabled_port_mask) == 0)\n continue;\n\n ret = rte_lpm_add(ipv4_l3fwd_lookup_struct[socketid], ipv4_l3fwd_route_array[i].ip,\n \t ipv4_l3fwd_route_array[i].depth, ipv4_l3fwd_route_array[i].if_out);\n\n if (ret < 0) {\n rte_exit(EXIT_FAILURE, \"Unable to add entry %u to the \"\n \"l3fwd LPM table on socket %d\\n\", i, socketid);\n }\n\n printf(\"LPM: Adding route 0x%08x / %d (%d)\\n\",\n (unsigned)ipv4_l3fwd_route_array[i].ip, ipv4_l3fwd_route_array[i].depth, ipv4_l3fwd_route_array[i].if_out);\n }\n }\n #endif\n\nPacket Forwarding for Hash-based Lookups\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nFor each input packet, the packet forwarding operation is done by the l3fwd_simple_forward()\nor simple_ipv4_fwd_4pkts() function for IPv4 packets or the simple_ipv6_fwd_4pkts() function for IPv6 packets.\nThe l3fwd_simple_forward() function provides the basic functionality for both IPv4 and IPv6 packet forwarding\nfor any number of burst packets received,\nand the packet forwarding decision (that is, the identification of the output interface for the packet)\nfor hash-based lookups is done by the get_ipv4_dst_port() or get_ipv6_dst_port() function.\nThe get_ipv4_dst_port() function is shown below:\n\n.. code-block:: c\n\n static inline uint8_t\n get_ipv4_dst_port(void *ipv4_hdr, uint8_t portid, lookup_struct_t *ipv4_l3fwd_lookup_struct)\n {\n int ret = 0;\n union ipv4_5tuple_host key;\n\n ipv4_hdr = (uint8_t \\*)ipv4_hdr + offsetof(struct ipv4_hdr, time_to_live);\n\n m128i data = _mm_loadu_si128(( m128i*)(ipv4_hdr));\n\n /* Get 5 tuple: dst port, src port, dst IP address, src IP address and protocol */\n\n key.xmm = _mm_and_si128(data, mask0);\n\n /* Find destination port */\n\n ret = rte_hash_lookup(ipv4_l3fwd_lookup_struct, (const void *)&key);\n\n return (uint8_t)((ret < 0)? portid : ipv4_l3fwd_out_if[ret]);\n }\n\nThe get_ipv6_dst_port() function is similar to the get_ipv4_dst_port() function.\n\nThe simple_ipv4_fwd_4pkts() and simple_ipv6_fwd_4pkts() function are optimized for continuous 4 valid ipv4 and ipv6 packets,\nthey leverage the multiple buffer optimization to boost the performance of forwarding packets with the exact match on hash table.\nThe key code snippet of simple_ipv4_fwd_4pkts() is shown below:\n\n.. code-block:: c\n\n static inline void\n simple_ipv4_fwd_4pkts(struct rte_mbuf* m[4], uint8_t portid, struct lcore_conf *qconf)\n {\n // ...\n\n data[0] = _mm_loadu_si128(( m128i*)(rte_pktmbuf_mtod(m[0], unsigned char *) + sizeof(struct ether_hdr) + offsetof(struct ipv4_hdr, time_to_live)));\n data[1] = _mm_loadu_si128(( m128i*)(rte_pktmbuf_mtod(m[1], unsigned char *) + sizeof(struct ether_hdr) + offsetof(struct ipv4_hdr, time_to_live)));\n data[2] = _mm_loadu_si128(( m128i*)(rte_pktmbuf_mtod(m[2], unsigned char *) + sizeof(struct ether_hdr) + offsetof(struct ipv4_hdr, time_to_live)));\n data[3] = _mm_loadu_si128(( m128i*)(rte_pktmbuf_mtod(m[3], unsigned char *) + sizeof(struct ether_hdr) + offsetof(struct ipv4_hdr, time_to_live)));\n\n key[0].xmm = _mm_and_si128(data[0], mask0);\n key[1].xmm = _mm_and_si128(data[1], mask0);\n key[2].xmm = _mm_and_si128(data[2], mask0);\n key[3].xmm = _mm_and_si128(data[3], mask0);\n\n const void *key_array[4] = {&key[0], &key[1], &key[2],&key[3]};\n\n rte_hash_lookup_multi(qconf->ipv4_lookup_struct, &key_array[0], 4, ret);\n\n dst_port[0] = (ret[0] < 0)? portid:ipv4_l3fwd_out_if[ret[0]];\n dst_port[1] = (ret[1] < 0)? portid:ipv4_l3fwd_out_if[ret[1]];\n dst_port[2] = (ret[2] < 0)? portid:ipv4_l3fwd_out_if[ret[2]];\n dst_port[3] = (ret[3] < 0)? portid:ipv4_l3fwd_out_if[ret[3]];\n\n // ...\n }\n\nThe simple_ipv6_fwd_4pkts() function is similar to the simple_ipv4_fwd_4pkts() function.\n\nPacket Forwarding for LPM-based Lookups\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nFor each input packet, the packet forwarding operation is done by the l3fwd_simple_forward() function,\nbut the packet forwarding decision (that is, the identification of the output interface for the packet)\nfor LPM-based lookups is done by the get_ipv4_dst_port() function below:\n\n.. code-block:: c\n\n static inline uint8_t\n get_ipv4_dst_port(struct ipv4_hdr *ipv4_hdr, uint8_t portid, lookup_struct_t *ipv4_l3fwd_lookup_struct)\n {\n uint8_t next_hop;\n\n return (uint8_t) ((rte_lpm_lookup(ipv4_l3fwd_lookup_struct, rte_be_to_cpu_32(ipv4_hdr->dst_addr), &next_hop) == 0)? next_hop : portid);\n }\n" }, { "path": "doc/guides/sample_app_ug/l3_forward_access_ctrl.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nL3 Forwarding with Access Control Sample Application\n====================================================\n\nThe L3 Forwarding with Access Control application is a simple example of packet processing using the DPDK.\nThe application performs a security check on received packets.\nPackets that are in the Access Control List (ACL), which is loaded during initialization, are dropped.\nOthers are forwarded to the correct port.\n\nOverview\n--------\n\nThe application demonstrates the use of the ACL library in the DPDK to implement access control\nand packet L3 forwarding.\nThe application loads two types of rules at initialization:\n\n* Route information rules, which are used for L3 forwarding\n\n* Access Control List (ACL) rules that blacklist (or block) packets with a specific characteristic\n\nWhen packets are received from a port,\nthe application extracts the necessary information from the TCP/IP header of the received packet and\nperforms a lookup in the rule database to figure out whether the packets should be dropped (in the ACL range)\nor forwarded to desired ports.\nThe initialization and run-time paths are similar to those of the L3 forwarding application\n(see Chapter 10, \"L3 Forwarding Sample Application\" for more information).\nHowever, there are significant differences in the two applications.\nFor example, the original L3 forwarding application uses either LPM or\nan exact match algorithm to perform forwarding port lookup,\nwhile this application uses the ACL library to perform both ACL and route entry lookup.\nThe following sections provide more detail.\n\nClassification for both IPv4 and IPv6 packets is supported in this application.\nThe application also assumes that all the packets it processes are TCP/UDP packets and\nalways extracts source/destination port information from the packets.\n\nTuple Packet Syntax\n~~~~~~~~~~~~~~~~~~~\n\nThe application implements packet classification for the IPv4/IPv6 5-tuple syntax specifically.\nThe 5-tuple syntax consist of a source IP address, a destination IP address,\na source port, a destination port and a protocol identifier.\nThe fields in the 5-tuple syntax have the following formats:\n\n* **Source IP address and destination IP address**\n : Each is either a 32-bit field (for IPv4), or a set of 4 32-bit fields (for IPv6) represented by a value and a mask length.\n For example, an IPv4 range of 192.168.1.0 to 192.168.1.255 could be represented by a value = [192, 168, 1, 0] and a mask length = 24.\n\n* **Source port and destination port**\n : Each is a 16-bit field, represented by a lower start and a higher end.\n For example, a range of ports 0 to 8192 could be represented by lower = 0 and higher = 8192.\n\n* **Protocol identifier**\n : An 8-bit field, represented by a value and a mask, that covers a range of values.\n To verify that a value is in the range, use the following expression: \"(VAL & mask) == value\"\n\nThe trick in how to represent a range with a mask and value is as follows.\nA range can be enumerated in binary numbers with some bits that are never changed and some bits that are dynamically changed.\nSet those bits that dynamically changed in mask and value with 0.\nSet those bits that never changed in the mask with 1, in value with number expected.\nFor example, a range of 6 to 7 is enumerated as 0b110 and 0b111.\nBit 1-7 are bits never changed and bit 0 is the bit dynamically changed.\nTherefore, set bit 0 in mask and value with 0, set bits 1-7 in mask with 1, and bits 1-7 in value with number 0b11.\nSo, mask is 0xfe, value is 0x6.\n\n.. note::\n\n The library assumes that each field in the rule is in LSB or Little Endian order when creating the database.\n It internally converts them to MSB or Big Endian order.\n When performing a lookup, the library assumes the input is in MSB or Big Endian order.\n\nAccess Rule Syntax\n~~~~~~~~~~~~~~~~~~\n\nIn this sample application, each rule is a combination of the following:\n\n* 5-tuple field: This field has a format described in Section.\n\n* priority field: A weight to measure the priority of the rules.\n The rule with the higher priority will ALWAYS be returned if the specific input has multiple matches in the rule database.\n Rules with lower priority will NEVER be returned in any cases.\n\n* userdata field: A user-defined field that could be any value.\n It can be the forwarding port number if the rule is a route table entry or it can be a pointer to a mapping address\n if the rule is used for address mapping in the NAT application.\n The key point is that it is a useful reserved field for user convenience.\n\nACL and Route Rules\n~~~~~~~~~~~~~~~~~~~\n\nThe application needs to acquire ACL and route rules before it runs.\nRoute rules are mandatory, while ACL rules are optional.\nTo simplify the complexity of the priority field for each rule, all ACL and route entries are assumed to be in the same file.\nTo read data from the specified file successfully, the application assumes the following:\n\n* Each rule occupies a single line.\n\n* Only the following four rule line types are valid in this application:\n\n* ACL rule line, which starts with a leading character '@'\n\n* Route rule line, which starts with a leading character 'R'\n\n* Comment line, which starts with a leading character '#'\n\n* Empty line, which consists of a space, form-feed ('\\f'), newline ('\\n'),\n carriage return ('\\r'), horizontal tab ('\\t'), or vertical tab ('\\v').\n\nOther lines types are considered invalid.\n\n* Rules are organized in descending order of priority,\n which means rules at the head of the file always have a higher priority than those further down in the file.\n\n* A typical IPv4 ACL rule line should have a format as shown below:\n\n\n.. _figure_ipv4_acl_rule:\n\n.. figure:: img/ipv4_acl_rule.*\n\n A typical IPv4 ACL rule\n\n\nIPv4 addresses are specified in CIDR format as specified in RFC 4632.\nThey consist of the dot notation for the address and a prefix length separated by '/'.\nFor example, 192.168.0.34/32, where the address is 192.168.0.34 and the prefix length is 32.\n\nPorts are specified as a range of 16-bit numbers in the format MIN:MAX,\nwhere MIN and MAX are the inclusive minimum and maximum values of the range.\nThe range 0:65535 represents all possible ports in a range.\nWhen MIN and MAX are the same value, a single port is represented, for example, 20:20.\n\nThe protocol identifier is an 8-bit value and a mask separated by '/'.\nFor example: 6/0xfe matches protocol values 6 and 7.\n\n* Route rules start with a leading character 'R' and have the same format as ACL rules except an extra field at the tail\n that indicates the forwarding port number.\n\nRules File Example\n~~~~~~~~~~~~~~~~~~\n\n.. _figure_example_rules:\n\n.. figure:: img/example_rules.*\n\n Rules example\n\n\nEach rule is explained as follows:\n\n* Rule 1 (the first line) tells the application to drop those packets with source IP address = [1.2.3.*],\n destination IP address = [192.168.0.36], protocol = [6]/[7]\n\n* Rule 2 (the second line) is similar to Rule 1, except the source IP address is ignored.\n It tells the application to forward packets with destination IP address = [192.168.0.36],\n protocol = [6]/[7], destined to port 1.\n\n* Rule 3 (the third line) tells the application to forward all packets to port 0.\n This is something like a default route entry.\n\nAs described earlier, the application assume rules are listed in descending order of priority,\ntherefore Rule 1 has the highest priority, then Rule 2, and finally,\nRule 3 has the lowest priority.\n\nConsider the arrival of the following three packets:\n\n* Packet 1 has source IP address = [1.2.3.4], destination IP address = [192.168.0.36], and protocol = [6]\n\n* Packet 2 has source IP address = [1.2.4.4], destination IP address = [192.168.0.36], and protocol = [6]\n\n* Packet 3 has source IP address = [1.2.3.4], destination IP address = [192.168.0.36], and protocol = [8]\n\nObserve that:\n\n* Packet 1 matches all of the rules\n\n* Packet 2 matches Rule 2 and Rule 3\n\n* Packet 3 only matches Rule 3\n\nFor priority reasons, Packet 1 matches Rule 1 and is dropped.\nPacket 2 matches Rule 2 and is forwarded to port 1.\nPacket 3 matches Rule 3 and is forwarded to port 0.\n\nFor more details on the rule file format,\nplease refer to rule_ipv4.db and rule_ipv6.db files (inside /examples/l3fwd-acl/).\n\nApplication Phases\n~~~~~~~~~~~~~~~~~~\n\nOnce the application starts, it transitions through three phases:\n\n* **Initialization Phase**\n - Perform the following tasks:\n\n* Parse command parameters. Check the validity of rule file(s) name(s), number of logical cores, receive and transmit queues.\n Bind ports, queues and logical cores. Check ACL search options, and so on.\n\n* Call Environmental Abstraction Layer (EAL) and Poll Mode Driver (PMD) functions to initialize the environment and detect possible NICs.\n The EAL creates several threads and sets affinity to a specific hardware thread CPU based on the configuration specified\n by the command line arguments.\n\n* Read the rule files and format the rules into the representation that the ACL library can recognize.\n Call the ACL library function to add the rules into the database and compile them as a trie of pattern sets.\n Note that application maintains a separate AC contexts for IPv4 and IPv6 rules.\n\n* **Runtime Phase**\n - Process the incoming packets from a port. Packets are processed in three steps:\n\n * Retrieval: Gets a packet from the receive queue. Each logical core may process several queues for different ports.\n This depends on the configuration specified by command line arguments.\n\n * Lookup: Checks that the packet type is supported (IPv4/IPv6) and performs a 5-tuple lookup over corresponding AC context.\n If an ACL rule is matched, the packets will be dropped and return back to step 1.\n If a route rule is matched, it indicates the packet is not in the ACL list and should be forwarded.\n If there is no matches for the packet, then the packet is dropped.\n\n * Forwarding: Forwards the packet to the corresponding port.\n\n* **Final Phase** - Perform the following tasks:\n\n Calls the EAL, PMD driver and ACL library to free resource, then quits.\n\nCompiling the Application\n-------------------------\n\nTo compile the application:\n\n#. Go to the sample application directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/l3fwd-acl\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the *DPDK IPL Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nThe application has a number of command line options:\n\n.. code-block:: console\n\n ./build/l3fwd-acl [EAL options] -- -p PORTMASK [-P] --config(port,queue,lcore)[,(port,queue,lcore)] --rule_ipv4 FILENAME rule_ipv6 FILENAME [--scalar] [--enable-jumbo [--max-pkt-len PKTLEN]] [--no-numa]\n\n\nwhere,\n\n* -p PORTMASK: Hexadecimal bitmask of ports to configure\n\n* -P: Sets all ports to promiscuous mode so that packets are accepted regardless of the packet's Ethernet MAC destination address.\n Without this option, only packets with the Ethernet MAC destination address set to the Ethernet address of the port are accepted.\n\n* --config (port,queue,lcore)[,(port,queue,lcore)]: determines which queues from which ports are mapped to which cores\n\n* --rule_ipv4 FILENAME: Specifies the IPv4 ACL and route rules file\n\n* --rule_ipv6 FILENAME: Specifies the IPv6 ACL and route rules file\n\n* --scalar: Use a scalar function to perform rule lookup\n\n* --enable-jumbo: optional, enables jumbo frames\n\n* --max-pkt-len: optional, maximum packet length in decimal (64-9600)\n\n* --no-numa: optional, disables numa awareness\n\nAs an example, consider a dual processor socket platform where cores 0, 2, 4, 6, 8 and 10 appear on socket 0,\nwhile cores 1, 3, 5, 7, 9 and 11 appear on socket 1.\nLet's say that the user wants to use memory from both NUMA nodes,\nthe platform has only two ports and the user wants to use two cores from each processor socket to do the packet processing.\n\nTo enable L3 forwarding between two ports, using two cores from each processor,\nwhile also taking advantage of local memory access by optimizing around NUMA,\nthe user must enable two queues from each port,\npin to the appropriate cores and allocate memory from the appropriate NUMA node.\nThis is achieved using the following command:\n\n.. code-block:: console\n\n ./build/l3fwd-acl -c f -n 4 -- -p 0x3 --config=\"(0,0,0),(0,1,2),(1,0,1),(1,1,3)\" --rule_ipv4=\"./rule_ipv4.db\" -- rule_ipv6=\"./rule_ipv6.db\" --scalar\n\nIn this command:\n\n* The -c option enables cores 0, 1, 2, 3\n\n* The -p option enables ports 0 and 1\n\n* The --config option enables two queues on each port and maps each (port,queue) pair to a specific core.\n Logic to enable multiple RX queues using RSS and to allocate memory from the correct NUMA nodes is included in the application\n and is done transparently.\n The following table shows the mapping in this example:\n\n +----------+------------+-----------+------------------------------------------------+\n | **Port** | **Queue** | **lcore** | **Description** |\n | | | | |\n +==========+============+===========+================================================+\n | 0 | 0 | 0 | Map queue 0 from port 0 to lcore 0. |\n | | | | |\n +----------+------------+-----------+------------------------------------------------+\n | 0 | 1 | 2 | Map queue 1 from port 0 to lcore 2. |\n | | | | |\n +----------+------------+-----------+------------------------------------------------+\n | 1 | 0 | 1 | Map queue 0 from port 1 to lcore 1. |\n | | | | |\n +----------+------------+-----------+------------------------------------------------+\n | 1 | 1 | 3 | Map queue 1 from port 1 to lcore 3. |\n | | | | |\n +----------+------------+-----------+------------------------------------------------+\n\n* The --rule_ipv4 option specifies the reading of IPv4 rules sets from the ./ rule_ipv4.db file.\n\n* The --rule_ipv6 option specifies the reading of IPv6 rules sets from the ./ rule_ipv6.db file.\n\n* The --scalar option specifies the performing of rule lookup with a scalar function.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of the sample application code.\nThe aspects of port, device and CPU configuration are similar to those of the L3 forwarding application\n(see Chapter 10, \"L3 Forwarding Sample Application\" for more information).\nThe following sections describe aspects that are specific to L3 forwarding with access control.\n\nParse Rules from File\n~~~~~~~~~~~~~~~~~~~~~\n\nAs described earlier, both ACL and route rules are assumed to be saved in the same file.\nThe application parses the rules from the file and adds them to the database by calling the ACL library function.\nIt ignores empty and comment lines, and parses and validates the rules it reads.\nIf errors are detected, the application exits with messages to identify the errors encountered.\n\nThe application needs to consider the userdata and priority fields.\nThe ACL rules save the index to the specific rules in the userdata field,\nwhile route rules save the forwarding port number.\nIn order to differentiate the two types of rules, ACL rules add a signature in the userdata field.\nAs for the priority field, the application assumes rules are organized in descending order of priority.\nTherefore, the code only decreases the priority number with each rule it parses.\n\nSetting Up the ACL Context\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nFor each supported AC rule format (IPv4 5-tuple, IPv6 6-tuple) application creates a separate context handler\nfrom the ACL library for each CPU socket on the board and adds parsed rules into that context.\n\nNote, that for each supported rule type,\napplication needs to calculate the expected offset of the fields from the start of the packet.\nThat's why only packets with fixed IPv4/ IPv6 header are supported.\nThat allows to perform ACL classify straight over incoming packet buffer -\nno extra protocol field retrieval need to be performed.\n\nSubsequently, the application checks whether NUMA is enabled.\nIf it is, the application records the socket IDs of the CPU cores involved in the task.\n\nFinally, the application creates contexts handler from the ACL library,\nadds rules parsed from the file into the database and build an ACL trie.\nIt is important to note that the application creates an independent copy of each database for each socket CPU\ninvolved in the task to reduce the time for remote memory access.\n" }, { "path": "doc/guides/sample_app_ug/l3_forward_power_man.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nL3 Forwarding with Power Management Sample Application\n======================================================\n\nIntroduction\n------------\n\nThe L3 Forwarding with Power Management application is an example of power-aware packet processing using the DPDK.\nThe application is based on existing L3 Forwarding sample application,\nwith the power management algorithms to control the P-states and\nC-states of the Intel processor via a power management library.\n\nOverview\n--------\n\nThe application demonstrates the use of the Power libraries in the DPDK to implement packet forwarding.\nThe initialization and run-time paths are very similar to those of the L3 forwarding sample application\n(see Chapter 10 \"L3 Forwarding Sample Application\" for more information).\nThe main difference from the L3 Forwarding sample application is that this application introduces power-aware optimization algorithms\nby leveraging the Power library to control P-state and C-state of processor based on packet load.\n\nThe DPDK includes poll-mode drivers to configure Intel NIC devices and their receive (Rx) and transmit (Tx) queues.\nThe design principle of this PMD is to access the Rx and Tx descriptors directly without any interrupts to quickly receive,\nprocess and deliver packets in the user space.\n\nIn general, the DPDK executes an endless packet processing loop on dedicated IA cores that include the following steps:\n\n* Retrieve input packets through the PMD to poll Rx queue\n\n* Process each received packet or provide received packets to other processing cores through software queues\n\n* Send pending output packets to Tx queue through the PMD\n\nIn this way, the PMD achieves better performance than a traditional interrupt-mode driver,\nat the cost of keeping cores active and running at the highest frequency,\nhence consuming the maximum power all the time.\nHowever, during the period of processing light network traffic,\nwhich happens regularly in communication infrastructure systems due to well-known \"tidal effect\",\nthe PMD is still busy waiting for network packets, which wastes a lot of power.\n\nProcessor performance states (P-states) are the capability of an Intel processor\nto switch between different supported operating frequencies and voltages.\nIf configured correctly, according to system workload, this feature provides power savings.\nCPUFreq is the infrastructure provided by the Linux* kernel to control the processor performance state capability.\nCPUFreq supports a user space governor that enables setting frequency via manipulating the virtual file device from a user space application.\nThe Power library in the DPDK provides a set of APIs for manipulating a virtual file device to allow user space application\nto set the CPUFreq governor and set the frequency of specific cores.\n\nThis application includes a P-state power management algorithm to generate a frequency hint to be sent to CPUFreq.\nThe algorithm uses the number of received and available Rx packets on recent polls to make a heuristic decision to scale frequency up/down.\nSpecifically, some thresholds are checked to see whether a specific core running an DPDK polling thread needs to increase frequency\na step up based on the near to full trend of polled Rx queues.\nAlso, it decreases frequency a step if packet processed per loop is far less than the expected threshold\nor the thread's sleeping time exceeds a threshold.\n\nC-States are also known as sleep states.\nThey allow software to put an Intel core into a low power idle state from which it is possible to exit via an event, such as an interrupt.\nHowever, there is a tradeoff between the power consumed in the idle state and the time required to wake up from the idle state (exit latency).\nTherefore, as you go into deeper C-states, the power consumed is lower but the exit latency is increased. Each C-state has a target residency.\nIt is essential that when entering into a C-state, the core remains in this C-state for at least as long as the target residency in order\nto fully realize the benefits of entering the C-state.\nCPUIdle is the infrastructure provide by the Linux kernel to control the processor C-state capability.\nUnlike CPUFreq, CPUIdle does not provide a mechanism that allows the application to change C-state.\nIt actually has its own heuristic algorithms in kernel space to select target C-state to enter by executing privileged instructions like HLT and MWAIT,\nbased on the speculative sleep duration of the core.\nIn this application, we introduce a heuristic algorithm that allows packet processing cores to sleep for a short period\nif there is no Rx packet received on recent polls.\nIn this way, CPUIdle automatically forces the corresponding cores to enter deeper C-states\ninstead of always running to the C0 state waiting for packets.\n\n.. note::\n\n To fully demonstrate the power saving capability of using C-states,\n it is recommended to enable deeper C3 and C6 states in the BIOS during system boot up.\n\nCompiling the Application\n-------------------------\n\nTo compile the application:\n\n#. Go to the sample application directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk cd ${RTE_SDK}/examples/l3fwd-power\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nThe application has a number of command line options:\n\n.. code-block:: console\n\n ./build/l3fwd_power [EAL options] -- -p PORTMASK [-P] --config(port,queue,lcore)[,(port,queue,lcore)] [--enable-jumbo [--max-pkt-len PKTLEN]] [--no-numa]\n\nwhere,\n\n* -p PORTMASK: Hexadecimal bitmask of ports to configure\n\n* -P: Sets all ports to promiscuous mode so that packets are accepted regardless of the packet's Ethernet MAC destination address.\n Without this option, only packets with the Ethernet MAC destination address set to the Ethernet address of the port are accepted.\n\n* --config (port,queue,lcore)[,(port,queue,lcore)]: determines which queues from which ports are mapped to which cores.\n\n* --enable-jumbo: optional, enables jumbo frames\n\n* --max-pkt-len: optional, maximum packet length in decimal (64-9600)\n\n* --no-numa: optional, disables numa awareness\n\nSee Chapter 10 \"L3 Forwarding Sample Application\" for details.\nThe L3fwd-power example reuses the L3fwd command line options.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of the sample application code.\nAs mentioned in the overview section,\nthe initialization and run-time paths are identical to those of the L3 forwarding application.\nThe following sections describe aspects that are specific to the L3 Forwarding with Power Management sample application.\n\nPower Library Initialization\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe Power library is initialized in the main routine.\nIt changes the P-state governor to userspace for specific cores that are under control.\nThe Timer library is also initialized and several timers are created later on,\nresponsible for checking if it needs to scale down frequency at run time by checking CPU utilization statistics.\n\n.. note::\n\n Only the power management related initialization is shown.\n\n.. code-block:: c\n\n int main(int argc, char **argv)\n {\n struct lcore_conf *qconf;\n int ret;\n unsigned nb_ports;\n uint16_t queueid;\n unsigned lcore_id;\n uint64_t hz;\n uint32_t n_tx_queue, nb_lcores;\n uint8_t portid, nb_rx_queue, queue, socketid;\n\n // ...\n\n /* init RTE timer library to be used to initialize per-core timers */\n\n rte_timer_subsystem_init();\n\n // ...\n\n\n /* per-core initialization */\n\n for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n if (rte_lcore_is_enabled(lcore_id) == 0)\n continue;\n\n /* init power management library for a specified core */\n\n ret = rte_power_init(lcore_id);\n if (ret)\n rte_exit(EXIT_FAILURE, \"Power management library \"\n \"initialization failed on core%d\\n\", lcore_id);\n\n /* init timer structures for each enabled lcore */\n\n rte_timer_init(&power_timers[lcore_id]);\n\n hz = rte_get_hpet_hz();\n\n rte_timer_reset(&power_timers[lcore_id], hz/TIMER_NUMBER_PER_SECOND, SINGLE, lcore_id, power_timer_cb, NULL);\n\n // ...\n }\n\n // ...\n }\n\nMonitoring Loads of Rx Queues\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nIn general, the polling nature of the DPDK prevents the OS power management subsystem from knowing\nif the network load is actually heavy or light.\nIn this sample, sampling network load work is done by monitoring received and\navailable descriptors on NIC Rx queues in recent polls.\nBased on the number of returned and available Rx descriptors,\nthis example implements algorithms to generate frequency scaling hints and speculative sleep duration,\nand use them to control P-state and C-state of processors via the power management library.\nFrequency (P-state) control and sleep state (C-state) control work individually for each logical core,\nand the combination of them contributes to a power efficient packet processing solution when serving light network loads.\n\nThe rte_eth_rx_burst() function and the newly-added rte_eth_rx_queue_count() function are used in the endless packet processing loop\nto return the number of received and available Rx descriptors.\nAnd those numbers of specific queue are passed to P-state and C-state heuristic algorithms\nto generate hints based on recent network load trends.\n\n.. note::\n\n Only power control related code is shown.\n\n.. code-block:: c\n\n static\n attribute ((noreturn)) int main_loop( attribute ((unused)) void *dummy)\n {\n // ...\n\n while (1) {\n // ...\n\n /**\n * Read packet from RX queues\n */\n\n lcore_scaleup_hint = FREQ_CURRENT;\n lcore_rx_idle_count = 0;\n\n for (i = 0; i < qconf->n_rx_queue; ++i)\n {\n rx_queue = &(qconf->rx_queue_list[i]);\n rx_queue->idle_hint = 0;\n portid = rx_queue->port_id;\n queueid = rx_queue->queue_id;\n\n nb_rx = rte_eth_rx_burst(portid, queueid, pkts_burst, MAX_PKT_BURST);\n stats[lcore_id].nb_rx_processed += nb_rx;\n\n if (unlikely(nb_rx == 0)) {\n /**\n * no packet received from rx queue, try to\n * sleep for a while forcing CPU enter deeper\n * C states.\n */\n\n rx_queue->zero_rx_packet_count++;\n\n if (rx_queue->zero_rx_packet_count <= MIN_ZERO_POLL_COUNT)\n continue;\n\n rx_queue->idle_hint = power_idle_heuristic(rx_queue->zero_rx_packet_count);\n lcore_rx_idle_count++;\n } else {\n rx_ring_length = rte_eth_rx_queue_count(portid, queueid);\n\n rx_queue->zero_rx_packet_count = 0;\n\n /**\n * do not scale up frequency immediately as\n * user to kernel space communication is costly\n * which might impact packet I/O for received\n * packets.\n */\n\n rx_queue->freq_up_hint = power_freq_scaleup_heuristic(lcore_id, rx_ring_length);\n }\n\n /* Prefetch and forward packets */\n\n // ...\n }\n\n if (likely(lcore_rx_idle_count != qconf->n_rx_queue)) {\n for (i = 1, lcore_scaleup_hint = qconf->rx_queue_list[0].freq_up_hint; i < qconf->n_rx_queue; ++i) {\n x_queue = &(qconf->rx_queue_list[i]);\n\n if (rx_queue->freq_up_hint > lcore_scaleup_hint)\n\n lcore_scaleup_hint = rx_queue->freq_up_hint;\n }\n\n if (lcore_scaleup_hint == FREQ_HIGHEST)\n\n rte_power_freq_max(lcore_id);\n\n else if (lcore_scaleup_hint == FREQ_HIGHER)\n rte_power_freq_up(lcore_id);\n } else {\n /**\n * All Rx queues empty in recent consecutive polls,\n * sleep in a conservative manner, meaning sleep as\n * less as possible.\n */\n\n for (i = 1, lcore_idle_hint = qconf->rx_queue_list[0].idle_hint; i < qconf->n_rx_queue; ++i) {\n rx_queue = &(qconf->rx_queue_list[i]);\n if (rx_queue->idle_hint < lcore_idle_hint)\n lcore_idle_hint = rx_queue->idle_hint;\n }\n\n if ( lcore_idle_hint < SLEEP_GEAR1_THRESHOLD)\n /**\n * execute \"pause\" instruction to avoid context\n * switch for short sleep.\n */\n rte_delay_us(lcore_idle_hint);\n else\n /* long sleep force ruining thread to suspend */\n usleep(lcore_idle_hint);\n\n stats[lcore_id].sleep_time += lcore_idle_hint;\n }\n }\n }\n\nP-State Heuristic Algorithm\n~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe power_freq_scaleup_heuristic() function is responsible for generating a frequency hint for the specified logical core\naccording to available descriptor number returned from rte_eth_rx_queue_count().\nOn every poll for new packets, the length of available descriptor on an Rx queue is evaluated,\nand the algorithm used for frequency hinting is as follows:\n\n* If the size of available descriptors exceeds 96, the maximum frequency is hinted.\n\n* If the size of available descriptors exceeds 64, a trend counter is incremented by 100.\n\n* If the length of the ring exceeds 32, the trend counter is incremented by 1.\n\n* When the trend counter reached 10000 the frequency hint is changed to the next higher frequency.\n\n.. note::\n\n The assumption is that the Rx queue size is 128 and the thresholds specified above\n must be adjusted accordingly based on actual hardware Rx queue size,\n which are configured via the rte_eth_rx_queue_setup() function.\n\nIn general, a thread needs to poll packets from multiple Rx queues.\nMost likely, different queue have different load, so they would return different frequency hints.\nThe algorithm evaluates all the hints and then scales up frequency in an aggressive manner\nby scaling up to highest frequency as long as one Rx queue requires.\nIn this way, we can minimize any negative performance impact.\n\nOn the other hand, frequency scaling down is controlled in the timer callback function.\nSpecifically, if the sleep times of a logical core indicate that it is sleeping more than 25% of the sampling period,\nor if the average packet per iteration is less than expectation, the frequency is decreased by one step.\n\nC-State Heuristic Algorithm\n~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nWhenever recent rte_eth_rx_burst() polls return 5 consecutive zero packets,\nan idle counter begins incrementing for each successive zero poll.\nAt the same time, the function power_idle_heuristic() is called to generate speculative sleep duration\nin order to force logical to enter deeper sleeping C-state.\nThere is no way to control C- state directly, and the CPUIdle subsystem in OS is intelligent enough\nto select C-state to enter based on actual sleep period time of giving logical core.\nThe algorithm has the following sleeping behavior depending on the idle counter:\n\n* If idle count less than 100, the counter value is used as a microsecond sleep value through rte_delay_us()\n which execute pause instructions to avoid costly context switch but saving power at the same time.\n\n* If idle count is between 100 and 999, a fixed sleep interval of 100 μs is used.\n A 100 μs sleep interval allows the core to enter the C1 state while keeping a fast response time in case new traffic arrives.\n\n* If idle count is greater than 1000, a fixed sleep value of 1 ms is used until the next timer expiration is used.\n This allows the core to enter the C3/C6 states.\n\n.. note::\n\n The thresholds specified above need to be adjusted for different Intel processors and traffic profiles.\n\nIf a thread polls multiple Rx queues and different queue returns different sleep duration values,\nthe algorithm controls the sleep time in a conservative manner by sleeping for the least possible time\nin order to avoid a potential performance impact.\n" }, { "path": "doc/guides/sample_app_ug/l3_forward_virtual.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nL3 Forwarding in a Virtualization Environment Sample Application\n================================================================\n\nThe L3 Forwarding in a Virtualization Environment sample application is a simple example of packet processing using the DPDK.\nThe application performs L3 forwarding that takes advantage of Single Root I/O Virtualization (SR-IOV) features\nin a virtualized environment.\n\nOverview\n--------\n\nThe application demonstrates the use of the hash and LPM libraries in the DPDK to implement packet forwarding.\nThe initialization and run-time paths are very similar to those of the L3 forwarding application\n(see Chapter 10 \"L3 Forwarding Sample Application\" for more information).\nThe forwarding decision is taken based on information read from the input packet.\n\nThe lookup method is either hash-based or LPM-based and is selected at compile time.\nWhen the selected lookup method is hash-based, a hash object is used to emulate the flow classification stage.\nThe hash object is used in correlation with the flow table to map each input packet to its flow at runtime.\n\nThe hash lookup key is represented by the DiffServ 5-tuple composed of the following fields read from the input packet:\nSource IP Address, Destination IP Address, Protocol, Source Port and Destination Port.\nThe ID of the output interface for the input packet is read from the identified flow table entry.\nThe set of flows used by the application is statically configured and loaded into the hash at initialization time.\nWhen the selected lookup method is LPM based, an LPM object is used to emulate the forwarding stage for IPv4 packets.\nThe LPM object is used as the routing table to identify the next hop for each input packet at runtime.\n\nThe LPM lookup key is represented by the Destination IP Address field read from the input packet.\nThe ID of the output interface for the input packet is the next hop returned by the LPM lookup.\nThe set of LPM rules used by the application is statically configured and loaded into the LPM object at the initialization time.\n\n.. note::\n\n Please refer to Section 9.1.1 \"Virtual Function Setup Instructions\" for virtualized test case setup.\n\nCompiling the Application\n-------------------------\n\nTo compile the application:\n\n#. Go to the sample application directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/l3fwd-vf\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\n.. note::\n\n The compiled application is written to the build subdirectory.\n To have the application written to a different location,\n the O=/path/to/build/directory option may be specified in the make command.\n\nRunning the Application\n-----------------------\n\nThe application has a number of command line options:\n\n.. code-block:: console\n\n ./build/l3fwd-vf [EAL options] -- -p PORTMASK --config(port,queue,lcore)[,(port,queue,lcore)] [--no-numa]\n\nwhere,\n\n* --p PORTMASK: Hexadecimal bitmask of ports to configure\n\n* --config (port,queue,lcore)[,(port,queue,lcore]: determines which queues from which ports are mapped to which cores\n\n* --no-numa: optional, disables numa awareness\n\nFor example, consider a dual processor socket platform where cores 0,2,4,6, 8, and 10 appear on socket 0,\nwhile cores 1,3,5,7,9, and 11 appear on socket 1.\nLet's say that the programmer wants to use memory from both NUMA nodes,\nthe platform has only two ports and the programmer wants to use one core from each processor socket to do the packet processing\nsince only one Rx/Tx queue pair can be used in virtualization mode.\n\nTo enable L3 forwarding between two ports, using one core from each processor,\nwhile also taking advantage of local memory accesses by optimizing around NUMA,\nthe programmer can pin to the appropriate cores and allocate memory from the appropriate NUMA node.\nThis is achieved using the following command:\n\n.. code-block:: console\n\n ./build/l3fwd-vf -c 0x03 -n 3 -- -p 0x3 --config=\"(0,0,0),(1,0,1)\"\n\nIn this command:\n\n* The -c option enables cores 0 and 1\n\n* The -p option enables ports 0 and 1\n\n* The --config option enables one queue on each port and maps each (port,queue) pair to a specific core.\n Logic to enable multiple RX queues using RSS and to allocate memory from the correct NUMA nodes\n is included in the application and is done transparently.\n The following table shows the mapping in this example:\n\n +----------+-----------+-----------+------------------------------------+\n | **Port** | **Queue** | **lcore** | **Description** |\n | | | | |\n +==========+===========+===========+====================================+\n | 0 | 0 | 0 | Map queue 0 from port 0 to lcore 0 |\n | | | | |\n +----------+-----------+-----------+------------------------------------+\n | 1 | 1 | 1 | Map queue 0 from port 1 to lcore 1 |\n | | | | |\n +----------+-----------+-----------+------------------------------------+\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications\nand the Environment Abstraction Layer (EAL) options.\n\nExplanation\n-----------\n\nThe operation of this application is similar to that of the basic L3 Forwarding Sample Application.\nSee Section 10.4 \"Explanation\" for more information.\n" }, { "path": "doc/guides/sample_app_ug/link_status_intr.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nLink Status Interrupt Sample Application\n========================================\n\nThe Link Status Interrupt sample application is a simple example of packet processing using\nthe Data Plane Development Kit (DPDK) that\ndemonstrates how network link status changes for a network port can be captured and\nused by a DPDK application.\n\nOverview\n--------\n\nThe Link Status Interrupt sample application registers a user space callback for the link status interrupt of each port\nand performs L2 forwarding for each packet that is received on an RX_PORT.\nThe following operations are performed:\n\n* RX_PORT and TX_PORT are paired with available ports one-by-one according to the core mask\n\n* The source MAC address is replaced by the TX_PORT MAC address\n\n* The destination MAC address is replaced by 02:00:00:00:00:TX_PORT_ID\n\nThis application can be used to demonstrate the usage of link status interrupt and its user space callbacks\nand the behavior of L2 forwarding each time the link status changes.\n\nCompiling the Application\n-------------------------\n\n#. Go to the example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/link_status_interrupt\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\n.. note::\n\n The compiled application is written to the build subdirectory.\n To have the application written to a different location,\n the O=/path/to/build/directory option may be specified on the make command line.\n\nRunning the Application\n-----------------------\n\nThe application requires a number of command line options:\n\n.. code-block:: console\n\n ./build/link_status_interrupt [EAL options] -- -p PORTMASK [-q NQ][-T PERIOD]\n\nwhere,\n\n* -p PORTMASK: A hexadecimal bitmask of the ports to configure\n\n* -q NQ: A number of queues (=ports) per lcore (default is 1)\n\n* -T PERIOD: statistics will be refreshed each PERIOD seconds (0 to disable, 10 default)\n\nTo run the application in a linuxapp environment with 4 lcores, 4 memory channels, 16 ports and 8 RX queues per lcore,\nissue the command:\n\n.. code-block:: console\n\n $ ./build/link_status_interrupt -c f -n 4-- -q 8 -p ffff\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications\nand the Environment Abstraction Layer (EAL) options.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of the code.\n\nCommand Line Arguments\n~~~~~~~~~~~~~~~~~~~~~~\n\nThe Link Status Interrupt sample application takes specific parameters,\nin addition to Environment Abstraction Layer (EAL) arguments (see Section 13.3).\n\nCommand line parsing is done in the same way as it is done in the L2 Forwarding Sample Application.\nSee Section 9.4.1, \"Command Line Arguments\" for more information.\n\nMbuf Pool Initialization\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nMbuf pool initialization is done in the same way as it is done in the L2 Forwarding Sample Application.\nSee Section 9.4.2, \"Mbuf Pool Initialization\" for more information.\n\nDriver Initialization\n~~~~~~~~~~~~~~~~~~~~~\n\nThe main part of the code in the main() function relates to the initialization of the driver.\nTo fully understand this code, it is recommended to study the chapters that related to the Poll Mode Driver in the\n*DPDK Programmer's Guide and the DPDK API Reference*.\n\n.. code-block:: c\n\n if (rte_eal_pci_probe() < 0)\n rte_exit(EXIT_FAILURE, \"Cannot probe PCI\\n\");\n\n nb_ports = rte_eth_dev_count();\n if (nb_ports == 0)\n rte_exit(EXIT_FAILURE, \"No Ethernet ports - bye\\n\");\n\n if (nb_ports > RTE_MAX_ETHPORTS)\n nb_ports = RTE_MAX_ETHPORTS;\n\n /*\n * Each logical core is assigned a dedicated TX queue on each port.\n */\n\n for (portid = 0; portid < nb_ports; portid++) {\n /* skip ports that are not enabled */\n\n if ((lsi_enabled_port_mask & (1 << portid)) == 0)\n continue;\n\n /* save the destination port id */\n\n if (nb_ports_in_mask % 2) {\n lsi_dst_ports[portid] = portid_last;\n lsi_dst_ports[portid_last] = portid;\n }\n else\n portid_last = portid;\n\n nb_ports_in_mask++;\n\n rte_eth_dev_info_get((uint8_t) portid, &dev_info);\n }\n\nObserve that:\n\n* rte_eal_pci_probe() parses the devices on the PCI bus and initializes recognized devices.\n\nThe next step is to configure the RX and TX queues.\nFor each port, there is only one RX queue (only one lcore is able to poll a given port).\nThe number of TX queues depends on the number of available lcores.\nThe rte_eth_dev_configure() function is used to configure the number of queues for a port:\n\n.. code-block:: c\n\n ret = rte_eth_dev_configure((uint8_t) portid, 1, 1, &port_conf);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Cannot configure device: err=%d, port=%u\\n\", ret, portid);\n\nThe global configuration is stored in a static structure:\n\n.. code-block:: c\n\n static const struct rte_eth_conf port_conf = {\n .rxmode = {\n .split_hdr_size = 0,\n .header_split = 0, /**< Header Split disabled */\n .hw_ip_checksum = 0, /**< IP checksum offload disabled */\n .hw_vlan_filter = 0, /**< VLAN filtering disabled */\n .hw_strip_crc= 0, /**< CRC stripped by hardware */\n },\n .txmode = {},\n .intr_conf = {\n .lsc = 1, /**< link status interrupt feature enabled */\n },\n };\n\nConfiguring lsc to 0 (the default) disables the generation of any link status change interrupts in kernel space\nand no user space interrupt event is received.\nThe public interface rte_eth_link_get() accesses the NIC registers directly to update the link status.\nConfiguring lsc to non-zero enables the generation of link status change interrupts in kernel space\nwhen a link status change is present and calls the user space callbacks registered by the application.\nThe public interface rte_eth_link_get() just reads the link status in a global structure\nthat would be updated in the interrupt host thread only.\n\nInterrupt Callback Registration\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe application can register one or more callbacks to a specific port and interrupt event.\nAn example callback function that has been written as indicated below.\n\n.. code-block:: c\n\n static void\n lsi_event_callback(uint8_t port_id, enum rte_eth_event_type type, void *param)\n {\n struct rte_eth_link link;\n\n RTE_SET_USED(param);\n\n printf(\"\\n\\nIn registered callback...\\n\");\n\n printf(\"Event type: %s\\n\", type == RTE_ETH_EVENT_INTR_LSC ? \"LSC interrupt\" : \"unknown event\");\n\n rte_eth_link_get_nowait(port_id, &link);\n\n if (link.link_status) {\n printf(\"Port %d Link Up - speed %u Mbps - %s\\n\\n\", port_id, (unsigned)link.link_speed,\n (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? (\"full-duplex\") : (\"half-duplex\"));\n } else\n printf(\"Port %d Link Down\\n\\n\", port_id);\n }\n\nThis function is called when a link status interrupt is present for the right port.\nThe port_id indicates which port the interrupt applies to.\nThe type parameter identifies the interrupt event type,\nwhich currently can be RTE_ETH_EVENT_INTR_LSC only, but other types can be added in the future.\nThe param parameter is the address of the parameter for the callback.\nThis function should be implemented with care since it will be called in the interrupt host thread,\nwhich is different from the main thread of its caller.\n\nThe application registers the lsi_event_callback and a NULL parameter to the link status interrupt event on each port:\n\n.. code-block:: c\n\n rte_eth_dev_callback_register((uint8_t)portid, RTE_ETH_EVENT_INTR_LSC, lsi_event_callback, NULL);\n\nThis registration can be done only after calling the rte_eth_dev_configure() function and before calling any other function.\nIf lsc is initialized with 0, the callback is never called since no interrupt event would ever be present.\n\nRX Queue Initialization\n~~~~~~~~~~~~~~~~~~~~~~~\n\nThe application uses one lcore to poll one or several ports, depending on the -q option,\nwhich specifies the number of queues per lcore.\n\nFor example, if the user specifies -q 4, the application is able to poll four ports with one lcore.\nIf there are 16 ports on the target (and if the portmask argument is -p ffff),\nthe application will need four lcores to poll all the ports.\n\n.. code-block:: c\n\n ret = rte_eth_rx_queue_setup((uint8_t) portid, 0, nb_rxd, SOCKET0, &rx_conf, lsi_pktmbuf_pool);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup: err=%d, port=%u\\n\", ret, portid);\n\nThe list of queues that must be polled for a given lcore is stored in a private structure called struct lcore_queue_conf.\n\n.. code-block:: c\n\n struct lcore_queue_conf {\n unsigned n_rx_port;\n unsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE]; unsigned tx_queue_id;\n struct mbuf_table tx_mbufs[LSI_MAX_PORTS];\n } rte_cache_aligned;\n\n struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];\n\nThe n_rx_port and rx_port_list[] fields are used in the main packet processing loop\n(see Section 13.4.7, \"Receive, Process and Transmit Packets\" later in this chapter).\n\nThe global configuration for the RX queues is stored in a static structure:\n\n.. code-block:: c\n\n static const struct rte_eth_rxconf rx_conf = {\n .rx_thresh = {\n .pthresh = RX_PTHRESH,\n .hthresh = RX_HTHRESH,\n .wthresh = RX_WTHRESH,\n },\n };\n\nTX Queue Initialization\n~~~~~~~~~~~~~~~~~~~~~~~\n\nEach lcore should be able to transmit on any port.\nFor every port, a single TX queue is initialized.\n\n.. code-block:: c\n\n /* init one TX queue logical core on each port */\n\n fflush(stdout);\n\n ret = rte_eth_tx_queue_setup(portid, 0, nb_txd, rte_eth_dev_socket_id(portid), &tx_conf);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup: err=%d,port=%u\\n\", ret, (unsigned) portid);\n\nThe global configuration for TX queues is stored in a static structure:\n\n.. code-block:: c\n\n static const struct rte_eth_txconf tx_conf = {\n .tx_thresh = {\n .pthresh = TX_PTHRESH,\n .hthresh = TX_HTHRESH,\n .wthresh = TX_WTHRESH,\n },\n .tx_free_thresh = RTE_TEST_TX_DESC_DEFAULT + 1, /* disable feature */\n };\n\nReceive, Process and Transmit Packets\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nIn the lsi_main_loop() function, the main task is to read ingress packets from the RX queues.\nThis is done using the following code:\n\n.. code-block:: c\n\n /*\n * Read packet from RX queues\n */\n\n for (i = 0; i < qconf->n_rx_port; i++) {\n portid = qconf->rx_port_list[i];\n nb_rx = rte_eth_rx_burst((uint8_t) portid, 0, pkts_burst, MAX_PKT_BURST);\n port_statistics[portid].rx += nb_rx;\n\n for (j = 0; j < nb_rx; j++) {\n m = pkts_burst[j];\n rte_prefetch0(rte_pktmbuf_mtod(m, void *));\n lsi_simple_forward(m, portid);\n }\n }\n\nPackets are read in a burst of size MAX_PKT_BURST.\nThe rte_eth_rx_burst() function writes the mbuf pointers in a local table and returns the number of available mbufs in the table.\n\nThen, each mbuf in the table is processed by the lsi_simple_forward() function.\nThe processing is very simple: processes the TX port from the RX port and then replaces the source and destination MAC addresses.\n\n.. note::\n\n In the following code, the two lines for calculating the output port require some explanation.\n If portId is even, the first line does nothing (as portid & 1 will be 0), and the second line adds 1.\n If portId is odd, the first line subtracts one and the second line does nothing.\n Therefore, 0 goes to 1, and 1 to 0, 2 goes to 3 and 3 to 2, and so on.\n\n.. code-block:: c\n\n static void\n lsi_simple_forward(struct rte_mbuf *m, unsigned portid)\n {\n struct ether_hdr *eth;\n void *tmp;\n unsigned dst_port = lsi_dst_ports[portid];\n\n eth = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n /* 02:00:00:00:00:xx */\n\n tmp = ð->d_addr.addr_bytes[0];\n\n *((uint64_t *)tmp) = 0x000000000002 + (dst_port << 40);\n\n /* src addr */\n ether_addr_copy(&lsi_ports_eth_addr[dst_port], ð->s_addr);\n\n lsi_send_packet(m, dst_port);\n }\n\nThen, the packet is sent using the lsi_send_packet(m, dst_port) function.\nFor this test application, the processing is exactly the same for all packets arriving on the same RX port.\nTherefore, it would have been possible to call the lsi_send_burst() function directly from the main loop\nto send all the received packets on the same TX port using\nthe burst-oriented send function, which is more efficient.\n\nHowever, in real-life applications (such as, L3 routing),\npacket N is not necessarily forwarded on the same port as packet N-1.\nThe application is implemented to illustrate that so the same approach can be reused in a more complex application.\n\nThe lsi_send_packet() function stores the packet in a per-lcore and per-txport table.\nIf the table is full, the whole packets table is transmitted using the lsi_send_burst() function:\n\n.. code-block:: c\n\n /* Send the packet on an output interface */\n\n static int\n lsi_send_packet(struct rte_mbuf *m, uint8_t port)\n {\n unsigned lcore_id, len;\n struct lcore_queue_conf *qconf;\n\n lcore_id = rte_lcore_id();\n qconf = &lcore_queue_conf[lcore_id];\n len = qconf->tx_mbufs[port].len;\n qconf->tx_mbufs[port].m_table[len] = m;\n len++;\n\n /* enough pkts to be sent */\n\n if (unlikely(len == MAX_PKT_BURST)) {\n lsi_send_burst(qconf, MAX_PKT_BURST, port);\n len = 0;\n }\n qconf->tx_mbufs[port].len = len;\n\n return 0;\n }\n\nTo ensure that no packets remain in the tables, each lcore does a draining of the TX queue in its main loop.\nThis technique introduces some latency when there are not many packets to send.\nHowever, it improves performance:\n\n.. code-block:: c\n\n cur_tsc = rte_rdtsc();\n\n /*\n * TX burst queue drain\n */\n\n diff_tsc = cur_tsc - prev_tsc;\n\n if (unlikely(diff_tsc > drain_tsc)) {\n /* this could be optimized (use queueid instead of * portid), but it is not called so often */\n\n for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n if (qconf->tx_mbufs[portid].len == 0)\n continue;\n\n lsi_send_burst(&lcore_queue_conf[lcore_id],\n qconf->tx_mbufs[portid].len, (uint8_t) portid);\n qconf->tx_mbufs[portid].len = 0;\n }\n\n /* if timer is enabled */\n\n if (timer_period > 0) {\n /* advance the timer */\n\n timer_tsc += diff_tsc;\n\n /* if timer has reached its timeout */\n\n if (unlikely(timer_tsc >= (uint64_t) timer_period)) {\n /* do this only on master core */\n\n if (lcore_id == rte_get_master_lcore()) {\n print_stats();\n\n /* reset the timer */\n timer_tsc = 0;\n }\n }\n }\n prev_tsc = cur_tsc;\n }\n" }, { "path": "doc/guides/sample_app_ug/load_balancer.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nLoad Balancer Sample Application\n================================\n\nThe Load Balancer sample application demonstrates the concept of isolating the packet I/O task\nfrom the application-specific workload.\nDepending on the performance target,\na number of logical cores (lcores) are dedicated to handle the interaction with the NIC ports (I/O lcores),\nwhile the rest of the lcores are dedicated to performing the application processing (worker lcores).\nThe worker lcores are totally oblivious to the intricacies of the packet I/O activity and\nuse the NIC-agnostic interface provided by software rings to exchange packets with the I/O cores.\n\nOverview\n--------\n\nThe architecture of the Load Balance application is presented in the following figure.\n\n.. _figure_load_bal_app_arch:\n\n.. figure:: img/load_bal_app_arch.*\n\n Load Balancer Application Architecture\n\n\nFor the sake of simplicity, the diagram illustrates a specific case of two I/O RX and two I/O TX lcores off loading the packet I/O\noverhead incurred by four NIC ports from four worker cores, with each I/O lcore handling RX/TX for two NIC ports.\n\nI/O RX Logical Cores\n~~~~~~~~~~~~~~~~~~~~\n\nEach I/O RX lcore performs packet RX from its assigned NIC RX rings and then distributes the received packets to the worker threads.\nThe application allows each I/O RX lcore to communicate with any of the worker threads,\ntherefore each (I/O RX lcore, worker lcore) pair is connected through a dedicated single producer - single consumer software ring.\n\nThe worker lcore to handle the current packet is determined by reading a predefined 1-byte field from the input packet:\n\nworker_id = packet[load_balancing_field] % n_workers\n\nSince all the packets that are part of the same traffic flow are expected to have the same value for the load balancing field,\nthis scheme also ensures that all the packets that are part of the same traffic flow are directed to the same worker lcore (flow affinity)\nin the same order they enter the system (packet ordering).\n\nI/O TX Logical Cores\n~~~~~~~~~~~~~~~~~~~~\n\nEach I/O lcore owns the packet TX for a predefined set of NIC ports. To enable each worker thread to send packets to any NIC TX port,\nthe application creates a software ring for each (worker lcore, NIC TX port) pair,\nwith each I/O TX core handling those software rings that are associated with NIC ports that it handles.\n\nWorker Logical Cores\n~~~~~~~~~~~~~~~~~~~~\n\nEach worker lcore reads packets from its set of input software rings and\nroutes them to the NIC ports for transmission by dispatching them to output software rings.\nThe routing logic is LPM based, with all the worker threads sharing the same LPM rules.\n\nCompiling the Application\n-------------------------\n\nThe sequence of steps used to build the application is:\n\n#. Export the required environment variables:\n\n .. code-block:: console\n\n export RTE_SDK=\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n#. Build the application executable file:\n\n .. code-block:: console\n\n cd ${RTE_SDK}/examples/load_balancer make\n\n For more details on how to build the DPDK libraries and sample applications,\n please refer to the *DPDK Getting Started Guide.*\n\nRunning the Application\n-----------------------\n\nTo successfully run the application,\nthe command line used to start the application has to be in sync with the traffic flows configured on the traffic generator side.\n\nFor examples of application command lines and traffic generator flows, please refer to the DPDK Test Report.\nFor more details on how to set up and run the sample applications provided with DPDK package,\nplease refer to the *DPDK Getting Started Guide*.\n\nExplanation\n-----------\n\nApplication Configuration\n~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe application run-time configuration is done through the application command line parameters.\nAny parameter that is not specified as mandatory is optional,\nwith the default value hard-coded in the main.h header file from the application folder.\n\nThe list of application command line parameters is listed below:\n\n#. --rx \"(PORT, QUEUE, LCORE), ...\": The list of NIC RX ports and queues handled by the I/O RX lcores.\n This parameter also implicitly defines the list of I/O RX lcores. This is a mandatory parameter.\n\n#. --tx \"(PORT, LCORE), ... \": The list of NIC TX ports handled by the I/O TX lcores.\n This parameter also implicitly defines the list of I/O TX lcores.\n This is a mandatory parameter.\n\n#. --w \"LCORE, ...\": The list of the worker lcores. This is a mandatory parameter.\n\n#. --lpm \"IP / PREFIX => PORT; ...\": The list of LPM rules used by the worker lcores for packet forwarding.\n This is a mandatory parameter.\n\n#. --rsz \"A, B, C, D\": Ring sizes:\n\n #. A = The size (in number of buffer descriptors) of each of the NIC RX rings read by the I/O RX lcores.\n\n #. B = The size (in number of elements) of each of the software rings used by the I/O RX lcores to send packets to worker lcores.\n\n #. C = The size (in number of elements) of each of the software rings used by the worker lcores to send packets to I/O TX lcores.\n\n #. D = The size (in number of buffer descriptors) of each of the NIC TX rings written by I/O TX lcores.\n\n#. --bsz \"(A, B), (C, D), (E, F)\": Burst sizes:\n\n #. A = The I/O RX lcore read burst size from NIC RX.\n\n #. B = The I/O RX lcore write burst size to the output software rings.\n\n #. C = The worker lcore read burst size from the input software rings.\n\n #. D = The worker lcore write burst size to the output software rings.\n\n #. E = The I/O TX lcore read burst size from the input software rings.\n\n #. F = The I/O TX lcore write burst size to the NIC TX.\n\n#. --pos-lb POS: The position of the 1-byte field within the input packet used by the I/O RX lcores\n to identify the worker lcore for the current packet.\n This field needs to be within the first 64 bytes of the input packet.\n\nThe infrastructure of software rings connecting I/O lcores and worker lcores is built by the application\nas a result of the application configuration provided by the user through the application command line parameters.\n\nA specific lcore performing the I/O RX role for a specific set of NIC ports can also perform the I/O TX role\nfor the same or a different set of NIC ports.\nA specific lcore cannot perform both the I/O role (either RX or TX) and the worker role during the same session.\n\nExample:\n\n.. code-block:: console\n\n ./load_balancer -c 0xf8 -n 4 -- --rx \"(0,0,3),(1,0,3)\" --tx \"(0,3),(1,3)\" --w \"4,5,6,7\" --lpm \"1.0.0.0/24=>0; 1.0.1.0/24=>1;\" --pos-lb 29\n\nThere is a single I/O lcore (lcore 3) that handles RX and TX for two NIC ports (ports 0 and 1) that\nhandles packets to/from four worker lcores (lcores 4, 5, 6 and 7) that\nare assigned worker IDs 0 to 3 (worker ID for lcore 4 is 0, for lcore 5 is 1, for lcore 6 is 2 and for lcore 7 is 3).\n\nAssuming that all the input packets are IPv4 packets with no VLAN label and the source IP address of the current packet is A.B.C.D,\nthe worker lcore for the current packet is determined by byte D (which is byte 29).\nThere are two LPM rules that are used by each worker lcore to route packets to the output NIC ports.\n\nThe following table illustrates the packet flow through the system for several possible traffic flows:\n\n+------------+----------------+-----------------+------------------------------+--------------+\n| **Flow #** | **Source** | **Destination** | **Worker ID (Worker lcore)** | **Output** |\n| | **IP Address** | **IP Address** | | **NIC Port** |\n| | | | | |\n+============+================+=================+==============================+==============+\n| 1 | 0.0.0.0 | 1.0.0.1 | 0 (4) | 0 |\n| | | | | |\n+------------+----------------+-----------------+------------------------------+--------------+\n| 2 | 0.0.0.1 | 1.0.1.2 | 1 (5) | 1 |\n| | | | | |\n+------------+----------------+-----------------+------------------------------+--------------+\n| 3 | 0.0.0.14 | 1.0.0.3 | 2 (6) | 0 |\n| | | | | |\n+------------+----------------+-----------------+------------------------------+--------------+\n| 4 | 0.0.0.15 | 1.0.1.4 | 3 (7) | 1 |\n| | | | | |\n+------------+----------------+-----------------+------------------------------+--------------+\n\nNUMA Support\n~~~~~~~~~~~~\n\nThe application has built-in performance enhancements for the NUMA case:\n\n#. One buffer pool per each CPU socket.\n\n#. One LPM table per each CPU socket.\n\n#. Memory for the NIC RX or TX rings is allocated on the same socket with the lcore handling the respective ring.\n\nIn the case where multiple CPU sockets are used in the system,\nit is recommended to enable at least one lcore to fulfill the I/O role for the NIC ports that\nare directly attached to that CPU socket through the PCI Express* bus.\nIt is always recommended to handle the packet I/O with lcores from the same CPU socket as the NICs.\n\nDepending on whether the I/O RX lcore (same CPU socket as NIC RX),\nthe worker lcore and the I/O TX lcore (same CPU socket as NIC TX) handling a specific input packet,\nare on the same or different CPU sockets, the following run-time scenarios are possible:\n\n#. AAA: The packet is received, processed and transmitted without going across CPU sockets.\n\n#. AAB: The packet is received and processed on socket A,\n but as it has to be transmitted on a NIC port connected to socket B,\n the packet is sent to socket B through software rings.\n\n#. ABB: The packet is received on socket A, but as it has to be processed by a worker lcore on socket B,\n the packet is sent to socket B through software rings.\n The packet is transmitted by a NIC port connected to the same CPU socket as the worker lcore that processed it.\n\n#. ABC: The packet is received on socket A, it is processed by an lcore on socket B,\n then it has to be transmitted out by a NIC connected to socket C.\n The performance price for crossing the CPU socket boundary is paid twice for this packet.\n" }, { "path": "doc/guides/sample_app_ug/multi_process.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.. _multi_process_app:\n\nMulti-process Sample Application\n================================\n\nThis chapter describes the example applications for multi-processing that are included in the DPDK.\n\nExample Applications\n--------------------\n\nBuilding the Sample Applications\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe multi-process example applications are built in the same way as other sample applications,\nand as documented in the *DPDK Getting Started Guide*.\nTo build all the example applications:\n\n#. Set RTE_SDK and go to the example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/multi_process\n\n#. Set the target (a default target will be used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the applications:\n\n .. code-block:: console\n\n make\n\n.. note::\n\n If just a specific multi-process application needs to be built,\n the final make command can be run just in that application's directory,\n rather than at the top-level multi-process directory.\n\nBasic Multi-process Example\n~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe examples/simple_mp folder in the DPDK release contains a basic example application to demonstrate how\ntwo DPDK processes can work together using queues and memory pools to share information.\n\nRunning the Application\n^^^^^^^^^^^^^^^^^^^^^^^\n\nTo run the application, start one copy of the simple_mp binary in one terminal,\npassing at least two cores in the coremask, as follows:\n\n.. code-block:: console\n\n ./build/simple_mp -c 3 -n 4 --proc-type=primary\n\nFor the first DPDK process run, the proc-type flag can be omitted or set to auto,\nsince all DPDK processes will default to being a primary instance,\nmeaning they have control over the hugepage shared memory regions.\nThe process should start successfully and display a command prompt as follows:\n\n.. code-block:: console\n\n $ ./build/simple_mp -c 3 -n 4 --proc-type=primary\n EAL: coremask set to 3\n EAL: Detected lcore 0 on socket 0\n EAL: Detected lcore 1 on socket 0\n EAL: Detected lcore 2 on socket 0\n EAL: Detected lcore 3 on socket 0\n ...\n\n EAL: Requesting 2 pages of size 1073741824\n EAL: Requesting 768 pages of size 2097152\n EAL: Ask a virtual area of 0x40000000 bytes\n EAL: Virtual area found at 0x7ff200000000 (size = 0x40000000)\n ...\n\n EAL: check igb_uio module\n EAL: check module finished\n EAL: Master core 0 is ready (tid=54e41820)\n EAL: Core 1 is ready (tid=53b32700)\n\n Starting core 1\n\n simple_mp >\n\nTo run the secondary process to communicate with the primary process,\nagain run the same binary setting at least two cores in the coremask:\n\n.. code-block:: console\n\n ./build/simple_mp -c C -n 4 --proc-type=secondary\n\nWhen running a secondary process such as that shown above, the proc-type parameter can again be specified as auto.\nHowever, omitting the parameter altogether will cause the process to try and start as a primary rather than secondary process.\n\nOnce the process type is specified correctly,\nthe process starts up, displaying largely similar status messages to the primary instance as it initializes.\nOnce again, you will be presented with a command prompt.\n\nOnce both processes are running, messages can be sent between them using the send command.\nAt any stage, either process can be terminated using the quit command.\n\n.. code-block:: console\n\n EAL: Master core 10 is ready (tid=b5f89820) EAL: Master core 8 is ready (tid=864a3820)\n EAL: Core 11 is ready (tid=84ffe700) EAL: Core 9 is ready (tid=85995700)\n Starting core 11 Starting core 9\n simple_mp > send hello_secondary simple_mp > core 9: Received 'hello_secondary'\n simple_mp > core 11: Received 'hello_primary' simple_mp > send hello_primary\n simple_mp > quit simple_mp > quit\n\n.. note::\n\n If the primary instance is terminated, the secondary instance must also be shut-down and restarted after the primary.\n This is necessary because the primary instance will clear and reset the shared memory regions on startup,\n invalidating the secondary process's pointers.\n The secondary process can be stopped and restarted without affecting the primary process.\n\nHow the Application Works\n^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe core of this example application is based on using two queues and a single memory pool in shared memory.\nThese three objects are created at startup by the primary process,\nsince the secondary process cannot create objects in memory as it cannot reserve memory zones,\nand the secondary process then uses lookup functions to attach to these objects as it starts up.\n\n.. code-block:: c\n\n if (rte_eal_process_type() == RTE_PROC_PRIMARY){\n send_ring = rte_ring_create(_PRI_2_SEC, ring_size, SOCKET0, flags);\n recv_ring = rte_ring_create(_SEC_2_PRI, ring_size, SOCKET0, flags);\n message_pool = rte_mempool_create(_MSG_POOL, pool_size, string_size, pool_cache, priv_data_sz, NULL, NULL, NULL, NULL, SOCKET0, flags);\n } else {\n recv_ring = rte_ring_lookup(_PRI_2_SEC);\n send_ring = rte_ring_lookup(_SEC_2_PRI);\n message_pool = rte_mempool_lookup(_MSG_POOL);\n }\n\nNote, however, that the named ring structure used as send_ring in the primary process is the recv_ring in the secondary process.\n\nOnce the rings and memory pools are all available in both the primary and secondary processes,\nthe application simply dedicates two threads to sending and receiving messages respectively.\nThe receive thread simply dequeues any messages on the receive ring, prints them,\nand frees the buffer space used by the messages back to the memory pool.\nThe send thread makes use of the command-prompt library to interactively request user input for messages to send.\nOnce a send command is issued by the user, a buffer is allocated from the memory pool, filled in with the message contents,\nthen enqueued on the appropriate rte_ring.\n\nSymmetric Multi-process Example\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe second example of DPDK multi-process support demonstrates how a set of processes can run in parallel,\nwith each process performing the same set of packet- processing operations.\n(Since each process is identical in functionality to the others,\nwe refer to this as symmetric multi-processing, to differentiate it from asymmetric multi- processing -\nsuch as a client-server mode of operation seen in the next example,\nwhere different processes perform different tasks, yet co-operate to form a packet-processing system.)\nThe following diagram shows the data-flow through the application, using two processes.\n\n.. _figure_sym_multi_proc_app:\n\n.. figure:: img/sym_multi_proc_app.*\n\n Example Data Flow in a Symmetric Multi-process Application\n\n\nAs the diagram shows, each process reads packets from each of the network ports in use.\nRSS is used to distribute incoming packets on each port to different hardware RX queues.\nEach process reads a different RX queue on each port and so does not contend with any other process for that queue access.\nSimilarly, each process writes outgoing packets to a different TX queue on each port.\n\nRunning the Application\n^^^^^^^^^^^^^^^^^^^^^^^\n\nAs with the simple_mp example, the first instance of the symmetric_mp process must be run as the primary instance,\nthough with a number of other application- specific parameters also provided after the EAL arguments.\nThese additional parameters are:\n\n* -p , where portmask is a hexadecimal bitmask of what ports on the system are to be used.\n For example: -p 3 to use ports 0 and 1 only.\n\n* --num-procs , where N is the total number of symmetric_mp instances that will be run side-by-side to perform packet processing.\n This parameter is used to configure the appropriate number of receive queues on each network port.\n\n* --proc-id , where n is a numeric value in the range 0 <= n < N (number of processes, specified above).\n This identifies which symmetric_mp instance is being run, so that each process can read a unique receive queue on each network port.\n\nThe secondary symmetric_mp instances must also have these parameters specified,\nand the first two must be the same as those passed to the primary instance, or errors result.\n\nFor example, to run a set of four symmetric_mp instances, running on lcores 1-4,\nall performing level-2 forwarding of packets between ports 0 and 1,\nthe following commands can be used (assuming run as root):\n\n.. code-block:: console\n\n # ./build/symmetric_mp -c 2 -n 4 --proc-type=auto -- -p 3 --num-procs=4 --proc-id=0\n # ./build/symmetric_mp -c 4 -n 4 --proc-type=auto -- -p 3 --num-procs=4 --proc-id=1\n # ./build/symmetric_mp -c 8 -n 4 --proc-type=auto -- -p 3 --num-procs=4 --proc-id=2\n # ./build/symmetric_mp -c 10 -n 4 --proc-type=auto -- -p 3 --num-procs=4 --proc-id=3\n\n.. note::\n\n In the above example, the process type can be explicitly specified as primary or secondary, rather than auto.\n When using auto, the first process run creates all the memory structures needed for all processes -\n irrespective of whether it has a proc-id of 0, 1, 2 or 3.\n\n.. note::\n\n For the symmetric multi-process example, since all processes work in the same manner,\n once the hugepage shared memory and the network ports are initialized,\n it is not necessary to restart all processes if the primary instance dies.\n Instead, that process can be restarted as a secondary,\n by explicitly setting the proc-type to secondary on the command line.\n (All subsequent instances launched will also need this explicitly specified,\n as auto-detection will detect no primary processes running and therefore attempt to re-initialize shared memory.)\n\nHow the Application Works\n^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe initialization calls in both the primary and secondary instances are the same for the most part,\ncalling the rte_eal_init(), 1 G and 10 G driver initialization and then rte_eal_pci_probe() functions.\nThereafter, the initialization done depends on whether the process is configured as a primary or secondary instance.\n\nIn the primary instance, a memory pool is created for the packet mbufs and the network ports to be used are initialized -\nthe number of RX and TX queues per port being determined by the num-procs parameter passed on the command-line.\nThe structures for the initialized network ports are stored in shared memory and\ntherefore will be accessible by the secondary process as it initializes.\n\n.. code-block:: c\n\n if (num_ports & 1)\n rte_exit(EXIT_FAILURE, \"Application must use an even number of ports\\n\");\n\n for(i = 0; i < num_ports; i++){\n if(proc_type == RTE_PROC_PRIMARY)\n if (smp_port_init(ports[i], mp, (uint16_t)num_procs) < 0)\n rte_exit(EXIT_FAILURE, \"Error initializing ports\\n\");\n }\n\nIn the secondary instance, rather than initializing the network ports, the port information exported by the primary process is used,\ngiving the secondary process access to the hardware and software rings for each network port.\nSimilarly, the memory pool of mbufs is accessed by doing a lookup for it by name:\n\n.. code-block:: c\n\n mp = (proc_type == RTE_PROC_SECONDARY) ? rte_mempool_lookup(_SMP_MBUF_POOL) : rte_mempool_create(_SMP_MBUF_POOL, NB_MBUFS, MBUF_SIZE, ... )\n\nOnce this initialization is complete, the main loop of each process, both primary and secondary,\nis exactly the same - each process reads from each port using the queue corresponding to its proc-id parameter,\nand writes to the corresponding transmit queue on the output port.\n\nClient-Server Multi-process Example\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe third example multi-process application included with the DPDK shows how one can\nuse a client-server type multi-process design to do packet processing.\nIn this example, a single server process performs the packet reception from the ports being used and\ndistributes these packets using round-robin ordering among a set of client processes,\nwhich perform the actual packet processing.\nIn this case, the client applications just perform level-2 forwarding of packets by sending each packet out on a different network port.\n\nThe following diagram shows the data-flow through the application, using two client processes.\n\n.. _figure_client_svr_sym_multi_proc_app:\n\n.. figure:: img/client_svr_sym_multi_proc_app.*\n\n Example Data Flow in a Client-Server Symmetric Multi-process Application\n\n\nRunning the Application\n^^^^^^^^^^^^^^^^^^^^^^^\n\nThe server process must be run initially as the primary process to set up all memory structures for use by the clients.\nIn addition to the EAL parameters, the application- specific parameters are:\n\n* -p , where portmask is a hexadecimal bitmask of what ports on the system are to be used.\n For example: -p 3 to use ports 0 and 1 only.\n\n* -n , where the num-clients parameter is the number of client processes that will process the packets received\n by the server application.\n\n.. note::\n\n In the server process, a single thread, the master thread, that is, the lowest numbered lcore in the coremask, performs all packet I/O.\n If a coremask is specified with more than a single lcore bit set in it,\n an additional lcore will be used for a thread to periodically print packet count statistics.\n\nSince the server application stores configuration data in shared memory, including the network ports to be used,\nthe only application parameter needed by a client process is its client instance ID.\nTherefore, to run a server application on lcore 1 (with lcore 2 printing statistics) along with two client processes running on lcores 3 and 4,\nthe following commands could be used:\n\n.. code-block:: console\n\n # ./mp_server/build/mp_server -c 6 -n 4 -- -p 3 -n 2\n # ./mp_client/build/mp_client -c 8 -n 4 --proc-type=auto -- -n 0\n # ./mp_client/build/mp_client -c 10 -n 4 --proc-type=auto -- -n 1\n\n.. note::\n\n If the server application dies and needs to be restarted, all client applications also need to be restarted,\n as there is no support in the server application for it to run as a secondary process.\n Any client processes that need restarting can be restarted without affecting the server process.\n\nHow the Application Works\n^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe server process performs the network port and data structure initialization much as the symmetric multi-process application does when run as primary.\nOne additional enhancement in this sample application is that the server process stores its port configuration data in a memory zone in hugepage shared memory.\nThis eliminates the need for the client processes to have the portmask parameter passed into them on the command line,\nas is done for the symmetric multi-process application, and therefore eliminates mismatched parameters as a potential source of errors.\n\nIn the same way that the server process is designed to be run as a primary process instance only,\nthe client processes are designed to be run as secondary instances only.\nThey have no code to attempt to create shared memory objects.\nInstead, handles to all needed rings and memory pools are obtained via calls to rte_ring_lookup() and rte_mempool_lookup().\nThe network ports for use by the processes are obtained by loading the network port drivers and probing the PCI bus,\nwhich will, as in the symmetric multi-process example,\nautomatically get access to the network ports using the settings already configured by the primary/server process.\n\nOnce all applications are initialized, the server operates by reading packets from each network port in turn and\ndistributing those packets to the client queues (software rings, one for each client process) in round-robin order.\nOn the client side, the packets are read from the rings in as big of bursts as possible, then routed out to a different network port.\nThe routing used is very simple. All packets received on the first NIC port are transmitted back out on the second port and vice versa.\nSimilarly, packets are routed between the 3rd and 4th network ports and so on.\nThe sending of packets is done by writing the packets directly to the network ports; they are not transferred back via the server process.\n\nIn both the server and the client processes, outgoing packets are buffered before being sent,\nso as to allow the sending of multiple packets in a single burst to improve efficiency.\nFor example, the client process will buffer packets to send,\nuntil either the buffer is full or until we receive no further packets from the server.\n\nMaster-slave Multi-process Example\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe fourth example of DPDK multi-process support demonstrates a master-slave model that\nprovide the capability of application recovery if a slave process crashes or meets unexpected conditions.\nIn addition, it also demonstrates the floating process,\nwhich can run among different cores in contrast to the traditional way of binding a process/thread to a specific CPU core,\nusing the local cache mechanism of mempool structures.\n\nThis application performs the same functionality as the L2 Forwarding sample application,\ntherefore this chapter does not cover that part but describes functionality that is introduced in this multi-process example only.\nPlease refer to Chapter 9, \"L2 Forwarding Sample Application (in Real and Virtualized Environments)\" for more information.\n\nUnlike previous examples where all processes are started from the command line with input arguments, in this example,\nonly one process is spawned from the command line and that process creates other processes.\nThe following section describes this in more detail.\n\nMaster-slave Process Models\n^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe process spawned from the command line is called the *master process* in this document.\nA process created by the master is called a *slave process*.\nThe application has only one master process, but could have multiple slave processes.\n\nOnce the master process begins to run, it tries to initialize all the resources such as\nmemory, CPU cores, driver, ports, and so on, as the other examples do.\nThereafter, it creates slave processes, as shown in the following figure.\n\n.. _figure_master_slave_proc:\n\n.. figure:: img/master_slave_proc.*\n\n Master-slave Process Workflow\n\n\nThe master process calls the rte_eal_mp_remote_launch() EAL function to launch an application function for each pinned thread through the pipe.\nThen, it waits to check if any slave processes have exited.\nIf so, the process tries to re-initialize the resources that belong to that slave and launch them in the pinned thread entry again.\nThe following section describes the recovery procedures in more detail.\n\nFor each pinned thread in EAL, after reading any data from the pipe, it tries to call the function that the application specified.\nIn this master specified function, a fork() call creates a slave process that performs the L2 forwarding task.\nThen, the function waits until the slave exits, is killed or crashes. Thereafter, it notifies the master of this event and returns.\nFinally, the EAL pinned thread waits until the new function is launched.\n\nAfter discussing the master-slave model, it is necessary to mention another issue, global and static variables.\n\nFor multiple-thread cases, all global and static variables have only one copy and they can be accessed by any thread if applicable.\nSo, they can be used to sync or share data among threads.\n\nIn the previous examples, each process has separate global and static variables in memory and are independent of each other.\nIf it is necessary to share the knowledge, some communication mechanism should be deployed, such as, memzone, ring, shared memory, and so on.\nThe global or static variables are not a valid approach to share data among processes.\nFor variables in this example, on the one hand, the slave process inherits all the knowledge of these variables after being created by the master.\nOn the other hand, other processes cannot know if one or more processes modifies them after slave creation since that\nis the nature of a multiple process address space.\nBut this does not mean that these variables cannot be used to share or sync data; it depends on the use case.\nThe following are the possible use cases:\n\n#. The master process starts and initializes a variable and it will never be changed after slave processes created. This case is OK.\n\n#. After the slave processes are created, the master or slave cores need to change a variable, but other processes do not need to know the change.\n This case is also OK.\n\n#. After the slave processes are created, the master or a slave needs to change a variable.\n In the meantime, one or more other process needs to be aware of the change.\n In this case, global and static variables cannot be used to share knowledge. Another communication mechanism is needed.\n A simple approach without lock protection can be a heap buffer allocated by rte_malloc or mem zone.\n\nSlave Process Recovery Mechanism\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nBefore talking about the recovery mechanism, it is necessary to know what is needed before a new slave instance can run if a previous one exited.\n\nWhen a slave process exits, the system returns all the resources allocated for this process automatically.\nHowever, this does not include the resources that were allocated by the DPDK. All the hardware resources are shared among the processes,\nwhich include memzone, mempool, ring, a heap buffer allocated by the rte_malloc library, and so on.\nIf the new instance runs and the allocated resource is not returned, either resource allocation failed or the hardware resource is lost forever.\n\nWhen a slave process runs, it may have dependencies on other processes.\nThey could have execution sequence orders; they could share the ring to communicate; they could share the same port for reception and forwarding;\nthey could use lock structures to do exclusive access in some critical path.\nWhat happens to the dependent process(es) if the peer leaves?\nThe consequence are varied since the dependency cases are complex.\nIt depends on what the processed had shared.\nHowever, it is necessary to notify the peer(s) if one slave exited.\nThen, the peer(s) will be aware of that and wait until the new instance begins to run.\n\nTherefore, to provide the capability to resume the new slave instance if the previous one exited, it is necessary to provide several mechanisms:\n\n#. Keep a resource list for each slave process.\n Before a slave process run, the master should prepare a resource list.\n After it exits, the master could either delete the allocated resources and create new ones,\n or re-initialize those for use by the new instance.\n\n#. Set up a notification mechanism for slave process exit cases. After the specific slave leaves,\n the master should be notified and then help to create a new instance.\n This mechanism is provided in Section 15.1.5.1, \"Master-slave Process Models\".\n\n#. Use a synchronization mechanism among dependent processes.\n The master should have the capability to stop or kill slave processes that have a dependency on the one that has exited.\n Then, after the new instance of exited slave process begins to run, the dependency ones could resume or run from the start.\n The example sends a STOP command to slave processes dependent on the exited one, then they will exit.\n Thereafter, the master creates new instances for the exited slave processes.\n\nThe following diagram describes slave process recovery.\n\n.. _figure_slave_proc_recov:\n\n.. figure:: img/slave_proc_recov.*\n\n Slave Process Recovery Process Flow\n\n\nFloating Process Support\n^^^^^^^^^^^^^^^^^^^^^^^^\n\nWhen the DPDK application runs, there is always a -c option passed in to indicate the cores that are enabled.\nThen, the DPDK creates a thread for each enabled core.\nBy doing so, it creates a 1:1 mapping between the enabled core and each thread.\nThe enabled core always has an ID, therefore, each thread has a unique core ID in the DPDK execution environment.\nWith the ID, each thread can easily access the structures or resources exclusively belonging to it without using function parameter passing.\nIt can easily use the rte_lcore_id() function to get the value in every function that is called.\n\nFor threads/processes not created in that way, either pinned to a core or not, they will not own a unique ID and the\nrte_lcore_id() function will not work in the correct way.\nHowever, sometimes these threads/processes still need the unique ID mechanism to do easy access on structures or resources.\nFor example, the DPDK mempool library provides a local cache mechanism\n(refer to *DPDK Programmer's Guide* , Section 6.4, \"Local Cache\")\nfor fast element allocation and freeing.\nIf using a non-unique ID or a fake one,\na race condition occurs if two or more threads/ processes with the same core ID try to use the local cache.\n\nTherefore, unused core IDs from the passing of parameters with the -c option are used to organize the core ID allocation array.\nOnce the floating process is spawned, it tries to allocate a unique core ID from the array and release it on exit.\n\nA natural way to spawn a floating process is to use the fork() function and allocate a unique core ID from the unused core ID array.\nHowever, it is necessary to write new code to provide a notification mechanism for slave exit\nand make sure the process recovery mechanism can work with it.\n\nTo avoid producing redundant code, the Master-Slave process model is still used to spawn floating processes,\nthen cancel the affinity to specific cores.\nBesides that, clear the core ID assigned to the DPDK spawning a thread that has a 1:1 mapping with the core mask.\nThereafter, get a new core ID from the unused core ID allocation array.\n\nRun the Application\n^^^^^^^^^^^^^^^^^^^\n\nThis example has a command line similar to the L2 Forwarding sample application with a few differences.\n\nTo run the application, start one copy of the l2fwd_fork binary in one terminal.\nUnlike the L2 Forwarding example,\nthis example requires at least three cores since the master process will wait and be accountable for slave process recovery.\nThe command is as follows:\n\n.. code-block:: console\n\n #./build/l2fwd_fork -c 1c -n 4 -- -p 3 -f\n\nThis example provides another -f option to specify the use of floating process.\nIf not specified, the example will use a pinned process to perform the L2 forwarding task.\n\nTo verify the recovery mechanism, proceed as follows: First, check the PID of the slave processes:\n\n.. code-block:: console\n\n #ps -fe | grep l2fwd_fork\n root 5136 4843 29 11:11 pts/1 00:00:05 ./build/l2fwd_fork\n root 5145 5136 98 11:11 pts/1 00:00:11 ./build/l2fwd_fork\n root 5146 5136 98 11:11 pts/1 00:00:11 ./build/l2fwd_fork\n\nThen, kill one of the slaves:\n\n.. code-block:: console\n\n #kill -9 5145\n\nAfter 1 or 2 seconds, check whether the slave has resumed:\n\n.. code-block:: console\n\n #ps -fe | grep l2fwd_fork\n root 5136 4843 3 11:11 pts/1 00:00:06 ./build/l2fwd_fork\n root 5247 5136 99 11:14 pts/1 00:00:01 ./build/l2fwd_fork\n root 5248 5136 99 11:14 pts/1 00:00:01 ./build/l2fwd_fork\n\nIt can also monitor the traffic generator statics to see whether slave processes have resumed.\n\nExplanation\n^^^^^^^^^^^\n\nAs described in previous sections,\nnot all global and static variables need to change to be accessible in multiple processes;\nit depends on how they are used.\nIn this example,\nthe statics info on packets dropped/forwarded/received count needs to be updated by the slave process,\nand the master needs to see the update and print them out.\nSo, it needs to allocate a heap buffer using rte_zmalloc.\nIn addition, if the -f option is specified,\nan array is needed to store the allocated core ID for the floating process so that the master can return it\nafter a slave has exited accidentally.\n\n.. code-block:: c\n\n static int\n l2fwd_malloc_shared_struct(void)\n {\n port_statistics = rte_zmalloc(\"port_stat\", sizeof(struct l2fwd_port_statistics) * RTE_MAX_ETHPORTS, 0);\n\n if (port_statistics == NULL)\n return -1;\n\n /* allocate mapping_id array */\n\n if (float_proc) {\n int i;\n\n mapping_id = rte_malloc(\"mapping_id\", sizeof(unsigned) * RTE_MAX_LCORE, 0);\n if (mapping_id == NULL)\n return -1;\n\n for (i = 0 ;i < RTE_MAX_LCORE; i++)\n mapping_id[i] = INVALID_MAPPING_ID;\n\n }\n return 0;\n }\n\nFor each slave process, packets are received from one port and forwarded to another port that another slave is operating on.\nIf the other slave exits accidentally, the port it is operating on may not work normally,\nso the first slave cannot forward packets to that port.\nThere is a dependency on the port in this case. So, the master should recognize the dependency.\nThe following is the code to detect this dependency:\n\n.. code-block:: c\n\n for (portid = 0; portid < nb_ports; portid++) {\n /* skip ports that are not enabled */\n\n if ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n continue;\n\n /* Find pair ports' lcores */\n\n find_lcore = find_pair_lcore = 0;\n pair_port = l2fwd_dst_ports[portid];\n\n for (i = 0; i < RTE_MAX_LCORE; i++) {\n if (!rte_lcore_is_enabled(i))\n continue;\n\n for (j = 0; j < lcore_queue_conf[i].n_rx_port;j++) {\n if (lcore_queue_conf[i].rx_port_list[j] == portid) {\n lcore = i;\n find_lcore = 1;\n break;\n }\n\n if (lcore_queue_conf[i].rx_port_list[j] == pair_port) {\n pair_lcore = i;\n find_pair_lcore = 1;\n break;\n }\n }\n\n if (find_lcore && find_pair_lcore)\n break;\n }\n\n if (!find_lcore || !find_pair_lcore)\n rte_exit(EXIT_FAILURE, \"Not find port=%d pair\\\\n\", portid);\n\n printf(\"lcore %u and %u paired\\\\n\", lcore, pair_lcore);\n\n lcore_resource[lcore].pair_id = pair_lcore;\n lcore_resource[pair_lcore].pair_id = lcore;\n }\n\nBefore launching the slave process,\nit is necessary to set up the communication channel between the master and slave so that\nthe master can notify the slave if its peer process with the dependency exited.\nIn addition, the master needs to register a callback function in the case where a specific slave exited.\n\n.. code-block:: c\n\n for (i = 0; i < RTE_MAX_LCORE; i++) {\n if (lcore_resource[i].enabled) {\n /* Create ring for master and slave communication */\n\n ret = create_ms_ring(i);\n if (ret != 0)\n rte_exit(EXIT_FAILURE, \"Create ring for lcore=%u failed\",i);\n\n if (flib_register_slave_exit_notify(i,slave_exit_cb) != 0)\n rte_exit(EXIT_FAILURE, \"Register master_trace_slave_exit failed\");\n }\n }\n\nAfter launching the slave process, the master waits and prints out the port statics periodically.\nIf an event indicating that a slave process exited is detected,\nit sends the STOP command to the peer and waits until it has also exited.\nThen, it tries to clean up the execution environment and prepare new resources.\nFinally, the new slave instance is launched.\n\n.. code-block:: c\n\n while (1) {\n sleep(1);\n cur_tsc = rte_rdtsc();\n diff_tsc = cur_tsc - prev_tsc;\n\n /* if timer is enabled */\n\n if (timer_period > 0) {\n /* advance the timer */\n timer_tsc += diff_tsc;\n\n /* if timer has reached its timeout */\n if (unlikely(timer_tsc >= (uint64_t) timer_period)) {\n print_stats();\n\n /* reset the timer */\n timer_tsc = 0;\n }\n }\n\n prev_tsc = cur_tsc;\n\n /* Check any slave need restart or recreate */\n\n rte_spinlock_lock(&res_lock);\n\n for (i = 0; i < RTE_MAX_LCORE; i++) {\n struct lcore_resource_struct *res = &lcore_resource[i];\n struct lcore_resource_struct *pair = &lcore_resource[res->pair_id];\n\n /* If find slave exited, try to reset pair */\n\n if (res->enabled && res->flags && pair->enabled) {\n if (!pair->flags) {\n master_sendcmd_with_ack(pair->lcore_id, CMD_STOP);\n rte_spinlock_unlock(&res_lock);\n sleep(1);\n rte_spinlock_lock(&res_lock);\n if (pair->flags)\n continue;\n }\n\n if (reset_pair(res->lcore_id, pair->lcore_id) != 0)\n rte_exit(EXIT_FAILURE, \"failed to reset slave\");\n\n res->flags = 0;\n pair->flags = 0;\n }\n }\n rte_spinlock_unlock(&res_lock);\n }\n\nWhen the slave process is spawned and starts to run, it checks whether the floating process option is applied.\nIf so, it clears the affinity to a specific core and also sets the unique core ID to 0.\nThen, it tries to allocate a new core ID.\nSince the core ID has changed, the resource allocated by the master cannot work,\nso it remaps the resource to the new core ID slot.\n\n.. code-block:: c\n\n static int\n l2fwd_launch_one_lcore( attribute ((unused)) void *dummy)\n {\n unsigned lcore_id = rte_lcore_id();\n\n if (float_proc) {\n unsigned flcore_id;\n\n /* Change it to floating process, also change it's lcore_id */\n\n clear_cpu_affinity();\n\n RTE_PER_LCORE(_lcore_id) = 0;\n\n /* Get a lcore_id */\n\n if (flib_assign_lcore_id() < 0 ) {\n printf(\"flib_assign_lcore_id failed\\n\");\n return -1;\n }\n\n flcore_id = rte_lcore_id();\n\n /* Set mapping id, so master can return it after slave exited */\n\n mapping_id[lcore_id] = flcore_id;\n printf(\"Org lcore_id = %u, cur lcore_id = %u\\n\",lcore_id, flcore_id);\n remapping_slave_resource(lcore_id, flcore_id);\n }\n\n l2fwd_main_loop();\n\n /* return lcore_id before return */\n if (float_proc) {\n flib_free_lcore_id(rte_lcore_id());\n mapping_id[lcore_id] = INVALID_MAPPING_ID;\n }\n return 0;\n }\n" }, { "path": "doc/guides/sample_app_ug/netmap_compatibility.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nNetmap Compatibility Sample Application\n=======================================\n\nIntroduction\n------------\n\nThe Netmap compatibility library provides a minimal set of APIs to give the ability to programs written against the Netmap APIs\nto be run with minimal changes to their source code, using the DPDK to perform the actual packet I/O.\n\nSince Netmap applications use regular system calls, like open(), ioctl() and\nmmap() to communicate with the Netmap kernel module performing the packet I/O,\nthe compat_netmap library provides a set of similar APIs to use in place of those system calls,\neffectively turning a Netmap application into a DPDK one.\n\nThe provided library is currently minimal and doesn't support all the features that Netmap supports,\nbut is enough to run simple applications, such as the bridge example detailed below.\n\nKnowledge of Netmap is required to understand the rest of this section.\nPlease refer to the Netmap distribution for details about Netmap.\n\nAvailable APIs\n--------------\n\nThe library provides the following drop-in replacements for system calls usually used in Netmap applications:rte_netmap_close()\n\n* rte_netmap_ioctl()\n\n* rte_netmap_open()\n\n* rte_netmap_mmap()\n\n* rte_netmap_poll()\n\nThey use the same signature as their libc counterparts, and can be used as drop-in replacements in most cases.\n\nCaveats\n-------\n\nGiven the difference between the way Netmap and the DPDK approach packet I/O,\nthere are caveats and limitations to be aware of when trying to use the compat_netmap library, the most important of which are listed below.\nAdditional caveats are presented in the $RTE_SDK/examples/netmap_compat/README.md file.\nThese can change as the library is updated:\n\n* Any system call that can potentially affect file descriptors cannot be used with a descriptor returned by the rte_netmap_open() function.\n\nNote that:\n\n* rte_netmap_mmap() merely returns the address of a DPDK memzone.\n The address, length, flags, offset, and so on arguments are therefore ignored completely.\n\n* rte_netmap_poll() only supports infinite (negative) or zero time outs.\n It effectively turns calls to the poll() system call made in a Netmap application into polling of the DPDK ports,\n changing the semantics of the usual POSIX defined poll.\n\n* Not all of Netmap's features are supported: \"host rings\",\n slot flags and so on are not supported or are simply not relevant in the DPDK model.\n\n* The Netmap manual page states that \"a device obtained through /dev/netmap also supports the ioctl supported by network devices\".\n It is not the case with this compatibility layer.\n\n* The Netmap kernel module exposes a sysfs interface to change some internal parameters, such as the size of the shared memory region.\n This interface is not available when using this compatibility layer.\n\nPorting Netmap Applications\n---------------------------\n\nPorting Netmap applications typically involves two major steps:\n\n* Changing the system calls to use their compat_netmap library counterparts\n\n* Adding further DPDK initialization code\n\nSince the compat_netmap functions have the same signature as the usual libc calls, the change is in most cases trivial.\n\nThe usual DPDK initialization code involving rte_eal_init() and rte_eal_pci_probe()\nhas to be added to the Netmap application in the same way it is used in all other DPDK sample applications.\nPlease refer to the *DPDK Programmer's Guide* - Rel 1.4 EAR and example source code for details about initialization.\n\nIn addition of the regular DPDK initialization code,\nthe ported application needs to call initialization functions for the compat_netmap library,\nnamely rte_netmap_init() and rte_netmap_init_port().\n\nThese two initialization functions take compat_netmap specific data structures as parameters:\nstruct rte_netmap_conf and struct rte_netmap_port_conf.\nThose structures' fields are Netmap related and are self-explanatory for developers familiar with Netmap.\nThey are defined in $RTE_SDK/examples/netmap_compat/ lib/compat_netmap.h.\n\nThe bridge application is an example largely based on the bridge example shipped with the Netmap distribution.\nIt shows how a minimal Netmap application with minimal and straightforward source code changes can be run on top of the DPDK.\nPlease refer to $RTE_SDK/examples/netmap_compat/bridge/bridge.c for an example of ported application.\n\nCompiling the \"bridge\" Sample Application\n-----------------------------------------\n\n#. Go to the example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/netmap_compat\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the \"bridge\" Sample Application\n---------------------------------------\n\nThe application requires a single command line option:\n\n.. code-block:: console\n\n ./build/packet_ordering [EAL options] -- -p PORT_A [-p PORT_B]\n\nwhere,\n\n* -p INTERFACE is the number of a valid DPDK port to use.\n\n If a single -p parameter is given, the interface will send back all the traffic it receives.\n If two -p parameters are given, the two interfaces form a bridge,\n where traffic received on one interface is replicated and sent by the other interface.\n\nTo run the application in a linuxapp environment using port 0 and 2, issue the following command:\n\n.. code-block:: console\n\n ./build/packet_ordering [EAL options] -- -p 0 -p 2\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications and\nthe Environment Abstraction Layer (EAL) options.\n\nNote that unlike a traditional bridge or the l2fwd sample application, no MAC address changes are done on the frames.\nDo not forget to take that into account when configuring your traffic generators if you decide to test this sample application.\n" }, { "path": "doc/guides/sample_app_ug/packet_ordering.rst", "content": ".. BSD LICENSE\n Copyright(c) 2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nPacket Ordering Application\n============================\n\nThe Packet Ordering sample app simply shows the impact of reordering a stream.\nIt's meant to stress the library with different configurations for performance.\n\nOverview\n--------\n\nThe application uses at least three CPU cores:\n\n* RX core (maser core) receives traffic from the NIC ports and feeds Worker\n cores with traffic through SW queues.\n\n* Worker core (slave core) basically do some light work on the packet.\n Currently it modifies the output port of the packet for configurations with\n more than one port enabled.\n\n* TX Core (slave core) receives traffic from Worker cores through software queues,\n inserts out-of-order packets into reorder buffer, extracts ordered packets\n from the reorder buffer and sends them to the NIC ports for transmission.\n\nCompiling the Application\n--------------------------\n\n#. Go to the example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/helloworld\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the *DPDK Getting Started* Guide for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nRefer to *DPDK Getting Started Guide* for general information on running applications\nand the Environment Abstraction Layer (EAL) options.\n\nApplication Command Line\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe application execution command line is:\n\n.. code-block:: console\n\n ./test-pipeline [EAL options] -- -p PORTMASK [--disable-reorder]\n\nThe -c EAL CPU_COREMASK option has to contain at least 3 CPU cores.\nThe first CPU core in the core mask is the master core and would be assigned to\nRX core, the last to TX core and the rest to Worker cores.\n\nThe PORTMASK parameter must contain either 1 or even enabled port numbers.\nWhen setting more than 1 port, traffic would be forwarded in pairs.\nFor example, if we enable 4 ports, traffic from port 0 to 1 and from 1 to 0,\nthen the other pair from 2 to 3 and from 3 to 2, having [0,1] and [2,3] pairs.\n\nThe disable-reorder long option does, as its name implies, disable the reordering\nof traffic, which should help evaluate reordering performance impact.\n" }, { "path": "doc/guides/sample_app_ug/proc_info.rst", "content": "\n.. BSD LICENSE\n Copyright(c) 2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nproc_info Application\n========================\n\nThe proc_info application is a Data Plane Development Kit (DPDK) application\nthat runs as a DPDK secondary process and is capable of retrieving port\nstatistics, resetting port statistics and printing DPDK memory information.\nThis application extends the original functionality that was supported by\ndump_cfg.\n\nRunning the Application\n-----------------------\nThe application has a number of command line options:\n\n.. code-block:: console\n\n ./$(RTE_TARGET)/app/proc_info -- -m | [-p PORTMASK] [--stats | --xstats |\n --stats-reset | --xstats-reset]\n\nParameters\n~~~~~~~~~~\n**-p PORTMASK**: Hexadecimal bitmask of ports to configure.\n\n**--stats**\nThe stats parameter controls the printing of generic port statistics. If no\nport mask is specified stats are printed for all DPDK ports.\n\n**--xstats**\nThe stats parameter controls the printing of extended port statistics. If no\nport mask is specified xstats are printed for all DPDK ports.\n\n**--stats-reset**\nThe stats-reset parameter controls the resetting of generic port statistics. If\nno port mask is specified, the generic stats are reset for all DPDK ports.\n\n**--xstats-reset**\nThe xstats-reset parameter controls the resetting of extended port statistics.\nIf no port mask is specified xstats are reset for all DPDK ports.\n\n**-m**: Print DPDK memory information.\n" }, { "path": "doc/guides/sample_app_ug/qos_metering.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nQoS Metering Sample Application\n===============================\n\nThe QoS meter sample application is an example that demonstrates the use of DPDK to provide QoS marking and metering,\nas defined by RFC2697 for Single Rate Three Color Marker (srTCM) and RFC 2698 for Two Rate Three Color Marker (trTCM) algorithm.\n\nOverview\n--------\n\nThe application uses a single thread for reading the packets from the RX port,\nmetering, marking them with the appropriate color (green, yellow or red) and writing them to the TX port.\n\nA policing scheme can be applied before writing the packets to the TX port by dropping or\nchanging the color of the packet in a static manner depending on both the input and output colors of the packets that are processed by the meter.\n\nThe operation mode can be selected as compile time out of the following options:\n\n* Simple forwarding\n\n* srTCM color blind\n\n* srTCM color aware\n\n* srTCM color blind\n\n* srTCM color aware\n\nPlease refer to RFC2697 and RFC2698 for details about the srTCM and trTCM configurable parameters\n(CIR, CBS and EBS for srTCM; CIR, PIR, CBS and PBS for trTCM).\n\nThe color blind modes are functionally equivalent with the color-aware modes when\nall the incoming packets are colored as green.\n\nCompiling the Application\n-------------------------\n\n#. Go to the example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/qos_meter\n\n#. Set the target\n (a default target is used if not specified):\n\n .. note::\n\n This application is intended as a linuxapp only.\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nThe application execution command line is as below:\n\n.. code-block:: console\n\n ./qos_meter [EAL options] -- -p PORTMASK\n\nThe application is constrained to use a single core in the EAL core mask and 2 ports only in the application port mask\n(first port from the port mask is used for RX and the other port in the core mask is used for TX).\n\nRefer to *DPDK Getting Started Guide* for general information on running applications and\nthe Environment Abstraction Layer (EAL) options.\n\nExplanation\n-----------\n\nSelecting one of the metering modes is done with these defines:\n\n.. code-block:: c\n\n #define APP_MODE_FWD 0\n #define APP_MODE_SRTCM_COLOR_BLIND 1\n #define APP_MODE_SRTCM_COLOR_AWARE 2\n #define APP_MODE_TRTCM_COLOR_BLIND 3\n #define APP_MODE_TRTCM_COLOR_AWARE 4\n\n #define APP_MODE APP_MODE_SRTCM_COLOR_BLIND\n\nTo simplify debugging (for example, by using the traffic generator RX side MAC address based packet filtering feature),\nthe color is defined as the LSB byte of the destination MAC address.\n\nThe traffic meter parameters are configured in the application source code with following default values:\n\n.. code-block:: c\n\n struct rte_meter_srtcm_params app_srtcm_params[] = {\n\n {.cir = 1000000 * 46, .cbs = 2048, .ebs = 2048},\n\n };\n\n struct rte_meter_trtcm_params app_trtcm_params[] = {\n\n {.cir = 1000000 * 46, .pir = 1500000 * 46, .cbs = 2048, .pbs = 2048},\n\n };\n\nAssuming the input traffic is generated at line rate and all packets are 64 bytes Ethernet frames (IPv4 packet size of 46 bytes)\nand green, the expected output traffic should be marked as shown in the following table:\n\n.. _table_qos_metering_1:\n\n.. table:: Output Traffic Marking\n\n +-------------+------------------+-------------------+----------------+\n | **Mode** | **Green (Mpps)** | **Yellow (Mpps)** | **Red (Mpps)** |\n | | | | |\n +=============+==================+===================+================+\n | srTCM blind | 1 | 1 | 12.88 |\n | | | | |\n +-------------+------------------+-------------------+----------------+\n | srTCM color | 1 | 1 | 12.88 |\n | | | | |\n +-------------+------------------+-------------------+----------------+\n | trTCM blind | 1 | 0.5 | 13.38 |\n | | | | |\n +-------------+------------------+-------------------+----------------+\n | trTCM color | 1 | 0.5 | 13.38 |\n | | | | |\n +-------------+------------------+-------------------+----------------+\n | FWD | 14.88 | 0 | 0 |\n | | | | |\n +-------------+------------------+-------------------+----------------+\n\nTo set up the policing scheme as desired, it is necessary to modify the main.h source file,\nwhere this policy is implemented as a static structure, as follows:\n\n.. code-block:: c\n\n int policer_table[e_RTE_METER_COLORS][e_RTE_METER_COLORS] =\n {\n { GREEN, RED, RED},\n { DROP, YELLOW, RED},\n { DROP, DROP, RED}\n };\n\nWhere rows indicate the input color, columns indicate the output color,\nand the value that is stored in the table indicates the action to be taken for that particular case.\n\nThere are four different actions:\n\n* GREEN: The packet's color is changed to green.\n\n* YELLOW: The packet's color is changed to yellow.\n\n* RED: The packet's color is changed to red.\n\n* DROP: The packet is dropped.\n\nIn this particular case:\n\n* Every packet which input and output color are the same, keeps the same color.\n\n* Every packet which color has improved is dropped (this particular case can't happen, so these values will not be used).\n\n* For the rest of the cases, the color is changed to red.\n" }, { "path": "doc/guides/sample_app_ug/qos_scheduler.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nQoS Scheduler Sample Application\n================================\n\nThe QoS sample application demonstrates the use of the DPDK to provide QoS scheduling.\n\nOverview\n--------\n\nThe architecture of the QoS scheduler application is shown in the following figure.\n\n.. _figure_qos_sched_app_arch:\n\n.. figure:: img/qos_sched_app_arch.*\n\n QoS Scheduler Application Architecture\n\n\nThere are two flavors of the runtime execution for this application,\nwith two or three threads per each packet flow configuration being used.\nThe RX thread reads packets from the RX port,\nclassifies the packets based on the double VLAN (outer and inner) and\nthe lower two bytes of the IP destination address and puts them into the ring queue.\nThe worker thread dequeues the packets from the ring and calls the QoS scheduler enqueue/dequeue functions.\nIf a separate TX core is used, these are sent to the TX ring.\nOtherwise, they are sent directly to the TX port.\nThe TX thread, if present, reads from the TX ring and write the packets to the TX port.\n\nCompiling the Application\n-------------------------\n\nTo compile the application:\n\n#. Go to the sample application directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk cd ${RTE_SDK}/examples/qos_sched\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. note::\n\n This application is intended as a linuxapp only.\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\n.. note::\n\n To get statistics on the sample app using the command line interface as described in the next section,\n DPDK must be compiled defining *CONFIG_RTE_SCHED_COLLECT_STATS*,\n which can be done by changing the configuration file for the specific target to be compiled.\n\nRunning the Application\n-----------------------\n\n.. note::\n\n In order to run the application, a total of at least 4\n G of huge pages must be set up for each of the used sockets (depending on the cores in use).\n\nThe application has a number of command line options:\n\n.. code-block:: console\n\n ./qos_sched [EAL options] -- \n\nMandatory application parameters include:\n\n* --pfc \"RX PORT, TX PORT, RX LCORE, WT LCORE, TX CORE\": Packet flow configuration.\n Multiple pfc entities can be configured in the command line,\n having 4 or 5 items (if TX core defined or not).\n\nOptional application parameters include:\n\n* -i: It makes the application to start in the interactive mode.\n In this mode, the application shows a command line that can be used for obtaining statistics while\n scheduling is taking place (see interactive mode below for more information).\n\n* --mst n: Master core index (the default value is 1).\n\n* --rsz \"A, B, C\": Ring sizes:\n\n* A = Size (in number of buffer descriptors) of each of the NIC RX rings read\n by the I/O RX lcores (the default value is 128).\n\n* B = Size (in number of elements) of each of the software rings used\n by the I/O RX lcores to send packets to worker lcores (the default value is 8192).\n\n* C = Size (in number of buffer descriptors) of each of the NIC TX rings written\n by worker lcores (the default value is 256)\n\n* --bsz \"A, B, C, D\": Burst sizes\n\n* A = I/O RX lcore read burst size from the NIC RX (the default value is 64)\n\n* B = I/O RX lcore write burst size to the output software rings,\n worker lcore read burst size from input software rings,QoS enqueue size (the default value is 64)\n\n* C = QoS dequeue size (the default value is 32)\n\n* D = Worker lcore write burst size to the NIC TX (the default value is 64)\n\n* --msz M: Mempool size (in number of mbufs) for each pfc (default 2097152)\n\n* --rth \"A, B, C\": The RX queue threshold parameters\n\n* A = RX prefetch threshold (the default value is 8)\n\n* B = RX host threshold (the default value is 8)\n\n* C = RX write-back threshold (the default value is 4)\n\n* --tth \"A, B, C\": TX queue threshold parameters\n\n* A = TX prefetch threshold (the default value is 36)\n\n* B = TX host threshold (the default value is 0)\n\n* C = TX write-back threshold (the default value is 0)\n\n* --cfg FILE: Profile configuration to load\n\nRefer to *DPDK Getting Started Guide* for general information on running applications and\nthe Environment Abstraction Layer (EAL) options.\n\nThe profile configuration file defines all the port/subport/pipe/traffic class/queue parameters\nneeded for the QoS scheduler configuration.\n\nThe profile file has the following format:\n\n::\n\n ; port configuration [port]\n\n frame overhead = 24\n number of subports per port = 1\n number of pipes per subport = 4096\n queue sizes = 64 64 64 64\n\n ; Subport configuration\n\n [subport 0]\n tb rate = 1250000000; Bytes per second\n tb size = 1000000; Bytes\n tc 0 rate = 1250000000; Bytes per second\n tc 1 rate = 1250000000; Bytes per second\n tc 2 rate = 1250000000; Bytes per second\n tc 3 rate = 1250000000; Bytes per second\n tc period = 10; Milliseconds\n tc oversubscription period = 10; Milliseconds\n\n pipe 0-4095 = 0; These pipes are configured with pipe profile 0\n\n ; Pipe configuration\n\n [pipe profile 0]\n tb rate = 305175; Bytes per second\n tb size = 1000000; Bytes\n\n tc 0 rate = 305175; Bytes per second\n tc 1 rate = 305175; Bytes per second\n tc 2 rate = 305175; Bytes per second\n tc 3 rate = 305175; Bytes per second\n tc period = 40; Milliseconds\n\n tc 0 oversubscription weight = 1\n tc 1 oversubscription weight = 1\n tc 2 oversubscription weight = 1\n tc 3 oversubscription weight = 1\n\n tc 0 wrr weights = 1 1 1 1\n tc 1 wrr weights = 1 1 1 1\n tc 2 wrr weights = 1 1 1 1\n tc 3 wrr weights = 1 1 1 1\n\n ; RED params per traffic class and color (Green / Yellow / Red)\n\n [red]\n tc 0 wred min = 48 40 32\n tc 0 wred max = 64 64 64\n tc 0 wred inv prob = 10 10 10\n tc 0 wred weight = 9 9 9\n\n tc 1 wred min = 48 40 32\n tc 1 wred max = 64 64 64\n tc 1 wred inv prob = 10 10 10\n tc 1 wred weight = 9 9 9\n\n tc 2 wred min = 48 40 32\n tc 2 wred max = 64 64 64\n tc 2 wred inv prob = 10 10 10\n tc 2 wred weight = 9 9 9\n\n tc 3 wred min = 48 40 32\n tc 3 wred max = 64 64 64\n tc 3 wred inv prob = 10 10 10\n tc 3 wred weight = 9 9 9\n\nInteractive mode\n~~~~~~~~~~~~~~~~\n\nThese are the commands that are currently working under the command line interface:\n\n* Control Commands\n\n* --quit: Quits the application.\n\n* General Statistics\n\n * stats app: Shows a table with in-app calculated statistics.\n\n * stats port X subport Y: For a specific subport, it shows the number of packets that\n went through the scheduler properly and the number of packets that were dropped.\n The same information is shown in bytes.\n The information is displayed in a table separating it in different traffic classes.\n\n * stats port X subport Y pipe Z: For a specific pipe, it shows the number of packets that\n went through the scheduler properly and the number of packets that were dropped.\n The same information is shown in bytes.\n This information is displayed in a table separating it in individual queues.\n\n* Average queue size\n\nAll of these commands work the same way, averaging the number of packets throughout a specific subset of queues.\n\nTwo parameters can be configured for this prior to calling any of these commands:\n\n * qavg n X: n is the number of times that the calculation will take place.\n Bigger numbers provide higher accuracy. The default value is 10.\n\n * qavg period X: period is the number of microseconds that will be allowed between each calculation.\n The default value is 100.\n\nThe commands that can be used for measuring average queue size are:\n\n* qavg port X subport Y: Show average queue size per subport.\n\n* qavg port X subport Y tc Z: Show average queue size per subport for a specific traffic class.\n\n* qavg port X subport Y pipe Z: Show average queue size per pipe.\n\n* qavg port X subport Y pipe Z tc A: Show average queue size per pipe for a specific traffic class.\n\n* qavg port X subport Y pipe Z tc A q B: Show average queue size of a specific queue.\n\nExample\n~~~~~~~\n\nThe following is an example command with a single packet flow configuration:\n\n.. code-block:: console\n\n ./qos_sched -c a2 -n 4 -- --pfc \"3,2,5,7\" --cfg ./profile.cfg\n\nThis example uses a single packet flow configuration which creates one RX thread on lcore 5 reading\nfrom port 3 and a worker thread on lcore 7 writing to port 2.\n\nAnother example with 2 packet flow configurations using different ports but sharing the same core for QoS scheduler is given below:\n\n.. code-block:: console\n\n ./qos_sched -c c6 -n 4 -- --pfc \"3,2,2,6,7\" --pfc \"1,0,2,6,7\" --cfg ./profile.cfg\n\nNote that independent cores for the packet flow configurations for each of the RX, WT and TX thread are also supported,\nproviding flexibility to balance the work.\n\nThe EAL coremask is constrained to contain the default mastercore 1 and the RX, WT and TX cores only.\n\nExplanation\n-----------\n\nThe Port/Subport/Pipe/Traffic Class/Queue are the hierarchical entities in a typical QoS application:\n\n* A subport represents a predefined group of users.\n\n* A pipe represents an individual user/subscriber.\n\n* A traffic class is the representation of a different traffic type with a specific loss rate,\n delay and jitter requirements; such as data voice, video or data transfers.\n\n* A queue hosts packets from one or multiple connections of the same type belonging to the same user.\n\nThe traffic flows that need to be configured are application dependent.\nThis application classifies based on the QinQ double VLAN tags and the IP destination address as indicated in the following table.\n\n.. _table_qos_scheduler_1:\n\n.. table:: Entity Types\n\n +----------------+-------------------------+--------------------------------------------------+----------------------------------+\n | **Level Name** | **Siblings per Parent** | **QoS Functional Description** | **Selected By** |\n | | | | |\n +================+=========================+==================================================+==================================+\n | Port | - | Ethernet port | Physical port |\n | | | | |\n +----------------+-------------------------+--------------------------------------------------+----------------------------------+\n | Subport | Config (8) | Traffic shaped (token bucket) | Outer VLAN tag |\n | | | | |\n +----------------+-------------------------+--------------------------------------------------+----------------------------------+\n | Pipe | Config (4k) | Traffic shaped (token bucket) | Inner VLAN tag |\n | | | | |\n +----------------+-------------------------+--------------------------------------------------+----------------------------------+\n | Traffic Class | 4 | TCs of the same pipe services in strict priority | Destination IP address (0.0.X.0) |\n | | | | |\n +----------------+-------------------------+--------------------------------------------------+----------------------------------+\n | Queue | 4 | Queue of the same TC serviced in WRR | Destination IP address (0.0.0.X) |\n | | | | |\n +----------------+-------------------------+--------------------------------------------------+----------------------------------+\n\nPlease refer to the \"QoS Scheduler\" chapter in the *DPDK Programmer's Guide* for more information about these parameters.\n" }, { "path": "doc/guides/sample_app_ug/quota_watermark.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nQuota and Watermark Sample Application\n======================================\n\nThe Quota and Watermark sample application is a simple example of packet processing using Data Plane Development Kit (DPDK) that\nshowcases the use of a quota as the maximum number of packets enqueue/dequeue at a time and low and high watermarks\nto signal low and high ring usage respectively.\n\nAdditionally, it shows how ring watermarks can be used to feedback congestion notifications to data producers by\ntemporarily stopping processing overloaded rings and sending Ethernet flow control frames.\n\nThis sample application is split in two parts:\n\n* qw - The core quota and watermark sample application\n\n* qwctl - A command line tool to alter quota and watermarks while qw is running\n\nOverview\n--------\n\nThe Quota and Watermark sample application performs forwarding for each packet that is received on a given port.\nThe destination port is the adjacent port from the enabled port mask, that is,\nif the first four ports are enabled (port mask 0xf), ports 0 and 1 forward into each other,\nand ports 2 and 3 forward into each other.\nThe MAC addresses of the forwarded Ethernet frames are not affected.\n\nInternally, packets are pulled from the ports by the master logical core and put on a variable length processing pipeline,\neach stage of which being connected by rings, as shown in :numref:`figure_pipeline_overview`.\n\n.. _figure_pipeline_overview:\n\n.. figure:: img/pipeline_overview.*\n\n Pipeline Overview\n\n\nAn adjustable quota value controls how many packets are being moved through the pipeline per enqueue and dequeue.\nAdjustable watermark values associated with the rings control a back-off mechanism that\ntries to prevent the pipeline from being overloaded by:\n\n* Stopping enqueuing on rings for which the usage has crossed the high watermark threshold\n\n* Sending Ethernet pause frames\n\n* Only resuming enqueuing on a ring once its usage goes below a global low watermark threshold\n\nThis mechanism allows congestion notifications to go up the ring pipeline and\neventually lead to an Ethernet flow control frame being send to the source.\n\nOn top of serving as an example of quota and watermark usage,\nthis application can be used to benchmark ring based processing pipelines performance using a traffic- generator,\nas shown in :numref:`figure_ring_pipeline_perf_setup`.\n\n.. _figure_ring_pipeline_perf_setup:\n\n.. figure:: img/ring_pipeline_perf_setup.*\n\n Ring-based Processing Pipeline Performance Setup\n\n\nCompiling the Application\n-------------------------\n\n#. Go to the example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/quota_watermark\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nThe core application, qw, has to be started first.\n\nOnce it is up and running, one can alter quota and watermarks while it runs using the control application, qwctl.\n\nRunning the Core Application\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe application requires a single command line option:\n\n.. code-block:: console\n\n ./qw/build/qw [EAL options] -- -p PORTMASK\n\nwhere,\n\n-p PORTMASK: A hexadecimal bitmask of the ports to configure\n\nTo run the application in a linuxapp environment with four logical cores and ports 0 and 2,\nissue the following command:\n\n.. code-block:: console\n\n ./qw/build/qw -c f -n 4 -- -p 5\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications and\nthe Environment Abstraction Layer (EAL) options.\n\nRunning the Control Application\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe control application requires a number of command line options:\n\n.. code-block:: console\n\n ./qwctl/build/qwctl [EAL options] --proc-type=secondary\n\nThe --proc-type=secondary option is necessary for the EAL to properly initialize the control application to\nuse the same huge pages as the core application and thus be able to access its rings.\n\nTo run the application in a linuxapp environment on logical core 0, issue the following command:\n\n.. code-block:: console\n\n ./qwctl/build/qwctl -c 1 -n 4 --proc-type=secondary\n\nRefer to the *DPDK Getting Started* Guide for general information on running applications and\nthe Environment Abstraction Layer (EAL) options.\n\nqwctl is an interactive command line that let the user change variables in a running instance of qw.\nThe help command gives a list of available commands:\n\n.. code-block:: console\n\n $ qwctl > help\n\nCode Overview\n-------------\n\nThe following sections provide a quick guide to the application's source code.\n\nCore Application - qw\n~~~~~~~~~~~~~~~~~~~~~\n\nEAL and Drivers Setup\n^^^^^^^^^^^^^^^^^^^^^\n\nThe EAL arguments are parsed at the beginning of the main() function:\n\n.. code-block:: c\n\n ret = rte_eal_init(argc, argv);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Cannot initialize EAL\\n\");\n\n argc -= ret;\n argv += ret;\n\nThen, a call to init_dpdk(), defined in init.c, is made to initialize the poll mode drivers:\n\n.. code-block:: c\n\n void\n init_dpdk(void)\n {\n int ret;\n\n /* Bind the drivers to usable devices */\n\n ret = rte_eal_pci_probe();\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"rte_eal_pci_probe(): error %d\\n\", ret);\n\n if (rte_eth_dev_count() < 2)\n rte_exit(EXIT_FAILURE, \"Not enough Ethernet port available\\n\");\n }\n\nTo fully understand this code, it is recommended to study the chapters that relate to the *Poll Mode Driver*\nin the *DPDK Getting Started Guide* and the *DPDK API Reference*.\n\nShared Variables Setup\n^^^^^^^^^^^^^^^^^^^^^^\n\nThe quota and low_watermark shared variables are put into an rte_memzone using a call to setup_shared_variables():\n\n.. code-block:: c\n\n void\n setup_shared_variables(void)\n {\n const struct rte_memzone *qw_memzone;\n\n qw_memzone = rte_memzone_reserve(QUOTA_WATERMARK_MEMZONE_NAME, 2 * sizeof(int), rte_socket_id(), RTE_MEMZONE_2MB);\n\n if (qw_memzone == NULL)\n rte_exit(EXIT_FAILURE, \"%s\\n\", rte_strerror(rte_errno));\n\n quota = qw_memzone->addr;\n low_watermark = (unsigned int *) qw_memzone->addr + sizeof(int);\n }\n\nThese two variables are initialized to a default value in main() and\ncan be changed while qw is running using the qwctl control program.\n\nApplication Arguments\n^^^^^^^^^^^^^^^^^^^^^\n\nThe qw application only takes one argument: a port mask that specifies which ports should be used by the application.\nAt least two ports are needed to run the application and there should be an even number of ports given in the port mask.\n\nThe port mask parsing is done in parse_qw_args(), defined in args.c.\n\nMbuf Pool Initialization\n^^^^^^^^^^^^^^^^^^^^^^^^\n\nOnce the application's arguments are parsed, an mbuf pool is created.\nIt contains a set of mbuf objects that are used by the driver and the application to store network packets:\n\n.. code-block:: c\n\n /* Create a pool of mbuf to store packets */\n\n mbuf_pool = rte_mempool_create(\"mbuf_pool\", MBUF_PER_POOL, MBUF_SIZE, 32, sizeof(struct rte_pktmbuf_pool_private),\n rte_pktmbuf_pool_init, NULL, rte_pktmbuf_init, NULL, rte_socket_id(), 0);\n\n if (mbuf_pool == NULL)\n rte_panic(\"%s\\n\", rte_strerror(rte_errno));\n\nThe rte_mempool is a generic structure used to handle pools of objects.\nIn this case, it is necessary to create a pool that will be used by the driver,\nwhich expects to have some reserved space in the mempool structure, sizeof(struct rte_pktmbuf_pool_private) bytes.\n\nThe number of allocated pkt mbufs is MBUF_PER_POOL, with a size of MBUF_SIZE each.\nA per-lcore cache of 32 mbufs is kept.\nThe memory is allocated in on the master lcore's socket, but it is possible to extend this code to allocate one mbuf pool per socket.\n\nTwo callback pointers are also given to the rte_mempool_create() function:\n\n* The first callback pointer is to rte_pktmbuf_pool_init() and is used to initialize the private data of the mempool,\n which is needed by the driver.\n This function is provided by the mbuf API, but can be copied and extended by the developer.\n\n* The second callback pointer given to rte_mempool_create() is the mbuf initializer.\n\nThe default is used, that is, rte_pktmbuf_init(), which is provided in the rte_mbuf library.\nIf a more complex application wants to extend the rte_pktmbuf structure for its own needs,\na new function derived from rte_pktmbuf_init() can be created.\n\nPorts Configuration and Pairing\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nEach port in the port mask is configured and a corresponding ring is created in the master lcore's array of rings.\nThis ring is the first in the pipeline and will hold the packets directly coming from the port.\n\n.. code-block:: c\n\n for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++)\n if (is_bit_set(port_id, portmask)) {\n configure_eth_port(port_id);\n init_ring(master_lcore_id, port_id);\n }\n\n pair_ports();\n\nThe configure_eth_port() and init_ring() functions are used to configure a port and a ring respectively and are defined in init.c.\nThey make use of the DPDK APIs defined in rte_eth.h and rte_ring.h.\n\npair_ports() builds the port_pairs[] array so that its key-value pairs are a mapping between reception and transmission ports.\nIt is defined in init.c.\n\nLogical Cores Assignment\n^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe application uses the master logical core to poll all the ports for new packets and enqueue them on a ring associated with the port.\n\nEach logical core except the last runs pipeline_stage() after a ring for each used port is initialized on that core.\npipeline_stage() on core X dequeues packets from core X-1's rings and enqueue them on its own rings. See :numref:`figure_threads_pipelines`.\n\n.. code-block:: c\n\n /* Start pipeline_stage() on all the available slave lcore but the last */\n\n for (lcore_id = 0 ; lcore_id < last_lcore_id; lcore_id++) {\n if (rte_lcore_is_enabled(lcore_id) && lcore_id != master_lcore_id) {\n for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++)\n if (is_bit_set(port_id, portmask))\n init_ring(lcore_id, port_id);\n\n rte_eal_remote_launch(pipeline_stage, NULL, lcore_id);\n }\n }\n\nThe last available logical core runs send_stage(),\nwhich is the last stage of the pipeline dequeuing packets from the last ring in the pipeline and\nsending them out on the destination port setup by pair_ports().\n\n.. code-block:: c\n\n /* Start send_stage() on the last slave core */\n\n rte_eal_remote_launch(send_stage, NULL, last_lcore_id);\n\nReceive, Process and Transmit Packets\n^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n\n.. _figure_threads_pipelines:\n\n.. figure:: img/threads_pipelines.*\n\n Threads and Pipelines\n\n\nIn the receive_stage() function running on the master logical core,\nthe main task is to read ingress packets from the RX ports and enqueue them\non the port's corresponding first ring in the pipeline.\nThis is done using the following code:\n\n.. code-block:: c\n\n lcore_id = rte_lcore_id();\n\n /* Process each port round robin style */\n\n for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {\n if (!is_bit_set(port_id, portmask))\n continue;\n\n ring = rings[lcore_id][port_id];\n\n if (ring_state[port_id] != RING_READY) {\n if (rte_ring_count(ring) > *low_watermark)\n continue;\n else\n ring_state[port_id] = RING_READY;\n }\n\n /* Enqueue received packets on the RX ring */\n\n nb_rx_pkts = rte_eth_rx_burst(port_id, 0, pkts, *quota);\n\n ret = rte_ring_enqueue_bulk(ring, (void *) pkts, nb_rx_pkts);\n if (ret == -EDQUOT) {\n ring_state[port_id] = RING_OVERLOADED;\n send_pause_frame(port_id, 1337);\n }\n }\n\nFor each port in the port mask, the corresponding ring's pointer is fetched into ring and that ring's state is checked:\n\n* If it is in the RING_READY state, \\*quota packets are grabbed from the port and put on the ring.\n Should this operation make the ring's usage cross its high watermark,\n the ring is marked as overloaded and an Ethernet flow control frame is sent to the source.\n\n* If it is not in the RING_READY state, this port is ignored until the ring's usage crosses the \\*low_watermark value.\n\nThe pipeline_stage() function's task is to process and move packets from the preceding pipeline stage.\nThis thread is running on most of the logical cores to create and arbitrarily long pipeline.\n\n.. code-block:: c\n\n lcore_id = rte_lcore_id();\n\n previous_lcore_id = get_previous_lcore_id(lcore_id);\n\n for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {\n if (!is_bit_set(port_id, portmask))\n continue;\n\n tx = rings[lcore_id][port_id];\n rx = rings[previous_lcore_id][port_id];\n if (ring_state[port_id] != RING_READY) {\n if (rte_ring_count(tx) > *low_watermark)\n continue;\n else\n ring_state[port_id] = RING_READY;\n }\n\n /* Dequeue up to quota mbuf from rx */\n\n nb_dq_pkts = rte_ring_dequeue_burst(rx, pkts, *quota);\n\n if (unlikely(nb_dq_pkts < 0))\n continue;\n\n /* Enqueue them on tx */\n\n ret = rte_ring_enqueue_bulk(tx, pkts, nb_dq_pkts);\n if (ret == -EDQUOT)\n ring_state[port_id] = RING_OVERLOADED;\n }\n\nThe thread's logic works mostly like receive_stage(),\nexcept that packets are moved from ring to ring instead of port to ring.\n\nIn this example, no actual processing is done on the packets,\nbut pipeline_stage() is an ideal place to perform any processing required by the application.\n\nFinally, the send_stage() function's task is to read packets from the last ring in a pipeline and\nsend them on the destination port defined in the port_pairs[] array.\nIt is running on the last available logical core only.\n\n.. code-block:: c\n\n lcore_id = rte_lcore_id();\n\n previous_lcore_id = get_previous_lcore_id(lcore_id);\n\n for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {\n if (!is_bit_set(port_id, portmask)) continue;\n\n dest_port_id = port_pairs[port_id];\n tx = rings[previous_lcore_id][port_id];\n\n if (rte_ring_empty(tx)) continue;\n\n /* Dequeue packets from tx and send them */\n\n nb_dq_pkts = rte_ring_dequeue_burst(tx, (void *) tx_pkts, *quota);\n nb_tx_pkts = rte_eth_tx_burst(dest_port_id, 0, tx_pkts, nb_dq_pkts);\n }\n\nFor each port in the port mask, up to \\*quota packets are pulled from the last ring in its pipeline and\nsent on the destination port paired with the current port.\n\nControl Application - qwctl\n~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe qwctl application uses the rte_cmdline library to provide the user with an interactive command line that\ncan be used to modify and inspect parameters in a running qw application.\nThose parameters are the global quota and low_watermark value as well as each ring's built-in high watermark.\n\nCommand Definitions\n^^^^^^^^^^^^^^^^^^^\n\nThe available commands are defined in commands.c.\n\nIt is advised to use the cmdline sample application user guide as a reference for everything related to the rte_cmdline library.\n\nAccessing Shared Variables\n^^^^^^^^^^^^^^^^^^^^^^^^^^\n\nThe setup_shared_variables() function retrieves the shared variables quota and\nlow_watermark from the rte_memzone previously created by qw.\n\n.. code-block:: c\n\n static void\n setup_shared_variables(void)\n {\n const struct rte_memzone *qw_memzone;\n\n qw_memzone = rte_memzone_lookup(QUOTA_WATERMARK_MEMZONE_NAME);\n if (qw_memzone == NULL)\n rte_exit(EXIT_FAILURE, \"Couldn't find memzone\\n\");\n\n quota = qw_memzone->addr;\n\n low_watermark = (unsigned int *) qw_memzone->addr + sizeof(int);\n }\n" }, { "path": "doc/guides/sample_app_ug/rxtx_callbacks.rst", "content": ".. BSD LICENSE\n Copyright(c) 2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nRX/TX Callbacks Sample Application\n==================================\n\nThe RX/TX Callbacks sample application is a packet forwarding application that\ndemonstrates the use of user defined callbacks on received and transmitted\npackets. The application performs a simple latency check, using callbacks, to\ndetermine the time packets spend within the application.\n\nIn the sample application a user defined callback is applied to all received\npackets to add a timestamp. A separate callback is applied to all packets\nprior to transmission to calculate the elapsed time, in CPU cycles.\n\n\nCompiling the Application\n-------------------------\n\nTo compile the application export the path to the DPDK source tree and go to\nthe example directory:\n\n.. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n\n cd ${RTE_SDK}/examples/rxtx_callbacks\n\n\nSet the target, for example:\n\n.. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\nSee the *DPDK Getting Started* Guide for possible ``RTE_TARGET`` values.\n\nThe callbacks feature requires that the ``CONFIG_RTE_ETHDEV_RXTX_CALLBACKS``\nsetting is on in the ``config/common_`` config file that applies to the\ntarget. This is generally on by default:\n\n.. code-block:: console\n\n CONFIG_RTE_ETHDEV_RXTX_CALLBACKS=y\n\nBuild the application as follows:\n\n.. code-block:: console\n\n make\n\n\nRunning the Application\n-----------------------\n\nTo run the example in a ``linuxapp`` environment:\n\n.. code-block:: console\n\n ./build/rxtx_callbacks -c 2 -n 4\n\nRefer to *DPDK Getting Started Guide* for general information on running\napplications and the Environment Abstraction Layer (EAL) options.\n\n\n\nExplanation\n-----------\n\nThe ``rxtx_callbacks`` application is mainly a simple forwarding application\nbased on the :doc:`skeleton`. See that section of the documentation for more\ndetails of the forwarding part of the application.\n\nThe sections below explain the additional RX/TX callback code.\n\n\nThe Main Function\n~~~~~~~~~~~~~~~~~\n\nThe ``main()`` function performs the application initialization and calls the\nexecution threads for each lcore. This function is effectively identical to\nthe ``main()`` function explained in :doc:`skeleton`.\n\nThe ``lcore_main()`` function is also identical.\n\nThe main difference is in the user defined ``port_init()`` function where the\ncallbacks are added. This is explained in the next section:\n\n\nThe Port Initialization Function\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe main functional part of the port initialization is shown below with\ncomments:\n\n.. code-block:: c\n\n static inline int\n port_init(uint8_t port, struct rte_mempool *mbuf_pool)\n {\n struct rte_eth_conf port_conf = port_conf_default;\n const uint16_t rx_rings = 1, tx_rings = 1;\n struct ether_addr addr;\n int retval;\n uint16_t q;\n\n if (port >= rte_eth_dev_count())\n return -1;\n\n /* Configure the Ethernet device. */\n retval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);\n if (retval != 0)\n return retval;\n\n /* Allocate and set up 1 RX queue per Ethernet port. */\n for (q = 0; q < rx_rings; q++) {\n retval = rte_eth_rx_queue_setup(port, q, RX_RING_SIZE,\n rte_eth_dev_socket_id(port), NULL, mbuf_pool);\n if (retval < 0)\n return retval;\n }\n\n /* Allocate and set up 1 TX queue per Ethernet port. */\n for (q = 0; q < tx_rings; q++) {\n retval = rte_eth_tx_queue_setup(port, q, TX_RING_SIZE,\n rte_eth_dev_socket_id(port), NULL);\n if (retval < 0)\n return retval;\n }\n\n /* Start the Ethernet port. */\n retval = rte_eth_dev_start(port);\n if (retval < 0)\n return retval;\n\n /* Enable RX in promiscuous mode for the Ethernet device. */\n rte_eth_promiscuous_enable(port);\n\n\n /* Add the callbacks for RX and TX.*/\n rte_eth_add_rx_callback(port, 0, add_timestamps, NULL);\n rte_eth_add_tx_callback(port, 0, calc_latency, NULL);\n\n return 0;\n }\n\n\nThe RX and TX callbacks are added to the ports/queues as function pointers:\n\n.. code-block:: c\n\n rte_eth_add_rx_callback(port, 0, add_timestamps, NULL);\n rte_eth_add_tx_callback(port, 0, calc_latency, NULL);\n\nMore than one callback can be added and additional information can be passed\nto callback function pointers as a ``void*``. In the examples above ``NULL``\nis used.\n\nThe ``add_timestamps()`` and ``calc_latency()`` functions are explained below.\n\n\nThe add_timestamps() Callback\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe ``add_timestamps()`` callback is added to the RX port and is applied to\nall packets received:\n\n.. code-block:: c\n\n static uint16_t\n add_timestamps(uint8_t port __rte_unused, uint16_t qidx __rte_unused,\n struct rte_mbuf **pkts, uint16_t nb_pkts, void *_ __rte_unused)\n {\n unsigned i;\n uint64_t now = rte_rdtsc();\n\n for (i = 0; i < nb_pkts; i++)\n pkts[i]->udata64 = now;\n\n return nb_pkts;\n }\n\nThe DPDK function ``rte_rdtsc()`` is used to add a cycle count timestamp to\neach packet (see the *cycles* section of the *DPDK API Documentation* for\ndetails).\n\n\nThe calc_latency() Callback\n~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe ``calc_latency()`` callback is added to the TX port and is applied to all\npackets prior to transmission:\n\n.. code-block:: c\n\n static uint16_t\n calc_latency(uint8_t port __rte_unused, uint16_t qidx __rte_unused,\n struct rte_mbuf **pkts, uint16_t nb_pkts, void *_ __rte_unused)\n {\n uint64_t cycles = 0;\n uint64_t now = rte_rdtsc();\n unsigned i;\n\n for (i = 0; i < nb_pkts; i++)\n cycles += now - pkts[i]->udata64;\n\n latency_numbers.total_cycles += cycles;\n latency_numbers.total_pkts += nb_pkts;\n\n if (latency_numbers.total_pkts > (100 * 1000 * 1000ULL)) {\n printf(\"Latency = %\"PRIu64\" cycles\\n\",\n latency_numbers.total_cycles / latency_numbers.total_pkts);\n\n latency_numbers.total_cycles = latency_numbers.total_pkts = 0;\n }\n\n return nb_pkts;\n }\n\nThe ``calc_latency()`` function accumulates the total number of packets and\nthe total number of cycles used. Once more than 100 million packets have been\ntransmitted the average cycle count per packet is printed out and the counters\nare reset.\n" }, { "path": "doc/guides/sample_app_ug/skeleton.rst", "content": ".. BSD LICENSE\n Copyright(c) 2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nBasic Forwarding Sample Application\n===================================\n\nThe Basic Forwarding sample application is a simple *skeleton* example of a\nforwarding application.\n\nIt is intended as a demonstration of the basic components of a DPDK forwarding\napplication. For more detailed implementations see the L2 and L3 forwarding\nsample applications.\n\n\nCompiling the Application\n-------------------------\n\nTo compile the application export the path to the DPDK source tree and go to\nthe example directory:\n\n.. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n\n cd ${RTE_SDK}/examples/skeleton\n\nSet the target, for example:\n\n.. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\nSee the *DPDK Getting Started* Guide for possible ``RTE_TARGET`` values.\n\nBuild the application as follows:\n\n.. code-block:: console\n\n make\n\n\nRunning the Application\n-----------------------\n\nTo run the example in a ``linuxapp`` environment:\n\n.. code-block:: console\n\n ./build/basicfwd -c 2 -n 4\n\nRefer to *DPDK Getting Started Guide* for general information on running\napplications and the Environment Abstraction Layer (EAL) options.\n\n\nExplanation\n-----------\n\nThe following sections provide an explanation of the main components of the\ncode.\n\nAll DPDK library functions used in the sample code are prefixed with ``rte_``\nand are explained in detail in the *DPDK API Documentation*.\n\n\nThe Main Function\n~~~~~~~~~~~~~~~~~\n\nThe ``main()`` function performs the initialization and calls the execution\nthreads for each lcore.\n\nThe first task is to initialize the Environment Abstraction Layer (EAL). The\n``argc`` and ``argv`` arguments are provided to the ``rte_eal_init()``\nfunction. The value returned is the number of parsed arguments:\n\n.. code-block:: c\n\n int ret = rte_eal_init(argc, argv);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Error with EAL initialization\\n\");\n\n\nThe ``main()`` also allocates a mempool to hold the mbufs (Message Buffers)\nused by the application:\n\n.. code-block:: c\n\n mbuf_pool = rte_mempool_create(\"MBUF_POOL\",\n NUM_MBUFS * nb_ports,\n MBUF_SIZE,\n MBUF_CACHE_SIZE,\n sizeof(struct rte_pktmbuf_pool_private),\n rte_pktmbuf_pool_init, NULL,\n rte_pktmbuf_init, NULL,\n rte_socket_id(),\n 0);\n\nMbufs are the packet buffer structure used by DPDK. They are explained in\ndetail in the \"Mbuf Library\" section of the *DPDK Programmer's Guide*.\n\nThe ``main()`` function also initializes all the ports using the user defined\n``port_init()`` function which is explained in the next section:\n\n.. code-block:: c\n\n for (portid = 0; portid < nb_ports; portid++) {\n if (port_init(portid, mbuf_pool) != 0) {\n rte_exit(EXIT_FAILURE,\n \"Cannot init port %\" PRIu8 \"\\n\", portid);\n }\n }\n\n\nOnce the initialization is complete, the application is ready to launch a\nfunction on an lcore. In this example ``lcore_main()`` is called on a single\nlcore.\n\n\n.. code-block:: c\n\n\tlcore_main();\n\nThe ``lcore_main()`` function is explained below.\n\n\n\nThe Port Initialization Function\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe main functional part of the port initialization used in the Basic\nForwarding application is shown below:\n\n.. code-block:: c\n\n static inline int\n port_init(uint8_t port, struct rte_mempool *mbuf_pool)\n {\n struct rte_eth_conf port_conf = port_conf_default;\n const uint16_t rx_rings = 1, tx_rings = 1;\n struct ether_addr addr;\n int retval;\n uint16_t q;\n\n if (port >= rte_eth_dev_count())\n return -1;\n\n /* Configure the Ethernet device. */\n retval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);\n if (retval != 0)\n return retval;\n\n /* Allocate and set up 1 RX queue per Ethernet port. */\n for (q = 0; q < rx_rings; q++) {\n retval = rte_eth_rx_queue_setup(port, q, RX_RING_SIZE,\n rte_eth_dev_socket_id(port), NULL, mbuf_pool);\n if (retval < 0)\n return retval;\n }\n\n /* Allocate and set up 1 TX queue per Ethernet port. */\n for (q = 0; q < tx_rings; q++) {\n retval = rte_eth_tx_queue_setup(port, q, TX_RING_SIZE,\n rte_eth_dev_socket_id(port), NULL);\n if (retval < 0)\n return retval;\n }\n\n /* Start the Ethernet port. */\n retval = rte_eth_dev_start(port);\n if (retval < 0)\n return retval;\n\n /* Enable RX in promiscuous mode for the Ethernet device. */\n rte_eth_promiscuous_enable(port);\n\n return 0;\n }\n\nThe Ethernet ports are configured with default settings using the\n``rte_eth_dev_configure()`` function and the ``port_conf_default`` struct:\n\n.. code-block:: c\n\n static const struct rte_eth_conf port_conf_default = {\n .rxmode = { .max_rx_pkt_len = ETHER_MAX_LEN }\n };\n\nFor this example the ports are set up with 1 RX and 1 TX queue using the\n``rte_eth_rx_queue_setup()`` and ``rte_eth_tx_queue_setup()`` functions.\n\nThe Ethernet port is then started:\n\n.. code-block:: c\n\n retval = rte_eth_dev_start(port);\n\n\nFinally the RX port is set in promiscuous mode:\n\n.. code-block:: c\n\n rte_eth_promiscuous_enable(port);\n\n\nThe Lcores Main\n~~~~~~~~~~~~~~~\n\nAs we saw above the ``main()`` function calls an application function on the\navailable lcores. For the Basic Forwarding application the lcore function\nlooks like the following:\n\n.. code-block:: c\n\n static __attribute__((noreturn)) void\n lcore_main(void)\n {\n const uint8_t nb_ports = rte_eth_dev_count();\n uint8_t port;\n\n /*\n * Check that the port is on the same NUMA node as the polling thread\n * for best performance.\n */\n for (port = 0; port < nb_ports; port++)\n if (rte_eth_dev_socket_id(port) > 0 &&\n rte_eth_dev_socket_id(port) !=\n (int)rte_socket_id())\n printf(\"WARNING, port %u is on remote NUMA node to \"\n \"polling thread.\\n\\tPerformance will \"\n \"not be optimal.\\n\", port);\n\n printf(\"\\nCore %u forwarding packets. [Ctrl+C to quit]\\n\",\n rte_lcore_id());\n\n /* Run until the application is quit or killed. */\n for (;;) {\n /*\n * Receive packets on a port and forward them on the paired\n * port. The mapping is 0 -> 1, 1 -> 0, 2 -> 3, 3 -> 2, etc.\n */\n for (port = 0; port < nb_ports; port++) {\n\n /* Get burst of RX packets, from first port of pair. */\n struct rte_mbuf *bufs[BURST_SIZE];\n const uint16_t nb_rx = rte_eth_rx_burst(port, 0,\n bufs, BURST_SIZE);\n\n if (unlikely(nb_rx == 0))\n continue;\n\n /* Send burst of TX packets, to second port of pair. */\n const uint16_t nb_tx = rte_eth_tx_burst(port ^ 1, 0,\n bufs, nb_rx);\n\n /* Free any unsent packets. */\n if (unlikely(nb_tx < nb_rx)) {\n uint16_t buf;\n for (buf = nb_tx; buf < nb_rx; buf++)\n rte_pktmbuf_free(bufs[buf]);\n }\n }\n }\n }\n\n\nThe main work of the application is done within the loop:\n\n.. code-block:: c\n\n for (;;) {\n for (port = 0; port < nb_ports; port++) {\n\n /* Get burst of RX packets, from first port of pair. */\n struct rte_mbuf *bufs[BURST_SIZE];\n const uint16_t nb_rx = rte_eth_rx_burst(port, 0,\n bufs, BURST_SIZE);\n\n if (unlikely(nb_rx == 0))\n continue;\n\n /* Send burst of TX packets, to second port of pair. */\n const uint16_t nb_tx = rte_eth_tx_burst(port ^ 1, 0,\n bufs, nb_rx);\n\n /* Free any unsent packets. */\n if (unlikely(nb_tx < nb_rx)) {\n uint16_t buf;\n for (buf = nb_tx; buf < nb_rx; buf++)\n rte_pktmbuf_free(bufs[buf]);\n }\n }\n }\n\nPackets are received in bursts on the RX ports and transmitted in bursts on\nthe TX ports. The ports are grouped in pairs with a simple mapping scheme\nusing the an XOR on the port number::\n\n 0 -> 1\n 1 -> 0\n\n 2 -> 3\n 3 -> 2\n\n etc.\n\nThe ``rte_eth_tx_burst()`` function frees the memory buffers of packets that\nare transmitted. If packets fail to transmit, ``(nb_tx < nb_rx)``, then they\nmust be freed explicitly using ``rte_pktmbuf_free()``.\n\nThe forwarding loop can be interrupted and the application closed using\n``Ctrl-C``.\n" }, { "path": "doc/guides/sample_app_ug/tep_termination.rst", "content": "\n.. BSD LICENSE\n Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nTEP termination Sample Application\n==================================\n\nThe TEP (Tunnel End point) termination sample application simulates a VXLAN\nTunnel Endpoint (VTEP) termination in DPDK, which is used to demonstrate\nthe offload and filtering capabilities of Intel® XL710 10/40 Gigabit Ethernet\nController for VXLAN packet.\nThis sample uses the basic virtio devices management mechanism from vhost example,\nand also uses the us-vHost interface and tunnel filtering mechanism to direct\na specified traffic to a specific VM.\nIn addition, this sample is also designed to show how tunneling protocols can be handled.\n\nBackground\n----------\n\nWith virtualization, overlay networks allow a network structure to be built\nor imposed across physical nodes which is abstracted away from the actual\nunderlining physical network connections.\nThis allows network isolation, QOS, etc to be provided on a per client basis.\n\n.. _figure_overlay_networking:\n\n.. figure:: img/overlay_networking.*\n\n Overlay Networking.\n\nIn a typical setup, the network overlay tunnel is terminated at the Virtual/Tunnel End Point (VEP/TEP).\nThe TEP is normally located at the physical host level ideally in the software switch.\nDue to processing constraints and the inevitable bottleneck that the switch\nbecomes the ability to offload overlay support features becomes an important requirement.\nIntel® XL710 10/40 G Ethernet network card provides hardware filtering\nand offload capabilities to support overlay networks implementations such as MAC in UDP and MAC in GRE.\n\nSample Code Overview\n--------------------\n\nThe DPDK TEP termination sample code demonstrates the offload and filtering\ncapabilities of Intel® XL710 10/40 Gigabit Ethernet Controller for VXLAN packet.\n\nThe sample code is based on vhost library.\nThe vhost library is developed for user space Ethernet switch to easily integrate with vhost functionality.\n\nThe sample will support the followings:\n\n* Tunneling packet recognition.\n\n* The port of UDP tunneling is configurable\n\n* Directing incoming traffic to the correct queue based on the tunnel filter type.\n The supported filter type are listed below.\n\n * Inner MAC and VLAN and tenant ID\n\n * Inner MAC and tenant ID, and Outer MAC\n\n * Inner MAC and tenant ID\n\n The tenant ID will be assigned from a static internal table based on the us-vhost device ID.\n Each device will receive a unique device ID.\n The inner MAC will be learned by the first packet transmitted from a device.\n\n* Decapsulation of RX VXLAN traffic. This is a software only operation.\n\n* Encapsulation of TX VXLAN traffic. This is a software only operation.\n\n* Inner IP and inner L4 checksum offload.\n\n* TSO offload support for tunneling packet.\n\nThe following figure shows the framework of the TEP termination sample application based on vhost-cuse.\n\n.. _figure_tep_termination_arch:\n\n.. figure:: img/tep_termination_arch.*\n\n TEP termination Framework Overview\n\nSupported Distributions\n-----------------------\n\nThe example in this section have been validated with the following distributions:\n\n* Fedora* 18\n\n* Fedora* 19\n\n* Fedora* 20\n\nPrerequisites\n-------------\n\nRefer to the guide in section 27.4 in the vhost sample.\n\nCompiling the Sample Code\n-------------------------\n#. Compile vhost lib:\n\n To enable vhost, turn on vhost library in the configure file config/common_linuxapp.\n\n .. code-block:: console\n\n CONFIG_RTE_LIBRTE_VHOST=n\n\n vhost user is turned on by default in the configure file config/common_linuxapp.\n To enable vhost cuse, disable vhost user.\n\n .. code-block:: console\n\n CONFIG_RTE_LIBRTE_VHOST_USER=y\n\n After vhost is enabled and the implementation is selected, build the vhost library.\n\n#. Go to the examples directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/tep_termination\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the DPDK Getting Started Guide for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n cd ${RTE_SDK}\n make config ${RTE_TARGET}\n make install ${RTE_TARGET}\n cd ${RTE_SDK}/examples/tep_termination\n make\n\n#. Go to the eventfd_link directory(vhost cuse required):\n\n .. code-block:: console\n\n cd ${RTE_SDK}/lib/librte_vhost/eventfd_link\n\n#. Build the eventfd_link kernel module(vhost cuse required):\n\n .. code-block:: console\n\n make\n\nRunning the Sample Code\n-----------------------\n\n#. Install the cuse kernel module(vhost cuse required):\n\n .. code-block:: console\n\n modprobe cuse\n\n#. Go to the eventfd_link directory(vhost cuse required):\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/lib/librte_vhost/eventfd_link\n\n#. Install the eventfd_link module(vhost cuse required):\n\n .. code-block:: console\n\n insmod ./eventfd_link.ko\n\n#. Go to the examples directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/tep_termination\n\n#. Run the tep_termination sample code:\n\n .. code-block:: console\n\n user@target:~$ ./build/app/tep_termination -c f -n 4 --huge-dir /mnt/huge --\n -p 0x1 --dev-basename tep-termination --nb-devices 4\n --udp-port 4789 --filter-type 1\n\n.. note::\n\n Please note the huge-dir parameter instructs the DPDK to allocate its memory from the 2 MB page hugetlbfs.\n\nParameters\n~~~~~~~~~~\n\n**The same parameters with the vhost sample.**\n\nRefer to the guide in section 27.6.1 in the vhost sample for the meanings of 'Basename',\n'Stats', 'RX Retry', 'RX Retry Number' and 'RX Retry Delay Time'.\n\n**Number of Devices.**\n\nThe nb-devices option specifies the number of virtIO device.\nThe default value is 2.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/tep_termination -c f -n 4 --huge-dir /mnt/huge --\n --nb-devices 2\n\n**Tunneling UDP port.**\n\nThe udp-port option is used to specify the destination UDP number for UDP tunneling packet.\nThe default value is 4789.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/tep_termination -c f -n 4 --huge-dir /mnt/huge --\n --nb-devices 2 --udp-port 4789\n\n**Filter Type.**\n\nThe filter-type option is used to specify which filter type is used to\nfilter UDP tunneling packet to a specified queue.\nThe default value is 1, which means the filter type of inner MAC and tenant ID is used.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/tep_termination -c f -n 4 --huge-dir /mnt/huge --\n --nb-devices 2 --udp-port 4789 --filter-type 1\n\n**TX Checksum.**\n\nThe tx-checksum option is used to enable or disable the inner header checksum offload.\nThe default value is 0, which means the checksum offload is disabled.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/tep_termination -c f -n 4 --huge-dir /mnt/huge --\n --nb-devices 2 --tx-checksum\n\n**TCP segment sise.**\n\nThe tso-segsz option specifies the TCP segment size for TSO offload for tunneling packet.\nThe default value is 0, which means TSO offload is disabled.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/tep_termination -c f -n 4 --huge-dir /mnt/huge --\n --tx-checksum --tso-segsz 800\n\n**Decapsulation option.**\n\nThe decap option is used to enable or disable decapsulation operation for received VXLAN packet.\nThe default value is 1.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/tep_termination -c f -n 4 --huge-dir /mnt/huge --\n --nb-devices 4 --udp-port 4789 --decap 1\n\n**Encapsulation option.**\n\nThe encap option is used to enable or disable encapsulation operation for transmitted packet.\nThe default value is 1.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/tep_termination -c f -n 4 --huge-dir /mnt/huge --\n --nb-devices 4 --udp-port 4789 --encap 1\n\n\nRunning the Virtual Machine (QEMU)\n----------------------------------\n\nRefer to the guide in section 27.7 in the vhost sample.\n\nRunning DPDK in the Virtual Machine\n-----------------------------------\n\nRefer to the guide in section 27.8 in the vHost sample.\n\nPassing Traffic to the Virtual Machine Device\n---------------------------------------------\n\nFor a virtio-net device to receive traffic, the traffic's Layer 2 header must include\nboth the virtio-net device's MAC address.\nThe DPDK sample code behaves in a similar manner to a learning switch in that\nit learns the MAC address of the virtio-net devices from the first transmitted packet.\nOn learning the MAC address,\nthe DPDK vhost sample code prints a message with the MAC address and tenant ID virtio-net device.\nFor example:\n\n.. code-block:: console\n\n DATA: (0) MAC_ADDRESS cc:bb:bb:bb:bb:bb and VNI 1000 registered\n\nThe above message indicates that device 0 has been registered with MAC address cc:bb:bb:bb:bb:bb and VNI 1000.\nAny packets received on the NIC with these values are placed on the devices receive queue.\n" }, { "path": "doc/guides/sample_app_ug/test_pipeline.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nTest Pipeline Application\n=========================\n\nThe Test Pipeline application illustrates the use of the DPDK Packet Framework tool suite.\nIts purpose is to demonstrate the performance of single-table DPDK pipelines.\n\nOverview\n--------\n\nThe application uses three CPU cores:\n\n* Core A (\"RX core\") receives traffic from the NIC ports and feeds core B with traffic through SW queues.\n\n* Core B (\"Pipeline core\") implements a single-table DPDK pipeline\n whose type is selectable through specific command line parameter.\n Core B receives traffic from core A through software queues,\n processes it according to the actions configured in the table entries that\n are hit by the input packets and feeds it to core C through another set of software queues.\n\n* Core C (\"TX core\") receives traffic from core B through software queues and sends it to the NIC ports for transmission.\n\n.. _figure_test_pipeline_app:\n\n.. figure:: img/test_pipeline_app.*\n\n Test Pipeline Application\n\n\nCompiling the Application\n-------------------------\n\n#. Go to the app/test directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/app/test/test-pipeline\n\n#. Set the target (a default target is used if not specified):\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nApplication Command Line\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe application execution command line is:\n\n.. code-block:: console\n\n ./test-pipeline [EAL options] -- -p PORTMASK --TABLE_TYPE\n\nThe -c EAL CPU core mask option has to contain exactly 3 CPU cores.\nThe first CPU core in the core mask is assigned for core A, the second for core B and the third for core C.\n\nThe PORTMASK parameter must contain 2 or 4 ports.\n\nTable Types and Behavior\n~~~~~~~~~~~~~~~~~~~~~~~~\n\n:numref:`table_test_pipeline_1` describes the table types used and how they are populated.\n\nThe hash tables are pre-populated with 16 million keys.\nFor hash tables, the following parameters can be selected:\n\n* **Configurable key size implementation or fixed (specialized) key size implementation (e.g. hash-8-ext or hash-spec-8-ext).**\n The key size specialized implementations are expected to provide better performance for 8-byte and 16-byte key sizes,\n while the key-size-non-specialized implementation is expected to provide better performance for larger key sizes;\n\n* **Key size (e.g. hash-spec-8-ext or hash-spec-16-ext).**\n The available options are 8, 16 and 32 bytes;\n\n* **Table type (e.g. hash-spec-16-ext or hash-spec-16-lru).**\n The available options are ext (extendable bucket) or lru (least recently used).\n\n.. _table_test_pipeline_1:\n\n.. table:: Table Types\n\n +-------+------------------------+----------------------------------------------------------+-------------------------------------------------------+\n | **#** | **TABLE_TYPE** | **Description of Core B Table** | **Pre-added Table Entries** |\n | | | | |\n +=======+========================+==========================================================+=======================================================+\n | 1 | none | Core B is not implementing a DPDK pipeline. | N/A |\n | | | Core B is implementing a pass-through from its input set | |\n | | | of software queues to its output set of software queues. | |\n | | | | |\n +-------+------------------------+----------------------------------------------------------+-------------------------------------------------------+\n | 2 | stub | Stub table. Core B is implementing the same pass-through | N/A |\n | | | functionality as described for the \"none\" option by | |\n | | | using the DPDK Packet Framework by using one | |\n | | | stub table for each input NIC port. | |\n | | | | |\n +-------+------------------------+----------------------------------------------------------+-------------------------------------------------------+\n | 3 | hash-[spec]-8-lru | LRU hash table with 8-byte key size and 16 million | 16 million entries are successfully added to the |\n | | | entries. | hash table with the following key format: |\n | | | | |\n | | | | [4-byte index, 4 bytes of 0] |\n | | | | |\n | | | | The action configured for all table entries is |\n | | | | \"Sendto output port\", with the output port index |\n | | | | uniformly distributed for the range of output ports. |\n | | | | |\n | | | | The default table rule (used in the case of a lookup |\n | | | | miss) is to drop the packet. |\n | | | | |\n | | | | At run time, core A is creating the following lookup |\n | | | | key and storing it into the packet meta data for |\n | | | | core B to use for table lookup: |\n | | | | |\n | | | | [destination IPv4 address, 4 bytes of 0] |\n | | | | |\n +-------+------------------------+----------------------------------------------------------+-------------------------------------------------------+\n | 4 | hash-[spec]-8-ext | Extendible bucket hash table with 8-byte key size | Same as hash-[spec]-8-lru table entries, above. |\n | | | and 16 million entries. | |\n | | | | |\n +-------+------------------------+----------------------------------------------------------+-------------------------------------------------------+\n | 5 | hash-[spec]-16-lru | LRU hash table with 16-byte key size and 16 million | 16 million entries are successfully added to the hash |\n | | | entries. | table with the following key format: |\n | | | | |\n | | | | [4-byte index, 12 bytes of 0] |\n | | | | |\n | | | | The action configured for all table entries is |\n | | | | \"Send to output port\", with the output port index |\n | | | | uniformly distributed for the range of output ports. |\n | | | | |\n | | | | The default table rule (used in the case of a lookup |\n | | | | miss) is to drop the packet. |\n | | | | |\n | | | | At run time, core A is creating the following lookup |\n | | | | key and storing it into the packet meta data for core |\n | | | | B to use for table lookup: |\n | | | | |\n | | | | [destination IPv4 address, 12 bytes of 0] |\n | | | | |\n +-------+------------------------+----------------------------------------------------------+-------------------------------------------------------+\n | 6 | hash-[spec]-16-ext | Extendible bucket hash table with 16-byte key size | Same as hash-[spec]-16-lru table entries, above. |\n | | | and 16 million entries. | |\n | | | | |\n +-------+------------------------+----------------------------------------------------------+-------------------------------------------------------+\n | 7 | hash-[spec]-32-lru | LRU hash table with 32-byte key size and 16 million | 16 million entries are successfully added to the hash |\n | | | entries. | table with the following key format: |\n | | | | |\n | | | | [4-byte index, 28 bytes of 0]. |\n | | | | |\n | | | | The action configured for all table entries is |\n | | | | \"Send to output port\", with the output port index |\n | | | | uniformly distributed for the range of output ports. |\n | | | | |\n | | | | The default table rule (used in the case of a lookup |\n | | | | miss) is to drop the packet. |\n | | | | |\n | | | | At run time, core A is creating the following lookup |\n | | | | key and storing it into the packet meta data for |\n | | | | Lpmcore B to use for table lookup: |\n | | | | |\n | | | | [destination IPv4 address, 28 bytes of 0] |\n | | | | |\n +-------+------------------------+----------------------------------------------------------+-------------------------------------------------------+\n | 8 | hash-[spec]-32-ext | Extendible bucket hash table with 32-byte key size | Same as hash-[spec]-32-lru table entries, above. |\n | | | and 16 million entries. | |\n | | | | |\n +-------+------------------------+----------------------------------------------------------+-------------------------------------------------------+\n | 9 | lpm | Longest Prefix Match (LPM) IPv4 table. | In the case of two ports, two routes |\n | | | | are added to the table: |\n | | | | |\n | | | | [0.0.0.0/9 => send to output port 0] |\n | | | | |\n | | | | [0.128.0.0/9 => send to output port 1] |\n | | | | |\n | | | | In case of four ports, four entries are added to the |\n | | | | table: |\n | | | | |\n | | | | [0.0.0.0/10 => send to output port 0] |\n | | | | |\n | | | | [0.64.0.0/10 => send to output port 1] |\n | | | | |\n | | | | [0.128.0.0/10 => send to output port 2] |\n | | | | |\n | | | | [0.192.0.0/10 => send to output port 3] |\n | | | | |\n | | | | The default table rule (used in the case of a lookup |\n | | | | miss) is to drop the packet. |\n | | | | |\n | | | | At run time, core A is storing the IPv4 destination |\n | | | | within the packet meta data to be later used by core |\n | | | | B as the lookup key. |\n | | | | |\n +-------+------------------------+----------------------------------------------------------+-------------------------------------------------------+\n | 10 | acl | Access Control List (ACL) table | In the case of two ports, two ACL rules are added to |\n | | | | the table: |\n | | | | |\n | | | | [priority = 0 (highest), |\n | | | | |\n | | | | IPv4 source = ANY, |\n | | | | |\n | | | | IPv4 destination = 0.0.0.0/9, |\n | | | | |\n | | | | L4 protocol = ANY, |\n | | | | |\n | | | | TCP source port = ANY, |\n | | | | |\n | | | | TCP destination port = ANY |\n | | | | |\n | | | | => send to output port 0] |\n | | | | |\n | | | | |\n | | | | [priority = 0 (highest), |\n | | | | |\n | | | | IPv4 source = ANY, |\n | | | | |\n | | | | IPv4 destination = 0.128.0.0/9, |\n | | | | |\n | | | | L4 protocol = ANY, |\n | | | | |\n | | | | TCP source port = ANY, |\n | | | | |\n | | | | TCP destination port = ANY |\n | | | | |\n | | | | => send to output port 0]. |\n | | | | |\n | | | | |\n | | | | The default table rule (used in the case of a lookup |\n | | | | miss) is to drop the packet. |\n | | | | |\n +-------+------------------------+----------------------------------------------------------+-------------------------------------------------------+\n\nInput Traffic\n~~~~~~~~~~~~~\n\nRegardless of the table type used for the core B pipeline,\nthe same input traffic can be used to hit all table entries with uniform distribution,\nwhich results in uniform distribution of packets sent out on the set of output NIC ports.\nThe profile for input traffic is TCP/IPv4 packets with:\n\n* destination IP address as A.B.C.D with A fixed to 0 and B, C,D random\n\n* source IP address fixed to 0.0.0.0\n\n* destination TCP port fixed to 0\n\n* source TCP port fixed to 0\n" }, { "path": "doc/guides/sample_app_ug/timer.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nTimer Sample Application\n========================\n\nThe Timer sample application is a simple application that demonstrates the use of a timer in a DPDK application.\nThis application prints some messages from different lcores regularly, demonstrating the use of timers.\n\nCompiling the Application\n-------------------------\n\n#. Go to the example directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk cd ${RTE_SDK}/examples/timer\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the *DPDK Getting Started Guide* for possible *RTE_TARGET* values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nTo run the example in linuxapp environment:\n\n.. code-block:: console\n\n $ ./build/timer -c f -n 4\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications and\nthe Environment Abstraction Layer (EAL) options.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of the code.\n\nInitialization and Main Loop\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nIn addition to EAL initialization, the timer subsystem must be initialized, by calling the rte_timer_subsystem_init() function.\n\n.. code-block:: c\n\n /* init EAL */\n\n ret = rte_eal_init(argc, argv);\n if (ret < 0)\n rte_panic(\"Cannot init EAL\\n\");\n\n /* init RTE timer library */\n\n rte_timer_subsystem_init();\n\nAfter timer creation (see the next paragraph),\nthe main loop is executed on each slave lcore using the well-known rte_eal_remote_launch() and also on the master.\n\n.. code-block:: c\n\n /* call lcore_mainloop() on every slave lcore */\n\n RTE_LCORE_FOREACH_SLAVE(lcore_id) {\n rte_eal_remote_launch(lcore_mainloop, NULL, lcore_id);\n }\n\n /* call it on master lcore too */\n\n (void) lcore_mainloop(NULL);\n\nThe main loop is very simple in this example:\n\n.. code-block:: c\n\n while (1) {\n /*\n * Call the timer handler on each core: as we don't\n * need a very precise timer, so only call\n * rte_timer_manage() every ~10ms (at 2 GHz). In a real\n * application, this will enhance performances as\n * reading the HPET timer is not efficient.\n */\n\n cur_tsc = rte_rdtsc();\n\n diff_tsc = cur_tsc - prev_tsc;\n\n if (diff_tsc > TIMER_RESOLUTION_CYCLES) {\n rte_timer_manage();\n prev_tsc = cur_tsc;\n }\n }\n\nAs explained in the comment, it is better to use the TSC register (as it is a per-lcore register) to check if the\nrte_timer_manage() function must be called or not.\nIn this example, the resolution of the timer is 10 milliseconds.\n\nManaging Timers\n~~~~~~~~~~~~~~~\n\nIn the main() function, the two timers are initialized.\nThis call to rte_timer_init() is necessary before doing any other operation on the timer structure.\n\n.. code-block:: c\n\n /* init timer structures */\n\n rte_timer_init(&timer0);\n rte_timer_init(&timer1);\n\nThen, the two timers are configured:\n\n* The first timer (timer0) is loaded on the master lcore and expires every second.\n Since the PERIODICAL flag is provided, the timer is reloaded automatically by the timer subsystem.\n The callback function is timer0_cb().\n\n* The second timer (timer1) is loaded on the next available lcore every 333 ms.\n The SINGLE flag means that the timer expires only once and must be reloaded manually if required.\n The callback function is timer1_cb().\n\n.. code-block:: c\n\n /* load timer0, every second, on master lcore, reloaded automatically */\n\n hz = rte_get_hpet_hz();\n\n lcore_id = rte_lcore_id();\n\n rte_timer_reset(&timer0, hz, PERIODICAL, lcore_id, timer0_cb, NULL);\n\n /* load timer1, every second/3, on next lcore, reloaded manually */\n\n lcore_id = rte_get_next_lcore(lcore_id, 0, 1);\n\n rte_timer_reset(&timer1, hz/3, SINGLE, lcore_id, timer1_cb, NULL);\n\nThe callback for the first timer (timer0) only displays a message until a global counter reaches 20 (after 20 seconds).\nIn this case, the timer is stopped using the rte_timer_stop() function.\n\n.. code-block:: c\n\n /* timer0 callback */\n\n static void\n timer0_cb( attribute ((unused)) struct rte_timer *tim, __attribute ((unused)) void *arg)\n {\n static unsigned counter = 0;\n\n unsigned lcore_id = rte_lcore_id();\n\n printf(\"%s() on lcore %u\\n\", FUNCTION , lcore_id);\n\n /* this timer is automatically reloaded until we decide to stop it, when counter reaches 20. */\n\n if ((counter ++) == 20)\n rte_timer_stop(tim);\n }\n\nThe callback for the second timer (timer1) displays a message and reloads the timer on the next lcore, using the\nrte_timer_reset() function:\n\n.. code-block:: c\n\n /* timer1 callback */\n\n static void\n timer1_cb( attribute ((unused)) struct rte_timer *tim, _attribute ((unused)) void *arg)\n {\n unsigned lcore_id = rte_lcore_id();\n uint64_t hz;\n\n printf(\"%s() on lcore %u\\\\n\", FUNCTION , lcore_id);\n\n /* reload it on another lcore */\n\n hz = rte_get_hpet_hz();\n\n lcore_id = rte_get_next_lcore(lcore_id, 0, 1);\n\n rte_timer_reset(&timer1, hz/3, SINGLE, lcore_id, timer1_cb, NULL);\n }\n" }, { "path": "doc/guides/sample_app_ug/vhost.rst", "content": "\n.. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nVhost Sample Application\n========================\n\nThe vhost sample application demonstrates integration of the Data Plane Development Kit (DPDK)\nwith the Linux* KVM hypervisor by implementing the vhost-net offload API.\nThe sample application performs simple packet switching between virtual machines based on Media Access Control\n(MAC) address or Virtual Local Area Network (VLAN) tag.\nThe splitting of Ethernet traffic from an external switch is performed in hardware by the Virtual Machine Device Queues\n(VMDQ) and Data Center Bridging (DCB) features of the Intel® 82599 10 Gigabit Ethernet Controller.\n\nBackground\n----------\n\nVirtio networking (virtio-net) was developed as the Linux* KVM para-virtualized method for communicating network packets\nbetween host and guest.\nIt was found that virtio-net performance was poor due to context switching and packet copying between host, guest, and QEMU.\nThe following figure shows the system architecture for a virtio-based networking (virtio-net).\n\n.. _figure_qemu_virtio_net:\n\n.. figure:: img/qemu_virtio_net.*\n\n System Architecture for Virtio-based Networking (virtio-net).\n\n\nThe Linux* Kernel vhost-net module was developed as an offload mechanism for virtio-net.\nThe vhost-net module enables KVM (QEMU) to offload the servicing of virtio-net devices to the vhost-net kernel module,\nreducing the context switching and packet copies in the virtual dataplane.\n\nThis is achieved by QEMU sharing the following information with the vhost-net module through the vhost-net API:\n\n* The layout of the guest memory space, to enable the vhost-net module to translate addresses.\n\n* The locations of virtual queues in QEMU virtual address space,\n to enable the vhost module to read/write directly to and from the virtqueues.\n\n* An event file descriptor (eventfd) configured in KVM to send interrupts to the virtio- net device driver in the guest.\n This enables the vhost-net module to notify (call) the guest.\n\n* An eventfd configured in KVM to be triggered on writes to the virtio-net device's\n Peripheral Component Interconnect (PCI) config space.\n This enables the vhost-net module to receive notifications (kicks) from the guest.\n\nThe following figure shows the system architecture for virtio-net networking with vhost-net offload.\n\n.. _figure_virtio_linux_vhost:\n\n.. figure:: img/virtio_linux_vhost.*\n\n Virtio with Linux\n\n\nSample Code Overview\n--------------------\n\nThe DPDK vhost-net sample code demonstrates KVM (QEMU) offloading the servicing of a Virtual Machine's (VM's)\nvirtio-net devices to a DPDK-based application in place of the kernel's vhost-net module.\n\nThe DPDK vhost-net sample code is based on vhost library. Vhost library is developed for user space Ethernet switch to\neasily integrate with vhost functionality.\n\nThe vhost library implements the following features:\n\n* Management of virtio-net device creation/destruction events.\n\n* Mapping of the VM's physical memory into the DPDK vhost-net's address space.\n\n* Triggering/receiving notifications to/from VMs via eventfds.\n\n* A virtio-net back-end implementation providing a subset of virtio-net features.\n\nThere are two vhost implementations in vhost library, vhost cuse and vhost user. In vhost cuse, a character device driver is implemented to\nreceive and process vhost requests through ioctl messages. In vhost user, a socket server is created to received vhost requests through\nsocket messages. Most of the messages share the same handler routine.\n\n.. note::\n **Any vhost cuse specific requirement in the following sections will be emphasized**.\n\nTwo implementations are turned on and off statically through configure file. Only one implementation could be turned on. They don't co-exist in current implementation.\n\nThe vhost sample code application is a simple packet switching application with the following feature:\n\n* Packet switching between virtio-net devices and the network interface card,\n including using VMDQs to reduce the switching that needs to be performed in software.\n\nThe following figure shows the architecture of the Vhost sample application based on vhost-cuse.\n\n.. _figure_vhost_net_arch:\n\n.. figure:: img/vhost_net_arch.*\n\n Vhost-net Architectural Overview\n\n\nThe following figure shows the flow of packets through the vhost-net sample application.\n\n.. _figure_vhost_net_sample_app:\n\n.. figure:: img/vhost_net_sample_app.*\n\n Packet Flow Through the vhost-net Sample Application\n\n\nSupported Distributions\n-----------------------\n\nThe example in this section have been validated with the following distributions:\n\n* Fedora* 18\n\n* Fedora* 19\n\n* Fedora* 20\n\nPrerequisites\n-------------\n\nThis section lists prerequisite packages that must be installed.\n\nInstalling Packages on the Host(vhost cuse required)\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe vhost cuse code uses the following packages; fuse, fuse-devel, and kernel-modules-extra.\nThe vhost user code don't rely on those modules as eventfds are already installed into vhost process through\nUnix domain socket.\n\n#. Install Fuse Development Libraries and headers:\n\n .. code-block:: console\n\n yum -y install fuse fuse-devel\n\n#. Install the Cuse Kernel Module:\n\n .. code-block:: console\n\n yum -y install kernel-modules-extra\n\nQEMU simulator\n~~~~~~~~~~~~~~\n\nFor vhost user, qemu 2.2 is required.\n\nSetting up the Execution Environment\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nThe vhost sample code requires that QEMU allocates a VM's memory on the hugetlbfs file system.\nAs the vhost sample code requires hugepages,\nthe best practice is to partition the system into separate hugepage mount points for the VMs and the vhost sample code.\n\n.. note::\n\n This is best-practice only and is not mandatory.\n For systems that only support 2 MB page sizes,\n both QEMU and vhost sample code can use the same hugetlbfs mount point without issue.\n\n**QEMU**\n\nVMs with gigabytes of memory can benefit from having QEMU allocate their memory from 1 GB huge pages.\n1 GB huge pages must be allocated at boot time by passing kernel parameters through the grub boot loader.\n\n#. Calculate the maximum memory usage of all VMs to be run on the system.\n Then, round this value up to the nearest Gigabyte the execution environment will require.\n\n#. Edit the /etc/default/grub file, and add the following to the GRUB_CMDLINE_LINUX entry:\n\n .. code-block:: console\n\n GRUB_CMDLINE_LINUX=\"... hugepagesz=1G hugepages= default_hugepagesz=1G\"\n\n#. Update the grub boot loader:\n\n .. code-block:: console\n\n grub2-mkconfig -o /boot/grub2/grub.cfg\n\n#. Reboot the system.\n\n#. The hugetlbfs mount point (/dev/hugepages) should now default to allocating gigabyte pages.\n\n.. note::\n\n Making the above modification will change the system default hugepage size to 1 GB for all applications.\n\n**Vhost Sample Code**\n\nIn this section, we create a second hugetlbs mount point to allocate hugepages for the DPDK vhost sample code.\n\n#. Allocate sufficient 2 MB pages for the DPDK vhost sample code:\n\n .. code-block:: console\n\n echo 256 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages\n\n#. Mount hugetlbs at a separate mount point for 2 MB pages:\n\n .. code-block:: console\n\n mount -t hugetlbfs nodev /mnt/huge -o pagesize=2M\n\nThe above steps can be automated by doing the following:\n\n#. Edit /etc/fstab to add an entry to automatically mount the second hugetlbfs mount point:\n\n ::\n\n hugetlbfs /mnt/huge hugetlbfs defaults,pagesize=1G 0 0\n\n#. Edit the /etc/default/grub file, and add the following to the GRUB_CMDLINE_LINUX entry:\n\n ::\n\n GRUB_CMDLINE_LINUX=\"... hugepagesz=2M hugepages=256 ... default_hugepagesz=1G\"\n\n#. Update the grub bootloader:\n\n .. code-block:: console\n\n grub2-mkconfig -o /boot/grub2/grub.cfg\n\n#. Reboot the system.\n\n.. note::\n\n Ensure that the default hugepage size after this setup is 1 GB.\n\nSetting up the Guest Execution Environment\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nIt is recommended for testing purposes that the DPDK testpmd sample application is used in the guest to forward packets,\nthe reasons for this are discussed in Section 22.7, \"Running the Virtual Machine (QEMU)\".\n\nThe testpmd application forwards packets between pairs of Ethernet devices,\nit requires an even number of Ethernet devices (virtio or otherwise) to execute.\nIt is therefore recommended to create multiples of two virtio-net devices for each Virtual Machine either through libvirt or\nat the command line as follows.\n\n.. note::\n\n Observe that in the example, \"-device\" and \"-netdev\" are repeated for two virtio-net devices.\n\nFor vhost cuse:\n\n.. code-block:: console\n\n user@target:~$ qemu-system-x86_64 ... \\\n -netdev tap,id=hostnet1,vhost=on,vhostfd= \\\n -device virtio-net-pci, netdev=hostnet1,id=net1 \\\n -netdev tap,id=hostnet2,vhost=on,vhostfd= \\\n -device virtio-net-pci, netdev=hostnet2,id=net1\n\nFor vhost user:\n\n.. code-block:: console\n\n user@target:~$ qemu-system-x86_64 ... \\\n -chardev socket,id=char1,path= \\\n -netdev type=vhost-user,id=hostnet1,chardev=char1 \\\n -device virtio-net-pci,netdev=hostnet1,id=net1 \\\n -chardev socket,id=char2,path= \\\n -netdev type=vhost-user,id=hostnet2,chardev=char2 \\\n -device virtio-net-pci,netdev=hostnet2,id=net2\n\nsock_path is the path for the socket file created by vhost.\n\nCompiling the Sample Code\n-------------------------\n#. Compile vhost lib:\n\n To enable vhost, turn on vhost library in the configure file config/common_linuxapp.\n\n .. code-block:: console\n\n CONFIG_RTE_LIBRTE_VHOST=n\n\n vhost user is turned on by default in the configure file config/common_linuxapp.\n To enable vhost cuse, disable vhost user.\n\n .. code-block:: console\n\n CONFIG_RTE_LIBRTE_VHOST_USER=y\n\n After vhost is enabled and the implementation is selected, build the vhost library.\n\n#. Go to the examples directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/vhost\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the DPDK Getting Started Guide for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n cd ${RTE_SDK}\n make config ${RTE_TARGET}\n make install ${RTE_TARGET}\n cd ${RTE_SDK}/examples/vhost\n make\n\n#. Go to the eventfd_link directory(vhost cuse required):\n\n .. code-block:: console\n\n cd ${RTE_SDK}/lib/librte_vhost/eventfd_link\n\n#. Build the eventfd_link kernel module(vhost cuse required):\n\n .. code-block:: console\n\n make\n\nRunning the Sample Code\n-----------------------\n\n#. Install the cuse kernel module(vhost cuse required):\n\n .. code-block:: console\n\n modprobe cuse\n\n#. Go to the eventfd_link directory(vhost cuse required):\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/lib/librte_vhost/eventfd_link\n\n#. Install the eventfd_link module(vhost cuse required):\n\n .. code-block:: console\n\n insmod ./eventfd_link.ko\n\n#. Go to the examples directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd ${RTE_SDK}/examples/vhost\n\n#. Run the vhost-switch sample code:\n\n vhost cuse:\n\n .. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir / mnt/huge -- -p 0x1 --dev-basename usvhost --dev-index 1\n\n vhost user: a socket file named usvhost will be created under current directory. Use its path as the socket path in guest's qemu commandline.\n\n .. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir / mnt/huge -- -p 0x1 --dev-basename usvhost\n\n.. note::\n\n Please note the huge-dir parameter instructs the DPDK to allocate its memory from the 2 MB page hugetlbfs.\n\nParameters\n~~~~~~~~~~\n\n**Basename and Index.**\nvhost cuse uses a Linux* character device to communicate with QEMU.\nThe basename and the index are used to generate the character devices name.\n\n /dev/-\n\nThe index parameter is provided for a situation where multiple instances of the virtual switch is required.\n\nFor compatibility with the QEMU wrapper script, a base name of \"usvhost\" and an index of \"1\" should be used:\n\n.. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir / mnt/huge -- -p 0x1 --dev-basename usvhost --dev-index 1\n\n**vm2vm.**\nThe vm2vm parameter disable/set mode of packet switching between guests in the host.\nValue of \"0\" means disabling vm2vm implies that on virtual machine packet transmission will always go to the Ethernet port;\nValue of \"1\" means software mode packet forwarding between guests, it needs packets copy in vHOST,\nso valid only in one-copy implementation, and invalid for zero copy implementation;\nvalue of \"2\" means hardware mode packet forwarding between guests, it allows packets go to the Ethernet port,\nhardware L2 switch will determine which guest the packet should forward to or need send to external,\nwhich bases on the packet destination MAC address and VLAN tag.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir /mnt/huge -- --vm2vm [0,1,2]\n\n**Mergeable Buffers.**\nThe mergeable buffers parameter controls how virtio-net descriptors are used for virtio-net headers.\nIn a disabled state, one virtio-net header is used per packet buffer;\nin an enabled state one virtio-net header is used for multiple packets.\nThe default value is 0 or disabled since recent kernels virtio-net drivers show performance degradation with this feature is enabled.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir / mnt/huge -- --mergeable [0,1]\n\n**Stats.**\nThe stats parameter controls the printing of virtio-net device statistics.\nThe parameter specifies an interval second to print statistics, with an interval of 0 seconds disabling statistics.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir / mnt/huge -- --stats [0,n]\n\n**RX Retry.**\nThe rx-retry option enables/disables enqueue retries when the guests RX queue is full.\nThis feature resolves a packet loss that is observed at high data-rates,\nby allowing it to delay and retry in the receive path.\nThis option is enabled by default.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir / mnt/huge -- --rx-retry [0,1]\n\n**RX Retry Number.**\nThe rx-retry-num option specifies the number of retries on an RX burst,\nit takes effect only when rx retry is enabled.\nThe default value is 4.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir / mnt/huge -- --rx-retry 1 --rx-retry-num 5\n\n**RX Retry Delay Time.**\nThe rx-retry-delay option specifies the timeout (in micro seconds) between retries on an RX burst,\nit takes effect only when rx retry is enabled.\nThe default value is 15.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir / mnt/huge -- --rx-retry 1 --rx-retry-delay 20\n\n**Zero copy.**\nThe zero copy option enables/disables the zero copy mode for RX/TX packet,\nin the zero copy mode the packet buffer address from guest translate into host physical address\nand then set directly as DMA address.\nIf the zero copy mode is disabled, then one copy mode is utilized in the sample.\nThis option is disabled by default.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir /mnt/huge -- --zero-copy [0,1]\n\n**RX descriptor number.**\nThe RX descriptor number option specify the Ethernet RX descriptor number,\nLinux legacy virtio-net has different behavior in how to use the vring descriptor from DPDK based virtio-net PMD,\nthe former likely allocate half for virtio header, another half for frame buffer,\nwhile the latter allocate all for frame buffer,\nthis lead to different number for available frame buffer in vring,\nand then lead to different Ethernet RX descriptor number could be used in zero copy mode.\nSo it is valid only in zero copy mode is enabled. The value is 32 by default.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir /mnt/huge -- --zero-copy 1 --rx-desc-num [0, n]\n\n**TX descriptor number.**\nThe TX descriptor number option specify the Ethernet TX descriptor number, it is valid only in zero copy mode is enabled.\nThe value is 64 by default.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir /mnt/huge -- --zero-copy 1 --tx-desc-num [0, n]\n\n**VLAN strip.**\nThe VLAN strip option enable/disable the VLAN strip on host, if disabled, the guest will receive the packets with VLAN tag.\nIt is enabled by default.\n\n.. code-block:: console\n\n user@target:~$ ./build/app/vhost-switch -c f -n 4 --huge-dir /mnt/huge -- --vlan-strip [0, 1]\n\nRunning the Virtual Machine (QEMU)\n----------------------------------\n\nQEMU must be executed with specific parameters to:\n\n* Ensure the guest is configured to use virtio-net network adapters.\n\n .. code-block:: console\n\n user@target:~$ qemu-system-x86_64 ... -device virtio-net-pci,netdev=hostnet1,id=net1 ...\n\n* Ensure the guest's virtio-net network adapter is configured with offloads disabled.\n\n .. code-block:: console\n\n user@target:~$ qemu-system-x86_64 ... -device virtio-net-pci,netdev=hostnet1,id=net1,csum=off,gso=off,guest_tso4=off,guest_tso6=off,guest_ecn=off\n\n* Redirect QEMU to communicate with the DPDK vhost-net sample code in place of the vhost-net kernel module(vhost cuse).\n\n .. code-block:: console\n\n user@target:~$ qemu-system-x86_64 ... -netdev tap,id=hostnet1,vhost=on,vhostfd= ...\n\n* Enable the vhost-net sample code to map the VM's memory into its own process address space.\n\n .. code-block:: console\n\n user@target:~$ qemu-system-x86_64 ... -mem-prealloc -mem-path / dev/hugepages ...\n\n.. note::\n\n The QEMU wrapper (qemu-wrap.py) is a Python script designed to automate the QEMU configuration described above.\n It also facilitates integration with libvirt, although the script may also be used standalone without libvirt.\n\nRedirecting QEMU to vhost-net Sample Code(vhost cuse)\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nTo redirect QEMU to the vhost-net sample code implementation of the vhost-net API,\nan open file descriptor must be passed to QEMU running as a child process.\n\n.. code-block:: python\n\n #!/usr/bin/python\n fd = os.open(\"/dev/usvhost-1\", os.O_RDWR)\n subprocess.call(\"qemu-system-x86_64 ... . -netdev tap,id=vhostnet0,vhost=on,vhostfd=\" + fd +\"...\", shell=True)\n\n.. note::\n\n This process is automated in the QEMU wrapper script discussed in Section 24.7.3.\n\nMapping the Virtual Machine's Memory\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nFor the DPDK vhost-net sample code to be run correctly, QEMU must allocate the VM's memory on hugetlbfs.\nThis is done by specifying mem-prealloc and mem-path when executing QEMU.\nThe vhost-net sample code accesses the virtio-net device's virtual rings and packet buffers\nby finding and mapping the VM's physical memory on hugetlbfs.\nIn this case, the path passed to the guest should be that of the 1 GB page hugetlbfs:\n\n.. code-block:: console\n\n user@target:~$ qemu-system-x86_64 ... -mem-prealloc -mem-path / dev/hugepages ...\n\n.. note::\n\n This process is automated in the QEMU wrapper script discussed in Section 24.7.3.\n The following two sections only applies to vhost cuse. For vhost-user, please make corresponding changes to qemu-wrapper script and guest XML file.\n\nQEMU Wrapper Script\n~~~~~~~~~~~~~~~~~~~\n\nThe QEMU wrapper script automatically detects and calls QEMU with the necessary parameters required\nto integrate with the vhost sample code.\nIt performs the following actions:\n\n* Automatically detects the location of the hugetlbfs and inserts this into the command line parameters.\n\n* Automatically open file descriptors for each virtio-net device and inserts this into the command line parameters.\n\n* Disables offloads on each virtio-net device.\n\n* Calls Qemu passing both the command line parameters passed to the script itself and those it has auto-detected.\n\nThe QEMU wrapper script will automatically configure calls to QEMU:\n\n.. code-block:: console\n\n user@target:~$ qemu-wrap.py -machine pc-i440fx-1.4,accel=kvm,usb=off -cpu SandyBridge -smp 4,sockets=4,cores=1,threads=1\n -netdev tap,id=hostnet1,vhost=on -device virtio-net-pci,netdev=hostnet1,id=net1 -hda -m 4096\n\nwhich will become the following call to QEMU:\n\n.. code-block:: console\n\n /usr/local/bin/qemu-system-x86_64 -machine pc-i440fx-1.4,accel=kvm,usb=off -cpu SandyBridge -smp 4,sockets=4,cores=1,threads=1\n -netdev tap,id=hostnet1,vhost=on,vhostfd= -device virtio-net-pci,netdev=hostnet1,id=net1,\n csum=off,gso=off,guest_tso4=off,guest_tso6=off,guest_ecn=off -hda -m 4096 -mem-path /dev/hugepages -mem-prealloc\n\nLibvirt Integration\n~~~~~~~~~~~~~~~~~~~\n\nThe QEMU wrapper script (qemu-wrap.py) \"wraps\" libvirt calls to QEMU,\nsuch that QEMU is called with the correct parameters described above.\nTo call the QEMU wrapper automatically from libvirt, the following configuration changes must be made:\n\n* Place the QEMU wrapper script in libvirt's binary search PATH ($PATH).\n A good location is in the directory that contains the QEMU binary.\n\n* Ensure that the script has the same owner/group and file permissions as the QEMU binary.\n\n* Update the VM xml file using virsh edit :\n\n * Set the VM to use the launch script\n\n * Set the emulator path contained in the # tags For example,\n replace /usr/bin/qemu-kvm with /usr/bin/qemu-wrap.py\n\n * Set the VM's virtio-net device's to use vhost-net offload:\n\n .. code-block:: xml\n\n \n \n \n \n\n * Enable libvirt to access the DPDK Vhost sample code's character device file by adding it\n to controllers cgroup for libvirtd using the following steps:\n\n .. code-block:: xml\n\n cgroup_controllers = [ ... \"devices\", ... ] clear_emulator_capabilities = 0\n user = \"root\" group = \"root\"\n cgroup_device_acl = [\n \"/dev/null\", \"/dev/full\", \"/dev/zero\",\n \"/dev/random\", \"/dev/urandom\",\n \"/dev/ptmx\", \"/dev/kvm\", \"/dev/kqemu\",\n \"/dev/rtc\", \"/dev/hpet\", \"/dev/net/tun\",\n \"/dev/-\",\n ]\n\n* Disable SELinux or set to permissive mode.\n\n\n* Mount cgroup device controller:\n\n .. code-block:: console\n\n user@target:~$ mkdir /dev/cgroup\n user@target:~$ mount -t cgroup none /dev/cgroup -o devices\n\n* Restart the libvirtd system process\n\n For example, on Fedora* \"systemctl restart libvirtd.service\"\n\n* Edit the configuration parameters section of the script:\n\n * Configure the \"emul_path\" variable to point to the QEMU emulator.\n\n .. code-block:: xml\n\n emul_path = \"/usr/local/bin/qemu-system-x86_64\"\n\n * Configure the \"us_vhost_path\" variable to point to the DPDK vhost-net sample code's character devices name.\n DPDK vhost-net sample code's character device will be in the format \"/dev/-\".\n\n .. code-block:: xml\n\n us_vhost_path = \"/dev/usvhost-1\"\n\nCommon Issues\n~~~~~~~~~~~~~\n\n* QEMU failing to allocate memory on hugetlbfs, with an error like the following::\n\n file_ram_alloc: can't mmap RAM pages: Cannot allocate memory\n\n When running QEMU the above error indicates that it has failed to allocate memory for the Virtual Machine on\n the hugetlbfs. This is typically due to insufficient hugepages being free to support the allocation request.\n The number of free hugepages can be checked as follows:\n\n .. code-block:: console\n\n cat /sys/kernel/mm/hugepages/hugepages-/nr_hugepages\n\n The command above indicates how many hugepages are free to support QEMU's allocation request.\n\n* User space VHOST when the guest has 2MB sized huge pages:\n\n The guest may have 2MB or 1GB sized huge pages. The user space VHOST should work properly in both cases.\n\n* User space VHOST will not work with QEMU without the ``-mem-prealloc`` option:\n\n The current implementation works properly only when the guest memory is pre-allocated, so it is required to\n use a QEMU version (e.g. 1.6) which supports ``-mem-prealloc``. The ``-mem-prealloc`` option must be\n specified explicitly in the QEMU command line.\n\n* User space VHOST will not work with a QEMU version without shared memory mapping:\n\n As shared memory mapping is mandatory for user space VHOST to work properly with the guest, user space VHOST\n needs access to the shared memory from the guest to receive and transmit packets. It is important to make sure\n the QEMU version supports shared memory mapping.\n\n* Issues with ``virsh destroy`` not destroying the VM:\n\n Using libvirt ``virsh create`` the ``qemu-wrap.py`` spawns a new process to run ``qemu-kvm``. This impacts the behavior\n of ``virsh destroy`` which kills the process running ``qemu-wrap.py`` without actually destroying the VM (it leaves\n the ``qemu-kvm`` process running):\n\n This following patch should fix this issue:\n http://dpdk.org/ml/archives/dev/2014-June/003607.html\n\n* In an Ubuntu environment, QEMU fails to start a new guest normally with user space VHOST due to not being able\n to allocate huge pages for the new guest:\n\n The solution for this issue is to add ``-boot c`` into the QEMU command line to make sure the huge pages are\n allocated properly and then the guest should start normally.\n\n Use ``cat /proc/meminfo`` to check if there is any changes in the value of ``HugePages_Total`` and ``HugePages_Free``\n after the guest startup.\n\n* Log message: ``eventfd_link: module verification failed: signature and/or required key missing - tainting kernel``:\n\n This log message may be ignored. The message occurs due to the kernel module ``eventfd_link``, which is not a standard\n Linux module but which is necessary for the user space VHOST current implementation (CUSE-based) to communicate with\n the guest.\n\n\nRunning DPDK in the Virtual Machine\n-----------------------------------\n\nFor the DPDK vhost-net sample code to switch packets into the VM,\nthe sample code must first learn the MAC address of the VM's virtio-net device.\nThe sample code detects the address from packets being transmitted from the VM, similar to a learning switch.\n\nThis behavior requires no special action or configuration with the Linux* virtio-net driver in the VM\nas the Linux* Kernel will automatically transmit packets during device initialization.\nHowever, DPDK-based applications must be modified to automatically transmit packets during initialization\nto facilitate the DPDK vhost- net sample code's MAC learning.\n\nThe DPDK testpmd application can be configured to automatically transmit packets during initialization\nand to act as an L2 forwarding switch.\n\nTestpmd MAC Forwarding\n~~~~~~~~~~~~~~~~~~~~~~\n\nAt high packet rates, a minor packet loss may be observed.\nTo resolve this issue, a \"wait and retry\" mode is implemented in the testpmd and vhost sample code.\nIn the \"wait and retry\" mode if the virtqueue is found to be full, then testpmd waits for a period of time before retrying to enqueue packets.\n\nThe \"wait and retry\" algorithm is implemented in DPDK testpmd as a forwarding method call \"mac_retry\".\nThe following sequence diagram describes the algorithm in detail.\n\n.. _figure_tx_dpdk_testpmd:\n\n.. figure:: img/tx_dpdk_testpmd.*\n\n Packet Flow on TX in DPDK-testpmd\n\n\nRunning Testpmd\n~~~~~~~~~~~~~~~\n\nThe testpmd application is automatically built when DPDK is installed.\nRun the testpmd application as follows:\n\n.. code-block:: console\n\n user@target:~$ x86_64-native-linuxapp-gcc/app/testpmd -c 0x3 -- n 4 -socket-mem 128 -- --burst=64 -i\n\nThe destination MAC address for packets transmitted on each port can be set at the command line:\n\n.. code-block:: console\n\n user@target:~$ x86_64-native-linuxapp-gcc/app/testpmd -c 0x3 -- n 4 -socket-mem 128 -- --burst=64 -i --eth- peer=0,aa:bb:cc:dd:ee:ff --eth-peer=1,ff,ee,dd,cc,bb,aa\n\n* Packets received on port 1 will be forwarded on port 0 to MAC address\n\n aa:bb:cc:dd:ee:ff.\n\n* Packets received on port 0 will be forwarded on port 1 to MAC address\n\n ff,ee,dd,cc,bb,aa.\n\nThe testpmd application can then be configured to act as an L2 forwarding application:\n\n.. code-block:: console\n\n testpmd> set fwd mac_retry\n\nThe testpmd can then be configured to start processing packets,\ntransmitting packets first so the DPDK vhost sample code on the host can learn the MAC address:\n\n.. code-block:: console\n\n testpmd> start tx_first\n\n.. note::\n\n Please note \"set fwd mac_retry\" is used in place of \"set fwd mac_fwd\" to ensure the retry feature is activated.\n\nPassing Traffic to the Virtual Machine Device\n---------------------------------------------\n\nFor a virtio-net device to receive traffic,\nthe traffic's Layer 2 header must include both the virtio-net device's MAC address and VLAN tag.\nThe DPDK sample code behaves in a similar manner to a learning switch in that\nit learns the MAC address of the virtio-net devices from the first transmitted packet.\nOn learning the MAC address,\nthe DPDK vhost sample code prints a message with the MAC address and VLAN tag virtio-net device.\nFor example:\n\n.. code-block:: console\n\n DATA: (0) MAC_ADDRESS cc:bb:bb:bb:bb:bb and VLAN_TAG 1000 registered\n\nThe above message indicates that device 0 has been registered with MAC address cc:bb:bb:bb:bb:bb and VLAN tag 1000.\nAny packets received on the NIC with these values is placed on the devices receive queue.\nWhen a virtio-net device transmits packets, the VLAN tag is added to the packet by the DPDK vhost sample code.\n" }, { "path": "doc/guides/sample_app_ug/vm_power_management.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nVM Power Management Application\n===============================\n\nIntroduction\n------------\n\nApplications running in Virtual Environments have an abstract view of\nthe underlying hardware on the Host, in particular applications cannot see\nthe binding of virtual to physical hardware.\nWhen looking at CPU resourcing, the pinning of Virtual CPUs(vCPUs) to\nHost Physical CPUs(pCPUS) is not apparent to an application\nand this pinning may change over time.\nFurthermore, Operating Systems on virtual machines do not have the ability\nto govern their own power policy; the Machine Specific Registers (MSRs)\nfor enabling P-State transitions are not exposed to Operating Systems\nrunning on Virtual Machines(VMs).\n\nThe Virtual Machine Power Management solution shows an example of\nhow a DPDK application can indicate its processing requirements using VM local\nonly information(vCPU/lcore) to a Host based Monitor which is responsible\nfor accepting requests for frequency changes for a vCPU, translating the vCPU\nto a pCPU via libvirt and affecting the change in frequency.\n\nThe solution is comprised of two high-level components:\n\n#. Example Host Application\n\n Using a Command Line Interface(CLI) for VM->Host communication channel management\n allows adding channels to the Monitor, setting and querying the vCPU to pCPU pinning,\n inspecting and manually changing the frequency for each CPU.\n The CLI runs on a single lcore while the thread responsible for managing\n VM requests runs on a second lcore.\n\n VM requests arriving on a channel for frequency changes are passed\n to the librte_power ACPI cpufreq sysfs based library.\n The Host Application relies on both qemu-kvm and libvirt to function.\n\n#. librte_power for Virtual Machines\n\n Using an alternate implementation for the librte_power API, requests for\n frequency changes are forwarded to the host monitor rather than\n the APCI cpufreq sysfs interface used on the host.\n\n The l3fwd-power application will use this implementation when deployed on a VM\n (see Chapter 11 \"L3 Forwarding with Power Management Application\").\n\n.. _figure_vm_power_mgr_highlevel:\n\n.. figure:: img/vm_power_mgr_highlevel.*\n\n Highlevel Solution\n\n\nOverview\n--------\n\nVM Power Management employs qemu-kvm to provide communications channels\nbetween the host and VMs in the form of Virtio-Serial which appears as\na paravirtualized serial device on a VM and can be configured to use\nvarious backends on the host. For this example each Virtio-Serial endpoint\non the host is configured as AF_UNIX file socket, supporting poll/select\nand epoll for event notification.\nIn this example each channel endpoint on the host is monitored via\nepoll for EPOLLIN events.\nEach channel is specified as qemu-kvm arguments or as libvirt XML for each VM,\nwhere each VM can have a number of channels up to a maximum of 64 per VM,\nin this example each DPDK lcore on a VM has exclusive access to a channel.\n\nTo enable frequency changes from within a VM, a request via the librte_power interface\nis forwarded via Virtio-Serial to the host, each request contains the vCPU\nand power command(scale up/down/min/max).\nThe API for host and guest librte_power is consistent across environments,\nwith the selection of VM or Host Implementation determined at automatically\nat runtime based on the environment.\n\nUpon receiving a request, the host translates the vCPU to a pCPU via\nthe libvirt API before forwarding to the host librte_power.\n\n.. _figure_vm_power_mgr_vm_request_seq:\n\n.. figure:: img/vm_power_mgr_vm_request_seq.*\n\n VM request to scale frequency\n\n\nPerformance Considerations\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nWhile Haswell Microarchitecture allows for independent power control for each core,\nearlier Microarchtectures do not offer such fine grained control.\nWhen deployed on pre-Haswell platforms greater care must be taken in selecting\nwhich cores are assigned to a VM, for instance a core will not scale down\nuntil its sibling is similarly scaled.\n\nConfiguration\n-------------\n\nBIOS\n~~~~\n\nEnhanced Intel SpeedStep® Technology must be enabled in the platform BIOS\nif the power management feature of DPDK is to be used.\nOtherwise, the sys file folder /sys/devices/system/cpu/cpu0/cpufreq will not exist,\nand the CPU frequency-based power management cannot be used.\nConsult the relevant BIOS documentation to determine how these settings\ncan be accessed.\n\nHost Operating System\n~~~~~~~~~~~~~~~~~~~~~\n\nThe Host OS must also have the *apci_cpufreq* module installed, in some cases\nthe *intel_pstate* driver may be the default Power Management environment.\nTo enable *acpi_cpufreq* and disable *intel_pstate*, add the following\nto the grub Linux command line:\n\n.. code-block:: console\n\n intel_pstate=disable\n\nUpon rebooting, load the *acpi_cpufreq* module:\n\n.. code-block:: console\n\n modprobe acpi_cpufreq\n\nHypervisor Channel Configuration\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nVirtio-Serial channels are configured via libvirt XML:\n\n\n.. code-block:: xml\n\n {vm_name}\n \n
\n \n \n \n \n \n\n\nWhere a single controller of type *virtio-serial* is created and up to 32 channels\ncan be associated with a single controller and multiple controllers can be specified.\nThe convention is to use the name of the VM in the host path *{vm_name}* and\nto increment *{channel_num}* for each channel, likewise the port value *{N}*\nmust be incremented for each channel.\n\nEach channel on the host will appear in *path*, the directory */tmp/powermonitor/*\nmust first be created and given qemu permissions\n\n.. code-block:: console\n\n mkdir /tmp/powermonitor/\n chown qemu:qemu /tmp/powermonitor\n\nNote that files and directories within /tmp are generally removed upon\nrebooting the host and the above steps may need to be carried out after each reboot.\n\nThe serial device as it appears on a VM is configured with the *target* element attribute *name*\nand must be in the form of *virtio.serial.port.poweragent.{vm_channel_num}*,\nwhere *vm_channel_num* is typically the lcore channel to be used in DPDK VM applications.\n\nEach channel on a VM will be present at */dev/virtio-ports/virtio.serial.port.poweragent.{vm_channel_num}*\n\nCompiling and Running the Host Application\n------------------------------------------\n\nCompiling\n~~~~~~~~~\n\n#. export RTE_SDK=/path/to/rte_sdk\n#. cd ${RTE_SDK}/examples/vm_power_manager\n#. make\n\nRunning\n~~~~~~~\n\nThe application does not have any specific command line options other than *EAL*:\n\n.. code-block:: console\n\n ./build/vm_power_mgr [EAL options]\n\nThe application requires exactly two cores to run, one core is dedicated to the CLI,\nwhile the other is dedicated to the channel endpoint monitor, for example to run\non cores 0 & 1 on a system with 4 memory channels:\n\n.. code-block:: console\n\n ./build/vm_power_mgr -c 0x3 -n 4\n\nAfter successful initialization the user is presented with VM Power Manager CLI:\n\n.. code-block:: console\n\n vm_power>\n\nVirtual Machines can now be added to the VM Power Manager:\n\n.. code-block:: console\n\n vm_power> add_vm {vm_name}\n\nWhen a {vm_name} is specified with the *add_vm* command a lookup is performed\nwith libvirt to ensure that the VM exists, {vm_name} is used as an unique identifier\nto associate channels with a particular VM and for executing operations on a VM within the CLI.\nVMs do not have to be running in order to add them.\n\nA number of commands can be issued via the CLI in relation to VMs:\n\n Remove a Virtual Machine identified by {vm_name} from the VM Power Manager.\n\n .. code-block:: console\n\n rm_vm {vm_name}\n\n Add communication channels for the specified VM, the virtio channels must be enabled\n in the VM configuration(qemu/libvirt) and the associated VM must be active.\n {list} is a comma-separated list of channel numbers to add, using the keyword 'all'\n will attempt to add all channels for the VM:\n\n .. code-block:: console\n\n add_channels {vm_name} {list}|all\n\n Enable or disable the communication channels in {list}(comma-separated)\n for the specified VM, alternatively list can be replaced with keyword 'all'.\n Disabled channels will still receive packets on the host, however the commands\n they specify will be ignored. Set status to 'enabled' to begin processing requests again:\n\n .. code-block:: console\n\n set_channel_status {vm_name} {list}|all enabled|disabled\n\n Print to the CLI the information on the specified VM, the information\n lists the number of vCPUS, the pinning to pCPU(s) as a bit mask, along with\n any communication channels associated with each VM, along with the status of each channel:\n\n .. code-block:: console\n\n show_vm {vm_name}\n\n Set the binding of Virtual CPU on VM with name {vm_name} to the Physical CPU mask:\n\n .. code-block:: console\n\n set_pcpu_mask {vm_name} {vcpu} {pcpu}\n\n Set the binding of Virtual CPU on VM to the Physical CPU:\n\n .. code-block:: console\n\n set_pcpu {vm_name} {vcpu} {pcpu}\n\nManual control and inspection can also be carried in relation CPU frequency scaling:\n\n Get the current frequency for each core specified in the mask:\n\n .. code-block:: console\n\n show_cpu_freq_mask {mask}\n\n Set the current frequency for the cores specified in {core_mask} by scaling each up/down/min/max:\n\n .. code-block:: console\n\n set_cpu_freq {core_mask} up|down|min|max\n\n Get the current frequency for the specified core:\n\n .. code-block:: console\n\n show_cpu_freq {core_num}\n\n Set the current frequency for the specified core by scaling up/down/min/max:\n\n .. code-block:: console\n\n set_cpu_freq {core_num} up|down|min|max\n\nCompiling and Running the Guest Applications\n--------------------------------------------\n\nFor compiling and running l3fwd-power, see Chapter 11 \"L3 Forwarding with Power Management Application\".\n\nA guest CLI is also provided for validating the setup.\n\nFor both l3fwd-power and guest CLI, the channels for the VM must be monitored by the\nhost application using the *add_channels* command on the host.\n\nCompiling\n~~~~~~~~~\n\n#. export RTE_SDK=/path/to/rte_sdk\n#. cd ${RTE_SDK}/examples/vm_power_manager/guest_cli\n#. make\n\nRunning\n~~~~~~~\n\nThe application does not have any specific command line options other than *EAL*:\n\n.. code-block:: console\n\n ./build/vm_power_mgr [EAL options]\n\nThe application for example purposes uses a channel for each lcore enabled,\nfor example to run on cores 0,1,2,3 on a system with 4 memory channels:\n\n.. code-block:: console\n\n ./build/guest_vm_power_mgr -c 0xf -n 4\n\n\nAfter successful initialization the user is presented with VM Power Manager Guest CLI:\n\n.. code-block:: console\n\n vm_power(guest)>\n\nTo change the frequency of a lcore, use the set_cpu_freq command.\nWhere {core_num} is the lcore and channel to change frequency by scaling up/down/min/max.\n\n.. code-block:: console\n\n set_cpu_freq {core_num} up|down|min|max\n" }, { "path": "doc/guides/sample_app_ug/vmdq_dcb_forwarding.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nVMDQ and DCB Forwarding Sample Application\n==========================================\n\nThe VMDQ and DCB Forwarding sample application is a simple example of packet processing using the DPDK.\nThe application performs L2 forwarding using VMDQ and DCB to divide the incoming traffic into 128 queues.\nThe traffic splitting is performed in hardware by the VMDQ and DCB features of the Intel® 82599 10 Gigabit Ethernet Controller.\n\nOverview\n--------\n\nThis sample application can be used as a starting point for developing a new application that is based on the DPDK and\nuses VMDQ and DCB for traffic partitioning.\n\nThe VMDQ and DCB filters work on VLAN traffic to divide the traffic into 128 input queues on the basis of the VLAN ID field and\nVLAN user priority field.\nVMDQ filters split the traffic into 16 or 32 groups based on the VLAN ID.\nThen, DCB places each packet into one of either 4 or 8 queues within that group, based upon the VLAN user priority field.\n\nIn either case, 16 groups of 8 queues, or 32 groups of 4 queues, the traffic can be split into 128 hardware queues on the NIC,\neach of which can be polled individually by a DPDK application.\n\nAll traffic is read from a single incoming port (port 0) and output on port 1, without any processing being performed.\nThe traffic is split into 128 queues on input, where each thread of the application reads from multiple queues.\nFor example, when run with 8 threads, that is, with the -c FF option, each thread receives and forwards packets from 16 queues.\n\nAs supplied, the sample application configures the VMDQ feature to have 16 pools with 8 queues each as indicated in :numref:`figure_vmdq_dcb_example`.\nThe Intel® 82599 10 Gigabit Ethernet Controller NIC also supports the splitting of traffic into 32 pools of 4 queues each and\nthis can be used by changing the NUM_POOLS parameter in the supplied code.\nThe NUM_POOLS parameter can be passed on the command line, after the EAL parameters:\n\n.. code-block:: console\n\n ./build/vmdq_dcb [EAL options] -- -p PORTMASK --nb-pools NP\n\nwhere, NP can be 16 or 32.\n\n.. _figure_vmdq_dcb_example:\n\n.. figure:: img/vmdq_dcb_example.*\n\n Packet Flow Through the VMDQ and DCB Sample Application\n\n\nIn Linux* user space, the application can display statistics with the number of packets received on each queue.\nTo have the application display the statistics, send a SIGHUP signal to the running application process, as follows:\n\nwhere, is the process id of the application process.\n\nThe VMDQ and DCB Forwarding sample application is in many ways simpler than the L2 Forwarding application\n(see Chapter 9 , \"L2 Forwarding Sample Application (in Real and Virtualized Environments)\")\nas it performs unidirectional L2 forwarding of packets from one port to a second port.\nNo command-line options are taken by this application apart from the standard EAL command-line options.\n\n.. note::\n\n Since VMD queues are being used for VMM, this application works correctly\n when VTd is disabled in the BIOS or Linux* kernel (intel_iommu=off).\n\nCompiling the Application\n-------------------------\n\n#. Go to the examples directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk cd ${RTE_SDK}/examples/vmdq_dcb\n\n#. Set the target (a default target is used if not specified). For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n See the *DPDK Getting Started Guide* for possible RTE_TARGET values.\n\n#. Build the application:\n\n .. code-block:: console\n\n make\n\nRunning the Application\n-----------------------\n\nTo run the example in a linuxapp environment:\n\n.. code-block:: console\n\n user@target:~$ ./build/vmdq_dcb -c f -n 4 -- -p 0x3 --nb-pools 16\n\nRefer to the *DPDK Getting Started Guide* for general information on running applications and\nthe Environment Abstraction Layer (EAL) options.\n\nExplanation\n-----------\n\nThe following sections provide some explanation of the code.\n\nInitialization\n~~~~~~~~~~~~~~\n\nThe EAL, driver and PCI configuration is performed largely as in the L2 Forwarding sample application,\nas is the creation of the mbuf pool.\nSee Chapter 9, \"L2 Forwarding Sample Application (in Real and Virtualized Environments)\".\nWhere this example application differs is in the configuration of the NIC port for RX.\n\nThe VMDQ and DCB hardware feature is configured at port initialization time by setting the appropriate values in the\nrte_eth_conf structure passed to the rte_eth_dev_configure() API.\nInitially in the application,\na default structure is provided for VMDQ and DCB configuration to be filled in later by the application.\n\n.. code-block:: c\n\n /* empty vmdq+dcb configuration structure. Filled in programmatically */\n\n static const struct rte_eth_conf vmdq_dcb_conf_default = {\n .rxmode = {\n .mq_mode = ETH_VMDQ_DCB,\n .split_hdr_size = 0,\n .header_split = 0, /**< Header Split disabled */\n .hw_ip_checksum = 0, /**< IP checksum offload disabled */\n .hw_vlan_filter = 0, /**< VLAN filtering disabled */\n .jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n },\n\n .txmode = {\n .mq_mode = ETH_DCB_NONE,\n },\n\n .rx_adv_conf = {\n /*\n * should be overridden separately in code with\n * appropriate values\n */\n\n .vmdq_dcb_conf = {\n .nb_queue_pools = ETH_16_POOLS,\n .enable_default_pool = 0,\n .default_pool = 0,\n .nb_pool_maps = 0,\n .pool_map = {{0, 0},},\n .dcb_queue = {0},\n },\n },\n };\n\nThe get_eth_conf() function fills in an rte_eth_conf structure with the appropriate values,\nbased on the global vlan_tags array,\nand dividing up the possible user priority values equally among the individual queues\n(also referred to as traffic classes) within each pool, that is,\nif the number of pools is 32, then the user priority fields are allocated two to a queue.\nIf 16 pools are used, then each of the 8 user priority fields is allocated to its own queue within the pool.\nFor the VLAN IDs, each one can be allocated to possibly multiple pools of queues,\nso the pools parameter in the rte_eth_vmdq_dcb_conf structure is specified as a bitmask value.\n\n.. code-block:: c\n\n const uint16_t vlan_tags[] = {\n 0, 1, 2, 3, 4, 5, 6, 7,\n 8, 9, 10, 11, 12, 13, 14, 15,\n 16, 17, 18, 19, 20, 21, 22, 23,\n 24, 25, 26, 27, 28, 29, 30, 31\n };\n\n\n /* Builds up the correct configuration for vmdq+dcb based on the vlan tags array\n * given above, and the number of traffic classes available for use. */\n\n static inline int\n get_eth_conf(struct rte_eth_conf *eth_conf, enum rte_eth_nb_pools num_pools)\n {\n struct rte_eth_vmdq_dcb_conf conf;\n unsigned i;\n\n if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS ) return -1;\n\n conf.nb_queue_pools = num_pools;\n conf.enable_default_pool = 0;\n conf.default_pool = 0; /* set explicit value, even if not used */\n conf.nb_pool_maps = sizeof( vlan_tags )/sizeof( vlan_tags[ 0 ]);\n\n for (i = 0; i < conf.nb_pool_maps; i++){\n conf.pool_map[i].vlan_id = vlan_tags[ i ];\n conf.pool_map[i].pools = 1 << (i % num_pools);\n }\n\n for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++){\n conf.dcb_queue[i] = (uint8_t)(i % (NUM_QUEUES/num_pools));\n }\n\n (void) rte_memcpy(eth_conf, &vmdq_dcb_conf_default, sizeof(\\*eth_conf));\n (void) rte_memcpy(ð_conf->rx_adv_conf.vmdq_dcb_conf, &conf, sizeof(eth_conf->rx_adv_conf.vmdq_dcb_conf));\n\n return 0;\n }\n\nOnce the network port has been initialized using the correct VMDQ and DCB values,\nthe initialization of the port's RX and TX hardware rings is performed similarly to that\nin the L2 Forwarding sample application.\nSee Chapter 9, \"L2 Forwarding Sample Application (in Real and Virtualized Environments)\" for more information.\n\nStatistics Display\n~~~~~~~~~~~~~~~~~~\n\nWhen run in a linuxapp environment,\nthe VMDQ and DCB Forwarding sample application can display statistics showing the number of packets read from each RX queue.\nThis is provided by way of a signal handler for the SIGHUP signal,\nwhich simply prints to standard output the packet counts in grid form.\nEach row of the output is a single pool with the columns being the queue number within that pool.\n\nTo generate the statistics output, use the following command:\n\n.. code-block:: console\n\n user@host$ sudo killall -HUP vmdq_dcb_app\n\nPlease note that the statistics output will appear on the terminal where the vmdq_dcb_app is running,\nrather than the terminal from which the HUP signal was sent.\n" }, { "path": "doc/guides/testpmd_app_ug/build_app.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nCompiling the Application\n=========================\n\nThe testpmd application is compiled as part of the main compilation of the DPDK libraries and tools.\nRefer to the DPDK Getting Started Guide for details.\nThe basic compilation steps are:\n\n#. Set the required environmental variables and go to the source directory:\n\n .. code-block:: console\n\n export RTE_SDK=/path/to/rte_sdk\n cd $RTE_SDK\n\n#. Set the compilation target. For example:\n\n .. code-block:: console\n\n export RTE_TARGET=x86_64-native-linuxapp-gcc\n\n#. Build the application:\n\n .. code-block:: console\n\n make install T=$RTE_TARGET\n\n The compiled application will be located at:\n\n .. code-block:: console\n\n $RTE_SDK/$RTE_TARGET/build/app/testpmd\n" }, { "path": "doc/guides/testpmd_app_ug/index.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nTestpmd Application User Guide\n==============================\n\n|today|\n\n**Contents**\n\n.. toctree::\n :maxdepth: 3\n :numbered:\n\n intro\n overview\n build_app\n run_app\n testpmd_funcs\n" }, { "path": "doc/guides/testpmd_app_ug/intro.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIntroduction\n============\n\nThis document is a user guide for the testpmd example application that is shipped as part of the Data Plane Development Kit.\n\nThe testpmd application can be used to test the DPDK in a packet forwarding mode\nand also to access NIC hardware features such as Flow Director.\nIt also serves as a example of how to build a more fully-featured application using the DPDK SDK.\n\nDocumentation Roadmap\n---------------------\n\nThe following is a list of DPDK documents in the suggested reading order:\n\n* **Release Notes** : Provides release-specific information, including supported features,\n limitations, fixed issues, known issues and so on.\n Also, provides the answers to frequently asked questions in FAQ format.\n\n* **Getting Started Guide** (this document): Describes how to install and configure the DPDK;\n designed to get users up and running quickly with the software.\n\n* **Programmer's Guide** : Describes:\n\n * The software architecture and how to use it (through examples), specifically in a Linux* application (linuxapp) environment\n\n * The content of the DPDK, the build system\n (including the commands that can be used in the root DPDK Makefile to build the development kit and an application)\n and guidelines for porting an application\n\n * Optimizations used in the software and those that should be considered for new development\n\n A glossary of terms is also provided.\n\n* **API Reference** : Provides detailed information about DPDK functions, data structures and other programming constructs.\n\n* **Sample Applications User Guide** : Describes a set of sample applications.\n Each chapter describes a sample application that showcases specific functionality and\n provides instructions on how to compile, run and use the sample application.\n\n.. note::\n\n These documents are available for download as a separate documentation package at the same location as the DPDK code package.\n" }, { "path": "doc/guides/testpmd_app_ug/overview.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nOverview\n========\n\nThe following sections show how to build and run the testpmd application and\nhow to configure the application from the command line and the run-time environment.\n" }, { "path": "doc/guides/testpmd_app_ug/run_app.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nRunning the Application\n=======================\n\nEAL Command-line Options\n------------------------\n\nThe following are the EAL command-line options that can be used in conjunction with the testpmd,\nor any other DPDK application.\nSee the DPDK Getting Started Guide for more information on these options.\n\n* -c COREMASK\n\n Set the hexadecimal bitmask of the cores to run on.\n\n* -l CORELIST\n\n List of cores to run on\n\n The argument format is [-c2][,c3[-c4],...]\n where c1, c2, etc are core indexes between 0 and 128\n\n* --lcores COREMAP\n\n Map lcore set to physical cpu set\n\n The argument format is\n '[<,lcores[@cpus]>...]'\n\n lcores and cpus list are grouped by '(' and ')'\n Within the group, '-' is used for range separator,\n ',' is used for single number separator.\n '( )' can be omitted for single element group,\n '@' can be omitted if cpus and lcores have the same value\n\n* --master-lcore ID\n\n Core ID that is used as master\n\n* -n NUM\n\n Set the number of memory channels to use.\n\n* -b, --pci-blacklist domain:bus:devid.func\n\n Blacklist a PCI devise to prevent EAL from using it. Multiple -b options are allowed.\n\n* -d LIB.so\n\n Load an external driver. Multiple -d options are allowed.\n\n* -w, --pci-whitelist domain:bus:devid:func\n\n Add a PCI device in white list.\n\n* -m MB\n\n Memory to allocate. See also --socket-mem.\n\n* -r NUM\n\n Set the number of memory ranks (auto-detected by default).\n\n* -v\n\n Display the version information on startup.\n\n* --xen-dom0\n\n Support application running on Xen Domain0 without hugetlbfs.\n\n* --syslog\n\n Set the syslog facility.\n\n* --socket-mem\n\n Set the memory to allocate on specific sockets (use comma separated values).\n\n* --huge-dir\n\n Specify the directory where the hugetlbfs is mounted.\n\n* --proc-type\n\n Set the type of the current process.\n\n* --file-prefix\n\n Prefix for hugepage filenames.\n\n* -vmware-tsc-map\n\n Use VMware TSC map instead of native RDTSC.\n\n* --vdev\n\n Add a virtual device, with format \"[,key=val, ...]\", e.g. --vdev=eth_pcap0,iface=eth2.\n\n* --base-virtaddr\n\n Specify base virtual address.\n\n* --create-uio-dev\n\n Create /dev/uioX (usually done by hotplug).\n\n* --no-shconf\n\n No shared config (mmap'd files).\n\n* --no-pci\n\n Disable pci.\n\n* --no-hpet\n\n Disable hpet.\n\n* --no-huge\n\n Use malloc instead of hugetlbfs.\n\n\nTestpmd Command-line Options\n----------------------------\n\nThe following are the command-line options for the testpmd applications.\nThey must be separated from the EAL options, shown in the previous section, with a -- separator:\n\n.. code-block:: console\n\n sudo ./testpmd -c 0xF -n 4 -- -i --portmask=0x1 --nb-cores=2\n\n* -i, --interactive\n\n Run testpmd in interactive mode.\n In this mode, the testpmd starts with a prompt that can be used to start and stop forwarding,\n configure the application and display stats on the current packet processing session.\n See the Section 5.0, \"Test Runtime Functions\" section for more details.\n\n In non-interactive mode,\n the application starts with the configuration specified on the command-line and\n immediately enters forwarding mode.\n\n* -h, --help\n\n Display a help message and quit.\n\n* -a, --auto-start\n\n Start forwarding on init.\n\n* --nb-cores=N\n\n Set the number of forwarding cores,\n where 1 <= N <= number of cores or RTE_MAX_LCORE from the configuration file.\n The default value is 1.\n\n* --nb-ports=N\n\n Set the number of forwarding ports,\n where 1 <= N <= number of ports on the board or RTE_MAX_ETHPORTS from the configuration file.\n The default value is the number of ports on the board.\n\n* --coremask=0xXX\n\n Set the hexadecimal bitmask of the cores running the packet forwarding test.\n The master lcore is reserved for command line parsing only and cannot be masked on for packet forwarding.\n\n* --portmask=0xXX\n\n Set the hexadecimal bitmask of the ports used by the packet forwarding test.\n\n* --numa\n\n Enable NUMA-aware allocation of RX/TX rings and of RX memory buffers (mbufs).\n\n* --port-numa-config=(port,socket)[,(port,socket)]\n\n Specify the socket on which the memory pool to be used by the port will be allocated.\n\n* --ring-numa-config=(port,flag,socket)[,(port,flag,socket)]\n\n Specify the socket on which the TX/RX rings for the port will be allocated.\n Where flag is 1 for RX, 2 for TX, and 3 for RX and TX.\n\n* --socket-num=N\n\n Set the socket from which all memory is allocated in NUMA mode,\n where 0 <= N < number of sockets on the board.\n\n* --mbuf-size=N\n\n Set the data size of the mbufs used to N bytes, where N < 65536. The default value is 2048.\n\n* --total-num-mbufs=N\n\n Set the number of mbufs to be allocated in the mbuf pools, where N > 1024.\n\n* --max-pkt-len=N\n\n Set the maximum packet size to N bytes, where N >= 64. The default value is 1518.\n\n* --eth-peers-configfile=name\n\n Use a configuration file containing the Ethernet addresses of the peer ports.\n The configuration file should contain the Ethernet addresses on separate lines:\n\n XX:XX:XX:XX:XX:01\n\n XX:XX:XX:XX:XX:02\n\n ...\n\n* --eth-peer=N,XX:XX:XX:XX:XX:XX\n\n Set the MAC address XX:XX:XX:XX:XX:XX of the peer port N,\n where 0 <= N < RTE_MAX_ETHPORTS from the configuration file.\n\n* --pkt-filter-mode=mode\n\n Set Flow Director mode where mode is either none (the default), signature or perfect.\n See the Section 5.6, \"Flow Director Functions\" for more detail.\n\n* --pkt-filter-report-hash=mode\n\n Set Flow Director hash match reporting mode where mode is none, match (the default) or always.\n\n* --pkt-filter-size=N\n\n Set Flow Director allocated memory size, where N is 64K, 128K or 256K.\n Sizes are in kilobytes. The default is 64.\n\n* --pkt-filter-flexbytes-offset=N\n\n Set the flexbytes offset.\n The offset is defined in words (not bytes) counted from the first byte of the destination Ethernet MAC address,\n where N is 0 <= N <= 32.\n The default value is 0x6.\n\n* --pkt-filter-drop-queue=N\n\n Set the drop-queue.\n In perfect filter mode, when a rule is added with queue = -1, the packet will be enqueued into the RX drop-queue.\n If the drop-queue does not exist, the packet is dropped. The default value is N=127.\n\n* --crc-strip\n\n Enable hardware CRC stripping.\n\n* --enable-rx-cksum\n\n Enable hardware RX checksum offload.\n\n* --disable-hw-vlan\n\n Disable hardware VLAN.\n\n* --disable-hw-vlan-filter\n\n Disable hardware VLAN filter.\n\n* --disable-hw-vlan-strip\n\n Disable hardware VLAN strip.\n\n* --disable-hw-vlan-extend\n\n Disable hardware VLAN extend.\n\n* --enable-drop-en\n\n Enable per-queue packet drop for packets with no descriptors.\n\n* --disable-rss\n\n Disable RSS (Receive Side Scaling).\n\n* --port-topology=mode\n\n Set port topology, where mode is paired(the default) or chained.\n In paired mode, the forwarding is between pairs of ports, for example: (0,1), (2,3), (4,5).\n In chained mode, the forwarding is to the next available port in the port mask, for example: (0,1), (1,2), (2,0).\n The ordering of the ports can be changed using the portlist testpmd runtime function.\n\n* --forward-mode=N\n\n Set forwarding mode. (N: io|mac|mac_retry|mac_swap|flowgen|rxonly|txonly|csum|icmpecho|ieee1588)\n\n* --rss-ip\n\n Set RSS functions for IPv4/IPv6 only.\n\n* --rss-udp\n\n Set RSS functions for IPv4/IPv6 and UDP.\n\n* --rxq=N\n\n Set the number of RX queues per port to N, where 1 <= N <= 65535.\n The default value is 1.\n\n* --rxd=N\n\n Set the number of descriptors in the RX rings to N, where N > 0.\n The default value is 128.\n\n* --txq=N\n\n Set the number of TX queues per port to N, where 1 <= N <= 65535.\n The default value is 1.\n\n* --txd=N\n\n Set the number of descriptors in the TX rings to N, where N > 0.\n The default value is 512.\n\n* --burst=N\n\n Set the number of packets per burst to N, where 1 <= N <= 512.\n The default value is 16.\n\n* --mbcache=N\n\n Set the cache of mbuf memory pools to N, where 0 <= N <= 512.\n The default value is 16.\n\n* --rxpt=N\n\n Set the prefetch threshold register of RX rings to N, where N >= 0.\n The default value is 8.\n\n* --rxht=N\n\n Set the host threshold register of RX rings to N, where N >= 0.\n The default value is 8.\n\n* --rxfreet=N\n\n Set the free threshold of RX descriptors to N, where 0 <= N < value of --rxd.\n The default value is 0.\n\n* --rxwt=N\n\n Set the write-back threshold register of RX rings to N, where N >= 0.\n The default value is 4.\n\n* --txpt=N\n\n Set the prefetch threshold register of TX rings to N, where N >= 0.\n The default value is 36.\n\n* --txht=N\n\n Set the host threshold register of TX rings to N, where N >= 0.\n The default value is 0.\n\n* --txwt=N\n\n Set the write-back threshold register of TX rings to N, where N >= 0.\n The default value is 0.\n\n* --txfreet=N\n\n Set the transmit free threshold of TX rings to N, where 0 <= N <= value of --txd.\n The default value is 0.\n\n* --txrst=N\n\n Set the transmit RS bit threshold of TX rings to N, where 0 <= N <= value of --txd.\n The default value is 0.\n\n* --txqflags=0xXXXXXXXX\n\n Set the hexadecimal bitmask of TX queue flags, where 0 <= N <= 0x7FFFFFFF.\n The default value is 0.\n\n Note::\n\n When using hardware offload functions such as vlan, checksum...,\n add txqflags=0, since depending on the PMD,\n txqflags might be set to a non-zero value.\n\n* --rx-queue-stats-mapping=(port,queue,mapping)[,(port,queue,mapping)]\n\n Set the RX queues statistics counters mapping 0 <= mapping <= 15.\n\n* --tx-queue-stats-mapping=(port,queue,mapping)[,(port,queue,mapping)]\n\n Set the TX queues statistics counters mapping 0 <= mapping <= 15.\n\n* --no-flush-rx\n\n Don't flush the RX streams before starting forwarding. Used mainly with PCAP drivers.\n\n* --txpkts=X[,Y]\n\n Set TX segment sizes.\n\n* --disable-link-check\n\n Disable check on link status when starting/stopping ports.\n" }, { "path": "doc/guides/testpmd_app_ug/testpmd_funcs.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nTestpmd Runtime Functions\n=========================\n\nWhere the testpmd application is started in interactive mode, (-i|--interactive),\nit displays a prompt that can be used to start and stop forwarding,\nconfigure the application, display statistics, set the Flow Director and other tasks.\n\n.. code-block:: console\n\n testpmd>\n\nThe testpmd prompt has some, limited, readline support.\nCommon bash command- line functions such as Ctrl+a and Ctrl+e to go to the start and end of the prompt line are supported\nas well as access to the command history via the up-arrow.\n\nThere is also support for tab completion.\nIf you type a partial command and hit you get a list of the available completions:\n\n.. code-block:: console\n\n testpmd> show port \n\n info [Mul-choice STRING]: show|clear port info|stats|fdir|stat_qmap X\n info [Mul-choice STRING]: show|clear port info|stats|fdir|stat_qmap all\n stats [Mul-choice STRING]: show|clear port info|stats|fdir|stat_qmap X\n stats [Mul-choice STRING]: show|clear port info|stats|fdir|stat_qmap all\n ...\n\nHelp Functions\n--------------\n\nThe testpmd has on-line help for the functions that are available at runtime.\nThese are divided into sections and can be accessed using help, help section or help all:\n\n.. code-block:: console\n\n testpmd> help\n\n Help is available for the following sections:\n help control : Start and stop forwarding.\n help display : Displaying port, stats and config information.\n help config : Configuration information.\n help ports : Configuring ports.\n help registers : Reading and setting port registers.\n help filters : Filters configuration help.\n help all : All of the above sections.\n\nControl Functions\n-----------------\n\nstart\n~~~~~\n\nStart packet forwarding with current configuration:\n\nstart\n\nstart tx_first\n~~~~~~~~~~~~~~\n\nStart packet forwarding with current configuration after sending one burst of packets:\n\nstart tx_first\n\nstop\n~~~~\n\nStop packet forwarding, and display accumulated statistics:\n\nstop\n\nquit\n~~~~\n\nQuit to prompt:\n\nquit\n\nDisplay Functions\n-----------------\n\nThe functions in the following sections are used to display information about the\ntestpmd configuration or the NIC status.\n\nshow port\n~~~~~~~~~\n\nDisplay information for a given port or all ports:\n\nshow port (info|stats|fdir|stat_qmap) (port_id|all)\n\nThe available information categories are:\n\ninfo : General port information such as MAC address.\n\nstats : RX/TX statistics.\n\nfdir : Flow Director information and statistics.\n\nstat_qmap : Queue statistics mapping.\n\nFor example:\n\n.. code-block:: console\n\n testpmd> show port info 0\n\n ********************* Infos for port 0 *********************\n\n MAC address: XX:XX:XX:XX:XX:XX\n Connect to socket: 0\n memory allocation on the socket: 0\n Link status: up\n Link speed: 40000 Mbps\n Link duplex: full-duplex\n Promiscuous mode: enabled\n Allmulticast mode: disabled\n Maximum number of MAC addresses: 64\n Maximum number of MAC addresses of hash filtering: 0\n VLAN offload:\n strip on\n filter on\n qinq(extend) off\n Redirection table size: 512\n Supported flow types:\n ipv4-frag\n ipv4-tcp\n ipv4-udp\n ipv4-sctp\n ipv4-other\n ipv6-frag\n ipv6-tcp\n ipv6-udp\n ipv6-sctp\n ipv6-other\n l2_payload\n\nshow port rss reta\n~~~~~~~~~~~~~~~~~~\n\nDisplay the rss redirection table entry indicated by masks on port X:\n\nshow port (port_id) rss reta (size) (mask0, mask1...)\n\nsize is used to indicate the hardware supported reta size\n\nshow port rss-hash\n~~~~~~~~~~~~~~~~~~\n\nDisplay the RSS hash functions and RSS hash key of a port:\n\nshow port (port_id) rss-hash [key]\n\nclear port\n~~~~~~~~~~\n\nClear the port statistics for a given port or for all ports:\n\nclear port (info|stats|fdir|stat_qmap) (port_id|all)\n\nFor example:\n\n.. code-block:: console\n\n testpmd> clear port stats all\n\nshow config\n~~~~~~~~~~~\n\nDisplays the configuration of the application.\nThe configuration comes from the command-line, the runtime or the application defaults:\n\nshow config (rxtx|cores|fwd)\n\nThe available information categories are:\n\nrxtx : RX/TX configuration items.\n\ncores : List of forwarding cores.\n\nfwd : Packet forwarding configuration.\n\nFor example:\n\n.. code-block:: console\n\n testpmd> show config rxtx\n\n io packet forwarding - CRC stripping disabled - packets/burst=16\n nb forwarding cores=2 - nb forwarding ports=1\n RX queues=1 - RX desc=128 - RX free threshold=0\n RX threshold registers: pthresh=8 hthresh=8 wthresh=4\n TX queues=1 - TX desc=512 - TX free threshold=0\n TX threshold registers: pthresh=36 hthresh=0 wthresh=0\n TX RS bit threshold=0 - TXQ flags=0x0\n\nread rxd\n~~~~~~~~\n\nDisplay an RX descriptor for a port RX queue:\n\nread rxd (port_id) (queue_id) (rxd_id)\n\nFor example:\n\n.. code-block:: console\n\n testpmd> read rxd 0 0 4\n 0x0000000B - 0x001D0180 / 0x0000000B - 0x001D0180\n\nread txd\n~~~~~~~~\n\nDisplay a TX descriptor for a port TX queue:\n\nread txd (port_id) (queue_id) (txd_id)\n\nFor example:\n\n.. code-block:: console\n\n testpmd> read txd 0 0 4\n 0x00000001 - 0x24C3C440 / 0x000F0000 - 0x2330003C\n\nConfiguration Functions\n-----------------------\n\nThe testpmd application can be configured from the runtime as well as from the command-line.\n\nThis section details the available configuration functions that are available.\n\n.. note::\n\n Configuration changes only become active when forwarding is started/restarted.\n\nset default\n~~~~~~~~~~~\n\nReset forwarding to the default configuration:\n\nset default\n\nset verbose\n~~~~~~~~~~~\n\nSet the debug verbosity level:\n\nset verbose (level)\n\nCurrently the only available levels are 0 (silent except for error) and 1 (fully verbose).\n\nset nbport\n~~~~~~~~~~\n\nSet the number of ports used by the application:\n\nset nbport (num)\n\nThis is equivalent to the --nb-ports command-line option.\n\nset nbcore\n~~~~~~~~~~\n\nSet the number of cores used by the application:\n\nset nbcore (num)\n\nThis is equivalent to the --nb-cores command-line option.\n\n.. note::\n\n The number of cores used must not be greater than number of ports used multiplied by the number of queues per port.\n\nset coremask\n~~~~~~~~~~~~\n\nSet the forwarding cores hexadecimal mask:\n\nset coremask (mask)\n\nThis is equivalent to the --coremask command-line option.\n\n.. note::\n\n The master lcore is reserved for command line parsing only and cannot be masked on for packet forwarding.\n\nset portmask\n~~~~~~~~~~~~\n\nSet the forwarding ports hexadecimal mask:\n\nset portmask (mask)\n\nThis is equivalent to the --portmask command-line option.\n\nset burst\n~~~~~~~~~\n\nSet number of packets per burst:\n\nset burst (num)\n\nThis is equivalent to the --burst command-line option.\n\nIn mac_retry forwarding mode, the transmit delay time and number of retries can also be set.\n\nset burst tx delay (micrseconds) retry (num)\n\nset txpkts\n~~~~~~~~~~\n\nSet the length of each segment of the TX-ONLY packets:\n\nset txpkts (x[,y]*)\n\nWhere x[,y]* represents a CSV list of values, without white space.\n\nset corelist\n~~~~~~~~~~~~\n\nSet the list of forwarding cores:\n\nset corelist (x[,y]*)\n\nFor example, to change the forwarding cores:\n\n.. code-block:: console\n\n testpmd> set corelist 3,1\n testpmd> show config fwd\n\n io packet forwarding - ports=2 - cores=2 - streams=2 - NUMA support disabled\n Logical Core 3 (socket 0) forwards packets on 1 streams:\n RX P=0/Q=0 (socket 0) -> TX P=1/Q=0 (socket 0) peer=02:00:00:00:00:01\n Logical Core 1 (socket 0) forwards packets on 1 streams:\n RX P=1/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00\n\n.. note::\n\n The cores are used in the same order as specified on the command line.\n\nset portlist\n~~~~~~~~~~~~\n\nSet the list of forwarding ports:\n\nset portlist (x[,y]*)\n\nFor example, to change the port forwarding:\n\n.. code-block:: console\n\n testpmd> set portlist 0,2,1,3\n testpmd> show config fwd\n\n io packet forwarding - ports=4 - cores=1 - streams=4\n Logical Core 3 (socket 0) forwards packets on 4 streams:\n RX P=0/Q=0 (socket 0) -> TX P=2/Q=0 (socket 0) peer=02:00:00:00:00:01\n RX P=2/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00\n RX P=1/Q=0 (socket 0) -> TX P=3/Q=0 (socket 0) peer=02:00:00:00:00:03\n RX P=3/Q=0 (socket 0) -> TX P=1/Q=0 (socket 0) peer=02:00:00:00:00:02\n\nvlan set strip\n~~~~~~~~~~~~~~\n\nSet the VLAN strip on a port:\n\nvlan set strip (on|off) (port_id)\n\nvlan set stripq\n~~~~~~~~~~~~~~~\n\nSet the VLAN strip for a queue on a port:\n\nvlan set stripq (on|off) (port_id,queue_id)\n\nvlan set filter\n~~~~~~~~~~~~~~~\n\nSet the VLAN filter on a port:\n\nvlan set filter (on|off) (port_id)\n\nvlan set qinq\n~~~~~~~~~~~~~\n\nSet the VLAN QinQ (extended queue in queue) on for a port:\n\nvlan set qinq (on|off) (port_id)\n\nvlan set tpid\n~~~~~~~~~~~~~\n\nSet the outer VLAN TPID for packet filtering on a port:\n\nvlan set tpid (value) (port_id)\n\n.. note::\n\n TPID value must be a 16-bit number (value <= 65536).\n\nrx_vlan add\n~~~~~~~~~~~\n\nAdd a VLAN ID, or all identifiers, to the set of VLAN identifiers filtered by port ID:\n\nrx_vlan add (vlan_id|all) (port_id)\n\n.. note::\n\n VLAN filter must be set on that port. VLAN ID < 4096.\n Depending on the NIC used, number of vlan_ids may be limited to the maximum entries\n in VFTA table. This is important if enabling all vlan_ids.\n\nrx_vlan rm\n~~~~~~~~~~\n\nRemove a VLAN ID, or all identifiers, from the set of VLAN identifiers filtered by port ID:\n\nrx_vlan rm (vlan_id|all) (port_id)\n\nrx_vlan add(for VF)\n~~~~~~~~~~~~~~~~~~~\n\nAdd a VLAN ID, to the set of VLAN identifiers filtered for VF(s) for port ID:\n\nrx_vlan add (vlan_id) port (port_id) vf (vf_mask)\n\nrx_vlan rm(for VF)\n~~~~~~~~~~~~~~~~~~\n\nRemove a VLAN ID, from the set of VLAN identifiers filtered for VF(s) for port ID:\n\nrx_vlan rm (vlan_id) port (port_id) vf (vf_mask)\n\nrx_vlan set tpid\n~~~~~~~~~~~~~~~~\n\nSet the outer VLAN TPID for packet filtering on a port:\n\nrx_vlan set tpid (value) (port_id)\n\ntunnel_filter add\n~~~~~~~~~~~~~~~~~\n\nAdd a tunnel filter on a port:\n\ntunnel_filter add (port_id) (outer_mac) (inner_mac) (ip_addr) (inner_vlan)\n (tunnel_type) (filter_type) (tenant_id) (queue_id)\n\ntunnel_filter remove\n~~~~~~~~~~~~~~~~~~~~\n\nRemove a tunnel filter on a port:\n\ntunnel_filter rm (port_id) (outer_mac) (inner_mac) (ip_addr) (inner_vlan)\n (tunnel_type) (filter_type) (tenant_id) (queue_id)\n\nrx_vxlan_port add\n~~~~~~~~~~~~~~~~~\n\nAdd an UDP port for VXLAN packet filter on a port:\n\nrx_vxlan_port add (udp_port) (port_id)\n\nrx_vxlan_port remove\n~~~~~~~~~~~~~~~~~~~~\n\nRemove an UDP port for VXLAN packet filter on a port:\n\nrx_vxlan_port rm (udp_port) (port_id)\n\ntx_vlan set\n~~~~~~~~~~~\n\nSet hardware insertion of VLAN IDs in packets sent on a port:\n\ntx_vlan set (port_id) vlan_id[, vlan_id_outer]\n\n.. code-block:: console\n\n Set a single VLAN ID (5) insertion on port 0.\n\n tx_vlan set 0 5\n\n Set double VLAN ID (inner: 2, outer: 3) insertion on port 1.\n\n tx_vlan set 1 2 3\n\ntx_vlan set pvid\n~~~~~~~~~~~~~~~~\n\nSet port based hardware insertion of VLAN ID in packets sent on a port:\n\ntx_vlan set pvid (port_id) (vlan_id) (on|off)\n\ntx_vlan reset\n~~~~~~~~~~~~~\n\nDisable hardware insertion of a VLAN header in packets sent on a port:\n\ntx_vlan reset (port_id)\n\ncsum set\n~~~~~~~~\n\nSelect hardware or software calculation of the checksum when\ntransmitting a packet using the csum forward engine:\n\ncsum set (ip|udp|tcp|sctp|outer-ip) (hw|sw) (port_id)\n\n- ip|udp|tcp|sctp always concern the inner layer.\n\n- outer-ip concerns the outer IP layer (only for IPv4) in case the packet is recognized\n as a tunnel packet by the forward engine (vxlan, gre and ipip are\n supported). See \"csum parse-tunnel\" command.\n\n.. note::\n\n Check the NIC Datasheet for hardware limits.\n\ncsum parse-tunnel\n~~~~~~~~~~~~~~~~~\n\nDefine how tunneled packets should be handled by the csum forward\nengine.\n\ncsum parse-tunnel (on|off) (tx_port_id)\n\nIf enabled, the csum forward engine will try to recognize supported\ntunnel headers (vxlan, gre, ipip).\n\nIf disabled, treat tunnel packets as non-tunneled packets (a inner\nheader is handled as a packet payload).\n\n.. note::\n\n The port argument is the TX port like in the \"csum set\" command.\n\nExample:\n\nConsider a packet as following:\n\"eth_out/ipv4_out/udp_out/vxlan/eth_in/ipv4_in/tcp_in\"\n\n- If parse-tunnel is enabled, the ip|udp|tcp|sctp parameters of \"csum\n set\" command are about inner headers (here ipv4_in and tcp_in), and the\n outer-ip parameter is about outer headers (here ipv4_out).\n\n- If parse-tunnel is disabled, the ip|udp|tcp|sctp parameters of \"csum\n set\" command are about outer headers, here ipv4_out and udp_out.\n\ncsum show\n~~~~~~~~~\n\nDisplay tx checksum offload configuration:\n\ncsum show (port_id)\n\ntso set\n~~~~~~~\n\nEnable TCP Segmentation Offload in csum forward engine:\n\ntso set (segsize) (port_id)\n\n.. note::\n\n Check the NIC datasheet for hardware limits\n\ntso show\n~~~~~~~~\n\nDisplay the status of TCP Segmentation Offload:\n\ntso show (port_id)\n\nset fwd\n~~~~~~~\n\nSet the packet forwarding mode:\n\nset fwd (io|mac|mac_retry|macswap|flowgen|rxonly|txonly|csum|icmpecho)\n\nThe available information categories are:\n\n* io: forwards packets \"as-is\" in I/O mode.\n This is the fastest possible forwarding operation as it does not access packets data.\n This is the default mode.\n\n* mac: changes the source and the destination Ethernet addresses of packets before forwarding them.\n\n* mac_retry: same as \"mac\" forwarding mode, but includes retries if the destination queue is full.\n\n* macswap: MAC swap forwarding mode.\n Swaps the source and the destination Ethernet addresses of packets before forwarding them.\n\n* flowgen: multi-flow generation mode.\n Originates a bunch of flows (varying destination IP addresses), and terminate receive traffic.\n\n* rxonly: receives packets but doesn't transmit them.\n\n* txonly: generates and transmits packets without receiving any.\n\n* csum: changes the checksum field with HW or SW methods depending on the offload flags on the packet.\n\n* icmpecho: receives a burst of packets, lookup for IMCP echo requests and, if any, send back ICMP echo replies.\n\n* ieee1588: demonstrate L2 IEEE1588 V2 PTP timestamping for RX and TX. Requires ``CONFIG_RTE_LIBRTE_IEEE1588=y``.\n Note: TX timestamping is only available in the \"Full Featured\" TX path. To force ``testpmd`` into this mode set ``--txqflags=0``.\n\nExample:\n\n.. code-block:: console\n\n testpmd> set fwd rxonly\n\n Set rxonly packet forwarding mode\n\nmac_addr add\n~~~~~~~~~~~~\n\nAdd an alternative MAC address to a port:\n\nmac_addr add (port_id) (XX:XX:XX:XX:XX:XX)\n\nmac_addr remove\n~~~~~~~~~~~~~~~\n\nRemove a MAC address from a port:\n\nmac_addr remove (port_id) (XX:XX:XX:XX:XX:XX)\n\nmac_addr add(for VF)\n~~~~~~~~~~~~~~~~~~~~\n\nAdd an alternative MAC address for a VF to a port:\n\nmac_add add port (port_id) vf (vf_id) (XX:XX:XX:XX:XX:XX)\n\nset port-uta\n~~~~~~~~~~~~\n\nSet the unicast hash filter(s) on/off for a port X:\n\nset port (port_id) uta (XX:XX:XX:XX:XX:XX|all) (on|off)\n\nset promisc\n~~~~~~~~~~~\n\nSet the promiscuous mode on for a port or for all ports.\nIn promiscuous mode packets are not dropped if they aren't for the specified MAC address:\n\nset promisc (port_id|all) (on|off)\n\nset allmulti\n~~~~~~~~~~~~\n\nSet the allmulti mode for a port or for all ports:\n\nset allmulti (port_id|all) (on|off)\n\nSame as the ifconfig (8) option. Controls how multicast packets are handled.\n\nset flow_ctrl rx\n~~~~~~~~~~~~~~~~\n\nSet the link flow control parameter on a port:\n\nset flow_ctrl rx (on|off) tx (on|off) (high_water) (low_water) \\\n(pause_time) (send_xon) (port_id)\n\nWhere:\n\nhigh_water (integer): High threshold value to trigger XOFF.\n\nlow_water (integer) : Low threshold value to trigger XON.\n\npause_time (integer): Pause quota in the Pause frame.\n\nsend_xon (0/1) : Send XON frame.\n\nmac_ctrl_frame_fwd : Enable receiving MAC control frames\n\nset pfc_ctrl rx\n~~~~~~~~~~~~~~~\n\nSet the priority flow control parameter on a port:\n\nset pfc_ctrl rx (on|off) tx (on|off) (high_water) (low_water) \\ (pause_time) (priority) (port_id)\n\nWhere:\n\npriority (0-7): VLAN User Priority.\n\nset stat_qmap\n~~~~~~~~~~~~~\n\nSet statistics mapping (qmapping 0..15) for RX/TX queue on port:\n\nset stat_qmap (tx|rx) (port_id) (queue_id) (qmapping)\n\nFor example, to set rx queue 2 on port 0 to mapping 5:\n\n.. code-block:: console\n\n testpmd>set stat_qmap rx 0 2 5\n\nset port - rx/tx(for VF)\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet VF receive/transmit from a port:\n\nset port (port_id) vf (vf_id) (rx|tx) (on|off)\n\nset port - mac address filter (for VF)\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nAdd/Remove unicast or multicast MAC addr filter for a VF:\n\nset port (port_id) vf (vf_id) (mac_addr)\n (exact-mac|exact-mac-vlan|hashmac|hashmac-vlan) (on|off)\n\nset port - rx mode(for VF)\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet the VF receive mode of a port:\n\nset port (port_id) vf (vf_id) rxmode (AUPE|ROPE|BAM|MPE) (on|off)\n\nThe available receive modes are:\n\n* AUPE: accepts untagged VLAN.\n\n* ROPE: accepts unicast hash.\n\n* BAM: accepts broadcast packets\n\n* MPE: accepts all multicast packets\n\nset port - tx_rate (for Queue)\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet TX rate limitation for queue of a port ID:\n\nset port (port_id) queue (queue_id) rate (rate_value)\n\nset port - tx_rate (for VF)\n~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet TX rate limitation for queues in VF of a port ID:\n\nset port (port_id) vf (vf_id) rate (rate_value) queue_mask (queue_mask)\n\nset port - mirror rule\n~~~~~~~~~~~~~~~~~~~~~~\n\nSet pool or vlan type mirror rule for a port:\n\nset port (port_id) mirror-rule (rule_id) (pool-mirror-up|pool-mirror-down|vlan-mirror) (poolmask|vlanid[,vlanid]*) dst-pool (pool_id) (on|off)\n\nSet link mirror rule for a port:\n\nset port (port_id) mirror-rule (rule_id) (uplink-mirror|downlink-mirror) dst-pool (pool_id) (on|off)\n\nFor example to enable mirror traffic with vlan 0,1 to pool 0:\n\n.. code-block:: console\n\n set port 0 mirror-rule 0 vlan-mirror 0,1 dst-pool 0 on\n\nreset port - mirror rule\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nReset a mirror rule for a port.\n\nreset port (port_id) mirror-rule (rule_id)\n\nset flush_rx\n~~~~~~~~~~~~\n\nFlush (default) or don't flush RX streams before forwarding.\nMainly used with PCAP drivers to avoid the default behavior of flushing the first 512 packets on RX streams.\n\nset flush_rx off\n\nset bypass mode\n~~~~~~~~~~~~~~~\n\nSet the bypass mode for the lowest port on bypass enabled NIC.\n\nset bypass mode (normal|bypass|isolate) (port_id)\n\nset bypass event\n~~~~~~~~~~~~~~~~\n\nSet the event required to initiate specified bypass mode for the lowest port on a bypass enabled NIC where:\n\n* timeout: enable bypass after watchdog timeout.\n\n* os_on: enable bypass when OS/board is powered on.\n\n* os_off: enable bypass when OS/board is powered off.\n\n* power_on: enable bypass when power supply is turned on.\n\n* power_off: enable bypass when power supply is turned off.\n\nset bypass event (timeout|os_on|os_off|power_on|power_off) mode (normal|bypass|isolate) (port_id)\n\nset bypass timeout\n~~~~~~~~~~~~~~~~~~\n\nSet the bypass watchdog timeout to 'n' seconds where 0 = instant.\n\nset bypass timeout (0|1.5|2|3|4|8|16|32)\n\nshow bypass config\n~~~~~~~~~~~~~~~~~~\n\nShow the bypass configuration for a bypass enabled NIC using the lowest port on the NIC.\n\nshow bypass config (port_id)\n\nset link up\n~~~~~~~~~~~\n\nSet link up for a port.\n\nset link-up port (port id)\n\nset link down\n~~~~~~~~~~~~~\n\nSet link down for a port.\n\nset link-down port (port id)\n\nPort Functions\n--------------\n\nThe following sections show functions for configuring ports.\n\n.. note::\n\n Port configuration changes only become active when forwarding is started/restarted.\n\nport attach\n~~~~~~~~~~~\n\nAttach a port specified by pci address or virtual device args.\n\nTo attach a new pci device, the device should be recognized by kernel first.\nThen it should be moved under DPDK management.\nFinally the port can be attached to testpmd.\n\nFor example, to move a pci device using ixgbe under DPDK management:\n\n.. code-block:: console\n\n ./tools/dpdk_nic_bind.py --status\n\n Network devices using DPDK-compatible driver\n ============================================\n \n\n Network devices using kernel driver\n ===================================\n 0000:0a:00.0 '82599ES 10-Gigabit SFI/SFP+ Network Connection' if=eth2 drv=ixgbe unused=\n\n ./tools/dpdk_nic_bind.py -b igb_uio 0000:0a:00.0\n ./tools/dpdk_nic_bind.py --status\n\n Network devices using DPDK-compatible driver\n ============================================\n 0000:0a:00.0 '82599ES 10-Gigabit SFI/SFP+ Network Connection' drv=igb_uio unused=\n\nTo attach a port created by virtual device, above steps are not needed.\n\nport attach (identifier)\n\nFor example, to attach a port whose pci address is 0000:0a:00.0.\n\n.. code-block:: console\n\n testpmd> port attach 0000:0a:00.0\n Attaching a new port...\n EAL: PCI device 0000:0a:00.0 on NUMA socket -1\n EAL: probe driver: 8086:10fb rte_ixgbe_pmd\n EAL: PCI memory mapped at 0x7f83bfa00000\n EAL: PCI memory mapped at 0x7f83bfa80000\n PMD: eth_ixgbe_dev_init(): MAC: 2, PHY: 18, SFP+: 5\n PMD: eth_ixgbe_dev_init(): port 0 vendorID=0x8086 deviceID=0x10fb\n Port 0 is attached. Now total ports is 1\n Done\n testpmd>\n\nFor example, to attach a port created by pcap PMD.\n\n.. code-block:: console\n\n testpmd> port attach eth_pcap0\n Attaching a new port...\n PMD: Initializing pmd_pcap for eth_pcap0\n PMD: Creating pcap-backed ethdev on numa socket 0\n Port 0 is attached. Now total ports is 1\n Done\n testpmd>\n\nIn this case, identifier is \"eth_pcap0\".\nThis identifier format is the same as \"--vdev\" format of DPDK applications.\n\nFor example, to re-attach a bonded port which has been previously detached,\nthe mode and slave parameters must be given.\n\n.. code-block:: console\n\n testpmd> port attach eth_bond_testpmd_0,mode=0,slave=1\n Attaching a new port...\n EAL: Initializing pmd_bond for eth_bond_testpmd_0\n EAL: Create bonded device eth_bond_testpmd_0 on port 0 in mode 0 on socket 0.\n Port 0 is attached. Now total ports is 1\n Done\n\n\nport detach\n~~~~~~~~~~~\n\nDetach a specific port.\n\nBefore detaching a port, the port should be closed.\n\nport detach (port_id)\n\nFor example, to detach a pci device port 0.\n\n.. code-block:: console\n\n testpmd> port close 0\n Closing ports...\n Done\n testpmd> port detach 0\n Detaching a port...\n EAL: PCI device 0000:0a:00.0 on NUMA socket -1\n EAL: remove driver: 8086:10fb rte_ixgbe_pmd\n EAL: PCI memory unmapped at 0x7f83bfa00000\n EAL: PCI memory unmapped at 0x7f83bfa80000\n Done\n testpmd>\n\nFor example, to detach a virtual device port 0.\n\n.. code-block:: console\n\n testpmd> port close 0\n Closing ports...\n Done\n testpmd> port detach 0\n Detaching a port...\n PMD: Closing pcap ethdev on numa socket 0\n Port 'eth_pcap0' is detached. Now total ports is 0\n Done\n testpmd>\n\nTo remove a pci device completely from the system, first detach the port from testpmd.\nThen the device should be moved under kernel management.\nFinally the device can be removed using kernel pci hotplug functionality.\n\nFor example, to move a pci device under kernel management:\n\n.. code-block:: console\n\n ./tools/dpdk_nic_bind.py -b ixgbe 0000:0a:00.0\n ./tools/dpdk_nic_bind.py --status\n\n Network devices using DPDK-compatible driver\n ============================================\n \n\n Network devices using kernel driver\n ===================================\n 0000:0a:00.0 '82599ES 10-Gigabit SFI/SFP+ Network Connection' if=eth2 drv=ixgbe unused=igb_uio\n\nTo remove a port created by a virtual device, above steps are not needed.\n\nport start\n~~~~~~~~~~\n\nStart all ports or a specific port:\n\nport start (port_id|all)\n\nport stop\n~~~~~~~~~\n\nStop all ports or a specific port:\n\nport stop (port_id|all)\n\nport close\n~~~~~~~~~~\n\nClose all ports or a specific port:\n\nport close (port_id|all)\n\nport start/stop queue\n~~~~~~~~~~~~~~~~~~~~~\n\nStart/stop a rx/tx queue on a specific port:\n\nport (port_id) (rxq|txq) (queue_id) (start|stop)\n\nOnly take effect when port is started.\n\nport config - speed\n~~~~~~~~~~~~~~~~~~~\n\nSet the speed and duplex mode for all ports or a specific port:\n\nport config (port_id|all) speed (10|100|1000|10000|auto) duplex (half|full|auto)\n\nport config - queues/descriptors\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet number of queues/descriptors for rxq, txq, rxd and txd:\n\nport config all (rxq|txq|rxd|txd) (value)\n\nThis is equivalent to the --rxq, --txq, --rxd and --txd command-line options.\n\nport config - max-pkt-len\n~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet the maximum packet length:\n\nport config all max-pkt-len (value)\n\nThis is equivalent to the --max-pkt-len command-line option.\n\nport config - CRC Strip\n~~~~~~~~~~~~~~~~~~~~~~~\n\nSet hardware CRC stripping on or off for all ports:\n\nport config all crc-strip (on|off)\n\nCRC stripping is off by default.\n\nThe on option is equivalent to the --crc-strip command-line option.\n\nport config - RX Checksum\n~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet hardware RX checksum offload to on or off for all ports:\n\nport config all rx-cksum (on|off)\n\nChecksum offload is off by default.\n\nThe on option is equivalent to the --enable-rx-cksum command-line option.\n\nport config - VLAN\n~~~~~~~~~~~~~~~~~~\n\nSet hardware VLAN on or off for all ports:\n\nport config all hw-vlan (on|off)\n\nHardware VLAN is on by default.\n\nThe off option is equivalent to the --disable-hw-vlan command-line option.\n\nport config - VLAN filter\n~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet hardware VLAN filter on or off for all ports:\n\nport config all hw-vlan-filter (on|off)\n\nHardware VLAN filter is on by default.\n\nThe off option is equivalent to the --disable-hw-vlan-filter command-line option.\n\nport config - VLAN strip\n~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet hardware VLAN strip on or off for all ports:\n\nport config all hw-vlan-strip (on|off)\n\nHardware VLAN strip is on by default.\n\nThe off option is equivalent to the --disable-hw-vlan-strip command-line option.\n\nport config - VLAN extend\n~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet hardware VLAN extend on or off for all ports:\n\nport config all hw-vlan-extend (on|off)\n\nHardware VLAN extend is off by default.\n\nThe off option is equivalent to the --disable-hw-vlan-extend command-line option.\n\nport config - Drop Packets\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet packet drop for packets with no descriptors on or off for all ports:\n\nport config all drop-en (on|off)\n\nPacket dropping for packets with no descriptors is off by default.\n\nThe on option is equivalent to the --enable-drop-en command-line option.\n\nport config - RSS\n~~~~~~~~~~~~~~~~~\n\nSet the RSS (Receive Side Scaling) mode on or off:\n\nport config all rss (all|ip|tcp|udp|sctp|ether|none)\n\nRSS is on by default.\n\nThe off option is equivalent to the --disable-rss command-line option.\n\nport config - RSS Reta\n~~~~~~~~~~~~~~~~~~~~~~\n\nSet the RSS (Receive Side Scaling) redirection table:\n\nport config all rss reta (hash,queue)[,(hash,queue)]\n\nport config - DCB\n~~~~~~~~~~~~~~~~~\n\nSet the DCB mode for an individual port:\n\nport config (port_id) dcb vt (on|off) (traffic_class) pfc (on|off)\n\nThe traffic class should be 4 or 8.\n\nport config - Burst\n~~~~~~~~~~~~~~~~~~~\n\nSet the number of packets per burst:\n\nport config all burst (value)\n\nThis is equivalent to the --burst command-line option.\n\nport config - Threshold\n~~~~~~~~~~~~~~~~~~~~~~~\n\nSet thresholds for TX/RX queues:\n\nport config all (threshold) (value)\n\nWhere the threshold type can be:\n\n* txpt: Set the prefetch threshold register of the TX rings, 0 <= value <= 255.\n\n* txht: Set the host threshold register of the TX rings, 0 <= value <= 255.\n\n* txwt: Set the write-back threshold register of the TX rings, 0 <= value <= 255.\n\n* rxpt: Set the prefetch threshold register of the RX rings, 0 <= value <= 255.\n\n* rxht: Set the host threshold register of the RX rings, 0 <= value <= 255.\n\n* rxwt: Set the write-back threshold register of the RX rings, 0 <= value <= 255.\n\n* txfreet: Set the transmit free threshold of the TX rings, 0 <= value <= txd.\n\n* rxfreet: Set the transmit free threshold of the RX rings, 0 <= value <= rxd.\n\n* txrst: Set the transmit RS bit threshold of TX rings, 0 <= value <= txd.\n These threshold options are also available from the command-line.\n\nLink Bonding Functions\n----------------------\n\nThe Link Bonding functions make it possible to dynamically create and\nmanage link bonding devices from within testpmd interactive prompt.\n\ncreate bonded device\n~~~~~~~~~~~~~~~~~~~~\n\nCreate a new bonding device:\n\ncreate bonded device (mode) (socket)\n\nFor example, to create a bonded device in mode 1 on socket 0.\n\n.. code-block:: console\n\n testpmd> create bonded 1 0\n created new bonded device (port X)\n\nadd bonding slave\n~~~~~~~~~~~~~~~~~\n\nAdds Ethernet device to a Link Bonding device:\n\nadd bonding slave (slave id) (port id)\n\nFor example, to add Ethernet device (port 6) to a Link Bonding device (port 10).\n\n.. code-block:: console\n\n testpmd> add bonding slave 6 10\n\n\nremove bonding slave\n~~~~~~~~~~~~~~~~~~~~\n\nRemoves an Ethernet slave device from a Link Bonding device:\n\nremove bonding slave (slave id) (port id)\n\nFor example, to remove Ethernet slave device (port 6) to a Link Bonding device (port 10).\n\n.. code-block:: console\n\n testpmd> remove bonding slave 6 10\n\nset bonding mode\n~~~~~~~~~~~~~~~~\n\nSet the Link Bonding mode of a Link Bonding device:\n\nset bonding mode (value) (port id)\n\nFor example, to set the bonding mode of a Link Bonding device (port 10) to broadcast (mode 3).\n\n.. code-block:: console\n\n testpmd> set bonding mode 3 10\n\nset bonding primary\n~~~~~~~~~~~~~~~~~~~\n\nSet an Ethernet slave device as the primary device on a Link Bonding device:\n\nset bonding primary (slave id) (port id)\n\nFor example, to set the Ethernet slave device (port 6) as the primary port of a Link Bonding device (port 10).\n\n.. code-block:: console\n\n testpmd> set bonding primary 6 10\n\nset bonding mac\n~~~~~~~~~~~~~~~\n\nSet the MAC address of a Link Bonding device:\n\nset bonding mac (port id) (mac)\n\nFor example, to set the MAC address of a Link Bonding device (port 10) to 00:00:00:00:00:01\n\n.. code-block:: console\n\n testpmd> set bonding mac 10 00:00:00:00:00:01\n\nset bonding xmit_balance_policy\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet the transmission policy for a Link Bonding device when it is in Balance XOR mode:\n\nset bonding xmit_balance_policy (port_id) (l2|l23|l34)\n\nFor example, set a Link Bonding device (port 10) to use a balance policy of layer 3+4 (IP addresses & UDP ports )\n\n.. code-block:: console\n\n testpmd> set bonding xmit_balance_policy 10 l34\n\n\nset bonding mon_period\n~~~~~~~~~~~~~~~~~~~~~~\n\nSet the link status monitoring polling period in milliseconds for a bonding device.\n\nThis adds support for PMD slave devices which do not support link status interrupts.\nWhen the mon_period is set to a value greater than 0 then all PMD's which do not support\nlink status ISR will be queried every polling interval to check if their link status has changed.\n\nset bonding mon_period (port_id) (value)\n\nFor example, to set the link status monitoring polling period of bonded device (port 5) to 150ms\n\n.. code-block:: console\n\n testpmd> set bonding mon_period 5 150\n\n\nshow bonding config\n~~~~~~~~~~~~~~~~~~~\n\nShow the current configuration of a Link Bonding device:\n\nshow bonding config (port id)\n\nFor example,\nto show the configuration a Link Bonding device (port 9) with 3 slave devices (1, 3, 4)\nin balance mode with a transmission policy of layer 2+3.\n\n.. code-block:: console\n\n testpmd> show bonding config 9\n Bonding mode: 2\n Balance Xmit Policy: BALANCE_XMIT_POLICY_LAYER23\n Slaves (3): [1 3 4]\n Active Slaves (3): [1 3 4]\n Primary: [3]\n\nRegister Functions\n------------------\n\nThe Register functions can be used to read from and write to registers on the network card referenced by a port number.\nThis is mainly useful for debugging purposes.\nReference should be made to the appropriate datasheet for the network card for details on the register addresses\nand fields that can be accessed.\n\nread reg\n~~~~~~~~\n\nDisplay the value of a port register:\n\nread reg (port_id) (address)\n\nFor example, to examine the Flow Director control register (FDIRCTL, 0x0000EE000) on an Intel® 82599 10 GbE Controller:\n\n.. code-block:: console\n\n testpmd> read reg 0 0xEE00\n port 0 PCI register at offset 0xEE00: 0x4A060029 (1241907241)\n\nread regfield\n~~~~~~~~~~~~~\n\nDisplay a port register bit field:\n\nread regfield (port_id) (address) (bit_x) (bit_y)\n\nFor example, reading the lowest two bits from the register in the example above:\n\n.. code-block:: console\n\n testpmd> read regfield 0 0xEE00 0 1\n port 0 PCI register at offset 0xEE00: bits[0, 1]=0x1 (1)\n\nread regbit\n~~~~~~~~~~~\n\nDisplay a single port register bit:\n\nread regbit (port_id) (address) (bit_x)\n\nFor example, reading the lowest bit from the register in the example above:\n\n.. code-block:: console\n\n testpmd> read regbit 0 0xEE00 0\n port 0 PCI register at offset 0xEE00: bit 0=1\n\nwrite reg\n~~~~~~~~~\n\nSet the value of a port register:\n\nwrite reg (port_id) (address) (value)\n\nFor example, to clear a register:\n\n.. code-block:: console\n\n testpmd> write reg 0 0xEE00 0x0\n port 0 PCI register at offset 0xEE00: 0x00000000 (0)\n\nwrite regfield\n~~~~~~~~~~~~~~\n\nSet bit field of a port register:\n\nwrite regfield (port_id) (address) (bit_x) (bit_y) (value)\n\nFor example, writing to the register cleared in the example above:\n\n.. code-block:: console\n\n testpmd> write regfield 0 0xEE00 0 1 2\n port 0 PCI register at offset 0xEE00: 0x00000002 (2)\n\nwrite regbit\n~~~~~~~~~~~~\n\nSet single bit value of a port register:\n\nwrite regbit (port_id) (address) (bit_x) (value)\n\nFor example, to set the high bit in the register from the example above:\n\n.. code-block:: console\n\n testpmd> write regbit 0 0xEE00 31 1\n port 0 PCI register at offset 0xEE00: 0x8000000A (2147483658)\n\nFilter Functions\n----------------\n\nThis section details the available filter functions that are available.\n\nethertype_filter\n~~~~~~~~~~~~~~~~~~~~\n\nAdd or delete a L2 Ethertype filter, which identify packets by their L2 Ethertype mainly assign them to a receive queue.\n\nethertype_filter (port_id) (add|del) (mac_addr|mac_ignr) (mac_address) ethertype (ether_type) (drop|fwd) queue (queue_id)\n\nThe available information parameters are:\n\n* port_id: the port which the Ethertype filter assigned on.\n\n* mac_addr: compare destination mac address.\n\n* mac_ignr: ignore destination mac address match.\n\n* mac_address: destination mac address to match.\n\n* ether_type: the EtherType value want to match,\n for example 0x0806 for ARP packet. 0x0800 (IPv4) and 0x86DD (IPv6) are invalid.\n\n* queue_id : The receive queue associated with this EtherType filter. It is meaningless when deleting or dropping.\n\nExample, to add/remove an ethertype filter rule:\n\n.. code-block:: console\n\n testpmd> ethertype_filter 0 add mac_ignr ethertype 0x0806 fwd queue 3\n testpmd> ethertype_filter 0 del mac_ignr ethertype 0x0806 fwd queue 3\n\n2tuple_filter\n~~~~~~~~~~~~~~~~~\n\nAdd or delete a 2-tuple filter,\nwhich identify packets by specific protocol and destination TCP/UDP port\nand forwards packets into one of the receive queues.\n\n2tuple_filter (port_id) (add|del) dst_port (dst_port_value) protocol (protocol_value)\nmask (mask_value) tcp_flags (tcp_flags_value) priority (prio_value) queue (queue_id)\n\nThe available information parameters are:\n\n* port_id: the port which the 2-tuple filter assigned on.\n\n* dst_port_value: destination port in L4.\n\n* protocol_value: IP L4 protocol.\n\n* mask_value: participates in the match or not by bit for field above, 1b means participate.\n\n* tcp_flags_value: TCP control bits. The non-zero value is invalid, when the pro_value is not set to 0x06 (TCP).\n\n* prio_value: priority of this filter.\n\n* queue_id: The receive queue associated with this 2-tuple filter.\n\nExample, to add/remove an 2tuple filter rule:\n\n.. code-block:: console\n\n testpmd> 2tuple_filter 0 add dst_port 32 protocol 0x06 mask 0x03 tcp_flags 0x02 priority 3 queue 3\n testpmd> 2tuple_filter 0 del dst_port 32 protocol 0x06 mask 0x03 tcp_flags 0x02 priority 3 queue 3\n\n5tuple_filter\n~~~~~~~~~~~~~~~~~\n\nAdd or delete a 5-tuple filter,\nwhich consists of a 5-tuple (protocol, source and destination IP addresses, source and destination TCP/UDP/SCTP port)\nand routes packets into one of the receive queues.\n\n5tuple_filter (port_id) (add|del) dst_ip (dst_address) src_ip (src_address) dst_port (dst_port_value) src_port (src_port_value)\nprotocol (protocol_value) mask (mask_value) tcp_flags (tcp_flags_value) priority (prio_value) queue (queue_id)\n\nThe available information parameters are:\n\n* port_id: the port which the 5-tuple filter assigned on.\n\n* dst_address: destination IP address.\n\n* src_address: source IP address.\n\n* dst_port_value: TCP/UDP destination port.\n\n* src_port_value: TCP/UDP source port.\n\n* protocol_value: L4 protocol.\n\n* mask_value: participates in the match or not by bit for field above, 1b means participate\n\n* tcp_flags_value: TCP control bits. The non-zero value is invalid, when the protocol_value is not set to 0x06 (TCP).\n\n* prio_value: the priority of this filter.\n\n* queue_id: The receive queue associated with this 5-tuple filter.\n\nExample, to add/remove an 5tuple filter rule:\n\n.. code-block:: console\n\n testpmd> 5tuple_filter 0 add dst_ip 2.2.2.5 src_ip 2.2.2.4 dst_port 64 src_port 32 protocol 0x06 mask 0x1F flags 0x0 priority 3 queue 3\n testpmd> 5tuple_filter 0 del dst_ip 2.2.2.5 src_ip 2.2.2.4 dst_port 64 src_port 32 protocol 0x06 mask 0x1F flags 0x0 priority 3 queue 3\n\nsyn_filter\n~~~~~~~~~~~~~~\n\nBy SYN filter, TCP packets whose *SYN* flag is set can be forwarded to a separate queue.\n\nsyn_filter (port_id) (add|del) priority (high|low) queue (queue_id)\n\nThe available information parameters are:\n\n* port_id: the port which the SYN filter assigned on.\n\n* high: this SYN filter has higher priority than other filters.\n\n* low: this SYN filter has lower priority than other filters.\n\n* queue_id: The receive queue associated with this SYN filter\n\nExample:\n\n.. code-block:: console\n\n testpmd> syn_filter 0 add priority high queue 3\n\nflex_filter\n~~~~~~~~~~~\n\nWith flex filter, packets can be recognized by any arbitrary pattern within the first 128 bytes of the packet\nand routes packets into one of the receive queues.\n\nflex_filter (port_id) (add|del) len (len_value) bytes (bytes_value)\nmask (mask_value) priority (prio_value) queue (queue_id)\n\nThe available information parameters are:\n\n* port_id: the port which the Flex filter is assigned on.\n\n* len_value: filter length in bytes, no greater than 128.\n\n* bytes_value: a string in hexadecimal, means the value the flex filter needs to match.\n\n* mask_value: a string in hexadecimal, bit 1 means corresponding byte participates in the match.\n\n* prio_value: the priority of this filter.\n\n* queue_id: the receive queue associated with this Flex filter.\n\nExample:\n\n.. code-block:: console\n\n testpmd> flex_filter 0 add len 16 bytes 0x00000000000000000000000008060000\n mask 000C priority 3 queue 3\n\n testpmd> flex_filter 0 del len 16 bytes 0x00000000000000000000000008060000\n mask 000C priority 3 queue 3\n\nflow_director_filter\n~~~~~~~~~~~~~~~~~~~~\n\nThe Flow Director works in receive mode to identify specific flows or sets of flows and route them to specific queues.\n\nTwo types of filtering are supported which are referred to as Perfect Match and Signature filters, the match mode\nis set by the --pkt-filter-mode command-line parameter:\n\n* Perfect match filters.\n The hardware checks a match between the masked fields of the received packets and the programmed filters.\n\n* Signature filters.\n The hardware checks a match between a hash-based signature of the masked fields of the received packet.\n\nThe Flow Director filters can match the different fields for different type of packet: flow type, specific input set\nper flow type and the flexible payload. The Flow Director can also mask out parts of all of these fields so that filters\nare only applied to certain fields or parts of the fields.\n\nDifferent NICs may have different capabilities, command show port fdir (port_id) can be used to acquire the information.\n\n# Commands to add flow director filters of different flow types.\n\nflow_director_filter (port_id) (add|del|update) flow (ipv4-other|ipv4-frag|ipv6-other|ipv6-frag)\nsrc (src_ip_address) dst (dst_ip_address) vlan (vlan_value) flexbytes (flexbytes_value)\n(drop|fwd) queue (queue_id) fd_id (fd_id_value)\n\nflow_director_filter (port_id) (add|del|update) flow (ipv4-tcp|ipv4-udp|ipv6-tcp|ipv6-udp)\nsrc (src_ip_address) (src_port) dst (dst_ip_address) (dst_port) vlan (vlan_value)\nflexbytes (flexbytes_value) (drop|fwd) queue (queue_id) fd_id (fd_id_value)\n\nflow_director_filter (port_id) (add|del|update) flow (ipv4-sctp|ipv6-sctp)\nsrc (src_ip_address) (src_port) dst (dst_ip_address) (dst_port) tag (verification_tag)\nvlan (vlan_value) flexbytes (flexbytes_value) (drop|fwd) queue (queue_id) fd_id (fd_id_value)\n\nflow_director_filter (port_id) (add|del|update) flow l2_payload\nether (ethertype) flexbytes (flexbytes_value) (drop|fwd) queue (queue_id) fd_id (fd_id_value)\n\nFor example, to add an ipv4-udp flow type filter:\n\n.. code-block:: console\n\n testpmd> flow_director_filter 0 add flow ipv4-udp src 2.2.2.3 32 dst 2.2.2.5 33 vlan 0x1 flexbytes (0x88,0x48) fwd queue 1 fd_id 1\n\nFor example, add an ipv4-other flow type filter:\n\n.. code-block:: console\n\n testpmd> flow_director_filter 0 add flow ipv4-other src 2.2.2.3 dst 2.2.2.5 vlan 0x1 flexbytes (0x88,0x48) fwd queue 1 fd_id 1\n\nflush_flow_director\n~~~~~~~~~~~~~~~~~~~\n\nflush all flow director filters on a device:\n\nflush_flow_director (port_id)\n\nExample, to flush all flow director filter on port 0:\n\n.. code-block:: console\n\n testpmd> flush_flow_director 0\n\nflow_director_mask\n~~~~~~~~~~~~~~~~~~\n\nset flow director's masks on match input set\n\nflow_director_mask (port_id) vlan (vlan_value) src_mask (ipv4_src) (ipv6_src) (src_port) dst_mask (ipv4_dst) (ipv6_dst) (dst_port)\n\nExample, to set flow director mask on port 0:\n\n.. code-block:: console\n\n testpmd> flow_director_mask 0 vlan 0xefff src_mask 255.255.255.255 FFFF:FFFF:FFFF:FFFF:FFFF:FFFF:FFFF:FFFF 0xFFFF dst_mask 255.255.255.255 FFFF:FFFF:FFFF:FFFF:FFFF:FFFF:FFFF:FFFF 0xFFFF\n\n\nflow_director_flex_mask\n~~~~~~~~~~~~~~~~~~~~~~~\n\nset masks of flow director's flexible payload based on certain flow type:\n\nflow_director_flex_mask (port_id) flow (none|ipv4-other|ipv4-frag|ipv4-tcp|ipv4-udp|ipv4-sctp|\nipv6-other|ipv6-frag|ipv6-tcp|ipv6-udp|ipv6-sctp|l2_payload|all) (mask)\n\nExample, to set flow director's flex mask for all flow type on port 0:\n\n.. code-block:: console\n\n testpmd> flow_director_flex_mask 0 flow all (0xff,0xff,0,0,0,0,0,0,0,0,0,0,0,0,0,0)\n\n\nflow_director_flex_payload\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nConfigure flexible payload selection.\n\nflow_director_flex_payload (port_id) (raw|l2|l3|l4) (config)\n\nFor example, to select the first 16 bytes from the offset 4 (bytes) of packet's payload as flexible payload.\n\n.. code-block:: console\n\n testpmd> flow_director_flex_payload 0 l4 (4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19)\n\nget_sym_hash_ena_per_port\n~~~~~~~~~~~~~~~~~~~~~~~~~\n\nGet symmetric hash enable configuration per port.\n\nget_sym_hash_ena_per_port (port_id)\n\nFor example, to get symmetric hash enable configuration of port 1.\n\n.. code-block:: console\n\n testpmd> get_sym_hash_ena_per_port 1\n\nset_sym_hash_ena_per_port\n~~~~~~~~~~~~~~~~~~~~~~~~~\n\nSet symmetric hash enable configuration per port to enable or disable.\n\nset_sym_hash_ena_per_port (port_id) (enable|disable)\n\nFor example, to set symmetric hash enable configuration of port 1 to enable.\n\n.. code-block:: console\n\n testpmd> set_sym_hash_ena_per_port 1 enable\n\nget_hash_global_config\n~~~~~~~~~~~~~~~~~~~~~~\n\nGet the global configurations of hash filters.\n\nget_hash_global_config (port_id)\n\nFor example, to get the global configurations of hash filters of port 1.\n\n.. code-block:: console\n\n testpmd> get_hash_global_config 1\n\nset_hash_global_config\n~~~~~~~~~~~~~~~~~~~~~~\n\nSet the global configurations of hash filters.\n\nset_hash_global_config (port_id) (toeplitz|simple_xor|default)\n(ipv4|ipv4-frag|ipv4-tcp|ipv4-udp|ipv4-sctp|ipv4-other|ipv6|ipv6-frag|ipv6-tcp|ipv6-udp|ipv6-sctp|ipv6-other|l2_payload)\n(enable|disable)\n\nFor example, to enable simple_xor for flow type of ipv6 on port 2.\n\n.. code-block:: console\n\n testpmd> set_hash_global_config 2 simple_xor ipv6 enable\n" }, { "path": "doc/guides/xen/index.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nXen Guide\n=========\n\n|today|\n\n**Contents**\n\n.. toctree::\n :maxdepth: 2\n :numbered:\n\n pkt_switch\n" }, { "path": "doc/guides/xen/pkt_switch.rst", "content": ".. BSD LICENSE\n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n\n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nDPDK Xen Based Packet-Switching Solution\n========================================\n\nIntroduction\n------------\n\nDPDK provides a para-virtualization packet switching solution, based on the Xen hypervisor's Grant Table, Note 1,\nwhich provides simple and fast packet switching capability between guest domains and host domain based on MAC address or VLAN tag.\n\nThis solution is comprised of two components;\na Poll Mode Driver (PMD) as the front end in the guest domain and a switching back end in the host domain.\nXenStore is used to exchange configure information between the PMD front end and switching back end,\nincluding grant reference IDs for shared Virtio RX/TX rings,\nMAC address, device state, and so on. XenStore is an information storage space shared between domains,\nsee further information on XenStore below.\n\nThe front end PMD can be found in the DPDK directory lib/ librte_pmd_xenvirt and back end example in examples/vhost_xen.\n\nThe PMD front end and switching back end use shared Virtio RX/TX rings as para- virtualized interface.\nThe Virtio ring is created by the front end, and Grant table references for the ring are passed to host.\nThe switching back end maps those grant table references and creates shared rings in a mapped address space.\n\nThe following diagram describes the functionality of the DPDK Xen Packet- Switching Solution.\n\n\n.. _figure_dpdk_xen_pkt_switch:\n\n.. figure:: img/dpdk_xen_pkt_switch.*\n\n Functionality of the DPDK Xen Packet Switching Solution.\n\n\nNote 1 The Xen hypervisor uses a mechanism called a Grant Table to share memory between domains\n(`http://wiki.xen.org/wiki/Grant Table `_).\n\nA diagram of the design is shown below, where \"gva\" is the Guest Virtual Address,\nwhich is the data pointer of the mbuf, and \"hva\" is the Host Virtual Address:\n\n\n.. _figure_grant_table:\n\n.. figure:: img/grant_table.*\n\n DPDK Xen Layout\n\n\nIn this design, a Virtio ring is used as a para-virtualized interface for better performance over a Xen private ring\nwhen packet switching to and from a VM.\nThe additional performance is gained by avoiding a system call and memory map in each memory copy with a XEN private ring.\n\nDevice Creation\n---------------\n\nPoll Mode Driver Front End\n~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n* Mbuf pool allocation:\n\n To use a Xen switching solution, the DPDK application should use rte_mempool_gntalloc_create()\n to reserve mbuf pools during initialization.\n rte_mempool_gntalloc_create() creates a mempool with objects from memory allocated and managed via gntalloc/gntdev.\n\n The DPDK now supports construction of mempools from allocated virtual memory through the rte_mempool_xmem_create() API.\n\n This front end constructs mempools based on memory allocated through the xen_gntalloc driver.\n rte_mempool_gntalloc_create() allocates Grant pages, maps them to continuous virtual address space,\n and calls rte_mempool_xmem_create() to build mempools.\n The Grant IDs for all Grant pages are passed to the host through XenStore.\n\n* Virtio Ring Creation:\n\n The Virtio queue size is defined as 256 by default in the VQ_DESC_NUM macro.\n Using the queue setup function,\n Grant pages are allocated based on ring size and are mapped to continuous virtual address space to form the Virtio ring.\n Normally, one ring is comprised of several pages.\n Their Grant IDs are passed to the host through XenStore.\n\n There is no requirement that this memory be physically continuous.\n\n* Interrupt and Kick:\n\n There are no interrupts in DPDK Xen Switching as both front and back ends work in polling mode.\n There is no requirement for notification.\n\n* Feature Negotiation:\n\n Currently, feature negotiation through XenStore is not supported.\n\n* Packet Reception & Transmission:\n\n With mempools and Virtio rings created, the front end can operate Virtio devices,\n as it does in Virtio PMD for KVM Virtio devices with the exception that the host\n does not require notifications or deal with interrupts.\n\nXenStore is a database that stores guest and host information in the form of (key, value) pairs.\nThe following is an example of the information generated during the startup of the front end PMD in a guest VM (domain ID 1):\n\n.. code-block:: console\n\n xenstore -ls /local/domain/1/control/dpdk\n 0_mempool_gref=\"3042,3043,3044,3045\"\n 0_mempool_va=\"0x7fcbc6881000\"\n 0_tx_vring_gref=\"3049\"\n 0_rx_vring_gref=\"3053\"\n 0_ether_addr=\"4e:0b:d0:4e:aa:f1\"\n 0_vring_flag=\"3054\"\n ...\n\nMultiple mempools and multiple Virtios may exist in the guest domain, the first number is the index, starting from zero.\n\nThe idx#_mempool_va stores the guest virtual address for mempool idx#.\n\nThe idx#_ether_adder stores the MAC address of the guest Virtio device.\n\nFor idx#_rx_ring_gref, idx#_tx_ring_gref, and idx#_mempool_gref, the value is a list of Grant references.\nTake idx#_mempool_gref node for example, the host maps those Grant references to a continuous virtual address space.\nThe real Grant reference information is stored in this virtual address space,\nwhere (gref, pfn) pairs follow each other with -1 as the terminator.\n\n\n.. _figure_grant_refs:\n\n.. figure:: img/grant_refs.*\n\n Mapping Grant references to a continuous virtual address space\n\n\nAfter all gref# IDs are retrieved, the host maps them to a continuous virtual address space.\nWith the guest mempool virtual address, the host establishes 1:1 address mapping.\nWith multiple guest mempools, the host establishes multiple address translation regions.\n\nSwitching Back End\n~~~~~~~~~~~~~~~~~~\n\nThe switching back end monitors changes in XenStore.\nWhen the back end detects that a new Virtio device has been created in a guest domain, it will:\n\n#. Retrieve Grant and configuration information from XenStore.\n\n#. Map and create a Virtio ring.\n\n#. Map mempools in the host and establish address translation between the guest address and host address.\n\n#. Select a free VMDQ pool, set its affinity with the Virtio device, and set the MAC/ VLAN filter.\n\nPacket Reception\n~~~~~~~~~~~~~~~~\n\nWhen packets arrive from an external network, the MAC?VLAN filter classifies packets into queues in one VMDQ pool.\nAs each pool is bonded to a Virtio device in some guest domain, the switching back end will:\n\n#. Fetch an available entry from the Virtio RX ring.\n\n#. Get gva, and translate it to hva.\n\n#. Copy the contents of the packet to the memory buffer pointed to by gva.\n\nThe DPDK application in the guest domain, based on the PMD front end,\nis polling the shared Virtio RX ring for available packets and receives them on arrival.\n\nPacket Transmission\n~~~~~~~~~~~~~~~~~~~\n\nWhen a Virtio device in one guest domain is to transmit a packet,\nit puts the virtual address of the packet's data area into the shared Virtio TX ring.\n\nThe packet switching back end is continuously polling the Virtio TX ring.\nWhen new packets are available for transmission from a guest, it will:\n\n#. Fetch an available entry from the Virtio TX ring.\n\n#. Get gva, and translate it to hva.\n\n#. Copy the packet from hva to the host mbuf's data area.\n\n#. Compare the destination MAC address with all the MAC addresses of the Virtio devices it manages.\n If a match exists, it directly copies the packet to the matched VIrtio RX ring.\n Otherwise, it sends the packet out through hardware.\n\n.. note::\n\n The packet switching back end is for demonstration purposes only.\n The user could implement their switching logic based on this example.\n In this example, only one physical port on the host is supported.\n Multiple segments are not supported. The biggest mbuf supported is 4KB.\n When the back end is restarted, all front ends must also be restarted.\n\nRunning the Application\n-----------------------\n\nThe following describes the steps required to run the application.\n\nValidated Environment\n~~~~~~~~~~~~~~~~~~~~~\n\nHost:\n\n Xen-hypervisor: 4.2.2\n\n Distribution: Fedora release 18\n\n Kernel: 3.10.0\n\n Xen development package (including Xen, Xen-libs, xen-devel): 4.2.3\n\nGuest:\n\n Distribution: Fedora 16 and 18\n\n Kernel: 3.6.11\n\nXen Host Prerequisites\n~~~~~~~~~~~~~~~~~~~~~~\n\nNote that the following commands might not be the same on different Linux* distributions.\n\n* Install xen-devel package:\n\n .. code-block:: console\n\n yum install xen-devel.x86_64\n\n* Start xend if not already started:\n\n .. code-block:: console\n\n /etc/init.d/xend start\n\n* Mount xenfs if not already mounted:\n\n .. code-block:: console\n\n mount -t xenfs none /proc/xen\n\n* Enlarge the limit for xen_gntdev driver:\n\n .. code-block:: console\n\n modprobe -r xen_gntdev\n modprobe xen_gntdev limit=1000000\n\n.. note::\n\n The default limit for earlier versions of the xen_gntdev driver is 1024.\n That is insufficient to support the mapping of multiple Virtio devices into multiple VMs,\n so it is necessary to enlarge the limit by reloading this module.\n The default limit of recent versions of xen_gntdev is 1048576.\n The rough calculation of this limit is:\n\n limit=nb_mbuf# * VM#.\n\n In DPDK examples, nb_mbuf# is normally 8192.\n\nBuilding and Running the Switching Backend\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n#. Edit config/common_linuxapp, and change the default configuration value for the following two items:\n\n .. code-block:: console\n\n CONFIG_RTE_LIBRTE_XEN_DOM0=y\n CONFIG RTE_LIBRTE_PMD_XENVIRT=n\n\n#. Build the target:\n\n .. code-block:: console\n\n make install T=x86_64-native-linuxapp-gcc\n\n#. Ensure that RTE_SDK and RTE_TARGET are correctly set. Build the switching example:\n\n .. code-block:: console\n\n make -C examples/vhost_xen/\n\n#. Load the Xen DPDK memory management module and preallocate memory:\n\n .. code-block:: console\n\n insmod ./x86_64-native-linuxapp-gcc/build/lib/librte_eal/linuxapp/xen_dom0/rte_dom0_mm.ko\n echo 2048> /sys/kernel/mm/dom0-mm/memsize-mB/memsize\n\n .. note::\n\n On Xen Dom0, there is no hugepage support.\n Under Xen Dom0, the DPDK uses a special memory management kernel module\n to allocate chunks of physically continuous memory.\n Refer to the *DPDK Getting Started Guide* for more information on memory management in the DPDK.\n In the above command, 4 GB memory is reserved (2048 of 2 MB pages) for DPDK.\n\n#. Load uio_pci_generic and bind one Intel NIC controller to it:\n\n .. code-block:: console\n\n modprobe uio_pci_generic\n python tools/dpdk_nic_bind.py -b uio_pci_generic 0000:09:00:00.0\n\n In this case, 0000:09:00.0 is the PCI address for the NIC controller.\n\n#. Run the switching back end example:\n\n .. code-block:: console\n\n examples/vhost_xen/build/vhost-switch -c f -n 3 --xen-dom0 -- -p1\n\n.. note::\n\n The -xen-dom0 option instructs the DPDK to use the Xen kernel module to allocate memory.\n\nOther Parameters:\n\n* -vm2vm\n\n The vm2vm parameter enables/disables packet switching in software.\n Disabling vm2vm implies that on a VM packet transmission will always go to the Ethernet port\n and will not be switched to another VM\n\n* -Stats\n\n The Stats parameter controls the printing of Virtio-net device statistics.\n The parameter specifies the interval (in seconds) at which to print statistics,\n an interval of 0 seconds will disable printing statistics.\n\nXen PMD Frontend Prerequisites\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n#. Install xen-devel package for accessing XenStore:\n\n .. code-block:: console\n\n yum install xen-devel.x86_64\n\n#. Mount xenfs, if it is not already mounted:\n\n .. code-block:: console\n\n mount -t xenfs none /proc/xen\n\n#. Enlarge the default limit for xen_gntalloc driver:\n\n .. code-block:: console\n\n modprobe -r xen_gntalloc\n modprobe xen_gntalloc limit=6000\n\n.. note::\n\n Before the Linux kernel version 3.8-rc5, Jan 15th 2013,\n a critical defect occurs when a guest is heavily allocating Grant pages.\n The Grant driver allocates fewer pages than expected which causes kernel memory corruption.\n This happens, for example, when a guest uses the v1 format of a Grant table entry and allocates\n more than 8192 Grant pages (this number might be different on different hypervisor versions).\n To work around this issue, set the limit for gntalloc driver to 6000.\n (The kernel normally allocates hundreds of Grant pages with one Xen front end per virtualized device).\n If the kernel allocates a lot of Grant pages, for example, if the user uses multiple net front devices,\n it is best to upgrade the Grant alloc driver.\n This defect has been fixed in kernel version 3.8-rc5 and later.\n\nBuilding and Running the Front End\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\n#. Edit config/common_linuxapp, and change the default configuration value:\n\n .. code-block:: console\n\n CONFIG_RTE_LIBRTE_XEN_DOM0=n\n CONFIG_RTE_LIBRTE_PMD_XENVIRT=y\n\n#. Build the package:\n\n .. code-block:: console\n\n make install T=x86_64-native-linuxapp-gcc\n\n#. Enable hugepages. Refer to the *DPDK Getting Started Guide* for instructions on\n how to use hugepages in the DPDK.\n\n#. Run TestPMD. Refer to *DPDK TestPMD Application User Guide* for detailed parameter usage.\n\n .. code-block:: console\n\n ./x86_64-native-linuxapp-gcc/app/testpmd -c f -n 4 --vdev=\"eth_xenvirt0,mac=00:00:00:00:00:11\"\n testpmd>set fwd mac\n testpmd>start\n\n As an example to run two TestPMD instances over 2 Xen Virtio devices:\n\n .. code-block:: console\n\n --vdev=\"eth_xenvirt0,mac=00:00:00:00:00:11\" --vdev=\"eth_xenvirt1;mac=00:00:00:00:00:22\"\n\n\nUsage Examples: Injecting a Packet Stream Using a Packet Generator\n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n\nLoopback Mode\n^^^^^^^^^^^^^\n\nRun TestPMD in a guest VM:\n\n.. code-block:: console\n\n ./x86_64-native-linuxapp-gcc/app/testpmd -c f -n 4 --vdev=\"eth_xenvirt0,mac=00:00:00:00:00:11\" -- -i --eth-peer=0,00:00:00:00:00:22\n testpmd> set fwd mac\n testpmd> start\n\nExample output of the vhost_switch would be:\n\n.. code-block:: console\n\n DATA:(0) MAC_ADDRESS 00:00:00:00:00:11 and VLAN_TAG 1000 registered.\n\nThe above message indicates that device 0 has been registered with MAC address 00:00:00:00:00:11 and VLAN tag 1000.\nAny packets received on the NIC with these values is placed on the device's receive queue.\n\nConfigure a packet stream in the packet generator, set the destination MAC address to 00:00:00:00:00:11, and VLAN to 1000,\nthe guest Virtio receives these packets and sends them out with destination MAC address 00:00:00:00:00:22.\n\nInter-VM Mode\n^^^^^^^^^^^^^\n\nRun TestPMD in guest VM1:\n\n.. code-block:: console\n\n ./x86_64-native-linuxapp-gcc/app/testpmd -c f -n 4 --vdev=\"eth_xenvirt0,mac=00:00:00:00:00:11\" -- -i --eth-peer=0,00:00:00:00:00:22 -- -i\n\nRun TestPMD in guest VM2:\n\n.. code-block:: console\n\n ./x86_64-native-linuxapp-gcc/app/testpmd -c f -n 4 --vdev=\"eth_xenvirt0,mac=00:00:00:00:00:22\" -- -i --eth-peer=0,00:00:00:00:00:33\n\nConfigure a packet stream in the packet generator, and set the destination MAC address to 00:00:00:00:00:11 and VLAN to 1000.\nThe packets received in Virtio in guest VM1 will be forwarded to Virtio in guest VM2 and\nthen sent out through hardware with destination MAC address 00:00:00:00:00:33.\n\nThe packet flow is:\n\npacket generator->Virtio in guest VM1->switching backend->Virtio in guest VM2->switching backend->wire\n" }, { "path": "drivers/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nDIRS-y += net\n\ninclude $(RTE_SDK)/mk/rte.subdir.mk\n" }, { "path": "drivers/net/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nDIRS-$(CONFIG_RTE_LIBRTE_PMD_AF_PACKET) += af_packet\nDIRS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x\nDIRS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += bonding\nDIRS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += cxgbe\nDIRS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000\nDIRS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += enic\nDIRS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k\nDIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e\nDIRS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe\nDIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += mlx4\nDIRS-$(CONFIG_RTE_LIBRTE_MPIPE_PMD) += mpipe\nDIRS-$(CONFIG_RTE_LIBRTE_PMD_NULL) += null\nDIRS-$(CONFIG_RTE_LIBRTE_PMD_PCAP) += pcap\nDIRS-$(CONFIG_RTE_LIBRTE_PMD_RING) += ring\nDIRS-$(CONFIG_RTE_LIBRTE_VIRTIO_PMD) += virtio\nDIRS-$(CONFIG_RTE_LIBRTE_VMXNET3_PMD) += vmxnet3\nDIRS-$(CONFIG_RTE_LIBRTE_PMD_XENVIRT) += xenvirt\n\ninclude $(RTE_SDK)/mk/rte.sharelib.mk\ninclude $(RTE_SDK)/mk/rte.subdir.mk\n" }, { "path": "drivers/net/af_packet/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2014 John W. Linville \n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# Copyright(c) 2014 6WIND S.A.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_af_packet.a\n\nEXPORT_MAP := rte_pmd_af_packet_version.map\n\nLIBABIVER := 1\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_AF_PACKET) += rte_eth_af_packet.c\n\n#\n# Export include files\n#\nSYMLINK-y-include += rte_eth_af_packet.h\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_AF_PACKET) += lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_AF_PACKET) += lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_AF_PACKET) += lib/librte_kvargs\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/af_packet/rte_eth_af_packet.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014 John W. Linville \n *\n * Originally based upon librte_pmd_pcap code:\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_eth_af_packet.h\"\n\n#define ETH_AF_PACKET_IFACE_ARG\t\t\"iface\"\n#define ETH_AF_PACKET_NUM_Q_ARG\t\t\"qpairs\"\n#define ETH_AF_PACKET_BLOCKSIZE_ARG\t\"blocksz\"\n#define ETH_AF_PACKET_FRAMESIZE_ARG\t\"framesz\"\n#define ETH_AF_PACKET_FRAMECOUNT_ARG\t\"framecnt\"\n\n#define DFLT_BLOCK_SIZE\t\t(1 << 12)\n#define DFLT_FRAME_SIZE\t\t(1 << 11)\n#define DFLT_FRAME_COUNT\t(1 << 9)\n\nstruct pkt_rx_queue {\n\tint sockfd;\n\n\tstruct iovec *rd;\n\tuint8_t *map;\n\tunsigned int framecount;\n\tunsigned int framenum;\n\n\tstruct rte_mempool *mb_pool;\n\n\tvolatile unsigned long rx_pkts;\n\tvolatile unsigned long err_pkts;\n};\n\nstruct pkt_tx_queue {\n\tint sockfd;\n\n\tstruct iovec *rd;\n\tuint8_t *map;\n\tunsigned int framecount;\n\tunsigned int framenum;\n\n\tvolatile unsigned long tx_pkts;\n\tvolatile unsigned long err_pkts;\n};\n\nstruct pmd_internals {\n\tunsigned nb_queues;\n\n\tint if_index;\n\tstruct ether_addr eth_addr;\n\n\tstruct tpacket_req req;\n\n\tstruct pkt_rx_queue rx_queue[RTE_PMD_AF_PACKET_MAX_RINGS];\n\tstruct pkt_tx_queue tx_queue[RTE_PMD_AF_PACKET_MAX_RINGS];\n};\n\nstatic const char *valid_arguments[] = {\n\tETH_AF_PACKET_IFACE_ARG,\n\tETH_AF_PACKET_NUM_Q_ARG,\n\tETH_AF_PACKET_BLOCKSIZE_ARG,\n\tETH_AF_PACKET_FRAMESIZE_ARG,\n\tETH_AF_PACKET_FRAMECOUNT_ARG,\n\tNULL\n};\n\nstatic const char *drivername = \"AF_PACKET PMD\";\n\nstatic struct rte_eth_link pmd_link = {\n\t.link_speed = 10000,\n\t.link_duplex = ETH_LINK_FULL_DUPLEX,\n\t.link_status = 0\n};\n\nstatic uint16_t\neth_af_packet_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n{\n\tunsigned i;\n\tstruct tpacket2_hdr *ppd;\n\tstruct rte_mbuf *mbuf;\n\tuint8_t *pbuf;\n\tstruct pkt_rx_queue *pkt_q = queue;\n\tuint16_t num_rx = 0;\n\tunsigned int framecount, framenum;\n\n\tif (unlikely(nb_pkts == 0))\n\t\treturn 0;\n\n\t/*\n\t * Reads the given number of packets from the AF_PACKET socket one by\n\t * one and copies the packet data into a newly allocated mbuf.\n\t */\n\tframecount = pkt_q->framecount;\n\tframenum = pkt_q->framenum;\n\tfor (i = 0; i < nb_pkts; i++) {\n\t\t/* point at the next incoming frame */\n\t\tppd = (struct tpacket2_hdr *) pkt_q->rd[framenum].iov_base;\n\t\tif ((ppd->tp_status & TP_STATUS_USER) == 0)\n\t\t\tbreak;\n\n\t\t/* allocate the next mbuf */\n\t\tmbuf = rte_pktmbuf_alloc(pkt_q->mb_pool);\n\t\tif (unlikely(mbuf == NULL))\n\t\t\tbreak;\n\n\t\t/* packet will fit in the mbuf, go ahead and receive it */\n\t\trte_pktmbuf_pkt_len(mbuf) = rte_pktmbuf_data_len(mbuf) = ppd->tp_snaplen;\n\t\tpbuf = (uint8_t *) ppd + ppd->tp_mac;\n\t\tmemcpy(rte_pktmbuf_mtod(mbuf, void *), pbuf, rte_pktmbuf_data_len(mbuf));\n\n\t\t/* release incoming frame and advance ring buffer */\n\t\tppd->tp_status = TP_STATUS_KERNEL;\n\t\tif (++framenum >= framecount)\n\t\t\tframenum = 0;\n\n\t\t/* account for the receive frame */\n\t\tbufs[i] = mbuf;\n\t\tnum_rx++;\n\t}\n\tpkt_q->framenum = framenum;\n\tpkt_q->rx_pkts += num_rx;\n\treturn num_rx;\n}\n\n/*\n * Callback to handle sending packets through a real NIC.\n */\nstatic uint16_t\neth_af_packet_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n{\n\tstruct tpacket2_hdr *ppd;\n\tstruct rte_mbuf *mbuf;\n\tuint8_t *pbuf;\n\tunsigned int framecount, framenum;\n\tstruct pollfd pfd;\n\tstruct pkt_tx_queue *pkt_q = queue;\n\tuint16_t num_tx = 0;\n\tint i;\n\n\tif (unlikely(nb_pkts == 0))\n\t\treturn 0;\n\n\tmemset(&pfd, 0, sizeof(pfd));\n\tpfd.fd = pkt_q->sockfd;\n\tpfd.events = POLLOUT;\n\tpfd.revents = 0;\n\n\tframecount = pkt_q->framecount;\n\tframenum = pkt_q->framenum;\n\tppd = (struct tpacket2_hdr *) pkt_q->rd[framenum].iov_base;\n\tfor (i = 0; i < nb_pkts; i++) {\n\t\t/* point at the next incoming frame */\n\t\tif ((ppd->tp_status != TP_STATUS_AVAILABLE) &&\n\t\t (poll(&pfd, 1, -1) < 0))\n\t\t\t\tcontinue;\n\n\t\t/* copy the tx frame data */\n\t\tmbuf = bufs[num_tx];\n\t\tpbuf = (uint8_t *) ppd + TPACKET2_HDRLEN -\n\t\t\tsizeof(struct sockaddr_ll);\n\t\tmemcpy(pbuf, rte_pktmbuf_mtod(mbuf, void*), rte_pktmbuf_data_len(mbuf));\n\t\tppd->tp_len = ppd->tp_snaplen = rte_pktmbuf_data_len(mbuf);\n\n\t\t/* release incoming frame and advance ring buffer */\n\t\tppd->tp_status = TP_STATUS_SEND_REQUEST;\n\t\tif (++framenum >= framecount)\n\t\t\tframenum = 0;\n\t\tppd = (struct tpacket2_hdr *) pkt_q->rd[framenum].iov_base;\n\n\t\tnum_tx++;\n\t\trte_pktmbuf_free(mbuf);\n\t}\n\n\t/* kick-off transmits */\n\tsendto(pkt_q->sockfd, NULL, 0, MSG_DONTWAIT, NULL, 0);\n\n\tpkt_q->framenum = framenum;\n\tpkt_q->tx_pkts += num_tx;\n\tpkt_q->err_pkts += nb_pkts - num_tx;\n\treturn num_tx;\n}\n\nstatic int\neth_dev_start(struct rte_eth_dev *dev)\n{\n\tdev->data->dev_link.link_status = 1;\n\treturn 0;\n}\n\n/*\n * This function gets called when the current port gets stopped.\n */\nstatic void\neth_dev_stop(struct rte_eth_dev *dev)\n{\n\tunsigned i;\n\tint sockfd;\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\n\tfor (i = 0; i < internals->nb_queues; i++) {\n\t\tsockfd = internals->rx_queue[i].sockfd;\n\t\tif (sockfd != -1)\n\t\t\tclose(sockfd);\n\t\tsockfd = internals->tx_queue[i].sockfd;\n\t\tif (sockfd != -1)\n\t\t\tclose(sockfd);\n\t}\n\n\tdev->data->dev_link.link_status = 0;\n}\n\nstatic int\neth_dev_configure(struct rte_eth_dev *dev __rte_unused)\n{\n\treturn 0;\n}\n\nstatic void\neth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n{\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\n\tdev_info->driver_name = drivername;\n\tdev_info->if_index = internals->if_index;\n\tdev_info->max_mac_addrs = 1;\n\tdev_info->max_rx_pktlen = (uint32_t)ETH_FRAME_LEN;\n\tdev_info->max_rx_queues = (uint16_t)internals->nb_queues;\n\tdev_info->max_tx_queues = (uint16_t)internals->nb_queues;\n\tdev_info->min_rx_bufsize = 0;\n\tdev_info->pci_dev = NULL;\n}\n\nstatic void\neth_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *igb_stats)\n{\n\tunsigned i, imax;\n\tunsigned long rx_total = 0, tx_total = 0, tx_err_total = 0;\n\tconst struct pmd_internals *internal = dev->data->dev_private;\n\n\timax = (internal->nb_queues < RTE_ETHDEV_QUEUE_STAT_CNTRS ?\n\t internal->nb_queues : RTE_ETHDEV_QUEUE_STAT_CNTRS);\n\tfor (i = 0; i < imax; i++) {\n\t\tigb_stats->q_ipackets[i] = internal->rx_queue[i].rx_pkts;\n\t\trx_total += igb_stats->q_ipackets[i];\n\t}\n\n\timax = (internal->nb_queues < RTE_ETHDEV_QUEUE_STAT_CNTRS ?\n\t internal->nb_queues : RTE_ETHDEV_QUEUE_STAT_CNTRS);\n\tfor (i = 0; i < imax; i++) {\n\t\tigb_stats->q_opackets[i] = internal->tx_queue[i].tx_pkts;\n\t\tigb_stats->q_errors[i] = internal->tx_queue[i].err_pkts;\n\t\ttx_total += igb_stats->q_opackets[i];\n\t\ttx_err_total += igb_stats->q_errors[i];\n\t}\n\n\tigb_stats->ipackets = rx_total;\n\tigb_stats->opackets = tx_total;\n\tigb_stats->oerrors = tx_err_total;\n}\n\nstatic void\neth_stats_reset(struct rte_eth_dev *dev)\n{\n\tunsigned i;\n\tstruct pmd_internals *internal = dev->data->dev_private;\n\n\tfor (i = 0; i < internal->nb_queues; i++)\n\t\tinternal->rx_queue[i].rx_pkts = 0;\n\n\tfor (i = 0; i < internal->nb_queues; i++) {\n\t\tinternal->tx_queue[i].tx_pkts = 0;\n\t\tinternal->tx_queue[i].err_pkts = 0;\n\t}\n}\n\nstatic void\neth_dev_close(struct rte_eth_dev *dev __rte_unused)\n{\n}\n\nstatic void\neth_queue_release(void *q __rte_unused)\n{\n}\n\nstatic int\neth_link_update(struct rte_eth_dev *dev __rte_unused,\n int wait_to_complete __rte_unused)\n{\n\treturn 0;\n}\n\nstatic int\neth_rx_queue_setup(struct rte_eth_dev *dev,\n uint16_t rx_queue_id,\n uint16_t nb_rx_desc __rte_unused,\n unsigned int socket_id __rte_unused,\n const struct rte_eth_rxconf *rx_conf __rte_unused,\n struct rte_mempool *mb_pool)\n{\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\tstruct pkt_rx_queue *pkt_q = &internals->rx_queue[rx_queue_id];\n\tuint16_t buf_size;\n\n\tpkt_q->mb_pool = mb_pool;\n\n\t/* Now get the space available for data in the mbuf */\n\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(pkt_q->mb_pool) -\n\t\tRTE_PKTMBUF_HEADROOM);\n\n\tif (ETH_FRAME_LEN > buf_size) {\n\t\tRTE_LOG(ERR, PMD,\n\t\t\t\"%s: %d bytes will not fit in mbuf (%d bytes)\\n\",\n\t\t\tdev->data->name, ETH_FRAME_LEN, buf_size);\n\t\treturn -ENOMEM;\n\t}\n\n\tdev->data->rx_queues[rx_queue_id] = pkt_q;\n\n\treturn 0;\n}\n\nstatic int\neth_tx_queue_setup(struct rte_eth_dev *dev,\n uint16_t tx_queue_id,\n uint16_t nb_tx_desc __rte_unused,\n unsigned int socket_id __rte_unused,\n const struct rte_eth_txconf *tx_conf __rte_unused)\n{\n\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\n\tdev->data->tx_queues[tx_queue_id] = &internals->tx_queue[tx_queue_id];\n\treturn 0;\n}\n\nstatic const struct eth_dev_ops ops = {\n\t.dev_start = eth_dev_start,\n\t.dev_stop = eth_dev_stop,\n\t.dev_close = eth_dev_close,\n\t.dev_configure = eth_dev_configure,\n\t.dev_infos_get = eth_dev_info,\n\t.rx_queue_setup = eth_rx_queue_setup,\n\t.tx_queue_setup = eth_tx_queue_setup,\n\t.rx_queue_release = eth_queue_release,\n\t.tx_queue_release = eth_queue_release,\n\t.link_update = eth_link_update,\n\t.stats_get = eth_stats_get,\n\t.stats_reset = eth_stats_reset,\n};\n\n/*\n * Opens an AF_PACKET socket\n */\nstatic int\nopen_packet_iface(const char *key __rte_unused,\n const char *value __rte_unused,\n void *extra_args)\n{\n\tint *sockfd = extra_args;\n\n\t/* Open an AF_PACKET socket... */\n\t*sockfd = socket(AF_PACKET, SOCK_RAW, htons(ETH_P_ALL));\n\tif (*sockfd == -1) {\n\t\tRTE_LOG(ERR, PMD, \"Could not open AF_PACKET socket\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_pmd_init_internals(const char *name,\n const int sockfd,\n const unsigned nb_queues,\n unsigned int blocksize,\n unsigned int blockcnt,\n unsigned int framesize,\n unsigned int framecnt,\n const unsigned numa_node,\n struct pmd_internals **internals,\n struct rte_eth_dev **eth_dev,\n struct rte_kvargs *kvlist)\n{\n\tstruct rte_eth_dev_data *data = NULL;\n\tstruct rte_pci_device *pci_dev = NULL;\n\tstruct rte_kvargs_pair *pair = NULL;\n\tstruct ifreq ifr;\n\tsize_t ifnamelen;\n\tunsigned k_idx;\n\tstruct sockaddr_ll sockaddr;\n\tstruct tpacket_req *req;\n\tstruct pkt_rx_queue *rx_queue;\n\tstruct pkt_tx_queue *tx_queue;\n\tint rc, tpver, discard;\n\tint qsockfd = -1;\n\tunsigned int i, q, rdsize;\n\tint fanout_arg __rte_unused, bypass __rte_unused;\n\n\tfor (k_idx = 0; k_idx < kvlist->count; k_idx++) {\n\t\tpair = &kvlist->pairs[k_idx];\n\t\tif (strstr(pair->key, ETH_AF_PACKET_IFACE_ARG) != NULL)\n\t\t\tbreak;\n\t}\n\tif (pair == NULL) {\n\t\tRTE_LOG(ERR, PMD,\n\t\t\t\"%s: no interface specified for AF_PACKET ethdev\\n\",\n\t\t name);\n\t\tgoto error;\n\t}\n\n\tRTE_LOG(INFO, PMD,\n\t\t\"%s: creating AF_PACKET-backed ethdev on numa socket %u\\n\",\n\t\tname, numa_node);\n\n\t/*\n\t * now do all data allocation - for eth_dev structure, dummy pci driver\n\t * and internal (private) data\n\t */\n\tdata = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node);\n\tif (data == NULL)\n\t\tgoto error;\n\n\tpci_dev = rte_zmalloc_socket(name, sizeof(*pci_dev), 0, numa_node);\n\tif (pci_dev == NULL)\n\t\tgoto error;\n\n\t*internals = rte_zmalloc_socket(name, sizeof(**internals),\n\t 0, numa_node);\n\tif (*internals == NULL)\n\t\tgoto error;\n\n\tfor (q = 0; q < nb_queues; q++) {\n\t\t(*internals)->rx_queue[q].map = MAP_FAILED;\n\t\t(*internals)->tx_queue[q].map = MAP_FAILED;\n\t}\n\n\treq = &((*internals)->req);\n\n\treq->tp_block_size = blocksize;\n\treq->tp_block_nr = blockcnt;\n\treq->tp_frame_size = framesize;\n\treq->tp_frame_nr = framecnt;\n\n\tifnamelen = strlen(pair->value);\n\tif (ifnamelen < sizeof(ifr.ifr_name)) {\n\t\tmemcpy(ifr.ifr_name, pair->value, ifnamelen);\n\t\tifr.ifr_name[ifnamelen] = '\\0';\n\t} else {\n\t\tRTE_LOG(ERR, PMD,\n\t\t\t\"%s: I/F name too long (%s)\\n\",\n\t\t\tname, pair->value);\n\t\tgoto error;\n\t}\n\tif (ioctl(sockfd, SIOCGIFINDEX, &ifr) == -1) {\n\t\tRTE_LOG(ERR, PMD,\n\t\t\t\"%s: ioctl failed (SIOCGIFINDEX)\\n\",\n\t\t name);\n\t\tgoto error;\n\t}\n\t(*internals)->if_index = ifr.ifr_ifindex;\n\n\tif (ioctl(sockfd, SIOCGIFHWADDR, &ifr) == -1) {\n\t\tRTE_LOG(ERR, PMD,\n\t\t\t\"%s: ioctl failed (SIOCGIFHWADDR)\\n\",\n\t\t name);\n\t\tgoto error;\n\t}\n\tmemcpy(&(*internals)->eth_addr, ifr.ifr_hwaddr.sa_data, ETH_ALEN);\n\n\tmemset(&sockaddr, 0, sizeof(sockaddr));\n\tsockaddr.sll_family = AF_PACKET;\n\tsockaddr.sll_protocol = htons(ETH_P_ALL);\n\tsockaddr.sll_ifindex = (*internals)->if_index;\n\n#if defined(PACKET_FANOUT)\n\tfanout_arg = (getpid() ^ (*internals)->if_index) & 0xffff;\n\tfanout_arg |= (PACKET_FANOUT_HASH | PACKET_FANOUT_FLAG_DEFRAG) << 16;\n#if defined(PACKET_FANOUT_FLAG_ROLLOVER)\n\tfanout_arg |= PACKET_FANOUT_FLAG_ROLLOVER << 16;\n#endif\n#endif\n\n\tfor (q = 0; q < nb_queues; q++) {\n\t\t/* Open an AF_PACKET socket for this queue... */\n\t\tqsockfd = socket(AF_PACKET, SOCK_RAW, htons(ETH_P_ALL));\n\t\tif (qsockfd == -1) {\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t \"%s: could not open AF_PACKET socket\\n\",\n\t\t\t name);\n\t\t\treturn -1;\n\t\t}\n\n\t\ttpver = TPACKET_V2;\n\t\trc = setsockopt(qsockfd, SOL_PACKET, PACKET_VERSION,\n\t\t\t\t&tpver, sizeof(tpver));\n\t\tif (rc == -1) {\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\"%s: could not set PACKET_VERSION on AF_PACKET \"\n\t\t\t\t\"socket for %s\\n\", name, pair->value);\n\t\t\tgoto error;\n\t\t}\n\n\t\tdiscard = 1;\n\t\trc = setsockopt(qsockfd, SOL_PACKET, PACKET_LOSS,\n\t\t\t\t&discard, sizeof(discard));\n\t\tif (rc == -1) {\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\"%s: could not set PACKET_LOSS on \"\n\t\t\t \"AF_PACKET socket for %s\\n\", name, pair->value);\n\t\t\tgoto error;\n\t\t}\n\n#if defined(PACKET_QDISC_BYPASS)\n\t\tbypass = 1;\n\t\trc = setsockopt(qsockfd, SOL_PACKET, PACKET_QDISC_BYPASS,\n\t\t\t\t&bypass, sizeof(bypass));\n\t\tif (rc == -1) {\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\"%s: could not set PACKET_QDISC_BYPASS \"\n\t\t\t \"on AF_PACKET socket for %s\\n\", name,\n\t\t\t pair->value);\n\t\t\tgoto error;\n\t\t}\n#endif\n\n\t\trc = setsockopt(qsockfd, SOL_PACKET, PACKET_RX_RING, req, sizeof(*req));\n\t\tif (rc == -1) {\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\"%s: could not set PACKET_RX_RING on AF_PACKET \"\n\t\t\t\t\"socket for %s\\n\", name, pair->value);\n\t\t\tgoto error;\n\t\t}\n\n\t\trc = setsockopt(qsockfd, SOL_PACKET, PACKET_TX_RING, req, sizeof(*req));\n\t\tif (rc == -1) {\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\"%s: could not set PACKET_TX_RING on AF_PACKET \"\n\t\t\t\t\"socket for %s\\n\", name, pair->value);\n\t\t\tgoto error;\n\t\t}\n\n\t\trx_queue = &((*internals)->rx_queue[q]);\n\t\trx_queue->framecount = req->tp_frame_nr;\n\n\t\trx_queue->map = mmap(NULL, 2 * req->tp_block_size * req->tp_block_nr,\n\t\t\t\t PROT_READ | PROT_WRITE, MAP_SHARED | MAP_LOCKED,\n\t\t\t\t qsockfd, 0);\n\t\tif (rx_queue->map == MAP_FAILED) {\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\"%s: call to mmap failed on AF_PACKET socket for %s\\n\",\n\t\t\t\tname, pair->value);\n\t\t\tgoto error;\n\t\t}\n\n\t\t/* rdsize is same for both Tx and Rx */\n\t\trdsize = req->tp_frame_nr * sizeof(*(rx_queue->rd));\n\n\t\trx_queue->rd = rte_zmalloc_socket(name, rdsize, 0, numa_node);\n\t\tif (rx_queue->rd == NULL)\n\t\t\tgoto error;\n\t\tfor (i = 0; i < req->tp_frame_nr; ++i) {\n\t\t\trx_queue->rd[i].iov_base = rx_queue->map + (i * framesize);\n\t\t\trx_queue->rd[i].iov_len = req->tp_frame_size;\n\t\t}\n\t\trx_queue->sockfd = qsockfd;\n\n\t\ttx_queue = &((*internals)->tx_queue[q]);\n\t\ttx_queue->framecount = req->tp_frame_nr;\n\n\t\ttx_queue->map = rx_queue->map + req->tp_block_size * req->tp_block_nr;\n\n\t\ttx_queue->rd = rte_zmalloc_socket(name, rdsize, 0, numa_node);\n\t\tif (tx_queue->rd == NULL)\n\t\t\tgoto error;\n\t\tfor (i = 0; i < req->tp_frame_nr; ++i) {\n\t\t\ttx_queue->rd[i].iov_base = tx_queue->map + (i * framesize);\n\t\t\ttx_queue->rd[i].iov_len = req->tp_frame_size;\n\t\t}\n\t\ttx_queue->sockfd = qsockfd;\n\n\t\trc = bind(qsockfd, (const struct sockaddr*)&sockaddr, sizeof(sockaddr));\n\t\tif (rc == -1) {\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\"%s: could not bind AF_PACKET socket to %s\\n\",\n\t\t\t name, pair->value);\n\t\t\tgoto error;\n\t\t}\n\n#if defined(PACKET_FANOUT)\n\t\trc = setsockopt(qsockfd, SOL_PACKET, PACKET_FANOUT,\n\t\t\t\t&fanout_arg, sizeof(fanout_arg));\n\t\tif (rc == -1) {\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\"%s: could not set PACKET_FANOUT on AF_PACKET socket \"\n\t\t\t\t\"for %s\\n\", name, pair->value);\n\t\t\tgoto error;\n\t\t}\n#endif\n\t}\n\n\t/* reserve an ethdev entry */\n\t*eth_dev = rte_eth_dev_allocate(name, RTE_ETH_DEV_VIRTUAL);\n\tif (*eth_dev == NULL)\n\t\tgoto error;\n\n\t/*\n\t * now put it all together\n\t * - store queue data in internals,\n\t * - store numa_node info in pci_driver\n\t * - point eth_dev_data to internals and pci_driver\n\t * - and point eth_dev structure to new eth_dev_data structure\n\t */\n\n\t(*internals)->nb_queues = nb_queues;\n\n\tdata->dev_private = *internals;\n\tdata->port_id = (*eth_dev)->data->port_id;\n\tdata->nb_rx_queues = (uint16_t)nb_queues;\n\tdata->nb_tx_queues = (uint16_t)nb_queues;\n\tdata->dev_link = pmd_link;\n\tdata->mac_addrs = &(*internals)->eth_addr;\n\n\tpci_dev->numa_node = numa_node;\n\n\t(*eth_dev)->data = data;\n\t(*eth_dev)->dev_ops = &ops;\n\t(*eth_dev)->pci_dev = pci_dev;\n\n\treturn 0;\n\nerror:\n\trte_free(data);\n\trte_free(pci_dev);\n\n\tif (*internals) {\n\t\tfor (q = 0; q < nb_queues; q++) {\n\t\t\tmunmap((*internals)->rx_queue[q].map,\n\t\t\t 2 * req->tp_block_size * req->tp_block_nr);\n\n\t\t\trte_free((*internals)->rx_queue[q].rd);\n\t\t\trte_free((*internals)->tx_queue[q].rd);\n\t\t\tif (((*internals)->rx_queue[q].sockfd != 0) &&\n\t\t\t\t((*internals)->rx_queue[q].sockfd != qsockfd))\n\t\t\t\tclose((*internals)->rx_queue[q].sockfd);\n\t\t}\n\t\trte_free(*internals);\n\t}\n\tif (qsockfd != -1)\n\t\tclose(qsockfd);\n\treturn -1;\n}\n\nstatic int\nrte_eth_from_packet(const char *name,\n int const *sockfd,\n const unsigned numa_node,\n struct rte_kvargs *kvlist)\n{\n\tstruct pmd_internals *internals = NULL;\n\tstruct rte_eth_dev *eth_dev = NULL;\n\tstruct rte_kvargs_pair *pair = NULL;\n\tunsigned k_idx;\n\tunsigned int blockcount;\n\tunsigned int blocksize = DFLT_BLOCK_SIZE;\n\tunsigned int framesize = DFLT_FRAME_SIZE;\n\tunsigned int framecount = DFLT_FRAME_COUNT;\n\tunsigned int qpairs = 1;\n\n\t/* do some parameter checking */\n\tif (*sockfd < 0)\n\t\treturn -1;\n\n\t/*\n\t * Walk arguments for configurable settings\n\t */\n\tfor (k_idx = 0; k_idx < kvlist->count; k_idx++) {\n\t\tpair = &kvlist->pairs[k_idx];\n\t\tif (strstr(pair->key, ETH_AF_PACKET_NUM_Q_ARG) != NULL) {\n\t\t\tqpairs = atoi(pair->value);\n\t\t\tif (qpairs < 1 ||\n\t\t\t qpairs > RTE_PMD_AF_PACKET_MAX_RINGS) {\n\t\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\t\"%s: invalid qpairs value\\n\",\n\t\t\t\t name);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tcontinue;\n\t\t}\n\t\tif (strstr(pair->key, ETH_AF_PACKET_BLOCKSIZE_ARG) != NULL) {\n\t\t\tblocksize = atoi(pair->value);\n\t\t\tif (!blocksize) {\n\t\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\t\"%s: invalid blocksize value\\n\",\n\t\t\t\t name);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tcontinue;\n\t\t}\n\t\tif (strstr(pair->key, ETH_AF_PACKET_FRAMESIZE_ARG) != NULL) {\n\t\t\tframesize = atoi(pair->value);\n\t\t\tif (!framesize) {\n\t\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\t\"%s: invalid framesize value\\n\",\n\t\t\t\t name);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tcontinue;\n\t\t}\n\t\tif (strstr(pair->key, ETH_AF_PACKET_FRAMECOUNT_ARG) != NULL) {\n\t\t\tframecount = atoi(pair->value);\n\t\t\tif (!framecount) {\n\t\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\t\"%s: invalid framecount value\\n\",\n\t\t\t\t name);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tcontinue;\n\t\t}\n\t}\n\n\tif (framesize > blocksize) {\n\t\tRTE_LOG(ERR, PMD,\n\t\t\t\"%s: AF_PACKET MMAP frame size exceeds block size!\\n\",\n\t\t name);\n\t\treturn -1;\n\t}\n\n\tblockcount = framecount / (blocksize / framesize);\n\tif (!blockcount) {\n\t\tRTE_LOG(ERR, PMD,\n\t\t\t\"%s: invalid AF_PACKET MMAP parameters\\n\", name);\n\t\treturn -1;\n\t}\n\n\tRTE_LOG(INFO, PMD, \"%s: AF_PACKET MMAP parameters:\\n\", name);\n\tRTE_LOG(INFO, PMD, \"%s:\\tblock size %d\\n\", name, blocksize);\n\tRTE_LOG(INFO, PMD, \"%s:\\tblock count %d\\n\", name, blockcount);\n\tRTE_LOG(INFO, PMD, \"%s:\\tframe size %d\\n\", name, framesize);\n\tRTE_LOG(INFO, PMD, \"%s:\\tframe count %d\\n\", name, framecount);\n\n\tif (rte_pmd_init_internals(name, *sockfd, qpairs,\n\t blocksize, blockcount,\n\t framesize, framecount,\n\t numa_node, &internals, ð_dev,\n\t kvlist) < 0)\n\t\treturn -1;\n\n\teth_dev->rx_pkt_burst = eth_af_packet_rx;\n\teth_dev->tx_pkt_burst = eth_af_packet_tx;\n\n\treturn 0;\n}\n\nint\nrte_pmd_af_packet_devinit(const char *name, const char *params)\n{\n\tunsigned numa_node;\n\tint ret = 0;\n\tstruct rte_kvargs *kvlist;\n\tint sockfd = -1;\n\n\tRTE_LOG(INFO, PMD, \"Initializing pmd_af_packet for %s\\n\", name);\n\n\tnuma_node = rte_socket_id();\n\n\tkvlist = rte_kvargs_parse(params, valid_arguments);\n\tif (kvlist == NULL) {\n\t\tret = -1;\n\t\tgoto exit;\n\t}\n\n\t/*\n\t * If iface argument is passed we open the NICs and use them for\n\t * reading / writing\n\t */\n\tif (rte_kvargs_count(kvlist, ETH_AF_PACKET_IFACE_ARG) == 1) {\n\n\t\tret = rte_kvargs_process(kvlist, ETH_AF_PACKET_IFACE_ARG,\n\t\t &open_packet_iface, &sockfd);\n\t\tif (ret < 0)\n\t\t\tgoto exit;\n\t}\n\n\tret = rte_eth_from_packet(name, &sockfd, numa_node, kvlist);\n\tclose(sockfd); /* no longer needed */\n\nexit:\n\trte_kvargs_free(kvlist);\n\treturn ret;\n}\n\nstatic struct rte_driver pmd_af_packet_drv = {\n\t.name = \"eth_af_packet\",\n\t.type = PMD_VDEV,\n\t.init = rte_pmd_af_packet_devinit,\n};\n\nPMD_REGISTER_DRIVER(pmd_af_packet_drv);\n" }, { "path": "drivers/net/af_packet/rte_eth_af_packet.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ETH_AF_PACKET_H_\n#define _RTE_ETH_AF_PACKET_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define RTE_PMD_AF_PACKET_MAX_RINGS 16\n\n/**\n * For use by the EAL only. Called as part of EAL init to set up any dummy NICs\n * configured on command line.\n */\nint rte_pmd_af_packet_devinit(const char *name, const char *params);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "drivers/net/bnx2x/Makefile", "content": "include $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_bnx2x.a\n\nCFLAGS += -O3 -g\nCFLAGS += $(WERROR_FLAGS)\nCFLAGS += -DZLIB_CONST\n\nEXPORT_MAP := rte_pmd_bnx2x_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x.c\nSRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_rxtx.c\nSRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_stats.c\nSRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_ethdev.c\nSRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += ecore_sp.c\nSRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += elink.c\nSRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_vfpf.c\nSRCS-$(CONFIG_RTE_LIBRTE_BNX2X_DEBUG) += debug.c\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += lib/librte_eal lib/librte_ether lib/librte_hash\nDEPDIRS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += lib/librte_mempool lib/librte_mbuf\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/bnx2x/bnx2x.c", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#define BNX2X_DRIVER_VERSION \"1.78.18\"\n\n#include \"bnx2x.h\"\n#include \"bnx2x_vfpf.h\"\n#include \"ecore_sp.h\"\n#include \"ecore_init.h\"\n#include \"ecore_init_ops.h\"\n\n#include \"rte_pci_dev_ids.h\"\n\n#include \n#include \n#include \n#include \n\nstatic z_stream zlib_stream;\n\n#define EVL_VLID_MASK 0x0FFF\n\n#define BNX2X_DEF_SB_ATT_IDX 0x0001\n#define BNX2X_DEF_SB_IDX 0x0002\n\n/*\n * FLR Support - bnx2x_pf_flr_clnup() is called during nic_load in the per\n * function HW initialization.\n */\n#define FLR_WAIT_USEC 10000\t/* 10 msecs */\n#define FLR_WAIT_INTERVAL 50\t/* usecs */\n#define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL)\t/* 200 */\n\nstruct pbf_pN_buf_regs {\n\tint pN;\n\tuint32_t init_crd;\n\tuint32_t crd;\n\tuint32_t crd_freed;\n};\n\nstruct pbf_pN_cmd_regs {\n\tint pN;\n\tuint32_t lines_occup;\n\tuint32_t lines_freed;\n};\n\n/* resources needed for unloading a previously loaded device */\n\n#define BNX2X_PREV_WAIT_NEEDED 1\nrte_spinlock_t bnx2x_prev_mtx;\nstruct bnx2x_prev_list_node {\n\tLIST_ENTRY(bnx2x_prev_list_node) node;\n\tuint8_t bus;\n\tuint8_t slot;\n\tuint8_t path;\n\tuint8_t aer;\n\tuint8_t undi;\n};\n\nstatic LIST_HEAD(, bnx2x_prev_list_node) bnx2x_prev_list\n\t= LIST_HEAD_INITIALIZER(bnx2x_prev_list);\n\nstatic int load_count[2][3] = { { 0 } };\n\t/* per-path: 0-common, 1-port0, 2-port1 */\n\nstatic void bnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg,\n\t\t\t\tuint8_t cmng_type);\nstatic int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc);\nstatic void storm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng,\n\t\t\t uint8_t port);\nstatic void bnx2x_set_reset_global(struct bnx2x_softc *sc);\nstatic void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc);\nstatic uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine);\nstatic uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc);\nstatic uint8_t bnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global,\n\t\t\t\t uint8_t print);\nstatic void bnx2x_int_disable(struct bnx2x_softc *sc);\nstatic int bnx2x_release_leader_lock(struct bnx2x_softc *sc);\nstatic void bnx2x_pf_disable(struct bnx2x_softc *sc);\nstatic void bnx2x_update_rx_prod(struct bnx2x_softc *sc,\n\t\t\t\t struct bnx2x_fastpath *fp,\n\t\t\t\t uint16_t rx_bd_prod, uint16_t rx_cq_prod);\nstatic void bnx2x_link_report(struct bnx2x_softc *sc);\nvoid bnx2x_link_status_update(struct bnx2x_softc *sc);\nstatic int bnx2x_alloc_mem(struct bnx2x_softc *sc);\nstatic void bnx2x_free_mem(struct bnx2x_softc *sc);\nstatic int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc);\nstatic void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc);\nstatic __attribute__ ((noinline))\nint bnx2x_nic_load(struct bnx2x_softc *sc);\n\nstatic int bnx2x_handle_sp_tq(struct bnx2x_softc *sc);\nstatic void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp);\nstatic void bnx2x_periodic_stop(struct bnx2x_softc *sc);\nstatic void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,\n\t\t\t uint8_t storm, uint16_t index, uint8_t op,\n\t\t\t uint8_t update);\n\nint bnx2x_test_bit(int nr, volatile unsigned long *addr)\n{\n\tint res;\n\n\tmb();\n\tres = ((*addr) & (1UL << nr)) != 0;\n\tmb();\n\treturn res;\n}\n\nvoid bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)\n{\n\t__sync_fetch_and_or(addr, (1UL << nr));\n}\n\nvoid bnx2x_clear_bit(int nr, volatile unsigned long *addr)\n{\n\t__sync_fetch_and_and(addr, ~(1UL << nr));\n}\n\nint bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)\n{\n\tunsigned long mask = (1UL << nr);\n\treturn __sync_fetch_and_and(addr, ~mask) & mask;\n}\n\nint bnx2x_cmpxchg(volatile int *addr, int old, int new)\n{\n\treturn __sync_val_compare_and_swap(addr, old, new);\n}\n\nint\nbnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size, struct bnx2x_dma *dma,\n\t const char *msg, uint32_t align)\n{\n\tchar mz_name[RTE_MEMZONE_NAMESIZE];\n\tconst struct rte_memzone *z;\n\n\tdma->sc = sc;\n\tif (IS_PF(sc))\n\t\tsprintf(mz_name, \"bnx2x%d_%s_%\" PRIx64, SC_ABS_FUNC(sc), msg,\n\t\t\trte_get_timer_cycles());\n\telse\n\t\tsprintf(mz_name, \"bnx2x%d_%s_%\" PRIx64, sc->pcie_device, msg,\n\t\t\trte_get_timer_cycles());\n\n\t/* Caller must take care that strlen(mz_name) < RTE_MEMZONE_NAMESIZE */\n\tz = rte_memzone_reserve_aligned(mz_name, (uint64_t) (size),\n\t\t\t\t\trte_lcore_to_socket_id(rte_lcore_id()),\n\t\t\t\t\t0, align);\n\tif (z == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"DMA alloc failed for %s\", msg);\n\t\treturn -ENOMEM;\n\t}\n\tdma->paddr = (uint64_t) z->phys_addr;\n\tdma->vaddr = z->addr;\n\n\tPMD_DRV_LOG(DEBUG, \"%s: virt=%p phys=%\" PRIx64, msg, dma->vaddr, dma->paddr);\n\n\treturn 0;\n}\n\nstatic int bnx2x_acquire_hw_lock(struct bnx2x_softc *sc, uint32_t resource)\n{\n\tuint32_t lock_status;\n\tuint32_t resource_bit = (1 << resource);\n\tint func = SC_FUNC(sc);\n\tuint32_t hw_lock_control_reg;\n\tint cnt;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* validate the resource is within range */\n\tif (resource > HW_LOCK_MAX_RESOURCE_VALUE) {\n\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t \"resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE\",\n\t\t\t resource);\n\t\treturn -1;\n\t}\n\n\tif (func <= 5) {\n\t\thw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));\n\t} else {\n\t\thw_lock_control_reg =\n\t\t (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));\n\t}\n\n\t/* validate the resource is not already taken */\n\tlock_status = REG_RD(sc, hw_lock_control_reg);\n\tif (lock_status & resource_bit) {\n\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t \"resource in use (status 0x%x bit 0x%x)\",\n\t\t\t lock_status, resource_bit);\n\t\treturn -1;\n\t}\n\n\t/* try every 5ms for 5 seconds */\n\tfor (cnt = 0; cnt < 1000; cnt++) {\n\t\tREG_WR(sc, (hw_lock_control_reg + 4), resource_bit);\n\t\tlock_status = REG_RD(sc, hw_lock_control_reg);\n\t\tif (lock_status & resource_bit) {\n\t\t\treturn 0;\n\t\t}\n\t\tDELAY(5000);\n\t}\n\n\tPMD_DRV_LOG(NOTICE, \"Resource lock timeout!\");\n\treturn -1;\n}\n\nstatic int bnx2x_release_hw_lock(struct bnx2x_softc *sc, uint32_t resource)\n{\n\tuint32_t lock_status;\n\tuint32_t resource_bit = (1 << resource);\n\tint func = SC_FUNC(sc);\n\tuint32_t hw_lock_control_reg;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* validate the resource is within range */\n\tif (resource > HW_LOCK_MAX_RESOURCE_VALUE) {\n\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t \"resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE\",\n\t\t\t resource);\n\t\treturn -1;\n\t}\n\n\tif (func <= 5) {\n\t\thw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));\n\t} else {\n\t\thw_lock_control_reg =\n\t\t (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));\n\t}\n\n\t/* validate the resource is currently taken */\n\tlock_status = REG_RD(sc, hw_lock_control_reg);\n\tif (!(lock_status & resource_bit)) {\n\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t \"resource not in use (status 0x%x bit 0x%x)\",\n\t\t\t lock_status, resource_bit);\n\t\treturn -1;\n\t}\n\n\tREG_WR(sc, hw_lock_control_reg, resource_bit);\n\treturn 0;\n}\n\n/* copy command into DMAE command memory and set DMAE command Go */\nvoid bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx)\n{\n\tuint32_t cmd_offset;\n\tuint32_t i;\n\n\tcmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));\n\tfor (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {\n\t\tREG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *) dmae) + i));\n\t}\n\n\tREG_WR(sc, dmae_reg_go_c[idx], 1);\n}\n\nuint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type)\n{\n\treturn (opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |\n\t\t\t DMAE_COMMAND_C_TYPE_ENABLE));\n}\n\nuint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode)\n{\n\treturn (opcode & ~DMAE_COMMAND_SRC_RESET);\n}\n\nuint32_t\nbnx2x_dmae_opcode(struct bnx2x_softc * sc, uint8_t src_type, uint8_t dst_type,\n\t\tuint8_t with_comp, uint8_t comp_type)\n{\n\tuint32_t opcode = 0;\n\n\topcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |\n\t\t (dst_type << DMAE_COMMAND_DST_SHIFT));\n\n\topcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);\n\n\topcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);\n\n\topcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |\n\t\t (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));\n\n\topcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);\n\n#ifdef __BIG_ENDIAN\n\topcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;\n#else\n\topcode |= DMAE_CMD_ENDIANITY_DW_SWAP;\n#endif\n\n\tif (with_comp) {\n\t\topcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);\n\t}\n\n\treturn opcode;\n}\n\nstatic void\nbnx2x_prep_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae,\n\t\t\tuint8_t src_type, uint8_t dst_type)\n{\n\tmemset(dmae, 0, sizeof(struct dmae_command));\n\n\t/* set the opcode */\n\tdmae->opcode = bnx2x_dmae_opcode(sc, src_type, dst_type,\n\t\t\t\t TRUE, DMAE_COMP_PCI);\n\n\t/* fill in the completion parameters */\n\tdmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_comp));\n\tdmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_comp));\n\tdmae->comp_val = DMAE_COMP_VAL;\n}\n\n/* issue a DMAE command over the init channel and wait for completion */\nstatic int\nbnx2x_issue_dmae_with_comp(struct bnx2x_softc *sc, struct dmae_command *dmae)\n{\n\tuint32_t *wb_comp = BNX2X_SP(sc, wb_comp);\n\tint timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;\n\n\t/* reset completion */\n\t*wb_comp = 0;\n\n\t/* post the command on the channel used for initializations */\n\tbnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));\n\n\t/* wait for completion */\n\tDELAY(500);\n\n\twhile ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {\n\t\tif (!timeout ||\n\t\t (sc->recovery_state != BNX2X_RECOVERY_DONE &&\n\t\t sc->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {\n\t\t\tPMD_DRV_LOG(INFO, \"DMAE timeout!\");\n\t\t\treturn DMAE_TIMEOUT;\n\t\t}\n\n\t\ttimeout--;\n\t\tDELAY(50);\n\t}\n\n\tif (*wb_comp & DMAE_PCI_ERR_FLAG) {\n\t\tPMD_DRV_LOG(INFO, \"DMAE PCI error!\");\n\t\treturn DMAE_PCI_ERROR;\n\t}\n\n\treturn 0;\n}\n\nvoid bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32)\n{\n\tstruct dmae_command dmae;\n\tuint32_t *data;\n\tuint32_t i;\n\tint rc;\n\n\tif (!sc->dmae_ready) {\n\t\tdata = BNX2X_SP(sc, wb_data[0]);\n\n\t\tfor (i = 0; i < len32; i++) {\n\t\t\tdata[i] = REG_RD(sc, (src_addr + (i * 4)));\n\t\t}\n\n\t\treturn;\n\t}\n\n\t/* set opcode and fixed command fields */\n\tbnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);\n\n\t/* fill in addresses and len */\n\tdmae.src_addr_lo = (src_addr >> 2);\t/* GRC addr has dword resolution */\n\tdmae.src_addr_hi = 0;\n\tdmae.dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, wb_data));\n\tdmae.dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, wb_data));\n\tdmae.len = len32;\n\n\t/* issue the command and wait for completion */\n\tif ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {\n\t\trte_panic(\"DMAE failed (%d)\", rc);\n\t};\n}\n\nvoid\nbnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr, uint32_t dst_addr,\n\t uint32_t len32)\n{\n\tstruct dmae_command dmae;\n\tint rc;\n\n\tif (!sc->dmae_ready) {\n\t\tecore_init_str_wr(sc, dst_addr, BNX2X_SP(sc, wb_data[0]), len32);\n\t\treturn;\n\t}\n\n\t/* set opcode and fixed command fields */\n\tbnx2x_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);\n\n\t/* fill in addresses and len */\n\tdmae.src_addr_lo = U64_LO(dma_addr);\n\tdmae.src_addr_hi = U64_HI(dma_addr);\n\tdmae.dst_addr_lo = (dst_addr >> 2);\t/* GRC addr has dword resolution */\n\tdmae.dst_addr_hi = 0;\n\tdmae.len = len32;\n\n\t/* issue the command and wait for completion */\n\tif ((rc = bnx2x_issue_dmae_with_comp(sc, &dmae)) != 0) {\n\t\trte_panic(\"DMAE failed (%d)\", rc);\n\t}\n}\n\nstatic void\nbnx2x_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,\n\t\t\tuint32_t addr, uint32_t len)\n{\n\tuint32_t dmae_wr_max = DMAE_LEN32_WR_MAX(sc);\n\tuint32_t offset = 0;\n\n\twhile (len > dmae_wr_max) {\n\t\tbnx2x_write_dmae(sc, (phys_addr + offset),\t/* src DMA address */\n\t\t\t (addr + offset),\t/* dst GRC address */\n\t\t\t dmae_wr_max);\n\t\toffset += (dmae_wr_max * 4);\n\t\tlen -= dmae_wr_max;\n\t}\n\n\tbnx2x_write_dmae(sc, (phys_addr + offset),\t/* src DMA address */\n\t\t (addr + offset),\t/* dst GRC address */\n\t\t len);\n}\n\nvoid\nbnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,\n\t\t uint32_t cid)\n{\n\t/* ustorm cxt validation */\n\tcxt->ustorm_ag_context.cdu_usage =\n\t CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),\n\t\t\t\t CDU_REGION_NUMBER_UCM_AG,\n\t\t\t\t ETH_CONNECTION_TYPE);\n\t/* xcontext validation */\n\tcxt->xstorm_ag_context.cdu_reserved =\n\t CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),\n\t\t\t\t CDU_REGION_NUMBER_XCM_AG,\n\t\t\t\t ETH_CONNECTION_TYPE);\n}\n\nstatic void\nbnx2x_storm_memset_hc_timeout(struct bnx2x_softc *sc, uint8_t fw_sb_id,\n\t\t\t uint8_t sb_index, uint8_t ticks)\n{\n\tuint32_t addr =\n\t (BAR_CSTRORM_INTMEM +\n\t CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));\n\n\tREG_WR8(sc, addr, ticks);\n}\n\nstatic void\nbnx2x_storm_memset_hc_disable(struct bnx2x_softc *sc, uint16_t fw_sb_id,\n\t\t\t uint8_t sb_index, uint8_t disable)\n{\n\tuint32_t enable_flag =\n\t (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);\n\tuint32_t addr =\n\t (BAR_CSTRORM_INTMEM +\n\t CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));\n\tuint8_t flags;\n\n\t/* clear and set */\n\tflags = REG_RD8(sc, addr);\n\tflags &= ~HC_INDEX_DATA_HC_ENABLED;\n\tflags |= enable_flag;\n\tREG_WR8(sc, addr, flags);\n}\n\nvoid\nbnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,\n\t\t\t uint8_t sb_index, uint8_t disable, uint16_t usec)\n{\n\tuint8_t ticks = (usec / 4);\n\n\tbnx2x_storm_memset_hc_timeout(sc, fw_sb_id, sb_index, ticks);\n\n\tdisable = (disable) ? 1 : ((usec) ? 0 : 1);\n\tbnx2x_storm_memset_hc_disable(sc, fw_sb_id, sb_index, disable);\n}\n\nuint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr)\n{\n\treturn REG_RD(sc, reg_addr);\n}\n\nvoid elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val)\n{\n\tREG_WR(sc, reg_addr, val);\n}\n\nvoid\nelink_cb_event_log(__rte_unused struct bnx2x_softc *sc,\n\t\t __rte_unused const elink_log_id_t elink_log_id, ...)\n{\n\tPMD_DRV_LOG(DEBUG, \"ELINK EVENT LOG (%d)\", elink_log_id);\n}\n\nstatic int bnx2x_set_spio(struct bnx2x_softc *sc, int spio, uint32_t mode)\n{\n\tuint32_t spio_reg;\n\n\t/* Only 2 SPIOs are configurable */\n\tif ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {\n\t\tPMD_DRV_LOG(NOTICE, \"Invalid SPIO 0x%x\", spio);\n\t\treturn -1;\n\t}\n\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);\n\n\t/* read SPIO and mask except the float bits */\n\tspio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);\n\n\tswitch (mode) {\n\tcase MISC_SPIO_OUTPUT_LOW:\n\t\t/* clear FLOAT and set CLR */\n\t\tspio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);\n\t\tspio_reg |= (spio << MISC_SPIO_CLR_POS);\n\t\tbreak;\n\n\tcase MISC_SPIO_OUTPUT_HIGH:\n\t\t/* clear FLOAT and set SET */\n\t\tspio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);\n\t\tspio_reg |= (spio << MISC_SPIO_SET_POS);\n\t\tbreak;\n\n\tcase MISC_SPIO_INPUT_HI_Z:\n\t\t/* set FLOAT */\n\t\tspio_reg |= (spio << MISC_SPIO_FLOAT_POS);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tREG_WR(sc, MISC_REG_SPIO, spio_reg);\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);\n\n\treturn 0;\n}\n\nstatic int bnx2x_gpio_read(struct bnx2x_softc *sc, int gpio_num, uint8_t port)\n{\n\t/* The GPIO should be swapped if swap register is set and active */\n\tint gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&\n\t\t\t REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);\n\tint gpio_shift = gpio_num;\n\tif (gpio_port)\n\t\tgpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;\n\n\tuint32_t gpio_mask = (1 << gpio_shift);\n\tuint32_t gpio_reg;\n\n\tif (gpio_num > MISC_REGISTERS_GPIO_3) {\n\t\tPMD_DRV_LOG(NOTICE, \"Invalid GPIO %d\", gpio_num);\n\t\treturn -1;\n\t}\n\n\t/* read GPIO value */\n\tgpio_reg = REG_RD(sc, MISC_REG_GPIO);\n\n\t/* get the requested pin value */\n\treturn ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;\n}\n\nstatic int\nbnx2x_gpio_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode, uint8_t port)\n{\n\t/* The GPIO should be swapped if swap register is set and active */\n\tint gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&\n\t\t\t REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);\n\tint gpio_shift = gpio_num;\n\tif (gpio_port)\n\t\tgpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;\n\n\tuint32_t gpio_mask = (1 << gpio_shift);\n\tuint32_t gpio_reg;\n\n\tif (gpio_num > MISC_REGISTERS_GPIO_3) {\n\t\tPMD_DRV_LOG(NOTICE, \"Invalid GPIO %d\", gpio_num);\n\t\treturn -1;\n\t}\n\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);\n\n\t/* read GPIO and mask except the float bits */\n\tgpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);\n\n\tswitch (mode) {\n\tcase MISC_REGISTERS_GPIO_OUTPUT_LOW:\n\t\t/* clear FLOAT and set CLR */\n\t\tgpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);\n\t\tgpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);\n\t\tbreak;\n\n\tcase MISC_REGISTERS_GPIO_OUTPUT_HIGH:\n\t\t/* clear FLOAT and set SET */\n\t\tgpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);\n\t\tgpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);\n\t\tbreak;\n\n\tcase MISC_REGISTERS_GPIO_INPUT_HI_Z:\n\t\t/* set FLOAT */\n\t\tgpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tREG_WR(sc, MISC_REG_GPIO, gpio_reg);\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);\n\n\treturn 0;\n}\n\nstatic int\nbnx2x_gpio_mult_write(struct bnx2x_softc *sc, uint8_t pins, uint32_t mode)\n{\n\tuint32_t gpio_reg;\n\n\t/* any port swapping should be handled by caller */\n\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);\n\n\t/* read GPIO and mask except the float bits */\n\tgpio_reg = REG_RD(sc, MISC_REG_GPIO);\n\tgpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);\n\tgpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);\n\tgpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);\n\n\tswitch (mode) {\n\tcase MISC_REGISTERS_GPIO_OUTPUT_LOW:\n\t\t/* set CLR */\n\t\tgpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);\n\t\tbreak;\n\n\tcase MISC_REGISTERS_GPIO_OUTPUT_HIGH:\n\t\t/* set SET */\n\t\tgpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);\n\t\tbreak;\n\n\tcase MISC_REGISTERS_GPIO_INPUT_HI_Z:\n\t\t/* set FLOAT */\n\t\tgpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);\n\t\tbreak;\n\n\tdefault:\n\t\tPMD_DRV_LOG(NOTICE, \"Invalid GPIO mode assignment %d\", mode);\n\t\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);\n\t\treturn -1;\n\t}\n\n\tREG_WR(sc, MISC_REG_GPIO, gpio_reg);\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);\n\n\treturn 0;\n}\n\nstatic int\nbnx2x_gpio_int_write(struct bnx2x_softc *sc, int gpio_num, uint32_t mode,\n\t\t uint8_t port)\n{\n\t/* The GPIO should be swapped if swap register is set and active */\n\tint gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&\n\t\t\t REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);\n\tint gpio_shift = gpio_num;\n\tif (gpio_port)\n\t\tgpio_shift += MISC_REGISTERS_GPIO_PORT_SHIFT;\n\n\tuint32_t gpio_mask = (1 << gpio_shift);\n\tuint32_t gpio_reg;\n\n\tif (gpio_num > MISC_REGISTERS_GPIO_3) {\n\t\tPMD_DRV_LOG(NOTICE, \"Invalid GPIO %d\", gpio_num);\n\t\treturn -1;\n\t}\n\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);\n\n\t/* read GPIO int */\n\tgpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);\n\n\tswitch (mode) {\n\tcase MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:\n\t\t/* clear SET and set CLR */\n\t\tgpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);\n\t\tgpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);\n\t\tbreak;\n\n\tcase MISC_REGISTERS_GPIO_INT_OUTPUT_SET:\n\t\t/* clear CLR and set SET */\n\t\tgpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);\n\t\tgpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tREG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);\n\n\treturn 0;\n}\n\nuint32_t\nelink_cb_gpio_read(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t port)\n{\n\treturn bnx2x_gpio_read(sc, gpio_num, port);\n}\n\nuint8_t elink_cb_gpio_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,\t/* 0=low 1=high */\n\t\t\t uint8_t port)\n{\n\treturn bnx2x_gpio_write(sc, gpio_num, mode, port);\n}\n\nuint8_t\nelink_cb_gpio_mult_write(struct bnx2x_softc * sc, uint8_t pins,\n\t\t\t uint8_t mode /* 0=low 1=high */ )\n{\n\treturn bnx2x_gpio_mult_write(sc, pins, mode);\n}\n\nuint8_t elink_cb_gpio_int_write(struct bnx2x_softc * sc, uint16_t gpio_num, uint8_t mode,\t/* 0=low 1=high */\n\t\t\t\tuint8_t port)\n{\n\treturn bnx2x_gpio_int_write(sc, gpio_num, mode, port);\n}\n\nvoid elink_cb_notify_link_changed(struct bnx2x_softc *sc)\n{\n\tREG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +\n\t\t (SC_FUNC(sc) * sizeof(uint32_t))), 1);\n}\n\n/* send the MCP a request, block until there is a reply */\nuint32_t\nelink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)\n{\n\tint mb_idx = SC_FW_MB_IDX(sc);\n\tuint32_t seq;\n\tuint32_t rc = 0;\n\tuint32_t cnt = 1;\n\tuint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;\n\n\tseq = ++sc->fw_seq;\n\tSHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);\n\tSHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));\n\n\tPMD_DRV_LOG(DEBUG,\n\t\t \"wrote command 0x%08x to FW MB param 0x%08x\",\n\t\t (command | seq), param);\n\n\t/* Let the FW do it's magic. GIve it up to 5 seconds... */\n\tdo {\n\t\tDELAY(delay * 1000);\n\t\trc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);\n\t} while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));\n\n\t/* is this a reply to our command? */\n\tif (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {\n\t\trc &= FW_MSG_CODE_MASK;\n\t} else {\n\t\t/* Ruh-roh! */\n\t\tPMD_DRV_LOG(NOTICE, \"FW failed to respond!\");\n\t\trc = 0;\n\t}\n\n\treturn rc;\n}\n\nstatic uint32_t\nbnx2x_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param)\n{\n\treturn elink_cb_fw_command(sc, command, param);\n}\n\nstatic void\n__storm_memset_dma_mapping(struct bnx2x_softc *sc, uint32_t addr,\n\t\t\t phys_addr_t mapping)\n{\n\tREG_WR(sc, addr, U64_LO(mapping));\n\tREG_WR(sc, (addr + 4), U64_HI(mapping));\n}\n\nstatic void\nstorm_memset_spq_addr(struct bnx2x_softc *sc, phys_addr_t mapping,\n\t\t uint16_t abs_fid)\n{\n\tuint32_t addr = (XSEM_REG_FAST_MEMORY +\n\t\t\t XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));\n\t__storm_memset_dma_mapping(sc, addr, mapping);\n}\n\nstatic void\nstorm_memset_vf_to_pf(struct bnx2x_softc *sc, uint16_t abs_fid, uint16_t pf_id)\n{\n\tREG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)),\n\t\tpf_id);\n\tREG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)),\n\t\tpf_id);\n\tREG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)),\n\t\tpf_id);\n\tREG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)),\n\t\tpf_id);\n}\n\nstatic void\nstorm_memset_func_en(struct bnx2x_softc *sc, uint16_t abs_fid, uint8_t enable)\n{\n\tREG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)),\n\t\tenable);\n\tREG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)),\n\t\tenable);\n\tREG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)),\n\t\tenable);\n\tREG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)),\n\t\tenable);\n}\n\nstatic void\nstorm_memset_eq_data(struct bnx2x_softc *sc, struct event_ring_data *eq_data,\n\t\t uint16_t pfid)\n{\n\tuint32_t addr;\n\tsize_t size;\n\n\taddr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));\n\tsize = sizeof(struct event_ring_data);\n\tecore_storm_memset_struct(sc, addr, size, (uint32_t *) eq_data);\n}\n\nstatic void\nstorm_memset_eq_prod(struct bnx2x_softc *sc, uint16_t eq_prod, uint16_t pfid)\n{\n\tuint32_t addr = (BAR_CSTRORM_INTMEM +\n\t\t\t CSTORM_EVENT_RING_PROD_OFFSET(pfid));\n\tREG_WR16(sc, addr, eq_prod);\n}\n\n/*\n * Post a slowpath command.\n *\n * A slowpath command is used to propogate a configuration change through\n * the controller in a controlled manner, allowing each STORM processor and\n * other H/W blocks to phase in the change. The commands sent on the\n * slowpath are referred to as ramrods. Depending on the ramrod used the\n * completion of the ramrod will occur in different ways. Here's a\n * breakdown of ramrods and how they complete:\n *\n * RAMROD_CMD_ID_ETH_PORT_SETUP\n * Used to setup the leading connection on a port. Completes on the\n * Receive Completion Queue (RCQ) of that port (typically fp[0]).\n *\n * RAMROD_CMD_ID_ETH_CLIENT_SETUP\n * Used to setup an additional connection on a port. Completes on the\n * RCQ of the multi-queue/RSS connection being initialized.\n *\n * RAMROD_CMD_ID_ETH_STAT_QUERY\n * Used to force the storm processors to update the statistics database\n * in host memory. This ramrod is send on the leading connection CID and\n * completes as an index increment of the CSTORM on the default status\n * block.\n *\n * RAMROD_CMD_ID_ETH_UPDATE\n * Used to update the state of the leading connection, usually to udpate\n * the RSS indirection table. Completes on the RCQ of the leading\n * connection. (Not currently used under FreeBSD until OS support becomes\n * available.)\n *\n * RAMROD_CMD_ID_ETH_HALT\n * Used when tearing down a connection prior to driver unload. Completes\n * on the RCQ of the multi-queue/RSS connection being torn down. Don't\n * use this on the leading connection.\n *\n * RAMROD_CMD_ID_ETH_SET_MAC\n * Sets the Unicast/Broadcast/Multicast used by the port. Completes on\n * the RCQ of the leading connection.\n *\n * RAMROD_CMD_ID_ETH_CFC_DEL\n * Used when tearing down a conneciton prior to driver unload. Completes\n * on the RCQ of the leading connection (since the current connection\n * has been completely removed from controller memory).\n *\n * RAMROD_CMD_ID_ETH_PORT_DEL\n * Used to tear down the leading connection prior to driver unload,\n * typically fp[0]. Completes as an index increment of the CSTORM on the\n * default status block.\n *\n * RAMROD_CMD_ID_ETH_FORWARD_SETUP\n * Used for connection offload. Completes on the RCQ of the multi-queue\n * RSS connection that is being offloaded. (Not currently used under\n * FreeBSD.)\n *\n * There can only be one command pending per function.\n *\n * Returns:\n * 0 = Success, !0 = Failure.\n */\n\n/* must be called under the spq lock */\nstatic inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x_softc *sc)\n{\n\tstruct eth_spe *next_spe = sc->spq_prod_bd;\n\n\tif (sc->spq_prod_bd == sc->spq_last_bd) {\n\t\t/* wrap back to the first eth_spq */\n\t\tsc->spq_prod_bd = sc->spq;\n\t\tsc->spq_prod_idx = 0;\n\t} else {\n\t\tsc->spq_prod_bd++;\n\t\tsc->spq_prod_idx++;\n\t}\n\n\treturn next_spe;\n}\n\n/* must be called under the spq lock */\nstatic void bnx2x_sp_prod_update(struct bnx2x_softc *sc)\n{\n\tint func = SC_FUNC(sc);\n\n\t/*\n\t * Make sure that BD data is updated before writing the producer.\n\t * BD data is written to the memory, the producer is read from the\n\t * memory, thus we need a full memory barrier to ensure the ordering.\n\t */\n\tmb();\n\n\tREG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),\n\t\t sc->spq_prod_idx);\n\n\tmb();\n}\n\n/**\n * bnx2x_is_contextless_ramrod - check if the current command ends on EQ\n *\n * @cmd: command to check\n * @cmd_type: command type\n */\nstatic int bnx2x_is_contextless_ramrod(int cmd, int cmd_type)\n{\n\tif ((cmd_type == NONE_CONNECTION_TYPE) ||\n\t (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||\n\t (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||\n\t (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||\n\t (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||\n\t (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||\n\t (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {\n\t\treturn TRUE;\n\t} else {\n\t\treturn FALSE;\n\t}\n}\n\n/**\n * bnx2x_sp_post - place a single command on an SP ring\n *\n * @sc: driver handle\n * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)\n * @cid: SW CID the command is related to\n * @data_hi: command private data address (high 32 bits)\n * @data_lo: command private data address (low 32 bits)\n * @cmd_type: command type (e.g. NONE, ETH)\n *\n * SP data is handled as if it's always an address pair, thus data fields are\n * not swapped to little endian in upper functions. Instead this function swaps\n * data as if it's two uint32 fields.\n */\nint\nbnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid, uint32_t data_hi,\n\t uint32_t data_lo, int cmd_type)\n{\n\tstruct eth_spe *spe;\n\tuint16_t type;\n\tint common;\n\n\tcommon = bnx2x_is_contextless_ramrod(command, cmd_type);\n\n\tif (common) {\n\t\tif (!atomic_load_acq_long(&sc->eq_spq_left)) {\n\t\t\tPMD_DRV_LOG(INFO, \"EQ ring is full!\");\n\t\t\treturn -1;\n\t\t}\n\t} else {\n\t\tif (!atomic_load_acq_long(&sc->cq_spq_left)) {\n\t\t\tPMD_DRV_LOG(INFO, \"SPQ ring is full!\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tspe = bnx2x_sp_get_next(sc);\n\n\t/* CID needs port number to be encoded int it */\n\tspe->hdr.conn_and_cmd_data =\n\t htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));\n\n\ttype = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;\n\n\t/* TBD: Check if it works for VFs */\n\ttype |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &\n\t\t SPE_HDR_FUNCTION_ID);\n\n\tspe->hdr.type = htole16(type);\n\n\tspe->data.update_data_addr.hi = htole32(data_hi);\n\tspe->data.update_data_addr.lo = htole32(data_lo);\n\n\t/*\n\t * It's ok if the actual decrement is issued towards the memory\n\t * somewhere between the lock and unlock. Thus no more explict\n\t * memory barrier is needed.\n\t */\n\tif (common) {\n\t\tatomic_subtract_acq_long(&sc->eq_spq_left, 1);\n\t} else {\n\t\tatomic_subtract_acq_long(&sc->cq_spq_left, 1);\n\t}\n\n\tPMD_DRV_LOG(DEBUG,\n\t\t \"SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x\"\n\t\t \"data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)\",\n\t\t sc->spq_prod_idx,\n\t\t (uint32_t) U64_HI(sc->spq_dma.paddr),\n\t\t (uint32_t) (U64_LO(sc->spq_dma.paddr) +\n\t\t\t\t(uint8_t *) sc->spq_prod_bd -\n\t\t\t\t(uint8_t *) sc->spq), command, common,\n\t\t HW_CID(sc, cid), data_hi, data_lo, type,\n\t\t atomic_load_acq_long(&sc->cq_spq_left),\n\t\t atomic_load_acq_long(&sc->eq_spq_left));\n\n\tbnx2x_sp_prod_update(sc);\n\n\treturn 0;\n}\n\nstatic void bnx2x_drv_pulse(struct bnx2x_softc *sc)\n{\n\tSHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,\n\t\t sc->fw_drv_pulse_wr_seq);\n}\n\nstatic int bnx2x_tx_queue_has_work(const struct bnx2x_fastpath *fp)\n{\n\tuint16_t hw_cons;\n\tstruct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];\n\n\tif (unlikely(!txq)) {\n\t\tPMD_TX_LOG(ERR, \"ERROR: TX queue is NULL\");\n\t\treturn 0;\n\t}\n\n\tmb();\t\t\t/* status block fields can change */\n\thw_cons = le16toh(*fp->tx_cons_sb);\n\treturn (hw_cons != txq->tx_pkt_head);\n}\n\nstatic uint8_t bnx2x_has_tx_work(struct bnx2x_fastpath *fp)\n{\n\t/* expand this for multi-cos if ever supported */\n\treturn bnx2x_tx_queue_has_work(fp);\n}\n\nstatic int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)\n{\n\tuint16_t rx_cq_cons_sb;\n\tstruct bnx2x_rx_queue *rxq;\n\trxq = fp->sc->rx_queues[fp->index];\n\tif (unlikely(!rxq)) {\n\t\tPMD_RX_LOG(ERR, \"ERROR: RX queue is NULL\");\n\t\treturn 0;\n\t}\n\n\tmb();\t\t\t/* status block fields can change */\n\trx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);\n\tif (unlikely((rx_cq_cons_sb & MAX_RCQ_ENTRIES(rxq)) ==\n\t\t MAX_RCQ_ENTRIES(rxq)))\n\t\trx_cq_cons_sb++;\n\treturn (rxq->rx_cq_head != rx_cq_cons_sb);\n}\n\nstatic void\nbnx2x_sp_event(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n\t union eth_rx_cqe *rr_cqe)\n{\n#ifdef RTE_LIBRTE_BNX2X_DEBUG\n\tint cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);\n#endif\n\tint command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);\n\tenum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;\n\tstruct ecore_queue_sp_obj *q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;\n\n\tPMD_DRV_LOG(DEBUG,\n\t\t \"fp=%d cid=%d got ramrod #%d state is %x type is %d\",\n\t\t fp->index, cid, command, sc->state,\n\t\t rr_cqe->ramrod_cqe.ramrod_type);\n\n\tswitch (command) {\n\tcase (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):\n\t\tPMD_DRV_LOG(DEBUG, \"got UPDATE ramrod. CID %d\", cid);\n\t\tdrv_cmd = ECORE_Q_CMD_UPDATE;\n\t\tbreak;\n\n\tcase (RAMROD_CMD_ID_ETH_CLIENT_SETUP):\n\t\tPMD_DRV_LOG(DEBUG, \"got MULTI[%d] setup ramrod\", cid);\n\t\tdrv_cmd = ECORE_Q_CMD_SETUP;\n\t\tbreak;\n\n\tcase (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):\n\t\tPMD_DRV_LOG(DEBUG, \"got MULTI[%d] tx-only setup ramrod\", cid);\n\t\tdrv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;\n\t\tbreak;\n\n\tcase (RAMROD_CMD_ID_ETH_HALT):\n\t\tPMD_DRV_LOG(DEBUG, \"got MULTI[%d] halt ramrod\", cid);\n\t\tdrv_cmd = ECORE_Q_CMD_HALT;\n\t\tbreak;\n\n\tcase (RAMROD_CMD_ID_ETH_TERMINATE):\n\t\tPMD_DRV_LOG(DEBUG, \"got MULTI[%d] teminate ramrod\", cid);\n\t\tdrv_cmd = ECORE_Q_CMD_TERMINATE;\n\t\tbreak;\n\n\tcase (RAMROD_CMD_ID_ETH_EMPTY):\n\t\tPMD_DRV_LOG(DEBUG, \"got MULTI[%d] empty ramrod\", cid);\n\t\tdrv_cmd = ECORE_Q_CMD_EMPTY;\n\t\tbreak;\n\n\tdefault:\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t \"ERROR: unexpected MC reply (%d)\"\n\t\t\t \"on fp[%d]\", command, fp->index);\n\t\treturn;\n\t}\n\n\tif ((drv_cmd != ECORE_Q_CMD_MAX) &&\n\t q_obj->complete_cmd(sc, q_obj, drv_cmd)) {\n\t\t/*\n\t\t * q_obj->complete_cmd() failure means that this was\n\t\t * an unexpected completion.\n\t\t *\n\t\t * In this case we don't want to increase the sc->spq_left\n\t\t * because apparently we haven't sent this command the first\n\t\t * place.\n\t\t */\n\t\t// rte_panic(\"Unexpected SP completion\");\n\t\treturn;\n\t}\n\n\tatomic_add_acq_long(&sc->cq_spq_left, 1);\n\n\tPMD_DRV_LOG(DEBUG, \"sc->cq_spq_left 0x%lx\",\n\t\t atomic_load_acq_long(&sc->cq_spq_left));\n}\n\nstatic uint8_t bnx2x_rxeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)\n{\n\tstruct bnx2x_rx_queue *rxq;\n\tuint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;\n\tuint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;\n\n\trxq = sc->rx_queues[fp->index];\n\tif (!rxq) {\n\t\tPMD_RX_LOG(ERR, \"RX queue %d is NULL\", fp->index);\n\t\treturn 0;\n\t}\n\n\t/* CQ \"next element\" is of the size of the regular element */\n\thw_cq_cons = le16toh(*fp->rx_cq_cons_sb);\n\tif (unlikely((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==\n\t\t USABLE_RCQ_ENTRIES_PER_PAGE)) {\n\t\thw_cq_cons++;\n\t}\n\n\tbd_cons = rxq->rx_bd_head;\n\tbd_prod = rxq->rx_bd_tail;\n\tbd_prod_fw = bd_prod;\n\tsw_cq_cons = rxq->rx_cq_head;\n\tsw_cq_prod = rxq->rx_cq_tail;\n\n\t/*\n\t * Memory barrier necessary as speculative reads of the rx\n\t * buffer can be ahead of the index in the status block\n\t */\n\trmb();\n\n\twhile (sw_cq_cons != hw_cq_cons) {\n\t\tunion eth_rx_cqe *cqe;\n\t\tstruct eth_fast_path_rx_cqe *cqe_fp;\n\t\tuint8_t cqe_fp_flags;\n\t\tenum eth_rx_cqe_type cqe_fp_type;\n\n\t\tcomp_ring_cons = RCQ_ENTRY(sw_cq_cons, rxq);\n\t\tbd_prod = RX_BD(bd_prod, rxq);\n\t\tbd_cons = RX_BD(bd_cons, rxq);\n\n\t\tcqe = &rxq->cq_ring[comp_ring_cons];\n\t\tcqe_fp = &cqe->fast_path_cqe;\n\t\tcqe_fp_flags = cqe_fp->type_error_flags;\n\t\tcqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;\n\n\t\t/* is this a slowpath msg? */\n\t\tif (CQE_TYPE_SLOW(cqe_fp_type)) {\n\t\t\tbnx2x_sp_event(sc, fp, cqe);\n\t\t\tgoto next_cqe;\n\t\t}\n\n\t\t/* is this an error packet? */\n\t\tif (unlikely(cqe_fp_flags &\n\t\t\t ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {\n\t\t\tPMD_RX_LOG(DEBUG, \"flags 0x%x rx packet %u\",\n\t\t\t\t cqe_fp_flags, sw_cq_cons);\n\t\t\tgoto next_rx;\n\t\t}\n\n\t\tPMD_RX_LOG(DEBUG, \"Dropping fastpath called from attn poller!\");\n\nnext_rx:\n\t\tbd_cons = NEXT_RX_BD(bd_cons);\n\t\tbd_prod = NEXT_RX_BD(bd_prod);\n\t\tbd_prod_fw = NEXT_RX_BD(bd_prod_fw);\n\nnext_cqe:\n\t\tsw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);\n\t\tsw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);\n\n\t}\t\t\t/* while work to do */\n\n\trxq->rx_bd_head = bd_cons;\n\trxq->rx_bd_tail = bd_prod_fw;\n\trxq->rx_cq_head = sw_cq_cons;\n\trxq->rx_cq_tail = sw_cq_prod;\n\n\t/* Update producers */\n\tbnx2x_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod);\n\n\treturn (sw_cq_cons != hw_cq_cons);\n}\n\nstatic uint16_t\nbnx2x_free_tx_pkt(__rte_unused struct bnx2x_fastpath *fp, struct bnx2x_tx_queue *txq,\n\t\tuint16_t pkt_idx, uint16_t bd_idx)\n{\n\tstruct eth_tx_start_bd *tx_start_bd =\n\t &txq->tx_ring[TX_BD(bd_idx, txq)].start_bd;\n\tuint16_t nbd = rte_le_to_cpu_16(tx_start_bd->nbd);\n\tstruct rte_mbuf *tx_mbuf = txq->sw_ring[TX_BD(pkt_idx, txq)];\n\n\tif (likely(tx_mbuf != NULL)) {\n\t\trte_pktmbuf_free(tx_mbuf);\n\t} else {\n\t\tPMD_RX_LOG(ERR, \"fp[%02d] lost mbuf %lu\",\n\t\t\t fp->index, (unsigned long)TX_BD(pkt_idx, txq));\n\t}\n\n\ttxq->sw_ring[TX_BD(pkt_idx, txq)] = NULL;\n\ttxq->nb_tx_avail += nbd;\n\n\twhile (nbd--)\n\t\tbd_idx = NEXT_TX_BD(bd_idx);\n\n\treturn bd_idx;\n}\n\n/* processes transmit completions */\nuint8_t bnx2x_txeof(__rte_unused struct bnx2x_softc * sc, struct bnx2x_fastpath * fp)\n{\n\tuint16_t bd_cons, hw_cons, sw_cons;\n\t__rte_unused uint16_t tx_bd_avail;\n\n\tstruct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];\n\n\tif (unlikely(!txq)) {\n\t\tPMD_TX_LOG(ERR, \"ERROR: TX queue is NULL\");\n\t\treturn 0;\n\t}\n\n\tbd_cons = txq->tx_bd_head;\n\thw_cons = rte_le_to_cpu_16(*fp->tx_cons_sb);\n\tsw_cons = txq->tx_pkt_head;\n\n\twhile (sw_cons != hw_cons) {\n\t\tbd_cons = bnx2x_free_tx_pkt(fp, txq, sw_cons, bd_cons);\n\t\tsw_cons++;\n\t}\n\n\ttxq->tx_pkt_head = sw_cons;\n\ttxq->tx_bd_head = bd_cons;\n\n\ttx_bd_avail = txq->nb_tx_avail;\n\n\tPMD_TX_LOG(DEBUG, \"fp[%02d] avail=%u cons_sb=%u, \"\n\t\t \"pkt_head=%u pkt_tail=%u bd_head=%u bd_tail=%u\",\n\t\t fp->index, tx_bd_avail, hw_cons,\n\t\t txq->tx_pkt_head, txq->tx_pkt_tail,\n\t\t txq->tx_bd_head, txq->tx_bd_tail);\n\treturn TRUE;\n}\n\nstatic void bnx2x_drain_tx_queues(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_fastpath *fp;\n\tint i, count;\n\n\t/* wait until all TX fastpath tasks have completed */\n\tfor (i = 0; i < sc->num_queues; i++) {\n\t\tfp = &sc->fp[i];\n\n\t\tcount = 1000;\n\n\t\twhile (bnx2x_has_tx_work(fp)) {\n\t\t\tbnx2x_txeof(sc, fp);\n\n\t\t\tif (count == 0) {\n\t\t\t\tPMD_TX_LOG(ERR,\n\t\t\t\t\t \"Timeout waiting for fp[%d] \"\n\t\t\t\t\t \"transmits to complete!\", i);\n\t\t\t\trte_panic(\"tx drain failure\");\n\t\t\t\treturn;\n\t\t\t}\n\n\t\t\tcount--;\n\t\t\tDELAY(1000);\n\t\t\trmb();\n\t\t}\n\t}\n\n\treturn;\n}\n\nstatic int\nbnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,\n\t\t int mac_type, uint8_t wait_for_comp)\n{\n\tunsigned long ramrod_flags = 0, vlan_mac_flags = 0;\n\tint rc;\n\n\t/* wait for completion of requested */\n\tif (wait_for_comp) {\n\t\tbnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);\n\t}\n\n\t/* Set the mac type of addresses we want to clear */\n\tbnx2x_set_bit(mac_type, &vlan_mac_flags);\n\n\trc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);\n\tif (rc < 0)\n\t\tPMD_DRV_LOG(ERR, \"Failed to delete MACs (%d)\", rc);\n\n\treturn rc;\n}\n\nint\nbnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,\n\t\t unsigned long *rx_accept_flags,\n\t\t unsigned long *tx_accept_flags)\n{\n\t/* Clear the flags first */\n\t*rx_accept_flags = 0;\n\t*tx_accept_flags = 0;\n\n\tswitch (rx_mode) {\n\tcase BNX2X_RX_MODE_NONE:\n\t\t/*\n\t\t * 'drop all' supersedes any accept flags that may have been\n\t\t * passed to the function.\n\t\t */\n\t\tbreak;\n\n\tcase BNX2X_RX_MODE_NORMAL:\n\t\tbnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);\n\n\t\t/* internal switching mode */\n\t\tbnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);\n\n\t\tbreak;\n\n\tcase BNX2X_RX_MODE_ALLMULTI:\n\t\tbnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);\n\n\t\t/* internal switching mode */\n\t\tbnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);\n\n\t\tbreak;\n\n\tcase BNX2X_RX_MODE_PROMISC:\n\t\t/*\n\t\t * According to deffinition of SI mode, iface in promisc mode\n\t\t * should receive matched and unmatched (in resolution of port)\n\t\t * unicast packets.\n\t\t */\n\t\tbnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);\n\n\t\t/* internal switching mode */\n\t\tbnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);\n\n\t\tif (IS_MF_SI(sc)) {\n\t\t\tbnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);\n\t\t} else {\n\t\t\tbnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);\n\t\t}\n\n\t\tbreak;\n\n\tdefault:\n\t\tPMD_RX_LOG(ERR, \"Unknown rx_mode (%d)\", rx_mode);\n\t\treturn -1;\n\t}\n\n\t/* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */\n\tif (rx_mode != BNX2X_RX_MODE_NONE) {\n\t\tbnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);\n\t\tbnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nbnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,\n\t\t unsigned long rx_mode_flags,\n\t\t unsigned long rx_accept_flags,\n\t\t unsigned long tx_accept_flags, unsigned long ramrod_flags)\n{\n\tstruct ecore_rx_mode_ramrod_params ramrod_param;\n\tint rc;\n\n\tmemset(&ramrod_param, 0, sizeof(ramrod_param));\n\n\t/* Prepare ramrod parameters */\n\tramrod_param.cid = 0;\n\tramrod_param.cl_id = cl_id;\n\tramrod_param.rx_mode_obj = &sc->rx_mode_obj;\n\tramrod_param.func_id = SC_FUNC(sc);\n\n\tramrod_param.pstate = &sc->sp_state;\n\tramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;\n\n\tramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);\n\tramrod_param.rdata_mapping =\n\t (phys_addr_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),\n\t bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);\n\n\tramrod_param.ramrod_flags = ramrod_flags;\n\tramrod_param.rx_mode_flags = rx_mode_flags;\n\n\tramrod_param.rx_accept_flags = rx_accept_flags;\n\tramrod_param.tx_accept_flags = tx_accept_flags;\n\n\trc = ecore_config_rx_mode(sc, &ramrod_param);\n\tif (rc < 0) {\n\t\tPMD_RX_LOG(ERR, \"Set rx_mode %d failed\", sc->rx_mode);\n\t\treturn rc;\n\t}\n\n\treturn 0;\n}\n\nint bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)\n{\n\tunsigned long rx_mode_flags = 0, ramrod_flags = 0;\n\tunsigned long rx_accept_flags = 0, tx_accept_flags = 0;\n\tint rc;\n\n\trc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,\n\t\t\t\t &tx_accept_flags);\n\tif (rc) {\n\t\treturn rc;\n\t}\n\n\tbnx2x_set_bit(RAMROD_RX, &ramrod_flags);\n\tbnx2x_set_bit(RAMROD_TX, &ramrod_flags);\n\tbnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);\n\n\treturn bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,\n\t\t\t\t rx_accept_flags, tx_accept_flags,\n\t\t\t\t ramrod_flags);\n}\n\n/* returns the \"mcp load_code\" according to global load_count array */\nstatic int bnx2x_nic_load_no_mcp(struct bnx2x_softc *sc)\n{\n\tint path = SC_PATH(sc);\n\tint port = SC_PORT(sc);\n\n\tPMD_DRV_LOG(INFO, \"NO MCP - load counts[%d] %d, %d, %d\",\n\t\t path, load_count[path][0], load_count[path][1],\n\t\t load_count[path][2]);\n\n\tload_count[path][0]++;\n\tload_count[path][1 + port]++;\n\tPMD_DRV_LOG(INFO, \"NO MCP - new load counts[%d] %d, %d, %d\",\n\t\t path, load_count[path][0], load_count[path][1],\n\t\t load_count[path][2]);\n\tif (load_count[path][0] == 1)\n\t\treturn FW_MSG_CODE_DRV_LOAD_COMMON;\n\telse if (load_count[path][1 + port] == 1)\n\t\treturn FW_MSG_CODE_DRV_LOAD_PORT;\n\telse\n\t\treturn FW_MSG_CODE_DRV_LOAD_FUNCTION;\n}\n\n/* returns the \"mcp load_code\" according to global load_count array */\nstatic int bnx2x_nic_unload_no_mcp(struct bnx2x_softc *sc)\n{\n\tint port = SC_PORT(sc);\n\tint path = SC_PATH(sc);\n\n\tPMD_DRV_LOG(INFO, \"NO MCP - load counts[%d] %d, %d, %d\",\n\t\t path, load_count[path][0], load_count[path][1],\n\t\t load_count[path][2]);\n\tload_count[path][0]--;\n\tload_count[path][1 + port]--;\n\tPMD_DRV_LOG(INFO, \"NO MCP - new load counts[%d] %d, %d, %d\",\n\t\t path, load_count[path][0], load_count[path][1],\n\t\t load_count[path][2]);\n\tif (load_count[path][0] == 0) {\n\t\treturn FW_MSG_CODE_DRV_UNLOAD_COMMON;\n\t} else if (load_count[path][1 + port] == 0) {\n\t\treturn FW_MSG_CODE_DRV_UNLOAD_PORT;\n\t} else {\n\t\treturn FW_MSG_CODE_DRV_UNLOAD_FUNCTION;\n\t}\n}\n\n/* request unload mode from the MCP: COMMON, PORT or FUNCTION */\nstatic uint32_t bnx2x_send_unload_req(struct bnx2x_softc *sc, int unload_mode)\n{\n\tuint32_t reset_code = 0;\n\n\t/* Select the UNLOAD request mode */\n\tif (unload_mode == UNLOAD_NORMAL) {\n\t\treset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;\n\t} else {\n\t\treset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;\n\t}\n\n\t/* Send the request to the MCP */\n\tif (!BNX2X_NOMCP(sc)) {\n\t\treset_code = bnx2x_fw_command(sc, reset_code, 0);\n\t} else {\n\t\treset_code = bnx2x_nic_unload_no_mcp(sc);\n\t}\n\n\treturn reset_code;\n}\n\n/* send UNLOAD_DONE command to the MCP */\nstatic void bnx2x_send_unload_done(struct bnx2x_softc *sc, uint8_t keep_link)\n{\n\tuint32_t reset_param =\n\t keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;\n\n\t/* Report UNLOAD_DONE to MCP */\n\tif (!BNX2X_NOMCP(sc)) {\n\t\tbnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);\n\t}\n}\n\nstatic int bnx2x_func_wait_started(struct bnx2x_softc *sc)\n{\n\tint tout = 50;\n\n\tif (!sc->port.pmf) {\n\t\treturn 0;\n\t}\n\n\t/*\n\t * (assumption: No Attention from MCP at this stage)\n\t * PMF probably in the middle of TX disable/enable transaction\n\t * 1. Sync IRS for default SB\n\t * 2. Sync SP queue - this guarantees us that attention handling started\n\t * 3. Wait, that TX disable/enable transaction completes\n\t *\n\t * 1+2 guarantee that if DCBX attention was scheduled it already changed\n\t * pending bit of transaction from STARTED-->TX_STOPPED, if we already\n\t * received completion for the transaction the state is TX_STOPPED.\n\t * State will return to STARTED after completion of TX_STOPPED-->STARTED\n\t * transaction.\n\t */\n\n\twhile (ecore_func_get_state(sc, &sc->func_obj) !=\n\t ECORE_F_STATE_STARTED && tout--) {\n\t\tDELAY(20000);\n\t}\n\n\tif (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {\n\t\t/*\n\t\t * Failed to complete the transaction in a \"good way\"\n\t\t * Force both transactions with CLR bit.\n\t\t */\n\t\tstruct ecore_func_state_params func_params = { NULL };\n\n\t\tPMD_DRV_LOG(NOTICE, \"Unexpected function state! \"\n\t\t\t \"Forcing STARTED-->TX_STOPPED-->STARTED\");\n\n\t\tfunc_params.f_obj = &sc->func_obj;\n\t\tbnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);\n\n\t\t/* STARTED-->TX_STOPPED */\n\t\tfunc_params.cmd = ECORE_F_CMD_TX_STOP;\n\t\tecore_func_state_change(sc, &func_params);\n\n\t\t/* TX_STOPPED-->STARTED */\n\t\tfunc_params.cmd = ECORE_F_CMD_TX_START;\n\t\treturn ecore_func_state_change(sc, &func_params);\n\t}\n\n\treturn 0;\n}\n\nstatic int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)\n{\n\tstruct bnx2x_fastpath *fp = &sc->fp[index];\n\tstruct ecore_queue_state_params q_params = { NULL };\n\tint rc;\n\n\tPMD_DRV_LOG(DEBUG, \"stopping queue %d cid %d\", index, fp->index);\n\n\tq_params.q_obj = &sc->sp_objs[fp->index].q_obj;\n\t/* We want to wait for completion in this context */\n\tbnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);\n\n\t/* Stop the primary connection: */\n\n\t/* ...halt the connection */\n\tq_params.cmd = ECORE_Q_CMD_HALT;\n\trc = ecore_queue_state_change(sc, &q_params);\n\tif (rc) {\n\t\treturn rc;\n\t}\n\n\t/* ...terminate the connection */\n\tq_params.cmd = ECORE_Q_CMD_TERMINATE;\n\tmemset(&q_params.params.terminate, 0,\n\t sizeof(q_params.params.terminate));\n\tq_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;\n\trc = ecore_queue_state_change(sc, &q_params);\n\tif (rc) {\n\t\treturn rc;\n\t}\n\n\t/* ...delete cfc entry */\n\tq_params.cmd = ECORE_Q_CMD_CFC_DEL;\n\tmemset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));\n\tq_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;\n\treturn ecore_queue_state_change(sc, &q_params);\n}\n\n/* wait for the outstanding SP commands */\nstatic uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)\n{\n\tunsigned long tmp;\n\tint tout = 5000;\t/* wait for 5 secs tops */\n\n\twhile (tout--) {\n\t\tmb();\n\t\tif (!(atomic_load_acq_long(&sc->sp_state) & mask)) {\n\t\t\treturn TRUE;\n\t\t}\n\n\t\tDELAY(1000);\n\t}\n\n\tmb();\n\n\ttmp = atomic_load_acq_long(&sc->sp_state);\n\tif (tmp & mask) {\n\t\tPMD_DRV_LOG(INFO, \"Filtering completion timed out: \"\n\t\t\t \"sp_state 0x%lx, mask 0x%lx\", tmp, mask);\n\t\treturn FALSE;\n\t}\n\n\treturn FALSE;\n}\n\nstatic int bnx2x_func_stop(struct bnx2x_softc *sc)\n{\n\tstruct ecore_func_state_params func_params = { NULL };\n\tint rc;\n\n\t/* prepare parameters for function state transitions */\n\tbnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);\n\tfunc_params.f_obj = &sc->func_obj;\n\tfunc_params.cmd = ECORE_F_CMD_STOP;\n\n\t/*\n\t * Try to stop the function the 'good way'. If it fails (in case\n\t * of a parity error during bnx2x_chip_cleanup()) and we are\n\t * not in a debug mode, perform a state transaction in order to\n\t * enable further HW_RESET transaction.\n\t */\n\trc = ecore_func_state_change(sc, &func_params);\n\tif (rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"FUNC_STOP ramrod failed. \"\n\t\t\t \"Running a dry transaction\");\n\t\tbnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);\n\t\treturn ecore_func_state_change(sc, &func_params);\n\t}\n\n\treturn 0;\n}\n\nstatic int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)\n{\n\tstruct ecore_func_state_params func_params = { NULL };\n\n\t/* Prepare parameters for function state transitions */\n\tbnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);\n\n\tfunc_params.f_obj = &sc->func_obj;\n\tfunc_params.cmd = ECORE_F_CMD_HW_RESET;\n\n\tfunc_params.params.hw_init.load_phase = load_code;\n\n\treturn ecore_func_state_change(sc, &func_params);\n}\n\nstatic void bnx2x_int_disable_sync(struct bnx2x_softc *sc, int disable_hw)\n{\n\tif (disable_hw) {\n\t\t/* prevent the HW from sending interrupts */\n\t\tbnx2x_int_disable(sc);\n\t}\n}\n\nstatic void\nbnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)\n{\n\tint port = SC_PORT(sc);\n\tstruct ecore_mcast_ramrod_params rparam = { NULL };\n\tuint32_t reset_code;\n\tint i, rc = 0;\n\n\tbnx2x_drain_tx_queues(sc);\n\n\t/* give HW time to discard old tx messages */\n\tDELAY(1000);\n\n\t/* Clean all ETH MACs */\n\trc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC,\n\t\t\t FALSE);\n\tif (rc < 0) {\n\t\tPMD_DRV_LOG(NOTICE, \"Failed to delete all ETH MACs (%d)\", rc);\n\t}\n\n\t/* Clean up UC list */\n\trc = bnx2x_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC,\n\t\t\t TRUE);\n\tif (rc < 0) {\n\t\tPMD_DRV_LOG(NOTICE, \"Failed to delete UC MACs list (%d)\", rc);\n\t}\n\n\t/* Disable LLH */\n\tREG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);\n\n\t/* Set \"drop all\" to stop Rx */\n\n\t/*\n\t * We need to take the if_maddr_lock() here in order to prevent\n\t * a race between the completion code and this code.\n\t */\n\n\tif (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {\n\t\tbnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);\n\t} else {\n\t\tbnx2x_set_storm_rx_mode(sc);\n\t}\n\n\t/* Clean up multicast configuration */\n\trparam.mcast_obj = &sc->mcast_obj;\n\trc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);\n\tif (rc < 0) {\n\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t \"Failed to send DEL MCAST command (%d)\", rc);\n\t}\n\n\t/*\n\t * Send the UNLOAD_REQUEST to the MCP. This will return if\n\t * this function should perform FUNCTION, PORT, or COMMON HW\n\t * reset.\n\t */\n\treset_code = bnx2x_send_unload_req(sc, unload_mode);\n\n\t/*\n\t * (assumption: No Attention from MCP at this stage)\n\t * PMF probably in the middle of TX disable/enable transaction\n\t */\n\trc = bnx2x_func_wait_started(sc);\n\tif (rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"bnx2x_func_wait_started failed\");\n\t}\n\n\t/*\n\t * Close multi and leading connections\n\t * Completions for ramrods are collected in a synchronous way\n\t */\n\tfor (i = 0; i < sc->num_queues; i++) {\n\t\tif (bnx2x_stop_queue(sc, i)) {\n\t\t\tgoto unload_error;\n\t\t}\n\t}\n\n\t/*\n\t * If SP settings didn't get completed so far - something\n\t * very wrong has happen.\n\t */\n\tif (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {\n\t\tPMD_DRV_LOG(NOTICE, \"Common slow path ramrods got stuck!\");\n\t}\n\nunload_error:\n\n\trc = bnx2x_func_stop(sc);\n\tif (rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"Function stop failed!\");\n\t}\n\n\t/* disable HW interrupts */\n\tbnx2x_int_disable_sync(sc, TRUE);\n\n\t/* Reset the chip */\n\trc = bnx2x_reset_hw(sc, reset_code);\n\tif (rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"Hardware reset failed\");\n\t}\n\n\t/* Report UNLOAD_DONE to MCP */\n\tbnx2x_send_unload_done(sc, keep_link);\n}\n\nstatic void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)\n{\n\tuint32_t val;\n\n\tPMD_DRV_LOG(DEBUG, \"Disabling 'close the gates'\");\n\n\tval = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);\n\tval &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |\n\t\t MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);\n\tREG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);\n}\n\n/*\n * Cleans the object that have internal lists without sending\n * ramrods. Should be run when interrutps are disabled.\n */\nstatic void bnx2x_squeeze_objects(struct bnx2x_softc *sc)\n{\n\tunsigned long ramrod_flags = 0, vlan_mac_flags = 0;\n\tstruct ecore_mcast_ramrod_params rparam = { NULL };\n\tstruct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;\n\tint rc;\n\n\t/* Cleanup MACs' object first... */\n\n\t/* Wait for completion of requested */\n\tbnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);\n\t/* Perform a dry cleanup */\n\tbnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);\n\n\t/* Clean ETH primary MAC */\n\tbnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);\n\trc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,\n\t\t\t\t &ramrod_flags);\n\tif (rc != 0) {\n\t\tPMD_DRV_LOG(NOTICE, \"Failed to clean ETH MACs (%d)\", rc);\n\t}\n\n\t/* Cleanup UC list */\n\tvlan_mac_flags = 0;\n\tbnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);\n\trc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);\n\tif (rc != 0) {\n\t\tPMD_DRV_LOG(NOTICE, \"Failed to clean UC list MACs (%d)\", rc);\n\t}\n\n\t/* Now clean mcast object... */\n\n\trparam.mcast_obj = &sc->mcast_obj;\n\tbnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);\n\n\t/* Add a DEL command... */\n\trc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);\n\tif (rc < 0) {\n\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t \"Failed to send DEL MCAST command (%d)\", rc);\n\t}\n\n\t/* now wait until all pending commands are cleared */\n\n\trc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);\n\twhile (rc != 0) {\n\t\tif (rc < 0) {\n\t\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t\t \"Failed to clean MCAST object (%d)\", rc);\n\t\t\treturn;\n\t\t}\n\n\t\trc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);\n\t}\n}\n\n/* stop the controller */\n__attribute__ ((noinline))\nint\nbnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link)\n{\n\tuint8_t global = FALSE;\n\tuint32_t val;\n\n\tPMD_DRV_LOG(DEBUG, \"Starting NIC unload...\");\n\n\t/* stop the periodic callout */\n\tbnx2x_periodic_stop(sc);\n\n\t/* mark driver as unloaded in shmem2 */\n\tif (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {\n\t\tval = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);\n\t\tSHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],\n\t\t\t val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);\n\t}\n\n\tif (IS_PF(sc) && sc->recovery_state != BNX2X_RECOVERY_DONE &&\n\t (sc->state == BNX2X_STATE_CLOSED || sc->state == BNX2X_STATE_ERROR)) {\n\t\t/*\n\t\t * We can get here if the driver has been unloaded\n\t\t * during parity error recovery and is either waiting for a\n\t\t * leader to complete or for other functions to unload and\n\t\t * then ifconfig down has been issued. In this case we want to\n\t\t * unload and let other functions to complete a recovery\n\t\t * process.\n\t\t */\n\t\tsc->recovery_state = BNX2X_RECOVERY_DONE;\n\t\tsc->is_leader = 0;\n\t\tbnx2x_release_leader_lock(sc);\n\t\tmb();\n\n\t\tPMD_DRV_LOG(NOTICE, \"Can't unload in closed or error state\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * Nothing to do during unload if previous bnx2x_nic_load()\n\t * did not completed succesfully - all resourses are released.\n\t */\n\tif ((sc->state == BNX2X_STATE_CLOSED) || (sc->state == BNX2X_STATE_ERROR)) {\n\t\treturn 0;\n\t}\n\n\tsc->state = BNX2X_STATE_CLOSING_WAITING_HALT;\n\tmb();\n\n\tsc->rx_mode = BNX2X_RX_MODE_NONE;\n\tbnx2x_set_rx_mode(sc);\n\tmb();\n\n\tif (IS_PF(sc)) {\n\t\t/* set ALWAYS_ALIVE bit in shmem */\n\t\tsc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;\n\n\t\tbnx2x_drv_pulse(sc);\n\n\t\tbnx2x_stats_handle(sc, STATS_EVENT_STOP);\n\t\tbnx2x_save_statistics(sc);\n\t}\n\n\t/* wait till consumers catch up with producers in all queues */\n\tbnx2x_drain_tx_queues(sc);\n\n\t/* if VF indicate to PF this function is going down (PF will delete sp\n\t * elements and clear initializations\n\t */\n\tif (IS_VF(sc)) {\n\t\tbnx2x_vf_unload(sc);\n\t} else if (unload_mode != UNLOAD_RECOVERY) {\n\t\t/* if this is a normal/close unload need to clean up chip */\n\t\tbnx2x_chip_cleanup(sc, unload_mode, keep_link);\n\t} else {\n\t\t/* Send the UNLOAD_REQUEST to the MCP */\n\t\tbnx2x_send_unload_req(sc, unload_mode);\n\n\t\t/*\n\t\t * Prevent transactions to host from the functions on the\n\t\t * engine that doesn't reset global blocks in case of global\n\t\t * attention once gloabl blocks are reset and gates are opened\n\t\t * (the engine which leader will perform the recovery\n\t\t * last).\n\t\t */\n\t\tif (!CHIP_IS_E1x(sc)) {\n\t\t\tbnx2x_pf_disable(sc);\n\t\t}\n\n\t\t/* disable HW interrupts */\n\t\tbnx2x_int_disable_sync(sc, TRUE);\n\n\t\t/* Report UNLOAD_DONE to MCP */\n\t\tbnx2x_send_unload_done(sc, FALSE);\n\t}\n\n\t/*\n\t * At this stage no more interrupts will arrive so we may safely clean\n\t * the queue'able objects here in case they failed to get cleaned so far.\n\t */\n\tif (IS_PF(sc)) {\n\t\tbnx2x_squeeze_objects(sc);\n\t}\n\n\t/* There should be no more pending SP commands at this stage */\n\tsc->sp_state = 0;\n\n\tsc->port.pmf = 0;\n\n\tif (IS_PF(sc)) {\n\t\tbnx2x_free_mem(sc);\n\t}\n\n\tbnx2x_free_fw_stats_mem(sc);\n\n\tsc->state = BNX2X_STATE_CLOSED;\n\n\t/*\n\t * Check if there are pending parity attentions. If there are - set\n\t * RECOVERY_IN_PROGRESS.\n\t */\n\tif (IS_PF(sc) && bnx2x_chk_parity_attn(sc, &global, FALSE)) {\n\t\tbnx2x_set_reset_in_progress(sc);\n\n\t\t/* Set RESET_IS_GLOBAL if needed */\n\t\tif (global) {\n\t\t\tbnx2x_set_reset_global(sc);\n\t\t}\n\t}\n\n\t/*\n\t * The last driver must disable a \"close the gate\" if there is no\n\t * parity attention or \"process kill\" pending.\n\t */\n\tif (IS_PF(sc) && !bnx2x_clear_pf_load(sc) &&\n\t bnx2x_reset_is_done(sc, SC_PATH(sc))) {\n\t\tbnx2x_disable_close_the_gate(sc);\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"Ended NIC unload\");\n\n\treturn 0;\n}\n\n/*\n * Encapsulte an mbuf cluster into the tx bd chain and makes the memory\n * visible to the controller.\n *\n * If an mbuf is submitted to this routine and cannot be given to the\n * controller (e.g. it has too many fragments) then the function may free\n * the mbuf and return to the caller.\n *\n * Returns:\n * 0 = Success, !0 = Failure\n * Note the side effect that an mbuf may be freed if it causes a problem.\n */\nint bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf **m_head, int m_pkts)\n{\n\tstruct rte_mbuf *m0;\n\tstruct eth_tx_start_bd *tx_start_bd;\n\tuint16_t bd_prod, pkt_prod;\n\tint m_tx;\n\tstruct bnx2x_softc *sc;\n\tuint32_t nbds = 0;\n\tstruct bnx2x_fastpath *fp;\n\n\tsc = txq->sc;\n\tfp = &sc->fp[txq->queue_id];\n\n\tbd_prod = txq->tx_bd_tail;\n\tpkt_prod = txq->tx_pkt_tail;\n\n\tfor (m_tx = 0; m_tx < m_pkts; m_tx++) {\n\n\t\tm0 = *m_head++;\n\n\t\tif (unlikely(txq->nb_tx_avail < 3)) {\n\t\t\tPMD_TX_LOG(ERR, \"no enough bds %d/%d\",\n\t\t\t\t bd_prod, txq->nb_tx_avail);\n\t\t\treturn -ENOMEM;\n\t\t}\n\n\t\ttxq->sw_ring[TX_BD(pkt_prod, txq)] = m0;\n\n\t\ttx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;\n\n\t\ttx_start_bd->addr =\n\t\t rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR(m0));\n\t\ttx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);\n\t\ttx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;\n\t\ttx_start_bd->general_data =\n\t\t (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);\n\n\t\ttx_start_bd->nbd = rte_cpu_to_le_16(2);\n\n\t\tif (m0->ol_flags & PKT_TX_VLAN_PKT) {\n\t\t\ttx_start_bd->vlan_or_ethertype =\n\t\t\t rte_cpu_to_le_16(m0->vlan_tci);\n\t\t\ttx_start_bd->bd_flags.as_bitfield |=\n\t\t\t (X_ETH_OUTBAND_VLAN <<\n\t\t\t ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);\n\t\t} else {\n\t\t\tif (IS_PF(sc))\n\t\t\t\ttx_start_bd->vlan_or_ethertype =\n\t\t\t\t rte_cpu_to_le_16(pkt_prod);\n\t\t\telse {\n\t\t\t\tstruct ether_hdr *eh\n\t\t\t\t = rte_pktmbuf_mtod(m0, struct ether_hdr *);\n\n\t\t\t\ttx_start_bd->vlan_or_ethertype = eh->ether_type;\n\t\t\t}\n\t\t}\n\n\t\tbd_prod = NEXT_TX_BD(bd_prod);\n\t\tif (IS_VF(sc)) {\n\t\t\tstruct eth_tx_parse_bd_e2 *tx_parse_bd;\n\t\t\tuint8_t *data = rte_pktmbuf_mtod(m0, uint8_t *);\n\n\t\t\ttx_parse_bd =\n\t\t\t &txq->tx_ring[TX_BD(bd_prod, txq)].parse_bd_e2;\n\t\t\ttx_parse_bd->parsing_data =\n\t\t\t (1 << ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);\n\n\t\t\trte_memcpy(&tx_parse_bd->data.mac_addr.dst_hi,\n\t\t\t\t &data[0], 2);\n\t\t\trte_memcpy(&tx_parse_bd->data.mac_addr.dst_mid,\n\t\t\t\t &data[2], 2);\n\t\t\trte_memcpy(&tx_parse_bd->data.mac_addr.dst_lo,\n\t\t\t\t &data[4], 2);\n\t\t\trte_memcpy(&tx_parse_bd->data.mac_addr.src_hi,\n\t\t\t\t &data[6], 2);\n\t\t\trte_memcpy(&tx_parse_bd->data.mac_addr.src_mid,\n\t\t\t\t &data[8], 2);\n\t\t\trte_memcpy(&tx_parse_bd->data.mac_addr.src_lo,\n\t\t\t\t &data[10], 2);\n\n\t\t\ttx_parse_bd->data.mac_addr.dst_hi =\n\t\t\t rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_hi);\n\t\t\ttx_parse_bd->data.mac_addr.dst_mid =\n\t\t\t rte_cpu_to_be_16(tx_parse_bd->data.\n\t\t\t\t\t mac_addr.dst_mid);\n\t\t\ttx_parse_bd->data.mac_addr.dst_lo =\n\t\t\t rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.dst_lo);\n\t\t\ttx_parse_bd->data.mac_addr.src_hi =\n\t\t\t rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_hi);\n\t\t\ttx_parse_bd->data.mac_addr.src_mid =\n\t\t\t rte_cpu_to_be_16(tx_parse_bd->data.\n\t\t\t\t\t mac_addr.src_mid);\n\t\t\ttx_parse_bd->data.mac_addr.src_lo =\n\t\t\t rte_cpu_to_be_16(tx_parse_bd->data.mac_addr.src_lo);\n\n\t\t\tPMD_TX_LOG(DEBUG,\n\t\t\t\t \"PBD dst %x %x %x src %x %x %x p_data %x\",\n\t\t\t\t tx_parse_bd->data.mac_addr.dst_hi,\n\t\t\t\t tx_parse_bd->data.mac_addr.dst_mid,\n\t\t\t\t tx_parse_bd->data.mac_addr.dst_lo,\n\t\t\t\t tx_parse_bd->data.mac_addr.src_hi,\n\t\t\t\t tx_parse_bd->data.mac_addr.src_mid,\n\t\t\t\t tx_parse_bd->data.mac_addr.src_lo,\n\t\t\t\t tx_parse_bd->parsing_data);\n\t\t}\n\n\t\tPMD_TX_LOG(DEBUG,\n\t\t\t \"start bd: nbytes %d flags %x vlan %x\\n\",\n\t\t\t tx_start_bd->nbytes,\n\t\t\t tx_start_bd->bd_flags.as_bitfield,\n\t\t\t tx_start_bd->vlan_or_ethertype);\n\n\t\tbd_prod = NEXT_TX_BD(bd_prod);\n\t\tpkt_prod++;\n\n\t\tif (TX_IDX(bd_prod) < 2) {\n\t\t\tnbds++;\n\t\t}\n\t}\n\n\ttxq->nb_tx_avail -= m_pkts << 1;\n\ttxq->tx_bd_tail = bd_prod;\n\ttxq->tx_pkt_tail = pkt_prod;\n\n\tmb();\n\tfp->tx_db.data.prod += (m_pkts << 1) + nbds;\n\tDOORBELL(sc, txq->queue_id, fp->tx_db.raw);\n\tmb();\n\n\treturn 0;\n}\n\nstatic uint16_t bnx2x_cid_ilt_lines(struct bnx2x_softc *sc)\n{\n\treturn L2_ILT_LINES(sc);\n}\n\nstatic void bnx2x_ilt_set_info(struct bnx2x_softc *sc)\n{\n\tstruct ilt_client_info *ilt_client;\n\tstruct ecore_ilt *ilt = sc->ilt;\n\tuint16_t line = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));\n\n\t/* CDU */\n\tilt_client = &ilt->clients[ILT_CLIENT_CDU];\n\tilt_client->client_num = ILT_CLIENT_CDU;\n\tilt_client->page_size = CDU_ILT_PAGE_SZ;\n\tilt_client->flags = ILT_CLIENT_SKIP_MEM;\n\tilt_client->start = line;\n\tline += bnx2x_cid_ilt_lines(sc);\n\n\tif (CNIC_SUPPORT(sc)) {\n\t\tline += CNIC_ILT_LINES;\n\t}\n\n\tilt_client->end = (line - 1);\n\n\t/* QM */\n\tif (QM_INIT(sc->qm_cid_count)) {\n\t\tilt_client = &ilt->clients[ILT_CLIENT_QM];\n\t\tilt_client->client_num = ILT_CLIENT_QM;\n\t\tilt_client->page_size = QM_ILT_PAGE_SZ;\n\t\tilt_client->flags = 0;\n\t\tilt_client->start = line;\n\n\t\t/* 4 bytes for each cid */\n\t\tline += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,\n\t\t\t\t QM_ILT_PAGE_SZ);\n\n\t\tilt_client->end = (line - 1);\n\t}\n\n\tif (CNIC_SUPPORT(sc)) {\n\t\t/* SRC */\n\t\tilt_client = &ilt->clients[ILT_CLIENT_SRC];\n\t\tilt_client->client_num = ILT_CLIENT_SRC;\n\t\tilt_client->page_size = SRC_ILT_PAGE_SZ;\n\t\tilt_client->flags = 0;\n\t\tilt_client->start = line;\n\t\tline += SRC_ILT_LINES;\n\t\tilt_client->end = (line - 1);\n\n\t\t/* TM */\n\t\tilt_client = &ilt->clients[ILT_CLIENT_TM];\n\t\tilt_client->client_num = ILT_CLIENT_TM;\n\t\tilt_client->page_size = TM_ILT_PAGE_SZ;\n\t\tilt_client->flags = 0;\n\t\tilt_client->start = line;\n\t\tline += TM_ILT_LINES;\n\t\tilt_client->end = (line - 1);\n\t}\n\n\tassert((line <= ILT_MAX_LINES));\n}\n\nstatic void bnx2x_set_fp_rx_buf_size(struct bnx2x_softc *sc)\n{\n\tint i;\n\n\tfor (i = 0; i < sc->num_queues; i++) {\n\t\t/* get the Rx buffer size for RX frames */\n\t\tsc->fp[i].rx_buf_size =\n\t\t (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);\n\n\t\t/* get the mbuf allocation size for RX frames */\n\t\tif (sc->fp[i].rx_buf_size <= MCLBYTES) {\n\t\t\tsc->fp[i].mbuf_alloc_size = MCLBYTES;\n\t\t} else if (sc->fp[i].rx_buf_size <= BNX2X_PAGE_SIZE) {\n\t\t\tsc->fp[i].mbuf_alloc_size = PAGE_SIZE;\n\t\t} else {\n\t\t\tsc->fp[i].mbuf_alloc_size = MJUM9BYTES;\n\t\t}\n\t}\n}\n\nint bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc)\n{\n\n\tsc->ilt = rte_malloc(\"\", sizeof(struct ecore_ilt), RTE_CACHE_LINE_SIZE);\n\n\treturn sc->ilt == NULL;\n}\n\nstatic int bnx2x_alloc_ilt_lines_mem(struct bnx2x_softc *sc)\n{\n\tsc->ilt->lines = rte_calloc(\"\",\n\t\t\t\t sizeof(struct ilt_line), ILT_MAX_LINES,\n\t\t\t\t RTE_CACHE_LINE_SIZE);\n\treturn sc->ilt->lines == NULL;\n}\n\nvoid bnx2x_free_ilt_mem(struct bnx2x_softc *sc)\n{\n\trte_free(sc->ilt);\n\tsc->ilt = NULL;\n}\n\nstatic void bnx2x_free_ilt_lines_mem(struct bnx2x_softc *sc)\n{\n\tif (sc->ilt->lines != NULL) {\n\t\trte_free(sc->ilt->lines);\n\t\tsc->ilt->lines = NULL;\n\t}\n}\n\nstatic void bnx2x_free_mem(struct bnx2x_softc *sc)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < L2_ILT_LINES(sc); i++) {\n\t\tsc->context[i].vcxt = NULL;\n\t\tsc->context[i].size = 0;\n\t}\n\n\tecore_ilt_mem_op(sc, ILT_MEMOP_FREE);\n\n\tbnx2x_free_ilt_lines_mem(sc);\n}\n\nstatic int bnx2x_alloc_mem(struct bnx2x_softc *sc)\n{\n\tint context_size;\n\tint allocated;\n\tint i;\n\tchar cdu_name[RTE_MEMZONE_NAMESIZE];\n\n\t/*\n\t * Allocate memory for CDU context:\n\t * This memory is allocated separately and not in the generic ILT\n\t * functions because CDU differs in few aspects:\n\t * 1. There can be multiple entities allocating memory for context -\n\t * regular L2, CNIC, and SRIOV drivers. Each separately controls\n\t * its own ILT lines.\n\t * 2. Since CDU page-size is not a single 4KB page (which is the case\n\t * for the other ILT clients), to be efficient we want to support\n\t * allocation of sub-page-size in the last entry.\n\t * 3. Context pointers are used by the driver to pass to FW / update\n\t * the context (for the other ILT clients the pointers are used just to\n\t * free the memory during unload).\n\t */\n\tcontext_size = (sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(sc));\n\tfor (i = 0, allocated = 0; allocated < context_size; i++) {\n\t\tsc->context[i].size = min(CDU_ILT_PAGE_SZ,\n\t\t\t\t\t (context_size - allocated));\n\n\t\tsnprintf(cdu_name, sizeof(cdu_name), \"cdu_%d\", i);\n\t\tif (bnx2x_dma_alloc(sc, sc->context[i].size,\n\t\t\t\t &sc->context[i].vcxt_dma,\n\t\t\t\t cdu_name, BNX2X_PAGE_SIZE) != 0) {\n\t\t\tbnx2x_free_mem(sc);\n\t\t\treturn -1;\n\t\t}\n\n\t\tsc->context[i].vcxt =\n\t\t (union cdu_context *)sc->context[i].vcxt_dma.vaddr;\n\n\t\tallocated += sc->context[i].size;\n\t}\n\n\tbnx2x_alloc_ilt_lines_mem(sc);\n\n\tif (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {\n\t\tPMD_DRV_LOG(NOTICE, \"ecore_ilt_mem_op ILT_MEMOP_ALLOC failed\");\n\t\tbnx2x_free_mem(sc);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic void bnx2x_free_fw_stats_mem(struct bnx2x_softc *sc)\n{\n\tsc->fw_stats_num = 0;\n\n\tsc->fw_stats_req_size = 0;\n\tsc->fw_stats_req = NULL;\n\tsc->fw_stats_req_mapping = 0;\n\n\tsc->fw_stats_data_size = 0;\n\tsc->fw_stats_data = NULL;\n\tsc->fw_stats_data_mapping = 0;\n}\n\nstatic int bnx2x_alloc_fw_stats_mem(struct bnx2x_softc *sc)\n{\n\tuint8_t num_queue_stats;\n\tint num_groups, vf_headroom = 0;\n\n\t/* number of queues for statistics is number of eth queues */\n\tnum_queue_stats = BNX2X_NUM_ETH_QUEUES(sc);\n\n\t/*\n\t * Total number of FW statistics requests =\n\t * 1 for port stats + 1 for PF stats + num of queues\n\t */\n\tsc->fw_stats_num = (2 + num_queue_stats);\n\n\t/*\n\t * Request is built from stats_query_header and an array of\n\t * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT\n\t * rules. The real number or requests is configured in the\n\t * stats_query_header.\n\t */\n\tnum_groups = (sc->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT;\n\tif ((sc->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT)\n\t\tnum_groups++;\n\n\tsc->fw_stats_req_size =\n\t (sizeof(struct stats_query_header) +\n\t (num_groups * sizeof(struct stats_query_cmd_group)));\n\n\t/*\n\t * Data for statistics requests + stats_counter.\n\t * stats_counter holds per-STORM counters that are incremented when\n\t * STORM has finished with the current request. Memory for FCoE\n\t * offloaded statistics are counted anyway, even if they will not be sent.\n\t * VF stats are not accounted for here as the data of VF stats is stored\n\t * in memory allocated by the VF, not here.\n\t */\n\tsc->fw_stats_data_size =\n\t (sizeof(struct stats_counter) +\n\t sizeof(struct per_port_stats) + sizeof(struct per_pf_stats) +\n\t /* sizeof(struct fcoe_statistics_params) + */\n\t (sizeof(struct per_queue_stats) * num_queue_stats));\n\n\tif (bnx2x_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),\n\t\t\t &sc->fw_stats_dma, \"fw_stats\",\n\t\t\t RTE_CACHE_LINE_SIZE) != 0) {\n\t\tbnx2x_free_fw_stats_mem(sc);\n\t\treturn -1;\n\t}\n\n\t/* set up the shortcuts */\n\n\tsc->fw_stats_req = (struct bnx2x_fw_stats_req *)sc->fw_stats_dma.vaddr;\n\tsc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;\n\n\tsc->fw_stats_data =\n\t (struct bnx2x_fw_stats_data *)((uint8_t *) sc->fw_stats_dma.vaddr +\n\t\t\t\t\t sc->fw_stats_req_size);\n\tsc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +\n\t\t\t\t sc->fw_stats_req_size);\n\n\treturn 0;\n}\n\n/*\n * Bits map:\n * 0-7 - Engine0 load counter.\n * 8-15 - Engine1 load counter.\n * 16 - Engine0 RESET_IN_PROGRESS bit.\n * 17 - Engine1 RESET_IN_PROGRESS bit.\n * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active\n * function on the engine\n * 19 - Engine1 ONE_IS_LOADED.\n * 20 - Chip reset flow bit. When set none-leader must wait for both engines\n * leader to complete (check for both RESET_IN_PROGRESS bits and not\n * for just the one belonging to its engine).\n */\n#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1\n#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff\n#define BNX2X_PATH0_LOAD_CNT_SHIFT 0\n#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00\n#define BNX2X_PATH1_LOAD_CNT_SHIFT 8\n#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000\n#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000\n#define BNX2X_GLOBAL_RESET_BIT 0x00040000\n\n/* set the GLOBAL_RESET bit, should be run under rtnl lock */\nstatic void bnx2x_set_reset_global(struct bnx2x_softc *sc)\n{\n\tuint32_t val;\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);\n\tval = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);\n\tREG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);\n}\n\n/* clear the GLOBAL_RESET bit, should be run under rtnl lock */\nstatic void bnx2x_clear_reset_global(struct bnx2x_softc *sc)\n{\n\tuint32_t val;\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);\n\tval = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);\n\tREG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);\n}\n\n/* checks the GLOBAL_RESET bit, should be run under rtnl lock */\nstatic uint8_t bnx2x_reset_is_global(struct bnx2x_softc *sc)\n{\n\treturn (REG_RD(sc, BNX2X_RECOVERY_GLOB_REG) & BNX2X_GLOBAL_RESET_BIT);\n}\n\n/* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */\nstatic void bnx2x_set_reset_done(struct bnx2x_softc *sc)\n{\n\tuint32_t val;\n\tuint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :\n\t BNX2X_PATH0_RST_IN_PROG_BIT;\n\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);\n\n\tval = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);\n\t/* Clear the bit */\n\tval &= ~bit;\n\tREG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);\n\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);\n}\n\n/* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */\nstatic void bnx2x_set_reset_in_progress(struct bnx2x_softc *sc)\n{\n\tuint32_t val;\n\tuint32_t bit = SC_PATH(sc) ? BNX2X_PATH1_RST_IN_PROG_BIT :\n\t BNX2X_PATH0_RST_IN_PROG_BIT;\n\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);\n\n\tval = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);\n\t/* Set the bit */\n\tval |= bit;\n\tREG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);\n\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);\n}\n\n/* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */\nstatic uint8_t bnx2x_reset_is_done(struct bnx2x_softc *sc, int engine)\n{\n\tuint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);\n\tuint32_t bit = engine ? BNX2X_PATH1_RST_IN_PROG_BIT :\n\t BNX2X_PATH0_RST_IN_PROG_BIT;\n\n\t/* return false if bit is set */\n\treturn (val & bit) ? FALSE : TRUE;\n}\n\n/* get the load status for an engine, should be run under rtnl lock */\nstatic uint8_t bnx2x_get_load_status(struct bnx2x_softc *sc, int engine)\n{\n\tuint32_t mask = engine ? BNX2X_PATH1_LOAD_CNT_MASK :\n\t BNX2X_PATH0_LOAD_CNT_MASK;\n\tuint32_t shift = engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :\n\t BNX2X_PATH0_LOAD_CNT_SHIFT;\n\tuint32_t val = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);\n\n\tval = ((val & mask) >> shift);\n\n\treturn (val != 0);\n}\n\n/* set pf load mark */\nstatic void bnx2x_set_pf_load(struct bnx2x_softc *sc)\n{\n\tuint32_t val;\n\tuint32_t val1;\n\tuint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :\n\t BNX2X_PATH0_LOAD_CNT_MASK;\n\tuint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :\n\t BNX2X_PATH0_LOAD_CNT_SHIFT;\n\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tval = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);\n\n\t/* get the current counter value */\n\tval1 = ((val & mask) >> shift);\n\n\t/* set bit of this PF */\n\tval1 |= (1 << SC_ABS_FUNC(sc));\n\n\t/* clear the old value */\n\tval &= ~mask;\n\n\t/* set the new one */\n\tval |= ((val1 << shift) & mask);\n\n\tREG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);\n\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);\n}\n\n/* clear pf load mark */\nstatic uint8_t bnx2x_clear_pf_load(struct bnx2x_softc *sc)\n{\n\tuint32_t val1, val;\n\tuint32_t mask = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_MASK :\n\t BNX2X_PATH0_LOAD_CNT_MASK;\n\tuint32_t shift = SC_PATH(sc) ? BNX2X_PATH1_LOAD_CNT_SHIFT :\n\t BNX2X_PATH0_LOAD_CNT_SHIFT;\n\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);\n\tval = REG_RD(sc, BNX2X_RECOVERY_GLOB_REG);\n\n\t/* get the current counter value */\n\tval1 = (val & mask) >> shift;\n\n\t/* clear bit of that PF */\n\tval1 &= ~(1 << SC_ABS_FUNC(sc));\n\n\t/* clear the old value */\n\tval &= ~mask;\n\n\t/* set the new one */\n\tval |= ((val1 << shift) & mask);\n\n\tREG_WR(sc, BNX2X_RECOVERY_GLOB_REG, val);\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);\n\treturn val1 != 0;\n}\n\n/* send load requrest to mcp and analyze response */\nstatic int bnx2x_nic_load_request(struct bnx2x_softc *sc, uint32_t * load_code)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* init fw_seq */\n\tsc->fw_seq =\n\t (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &\n\t DRV_MSG_SEQ_NUMBER_MASK);\n\n\tPMD_DRV_LOG(DEBUG, \"initial fw_seq 0x%04x\", sc->fw_seq);\n\n#ifdef BNX2X_PULSE\n\t/* get the current FW pulse sequence */\n\tsc->fw_drv_pulse_wr_seq =\n\t (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &\n\t DRV_PULSE_SEQ_MASK);\n#else\n\t/* set ALWAYS_ALIVE bit in shmem */\n\tsc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;\n\tbnx2x_drv_pulse(sc);\n#endif\n\n\t/* load request */\n\t(*load_code) = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,\n\t\t\t\t DRV_MSG_CODE_LOAD_REQ_WITH_LFA);\n\n\t/* if the MCP fails to respond we must abort */\n\tif (!(*load_code)) {\n\t\tPMD_DRV_LOG(NOTICE, \"MCP response failure!\");\n\t\treturn -1;\n\t}\n\n\t/* if MCP refused then must abort */\n\tif ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {\n\t\tPMD_DRV_LOG(NOTICE, \"MCP refused load request\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Check whether another PF has already loaded FW to chip. In virtualized\n * environments a pf from anoth VM may have already initialized the device\n * including loading FW.\n */\nstatic int bnx2x_nic_load_analyze_req(struct bnx2x_softc *sc, uint32_t load_code)\n{\n\tuint32_t my_fw, loaded_fw;\n\n\t/* is another pf loaded on this engine? */\n\tif ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&\n\t (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {\n\t\t/* build my FW version dword */\n\t\tmy_fw = (BNX2X_5710_FW_MAJOR_VERSION +\n\t\t\t (BNX2X_5710_FW_MINOR_VERSION << 8) +\n\t\t\t (BNX2X_5710_FW_REVISION_VERSION << 16) +\n\t\t\t (BNX2X_5710_FW_ENGINEERING_VERSION << 24));\n\n\t\t/* read loaded FW from chip */\n\t\tloaded_fw = REG_RD(sc, XSEM_REG_PRAM);\n\t\tPMD_DRV_LOG(DEBUG, \"loaded FW 0x%08x / my FW 0x%08x\",\n\t\t\t loaded_fw, my_fw);\n\n\t\t/* abort nic load if version mismatch */\n\t\tif (my_fw != loaded_fw) {\n\t\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t\t \"FW 0x%08x already loaded (mine is 0x%08x)\",\n\t\t\t\t loaded_fw, my_fw);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/* mark PMF if applicable */\nstatic void bnx2x_nic_load_pmf(struct bnx2x_softc *sc, uint32_t load_code)\n{\n\tuint32_t ncsi_oem_data_addr;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||\n\t (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||\n\t (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {\n\t\t/*\n\t\t * Barrier here for ordering between the writing to sc->port.pmf here\n\t\t * and reading it from the periodic task.\n\t\t */\n\t\tsc->port.pmf = 1;\n\t\tmb();\n\t} else {\n\t\tsc->port.pmf = 0;\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"pmf %d\", sc->port.pmf);\n\n\tif (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {\n\t\tif (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {\n\t\t\tncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);\n\t\t\tif (ncsi_oem_data_addr) {\n\t\t\t\tREG_WR(sc,\n\t\t\t\t (ncsi_oem_data_addr +\n\t\t\t\t\toffsetof(struct glob_ncsi_oem_data,\n\t\t\t\t\t\t driver_version)), 0);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void bnx2x_read_mf_cfg(struct bnx2x_softc *sc)\n{\n\tint n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);\n\tint abs_func;\n\tint vn;\n\n\tif (BNX2X_NOMCP(sc)) {\n\t\treturn;\t\t/* what should be the default bvalue in this case */\n\t}\n\n\t/*\n\t * The formula for computing the absolute function number is...\n\t * For 2 port configuration (4 functions per port):\n\t * abs_func = 2 * vn + SC_PORT + SC_PATH\n\t * For 4 port configuration (2 functions per port):\n\t * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH\n\t */\n\tfor (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {\n\t\tabs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));\n\t\tif (abs_func >= E1H_FUNC_MAX) {\n\t\t\tbreak;\n\t\t}\n\t\tsc->devinfo.mf_info.mf_config[vn] =\n\t\t MFCFG_RD(sc, func_mf_config[abs_func].config);\n\t}\n\n\tif (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &\n\t FUNC_MF_CFG_FUNC_DISABLED) {\n\t\tPMD_DRV_LOG(DEBUG, \"mf_cfg function disabled\");\n\t\tsc->flags |= BNX2X_MF_FUNC_DIS;\n\t} else {\n\t\tPMD_DRV_LOG(DEBUG, \"mf_cfg function enabled\");\n\t\tsc->flags &= ~BNX2X_MF_FUNC_DIS;\n\t}\n}\n\n/* acquire split MCP access lock register */\nstatic int bnx2x_acquire_alr(struct bnx2x_softc *sc)\n{\n\tuint32_t j, val;\n\n\tfor (j = 0; j < 1000; j++) {\n\t\tval = (1UL << 31);\n\t\tREG_WR(sc, GRCBASE_MCP + 0x9c, val);\n\t\tval = REG_RD(sc, GRCBASE_MCP + 0x9c);\n\t\tif (val & (1L << 31))\n\t\t\tbreak;\n\n\t\tDELAY(5000);\n\t}\n\n\tif (!(val & (1L << 31))) {\n\t\tPMD_DRV_LOG(NOTICE, \"Cannot acquire MCP access lock register\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* release split MCP access lock register */\nstatic void bnx2x_release_alr(struct bnx2x_softc *sc)\n{\n\tREG_WR(sc, GRCBASE_MCP + 0x9c, 0);\n}\n\nstatic void bnx2x_fan_failure(struct bnx2x_softc *sc)\n{\n\tint port = SC_PORT(sc);\n\tuint32_t ext_phy_config;\n\n\t/* mark the failure */\n\text_phy_config =\n\t SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);\n\n\text_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;\n\text_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;\n\tSHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,\n\t\t ext_phy_config);\n\n\t/* log the failure */\n\tPMD_DRV_LOG(INFO,\n\t\t \"Fan Failure has caused the driver to shutdown \"\n\t\t \"the card to prevent permanent damage. \"\n\t\t \"Please contact OEM Support for assistance\");\n\n\trte_panic(\"Schedule task to handle fan failure\");\n}\n\n/* this function is called upon a link interrupt */\nstatic void bnx2x_link_attn(struct bnx2x_softc *sc)\n{\n\tuint32_t pause_enabled = 0;\n\tstruct host_port_stats *pstats;\n\tint cmng_fns;\n\n\t/* Make sure that we are synced with the current statistics */\n\tbnx2x_stats_handle(sc, STATS_EVENT_STOP);\n\n\telink_link_update(&sc->link_params, &sc->link_vars);\n\n\tif (sc->link_vars.link_up) {\n\n\t\t/* dropless flow control */\n\t\tif (sc->dropless_fc) {\n\t\t\tpause_enabled = 0;\n\n\t\t\tif (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {\n\t\t\t\tpause_enabled = 1;\n\t\t\t}\n\n\t\t\tREG_WR(sc,\n\t\t\t (BAR_USTRORM_INTMEM +\n\t\t\t\tUSTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),\n\t\t\t pause_enabled);\n\t\t}\n\n\t\tif (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {\n\t\t\tpstats = BNX2X_SP(sc, port_stats);\n\t\t\t/* reset old mac stats */\n\t\t\tmemset(&(pstats->mac_stx[0]), 0,\n\t\t\t sizeof(struct mac_stx));\n\t\t}\n\n\t\tif (sc->state == BNX2X_STATE_OPEN) {\n\t\t\tbnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);\n\t\t}\n\t}\n\n\tif (sc->link_vars.link_up && sc->link_vars.line_speed) {\n\t\tcmng_fns = bnx2x_get_cmng_fns_mode(sc);\n\n\t\tif (cmng_fns != CMNG_FNS_NONE) {\n\t\t\tbnx2x_cmng_fns_init(sc, FALSE, cmng_fns);\n\t\t\tstorm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));\n\t\t}\n\t}\n\n\tbnx2x_link_report(sc);\n\n\tif (IS_MF(sc)) {\n\t\tbnx2x_link_sync_notify(sc);\n\t}\n}\n\nstatic void bnx2x_attn_int_asserted(struct bnx2x_softc *sc, uint32_t asserted)\n{\n\tint port = SC_PORT(sc);\n\tuint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :\n\t MISC_REG_AEU_MASK_ATTN_FUNC_0;\n\tuint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :\n\t NIG_REG_MASK_INTERRUPT_PORT0;\n\tuint32_t aeu_mask;\n\tuint32_t nig_mask = 0;\n\tuint32_t reg_addr;\n\tuint32_t igu_acked;\n\tuint32_t cnt;\n\n\tif (sc->attn_state & asserted) {\n\t\tPMD_DRV_LOG(ERR, \"IGU ERROR attn=0x%08x\", asserted);\n\t}\n\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);\n\n\taeu_mask = REG_RD(sc, aeu_addr);\n\n\taeu_mask &= ~(asserted & 0x3ff);\n\n\tREG_WR(sc, aeu_addr, aeu_mask);\n\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);\n\n\tsc->attn_state |= asserted;\n\n\tif (asserted & ATTN_HARD_WIRED_MASK) {\n\t\tif (asserted & ATTN_NIG_FOR_FUNC) {\n\n\t\t\t/* save nig interrupt mask */\n\t\t\tnig_mask = REG_RD(sc, nig_int_mask_addr);\n\n\t\t\t/* If nig_mask is not set, no need to call the update function */\n\t\t\tif (nig_mask) {\n\t\t\t\tREG_WR(sc, nig_int_mask_addr, 0);\n\n\t\t\t\tbnx2x_link_attn(sc);\n\t\t\t}\n\n\t\t\t/* handle unicore attn? */\n\t\t}\n\n\t\tif (asserted & ATTN_SW_TIMER_4_FUNC) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"ATTN_SW_TIMER_4_FUNC!\");\n\t\t}\n\n\t\tif (asserted & GPIO_2_FUNC) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"GPIO_2_FUNC!\");\n\t\t}\n\n\t\tif (asserted & GPIO_3_FUNC) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"GPIO_3_FUNC!\");\n\t\t}\n\n\t\tif (asserted & GPIO_4_FUNC) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"GPIO_4_FUNC!\");\n\t\t}\n\n\t\tif (port == 0) {\n\t\t\tif (asserted & ATTN_GENERAL_ATTN_1) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"ATTN_GENERAL_ATTN_1!\");\n\t\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);\n\t\t\t}\n\t\t\tif (asserted & ATTN_GENERAL_ATTN_2) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"ATTN_GENERAL_ATTN_2!\");\n\t\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);\n\t\t\t}\n\t\t\tif (asserted & ATTN_GENERAL_ATTN_3) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"ATTN_GENERAL_ATTN_3!\");\n\t\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);\n\t\t\t}\n\t\t} else {\n\t\t\tif (asserted & ATTN_GENERAL_ATTN_4) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"ATTN_GENERAL_ATTN_4!\");\n\t\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);\n\t\t\t}\n\t\t\tif (asserted & ATTN_GENERAL_ATTN_5) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"ATTN_GENERAL_ATTN_5!\");\n\t\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);\n\t\t\t}\n\t\t\tif (asserted & ATTN_GENERAL_ATTN_6) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"ATTN_GENERAL_ATTN_6!\");\n\t\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);\n\t\t\t}\n\t\t}\n\t}\n\t/* hardwired */\n\tif (sc->devinfo.int_block == INT_BLOCK_HC) {\n\t\treg_addr =\n\t\t (HC_REG_COMMAND_REG + port * 32 +\n\t\t COMMAND_REG_ATTN_BITS_SET);\n\t} else {\n\t\treg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER * 8);\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"about to mask 0x%08x at %s addr 0x%08x\",\n\t\t asserted,\n\t\t (sc->devinfo.int_block == INT_BLOCK_HC) ? \"HC\" : \"IGU\",\n\t\t reg_addr);\n\tREG_WR(sc, reg_addr, asserted);\n\n\t/* now set back the mask */\n\tif (asserted & ATTN_NIG_FOR_FUNC) {\n\t\t/*\n\t\t * Verify that IGU ack through BAR was written before restoring\n\t\t * NIG mask. This loop should exit after 2-3 iterations max.\n\t\t */\n\t\tif (sc->devinfo.int_block != INT_BLOCK_HC) {\n\t\t\tcnt = 0;\n\n\t\t\tdo {\n\t\t\t\tigu_acked =\n\t\t\t\t REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);\n\t\t\t} while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0)\n\t\t\t\t && (++cnt < MAX_IGU_ATTN_ACK_TO));\n\n\t\t\tif (!igu_acked) {\n\t\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\t \"Failed to verify IGU ack on time\");\n\t\t\t}\n\n\t\t\tmb();\n\t\t}\n\n\t\tREG_WR(sc, nig_int_mask_addr, nig_mask);\n\n\t}\n}\n\nstatic void\nbnx2x_print_next_block(__rte_unused struct bnx2x_softc *sc, __rte_unused int idx,\n\t\t __rte_unused const char *blk)\n{\n\tPMD_DRV_LOG(INFO, \"%s%s\", idx ? \", \" : \"\", blk);\n}\n\nstatic int\nbnx2x_check_blocks_with_parity0(struct bnx2x_softc *sc, uint32_t sig, int par_num,\n\t\t\t uint8_t print)\n{\n\tuint32_t cur_bit = 0;\n\tint i = 0;\n\n\tfor (i = 0; sig; i++) {\n\t\tcur_bit = ((uint32_t) 0x1 << i);\n\t\tif (sig & cur_bit) {\n\t\t\tswitch (cur_bit) {\n\t\t\tcase AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"BRB\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"PARSER\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"TSDM\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"SEARCHER\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"TCM\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"TSEMI\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"XPB\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* Clear the bit */\n\t\t\tsig &= ~cur_bit;\n\t\t}\n\t}\n\n\treturn par_num;\n}\n\nstatic int\nbnx2x_check_blocks_with_parity1(struct bnx2x_softc *sc, uint32_t sig, int par_num,\n\t\t\t uint8_t * global, uint8_t print)\n{\n\tint i = 0;\n\tuint32_t cur_bit = 0;\n\tfor (i = 0; sig; i++) {\n\t\tcur_bit = ((uint32_t) 0x1 << i);\n\t\tif (sig & cur_bit) {\n\t\t\tswitch (cur_bit) {\n\t\t\tcase AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"PBF\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"QM\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"TM\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"XSDM\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"XCM\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"XSEMI\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"DOORBELLQ\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"NIG\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"VAUX PCI CORE\");\n\t\t\t\t*global = TRUE;\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"DEBUG\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"USDM\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"UCM\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"USEMI\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"UPB\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"CSDM\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"CCM\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* Clear the bit */\n\t\t\tsig &= ~cur_bit;\n\t\t}\n\t}\n\n\treturn par_num;\n}\n\nstatic int\nbnx2x_check_blocks_with_parity2(struct bnx2x_softc *sc, uint32_t sig, int par_num,\n\t\t\t uint8_t print)\n{\n\tuint32_t cur_bit = 0;\n\tint i = 0;\n\n\tfor (i = 0; sig; i++) {\n\t\tcur_bit = ((uint32_t) 0x1 << i);\n\t\tif (sig & cur_bit) {\n\t\t\tswitch (cur_bit) {\n\t\t\tcase AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"CSEMI\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"PXP\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"PXPPCICLOCKCLIENT\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"CFC\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"CDU\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"DMAE\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"IGU\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"MISC\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* Clear the bit */\n\t\t\tsig &= ~cur_bit;\n\t\t}\n\t}\n\n\treturn par_num;\n}\n\nstatic int\nbnx2x_check_blocks_with_parity3(struct bnx2x_softc *sc, uint32_t sig, int par_num,\n\t\t\t uint8_t * global, uint8_t print)\n{\n\tuint32_t cur_bit = 0;\n\tint i = 0;\n\n\tfor (i = 0; sig; i++) {\n\t\tcur_bit = ((uint32_t) 0x1 << i);\n\t\tif (sig & cur_bit) {\n\t\t\tswitch (cur_bit) {\n\t\t\tcase AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"MCP ROM\");\n\t\t\t\t*global = TRUE;\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"MCP UMP RX\");\n\t\t\t\t*global = TRUE;\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"MCP UMP TX\");\n\t\t\t\t*global = TRUE;\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"MCP SCPAD\");\n\t\t\t\t*global = TRUE;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* Clear the bit */\n\t\t\tsig &= ~cur_bit;\n\t\t}\n\t}\n\n\treturn par_num;\n}\n\nstatic int\nbnx2x_check_blocks_with_parity4(struct bnx2x_softc *sc, uint32_t sig, int par_num,\n\t\t\t uint8_t print)\n{\n\tuint32_t cur_bit = 0;\n\tint i = 0;\n\n\tfor (i = 0; sig; i++) {\n\t\tcur_bit = ((uint32_t) 0x1 << i);\n\t\tif (sig & cur_bit) {\n\t\t\tswitch (cur_bit) {\n\t\t\tcase AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"PGLUE_B\");\n\t\t\t\tbreak;\n\t\t\tcase AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:\n\t\t\t\tif (print)\n\t\t\t\t\tbnx2x_print_next_block(sc, par_num++,\n\t\t\t\t\t\t\t \"ATC\");\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* Clear the bit */\n\t\t\tsig &= ~cur_bit;\n\t\t}\n\t}\n\n\treturn par_num;\n}\n\nstatic uint8_t\nbnx2x_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print,\n\t\tuint32_t * sig)\n{\n\tint par_num = 0;\n\n\tif ((sig[0] & HW_PRTY_ASSERT_SET_0) ||\n\t (sig[1] & HW_PRTY_ASSERT_SET_1) ||\n\t (sig[2] & HW_PRTY_ASSERT_SET_2) ||\n\t (sig[3] & HW_PRTY_ASSERT_SET_3) ||\n\t (sig[4] & HW_PRTY_ASSERT_SET_4)) {\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"Parity error: HW block parity attention:\"\n\t\t\t \"[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\",\n\t\t\t (uint32_t) (sig[0] & HW_PRTY_ASSERT_SET_0),\n\t\t\t (uint32_t) (sig[1] & HW_PRTY_ASSERT_SET_1),\n\t\t\t (uint32_t) (sig[2] & HW_PRTY_ASSERT_SET_2),\n\t\t\t (uint32_t) (sig[3] & HW_PRTY_ASSERT_SET_3),\n\t\t\t (uint32_t) (sig[4] & HW_PRTY_ASSERT_SET_4));\n\n\t\tif (print)\n\t\t\tPMD_DRV_LOG(INFO, \"Parity errors detected in blocks: \");\n\n\t\tpar_num =\n\t\t bnx2x_check_blocks_with_parity0(sc, sig[0] &\n\t\t\t\t\t\t HW_PRTY_ASSERT_SET_0,\n\t\t\t\t\t\t par_num, print);\n\t\tpar_num =\n\t\t bnx2x_check_blocks_with_parity1(sc, sig[1] &\n\t\t\t\t\t\t HW_PRTY_ASSERT_SET_1,\n\t\t\t\t\t\t par_num, global, print);\n\t\tpar_num =\n\t\t bnx2x_check_blocks_with_parity2(sc, sig[2] &\n\t\t\t\t\t\t HW_PRTY_ASSERT_SET_2,\n\t\t\t\t\t\t par_num, print);\n\t\tpar_num =\n\t\t bnx2x_check_blocks_with_parity3(sc, sig[3] &\n\t\t\t\t\t\t HW_PRTY_ASSERT_SET_3,\n\t\t\t\t\t\t par_num, global, print);\n\t\tpar_num =\n\t\t bnx2x_check_blocks_with_parity4(sc, sig[4] &\n\t\t\t\t\t\t HW_PRTY_ASSERT_SET_4,\n\t\t\t\t\t\t par_num, print);\n\n\t\tif (print)\n\t\t\tPMD_DRV_LOG(INFO, \"\");\n\n\t\treturn TRUE;\n\t}\n\n\treturn FALSE;\n}\n\nstatic uint8_t\nbnx2x_chk_parity_attn(struct bnx2x_softc *sc, uint8_t * global, uint8_t print)\n{\n\tstruct attn_route attn = { {0} };\n\tint port = SC_PORT(sc);\n\n\tattn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);\n\tattn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);\n\tattn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);\n\tattn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);\n\n\tif (!CHIP_IS_E1x(sc))\n\t\tattn.sig[4] =\n\t\t REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);\n\n\treturn bnx2x_parity_attn(sc, global, print, attn.sig);\n}\n\nstatic void bnx2x_attn_int_deasserted4(struct bnx2x_softc *sc, uint32_t attn)\n{\n\tuint32_t val;\n\n\tif (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {\n\t\tval = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);\n\t\tPMD_DRV_LOG(INFO, \"ERROR: PGLUE hw attention 0x%08x\", val);\n\t\tif (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\");\n\t\tif (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\");\n\t\tif (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\");\n\t\tif (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\");\n\t\tif (val &\n\t\t PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\");\n\t\tif (val &\n\t\t PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\");\n\t\tif (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\");\n\t\tif (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\");\n\t\tif (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\");\n\t}\n\n\tif (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {\n\t\tval = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);\n\t\tPMD_DRV_LOG(INFO, \"ERROR: ATC hw attention 0x%08x\", val);\n\t\tif (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: ATC_ATC_INT_STS_REG_ADDRESS_ERROR\");\n\t\tif (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\");\n\t\tif (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\");\n\t\tif (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\");\n\t\tif (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\");\n\t\tif (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"ERROR: ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\");\n\t}\n\n\tif (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |\n\t\t AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {\n\t\tPMD_DRV_LOG(INFO,\n\t\t\t \"ERROR: FATAL parity attention set4 0x%08x\",\n\t\t\t (uint32_t) (attn &\n\t\t\t\t\t(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR\n\t\t\t\t\t |\n\t\t\t\t\t AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));\n\t}\n}\n\nstatic void bnx2x_e1h_disable(struct bnx2x_softc *sc)\n{\n\tint port = SC_PORT(sc);\n\n\tREG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);\n}\n\nstatic void bnx2x_e1h_enable(struct bnx2x_softc *sc)\n{\n\tint port = SC_PORT(sc);\n\n\tREG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);\n}\n\n/*\n * called due to MCP event (on pmf):\n * reread new bandwidth configuration\n * configure FW\n * notify others function about the change\n */\nstatic void bnx2x_config_mf_bw(struct bnx2x_softc *sc)\n{\n\tif (sc->link_vars.link_up) {\n\t\tbnx2x_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);\n\t\tbnx2x_link_sync_notify(sc);\n\t}\n\n\tstorm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));\n}\n\nstatic void bnx2x_set_mf_bw(struct bnx2x_softc *sc)\n{\n\tbnx2x_config_mf_bw(sc);\n\tbnx2x_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);\n}\n\nstatic void bnx2x_handle_eee_event(struct bnx2x_softc *sc)\n{\n\tbnx2x_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);\n}\n\n#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3\n\nstatic void bnx2x_drv_info_ether_stat(struct bnx2x_softc *sc)\n{\n\tstruct eth_stats_info *ether_stat = &sc->sp->drv_info_to_mcp.ether_stat;\n\n\tstrncpy(ether_stat->version, BNX2X_DRIVER_VERSION,\n\t\tETH_STAT_INFO_VERSION_LEN);\n\n\tsc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,\n\t\t\t\t\t DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,\n\t\t\t\t\t ether_stat->mac_local + MAC_PAD,\n\t\t\t\t\t MAC_PAD, ETH_ALEN);\n\n\tether_stat->mtu_size = sc->mtu;\n\n\tether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;\n\tether_stat->promiscuous_mode = 0;\t// (flags & PROMISC) ? 1 : 0;\n\n\tether_stat->txq_size = sc->tx_ring_size;\n\tether_stat->rxq_size = sc->rx_ring_size;\n}\n\nstatic void bnx2x_handle_drv_info_req(struct bnx2x_softc *sc)\n{\n\tenum drv_info_opcode op_code;\n\tuint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);\n\n\t/* if drv_info version supported by MFW doesn't match - send NACK */\n\tif ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {\n\t\tbnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);\n\t\treturn;\n\t}\n\n\top_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>\n\t\t DRV_INFO_CONTROL_OP_CODE_SHIFT);\n\n\tmemset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));\n\n\tswitch (op_code) {\n\tcase ETH_STATS_OPCODE:\n\t\tbnx2x_drv_info_ether_stat(sc);\n\t\tbreak;\n\tcase FCOE_STATS_OPCODE:\n\tcase ISCSI_STATS_OPCODE:\n\tdefault:\n\t\t/* if op code isn't supported - send NACK */\n\t\tbnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);\n\t\treturn;\n\t}\n\n\t/*\n\t * If we got drv_info attn from MFW then these fields are defined in\n\t * shmem2 for sure\n\t */\n\tSHMEM2_WR(sc, drv_info_host_addr_lo,\n\t\t U64_LO(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));\n\tSHMEM2_WR(sc, drv_info_host_addr_hi,\n\t\t U64_HI(BNX2X_SP_MAPPING(sc, drv_info_to_mcp)));\n\n\tbnx2x_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);\n}\n\nstatic void bnx2x_dcc_event(struct bnx2x_softc *sc, uint32_t dcc_event)\n{\n\tif (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {\n/*\n * This is the only place besides the function initialization\n * where the sc->flags can change so it is done without any\n * locks\n */\n\t\tif (sc->devinfo.\n\t\t mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"mf_cfg function disabled\");\n\t\t\tsc->flags |= BNX2X_MF_FUNC_DIS;\n\t\t\tbnx2x_e1h_disable(sc);\n\t\t} else {\n\t\t\tPMD_DRV_LOG(DEBUG, \"mf_cfg function enabled\");\n\t\t\tsc->flags &= ~BNX2X_MF_FUNC_DIS;\n\t\t\tbnx2x_e1h_enable(sc);\n\t\t}\n\t\tdcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;\n\t}\n\n\tif (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {\n\t\tbnx2x_config_mf_bw(sc);\n\t\tdcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;\n\t}\n\n\t/* Report results to MCP */\n\tif (dcc_event)\n\t\tbnx2x_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);\n\telse\n\t\tbnx2x_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);\n}\n\nstatic void bnx2x_pmf_update(struct bnx2x_softc *sc)\n{\n\tint port = SC_PORT(sc);\n\tuint32_t val;\n\n\tsc->port.pmf = 1;\n\n\t/*\n\t * We need the mb() to ensure the ordering between the writing to\n\t * sc->port.pmf here and reading it from the bnx2x_periodic_task().\n\t */\n\tmb();\n\n\t/* enable nig attention */\n\tval = (0xff0f | (1 << (SC_VN(sc) + 4)));\n\tif (sc->devinfo.int_block == INT_BLOCK_HC) {\n\t\tREG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);\n\t\tREG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);\n\t} else if (!CHIP_IS_E1x(sc)) {\n\t\tREG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);\n\t\tREG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);\n\t}\n\n\tbnx2x_stats_handle(sc, STATS_EVENT_PMF);\n}\n\nstatic int bnx2x_mc_assert(struct bnx2x_softc *sc)\n{\n\tchar last_idx;\n\tint i, rc = 0;\n\t__rte_unused uint32_t row0, row1, row2, row3;\n\n\t/* XSTORM */\n\tlast_idx =\n\t REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);\n\tif (last_idx)\n\t\tPMD_DRV_LOG(ERR, \"XSTORM_ASSERT_LIST_INDEX 0x%x\", last_idx);\n\n\t/* print the asserts */\n\tfor (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {\n\n\t\trow0 =\n\t\t REG_RD(sc,\n\t\t\t BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));\n\t\trow1 =\n\t\t REG_RD(sc,\n\t\t\t BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +\n\t\t\t 4);\n\t\trow2 =\n\t\t REG_RD(sc,\n\t\t\t BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +\n\t\t\t 8);\n\t\trow3 =\n\t\t REG_RD(sc,\n\t\t\t BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) +\n\t\t\t 12);\n\n\t\tif (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {\n\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t \"XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\",\n\t\t\t\t i, row3, row2, row1, row0);\n\t\t\trc++;\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* TSTORM */\n\tlast_idx =\n\t REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);\n\tif (last_idx) {\n\t\tPMD_DRV_LOG(ERR, \"TSTORM_ASSERT_LIST_INDEX 0x%x\", last_idx);\n\t}\n\n\t/* print the asserts */\n\tfor (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {\n\n\t\trow0 =\n\t\t REG_RD(sc,\n\t\t\t BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));\n\t\trow1 =\n\t\t REG_RD(sc,\n\t\t\t BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +\n\t\t\t 4);\n\t\trow2 =\n\t\t REG_RD(sc,\n\t\t\t BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +\n\t\t\t 8);\n\t\trow3 =\n\t\t REG_RD(sc,\n\t\t\t BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) +\n\t\t\t 12);\n\n\t\tif (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {\n\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t \"TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\",\n\t\t\t\t i, row3, row2, row1, row0);\n\t\t\trc++;\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* CSTORM */\n\tlast_idx =\n\t REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);\n\tif (last_idx) {\n\t\tPMD_DRV_LOG(ERR, \"CSTORM_ASSERT_LIST_INDEX 0x%x\", last_idx);\n\t}\n\n\t/* print the asserts */\n\tfor (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {\n\n\t\trow0 =\n\t\t REG_RD(sc,\n\t\t\t BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));\n\t\trow1 =\n\t\t REG_RD(sc,\n\t\t\t BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +\n\t\t\t 4);\n\t\trow2 =\n\t\t REG_RD(sc,\n\t\t\t BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +\n\t\t\t 8);\n\t\trow3 =\n\t\t REG_RD(sc,\n\t\t\t BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) +\n\t\t\t 12);\n\n\t\tif (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {\n\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t \"CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\",\n\t\t\t\t i, row3, row2, row1, row0);\n\t\t\trc++;\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* USTORM */\n\tlast_idx =\n\t REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);\n\tif (last_idx) {\n\t\tPMD_DRV_LOG(ERR, \"USTORM_ASSERT_LIST_INDEX 0x%x\", last_idx);\n\t}\n\n\t/* print the asserts */\n\tfor (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {\n\n\t\trow0 =\n\t\t REG_RD(sc,\n\t\t\t BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));\n\t\trow1 =\n\t\t REG_RD(sc,\n\t\t\t BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +\n\t\t\t 4);\n\t\trow2 =\n\t\t REG_RD(sc,\n\t\t\t BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +\n\t\t\t 8);\n\t\trow3 =\n\t\t REG_RD(sc,\n\t\t\t BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) +\n\t\t\t 12);\n\n\t\tif (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {\n\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t \"USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\",\n\t\t\t\t i, row3, row2, row1, row0);\n\t\t\trc++;\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn rc;\n}\n\nstatic void bnx2x_attn_int_deasserted3(struct bnx2x_softc *sc, uint32_t attn)\n{\n\tint func = SC_FUNC(sc);\n\tuint32_t val;\n\n\tif (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {\n\n\t\tif (attn & BNX2X_PMF_LINK_ASSERT(sc)) {\n\n\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);\n\t\t\tbnx2x_read_mf_cfg(sc);\n\t\t\tsc->devinfo.mf_info.mf_config[SC_VN(sc)] =\n\t\t\t MFCFG_RD(sc,\n\t\t\t\t func_mf_config[SC_ABS_FUNC(sc)].config);\n\t\t\tval =\n\t\t\t SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);\n\n\t\t\tif (val & DRV_STATUS_DCC_EVENT_MASK)\n\t\t\t\tbnx2x_dcc_event(sc,\n\t\t\t\t\t (val &\n\t\t\t\t\t DRV_STATUS_DCC_EVENT_MASK));\n\n\t\t\tif (val & DRV_STATUS_SET_MF_BW)\n\t\t\t\tbnx2x_set_mf_bw(sc);\n\n\t\t\tif (val & DRV_STATUS_DRV_INFO_REQ)\n\t\t\t\tbnx2x_handle_drv_info_req(sc);\n\n\t\t\tif ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))\n\t\t\t\tbnx2x_pmf_update(sc);\n\n\t\t\tif (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)\n\t\t\t\tbnx2x_handle_eee_event(sc);\n\n\t\t\tif (sc->link_vars.periodic_flags &\n\t\t\t ELINK_PERIODIC_FLAGS_LINK_EVENT) {\n\t\t\t\t/* sync with link */\n\t\t\t\tsc->link_vars.periodic_flags &=\n\t\t\t\t ~ELINK_PERIODIC_FLAGS_LINK_EVENT;\n\t\t\t\tif (IS_MF(sc)) {\n\t\t\t\t\tbnx2x_link_sync_notify(sc);\n\t\t\t\t}\n\t\t\t\tbnx2x_link_report(sc);\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Always call it here: bnx2x_link_report() will\n\t\t\t * prevent the link indication duplication.\n\t\t\t */\n\t\t\tbnx2x_link_status_update(sc);\n\n\t\t} else if (attn & BNX2X_MC_ASSERT_BITS) {\n\n\t\t\tPMD_DRV_LOG(ERR, \"MC assert!\");\n\t\t\tbnx2x_mc_assert(sc);\n\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);\n\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);\n\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);\n\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);\n\t\t\trte_panic(\"MC assert!\");\n\n\t\t} else if (attn & BNX2X_MCP_ASSERT) {\n\n\t\t\tPMD_DRV_LOG(ERR, \"MCP assert!\");\n\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);\n\n\t\t} else {\n\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t \"Unknown HW assert! (attn 0x%08x)\", attn);\n\t\t}\n\t}\n\n\tif (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {\n\t\tPMD_DRV_LOG(ERR, \"LATCHED attention 0x%08x (masked)\", attn);\n\t\tif (attn & BNX2X_GRC_TIMEOUT) {\n\t\t\tval = REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);\n\t\t\tPMD_DRV_LOG(ERR, \"GRC time-out 0x%08x\", val);\n\t\t}\n\t\tif (attn & BNX2X_GRC_RSV) {\n\t\t\tval = REG_RD(sc, MISC_REG_GRC_RSV_ATTN);\n\t\t\tPMD_DRV_LOG(ERR, \"GRC reserved 0x%08x\", val);\n\t\t}\n\t\tREG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);\n\t}\n}\n\nstatic void bnx2x_attn_int_deasserted2(struct bnx2x_softc *sc, uint32_t attn)\n{\n\tint port = SC_PORT(sc);\n\tint reg_offset;\n\tuint32_t val0, mask0, val1, mask1;\n\tuint32_t val;\n\n\tif (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {\n\t\tval = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);\n\t\tPMD_DRV_LOG(ERR, \"CFC hw attention 0x%08x\", val);\n/* CFC error attention */\n\t\tif (val & 0x2) {\n\t\t\tPMD_DRV_LOG(ERR, \"FATAL error from CFC\");\n\t\t}\n\t}\n\n\tif (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {\n\t\tval = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);\n\t\tPMD_DRV_LOG(ERR, \"PXP hw attention-0 0x%08x\", val);\n/* RQ_USDMDP_FIFO_OVERFLOW */\n\t\tif (val & 0x18000) {\n\t\t\tPMD_DRV_LOG(ERR, \"FATAL error from PXP\");\n\t\t}\n\n\t\tif (!CHIP_IS_E1x(sc)) {\n\t\t\tval = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);\n\t\t\tPMD_DRV_LOG(ERR, \"PXP hw attention-1 0x%08x\", val);\n\t\t}\n\t}\n#define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR\n#define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT\n\n\tif (attn & AEU_PXP2_HW_INT_BIT) {\n/* CQ47854 workaround do not panic on\n * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR\n */\n\t\tif (!CHIP_IS_E1x(sc)) {\n\t\t\tmask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);\n\t\t\tval1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);\n\t\t\tmask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);\n\t\t\tval0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);\n\t\t\t/*\n\t\t\t * If the olny PXP2_EOP_ERROR_BIT is set in\n\t\t\t * STS0 and STS1 - clear it\n\t\t\t *\n\t\t\t * probably we lose additional attentions between\n\t\t\t * STS0 and STS_CLR0, in this case user will not\n\t\t\t * be notified about them\n\t\t\t */\n\t\t\tif (val0 & mask0 & PXP2_EOP_ERROR_BIT &&\n\t\t\t !(val1 & mask1))\n\t\t\t\tval0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);\n\n\t\t\t/* print the register, since no one can restore it */\n\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t \"PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x\", val0);\n\n\t\t\t/*\n\t\t\t * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR\n\t\t\t * then notify\n\t\t\t */\n\t\t\tif (val0 & PXP2_EOP_ERROR_BIT) {\n\t\t\t\tPMD_DRV_LOG(ERR, \"PXP2_WR_PGLUE_EOP_ERROR\");\n\n\t\t\t\t/*\n\t\t\t\t * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is\n\t\t\t\t * set then clear attention from PXP2 block without panic\n\t\t\t\t */\n\t\t\t\tif (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&\n\t\t\t\t ((val1 & mask1) == 0))\n\t\t\t\t\tattn &= ~AEU_PXP2_HW_INT_BIT;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (attn & HW_INTERRUT_ASSERT_SET_2) {\n\t\treg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :\n\t\t\t MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);\n\n\t\tval = REG_RD(sc, reg_offset);\n\t\tval &= ~(attn & HW_INTERRUT_ASSERT_SET_2);\n\t\tREG_WR(sc, reg_offset, val);\n\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"FATAL HW block attention set2 0x%x\",\n\t\t\t (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_2));\n\t\trte_panic(\"HW block attention set2\");\n\t}\n}\n\nstatic void bnx2x_attn_int_deasserted1(struct bnx2x_softc *sc, uint32_t attn)\n{\n\tint port = SC_PORT(sc);\n\tint reg_offset;\n\tuint32_t val;\n\n\tif (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {\n\t\tval = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);\n\t\tPMD_DRV_LOG(ERR, \"DB hw attention 0x%08x\", val);\n/* DORQ discard attention */\n\t\tif (val & 0x2) {\n\t\t\tPMD_DRV_LOG(ERR, \"FATAL error from DORQ\");\n\t\t}\n\t}\n\n\tif (attn & HW_INTERRUT_ASSERT_SET_1) {\n\t\treg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :\n\t\t\t MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);\n\n\t\tval = REG_RD(sc, reg_offset);\n\t\tval &= ~(attn & HW_INTERRUT_ASSERT_SET_1);\n\t\tREG_WR(sc, reg_offset, val);\n\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"FATAL HW block attention set1 0x%08x\",\n\t\t\t (uint32_t) (attn & HW_INTERRUT_ASSERT_SET_1));\n\t\trte_panic(\"HW block attention set1\");\n\t}\n}\n\nstatic void bnx2x_attn_int_deasserted0(struct bnx2x_softc *sc, uint32_t attn)\n{\n\tint port = SC_PORT(sc);\n\tint reg_offset;\n\tuint32_t val;\n\n\treg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :\n\t MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;\n\n\tif (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {\n\t\tval = REG_RD(sc, reg_offset);\n\t\tval &= ~AEU_INPUTS_ATTN_BITS_SPIO5;\n\t\tREG_WR(sc, reg_offset, val);\n\n\t\tPMD_DRV_LOG(WARNING, \"SPIO5 hw attention\");\n\n/* Fan failure attention */\n\t\telink_hw_reset_phy(&sc->link_params);\n\t\tbnx2x_fan_failure(sc);\n\t}\n\n\tif ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {\n\t\telink_handle_module_detect_int(&sc->link_params);\n\t}\n\n\tif (attn & HW_INTERRUT_ASSERT_SET_0) {\n\t\tval = REG_RD(sc, reg_offset);\n\t\tval &= ~(attn & HW_INTERRUT_ASSERT_SET_0);\n\t\tREG_WR(sc, reg_offset, val);\n\n\t\trte_panic(\"FATAL HW block attention set0 0x%lx\",\n\t\t\t (attn & HW_INTERRUT_ASSERT_SET_0));\n\t}\n}\n\nstatic void bnx2x_attn_int_deasserted(struct bnx2x_softc *sc, uint32_t deasserted)\n{\n\tstruct attn_route attn;\n\tstruct attn_route *group_mask;\n\tint port = SC_PORT(sc);\n\tint index;\n\tuint32_t reg_addr;\n\tuint32_t val;\n\tuint32_t aeu_mask;\n\tuint8_t global = FALSE;\n\n\t/*\n\t * Need to take HW lock because MCP or other port might also\n\t * try to handle this event.\n\t */\n\tbnx2x_acquire_alr(sc);\n\n\tif (bnx2x_chk_parity_attn(sc, &global, TRUE)) {\n\t\tsc->recovery_state = BNX2X_RECOVERY_INIT;\n\n/* disable HW interrupts */\n\t\tbnx2x_int_disable(sc);\n\t\tbnx2x_release_alr(sc);\n\t\treturn;\n\t}\n\n\tattn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);\n\tattn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);\n\tattn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);\n\tattn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tattn.sig[4] =\n\t\t REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port * 4);\n\t} else {\n\t\tattn.sig[4] = 0;\n\t}\n\n\tfor (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {\n\t\tif (deasserted & (1 << index)) {\n\t\t\tgroup_mask = &sc->attn_group[index];\n\n\t\t\tbnx2x_attn_int_deasserted4(sc,\n\t\t\t\t\t\t attn.\n\t\t\t\t\t\t sig[4] & group_mask->sig[4]);\n\t\t\tbnx2x_attn_int_deasserted3(sc,\n\t\t\t\t\t\t attn.\n\t\t\t\t\t\t sig[3] & group_mask->sig[3]);\n\t\t\tbnx2x_attn_int_deasserted1(sc,\n\t\t\t\t\t\t attn.\n\t\t\t\t\t\t sig[1] & group_mask->sig[1]);\n\t\t\tbnx2x_attn_int_deasserted2(sc,\n\t\t\t\t\t\t attn.\n\t\t\t\t\t\t sig[2] & group_mask->sig[2]);\n\t\t\tbnx2x_attn_int_deasserted0(sc,\n\t\t\t\t\t\t attn.\n\t\t\t\t\t\t sig[0] & group_mask->sig[0]);\n\t\t}\n\t}\n\n\tbnx2x_release_alr(sc);\n\n\tif (sc->devinfo.int_block == INT_BLOCK_HC) {\n\t\treg_addr = (HC_REG_COMMAND_REG + port * 32 +\n\t\t\t COMMAND_REG_ATTN_BITS_CLR);\n\t} else {\n\t\treg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER * 8);\n\t}\n\n\tval = ~deasserted;\n\tPMD_DRV_LOG(DEBUG,\n\t\t \"about to mask 0x%08x at %s addr 0x%08x\", val,\n\t\t (sc->devinfo.int_block == INT_BLOCK_HC) ? \"HC\" : \"IGU\",\n\t\t reg_addr);\n\tREG_WR(sc, reg_addr, val);\n\n\tif (~sc->attn_state & deasserted) {\n\t\tPMD_DRV_LOG(ERR, \"IGU error\");\n\t}\n\n\treg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :\n\t MISC_REG_AEU_MASK_ATTN_FUNC_0;\n\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);\n\n\taeu_mask = REG_RD(sc, reg_addr);\n\n\taeu_mask |= (deasserted & 0x3ff);\n\n\tREG_WR(sc, reg_addr, aeu_mask);\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);\n\n\tsc->attn_state &= ~deasserted;\n}\n\nstatic void bnx2x_attn_int(struct bnx2x_softc *sc)\n{\n\t/* read local copy of bits */\n\tuint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);\n\tuint32_t attn_ack =\n\t le32toh(sc->def_sb->atten_status_block.attn_bits_ack);\n\tuint32_t attn_state = sc->attn_state;\n\n\t/* look for changed bits */\n\tuint32_t asserted = attn_bits & ~attn_ack & ~attn_state;\n\tuint32_t deasserted = ~attn_bits & attn_ack & attn_state;\n\n\tPMD_DRV_LOG(DEBUG,\n\t\t \"attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x\",\n\t\t attn_bits, attn_ack, asserted, deasserted);\n\n\tif (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {\n\t\tPMD_DRV_LOG(ERR, \"BAD attention state\");\n\t}\n\n\t/* handle bits that were raised */\n\tif (asserted) {\n\t\tbnx2x_attn_int_asserted(sc, asserted);\n\t}\n\n\tif (deasserted) {\n\t\tbnx2x_attn_int_deasserted(sc, deasserted);\n\t}\n}\n\nstatic uint16_t bnx2x_update_dsb_idx(struct bnx2x_softc *sc)\n{\n\tstruct host_sp_status_block *def_sb = sc->def_sb;\n\tuint16_t rc = 0;\n\n\tmb();\t\t\t/* status block is written to by the chip */\n\n\tif (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {\n\t\tsc->def_att_idx = def_sb->atten_status_block.attn_bits_index;\n\t\trc |= BNX2X_DEF_SB_ATT_IDX;\n\t}\n\n\tif (sc->def_idx != def_sb->sp_sb.running_index) {\n\t\tsc->def_idx = def_sb->sp_sb.running_index;\n\t\trc |= BNX2X_DEF_SB_IDX;\n\t}\n\n\tmb();\n\n\treturn rc;\n}\n\nstatic struct ecore_queue_sp_obj *bnx2x_cid_to_q_obj(struct bnx2x_softc *sc,\n\t\t\t\t\t\t\t uint32_t cid)\n{\n\treturn &sc->sp_objs[CID_TO_FP(cid, sc)].q_obj;\n}\n\nstatic void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)\n{\n\tstruct ecore_mcast_ramrod_params rparam;\n\tint rc;\n\n\tmemset(&rparam, 0, sizeof(rparam));\n\n\trparam.mcast_obj = &sc->mcast_obj;\n\n\t/* clear pending state for the last command */\n\tsc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);\n\n\t/* if there are pending mcast commands - send them */\n\tif (sc->mcast_obj.check_pending(&sc->mcast_obj)) {\n\t\trc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);\n\t\tif (rc < 0) {\n\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t \"Failed to send pending mcast commands (%d)\",\n\t\t\t\t rc);\n\t\t}\n\t}\n}\n\nstatic void\nbnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)\n{\n\tunsigned long ramrod_flags = 0;\n\tint rc = 0;\n\tuint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;\n\tstruct ecore_vlan_mac_obj *vlan_mac_obj;\n\n\t/* always push next commands out, don't wait here */\n\tbnx2x_set_bit(RAMROD_CONT, &ramrod_flags);\n\n\tswitch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {\n\tcase ECORE_FILTER_MAC_PENDING:\n\t\tPMD_DRV_LOG(DEBUG, \"Got SETUP_MAC completions\");\n\t\tvlan_mac_obj = &sc->sp_objs[cid].mac_obj;\n\t\tbreak;\n\n\tcase ECORE_FILTER_MCAST_PENDING:\n\t\tPMD_DRV_LOG(DEBUG, \"Got SETUP_MCAST completions\");\n\t\tbnx2x_handle_mcast_eqe(sc);\n\t\treturn;\n\n\tdefault:\n\t\tPMD_DRV_LOG(NOTICE, \"Unsupported classification command: %d\",\n\t\t\t elem->message.data.eth_event.echo);\n\t\treturn;\n\t}\n\n\trc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);\n\n\tif (rc < 0) {\n\t\tPMD_DRV_LOG(NOTICE, \"Failed to schedule new commands (%d)\", rc);\n\t} else if (rc > 0) {\n\t\tPMD_DRV_LOG(DEBUG, \"Scheduled next pending commands...\");\n\t}\n}\n\nstatic void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)\n{\n\tbnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);\n\n\t/* send rx_mode command again if was requested */\n\tif (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {\n\t\tbnx2x_set_storm_rx_mode(sc);\n\t}\n}\n\nstatic void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)\n{\n\tstorm_memset_eq_prod(sc, prod, SC_FUNC(sc));\n\twmb();\t\t\t/* keep prod updates ordered */\n}\n\nstatic void bnx2x_eq_int(struct bnx2x_softc *sc)\n{\n\tuint16_t hw_cons, sw_cons, sw_prod;\n\tunion event_ring_elem *elem;\n\tuint8_t echo;\n\tuint32_t cid;\n\tuint8_t opcode;\n\tint spqe_cnt = 0;\n\tstruct ecore_queue_sp_obj *q_obj;\n\tstruct ecore_func_sp_obj *f_obj = &sc->func_obj;\n\tstruct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;\n\n\thw_cons = le16toh(*sc->eq_cons_sb);\n\n\t/*\n\t * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.\n\t * when we get to the next-page we need to adjust so the loop\n\t * condition below will be met. The next element is the size of a\n\t * regular element and hence incrementing by 1\n\t */\n\tif ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {\n\t\thw_cons++;\n\t}\n\n\t/*\n\t * This function may never run in parallel with itself for a\n\t * specific sc and no need for a read memory barrier here.\n\t */\n\tsw_cons = sc->eq_cons;\n\tsw_prod = sc->eq_prod;\n\n\tfor (;\n\t sw_cons != hw_cons;\n\t sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {\n\n\t\telem = &sc->eq[EQ_DESC(sw_cons)];\n\n/* elem CID originates from FW, actually LE */\n\t\tcid = SW_CID(elem->message.data.cfc_del_event.cid);\n\t\topcode = elem->message.opcode;\n\n/* handle eq element */\n\t\tswitch (opcode) {\n\t\tcase EVENT_RING_OPCODE_STAT_QUERY:\n\t\t\tPMD_DRV_LOG(DEBUG, \"got statistics completion event %d\",\n\t\t\t\t sc->stats_comp++);\n\t\t\t/* nothing to do with stats comp */\n\t\t\tgoto next_spqe;\n\n\t\tcase EVENT_RING_OPCODE_CFC_DEL:\n\t\t\t/* handle according to cid range */\n\t\t\t/* we may want to verify here that the sc state is HALTING */\n\t\t\tPMD_DRV_LOG(DEBUG, \"got delete ramrod for MULTI[%d]\",\n\t\t\t\t cid);\n\t\t\tq_obj = bnx2x_cid_to_q_obj(sc, cid);\n\t\t\tif (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tgoto next_spqe;\n\n\t\tcase EVENT_RING_OPCODE_STOP_TRAFFIC:\n\t\t\tPMD_DRV_LOG(DEBUG, \"got STOP TRAFFIC\");\n\t\t\tif (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tgoto next_spqe;\n\n\t\tcase EVENT_RING_OPCODE_START_TRAFFIC:\n\t\t\tPMD_DRV_LOG(DEBUG, \"got START TRAFFIC\");\n\t\t\tif (f_obj->complete_cmd\n\t\t\t (sc, f_obj, ECORE_F_CMD_TX_START)) {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tgoto next_spqe;\n\n\t\tcase EVENT_RING_OPCODE_FUNCTION_UPDATE:\n\t\t\techo = elem->message.data.function_update_event.echo;\n\t\t\tif (echo == SWITCH_UPDATE) {\n\t\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t\t \"got FUNC_SWITCH_UPDATE ramrod\");\n\t\t\t\tif (f_obj->complete_cmd(sc, f_obj,\n\t\t\t\t\t\t\tECORE_F_CMD_SWITCH_UPDATE))\n\t\t\t\t{\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t\t \"AFEX: ramrod completed FUNCTION_UPDATE\");\n\t\t\t\tf_obj->complete_cmd(sc, f_obj,\n\t\t\t\t\t\t ECORE_F_CMD_AFEX_UPDATE);\n\t\t\t}\n\t\t\tgoto next_spqe;\n\n\t\tcase EVENT_RING_OPCODE_FORWARD_SETUP:\n\t\t\tq_obj = &bnx2x_fwd_sp_obj(sc, q_obj);\n\t\t\tif (q_obj->complete_cmd(sc, q_obj,\n\t\t\t\t\t\tECORE_Q_CMD_SETUP_TX_ONLY)) {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tgoto next_spqe;\n\n\t\tcase EVENT_RING_OPCODE_FUNCTION_START:\n\t\t\tPMD_DRV_LOG(DEBUG, \"got FUNC_START ramrod\");\n\t\t\tif (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tgoto next_spqe;\n\n\t\tcase EVENT_RING_OPCODE_FUNCTION_STOP:\n\t\t\tPMD_DRV_LOG(DEBUG, \"got FUNC_STOP ramrod\");\n\t\t\tif (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tgoto next_spqe;\n\t\t}\n\n\t\tswitch (opcode | sc->state) {\n\t\tcase (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPEN):\n\t\tcase (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BNX2X_STATE_OPENING_WAITING_PORT):\n\t\t\tcid =\n\t\t\t elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;\n\t\t\tPMD_DRV_LOG(DEBUG, \"got RSS_UPDATE ramrod. CID %d\",\n\t\t\t\t cid);\n\t\t\trss_raw->clear_pending(rss_raw);\n\t\t\tbreak;\n\n\t\tcase (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):\n\t\tcase (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):\n\t\tcase (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_CLOSING_WAITING_HALT):\n\t\tcase (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_OPEN):\n\t\tcase (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_DIAG):\n\t\tcase (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"got (un)set mac ramrod\");\n\t\t\tbnx2x_handle_classification_eqe(sc, elem);\n\t\t\tbreak;\n\n\t\tcase (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_OPEN):\n\t\tcase (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_DIAG):\n\t\tcase (EVENT_RING_OPCODE_MULTICAST_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"got mcast ramrod\");\n\t\t\tbnx2x_handle_mcast_eqe(sc);\n\t\t\tbreak;\n\n\t\tcase (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_OPEN):\n\t\tcase (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_DIAG):\n\t\tcase (EVENT_RING_OPCODE_FILTERS_RULES | BNX2X_STATE_CLOSING_WAITING_HALT):\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"got rx_mode ramrod\");\n\t\t\tbnx2x_handle_rx_mode_eqe(sc);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\t/* unknown event log error and continue */\n\t\t\tPMD_DRV_LOG(INFO, \"Unknown EQ event %d, sc->state 0x%x\",\n\t\t\t\t elem->message.opcode, sc->state);\n\t\t}\n\nnext_spqe:\n\t\tspqe_cnt++;\n\t}\t\t\t/* for */\n\n\tmb();\n\tatomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);\n\n\tsc->eq_cons = sw_cons;\n\tsc->eq_prod = sw_prod;\n\n\t/* make sure that above mem writes were issued towards the memory */\n\twmb();\n\n\t/* update producer */\n\tbnx2x_update_eq_prod(sc, sc->eq_prod);\n}\n\nstatic int bnx2x_handle_sp_tq(struct bnx2x_softc *sc)\n{\n\tuint16_t status;\n\tint rc = 0;\n\n\t/* what work needs to be performed? */\n\tstatus = bnx2x_update_dsb_idx(sc);\n\n\t/* HW attentions */\n\tif (status & BNX2X_DEF_SB_ATT_IDX) {\n\t\tPMD_DRV_LOG(DEBUG, \"---> ATTN INTR <---\");\n\t\tbnx2x_attn_int(sc);\n\t\tstatus &= ~BNX2X_DEF_SB_ATT_IDX;\n\t\trc = 1;\n\t}\n\n\t/* SP events: STAT_QUERY and others */\n\tif (status & BNX2X_DEF_SB_IDX) {\n/* handle EQ completions */\n\t\tPMD_DRV_LOG(DEBUG, \"---> EQ INTR <---\");\n\t\tbnx2x_eq_int(sc);\n\t\tbnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,\n\t\t\t le16toh(sc->def_idx), IGU_INT_NOP, 1);\n\t\tstatus &= ~BNX2X_DEF_SB_IDX;\n\t}\n\n\t/* if status is non zero then something went wrong */\n\tif (unlikely(status)) {\n\t\tPMD_DRV_LOG(INFO,\n\t\t\t \"Got an unknown SP interrupt! (0x%04x)\", status);\n\t}\n\n\t/* ack status block only if something was actually handled */\n\tbnx2x_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,\n\t\t le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);\n\n\treturn rc;\n}\n\nstatic void bnx2x_handle_fp_tq(struct bnx2x_fastpath *fp, int scan_fp)\n{\n\tstruct bnx2x_softc *sc = fp->sc;\n\tuint8_t more_rx = FALSE;\n\n\t/* update the fastpath index */\n\tbnx2x_update_fp_sb_idx(fp);\n\n\tif (scan_fp) {\n\t\tif (bnx2x_has_rx_work(fp)) {\n\t\t\tmore_rx = bnx2x_rxeof(sc, fp);\n\t\t}\n\n\t\tif (more_rx) {\n\t\t\t/* still more work to do */\n\t\t\tbnx2x_handle_fp_tq(fp, scan_fp);\n\t\t\treturn;\n\t\t}\n\t}\n\n\tbnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID,\n\t\t le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);\n}\n\n/*\n * Legacy interrupt entry point.\n *\n * Verifies that the controller generated the interrupt and\n * then calls a separate routine to handle the various\n * interrupt causes: link, RX, and TX.\n */\nint bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp)\n{\n\tstruct bnx2x_fastpath *fp;\n\tuint32_t status, mask;\n\tint i, rc = 0;\n\n\t/*\n\t * 0 for ustorm, 1 for cstorm\n\t * the bits returned from ack_int() are 0-15\n\t * bit 0 = attention status block\n\t * bit 1 = fast path status block\n\t * a mask of 0x2 or more = tx/rx event\n\t * a mask of 1 = slow path event\n\t */\n\n\tstatus = bnx2x_ack_int(sc);\n\n\t/* the interrupt is not for us */\n\tif (unlikely(status == 0)) {\n\t\treturn 0;\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"Interrupt status 0x%04x\", status);\n\t//bnx2x_dump_status_block(sc);\n\n\tFOR_EACH_ETH_QUEUE(sc, i) {\n\t\tfp = &sc->fp[i];\n\t\tmask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));\n\t\tif (status & mask) {\n\t\t\tbnx2x_handle_fp_tq(fp, scan_fp);\n\t\t\tstatus &= ~mask;\n\t\t}\n\t}\n\n\tif (unlikely(status & 0x1)) {\n\t\trc = bnx2x_handle_sp_tq(sc);\n\t\tstatus &= ~0x1;\n\t}\n\n\tif (unlikely(status)) {\n\t\tPMD_DRV_LOG(WARNING,\n\t\t\t \"Unexpected fastpath status (0x%08x)!\", status);\n\t}\n\n\treturn rc;\n}\n\nstatic int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc);\nstatic int bnx2x_init_hw_common(struct bnx2x_softc *sc);\nstatic int bnx2x_init_hw_port(struct bnx2x_softc *sc);\nstatic int bnx2x_init_hw_func(struct bnx2x_softc *sc);\nstatic void bnx2x_reset_common(struct bnx2x_softc *sc);\nstatic void bnx2x_reset_port(struct bnx2x_softc *sc);\nstatic void bnx2x_reset_func(struct bnx2x_softc *sc);\nstatic int bnx2x_init_firmware(struct bnx2x_softc *sc);\nstatic void bnx2x_release_firmware(struct bnx2x_softc *sc);\n\nstatic struct\necore_func_sp_drv_ops bnx2x_func_sp_drv = {\n\t.init_hw_cmn_chip = bnx2x_init_hw_common_chip,\n\t.init_hw_cmn = bnx2x_init_hw_common,\n\t.init_hw_port = bnx2x_init_hw_port,\n\t.init_hw_func = bnx2x_init_hw_func,\n\n\t.reset_hw_cmn = bnx2x_reset_common,\n\t.reset_hw_port = bnx2x_reset_port,\n\t.reset_hw_func = bnx2x_reset_func,\n\n\t.init_fw = bnx2x_init_firmware,\n\t.release_fw = bnx2x_release_firmware,\n};\n\nstatic void bnx2x_init_func_obj(struct bnx2x_softc *sc)\n{\n\tsc->dmae_ready = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tecore_init_func_obj(sc,\n\t\t\t &sc->func_obj,\n\t\t\t BNX2X_SP(sc, func_rdata),\n\t\t\t (phys_addr_t)BNX2X_SP_MAPPING(sc, func_rdata),\n\t\t\t BNX2X_SP(sc, func_afex_rdata),\n\t\t\t (phys_addr_t)BNX2X_SP_MAPPING(sc, func_afex_rdata),\n\t\t\t &bnx2x_func_sp_drv);\n}\n\nstatic int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)\n{\n\tstruct ecore_func_state_params func_params = { NULL };\n\tint rc;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* prepare the parameters for function state transitions */\n\tbnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);\n\n\tfunc_params.f_obj = &sc->func_obj;\n\tfunc_params.cmd = ECORE_F_CMD_HW_INIT;\n\n\tfunc_params.params.hw_init.load_phase = load_code;\n\n\t/*\n\t * Via a plethora of function pointers, we will eventually reach\n\t * bnx2x_init_hw_common(), bnx2x_init_hw_port(), or bnx2x_init_hw_func().\n\t */\n\trc = ecore_func_state_change(sc, &func_params);\n\n\treturn rc;\n}\n\nstatic void\nbnx2x_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, uint32_t len)\n{\n\tuint32_t i;\n\n\tif (!(len % 4) && !(addr % 4)) {\n\t\tfor (i = 0; i < len; i += 4) {\n\t\t\tREG_WR(sc, (addr + i), fill);\n\t\t}\n\t} else {\n\t\tfor (i = 0; i < len; i++) {\n\t\t\tREG_WR8(sc, (addr + i), fill);\n\t\t}\n\t}\n}\n\n/* writes FP SP data to FW - data_size in dwords */\nstatic void\nbnx2x_wr_fp_sb_data(struct bnx2x_softc *sc, int fw_sb_id, uint32_t * sb_data_p,\n\t\t uint32_t data_size)\n{\n\tuint32_t index;\n\n\tfor (index = 0; index < data_size; index++) {\n\t\tREG_WR(sc,\n\t\t (BAR_CSTRORM_INTMEM +\n\t\t\tCSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +\n\t\t\t(sizeof(uint32_t) * index)), *(sb_data_p + index));\n\t}\n}\n\nstatic void bnx2x_zero_fp_sb(struct bnx2x_softc *sc, int fw_sb_id)\n{\n\tstruct hc_status_block_data_e2 sb_data_e2;\n\tstruct hc_status_block_data_e1x sb_data_e1x;\n\tuint32_t *sb_data_p;\n\tuint32_t data_size = 0;\n\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tmemset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));\n\t\tsb_data_e2.common.state = SB_DISABLED;\n\t\tsb_data_e2.common.p_func.vf_valid = FALSE;\n\t\tsb_data_p = (uint32_t *) & sb_data_e2;\n\t\tdata_size = (sizeof(struct hc_status_block_data_e2) /\n\t\t\t sizeof(uint32_t));\n\t} else {\n\t\tmemset(&sb_data_e1x, 0,\n\t\t sizeof(struct hc_status_block_data_e1x));\n\t\tsb_data_e1x.common.state = SB_DISABLED;\n\t\tsb_data_e1x.common.p_func.vf_valid = FALSE;\n\t\tsb_data_p = (uint32_t *) & sb_data_e1x;\n\t\tdata_size = (sizeof(struct hc_status_block_data_e1x) /\n\t\t\t sizeof(uint32_t));\n\t}\n\n\tbnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);\n\n\tbnx2x_fill(sc,\n\t\t (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 0,\n\t\t CSTORM_STATUS_BLOCK_SIZE);\n\tbnx2x_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),\n\t\t 0, CSTORM_SYNC_BLOCK_SIZE);\n}\n\nstatic void\nbnx2x_wr_sp_sb_data(struct bnx2x_softc *sc,\n\t\t struct hc_sp_status_block_data *sp_sb_data)\n{\n\tuint32_t i;\n\n\tfor (i = 0;\n\t i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));\n\t i++) {\n\t\tREG_WR(sc,\n\t\t (BAR_CSTRORM_INTMEM +\n\t\t\tCSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +\n\t\t\t(i * sizeof(uint32_t))),\n\t\t *((uint32_t *) sp_sb_data + i));\n\t}\n}\n\nstatic void bnx2x_zero_sp_sb(struct bnx2x_softc *sc)\n{\n\tstruct hc_sp_status_block_data sp_sb_data;\n\n\tmemset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));\n\n\tsp_sb_data.state = SB_DISABLED;\n\tsp_sb_data.p_func.vf_valid = FALSE;\n\n\tbnx2x_wr_sp_sb_data(sc, &sp_sb_data);\n\n\tbnx2x_fill(sc,\n\t\t (BAR_CSTRORM_INTMEM +\n\t\t CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),\n\t\t 0, CSTORM_SP_STATUS_BLOCK_SIZE);\n\tbnx2x_fill(sc,\n\t\t (BAR_CSTRORM_INTMEM +\n\t\t CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),\n\t\t 0, CSTORM_SP_SYNC_BLOCK_SIZE);\n}\n\nstatic void\nbnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, int igu_sb_id,\n\t\t\t int igu_seg_id)\n{\n\thc_sm->igu_sb_id = igu_sb_id;\n\thc_sm->igu_seg_id = igu_seg_id;\n\thc_sm->timer_value = 0xFF;\n\thc_sm->time_to_expire = 0xFFFFFFFF;\n}\n\nstatic void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)\n{\n\t/* zero out state machine indices */\n\n\t/* rx indices */\n\tindex_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;\n\n\t/* tx indices */\n\tindex_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;\n\tindex_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;\n\tindex_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;\n\tindex_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;\n\n\t/* map indices */\n\n\t/* rx indices */\n\tindex_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=\n\t (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);\n\n\t/* tx indices */\n\tindex_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=\n\t (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);\n\tindex_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=\n\t (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);\n\tindex_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=\n\t (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);\n\tindex_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=\n\t (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);\n}\n\nstatic void\nbnx2x_init_sb(struct bnx2x_softc *sc, phys_addr_t busaddr, int vfid,\n\t uint8_t vf_valid, int fw_sb_id, int igu_sb_id)\n{\n\tstruct hc_status_block_data_e2 sb_data_e2;\n\tstruct hc_status_block_data_e1x sb_data_e1x;\n\tstruct hc_status_block_sm *hc_sm_p;\n\tuint32_t *sb_data_p;\n\tint igu_seg_id;\n\tint data_size;\n\n\tif (CHIP_INT_MODE_IS_BC(sc)) {\n\t\tigu_seg_id = HC_SEG_ACCESS_NORM;\n\t} else {\n\t\tigu_seg_id = IGU_SEG_ACCESS_NORM;\n\t}\n\n\tbnx2x_zero_fp_sb(sc, fw_sb_id);\n\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tmemset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));\n\t\tsb_data_e2.common.state = SB_ENABLED;\n\t\tsb_data_e2.common.p_func.pf_id = SC_FUNC(sc);\n\t\tsb_data_e2.common.p_func.vf_id = vfid;\n\t\tsb_data_e2.common.p_func.vf_valid = vf_valid;\n\t\tsb_data_e2.common.p_func.vnic_id = SC_VN(sc);\n\t\tsb_data_e2.common.same_igu_sb_1b = TRUE;\n\t\tsb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);\n\t\tsb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);\n\t\thc_sm_p = sb_data_e2.common.state_machine;\n\t\tsb_data_p = (uint32_t *) & sb_data_e2;\n\t\tdata_size = (sizeof(struct hc_status_block_data_e2) /\n\t\t\t sizeof(uint32_t));\n\t\tbnx2x_map_sb_state_machines(sb_data_e2.index_data);\n\t} else {\n\t\tmemset(&sb_data_e1x, 0,\n\t\t sizeof(struct hc_status_block_data_e1x));\n\t\tsb_data_e1x.common.state = SB_ENABLED;\n\t\tsb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);\n\t\tsb_data_e1x.common.p_func.vf_id = 0xff;\n\t\tsb_data_e1x.common.p_func.vf_valid = FALSE;\n\t\tsb_data_e1x.common.p_func.vnic_id = SC_VN(sc);\n\t\tsb_data_e1x.common.same_igu_sb_1b = TRUE;\n\t\tsb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);\n\t\tsb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);\n\t\thc_sm_p = sb_data_e1x.common.state_machine;\n\t\tsb_data_p = (uint32_t *) & sb_data_e1x;\n\t\tdata_size = (sizeof(struct hc_status_block_data_e1x) /\n\t\t\t sizeof(uint32_t));\n\t\tbnx2x_map_sb_state_machines(sb_data_e1x.index_data);\n\t}\n\n\tbnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);\n\tbnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);\n\n\t/* write indices to HW - PCI guarantees endianity of regpairs */\n\tbnx2x_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);\n}\n\nstatic uint8_t bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)\n{\n\tif (CHIP_IS_E1x(fp->sc)) {\n\t\treturn (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);\n\t} else {\n\t\treturn (fp->cl_id);\n\t}\n}\n\nstatic uint32_t\nbnx2x_rx_ustorm_prods_offset(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp)\n{\n\tuint32_t offset = BAR_USTRORM_INTMEM;\n\n\tif (IS_VF(sc)) {\n\t\treturn (PXP_VF_ADDR_USDM_QUEUES_START +\n\t\t\t(sc->acquire_resp.resc.hw_qid[fp->index] *\n\t\t\t sizeof(struct ustorm_queue_zone_data)));\n\t} else if (!CHIP_IS_E1x(sc)) {\n\t\toffset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);\n\t} else {\n\t\toffset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);\n\t}\n\n\treturn offset;\n}\n\nstatic void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)\n{\n\tstruct bnx2x_fastpath *fp = &sc->fp[idx];\n\tuint32_t cids[ECORE_MULTI_TX_COS] = { 0 };\n\tunsigned long q_type = 0;\n\tint cos;\n\n\tfp->sc = sc;\n\tfp->index = idx;\n\n\tfp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));\n\tfp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));\n\n\tif (CHIP_IS_E1x(sc))\n\t\tfp->cl_id = SC_L_ID(sc) + idx;\n\telse\n/* want client ID same as IGU SB ID for non-E1 */\n\t\tfp->cl_id = fp->igu_sb_id;\n\tfp->cl_qzone_id = bnx2x_fp_qzone_id(fp);\n\n\t/* setup sb indices */\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tfp->sb_index_values = fp->status_block.e2_sb->sb.index_values;\n\t\tfp->sb_running_index = fp->status_block.e2_sb->sb.running_index;\n\t} else {\n\t\tfp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;\n\t\tfp->sb_running_index =\n\t\t fp->status_block.e1x_sb->sb.running_index;\n\t}\n\n\t/* init shortcut */\n\tfp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(sc, fp);\n\n\tfp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];\n\n\tfor (cos = 0; cos < sc->max_cos; cos++) {\n\t\tcids[cos] = idx;\n\t}\n\tfp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];\n\n\t/* nothing more for a VF to do */\n\tif (IS_VF(sc)) {\n\t\treturn;\n\t}\n\n\tbnx2x_init_sb(sc, fp->sb_dma.paddr, BNX2X_VF_ID_INVALID, FALSE,\n\t\t fp->fw_sb_id, fp->igu_sb_id);\n\n\tbnx2x_update_fp_sb_idx(fp);\n\n\t/* Configure Queue State object */\n\tbnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);\n\tbnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);\n\n\tecore_init_queue_obj(sc,\n\t\t\t &sc->sp_objs[idx].q_obj,\n\t\t\t fp->cl_id,\n\t\t\t cids,\n\t\t\t sc->max_cos,\n\t\t\t SC_FUNC(sc),\n\t\t\t BNX2X_SP(sc, q_rdata),\n\t\t\t (phys_addr_t)BNX2X_SP_MAPPING(sc, q_rdata),\n\t\t\t q_type);\n\n\t/* configure classification DBs */\n\tecore_init_mac_obj(sc,\n\t\t\t &sc->sp_objs[idx].mac_obj,\n\t\t\t fp->cl_id,\n\t\t\t idx,\n\t\t\t SC_FUNC(sc),\n\t\t\t BNX2X_SP(sc, mac_rdata),\n\t\t\t (phys_addr_t)BNX2X_SP_MAPPING(sc, mac_rdata),\n\t\t\t ECORE_FILTER_MAC_PENDING, &sc->sp_state,\n\t\t\t ECORE_OBJ_TYPE_RX_TX, &sc->macs_pool);\n}\n\nstatic void\nbnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n\t\t uint16_t rx_bd_prod, uint16_t rx_cq_prod)\n{\n\tunion ustorm_eth_rx_producers rx_prods;\n\tuint32_t i;\n\n\t/* update producers */\n\trx_prods.prod.bd_prod = rx_bd_prod;\n\trx_prods.prod.cqe_prod = rx_cq_prod;\n\trx_prods.prod.reserved = 0;\n\n\t/*\n\t * Make sure that the BD and SGE data is updated before updating the\n\t * producers since FW might read the BD/SGE right after the producer\n\t * is updated.\n\t * This is only applicable for weak-ordered memory model archs such\n\t * as IA-64. The following barrier is also mandatory since FW will\n\t * assumes BDs must have buffers.\n\t */\n\twmb();\n\n\tfor (i = 0; i < (sizeof(rx_prods) / 4); i++) {\n\t\tREG_WR(sc,\n\t\t (fp->ustorm_rx_prods_offset + (i * 4)),\n\t\t rx_prods.raw_data[i]);\n\t}\n\n\twmb();\t\t\t/* keep prod updates ordered */\n}\n\nstatic void bnx2x_init_rx_rings(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_fastpath *fp;\n\tint i;\n\tstruct bnx2x_rx_queue *rxq;\n\n\tfor (i = 0; i < sc->num_queues; i++) {\n\t\tfp = &sc->fp[i];\n\t\trxq = sc->rx_queues[fp->index];\n\t\tif (!rxq) {\n\t\t\tPMD_RX_LOG(ERR, \"RX queue is NULL\");\n\t\t\treturn;\n\t\t}\n\n/*\n * Activate the BD ring...\n * Warning, this will generate an interrupt (to the TSTORM)\n * so this can only be done after the chip is initialized\n */\n\t\tbnx2x_update_rx_prod(sc, fp, rxq->rx_bd_tail, rxq->rx_cq_tail);\n\n\t\tif (i != 0) {\n\t\t\tcontinue;\n\t\t}\n\t}\n}\n\nstatic void bnx2x_init_tx_ring_one(struct bnx2x_fastpath *fp)\n{\n\tstruct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];\n\n\tfp->tx_db.data.header.header = 1 << DOORBELL_HDR_DB_TYPE_SHIFT;\n\tfp->tx_db.data.zero_fill1 = 0;\n\tfp->tx_db.data.prod = 0;\n\n\tif (!txq) {\n\t\tPMD_TX_LOG(ERR, \"ERROR: TX queue is NULL\");\n\t\treturn;\n\t}\n\n\ttxq->tx_pkt_tail = 0;\n\ttxq->tx_pkt_head = 0;\n\ttxq->tx_bd_tail = 0;\n\ttxq->tx_bd_head = 0;\n}\n\nstatic void bnx2x_init_tx_rings(struct bnx2x_softc *sc)\n{\n\tint i;\n\n\tfor (i = 0; i < sc->num_queues; i++) {\n\t\tbnx2x_init_tx_ring_one(&sc->fp[i]);\n\t}\n}\n\nstatic void bnx2x_init_def_sb(struct bnx2x_softc *sc)\n{\n\tstruct host_sp_status_block *def_sb = sc->def_sb;\n\tphys_addr_t mapping = sc->def_sb_dma.paddr;\n\tint igu_sp_sb_index;\n\tint igu_seg_id;\n\tint port = SC_PORT(sc);\n\tint func = SC_FUNC(sc);\n\tint reg_offset, reg_offset_en5;\n\tuint64_t section;\n\tint index, sindex;\n\tstruct hc_sp_status_block_data sp_sb_data;\n\n\tmemset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));\n\n\tif (CHIP_INT_MODE_IS_BC(sc)) {\n\t\tigu_sp_sb_index = DEF_SB_IGU_ID;\n\t\tigu_seg_id = HC_SEG_ACCESS_DEF;\n\t} else {\n\t\tigu_sp_sb_index = sc->igu_dsb_id;\n\t\tigu_seg_id = IGU_SEG_ACCESS_DEF;\n\t}\n\n\t/* attentions */\n\tsection = ((uint64_t) mapping +\n\t\t offsetof(struct host_sp_status_block, atten_status_block));\n\tdef_sb->atten_status_block.status_block_id = igu_sp_sb_index;\n\tsc->attn_state = 0;\n\n\treg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :\n\t MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;\n\n\treg_offset_en5 = (port) ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :\n\t MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;\n\n\tfor (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {\n/* take care of sig[0]..sig[4] */\n\t\tfor (sindex = 0; sindex < 4; sindex++) {\n\t\t\tsc->attn_group[index].sig[sindex] =\n\t\t\t REG_RD(sc,\n\t\t\t\t (reg_offset + (sindex * 0x4) +\n\t\t\t\t (0x10 * index)));\n\t\t}\n\n\t\tif (!CHIP_IS_E1x(sc)) {\n\t\t\t/*\n\t\t\t * enable5 is separate from the rest of the registers,\n\t\t\t * and the address skip is 4 and not 16 between the\n\t\t\t * different groups\n\t\t\t */\n\t\t\tsc->attn_group[index].sig[4] =\n\t\t\t REG_RD(sc, (reg_offset_en5 + (0x4 * index)));\n\t\t} else {\n\t\t\tsc->attn_group[index].sig[4] = 0;\n\t\t}\n\t}\n\n\tif (sc->devinfo.int_block == INT_BLOCK_HC) {\n\t\treg_offset =\n\t\t port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;\n\t\tREG_WR(sc, reg_offset, U64_LO(section));\n\t\tREG_WR(sc, (reg_offset + 4), U64_HI(section));\n\t} else if (!CHIP_IS_E1x(sc)) {\n\t\tREG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));\n\t\tREG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));\n\t}\n\n\tsection = ((uint64_t) mapping +\n\t\t offsetof(struct host_sp_status_block, sp_sb));\n\n\tbnx2x_zero_sp_sb(sc);\n\n\t/* PCI guarantees endianity of regpair */\n\tsp_sb_data.state = SB_ENABLED;\n\tsp_sb_data.host_sb_addr.lo = U64_LO(section);\n\tsp_sb_data.host_sb_addr.hi = U64_HI(section);\n\tsp_sb_data.igu_sb_id = igu_sp_sb_index;\n\tsp_sb_data.igu_seg_id = igu_seg_id;\n\tsp_sb_data.p_func.pf_id = func;\n\tsp_sb_data.p_func.vnic_id = SC_VN(sc);\n\tsp_sb_data.p_func.vf_id = 0xff;\n\n\tbnx2x_wr_sp_sb_data(sc, &sp_sb_data);\n\n\tbnx2x_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);\n}\n\nstatic void bnx2x_init_sp_ring(struct bnx2x_softc *sc)\n{\n\tatomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);\n\tsc->spq_prod_idx = 0;\n\tsc->dsb_sp_prod =\n\t &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];\n\tsc->spq_prod_bd = sc->spq;\n\tsc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);\n}\n\nstatic void bnx2x_init_eq_ring(struct bnx2x_softc *sc)\n{\n\tunion event_ring_elem *elem;\n\tint i;\n\n\tfor (i = 1; i <= NUM_EQ_PAGES; i++) {\n\t\telem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];\n\n\t\telem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +\n\t\t\t\t\t\t\t BNX2X_PAGE_SIZE *\n\t\t\t\t\t\t\t (i % NUM_EQ_PAGES)));\n\t\telem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +\n\t\t\t\t\t\t\t BNX2X_PAGE_SIZE *\n\t\t\t\t\t\t\t (i % NUM_EQ_PAGES)));\n\t}\n\n\tsc->eq_cons = 0;\n\tsc->eq_prod = NUM_EQ_DESC;\n\tsc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];\n\n\tatomic_store_rel_long(&sc->eq_spq_left,\n\t\t\t (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),\n\t\t\t\t NUM_EQ_DESC) - 1));\n}\n\nstatic void bnx2x_init_internal_common(struct bnx2x_softc *sc)\n{\n\tint i;\n\n\tif (IS_MF_SI(sc)) {\n/*\n * In switch independent mode, the TSTORM needs to accept\n * packets that failed classification, since approximate match\n * mac addresses aren't written to NIG LLH.\n */\n\t\tREG_WR8(sc,\n\t\t\t(BAR_TSTRORM_INTMEM +\n\t\t\t TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 2);\n\t} else\n\t\tREG_WR8(sc,\n\t\t\t(BAR_TSTRORM_INTMEM +\n\t\t\t TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 0);\n\n\t/*\n\t * Zero this manually as its initialization is currently missing\n\t * in the initTool.\n\t */\n\tfor (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {\n\t\tREG_WR(sc,\n\t\t (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),\n\t\t 0);\n\t}\n\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tREG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),\n\t\t\tCHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE :\n\t\t\tHC_IGU_NBC_MODE);\n\t}\n}\n\nstatic void bnx2x_init_internal(struct bnx2x_softc *sc, uint32_t load_code)\n{\n\tswitch (load_code) {\n\tcase FW_MSG_CODE_DRV_LOAD_COMMON:\n\tcase FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:\n\t\tbnx2x_init_internal_common(sc);\n\t\t/* no break */\n\n\tcase FW_MSG_CODE_DRV_LOAD_PORT:\n\t\t/* nothing to do */\n\t\t/* no break */\n\n\tcase FW_MSG_CODE_DRV_LOAD_FUNCTION:\n\t\t/* internal memory per function is initialized inside bnx2x_pf_init */\n\t\tbreak;\n\n\tdefault:\n\t\tPMD_DRV_LOG(NOTICE, \"Unknown load_code (0x%x) from MCP\",\n\t\t\t load_code);\n\t\tbreak;\n\t}\n}\n\nstatic void\nstorm_memset_func_cfg(struct bnx2x_softc *sc,\n\t\t struct tstorm_eth_function_common_config *tcfg,\n\t\t uint16_t abs_fid)\n{\n\tuint32_t addr;\n\tsize_t size;\n\n\taddr = (BAR_TSTRORM_INTMEM +\n\t\tTSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));\n\tsize = sizeof(struct tstorm_eth_function_common_config);\n\tecore_storm_memset_struct(sc, addr, size, (uint32_t *) tcfg);\n}\n\nstatic void bnx2x_func_init(struct bnx2x_softc *sc, struct bnx2x_func_init_params *p)\n{\n\tstruct tstorm_eth_function_common_config tcfg = { 0 };\n\n\tif (CHIP_IS_E1x(sc)) {\n\t\tstorm_memset_func_cfg(sc, &tcfg, p->func_id);\n\t}\n\n\t/* Enable the function in the FW */\n\tstorm_memset_vf_to_pf(sc, p->func_id, p->pf_id);\n\tstorm_memset_func_en(sc, p->func_id, 1);\n\n\t/* spq */\n\tif (p->func_flgs & FUNC_FLG_SPQ) {\n\t\tstorm_memset_spq_addr(sc, p->spq_map, p->func_id);\n\t\tREG_WR(sc,\n\t\t (XSEM_REG_FAST_MEMORY +\n\t\t\tXSTORM_SPQ_PROD_OFFSET(p->func_id)), p->spq_prod);\n\t}\n}\n\n/*\n * Calculates the sum of vn_min_rates.\n * It's needed for further normalizing of the min_rates.\n * Returns:\n * sum of vn_min_rates.\n * or\n * 0 - if all the min_rates are 0.\n * In the later case fainess algorithm should be deactivated.\n * If all min rates are not zero then those that are zeroes will be set to 1.\n */\nstatic void bnx2x_calc_vn_min(struct bnx2x_softc *sc, struct cmng_init_input *input)\n{\n\tuint32_t vn_cfg;\n\tuint32_t vn_min_rate;\n\tint all_zero = 1;\n\tint vn;\n\n\tfor (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {\n\t\tvn_cfg = sc->devinfo.mf_info.mf_config[vn];\n\t\tvn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>\n\t\t\t\tFUNC_MF_CFG_MIN_BW_SHIFT) * 100);\n\n\t\tif (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {\n\t\t\t/* skip hidden VNs */\n\t\t\tvn_min_rate = 0;\n\t\t} else if (!vn_min_rate) {\n\t\t\t/* If min rate is zero - set it to 100 */\n\t\t\tvn_min_rate = DEF_MIN_RATE;\n\t\t} else {\n\t\t\tall_zero = 0;\n\t\t}\n\n\t\tinput->vnic_min_rate[vn] = vn_min_rate;\n\t}\n\n\t/* if ETS or all min rates are zeros - disable fairness */\n\tif (all_zero) {\n\t\tinput->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;\n\t} else {\n\t\tinput->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;\n\t}\n}\n\nstatic uint16_t\nbnx2x_extract_max_cfg(__rte_unused struct bnx2x_softc *sc, uint32_t mf_cfg)\n{\n\tuint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>\n\t\t\t FUNC_MF_CFG_MAX_BW_SHIFT);\n\n\tif (!max_cfg) {\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t \"Max BW configured to 0 - using 100 instead\");\n\t\tmax_cfg = 100;\n\t}\n\n\treturn max_cfg;\n}\n\nstatic void\nbnx2x_calc_vn_max(struct bnx2x_softc *sc, int vn, struct cmng_init_input *input)\n{\n\tuint16_t vn_max_rate;\n\tuint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];\n\tuint32_t max_cfg;\n\n\tif (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {\n\t\tvn_max_rate = 0;\n\t} else {\n\t\tmax_cfg = bnx2x_extract_max_cfg(sc, vn_cfg);\n\n\t\tif (IS_MF_SI(sc)) {\n\t\t\t/* max_cfg in percents of linkspeed */\n\t\t\tvn_max_rate =\n\t\t\t ((sc->link_vars.line_speed * max_cfg) / 100);\n\t\t} else {\t/* SD modes */\n\t\t\t/* max_cfg is absolute in 100Mb units */\n\t\t\tvn_max_rate = (max_cfg * 100);\n\t\t}\n\t}\n\n\tinput->vnic_max_rate[vn] = vn_max_rate;\n}\n\nstatic void\nbnx2x_cmng_fns_init(struct bnx2x_softc *sc, uint8_t read_cfg, uint8_t cmng_type)\n{\n\tstruct cmng_init_input input;\n\tint vn;\n\n\tmemset(&input, 0, sizeof(struct cmng_init_input));\n\n\tinput.port_rate = sc->link_vars.line_speed;\n\n\tif (cmng_type == CMNG_FNS_MINMAX) {\n/* read mf conf from shmem */\n\t\tif (read_cfg) {\n\t\t\tbnx2x_read_mf_cfg(sc);\n\t\t}\n\n/* get VN min rate and enable fairness if not 0 */\n\t\tbnx2x_calc_vn_min(sc, &input);\n\n/* get VN max rate */\n\t\tif (sc->port.pmf) {\n\t\t\tfor (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {\n\t\t\t\tbnx2x_calc_vn_max(sc, vn, &input);\n\t\t\t}\n\t\t}\n\n/* always enable rate shaping and fairness */\n\t\tinput.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;\n\n\t\tecore_init_cmng(&input, &sc->cmng);\n\t\treturn;\n\t}\n}\n\nstatic int bnx2x_get_cmng_fns_mode(struct bnx2x_softc *sc)\n{\n\tif (CHIP_REV_IS_SLOW(sc)) {\n\t\treturn CMNG_FNS_NONE;\n\t}\n\n\tif (IS_MF(sc)) {\n\t\treturn CMNG_FNS_MINMAX;\n\t}\n\n\treturn CMNG_FNS_NONE;\n}\n\nstatic void\nstorm_memset_cmng(struct bnx2x_softc *sc, struct cmng_init *cmng, uint8_t port)\n{\n\tint vn;\n\tint func;\n\tuint32_t addr;\n\tsize_t size;\n\n\taddr = (BAR_XSTRORM_INTMEM + XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));\n\tsize = sizeof(struct cmng_struct_per_port);\n\tecore_storm_memset_struct(sc, addr, size, (uint32_t *) & cmng->port);\n\n\tfor (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {\n\t\tfunc = func_by_vn(sc, vn);\n\n\t\taddr = (BAR_XSTRORM_INTMEM +\n\t\t\tXSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));\n\t\tsize = sizeof(struct rate_shaping_vars_per_vn);\n\t\tecore_storm_memset_struct(sc, addr, size,\n\t\t\t\t\t (uint32_t *) & cmng->\n\t\t\t\t\t vnic.vnic_max_rate[vn]);\n\n\t\taddr = (BAR_XSTRORM_INTMEM +\n\t\t\tXSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));\n\t\tsize = sizeof(struct fairness_vars_per_vn);\n\t\tecore_storm_memset_struct(sc, addr, size,\n\t\t\t\t\t (uint32_t *) & cmng->\n\t\t\t\t\t vnic.vnic_min_rate[vn]);\n\t}\n}\n\nstatic void bnx2x_pf_init(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_func_init_params func_init;\n\tstruct event_ring_data eq_data;\n\tuint16_t flags;\n\n\tmemset(&eq_data, 0, sizeof(struct event_ring_data));\n\tmemset(&func_init, 0, sizeof(struct bnx2x_func_init_params));\n\n\tif (!CHIP_IS_E1x(sc)) {\n/* reset IGU PF statistics: MSIX + ATTN */\n/* PF */\n\t\tREG_WR(sc,\n\t\t (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +\n\t\t\t(BNX2X_IGU_STAS_MSG_VF_CNT * 4) +\n\t\t\t((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *\n\t\t\t 4)), 0);\n/* ATTN */\n\t\tREG_WR(sc,\n\t\t (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +\n\t\t\t(BNX2X_IGU_STAS_MSG_VF_CNT * 4) +\n\t\t\t(BNX2X_IGU_STAS_MSG_PF_CNT * 4) +\n\t\t\t((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) *\n\t\t\t 4)), 0);\n\t}\n\n\t/* function setup flags */\n\tflags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);\n\n\tfunc_init.func_flgs = flags;\n\tfunc_init.pf_id = SC_FUNC(sc);\n\tfunc_init.func_id = SC_FUNC(sc);\n\tfunc_init.spq_map = sc->spq_dma.paddr;\n\tfunc_init.spq_prod = sc->spq_prod_idx;\n\n\tbnx2x_func_init(sc, &func_init);\n\n\tmemset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));\n\n\t/*\n\t * Congestion management values depend on the link rate.\n\t * There is no active link so initial link rate is set to 10Gbps.\n\t * When the link comes up the congestion management values are\n\t * re-calculated according to the actual link rate.\n\t */\n\tsc->link_vars.line_speed = SPEED_10000;\n\tbnx2x_cmng_fns_init(sc, TRUE, bnx2x_get_cmng_fns_mode(sc));\n\n\t/* Only the PMF sets the HW */\n\tif (sc->port.pmf) {\n\t\tstorm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));\n\t}\n\n\t/* init Event Queue - PCI bus guarantees correct endainity */\n\teq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);\n\teq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);\n\teq_data.producer = sc->eq_prod;\n\teq_data.index_id = HC_SP_INDEX_EQ_CONS;\n\teq_data.sb_id = DEF_SB_ID;\n\tstorm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));\n}\n\nstatic void bnx2x_hc_int_enable(struct bnx2x_softc *sc)\n{\n\tint port = SC_PORT(sc);\n\tuint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;\n\tuint32_t val = REG_RD(sc, addr);\n\tuint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)\n\t || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);\n\tuint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);\n\tuint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);\n\n\tif (msix) {\n\t\tval &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |\n\t\t\t HC_CONFIG_0_REG_INT_LINE_EN_0);\n\t\tval |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |\n\t\t\tHC_CONFIG_0_REG_ATTN_BIT_EN_0);\n\t\tif (single_msix) {\n\t\t\tval |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;\n\t\t}\n\t} else if (msi) {\n\t\tval &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;\n\t\tval |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |\n\t\t\tHC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |\n\t\t\tHC_CONFIG_0_REG_ATTN_BIT_EN_0);\n\t} else {\n\t\tval |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |\n\t\t\tHC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |\n\t\t\tHC_CONFIG_0_REG_INT_LINE_EN_0 |\n\t\t\tHC_CONFIG_0_REG_ATTN_BIT_EN_0);\n\n\t\tREG_WR(sc, addr, val);\n\n\t\tval &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;\n\t}\n\n\tREG_WR(sc, addr, val);\n\n\t/* ensure that HC_CONFIG is written before leading/trailing edge config */\n\tmb();\n\n\t/* init leading/trailing edge */\n\tif (IS_MF(sc)) {\n\t\tval = (0xee0f | (1 << (SC_VN(sc) + 4)));\n\t\tif (sc->port.pmf) {\n\t\t\t/* enable nig and gpio3 attention */\n\t\t\tval |= 0x1100;\n\t\t}\n\t} else {\n\t\tval = 0xffff;\n\t}\n\n\tREG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port * 8), val);\n\tREG_WR(sc, (HC_REG_LEADING_EDGE_0 + port * 8), val);\n\n\t/* make sure that interrupts are indeed enabled from here on */\n\tmb();\n}\n\nstatic void bnx2x_igu_int_enable(struct bnx2x_softc *sc)\n{\n\tuint32_t val;\n\tuint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX)\n\t || (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);\n\tuint8_t single_msix = (sc->interrupt_mode == INTR_MODE_SINGLE_MSIX);\n\tuint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI);\n\n\tval = REG_RD(sc, IGU_REG_PF_CONFIGURATION);\n\n\tif (msix) {\n\t\tval &= ~(IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_SINGLE_ISR_EN);\n\t\tval |= (IGU_PF_CONF_MSI_MSIX_EN | IGU_PF_CONF_ATTN_BIT_EN);\n\t\tif (single_msix) {\n\t\t\tval |= IGU_PF_CONF_SINGLE_ISR_EN;\n\t\t}\n\t} else if (msi) {\n\t\tval &= ~IGU_PF_CONF_INT_LINE_EN;\n\t\tval |= (IGU_PF_CONF_MSI_MSIX_EN |\n\t\t\tIGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);\n\t} else {\n\t\tval &= ~IGU_PF_CONF_MSI_MSIX_EN;\n\t\tval |= (IGU_PF_CONF_INT_LINE_EN |\n\t\t\tIGU_PF_CONF_ATTN_BIT_EN | IGU_PF_CONF_SINGLE_ISR_EN);\n\t}\n\n\t/* clean previous status - need to configure igu prior to ack */\n\tif ((!msix) || single_msix) {\n\t\tREG_WR(sc, IGU_REG_PF_CONFIGURATION, val);\n\t\tbnx2x_ack_int(sc);\n\t}\n\n\tval |= IGU_PF_CONF_FUNC_EN;\n\n\tPMD_DRV_LOG(DEBUG, \"write 0x%x to IGU mode %s\",\n\t\t val, ((msix) ? \"MSI-X\" : ((msi) ? \"MSI\" : \"INTx\")));\n\n\tREG_WR(sc, IGU_REG_PF_CONFIGURATION, val);\n\n\tmb();\n\n\t/* init leading/trailing edge */\n\tif (IS_MF(sc)) {\n\t\tval = (0xee0f | (1 << (SC_VN(sc) + 4)));\n\t\tif (sc->port.pmf) {\n\t\t\t/* enable nig and gpio3 attention */\n\t\t\tval |= 0x1100;\n\t\t}\n\t} else {\n\t\tval = 0xffff;\n\t}\n\n\tREG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);\n\tREG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);\n\n\t/* make sure that interrupts are indeed enabled from here on */\n\tmb();\n}\n\nstatic void bnx2x_int_enable(struct bnx2x_softc *sc)\n{\n\tif (sc->devinfo.int_block == INT_BLOCK_HC) {\n\t\tbnx2x_hc_int_enable(sc);\n\t} else {\n\t\tbnx2x_igu_int_enable(sc);\n\t}\n}\n\nstatic void bnx2x_hc_int_disable(struct bnx2x_softc *sc)\n{\n\tint port = SC_PORT(sc);\n\tuint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;\n\tuint32_t val = REG_RD(sc, addr);\n\n\tval &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |\n\t\t HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |\n\t\t HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);\n\t/* flush all outstanding writes */\n\tmb();\n\n\tREG_WR(sc, addr, val);\n\tif (REG_RD(sc, addr) != val) {\n\t\tPMD_DRV_LOG(ERR, \"proper val not read from HC IGU!\");\n\t}\n}\n\nstatic void bnx2x_igu_int_disable(struct bnx2x_softc *sc)\n{\n\tuint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);\n\n\tval &= ~(IGU_PF_CONF_MSI_MSIX_EN |\n\t\t IGU_PF_CONF_INT_LINE_EN | IGU_PF_CONF_ATTN_BIT_EN);\n\n\tPMD_DRV_LOG(DEBUG, \"write %x to IGU\", val);\n\n\t/* flush all outstanding writes */\n\tmb();\n\n\tREG_WR(sc, IGU_REG_PF_CONFIGURATION, val);\n\tif (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {\n\t\tPMD_DRV_LOG(ERR, \"proper val not read from IGU!\");\n\t}\n}\n\nstatic void bnx2x_int_disable(struct bnx2x_softc *sc)\n{\n\tif (sc->devinfo.int_block == INT_BLOCK_HC) {\n\t\tbnx2x_hc_int_disable(sc);\n\t} else {\n\t\tbnx2x_igu_int_disable(sc);\n\t}\n}\n\nstatic void bnx2x_nic_init(struct bnx2x_softc *sc, int load_code)\n{\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tfor (i = 0; i < sc->num_queues; i++) {\n\t\tbnx2x_init_eth_fp(sc, i);\n\t}\n\n\trmb();\t\t\t/* ensure status block indices were read */\n\n\tbnx2x_init_rx_rings(sc);\n\tbnx2x_init_tx_rings(sc);\n\n\tif (IS_VF(sc)) {\n\t\tbnx2x_memset_stats(sc);\n\t\treturn;\n\t}\n\n\t/* initialize MOD_ABS interrupts */\n\telink_init_mod_abs_int(sc, &sc->link_vars,\n\t\t\t sc->devinfo.chip_id,\n\t\t\t sc->devinfo.shmem_base,\n\t\t\t sc->devinfo.shmem2_base, SC_PORT(sc));\n\n\tbnx2x_init_def_sb(sc);\n\tbnx2x_update_dsb_idx(sc);\n\tbnx2x_init_sp_ring(sc);\n\tbnx2x_init_eq_ring(sc);\n\tbnx2x_init_internal(sc, load_code);\n\tbnx2x_pf_init(sc);\n\tbnx2x_stats_init(sc);\n\n\t/* flush all before enabling interrupts */\n\tmb();\n\n\tbnx2x_int_enable(sc);\n\n\t/* check for SPIO5 */\n\tbnx2x_attn_int_deasserted0(sc,\n\t\t\t\t REG_RD(sc,\n\t\t\t\t\t(MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +\n\t\t\t\t\t SC_PORT(sc) * 4)) &\n\t\t\t\t AEU_INPUTS_ATTN_BITS_SPIO5);\n}\n\nstatic void bnx2x_init_objs(struct bnx2x_softc *sc)\n{\n\t/* mcast rules must be added to tx if tx switching is enabled */\n\tecore_obj_type o_type;\n\tif (sc->flags & BNX2X_TX_SWITCHING)\n\t\to_type = ECORE_OBJ_TYPE_RX_TX;\n\telse\n\t\to_type = ECORE_OBJ_TYPE_RX;\n\n\t/* RX_MODE controlling object */\n\tecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);\n\n\t/* multicast configuration controlling object */\n\tecore_init_mcast_obj(sc,\n\t\t\t &sc->mcast_obj,\n\t\t\t sc->fp[0].cl_id,\n\t\t\t sc->fp[0].index,\n\t\t\t SC_FUNC(sc),\n\t\t\t SC_FUNC(sc),\n\t\t\t BNX2X_SP(sc, mcast_rdata),\n\t\t\t (phys_addr_t)BNX2X_SP_MAPPING(sc, mcast_rdata),\n\t\t\t ECORE_FILTER_MCAST_PENDING,\n\t\t\t &sc->sp_state, o_type);\n\n\t/* Setup CAM credit pools */\n\tecore_init_mac_credit_pool(sc,\n\t\t\t\t &sc->macs_pool,\n\t\t\t\t SC_FUNC(sc),\n\t\t\t\t CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :\n\t\t\t\t VNICS_PER_PATH(sc));\n\n\tecore_init_vlan_credit_pool(sc,\n\t\t\t\t &sc->vlans_pool,\n\t\t\t\t SC_ABS_FUNC(sc) >> 1,\n\t\t\t\t CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :\n\t\t\t\t VNICS_PER_PATH(sc));\n\n\t/* RSS configuration object */\n\tecore_init_rss_config_obj(&sc->rss_conf_obj,\n\t\t\t\t sc->fp[0].cl_id,\n\t\t\t\t sc->fp[0].index,\n\t\t\t\t SC_FUNC(sc),\n\t\t\t\t SC_FUNC(sc),\n\t\t\t\t BNX2X_SP(sc, rss_rdata),\n\t\t\t\t (phys_addr_t)BNX2X_SP_MAPPING(sc, rss_rdata),\n\t\t\t\t ECORE_FILTER_RSS_CONF_PENDING,\n\t\t\t\t &sc->sp_state, ECORE_OBJ_TYPE_RX);\n}\n\n/*\n * Initialize the function. This must be called before sending CLIENT_SETUP\n * for the first client.\n */\nstatic int bnx2x_func_start(struct bnx2x_softc *sc)\n{\n\tstruct ecore_func_state_params func_params = { NULL };\n\tstruct ecore_func_start_params *start_params =\n\t &func_params.params.start;\n\n\t/* Prepare parameters for function state transitions */\n\tbnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);\n\n\tfunc_params.f_obj = &sc->func_obj;\n\tfunc_params.cmd = ECORE_F_CMD_START;\n\n\t/* Function parameters */\n\tstart_params->mf_mode = sc->devinfo.mf_info.mf_mode;\n\tstart_params->sd_vlan_tag = OVLAN(sc);\n\n\tif (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {\n\t\tstart_params->network_cos_mode = STATIC_COS;\n\t} else {\t\t/* CHIP_IS_E1X */\n\t\tstart_params->network_cos_mode = FW_WRR;\n\t}\n\n\tstart_params->gre_tunnel_mode = 0;\n\tstart_params->gre_tunnel_rss = 0;\n\n\treturn ecore_func_state_change(sc, &func_params);\n}\n\nstatic int bnx2x_set_power_state(struct bnx2x_softc *sc, uint8_t state)\n{\n\tuint16_t pmcsr;\n\n\t/* If there is no power capability, silently succeed */\n\tif (!(sc->devinfo.pcie_cap_flags & BNX2X_PM_CAPABLE_FLAG)) {\n\t\tPMD_DRV_LOG(WARNING, \"No power capability\");\n\t\treturn 0;\n\t}\n\n\tpci_read(sc, (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), &pmcsr,\n\t\t 2);\n\n\tswitch (state) {\n\tcase PCI_PM_D0:\n\t\tpci_write_word(sc,\n\t\t\t (sc->devinfo.pcie_pm_cap_reg +\n\t\t\t\tPCIR_POWER_STATUS),\n\t\t\t ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME));\n\n\t\tif (pmcsr & PCIM_PSTAT_DMASK) {\n\t\t\t/* delay required during transition out of D3hot */\n\t\t\tDELAY(20000);\n\t\t}\n\n\t\tbreak;\n\n\tcase PCI_PM_D3hot:\n\t\t/* don't shut down the power for emulation and FPGA */\n\t\tif (CHIP_REV_IS_SLOW(sc)) {\n\t\t\treturn 0;\n\t\t}\n\n\t\tpmcsr &= ~PCIM_PSTAT_DMASK;\n\t\tpmcsr |= PCIM_PSTAT_D3;\n\n\t\tif (sc->wol) {\n\t\t\tpmcsr |= PCIM_PSTAT_PMEENABLE;\n\t\t}\n\n\t\tpci_write_long(sc,\n\t\t\t (sc->devinfo.pcie_pm_cap_reg +\n\t\t\t\tPCIR_POWER_STATUS), pmcsr);\n\n\t\t/*\n\t\t * No more memory access after this point until device is brought back\n\t\t * to D0 state.\n\t\t */\n\t\tbreak;\n\n\tdefault:\n\t\tPMD_DRV_LOG(NOTICE, \"Can't support PCI power state = %d\",\n\t\t\t state);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* return true if succeeded to acquire the lock */\nstatic uint8_t bnx2x_trylock_hw_lock(struct bnx2x_softc *sc, uint32_t resource)\n{\n\tuint32_t lock_status;\n\tuint32_t resource_bit = (1 << resource);\n\tint func = SC_FUNC(sc);\n\tuint32_t hw_lock_control_reg;\n\n\t/* Validating that the resource is within range */\n\tif (resource > HW_LOCK_MAX_RESOURCE_VALUE) {\n\t\tPMD_DRV_LOG(INFO,\n\t\t\t \"resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\",\n\t\t\t resource, HW_LOCK_MAX_RESOURCE_VALUE);\n\t\treturn FALSE;\n\t}\n\n\tif (func <= 5) {\n\t\thw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func * 8);\n\t} else {\n\t\thw_lock_control_reg =\n\t\t (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8);\n\t}\n\n\t/* try to acquire the lock */\n\tREG_WR(sc, hw_lock_control_reg + 4, resource_bit);\n\tlock_status = REG_RD(sc, hw_lock_control_reg);\n\tif (lock_status & resource_bit) {\n\t\treturn TRUE;\n\t}\n\n\tPMD_DRV_LOG(NOTICE, \"Failed to get a resource lock 0x%x\", resource);\n\n\treturn FALSE;\n}\n\n/*\n * Get the recovery leader resource id according to the engine this function\n * belongs to. Currently only only 2 engines is supported.\n */\nstatic int bnx2x_get_leader_lock_resource(struct bnx2x_softc *sc)\n{\n\tif (SC_PATH(sc)) {\n\t\treturn HW_LOCK_RESOURCE_RECOVERY_LEADER_1;\n\t} else {\n\t\treturn HW_LOCK_RESOURCE_RECOVERY_LEADER_0;\n\t}\n}\n\n/* try to acquire a leader lock for current engine */\nstatic uint8_t bnx2x_trylock_leader_lock(struct bnx2x_softc *sc)\n{\n\treturn bnx2x_trylock_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));\n}\n\nstatic int bnx2x_release_leader_lock(struct bnx2x_softc *sc)\n{\n\treturn bnx2x_release_hw_lock(sc, bnx2x_get_leader_lock_resource(sc));\n}\n\n/* close gates #2, #3 and #4 */\nstatic void bnx2x_set_234_gates(struct bnx2x_softc *sc, uint8_t close)\n{\n\tuint32_t val;\n\n\t/* gates #2 and #4a are closed/opened */\n\t/* #4 */\n\tREG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, ! !close);\n\t/* #2 */\n\tREG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, ! !close);\n\n\t/* #3 */\n\tif (CHIP_IS_E1x(sc)) {\n/* prevent interrupts from HC on both ports */\n\t\tval = REG_RD(sc, HC_REG_CONFIG_1);\n\t\tif (close)\n\t\t\tREG_WR(sc, HC_REG_CONFIG_1, (val & ~(uint32_t)\n\t\t\t\t\t\t HC_CONFIG_1_REG_BLOCK_DISABLE_1));\n\t\telse\n\t\t\tREG_WR(sc, HC_REG_CONFIG_1,\n\t\t\t (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1));\n\n\t\tval = REG_RD(sc, HC_REG_CONFIG_0);\n\t\tif (close)\n\t\t\tREG_WR(sc, HC_REG_CONFIG_0, (val & ~(uint32_t)\n\t\t\t\t\t\t HC_CONFIG_0_REG_BLOCK_DISABLE_0));\n\t\telse\n\t\t\tREG_WR(sc, HC_REG_CONFIG_0,\n\t\t\t (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0));\n\n\t} else {\n/* Prevent incomming interrupts in IGU */\n\t\tval = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);\n\n\t\tif (close)\n\t\t\tREG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,\n\t\t\t (val & ~(uint32_t)\n\t\t\t\tIGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));\n\t\telse\n\t\t\tREG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,\n\t\t\t (val |\n\t\t\t\tIGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));\n\t}\n\n\twmb();\n}\n\n/* poll for pending writes bit, it should get cleared in no more than 1s */\nstatic int bnx2x_er_poll_igu_vq(struct bnx2x_softc *sc)\n{\n\tuint32_t cnt = 1000;\n\tuint32_t pend_bits = 0;\n\n\tdo {\n\t\tpend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);\n\n\t\tif (pend_bits == 0) {\n\t\t\tbreak;\n\t\t}\n\n\t\tDELAY(1000);\n\t} while (cnt-- > 0);\n\n\tif (cnt <= 0) {\n\t\tPMD_DRV_LOG(NOTICE, \"Still pending IGU requests bits=0x%08x!\",\n\t\t\t pend_bits);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n#define SHARED_MF_CLP_MAGIC 0x80000000\t/* 'magic' bit */\n\nstatic void bnx2x_clp_reset_prep(struct bnx2x_softc *sc, uint32_t * magic_val)\n{\n\t/* Do some magic... */\n\tuint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);\n\t*magic_val = val & SHARED_MF_CLP_MAGIC;\n\tMFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);\n}\n\n/* restore the value of the 'magic' bit */\nstatic void bnx2x_clp_reset_done(struct bnx2x_softc *sc, uint32_t magic_val)\n{\n\t/* Restore the 'magic' bit value... */\n\tuint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);\n\tMFCFG_WR(sc, shared_mf_config.clp_mb,\n\t\t (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);\n}\n\n/* prepare for MCP reset, takes care of CLP configurations */\nstatic void bnx2x_reset_mcp_prep(struct bnx2x_softc *sc, uint32_t * magic_val)\n{\n\tuint32_t shmem;\n\tuint32_t validity_offset;\n\n\t/* set `magic' bit in order to save MF config */\n\tbnx2x_clp_reset_prep(sc, magic_val);\n\n\t/* get shmem offset */\n\tshmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);\n\tvalidity_offset =\n\t offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);\n\n\t/* Clear validity map flags */\n\tif (shmem > 0) {\n\t\tREG_WR(sc, shmem + validity_offset, 0);\n\t}\n}\n\n#define MCP_TIMEOUT 5000\t/* 5 seconds (in ms) */\n#define MCP_ONE_TIMEOUT 100\t/* 100 ms */\n\nstatic void bnx2x_mcp_wait_one(struct bnx2x_softc *sc)\n{\n\t/* special handling for emulation and FPGA (10 times longer) */\n\tif (CHIP_REV_IS_SLOW(sc)) {\n\t\tDELAY((MCP_ONE_TIMEOUT * 10) * 1000);\n\t} else {\n\t\tDELAY((MCP_ONE_TIMEOUT) * 1000);\n\t}\n}\n\n/* initialize shmem_base and waits for validity signature to appear */\nstatic int bnx2x_init_shmem(struct bnx2x_softc *sc)\n{\n\tint cnt = 0;\n\tuint32_t val = 0;\n\n\tdo {\n\t\tsc->devinfo.shmem_base =\n\t\t sc->link_params.shmem_base =\n\t\t REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);\n\n\t\tif (sc->devinfo.shmem_base) {\n\t\t\tval = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);\n\t\t\tif (val & SHR_MEM_VALIDITY_MB)\n\t\t\t\treturn 0;\n\t\t}\n\n\t\tbnx2x_mcp_wait_one(sc);\n\n\t} while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));\n\n\tPMD_DRV_LOG(NOTICE, \"BAD MCP validity signature\");\n\n\treturn -1;\n}\n\nstatic int bnx2x_reset_mcp_comp(struct bnx2x_softc *sc, uint32_t magic_val)\n{\n\tint rc = bnx2x_init_shmem(sc);\n\n\t/* Restore the `magic' bit value */\n\tbnx2x_clp_reset_done(sc, magic_val);\n\n\treturn rc;\n}\n\nstatic void bnx2x_pxp_prep(struct bnx2x_softc *sc)\n{\n\tREG_WR(sc, PXP2_REG_RD_START_INIT, 0);\n\tREG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);\n\twmb();\n}\n\n/*\n * Reset the whole chip except for:\n * - PCIE core\n * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)\n * - IGU\n * - MISC (including AEU)\n * - GRC\n * - RBCN, RBCP\n */\nstatic void bnx2x_process_kill_chip_reset(struct bnx2x_softc *sc, uint8_t global)\n{\n\tuint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;\n\tuint32_t global_bits2, stay_reset2;\n\n\t/*\n\t * Bits that have to be set in reset_mask2 if we want to reset 'global'\n\t * (per chip) blocks.\n\t */\n\tglobal_bits2 =\n\t MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |\n\t MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;\n\n\t/*\n\t * Don't reset the following blocks.\n\t * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be\n\t * reset, as in 4 port device they might still be owned\n\t * by the MCP (there is only one leader per path).\n\t */\n\tnot_reset_mask1 =\n\t MISC_REGISTERS_RESET_REG_1_RST_HC |\n\t MISC_REGISTERS_RESET_REG_1_RST_PXPV |\n\t MISC_REGISTERS_RESET_REG_1_RST_PXP;\n\n\tnot_reset_mask2 =\n\t MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |\n\t MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |\n\t MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |\n\t MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |\n\t MISC_REGISTERS_RESET_REG_2_RST_RBCN |\n\t MISC_REGISTERS_RESET_REG_2_RST_GRC |\n\t MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |\n\t MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |\n\t MISC_REGISTERS_RESET_REG_2_RST_ATC |\n\t MISC_REGISTERS_RESET_REG_2_PGLC |\n\t MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |\n\t MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |\n\t MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |\n\t MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |\n\t MISC_REGISTERS_RESET_REG_2_UMAC0 | MISC_REGISTERS_RESET_REG_2_UMAC1;\n\n\t/*\n\t * Keep the following blocks in reset:\n\t * - all xxMACs are handled by the elink code.\n\t */\n\tstay_reset2 =\n\t MISC_REGISTERS_RESET_REG_2_XMAC |\n\t MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;\n\n\t/* Full reset masks according to the chip */\n\treset_mask1 = 0xffffffff;\n\n\tif (CHIP_IS_E1H(sc))\n\t\treset_mask2 = 0x1ffff;\n\telse if (CHIP_IS_E2(sc))\n\t\treset_mask2 = 0xfffff;\n\telse\t\t\t/* CHIP_IS_E3 */\n\t\treset_mask2 = 0x3ffffff;\n\n\t/* Don't reset global blocks unless we need to */\n\tif (!global)\n\t\treset_mask2 &= ~global_bits2;\n\n\t/*\n\t * In case of attention in the QM, we need to reset PXP\n\t * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM\n\t * because otherwise QM reset would release 'close the gates' shortly\n\t * before resetting the PXP, then the PSWRQ would send a write\n\t * request to PGLUE. Then when PXP is reset, PGLUE would try to\n\t * read the payload data from PSWWR, but PSWWR would not\n\t * respond. The write queue in PGLUE would stuck, dmae commands\n\t * would not return. Therefore it's important to reset the second\n\t * reset register (containing the\n\t * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the\n\t * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM\n\t * bit).\n\t */\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,\n\t reset_mask2 & (~not_reset_mask2));\n\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,\n\t reset_mask1 & (~not_reset_mask1));\n\n\tmb();\n\twmb();\n\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,\n\t reset_mask2 & (~stay_reset2));\n\n\tmb();\n\twmb();\n\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);\n\twmb();\n}\n\nstatic int bnx2x_process_kill(struct bnx2x_softc *sc, uint8_t global)\n{\n\tint cnt = 1000;\n\tuint32_t val = 0;\n\tuint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;\n\tuint32_t tags_63_32 = 0;\n\n\t/* Empty the Tetris buffer, wait for 1s */\n\tdo {\n\t\tsr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);\n\t\tblk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);\n\t\tport_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);\n\t\tport_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);\n\t\tpgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);\n\t\tif (CHIP_IS_E3(sc)) {\n\t\t\ttags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);\n\t\t}\n\n\t\tif ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&\n\t\t ((port_is_idle_0 & 0x1) == 0x1) &&\n\t\t ((port_is_idle_1 & 0x1) == 0x1) &&\n\t\t (pgl_exp_rom2 == 0xffffffff) &&\n\t\t (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))\n\t\t\tbreak;\n\t\tDELAY(1000);\n\t} while (cnt-- > 0);\n\n\tif (cnt <= 0) {\n\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t \"ERROR: Tetris buffer didn't get empty or there \"\n\t\t\t \"are still outstanding read requests after 1s! \"\n\t\t\t \"sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, \"\n\t\t\t \"port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\",\n\t\t\t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,\n\t\t\t pgl_exp_rom2);\n\t\treturn -1;\n\t}\n\n\tmb();\n\n\t/* Close gates #2, #3 and #4 */\n\tbnx2x_set_234_gates(sc, TRUE);\n\n\t/* Poll for IGU VQs for 57712 and newer chips */\n\tif (!CHIP_IS_E1x(sc) && bnx2x_er_poll_igu_vq(sc)) {\n\t\treturn -1;\n\t}\n\n\t/* clear \"unprepared\" bit */\n\tREG_WR(sc, MISC_REG_UNPREPARED, 0);\n\tmb();\n\n\t/* Make sure all is written to the chip before the reset */\n\twmb();\n\n\t/*\n\t * Wait for 1ms to empty GLUE and PCI-E core queues,\n\t * PSWHST, GRC and PSWRD Tetris buffer.\n\t */\n\tDELAY(1000);\n\n\t/* Prepare to chip reset: */\n\t/* MCP */\n\tif (global) {\n\t\tbnx2x_reset_mcp_prep(sc, &val);\n\t}\n\n\t/* PXP */\n\tbnx2x_pxp_prep(sc);\n\tmb();\n\n\t/* reset the chip */\n\tbnx2x_process_kill_chip_reset(sc, global);\n\tmb();\n\n\t/* Recover after reset: */\n\t/* MCP */\n\tif (global && bnx2x_reset_mcp_comp(sc, val)) {\n\t\treturn -1;\n\t}\n\n\t/* Open the gates #2, #3 and #4 */\n\tbnx2x_set_234_gates(sc, FALSE);\n\n\treturn 0;\n}\n\nstatic int bnx2x_leader_reset(struct bnx2x_softc *sc)\n{\n\tint rc = 0;\n\tuint8_t global = bnx2x_reset_is_global(sc);\n\tuint32_t load_code;\n\n\t/*\n\t * If not going to reset MCP, load \"fake\" driver to reset HW while\n\t * driver is owner of the HW.\n\t */\n\tif (!global && !BNX2X_NOMCP(sc)) {\n\t\tload_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,\n\t\t\t\t\t DRV_MSG_CODE_LOAD_REQ_WITH_LFA);\n\t\tif (!load_code) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"MCP response failure, aborting\");\n\t\t\trc = -1;\n\t\t\tgoto exit_leader_reset;\n\t\t}\n\n\t\tif ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&\n\t\t (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {\n\t\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t\t \"MCP unexpected response, aborting\");\n\t\t\trc = -1;\n\t\t\tgoto exit_leader_reset2;\n\t\t}\n\n\t\tload_code = bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);\n\t\tif (!load_code) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"MCP response failure, aborting\");\n\t\t\trc = -1;\n\t\t\tgoto exit_leader_reset2;\n\t\t}\n\t}\n\n\t/* try to recover after the failure */\n\tif (bnx2x_process_kill(sc, global)) {\n\t\tPMD_DRV_LOG(NOTICE, \"Something bad occurred on engine %d!\",\n\t\t\t SC_PATH(sc));\n\t\trc = -1;\n\t\tgoto exit_leader_reset2;\n\t}\n\n\t/*\n\t * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver\n\t * state.\n\t */\n\tbnx2x_set_reset_done(sc);\n\tif (global) {\n\t\tbnx2x_clear_reset_global(sc);\n\t}\n\nexit_leader_reset2:\n\n\t/* unload \"fake driver\" if it was loaded */\n\tif (!global &&!BNX2X_NOMCP(sc)) {\n\t\tbnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);\n\t\tbnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);\n\t}\n\nexit_leader_reset:\n\n\tsc->is_leader = 0;\n\tbnx2x_release_leader_lock(sc);\n\n\tmb();\n\treturn rc;\n}\n\n/*\n * prepare INIT transition, parameters configured:\n * - HC configuration\n * - Queue's CDU context\n */\nstatic void\nbnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n\t\t struct ecore_queue_init_params *init_params)\n{\n\tuint8_t cos;\n\tint cxt_index, cxt_offset;\n\n\tbnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);\n\tbnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);\n\n\tbnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);\n\tbnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);\n\n\t/* HC rate */\n\tinit_params->rx.hc_rate =\n\t sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;\n\tinit_params->tx.hc_rate =\n\t sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;\n\n\t/* FW SB ID */\n\tinit_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;\n\n\t/* CQ index among the SB indices */\n\tinit_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;\n\tinit_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;\n\n\t/* set maximum number of COSs supported by this queue */\n\tinit_params->max_cos = sc->max_cos;\n\n\t/* set the context pointers queue object */\n\tfor (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {\n\t\tcxt_index = fp->index / ILT_PAGE_CIDS;\n\t\tcxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);\n\t\tinit_params->cxts[cos] =\n\t\t &sc->context[cxt_index].vcxt[cxt_offset].eth;\n\t}\n}\n\n/* set flags that are common for the Tx-only and not normal connections */\nstatic unsigned long\nbnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)\n{\n\tunsigned long flags = 0;\n\n\t/* PF driver will always initialize the Queue to an ACTIVE state */\n\tbnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);\n\n\t/*\n\t * tx only connections collect statistics (on the same index as the\n\t * parent connection). The statistics are zeroed when the parent\n\t * connection is initialized.\n\t */\n\n\tbnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);\n\tif (zero_stats) {\n\t\tbnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);\n\t}\n\n\t/*\n\t * tx only connections can support tx-switching, though their\n\t * CoS-ness doesn't survive the loopback\n\t */\n\tif (sc->flags & BNX2X_TX_SWITCHING) {\n\t\tbnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);\n\t}\n\n\tbnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);\n\n\treturn flags;\n}\n\nstatic unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)\n{\n\tunsigned long flags = 0;\n\n\tif (IS_MF_SD(sc)) {\n\t\tbnx2x_set_bit(ECORE_Q_FLG_OV, &flags);\n\t}\n\n\tif (leading) {\n\t\tbnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);\n\t\tbnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);\n\t}\n\n\tbnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);\n\n\t/* merge with common flags */\n\treturn flags | bnx2x_get_common_flags(sc, TRUE);\n}\n\nstatic void\nbnx2x_pf_q_prep_general(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n\t\t struct ecore_general_setup_params *gen_init, uint8_t cos)\n{\n\tgen_init->stat_id = bnx2x_stats_id(fp);\n\tgen_init->spcl_id = fp->cl_id;\n\tgen_init->mtu = sc->mtu;\n\tgen_init->cos = cos;\n}\n\nstatic void\nbnx2x_pf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n\t\t struct rxq_pause_params *pause,\n\t\t struct ecore_rxq_setup_params *rxq_init)\n{\n\tstruct bnx2x_rx_queue *rxq;\n\n\trxq = sc->rx_queues[fp->index];\n\tif (!rxq) {\n\t\tPMD_RX_LOG(ERR, \"RX queue is NULL\");\n\t\treturn;\n\t}\n\t/* pause */\n\tpause->bd_th_lo = BD_TH_LO(sc);\n\tpause->bd_th_hi = BD_TH_HI(sc);\n\n\tpause->rcq_th_lo = RCQ_TH_LO(sc);\n\tpause->rcq_th_hi = RCQ_TH_HI(sc);\n\n\t/* validate rings have enough entries to cross high thresholds */\n\tif (sc->dropless_fc &&\n\t pause->bd_th_hi + FW_PREFETCH_CNT > sc->rx_ring_size) {\n\t\tPMD_DRV_LOG(WARNING, \"rx bd ring threshold limit\");\n\t}\n\n\tif (sc->dropless_fc &&\n\t pause->rcq_th_hi + FW_PREFETCH_CNT > USABLE_RCQ_ENTRIES(rxq)) {\n\t\tPMD_DRV_LOG(WARNING, \"rcq ring threshold limit\");\n\t}\n\n\tpause->pri_map = 1;\n\n\t/* rxq setup */\n\trxq_init->dscr_map = (phys_addr_t)rxq->rx_ring_phys_addr;\n\trxq_init->rcq_map = (phys_addr_t)rxq->cq_ring_phys_addr;\n\trxq_init->rcq_np_map = (phys_addr_t)(rxq->cq_ring_phys_addr +\n\t\t\t\t\t BNX2X_PAGE_SIZE);\n\n\t/*\n\t * This should be a maximum number of data bytes that may be\n\t * placed on the BD (not including paddings).\n\t */\n\trxq_init->buf_sz = (fp->rx_buf_size - IP_HEADER_ALIGNMENT_PADDING);\n\n\trxq_init->cl_qzone_id = fp->cl_qzone_id;\n\trxq_init->rss_engine_id = SC_FUNC(sc);\n\trxq_init->mcast_engine_id = SC_FUNC(sc);\n\n\trxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;\n\trxq_init->fw_sb_id = fp->fw_sb_id;\n\n\trxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;\n\n\t/*\n\t * configure silent vlan removal\n\t * if multi function mode is afex, then mask default vlan\n\t */\n\tif (IS_MF_AFEX(sc)) {\n\t\trxq_init->silent_removal_value =\n\t\t sc->devinfo.mf_info.afex_def_vlan_tag;\n\t\trxq_init->silent_removal_mask = EVL_VLID_MASK;\n\t}\n}\n\nstatic void\nbnx2x_pf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n\t\t struct ecore_txq_setup_params *txq_init, uint8_t cos)\n{\n\tstruct bnx2x_tx_queue *txq = fp->sc->tx_queues[fp->index];\n\n\tif (!txq) {\n\t\tPMD_TX_LOG(ERR, \"ERROR: TX queue is NULL\");\n\t\treturn;\n\t}\n\ttxq_init->dscr_map = (phys_addr_t)txq->tx_ring_phys_addr;\n\ttxq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;\n\ttxq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;\n\ttxq_init->fw_sb_id = fp->fw_sb_id;\n\n\t/*\n\t * set the TSS leading client id for TX classfication to the\n\t * leading RSS client id\n\t */\n\ttxq_init->tss_leading_cl_id = BNX2X_FP(sc, 0, cl_id);\n}\n\n/*\n * This function performs 2 steps in a queue state machine:\n * 1) RESET->INIT\n * 2) INIT->SETUP\n */\nstatic int\nbnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t leading)\n{\n\tstruct ecore_queue_state_params q_params = { NULL };\n\tstruct ecore_queue_setup_params *setup_params = &q_params.params.setup;\n\tint rc;\n\n\tPMD_DRV_LOG(DEBUG, \"setting up queue %d\", fp->index);\n\n\tbnx2x_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);\n\n\tq_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;\n\n\t/* we want to wait for completion in this context */\n\tbnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);\n\n\t/* prepare the INIT parameters */\n\tbnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);\n\n\t/* Set the command */\n\tq_params.cmd = ECORE_Q_CMD_INIT;\n\n\t/* Change the state to INIT */\n\trc = ecore_queue_state_change(sc, &q_params);\n\tif (rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"Queue(%d) INIT failed\", fp->index);\n\t\treturn rc;\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"init complete\");\n\n\t/* now move the Queue to the SETUP state */\n\tmemset(setup_params, 0, sizeof(*setup_params));\n\n\t/* set Queue flags */\n\tsetup_params->flags = bnx2x_get_q_flags(sc, leading);\n\n\t/* set general SETUP parameters */\n\tbnx2x_pf_q_prep_general(sc, fp, &setup_params->gen_params,\n\t\t\t FIRST_TX_COS_INDEX);\n\n\tbnx2x_pf_rx_q_prep(sc, fp,\n\t\t\t &setup_params->pause_params,\n\t\t\t &setup_params->rxq_params);\n\n\tbnx2x_pf_tx_q_prep(sc, fp, &setup_params->txq_params, FIRST_TX_COS_INDEX);\n\n\t/* Set the command */\n\tq_params.cmd = ECORE_Q_CMD_SETUP;\n\n\t/* change the state to SETUP */\n\trc = ecore_queue_state_change(sc, &q_params);\n\tif (rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"Queue(%d) SETUP failed\", fp->index);\n\t\treturn rc;\n\t}\n\n\treturn rc;\n}\n\nstatic int bnx2x_setup_leading(struct bnx2x_softc *sc)\n{\n\tif (IS_PF(sc))\n\t\treturn bnx2x_setup_queue(sc, &sc->fp[0], TRUE);\n\telse\t\t\t/* VF */\n\t\treturn bnx2x_vf_setup_queue(sc, &sc->fp[0], TRUE);\n}\n\nstatic int\nbnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj,\n\t\t uint8_t config_hash)\n{\n\tstruct ecore_config_rss_params params = { NULL };\n\tuint32_t i;\n\n\t/*\n\t * Although RSS is meaningless when there is a single HW queue we\n\t * still need it enabled in order to have HW Rx hash generated.\n\t */\n\n\tparams.rss_obj = rss_obj;\n\n\tbnx2x_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);\n\n\tbnx2x_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);\n\n\t/* RSS configuration */\n\tbnx2x_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);\n\tbnx2x_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);\n\tbnx2x_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);\n\tbnx2x_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);\n\tif (rss_obj->udp_rss_v4) {\n\t\tbnx2x_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);\n\t}\n\tif (rss_obj->udp_rss_v6) {\n\t\tbnx2x_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);\n\t}\n\n\t/* Hash bits */\n\tparams.rss_result_mask = MULTI_MASK;\n\n\t(void)rte_memcpy(params.ind_table, rss_obj->ind_table,\n\t\t\t sizeof(params.ind_table));\n\n\tif (config_hash) {\n/* RSS keys */\n\t\tfor (i = 0; i < sizeof(params.rss_key) / 4; i++) {\n\t\t\tparams.rss_key[i] = (uint32_t) rte_rand();\n\t\t}\n\n\t\tbnx2x_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);\n\t}\n\n\tif (IS_PF(sc))\n\t\treturn ecore_config_rss(sc, ¶ms);\n\telse\n\t\treturn bnx2x_vf_config_rss(sc, ¶ms);\n}\n\nstatic int bnx2x_config_rss_eth(struct bnx2x_softc *sc, uint8_t config_hash)\n{\n\treturn bnx2x_config_rss_pf(sc, &sc->rss_conf_obj, config_hash);\n}\n\nstatic int bnx2x_init_rss_pf(struct bnx2x_softc *sc)\n{\n\tuint8_t num_eth_queues = BNX2X_NUM_ETH_QUEUES(sc);\n\tuint32_t i;\n\n\t/*\n\t * Prepare the initial contents of the indirection table if\n\t * RSS is enabled\n\t */\n\tfor (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {\n\t\tsc->rss_conf_obj.ind_table[i] =\n\t\t (sc->fp->cl_id + (i % num_eth_queues));\n\t}\n\n\tif (sc->udp_rss) {\n\t\tsc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;\n\t}\n\n\t/*\n\t * For 57711 SEARCHER configuration (rss_keys) is\n\t * per-port, so if explicit configuration is needed, do it only\n\t * for a PMF.\n\t *\n\t * For 57712 and newer it's a per-function configuration.\n\t */\n\treturn bnx2x_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc));\n}\n\nstatic int\nbnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,\n\t\tstruct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,\n\t\tunsigned long *ramrod_flags)\n{\n\tstruct ecore_vlan_mac_ramrod_params ramrod_param;\n\tint rc;\n\n\tmemset(&ramrod_param, 0, sizeof(ramrod_param));\n\n\t/* fill in general parameters */\n\tramrod_param.vlan_mac_obj = obj;\n\tramrod_param.ramrod_flags = *ramrod_flags;\n\n\t/* fill a user request section if needed */\n\tif (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {\n\t\t(void)rte_memcpy(ramrod_param.user_req.u.mac.mac, mac,\n\t\t\t\t ETH_ALEN);\n\n\t\tbnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);\n\n/* Set the command: ADD or DEL */\n\t\tramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :\n\t\t ECORE_VLAN_MAC_DEL;\n\t}\n\n\trc = ecore_config_vlan_mac(sc, &ramrod_param);\n\n\tif (rc == ECORE_EXISTS) {\n\t\tPMD_DRV_LOG(INFO, \"Failed to schedule ADD operations (EEXIST)\");\n/* do not treat adding same MAC as error */\n\t\trc = 0;\n\t} else if (rc < 0) {\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"%s MAC failed (%d)\", (set ? \"Set\" : \"Delete\"), rc);\n\t}\n\n\treturn rc;\n}\n\nstatic int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)\n{\n\tunsigned long ramrod_flags = 0;\n\n\tPMD_DRV_LOG(DEBUG, \"Adding Ethernet MAC\");\n\n\tbnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);\n\n\t/* Eth MAC is set on RSS leading client (fp[0]) */\n\treturn bnx2x_set_mac_one(sc, sc->link_params.mac_addr,\n\t\t\t &sc->sp_objs->mac_obj,\n\t\t\t set, ECORE_ETH_MAC, &ramrod_flags);\n}\n\nstatic int bnx2x_get_cur_phy_idx(struct bnx2x_softc *sc)\n{\n\tuint32_t sel_phy_idx = 0;\n\n\tif (sc->link_params.num_phys <= 1) {\n\t\treturn ELINK_INT_PHY;\n\t}\n\n\tif (sc->link_vars.link_up) {\n\t\tsel_phy_idx = ELINK_EXT_PHY1;\n/* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */\n\t\tif ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&\n\t\t (sc->link_params.phy[ELINK_EXT_PHY2].supported &\n\t\t ELINK_SUPPORTED_FIBRE))\n\t\t\tsel_phy_idx = ELINK_EXT_PHY2;\n\t} else {\n\t\tswitch (elink_phy_selection(&sc->link_params)) {\n\t\tcase PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:\n\t\tcase PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:\n\t\tcase PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:\n\t\t\tsel_phy_idx = ELINK_EXT_PHY1;\n\t\t\tbreak;\n\t\tcase PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:\n\t\tcase PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:\n\t\t\tsel_phy_idx = ELINK_EXT_PHY2;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn sel_phy_idx;\n}\n\nstatic int bnx2x_get_link_cfg_idx(struct bnx2x_softc *sc)\n{\n\tuint32_t sel_phy_idx = bnx2x_get_cur_phy_idx(sc);\n\n\t/*\n\t * The selected activated PHY is always after swapping (in case PHY\n\t * swapping is enabled). So when swapping is enabled, we need to reverse\n\t * the configuration\n\t */\n\n\tif (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {\n\t\tif (sel_phy_idx == ELINK_EXT_PHY1)\n\t\t\tsel_phy_idx = ELINK_EXT_PHY2;\n\t\telse if (sel_phy_idx == ELINK_EXT_PHY2)\n\t\t\tsel_phy_idx = ELINK_EXT_PHY1;\n\t}\n\n\treturn ELINK_LINK_CONFIG_IDX(sel_phy_idx);\n}\n\nstatic void bnx2x_set_requested_fc(struct bnx2x_softc *sc)\n{\n\t/*\n\t * Initialize link parameters structure variables\n\t * It is recommended to turn off RX FC for jumbo frames\n\t * for better performance\n\t */\n\tif (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {\n\t\tsc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;\n\t} else {\n\t\tsc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;\n\t}\n}\n\nstatic void bnx2x_calc_fc_adv(struct bnx2x_softc *sc)\n{\n\tuint8_t cfg_idx = bnx2x_get_link_cfg_idx(sc);\n\tswitch (sc->link_vars.ieee_fc &\n\t\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {\n\tcase MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:\n\tdefault:\n\t\tsc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |\n\t\t\t\t\t\t ADVERTISED_Pause);\n\t\tbreak;\n\n\tcase MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:\n\t\tsc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |\n\t\t\t\t\t\t ADVERTISED_Pause);\n\t\tbreak;\n\n\tcase MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:\n\t\tsc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;\n\t\tbreak;\n\t}\n}\n\nstatic uint16_t bnx2x_get_mf_speed(struct bnx2x_softc *sc)\n{\n\tuint16_t line_speed = sc->link_vars.line_speed;\n\tif (IS_MF(sc)) {\n\t\tuint16_t maxCfg = bnx2x_extract_max_cfg(sc,\n\t\t\t\t\t\t sc->devinfo.\n\t\t\t\t\t\t mf_info.mf_config[SC_VN\n\t\t\t\t\t\t\t\t\t(sc)]);\n\n/* calculate the current MAX line speed limit for the MF devices */\n\t\tif (IS_MF_SI(sc)) {\n\t\t\tline_speed = (line_speed * maxCfg) / 100;\n\t\t} else {\t/* SD mode */\n\t\t\tuint16_t vn_max_rate = maxCfg * 100;\n\n\t\t\tif (vn_max_rate < line_speed) {\n\t\t\t\tline_speed = vn_max_rate;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn line_speed;\n}\n\nstatic void\nbnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *data)\n{\n\tuint16_t line_speed = bnx2x_get_mf_speed(sc);\n\n\tmemset(data, 0, sizeof(*data));\n\n\t/* fill the report data with the effective line speed */\n\tdata->line_speed = line_speed;\n\n\t/* Link is down */\n\tif (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {\n\t\tbnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,\n\t\t\t &data->link_report_flags);\n\t}\n\n\t/* Full DUPLEX */\n\tif (sc->link_vars.duplex == DUPLEX_FULL) {\n\t\tbnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,\n\t\t\t &data->link_report_flags);\n\t}\n\n\t/* Rx Flow Control is ON */\n\tif (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {\n\t\tbnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);\n\t}\n\n\t/* Tx Flow Control is ON */\n\tif (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {\n\t\tbnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);\n\t}\n}\n\n/* report link status to OS, should be called under phy_lock */\nstatic void bnx2x_link_report(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_link_report_data cur_data;\n\n\t/* reread mf_cfg */\n\tif (IS_PF(sc)) {\n\t\tbnx2x_read_mf_cfg(sc);\n\t}\n\n\t/* Read the current link report info */\n\tbnx2x_fill_report_data(sc, &cur_data);\n\n\t/* Don't report link down or exactly the same link status twice */\n\tif (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||\n\t (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,\n\t\t\t &sc->last_reported_link.link_report_flags) &&\n\t bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,\n\t\t\t &cur_data.link_report_flags))) {\n\t\treturn;\n\t}\n\n\tsc->link_cnt++;\n\n\t/* report new link params and remember the state for the next time */\n\t(void)rte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));\n\n\tif (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,\n\t\t\t &cur_data.link_report_flags)) {\n\t\tPMD_DRV_LOG(INFO, \"NIC Link is Down\");\n\t} else {\n\t\t__rte_unused const char *duplex;\n\t\t__rte_unused const char *flow;\n\n\t\tif (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,\n\t\t\t\t\t &cur_data.link_report_flags)) {\n\t\t\tduplex = \"full\";\n\t\t} else {\n\t\t\tduplex = \"half\";\n\t\t}\n\n/*\n * Handle the FC at the end so that only these flags would be\n * possibly set. This way we may easily check if there is no FC\n * enabled.\n */\n\t\tif (cur_data.link_report_flags) {\n\t\t\tif (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,\n\t\t\t\t\t &cur_data.link_report_flags) &&\n\t\t\t bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,\n\t\t\t\t\t &cur_data.link_report_flags)) {\n\t\t\t\tflow = \"ON - receive & transmit\";\n\t\t\t} else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,\n\t\t\t\t\t\t&cur_data.link_report_flags) &&\n\t\t\t\t !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,\n\t\t\t\t\t\t &cur_data.link_report_flags)) {\n\t\t\t\tflow = \"ON - receive\";\n\t\t\t} else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,\n\t\t\t\t\t\t &cur_data.link_report_flags) &&\n\t\t\t\t bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,\n\t\t\t\t\t\t&cur_data.link_report_flags)) {\n\t\t\t\tflow = \"ON - transmit\";\n\t\t\t} else {\n\t\t\t\tflow = \"none\";\t/* possible? */\n\t\t\t}\n\t\t} else {\n\t\t\tflow = \"none\";\n\t\t}\n\n\t\tPMD_DRV_LOG(INFO,\n\t\t\t \"NIC Link is Up, %d Mbps %s duplex, Flow control: %s\",\n\t\t\t cur_data.line_speed, duplex, flow);\n\t}\n}\n\nvoid bnx2x_link_status_update(struct bnx2x_softc *sc)\n{\n\tif (sc->state != BNX2X_STATE_OPEN) {\n\t\treturn;\n\t}\n\n\tif (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {\n\t\telink_link_status_update(&sc->link_params, &sc->link_vars);\n\t} else {\n\t\tsc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |\n\t\t\t\t\t ELINK_SUPPORTED_10baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_100baseT_Half |\n\t\t\t\t\t ELINK_SUPPORTED_100baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_2500baseX_Full |\n\t\t\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_TP |\n\t\t\t\t\t ELINK_SUPPORTED_FIBRE |\n\t\t\t\t\t ELINK_SUPPORTED_Autoneg |\n\t\t\t\t\t ELINK_SUPPORTED_Pause |\n\t\t\t\t\t ELINK_SUPPORTED_Asym_Pause);\n\t\tsc->port.advertising[0] = sc->port.supported[0];\n\n\t\tsc->link_params.sc = sc;\n\t\tsc->link_params.port = SC_PORT(sc);\n\t\tsc->link_params.req_duplex[0] = DUPLEX_FULL;\n\t\tsc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;\n\t\tsc->link_params.req_line_speed[0] = SPEED_10000;\n\t\tsc->link_params.speed_cap_mask[0] = 0x7f0000;\n\t\tsc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;\n\n\t\tif (CHIP_REV_IS_FPGA(sc)) {\n\t\t\tsc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;\n\t\t\tsc->link_vars.line_speed = ELINK_SPEED_1000;\n\t\t\tsc->link_vars.link_status = (LINK_STATUS_LINK_UP |\n\t\t\t\t\t\t LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);\n\t\t} else {\n\t\t\tsc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;\n\t\t\tsc->link_vars.line_speed = ELINK_SPEED_10000;\n\t\t\tsc->link_vars.link_status = (LINK_STATUS_LINK_UP |\n\t\t\t\t\t\t LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);\n\t\t}\n\n\t\tsc->link_vars.link_up = 1;\n\n\t\tsc->link_vars.duplex = DUPLEX_FULL;\n\t\tsc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\n\t\tif (IS_PF(sc)) {\n\t\t\tREG_WR(sc,\n\t\t\t NIG_REG_EGRESS_DRAIN0_MODE +\n\t\t\t sc->link_params.port * 4, 0);\n\t\t\tbnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);\n\t\t\tbnx2x_link_report(sc);\n\t\t}\n\t}\n\n\tif (IS_PF(sc)) {\n\t\tif (sc->link_vars.link_up) {\n\t\t\tbnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);\n\t\t} else {\n\t\t\tbnx2x_stats_handle(sc, STATS_EVENT_STOP);\n\t\t}\n\t\tbnx2x_link_report(sc);\n\t} else {\n\t\tbnx2x_link_report(sc);\n\t\tbnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);\n\t}\n}\n\nstatic void bnx2x_periodic_start(struct bnx2x_softc *sc)\n{\n\tatomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);\n}\n\nstatic void bnx2x_periodic_stop(struct bnx2x_softc *sc)\n{\n\tatomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);\n}\n\nstatic int bnx2x_initial_phy_init(struct bnx2x_softc *sc, int load_mode)\n{\n\tint rc, cfg_idx = bnx2x_get_link_cfg_idx(sc);\n\tuint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];\n\tstruct elink_params *lp = &sc->link_params;\n\n\tbnx2x_set_requested_fc(sc);\n\n\tif (CHIP_REV_IS_SLOW(sc)) {\n\t\tuint32_t bond = CHIP_BOND_ID(sc);\n\t\tuint32_t feat = 0;\n\n\t\tif (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {\n\t\t\tfeat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;\n\t\t} else if (bond & 0x4) {\n\t\t\tif (CHIP_IS_E3(sc)) {\n\t\t\t\tfeat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;\n\t\t\t} else {\n\t\t\t\tfeat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;\n\t\t\t}\n\t\t} else if (bond & 0x8) {\n\t\t\tif (CHIP_IS_E3(sc)) {\n\t\t\t\tfeat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;\n\t\t\t} else {\n\t\t\t\tfeat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;\n\t\t\t}\n\t\t}\n\n/* disable EMAC for E3 and above */\n\t\tif (bond & 0x2) {\n\t\t\tfeat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;\n\t\t}\n\n\t\tsc->link_params.feature_config_flags |= feat;\n\t}\n\n\tif (load_mode == LOAD_DIAG) {\n\t\tlp->loopback_mode = ELINK_LOOPBACK_XGXS;\n/* Prefer doing PHY loopback at 10G speed, if possible */\n\t\tif (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {\n\t\t\tif (lp->speed_cap_mask[cfg_idx] &\n\t\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {\n\t\t\t\tlp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;\n\t\t\t} else {\n\t\t\t\tlp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (load_mode == LOAD_LOOPBACK_EXT) {\n\t\tlp->loopback_mode = ELINK_LOOPBACK_EXT;\n\t}\n\n\trc = elink_phy_init(&sc->link_params, &sc->link_vars);\n\n\tbnx2x_calc_fc_adv(sc);\n\n\tif (sc->link_vars.link_up) {\n\t\tbnx2x_stats_handle(sc, STATS_EVENT_LINK_UP);\n\t\tbnx2x_link_report(sc);\n\t}\n\n\tif (!CHIP_REV_IS_SLOW(sc)) {\n\t\tbnx2x_periodic_start(sc);\n\t}\n\n\tsc->link_params.req_line_speed[cfg_idx] = req_line_speed;\n\treturn rc;\n}\n\n/* update flags in shmem */\nstatic void\nbnx2x_update_drv_flags(struct bnx2x_softc *sc, uint32_t flags, uint32_t set)\n{\n\tuint32_t drv_flags;\n\n\tif (SHMEM2_HAS(sc, drv_flags)) {\n\t\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);\n\t\tdrv_flags = SHMEM2_RD(sc, drv_flags);\n\n\t\tif (set) {\n\t\t\tdrv_flags |= flags;\n\t\t} else {\n\t\t\tdrv_flags &= ~flags;\n\t\t}\n\n\t\tSHMEM2_WR(sc, drv_flags, drv_flags);\n\n\t\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);\n\t}\n}\n\n/* periodic timer callout routine, only runs when the interface is up */\nvoid bnx2x_periodic_callout(struct bnx2x_softc *sc)\n{\n\tif ((sc->state != BNX2X_STATE_OPEN) ||\n\t (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {\n\t\tPMD_DRV_LOG(WARNING, \"periodic callout exit (state=0x%x)\",\n\t\t\t sc->state);\n\t\treturn;\n\t}\n\tif (!CHIP_REV_IS_SLOW(sc)) {\n/*\n * This barrier is needed to ensure the ordering between the writing\n * to the sc->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and\n * the reading here.\n */\n\t\tmb();\n\t\tif (sc->port.pmf) {\n\t\t\telink_period_func(&sc->link_params, &sc->link_vars);\n\t\t}\n\t}\n#ifdef BNX2X_PULSE\n\tif (IS_PF(sc) && !BNX2X_NOMCP(sc)) {\n\t\tint mb_idx = SC_FW_MB_IDX(sc);\n\t\tuint32_t drv_pulse;\n\t\tuint32_t mcp_pulse;\n\n\t\t++sc->fw_drv_pulse_wr_seq;\n\t\tsc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;\n\n\t\tdrv_pulse = sc->fw_drv_pulse_wr_seq;\n\t\tbnx2x_drv_pulse(sc);\n\n\t\tmcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &\n\t\t\t MCP_PULSE_SEQ_MASK);\n\n/*\n * The delta between driver pulse and mcp response should\n * be 1 (before mcp response) or 0 (after mcp response).\n */\n\t\tif ((drv_pulse != mcp_pulse) &&\n\t\t (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {\n\t\t\t/* someone lost a heartbeat... */\n\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t \"drv_pulse (0x%x) != mcp_pulse (0x%x)\",\n\t\t\t\t drv_pulse, mcp_pulse);\n\t\t}\n\t}\n#endif\n}\n\n/* start the controller */\nstatic __attribute__ ((noinline))\nint bnx2x_nic_load(struct bnx2x_softc *sc)\n{\n\tuint32_t val;\n\tuint32_t load_code = 0;\n\tint i, rc = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tsc->state = BNX2X_STATE_OPENING_WAITING_LOAD;\n\n\tif (IS_PF(sc)) {\n/* must be called before memory allocation and HW init */\n\t\tbnx2x_ilt_set_info(sc);\n\t}\n\n\tbnx2x_set_fp_rx_buf_size(sc);\n\n\tif (IS_PF(sc)) {\n\t\tif (bnx2x_alloc_mem(sc) != 0) {\n\t\t\tsc->state = BNX2X_STATE_CLOSED;\n\t\t\trc = -ENOMEM;\n\t\t\tgoto bnx2x_nic_load_error0;\n\t\t}\n\t}\n\n\tif (bnx2x_alloc_fw_stats_mem(sc) != 0) {\n\t\tsc->state = BNX2X_STATE_CLOSED;\n\t\trc = -ENOMEM;\n\t\tgoto bnx2x_nic_load_error0;\n\t}\n\n\tif (IS_VF(sc)) {\n\t\trc = bnx2x_vf_init(sc);\n\t\tif (rc) {\n\t\t\tsc->state = BNX2X_STATE_ERROR;\n\t\t\tgoto bnx2x_nic_load_error0;\n\t\t}\n\t}\n\n\tif (IS_PF(sc)) {\n/* set pf load just before approaching the MCP */\n\t\tbnx2x_set_pf_load(sc);\n\n/* if MCP exists send load request and analyze response */\n\t\tif (!BNX2X_NOMCP(sc)) {\n\t\t\t/* attempt to load pf */\n\t\t\tif (bnx2x_nic_load_request(sc, &load_code) != 0) {\n\t\t\t\tsc->state = BNX2X_STATE_CLOSED;\n\t\t\t\trc = -ENXIO;\n\t\t\t\tgoto bnx2x_nic_load_error1;\n\t\t\t}\n\n\t\t\t/* what did the MCP say? */\n\t\t\tif (bnx2x_nic_load_analyze_req(sc, load_code) != 0) {\n\t\t\t\tbnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);\n\t\t\t\tsc->state = BNX2X_STATE_CLOSED;\n\t\t\t\trc = -ENXIO;\n\t\t\t\tgoto bnx2x_nic_load_error2;\n\t\t\t}\n\t\t} else {\n\t\t\tPMD_DRV_LOG(INFO, \"Device has no MCP!\");\n\t\t\tload_code = bnx2x_nic_load_no_mcp(sc);\n\t\t}\n\n/* mark PMF if applicable */\n\t\tbnx2x_nic_load_pmf(sc, load_code);\n\n/* Init Function state controlling object */\n\t\tbnx2x_init_func_obj(sc);\n\n/* Initialize HW */\n\t\tif (bnx2x_init_hw(sc, load_code) != 0) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"HW init failed\");\n\t\t\tbnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);\n\t\t\tsc->state = BNX2X_STATE_CLOSED;\n\t\t\trc = -ENXIO;\n\t\t\tgoto bnx2x_nic_load_error2;\n\t\t}\n\t}\n\n\tbnx2x_nic_init(sc, load_code);\n\n\t/* Init per-function objects */\n\tif (IS_PF(sc)) {\n\t\tbnx2x_init_objs(sc);\n\n/* set AFEX default VLAN tag to an invalid value */\n\t\tsc->devinfo.mf_info.afex_def_vlan_tag = -1;\n\n\t\tsc->state = BNX2X_STATE_OPENING_WAITING_PORT;\n\t\trc = bnx2x_func_start(sc);\n\t\tif (rc) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"Function start failed!\");\n\t\t\tbnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);\n\t\t\tsc->state = BNX2X_STATE_ERROR;\n\t\t\tgoto bnx2x_nic_load_error3;\n\t\t}\n\n/* send LOAD_DONE command to MCP */\n\t\tif (!BNX2X_NOMCP(sc)) {\n\t\t\tload_code =\n\t\t\t bnx2x_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);\n\t\t\tif (!load_code) {\n\t\t\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t\t\t \"MCP response failure, aborting\");\n\t\t\t\tsc->state = BNX2X_STATE_ERROR;\n\t\t\t\trc = -ENXIO;\n\t\t\t\tgoto bnx2x_nic_load_error3;\n\t\t\t}\n\t\t}\n\t}\n\n\trc = bnx2x_setup_leading(sc);\n\tif (rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"Setup leading failed!\");\n\t\tsc->state = BNX2X_STATE_ERROR;\n\t\tgoto bnx2x_nic_load_error3;\n\t}\n\n\tFOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {\n\t\tif (IS_PF(sc))\n\t\t\trc = bnx2x_setup_queue(sc, &sc->fp[i], FALSE);\n\t\telse\t\t/* IS_VF(sc) */\n\t\t\trc = bnx2x_vf_setup_queue(sc, &sc->fp[i], FALSE);\n\n\t\tif (rc) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"Queue(%d) setup failed\", i);\n\t\t\tsc->state = BNX2X_STATE_ERROR;\n\t\t\tgoto bnx2x_nic_load_error3;\n\t\t}\n\t}\n\n\trc = bnx2x_init_rss_pf(sc);\n\tif (rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"PF RSS init failed\");\n\t\tsc->state = BNX2X_STATE_ERROR;\n\t\tgoto bnx2x_nic_load_error3;\n\t}\n\n\t/* now when Clients are configured we are ready to work */\n\tsc->state = BNX2X_STATE_OPEN;\n\n\t/* Configure a ucast MAC */\n\tif (IS_PF(sc)) {\n\t\trc = bnx2x_set_eth_mac(sc, TRUE);\n\t} else {\t\t/* IS_VF(sc) */\n\t\trc = bnx2x_vf_set_mac(sc, TRUE);\n\t}\n\n\tif (rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"Setting Ethernet MAC failed\");\n\t\tsc->state = BNX2X_STATE_ERROR;\n\t\tgoto bnx2x_nic_load_error3;\n\t}\n\n\tif (sc->port.pmf) {\n\t\trc = bnx2x_initial_phy_init(sc, LOAD_OPEN);\n\t\tif (rc) {\n\t\t\tsc->state = BNX2X_STATE_ERROR;\n\t\t\tgoto bnx2x_nic_load_error3;\n\t\t}\n\t}\n\n\tsc->link_params.feature_config_flags &=\n\t ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;\n\n\t/* start the Tx */\n\tswitch (LOAD_OPEN) {\n\tcase LOAD_NORMAL:\n\tcase LOAD_OPEN:\n\t\tbreak;\n\n\tcase LOAD_DIAG:\n\tcase LOAD_LOOPBACK_EXT:\n\t\tsc->state = BNX2X_STATE_DIAG;\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (sc->port.pmf) {\n\t\tbnx2x_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);\n\t} else {\n\t\tbnx2x_link_status_update(sc);\n\t}\n\n\tif (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {\n/* mark driver is loaded in shmem2 */\n\t\tval = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);\n\t\tSHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],\n\t\t\t (val |\n\t\t\t DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |\n\t\t\t DRV_FLAGS_CAPABILITIES_LOADED_L2));\n\t}\n\n\t/* start fast path */\n\t/* Initialize Rx filter */\n\tbnx2x_set_rx_mode(sc);\n\n\t/* wait for all pending SP commands to complete */\n\tif (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {\n\t\tPMD_DRV_LOG(NOTICE, \"Timeout waiting for all SPs to complete!\");\n\t\tbnx2x_periodic_stop(sc);\n\t\tbnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);\n\t\treturn -ENXIO;\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"NIC successfully loaded\");\n\n\treturn 0;\n\nbnx2x_nic_load_error3:\n\n\tif (IS_PF(sc)) {\n\t\tbnx2x_int_disable_sync(sc, 1);\n\n/* clean out queued objects */\n\t\tbnx2x_squeeze_objects(sc);\n\t}\n\nbnx2x_nic_load_error2:\n\n\tif (IS_PF(sc) && !BNX2X_NOMCP(sc)) {\n\t\tbnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);\n\t\tbnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);\n\t}\n\n\tsc->port.pmf = 0;\n\nbnx2x_nic_load_error1:\n\n\t/* clear pf_load status, as it was already set */\n\tif (IS_PF(sc)) {\n\t\tbnx2x_clear_pf_load(sc);\n\t}\n\nbnx2x_nic_load_error0:\n\n\tbnx2x_free_fw_stats_mem(sc);\n\tbnx2x_free_mem(sc);\n\n\treturn rc;\n}\n\n/*\n* Handles controller initialization.\n*/\nint bnx2x_init(struct bnx2x_softc *sc)\n{\n\tint other_engine = SC_PATH(sc) ? 0 : 1;\n\tuint8_t other_load_status, load_status;\n\tuint8_t global = FALSE;\n\tint rc;\n\n\t/* Check if the driver is still running and bail out if it is. */\n\tif (sc->link_vars.link_up) {\n\t\tPMD_DRV_LOG(DEBUG, \"Init called while driver is running!\");\n\t\trc = 0;\n\t\tgoto bnx2x_init_done;\n\t}\n\n\tbnx2x_set_power_state(sc, PCI_PM_D0);\n\n\t/*\n\t * If parity occurred during the unload, then attentions and/or\n\t * RECOVERY_IN_PROGRESS may still be set. If so we want the first function\n\t * loaded on the current engine to complete the recovery. Parity recovery\n\t * is only relevant for PF driver.\n\t */\n\tif (IS_PF(sc)) {\n\t\tother_load_status = bnx2x_get_load_status(sc, other_engine);\n\t\tload_status = bnx2x_get_load_status(sc, SC_PATH(sc));\n\n\t\tif (!bnx2x_reset_is_done(sc, SC_PATH(sc)) ||\n\t\t bnx2x_chk_parity_attn(sc, &global, TRUE)) {\n\t\t\tdo {\n\t\t\t\t/*\n\t\t\t\t * If there are attentions and they are in global blocks, set\n\t\t\t\t * the GLOBAL_RESET bit regardless whether it will be this\n\t\t\t\t * function that will complete the recovery or not.\n\t\t\t\t */\n\t\t\t\tif (global) {\n\t\t\t\t\tbnx2x_set_reset_global(sc);\n\t\t\t\t}\n\n\t\t\t\t/*\n\t\t\t\t * Only the first function on the current engine should try\n\t\t\t\t * to recover in open. In case of attentions in global blocks\n\t\t\t\t * only the first in the chip should try to recover.\n\t\t\t\t */\n\t\t\t\tif ((!load_status\n\t\t\t\t && (!global ||!other_load_status))\n\t\t\t\t && bnx2x_trylock_leader_lock(sc)\n\t\t\t\t && !bnx2x_leader_reset(sc)) {\n\t\t\t\t\tPMD_DRV_LOG(INFO,\n\t\t\t\t\t\t \"Recovered during init\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\t/* recovery has failed... */\n\t\t\t\tbnx2x_set_power_state(sc, PCI_PM_D3hot);\n\n\t\t\t\tsc->recovery_state = BNX2X_RECOVERY_FAILED;\n\n\t\t\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t\t\t \"Recovery flow hasn't properly \"\n\t\t\t\t\t \"completed yet, try again later. \"\n\t\t\t\t\t \"If you still see this message after a \"\n\t\t\t\t\t \"few retries then power cycle is required.\");\n\n\t\t\t\trc = -ENXIO;\n\t\t\t\tgoto bnx2x_init_done;\n\t\t\t} while (0);\n\t\t}\n\t}\n\n\tsc->recovery_state = BNX2X_RECOVERY_DONE;\n\n\trc = bnx2x_nic_load(sc);\n\nbnx2x_init_done:\n\n\tif (rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"Initialization failed, \"\n\t\t\t \"stack notified driver is NOT running!\");\n\t}\n\n\treturn rc;\n}\n\nstatic void bnx2x_get_function_num(struct bnx2x_softc *sc)\n{\n\tuint32_t val = 0;\n\n\t/*\n\t * Read the ME register to get the function number. The ME register\n\t * holds the relative-function number and absolute-function number. The\n\t * absolute-function number appears only in E2 and above. Before that\n\t * these bits always contained zero, therefore we cannot blindly use them.\n\t */\n\n\tval = REG_RD(sc, BAR_ME_REGISTER);\n\n\tsc->pfunc_rel =\n\t (uint8_t) ((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);\n\tsc->path_id =\n\t (uint8_t) ((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) &\n\t 1;\n\n\tif (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {\n\t\tsc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);\n\t} else {\n\t\tsc->pfunc_abs = (sc->pfunc_rel | sc->path_id);\n\t}\n\n\tPMD_DRV_LOG(DEBUG,\n\t\t \"Relative function %d, Absolute function %d, Path %d\",\n\t\t sc->pfunc_rel, sc->pfunc_abs, sc->path_id);\n}\n\nstatic uint32_t bnx2x_get_shmem_mf_cfg_base(struct bnx2x_softc *sc)\n{\n\tuint32_t shmem2_size;\n\tuint32_t offset;\n\tuint32_t mf_cfg_offset_value;\n\n\t/* Non 57712 */\n\toffset = (SHMEM_ADDR(sc, func_mb) +\n\t\t (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));\n\n\t/* 57712 plus */\n\tif (sc->devinfo.shmem2_base != 0) {\n\t\tshmem2_size = SHMEM2_RD(sc, size);\n\t\tif (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {\n\t\t\tmf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);\n\t\t\tif (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {\n\t\t\t\toffset = mf_cfg_offset_value;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn offset;\n}\n\nstatic uint32_t bnx2x_pcie_capability_read(struct bnx2x_softc *sc, int reg)\n{\n\tuint32_t ret;\n\tstruct bnx2x_pci_cap *caps;\n\n\t/* ensure PCIe capability is enabled */\n\tcaps = pci_find_cap(sc, PCIY_EXPRESS, BNX2X_PCI_CAP);\n\tif (NULL != caps) {\n\t\tPMD_DRV_LOG(DEBUG, \"Found PCIe capability: \"\n\t\t\t \"id=0x%04X type=0x%04X addr=0x%08X\",\n\t\t\t caps->id, caps->type, caps->addr);\n\t\tpci_read(sc, (caps->addr + reg), &ret, 2);\n\t\treturn ret;\n\t}\n\n\tPMD_DRV_LOG(WARNING, \"PCIe capability NOT FOUND!!!\");\n\n\treturn 0;\n}\n\nstatic uint8_t bnx2x_is_pcie_pending(struct bnx2x_softc *sc)\n{\n\treturn (bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA) &\n\t\tPCIM_EXP_STA_TRANSACTION_PND);\n}\n\n/*\n* Walk the PCI capabiites list for the device to find what features are\n* supported. These capabilites may be enabled/disabled by firmware so it's\n* best to walk the list rather than make assumptions.\n*/\nstatic void bnx2x_probe_pci_caps(struct bnx2x_softc *sc)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\tstruct bnx2x_pci_cap *caps;\n\tuint16_t link_status;\n#ifdef RTE_LIBRTE_BNX2X_DEBUG\n\tint reg = 0;\n#endif\n\n\t/* check if PCI Power Management is enabled */\n\tcaps = pci_find_cap(sc, PCIY_PMG, BNX2X_PCI_CAP);\n\tif (NULL != caps) {\n\t\tPMD_DRV_LOG(DEBUG, \"Found PM capability: \"\n\t\t\t \"id=0x%04X type=0x%04X addr=0x%08X\",\n\t\t\t caps->id, caps->type, caps->addr);\n\n\t\tsc->devinfo.pcie_cap_flags |= BNX2X_PM_CAPABLE_FLAG;\n\t\tsc->devinfo.pcie_pm_cap_reg = caps->addr;\n\t}\n\n\tlink_status = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA);\n\n\tsc->devinfo.pcie_link_speed = (link_status & PCIM_LINK_STA_SPEED);\n\tsc->devinfo.pcie_link_width =\n\t ((link_status & PCIM_LINK_STA_WIDTH) >> 4);\n\n\tPMD_DRV_LOG(DEBUG, \"PCIe link speed=%d width=%d\",\n\t\t sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);\n\n\tsc->devinfo.pcie_cap_flags |= BNX2X_PCIE_CAPABLE_FLAG;\n\n\t/* check if MSI capability is enabled */\n\tcaps = pci_find_cap(sc, PCIY_MSI, BNX2X_PCI_CAP);\n\tif (NULL != caps) {\n\t\tPMD_DRV_LOG(DEBUG, \"Found MSI capability at 0x%04x\", reg);\n\n\t\tsc->devinfo.pcie_cap_flags |= BNX2X_MSI_CAPABLE_FLAG;\n\t\tsc->devinfo.pcie_msi_cap_reg = caps->addr;\n\t}\n\n\t/* check if MSI-X capability is enabled */\n\tcaps = pci_find_cap(sc, PCIY_MSIX, BNX2X_PCI_CAP);\n\tif (NULL != caps) {\n\t\tPMD_DRV_LOG(DEBUG, \"Found MSI-X capability at 0x%04x\", reg);\n\n\t\tsc->devinfo.pcie_cap_flags |= BNX2X_MSIX_CAPABLE_FLAG;\n\t\tsc->devinfo.pcie_msix_cap_reg = caps->addr;\n\t}\n}\n\nstatic int bnx2x_get_shmem_mf_cfg_info_sd(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;\n\tuint32_t val;\n\n\t/* get the outer vlan if we're in switch-dependent mode */\n\n\tval = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);\n\tmf_info->ext_id = (uint16_t) val;\n\n\tmf_info->multi_vnics_mode = 1;\n\n\tif (!VALID_OVLAN(mf_info->ext_id)) {\n\t\tPMD_DRV_LOG(NOTICE, \"Invalid VLAN (%d)\", mf_info->ext_id);\n\t\treturn 1;\n\t}\n\n\t/* get the capabilities */\n\tif ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==\n\t FUNC_MF_CFG_PROTOCOL_ISCSI) {\n\t\tmf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;\n\t} else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK)\n\t\t == FUNC_MF_CFG_PROTOCOL_FCOE) {\n\t\tmf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;\n\t} else {\n\t\tmf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;\n\t}\n\n\tmf_info->vnics_per_port =\n\t (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;\n\n\treturn 0;\n}\n\nstatic uint32_t bnx2x_get_shmem_ext_proto_support_flags(struct bnx2x_softc *sc)\n{\n\tuint32_t retval = 0;\n\tuint32_t val;\n\n\tval = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);\n\n\tif (val & MACP_FUNC_CFG_FLAGS_ENABLED) {\n\t\tif (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {\n\t\t\tretval |= MF_PROTO_SUPPORT_ETHERNET;\n\t\t}\n\t\tif (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {\n\t\t\tretval |= MF_PROTO_SUPPORT_ISCSI;\n\t\t}\n\t\tif (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {\n\t\t\tretval |= MF_PROTO_SUPPORT_FCOE;\n\t\t}\n\t}\n\n\treturn retval;\n}\n\nstatic int bnx2x_get_shmem_mf_cfg_info_si(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;\n\tuint32_t val;\n\n\t/*\n\t * There is no outer vlan if we're in switch-independent mode.\n\t * If the mac is valid then assume multi-function.\n\t */\n\n\tval = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);\n\n\tmf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);\n\n\tmf_info->mf_protos_supported =\n\t bnx2x_get_shmem_ext_proto_support_flags(sc);\n\n\tmf_info->vnics_per_port =\n\t (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;\n\n\treturn 0;\n}\n\nstatic int bnx2x_get_shmem_mf_cfg_info_niv(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;\n\tuint32_t e1hov_tag;\n\tuint32_t func_config;\n\tuint32_t niv_config;\n\n\tmf_info->multi_vnics_mode = 1;\n\n\te1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);\n\tfunc_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);\n\tniv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);\n\n\tmf_info->ext_id =\n\t (uint16_t) ((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>\n\t\t\tFUNC_MF_CFG_E1HOV_TAG_SHIFT);\n\n\tmf_info->default_vlan =\n\t (uint16_t) ((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>\n\t\t\tFUNC_MF_CFG_AFEX_VLAN_SHIFT);\n\n\tmf_info->niv_allowed_priorities =\n\t (uint8_t) ((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>\n\t\t FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);\n\n\tmf_info->niv_default_cos =\n\t (uint8_t) ((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>\n\t\t FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);\n\n\tmf_info->afex_vlan_mode =\n\t ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>\n\t FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);\n\n\tmf_info->niv_mba_enabled =\n\t ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>\n\t FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);\n\n\tmf_info->mf_protos_supported =\n\t bnx2x_get_shmem_ext_proto_support_flags(sc);\n\n\tmf_info->vnics_per_port =\n\t (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;\n\n\treturn 0;\n}\n\nstatic int bnx2x_check_valid_mf_cfg(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;\n\tuint32_t mf_cfg1;\n\tuint32_t mf_cfg2;\n\tuint32_t ovlan1;\n\tuint32_t ovlan2;\n\tuint8_t i, j;\n\n\t/* various MF mode sanity checks... */\n\n\tif (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {\n\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t \"Enumerated function %d is marked as hidden\",\n\t\t\t SC_PORT(sc));\n\t\treturn 1;\n\t}\n\n\tif ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {\n\t\tPMD_DRV_LOG(NOTICE, \"vnics_per_port=%d multi_vnics_mode=%d\",\n\t\t\t mf_info->vnics_per_port, mf_info->multi_vnics_mode);\n\t\treturn 1;\n\t}\n\n\tif (mf_info->mf_mode == MULTI_FUNCTION_SD) {\n/* vnic id > 0 must have valid ovlan in switch-dependent mode */\n\t\tif ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"mf_mode=SD vnic_id=%d ovlan=%d\",\n\t\t\t\t SC_VN(sc), OVLAN(sc));\n\t\t\treturn 1;\n\t\t}\n\n\t\tif (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {\n\t\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t\t \"mf_mode=SD multi_vnics_mode=%d ovlan=%d\",\n\t\t\t\t mf_info->multi_vnics_mode, OVLAN(sc));\n\t\t\treturn 1;\n\t\t}\n\n/*\n * Verify all functions are either MF or SF mode. If MF, make sure\n * sure that all non-hidden functions have a valid ovlan. If SF,\n * make sure that all non-hidden functions have an invalid ovlan.\n */\n\t\tFOREACH_ABS_FUNC_IN_PORT(sc, i) {\n\t\t\tmf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);\n\t\t\tovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);\n\t\t\tif (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&\n\t\t\t (((mf_info->multi_vnics_mode)\n\t\t\t && !VALID_OVLAN(ovlan1))\n\t\t\t || ((!mf_info->multi_vnics_mode)\n\t\t\t\t && VALID_OVLAN(ovlan1)))) {\n\t\t\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t\t\t \"mf_mode=SD function %d MF config \"\n\t\t\t\t\t \"mismatch, multi_vnics_mode=%d ovlan=%d\",\n\t\t\t\t\t i, mf_info->multi_vnics_mode,\n\t\t\t\t\t ovlan1);\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t}\n\n/* Verify all funcs on the same port each have a different ovlan. */\n\t\tFOREACH_ABS_FUNC_IN_PORT(sc, i) {\n\t\t\tmf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);\n\t\t\tovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);\n\t\t\t/* iterate from the next function on the port to the max func */\n\t\t\tfor (j = i + 2; j < MAX_FUNC_NUM; j += 2) {\n\t\t\t\tmf_cfg2 =\n\t\t\t\t MFCFG_RD(sc, func_mf_config[j].config);\n\t\t\t\tovlan2 =\n\t\t\t\t MFCFG_RD(sc, func_mf_config[j].e1hov_tag);\n\t\t\t\tif (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE)\n\t\t\t\t && VALID_OVLAN(ovlan1)\n\t\t\t\t && !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE)\n\t\t\t\t && VALID_OVLAN(ovlan2)\n\t\t\t\t && (ovlan1 == ovlan2)) {\n\t\t\t\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t\t\t\t \"mf_mode=SD functions %d and %d \"\n\t\t\t\t\t\t \"have the same ovlan (%d)\",\n\t\t\t\t\t\t i, j, ovlan1);\n\t\t\t\t\treturn 1;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\t/* MULTI_FUNCTION_SD */\n\treturn 0;\n}\n\nstatic int bnx2x_get_mf_cfg_info(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_mf_info *mf_info = &sc->devinfo.mf_info;\n\tuint32_t val, mac_upper;\n\tuint8_t i, vnic;\n\n\t/* initialize mf_info defaults */\n\tmf_info->vnics_per_port = 1;\n\tmf_info->multi_vnics_mode = FALSE;\n\tmf_info->path_has_ovlan = FALSE;\n\tmf_info->mf_mode = SINGLE_FUNCTION;\n\n\tif (!CHIP_IS_MF_CAP(sc)) {\n\t\treturn 0;\n\t}\n\n\tif (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {\n\t\tPMD_DRV_LOG(NOTICE, \"Invalid mf_cfg_base!\");\n\t\treturn 1;\n\t}\n\n\t/* get the MF mode (switch dependent / independent / single-function) */\n\n\tval = SHMEM_RD(sc, dev_info.shared_feature_config.config);\n\n\tswitch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) {\n\tcase SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:\n\n\t\tmac_upper =\n\t\t MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);\n\n\t\t/* check for legal upper mac bytes */\n\t\tif (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {\n\t\t\tmf_info->mf_mode = MULTI_FUNCTION_SI;\n\t\t} else {\n\t\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t\t \"Invalid config for Switch Independent mode\");\n\t\t}\n\n\t\tbreak;\n\n\tcase SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:\n\tcase SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:\n\n\t\t/* get outer vlan configuration */\n\t\tval = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);\n\n\t\tif ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=\n\t\t FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {\n\t\t\tmf_info->mf_mode = MULTI_FUNCTION_SD;\n\t\t} else {\n\t\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t\t \"Invalid config for Switch Dependent mode\");\n\t\t}\n\n\t\tbreak;\n\n\tcase SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:\n\n\t\t/* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */\n\t\treturn 0;\n\n\tcase SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:\n\n\t\t/*\n\t\t * Mark MF mode as NIV if MCP version includes NPAR-SD support\n\t\t * and the MAC address is valid.\n\t\t */\n\t\tmac_upper =\n\t\t MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);\n\n\t\tif ((SHMEM2_HAS(sc, afex_driver_support)) &&\n\t\t (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {\n\t\t\tmf_info->mf_mode = MULTI_FUNCTION_AFEX;\n\t\t} else {\n\t\t\tPMD_DRV_LOG(NOTICE, \"Invalid config for AFEX mode\");\n\t\t}\n\n\t\tbreak;\n\n\tdefault:\n\n\t\tPMD_DRV_LOG(NOTICE, \"Unknown MF mode (0x%08x)\",\n\t\t\t (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));\n\n\t\treturn 1;\n\t}\n\n\t/* set path mf_mode (which could be different than function mf_mode) */\n\tif (mf_info->mf_mode == MULTI_FUNCTION_SD) {\n\t\tmf_info->path_has_ovlan = TRUE;\n\t} else if (mf_info->mf_mode == SINGLE_FUNCTION) {\n/*\n * Decide on path multi vnics mode. If we're not in MF mode and in\n * 4-port mode, this is good enough to check vnic-0 of the other port\n * on the same path\n */\n\t\tif (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {\n\t\t\tuint8_t other_port = !(PORT_ID(sc) & 1);\n\t\t\tuint8_t abs_func_other_port =\n\t\t\t (SC_PATH(sc) + (2 * other_port));\n\n\t\t\tval =\n\t\t\t MFCFG_RD(sc,\n\t\t\t\t func_mf_config\n\t\t\t\t [abs_func_other_port].e1hov_tag);\n\n\t\t\tmf_info->path_has_ovlan = VALID_OVLAN((uint16_t) val);\n\t\t}\n\t}\n\n\tif (mf_info->mf_mode == SINGLE_FUNCTION) {\n/* invalid MF config */\n\t\tif (SC_VN(sc) >= 1) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"VNIC ID >= 1 in SF mode\");\n\t\t\treturn 1;\n\t\t}\n\n\t\treturn 0;\n\t}\n\n\t/* get the MF configuration */\n\tmf_info->mf_config[SC_VN(sc)] =\n\t MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);\n\n\tswitch (mf_info->mf_mode) {\n\tcase MULTI_FUNCTION_SD:\n\n\t\tbnx2x_get_shmem_mf_cfg_info_sd(sc);\n\t\tbreak;\n\n\tcase MULTI_FUNCTION_SI:\n\n\t\tbnx2x_get_shmem_mf_cfg_info_si(sc);\n\t\tbreak;\n\n\tcase MULTI_FUNCTION_AFEX:\n\n\t\tbnx2x_get_shmem_mf_cfg_info_niv(sc);\n\t\tbreak;\n\n\tdefault:\n\n\t\tPMD_DRV_LOG(NOTICE, \"Get MF config failed (mf_mode=0x%08x)\",\n\t\t\t mf_info->mf_mode);\n\t\treturn 1;\n\t}\n\n\t/* get the congestion management parameters */\n\n\tvnic = 0;\n\tFOREACH_ABS_FUNC_IN_PORT(sc, i) {\n/* get min/max bw */\n\t\tval = MFCFG_RD(sc, func_mf_config[i].config);\n\t\tmf_info->min_bw[vnic] =\n\t\t ((val & FUNC_MF_CFG_MIN_BW_MASK) >>\n\t\t FUNC_MF_CFG_MIN_BW_SHIFT);\n\t\tmf_info->max_bw[vnic] =\n\t\t ((val & FUNC_MF_CFG_MAX_BW_MASK) >>\n\t\t FUNC_MF_CFG_MAX_BW_SHIFT);\n\t\tvnic++;\n\t}\n\n\treturn bnx2x_check_valid_mf_cfg(sc);\n}\n\nstatic int bnx2x_get_shmem_info(struct bnx2x_softc *sc)\n{\n\tint port;\n\tuint32_t mac_hi, mac_lo, val;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tport = SC_PORT(sc);\n\tmac_hi = mac_lo = 0;\n\n\tsc->link_params.sc = sc;\n\tsc->link_params.port = port;\n\n\t/* get the hardware config info */\n\tsc->devinfo.hw_config = SHMEM_RD(sc, dev_info.shared_hw_config.config);\n\tsc->devinfo.hw_config2 =\n\t SHMEM_RD(sc, dev_info.shared_hw_config.config2);\n\n\tsc->link_params.hw_led_mode =\n\t ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>\n\t SHARED_HW_CFG_LED_MODE_SHIFT);\n\n\t/* get the port feature config */\n\tsc->port.config =\n\t SHMEM_RD(sc, dev_info.port_feature_config[port].config);\n\n\t/* get the link params */\n\tsc->link_params.speed_cap_mask[ELINK_INT_PHY] =\n\t SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask)\n\t & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;\n\tsc->link_params.speed_cap_mask[ELINK_EXT_PHY1] =\n\t SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2)\n\t & PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;\n\n\t/* get the lane config */\n\tsc->link_params.lane_config =\n\t SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);\n\n\t/* get the link config */\n\tval = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);\n\tsc->port.link_config[ELINK_INT_PHY] = val;\n\tsc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);\n\tsc->port.link_config[ELINK_EXT_PHY1] =\n\t SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);\n\n\t/* get the override preemphasis flag and enable it or turn it off */\n\tval = SHMEM_RD(sc, dev_info.shared_feature_config.config);\n\tif (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {\n\t\tsc->link_params.feature_config_flags |=\n\t\t ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;\n\t} else {\n\t\tsc->link_params.feature_config_flags &=\n\t\t ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;\n\t}\n\n\t/* get the initial value of the link params */\n\tsc->link_params.multi_phy_config =\n\t SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);\n\n\t/* get external phy info */\n\tsc->port.ext_phy_config =\n\t SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);\n\n\t/* get the multifunction configuration */\n\tbnx2x_get_mf_cfg_info(sc);\n\n\t/* get the mac address */\n\tif (IS_MF(sc)) {\n\t\tmac_hi =\n\t\t MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);\n\t\tmac_lo =\n\t\t MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);\n\t} else {\n\t\tmac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);\n\t\tmac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);\n\t}\n\n\tif ((mac_lo == 0) && (mac_hi == 0)) {\n\t\t*sc->mac_addr_str = 0;\n\t\tPMD_DRV_LOG(NOTICE, \"No Ethernet address programmed!\");\n\t} else {\n\t\tsc->link_params.mac_addr[0] = (uint8_t) (mac_hi >> 8);\n\t\tsc->link_params.mac_addr[1] = (uint8_t) (mac_hi);\n\t\tsc->link_params.mac_addr[2] = (uint8_t) (mac_lo >> 24);\n\t\tsc->link_params.mac_addr[3] = (uint8_t) (mac_lo >> 16);\n\t\tsc->link_params.mac_addr[4] = (uint8_t) (mac_lo >> 8);\n\t\tsc->link_params.mac_addr[5] = (uint8_t) (mac_lo);\n\t\tsnprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),\n\t\t\t \"%02x:%02x:%02x:%02x:%02x:%02x\",\n\t\t\t sc->link_params.mac_addr[0],\n\t\t\t sc->link_params.mac_addr[1],\n\t\t\t sc->link_params.mac_addr[2],\n\t\t\t sc->link_params.mac_addr[3],\n\t\t\t sc->link_params.mac_addr[4],\n\t\t\t sc->link_params.mac_addr[5]);\n\t\tPMD_DRV_LOG(DEBUG, \"Ethernet address: %s\", sc->mac_addr_str);\n\t}\n\n\treturn 0;\n}\n\nstatic void bnx2x_media_detect(struct bnx2x_softc *sc)\n{\n\tuint32_t phy_idx = bnx2x_get_cur_phy_idx(sc);\n\tswitch (sc->link_params.phy[phy_idx].media_type) {\n\tcase ELINK_ETH_PHY_SFPP_10G_FIBER:\n\tcase ELINK_ETH_PHY_SFP_1G_FIBER:\n\tcase ELINK_ETH_PHY_XFP_FIBER:\n\tcase ELINK_ETH_PHY_KR:\n\tcase ELINK_ETH_PHY_CX4:\n\t\tPMD_DRV_LOG(INFO, \"Found 10GBase-CX4 media.\");\n\t\tsc->media = IFM_10G_CX4;\n\t\tbreak;\n\tcase ELINK_ETH_PHY_DA_TWINAX:\n\t\tPMD_DRV_LOG(INFO, \"Found 10Gb Twinax media.\");\n\t\tsc->media = IFM_10G_TWINAX;\n\t\tbreak;\n\tcase ELINK_ETH_PHY_BASE_T:\n\t\tPMD_DRV_LOG(INFO, \"Found 10GBase-T media.\");\n\t\tsc->media = IFM_10G_T;\n\t\tbreak;\n\tcase ELINK_ETH_PHY_NOT_PRESENT:\n\t\tPMD_DRV_LOG(INFO, \"Media not present.\");\n\t\tsc->media = 0;\n\t\tbreak;\n\tcase ELINK_ETH_PHY_UNSPECIFIED:\n\tdefault:\n\t\tPMD_DRV_LOG(INFO, \"Unknown media!\");\n\t\tsc->media = 0;\n\t\tbreak;\n\t}\n}\n\n#define GET_FIELD(value, fname) \\\n(((value) & (fname##_MASK)) >> (fname##_SHIFT))\n#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)\n#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)\n\nstatic int bnx2x_get_igu_cam_info(struct bnx2x_softc *sc)\n{\n\tint pfid = SC_FUNC(sc);\n\tint igu_sb_id;\n\tuint32_t val;\n\tuint8_t fid, igu_sb_cnt = 0;\n\n\tsc->igu_base_sb = 0xff;\n\n\tif (CHIP_INT_MODE_IS_BC(sc)) {\n\t\tint vn = SC_VN(sc);\n\t\tigu_sb_cnt = sc->igu_sb_cnt;\n\t\tsc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *\n\t\t\t\t FP_SB_MAX_E1x);\n\t\tsc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +\n\t\t\t\t (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));\n\t\treturn 0;\n\t}\n\n\t/* IGU in normal mode - read CAM */\n\tfor (igu_sb_id = 0;\n\t igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; igu_sb_id++) {\n\t\tval = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);\n\t\tif (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {\n\t\t\tcontinue;\n\t\t}\n\t\tfid = IGU_FID(val);\n\t\tif ((fid & IGU_FID_ENCODE_IS_PF)) {\n\t\t\tif ((fid & IGU_FID_PF_NUM_MASK) != pfid) {\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (IGU_VEC(val) == 0) {\n\t\t\t\t/* default status block */\n\t\t\t\tsc->igu_dsb_id = igu_sb_id;\n\t\t\t} else {\n\t\t\t\tif (sc->igu_base_sb == 0xff) {\n\t\t\t\t\tsc->igu_base_sb = igu_sb_id;\n\t\t\t\t}\n\t\t\t\tigu_sb_cnt++;\n\t\t\t}\n\t\t}\n\t}\n\n\t/*\n\t * Due to new PF resource allocation by MFW T7.4 and above, it's optional\n\t * that number of CAM entries will not be equal to the value advertised in\n\t * PCI. Driver should use the minimal value of both as the actual status\n\t * block count\n\t */\n\tsc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);\n\n\tif (igu_sb_cnt == 0) {\n\t\tPMD_DRV_LOG(ERR, \"CAM configuration error\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/*\n* Gather various information from the device config space, the device itself,\n* shmem, and the user input.\n*/\nstatic int bnx2x_get_device_info(struct bnx2x_softc *sc)\n{\n\tuint32_t val;\n\tint rc;\n\n\t/* get the chip revision (chip metal comes from pci config space) */\n\tsc->devinfo.chip_id = sc->link_params.chip_id =\n\t (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |\n\t ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |\n\t (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |\n\t ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));\n\n\t/* force 57811 according to MISC register */\n\tif (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {\n\t\tif (CHIP_IS_57810(sc)) {\n\t\t\tsc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |\n\t\t\t\t\t (sc->\n\t\t\t\t\t\tdevinfo.chip_id & 0x0000ffff));\n\t\t} else if (CHIP_IS_57810_MF(sc)) {\n\t\t\tsc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |\n\t\t\t\t\t (sc->\n\t\t\t\t\t\tdevinfo.chip_id & 0x0000ffff));\n\t\t}\n\t\tsc->devinfo.chip_id |= 0x1;\n\t}\n\n\tPMD_DRV_LOG(DEBUG,\n\t\t \"chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)\",\n\t\t sc->devinfo.chip_id,\n\t\t ((sc->devinfo.chip_id >> 16) & 0xffff),\n\t\t ((sc->devinfo.chip_id >> 12) & 0xf),\n\t\t ((sc->devinfo.chip_id >> 4) & 0xff),\n\t\t ((sc->devinfo.chip_id >> 0) & 0xf));\n\n\tval = (REG_RD(sc, 0x2874) & 0x55);\n\tif ((sc->devinfo.chip_id & 0x1) || (CHIP_IS_E1H(sc) && (val == 0x55))) {\n\t\tsc->flags |= BNX2X_ONE_PORT_FLAG;\n\t\tPMD_DRV_LOG(DEBUG, \"single port device\");\n\t}\n\n\t/* set the doorbell size */\n\tsc->doorbell_size = (1 << BNX2X_DB_SHIFT);\n\n\t/* determine whether the device is in 2 port or 4 port mode */\n\tsc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE;\t/* E1h */\n\tif (CHIP_IS_E2E3(sc)) {\n/*\n * Read port4mode_en_ovwr[0]:\n * If 1, four port mode is in port4mode_en_ovwr[1].\n * If 0, four port mode is in port4mode_en[0].\n */\n\t\tval = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);\n\t\tif (val & 1) {\n\t\t\tval = ((val >> 1) & 1);\n\t\t} else {\n\t\t\tval = REG_RD(sc, MISC_REG_PORT4MODE_EN);\n\t\t}\n\n\t\tsc->devinfo.chip_port_mode =\n\t\t (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;\n\n\t\tPMD_DRV_LOG(DEBUG, \"Port mode = %s\", (val) ? \"4\" : \"2\");\n\t}\n\n\t/* get the function and path info for the device */\n\tbnx2x_get_function_num(sc);\n\n\t/* get the shared memory base address */\n\tsc->devinfo.shmem_base =\n\t sc->link_params.shmem_base = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);\n\tsc->devinfo.shmem2_base =\n\t REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :\n\t\t\tMISC_REG_GENERIC_CR_0));\n\n\tif (!sc->devinfo.shmem_base) {\n/* this should ONLY prevent upcoming shmem reads */\n\t\tPMD_DRV_LOG(INFO, \"MCP not active\");\n\t\tsc->flags |= BNX2X_NO_MCP_FLAG;\n\t\treturn 0;\n\t}\n\n\t/* make sure the shared memory contents are valid */\n\tval = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);\n\tif ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=\n\t (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {\n\t\tPMD_DRV_LOG(NOTICE, \"Invalid SHMEM validity signature: 0x%08x\",\n\t\t\t val);\n\t\treturn 0;\n\t}\n\n\t/* get the bootcode version */\n\tsc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);\n\tsnprintf(sc->devinfo.bc_ver_str,\n\t\t sizeof(sc->devinfo.bc_ver_str),\n\t\t \"%d.%d.%d\",\n\t\t ((sc->devinfo.bc_ver >> 24) & 0xff),\n\t\t ((sc->devinfo.bc_ver >> 16) & 0xff),\n\t\t ((sc->devinfo.bc_ver >> 8) & 0xff));\n\tPMD_DRV_LOG(INFO, \"Bootcode version: %s\", sc->devinfo.bc_ver_str);\n\n\t/* get the bootcode shmem address */\n\tsc->devinfo.mf_cfg_base = bnx2x_get_shmem_mf_cfg_base(sc);\n\n\t/* clean indirect addresses as they're not used */\n\tpci_write_long(sc, PCICFG_GRC_ADDRESS, 0);\n\tif (IS_PF(sc)) {\n\t\tREG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);\n\t\tREG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);\n\t\tREG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);\n\t\tREG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);\n\t\tif (CHIP_IS_E1x(sc)) {\n\t\t\tREG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);\n\t\t\tREG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);\n\t\t\tREG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);\n\t\t\tREG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);\n\t\t}\n\n/*\n * Enable internal target-read (in case we are probed after PF\n * FLR). Must be done prior to any BAR read access. Only for\n * 57712 and up\n */\n\t\tif (!CHIP_IS_E1x(sc)) {\n\t\t\tREG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ,\n\t\t\t 1);\n\t\t}\n\t}\n\n\t/* get the nvram size */\n\tval = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);\n\tsc->devinfo.flash_size =\n\t (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));\n\n\tbnx2x_set_power_state(sc, PCI_PM_D0);\n\t/* get various configuration parameters from shmem */\n\tbnx2x_get_shmem_info(sc);\n\n\t/* initialize IGU parameters */\n\tif (CHIP_IS_E1x(sc)) {\n\t\tsc->devinfo.int_block = INT_BLOCK_HC;\n\t\tsc->igu_dsb_id = DEF_SB_IGU_ID;\n\t\tsc->igu_base_sb = 0;\n\t} else {\n\t\tsc->devinfo.int_block = INT_BLOCK_IGU;\n\n/* do not allow device reset during IGU info preocessing */\n\t\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);\n\n\t\tval = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);\n\n\t\tif (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {\n\t\t\tint tout = 5000;\n\n\t\t\tval &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);\n\t\t\tREG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);\n\t\t\tREG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);\n\n\t\t\twhile (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {\n\t\t\t\ttout--;\n\t\t\t\tDELAY(1000);\n\t\t\t}\n\n\t\t\tif (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {\n\t\t\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t\t\t \"FORCING IGU Normal Mode failed!!!\");\n\t\t\t\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\n\t\tif (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"IGU Backward Compatible Mode\");\n\t\t\tsc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;\n\t\t} else {\n\t\t\tPMD_DRV_LOG(DEBUG, \"IGU Normal Mode\");\n\t\t}\n\n\t\trc = bnx2x_get_igu_cam_info(sc);\n\n\t\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);\n\n\t\tif (rc) {\n\t\t\treturn rc;\n\t\t}\n\t}\n\n\t/*\n\t * Get base FW non-default (fast path) status block ID. This value is\n\t * used to initialize the fw_sb_id saved on the fp/queue structure to\n\t * determine the id used by the FW.\n\t */\n\tif (CHIP_IS_E1x(sc)) {\n\t\tsc->base_fw_ndsb =\n\t\t ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));\n\t} else {\n/*\n * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of\n * the same queue are indicated on the same IGU SB). So we prefer\n * FW and IGU SBs to be the same value.\n */\n\t\tsc->base_fw_ndsb = sc->igu_base_sb;\n\t}\n\n\telink_phy_probe(&sc->link_params);\n\n\treturn 0;\n}\n\nstatic void\nbnx2x_link_settings_supported(struct bnx2x_softc *sc, uint32_t switch_cfg)\n{\n\tuint32_t cfg_size = 0;\n\tuint32_t idx;\n\tuint8_t port = SC_PORT(sc);\n\n\t/* aggregation of supported attributes of all external phys */\n\tsc->port.supported[0] = 0;\n\tsc->port.supported[1] = 0;\n\n\tswitch (sc->link_params.num_phys) {\n\tcase 1:\n\t\tsc->port.supported[0] =\n\t\t sc->link_params.phy[ELINK_INT_PHY].supported;\n\t\tcfg_size = 1;\n\t\tbreak;\n\tcase 2:\n\t\tsc->port.supported[0] =\n\t\t sc->link_params.phy[ELINK_EXT_PHY1].supported;\n\t\tcfg_size = 1;\n\t\tbreak;\n\tcase 3:\n\t\tif (sc->link_params.multi_phy_config &\n\t\t PORT_HW_CFG_PHY_SWAPPED_ENABLED) {\n\t\t\tsc->port.supported[1] =\n\t\t\t sc->link_params.phy[ELINK_EXT_PHY1].supported;\n\t\t\tsc->port.supported[0] =\n\t\t\t sc->link_params.phy[ELINK_EXT_PHY2].supported;\n\t\t} else {\n\t\t\tsc->port.supported[0] =\n\t\t\t sc->link_params.phy[ELINK_EXT_PHY1].supported;\n\t\t\tsc->port.supported[1] =\n\t\t\t sc->link_params.phy[ELINK_EXT_PHY2].supported;\n\t\t}\n\t\tcfg_size = 2;\n\t\tbreak;\n\t}\n\n\tif (!(sc->port.supported[0] || sc->port.supported[1])) {\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)\",\n\t\t\t SHMEM_RD(sc,\n\t\t\t\t dev_info.port_hw_config\n\t\t\t\t [port].external_phy_config),\n\t\t\t SHMEM_RD(sc,\n\t\t\t\t dev_info.port_hw_config\n\t\t\t\t [port].external_phy_config2));\n\t\treturn;\n\t}\n\n\tif (CHIP_IS_E3(sc))\n\t\tsc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);\n\telse {\n\t\tswitch (switch_cfg) {\n\t\tcase ELINK_SWITCH_CFG_1G:\n\t\t\tsc->port.phy_addr =\n\t\t\t REG_RD(sc,\n\t\t\t\t NIG_REG_SERDES0_CTRL_PHY_ADDR + port * 0x10);\n\t\t\tbreak;\n\t\tcase ELINK_SWITCH_CFG_10G:\n\t\t\tsc->port.phy_addr =\n\t\t\t REG_RD(sc,\n\t\t\t\t NIG_REG_XGXS0_CTRL_PHY_ADDR + port * 0x18);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t \"Invalid switch config in\"\n\t\t\t\t \"link_config=0x%08x\",\n\t\t\t\t sc->port.link_config[0]);\n\t\t\treturn;\n\t\t}\n\t}\n\n\tPMD_DRV_LOG(INFO, \"PHY addr 0x%08x\", sc->port.phy_addr);\n\n\t/* mask what we support according to speed_cap_mask per configuration */\n\tfor (idx = 0; idx < cfg_size; idx++) {\n\t\tif (!(sc->link_params.speed_cap_mask[idx] &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {\n\t\t\tsc->port.supported[idx] &=\n\t\t\t ~ELINK_SUPPORTED_10baseT_Half;\n\t\t}\n\n\t\tif (!(sc->link_params.speed_cap_mask[idx] &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {\n\t\t\tsc->port.supported[idx] &=\n\t\t\t ~ELINK_SUPPORTED_10baseT_Full;\n\t\t}\n\n\t\tif (!(sc->link_params.speed_cap_mask[idx] &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {\n\t\t\tsc->port.supported[idx] &=\n\t\t\t ~ELINK_SUPPORTED_100baseT_Half;\n\t\t}\n\n\t\tif (!(sc->link_params.speed_cap_mask[idx] &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {\n\t\t\tsc->port.supported[idx] &=\n\t\t\t ~ELINK_SUPPORTED_100baseT_Full;\n\t\t}\n\n\t\tif (!(sc->link_params.speed_cap_mask[idx] &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {\n\t\t\tsc->port.supported[idx] &=\n\t\t\t ~ELINK_SUPPORTED_1000baseT_Full;\n\t\t}\n\n\t\tif (!(sc->link_params.speed_cap_mask[idx] &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {\n\t\t\tsc->port.supported[idx] &=\n\t\t\t ~ELINK_SUPPORTED_2500baseX_Full;\n\t\t}\n\n\t\tif (!(sc->link_params.speed_cap_mask[idx] &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {\n\t\t\tsc->port.supported[idx] &=\n\t\t\t ~ELINK_SUPPORTED_10000baseT_Full;\n\t\t}\n\n\t\tif (!(sc->link_params.speed_cap_mask[idx] &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {\n\t\t\tsc->port.supported[idx] &=\n\t\t\t ~ELINK_SUPPORTED_20000baseKR2_Full;\n\t\t}\n\t}\n\n\tPMD_DRV_LOG(INFO, \"PHY supported 0=0x%08x 1=0x%08x\",\n\t\t sc->port.supported[0], sc->port.supported[1]);\n}\n\nstatic void bnx2x_link_settings_requested(struct bnx2x_softc *sc)\n{\n\tuint32_t link_config;\n\tuint32_t idx;\n\tuint32_t cfg_size = 0;\n\n\tsc->port.advertising[0] = 0;\n\tsc->port.advertising[1] = 0;\n\n\tswitch (sc->link_params.num_phys) {\n\tcase 1:\n\tcase 2:\n\t\tcfg_size = 1;\n\t\tbreak;\n\tcase 3:\n\t\tcfg_size = 2;\n\t\tbreak;\n\t}\n\n\tfor (idx = 0; idx < cfg_size; idx++) {\n\t\tsc->link_params.req_duplex[idx] = DUPLEX_FULL;\n\t\tlink_config = sc->port.link_config[idx];\n\n\t\tswitch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {\n\t\tcase PORT_FEATURE_LINK_SPEED_AUTO:\n\t\t\tif (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {\n\t\t\t\tsc->link_params.req_line_speed[idx] =\n\t\t\t\t ELINK_SPEED_AUTO_NEG;\n\t\t\t\tsc->port.advertising[idx] |=\n\t\t\t\t sc->port.supported[idx];\n\t\t\t\tif (sc->link_params.phy[ELINK_EXT_PHY1].type ==\n\t\t\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833)\n\t\t\t\t\tsc->port.advertising[idx] |=\n\t\t\t\t\t (ELINK_SUPPORTED_100baseT_Half |\n\t\t\t\t\t ELINK_SUPPORTED_100baseT_Full);\n\t\t\t} else {\n\t\t\t\t/* force 10G, no AN */\n\t\t\t\tsc->link_params.req_line_speed[idx] =\n\t\t\t\t ELINK_SPEED_10000;\n\t\t\t\tsc->port.advertising[idx] |=\n\t\t\t\t (ADVERTISED_10000baseT_Full |\n\t\t\t\t ADVERTISED_FIBRE);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase PORT_FEATURE_LINK_SPEED_10M_FULL:\n\t\t\tif (sc->\n\t\t\t port.supported[idx] & ELINK_SUPPORTED_10baseT_Full)\n\t\t\t{\n\t\t\t\tsc->link_params.req_line_speed[idx] =\n\t\t\t\t ELINK_SPEED_10;\n\t\t\t\tsc->port.advertising[idx] |=\n\t\t\t\t (ADVERTISED_10baseT_Full | ADVERTISED_TP);\n\t\t\t} else {\n\t\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\t \"Invalid NVRAM config link_config=0x%08x \"\n\t\t\t\t\t \"speed_cap_mask=0x%08x\",\n\t\t\t\t\t link_config,\n\t\t\t\t\t sc->\n\t\t\t\t\t link_params.speed_cap_mask[idx]);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase PORT_FEATURE_LINK_SPEED_10M_HALF:\n\t\t\tif (sc->\n\t\t\t port.supported[idx] & ELINK_SUPPORTED_10baseT_Half)\n\t\t\t{\n\t\t\t\tsc->link_params.req_line_speed[idx] =\n\t\t\t\t ELINK_SPEED_10;\n\t\t\t\tsc->link_params.req_duplex[idx] = DUPLEX_HALF;\n\t\t\t\tsc->port.advertising[idx] |=\n\t\t\t\t (ADVERTISED_10baseT_Half | ADVERTISED_TP);\n\t\t\t} else {\n\t\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\t \"Invalid NVRAM config link_config=0x%08x \"\n\t\t\t\t\t \"speed_cap_mask=0x%08x\",\n\t\t\t\t\t link_config,\n\t\t\t\t\t sc->\n\t\t\t\t\t link_params.speed_cap_mask[idx]);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase PORT_FEATURE_LINK_SPEED_100M_FULL:\n\t\t\tif (sc->\n\t\t\t port.supported[idx] & ELINK_SUPPORTED_100baseT_Full)\n\t\t\t{\n\t\t\t\tsc->link_params.req_line_speed[idx] =\n\t\t\t\t ELINK_SPEED_100;\n\t\t\t\tsc->port.advertising[idx] |=\n\t\t\t\t (ADVERTISED_100baseT_Full | ADVERTISED_TP);\n\t\t\t} else {\n\t\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\t \"Invalid NVRAM config link_config=0x%08x \"\n\t\t\t\t\t \"speed_cap_mask=0x%08x\",\n\t\t\t\t\t link_config,\n\t\t\t\t\t sc->\n\t\t\t\t\t link_params.speed_cap_mask[idx]);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase PORT_FEATURE_LINK_SPEED_100M_HALF:\n\t\t\tif (sc->\n\t\t\t port.supported[idx] & ELINK_SUPPORTED_100baseT_Half)\n\t\t\t{\n\t\t\t\tsc->link_params.req_line_speed[idx] =\n\t\t\t\t ELINK_SPEED_100;\n\t\t\t\tsc->link_params.req_duplex[idx] = DUPLEX_HALF;\n\t\t\t\tsc->port.advertising[idx] |=\n\t\t\t\t (ADVERTISED_100baseT_Half | ADVERTISED_TP);\n\t\t\t} else {\n\t\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\t \"Invalid NVRAM config link_config=0x%08x \"\n\t\t\t\t\t \"speed_cap_mask=0x%08x\",\n\t\t\t\t\t link_config,\n\t\t\t\t\t sc->\n\t\t\t\t\t link_params.speed_cap_mask[idx]);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase PORT_FEATURE_LINK_SPEED_1G:\n\t\t\tif (sc->port.supported[idx] &\n\t\t\t ELINK_SUPPORTED_1000baseT_Full) {\n\t\t\t\tsc->link_params.req_line_speed[idx] =\n\t\t\t\t ELINK_SPEED_1000;\n\t\t\t\tsc->port.advertising[idx] |=\n\t\t\t\t (ADVERTISED_1000baseT_Full | ADVERTISED_TP);\n\t\t\t} else {\n\t\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\t \"Invalid NVRAM config link_config=0x%08x \"\n\t\t\t\t\t \"speed_cap_mask=0x%08x\",\n\t\t\t\t\t link_config,\n\t\t\t\t\t sc->\n\t\t\t\t\t link_params.speed_cap_mask[idx]);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase PORT_FEATURE_LINK_SPEED_2_5G:\n\t\t\tif (sc->port.supported[idx] &\n\t\t\t ELINK_SUPPORTED_2500baseX_Full) {\n\t\t\t\tsc->link_params.req_line_speed[idx] =\n\t\t\t\t ELINK_SPEED_2500;\n\t\t\t\tsc->port.advertising[idx] |=\n\t\t\t\t (ADVERTISED_2500baseX_Full | ADVERTISED_TP);\n\t\t\t} else {\n\t\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\t \"Invalid NVRAM config link_config=0x%08x \"\n\t\t\t\t\t \"speed_cap_mask=0x%08x\",\n\t\t\t\t\t link_config,\n\t\t\t\t\t sc->\n\t\t\t\t\t link_params.speed_cap_mask[idx]);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase PORT_FEATURE_LINK_SPEED_10G_CX4:\n\t\t\tif (sc->port.supported[idx] &\n\t\t\t ELINK_SUPPORTED_10000baseT_Full) {\n\t\t\t\tsc->link_params.req_line_speed[idx] =\n\t\t\t\t ELINK_SPEED_10000;\n\t\t\t\tsc->port.advertising[idx] |=\n\t\t\t\t (ADVERTISED_10000baseT_Full |\n\t\t\t\t ADVERTISED_FIBRE);\n\t\t\t} else {\n\t\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\t \"Invalid NVRAM config link_config=0x%08x \"\n\t\t\t\t\t \"speed_cap_mask=0x%08x\",\n\t\t\t\t\t link_config,\n\t\t\t\t\t sc->\n\t\t\t\t\t link_params.speed_cap_mask[idx]);\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase PORT_FEATURE_LINK_SPEED_20G:\n\t\t\tsc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t \"Invalid NVRAM config link_config=0x%08x \"\n\t\t\t\t \"speed_cap_mask=0x%08x\", link_config,\n\t\t\t\t sc->link_params.speed_cap_mask[idx]);\n\t\t\tsc->link_params.req_line_speed[idx] =\n\t\t\t ELINK_SPEED_AUTO_NEG;\n\t\t\tsc->port.advertising[idx] = sc->port.supported[idx];\n\t\t\tbreak;\n\t\t}\n\n\t\tsc->link_params.req_flow_ctrl[idx] =\n\t\t (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);\n\n\t\tif (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {\n\t\t\tif (!\n\t\t\t (sc->\n\t\t\t port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {\n\t\t\t\tsc->link_params.req_flow_ctrl[idx] =\n\t\t\t\t ELINK_FLOW_CTRL_NONE;\n\t\t\t} else {\n\t\t\t\tbnx2x_set_requested_fc(sc);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void bnx2x_get_phy_info(struct bnx2x_softc *sc)\n{\n\tuint8_t port = SC_PORT(sc);\n\tuint32_t eee_mode;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* shmem data already read in bnx2x_get_shmem_info() */\n\n\tbnx2x_link_settings_supported(sc, sc->link_params.switch_cfg);\n\tbnx2x_link_settings_requested(sc);\n\n\t/* configure link feature according to nvram value */\n\teee_mode =\n\t (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode))\n\t & PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>\n\t PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);\n\tif (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {\n\t\tsc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |\n\t\t\t\t\t ELINK_EEE_MODE_ENABLE_LPI |\n\t\t\t\t\t ELINK_EEE_MODE_OUTPUT_TIME);\n\t} else {\n\t\tsc->link_params.eee_mode = 0;\n\t}\n\n\t/* get the media type */\n\tbnx2x_media_detect(sc);\n}\n\nstatic void bnx2x_set_modes_bitmap(struct bnx2x_softc *sc)\n{\n\tuint32_t flags = MODE_ASIC | MODE_PORT2;\n\n\tif (CHIP_IS_E2(sc)) {\n\t\tflags |= MODE_E2;\n\t} else if (CHIP_IS_E3(sc)) {\n\t\tflags |= MODE_E3;\n\t\tif (CHIP_REV(sc) == CHIP_REV_Ax) {\n\t\t\tflags |= MODE_E3_A0;\n\t\t} else {\t/*if (CHIP_REV(sc) == CHIP_REV_Bx) */\n\n\t\t\tflags |= MODE_E3_B0 | MODE_COS3;\n\t\t}\n\t}\n\n\tif (IS_MF(sc)) {\n\t\tflags |= MODE_MF;\n\t\tswitch (sc->devinfo.mf_info.mf_mode) {\n\t\tcase MULTI_FUNCTION_SD:\n\t\t\tflags |= MODE_MF_SD;\n\t\t\tbreak;\n\t\tcase MULTI_FUNCTION_SI:\n\t\t\tflags |= MODE_MF_SI;\n\t\t\tbreak;\n\t\tcase MULTI_FUNCTION_AFEX:\n\t\t\tflags |= MODE_MF_AFEX;\n\t\t\tbreak;\n\t\t}\n\t} else {\n\t\tflags |= MODE_SF;\n\t}\n\n#if defined(__LITTLE_ENDIAN)\n\tflags |= MODE_LITTLE_ENDIAN;\n#else /* __BIG_ENDIAN */\n\tflags |= MODE_BIG_ENDIAN;\n#endif\n\n\tINIT_MODE_FLAGS(sc) = flags;\n}\n\nint bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_fastpath *fp;\n\tchar buf[32];\n\tuint32_t i;\n\n\tif (IS_PF(sc)) {\n/************************/\n/* DEFAULT STATUS BLOCK */\n/************************/\n\n\t\tif (bnx2x_dma_alloc(sc, sizeof(struct host_sp_status_block),\n\t\t\t\t &sc->def_sb_dma, \"def_sb\",\n\t\t\t\t RTE_CACHE_LINE_SIZE) != 0) {\n\t\t\treturn -1;\n\t\t}\n\n\t\tsc->def_sb =\n\t\t (struct host_sp_status_block *)sc->def_sb_dma.vaddr;\n/***************/\n/* EVENT QUEUE */\n/***************/\n\n\t\tif (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,\n\t\t\t\t &sc->eq_dma, \"ev_queue\",\n\t\t\t\t RTE_CACHE_LINE_SIZE) != 0) {\n\t\t\tsc->def_sb = NULL;\n\t\t\treturn -1;\n\t\t}\n\n\t\tsc->eq = (union event_ring_elem *)sc->eq_dma.vaddr;\n\n/*************/\n/* SLOW PATH */\n/*************/\n\n\t\tif (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_slowpath),\n\t\t\t\t &sc->sp_dma, \"sp\",\n\t\t\t\t RTE_CACHE_LINE_SIZE) != 0) {\n\t\t\tsc->eq = NULL;\n\t\t\tsc->def_sb = NULL;\n\t\t\treturn -1;\n\t\t}\n\n\t\tsc->sp = (struct bnx2x_slowpath *)sc->sp_dma.vaddr;\n\n/*******************/\n/* SLOW PATH QUEUE */\n/*******************/\n\n\t\tif (bnx2x_dma_alloc(sc, BNX2X_PAGE_SIZE,\n\t\t\t\t &sc->spq_dma, \"sp_queue\",\n\t\t\t\t RTE_CACHE_LINE_SIZE) != 0) {\n\t\t\tsc->sp = NULL;\n\t\t\tsc->eq = NULL;\n\t\t\tsc->def_sb = NULL;\n\t\t\treturn -1;\n\t\t}\n\n\t\tsc->spq = (struct eth_spe *)sc->spq_dma.vaddr;\n\n/***************************/\n/* FW DECOMPRESSION BUFFER */\n/***************************/\n\n\t\tif (bnx2x_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,\n\t\t\t\t \"fw_dec_buf\", RTE_CACHE_LINE_SIZE) != 0) {\n\t\t\tsc->spq = NULL;\n\t\t\tsc->sp = NULL;\n\t\t\tsc->eq = NULL;\n\t\t\tsc->def_sb = NULL;\n\t\t\treturn -1;\n\t\t}\n\n\t\tsc->gz_buf = (void *)sc->gz_buf_dma.vaddr;\n\t}\n\n\t/*************/\n\t/* FASTPATHS */\n\t/*************/\n\n\t/* allocate DMA memory for each fastpath structure */\n\tfor (i = 0; i < sc->num_queues; i++) {\n\t\tfp = &sc->fp[i];\n\t\tfp->sc = sc;\n\t\tfp->index = i;\n\n/*******************/\n/* FP STATUS BLOCK */\n/*******************/\n\n\t\tsnprintf(buf, sizeof(buf), \"fp_%d_sb\", i);\n\t\tif (bnx2x_dma_alloc(sc, sizeof(union bnx2x_host_hc_status_block),\n\t\t\t\t &fp->sb_dma, buf, RTE_CACHE_LINE_SIZE) != 0) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"Failed to alloc %s\", buf);\n\t\t\treturn -1;\n\t\t} else {\n\t\t\tif (CHIP_IS_E2E3(sc)) {\n\t\t\t\tfp->status_block.e2_sb =\n\t\t\t\t (struct host_hc_status_block_e2 *)\n\t\t\t\t fp->sb_dma.vaddr;\n\t\t\t} else {\n\t\t\t\tfp->status_block.e1x_sb =\n\t\t\t\t (struct host_hc_status_block_e1x *)\n\t\t\t\t fp->sb_dma.vaddr;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nvoid bnx2x_free_hsi_mem(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_fastpath *fp;\n\tint i;\n\n\tfor (i = 0; i < sc->num_queues; i++) {\n\t\tfp = &sc->fp[i];\n\n/*******************/\n/* FP STATUS BLOCK */\n/*******************/\n\n\t\tmemset(&fp->status_block, 0, sizeof(fp->status_block));\n\t}\n\n\t/***************************/\n\t/* FW DECOMPRESSION BUFFER */\n\t/***************************/\n\n\tsc->gz_buf = NULL;\n\n\t/*******************/\n\t/* SLOW PATH QUEUE */\n\t/*******************/\n\n\tsc->spq = NULL;\n\n\t/*************/\n\t/* SLOW PATH */\n\t/*************/\n\n\tsc->sp = NULL;\n\n\t/***************/\n\t/* EVENT QUEUE */\n\t/***************/\n\n\tsc->eq = NULL;\n\n\t/************************/\n\t/* DEFAULT STATUS BLOCK */\n\t/************************/\n\n\tsc->def_sb = NULL;\n\n}\n\n/*\n* Previous driver DMAE transaction may have occurred when pre-boot stage\n* ended and boot began. This would invalidate the addresses of the\n* transaction, resulting in was-error bit set in the PCI causing all\n* hw-to-host PCIe transactions to timeout. If this happened we want to clear\n* the interrupt which detected this from the pglueb and the was-done bit\n*/\nstatic void bnx2x_prev_interrupted_dmae(struct bnx2x_softc *sc)\n{\n\tuint32_t val;\n\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tval = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);\n\t\tif (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {\n\t\t\tREG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,\n\t\t\t 1 << SC_FUNC(sc));\n\t\t}\n\t}\n}\n\nstatic int bnx2x_prev_mcp_done(struct bnx2x_softc *sc)\n{\n\tuint32_t rc = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,\n\t\t\t\t DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);\n\tif (!rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"MCP response failure, aborting\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic struct bnx2x_prev_list_node *bnx2x_prev_path_get_entry(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_prev_list_node *tmp;\n\n\tLIST_FOREACH(tmp, &bnx2x_prev_list, node) {\n\t\tif ((sc->pcie_bus == tmp->bus) &&\n\t\t (sc->pcie_device == tmp->slot) &&\n\t\t (SC_PATH(sc) == tmp->path)) {\n\t\t\treturn tmp;\n\t\t}\n\t}\n\n\treturn NULL;\n}\n\nstatic uint8_t bnx2x_prev_is_path_marked(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_prev_list_node *tmp;\n\tint rc = FALSE;\n\n\trte_spinlock_lock(&bnx2x_prev_mtx);\n\n\ttmp = bnx2x_prev_path_get_entry(sc);\n\tif (tmp) {\n\t\tif (tmp->aer) {\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"Path %d/%d/%d was marked by AER\",\n\t\t\t\t sc->pcie_bus, sc->pcie_device, SC_PATH(sc));\n\t\t} else {\n\t\t\trc = TRUE;\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"Path %d/%d/%d was already cleaned from previous drivers\",\n\t\t\t\t sc->pcie_bus, sc->pcie_device, SC_PATH(sc));\n\t\t}\n\t}\n\n\trte_spinlock_unlock(&bnx2x_prev_mtx);\n\n\treturn rc;\n}\n\nstatic int bnx2x_prev_mark_path(struct bnx2x_softc *sc, uint8_t after_undi)\n{\n\tstruct bnx2x_prev_list_node *tmp;\n\n\trte_spinlock_lock(&bnx2x_prev_mtx);\n\n\t/* Check whether the entry for this path already exists */\n\ttmp = bnx2x_prev_path_get_entry(sc);\n\tif (tmp) {\n\t\tif (!tmp->aer) {\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"Re-marking AER in path %d/%d/%d\",\n\t\t\t\t sc->pcie_bus, sc->pcie_device, SC_PATH(sc));\n\t\t} else {\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"Removing AER indication from path %d/%d/%d\",\n\t\t\t\t sc->pcie_bus, sc->pcie_device, SC_PATH(sc));\n\t\t\ttmp->aer = 0;\n\t\t}\n\n\t\trte_spinlock_unlock(&bnx2x_prev_mtx);\n\t\treturn 0;\n\t}\n\n\trte_spinlock_unlock(&bnx2x_prev_mtx);\n\n\t/* Create an entry for this path and add it */\n\ttmp = rte_malloc(\"\", sizeof(struct bnx2x_prev_list_node),\n\t\t\t RTE_CACHE_LINE_SIZE);\n\tif (!tmp) {\n\t\tPMD_DRV_LOG(NOTICE, \"Failed to allocate 'bnx2x_prev_list_node'\");\n\t\treturn -1;\n\t}\n\n\ttmp->bus = sc->pcie_bus;\n\ttmp->slot = sc->pcie_device;\n\ttmp->path = SC_PATH(sc);\n\ttmp->aer = 0;\n\ttmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;\n\n\trte_spinlock_lock(&bnx2x_prev_mtx);\n\n\tLIST_INSERT_HEAD(&bnx2x_prev_list, tmp, node);\n\n\trte_spinlock_unlock(&bnx2x_prev_mtx);\n\n\treturn 0;\n}\n\nstatic int bnx2x_do_flr(struct bnx2x_softc *sc)\n{\n\tint i;\n\n\t/* only E2 and onwards support FLR */\n\tif (CHIP_IS_E1x(sc)) {\n\t\tPMD_DRV_LOG(WARNING, \"FLR not supported in E1H\");\n\t\treturn -1;\n\t}\n\n\t/* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */\n\tif (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {\n\t\tPMD_DRV_LOG(WARNING,\n\t\t\t \"FLR not supported by BC_VER: 0x%08x\",\n\t\t\t sc->devinfo.bc_ver);\n\t\treturn -1;\n\t}\n\n\t/* Wait for Transaction Pending bit clean */\n\tfor (i = 0; i < 4; i++) {\n\t\tif (i) {\n\t\t\tDELAY(((1 << (i - 1)) * 100) * 1000);\n\t\t}\n\n\t\tif (!bnx2x_is_pcie_pending(sc)) {\n\t\t\tgoto clear;\n\t\t}\n\t}\n\n\tPMD_DRV_LOG(NOTICE, \"PCIE transaction is not cleared, \"\n\t\t \"proceeding with reset anyway\");\n\nclear:\n\tbnx2x_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);\n\n\treturn 0;\n}\n\nstruct bnx2x_mac_vals {\n\tuint32_t xmac_addr;\n\tuint32_t xmac_val;\n\tuint32_t emac_addr;\n\tuint32_t emac_val;\n\tuint32_t umac_addr;\n\tuint32_t umac_val;\n\tuint32_t bmac_addr;\n\tuint32_t bmac_val[2];\n};\n\nstatic void\nbnx2x_prev_unload_close_mac(struct bnx2x_softc *sc, struct bnx2x_mac_vals *vals)\n{\n\tuint32_t val, base_addr, offset, mask, reset_reg;\n\tuint8_t mac_stopped = FALSE;\n\tuint8_t port = SC_PORT(sc);\n\tuint32_t wb_data[2];\n\n\t/* reset addresses as they also mark which values were changed */\n\tvals->bmac_addr = 0;\n\tvals->umac_addr = 0;\n\tvals->xmac_addr = 0;\n\tvals->emac_addr = 0;\n\n\treset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);\n\n\tif (!CHIP_IS_E3(sc)) {\n\t\tval = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);\n\t\tmask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;\n\t\tif ((mask & reset_reg) && val) {\n\t\t\tbase_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM\n\t\t\t : NIG_REG_INGRESS_BMAC0_MEM;\n\t\t\toffset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL\n\t\t\t : BIGMAC_REGISTER_BMAC_CONTROL;\n\n\t\t\t/*\n\t\t\t * use rd/wr since we cannot use dmae. This is safe\n\t\t\t * since MCP won't access the bus due to the request\n\t\t\t * to unload, and no function on the path can be\n\t\t\t * loaded at this time.\n\t\t\t */\n\t\t\twb_data[0] = REG_RD(sc, base_addr + offset);\n\t\t\twb_data[1] = REG_RD(sc, base_addr + offset + 0x4);\n\t\t\tvals->bmac_addr = base_addr + offset;\n\t\t\tvals->bmac_val[0] = wb_data[0];\n\t\t\tvals->bmac_val[1] = wb_data[1];\n\t\t\twb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;\n\t\t\tREG_WR(sc, vals->bmac_addr, wb_data[0]);\n\t\t\tREG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);\n\t\t}\n\n\t\tvals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc) * 4;\n\t\tvals->emac_val = REG_RD(sc, vals->emac_addr);\n\t\tREG_WR(sc, vals->emac_addr, 0);\n\t\tmac_stopped = TRUE;\n\t} else {\n\t\tif (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {\n\t\t\tbase_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;\n\t\t\tval = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);\n\t\t\tREG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,\n\t\t\t val & ~(1 << 1));\n\t\t\tREG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI,\n\t\t\t val | (1 << 1));\n\t\t\tvals->xmac_addr = base_addr + XMAC_REG_CTRL;\n\t\t\tvals->xmac_val = REG_RD(sc, vals->xmac_addr);\n\t\t\tREG_WR(sc, vals->xmac_addr, 0);\n\t\t\tmac_stopped = TRUE;\n\t\t}\n\n\t\tmask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;\n\t\tif (mask & reset_reg) {\n\t\t\tbase_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;\n\t\t\tvals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;\n\t\t\tvals->umac_val = REG_RD(sc, vals->umac_addr);\n\t\t\tREG_WR(sc, vals->umac_addr, 0);\n\t\t\tmac_stopped = TRUE;\n\t\t}\n\t}\n\n\tif (mac_stopped) {\n\t\tDELAY(20000);\n\t}\n}\n\n#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))\n#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)\n#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)\n#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))\n\nstatic void\nbnx2x_prev_unload_undi_inc(struct bnx2x_softc *sc, uint8_t port, uint8_t inc)\n{\n\tuint16_t rcq, bd;\n\tuint32_t tmp_reg = REG_RD(sc, BNX2X_PREV_UNDI_PROD_ADDR(port));\n\n\trcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;\n\tbd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;\n\n\ttmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);\n\tREG_WR(sc, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);\n}\n\nstatic int bnx2x_prev_unload_common(struct bnx2x_softc *sc)\n{\n\tuint32_t reset_reg, tmp_reg = 0, rc;\n\tuint8_t prev_undi = FALSE;\n\tstruct bnx2x_mac_vals mac_vals;\n\tuint32_t timer_count = 1000;\n\tuint32_t prev_brb;\n\n\t/*\n\t * It is possible a previous function received 'common' answer,\n\t * but hasn't loaded yet, therefore creating a scenario of\n\t * multiple functions receiving 'common' on the same path.\n\t */\n\tmemset(&mac_vals, 0, sizeof(mac_vals));\n\n\tif (bnx2x_prev_is_path_marked(sc)) {\n\t\treturn bnx2x_prev_mcp_done(sc);\n\t}\n\n\treset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);\n\n\t/* Reset should be performed after BRB is emptied */\n\tif (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {\n\t\t/* Close the MAC Rx to prevent BRB from filling up */\n\t\tbnx2x_prev_unload_close_mac(sc, &mac_vals);\n\n\t\t/* close LLH filters towards the BRB */\n\t\telink_set_rx_filter(&sc->link_params, 0);\n\n\t\t/*\n\t\t * Check if the UNDI driver was previously loaded.\n\t\t * UNDI driver initializes CID offset for normal bell to 0x7\n\t\t */\n\t\tif (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {\n\t\t\ttmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);\n\t\t\tif (tmp_reg == 0x7) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"UNDI previously loaded\");\n\t\t\t\tprev_undi = TRUE;\n\t\t\t\t/* clear the UNDI indication */\n\t\t\t\tREG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);\n\t\t\t\t/* clear possible idle check errors */\n\t\t\t\tREG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);\n\t\t\t}\n\t\t}\n\n\t\t/* wait until BRB is empty */\n\t\ttmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);\n\t\twhile (timer_count) {\n\t\t\tprev_brb = tmp_reg;\n\n\t\t\ttmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);\n\t\t\tif (!tmp_reg) {\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tPMD_DRV_LOG(DEBUG, \"BRB still has 0x%08x\", tmp_reg);\n\n\t\t\t/* reset timer as long as BRB actually gets emptied */\n\t\t\tif (prev_brb > tmp_reg) {\n\t\t\t\ttimer_count = 1000;\n\t\t\t} else {\n\t\t\t\ttimer_count--;\n\t\t\t}\n\n\t\t\t/* If UNDI resides in memory, manually increment it */\n\t\t\tif (prev_undi) {\n\t\t\t\tbnx2x_prev_unload_undi_inc(sc, SC_PORT(sc), 1);\n\t\t\t}\n\n\t\t\tDELAY(10);\n\t\t}\n\n\t\tif (!timer_count) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"Failed to empty BRB\");\n\t\t}\n\t}\n\n\t/* No packets are in the pipeline, path is ready for reset */\n\tbnx2x_reset_common(sc);\n\n\tif (mac_vals.xmac_addr) {\n\t\tREG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);\n\t}\n\tif (mac_vals.umac_addr) {\n\t\tREG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);\n\t}\n\tif (mac_vals.emac_addr) {\n\t\tREG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);\n\t}\n\tif (mac_vals.bmac_addr) {\n\t\tREG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);\n\t\tREG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);\n\t}\n\n\trc = bnx2x_prev_mark_path(sc, prev_undi);\n\tif (rc) {\n\t\tbnx2x_prev_mcp_done(sc);\n\t\treturn rc;\n\t}\n\n\treturn bnx2x_prev_mcp_done(sc);\n}\n\nstatic int bnx2x_prev_unload_uncommon(struct bnx2x_softc *sc)\n{\n\tint rc;\n\n\t/* Test if previous unload process was already finished for this path */\n\tif (bnx2x_prev_is_path_marked(sc)) {\n\t\treturn bnx2x_prev_mcp_done(sc);\n\t}\n\n\t/*\n\t * If function has FLR capabilities, and existing FW version matches\n\t * the one required, then FLR will be sufficient to clean any residue\n\t * left by previous driver\n\t */\n\trc = bnx2x_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);\n\tif (!rc) {\n\t\t/* fw version is good */\n\t\trc = bnx2x_do_flr(sc);\n\t}\n\n\tif (!rc) {\n\t\t/* FLR was performed */\n\t\treturn 0;\n\t}\n\n\tPMD_DRV_LOG(INFO, \"Could not FLR\");\n\n\t/* Close the MCP request, return failure */\n\trc = bnx2x_prev_mcp_done(sc);\n\tif (!rc) {\n\t\trc = BNX2X_PREV_WAIT_NEEDED;\n\t}\n\n\treturn rc;\n}\n\nstatic int bnx2x_prev_unload(struct bnx2x_softc *sc)\n{\n\tint time_counter = 10;\n\tuint32_t fw, hw_lock_reg, hw_lock_val;\n\tuint32_t rc = 0;\n\n\t/*\n\t * Clear HW from errors which may have resulted from an interrupted\n\t * DMAE transaction.\n\t */\n\tbnx2x_prev_interrupted_dmae(sc);\n\n\t/* Release previously held locks */\n\tif (SC_FUNC(sc) <= 5)\n\t\thw_lock_reg = (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8);\n\telse\n\t\thw_lock_reg =\n\t\t (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);\n\n\thw_lock_val = (REG_RD(sc, hw_lock_reg));\n\tif (hw_lock_val) {\n\t\tif (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {\n\t\t\tREG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,\n\t\t\t (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));\n\t\t}\n\t\tREG_WR(sc, hw_lock_reg, 0xffffffff);\n\t}\n\n\tif (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {\n\t\tREG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);\n\t}\n\n\tdo {\n\t\t/* Lock MCP using an unload request */\n\t\tfw = bnx2x_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);\n\t\tif (!fw) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"MCP response failure, aborting\");\n\t\t\trc = -1;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {\n\t\t\trc = bnx2x_prev_unload_common(sc);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* non-common reply from MCP might require looping */\n\t\trc = bnx2x_prev_unload_uncommon(sc);\n\t\tif (rc != BNX2X_PREV_WAIT_NEEDED) {\n\t\t\tbreak;\n\t\t}\n\n\t\tDELAY(20000);\n\t} while (--time_counter);\n\n\tif (!time_counter || rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"Failed to unload previous driver!\");\n\t\trc = -1;\n\t}\n\n\treturn rc;\n}\n\nstatic void\nbnx2x_dcbx_set_state(struct bnx2x_softc *sc, uint8_t dcb_on, uint32_t dcbx_enabled)\n{\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tsc->dcb_state = dcb_on;\n\t\tsc->dcbx_enabled = dcbx_enabled;\n\t} else {\n\t\tsc->dcb_state = FALSE;\n\t\tsc->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;\n\t}\n\tPMD_DRV_LOG(DEBUG,\n\t\t \"DCB state [%s:%s]\",\n\t\t dcb_on ? \"ON\" : \"OFF\",\n\t\t (dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ? \"user-mode\" :\n\t\t (dcbx_enabled ==\n\t\t BNX2X_DCBX_ENABLED_ON_NEG_OFF) ? \"on-chip static\"\n\t\t : (dcbx_enabled ==\n\t\t BNX2X_DCBX_ENABLED_ON_NEG_ON) ?\n\t\t \"on-chip with negotiation\" : \"invalid\");\n}\n\nstatic int bnx2x_set_qm_cid_count(struct bnx2x_softc *sc)\n{\n\tint cid_count = BNX2X_L2_MAX_CID(sc);\n\n\tif (CNIC_SUPPORT(sc)) {\n\t\tcid_count += CNIC_CID_MAX;\n\t}\n\n\treturn roundup(cid_count, QM_CID_ROUND);\n}\n\nstatic void bnx2x_init_multi_cos(struct bnx2x_softc *sc)\n{\n\tint pri, cos;\n\n\tuint32_t pri_map = 0;\n\n\tfor (pri = 0; pri < BNX2X_MAX_PRIORITY; pri++) {\n\t\tcos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));\n\t\tif (cos < sc->max_cos) {\n\t\t\tsc->prio_to_cos[pri] = cos;\n\t\t} else {\n\t\t\tPMD_DRV_LOG(WARNING,\n\t\t\t\t \"Invalid COS %d for priority %d \"\n\t\t\t\t \"(max COS is %d), setting to 0\", cos, pri,\n\t\t\t\t (sc->max_cos - 1));\n\t\t\tsc->prio_to_cos[pri] = 0;\n\t\t}\n\t}\n}\n\nstatic int bnx2x_pci_get_caps(struct bnx2x_softc *sc)\n{\n\tstruct {\n\t\tuint8_t id;\n\t\tuint8_t next;\n\t} pci_cap;\n\tuint16_t status;\n\tstruct bnx2x_pci_cap *cap;\n\n\tcap = sc->pci_caps = rte_zmalloc(\"caps\", sizeof(struct bnx2x_pci_cap),\n\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n\tif (!cap) {\n\t\tPMD_DRV_LOG(NOTICE, \"Failed to allocate memory\");\n\t\treturn -ENOMEM;\n\t}\n\n\tpci_read(sc, PCI_STATUS, &status, 2);\n\tif (!(status & PCI_STATUS_CAP_LIST)) {\n\t\tPMD_DRV_LOG(NOTICE, \"PCIe capability reading failed\");\n\t\treturn -1;\n\t}\n\n\tpci_read(sc, PCI_CAPABILITY_LIST, &pci_cap.next, 1);\n\twhile (pci_cap.next) {\n\t\tcap->addr = pci_cap.next & ~3;\n\t\tpci_read(sc, pci_cap.next & ~3, &pci_cap, 2);\n\t\tif (pci_cap.id == 0xff)\n\t\t\tbreak;\n\t\tcap->id = pci_cap.id;\n\t\tcap->type = BNX2X_PCI_CAP;\n\t\tcap->next = rte_zmalloc(\"pci_cap\",\n\t\t\t\t\tsizeof(struct bnx2x_pci_cap),\n\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n\t\tif (!cap->next) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"Failed to allocate memory\");\n\t\t\treturn -ENOMEM;\n\t\t}\n\t\tcap = cap->next;\n\t}\n\n\treturn 0;\n}\n\nstatic void bnx2x_init_rte(struct bnx2x_softc *sc)\n{\n\tsc->max_tx_queues = 128;\n\tsc->max_rx_queues = 128;\n}\n\n#define FW_HEADER_LEN 104\n#define FW_NAME_57711 \"/lib/firmware/bnx2x/bnx2x-e1h-7.2.51.0.fw\"\n#define FW_NAME_57810 \"/lib/firmware/bnx2x/bnx2x-e2-7.2.51.0.fw\"\n\nvoid bnx2x_load_firmware(struct bnx2x_softc *sc)\n{\n\tconst char *fwname;\n\tint f;\n\tstruct stat st;\n\n\tfwname = sc->devinfo.device_id == BNX2X_DEV_ID_57711\n\t\t? FW_NAME_57711 : FW_NAME_57810;\n\tf = open(fwname, O_RDONLY);\n\tif (f < 0) {\n\t\tPMD_DRV_LOG(NOTICE, \"Can't open firmware file\");\n\t\treturn;\n\t}\n\n\tif (fstat(f, &st) < 0) {\n\t\tPMD_DRV_LOG(NOTICE, \"Can't stat firmware file\");\n\t\tclose(f);\n\t\treturn;\n\t}\n\n\tsc->firmware = rte_zmalloc(\"bnx2x_fw\", st.st_size, RTE_CACHE_LINE_SIZE);\n\tif (!sc->firmware) {\n\t\tPMD_DRV_LOG(NOTICE, \"Can't allocate memory for firmware\");\n\t\tclose(f);\n\t\treturn;\n\t}\n\n\tif (read(f, sc->firmware, st.st_size) != st.st_size) {\n\t\tPMD_DRV_LOG(NOTICE, \"Can't read firmware data\");\n\t\tclose(f);\n\t\treturn;\n\t}\n\tclose(f);\n\n\tsc->fw_len = st.st_size;\n\tif (sc->fw_len < FW_HEADER_LEN) {\n\t\tPMD_DRV_LOG(NOTICE, \"Invalid fw size: %\" PRIu64, sc->fw_len);\n\t\treturn;\n\t}\n\tPMD_DRV_LOG(DEBUG, \"fw_len = %\" PRIu64, sc->fw_len);\n}\n\nstatic void\nbnx2x_data_to_init_ops(uint8_t * data, struct raw_op *dst, uint32_t len)\n{\n\tuint32_t *src = (uint32_t *) data;\n\tuint32_t i, j, tmp;\n\n\tfor (i = 0, j = 0; i < len / 8; ++i, j += 2) {\n\t\ttmp = rte_be_to_cpu_32(src[j]);\n\t\tdst[i].op = (tmp >> 24) & 0xFF;\n\t\tdst[i].offset = tmp & 0xFFFFFF;\n\t\tdst[i].raw_data = rte_be_to_cpu_32(src[j + 1]);\n\t}\n}\n\nstatic void\nbnx2x_data_to_init_offsets(uint8_t * data, uint16_t * dst, uint32_t len)\n{\n\tuint16_t *src = (uint16_t *) data;\n\tuint32_t i;\n\n\tfor (i = 0; i < len / 2; ++i)\n\t\tdst[i] = rte_be_to_cpu_16(src[i]);\n}\n\nstatic void bnx2x_data_to_init_data(uint8_t * data, uint32_t * dst, uint32_t len)\n{\n\tuint32_t *src = (uint32_t *) data;\n\tuint32_t i;\n\n\tfor (i = 0; i < len / 4; ++i)\n\t\tdst[i] = rte_be_to_cpu_32(src[i]);\n}\n\nstatic void bnx2x_data_to_iro_array(uint8_t * data, struct iro *dst, uint32_t len)\n{\n\tuint32_t *src = (uint32_t *) data;\n\tuint32_t i, j, tmp;\n\n\tfor (i = 0, j = 0; i < len / sizeof(struct iro); ++i, ++j) {\n\t\tdst[i].base = rte_be_to_cpu_32(src[j++]);\n\t\ttmp = rte_be_to_cpu_32(src[j]);\n\t\tdst[i].m1 = (tmp >> 16) & 0xFFFF;\n\t\tdst[i].m2 = tmp & 0xFFFF;\n\t\t++j;\n\t\ttmp = rte_be_to_cpu_32(src[j]);\n\t\tdst[i].m3 = (tmp >> 16) & 0xFFFF;\n\t\tdst[i].size = tmp & 0xFFFF;\n\t}\n}\n\n/*\n* Device attach function.\n*\n* Allocates device resources, performs secondary chip identification, and\n* initializes driver instance variables. This function is called from driver\n* load after a successful probe.\n*\n* Returns:\n* 0 = Success, >0 = Failure\n*/\nint bnx2x_attach(struct bnx2x_softc *sc)\n{\n\tint rc;\n\n\tPMD_DRV_LOG(DEBUG, \"Starting attach...\");\n\n\trc = bnx2x_pci_get_caps(sc);\n\tif (rc) {\n\t\tPMD_DRV_LOG(NOTICE, \"PCIe caps reading was failed\");\n\t\treturn rc;\n\t}\n\n\tsc->state = BNX2X_STATE_CLOSED;\n\n\t/* Init RTE stuff */\n\tbnx2x_init_rte(sc);\n\n\tpci_write_long(sc, PCICFG_GRC_ADDRESS, PCICFG_VENDOR_ID_OFFSET);\n\n\tsc->igu_base_addr = IS_VF(sc) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;\n\n\t/* get PCI capabilites */\n\tbnx2x_probe_pci_caps(sc);\n\n\tif (sc->devinfo.pcie_msix_cap_reg != 0) {\n\t\tuint32_t val;\n\t\tpci_read(sc,\n\t\t\t (sc->devinfo.pcie_msix_cap_reg + PCIR_MSIX_CTRL), &val,\n\t\t\t 2);\n\t\tsc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);\n\t} else {\n\t\tsc->igu_sb_cnt = 1;\n\t}\n\n\tif (IS_PF(sc)) {\n/* get device info and set params */\n\t\tif (bnx2x_get_device_info(sc) != 0) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"getting device info\");\n\t\t\treturn -ENXIO;\n\t\t}\n\n/* get phy settings from shmem and 'and' against admin settings */\n\t\tbnx2x_get_phy_info(sc);\n\t} else {\n/* Left mac of VF unfilled, PF should set it for VF */\n\t\tmemset(sc->link_params.mac_addr, 0, ETHER_ADDR_LEN);\n\t}\n\n\tsc->wol = 0;\n\n\t/* set the default MTU (changed via ifconfig) */\n\tsc->mtu = ETHER_MTU;\n\n\tbnx2x_set_modes_bitmap(sc);\n\n\t/* need to reset chip if UNDI was active */\n\tif (IS_PF(sc) && !BNX2X_NOMCP(sc)) {\n/* init fw_seq */\n\t\tsc->fw_seq =\n\t\t (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &\n\t\t DRV_MSG_SEQ_NUMBER_MASK);\n\t\tbnx2x_prev_unload(sc);\n\t}\n\n\tbnx2x_dcbx_set_state(sc, FALSE, BNX2X_DCBX_ENABLED_OFF);\n\n\t/* calculate qm_cid_count */\n\tsc->qm_cid_count = bnx2x_set_qm_cid_count(sc);\n\n\tsc->max_cos = 1;\n\tbnx2x_init_multi_cos(sc);\n\n\treturn 0;\n}\n\nstatic void\nbnx2x_igu_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t segment,\n\t uint16_t index, uint8_t op, uint8_t update)\n{\n\tuint32_t igu_addr = sc->igu_base_addr;\n\tigu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;\n\tbnx2x_igu_ack_sb_gen(sc, segment, index, op, update, igu_addr);\n}\n\nstatic void\nbnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id, uint8_t storm,\n\t uint16_t index, uint8_t op, uint8_t update)\n{\n\tif (unlikely(sc->devinfo.int_block == INT_BLOCK_HC))\n\t\tbnx2x_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);\n\telse {\n\t\tuint8_t segment;\n\t\tif (CHIP_INT_MODE_IS_BC(sc)) {\n\t\t\tsegment = storm;\n\t\t} else if (igu_sb_id != sc->igu_dsb_id) {\n\t\t\tsegment = IGU_SEG_ACCESS_DEF;\n\t\t} else if (storm == ATTENTION_ID) {\n\t\t\tsegment = IGU_SEG_ACCESS_ATTN;\n\t\t} else {\n\t\t\tsegment = IGU_SEG_ACCESS_DEF;\n\t\t}\n\t\tbnx2x_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);\n\t}\n}\n\nstatic void\nbnx2x_igu_clear_sb_gen(struct bnx2x_softc *sc, uint8_t func, uint8_t idu_sb_id,\n\t\t uint8_t is_pf)\n{\n\tuint32_t data, ctl, cnt = 100;\n\tuint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;\n\tuint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;\n\tuint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP +\n\t (idu_sb_id / 32) * 4;\n\tuint32_t sb_bit = 1 << (idu_sb_id % 32);\n\tuint32_t func_encode = func |\n\t (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;\n\tuint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;\n\n\t/* Not supported in BC mode */\n\tif (CHIP_INT_MODE_IS_BC(sc)) {\n\t\treturn;\n\t}\n\n\tdata = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<\n\t\t IGU_REGULAR_CLEANUP_TYPE_SHIFT) |\n\t\tIGU_REGULAR_CLEANUP_SET | IGU_REGULAR_BCLEANUP);\n\n\tctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |\n\t (func_encode << IGU_CTRL_REG_FID_SHIFT) |\n\t (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));\n\n\tREG_WR(sc, igu_addr_data, data);\n\n\tmb();\n\n\tPMD_DRV_LOG(DEBUG, \"write 0x%08x to IGU(via GRC) addr 0x%x\",\n\t\t ctl, igu_addr_ctl);\n\tREG_WR(sc, igu_addr_ctl, ctl);\n\n\tmb();\n\n\t/* wait for clean up to finish */\n\twhile (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {\n\t\tDELAY(20000);\n\t}\n\n\tif (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t \"Unable to finish IGU cleanup: \"\n\t\t\t \"idu_sb_id %d offset %d bit %d (cnt %d)\",\n\t\t\t idu_sb_id, idu_sb_id / 32, idu_sb_id % 32, cnt);\n\t}\n}\n\nstatic void bnx2x_igu_clear_sb(struct bnx2x_softc *sc, uint8_t idu_sb_id)\n{\n\tbnx2x_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);\n}\n\n/*******************/\n/* ECORE CALLBACKS */\n/*******************/\n\nstatic void bnx2x_reset_common(struct bnx2x_softc *sc)\n{\n\tuint32_t val = 0x1400;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* reset_common */\n\tREG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR),\n\t 0xd3ffff7f);\n\n\tif (CHIP_IS_E3(sc)) {\n\t\tval |= MISC_REGISTERS_RESET_REG_2_MSTAT0;\n\t\tval |= MISC_REGISTERS_RESET_REG_2_MSTAT1;\n\t}\n\n\tREG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);\n}\n\nstatic void bnx2x_common_init_phy(struct bnx2x_softc *sc)\n{\n\tuint32_t shmem_base[2];\n\tuint32_t shmem2_base[2];\n\n\t/* Avoid common init in case MFW supports LFA */\n\tif (SHMEM2_RD(sc, size) >\n\t (uint32_t) offsetof(struct shmem2_region,\n\t\t\t\tlfa_host_addr[SC_PORT(sc)])) {\n\t\treturn;\n\t}\n\n\tshmem_base[0] = sc->devinfo.shmem_base;\n\tshmem2_base[0] = sc->devinfo.shmem2_base;\n\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tshmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);\n\t\tshmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);\n\t}\n\n\telink_common_init_phy(sc, shmem_base, shmem2_base,\n\t\t\t sc->devinfo.chip_id, 0);\n}\n\nstatic void bnx2x_pf_disable(struct bnx2x_softc *sc)\n{\n\tuint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);\n\n\tval &= ~IGU_PF_CONF_FUNC_EN;\n\n\tREG_WR(sc, IGU_REG_PF_CONFIGURATION, val);\n\tREG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);\n\tREG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);\n}\n\nstatic void bnx2x_init_pxp(struct bnx2x_softc *sc)\n{\n\tuint16_t devctl;\n\tint r_order, w_order;\n\n\tdevctl = bnx2x_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL);\n\n\tw_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);\n\tr_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);\n\n\tecore_init_pxp_arb(sc, r_order, w_order);\n}\n\nstatic uint32_t bnx2x_get_pretend_reg(struct bnx2x_softc *sc)\n{\n\tuint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;\n\tuint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);\n\treturn (base + (SC_ABS_FUNC(sc)) * stride);\n}\n\n/*\n * Called only on E1H or E2.\n * When pretending to be PF, the pretend value is the function number 0..7.\n * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID\n * combination.\n */\nstatic int bnx2x_pretend_func(struct bnx2x_softc *sc, uint16_t pretend_func_val)\n{\n\tuint32_t pretend_reg;\n\n\tif (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX))\n\t\treturn -1;\n\n\t/* get my own pretend register */\n\tpretend_reg = bnx2x_get_pretend_reg(sc);\n\tREG_WR(sc, pretend_reg, pretend_func_val);\n\tREG_RD(sc, pretend_reg);\n\treturn 0;\n}\n\nstatic void bnx2x_setup_fan_failure_detection(struct bnx2x_softc *sc)\n{\n\tint is_required;\n\tuint32_t val;\n\tint port;\n\n\tis_required = 0;\n\tval = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &\n\t SHARED_HW_CFG_FAN_FAILURE_MASK);\n\n\tif (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {\n\t\tis_required = 1;\n\t}\n\t/*\n\t * The fan failure mechanism is usually related to the PHY type since\n\t * the power consumption of the board is affected by the PHY. Currently,\n\t * fan is required for most designs with SFX7101, BNX2X8727 and BNX2X8481.\n\t */\n\telse if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {\n\t\tfor (port = PORT_0; port < PORT_MAX; port++) {\n\t\t\tis_required |= elink_fan_failure_det_req(sc,\n\t\t\t\t\t\t\t\t sc->\n\t\t\t\t\t\t\t\t devinfo.shmem_base,\n\t\t\t\t\t\t\t\t sc->\n\t\t\t\t\t\t\t\t devinfo.shmem2_base,\n\t\t\t\t\t\t\t\t port);\n\t\t}\n\t}\n\n\tif (is_required == 0) {\n\t\treturn;\n\t}\n\n\t/* Fan failure is indicated by SPIO 5 */\n\tbnx2x_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);\n\n\t/* set to active low mode */\n\tval = REG_RD(sc, MISC_REG_SPIO_INT);\n\tval |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);\n\tREG_WR(sc, MISC_REG_SPIO_INT, val);\n\n\t/* enable interrupt to signal the IGU */\n\tval = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);\n\tval |= MISC_SPIO_SPIO5;\n\tREG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);\n}\n\nstatic void bnx2x_enable_blocks_attention(struct bnx2x_softc *sc)\n{\n\tuint32_t val;\n\n\tREG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tREG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);\n\t} else {\n\t\tREG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);\n\t}\n\tREG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);\n\tREG_WR(sc, CFC_REG_CFC_INT_MASK, 0);\n\t/*\n\t * mask read length error interrupts in brb for parser\n\t * (parsing unit and 'checksum and crc' unit)\n\t * these errors are legal (PU reads fixed length and CAC can cause\n\t * read length error on truncated packets)\n\t */\n\tREG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);\n\tREG_WR(sc, QM_REG_QM_INT_MASK, 0);\n\tREG_WR(sc, TM_REG_TM_INT_MASK, 0);\n\tREG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);\n\tREG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);\n\tREG_WR(sc, XCM_REG_XCM_INT_MASK, 0);\n\t/* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */\n\t/* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */\n\tREG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);\n\tREG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);\n\tREG_WR(sc, UCM_REG_UCM_INT_MASK, 0);\n\t/* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */\n\t/* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */\n\tREG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);\n\tREG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);\n\tREG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);\n\tREG_WR(sc, CCM_REG_CCM_INT_MASK, 0);\n\t/* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */\n\t/* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */\n\n\tval = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |\n\t PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |\n\t PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tval |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |\n\t\t\tPXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);\n\t}\n\tREG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);\n\n\tREG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);\n\tREG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);\n\tREG_WR(sc, TCM_REG_TCM_INT_MASK, 0);\n\t/* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */\n\n\tif (!CHIP_IS_E1x(sc)) {\n/* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */\n\t\tREG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);\n\t}\n\n\tREG_WR(sc, CDU_REG_CDU_INT_MASK, 0);\n\tREG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);\n\t/* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */\n\tREG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18);\t/* bit 3,4 masked */\n}\n\n/**\n * bnx2x_init_hw_common - initialize the HW at the COMMON phase.\n *\n * @sc: driver handle\n */\nstatic int bnx2x_init_hw_common(struct bnx2x_softc *sc)\n{\n\tuint8_t abs_func_id;\n\tuint32_t val;\n\n\tPMD_DRV_LOG(DEBUG, \"starting common init for func %d\", SC_ABS_FUNC(sc));\n\n\t/*\n\t * take the RESET lock to protect undi_unload flow from accessing\n\t * registers while we are resetting the chip\n\t */\n\tbnx2x_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);\n\n\tbnx2x_reset_common(sc);\n\n\tREG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);\n\n\tval = 0xfffc;\n\tif (CHIP_IS_E3(sc)) {\n\t\tval |= MISC_REGISTERS_RESET_REG_2_MSTAT0;\n\t\tval |= MISC_REGISTERS_RESET_REG_2_MSTAT1;\n\t}\n\n\tREG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);\n\n\tbnx2x_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);\n\n\tecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);\n\n\tif (!CHIP_IS_E1x(sc)) {\n/*\n * 4-port mode or 2-port mode we need to turn off master-enable for\n * everyone. After that we turn it back on for self. So, we disregard\n * multi-function, and always disable all functions on the given path,\n * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1\n */\n\t\tfor (abs_func_id = SC_PATH(sc);\n\t\t abs_func_id < (E2_FUNC_MAX * 2); abs_func_id += 2) {\n\t\t\tif (abs_func_id == SC_ABS_FUNC(sc)) {\n\t\t\t\tREG_WR(sc,\n\t\t\t\t PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,\n\t\t\t\t 1);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tbnx2x_pretend_func(sc, abs_func_id);\n\n\t\t\t/* clear pf enable */\n\t\t\tbnx2x_pf_disable(sc);\n\n\t\t\tbnx2x_pretend_func(sc, SC_ABS_FUNC(sc));\n\t\t}\n\t}\n\n\tecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);\n\n\tecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);\n\tbnx2x_init_pxp(sc);\n\n#ifdef __BIG_ENDIAN\n\tREG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);\n\tREG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);\n\tREG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);\n\tREG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);\n\tREG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);\n\t/* make sure this value is 0 */\n\tREG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);\n\n\t//REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);\n\tREG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);\n\tREG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);\n\tREG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);\n\tREG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);\n#endif\n\n\tecore_ilt_init_page_size(sc, INITOP_SET);\n\n\tif (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {\n\t\tREG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);\n\t}\n\n\t/* let the HW do it's magic... */\n\tDELAY(100000);\n\n\t/* finish PXP init */\n\n\tval = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);\n\tif (val != 1) {\n\t\tPMD_DRV_LOG(NOTICE, \"PXP2 CFG failed\");\n\t\treturn -1;\n\t}\n\tval = REG_RD(sc, PXP2_REG_RD_INIT_DONE);\n\tif (val != 1) {\n\t\tPMD_DRV_LOG(NOTICE, \"PXP2 RD_INIT failed\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * Timer bug workaround for E2 only. We need to set the entire ILT to have\n\t * entries with value \"0\" and valid bit on. This needs to be done by the\n\t * first PF that is loaded in a path (i.e. common phase)\n\t */\n\tif (!CHIP_IS_E1x(sc)) {\n/*\n * In E2 there is a bug in the timers block that can cause function 6 / 7\n * (i.e. vnic3) to start even if it is marked as \"scan-off\".\n * This occurs when a different function (func2,3) is being marked\n * as \"scan-off\". Real-life scenario for example: if a driver is being\n * load-unloaded while func6,7 are down. This will cause the timer to access\n * the ilt, translate to a logical address and send a request to read/write.\n * Since the ilt for the function that is down is not valid, this will cause\n * a translation error which is unrecoverable.\n * The Workaround is intended to make sure that when this happens nothing\n * fatal will occur. The workaround:\n * 1. First PF driver which loads on a path will:\n * a. After taking the chip out of reset, by using pretend,\n * it will write \"0\" to the following registers of\n * the other vnics.\n * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);\n * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);\n * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);\n * And for itself it will write '1' to\n * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable\n * dmae-operations (writing to pram for example.)\n * note: can be done for only function 6,7 but cleaner this\n * way.\n * b. Write zero+valid to the entire ILT.\n * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of\n * VNIC3 (of that port). The range allocated will be the\n * entire ILT. This is needed to prevent ILT range error.\n * 2. Any PF driver load flow:\n * a. ILT update with the physical addresses of the allocated\n * logical pages.\n * b. Wait 20msec. - note that this timeout is needed to make\n * sure there are no requests in one of the PXP internal\n * queues with \"old\" ILT addresses.\n * c. PF enable in the PGLC.\n * d. Clear the was_error of the PF in the PGLC. (could have\n * occurred while driver was down)\n * e. PF enable in the CFC (WEAK + STRONG)\n * f. Timers scan enable\n * 3. PF driver unload flow:\n * a. Clear the Timers scan_en.\n * b. Polling for scan_on=0 for that PF.\n * c. Clear the PF enable bit in the PXP.\n * d. Clear the PF enable in the CFC (WEAK + STRONG)\n * e. Write zero+valid to all ILT entries (The valid bit must\n * stay set)\n * f. If this is VNIC 3 of a port then also init\n * first_timers_ilt_entry to zero and last_timers_ilt_entry\n * to the last enrty in the ILT.\n *\n * Notes:\n * Currently the PF error in the PGLC is non recoverable.\n * In the future the there will be a recovery routine for this error.\n * Currently attention is masked.\n * Having an MCP lock on the load/unload process does not guarantee that\n * there is no Timer disable during Func6/7 enable. This is because the\n * Timers scan is currently being cleared by the MCP on FLR.\n * Step 2.d can be done only for PF6/7 and the driver can also check if\n * there is error before clearing it. But the flow above is simpler and\n * more general.\n * All ILT entries are written by zero+valid and not just PF6/7\n * ILT entries since in the future the ILT entries allocation for\n * PF-s might be dynamic.\n */\n\t\tstruct ilt_client_info ilt_cli;\n\t\tstruct ecore_ilt ilt;\n\n\t\tmemset(&ilt_cli, 0, sizeof(struct ilt_client_info));\n\t\tmemset(&ilt, 0, sizeof(struct ecore_ilt));\n\n/* initialize dummy TM client */\n\t\tilt_cli.start = 0;\n\t\tilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;\n\t\tilt_cli.client_num = ILT_CLIENT_TM;\n\n/*\n * Step 1: set zeroes to all ilt page entries with valid bit on\n * Step 2: set the timers first/last ilt entry to point\n * to the entire range to prevent ILT range error for 3rd/4th\n * vnic (this code assumes existence of the vnic)\n *\n * both steps performed by call to ecore_ilt_client_init_op()\n * with dummy TM client\n *\n * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT\n * and his brother are split registers\n */\n\n\t\tbnx2x_pretend_func(sc, (SC_PATH(sc) + 6));\n\t\tecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);\n\t\tbnx2x_pretend_func(sc, SC_ABS_FUNC(sc));\n\n\t\tREG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);\n\t\tREG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);\n\t\tREG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);\n\t}\n\n\tREG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);\n\tREG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);\n\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tint factor = 0;\n\n\t\tecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);\n\t\tecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);\n\n/* let the HW do it's magic... */\n\t\tdo {\n\t\t\tDELAY(200000);\n\t\t\tval = REG_RD(sc, ATC_REG_ATC_INIT_DONE);\n\t\t} while (factor-- && (val != 1));\n\n\t\tif (val != 1) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"ATC_INIT failed\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);\n\n\t/* clean the DMAE memory */\n\tsc->dmae_ready = 1;\n\tecore_init_fill(sc, TSEM_REG_PRAM, 0, 8);\n\n\tecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);\n\n\tecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);\n\n\tecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);\n\n\tecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);\n\n\tbnx2x_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);\n\tbnx2x_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);\n\tbnx2x_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);\n\tbnx2x_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);\n\n\tecore_init_block(sc, BLOCK_QM, PHASE_COMMON);\n\n\t/* QM queues pointers table */\n\tecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);\n\n\t/* soft reset pulse */\n\tREG_WR(sc, QM_REG_SOFT_RESET, 1);\n\tREG_WR(sc, QM_REG_SOFT_RESET, 0);\n\n\tif (CNIC_SUPPORT(sc))\n\t\tecore_init_block(sc, BLOCK_TM, PHASE_COMMON);\n\n\tecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);\n\tREG_WR(sc, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);\n\n\tif (!CHIP_REV_IS_SLOW(sc)) {\n/* enable hw interrupt from doorbell Q */\n\t\tREG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);\n\t}\n\n\tecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);\n\n\tecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);\n\tREG_WR(sc, PRS_REG_A_PRSU_20, 0xf);\n\tREG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);\n\n\tif (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {\n\t\tif (IS_MF_AFEX(sc)) {\n\t\t\t/*\n\t\t\t * configure that AFEX and VLAN headers must be\n\t\t\t * received in AFEX mode\n\t\t\t */\n\t\t\tREG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);\n\t\t\tREG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);\n\t\t\tREG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);\n\t\t\tREG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);\n\t\t\tREG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);\n\t\t} else {\n\t\t\t/*\n\t\t\t * Bit-map indicating which L2 hdrs may appear\n\t\t\t * after the basic Ethernet header\n\t\t\t */\n\t\t\tREG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,\n\t\t\t sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);\n\t\t}\n\t}\n\n\tecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);\n\tecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);\n\tecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);\n\tecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);\n\n\tif (!CHIP_IS_E1x(sc)) {\n/* reset VFC memories */\n\t\tREG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,\n\t\t VFC_MEMORIES_RST_REG_CAM_RST |\n\t\t VFC_MEMORIES_RST_REG_RAM_RST);\n\t\tREG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,\n\t\t VFC_MEMORIES_RST_REG_CAM_RST |\n\t\t VFC_MEMORIES_RST_REG_RAM_RST);\n\n\t\tDELAY(20000);\n\t}\n\n\tecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);\n\tecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);\n\tecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);\n\tecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);\n\n\t/* sync semi rtc */\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);\n\n\tecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);\n\tecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);\n\tecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);\n\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tif (IS_MF_AFEX(sc)) {\n\t\t\t/*\n\t\t\t * configure that AFEX and VLAN headers must be\n\t\t\t * sent in AFEX mode\n\t\t\t */\n\t\t\tREG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);\n\t\t\tREG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);\n\t\t\tREG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);\n\t\t\tREG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);\n\t\t\tREG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);\n\t\t} else {\n\t\t\tREG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,\n\t\t\t sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);\n\t\t}\n\t}\n\n\tREG_WR(sc, SRC_REG_SOFT_RST, 1);\n\n\tecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);\n\n\tif (CNIC_SUPPORT(sc)) {\n\t\tREG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);\n\t\tREG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);\n\t\tREG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);\n\t\tREG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);\n\t\tREG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);\n\t\tREG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);\n\t\tREG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);\n\t\tREG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);\n\t\tREG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);\n\t\tREG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);\n\t}\n\tREG_WR(sc, SRC_REG_SOFT_RST, 0);\n\n\tif (sizeof(union cdu_context) != 1024) {\n/* we currently assume that a context is 1024 bytes */\n\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t \"please adjust the size of cdu_context(%ld)\",\n\t\t\t (long)sizeof(union cdu_context));\n\t}\n\n\tecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);\n\tval = (4 << 24) + (0 << 12) + 1024;\n\tREG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);\n\n\tecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);\n\n\tREG_WR(sc, CFC_REG_INIT_REG, 0x7FF);\n\t/* enable context validation interrupt from CFC */\n\tREG_WR(sc, CFC_REG_CFC_INT_MASK, 0);\n\n\t/* set the thresholds to prevent CFC/CDU race */\n\tREG_WR(sc, CFC_REG_DEBUG0, 0x20020000);\n\tecore_init_block(sc, BLOCK_HC, PHASE_COMMON);\n\n\tif (!CHIP_IS_E1x(sc) && BNX2X_NOMCP(sc)) {\n\t\tREG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);\n\t}\n\n\tecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);\n\tecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);\n\n\t/* Reset PCIE errors for debug */\n\tREG_WR(sc, 0x2814, 0xffffffff);\n\tREG_WR(sc, 0x3820, 0xffffffff);\n\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tREG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,\n\t\t (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |\n\t\t\tPXPCS_TL_CONTROL_5_ERR_UNSPPORT));\n\t\tREG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,\n\t\t (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |\n\t\t\tPXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |\n\t\t\tPXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));\n\t\tREG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,\n\t\t (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |\n\t\t\tPXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |\n\t\t\tPXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));\n\t}\n\n\tecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);\n\n\t/* in E3 this done in per-port section */\n\tif (!CHIP_IS_E3(sc))\n\t\tREG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));\n\n\tif (CHIP_IS_E1H(sc)) {\n/* not applicable for E2 (and above ...) */\n\t\tREG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));\n\t}\n\n\tif (CHIP_REV_IS_SLOW(sc)) {\n\t\tDELAY(200000);\n\t}\n\n\t/* finish CFC init */\n\tval = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);\n\tif (val != 1) {\n\t\tPMD_DRV_LOG(NOTICE, \"CFC LL_INIT failed\");\n\t\treturn -1;\n\t}\n\tval = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);\n\tif (val != 1) {\n\t\tPMD_DRV_LOG(NOTICE, \"CFC AC_INIT failed\");\n\t\treturn -1;\n\t}\n\tval = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);\n\tif (val != 1) {\n\t\tPMD_DRV_LOG(NOTICE, \"CFC CAM_INIT failed\");\n\t\treturn -1;\n\t}\n\tREG_WR(sc, CFC_REG_DEBUG0, 0);\n\n\tbnx2x_setup_fan_failure_detection(sc);\n\n\t/* clear PXP2 attentions */\n\tREG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);\n\n\tbnx2x_enable_blocks_attention(sc);\n\n\tif (!CHIP_REV_IS_SLOW(sc)) {\n\t\tecore_enable_blocks_parity(sc);\n\t}\n\n\tif (!BNX2X_NOMCP(sc)) {\n\t\tif (CHIP_IS_E1x(sc)) {\n\t\t\tbnx2x_common_init_phy(sc);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/**\n * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.\n *\n * @sc: driver handle\n */\nstatic int bnx2x_init_hw_common_chip(struct bnx2x_softc *sc)\n{\n\tint rc = bnx2x_init_hw_common(sc);\n\n\tif (rc) {\n\t\treturn rc;\n\t}\n\n\t/* In E2 2-PORT mode, same ext phy is used for the two paths */\n\tif (!BNX2X_NOMCP(sc)) {\n\t\tbnx2x_common_init_phy(sc);\n\t}\n\n\treturn 0;\n}\n\nstatic int bnx2x_init_hw_port(struct bnx2x_softc *sc)\n{\n\tint port = SC_PORT(sc);\n\tint init_phase = port ? PHASE_PORT1 : PHASE_PORT0;\n\tuint32_t low, high;\n\tuint32_t val;\n\n\tPMD_DRV_LOG(DEBUG, \"starting port init for port %d\", port);\n\n\tREG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);\n\n\tecore_init_block(sc, BLOCK_MISC, init_phase);\n\tecore_init_block(sc, BLOCK_PXP, init_phase);\n\tecore_init_block(sc, BLOCK_PXP2, init_phase);\n\n\t/*\n\t * Timers bug workaround: disables the pf_master bit in pglue at\n\t * common phase, we need to enable it here before any dmae access are\n\t * attempted. Therefore we manually added the enable-master to the\n\t * port phase (it also happens in the function phase)\n\t */\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tREG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);\n\t}\n\n\tecore_init_block(sc, BLOCK_ATC, init_phase);\n\tecore_init_block(sc, BLOCK_DMAE, init_phase);\n\tecore_init_block(sc, BLOCK_PGLUE_B, init_phase);\n\tecore_init_block(sc, BLOCK_QM, init_phase);\n\n\tecore_init_block(sc, BLOCK_TCM, init_phase);\n\tecore_init_block(sc, BLOCK_UCM, init_phase);\n\tecore_init_block(sc, BLOCK_CCM, init_phase);\n\tecore_init_block(sc, BLOCK_XCM, init_phase);\n\n\t/* QM cid (connection) count */\n\tecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);\n\n\tif (CNIC_SUPPORT(sc)) {\n\t\tecore_init_block(sc, BLOCK_TM, init_phase);\n\t\tREG_WR(sc, TM_REG_LIN0_SCAN_TIME + port * 4, 20);\n\t\tREG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port * 4, 31);\n\t}\n\n\tecore_init_block(sc, BLOCK_DORQ, init_phase);\n\n\tecore_init_block(sc, BLOCK_BRB1, init_phase);\n\n\tif (CHIP_IS_E1H(sc)) {\n\t\tif (IS_MF(sc)) {\n\t\t\tlow = (BNX2X_ONE_PORT(sc) ? 160 : 246);\n\t\t} else if (sc->mtu > 4096) {\n\t\t\tif (BNX2X_ONE_PORT(sc)) {\n\t\t\t\tlow = 160;\n\t\t\t} else {\n\t\t\t\tval = sc->mtu;\n\t\t\t\t/* (24*1024 + val*4)/256 */\n\t\t\t\tlow = (96 + (val / 64) + ((val % 64) ? 1 : 0));\n\t\t\t}\n\t\t} else {\n\t\t\tlow = (BNX2X_ONE_PORT(sc) ? 80 : 160);\n\t\t}\n\t\thigh = (low + 56);\t/* 14*1024/256 */\n\t\tREG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);\n\t\tREG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);\n\t}\n\n\tif (CHIP_IS_MODE_4_PORT(sc)) {\n\t\tREG_WR(sc, SC_PORT(sc) ?\n\t\t BRB1_REG_MAC_GUARANTIED_1 :\n\t\t BRB1_REG_MAC_GUARANTIED_0, 40);\n\t}\n\n\tecore_init_block(sc, BLOCK_PRS, init_phase);\n\tif (CHIP_IS_E3B0(sc)) {\n\t\tif (IS_MF_AFEX(sc)) {\n\t\t\t/* configure headers for AFEX mode */\n\t\t\tif (SC_PORT(sc)) {\n\t\t\t\tREG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_1,\n\t\t\t\t 0xE);\n\t\t\t\tREG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_1,\n\t\t\t\t 0x6);\n\t\t\t\tREG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_1, 0xA);\n\t\t\t} else {\n\t\t\t\tREG_WR(sc, PRS_REG_HDRS_AFTER_BASIC_PORT_0,\n\t\t\t\t 0xE);\n\t\t\t\tREG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0_PORT_0,\n\t\t\t\t 0x6);\n\t\t\t\tREG_WR(sc, PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);\n\t\t\t}\n\t\t} else {\n\t\t\t/* Ovlan exists only if we are in multi-function +\n\t\t\t * switch-dependent mode, in switch-independent there\n\t\t\t * is no ovlan headers\n\t\t\t */\n\t\t\tREG_WR(sc, SC_PORT(sc) ?\n\t\t\t PRS_REG_HDRS_AFTER_BASIC_PORT_1 :\n\t\t\t PRS_REG_HDRS_AFTER_BASIC_PORT_0,\n\t\t\t (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));\n\t\t}\n\t}\n\n\tecore_init_block(sc, BLOCK_TSDM, init_phase);\n\tecore_init_block(sc, BLOCK_CSDM, init_phase);\n\tecore_init_block(sc, BLOCK_USDM, init_phase);\n\tecore_init_block(sc, BLOCK_XSDM, init_phase);\n\n\tecore_init_block(sc, BLOCK_TSEM, init_phase);\n\tecore_init_block(sc, BLOCK_USEM, init_phase);\n\tecore_init_block(sc, BLOCK_CSEM, init_phase);\n\tecore_init_block(sc, BLOCK_XSEM, init_phase);\n\n\tecore_init_block(sc, BLOCK_UPB, init_phase);\n\tecore_init_block(sc, BLOCK_XPB, init_phase);\n\n\tecore_init_block(sc, BLOCK_PBF, init_phase);\n\n\tif (CHIP_IS_E1x(sc)) {\n/* configure PBF to work without PAUSE mtu 9000 */\n\t\tREG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);\n\n/* update threshold */\n\t\tREG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040 / 16));\n/* update init credit */\n\t\tREG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4,\n\t\t (9040 / 16) + 553 - 22);\n\n/* probe changes */\n\t\tREG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);\n\t\tDELAY(50);\n\t\tREG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);\n\t}\n\n\tif (CNIC_SUPPORT(sc)) {\n\t\tecore_init_block(sc, BLOCK_SRC, init_phase);\n\t}\n\n\tecore_init_block(sc, BLOCK_CDU, init_phase);\n\tecore_init_block(sc, BLOCK_CFC, init_phase);\n\tecore_init_block(sc, BLOCK_HC, init_phase);\n\tecore_init_block(sc, BLOCK_IGU, init_phase);\n\tecore_init_block(sc, BLOCK_MISC_AEU, init_phase);\n\t/* init aeu_mask_attn_func_0/1:\n\t * - SF mode: bits 3-7 are masked. only bits 0-2 are in use\n\t * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF\n\t * bits 4-7 are used for \"per vn group attention\" */\n\tval = IS_MF(sc) ? 0xF7 : 0x7;\n\tval |= 0x10;\n\tREG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, val);\n\n\tecore_init_block(sc, BLOCK_NIG, init_phase);\n\n\tif (!CHIP_IS_E1x(sc)) {\n/* Bit-map indicating which L2 hdrs may appear after the\n * basic Ethernet header\n */\n\t\tif (IS_MF_AFEX(sc)) {\n\t\t\tREG_WR(sc, SC_PORT(sc) ?\n\t\t\t NIG_REG_P1_HDRS_AFTER_BASIC :\n\t\t\t NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);\n\t\t} else {\n\t\t\tREG_WR(sc, SC_PORT(sc) ?\n\t\t\t NIG_REG_P1_HDRS_AFTER_BASIC :\n\t\t\t NIG_REG_P0_HDRS_AFTER_BASIC,\n\t\t\t IS_MF_SD(sc) ? 7 : 6);\n\t\t}\n\n\t\tif (CHIP_IS_E3(sc)) {\n\t\t\tREG_WR(sc, SC_PORT(sc) ?\n\t\t\t NIG_REG_LLH1_MF_MODE :\n\t\t\t NIG_REG_LLH_MF_MODE, IS_MF(sc));\n\t\t}\n\t}\n\tif (!CHIP_IS_E3(sc)) {\n\t\tREG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);\n\t}\n\n\t/* 0x2 disable mf_ov, 0x1 enable */\n\tREG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,\n\t (IS_MF_SD(sc) ? 0x1 : 0x2));\n\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tval = 0;\n\t\tswitch (sc->devinfo.mf_info.mf_mode) {\n\t\tcase MULTI_FUNCTION_SD:\n\t\t\tval = 1;\n\t\t\tbreak;\n\t\tcase MULTI_FUNCTION_SI:\n\t\tcase MULTI_FUNCTION_AFEX:\n\t\t\tval = 2;\n\t\t\tbreak;\n\t\t}\n\n\t\tREG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :\n\t\t\t NIG_REG_LLH0_CLS_TYPE), val);\n\t}\n\tREG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);\n\tREG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);\n\tREG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);\n\n\t/* If SPIO5 is set to generate interrupts, enable it for this port */\n\tval = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);\n\tif (val & MISC_SPIO_SPIO5) {\n\t\tuint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :\n\t\t\t\t MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);\n\t\tval = REG_RD(sc, reg_addr);\n\t\tval |= AEU_INPUTS_ATTN_BITS_SPIO5;\n\t\tREG_WR(sc, reg_addr, val);\n\t}\n\n\treturn 0;\n}\n\nstatic uint32_t\nbnx2x_flr_clnup_reg_poll(struct bnx2x_softc *sc, uint32_t reg,\n\t\t uint32_t expected, uint32_t poll_count)\n{\n\tuint32_t cur_cnt = poll_count;\n\tuint32_t val;\n\n\twhile ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {\n\t\tDELAY(FLR_WAIT_INTERVAL);\n\t}\n\n\treturn val;\n}\n\nstatic int\nbnx2x_flr_clnup_poll_hw_counter(struct bnx2x_softc *sc, uint32_t reg,\n\t\t\t __rte_unused const char *msg, uint32_t poll_cnt)\n{\n\tuint32_t val = bnx2x_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);\n\n\tif (val != 0) {\n\t\tPMD_DRV_LOG(NOTICE, \"%s usage count=%d\", msg, val);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* Common routines with VF FLR cleanup */\nstatic uint32_t bnx2x_flr_clnup_poll_count(struct bnx2x_softc *sc)\n{\n\t/* adjust polling timeout */\n\tif (CHIP_REV_IS_EMUL(sc)) {\n\t\treturn (FLR_POLL_CNT * 2000);\n\t}\n\n\tif (CHIP_REV_IS_FPGA(sc)) {\n\t\treturn (FLR_POLL_CNT * 120);\n\t}\n\n\treturn FLR_POLL_CNT;\n}\n\nstatic int bnx2x_poll_hw_usage_counters(struct bnx2x_softc *sc, uint32_t poll_cnt)\n{\n\t/* wait for CFC PF usage-counter to zero (includes all the VFs) */\n\tif (bnx2x_flr_clnup_poll_hw_counter(sc,\n\t\t\t\t\t CFC_REG_NUM_LCIDS_INSIDE_PF,\n\t\t\t\t\t \"CFC PF usage counter timed out\",\n\t\t\t\t\t poll_cnt)) {\n\t\treturn -1;\n\t}\n\n\t/* Wait for DQ PF usage-counter to zero (until DQ cleanup) */\n\tif (bnx2x_flr_clnup_poll_hw_counter(sc,\n\t\t\t\t\t DORQ_REG_PF_USAGE_CNT,\n\t\t\t\t\t \"DQ PF usage counter timed out\",\n\t\t\t\t\t poll_cnt)) {\n\t\treturn -1;\n\t}\n\n\t/* Wait for QM PF usage-counter to zero (until DQ cleanup) */\n\tif (bnx2x_flr_clnup_poll_hw_counter(sc,\n\t\t\t\t\t QM_REG_PF_USG_CNT_0 + 4 * SC_FUNC(sc),\n\t\t\t\t\t \"QM PF usage counter timed out\",\n\t\t\t\t\t poll_cnt)) {\n\t\treturn -1;\n\t}\n\n\t/* Wait for Timer PF usage-counters to zero (until DQ cleanup) */\n\tif (bnx2x_flr_clnup_poll_hw_counter(sc,\n\t\t\t\t\t TM_REG_LIN0_VNIC_UC + 4 * SC_PORT(sc),\n\t\t\t\t\t \"Timers VNIC usage counter timed out\",\n\t\t\t\t\t poll_cnt)) {\n\t\treturn -1;\n\t}\n\n\tif (bnx2x_flr_clnup_poll_hw_counter(sc,\n\t\t\t\t\t TM_REG_LIN0_NUM_SCANS +\n\t\t\t\t\t 4 * SC_PORT(sc),\n\t\t\t\t\t \"Timers NUM_SCANS usage counter timed out\",\n\t\t\t\t\t poll_cnt)) {\n\t\treturn -1;\n\t}\n\n\t/* Wait DMAE PF usage counter to zero */\n\tif (bnx2x_flr_clnup_poll_hw_counter(sc,\n\t\t\t\t\t dmae_reg_go_c[INIT_DMAE_C(sc)],\n\t\t\t\t\t \"DMAE dommand register timed out\",\n\t\t\t\t\t poll_cnt)) {\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n#define OP_GEN_PARAM(param) \\\n\t(((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)\n#define OP_GEN_TYPE(type) \\\n\t(((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)\n#define OP_GEN_AGG_VECT(index) \\\n\t(((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)\n\nstatic int\nbnx2x_send_final_clnup(struct bnx2x_softc *sc, uint8_t clnup_func,\n\t\t uint32_t poll_cnt)\n{\n\tuint32_t op_gen_command = 0;\n\tuint32_t comp_addr = (BAR_CSTRORM_INTMEM +\n\t\t\t CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));\n\tint ret = 0;\n\n\tif (REG_RD(sc, comp_addr)) {\n\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t \"Cleanup complete was not 0 before sending\");\n\t\treturn -1;\n\t}\n\n\top_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);\n\top_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);\n\top_gen_command |= OP_GEN_AGG_VECT(clnup_func);\n\top_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;\n\n\tREG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);\n\n\tif (bnx2x_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {\n\t\tPMD_DRV_LOG(NOTICE, \"FW final cleanup did not succeed\");\n\t\tPMD_DRV_LOG(DEBUG, \"At timeout completion address contained %x\",\n\t\t\t (REG_RD(sc, comp_addr)));\n\t\trte_panic(\"FLR cleanup failed\");\n\t\treturn -1;\n\t}\n\n\t/* Zero completion for nxt FLR */\n\tREG_WR(sc, comp_addr, 0);\n\n\treturn ret;\n}\n\nstatic void\nbnx2x_pbf_pN_buf_flushed(struct bnx2x_softc *sc, struct pbf_pN_buf_regs *regs,\n\t\t uint32_t poll_count)\n{\n\tuint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;\n\tuint32_t cur_cnt = poll_count;\n\n\tcrd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);\n\tcrd = crd_start = REG_RD(sc, regs->crd);\n\tinit_crd = REG_RD(sc, regs->init_crd);\n\n\twhile ((crd != init_crd) &&\n\t ((uint32_t) ((int32_t) crd_freed - (int32_t) crd_freed_start) <\n\t\t(init_crd - crd_start))) {\n\t\tif (cur_cnt--) {\n\t\t\tDELAY(FLR_WAIT_INTERVAL);\n\t\t\tcrd = REG_RD(sc, regs->crd);\n\t\t\tcrd_freed = REG_RD(sc, regs->crd_freed);\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nstatic void\nbnx2x_pbf_pN_cmd_flushed(struct bnx2x_softc *sc, struct pbf_pN_cmd_regs *regs,\n\t\t uint32_t poll_count)\n{\n\tuint32_t occup, to_free, freed, freed_start;\n\tuint32_t cur_cnt = poll_count;\n\n\toccup = to_free = REG_RD(sc, regs->lines_occup);\n\tfreed = freed_start = REG_RD(sc, regs->lines_freed);\n\n\twhile (occup &&\n\t ((uint32_t) ((int32_t) freed - (int32_t) freed_start) <\n\t\tto_free)) {\n\t\tif (cur_cnt--) {\n\t\t\tDELAY(FLR_WAIT_INTERVAL);\n\t\t\toccup = REG_RD(sc, regs->lines_occup);\n\t\t\tfreed = REG_RD(sc, regs->lines_freed);\n\t\t} else {\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nstatic void bnx2x_tx_hw_flushed(struct bnx2x_softc *sc, uint32_t poll_count)\n{\n\tstruct pbf_pN_cmd_regs cmd_regs[] = {\n\t\t{0, (CHIP_IS_E3B0(sc)) ?\n\t\t PBF_REG_TQ_OCCUPANCY_Q0 : PBF_REG_P0_TQ_OCCUPANCY,\n\t\t (CHIP_IS_E3B0(sc)) ?\n\t\t PBF_REG_TQ_LINES_FREED_CNT_Q0 : PBF_REG_P0_TQ_LINES_FREED_CNT},\n\t\t{1, (CHIP_IS_E3B0(sc)) ?\n\t\t PBF_REG_TQ_OCCUPANCY_Q1 : PBF_REG_P1_TQ_OCCUPANCY,\n\t\t (CHIP_IS_E3B0(sc)) ?\n\t\t PBF_REG_TQ_LINES_FREED_CNT_Q1 : PBF_REG_P1_TQ_LINES_FREED_CNT},\n\t\t{4, (CHIP_IS_E3B0(sc)) ?\n\t\t PBF_REG_TQ_OCCUPANCY_LB_Q : PBF_REG_P4_TQ_OCCUPANCY,\n\t\t (CHIP_IS_E3B0(sc)) ?\n\t\t PBF_REG_TQ_LINES_FREED_CNT_LB_Q :\n\t\t PBF_REG_P4_TQ_LINES_FREED_CNT}\n\t};\n\n\tstruct pbf_pN_buf_regs buf_regs[] = {\n\t\t{0, (CHIP_IS_E3B0(sc)) ?\n\t\t PBF_REG_INIT_CRD_Q0 : PBF_REG_P0_INIT_CRD,\n\t\t (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q0 : PBF_REG_P0_CREDIT,\n\t\t (CHIP_IS_E3B0(sc)) ?\n\t\t PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :\n\t\t PBF_REG_P0_INTERNAL_CRD_FREED_CNT},\n\t\t{1, (CHIP_IS_E3B0(sc)) ?\n\t\t PBF_REG_INIT_CRD_Q1 : PBF_REG_P1_INIT_CRD,\n\t\t (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_Q1 : PBF_REG_P1_CREDIT,\n\t\t (CHIP_IS_E3B0(sc)) ?\n\t\t PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :\n\t\t PBF_REG_P1_INTERNAL_CRD_FREED_CNT},\n\t\t{4, (CHIP_IS_E3B0(sc)) ?\n\t\t PBF_REG_INIT_CRD_LB_Q : PBF_REG_P4_INIT_CRD,\n\t\t (CHIP_IS_E3B0(sc)) ? PBF_REG_CREDIT_LB_Q : PBF_REG_P4_CREDIT,\n\t\t (CHIP_IS_E3B0(sc)) ?\n\t\t PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :\n\t\t PBF_REG_P4_INTERNAL_CRD_FREED_CNT},\n\t};\n\n\tuint32_t i;\n\n\t/* Verify the command queues are flushed P0, P1, P4 */\n\tfor (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {\n\t\tbnx2x_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);\n\t}\n\n\t/* Verify the transmission buffers are flushed P0, P1, P4 */\n\tfor (i = 0; i < ARRAY_SIZE(buf_regs); i++) {\n\t\tbnx2x_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);\n\t}\n}\n\nstatic void bnx2x_hw_enable_status(struct bnx2x_softc *sc)\n{\n\t__rte_unused uint32_t val;\n\n\tval = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);\n\tPMD_DRV_LOG(DEBUG, \"CFC_REG_WEAK_ENABLE_PF is 0x%x\", val);\n\n\tval = REG_RD(sc, PBF_REG_DISABLE_PF);\n\tPMD_DRV_LOG(DEBUG, \"PBF_REG_DISABLE_PF is 0x%x\", val);\n\n\tval = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);\n\tPMD_DRV_LOG(DEBUG, \"IGU_REG_PCI_PF_MSI_EN is 0x%x\", val);\n\n\tval = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);\n\tPMD_DRV_LOG(DEBUG, \"IGU_REG_PCI_PF_MSIX_EN is 0x%x\", val);\n\n\tval = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);\n\tPMD_DRV_LOG(DEBUG, \"IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\", val);\n\n\tval = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);\n\tPMD_DRV_LOG(DEBUG, \"PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\", val);\n\n\tval = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);\n\tPMD_DRV_LOG(DEBUG, \"PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\", val);\n\n\tval = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);\n\tPMD_DRV_LOG(DEBUG, \"PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\",\n\t\t val);\n}\n\n/**\n *\tbnx2x_pf_flr_clnup\n *\ta. re-enable target read on the PF\n *\tb. poll cfc per function usgae counter\n *\tc. poll the qm perfunction usage counter\n *\td. poll the tm per function usage counter\n *\te. poll the tm per function scan-done indication\n *\tf. clear the dmae channel associated wit hthe PF\n *\tg. zero the igu 'trailing edge' and 'leading edge' regs (attentions)\n *\th. call the common flr cleanup code with -1 (pf indication)\n */\nstatic int bnx2x_pf_flr_clnup(struct bnx2x_softc *sc)\n{\n\tuint32_t poll_cnt = bnx2x_flr_clnup_poll_count(sc);\n\n\t/* Re-enable PF target read access */\n\tREG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);\n\n\t/* Poll HW usage counters */\n\tif (bnx2x_poll_hw_usage_counters(sc, poll_cnt)) {\n\t\treturn -1;\n\t}\n\n\t/* Zero the igu 'trailing edge' and 'leading edge' */\n\n\t/* Send the FW cleanup command */\n\tif (bnx2x_send_final_clnup(sc, (uint8_t) SC_FUNC(sc), poll_cnt)) {\n\t\treturn -1;\n\t}\n\n\t/* ATC cleanup */\n\n\t/* Verify TX hw is flushed */\n\tbnx2x_tx_hw_flushed(sc, poll_cnt);\n\n\t/* Wait 100ms (not adjusted according to platform) */\n\tDELAY(100000);\n\n\t/* Verify no pending pci transactions */\n\tif (bnx2x_is_pcie_pending(sc)) {\n\t\tPMD_DRV_LOG(NOTICE, \"PCIE Transactions still pending\");\n\t}\n\n\t/* Debug */\n\tbnx2x_hw_enable_status(sc);\n\n\t/*\n\t * Master enable - Due to WB DMAE writes performed before this\n\t * register is re-initialized as part of the regular function init\n\t */\n\tREG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);\n\n\treturn 0;\n}\n\nstatic int bnx2x_init_hw_func(struct bnx2x_softc *sc)\n{\n\tint port = SC_PORT(sc);\n\tint func = SC_FUNC(sc);\n\tint init_phase = PHASE_PF0 + func;\n\tstruct ecore_ilt *ilt = sc->ilt;\n\tuint16_t cdu_ilt_start;\n\tuint32_t addr, val;\n\tuint32_t main_mem_base, main_mem_size, main_mem_prty_clr;\n\tint main_mem_width, rc;\n\tuint32_t i;\n\n\tPMD_DRV_LOG(DEBUG, \"starting func init for func %d\", func);\n\n\t/* FLR cleanup */\n\tif (!CHIP_IS_E1x(sc)) {\n\t\trc = bnx2x_pf_flr_clnup(sc);\n\t\tif (rc) {\n\t\t\tPMD_DRV_LOG(NOTICE, \"FLR cleanup failed!\");\n\t\t\treturn rc;\n\t\t}\n\t}\n\n\t/* set MSI reconfigure capability */\n\tif (sc->devinfo.int_block == INT_BLOCK_HC) {\n\t\taddr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);\n\t\tval = REG_RD(sc, addr);\n\t\tval |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;\n\t\tREG_WR(sc, addr, val);\n\t}\n\n\tecore_init_block(sc, BLOCK_PXP, init_phase);\n\tecore_init_block(sc, BLOCK_PXP2, init_phase);\n\n\tilt = sc->ilt;\n\tcdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;\n\n\tfor (i = 0; i < L2_ILT_LINES(sc); i++) {\n\t\tilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;\n\t\tilt->lines[cdu_ilt_start + i].page_mapping =\n\t\t (phys_addr_t)sc->context[i].vcxt_dma.paddr;\n\t\tilt->lines[cdu_ilt_start + i].size = sc->context[i].size;\n\t}\n\tecore_ilt_init_op(sc, INITOP_SET);\n\n\tREG_WR(sc, PRS_REG_NIC_MODE, 1);\n\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tuint32_t pf_conf = IGU_PF_CONF_FUNC_EN;\n\n/* Turn on a single ISR mode in IGU if driver is going to use\n * INT#x or MSI\n */\n\t\tif ((sc->interrupt_mode != INTR_MODE_MSIX)\n\t\t || (sc->interrupt_mode != INTR_MODE_SINGLE_MSIX)) {\n\t\t\tpf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;\n\t\t}\n\n/*\n * Timers workaround bug: function init part.\n * Need to wait 20msec after initializing ILT,\n * needed to make sure there are no requests in\n * one of the PXP internal queues with \"old\" ILT addresses\n */\n\t\tDELAY(20000);\n\n/*\n * Master enable - Due to WB DMAE writes performed before this\n * register is re-initialized as part of the regular function\n * init\n */\n\t\tREG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);\n/* Enable the function in IGU */\n\t\tREG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);\n\t}\n\n\tsc->dmae_ready = 1;\n\n\tecore_init_block(sc, BLOCK_PGLUE_B, init_phase);\n\n\tif (!CHIP_IS_E1x(sc))\n\t\tREG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);\n\n\tecore_init_block(sc, BLOCK_ATC, init_phase);\n\tecore_init_block(sc, BLOCK_DMAE, init_phase);\n\tecore_init_block(sc, BLOCK_NIG, init_phase);\n\tecore_init_block(sc, BLOCK_SRC, init_phase);\n\tecore_init_block(sc, BLOCK_MISC, init_phase);\n\tecore_init_block(sc, BLOCK_TCM, init_phase);\n\tecore_init_block(sc, BLOCK_UCM, init_phase);\n\tecore_init_block(sc, BLOCK_CCM, init_phase);\n\tecore_init_block(sc, BLOCK_XCM, init_phase);\n\tecore_init_block(sc, BLOCK_TSEM, init_phase);\n\tecore_init_block(sc, BLOCK_USEM, init_phase);\n\tecore_init_block(sc, BLOCK_CSEM, init_phase);\n\tecore_init_block(sc, BLOCK_XSEM, init_phase);\n\n\tif (!CHIP_IS_E1x(sc))\n\t\tREG_WR(sc, QM_REG_PF_EN, 1);\n\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tREG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);\n\t\tREG_WR(sc, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);\n\t\tREG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);\n\t\tREG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);\n\t}\n\tecore_init_block(sc, BLOCK_QM, init_phase);\n\n\tecore_init_block(sc, BLOCK_TM, init_phase);\n\tecore_init_block(sc, BLOCK_DORQ, init_phase);\n\n\tecore_init_block(sc, BLOCK_BRB1, init_phase);\n\tecore_init_block(sc, BLOCK_PRS, init_phase);\n\tecore_init_block(sc, BLOCK_TSDM, init_phase);\n\tecore_init_block(sc, BLOCK_CSDM, init_phase);\n\tecore_init_block(sc, BLOCK_USDM, init_phase);\n\tecore_init_block(sc, BLOCK_XSDM, init_phase);\n\tecore_init_block(sc, BLOCK_UPB, init_phase);\n\tecore_init_block(sc, BLOCK_XPB, init_phase);\n\tecore_init_block(sc, BLOCK_PBF, init_phase);\n\tif (!CHIP_IS_E1x(sc))\n\t\tREG_WR(sc, PBF_REG_DISABLE_PF, 0);\n\n\tecore_init_block(sc, BLOCK_CDU, init_phase);\n\n\tecore_init_block(sc, BLOCK_CFC, init_phase);\n\n\tif (!CHIP_IS_E1x(sc))\n\t\tREG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);\n\n\tif (IS_MF(sc)) {\n\t\tREG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);\n\t\tREG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, OVLAN(sc));\n\t}\n\n\tecore_init_block(sc, BLOCK_MISC_AEU, init_phase);\n\n\t/* HC init per function */\n\tif (sc->devinfo.int_block == INT_BLOCK_HC) {\n\t\tif (CHIP_IS_E1H(sc)) {\n\t\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);\n\n\t\t\tREG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);\n\t\t\tREG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);\n\t\t}\n\t\tecore_init_block(sc, BLOCK_HC, init_phase);\n\n\t} else {\n\t\tuint32_t num_segs, sb_idx, prod_offset;\n\n\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);\n\n\t\tif (!CHIP_IS_E1x(sc)) {\n\t\t\tREG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);\n\t\t\tREG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);\n\t\t}\n\n\t\tecore_init_block(sc, BLOCK_IGU, init_phase);\n\n\t\tif (!CHIP_IS_E1x(sc)) {\n\t\t\tint dsb_idx = 0;\n\t/**\n\t * Producer memory:\n\t * E2 mode: address 0-135 match to the mapping memory;\n\t * 136 - PF0 default prod; 137 - PF1 default prod;\n\t * 138 - PF2 default prod; 139 - PF3 default prod;\n\t * 140 - PF0 attn prod; 141 - PF1 attn prod;\n\t * 142 - PF2 attn prod; 143 - PF3 attn prod;\n\t * 144-147 reserved.\n\t *\n\t * E1.5 mode - In backward compatible mode;\n\t * for non default SB; each even line in the memory\n\t * holds the U producer and each odd line hold\n\t * the C producer. The first 128 producers are for\n\t * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20\n\t * producers are for the DSB for each PF.\n\t * Each PF has five segments: (the order inside each\n\t * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;\n\t * 132-135 C prods; 136-139 X prods; 140-143 T prods;\n\t * 144-147 attn prods;\n\t */\n\t\t\t/* non-default-status-blocks */\n\t\t\tnum_segs = CHIP_INT_MODE_IS_BC(sc) ?\n\t\t\t IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;\n\t\t\tfor (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {\n\t\t\t\tprod_offset = (sc->igu_base_sb + sb_idx) *\n\t\t\t\t num_segs;\n\n\t\t\t\tfor (i = 0; i < num_segs; i++) {\n\t\t\t\t\taddr = IGU_REG_PROD_CONS_MEMORY +\n\t\t\t\t\t (prod_offset + i) * 4;\n\t\t\t\t\tREG_WR(sc, addr, 0);\n\t\t\t\t}\n\t\t\t\t/* send consumer update with value 0 */\n\t\t\t\tbnx2x_ack_sb(sc, sc->igu_base_sb + sb_idx,\n\t\t\t\t\t USTORM_ID, 0, IGU_INT_NOP, 1);\n\t\t\t\tbnx2x_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);\n\t\t\t}\n\n\t\t\t/* default-status-blocks */\n\t\t\tnum_segs = CHIP_INT_MODE_IS_BC(sc) ?\n\t\t\t IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;\n\n\t\t\tif (CHIP_IS_MODE_4_PORT(sc))\n\t\t\t\tdsb_idx = SC_FUNC(sc);\n\t\t\telse\n\t\t\t\tdsb_idx = SC_VN(sc);\n\n\t\t\tprod_offset = (CHIP_INT_MODE_IS_BC(sc) ?\n\t\t\t\t IGU_BC_BASE_DSB_PROD + dsb_idx :\n\t\t\t\t IGU_NORM_BASE_DSB_PROD + dsb_idx);\n\n\t\t\t/*\n\t\t\t * igu prods come in chunks of E1HVN_MAX (4) -\n\t\t\t * does not matters what is the current chip mode\n\t\t\t */\n\t\t\tfor (i = 0; i < (num_segs * E1HVN_MAX); i += E1HVN_MAX) {\n\t\t\t\taddr = IGU_REG_PROD_CONS_MEMORY +\n\t\t\t\t (prod_offset + i) * 4;\n\t\t\t\tREG_WR(sc, addr, 0);\n\t\t\t}\n\t\t\t/* send consumer update with 0 */\n\t\t\tif (CHIP_INT_MODE_IS_BC(sc)) {\n\t\t\t\tbnx2x_ack_sb(sc, sc->igu_dsb_id,\n\t\t\t\t\t USTORM_ID, 0, IGU_INT_NOP, 1);\n\t\t\t\tbnx2x_ack_sb(sc, sc->igu_dsb_id,\n\t\t\t\t\t CSTORM_ID, 0, IGU_INT_NOP, 1);\n\t\t\t\tbnx2x_ack_sb(sc, sc->igu_dsb_id,\n\t\t\t\t\t XSTORM_ID, 0, IGU_INT_NOP, 1);\n\t\t\t\tbnx2x_ack_sb(sc, sc->igu_dsb_id,\n\t\t\t\t\t TSTORM_ID, 0, IGU_INT_NOP, 1);\n\t\t\t\tbnx2x_ack_sb(sc, sc->igu_dsb_id,\n\t\t\t\t\t ATTENTION_ID, 0, IGU_INT_NOP, 1);\n\t\t\t} else {\n\t\t\t\tbnx2x_ack_sb(sc, sc->igu_dsb_id,\n\t\t\t\t\t USTORM_ID, 0, IGU_INT_NOP, 1);\n\t\t\t\tbnx2x_ack_sb(sc, sc->igu_dsb_id,\n\t\t\t\t\t ATTENTION_ID, 0, IGU_INT_NOP, 1);\n\t\t\t}\n\t\t\tbnx2x_igu_clear_sb(sc, sc->igu_dsb_id);\n\n\t\t\t/* !!! these should become driver const once\n\t\t\t rf-tool supports split-68 const */\n\t\t\tREG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);\n\t\t\tREG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);\n\t\t\tREG_WR(sc, IGU_REG_SB_MASK_LSB, 0);\n\t\t\tREG_WR(sc, IGU_REG_SB_MASK_MSB, 0);\n\t\t\tREG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);\n\t\t\tREG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);\n\t\t}\n\t}\n\n\t/* Reset PCIE errors for debug */\n\tREG_WR(sc, 0x2114, 0xffffffff);\n\tREG_WR(sc, 0x2120, 0xffffffff);\n\n\tif (CHIP_IS_E1x(sc)) {\n\t\tmain_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2;\t/*dwords */\n\t\tmain_mem_base = HC_REG_MAIN_MEMORY +\n\t\t SC_PORT(sc) * (main_mem_size * 4);\n\t\tmain_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;\n\t\tmain_mem_width = 8;\n\n\t\tval = REG_RD(sc, main_mem_prty_clr);\n\t\tif (val) {\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"Parity errors in HC block during function init (0x%x)!\",\n\t\t\t\t val);\n\t\t}\n\n/* Clear \"false\" parity errors in MSI-X table */\n\t\tfor (i = main_mem_base;\n\t\t i < main_mem_base + main_mem_size * 4;\n\t\t i += main_mem_width) {\n\t\t\tbnx2x_read_dmae(sc, i, main_mem_width / 4);\n\t\t\tbnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data),\n\t\t\t\t i, main_mem_width / 4);\n\t\t}\n/* Clear HC parity attention */\n\t\tREG_RD(sc, main_mem_prty_clr);\n\t}\n\n\t/* Enable STORMs SP logging */\n\tREG_WR8(sc, BAR_USTRORM_INTMEM +\n\t\tUSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);\n\tREG_WR8(sc, BAR_TSTRORM_INTMEM +\n\t\tTSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);\n\tREG_WR8(sc, BAR_CSTRORM_INTMEM +\n\t\tCSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);\n\tREG_WR8(sc, BAR_XSTRORM_INTMEM +\n\t\tXSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);\n\n\telink_phy_probe(&sc->link_params);\n\n\treturn 0;\n}\n\nstatic void bnx2x_link_reset(struct bnx2x_softc *sc)\n{\n\tif (!BNX2X_NOMCP(sc)) {\n\t\telink_lfa_reset(&sc->link_params, &sc->link_vars);\n\t} else {\n\t\tif (!CHIP_REV_IS_SLOW(sc)) {\n\t\t\tPMD_DRV_LOG(WARNING,\n\t\t\t\t \"Bootcode is missing - cannot reset link\");\n\t\t}\n\t}\n}\n\nstatic void bnx2x_reset_port(struct bnx2x_softc *sc)\n{\n\tint port = SC_PORT(sc);\n\tuint32_t val;\n\n\t/* reset physical Link */\n\tbnx2x_link_reset(sc);\n\n\tREG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);\n\n\t/* Do not rcv packets to BRB */\n\tREG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);\n\t/* Do not direct rcv packets that are not for MCP to the BRB */\n\tREG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :\n\t\t NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);\n\n\t/* Configure AEU */\n\tREG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);\n\n\tDELAY(100000);\n\n\t/* Check for BRB port occupancy */\n\tval = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);\n\tif (val) {\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t \"BRB1 is not empty, %d blocks are occupied\", val);\n\t}\n}\n\nstatic void bnx2x_ilt_wr(struct bnx2x_softc *sc, uint32_t index, phys_addr_t addr)\n{\n\tint reg;\n\tuint32_t wb_write[2];\n\n\treg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;\n\n\twb_write[0] = ONCHIP_ADDR1(addr);\n\twb_write[1] = ONCHIP_ADDR2(addr);\n\tREG_WR_DMAE(sc, reg, wb_write, 2);\n}\n\nstatic void bnx2x_clear_func_ilt(struct bnx2x_softc *sc, uint32_t func)\n{\n\tuint32_t i, base = FUNC_ILT_BASE(func);\n\tfor (i = base; i < base + ILT_PER_FUNC; i++) {\n\t\tbnx2x_ilt_wr(sc, i, 0);\n\t}\n}\n\nstatic void bnx2x_reset_func(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_fastpath *fp;\n\tint port = SC_PORT(sc);\n\tint func = SC_FUNC(sc);\n\tint i;\n\n\t/* Disable the function in the FW */\n\tREG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);\n\tREG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);\n\tREG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);\n\tREG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);\n\n\t/* FP SBs */\n\tFOR_EACH_ETH_QUEUE(sc, i) {\n\t\tfp = &sc->fp[i];\n\t\tREG_WR8(sc, BAR_CSTRORM_INTMEM +\n\t\t\tCSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),\n\t\t\tSB_DISABLED);\n\t}\n\n\t/* SP SB */\n\tREG_WR8(sc, BAR_CSTRORM_INTMEM +\n\t\tCSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), SB_DISABLED);\n\n\tfor (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {\n\t\tREG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),\n\t\t 0);\n\t}\n\n\t/* Configure IGU */\n\tif (sc->devinfo.int_block == INT_BLOCK_HC) {\n\t\tREG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);\n\t\tREG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);\n\t} else {\n\t\tREG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);\n\t\tREG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);\n\t}\n\n\tif (CNIC_LOADED(sc)) {\n/* Disable Timer scan */\n\t\tREG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port * 4, 0);\n/*\n * Wait for at least 10ms and up to 2 second for the timers\n * scan to complete\n */\n\t\tfor (i = 0; i < 200; i++) {\n\t\t\tDELAY(10000);\n\t\t\tif (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port * 4))\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Clear ILT */\n\tbnx2x_clear_func_ilt(sc, func);\n\n\t/*\n\t * Timers workaround bug for E2: if this is vnic-3,\n\t * we need to set the entire ilt range for this timers.\n\t */\n\tif (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {\n\t\tstruct ilt_client_info ilt_cli;\n/* use dummy TM client */\n\t\tmemset(&ilt_cli, 0, sizeof(struct ilt_client_info));\n\t\tilt_cli.start = 0;\n\t\tilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;\n\t\tilt_cli.client_num = ILT_CLIENT_TM;\n\n\t\tecore_ilt_boundry_init_op(sc, &ilt_cli, 0);\n\t}\n\n\t/* this assumes that reset_port() called before reset_func() */\n\tif (!CHIP_IS_E1x(sc)) {\n\t\tbnx2x_pf_disable(sc);\n\t}\n\n\tsc->dmae_ready = 0;\n}\n\nstatic void bnx2x_release_firmware(struct bnx2x_softc *sc)\n{\n\trte_free(sc->init_ops);\n\trte_free(sc->init_ops_offsets);\n\trte_free(sc->init_data);\n\trte_free(sc->iro_array);\n}\n\nstatic int bnx2x_init_firmware(struct bnx2x_softc *sc)\n{\n\tuint32_t len, i;\n\tuint8_t *p = sc->firmware;\n\tuint32_t off[24];\n\n\tfor (i = 0; i < 24; ++i)\n\t\toff[i] = rte_be_to_cpu_32(*((uint32_t *) sc->firmware + i));\n\n\tlen = off[0];\n\tsc->init_ops = rte_zmalloc(\"\", len, RTE_CACHE_LINE_SIZE);\n\tif (!sc->init_ops)\n\t\tgoto alloc_failed;\n\tbnx2x_data_to_init_ops(p + off[1], sc->init_ops, len);\n\n\tlen = off[2];\n\tsc->init_ops_offsets = rte_zmalloc(\"\", len, RTE_CACHE_LINE_SIZE);\n\tif (!sc->init_ops_offsets)\n\t\tgoto alloc_failed;\n\tbnx2x_data_to_init_offsets(p + off[3], sc->init_ops_offsets, len);\n\n\tlen = off[4];\n\tsc->init_data = rte_zmalloc(\"\", len, RTE_CACHE_LINE_SIZE);\n\tif (!sc->init_data)\n\t\tgoto alloc_failed;\n\tbnx2x_data_to_init_data(p + off[5], sc->init_data, len);\n\n\tsc->tsem_int_table_data = p + off[7];\n\tsc->tsem_pram_data = p + off[9];\n\tsc->usem_int_table_data = p + off[11];\n\tsc->usem_pram_data = p + off[13];\n\tsc->csem_int_table_data = p + off[15];\n\tsc->csem_pram_data = p + off[17];\n\tsc->xsem_int_table_data = p + off[19];\n\tsc->xsem_pram_data = p + off[21];\n\n\tlen = off[22];\n\tsc->iro_array = rte_zmalloc(\"\", len, RTE_CACHE_LINE_SIZE);\n\tif (!sc->iro_array)\n\t\tgoto alloc_failed;\n\tbnx2x_data_to_iro_array(p + off[23], sc->iro_array, len);\n\n\treturn 0;\n\nalloc_failed:\n\tbnx2x_release_firmware(sc);\n\treturn -1;\n}\n\nstatic int cut_gzip_prefix(const uint8_t * zbuf, int len)\n{\n#define MIN_PREFIX_SIZE (10)\n\n\tint n = MIN_PREFIX_SIZE;\n\tuint16_t xlen;\n\n\tif (!(zbuf[0] == 0x1f && zbuf[1] == 0x8b && zbuf[2] == Z_DEFLATED) ||\n\t len <= MIN_PREFIX_SIZE) {\n\t\treturn -1;\n\t}\n\n\t/* optional extra fields are present */\n\tif (zbuf[3] & 0x4) {\n\t\txlen = zbuf[13];\n\t\txlen <<= 8;\n\t\txlen += zbuf[12];\n\n\t\tn += xlen;\n\t}\n\t/* file name is present */\n\tif (zbuf[3] & 0x8) {\n\t\twhile ((zbuf[n++] != 0) && (n < len)) ;\n\t}\n\n\treturn n;\n}\n\nstatic int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t * zbuf, int len)\n{\n\tint ret;\n\tint data_begin = cut_gzip_prefix(zbuf, len);\n\n\tPMD_DRV_LOG(DEBUG, \"ecore_gunzip %d\", len);\n\n\tif (data_begin <= 0) {\n\t\tPMD_DRV_LOG(NOTICE, \"bad gzip prefix\");\n\t\treturn -1;\n\t}\n\n\tmemset(&zlib_stream, 0, sizeof(zlib_stream));\n\tzlib_stream.next_in = zbuf + data_begin;\n\tzlib_stream.avail_in = len - data_begin;\n\tzlib_stream.next_out = sc->gz_buf;\n\tzlib_stream.avail_out = FW_BUF_SIZE;\n\n\tret = inflateInit2(&zlib_stream, -MAX_WBITS);\n\tif (ret != Z_OK) {\n\t\tPMD_DRV_LOG(NOTICE, \"zlib inflateInit2 error\");\n\t\treturn ret;\n\t}\n\n\tret = inflate(&zlib_stream, Z_FINISH);\n\tif ((ret != Z_STREAM_END) && (ret != Z_OK)) {\n\t\tPMD_DRV_LOG(NOTICE, \"zlib inflate error: %d %s\", ret,\n\t\t\t zlib_stream.msg);\n\t}\n\n\tsc->gz_outlen = zlib_stream.total_out;\n\tif (sc->gz_outlen & 0x3) {\n\t\tPMD_DRV_LOG(NOTICE, \"firmware is not aligned. gz_outlen == %d\",\n\t\t\t sc->gz_outlen);\n\t}\n\tsc->gz_outlen >>= 2;\n\n\tinflateEnd(&zlib_stream);\n\n\tif (ret == Z_STREAM_END)\n\t\treturn 0;\n\n\treturn ret;\n}\n\nstatic void\necore_write_dmae_phys_len(struct bnx2x_softc *sc, phys_addr_t phys_addr,\n\t\t\t uint32_t addr, uint32_t len)\n{\n\tbnx2x_write_dmae_phys_len(sc, phys_addr, addr, len);\n}\n\nvoid\necore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr, size_t size,\n\t\t\t uint32_t * data)\n{\n\tuint8_t i;\n\tfor (i = 0; i < size / 4; i++) {\n\t\tREG_WR(sc, addr + (i * 4), data[i]);\n\t}\n}\n\nstatic const char *get_ext_phy_type(uint32_t ext_phy_type)\n{\n\tuint32_t phy_type_idx = ext_phy_type >> 8;\n\tstatic const char *types[] =\n\t { \"DIRECT\", \"BNX2X-8071\", \"BNX2X-8072\", \"BNX2X-8073\",\n\t\t\"BNX2X-8705\", \"BNX2X-8706\", \"BNX2X-8726\", \"BNX2X-8481\", \"SFX-7101\",\n\t\t\"BNX2X-8727\",\n\t\t\"BNX2X-8727-NOC\", \"BNX2X-84823\", \"NOT_CONN\", \"FAILURE\"\n\t};\n\n\tif (phy_type_idx < 12)\n\t\treturn types[phy_type_idx];\n\telse if (PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN == ext_phy_type)\n\t\treturn types[12];\n\telse\n\t\treturn types[13];\n}\n\nstatic const char *get_state(uint32_t state)\n{\n\tuint32_t state_idx = state >> 12;\n\tstatic const char *states[] = { \"CLOSED\", \"OPENING_WAIT4_LOAD\",\n\t\t\"OPENING_WAIT4_PORT\", \"OPEN\", \"CLOSING_WAIT4_HALT\",\n\t\t\"CLOSING_WAIT4_DELETE\", \"CLOSING_WAIT4_UNLOAD\",\n\t\t\"UNKNOWN\", \"UNKNOWN\", \"UNKNOWN\", \"UNKNOWN\", \"UNKNOWN\",\n\t\t\"UNKNOWN\", \"DISABLED\", \"DIAG\", \"ERROR\", \"UNDEFINED\"\n\t};\n\n\tif (state_idx <= 0xF)\n\t\treturn states[state_idx];\n\telse\n\t\treturn states[0x10];\n}\n\nstatic const char *get_recovery_state(uint32_t state)\n{\n\tstatic const char *states[] = { \"NONE\", \"DONE\", \"INIT\",\n\t\t\"WAIT\", \"FAILED\", \"NIC_LOADING\"\n\t};\n\treturn states[state];\n}\n\nstatic const char *get_rx_mode(uint32_t mode)\n{\n\tstatic const char *modes[] = { \"NONE\", \"NORMAL\", \"ALLMULTI\",\n\t\t\"PROMISC\", \"MAX_MULTICAST\", \"ERROR\"\n\t};\n\n\tif (mode < 0x4)\n\t\treturn modes[mode];\n\telse if (BNX2X_MAX_MULTICAST == mode)\n\t\treturn modes[4];\n\telse\n\t\treturn modes[5];\n}\n\n#define BNX2X_INFO_STR_MAX 256\nstatic const char *get_bnx2x_flags(uint32_t flags)\n{\n\tint i;\n\tstatic const char *flag[] = { \"ONE_PORT \", \"NO_ISCSI \",\n\t\t\"NO_FCOE \", \"NO_WOL \", \"USING_DAC \", \"USING_MSIX \",\n\t\t\"USING_MSI \", \"DISABLE_MSI \", \"UNKNOWN \", \"NO_MCP \",\n\t\t\"SAFC_TX_FLAG \", \"MF_FUNC_DIS \", \"TX_SWITCHING \"\n\t};\n\tstatic char flag_str[BNX2X_INFO_STR_MAX];\n\tmemset(flag_str, 0, BNX2X_INFO_STR_MAX);\n\n\tfor (i = 0; i < 5; i++)\n\t\tif (flags & (1 << i)) {\n\t\t\tstrcat(flag_str, flag[i]);\n\t\t\tflags ^= (1 << i);\n\t\t}\n\tif (flags) {\n\t\tstatic char unknown[BNX2X_INFO_STR_MAX];\n\t\tsnprintf(unknown, 32, \"Unknown flag mask %x\", flags);\n\t\tstrcat(flag_str, unknown);\n\t}\n\treturn flag_str;\n}\n\n/*\n * Prints useful adapter info.\n */\nvoid bnx2x_print_adapter_info(struct bnx2x_softc *sc)\n{\n\tint i = 0;\n\t__rte_unused uint32_t ext_phy_type;\n\n\tPMD_INIT_FUNC_TRACE();\n\tif (sc->link_vars.phy_flags & PHY_XGXS_FLAG)\n\t\text_phy_type = ELINK_XGXS_EXT_PHY_TYPE(REG_RD(sc,\n\t\t\t\t\t\t\t sc->\n\t\t\t\t\t\t\t devinfo.shmem_base\n\t\t\t\t\t\t\t + offsetof(struct\n\t\t\t\t\t\t\t\t\t shmem_region,\n\t\t\t\t\t\t\t\t\t dev_info.port_hw_config\n\t\t\t\t\t\t\t\t\t [0].external_phy_config)));\n\telse\n\t\text_phy_type = ELINK_SERDES_EXT_PHY_TYPE(REG_RD(sc,\n\t\t\t\t\t\t\t\tsc->\n\t\t\t\t\t\t\t\tdevinfo.shmem_base\n\t\t\t\t\t\t\t\t+\n\t\t\t\t\t\t\t\toffsetof(struct\n\t\t\t\t\t\t\t\t\t shmem_region,\n\t\t\t\t\t\t\t\t\t dev_info.port_hw_config\n\t\t\t\t\t\t\t\t\t [0].external_phy_config)));\n\n\tPMD_INIT_LOG(DEBUG, \"\\n\\n===================================\\n\");\n\t/* Hardware chip info. */\n\tPMD_INIT_LOG(DEBUG, \"%10s : %#08x\\n\", \"ASIC\", sc->devinfo.chip_id);\n\tPMD_INIT_LOG(DEBUG, \"%10s : %c%d\\n\", \"Rev\", (CHIP_REV(sc) >> 12) + 'A',\n\t\t (CHIP_METAL(sc) >> 4));\n\n\t/* Bus info. */\n\tPMD_INIT_LOG(DEBUG, \"%10s : %d, \", \"Bus PCIe\", sc->devinfo.pcie_link_width);\n\tswitch (sc->devinfo.pcie_link_speed) {\n\tcase 1:\n\t\tPMD_INIT_LOG(DEBUG, \"2.5 Gbps\\n\");\n\t\tbreak;\n\tcase 2:\n\t\tPMD_INIT_LOG(DEBUG, \"5 Gbps\\n\");\n\t\tbreak;\n\tcase 4:\n\t\tPMD_INIT_LOG(DEBUG, \"8 Gbps\\n\");\n\t\tbreak;\n\tdefault:\n\t\tPMD_INIT_LOG(DEBUG, \"Unknown link speed\\n\");\n\t}\n\n\t/* Device features. */\n\tPMD_INIT_LOG(DEBUG, \"%10s : \", \"Flags\");\n\n\t/* Miscellaneous flags. */\n\tif (sc->devinfo.pcie_cap_flags & BNX2X_MSI_CAPABLE_FLAG) {\n\t\tPMD_INIT_LOG(DEBUG, \"MSI\");\n\t\ti++;\n\t}\n\n\tif (sc->devinfo.pcie_cap_flags & BNX2X_MSIX_CAPABLE_FLAG) {\n\t\tif (i > 0)\n\t\t\tPMD_INIT_LOG(DEBUG, \"|\");\n\t\tPMD_INIT_LOG(DEBUG, \"MSI-X\");\n\t\ti++;\n\t}\n\n\tPMD_INIT_LOG(DEBUG, \"\\n\");\n\n\tif (IS_PF(sc)) {\n\t\tPMD_INIT_LOG(DEBUG, \"\\n%10s : \", \"Queues\");\n\t\tswitch (sc->sp->rss_rdata.rss_mode) {\n\t\tcase ETH_RSS_MODE_DISABLED:\n\t\t\tPMD_INIT_LOG(DEBUG, \"None\\n\");\n\t\t\tbreak;\n\t\tcase ETH_RSS_MODE_REGULAR:\n\t\t\tPMD_INIT_LOG(DEBUG, \"RSS : %d\\n\", sc->num_queues);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_INIT_LOG(DEBUG, \"Unknown\\n\");\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Firmware versions and device features. */\n\tPMD_INIT_LOG(DEBUG, \"%10s : %d.%d.%d\\n%10s : %s\\n\",\n\t\t \"Firmware\",\n\t\t BNX2X_5710_FW_MAJOR_VERSION,\n\t\t BNX2X_5710_FW_MINOR_VERSION,\n\t\t BNX2X_5710_FW_REVISION_VERSION,\n\t\t \"Bootcode\", sc->devinfo.bc_ver_str);\n\n\tPMD_INIT_LOG(DEBUG, \"===================================\\n\");\n\tPMD_INIT_LOG(DEBUG, \"%10s : %u\\n\", \"Bnx2x Func\", sc->pcie_func);\n\tPMD_INIT_LOG(DEBUG, \"%10s : %s\\n\", \"Bnx2x Flags\", get_bnx2x_flags(sc->flags));\n\tPMD_INIT_LOG(DEBUG, \"%10s : %s\\n\", \"DMAE Is\",\n\t\t (sc->dmae_ready ? \"Ready\" : \"Not Ready\"));\n\tPMD_INIT_LOG(DEBUG, \"%10s : %s\\n\", \"OVLAN\", (OVLAN(sc) ? \"YES\" : \"NO\"));\n\tPMD_INIT_LOG(DEBUG, \"%10s : %s\\n\", \"MF\", (IS_MF(sc) ? \"YES\" : \"NO\"));\n\tPMD_INIT_LOG(DEBUG, \"%10s : %u\\n\", \"MTU\", sc->mtu);\n\tPMD_INIT_LOG(DEBUG, \"%10s : %s\\n\", \"PHY Type\", get_ext_phy_type(ext_phy_type));\n\tPMD_INIT_LOG(DEBUG, \"%10s : \", \"MAC Addr\");\n\tfor (i = 0; i < 6; i++)\n\t\tPMD_INIT_LOG(DEBUG, \"%x%s\", sc->link_params.mac_addr[i],\n\t\t\t i < 5 ? \":\" : \"\\n\");\n\tPMD_INIT_LOG(DEBUG, \"%10s : %s\\n\", \"RX Mode\", get_rx_mode(sc->rx_mode));\n\tPMD_INIT_LOG(DEBUG, \"%10s : %s\\n\", \"State\", get_state(sc->state));\n\tif (sc->recovery_state)\n\t\tPMD_INIT_LOG(DEBUG, \"%10s : %s\\n\", \"Recovery\",\n\t\t\t get_recovery_state(sc->recovery_state));\n\tPMD_INIT_LOG(DEBUG, \"%10s : CQ = %lx, EQ = %lx\\n\", \"SPQ Left\",\n\t\t sc->cq_spq_left, sc->eq_spq_left);\n\tPMD_INIT_LOG(DEBUG, \"%10s : %x\\n\", \"Switch\", sc->link_params.switch_cfg);\n\tPMD_INIT_LOG(DEBUG, \"===================================\\n\\n\");\n}\n" }, { "path": "drivers/net/bnx2x/bnx2x.h", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __BNX2X_H__\n#define __BNX2X_H__\n\n#include \"bnx2x_ethdev.h\"\n\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n#ifndef LITTLE_ENDIAN\n#define LITTLE_ENDIAN\n#endif\n#ifndef __LITTLE_ENDIAN\n#define __LITTLE_ENDIAN\n#endif\n#undef BIG_ENDIAN\n#undef __BIG_ENDIAN\n#else /* _BIG_ENDIAN */\n#ifndef BIG_ENDIAN\n#define BIG_ENDIAN\n#endif\n#ifndef __BIG_ENDIAN\n#define __BIG_ENDIAN\n#endif\n#undef LITTLE_ENDIAN\n#undef __LITTLE_ENDIAN\n#endif\n\n#include \"ecore_mfw_req.h\"\n#include \"ecore_fw_defs.h\"\n#include \"ecore_hsi.h\"\n#include \"ecore_reg.h\"\n#include \"bnx2x_stats.h\"\n#include \"bnx2x_vfpf.h\"\n\n#include \"elink.h\"\n\n#include \n\n#define PCIY_PMG PCI_CAP_ID_PM\n#define PCIY_MSI PCI_CAP_ID_MSI\n#define PCIY_EXPRESS PCI_CAP_ID_EXP\n#define PCIY_MSIX PCI_CAP_ID_MSIX\n#define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC\n#define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND\n#define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA\n#define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW\n#define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS\n#define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL\n#define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD\n#define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ\n#define PCIR_POWER_STATUS PCI_PM_CTRL\n#define PCIM_PSTAT_DMASK PCI_PM_CTRL_STATE_MASK\n#define PCIM_PSTAT_PME PCI_PM_CTRL_PME_STATUS\n#define PCIM_PSTAT_D3 0x3\n#define PCIM_PSTAT_PMEENABLE PCI_PM_CTRL_PME_ENABLE\n#define PCIR_MSIX_CTRL PCI_MSIX_FLAGS\n#define PCIM_MSIXCTRL_TABLE_SIZE PCI_MSIX_FLAGS_QSIZE\n\n#define IFM_10G_CX4 20 /* 10GBase CX4 copper */\n#define IFM_10G_TWINAX 22 /* 10GBase Twinax copper */\n#define IFM_10G_T 26 /* 10GBase-T - RJ45 */\n\n#define PCIR_EXPRESS_DEVICE_STA PCI_EXP_TYPE_RC_EC\n#define PCIM_EXP_STA_TRANSACTION_PND PCI_EXP_DEVSTA_TRPND\n#define PCIR_EXPRESS_LINK_STA PCI_EXP_LNKSTA\n#define PCIM_LINK_STA_WIDTH PCI_EXP_LNKSTA_NLW\n#define PCIM_LINK_STA_SPEED PCI_EXP_LNKSTA_CLS\n#define PCIR_EXPRESS_DEVICE_CTL PCI_EXP_DEVCTL\n#define PCIM_EXP_CTL_MAX_PAYLOAD PCI_EXP_DEVCTL_PAYLOAD\n#define PCIM_EXP_CTL_MAX_READ_REQUEST PCI_EXP_DEVCTL_READRQ\n\n#ifndef ARRAY_SIZE\n#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))\n#endif\n#ifndef ARRSIZE\n#define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))\n#endif\n#ifndef DIV_ROUND_UP\n#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n#endif\n#ifndef roundup\n#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))\n#endif\n#ifndef ilog2\nstatic inline\nint bnx2x_ilog2(int x)\n{\n\tint log = 0;\n\tx >>= 1;\n\n\twhile(x) {\n\t\tlog++;\n\t\tx >>= 1;\n\t}\n\treturn log;\n}\n#define ilog2(x) bnx2x_ilog2(x)\n#endif\n\n#include \"ecore_sp.h\"\n\nstruct bnx2x_device_type {\n\tuint16_t bnx2x_vid;\n\tuint16_t bnx2x_did;\n\tuint16_t bnx2x_svid;\n\tuint16_t bnx2x_sdid;\n\tchar *bnx2x_name;\n};\n\n#define RTE_MBUF_DATA_DMA_ADDR(mb) \\\n\t((uint64_t)((mb)->buf_physaddr + (mb)->data_off))\n\n#define BNX2X_PAGE_SHIFT 12\n#define BNX2X_PAGE_SIZE (1 << BNX2X_PAGE_SHIFT)\n#define BNX2X_PAGE_MASK (~(BNX2X_PAGE_SIZE - 1))\n#define BNX2X_PAGE_ALIGN(addr) ((addr + BNX2X_PAGE_SIZE - 1) & BNX2X_PAGE_MASK)\n\n#if BNX2X_PAGE_SIZE != 4096\n#error Page sizes other than 4KB are unsupported!\n#endif\n\n#define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))\n#define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))\n#define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))\n\n/* dropless fc FW/HW related params */\n#define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)\n#define MAX_AGG_QS(sc) ETH_MAX_AGGREGATION_QUEUES_E1H_E2\n#define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))\n#define FW_PREFETCH_CNT 16U\n#define DROPLESS_FC_HEADROOM 100\n\n#ifndef MCLSHIFT\n#define MCLSHIFT 11\n#endif\n#define MCLBYTES (1 << MCLSHIFT)\n\n#if BNX2X_PAGE_SIZE < 2048\n#define MJUMPAGESIZE MCLBYTES\n#elif BNX2X_PAGE_SIZE <= 8192\n#define MJUMPAGESIZE BNX2X_PAGE_SIZE\n#else\n#define MJUMPAGESIZE (8 * 1024)\n#endif\n#define MJUM9BYTES (9 * 1024)\n#define MJUM16BYTES (16 * 1024)\n\n/*\n * Transmit Buffer Descriptor (tx_bd) definitions*\n */\n/* NUM_TX_PAGES must be a power of 2. */\n#define TOTAL_TX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /* 256 */\n#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) /* 255 */\n\n#define TOTAL_TX_BD(q) (TOTAL_TX_BD_PER_PAGE * q->nb_tx_pages) /* 512 */\n#define USABLE_TX_BD(q) (USABLE_TX_BD_PER_PAGE * q->nb_tx_pages) /* 510 */\n#define MAX_TX_BD(q) (TOTAL_TX_BD(q) - 1) /* 511 */\n\n#define NEXT_TX_BD(x) \\\n\t((((x) & USABLE_TX_BD_PER_PAGE) == \\\n\t (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)\n\n#define TX_BD(x, q) ((x) & MAX_TX_BD(q))\n#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)\n#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)\n\n/*\n * Trigger pending transmits when the number of available BDs is greater\n * than 1/8 of the total number of usable BDs.\n */\n#define BNX2X_TX_CLEANUP_THRESHOLD(q) (USABLE_TX_BD(q) / 8)\n#define BNX2X_TX_TIMEOUT 5\n\n/*\n * Receive Buffer Descriptor (rx_bd) definitions*\n */\n//#define NUM_RX_PAGES 1\n#define TOTAL_RX_BD_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(struct eth_rx_bd)) /* 512 */\n#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 2) /* 510 */\n#define RX_BD_PER_PAGE_MASK (TOTAL_RX_BD_PER_PAGE - 1) /* 511 */\n#define TOTAL_RX_BD(q) (TOTAL_RX_BD_PER_PAGE * q->nb_rx_pages) /* 512 */\n#define USABLE_RX_BD(q) (USABLE_RX_BD_PER_PAGE * q->nb_rx_pages) /* 510 */\n#define MAX_RX_BD(q) (TOTAL_RX_BD(q) - 1) /* 511 */\n#define RX_BD_NEXT_PAGE_DESC_CNT 2\n\n#define NEXT_RX_BD(x) \\\n\t((((x) & RX_BD_PER_PAGE_MASK) == \\\n\t(USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 3 : (x) + 1)\n\n/* x & 0x3ff */\n#define RX_BD(x, q) ((x) & MAX_RX_BD(q))\n#define RX_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)\n#define RX_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)\n\n/*\n * Receive Completion Queue definitions*\n */\n//#define NUM_RCQ_PAGES (NUM_RX_PAGES * 4)\n#define TOTAL_RCQ_ENTRIES_PER_PAGE (BNX2X_PAGE_SIZE / sizeof(union eth_rx_cqe)) /* 128 */\n#define USABLE_RCQ_ENTRIES_PER_PAGE (TOTAL_RCQ_ENTRIES_PER_PAGE - 1) /* 127 */\n#define TOTAL_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 512 */\n#define USABLE_RCQ_ENTRIES(q) (USABLE_RCQ_ENTRIES_PER_PAGE * q->nb_cq_pages) /* 508 */\n#define MAX_RCQ_ENTRIES(q) (TOTAL_RCQ_ENTRIES(q) - 1) /* 511 */\n#define RCQ_NEXT_PAGE_DESC_CNT 1\n\n#define NEXT_RCQ_IDX(x) \\\n\t((((x) & USABLE_RCQ_ENTRIES_PER_PAGE) == \\\n\t(USABLE_RCQ_ENTRIES_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)\n\n#define CQE_BD_REL \\\n\t(sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))\n\n#define RCQ_BD_PAGES(q) \\\n\t(q->nb_rx_pages * CQE_BD_REL)\n\n#define RCQ_ENTRY(x, q) ((x) & MAX_RCQ_ENTRIES(q))\n#define RCQ_PAGE(x) (((x) & ~USABLE_RCQ_ENTRIES_PER_PAGE) >> 7)\n#define RCQ_IDX(x) ((x) & USABLE_RCQ_ENTRIES_PER_PAGE)\n\n/*\n * dropless fc calculations for BDs\n * Number of BDs should be as number of buffers in BRB:\n * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT\n * \"next\" elements on each page\n */\n#define NUM_BD_REQ(sc) \\\n\tBRB_SIZE(sc)\n#define NUM_BD_PG_REQ(sc) \\\n\t((NUM_BD_REQ(sc) + USABLE_RX_BD_PER_PAGE - 1) / USABLE_RX_BD_PER_PAGE)\n#define BD_TH_LO(sc) \\\n\t(NUM_BD_REQ(sc) +\t\t\t \\\n\t NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \\\n\t FW_DROP_LEVEL(sc))\n#define BD_TH_HI(sc) \\\n\t(BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)\n#define MIN_RX_AVAIL(sc)\t\t\t\t\\\n\t((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)\n\n/*\n * dropless fc calculations for RCQs\n * Number of RCQs should be as number of buffers in BRB:\n * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT\n * \"next\" elements on each page\n */\n#define NUM_RCQ_REQ(sc) \\\n BRB_SIZE(sc)\n#define NUM_RCQ_PG_REQ(sc) \\\n ((NUM_RCQ_REQ(sc) + USABLE_RCQ_ENTRIES_PER_PAGE - 1) / USABLE_RCQ_ENTRIES_PER_PAGE)\n#define RCQ_TH_LO(sc) \\\n (NUM_RCQ_REQ(sc) + \\\n NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \\\n FW_DROP_LEVEL(sc))\n#define RCQ_TH_HI(sc) \\\n (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)\n\n/* Load / Unload modes */\n#define LOAD_NORMAL 0\n#define LOAD_OPEN 1\n#define LOAD_DIAG 2\n#define LOAD_LOOPBACK_EXT 3\n#define UNLOAD_NORMAL 0\n#define UNLOAD_CLOSE 1\n#define UNLOAD_RECOVERY 2\n\n/* Some constants... */\n//#define MAX_PATH_NUM 2\n//#define E2_MAX_NUM_OF_VFS 64\n//#define E1H_FUNC_MAX 8\n//#define E2_FUNC_MAX 4 /* per path */\n#define MAX_VNIC_NUM 4\n#define MAX_FUNC_NUM 8 /* common to all chips */\n//#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */\n#define MAX_RSS_CHAINS 16 /* a constant for HW limit */\n#define MAX_MSI_VECTOR 8 /* a constant for HW limit */\n\n#define ILT_NUM_PAGE_ENTRIES 3072\n/*\n * 57711 we use whole table since we have 8 functions.\n * 57712 we have only 4 functions, but use same size per func, so only half\n * of the table is used.\n */\n#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)\n#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)\n/*\n * the phys address is shifted right 12 bits and has an added\n * 1=valid bit added to the 53rd bit\n * then since this is a wide register(TM)\n * we split it into two 32 bit writes\n */\n#define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))\n#define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))\n\n/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */\n#define ETH_HLEN 14\n#define ETH_OVERHEAD (ETH_HLEN + 8 + 8)\n#define ETH_MIN_PACKET_SIZE 60\n#define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */\n#define ETH_MAX_JUMBO_PACKET_SIZE 9600\n/* TCP with Timestamp Option (32) + IPv6 (40) */\n\n/* max supported alignment is 256 (8 shift) */\n#define BNX2X_RX_ALIGN_SHIFT 8\n/* FW uses 2 cache lines alignment for start packet and size */\n#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)\n#define BNX2X_FW_RX_ALIGN_END (1 << BNX2X_RX_ALIGN_SHIFT)\n\n#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)\n\nstruct bnx2x_bar {\n\tvoid *base_addr;\n};\n\n/* Used to manage DMA allocations. */\nstruct bnx2x_dma {\n\tstruct bnx2x_softc *sc;\n\tphys_addr_t paddr;\n\tvoid *vaddr;\n\tint nseg;\n\tchar msg[RTE_MEMZONE_NAMESIZE - 6];\n};\n\n/* attn group wiring */\n#define MAX_DYNAMIC_ATTN_GRPS 8\n\nstruct attn_route {\n\tuint32_t sig[5];\n};\n\nstruct iro {\n\tuint32_t base;\n\tuint16_t m1;\n\tuint16_t m2;\n\tuint16_t m3;\n\tuint16_t size;\n};\n\nunion bnx2x_host_hc_status_block {\n\t/* pointer to fp status block e2 */\n\tstruct host_hc_status_block_e2 *e2_sb;\n\t/* pointer to fp status block e1x */\n\tstruct host_hc_status_block_e1x *e1x_sb;\n};\n\nunion bnx2x_db_prod {\n\tstruct doorbell_set_prod data;\n\tuint32_t raw;\n};\n\nstruct bnx2x_sw_tx_bd {\n\tstruct mbuf *m;\n\tuint16_t first_bd;\n\tuint8_t flags;\n/* set on the first BD descriptor when there is a split BD */\n#define BNX2X_TSO_SPLIT_BD (1 << 0)\n};\n\n/*\n * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN\n * instances of the fastpath structure when using multiple queues.\n */\nstruct bnx2x_fastpath {\n\t/* pointer back to parent structure */\n\tstruct bnx2x_softc *sc;\n\n\t/* status block */\n\tstruct bnx2x_dma sb_dma;\n\tunion bnx2x_host_hc_status_block status_block;\n\n\tphys_addr_t tx_desc_mapping;\n\n\tphys_addr_t rx_desc_mapping;\n\tphys_addr_t rx_comp_mapping;\n\n\tuint16_t *sb_index_values;\n\tuint16_t *sb_running_index;\n\tuint32_t ustorm_rx_prods_offset;\n\n\tuint8_t igu_sb_id; /* status block number in HW */\n\tuint8_t fw_sb_id; /* status block number in FW */\n\n\tuint32_t rx_buf_size;\n\tint mbuf_alloc_size;\n\n\tint state;\n#define BNX2X_FP_STATE_CLOSED 0x01\n#define BNX2X_FP_STATE_IRQ 0x02\n#define BNX2X_FP_STATE_OPENING 0x04\n#define BNX2X_FP_STATE_OPEN 0x08\n#define BNX2X_FP_STATE_HALTING 0x10\n#define BNX2X_FP_STATE_HALTED 0x20\n\n\t/* reference back to this fastpath queue number */\n\tuint8_t index; /* this is also the 'cid' */\n#define FP_IDX(fp) (fp->index)\n\n\t/* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */\n\tuint8_t cl_id;\n#define FP_CL_ID(fp) (fp->cl_id)\n\tuint8_t cl_qzone_id;\n\n\tuint16_t fp_hc_idx;\n\n\tunion bnx2x_db_prod tx_db;\n\n\tstruct tstorm_per_queue_stats old_tclient;\n\tstruct ustorm_per_queue_stats old_uclient;\n\tstruct xstorm_per_queue_stats old_xclient;\n\tstruct bnx2x_eth_q_stats eth_q_stats;\n\tstruct bnx2x_eth_q_stats_old eth_q_stats_old;\n\n\t/* Pointer to the receive consumer in the status block */\n\tuint16_t *rx_cq_cons_sb;\n\n\t/* Pointer to the transmit consumer in the status block */\n\tuint16_t *tx_cons_sb;\n\n\t/* transmit timeout until chip reset */\n\tint watchdog_timer;\n\n}; /* struct bnx2x_fastpath */\n\n#define BNX2X_MAX_NUM_OF_VFS 64\n#define BNX2X_VF_ID_INVALID 0xFF\n\n/* maximum number of fast-path interrupt contexts */\n#define FP_SB_MAX_E1x 16\n#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2\n\nunion cdu_context {\n struct eth_context eth;\n char pad[1024];\n};\n\n/* CDU host DB constants */\n#define CDU_ILT_PAGE_SZ_HW 2\n#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */\n#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))\n\n#define CNIC_ISCSI_CID_MAX 256\n#define CNIC_FCOE_CID_MAX 2048\n#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)\n#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)\n\n#define QM_ILT_PAGE_SZ_HW 0\n#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */\n#define QM_CID_ROUND 1024\n\n/* TM (timers) host DB constants */\n#define TM_ILT_PAGE_SZ_HW 0\n#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */\n/*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */\n#define TM_CONN_NUM 1024\n#define TM_ILT_SZ (8 * TM_CONN_NUM)\n#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)\n\n/* SRC (Searcher) host DB constants */\n#define SRC_ILT_PAGE_SZ_HW 0\n#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */\n#define SRC_HASH_BITS 10\n#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */\n#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)\n#define SRC_T2_SZ SRC_ILT_SZ\n#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)\n\nstruct hw_context {\n struct bnx2x_dma vcxt_dma;\n union cdu_context *vcxt;\n //phys_addr_t cxt_mapping;\n size_t size;\n};\n\n#define SM_RX_ID 0\n#define SM_TX_ID 1\n\n/* defines for multiple tx priority indices */\n#define FIRST_TX_ONLY_COS_INDEX 1\n#define FIRST_TX_COS_INDEX 0\n\n#define CID_TO_FP(cid, sc) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(sc))\n\n#define HC_INDEX_ETH_RX_CQ_CONS 1\n#define HC_INDEX_OOO_TX_CQ_CONS 4\n#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5\n#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6\n#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7\n#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0\n\n/* congestion management fairness mode */\n#define CMNG_FNS_NONE 0\n#define CMNG_FNS_MINMAX 1\n\n/* CMNG constants, as derived from system spec calculations */\n/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */\n#define DEF_MIN_RATE 100\n/* resolution of the rate shaping timer - 400 usec */\n#define RS_PERIODIC_TIMEOUT_USEC 400\n/* number of bytes in single QM arbitration cycle -\n * coefficient for calculating the fairness timer */\n#define QM_ARB_BYTES 160000\n/* resolution of Min algorithm 1:100 */\n#define MIN_RES 100\n/* how many bytes above threshold for the minimal credit of Min algorithm*/\n#define MIN_ABOVE_THRESH 32768\n/* fairness algorithm integration time coefficient -\n * for calculating the actual Tfair */\n#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)\n/* memory of fairness algorithm - 2 cycles */\n#define FAIR_MEM 2\n\n#define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */\n#define HC_SEG_ACCESS_ATTN 4\n#define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */\n\n/*\n * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is\n * control by the number of fast-path status blocks supported by the\n * device (HW/FW). Each fast-path status block (FP-SB) aka non-default\n * status block represents an independent interrupts context that can\n * serve a regular L2 networking queue. However special L2 queues such\n * as the FCoE queue do not require a FP-SB and other components like\n * the CNIC may consume FP-SB reducing the number of possible L2 queues\n *\n * If the maximum number of FP-SB available is X then:\n * a. If CNIC is supported it consumes 1 FP-SB thus the max number of\n * regular L2 queues is Y=X-1\n * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)\n * c. If the FCoE L2 queue is supported the actual number of L2 queues\n * is Y+1\n * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for\n * slow-path interrupts) or Y+2 if CNIC is supported (one additional\n * FP interrupt context for the CNIC).\n * e. The number of HW context (CID count) is always X or X+1 if FCoE\n * L2 queue is supported. the cid for the FCoE L2 queue is always X.\n *\n * So this is quite simple for now as no ULPs are supported yet. :-)\n */\n#define BNX2X_NUM_QUEUES(sc) ((sc)->num_queues)\n#define BNX2X_NUM_ETH_QUEUES(sc) BNX2X_NUM_QUEUES(sc)\n#define BNX2X_NUM_NON_CNIC_QUEUES(sc) BNX2X_NUM_QUEUES(sc)\n#define BNX2X_NUM_RX_QUEUES(sc) BNX2X_NUM_QUEUES(sc)\n\n#define FOR_EACH_QUEUE(sc, var) \\\n for ((var) = 0; (var) < BNX2X_NUM_QUEUES(sc); (var)++)\n\n#define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \\\n for ((var) = 1; (var) < BNX2X_NUM_QUEUES(sc); (var)++)\n\n#define FOR_EACH_ETH_QUEUE(sc, var) \\\n for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)\n\n#define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \\\n for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(sc); (var)++)\n\n#define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \\\n for ((var) = 0; (var) < (sc)->max_cos; (var)++)\n\n#define FOR_EACH_CNIC_QUEUE(sc, var) \\\n for ((var) = BNX2X_NUM_ETH_QUEUES(sc); \\\n\t (var) < BNX2X_NUM_QUEUES(sc); \\\n\t (var)++)\n\nenum {\n OOO_IDX_OFFSET,\n FCOE_IDX_OFFSET,\n FWD_IDX_OFFSET,\n};\n\n#define FCOE_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)\n#define bnx2x_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])\n#define bnx2x_fcoe(sc, var) (bnx2x_fcoe_fp(sc)->var)\n#define bnx2x_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])\n#define bnx2x_fcoe_sp_obj(sc, var) (bnx2x_fcoe_inner_sp_obj(sc)->var)\n#define bnx2x_fcoe_tx(sc, var) (bnx2x_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)\n\n#define OOO_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)\n#define bnx2x_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])\n#define bnx2x_ooo(sc, var) (bnx2x_ooo_fp(sc)->var)\n#define bnx2x_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])\n#define bnx2x_ooo_sp_obj(sc, var) (bnx2x_ooo_inner_sp_obj(sc)->var)\n\n#define FWD_IDX(sc) (BNX2X_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)\n#define bnx2x_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])\n#define bnx2x_fwd(sc, var) (bnx2x_fwd_fp(sc)->var)\n#define bnx2x_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])\n#define bnx2x_fwd_sp_obj(sc, var) (bnx2x_fwd_inner_sp_obj(sc)->var)\n#define bnx2x_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])\n\n#define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->sc))\n#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))\n#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))\n#define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))\n#define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))\n#define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))\n#define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))\n\nenum {\n BNX2X_PORT_QUERY_IDX,\n BNX2X_PF_QUERY_IDX,\n BNX2X_FCOE_QUERY_IDX,\n BNX2X_FIRST_QUEUE_QUERY_IDX,\n};\n\nstruct bnx2x_fw_stats_req {\n struct stats_query_header hdr;\n struct stats_query_entry query[FP_SB_MAX_E1x +\n\t\t\t\t BNX2X_FIRST_QUEUE_QUERY_IDX];\n};\n\nstruct bnx2x_fw_stats_data {\n struct stats_counter storm_counters;\n struct per_port_stats port;\n struct per_pf_stats pf;\n struct per_queue_stats queue_stats[1];\n};\n\n/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */\n#define BNX2X_IGU_STAS_MSG_VF_CNT 64\n#define BNX2X_IGU_STAS_MSG_PF_CNT 4\n\n#define MAX_DMAE_C 8\n\n/*\n * This is the slowpath data structure. It is mapped into non-paged memory\n * so that the hardware can access it's contents directly and must be page\n * aligned.\n */\nstruct bnx2x_slowpath {\n\n /* used by the DMAE command executer */\n struct dmae_command dmae[MAX_DMAE_C];\n\n /* statistics completion */\n uint32_t stats_comp;\n\n /* firmware defined statistics blocks */\n union mac_stats mac_stats;\n struct nig_stats nig_stats;\n struct host_port_stats port_stats;\n struct host_func_stats func_stats;\n\n /* DMAE completion value and data source/sink */\n uint32_t wb_comp;\n uint32_t wb_data[4];\n\n union {\n\tstruct mac_configuration_cmd e1x;\n\tstruct eth_classify_rules_ramrod_data e2;\n } mac_rdata;\n\n union {\n\tstruct tstorm_eth_mac_filter_config e1x;\n\tstruct eth_filter_rules_ramrod_data e2;\n } rx_mode_rdata;\n\n struct eth_rss_update_ramrod_data rss_rdata;\n\n union {\n\tstruct mac_configuration_cmd e1;\n\tstruct eth_multicast_rules_ramrod_data e2;\n } mcast_rdata;\n\n union {\n\tstruct function_start_data func_start;\n\tstruct flow_control_configuration pfc_config; /* for DCBX ramrod */\n } func_rdata;\n\n /* Queue State related ramrods */\n union {\n\tstruct client_init_ramrod_data init_data;\n\tstruct client_update_ramrod_data update_data;\n } q_rdata;\n\n /*\n * AFEX ramrod can not be a part of func_rdata union because these\n * events might arrive in parallel to other events from func_rdata.\n * If they were defined in the same union the data can get corrupted.\n */\n struct afex_vif_list_ramrod_data func_afex_rdata;\n\n union drv_info_to_mcp drv_info_to_mcp;\n}; /* struct bnx2x_slowpath */\n\n/*\n * Port specifc data structure.\n */\nstruct bnx2x_port {\n /*\n * Port Management Function (for 57711E only).\n * When this field is set the driver instance is\n * responsible for managing port specifc\n * configurations such as handling link attentions.\n */\n uint32_t pmf;\n\n /* Ethernet maximum transmission unit. */\n uint16_t ether_mtu;\n\n uint32_t link_config[ELINK_LINK_CONFIG_SIZE];\n\n uint32_t ext_phy_config;\n\n /* Port feature config.*/\n uint32_t config;\n\n /* Defines the features supported by the PHY. */\n uint32_t supported[ELINK_LINK_CONFIG_SIZE];\n\n /* Defines the features advertised by the PHY. */\n uint32_t advertising[ELINK_LINK_CONFIG_SIZE];\n#define ADVERTISED_10baseT_Half (1 << 1)\n#define ADVERTISED_10baseT_Full (1 << 2)\n#define ADVERTISED_100baseT_Half (1 << 3)\n#define ADVERTISED_100baseT_Full (1 << 4)\n#define ADVERTISED_1000baseT_Half (1 << 5)\n#define ADVERTISED_1000baseT_Full (1 << 6)\n#define ADVERTISED_TP (1 << 7)\n#define ADVERTISED_FIBRE (1 << 8)\n#define ADVERTISED_Autoneg (1 << 9)\n#define ADVERTISED_Asym_Pause (1 << 10)\n#define ADVERTISED_Pause (1 << 11)\n#define ADVERTISED_2500baseX_Full (1 << 15)\n#define ADVERTISED_10000baseT_Full (1 << 16)\n\n uint32_t phy_addr;\n\n /*\n * MCP scratchpad address for port specific statistics.\n * The device is responsible for writing statistcss\n * back to the MCP for use with management firmware such\n * as UMP/NC-SI.\n */\n uint32_t port_stx;\n\n struct nig_stats old_nig_stats;\n}; /* struct bnx2x_port */\n\nstruct bnx2x_mf_info {\n\tuint32_t mf_config[E1HVN_MAX];\n\n\tuint32_t vnics_per_port; /* 1, 2 or 4 */\n\tuint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */\n\tuint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */\n\n#define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)\n#define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)\n#define VNICS_PER_PATH(sc) \\\n\t((sc)->devinfo.mf_info.vnics_per_port * \\\n\t ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))\n\n\tuint8_t min_bw[MAX_VNIC_NUM];\n\tuint8_t max_bw[MAX_VNIC_NUM];\n\n\tuint16_t ext_id; /* vnic outer vlan or VIF ID */\n#define VALID_OVLAN(ovlan) ((ovlan) <= 4096)\n#define INVALID_VIF_ID 0xFFFF\n#define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)\n#define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)\n\n\tuint16_t default_vlan;\n#define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)\n\n\tuint8_t niv_allowed_priorities;\n#define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)\n\n\tuint8_t niv_default_cos;\n#define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)\n\n\tuint8_t niv_mba_enabled;\n\n\tenum mf_cfg_afex_vlan_mode afex_vlan_mode;\n#define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)\n\tint afex_def_vlan_tag;\n\tuint32_t pending_max;\n\n\tuint16_t flags;\n#define MF_INFO_VALID_MAC 0x0001\n\n\tuint16_t mf_ov;\n\tuint8_t mf_mode; /* Switch-Dependent or Switch-Independent */\n#define IS_MF(sc) \\\n\t(IS_MULTI_VNIC(sc) && \\\n\t ((sc)->devinfo.mf_info.mf_mode != 0))\n#define IS_MF_SD(sc) \\\n\t(IS_MULTI_VNIC(sc) && \\\n\t ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))\n#define IS_MF_SI(sc) \\\n\t(IS_MULTI_VNIC(sc) && \\\n\t ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))\n#define IS_MF_AFEX(sc) \\\n\t(IS_MULTI_VNIC(sc) && \\\n\t ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))\n#define IS_MF_SD_MODE(sc) IS_MF_SD(sc)\n#define IS_MF_SI_MODE(sc) IS_MF_SI(sc)\n#define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)\n\n\tuint32_t mf_protos_supported;\n\t#define MF_PROTO_SUPPORT_ETHERNET 0x1\n\t#define MF_PROTO_SUPPORT_ISCSI 0x2\n\t#define MF_PROTO_SUPPORT_FCOE 0x4\n}; /* struct bnx2x_mf_info */\n\n/* Device information data structure. */\nstruct bnx2x_devinfo {\n\t/* PCIe info */\n\tuint16_t vendor_id;\n\tuint16_t device_id;\n\tuint16_t subvendor_id;\n\tuint16_t subdevice_id;\n\n\t/*\n\t * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'\n\t * C = Chip Number (bits 16-31)\n\t * R = Chip Revision (bits 12-15)\n\t * M = Chip Metal (bits 4-11)\n\t * B = Chip Bond ID (bits 0-3)\n\t */\n\tuint32_t chip_id;\n#define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)\n#define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)\n/* device ids */\n#define CHIP_NUM_57711 0x164f\n#define CHIP_NUM_57711E 0x1650\n#define CHIP_NUM_57712 0x1662\n#define CHIP_NUM_57712_MF 0x1663\n#define CHIP_NUM_57712_VF 0x166f\n#define CHIP_NUM_57800 0x168a\n#define CHIP_NUM_57800_MF 0x16a5\n#define CHIP_NUM_57800_VF 0x16a9\n#define CHIP_NUM_57810 0x168e\n#define CHIP_NUM_57810_MF 0x16ae\n#define CHIP_NUM_57810_VF 0x16af\n#define CHIP_NUM_57811 0x163d\n#define CHIP_NUM_57811_MF 0x163e\n#define CHIP_NUM_57811_VF 0x163f\n#define CHIP_NUM_57840_OBS 0x168d\n#define CHIP_NUM_57840_OBS_MF 0x16ab\n#define CHIP_NUM_57840_4_10 0x16a1\n#define CHIP_NUM_57840_2_20 0x16a2\n#define CHIP_NUM_57840_MF 0x16a4\n#define CHIP_NUM_57840_VF 0x16ad\n\n#define CHIP_REV_SHIFT 12\n#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)\n#define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)\n\n#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)\n#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)\n#define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)\n\n#define CHIP_REV_IS_SLOW(sc) \\\n\t(CHIP_REV(sc) > 0x00005000)\n#define CHIP_REV_IS_FPGA(sc) \\\n\t(CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))\n#define CHIP_REV_IS_EMUL(sc) \\\n\t(CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))\n#define CHIP_REV_IS_ASIC(sc) \\\n\t(!CHIP_REV_IS_SLOW(sc))\n\n#define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)\n#define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)\n\n#define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)\n#define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)\n#define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \\\n\t\t\t (CHIP_IS_57711E(sc)))\n#define CHIP_IS_E1x(sc) CHIP_IS_E1H(sc)\n\n#define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)\n#define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)\n#define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)\n#define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \\\n\t\t\t CHIP_IS_57712_MF(sc))\n\n#define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)\n#define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)\n#define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)\n#define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)\n#define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)\n#define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)\n#define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)\n#define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)\n#define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)\n#define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \\\n\t\t\t (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \\\n\t\t\t (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))\n#define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \\\n\t\t\t (CHIP_NUM(sc) == CHIP_NUM_57840_MF))\n#define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)\n\n#define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \\\n\t\t\t CHIP_IS_57800_MF(sc) || \\\n\t\t\t CHIP_IS_57800_VF(sc) || \\\n\t\t\t CHIP_IS_57810(sc) || \\\n\t\t\t CHIP_IS_57810_MF(sc) || \\\n\t\t\t CHIP_IS_57810_VF(sc) || \\\n\t\t\t CHIP_IS_57811(sc) || \\\n\t\t\t CHIP_IS_57811_MF(sc) || \\\n\t\t\t CHIP_IS_57811_VF(sc) || \\\n\t\t\t CHIP_IS_57840(sc) || \\\n\t\t\t CHIP_IS_57840_MF(sc) || \\\n\t\t\t CHIP_IS_57840_VF(sc))\n#define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \\\n\t\t\t (CHIP_REV(sc) == CHIP_REV_Ax))\n#define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \\\n\t\t\t (CHIP_REV(sc) == CHIP_REV_Bx))\n\n#define USES_WARPCORE(sc) (CHIP_IS_E3(sc))\n#define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \\\n\t\t\t CHIP_IS_E3(sc))\n\n#define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \\\n\t\t\t CHIP_IS_57712_MF(sc) || \\\n\t\t\t CHIP_IS_E3(sc))\n\n#define IS_VF(sc) ((sc)->flags & BNX2X_IS_VF_FLAG)\n#define IS_PF(sc) (!IS_VF(sc))\n\n/*\n * This define is used in two main places:\n * 1. In the early stages of nic_load, to know if to configure Parser/Searcher\n * to nic-only mode or to offload mode. Offload mode is configured if either\n * the chip is E1x (where NIC_MODE register is not applicable), or if cnic\n * already registered for this port (which means that the user wants storage\n * services).\n * 2. During cnic-related load, to know if offload mode is already configured\n * in the HW or needs to be configrued. Since the transition from nic-mode to\n * offload-mode in HW causes traffic coruption, nic-mode is configured only\n * in ports on which storage services where never requested.\n */\n#define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))\n\n\tuint8_t chip_port_mode;\n#define CHIP_4_PORT_MODE 0x0\n#define CHIP_2_PORT_MODE 0x1\n#define CHIP_PORT_MODE_NONE 0x2\n#define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)\n#define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)\n\n\tuint8_t int_block;\n#define INT_BLOCK_HC 0\n#define INT_BLOCK_IGU 1\n#define INT_BLOCK_MODE_NORMAL 0\n#define INT_BLOCK_MODE_BW_COMP 2\n#define CHIP_INT_MODE_IS_NBC(sc) \\\n\t(!CHIP_IS_E1x(sc) && \\\n\t !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))\n#define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))\n\n\tuint32_t shmem_base;\n\tuint32_t shmem2_base;\n\tuint32_t bc_ver;\n\tchar bc_ver_str[32];\n\tuint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */\n\tstruct bnx2x_mf_info mf_info;\n\n\tuint32_t flash_size;\n#define NVRAM_1MB_SIZE 0x20000\n#define NVRAM_TIMEOUT_COUNT 30000\n#define NVRAM_PAGE_SIZE 256\n\n\t/* PCIe capability information */\n\tuint32_t pcie_cap_flags;\n#define BNX2X_PM_CAPABLE_FLAG 0x00000001\n#define BNX2X_PCIE_CAPABLE_FLAG 0x00000002\n#define BNX2X_MSI_CAPABLE_FLAG 0x00000004\n#define BNX2X_MSIX_CAPABLE_FLAG 0x00000008\n\tuint16_t pcie_pm_cap_reg;\n\tuint16_t pcie_link_width;\n\tuint16_t pcie_link_speed;\n\tuint16_t pcie_msi_cap_reg;\n\tuint16_t pcie_msix_cap_reg;\n\n\t/* device configuration read from bootcode shared memory */\n\tuint32_t hw_config;\n\tuint32_t hw_config2;\n}; /* struct bnx2x_devinfo */\n\nstruct bnx2x_sp_objs {\n\tstruct ecore_vlan_mac_obj mac_obj; /* MACs object */\n\tstruct ecore_queue_sp_obj q_obj; /* Queue State object */\n}; /* struct bnx2x_sp_objs */\n\n/*\n * Data that will be used to create a link report message. We will keep the\n * data used for the last link report in order to prevent reporting the same\n * link parameters twice.\n */\nstruct bnx2x_link_report_data {\n\tuint16_t line_speed; /* Effective line speed */\n\tunsigned long link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */\n};\n\nenum {\n\tBNX2X_LINK_REPORT_FULL_DUPLEX,\n\tBNX2X_LINK_REPORT_LINK_DOWN,\n\tBNX2X_LINK_REPORT_RX_FC_ON,\n\tBNX2X_LINK_REPORT_TX_FC_ON\n};\n\n#define BNX2X_RX_CHAIN_PAGE_SZ BNX2X_PAGE_SIZE\n\nstruct bnx2x_pci_cap {\n\tstruct bnx2x_pci_cap *next;\n\tuint16_t id;\n\tuint16_t type;\n\tuint16_t addr;\n};\n\nstruct bnx2x_vfdb;\n\n/* Top level device private data structure. */\nstruct bnx2x_softc {\n\n\tvoid **rx_queues;\n\tvoid **tx_queues;\n\tuint32_t max_tx_queues;\n\tuint32_t max_rx_queues;\n\tconst struct rte_pci_device *pci_dev;\n\tuint32_t pci_val;\n\tstruct bnx2x_pci_cap *pci_caps;\n#define BNX2X_INTRS_POLL_PERIOD 1\n\n\tvoid *firmware;\n\tuint64_t fw_len;\n\n\t/* MAC address operations */\n\tstruct bnx2x_mac_ops mac_ops;\n\n\t/* structures for VF mbox/response/bulletin */\n\tstruct bnx2x_vf_mbx_msg\t*vf2pf_mbox;\n\tstruct bnx2x_dma\t\tvf2pf_mbox_mapping;\n\tstruct vf_acquire_resp_tlv acquire_resp;\n\tstruct bnx2x_vf_bulletin\t*pf2vf_bulletin;\n\tstruct bnx2x_dma\t\tpf2vf_bulletin_mapping;\n\tstruct bnx2x_vf_bulletin\told_bulletin;\n\n\tint media;\n\n\tint state; /* device state */\n#define BNX2X_STATE_CLOSED 0x0000\n#define BNX2X_STATE_OPENING_WAITING_LOAD 0x1000\n#define BNX2X_STATE_OPENING_WAITING_PORT 0x2000\n#define BNX2X_STATE_OPEN 0x3000\n#define BNX2X_STATE_CLOSING_WAITING_HALT 0x4000\n#define BNX2X_STATE_CLOSING_WAITING_DELETE 0x5000\n#define BNX2X_STATE_CLOSING_WAITING_UNLOAD 0x6000\n#define BNX2X_STATE_DISABLED 0xD000\n#define BNX2X_STATE_DIAG 0xE000\n#define BNX2X_STATE_ERROR 0xF000\n\n\tint flags;\n#define BNX2X_ONE_PORT_FLAG 0x1\n#define BNX2X_NO_FCOE_FLAG 0x2\n#define BNX2X_NO_WOL_FLAG 0x4\n#define BNX2X_NO_MCP_FLAG 0x8\n#define BNX2X_NO_ISCSI_OOO_FLAG 0x10\n#define BNX2X_NO_ISCSI_FLAG 0x20\n#define BNX2X_MF_FUNC_DIS 0x40\n#define BNX2X_TX_SWITCHING 0x80\n#define BNX2X_IS_VF_FLAG 0x100\n\n#define BNX2X_ONE_PORT(sc) (sc->flags & BNX2X_ONE_PORT_FLAG)\n#define BNX2X_NOFCOE(sc) (sc->flags & BNX2X_NO_FCOE_FLAG)\n#define BNX2X_NOMCP(sc) (sc->flags & BNX2X_NO_MCP_FLAG)\n\n#define MAX_BARS 5\n\tstruct bnx2x_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */\n\n\tuint16_t doorbell_size;\n\n\t/* periodic timer callout */\n#define PERIODIC_STOP 0\n#define PERIODIC_GO 1\n\tvolatile unsigned long periodic_flags;\n\n\tstruct bnx2x_fastpath fp[MAX_RSS_CHAINS];\n\tstruct bnx2x_sp_objs sp_objs[MAX_RSS_CHAINS];\n\n\tuint8_t unit; /* driver instance number */\n\n\tint pcie_bus; /* PCIe bus number */\n\tint pcie_device; /* PCIe device/slot number */\n\tint pcie_func; /* PCIe function number */\n\n\tuint8_t pfunc_rel; /* function relative */\n\tuint8_t pfunc_abs; /* function absolute */\n\tuint8_t path_id; /* function absolute */\n#define SC_PATH(sc) (sc->path_id)\n#define SC_PORT(sc) (sc->pfunc_rel & 1)\n#define SC_FUNC(sc) (sc->pfunc_rel)\n#define SC_ABS_FUNC(sc) (sc->pfunc_abs)\n#define SC_VN(sc) (sc->pfunc_rel >> 1)\n#define SC_L_ID(sc) (SC_VN(sc) << 2)\n#define PORT_ID(sc) SC_PORT(sc)\n#define PATH_ID(sc) SC_PATH(sc)\n#define VNIC_ID(sc) SC_VN(sc)\n#define FUNC_ID(sc) SC_FUNC(sc)\n#define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)\n#define SC_FW_MB_IDX_VN(sc, vn) \\\n\t(SC_PORT(sc) + (vn) * \\\n\t ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))\n#define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))\n\n\tint if_capen; /* enabled interface capabilities */\n\n\tstruct bnx2x_devinfo devinfo;\n\tchar fw_ver_str[32];\n\tchar mf_mode_str[32];\n\tchar pci_link_str[32];\n\n\tstruct iro *iro_array;\n\n\tint dmae_ready;\n#define DMAE_READY(sc) (sc->dmae_ready)\n\n\tstruct ecore_credit_pool_obj vlans_pool;\n\tstruct ecore_credit_pool_obj macs_pool;\n\tstruct ecore_rx_mode_obj rx_mode_obj;\n\tstruct ecore_mcast_obj mcast_obj;\n\tstruct ecore_rss_config_obj rss_conf_obj;\n\tstruct ecore_func_sp_obj func_obj;\n\n\tuint16_t fw_seq;\n\tuint16_t fw_drv_pulse_wr_seq;\n\tuint32_t func_stx;\n\n\tstruct elink_params link_params;\n\tstruct elink_vars link_vars;\n\tuint32_t link_cnt;\n\tstruct bnx2x_link_report_data last_reported_link;\n\tchar mac_addr_str[32];\n\n\tuint32_t tx_ring_size;\n\tuint32_t rx_ring_size;\n\tint wol;\n\n\tint is_leader;\n\tint recovery_state;\n#define BNX2X_RECOVERY_DONE 1\n#define BNX2X_RECOVERY_INIT 2\n#define BNX2X_RECOVERY_WAIT 3\n#define BNX2X_RECOVERY_FAILED 4\n#define BNX2X_RECOVERY_NIC_LOADING 5\n\n\tuint32_t rx_mode;\n#define BNX2X_RX_MODE_NONE 0\n#define BNX2X_RX_MODE_NORMAL 1\n#define BNX2X_RX_MODE_ALLMULTI 2\n#define BNX2X_RX_MODE_PROMISC 3\n#define BNX2X_MAX_MULTICAST 64\n\n\tstruct bnx2x_port port;\n\n\tstruct cmng_init cmng;\n\n\t/* user configs */\n\tuint8_t num_queues;\n\tint hc_rx_ticks;\n\tint hc_tx_ticks;\n\tuint32_t rx_budget;\n\tint interrupt_mode;\n#define INTR_MODE_INTX 0\n#define INTR_MODE_MSI 1\n#define INTR_MODE_MSIX 2\n#define INTR_MODE_SINGLE_MSIX 3\n\tint udp_rss;\n\n\tuint8_t igu_dsb_id;\n\tuint8_t igu_base_sb;\n\tuint8_t igu_sb_cnt;\n\tuint32_t igu_base_addr;\n\tuint8_t base_fw_ndsb;\n#define DEF_SB_IGU_ID 16\n#define DEF_SB_ID HC_SP_SB_ID\n\n\t/* default status block */\n\tstruct bnx2x_dma def_sb_dma;\n\tstruct host_sp_status_block *def_sb;\n\tuint16_t def_idx;\n\tuint16_t def_att_idx;\n\tuint32_t attn_state;\n\tstruct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];\n\n\t/* general SP events - stats query, cfc delete, etc */\n#define HC_SP_INDEX_ETH_DEF_CONS 3\n\t/* EQ completions */\n#define HC_SP_INDEX_EQ_CONS 7\n\t/* FCoE L2 connection completions */\n#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6\n#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4\n\t/* iSCSI L2 */\n#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5\n#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1\n\n\t/* event queue */\n\tstruct bnx2x_dma eq_dma;\n\tunion event_ring_elem *eq;\n\tuint16_t eq_prod;\n\tuint16_t eq_cons;\n\tuint16_t *eq_cons_sb;\n#define NUM_EQ_PAGES 1 /* must be a power of 2 */\n#define EQ_DESC_CNT_PAGE (BNX2X_PAGE_SIZE / sizeof(union event_ring_elem))\n#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)\n#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)\n#define EQ_DESC_MASK (NUM_EQ_DESC - 1)\n#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)\n\t/* depends on EQ_DESC_CNT_PAGE being a power of 2 */\n#define NEXT_EQ_IDX(x) \\\n\t((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \\\n\t ((x) + 2) : ((x) + 1))\n\t/* depends on the above and on NUM_EQ_PAGES being a power of 2 */\n#define EQ_DESC(x) ((x) & EQ_DESC_MASK)\n\n\t/* slow path */\n\tstruct bnx2x_dma sp_dma;\n\tstruct bnx2x_slowpath *sp;\n\tunsigned long sp_state;\n\n\t/* slow path queue */\n\tstruct bnx2x_dma spq_dma;\n\tstruct eth_spe *spq;\n#define SP_DESC_CNT (BNX2X_PAGE_SIZE / sizeof(struct eth_spe))\n#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)\n#define MAX_SPQ_PENDING 8\n\n\tuint16_t spq_prod_idx;\n\tstruct eth_spe *spq_prod_bd;\n\tstruct eth_spe *spq_last_bd;\n\tuint16_t *dsb_sp_prod;\n\n\tvolatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */\n\tvolatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */\n\n\t/* fw decompression buffer */\n\tstruct bnx2x_dma gz_buf_dma;\n\tvoid *gz_buf;\n\tuint32_t gz_outlen;\n#define GUNZIP_BUF(sc) (sc->gz_buf)\n#define GUNZIP_OUTLEN(sc) (sc->gz_outlen)\n#define GUNZIP_PHYS(sc) (phys_addr_t)(sc->gz_buf_dma.paddr)\n#define FW_BUF_SIZE 0x40000\n\n\tstruct raw_op *init_ops;\n\tuint16_t *init_ops_offsets; /* init block offsets inside init_ops */\n\tuint32_t *init_data; /* data blob, 32 bit granularity */\n\tuint32_t init_mode_flags;\n#define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)\n\t/* PRAM blobs - raw data */\n\tconst uint8_t *tsem_int_table_data;\n\tconst uint8_t *tsem_pram_data;\n\tconst uint8_t *usem_int_table_data;\n\tconst uint8_t *usem_pram_data;\n\tconst uint8_t *xsem_int_table_data;\n\tconst uint8_t *xsem_pram_data;\n\tconst uint8_t *csem_int_table_data;\n\tconst uint8_t *csem_pram_data;\n#define INIT_OPS(sc) (sc->init_ops)\n#define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)\n#define INIT_DATA(sc) (sc->init_data)\n#define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)\n#define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)\n#define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)\n#define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)\n#define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)\n#define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)\n#define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)\n#define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)\n\n#define PHY_FW_VER_LEN\t\t\t20\n\tchar\t\t\tfw_ver[32];\n\n\t/* ILT\n\t * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB\n\t * context size we need 8 ILT entries.\n\t */\n#define ILT_MAX_L2_LINES 8\n\tstruct hw_context context[ILT_MAX_L2_LINES];\n\tstruct ecore_ilt *ilt;\n#define ILT_MAX_LINES 256\n\n\t/* max supported number of RSS queues: IGU SBs minus one for CNIC */\n#define BNX2X_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))\n\t/* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */\n#define BNX2X_L2_MAX_CID(sc) \\\n\t(BNX2X_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))\n#define BNX2X_L2_CID_COUNT(sc) \\\n\t(BNX2X_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))\n#define L2_ILT_LINES(sc) \\\n\t(DIV_ROUND_UP(BNX2X_L2_CID_COUNT(sc), ILT_PAGE_CIDS))\n\n\tint qm_cid_count;\n\n\tuint8_t dropless_fc;\n\n\t/* total number of FW statistics requests */\n\tuint8_t fw_stats_num;\n\t/*\n\t * This is a memory buffer that will contain both statistics ramrod\n\t * request and data.\n\t */\n\tstruct bnx2x_dma fw_stats_dma;\n\t/*\n\t * FW statistics request shortcut (points at the beginning of fw_stats\n\t * buffer).\n\t */\n\tint fw_stats_req_size;\n\tstruct bnx2x_fw_stats_req *fw_stats_req;\n\tphys_addr_t fw_stats_req_mapping;\n\t/*\n\t * FW statistics data shortcut (points at the beginning of fw_stats\n\t * buffer + fw_stats_req_size).\n\t */\n\tint fw_stats_data_size;\n\tstruct bnx2x_fw_stats_data *fw_stats_data;\n\tphys_addr_t fw_stats_data_mapping;\n\n\t/* tracking a pending STAT_QUERY ramrod */\n\tuint16_t stats_pending;\n\t/* number of completed statistics ramrods */\n\tuint16_t stats_comp;\n\tuint16_t stats_counter;\n\tuint8_t stats_init;\n\tint stats_state;\n\n\tstruct bnx2x_eth_stats eth_stats;\n\tstruct host_func_stats func_stats;\n\tstruct bnx2x_eth_stats_old eth_stats_old;\n\tstruct bnx2x_net_stats_old net_stats_old;\n\tstruct bnx2x_fw_port_stats_old fw_stats_old;\n\n\tstruct dmae_command stats_dmae; /* used by dmae command loader */\n\tint executer_idx;\n\n\tint mtu;\n\n\t/* DCB support on/off */\n\tint dcb_state;\n#define BNX2X_DCB_STATE_OFF 0\n#define BNX2X_DCB_STATE_ON 1\n\t/* DCBX engine mode */\n\tint dcbx_enabled;\n#define BNX2X_DCBX_ENABLED_OFF 0\n#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1\n#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2\n#define BNX2X_DCBX_ENABLED_INVALID -1\n\n\tuint8_t cnic_support;\n\tuint8_t cnic_enabled;\n\tuint8_t cnic_loaded;\n#define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */\n#define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */\n#define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */\n\n\t/* multiple tx classes of service */\n\tuint8_t max_cos;\n#define BNX2X_MAX_PRIORITY 8\n\t/* priority to cos mapping */\n\tuint8_t prio_to_cos[BNX2X_MAX_PRIORITY];\n\n\tint panic;\n}; /* struct bnx2x_softc */\n\n/* IOCTL sub-commands for edebug and firmware upgrade */\n#define BNX2X_IOC_RD_NVRAM 1\n#define BNX2X_IOC_WR_NVRAM 2\n#define BNX2X_IOC_STATS_SHOW_NUM 3\n#define BNX2X_IOC_STATS_SHOW_STR 4\n#define BNX2X_IOC_STATS_SHOW_CNT 5\n\nstruct bnx2x_nvram_data {\n uint32_t op; /* ioctl sub-command */\n uint32_t offset;\n uint32_t len;\n uint32_t value[1]; /* variable */\n};\n\nunion bnx2x_stats_show_data {\n uint32_t op; /* ioctl sub-command */\n\n struct {\n\tuint32_t num; /* return number of stats */\n\tuint32_t len; /* length of each string item */\n } desc;\n\n /* variable length... */\n char str[1]; /* holds names of desc.num stats, each desc.len in length */\n\n /* variable length... */\n uint64_t stats[1]; /* holds all stats */\n};\n\n/* function init flags */\n#define FUNC_FLG_RSS 0x0001\n#define FUNC_FLG_STATS 0x0002\n/* FUNC_FLG_UNMATCHED 0x0004 */\n#define FUNC_FLG_SPQ 0x0010\n#define FUNC_FLG_LEADING 0x0020 /* PF only */\n\nstruct bnx2x_func_init_params {\n phys_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */\n phys_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */\n uint16_t func_flgs;\n uint16_t func_id; /* abs function id */\n uint16_t pf_id;\n uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */\n};\n\n/* memory resources reside at BARs 0, 2, 4 */\n/* Run `pciconf -lb` to see mappings */\n#define BAR0 0\n#define BAR1 2\n#define BAR2 4\n\n#ifdef RTE_LIBRTE_BNX2X_DEBUG\nuint8_t bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset);\nuint16_t bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset);\nuint32_t bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset);\n\nvoid bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val);\nvoid bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val);\nvoid bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val);\n#else\n#define bnx2x_reg_write8(sc, offset, val)\\\n\t*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val\n\n#define bnx2x_reg_write16(sc, offset, val)\\\n\t*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val\n\n#define bnx2x_reg_write32(sc, offset, val)\\\n\t*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val\n\n#define bnx2x_reg_read8(sc, offset)\\\n\t(*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)))\n\n#define bnx2x_reg_read16(sc, offset)\\\n\t(*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)))\n\n#define bnx2x_reg_read32(sc, offset)\\\n\t(*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)))\n#endif\n\n#define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset))\n\n#define REG_RD8(sc, offset) bnx2x_reg_read8(sc, (offset))\n#define REG_RD16(sc, offset) bnx2x_reg_read16(sc, (offset))\n#define REG_RD32(sc, offset) bnx2x_reg_read32(sc, (offset))\n\n#define REG_WR8(sc, offset, val) bnx2x_reg_write8(sc, (offset), val)\n#define REG_WR16(sc, offset, val) bnx2x_reg_write16(sc, (offset), val)\n#define REG_WR32(sc, offset, val) bnx2x_reg_write32(sc, (offset), val)\n\n#define REG_RD(sc, offset) REG_RD32(sc, offset)\n#define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)\n\n#define BNX2X_SP(sc, var) (&(sc)->sp->var)\n#define BNX2X_SP_MAPPING(sc, var) \\\n (sc->sp_dma.paddr + offsetof(struct bnx2x_slowpath, var))\n\n#define BNX2X_FP(sc, nr, var) ((sc)->fp[(nr)].var)\n#define BNX2X_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])\n\n#define bnx2x_fp(sc, nr, var) ((sc)->fp[nr].var)\n\n#define REG_RD_DMAE(sc, offset, valp, len32) \\\n do { \\\n\t(void)bnx2x_read_dmae(sc, offset, len32); \\\n\t(void)rte_memcpy(valp, BNX2X_SP(sc, wb_data[0]), (len32) * 4); \\\n } while (0)\n\n#define REG_WR_DMAE(sc, offset, valp, len32) \\\n do { \\\n\t(void)rte_memcpy(BNX2X_SP(sc, wb_data[0]), valp, (len32) * 4); \\\n\t(void)bnx2x_write_dmae(sc, BNX2X_SP_MAPPING(sc, wb_data), offset, len32); \\\n } while (0)\n\n#define REG_WR_DMAE_LEN(sc, offset, valp, len32) \\\n REG_WR_DMAE(sc, offset, valp, len32)\n\n#define REG_RD_DMAE_LEN(sc, offset, valp, len32) \\\n REG_RD_DMAE(sc, offset, valp, len32)\n\n#define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \\\n do { \\\n\t/* if (le32_swap) { */ \\\n\t/* PMD_PWARN_LOG(sc, \"VIRT_WR_DMAE_LEN with le32_swap=1\"); */ \\\n\t/* } */ \\\n\trte_memcpy(GUNZIP_BUF(sc), data, len32 * 4); \\\n\tecore_write_big_buf_wb(sc, addr, len32); \\\n } while (0)\n\n#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */\n#define BNX2X_DB_SHIFT 7 /* 128 bytes */\n#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)\n#error \"Minimum DB doorbell stride is 8\"\n#endif\n#define DPM_TRIGGER_TYPE 0x40\n\n/* Doorbell macro */\n#define BNX2X_DB_WRITE(db_bar, val) \\\n\t*((volatile uint32_t *)(db_bar)) = (val)\n\n#define BNX2X_DB_READ(db_bar) \\\n\t*((volatile uint32_t *)(db_bar))\n\n#define DOORBELL_ADDR(sc, offset) \\\n\t(volatile uint32_t *)(((char *)(sc)->bar[BAR1].base_addr + (offset)))\n\n#define DOORBELL(sc, cid, val) \\\n\tif (IS_PF(sc)) \\\n\tBNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid) + DPM_TRIGGER_TYPE)), (val)); \\\n\telse \\\n\tBNX2X_DB_WRITE((DOORBELL_ADDR(sc, sc->doorbell_size * (cid))), (val)) \\\n\n#define SHMEM_ADDR(sc, field) \\\n (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))\n#define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))\n#define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))\n#define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)\n\n#define SHMEM2_ADDR(sc, field) \\\n (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))\n#define SHMEM2_HAS(sc, field) \\\n (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \\\n\t\t\t\t offsetof(struct shmem2_region, field)))\n#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))\n#define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)\n\n#define MFCFG_ADDR(sc, field) \\\n (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))\n#define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))\n#define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))\n#define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)\n\n/* DMAE command defines */\n\n#define DMAE_TIMEOUT -1\n#define DMAE_PCI_ERROR -2 /* E2 and onward */\n#define DMAE_NOT_RDY -3\n#define DMAE_PCI_ERR_FLAG 0x80000000\n\n#define DMAE_SRC_PCI 0\n#define DMAE_SRC_GRC 1\n\n#define DMAE_DST_NONE 0\n#define DMAE_DST_PCI 1\n#define DMAE_DST_GRC 2\n\n#define DMAE_COMP_PCI 0\n#define DMAE_COMP_GRC 1\n\n#define DMAE_COMP_REGULAR 0\n#define DMAE_COM_SET_ERR 1\n\n#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT)\n#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT)\n#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT)\n#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT)\n\n#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT)\n#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT)\n\n#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)\n#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)\n#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)\n#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)\n\n#define DMAE_CMD_PORT_0 0\n#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT\n\n#define DMAE_SRC_PF 0\n#define DMAE_SRC_VF 1\n\n#define DMAE_DST_PF 0\n#define DMAE_DST_VF 1\n\n#define DMAE_C_SRC 0\n#define DMAE_C_DST 1\n\n#define DMAE_LEN32_RD_MAX 0x80\n#define DMAE_LEN32_WR_MAX(sc) 0x2000\n\n#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */\n\n#define MAX_DMAE_C_PER_PORT 8\n#define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))\n#define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)\n\nstatic const uint32_t dmae_reg_go_c[] = {\n DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,\n DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,\n DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,\n DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15\n};\n\n#define ATTN_NIG_FOR_FUNC (1L << 8)\n#define ATTN_SW_TIMER_4_FUNC (1L << 9)\n#define GPIO_2_FUNC (1L << 10)\n#define GPIO_3_FUNC (1L << 11)\n#define GPIO_4_FUNC (1L << 12)\n#define ATTN_GENERAL_ATTN_1 (1L << 13)\n#define ATTN_GENERAL_ATTN_2 (1L << 14)\n#define ATTN_GENERAL_ATTN_3 (1L << 15)\n#define ATTN_GENERAL_ATTN_4 (1L << 13)\n#define ATTN_GENERAL_ATTN_5 (1L << 14)\n#define ATTN_GENERAL_ATTN_6 (1L << 15)\n#define ATTN_HARD_WIRED_MASK 0xff00\n#define ATTENTION_ID 4\n\n#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \\\n AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR\n\n#define MAX_IGU_ATTN_ACK_TO 100\n\n#define STORM_ASSERT_ARRAY_SIZE 50\n\n#define BNX2X_PMF_LINK_ASSERT(sc) \\\n GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))\n\n#define BNX2X_MC_ASSERT_BITS \\\n (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \\\n GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \\\n GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \\\n GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))\n\n#define BNX2X_MCP_ASSERT \\\n GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)\n\n#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)\n#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \\\n\t\t\t GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \\\n\t\t\t GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \\\n\t\t\t GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \\\n\t\t\t GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \\\n\t\t\t GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))\n\n#define MULTI_MASK 0x7f\n\n#define PFS_PER_PORT(sc) \\\n ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)\n#define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)\n\n#define FIRST_ABS_FUNC_IN_PORT(sc) \\\n ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \\\n PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))\n\n#define FOREACH_ABS_FUNC_IN_PORT(sc, i) \\\n for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \\\n\t (i) < MAX_FUNC_NUM; \\\n\t (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))\n\n#define BNX2X_SWCID_SHIFT 17\n#define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)\n\n#define SW_CID(x) (le32toh(x) & BNX2X_SWCID_MASK)\n#define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)\n\n#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)\n#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)\n#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)\n#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)\n#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)\n\n/* must be used on a CID before placing it on a HW ring */\n#define HW_CID(sc, x) \\\n ((SC_PORT(sc) << 23) | (SC_VN(sc) << BNX2X_SWCID_SHIFT) | (x))\n\n#define SPEED_10 10\n#define SPEED_100 100\n#define SPEED_1000 1000\n#define SPEED_2500 2500\n#define SPEED_10000 10000\n\n#define PCI_PM_D0 1\n#define PCI_PM_D3hot 2\n\nint bnx2x_test_bit(int nr, volatile unsigned long * addr);\nvoid bnx2x_set_bit(unsigned int nr, volatile unsigned long * addr);\nvoid bnx2x_clear_bit(int nr, volatile unsigned long * addr);\nint bnx2x_test_and_clear_bit(int nr, volatile unsigned long * addr);\nint bnx2x_cmpxchg(volatile int *addr, int old, int new);\n\nint bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size,\n\t\tstruct bnx2x_dma *dma, const char *msg, uint32_t align);\n\nuint32_t bnx2x_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);\nuint32_t bnx2x_dmae_opcode_clr_src_reset(uint32_t opcode);\nuint32_t bnx2x_dmae_opcode(struct bnx2x_softc *sc, uint8_t src_type,\n\t\t\t uint8_t dst_type, uint8_t with_comp,\n\t\t\t uint8_t comp_type);\nvoid bnx2x_post_dmae(struct bnx2x_softc *sc, struct dmae_command *dmae, int idx);\nvoid bnx2x_read_dmae(struct bnx2x_softc *sc, uint32_t src_addr, uint32_t len32);\nvoid bnx2x_write_dmae(struct bnx2x_softc *sc, phys_addr_t dma_addr,\n\t\t uint32_t dst_addr, uint32_t len32);\nvoid bnx2x_set_ctx_validation(struct bnx2x_softc *sc, struct eth_context *cxt,\n\t\t\t uint32_t cid);\nvoid bnx2x_update_coalesce_sb_index(struct bnx2x_softc *sc, uint8_t fw_sb_id,\n\t\t\t\t uint8_t sb_index, uint8_t disable,\n\t\t\t\t uint16_t usec);\n\nint bnx2x_sp_post(struct bnx2x_softc *sc, int command, int cid,\n\t\tuint32_t data_hi, uint32_t data_lo, int cmd_type);\n\nvoid ecore_init_e1h_firmware(struct bnx2x_softc *sc);\nvoid ecore_init_e2_firmware(struct bnx2x_softc *sc);\n\nvoid ecore_storm_memset_struct(struct bnx2x_softc *sc, uint32_t addr,\n\t\t\t size_t size, uint32_t *data);\n\n#define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));\n#define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)\n\n#define BNX2X_MAC_FMT\t\t\"%pM\"\n#define BNX2X_MAC_PRN_LIST(mac)\t(mac)\n\n/***********/\n/* INLINES */\n/***********/\n\nstatic inline uint32_t\nreg_poll(struct bnx2x_softc *sc, uint32_t reg, uint32_t expected, int ms, int wait)\n{\n uint32_t val;\n do {\n\tval = REG_RD(sc, reg);\n\tif (val == expected) {\n\t break;\n\t}\n\tms -= wait;\n\tDELAY(wait * 1000);\n } while (ms > 0);\n\n return val;\n}\n\nstatic inline void\nbnx2x_update_fp_sb_idx(struct bnx2x_fastpath *fp)\n{\n\tmb(); /* status block is written to by the chip */\n\tfp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];\n}\n\nstatic inline void\nbnx2x_igu_ack_sb_gen(struct bnx2x_softc *sc, uint8_t segment,\n\tuint16_t index, uint8_t op, uint8_t update, uint32_t igu_addr)\n{\n\tstruct igu_regular cmd_data = {0};\n\n\tcmd_data.sb_id_and_flags =\n\t\t((index << IGU_REGULAR_SB_INDEX_SHIFT) |\n\t\t (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |\n\t\t (update << IGU_REGULAR_BUPDATE_SHIFT) |\n\t\t (op << IGU_REGULAR_ENABLE_INT_SHIFT));\n\n\tREG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);\n\n\t/* Make sure that ACK is written */\n\tmb();\n}\n\nstatic inline void\nbnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,\n\t\tuint16_t index, uint8_t op, uint8_t update)\n{\n\tuint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +\n\t\t\tCOMMAND_REG_INT_ACK);\n\tunion igu_ack_register igu_ack;\n\n\tigu_ack.sb.status_block_index = index;\n\tigu_ack.sb.sb_id_and_flags =\n\t\t((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |\n\t\t (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |\n\t\t (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |\n\t\t (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));\n\n\tREG_WR(sc, hc_addr, igu_ack.raw_data);\n\n\t/* Make sure that ACK is written */\n\tmb();\n}\n\nstatic inline uint32_t\nbnx2x_hc_ack_int(struct bnx2x_softc *sc)\n{\n\tuint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +\n\t\t\tCOMMAND_REG_SIMD_MASK);\n\tuint32_t result = REG_RD(sc, hc_addr);\n\n\tmb();\n\treturn result;\n}\n\nstatic inline uint32_t\nbnx2x_igu_ack_int(struct bnx2x_softc *sc)\n{\n\tuint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER * 8);\n\tuint32_t result = REG_RD(sc, igu_addr);\n\n\t/* PMD_PDEBUG_LOG(sc, DBG_INTR, \"read 0x%08x from IGU addr 0x%x\",\n\t\t\tresult, igu_addr); */\n\n\tmb();\n\treturn result;\n}\n\nstatic inline uint32_t\nbnx2x_ack_int(struct bnx2x_softc *sc)\n{\n\tmb();\n\tif (sc->devinfo.int_block == INT_BLOCK_HC) {\n\t\treturn bnx2x_hc_ack_int(sc);\n\t} else {\n\t\treturn bnx2x_igu_ack_int(sc);\n\t}\n}\n\nstatic inline int\nfunc_by_vn(struct bnx2x_softc *sc, int vn)\n{\n return (2 * vn + SC_PORT(sc));\n}\n\n/*\n * send notification to other functions.\n */\nstatic inline void\nbnx2x_link_sync_notify(struct bnx2x_softc *sc)\n{\n\tint func, vn;\n\n\t/* Set the attention towards other drivers on the same port */\n\tfor (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {\n\t\tif (vn == SC_VN(sc))\n\t\t\tcontinue;\n\n\t\tfunc = func_by_vn(sc, vn);\n\t\tREG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_0 +\n\t\t\t\t(LINK_SYNC_ATTENTION_BIT_FUNC_0 + func) * 4, 1);\n\t}\n}\n\n/*\n * Statistics ID are global per chip/path, while Client IDs for E1x\n * are per port.\n */\nstatic inline uint8_t\nbnx2x_stats_id(struct bnx2x_fastpath *fp)\n{\n struct bnx2x_softc *sc = fp->sc;\n\n if (!CHIP_IS_E1x(sc)) {\n\treturn fp->cl_id;\n }\n\n return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x);\n}\n\nint bnx2x_init(struct bnx2x_softc *sc);\nvoid bnx2x_load_firmware(struct bnx2x_softc *sc);\nint bnx2x_attach(struct bnx2x_softc *sc);\nint bnx2x_nic_unload(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_link);\nint bnx2x_alloc_hsi_mem(struct bnx2x_softc *sc);\nint bnx2x_alloc_ilt_mem(struct bnx2x_softc *sc);\nvoid bnx2x_free_ilt_mem(struct bnx2x_softc *sc);\nvoid bnx2x_dump_tx_chain(struct bnx2x_fastpath * fp, int bd_prod, int count);\nint bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf **m_head, int m_pkts);\nuint8_t bnx2x_txeof(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp);\nvoid bnx2x_print_adapter_info(struct bnx2x_softc *sc);\nint bnx2x_intr_legacy(struct bnx2x_softc *sc, int scan_fp);\nvoid bnx2x_link_status_update(struct bnx2x_softc *sc);\nint bnx2x_complete_sp(struct bnx2x_softc *sc);\nint bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc);\nvoid bnx2x_periodic_callout(struct bnx2x_softc *sc);\n\nint bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count);\nvoid bnx2x_vf_close(struct bnx2x_softc *sc);\nint bnx2x_vf_init(struct bnx2x_softc *sc);\nvoid bnx2x_vf_unload(struct bnx2x_softc *sc);\nint bnx2x_vf_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n\tint leading);\nvoid bnx2x_free_hsi_mem(struct bnx2x_softc *sc);\nint bnx2x_vf_set_rx_mode(struct bnx2x_softc *sc);\nint bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,\n\tunsigned long *rx_accept_flags, unsigned long *tx_accept_flags);\nint bnx2x_check_bull(struct bnx2x_softc *sc);\n\n//#define BNX2X_PULSE\n\n#define BNX2X_PCI_CAP 1\n#define BNX2X_PCI_ECAP 2\n\nstatic inline struct bnx2x_pci_cap*\npci_find_cap(struct bnx2x_softc *sc, uint8_t id, uint8_t type)\n{\n\tstruct bnx2x_pci_cap *cap = sc->pci_caps;\n\n\twhile (cap) {\n\t\tif (cap->id == id && cap->type == type)\n\t\t\treturn cap;\n\t\tcap = cap->next;\n\t}\n\n\treturn NULL;\n}\n\nstatic inline int is_valid_ether_addr(uint8_t *addr)\n{\n\tif (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]))\n\t\treturn 0;\n\telse\n\t\treturn 1;\n}\n\nstatic inline void\nbnx2x_set_rx_mode(struct bnx2x_softc *sc)\n{\n\tif (sc->state == BNX2X_STATE_OPEN) {\n\t\tif (IS_PF(sc)) {\n\t\t\tbnx2x_set_storm_rx_mode(sc);\n\t\t} else {\n\t\t\tsc->rx_mode = BNX2X_RX_MODE_PROMISC;\n\t\t\tbnx2x_vf_set_rx_mode(sc);\n\t\t}\n\t} else {\n\t\tPMD_DRV_LOG(NOTICE, \"Card is not ready to change mode\");\n\t}\n}\n\nstatic inline int pci_read(struct bnx2x_softc *sc, size_t addr,\n\t\t\t void *val, uint8_t size)\n{\n\tif (rte_eal_pci_read_config(sc->pci_dev, val, size, addr) <= 0) {\n\t\tPMD_DRV_LOG(ERR, \"Can't read from PCI config space\");\n\t\treturn ENXIO;\n\t}\n\n\treturn 0;\n}\n\nstatic inline int pci_write_word(struct bnx2x_softc *sc, size_t addr, off_t val)\n{\n\tuint16_t val16 = val;\n\n\tif (rte_eal_pci_write_config(sc->pci_dev, &val16,\n\t\t\t\t sizeof(val16), addr) <= 0) {\n\t\tPMD_DRV_LOG(ERR, \"Can't write to PCI config space\");\n\t\treturn ENXIO;\n\t}\n\n\treturn 0;\n}\n\nstatic inline int pci_write_long(struct bnx2x_softc *sc, size_t addr, off_t val)\n{\n\tuint32_t val32 = val;\n\tif (rte_eal_pci_write_config(sc->pci_dev, &val32,\n\t\t\t\t sizeof(val32), addr) <= 0) {\n\t\tPMD_DRV_LOG(ERR, \"Can't write to PCI config space\");\n\t\treturn ENXIO;\n\t}\n\n\treturn 0;\n}\n\n#endif /* __BNX2X_H__ */\n" }, { "path": "drivers/net/bnx2x/bnx2x_ethdev.c", "content": "/*\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n *\n * All rights reserved.\n */\n\n#include \"bnx2x.h\"\n#include \"bnx2x_rxtx.h\"\n\n#include \n\n/*\n * The set of PCI devices this driver supports\n */\nstatic struct rte_pci_id pci_id_bnx2x_map[] = {\n#define RTE_PCI_DEV_ID_DECL_BNX2X(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \"rte_pci_dev_ids.h\"\n\t{ .vendor_id = 0, }\n};\n\nstatic struct rte_pci_id pci_id_bnx2xvf_map[] = {\n#define RTE_PCI_DEV_ID_DECL_BNX2XVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \"rte_pci_dev_ids.h\"\n\t{ .vendor_id = 0, }\n};\n\nstatic void\nbnx2x_link_update(struct rte_eth_dev *dev)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\tbnx2x_link_status_update(sc);\n\tmb();\n\tdev->data->dev_link.link_speed = sc->link_vars.line_speed;\n\tswitch (sc->link_vars.duplex) {\n\t\tcase DUPLEX_FULL:\n\t\t\tdev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;\n\t\t\tbreak;\n\t\tcase DUPLEX_HALF:\n\t\t\tdev->data->dev_link.link_duplex = ETH_LINK_HALF_DUPLEX;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tdev->data->dev_link.link_duplex = ETH_LINK_AUTONEG_DUPLEX;\n\t}\n\tdev->data->dev_link.link_status = sc->link_vars.link_up;\n}\n\nstatic void\nbnx2x_interrupt_action(struct rte_eth_dev *dev)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\tuint32_t link_status;\n\n\tPMD_DRV_LOG(INFO, \"Interrupt handled\");\n\n\tif (bnx2x_intr_legacy(sc, 0))\n\t\tDELAY_MS(250);\n\tif (sc->periodic_flags & PERIODIC_GO)\n\t\tbnx2x_periodic_callout(sc);\n\tlink_status = REG_RD(sc, sc->link_params.shmem_base +\n\t\t\toffsetof(struct shmem_region,\n\t\t\t\tport_mb[sc->link_params.port].link_status));\n\tif ((link_status & LINK_STATUS_LINK_UP) != dev->data->dev_link.link_status)\n\t\tbnx2x_link_update(dev);\n}\n\nstatic __rte_unused void\nbnx2x_interrupt_handler(__rte_unused struct rte_intr_handle *handle, void *param)\n{\n\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n\n\tbnx2x_interrupt_action(dev);\n\trte_intr_enable(&(dev->pci_dev->intr_handle));\n}\n\n/*\n * Devops - helper functions can be called from user application\n */\n\nstatic int\nbnx2x_dev_configure(struct rte_eth_dev *dev)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\tint mp_ncpus = sysconf(_SC_NPROCESSORS_CONF);\n\tint ret;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (dev->data->dev_conf.rxmode.jumbo_frame)\n\t\tsc->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len;\n\n\tif (dev->data->nb_tx_queues > dev->data->nb_rx_queues) {\n\t\tPMD_DRV_LOG(ERR, \"The number of TX queues is greater than number of RX queues\");\n\t\treturn -EINVAL;\n\t}\n\n\tsc->num_queues = MAX(dev->data->nb_rx_queues, dev->data->nb_tx_queues);\n\tif (sc->num_queues > mp_ncpus) {\n\t\tPMD_DRV_LOG(ERR, \"The number of queues is more than number of CPUs\");\n\t\treturn -EINVAL;\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"num_queues=%d, mtu=%d\",\n\t\t sc->num_queues, sc->mtu);\n\n\t/* allocate ilt */\n\tif (bnx2x_alloc_ilt_mem(sc) != 0) {\n\t\tPMD_DRV_LOG(ERR, \"bnx2x_alloc_ilt_mem was failed\");\n\t\treturn -ENXIO;\n\t}\n\n\t/* allocate the host hardware/software hsi structures */\n\tif (bnx2x_alloc_hsi_mem(sc) != 0) {\n\t\tPMD_DRV_LOG(ERR, \"bnx2x_alloc_hsi_mem was failed\");\n\t\tbnx2x_free_ilt_mem(sc);\n\t\treturn -ENXIO;\n\t}\n\n\tif (IS_VF(sc)) {\n\t\tif (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_vf_mbx_msg),\n\t\t\t\t &sc->vf2pf_mbox_mapping, \"vf2pf_mbox\",\n\t\t\t\t RTE_CACHE_LINE_SIZE) != 0)\n\t\t\treturn -ENOMEM;\n\n\t\tsc->vf2pf_mbox = (struct bnx2x_vf_mbx_msg *)sc->vf2pf_mbox_mapping.vaddr;\n\t\tif (bnx2x_dma_alloc(sc, sizeof(struct bnx2x_vf_bulletin),\n\t\t\t\t &sc->pf2vf_bulletin_mapping, \"vf2pf_bull\",\n\t\t\t\t RTE_CACHE_LINE_SIZE) != 0)\n\t\t\treturn -ENOMEM;\n\n\t\tsc->pf2vf_bulletin = (struct bnx2x_vf_bulletin *)sc->pf2vf_bulletin_mapping.vaddr;\n\n\t\tret = bnx2x_vf_get_resources(sc, sc->num_queues, sc->num_queues);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nbnx2x_dev_start(struct rte_eth_dev *dev)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\tint ret = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tret = bnx2x_init(sc);\n\tif (ret) {\n\t\tPMD_DRV_LOG(DEBUG, \"bnx2x_init failed (%d)\", ret);\n\t\treturn -1;\n\t}\n\n\tif (IS_PF(sc)) {\n\t\trte_intr_callback_register(&(dev->pci_dev->intr_handle),\n\t\t\t\tbnx2x_interrupt_handler, (void *)dev);\n\n\t\tif(rte_intr_enable(&(dev->pci_dev->intr_handle)))\n\t\t\tPMD_DRV_LOG(ERR, \"rte_intr_enable failed\");\n\t}\n\n\tret = bnx2x_dev_rx_init(dev);\n\tif (ret != 0) {\n\t\tPMD_DRV_LOG(DEBUG, \"bnx2x_dev_rx_init returned error code\");\n\t\treturn -3;\n\t}\n\n\t/* Print important adapter info for the user. */\n\tbnx2x_print_adapter_info(sc);\n\n\tDELAY_MS(2500);\n\n\treturn ret;\n}\n\nstatic void\nbnx2x_dev_stop(struct rte_eth_dev *dev)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\tint ret = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (IS_PF(sc)) {\n\t\trte_intr_disable(&(dev->pci_dev->intr_handle));\n\t\trte_intr_callback_unregister(&(dev->pci_dev->intr_handle),\n\t\t\t\tbnx2x_interrupt_handler, (void *)dev);\n\t}\n\n\tret = bnx2x_nic_unload(sc, UNLOAD_NORMAL, FALSE);\n\tif (ret) {\n\t\tPMD_DRV_LOG(DEBUG, \"bnx2x_nic_unload failed (%d)\", ret);\n\t\treturn;\n\t}\n\n\treturn;\n}\n\nstatic void\nbnx2x_dev_close(struct rte_eth_dev *dev)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (IS_VF(sc))\n\t\tbnx2x_vf_close(sc);\n\n\tbnx2x_dev_clear_queues(dev);\n\tmemset(&(dev->data->dev_link), 0 , sizeof(struct rte_eth_link));\n\n\t/* free the host hardware/software hsi structures */\n\tbnx2x_free_hsi_mem(sc);\n\n\t/* free ilt */\n\tbnx2x_free_ilt_mem(sc);\n}\n\nstatic void\nbnx2x_promisc_enable(struct rte_eth_dev *dev)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\tsc->rx_mode = BNX2X_RX_MODE_PROMISC;\n\tbnx2x_set_rx_mode(sc);\n}\n\nstatic void\nbnx2x_promisc_disable(struct rte_eth_dev *dev)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\tsc->rx_mode = BNX2X_RX_MODE_NORMAL;\n\tbnx2x_set_rx_mode(sc);\n}\n\nstatic void\nbnx2x_dev_allmulticast_enable(struct rte_eth_dev *dev)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\tsc->rx_mode = BNX2X_RX_MODE_ALLMULTI;\n\tbnx2x_set_rx_mode(sc);\n}\n\nstatic void\nbnx2x_dev_allmulticast_disable(struct rte_eth_dev *dev)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\tsc->rx_mode = BNX2X_RX_MODE_NORMAL;\n\tbnx2x_set_rx_mode(sc);\n}\n\nstatic int\nbnx2x_dev_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\tint old_link_status = dev->data->dev_link.link_status;\n\n\tbnx2x_link_update(dev);\n\n\treturn old_link_status == dev->data->dev_link.link_status ? -1 : 0;\n}\n\nstatic int\nbnx2xvf_dev_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)\n{\n\tint old_link_status = dev->data->dev_link.link_status;\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\n\tbnx2x_link_update(dev);\n\n\tbnx2x_check_bull(sc);\n\tif (sc->old_bulletin.valid_bitmap & (1 << CHANNEL_DOWN)) {\n\t\tPMD_DRV_LOG(ERR, \"PF indicated channel is down.\"\n\t\t\t\t\"VF device is no longer operational\");\n\t\tdev->data->dev_link.link_status = 0;\n\t}\n\n\treturn old_link_status == dev->data->dev_link.link_status ? -1 : 0;\n}\n\nstatic void\nbnx2x_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tbnx2x_stats_handle(sc, STATS_EVENT_UPDATE);\n\n\tmemset(stats, 0, sizeof (struct rte_eth_stats));\n\n\tstats->ipackets =\n\t\tHILO_U64(sc->eth_stats.total_unicast_packets_received_hi,\n\t\t\t\tsc->eth_stats.total_unicast_packets_received_lo) +\n\t\tHILO_U64(sc->eth_stats.total_multicast_packets_received_hi,\n\t\t\t\tsc->eth_stats.total_multicast_packets_received_lo) +\n\t\tHILO_U64(sc->eth_stats.total_broadcast_packets_received_hi,\n\t\t\t\tsc->eth_stats.total_broadcast_packets_received_lo);\n\n\tstats->opackets =\n\t\tHILO_U64(sc->eth_stats.total_unicast_packets_transmitted_hi,\n\t\t\t\tsc->eth_stats.total_unicast_packets_transmitted_lo) +\n\t\tHILO_U64(sc->eth_stats.total_multicast_packets_transmitted_hi,\n\t\t\t\tsc->eth_stats.total_multicast_packets_transmitted_lo) +\n\t\tHILO_U64(sc->eth_stats.total_broadcast_packets_transmitted_hi,\n\t\t\t\tsc->eth_stats.total_broadcast_packets_transmitted_lo);\n\n\tstats->ibytes =\n\t\tHILO_U64(sc->eth_stats.total_bytes_received_hi,\n\t\t\t\tsc->eth_stats.total_bytes_received_lo);\n\n\tstats->obytes =\n\t\tHILO_U64(sc->eth_stats.total_bytes_transmitted_hi,\n\t\t\t\tsc->eth_stats.total_bytes_transmitted_lo);\n\n\tstats->ierrors =\n\t\tHILO_U64(sc->eth_stats.error_bytes_received_hi,\n\t\t\t\tsc->eth_stats.error_bytes_received_lo);\n\n\tstats->oerrors = 0;\n\n\tstats->rx_nombuf =\n\t\tHILO_U64(sc->eth_stats.no_buff_discard_hi,\n\t\t\t\tsc->eth_stats.no_buff_discard_lo);\n}\n\nstatic void\nbnx2x_dev_infos_get(struct rte_eth_dev *dev, __rte_unused struct rte_eth_dev_info *dev_info)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\tdev_info->max_rx_queues = sc->max_rx_queues;\n\tdev_info->max_tx_queues = sc->max_tx_queues;\n\tdev_info->min_rx_bufsize = BNX2X_MIN_RX_BUF_SIZE;\n\tdev_info->max_rx_pktlen = BNX2X_MAX_RX_PKT_LEN;\n\tdev_info->max_mac_addrs = BNX2X_MAX_MAC_ADDRS;\n}\n\nstatic void\nbnx2x_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,\n\t\tuint32_t index, uint32_t pool)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\n\tif (sc->mac_ops.mac_addr_add)\n\t\tsc->mac_ops.mac_addr_add(dev, mac_addr, index, pool);\n}\n\nstatic void\nbnx2x_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)\n{\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\n\tif (sc->mac_ops.mac_addr_remove)\n\t\tsc->mac_ops.mac_addr_remove(dev, index);\n}\n\nstatic struct eth_dev_ops bnx2x_eth_dev_ops = {\n\t.dev_configure = bnx2x_dev_configure,\n\t.dev_start = bnx2x_dev_start,\n\t.dev_stop = bnx2x_dev_stop,\n\t.dev_close = bnx2x_dev_close,\n\t.promiscuous_enable = bnx2x_promisc_enable,\n\t.promiscuous_disable = bnx2x_promisc_disable,\n\t.allmulticast_enable = bnx2x_dev_allmulticast_enable,\n\t.allmulticast_disable = bnx2x_dev_allmulticast_disable,\n\t.link_update = bnx2x_dev_link_update,\n\t.stats_get = bnx2x_dev_stats_get,\n\t.dev_infos_get = bnx2x_dev_infos_get,\n\t.rx_queue_setup = bnx2x_dev_rx_queue_setup,\n\t.rx_queue_release = bnx2x_dev_rx_queue_release,\n\t.tx_queue_setup = bnx2x_dev_tx_queue_setup,\n\t.tx_queue_release = bnx2x_dev_tx_queue_release,\n\t.mac_addr_add = bnx2x_mac_addr_add,\n\t.mac_addr_remove = bnx2x_mac_addr_remove,\n};\n\n/*\n * dev_ops for virtual function\n */\nstatic struct eth_dev_ops bnx2xvf_eth_dev_ops = {\n\t.dev_configure = bnx2x_dev_configure,\n\t.dev_start = bnx2x_dev_start,\n\t.dev_stop = bnx2x_dev_stop,\n\t.dev_close = bnx2x_dev_close,\n\t.promiscuous_enable = bnx2x_promisc_enable,\n\t.promiscuous_disable = bnx2x_promisc_disable,\n\t.allmulticast_enable = bnx2x_dev_allmulticast_enable,\n\t.allmulticast_disable = bnx2x_dev_allmulticast_disable,\n\t.link_update = bnx2xvf_dev_link_update,\n\t.stats_get = bnx2x_dev_stats_get,\n\t.dev_infos_get = bnx2x_dev_infos_get,\n\t.rx_queue_setup = bnx2x_dev_rx_queue_setup,\n\t.rx_queue_release = bnx2x_dev_rx_queue_release,\n\t.tx_queue_setup = bnx2x_dev_tx_queue_setup,\n\t.tx_queue_release = bnx2x_dev_tx_queue_release,\n\t.mac_addr_add = bnx2x_mac_addr_add,\n\t.mac_addr_remove = bnx2x_mac_addr_remove,\n};\n\n\nstatic int\nbnx2x_common_dev_init(struct rte_eth_dev *eth_dev, int is_vf)\n{\n\tint ret = 0;\n\tstruct rte_pci_device *pci_dev;\n\tstruct bnx2x_softc *sc;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\teth_dev->dev_ops = is_vf ? &bnx2xvf_eth_dev_ops : &bnx2x_eth_dev_ops;\n\tpci_dev = eth_dev->pci_dev;\n\tsc = eth_dev->data->dev_private;\n\tsc->pcie_bus = pci_dev->addr.bus;\n\tsc->pcie_device = pci_dev->addr.devid;\n\n\tif (is_vf)\n\t\tsc->flags = BNX2X_IS_VF_FLAG;\n\n\tsc->devinfo.vendor_id = pci_dev->id.vendor_id;\n\tsc->devinfo.device_id = pci_dev->id.device_id;\n\tsc->devinfo.subvendor_id = pci_dev->id.subsystem_vendor_id;\n\tsc->devinfo.subdevice_id = pci_dev->id.subsystem_device_id;\n\n\tsc->pcie_func = pci_dev->addr.function;\n\tsc->bar[BAR0].base_addr = (void *)pci_dev->mem_resource[0].addr;\n\tif (is_vf)\n\t\tsc->bar[BAR1].base_addr = (void *)\n\t\t\t((uint64_t)pci_dev->mem_resource[0].addr + PXP_VF_ADDR_DB_START);\n\telse\n\t\tsc->bar[BAR1].base_addr = pci_dev->mem_resource[2].addr;\n\n\tassert(sc->bar[BAR0].base_addr);\n\tassert(sc->bar[BAR1].base_addr);\n\n\tbnx2x_load_firmware(sc);\n\tassert(sc->firmware);\n\n\tif (eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)\n\t\tsc->udp_rss = 1;\n\n\tsc->rx_budget = BNX2X_RX_BUDGET;\n\tsc->hc_rx_ticks = BNX2X_RX_TICKS;\n\tsc->hc_tx_ticks = BNX2X_TX_TICKS;\n\n\tsc->interrupt_mode = INTR_MODE_SINGLE_MSIX;\n\tsc->rx_mode = BNX2X_RX_MODE_NORMAL;\n\n\tsc->pci_dev = pci_dev;\n\tret = bnx2x_attach(sc);\n\tif (ret) {\n\t\tPMD_DRV_LOG(ERR, \"bnx2x_attach failed (%d)\", ret);\n\t}\n\n\teth_dev->data->mac_addrs = (struct ether_addr *)sc->link_params.mac_addr;\n\n\tPMD_DRV_LOG(INFO, \"pcie_bus=%d, pcie_device=%d\",\n\t\t\tsc->pcie_bus, sc->pcie_device);\n\tPMD_DRV_LOG(INFO, \"bar0.addr=%p, bar1.addr=%p\",\n\t\t\tsc->bar[BAR0].base_addr, sc->bar[BAR1].base_addr);\n\tPMD_DRV_LOG(INFO, \"port=%d, path=%d, vnic=%d, func=%d\",\n\t\t\tPORT_ID(sc), PATH_ID(sc), VNIC_ID(sc), FUNC_ID(sc));\n\tPMD_DRV_LOG(INFO, \"portID=%d vendorID=0x%x deviceID=0x%x\",\n\t\t\teth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id);\n\n\treturn ret;\n}\n\nstatic int\neth_bnx2x_dev_init(struct rte_eth_dev *eth_dev)\n{\n\tPMD_INIT_FUNC_TRACE();\n\treturn bnx2x_common_dev_init(eth_dev, 0);\n}\n\nstatic int\neth_bnx2xvf_dev_init(struct rte_eth_dev *eth_dev)\n{\n\tPMD_INIT_FUNC_TRACE();\n\treturn bnx2x_common_dev_init(eth_dev, 1);\n}\n\nstatic struct eth_driver rte_bnx2x_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_bnx2x_pmd\",\n\t\t.id_table = pci_id_bnx2x_map,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,\n\t},\n\t.eth_dev_init = eth_bnx2x_dev_init,\n\t.dev_private_size = sizeof(struct bnx2x_softc),\n};\n\n/*\n * virtual function driver struct\n */\nstatic struct eth_driver rte_bnx2xvf_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_bnx2xvf_pmd\",\n\t\t.id_table = pci_id_bnx2xvf_map,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n\t},\n\t.eth_dev_init = eth_bnx2xvf_dev_init,\n\t.dev_private_size = sizeof(struct bnx2x_softc),\n};\n\nstatic int rte_bnx2x_pmd_init(const char *name __rte_unused, const char *params __rte_unused)\n{\n\tPMD_INIT_FUNC_TRACE();\n\trte_eth_driver_register(&rte_bnx2x_pmd);\n\n\treturn 0;\n}\n\nstatic int rte_bnx2xvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)\n{\n\tPMD_INIT_FUNC_TRACE();\n\trte_eth_driver_register(&rte_bnx2xvf_pmd);\n\n\treturn 0;\n}\n\nstatic struct rte_driver rte_bnx2x_driver = {\n\t.type = PMD_PDEV,\n\t.init = rte_bnx2x_pmd_init,\n};\n\nstatic struct rte_driver rte_bnx2xvf_driver = {\n\t.type = PMD_PDEV,\n\t.init = rte_bnx2xvf_pmd_init,\n};\n\nPMD_REGISTER_DRIVER(rte_bnx2x_driver);\nPMD_REGISTER_DRIVER(rte_bnx2xvf_driver);\n" }, { "path": "drivers/net/bnx2x/bnx2x_ethdev.h", "content": "/*\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n *\n * All rights reserved.\n */\n\n#ifndef PMD_BNX2X_ETHDEV_H\n#define PMD_BNX2X_ETHDEV_H\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"bnx2x_rxtx.h\"\n#include \"bnx2x_logs.h\"\n\n#define DELAY(x) rte_delay_us(x)\n#define DELAY_MS(x) rte_delay_ms(x)\n#define usec_delay(x) DELAY(x)\n#define msec_delay(x) DELAY(1000*(x))\n\n#define FALSE 0\n#define TRUE 1\n\n#define false 0\n#define true 1\n#define min(a,b) RTE_MIN(a,b)\n\n#define mb() rte_mb()\n#define wmb() rte_wmb()\n#define rmb() rte_rmb()\n\n\n#define MAX_QUEUES sysconf(_SC_NPROCESSORS_CONF)\n\n#define BNX2X_MIN_RX_BUF_SIZE 1024\n#define BNX2X_MAX_RX_PKT_LEN 15872\n#define BNX2X_MAX_MAC_ADDRS 1\n\n/* Hardware RX tick timer (usecs) */\n#define BNX2X_RX_TICKS 25\n/* Hardware TX tick timer (usecs) */\n#define BNX2X_TX_TICKS 50\n/* Maximum number of Rx packets to process at a time */\n#define BNX2X_RX_BUDGET 0xffffffff\n\n#endif\n\n/* MAC address operations */\nstruct bnx2x_mac_ops {\n\tvoid (*mac_addr_add)(struct rte_eth_dev *dev, struct ether_addr *addr,\n\t\t\tuint16_t index, uint32_t pool); /* not implemented yet */\n\tvoid (*mac_addr_remove)(struct rte_eth_dev *dev, uint16_t index); /* not implemented yet */\n};\n" }, { "path": "drivers/net/bnx2x/bnx2x_logs.h", "content": "/*\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n *\n * All rights reserved.\n */\n\n#ifndef _PMD_LOGS_H_\n#define _PMD_LOGS_H_\n\n#define PMD_INIT_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ##args)\n\n#ifdef RTE_LIBRTE_BNX2X_DEBUG_INIT\n#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, \" >>\")\n#else\n#define PMD_INIT_FUNC_TRACE() do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_BNX2X_DEBUG_RX\n#define PMD_RX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_RX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_BNX2X_DEBUG_TX\n#define PMD_TX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_TX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_BNX2X_DEBUG_TX_FREE\n#define PMD_TX_FREE_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_TX_FREE_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_BNX2X_DEBUG\n#define PMD_DRV_LOG_RAW(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt, __func__, ## args)\n#else\n#define PMD_DRV_LOG_RAW(level, fmt, args...) do { } while (0)\n#endif\n\n#define PMD_DRV_LOG(level, fmt, args...) \\\n\tPMD_DRV_LOG_RAW(level, fmt \"\\n\", ## args)\n\n#endif /* _PMD_LOGS_H_ */\n" }, { "path": "drivers/net/bnx2x/bnx2x_rxtx.c", "content": "/*\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n *\n * All rights reserved.\n */\n\n#include \"bnx2x.h\"\n#include \"bnx2x_rxtx.h\"\n\nstatic inline struct rte_mbuf *\nbnx2x_rxmbuf_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\n\tm = __rte_mbuf_raw_alloc(mp);\n\t__rte_mbuf_sanity_check(m, 0);\n\n\treturn m;\n}\n\nstatic const struct rte_memzone *\nring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,\n\t\t uint16_t queue_id, uint32_t ring_size, int socket_id)\n{\n\tchar z_name[RTE_MEMZONE_NAMESIZE];\n\tconst struct rte_memzone *mz;\n\n\tsnprintf(z_name, sizeof(z_name), \"%s_%s_%d_%d\",\n\t\t\tdev->driver->pci_drv.name, ring_name, dev->data->port_id, queue_id);\n\n\tmz = rte_memzone_lookup(z_name);\n\tif (mz)\n\t\treturn mz;\n\n\treturn rte_memzone_reserve_aligned(z_name, ring_size, socket_id, 0, BNX2X_PAGE_SIZE);\n}\n\nstatic void\nbnx2x_rx_queue_release(struct bnx2x_rx_queue *rx_queue)\n{\n\tuint16_t i;\n\tstruct rte_mbuf **sw_ring;\n\n\tif (NULL != rx_queue) {\n\n\t\tsw_ring = rx_queue->sw_ring;\n\t\tif (NULL != sw_ring) {\n\t\t\tfor (i = 0; i < rx_queue->nb_rx_desc; i++) {\n\t\t\t\tif (NULL != sw_ring[i])\n\t\t\t\t\trte_pktmbuf_free(sw_ring[i]);\n\t\t\t}\n\t\t\trte_free(sw_ring);\n\t\t}\n\t\trte_free(rx_queue);\n\t}\n}\n\nvoid\nbnx2x_dev_rx_queue_release(void *rxq)\n{\n\tbnx2x_rx_queue_release(rxq);\n}\n\nint\nbnx2x_dev_rx_queue_setup(struct rte_eth_dev *dev,\n\t\t uint16_t queue_idx,\n\t\t uint16_t nb_desc,\n\t\t unsigned int socket_id,\n\t\t const struct rte_eth_rxconf *rx_conf,\n\t\t struct rte_mempool *mp)\n{\n\tuint16_t j, idx;\n\tconst struct rte_memzone *dma;\n\tstruct bnx2x_rx_queue *rxq;\n\tuint32_t dma_size;\n\tstruct rte_mbuf *mbuf;\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\tstruct bnx2x_fastpath *fp = &sc->fp[queue_idx];\n\tstruct eth_rx_cqe_next_page *nextpg;\n\tphys_addr_t *rx_bd;\n\tphys_addr_t busaddr;\n\n\t/* First allocate the rx queue data structure */\n\trxq = rte_zmalloc_socket(\"ethdev RX queue\", sizeof(struct bnx2x_rx_queue),\n\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n\tif (NULL == rxq) {\n\t\tPMD_INIT_LOG(ERR, \"rte_zmalloc for rxq failed!\");\n\t\treturn (-ENOMEM);\n\t}\n\trxq->sc = sc;\n\trxq->mb_pool = mp;\n\trxq->queue_id = queue_idx;\n\trxq->port_id = dev->data->port_id;\n\trxq->crc_len = (uint8_t)((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 : ETHER_CRC_LEN);\n\n\trxq->nb_rx_pages = 1;\n\twhile (USABLE_RX_BD(rxq) < nb_desc)\n\t\trxq->nb_rx_pages <<= 1;\n\n\trxq->nb_rx_desc = TOTAL_RX_BD(rxq);\n\tsc->rx_ring_size = USABLE_RX_BD(rxq);\n\trxq->nb_cq_pages = RCQ_BD_PAGES(rxq);\n\n\trxq->rx_free_thresh = rx_conf->rx_free_thresh ?\n\t\trx_conf->rx_free_thresh : DEFAULT_RX_FREE_THRESH;\n\n\tPMD_INIT_LOG(DEBUG, \"fp[%02d] req_bd=%u, thresh=%u, usable_bd=%lu, \"\n\t\t \"total_bd=%lu, rx_pages=%u, cq_pages=%u\",\n\t\t queue_idx, nb_desc, rxq->rx_free_thresh, USABLE_RX_BD(rxq),\n\t\t TOTAL_RX_BD(rxq), rxq->nb_rx_pages, rxq->nb_cq_pages);\n\n\t/* Allocate RX ring hardware descriptors */\n\tdma_size = rxq->nb_rx_desc * sizeof(struct eth_rx_bd);\n\tdma = ring_dma_zone_reserve(dev, \"hw_ring\", queue_idx, dma_size, socket_id);\n\tif (NULL == dma) {\n\t\tPMD_RX_LOG(ERR, \"ring_dma_zone_reserve for rx_ring failed!\");\n\t\tbnx2x_rx_queue_release(rxq);\n\t\treturn (-ENOMEM);\n\t}\n\tfp->rx_desc_mapping = rxq->rx_ring_phys_addr = (uint64_t)dma->phys_addr;\n\trxq->rx_ring = (uint64_t*)dma->addr;\n\tmemset((void *)rxq->rx_ring, 0, dma_size);\n\n\t/* Link the RX chain pages. */\n\tfor (j = 1; j <= rxq->nb_rx_pages; j++) {\n\t\trx_bd = &rxq->rx_ring[TOTAL_RX_BD_PER_PAGE * j - 2];\n\t\tbusaddr = rxq->rx_ring_phys_addr + BNX2X_PAGE_SIZE * (j % rxq->nb_rx_pages);\n\t\t*rx_bd = busaddr;\n\t}\n\n\t/* Allocate software ring */\n\tdma_size = rxq->nb_rx_desc * sizeof(struct bnx2x_rx_entry);\n\trxq->sw_ring = rte_zmalloc_socket(\"sw_ring\", dma_size,\n\t\t\t\t\t RTE_CACHE_LINE_SIZE,\n\t\t\t\t\t socket_id);\n\tif (NULL == rxq->sw_ring) {\n\t\tPMD_RX_LOG(ERR, \"rte_zmalloc for sw_ring failed!\");\n\t\tbnx2x_rx_queue_release(rxq);\n\t\treturn (-ENOMEM);\n\t}\n\n\t/* Initialize software ring entries */\n\trxq->rx_mbuf_alloc = 0;\n\tfor (idx = 0; idx < rxq->nb_rx_desc; idx = NEXT_RX_BD(idx)) {\n\t\tmbuf = bnx2x_rxmbuf_alloc(mp);\n\t\tif (NULL == mbuf) {\n\t\t\tPMD_RX_LOG(ERR, \"RX mbuf alloc failed queue_id=%u, idx=%d\",\n\t\t\t\t (unsigned)rxq->queue_id, idx);\n\t\t\tbnx2x_rx_queue_release(rxq);\n\t\t\treturn (-ENOMEM);\n\t\t}\n\t\trxq->sw_ring[idx] = mbuf;\n\t\trxq->rx_ring[idx] = mbuf->buf_physaddr;\n\t\trxq->rx_mbuf_alloc++;\n\t}\n\trxq->pkt_first_seg = NULL;\n\trxq->pkt_last_seg = NULL;\n\trxq->rx_bd_head = 0;\n\trxq->rx_bd_tail = idx;\n\n\t/* Allocate CQ chain. */\n\tdma_size = BNX2X_RX_CHAIN_PAGE_SZ * rxq->nb_cq_pages;\n\tdma = ring_dma_zone_reserve(dev, \"bnx2x_rcq\", queue_idx, dma_size, socket_id);\n\tif (NULL == dma) {\n\t\tPMD_RX_LOG(ERR, \"RCQ alloc failed\");\n\t\treturn (-ENOMEM);\n\t}\n\tfp->rx_comp_mapping = rxq->cq_ring_phys_addr = (uint64_t)dma->phys_addr;\n\trxq->cq_ring = (union eth_rx_cqe*)dma->addr;\n\n\t/* Link the CQ chain pages. */\n\tfor (j = 1; j <= rxq->nb_cq_pages; j++) {\n\t\tnextpg = &rxq->cq_ring[TOTAL_RCQ_ENTRIES_PER_PAGE * j - 1].next_page_cqe;\n\t\tbusaddr = rxq->cq_ring_phys_addr + BNX2X_PAGE_SIZE * (j % rxq->nb_cq_pages);\n\t\tnextpg->addr_hi = rte_cpu_to_le_32(U64_HI(busaddr));\n\t\tnextpg->addr_lo = rte_cpu_to_le_32(U64_LO(busaddr));\n\t}\n\trxq->rx_cq_head = 0;\n\trxq->rx_cq_tail = TOTAL_RCQ_ENTRIES(rxq);\n\n\tdev->data->rx_queues[queue_idx] = rxq;\n\tif (!sc->rx_queues) sc->rx_queues = dev->data->rx_queues;\n\n\treturn 0;\n}\n\nstatic void\nbnx2x_tx_queue_release(struct bnx2x_tx_queue *tx_queue)\n{\n\tuint16_t i;\n\tstruct rte_mbuf **sw_ring;\n\n\tif (NULL != tx_queue) {\n\n\t\tsw_ring = tx_queue->sw_ring;\n\t\tif (NULL != sw_ring) {\n\t\t\tfor (i = 0; i < tx_queue->nb_tx_desc; i++) {\n\t\t\t\tif (NULL != sw_ring[i])\n\t\t\t\t\trte_pktmbuf_free(sw_ring[i]);\n\t\t\t}\n\t\t\trte_free(sw_ring);\n\t\t}\n\t\trte_free(tx_queue);\n\t}\n}\n\nvoid\nbnx2x_dev_tx_queue_release(void *txq)\n{\n\tbnx2x_tx_queue_release(txq);\n}\n\nstatic uint16_t\nbnx2x_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n{\n\tstruct bnx2x_tx_queue *txq;\n\tstruct bnx2x_softc *sc;\n\tstruct bnx2x_fastpath *fp;\n\tuint32_t burst, nb_tx;\n\tstruct rte_mbuf **m = tx_pkts;\n\tint ret;\n\n\ttxq = p_txq;\n\tsc = txq->sc;\n\tfp = &sc->fp[txq->queue_id];\n\n\tnb_tx = nb_pkts;\n\n\tdo {\n\t\tburst = RTE_MIN(nb_pkts, RTE_PMD_BNX2X_TX_MAX_BURST);\n\n\t\tret = bnx2x_tx_encap(txq, m, burst);\n\t\tif (unlikely(ret)) {\n\t\t\tPMD_TX_LOG(ERR, \"tx_encap failed!\");\n\t\t}\n\n\t\tbnx2x_update_fp_sb_idx(fp);\n\n\t\tif ((txq->nb_tx_desc - txq->nb_tx_avail) > txq->tx_free_thresh) {\n\t\t\tbnx2x_txeof(sc, fp);\n\t\t}\n\n\t\tif (unlikely(ret == ENOMEM)) {\n\t\t\tbreak;\n\t\t}\n\n\t\tm += burst;\n\t\tnb_pkts -= burst;\n\n\t} while (nb_pkts);\n\n\treturn nb_tx - nb_pkts;\n}\n\nint\nbnx2x_dev_tx_queue_setup(struct rte_eth_dev *dev,\n\t\t uint16_t queue_idx,\n\t\t uint16_t nb_desc,\n\t\t unsigned int socket_id,\n\t\t const struct rte_eth_txconf *tx_conf)\n{\n\tuint16_t i;\n\tunsigned int tsize;\n\tconst struct rte_memzone *tz;\n\tstruct bnx2x_tx_queue *txq;\n\tstruct eth_tx_next_bd *tx_n_bd;\n\tuint64_t busaddr;\n\tstruct bnx2x_softc *sc = dev->data->dev_private;\n\tstruct bnx2x_fastpath *fp = &sc->fp[queue_idx];\n\n\t/* First allocate the tx queue data structure */\n\ttxq = rte_zmalloc(\"ethdev TX queue\", sizeof(struct bnx2x_tx_queue),\n\t\t\t RTE_CACHE_LINE_SIZE);\n\tif (txq == NULL)\n\t\treturn (-ENOMEM);\n\ttxq->sc = sc;\n\n\ttxq->nb_tx_pages = 1;\n\twhile (USABLE_TX_BD(txq) < nb_desc)\n\t\ttxq->nb_tx_pages <<= 1;\n\n\ttxq->nb_tx_desc = TOTAL_TX_BD(txq);\n\tsc->tx_ring_size = TOTAL_TX_BD(txq);\n\n\ttxq->tx_free_thresh = tx_conf->tx_free_thresh ?\n\t\ttx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH;\n\n\tPMD_INIT_LOG(DEBUG, \"fp[%02d] req_bd=%u, thresh=%u, usable_bd=%lu, \"\n\t\t \"total_bd=%lu, tx_pages=%u\",\n\t\t queue_idx, nb_desc, txq->tx_free_thresh, USABLE_TX_BD(txq),\n\t\t TOTAL_TX_BD(txq), txq->nb_tx_pages);\n\n\t/* Allocate TX ring hardware descriptors */\n\ttsize = txq->nb_tx_desc * sizeof(union eth_tx_bd_types);\n\ttz = ring_dma_zone_reserve(dev, \"tx_hw_ring\", queue_idx, tsize, socket_id);\n\tif (tz == NULL) {\n\t\tbnx2x_tx_queue_release(txq);\n\t\treturn (-ENOMEM);\n\t}\n\tfp->tx_desc_mapping = txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;\n\ttxq->tx_ring = (union eth_tx_bd_types *) tz->addr;\n\tmemset(txq->tx_ring, 0, tsize);\n\n\t/* Allocate software ring */\n\ttsize = txq->nb_tx_desc * sizeof(struct rte_mbuf *);\n\ttxq->sw_ring = rte_zmalloc(\"tx_sw_ring\", tsize,\n\t\t\t\t RTE_CACHE_LINE_SIZE);\n\tif (txq->sw_ring == NULL) {\n\t\tbnx2x_tx_queue_release(txq);\n\t\treturn (-ENOMEM);\n\t}\n\n\t/* PMD_DRV_LOG(DEBUG, \"sw_ring=%p hw_ring=%p dma_addr=0x%\"PRIx64,\n\t txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr); */\n\n\t/* Link TX pages */\n\tfor (i = 1; i <= txq->nb_tx_pages; i++) {\n\t\ttx_n_bd = &txq->tx_ring[TOTAL_TX_BD_PER_PAGE * i - 1].next_bd;\n\t\tbusaddr = txq->tx_ring_phys_addr + BNX2X_PAGE_SIZE * (i % txq->nb_tx_pages);\n\t\ttx_n_bd->addr_hi = rte_cpu_to_le_32(U64_HI(busaddr));\n\t\ttx_n_bd->addr_lo = rte_cpu_to_le_32(U64_LO(busaddr));\n\t\t/* PMD_DRV_LOG(DEBUG, \"link tx page %lu\", (TOTAL_TX_BD_PER_PAGE * i - 1)); */\n\t}\n\n\ttxq->queue_id = queue_idx;\n\ttxq->port_id = dev->data->port_id;\n\ttxq->tx_pkt_tail = 0;\n\ttxq->tx_pkt_head = 0;\n\ttxq->tx_bd_tail = 0;\n\ttxq->tx_bd_head = 0;\n\ttxq->nb_tx_avail = txq->nb_tx_desc;\n\tdev->tx_pkt_burst = bnx2x_xmit_pkts;\n\tdev->data->tx_queues[queue_idx] = txq;\n\tif (!sc->tx_queues) sc->tx_queues = dev->data->tx_queues;\n\n\treturn 0;\n}\n\nstatic inline void\nbnx2x_upd_rx_prod_fast(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n\t\tuint16_t rx_bd_prod, uint16_t rx_cq_prod)\n{\n\tunion ustorm_eth_rx_producers rx_prods;\n\n\trx_prods.prod.bd_prod = rx_bd_prod;\n\trx_prods.prod.cqe_prod = rx_cq_prod;\n\n\tREG_WR(sc, fp->ustorm_rx_prods_offset, rx_prods.raw_data[0]);\n}\n\nstatic uint16_t\nbnx2x_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n{\n\tstruct bnx2x_rx_queue *rxq = p_rxq;\n\tstruct bnx2x_softc *sc = rxq->sc;\n\tstruct bnx2x_fastpath *fp = &sc->fp[rxq->queue_id];\n\tuint32_t nb_rx = 0;\n\tuint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;\n\tuint16_t bd_cons, bd_prod;\n\tstruct rte_mbuf *new_mb;\n\tuint16_t rx_pref;\n\tstruct eth_fast_path_rx_cqe *cqe_fp;\n\tuint16_t len, pad;\n\tstruct rte_mbuf *rx_mb = NULL;\n\n\thw_cq_cons = le16toh(*fp->rx_cq_cons_sb);\n\tif ((hw_cq_cons & USABLE_RCQ_ENTRIES_PER_PAGE) ==\n\t\t\tUSABLE_RCQ_ENTRIES_PER_PAGE) {\n\t\t++hw_cq_cons;\n\t}\n\n\tbd_cons = rxq->rx_bd_head;\n\tbd_prod = rxq->rx_bd_tail;\n\tsw_cq_cons = rxq->rx_cq_head;\n\tsw_cq_prod = rxq->rx_cq_tail;\n\n\twhile (nb_rx < nb_pkts && sw_cq_cons != hw_cq_cons) {\n\n\t\tbd_prod &= MAX_RX_BD(rxq);\n\t\tbd_cons &= MAX_RX_BD(rxq);\n\n\t\tcqe_fp = &rxq->cq_ring[sw_cq_cons & MAX_RX_BD(rxq)].fast_path_cqe;\n\n\t\tif (unlikely(CQE_TYPE_SLOW(cqe_fp->type_error_flags & ETH_FAST_PATH_RX_CQE_TYPE))) {\n\t\t\tPMD_RX_LOG(ERR, \"slowpath event during traffic processing\");\n\t\t\tbreak;\n\t\t}\n\n\t\tif (unlikely(cqe_fp->type_error_flags & ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {\n\t\t\tPMD_RX_LOG(ERR, \"flags 0x%x rx packet %u\",\n\t\t\t\t\tcqe_fp->type_error_flags, sw_cq_cons);\n\t\t\tgoto next_rx;\n\t\t}\n\n\t\tlen = cqe_fp->pkt_len_or_gro_seg_len;\n\t\tpad = cqe_fp->placement_offset;\n\n\t\tnew_mb = bnx2x_rxmbuf_alloc(rxq->mb_pool);\n\t\tif (unlikely(!new_mb)) {\n\t\t\tPMD_RX_LOG(ERR, \"mbuf alloc fail fp[%02d]\", fp->index);\n\t\t\tgoto next_rx;\n\t\t}\n\n\t\trx_mb = rxq->sw_ring[bd_cons];\n\t\trxq->sw_ring[bd_cons] = new_mb;\n\t\trxq->rx_ring[bd_prod] = new_mb->buf_physaddr;\n\n\t\trx_pref = NEXT_RX_BD(bd_cons) & MAX_RX_BD(rxq);\n\t\trte_prefetch0(rxq->sw_ring[rx_pref]);\n\t\tif ((rx_pref & 0x3) == 0) {\n\t\t\trte_prefetch0(&rxq->rx_ring[rx_pref]);\n\t\t\trte_prefetch0(&rxq->sw_ring[rx_pref]);\n\t\t}\n\n\t\trx_mb->data_off = pad;\n\t\trx_mb->nb_segs = 1;\n\t\trx_mb->next = NULL;\n\t\trx_mb->pkt_len = rx_mb->data_len = len;\n\t\trx_mb->port = rxq->port_id;\n\t\trx_mb->buf_len = len + pad;\n\t\trte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));\n\n\t\t/*\n\t\t * If we received a packet with a vlan tag,\n\t\t * attach that information to the packet.\n\t\t */\n\t\tif (cqe_fp->pars_flags.flags & PARSING_FLAGS_VLAN) {\n\t\t\trx_mb->vlan_tci = cqe_fp->vlan_tag;\n\t\t\trx_mb->ol_flags |= PKT_RX_VLAN_PKT;\n\t\t}\n\n\t\trx_pkts[nb_rx] = rx_mb;\n\t\tnb_rx++;\n\n\t\t/* limit spinning on the queue */\n\t\tif (unlikely(nb_rx == sc->rx_budget)) {\n\t\t\tPMD_RX_LOG(ERR, \"Limit spinning on the queue\");\n\t\t\tbreak;\n\t\t}\n\nnext_rx:\n\t\tbd_cons = NEXT_RX_BD(bd_cons);\n\t\tbd_prod = NEXT_RX_BD(bd_prod);\n\t\tsw_cq_prod = NEXT_RCQ_IDX(sw_cq_prod);\n\t\tsw_cq_cons = NEXT_RCQ_IDX(sw_cq_cons);\n\t}\n\trxq->rx_bd_head = bd_cons;\n\trxq->rx_bd_tail = bd_prod;\n\trxq->rx_cq_head = sw_cq_cons;\n\trxq->rx_cq_tail = sw_cq_prod;\n\n\tbnx2x_upd_rx_prod_fast(sc, fp, bd_prod, sw_cq_prod);\n\n\treturn nb_rx;\n}\n\nint\nbnx2x_dev_rx_init(struct rte_eth_dev *dev)\n{\n\tdev->rx_pkt_burst = bnx2x_recv_pkts;\n\n\treturn 0;\n}\n\nvoid\nbnx2x_dev_clear_queues(struct rte_eth_dev *dev)\n{\n\tuint8_t i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tstruct bnx2x_tx_queue *txq = dev->data->tx_queues[i];\n\t\tif (txq != NULL) {\n\t\t\tbnx2x_tx_queue_release(txq);\n\t\t\tdev->data->tx_queues[i] = NULL;\n\t\t}\n\t}\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tstruct bnx2x_rx_queue *rxq = dev->data->rx_queues[i];\n\t\tif (rxq != NULL) {\n\t\t\tbnx2x_rx_queue_release(rxq);\n\t\t\tdev->data->rx_queues[i] = NULL;\n\t\t}\n\t}\n}\n" }, { "path": "drivers/net/bnx2x/bnx2x_rxtx.h", "content": "/*\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n *\n * All rights reserved.\n */\n\n#ifndef _BNX2X_RXTX_H_\n#define _BNX2X_RXTX_H_\n\n\n#define DEFAULT_RX_FREE_THRESH 0\n#define DEFAULT_TX_FREE_THRESH 512\n#define RTE_PMD_BNX2X_TX_MAX_BURST 1\n\n/**\n * Structure associated with each descriptor of the RX ring of a RX queue.\n */\nstruct bnx2x_rx_entry {\n\tstruct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */\n};\n\n/**\n * Structure associated with each RX queue.\n */\nstruct bnx2x_rx_queue {\n\tstruct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */\n\tunion eth_rx_cqe *cq_ring; /**< RCQ ring virtual address. */\n\tuint64_t cq_ring_phys_addr; /**< RCQ ring DMA address. */\n\tuint64_t *rx_ring; /**< RX ring virtual address. */\n\tuint64_t rx_ring_phys_addr; /**< RX ring DMA address. */\n\tstruct rte_mbuf **sw_ring; /**< address of RX software ring. */\n\tstruct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */\n\tstruct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */\n\tuint16_t nb_cq_pages; /**< number of RCQ pages. */\n\tuint16_t nb_rx_desc; /**< number of RX descriptors. */\n\tuint16_t nb_rx_pages; /**< number of RX pages. */\n\tuint16_t rx_bd_head; /**< Index of current rx bd. */\n\tuint16_t rx_bd_tail; /**< Index of last rx bd. */\n\tuint16_t rx_cq_head; /**< Index of current rcq bd. */\n\tuint16_t rx_cq_tail; /**< Index of last rcq bd. */\n\tuint16_t nb_rx_hold; /**< number of held free RX desc. */\n\tuint16_t rx_free_thresh; /**< max free RX desc to hold. */\n\tuint16_t queue_id; /**< RX queue index. */\n\tuint8_t port_id; /**< Device port identifier. */\n\tuint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */\n\tstruct bnx2x_softc *sc; /**< Ptr to dev_private data. */\n\tuint64_t rx_mbuf_alloc; /**< Number of allocated mbufs. */\n};\n\n/**\n * Structure associated with each TX queue.\n */\nstruct bnx2x_tx_queue {\n\t/** TX ring virtual address. */\n\tunion eth_tx_bd_types *tx_ring; /**< TX ring virtual address. */\n\tuint64_t tx_ring_phys_addr; /**< TX ring DMA address. */\n\tstruct rte_mbuf **sw_ring; /**< virtual address of SW ring. */\n\tuint16_t tx_pkt_tail; /**< Index of current tx pkt. */\n\tuint16_t tx_pkt_head; /**< Index of last pkt counted by txeof. */\n\tuint16_t tx_bd_tail; /**< Index of current tx bd. */\n\tuint16_t tx_bd_head; /**< Index of last bd counted by txeof. */\n\tuint16_t nb_tx_desc; /**< number of TX descriptors. */\n\tuint16_t tx_free_thresh; /**< minimum TX before freeing. */\n\tuint16_t nb_tx_avail; /**< Number of TX descriptors available. */\n\tuint16_t nb_tx_pages; /**< number of TX pages */\n\tuint16_t queue_id; /**< TX queue index. */\n\tuint8_t port_id; /**< Device port identifier. */\n\tstruct bnx2x_softc *sc; /**< Ptr to dev_private data */\n};\n\nint bnx2x_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n\t\t\t uint16_t nb_rx_desc, unsigned int socket_id,\n\t\t\t const struct rte_eth_rxconf *rx_conf,\n\t\t\t struct rte_mempool *mb_pool);\n\nint bnx2x_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n\t\t\t uint16_t nb_tx_desc, unsigned int socket_id,\n\t\t\t const struct rte_eth_txconf *tx_conf);\n\nvoid bnx2x_dev_rx_queue_release(void *rxq);\nvoid bnx2x_dev_tx_queue_release(void *txq);\nint bnx2x_dev_rx_init(struct rte_eth_dev *dev);\nvoid bnx2x_dev_clear_queues(struct rte_eth_dev *dev);\n\n#endif /* _BNX2X_RXTX_H_ */\n" }, { "path": "drivers/net/bnx2x/bnx2x_stats.c", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"bnx2x.h\"\n#include \"bnx2x_stats.h\"\n\n#ifdef __i386__\n#define BITS_PER_LONG 32\n#else\n#define BITS_PER_LONG 64\n#endif\n\nstatic inline uint16_t\nbnx2x_get_port_stats_dma_len(struct bnx2x_softc *sc)\n{\n\tuint16_t res = 0;\n\tuint32_t size;\n\n\t/* 'newest' convention - shmem2 contains the size of the port stats */\n\tif (SHMEM2_HAS(sc, sizeof_port_stats)) {\n\t\tsize = SHMEM2_RD(sc, sizeof_port_stats);\n\t\tif (size) {\n\t\t\tres = size;\n\t\t}\n\n\t\t/* prevent newer BC from causing buffer overflow */\n\t\tif (res > sizeof(struct host_port_stats)) {\n\t\t\tres = sizeof(struct host_port_stats);\n\t\t}\n\t}\n\n\t/*\n\t * Older convention - all BCs support the port stats fields up until\n\t * the 'not_used' field\n\t */\n\tif (!res) {\n\t\tres = (offsetof(struct host_port_stats, not_used) + 4);\n\n\t\t/* if PFC stats are supported by the MFW, DMA them as well */\n\t\tif (sc->devinfo.bc_ver >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) {\n\t\t\tres += (offsetof(struct host_port_stats, pfc_frames_rx_lo) -\n\t\t\t\toffsetof(struct host_port_stats, pfc_frames_tx_hi) + 4);\n\t\t}\n\t}\n\n\tres >>= 2;\n\n\treturn res;\n}\n\n/*\n * Init service functions\n */\n\n/*\n * Post the next statistics ramrod. Protect it with the lock in\n * order to ensure the strict order between statistics ramrods\n * (each ramrod has a sequence number passed in a\n * sc->fw_stats_req->hdr.drv_stats_counter and ramrods must be\n * sent in order).\n */\nstatic void\nbnx2x_storm_stats_post(struct bnx2x_softc *sc)\n{\n\tint rc;\n\n\tif (!sc->stats_pending) {\n\t\tif (sc->stats_pending) {\n\t\t\treturn;\n\t\t}\n\n\t\tsc->fw_stats_req->hdr.drv_stats_counter =\n\t\t\thtole16(sc->stats_counter++);\n\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t\"sending statistics ramrod %d\",\n\t\t\t\tle16toh(sc->fw_stats_req->hdr.drv_stats_counter));\n\n\t\t/* adjust the ramrod to include VF queues statistics */\n\n\t\t/* send FW stats ramrod */\n\t\trc = bnx2x_sp_post(sc, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,\n\t\t\t\tU64_HI(sc->fw_stats_req_mapping),\n\t\t\t\tU64_LO(sc->fw_stats_req_mapping),\n\t\t\t\tNONE_CONNECTION_TYPE);\n\t\tif (rc == 0) {\n\t\t\tsc->stats_pending = 1;\n\t\t}\n\t}\n}\n\nstatic void\nbnx2x_hw_stats_post(struct bnx2x_softc *sc)\n{\n\tstruct dmae_command *dmae = &sc->stats_dmae;\n\tuint32_t *stats_comp = BNX2X_SP(sc, stats_comp);\n\tint loader_idx;\n\tuint32_t opcode;\n\n\t*stats_comp = DMAE_COMP_VAL;\n\tif (CHIP_REV_IS_SLOW(sc)) {\n\t\treturn;\n\t}\n\n\t/* Update MCP's statistics if possible */\n\tif (sc->func_stx) {\n\t\trte_memcpy(BNX2X_SP(sc, func_stats), &sc->func_stats,\n\t\t\t\tsizeof(sc->func_stats));\n\t}\n\n\t/* loader */\n\tif (sc->executer_idx) {\n\t\tloader_idx = PMF_DMAE_C(sc);\n\t\topcode = bnx2x_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC,\n\t\t\t\tTRUE, DMAE_COMP_GRC);\n\t\topcode = bnx2x_dmae_opcode_clr_src_reset(opcode);\n\n\t\tmemset(dmae, 0, sizeof(struct dmae_command));\n\t\tdmae->opcode = opcode;\n\t\tdmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, dmae[0]));\n\t\tdmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, dmae[0]));\n\t\tdmae->dst_addr_lo = ((DMAE_REG_CMD_MEM +\n\t\t\t\t\tsizeof(struct dmae_command) *\n\t\t\t\t\t(loader_idx + 1)) >> 2);\n\t\tdmae->dst_addr_hi = 0;\n\t\tdmae->len = sizeof(struct dmae_command) >> 2;\n\t\tdmae->comp_addr_lo = (dmae_reg_go_c[loader_idx + 1] >> 2);\n\t\tdmae->comp_addr_hi = 0;\n\t\tdmae->comp_val = 1;\n\n\t\t*stats_comp = 0;\n\t\tbnx2x_post_dmae(sc, dmae, loader_idx);\n\t} else if (sc->func_stx) {\n\t\t*stats_comp = 0;\n\t\tbnx2x_post_dmae(sc, dmae, INIT_DMAE_C(sc));\n\t}\n}\n\nstatic int\nbnx2x_stats_comp(struct bnx2x_softc *sc)\n{\n\tuint32_t *stats_comp = BNX2X_SP(sc, stats_comp);\n\tint cnt = 10;\n\n\twhile (*stats_comp != DMAE_COMP_VAL) {\n\t\tif (!cnt) {\n\t\t\tPMD_DRV_LOG(ERR, \"Timeout waiting for stats finished\");\n\t\t\tbreak;\n\t\t}\n\n\t\tcnt--;\n\t\tDELAY(1000);\n\t}\n\n\treturn 1;\n}\n\n/*\n * Statistics service functions\n */\n\nstatic void\nbnx2x_stats_pmf_update(struct bnx2x_softc *sc)\n{\n\tstruct dmae_command *dmae;\n\tuint32_t opcode;\n\tint loader_idx = PMF_DMAE_C(sc);\n\tuint32_t *stats_comp = BNX2X_SP(sc, stats_comp);\n\n\tif (sc->devinfo.bc_ver <= 0x06001400) {\n\t\t/*\n\t\t * Bootcode v6.0.21 fixed a GRC timeout that occurs when accessing\n\t\t * BRB registers while the BRB block is in reset. The DMA transfer\n\t\t * below triggers this issue resulting in the DMAE to stop\n\t\t * functioning. Skip this initial stats transfer for old bootcode\n\t\t * versions <= 6.0.20.\n\t\t */\n\t\treturn;\n\t}\n\t/* sanity */\n\tif (!sc->port.pmf || !sc->port.port_stx) {\n\t\tPMD_DRV_LOG(ERR, \"BUG!\");\n\t\treturn;\n\t}\n\n\tsc->executer_idx = 0;\n\n\topcode = bnx2x_dmae_opcode(sc, DMAE_SRC_GRC, DMAE_DST_PCI, FALSE, 0);\n\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\tdmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);\n\tdmae->src_addr_lo = (sc->port.port_stx >> 2);\n\tdmae->src_addr_hi = 0;\n\tdmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, port_stats));\n\tdmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, port_stats));\n\tdmae->len = DMAE_LEN32_RD_MAX;\n\tdmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);\n\tdmae->comp_addr_hi = 0;\n\tdmae->comp_val = 1;\n\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\tdmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);\n\tdmae->src_addr_lo = ((sc->port.port_stx >> 2) + DMAE_LEN32_RD_MAX);\n\tdmae->src_addr_hi = 0;\n\tdmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, port_stats) +\n\t\t\tDMAE_LEN32_RD_MAX * 4);\n\tdmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, port_stats) +\n\t\t\tDMAE_LEN32_RD_MAX * 4);\n\tdmae->len = (bnx2x_get_port_stats_dma_len(sc) - DMAE_LEN32_RD_MAX);\n\n\tdmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, stats_comp));\n\tdmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, stats_comp));\n\tdmae->comp_val = DMAE_COMP_VAL;\n\n\t*stats_comp = 0;\n\tbnx2x_hw_stats_post(sc);\n\tbnx2x_stats_comp(sc);\n}\n\nstatic void\nbnx2x_port_stats_init(struct bnx2x_softc *sc)\n{\n struct dmae_command *dmae;\n int port = SC_PORT(sc);\n uint32_t opcode;\n int loader_idx = PMF_DMAE_C(sc);\n uint32_t mac_addr;\n uint32_t *stats_comp = BNX2X_SP(sc, stats_comp);\n\n /* sanity */\n if (!sc->link_vars.link_up || !sc->port.pmf) {\n\tPMD_DRV_LOG(ERR, \"BUG!\");\n\treturn;\n }\n\n sc->executer_idx = 0;\n\n /* MCP */\n opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC,\n\t\t\t TRUE, DMAE_COMP_GRC);\n\n if (sc->port.port_stx) {\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\tdmae->opcode = opcode;\n\tdmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, port_stats));\n\tdmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, port_stats));\n\tdmae->dst_addr_lo = sc->port.port_stx >> 2;\n\tdmae->dst_addr_hi = 0;\n\tdmae->len = bnx2x_get_port_stats_dma_len(sc);\n\tdmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;\n\tdmae->comp_addr_hi = 0;\n\tdmae->comp_val = 1;\n }\n\n if (sc->func_stx) {\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\tdmae->opcode = opcode;\n\tdmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, func_stats));\n\tdmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, func_stats));\n\tdmae->dst_addr_lo = (sc->func_stx >> 2);\n\tdmae->dst_addr_hi = 0;\n\tdmae->len = (sizeof(struct host_func_stats) >> 2);\n\tdmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);\n\tdmae->comp_addr_hi = 0;\n\tdmae->comp_val = 1;\n }\n\n /* MAC */\n opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_GRC, DMAE_DST_PCI,\n\t\t\t TRUE, DMAE_COMP_GRC);\n\n /* EMAC is special */\n if (sc->link_vars.mac_type == ELINK_MAC_TYPE_EMAC) {\n\tmac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);\n\n\t/* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\tdmae->opcode = opcode;\n\tdmae->src_addr_lo = (mac_addr + EMAC_REG_EMAC_RX_STAT_AC) >> 2;\n\tdmae->src_addr_hi = 0;\n\tdmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, mac_stats));\n\tdmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, mac_stats));\n\tdmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;\n\tdmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);\n\tdmae->comp_addr_hi = 0;\n\tdmae->comp_val = 1;\n\n\t/* EMAC_REG_EMAC_RX_STAT_AC_28 */\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\tdmae->opcode = opcode;\n\tdmae->src_addr_lo = ((mac_addr + EMAC_REG_EMAC_RX_STAT_AC_28) >> 2);\n\tdmae->src_addr_hi = 0;\n\tdmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, mac_stats) +\n\t\t\t\t offsetof(struct emac_stats,\n\t\t\t\t\t rx_stat_falsecarriererrors));\n\tdmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, mac_stats) +\n\t\t\t\t offsetof(struct emac_stats,\n\t\t\t\t\t rx_stat_falsecarriererrors));\n\tdmae->len = 1;\n\tdmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);\n\tdmae->comp_addr_hi = 0;\n\tdmae->comp_val = 1;\n\n\t/* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\tdmae->opcode = opcode;\n\tdmae->src_addr_lo = ((mac_addr + EMAC_REG_EMAC_TX_STAT_AC) >> 2);\n\tdmae->src_addr_hi = 0;\n\tdmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, mac_stats) +\n\t\t\t\t offsetof(struct emac_stats,\n\t\t\t\t\t tx_stat_ifhcoutoctets));\n\tdmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, mac_stats) +\n\t\t\t\t offsetof(struct emac_stats,\n\t\t\t\t\t tx_stat_ifhcoutoctets));\n\tdmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;\n\tdmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);\n\tdmae->comp_addr_hi = 0;\n\tdmae->comp_val = 1;\n } else {\n\tuint32_t tx_src_addr_lo, rx_src_addr_lo;\n\tuint16_t rx_len, tx_len;\n\n\t/* configure the params according to MAC type */\n\tswitch (sc->link_vars.mac_type) {\n\tcase ELINK_MAC_TYPE_BMAC:\n\t mac_addr = (port) ? NIG_REG_INGRESS_BMAC1_MEM :\n\t\t\t\tNIG_REG_INGRESS_BMAC0_MEM;\n\n\t /* BIGMAC_REGISTER_TX_STAT_GTPKT ..\n\t BIGMAC_REGISTER_TX_STAT_GTBYT */\n\t if (CHIP_IS_E1x(sc)) {\n\t\ttx_src_addr_lo =\n\t\t ((mac_addr + BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2);\n\t\ttx_len = ((8 + BIGMAC_REGISTER_TX_STAT_GTBYT -\n\t\t\t BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2);\n\t\trx_src_addr_lo =\n\t\t ((mac_addr + BIGMAC_REGISTER_RX_STAT_GR64) >> 2);\n\t\trx_len = ((8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -\n\t\t\t BIGMAC_REGISTER_RX_STAT_GR64) >> 2);\n\t } else {\n\t\ttx_src_addr_lo =\n\t\t ((mac_addr + BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2);\n\t\ttx_len = ((8 + BIGMAC2_REGISTER_TX_STAT_GTBYT -\n\t\t\t BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2);\n\t\trx_src_addr_lo =\n\t\t ((mac_addr + BIGMAC2_REGISTER_RX_STAT_GR64) >> 2);\n\t\trx_len = ((8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ -\n\t\t\t BIGMAC2_REGISTER_RX_STAT_GR64) >> 2);\n\t }\n\n\t break;\n\n\tcase ELINK_MAC_TYPE_UMAC: /* handled by MSTAT */\n\tcase ELINK_MAC_TYPE_XMAC: /* handled by MSTAT */\n\tdefault:\n\t mac_addr = (port) ? GRCBASE_MSTAT1 : GRCBASE_MSTAT0;\n\t tx_src_addr_lo = ((mac_addr + MSTAT_REG_TX_STAT_GTXPOK_LO) >> 2);\n\t rx_src_addr_lo = ((mac_addr + MSTAT_REG_RX_STAT_GR64_LO) >> 2);\n\t tx_len =\n\t\t(sizeof(sc->sp->mac_stats.mstat_stats.stats_tx) >> 2);\n\t rx_len =\n\t\t(sizeof(sc->sp->mac_stats.mstat_stats.stats_rx) >> 2);\n\t break;\n\t}\n\n\t/* TX stats */\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\tdmae->opcode = opcode;\n\tdmae->src_addr_lo = tx_src_addr_lo;\n\tdmae->src_addr_hi = 0;\n\tdmae->len = tx_len;\n\tdmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, mac_stats));\n\tdmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, mac_stats));\n\tdmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;\n\tdmae->comp_addr_hi = 0;\n\tdmae->comp_val = 1;\n\n\t/* RX stats */\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\tdmae->opcode = opcode;\n\tdmae->src_addr_hi = 0;\n\tdmae->src_addr_lo = rx_src_addr_lo;\n\tdmae->dst_addr_lo =\n\t U64_LO(BNX2X_SP_MAPPING(sc, mac_stats) + (tx_len << 2));\n\tdmae->dst_addr_hi =\n\t U64_HI(BNX2X_SP_MAPPING(sc, mac_stats) + (tx_len << 2));\n\tdmae->len = rx_len;\n\tdmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;\n\tdmae->comp_addr_hi = 0;\n\tdmae->comp_val = 1;\n }\n\n /* NIG */\n if (!CHIP_IS_E3(sc)) {\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\tdmae->opcode = opcode;\n\tdmae->src_addr_lo =\n\t (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :\n\t\t NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;\n\tdmae->src_addr_hi = 0;\n\tdmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, nig_stats) +\n\t\t\t\t offsetof(struct nig_stats,\n\t\t\t\t\t egress_mac_pkt0_lo));\n\tdmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, nig_stats) +\n\t\t\t\t offsetof(struct nig_stats,\n\t\t\t\t\t egress_mac_pkt0_lo));\n\tdmae->len = ((2 * sizeof(uint32_t)) >> 2);\n\tdmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);\n\tdmae->comp_addr_hi = 0;\n\tdmae->comp_val = 1;\n\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\tdmae->opcode = opcode;\n\tdmae->src_addr_lo =\n\t (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :\n\t\t NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;\n\tdmae->src_addr_hi = 0;\n\tdmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, nig_stats) +\n\t\t\t\t offsetof(struct nig_stats,\n\t\t\t\t\t egress_mac_pkt1_lo));\n\tdmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, nig_stats) +\n\t\t\t\t offsetof(struct nig_stats,\n\t\t\t\t\t egress_mac_pkt1_lo));\n\tdmae->len = ((2 * sizeof(uint32_t)) >> 2);\n\tdmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);\n\tdmae->comp_addr_hi = 0;\n\tdmae->comp_val = 1;\n }\n\n dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n dmae->opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_GRC, DMAE_DST_PCI,\n\t\t\t\t TRUE, DMAE_COMP_PCI);\n dmae->src_addr_lo =\n\t(port ? NIG_REG_STAT1_BRB_DISCARD :\n\t\tNIG_REG_STAT0_BRB_DISCARD) >> 2;\n dmae->src_addr_hi = 0;\n dmae->dst_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, nig_stats));\n dmae->dst_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, nig_stats));\n dmae->len = (sizeof(struct nig_stats) - 4*sizeof(uint32_t)) >> 2;\n\n dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, stats_comp));\n dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, stats_comp));\n dmae->comp_val = DMAE_COMP_VAL;\n\n *stats_comp = 0;\n}\n\nstatic void\nbnx2x_func_stats_init(struct bnx2x_softc *sc)\n{\n struct dmae_command *dmae = &sc->stats_dmae;\n uint32_t *stats_comp = BNX2X_SP(sc, stats_comp);\n\n /* sanity */\n if (!sc->func_stx) {\n\tPMD_DRV_LOG(ERR, \"BUG!\");\n\treturn;\n }\n\n sc->executer_idx = 0;\n memset(dmae, 0, sizeof(struct dmae_command));\n\n dmae->opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC,\n\t\t\t\t TRUE, DMAE_COMP_PCI);\n dmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, func_stats));\n dmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, func_stats));\n dmae->dst_addr_lo = (sc->func_stx >> 2);\n dmae->dst_addr_hi = 0;\n dmae->len = (sizeof(struct host_func_stats) >> 2);\n dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, stats_comp));\n dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, stats_comp));\n dmae->comp_val = DMAE_COMP_VAL;\n\n *stats_comp = 0;\n}\n\nstatic void\nbnx2x_stats_start(struct bnx2x_softc *sc)\n{\n /*\n * VFs travel through here as part of the statistics FSM, but no action\n * is required\n */\n if (IS_VF(sc)) {\n\treturn;\n }\n\n if (sc->port.pmf) {\n\tbnx2x_port_stats_init(sc);\n }\n\n else if (sc->func_stx) {\n\tbnx2x_func_stats_init(sc);\n }\n\n bnx2x_hw_stats_post(sc);\n bnx2x_storm_stats_post(sc);\n}\n\nstatic void\nbnx2x_stats_pmf_start(struct bnx2x_softc *sc)\n{\n bnx2x_stats_comp(sc);\n bnx2x_stats_pmf_update(sc);\n bnx2x_stats_start(sc);\n}\n\nstatic void\nbnx2x_stats_restart(struct bnx2x_softc *sc)\n{\n /*\n * VFs travel through here as part of the statistics FSM, but no action\n * is required\n */\n if (IS_VF(sc)) {\n\treturn;\n }\n\n bnx2x_stats_comp(sc);\n bnx2x_stats_start(sc);\n}\n\nstatic void\nbnx2x_bmac_stats_update(struct bnx2x_softc *sc)\n{\n struct host_port_stats *pstats = BNX2X_SP(sc, port_stats);\n struct bnx2x_eth_stats *estats = &sc->eth_stats;\n struct {\n\tuint32_t lo;\n\tuint32_t hi;\n } diff;\n\n if (CHIP_IS_E1x(sc)) {\n\tstruct bmac1_stats *new = BNX2X_SP(sc, mac_stats.bmac1_stats);\n\n\t/* the macros below will use \"bmac1_stats\" type */\n\tUPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);\n\tUPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);\n\tUPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);\n\tUPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);\n\tUPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);\n\tUPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);\n\tUPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);\n\tUPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);\n\tUPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);\n\n\tUPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);\n\tUPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);\n\tUPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);\n\tUPDATE_STAT64(tx_stat_gt127,\n\t\t tx_stat_etherstatspkts65octetsto127octets);\n\tUPDATE_STAT64(tx_stat_gt255,\n\t\t tx_stat_etherstatspkts128octetsto255octets);\n\tUPDATE_STAT64(tx_stat_gt511,\n\t\t tx_stat_etherstatspkts256octetsto511octets);\n\tUPDATE_STAT64(tx_stat_gt1023,\n\t\t tx_stat_etherstatspkts512octetsto1023octets);\n\tUPDATE_STAT64(tx_stat_gt1518,\n\t\t tx_stat_etherstatspkts1024octetsto1522octets);\n\tUPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);\n\tUPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);\n\tUPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);\n\tUPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);\n\tUPDATE_STAT64(tx_stat_gterr,\n\t\t tx_stat_dot3statsinternalmactransmiterrors);\n\tUPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);\n } else {\n\tstruct bmac2_stats *new = BNX2X_SP(sc, mac_stats.bmac2_stats);\n\tstruct bnx2x_fw_port_stats_old *fwstats = &sc->fw_stats_old;\n\n\t/* the macros below will use \"bmac2_stats\" type */\n\tUPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);\n\tUPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);\n\tUPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);\n\tUPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);\n\tUPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);\n\tUPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);\n\tUPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);\n\tUPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);\n\tUPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);\n\tUPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);\n\tUPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);\n\tUPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);\n\tUPDATE_STAT64(tx_stat_gt127,\n\t\t tx_stat_etherstatspkts65octetsto127octets);\n\tUPDATE_STAT64(tx_stat_gt255,\n\t\t tx_stat_etherstatspkts128octetsto255octets);\n\tUPDATE_STAT64(tx_stat_gt511,\n\t\t tx_stat_etherstatspkts256octetsto511octets);\n\tUPDATE_STAT64(tx_stat_gt1023,\n\t\t tx_stat_etherstatspkts512octetsto1023octets);\n\tUPDATE_STAT64(tx_stat_gt1518,\n\t\t tx_stat_etherstatspkts1024octetsto1522octets);\n\tUPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);\n\tUPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);\n\tUPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);\n\tUPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);\n\tUPDATE_STAT64(tx_stat_gterr,\n\t\t tx_stat_dot3statsinternalmactransmiterrors);\n\tUPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);\n\n\t/* collect PFC stats */\n\tpstats->pfc_frames_tx_hi = new->tx_stat_gtpp_hi;\n\tpstats->pfc_frames_tx_lo = new->tx_stat_gtpp_lo;\n\tADD_64(pstats->pfc_frames_tx_hi, fwstats->pfc_frames_tx_hi,\n\t pstats->pfc_frames_tx_lo, fwstats->pfc_frames_tx_lo);\n\n\tpstats->pfc_frames_rx_hi = new->rx_stat_grpp_hi;\n\tpstats->pfc_frames_rx_lo = new->rx_stat_grpp_lo;\n\tADD_64(pstats->pfc_frames_rx_hi, fwstats->pfc_frames_rx_hi,\n\t pstats->pfc_frames_rx_lo, fwstats->pfc_frames_rx_lo);\n }\n\n estats->pause_frames_received_hi = pstats->mac_stx[1].rx_stat_mac_xpf_hi;\n estats->pause_frames_received_lo = pstats->mac_stx[1].rx_stat_mac_xpf_lo;\n\n estats->pause_frames_sent_hi = pstats->mac_stx[1].tx_stat_outxoffsent_hi;\n estats->pause_frames_sent_lo = pstats->mac_stx[1].tx_stat_outxoffsent_lo;\n\n estats->pfc_frames_received_hi = pstats->pfc_frames_rx_hi;\n estats->pfc_frames_received_lo = pstats->pfc_frames_rx_lo;\n estats->pfc_frames_sent_hi = pstats->pfc_frames_tx_hi;\n estats->pfc_frames_sent_lo = pstats->pfc_frames_tx_lo;\n}\n\nstatic void\nbnx2x_mstat_stats_update(struct bnx2x_softc *sc)\n{\n struct host_port_stats *pstats = BNX2X_SP(sc, port_stats);\n struct bnx2x_eth_stats *estats = &sc->eth_stats;\n struct mstat_stats *new = BNX2X_SP(sc, mac_stats.mstat_stats);\n\n ADD_STAT64(stats_rx.rx_grerb, rx_stat_ifhcinbadoctets);\n ADD_STAT64(stats_rx.rx_grfcs, rx_stat_dot3statsfcserrors);\n ADD_STAT64(stats_rx.rx_grund, rx_stat_etherstatsundersizepkts);\n ADD_STAT64(stats_rx.rx_grovr, rx_stat_dot3statsframestoolong);\n ADD_STAT64(stats_rx.rx_grfrg, rx_stat_etherstatsfragments);\n ADD_STAT64(stats_rx.rx_grxcf, rx_stat_maccontrolframesreceived);\n ADD_STAT64(stats_rx.rx_grxpf, rx_stat_xoffstateentered);\n ADD_STAT64(stats_rx.rx_grxpf, rx_stat_mac_xpf);\n ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_outxoffsent);\n ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_flowcontroldone);\n\n /* collect pfc stats */\n ADD_64(pstats->pfc_frames_tx_hi, new->stats_tx.tx_gtxpp_hi,\n\t pstats->pfc_frames_tx_lo, new->stats_tx.tx_gtxpp_lo);\n ADD_64(pstats->pfc_frames_rx_hi, new->stats_rx.rx_grxpp_hi,\n\t pstats->pfc_frames_rx_lo, new->stats_rx.rx_grxpp_lo);\n\n ADD_STAT64(stats_tx.tx_gt64, tx_stat_etherstatspkts64octets);\n ADD_STAT64(stats_tx.tx_gt127, tx_stat_etherstatspkts65octetsto127octets);\n ADD_STAT64(stats_tx.tx_gt255, tx_stat_etherstatspkts128octetsto255octets);\n ADD_STAT64(stats_tx.tx_gt511, tx_stat_etherstatspkts256octetsto511octets);\n ADD_STAT64(stats_tx.tx_gt1023,\n\t tx_stat_etherstatspkts512octetsto1023octets);\n ADD_STAT64(stats_tx.tx_gt1518,\n\t tx_stat_etherstatspkts1024octetsto1522octets);\n ADD_STAT64(stats_tx.tx_gt2047, tx_stat_mac_2047);\n\n ADD_STAT64(stats_tx.tx_gt4095, tx_stat_mac_4095);\n ADD_STAT64(stats_tx.tx_gt9216, tx_stat_mac_9216);\n ADD_STAT64(stats_tx.tx_gt16383, tx_stat_mac_16383);\n\n ADD_STAT64(stats_tx.tx_gterr, tx_stat_dot3statsinternalmactransmiterrors);\n ADD_STAT64(stats_tx.tx_gtufl, tx_stat_mac_ufl);\n\n estats->etherstatspkts1024octetsto1522octets_hi =\n\tpstats->mac_stx[1].tx_stat_etherstatspkts1024octetsto1522octets_hi;\n estats->etherstatspkts1024octetsto1522octets_lo =\n\tpstats->mac_stx[1].tx_stat_etherstatspkts1024octetsto1522octets_lo;\n\n estats->etherstatspktsover1522octets_hi =\n\tpstats->mac_stx[1].tx_stat_mac_2047_hi;\n estats->etherstatspktsover1522octets_lo =\n\tpstats->mac_stx[1].tx_stat_mac_2047_lo;\n\n ADD_64(estats->etherstatspktsover1522octets_hi,\n\t pstats->mac_stx[1].tx_stat_mac_4095_hi,\n\t estats->etherstatspktsover1522octets_lo,\n\t pstats->mac_stx[1].tx_stat_mac_4095_lo);\n\n ADD_64(estats->etherstatspktsover1522octets_hi,\n\t pstats->mac_stx[1].tx_stat_mac_9216_hi,\n\t estats->etherstatspktsover1522octets_lo,\n\t pstats->mac_stx[1].tx_stat_mac_9216_lo);\n\n ADD_64(estats->etherstatspktsover1522octets_hi,\n\t pstats->mac_stx[1].tx_stat_mac_16383_hi,\n\t estats->etherstatspktsover1522octets_lo,\n\t pstats->mac_stx[1].tx_stat_mac_16383_lo);\n\n estats->pause_frames_received_hi = pstats->mac_stx[1].rx_stat_mac_xpf_hi;\n estats->pause_frames_received_lo = pstats->mac_stx[1].rx_stat_mac_xpf_lo;\n\n estats->pause_frames_sent_hi = pstats->mac_stx[1].tx_stat_outxoffsent_hi;\n estats->pause_frames_sent_lo = pstats->mac_stx[1].tx_stat_outxoffsent_lo;\n\n estats->pfc_frames_received_hi = pstats->pfc_frames_rx_hi;\n estats->pfc_frames_received_lo = pstats->pfc_frames_rx_lo;\n estats->pfc_frames_sent_hi = pstats->pfc_frames_tx_hi;\n estats->pfc_frames_sent_lo = pstats->pfc_frames_tx_lo;\n}\n\nstatic void\nbnx2x_emac_stats_update(struct bnx2x_softc *sc)\n{\n struct emac_stats *new = BNX2X_SP(sc, mac_stats.emac_stats);\n struct host_port_stats *pstats = BNX2X_SP(sc, port_stats);\n struct bnx2x_eth_stats *estats = &sc->eth_stats;\n\n UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);\n UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);\n UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);\n UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);\n UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);\n UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);\n UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);\n UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);\n UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);\n UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);\n UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);\n UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);\n UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);\n UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);\n UPDATE_EXTEND_STAT(tx_stat_outxonsent);\n UPDATE_EXTEND_STAT(tx_stat_outxoffsent);\n UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);\n UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);\n UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);\n UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);\n UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);\n UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);\n UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);\n UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);\n UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);\n UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);\n UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);\n UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);\n UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);\n UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);\n UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);\n\n estats->pause_frames_received_hi =\n\tpstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;\n estats->pause_frames_received_lo =\n\tpstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;\n ADD_64(estats->pause_frames_received_hi,\n\t pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,\n\t estats->pause_frames_received_lo,\n\t pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);\n\n estats->pause_frames_sent_hi =\n\tpstats->mac_stx[1].tx_stat_outxonsent_hi;\n estats->pause_frames_sent_lo =\n\tpstats->mac_stx[1].tx_stat_outxonsent_lo;\n ADD_64(estats->pause_frames_sent_hi,\n\t pstats->mac_stx[1].tx_stat_outxoffsent_hi,\n\t estats->pause_frames_sent_lo,\n\t pstats->mac_stx[1].tx_stat_outxoffsent_lo);\n}\n\nstatic int\nbnx2x_hw_stats_update(struct bnx2x_softc *sc)\n{\n struct nig_stats *new = BNX2X_SP(sc, nig_stats);\n struct nig_stats *old = &(sc->port.old_nig_stats);\n struct host_port_stats *pstats = BNX2X_SP(sc, port_stats);\n struct bnx2x_eth_stats *estats = &sc->eth_stats;\n uint32_t lpi_reg, nig_timer_max;\n struct {\n\tuint32_t lo;\n\tuint32_t hi;\n } diff;\n\n switch (sc->link_vars.mac_type) {\n case ELINK_MAC_TYPE_BMAC:\n\tbnx2x_bmac_stats_update(sc);\n\tbreak;\n\n case ELINK_MAC_TYPE_EMAC:\n\tbnx2x_emac_stats_update(sc);\n\tbreak;\n\n case ELINK_MAC_TYPE_UMAC:\n case ELINK_MAC_TYPE_XMAC:\n\tbnx2x_mstat_stats_update(sc);\n\tbreak;\n\n case ELINK_MAC_TYPE_NONE: /* unreached */\n\tPMD_DRV_LOG(DEBUG,\n\t \"stats updated by DMAE but no MAC active\");\n\treturn -1;\n\n default: /* unreached */\n\tPMD_DRV_LOG(ERR, \"stats update failed, unknown MAC type\");\n }\n\n ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,\n\t\t new->brb_discard - old->brb_discard);\n ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,\n\t\t new->brb_truncate - old->brb_truncate);\n\n if (!CHIP_IS_E3(sc)) {\n\tUPDATE_STAT64_NIG(egress_mac_pkt0,\n\t\t\t etherstatspkts1024octetsto1522octets);\n\tUPDATE_STAT64_NIG(egress_mac_pkt1,\n\t\t\t etherstatspktsover1522octets);\n }\n\n rte_memcpy(old, new, sizeof(struct nig_stats));\n\n rte_memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),\n\t sizeof(struct mac_stx));\n estats->brb_drop_hi = pstats->brb_drop_hi;\n estats->brb_drop_lo = pstats->brb_drop_lo;\n\n pstats->host_port_stats_counter++;\n\n if (CHIP_IS_E3(sc)) {\n\tlpi_reg = (SC_PORT(sc)) ?\n\t\t MISC_REG_CPMU_LP_SM_ENT_CNT_P1 :\n\t\t MISC_REG_CPMU_LP_SM_ENT_CNT_P0;\n\testats->eee_tx_lpi += REG_RD(sc, lpi_reg);\n }\n\n if (!BNX2X_NOMCP(sc)) {\n\tnig_timer_max = SHMEM_RD(sc, port_mb[SC_PORT(sc)].stat_nig_timer);\n\tif (nig_timer_max != estats->nig_timer_max) {\n\t estats->nig_timer_max = nig_timer_max;\n\t PMD_DRV_LOG(ERR, \"invalid NIG timer max (%u)\",\n\t\t estats->nig_timer_max);\n\t}\n }\n\n return 0;\n}\n\nstatic int\nbnx2x_storm_stats_validate_counters(struct bnx2x_softc *sc)\n{\n struct stats_counter *counters = &sc->fw_stats_data->storm_counters;\n uint16_t cur_stats_counter;\n\n /*\n * Make sure we use the value of the counter\n * used for sending the last stats ramrod.\n */\n cur_stats_counter = (sc->stats_counter - 1);\n\n /* are storm stats valid? */\n if (le16toh(counters->xstats_counter) != cur_stats_counter) {\n\tPMD_DRV_LOG(DEBUG,\n\t \"stats not updated by xstorm, \"\n\t \"counter 0x%x != stats_counter 0x%x\",\n\t le16toh(counters->xstats_counter), sc->stats_counter);\n\treturn -EAGAIN;\n }\n\n if (le16toh(counters->ustats_counter) != cur_stats_counter) {\n\tPMD_DRV_LOG(DEBUG,\n\t \"stats not updated by ustorm, \"\n\t \"counter 0x%x != stats_counter 0x%x\",\n\t le16toh(counters->ustats_counter), sc->stats_counter);\n\treturn -EAGAIN;\n }\n\n if (le16toh(counters->cstats_counter) != cur_stats_counter) {\n\tPMD_DRV_LOG(DEBUG,\n\t \"stats not updated by cstorm, \"\n\t \"counter 0x%x != stats_counter 0x%x\",\n\t le16toh(counters->cstats_counter), sc->stats_counter);\n\treturn -EAGAIN;\n }\n\n if (le16toh(counters->tstats_counter) != cur_stats_counter) {\n\tPMD_DRV_LOG(DEBUG,\n\t \"stats not updated by tstorm, \"\n\t \"counter 0x%x != stats_counter 0x%x\",\n\t le16toh(counters->tstats_counter), sc->stats_counter);\n\treturn -EAGAIN;\n }\n\n return 0;\n}\n\nstatic int\nbnx2x_storm_stats_update(struct bnx2x_softc *sc)\n{\n\tstruct tstorm_per_port_stats *tport =\n\t\t&sc->fw_stats_data->port.tstorm_port_statistics;\n\tstruct tstorm_per_pf_stats *tfunc =\n\t\t&sc->fw_stats_data->pf.tstorm_pf_statistics;\n\tstruct host_func_stats *fstats = &sc->func_stats;\n\tstruct bnx2x_eth_stats *estats = &sc->eth_stats;\n\tstruct bnx2x_eth_stats_old *estats_old = &sc->eth_stats_old;\n\tint i;\n\n\t/* vfs stat counter is managed by pf */\n\tif (IS_PF(sc) && bnx2x_storm_stats_validate_counters(sc)) {\n\t\treturn -EAGAIN;\n\t}\n\n\testats->error_bytes_received_hi = 0;\n\testats->error_bytes_received_lo = 0;\n\n\tfor (i = 0; i < sc->num_queues; i++) {\n\t\tstruct bnx2x_fastpath *fp = &sc->fp[i];\n\t\tstruct tstorm_per_queue_stats *tclient =\n\t\t\t&sc->fw_stats_data->queue_stats[i].tstorm_queue_statistics;\n\t\tstruct tstorm_per_queue_stats *old_tclient = &fp->old_tclient;\n\t\tstruct ustorm_per_queue_stats *uclient =\n\t\t\t&sc->fw_stats_data->queue_stats[i].ustorm_queue_statistics;\n\t\tstruct ustorm_per_queue_stats *old_uclient = &fp->old_uclient;\n\t\tstruct xstorm_per_queue_stats *xclient =\n\t\t\t&sc->fw_stats_data->queue_stats[i].xstorm_queue_statistics;\n\t\tstruct xstorm_per_queue_stats *old_xclient = &fp->old_xclient;\n\t\tstruct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;\n\t\tstruct bnx2x_eth_q_stats_old *qstats_old = &fp->eth_q_stats_old;\n\n\t\tuint32_t diff;\n\n\t\t/* PMD_DRV_LOG(DEBUG,\n\t\t\t\t\"queue[%d]: ucast_sent 0x%x bcast_sent 0x%x mcast_sent 0x%x\",\n\t\t\t\ti, xclient->ucast_pkts_sent, xclient->bcast_pkts_sent,\n\t\t\t\txclient->mcast_pkts_sent);\n\n\t\tPMD_DRV_LOG(DEBUG, \"---------------\"); */\n\n\t\tUPDATE_QSTAT(tclient->rcv_bcast_bytes,\n\t\t\t\ttotal_broadcast_bytes_received);\n\t\tUPDATE_QSTAT(tclient->rcv_mcast_bytes,\n\t\t\t\ttotal_multicast_bytes_received);\n\t\tUPDATE_QSTAT(tclient->rcv_ucast_bytes,\n\t\t\t\ttotal_unicast_bytes_received);\n\n\t\t/*\n\t\t * sum to total_bytes_received all\n\t\t * unicast/multicast/broadcast\n\t\t */\n\t\tqstats->total_bytes_received_hi =\n\t\t\tqstats->total_broadcast_bytes_received_hi;\n\t\tqstats->total_bytes_received_lo =\n\t\t\tqstats->total_broadcast_bytes_received_lo;\n\n\t\tADD_64(qstats->total_bytes_received_hi,\n\t\t\t\tqstats->total_multicast_bytes_received_hi,\n\t\t\t\tqstats->total_bytes_received_lo,\n\t\t\t\tqstats->total_multicast_bytes_received_lo);\n\n\t\tADD_64(qstats->total_bytes_received_hi,\n\t\t\t\tqstats->total_unicast_bytes_received_hi,\n\t\t\t\tqstats->total_bytes_received_lo,\n\t\t\t\tqstats->total_unicast_bytes_received_lo);\n\n\t\tqstats->valid_bytes_received_hi = qstats->total_bytes_received_hi;\n\t\tqstats->valid_bytes_received_lo = qstats->total_bytes_received_lo;\n\n\t\tUPDATE_EXTEND_TSTAT(rcv_ucast_pkts, total_unicast_packets_received);\n\t\tUPDATE_EXTEND_TSTAT(rcv_mcast_pkts, total_multicast_packets_received);\n\t\tUPDATE_EXTEND_TSTAT(rcv_bcast_pkts, total_broadcast_packets_received);\n\t\tUPDATE_EXTEND_E_TSTAT(pkts_too_big_discard,\n\t\t\t\tetherstatsoverrsizepkts, 32);\n\t\tUPDATE_EXTEND_E_TSTAT(no_buff_discard, no_buff_discard, 16);\n\n\t\tSUB_EXTEND_USTAT(ucast_no_buff_pkts, total_unicast_packets_received);\n\t\tSUB_EXTEND_USTAT(mcast_no_buff_pkts,\n\t\t\t\ttotal_multicast_packets_received);\n\t\tSUB_EXTEND_USTAT(bcast_no_buff_pkts,\n\t\t\t\ttotal_broadcast_packets_received);\n\t\tUPDATE_EXTEND_E_USTAT(ucast_no_buff_pkts, no_buff_discard);\n\t\tUPDATE_EXTEND_E_USTAT(mcast_no_buff_pkts, no_buff_discard);\n\t\tUPDATE_EXTEND_E_USTAT(bcast_no_buff_pkts, no_buff_discard);\n\n\t\tUPDATE_QSTAT(xclient->bcast_bytes_sent,\n\t\t\t\ttotal_broadcast_bytes_transmitted);\n\t\tUPDATE_QSTAT(xclient->mcast_bytes_sent,\n\t\t\t\ttotal_multicast_bytes_transmitted);\n\t\tUPDATE_QSTAT(xclient->ucast_bytes_sent,\n\t\t\t\ttotal_unicast_bytes_transmitted);\n\n\t\t/*\n\t\t * sum to total_bytes_transmitted all\n\t\t * unicast/multicast/broadcast\n\t\t */\n\t\tqstats->total_bytes_transmitted_hi =\n\t\t\tqstats->total_unicast_bytes_transmitted_hi;\n\t\tqstats->total_bytes_transmitted_lo =\n\t\t\tqstats->total_unicast_bytes_transmitted_lo;\n\n\t\tADD_64(qstats->total_bytes_transmitted_hi,\n\t\t\t\tqstats->total_broadcast_bytes_transmitted_hi,\n\t\t\t\tqstats->total_bytes_transmitted_lo,\n\t\t\t\tqstats->total_broadcast_bytes_transmitted_lo);\n\n\t\tADD_64(qstats->total_bytes_transmitted_hi,\n\t\t\t\tqstats->total_multicast_bytes_transmitted_hi,\n\t\t\t\tqstats->total_bytes_transmitted_lo,\n\t\t\t\tqstats->total_multicast_bytes_transmitted_lo);\n\n\t\tUPDATE_EXTEND_XSTAT(ucast_pkts_sent,\n\t\t\t\ttotal_unicast_packets_transmitted);\n\t\tUPDATE_EXTEND_XSTAT(mcast_pkts_sent,\n\t\t\t\ttotal_multicast_packets_transmitted);\n\t\tUPDATE_EXTEND_XSTAT(bcast_pkts_sent,\n\t\t\t\ttotal_broadcast_packets_transmitted);\n\n\t\tUPDATE_EXTEND_TSTAT(checksum_discard,\n\t\t\t\ttotal_packets_received_checksum_discarded);\n\t\tUPDATE_EXTEND_TSTAT(ttl0_discard,\n\t\t\t\ttotal_packets_received_ttl0_discarded);\n\n\t\tUPDATE_EXTEND_XSTAT(error_drop_pkts,\n\t\t\t\ttotal_transmitted_dropped_packets_error);\n\n\t\tUPDATE_FSTAT_QSTAT(total_bytes_received);\n\t\tUPDATE_FSTAT_QSTAT(total_bytes_transmitted);\n\t\tUPDATE_FSTAT_QSTAT(total_unicast_packets_received);\n\t\tUPDATE_FSTAT_QSTAT(total_multicast_packets_received);\n\t\tUPDATE_FSTAT_QSTAT(total_broadcast_packets_received);\n\t\tUPDATE_FSTAT_QSTAT(total_unicast_packets_transmitted);\n\t\tUPDATE_FSTAT_QSTAT(total_multicast_packets_transmitted);\n\t\tUPDATE_FSTAT_QSTAT(total_broadcast_packets_transmitted);\n\t\tUPDATE_FSTAT_QSTAT(valid_bytes_received);\n\t}\n\n\tADD_64(estats->total_bytes_received_hi,\n\t\t\testats->rx_stat_ifhcinbadoctets_hi,\n\t\t\testats->total_bytes_received_lo,\n\t\t\testats->rx_stat_ifhcinbadoctets_lo);\n\n\tADD_64_LE(estats->total_bytes_received_hi,\n\t\t\ttfunc->rcv_error_bytes.hi,\n\t\t\testats->total_bytes_received_lo,\n\t\t\ttfunc->rcv_error_bytes.lo);\n\n\tADD_64_LE(estats->error_bytes_received_hi,\n\t\t\ttfunc->rcv_error_bytes.hi,\n\t\t\testats->error_bytes_received_lo,\n\t\t\ttfunc->rcv_error_bytes.lo);\n\n\tUPDATE_ESTAT(etherstatsoverrsizepkts, rx_stat_dot3statsframestoolong);\n\n\tADD_64(estats->error_bytes_received_hi,\n\t\t\testats->rx_stat_ifhcinbadoctets_hi,\n\t\t\testats->error_bytes_received_lo,\n\t\t\testats->rx_stat_ifhcinbadoctets_lo);\n\n\tif (sc->port.pmf) {\n\t\tstruct bnx2x_fw_port_stats_old *fwstats = &sc->fw_stats_old;\n\t\tUPDATE_FW_STAT(mac_filter_discard);\n\t\tUPDATE_FW_STAT(mf_tag_discard);\n\t\tUPDATE_FW_STAT(brb_truncate_discard);\n\t\tUPDATE_FW_STAT(mac_discard);\n\t}\n\n\tfstats->host_func_stats_start = ++fstats->host_func_stats_end;\n\n\tsc->stats_pending = 0;\n\n\treturn 0;\n}\n\nstatic void\nbnx2x_drv_stats_update(struct bnx2x_softc *sc)\n{\n struct bnx2x_eth_stats *estats = &sc->eth_stats;\n int i;\n\n for (i = 0; i < sc->num_queues; i++) {\n\tstruct bnx2x_eth_q_stats *qstats = &sc->fp[i].eth_q_stats;\n\tstruct bnx2x_eth_q_stats_old *qstats_old = &sc->fp[i].eth_q_stats_old;\n\n\tUPDATE_ESTAT_QSTAT(rx_calls);\n\tUPDATE_ESTAT_QSTAT(rx_pkts);\n\tUPDATE_ESTAT_QSTAT(rx_soft_errors);\n\tUPDATE_ESTAT_QSTAT(rx_hw_csum_errors);\n\tUPDATE_ESTAT_QSTAT(rx_ofld_frames_csum_ip);\n\tUPDATE_ESTAT_QSTAT(rx_ofld_frames_csum_tcp_udp);\n\tUPDATE_ESTAT_QSTAT(rx_budget_reached);\n\tUPDATE_ESTAT_QSTAT(tx_pkts);\n\tUPDATE_ESTAT_QSTAT(tx_soft_errors);\n\tUPDATE_ESTAT_QSTAT(tx_ofld_frames_csum_ip);\n\tUPDATE_ESTAT_QSTAT(tx_ofld_frames_csum_tcp);\n\tUPDATE_ESTAT_QSTAT(tx_ofld_frames_csum_udp);\n\tUPDATE_ESTAT_QSTAT(tx_encap_failures);\n\tUPDATE_ESTAT_QSTAT(tx_hw_queue_full);\n\tUPDATE_ESTAT_QSTAT(tx_hw_max_queue_depth);\n\tUPDATE_ESTAT_QSTAT(tx_dma_mapping_failure);\n\tUPDATE_ESTAT_QSTAT(tx_max_drbr_queue_depth);\n\tUPDATE_ESTAT_QSTAT(tx_window_violation_std);\n\tUPDATE_ESTAT_QSTAT(tx_chain_lost_mbuf);\n\tUPDATE_ESTAT_QSTAT(tx_frames_deferred);\n\tUPDATE_ESTAT_QSTAT(tx_queue_xoff);\n\n\t/* mbuf driver statistics */\n\tUPDATE_ESTAT_QSTAT(mbuf_defrag_attempts);\n\tUPDATE_ESTAT_QSTAT(mbuf_defrag_failures);\n\tUPDATE_ESTAT_QSTAT(mbuf_rx_bd_alloc_failed);\n\tUPDATE_ESTAT_QSTAT(mbuf_rx_bd_mapping_failed);\n\n\t/* track the number of allocated mbufs */\n\tUPDATE_ESTAT_QSTAT(mbuf_alloc_tx);\n\tUPDATE_ESTAT_QSTAT(mbuf_alloc_rx);\n }\n}\n\nstatic uint8_t\nbnx2x_edebug_stats_stopped(struct bnx2x_softc *sc)\n{\n uint32_t val;\n\n if (SHMEM2_HAS(sc, edebug_driver_if[1])) {\n\tval = SHMEM2_RD(sc, edebug_driver_if[1]);\n\n\tif (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT) {\n\t return TRUE;\n\t}\n }\n\n return FALSE;\n}\n\nstatic void\nbnx2x_stats_update(struct bnx2x_softc *sc)\n{\n\tuint32_t *stats_comp = BNX2X_SP(sc, stats_comp);\n\n\tif (bnx2x_edebug_stats_stopped(sc)) {\n\t\treturn;\n\t}\n\n\tif (IS_PF(sc)) {\n\n\t\tbnx2x_storm_stats_update(sc);\n\t\tbnx2x_hw_stats_post(sc);\n\t\tbnx2x_storm_stats_post(sc);\n\t\tDELAY_MS(5);\n\n\t\tif (*stats_comp != DMAE_COMP_VAL) {\n\t\t\treturn;\n\t\t}\n\n\t\tif (sc->port.pmf) {\n\t\t\tbnx2x_hw_stats_update(sc);\n\t\t}\n\n\t\tif (bnx2x_storm_stats_update(sc)) {\n\t\t\tif (sc->stats_pending++ == 3) {\n\t\t\t\trte_panic(\"storm stats not updated for 3 times\");\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\t} else {\n\t\t/*\n\t\t * VF doesn't collect HW statistics, and doesn't get completions,\n\t\t * performs only update.\n\t\t */\n\t\tbnx2x_storm_stats_update(sc);\n\t}\n\n\tbnx2x_drv_stats_update(sc);\n}\n\nstatic void\nbnx2x_port_stats_stop(struct bnx2x_softc *sc)\n{\n struct dmae_command *dmae;\n uint32_t opcode;\n int loader_idx = PMF_DMAE_C(sc);\n uint32_t *stats_comp = BNX2X_SP(sc, stats_comp);\n\n sc->executer_idx = 0;\n\n opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC, FALSE, 0);\n\n if (sc->port.port_stx) {\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\n\tif (sc->func_stx) {\n\t dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);\n\t} else {\n\t dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);\n\t}\n\n\tdmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, port_stats));\n\tdmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, port_stats));\n\tdmae->dst_addr_lo = sc->port.port_stx >> 2;\n\tdmae->dst_addr_hi = 0;\n\tdmae->len = bnx2x_get_port_stats_dma_len(sc);\n\tif (sc->func_stx) {\n\t dmae->comp_addr_lo = (dmae_reg_go_c[loader_idx] >> 2);\n\t dmae->comp_addr_hi = 0;\n\t dmae->comp_val = 1;\n\t} else {\n\t dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, stats_comp));\n\t dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, stats_comp));\n\t dmae->comp_val = DMAE_COMP_VAL;\n\n\t *stats_comp = 0;\n\t}\n }\n\n if (sc->func_stx) {\n\tdmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n\tdmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);\n\tdmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, func_stats));\n\tdmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, func_stats));\n\tdmae->dst_addr_lo = (sc->func_stx >> 2);\n\tdmae->dst_addr_hi = 0;\n\tdmae->len = (sizeof(struct host_func_stats) >> 2);\n\tdmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, stats_comp));\n\tdmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, stats_comp));\n\tdmae->comp_val = DMAE_COMP_VAL;\n\n\t*stats_comp = 0;\n }\n}\n\nstatic void\nbnx2x_stats_stop(struct bnx2x_softc *sc)\n{\n uint8_t update = FALSE;\n\n bnx2x_stats_comp(sc);\n\n if (sc->port.pmf) {\n\tupdate = bnx2x_hw_stats_update(sc) == 0;\n }\n\n update |= bnx2x_storm_stats_update(sc) == 0;\n\n if (update) {\n\n\tif (sc->port.pmf) {\n\t bnx2x_port_stats_stop(sc);\n\t}\n\n\tbnx2x_hw_stats_post(sc);\n\tbnx2x_stats_comp(sc);\n }\n}\n\nstatic void\nbnx2x_stats_do_nothing(__rte_unused struct bnx2x_softc *sc)\n{\n return;\n}\n\nstatic const struct {\n void (*action)(struct bnx2x_softc *sc);\n enum bnx2x_stats_state next_state;\n} bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {\n {\n /* DISABLED PMF */ { bnx2x_stats_pmf_update, STATS_STATE_DISABLED },\n /* LINK_UP */ { bnx2x_stats_start, STATS_STATE_ENABLED },\n /* UPDATE */ { bnx2x_stats_do_nothing, STATS_STATE_DISABLED },\n /* STOP */ { bnx2x_stats_do_nothing, STATS_STATE_DISABLED }\n },\n {\n /* ENABLED PMF */ { bnx2x_stats_pmf_start, STATS_STATE_ENABLED },\n /* LINK_UP */ { bnx2x_stats_restart, STATS_STATE_ENABLED },\n /* UPDATE */ { bnx2x_stats_update, STATS_STATE_ENABLED },\n /* STOP */ { bnx2x_stats_stop, STATS_STATE_DISABLED }\n }\n};\n\nvoid bnx2x_stats_handle(struct bnx2x_softc *sc, enum bnx2x_stats_event event)\n{\n\tenum bnx2x_stats_state state;\n\n\tif (unlikely(sc->panic)) {\n\t\treturn;\n\t}\n\n\tstate = sc->stats_state;\n\tsc->stats_state = bnx2x_stats_stm[state][event].next_state;\n\n\tbnx2x_stats_stm[state][event].action(sc);\n\n\tif (event != STATS_EVENT_UPDATE) {\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t\"state %d -> event %d -> state %d\",\n\t\t\t\tstate, event, sc->stats_state);\n\t}\n}\n\nstatic void\nbnx2x_port_stats_base_init(struct bnx2x_softc *sc)\n{\n struct dmae_command *dmae;\n uint32_t *stats_comp = BNX2X_SP(sc, stats_comp);\n\n /* sanity */\n if (!sc->port.pmf || !sc->port.port_stx) {\n\tPMD_DRV_LOG(ERR, \"BUG!\");\n\treturn;\n }\n\n sc->executer_idx = 0;\n\n dmae = BNX2X_SP(sc, dmae[sc->executer_idx++]);\n dmae->opcode = bnx2x_dmae_opcode(sc, DMAE_SRC_PCI, DMAE_DST_GRC,\n\t\t\t\t TRUE, DMAE_COMP_PCI);\n dmae->src_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, port_stats));\n dmae->src_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, port_stats));\n dmae->dst_addr_lo = (sc->port.port_stx >> 2);\n dmae->dst_addr_hi = 0;\n dmae->len = bnx2x_get_port_stats_dma_len(sc);\n dmae->comp_addr_lo = U64_LO(BNX2X_SP_MAPPING(sc, stats_comp));\n dmae->comp_addr_hi = U64_HI(BNX2X_SP_MAPPING(sc, stats_comp));\n dmae->comp_val = DMAE_COMP_VAL;\n\n *stats_comp = 0;\n bnx2x_hw_stats_post(sc);\n bnx2x_stats_comp(sc);\n}\n\n/*\n * This function will prepare the statistics ramrod data the way\n * we will only have to increment the statistics counter and\n * send the ramrod each time we have to.\n */\nstatic void\nbnx2x_prep_fw_stats_req(struct bnx2x_softc *sc)\n{\n int i;\n int first_queue_query_index;\n struct stats_query_header *stats_hdr = &sc->fw_stats_req->hdr;\n phys_addr_t cur_data_offset;\n struct stats_query_entry *cur_query_entry;\n\n stats_hdr->cmd_num = sc->fw_stats_num;\n stats_hdr->drv_stats_counter = 0;\n\n /*\n * The storm_counters struct contains the counters of completed\n * statistics requests per storm which are incremented by FW\n * each time it completes hadning a statistics ramrod. We will\n * check these counters in the timer handler and discard a\n * (statistics) ramrod completion.\n */\n cur_data_offset = (sc->fw_stats_data_mapping +\n\t\t offsetof(struct bnx2x_fw_stats_data, storm_counters));\n\n stats_hdr->stats_counters_addrs.hi = htole32(U64_HI(cur_data_offset));\n stats_hdr->stats_counters_addrs.lo = htole32(U64_LO(cur_data_offset));\n\n /*\n * Prepare the first stats ramrod (will be completed with\n * the counters equal to zero) - init counters to somethig different.\n */\n memset(&sc->fw_stats_data->storm_counters, 0xff,\n\t sizeof(struct stats_counter));\n\n /**** Port FW statistics data ****/\n cur_data_offset = (sc->fw_stats_data_mapping +\n\t\t offsetof(struct bnx2x_fw_stats_data, port));\n\n cur_query_entry = &sc->fw_stats_req->query[BNX2X_PORT_QUERY_IDX];\n\n cur_query_entry->kind = STATS_TYPE_PORT;\n /* For port query index is a DONT CARE */\n cur_query_entry->index = SC_PORT(sc);\n /* For port query funcID is a DONT CARE */\n cur_query_entry->funcID = htole16(SC_FUNC(sc));\n cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));\n cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));\n\n /**** PF FW statistics data ****/\n cur_data_offset = (sc->fw_stats_data_mapping +\n\t\t offsetof(struct bnx2x_fw_stats_data, pf));\n\n cur_query_entry = &sc->fw_stats_req->query[BNX2X_PF_QUERY_IDX];\n\n cur_query_entry->kind = STATS_TYPE_PF;\n /* For PF query index is a DONT CARE */\n cur_query_entry->index = SC_PORT(sc);\n cur_query_entry->funcID = htole16(SC_FUNC(sc));\n cur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));\n cur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));\n\n /**** Clients' queries ****/\n cur_data_offset = (sc->fw_stats_data_mapping +\n\t\t offsetof(struct bnx2x_fw_stats_data, queue_stats));\n\n /*\n * First queue query index depends whether FCoE offloaded request will\n * be included in the ramrod\n */\n\tfirst_queue_query_index = (BNX2X_FIRST_QUEUE_QUERY_IDX - 1);\n\n for (i = 0; i < sc->num_queues; i++) {\n\tcur_query_entry =\n\t &sc->fw_stats_req->query[first_queue_query_index + i];\n\n\tcur_query_entry->kind = STATS_TYPE_QUEUE;\n\tcur_query_entry->index = bnx2x_stats_id(&sc->fp[i]);\n\tcur_query_entry->funcID = htole16(SC_FUNC(sc));\n\tcur_query_entry->address.hi = htole32(U64_HI(cur_data_offset));\n\tcur_query_entry->address.lo = htole32(U64_LO(cur_data_offset));\n\n\tcur_data_offset += sizeof(struct per_queue_stats);\n }\n}\n\nvoid bnx2x_memset_stats(struct bnx2x_softc *sc)\n{\n\tint i;\n\n\t/* function stats */\n\tfor (i = 0; i < sc->num_queues; i++) {\n\t\tstruct bnx2x_fastpath *fp = &sc->fp[i];\n\n\t\tmemset(&fp->old_tclient, 0,\n\t\t\t\tsizeof(fp->old_tclient));\n\t\tmemset(&fp->old_uclient, 0,\n\t\t\t\tsizeof(fp->old_uclient));\n\t\tmemset(&fp->old_xclient, 0,\n\t\t\t\tsizeof(fp->old_xclient));\n\t\tif (sc->stats_init) {\n\t\t\tmemset(&fp->eth_q_stats, 0,\n\t\t\t\t\tsizeof(fp->eth_q_stats));\n\t\t\tmemset(&fp->eth_q_stats_old, 0,\n\t\t\t\t\tsizeof(fp->eth_q_stats_old));\n\t\t}\n\t}\n\n\tif (sc->stats_init) {\n\t\tmemset(&sc->net_stats_old, 0, sizeof(sc->net_stats_old));\n\t\tmemset(&sc->fw_stats_old, 0, sizeof(sc->fw_stats_old));\n\t\tmemset(&sc->eth_stats_old, 0, sizeof(sc->eth_stats_old));\n\t\tmemset(&sc->eth_stats, 0, sizeof(sc->eth_stats));\n\t\tmemset(&sc->func_stats, 0, sizeof(sc->func_stats));\n\t}\n\n\tsc->stats_state = STATS_STATE_DISABLED;\n\n\tif (sc->port.pmf && sc->port.port_stx)\n\t\tbnx2x_port_stats_base_init(sc);\n\n\t/* mark the end of statistics initializiation */\n\tsc->stats_init = false;\n}\n\nvoid\nbnx2x_stats_init(struct bnx2x_softc *sc)\n{\n\tint /*abs*/port = SC_PORT(sc);\n\tint mb_idx = SC_FW_MB_IDX(sc);\n\tint i;\n\n\tsc->stats_pending = 0;\n\tsc->executer_idx = 0;\n\tsc->stats_counter = 0;\n\n\tsc->stats_init = TRUE;\n\n\t/* port and func stats for management */\n\tif (!BNX2X_NOMCP(sc)) {\n\t\tsc->port.port_stx = SHMEM_RD(sc, port_mb[port].port_stx);\n\t\tsc->func_stx = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_param);\n\t} else {\n\t\tsc->port.port_stx = 0;\n\t\tsc->func_stx = 0;\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"port_stx 0x%x func_stx 0x%x\",\n\t\t\tsc->port.port_stx, sc->func_stx);\n\n\t/* pmf should retrieve port statistics from SP on a non-init*/\n\tif (!sc->stats_init && sc->port.pmf && sc->port.port_stx) {\n\t\tbnx2x_stats_handle(sc, STATS_EVENT_PMF);\n\t}\n\n\tport = SC_PORT(sc);\n\t/* port stats */\n\tmemset(&(sc->port.old_nig_stats), 0, sizeof(struct nig_stats));\n\tsc->port.old_nig_stats.brb_discard =\n\t\tREG_RD(sc, NIG_REG_STAT0_BRB_DISCARD + port*0x38);\n\tsc->port.old_nig_stats.brb_truncate =\n\t\tREG_RD(sc, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);\n\tif (!CHIP_IS_E3(sc)) {\n\t\tREG_RD_DMAE(sc, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,\n\t\t\t\t&(sc->port.old_nig_stats.egress_mac_pkt0_lo), 2);\n\t\tREG_RD_DMAE(sc, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,\n\t\t\t\t&(sc->port.old_nig_stats.egress_mac_pkt1_lo), 2);\n\t}\n\n\t/* function stats */\n\tfor (i = 0; i < sc->num_queues; i++) {\n\t\tmemset(&sc->fp[i].old_tclient, 0, sizeof(sc->fp[i].old_tclient));\n\t\tmemset(&sc->fp[i].old_uclient, 0, sizeof(sc->fp[i].old_uclient));\n\t\tmemset(&sc->fp[i].old_xclient, 0, sizeof(sc->fp[i].old_xclient));\n\t\tif (sc->stats_init) {\n\t\t\tmemset(&sc->fp[i].eth_q_stats, 0,\n\t\t\t\t\tsizeof(sc->fp[i].eth_q_stats));\n\t\t\tmemset(&sc->fp[i].eth_q_stats_old, 0,\n\t\t\t\t\tsizeof(sc->fp[i].eth_q_stats_old));\n\t\t}\n\t}\n\n\t/* prepare statistics ramrod data */\n\tbnx2x_prep_fw_stats_req(sc);\n\n\tif (sc->stats_init) {\n\t\tmemset(&sc->net_stats_old, 0, sizeof(sc->net_stats_old));\n\t\tmemset(&sc->fw_stats_old, 0, sizeof(sc->fw_stats_old));\n\t\tmemset(&sc->eth_stats_old, 0, sizeof(sc->eth_stats_old));\n\t\tmemset(&sc->eth_stats, 0, sizeof(sc->eth_stats));\n\t\tmemset(&sc->func_stats, 0, sizeof(sc->func_stats));\n\n\t\t/* Clean SP from previous statistics */\n\t\tif (sc->func_stx) {\n\t\t\tmemset(BNX2X_SP(sc, func_stats), 0, sizeof(struct host_func_stats));\n\t\t\tbnx2x_func_stats_init(sc);\n\t\t\tbnx2x_hw_stats_post(sc);\n\t\t\tbnx2x_stats_comp(sc);\n\t\t}\n\t}\n\n\tsc->stats_state = STATS_STATE_DISABLED;\n\n\tif (sc->port.pmf && sc->port.port_stx) {\n\t\tbnx2x_port_stats_base_init(sc);\n\t}\n\n\t/* mark the end of statistics initializiation */\n\tsc->stats_init = FALSE;\n}\n\nvoid\nbnx2x_save_statistics(struct bnx2x_softc *sc)\n{\n\tint i;\n\n\t/* save queue statistics */\n\tfor (i = 0; i < sc->num_queues; i++) {\n\t\tstruct bnx2x_fastpath *fp = &sc->fp[i];\n\t\tstruct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;\n\t\tstruct bnx2x_eth_q_stats_old *qstats_old = &fp->eth_q_stats_old;\n\n\t\tUPDATE_QSTAT_OLD(total_unicast_bytes_received_hi);\n\t\tUPDATE_QSTAT_OLD(total_unicast_bytes_received_lo);\n\t\tUPDATE_QSTAT_OLD(total_broadcast_bytes_received_hi);\n\t\tUPDATE_QSTAT_OLD(total_broadcast_bytes_received_lo);\n\t\tUPDATE_QSTAT_OLD(total_multicast_bytes_received_hi);\n\t\tUPDATE_QSTAT_OLD(total_multicast_bytes_received_lo);\n\t\tUPDATE_QSTAT_OLD(total_unicast_bytes_transmitted_hi);\n\t\tUPDATE_QSTAT_OLD(total_unicast_bytes_transmitted_lo);\n\t\tUPDATE_QSTAT_OLD(total_broadcast_bytes_transmitted_hi);\n\t\tUPDATE_QSTAT_OLD(total_broadcast_bytes_transmitted_lo);\n\t\tUPDATE_QSTAT_OLD(total_multicast_bytes_transmitted_hi);\n\t\tUPDATE_QSTAT_OLD(total_multicast_bytes_transmitted_lo);\n\t}\n\n\t/* store port firmware statistics */\n\tif (sc->port.pmf) {\n\t\tstruct bnx2x_eth_stats *estats = &sc->eth_stats;\n\t\tstruct bnx2x_fw_port_stats_old *fwstats = &sc->fw_stats_old;\n\t\tstruct host_port_stats *pstats = BNX2X_SP(sc, port_stats);\n\n\t\tfwstats->pfc_frames_rx_hi = pstats->pfc_frames_rx_hi;\n\t\tfwstats->pfc_frames_rx_lo = pstats->pfc_frames_rx_lo;\n\t\tfwstats->pfc_frames_tx_hi = pstats->pfc_frames_tx_hi;\n\t\tfwstats->pfc_frames_tx_lo = pstats->pfc_frames_tx_lo;\n\n\t\tif (IS_MF(sc)) {\n\t\t\tUPDATE_FW_STAT_OLD(mac_filter_discard);\n\t\t\tUPDATE_FW_STAT_OLD(mf_tag_discard);\n\t\t\tUPDATE_FW_STAT_OLD(brb_truncate_discard);\n\t\t\tUPDATE_FW_STAT_OLD(mac_discard);\n\t\t}\n\t}\n}\n" }, { "path": "drivers/net/bnx2x/bnx2x_stats.h", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef BNX2X_STATS_H\n#define BNX2X_STATS_H\n\n#include \n\nstruct nig_stats {\n uint32_t brb_discard;\n uint32_t brb_packet;\n uint32_t brb_truncate;\n uint32_t flow_ctrl_discard;\n uint32_t flow_ctrl_octets;\n uint32_t flow_ctrl_packet;\n uint32_t mng_discard;\n uint32_t mng_octet_inp;\n uint32_t mng_octet_out;\n uint32_t mng_packet_inp;\n uint32_t mng_packet_out;\n uint32_t pbf_octets;\n uint32_t pbf_packet;\n uint32_t safc_inp;\n uint32_t egress_mac_pkt0_lo;\n uint32_t egress_mac_pkt0_hi;\n uint32_t egress_mac_pkt1_lo;\n uint32_t egress_mac_pkt1_hi;\n};\n\n\nenum bnx2x_stats_event {\n STATS_EVENT_PMF = 0,\n STATS_EVENT_LINK_UP,\n STATS_EVENT_UPDATE,\n STATS_EVENT_STOP,\n STATS_EVENT_MAX\n};\n\nenum bnx2x_stats_state {\n STATS_STATE_DISABLED = 0,\n STATS_STATE_ENABLED,\n STATS_STATE_MAX\n};\n\nstruct bnx2x_eth_stats {\n uint32_t total_bytes_received_hi;\n uint32_t total_bytes_received_lo;\n uint32_t total_bytes_transmitted_hi;\n uint32_t total_bytes_transmitted_lo;\n uint32_t total_unicast_packets_received_hi;\n uint32_t total_unicast_packets_received_lo;\n uint32_t total_multicast_packets_received_hi;\n uint32_t total_multicast_packets_received_lo;\n uint32_t total_broadcast_packets_received_hi;\n uint32_t total_broadcast_packets_received_lo;\n uint32_t total_unicast_packets_transmitted_hi;\n uint32_t total_unicast_packets_transmitted_lo;\n uint32_t total_multicast_packets_transmitted_hi;\n uint32_t total_multicast_packets_transmitted_lo;\n uint32_t total_broadcast_packets_transmitted_hi;\n uint32_t total_broadcast_packets_transmitted_lo;\n uint32_t valid_bytes_received_hi;\n uint32_t valid_bytes_received_lo;\n\n uint32_t error_bytes_received_hi;\n uint32_t error_bytes_received_lo;\n uint32_t etherstatsoverrsizepkts_hi;\n uint32_t etherstatsoverrsizepkts_lo;\n uint32_t no_buff_discard_hi;\n uint32_t no_buff_discard_lo;\n\n uint32_t rx_stat_ifhcinbadoctets_hi;\n uint32_t rx_stat_ifhcinbadoctets_lo;\n uint32_t tx_stat_ifhcoutbadoctets_hi;\n uint32_t tx_stat_ifhcoutbadoctets_lo;\n uint32_t rx_stat_dot3statsfcserrors_hi;\n uint32_t rx_stat_dot3statsfcserrors_lo;\n uint32_t rx_stat_dot3statsalignmenterrors_hi;\n uint32_t rx_stat_dot3statsalignmenterrors_lo;\n uint32_t rx_stat_dot3statscarriersenseerrors_hi;\n uint32_t rx_stat_dot3statscarriersenseerrors_lo;\n uint32_t rx_stat_falsecarriererrors_hi;\n uint32_t rx_stat_falsecarriererrors_lo;\n uint32_t rx_stat_etherstatsundersizepkts_hi;\n uint32_t rx_stat_etherstatsundersizepkts_lo;\n uint32_t rx_stat_dot3statsframestoolong_hi;\n uint32_t rx_stat_dot3statsframestoolong_lo;\n uint32_t rx_stat_etherstatsfragments_hi;\n uint32_t rx_stat_etherstatsfragments_lo;\n uint32_t rx_stat_etherstatsjabbers_hi;\n uint32_t rx_stat_etherstatsjabbers_lo;\n uint32_t rx_stat_maccontrolframesreceived_hi;\n uint32_t rx_stat_maccontrolframesreceived_lo;\n uint32_t rx_stat_bmac_xpf_hi;\n uint32_t rx_stat_bmac_xpf_lo;\n uint32_t rx_stat_bmac_xcf_hi;\n uint32_t rx_stat_bmac_xcf_lo;\n uint32_t rx_stat_xoffstateentered_hi;\n uint32_t rx_stat_xoffstateentered_lo;\n uint32_t rx_stat_xonpauseframesreceived_hi;\n uint32_t rx_stat_xonpauseframesreceived_lo;\n uint32_t rx_stat_xoffpauseframesreceived_hi;\n uint32_t rx_stat_xoffpauseframesreceived_lo;\n uint32_t tx_stat_outxonsent_hi;\n uint32_t tx_stat_outxonsent_lo;\n uint32_t tx_stat_outxoffsent_hi;\n uint32_t tx_stat_outxoffsent_lo;\n uint32_t tx_stat_flowcontroldone_hi;\n uint32_t tx_stat_flowcontroldone_lo;\n uint32_t tx_stat_etherstatscollisions_hi;\n uint32_t tx_stat_etherstatscollisions_lo;\n uint32_t tx_stat_dot3statssinglecollisionframes_hi;\n uint32_t tx_stat_dot3statssinglecollisionframes_lo;\n uint32_t tx_stat_dot3statsmultiplecollisionframes_hi;\n uint32_t tx_stat_dot3statsmultiplecollisionframes_lo;\n uint32_t tx_stat_dot3statsdeferredtransmissions_hi;\n uint32_t tx_stat_dot3statsdeferredtransmissions_lo;\n uint32_t tx_stat_dot3statsexcessivecollisions_hi;\n uint32_t tx_stat_dot3statsexcessivecollisions_lo;\n uint32_t tx_stat_dot3statslatecollisions_hi;\n uint32_t tx_stat_dot3statslatecollisions_lo;\n uint32_t tx_stat_etherstatspkts64octets_hi;\n uint32_t tx_stat_etherstatspkts64octets_lo;\n uint32_t tx_stat_etherstatspkts65octetsto127octets_hi;\n uint32_t tx_stat_etherstatspkts65octetsto127octets_lo;\n uint32_t tx_stat_etherstatspkts128octetsto255octets_hi;\n uint32_t tx_stat_etherstatspkts128octetsto255octets_lo;\n uint32_t tx_stat_etherstatspkts256octetsto511octets_hi;\n uint32_t tx_stat_etherstatspkts256octetsto511octets_lo;\n uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi;\n uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo;\n uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi;\n uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo;\n uint32_t tx_stat_etherstatspktsover1522octets_hi;\n uint32_t tx_stat_etherstatspktsover1522octets_lo;\n uint32_t tx_stat_bmac_2047_hi;\n uint32_t tx_stat_bmac_2047_lo;\n uint32_t tx_stat_bmac_4095_hi;\n uint32_t tx_stat_bmac_4095_lo;\n uint32_t tx_stat_bmac_9216_hi;\n uint32_t tx_stat_bmac_9216_lo;\n uint32_t tx_stat_bmac_16383_hi;\n uint32_t tx_stat_bmac_16383_lo;\n uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi;\n uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo;\n uint32_t tx_stat_bmac_ufl_hi;\n uint32_t tx_stat_bmac_ufl_lo;\n\n uint32_t pause_frames_received_hi;\n uint32_t pause_frames_received_lo;\n uint32_t pause_frames_sent_hi;\n uint32_t pause_frames_sent_lo;\n\n uint32_t etherstatspkts1024octetsto1522octets_hi;\n uint32_t etherstatspkts1024octetsto1522octets_lo;\n uint32_t etherstatspktsover1522octets_hi;\n uint32_t etherstatspktsover1522octets_lo;\n\n uint32_t brb_drop_hi;\n uint32_t brb_drop_lo;\n uint32_t brb_truncate_hi;\n uint32_t brb_truncate_lo;\n\n uint32_t mac_filter_discard;\n uint32_t mf_tag_discard;\n uint32_t brb_truncate_discard;\n uint32_t mac_discard;\n\n uint32_t nig_timer_max;\n\n /* PFC */\n uint32_t pfc_frames_received_hi;\n uint32_t pfc_frames_received_lo;\n uint32_t pfc_frames_sent_hi;\n uint32_t pfc_frames_sent_lo;\n\n /* Recovery */\n uint32_t recoverable_error;\n uint32_t unrecoverable_error;\n\n /* src: Clear-on-Read register; Will not survive PMF Migration */\n uint32_t eee_tx_lpi;\n\n /* receive path driver statistics */\n uint32_t rx_calls;\n uint32_t rx_pkts;\n uint32_t rx_soft_errors;\n uint32_t rx_hw_csum_errors;\n uint32_t rx_ofld_frames_csum_ip;\n uint32_t rx_ofld_frames_csum_tcp_udp;\n uint32_t rx_budget_reached;\n\n /* tx path driver statistics */\n uint32_t tx_pkts;\n uint32_t tx_soft_errors;\n uint32_t tx_ofld_frames_csum_ip;\n uint32_t tx_ofld_frames_csum_tcp;\n uint32_t tx_ofld_frames_csum_udp;\n uint32_t tx_encap_failures;\n uint32_t tx_hw_queue_full;\n uint32_t tx_hw_max_queue_depth;\n uint32_t tx_dma_mapping_failure;\n uint32_t tx_max_drbr_queue_depth;\n uint32_t tx_window_violation_std;\n uint32_t tx_chain_lost_mbuf;\n uint32_t tx_frames_deferred;\n uint32_t tx_queue_xoff;\n\n /* mbuf driver statistics */\n uint32_t mbuf_defrag_attempts;\n uint32_t mbuf_defrag_failures;\n uint32_t mbuf_rx_bd_alloc_failed;\n uint32_t mbuf_rx_bd_mapping_failed;\n\n /* track the number of allocated mbufs */\n uint32_t mbuf_alloc_tx;\n uint32_t mbuf_alloc_rx;\n};\n\n\nstruct bnx2x_eth_q_stats {\n uint32_t total_unicast_bytes_received_hi;\n uint32_t total_unicast_bytes_received_lo;\n uint32_t total_broadcast_bytes_received_hi;\n uint32_t total_broadcast_bytes_received_lo;\n uint32_t total_multicast_bytes_received_hi;\n uint32_t total_multicast_bytes_received_lo;\n uint32_t total_bytes_received_hi;\n uint32_t total_bytes_received_lo;\n uint32_t total_unicast_bytes_transmitted_hi;\n uint32_t total_unicast_bytes_transmitted_lo;\n uint32_t total_broadcast_bytes_transmitted_hi;\n uint32_t total_broadcast_bytes_transmitted_lo;\n uint32_t total_multicast_bytes_transmitted_hi;\n uint32_t total_multicast_bytes_transmitted_lo;\n uint32_t total_bytes_transmitted_hi;\n uint32_t total_bytes_transmitted_lo;\n uint32_t total_unicast_packets_received_hi;\n uint32_t total_unicast_packets_received_lo;\n uint32_t total_multicast_packets_received_hi;\n uint32_t total_multicast_packets_received_lo;\n uint32_t total_broadcast_packets_received_hi;\n uint32_t total_broadcast_packets_received_lo;\n uint32_t total_unicast_packets_transmitted_hi;\n uint32_t total_unicast_packets_transmitted_lo;\n uint32_t total_multicast_packets_transmitted_hi;\n uint32_t total_multicast_packets_transmitted_lo;\n uint32_t total_broadcast_packets_transmitted_hi;\n uint32_t total_broadcast_packets_transmitted_lo;\n uint32_t valid_bytes_received_hi;\n uint32_t valid_bytes_received_lo;\n\n uint32_t etherstatsoverrsizepkts_hi;\n uint32_t etherstatsoverrsizepkts_lo;\n uint32_t no_buff_discard_hi;\n uint32_t no_buff_discard_lo;\n\n uint32_t total_packets_received_checksum_discarded_hi;\n uint32_t total_packets_received_checksum_discarded_lo;\n uint32_t total_packets_received_ttl0_discarded_hi;\n uint32_t total_packets_received_ttl0_discarded_lo;\n uint32_t total_transmitted_dropped_packets_error_hi;\n uint32_t total_transmitted_dropped_packets_error_lo;\n\n /* receive path driver statistics */\n uint32_t rx_calls;\n uint32_t rx_pkts;\n uint32_t rx_soft_errors;\n uint32_t rx_hw_csum_errors;\n uint32_t rx_ofld_frames_csum_ip;\n uint32_t rx_ofld_frames_csum_tcp_udp;\n uint32_t rx_budget_reached;\n\n /* tx path driver statistics */\n uint32_t tx_pkts;\n uint32_t tx_soft_errors;\n uint32_t tx_ofld_frames_csum_ip;\n uint32_t tx_ofld_frames_csum_tcp;\n uint32_t tx_ofld_frames_csum_udp;\n uint32_t tx_encap_failures;\n uint32_t tx_hw_queue_full;\n uint32_t tx_hw_max_queue_depth;\n uint32_t tx_dma_mapping_failure;\n uint32_t tx_max_drbr_queue_depth;\n uint32_t tx_window_violation_std;\n uint32_t tx_chain_lost_mbuf;\n uint32_t tx_frames_deferred;\n uint32_t tx_queue_xoff;\n\n /* mbuf driver statistics */\n uint32_t mbuf_defrag_attempts;\n uint32_t mbuf_defrag_failures;\n uint32_t mbuf_rx_bd_alloc_failed;\n uint32_t mbuf_rx_bd_mapping_failed;\n\n /* track the number of allocated mbufs */\n uint32_t mbuf_alloc_tx;\n uint32_t mbuf_alloc_rx;\n};\n\nstruct bnx2x_eth_stats_old {\n uint32_t rx_stat_dot3statsframestoolong_hi;\n uint32_t rx_stat_dot3statsframestoolong_lo;\n};\n\nstruct bnx2x_eth_q_stats_old {\n /* Fields to perserve over fw reset*/\n uint32_t total_unicast_bytes_received_hi;\n uint32_t total_unicast_bytes_received_lo;\n uint32_t total_broadcast_bytes_received_hi;\n uint32_t total_broadcast_bytes_received_lo;\n uint32_t total_multicast_bytes_received_hi;\n uint32_t total_multicast_bytes_received_lo;\n uint32_t total_unicast_bytes_transmitted_hi;\n uint32_t total_unicast_bytes_transmitted_lo;\n uint32_t total_broadcast_bytes_transmitted_hi;\n uint32_t total_broadcast_bytes_transmitted_lo;\n uint32_t total_multicast_bytes_transmitted_hi;\n uint32_t total_multicast_bytes_transmitted_lo;\n\n /* Fields to perserve last of */\n uint32_t total_bytes_received_hi;\n uint32_t total_bytes_received_lo;\n uint32_t total_bytes_transmitted_hi;\n uint32_t total_bytes_transmitted_lo;\n uint32_t total_unicast_packets_received_hi;\n uint32_t total_unicast_packets_received_lo;\n uint32_t total_multicast_packets_received_hi;\n uint32_t total_multicast_packets_received_lo;\n uint32_t total_broadcast_packets_received_hi;\n uint32_t total_broadcast_packets_received_lo;\n uint32_t total_unicast_packets_transmitted_hi;\n uint32_t total_unicast_packets_transmitted_lo;\n uint32_t total_multicast_packets_transmitted_hi;\n uint32_t total_multicast_packets_transmitted_lo;\n uint32_t total_broadcast_packets_transmitted_hi;\n uint32_t total_broadcast_packets_transmitted_lo;\n uint32_t valid_bytes_received_hi;\n uint32_t valid_bytes_received_lo;\n\n /* receive path driver statistics */\n uint32_t rx_calls_old;\n uint32_t rx_pkts_old;\n uint32_t rx_soft_errors_old;\n uint32_t rx_hw_csum_errors_old;\n uint32_t rx_ofld_frames_csum_ip_old;\n uint32_t rx_ofld_frames_csum_tcp_udp_old;\n uint32_t rx_budget_reached_old;\n\n /* tx path driver statistics */\n uint32_t tx_pkts_old;\n uint32_t tx_soft_errors_old;\n uint32_t tx_ofld_frames_csum_ip_old;\n uint32_t tx_ofld_frames_csum_tcp_old;\n uint32_t tx_ofld_frames_csum_udp_old;\n uint32_t tx_encap_failures_old;\n uint32_t tx_hw_queue_full_old;\n uint32_t tx_hw_max_queue_depth_old;\n uint32_t tx_dma_mapping_failure_old;\n uint32_t tx_max_drbr_queue_depth_old;\n uint32_t tx_window_violation_std_old;\n uint32_t tx_chain_lost_mbuf_old;\n uint32_t tx_frames_deferred_old;\n uint32_t tx_queue_xoff_old;\n\n /* mbuf driver statistics */\n uint32_t mbuf_defrag_attempts_old;\n uint32_t mbuf_defrag_failures_old;\n uint32_t mbuf_rx_bd_alloc_failed_old;\n uint32_t mbuf_rx_bd_mapping_failed_old;\n\n /* track the number of allocated mbufs */\n int mbuf_alloc_tx_old;\n int mbuf_alloc_rx_old;\n};\n\nstruct bnx2x_net_stats_old {\n uint32_t rx_dropped;\n};\n\nstruct bnx2x_fw_port_stats_old {\n uint32_t pfc_frames_tx_hi;\n uint32_t pfc_frames_tx_lo;\n uint32_t pfc_frames_rx_hi;\n uint32_t pfc_frames_rx_lo;\n\n uint32_t mac_filter_discard;\n uint32_t mf_tag_discard;\n uint32_t brb_truncate_discard;\n uint32_t mac_discard;\n};\n\n/* sum[hi:lo] += add[hi:lo] */\n#define ADD_64(s_hi, a_hi, s_lo, a_lo) \\\n do { \\\n\ts_lo += a_lo; \\\n\ts_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \\\n } while (0)\n\n#define LE32_0 ((uint32_t) 0)\n#define LE16_0 ((uint16_t) 0)\n\n/* The _force is for cases where high value is 0 */\n#define ADD_64_LE(s_hi, a_hi_le, s_lo, a_lo_le) \\\n\tADD_64(s_hi, le32toh(a_hi_le), \\\n\t s_lo, le32toh(a_lo_le))\n\n#define ADD_64_LE16(s_hi, a_hi_le, s_lo, a_lo_le) \\\n\tADD_64(s_hi, le16toh(a_hi_le), \\\n\t s_lo, le16toh(a_lo_le))\n\n/* difference = minuend - subtrahend */\n#define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \\\n do { \\\n\tif (m_lo < s_lo) { \\\n\t /* underflow */ \\\n\t d_hi = m_hi - s_hi; \\\n\t if (d_hi > 0) { \\\n\t\t/* we can 'loan' 1 */ \\\n\t\td_hi--; \\\n\t\td_lo = m_lo + (UINT_MAX - s_lo) + 1; \\\n\t } else { \\\n\t\t/* m_hi <= s_hi */ \\\n\t\td_hi = 0; \\\n\t\td_lo = 0; \\\n\t } \\\n\t} else { \\\n\t /* m_lo >= s_lo */ \\\n\t if (m_hi < s_hi) { \\\n\t\td_hi = 0; \\\n\t\td_lo = 0; \\\n\t } else { \\\n\t\t/* m_hi >= s_hi */ \\\n\t\td_hi = m_hi - s_hi; \\\n\t\td_lo = m_lo - s_lo; \\\n\t } \\\n\t} \\\n } while (0)\n\n#define UPDATE_STAT64(s, t) \\\n do { \\\n\tDIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \\\n\t diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \\\n\tpstats->mac_stx[0].t##_hi = new->s##_hi; \\\n\tpstats->mac_stx[0].t##_lo = new->s##_lo; \\\n\tADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \\\n\t pstats->mac_stx[1].t##_lo, diff.lo); \\\n } while (0)\n\n#define UPDATE_STAT64_NIG(s, t) \\\n do { \\\n\tDIFF_64(diff.hi, new->s##_hi, old->s##_hi, \\\n\t diff.lo, new->s##_lo, old->s##_lo); \\\n\tADD_64(estats->t##_hi, diff.hi, \\\n\t estats->t##_lo, diff.lo); \\\n } while (0)\n\n/* sum[hi:lo] += add */\n#define ADD_EXTEND_64(s_hi, s_lo, a) \\\n do { \\\n\ts_lo += a; \\\n\ts_hi += (s_lo < a) ? 1 : 0; \\\n } while (0)\n\n#define ADD_STAT64(diff, t) \\\n do { \\\n\tADD_64(pstats->mac_stx[1].t##_hi, new->diff##_hi, \\\n\t pstats->mac_stx[1].t##_lo, new->diff##_lo); \\\n } while (0)\n\n#define UPDATE_EXTEND_STAT(s) \\\n do { \\\n\tADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \\\n\t\t pstats->mac_stx[1].s##_lo, \\\n\t\t new->s); \\\n } while (0)\n\n#define UPDATE_EXTEND_TSTAT_X(s, t, size) \\\n do { \\\n\tdiff = le##size##toh(tclient->s) - \\\n\t le##size##toh(old_tclient->s); \\\n\told_tclient->s = tclient->s; \\\n\tADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \\\n } while (0)\n\n#define UPDATE_EXTEND_TSTAT(s, t) UPDATE_EXTEND_TSTAT_X(s, t, 32)\n\n#define UPDATE_EXTEND_E_TSTAT(s, t, size) \\\n do { \\\n\tUPDATE_EXTEND_TSTAT_X(s, t, size); \\\n\tADD_EXTEND_64(estats->t##_hi, estats->t##_lo, diff); \\\n } while (0)\n\n#define UPDATE_EXTEND_USTAT(s, t) \\\n do { \\\n\tdiff = le32toh(uclient->s) - le32toh(old_uclient->s); \\\n\told_uclient->s = uclient->s; \\\n\tADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \\\n } while (0)\n\n#define UPDATE_EXTEND_E_USTAT(s, t) \\\n do { \\\n\tUPDATE_EXTEND_USTAT(s, t); \\\n\tADD_EXTEND_64(estats->t##_hi, estats->t##_lo, diff); \\\n } while (0)\n\n#define UPDATE_EXTEND_XSTAT(s, t) \\\n do { \\\n\tdiff = le32toh(xclient->s) - le32toh(old_xclient->s); \\\n\told_xclient->s = xclient->s; \\\n\tADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \\\n } while (0)\n\n#define UPDATE_QSTAT(s, t) \\\n do { \\\n\tqstats->t##_hi = qstats_old->t##_hi + le32toh(s.hi); \\\n\tqstats->t##_lo = qstats_old->t##_lo + le32toh(s.lo); \\\n } while (0)\n\n#define UPDATE_QSTAT_OLD(f) \\\n do { \\\n\tqstats_old->f = qstats->f; \\\n } while (0)\n\n#define UPDATE_ESTAT_QSTAT_64(s) \\\n do { \\\n\tADD_64(estats->s##_hi, qstats->s##_hi, \\\n\t estats->s##_lo, qstats->s##_lo); \\\n\tSUB_64(estats->s##_hi, qstats_old->s##_hi_old, \\\n\t estats->s##_lo, qstats_old->s##_lo_old); \\\n\tqstats_old->s##_hi_old = qstats->s##_hi; \\\n\tqstats_old->s##_lo_old = qstats->s##_lo; \\\n } while (0)\n\n#define UPDATE_ESTAT_QSTAT(s) \\\n do { \\\n\testats->s += qstats->s; \\\n\testats->s -= qstats_old->s##_old; \\\n\tqstats_old->s##_old = qstats->s; \\\n } while (0)\n\n#define UPDATE_FSTAT_QSTAT(s) \\\n do { \\\n\tADD_64(fstats->s##_hi, qstats->s##_hi, \\\n\t fstats->s##_lo, qstats->s##_lo); \\\n\tSUB_64(fstats->s##_hi, qstats_old->s##_hi, \\\n\t fstats->s##_lo, qstats_old->s##_lo); \\\n\testats->s##_hi = fstats->s##_hi; \\\n\testats->s##_lo = fstats->s##_lo; \\\n\tqstats_old->s##_hi = qstats->s##_hi; \\\n\tqstats_old->s##_lo = qstats->s##_lo; \\\n } while (0)\n\n#define UPDATE_FW_STAT(s) \\\n do { \\\n\testats->s = le32toh(tport->s) + fwstats->s; \\\n } while (0)\n\n#define UPDATE_FW_STAT_OLD(f) \\\n do { \\\n\tfwstats->f = estats->f; \\\n } while (0)\n\n#define UPDATE_ESTAT(s, t) \\\n do { \\\n\tSUB_64(estats->s##_hi, estats_old->t##_hi, \\\n\t estats->s##_lo, estats_old->t##_lo); \\\n\tADD_64(estats->s##_hi, estats->t##_hi, \\\n\t estats->s##_lo, estats->t##_lo); \\\n\testats_old->t##_hi = estats->t##_hi; \\\n\testats_old->t##_lo = estats->t##_lo; \\\n } while (0)\n\n/* minuend -= subtrahend */\n#define SUB_64(m_hi, s_hi, m_lo, s_lo) \\\n do { \\\n\tDIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \\\n } while (0)\n\n/* minuend[hi:lo] -= subtrahend */\n#define SUB_EXTEND_64(m_hi, m_lo, s) \\\n do { \\\n\tuint32_t s_hi = 0; \\\n\tSUB_64(m_hi, s_hi, m_lo, s); \\\n } while (0)\n\n#define SUB_EXTEND_USTAT(s, t) \\\n do { \\\n\tdiff = le32toh(uclient->s) - le32toh(old_uclient->s); \\\n\tSUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \\\n } while (0)\n\nstruct bnx2x_softc;\nvoid bnx2x_stats_init(struct bnx2x_softc *sc);\nvoid bnx2x_stats_handle(struct bnx2x_softc *sc, enum bnx2x_stats_event event);\nvoid bnx2x_save_statistics(struct bnx2x_softc *sc);\nvoid bnx2x_memset_stats(struct bnx2x_softc *sc);\n\n#endif /* BNX2X_STATS_H */\n" }, { "path": "drivers/net/bnx2x/bnx2x_vfpf.c", "content": "/*\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n *\n * All rights reserved.\n */\n\n#include \"bnx2x.h\"\n\n/* calculate the crc in the bulletin board */\nstatic inline uint32_t\nbnx2x_vf_crc(struct bnx2x_vf_bulletin *bull)\n{\n\tuint32_t crc_sz = sizeof(bull->crc), length = bull->length - crc_sz;\n\n\treturn ECORE_CRC32_LE(0, (uint8_t *)bull + crc_sz, length);\n}\n\n/* Checks are there mac/channel updates for VF\n * returns TRUE if something was updated\n*/\nint\nbnx2x_check_bull(struct bnx2x_softc *sc)\n{\n\tstruct bnx2x_vf_bulletin *bull;\n\tuint8_t tries = 0;\n\tuint16_t old_version = sc->old_bulletin.version;\n\tuint64_t valid_bitmap;\n\n\tbull = sc->pf2vf_bulletin;\n\tif (old_version == bull->version) {\n\t\treturn FALSE;\n\t} else {\n\t\t/* Check the crc until we get the correct data */\n\t\twhile (tries < BNX2X_VF_BULLETIN_TRIES) {\n\t\t\tbull = sc->pf2vf_bulletin;\n\t\t\tif (bull->crc == bnx2x_vf_crc(bull))\n\t\t\t\tbreak;\n\n\t\t\tPMD_DRV_LOG(ERR, \"bad crc on bulletin board. contained %x computed %x\",\n\t\t\t\t\tbull->crc, bnx2x_vf_crc(bull));\n\t\t\t++tries;\n\t\t}\n\t\tif (tries == BNX2X_VF_BULLETIN_TRIES) {\n\t\t\tPMD_DRV_LOG(ERR, \"pf to vf bulletin board crc was wrong %d consecutive times. Aborting\",\n\t\t\t\t\ttries);\n\t\t\treturn FALSE;\n\t\t}\n\t}\n\n\tvalid_bitmap = bull->valid_bitmap;\n\n\t/* check the mac address and VLAN and allocate memory if valid */\n\tif (valid_bitmap & (1 << MAC_ADDR_VALID) && memcmp(bull->mac, sc->old_bulletin.mac, ETH_ALEN))\n\t\trte_memcpy(&sc->link_params.mac_addr, bull->mac, ETH_ALEN);\n\tif (valid_bitmap & (1 << VLAN_VALID))\n\t\trte_memcpy(&bull->vlan, &sc->old_bulletin.vlan, VLAN_HLEN);\n\n\tsc->old_bulletin = *bull;\n\n\treturn TRUE;\n}\n\n/* add tlv to a buffer */\n#define BNX2X_TLV_APPEND(_tlvs, _offset, _type, _length) \\\n\t((struct vf_first_tlv *)((uint64_t)_tlvs + _offset))->type = _type; \\\n\t((struct vf_first_tlv *)((uint64_t)_tlvs + _offset))->length = _length\n\n/* Initiliaze header of the first tlv and clear mailbox*/\nstatic void\nbnx2x_init_first_tlv(struct bnx2x_softc *sc, struct vf_first_tlv *tlv,\n\tuint16_t type, uint16_t len)\n{\n\tstruct bnx2x_vf_mbx_msg *mbox = sc->vf2pf_mbox;\n\tPMD_DRV_LOG(DEBUG, \"Preparing %d tlv for sending\", type);\n\n\tmemset(mbox, 0, sizeof(struct bnx2x_vf_mbx_msg));\n\n\tBNX2X_TLV_APPEND(tlv, 0, type, len);\n\n\t/* Initialize header of the first tlv */\n\ttlv->reply_offset = sizeof(mbox->query);\n}\n\n#define BNX2X_VF_CMD_ADDR_LO PXP_VF_ADDR_CSDM_GLOBAL_START\n#define BNX2X_VF_CMD_ADDR_HI BNX2X_VF_CMD_ADDR_LO + 4\n#define BNX2X_VF_CMD_TRIGGER BNX2X_VF_CMD_ADDR_HI + 4\n#define BNX2X_VF_CHANNEL_DELAY 100\n#define BNX2X_VF_CHANNEL_TRIES 100\n\nstatic int\nbnx2x_do_req4pf(struct bnx2x_softc *sc, phys_addr_t phys_addr)\n{\n\tuint8_t *status = &sc->vf2pf_mbox->resp.common_reply.status;\n\tuint8_t i;\n\n\tif (!*status) {\n\t\tbnx2x_check_bull(sc);\n\t\tif (sc->old_bulletin.valid_bitmap & (1 << CHANNEL_DOWN)) {\n\t\t\tPMD_DRV_LOG(ERR, \"channel is down. Aborting message sending\");\n\t\t\t*status = BNX2X_VF_STATUS_SUCCESS;\n\t\t\treturn 0;\n\t\t}\n\n\t\tREG_WR(sc, BNX2X_VF_CMD_ADDR_LO, U64_LO(phys_addr));\n\t\tREG_WR(sc, BNX2X_VF_CMD_ADDR_HI, U64_HI(phys_addr));\n\n\t\t/* memory barrier to ensure that FW can read phys_addr */\n\t\twmb();\n\n\t\tREG_WR8(sc, BNX2X_VF_CMD_TRIGGER, 1);\n\n\t\t/* Do several attempts until PF completes\n\t\t * \".\" is used to show progress\n\t\t */\n\t\tfor (i = 0; i < BNX2X_VF_CHANNEL_TRIES; i++) {\n\t\t\tDELAY_MS(BNX2X_VF_CHANNEL_DELAY);\n\t\t\tif (*status)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tif (i == BNX2X_VF_CHANNEL_TRIES) {\n\t\t\tPMD_DRV_LOG(ERR, \"Response from PF timed out\");\n\t\t\treturn -EAGAIN;\n\t\t}\n\n\t\tif (BNX2X_VF_STATUS_SUCCESS != *status) {\n\t\t\tPMD_DRV_LOG(ERR, \"Bad reply from PF : %u\",\n\t\t\t\t\t*status);\n\t\t\treturn -EINVAL;\n\t\t}\n\t} else {\n\t\tPMD_DRV_LOG(ERR, \"status should be zero before message\"\n\t\t\t\t\"to pf was sent\");\n\t\treturn -EINVAL;\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"Response from PF was received\");\n\treturn 0;\n}\n\nstatic inline uint16_t bnx2x_check_me_flags(uint32_t val)\n{\n\tif (((val) & ME_REG_VF_VALID) && (!((val) & ME_REG_VF_ERR)))\n\t\treturn ME_REG_VF_VALID;\n\telse\n\t\treturn 0;\n}\n\n#define BNX2X_ME_ANSWER_DELAY 100\n#define BNX2X_ME_ANSWER_TRIES 10\n\nstatic inline int bnx2x_read_vf_id(struct bnx2x_softc *sc)\n{\n\tuint32_t val;\n\tuint8_t i = 0;\n\n\twhile (i <= BNX2X_ME_ANSWER_TRIES) {\n\t\tval = BNX2X_DB_READ(DOORBELL_ADDR(sc, 0));\n\t\tif (bnx2x_check_me_flags(val))\n\t\t\treturn VF_ID(val);\n\n\t\tDELAY_MS(BNX2X_ME_ANSWER_DELAY);\n\t\ti++;\n\t}\n\n\treturn -EINVAL;\n}\n\n#define BNX2X_VF_OBTAIN_MAX_TRIES 3\n#define BNX2X_VF_OBTAIN_MAC_FILTERS 1\n#define BNX2X_VF_OBTAIN_MC_FILTERS 10\n\nstruct bnx2x_obtain_status {\n\tint success;\n\tint err_code;\n};\n\nstatic\nstruct bnx2x_obtain_status bnx2x_loop_obtain_resources(struct bnx2x_softc *sc)\n{\n\tint tries = 0;\n\tstruct vf_acquire_resp_tlv *resp = &sc->vf2pf_mbox->resp.acquire_resp,\n\t\t\t\t\t\t\t\t *sc_resp = &sc->acquire_resp;\n\tstruct vf_resource_query *res_query;\n\tstruct vf_resc *resc;\n\tstruct bnx2x_obtain_status status;\n\tint res_obtained = false;\n\n\tdo {\n\t\tPMD_DRV_LOG(DEBUG, \"trying to get resources\");\n\n\t\tif ( bnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr) ) {\n\t\t\t/* timeout */\n\t\t\tstatus.success = 0;\n\t\t\tstatus.err_code = 0;\n\t\t\treturn status;\n\t\t}\n\n\t\tmemcpy(sc_resp, resp, sizeof(sc->acquire_resp));\n\n\t\ttries++;\n\n\t\t/* check PF to request acceptance */\n\t\tif (sc_resp->status == BNX2X_VF_STATUS_SUCCESS) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"resources obtained successfully\");\n\t\t\tres_obtained = true;\n\t\t} else if (sc_resp->status == BNX2X_VF_STATUS_NO_RESOURCES &&\n\t\t\ttries < BNX2X_VF_OBTAIN_MAX_TRIES) {\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t \"PF cannot allocate requested amount of resources\");\n\n\t\t\tres_query = &sc->vf2pf_mbox->query[0].acquire.res_query;\n\t\t\tresc = &sc_resp->resc;\n\n\t\t\t/* PF refused our request. Try to decrease request params */\n\t\t\tres_query->num_txqs = min(res_query->num_txqs, resc->num_txqs);\n\t\t\tres_query->num_rxqs = min(res_query->num_rxqs, resc->num_rxqs);\n\t\t\tres_query->num_sbs = min(res_query->num_sbs, resc->num_sbs);\n\t\t\tres_query->num_mac_filters = min(res_query->num_mac_filters, resc->num_mac_filters);\n\t\t\tres_query->num_vlan_filters = min(res_query->num_vlan_filters, resc->num_vlan_filters);\n\t\t\tres_query->num_mc_filters = min(res_query->num_mc_filters, resc->num_mc_filters);\n\n\t\t\tmemset(&sc->vf2pf_mbox->resp, 0, sizeof(union resp_tlvs));\n\t\t} else {\n\t\t\tPMD_DRV_LOG(ERR, \"Resources cannot be obtained. Status of handling: %d. Aborting\",\n\t\t\t\t\tsc_resp->status);\n\t\t\tstatus.success = 0;\n\t\t\tstatus.err_code = -EAGAIN;\n\t\t\treturn status;\n\t\t}\n\t} while (!res_obtained);\n\n\tstatus.success = 1;\n\treturn status;\n}\n\nint bnx2x_vf_get_resources(struct bnx2x_softc *sc, uint8_t tx_count, uint8_t rx_count)\n{\n\tstruct vf_acquire_tlv *acq = &sc->vf2pf_mbox->query[0].acquire;\n\tint vf_id;\n\tstruct bnx2x_obtain_status obtain_status;\n\n\tbnx2x_vf_close(sc);\n\tbnx2x_init_first_tlv(sc, &acq->first_tlv, BNX2X_VF_TLV_ACQUIRE, sizeof(*acq));\n\n\tvf_id = bnx2x_read_vf_id(sc);\n\tif (vf_id < 0)\n\t\treturn -EAGAIN;\n\n\tacq->vf_id = vf_id;\n\n\tacq->res_query.num_rxqs = rx_count;\n\tacq->res_query.num_txqs = tx_count;\n\tacq->res_query.num_sbs = sc->igu_sb_cnt;\n\tacq->res_query.num_mac_filters = BNX2X_VF_OBTAIN_MAC_FILTERS;\n\tacq->res_query.num_mc_filters = BNX2X_VF_OBTAIN_MC_FILTERS;\n\n\tacq->bulletin_addr = sc->pf2vf_bulletin_mapping.paddr;\n\n\tBNX2X_TLV_APPEND(acq, acq->first_tlv.length, BNX2X_VF_TLV_LIST_END,\n\t\t\tsizeof(struct channel_list_end_tlv));\n\n\t/* requesting the resources in loop */\n\tobtain_status = bnx2x_loop_obtain_resources(sc);\n\tif (!obtain_status.success)\n\t\treturn obtain_status.err_code;\n\n\tstruct vf_acquire_resp_tlv sc_resp = sc->acquire_resp;\n\n\tsc->devinfo.chip_id |= (sc_resp.chip_num & 0xFFFF);\n\tsc->devinfo.int_block = INT_BLOCK_IGU;\n\tsc->devinfo.chip_port_mode = CHIP_2_PORT_MODE;\n\tsc->devinfo.mf_info.mf_ov = 0;\n\tsc->devinfo.mf_info.mf_mode = 0;\n\tsc->devinfo.flash_size = 0;\n\n\tsc->igu_sb_cnt = sc_resp.resc.num_sbs;\n\tsc->igu_base_sb = sc_resp.resc.hw_sbs[0] & 0xFF;\n\tsc->igu_dsb_id = -1;\n\n\tsc->link_params.chip_id = sc->devinfo.chip_id;\n\tsc->doorbell_size = sc_resp.db_size;\n\tsc->flags |= BNX2X_NO_WOL_FLAG | BNX2X_NO_ISCSI_OOO_FLAG | BNX2X_NO_ISCSI_FLAG | BNX2X_NO_FCOE_FLAG;\n\n\tPMD_DRV_LOG(DEBUG, \"status block count = %d, base status block = %x\",\n\t\tsc->igu_sb_cnt, sc->igu_base_sb);\n\tstrncpy(sc->fw_ver, sc_resp.fw_ver, sizeof(sc->fw_ver));\n\n\tif (is_valid_ether_addr(sc_resp.resc.current_mac_addr))\n\t\t(void)rte_memcpy(sc->link_params.mac_addr,\n\t\t sc_resp.resc.current_mac_addr,\n\t\t ETH_ALEN);\n\n\treturn 0;\n}\n\n/* Ask PF to release VF's resources */\nvoid\nbnx2x_vf_close(struct bnx2x_softc *sc)\n{\n\tstruct vf_release_tlv *query;\n\tint vf_id = bnx2x_read_vf_id(sc);\n\tint ret;\n\n\tif (vf_id >= 0) {\n\t\tquery = &sc->vf2pf_mbox->query[0].release;\n\t\tbnx2x_init_first_tlv(sc, &query->first_tlv, BNX2X_VF_TLV_RELEASE,\n\t\t\t\tsizeof(*query));\n\n\t\tquery->vf_id = vf_id;\n\t\tBNX2X_TLV_APPEND(query, query->first_tlv.length, BNX2X_VF_TLV_LIST_END,\n\t\t\t\tsizeof(struct channel_list_end_tlv));\n\n\t\tret = bnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);\n\n\t\tif (ret) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to release VF\");\n\t\t}\n\t}\n}\n\n/* Let PF know the VF status blocks phys_addrs */\nint\nbnx2x_vf_init(struct bnx2x_softc *sc)\n{\n\tstruct vf_init_tlv *query;\n\tint i, ret;\n\n\tquery = &sc->vf2pf_mbox->query[0].init;\n\tbnx2x_init_first_tlv(sc, &query->first_tlv, BNX2X_VF_TLV_INIT,\n\t\t\tsizeof(*query));\n\n\tFOR_EACH_QUEUE(sc, i) {\n\t\tquery->sb_addr[i] = (unsigned long)(sc->fp[i].sb_dma.paddr);\n\t}\n\n\tquery->stats_step = sizeof(struct per_queue_stats);\n\tquery->stats_addr = sc->fw_stats_data_mapping +\n\t\toffsetof(struct bnx2x_fw_stats_data, queue_stats);\n\n\tBNX2X_TLV_APPEND(query, query->first_tlv.length, BNX2X_VF_TLV_LIST_END,\n\t\t\tsizeof(struct channel_list_end_tlv));\n\n\tret = bnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);\n\n\tif (ret) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to init VF\");\n\t\treturn ret;\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"VF was initialized\");\n\treturn 0;\n}\n\nvoid\nbnx2x_vf_unload(struct bnx2x_softc *sc)\n{\n\tstruct vf_close_tlv *query;\n\tstruct vf_q_op_tlv *query_op;\n\tint i, vf_id, ret;\n\n\tvf_id = bnx2x_read_vf_id(sc);\n\tif (vf_id > 0) {\n\t\tFOR_EACH_QUEUE(sc, i) {\n\t\t\tquery_op = &sc->vf2pf_mbox->query[0].q_op;\n\t\t\tbnx2x_init_first_tlv(sc, &query_op->first_tlv,\n\t\t\t\t\tBNX2X_VF_TLV_TEARDOWN_Q,\n\t\t\t\t\tsizeof(*query_op));\n\n\t\t\tquery_op->vf_qid = i;\n\n\t\t\tBNX2X_TLV_APPEND(query_op, query_op->first_tlv.length,\n\t\t\t\t\tBNX2X_VF_TLV_LIST_END,\n\t\t\t\t\tsizeof(struct channel_list_end_tlv));\n\n\t\t\tret = bnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);\n\t\t\tif (ret)\n\t\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\t\t\"Bad reply for vf_q %d teardown\", i);\n\t\t}\n\n\t\tbnx2x_vf_set_mac(sc, false);\n\n\t\tquery = &sc->vf2pf_mbox->query[0].close;\n\t\tbnx2x_init_first_tlv(sc, &query->first_tlv, BNX2X_VF_TLV_CLOSE,\n\t\t\t\tsizeof(*query));\n\n\t\tquery->vf_id = vf_id;\n\n\t\tBNX2X_TLV_APPEND(query, query->first_tlv.length,\n\t\t\t\tBNX2X_VF_TLV_LIST_END,\n\t\t\t\tsizeof(struct channel_list_end_tlv));\n\n\t\tret = bnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);\n\n\t\tif (ret)\n\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\"Bad reply from PF for close message\");\n\t}\n}\n\nstatic inline uint16_t\nbnx2x_vf_q_flags(uint8_t leading)\n{\n\tuint16_t flags = leading ? BNX2X_VF_Q_FLAG_LEADING_RSS : 0;\n\n\tflags |= BNX2X_VF_Q_FLAG_CACHE_ALIGN;\n\tflags |= BNX2X_VF_Q_FLAG_STATS;\n\tflags |= BNX2X_VF_Q_FLAG_VLAN;\n\n\treturn flags;\n}\n\nstatic void\nbnx2x_vf_rx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n\t\tstruct vf_rxq_params *rxq_init, uint16_t flags)\n{\n\tstruct bnx2x_rx_queue *rxq;\n\n\trxq = sc->rx_queues[fp->index];\n\tif (!rxq) {\n\t\tPMD_DRV_LOG(ERR, \"RX queue %d is NULL\", fp->index);\n\t\treturn;\n\t}\n\n\trxq_init->rcq_addr = rxq->cq_ring_phys_addr;\n\trxq_init->rcq_np_addr = rxq->cq_ring_phys_addr + BNX2X_PAGE_SIZE;\n\trxq_init->rxq_addr = rxq->rx_ring_phys_addr;\n\trxq_init->vf_sb_id = fp->index;\n\trxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;\n\trxq_init->mtu = sc->mtu;\n\trxq_init->buf_sz = fp->rx_buf_size;\n\trxq_init->flags = flags;\n\trxq_init->stat_id = -1;\n\trxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;\n}\n\nstatic void\nbnx2x_vf_tx_q_prep(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n\t\tstruct vf_txq_params *txq_init, uint16_t flags)\n{\n\tstruct bnx2x_tx_queue *txq;\n\n\ttxq = sc->tx_queues[fp->index];\n\tif (!txq) {\n\t\tPMD_DRV_LOG(ERR, \"TX queue %d is NULL\", fp->index);\n\t\treturn;\n\t}\n\n\ttxq_init->txq_addr = txq->tx_ring_phys_addr;\n\ttxq_init->sb_index = HC_INDEX_ETH_TX_CQ_CONS_COS0;\n\ttxq_init->flags = flags;\n\ttxq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;\n\ttxq_init->vf_sb_id = fp->index;\n}\n\nint\nbnx2x_vf_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, int leading)\n{\n\tstruct vf_setup_q_tlv *query;\n\tuint16_t flags = bnx2x_vf_q_flags(leading);\n\tint ret;\n\n\tquery = &sc->vf2pf_mbox->query[0].setup_q;\n\tbnx2x_init_first_tlv(sc, &query->first_tlv, BNX2X_VF_TLV_SETUP_Q,\n\t\t\tsizeof(*query));\n\n\tquery->vf_qid = fp->index;\n\tquery->param_valid = VF_RXQ_VALID | VF_TXQ_VALID;\n\n\tbnx2x_vf_rx_q_prep(sc, fp, &query->rxq, flags);\n\tbnx2x_vf_tx_q_prep(sc, fp, &query->txq, flags);\n\n\tBNX2X_TLV_APPEND(query, query->first_tlv.length, BNX2X_VF_TLV_LIST_END,\n\t\t\tsizeof(struct channel_list_end_tlv));\n\n\tret = bnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);\n\n\tif (ret) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to setup VF queue[%d]\",\n\t\t\t\tfp->index);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nint\nbnx2x_vf_set_mac(struct bnx2x_softc *sc, int set)\n{\n\tstruct vf_set_q_filters_tlv *query;\n\tstruct vf_common_reply_tlv *reply;\n\n\tquery = &sc->vf2pf_mbox->query[0].set_q_filters;\n\tbnx2x_init_first_tlv(sc, &query->first_tlv, BNX2X_VF_TLV_SET_Q_FILTERS,\n\t\t\tsizeof(*query));\n\n\tquery->vf_qid = sc->fp->index;\n\tquery->mac_filters_cnt = 1;\n\tquery->flags = BNX2X_VF_MAC_VLAN_CHANGED;\n\n\tquery->filters[0].flags = (set ? BNX2X_VF_Q_FILTER_SET_MAC : 0) |\n\t\tBNX2X_VF_Q_FILTER_DEST_MAC_VALID;\n\n\tbnx2x_check_bull(sc);\n\n\trte_memcpy(query->filters[0].mac, sc->link_params.mac_addr, ETH_ALEN);\n\n\tBNX2X_TLV_APPEND(query, query->first_tlv.length, BNX2X_VF_TLV_LIST_END,\n\t\t\tsizeof(struct channel_list_end_tlv));\n\n\tbnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);\n\treply = &sc->vf2pf_mbox->resp.common_reply;\n\n\twhile (BNX2X_VF_STATUS_FAILURE == reply->status &&\n\t\t\tbnx2x_check_bull(sc)) {\n\t\t/* A new mac was configured by PF for us */\n\t\trte_memcpy(sc->link_params.mac_addr, sc->pf2vf_bulletin->mac,\n\t\t\t\tETH_ALEN);\n\t\trte_memcpy(query->filters[0].mac, sc->pf2vf_bulletin->mac,\n\t\t\t\tETH_ALEN);\n\n\t\tbnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);\n\t}\n\n\tif (BNX2X_VF_STATUS_SUCCESS != reply->status) {\n\t\tPMD_DRV_LOG(ERR, \"Bad reply from PF for SET MAC message: %d\",\n\t\t\t\treply->status);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nint\nbnx2x_vf_config_rss(struct bnx2x_softc *sc,\n\t\t\t struct ecore_config_rss_params *params)\n{\n\tstruct vf_rss_tlv *query;\n\tint ret;\n\n\tquery = &sc->vf2pf_mbox->query[0].update_rss;\n\n\tbnx2x_init_first_tlv(sc, &query->first_tlv, BNX2X_VF_TLV_UPDATE_RSS,\n\t\t\tsizeof(*query));\n\n\t/* add list termination tlv */\n\tBNX2X_TLV_APPEND(query, query->first_tlv.length, BNX2X_VF_TLV_LIST_END,\n\t\t\tsizeof(struct channel_list_end_tlv));\n\n\trte_memcpy(query->rss_key, params->rss_key, sizeof(params->rss_key));\n\tquery->rss_key_size = T_ETH_RSS_KEY;\n\n\trte_memcpy(query->ind_table, params->ind_table, T_ETH_INDIRECTION_TABLE_SIZE);\n\tquery->ind_table_size = T_ETH_INDIRECTION_TABLE_SIZE;\n\n\tquery->rss_result_mask = params->rss_result_mask;\n\tquery->rss_flags = params->rss_flags;\n\n\tret = bnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);\n\tif (ret) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to send message to PF, rc %d\", ret);\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nint\nbnx2x_vf_set_rx_mode(struct bnx2x_softc *sc)\n{\n\tstruct vf_set_q_filters_tlv *query;\n\tunsigned long tx_mask;\n\tint ret;\n\n\tquery = &sc->vf2pf_mbox->query[0].set_q_filters;\n\tbnx2x_init_first_tlv(sc, &query->first_tlv, BNX2X_VF_TLV_SET_Q_FILTERS,\n\t\t\tsizeof(*query));\n\n\tquery->vf_qid = 0;\n\tquery->flags = BNX2X_VF_RX_MASK_CHANGED;\n\n\tif (bnx2x_fill_accept_flags(sc, sc->rx_mode, &query->rx_mask, &tx_mask)) {\n\t\treturn -EINVAL;\n\t}\n\n\tBNX2X_TLV_APPEND(query, query->first_tlv.length, BNX2X_VF_TLV_LIST_END,\n\t\t\tsizeof(struct channel_list_end_tlv));\n\n\tret = bnx2x_do_req4pf(sc, sc->vf2pf_mbox_mapping.paddr);\n\tif (ret) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to send message to PF, rc %d\", ret);\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "drivers/net/bnx2x/bnx2x_vfpf.h", "content": "/*\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n *\n * All rights reserved.\n */\n\n#ifndef BNX2X_VFPF_H\n#define BNX2X_VFPF_H\n\n#include \"ecore_sp.h\"\n\n#define VLAN_HLEN 4\n\nstruct vf_resource_query {\n\tuint8_t num_rxqs;\n\tuint8_t num_txqs;\n\tuint8_t num_sbs;\n\tuint8_t num_mac_filters;\n\tuint8_t num_vlan_filters;\n\tuint8_t num_mc_filters;\n};\n\n#define\tBNX2X_VF_STATUS_SUCCESS 1\n#define\tBNX2X_VF_STATUS_FAILURE 2\n#define\tBNX2X_VF_STATUS_NO_RESOURCES 4\n#define\tBNX2X_VF_BULLETIN_TRIES 5\n\n#define\tBNX2X_VF_Q_FLAG_CACHE_ALIGN 0x0008\n#define\tBNX2X_VF_Q_FLAG_STATS 0x0010\n#define\tBNX2X_VF_Q_FLAG_OV 0x0020\n#define\tBNX2X_VF_Q_FLAG_VLAN 0x0040\n#define\tBNX2X_VF_Q_FLAG_COS 0x0080\n#define\tBNX2X_VF_Q_FLAG_HC 0x0100\n#define\tBNX2X_VF_Q_FLAG_DHC 0x0200\n#define\tBNX2X_VF_Q_FLAG_LEADING_RSS 0x0400\n\nstruct vf_first_tlv {\n\tuint16_t type;\n\tuint16_t length;\n\tuint32_t reply_offset;\n};\n\n/* tlv struct for all PF replies except acquire */\nstruct vf_common_reply_tlv {\n\tuint16_t type;\n\tuint16_t length;\n\tuint8_t status;\n\tuint8_t pad[3];\n};\n\n/* used to terminate and pad a tlv list */\nstruct channel_list_end_tlv {\n\tuint16_t type;\n\tuint16_t length;\n\tuint32_t pad;\n};\n\n/* Acquire */\nstruct vf_acquire_tlv {\n\tstruct vf_first_tlv first_tlv;\n\n\tuint8_t vf_id;\n\tuint8_t pad[3];\n\n\tstruct vf_resource_query res_query;\n\n\tuint64_t bulletin_addr;\n};\n\n/* simple operation request on queue */\nstruct vf_q_op_tlv {\n\tstruct vf_first_tlv\tfirst_tlv;\n\tuint8_t vf_qid;\n\tuint8_t pad[3];\n};\n\n/* receive side scaling tlv */\nstruct vf_rss_tlv {\n\tstruct vf_first_tlv\tfirst_tlv;\n\tuint32_t\t\trss_flags;\n\tuint8_t\t\t\trss_result_mask;\n\tuint8_t\t\t\tind_table_size;\n\tuint8_t\t\t\trss_key_size;\n\tuint8_t\t\t\tpad;\n\tuint8_t\t\t\tind_table[T_ETH_INDIRECTION_TABLE_SIZE];\n\tuint32_t\t\trss_key[T_ETH_RSS_KEY];\t/* hash values */\n};\n\nstruct vf_resc {\n#define BNX2X_VF_MAX_QUEUES_PER_VF 16\n#define BNX2X_VF_MAX_SBS_PER_VF 16\n\tuint16_t hw_sbs[BNX2X_VF_MAX_SBS_PER_VF];\n\tuint8_t hw_qid[BNX2X_VF_MAX_QUEUES_PER_VF];\n\tuint8_t num_rxqs;\n\tuint8_t num_txqs;\n\tuint8_t num_sbs;\n\tuint8_t num_mac_filters;\n\tuint8_t num_vlan_filters;\n\tuint8_t num_mc_filters;\n\tuint8_t permanent_mac_addr[ETH_ALEN];\n\tuint8_t current_mac_addr[ETH_ALEN];\n\tuint16_t pf_link_speed;\n\tuint32_t pf_link_supported;\n};\n\n/* tlv struct holding reply for acquire */\nstruct vf_acquire_resp_tlv {\n\tuint16_t type;\n\tuint16_t length;\n\tuint8_t status;\n\tuint8_t pad1[3];\n\tuint32_t chip_num;\n\tuint8_t pad2[4];\n\tchar fw_ver[32];\n\tuint16_t db_size;\n\tuint8_t pad3[2];\n\tstruct vf_resc resc;\n};\n\n/* Init VF */\nstruct vf_init_tlv {\n\tstruct vf_first_tlv first_tlv;\n\tuint64_t sb_addr[BNX2X_VF_MAX_SBS_PER_VF];\n\tuint64_t spq_addr;\n\tuint64_t stats_addr;\n\tuint16_t stats_step;\n\tuint32_t flags;\n\tuint32_t pad[2];\n};\n\nstruct vf_rxq_params {\n\t/* physical addresses */\n\tuint64_t rcq_addr;\n\tuint64_t rcq_np_addr;\n\tuint64_t rxq_addr;\n\tuint64_t pad1;\n\n\t/* sb + hc info */\n\tuint8_t vf_sb_id;\n\tuint8_t sb_cq_index;\n\tuint16_t hc_rate;\t/* desired interrupts per sec. */\n\t/* rx buffer info */\n\tuint16_t mtu;\n\tuint16_t buf_sz;\n\tuint16_t flags; /* for BNX2X_VF_Q_FLAG_X flags */\n\tuint16_t stat_id;\t/* valid if BNX2X_VF_Q_FLAG_STATS */\n\n\tuint8_t pad2[5];\n\n\tuint8_t drop_flags;\n\tuint8_t cache_line_log;\t/* BNX2X_VF_Q_FLAG_CACHE_ALIGN */\n\tuint8_t pad3;\n};\n\nstruct vf_txq_params {\n\t/* physical addresses */\n\tuint64_t txq_addr;\n\n\t/* sb + hc info */\n\tuint8_t vf_sb_id;\t/* index in hw_sbs[] */\n\tuint8_t sb_index;\t/* Index in the SB */\n\tuint16_t hc_rate;\t/* desired interrupts per sec. */\n\tuint32_t flags;\t\t/* for BNX2X_VF_Q_FLAG_X flags */\n\tuint16_t stat_id;\t/* valid if BNX2X_VF_Q_FLAG_STATS */\n\tuint8_t traffic_type;\t/* see in setup_context() */\n\tuint8_t pad;\n};\n\n/* Setup Queue */\nstruct vf_setup_q_tlv {\n\tstruct vf_first_tlv first_tlv;\n\n\tstruct vf_rxq_params rxq;\n\tstruct vf_txq_params txq;\n\n\tuint8_t vf_qid;\t\t\t/* index in hw_qid[] */\n\tuint8_t param_valid;\n\t#define VF_RXQ_VALID\t\t0x01\n\t#define VF_TXQ_VALID\t\t0x02\n\tuint8_t pad[2];\n};\n\n/* Set Queue Filters */\nstruct vf_q_mac_vlan_filter {\n\tuint32_t flags;\n\t#define BNX2X_VF_Q_FILTER_DEST_MAC_VALID\t0x01\n\t#define BNX2X_VF_Q_FILTER_VLAN_TAG_VALID\t0x02\n\t#define BNX2X_VF_Q_FILTER_SET_MAC\t\t0x100\t/* set/clear */\n\tuint8_t mac[ETH_ALEN];\n\tuint16_t vlan_tag;\n};\n\n\n#define _UP_ETH_ALEN\t(6)\n\n/* configure queue filters */\nstruct vf_set_q_filters_tlv {\n\tstruct vf_first_tlv first_tlv;\n\n\tuint32_t flags;\n\t#define BNX2X_VF_MAC_VLAN_CHANGED \t0x01\n\t#define BNX2X_VF_MULTICAST_CHANGED\t0x02\n\t#define BNX2X_VF_RX_MASK_CHANGED \t0x04\n\n\tuint8_t vf_qid;\t\t\t/* index in hw_qid[] */\n\tuint8_t mac_filters_cnt;\n\tuint8_t multicast_cnt;\n\tuint8_t pad;\n\n\t#define VF_MAX_MAC_FILTERS\t\t\t16\n\t#define VF_MAX_VLAN_FILTERS \t\t16\n\t#define VF_MAX_FILTERS \t\t\t(VF_MAX_MAC_FILTERS +\\\n\t\t\t\t\t\t\tVF_MAX_VLAN_FILTERS)\n\tstruct vf_q_mac_vlan_filter filters[VF_MAX_FILTERS];\n\n\t#define VF_MAX_MULTICAST_PER_VF \t\t32\n\tuint8_t multicast[VF_MAX_MULTICAST_PER_VF][_UP_ETH_ALEN];\n\tunsigned long rx_mask;\n};\n\n\n/* close VF (disable VF) */\nstruct vf_close_tlv {\n\tstruct vf_first_tlv\tfirst_tlv;\n\tuint16_t\t\tvf_id; /* for debug */\n\tuint8_t pad[2];\n};\n\n/* rlease the VF's acquired resources */\nstruct vf_release_tlv {\n\tstruct vf_first_tlv first_tlv;\n\tuint16_t\t\tvf_id; /* for debug */\n\tuint8_t pad[2];\n};\n\nunion query_tlvs {\n\tstruct vf_first_tlv\t\tfirst_tlv;\n\tstruct vf_acquire_tlv\t\tacquire;\n\tstruct vf_init_tlv\t\tinit;\n\tstruct vf_close_tlv\t\tclose;\n\tstruct vf_q_op_tlv\t\tq_op;\n\tstruct vf_setup_q_tlv\t\tsetup_q;\n\tstruct vf_set_q_filters_tlv\tset_q_filters;\n\tstruct vf_release_tlv\t\trelease;\n\tstruct vf_rss_tlv\t\tupdate_rss;\n\tstruct channel_list_end_tlv list_end;\n};\n\nunion resp_tlvs {\n\tstruct vf_common_reply_tlv\tcommon_reply;\n\tstruct vf_acquire_resp_tlv\tacquire_resp;\n\tstruct channel_list_end_tlv\tlist_end;\n};\n\n/* struct allocated by VF driver, PF sends updates to VF via bulletin */\nstruct bnx2x_vf_bulletin {\n\tuint32_t crc;\t\t\t/* crc of structure to ensure is not in\n\t\t\t\t\t * mid-update\n\t\t\t\t\t */\n\tuint16_t version;\n\tuint16_t length;\n\n\tuint64_t valid_bitmap;\t/* bitmap indicating wich fields\n\t\t\t\t\t * hold valid values\n\t\t\t\t\t */\n\n#define MAC_ADDR_VALID\t\t0\t/* alert the vf that a new mac address\n\t\t\t\t\t * is available for it\n\t\t\t\t\t */\n#define VLAN_VALID\t\t1\t/* when set, the vf should no access the\n\t\t\t\t\t * vf channel\n\t\t\t\t\t */\n#define CHANNEL_DOWN\t\t2\t/* vf channel is disabled. VFs are not\n\t\t\t\t\t * to attempt to send messages on the\n\t\t\t\t\t * channel after this bit is set\n\t\t\t\t\t */\n\tuint8_t mac[ETH_ALEN];\n\tuint8_t mac_pad[2];\n\n\tuint16_t vlan;\n\tuint8_t vlan_pad[6];\n};\n\n#define MAX_TLVS_IN_LIST 50\nenum channel_tlvs {\n\tBNX2X_VF_TLV_NONE, /* ends tlv sequence */\n\tBNX2X_VF_TLV_ACQUIRE,\n\tBNX2X_VF_TLV_INIT,\n\tBNX2X_VF_TLV_SETUP_Q,\n\tBNX2X_VF_TLV_SET_Q_FILTERS,\n\tBNX2X_VF_TLV_ACTIVATE_Q,\n\tBNX2X_VF_TLV_DEACTIVATE_Q,\n\tBNX2X_VF_TLV_TEARDOWN_Q,\n\tBNX2X_VF_TLV_CLOSE,\n\tBNX2X_VF_TLV_RELEASE,\n\tBNX2X_VF_TLV_UPDATE_RSS_OLD,\n\tBNX2X_VF_TLV_PF_RELEASE_VF,\n\tBNX2X_VF_TLV_LIST_END,\n\tBNX2X_VF_TLV_FLR,\n\tBNX2X_VF_TLV_PF_SET_MAC,\n\tBNX2X_VF_TLV_PF_SET_VLAN,\n\tBNX2X_VF_TLV_UPDATE_RSS,\n\tBNX2X_VF_TLV_MAX\n};\n\nstruct bnx2x_vf_mbx_msg {\n\tunion query_tlvs query[BNX2X_VF_MAX_QUEUES_PER_VF];\n\tunion resp_tlvs resp;\n};\n\nvoid bnx2x_add_tlv(void *tlvs_list, uint16_t offset, uint16_t type, uint16_t length);\nint bnx2x_vf_set_mac(struct bnx2x_softc *sc, int set);\nint bnx2x_vf_config_rss(struct bnx2x_softc *sc, struct ecore_config_rss_params *params);\n\n#endif /* BNX2X_VFPF_H */\n" }, { "path": "drivers/net/bnx2x/debug.c", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"bnx2x.h\"\n\n\n/*\n * Debug versions of the 8/16/32 bit OS register read/write functions to\n * capture/display values read/written from/to the controller.\n */\nvoid\nbnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val)\n{\n\tPMD_DRV_LOG(DEBUG, \"offset=0x%08lx val=0x%02x\", offset, val);\n\t*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val;\n}\n\nvoid\nbnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val)\n{\n\tif ((offset % 2) != 0) {\n\t\tPMD_DRV_LOG(DEBUG, \"Unaligned 16-bit write to 0x%08lx\", offset);\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"offset=0x%08lx val=0x%04x\", offset, val);\n\t*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val;\n}\n\nvoid\nbnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val)\n{\n\tif ((offset % 4) != 0) {\n\t\tPMD_DRV_LOG(DEBUG, \"Unaligned 32-bit write to 0x%08lx\", offset);\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"offset=0x%08lx val=0x%08x\", offset, val);\n\t*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)) = val;\n}\n\nuint8_t\nbnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset)\n{\n\tuint8_t val;\n\n\tval = (uint8_t)(*((volatile uint8_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)));\n\tPMD_DRV_LOG(DEBUG, \"offset=0x%08lx val=0x%02x\", offset, val);\n\n\treturn (val);\n}\n\nuint16_t\nbnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset)\n{\n\tuint16_t val;\n\n\tif ((offset % 2) != 0) {\n\t\tPMD_DRV_LOG(DEBUG, \"Unaligned 16-bit read from 0x%08lx\", offset);\n\t}\n\n\tval = (uint16_t)(*((volatile uint16_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)));\n\tPMD_DRV_LOG(DEBUG, \"offset=0x%08lx val=0x%08x\", offset, val);\n\n\treturn (val);\n}\n\nuint32_t\nbnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset)\n{\n\tuint32_t val;\n\n\tif ((offset % 4) != 0) {\n\t\tPMD_DRV_LOG(DEBUG, \"Unaligned 32-bit read from 0x%08lx\", offset);\n\t\treturn 0;\n\t}\n\n\tval = (uint32_t)(*((volatile uint32_t*)((uint64_t)sc->bar[BAR0].base_addr + offset)));\n\tPMD_DRV_LOG(DEBUG, \"offset=0x%08lx val=0x%08x\", offset, val);\n\n\treturn (val);\n}\n" }, { "path": "drivers/net/bnx2x/ecore_fw_defs.h", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ECORE_FW_DEFS_H\n#define ECORE_FW_DEFS_H\n\n\n#define CSTORM_ASSERT_LIST_INDEX_OFFSET\t(IRO[148].base)\n#define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \\\n\t(IRO[147].base + ((assertListEntry) * IRO[147].m1))\n#define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \\\n\t(IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \\\n\tIRO[153].m2))\n#define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \\\n\t(IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \\\n\tIRO[154].m2))\n#define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \\\n\t(IRO[155].base + ((vfId) * IRO[155].m1))\n#define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \\\n\t(IRO[156].base + ((vfId) * IRO[156].m1))\n#define CSTORM_VF_TO_PF_OFFSET(funcId) \\\n\t(IRO[150].base + ((funcId) * IRO[150].m1))\n#define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \\\n\t(IRO[159].base + ((funcId) * IRO[159].m1))\n#define CSTORM_FUNC_EN_OFFSET(funcId) \\\n\t(IRO[149].base + ((funcId) * IRO[149].m1))\n#define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \\\n\t(IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2))\n#define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \\\n\t(IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \\\n\t* IRO[138].m2) + ((sbId) * IRO[138].m3))\n#define CSTORM_IGU_MODE_OFFSET (IRO[157].base)\n#define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \\\n\t(IRO[317].base + ((pfId) * IRO[317].m1))\n#define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \\\n\t(IRO[318].base + ((pfId) * IRO[318].m1))\n#define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \\\n\t(IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2))\n#define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \\\n\t(IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2))\n#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \\\n\t(IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2))\n#define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \\\n\t(IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2))\n#define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \\\n\t(IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2))\n#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \\\n\t(IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))\n#define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \\\n\t(IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2))\n#define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \\\n\t(IRO[316].base + ((pfId) * IRO[316].m1))\n#define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \\\n\t(IRO[308].base + ((pfId) * IRO[308].m1))\n#define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \\\n\t(IRO[307].base + ((pfId) * IRO[307].m1))\n#define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \\\n\t(IRO[306].base + ((pfId) * IRO[306].m1))\n#define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \\\n\t(IRO[151].base + ((funcId) * IRO[151].m1))\n#define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \\\n\t(IRO[142].base + ((pfId) * IRO[142].m1))\n#define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \\\n\t(IRO[143].base + ((pfId) * IRO[143].m1))\n#define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \\\n\t(IRO[141].base + ((pfId) * IRO[141].m1))\n#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size)\n#define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \\\n\t(IRO[144].base + ((pfId) * IRO[144].m1))\n#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size)\n#define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \\\n\t(IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2))\n#define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \\\n\t(IRO[133].base + ((sbId) * IRO[133].m1))\n#define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \\\n\t(IRO[134].base + ((sbId) * IRO[134].m1))\n#define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \\\n\t(IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2))\n#define CSTORM_STATUS_BLOCK_OFFSET(sbId) \\\n\t(IRO[132].base + ((sbId) * IRO[132].m1))\n#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size)\n#define CSTORM_SYNC_BLOCK_OFFSET(sbId) \\\n\t(IRO[137].base + ((sbId) * IRO[137].m1))\n#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size)\n#define CSTORM_VF_TO_PF_OFFSET(funcId) \\\n\t(IRO[150].base + ((funcId) * IRO[150].m1))\n#define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[204].base)\n#define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \\\n\t(IRO[203].base + ((pfId) * IRO[203].m1))\n#define TSTORM_ASSERT_LIST_INDEX_OFFSET\t(IRO[102].base)\n#define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \\\n\t(IRO[101].base + ((assertListEntry) * IRO[101].m1))\n#define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \\\n\t(IRO[201].base + ((pfId) * IRO[201].m1))\n#define TSTORM_FUNC_EN_OFFSET(funcId) \\\n\t(IRO[103].base + ((funcId) * IRO[103].m1))\n#define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \\\n\t(IRO[272].base + ((pfId) * IRO[272].m1))\n#define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \\\n\t(IRO[271].base + ((pfId) * IRO[271].m1))\n#define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \\\n\t(IRO[270].base + ((pfId) * IRO[270].m1))\n#define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \\\n\t(IRO[269].base + ((pfId) * IRO[269].m1))\n#define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \\\n\t(IRO[268].base + ((pfId) * IRO[268].m1))\n#define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \\\n\t(IRO[278].base + ((pfId) * IRO[278].m1))\n#define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \\\n\t(IRO[264].base + ((pfId) * IRO[264].m1))\n#define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \\\n\t(IRO[265].base + ((pfId) * IRO[265].m1))\n#define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \\\n\t(IRO[266].base + ((pfId) * IRO[266].m1))\n#define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \\\n\t(IRO[267].base + ((pfId) * IRO[267].m1))\n#define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \\\n\t(IRO[202].base + ((pfId) * IRO[202].m1))\n#define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \\\n\t(IRO[105].base + ((funcId) * IRO[105].m1))\n#define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \\\n\t(IRO[217].base + ((pfId) * IRO[217].m1))\n#define TSTORM_VF_TO_PF_OFFSET(funcId) \\\n\t(IRO[104].base + ((funcId) * IRO[104].m1))\n#define USTORM_AGG_DATA_OFFSET (IRO[206].base)\n#define USTORM_AGG_DATA_SIZE (IRO[206].size)\n#define USTORM_ASSERT_LIST_INDEX_OFFSET\t(IRO[177].base)\n#define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \\\n\t(IRO[176].base + ((assertListEntry) * IRO[176].m1))\n#define USTORM_CQE_PAGE_NEXT_OFFSET(portId, clientId) \\\n\t(IRO[205].base + ((portId) * IRO[205].m1) + ((clientId) * IRO[205].m2))\n#define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \\\n\t(IRO[183].base + ((portId) * IRO[183].m1))\n#define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \\\n\t(IRO[319].base + ((pfId) * IRO[319].m1))\n#define USTORM_FUNC_EN_OFFSET(funcId) \\\n\t(IRO[178].base + ((funcId) * IRO[178].m1))\n#define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \\\n\t(IRO[283].base + ((pfId) * IRO[283].m1))\n#define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \\\n\t(IRO[284].base + ((pfId) * IRO[284].m1))\n#define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \\\n\t(IRO[288].base + ((pfId) * IRO[288].m1))\n#define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \\\n\t(IRO[285].base + ((pfId) * IRO[285].m1))\n#define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \\\n\t(IRO[281].base + ((pfId) * IRO[281].m1))\n#define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \\\n\t(IRO[280].base + ((pfId) * IRO[280].m1))\n#define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \\\n\t(IRO[279].base + ((pfId) * IRO[279].m1))\n#define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \\\n\t(IRO[282].base + ((pfId) * IRO[282].m1))\n#define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \\\n\t(IRO[286].base + ((pfId) * IRO[286].m1))\n#define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \\\n\t(IRO[287].base + ((pfId) * IRO[287].m1))\n#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \\\n\t(IRO[182].base + ((pfId) * IRO[182].m1))\n#define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \\\n\t(IRO[180].base + ((funcId) * IRO[180].m1))\n#define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \\\n\t(IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \\\n\tIRO[209].m2))\n#define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \\\n\t(IRO[210].base + ((qzoneId) * IRO[210].m1))\n#define USTORM_TPA_BTR_OFFSET (IRO[207].base)\n#define USTORM_TPA_BTR_SIZE (IRO[207].size)\n#define USTORM_VF_TO_PF_OFFSET(funcId) \\\n\t(IRO[179].base + ((funcId) * IRO[179].m1))\n#define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)\n#define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)\n#define XSTORM_ASSERT_LIST_INDEX_OFFSET\t(IRO[51].base)\n#define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \\\n\t(IRO[50].base + ((assertListEntry) * IRO[50].m1))\n#define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \\\n\t(IRO[43].base + ((portId) * IRO[43].m1))\n#define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \\\n\t(IRO[45].base + ((pfId) * IRO[45].m1))\n#define XSTORM_FUNC_EN_OFFSET(funcId) \\\n\t(IRO[47].base + ((funcId) * IRO[47].m1))\n#define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \\\n\t(IRO[296].base + ((pfId) * IRO[296].m1))\n#define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \\\n\t(IRO[299].base + ((pfId) * IRO[299].m1))\n#define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \\\n\t(IRO[300].base + ((pfId) * IRO[300].m1))\n#define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \\\n\t(IRO[301].base + ((pfId) * IRO[301].m1))\n#define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \\\n\t(IRO[302].base + ((pfId) * IRO[302].m1))\n#define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \\\n\t(IRO[303].base + ((pfId) * IRO[303].m1))\n#define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \\\n\t(IRO[304].base + ((pfId) * IRO[304].m1))\n#define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \\\n\t(IRO[305].base + ((pfId) * IRO[305].m1))\n#define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \\\n\t(IRO[295].base + ((pfId) * IRO[295].m1))\n#define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \\\n\t(IRO[294].base + ((pfId) * IRO[294].m1))\n#define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \\\n\t(IRO[293].base + ((pfId) * IRO[293].m1))\n#define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \\\n\t(IRO[298].base + ((pfId) * IRO[298].m1))\n#define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \\\n\t(IRO[297].base + ((pfId) * IRO[297].m1))\n#define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \\\n\t(IRO[292].base + ((pfId) * IRO[292].m1))\n#define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \\\n\t(IRO[291].base + ((pfId) * IRO[291].m1))\n#define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \\\n\t(IRO[290].base + ((pfId) * IRO[290].m1))\n#define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \\\n\t(IRO[289].base + ((pfId) * IRO[289].m1))\n#define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \\\n\t(IRO[44].base + ((pfId) * IRO[44].m1))\n#define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \\\n\t(IRO[49].base + ((funcId) * IRO[49].m1))\n#define XSTORM_SPQ_DATA_OFFSET(funcId) \\\n\t(IRO[32].base + ((funcId) * IRO[32].m1))\n#define XSTORM_SPQ_DATA_SIZE (IRO[32].size)\n#define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \\\n\t(IRO[30].base + ((funcId) * IRO[30].m1))\n#define XSTORM_SPQ_PROD_OFFSET(funcId) \\\n\t(IRO[31].base + ((funcId) * IRO[31].m1))\n#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \\\n\t(IRO[211].base + ((portId) * IRO[211].m1))\n#define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \\\n\t(IRO[212].base + ((portId) * IRO[212].m1))\n#define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \\\n\t(IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \\\n\tIRO[214].m2))\n#define XSTORM_VF_TO_PF_OFFSET(funcId) \\\n\t(IRO[48].base + ((funcId) * IRO[48].m1))\n#define COMMON_ASM_INVALID_ASSERT_OPCODE (IRO[7].base)\n\n\n/* Ethernet Ring parameters */\n#define X_ETH_LOCAL_RING_SIZE 13\n#define FIRST_BD_IN_PKT\t0\n#define PARSE_BD_INDEX 1\n#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))\n\n/* Rx ring params */\n#define U_ETH_LOCAL_BD_RING_SIZE 8\n#define U_ETH_SGL_SIZE 8\n\t/* The fw will padd the buffer with this value, so the IP header \\\n\twill be align to 4 Byte */\n#define IP_HEADER_ALIGNMENT_PADDING 2\n\n#define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))\n#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))\n\n#define U_ETH_BDS_PER_PAGE_MASK\t(U_ETH_BDS_PER_PAGE-1)\n#define U_ETH_CQE_PER_PAGE_MASK\t(TU_ETH_CQES_PER_PAGE-1)\n\n#define U_ETH_UNDEFINED_Q 0xFF\n\n#define T_ETH_INDIRECTION_TABLE_SIZE 128\n#define T_ETH_RSS_KEY 10\n#define ETH_NUM_OF_RSS_ENGINES_E2 72\n\n#define FILTER_RULES_COUNT 16\n#define MULTICAST_RULES_COUNT 16\n#define CLASSIFY_RULES_COUNT 16\n\n/*The CRC32 seed, that is used for the hash(reduction) multicast address */\n#define ETH_CRC32_HASH_SEED 0x00000000\n\n#define ETH_CRC32_HASH_BIT_SIZE\t(8)\n#define ETH_CRC32_HASH_MASK EVAL((1<\n * David Christensen \n * Gary Zambrano \n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ECORE_HSI_H\n#define ECORE_HSI_H\n\n#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e\n\nstruct license_key {\n uint32_t reserved[6];\n\n uint32_t max_iscsi_conn;\n#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF\n#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0\n#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000\n#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16\n\n uint32_t reserved_a;\n\n uint32_t max_fcoe_conn;\n#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF\n#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0\n#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000\n#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16\n\n uint32_t reserved_b[4];\n};\n\ntypedef struct license_key license_key_t;\n\n\n/****************************************************************************\n * Shared HW configuration *\n ****************************************************************************/\n#define PIN_CFG_NA 0x00000000\n#define PIN_CFG_GPIO0_P0 0x00000001\n#define PIN_CFG_GPIO1_P0 0x00000002\n#define PIN_CFG_GPIO2_P0 0x00000003\n#define PIN_CFG_GPIO3_P0 0x00000004\n#define PIN_CFG_GPIO0_P1 0x00000005\n#define PIN_CFG_GPIO1_P1 0x00000006\n#define PIN_CFG_GPIO2_P1 0x00000007\n#define PIN_CFG_GPIO3_P1 0x00000008\n#define PIN_CFG_EPIO0 0x00000009\n#define PIN_CFG_EPIO1 0x0000000a\n#define PIN_CFG_EPIO2 0x0000000b\n#define PIN_CFG_EPIO3 0x0000000c\n#define PIN_CFG_EPIO4 0x0000000d\n#define PIN_CFG_EPIO5 0x0000000e\n#define PIN_CFG_EPIO6 0x0000000f\n#define PIN_CFG_EPIO7 0x00000010\n#define PIN_CFG_EPIO8 0x00000011\n#define PIN_CFG_EPIO9 0x00000012\n#define PIN_CFG_EPIO10 0x00000013\n#define PIN_CFG_EPIO11 0x00000014\n#define PIN_CFG_EPIO12 0x00000015\n#define PIN_CFG_EPIO13 0x00000016\n#define PIN_CFG_EPIO14 0x00000017\n#define PIN_CFG_EPIO15 0x00000018\n#define PIN_CFG_EPIO16 0x00000019\n#define PIN_CFG_EPIO17 0x0000001a\n#define PIN_CFG_EPIO18 0x0000001b\n#define PIN_CFG_EPIO19 0x0000001c\n#define PIN_CFG_EPIO20 0x0000001d\n#define PIN_CFG_EPIO21 0x0000001e\n#define PIN_CFG_EPIO22 0x0000001f\n#define PIN_CFG_EPIO23 0x00000020\n#define PIN_CFG_EPIO24 0x00000021\n#define PIN_CFG_EPIO25 0x00000022\n#define PIN_CFG_EPIO26 0x00000023\n#define PIN_CFG_EPIO27 0x00000024\n#define PIN_CFG_EPIO28 0x00000025\n#define PIN_CFG_EPIO29 0x00000026\n#define PIN_CFG_EPIO30 0x00000027\n#define PIN_CFG_EPIO31 0x00000028\n\n/* EPIO definition */\n#define EPIO_CFG_NA 0x00000000\n#define EPIO_CFG_EPIO0 0x00000001\n#define EPIO_CFG_EPIO1 0x00000002\n#define EPIO_CFG_EPIO2 0x00000003\n#define EPIO_CFG_EPIO3 0x00000004\n#define EPIO_CFG_EPIO4 0x00000005\n#define EPIO_CFG_EPIO5 0x00000006\n#define EPIO_CFG_EPIO6 0x00000007\n#define EPIO_CFG_EPIO7 0x00000008\n#define EPIO_CFG_EPIO8 0x00000009\n#define EPIO_CFG_EPIO9 0x0000000a\n#define EPIO_CFG_EPIO10 0x0000000b\n#define EPIO_CFG_EPIO11 0x0000000c\n#define EPIO_CFG_EPIO12 0x0000000d\n#define EPIO_CFG_EPIO13 0x0000000e\n#define EPIO_CFG_EPIO14 0x0000000f\n#define EPIO_CFG_EPIO15 0x00000010\n#define EPIO_CFG_EPIO16 0x00000011\n#define EPIO_CFG_EPIO17 0x00000012\n#define EPIO_CFG_EPIO18 0x00000013\n#define EPIO_CFG_EPIO19 0x00000014\n#define EPIO_CFG_EPIO20 0x00000015\n#define EPIO_CFG_EPIO21 0x00000016\n#define EPIO_CFG_EPIO22 0x00000017\n#define EPIO_CFG_EPIO23 0x00000018\n#define EPIO_CFG_EPIO24 0x00000019\n#define EPIO_CFG_EPIO25 0x0000001a\n#define EPIO_CFG_EPIO26 0x0000001b\n#define EPIO_CFG_EPIO27 0x0000001c\n#define EPIO_CFG_EPIO28 0x0000001d\n#define EPIO_CFG_EPIO29 0x0000001e\n#define EPIO_CFG_EPIO30 0x0000001f\n#define EPIO_CFG_EPIO31 0x00000020\n\nstruct mac_addr {\n\tuint32_t upper;\n\tuint32_t lower;\n};\n\n\nstruct shared_hw_cfg {\t\t\t /* NVRAM Offset */\n\t/* Up to 16 bytes of NULL-terminated string */\n\tuint8_t part_num[16];\t\t /* 0x104 */\n\n\tuint32_t config;\t\t\t/* 0x114 */\n\t#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001\n\t\t#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0\n\t\t#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000\n\t\t#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001\n\n\t#define SHARED_HW_CFG_PORT_SWAP 0x00000004\n\n\t #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008\n\n\t #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000\n\t #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010\n\n\t#define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700\n\t\t#define SHARED_HW_CFG_MFW_SELECT_SHIFT 8\n\t/* Whatever MFW found in NVM\n\t (if multiple found, priority order is: NC-SI, UMP, IPMI) */\n\t\t#define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000\n\t\t#define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100\n\t\t#define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200\n\t\t#define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300\n\t/* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI\n\t (can only be used when an add-in board, not BMC, pulls-down SPIO4) */\n\t\t#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400\n\t/* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI\n\t (can only be used when an add-in board, not BMC, pulls-down SPIO4) */\n\t\t#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500\n\t/* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP\n\t (can only be used when an add-in board, not BMC, pulls-down SPIO4) */\n\t\t#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600\n\n\t/* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For\n\t backwards compatibility, value of 0 is disabling this feature.\n\t That means that though 0 is a valid value, it cannot be\n\t configured. */\n\t#define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000\n\t#define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12\n\n\t#define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000\n\t\t#define SHARED_HW_CFG_LED_MODE_SHIFT 16\n\t\t#define SHARED_HW_CFG_LED_MAC1 0x00000000\n\t\t#define SHARED_HW_CFG_LED_PHY1 0x00010000\n\t\t#define SHARED_HW_CFG_LED_PHY2 0x00020000\n\t\t#define SHARED_HW_CFG_LED_PHY3 0x00030000\n\t\t#define SHARED_HW_CFG_LED_MAC2 0x00040000\n\t\t#define SHARED_HW_CFG_LED_PHY4 0x00050000\n\t\t#define SHARED_HW_CFG_LED_PHY5 0x00060000\n\t\t#define SHARED_HW_CFG_LED_PHY6 0x00070000\n\t\t#define SHARED_HW_CFG_LED_MAC3 0x00080000\n\t\t#define SHARED_HW_CFG_LED_PHY7 0x00090000\n\t\t#define SHARED_HW_CFG_LED_PHY9 0x000a0000\n\t\t#define SHARED_HW_CFG_LED_PHY11 0x000b0000\n\t\t#define SHARED_HW_CFG_LED_MAC4 0x000c0000\n\t\t#define SHARED_HW_CFG_LED_PHY8 0x000d0000\n\t\t#define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000\n\t\t#define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000\n\n #define SHARED_HW_CFG_SRIOV_MASK 0x40000000\n\t\t#define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000\n\t\t#define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000\n\n\t#define SHARED_HW_CFG_ATC_MASK 0x80000000\n\t\t#define SHARED_HW_CFG_ATC_DISABLED 0x00000000\n\t\t#define SHARED_HW_CFG_ATC_ENABLED 0x80000000\n\n\tuint32_t config2;\t\t\t /* 0x118 */\n\n\t#define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100\n\t #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8\n\t #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000\n\t#define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100\n\n\t#define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000\n\t\t#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000\n\t\t#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000\n\n\t#define SHARED_HW_CFG_HIDE_PORT1 0x00002000\n\n\n\t\t/* Output low when PERST is asserted */\n\t#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000\n\t\t#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000\n\t\t#define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000\n\n\t#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000\n\t\t#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16\n\t\t#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000\n\t\t#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000\n\t\t#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000\n\t\t#define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000\n\n\t/* The fan failure mechanism is usually related to the PHY type\n\t since the power consumption of the board is determined by the PHY.\n\t Currently, fan is required for most designs with SFX7101, BNX2X8727\n\t and BNX2X8481. If a fan is not required for a board which uses one\n\t of those PHYs, this field should be set to \"Disabled\". If a fan is\n\t required for a different PHY type, this option should be set to\n\t \"Enabled\". The fan failure indication is expected on SPIO5 */\n\t#define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000\n\t\t#define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19\n\t\t#define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000\n\t\t#define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000\n\t\t#define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000\n\n\t\t/* ASPM Power Management support */\n\t#define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000\n\t\t#define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21\n\t\t#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000\n\t\t#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000\n\t\t#define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000\n\t\t#define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000\n\n\t/* The value of PM_TL_IGNORE_REQS (bit0) in PCI register\n\t tl_control_0 (register 0x2800) */\n\t#define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000\n\t\t#define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000\n\t\t#define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000\n\n\n\t/* Set the MDC/MDIO access for the first external phy */\n\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000\n\t\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26\n\t\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000\n\t\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000\n\t\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000\n\t\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000\n\t\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000\n\n\t/* Set the MDC/MDIO access for the second external phy */\n\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000\n\t\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29\n\t\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000\n\t\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000\n\t\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000\n\t\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000\n\t\t#define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000\n\n\t/* Max number of PF MSIX vectors */\n\tuint32_t config_3; /* 0x11C */\n\t#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F\n\t#define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0\n\n\tuint32_t ump_nc_si_config;\t\t\t/* 0x120 */\n\t#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003\n\t\t#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0\n\t\t#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000\n\t\t#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001\n\t\t#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000\n\t\t#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002\n\n\t/* Reserved bits: 226-230 */\n\n\t/* The output pin template BSC_SEL which selects the I2C for this\n\tport in the I2C Mux */\n\tuint32_t board;\t\t\t/* 0x124 */\n\t#define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F\n\t #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0\n\n\t#define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0\n\t#define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6\n\t/* Use the PIN_CFG_XXX defines on top */\n\t#define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000\n\t#define SHARED_HW_CFG_BOARD_REV_SHIFT 16\n\n\t#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000\n\t#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24\n\n\t#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000\n\t#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28\n\n\tuint32_t wc_lane_config;\t\t\t\t /* 0x128 */\n\t#define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF\n\t\t#define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0\n\t\t#define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b\n\t\t#define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4\n\t\t#define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8\n\t\t#define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827\n\t\t#define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b\n\t\t#define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4\n\t#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF\n\t#define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0\n\t#define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00\n\t#define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8\n\n\t/* TX lane Polarity swap */\n\t#define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000\n\t#define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000\n\t#define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000\n\t#define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000\n\t/* TX lane Polarity swap */\n\t#define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000\n\t#define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000\n\t#define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000\n\t#define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000\n\n\t/* Selects the port layout of the board */\n\t#define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000\n\t\t#define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24\n\t\t#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000\n\t\t#define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000\n\t\t#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000\n\t\t#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000\n\t\t#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000\n\t\t#define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000\n};\n\n\n/****************************************************************************\n * Port HW configuration *\n ****************************************************************************/\nstruct port_hw_cfg {\t\t /* port 0: 0x12c port 1: 0x2bc */\n\n\tuint32_t pci_id;\n\t#define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF\n\t#define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0\n\n\t#define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000\n\t#define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16\n\n\tuint32_t pci_sub_id;\n\t#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF\n\t#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0\n\n\t#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000\n\t#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16\n\n\tuint32_t power_dissipated;\n\t#define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF\n\t#define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0\n\t#define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00\n\t#define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8\n\t#define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000\n\t#define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16\n\t#define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000\n\t#define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24\n\n\tuint32_t power_consumed;\n\t#define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF\n\t#define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0\n\t#define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00\n\t#define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8\n\t#define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000\n\t#define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16\n\t#define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000\n\t#define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24\n\n\tuint32_t mac_upper;\n\tuint32_t mac_lower; /* 0x140 */\n\t#define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF\n\t#define PORT_HW_CFG_UPPERMAC_SHIFT 0\n\n\n\tuint32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */\n\tuint32_t iscsi_mac_lower;\n\n\tuint32_t rdma_mac_upper; /* Upper 16 bits are always zeroes */\n\tuint32_t rdma_mac_lower;\n\n\tuint32_t serdes_config;\n\t#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF\n\t#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0\n\n\t#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000\n\t#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16\n\n\n\t/* Default values: 2P-64, 4P-32 */\n\tuint32_t reserved;\n\n\tuint32_t vf_config;\t\t\t\t\t /* 0x15C */\n\t#define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000\n\t#define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16\n\n\tuint32_t mf_pci_id;\t\t\t\t\t /* 0x160 */\n\t#define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF\n\t#define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0\n\n\t/* Controls the TX laser of the SFP+ module */\n\tuint32_t sfp_ctrl;\t\t\t\t\t /* 0x164 */\n\t#define PORT_HW_CFG_TX_LASER_MASK 0x000000FF\n\t\t#define PORT_HW_CFG_TX_LASER_SHIFT 0\n\t\t#define PORT_HW_CFG_TX_LASER_MDIO 0x00000000\n\t\t#define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001\n\t\t#define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002\n\t\t#define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003\n\t\t#define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004\n\n\t/* Controls the fault module LED of the SFP+ */\n\t#define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00\n\t\t#define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8\n\t\t#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000\n\t\t#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100\n\t\t#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200\n\t\t#define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300\n\t\t#define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400\n\n\t/* The output pin TX_DIS that controls the TX laser of the SFP+\n\t module. Use the PIN_CFG_XXX defines on top */\n\tuint32_t e3_sfp_ctrl;\t\t\t\t /* 0x168 */\n\t#define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF\n\t#define PORT_HW_CFG_E3_TX_LASER_SHIFT 0\n\n\t/* The output pin for SFPP_TYPE which turns on the Fault module LED */\n\t#define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00\n\t#define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8\n\n\t/* The input pin MOD_ABS that indicates whether SFP+ module is\n\t present or not. Use the PIN_CFG_XXX defines on top */\n\t#define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000\n\t#define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16\n\n\t/* The output pin PWRDIS_SFP_X which disable the power of the SFP+\n\t module. Use the PIN_CFG_XXX defines on top */\n\t#define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000\n\t#define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24\n\n\t/*\n\t * The input pin which signals module transmit fault. Use the\n\t * PIN_CFG_XXX defines on top\n\t */\n\tuint32_t e3_cmn_pin_cfg;\t\t\t\t /* 0x16C */\n\t#define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF\n\t#define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0\n\n\t/* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on\n\t top */\n\t#define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00\n\t#define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8\n\n\t/*\n\t * The output pin which powers down the PHY. Use the PIN_CFG_XXX\n\t * defines on top\n\t */\n\t#define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000\n\t#define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16\n\n\t/* The output pin values BSC_SEL which selects the I2C for this port\n\t in the I2C Mux */\n\t#define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000\n\t#define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000\n\n\n\t/*\n\t * The input pin I_FAULT which indicate over-current has occurred.\n\t * Use the PIN_CFG_XXX defines on top\n\t */\n\tuint32_t e3_cmn_pin_cfg1;\t\t\t\t /* 0x170 */\n\t#define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF\n\t#define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0\n\n\t/* pause on host ring */\n\tuint32_t generic_features; /* 0x174 */\n\t#define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001\n\t#define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0\n\t#define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000\n\t#define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001\n\n\t/* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2\n\t * LOM recommended and tested value is 0xBEB2. Using a different\n\t * value means using a value not tested by BRCM\n\t */\n\tuint32_t sfi_tap_values; /* 0x178 */\n\t#define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF\n\t#define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0\n\n\t/* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested\n\t * value is 0x2. LOM recommended and tested value is 0x2. Using a\n\t * different value means using a value not tested by BRCM\n\t */\n\t#define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000\n\t#define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16\n\n\tuint32_t reserved0[5];\t\t\t\t /* 0x17c */\n\n\tuint32_t aeu_int_mask;\t\t\t\t /* 0x190 */\n\n\tuint32_t media_type;\t\t\t\t\t /* 0x194 */\n\t#define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF\n\t#define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0\n\n\t#define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00\n\t#define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8\n\n\t#define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000\n\t#define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16\n\n\t/* 4 times 16 bits for all 4 lanes. In case external PHY is present\n\t (not direct mode), those values will not take effect on the 4 XGXS\n\t lanes. For some external PHYs (such as 8706 and 8726) the values\n\t will be used to configure the external PHY in those cases, not\n\t all 4 values are needed. */\n\tuint16_t xgxs_config_rx[4];\t\t\t/* 0x198 */\n\tuint16_t xgxs_config_tx[4];\t\t\t/* 0x1A0 */\n\n\n\t/* For storing FCOE mac on shared memory */\n\tuint32_t fcoe_fip_mac_upper;\n\t#define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff\n\t#define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0\n\tuint32_t fcoe_fip_mac_lower;\n\n\tuint32_t fcoe_wwn_port_name_upper;\n\tuint32_t fcoe_wwn_port_name_lower;\n\n\tuint32_t fcoe_wwn_node_name_upper;\n\tuint32_t fcoe_wwn_node_name_lower;\n\n\t/* wwpn for npiv enabled */\n\tuint32_t wwpn_for_npiv_config; /* 0x1C0 */\n\t#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001\n\t#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0\n\t#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000\n\t#define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001\n\n\t/* wwpn for npiv valid addresses */\n\tuint32_t wwpn_for_npiv_valid_addresses; /* 0x1C4 */\n\t#define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF\n\t#define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0\n\n\tstruct mac_addr wwpn_for_niv_macs[16];\n\n\t/* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */\n\tuint32_t Reserved1[14];\n\n\tuint32_t pf_allocation; /* 0x280 */\n\t/* number of vfs per PF, if 0 - sriov disabled */\n\t#define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF\n\t#define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0\n\n\t/* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),\n\t 84833 only */\n\tuint32_t xgbt_phy_cfg;\t\t\t\t /* 0x284 */\n\t#define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF\n\t#define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0\n\n\t\tuint32_t default_cfg;\t\t\t /* 0x288 */\n\t#define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003\n\t\t#define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0\n\t\t#define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000\n\t\t#define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001\n\t\t#define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002\n\t\t#define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003\n\n\t#define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C\n\t\t#define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2\n\t\t#define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000\n\t\t#define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004\n\t\t#define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008\n\t\t#define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c\n\n\t#define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030\n\t\t#define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4\n\t\t#define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000\n\t\t#define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010\n\t\t#define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020\n\t\t#define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030\n\n\t#define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0\n\t\t#define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6\n\t\t#define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000\n\t\t#define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040\n\t\t#define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080\n\t\t#define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0\n\n\t/* When KR link is required to be set to force which is not\n\t KR-compliant, this parameter determine what is the trigger for it.\n\t When GPIO is selected, low input will force the speed. Currently\n\t default speed is 1G. In the future, it may be widen to select the\n\t forced speed in with another parameter. Note when force-1G is\n\t enabled, it override option 56: Link Speed option. */\n\t#define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00\n\t\t#define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8\n\t\t#define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000\n\t\t#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100\n\t\t#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200\n\t\t#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300\n\t\t#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400\n\t\t#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500\n\t\t#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600\n\t\t#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700\n\t\t#define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800\n\t\t#define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900\n\t/* Enable to determine with which GPIO to reset the external phy */\n\t#define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000\n\t\t#define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16\n\t\t#define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000\n\t\t#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000\n\t\t#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000\n\t\t#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000\n\t\t#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000\n\t\t#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000\n\t\t#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000\n\t\t#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000\n\t\t#define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000\n\n\t/* Enable BAM on KR */\n\t#define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000\n\t#define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20\n\t#define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000\n\t#define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000\n\n\t/* Enable Common Mode Sense */\n\t#define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000\n\t#define PORT_HW_CFG_ENABLE_CMS_SHIFT 21\n\t#define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000\n\t#define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000\n\n\t/* Determine the Serdes electrical interface */\n\t#define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000\n\t#define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24\n\t#define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000\n\t#define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000\n\t#define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000\n\t#define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000\n\t#define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000\n\t#define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000\n\n\t/* SFP+ main TAP and post TAP volumes */\n\t#define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000\n\t#define PORT_HW_CFG_TAP_LEVELS_SHIFT 28\n\t#define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000\n\t#define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000\n\t#define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000\n\t#define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000\n\t#define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000\n\t#define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000\n\n\tuint32_t speed_capability_mask2;\t\t\t /* 0x28C */\n\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002\n\t #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080\n\n\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000\n\t #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000\n\n\n\t/* In the case where two media types (e.g. copper and fiber) are\n\t present and electrically active at the same time, PHY Selection\n\t will determine which of the two PHYs will be designated as the\n\t Active PHY and used for a connection to the network. */\n\tuint32_t multi_phy_config;\t\t\t\t /* 0x290 */\n\t#define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007\n\t\t#define PORT_HW_CFG_PHY_SELECTION_SHIFT 0\n\t\t#define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000\n\t\t#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001\n\t\t#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002\n\t\t#define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003\n\t\t#define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004\n\n\t/* When enabled, all second phy nvram parameters will be swapped\n\t with the first phy parameters */\n\t#define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008\n\t\t#define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3\n\t\t#define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000\n\t\t#define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008\n\n\n\t/* Address of the second external phy */\n\tuint32_t external_phy_config2;\t\t\t /* 0x294 */\n\t#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF\n\t#define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0\n\n\t/* The second XGXS external PHY type */\n\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8071 0x00000100\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8072 0x00000200\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8073 0x00000300\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8705 0x00000400\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8706 0x00000500\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8726 0x00000600\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8481 0x00000700\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8727 0x00000900\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8727_NOC 0x00000a00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84823 0x00000b00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54640 0x00000c00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84833 0x00000d00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54618SE 0x00000e00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X8722 0x00000f00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X54616 0x00001000\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BNX2X84834 0x00001100\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00\n\n\n\t/* 4 times 16 bits for all 4 lanes. For some external PHYs (such as\n\t 8706, 8726 and 8727) not all 4 values are needed. */\n\tuint16_t xgxs_config2_rx[4];\t\t\t\t /* 0x296 */\n\tuint16_t xgxs_config2_tx[4];\t\t\t\t /* 0x2A0 */\n\n\tuint32_t lane_config;\n\t#define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF\n\t\t#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0\n\t\t/* AN and forced */\n\t\t#define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b\n\t\t/* forced only */\n\t\t#define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4\n\t\t/* forced only */\n\t\t#define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8\n\t\t/* forced only */\n\t\t#define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4\n\t#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF\n\t#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0\n\t#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00\n\t#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8\n\t#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000\n\t#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14\n\n\t/* Indicate whether to swap the external phy polarity */\n\t#define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000\n\t\t#define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000\n\t\t#define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000\n\n\n\tuint32_t external_phy_config;\n\t#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF\n\t#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0\n\n\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8071 0x00000100\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8072 0x00000200\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073 0x00000300\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705 0x00000400\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706 0x00000500\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726 0x00000600\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481 0x00000700\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727 0x00000900\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC 0x00000a00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823 0x00000b00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54640 0x00000c00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833 0x00000d00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE 0x00000e00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722 0x00000f00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616 0x00001000\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834 0x00001100\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00\n\t\t#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00\n\n\t#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000\n\t#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16\n\n\t#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000\n\t\t#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24\n\t\t#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000\n\t\t#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BNX2X5482 0x01000000\n\t\t#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000\n\t\t#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000\n\n\tuint32_t speed_capability_mask;\n\t#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000\n\n\t#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000\n\t\t#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000\n\n\t/* A place to hold the original MAC address as a backup */\n\tuint32_t backup_mac_upper;\t\t\t/* 0x2B4 */\n\tuint32_t backup_mac_lower;\t\t\t/* 0x2B8 */\n\n};\n\n\n/****************************************************************************\n * Shared Feature configuration *\n ****************************************************************************/\nstruct shared_feat_cfg {\t\t /* NVRAM Offset */\n\n\tuint32_t config;\t\t\t/* 0x450 */\n\t#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001\n\n\t/* Use NVRAM values instead of HW default values */\n\t#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \\\n\t\t\t\t\t\t\t 0x00000002\n\t\t#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \\\n\t\t\t\t\t\t\t\t 0x00000000\n\t\t#define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \\\n\t\t\t\t\t\t\t\t 0x00000002\n\n\t#define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008\n\t\t#define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000\n\t\t#define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008\n\n\t#define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030\n\t#define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4\n\n\t/* Override the OTP back to single function mode. When using GPIO,\n\t high means only SF, 0 is according to CLP configuration */\n\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700\n\t\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8\n\t\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000\n\t\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100\n\t\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200\n\t\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300\n\t\t#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400\n\n\t/* Act as if the FCoE license is invalid */\n\t#define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000\n\n /* Force FLR capability to all ports */\n\t#define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000\n\n\t/* Act as if the iSCSI license is invalid */\n\t#define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000\n\t#define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14\n\t#define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000\n\t#define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000\n\n\t/* The interval in seconds between sending LLDP packets. Set to zero\n\t to disable the feature */\n\t#define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000\n\t#define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16\n\n\t/* The assigned device type ID for LLDP usage */\n\t#define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000\n\t#define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24\n\n};\n\n\n/****************************************************************************\n * Port Feature configuration *\n ****************************************************************************/\nstruct port_feat_cfg {\t\t /* port 0: 0x454 port 1: 0x4c8 */\n\n\tuint32_t config;\n\t#define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e\n\t\t#define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f\n\t#define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0\n\t\t#define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0\n\n\t#define PORT_FEAT_CFG_DCBX_MASK 0x00000100\n\t\t#define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000\n\t\t#define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100\n\n #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200\n\t #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9\n\t #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000\n\t #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200\n\n\t#define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00\n\t#define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10\n\t#define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000\n\t#define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400\n\t#define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800\n\t#define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00\n\n\t#define PORT_FEATURE_EN_SIZE_MASK 0x0f000000\n\t#define PORT_FEATURE_EN_SIZE_SHIFT 24\n\t#define PORT_FEATURE_WOL_ENABLED 0x01000000\n\t#define PORT_FEATURE_MBA_ENABLED 0x02000000\n\t#define PORT_FEATURE_MFW_ENABLED 0x04000000\n\n\t/* Advertise expansion ROM even if MBA is disabled */\n\t#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000\n\t\t#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000\n\t\t#define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000\n\n\t/* Check the optic vendor via i2c against a list of approved modules\n\t in a separate nvram image */\n\t#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000\n\t\t#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29\n\t\t#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \\\n\t\t\t\t\t\t\t\t 0x00000000\n\t\t#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \\\n\t\t\t\t\t\t\t\t 0x20000000\n\t\t#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000\n\t\t#define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000\n\n\tuint32_t wol_config;\n\t/* Default is used when driver sets to \"auto\" mode */\n\t#define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010\n\n\tuint32_t mba_config;\n\t#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007\n\t\t#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0\n\t\t#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000\n\t\t#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001\n\t\t#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002\n\t\t#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003\n\t\t#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004\n\t\t#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007\n\n\t#define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038\n\t#define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3\n\n #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400\n\t#define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800\n\t\t#define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000\n\t\t#define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800\n\n\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000\n\t\t#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000\n\t#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000\n\t#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20\n\t#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000\n\t\t#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24\n\t\t#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000\n\t\t#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000\n\t\t#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000\n\t\t#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000\n\t#define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000\n\t\t#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26\n\t\t#define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000\n\t\t#define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000\n\t\t#define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000\n\t\t#define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000\n\t\t#define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000\n\t\t#define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000\n\t\t#define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000\n\t\t#define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000\n\t\t#define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000\n\n\tuint32_t Reserved0; /* 0x460 */\n\n\tuint32_t mba_vlan_cfg;\n\t#define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF\n\t#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0\n\t#define PORT_FEATURE_MBA_VLAN_EN 0x00010000\n\n\tuint32_t Reserved1;\n\tuint32_t smbus_config;\n\t#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe\n\t#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1\n\n\tuint32_t vf_config;\n\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e\n\t\t#define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f\n\n\tuint32_t link_config; /* Used as HW defaults for the driver */\n\n #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700\n\t\t#define PORT_FEATURE_FLOW_CONTROL_SHIFT 8\n\t\t#define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000\n\t\t#define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100\n\t\t#define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200\n\t\t#define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300\n\t\t#define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400\n\t\t#define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500\n\t\t#define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600\n\t\t#define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700\n\n #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000\n\t\t#define PORT_FEATURE_LINK_SPEED_SHIFT 16\n\t\t#define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000\n\t\t#define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000\n\t\t#define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000\n\t\t#define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000\n\t\t#define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000\n\t\t#define PORT_FEATURE_LINK_SPEED_1G 0x00050000\n\t\t#define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000\n\t\t#define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000\n\t\t#define PORT_FEATURE_LINK_SPEED_20G 0x00080000\n\n\t#define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000\n\t\t#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24\n\t\t/* (forced) low speed switch (< 10G) */\n\t\t#define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000\n\t\t/* (forced) high speed switch (>= 10G) */\n\t\t#define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000\n\t\t#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000\n\t\t#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000\n\n\n\t/* The default for MCP link configuration,\n\t uses the same defines as link_config */\n\tuint32_t mfw_wol_link_cfg;\n\n\t/* The default for the driver of the second external phy,\n\t uses the same defines as link_config */\n\tuint32_t link_config2;\t\t\t\t /* 0x47C */\n\n\t/* The default for MCP of the second external phy,\n\t uses the same defines as link_config */\n\tuint32_t mfw_wol_link_cfg2;\t\t\t\t /* 0x480 */\n\n\n\t/* EEE power saving mode */\n\tuint32_t eee_power_mode; /* 0x484 */\n\t#define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF\n\t#define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0\n\t#define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000\n\t#define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001\n\t#define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002\n\t#define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003\n\n\n\tuint32_t Reserved2[16]; /* 0x488 */\n};\n\n/****************************************************************************\n * Device Information *\n ****************************************************************************/\nstruct shm_dev_info {\t\t\t\t/* size */\n\n\tuint32_t bc_rev; /* 8 bits each: major, minor, build */\t /* 4 */\n\n\tstruct shared_hw_cfg shared_hw_config;\t /* 40 */\n\n\tstruct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */\n\n\tstruct shared_feat_cfg shared_feature_config;\t\t /* 4 */\n\n\tstruct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */\n\n};\n\nstruct extended_dev_info_shared_cfg { /* NVRAM OFFSET */\n\n\t/* Threshold in celcius to start using the fan */\n\tuint32_t temperature_monitor1; /* 0x4000 */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0\n\n\t/* Threshold in celcius to shut down the board */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8\n\n\t/* EPIO of fan temperature status */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000\n\n\t/* EPIO of shut down temperature status */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000\n\n\n\t/* EPIO of shut down temperature status */\n\tuint32_t temperature_monitor2; /* 0x4004 */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0\n\n\n\t/* MFW flavor to be used */\n\tuint32_t mfw_cfg; /* 0x4008 */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001\n\n\t/* Should NIC data query remain enabled upon last drv unload */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100\n\n\t/* Hide DCBX feature in CCM/BACS menus */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000\n\n\tuint32_t smbus_config; /* 0x400C */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0\n\n\t/* Switching regulator loop gain */\n\tuint32_t board_cfg; /* 0x4010 */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f\n\n\t/* whether shadow swim feature is supported */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100\n\n /* whether to show/hide SRIOV menu in CCM */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200\n\n\t/* Threshold in celcius for max continuous operation */\n\tuint32_t temperature_report; /* 0x4014 */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0\n\n\t/* Threshold in celcius for sensor caution */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8\n\n\t/* wwn node prefix to be used (unless value is 0) */\n\tuint32_t wwn_prefix; /* 0x4018 */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0\n\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8\n\n\t/* wwn port prefix to be used (unless value is 0) */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16\n\n\t/* wwn port prefix to be used (unless value is 0) */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24\n\n\t/* General debug nvm cfg */\n\tuint32_t dbg_cfg_flags; /* 0x401C */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000\n\n\t/* Debug signet rx threshold */\n\tuint32_t dbg_rx_sigdet_threshold; /* 0x4020 */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0\n\n /* Enable IFFE feature */\n\tuint32_t iffe_features; /* 0x4024 */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001\n\n\t/* Allowable port enablement (bitmask for ports 3-1) */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1\n\n\t/* Allow iSCSI offload override */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010\n\n\t/* Allow FCoE offload override */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020\n\n\t/* Tie to adaptor */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000\n\n\t/* Currently enabled port(s) (bitmask for ports 3-1) */\n\tuint32_t current_iffe_mask; /* 0x4028 */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1\n\n\t/* Current iSCSI offload */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010\n\n\t/* Current FCoE offload */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020\n\n\t/* FW set this pin to \"0\" (assert) these signal if either of its MAC\n\t * or PHY specific threshold values is exceeded.\n\t * Values are standard GPIO/EPIO pins.\n\t */\n\tuint32_t threshold_pin; /* 0x402C */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16\n\n\t/* MAC die temperature threshold in Celsius. */\n\tuint32_t mac_threshold_val; /* 0x4030 */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16\n\n\t/* PHY die temperature threshold in Celsius. */\n\tuint32_t phy_threshold_val; /* 0x4034 */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16\n\n\t/* External pins to communicate with host.\n\t * Values are standard GPIO/EPIO pins.\n\t */\n\tuint32_t host_pin; /* 0x4038 */\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000\n\t#define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24\n};\n\n\n#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)\n\t#error \"Missing either LITTLE_ENDIAN or BIG_ENDIAN definition.\"\n#endif\n\n#define FUNC_0 0\n#define FUNC_1 1\n#define FUNC_2 2\n#define FUNC_3 3\n#define FUNC_4 4\n#define FUNC_5 5\n#define FUNC_6 6\n#define FUNC_7 7\n#define E1H_FUNC_MAX 8\n#define E2_FUNC_MAX 4 /* per path */\n\n#define VN_0 0\n#define VN_1 1\n#define VN_2 2\n#define VN_3 3\n#define E1VN_MAX 1\n#define E1HVN_MAX 4\n\n#define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */\n/* This value (in milliseconds) determines the frequency of the driver\n * issuing the PULSE message code. The firmware monitors this periodic\n * pulse to determine when to switch to an OS-absent mode. */\n#define DRV_PULSE_PERIOD_MS 250\n\n/* This value (in milliseconds) determines how long the driver should\n * wait for an acknowledgement from the firmware before timing out. Once\n * the firmware has timed out, the driver will assume there is no firmware\n * running and there won't be any firmware-driver synchronization during a\n * driver reset. */\n#define FW_ACK_TIME_OUT_MS 5000\n\n#define FW_ACK_POLL_TIME_MS 1\n\n#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)\n\n#define MFW_TRACE_SIGNATURE 0x54524342\n\n/****************************************************************************\n * Driver <-> FW Mailbox *\n ****************************************************************************/\nstruct drv_port_mb {\n\n\tuint32_t link_status;\n\t/* Driver should update this field on any link change event */\n\n\t#define LINK_STATUS_NONE\t\t\t\t(0<<0)\n\t#define LINK_STATUS_LINK_FLAG_MASK\t\t\t0x00000001\n\t#define LINK_STATUS_LINK_UP\t\t\t\t0x00000001\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_MASK\t\t0x0000001E\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE\t(0<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_10THD\t\t(1<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD\t\t(2<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD\t\t(3<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_100T4\t\t(4<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD\t\t(5<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD\t\t(6<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD\t\t(7<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD\t\t(7<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD\t\t(8<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD\t\t(9<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD\t\t(9<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD\t\t(10<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD\t\t(10<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD\t\t(11<<1)\n\t#define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD\t\t(11<<1)\n\n\t#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK\t\t0x00000020\n\t#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED\t\t0x00000020\n\n\t#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE\t\t0x00000040\n\t#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK\t0x00000080\n\t#define LINK_STATUS_PARALLEL_DETECTION_USED\t\t0x00000080\n\n\t#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE\t0x00000200\n\t#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE\t0x00000400\n\t#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE\t\t0x00000800\n\t#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE\t0x00001000\n\t#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE\t0x00002000\n\t#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE\t\t0x00004000\n\t#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE\t\t0x00008000\n\n\t#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK\t\t0x00010000\n\t#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED\t\t0x00010000\n\n\t#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK\t\t0x00020000\n\t#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED\t\t0x00020000\n\n\t#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK\t0x000C0000\n\t#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE\t(0<<18)\n\t#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE\t(1<<18)\n\t#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE\t(2<<18)\n\t#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE\t\t(3<<18)\n\n\t#define LINK_STATUS_SERDES_LINK\t\t\t\t0x00100000\n\n\t#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE\t0x00200000\n\t#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE\t0x00400000\n\t#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE\t\t0x00800000\n\t#define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE\t\t0x10000000\n\n\t#define LINK_STATUS_PFC_ENABLED\t\t\t\t0x20000000\n\n\t#define LINK_STATUS_PHYSICAL_LINK_FLAG\t\t\t0x40000000\n\t#define LINK_STATUS_SFP_TX_FAULT\t\t\t0x80000000\n\n\tuint32_t port_stx;\n\n\tuint32_t stat_nig_timer;\n\n\t/* MCP firmware does not use this field */\n\tuint32_t ext_phy_fw_version;\n\n};\n\n\nstruct drv_func_mb {\n\n\tuint32_t drv_mb_header;\n\t#define DRV_MSG_CODE_MASK 0xffff0000\n\t#define DRV_MSG_CODE_LOAD_REQ 0x10000000\n\t#define DRV_MSG_CODE_LOAD_DONE 0x11000000\n\t#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000\n\t#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000\n\t#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000\n\t#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000\n\t#define DRV_MSG_CODE_DCC_OK 0x30000000\n\t#define DRV_MSG_CODE_DCC_FAILURE 0x31000000\n\t#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000\n\t#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000\n\t#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000\n\t#define DRV_MSG_CODE_GET_CURR_KEY 0x80000000\n\t#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000\n\t#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000\n\t#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000\n\n\t/*\n\t * The optic module verification command requires bootcode\n\t * v5.0.6 or later, te specific optic module verification command\n\t * requires bootcode v5.2.12 or later\n\t */\n\t#define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000\n\t#define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006\n\t#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000\n\t#define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234\n\t#define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000\n\t#define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002\n\t#define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014\n\t#define REQ_BC_VER_4_MT_SUPPORTED 0x00070201\n\t#define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201\n\t#define REQ_BC_VER_4_FCOE_FEATURES 0x00070209\n\n\t#define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000\n\t#define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000\n\t#define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401\n\n\t#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000\n\n\t#define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000\n\t#define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000\n\t#define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000\n\t#define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000\n\t#define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000\n\n\t#define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000\n\t#define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000\n\n\t#define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000\n\n\t#define DRV_MSG_CODE_RMMOD 0xdb000000\n\t#define REQ_BC_VER_4_RMMOD_CMD 0x0007080f\n\n\t#define DRV_MSG_CODE_SET_MF_BW 0xe0000000\n\t#define REQ_BC_VER_4_SET_MF_BW 0x00060202\n\t#define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000\n\n\t#define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000\n\n\t#define DRV_MSG_CODE_INITIATE_FLR 0x02000000\n\t#define REQ_BC_VER_4_INITIATE_FLR 0x00070213\n\n\t#define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000\n\t#define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000\n\t#define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000\n\t#define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000\n\n\t#define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000\n\t#define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000\n\n\t#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff\n\n\tuint32_t drv_mb_param;\n\t#define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000\n\t#define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000\n\n\t#define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001\n\t#define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002\n\n\t#define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a\n\t#define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000\n\n\t#define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001\n\n\tuint32_t fw_mb_header;\n\t#define FW_MSG_CODE_MASK 0xffff0000\n\t#define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000\n\t#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000\n\t#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000\n\t/* Load common chip is supported from bc 6.0.0 */\n\t#define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000\n\t#define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000\n\n\t#define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000\n\t#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000\n\t#define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000\n\t#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000\n\t#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000\n\t#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000\n\t#define FW_MSG_CODE_DCC_DONE 0x30100000\n\t#define FW_MSG_CODE_LLDP_DONE 0x40100000\n\t#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000\n\t#define FW_MSG_CODE_DIAG_REFUSE 0x50200000\n\t#define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000\n\t#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000\n\t#define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000\n\t#define FW_MSG_CODE_GET_KEY_DONE 0x80100000\n\t#define FW_MSG_CODE_NO_KEY 0x80f00000\n\t#define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000\n\t#define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000\n\t#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000\n\t#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000\n\t#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000\n\t#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000\n\t#define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000\n\t#define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000\n\t#define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000\n\t#define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000\n\t#define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000\n\n\t#define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000\n\t#define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000\n\t#define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000\n\t#define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000\n\t#define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000\n\n\t#define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000\n\t#define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000\n\n\t#define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000\n\n\t#define FW_MSG_CODE_RMMOD_ACK 0xdb100000\n\n\t#define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000\n\t#define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000\n\n\t#define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000\n\n\t#define FW_MSG_CODE_FLR_ACK 0x02000000\n\t#define FW_MSG_CODE_FLR_NACK 0x02100000\n\n\t#define FW_MSG_CODE_LIC_CHALLENGE 0xff010000\n\t#define FW_MSG_CODE_LIC_RESPONSE 0xff020000\n\t#define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000\n\t#define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000\n\n\t#define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000\n\t#define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000\n\n\t#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff\n\n\tuint32_t fw_mb_param;\n\n\t#define FW_PARAM_INVALID_IMG 0xffffffff\n\n\tuint32_t drv_pulse_mb;\n\t#define DRV_PULSE_SEQ_MASK 0x00007fff\n\t#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000\n\t/*\n\t * The system time is in the format of\n\t * (year-2001)*12*32 + month*32 + day.\n\t */\n\t#define DRV_PULSE_ALWAYS_ALIVE 0x00008000\n\t/*\n\t * Indicate to the firmware not to go into the\n\t * OS-absent when it is not getting driver pulse.\n\t * This is used for debugging as well for PXE(MBA).\n\t */\n\n\tuint32_t mcp_pulse_mb;\n\t#define MCP_PULSE_SEQ_MASK 0x00007fff\n\t#define MCP_PULSE_ALWAYS_ALIVE 0x00008000\n\t/* Indicates to the driver not to assert due to lack\n\t * of MCP response */\n\t#define MCP_EVENT_MASK 0xffff0000\n\t#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000\n\n\tuint32_t iscsi_boot_signature;\n\tuint32_t iscsi_boot_block_offset;\n\n\tuint32_t drv_status;\n\t#define DRV_STATUS_PMF 0x00000001\n\t#define DRV_STATUS_VF_DISABLED 0x00000002\n\t#define DRV_STATUS_SET_MF_BW 0x00000004\n\t#define DRV_STATUS_LINK_EVENT 0x00000008\n\n\t#define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00\n\t#define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100\n\t#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200\n\t#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400\n\t#define DRV_STATUS_DCC_RESERVED1 0x00000800\n\t#define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000\n\t#define DRV_STATUS_DCC_SET_PRIORITY 0x00002000\n\n\t#define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000\n\t#define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000\n\t#define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000\n\t#define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000\n\t#define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000\n\t#define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000\n\t#define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000\n\n\t#define DRV_STATUS_DRV_INFO_REQ 0x04000000\n\n\t#define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000\n\n\tuint32_t virt_mac_upper;\n\t#define VIRT_MAC_SIGN_MASK 0xffff0000\n\t#define VIRT_MAC_SIGNATURE 0x564d0000\n\tuint32_t virt_mac_lower;\n\n};\n\n\n/****************************************************************************\n * Management firmware state *\n ****************************************************************************/\n/* Allocate 440 bytes for management firmware */\n#define MGMTFW_STATE_WORD_SIZE 110\n\nstruct mgmtfw_state {\n\tuint32_t opaque[MGMTFW_STATE_WORD_SIZE];\n};\n\n\n/****************************************************************************\n * Multi-Function configuration *\n ****************************************************************************/\nstruct shared_mf_cfg {\n\n\tuint32_t clp_mb;\n\t#define SHARED_MF_CLP_SET_DEFAULT 0x00000000\n\t/* set by CLP */\n\t#define SHARED_MF_CLP_EXIT 0x00000001\n\t/* set by MCP */\n\t#define SHARED_MF_CLP_EXIT_DONE 0x00010000\n\n};\n\nstruct port_mf_cfg {\n\n\tuint32_t dynamic_cfg; /* device control channel */\n\t#define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff\n\t#define PORT_MF_CFG_E1HOV_TAG_SHIFT 0\n\t#define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK\n\n\tuint32_t reserved[1];\n\n};\n\nstruct func_mf_cfg {\n\n\tuint32_t config;\n\t/* E/R/I/D */\n\t/* function 0 of each port cannot be hidden */\n\t#define FUNC_MF_CFG_FUNC_HIDE 0x00000001\n\n\t#define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006\n\t#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000\n\t#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002\n\t#define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004\n\t#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006\n\t#define FUNC_MF_CFG_PROTOCOL_DEFAULT \\\n\t\t\t\tFUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA\n\n\t#define FUNC_MF_CFG_FUNC_DISABLED 0x00000008\n\t#define FUNC_MF_CFG_FUNC_DELETED 0x00000010\n\n\t#define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060\n\t#define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000\n\t#define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020\n\t#define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040\n\n\t/* PRI */\n\t/* 0 - low priority, 3 - high priority */\n\t#define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300\n\t#define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8\n\t#define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000\n\n\t/* MINBW, MAXBW */\n\t/* value range - 0..100, increments in 100Mbps */\n\t#define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000\n\t#define FUNC_MF_CFG_MIN_BW_SHIFT 16\n\t#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000\n\t#define FUNC_MF_CFG_MAX_BW_MASK 0xff000000\n\t#define FUNC_MF_CFG_MAX_BW_SHIFT 24\n\t#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000\n\n\tuint32_t mac_upper;\t /* MAC */\n\t#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff\n\t#define FUNC_MF_CFG_UPPERMAC_SHIFT 0\n\t#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK\n\tuint32_t mac_lower;\n\t#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff\n\n\tuint32_t e1hov_tag;\t/* VNI */\n\t#define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff\n\t#define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0\n\t#define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK\n\n\t/* afex default VLAN ID - 12 bits */\n\t#define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000\n\t#define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16\n\n\tuint32_t afex_config;\n\t#define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff\n\t#define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0\n\t#define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00\n\t#define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8\n\t#define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100\n\t#define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000\n\t#define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16\n\n\tuint32_t pf_allocation;\n\t/* number of vfs in function, if 0 - sriov disabled */\n\t#define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF\n\t#define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0\n};\n\nenum mf_cfg_afex_vlan_mode {\n\tFUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,\n\tFUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,\n\tFUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE\n};\n\n/* This structure is not applicable and should not be accessed on 57711 */\nstruct func_ext_cfg {\n\tuint32_t func_cfg;\n\t#define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F\n\t#define MACP_FUNC_CFG_FLAGS_SHIFT 0\n\t#define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001\n\t#define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002\n\t#define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004\n\t#define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008\n #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080\n\n\tuint32_t iscsi_mac_addr_upper;\n\tuint32_t iscsi_mac_addr_lower;\n\n\tuint32_t fcoe_mac_addr_upper;\n\tuint32_t fcoe_mac_addr_lower;\n\n\tuint32_t fcoe_wwn_port_name_upper;\n\tuint32_t fcoe_wwn_port_name_lower;\n\n\tuint32_t fcoe_wwn_node_name_upper;\n\tuint32_t fcoe_wwn_node_name_lower;\n\n\tuint32_t preserve_data;\n\t#define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)\n\t#define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)\n\t#define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)\n\t#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)\n\t#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)\n\t#define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)\n};\n\nstruct mf_cfg {\n\n\tstruct shared_mf_cfg shared_mf_config; /* 0x4 */\n\tstruct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX];\n /* 0x10*2=0x20 */\n\t/* for all chips, there are 8 mf functions */\n\tstruct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */\n\t/*\n\t * Extended configuration per function - this array does not exist and\n\t * should not be accessed on 57711\n\t */\n\tstruct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/\n}; /* 0x224 */\n\n/****************************************************************************\n * Shared Memory Region *\n ****************************************************************************/\nstruct shmem_region {\t\t /* SharedMem Offset (size) */\n\n\tuint32_t validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */\n\t#define SHR_MEM_FORMAT_REV_MASK 0xff000000\n\t#define SHR_MEM_FORMAT_REV_ID ('A'<<24)\n\t/* validity bits */\n\t#define SHR_MEM_VALIDITY_PCI_CFG 0x00100000\n\t#define SHR_MEM_VALIDITY_MB 0x00200000\n\t#define SHR_MEM_VALIDITY_DEV_INFO 0x00400000\n\t#define SHR_MEM_VALIDITY_RESERVED 0x00000007\n\t/* One licensing bit should be set */\n\t#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038\n\t#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008\n\t#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010\n\t#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020\n\t/* Active MFW */\n\t#define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000\n\t#define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0\n\t#define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040\n\t#define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080\n\t#define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0\n\t#define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0\n\n\tstruct shm_dev_info dev_info;\t /* 0x8 (0x438) */\n\n\tlicense_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */\n\n\t/* FW information (for internal FW use) */\n\tuint32_t fw_info_fio_offset;\t\t/* 0x4a8 (0x4) */\n\tstruct mgmtfw_state mgmtfw_state;\t/* 0x4ac (0x1b8) */\n\n\tstruct drv_port_mb port_mb[PORT_MAX];\t/* 0x664 (16*2=0x20) */\n\n\n#ifdef BMAPI\n\t/* This is a variable length array */\n\t/* the number of function depends on the chip type */\n\tstruct drv_func_mb func_mb[1];\t/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */\n#else\n\t/* the number of function depends on the chip type */\n\tstruct drv_func_mb func_mb[];\t/* 0x684 (44*2/4/8=0x58/0xb0/0x160) */\n#endif /* BMAPI */\n\n}; /* 57711 = 0x7E4 | 57712 = 0x734 */\n\n/****************************************************************************\n * Shared Memory 2 Region *\n ****************************************************************************/\n/* The fw_flr_ack is actually built in the following way: */\n/* 8 bit: PF ack */\n/* 64 bit: VF ack */\n/* 8 bit: ios_dis_ack */\n/* In order to maintain endianity in the mailbox hsi, we want to keep using */\n/* uint32_t. The fw must have the VF right after the PF since this is how it */\n/* access arrays(it expects always the VF to reside after the PF, and that */\n/* makes the calculation much easier for it. ) */\n/* In order to answer both limitations, and keep the struct small, the code */\n/* will abuse the structure defined here to achieve the actual partition */\n/* above */\n/****************************************************************************/\nstruct fw_flr_ack {\n\tuint32_t pf_ack;\n\tuint32_t vf_ack[1];\n\tuint32_t iov_dis_ack;\n};\n\nstruct fw_flr_mb {\n\tuint32_t aggint;\n\tuint32_t opgen_addr;\n\tstruct fw_flr_ack ack;\n};\n\nstruct eee_remote_vals {\n\tuint32_t tx_tw;\n\tuint32_t rx_tw;\n};\n\n/**** SUPPORT FOR SHMEM ARRRAYS ***\n * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to\n * define arrays with storage types smaller then unsigned dwords.\n * The macros below add generic support for SHMEM arrays with numeric elements\n * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword\n * array with individual bit-filed elements accessed using shifts and masks.\n *\n */\n\n/* eb is the bitwidth of a single element */\n#define SHMEM_ARRAY_MASK(eb)\t\t((1<<(eb))-1)\n#define SHMEM_ARRAY_ENTRY(i, eb)\t((i)/(32/(eb)))\n\n/* the bit-position macro allows the used to flip the order of the arrays\n * elements on a per byte or word boundary.\n *\n * example: an array with 8 entries each 4 bit wide. This array will fit into\n * a single dword. The diagrmas below show the array order of the nibbles.\n *\n * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:\n *\n * | | | |\n * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |\n * | | | |\n *\n * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:\n *\n * | | | |\n * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |\n * | | | |\n *\n * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:\n *\n * | | | |\n * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |\n * | | | |\n */\n#define SHMEM_ARRAY_BITPOS(i, eb, fb)\t\\\n\t((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \\\n\t(((i)%((fb)/(eb))) * (eb)))\n\n#define SHMEM_ARRAY_GET(a, i, eb, fb)\t\t\t\t\t\\\n\t((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \\\n\tSHMEM_ARRAY_MASK(eb))\n\n#define SHMEM_ARRAY_SET(a, i, eb, fb, val)\t\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\t \\\n\ta[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<\t \\\n\tSHMEM_ARRAY_BITPOS(i, eb, fb));\t\t\t\t\t \\\n\ta[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \\\n\tSHMEM_ARRAY_BITPOS(i, eb, fb));\t\t\t\t\t \\\n} while (0)\n\n\n/****START OF DCBX STRUCTURES DECLARATIONS****/\n#define DCBX_MAX_NUM_PRI_PG_ENTRIES\t8\n#define DCBX_PRI_PG_BITWIDTH\t\t4\n#define DCBX_PRI_PG_FBITS\t\t8\n#define DCBX_PRI_PG_GET(a, i)\t\t\\\n\tSHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)\n#define DCBX_PRI_PG_SET(a, i, val)\t\\\n\tSHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)\n#define DCBX_MAX_NUM_PG_BW_ENTRIES\t8\n#define DCBX_BW_PG_BITWIDTH\t\t8\n#define DCBX_PG_BW_GET(a, i)\t\t\\\n\tSHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)\n#define DCBX_PG_BW_SET(a, i, val)\t\\\n\tSHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)\n#define DCBX_STRICT_PRI_PG\t\t15\n#define DCBX_MAX_APP_PROTOCOL\t\t16\n#define DCBX_MAX_APP_LOCAL\t 32\n#define FCOE_APP_IDX\t\t\t0\n#define ISCSI_APP_IDX\t\t\t1\n#define PREDEFINED_APP_IDX_MAX\t\t2\n\n\n/* Big/Little endian have the same representation. */\nstruct dcbx_ets_feature {\n\t/*\n\t * For Admin MIB - is this feature supported by the\n\t * driver | For Local MIB - should this feature be enabled.\n\t */\n\tuint32_t enabled;\n\tuint32_t pg_bw_tbl[2];\n\tuint32_t pri_pg_tbl[1];\n};\n\n/* Driver structure in LE */\nstruct dcbx_pfc_feature {\n#ifdef __BIG_ENDIAN\n\tuint8_t pri_en_bitmap;\n\t#define DCBX_PFC_PRI_0 0x01\n\t#define DCBX_PFC_PRI_1 0x02\n\t#define DCBX_PFC_PRI_2 0x04\n\t#define DCBX_PFC_PRI_3 0x08\n\t#define DCBX_PFC_PRI_4 0x10\n\t#define DCBX_PFC_PRI_5 0x20\n\t#define DCBX_PFC_PRI_6 0x40\n\t#define DCBX_PFC_PRI_7 0x80\n\tuint8_t pfc_caps;\n\tuint8_t reserved;\n\tuint8_t enabled;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t enabled;\n\tuint8_t reserved;\n\tuint8_t pfc_caps;\n\tuint8_t pri_en_bitmap;\n\t#define DCBX_PFC_PRI_0 0x01\n\t#define DCBX_PFC_PRI_1 0x02\n\t#define DCBX_PFC_PRI_2 0x04\n\t#define DCBX_PFC_PRI_3 0x08\n\t#define DCBX_PFC_PRI_4 0x10\n\t#define DCBX_PFC_PRI_5 0x20\n\t#define DCBX_PFC_PRI_6 0x40\n\t#define DCBX_PFC_PRI_7 0x80\n#endif\n};\n\nstruct dcbx_app_priority_entry {\n#ifdef __BIG_ENDIAN\n\tuint16_t app_id;\n\tuint8_t pri_bitmap;\n\tuint8_t appBitfield;\n\t#define DCBX_APP_ENTRY_VALID 0x01\n\t#define DCBX_APP_ENTRY_SF_MASK 0x30\n\t#define DCBX_APP_ENTRY_SF_SHIFT 4\n\t#define DCBX_APP_SF_ETH_TYPE 0x10\n\t#define DCBX_APP_SF_PORT 0x20\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t appBitfield;\n\t#define DCBX_APP_ENTRY_VALID 0x01\n\t#define DCBX_APP_ENTRY_SF_MASK 0x30\n\t#define DCBX_APP_ENTRY_SF_SHIFT 4\n\t#define DCBX_APP_SF_ETH_TYPE 0x10\n\t#define DCBX_APP_SF_PORT 0x20\n\tuint8_t pri_bitmap;\n\tuint16_t app_id;\n#endif\n};\n\n\n/* FW structure in BE */\nstruct dcbx_app_priority_feature {\n#ifdef __BIG_ENDIAN\n\tuint8_t reserved;\n\tuint8_t default_pri;\n\tuint8_t tc_supported;\n\tuint8_t enabled;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t enabled;\n\tuint8_t tc_supported;\n\tuint8_t default_pri;\n\tuint8_t reserved;\n#endif\n\tstruct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];\n};\n\n/* FW structure in BE */\nstruct dcbx_features {\n\t/* PG feature */\n\tstruct dcbx_ets_feature ets;\n\t/* PFC feature */\n\tstruct dcbx_pfc_feature pfc;\n\t/* APP feature */\n\tstruct dcbx_app_priority_feature app;\n};\n\n/* LLDP protocol parameters */\n/* FW structure in BE */\nstruct lldp_params {\n#ifdef __BIG_ENDIAN\n\tuint8_t msg_fast_tx_interval;\n\tuint8_t msg_tx_hold;\n\tuint8_t msg_tx_interval;\n\tuint8_t admin_status;\n\t#define LLDP_TX_ONLY 0x01\n\t#define LLDP_RX_ONLY 0x02\n\t#define LLDP_TX_RX 0x03\n\t#define LLDP_DISABLED 0x04\n\tuint8_t reserved1;\n\tuint8_t tx_fast;\n\tuint8_t tx_crd_max;\n\tuint8_t tx_crd;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t admin_status;\n\t#define LLDP_TX_ONLY 0x01\n\t#define LLDP_RX_ONLY 0x02\n\t#define LLDP_TX_RX 0x03\n\t#define LLDP_DISABLED 0x04\n\tuint8_t msg_tx_interval;\n\tuint8_t msg_tx_hold;\n\tuint8_t msg_fast_tx_interval;\n\tuint8_t tx_crd;\n\tuint8_t tx_crd_max;\n\tuint8_t tx_fast;\n\tuint8_t reserved1;\n#endif\n\t#define REM_CHASSIS_ID_STAT_LEN 4\n\t#define REM_PORT_ID_STAT_LEN 4\n\t/* Holds remote Chassis ID TLV header, subtype and 9B of payload. */\n\tuint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];\n\t/* Holds remote Port ID TLV header, subtype and 9B of payload. */\n\tuint32_t peer_port_id[REM_PORT_ID_STAT_LEN];\n};\n\nstruct lldp_dcbx_stat {\n\t#define LOCAL_CHASSIS_ID_STAT_LEN 2\n\t#define LOCAL_PORT_ID_STAT_LEN 2\n\t/* Holds local Chassis ID 8B payload of constant subtype 4. */\n\tuint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];\n\t/* Holds local Port ID 8B payload of constant subtype 3. */\n\tuint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN];\n\t/* Number of DCBX frames transmitted. */\n\tuint32_t num_tx_dcbx_pkts;\n\t/* Number of DCBX frames received. */\n\tuint32_t num_rx_dcbx_pkts;\n};\n\n/* ADMIN MIB - DCBX local machine default configuration. */\nstruct lldp_admin_mib {\n\tuint32_t ver_cfg_flags;\n\t#define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001\n\t#define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002\n\t#define DCBX_APP_CONFIG_TX_ENABLED 0x00000004\n\t#define DCBX_ETS_RECO_TX_ENABLED 0x00000008\n\t#define DCBX_ETS_RECO_VALID 0x00000010\n\t#define DCBX_ETS_WILLING 0x00000020\n\t#define DCBX_PFC_WILLING 0x00000040\n\t#define DCBX_APP_WILLING 0x00000080\n\t#define DCBX_VERSION_CEE 0x00000100\n\t#define DCBX_VERSION_IEEE 0x00000200\n\t#define DCBX_DCBX_ENABLED 0x00000400\n\t#define DCBX_CEE_VERSION_MASK 0x0000f000\n\t#define DCBX_CEE_VERSION_SHIFT 12\n\t#define DCBX_CEE_MAX_VERSION_MASK 0x000f0000\n\t#define DCBX_CEE_MAX_VERSION_SHIFT 16\n\tstruct dcbx_features features;\n};\n\n/* REMOTE MIB - remote machine DCBX configuration. */\nstruct lldp_remote_mib {\n\tuint32_t prefix_seq_num;\n\tuint32_t flags;\n\t#define DCBX_ETS_TLV_RX 0x00000001\n\t#define DCBX_PFC_TLV_RX 0x00000002\n\t#define DCBX_APP_TLV_RX 0x00000004\n\t#define DCBX_ETS_RX_ERROR 0x00000010\n\t#define DCBX_PFC_RX_ERROR 0x00000020\n\t#define DCBX_APP_RX_ERROR 0x00000040\n\t#define DCBX_ETS_REM_WILLING 0x00000100\n\t#define DCBX_PFC_REM_WILLING 0x00000200\n\t#define DCBX_APP_REM_WILLING 0x00000400\n\t#define DCBX_REMOTE_ETS_RECO_VALID 0x00001000\n\t#define DCBX_REMOTE_MIB_VALID 0x00002000\n\tstruct dcbx_features features;\n\tuint32_t suffix_seq_num;\n};\n\n/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */\nstruct lldp_local_mib {\n\tuint32_t prefix_seq_num;\n\t/* Indicates if there is mismatch with negotiation results. */\n\tuint32_t error;\n\t#define DCBX_LOCAL_ETS_ERROR 0x00000001\n\t#define DCBX_LOCAL_PFC_ERROR 0x00000002\n\t#define DCBX_LOCAL_APP_ERROR 0x00000004\n\t#define DCBX_LOCAL_PFC_MISMATCH 0x00000010\n\t#define DCBX_LOCAL_APP_MISMATCH 0x00000020\n\t#define DCBX_REMOTE_MIB_ERROR 0x00000040\n\t#define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080\n\t#define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100\n\t#define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200\n\tstruct dcbx_features features;\n\tuint32_t suffix_seq_num;\n};\n\nstruct lldp_local_mib_ext {\n\tuint32_t prefix_seq_num;\n\t/* APP TLV extension - 16 more entries for negotiation results*/\n\tstruct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL];\n\tuint32_t suffix_seq_num;\n};\n/***END OF DCBX STRUCTURES DECLARATIONS***/\n\n/***********************************************************/\n/* Elink section */\n/***********************************************************/\n#define SHMEM_LINK_CONFIG_SIZE 2\nstruct shmem_lfa {\n\tuint32_t req_duplex;\n\t#define REQ_DUPLEX_PHY0_MASK 0x0000ffff\n\t#define REQ_DUPLEX_PHY0_SHIFT 0\n\t#define REQ_DUPLEX_PHY1_MASK 0xffff0000\n\t#define REQ_DUPLEX_PHY1_SHIFT 16\n\tuint32_t req_flow_ctrl;\n\t#define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff\n\t#define REQ_FLOW_CTRL_PHY0_SHIFT 0\n\t#define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000\n\t#define REQ_FLOW_CTRL_PHY1_SHIFT 16\n\tuint32_t req_line_speed; /* Also determine AutoNeg */\n\t#define REQ_LINE_SPD_PHY0_MASK 0x0000ffff\n\t#define REQ_LINE_SPD_PHY0_SHIFT 0\n\t#define REQ_LINE_SPD_PHY1_MASK 0xffff0000\n\t#define REQ_LINE_SPD_PHY1_SHIFT 16\n\tuint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];\n\tuint32_t additional_config;\n\t#define REQ_FC_AUTO_ADV_MASK 0x0000ffff\n\t#define REQ_FC_AUTO_ADV0_SHIFT 0\n\t#define NO_LFA_DUE_TO_DCC_MASK 0x00010000\n\tuint32_t lfa_sts;\n\t#define LFA_LINK_FLAP_REASON_OFFSET\t\t0\n\t#define LFA_LINK_FLAP_REASON_MASK\t\t0x000000ff\n\t\t#define LFA_LINK_DOWN\t\t\t 0x1\n\t\t#define LFA_LOOPBACK_ENABLED\t\t0x2\n\t\t#define LFA_DUPLEX_MISMATCH\t\t 0x3\n\t\t#define LFA_MFW_IS_TOO_OLD\t\t 0x4\n\t\t#define LFA_LINK_SPEED_MISMATCH\t\t0x5\n\t\t#define LFA_FLOW_CTRL_MISMATCH\t\t0x6\n\t\t#define LFA_SPEED_CAP_MISMATCH\t\t0x7\n\t\t#define LFA_DCC_LFA_DISABLED\t\t0x8\n\t\t#define LFA_EEE_MISMATCH\t\t0x9\n\n\t#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET\t8\n\t#define LINK_FLAP_AVOIDANCE_COUNT_MASK\t\t0x0000ff00\n\n\t#define LINK_FLAP_COUNT_OFFSET\t\t\t16\n\t#define LINK_FLAP_COUNT_MASK\t\t\t0x00ff0000\n\n\t#define LFA_FLAGS_MASK\t\t\t\t0xff000000\n\t#define SHMEM_LFA_DONT_CLEAR_STAT\t\t(1<<24)\n\n};\n\nstruct shmem2_region {\n\n\tuint32_t size;\t\t\t\t\t/* 0x0000 */\n\n\tuint32_t dcc_support;\t\t\t\t/* 0x0004 */\n\t#define SHMEM_DCC_SUPPORT_NONE 0x00000000\n\t#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001\n\t#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004\n\t#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008\n\t#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040\n\t#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080\n\n\tuint32_t ext_phy_fw_version2[PORT_MAX];\t\t/* 0x0008 */\n\t/*\n\t * For backwards compatibility, if the mf_cfg_addr does not exist\n\t * (the size filed is smaller than 0xc) the mf_cfg resides at the\n\t * end of struct shmem_region\n\t */\n\tuint32_t mf_cfg_addr;\t\t\t\t/* 0x0010 */\n\t#define SHMEM_MF_CFG_ADDR_NONE 0x00000000\n\n\tstruct fw_flr_mb flr_mb;\t\t\t/* 0x0014 */\n\tuint32_t dcbx_lldp_params_offset;\t\t\t/* 0x0028 */\n\t#define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000\n\tuint32_t dcbx_neg_res_offset;\t\t\t/* 0x002c */\n\t#define SHMEM_DCBX_NEG_RES_NONE\t\t\t0x00000000\n\tuint32_t dcbx_remote_mib_offset;\t\t\t/* 0x0030 */\n\t#define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000\n\t/*\n\t * The other shmemX_base_addr holds the other path's shmem address\n\t * required for example in case of common phy init, or for path1 to know\n\t * the address of mcp debug trace which is located in offset from shmem\n\t * of path0\n\t */\n\tuint32_t other_shmem_base_addr;\t\t\t/* 0x0034 */\n\tuint32_t other_shmem2_base_addr;\t\t\t/* 0x0038 */\n\t/*\n\t * mcp_vf_disabled is set by the MCP to indicate the driver about VFs\n\t * which were disabled/flred\n\t */\n\tuint32_t mcp_vf_disabled[E2_VF_MAX / 32];\t\t/* 0x003c */\n\n\t/*\n\t * drv_ack_vf_disabled is set by the PF driver to ack handled disabled\n\t * VFs\n\t */\n\tuint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */\n\n\tuint32_t dcbx_lldp_dcbx_stat_offset;\t\t\t/* 0x0064 */\n\t#define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000\n\n\t/*\n\t * edebug_driver_if field is used to transfer messages between edebug\n\t * app to the driver through shmem2.\n\t *\n\t * message format:\n\t * bits 0-2 - function number / instance of driver to perform request\n\t * bits 3-5 - op code / is_ack?\n\t * bits 6-63 - data\n\t */\n\tuint32_t edebug_driver_if[2];\t\t\t/* 0x0068 */\n\t#define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1\n\t#define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2\n\t#define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3\n\n\tuint32_t nvm_retain_bitmap_addr;\t\t\t/* 0x0070 */\n\n\t/* afex support of that driver */\n\tuint32_t afex_driver_support;\t\t\t/* 0x0074 */\n\t#define SHMEM_AFEX_VERSION_MASK 0x100f\n\t#define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001\n\t#define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000\n\n\t/* driver receives addr in scratchpad to which it should respond */\n\tuint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX];\n\n\t/*\n\t * generic params from MCP to driver (value depends on the msg sent\n\t * to driver\n\t */\n\tuint32_t afex_param1_to_driver[E2_FUNC_MAX];\t\t/* 0x0088 */\n\tuint32_t afex_param2_to_driver[E2_FUNC_MAX];\t\t/* 0x0098 */\n\n\tuint32_t swim_base_addr;\t\t\t\t/* 0x0108 */\n\tuint32_t swim_funcs;\n\tuint32_t swim_main_cb;\n\n\t/*\n\t * bitmap notifying which VIF profiles stored in nvram are enabled by\n\t * switch\n\t */\n\tuint32_t afex_profiles_enabled[2];\n\n\t/* generic flags controlled by the driver */\n\tuint32_t drv_flags;\n\t#define DRV_FLAGS_DCB_CONFIGURED\t\t0x0\n\t#define DRV_FLAGS_DCB_CONFIGURATION_ABORTED\t0x1\n\t#define DRV_FLAGS_DCB_MFW_CONFIGURED\t0x2\n\n #define DRV_FLAGS_PORT_MASK\t((1 << DRV_FLAGS_DCB_CONFIGURED) | \\\n\t\t\t(1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \\\n\t\t\t(1 << DRV_FLAGS_DCB_MFW_CONFIGURED))\n\t/* Port offset*/\n\t#define DRV_FLAGS_P0_OFFSET\t\t0\n\t#define DRV_FLAGS_P1_OFFSET\t\t16\n\t#define DRV_FLAGS_GET_PORT_OFFSET(_port)\t((0 == _port) ? \\\n\t\t\t\t\t\tDRV_FLAGS_P0_OFFSET : \\\n\t\t\t\t\t\tDRV_FLAGS_P1_OFFSET)\n\n\t#define DRV_FLAGS_GET_PORT_MASK(_port)\t(DRV_FLAGS_PORT_MASK << \\\n\tDRV_FLAGS_GET_PORT_OFFSET(_port))\n\n\t#define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port)\t(1 << ( \\\n\t(_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))\n\n\t/* pointer to extended dev_info shared data copied from nvm image */\n\tuint32_t extended_dev_info_shared_addr;\n\tuint32_t ncsi_oem_data_addr;\n\n\tuint32_t sensor_data_addr;\n\tuint32_t buffer_block_addr;\n\tuint32_t sensor_data_req_update_interval;\n\tuint32_t temperature_in_half_celsius;\n\tuint32_t glob_struct_in_host;\n\n\tuint32_t dcbx_neg_res_ext_offset;\n\t#define SHMEM_DCBX_NEG_RES_EXT_NONE\t\t\t0x00000000\n\n\tuint32_t drv_capabilities_flag[E2_FUNC_MAX];\n\t#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001\n\t#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002\n\t#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004\n\t#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008\n\n\tuint32_t extended_dev_info_shared_cfg_size;\n\n\tuint32_t dcbx_en[PORT_MAX];\n\n\t/* The offset points to the multi threaded meta structure */\n\tuint32_t multi_thread_data_offset;\n\n\t/* address of DMAable host address holding values from the drivers */\n\tuint32_t drv_info_host_addr_lo;\n\tuint32_t drv_info_host_addr_hi;\n\n\t/* general values written by the MFW (such as current version) */\n\tuint32_t drv_info_control;\n\t#define DRV_INFO_CONTROL_VER_MASK 0x000000ff\n\t#define DRV_INFO_CONTROL_VER_SHIFT 0\n\t#define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00\n\t#define DRV_INFO_CONTROL_OP_CODE_SHIFT 8\n\tuint32_t ibft_host_addr; /* initialized by option ROM */\n\n\tstruct eee_remote_vals eee_remote_vals[PORT_MAX];\n\tuint32_t pf_allocation[E2_FUNC_MAX];\n\t#define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */\n\t#define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0\n\n\t/* the status of EEE auto-negotiation\n\t * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.\n\t * bits 19:16 the supported modes for EEE.\n\t * bits 23:20 the speeds advertised for EEE.\n\t * bits 27:24 the speeds the Link partner advertised for EEE.\n\t * The supported/adv. modes in bits 27:19 originate from the\n\t * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).\n\t * bit 28 when 1'b1 EEE was requested.\n\t * bit 29 when 1'b1 tx lpi was requested.\n\t * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff\n\t * 30:29 are 2'b11.\n\t * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as\n\t * value. When 1'b1 those bits contains a value times 16 microseconds.\n\t */\n\tuint32_t eee_status[PORT_MAX];\n\t#define SHMEM_EEE_TIMER_MASK\t\t 0x0000ffff\n\t#define SHMEM_EEE_SUPPORTED_MASK\t 0x000f0000\n\t#define SHMEM_EEE_SUPPORTED_SHIFT\t 16\n\t#define SHMEM_EEE_ADV_STATUS_MASK\t 0x00f00000\n\t\t#define SHMEM_EEE_100M_ADV\t (1<<0)\n\t\t#define SHMEM_EEE_1G_ADV\t (1<<1)\n\t\t#define SHMEM_EEE_10G_ADV\t (1<<2)\n\t#define SHMEM_EEE_ADV_STATUS_SHIFT\t 20\n\t#define\tSHMEM_EEE_LP_ADV_STATUS_MASK\t 0x0f000000\n\t#define SHMEM_EEE_LP_ADV_STATUS_SHIFT\t 24\n\t#define SHMEM_EEE_REQUESTED_BIT\t\t 0x10000000\n\t#define SHMEM_EEE_LPI_REQUESTED_BIT\t 0x20000000\n\t#define SHMEM_EEE_ACTIVE_BIT\t\t 0x40000000\n\t#define SHMEM_EEE_TIME_OUTPUT_BIT\t 0x80000000\n\n\tuint32_t sizeof_port_stats;\n\n\t/* Link Flap Avoidance */\n\tuint32_t lfa_host_addr[PORT_MAX];\n\n /* External PHY temperature in deg C. */\n\tuint32_t extphy_temps_in_celsius;\n\t#define EXTPHY1_TEMP_MASK 0x0000ffff\n\t#define EXTPHY1_TEMP_SHIFT 0\n\n\tuint32_t ocdata_info_addr;\t\t\t/* Offset 0x148 */\n\tuint32_t drv_func_info_addr;\t\t\t/* Offset 0x14C */\n\tuint32_t drv_func_info_size;\t\t\t/* Offset 0x150 */\n\tuint32_t link_attr_sync[PORT_MAX];\t\t/* Offset 0x154 */\n\t#define LINK_ATTR_SYNC_KR2_ENABLE\t(1<<0)\n};\n\n\nstruct emac_stats {\n\tuint32_t rx_stat_ifhcinoctets;\n\tuint32_t rx_stat_ifhcinbadoctets;\n\tuint32_t rx_stat_etherstatsfragments;\n\tuint32_t rx_stat_ifhcinucastpkts;\n\tuint32_t rx_stat_ifhcinmulticastpkts;\n\tuint32_t rx_stat_ifhcinbroadcastpkts;\n\tuint32_t rx_stat_dot3statsfcserrors;\n\tuint32_t rx_stat_dot3statsalignmenterrors;\n\tuint32_t rx_stat_dot3statscarriersenseerrors;\n\tuint32_t rx_stat_xonpauseframesreceived;\n\tuint32_t rx_stat_xoffpauseframesreceived;\n\tuint32_t rx_stat_maccontrolframesreceived;\n\tuint32_t rx_stat_xoffstateentered;\n\tuint32_t rx_stat_dot3statsframestoolong;\n\tuint32_t rx_stat_etherstatsjabbers;\n\tuint32_t rx_stat_etherstatsundersizepkts;\n\tuint32_t rx_stat_etherstatspkts64octets;\n\tuint32_t rx_stat_etherstatspkts65octetsto127octets;\n\tuint32_t rx_stat_etherstatspkts128octetsto255octets;\n\tuint32_t rx_stat_etherstatspkts256octetsto511octets;\n\tuint32_t rx_stat_etherstatspkts512octetsto1023octets;\n\tuint32_t rx_stat_etherstatspkts1024octetsto1522octets;\n\tuint32_t rx_stat_etherstatspktsover1522octets;\n\n\tuint32_t rx_stat_falsecarriererrors;\n\n\tuint32_t tx_stat_ifhcoutoctets;\n\tuint32_t tx_stat_ifhcoutbadoctets;\n\tuint32_t tx_stat_etherstatscollisions;\n\tuint32_t tx_stat_outxonsent;\n\tuint32_t tx_stat_outxoffsent;\n\tuint32_t tx_stat_flowcontroldone;\n\tuint32_t tx_stat_dot3statssinglecollisionframes;\n\tuint32_t tx_stat_dot3statsmultiplecollisionframes;\n\tuint32_t tx_stat_dot3statsdeferredtransmissions;\n\tuint32_t tx_stat_dot3statsexcessivecollisions;\n\tuint32_t tx_stat_dot3statslatecollisions;\n\tuint32_t tx_stat_ifhcoutucastpkts;\n\tuint32_t tx_stat_ifhcoutmulticastpkts;\n\tuint32_t tx_stat_ifhcoutbroadcastpkts;\n\tuint32_t tx_stat_etherstatspkts64octets;\n\tuint32_t tx_stat_etherstatspkts65octetsto127octets;\n\tuint32_t tx_stat_etherstatspkts128octetsto255octets;\n\tuint32_t tx_stat_etherstatspkts256octetsto511octets;\n\tuint32_t tx_stat_etherstatspkts512octetsto1023octets;\n\tuint32_t tx_stat_etherstatspkts1024octetsto1522octets;\n\tuint32_t tx_stat_etherstatspktsover1522octets;\n\tuint32_t tx_stat_dot3statsinternalmactransmiterrors;\n};\n\n\nstruct bmac1_stats {\n\tuint32_t\ttx_stat_gtpkt_lo;\n\tuint32_t\ttx_stat_gtpkt_hi;\n\tuint32_t\ttx_stat_gtxpf_lo;\n\tuint32_t\ttx_stat_gtxpf_hi;\n\tuint32_t\ttx_stat_gtfcs_lo;\n\tuint32_t\ttx_stat_gtfcs_hi;\n\tuint32_t\ttx_stat_gtmca_lo;\n\tuint32_t\ttx_stat_gtmca_hi;\n\tuint32_t\ttx_stat_gtbca_lo;\n\tuint32_t\ttx_stat_gtbca_hi;\n\tuint32_t\ttx_stat_gtfrg_lo;\n\tuint32_t\ttx_stat_gtfrg_hi;\n\tuint32_t\ttx_stat_gtovr_lo;\n\tuint32_t\ttx_stat_gtovr_hi;\n\tuint32_t\ttx_stat_gt64_lo;\n\tuint32_t\ttx_stat_gt64_hi;\n\tuint32_t\ttx_stat_gt127_lo;\n\tuint32_t\ttx_stat_gt127_hi;\n\tuint32_t\ttx_stat_gt255_lo;\n\tuint32_t\ttx_stat_gt255_hi;\n\tuint32_t\ttx_stat_gt511_lo;\n\tuint32_t\ttx_stat_gt511_hi;\n\tuint32_t\ttx_stat_gt1023_lo;\n\tuint32_t\ttx_stat_gt1023_hi;\n\tuint32_t\ttx_stat_gt1518_lo;\n\tuint32_t\ttx_stat_gt1518_hi;\n\tuint32_t\ttx_stat_gt2047_lo;\n\tuint32_t\ttx_stat_gt2047_hi;\n\tuint32_t\ttx_stat_gt4095_lo;\n\tuint32_t\ttx_stat_gt4095_hi;\n\tuint32_t\ttx_stat_gt9216_lo;\n\tuint32_t\ttx_stat_gt9216_hi;\n\tuint32_t\ttx_stat_gt16383_lo;\n\tuint32_t\ttx_stat_gt16383_hi;\n\tuint32_t\ttx_stat_gtmax_lo;\n\tuint32_t\ttx_stat_gtmax_hi;\n\tuint32_t\ttx_stat_gtufl_lo;\n\tuint32_t\ttx_stat_gtufl_hi;\n\tuint32_t\ttx_stat_gterr_lo;\n\tuint32_t\ttx_stat_gterr_hi;\n\tuint32_t\ttx_stat_gtbyt_lo;\n\tuint32_t\ttx_stat_gtbyt_hi;\n\n\tuint32_t\trx_stat_gr64_lo;\n\tuint32_t\trx_stat_gr64_hi;\n\tuint32_t\trx_stat_gr127_lo;\n\tuint32_t\trx_stat_gr127_hi;\n\tuint32_t\trx_stat_gr255_lo;\n\tuint32_t\trx_stat_gr255_hi;\n\tuint32_t\trx_stat_gr511_lo;\n\tuint32_t\trx_stat_gr511_hi;\n\tuint32_t\trx_stat_gr1023_lo;\n\tuint32_t\trx_stat_gr1023_hi;\n\tuint32_t\trx_stat_gr1518_lo;\n\tuint32_t\trx_stat_gr1518_hi;\n\tuint32_t\trx_stat_gr2047_lo;\n\tuint32_t\trx_stat_gr2047_hi;\n\tuint32_t\trx_stat_gr4095_lo;\n\tuint32_t\trx_stat_gr4095_hi;\n\tuint32_t\trx_stat_gr9216_lo;\n\tuint32_t\trx_stat_gr9216_hi;\n\tuint32_t\trx_stat_gr16383_lo;\n\tuint32_t\trx_stat_gr16383_hi;\n\tuint32_t\trx_stat_grmax_lo;\n\tuint32_t\trx_stat_grmax_hi;\n\tuint32_t\trx_stat_grpkt_lo;\n\tuint32_t\trx_stat_grpkt_hi;\n\tuint32_t\trx_stat_grfcs_lo;\n\tuint32_t\trx_stat_grfcs_hi;\n\tuint32_t\trx_stat_grmca_lo;\n\tuint32_t\trx_stat_grmca_hi;\n\tuint32_t\trx_stat_grbca_lo;\n\tuint32_t\trx_stat_grbca_hi;\n\tuint32_t\trx_stat_grxcf_lo;\n\tuint32_t\trx_stat_grxcf_hi;\n\tuint32_t\trx_stat_grxpf_lo;\n\tuint32_t\trx_stat_grxpf_hi;\n\tuint32_t\trx_stat_grxuo_lo;\n\tuint32_t\trx_stat_grxuo_hi;\n\tuint32_t\trx_stat_grjbr_lo;\n\tuint32_t\trx_stat_grjbr_hi;\n\tuint32_t\trx_stat_grovr_lo;\n\tuint32_t\trx_stat_grovr_hi;\n\tuint32_t\trx_stat_grflr_lo;\n\tuint32_t\trx_stat_grflr_hi;\n\tuint32_t\trx_stat_grmeg_lo;\n\tuint32_t\trx_stat_grmeg_hi;\n\tuint32_t\trx_stat_grmeb_lo;\n\tuint32_t\trx_stat_grmeb_hi;\n\tuint32_t\trx_stat_grbyt_lo;\n\tuint32_t\trx_stat_grbyt_hi;\n\tuint32_t\trx_stat_grund_lo;\n\tuint32_t\trx_stat_grund_hi;\n\tuint32_t\trx_stat_grfrg_lo;\n\tuint32_t\trx_stat_grfrg_hi;\n\tuint32_t\trx_stat_grerb_lo;\n\tuint32_t\trx_stat_grerb_hi;\n\tuint32_t\trx_stat_grfre_lo;\n\tuint32_t\trx_stat_grfre_hi;\n\tuint32_t\trx_stat_gripj_lo;\n\tuint32_t\trx_stat_gripj_hi;\n};\n\nstruct bmac2_stats {\n\tuint32_t\ttx_stat_gtpk_lo; /* gtpok */\n\tuint32_t\ttx_stat_gtpk_hi; /* gtpok */\n\tuint32_t\ttx_stat_gtxpf_lo; /* gtpf */\n\tuint32_t\ttx_stat_gtxpf_hi; /* gtpf */\n\tuint32_t\ttx_stat_gtpp_lo; /* NEW BMAC2 */\n\tuint32_t\ttx_stat_gtpp_hi; /* NEW BMAC2 */\n\tuint32_t\ttx_stat_gtfcs_lo;\n\tuint32_t\ttx_stat_gtfcs_hi;\n\tuint32_t\ttx_stat_gtuca_lo; /* NEW BMAC2 */\n\tuint32_t\ttx_stat_gtuca_hi; /* NEW BMAC2 */\n\tuint32_t\ttx_stat_gtmca_lo;\n\tuint32_t\ttx_stat_gtmca_hi;\n\tuint32_t\ttx_stat_gtbca_lo;\n\tuint32_t\ttx_stat_gtbca_hi;\n\tuint32_t\ttx_stat_gtovr_lo;\n\tuint32_t\ttx_stat_gtovr_hi;\n\tuint32_t\ttx_stat_gtfrg_lo;\n\tuint32_t\ttx_stat_gtfrg_hi;\n\tuint32_t\ttx_stat_gtpkt1_lo; /* gtpkt */\n\tuint32_t\ttx_stat_gtpkt1_hi; /* gtpkt */\n\tuint32_t\ttx_stat_gt64_lo;\n\tuint32_t\ttx_stat_gt64_hi;\n\tuint32_t\ttx_stat_gt127_lo;\n\tuint32_t\ttx_stat_gt127_hi;\n\tuint32_t\ttx_stat_gt255_lo;\n\tuint32_t\ttx_stat_gt255_hi;\n\tuint32_t\ttx_stat_gt511_lo;\n\tuint32_t\ttx_stat_gt511_hi;\n\tuint32_t\ttx_stat_gt1023_lo;\n\tuint32_t\ttx_stat_gt1023_hi;\n\tuint32_t\ttx_stat_gt1518_lo;\n\tuint32_t\ttx_stat_gt1518_hi;\n\tuint32_t\ttx_stat_gt2047_lo;\n\tuint32_t\ttx_stat_gt2047_hi;\n\tuint32_t\ttx_stat_gt4095_lo;\n\tuint32_t\ttx_stat_gt4095_hi;\n\tuint32_t\ttx_stat_gt9216_lo;\n\tuint32_t\ttx_stat_gt9216_hi;\n\tuint32_t\ttx_stat_gt16383_lo;\n\tuint32_t\ttx_stat_gt16383_hi;\n\tuint32_t\ttx_stat_gtmax_lo;\n\tuint32_t\ttx_stat_gtmax_hi;\n\tuint32_t\ttx_stat_gtufl_lo;\n\tuint32_t\ttx_stat_gtufl_hi;\n\tuint32_t\ttx_stat_gterr_lo;\n\tuint32_t\ttx_stat_gterr_hi;\n\tuint32_t\ttx_stat_gtbyt_lo;\n\tuint32_t\ttx_stat_gtbyt_hi;\n\n\tuint32_t\trx_stat_gr64_lo;\n\tuint32_t\trx_stat_gr64_hi;\n\tuint32_t\trx_stat_gr127_lo;\n\tuint32_t\trx_stat_gr127_hi;\n\tuint32_t\trx_stat_gr255_lo;\n\tuint32_t\trx_stat_gr255_hi;\n\tuint32_t\trx_stat_gr511_lo;\n\tuint32_t\trx_stat_gr511_hi;\n\tuint32_t\trx_stat_gr1023_lo;\n\tuint32_t\trx_stat_gr1023_hi;\n\tuint32_t\trx_stat_gr1518_lo;\n\tuint32_t\trx_stat_gr1518_hi;\n\tuint32_t\trx_stat_gr2047_lo;\n\tuint32_t\trx_stat_gr2047_hi;\n\tuint32_t\trx_stat_gr4095_lo;\n\tuint32_t\trx_stat_gr4095_hi;\n\tuint32_t\trx_stat_gr9216_lo;\n\tuint32_t\trx_stat_gr9216_hi;\n\tuint32_t\trx_stat_gr16383_lo;\n\tuint32_t\trx_stat_gr16383_hi;\n\tuint32_t\trx_stat_grmax_lo;\n\tuint32_t\trx_stat_grmax_hi;\n\tuint32_t\trx_stat_grpkt_lo;\n\tuint32_t\trx_stat_grpkt_hi;\n\tuint32_t\trx_stat_grfcs_lo;\n\tuint32_t\trx_stat_grfcs_hi;\n\tuint32_t\trx_stat_gruca_lo;\n\tuint32_t\trx_stat_gruca_hi;\n\tuint32_t\trx_stat_grmca_lo;\n\tuint32_t\trx_stat_grmca_hi;\n\tuint32_t\trx_stat_grbca_lo;\n\tuint32_t\trx_stat_grbca_hi;\n\tuint32_t\trx_stat_grxpf_lo; /* grpf */\n\tuint32_t\trx_stat_grxpf_hi; /* grpf */\n\tuint32_t\trx_stat_grpp_lo;\n\tuint32_t\trx_stat_grpp_hi;\n\tuint32_t\trx_stat_grxuo_lo; /* gruo */\n\tuint32_t\trx_stat_grxuo_hi; /* gruo */\n\tuint32_t\trx_stat_grjbr_lo;\n\tuint32_t\trx_stat_grjbr_hi;\n\tuint32_t\trx_stat_grovr_lo;\n\tuint32_t\trx_stat_grovr_hi;\n\tuint32_t\trx_stat_grxcf_lo; /* grcf */\n\tuint32_t\trx_stat_grxcf_hi; /* grcf */\n\tuint32_t\trx_stat_grflr_lo;\n\tuint32_t\trx_stat_grflr_hi;\n\tuint32_t\trx_stat_grpok_lo;\n\tuint32_t\trx_stat_grpok_hi;\n\tuint32_t\trx_stat_grmeg_lo;\n\tuint32_t\trx_stat_grmeg_hi;\n\tuint32_t\trx_stat_grmeb_lo;\n\tuint32_t\trx_stat_grmeb_hi;\n\tuint32_t\trx_stat_grbyt_lo;\n\tuint32_t\trx_stat_grbyt_hi;\n\tuint32_t\trx_stat_grund_lo;\n\tuint32_t\trx_stat_grund_hi;\n\tuint32_t\trx_stat_grfrg_lo;\n\tuint32_t\trx_stat_grfrg_hi;\n\tuint32_t\trx_stat_grerb_lo; /* grerrbyt */\n\tuint32_t\trx_stat_grerb_hi; /* grerrbyt */\n\tuint32_t\trx_stat_grfre_lo; /* grfrerr */\n\tuint32_t\trx_stat_grfre_hi; /* grfrerr */\n\tuint32_t\trx_stat_gripj_lo;\n\tuint32_t\trx_stat_gripj_hi;\n};\n\nstruct mstat_stats {\n\tstruct {\n\t\t/* OTE MSTAT on E3 has a bug where this register's contents are\n\t\t * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp\n\t\t */\n\t\tuint32_t tx_gtxpok_lo;\n\t\tuint32_t tx_gtxpok_hi;\n\t\tuint32_t tx_gtxpf_lo;\n\t\tuint32_t tx_gtxpf_hi;\n\t\tuint32_t tx_gtxpp_lo;\n\t\tuint32_t tx_gtxpp_hi;\n\t\tuint32_t tx_gtfcs_lo;\n\t\tuint32_t tx_gtfcs_hi;\n\t\tuint32_t tx_gtuca_lo;\n\t\tuint32_t tx_gtuca_hi;\n\t\tuint32_t tx_gtmca_lo;\n\t\tuint32_t tx_gtmca_hi;\n\t\tuint32_t tx_gtgca_lo;\n\t\tuint32_t tx_gtgca_hi;\n\t\tuint32_t tx_gtpkt_lo;\n\t\tuint32_t tx_gtpkt_hi;\n\t\tuint32_t tx_gt64_lo;\n\t\tuint32_t tx_gt64_hi;\n\t\tuint32_t tx_gt127_lo;\n\t\tuint32_t tx_gt127_hi;\n\t\tuint32_t tx_gt255_lo;\n\t\tuint32_t tx_gt255_hi;\n\t\tuint32_t tx_gt511_lo;\n\t\tuint32_t tx_gt511_hi;\n\t\tuint32_t tx_gt1023_lo;\n\t\tuint32_t tx_gt1023_hi;\n\t\tuint32_t tx_gt1518_lo;\n\t\tuint32_t tx_gt1518_hi;\n\t\tuint32_t tx_gt2047_lo;\n\t\tuint32_t tx_gt2047_hi;\n\t\tuint32_t tx_gt4095_lo;\n\t\tuint32_t tx_gt4095_hi;\n\t\tuint32_t tx_gt9216_lo;\n\t\tuint32_t tx_gt9216_hi;\n\t\tuint32_t tx_gt16383_lo;\n\t\tuint32_t tx_gt16383_hi;\n\t\tuint32_t tx_gtufl_lo;\n\t\tuint32_t tx_gtufl_hi;\n\t\tuint32_t tx_gterr_lo;\n\t\tuint32_t tx_gterr_hi;\n\t\tuint32_t tx_gtbyt_lo;\n\t\tuint32_t tx_gtbyt_hi;\n\t\tuint32_t tx_collisions_lo;\n\t\tuint32_t tx_collisions_hi;\n\t\tuint32_t tx_singlecollision_lo;\n\t\tuint32_t tx_singlecollision_hi;\n\t\tuint32_t tx_multiplecollisions_lo;\n\t\tuint32_t tx_multiplecollisions_hi;\n\t\tuint32_t tx_deferred_lo;\n\t\tuint32_t tx_deferred_hi;\n\t\tuint32_t tx_excessivecollisions_lo;\n\t\tuint32_t tx_excessivecollisions_hi;\n\t\tuint32_t tx_latecollisions_lo;\n\t\tuint32_t tx_latecollisions_hi;\n\t} stats_tx;\n\n\tstruct {\n\t\tuint32_t rx_gr64_lo;\n\t\tuint32_t rx_gr64_hi;\n\t\tuint32_t rx_gr127_lo;\n\t\tuint32_t rx_gr127_hi;\n\t\tuint32_t rx_gr255_lo;\n\t\tuint32_t rx_gr255_hi;\n\t\tuint32_t rx_gr511_lo;\n\t\tuint32_t rx_gr511_hi;\n\t\tuint32_t rx_gr1023_lo;\n\t\tuint32_t rx_gr1023_hi;\n\t\tuint32_t rx_gr1518_lo;\n\t\tuint32_t rx_gr1518_hi;\n\t\tuint32_t rx_gr2047_lo;\n\t\tuint32_t rx_gr2047_hi;\n\t\tuint32_t rx_gr4095_lo;\n\t\tuint32_t rx_gr4095_hi;\n\t\tuint32_t rx_gr9216_lo;\n\t\tuint32_t rx_gr9216_hi;\n\t\tuint32_t rx_gr16383_lo;\n\t\tuint32_t rx_gr16383_hi;\n\t\tuint32_t rx_grpkt_lo;\n\t\tuint32_t rx_grpkt_hi;\n\t\tuint32_t rx_grfcs_lo;\n\t\tuint32_t rx_grfcs_hi;\n\t\tuint32_t rx_gruca_lo;\n\t\tuint32_t rx_gruca_hi;\n\t\tuint32_t rx_grmca_lo;\n\t\tuint32_t rx_grmca_hi;\n\t\tuint32_t rx_grbca_lo;\n\t\tuint32_t rx_grbca_hi;\n\t\tuint32_t rx_grxpf_lo;\n\t\tuint32_t rx_grxpf_hi;\n\t\tuint32_t rx_grxpp_lo;\n\t\tuint32_t rx_grxpp_hi;\n\t\tuint32_t rx_grxuo_lo;\n\t\tuint32_t rx_grxuo_hi;\n\t\tuint32_t rx_grovr_lo;\n\t\tuint32_t rx_grovr_hi;\n\t\tuint32_t rx_grxcf_lo;\n\t\tuint32_t rx_grxcf_hi;\n\t\tuint32_t rx_grflr_lo;\n\t\tuint32_t rx_grflr_hi;\n\t\tuint32_t rx_grpok_lo;\n\t\tuint32_t rx_grpok_hi;\n\t\tuint32_t rx_grbyt_lo;\n\t\tuint32_t rx_grbyt_hi;\n\t\tuint32_t rx_grund_lo;\n\t\tuint32_t rx_grund_hi;\n\t\tuint32_t rx_grfrg_lo;\n\t\tuint32_t rx_grfrg_hi;\n\t\tuint32_t rx_grerb_lo;\n\t\tuint32_t rx_grerb_hi;\n\t\tuint32_t rx_grfre_lo;\n\t\tuint32_t rx_grfre_hi;\n\n\t\tuint32_t rx_alignmenterrors_lo;\n\t\tuint32_t rx_alignmenterrors_hi;\n\t\tuint32_t rx_falsecarrier_lo;\n\t\tuint32_t rx_falsecarrier_hi;\n\t\tuint32_t rx_llfcmsgcnt_lo;\n\t\tuint32_t rx_llfcmsgcnt_hi;\n\t} stats_rx;\n};\n\nunion mac_stats {\n\tstruct emac_stats\temac_stats;\n\tstruct bmac1_stats\tbmac1_stats;\n\tstruct bmac2_stats\tbmac2_stats;\n\tstruct mstat_stats\tmstat_stats;\n};\n\n\nstruct mac_stx {\n\t/* in_bad_octets */\n\tuint32_t rx_stat_ifhcinbadoctets_hi;\n\tuint32_t rx_stat_ifhcinbadoctets_lo;\n\n\t/* out_bad_octets */\n\tuint32_t tx_stat_ifhcoutbadoctets_hi;\n\tuint32_t tx_stat_ifhcoutbadoctets_lo;\n\n\t/* crc_receive_errors */\n\tuint32_t rx_stat_dot3statsfcserrors_hi;\n\tuint32_t rx_stat_dot3statsfcserrors_lo;\n\t/* alignment_errors */\n\tuint32_t rx_stat_dot3statsalignmenterrors_hi;\n\tuint32_t rx_stat_dot3statsalignmenterrors_lo;\n\t/* carrier_sense_errors */\n\tuint32_t rx_stat_dot3statscarriersenseerrors_hi;\n\tuint32_t rx_stat_dot3statscarriersenseerrors_lo;\n\t/* false_carrier_detections */\n\tuint32_t rx_stat_falsecarriererrors_hi;\n\tuint32_t rx_stat_falsecarriererrors_lo;\n\n\t/* runt_packets_received */\n\tuint32_t rx_stat_etherstatsundersizepkts_hi;\n\tuint32_t rx_stat_etherstatsundersizepkts_lo;\n\t/* jabber_packets_received */\n\tuint32_t rx_stat_dot3statsframestoolong_hi;\n\tuint32_t rx_stat_dot3statsframestoolong_lo;\n\n\t/* error_runt_packets_received */\n\tuint32_t rx_stat_etherstatsfragments_hi;\n\tuint32_t rx_stat_etherstatsfragments_lo;\n\t/* error_jabber_packets_received */\n\tuint32_t rx_stat_etherstatsjabbers_hi;\n\tuint32_t rx_stat_etherstatsjabbers_lo;\n\n\t/* control_frames_received */\n\tuint32_t rx_stat_maccontrolframesreceived_hi;\n\tuint32_t rx_stat_maccontrolframesreceived_lo;\n\tuint32_t rx_stat_mac_xpf_hi;\n\tuint32_t rx_stat_mac_xpf_lo;\n\tuint32_t rx_stat_mac_xcf_hi;\n\tuint32_t rx_stat_mac_xcf_lo;\n\n\t/* xoff_state_entered */\n\tuint32_t rx_stat_xoffstateentered_hi;\n\tuint32_t rx_stat_xoffstateentered_lo;\n\t/* pause_xon_frames_received */\n\tuint32_t rx_stat_xonpauseframesreceived_hi;\n\tuint32_t rx_stat_xonpauseframesreceived_lo;\n\t/* pause_xoff_frames_received */\n\tuint32_t rx_stat_xoffpauseframesreceived_hi;\n\tuint32_t rx_stat_xoffpauseframesreceived_lo;\n\t/* pause_xon_frames_transmitted */\n\tuint32_t tx_stat_outxonsent_hi;\n\tuint32_t tx_stat_outxonsent_lo;\n\t/* pause_xoff_frames_transmitted */\n\tuint32_t tx_stat_outxoffsent_hi;\n\tuint32_t tx_stat_outxoffsent_lo;\n\t/* flow_control_done */\n\tuint32_t tx_stat_flowcontroldone_hi;\n\tuint32_t tx_stat_flowcontroldone_lo;\n\n\t/* ether_stats_collisions */\n\tuint32_t tx_stat_etherstatscollisions_hi;\n\tuint32_t tx_stat_etherstatscollisions_lo;\n\t/* single_collision_transmit_frames */\n\tuint32_t tx_stat_dot3statssinglecollisionframes_hi;\n\tuint32_t tx_stat_dot3statssinglecollisionframes_lo;\n\t/* multiple_collision_transmit_frames */\n\tuint32_t tx_stat_dot3statsmultiplecollisionframes_hi;\n\tuint32_t tx_stat_dot3statsmultiplecollisionframes_lo;\n\t/* deferred_transmissions */\n\tuint32_t tx_stat_dot3statsdeferredtransmissions_hi;\n\tuint32_t tx_stat_dot3statsdeferredtransmissions_lo;\n\t/* excessive_collision_frames */\n\tuint32_t tx_stat_dot3statsexcessivecollisions_hi;\n\tuint32_t tx_stat_dot3statsexcessivecollisions_lo;\n\t/* late_collision_frames */\n\tuint32_t tx_stat_dot3statslatecollisions_hi;\n\tuint32_t tx_stat_dot3statslatecollisions_lo;\n\n\t/* frames_transmitted_64_bytes */\n\tuint32_t tx_stat_etherstatspkts64octets_hi;\n\tuint32_t tx_stat_etherstatspkts64octets_lo;\n\t/* frames_transmitted_65_127_bytes */\n\tuint32_t tx_stat_etherstatspkts65octetsto127octets_hi;\n\tuint32_t tx_stat_etherstatspkts65octetsto127octets_lo;\n\t/* frames_transmitted_128_255_bytes */\n\tuint32_t tx_stat_etherstatspkts128octetsto255octets_hi;\n\tuint32_t tx_stat_etherstatspkts128octetsto255octets_lo;\n\t/* frames_transmitted_256_511_bytes */\n\tuint32_t tx_stat_etherstatspkts256octetsto511octets_hi;\n\tuint32_t tx_stat_etherstatspkts256octetsto511octets_lo;\n\t/* frames_transmitted_512_1023_bytes */\n\tuint32_t tx_stat_etherstatspkts512octetsto1023octets_hi;\n\tuint32_t tx_stat_etherstatspkts512octetsto1023octets_lo;\n\t/* frames_transmitted_1024_1522_bytes */\n\tuint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi;\n\tuint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo;\n\t/* frames_transmitted_1523_9022_bytes */\n\tuint32_t tx_stat_etherstatspktsover1522octets_hi;\n\tuint32_t tx_stat_etherstatspktsover1522octets_lo;\n\tuint32_t tx_stat_mac_2047_hi;\n\tuint32_t tx_stat_mac_2047_lo;\n\tuint32_t tx_stat_mac_4095_hi;\n\tuint32_t tx_stat_mac_4095_lo;\n\tuint32_t tx_stat_mac_9216_hi;\n\tuint32_t tx_stat_mac_9216_lo;\n\tuint32_t tx_stat_mac_16383_hi;\n\tuint32_t tx_stat_mac_16383_lo;\n\n\t/* internal_mac_transmit_errors */\n\tuint32_t tx_stat_dot3statsinternalmactransmiterrors_hi;\n\tuint32_t tx_stat_dot3statsinternalmactransmiterrors_lo;\n\n\t/* if_out_discards */\n\tuint32_t tx_stat_mac_ufl_hi;\n\tuint32_t tx_stat_mac_ufl_lo;\n};\n\n\n#define MAC_STX_IDX_MAX 2\n\nstruct host_port_stats {\n\tuint32_t host_port_stats_counter;\n\n\tstruct mac_stx mac_stx[MAC_STX_IDX_MAX];\n\n\tuint32_t brb_drop_hi;\n\tuint32_t brb_drop_lo;\n\n\tuint32_t not_used; /* obsolete as of MFW 7.2.1 */\n\n\tuint32_t pfc_frames_tx_hi;\n\tuint32_t pfc_frames_tx_lo;\n\tuint32_t pfc_frames_rx_hi;\n\tuint32_t pfc_frames_rx_lo;\n\n\tuint32_t eee_lpi_count_hi;\n\tuint32_t eee_lpi_count_lo;\n};\n\n\nstruct host_func_stats {\n\tuint32_t host_func_stats_start;\n\n\tuint32_t total_bytes_received_hi;\n\tuint32_t total_bytes_received_lo;\n\n\tuint32_t total_bytes_transmitted_hi;\n\tuint32_t total_bytes_transmitted_lo;\n\n\tuint32_t total_unicast_packets_received_hi;\n\tuint32_t total_unicast_packets_received_lo;\n\n\tuint32_t total_multicast_packets_received_hi;\n\tuint32_t total_multicast_packets_received_lo;\n\n\tuint32_t total_broadcast_packets_received_hi;\n\tuint32_t total_broadcast_packets_received_lo;\n\n\tuint32_t total_unicast_packets_transmitted_hi;\n\tuint32_t total_unicast_packets_transmitted_lo;\n\n\tuint32_t total_multicast_packets_transmitted_hi;\n\tuint32_t total_multicast_packets_transmitted_lo;\n\n\tuint32_t total_broadcast_packets_transmitted_hi;\n\tuint32_t total_broadcast_packets_transmitted_lo;\n\n\tuint32_t valid_bytes_received_hi;\n\tuint32_t valid_bytes_received_lo;\n\n\tuint32_t host_func_stats_end;\n};\n\n/* VIC definitions */\n#define VICSTATST_UIF_INDEX 2\n\n/*\n * stats collected for afex.\n * NOTE: structure is exactly as expected to be received by the switch.\n * order must remain exactly as is unless protocol changes !\n */\nstruct afex_stats {\n\tuint32_t tx_unicast_frames_hi;\n\tuint32_t tx_unicast_frames_lo;\n\tuint32_t tx_unicast_bytes_hi;\n\tuint32_t tx_unicast_bytes_lo;\n\tuint32_t tx_multicast_frames_hi;\n\tuint32_t tx_multicast_frames_lo;\n\tuint32_t tx_multicast_bytes_hi;\n\tuint32_t tx_multicast_bytes_lo;\n\tuint32_t tx_broadcast_frames_hi;\n\tuint32_t tx_broadcast_frames_lo;\n\tuint32_t tx_broadcast_bytes_hi;\n\tuint32_t tx_broadcast_bytes_lo;\n\tuint32_t tx_frames_discarded_hi;\n\tuint32_t tx_frames_discarded_lo;\n\tuint32_t tx_frames_dropped_hi;\n\tuint32_t tx_frames_dropped_lo;\n\n\tuint32_t rx_unicast_frames_hi;\n\tuint32_t rx_unicast_frames_lo;\n\tuint32_t rx_unicast_bytes_hi;\n\tuint32_t rx_unicast_bytes_lo;\n\tuint32_t rx_multicast_frames_hi;\n\tuint32_t rx_multicast_frames_lo;\n\tuint32_t rx_multicast_bytes_hi;\n\tuint32_t rx_multicast_bytes_lo;\n\tuint32_t rx_broadcast_frames_hi;\n\tuint32_t rx_broadcast_frames_lo;\n\tuint32_t rx_broadcast_bytes_hi;\n\tuint32_t rx_broadcast_bytes_lo;\n\tuint32_t rx_frames_discarded_hi;\n\tuint32_t rx_frames_discarded_lo;\n\tuint32_t rx_frames_dropped_hi;\n\tuint32_t rx_frames_dropped_lo;\n};\n\n/* To maintain backward compatibility between FW and drivers, new elements */\n/* should be added to the end of the structure. */\n\n/* Per Port Statistics */\nstruct port_info {\n\tuint32_t size; /* size of this structure (i.e. sizeof(port_info)) */\n\tuint32_t enabled; /* 0 =Disabled, 1= Enabled */\n\tuint32_t link_speed; /* multiplier of 100Mb */\n\tuint32_t wol_support; /* WoL Support (i.e. Non-Zero if WOL supported ) */\n\tuint32_t flow_control; /* 802.3X Flow Ctrl. 0=off 1=RX 2=TX 3=RX&TX.*/\n\tuint32_t flex10; /* Flex10 mode enabled. non zero = yes */\n\tuint32_t rx_drops; /* RX Discards. Counters roll over, never reset */\n\tuint32_t rx_errors; /* RX Errors. Physical Port Stats L95, All PFs and NC-SI.\n\t\t\t\t This is flagged by Consumer as an error. */\n\tuint32_t rx_uncast_lo; /* RX Unicast Packets. Free running counters: */\n\tuint32_t rx_uncast_hi; /* RX Unicast Packets. Free running counters: */\n\tuint32_t rx_mcast_lo; /* RX Multicast Packets */\n\tuint32_t rx_mcast_hi; /* RX Multicast Packets */\n\tuint32_t rx_bcast_lo; /* RX Broadcast Packets */\n\tuint32_t rx_bcast_hi; /* RX Broadcast Packets */\n\tuint32_t tx_uncast_lo; /* TX Unicast Packets */\n\tuint32_t tx_uncast_hi; /* TX Unicast Packets */\n\tuint32_t tx_mcast_lo; /* TX Multicast Packets */\n\tuint32_t tx_mcast_hi; /* TX Multicast Packets */\n\tuint32_t tx_bcast_lo; /* TX Broadcast Packets */\n\tuint32_t tx_bcast_hi; /* TX Broadcast Packets */\n\tuint32_t tx_errors; /* TX Errors */\n\tuint32_t tx_discards; /* TX Discards */\n\tuint32_t rx_frames_lo; /* RX Frames received */\n\tuint32_t rx_frames_hi; /* RX Frames received */\n\tuint32_t rx_bytes_lo; /* RX Bytes received */\n\tuint32_t rx_bytes_hi; /* RX Bytes received */\n\tuint32_t tx_frames_lo; /* TX Frames sent */\n\tuint32_t tx_frames_hi; /* TX Frames sent */\n\tuint32_t tx_bytes_lo; /* TX Bytes sent */\n\tuint32_t tx_bytes_hi; /* TX Bytes sent */\n\tuint32_t link_status; /* Port P Link Status. 1:0 bit for port enabled.\n\t\t\t\t1:1 bit for link good,\n\t\t\t\t2:1 Set if link changed between last poll. */\n\tuint32_t tx_pfc_frames_lo; /* PFC Frames sent. */\n\tuint32_t tx_pfc_frames_hi; /* PFC Frames sent. */\n\tuint32_t rx_pfc_frames_lo; /* PFC Frames Received. */\n\tuint32_t rx_pfc_frames_hi; /* PFC Frames Received. */\n};\n\n\n#define BNX2X_5710_FW_MAJOR_VERSION\t\t\t7\n#define BNX2X_5710_FW_MINOR_VERSION\t\t\t2\n#define BNX2X_5710_FW_REVISION_VERSION\t\t51\n#define BNX2X_5710_FW_ENGINEERING_VERSION\t\t0\n#define BNX2X_5710_FW_COMPILE_FLAGS\t\t\t1\n\n\n/*\n * attention bits $$KEEP_ENDIANNESS$$\n */\nstruct atten_sp_status_block\n{\n\tuint32_t attn_bits /* 16 bit of attention signal lines */;\n\tuint32_t attn_bits_ack /* 16 bit of attention signal ack */;\n\tuint8_t status_block_id /* status block id */;\n\tuint8_t reserved0 /* resreved for padding */;\n\tuint16_t attn_bits_index /* attention bits running index */;\n\tuint32_t reserved1 /* resreved for padding */;\n};\n\n\n/*\n * The eth aggregative context of Cstorm\n */\nstruct cstorm_eth_ag_context\n{\n\tuint32_t __reserved0[10];\n};\n\n\n/*\n * dmae command structure\n */\nstruct dmae_command\n{\n\tuint32_t opcode;\n#define DMAE_COMMAND_SRC (0x1<<0) /* BitField opcode\tWhether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */\n#define DMAE_COMMAND_SRC_SHIFT 0\n#define DMAE_COMMAND_DST (0x3<<1) /* BitField opcode\tThe destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */\n#define DMAE_COMMAND_DST_SHIFT 1\n#define DMAE_COMMAND_C_DST (0x1<<3) /* BitField opcode\tThe destination of the completion: 0-PCIe 1-GRC */\n#define DMAE_COMMAND_C_DST_SHIFT 3\n#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) /* BitField opcode\tWhether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */\n#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4\n#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode\tWhether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */\n#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5\n#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode\tThe CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */\n#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6\n#define DMAE_COMMAND_ENDIANITY (0x3<<9) /* BitField opcode\tswapping mode. */\n#define DMAE_COMMAND_ENDIANITY_SHIFT 9\n#define DMAE_COMMAND_PORT (0x1<<11) /* BitField opcode\tWhich network port ID to present to the PCI request interface */\n#define DMAE_COMMAND_PORT_SHIFT 11\n#define DMAE_COMMAND_CRC_RESET (0x1<<12) /* BitField opcode\treset crc result */\n#define DMAE_COMMAND_CRC_RESET_SHIFT 12\n#define DMAE_COMMAND_SRC_RESET (0x1<<13) /* BitField opcode\treset source address in next go */\n#define DMAE_COMMAND_SRC_RESET_SHIFT 13\n#define DMAE_COMMAND_DST_RESET (0x1<<14) /* BitField opcode\treset dest address in next go */\n#define DMAE_COMMAND_DST_RESET_SHIFT 14\n#define DMAE_COMMAND_E1HVN (0x3<<15) /* BitField opcode\tvnic number E2 and onwards source vnic */\n#define DMAE_COMMAND_E1HVN_SHIFT 15\n#define DMAE_COMMAND_DST_VN (0x3<<17) /* BitField opcode\tE2 and onwards dest vnic */\n#define DMAE_COMMAND_DST_VN_SHIFT 17\n#define DMAE_COMMAND_C_FUNC (0x1<<19) /* BitField opcode\tE2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */\n#define DMAE_COMMAND_C_FUNC_SHIFT 19\n#define DMAE_COMMAND_ERR_POLICY (0x3<<20) /* BitField opcode\tE2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */\n#define DMAE_COMMAND_ERR_POLICY_SHIFT 20\n#define DMAE_COMMAND_RESERVED0 (0x3FF<<22) /* BitField opcode\t */\n#define DMAE_COMMAND_RESERVED0_SHIFT 22\n\tuint32_t src_addr_lo /* source address low/grc address */;\n\tuint32_t src_addr_hi /* source address hi */;\n\tuint32_t dst_addr_lo /* dest address low/grc address */;\n\tuint32_t dst_addr_hi /* dest address hi */;\n#if defined(__BIG_ENDIAN)\n\tuint16_t opcode_iov;\n#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tsource VF id */\n#define DMAE_COMMAND_SRC_VFID_SHIFT 0\n#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tselects the source function PF-0, VF-1 */\n#define DMAE_COMMAND_SRC_VFPF_SHIFT 6\n#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\t */\n#define DMAE_COMMAND_RESERVED1_SHIFT 7\n#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tdestination VF id */\n#define DMAE_COMMAND_DST_VFID_SHIFT 8\n#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tselects the destination function PF-0, VF-1 */\n#define DMAE_COMMAND_DST_VFPF_SHIFT 14\n#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\t */\n#define DMAE_COMMAND_RESERVED2_SHIFT 15\n\tuint16_t len /* copy length */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t len /* copy length */;\n\tuint16_t opcode_iov;\n#define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tsource VF id */\n#define DMAE_COMMAND_SRC_VFID_SHIFT 0\n#define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tselects the source function PF-0, VF-1 */\n#define DMAE_COMMAND_SRC_VFPF_SHIFT 6\n#define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\t */\n#define DMAE_COMMAND_RESERVED1_SHIFT 7\n#define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tdestination VF id */\n#define DMAE_COMMAND_DST_VFID_SHIFT 8\n#define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\tselects the destination function PF-0, VF-1 */\n#define DMAE_COMMAND_DST_VFPF_SHIFT 14\n#define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility\t */\n#define DMAE_COMMAND_RESERVED2_SHIFT 15\n#endif\n\tuint32_t comp_addr_lo /* completion address low/grc address */;\n\tuint32_t comp_addr_hi /* completion address hi */;\n\tuint32_t comp_val /* value to write to completion address */;\n\tuint32_t crc32 /* crc32 result */;\n\tuint32_t crc32_c /* crc32_c result */;\n#if defined(__BIG_ENDIAN)\n\tuint16_t crc16_c /* crc16_c result */;\n\tuint16_t crc16 /* crc16 result */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t crc16 /* crc16 result */;\n\tuint16_t crc16_c /* crc16_c result */;\n#endif\n#if defined(__BIG_ENDIAN)\n\tuint16_t reserved3;\n\tuint16_t crc_t10 /* crc_t10 result */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t crc_t10 /* crc_t10 result */;\n\tuint16_t reserved3;\n#endif\n#if defined(__BIG_ENDIAN)\n\tuint16_t xsum8 /* checksum8 result */;\n\tuint16_t xsum16 /* checksum16 result */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t xsum16 /* checksum16 result */;\n\tuint16_t xsum8 /* checksum8 result */;\n#endif\n};\n\n\n/*\n * common data for all protocols\n */\nstruct doorbell_hdr\n{\n\tuint8_t header;\n#define DOORBELL_HDR_RX (0x1<<0) /* BitField header\t1 for rx doorbell, 0 for tx doorbell */\n#define DOORBELL_HDR_RX_SHIFT 0\n#define DOORBELL_HDR_DB_TYPE (0x1<<1) /* BitField header\t0 for normal doorbell, 1 for advertise wnd doorbell */\n#define DOORBELL_HDR_DB_TYPE_SHIFT 1\n#define DOORBELL_HDR_DPM_SIZE (0x3<<2) /* BitField header\trdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */\n#define DOORBELL_HDR_DPM_SIZE_SHIFT 2\n#define DOORBELL_HDR_CONN_TYPE (0xF<<4) /* BitField header\tconnection type */\n#define DOORBELL_HDR_CONN_TYPE_SHIFT 4\n};\n\n/*\n * Ethernet doorbell\n */\nstruct eth_tx_doorbell\n{\n#if defined(__BIG_ENDIAN)\n\tuint16_t npackets /* number of data bytes that were added in the doorbell */;\n\tuint8_t params;\n#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params\tnumber of buffer descriptors that were added in the doorbell */\n#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0\n#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params\ttx fin command flag */\n#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6\n#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params\tdoorbell queue spare flag */\n#define ETH_TX_DOORBELL_SPARE_SHIFT 7\n\tstruct doorbell_hdr hdr;\n#elif defined(__LITTLE_ENDIAN)\n\tstruct doorbell_hdr hdr;\n\tuint8_t params;\n#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params\tnumber of buffer descriptors that were added in the doorbell */\n#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0\n#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params\ttx fin command flag */\n#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6\n#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params\tdoorbell queue spare flag */\n#define ETH_TX_DOORBELL_SPARE_SHIFT 7\n\tuint16_t npackets /* number of data bytes that were added in the doorbell */;\n#endif\n};\n\n\n/*\n * 3 lines. status block $$KEEP_ENDIANNESS$$\n */\nstruct hc_status_block_e1x\n{\n\tuint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */;\n\tuint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;\n\tuint32_t rsrv[11];\n};\n\n/*\n * host status block\n */\nstruct host_hc_status_block_e1x\n{\n\tstruct hc_status_block_e1x sb /* fast path indices */;\n};\n\n\n/*\n * 3 lines. status block $$KEEP_ENDIANNESS$$\n */\nstruct hc_status_block_e2\n{\n\tuint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */;\n\tuint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;\n\tuint32_t reserved[11];\n};\n\n/*\n * host status block\n */\nstruct host_hc_status_block_e2\n{\n\tstruct hc_status_block_e2 sb /* fast path indices */;\n};\n\n\n/*\n * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$\n */\nstruct hc_sp_status_block\n{\n\tuint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */;\n\tuint16_t running_index /* Status Block running index */;\n\tuint16_t rsrv;\n\tuint32_t rsrv1;\n};\n\n/*\n * host status block\n */\nstruct host_sp_status_block\n{\n\tstruct atten_sp_status_block atten_status_block /* attention bits section */;\n\tstruct hc_sp_status_block sp_sb /* slow path indices */;\n};\n\n\n/*\n * IGU driver acknowledgment register\n */\nunion igu_ack_register\n{\n\tstruct {\n#if defined(__BIG_ENDIAN)\n\t\tuint16_t sb_id_and_flags;\n#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags\t0-15: non default status blocks, 16: default status block */\n#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0\n#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags\t0-3:storm id, 4: attn status block (valid in default sb only) */\n#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5\n#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags\tif set, acknowledges status block index */\n#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8\n#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags\tinterrupt enable/disable/nop: use IGU_INT_xxx constants */\n#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9\n#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags\t */\n#define IGU_ACK_REGISTER_RESERVED_SHIFT 11\n\t\tuint16_t status_block_index /* status block index acknowledgement */;\n#elif defined(__LITTLE_ENDIAN)\n\t\tuint16_t status_block_index /* status block index acknowledgement */;\n\t\tuint16_t sb_id_and_flags;\n#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags\t0-15: non default status blocks, 16: default status block */\n#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0\n#define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags\t0-3:storm id, 4: attn status block (valid in default sb only) */\n#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5\n#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags\tif set, acknowledges status block index */\n#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8\n#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags\tinterrupt enable/disable/nop: use IGU_INT_xxx constants */\n#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9\n#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags\t */\n#define IGU_ACK_REGISTER_RESERVED_SHIFT 11\n#endif\n\t} sb;\n\tuint32_t raw_data;\n};\n\n\n/*\n * IGU driver acknowledgement register\n */\nstruct igu_backward_compatible\n{\n\tuint32_t sb_id_and_flags;\n#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags\t */\n#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0\n#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags\t */\n#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16\n#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags\t0-3:storm id, 4: attn status block (valid in default sb only) */\n#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21\n#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags\tif set, acknowledges status block index */\n#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24\n#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags\tinterrupt enable/disable/nop: use IGU_INT_xxx constants */\n#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25\n#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags\t */\n#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27\n\tuint32_t reserved_2;\n};\n\n\n/*\n * IGU driver acknowledgement register\n */\nstruct igu_regular\n{\n\tuint32_t sb_id_and_flags;\n#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags\t */\n#define IGU_REGULAR_SB_INDEX_SHIFT 0\n#define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags\t */\n#define IGU_REGULAR_RESERVED0_SHIFT 20\n#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags\t21-23 (use enum igu_seg_access) */\n#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21\n#define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags\t */\n#define IGU_REGULAR_BUPDATE_SHIFT 24\n#define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags\tinterrupt enable/disable/nop (use enum igu_int_cmd) */\n#define IGU_REGULAR_ENABLE_INT_SHIFT 25\n#define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags\t */\n#define IGU_REGULAR_RESERVED_1_SHIFT 27\n#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags\t */\n#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28\n#define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags\t */\n#define IGU_REGULAR_CLEANUP_SET_SHIFT 30\n#define IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags\t */\n#define IGU_REGULAR_BCLEANUP_SHIFT 31\n\tuint32_t reserved_2;\n};\n\n/*\n * IGU driver acknowledgement register\n */\nunion igu_consprod_reg\n{\n\tstruct igu_regular regular;\n\tstruct igu_backward_compatible backward_compatible;\n};\n\n\n/*\n * Igu control commands\n */\nenum igu_ctrl_cmd\n{\n\tIGU_CTRL_CMD_TYPE_RD,\n\tIGU_CTRL_CMD_TYPE_WR,\n\tMAX_IGU_CTRL_CMD};\n\n\n/*\n * Control register for the IGU command register\n */\nstruct igu_ctrl_reg\n{\n\tuint32_t ctrl_data;\n#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data\t */\n#define IGU_CTRL_REG_ADDRESS_SHIFT 0\n#define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data\t */\n#define IGU_CTRL_REG_FID_SHIFT 12\n#define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data\t */\n#define IGU_CTRL_REG_RESERVED_SHIFT 19\n#define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data\t (use enum igu_ctrl_cmd) */\n#define IGU_CTRL_REG_TYPE_SHIFT 20\n#define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data\t */\n#define IGU_CTRL_REG_UNUSED_SHIFT 21\n};\n\n\n/*\n * Igu interrupt command\n */\nenum igu_int_cmd\n{\n\tIGU_INT_ENABLE,\n\tIGU_INT_DISABLE,\n\tIGU_INT_NOP,\n\tIGU_INT_NOP2,\n\tMAX_IGU_INT_CMD};\n\n\n/*\n * Igu segments\n */\nenum igu_seg_access\n{\n\tIGU_SEG_ACCESS_NORM,\n\tIGU_SEG_ACCESS_DEF,\n\tIGU_SEG_ACCESS_ATTN,\n\tMAX_IGU_SEG_ACCESS};\n\n\n/*\n * Parser parsing flags field\n */\nstruct parsing_flags\n{\n\tuint16_t flags;\n#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags\t0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */\n#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0\n#define PARSING_FLAGS_VLAN (0x1<<1) /* BitField flagscontext flags\t0 or 1 */\n#define PARSING_FLAGS_VLAN_SHIFT 1\n#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) /* BitField flagscontext flags\t0 or 1 */\n#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2\n#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags\t0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */\n#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3\n#define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags\t0=no IP options / extension headers. 1=IP options / extension header exist */\n#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5\n#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags\t0=non-fragmented, 1=fragmented */\n#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6\n#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags\t0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */\n#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7\n#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags\t0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */\n#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9\n#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags\t0=no TCP options. 1=TCP options */\n#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10\n#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags\tAccording to the TCP header options parsing */\n#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11\n#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags\tconnection match in searcher indication */\n#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12\n#define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags\tLLC SNAP indication */\n#define PARSING_FLAGS_LLC_SNAP_SHIFT 13\n#define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags\t */\n#define PARSING_FLAGS_RESERVED0_SHIFT 14\n};\n\n\n/*\n * Parsing flags for TCP ACK type\n */\nenum prs_flags_ack_type\n{\n\tPRS_FLAG_PUREACK_PIGGY,\n\tPRS_FLAG_PUREACK_PURE,\n\tMAX_PRS_FLAGS_ACK_TYPE};\n\n\n/*\n * Parsing flags for Ethernet address type\n */\nenum prs_flags_eth_addr_type\n{\n\tPRS_FLAG_ETHTYPE_NON_UNICAST,\n\tPRS_FLAG_ETHTYPE_UNICAST,\n\tMAX_PRS_FLAGS_ETH_ADDR_TYPE};\n\n\n/*\n * Parsing flags for over-ethernet protocol\n */\nenum prs_flags_over_eth\n{\n\tPRS_FLAG_OVERETH_UNKNOWN,\n\tPRS_FLAG_OVERETH_IPV4,\n\tPRS_FLAG_OVERETH_IPV6,\n\tPRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,\n\tMAX_PRS_FLAGS_OVER_ETH};\n\n\n/*\n * Parsing flags for over-IP protocol\n */\nenum prs_flags_over_ip\n{\n\tPRS_FLAG_OVERIP_UNKNOWN,\n\tPRS_FLAG_OVERIP_TCP,\n\tPRS_FLAG_OVERIP_UDP,\n\tMAX_PRS_FLAGS_OVER_IP};\n\n\n/*\n * SDM operation gen command (generate aggregative interrupt)\n */\nstruct sdm_op_gen\n{\n\tuint32_t command;\n#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type\tthread ID/aggr interrupt number/counter depending on the completion type */\n#define SDM_OP_GEN_COMP_PARAM_SHIFT 0\n#define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type\tDirect messages to CM / PCI switch are not supported in operation_gen completion */\n#define SDM_OP_GEN_COMP_TYPE_SHIFT 5\n#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type\tbit index in aggregated interrupt vector */\n#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8\n#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type\t */\n#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16\n#define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type\t */\n#define SDM_OP_GEN_RESERVED_SHIFT 17\n};\n\n\n/*\n * Timers connection context\n */\nstruct timers_block_context\n{\n\tuint32_t __reserved_0 /* data of client 0 of the timers block*/;\n\tuint32_t __reserved_1 /* data of client 1 of the timers block*/;\n\tuint32_t __reserved_2 /* data of client 2 of the timers block*/;\n\tuint32_t flags;\n#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags\tnumber of active timers running */\n#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0\n#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags\tflag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */\n#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2\n#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags\t */\n#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3\n};\n\n\n/*\n * The eth aggregative context of Tstorm\n */\nstruct tstorm_eth_ag_context\n{\n\tuint32_t __reserved0[14];\n};\n\n\n/*\n * The eth aggregative context of Ustorm\n */\nstruct ustorm_eth_ag_context\n{\n\tuint32_t __reserved0;\n#if defined(__BIG_ENDIAN)\n\tuint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;\n\tuint8_t __reserved2;\n\tuint16_t __reserved1;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t __reserved1;\n\tuint8_t __reserved2;\n\tuint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;\n#endif\n\tuint32_t __reserved3[6];\n};\n\n\n/*\n * The eth aggregative context of Xstorm\n */\nstruct xstorm_eth_ag_context\n{\n\tuint32_t reserved0;\n#if defined(__BIG_ENDIAN)\n\tuint8_t cdu_reserved /* Used by the CDU for validation and debugging */;\n\tuint8_t reserved2;\n\tuint16_t reserved1;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t reserved1;\n\tuint8_t reserved2;\n\tuint8_t cdu_reserved /* Used by the CDU for validation and debugging */;\n#endif\n\tuint32_t reserved3[30];\n};\n\n\n/*\n * doorbell message sent to the chip\n */\nstruct doorbell\n{\n#if defined(__BIG_ENDIAN)\n\tuint16_t zero_fill2 /* driver must zero this field! */;\n\tuint8_t zero_fill1 /* driver must zero this field! */;\n\tstruct doorbell_hdr header;\n#elif defined(__LITTLE_ENDIAN)\n\tstruct doorbell_hdr header;\n\tuint8_t zero_fill1 /* driver must zero this field! */;\n\tuint16_t zero_fill2 /* driver must zero this field! */;\n#endif\n};\n\n\n/*\n * doorbell message sent to the chip\n */\nstruct doorbell_set_prod\n{\n#if defined(__BIG_ENDIAN)\n\tuint16_t prod /* Producer index to be set */;\n\tuint8_t zero_fill1 /* driver must zero this field! */;\n\tstruct doorbell_hdr header;\n#elif defined(__LITTLE_ENDIAN)\n\tstruct doorbell_hdr header;\n\tuint8_t zero_fill1 /* driver must zero this field! */;\n\tuint16_t prod /* Producer index to be set */;\n#endif\n};\n\n\nstruct regpair\n{\n\tuint32_t lo /* low word for reg-pair */;\n\tuint32_t hi /* high word for reg-pair */;\n};\n\n\nstruct regpair_native\n{\n\tuint32_t lo /* low word for reg-pair */;\n\tuint32_t hi /* high word for reg-pair */;\n};\n\n\n/*\n * Classify rule opcodes in E2/E3\n */\nenum classify_rule\n{\n\tCLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */,\n\tCLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */,\n\tCLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */,\n\tMAX_CLASSIFY_RULE};\n\n\n/*\n * Classify rule types in E2/E3\n */\nenum classify_rule_action_type\n{\n\tCLASSIFY_RULE_REMOVE,\n\tCLASSIFY_RULE_ADD,\n\tMAX_CLASSIFY_RULE_ACTION_TYPE};\n\n\n/*\n * client init ramrod data $$KEEP_ENDIANNESS$$\n */\nstruct client_init_general_data\n{\n\tuint8_t client_id /* client_id */;\n\tuint8_t statistics_counter_id /* statistics counter id */;\n\tuint8_t statistics_en_flg /* statistics en flg */;\n\tuint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */;\n\tuint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;\n\tuint8_t sp_client_id /* the slow path rings client Id. */;\n\tuint16_t mtu /* Host MTU from client config */;\n\tuint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */;\n\tuint8_t func_id /* PCI function ID (0-71) */;\n\tuint8_t cos /* The connection cos, if applicable */;\n\tuint8_t traffic_type;\n\tuint32_t reserved0;\n};\n\n\n/*\n * client init rx data $$KEEP_ENDIANNESS$$\n */\nstruct client_init_rx_data\n{\n\tuint8_t tpa_en;\n#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable\ttpa enable flg ipv4 */\n#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0\n#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable\ttpa enable flg ipv6 */\n#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1\n#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable\ttpa mode (LRO or GRO) (use enum tpa_mode) */\n#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2\n#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable\t */\n#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3\n\tuint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */;\n\tuint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */;\n\tuint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */;\n\tuint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */;\n\tuint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;\n\tuint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */;\n\tuint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */;\n\tuint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */;\n\tuint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */;\n\tuint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */;\n\tuint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */;\n\tuint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */;\n\tuint8_t status_block_id /* rx status block id */;\n\tuint8_t rx_sb_index_number /* status block indices */;\n\tuint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;\n\tuint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;\n\tuint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;\n\tuint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */;\n\tuint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;\n\tuint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */;\n\tuint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */;\n\tstruct regpair bd_page_base /* BD page base address at the host */;\n\tstruct regpair sge_page_base /* SGE page base address at the host */;\n\tstruct regpair cqe_page_base /* Completion queue base address */;\n\tuint8_t is_leading_rss;\n\tuint8_t is_approx_mcast;\n\tuint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;\n\tuint16_t state;\n#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state\tdrop all unicast packets */\n#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0\n#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state\taccept all unicast packets (subject to vlan) */\n#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1\n#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state\taccept all unmatched unicast packets (subject to vlan) */\n#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2\n#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state\tdrop all multicast packets */\n#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3\n#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state\taccept all multicast packets (subject to vlan) */\n#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4\n#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state\taccept all broadcast packets (subject to vlan) */\n#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5\n#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state\taccept packets matched only by MAC (without checking vlan) */\n#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6\n#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state\t */\n#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7\n\tuint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */;\n\tuint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */;\n\tuint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */;\n\tuint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */;\n\tuint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;\n\tuint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;\n\tuint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket whith will be genratet when this ring is full. for regular flow control set this to 1 */;\n\tuint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;\n\tuint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;\n\tuint32_t reserved6[2];\n};\n\n/*\n * client init tx data $$KEEP_ENDIANNESS$$\n */\nstruct client_init_tx_data\n{\n\tuint8_t enforce_security_flg /* if set, security checks will be made for this connection */;\n\tuint8_t tx_status_block_id /* the number of status block to update */;\n\tuint8_t tx_sb_index_number /* the index to use inside the status block */;\n\tuint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */;\n\tuint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */;\n\tuint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */;\n\tuint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;\n\tstruct regpair tx_bd_page_base /* BD page base address at the host for TxBdCons */;\n\tuint16_t state;\n#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state\taccept all unicast packets (subject to vlan) */\n#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0\n#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state\taccept all multicast packets (subject to vlan) */\n#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1\n#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state\taccept all broadcast packets (subject to vlan) */\n#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2\n#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state\taccept packets matched only by MAC (without checking vlan) */\n#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3\n#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state\t */\n#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4\n\tuint8_t default_vlan_flg /* is default vlan valid for this client. */;\n\tuint8_t force_default_pri_flg /* if set, force default priority */;\n\tuint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */;\n\tuint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */;\n\tuint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */;\n\tuint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */;\n};\n\n/*\n * client init ramrod data $$KEEP_ENDIANNESS$$\n */\nstruct client_init_ramrod_data\n{\n\tstruct client_init_general_data general /* client init general data */;\n\tstruct client_init_rx_data rx /* client init rx data */;\n\tstruct client_init_tx_data tx /* client init tx data */;\n};\n\n\n/*\n * client update ramrod data $$KEEP_ENDIANNESS$$\n */\nstruct client_update_ramrod_data\n{\n\tuint8_t client_id /* the client to update */;\n\tuint8_t func_id /* PCI function ID this client belongs to (0-71) */;\n\tuint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */;\n\tuint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */;\n\tuint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */;\n\tuint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */;\n\tuint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */;\n\tuint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */;\n\tuint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;\n\tuint8_t activate_change_flg /* If set, activate_flg will be checked */;\n\tuint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;\n\tuint8_t default_vlan_enable_flg;\n\tuint8_t default_vlan_change_flg;\n\tuint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;\n\tuint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;\n\tuint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;\n\tuint8_t silent_vlan_change_flg;\n\tuint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */;\n\tuint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */;\n\tuint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */;\n\tuint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */;\n\tuint32_t reserved1;\n\tuint32_t echo /* echo value to be sent to driver on event ring */;\n};\n\n\n/*\n * The eth storm context of Cstorm\n */\nstruct cstorm_eth_st_context\n{\n\tuint32_t __reserved0[4];\n};\n\n\nstruct double_regpair\n{\n\tuint32_t regpair0_lo /* low word for reg-pair0 */;\n\tuint32_t regpair0_hi /* high word for reg-pair0 */;\n\tuint32_t regpair1_lo /* low word for reg-pair1 */;\n\tuint32_t regpair1_hi /* high word for reg-pair1 */;\n};\n\n\n/*\n * Ethernet address typesm used in ethernet tx BDs\n */\nenum eth_addr_type\n{\n\tUNKNOWN_ADDRESS,\n\tUNICAST_ADDRESS,\n\tMULTICAST_ADDRESS,\n\tBROADCAST_ADDRESS,\n\tMAX_ETH_ADDR_TYPE};\n\n\n/*\n * $$KEEP_ENDIANNESS$$\n */\nstruct eth_classify_cmd_header\n{\n\tuint8_t cmd_general_data;\n#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data\tshould this cmd be applied for Rx */\n#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0\n#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data\tshould this cmd be applied for Tx */\n#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1\n#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data\tcommand opcode for MAC/VLAN/PAIR (use enum classify_rule) */\n#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2\n#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data\t (use enum classify_rule_action_type) */\n#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4\n#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data\t */\n#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5\n\tuint8_t func_id /* the function id */;\n\tuint8_t client_id;\n\tuint8_t reserved1;\n};\n\n\n/*\n * header for eth classification config ramrod $$KEEP_ENDIANNESS$$\n */\nstruct eth_classify_header\n{\n\tuint8_t rule_cnt /* number of rules in classification config ramrod */;\n\tuint8_t reserved0;\n\tuint16_t reserved1;\n\tuint32_t echo /* echo value to be sent to driver on event ring */;\n};\n\n\n/*\n * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$\n */\nstruct eth_classify_mac_cmd\n{\n\tstruct eth_classify_cmd_header header;\n\tuint16_t reserved0;\n\tuint16_t inner_mac;\n\tuint16_t mac_lsb;\n\tuint16_t mac_mid;\n\tuint16_t mac_msb;\n\tuint16_t reserved1;\n};\n\n\n/*\n * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$\n */\nstruct eth_classify_pair_cmd\n{\n\tstruct eth_classify_cmd_header header;\n\tuint16_t reserved0;\n\tuint16_t inner_mac;\n\tuint16_t mac_lsb;\n\tuint16_t mac_mid;\n\tuint16_t mac_msb;\n\tuint16_t vlan;\n};\n\n\n/*\n * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$\n */\nstruct eth_classify_vlan_cmd\n{\n\tstruct eth_classify_cmd_header header;\n\tuint32_t reserved0;\n\tuint32_t reserved1;\n\tuint16_t reserved2;\n\tuint16_t vlan;\n};\n\n/*\n * union for eth classification rule $$KEEP_ENDIANNESS$$\n */\nunion eth_classify_rule_cmd\n{\n\tstruct eth_classify_mac_cmd mac;\n\tstruct eth_classify_vlan_cmd vlan;\n\tstruct eth_classify_pair_cmd pair;\n};\n\n/*\n * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$\n */\nstruct eth_classify_rules_ramrod_data\n{\n\tstruct eth_classify_header header;\n\tunion eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];\n};\n\n\n/*\n * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$\n */\nstruct eth_common_ramrod_data\n{\n\tuint32_t client_id /* id of this client. (5 bits are used) */;\n\tuint32_t reserved1;\n};\n\n\n/*\n * The eth storm context of Ustorm\n */\nstruct ustorm_eth_st_context\n{\n\tuint32_t reserved0[52];\n};\n\n/*\n * The eth storm context of Tstorm\n */\nstruct tstorm_eth_st_context\n{\n\tuint32_t __reserved0[28];\n};\n\n/*\n * The eth storm context of Xstorm\n */\nstruct xstorm_eth_st_context\n{\n\tuint32_t reserved0[60];\n};\n\n/*\n * Ethernet connection context\n */\nstruct eth_context\n{\n\tstruct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */;\n\tstruct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */;\n\tstruct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */;\n\tstruct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */;\n\tstruct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */;\n\tstruct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */;\n\tstruct timers_block_context timers_context /* Timers block context */;\n\tstruct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */;\n\tstruct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */;\n};\n\n\n/*\n * union for sgl and raw data.\n */\nunion eth_sgl_or_raw_data\n{\n\tuint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */;\n\tuint32_t raw_data[4] /* raw data from Tstorm to the driver. */;\n};\n\n/*\n * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$\n */\nstruct eth_end_agg_rx_cqe\n{\n\tuint8_t type_error_flags;\n#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags\t (use enum eth_rx_cqe_type) */\n#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0\n#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags\t (use enum eth_rx_fp_sel) */\n#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2\n#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags\t */\n#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3\n\tuint8_t reserved1;\n\tuint8_t queue_index /* The aggregation queue index of this packet */;\n\tuint8_t reserved2;\n\tuint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */;\n\tuint16_t num_of_coalesced_segs /* Num of coalesced segments. */;\n\tuint16_t pkt_len /* Packet length */;\n\tuint8_t pure_ack_count /* Number of pure acks coalesced. */;\n\tuint8_t reserved3;\n\tuint16_t reserved4;\n\tunion eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;\n\tuint32_t reserved5[8];\n};\n\n\n/*\n * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$\n */\nstruct eth_fast_path_rx_cqe\n{\n\tuint8_t type_error_flags;\n#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags\t (use enum eth_rx_cqe_type) */\n#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0\n#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags\t (use enum eth_rx_fp_sel) */\n#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2\n#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags\tPhysical layer errors */\n#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3\n#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags\tIP checksum error */\n#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4\n#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags\tTCP/UDP checksum error */\n#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5\n#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) /* BitField type_error_flags\t */\n#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6\n\tuint8_t status_flags;\n#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags\t (use enum eth_rss_hash_type) */\n#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0\n#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags\tRSS hashing on/off */\n#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3\n#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags\tif set to 1, this is a broadcast packet */\n#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4\n#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags\tif set to 1, the MAC address was matched in the tstorm CAM search */\n#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5\n#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags\tIP checksum validation was not performed (if packet is not IPv4) */\n#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6\n#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags\tTCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */\n#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7\n\tuint8_t queue_index /* The aggregation queue index of this packet */;\n\tuint8_t placement_offset /* Placement offset from the start of the BD, in bytes */;\n\tuint32_t rss_hash_result /* RSS toeplitz hash result */;\n\tuint16_t vlan_tag /* Ethernet VLAN tag field */;\n\tuint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */;\n\tuint16_t len_on_bd /* Number of bytes placed on the BD */;\n\tstruct parsing_flags pars_flags;\n\tunion eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;\n\tuint32_t reserved1[8];\n};\n\n\n/*\n * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$\n */\nstruct eth_filter_rules_cmd\n{\n\tuint8_t cmd_general_data;\n#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data\tshould this cmd be applied for Rx */\n#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0\n#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data\tshould this cmd be applied for Tx */\n#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1\n#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data\t */\n#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2\n\tuint8_t func_id /* the function id */;\n\tuint8_t client_id /* the client id */;\n\tuint8_t reserved1;\n\tuint16_t state;\n#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state\tdrop all unicast packets */\n#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0\n#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state\taccept all unicast packets (subject to vlan) */\n#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1\n#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state\taccept all unmatched unicast packets */\n#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2\n#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state\tdrop all multicast packets */\n#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3\n#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state\taccept all multicast packets (subject to vlan) */\n#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4\n#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state\taccept all broadcast packets (subject to vlan) */\n#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5\n#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state\taccept packets matched only by MAC (without checking vlan) */\n#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6\n#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state\t */\n#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7\n\tuint16_t reserved3;\n\tstruct regpair reserved4;\n};\n\n\n/*\n * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$\n */\nstruct eth_filter_rules_ramrod_data\n{\n\tstruct eth_classify_header header;\n\tstruct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];\n};\n\n\n/*\n * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$\n */\nstruct eth_general_rules_ramrod_data\n{\n\tstruct eth_classify_header header;\n\tunion eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];\n};\n\n\n/*\n * The data for Halt ramrod\n */\nstruct eth_halt_ramrod_data\n{\n\tuint32_t client_id /* id of this client. (5 bits are used) */;\n\tuint32_t reserved0;\n};\n\n\n/*\n * destination and source mac address.\n */\nstruct eth_mac_addresses\n{\n#if defined(__BIG_ENDIAN)\n\tuint16_t dst_mid /* destination mac address 16 middle bits */;\n\tuint16_t dst_lo /* destination mac address 16 low bits */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t dst_lo /* destination mac address 16 low bits */;\n\tuint16_t dst_mid /* destination mac address 16 middle bits */;\n#endif\n#if defined(__BIG_ENDIAN)\n\tuint16_t src_lo /* source mac address 16 low bits */;\n\tuint16_t dst_hi /* destination mac address 16 high bits */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t dst_hi /* destination mac address 16 high bits */;\n\tuint16_t src_lo /* source mac address 16 low bits */;\n#endif\n#if defined(__BIG_ENDIAN)\n\tuint16_t src_hi /* source mac address 16 high bits */;\n\tuint16_t src_mid /* source mac address 16 middle bits */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t src_mid /* source mac address 16 middle bits */;\n\tuint16_t src_hi /* source mac address 16 high bits */;\n#endif\n};\n\n\n/*\n * tunneling related data.\n */\nstruct eth_tunnel_data\n{\n#if defined(__BIG_ENDIAN)\n\tuint16_t dst_mid /* destination mac address 16 middle bits */;\n\tuint16_t dst_lo /* destination mac address 16 low bits */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t dst_lo /* destination mac address 16 low bits */;\n\tuint16_t dst_mid /* destination mac address 16 middle bits */;\n#endif\n#if defined(__BIG_ENDIAN)\n\tuint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;\n\tuint16_t dst_hi /* destination mac address 16 high bits */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t dst_hi /* destination mac address 16 high bits */;\n\tuint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;\n#endif\n#if defined(__BIG_ENDIAN)\n\tuint8_t flags;\n#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags\tSet in case outer IP header is ipV6 */\n#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0\n#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags\tShould be set with 0 */\n#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1\n\tuint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;\n\tuint16_t pseudo_csum /* Pseudo checksum with length field=0 */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t pseudo_csum /* Pseudo checksum with length field=0 */;\n\tuint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;\n\tuint8_t flags;\n#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags\tSet in case outer IP header is ipV6 */\n#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0\n#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags\tShould be set with 0 */\n#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1\n#endif\n};\n\n/*\n * union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1).\n */\nunion eth_mac_addr_or_tunnel_data\n{\n\tstruct eth_mac_addresses mac_addr /* destination and source mac addresses. */;\n\tstruct eth_tunnel_data tunnel_data /* tunneling related data. */;\n};\n\n\n/*\n * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$\n */\nstruct eth_multicast_rules_cmd\n{\n\tuint8_t cmd_general_data;\n#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data\tshould this cmd be applied for Rx */\n#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0\n#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data\tshould this cmd be applied for Tx */\n#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1\n#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data\t1 for add rule, 0 for remove rule */\n#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2\n#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data\t */\n#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3\n\tuint8_t func_id /* the function id */;\n\tuint8_t bin_id /* the bin to add this function to (0-255) */;\n\tuint8_t engine_id /* the approximate multicast engine id */;\n\tuint32_t reserved2;\n\tstruct regpair reserved3;\n};\n\n\n/*\n * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$\n */\nstruct eth_multicast_rules_ramrod_data\n{\n\tstruct eth_classify_header header;\n\tstruct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];\n};\n\n\n/*\n * Place holder for ramrods protocol specific data\n */\nstruct ramrod_data\n{\n\tuint32_t data_lo;\n\tuint32_t data_hi;\n};\n\n/*\n * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)\n */\nunion eth_ramrod_data\n{\n\tstruct ramrod_data general;\n};\n\n\n/*\n * RSS toeplitz hash type, as reported in CQE\n */\nenum eth_rss_hash_type\n{\n\tDEFAULT_HASH_TYPE,\n\tIPV4_HASH_TYPE,\n\tTCP_IPV4_HASH_TYPE,\n\tIPV6_HASH_TYPE,\n\tTCP_IPV6_HASH_TYPE,\n\tVLAN_PRI_HASH_TYPE,\n\tE1HOV_PRI_HASH_TYPE,\n\tDSCP_HASH_TYPE,\n\tMAX_ETH_RSS_HASH_TYPE};\n\n\n/*\n * Ethernet RSS mode\n */\nenum eth_rss_mode\n{\n\tETH_RSS_MODE_DISABLED,\n\tETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS if packet is UDP with dst port that matches the UDP 4-tuble Destination Port mask and value) */,\n\tETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,\n\tETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field */,\n\tETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field */,\n\tETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field */,\n\tMAX_ETH_RSS_MODE};\n\n\n/*\n * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$\n */\nstruct eth_rss_update_ramrod_data\n{\n\tuint8_t rss_engine_id;\n\tuint8_t capabilities;\n#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the IpV4 2-tupple capability */\n#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0\n#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the IpV4 4-tupple capability for TCP */\n#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1\n#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the IpV4 4-tupple capability for UDP */\n#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2\n#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the IpV6 2-tupple capability */\n#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3\n#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the IpV6 4-tupple capability for TCP */\n#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4\n#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the IpV6 4-tupple capability for UDP */\n#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5\n#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities\tconfiguration of the 5-tupple capability */\n#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6\n#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities\tif set update the rss keys */\n#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7\n\tuint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;\n\tuint8_t rss_mode /* The RSS mode for this function */;\n\tuint16_t udp_4tuple_dst_port_mask /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;\n\tuint16_t udp_4tuple_dst_port_value /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */;\n\tuint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */;\n\tuint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */;\n\tuint32_t echo;\n\tuint32_t reserved3;\n};\n\n\n/*\n * The eth Rx Buffer Descriptor\n */\nstruct eth_rx_bd\n{\n\tuint32_t addr_lo /* Single continuous buffer low pointer */;\n\tuint32_t addr_hi /* Single continuous buffer high pointer */;\n};\n\n\n/*\n * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$\n */\nstruct common_ramrod_eth_rx_cqe\n{\n\tuint8_t ramrod_type;\n#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type\t (use enum eth_rx_cqe_type) */\n#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0\n#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type\t */\n#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2\n#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type\t */\n#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3\n\tuint8_t conn_type /* only 3 bits are used */;\n\tuint16_t reserved1 /* protocol specific data */;\n\tuint32_t conn_and_cmd_data;\n#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data\t */\n#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0\n#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data\tcommand id of the ramrod- use RamrodCommandIdEnum */\n#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24\n\tstruct ramrod_data protocol_data /* protocol specific data */;\n\tuint32_t echo;\n\tuint32_t reserved2[11];\n};\n\n/*\n * Rx Last CQE in page (in ETH)\n */\nstruct eth_rx_cqe_next_page\n{\n\tuint32_t addr_lo /* Next page low pointer */;\n\tuint32_t addr_hi /* Next page high pointer */;\n\tuint32_t reserved[14];\n};\n\n/*\n * union for all eth rx cqe types (fix their sizes)\n */\nunion eth_rx_cqe\n{\n\tstruct eth_fast_path_rx_cqe fast_path_cqe;\n\tstruct common_ramrod_eth_rx_cqe ramrod_cqe;\n\tstruct eth_rx_cqe_next_page next_page_cqe;\n\tstruct eth_end_agg_rx_cqe end_agg_cqe;\n};\n\n\n/*\n * Values for RX ETH CQE type field\n */\nenum eth_rx_cqe_type\n{\n\tRX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */,\n\tRX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */,\n\tRX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */,\n\tRX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */,\n\tMAX_ETH_RX_CQE_TYPE};\n\n\n/*\n * Type of SGL/Raw field in ETH RX fast path CQE\n */\nenum eth_rx_fp_sel\n{\n\tETH_FP_CQE_REGULAR /* Regular CQE- no extra data */,\n\tETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */,\n\tMAX_ETH_RX_FP_SEL};\n\n\n/*\n * The eth Rx SGE Descriptor\n */\nstruct eth_rx_sge\n{\n\tuint32_t addr_lo /* Single continuous buffer low pointer */;\n\tuint32_t addr_hi /* Single continuous buffer high pointer */;\n};\n\n\n/*\n * common data for all protocols $$KEEP_ENDIANNESS$$\n */\nstruct spe_hdr\n{\n\tuint32_t conn_and_cmd_data;\n#define SPE_HDR_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data\t */\n#define SPE_HDR_CID_SHIFT 0\n#define SPE_HDR_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data\tcommand id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */\n#define SPE_HDR_CMD_ID_SHIFT 24\n\tuint16_t type;\n#define SPE_HDR_CONN_TYPE (0xFF<<0) /* BitField type\tconnection type. (3 bits are used) (use enum connection_type) */\n#define SPE_HDR_CONN_TYPE_SHIFT 0\n#define SPE_HDR_FUNCTION_ID (0xFF<<8) /* BitField type\t */\n#define SPE_HDR_FUNCTION_ID_SHIFT 8\n\tuint16_t reserved1;\n};\n\n/*\n * specific data for ethernet slow path element\n */\nunion eth_specific_data\n{\n\tuint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;\n\tstruct regpair client_update_ramrod_data /* The address of the data for client update ramrod */;\n\tstruct regpair client_init_ramrod_init_data /* The data for client setup ramrod */;\n\tstruct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */;\n\tstruct regpair update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */;\n\tstruct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */;\n\tstruct regpair classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */;\n\tstruct regpair filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */;\n\tstruct regpair mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */;\n};\n\n/*\n * Ethernet slow path element\n */\nstruct eth_spe\n{\n\tstruct spe_hdr hdr /* common data for all protocols */;\n\tunion eth_specific_data data /* data specific to ethernet protocol */;\n};\n\n\n/*\n * Ethernet command ID for slow path elements\n */\nenum eth_spqe_cmd_id\n{\n\tRAMROD_CMD_ID_ETH_UNUSED,\n\tRAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */,\n\tRAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */,\n\tRAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */,\n\tRAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */,\n\tRAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */,\n\tRAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */,\n\tRAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */,\n\tRAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */,\n\tRAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,\n\tRAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,\n\tRAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,\n\tRAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */,\n\tRAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */,\n\tMAX_ETH_SPQE_CMD_ID};\n\n\n/*\n * eth tpa update command\n */\nenum eth_tpa_update_command\n{\n\tTPA_UPDATE_NONE_COMMAND /* nop command */,\n\tTPA_UPDATE_ENABLE_COMMAND /* enable command */,\n\tTPA_UPDATE_DISABLE_COMMAND /* disable command */,\n\tMAX_ETH_TPA_UPDATE_COMMAND};\n\n\n/*\n * In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header\n */\nenum eth_tunnel_lso_inc_ip_id\n{\n\tEXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */,\n\tINT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */,\n\tMAX_ETH_TUNNEL_LSO_INC_IP_ID};\n\n\n/*\n * In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD.\n */\nenum eth_tunnel_non_lso_csum_location\n{\n\tCSUM_ON_PKT /* checksum is on the packet. */,\n\tCSUM_ON_BD /* checksum is on the BD. */,\n\tMAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION};\n\n\n/*\n * Tx regular BD structure $$KEEP_ENDIANNESS$$\n */\nstruct eth_tx_bd\n{\n\tuint32_t addr_lo /* Single continuous buffer low pointer */;\n\tuint32_t addr_hi /* Single continuous buffer high pointer */;\n\tuint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */;\n\tuint16_t nbytes /* Size of the data represented by the BD */;\n\tuint8_t reserved[4] /* keeps same size as other eth tx bd types */;\n};\n\n\n/*\n * structure for easy accessibility to assembler\n */\nstruct eth_tx_bd_flags\n{\n\tuint8_t as_bitfield;\n#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield\tIP CKSUM flag,Relevant in START */\n#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0\n#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield\tL4 CKSUM flag,Relevant in START */\n#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1\n#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield\t00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */\n#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2\n#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield\tStart of packet BD */\n#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4\n#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield\tflag that indicates that the current packet is a udp packet */\n#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5\n#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield\tLSO flag, Relevant in START */\n#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6\n#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield\tset in case ipV6 packet, Relevant in START */\n#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7\n};\n\n/*\n * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$\n */\nstruct eth_tx_start_bd\n{\n\tuint64_t addr;\n\tuint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */;\n\tuint16_t nbytes /* Size of the data represented by the BD */;\n\tuint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */;\n\tstruct eth_tx_bd_flags bd_flags;\n\tuint8_t general_data;\n#define ETH_TX_START_BD_HDR_NBDS (0xF<<0) /* BitField general_data\tcontains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */\n#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0\n#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data\tforce vlan mode according to bds (vlan mode can change accroding to global configuration) */\n#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4\n#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data\tDetermines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */\n#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5\n#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data\tset in case of tunneling encapsulated packet */\n#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7\n};\n\n/*\n * Tx parsing BD structure for ETH E1h $$KEEP_ENDIANNESS$$\n */\nstruct eth_tx_parse_bd_e1x\n{\n\tuint16_t global_data;\n#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data\tIP header Offset in WORDs from start of packet */\n#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0\n#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data\tmarks ethernet address type (use enum eth_addr_type) */\n#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4\n#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data\t */\n#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6\n#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data\t */\n#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7\n#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data\tan optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */\n#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8\n#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data\treserved bit, should be set with 0 */\n#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9\n\tuint8_t tcp_flags;\n#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags\tEnd of data flag */\n#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0\n#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags\tSynchronize sequence numbers flag */\n#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1\n#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags\tReset connection flag */\n#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2\n#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags\tPush flag */\n#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3\n#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags\tAcknowledgment number valid flag */\n#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4\n#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags\tUrgent pointer valid flag */\n#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5\n#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags\tECN-Echo */\n#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6\n#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags\tCongestion Window Reduced */\n#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7\n\tuint8_t ip_hlen_w /* IP header length in WORDs */;\n\tuint16_t total_hlen_w /* IP+TCP+ETH */;\n\tuint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */;\n\tuint16_t lso_mss /* for LSO mode */;\n\tuint16_t ip_id /* for LSO mode */;\n\tuint32_t tcp_send_seq /* for LSO mode */;\n};\n\n/*\n * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$\n */\nstruct eth_tx_parse_bd_e2\n{\n\tunion eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */;\n\tuint32_t parsing_data;\n#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data\tTCP/UDP header Offset in WORDs from start of packet */\n#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0\n#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data\tTCP header size in DOUBLE WORDS */\n#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11\n#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data\ta flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */\n#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15\n#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data\tfor LSO mode */\n#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16\n#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data\tmarks ethernet address type (use enum eth_addr_type) */\n#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30\n};\n\n/*\n * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$\n */\nstruct eth_tx_parse_2nd_bd\n{\n\tuint16_t global_data;\n#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data\tOuter IP header offset in WORDs (16-bit) from start of packet */\n#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0\n#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data\tshould be set with 0 */\n#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4\n#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data\t */\n#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5\n#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data\tan optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */\n#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6\n#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data\tSet in case UDP header exists in tunnel outer hedears. */\n#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7\n#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data\tOuter IP header length in WORDs (16-bit). Valid only for IpV4. */\n#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8\n#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data\tshould be set with 0 */\n#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13\n\tuint16_t reserved2;\n\tuint8_t tcp_flags;\n#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags\tEnd of data flag */\n#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0\n#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags\tSynchronize sequence numbers flag */\n#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1\n#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags\tReset connection flag */\n#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2\n#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags\tPush flag */\n#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3\n#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags\tAcknowledgment number valid flag */\n#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4\n#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags\tUrgent pointer valid flag */\n#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5\n#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags\tECN-Echo */\n#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6\n#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags\tCongestion Window Reduced */\n#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7\n\tuint8_t reserved3;\n\tuint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */;\n\tuint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */;\n\tuint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */;\n\tuint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */;\n\tuint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */;\n};\n\n/*\n * The last BD in the BD memory will hold a pointer to the next BD memory\n */\nstruct eth_tx_next_bd\n{\n\tuint32_t addr_lo /* Single continuous buffer low pointer */;\n\tuint32_t addr_hi /* Single continuous buffer high pointer */;\n\tuint8_t reserved[8] /* keeps same size as other eth tx bd types */;\n};\n\n/*\n * union for 4 Bd types\n */\nunion eth_tx_bd_types\n{\n\tstruct eth_tx_start_bd start_bd /* the first bd in a packets */;\n\tstruct eth_tx_bd reg_bd /* the common bd */;\n\tstruct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */;\n\tstruct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */;\n\tstruct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */;\n\tstruct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */;\n};\n\n/*\n * array of 13 bds as appears in the eth xstorm context\n */\nstruct eth_tx_bds_array\n{\n\tunion eth_tx_bd_types bds[13];\n};\n\n\n/*\n * VLAN mode on TX BDs\n */\nenum eth_tx_vlan_type\n{\n\tX_ETH_NO_VLAN,\n\tX_ETH_OUTBAND_VLAN,\n\tX_ETH_INBAND_VLAN,\n\tX_ETH_FW_ADDED_VLAN /* Driver should not use this! */,\n\tMAX_ETH_TX_VLAN_TYPE};\n\n\n/*\n * Ethernet VLAN filtering mode in E1x\n */\nenum eth_vlan_filter_mode\n{\n\tETH_VLAN_FILTER_ANY_VLAN /* Dont filter by vlan */,\n\tETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */,\n\tETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */,\n\tMAX_ETH_VLAN_FILTER_MODE};\n\n\n/*\n * MAC filtering configuration command header $$KEEP_ENDIANNESS$$\n */\nstruct mac_configuration_hdr\n{\n\tuint8_t length /* number of entries valid in this command (6 bits) */;\n\tuint8_t offset /* offset of the first entry in the list */;\n\tuint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */;\n\tuint32_t echo /* echo value to be sent to driver on event ring */;\n};\n\n/*\n * MAC address in list for ramrod $$KEEP_ENDIANNESS$$\n */\nstruct mac_configuration_entry\n{\n\tuint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;\n\tuint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */;\n\tuint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;\n\tuint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */;\n\tuint8_t pf_id /* The pf id, for multi function mode */;\n\tuint8_t flags;\n#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags\tconfigures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */\n#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0\n#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags\tIf set, this MAC also belongs to RDMA client */\n#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1\n#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags\t (use enum eth_vlan_filter_mode) */\n#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2\n#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags\tBitField flags 0 - cant remove vlan 1 - can remove vlan. relevant only to everest1 */\n#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4\n#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags\tBitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */\n#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5\n#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags\t */\n#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6\n\tuint16_t reserved0;\n\tuint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */;\n};\n\n/*\n * MAC filtering configuration command\n */\nstruct mac_configuration_cmd\n{\n\tstruct mac_configuration_hdr hdr /* header */;\n\tstruct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */;\n};\n\n\n/*\n * Set-MAC command type (in E1x)\n */\nenum set_mac_action_type\n{\n\tT_ETH_MAC_COMMAND_INVALIDATE,\n\tT_ETH_MAC_COMMAND_SET,\n\tMAX_SET_MAC_ACTION_TYPE};\n\n\n/*\n * Ethernet TPA Modes\n */\nenum tpa_mode\n{\n\tTPA_LRO /* LRO mode TPA */,\n\tTPA_GRO /* GRO mode TPA */,\n\tMAX_TPA_MODE};\n\n\n/*\n * tpa update ramrod data $$KEEP_ENDIANNESS$$\n */\nstruct tpa_update_ramrod_data\n{\n\tuint8_t update_ipv4 /* none, enable or disable */;\n\tuint8_t update_ipv6 /* none, enable or disable */;\n\tuint8_t client_id /* client init flow control data */;\n\tuint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;\n\tuint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;\n\tuint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */;\n\tuint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;\n\tuint8_t tpa_mode /* TPA mode to use (LRO or GRO) */;\n\tuint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;\n\tuint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;\n\tuint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */;\n\tuint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */;\n\tuint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;\n\tuint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;\n};\n\n\n/*\n * approximate-match multicast filtering for E1H per function in Tstorm\n */\nstruct tstorm_eth_approximate_match_multicast_filtering\n{\n\tuint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */;\n};\n\n\n/*\n * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$\n */\nstruct tstorm_eth_function_common_config\n{\n\tuint16_t config_flags;\n#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags\tconfiguration of the port RSS IpV4 2-tupple capability */\n#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0\n#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags\tconfiguration of the port RSS IpV4 4-tupple capability */\n#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1\n#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags\tconfiguration of the port RSS IpV4 2-tupple capability */\n#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2\n#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags\tconfiguration of the port RSS IpV6 4-tupple capability */\n#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3\n#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags\tRSS mode of operation (use enum eth_rss_mode) */\n#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4\n#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags\t0 - Dont filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */\n#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7\n#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags\t */\n#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8\n\tuint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;\n\tuint8_t reserved1;\n\tuint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */;\n};\n\n\n/*\n * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$\n */\nstruct tstorm_eth_mac_filter_config\n{\n\tuint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */;\n\tuint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */;\n\tuint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */;\n\tuint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */;\n\tuint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */;\n\tuint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. The primary vlan is taken from the CAM target table. */;\n\tuint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */;\n};\n\n\n/*\n * tx only queue init ramrod data $$KEEP_ENDIANNESS$$\n */\nstruct tx_queue_init_ramrod_data\n{\n\tstruct client_init_general_data general /* client init general data */;\n\tstruct client_init_tx_data tx /* client init tx data */;\n};\n\n\n/*\n * Three RX producers for ETH\n */\nunion ustorm_eth_rx_producers\n{\n\tstruct {\n#if defined(__BIG_ENDIAN)\n\t\tuint16_t bd_prod /* Producer of the RX BD ring */;\n\t\tuint16_t cqe_prod /* Producer of the RX CQE ring */;\n#elif defined(__LITTLE_ENDIAN)\n\t\tuint16_t cqe_prod /* Producer of the RX CQE ring */;\n\t\tuint16_t bd_prod /* Producer of the RX BD ring */;\n#endif\n#if defined(__BIG_ENDIAN)\n\t\tuint16_t reserved;\n\t\tuint16_t sge_prod /* Producer of the RX SGE ring */;\n#elif defined(__LITTLE_ENDIAN)\n\t\tuint16_t sge_prod /* Producer of the RX SGE ring */;\n\t\tuint16_t reserved;\n#endif\n\t} prod;\n\tuint32_t raw_data[2];\n};\n\n\n/*\n * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$\n */\nstruct afex_vif_list_ramrod_data\n{\n\tuint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */;\n\tuint8_t func_bit_map /* the function bit map to set */;\n\tuint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */;\n\tuint8_t func_to_clear /* the func id to clear in case of clear func mode */;\n\tuint8_t echo;\n\tuint16_t reserved1;\n};\n\n\n/*\n * cfc delete event data $$KEEP_ENDIANNESS$$\n */\nstruct cfc_del_event_data\n{\n\tuint32_t cid /* cid of deleted connection */;\n\tuint32_t reserved0;\n\tuint32_t reserved1;\n};\n\n\n/*\n * per-port SAFC demo variables\n */\nstruct cmng_flags_per_port\n{\n\tuint32_t cmng_enables;\n#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes\tif set, enable fairness between vnics */\n#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0\n#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes\tif set, enable rate shaping between vnics */\n#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1\n#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes\tif set, enable fairness between COSes */\n#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2\n#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes\t (use enum fairness_mode) */\n#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3\n#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes\treserved */\n#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4\n\tuint32_t __reserved1;\n};\n\n\n/*\n * per-port rate shaping variables\n */\nstruct rate_shaping_vars_per_port\n{\n\tuint32_t rs_periodic_timeout /* timeout of periodic timer */;\n\tuint32_t rs_threshold /* threshold, below which we start to stop queues */;\n};\n\n/*\n * per-port fairness variables\n */\nstruct fairness_vars_per_port\n{\n\tuint32_t upper_bound /* Quota for a protocol/vnic */;\n\tuint32_t fair_threshold /* almost-empty threshold */;\n\tuint32_t fairness_timeout /* timeout of fairness timer */;\n\tuint32_t reserved0;\n};\n\n/*\n * per-port SAFC variables\n */\nstruct safc_struct_per_port\n{\n#if defined(__BIG_ENDIAN)\n\tuint16_t __reserved1;\n\tuint8_t __reserved0;\n\tuint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;\n\tuint8_t __reserved0;\n\tuint16_t __reserved1;\n#endif\n\tuint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */;\n\tuint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */;\n};\n\n/*\n * Per-port congestion management variables\n */\nstruct cmng_struct_per_port\n{\n\tstruct rate_shaping_vars_per_port rs_vars;\n\tstruct fairness_vars_per_port fair_vars;\n\tstruct safc_struct_per_port safc_vars;\n\tstruct cmng_flags_per_port flags;\n};\n\n/*\n * a single rate shaping counter. can be used as protocol or vnic counter\n */\nstruct rate_shaping_counter\n{\n\tuint32_t quota /* Quota for a protocol/vnic */;\n#if defined(__BIG_ENDIAN)\n\tuint16_t __reserved0;\n\tuint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;\n\tuint16_t __reserved0;\n#endif\n};\n\n/*\n * per-vnic rate shaping variables\n */\nstruct rate_shaping_vars_per_vn\n{\n\tstruct rate_shaping_counter vn_counter /* per-vnic counter */;\n};\n\n/*\n * per-vnic fairness variables\n */\nstruct fairness_vars_per_vn\n{\n\tuint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */;\n\tuint32_t vn_credit_delta /* used for incrementing the credit */;\n\tuint32_t __reserved0;\n};\n\n/*\n * cmng port init state\n */\nstruct cmng_vnic\n{\n\tstruct rate_shaping_vars_per_vn vnic_max_rate[4];\n\tstruct fairness_vars_per_vn vnic_min_rate[4];\n};\n\n/*\n * cmng port init state\n */\nstruct cmng_init\n{\n\tstruct cmng_struct_per_port port;\n\tstruct cmng_vnic vnic;\n};\n\n\n/*\n * driver parameters for congestion management init, all rates are in Mbps\n */\nstruct cmng_init_input\n{\n\tuint32_t port_rate;\n\tuint16_t vnic_min_rate[4] /* rates are in Mbps */;\n\tuint16_t vnic_max_rate[4] /* rates are in Mbps */;\n\tuint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */;\n\tuint16_t cos_to_pause_mask[MAX_COS_NUMBER];\n\tstruct cmng_flags_per_port flags;\n};\n\n\n/*\n * Protocol-common command ID for slow path elements\n */\nenum common_spqe_cmd_id\n{\n\tRAMROD_CMD_ID_COMMON_UNUSED,\n\tRAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */,\n\tRAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */,\n\tRAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */,\n\tRAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */,\n\tRAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,\n\tRAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */,\n\tRAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,\n\tRAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,\n\tRAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */,\n\tRAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,\n\tMAX_COMMON_SPQE_CMD_ID};\n\n\n/*\n * Per-protocol connection types\n */\nenum connection_type\n{\n\tETH_CONNECTION_TYPE /* Ethernet */,\n\tTOE_CONNECTION_TYPE /* TOE */,\n\tRDMA_CONNECTION_TYPE /* RDMA */,\n\tISCSI_CONNECTION_TYPE /* iSCSI */,\n\tFCOE_CONNECTION_TYPE /* FCoE */,\n\tRESERVED_CONNECTION_TYPE_0,\n\tRESERVED_CONNECTION_TYPE_1,\n\tRESERVED_CONNECTION_TYPE_2,\n\tNONE_CONNECTION_TYPE /* General- used for common slow path */,\n\tMAX_CONNECTION_TYPE};\n\n\n/*\n * Cos modes\n */\nenum cos_mode\n{\n\tOVERRIDE_COS /* Firmware deduce cos according to DCB */,\n\tSTATIC_COS /* Firmware has constant queues per CoS */,\n\tFW_WRR /* Firmware keep fairness between different CoSes */,\n\tMAX_COS_MODE};\n\n\n/*\n * Dynamic HC counters set by the driver\n */\nstruct hc_dynamic_drv_counter\n{\n\tuint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */;\n};\n\n/*\n * zone A per-queue data\n */\nstruct cstorm_queue_zone_data\n{\n\tstruct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */;\n\tstruct regpair reserved[2];\n};\n\n\n/*\n * Vf-PF channel data in cstorm ram (non-triggered zone)\n */\nstruct vf_pf_channel_zone_data\n{\n\tuint32_t msg_addr_lo /* the message address on VF memory */;\n\tuint32_t msg_addr_hi /* the message address on VF memory */;\n};\n\n/*\n * zone for VF non-triggered data\n */\nstruct non_trigger_vf_zone\n{\n\tstruct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */;\n};\n\n/*\n * Vf-PF channel trigger zone in cstorm ram\n */\nstruct vf_pf_channel_zone_trigger\n{\n\tuint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */;\n};\n\n/*\n * zone that triggers the in-bound interrupt\n */\nstruct trigger_vf_zone\n{\n#if defined(__BIG_ENDIAN)\n\tuint16_t reserved1;\n\tuint8_t reserved0;\n\tstruct vf_pf_channel_zone_trigger vf_pf_channel;\n#elif defined(__LITTLE_ENDIAN)\n\tstruct vf_pf_channel_zone_trigger vf_pf_channel;\n\tuint8_t reserved0;\n\tuint16_t reserved1;\n#endif\n\tuint32_t reserved2;\n};\n\n/*\n * zone B per-VF data\n */\nstruct cstorm_vf_zone_data\n{\n\tstruct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */;\n\tstruct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */;\n};\n\n\n/*\n * Dynamic host coalescing init parameters, per state machine\n */\nstruct dynamic_hc_sm_config\n{\n\tuint32_t threshold[3] /* thresholds of number of outstanding bytes */;\n\tuint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */;\n\tuint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */;\n\tuint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */;\n\tuint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */;\n\tuint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */;\n};\n\n/*\n * Dynamic host coalescing init parameters\n */\nstruct dynamic_hc_config\n{\n\tstruct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */;\n};\n\n\nstruct e2_integ_data\n{\n#if defined(__BIG_ENDIAN)\n\tuint8_t flags;\n#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags\tintegration testing enabled */\n#define E2_INTEG_DATA_TESTING_EN_SHIFT 0\n#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags\tflag indicating this connection will transmit on loopback */\n#define E2_INTEG_DATA_LB_TX_SHIFT 1\n#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags\tflag indicating this connection will transmit according to cos field */\n#define E2_INTEG_DATA_COS_TX_SHIFT 2\n#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags\tflag indicating this connection will activate the opportunistic QM credit flow */\n#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3\n#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags\tflag indicating this connection will release the door bell queue (DQ) */\n#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4\n#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags\t */\n#define E2_INTEG_DATA_RESERVED_SHIFT 5\n\tuint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;\n\tuint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;\n\tuint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;\n\tuint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;\n\tuint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;\n\tuint8_t flags;\n#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags\tintegration testing enabled */\n#define E2_INTEG_DATA_TESTING_EN_SHIFT 0\n#define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags\tflag indicating this connection will transmit on loopback */\n#define E2_INTEG_DATA_LB_TX_SHIFT 1\n#define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags\tflag indicating this connection will transmit according to cos field */\n#define E2_INTEG_DATA_COS_TX_SHIFT 2\n#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags\tflag indicating this connection will activate the opportunistic QM credit flow */\n#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3\n#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags\tflag indicating this connection will release the door bell queue (DQ) */\n#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4\n#define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags\t */\n#define E2_INTEG_DATA_RESERVED_SHIFT 5\n#endif\n#if defined(__BIG_ENDIAN)\n\tuint16_t reserved3;\n\tuint8_t reserved2;\n\tuint8_t ramEn /* context area reserved for reading enable bit from ram */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t ramEn /* context area reserved for reading enable bit from ram */;\n\tuint8_t reserved2;\n\tuint16_t reserved3;\n#endif\n};\n\n\n/*\n * set mac event data $$KEEP_ENDIANNESS$$\n */\nstruct eth_event_data\n{\n\tuint32_t echo /* set mac echo data to return to driver */;\n\tuint32_t reserved0;\n\tuint32_t reserved1;\n};\n\n\n/*\n * pf-vf event data $$KEEP_ENDIANNESS$$\n */\nstruct vf_pf_event_data\n{\n\tuint8_t vf_id /* VF ID (0-63) */;\n\tuint8_t reserved0;\n\tuint16_t reserved1;\n\tuint32_t msg_addr_lo /* message address on Vf (low 32 bits) */;\n\tuint32_t msg_addr_hi /* message address on Vf (high 32 bits) */;\n};\n\n/*\n * VF FLR event data $$KEEP_ENDIANNESS$$\n */\nstruct vf_flr_event_data\n{\n\tuint8_t vf_id /* VF ID (0-63) */;\n\tuint8_t reserved0;\n\tuint16_t reserved1;\n\tuint32_t reserved2;\n\tuint32_t reserved3;\n};\n\n/*\n * malicious VF event data $$KEEP_ENDIANNESS$$\n */\nstruct malicious_vf_event_data\n{\n\tuint8_t vf_id /* VF ID (0-63) */;\n\tuint8_t err_id /* reason for malicious notification */;\n\tuint16_t reserved1;\n\tuint32_t reserved2;\n\tuint32_t reserved3;\n};\n\n/*\n * vif list event data $$KEEP_ENDIANNESS$$\n */\nstruct vif_list_event_data\n{\n\tuint8_t func_bit_map /* bit map of pf indice */;\n\tuint8_t echo;\n\tuint16_t reserved0;\n\tuint32_t reserved1;\n\tuint32_t reserved2;\n};\n\n/*\n * function update event data $$KEEP_ENDIANNESS$$\n */\nstruct function_update_event_data\n{\n\tuint8_t echo;\n\tuint8_t reserved;\n\tuint16_t reserved0;\n\tuint32_t reserved1;\n\tuint32_t reserved2;\n};\n\n/*\n * union for all event ring message types\n */\nunion event_data\n{\n\tstruct vf_pf_event_data vf_pf_event /* vf-pf event data */;\n\tstruct eth_event_data eth_event /* set mac event data */;\n\tstruct cfc_del_event_data cfc_del_event /* cfc delete event data */;\n\tstruct vf_flr_event_data vf_flr_event /* vf flr event data */;\n\tstruct malicious_vf_event_data malicious_vf_event /* malicious vf event data */;\n\tstruct vif_list_event_data vif_list_event /* vif list event data */;\n\tstruct function_update_event_data function_update_event /* function update event data */;\n};\n\n\n/*\n * per PF event ring data\n */\nstruct event_ring_data\n{\n\tstruct regpair_native base_addr /* ring base address */;\n#if defined(__BIG_ENDIAN)\n\tuint8_t index_id /* index ID within the status block */;\n\tuint8_t sb_id /* status block ID */;\n\tuint16_t producer /* event ring producer */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint16_t producer /* event ring producer */;\n\tuint8_t sb_id /* status block ID */;\n\tuint8_t index_id /* index ID within the status block */;\n#endif\n\tuint32_t reserved0;\n};\n\n\n/*\n * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$\n */\nstruct event_ring_msg\n{\n\tuint8_t opcode;\n\tuint8_t error /* error on the mesasage */;\n\tuint16_t reserved1;\n\tunion event_data data /* message data (96 bits data) */;\n};\n\n/*\n * event ring next page element (128 bits)\n */\nstruct event_ring_next\n{\n\tstruct regpair addr /* Address of the next page of the ring */;\n\tuint32_t reserved[2];\n};\n\n/*\n * union for event ring element types (each element is 128 bits)\n */\nunion event_ring_elem\n{\n\tstruct event_ring_msg message /* event ring message */;\n\tstruct event_ring_next next_page /* event ring next page */;\n};\n\n\n/*\n * Common event ring opcodes\n */\nenum event_ring_opcode\n{\n\tEVENT_RING_OPCODE_VF_PF_CHANNEL,\n\tEVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */,\n\tEVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */,\n\tEVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */,\n\tEVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,\n\tEVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */,\n\tEVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,\n\tEVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,\n\tEVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */,\n\tEVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */,\n\tEVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */,\n\tEVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */,\n\tEVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */,\n\tEVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */,\n\tEVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */,\n\tEVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */,\n\tEVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,\n\tEVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,\n\tEVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,\n\tMAX_EVENT_RING_OPCODE};\n\n\n/*\n * Modes for fairness algorithm\n */\nenum fairness_mode\n{\n\tFAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */,\n\tFAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */,\n\tMAX_FAIRNESS_MODE};\n\n\n/*\n * Priority and cos $$KEEP_ENDIANNESS$$\n */\nstruct priority_cos\n{\n\tuint8_t priority /* Priority */;\n\tuint8_t cos /* Cos */;\n\tuint16_t reserved1;\n};\n\n/*\n * The data for flow control configuration $$KEEP_ENDIANNESS$$\n */\nstruct flow_control_configuration\n{\n\tstruct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */;\n\tuint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */;\n\tuint8_t dcb_version /* DCB version Increase by one on each DCB update */;\n\tuint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */;\n\tuint8_t reserved1;\n\tuint32_t reserved2;\n};\n\n\n/*\n * $$KEEP_ENDIANNESS$$\n */\nstruct function_start_data\n{\n\tuint8_t function_mode /* the function mode */;\n\tuint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independant function mode. (E2/E3 Only) */;\n\tuint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */;\n\tuint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;\n\tuint8_t path_id;\n\tuint8_t network_cos_mode /* The cos mode for network traffic. */;\n\tuint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */;\n\tuint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;\n\tuint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;\n\tuint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;\n\tuint16_t reserved1[2];\n};\n\n\n/*\n * $$KEEP_ENDIANNESS$$\n */\nstruct function_update_data\n{\n\tuint8_t vif_id_change_flg /* If set, vif_id will be checked */;\n\tuint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */;\n\tuint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */;\n\tuint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */;\n\tuint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;\n\tuint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */;\n\tuint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */;\n\tuint8_t network_cos_mode /* The cos mode for network traffic. */;\n\tuint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */;\n\tuint8_t lb_mode_en /* If set, niv loopback mode will be enabled */;\n\tuint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */;\n\tuint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */;\n\tuint8_t echo;\n\tuint8_t reserved1;\n\tuint8_t update_gre_cfg_flg /* If set, GRE config for the function will be updated according to the gre_tunnel_rss and nvgre_clss_en fields */;\n\tuint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */;\n\tuint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */;\n\tuint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */;\n\tuint32_t reserved3;\n};\n\n\n/*\n * FW version stored in the Xstorm RAM\n */\nstruct fw_version\n{\n#if defined(__BIG_ENDIAN)\n\tuint8_t engineering /* firmware current engineering version */;\n\tuint8_t revision /* firmware current revision version */;\n\tuint8_t minor /* firmware current minor version */;\n\tuint8_t major /* firmware current major version */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t major /* firmware current major version */;\n\tuint8_t minor /* firmware current minor version */;\n\tuint8_t revision /* firmware current revision version */;\n\tuint8_t engineering /* firmware current engineering version */;\n#endif\n\tuint32_t flags;\n#define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags\tif set, this is optimized ASM */\n#define FW_VERSION_OPTIMIZED_SHIFT 0\n#define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags\tif set, this is big-endien ASM */\n#define FW_VERSION_BIG_ENDIEN_SHIFT 1\n#define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags\t1 - E1H */\n#define FW_VERSION_CHIP_VERSION_SHIFT 2\n#define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags\t */\n#define __FW_VERSION_RESERVED_SHIFT 4\n};\n\n\n/*\n * GRE RSS Mode\n */\nenum gre_rss_mode\n{\n\tGRE_OUTER_HEADERS_RSS /* RSS for GRE Packets is performed on the outer headers */,\n\tGRE_INNER_HEADERS_RSS /* RSS for GRE Packets is performed on the inner headers */,\n\tNVGRE_KEY_ENTROPY_RSS /* RSS for NVGRE Packets is done based on a hash containing the entropy bits from the GRE Key Field (gre_tunnel must be NVGRE_TUNNEL) */,\n\tMAX_GRE_RSS_MODE};\n\n\n/*\n * GRE Tunnel Mode\n */\nenum gre_tunnel_type\n{\n\tNO_GRE_TUNNEL,\n\tNVGRE_TUNNEL /* NV-GRE Tunneling Microsoft L2 over GRE. GRE header contains mandatory Key Field. */,\n\tL2GRE_TUNNEL /* L2-GRE Tunneling General L2 over GRE. GRE can contain Key field with Tenant ID and Sequence Field */,\n\tIPGRE_TUNNEL /* IP-GRE Tunneling IP over GRE. GRE may contain Key field with Tenant ID, Sequence Field and/or Checksum Field */,\n\tMAX_GRE_TUNNEL_TYPE};\n\n\n/*\n * Dynamic Host-Coalescing - Driver(host) counters\n */\nstruct hc_dynamic_sb_drv_counters\n{\n\tuint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */;\n};\n\n\n/*\n * 2 bytes. configuration/state parameters for a single protocol index\n */\nstruct hc_index_data\n{\n#if defined(__BIG_ENDIAN)\n\tuint8_t flags;\n#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags\tIndex to a state machine. Can be 0 or 1 */\n#define HC_INDEX_DATA_SM_ID_SHIFT 0\n#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags\tif set, host coalescing would be done for this index */\n#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1\n#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags\tif set, dynamic HC will be done for this index */\n#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2\n#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags\t */\n#define HC_INDEX_DATA_RESERVE_SHIFT 3\n\tuint8_t timeout /* the timeout values for this index. Units are 4 usec */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t timeout /* the timeout values for this index. Units are 4 usec */;\n\tuint8_t flags;\n#define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags\tIndex to a state machine. Can be 0 or 1 */\n#define HC_INDEX_DATA_SM_ID_SHIFT 0\n#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags\tif set, host coalescing would be done for this index */\n#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1\n#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags\tif set, dynamic HC will be done for this index */\n#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2\n#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags\t */\n#define HC_INDEX_DATA_RESERVE_SHIFT 3\n#endif\n};\n\n\n/*\n * HC state-machine\n */\nstruct hc_status_block_sm\n{\n#if defined(__BIG_ENDIAN)\n\tuint8_t igu_seg_id;\n\tuint8_t igu_sb_id /* sb_id within the IGU */;\n\tuint8_t timer_value /* Determines the time_to_expire */;\n\tuint8_t __flags;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t __flags;\n\tuint8_t timer_value /* Determines the time_to_expire */;\n\tuint8_t igu_sb_id /* sb_id within the IGU */;\n\tuint8_t igu_seg_id;\n#endif\n\tuint32_t time_to_expire /* The time in which it expects to wake up */;\n};\n\n/*\n * hold PCI identification variables- used in various places in firmware\n */\nstruct pci_entity\n{\n#if defined(__BIG_ENDIAN)\n\tuint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;\n\tuint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;\n\tuint8_t vnic_id /* Virtual NIC ID (0-3) */;\n\tuint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;\n\tuint8_t vnic_id /* Virtual NIC ID (0-3) */;\n\tuint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;\n\tuint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;\n#endif\n};\n\n/*\n * The fast-path status block meta-data, common to all chips\n */\nstruct hc_sb_data\n{\n\tstruct regpair_native host_sb_addr /* Host status block address */;\n\tstruct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */;\n\tstruct pci_entity p_func /* vnic / port of the status block to be set by the driver */;\n#if defined(__BIG_ENDIAN)\n\tuint8_t rsrv0;\n\tuint8_t state;\n\tuint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;\n\tuint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;\n\tuint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;\n\tuint8_t state;\n\tuint8_t rsrv0;\n#endif\n\tstruct regpair_native rsrv1[2];\n};\n\n\n/*\n * Segment types for host coaslescing\n */\nenum hc_segment\n{\n\tHC_REGULAR_SEGMENT,\n\tHC_DEFAULT_SEGMENT,\n\tMAX_HC_SEGMENT};\n\n\n/*\n * The fast-path status block meta-data\n */\nstruct hc_sp_status_block_data\n{\n\tstruct regpair_native host_sb_addr /* Host status block address */;\n#if defined(__BIG_ENDIAN)\n\tuint8_t rsrv1;\n\tuint8_t state;\n\tuint8_t igu_seg_id /* segment id of the IGU */;\n\tuint8_t igu_sb_id /* sb_id within the IGU */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t igu_sb_id /* sb_id within the IGU */;\n\tuint8_t igu_seg_id /* segment id of the IGU */;\n\tuint8_t state;\n\tuint8_t rsrv1;\n#endif\n\tstruct pci_entity p_func /* vnic / port of the status block to be set by the driver */;\n};\n\n\n/*\n * The fast-path status block meta-data\n */\nstruct hc_status_block_data_e1x\n{\n\tstruct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */;\n\tstruct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;\n};\n\n\n/*\n * The fast-path status block meta-data\n */\nstruct hc_status_block_data_e2\n{\n\tstruct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */;\n\tstruct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;\n};\n\n\n/*\n * IGU block operartion modes (in Everest2)\n */\nenum igu_mode\n{\n\tHC_IGU_BC_MODE /* Backward compatible mode */,\n\tHC_IGU_NBC_MODE /* Non-backward compatible mode */,\n\tMAX_IGU_MODE};\n\n\n/*\n * IP versions\n */\nenum ip_ver\n{\n\tIP_V4,\n\tIP_V6,\n\tMAX_IP_VER};\n\n\n/*\n * Malicious VF error ID\n */\nenum malicious_vf_error_id\n{\n\tVF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */,\n\tETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */,\n\tETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */,\n\tETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */,\n\tETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */,\n\tETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */,\n\tETH_TOO_MANY_BDS /* Tx packet has too many BDs */,\n\tETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */,\n\tETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */,\n\tETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */,\n\tETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */,\n\tETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */,\n\tETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */,\n\tETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */,\n\tMAX_MALICIOUS_VF_ERROR_ID};\n\n\n/*\n * Multi-function modes\n */\nenum mf_mode\n{\n\tSINGLE_FUNCTION,\n\tMULTI_FUNCTION_SD /* Switch dependent (vlan based) */,\n\tMULTI_FUNCTION_SI /* Switch independent (mac based) */,\n\tMULTI_FUNCTION_AFEX /* Switch dependent (niv based) */,\n\tMAX_MF_MODE};\n\n\n/*\n * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$\n */\nstruct tstorm_per_pf_stats\n{\n\tstruct regpair rcv_error_bytes /* number of bytes received with errors */;\n};\n\n/*\n * $$KEEP_ENDIANNESS$$\n */\nstruct per_pf_stats\n{\n\tstruct tstorm_per_pf_stats tstorm_pf_statistics;\n};\n\n\n/*\n * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$\n */\nstruct tstorm_per_port_stats\n{\n\tuint32_t mac_discard /* number of packets with mac errors */;\n\tuint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */;\n\tuint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */;\n\tuint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */;\n\tuint32_t packet_drop /* general packet drop conter- incremented for every packet drop */;\n\tuint32_t reserved;\n};\n\n/*\n * $$KEEP_ENDIANNESS$$\n */\nstruct per_port_stats\n{\n\tstruct tstorm_per_port_stats tstorm_port_statistics;\n};\n\n\n/*\n * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$\n */\nstruct tstorm_per_queue_stats\n{\n\tstruct regpair rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */;\n\tuint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */;\n\tuint32_t checksum_discard /* number of total packets received with checksum error */;\n\tstruct regpair rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */;\n\tuint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */;\n\tuint32_t pkts_too_big_discard /* number of too long packets received */;\n\tstruct regpair rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */;\n\tuint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */;\n\tuint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */;\n\tuint16_t no_buff_discard;\n\tuint16_t reserved0;\n\tuint32_t reserved1;\n};\n\n/*\n * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$\n */\nstruct ustorm_per_queue_stats\n{\n\tstruct regpair ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */;\n\tstruct regpair mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */;\n\tstruct regpair bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */;\n\tuint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;\n\tuint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;\n\tuint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;\n\tuint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */;\n\tstruct regpair coalesced_bytes /* the number of bytes coalesced in all aggregations */;\n\tuint32_t coalesced_events /* the number of aggregations */;\n\tuint32_t coalesced_aborts /* the number of exception which avoid aggregation */;\n};\n\n/*\n * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$\n */\nstruct xstorm_per_queue_stats\n{\n\tstruct regpair ucast_bytes_sent /* number of total bytes sent without errors */;\n\tstruct regpair mcast_bytes_sent /* number of total bytes sent without errors */;\n\tstruct regpair bcast_bytes_sent /* number of total bytes sent without errors */;\n\tuint32_t ucast_pkts_sent /* number of total packets sent without errors */;\n\tuint32_t mcast_pkts_sent /* number of total packets sent without errors */;\n\tuint32_t bcast_pkts_sent /* number of total packets sent without errors */;\n\tuint32_t error_drop_pkts /* number of total packets drooped due to errors */;\n};\n\n/*\n * $$KEEP_ENDIANNESS$$\n */\nstruct per_queue_stats\n{\n\tstruct tstorm_per_queue_stats tstorm_queue_statistics;\n\tstruct ustorm_per_queue_stats ustorm_queue_statistics;\n\tstruct xstorm_per_queue_stats xstorm_queue_statistics;\n};\n\n\n/*\n * FW version stored in first line of pram $$KEEP_ENDIANNESS$$\n */\nstruct pram_fw_version\n{\n\tuint8_t major /* firmware current major version */;\n\tuint8_t minor /* firmware current minor version */;\n\tuint8_t revision /* firmware current revision version */;\n\tuint8_t engineering /* firmware current engineering version */;\n\tuint8_t flags;\n#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags\tif set, this is optimized ASM */\n#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0\n#define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags\tstorm_id identification */\n#define PRAM_FW_VERSION_STORM_ID_SHIFT 1\n#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags\tif set, this is big-endien ASM */\n#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3\n#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 1 - E1H */\n#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4\n#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags\t */\n#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6\n};\n\n\n/*\n * Ethernet slow path element\n */\nunion protocol_common_specific_data\n{\n\tuint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;\n\tstruct regpair phy_address /* SPE physical address */;\n\tstruct regpair mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */;\n\tstruct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */;\n};\n\n/*\n * The send queue element\n */\nstruct protocol_common_spe\n{\n\tstruct spe_hdr hdr /* SPE header */;\n\tunion protocol_common_specific_data data /* data specific to common protocol */;\n};\n\n\n/*\n * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$\n */\nstruct set_timesync_ramrod_data\n{\n\tuint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */;\n\tuint8_t offset_cmd /* Timesync Offset Command */;\n\tuint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */;\n\tuint8_t drift_adjust_value /* Drift Adjust Value (in ns) */;\n\tuint32_t drift_adjust_period /* Drift Adjust Period (in us) */;\n\tstruct regpair offset_delta /* Timesync Offset Delta (in ns) */;\n};\n\n\n/*\n * The send queue element\n */\nstruct slow_path_element\n{\n\tstruct spe_hdr hdr /* common data for all protocols */;\n\tstruct regpair protocol_data /* additional data specific to the protocol */;\n};\n\n\n/*\n * Protocol-common statistics counter $$KEEP_ENDIANNESS$$\n */\nstruct stats_counter\n{\n\tuint16_t xstats_counter /* xstorm statistics counter */;\n\tuint16_t reserved0;\n\tuint32_t reserved1;\n\tuint16_t tstats_counter /* tstorm statistics counter */;\n\tuint16_t reserved2;\n\tuint32_t reserved3;\n\tuint16_t ustats_counter /* ustorm statistics counter */;\n\tuint16_t reserved4;\n\tuint32_t reserved5;\n\tuint16_t cstats_counter /* ustorm statistics counter */;\n\tuint16_t reserved6;\n\tuint32_t reserved7;\n};\n\n\n/*\n * $$KEEP_ENDIANNESS$$\n */\nstruct stats_query_entry\n{\n\tuint8_t kind;\n\tuint8_t index /* queue index */;\n\tuint16_t funcID /* the func the statistic will send to */;\n\tuint32_t reserved;\n\tstruct regpair address /* pxp address */;\n};\n\n/*\n * statistic command $$KEEP_ENDIANNESS$$\n */\nstruct stats_query_cmd_group\n{\n\tstruct stats_query_entry query[STATS_QUERY_CMD_COUNT];\n};\n\n\n/*\n * statistic command header $$KEEP_ENDIANNESS$$\n */\nstruct stats_query_header\n{\n\tuint8_t cmd_num /* command number */;\n\tuint8_t reserved0;\n\tuint16_t drv_stats_counter;\n\tuint32_t reserved1;\n\tstruct regpair stats_counters_addrs /* stats counter */;\n};\n\n\n/*\n * Types of statistcis query entry\n */\nenum stats_query_type\n{\n\tSTATS_TYPE_QUEUE,\n\tSTATS_TYPE_PORT,\n\tSTATS_TYPE_PF,\n\tSTATS_TYPE_TOE,\n\tSTATS_TYPE_FCOE,\n\tMAX_STATS_QUERY_TYPE};\n\n\n/*\n * Indicate of the function status block state\n */\nenum status_block_state\n{\n\tSB_DISABLED,\n\tSB_ENABLED,\n\tSB_CLEANED,\n\tMAX_STATUS_BLOCK_STATE};\n\n\n/*\n * Storm IDs (including attentions for IGU related enums)\n */\nenum storm_id\n{\n\tUSTORM_ID,\n\tCSTORM_ID,\n\tXSTORM_ID,\n\tTSTORM_ID,\n\tATTENTION_ID,\n\tMAX_STORM_ID};\n\n\n/*\n * Taffic types used in ETS and flow control algorithms\n */\nenum traffic_type\n{\n\tLLFC_TRAFFIC_TYPE_NW /* Networking */,\n\tLLFC_TRAFFIC_TYPE_FCOE /* FCoE */,\n\tLLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */,\n\tMAX_TRAFFIC_TYPE};\n\n\n/*\n * zone A per-queue data\n */\nstruct tstorm_queue_zone_data\n{\n\tstruct regpair reserved[4];\n};\n\n\n/*\n * zone B per-VF data\n */\nstruct tstorm_vf_zone_data\n{\n\tstruct regpair reserved;\n};\n\n\n/*\n * Add or Subtract Value for Set Timesync Ramrod\n */\nenum ts_add_sub_value\n{\n\tTS_SUB_VALUE /* Subtract Value */,\n\tTS_ADD_VALUE /* Add Value */,\n\tMAX_TS_ADD_SUB_VALUE};\n\n\n/*\n * Drift-Adjust Commands for Set Timesync Ramrod\n */\nenum ts_drift_adjust_cmd\n{\n\tTS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */,\n\tTS_DRIFT_ADJUST_SET /* Set Drift-Adjust */,\n\tTS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */,\n\tMAX_TS_DRIFT_ADJUST_CMD};\n\n\n/*\n * Offset Commands for Set Timesync Ramrod\n */\nenum ts_offset_cmd\n{\n\tTS_OFFSET_KEEP /* Keep Offset at current values */,\n\tTS_OFFSET_INC /* Increase Offset by Offset Delta */,\n\tTS_OFFSET_DEC /* Decrease Offset by Offset Delta */,\n\tMAX_TS_OFFSET_CMD};\n\n\n/*\n * zone A per-queue data\n */\nstruct ustorm_queue_zone_data\n{\n\tunion ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */;\n\tstruct regpair reserved[3];\n};\n\n\n/*\n * zone B per-VF data\n */\nstruct ustorm_vf_zone_data\n{\n\tstruct regpair reserved;\n};\n\n\n/*\n * data per VF-PF channel\n */\nstruct vf_pf_channel_data\n{\n#if defined(__BIG_ENDIAN)\n\tuint16_t reserved0;\n\tuint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;\n\tuint8_t state /* channel state (ready / waiting for ack) */;\n#elif defined(__LITTLE_ENDIAN)\n\tuint8_t state /* channel state (ready / waiting for ack) */;\n\tuint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;\n\tuint16_t reserved0;\n#endif\n\tuint32_t reserved1;\n};\n\n\n/*\n * State of VF-PF channel\n */\nenum vf_pf_channel_state\n{\n\tVF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */,\n\tVF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */,\n\tMAX_VF_PF_CHANNEL_STATE};\n\n\n/*\n * vif_list_rule_kind\n */\nenum vif_list_rule_kind\n{\n\tVIF_LIST_RULE_SET,\n\tVIF_LIST_RULE_GET,\n\tVIF_LIST_RULE_CLEAR_ALL,\n\tVIF_LIST_RULE_CLEAR_FUNC,\n\tMAX_VIF_LIST_RULE_KIND};\n\n\n/*\n * zone A per-queue data\n */\nstruct xstorm_queue_zone_data\n{\n\tstruct regpair reserved[4];\n};\n\n\n/*\n * zone B per-VF data\n */\nstruct xstorm_vf_zone_data\n{\n\tstruct regpair reserved;\n};\n\n\n#endif /* ECORE_HSI_H */\n" }, { "path": "drivers/net/bnx2x/ecore_init.h", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ECORE_INIT_H\n#define ECORE_INIT_H\n\n/* Init operation types and structures */\nenum {\n\tOP_RD = 0x1,\t/* read a single register */\n\tOP_WR,\t\t/* write a single register */\n\tOP_SW,\t\t/* copy a string to the device */\n\tOP_ZR,\t\t/* clear memory */\n\tOP_ZP,\t\t/* unzip then copy with DMAE */\n\tOP_WR_64,\t/* write 64 bit pattern */\n\tOP_WB,\t\t/* copy a string using DMAE */\n\tOP_WB_ZR,\t/* Clear a string using DMAE or indirect-wr */\n\tOP_IF_MODE_OR, /* Skip the following ops if all init modes don't match */\n\tOP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */\n\tOP_IF_PHASE,\n\tOP_RT,\n\tOP_DELAY,\n\tOP_VERIFY,\n\tOP_MAX\n};\n\nenum {\n\tSTAGE_START,\n\tSTAGE_END,\n};\n\n/* Returns the index of start or end of a specific block stage in ops array*/\n#define BLOCK_OPS_IDX(block, stage, end) \\\n\t(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))\n\n\n/* structs for the various opcodes */\nstruct raw_op {\n\tuint32_t op:8;\n\tuint32_t offset:24;\n\tuint32_t raw_data;\n};\n\nstruct op_read {\n\tuint32_t op:8;\n\tuint32_t offset:24;\n\tuint32_t val;\n};\n\nstruct op_write {\n\tuint32_t op:8;\n\tuint32_t offset:24;\n\tuint32_t val;\n};\n\nstruct op_arr_write {\n\tuint32_t op:8;\n\tuint32_t offset:24;\n#ifdef __BIG_ENDIAN\n\tuint16_t data_len;\n\tuint16_t data_off;\n#else /* __LITTLE_ENDIAN */\n\tuint16_t data_off;\n\tuint16_t data_len;\n#endif\n};\n\nstruct op_zero {\n\tuint32_t op:8;\n\tuint32_t offset:24;\n\tuint32_t len;\n};\n\nstruct op_if_mode {\n\tuint32_t op:8;\n\tuint32_t cmd_offset:24;\n\tuint32_t mode_bit_map;\n};\n\nstruct op_if_phase {\n\tuint32_t op:8;\n\tuint32_t cmd_offset:24;\n\tuint32_t phase_bit_map;\n};\n\nstruct op_delay {\n\tuint32_t op:8;\n\tuint32_t reserved:24;\n\tuint32_t delay;\n};\n\nunion init_op {\n\tstruct op_read\t\tread;\n\tstruct op_write\t\twrite;\n\tstruct op_arr_write\tarr_wr;\n\tstruct op_zero\t\tzero;\n\tstruct raw_op\t\traw;\n\tstruct op_if_mode\tif_mode;\n\tstruct op_if_phase\tif_phase;\n\tstruct op_delay\t\tdelay;\n};\n\n\n/* Init Phases */\nenum {\n\tPHASE_COMMON,\n\tPHASE_PORT0,\n\tPHASE_PORT1,\n\tPHASE_PF0,\n\tPHASE_PF1,\n\tPHASE_PF2,\n\tPHASE_PF3,\n\tPHASE_PF4,\n\tPHASE_PF5,\n\tPHASE_PF6,\n\tPHASE_PF7,\n\tNUM_OF_INIT_PHASES\n};\n\n/* Init Modes */\nenum {\n\tMODE_ASIC = 0x00000001,\n\tMODE_FPGA = 0x00000002,\n\tMODE_EMUL = 0x00000004,\n\tMODE_E2 = 0x00000008,\n\tMODE_E3 = 0x00000010,\n\tMODE_PORT2 = 0x00000020,\n\tMODE_PORT4 = 0x00000040,\n\tMODE_SF = 0x00000080,\n\tMODE_MF = 0x00000100,\n\tMODE_MF_SD = 0x00000200,\n\tMODE_MF_SI = 0x00000400,\n\tMODE_MF_AFEX = 0x00000800,\n\tMODE_E3_A0 = 0x00001000,\n\tMODE_E3_B0 = 0x00002000,\n\tMODE_COS3 = 0x00004000,\n\tMODE_COS6 = 0x00008000,\n\tMODE_LITTLE_ENDIAN = 0x00010000,\n\tMODE_BIG_ENDIAN = 0x00020000,\n};\n\n/* Init Blocks */\nenum {\n\tBLOCK_ATC,\n\tBLOCK_BRB1,\n\tBLOCK_CCM,\n\tBLOCK_CDU,\n\tBLOCK_CFC,\n\tBLOCK_CSDM,\n\tBLOCK_CSEM,\n\tBLOCK_DBG,\n\tBLOCK_DMAE,\n\tBLOCK_DORQ,\n\tBLOCK_HC,\n\tBLOCK_IGU,\n\tBLOCK_MISC,\n\tBLOCK_NIG,\n\tBLOCK_PBF,\n\tBLOCK_PGLUE_B,\n\tBLOCK_PRS,\n\tBLOCK_PXP2,\n\tBLOCK_PXP,\n\tBLOCK_QM,\n\tBLOCK_SRC,\n\tBLOCK_TCM,\n\tBLOCK_TM,\n\tBLOCK_TSDM,\n\tBLOCK_TSEM,\n\tBLOCK_UCM,\n\tBLOCK_UPB,\n\tBLOCK_USDM,\n\tBLOCK_USEM,\n\tBLOCK_XCM,\n\tBLOCK_XPB,\n\tBLOCK_XSDM,\n\tBLOCK_XSEM,\n\tBLOCK_MISC_AEU,\n\tNUM_OF_INIT_BLOCKS\n};\n\n\n\n\n\n\n\n\n/* Vnics per mode */\n#define ECORE_PORT2_MODE_NUM_VNICS 4\n\n\n/* QM queue numbers */\n#define ECORE_ETH_Q\t\t0\n#define ECORE_TOE_Q\t\t3\n#define ECORE_TOE_ACK_Q\t\t6\n#define ECORE_ISCSI_Q\t\t9\n#define ECORE_ISCSI_ACK_Q\t11\n#define ECORE_FCOE_Q\t\t10\n\n/* Vnics per mode */\n#define ECORE_PORT4_MODE_NUM_VNICS 2\n\n/* COS offset for port1 in E3 B0 4port mode */\n#define ECORE_E3B0_PORT1_COS_OFFSET 3\n\n/* QM Register addresses */\n#define ECORE_Q_VOQ_REG_ADDR(pf_q_num)\\\n\t(QM_REG_QVOQIDX_0 + 4 * (pf_q_num))\n#define ECORE_VOQ_Q_REG_ADDR(cos, pf_q_num)\\\n\t(QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))\n#define ECORE_Q_CMDQ_REG_ADDR(pf_q_num)\\\n\t(QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))\n\n/* extracts the QM queue number for the specified port and vnic */\n#define ECORE_PF_Q_NUM(q_num, port, vnic)\\\n\t((((port) << 1) | (vnic)) * 16 + (q_num))\n\n\n/* Maps the specified queue to the specified COS */\nstatic inline void ecore_map_q_cos(struct bnx2x_softc *sc, uint32_t q_num, uint32_t new_cos)\n{\n\t/* find current COS mapping */\n\tuint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4);\n\n\t/* check if queue->COS mapping has changed */\n\tif (curr_cos != new_cos) {\n\t\tuint32_t num_vnics = ECORE_PORT2_MODE_NUM_VNICS;\n\t\tuint32_t reg_addr, reg_bit_map, vnic;\n\n\t\t/* update parameters for 4port mode */\n\t\tif (INIT_MODE_FLAGS(sc) & MODE_PORT4) {\n\t\t\tnum_vnics = ECORE_PORT4_MODE_NUM_VNICS;\n\t\t\tif (PORT_ID(sc)) {\n\t\t\t\tcurr_cos += ECORE_E3B0_PORT1_COS_OFFSET;\n\t\t\t\tnew_cos += ECORE_E3B0_PORT1_COS_OFFSET;\n\t\t\t}\n\t\t}\n\n\t\t/* change queue mapping for each VNIC */\n\t\tfor (vnic = 0; vnic < num_vnics; vnic++) {\n\t\t\tuint32_t pf_q_num =\n\t\t\t\tECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic);\n\t\t\tuint32_t q_bit_map = 1 << (pf_q_num & 0x1f);\n\n\t\t\t/* overwrite queue->VOQ mapping */\n\t\t\tREG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos);\n\n\t\t\t/* clear queue bit from current COS bit map */\n\t\t\treg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);\n\t\t\treg_bit_map = REG_RD(sc, reg_addr);\n\t\t\tREG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map));\n\n\t\t\t/* set queue bit in new COS bit map */\n\t\t\treg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num);\n\t\t\treg_bit_map = REG_RD(sc, reg_addr);\n\t\t\tREG_WR(sc, reg_addr, reg_bit_map | q_bit_map);\n\n\t\t\t/* set/clear queue bit in command-queue bit map\n\t\t\t(E2/E3A0 only, valid COS values are 0/1) */\n\t\t\tif (!(INIT_MODE_FLAGS(sc) & MODE_E3_B0)) {\n\t\t\t\treg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num);\n\t\t\t\treg_bit_map = REG_RD(sc, reg_addr);\n\t\t\t\tq_bit_map = 1 << (2 * (pf_q_num & 0xf));\n\t\t\t\treg_bit_map = new_cos ?\n\t\t\t\t\t (reg_bit_map | q_bit_map) :\n\t\t\t\t\t (reg_bit_map & (~q_bit_map));\n\t\t\t\tREG_WR(sc, reg_addr, reg_bit_map);\n\t\t\t}\n\t\t}\n\t}\n}\n\n/* Configures the QM according to the specified per-traffic-type COSes */\nstatic inline void ecore_dcb_config_qm(struct bnx2x_softc *sc, enum cos_mode mode,\n\t\t\t\t struct priority_cos *traffic_cos)\n{\n\tecore_map_q_cos(sc, ECORE_FCOE_Q,\n\t\t\ttraffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);\n\tecore_map_q_cos(sc, ECORE_ISCSI_Q,\n\t\t\ttraffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);\n\tecore_map_q_cos(sc, ECORE_ISCSI_ACK_Q,\n\t\ttraffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);\n\tif (mode != STATIC_COS) {\n\t\t/* required only in OVERRIDE_COS mode */\n\t\tecore_map_q_cos(sc, ECORE_ETH_Q,\n\t\t\t\ttraffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);\n\t\tecore_map_q_cos(sc, ECORE_TOE_Q,\n\t\t\t\ttraffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);\n\t\tecore_map_q_cos(sc, ECORE_TOE_ACK_Q,\n\t\t\t\ttraffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);\n\t}\n}\n\n\n/*\n * congestion managment port init api description\n * the api works as follows:\n * the driver should pass the cmng_init_input struct, the port_init function\n * will prepare the required internal ram structure which will be passed back\n * to the driver (cmng_init) that will write it into the internal ram.\n *\n * IMPORTANT REMARKS:\n * 1. the cmng_init struct does not represent the contiguous internal ram\n * structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET\n * offset in order to write the port sub struct and the\n * PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other\n * words - don't use memcpy!).\n * 2. although the cmng_init struct is filled for the maximal vnic number\n * possible, the driver should only write the valid vnics into the internal\n * ram according to the appropriate port mode.\n */\n#define BITS_TO_BYTES(x) ((x)/8)\n\n/* CMNG constants, as derived from system spec calculations */\n\n/* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */\n#define DEF_MIN_RATE 100\n\n/* resolution of the rate shaping timer - 400 usec */\n#define RS_PERIODIC_TIMEOUT_USEC 400\n\n/*\n * number of bytes in single QM arbitration cycle -\n * coefficient for calculating the fairness timer\n */\n#define QM_ARB_BYTES 160000\n\n/* resolution of Min algorithm 1:100 */\n#define MIN_RES 100\n\n/*\n * how many bytes above threshold for\n * the minimal credit of Min algorithm\n */\n#define MIN_ABOVE_THRESH 32768\n\n/*\n * Fairness algorithm integration time coefficient -\n * for calculating the actual Tfair\n */\n#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)\n\n/* Memory of fairness algorithm - 2 cycles */\n#define FAIR_MEM 2\n#define SAFC_TIMEOUT_USEC 52\n\n#define SDM_TICKS 4\n\n\nstatic inline void ecore_init_max(const struct cmng_init_input *input_data,\n\t\t\t\t uint32_t r_param, struct cmng_init *ram_data)\n{\n\tuint32_t vnic;\n\tstruct cmng_vnic *vdata = &ram_data->vnic;\n\tstruct cmng_struct_per_port *pdata = &ram_data->port;\n\t/*\n\t * rate shaping per-port variables\n\t * 100 micro seconds in SDM ticks = 25\n\t * since each tick is 4 microSeconds\n\t */\n\n\tpdata->rs_vars.rs_periodic_timeout =\n\tRS_PERIODIC_TIMEOUT_USEC / SDM_TICKS;\n\n\t/* this is the threshold below which no timer arming will occur.\n\t * 1.25 coefficient is for the threshold to be a little bigger\n\t * then the real time to compensate for timer in-accuracy\n\t */\n\tpdata->rs_vars.rs_threshold =\n\t(5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4;\n\n\t/* rate shaping per-vnic variables */\n\tfor (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {\n\t\t/* global vnic counter */\n\t\tvdata->vnic_max_rate[vnic].vn_counter.rate =\n\t\tinput_data->vnic_max_rate[vnic];\n\t\t/*\n\t\t * maximal Mbps for this vnic\n\t\t * the quota in each timer period - number of bytes\n\t\t * transmitted in this period\n\t\t */\n\t\tvdata->vnic_max_rate[vnic].vn_counter.quota =\n\t\t\tRS_PERIODIC_TIMEOUT_USEC *\n\t\t\t(uint32_t)vdata->vnic_max_rate[vnic].vn_counter.rate / 8;\n\t}\n\n}\n\nstatic inline void ecore_init_max_per_vn(uint16_t vnic_max_rate,\n\t\t\t\t struct rate_shaping_vars_per_vn *ram_data)\n{\n\t/* global vnic counter */\n\tram_data->vn_counter.rate = vnic_max_rate;\n\n\t/*\n\t* maximal Mbps for this vnic\n\t* the quota in each timer period - number of bytes\n\t* transmitted in this period\n\t*/\n\tram_data->vn_counter.quota =\n\t\tRS_PERIODIC_TIMEOUT_USEC * (uint32_t)vnic_max_rate / 8;\n}\n\nstatic inline void ecore_init_min(const struct cmng_init_input *input_data,\n\t\t\t\t uint32_t r_param, struct cmng_init *ram_data)\n{\n\tuint32_t vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair;\n\tstruct cmng_vnic *vdata = &ram_data->vnic;\n\tstruct cmng_struct_per_port *pdata = &ram_data->port;\n\n\t/* this is the resolution of the fairness timer */\n\tfair_periodic_timeout_usec = QM_ARB_BYTES / r_param;\n\n\t/*\n\t * fairness per-port variables\n\t * for 10G it is 1000usec. for 1G it is 10000usec.\n\t */\n\ttFair = T_FAIR_COEF / input_data->port_rate;\n\n\t/* this is the threshold below which we won't arm the timer anymore */\n\tpdata->fair_vars.fair_threshold = QM_ARB_BYTES;\n\n\t/*\n\t * we multiply by 1e3/8 to get bytes/msec. We don't want the credits\n\t * to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution)\n\t */\n\tpdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM;\n\n\t/* since each tick is 4 microSeconds */\n\tpdata->fair_vars.fairness_timeout =\n\t\t\t\tfair_periodic_timeout_usec / SDM_TICKS;\n\n\t/* calculate sum of weights */\n\tvnicWeightSum = 0;\n\n\tfor (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++)\n\t\tvnicWeightSum += input_data->vnic_min_rate[vnic];\n\n\t/* global vnic counter */\n\tif (vnicWeightSum > 0) {\n\t\t/* fairness per-vnic variables */\n\t\tfor (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {\n\t\t\t/*\n\t\t\t * this is the credit for each period of the fairness\n\t\t\t * algorithm - number of bytes in T_FAIR (this vnic\n\t\t\t * share of the port rate)\n\t\t\t */\n\t\t\tvdata->vnic_min_rate[vnic].vn_credit_delta =\n\t\t\t\t((uint32_t)(input_data->vnic_min_rate[vnic]) * 100 *\n\t\t\t\t(T_FAIR_COEF / (8 * 100 * vnicWeightSum)));\n\t\t\tif (vdata->vnic_min_rate[vnic].vn_credit_delta <\n\t\t\t pdata->fair_vars.fair_threshold +\n\t\t\t MIN_ABOVE_THRESH) {\n\t\t\t\tvdata->vnic_min_rate[vnic].vn_credit_delta =\n\t\t\t\t\tpdata->fair_vars.fair_threshold +\n\t\t\t\t\tMIN_ABOVE_THRESH;\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data,\n\t\t\t\t struct cmng_init *ram_data)\n{\n\tuint32_t vnic, cos;\n\tuint32_t cosWeightSum = 0;\n\tstruct cmng_vnic *vdata = &ram_data->vnic;\n\tstruct cmng_struct_per_port *pdata = &ram_data->port;\n\n\tfor (cos = 0; cos < MAX_COS_NUMBER; cos++)\n\t\tcosWeightSum += input_data->cos_min_rate[cos];\n\n\tif (cosWeightSum > 0) {\n\n\t\tfor (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) {\n\t\t\t/*\n\t\t\t * Since cos and vnic shouldn't work together the rate\n\t\t\t * to divide between the coses is the port rate.\n\t\t\t */\n\t\t\tuint32_t *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta;\n\t\t\tfor (cos = 0; cos < MAX_COS_NUMBER; cos++) {\n\t\t\t\t/*\n\t\t\t\t * this is the credit for each period of\n\t\t\t\t * the fairness algorithm - number of bytes\n\t\t\t\t * in T_FAIR (this cos share of the vnic rate)\n\t\t\t\t */\n\t\t\t\tccd[cos] =\n\t\t\t\t ((uint32_t)input_data->cos_min_rate[cos] * 100 *\n\t\t\t\t (T_FAIR_COEF / (8 * 100 * cosWeightSum)));\n\t\t\t\t if (ccd[cos] < pdata->fair_vars.fair_threshold\n\t\t\t\t\t\t+ MIN_ABOVE_THRESH) {\n\t\t\t\t\tccd[cos] =\n\t\t\t\t\t pdata->fair_vars.fair_threshold +\n\t\t\t\t\t MIN_ABOVE_THRESH;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic inline void ecore_init_safc(struct cmng_init *ram_data)\n{\n\t/* in microSeconds */\n\tram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC;\n}\n\n/* Congestion management port init */\nstatic inline void ecore_init_cmng(const struct cmng_init_input *input_data,\n\t\t\t\t struct cmng_init *ram_data)\n{\n\tuint32_t r_param;\n\tECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init));\n\n\tram_data->port.flags = input_data->flags;\n\n\t/*\n\t * number of bytes transmitted in a rate of 10Gbps\n\t * in one usec = 1.25KB.\n\t */\n\tr_param = BITS_TO_BYTES(input_data->port_rate);\n\tecore_init_max(input_data, r_param, ram_data);\n\tecore_init_min(input_data, r_param, ram_data);\n\tecore_init_fw_wrr(input_data, ram_data);\n\tecore_init_safc(ram_data);\n}\n\n\n\n\n/* Returns the index of start or end of a specific block stage in ops array*/\n#define BLOCK_OPS_IDX(block, stage, end) \\\n\t\t\t(2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))\n\n\n#define INITOP_SET\t\t0\t/* set the HW directly */\n#define INITOP_CLEAR\t\t1\t/* clear the HW directly */\n#define INITOP_INIT\t\t2\t/* set the init-value array */\n\n/****************************************************************************\n* ILT management\n****************************************************************************/\nstruct ilt_line {\n\tecore_dma_addr_t page_mapping;\n\tvoid *page;\n\tuint32_t size;\n};\n\nstruct ilt_client_info {\n\tuint32_t page_size;\n\tuint16_t start;\n\tuint16_t end;\n\tuint16_t client_num;\n\tuint16_t flags;\n#define ILT_CLIENT_SKIP_INIT\t0x1\n#define ILT_CLIENT_SKIP_MEM\t0x2\n};\n\nstruct ecore_ilt {\n\tuint32_t start_line;\n\tstruct ilt_line\t\t*lines;\n\tstruct ilt_client_info\tclients[4];\n#define ILT_CLIENT_CDU\t0\n#define ILT_CLIENT_QM\t1\n#define ILT_CLIENT_SRC\t2\n#define ILT_CLIENT_TM\t3\n};\n\n/****************************************************************************\n* SRC configuration\n****************************************************************************/\nstruct src_ent {\n\tuint8_t opaque[56];\n\tuint64_t next;\n};\n\n/****************************************************************************\n* Parity configuration\n****************************************************************************/\n#define BLOCK_PRTY_INFO(block, en_mask, m1h, m2, m3) \\\n{ \\\n\tblock##_REG_##block##_PRTY_MASK, \\\n\tblock##_REG_##block##_PRTY_STS_CLR, \\\n\ten_mask, {m1h, m2, m3}, #block \\\n}\n\n#define BLOCK_PRTY_INFO_0(block, en_mask, m1h, m2, m3) \\\n{ \\\n\tblock##_REG_##block##_PRTY_MASK_0, \\\n\tblock##_REG_##block##_PRTY_STS_CLR_0, \\\n\ten_mask, {m1h, m2, m3}, #block\"_0\" \\\n}\n\n#define BLOCK_PRTY_INFO_1(block, en_mask, m1h, m2, m3) \\\n{ \\\n\tblock##_REG_##block##_PRTY_MASK_1, \\\n\tblock##_REG_##block##_PRTY_STS_CLR_1, \\\n\ten_mask, {m1h, m2, m3}, #block\"_1\" \\\n}\n\nstatic const struct {\n\tuint32_t mask_addr;\n\tuint32_t sts_clr_addr;\n\tuint32_t en_mask;\t\t/* Mask to enable parity attentions */\n\tstruct {\n\t\tuint32_t e1h;\t/* 57711 */\n\t\tuint32_t e2;\t\t/* 57712 */\n\t\tuint32_t e3;\t\t/* 578xx */\n\t} reg_mask;\t\t/* Register mask (all valid bits) */\n\tchar name[8];\t\t/* Block's longest name is 7 characters long\n\t\t\t\t * (name + suffix)\n\t\t\t\t */\n} ecore_blocks_parity_data[] = {\n\t/* bit 19 masked */\n\t/* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */\n\t/* bit 5,18,20-31 */\n\t/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */\n\t/* bit 5 */\n\t/* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20);\t*/\n\t/* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */\n\t/* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */\n\n\t/* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't\n\t * want to handle \"system kill\" flow at the moment.\n\t */\n\tBLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x7ffffff,\n\t\t\t0x7ffffff),\n\tBLOCK_PRTY_INFO_0(PXP2,\t0xffffffff, 0xffffffff, 0xffffffff,\n\t\t\t 0xffffffff),\n\tBLOCK_PRTY_INFO_1(PXP2,\t0x1ffffff, 0x7f, 0x7ff, 0x1ffffff),\n\tBLOCK_PRTY_INFO(HC, 0x7, 0x7, 0, 0),\n\tBLOCK_PRTY_INFO(NIG, 0xffffffff, 0xffffffff, 0, 0),\n\tBLOCK_PRTY_INFO_0(NIG,\t0xffffffff, 0, 0xffffffff, 0xffffffff),\n\tBLOCK_PRTY_INFO_1(NIG,\t0xffff, 0, 0xff, 0xffff),\n\tBLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0x7ff, 0x7ff),\n\tBLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),\n\tBLOCK_PRTY_INFO(QM, 0, 0xfff, 0xfff, 0xfff),\n\tBLOCK_PRTY_INFO(ATC, 0x1f, 0, 0x1f, 0x1f),\n\tBLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0x3, 0x3),\n\tBLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),\n\t{GRCBASE_UPB + PB_REG_PB_PRTY_MASK,\n\t\tGRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,\n\t\t{0xf, 0xf, 0xf}, \"UPB\"},\n\t{GRCBASE_XPB + PB_REG_PB_PRTY_MASK,\n\t\tGRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,\n\t\t{0xf, 0xf, 0xf}, \"XPB\"},\n\tBLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),\n\tBLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),\n\tBLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0x3f),\n\tBLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),\n\tBLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),\n\tBLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),\n\tBLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),\n\tBLOCK_PRTY_INFO(PBF, 0, 0x3ffff, 0xfffff, 0xfffffff),\n\tBLOCK_PRTY_INFO(TM, 0, 0x7f, 0x7f, 0x7f),\n\tBLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),\n\tBLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),\n\tBLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),\n\tBLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),\n\tBLOCK_PRTY_INFO(TCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),\n\tBLOCK_PRTY_INFO(CCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),\n\tBLOCK_PRTY_INFO(UCM, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),\n\tBLOCK_PRTY_INFO(XCM, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),\n\tBLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),\n\tBLOCK_PRTY_INFO_1(TSEM, 0, 0x1f, 0x3f, 0x3f),\n\tBLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),\n\tBLOCK_PRTY_INFO_1(USEM, 0, 0x1f, 0x1f, 0x1f),\n\tBLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),\n\tBLOCK_PRTY_INFO_1(CSEM, 0, 0x1f, 0x1f, 0x1f),\n\tBLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),\n\tBLOCK_PRTY_INFO_1(XSEM, 0, 0x1f, 0x3f, 0x3f),\n};\n\n\n/* [28] MCP Latched rom_parity\n * [29] MCP Latched ump_rx_parity\n * [30] MCP Latched ump_tx_parity\n * [31] MCP Latched scpad_parity\n */\n#define MISC_AEU_ENABLE_MCP_PRTY_BITS\t\\\n\t(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \\\n\t AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \\\n\t AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \\\n\t AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)\n\n/* Below registers control the MCP parity attention output. When\n * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are\n * enabled, when cleared - disabled.\n */\nstatic const uint32_t mcp_attn_ctl_regs[] = {\n\tMISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,\n\tMISC_REG_AEU_ENABLE4_NIG_0,\n\tMISC_REG_AEU_ENABLE4_PXP_0,\n\tMISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,\n\tMISC_REG_AEU_ENABLE4_NIG_1,\n\tMISC_REG_AEU_ENABLE4_PXP_1\n};\n\nstatic inline void ecore_set_mcp_parity(struct bnx2x_softc *sc, uint8_t enable)\n{\n\tuint32_t i;\n\tuint32_t reg_val;\n\n\tfor (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) {\n\t\treg_val = REG_RD(sc, mcp_attn_ctl_regs[i]);\n\n\t\tif (enable)\n\t\t\treg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;\n\t\telse\n\t\t\treg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;\n\n\t\tREG_WR(sc, mcp_attn_ctl_regs[i], reg_val);\n\t}\n}\n\nstatic inline uint32_t ecore_parity_reg_mask(struct bnx2x_softc *sc, int idx)\n{\n\tif (CHIP_IS_E1H(sc))\n\t\treturn ecore_blocks_parity_data[idx].reg_mask.e1h;\n\telse if (CHIP_IS_E2(sc))\n\t\treturn ecore_blocks_parity_data[idx].reg_mask.e2;\n\telse /* CHIP_IS_E3 */\n\t\treturn ecore_blocks_parity_data[idx].reg_mask.e3;\n}\n\nstatic inline void ecore_disable_blocks_parity(struct bnx2x_softc *sc)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {\n\t\tuint32_t dis_mask = ecore_parity_reg_mask(sc, i);\n\n\t\tif (dis_mask) {\n\t\t\tREG_WR(sc, ecore_blocks_parity_data[i].mask_addr,\n\t\t\t dis_mask);\n\t\t\tECORE_MSG(\"Setting parity mask \"\n\t\t\t\t\t\t \"for %s to\\t\\t0x%x\",\n\t\t\t\t ecore_blocks_parity_data[i].name, dis_mask);\n\t\t}\n\t}\n\n\t/* Disable MCP parity attentions */\n\tecore_set_mcp_parity(sc, FALSE);\n}\n\n/**\n * Clear the parity error status registers.\n */\nstatic inline void ecore_clear_blocks_parity(struct bnx2x_softc *sc)\n{\n\tuint32_t i;\n\tuint32_t reg_val, mcp_aeu_bits =\n\t\tAEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |\n\t\tAEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |\n\t\tAEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |\n\t\tAEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;\n\n\t/* Clear SEM_FAST parities */\n\tREG_WR(sc, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);\n\tREG_WR(sc, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);\n\tREG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);\n\tREG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);\n\n\tfor (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {\n\t\tuint32_t reg_mask = ecore_parity_reg_mask(sc, i);\n\n\t\tif (reg_mask) {\n\t\t\treg_val = REG_RD(sc, ecore_blocks_parity_data[i].\n\t\t\t\t\t sts_clr_addr);\n\t\t\tif (reg_val & reg_mask)\n\t\t\t\tECORE_MSG(\"Parity errors in %s: 0x%x\",\n\t\t\t\t\t ecore_blocks_parity_data[i].name,\n\t\t\t\t\t reg_val & reg_mask);\n\t\t}\n\t}\n\n\t/* Check if there were parity attentions in MCP */\n\treg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP);\n\tif (reg_val & mcp_aeu_bits)\n\t\tECORE_MSG(\"Parity error in MCP: 0x%x\",\n\t\t\t reg_val & mcp_aeu_bits);\n\n\t/* Clear parity attentions in MCP:\n\t * [7] clears Latched rom_parity\n\t * [8] clears Latched ump_rx_parity\n\t * [9] clears Latched ump_tx_parity\n\t * [10] clears Latched scpad_parity (both ports)\n\t */\n\tREG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);\n}\n\nstatic inline void ecore_enable_blocks_parity(struct bnx2x_softc *sc)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) {\n\t\tuint32_t reg_mask = ecore_parity_reg_mask(sc, i);\n\n\t\tif (reg_mask)\n\t\t\tREG_WR(sc, ecore_blocks_parity_data[i].mask_addr,\n\t\t\t\tecore_blocks_parity_data[i].en_mask & reg_mask);\n\t}\n\n\t/* Enable MCP parity attentions */\n\tecore_set_mcp_parity(sc, TRUE);\n}\n\n\n#endif /* ECORE_INIT_H */\n" }, { "path": "drivers/net/bnx2x/ecore_init_ops.h", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ECORE_INIT_OPS_H\n#define ECORE_INIT_OPS_H\n\nstatic int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t *zbuf, int len);\nstatic void ecore_write_dmae_phys_len(struct bnx2x_softc *sc,\n\t\t\t\t ecore_dma_addr_t phys_addr, uint32_t addr,\n\t\t\t\t uint32_t len);\n\nstatic void ecore_init_str_wr(struct bnx2x_softc *sc, uint32_t addr,\n\t\t\t const uint32_t *data, uint32_t len)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < len; i++)\n\t\tREG_WR(sc, addr + i*4, data[i]);\n}\n\nstatic void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr, uint32_t len)\n{\n\tif (DMAE_READY(sc))\n\t\tecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);\n\n\telse ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);\n}\n\nstatic void ecore_init_fill(struct bnx2x_softc *sc, uint32_t addr, int fill,\n\t\t\t uint32_t len)\n{\n\tuint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));\n\tuint32_t buf_len32 = buf_len/4;\n\tuint32_t i;\n\n\tECORE_MEMSET(GUNZIP_BUF(sc), (uint8_t)fill, buf_len);\n\n\tfor (i = 0; i < len; i += buf_len32) {\n\t\tuint32_t cur_len = min(buf_len32, len - i);\n\n\t\tecore_write_big_buf(sc, addr + i*4, cur_len);\n\t}\n}\n\nstatic void ecore_write_big_buf_wb(struct bnx2x_softc *sc, uint32_t addr, uint32_t len)\n{\n\tif (DMAE_READY(sc))\n\t\tecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);\n\n\telse ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);\n}\n\nstatic void ecore_init_wr_64(struct bnx2x_softc *sc, uint32_t addr,\n\t\t\t const uint32_t *data, uint32_t len64)\n{\n\tuint32_t buf_len32 = FW_BUF_SIZE/4;\n\tuint32_t len = len64*2;\n\tuint64_t data64 = 0;\n\tuint32_t i;\n\n\t/* 64 bit value is in a blob: first low DWORD, then high DWORD */\n\tdata64 = HILO_U64((*(data + 1)), (*data));\n\n\tlen64 = min((uint32_t)(FW_BUF_SIZE/8), len64);\n\tfor (i = 0; i < len64; i++) {\n\t\tuint64_t *pdata = ((uint64_t *)(GUNZIP_BUF(sc))) + i;\n\n\t\t*pdata = data64;\n\t}\n\n\tfor (i = 0; i < len; i += buf_len32) {\n\t\tuint32_t cur_len = min(buf_len32, len - i);\n\n\t\tecore_write_big_buf_wb(sc, addr + i*4, cur_len);\n\t}\n}\n\n/*********************************************************\n There are different blobs for each PRAM section.\n In addition, each blob write operation is divided into a few operations\n in order to decrease the amount of phys. contiguous buffer needed.\n Thus, when we select a blob the address may be with some offset\n from the beginning of PRAM section.\n The same holds for the INT_TABLE sections.\n**********************************************************/\n#define IF_IS_INT_TABLE_ADDR(base, addr) \\\n\t\t\tif (((base) <= (addr)) && ((base) + 0x400 >= (addr)))\n\n#define IF_IS_PRAM_ADDR(base, addr) \\\n\t\t\tif (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))\n\nstatic const uint8_t *ecore_sel_blob(struct bnx2x_softc *sc, uint32_t addr,\n\t\t\t\tconst uint8_t *data)\n{\n\tIF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)\n\t\tdata = INIT_TSEM_INT_TABLE_DATA(sc);\n\telse\n\t\tIF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)\n\t\t\tdata = INIT_CSEM_INT_TABLE_DATA(sc);\n\telse\n\t\tIF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)\n\t\t\tdata = INIT_USEM_INT_TABLE_DATA(sc);\n\telse\n\t\tIF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)\n\t\t\tdata = INIT_XSEM_INT_TABLE_DATA(sc);\n\telse\n\t\tIF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)\n\t\t\tdata = INIT_TSEM_PRAM_DATA(sc);\n\telse\n\t\tIF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)\n\t\t\tdata = INIT_CSEM_PRAM_DATA(sc);\n\telse\n\t\tIF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)\n\t\t\tdata = INIT_USEM_PRAM_DATA(sc);\n\telse\n\t\tIF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)\n\t\t\tdata = INIT_XSEM_PRAM_DATA(sc);\n\n\treturn data;\n}\n\nstatic void ecore_init_wr_wb(struct bnx2x_softc *sc, uint32_t addr,\n\t\t\t const uint32_t *data, uint32_t len)\n{\n\tif (DMAE_READY(sc))\n\t\tVIRT_WR_DMAE_LEN(sc, data, addr, len, 0);\n\n\telse ecore_init_str_wr(sc, addr, data, len);\n}\n\nstatic void ecore_wr_64(struct bnx2x_softc *sc, uint32_t reg, uint32_t val_lo,\n\t\t\tuint32_t val_hi)\n{\n\tuint32_t wb_write[2];\n\n\twb_write[0] = val_lo;\n\twb_write[1] = val_hi;\n\tREG_WR_DMAE_LEN(sc, reg, wb_write, 2);\n}\n\nstatic void ecore_init_wr_zp(struct bnx2x_softc *sc, uint32_t addr, uint32_t len,\n\t\t\t uint32_t blob_off)\n{\n\tconst uint8_t *data = NULL;\n\tint rc;\n\tuint32_t i;\n\n\tdata = ecore_sel_blob(sc, addr, data) + blob_off*4;\n\n\trc = ecore_gunzip(sc, data, len);\n\tif (rc)\n\t\treturn;\n\n\t/* gunzip_outlen is in dwords */\n\tlen = GUNZIP_OUTLEN(sc);\n\tfor (i = 0; i < len; i++)\n\t\t((uint32_t *)GUNZIP_BUF(sc))[i] = (uint32_t)\n\t\t\t\tECORE_CPU_TO_LE32(((uint32_t *)GUNZIP_BUF(sc))[i]);\n\n\tecore_write_big_buf_wb(sc, addr, len);\n}\n\nstatic void ecore_init_block(struct bnx2x_softc *sc, uint32_t block, uint32_t stage)\n{\n\tuint16_t op_start =\n\t\tINIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,\n\t\t\t\t\t\t STAGE_START)];\n\tuint16_t op_end =\n\t\tINIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,\n\t\t\t\t\t\t STAGE_END)];\n\tconst union init_op *op;\n\tuint32_t op_idx, op_type, addr, len;\n\tconst uint32_t *data, *data_base;\n\n\t/* If empty block */\n\tif (op_start == op_end)\n\t\treturn;\n\n\tdata_base = INIT_DATA(sc);\n\n\tfor (op_idx = op_start; op_idx < op_end; op_idx++) {\n\n\t\top = (const union init_op *)&(INIT_OPS(sc)[op_idx]);\n\t\t/* Get generic data */\n\t\top_type = op->raw.op;\n\t\taddr = op->raw.offset;\n\t\t/* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and\n\t\t * OP_WR64 (we assume that op_arr_write and op_write have the\n\t\t * same structure).\n\t\t */\n\t\tlen = op->arr_wr.data_len;\n\t\tdata = data_base + op->arr_wr.data_off;\n\n\t\tswitch (op_type) {\n\t\tcase OP_RD:\n\t\t\tREG_RD(sc, addr);\n\t\t\tbreak;\n\t\tcase OP_WR:\n\t\t\tREG_WR(sc, addr, op->write.val);\n\t\t\tbreak;\n\t\tcase OP_SW:\n\t\t\tecore_init_str_wr(sc, addr, data, len);\n\t\t\tbreak;\n\t\tcase OP_WB:\n\t\t\tecore_init_wr_wb(sc, addr, data, len);\n\t\t\tbreak;\n\t\tcase OP_ZR:\n\t\tcase OP_WB_ZR:\n\t\t\tecore_init_fill(sc, addr, 0, op->zero.len);\n\t\t\tbreak;\n\t\tcase OP_ZP:\n\t\t\tecore_init_wr_zp(sc, addr, len, op->arr_wr.data_off);\n\t\t\tbreak;\n\t\tcase OP_WR_64:\n\t\t\tecore_init_wr_64(sc, addr, data, len);\n\t\t\tbreak;\n\t\tcase OP_IF_MODE_AND:\n\t\t\t/* if any of the flags doesn't match, skip the\n\t\t\t * conditional block.\n\t\t\t */\n\t\t\tif ((INIT_MODE_FLAGS(sc) &\n\t\t\t\top->if_mode.mode_bit_map) !=\n\t\t\t\top->if_mode.mode_bit_map)\n\t\t\t\top_idx += op->if_mode.cmd_offset;\n\t\t\tbreak;\n\t\tcase OP_IF_MODE_OR:\n\t\t\t/* if all the flags don't match, skip the conditional\n\t\t\t * block.\n\t\t\t */\n\t\t\tif ((INIT_MODE_FLAGS(sc) &\n\t\t\t\top->if_mode.mode_bit_map) == 0)\n\t\t\t\top_idx += op->if_mode.cmd_offset;\n\t\t\tbreak;\n\t\t /* the following opcodes are unused at the moment. */\n\t\tcase OP_IF_PHASE:\n\t\tcase OP_RT:\n\t\tcase OP_DELAY:\n\t\tcase OP_VERIFY:\n\t\tdefault:\n\t\t\t/* Should never get here! */\n\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\n\n/****************************************************************************\n* PXP Arbiter\n****************************************************************************/\n/*\n * This code configures the PCI read/write arbiter\n * which implements a weighted round robin\n * between the virtual queues in the chip.\n *\n * The values were derived for each PCI max payload and max request size.\n * since max payload and max request size are only known at run time,\n * this is done as a separate init stage.\n */\n\n#define NUM_WR_Q\t\t\t13\n#define NUM_RD_Q\t\t\t29\n#define MAX_RD_ORD\t\t\t3\n#define MAX_WR_ORD\t\t\t2\n\n/* configuration for one arbiter queue */\nstruct arb_line {\n\tint l;\n\tint add;\n\tint ubound;\n};\n\n/* derived configuration for each read queue for each max request size */\nstatic const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {\n/* 1 */\t{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },\n\t{ {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },\n\t{ {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },\n\t{ {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },\n\t{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },\n/* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n/* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },\n\t{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }\n};\n\n/* derived configuration for each write queue for each max request size */\nstatic const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {\n/* 1 */\t{ {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },\n\t{ {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },\n\t{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },\n\t{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },\n\t{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },\n\t{ {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },\n\t{ {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },\n\t{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },\n\t{ {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },\n/* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },\n\t{ {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },\n\t{ {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },\n\t{ {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }\n};\n\n/* register addresses for read queues */\nstatic const struct arb_line read_arb_addr[NUM_RD_Q-1] = {\n/* 1 */\t{PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND0},\n\t{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,\n\t\tPXP2_REG_PSWRQ_BW_UB1},\n\t{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,\n\t\tPXP2_REG_PSWRQ_BW_UB2},\n\t{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,\n\t\tPXP2_REG_PSWRQ_BW_UB3},\n\t{PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND4},\n\t{PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND5},\n\t{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,\n\t\tPXP2_REG_PSWRQ_BW_UB6},\n\t{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,\n\t\tPXP2_REG_PSWRQ_BW_UB7},\n\t{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,\n\t\tPXP2_REG_PSWRQ_BW_UB8},\n/* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,\n\t\tPXP2_REG_PSWRQ_BW_UB9},\n\t{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,\n\t\tPXP2_REG_PSWRQ_BW_UB10},\n\t{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,\n\t\tPXP2_REG_PSWRQ_BW_UB11},\n\t{PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND12},\n\t{PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND13},\n\t{PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND14},\n\t{PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND15},\n\t{PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND16},\n\t{PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND17},\n\t{PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND18},\n/* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND19},\n\t{PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND20},\n\t{PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND22},\n\t{PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND23},\n\t{PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND24},\n\t{PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND25},\n\t{PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND26},\n\t{PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,\n\t\tPXP2_REG_RQ_BW_RD_UBOUND27},\n\t{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,\n\t\tPXP2_REG_PSWRQ_BW_UB28}\n};\n\n/* register addresses for write queues */\nstatic const struct arb_line write_arb_addr[NUM_WR_Q-1] = {\n/* 1 */\t{PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,\n\t\tPXP2_REG_PSWRQ_BW_UB1},\n\t{PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,\n\t\tPXP2_REG_PSWRQ_BW_UB2},\n\t{PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,\n\t\tPXP2_REG_PSWRQ_BW_UB3},\n\t{PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,\n\t\tPXP2_REG_PSWRQ_BW_UB6},\n\t{PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,\n\t\tPXP2_REG_PSWRQ_BW_UB7},\n\t{PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,\n\t\tPXP2_REG_PSWRQ_BW_UB8},\n\t{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,\n\t\tPXP2_REG_PSWRQ_BW_UB9},\n\t{PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,\n\t\tPXP2_REG_PSWRQ_BW_UB10},\n\t{PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,\n\t\tPXP2_REG_PSWRQ_BW_UB11},\n/* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,\n\t\tPXP2_REG_PSWRQ_BW_UB28},\n\t{PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,\n\t\tPXP2_REG_RQ_BW_WR_UBOUND29},\n\t{PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,\n\t\tPXP2_REG_RQ_BW_WR_UBOUND30}\n};\n\nstatic void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order,\n\t\t\t int w_order)\n{\n\tuint32_t val, i;\n\n\tif (r_order > MAX_RD_ORD) {\n\t\tECORE_MSG(\"read order of %d order adjusted to %d\",\n\t\t\t r_order, MAX_RD_ORD);\n\t\tr_order = MAX_RD_ORD;\n\t}\n\tif (w_order > MAX_WR_ORD) {\n\t\tECORE_MSG(\"write order of %d order adjusted to %d\",\n\t\t\t w_order, MAX_WR_ORD);\n\t\tw_order = MAX_WR_ORD;\n\t}\n\tif (CHIP_REV_IS_FPGA(sc)) {\n\t\tECORE_MSG(\"write order adjusted to 1 for FPGA\");\n\t\tw_order = 0;\n\t}\n\tECORE_MSG(\"read order %d write order %d\", r_order, w_order);\n\n\tfor (i = 0; i < NUM_RD_Q-1; i++) {\n\t\tREG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l);\n\t\tREG_WR(sc, read_arb_addr[i].add,\n\t\t read_arb_data[i][r_order].add);\n\t\tREG_WR(sc, read_arb_addr[i].ubound,\n\t\t read_arb_data[i][r_order].ubound);\n\t}\n\n\tfor (i = 0; i < NUM_WR_Q-1; i++) {\n\t\tif ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||\n\t\t (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {\n\n\t\t\tREG_WR(sc, write_arb_addr[i].l,\n\t\t\t write_arb_data[i][w_order].l);\n\n\t\t\tREG_WR(sc, write_arb_addr[i].add,\n\t\t\t write_arb_data[i][w_order].add);\n\n\t\t\tREG_WR(sc, write_arb_addr[i].ubound,\n\t\t\t write_arb_data[i][w_order].ubound);\n\t\t} else {\n\n\t\t\tval = REG_RD(sc, write_arb_addr[i].l);\n\t\t\tREG_WR(sc, write_arb_addr[i].l,\n\t\t\t val | (write_arb_data[i][w_order].l << 10));\n\n\t\t\tval = REG_RD(sc, write_arb_addr[i].add);\n\t\t\tREG_WR(sc, write_arb_addr[i].add,\n\t\t\t val | (write_arb_data[i][w_order].add << 10));\n\n\t\t\tval = REG_RD(sc, write_arb_addr[i].ubound);\n\t\t\tREG_WR(sc, write_arb_addr[i].ubound,\n\t\t\t val | (write_arb_data[i][w_order].ubound << 7));\n\t\t}\n\t}\n\n\tval = write_arb_data[NUM_WR_Q-1][w_order].add;\n\tval += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;\n\tval += write_arb_data[NUM_WR_Q-1][w_order].l << 17;\n\tREG_WR(sc, PXP2_REG_PSWRQ_BW_RD, val);\n\n\tval = read_arb_data[NUM_RD_Q-1][r_order].add;\n\tval += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;\n\tval += read_arb_data[NUM_RD_Q-1][r_order].l << 17;\n\tREG_WR(sc, PXP2_REG_PSWRQ_BW_WR, val);\n\n\tREG_WR(sc, PXP2_REG_RQ_WR_MBS0, w_order);\n\tREG_WR(sc, PXP2_REG_RQ_WR_MBS1, w_order);\n\tREG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);\n\tREG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);\n\n\tif (CHIP_IS_E1H(sc) && (r_order == MAX_RD_ORD))\n\t\tREG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);\n\n\tif (CHIP_IS_E3(sc))\n\t\tREG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));\n\telse if (CHIP_IS_E2(sc))\n\t\tREG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));\n\telse\n\t\tREG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));\n\n\t/* MPS w_order optimal TH presently TH\n\t * 128 0 0 2\n\t * 256 1 1 3\n\t * >=512 2 2 3\n\t */\n\t/* DMAE is special */\n\tif (!CHIP_IS_E1H(sc)) {\n\t\t/* E2 can use optimal TH */\n\t\tval = w_order;\n\t\tREG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);\n\t} else {\n\t\tval = ((w_order == 0) ? 2 : 3);\n\t\tREG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);\n\t}\n\n\tREG_WR(sc, PXP2_REG_WR_HC_MPS, val);\n\tREG_WR(sc, PXP2_REG_WR_USDM_MPS, val);\n\tREG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);\n\tREG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);\n\tREG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);\n\tREG_WR(sc, PXP2_REG_WR_QM_MPS, val);\n\tREG_WR(sc, PXP2_REG_WR_TM_MPS, val);\n\tREG_WR(sc, PXP2_REG_WR_SRC_MPS, val);\n\tREG_WR(sc, PXP2_REG_WR_DBG_MPS, val);\n\tREG_WR(sc, PXP2_REG_WR_CDU_MPS, val);\n\n\t/* Validate number of tags suppoted by device */\n#define PCIE_REG_PCIER_TL_HDR_FC_ST\t\t0x2980\n\tval = REG_RD(sc, PCIE_REG_PCIER_TL_HDR_FC_ST);\n\tval &= 0xFF;\n\tif (val <= 0x20)\n\t\tREG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x20);\n}\n\n/****************************************************************************\n* ILT management\n****************************************************************************/\n/*\n * This codes hides the low level HW interaction for ILT management and\n * configuration. The API consists of a shadow ILT table which is set by the\n * driver and a set of routines to use it to configure the HW.\n *\n */\n\n/* ILT HW init operations */\n\n/* ILT memory management operations */\n#define ILT_MEMOP_ALLOC\t\t0\n#define ILT_MEMOP_FREE\t\t1\n\n/* the phys address is shifted right 12 bits and has an added\n * 1=valid bit added to the 53rd bit\n * then since this is a wide register(TM)\n * we split it into two 32 bit writes\n */\n#define ILT_ADDR1(x)\t\t((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))\n#define ILT_ADDR2(x)\t\t((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))\n#define ILT_RANGE(f, l)\t\t(((l) << 10) | f)\n\nstatic int ecore_ilt_line_mem_op(struct bnx2x_softc *sc,\n\t\t\t\t struct ilt_line *line, uint32_t size, uint8_t memop, int cli_num, int i)\n{\n#define ECORE_ILT_NAMESIZE 10\n\tchar str[ECORE_ILT_NAMESIZE];\n\n\tif (memop == ILT_MEMOP_FREE) {\n\t\tECORE_ILT_FREE(line->page, line->page_mapping, line->size);\n\t\treturn 0;\n\t}\n\tsnprintf(str, ECORE_ILT_NAMESIZE, \"ILT_%d_%d\", cli_num, i);\n\tECORE_ILT_ZALLOC(line->page, &line->page_mapping, size, str);\n\tif (!line->page)\n\t\treturn -1;\n\tline->size = size;\n\treturn 0;\n}\n\n\nstatic int ecore_ilt_client_mem_op(struct bnx2x_softc *sc, int cli_num,\n\t\t\t\t uint8_t memop)\n{\n\tint i, rc = 0;\n\tstruct ecore_ilt *ilt = SC_ILT(sc);\n\tstruct ilt_client_info *ilt_cli = &ilt->clients[cli_num];\n\n\tif (!ilt || !ilt->lines)\n\t\treturn -1;\n\n\tif (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))\n\t\treturn 0;\n\n\tfor (i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {\n\t\trc = ecore_ilt_line_mem_op(sc, &ilt->lines[i],\n\t\t\t\t\t ilt_cli->page_size, memop, cli_num, i);\n\t}\n\treturn rc;\n}\n\nstatic inline int ecore_ilt_mem_op_cnic(struct bnx2x_softc *sc, uint8_t memop)\n{\n\tint rc = 0;\n\n\tif (CONFIGURE_NIC_MODE(sc))\n\t\trc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);\n\tif (!rc)\n\t\trc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_TM, memop);\n\n\treturn rc;\n}\n\nstatic int ecore_ilt_mem_op(struct bnx2x_softc *sc, uint8_t memop)\n{\n\tint rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_CDU, memop);\n\tif (!rc)\n\t\trc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_QM, memop);\n\tif (!rc && CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc))\n\t\trc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);\n\n\treturn rc;\n}\n\nstatic void ecore_ilt_line_wr(struct bnx2x_softc *sc, int abs_idx,\n\t\t\t ecore_dma_addr_t page_mapping)\n{\n\tuint32_t reg;\n\n\treg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;\n\n\tecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));\n}\n\nstatic void ecore_ilt_line_init_op(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_ilt *ilt, int idx, uint8_t initop)\n{\n\tecore_dma_addr_t\tnull_mapping;\n\tint abs_idx = ilt->start_line + idx;\n\n\tswitch (initop) {\n\tcase INITOP_INIT:\n\t\t/* set in the init-value array */\n\tcase INITOP_SET:\n\t\tecore_ilt_line_wr(sc, abs_idx, ilt->lines[idx].page_mapping);\n\t\tbreak;\n\tcase INITOP_CLEAR:\n\t\tnull_mapping = 0;\n\t\tecore_ilt_line_wr(sc, abs_idx, null_mapping);\n\t\tbreak;\n\t}\n}\n\nstatic void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc,\n\t\t\t\t struct ilt_client_info *ilt_cli,\n\t\t\t\t uint32_t ilt_start)\n{\n\tuint32_t start_reg = 0;\n\tuint32_t end_reg = 0;\n\n\t/* The boundary is either SET or INIT,\n\t CLEAR => SET and for now SET ~~ INIT */\n\n\t/* find the appropriate regs */\n\tswitch (ilt_cli->client_num) {\n\t\tcase ILT_CLIENT_CDU:\n\t\t\tstart_reg = PXP2_REG_RQ_CDU_FIRST_ILT;\n\t\t\tend_reg = PXP2_REG_RQ_CDU_LAST_ILT;\n\t\t\tbreak;\n\t\tcase ILT_CLIENT_QM:\n\t\t\tstart_reg = PXP2_REG_RQ_QM_FIRST_ILT;\n\t\t\tend_reg = PXP2_REG_RQ_QM_LAST_ILT;\n\t\t\tbreak;\n\t\tcase ILT_CLIENT_SRC:\n\t\t\tstart_reg = PXP2_REG_RQ_SRC_FIRST_ILT;\n\t\t\tend_reg = PXP2_REG_RQ_SRC_LAST_ILT;\n\t\t\tbreak;\n\t\tcase ILT_CLIENT_TM:\n\t\t\tstart_reg = PXP2_REG_RQ_TM_FIRST_ILT;\n\t\t\tend_reg = PXP2_REG_RQ_TM_LAST_ILT;\n\t\t\tbreak;\n\t}\n\tREG_WR(sc, start_reg, (ilt_start + ilt_cli->start));\n\tREG_WR(sc, end_reg, (ilt_start + ilt_cli->end));\n}\n\nstatic void ecore_ilt_client_init_op_ilt(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_ilt *ilt,\n\t\t\t\t\t struct ilt_client_info *ilt_cli,\n\t\t\t\t\t uint8_t initop)\n{\n\tint i;\n\n\tif (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)\n\t\treturn;\n\n\tfor (i = ilt_cli->start; i <= ilt_cli->end; i++)\n\t\tecore_ilt_line_init_op(sc, ilt, i, initop);\n\n\t/* init/clear the ILT boundries */\n\tecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line);\n}\n\nstatic void ecore_ilt_client_init_op(struct bnx2x_softc *sc,\n\t\t\t\t struct ilt_client_info *ilt_cli, uint8_t initop)\n{\n\tstruct ecore_ilt *ilt = SC_ILT(sc);\n\n\tecore_ilt_client_init_op_ilt(sc, ilt, ilt_cli, initop);\n}\n\nstatic void ecore_ilt_client_id_init_op(struct bnx2x_softc *sc,\n\t\t\t\t\tint cli_num, uint8_t initop)\n{\n\tstruct ecore_ilt *ilt = SC_ILT(sc);\n\tstruct ilt_client_info *ilt_cli = &ilt->clients[cli_num];\n\n\tecore_ilt_client_init_op(sc, ilt_cli, initop);\n}\n\nstatic inline void ecore_ilt_init_op_cnic(struct bnx2x_softc *sc, uint8_t initop)\n{\n\tif (CONFIGURE_NIC_MODE(sc))\n\t\tecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);\n\tecore_ilt_client_id_init_op(sc, ILT_CLIENT_TM, initop);\n}\n\nstatic void ecore_ilt_init_op(struct bnx2x_softc *sc, uint8_t initop)\n{\n\tecore_ilt_client_id_init_op(sc, ILT_CLIENT_CDU, initop);\n\tecore_ilt_client_id_init_op(sc, ILT_CLIENT_QM, initop);\n\tif (CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc))\n\t\tecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);\n}\n\nstatic void ecore_ilt_init_client_psz(struct bnx2x_softc *sc, int cli_num,\n\t\t\t\t uint32_t psz_reg, uint8_t initop)\n{\n\tstruct ecore_ilt *ilt = SC_ILT(sc);\n\tstruct ilt_client_info *ilt_cli = &ilt->clients[cli_num];\n\n\tif (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)\n\t\treturn;\n\n\tswitch (initop) {\n\tcase INITOP_INIT:\n\t\t/* set in the init-value array */\n\tcase INITOP_SET:\n\t\tREG_WR(sc, psz_reg, ILOG2(ilt_cli->page_size >> 12));\n\t\tbreak;\n\tcase INITOP_CLEAR:\n\t\tbreak;\n\t}\n}\n\n/*\n * called during init common stage, ilt clients should be initialized\n * prioir to calling this function\n */\nstatic void ecore_ilt_init_page_size(struct bnx2x_softc *sc, uint8_t initop)\n{\n\tecore_ilt_init_client_psz(sc, ILT_CLIENT_CDU,\n\t\t\t\t PXP2_REG_RQ_CDU_P_SIZE, initop);\n\tecore_ilt_init_client_psz(sc, ILT_CLIENT_QM,\n\t\t\t\t PXP2_REG_RQ_QM_P_SIZE, initop);\n\tecore_ilt_init_client_psz(sc, ILT_CLIENT_SRC,\n\t\t\t\t PXP2_REG_RQ_SRC_P_SIZE, initop);\n\tecore_ilt_init_client_psz(sc, ILT_CLIENT_TM,\n\t\t\t\t PXP2_REG_RQ_TM_P_SIZE, initop);\n}\n\n/****************************************************************************\n* QM initializations\n****************************************************************************/\n#define QM_QUEUES_PER_FUNC\t16\n#define QM_INIT_MIN_CID_COUNT\t31\n#define QM_INIT(cid_cnt)\t(cid_cnt > QM_INIT_MIN_CID_COUNT)\n\n/* called during init port stage */\nstatic void ecore_qm_init_cid_count(struct bnx2x_softc *sc, int qm_cid_count,\n\t\t\t\t uint8_t initop)\n{\n\tint port = SC_PORT(sc);\n\n\tif (QM_INIT(qm_cid_count)) {\n\t\tswitch (initop) {\n\t\tcase INITOP_INIT:\n\t\t\t/* set in the init-value array */\n\t\tcase INITOP_SET:\n\t\t\tREG_WR(sc, QM_REG_CONNNUM_0 + port*4,\n\t\t\t qm_cid_count/16 - 1);\n\t\t\tbreak;\n\t\tcase INITOP_CLEAR:\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\nstatic void ecore_qm_set_ptr_table(struct bnx2x_softc *sc, int qm_cid_count,\n\t\t\t\t uint32_t base_reg, uint32_t reg)\n{\n\tint i;\n\tuint32_t wb_data[2] = {0, 0};\n\tfor (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {\n\t\tREG_WR(sc, base_reg + i*4,\n\t\t qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));\n\t\tecore_init_wr_wb(sc, reg + i*8,\n\t\t\t\t wb_data, 2);\n\t}\n}\n\n/* called during init common stage */\nstatic void ecore_qm_init_ptr_table(struct bnx2x_softc *sc, int qm_cid_count,\n\t\t\t\t uint8_t initop)\n{\n\tif (!QM_INIT(qm_cid_count))\n\t\treturn;\n\n\tswitch (initop) {\n\tcase INITOP_INIT:\n\t\t/* set in the init-value array */\n\tcase INITOP_SET:\n\t\tecore_qm_set_ptr_table(sc, qm_cid_count,\n\t\t\t\t QM_REG_BASEADDR, QM_REG_PTRTBL);\n\t\tif (CHIP_IS_E1H(sc))\n\t\t\tecore_qm_set_ptr_table(sc, qm_cid_count,\n\t\t\t\t\t QM_REG_BASEADDR_EXT_A,\n\t\t\t\t\t QM_REG_PTRTBL_EXT_A);\n\t\tbreak;\n\tcase INITOP_CLEAR:\n\t\tbreak;\n\t}\n}\n\n/****************************************************************************\n* SRC initializations\n****************************************************************************/\n#ifdef ECORE_L5\n/* called during init func stage */\nstatic void ecore_src_init_t2(struct bnx2x_softc *sc, struct src_ent *t2,\n\t\t\t ecore_dma_addr_t t2_mapping, int src_cid_count)\n{\n\tint i;\n\tint port = SC_PORT(sc);\n\n\t/* Initialize T2 */\n\tfor (i = 0; i < src_cid_count-1; i++)\n\t\tt2[i].next = (uint64_t)(t2_mapping +\n\t\t\t (i+1)*sizeof(struct src_ent));\n\n\t/* tell the searcher where the T2 table is */\n\tREG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count);\n\n\tecore_wr_64(sc, SRC_REG_FIRSTFREE0 + port*16,\n\t\t U64_LO(t2_mapping), U64_HI(t2_mapping));\n\n\tecore_wr_64(sc, SRC_REG_LASTFREE0 + port*16,\n\t\t U64_LO((uint64_t)t2_mapping +\n\t\t\t (src_cid_count-1) * sizeof(struct src_ent)),\n\t\t U64_HI((uint64_t)t2_mapping +\n\t\t\t (src_cid_count-1) * sizeof(struct src_ent)));\n}\n#endif\n#endif /* ECORE_INIT_OPS_H */\n" }, { "path": "drivers/net/bnx2x/ecore_mfw_req.h", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ECORE_MFW_REQ_H\n#define ECORE_MFW_REQ_H\n\n\n\n#define PORT_0 0\n#define PORT_1 1\n#define PORT_MAX 2\n#define NVM_PATH_MAX 2\n\n/* FCoE capabilities required from the driver */\nstruct fcoe_capabilities {\n\tuint32_t capability1;\n\t/* Maximum number of I/Os per connection */\n\t#define FCOE_IOS_PER_CONNECTION_MASK 0x0000ffff\n\t#define FCOE_IOS_PER_CONNECTION_SHIFT 0\n\t/* Maximum number of Logins per port */\n\t#define FCOE_LOGINS_PER_PORT_MASK 0xffff0000\n\t#define FCOE_LOGINS_PER_PORT_SHIFT 16\n\n\tuint32_t capability2;\n\t/* Maximum number of exchanges */\n\t#define FCOE_NUMBER_OF_EXCHANGES_MASK 0x0000ffff\n\t#define FCOE_NUMBER_OF_EXCHANGES_SHIFT 0\n\t/* Maximum NPIV WWN per port */\n\t#define FCOE_NPIV_WWN_PER_PORT_MASK 0xffff0000\n\t#define FCOE_NPIV_WWN_PER_PORT_SHIFT 16\n\n\tuint32_t capability3;\n\t/* Maximum number of targets supported */\n\t#define FCOE_TARGETS_SUPPORTED_MASK 0x0000ffff\n\t#define FCOE_TARGETS_SUPPORTED_SHIFT 0\n\t/* Maximum number of outstanding commands across all connections */\n\t#define FCOE_OUTSTANDING_COMMANDS_MASK 0xffff0000\n\t#define FCOE_OUTSTANDING_COMMANDS_SHIFT 16\n\n\tuint32_t capability4;\n\t#define FCOE_CAPABILITY4_STATEFUL \t\t0x00000001\n\t#define FCOE_CAPABILITY4_STATELESS \t\t0x00000002\n\t#define FCOE_CAPABILITY4_CAPABILITIES_REPORTED_VALID \t0x00000004\n};\n\nstruct glob_ncsi_oem_data\n{\n\tuint32_t driver_version;\n\tuint32_t unused[3];\n\tstruct fcoe_capabilities fcoe_features[NVM_PATH_MAX][PORT_MAX];\n};\n\n/* current drv_info version */\n#define DRV_INFO_CUR_VER 2\n\n/* drv_info op codes supported */\nenum drv_info_opcode {\n\tETH_STATS_OPCODE,\n\tFCOE_STATS_OPCODE,\n\tISCSI_STATS_OPCODE\n};\n\n#define ETH_STAT_INFO_VERSION_LEN\t12\n/* Per PCI Function Ethernet Statistics required from the driver */\nstruct eth_stats_info {\n\t/* Function's Driver Version. padded to 12 */\n\tchar version[ETH_STAT_INFO_VERSION_LEN];\n\t/* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */\n\tuint8_t mac_local[8];\n\tuint8_t mac_add1[8];\t\t/* Additional Programmed MAC Addr 1. */\n\tuint8_t mac_add2[8];\t\t/* Additional Programmed MAC Addr 2. */\n\tuint32_t mtu_size;\t\t/* MTU Size. Note : Negotiated MTU */\n\tuint32_t feature_flags;\t/* Feature_Flags. */\n#define FEATURE_ETH_CHKSUM_OFFLOAD_MASK\t\t0x01\n#define FEATURE_ETH_LSO_MASK\t\t\t0x02\n#define FEATURE_ETH_BOOTMODE_MASK\t\t0x1C\n#define FEATURE_ETH_BOOTMODE_SHIFT\t\t2\n#define FEATURE_ETH_BOOTMODE_NONE\t\t(0x0 << 2)\n#define FEATURE_ETH_BOOTMODE_PXE\t\t(0x1 << 2)\n#define FEATURE_ETH_BOOTMODE_ISCSI\t\t(0x2 << 2)\n#define FEATURE_ETH_BOOTMODE_FCOE\t\t(0x3 << 2)\n#define FEATURE_ETH_TOE_MASK\t\t\t0x20\n\tuint32_t lso_max_size;\t/* LSO MaxOffloadSize. */\n\tuint32_t lso_min_seg_cnt;\t/* LSO MinSegmentCount. */\n\t/* Num Offloaded Connections TCP_IPv4. */\n\tuint32_t ipv4_ofld_cnt;\n\t/* Num Offloaded Connections TCP_IPv6. */\n\tuint32_t ipv6_ofld_cnt;\n\tuint32_t promiscuous_mode;\t/* Promiscuous Mode. non-zero true */\n\tuint32_t txq_size;\t\t/* TX Descriptors Queue Size */\n\tuint32_t rxq_size;\t\t/* RX Descriptors Queue Size */\n\t/* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */\n\tuint32_t txq_avg_depth;\n\t/* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */\n\tuint32_t rxq_avg_depth;\n\t/* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/\n\tuint32_t iov_offload;\n\t/* Number of NetQueue/VMQ Config'd. */\n\tuint32_t netq_cnt;\n\tuint32_t vf_cnt;\t\t/* Num VF assigned to this PF. */\n};\n\n/* Per PCI Function FCOE Statistics required from the driver */\nstruct fcoe_stats_info {\n\tuint8_t version[12];\t\t/* Function's Driver Version. */\n\tuint8_t mac_local[8];\t/* Locally Admin Addr. */\n\tuint8_t mac_add1[8];\t\t/* Additional Programmed MAC Addr 1. */\n\tuint8_t mac_add2[8];\t\t/* Additional Programmed MAC Addr 2. */\n\t/* QoS Priority (per 802.1p). 0-7255 */\n\tuint32_t qos_priority;\n\tuint32_t txq_size;\t\t/* FCoE TX Descriptors Queue Size. */\n\tuint32_t rxq_size;\t\t/* FCoE RX Descriptors Queue Size. */\n\t/* FCoE TX Descriptor Queue Avg Depth. */\n\tuint32_t txq_avg_depth;\n\t/* FCoE RX Descriptors Queue Avg Depth. */\n\tuint32_t rxq_avg_depth;\n\tuint32_t rx_frames_lo;\t/* FCoE RX Frames received. */\n\tuint32_t rx_frames_hi;\t/* FCoE RX Frames received. */\n\tuint32_t rx_bytes_lo;\t/* FCoE RX Bytes received. */\n\tuint32_t rx_bytes_hi;\t/* FCoE RX Bytes received. */\n\tuint32_t tx_frames_lo;\t/* FCoE TX Frames sent. */\n\tuint32_t tx_frames_hi;\t/* FCoE TX Frames sent. */\n\tuint32_t tx_bytes_lo;\t/* FCoE TX Bytes sent. */\n\tuint32_t tx_bytes_hi;\t/* FCoE TX Bytes sent. */\n\tuint32_t rx_fcs_errors;\t/* number of receive packets with FCS errors */\n\tuint32_t rx_fc_crc_errors;\t/* number of FC frames with CRC errors*/\n\tuint32_t fip_login_failures;\t/* number of FCoE/FIP Login failures */\n};\n\n/* Per PCI Function iSCSI Statistics required from the driver*/\nstruct iscsi_stats_info {\n\tuint8_t version[12];\t\t/* Function's Driver Version. */\n\tuint8_t mac_local[8];\t/* Locally Admin iSCSI MAC Addr. */\n\tuint8_t mac_add1[8];\t\t/* Additional Programmed MAC Addr 1. */\n\t/* QoS Priority (per 802.1p). 0-7255 */\n\tuint32_t qos_priority;\n\n\tuint8_t initiator_name[64];\t/* iSCSI Boot Initiator Node name. */\n\n\tuint8_t ww_port_name[64];\t/* iSCSI World wide port name */\n\n\tuint8_t boot_target_name[64];/* iSCSI Boot Target Name. */\n\n\tuint8_t boot_target_ip[16];\t/* iSCSI Boot Target IP. */\n\tuint32_t boot_target_portal;\t/* iSCSI Boot Target Portal. */\n\tuint8_t boot_init_ip[16];\t/* iSCSI Boot Initiator IP Address. */\n\tuint32_t max_frame_size;\t/* Max Frame Size. bytes */\n\tuint32_t txq_size;\t\t/* PDU TX Descriptors Queue Size. */\n\tuint32_t rxq_size;\t\t/* PDU RX Descriptors Queue Size. */\n\n\tuint32_t txq_avg_depth;\t/*PDU TX Descriptor Queue Avg Depth. */\n\tuint32_t rxq_avg_depth;\t/*PDU RX Descriptors Queue Avg Depth. */\n\tuint32_t rx_pdus_lo;\t\t/* iSCSI PDUs received. */\n\tuint32_t rx_pdus_hi;\t\t/* iSCSI PDUs received. */\n\n\tuint32_t rx_bytes_lo;\t/* iSCSI RX Bytes received. */\n\tuint32_t rx_bytes_hi;\t/* iSCSI RX Bytes received. */\n\tuint32_t tx_pdus_lo;\t\t/* iSCSI PDUs sent. */\n\tuint32_t tx_pdus_hi;\t\t/* iSCSI PDUs sent. */\n\n\tuint32_t tx_bytes_lo;\t/* iSCSI PDU TX Bytes sent. */\n\tuint32_t tx_bytes_hi;\t/* iSCSI PDU TX Bytes sent. */\n\tuint32_t pcp_prior_map_tbl;\t/*C-PCP to S-PCP Priority MapTable.\n\t\t\t\t9 nibbles, the position of each nibble\n\t\t\t\trepresents the C-PCP value, the value\n\t\t\t\tof the nibble = S-PCP value.*/\n};\n\nunion drv_info_to_mcp {\n\tstruct eth_stats_info\t\tether_stat;\n\tstruct fcoe_stats_info\t\tfcoe_stat;\n\tstruct iscsi_stats_info\t\tiscsi_stat;\n};\n\n\n#endif /* ECORE_MFW_REQ_H */\n" }, { "path": "drivers/net/bnx2x/ecore_reg.h", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ECORE_REG_H\n#define ECORE_REG_H\n\n\n#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR \\\n\t(0x1<<0)\n#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS \\\n\t(0x1<<2)\n#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU \\\n\t(0x1<<5)\n#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT \\\n\t(0x1<<3)\n#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR \\\n\t(0x1<<4)\n#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND \\\n\t(0x1<<1)\n#define ATC_REG_ATC_INIT_DONE \\\n\t0x1100bcUL\n#define ATC_REG_ATC_INT_STS_CLR \\\n\t0x1101c0UL\n#define ATC_REG_ATC_PRTY_MASK \\\n\t0x1101d8UL\n#define ATC_REG_ATC_PRTY_STS_CLR \\\n\t0x1101d0UL\n#define BRB1_REG_BRB1_INT_MASK \\\n\t0x60128UL\n#define BRB1_REG_BRB1_PRTY_MASK \\\n\t0x60138UL\n#define BRB1_REG_BRB1_PRTY_STS_CLR \\\n\t0x60130UL\n#define BRB1_REG_MAC_GUARANTIED_0 \\\n\t0x601e8UL\n#define BRB1_REG_MAC_GUARANTIED_1 \\\n\t0x60240UL\n#define BRB1_REG_NUM_OF_FULL_BLOCKS \\\n\t0x60090UL\n#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 \\\n\t0x60078UL\n#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 \\\n\t0x60068UL\n#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 \\\n\t0x60094UL\n#define CCM_REG_CCM_INT_MASK \\\n\t0xd01e4UL\n#define CCM_REG_CCM_PRTY_MASK \\\n\t0xd01f4UL\n#define CCM_REG_CCM_PRTY_STS_CLR \\\n\t0xd01ecUL\n#define CDU_REG_CDU_GLOBAL_PARAMS \\\n\t0x101020UL\n#define CDU_REG_CDU_INT_MASK \\\n\t0x10103cUL\n#define CDU_REG_CDU_PRTY_MASK \\\n\t0x10104cUL\n#define CDU_REG_CDU_PRTY_STS_CLR \\\n\t0x101044UL\n#define CFC_REG_AC_INIT_DONE \\\n\t0x104078UL\n#define CFC_REG_CAM_INIT_DONE \\\n\t0x10407cUL\n#define CFC_REG_CFC_INT_MASK \\\n\t0x104108UL\n#define CFC_REG_CFC_INT_STS_CLR \\\n\t0x104100UL\n#define CFC_REG_CFC_PRTY_MASK \\\n\t0x104118UL\n#define CFC_REG_CFC_PRTY_STS_CLR \\\n\t0x104110UL\n#define CFC_REG_DEBUG0 \\\n\t0x104050UL\n#define CFC_REG_INIT_REG \\\n\t0x10404cUL\n#define CFC_REG_LL_INIT_DONE \\\n\t0x104074UL\n#define CFC_REG_NUM_LCIDS_INSIDE_PF \\\n\t0x104120UL\n#define CFC_REG_STRONG_ENABLE_PF \\\n\t0x104128UL\n#define CFC_REG_WEAK_ENABLE_PF \\\n\t0x104124UL\n#define CSDM_REG_CSDM_INT_MASK_0 \\\n\t0xc229cUL\n#define CSDM_REG_CSDM_INT_MASK_1 \\\n\t0xc22acUL\n#define CSDM_REG_CSDM_PRTY_MASK \\\n\t0xc22bcUL\n#define CSDM_REG_CSDM_PRTY_STS_CLR \\\n\t0xc22b4UL\n#define CSEM_REG_CSEM_INT_MASK_0 \\\n\t0x200110UL\n#define CSEM_REG_CSEM_INT_MASK_1 \\\n\t0x200120UL\n#define CSEM_REG_CSEM_PRTY_MASK_0 \\\n\t0x200130UL\n#define CSEM_REG_CSEM_PRTY_MASK_1 \\\n\t0x200140UL\n#define CSEM_REG_CSEM_PRTY_STS_CLR_0 \\\n\t0x200128UL\n#define CSEM_REG_CSEM_PRTY_STS_CLR_1 \\\n\t0x200138UL\n#define CSEM_REG_FAST_MEMORY \\\n\t0x220000UL\n#define CSEM_REG_INT_TABLE \\\n\t0x200400UL\n#define CSEM_REG_PASSIVE_BUFFER \\\n\t0x202000UL\n#define CSEM_REG_PRAM \\\n\t0x240000UL\n#define CSEM_REG_VFPF_ERR_NUM \\\n\t0x200380UL\n#define DBG_REG_DBG_PRTY_MASK \\\n\t0xc0a8UL\n#define DBG_REG_DBG_PRTY_STS_CLR \\\n\t0xc0a0UL\n#define DMAE_REG_BACKWARD_COMP_EN \\\n\t0x10207cUL\n#define DMAE_REG_CMD_MEM \\\n\t0x102400UL\n#define DMAE_REG_DMAE_INT_MASK \\\n\t0x102054UL\n#define DMAE_REG_DMAE_PRTY_MASK \\\n\t0x102064UL\n#define DMAE_REG_DMAE_PRTY_STS_CLR \\\n\t0x10205cUL\n#define DMAE_REG_GO_C0 \\\n\t0x102080UL\n#define DMAE_REG_GO_C1 \\\n\t0x102084UL\n#define DMAE_REG_GO_C10 \\\n\t0x102088UL\n#define DMAE_REG_GO_C11 \\\n\t0x10208cUL\n#define DMAE_REG_GO_C12 \\\n\t0x102090UL\n#define DMAE_REG_GO_C13 \\\n\t0x102094UL\n#define DMAE_REG_GO_C14 \\\n\t0x102098UL\n#define DMAE_REG_GO_C15 \\\n\t0x10209cUL\n#define DMAE_REG_GO_C2 \\\n\t0x1020a0UL\n#define DMAE_REG_GO_C3 \\\n\t0x1020a4UL\n#define DMAE_REG_GO_C4 \\\n\t0x1020a8UL\n#define DMAE_REG_GO_C5 \\\n\t0x1020acUL\n#define DMAE_REG_GO_C6 \\\n\t0x1020b0UL\n#define DMAE_REG_GO_C7 \\\n\t0x1020b4UL\n#define DMAE_REG_GO_C8 \\\n\t0x1020b8UL\n#define DMAE_REG_GO_C9 \\\n\t0x1020bcUL\n#define DORQ_REG_DORQ_INT_MASK \\\n\t0x170180UL\n#define DORQ_REG_DORQ_INT_STS_CLR \\\n\t0x170178UL\n#define DORQ_REG_DORQ_PRTY_MASK \\\n\t0x170190UL\n#define DORQ_REG_DORQ_PRTY_STS_CLR \\\n\t0x170188UL\n#define DORQ_REG_DPM_CID_OFST \\\n\t0x170030UL\n#define DORQ_REG_MAX_RVFID_SIZE \\\n\t0x1701ecUL\n#define DORQ_REG_NORM_CID_OFST \\\n\t0x17002cUL\n#define DORQ_REG_PF_USAGE_CNT \\\n\t0x1701d0UL\n#define DORQ_REG_VF_NORM_CID_BASE \\\n\t0x1701a0UL\n#define DORQ_REG_VF_NORM_CID_OFST \\\n\t0x1701f4UL\n#define DORQ_REG_VF_NORM_CID_WND_SIZE \\\n\t0x1701a4UL\n#define DORQ_REG_VF_NORM_MAX_CID_COUNT \\\n\t0x1701e4UL\n#define DORQ_REG_VF_NORM_VF_BASE \\\n\t0x1701a8UL\n#define DORQ_REG_VF_TYPE_MASK_0 \\\n\t0x170218UL\n#define DORQ_REG_VF_TYPE_MAX_MCID_0 \\\n\t0x1702d8UL\n#define DORQ_REG_VF_TYPE_MIN_MCID_0 \\\n\t0x170298UL\n#define DORQ_REG_VF_TYPE_VALUE_0 \\\n\t0x170258UL\n#define DORQ_REG_VF_USAGE_CNT \\\n\t0x170320UL\n#define DORQ_REG_VF_USAGE_CT_LIMIT \\\n\t0x170340UL\n#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 \\\n\t(0x1<<4)\n#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 \\\n\t(0x1<<0)\n#define HC_CONFIG_0_REG_INT_LINE_EN_0 \\\n\t(0x1<<3)\n#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 \\\n\t(0x1<<7)\n#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 \\\n\t(0x1<<2)\n#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 \\\n\t(0x1<<1)\n#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 \\\n\t(0x1<<0)\n#define HC_REG_ATTN_MSG0_ADDR_L \\\n\t0x108018UL\n#define HC_REG_ATTN_MSG1_ADDR_L \\\n\t0x108020UL\n#define HC_REG_COMMAND_REG \\\n\t0x108180UL\n#define HC_REG_CONFIG_0 \\\n\t0x108000UL\n#define HC_REG_CONFIG_1 \\\n\t0x108004UL\n#define HC_REG_HC_PRTY_MASK \\\n\t0x1080a0UL\n#define HC_REG_HC_PRTY_STS_CLR \\\n\t0x108098UL\n#define HC_REG_INT_MASK \\\n\t0x108108UL\n#define HC_REG_LEADING_EDGE_0 \\\n\t0x108040UL\n#define HC_REG_MAIN_MEMORY \\\n\t0x108800UL\n#define HC_REG_MAIN_MEMORY_SIZE \\\n\t152\n#define HC_REG_TRAILING_EDGE_0 \\\n\t0x108044UL\n#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN \\\n\t(0x1<<1)\n#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE \\\n\t(0x1<<0)\n#define IGU_REG_ATTENTION_ACK_BITS \\\n\t0x130108UL\n#define IGU_REG_ATTN_MSG_ADDR_H \\\n\t0x13011cUL\n#define IGU_REG_ATTN_MSG_ADDR_L \\\n\t0x130120UL\n#define IGU_REG_BLOCK_CONFIGURATION \\\n\t0x130000UL\n#define IGU_REG_COMMAND_REG_32LSB_DATA \\\n\t0x130124UL\n#define IGU_REG_COMMAND_REG_CTRL \\\n\t0x13012cUL\n#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP \\\n\t0x130200UL\n#define IGU_REG_IGU_PRTY_MASK \\\n\t0x1300a8UL\n#define IGU_REG_IGU_PRTY_STS_CLR \\\n\t0x1300a0UL\n#define IGU_REG_LEADING_EDGE_LATCH \\\n\t0x130134UL\n#define IGU_REG_MAPPING_MEMORY \\\n\t0x131000UL\n#define IGU_REG_MAPPING_MEMORY_SIZE \\\n\t136\n#define IGU_REG_PBA_STATUS_LSB \\\n\t0x130138UL\n#define IGU_REG_PBA_STATUS_MSB \\\n\t0x13013cUL\n#define IGU_REG_PCI_PF_MSIX_EN \\\n\t0x130144UL\n#define IGU_REG_PCI_PF_MSIX_FUNC_MASK \\\n\t0x130148UL\n#define IGU_REG_PCI_PF_MSI_EN \\\n\t0x130140UL\n#define IGU_REG_PENDING_BITS_STATUS \\\n\t0x130300UL\n#define IGU_REG_PF_CONFIGURATION \\\n\t0x130154UL\n#define IGU_REG_PROD_CONS_MEMORY \\\n\t0x132000UL\n#define IGU_REG_RESET_MEMORIES \\\n\t0x130158UL\n#define IGU_REG_SB_INT_BEFORE_MASK_LSB \\\n\t0x13015cUL\n#define IGU_REG_SB_INT_BEFORE_MASK_MSB \\\n\t0x130160UL\n#define IGU_REG_SB_MASK_LSB \\\n\t0x130164UL\n#define IGU_REG_SB_MASK_MSB \\\n\t0x130168UL\n#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT \\\n\t0x130800UL\n#define IGU_REG_TRAILING_EDGE_LATCH \\\n\t0x130104UL\n#define IGU_REG_VF_CONFIGURATION \\\n\t0x130170UL\n#define MCP_REG_MCPR_ACCESS_LOCK \\\n\t0x8009c\n#define MCP_REG_MCPR_GP_INPUTS \\\n\t0x800c0\n#define MCP_REG_MCPR_GP_OENABLE \\\n\t0x800c8\n#define MCP_REG_MCPR_GP_OUTPUTS \\\n\t0x800c4\n#define MCP_REG_MCPR_IMC_COMMAND \\\n\t0x85900\n#define MCP_REG_MCPR_IMC_DATAREG0 \\\n\t0x85920\n#define MCP_REG_MCPR_IMC_SLAVE_CONTROL \\\n\t0x85904\n#define MCP_REG_MCPR_NVM_ACCESS_ENABLE \\\n\t0x86424\n#define MCP_REG_MCPR_NVM_ADDR \\\n\t0x8640c\n#define MCP_REG_MCPR_NVM_CFG4 \\\n\t0x8642c\n#define MCP_REG_MCPR_NVM_COMMAND \\\n\t0x86400\n#define MCP_REG_MCPR_NVM_READ \\\n\t0x86410\n#define MCP_REG_MCPR_NVM_SW_ARB \\\n\t0x86420\n#define MCP_REG_MCPR_NVM_WRITE \\\n\t0x86408\n#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK \\\n\t(0x1<<1)\n#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK \\\n\t(0x1<<0)\n#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 \\\n\t0xa42cUL\n#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 \\\n\t0xa438UL\n#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 \\\n\t0xa444UL\n#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 \\\n\t0xa450UL\n#define MISC_REG_AEU_AFTER_INVERT_4_MCP \\\n\t0xa458UL\n#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 \\\n\t0xa700UL\n#define MISC_REG_AEU_CLR_LATCH_SIGNAL \\\n\t0xa45cUL\n#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 \\\n\t0xa06cUL\n#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 \\\n\t0xa07cUL\n#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 \\\n\t0xa08cUL\n#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 \\\n\t0xa10cUL\n#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 \\\n\t0xa11cUL\n#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 \\\n\t0xa12cUL\n#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 \\\n\t0xa078UL\n#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 \\\n\t0xa118UL\n#define MISC_REG_AEU_ENABLE4_NIG_0 \\\n\t0xa0f8UL\n#define MISC_REG_AEU_ENABLE4_NIG_1 \\\n\t0xa198UL\n#define MISC_REG_AEU_ENABLE4_PXP_0 \\\n\t0xa108UL\n#define MISC_REG_AEU_ENABLE4_PXP_1 \\\n\t0xa1a8UL\n#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 \\\n\t0xa688UL\n#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 \\\n\t0xa6b0UL\n#define MISC_REG_AEU_GENERAL_ATTN_0 \\\n\t0xa000UL\n#define MISC_REG_AEU_GENERAL_ATTN_1 \\\n\t0xa004UL\n#define MISC_REG_AEU_GENERAL_ATTN_10 \\\n\t0xa028UL\n#define MISC_REG_AEU_GENERAL_ATTN_11 \\\n\t0xa02cUL\n#define MISC_REG_AEU_GENERAL_ATTN_12 \\\n\t0xa030UL\n#define MISC_REG_AEU_GENERAL_ATTN_2 \\\n\t0xa008UL\n#define MISC_REG_AEU_GENERAL_ATTN_3 \\\n\t0xa00cUL\n#define MISC_REG_AEU_GENERAL_ATTN_4 \\\n\t0xa010UL\n#define MISC_REG_AEU_GENERAL_ATTN_5 \\\n\t0xa014UL\n#define MISC_REG_AEU_GENERAL_ATTN_6 \\\n\t0xa018UL\n#define MISC_REG_AEU_GENERAL_ATTN_7 \\\n\t0xa01cUL\n#define MISC_REG_AEU_GENERAL_ATTN_8 \\\n\t0xa020UL\n#define MISC_REG_AEU_GENERAL_ATTN_9 \\\n\t0xa024UL\n#define MISC_REG_AEU_GENERAL_MASK \\\n\t0xa61cUL\n#define MISC_REG_AEU_MASK_ATTN_FUNC_0 \\\n\t0xa060UL\n#define MISC_REG_AEU_MASK_ATTN_FUNC_1 \\\n\t0xa064UL\n#define MISC_REG_BOND_ID \\\n\t0xa400UL\n#define MISC_REG_CHIP_NUM \\\n\t0xa408UL\n#define MISC_REG_CHIP_REV \\\n\t0xa40cUL\n#define MISC_REG_CHIP_TYPE \\\n\t0xac60UL\n#define MISC_REG_CHIP_TYPE_57811_MASK \\\n\t(1<<1)\n#define MISC_REG_CPMU_LP_DR_ENABLE \\\n\t0xa858UL\n#define MISC_REG_CPMU_LP_FW_ENABLE_P0 \\\n\t0xa84cUL\n#define MISC_REG_CPMU_LP_IDLE_THR_P0 \\\n\t0xa8a0UL\n#define MISC_REG_CPMU_LP_MASK_ENT_P0 \\\n\t0xa880UL\n#define MISC_REG_CPMU_LP_MASK_EXT_P0 \\\n\t0xa888UL\n#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 \\\n\t0xa8b8UL\n#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 \\\n\t0xa8bcUL\n#define MISC_REG_DRIVER_CONTROL_1 \\\n\t0xa510UL\n#define MISC_REG_DRIVER_CONTROL_7 \\\n\t0xa3c8UL\n#define MISC_REG_FOUR_PORT_PATH_SWAP \\\n\t0xa75cUL\n#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR \\\n\t0xa738UL\n#define MISC_REG_FOUR_PORT_PORT_SWAP \\\n\t0xa754UL\n#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR \\\n\t0xa734UL\n#define MISC_REG_GENERIC_CR_0 \\\n\t0xa460UL\n#define MISC_REG_GENERIC_CR_1 \\\n\t0xa464UL\n#define MISC_REG_GENERIC_POR_1 \\\n\t0xa474UL\n#define MISC_REG_GEN_PURP_HWG \\\n\t0xa9a0UL\n#define MISC_REG_GPIO \\\n\t0xa490UL\n#define MISC_REG_GPIO_EVENT_EN \\\n\t0xa2bcUL\n#define MISC_REG_GPIO_INT \\\n\t0xa494UL\n#define MISC_REG_GRC_RSV_ATTN \\\n\t0xa3c0UL\n#define MISC_REG_GRC_TIMEOUT_ATTN \\\n\t0xa3c4UL\n#define MISC_REG_LCPLL_E40_PWRDWN \\\n\t0xaa74UL\n#define MISC_REG_LCPLL_E40_RESETB_ANA \\\n\t0xaa78UL\n#define MISC_REG_LCPLL_E40_RESETB_DIG \\\n\t0xaa7cUL\n#define MISC_REG_MISC_INT_MASK \\\n\t0xa388UL\n#define MISC_REG_MISC_PRTY_MASK \\\n\t0xa398UL\n#define MISC_REG_MISC_PRTY_STS_CLR \\\n\t0xa390UL\n#define MISC_REG_PORT4MODE_EN \\\n\t0xa750UL\n#define MISC_REG_PORT4MODE_EN_OVWR \\\n\t0xa720UL\n#define MISC_REG_RESET_REG_1 \\\n\t0xa580UL\n#define MISC_REG_RESET_REG_2 \\\n\t0xa590UL\n#define MISC_REG_SHARED_MEM_ADDR \\\n\t0xa2b4UL\n#define MISC_REG_SPIO \\\n\t0xa4fcUL\n#define MISC_REG_SPIO_EVENT_EN \\\n\t0xa2b8UL\n#define MISC_REG_SPIO_INT \\\n\t0xa500UL\n#define MISC_REG_TWO_PORT_PATH_SWAP \\\n\t0xa758UL\n#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR \\\n\t0xa72cUL\n#define MISC_REG_UNPREPARED \\\n\t0xa424UL\n#define MISC_REG_WC0_CTRL_PHY_ADDR \\\n\t0xa9ccUL\n#define MISC_REG_WC0_RESET \\\n\t0xac30UL\n#define MISC_REG_XMAC_CORE_PORT_MODE \\\n\t0xa964UL\n#define MISC_REG_XMAC_PHY_PORT_MODE \\\n\t0xa960UL\n#define MSTAT_REG_RX_STAT_GR64_LO \\\n\t0x200UL\n#define MSTAT_REG_TX_STAT_GTXPOK_LO \\\n\t0UL\n#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN \\\n\t(0x1<<0)\n#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN \\\n\t(0x1<<0)\n#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT \\\n\t(0x1<<0)\n#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS \\\n\t(0x1<<9)\n#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G \\\n\t(0x1<<15)\n#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS \\\n\t(0xf<<18)\n#define NIG_REG_BMAC0_IN_EN \\\n\t0x100acUL\n#define NIG_REG_BMAC0_OUT_EN \\\n\t0x100e0UL\n#define NIG_REG_BMAC0_PAUSE_OUT_EN \\\n\t0x10110UL\n#define NIG_REG_BMAC0_REGS_OUT_EN \\\n\t0x100e8UL\n#define NIG_REG_BRB0_PAUSE_IN_EN \\\n\t0x100c4UL\n#define NIG_REG_BRB1_PAUSE_IN_EN \\\n\t0x100c8UL\n#define NIG_REG_DEBUG_PACKET_LB \\\n\t0x10800UL\n#define NIG_REG_EGRESS_DRAIN0_MODE \\\n\t0x10060UL\n#define NIG_REG_EGRESS_EMAC0_OUT_EN \\\n\t0x10120UL\n#define NIG_REG_EGRESS_EMAC0_PORT \\\n\t0x10058UL\n#define NIG_REG_EMAC0_IN_EN \\\n\t0x100a4UL\n#define NIG_REG_EMAC0_PAUSE_OUT_EN \\\n\t0x10118UL\n#define NIG_REG_EMAC0_STATUS_MISC_MI_INT \\\n\t0x10494UL\n#define NIG_REG_INGRESS_BMAC0_MEM \\\n\t0x10c00UL\n#define NIG_REG_INGRESS_BMAC1_MEM \\\n\t0x11000UL\n#define NIG_REG_INGRESS_EOP_LB_EMPTY \\\n\t0x104e0UL\n#define NIG_REG_INGRESS_EOP_LB_FIFO \\\n\t0x104e4UL\n#define NIG_REG_LATCH_BC_0 \\\n\t0x16210UL\n#define NIG_REG_LATCH_STATUS_0 \\\n\t0x18000UL\n#define NIG_REG_LED_10G_P0 \\\n\t0x10320UL\n#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 \\\n\t0x10318UL\n#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 \\\n\t0x10310UL\n#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 \\\n\t0x10308UL\n#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 \\\n\t0x102f8UL\n#define NIG_REG_LED_CONTROL_TRAFFIC_P0 \\\n\t0x10300UL\n#define NIG_REG_LED_MODE_P0 \\\n\t0x102f0UL\n#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 \\\n\t0x16070UL\n#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 \\\n\t0x16074UL\n#define NIG_REG_LLFC_ENABLE_0 \\\n\t0x16208UL\n#define NIG_REG_LLFC_ENABLE_1 \\\n\t0x1620cUL\n#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 \\\n\t0x16058UL\n#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 \\\n\t0x1605cUL\n#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 \\\n\t0x16060UL\n#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 \\\n\t0x16064UL\n#define NIG_REG_LLFC_OUT_EN_0 \\\n\t0x160c8UL\n#define NIG_REG_LLFC_OUT_EN_1 \\\n\t0x160ccUL\n#define NIG_REG_LLH0_BRB1_DRV_MASK \\\n\t0x10244UL\n#define NIG_REG_LLH0_BRB1_DRV_MASK_MF \\\n\t0x16048UL\n#define NIG_REG_LLH0_BRB1_NOT_MCP \\\n\t0x1025cUL\n#define NIG_REG_LLH0_CLS_TYPE \\\n\t0x16080UL\n#define NIG_REG_LLH0_FUNC_EN \\\n\t0x160fcUL\n#define NIG_REG_LLH0_FUNC_MEM \\\n\t0x16180UL\n#define NIG_REG_LLH0_FUNC_MEM_ENABLE \\\n\t0x16140UL\n#define NIG_REG_LLH0_FUNC_VLAN_ID \\\n\t0x16100UL\n#define NIG_REG_LLH0_XCM_MASK \\\n\t0x10130UL\n#define NIG_REG_LLH1_BRB1_NOT_MCP \\\n\t0x102dcUL\n#define NIG_REG_LLH1_CLS_TYPE \\\n\t0x16084UL\n#define NIG_REG_LLH1_FUNC_MEM \\\n\t0x161c0UL\n#define NIG_REG_LLH1_FUNC_MEM_ENABLE \\\n\t0x16160UL\n#define NIG_REG_LLH1_FUNC_MEM_SIZE \\\n\t16\n#define NIG_REG_LLH1_MF_MODE \\\n\t0x18614UL\n#define NIG_REG_LLH1_XCM_MASK \\\n\t0x10134UL\n#define NIG_REG_LLH_E1HOV_MODE \\\n\t0x160d8UL\n#define NIG_REG_LLH_MF_MODE \\\n\t0x16024UL\n#define NIG_REG_MASK_INTERRUPT_PORT0 \\\n\t0x10330UL\n#define NIG_REG_MASK_INTERRUPT_PORT1 \\\n\t0x10334UL\n#define NIG_REG_NIG_EMAC0_EN \\\n\t0x1003cUL\n#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC \\\n\t0x10044UL\n#define NIG_REG_NIG_INT_STS_CLR_0 \\\n\t0x103b4UL\n#define NIG_REG_NIG_PRTY_MASK \\\n\t0x103dcUL\n#define NIG_REG_NIG_PRTY_MASK_0 \\\n\t0x183c8UL\n#define NIG_REG_NIG_PRTY_MASK_1 \\\n\t0x183d8UL\n#define NIG_REG_NIG_PRTY_STS_CLR \\\n\t0x103d4UL\n#define NIG_REG_NIG_PRTY_STS_CLR_0 \\\n\t0x183c0UL\n#define NIG_REG_NIG_PRTY_STS_CLR_1 \\\n\t0x183d0UL\n#define NIG_REG_P0_HDRS_AFTER_BASIC \\\n\t0x18038UL\n#define NIG_REG_P0_HWPFC_ENABLE \\\n\t0x18078UL\n#define NIG_REG_P0_LLH_FUNC_MEM2 \\\n\t0x18480UL\n#define NIG_REG_P0_MAC_IN_EN \\\n\t0x185acUL\n#define NIG_REG_P0_MAC_OUT_EN \\\n\t0x185b0UL\n#define NIG_REG_P0_MAC_PAUSE_OUT_EN \\\n\t0x185b4UL\n#define NIG_REG_P0_PKT_PRIORITY_TO_COS \\\n\t0x18054UL\n#define NIG_REG_P0_RX_COS0_PRIORITY_MASK \\\n\t0x18058UL\n#define NIG_REG_P0_RX_COS1_PRIORITY_MASK \\\n\t0x1805cUL\n#define NIG_REG_P0_RX_COS2_PRIORITY_MASK \\\n\t0x186b0UL\n#define NIG_REG_P0_RX_COS3_PRIORITY_MASK \\\n\t0x186b4UL\n#define NIG_REG_P0_RX_COS4_PRIORITY_MASK \\\n\t0x186b8UL\n#define NIG_REG_P0_RX_COS5_PRIORITY_MASK \\\n\t0x186bcUL\n#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP \\\n\t0x180f0UL\n#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB \\\n\t0x18688UL\n#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB \\\n\t0x1868cUL\n#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT \\\n\t0x180e8UL\n#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ \\\n\t0x180ecUL\n#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 \\\n\t0x1810cUL\n#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 \\\n\t0x18110UL\n#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 \\\n\t0x18114UL\n#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 \\\n\t0x18118UL\n#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 \\\n\t0x1811cUL\n#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 \\\n\t0x186a0UL\n#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 \\\n\t0x186a4UL\n#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 \\\n\t0x186a8UL\n#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 \\\n\t0x186acUL\n#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 \\\n\t0x180f8UL\n#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 \\\n\t0x180fcUL\n#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 \\\n\t0x18100UL\n#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 \\\n\t0x18104UL\n#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 \\\n\t0x18108UL\n#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 \\\n\t0x18690UL\n#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 \\\n\t0x18694UL\n#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 \\\n\t0x18698UL\n#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 \\\n\t0x1869cUL\n#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS \\\n\t0x180f4UL\n#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT \\\n\t0x180e4UL\n#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB \\\n\t0x18680UL\n#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB \\\n\t0x18684UL\n#define NIG_REG_P1_HDRS_AFTER_BASIC \\\n\t0x1818cUL\n#define NIG_REG_P1_HWPFC_ENABLE \\\n\t0x181d0UL\n#define NIG_REG_P1_LLH_FUNC_MEM2 \\\n\t0x184c0UL\n#define NIG_REG_P1_MAC_IN_EN \\\n\t0x185c0UL\n#define NIG_REG_P1_MAC_OUT_EN \\\n\t0x185c4UL\n#define NIG_REG_P1_MAC_PAUSE_OUT_EN \\\n\t0x185c8UL\n#define NIG_REG_P1_PKT_PRIORITY_TO_COS \\\n\t0x181a8UL\n#define NIG_REG_P1_RX_COS0_PRIORITY_MASK \\\n\t0x181acUL\n#define NIG_REG_P1_RX_COS1_PRIORITY_MASK \\\n\t0x181b0UL\n#define NIG_REG_P1_RX_COS2_PRIORITY_MASK \\\n\t0x186f8UL\n#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB \\\n\t0x186e8UL\n#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB \\\n\t0x186ecUL\n#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT \\\n\t0x18234UL\n#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ \\\n\t0x18238UL\n#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 \\\n\t0x18258UL\n#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 \\\n\t0x1825cUL\n#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 \\\n\t0x18260UL\n#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 \\\n\t0x18264UL\n#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 \\\n\t0x18268UL\n#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 \\\n\t0x186f4UL\n#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 \\\n\t0x18244UL\n#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 \\\n\t0x18248UL\n#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 \\\n\t0x1824cUL\n#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 \\\n\t0x18250UL\n#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 \\\n\t0x18254UL\n#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 \\\n\t0x186f0UL\n#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS \\\n\t0x18240UL\n#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB \\\n\t0x186e0UL\n#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB \\\n\t0x186e4UL\n#define NIG_REG_PAUSE_ENABLE_0 \\\n\t0x160c0UL\n#define NIG_REG_PAUSE_ENABLE_1 \\\n\t0x160c4UL\n#define NIG_REG_PORT_SWAP \\\n\t0x10394UL\n#define NIG_REG_PPP_ENABLE_0 \\\n\t0x160b0UL\n#define NIG_REG_PPP_ENABLE_1 \\\n\t0x160b4UL\n#define NIG_REG_PRS_REQ_IN_EN \\\n\t0x100b8UL\n#define NIG_REG_SERDES0_CTRL_MD_DEVAD \\\n\t0x10370UL\n#define NIG_REG_SERDES0_CTRL_MD_ST \\\n\t0x1036cUL\n#define NIG_REG_SERDES0_CTRL_PHY_ADDR \\\n\t0x10374UL\n#define NIG_REG_SERDES0_STATUS_LINK_STATUS \\\n\t0x10578UL\n#define NIG_REG_STAT0_BRB_DISCARD \\\n\t0x105f0UL\n#define NIG_REG_STAT0_BRB_TRUNCATE \\\n\t0x105f8UL\n#define NIG_REG_STAT0_EGRESS_MAC_PKT0 \\\n\t0x10750UL\n#define NIG_REG_STAT0_EGRESS_MAC_PKT1 \\\n\t0x10760UL\n#define NIG_REG_STAT1_BRB_DISCARD \\\n\t0x10628UL\n#define NIG_REG_STAT1_EGRESS_MAC_PKT0 \\\n\t0x107a0UL\n#define NIG_REG_STAT1_EGRESS_MAC_PKT1 \\\n\t0x107b0UL\n#define NIG_REG_STAT2_BRB_OCTET \\\n\t0x107e0UL\n#define NIG_REG_STATUS_INTERRUPT_PORT0 \\\n\t0x10328UL\n#define NIG_REG_STRAP_OVERRIDE \\\n\t0x10398UL\n#define NIG_REG_XCM0_OUT_EN \\\n\t0x100f0UL\n#define NIG_REG_XCM1_OUT_EN \\\n\t0x100f4UL\n#define NIG_REG_XGXS0_CTRL_MD_DEVAD \\\n\t0x1033cUL\n#define NIG_REG_XGXS0_CTRL_MD_ST \\\n\t0x10338UL\n#define NIG_REG_XGXS0_CTRL_PHY_ADDR \\\n\t0x10340UL\n#define NIG_REG_XGXS0_STATUS_LINK10G \\\n\t0x10680UL\n#define NIG_REG_XGXS0_STATUS_LINK_STATUS \\\n\t0x10684UL\n#define NIG_REG_XGXS_LANE_SEL_P0 \\\n\t0x102e8UL\n#define NIG_REG_XGXS_SERDES0_MODE_SEL \\\n\t0x102e0UL\n#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT \\\n\t(0x1<<0)\n#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS \\\n\t(0x1<<9)\n#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G \\\n\t(0x1<<15)\n#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS \\\n\t(0xf<<18)\n#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE \\\n\t18\n#define PBF_REG_COS0_UPPER_BOUND \\\n\t0x15c05cUL\n#define PBF_REG_COS0_UPPER_BOUND_P0 \\\n\t0x15c2ccUL\n#define PBF_REG_COS0_UPPER_BOUND_P1 \\\n\t0x15c2e4UL\n#define PBF_REG_COS0_WEIGHT \\\n\t0x15c054UL\n#define PBF_REG_COS0_WEIGHT_P0 \\\n\t0x15c2a8UL\n#define PBF_REG_COS0_WEIGHT_P1 \\\n\t0x15c2c0UL\n#define PBF_REG_COS1_UPPER_BOUND \\\n\t0x15c060UL\n#define PBF_REG_COS1_WEIGHT \\\n\t0x15c058UL\n#define PBF_REG_COS1_WEIGHT_P0 \\\n\t0x15c2acUL\n#define PBF_REG_COS1_WEIGHT_P1 \\\n\t0x15c2c4UL\n#define PBF_REG_COS2_WEIGHT_P0 \\\n\t0x15c2b0UL\n#define PBF_REG_COS2_WEIGHT_P1 \\\n\t0x15c2c8UL\n#define PBF_REG_COS3_WEIGHT_P0 \\\n\t0x15c2b4UL\n#define PBF_REG_COS4_WEIGHT_P0 \\\n\t0x15c2b8UL\n#define PBF_REG_COS5_WEIGHT_P0 \\\n\t0x15c2bcUL\n#define PBF_REG_CREDIT_LB_Q \\\n\t0x140338UL\n#define PBF_REG_CREDIT_Q0 \\\n\t0x14033cUL\n#define PBF_REG_CREDIT_Q1 \\\n\t0x140340UL\n#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 \\\n\t0x14005cUL\n#define PBF_REG_DISABLE_PF \\\n\t0x1402e8UL\n#define PBF_REG_DISABLE_VF \\\n\t0x1402ecUL\n#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 \\\n\t0x15c288UL\n#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 \\\n\t0x15c28cUL\n#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 \\\n\t0x15c278UL\n#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 \\\n\t0x15c27cUL\n#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 \\\n\t0x15c280UL\n#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 \\\n\t0x15c284UL\n#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 \\\n\t0x15c2a0UL\n#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 \\\n\t0x15c2a4UL\n#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 \\\n\t0x15c270UL\n#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 \\\n\t0x15c274UL\n#define PBF_REG_ETS_ENABLED \\\n\t0x15c050UL\n#define PBF_REG_HDRS_AFTER_BASIC \\\n\t0x15c0a8UL\n#define PBF_REG_HDRS_AFTER_TAG_0 \\\n\t0x15c0b8UL\n#define PBF_REG_HIGH_PRIORITY_COS_NUM \\\n\t0x15c04cUL\n#define PBF_REG_INIT_CRD_LB_Q \\\n\t0x15c248UL\n#define PBF_REG_INIT_CRD_Q0 \\\n\t0x15c230UL\n#define PBF_REG_INIT_CRD_Q1 \\\n\t0x15c234UL\n#define PBF_REG_INIT_P0 \\\n\t0x140004UL\n#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q \\\n\t0x140354UL\n#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 \\\n\t0x140358UL\n#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 \\\n\t0x14035cUL\n#define PBF_REG_MUST_HAVE_HDRS \\\n\t0x15c0c4UL\n#define PBF_REG_NUM_STRICT_ARB_SLOTS \\\n\t0x15c064UL\n#define PBF_REG_P0_ARB_THRSH \\\n\t0x1400e4UL\n#define PBF_REG_P0_CREDIT \\\n\t0x140200UL\n#define PBF_REG_P0_INIT_CRD \\\n\t0x1400d0UL\n#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT \\\n\t0x140308UL\n#define PBF_REG_P0_PAUSE_ENABLE \\\n\t0x140014UL\n#define PBF_REG_P0_TQ_LINES_FREED_CNT \\\n\t0x1402f0UL\n#define PBF_REG_P0_TQ_OCCUPANCY \\\n\t0x1402fcUL\n#define PBF_REG_P1_CREDIT \\\n\t0x140208UL\n#define PBF_REG_P1_INIT_CRD \\\n\t0x1400d4UL\n#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT \\\n\t0x14030cUL\n#define PBF_REG_P1_TQ_LINES_FREED_CNT \\\n\t0x1402f4UL\n#define PBF_REG_P1_TQ_OCCUPANCY \\\n\t0x140300UL\n#define PBF_REG_P4_CREDIT \\\n\t0x140210UL\n#define PBF_REG_P4_INIT_CRD \\\n\t0x1400e0UL\n#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT \\\n\t0x140310UL\n#define PBF_REG_P4_TQ_LINES_FREED_CNT \\\n\t0x1402f8UL\n#define PBF_REG_P4_TQ_OCCUPANCY \\\n\t0x140304UL\n#define PBF_REG_PBF_INT_MASK \\\n\t0x1401d4UL\n#define PBF_REG_PBF_PRTY_MASK \\\n\t0x1401e4UL\n#define PBF_REG_PBF_PRTY_STS_CLR \\\n\t0x1401dcUL\n#define PBF_REG_TAG_ETHERTYPE_0 \\\n\t0x15c090UL\n#define PBF_REG_TAG_LEN_0 \\\n\t0x15c09cUL\n#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q \\\n\t0x14038cUL\n#define PBF_REG_TQ_LINES_FREED_CNT_Q0 \\\n\t0x140390UL\n#define PBF_REG_TQ_LINES_FREED_CNT_Q1 \\\n\t0x140394UL\n#define PBF_REG_TQ_OCCUPANCY_LB_Q \\\n\t0x1403a8UL\n#define PBF_REG_TQ_OCCUPANCY_Q0 \\\n\t0x1403acUL\n#define PBF_REG_TQ_OCCUPANCY_Q1 \\\n\t0x1403b0UL\n#define PB_REG_PB_INT_MASK \\\n\t0x28UL\n#define PB_REG_PB_PRTY_MASK \\\n\t0x38UL\n#define PB_REG_PB_PRTY_STS_CLR \\\n\t0x30UL\n#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR \\\n\t(0x1<<0)\n#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW \\\n\t(0x1<<8)\n#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR \\\n\t(0x1<<1)\n#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN \\\n\t(0x1<<6)\n#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN \\\n\t(0x1<<7)\n#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN \\\n\t(0x1<<4)\n#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN \\\n\t(0x1<<3)\n#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN \\\n\t(0x1<<5)\n#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN \\\n\t(0x1<<2)\n#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR \\\n\t0x9418UL\n#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \\\n\t0x9478UL\n#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR \\\n\t0x947cUL\n#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR \\\n\t0x9480UL\n#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR \\\n\t0x9474UL\n#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \\\n\t0x942cUL\n#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \\\n\t0x9430UL\n#define PGLUE_B_REG_INTERNAL_VFID_ENABLE \\\n\t0x9438UL\n#define PGLUE_B_REG_PGLUE_B_INT_STS \\\n\t0x9298UL\n#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR \\\n\t0x929cUL\n#define PGLUE_B_REG_PGLUE_B_PRTY_MASK \\\n\t0x92b4UL\n#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR \\\n\t0x92acUL\n#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR \\\n\t0x9458UL\n#define PGLUE_B_REG_TAGS_63_32 \\\n\t0x9244UL\n#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR \\\n\t0x9470UL\n#define PRS_REG_A_PRSU_20 \\\n\t0x40134UL\n#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT \\\n\t0x4011cUL\n#define PRS_REG_E1HOV_MODE \\\n\t0x401c8UL\n#define PRS_REG_HDRS_AFTER_BASIC \\\n\t0x40238UL\n#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 \\\n\t0x40270UL\n#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 \\\n\t0x40290UL\n#define PRS_REG_HDRS_AFTER_TAG_0 \\\n\t0x40248UL\n#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 \\\n\t0x40280UL\n#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 \\\n\t0x402a0UL\n#define PRS_REG_MUST_HAVE_HDRS \\\n\t0x40254UL\n#define PRS_REG_MUST_HAVE_HDRS_PORT_0 \\\n\t0x4028cUL\n#define PRS_REG_MUST_HAVE_HDRS_PORT_1 \\\n\t0x402acUL\n#define PRS_REG_NIC_MODE \\\n\t0x40138UL\n#define PRS_REG_NUM_OF_PACKETS \\\n\t0x40124UL\n#define PRS_REG_PRS_PRTY_MASK \\\n\t0x401a4UL\n#define PRS_REG_PRS_PRTY_STS_CLR \\\n\t0x4019cUL\n#define PRS_REG_TAG_ETHERTYPE_0 \\\n\t0x401d4UL\n#define PRS_REG_TAG_LEN_0 \\\n\t0x4022cUL\n#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT \\\n\t(0x1<<19)\n#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF \\\n\t(0x1<<20)\n#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN \\\n\t(0x1<<22)\n#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED \\\n\t(0x1<<23)\n#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED \\\n\t(0x1<<24)\n#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR \\\n\t(0x1<<7)\n#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR \\\n\t(0x1<<7)\n#define PXP2_REG_PGL_ADDR_88_F0 \\\n\t0x120534UL\n#define PXP2_REG_PGL_ADDR_88_F1 \\\n\t0x120544UL\n#define PXP2_REG_PGL_ADDR_8C_F0 \\\n\t0x120538UL\n#define PXP2_REG_PGL_ADDR_8C_F1 \\\n\t0x120548UL\n#define PXP2_REG_PGL_ADDR_90_F0 \\\n\t0x12053cUL\n#define PXP2_REG_PGL_ADDR_90_F1 \\\n\t0x12054cUL\n#define PXP2_REG_PGL_ADDR_94_F0 \\\n\t0x120540UL\n#define PXP2_REG_PGL_ADDR_94_F1 \\\n\t0x120550UL\n#define PXP2_REG_PGL_EXP_ROM2 \\\n\t0x120808UL\n#define PXP2_REG_PGL_PRETEND_FUNC_F0 \\\n\t0x120674UL\n#define PXP2_REG_PGL_PRETEND_FUNC_F1 \\\n\t0x120678UL\n#define PXP2_REG_PGL_TAGS_LIMIT \\\n\t0x1205a8UL\n#define PXP2_REG_PSWRQ_BW_ADD1 \\\n\t0x1201c0UL\n#define PXP2_REG_PSWRQ_BW_ADD10 \\\n\t0x1201e4UL\n#define PXP2_REG_PSWRQ_BW_ADD11 \\\n\t0x1201e8UL\n#define PXP2_REG_PSWRQ_BW_ADD2 \\\n\t0x1201c4UL\n#define PXP2_REG_PSWRQ_BW_ADD28 \\\n\t0x120228UL\n#define PXP2_REG_PSWRQ_BW_ADD3 \\\n\t0x1201c8UL\n#define PXP2_REG_PSWRQ_BW_ADD6 \\\n\t0x1201d4UL\n#define PXP2_REG_PSWRQ_BW_ADD7 \\\n\t0x1201d8UL\n#define PXP2_REG_PSWRQ_BW_ADD8 \\\n\t0x1201dcUL\n#define PXP2_REG_PSWRQ_BW_ADD9 \\\n\t0x1201e0UL\n#define PXP2_REG_PSWRQ_BW_L1 \\\n\t0x1202b0UL\n#define PXP2_REG_PSWRQ_BW_L10 \\\n\t0x1202d4UL\n#define PXP2_REG_PSWRQ_BW_L11 \\\n\t0x1202d8UL\n#define PXP2_REG_PSWRQ_BW_L2 \\\n\t0x1202b4UL\n#define PXP2_REG_PSWRQ_BW_L28 \\\n\t0x120318UL\n#define PXP2_REG_PSWRQ_BW_L3 \\\n\t0x1202b8UL\n#define PXP2_REG_PSWRQ_BW_L6 \\\n\t0x1202c4UL\n#define PXP2_REG_PSWRQ_BW_L7 \\\n\t0x1202c8UL\n#define PXP2_REG_PSWRQ_BW_L8 \\\n\t0x1202ccUL\n#define PXP2_REG_PSWRQ_BW_L9 \\\n\t0x1202d0UL\n#define PXP2_REG_PSWRQ_BW_RD \\\n\t0x120324UL\n#define PXP2_REG_PSWRQ_BW_UB1 \\\n\t0x120238UL\n#define PXP2_REG_PSWRQ_BW_UB10 \\\n\t0x12025cUL\n#define PXP2_REG_PSWRQ_BW_UB11 \\\n\t0x120260UL\n#define PXP2_REG_PSWRQ_BW_UB2 \\\n\t0x12023cUL\n#define PXP2_REG_PSWRQ_BW_UB28 \\\n\t0x1202a0UL\n#define PXP2_REG_PSWRQ_BW_UB3 \\\n\t0x120240UL\n#define PXP2_REG_PSWRQ_BW_UB6 \\\n\t0x12024cUL\n#define PXP2_REG_PSWRQ_BW_UB7 \\\n\t0x120250UL\n#define PXP2_REG_PSWRQ_BW_UB8 \\\n\t0x120254UL\n#define PXP2_REG_PSWRQ_BW_UB9 \\\n\t0x120258UL\n#define PXP2_REG_PSWRQ_BW_WR \\\n\t0x120328UL\n#define PXP2_REG_PSWRQ_CDU0_L2P \\\n\t0x120000UL\n#define PXP2_REG_PSWRQ_QM0_L2P \\\n\t0x120038UL\n#define PXP2_REG_PSWRQ_SRC0_L2P \\\n\t0x120054UL\n#define PXP2_REG_PSWRQ_TM0_L2P \\\n\t0x12001cUL\n#define PXP2_REG_PXP2_INT_MASK_0 \\\n\t0x120578UL\n#define PXP2_REG_PXP2_INT_MASK_1 \\\n\t0x120614UL\n#define PXP2_REG_PXP2_INT_STS_0 \\\n\t0x12056cUL\n#define PXP2_REG_PXP2_INT_STS_1 \\\n\t0x120608UL\n#define PXP2_REG_PXP2_INT_STS_CLR_0 \\\n\t0x120570UL\n#define PXP2_REG_PXP2_PRTY_MASK_0 \\\n\t0x120588UL\n#define PXP2_REG_PXP2_PRTY_MASK_1 \\\n\t0x120598UL\n#define PXP2_REG_PXP2_PRTY_STS_CLR_0 \\\n\t0x120580UL\n#define PXP2_REG_PXP2_PRTY_STS_CLR_1 \\\n\t0x120590UL\n#define PXP2_REG_RD_BLK_CNT \\\n\t0x120418UL\n#define PXP2_REG_RD_CDURD_SWAP_MODE \\\n\t0x120404UL\n#define PXP2_REG_RD_DISABLE_INPUTS \\\n\t0x120374UL\n#define PXP2_REG_RD_INIT_DONE \\\n\t0x120370UL\n#define PXP2_REG_RD_PBF_SWAP_MODE \\\n\t0x1203f4UL\n#define PXP2_REG_RD_PORT_IS_IDLE_0 \\\n\t0x12041cUL\n#define PXP2_REG_RD_PORT_IS_IDLE_1 \\\n\t0x120420UL\n#define PXP2_REG_RD_QM_SWAP_MODE \\\n\t0x1203f8UL\n#define PXP2_REG_RD_SRC_SWAP_MODE \\\n\t0x120400UL\n#define PXP2_REG_RD_SR_CNT \\\n\t0x120414UL\n#define PXP2_REG_RD_START_INIT \\\n\t0x12036cUL\n#define PXP2_REG_RD_TM_SWAP_MODE \\\n\t0x1203fcUL\n#define PXP2_REG_RQ_BW_RD_ADD0 \\\n\t0x1201bcUL\n#define PXP2_REG_RQ_BW_RD_ADD12 \\\n\t0x1201ecUL\n#define PXP2_REG_RQ_BW_RD_ADD13 \\\n\t0x1201f0UL\n#define PXP2_REG_RQ_BW_RD_ADD14 \\\n\t0x1201f4UL\n#define PXP2_REG_RQ_BW_RD_ADD15 \\\n\t0x1201f8UL\n#define PXP2_REG_RQ_BW_RD_ADD16 \\\n\t0x1201fcUL\n#define PXP2_REG_RQ_BW_RD_ADD17 \\\n\t0x120200UL\n#define PXP2_REG_RQ_BW_RD_ADD18 \\\n\t0x120204UL\n#define PXP2_REG_RQ_BW_RD_ADD19 \\\n\t0x120208UL\n#define PXP2_REG_RQ_BW_RD_ADD20 \\\n\t0x12020cUL\n#define PXP2_REG_RQ_BW_RD_ADD22 \\\n\t0x120210UL\n#define PXP2_REG_RQ_BW_RD_ADD23 \\\n\t0x120214UL\n#define PXP2_REG_RQ_BW_RD_ADD24 \\\n\t0x120218UL\n#define PXP2_REG_RQ_BW_RD_ADD25 \\\n\t0x12021cUL\n#define PXP2_REG_RQ_BW_RD_ADD26 \\\n\t0x120220UL\n#define PXP2_REG_RQ_BW_RD_ADD27 \\\n\t0x120224UL\n#define PXP2_REG_RQ_BW_RD_ADD4 \\\n\t0x1201ccUL\n#define PXP2_REG_RQ_BW_RD_ADD5 \\\n\t0x1201d0UL\n#define PXP2_REG_RQ_BW_RD_L0 \\\n\t0x1202acUL\n#define PXP2_REG_RQ_BW_RD_L12 \\\n\t0x1202dcUL\n#define PXP2_REG_RQ_BW_RD_L13 \\\n\t0x1202e0UL\n#define PXP2_REG_RQ_BW_RD_L14 \\\n\t0x1202e4UL\n#define PXP2_REG_RQ_BW_RD_L15 \\\n\t0x1202e8UL\n#define PXP2_REG_RQ_BW_RD_L16 \\\n\t0x1202ecUL\n#define PXP2_REG_RQ_BW_RD_L17 \\\n\t0x1202f0UL\n#define PXP2_REG_RQ_BW_RD_L18 \\\n\t0x1202f4UL\n#define PXP2_REG_RQ_BW_RD_L19 \\\n\t0x1202f8UL\n#define PXP2_REG_RQ_BW_RD_L20 \\\n\t0x1202fcUL\n#define PXP2_REG_RQ_BW_RD_L22 \\\n\t0x120300UL\n#define PXP2_REG_RQ_BW_RD_L23 \\\n\t0x120304UL\n#define PXP2_REG_RQ_BW_RD_L24 \\\n\t0x120308UL\n#define PXP2_REG_RQ_BW_RD_L25 \\\n\t0x12030cUL\n#define PXP2_REG_RQ_BW_RD_L26 \\\n\t0x120310UL\n#define PXP2_REG_RQ_BW_RD_L27 \\\n\t0x120314UL\n#define PXP2_REG_RQ_BW_RD_L4 \\\n\t0x1202bcUL\n#define PXP2_REG_RQ_BW_RD_L5 \\\n\t0x1202c0UL\n#define PXP2_REG_RQ_BW_RD_UBOUND0 \\\n\t0x120234UL\n#define PXP2_REG_RQ_BW_RD_UBOUND12 \\\n\t0x120264UL\n#define PXP2_REG_RQ_BW_RD_UBOUND13 \\\n\t0x120268UL\n#define PXP2_REG_RQ_BW_RD_UBOUND14 \\\n\t0x12026cUL\n#define PXP2_REG_RQ_BW_RD_UBOUND15 \\\n\t0x120270UL\n#define PXP2_REG_RQ_BW_RD_UBOUND16 \\\n\t0x120274UL\n#define PXP2_REG_RQ_BW_RD_UBOUND17 \\\n\t0x120278UL\n#define PXP2_REG_RQ_BW_RD_UBOUND18 \\\n\t0x12027cUL\n#define PXP2_REG_RQ_BW_RD_UBOUND19 \\\n\t0x120280UL\n#define PXP2_REG_RQ_BW_RD_UBOUND20 \\\n\t0x120284UL\n#define PXP2_REG_RQ_BW_RD_UBOUND22 \\\n\t0x120288UL\n#define PXP2_REG_RQ_BW_RD_UBOUND23 \\\n\t0x12028cUL\n#define PXP2_REG_RQ_BW_RD_UBOUND24 \\\n\t0x120290UL\n#define PXP2_REG_RQ_BW_RD_UBOUND25 \\\n\t0x120294UL\n#define PXP2_REG_RQ_BW_RD_UBOUND26 \\\n\t0x120298UL\n#define PXP2_REG_RQ_BW_RD_UBOUND27 \\\n\t0x12029cUL\n#define PXP2_REG_RQ_BW_RD_UBOUND4 \\\n\t0x120244UL\n#define PXP2_REG_RQ_BW_RD_UBOUND5 \\\n\t0x120248UL\n#define PXP2_REG_RQ_BW_WR_ADD29 \\\n\t0x12022cUL\n#define PXP2_REG_RQ_BW_WR_ADD30 \\\n\t0x120230UL\n#define PXP2_REG_RQ_BW_WR_L29 \\\n\t0x12031cUL\n#define PXP2_REG_RQ_BW_WR_L30 \\\n\t0x120320UL\n#define PXP2_REG_RQ_BW_WR_UBOUND29 \\\n\t0x1202a4UL\n#define PXP2_REG_RQ_BW_WR_UBOUND30 \\\n\t0x1202a8UL\n#define PXP2_REG_RQ_CDU_ENDIAN_M \\\n\t0x1201a0UL\n#define PXP2_REG_RQ_CDU_FIRST_ILT \\\n\t0x12061cUL\n#define PXP2_REG_RQ_CDU_LAST_ILT \\\n\t0x120620UL\n#define PXP2_REG_RQ_CDU_P_SIZE \\\n\t0x120018UL\n#define PXP2_REG_RQ_CFG_DONE \\\n\t0x1201b4UL\n#define PXP2_REG_RQ_DBG_ENDIAN_M \\\n\t0x1201a4UL\n#define PXP2_REG_RQ_DISABLE_INPUTS \\\n\t0x120330UL\n#define PXP2_REG_RQ_DRAM_ALIGN \\\n\t0x1205b0UL\n#define PXP2_REG_RQ_DRAM_ALIGN_RD \\\n\t0x12092cUL\n#define PXP2_REG_RQ_DRAM_ALIGN_SEL \\\n\t0x120930UL\n#define PXP2_REG_RQ_HC_ENDIAN_M \\\n\t0x1201a8UL\n#define PXP2_REG_RQ_ONCHIP_AT \\\n\t0x122000UL\n#define PXP2_REG_RQ_ONCHIP_AT_B0 \\\n\t0x128000UL\n#define PXP2_REG_RQ_PDR_LIMIT \\\n\t0x12033cUL\n#define PXP2_REG_RQ_QM_ENDIAN_M \\\n\t0x120194UL\n#define PXP2_REG_RQ_QM_FIRST_ILT \\\n\t0x120634UL\n#define PXP2_REG_RQ_QM_LAST_ILT \\\n\t0x120638UL\n#define PXP2_REG_RQ_QM_P_SIZE \\\n\t0x120050UL\n#define PXP2_REG_RQ_RBC_DONE \\\n\t0x1201b0UL\n#define PXP2_REG_RQ_RD_MBS0 \\\n\t0x120160UL\n#define PXP2_REG_RQ_RD_MBS1 \\\n\t0x120168UL\n#define PXP2_REG_RQ_SRC_ENDIAN_M \\\n\t0x12019cUL\n#define PXP2_REG_RQ_SRC_FIRST_ILT \\\n\t0x12063cUL\n#define PXP2_REG_RQ_SRC_LAST_ILT \\\n\t0x120640UL\n#define PXP2_REG_RQ_SRC_P_SIZE \\\n\t0x12006cUL\n#define PXP2_REG_RQ_TM_ENDIAN_M \\\n\t0x120198UL\n#define PXP2_REG_RQ_TM_FIRST_ILT \\\n\t0x120644UL\n#define PXP2_REG_RQ_TM_LAST_ILT \\\n\t0x120648UL\n#define PXP2_REG_RQ_TM_P_SIZE \\\n\t0x120034UL\n#define PXP2_REG_RQ_WR_MBS0 \\\n\t0x12015cUL\n#define PXP2_REG_RQ_WR_MBS1 \\\n\t0x120164UL\n#define PXP2_REG_WR_CDU_MPS \\\n\t0x1205f0UL\n#define PXP2_REG_WR_CSDM_MPS \\\n\t0x1205d0UL\n#define PXP2_REG_WR_DBG_MPS \\\n\t0x1205e8UL\n#define PXP2_REG_WR_DMAE_MPS \\\n\t0x1205ecUL\n#define PXP2_REG_WR_HC_MPS \\\n\t0x1205c8UL\n#define PXP2_REG_WR_QM_MPS \\\n\t0x1205dcUL\n#define PXP2_REG_WR_SRC_MPS \\\n\t0x1205e4UL\n#define PXP2_REG_WR_TM_MPS \\\n\t0x1205e0UL\n#define PXP2_REG_WR_TSDM_MPS \\\n\t0x1205d4UL\n#define PXP2_REG_WR_USDMDP_TH \\\n\t0x120348UL\n#define PXP2_REG_WR_USDM_MPS \\\n\t0x1205ccUL\n#define PXP2_REG_WR_XSDM_MPS \\\n\t0x1205d8UL\n#define PXP_REG_HST_DISCARD_DOORBELLS \\\n\t0x1030a4UL\n#define PXP_REG_HST_DISCARD_INTERNAL_WRITES \\\n\t0x1030a8UL\n#define PXP_REG_HST_ZONE_PERMISSION_TABLE \\\n\t0x103400UL\n#define PXP_REG_PXP_INT_MASK_0 \\\n\t0x103074UL\n#define PXP_REG_PXP_INT_MASK_1 \\\n\t0x103084UL\n#define PXP_REG_PXP_INT_STS_CLR_0 \\\n\t0x10306cUL\n#define PXP_REG_PXP_INT_STS_CLR_1 \\\n\t0x10307cUL\n#define PXP_REG_PXP_PRTY_MASK \\\n\t0x103094UL\n#define PXP_REG_PXP_PRTY_STS_CLR \\\n\t0x10308cUL\n#define QM_REG_BASEADDR \\\n\t0x168900UL\n#define QM_REG_BASEADDR_EXT_A \\\n\t0x16e100UL\n#define QM_REG_BYTECRDCMDQ_0 \\\n\t0x16e6e8UL\n#define QM_REG_CONNNUM_0 \\\n\t0x168020UL\n#define QM_REG_PF_EN \\\n\t0x16e70cUL\n#define QM_REG_PF_USG_CNT_0 \\\n\t0x16e040UL\n#define QM_REG_PTRTBL \\\n\t0x168a00UL\n#define QM_REG_PTRTBL_EXT_A \\\n\t0x16e200UL\n#define QM_REG_QM_INT_MASK \\\n\t0x168444UL\n#define QM_REG_QM_PRTY_MASK \\\n\t0x168454UL\n#define QM_REG_QM_PRTY_STS_CLR \\\n\t0x16844cUL\n#define QM_REG_QVOQIDX_0 \\\n\t0x1680f4UL\n#define QM_REG_SOFT_RESET \\\n\t0x168428UL\n#define QM_REG_VOQQMASK_0_LSB \\\n\t0x168240UL\n#define SEM_FAST_REG_PARITY_RST \\\n\t0x18840UL\n#define SRC_REG_COUNTFREE0 \\\n\t0x40500UL\n#define SRC_REG_FIRSTFREE0 \\\n\t0x40510UL\n#define SRC_REG_KEYSEARCH_0 \\\n\t0x40458UL\n#define SRC_REG_KEYSEARCH_1 \\\n\t0x4045cUL\n#define SRC_REG_KEYSEARCH_2 \\\n\t0x40460UL\n#define SRC_REG_KEYSEARCH_3 \\\n\t0x40464UL\n#define SRC_REG_KEYSEARCH_4 \\\n\t0x40468UL\n#define SRC_REG_KEYSEARCH_5 \\\n\t0x4046cUL\n#define SRC_REG_KEYSEARCH_6 \\\n\t0x40470UL\n#define SRC_REG_KEYSEARCH_7 \\\n\t0x40474UL\n#define SRC_REG_KEYSEARCH_8 \\\n\t0x40478UL\n#define SRC_REG_KEYSEARCH_9 \\\n\t0x4047cUL\n#define SRC_REG_LASTFREE0 \\\n\t0x40530UL\n#define SRC_REG_NUMBER_HASH_BITS0 \\\n\t0x40400UL\n#define SRC_REG_SOFT_RST \\\n\t0x4049cUL\n#define SRC_REG_SRC_PRTY_MASK \\\n\t0x404c8UL\n#define SRC_REG_SRC_PRTY_STS_CLR \\\n\t0x404c0UL\n#define TCM_REG_PRS_IFEN \\\n\t0x50020UL\n#define TCM_REG_TCM_INT_MASK \\\n\t0x501dcUL\n#define TCM_REG_TCM_PRTY_MASK \\\n\t0x501ecUL\n#define TCM_REG_TCM_PRTY_STS_CLR \\\n\t0x501e4UL\n#define TM_REG_EN_LINEAR0_TIMER \\\n\t0x164014UL\n#define TM_REG_LIN0_MAX_ACTIVE_CID \\\n\t0x164048UL\n#define TM_REG_LIN0_NUM_SCANS \\\n\t0x1640a0UL\n#define TM_REG_LIN0_SCAN_ON \\\n\t0x1640d0UL\n#define TM_REG_LIN0_SCAN_TIME \\\n\t0x16403cUL\n#define TM_REG_LIN0_VNIC_UC \\\n\t0x164128UL\n#define TM_REG_TM_INT_MASK \\\n\t0x1640fcUL\n#define TM_REG_TM_PRTY_MASK \\\n\t0x16410cUL\n#define TM_REG_TM_PRTY_STS_CLR \\\n\t0x164104UL\n#define TSDM_REG_ENABLE_IN1 \\\n\t0x42238UL\n#define TSDM_REG_TSDM_INT_MASK_0 \\\n\t0x4229cUL\n#define TSDM_REG_TSDM_INT_MASK_1 \\\n\t0x422acUL\n#define TSDM_REG_TSDM_PRTY_MASK \\\n\t0x422bcUL\n#define TSDM_REG_TSDM_PRTY_STS_CLR \\\n\t0x422b4UL\n#define TSEM_REG_FAST_MEMORY \\\n\t0x1a0000UL\n#define TSEM_REG_INT_TABLE \\\n\t0x180400UL\n#define TSEM_REG_PASSIVE_BUFFER \\\n\t0x181000UL\n#define TSEM_REG_PRAM \\\n\t0x1c0000UL\n#define TSEM_REG_TSEM_INT_MASK_0 \\\n\t0x180100UL\n#define TSEM_REG_TSEM_INT_MASK_1 \\\n\t0x180110UL\n#define TSEM_REG_TSEM_PRTY_MASK_0 \\\n\t0x180120UL\n#define TSEM_REG_TSEM_PRTY_MASK_1 \\\n\t0x180130UL\n#define TSEM_REG_TSEM_PRTY_STS_CLR_0 \\\n\t0x180118UL\n#define TSEM_REG_TSEM_PRTY_STS_CLR_1 \\\n\t0x180128UL\n#define TSEM_REG_VFPF_ERR_NUM \\\n\t0x180380UL\n#define UCM_REG_UCM_INT_MASK \\\n\t0xe01d4UL\n#define UCM_REG_UCM_PRTY_MASK \\\n\t0xe01e4UL\n#define UCM_REG_UCM_PRTY_STS_CLR \\\n\t0xe01dcUL\n#define UMAC_COMMAND_CONFIG_REG_HD_ENA \\\n\t(0x1<<10)\n#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE \\\n\t(0x1<<28)\n#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA \\\n\t(0x1<<15)\n#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK \\\n\t(0x1<<24)\n#define UMAC_COMMAND_CONFIG_REG_PAD_EN \\\n\t(0x1<<5)\n#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE \\\n\t(0x1<<8)\n#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN \\\n\t(0x1<<4)\n#define UMAC_COMMAND_CONFIG_REG_RX_ENA \\\n\t(0x1<<1)\n#define UMAC_COMMAND_CONFIG_REG_SW_RESET \\\n\t(0x1<<13)\n#define UMAC_COMMAND_CONFIG_REG_TX_ENA \\\n\t(0x1<<0)\n#define UMAC_REG_COMMAND_CONFIG \\\n\t0x8UL\n#define UMAC_REG_EEE_WAKE_TIMER \\\n\t0x6cUL\n#define UMAC_REG_MAC_ADDR0 \\\n\t0xcUL\n#define UMAC_REG_MAC_ADDR1 \\\n\t0x10UL\n#define UMAC_REG_MAXFR \\\n\t0x14UL\n#define UMAC_REG_UMAC_EEE_CTRL \\\n\t0x64UL\n#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN \\\n\t(0x1<<3)\n#define USDM_REG_USDM_INT_MASK_0 \\\n\t0xc42a0UL\n#define USDM_REG_USDM_INT_MASK_1 \\\n\t0xc42b0UL\n#define USDM_REG_USDM_PRTY_MASK \\\n\t0xc42c0UL\n#define USDM_REG_USDM_PRTY_STS_CLR \\\n\t0xc42b8UL\n#define USEM_REG_FAST_MEMORY \\\n\t0x320000UL\n#define USEM_REG_INT_TABLE \\\n\t0x300400UL\n#define USEM_REG_PASSIVE_BUFFER \\\n\t0x302000UL\n#define USEM_REG_PRAM \\\n\t0x340000UL\n#define USEM_REG_USEM_INT_MASK_0 \\\n\t0x300110UL\n#define USEM_REG_USEM_INT_MASK_1 \\\n\t0x300120UL\n#define USEM_REG_USEM_PRTY_MASK_0 \\\n\t0x300130UL\n#define USEM_REG_USEM_PRTY_MASK_1 \\\n\t0x300140UL\n#define USEM_REG_USEM_PRTY_STS_CLR_0 \\\n\t0x300128UL\n#define USEM_REG_USEM_PRTY_STS_CLR_1 \\\n\t0x300138UL\n#define USEM_REG_VFPF_ERR_NUM \\\n\t0x300380UL\n#define VFC_MEMORIES_RST_REG_CAM_RST \\\n\t(0x1<<0)\n#define VFC_MEMORIES_RST_REG_RAM_RST \\\n\t(0x1<<1)\n#define VFC_REG_MEMORIES_RST \\\n\t0x1943cUL\n#define XCM_REG_XCM_INT_MASK \\\n\t0x202b4UL\n#define XCM_REG_XCM_PRTY_MASK \\\n\t0x202c4UL\n#define XCM_REG_XCM_PRTY_STS_CLR \\\n\t0x202bcUL\n#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS \\\n\t(0x1<<0)\n#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS \\\n\t(0x1<<1)\n#define XMAC_CTRL_REG_LINE_LOCAL_LPBK \\\n\t(0x1<<2)\n#define XMAC_CTRL_REG_RX_EN \\\n\t(0x1<<1)\n#define XMAC_CTRL_REG_SOFT_RESET \\\n\t(0x1<<6)\n#define XMAC_CTRL_REG_TX_EN \\\n\t(0x1<<0)\n#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB \\\n\t(0x1<<7)\n#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN \\\n\t(0x1<<18)\n#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN \\\n\t(0x1<<17)\n#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON \\\n\t(0x1<<1)\n#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN \\\n\t(0x1<<0)\n#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN \\\n\t(0x1<<3)\n#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN \\\n\t(0x1<<4)\n#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN \\\n\t(0x1<<5)\n#define XMAC_REG_CLEAR_RX_LSS_STATUS \\\n\t0x60UL\n#define XMAC_REG_CTRL \\\n\t0UL\n#define XMAC_REG_CTRL_SA_HI \\\n\t0x2cUL\n#define XMAC_REG_CTRL_SA_LO \\\n\t0x28UL\n#define XMAC_REG_EEE_CTRL \\\n\t0xd8UL\n#define XMAC_REG_EEE_TIMERS_HI \\\n\t0xe4UL\n#define XMAC_REG_PAUSE_CTRL \\\n\t0x68UL\n#define XMAC_REG_PFC_CTRL \\\n\t0x70UL\n#define XMAC_REG_PFC_CTRL_HI \\\n\t0x74UL\n#define XMAC_REG_RX_LSS_CTRL \\\n\t0x50UL\n#define XMAC_REG_RX_LSS_STATUS \\\n\t0x58UL\n#define XMAC_REG_RX_MAX_SIZE \\\n\t0x40UL\n#define XMAC_REG_TX_CTRL \\\n\t0x20UL\n#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE \\\n\t(0x1<<0)\n#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE \\\n\t(0x1<<1)\n#define XSDM_REG_OPERATION_GEN \\\n\t0x1664c4UL\n#define XSDM_REG_XSDM_INT_MASK_0 \\\n\t0x16629cUL\n#define XSDM_REG_XSDM_INT_MASK_1 \\\n\t0x1662acUL\n#define XSDM_REG_XSDM_PRTY_MASK \\\n\t0x1662bcUL\n#define XSDM_REG_XSDM_PRTY_STS_CLR \\\n\t0x1662b4UL\n#define XSEM_REG_FAST_MEMORY \\\n\t0x2a0000UL\n#define XSEM_REG_INT_TABLE \\\n\t0x280400UL\n#define XSEM_REG_PASSIVE_BUFFER \\\n\t0x282000UL\n#define XSEM_REG_PRAM \\\n\t0x2c0000UL\n#define XSEM_REG_VFPF_ERR_NUM \\\n\t0x280380UL\n#define XSEM_REG_XSEM_INT_MASK_0 \\\n\t0x280110UL\n#define XSEM_REG_XSEM_INT_MASK_1 \\\n\t0x280120UL\n#define XSEM_REG_XSEM_PRTY_MASK_0 \\\n\t0x280130UL\n#define XSEM_REG_XSEM_PRTY_MASK_1 \\\n\t0x280140UL\n#define XSEM_REG_XSEM_PRTY_STS_CLR_0 \\\n\t0x280128UL\n#define XSEM_REG_XSEM_PRTY_STS_CLR_1 \\\n\t0x280138UL\n#define MCPR_ACCESS_LOCK_LOCK\t\t\t (1L<<31)\n#define MCPR_IMC_COMMAND_ENABLE\t\t\t (1L<<31)\n#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT\t 16\n#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT\t 28\n#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8\n#define MCPR_NVM_ACCESS_ENABLE_EN\t\t (1L<<0)\n#define MCPR_NVM_ACCESS_ENABLE_WR_EN\t\t (1L<<1)\n#define MCPR_NVM_ADDR_NVM_ADDR_VALUE\t\t (0xffffffL<<0)\n#define MCPR_NVM_CFG4_FLASH_SIZE\t\t (0x7L<<0)\n#define MCPR_NVM_COMMAND_DOIT\t\t\t (1L<<4)\n#define MCPR_NVM_COMMAND_DONE\t\t\t (1L<<3)\n#define MCPR_NVM_COMMAND_FIRST\t\t\t (1L<<7)\n#define MCPR_NVM_COMMAND_LAST\t\t\t (1L<<8)\n#define MCPR_NVM_COMMAND_WR\t\t\t (1L<<5)\n#define MCPR_NVM_SW_ARB_ARB_ARB1\t\t (1L<<9)\n#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1\t\t (1L<<5)\n#define MCPR_NVM_SW_ARB_ARB_REQ_SET1\t\t (1L<<1)\n\n\n#define BIGMAC_REGISTER_BMAC_CONTROL\t (0x00<<3)\n#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)\n#define BIGMAC_REGISTER_CNT_MAX_SIZE\t (0x05<<3)\n#define BIGMAC_REGISTER_RX_CONTROL\t (0x21<<3)\n#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)\n#define BIGMAC_REGISTER_RX_LSS_STATUS\t (0x43<<3)\n#define BIGMAC_REGISTER_RX_MAX_SIZE\t (0x23<<3)\n#define BIGMAC_REGISTER_RX_STAT_GR64\t (0x26<<3)\n#define BIGMAC_REGISTER_RX_STAT_GRIPJ\t (0x42<<3)\n#define BIGMAC_REGISTER_TX_CONTROL\t (0x07<<3)\n#define BIGMAC_REGISTER_TX_MAX_SIZE\t (0x09<<3)\n#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)\n#define BIGMAC_REGISTER_TX_SOURCE_ADDR\t (0x08<<3)\n#define BIGMAC_REGISTER_TX_STAT_GTBYT\t (0x20<<3)\n#define BIGMAC_REGISTER_TX_STAT_GTPKT\t (0x0C<<3)\n#define BIGMAC2_REGISTER_BMAC_CONTROL\t (0x00<<3)\n#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)\n#define BIGMAC2_REGISTER_CNT_MAX_SIZE\t (0x05<<3)\n#define BIGMAC2_REGISTER_PFC_CONTROL\t (0x06<<3)\n#define BIGMAC2_REGISTER_RX_CONTROL\t (0x3A<<3)\n#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)\n#define BIGMAC2_REGISTER_RX_LSS_STAT\t (0x3E<<3)\n#define BIGMAC2_REGISTER_RX_MAX_SIZE\t (0x3C<<3)\n#define BIGMAC2_REGISTER_RX_STAT_GR64\t (0x40<<3)\n#define BIGMAC2_REGISTER_RX_STAT_GRIPJ\t (0x5f<<3)\n#define BIGMAC2_REGISTER_TX_CONTROL\t (0x1C<<3)\n#define BIGMAC2_REGISTER_TX_MAX_SIZE\t (0x1E<<3)\n#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)\n#define BIGMAC2_REGISTER_TX_SOURCE_ADDR\t (0x1D<<3)\n#define BIGMAC2_REGISTER_TX_STAT_GTBYT\t (0x39<<3)\n#define BIGMAC2_REGISTER_TX_STAT_GTPOK\t (0x22<<3)\n\n\n#define EMAC_LED_1000MB_OVERRIDE\t\t (1L<<1)\n#define EMAC_LED_100MB_OVERRIDE\t\t\t (1L<<2)\n#define EMAC_LED_10MB_OVERRIDE\t\t\t (1L<<3)\n#define EMAC_LED_OVERRIDE\t\t\t (1L<<0)\n#define EMAC_MDIO_COMM_COMMAND_ADDRESS\t (0L<<26)\n#define EMAC_MDIO_COMM_COMMAND_READ_22\t (2L<<26)\n#define EMAC_MDIO_COMM_COMMAND_READ_45\t (3L<<26)\n#define EMAC_MDIO_COMM_COMMAND_WRITE_22\t (1L<<26)\n#define EMAC_MDIO_COMM_COMMAND_WRITE_45\t (1L<<26)\n#define EMAC_MDIO_COMM_DATA\t\t\t (0xffffL<<0)\n#define EMAC_MDIO_COMM_START_BUSY\t\t (1L<<29)\n#define EMAC_MDIO_MODE_AUTO_POLL\t\t (1L<<4)\n#define EMAC_MDIO_MODE_CLAUSE_45\t\t (1L<<31)\n#define EMAC_MDIO_MODE_CLOCK_CNT\t\t (0x3ffL<<16)\n#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT\t 16\n#define EMAC_MDIO_STATUS_10MB\t\t\t (1L<<1)\n#define EMAC_MODE_25G_MODE\t\t\t (1L<<5)\n#define EMAC_MODE_HALF_DUPLEX\t\t\t (1L<<1)\n#define EMAC_MODE_PORT_GMII\t\t (2L<<2)\n#define EMAC_MODE_PORT_MII\t\t (1L<<2)\n#define EMAC_MODE_PORT_MII_10M\t\t (3L<<2)\n#define EMAC_MODE_RESET\t\t\t\t (1L<<0)\n#define EMAC_REG_EMAC_LED\t\t\t\t\t 0xc\n#define EMAC_REG_EMAC_MAC_MATCH\t\t\t\t\t 0x10\n#define EMAC_REG_EMAC_MDIO_COMM\t\t\t\t\t 0xac\n#define EMAC_REG_EMAC_MDIO_MODE\t\t\t\t\t 0xb4\n#define EMAC_REG_EMAC_MDIO_STATUS\t\t\t\t 0xb0\n#define EMAC_REG_EMAC_MODE\t\t\t\t\t 0x0\n#define EMAC_REG_EMAC_RX_MODE\t\t\t\t\t 0xc8\n#define EMAC_REG_EMAC_RX_MTU_SIZE\t\t\t\t 0x9c\n#define EMAC_REG_EMAC_RX_STAT_AC\t\t\t\t 0x180\n#define EMAC_REG_EMAC_RX_STAT_AC_28\t\t\t\t 0x1f4\n#define EMAC_REG_EMAC_RX_STAT_AC_COUNT\t\t\t\t 23\n#define EMAC_REG_EMAC_TX_MODE\t\t\t\t\t 0xbc\n#define EMAC_REG_EMAC_TX_STAT_AC\t\t\t\t 0x280\n#define EMAC_REG_EMAC_TX_STAT_AC_COUNT\t\t\t\t 22\n#define EMAC_REG_RX_PFC_MODE\t\t\t\t\t 0x320\n#define EMAC_REG_RX_PFC_MODE_PRIORITIES\t\t\t (1L<<2)\n#define EMAC_REG_RX_PFC_MODE_RX_EN\t\t\t (1L<<1)\n#define EMAC_REG_RX_PFC_MODE_TX_EN\t\t\t (1L<<0)\n#define EMAC_REG_RX_PFC_PARAM\t\t\t\t\t 0x324\n#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT\t\t 0\n#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT\t 16\n#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD\t\t\t 0x328\n#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT\t\t(0xffff<<0)\n#define EMAC_REG_RX_PFC_STATS_XOFF_SENT\t\t\t 0x330\n#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT\t\t(0xffff<<0)\n#define EMAC_REG_RX_PFC_STATS_XON_RCVD\t\t\t 0x32c\n#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT\t\t(0xffff<<0)\n#define EMAC_REG_RX_PFC_STATS_XON_SENT\t\t\t 0x334\n#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT\t\t(0xffff<<0)\n#define EMAC_RX_MODE_FLOW_EN\t\t\t (1L<<2)\n#define EMAC_RX_MODE_KEEP_MAC_CONTROL\t\t (1L<<3)\n#define EMAC_RX_MODE_KEEP_VLAN_TAG\t\t (1L<<10)\n#define EMAC_RX_MODE_PROMISCUOUS\t\t (1L<<8)\n#define EMAC_RX_MODE_RESET\t\t\t (1L<<0)\n#define EMAC_RX_MTU_SIZE_JUMBO_ENA\t\t (1L<<31)\n#define EMAC_TX_MODE_EXT_PAUSE_EN\t\t (1L<<3)\n#define EMAC_TX_MODE_FLOW_EN\t\t\t (1L<<4)\n#define EMAC_TX_MODE_RESET\t\t\t (1L<<0)\n\n\n#define MISC_REGISTERS_GPIO_0\t\t\t 0\n#define MISC_REGISTERS_GPIO_1\t\t\t 1\n#define MISC_REGISTERS_GPIO_2\t\t\t 2\n#define MISC_REGISTERS_GPIO_3\t\t\t 3\n#define MISC_REGISTERS_GPIO_CLR_POS\t\t 16\n#define MISC_REGISTERS_GPIO_FLOAT\t\t (0xffL<<24)\n#define MISC_REGISTERS_GPIO_FLOAT_POS\t\t 24\n#define MISC_REGISTERS_GPIO_HIGH\t\t 1\n#define MISC_REGISTERS_GPIO_INPUT_HI_Z\t\t 2\n#define MISC_REGISTERS_GPIO_INT_CLR_POS\t\t 24\n#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR\t 0\n#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET\t 1\n#define MISC_REGISTERS_GPIO_INT_SET_POS\t\t 16\n#define MISC_REGISTERS_GPIO_LOW\t\t\t 0\n#define MISC_REGISTERS_GPIO_OUTPUT_HIGH\t\t 1\n#define MISC_REGISTERS_GPIO_OUTPUT_LOW\t\t 0\n#define MISC_REGISTERS_GPIO_PORT_SHIFT\t\t 4\n#define MISC_REGISTERS_GPIO_SET_POS\t\t 8\n#define MISC_REGISTERS_RESET_REG_1_CLEAR\t\t\t\t0x588\n#define MISC_REGISTERS_RESET_REG_1_RST_BRB1\t\t\t\t(0x1<<0)\n#define MISC_REGISTERS_RESET_REG_1_RST_DORQ \\\n\t(0x1<<19)\n#define MISC_REGISTERS_RESET_REG_1_RST_HC \\\n\t(0x1<<29)\n#define MISC_REGISTERS_RESET_REG_1_RST_PXP \\\n\t(0x1<<26)\n#define MISC_REGISTERS_RESET_REG_1_RST_PXPV \\\n\t(0x1<<27)\n#define MISC_REGISTERS_RESET_REG_1_RST_QM \\\n\t(0x1<<17)\n#define MISC_REGISTERS_RESET_REG_1_SET\t\t\t\t\t0x584\n#define MISC_REGISTERS_RESET_REG_2_CLEAR\t\t\t\t0x598\n#define MISC_REGISTERS_RESET_REG_2_MSTAT0 \\\n\t(0x1<<24)\n#define MISC_REGISTERS_RESET_REG_2_MSTAT1 \\\n\t(0x1<<25)\n#define MISC_REGISTERS_RESET_REG_2_PGLC \\\n\t(0x1<<19)\n#define MISC_REGISTERS_RESET_REG_2_RST_ATC \\\n\t(0x1<<17)\n#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0\t\t\t\t(0x1<<0)\n#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1\t\t\t\t(0x1<<1)\n#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0\t\t\t\t(0x1<<2)\n#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE \\\n\t(0x1<<14)\n#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1\t\t\t\t(0x1<<3)\n#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE \\\n\t(0x1<<15)\n#define MISC_REGISTERS_RESET_REG_2_RST_GRC\t\t\t\t(0x1<<4)\n#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B\t\t(0x1<<6)\n#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE\t\t(0x1<<8)\n#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU\t\t(0x1<<7)\n#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE\t(0x1<<5)\n#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE \\\n\t(0x1<<11)\n#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO \\\n\t(0x1<<13)\n#define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR \\\n\t(0x1<<16)\n#define MISC_REGISTERS_RESET_REG_2_RST_RBCN\t\t\t\t(0x1<<9)\n#define MISC_REGISTERS_RESET_REG_2_SET\t\t\t\t\t0x594\n#define MISC_REGISTERS_RESET_REG_2_UMAC0 \\\n\t(0x1<<20)\n#define MISC_REGISTERS_RESET_REG_2_UMAC1 \\\n\t(0x1<<21)\n#define MISC_REGISTERS_RESET_REG_2_XMAC \\\n\t(0x1<<22)\n#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT \\\n\t(0x1<<23)\n#define MISC_REGISTERS_RESET_REG_3_CLEAR\t\t\t\t0x5a8\n#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ\t\t(0x1<<1)\n#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN\t\t(0x1<<2)\n#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD\t(0x1<<3)\n#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW\t\t(0x1<<0)\n#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ\t\t(0x1<<5)\n#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN\t\t(0x1<<6)\n#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD\t\t(0x1<<7)\n#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW\t\t(0x1<<4)\n#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB\t(0x1<<8)\n#define MISC_REGISTERS_RESET_REG_3_SET\t\t\t\t\t0x5a4\n#define MISC_SPIO_CLR_POS\t 16\n#define MISC_SPIO_FLOAT\t\t (0xffL<<24)\n#define MISC_SPIO_FLOAT_POS\t 24\n#define MISC_SPIO_INPUT_HI_Z\t 2\n#define MISC_SPIO_INT_OLD_SET_POS 16\n#define MISC_SPIO_OUTPUT_HIGH\t 1\n#define MISC_SPIO_OUTPUT_LOW\t 0\n#define MISC_SPIO_SET_POS\t 8\n#define MISC_SPIO_SPIO4\t\t 0x10\n#define MISC_SPIO_SPIO5\t\t 0x20\n#define HW_LOCK_MAX_RESOURCE_VALUE\t\t 31\n#define HW_LOCK_RESOURCE_DRV_FLAGS\t\t 10\n#define HW_LOCK_RESOURCE_GPIO\t\t\t 1\n#define HW_LOCK_RESOURCE_NVRAM\t\t\t 12\n#define HW_LOCK_RESOURCE_PORT0_ATT_MASK\t\t 3\n#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0\t 8\n#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1\t 9\n#define HW_LOCK_RESOURCE_RECOVERY_REG\t\t 11\n#define HW_LOCK_RESOURCE_RESET\t\t\t 5\n#define HW_LOCK_RESOURCE_SPIO\t\t\t 2\n\n\n#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT\t\t (0x1<<4)\n#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR\t\t (0x1<<5)\n#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT\t\t (0x1<<19)\n#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR\t\t (0x1<<18)\n#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT\t\t (0x1<<31)\n#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR\t\t (0x1<<30)\n#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT\t\t (0x1<<9)\n#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR\t\t (0x1<<8)\n#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT\t\t (0x1<<7)\n#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR\t\t (0x1<<6)\n#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT\t\t (0x1<<29)\n#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR\t\t (0x1<<28)\n#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT\t\t (0x1<<1)\n#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR\t\t (0x1<<0)\n#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR\t\t (0x1<<18)\n#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT\t\t (0x1<<11)\n#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR\t\t (0x1<<10)\n#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT\t (0x1<<13)\n#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR\t (0x1<<12)\n#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0\t\t (0x1<<2)\n#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR\t\t (0x1<<12)\n#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY\t (0x1<<28)\n#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY\t (0x1UL<<31)\n#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY\t (0x1<<29)\n#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY\t (0x1<<30)\n#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT\t\t (0x1<<15)\n#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR\t\t (0x1<<14)\n#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR\t\t (0x1<<14)\n#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR\t (0x1<<20)\n#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT\t (0x1UL<<31)\n#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR\t (0x1<<30)\n#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR\t\t (0x1<<0)\n#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT\t\t (0x1<<2)\n#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR\t\t (0x1<<3)\n#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)\n#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)\n#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT\t\t (0x1<<3)\n#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR\t\t (0x1<<2)\n#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT\t\t (0x1<<3)\n#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR\t\t (0x1<<2)\n#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR\t (0x1<<22)\n#define AEU_INPUTS_ATTN_BITS_SPIO5\t\t\t (0x1<<15)\n#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT\t\t (0x1<<27)\n#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR\t\t (0x1<<26)\n#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT\t (0x1<<5)\n#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR\t (0x1<<4)\n#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT\t\t (0x1<<25)\n#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR\t\t (0x1<<24)\n#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT\t\t (0x1<<29)\n#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR\t\t (0x1<<28)\n#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT\t\t (0x1<<23)\n#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR\t\t (0x1<<22)\n#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT\t\t (0x1<<27)\n#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR\t\t (0x1<<26)\n#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT\t\t (0x1<<21)\n#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR\t\t (0x1<<20)\n#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT\t\t (0x1<<25)\n#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR\t\t (0x1<<24)\n#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR\t (0x1<<16)\n#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT\t\t (0x1<<9)\n#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR\t\t (0x1<<8)\n#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT\t\t (0x1<<7)\n#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR\t\t (0x1<<6)\n#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT\t\t (0x1<<11)\n#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR\t\t (0x1<<10)\n#define HW_PRTY_ASSERT_SET_0 \\\n(AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR\t |\\\n AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR |\\\n AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR |\\\n AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\\\n AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\\\n AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\\\n AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)\n#define HW_PRTY_ASSERT_SET_1 \\\n(AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR\t\t |\\\n AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR\t\t |\\\n AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR\t |\\\n AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR\t |\\\n AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR\t\t |\\\n AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR\t |\\\n AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR\t |\\\n AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR\t\t |\\\n AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\\\n AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR\t |\\\n AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR\t |\\\n AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR\t\t |\\\n AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR\t |\\\n AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR\t\t |\\\n AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR\t |\\\n AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)\n#define HW_PRTY_ASSERT_SET_2 \\\n(AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR\t |\\\n AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR\t\t |\\\n AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\\\n AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR\t\t |\\\n AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR\t\t |\\\n AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR\t |\\\n AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR\t\t |\\\n AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)\n#define HW_PRTY_ASSERT_SET_3 \\\n(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY\t | \\\n AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \\\n AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \\\n AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)\n#define HW_PRTY_ASSERT_SET_4 \\\n(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |\\\n AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)\n#define HW_INTERRUT_ASSERT_SET_0 \\\n(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)\n#define HW_INTERRUT_ASSERT_SET_1 \\\n(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT\t |\\\n AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT |\\\n AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)\n#define HW_INTERRUT_ASSERT_SET_2 \\\n(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT\t |\\\n AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT\t\t\t|\\\n AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT\t\t\t|\\\n AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT\t\t\t|\\\n AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT\t\t|\\\n AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT\t|\\\n AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)\n\n\n#define RESERVED_GENERAL_ATTENTION_BIT_0\t0\n\n#define EVEREST_GEN_ATTN_IN_USE_MASK\t\t0x7ffe0\n#define EVEREST_LATCHED_ATTN_IN_USE_MASK\t0xffe00000\n\n#define RESERVED_GENERAL_ATTENTION_BIT_6\t6\n#define RESERVED_GENERAL_ATTENTION_BIT_7\t7\n#define RESERVED_GENERAL_ATTENTION_BIT_8\t8\n#define RESERVED_GENERAL_ATTENTION_BIT_9\t9\n#define RESERVED_GENERAL_ATTENTION_BIT_10\t10\n#define RESERVED_GENERAL_ATTENTION_BIT_11\t11\n#define RESERVED_GENERAL_ATTENTION_BIT_12\t12\n#define RESERVED_GENERAL_ATTENTION_BIT_13\t13\n#define RESERVED_GENERAL_ATTENTION_BIT_14\t14\n#define RESERVED_GENERAL_ATTENTION_BIT_15\t15\n#define RESERVED_GENERAL_ATTENTION_BIT_16\t16\n#define RESERVED_GENERAL_ATTENTION_BIT_17\t17\n#define RESERVED_GENERAL_ATTENTION_BIT_18\t18\n#define RESERVED_GENERAL_ATTENTION_BIT_19\t19\n#define RESERVED_GENERAL_ATTENTION_BIT_20\t20\n#define RESERVED_GENERAL_ATTENTION_BIT_21\t21\n\n/* storm asserts attention bits */\n#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7\n#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8\n#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9\n#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10\n\n/* mcp error attention bit */\n#define MCP_FATAL_ASSERT_ATTENTION_BIT\t RESERVED_GENERAL_ATTENTION_BIT_11\n\n/*E1H NIG status sync attention mapped to group 4-7*/\n#define LINK_SYNC_ATTENTION_BIT_FUNC_0\t RESERVED_GENERAL_ATTENTION_BIT_12\n#define LINK_SYNC_ATTENTION_BIT_FUNC_1\t RESERVED_GENERAL_ATTENTION_BIT_13\n#define LINK_SYNC_ATTENTION_BIT_FUNC_2\t RESERVED_GENERAL_ATTENTION_BIT_14\n#define LINK_SYNC_ATTENTION_BIT_FUNC_3\t RESERVED_GENERAL_ATTENTION_BIT_15\n#define LINK_SYNC_ATTENTION_BIT_FUNC_4\t RESERVED_GENERAL_ATTENTION_BIT_16\n#define LINK_SYNC_ATTENTION_BIT_FUNC_5\t RESERVED_GENERAL_ATTENTION_BIT_17\n#define LINK_SYNC_ATTENTION_BIT_FUNC_6\t RESERVED_GENERAL_ATTENTION_BIT_18\n#define LINK_SYNC_ATTENTION_BIT_FUNC_7\t RESERVED_GENERAL_ATTENTION_BIT_19\n\n\t/* Used For Error Recovery: changing this will require more \\\n\tchanges in code that assume\n * error recovery uses general attn bit20 ! */\n#define ERROR_RECOVERY_ATTENTION_BIT \\\n\tRESERVED_GENERAL_ATTENTION_BIT_20\n#define RESERVED_ATTENTION_BIT \\\n\tRESERVED_GENERAL_ATTENTION_BIT_21\n\n#define LATCHED_ATTN_RBCR\t\t\t23\n#define LATCHED_ATTN_RBCT\t\t\t24\n#define LATCHED_ATTN_RBCN\t\t\t25\n#define LATCHED_ATTN_RBCU\t\t\t26\n#define LATCHED_ATTN_RBCP\t\t\t27\n#define LATCHED_ATTN_TIMEOUT_GRC\t\t28\n#define LATCHED_ATTN_RSVD_GRC\t\t\t29\n#define LATCHED_ATTN_ROM_PARITY_MCP\t\t30\n#define LATCHED_ATTN_UM_RX_PARITY_MCP\t\t31\n#define LATCHED_ATTN_UM_TX_PARITY_MCP\t\t32\n#define LATCHED_ATTN_SCPAD_PARITY_MCP\t\t33\n\n#define GENERAL_ATTEN_WORD(atten_name)\t ((94 + atten_name) / 32)\n#define GENERAL_ATTEN_OFFSET(atten_name) (1UL << ((94 + atten_name) % 32))\n\n\n/*\n * This file defines GRC base address for every block.\n * This file is included by chipsim, asm microcode and cpp microcode.\n * These values are used in Design.xml on regBase attribute\n * Use the base with the generated offsets of specific registers.\n */\n\n#define GRCBASE_PXPCS\t 0x000000\n#define GRCBASE_PCICONFIG 0x002000\n#define GRCBASE_PCIREG\t 0x002400\n#define GRCBASE_EMAC0\t 0x008000\n#define GRCBASE_EMAC1\t 0x008400\n#define GRCBASE_DBU\t\t0x008800\n#define GRCBASE_PGLUE_B\t 0x009000\n#define GRCBASE_MISC\t 0x00A000\n#define GRCBASE_DBG\t\t0x00C000\n#define GRCBASE_NIG\t\t0x010000\n#define GRCBASE_XCM\t\t0x020000\n#define GRCBASE_PRS\t 0x040000\n#define GRCBASE_SRCH\t 0x040400\n#define GRCBASE_TSDM\t 0x042000\n#define GRCBASE_TCM\t\t0x050000\n#define GRCBASE_BRB1\t 0x060000\n#define GRCBASE_MCP\t\t0x080000\n#define GRCBASE_UPB\t\t0x0C1000\n#define GRCBASE_CSDM\t 0x0C2000\n#define GRCBASE_USDM\t 0x0C4000\n#define GRCBASE_CCM\t\t0x0D0000\n#define GRCBASE_UCM\t\t0x0E0000\n#define GRCBASE_CDU\t\t0x101000\n#define GRCBASE_DMAE\t 0x102000\n#define GRCBASE_PXP\t\t0x103000\n#define GRCBASE_CFC\t\t0x104000\n#define GRCBASE_HC\t\t0x108000\n#define GRCBASE_ATC\t\t0x110000\n#define GRCBASE_PXP2\t 0x120000\n#define GRCBASE_IGU\t 0x130000\n#define GRCBASE_PBF\t 0x140000\n#define GRCBASE_UMAC0\t 0x160000\n#define GRCBASE_UMAC1\t 0x160400\n#define GRCBASE_XPB\t 0x161000\n#define GRCBASE_MSTAT0\t 0x162000\n#define GRCBASE_MSTAT1\t 0x162800\n#define GRCBASE_XMAC0\t 0x163000\n#define GRCBASE_XMAC1\t 0x163800\n#define GRCBASE_TIMERS\t 0x164000\n#define GRCBASE_XSDM\t 0x166000\n#define GRCBASE_QM\t\t0x168000\n#define GRCBASE_QM_4PORT 0x168000\n#define GRCBASE_DQ\t\t0x170000\n#define GRCBASE_TSEM\t 0x180000\n#define GRCBASE_CSEM\t 0x200000\n#define GRCBASE_XSEM\t 0x280000\n#define GRCBASE_XSEM_4PORT 0x280000\n#define GRCBASE_USEM\t 0x300000\n#define GRCBASE_MCP_A\t 0x380000\n#define GRCBASE_MISC_AEU GRCBASE_MISC\n#define GRCBASE_Tstorm\t GRCBASE_TSEM\n#define GRCBASE_Cstorm\t GRCBASE_CSEM\n#define GRCBASE_Xstorm\t GRCBASE_XSEM\n#define GRCBASE_Ustorm\t GRCBASE_USEM\n\n\n/* offset of configuration space in the pci core register */\n#define PCICFG_OFFSET\t\t\t\t\t0x2000\n#define PCICFG_VENDOR_ID_OFFSET\t\t\t\t0x00\n#define PCICFG_DEVICE_ID_OFFSET\t\t\t\t0x02\n#define PCICFG_COMMAND_OFFSET\t\t\t\t0x04\n#define PCICFG_COMMAND_IO_SPACE\t\t\t(1<<0)\n#define PCICFG_COMMAND_MEM_SPACE\t\t(1<<1)\n#define PCICFG_COMMAND_BUS_MASTER\t\t(1<<2)\n#define PCICFG_COMMAND_SPECIAL_CYCLES\t\t(1<<3)\n#define PCICFG_COMMAND_MWI_CYCLES\t\t(1<<4)\n#define PCICFG_COMMAND_VGA_SNOOP\t\t(1<<5)\n#define PCICFG_COMMAND_PERR_ENA\t\t\t(1<<6)\n#define PCICFG_COMMAND_STEPPING\t\t\t(1<<7)\n#define PCICFG_COMMAND_SERR_ENA\t\t\t(1<<8)\n#define PCICFG_COMMAND_FAST_B2B\t\t\t(1<<9)\n#define PCICFG_COMMAND_INT_DISABLE\t\t(1<<10)\n#define PCICFG_COMMAND_RESERVED\t\t\t(0x1f<<11)\n#define PCICFG_STATUS_OFFSET\t\t\t\t0x06\n#define PCICFG_REVISION_ID_OFFSET\t\t\t0x08\n#define PCICFG_REVESION_ID_MASK\t\t\t0xff\n#define PCICFG_REVESION_ID_ERROR_VAL\t\t0xff\n#define PCICFG_CACHE_LINE_SIZE\t\t\t\t0x0c\n#define PCICFG_LATENCY_TIMER\t\t\t\t0x0d\n#define PCICFG_HEADER_TYPE\t\t\t\t0x0e\n#define PCICFG_HEADER_TYPE_NORMAL\t 0\n#define PCICFG_HEADER_TYPE_BRIDGE\t 1\n#define PCICFG_HEADER_TYPE_CARDBUS\t 2\n#define PCICFG_BAR_1_LOW\t\t\t\t0x10\n#define PCICFG_BAR_1_HIGH\t\t\t\t0x14\n#define PCICFG_BAR_2_LOW\t\t\t\t0x18\n#define PCICFG_BAR_2_HIGH\t\t\t\t0x1c\n#define PCICFG_BAR_3_LOW\t\t\t\t0x20\n#define PCICFG_BAR_3_HIGH\t\t\t\t0x24\n#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET\t\t0x2c\n#define PCICFG_SUBSYSTEM_ID_OFFSET\t\t\t0x2e\n#define PCICFG_INT_LINE\t\t\t\t\t0x3c\n#define PCICFG_INT_PIN\t\t\t\t\t0x3d\n#define PCICFG_PM_CAPABILITY\t\t\t\t0x48\n#define PCICFG_PM_CAPABILITY_VERSION\t\t(0x3<<16)\n#define PCICFG_PM_CAPABILITY_CLOCK\t\t(1<<19)\n#define PCICFG_PM_CAPABILITY_RESERVED\t\t(1<<20)\n#define PCICFG_PM_CAPABILITY_DSI\t\t(1<<21)\n#define PCICFG_PM_CAPABILITY_AUX_CURRENT\t(0x7<<22)\n#define PCICFG_PM_CAPABILITY_D1_SUPPORT\t\t(1<<25)\n#define PCICFG_PM_CAPABILITY_D2_SUPPORT\t\t(1<<26)\n#define PCICFG_PM_CAPABILITY_PME_IN_D0\t\t(1<<27)\n#define PCICFG_PM_CAPABILITY_PME_IN_D1\t\t(1<<28)\n#define PCICFG_PM_CAPABILITY_PME_IN_D2\t\t(1<<29)\n#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT\t(1<<30)\n#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD\t(1<<31)\n#define PCICFG_PM_CSR_OFFSET\t\t\t\t0x4c\n#define PCICFG_PM_CSR_STATE\t\t\t(0x3<<0)\n#define PCICFG_PM_CSR_PME_ENABLE\t\t(1<<8)\n#define PCICFG_PM_CSR_PME_STATUS\t\t(1<<15)\n#define PCICFG_VPD_FLAG_ADDR_OFFSET\t\t\t0x50\n#define PCICFG_VPD_DATA_OFFSET\t\t\t\t0x54\n#define PCICFG_MSI_CAP_ID_OFFSET\t\t\t0x58\n#define PCICFG_MSI_CONTROL_ENABLE\t\t(0x1<<16)\n#define PCICFG_MSI_CONTROL_MCAP\t\t\t(0x7<<17)\n#define PCICFG_MSI_CONTROL_MENA\t\t\t(0x7<<20)\n#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP\t(0x1<<23)\n#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE\t(0x1<<24)\n#define PCICFG_MSI_ADDR_LOW_OFFSET\t\t\t0x5c\n#define PCICFG_MSI_ADDR_HIGH_OFFSET\t\t\t0x60\n#define PCICFG_MSI_DATA_OFFSET\t\t\t\t0x64\n#define PCICFG_GRC_ADDRESS\t\t\t\t0x78\n#define PCICFG_GRC_DATA\t\t\t\t\t0x80\n#define PCICFG_ME_REGISTER\t\t 0x98\n#define PCICFG_MSIX_CAP_ID_OFFSET\t\t\t0xa0\n#define PCICFG_MSIX_CONTROL_TABLE_SIZE\t\t(0x7ff<<16)\n#define PCICFG_MSIX_CONTROL_RESERVED\t\t(0x7<<27)\n#define PCICFG_MSIX_CONTROL_FUNC_MASK\t\t(0x1<<30)\n#define PCICFG_MSIX_CONTROL_MSIX_ENABLE\t\t(0x1<<31)\n\n#define PCICFG_DEVICE_CONTROL\t\t\t\t0xb4\n#define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND (1<<21)\n#define PCICFG_DEVICE_STATUS\t\t\t\t0xb6\n#define PCICFG_DEVICE_STATUS_CORR_ERR_DET\t(1<<0)\n#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET\t(1<<1)\n#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET\t(1<<2)\n#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET\t(1<<3)\n#define PCICFG_DEVICE_STATUS_AUX_PWR_DET\t(1<<4)\n#define PCICFG_DEVICE_STATUS_NO_PEND\t\t(1<<5)\n#define PCICFG_LINK_CONTROL\t\t\t\t0xbc\n\n\n/* config_2 offset */\n#define GRC_CONFIG_2_SIZE_REG\t\t\t\t0x408\n#define PCI_CONFIG_2_BAR1_SIZE\t\t\t(0xfL<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_DISABLED\t\t(0L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_64K\t\t(1L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_128K\t\t(2L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_256K\t\t(3L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_512K\t\t(4L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_1M\t\t(5L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_2M\t\t(6L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_4M\t\t(7L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_8M\t\t(8L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_16M\t\t(9L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_32M\t\t(10L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_64M\t\t(11L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_128M\t\t(12L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_256M\t\t(13L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_512M\t\t(14L<<0)\n#define PCI_CONFIG_2_BAR1_SIZE_1G\t\t(15L<<0)\n#define PCI_CONFIG_2_BAR1_64ENA\t\t\t(1L<<4)\n#define PCI_CONFIG_2_EXP_ROM_RETRY\t\t(1L<<5)\n#define PCI_CONFIG_2_CFG_CYCLE_RETRY\t\t(1L<<6)\n#define PCI_CONFIG_2_FIRST_CFG_DONE\t\t(1L<<7)\n#define PCI_CONFIG_2_EXP_ROM_SIZE\t\t(0xffL<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED\t(0L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_2K\t\t(1L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_4K\t\t(2L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_8K\t\t(3L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_16K\t\t(4L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_32K\t\t(5L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_64K\t\t(6L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_128K\t\t(7L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_256K\t\t(8L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_512K\t\t(9L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_1M\t\t(10L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_2M\t\t(11L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_4M\t\t(12L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_8M\t\t(13L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_16M\t\t(14L<<8)\n#define PCI_CONFIG_2_EXP_ROM_SIZE_32M\t\t(15L<<8)\n#define PCI_CONFIG_2_BAR_PREFETCH\t\t(1L<<16)\n#define PCI_CONFIG_2_RESERVED0\t\t\t(0x7fffL<<17)\n\n/* config_3 offset */\n#define GRC_CONFIG_3_SIZE_REG\t\t\t\t0x40c\n#define PCI_CONFIG_3_STICKY_BYTE\t\t\t(0xffL<<0)\n#define PCI_CONFIG_3_FORCE_PME\t\t\t(1L<<24)\n#define PCI_CONFIG_3_PME_STATUS\t\t\t(1L<<25)\n#define PCI_CONFIG_3_PME_ENABLE\t\t\t(1L<<26)\n#define PCI_CONFIG_3_PM_STATE\t\t\t(0x3L<<27)\n#define PCI_CONFIG_3_VAUX_PRESET\t\t\t(1L<<30)\n#define PCI_CONFIG_3_PCI_POWER\t\t\t(1L<<31)\n\n#define GRC_REG_DEVICE_CONTROL\t\t 0x4d8\n#define PCIE_SRIOV_DISABLE_IN_PROGRESS \\\n\t(1 << 29) /*When VF Enable is cleared(after it was previously set),\n this register will read a value of 1, indicating that all the\n VFs that belong to this PF should be flushed.\n Software should clear this bit within 1 second of VF Enable\n being set by writing a 1 to it, so that VFs are visible to the system again.\n\t\t\t\t\t\t\tWC */\n#define PCIE_FLR_IN_PROGRESS \\\n\t(1 << 27) /*When FLR is initiated, this register will read a \\\n\tvalue of 1 indicating that the\n Function is in FLR state. Func can be brought out of FLR state either by\n writing 1 to this register (at least 50 ms after FLR was initiated),\n or it can also be cleared automatically after 55 ms if auto_clear bit\n in private reg space is set. This bit also exists in VF register space\n\t\t\t\t\t\t\tWC */\n\n#define GRC_BAR2_CONFIG\t\t\t\t\t0x4e0\n#define PCI_CONFIG_2_BAR2_SIZE\t\t\t(0xfL<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_DISABLED\t\t(0L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_64K\t\t(1L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_128K\t\t(2L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_256K\t\t(3L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_512K\t\t(4L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_1M\t\t(5L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_2M\t\t(6L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_4M\t\t(7L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_8M\t\t(8L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_16M\t\t(9L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_32M\t\t(10L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_64M\t\t(11L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_128M\t\t(12L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_256M\t\t(13L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_512M\t\t(14L<<0)\n#define PCI_CONFIG_2_BAR2_SIZE_1G\t\t(15L<<0)\n#define PCI_CONFIG_2_BAR2_64ENA\t\t\t(1L<<4)\n\n#define GRC_BAR3_CONFIG\t\t\t\t\t0x4f4\n#define PCI_CONFIG_2_BAR3_SIZE\t\t\t(0xfL<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_DISABLED\t\t(0L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_64K\t\t(1L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_128K\t\t(2L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_256K\t\t(3L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_512K\t\t(4L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_1M\t\t(5L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_2M\t\t(6L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_4M\t\t(7L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_8M\t\t(8L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_16M\t\t(9L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_32M\t\t(10L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_64M\t\t(11L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_128M\t\t(12L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_256M\t\t(13L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_512M\t\t(14L<<0)\n#define PCI_CONFIG_2_BAR3_SIZE_1G\t\t(15L<<0)\n#define PCI_CONFIG_2_BAR3_64ENA\t\t\t(1L<<4)\n\n#define PCI_PM_DATA_A\t\t\t\t\t0x410\n#define PCI_PM_DATA_B\t\t\t\t\t0x414\n#define PCI_ID_VAL1\t\t\t\t\t0x434\n#define PCI_ID_VAL2\t\t\t\t\t0x438\n#define PCI_ID_VAL3\t\t\t\t\t0x43c\n#define PCI_ID_VAL3_REVISION_ID_ERROR\t\t (0xffL<<24)\n\n\n#define GRC_CONFIG_REG_VF_BAR_REG_1\t\t0x608\n#define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE\t0xf\n\n#define GRC_CONFIG_REG_VF_MSIX_CONTROL\t\t 0x61C\n#define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK \\\n\t0x3F /*This field resides in VF only and does not exist in PF.\n This register controls the read value of the MSIX_CONTROL[10:0] register\n in the VF configuration space. A value of \"00000000011\" indicates\n a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ\n define in version.v */\n\n#define GRC_CONFIG_REG_PF_INIT_VF\t\t0x624\n#define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK \\\n\t0xf /*First VF_NUM for PF is encoded in this register.\n The number of VFs assigned to a PF is assumed to be a multiple of 8.\n\tSoftware should program these bits based on Total Number of VFs \\\n\tprogrammed for each PF.\n Since registers from 0x000-0x7ff are spilt across functions, each PF will have\n the same location for the same 4 bits*/\n\n#define PXPCS_TL_CONTROL_5\t\t\t0x814\n#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN\t (1 << 29) /*WC*/\n#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN\t (1 << 28) /*WC*/\n#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/\n#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN\t (1 << 26) /*WC*/\n#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/\n#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW\t (1 << 24) /*WC*/\n#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN\t (1 << 23) /*RO*/\n#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN\t (1 << 22) /*RO*/\n#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/\n#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/\n#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1\t (1 << 11) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/\n#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT\t (1 << 9) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT\t (1 << 8) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP\t (1 << 6) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW\t (1 << 5) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL\t (1 << 1) /*WC*/\n#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP\t (1 << 0) /*WC*/\n\n\n#define PXPCS_TL_FUNC345_STAT\t 0x854\n#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 \\\n\t(1 << 28) /* Unsupported Request Error Status in function4, if \\\n\tset, generate pcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 \\\n\t(1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 \\\n\t(1 << 26) /* Malformed TLP Status Status in function 4, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 \\\n\t(1 << 25) /* Receiver Overflow Status Status in function 4, if \\\n\tset, generate pcie_err_attn output when this error is seen.. WC \\\n\t*/\n#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 \\\n\t(1 << 24) /* Unexpected Completion Status Status in function 4, \\\n\tif set, generate pcie_err_attn output when this error is seen. WC \\\n\t*/\n#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 \\\n\t(1 << 23) /* Receive UR Statusin function 4. If set, generate \\\n\tpcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 \\\n\t(1 << 22) /* Completer Timeout Status Status in function 4, if \\\n\tset, generate pcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 \\\n\t(1 << 21) /* Flow Control Protocol Error Status Status in \\\n\tfunction 4, if set, generate pcie_err_attn output when this error \\\n\tis seen. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 \\\n\t(1 << 20) /* Poisoned Error Status Status in function 4, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 \\\n\t(1 << 18) /* Unsupported Request Error Status in function3, if \\\n\tset, generate pcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 \\\n\t(1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 \\\n\t(1 << 16) /* Malformed TLP Status Status in function 3, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 \\\n\t(1 << 15) /* Receiver Overflow Status Status in function 3, if \\\n\tset, generate pcie_err_attn output when this error is seen.. WC \\\n\t*/\n#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 \\\n\t(1 << 14) /* Unexpected Completion Status Status in function 3, \\\n\tif set, generate pcie_err_attn output when this error is seen. WC \\\n\t*/\n#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 \\\n\t(1 << 13) /* Receive UR Statusin function 3. If set, generate \\\n\tpcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 \\\n\t(1 << 12) /* Completer Timeout Status Status in function 3, if \\\n\tset, generate pcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 \\\n\t(1 << 11) /* Flow Control Protocol Error Status Status in \\\n\tfunction 3, if set, generate pcie_err_attn output when this error \\\n\tis seen. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 \\\n\t(1 << 10) /* Poisoned Error Status Status in function 3, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 \\\n\t(1 << 8) /* Unsupported Request Error Status for Function 2, if \\\n\tset, generate pcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 \\\n\t(1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 \\\n\t(1 << 6) /* Malformed TLP Status Status for Function 2, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 \\\n\t(1 << 5) /* Receiver Overflow Status Status for Function 2, if \\\n\tset, generate pcie_err_attn output when this error is seen.. WC \\\n\t*/\n#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 \\\n\t(1 << 4) /* Unexpected Completion Status Status for Function 2, \\\n\tif set, generate pcie_err_attn output when this error is seen. WC \\\n\t*/\n#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 \\\n\t(1 << 3) /* Receive UR Statusfor Function 2. If set, generate \\\n\tpcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 \\\n\t(1 << 2) /* Completer Timeout Status Status for Function 2, if \\\n\tset, generate pcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 \\\n\t(1 << 1) /* Flow Control Protocol Error Status Status for \\\n\tFunction 2, if set, generate pcie_err_attn output when this error \\\n\tis seen. WC */\n#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 \\\n\t(1 << 0) /* Poisoned Error Status Status for Function 2, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n\n\n#define PXPCS_TL_FUNC678_STAT 0x85C\n#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /*\t WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 \\\n\t(1 << 28) /* Unsupported Request Error Status in function7, if \\\n\tset, generate pcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 \\\n\t(1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 \\\n\t(1 << 26) /* Malformed TLP Status Status in function 7, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 \\\n\t(1 << 25) /* Receiver Overflow Status Status in function 7, if \\\n\tset, generate pcie_err_attn output when this error is seen.. WC \\\n\t*/\n#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 \\\n\t(1 << 24) /* Unexpected Completion Status Status in function 7, \\\n\tif set, generate pcie_err_attn output when this error is seen. WC \\\n\t*/\n#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 \\\n\t(1 << 23) /* Receive UR Statusin function 7. If set, generate \\\n\tpcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 \\\n\t(1 << 22) /* Completer Timeout Status Status in function 7, if \\\n\tset, generate pcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 \\\n\t(1 << 21) /* Flow Control Protocol Error Status Status in \\\n\tfunction 7, if set, generate pcie_err_attn output when this error \\\n\tis seen. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 \\\n\t(1 << 20) /* Poisoned Error Status Status in function 7, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /*\t WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 \\\n\t(1 << 18) /* Unsupported Request Error Status in function6, if \\\n\tset, generate pcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 \\\n\t(1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 \\\n\t(1 << 16) /* Malformed TLP Status Status in function 6, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 \\\n\t(1 << 15) /* Receiver Overflow Status Status in function 6, if \\\n\tset, generate pcie_err_attn output when this error is seen.. WC \\\n\t*/\n#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 \\\n\t(1 << 14) /* Unexpected Completion Status Status in function 6, \\\n\tif set, generate pcie_err_attn output when this error is seen. WC \\\n\t*/\n#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 \\\n\t(1 << 13) /* Receive UR Statusin function 6. If set, generate \\\n\tpcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 \\\n\t(1 << 12) /* Completer Timeout Status Status in function 6, if \\\n\tset, generate pcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 \\\n\t(1 << 11) /* Flow Control Protocol Error Status Status in \\\n\tfunction 6, if set, generate pcie_err_attn output when this error \\\n\tis seen. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 \\\n\t(1 << 10) /* Poisoned Error Status Status in function 6, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 \\\n\t(1 << 8) /* Unsupported Request Error Status for Function 5, if \\\n\tset, generate pcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 \\\n\t(1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 \\\n\t(1 << 6) /* Malformed TLP Status Status for Function 5, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 \\\n\t(1 << 5) /* Receiver Overflow Status Status for Function 5, if \\\n\tset, generate pcie_err_attn output when this error is seen.. WC \\\n\t*/\n#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 \\\n\t(1 << 4) /* Unexpected Completion Status Status for Function 5, \\\n\tif set, generate pcie_err_attn output when this error is seen. WC \\\n\t*/\n#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 \\\n\t(1 << 3) /* Receive UR Statusfor Function 5. If set, generate \\\n\tpcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 \\\n\t(1 << 2) /* Completer Timeout Status Status for Function 5, if \\\n\tset, generate pcie_err_attn output when this error is seen. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 \\\n\t(1 << 1) /* Flow Control Protocol Error Status Status for \\\n\tFunction 5, if set, generate pcie_err_attn output when this error \\\n\tis seen. WC */\n#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 \\\n\t(1 << 0) /* Poisoned Error Status Status for Function 5, if set, \\\n\tgenerate pcie_err_attn output when this error is seen.. WC */\n\n\n#define BAR_USTRORM_INTMEM\t\t\t\t0x400000\n#define BAR_CSTRORM_INTMEM\t\t\t\t0x410000\n#define BAR_XSTRORM_INTMEM\t\t\t\t0x420000\n#define BAR_TSTRORM_INTMEM\t\t\t\t0x430000\n\n/* for accessing the IGU in case of status block ACK */\n#define BAR_IGU_INTMEM\t\t\t\t\t0x440000\n\n#define BAR_DOORBELL_OFFSET\t\t\t\t0x800000\n\n#define BAR_ME_REGISTER\t\t\t\t\t0x450000\n#define ME_REG_PF_NUM_SHIFT\t\t0\n#define ME_REG_PF_NUM \\\n\t(7L<> ME_REG_VF_NUM_SHIFT)\n#define ME_REG_VF_ERR\t\t\t(0x1<<3)\n#define ME_REG_ABS_PF_NUM_SHIFT\t\t16\n#define ME_REG_ABS_PF_NUM \\\n\t(7L<\n * David Christensen \n * Gary Zambrano \n *\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"bnx2x.h\"\n#include \"ecore_init.h\"\n\n/**** Exe Queue interfaces ****/\n\n/**\n * ecore_exe_queue_init - init the Exe Queue object\n *\n * @o:\t\tpointer to the object\n * @exe_len:\tlength\n * @owner:\tpointer to the owner\n * @validate:\tvalidate function pointer\n * @optimize:\toptimize function pointer\n * @exec:\texecute function pointer\n * @get:\tget function pointer\n */\nstatic void\necore_exe_queue_init(struct bnx2x_softc *sc __rte_unused,\n\t\t struct ecore_exe_queue_obj *o,\n\t\t int exe_len,\n\t\t union ecore_qable_obj *owner,\n\t\t exe_q_validate validate,\n\t\t exe_q_remove remove,\n\t\t exe_q_optimize optimize, exe_q_execute exec, exe_q_get get)\n{\n\tECORE_MEMSET(o, 0, sizeof(*o));\n\n\tECORE_LIST_INIT(&o->exe_queue);\n\tECORE_LIST_INIT(&o->pending_comp);\n\n\tECORE_SPIN_LOCK_INIT(&o->lock, sc);\n\n\to->exe_chunk_len = exe_len;\n\to->owner = owner;\n\n\t/* Owner specific callbacks */\n\to->validate = validate;\n\to->remove = remove;\n\to->optimize = optimize;\n\to->execute = exec;\n\to->get = get;\n\n\tECORE_MSG(\"Setup the execution queue with the chunk length of %d\",\n\t\t exe_len);\n}\n\nstatic void ecore_exe_queue_free_elem(struct bnx2x_softc *sc __rte_unused,\n\t\t\t\t struct ecore_exeq_elem *elem)\n{\n\tECORE_MSG(\"Deleting an exe_queue element\");\n\tECORE_FREE(sc, elem, sizeof(*elem));\n}\n\nstatic inline int ecore_exe_queue_length(struct ecore_exe_queue_obj *o)\n{\n\tstruct ecore_exeq_elem *elem;\n\tint cnt = 0;\n\n\tECORE_SPIN_LOCK_BH(&o->lock);\n\n\tECORE_LIST_FOR_EACH_ENTRY(elem, &o->exe_queue, link,\n\t\t\t\t struct ecore_exeq_elem) cnt++;\n\n\tECORE_SPIN_UNLOCK_BH(&o->lock);\n\n\treturn cnt;\n}\n\n/**\n * ecore_exe_queue_add - add a new element to the execution queue\n *\n * @sc:\t\tdriver handle\n * @o:\t\tqueue\n * @cmd:\tnew command to add\n * @restore:\ttrue - do not optimize the command\n *\n * If the element is optimized or is illegal, frees it.\n */\nstatic int ecore_exe_queue_add(struct bnx2x_softc *sc,\n\t\t\t struct ecore_exe_queue_obj *o,\n\t\t\t struct ecore_exeq_elem *elem, int restore)\n{\n\tint rc;\n\n\tECORE_SPIN_LOCK_BH(&o->lock);\n\n\tif (!restore) {\n\t\t/* Try to cancel this element queue */\n\t\trc = o->optimize(sc, o->owner, elem);\n\t\tif (rc)\n\t\t\tgoto free_and_exit;\n\n\t\t/* Check if this request is ok */\n\t\trc = o->validate(sc, o->owner, elem);\n\t\tif (rc) {\n\t\t\tECORE_MSG(\"Preamble failed: %d\", rc);\n\t\t\tgoto free_and_exit;\n\t\t}\n\t}\n\n\t/* If so, add it to the execution queue */\n\tECORE_LIST_PUSH_TAIL(&elem->link, &o->exe_queue);\n\n\tECORE_SPIN_UNLOCK_BH(&o->lock);\n\n\treturn ECORE_SUCCESS;\n\nfree_and_exit:\n\tecore_exe_queue_free_elem(sc, elem);\n\n\tECORE_SPIN_UNLOCK_BH(&o->lock);\n\n\treturn rc;\n}\n\nstatic void __ecore_exe_queue_reset_pending(struct bnx2x_softc *sc, struct ecore_exe_queue_obj\n\t\t\t\t\t *o)\n{\n\tstruct ecore_exeq_elem *elem;\n\n\twhile (!ECORE_LIST_IS_EMPTY(&o->pending_comp)) {\n\t\telem = ECORE_LIST_FIRST_ENTRY(&o->pending_comp,\n\t\t\t\t\t struct ecore_exeq_elem, link);\n\n\t\tECORE_LIST_REMOVE_ENTRY(&elem->link, &o->pending_comp);\n\t\tecore_exe_queue_free_elem(sc, elem);\n\t}\n}\n\nstatic inline void ecore_exe_queue_reset_pending(struct bnx2x_softc *sc,\n\t\t\t\t\t\t struct ecore_exe_queue_obj *o)\n{\n\tECORE_SPIN_LOCK_BH(&o->lock);\n\n\t__ecore_exe_queue_reset_pending(sc, o);\n\n\tECORE_SPIN_UNLOCK_BH(&o->lock);\n}\n\n/**\n * ecore_exe_queue_step - execute one execution chunk atomically\n *\n * @sc:\t\t\tdriver handle\n * @o:\t\t\tqueue\n * @ramrod_flags:\tflags\n *\n * (Should be called while holding the exe_queue->lock).\n */\nstatic int ecore_exe_queue_step(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_exe_queue_obj *o,\n\t\t\t\tunsigned long *ramrod_flags)\n{\n\tstruct ecore_exeq_elem *elem, spacer;\n\tint cur_len = 0, rc;\n\n\tECORE_MEMSET(&spacer, 0, sizeof(spacer));\n\n\t/* Next step should not be performed until the current is finished,\n\t * unless a DRV_CLEAR_ONLY bit is set. In this case we just want to\n\t * properly clear object internals without sending any command to the FW\n\t * which also implies there won't be any completion to clear the\n\t * 'pending' list.\n\t */\n\tif (!ECORE_LIST_IS_EMPTY(&o->pending_comp)) {\n\t\tif (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {\n\t\t\tECORE_MSG\n\t\t\t (\"RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\");\n\t\t\t__ecore_exe_queue_reset_pending(sc, o);\n\t\t} else {\n\t\t\treturn ECORE_PENDING;\n\t\t}\n\t}\n\n\t/* Run through the pending commands list and create a next\n\t * execution chunk.\n\t */\n\twhile (!ECORE_LIST_IS_EMPTY(&o->exe_queue)) {\n\t\telem = ECORE_LIST_FIRST_ENTRY(&o->exe_queue,\n\t\t\t\t\t struct ecore_exeq_elem, link);\n\t\tECORE_DBG_BREAK_IF(!elem->cmd_len);\n\n\t\tif (cur_len + elem->cmd_len <= o->exe_chunk_len) {\n\t\t\tcur_len += elem->cmd_len;\n\t\t\t/* Prevent from both lists being empty when moving an\n\t\t\t * element. This will allow the call of\n\t\t\t * ecore_exe_queue_empty() without locking.\n\t\t\t */\n\t\t\tECORE_LIST_PUSH_TAIL(&spacer.link, &o->pending_comp);\n\t\t\tmb();\n\t\t\tECORE_LIST_REMOVE_ENTRY(&elem->link, &o->exe_queue);\n\t\t\tECORE_LIST_PUSH_TAIL(&elem->link, &o->pending_comp);\n\t\t\tECORE_LIST_REMOVE_ENTRY(&spacer.link, &o->pending_comp);\n\t\t} else\n\t\t\tbreak;\n\t}\n\n\t/* Sanity check */\n\tif (!cur_len)\n\t\treturn ECORE_SUCCESS;\n\n\trc = o->execute(sc, o->owner, &o->pending_comp, ramrod_flags);\n\tif (rc < 0)\n\t\t/* In case of an error return the commands back to the queue\n\t\t * and reset the pending_comp.\n\t\t */\n\t\tECORE_LIST_SPLICE_INIT(&o->pending_comp, &o->exe_queue);\n\telse if (!rc)\n\t\t/* If zero is returned, means there are no outstanding pending\n\t\t * completions and we may dismiss the pending list.\n\t\t */\n\t\t__ecore_exe_queue_reset_pending(sc, o);\n\n\treturn rc;\n}\n\nstatic inline int ecore_exe_queue_empty(struct ecore_exe_queue_obj *o)\n{\n\tint empty = ECORE_LIST_IS_EMPTY(&o->exe_queue);\n\n\t/* Don't reorder!!! */\n\tmb();\n\n\treturn empty && ECORE_LIST_IS_EMPTY(&o->pending_comp);\n}\n\nstatic struct ecore_exeq_elem *ecore_exe_queue_alloc_elem(struct\n\t\t\t\t\t\t\t bnx2x_softc *sc\n\t\t\t\t\t\t\t __rte_unused)\n{\n\tECORE_MSG(\"Allocating a new exe_queue element\");\n\treturn ECORE_ZALLOC(sizeof(struct ecore_exeq_elem), GFP_ATOMIC, sc);\n}\n\n/************************ raw_obj functions ***********************************/\nstatic int ecore_raw_check_pending(struct ecore_raw_obj *o)\n{\n\t/*\n\t * !! converts the value returned by ECORE_TEST_BIT such that it\n\t * is guaranteed not to be truncated regardless of int definition.\n\t *\n\t * Note we cannot simply define the function's return value type\n\t * to match the type returned by ECORE_TEST_BIT, as it varies by\n\t * platform/implementation.\n\t */\n\n\treturn ! !ECORE_TEST_BIT(o->state, o->pstate);\n}\n\nstatic void ecore_raw_clear_pending(struct ecore_raw_obj *o)\n{\n\tECORE_SMP_MB_BEFORE_CLEAR_BIT();\n\tECORE_CLEAR_BIT(o->state, o->pstate);\n\tECORE_SMP_MB_AFTER_CLEAR_BIT();\n}\n\nstatic void ecore_raw_set_pending(struct ecore_raw_obj *o)\n{\n\tECORE_SMP_MB_BEFORE_CLEAR_BIT();\n\tECORE_SET_BIT(o->state, o->pstate);\n\tECORE_SMP_MB_AFTER_CLEAR_BIT();\n}\n\n/**\n * ecore_state_wait - wait until the given bit(state) is cleared\n *\n * @sc:\t\tdevice handle\n * @state:\tstate which is to be cleared\n * @state_p:\tstate buffer\n *\n */\nstatic int ecore_state_wait(struct bnx2x_softc *sc, int state,\n\t\t\t unsigned long *pstate)\n{\n\t/* can take a while if any port is running */\n\tint cnt = 5000;\n\n\tif (CHIP_REV_IS_EMUL(sc))\n\t\tcnt *= 20;\n\n\tECORE_MSG(\"waiting for state to become %d\", state);\n\n\tECORE_MIGHT_SLEEP();\n\twhile (cnt--) {\n\t\tbnx2x_intr_legacy(sc, 1);\n\t\tif (!ECORE_TEST_BIT(state, pstate)) {\n#ifdef ECORE_STOP_ON_ERROR\n\t\t\tECORE_MSG(\"exit (cnt %d)\", 5000 - cnt);\n#endif\n\t\t\treturn ECORE_SUCCESS;\n\t\t}\n\n\t\tECORE_WAIT(sc, delay_us);\n\n\t\tif (sc->panic)\n\t\t\treturn ECORE_IO;\n\t}\n\n\t/* timeout! */\n\tPMD_DRV_LOG(ERR, \"timeout waiting for state %d\", state);\n#ifdef ECORE_STOP_ON_ERROR\n\tecore_panic();\n#endif\n\n\treturn ECORE_TIMEOUT;\n}\n\nstatic int ecore_raw_wait(struct bnx2x_softc *sc, struct ecore_raw_obj *raw)\n{\n\treturn ecore_state_wait(sc, raw->state, raw->pstate);\n}\n\n/***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/\n/* credit handling callbacks */\nstatic int ecore_get_cam_offset_mac(struct ecore_vlan_mac_obj *o, int *offset)\n{\n\tstruct ecore_credit_pool_obj *mp = o->macs_pool;\n\n\tECORE_DBG_BREAK_IF(!mp);\n\n\treturn mp->get_entry(mp, offset);\n}\n\nstatic int ecore_get_credit_mac(struct ecore_vlan_mac_obj *o)\n{\n\tstruct ecore_credit_pool_obj *mp = o->macs_pool;\n\n\tECORE_DBG_BREAK_IF(!mp);\n\n\treturn mp->get(mp, 1);\n}\n\nstatic int ecore_put_cam_offset_mac(struct ecore_vlan_mac_obj *o, int offset)\n{\n\tstruct ecore_credit_pool_obj *mp = o->macs_pool;\n\n\treturn mp->put_entry(mp, offset);\n}\n\nstatic int ecore_put_credit_mac(struct ecore_vlan_mac_obj *o)\n{\n\tstruct ecore_credit_pool_obj *mp = o->macs_pool;\n\n\treturn mp->put(mp, 1);\n}\n\n/**\n * __ecore_vlan_mac_h_write_trylock - try getting the writer lock on vlan mac\n * head list.\n *\n * @sc:\t\tdevice handle\n * @o:\t\tvlan_mac object\n *\n * @details: Non-blocking implementation; should be called under execution\n * queue lock.\n */\nstatic int __ecore_vlan_mac_h_write_trylock(struct bnx2x_softc *sc __rte_unused,\n\t\t\t\t\t struct ecore_vlan_mac_obj *o)\n{\n\tif (o->head_reader) {\n\t\tECORE_MSG(\"vlan_mac_lock writer - There are readers; Busy\");\n\t\treturn ECORE_BUSY;\n\t}\n\n\tECORE_MSG(\"vlan_mac_lock writer - Taken\");\n\treturn ECORE_SUCCESS;\n}\n\n/**\n * __ecore_vlan_mac_h_exec_pending - execute step instead of a previous step\n * which wasn't able to run due to a taken lock on vlan mac head list.\n *\n * @sc:\t\tdevice handle\n * @o:\t\tvlan_mac object\n *\n * @details Should be called under execution queue lock; notice it might release\n * and reclaim it during its run.\n */\nstatic void __ecore_vlan_mac_h_exec_pending(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_vlan_mac_obj *o)\n{\n\tint rc;\n\tunsigned long ramrod_flags = o->saved_ramrod_flags;\n\n\tECORE_MSG(\"vlan_mac_lock execute pending command with ramrod flags %lu\",\n\t\t ramrod_flags);\n\to->head_exe_request = FALSE;\n\to->saved_ramrod_flags = 0;\n\trc = ecore_exe_queue_step(sc, &o->exe_queue, &ramrod_flags);\n\tif (rc != ECORE_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"execution of pending commands failed with rc %d\",\n\t\t\t rc);\n#ifdef ECORE_STOP_ON_ERROR\n\t\tecore_panic();\n#endif\n\t}\n}\n\n/**\n * __ecore_vlan_mac_h_pend - Pend an execution step which couldn't have been\n * called due to vlan mac head list lock being taken.\n *\n * @sc:\t\t\tdevice handle\n * @o:\t\t\tvlan_mac object\n * @ramrod_flags:\tramrod flags of missed execution\n *\n * @details Should be called under execution queue lock.\n */\nstatic void __ecore_vlan_mac_h_pend(struct bnx2x_softc *sc __rte_unused,\n\t\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t\t unsigned long ramrod_flags)\n{\n\to->head_exe_request = TRUE;\n\to->saved_ramrod_flags = ramrod_flags;\n\tECORE_MSG(\"Placing pending execution with ramrod flags %lu\",\n\t\t ramrod_flags);\n}\n\n/**\n * __ecore_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock\n *\n * @sc:\t\t\tdevice handle\n * @o:\t\t\tvlan_mac object\n *\n * @details Should be called under execution queue lock. Notice if a pending\n * execution exists, it would perform it - possibly releasing and\n * reclaiming the execution queue lock.\n */\nstatic void __ecore_vlan_mac_h_write_unlock(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_vlan_mac_obj *o)\n{\n\t/* It's possible a new pending execution was added since this writer\n\t * executed. If so, execute again. [Ad infinitum]\n\t */\n\twhile (o->head_exe_request) {\n\t\tECORE_MSG\n\t\t (\"vlan_mac_lock - writer release encountered a pending request\");\n\t\t__ecore_vlan_mac_h_exec_pending(sc, o);\n\t}\n}\n\n/**\n * ecore_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock\n *\n * @sc:\t\t\tdevice handle\n * @o:\t\t\tvlan_mac object\n *\n * @details Notice if a pending execution exists, it would perform it -\n * possibly releasing and reclaiming the execution queue lock.\n */\nvoid ecore_vlan_mac_h_write_unlock(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_vlan_mac_obj *o)\n{\n\tECORE_SPIN_LOCK_BH(&o->exe_queue.lock);\n\t__ecore_vlan_mac_h_write_unlock(sc, o);\n\tECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock);\n}\n\n/**\n * __ecore_vlan_mac_h_read_lock - lock the vlan mac head list reader lock\n *\n * @sc:\t\t\tdevice handle\n * @o:\t\t\tvlan_mac object\n *\n * @details Should be called under the execution queue lock. May sleep. May\n * release and reclaim execution queue lock during its run.\n */\nstatic int __ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc __rte_unused,\n\t\t\t\t\tstruct ecore_vlan_mac_obj *o)\n{\n\t/* If we got here, we're holding lock --> no WRITER exists */\n\to->head_reader++;\n\tECORE_MSG(\"vlan_mac_lock - locked reader - number %d\", o->head_reader);\n\n\treturn ECORE_SUCCESS;\n}\n\n/**\n * ecore_vlan_mac_h_read_lock - lock the vlan mac head list reader lock\n *\n * @sc:\t\t\tdevice handle\n * @o:\t\t\tvlan_mac object\n *\n * @details May sleep. Claims and releases execution queue lock during its run.\n */\nstatic int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_vlan_mac_obj *o)\n{\n\tint rc;\n\n\tECORE_SPIN_LOCK_BH(&o->exe_queue.lock);\n\trc = __ecore_vlan_mac_h_read_lock(sc, o);\n\tECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock);\n\n\treturn rc;\n}\n\n/**\n * __ecore_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock\n *\n * @sc:\t\t\tdevice handle\n * @o:\t\t\tvlan_mac object\n *\n * @details Should be called under execution queue lock. Notice if a pending\n * execution exists, it would be performed if this was the last\n * reader. possibly releasing and reclaiming the execution queue lock.\n */\nstatic void __ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_vlan_mac_obj *o)\n{\n\tif (!o->head_reader) {\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"Need to release vlan mac reader lock, but lock isn't taken\");\n#ifdef ECORE_STOP_ON_ERROR\n\t\tecore_panic();\n#endif\n\t} else {\n\t\to->head_reader--;\n\t\tPMD_DRV_LOG(INFO,\n\t\t\t \"vlan_mac_lock - decreased readers to %d\",\n\t\t\t o->head_reader);\n\t}\n\n\t/* It's possible a new pending execution was added, and that this reader\n\t * was last - if so we need to execute the command.\n\t */\n\tif (!o->head_reader && o->head_exe_request) {\n\t\tPMD_DRV_LOG(INFO,\n\t\t\t \"vlan_mac_lock - reader release encountered a pending request\");\n\n\t\t/* Writer release will do the trick */\n\t\t__ecore_vlan_mac_h_write_unlock(sc, o);\n\t}\n}\n\n/**\n * ecore_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock\n *\n * @sc:\t\t\tdevice handle\n * @o:\t\t\tvlan_mac object\n *\n * @details Notice if a pending execution exists, it would be performed if this\n * was the last reader. Claims and releases the execution queue lock\n * during its run.\n */\nvoid ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_vlan_mac_obj *o)\n{\n\tECORE_SPIN_LOCK_BH(&o->exe_queue.lock);\n\t__ecore_vlan_mac_h_read_unlock(sc, o);\n\tECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock);\n}\n\n/**\n * ecore_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock\n *\n * @sc:\t\t\tdevice handle\n * @o:\t\t\tvlan_mac object\n * @n:\t\t\tnumber of elements to get\n * @base:\t\tbase address for element placement\n * @stride:\t\tstride between elements (in bytes)\n */\nstatic int ecore_get_n_elements(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_vlan_mac_obj *o, int n,\n\t\t\t\tuint8_t * base, uint8_t stride, uint8_t size)\n{\n\tstruct ecore_vlan_mac_registry_elem *pos;\n\tuint8_t *next = base;\n\tint counter = 0, read_lock;\n\n\tECORE_MSG(\"get_n_elements - taking vlan_mac_lock (reader)\");\n\tread_lock = ecore_vlan_mac_h_read_lock(sc, o);\n\tif (read_lock != ECORE_SUCCESS)\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"get_n_elements failed to get vlan mac reader lock; Access without lock\");\n\n\t/* traverse list */\n\tECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link,\n\t\t\t\t struct ecore_vlan_mac_registry_elem) {\n\t\tif (counter < n) {\n\t\t\tECORE_MEMCPY(next, &pos->u, size);\n\t\t\tcounter++;\n\t\t\tECORE_MSG\n\t\t\t (\"copied element number %d to address %p element was:\",\n\t\t\t counter, next);\n\t\t\tnext += stride + size;\n\t\t}\n\t}\n\n\tif (read_lock == ECORE_SUCCESS) {\n\t\tECORE_MSG(\"get_n_elements - releasing vlan_mac_lock (reader)\");\n\t\tecore_vlan_mac_h_read_unlock(sc, o);\n\t}\n\n\treturn counter * ETH_ALEN;\n}\n\n/* check_add() callbacks */\nstatic int ecore_check_mac_add(struct bnx2x_softc *sc __rte_unused,\n\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t union ecore_classification_ramrod_data *data)\n{\n\tstruct ecore_vlan_mac_registry_elem *pos;\n\n\tECORE_MSG(\"Checking MAC %02x:%02x:%02x:%02x:%02x:%02x for ADD command\",\n\t\t data->mac.mac[0], data->mac.mac[1], data->mac.mac[2],\n\t\t data->mac.mac[3], data->mac.mac[4], data->mac.mac[5]);\n\n\tif (!ECORE_IS_VALID_ETHER_ADDR(data->mac.mac))\n\t\treturn ECORE_INVAL;\n\n\t/* Check if a requested MAC already exists */\n\tECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link,\n\t\t\t\t struct ecore_vlan_mac_registry_elem)\n\t if (!ECORE_MEMCMP(data->mac.mac, pos->u.mac.mac, ETH_ALEN) &&\n\t\t(data->mac.is_inner_mac == pos->u.mac.is_inner_mac))\n\t\treturn ECORE_EXISTS;\n\n\treturn ECORE_SUCCESS;\n}\n\n/* check_del() callbacks */\nstatic struct ecore_vlan_mac_registry_elem *ecore_check_mac_del(struct bnx2x_softc\n\t\t\t\t\t\t\t\t*sc\n\t\t\t\t\t\t\t\t__rte_unused,\n\t\t\t\t\t\t\t\tstruct\n\t\t\t\t\t\t\t\tecore_vlan_mac_obj\n\t\t\t\t\t\t\t\t*o, union\n\t\t\t\t\t\t\t\tecore_classification_ramrod_data\n\t\t\t\t\t\t\t\t*data)\n{\n\tstruct ecore_vlan_mac_registry_elem *pos;\n\n\tECORE_MSG(\"Checking MAC %02x:%02x:%02x:%02x:%02x:%02x for DEL command\",\n\t\t data->mac.mac[0], data->mac.mac[1], data->mac.mac[2],\n\t\t data->mac.mac[3], data->mac.mac[4], data->mac.mac[5]);\n\n\tECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link,\n\t\t\t\t struct ecore_vlan_mac_registry_elem)\n\tif ((!ECORE_MEMCMP(data->mac.mac, pos->u.mac.mac, ETH_ALEN)) &&\n\t (data->mac.is_inner_mac == pos->u.mac.is_inner_mac))\n\t\treturn pos;\n\n\treturn NULL;\n}\n\n/* check_move() callback */\nstatic int ecore_check_move(struct bnx2x_softc *sc,\n\t\t\t struct ecore_vlan_mac_obj *src_o,\n\t\t\t struct ecore_vlan_mac_obj *dst_o,\n\t\t\t union ecore_classification_ramrod_data *data)\n{\n\tstruct ecore_vlan_mac_registry_elem *pos;\n\tint rc;\n\n\t/* Check if we can delete the requested configuration from the first\n\t * object.\n\t */\n\tpos = src_o->check_del(sc, src_o, data);\n\n\t/* check if configuration can be added */\n\trc = dst_o->check_add(sc, dst_o, data);\n\n\t/* If this classification can not be added (is already set)\n\t * or can't be deleted - return an error.\n\t */\n\tif (rc || !pos)\n\t\treturn FALSE;\n\n\treturn TRUE;\n}\n\nstatic int ecore_check_move_always_err(__rte_unused struct bnx2x_softc *sc,\n\t\t\t\t __rte_unused struct ecore_vlan_mac_obj\n\t\t\t\t *src_o, __rte_unused struct ecore_vlan_mac_obj\n\t\t\t\t *dst_o, __rte_unused union\n\t\t\t\t ecore_classification_ramrod_data *data)\n{\n\treturn FALSE;\n}\n\nstatic uint8_t ecore_vlan_mac_get_rx_tx_flag(struct ecore_vlan_mac_obj\n\t\t\t\t\t *o)\n{\n\tstruct ecore_raw_obj *raw = &o->raw;\n\tuint8_t rx_tx_flag = 0;\n\n\tif ((raw->obj_type == ECORE_OBJ_TYPE_TX) ||\n\t (raw->obj_type == ECORE_OBJ_TYPE_RX_TX))\n\t\trx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_TX_CMD;\n\n\tif ((raw->obj_type == ECORE_OBJ_TYPE_RX) ||\n\t (raw->obj_type == ECORE_OBJ_TYPE_RX_TX))\n\t\trx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_RX_CMD;\n\n\treturn rx_tx_flag;\n}\n\nstatic void ecore_set_mac_in_nig(struct bnx2x_softc *sc,\n\t\t\t\t int add, unsigned char *dev_addr, int index)\n{\n\tuint32_t wb_data[2];\n\tuint32_t reg_offset = ECORE_PORT_ID(sc) ? NIG_REG_LLH1_FUNC_MEM :\n\t NIG_REG_LLH0_FUNC_MEM;\n\n\tif (!ECORE_IS_MF_SI_MODE(sc) && !IS_MF_AFEX(sc))\n\t\treturn;\n\n\tif (index > ECORE_LLH_CAM_MAX_PF_LINE)\n\t\treturn;\n\n\tECORE_MSG(\"Going to %s LLH configuration at entry %d\",\n\t\t (add ? \"ADD\" : \"DELETE\"), index);\n\n\tif (add) {\n\t\t/* LLH_FUNC_MEM is a uint64_t WB register */\n\t\treg_offset += 8 * index;\n\n\t\twb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |\n\t\t\t (dev_addr[4] << 8) | dev_addr[5]);\n\t\twb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);\n\n\t\tECORE_REG_WR_DMAE_LEN(sc, reg_offset, wb_data, 2);\n\t}\n\n\tREG_WR(sc, (ECORE_PORT_ID(sc) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :\n\t\t NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4 * index, add);\n}\n\n/**\n * ecore_vlan_mac_set_cmd_hdr_e2 - set a header in a single classify ramrod\n *\n * @sc:\t\tdevice handle\n * @o:\t\tqueue for which we want to configure this rule\n * @add:\tif TRUE the command is an ADD command, DEL otherwise\n * @opcode:\tCLASSIFY_RULE_OPCODE_XXX\n * @hdr:\tpointer to a header to setup\n *\n */\nstatic void ecore_vlan_mac_set_cmd_hdr_e2(struct ecore_vlan_mac_obj *o,\n\t\t\t\t\t int add, int opcode,\n\t\t\t\t\t struct eth_classify_cmd_header\n\t\t\t\t\t *hdr)\n{\n\tstruct ecore_raw_obj *raw = &o->raw;\n\n\thdr->client_id = raw->cl_id;\n\thdr->func_id = raw->func_id;\n\n\t/* Rx or/and Tx (internal switching) configuration ? */\n\thdr->cmd_general_data |= ecore_vlan_mac_get_rx_tx_flag(o);\n\n\tif (add)\n\t\thdr->cmd_general_data |= ETH_CLASSIFY_CMD_HEADER_IS_ADD;\n\n\thdr->cmd_general_data |=\n\t (opcode << ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT);\n}\n\n/**\n * ecore_vlan_mac_set_rdata_hdr_e2 - set the classify ramrod data header\n *\n * @cid:\tconnection id\n * @type:\tECORE_FILTER_XXX_PENDING\n * @hdr:\tpointer to header to setup\n * @rule_cnt:\n *\n * currently we always configure one rule and echo field to contain a CID and an\n * opcode type.\n */\nstatic void ecore_vlan_mac_set_rdata_hdr_e2(uint32_t cid, int type, struct eth_classify_header\n\t\t\t\t\t *hdr, int rule_cnt)\n{\n\thdr->echo = ECORE_CPU_TO_LE32((cid & ECORE_SWCID_MASK) |\n\t\t\t\t (type << ECORE_SWCID_SHIFT));\n\thdr->rule_cnt = (uint8_t) rule_cnt;\n}\n\n/* hw_config() callbacks */\nstatic void ecore_set_one_mac_e2(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t\t struct ecore_exeq_elem *elem, int rule_idx,\n\t\t\t\t __rte_unused int cam_offset)\n{\n\tstruct ecore_raw_obj *raw = &o->raw;\n\tstruct eth_classify_rules_ramrod_data *data =\n\t (struct eth_classify_rules_ramrod_data *)(raw->rdata);\n\tint rule_cnt = rule_idx + 1, cmd = elem->cmd_data.vlan_mac.cmd;\n\tunion eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];\n\tint add = (cmd == ECORE_VLAN_MAC_ADD) ? TRUE : FALSE;\n\tunsigned long *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags;\n\tuint8_t *mac = elem->cmd_data.vlan_mac.u.mac.mac;\n\n\t/* Set LLH CAM entry: currently only iSCSI and ETH macs are\n\t * relevant. In addition, current implementation is tuned for a\n\t * single ETH MAC.\n\t *\n\t * When multiple unicast ETH MACs PF configuration in switch\n\t * independent mode is required (NetQ, multiple netdev MACs,\n\t * etc.), consider better utilisation of 8 per function MAC\n\t * entries in the LLH register. There is also\n\t * NIG_REG_P[01]_LLH_FUNC_MEM2 registers that complete the\n\t * total number of CAM entries to 16.\n\t *\n\t * Currently we won't configure NIG for MACs other than a primary ETH\n\t * MAC and iSCSI L2 MAC.\n\t *\n\t * If this MAC is moving from one Queue to another, no need to change\n\t * NIG configuration.\n\t */\n\tif (cmd != ECORE_VLAN_MAC_MOVE) {\n\t\tif (ECORE_TEST_BIT(ECORE_ISCSI_ETH_MAC, vlan_mac_flags))\n\t\t\tecore_set_mac_in_nig(sc, add, mac,\n\t\t\t\t\t ECORE_LLH_CAM_ISCSI_ETH_LINE);\n\t\telse if (ECORE_TEST_BIT(ECORE_ETH_MAC, vlan_mac_flags))\n\t\t\tecore_set_mac_in_nig(sc, add, mac,\n\t\t\t\t\t ECORE_LLH_CAM_ETH_LINE);\n\t}\n\n\t/* Reset the ramrod data buffer for the first rule */\n\tif (rule_idx == 0)\n\t\tECORE_MEMSET(data, 0, sizeof(*data));\n\n\t/* Setup a command header */\n\tecore_vlan_mac_set_cmd_hdr_e2(o, add, CLASSIFY_RULE_OPCODE_MAC,\n\t\t\t\t &rule_entry->mac.header);\n\n\tECORE_MSG(\"About to %s MAC %02x:%02x:%02x:%02x:%02x:%02x for Queue %d\",\n\t\t (add ? \"add\" : \"delete\"), mac[0], mac[1], mac[2], mac[3],\n\t\t mac[4], mac[5], raw->cl_id);\n\n\t/* Set a MAC itself */\n\tecore_set_fw_mac_addr(&rule_entry->mac.mac_msb,\n\t\t\t &rule_entry->mac.mac_mid,\n\t\t\t &rule_entry->mac.mac_lsb, mac);\n\trule_entry->mac.inner_mac = elem->cmd_data.vlan_mac.u.mac.is_inner_mac;\n\n\t/* MOVE: Add a rule that will add this MAC to the target Queue */\n\tif (cmd == ECORE_VLAN_MAC_MOVE) {\n\t\trule_entry++;\n\t\trule_cnt++;\n\n\t\t/* Setup ramrod data */\n\t\tecore_vlan_mac_set_cmd_hdr_e2(elem->cmd_data.\n\t\t\t\t\t vlan_mac.target_obj, TRUE,\n\t\t\t\t\t CLASSIFY_RULE_OPCODE_MAC,\n\t\t\t\t\t &rule_entry->mac.header);\n\n\t\t/* Set a MAC itself */\n\t\tecore_set_fw_mac_addr(&rule_entry->mac.mac_msb,\n\t\t\t\t &rule_entry->mac.mac_mid,\n\t\t\t\t &rule_entry->mac.mac_lsb, mac);\n\t\trule_entry->mac.inner_mac =\n\t\t elem->cmd_data.vlan_mac.u.mac.is_inner_mac;\n\t}\n\n\t/* Set the ramrod data header */\n\tecore_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,\n\t\t\t\t\trule_cnt);\n}\n\n/**\n * ecore_vlan_mac_set_rdata_hdr_e1x - set a header in a single classify ramrod\n *\n * @sc:\t\tdevice handle\n * @o:\t\tqueue\n * @type:\n * @cam_offset:\toffset in cam memory\n * @hdr:\tpointer to a header to setup\n *\n * E1H\n */\nstatic void ecore_vlan_mac_set_rdata_hdr_e1x(struct ecore_vlan_mac_obj\n\t\t\t\t\t *o, int type, int cam_offset, struct mac_configuration_hdr\n\t\t\t\t\t *hdr)\n{\n\tstruct ecore_raw_obj *r = &o->raw;\n\n\thdr->length = 1;\n\thdr->offset = (uint8_t) cam_offset;\n\thdr->client_id = ECORE_CPU_TO_LE16(0xff);\n\thdr->echo = ECORE_CPU_TO_LE32((r->cid & ECORE_SWCID_MASK) |\n\t\t\t\t (type << ECORE_SWCID_SHIFT));\n}\n\nstatic void ecore_vlan_mac_set_cfg_entry_e1x(struct ecore_vlan_mac_obj\n\t\t\t\t\t *o, int add, int opcode,\n\t\t\t\t\t uint8_t * mac,\n\t\t\t\t\t uint16_t vlan_id, struct\n\t\t\t\t\t mac_configuration_entry\n\t\t\t\t\t *cfg_entry)\n{\n\tstruct ecore_raw_obj *r = &o->raw;\n\tuint32_t cl_bit_vec = (1 << r->cl_id);\n\n\tcfg_entry->clients_bit_vector = ECORE_CPU_TO_LE32(cl_bit_vec);\n\tcfg_entry->pf_id = r->func_id;\n\tcfg_entry->vlan_id = ECORE_CPU_TO_LE16(vlan_id);\n\n\tif (add) {\n\t\tECORE_SET_FLAG(cfg_entry->flags,\n\t\t\t MAC_CONFIGURATION_ENTRY_ACTION_TYPE,\n\t\t\t T_ETH_MAC_COMMAND_SET);\n\t\tECORE_SET_FLAG(cfg_entry->flags,\n\t\t\t MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE,\n\t\t\t opcode);\n\n\t\t/* Set a MAC in a ramrod data */\n\t\tecore_set_fw_mac_addr(&cfg_entry->msb_mac_addr,\n\t\t\t\t &cfg_entry->middle_mac_addr,\n\t\t\t\t &cfg_entry->lsb_mac_addr, mac);\n\t} else\n\t\tECORE_SET_FLAG(cfg_entry->flags,\n\t\t\t MAC_CONFIGURATION_ENTRY_ACTION_TYPE,\n\t\t\t T_ETH_MAC_COMMAND_INVALIDATE);\n}\n\nstatic void ecore_vlan_mac_set_rdata_e1x(struct bnx2x_softc *sc\n\t\t\t\t\t __rte_unused,\n\t\t\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t\t\t int type, int cam_offset,\n\t\t\t\t\t int add, uint8_t * mac,\n\t\t\t\t\t uint16_t vlan_id, int opcode,\n\t\t\t\t\t struct mac_configuration_cmd\n\t\t\t\t\t *config)\n{\n\tstruct mac_configuration_entry *cfg_entry = &config->config_table[0];\n\n\tecore_vlan_mac_set_rdata_hdr_e1x(o, type, cam_offset, &config->hdr);\n\tecore_vlan_mac_set_cfg_entry_e1x(o, add, opcode, mac, vlan_id,\n\t\t\t\t\t cfg_entry);\n\n\tECORE_MSG(\"%s MAC %02x:%02x:%02x:%02x:%02x:%02x CLID %d CAM offset %d\",\n\t\t (add ? \"setting\" : \"clearing\"),\n\t\t mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],\n\t\t o->raw.cl_id, cam_offset);\n}\n\n/**\n * ecore_set_one_mac_e1x - fill a single MAC rule ramrod data\n *\n * @sc:\t\tdevice handle\n * @o:\t\tecore_vlan_mac_obj\n * @elem:\tecore_exeq_elem\n * @rule_idx:\trule_idx\n * @cam_offset: cam_offset\n */\nstatic void ecore_set_one_mac_e1x(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t\t struct ecore_exeq_elem *elem,\n\t\t\t\t __rte_unused int rule_idx, int cam_offset)\n{\n\tstruct ecore_raw_obj *raw = &o->raw;\n\tstruct mac_configuration_cmd *config =\n\t (struct mac_configuration_cmd *)(raw->rdata);\n\t/* 57711 do not support MOVE command,\n\t * so it's either ADD or DEL\n\t */\n\tint add = (elem->cmd_data.vlan_mac.cmd == ECORE_VLAN_MAC_ADD) ?\n\t TRUE : FALSE;\n\n\t/* Reset the ramrod data buffer */\n\tECORE_MEMSET(config, 0, sizeof(*config));\n\n\tecore_vlan_mac_set_rdata_e1x(sc, o, raw->state,\n\t\t\t\t cam_offset, add,\n\t\t\t\t elem->cmd_data.vlan_mac.u.mac.mac, 0,\n\t\t\t\t ETH_VLAN_FILTER_ANY_VLAN, config);\n}\n\n/**\n * ecore_vlan_mac_restore - reconfigure next MAC/VLAN/VLAN-MAC element\n *\n * @sc:\t\tdevice handle\n * @p:\t\tcommand parameters\n * @ppos:\tpointer to the cookie\n *\n * reconfigure next MAC/VLAN/VLAN-MAC element from the\n * previously configured elements list.\n *\n * from command parameters only RAMROD_COMP_WAIT bit in ramrod_flags is\ttaken\n * into an account\n *\n * pointer to the cookie - that should be given back in the next call to make\n * function handle the next element. If *ppos is set to NULL it will restart the\n * iterator. If returned *ppos == NULL this means that the last element has been\n * handled.\n *\n */\nstatic int ecore_vlan_mac_restore(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_vlan_mac_ramrod_params *p,\n\t\t\t\t struct ecore_vlan_mac_registry_elem **ppos)\n{\n\tstruct ecore_vlan_mac_registry_elem *pos;\n\tstruct ecore_vlan_mac_obj *o = p->vlan_mac_obj;\n\n\t/* If list is empty - there is nothing to do here */\n\tif (ECORE_LIST_IS_EMPTY(&o->head)) {\n\t\t*ppos = NULL;\n\t\treturn 0;\n\t}\n\n\t/* make a step... */\n\tif (*ppos == NULL)\n\t\t*ppos = ECORE_LIST_FIRST_ENTRY(&o->head, struct\n\t\t\t\t\t ecore_vlan_mac_registry_elem,\n\t\t\t\t\t link);\n\telse\n\t\t*ppos = ECORE_LIST_NEXT(*ppos, link,\n\t\t\t\t\tstruct ecore_vlan_mac_registry_elem);\n\n\tpos = *ppos;\n\n\t/* If it's the last step - return NULL */\n\tif (ECORE_LIST_IS_LAST(&pos->link, &o->head))\n\t\t*ppos = NULL;\n\n\t/* Prepare a 'user_req' */\n\tECORE_MEMCPY(&p->user_req.u, &pos->u, sizeof(pos->u));\n\n\t/* Set the command */\n\tp->user_req.cmd = ECORE_VLAN_MAC_ADD;\n\n\t/* Set vlan_mac_flags */\n\tp->user_req.vlan_mac_flags = pos->vlan_mac_flags;\n\n\t/* Set a restore bit */\n\tECORE_SET_BIT_NA(RAMROD_RESTORE, &p->ramrod_flags);\n\n\treturn ecore_config_vlan_mac(sc, p);\n}\n\n/* ecore_exeq_get_mac/ecore_exeq_get_vlan/ecore_exeq_get_vlan_mac return a\n * pointer to an element with a specific criteria and NULL if such an element\n * hasn't been found.\n */\nstatic struct ecore_exeq_elem *ecore_exeq_get_mac(struct ecore_exe_queue_obj *o,\n\t\t\t\t\t\t struct ecore_exeq_elem *elem)\n{\n\tstruct ecore_exeq_elem *pos;\n\tstruct ecore_mac_ramrod_data *data = &elem->cmd_data.vlan_mac.u.mac;\n\n\t/* Check pending for execution commands */\n\tECORE_LIST_FOR_EACH_ENTRY(pos, &o->exe_queue, link,\n\t\t\t\t struct ecore_exeq_elem)\n\tif (!ECORE_MEMCMP(&pos->cmd_data.vlan_mac.u.mac, data,\n\t\t\t sizeof(*data)) &&\n\t (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))\n\t\treturn pos;\n\n\treturn NULL;\n}\n\n/**\n * ecore_validate_vlan_mac_add - check if an ADD command can be executed\n *\n * @sc:\t\tdevice handle\n * @qo:\t\tecore_qable_obj\n * @elem:\tecore_exeq_elem\n *\n * Checks that the requested configuration can be added. If yes and if\n * requested, consume CAM credit.\n *\n * The 'validate' is run after the 'optimize'.\n *\n */\nstatic int ecore_validate_vlan_mac_add(struct bnx2x_softc *sc,\n\t\t\t\t union ecore_qable_obj *qo,\n\t\t\t\t struct ecore_exeq_elem *elem)\n{\n\tstruct ecore_vlan_mac_obj *o = &qo->vlan_mac;\n\tstruct ecore_exe_queue_obj *exeq = &o->exe_queue;\n\tint rc;\n\n\t/* Check the registry */\n\trc = o->check_add(sc, o, &elem->cmd_data.vlan_mac.u);\n\tif (rc) {\n\t\tECORE_MSG\n\t\t (\"ADD command is not allowed considering current registry state.\");\n\t\treturn rc;\n\t}\n\n\t/* Check if there is a pending ADD command for this\n\t * MAC/VLAN/VLAN-MAC. Return an error if there is.\n\t */\n\tif (exeq->get(exeq, elem)) {\n\t\tECORE_MSG(\"There is a pending ADD command already\");\n\t\treturn ECORE_EXISTS;\n\t}\n\n\t/* Consume the credit if not requested not to */\n\tif (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT,\n\t\t\t &elem->cmd_data.vlan_mac.vlan_mac_flags) ||\n\t o->get_credit(o)))\n\t\treturn ECORE_INVAL;\n\n\treturn ECORE_SUCCESS;\n}\n\n/**\n * ecore_validate_vlan_mac_del - check if the DEL command can be executed\n *\n * @sc:\t\tdevice handle\n * @qo:\t\tquable object to check\n * @elem:\telement that needs to be deleted\n *\n * Checks that the requested configuration can be deleted. If yes and if\n * requested, returns a CAM credit.\n *\n * The 'validate' is run after the 'optimize'.\n */\nstatic int ecore_validate_vlan_mac_del(struct bnx2x_softc *sc,\n\t\t\t\t union ecore_qable_obj *qo,\n\t\t\t\t struct ecore_exeq_elem *elem)\n{\n\tstruct ecore_vlan_mac_obj *o = &qo->vlan_mac;\n\tstruct ecore_vlan_mac_registry_elem *pos;\n\tstruct ecore_exe_queue_obj *exeq = &o->exe_queue;\n\tstruct ecore_exeq_elem query_elem;\n\n\t/* If this classification can not be deleted (doesn't exist)\n\t * - return a ECORE_EXIST.\n\t */\n\tpos = o->check_del(sc, o, &elem->cmd_data.vlan_mac.u);\n\tif (!pos) {\n\t\tECORE_MSG\n\t\t (\"DEL command is not allowed considering current registry state\");\n\t\treturn ECORE_EXISTS;\n\t}\n\n\t/* Check if there are pending DEL or MOVE commands for this\n\t * MAC/VLAN/VLAN-MAC. Return an error if so.\n\t */\n\tECORE_MEMCPY(&query_elem, elem, sizeof(query_elem));\n\n\t/* Check for MOVE commands */\n\tquery_elem.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_MOVE;\n\tif (exeq->get(exeq, &query_elem)) {\n\t\tPMD_DRV_LOG(ERR, \"There is a pending MOVE command already\");\n\t\treturn ECORE_INVAL;\n\t}\n\n\t/* Check for DEL commands */\n\tif (exeq->get(exeq, elem)) {\n\t\tECORE_MSG(\"There is a pending DEL command already\");\n\t\treturn ECORE_EXISTS;\n\t}\n\n\t/* Return the credit to the credit pool if not requested not to */\n\tif (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT,\n\t\t\t &elem->cmd_data.vlan_mac.vlan_mac_flags) ||\n\t o->put_credit(o))) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to return a credit\");\n\t\treturn ECORE_INVAL;\n\t}\n\n\treturn ECORE_SUCCESS;\n}\n\n/**\n * ecore_validate_vlan_mac_move - check if the MOVE command can be executed\n *\n * @sc:\t\tdevice handle\n * @qo:\t\tquable object to check (source)\n * @elem:\telement that needs to be moved\n *\n * Checks that the requested configuration can be moved. If yes and if\n * requested, returns a CAM credit.\n *\n * The 'validate' is run after the 'optimize'.\n */\nstatic int ecore_validate_vlan_mac_move(struct bnx2x_softc *sc,\n\t\t\t\t\tunion ecore_qable_obj *qo,\n\t\t\t\t\tstruct ecore_exeq_elem *elem)\n{\n\tstruct ecore_vlan_mac_obj *src_o = &qo->vlan_mac;\n\tstruct ecore_vlan_mac_obj *dest_o = elem->cmd_data.vlan_mac.target_obj;\n\tstruct ecore_exeq_elem query_elem;\n\tstruct ecore_exe_queue_obj *src_exeq = &src_o->exe_queue;\n\tstruct ecore_exe_queue_obj *dest_exeq = &dest_o->exe_queue;\n\n\t/* Check if we can perform this operation based on the current registry\n\t * state.\n\t */\n\tif (!src_o->check_move(sc, src_o, dest_o, &elem->cmd_data.vlan_mac.u)) {\n\t\tECORE_MSG\n\t\t (\"MOVE command is not allowed considering current registry state\");\n\t\treturn ECORE_INVAL;\n\t}\n\n\t/* Check if there is an already pending DEL or MOVE command for the\n\t * source object or ADD command for a destination object. Return an\n\t * error if so.\n\t */\n\tECORE_MEMCPY(&query_elem, elem, sizeof(query_elem));\n\n\t/* Check DEL on source */\n\tquery_elem.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_DEL;\n\tif (src_exeq->get(src_exeq, &query_elem)) {\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"There is a pending DEL command on the source queue already\");\n\t\treturn ECORE_INVAL;\n\t}\n\n\t/* Check MOVE on source */\n\tif (src_exeq->get(src_exeq, elem)) {\n\t\tECORE_MSG(\"There is a pending MOVE command already\");\n\t\treturn ECORE_EXISTS;\n\t}\n\n\t/* Check ADD on destination */\n\tquery_elem.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_ADD;\n\tif (dest_exeq->get(dest_exeq, &query_elem)) {\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"There is a pending ADD command on the destination queue already\");\n\t\treturn ECORE_INVAL;\n\t}\n\n\t/* Consume the credit if not requested not to */\n\tif (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT_DEST,\n\t\t\t &elem->cmd_data.vlan_mac.vlan_mac_flags) ||\n\t dest_o->get_credit(dest_o)))\n\t\treturn ECORE_INVAL;\n\n\tif (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT,\n\t\t\t &elem->cmd_data.vlan_mac.vlan_mac_flags) ||\n\t src_o->put_credit(src_o))) {\n\t\t/* return the credit taken from dest... */\n\t\tdest_o->put_credit(dest_o);\n\t\treturn ECORE_INVAL;\n\t}\n\n\treturn ECORE_SUCCESS;\n}\n\nstatic int ecore_validate_vlan_mac(struct bnx2x_softc *sc,\n\t\t\t\t union ecore_qable_obj *qo,\n\t\t\t\t struct ecore_exeq_elem *elem)\n{\n\tswitch (elem->cmd_data.vlan_mac.cmd) {\n\tcase ECORE_VLAN_MAC_ADD:\n\t\treturn ecore_validate_vlan_mac_add(sc, qo, elem);\n\tcase ECORE_VLAN_MAC_DEL:\n\t\treturn ecore_validate_vlan_mac_del(sc, qo, elem);\n\tcase ECORE_VLAN_MAC_MOVE:\n\t\treturn ecore_validate_vlan_mac_move(sc, qo, elem);\n\tdefault:\n\t\treturn ECORE_INVAL;\n\t}\n}\n\nstatic int ecore_remove_vlan_mac(__rte_unused struct bnx2x_softc *sc,\n\t\t\t\t union ecore_qable_obj *qo,\n\t\t\t\t struct ecore_exeq_elem *elem)\n{\n\tint rc = 0;\n\n\t/* If consumption wasn't required, nothing to do */\n\tif (ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT,\n\t\t\t &elem->cmd_data.vlan_mac.vlan_mac_flags))\n\t\treturn ECORE_SUCCESS;\n\n\tswitch (elem->cmd_data.vlan_mac.cmd) {\n\tcase ECORE_VLAN_MAC_ADD:\n\tcase ECORE_VLAN_MAC_MOVE:\n\t\trc = qo->vlan_mac.put_credit(&qo->vlan_mac);\n\t\tbreak;\n\tcase ECORE_VLAN_MAC_DEL:\n\t\trc = qo->vlan_mac.get_credit(&qo->vlan_mac);\n\t\tbreak;\n\tdefault:\n\t\treturn ECORE_INVAL;\n\t}\n\n\tif (rc != TRUE)\n\t\treturn ECORE_INVAL;\n\n\treturn ECORE_SUCCESS;\n}\n\n/**\n * ecore_wait_vlan_mac - passively wait for 5 seconds until all work completes.\n *\n * @sc:\t\tdevice handle\n * @o:\t\tecore_vlan_mac_obj\n *\n */\nstatic int ecore_wait_vlan_mac(struct bnx2x_softc *sc,\n\t\t\t struct ecore_vlan_mac_obj *o)\n{\n\tint cnt = 5000, rc;\n\tstruct ecore_exe_queue_obj *exeq = &o->exe_queue;\n\tstruct ecore_raw_obj *raw = &o->raw;\n\n\twhile (cnt--) {\n\t\t/* Wait for the current command to complete */\n\t\trc = raw->wait_comp(sc, raw);\n\t\tif (rc)\n\t\t\treturn rc;\n\n\t\t/* Wait until there are no pending commands */\n\t\tif (!ecore_exe_queue_empty(exeq))\n\t\t\tECORE_WAIT(sc, 1000);\n\t\telse\n\t\t\treturn ECORE_SUCCESS;\n\t}\n\n\treturn ECORE_TIMEOUT;\n}\n\nstatic int __ecore_vlan_mac_execute_step(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t\t\t unsigned long *ramrod_flags)\n{\n\tint rc = ECORE_SUCCESS;\n\n\tECORE_SPIN_LOCK_BH(&o->exe_queue.lock);\n\n\tECORE_MSG(\"vlan_mac_execute_step - trying to take writer lock\");\n\trc = __ecore_vlan_mac_h_write_trylock(sc, o);\n\n\tif (rc != ECORE_SUCCESS) {\n\t\t__ecore_vlan_mac_h_pend(sc, o, *ramrod_flags);\n\n\t\t/** Calling function should not diffrentiate between this case\n\t\t * and the case in which there is already a pending ramrod\n\t\t */\n\t\trc = ECORE_PENDING;\n\t} else {\n\t\trc = ecore_exe_queue_step(sc, &o->exe_queue, ramrod_flags);\n\t}\n\tECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock);\n\n\treturn rc;\n}\n\n/**\n * ecore_complete_vlan_mac - complete one VLAN-MAC ramrod\n *\n * @sc:\t\tdevice handle\n * @o:\t\tecore_vlan_mac_obj\n * @cqe:\n * @cont:\tif TRUE schedule next execution chunk\n *\n */\nstatic int ecore_complete_vlan_mac(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t\t union event_ring_elem *cqe,\n\t\t\t\t unsigned long *ramrod_flags)\n{\n\tstruct ecore_raw_obj *r = &o->raw;\n\tint rc;\n\n\t/* Reset pending list */\n\tecore_exe_queue_reset_pending(sc, &o->exe_queue);\n\n\t/* Clear pending */\n\tr->clear_pending(r);\n\n\t/* If ramrod failed this is most likely a SW bug */\n\tif (cqe->message.error)\n\t\treturn ECORE_INVAL;\n\n\t/* Run the next bulk of pending commands if requested */\n\tif (ECORE_TEST_BIT(RAMROD_CONT, ramrod_flags)) {\n\t\trc = __ecore_vlan_mac_execute_step(sc, o, ramrod_flags);\n\t\tif (rc < 0)\n\t\t\treturn rc;\n\t}\n\n\t/* If there is more work to do return PENDING */\n\tif (!ecore_exe_queue_empty(&o->exe_queue))\n\t\treturn ECORE_PENDING;\n\n\treturn ECORE_SUCCESS;\n}\n\n/**\n * ecore_optimize_vlan_mac - optimize ADD and DEL commands.\n *\n * @sc:\t\tdevice handle\n * @o:\t\tecore_qable_obj\n * @elem:\tecore_exeq_elem\n */\nstatic int ecore_optimize_vlan_mac(struct bnx2x_softc *sc,\n\t\t\t\t union ecore_qable_obj *qo,\n\t\t\t\t struct ecore_exeq_elem *elem)\n{\n\tstruct ecore_exeq_elem query, *pos;\n\tstruct ecore_vlan_mac_obj *o = &qo->vlan_mac;\n\tstruct ecore_exe_queue_obj *exeq = &o->exe_queue;\n\n\tECORE_MEMCPY(&query, elem, sizeof(query));\n\n\tswitch (elem->cmd_data.vlan_mac.cmd) {\n\tcase ECORE_VLAN_MAC_ADD:\n\t\tquery.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_DEL;\n\t\tbreak;\n\tcase ECORE_VLAN_MAC_DEL:\n\t\tquery.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_ADD;\n\t\tbreak;\n\tdefault:\n\t\t/* Don't handle anything other than ADD or DEL */\n\t\treturn 0;\n\t}\n\n\t/* If we found the appropriate element - delete it */\n\tpos = exeq->get(exeq, &query);\n\tif (pos) {\n\n\t\t/* Return the credit of the optimized command */\n\t\tif (!ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT,\n\t\t\t\t &pos->cmd_data.vlan_mac.vlan_mac_flags)) {\n\t\t\tif ((query.cmd_data.vlan_mac.cmd ==\n\t\t\t ECORE_VLAN_MAC_ADD) && !o->put_credit(o)) {\n\t\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\t \"Failed to return the credit for the optimized ADD command\");\n\t\t\t\treturn ECORE_INVAL;\n\t\t\t} else if (!o->get_credit(o)) {\t/* VLAN_MAC_DEL */\n\t\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\t \"Failed to recover the credit from the optimized DEL command\");\n\t\t\t\treturn ECORE_INVAL;\n\t\t\t}\n\t\t}\n\n\t\tECORE_MSG(\"Optimizing %s command\",\n\t\t\t (elem->cmd_data.vlan_mac.cmd == ECORE_VLAN_MAC_ADD) ?\n\t\t\t \"ADD\" : \"DEL\");\n\n\t\tECORE_LIST_REMOVE_ENTRY(&pos->link, &exeq->exe_queue);\n\t\tecore_exe_queue_free_elem(sc, pos);\n\t\treturn 1;\n\t}\n\n\treturn 0;\n}\n\n/**\n * ecore_vlan_mac_get_registry_elem - prepare a registry element\n *\n * @sc:\t device handle\n * @o:\n * @elem:\n * @restore:\n * @re:\n *\n * prepare a registry element according to the current command request.\n */\nstatic int ecore_vlan_mac_get_registry_elem(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t\t\t struct ecore_exeq_elem *elem,\n\t\t\t\t\t int restore, struct\n\t\t\t\t\t ecore_vlan_mac_registry_elem\n\t\t\t\t\t **re)\n{\n\tenum ecore_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;\n\tstruct ecore_vlan_mac_registry_elem *reg_elem;\n\n\t/* Allocate a new registry element if needed. */\n\tif (!restore &&\n\t ((cmd == ECORE_VLAN_MAC_ADD) || (cmd == ECORE_VLAN_MAC_MOVE))) {\n\t\treg_elem = ECORE_ZALLOC(sizeof(*reg_elem), GFP_ATOMIC, sc);\n\t\tif (!reg_elem)\n\t\t\treturn ECORE_NOMEM;\n\n\t\t/* Get a new CAM offset */\n\t\tif (!o->get_cam_offset(o, ®_elem->cam_offset)) {\n\t\t\t/* This shall never happen, because we have checked the\n\t\t\t * CAM availability in the 'validate'.\n\t\t\t */\n\t\t\tECORE_DBG_BREAK_IF(1);\n\t\t\tECORE_FREE(sc, reg_elem, sizeof(*reg_elem));\n\t\t\treturn ECORE_INVAL;\n\t\t}\n\n\t\tECORE_MSG(\"Got cam offset %d\", reg_elem->cam_offset);\n\n\t\t/* Set a VLAN-MAC data */\n\t\tECORE_MEMCPY(®_elem->u, &elem->cmd_data.vlan_mac.u,\n\t\t\t sizeof(reg_elem->u));\n\n\t\t/* Copy the flags (needed for DEL and RESTORE flows) */\n\t\treg_elem->vlan_mac_flags =\n\t\t elem->cmd_data.vlan_mac.vlan_mac_flags;\n\t} else\t\t\t/* DEL, RESTORE */\n\t\treg_elem = o->check_del(sc, o, &elem->cmd_data.vlan_mac.u);\n\n\t*re = reg_elem;\n\treturn ECORE_SUCCESS;\n}\n\n/**\n * ecore_execute_vlan_mac - execute vlan mac command\n *\n * @sc:\t\t\tdevice handle\n * @qo:\n * @exe_chunk:\n * @ramrod_flags:\n *\n * go and send a ramrod!\n */\nstatic int ecore_execute_vlan_mac(struct bnx2x_softc *sc,\n\t\t\t\t union ecore_qable_obj *qo,\n\t\t\t\t ecore_list_t * exe_chunk,\n\t\t\t\t unsigned long *ramrod_flags)\n{\n\tstruct ecore_exeq_elem *elem;\n\tstruct ecore_vlan_mac_obj *o = &qo->vlan_mac, *cam_obj;\n\tstruct ecore_raw_obj *r = &o->raw;\n\tint rc, idx = 0;\n\tint restore = ECORE_TEST_BIT(RAMROD_RESTORE, ramrod_flags);\n\tint drv_only = ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ramrod_flags);\n\tstruct ecore_vlan_mac_registry_elem *reg_elem;\n\tenum ecore_vlan_mac_cmd cmd;\n\n\t/* If DRIVER_ONLY execution is requested, cleanup a registry\n\t * and exit. Otherwise send a ramrod to FW.\n\t */\n\tif (!drv_only) {\n\n\t\t/* Set pending */\n\t\tr->set_pending(r);\n\n\t\t/* Fill the ramrod data */\n\t\tECORE_LIST_FOR_EACH_ENTRY(elem, exe_chunk, link,\n\t\t\t\t\t struct ecore_exeq_elem) {\n\t\t\tcmd = elem->cmd_data.vlan_mac.cmd;\n\t\t\t/* We will add to the target object in MOVE command, so\n\t\t\t * change the object for a CAM search.\n\t\t\t */\n\t\t\tif (cmd == ECORE_VLAN_MAC_MOVE)\n\t\t\t\tcam_obj = elem->cmd_data.vlan_mac.target_obj;\n\t\t\telse\n\t\t\t\tcam_obj = o;\n\n\t\t\trc = ecore_vlan_mac_get_registry_elem(sc, cam_obj,\n\t\t\t\t\t\t\t elem, restore,\n\t\t\t\t\t\t\t ®_elem);\n\t\t\tif (rc)\n\t\t\t\tgoto error_exit;\n\n\t\t\tECORE_DBG_BREAK_IF(!reg_elem);\n\n\t\t\t/* Push a new entry into the registry */\n\t\t\tif (!restore &&\n\t\t\t ((cmd == ECORE_VLAN_MAC_ADD) ||\n\t\t\t (cmd == ECORE_VLAN_MAC_MOVE)))\n\t\t\t\tECORE_LIST_PUSH_HEAD(®_elem->link,\n\t\t\t\t\t\t &cam_obj->head);\n\n\t\t\t/* Configure a single command in a ramrod data buffer */\n\t\t\to->set_one_rule(sc, o, elem, idx, reg_elem->cam_offset);\n\n\t\t\t/* MOVE command consumes 2 entries in the ramrod data */\n\t\t\tif (cmd == ECORE_VLAN_MAC_MOVE)\n\t\t\t\tidx += 2;\n\t\t\telse\n\t\t\t\tidx++;\n\t\t}\n\n\t\t/*\n\t\t * No need for an explicit memory barrier here as long we would\n\t\t * need to ensure the ordering of writing to the SPQ element\n\t\t * and updating of the SPQ producer which involves a memory\n\t\t * read and we will have to put a full memory barrier there\n\t\t * (inside ecore_sp_post()).\n\t\t */\n\n\t\trc = ecore_sp_post(sc, o->ramrod_cmd, r->cid,\n\t\t\t\t r->rdata_mapping, ETH_CONNECTION_TYPE);\n\t\tif (rc)\n\t\t\tgoto error_exit;\n\t}\n\n\t/* Now, when we are done with the ramrod - clean up the registry */\n\tECORE_LIST_FOR_EACH_ENTRY(elem, exe_chunk, link, struct ecore_exeq_elem) {\n\t\tcmd = elem->cmd_data.vlan_mac.cmd;\n\t\tif ((cmd == ECORE_VLAN_MAC_DEL) || (cmd == ECORE_VLAN_MAC_MOVE)) {\n\t\t\treg_elem = o->check_del(sc, o,\n\t\t\t\t\t\t&elem->cmd_data.vlan_mac.u);\n\n\t\t\tECORE_DBG_BREAK_IF(!reg_elem);\n\n\t\t\to->put_cam_offset(o, reg_elem->cam_offset);\n\t\t\tECORE_LIST_REMOVE_ENTRY(®_elem->link, &o->head);\n\t\t\tECORE_FREE(sc, reg_elem, sizeof(*reg_elem));\n\t\t}\n\t}\n\n\tif (!drv_only)\n\t\treturn ECORE_PENDING;\n\telse\n\t\treturn ECORE_SUCCESS;\n\nerror_exit:\n\tr->clear_pending(r);\n\n\t/* Cleanup a registry in case of a failure */\n\tECORE_LIST_FOR_EACH_ENTRY(elem, exe_chunk, link, struct ecore_exeq_elem) {\n\t\tcmd = elem->cmd_data.vlan_mac.cmd;\n\n\t\tif (cmd == ECORE_VLAN_MAC_MOVE)\n\t\t\tcam_obj = elem->cmd_data.vlan_mac.target_obj;\n\t\telse\n\t\t\tcam_obj = o;\n\n\t\t/* Delete all newly added above entries */\n\t\tif (!restore &&\n\t\t ((cmd == ECORE_VLAN_MAC_ADD) ||\n\t\t (cmd == ECORE_VLAN_MAC_MOVE))) {\n\t\t\treg_elem = o->check_del(sc, cam_obj,\n\t\t\t\t\t\t&elem->cmd_data.vlan_mac.u);\n\t\t\tif (reg_elem) {\n\t\t\t\tECORE_LIST_REMOVE_ENTRY(®_elem->link,\n\t\t\t\t\t\t\t&cam_obj->head);\n\t\t\t\tECORE_FREE(sc, reg_elem, sizeof(*reg_elem));\n\t\t\t}\n\t\t}\n\t}\n\n\treturn rc;\n}\n\nstatic int ecore_vlan_mac_push_new_cmd(struct bnx2x_softc *sc, struct\n\t\t\t\t ecore_vlan_mac_ramrod_params *p)\n{\n\tstruct ecore_exeq_elem *elem;\n\tstruct ecore_vlan_mac_obj *o = p->vlan_mac_obj;\n\tint restore = ECORE_TEST_BIT(RAMROD_RESTORE, &p->ramrod_flags);\n\n\t/* Allocate the execution queue element */\n\telem = ecore_exe_queue_alloc_elem(sc);\n\tif (!elem)\n\t\treturn ECORE_NOMEM;\n\n\t/* Set the command 'length' */\n\tswitch (p->user_req.cmd) {\n\tcase ECORE_VLAN_MAC_MOVE:\n\t\telem->cmd_len = 2;\n\t\tbreak;\n\tdefault:\n\t\telem->cmd_len = 1;\n\t}\n\n\t/* Fill the object specific info */\n\tECORE_MEMCPY(&elem->cmd_data.vlan_mac, &p->user_req,\n\t\t sizeof(p->user_req));\n\n\t/* Try to add a new command to the pending list */\n\treturn ecore_exe_queue_add(sc, &o->exe_queue, elem, restore);\n}\n\n/**\n * ecore_config_vlan_mac - configure VLAN/MAC/VLAN_MAC filtering rules.\n *\n * @sc:\t device handle\n * @p:\n *\n */\nint ecore_config_vlan_mac(struct bnx2x_softc *sc,\n\t\t\t struct ecore_vlan_mac_ramrod_params *p)\n{\n\tint rc = ECORE_SUCCESS;\n\tstruct ecore_vlan_mac_obj *o = p->vlan_mac_obj;\n\tunsigned long *ramrod_flags = &p->ramrod_flags;\n\tint cont = ECORE_TEST_BIT(RAMROD_CONT, ramrod_flags);\n\tstruct ecore_raw_obj *raw = &o->raw;\n\n\t/*\n\t * Add new elements to the execution list for commands that require it.\n\t */\n\tif (!cont) {\n\t\trc = ecore_vlan_mac_push_new_cmd(sc, p);\n\t\tif (rc)\n\t\t\treturn rc;\n\t}\n\n\t/* If nothing will be executed further in this iteration we want to\n\t * return PENDING if there are pending commands\n\t */\n\tif (!ecore_exe_queue_empty(&o->exe_queue))\n\t\trc = ECORE_PENDING;\n\n\tif (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {\n\t\tECORE_MSG\n\t\t (\"RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\");\n\t\traw->clear_pending(raw);\n\t}\n\n\t/* Execute commands if required */\n\tif (cont || ECORE_TEST_BIT(RAMROD_EXEC, ramrod_flags) ||\n\t ECORE_TEST_BIT(RAMROD_COMP_WAIT, ramrod_flags)) {\n\t\trc = __ecore_vlan_mac_execute_step(sc, p->vlan_mac_obj,\n\t\t\t\t\t\t &p->ramrod_flags);\n\t\tif (rc < 0)\n\t\t\treturn rc;\n\t}\n\n\t/* RAMROD_COMP_WAIT is a superset of RAMROD_EXEC. If it was set\n\t * then user want to wait until the last command is done.\n\t */\n\tif (ECORE_TEST_BIT(RAMROD_COMP_WAIT, &p->ramrod_flags)) {\n\t\t/* Wait maximum for the current exe_queue length iterations plus\n\t\t * one (for the current pending command).\n\t\t */\n\t\tint max_iterations = ecore_exe_queue_length(&o->exe_queue) + 1;\n\n\t\twhile (!ecore_exe_queue_empty(&o->exe_queue) &&\n\t\t max_iterations--) {\n\n\t\t\t/* Wait for the current command to complete */\n\t\t\trc = raw->wait_comp(sc, raw);\n\t\t\tif (rc)\n\t\t\t\treturn rc;\n\n\t\t\t/* Make a next step */\n\t\t\trc = __ecore_vlan_mac_execute_step(sc,\n\t\t\t\t\t\t\t p->vlan_mac_obj,\n\t\t\t\t\t\t\t &p->ramrod_flags);\n\t\t\tif (rc < 0)\n\t\t\t\treturn rc;\n\t\t}\n\n\t\treturn ECORE_SUCCESS;\n\t}\n\n\treturn rc;\n}\n\n/**\n * ecore_vlan_mac_del_all - delete elements with given vlan_mac_flags spec\n *\n * @sc:\t\t\tdevice handle\n * @o:\n * @vlan_mac_flags:\n * @ramrod_flags:\texecution flags to be used for this deletion\n *\n * if the last operation has completed successfully and there are no\n * more elements left, positive value if the last operation has completed\n * successfully and there are more previously configured elements, negative\n * value is current operation has failed.\n */\nstatic int ecore_vlan_mac_del_all(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t\t unsigned long *vlan_mac_flags,\n\t\t\t\t unsigned long *ramrod_flags)\n{\n\tstruct ecore_vlan_mac_registry_elem *pos = NULL;\n\tint rc = 0, read_lock;\n\tstruct ecore_vlan_mac_ramrod_params p;\n\tstruct ecore_exe_queue_obj *exeq = &o->exe_queue;\n\tstruct ecore_exeq_elem *exeq_pos, *exeq_pos_n;\n\n\t/* Clear pending commands first */\n\n\tECORE_SPIN_LOCK_BH(&exeq->lock);\n\n\tECORE_LIST_FOR_EACH_ENTRY_SAFE(exeq_pos, exeq_pos_n,\n\t\t\t\t &exeq->exe_queue, link,\n\t\t\t\t struct ecore_exeq_elem) {\n\t\tif (exeq_pos->cmd_data.vlan_mac.vlan_mac_flags ==\n\t\t *vlan_mac_flags) {\n\t\t\trc = exeq->remove(sc, exeq->owner, exeq_pos);\n\t\t\tif (rc) {\n\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to remove command\");\n\t\t\t\tECORE_SPIN_UNLOCK_BH(&exeq->lock);\n\t\t\t\treturn rc;\n\t\t\t}\n\t\t\tECORE_LIST_REMOVE_ENTRY(&exeq_pos->link,\n\t\t\t\t\t\t&exeq->exe_queue);\n\t\t\tecore_exe_queue_free_elem(sc, exeq_pos);\n\t\t}\n\t}\n\n\tECORE_SPIN_UNLOCK_BH(&exeq->lock);\n\n\t/* Prepare a command request */\n\tECORE_MEMSET(&p, 0, sizeof(p));\n\tp.vlan_mac_obj = o;\n\tp.ramrod_flags = *ramrod_flags;\n\tp.user_req.cmd = ECORE_VLAN_MAC_DEL;\n\n\t/* Add all but the last VLAN-MAC to the execution queue without actually\n\t * execution anything.\n\t */\n\tECORE_CLEAR_BIT_NA(RAMROD_COMP_WAIT, &p.ramrod_flags);\n\tECORE_CLEAR_BIT_NA(RAMROD_EXEC, &p.ramrod_flags);\n\tECORE_CLEAR_BIT_NA(RAMROD_CONT, &p.ramrod_flags);\n\n\tECORE_MSG(\"vlan_mac_del_all -- taking vlan_mac_lock (reader)\");\n\tread_lock = ecore_vlan_mac_h_read_lock(sc, o);\n\tif (read_lock != ECORE_SUCCESS)\n\t\treturn read_lock;\n\n\tECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link,\n\t\t\t\t struct ecore_vlan_mac_registry_elem) {\n\t\tif (pos->vlan_mac_flags == *vlan_mac_flags) {\n\t\t\tp.user_req.vlan_mac_flags = pos->vlan_mac_flags;\n\t\t\tECORE_MEMCPY(&p.user_req.u, &pos->u, sizeof(pos->u));\n\t\t\trc = ecore_config_vlan_mac(sc, &p);\n\t\t\tif (rc < 0) {\n\t\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t\t \"Failed to add a new DEL command\");\n\t\t\t\tecore_vlan_mac_h_read_unlock(sc, o);\n\t\t\t\treturn rc;\n\t\t\t}\n\t\t}\n\t}\n\n\tECORE_MSG(\"vlan_mac_del_all -- releasing vlan_mac_lock (reader)\");\n\tecore_vlan_mac_h_read_unlock(sc, o);\n\n\tp.ramrod_flags = *ramrod_flags;\n\tECORE_SET_BIT_NA(RAMROD_CONT, &p.ramrod_flags);\n\n\treturn ecore_config_vlan_mac(sc, &p);\n}\n\nstatic void ecore_init_raw_obj(struct ecore_raw_obj *raw, uint8_t cl_id,\n\t\t\t uint32_t cid, uint8_t func_id,\n\t\t\t void *rdata,\n\t\t\t ecore_dma_addr_t rdata_mapping, int state,\n\t\t\t unsigned long *pstate, ecore_obj_type type)\n{\n\traw->func_id = func_id;\n\traw->cid = cid;\n\traw->cl_id = cl_id;\n\traw->rdata = rdata;\n\traw->rdata_mapping = rdata_mapping;\n\traw->state = state;\n\traw->pstate = pstate;\n\traw->obj_type = type;\n\traw->check_pending = ecore_raw_check_pending;\n\traw->clear_pending = ecore_raw_clear_pending;\n\traw->set_pending = ecore_raw_set_pending;\n\traw->wait_comp = ecore_raw_wait;\n}\n\nstatic void ecore_init_vlan_mac_common(struct ecore_vlan_mac_obj *o,\n\t\t\t\t uint8_t cl_id, uint32_t cid,\n\t\t\t\t uint8_t func_id, void *rdata,\n\t\t\t\t ecore_dma_addr_t rdata_mapping,\n\t\t\t\t int state, unsigned long *pstate,\n\t\t\t\t ecore_obj_type type,\n\t\t\t\t struct ecore_credit_pool_obj\n\t\t\t\t *macs_pool, struct ecore_credit_pool_obj\n\t\t\t\t *vlans_pool)\n{\n\tECORE_LIST_INIT(&o->head);\n\to->head_reader = 0;\n\to->head_exe_request = FALSE;\n\to->saved_ramrod_flags = 0;\n\n\to->macs_pool = macs_pool;\n\to->vlans_pool = vlans_pool;\n\n\to->delete_all = ecore_vlan_mac_del_all;\n\to->restore = ecore_vlan_mac_restore;\n\to->complete = ecore_complete_vlan_mac;\n\to->wait = ecore_wait_vlan_mac;\n\n\tecore_init_raw_obj(&o->raw, cl_id, cid, func_id, rdata, rdata_mapping,\n\t\t\t state, pstate, type);\n}\n\nvoid ecore_init_mac_obj(struct bnx2x_softc *sc,\n\t\t\tstruct ecore_vlan_mac_obj *mac_obj,\n\t\t\tuint8_t cl_id, uint32_t cid, uint8_t func_id,\n\t\t\tvoid *rdata, ecore_dma_addr_t rdata_mapping, int state,\n\t\t\tunsigned long *pstate, ecore_obj_type type,\n\t\t\tstruct ecore_credit_pool_obj *macs_pool)\n{\n\tunion ecore_qable_obj *qable_obj = (union ecore_qable_obj *)mac_obj;\n\n\tecore_init_vlan_mac_common(mac_obj, cl_id, cid, func_id, rdata,\n\t\t\t\t rdata_mapping, state, pstate, type,\n\t\t\t\t macs_pool, NULL);\n\n\t/* CAM credit pool handling */\n\tmac_obj->get_credit = ecore_get_credit_mac;\n\tmac_obj->put_credit = ecore_put_credit_mac;\n\tmac_obj->get_cam_offset = ecore_get_cam_offset_mac;\n\tmac_obj->put_cam_offset = ecore_put_cam_offset_mac;\n\n\tif (CHIP_IS_E1x(sc)) {\n\t\tmac_obj->set_one_rule = ecore_set_one_mac_e1x;\n\t\tmac_obj->check_del = ecore_check_mac_del;\n\t\tmac_obj->check_add = ecore_check_mac_add;\n\t\tmac_obj->check_move = ecore_check_move_always_err;\n\t\tmac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC;\n\n\t\t/* Exe Queue */\n\t\tecore_exe_queue_init(sc,\n\t\t\t\t &mac_obj->exe_queue, 1, qable_obj,\n\t\t\t\t ecore_validate_vlan_mac,\n\t\t\t\t ecore_remove_vlan_mac,\n\t\t\t\t ecore_optimize_vlan_mac,\n\t\t\t\t ecore_execute_vlan_mac,\n\t\t\t\t ecore_exeq_get_mac);\n\t} else {\n\t\tmac_obj->set_one_rule = ecore_set_one_mac_e2;\n\t\tmac_obj->check_del = ecore_check_mac_del;\n\t\tmac_obj->check_add = ecore_check_mac_add;\n\t\tmac_obj->check_move = ecore_check_move;\n\t\tmac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;\n\t\tmac_obj->get_n_elements = ecore_get_n_elements;\n\n\t\t/* Exe Queue */\n\t\tecore_exe_queue_init(sc,\n\t\t\t\t &mac_obj->exe_queue, CLASSIFY_RULES_COUNT,\n\t\t\t\t qable_obj, ecore_validate_vlan_mac,\n\t\t\t\t ecore_remove_vlan_mac,\n\t\t\t\t ecore_optimize_vlan_mac,\n\t\t\t\t ecore_execute_vlan_mac,\n\t\t\t\t ecore_exeq_get_mac);\n\t}\n}\n\n/* RX_MODE verbs: DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */\nstatic void __storm_memset_mac_filters(struct bnx2x_softc *sc, struct\n\t\t\t\t tstorm_eth_mac_filter_config\n\t\t\t\t *mac_filters, uint16_t pf_id)\n{\n\tsize_t size = sizeof(struct tstorm_eth_mac_filter_config);\n\n\tuint32_t addr = BAR_TSTRORM_INTMEM +\n\t TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id);\n\n\tecore_storm_memset_struct(sc, addr, size, (uint32_t *) mac_filters);\n}\n\nstatic int ecore_set_rx_mode_e1x(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_rx_mode_ramrod_params *p)\n{\n\t/* update the sc MAC filter structure */\n\tuint32_t mask = (1 << p->cl_id);\n\n\tstruct tstorm_eth_mac_filter_config *mac_filters =\n\t (struct tstorm_eth_mac_filter_config *)p->rdata;\n\n\t/* initial setting is drop-all */\n\tuint8_t drop_all_ucast = 1, drop_all_mcast = 1;\n\tuint8_t accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;\n\tuint8_t unmatched_unicast = 0;\n\n\t/* In e1x there we only take into account rx accept flag since tx switching\n\t * isn't enabled. */\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_UNICAST, &p->rx_accept_flags))\n\t\t/* accept matched ucast */\n\t\tdrop_all_ucast = 0;\n\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_MULTICAST, &p->rx_accept_flags))\n\t\t/* accept matched mcast */\n\t\tdrop_all_mcast = 0;\n\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_ALL_UNICAST, &p->rx_accept_flags)) {\n\t\t/* accept all mcast */\n\t\tdrop_all_ucast = 0;\n\t\taccp_all_ucast = 1;\n\t}\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_ALL_MULTICAST, &p->rx_accept_flags)) {\n\t\t/* accept all mcast */\n\t\tdrop_all_mcast = 0;\n\t\taccp_all_mcast = 1;\n\t}\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_BROADCAST, &p->rx_accept_flags))\n\t\t/* accept (all) bcast */\n\t\taccp_all_bcast = 1;\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_UNMATCHED, &p->rx_accept_flags))\n\t\t/* accept unmatched unicasts */\n\t\tunmatched_unicast = 1;\n\n\tmac_filters->ucast_drop_all = drop_all_ucast ?\n\t mac_filters->ucast_drop_all | mask :\n\t mac_filters->ucast_drop_all & ~mask;\n\n\tmac_filters->mcast_drop_all = drop_all_mcast ?\n\t mac_filters->mcast_drop_all | mask :\n\t mac_filters->mcast_drop_all & ~mask;\n\n\tmac_filters->ucast_accept_all = accp_all_ucast ?\n\t mac_filters->ucast_accept_all | mask :\n\t mac_filters->ucast_accept_all & ~mask;\n\n\tmac_filters->mcast_accept_all = accp_all_mcast ?\n\t mac_filters->mcast_accept_all | mask :\n\t mac_filters->mcast_accept_all & ~mask;\n\n\tmac_filters->bcast_accept_all = accp_all_bcast ?\n\t mac_filters->bcast_accept_all | mask :\n\t mac_filters->bcast_accept_all & ~mask;\n\n\tmac_filters->unmatched_unicast = unmatched_unicast ?\n\t mac_filters->unmatched_unicast | mask :\n\t mac_filters->unmatched_unicast & ~mask;\n\n\tECORE_MSG(\"drop_ucast 0x%xdrop_mcast 0x%x accp_ucast 0x%x\"\n\t\t \"accp_mcast 0x%xaccp_bcast 0x%x\",\n\t\t mac_filters->ucast_drop_all, mac_filters->mcast_drop_all,\n\t\t mac_filters->ucast_accept_all, mac_filters->mcast_accept_all,\n\t\t mac_filters->bcast_accept_all);\n\n\t/* write the MAC filter structure */\n\t__storm_memset_mac_filters(sc, mac_filters, p->func_id);\n\n\t/* The operation is completed */\n\tECORE_CLEAR_BIT(p->state, p->pstate);\n\tECORE_SMP_MB_AFTER_CLEAR_BIT();\n\n\treturn ECORE_SUCCESS;\n}\n\n/* Setup ramrod data */\nstatic void ecore_rx_mode_set_rdata_hdr_e2(uint32_t cid, struct eth_classify_header\n\t\t\t\t\t *hdr, uint8_t rule_cnt)\n{\n\thdr->echo = ECORE_CPU_TO_LE32(cid);\n\thdr->rule_cnt = rule_cnt;\n}\n\nstatic void ecore_rx_mode_set_cmd_state_e2(unsigned long *accept_flags, struct eth_filter_rules_cmd\n\t\t\t\t\t *cmd, int clear_accept_all)\n{\n\tuint16_t state;\n\n\t/* start with 'drop-all' */\n\tstate = ETH_FILTER_RULES_CMD_UCAST_DROP_ALL |\n\t ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;\n\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_UNICAST, accept_flags))\n\t\tstate &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;\n\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_MULTICAST, accept_flags))\n\t\tstate &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;\n\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_ALL_UNICAST, accept_flags)) {\n\t\tstate &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;\n\t\tstate |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL;\n\t}\n\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_ALL_MULTICAST, accept_flags)) {\n\t\tstate |= ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL;\n\t\tstate &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;\n\t}\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_BROADCAST, accept_flags))\n\t\tstate |= ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL;\n\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_UNMATCHED, accept_flags)) {\n\t\tstate &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;\n\t\tstate |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED;\n\t}\n\tif (ECORE_TEST_BIT(ECORE_ACCEPT_ANY_VLAN, accept_flags))\n\t\tstate |= ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN;\n\n\t/* Clear ACCEPT_ALL_XXX flags for FCoE L2 Queue */\n\tif (clear_accept_all) {\n\t\tstate &= ~ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL;\n\t\tstate &= ~ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL;\n\t\tstate &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL;\n\t\tstate &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED;\n\t}\n\n\tcmd->state = ECORE_CPU_TO_LE16(state);\n}\n\nstatic int ecore_set_rx_mode_e2(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_rx_mode_ramrod_params *p)\n{\n\tstruct eth_filter_rules_ramrod_data *data = p->rdata;\n\tint rc;\n\tuint8_t rule_idx = 0;\n\n\t/* Reset the ramrod data buffer */\n\tECORE_MEMSET(data, 0, sizeof(*data));\n\n\t/* Setup ramrod data */\n\n\t/* Tx (internal switching) */\n\tif (ECORE_TEST_BIT(RAMROD_TX, &p->ramrod_flags)) {\n\t\tdata->rules[rule_idx].client_id = p->cl_id;\n\t\tdata->rules[rule_idx].func_id = p->func_id;\n\n\t\tdata->rules[rule_idx].cmd_general_data =\n\t\t ETH_FILTER_RULES_CMD_TX_CMD;\n\n\t\tecore_rx_mode_set_cmd_state_e2(&p->tx_accept_flags,\n\t\t\t\t\t &(data->rules[rule_idx++]),\n\t\t\t\t\t FALSE);\n\t}\n\n\t/* Rx */\n\tif (ECORE_TEST_BIT(RAMROD_RX, &p->ramrod_flags)) {\n\t\tdata->rules[rule_idx].client_id = p->cl_id;\n\t\tdata->rules[rule_idx].func_id = p->func_id;\n\n\t\tdata->rules[rule_idx].cmd_general_data =\n\t\t ETH_FILTER_RULES_CMD_RX_CMD;\n\n\t\tecore_rx_mode_set_cmd_state_e2(&p->rx_accept_flags,\n\t\t\t\t\t &(data->rules[rule_idx++]),\n\t\t\t\t\t FALSE);\n\t}\n\n\t/* If FCoE Queue configuration has been requested configure the Rx and\n\t * internal switching modes for this queue in separate rules.\n\t *\n\t * FCoE queue shell never be set to ACCEPT_ALL packets of any sort:\n\t * MCAST_ALL, UCAST_ALL, BCAST_ALL and UNMATCHED.\n\t */\n\tif (ECORE_TEST_BIT(ECORE_RX_MODE_FCOE_ETH, &p->rx_mode_flags)) {\n\t\t/* Tx (internal switching) */\n\t\tif (ECORE_TEST_BIT(RAMROD_TX, &p->ramrod_flags)) {\n\t\t\tdata->rules[rule_idx].client_id = ECORE_FCOE_CID(sc);\n\t\t\tdata->rules[rule_idx].func_id = p->func_id;\n\n\t\t\tdata->rules[rule_idx].cmd_general_data =\n\t\t\t ETH_FILTER_RULES_CMD_TX_CMD;\n\n\t\t\tecore_rx_mode_set_cmd_state_e2(&p->tx_accept_flags,\n\t\t\t\t\t\t &(data->rules\n\t\t\t\t\t\t\t [rule_idx++]), TRUE);\n\t\t}\n\n\t\t/* Rx */\n\t\tif (ECORE_TEST_BIT(RAMROD_RX, &p->ramrod_flags)) {\n\t\t\tdata->rules[rule_idx].client_id = ECORE_FCOE_CID(sc);\n\t\t\tdata->rules[rule_idx].func_id = p->func_id;\n\n\t\t\tdata->rules[rule_idx].cmd_general_data =\n\t\t\t ETH_FILTER_RULES_CMD_RX_CMD;\n\n\t\t\tecore_rx_mode_set_cmd_state_e2(&p->rx_accept_flags,\n\t\t\t\t\t\t &(data->rules\n\t\t\t\t\t\t\t [rule_idx++]), TRUE);\n\t\t}\n\t}\n\n\t/* Set the ramrod header (most importantly - number of rules to\n\t * configure).\n\t */\n\tecore_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx);\n\n\tECORE_MSG\n\t (\"About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\",\n\t data->header.rule_cnt, p->rx_accept_flags, p->tx_accept_flags);\n\n\t/* No need for an explicit memory barrier here as long we would\n\t * need to ensure the ordering of writing to the SPQ element\n\t * and updating of the SPQ producer which involves a memory\n\t * read and we will have to put a full memory barrier there\n\t * (inside ecore_sp_post()).\n\t */\n\n\t/* Send a ramrod */\n\trc = ecore_sp_post(sc,\n\t\t\t RAMROD_CMD_ID_ETH_FILTER_RULES,\n\t\t\t p->cid, p->rdata_mapping, ETH_CONNECTION_TYPE);\n\tif (rc)\n\t\treturn rc;\n\n\t/* Ramrod completion is pending */\n\treturn ECORE_PENDING;\n}\n\nstatic int ecore_wait_rx_mode_comp_e2(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_rx_mode_ramrod_params *p)\n{\n\treturn ecore_state_wait(sc, p->state, p->pstate);\n}\n\nstatic int ecore_empty_rx_mode_wait(__rte_unused struct bnx2x_softc *sc,\n\t\t\t\t __rte_unused struct\n\t\t\t\t ecore_rx_mode_ramrod_params *p)\n{\n\t/* Do nothing */\n\treturn ECORE_SUCCESS;\n}\n\nint ecore_config_rx_mode(struct bnx2x_softc *sc,\n\t\t\t struct ecore_rx_mode_ramrod_params *p)\n{\n\tint rc;\n\n\t/* Configure the new classification in the chip */\n\tif (p->rx_mode_obj->config_rx_mode) {\n\t\trc = p->rx_mode_obj->config_rx_mode(sc, p);\n\t\tif (rc < 0)\n\t\t\treturn rc;\n\n\t\t/* Wait for a ramrod completion if was requested */\n\t\tif (ECORE_TEST_BIT(RAMROD_COMP_WAIT, &p->ramrod_flags)) {\n\t\t\trc = p->rx_mode_obj->wait_comp(sc, p);\n\t\t\tif (rc)\n\t\t\t\treturn rc;\n\t\t}\n\t} else {\n\t\tECORE_MSG(\"ERROR: config_rx_mode is NULL\");\n\t\treturn -1;\n\t}\n\n\treturn rc;\n}\n\nvoid ecore_init_rx_mode_obj(struct bnx2x_softc *sc, struct ecore_rx_mode_obj *o)\n{\n\tif (CHIP_IS_E1x(sc)) {\n\t\to->wait_comp = ecore_empty_rx_mode_wait;\n\t\to->config_rx_mode = ecore_set_rx_mode_e1x;\n\t} else {\n\t\to->wait_comp = ecore_wait_rx_mode_comp_e2;\n\t\to->config_rx_mode = ecore_set_rx_mode_e2;\n\t}\n}\n\n/********************* Multicast verbs: SET, CLEAR ****************************/\nstatic uint8_t ecore_mcast_bin_from_mac(uint8_t * mac)\n{\n\treturn (ECORE_CRC32_LE(0, mac, ETH_ALEN) >> 24) & 0xff;\n}\n\nstruct ecore_mcast_mac_elem {\n\tecore_list_entry_t link;\n\tuint8_t mac[ETH_ALEN];\n\tuint8_t pad[2];\t\t/* For a natural alignment of the following buffer */\n};\n\nstruct ecore_pending_mcast_cmd {\n\tecore_list_entry_t link;\n\tint type;\t\t/* ECORE_MCAST_CMD_X */\n\tunion {\n\t\tecore_list_t macs_head;\n\t\tuint32_t macs_num;\t/* Needed for DEL command */\n\t\tint next_bin;\t/* Needed for RESTORE flow with aprox match */\n\t} data;\n\n\tint done;\t\t/* set to TRUE, when the command has been handled,\n\t\t\t\t * practically used in 57712 handling only, where one pending\n\t\t\t\t * command may be handled in a few operations. As long as for\n\t\t\t\t * other chips every operation handling is completed in a\n\t\t\t\t * single ramrod, there is no need to utilize this field.\n\t\t\t\t */\n};\n\nstatic int ecore_mcast_wait(struct bnx2x_softc *sc, struct ecore_mcast_obj *o)\n{\n\tif (ecore_state_wait(sc, o->sched_state, o->raw.pstate) ||\n\t o->raw.wait_comp(sc, &o->raw))\n\t\treturn ECORE_TIMEOUT;\n\n\treturn ECORE_SUCCESS;\n}\n\nstatic int ecore_mcast_enqueue_cmd(struct bnx2x_softc *sc __rte_unused,\n\t\t\t\t struct ecore_mcast_obj *o,\n\t\t\t\t struct ecore_mcast_ramrod_params *p,\n\t\t\t\t enum ecore_mcast_cmd cmd)\n{\n\tint total_sz;\n\tstruct ecore_pending_mcast_cmd *new_cmd;\n\tstruct ecore_mcast_mac_elem *cur_mac = NULL;\n\tstruct ecore_mcast_list_elem *pos;\n\tint macs_list_len = ((cmd == ECORE_MCAST_CMD_ADD) ?\n\t\t\t p->mcast_list_len : 0);\n\n\t/* If the command is empty (\"handle pending commands only\"), break */\n\tif (!p->mcast_list_len)\n\t\treturn ECORE_SUCCESS;\n\n\ttotal_sz = sizeof(*new_cmd) +\n\t macs_list_len * sizeof(struct ecore_mcast_mac_elem);\n\n\t/* Add mcast is called under spin_lock, thus calling with GFP_ATOMIC */\n\tnew_cmd = ECORE_ZALLOC(total_sz, GFP_ATOMIC, sc);\n\n\tif (!new_cmd)\n\t\treturn ECORE_NOMEM;\n\n\tECORE_MSG(\"About to enqueue a new %d command. macs_list_len=%d\",\n\t\t cmd, macs_list_len);\n\n\tECORE_LIST_INIT(&new_cmd->data.macs_head);\n\n\tnew_cmd->type = cmd;\n\tnew_cmd->done = FALSE;\n\n\tswitch (cmd) {\n\tcase ECORE_MCAST_CMD_ADD:\n\t\tcur_mac = (struct ecore_mcast_mac_elem *)\n\t\t ((uint8_t *) new_cmd + sizeof(*new_cmd));\n\n\t\t/* Push the MACs of the current command into the pending command\n\t\t * MACs list: FIFO\n\t\t */\n\t\tECORE_LIST_FOR_EACH_ENTRY(pos, &p->mcast_list, link,\n\t\t\t\t\t struct ecore_mcast_list_elem) {\n\t\t\tECORE_MEMCPY(cur_mac->mac, pos->mac, ETH_ALEN);\n\t\t\tECORE_LIST_PUSH_TAIL(&cur_mac->link,\n\t\t\t\t\t &new_cmd->data.macs_head);\n\t\t\tcur_mac++;\n\t\t}\n\n\t\tbreak;\n\n\tcase ECORE_MCAST_CMD_DEL:\n\t\tnew_cmd->data.macs_num = p->mcast_list_len;\n\t\tbreak;\n\n\tcase ECORE_MCAST_CMD_RESTORE:\n\t\tnew_cmd->data.next_bin = 0;\n\t\tbreak;\n\n\tdefault:\n\t\tECORE_FREE(sc, new_cmd, total_sz);\n\t\tPMD_DRV_LOG(ERR, \"Unknown command: %d\", cmd);\n\t\treturn ECORE_INVAL;\n\t}\n\n\t/* Push the new pending command to the tail of the pending list: FIFO */\n\tECORE_LIST_PUSH_TAIL(&new_cmd->link, &o->pending_cmds_head);\n\n\to->set_sched(o);\n\n\treturn ECORE_PENDING;\n}\n\n/**\n * ecore_mcast_get_next_bin - get the next set bin (index)\n *\n * @o:\n * @last:\tindex to start looking from (including)\n *\n * returns the next found (set) bin or a negative value if none is found.\n */\nstatic int ecore_mcast_get_next_bin(struct ecore_mcast_obj *o, int last)\n{\n\tint i, j, inner_start = last % BIT_VEC64_ELEM_SZ;\n\n\tfor (i = last / BIT_VEC64_ELEM_SZ; i < ECORE_MCAST_VEC_SZ; i++) {\n\t\tif (o->registry.aprox_match.vec[i])\n\t\t\tfor (j = inner_start; j < BIT_VEC64_ELEM_SZ; j++) {\n\t\t\t\tint cur_bit = j + BIT_VEC64_ELEM_SZ * i;\n\t\t\t\tif (BIT_VEC64_TEST_BIT\n\t\t\t\t (o->registry.aprox_match.vec, cur_bit)) {\n\t\t\t\t\treturn cur_bit;\n\t\t\t\t}\n\t\t\t}\n\t\tinner_start = 0;\n\t}\n\n\t/* None found */\n\treturn -1;\n}\n\n/**\n * ecore_mcast_clear_first_bin - find the first set bin and clear it\n *\n * @o:\n *\n * returns the index of the found bin or -1 if none is found\n */\nstatic int ecore_mcast_clear_first_bin(struct ecore_mcast_obj *o)\n{\n\tint cur_bit = ecore_mcast_get_next_bin(o, 0);\n\n\tif (cur_bit >= 0)\n\t\tBIT_VEC64_CLEAR_BIT(o->registry.aprox_match.vec, cur_bit);\n\n\treturn cur_bit;\n}\n\nstatic uint8_t ecore_mcast_get_rx_tx_flag(struct ecore_mcast_obj *o)\n{\n\tstruct ecore_raw_obj *raw = &o->raw;\n\tuint8_t rx_tx_flag = 0;\n\n\tif ((raw->obj_type == ECORE_OBJ_TYPE_TX) ||\n\t (raw->obj_type == ECORE_OBJ_TYPE_RX_TX))\n\t\trx_tx_flag |= ETH_MULTICAST_RULES_CMD_TX_CMD;\n\n\tif ((raw->obj_type == ECORE_OBJ_TYPE_RX) ||\n\t (raw->obj_type == ECORE_OBJ_TYPE_RX_TX))\n\t\trx_tx_flag |= ETH_MULTICAST_RULES_CMD_RX_CMD;\n\n\treturn rx_tx_flag;\n}\n\nstatic void ecore_mcast_set_one_rule_e2(struct bnx2x_softc *sc __rte_unused,\n\t\t\t\t\tstruct ecore_mcast_obj *o, int idx,\n\t\t\t\t\tunion ecore_mcast_config_data *cfg_data,\n\t\t\t\t\tenum ecore_mcast_cmd cmd)\n{\n\tstruct ecore_raw_obj *r = &o->raw;\n\tstruct eth_multicast_rules_ramrod_data *data =\n\t (struct eth_multicast_rules_ramrod_data *)(r->rdata);\n\tuint8_t func_id = r->func_id;\n\tuint8_t rx_tx_add_flag = ecore_mcast_get_rx_tx_flag(o);\n\tint bin;\n\n\tif ((cmd == ECORE_MCAST_CMD_ADD) || (cmd == ECORE_MCAST_CMD_RESTORE))\n\t\trx_tx_add_flag |= ETH_MULTICAST_RULES_CMD_IS_ADD;\n\n\tdata->rules[idx].cmd_general_data |= rx_tx_add_flag;\n\n\t/* Get a bin and update a bins' vector */\n\tswitch (cmd) {\n\tcase ECORE_MCAST_CMD_ADD:\n\t\tbin = ecore_mcast_bin_from_mac(cfg_data->mac);\n\t\tBIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bin);\n\t\tbreak;\n\n\tcase ECORE_MCAST_CMD_DEL:\n\t\t/* If there were no more bins to clear\n\t\t * (ecore_mcast_clear_first_bin() returns -1) then we would\n\t\t * clear any (0xff) bin.\n\t\t * See ecore_mcast_validate_e2() for explanation when it may\n\t\t * happen.\n\t\t */\n\t\tbin = ecore_mcast_clear_first_bin(o);\n\t\tbreak;\n\n\tcase ECORE_MCAST_CMD_RESTORE:\n\t\tbin = cfg_data->bin;\n\t\tbreak;\n\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Unknown command: %d\", cmd);\n\t\treturn;\n\t}\n\n\tECORE_MSG(\"%s bin %d\",\n\t\t ((rx_tx_add_flag & ETH_MULTICAST_RULES_CMD_IS_ADD) ?\n\t\t \"Setting\" : \"Clearing\"), bin);\n\n\tdata->rules[idx].bin_id = (uint8_t) bin;\n\tdata->rules[idx].func_id = func_id;\n\tdata->rules[idx].engine_id = o->engine_id;\n}\n\n/**\n * ecore_mcast_handle_restore_cmd_e2 - restore configuration from the registry\n *\n * @sc:\t\tdevice handle\n * @o:\n * @start_bin:\tindex in the registry to start from (including)\n * @rdata_idx:\tindex in the ramrod data to start from\n *\n * returns last handled bin index or -1 if all bins have been handled\n */\nstatic int ecore_mcast_handle_restore_cmd_e2(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_mcast_obj *o,\n\t\t\t\t\t int start_bin, int *rdata_idx)\n{\n\tint cur_bin, cnt = *rdata_idx;\n\tunion ecore_mcast_config_data cfg_data = { NULL };\n\n\t/* go through the registry and configure the bins from it */\n\tfor (cur_bin = ecore_mcast_get_next_bin(o, start_bin); cur_bin >= 0;\n\t cur_bin = ecore_mcast_get_next_bin(o, cur_bin + 1)) {\n\n\t\tcfg_data.bin = (uint8_t) cur_bin;\n\t\to->set_one_rule(sc, o, cnt, &cfg_data, ECORE_MCAST_CMD_RESTORE);\n\n\t\tcnt++;\n\n\t\tECORE_MSG(\"About to configure a bin %d\", cur_bin);\n\n\t\t/* Break if we reached the maximum number\n\t\t * of rules.\n\t\t */\n\t\tif (cnt >= o->max_cmd_len)\n\t\t\tbreak;\n\t}\n\n\t*rdata_idx = cnt;\n\n\treturn cur_bin;\n}\n\nstatic void ecore_mcast_hdl_pending_add_e2(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_mcast_obj *o,\n\t\t\t\t\t struct ecore_pending_mcast_cmd\n\t\t\t\t\t *cmd_pos, int *line_idx)\n{\n\tstruct ecore_mcast_mac_elem *pmac_pos, *pmac_pos_n;\n\tint cnt = *line_idx;\n\tunion ecore_mcast_config_data cfg_data = { NULL };\n\n\tECORE_LIST_FOR_EACH_ENTRY_SAFE(pmac_pos, pmac_pos_n,\n\t\t\t\t &cmd_pos->data.macs_head, link,\n\t\t\t\t struct ecore_mcast_mac_elem) {\n\n\t\tcfg_data.mac = &pmac_pos->mac[0];\n\t\to->set_one_rule(sc, o, cnt, &cfg_data, cmd_pos->type);\n\n\t\tcnt++;\n\n\t\tECORE_MSG\n\t\t (\"About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC\",\n\t\t pmac_pos->mac[0], pmac_pos->mac[1], pmac_pos->mac[2],\n\t\t pmac_pos->mac[3], pmac_pos->mac[4], pmac_pos->mac[5]);\n\n\t\tECORE_LIST_REMOVE_ENTRY(&pmac_pos->link,\n\t\t\t\t\t&cmd_pos->data.macs_head);\n\n\t\t/* Break if we reached the maximum number\n\t\t * of rules.\n\t\t */\n\t\tif (cnt >= o->max_cmd_len)\n\t\t\tbreak;\n\t}\n\n\t*line_idx = cnt;\n\n\t/* if no more MACs to configure - we are done */\n\tif (ECORE_LIST_IS_EMPTY(&cmd_pos->data.macs_head))\n\t\tcmd_pos->done = TRUE;\n}\n\nstatic void ecore_mcast_hdl_pending_del_e2(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_mcast_obj *o,\n\t\t\t\t\t struct ecore_pending_mcast_cmd\n\t\t\t\t\t *cmd_pos, int *line_idx)\n{\n\tint cnt = *line_idx;\n\n\twhile (cmd_pos->data.macs_num) {\n\t\to->set_one_rule(sc, o, cnt, NULL, cmd_pos->type);\n\n\t\tcnt++;\n\n\t\tcmd_pos->data.macs_num--;\n\n\t\tECORE_MSG(\"Deleting MAC. %d left,cnt is %d\",\n\t\t\t cmd_pos->data.macs_num, cnt);\n\n\t\t/* Break if we reached the maximum\n\t\t * number of rules.\n\t\t */\n\t\tif (cnt >= o->max_cmd_len)\n\t\t\tbreak;\n\t}\n\n\t*line_idx = cnt;\n\n\t/* If we cleared all bins - we are done */\n\tif (!cmd_pos->data.macs_num)\n\t\tcmd_pos->done = TRUE;\n}\n\nstatic void ecore_mcast_hdl_pending_restore_e2(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_mcast_obj *o, struct\n\t\t\t\t\t ecore_pending_mcast_cmd\n\t\t\t\t\t *cmd_pos, int *line_idx)\n{\n\tcmd_pos->data.next_bin = o->hdl_restore(sc, o, cmd_pos->data.next_bin,\n\t\t\t\t\t\tline_idx);\n\n\tif (cmd_pos->data.next_bin < 0)\n\t\t/* If o->set_restore returned -1 we are done */\n\t\tcmd_pos->done = TRUE;\n\telse\n\t\t/* Start from the next bin next time */\n\t\tcmd_pos->data.next_bin++;\n}\n\nstatic int ecore_mcast_handle_pending_cmds_e2(struct bnx2x_softc *sc, struct\n\t\t\t\t\t ecore_mcast_ramrod_params\n\t\t\t\t\t *p)\n{\n\tstruct ecore_pending_mcast_cmd *cmd_pos, *cmd_pos_n;\n\tint cnt = 0;\n\tstruct ecore_mcast_obj *o = p->mcast_obj;\n\n\tECORE_LIST_FOR_EACH_ENTRY_SAFE(cmd_pos, cmd_pos_n,\n\t\t\t\t &o->pending_cmds_head, link,\n\t\t\t\t struct ecore_pending_mcast_cmd) {\n\t\tswitch (cmd_pos->type) {\n\t\tcase ECORE_MCAST_CMD_ADD:\n\t\t\tecore_mcast_hdl_pending_add_e2(sc, o, cmd_pos, &cnt);\n\t\t\tbreak;\n\n\t\tcase ECORE_MCAST_CMD_DEL:\n\t\t\tecore_mcast_hdl_pending_del_e2(sc, o, cmd_pos, &cnt);\n\t\t\tbreak;\n\n\t\tcase ECORE_MCAST_CMD_RESTORE:\n\t\t\tecore_mcast_hdl_pending_restore_e2(sc, o, cmd_pos,\n\t\t\t\t\t\t\t &cnt);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(ERR, \"Unknown command: %d\", cmd_pos->type);\n\t\t\treturn ECORE_INVAL;\n\t\t}\n\n\t\t/* If the command has been completed - remove it from the list\n\t\t * and free the memory\n\t\t */\n\t\tif (cmd_pos->done) {\n\t\t\tECORE_LIST_REMOVE_ENTRY(&cmd_pos->link,\n\t\t\t\t\t\t&o->pending_cmds_head);\n\t\t\tECORE_FREE(sc, cmd_pos, cmd_pos->alloc_len);\n\t\t}\n\n\t\t/* Break if we reached the maximum number of rules */\n\t\tif (cnt >= o->max_cmd_len)\n\t\t\tbreak;\n\t}\n\n\treturn cnt;\n}\n\nstatic void ecore_mcast_hdl_add(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_mcast_obj *o,\n\t\t\t\tstruct ecore_mcast_ramrod_params *p,\n\t\t\t\tint *line_idx)\n{\n\tstruct ecore_mcast_list_elem *mlist_pos;\n\tunion ecore_mcast_config_data cfg_data = { NULL };\n\tint cnt = *line_idx;\n\n\tECORE_LIST_FOR_EACH_ENTRY(mlist_pos, &p->mcast_list, link,\n\t\t\t\t struct ecore_mcast_list_elem) {\n\t\tcfg_data.mac = mlist_pos->mac;\n\t\to->set_one_rule(sc, o, cnt, &cfg_data, ECORE_MCAST_CMD_ADD);\n\n\t\tcnt++;\n\n\t\tECORE_MSG\n\t\t (\"About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC\",\n\t\t mlist_pos->mac[0], mlist_pos->mac[1], mlist_pos->mac[2],\n\t\t mlist_pos->mac[3], mlist_pos->mac[4], mlist_pos->mac[5]);\n\t}\n\n\t*line_idx = cnt;\n}\n\nstatic void ecore_mcast_hdl_del(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_mcast_obj *o,\n\t\t\t\tstruct ecore_mcast_ramrod_params *p,\n\t\t\t\tint *line_idx)\n{\n\tint cnt = *line_idx, i;\n\n\tfor (i = 0; i < p->mcast_list_len; i++) {\n\t\to->set_one_rule(sc, o, cnt, NULL, ECORE_MCAST_CMD_DEL);\n\n\t\tcnt++;\n\n\t\tECORE_MSG(\"Deleting MAC. %d left\", p->mcast_list_len - i - 1);\n\t}\n\n\t*line_idx = cnt;\n}\n\n/**\n * ecore_mcast_handle_current_cmd -\n *\n * @sc:\t\tdevice handle\n * @p:\n * @cmd:\n * @start_cnt:\tfirst line in the ramrod data that may be used\n *\n * This function is called iff there is enough place for the current command in\n * the ramrod data.\n * Returns number of lines filled in the ramrod data in total.\n */\nstatic int ecore_mcast_handle_current_cmd(struct bnx2x_softc *sc, struct\n\t\t\t\t\t ecore_mcast_ramrod_params *p,\n\t\t\t\t\t enum ecore_mcast_cmd cmd,\n\t\t\t\t\t int start_cnt)\n{\n\tstruct ecore_mcast_obj *o = p->mcast_obj;\n\tint cnt = start_cnt;\n\n\tECORE_MSG(\"p->mcast_list_len=%d\", p->mcast_list_len);\n\n\tswitch (cmd) {\n\tcase ECORE_MCAST_CMD_ADD:\n\t\tecore_mcast_hdl_add(sc, o, p, &cnt);\n\t\tbreak;\n\n\tcase ECORE_MCAST_CMD_DEL:\n\t\tecore_mcast_hdl_del(sc, o, p, &cnt);\n\t\tbreak;\n\n\tcase ECORE_MCAST_CMD_RESTORE:\n\t\to->hdl_restore(sc, o, 0, &cnt);\n\t\tbreak;\n\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Unknown command: %d\", cmd);\n\t\treturn ECORE_INVAL;\n\t}\n\n\t/* The current command has been handled */\n\tp->mcast_list_len = 0;\n\n\treturn cnt;\n}\n\nstatic int ecore_mcast_validate_e2(__rte_unused struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_mcast_ramrod_params *p,\n\t\t\t\t enum ecore_mcast_cmd cmd)\n{\n\tstruct ecore_mcast_obj *o = p->mcast_obj;\n\tint reg_sz = o->get_registry_size(o);\n\n\tswitch (cmd) {\n\t\t/* DEL command deletes all currently configured MACs */\n\tcase ECORE_MCAST_CMD_DEL:\n\t\to->set_registry_size(o, 0);\n\t\t/* Don't break */\n\n\t\t/* RESTORE command will restore the entire multicast configuration */\n\tcase ECORE_MCAST_CMD_RESTORE:\n\t\t/* Here we set the approximate amount of work to do, which in\n\t\t * fact may be only less as some MACs in postponed ADD\n\t\t * command(s) scheduled before this command may fall into\n\t\t * the same bin and the actual number of bins set in the\n\t\t * registry would be less than we estimated here. See\n\t\t * ecore_mcast_set_one_rule_e2() for further details.\n\t\t */\n\t\tp->mcast_list_len = reg_sz;\n\t\tbreak;\n\n\tcase ECORE_MCAST_CMD_ADD:\n\tcase ECORE_MCAST_CMD_CONT:\n\t\t/* Here we assume that all new MACs will fall into new bins.\n\t\t * However we will correct the real registry size after we\n\t\t * handle all pending commands.\n\t\t */\n\t\to->set_registry_size(o, reg_sz + p->mcast_list_len);\n\t\tbreak;\n\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Unknown command: %d\", cmd);\n\t\treturn ECORE_INVAL;\n\t}\n\n\t/* Increase the total number of MACs pending to be configured */\n\to->total_pending_num += p->mcast_list_len;\n\n\treturn ECORE_SUCCESS;\n}\n\nstatic void ecore_mcast_revert_e2(__rte_unused struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_mcast_ramrod_params *p,\n\t\t\t\t int old_num_bins)\n{\n\tstruct ecore_mcast_obj *o = p->mcast_obj;\n\n\to->set_registry_size(o, old_num_bins);\n\to->total_pending_num -= p->mcast_list_len;\n}\n\n/**\n * ecore_mcast_set_rdata_hdr_e2 - sets a header values\n *\n * @sc:\t\tdevice handle\n * @p:\n * @len:\tnumber of rules to handle\n */\nstatic void ecore_mcast_set_rdata_hdr_e2(__rte_unused struct bnx2x_softc\n\t\t\t\t\t *sc, struct ecore_mcast_ramrod_params\n\t\t\t\t\t *p, uint8_t len)\n{\n\tstruct ecore_raw_obj *r = &p->mcast_obj->raw;\n\tstruct eth_multicast_rules_ramrod_data *data =\n\t (struct eth_multicast_rules_ramrod_data *)(r->rdata);\n\n\tdata->header.echo = ECORE_CPU_TO_LE32((r->cid & ECORE_SWCID_MASK) |\n\t\t\t\t\t (ECORE_FILTER_MCAST_PENDING <<\n\t\t\t\t\t ECORE_SWCID_SHIFT));\n\tdata->header.rule_cnt = len;\n}\n\n/**\n * ecore_mcast_refresh_registry_e2 - recalculate the actual number of set bins\n *\n * @sc:\t\tdevice handle\n * @o:\n *\n * Recalculate the actual number of set bins in the registry using Brian\n * Kernighan's algorithm: it's execution complexity is as a number of set bins.\n */\nstatic int ecore_mcast_refresh_registry_e2(struct ecore_mcast_obj *o)\n{\n\tint i, cnt = 0;\n\tuint64_t elem;\n\n\tfor (i = 0; i < ECORE_MCAST_VEC_SZ; i++) {\n\t\telem = o->registry.aprox_match.vec[i];\n\t\tfor (; elem; cnt++)\n\t\t\telem &= elem - 1;\n\t}\n\n\to->set_registry_size(o, cnt);\n\n\treturn ECORE_SUCCESS;\n}\n\nstatic int ecore_mcast_setup_e2(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_mcast_ramrod_params *p,\n\t\t\t\tenum ecore_mcast_cmd cmd)\n{\n\tstruct ecore_raw_obj *raw = &p->mcast_obj->raw;\n\tstruct ecore_mcast_obj *o = p->mcast_obj;\n\tstruct eth_multicast_rules_ramrod_data *data =\n\t (struct eth_multicast_rules_ramrod_data *)(raw->rdata);\n\tint cnt = 0, rc;\n\n\t/* Reset the ramrod data buffer */\n\tECORE_MEMSET(data, 0, sizeof(*data));\n\n\tcnt = ecore_mcast_handle_pending_cmds_e2(sc, p);\n\n\t/* If there are no more pending commands - clear SCHEDULED state */\n\tif (ECORE_LIST_IS_EMPTY(&o->pending_cmds_head))\n\t\to->clear_sched(o);\n\n\t/* The below may be TRUE iff there was enough room in ramrod\n\t * data for all pending commands and for the current\n\t * command. Otherwise the current command would have been added\n\t * to the pending commands and p->mcast_list_len would have been\n\t * zeroed.\n\t */\n\tif (p->mcast_list_len > 0)\n\t\tcnt = ecore_mcast_handle_current_cmd(sc, p, cmd, cnt);\n\n\t/* We've pulled out some MACs - update the total number of\n\t * outstanding.\n\t */\n\to->total_pending_num -= cnt;\n\n\t/* send a ramrod */\n\tECORE_DBG_BREAK_IF(o->total_pending_num < 0);\n\tECORE_DBG_BREAK_IF(cnt > o->max_cmd_len);\n\n\tecore_mcast_set_rdata_hdr_e2(sc, p, (uint8_t) cnt);\n\n\t/* Update a registry size if there are no more pending operations.\n\t *\n\t * We don't want to change the value of the registry size if there are\n\t * pending operations because we want it to always be equal to the\n\t * exact or the approximate number (see ecore_mcast_validate_e2()) of\n\t * set bins after the last requested operation in order to properly\n\t * evaluate the size of the next DEL/RESTORE operation.\n\t *\n\t * Note that we update the registry itself during command(s) handling\n\t * - see ecore_mcast_set_one_rule_e2(). That's because for 57712 we\n\t * aggregate multiple commands (ADD/DEL/RESTORE) into one ramrod but\n\t * with a limited amount of update commands (per MAC/bin) and we don't\n\t * know in this scope what the actual state of bins configuration is\n\t * going to be after this ramrod.\n\t */\n\tif (!o->total_pending_num)\n\t\tecore_mcast_refresh_registry_e2(o);\n\n\t/* If CLEAR_ONLY was requested - don't send a ramrod and clear\n\t * RAMROD_PENDING status immediately.\n\t */\n\tif (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {\n\t\traw->clear_pending(raw);\n\t\treturn ECORE_SUCCESS;\n\t} else {\n\t\t/* No need for an explicit memory barrier here as long we would\n\t\t * need to ensure the ordering of writing to the SPQ element\n\t\t * and updating of the SPQ producer which involves a memory\n\t\t * read and we will have to put a full memory barrier there\n\t\t * (inside ecore_sp_post()).\n\t\t */\n\n\t\t/* Send a ramrod */\n\t\trc = ecore_sp_post(sc,\n\t\t\t\t RAMROD_CMD_ID_ETH_MULTICAST_RULES,\n\t\t\t\t raw->cid,\n\t\t\t\t raw->rdata_mapping, ETH_CONNECTION_TYPE);\n\t\tif (rc)\n\t\t\treturn rc;\n\n\t\t/* Ramrod completion is pending */\n\t\treturn ECORE_PENDING;\n\t}\n}\n\nstatic int ecore_mcast_validate_e1h(__rte_unused struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_mcast_ramrod_params *p,\n\t\t\t\t enum ecore_mcast_cmd cmd)\n{\n\t/* Mark, that there is a work to do */\n\tif ((cmd == ECORE_MCAST_CMD_DEL) || (cmd == ECORE_MCAST_CMD_RESTORE))\n\t\tp->mcast_list_len = 1;\n\n\treturn ECORE_SUCCESS;\n}\n\nstatic void ecore_mcast_revert_e1h(__rte_unused struct bnx2x_softc *sc,\n\t\t\t\t __rte_unused struct ecore_mcast_ramrod_params\n\t\t\t\t *p, __rte_unused int old_num_bins)\n{\n\t/* Do nothing */\n}\n\n#define ECORE_57711_SET_MC_FILTER(filter, bit) \\\ndo { \\\n\t(filter)[(bit) >> 5] |= (1 << ((bit) & 0x1f)); \\\n} while (0)\n\nstatic void ecore_mcast_hdl_add_e1h(struct bnx2x_softc *sc __rte_unused,\n\t\t\t\t struct ecore_mcast_obj *o,\n\t\t\t\t struct ecore_mcast_ramrod_params *p,\n\t\t\t\t uint32_t * mc_filter)\n{\n\tstruct ecore_mcast_list_elem *mlist_pos;\n\tint bit;\n\n\tECORE_LIST_FOR_EACH_ENTRY(mlist_pos, &p->mcast_list, link,\n\t\t\t\t struct ecore_mcast_list_elem) {\n\t\tbit = ecore_mcast_bin_from_mac(mlist_pos->mac);\n\t\tECORE_57711_SET_MC_FILTER(mc_filter, bit);\n\n\t\tECORE_MSG\n\t\t (\"About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC, bin %d\",\n\t\t mlist_pos->mac[0], mlist_pos->mac[1], mlist_pos->mac[2],\n\t\t mlist_pos->mac[3], mlist_pos->mac[4], mlist_pos->mac[5],\n\t\t bit);\n\n\t\t/* bookkeeping... */\n\t\tBIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bit);\n\t}\n}\n\nstatic void ecore_mcast_hdl_restore_e1h(struct bnx2x_softc *sc\n\t\t\t\t\t__rte_unused,\n\t\t\t\t\tstruct ecore_mcast_obj *o,\n\t\t\t\t\tuint32_t * mc_filter)\n{\n\tint bit;\n\n\tfor (bit = ecore_mcast_get_next_bin(o, 0);\n\t bit >= 0; bit = ecore_mcast_get_next_bin(o, bit + 1)) {\n\t\tECORE_57711_SET_MC_FILTER(mc_filter, bit);\n\t\tECORE_MSG(\"About to set bin %d\", bit);\n\t}\n}\n\n/* On 57711 we write the multicast MACs' approximate match\n * table by directly into the TSTORM's internal RAM. So we don't\n * really need to handle any tricks to make it work.\n */\nstatic int ecore_mcast_setup_e1h(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_mcast_ramrod_params *p,\n\t\t\t\t enum ecore_mcast_cmd cmd)\n{\n\tint i;\n\tstruct ecore_mcast_obj *o = p->mcast_obj;\n\tstruct ecore_raw_obj *r = &o->raw;\n\n\t/* If CLEAR_ONLY has been requested - clear the registry\n\t * and clear a pending bit.\n\t */\n\tif (!ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {\n\t\tuint32_t mc_filter[ECORE_MC_HASH_SIZE] = { 0 };\n\n\t\t/* Set the multicast filter bits before writing it into\n\t\t * the internal memory.\n\t\t */\n\t\tswitch (cmd) {\n\t\tcase ECORE_MCAST_CMD_ADD:\n\t\t\tecore_mcast_hdl_add_e1h(sc, o, p, mc_filter);\n\t\t\tbreak;\n\n\t\tcase ECORE_MCAST_CMD_DEL:\n\t\t\tECORE_MSG(\"Invalidating multicast MACs configuration\");\n\n\t\t\t/* clear the registry */\n\t\t\tECORE_MEMSET(o->registry.aprox_match.vec, 0,\n\t\t\t\t sizeof(o->registry.aprox_match.vec));\n\t\t\tbreak;\n\n\t\tcase ECORE_MCAST_CMD_RESTORE:\n\t\t\tecore_mcast_hdl_restore_e1h(sc, o, mc_filter);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(ERR, \"Unknown command: %d\", cmd);\n\t\t\treturn ECORE_INVAL;\n\t\t}\n\n\t\t/* Set the mcast filter in the internal memory */\n\t\tfor (i = 0; i < ECORE_MC_HASH_SIZE; i++)\n\t\t\tREG_WR(sc, ECORE_MC_HASH_OFFSET(sc, i), mc_filter[i]);\n\t} else\n\t\t/* clear the registry */\n\t\tECORE_MEMSET(o->registry.aprox_match.vec, 0,\n\t\t\t sizeof(o->registry.aprox_match.vec));\n\n\t/* We are done */\n\tr->clear_pending(r);\n\n\treturn ECORE_SUCCESS;\n}\n\nstatic int ecore_mcast_get_registry_size_aprox(struct ecore_mcast_obj *o)\n{\n\treturn o->registry.aprox_match.num_bins_set;\n}\n\nstatic void ecore_mcast_set_registry_size_aprox(struct ecore_mcast_obj *o,\n\t\t\t\t\t\tint n)\n{\n\to->registry.aprox_match.num_bins_set = n;\n}\n\nint ecore_config_mcast(struct bnx2x_softc *sc,\n\t\t struct ecore_mcast_ramrod_params *p,\n\t\t enum ecore_mcast_cmd cmd)\n{\n\tstruct ecore_mcast_obj *o = p->mcast_obj;\n\tstruct ecore_raw_obj *r = &o->raw;\n\tint rc = 0, old_reg_size;\n\n\t/* This is needed to recover number of currently configured mcast macs\n\t * in case of failure.\n\t */\n\told_reg_size = o->get_registry_size(o);\n\n\t/* Do some calculations and checks */\n\trc = o->validate(sc, p, cmd);\n\tif (rc)\n\t\treturn rc;\n\n\t/* Return if there is no work to do */\n\tif ((!p->mcast_list_len) && (!o->check_sched(o)))\n\t\treturn ECORE_SUCCESS;\n\n\tECORE_MSG\n\t (\"o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\",\n\t o->total_pending_num, p->mcast_list_len, o->max_cmd_len);\n\n\t/* Enqueue the current command to the pending list if we can't complete\n\t * it in the current iteration\n\t */\n\tif (r->check_pending(r) ||\n\t ((o->max_cmd_len > 0) && (o->total_pending_num > o->max_cmd_len))) {\n\t\trc = o->enqueue_cmd(sc, p->mcast_obj, p, cmd);\n\t\tif (rc < 0)\n\t\t\tgoto error_exit1;\n\n\t\t/* As long as the current command is in a command list we\n\t\t * don't need to handle it separately.\n\t\t */\n\t\tp->mcast_list_len = 0;\n\t}\n\n\tif (!r->check_pending(r)) {\n\n\t\t/* Set 'pending' state */\n\t\tr->set_pending(r);\n\n\t\t/* Configure the new classification in the chip */\n\t\trc = o->config_mcast(sc, p, cmd);\n\t\tif (rc < 0)\n\t\t\tgoto error_exit2;\n\n\t\t/* Wait for a ramrod completion if was requested */\n\t\tif (ECORE_TEST_BIT(RAMROD_COMP_WAIT, &p->ramrod_flags))\n\t\t\trc = o->wait_comp(sc, o);\n\t}\n\n\treturn rc;\n\nerror_exit2:\n\tr->clear_pending(r);\n\nerror_exit1:\n\to->revert(sc, p, old_reg_size);\n\n\treturn rc;\n}\n\nstatic void ecore_mcast_clear_sched(struct ecore_mcast_obj *o)\n{\n\tECORE_SMP_MB_BEFORE_CLEAR_BIT();\n\tECORE_CLEAR_BIT(o->sched_state, o->raw.pstate);\n\tECORE_SMP_MB_AFTER_CLEAR_BIT();\n}\n\nstatic void ecore_mcast_set_sched(struct ecore_mcast_obj *o)\n{\n\tECORE_SMP_MB_BEFORE_CLEAR_BIT();\n\tECORE_SET_BIT(o->sched_state, o->raw.pstate);\n\tECORE_SMP_MB_AFTER_CLEAR_BIT();\n}\n\nstatic int ecore_mcast_check_sched(struct ecore_mcast_obj *o)\n{\n\treturn ! !ECORE_TEST_BIT(o->sched_state, o->raw.pstate);\n}\n\nstatic int ecore_mcast_check_pending(struct ecore_mcast_obj *o)\n{\n\treturn o->raw.check_pending(&o->raw) || o->check_sched(o);\n}\n\nvoid ecore_init_mcast_obj(struct bnx2x_softc *sc,\n\t\t\t struct ecore_mcast_obj *mcast_obj,\n\t\t\t uint8_t mcast_cl_id, uint32_t mcast_cid,\n\t\t\t uint8_t func_id, uint8_t engine_id, void *rdata,\n\t\t\t ecore_dma_addr_t rdata_mapping, int state,\n\t\t\t unsigned long *pstate, ecore_obj_type type)\n{\n\tECORE_MEMSET(mcast_obj, 0, sizeof(*mcast_obj));\n\n\tecore_init_raw_obj(&mcast_obj->raw, mcast_cl_id, mcast_cid, func_id,\n\t\t\t rdata, rdata_mapping, state, pstate, type);\n\n\tmcast_obj->engine_id = engine_id;\n\n\tECORE_LIST_INIT(&mcast_obj->pending_cmds_head);\n\n\tmcast_obj->sched_state = ECORE_FILTER_MCAST_SCHED;\n\tmcast_obj->check_sched = ecore_mcast_check_sched;\n\tmcast_obj->set_sched = ecore_mcast_set_sched;\n\tmcast_obj->clear_sched = ecore_mcast_clear_sched;\n\n\tif (CHIP_IS_E1H(sc)) {\n\t\tmcast_obj->config_mcast = ecore_mcast_setup_e1h;\n\t\tmcast_obj->enqueue_cmd = NULL;\n\t\tmcast_obj->hdl_restore = NULL;\n\t\tmcast_obj->check_pending = ecore_mcast_check_pending;\n\n\t\t/* 57711 doesn't send a ramrod, so it has unlimited credit\n\t\t * for one command.\n\t\t */\n\t\tmcast_obj->max_cmd_len = -1;\n\t\tmcast_obj->wait_comp = ecore_mcast_wait;\n\t\tmcast_obj->set_one_rule = NULL;\n\t\tmcast_obj->validate = ecore_mcast_validate_e1h;\n\t\tmcast_obj->revert = ecore_mcast_revert_e1h;\n\t\tmcast_obj->get_registry_size =\n\t\t ecore_mcast_get_registry_size_aprox;\n\t\tmcast_obj->set_registry_size =\n\t\t ecore_mcast_set_registry_size_aprox;\n\t} else {\n\t\tmcast_obj->config_mcast = ecore_mcast_setup_e2;\n\t\tmcast_obj->enqueue_cmd = ecore_mcast_enqueue_cmd;\n\t\tmcast_obj->hdl_restore = ecore_mcast_handle_restore_cmd_e2;\n\t\tmcast_obj->check_pending = ecore_mcast_check_pending;\n\t\tmcast_obj->max_cmd_len = 16;\n\t\tmcast_obj->wait_comp = ecore_mcast_wait;\n\t\tmcast_obj->set_one_rule = ecore_mcast_set_one_rule_e2;\n\t\tmcast_obj->validate = ecore_mcast_validate_e2;\n\t\tmcast_obj->revert = ecore_mcast_revert_e2;\n\t\tmcast_obj->get_registry_size =\n\t\t ecore_mcast_get_registry_size_aprox;\n\t\tmcast_obj->set_registry_size =\n\t\t ecore_mcast_set_registry_size_aprox;\n\t}\n}\n\n/*************************** Credit handling **********************************/\n\n/**\n * atomic_add_ifless - add if the result is less than a given value.\n *\n * @v:\tpointer of type ecore_atomic_t\n * @a:\tthe amount to add to v...\n * @u:\t...if (v + a) is less than u.\n *\n * returns TRUE if (v + a) was less than u, and FALSE otherwise.\n *\n */\nstatic int __atomic_add_ifless(ecore_atomic_t * v, int a, int u)\n{\n\tint c, old;\n\n\tc = ECORE_ATOMIC_READ(v);\n\tfor (;;) {\n\t\tif (ECORE_UNLIKELY(c + a >= u))\n\t\t\treturn FALSE;\n\n\t\told = ECORE_ATOMIC_CMPXCHG((v), c, c + a);\n\t\tif (ECORE_LIKELY(old == c))\n\t\t\tbreak;\n\t\tc = old;\n\t}\n\n\treturn TRUE;\n}\n\n/**\n * atomic_dec_ifmoe - dec if the result is more or equal than a given value.\n *\n * @v:\tpointer of type ecore_atomic_t\n * @a:\tthe amount to dec from v...\n * @u:\t...if (v - a) is more or equal than u.\n *\n * returns TRUE if (v - a) was more or equal than u, and FALSE\n * otherwise.\n */\nstatic int __atomic_dec_ifmoe(ecore_atomic_t * v, int a, int u)\n{\n\tint c, old;\n\n\tc = ECORE_ATOMIC_READ(v);\n\tfor (;;) {\n\t\tif (ECORE_UNLIKELY(c - a < u))\n\t\t\treturn FALSE;\n\n\t\told = ECORE_ATOMIC_CMPXCHG((v), c, c - a);\n\t\tif (ECORE_LIKELY(old == c))\n\t\t\tbreak;\n\t\tc = old;\n\t}\n\n\treturn TRUE;\n}\n\nstatic int ecore_credit_pool_get(struct ecore_credit_pool_obj *o, int cnt)\n{\n\tint rc;\n\n\tECORE_SMP_MB();\n\trc = __atomic_dec_ifmoe(&o->credit, cnt, 0);\n\tECORE_SMP_MB();\n\n\treturn rc;\n}\n\nstatic int ecore_credit_pool_put(struct ecore_credit_pool_obj *o, int cnt)\n{\n\tint rc;\n\n\tECORE_SMP_MB();\n\n\t/* Don't let to refill if credit + cnt > pool_sz */\n\trc = __atomic_add_ifless(&o->credit, cnt, o->pool_sz + 1);\n\n\tECORE_SMP_MB();\n\n\treturn rc;\n}\n\nstatic int ecore_credit_pool_check(struct ecore_credit_pool_obj *o)\n{\n\tint cur_credit;\n\n\tECORE_SMP_MB();\n\tcur_credit = ECORE_ATOMIC_READ(&o->credit);\n\n\treturn cur_credit;\n}\n\nstatic int ecore_credit_pool_always_TRUE(__rte_unused struct\n\t\t\t\t\t ecore_credit_pool_obj *o,\n\t\t\t\t\t __rte_unused int cnt)\n{\n\treturn TRUE;\n}\n\nstatic int ecore_credit_pool_get_entry(struct ecore_credit_pool_obj *o,\n\t\t\t\t int *offset)\n{\n\tint idx, vec, i;\n\n\t*offset = -1;\n\n\t/* Find \"internal cam-offset\" then add to base for this object... */\n\tfor (vec = 0; vec < ECORE_POOL_VEC_SIZE; vec++) {\n\n\t\t/* Skip the current vector if there are no free entries in it */\n\t\tif (!o->pool_mirror[vec])\n\t\t\tcontinue;\n\n\t\t/* If we've got here we are going to find a free entry */\n\t\tfor (idx = vec * BIT_VEC64_ELEM_SZ, i = 0;\n\t\t i < BIT_VEC64_ELEM_SZ; idx++, i++)\n\n\t\t\tif (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) {\n\t\t\t\t/* Got one!! */\n\t\t\t\tBIT_VEC64_CLEAR_BIT(o->pool_mirror, idx);\n\t\t\t\t*offset = o->base_pool_offset + idx;\n\t\t\t\treturn TRUE;\n\t\t\t}\n\t}\n\n\treturn FALSE;\n}\n\nstatic int ecore_credit_pool_put_entry(struct ecore_credit_pool_obj *o,\n\t\t\t\t int offset)\n{\n\tif (offset < o->base_pool_offset)\n\t\treturn FALSE;\n\n\toffset -= o->base_pool_offset;\n\n\tif (offset >= o->pool_sz)\n\t\treturn FALSE;\n\n\t/* Return the entry to the pool */\n\tBIT_VEC64_SET_BIT(o->pool_mirror, offset);\n\n\treturn TRUE;\n}\n\nstatic int ecore_credit_pool_put_entry_always_TRUE(__rte_unused struct\n\t\t\t\t\t\t ecore_credit_pool_obj *o,\n\t\t\t\t\t\t __rte_unused int offset)\n{\n\treturn TRUE;\n}\n\nstatic int ecore_credit_pool_get_entry_always_TRUE(__rte_unused struct\n\t\t\t\t\t\t ecore_credit_pool_obj *o,\n\t\t\t\t\t\t __rte_unused int *offset)\n{\n\t*offset = -1;\n\treturn TRUE;\n}\n\n/**\n * ecore_init_credit_pool - initialize credit pool internals.\n *\n * @p:\n * @base:\tBase entry in the CAM to use.\n * @credit:\tpool size.\n *\n * If base is negative no CAM entries handling will be performed.\n * If credit is negative pool operations will always succeed (unlimited pool).\n *\n */\nstatic void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,\n\t\t\t\t int base, int credit)\n{\n\t/* Zero the object first */\n\tECORE_MEMSET(p, 0, sizeof(*p));\n\n\t/* Set the table to all 1s */\n\tECORE_MEMSET(&p->pool_mirror, 0xff, sizeof(p->pool_mirror));\n\n\t/* Init a pool as full */\n\tECORE_ATOMIC_SET(&p->credit, credit);\n\n\t/* The total poll size */\n\tp->pool_sz = credit;\n\n\tp->base_pool_offset = base;\n\n\t/* Commit the change */\n\tECORE_SMP_MB();\n\n\tp->check = ecore_credit_pool_check;\n\n\t/* if pool credit is negative - disable the checks */\n\tif (credit >= 0) {\n\t\tp->put = ecore_credit_pool_put;\n\t\tp->get = ecore_credit_pool_get;\n\t\tp->put_entry = ecore_credit_pool_put_entry;\n\t\tp->get_entry = ecore_credit_pool_get_entry;\n\t} else {\n\t\tp->put = ecore_credit_pool_always_TRUE;\n\t\tp->get = ecore_credit_pool_always_TRUE;\n\t\tp->put_entry = ecore_credit_pool_put_entry_always_TRUE;\n\t\tp->get_entry = ecore_credit_pool_get_entry_always_TRUE;\n\t}\n\n\t/* If base is negative - disable entries handling */\n\tif (base < 0) {\n\t\tp->put_entry = ecore_credit_pool_put_entry_always_TRUE;\n\t\tp->get_entry = ecore_credit_pool_get_entry_always_TRUE;\n\t}\n}\n\nvoid ecore_init_mac_credit_pool(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_credit_pool_obj *p,\n\t\t\t\tuint8_t func_id, uint8_t func_num)\n{\n\n#define ECORE_CAM_SIZE_EMUL 5\n\n\tint cam_sz;\n\n\tif (CHIP_IS_E1H(sc)) {\n\t\t/* CAM credit is equally divided between all active functions\n\t\t * on the PORT!.\n\t\t */\n\t\tif ((func_num > 0)) {\n\t\t\tif (!CHIP_REV_IS_SLOW(sc))\n\t\t\t\tcam_sz = (MAX_MAC_CREDIT_E1H / (2 * func_num));\n\t\t\telse\n\t\t\t\tcam_sz = ECORE_CAM_SIZE_EMUL;\n\t\t\tecore_init_credit_pool(p, func_id * cam_sz, cam_sz);\n\t\t} else {\n\t\t\t/* this should never happen! Block MAC operations. */\n\t\t\tecore_init_credit_pool(p, 0, 0);\n\t\t}\n\n\t} else {\n\n\t\t/*\n\t\t * CAM credit is equaly divided between all active functions\n\t\t * on the PATH.\n\t\t */\n\t\tif ((func_num > 0)) {\n\t\t\tif (!CHIP_REV_IS_SLOW(sc))\n\t\t\t\tcam_sz = (MAX_MAC_CREDIT_E2 / func_num);\n\t\t\telse\n\t\t\t\tcam_sz = ECORE_CAM_SIZE_EMUL;\n\n\t\t\t/* No need for CAM entries handling for 57712 and\n\t\t\t * newer.\n\t\t\t */\n\t\t\tecore_init_credit_pool(p, -1, cam_sz);\n\t\t} else {\n\t\t\t/* this should never happen! Block MAC operations. */\n\t\t\tecore_init_credit_pool(p, 0, 0);\n\t\t}\n\t}\n}\n\nvoid ecore_init_vlan_credit_pool(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_credit_pool_obj *p,\n\t\t\t\t uint8_t func_id, uint8_t func_num)\n{\n\tif (CHIP_IS_E1x(sc)) {\n\t\t/* There is no VLAN credit in HW on 57711 only\n\t\t * MAC / MAC-VLAN can be set\n\t\t */\n\t\tecore_init_credit_pool(p, 0, -1);\n\t} else {\n\t\t/* CAM credit is equally divided between all active functions\n\t\t * on the PATH.\n\t\t */\n\t\tif (func_num > 0) {\n\t\t\tint credit = MAX_VLAN_CREDIT_E2 / func_num;\n\t\t\tecore_init_credit_pool(p, func_id * credit, credit);\n\t\t} else\n\t\t\t/* this should never happen! Block VLAN operations. */\n\t\t\tecore_init_credit_pool(p, 0, 0);\n\t}\n}\n\n/****************** RSS Configuration ******************/\n\n/**\n * ecore_setup_rss - configure RSS\n *\n * @sc:\t\tdevice handle\n * @p:\t\trss configuration\n *\n * sends on UPDATE ramrod for that matter.\n */\nstatic int ecore_setup_rss(struct bnx2x_softc *sc,\n\t\t\t struct ecore_config_rss_params *p)\n{\n\tstruct ecore_rss_config_obj *o = p->rss_obj;\n\tstruct ecore_raw_obj *r = &o->raw;\n\tstruct eth_rss_update_ramrod_data *data =\n\t (struct eth_rss_update_ramrod_data *)(r->rdata);\n\tuint8_t rss_mode = 0;\n\tint rc;\n\n\tECORE_MEMSET(data, 0, sizeof(*data));\n\n\tECORE_MSG(\"Configuring RSS\");\n\n\t/* Set an echo field */\n\tdata->echo = ECORE_CPU_TO_LE32((r->cid & ECORE_SWCID_MASK) |\n\t\t\t\t (r->state << ECORE_SWCID_SHIFT));\n\n\t/* RSS mode */\n\tif (ECORE_TEST_BIT(ECORE_RSS_MODE_DISABLED, &p->rss_flags))\n\t\trss_mode = ETH_RSS_MODE_DISABLED;\n\telse if (ECORE_TEST_BIT(ECORE_RSS_MODE_REGULAR, &p->rss_flags))\n\t\trss_mode = ETH_RSS_MODE_REGULAR;\n\n\tdata->rss_mode = rss_mode;\n\n\tECORE_MSG(\"rss_mode=%d\", rss_mode);\n\n\t/* RSS capabilities */\n\tif (ECORE_TEST_BIT(ECORE_RSS_IPV4, &p->rss_flags))\n\t\tdata->capabilities |=\n\t\t ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY;\n\n\tif (ECORE_TEST_BIT(ECORE_RSS_IPV4_TCP, &p->rss_flags))\n\t\tdata->capabilities |=\n\t\t ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY;\n\n\tif (ECORE_TEST_BIT(ECORE_RSS_IPV4_UDP, &p->rss_flags))\n\t\tdata->capabilities |=\n\t\t ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY;\n\n\tif (ECORE_TEST_BIT(ECORE_RSS_IPV6, &p->rss_flags))\n\t\tdata->capabilities |=\n\t\t ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY;\n\n\tif (ECORE_TEST_BIT(ECORE_RSS_IPV6_TCP, &p->rss_flags))\n\t\tdata->capabilities |=\n\t\t ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY;\n\n\tif (ECORE_TEST_BIT(ECORE_RSS_IPV6_UDP, &p->rss_flags))\n\t\tdata->capabilities |=\n\t\t ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;\n\n\tif (ECORE_TEST_BIT(ECORE_RSS_TUNNELING, &p->rss_flags)) {\n\t\tdata->udp_4tuple_dst_port_mask =\n\t\t ECORE_CPU_TO_LE16(p->tunnel_mask);\n\t\tdata->udp_4tuple_dst_port_value =\n\t\t ECORE_CPU_TO_LE16(p->tunnel_value);\n\t}\n\n\t/* Hashing mask */\n\tdata->rss_result_mask = p->rss_result_mask;\n\n\t/* RSS engine ID */\n\tdata->rss_engine_id = o->engine_id;\n\n\tECORE_MSG(\"rss_engine_id=%d\", data->rss_engine_id);\n\n\t/* Indirection table */\n\tECORE_MEMCPY(data->indirection_table, p->ind_table,\n\t\t T_ETH_INDIRECTION_TABLE_SIZE);\n\n\t/* Remember the last configuration */\n\tECORE_MEMCPY(o->ind_table, p->ind_table, T_ETH_INDIRECTION_TABLE_SIZE);\n\n\t/* RSS keys */\n\tif (ECORE_TEST_BIT(ECORE_RSS_SET_SRCH, &p->rss_flags)) {\n\t\tECORE_MEMCPY(&data->rss_key[0], &p->rss_key[0],\n\t\t\t sizeof(data->rss_key));\n\t\tdata->capabilities |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY;\n\t}\n\n\t/* No need for an explicit memory barrier here as long we would\n\t * need to ensure the ordering of writing to the SPQ element\n\t * and updating of the SPQ producer which involves a memory\n\t * read and we will have to put a full memory barrier there\n\t * (inside ecore_sp_post()).\n\t */\n\n\t/* Send a ramrod */\n\trc = ecore_sp_post(sc,\n\t\t\t RAMROD_CMD_ID_ETH_RSS_UPDATE,\n\t\t\t r->cid, r->rdata_mapping, ETH_CONNECTION_TYPE);\n\n\tif (rc < 0)\n\t\treturn rc;\n\n\treturn ECORE_PENDING;\n}\n\nint ecore_config_rss(struct bnx2x_softc *sc, struct ecore_config_rss_params *p)\n{\n\tint rc;\n\tstruct ecore_rss_config_obj *o = p->rss_obj;\n\tstruct ecore_raw_obj *r = &o->raw;\n\n\t/* Do nothing if only driver cleanup was requested */\n\tif (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags))\n\t\treturn ECORE_SUCCESS;\n\n\tr->set_pending(r);\n\n\trc = o->config_rss(sc, p);\n\tif (rc < 0) {\n\t\tr->clear_pending(r);\n\t\treturn rc;\n\t}\n\n\tif (ECORE_TEST_BIT(RAMROD_COMP_WAIT, &p->ramrod_flags))\n\t\trc = r->wait_comp(sc, r);\n\n\treturn rc;\n}\n\nvoid ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,\n\t\t\t uint8_t cl_id, uint32_t cid, uint8_t func_id,\n\t\t\t uint8_t engine_id, void *rdata,\n\t\t\t ecore_dma_addr_t rdata_mapping, int state,\n\t\t\t unsigned long *pstate, ecore_obj_type type)\n{\n\tecore_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata,\n\t\t\t rdata_mapping, state, pstate, type);\n\n\trss_obj->engine_id = engine_id;\n\trss_obj->config_rss = ecore_setup_rss;\n}\n\n/********************** Queue state object ***********************************/\n\n/**\n * ecore_queue_state_change - perform Queue state change transition\n *\n * @sc:\t\tdevice handle\n * @params:\tparameters to perform the transition\n *\n * returns 0 in case of successfully completed transition, negative error\n * code in case of failure, positive (EBUSY) value if there is a completion\n * to that is still pending (possible only if RAMROD_COMP_WAIT is\n * not set in params->ramrod_flags for asynchronous commands).\n *\n */\nint ecore_queue_state_change(struct bnx2x_softc *sc,\n\t\t\t struct ecore_queue_state_params *params)\n{\n\tstruct ecore_queue_sp_obj *o = params->q_obj;\n\tint rc, pending_bit;\n\tunsigned long *pending = &o->pending;\n\n\t/* Check that the requested transition is legal */\n\trc = o->check_transition(sc, o, params);\n\tif (rc) {\n\t\tPMD_DRV_LOG(ERR, \"check transition returned an error. rc %d\",\n\t\t\t rc);\n\t\treturn ECORE_INVAL;\n\t}\n\n\t/* Set \"pending\" bit */\n\tECORE_MSG(\"pending bit was=%lx\", o->pending);\n\tpending_bit = o->set_pending(o, params);\n\tECORE_MSG(\"pending bit now=%lx\", o->pending);\n\n\t/* Don't send a command if only driver cleanup was requested */\n\tif (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags))\n\t\to->complete_cmd(sc, o, pending_bit);\n\telse {\n\t\t/* Send a ramrod */\n\t\trc = o->send_cmd(sc, params);\n\t\tif (rc) {\n\t\t\to->next_state = ECORE_Q_STATE_MAX;\n\t\t\tECORE_CLEAR_BIT(pending_bit, pending);\n\t\t\tECORE_SMP_MB_AFTER_CLEAR_BIT();\n\t\t\treturn rc;\n\t\t}\n\n\t\tif (ECORE_TEST_BIT(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) {\n\t\t\trc = o->wait_comp(sc, o, pending_bit);\n\t\t\tif (rc)\n\t\t\t\treturn rc;\n\n\t\t\treturn ECORE_SUCCESS;\n\t\t}\n\t}\n\n\treturn ECORE_RET_PENDING(pending_bit, pending);\n}\n\nstatic int ecore_queue_set_pending(struct ecore_queue_sp_obj *obj,\n\t\t\t\t struct ecore_queue_state_params *params)\n{\n\tenum ecore_queue_cmd cmd = params->cmd, bit;\n\n\t/* ACTIVATE and DEACTIVATE commands are implemented on top of\n\t * UPDATE command.\n\t */\n\tif ((cmd == ECORE_Q_CMD_ACTIVATE) || (cmd == ECORE_Q_CMD_DEACTIVATE))\n\t\tbit = ECORE_Q_CMD_UPDATE;\n\telse\n\t\tbit = cmd;\n\n\tECORE_SET_BIT(bit, &obj->pending);\n\treturn bit;\n}\n\nstatic int ecore_queue_wait_comp(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_queue_sp_obj *o,\n\t\t\t\t enum ecore_queue_cmd cmd)\n{\n\treturn ecore_state_wait(sc, cmd, &o->pending);\n}\n\n/**\n * ecore_queue_comp_cmd - complete the state change command.\n *\n * @sc:\t\tdevice handle\n * @o:\n * @cmd:\n *\n * Checks that the arrived completion is expected.\n */\nstatic int ecore_queue_comp_cmd(struct bnx2x_softc *sc __rte_unused,\n\t\t\t\tstruct ecore_queue_sp_obj *o,\n\t\t\t\tenum ecore_queue_cmd cmd)\n{\n\tunsigned long cur_pending = o->pending;\n\n\tif (!ECORE_TEST_AND_CLEAR_BIT(cmd, &cur_pending)) {\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\",\n\t\t\t cmd, o->cids[ECORE_PRIMARY_CID_INDEX], o->state,\n\t\t\t cur_pending, o->next_state);\n\t\treturn ECORE_INVAL;\n\t}\n\n\tif (o->next_tx_only >= o->max_cos)\n\t\t/* >= because tx only must always be smaller than cos since the\n\t\t * primary connection supports COS 0\n\t\t */\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"illegal value for next tx_only: %d. max cos was %d\",\n\t\t\t o->next_tx_only, o->max_cos);\n\n\tECORE_MSG(\"Completing command %d for queue %d, setting state to %d\",\n\t\t cmd, o->cids[ECORE_PRIMARY_CID_INDEX], o->next_state);\n\n\tif (o->next_tx_only)\t/* print num tx-only if any exist */\n\t\tECORE_MSG(\"primary cid %d: num tx-only cons %d\",\n\t\t\t o->cids[ECORE_PRIMARY_CID_INDEX], o->next_tx_only);\n\n\to->state = o->next_state;\n\to->num_tx_only = o->next_tx_only;\n\to->next_state = ECORE_Q_STATE_MAX;\n\n\t/* It's important that o->state and o->next_state are\n\t * updated before o->pending.\n\t */\n\twmb();\n\n\tECORE_CLEAR_BIT(cmd, &o->pending);\n\tECORE_SMP_MB_AFTER_CLEAR_BIT();\n\n\treturn ECORE_SUCCESS;\n}\n\nstatic void ecore_q_fill_setup_data_e2(struct ecore_queue_state_params\n\t\t\t\t *cmd_params,\n\t\t\t\t struct client_init_ramrod_data *data)\n{\n\tstruct ecore_queue_setup_params *params = &cmd_params->params.setup;\n\n\t/* Rx data */\n\n\t/* IPv6 TPA supported for E2 and above only */\n\tdata->rx.tpa_en |= ECORE_TEST_BIT(ECORE_Q_FLG_TPA_IPV6,\n\t\t\t\t\t ¶ms->flags) *\n\t CLIENT_INIT_RX_DATA_TPA_EN_IPV6;\n}\n\nstatic void ecore_q_fill_init_general_data(struct bnx2x_softc *sc __rte_unused,\n\t\t\t\t\t struct ecore_queue_sp_obj *o,\n\t\t\t\t\t struct ecore_general_setup_params\n\t\t\t\t\t *params, struct client_init_general_data\n\t\t\t\t\t *gen_data, unsigned long *flags)\n{\n\tgen_data->client_id = o->cl_id;\n\n\tif (ECORE_TEST_BIT(ECORE_Q_FLG_STATS, flags)) {\n\t\tgen_data->statistics_counter_id = params->stat_id;\n\t\tgen_data->statistics_en_flg = 1;\n\t\tgen_data->statistics_zero_flg =\n\t\t ECORE_TEST_BIT(ECORE_Q_FLG_ZERO_STATS, flags);\n\t} else\n\t\tgen_data->statistics_counter_id =\n\t\t DISABLE_STATISTIC_COUNTER_ID_VALUE;\n\n\tgen_data->is_fcoe_flg = ECORE_TEST_BIT(ECORE_Q_FLG_FCOE, flags);\n\tgen_data->activate_flg = ECORE_TEST_BIT(ECORE_Q_FLG_ACTIVE, flags);\n\tgen_data->sp_client_id = params->spcl_id;\n\tgen_data->mtu = ECORE_CPU_TO_LE16(params->mtu);\n\tgen_data->func_id = o->func_id;\n\n\tgen_data->cos = params->cos;\n\n\tgen_data->traffic_type =\n\t ECORE_TEST_BIT(ECORE_Q_FLG_FCOE, flags) ?\n\t LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;\n\n\tECORE_MSG(\"flags: active %d, cos %d, stats en %d\",\n\t\t gen_data->activate_flg, gen_data->cos,\n\t\t gen_data->statistics_en_flg);\n}\n\nstatic void ecore_q_fill_init_tx_data(struct ecore_txq_setup_params *params,\n\t\t\t\t struct client_init_tx_data *tx_data,\n\t\t\t\t unsigned long *flags)\n{\n\ttx_data->enforce_security_flg =\n\t ECORE_TEST_BIT(ECORE_Q_FLG_TX_SEC, flags);\n\ttx_data->default_vlan = ECORE_CPU_TO_LE16(params->default_vlan);\n\ttx_data->default_vlan_flg = ECORE_TEST_BIT(ECORE_Q_FLG_DEF_VLAN, flags);\n\ttx_data->tx_switching_flg =\n\t ECORE_TEST_BIT(ECORE_Q_FLG_TX_SWITCH, flags);\n\ttx_data->anti_spoofing_flg =\n\t ECORE_TEST_BIT(ECORE_Q_FLG_ANTI_SPOOF, flags);\n\ttx_data->force_default_pri_flg =\n\t ECORE_TEST_BIT(ECORE_Q_FLG_FORCE_DEFAULT_PRI, flags);\n\ttx_data->refuse_outband_vlan_flg =\n\t ECORE_TEST_BIT(ECORE_Q_FLG_REFUSE_OUTBAND_VLAN, flags);\n\ttx_data->tunnel_non_lso_pcsum_location =\n\t ECORE_TEST_BIT(ECORE_Q_FLG_PCSUM_ON_PKT, flags) ? CSUM_ON_PKT :\n\t CSUM_ON_BD;\n\n\ttx_data->tx_status_block_id = params->fw_sb_id;\n\ttx_data->tx_sb_index_number = params->sb_cq_index;\n\ttx_data->tss_leading_client_id = params->tss_leading_cl_id;\n\n\ttx_data->tx_bd_page_base.lo =\n\t ECORE_CPU_TO_LE32(U64_LO(params->dscr_map));\n\ttx_data->tx_bd_page_base.hi =\n\t ECORE_CPU_TO_LE32(U64_HI(params->dscr_map));\n\n\t/* Don't configure any Tx switching mode during queue SETUP */\n\ttx_data->state = 0;\n}\n\nstatic void ecore_q_fill_init_pause_data(struct rxq_pause_params *params,\n\t\t\t\t\t struct client_init_rx_data *rx_data)\n{\n\t/* flow control data */\n\trx_data->cqe_pause_thr_low = ECORE_CPU_TO_LE16(params->rcq_th_lo);\n\trx_data->cqe_pause_thr_high = ECORE_CPU_TO_LE16(params->rcq_th_hi);\n\trx_data->bd_pause_thr_low = ECORE_CPU_TO_LE16(params->bd_th_lo);\n\trx_data->bd_pause_thr_high = ECORE_CPU_TO_LE16(params->bd_th_hi);\n\trx_data->sge_pause_thr_low = ECORE_CPU_TO_LE16(params->sge_th_lo);\n\trx_data->sge_pause_thr_high = ECORE_CPU_TO_LE16(params->sge_th_hi);\n\trx_data->rx_cos_mask = ECORE_CPU_TO_LE16(params->pri_map);\n}\n\nstatic void ecore_q_fill_init_rx_data(struct ecore_rxq_setup_params *params,\n\t\t\t\t struct client_init_rx_data *rx_data,\n\t\t\t\t unsigned long *flags)\n{\n\trx_data->tpa_en = ECORE_TEST_BIT(ECORE_Q_FLG_TPA, flags) *\n\t CLIENT_INIT_RX_DATA_TPA_EN_IPV4;\n\trx_data->tpa_en |= ECORE_TEST_BIT(ECORE_Q_FLG_TPA_GRO, flags) *\n\t CLIENT_INIT_RX_DATA_TPA_MODE;\n\trx_data->vmqueue_mode_en_flg = 0;\n\n\trx_data->extra_data_over_sgl_en_flg =\n\t ECORE_TEST_BIT(ECORE_Q_FLG_OOO, flags);\n\trx_data->cache_line_alignment_log_size = params->cache_line_log;\n\trx_data->enable_dynamic_hc = ECORE_TEST_BIT(ECORE_Q_FLG_DHC, flags);\n\trx_data->client_qzone_id = params->cl_qzone_id;\n\trx_data->max_agg_size = ECORE_CPU_TO_LE16(params->tpa_agg_sz);\n\n\t/* Always start in DROP_ALL mode */\n\trx_data->state = ECORE_CPU_TO_LE16(CLIENT_INIT_RX_DATA_UCAST_DROP_ALL |\n\t\t\t\t\t CLIENT_INIT_RX_DATA_MCAST_DROP_ALL);\n\n\t/* We don't set drop flags */\n\trx_data->drop_ip_cs_err_flg = 0;\n\trx_data->drop_tcp_cs_err_flg = 0;\n\trx_data->drop_ttl0_flg = 0;\n\trx_data->drop_udp_cs_err_flg = 0;\n\trx_data->inner_vlan_removal_enable_flg =\n\t ECORE_TEST_BIT(ECORE_Q_FLG_VLAN, flags);\n\trx_data->outer_vlan_removal_enable_flg =\n\t ECORE_TEST_BIT(ECORE_Q_FLG_OV, flags);\n\trx_data->status_block_id = params->fw_sb_id;\n\trx_data->rx_sb_index_number = params->sb_cq_index;\n\trx_data->max_tpa_queues = params->max_tpa_queues;\n\trx_data->max_bytes_on_bd = ECORE_CPU_TO_LE16(params->buf_sz);\n\trx_data->bd_page_base.lo = ECORE_CPU_TO_LE32(U64_LO(params->dscr_map));\n\trx_data->bd_page_base.hi = ECORE_CPU_TO_LE32(U64_HI(params->dscr_map));\n\trx_data->cqe_page_base.lo = ECORE_CPU_TO_LE32(U64_LO(params->rcq_map));\n\trx_data->cqe_page_base.hi = ECORE_CPU_TO_LE32(U64_HI(params->rcq_map));\n\trx_data->is_leading_rss = ECORE_TEST_BIT(ECORE_Q_FLG_LEADING_RSS,\n\t\t\t\t\t\t flags);\n\n\tif (ECORE_TEST_BIT(ECORE_Q_FLG_MCAST, flags)) {\n\t\trx_data->approx_mcast_engine_id = params->mcast_engine_id;\n\t\trx_data->is_approx_mcast = 1;\n\t}\n\n\trx_data->rss_engine_id = params->rss_engine_id;\n\n\t/* silent vlan removal */\n\trx_data->silent_vlan_removal_flg =\n\t ECORE_TEST_BIT(ECORE_Q_FLG_SILENT_VLAN_REM, flags);\n\trx_data->silent_vlan_value =\n\t ECORE_CPU_TO_LE16(params->silent_removal_value);\n\trx_data->silent_vlan_mask =\n\t ECORE_CPU_TO_LE16(params->silent_removal_mask);\n}\n\n/* initialize the general, tx and rx parts of a queue object */\nstatic void ecore_q_fill_setup_data_cmn(struct bnx2x_softc *sc, struct ecore_queue_state_params\n\t\t\t\t\t*cmd_params,\n\t\t\t\t\tstruct client_init_ramrod_data *data)\n{\n\tecore_q_fill_init_general_data(sc, cmd_params->q_obj,\n\t\t\t\t &cmd_params->params.setup.gen_params,\n\t\t\t\t &data->general,\n\t\t\t\t &cmd_params->params.setup.flags);\n\n\tecore_q_fill_init_tx_data(&cmd_params->params.setup.txq_params,\n\t\t\t\t &data->tx, &cmd_params->params.setup.flags);\n\n\tecore_q_fill_init_rx_data(&cmd_params->params.setup.rxq_params,\n\t\t\t\t &data->rx, &cmd_params->params.setup.flags);\n\n\tecore_q_fill_init_pause_data(&cmd_params->params.setup.pause_params,\n\t\t\t\t &data->rx);\n}\n\n/* initialize the general and tx parts of a tx-only queue object */\nstatic void ecore_q_fill_setup_tx_only(struct bnx2x_softc *sc, struct ecore_queue_state_params\n\t\t\t\t *cmd_params,\n\t\t\t\t struct tx_queue_init_ramrod_data *data)\n{\n\tecore_q_fill_init_general_data(sc, cmd_params->q_obj,\n\t\t\t\t &cmd_params->params.tx_only.gen_params,\n\t\t\t\t &data->general,\n\t\t\t\t &cmd_params->params.tx_only.flags);\n\n\tecore_q_fill_init_tx_data(&cmd_params->params.tx_only.txq_params,\n\t\t\t\t &data->tx, &cmd_params->params.tx_only.flags);\n\n\tECORE_MSG(\"cid %d, tx bd page lo %x hi %x\",\n\t\t cmd_params->q_obj->cids[0],\n\t\t data->tx.tx_bd_page_base.lo, data->tx.tx_bd_page_base.hi);\n}\n\n/**\n * ecore_q_init - init HW/FW queue\n *\n * @sc:\t\tdevice handle\n * @params:\n *\n * HW/FW initial Queue configuration:\n * - HC: Rx and Tx\n * - CDU context validation\n *\n */\nstatic int ecore_q_init(struct bnx2x_softc *sc,\n\t\t\tstruct ecore_queue_state_params *params)\n{\n\tstruct ecore_queue_sp_obj *o = params->q_obj;\n\tstruct ecore_queue_init_params *init = ¶ms->params.init;\n\tuint16_t hc_usec;\n\tuint8_t cos;\n\n\t/* Tx HC configuration */\n\tif (ECORE_TEST_BIT(ECORE_Q_TYPE_HAS_TX, &o->type) &&\n\t ECORE_TEST_BIT(ECORE_Q_FLG_HC, &init->tx.flags)) {\n\t\thc_usec = init->tx.hc_rate ? 1000000 / init->tx.hc_rate : 0;\n\n\t\tECORE_UPDATE_COALESCE_SB_INDEX(sc, init->tx.fw_sb_id,\n\t\t\t\t\t init->tx.sb_cq_index,\n\t\t\t\t\t !ECORE_TEST_BIT\n\t\t\t\t\t (ECORE_Q_FLG_HC_EN,\n\t\t\t\t\t\t&init->tx.flags), hc_usec);\n\t}\n\n\t/* Rx HC configuration */\n\tif (ECORE_TEST_BIT(ECORE_Q_TYPE_HAS_RX, &o->type) &&\n\t ECORE_TEST_BIT(ECORE_Q_FLG_HC, &init->rx.flags)) {\n\t\thc_usec = init->rx.hc_rate ? 1000000 / init->rx.hc_rate : 0;\n\n\t\tECORE_UPDATE_COALESCE_SB_INDEX(sc, init->rx.fw_sb_id,\n\t\t\t\t\t init->rx.sb_cq_index,\n\t\t\t\t\t !ECORE_TEST_BIT\n\t\t\t\t\t (ECORE_Q_FLG_HC_EN,\n\t\t\t\t\t\t&init->rx.flags), hc_usec);\n\t}\n\n\t/* Set CDU context validation values */\n\tfor (cos = 0; cos < o->max_cos; cos++) {\n\t\tECORE_MSG(\"setting context validation. cid %d, cos %d\",\n\t\t\t o->cids[cos], cos);\n\t\tECORE_MSG(\"context pointer %p\", init->cxts[cos]);\n\t\tECORE_SET_CTX_VALIDATION(sc, init->cxts[cos], o->cids[cos]);\n\t}\n\n\t/* As no ramrod is sent, complete the command immediately */\n\to->complete_cmd(sc, o, ECORE_Q_CMD_INIT);\n\n\tECORE_MMIOWB();\n\tECORE_SMP_MB();\n\n\treturn ECORE_SUCCESS;\n}\n\nstatic int ecore_q_send_setup_e1x(struct bnx2x_softc *sc, struct ecore_queue_state_params\n\t\t\t\t *params)\n{\n\tstruct ecore_queue_sp_obj *o = params->q_obj;\n\tstruct client_init_ramrod_data *rdata =\n\t (struct client_init_ramrod_data *)o->rdata;\n\tecore_dma_addr_t data_mapping = o->rdata_mapping;\n\tint ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;\n\n\t/* Clear the ramrod data */\n\tECORE_MEMSET(rdata, 0, sizeof(*rdata));\n\n\t/* Fill the ramrod data */\n\tecore_q_fill_setup_data_cmn(sc, params, rdata);\n\n\t/* No need for an explicit memory barrier here as long we would\n\t * need to ensure the ordering of writing to the SPQ element\n\t * and updating of the SPQ producer which involves a memory\n\t * read and we will have to put a full memory barrier there\n\t * (inside ecore_sp_post()).\n\t */\n\n\treturn ecore_sp_post(sc,\n\t\t\t ramrod,\n\t\t\t o->cids[ECORE_PRIMARY_CID_INDEX],\n\t\t\t data_mapping, ETH_CONNECTION_TYPE);\n}\n\nstatic int ecore_q_send_setup_e2(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_queue_state_params *params)\n{\n\tstruct ecore_queue_sp_obj *o = params->q_obj;\n\tstruct client_init_ramrod_data *rdata =\n\t (struct client_init_ramrod_data *)o->rdata;\n\tecore_dma_addr_t data_mapping = o->rdata_mapping;\n\tint ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;\n\n\t/* Clear the ramrod data */\n\tECORE_MEMSET(rdata, 0, sizeof(*rdata));\n\n\t/* Fill the ramrod data */\n\tecore_q_fill_setup_data_cmn(sc, params, rdata);\n\tecore_q_fill_setup_data_e2(params, rdata);\n\n\t/* No need for an explicit memory barrier here as long we would\n\t * need to ensure the ordering of writing to the SPQ element\n\t * and updating of the SPQ producer which involves a memory\n\t * read and we will have to put a full memory barrier there\n\t * (inside ecore_sp_post()).\n\t */\n\n\treturn ecore_sp_post(sc,\n\t\t\t ramrod,\n\t\t\t o->cids[ECORE_PRIMARY_CID_INDEX],\n\t\t\t data_mapping, ETH_CONNECTION_TYPE);\n}\n\nstatic int ecore_q_send_setup_tx_only(struct bnx2x_softc *sc, struct ecore_queue_state_params\n\t\t\t\t *params)\n{\n\tstruct ecore_queue_sp_obj *o = params->q_obj;\n\tstruct tx_queue_init_ramrod_data *rdata =\n\t (struct tx_queue_init_ramrod_data *)o->rdata;\n\tecore_dma_addr_t data_mapping = o->rdata_mapping;\n\tint ramrod = RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP;\n\tstruct ecore_queue_setup_tx_only_params *tx_only_params =\n\t ¶ms->params.tx_only;\n\tuint8_t cid_index = tx_only_params->cid_index;\n\n\tif (ECORE_TEST_BIT(ECORE_Q_TYPE_FWD, &o->type))\n\t\tramrod = RAMROD_CMD_ID_ETH_FORWARD_SETUP;\n\tECORE_MSG(\"sending forward tx-only ramrod\");\n\n\tif (cid_index >= o->max_cos) {\n\t\tPMD_DRV_LOG(ERR, \"queue[%d]: cid_index (%d) is out of range\",\n\t\t\t o->cl_id, cid_index);\n\t\treturn ECORE_INVAL;\n\t}\n\n\tECORE_MSG(\"parameters received: cos: %d sp-id: %d\",\n\t\t tx_only_params->gen_params.cos,\n\t\t tx_only_params->gen_params.spcl_id);\n\n\t/* Clear the ramrod data */\n\tECORE_MEMSET(rdata, 0, sizeof(*rdata));\n\n\t/* Fill the ramrod data */\n\tecore_q_fill_setup_tx_only(sc, params, rdata);\n\n\tECORE_MSG\n\t (\"sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\",\n\t o->cids[cid_index], rdata->general.client_id,\n\t rdata->general.sp_client_id, rdata->general.cos);\n\n\t/* No need for an explicit memory barrier here as long we would\n\t * need to ensure the ordering of writing to the SPQ element\n\t * and updating of the SPQ producer which involves a memory\n\t * read and we will have to put a full memory barrier there\n\t * (inside ecore_sp_post()).\n\t */\n\n\treturn ecore_sp_post(sc, ramrod, o->cids[cid_index],\n\t\t\t data_mapping, ETH_CONNECTION_TYPE);\n}\n\nstatic void ecore_q_fill_update_data(struct ecore_queue_sp_obj *obj,\n\t\t\t\t struct ecore_queue_update_params *params,\n\t\t\t\t struct client_update_ramrod_data *data)\n{\n\t/* Client ID of the client to update */\n\tdata->client_id = obj->cl_id;\n\n\t/* Function ID of the client to update */\n\tdata->func_id = obj->func_id;\n\n\t/* Default VLAN value */\n\tdata->default_vlan = ECORE_CPU_TO_LE16(params->def_vlan);\n\n\t/* Inner VLAN stripping */\n\tdata->inner_vlan_removal_enable_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_IN_VLAN_REM, ¶ms->update_flags);\n\tdata->inner_vlan_removal_change_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_IN_VLAN_REM_CHNG,\n\t\t\t ¶ms->update_flags);\n\n\t/* Outer VLAN stripping */\n\tdata->outer_vlan_removal_enable_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_OUT_VLAN_REM, ¶ms->update_flags);\n\tdata->outer_vlan_removal_change_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG,\n\t\t\t ¶ms->update_flags);\n\n\t/* Drop packets that have source MAC that doesn't belong to this\n\t * Queue.\n\t */\n\tdata->anti_spoofing_enable_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_ANTI_SPOOF, ¶ms->update_flags);\n\tdata->anti_spoofing_change_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_ANTI_SPOOF_CHNG,\n\t\t\t ¶ms->update_flags);\n\n\t/* Activate/Deactivate */\n\tdata->activate_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE, ¶ms->update_flags);\n\tdata->activate_change_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE_CHNG, ¶ms->update_flags);\n\n\t/* Enable default VLAN */\n\tdata->default_vlan_enable_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_DEF_VLAN_EN, ¶ms->update_flags);\n\tdata->default_vlan_change_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG,\n\t\t\t ¶ms->update_flags);\n\n\t/* silent vlan removal */\n\tdata->silent_vlan_change_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG,\n\t\t\t ¶ms->update_flags);\n\tdata->silent_vlan_removal_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_SILENT_VLAN_REM,\n\t\t\t ¶ms->update_flags);\n\tdata->silent_vlan_value =\n\t ECORE_CPU_TO_LE16(params->silent_removal_value);\n\tdata->silent_vlan_mask = ECORE_CPU_TO_LE16(params->silent_removal_mask);\n\n\t/* tx switching */\n\tdata->tx_switching_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_TX_SWITCHING, ¶ms->update_flags);\n\tdata->tx_switching_change_flg =\n\t ECORE_TEST_BIT(ECORE_Q_UPDATE_TX_SWITCHING_CHNG,\n\t\t\t ¶ms->update_flags);\n}\n\nstatic int ecore_q_send_update(struct bnx2x_softc *sc,\n\t\t\t struct ecore_queue_state_params *params)\n{\n\tstruct ecore_queue_sp_obj *o = params->q_obj;\n\tstruct client_update_ramrod_data *rdata =\n\t (struct client_update_ramrod_data *)o->rdata;\n\tecore_dma_addr_t data_mapping = o->rdata_mapping;\n\tstruct ecore_queue_update_params *update_params =\n\t ¶ms->params.update;\n\tuint8_t cid_index = update_params->cid_index;\n\n\tif (cid_index >= o->max_cos) {\n\t\tPMD_DRV_LOG(ERR, \"queue[%d]: cid_index (%d) is out of range\",\n\t\t\t o->cl_id, cid_index);\n\t\treturn ECORE_INVAL;\n\t}\n\n\t/* Clear the ramrod data */\n\tECORE_MEMSET(rdata, 0, sizeof(*rdata));\n\n\t/* Fill the ramrod data */\n\tecore_q_fill_update_data(o, update_params, rdata);\n\n\t/* No need for an explicit memory barrier here as long we would\n\t * need to ensure the ordering of writing to the SPQ element\n\t * and updating of the SPQ producer which involves a memory\n\t * read and we will have to put a full memory barrier there\n\t * (inside ecore_sp_post()).\n\t */\n\n\treturn ecore_sp_post(sc, RAMROD_CMD_ID_ETH_CLIENT_UPDATE,\n\t\t\t o->cids[cid_index], data_mapping,\n\t\t\t ETH_CONNECTION_TYPE);\n}\n\n/**\n * ecore_q_send_deactivate - send DEACTIVATE command\n *\n * @sc:\t\tdevice handle\n * @params:\n *\n * implemented using the UPDATE command.\n */\nstatic int ecore_q_send_deactivate(struct bnx2x_softc *sc, struct ecore_queue_state_params\n\t\t\t\t *params)\n{\n\tstruct ecore_queue_update_params *update = ¶ms->params.update;\n\n\tECORE_MEMSET(update, 0, sizeof(*update));\n\n\tECORE_SET_BIT_NA(ECORE_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags);\n\n\treturn ecore_q_send_update(sc, params);\n}\n\n/**\n * ecore_q_send_activate - send ACTIVATE command\n *\n * @sc:\t\tdevice handle\n * @params:\n *\n * implemented using the UPDATE command.\n */\nstatic int ecore_q_send_activate(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_queue_state_params *params)\n{\n\tstruct ecore_queue_update_params *update = ¶ms->params.update;\n\n\tECORE_MEMSET(update, 0, sizeof(*update));\n\n\tECORE_SET_BIT_NA(ECORE_Q_UPDATE_ACTIVATE, &update->update_flags);\n\tECORE_SET_BIT_NA(ECORE_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags);\n\n\treturn ecore_q_send_update(sc, params);\n}\n\nstatic int ecore_q_send_update_tpa(__rte_unused struct bnx2x_softc *sc,\n\t\t\t\t __rte_unused struct\n\t\t\t\t ecore_queue_state_params *params)\n{\n\t/* Not implemented yet. */\n\treturn -1;\n}\n\nstatic int ecore_q_send_halt(struct bnx2x_softc *sc,\n\t\t\t struct ecore_queue_state_params *params)\n{\n\tstruct ecore_queue_sp_obj *o = params->q_obj;\n\n\t/* build eth_halt_ramrod_data.client_id in a big-endian friendly way */\n\tecore_dma_addr_t data_mapping = 0;\n\tdata_mapping = (ecore_dma_addr_t) o->cl_id;\n\n\treturn ecore_sp_post(sc,\n\t\t\t RAMROD_CMD_ID_ETH_HALT,\n\t\t\t o->cids[ECORE_PRIMARY_CID_INDEX],\n\t\t\t data_mapping, ETH_CONNECTION_TYPE);\n}\n\nstatic int ecore_q_send_cfc_del(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_queue_state_params *params)\n{\n\tstruct ecore_queue_sp_obj *o = params->q_obj;\n\tuint8_t cid_idx = params->params.cfc_del.cid_index;\n\n\tif (cid_idx >= o->max_cos) {\n\t\tPMD_DRV_LOG(ERR, \"queue[%d]: cid_index (%d) is out of range\",\n\t\t\t o->cl_id, cid_idx);\n\t\treturn ECORE_INVAL;\n\t}\n\n\treturn ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_CFC_DEL,\n\t\t\t o->cids[cid_idx], 0, NONE_CONNECTION_TYPE);\n}\n\nstatic int ecore_q_send_terminate(struct bnx2x_softc *sc, struct ecore_queue_state_params\n\t\t\t\t *params)\n{\n\tstruct ecore_queue_sp_obj *o = params->q_obj;\n\tuint8_t cid_index = params->params.terminate.cid_index;\n\n\tif (cid_index >= o->max_cos) {\n\t\tPMD_DRV_LOG(ERR, \"queue[%d]: cid_index (%d) is out of range\",\n\t\t\t o->cl_id, cid_index);\n\t\treturn ECORE_INVAL;\n\t}\n\n\treturn ecore_sp_post(sc, RAMROD_CMD_ID_ETH_TERMINATE,\n\t\t\t o->cids[cid_index], 0, ETH_CONNECTION_TYPE);\n}\n\nstatic int ecore_q_send_empty(struct bnx2x_softc *sc,\n\t\t\t struct ecore_queue_state_params *params)\n{\n\tstruct ecore_queue_sp_obj *o = params->q_obj;\n\n\treturn ecore_sp_post(sc, RAMROD_CMD_ID_ETH_EMPTY,\n\t\t\t o->cids[ECORE_PRIMARY_CID_INDEX], 0,\n\t\t\t ETH_CONNECTION_TYPE);\n}\n\nstatic int ecore_queue_send_cmd_cmn(struct bnx2x_softc *sc, struct ecore_queue_state_params\n\t\t\t\t *params)\n{\n\tswitch (params->cmd) {\n\tcase ECORE_Q_CMD_INIT:\n\t\treturn ecore_q_init(sc, params);\n\tcase ECORE_Q_CMD_SETUP_TX_ONLY:\n\t\treturn ecore_q_send_setup_tx_only(sc, params);\n\tcase ECORE_Q_CMD_DEACTIVATE:\n\t\treturn ecore_q_send_deactivate(sc, params);\n\tcase ECORE_Q_CMD_ACTIVATE:\n\t\treturn ecore_q_send_activate(sc, params);\n\tcase ECORE_Q_CMD_UPDATE:\n\t\treturn ecore_q_send_update(sc, params);\n\tcase ECORE_Q_CMD_UPDATE_TPA:\n\t\treturn ecore_q_send_update_tpa(sc, params);\n\tcase ECORE_Q_CMD_HALT:\n\t\treturn ecore_q_send_halt(sc, params);\n\tcase ECORE_Q_CMD_CFC_DEL:\n\t\treturn ecore_q_send_cfc_del(sc, params);\n\tcase ECORE_Q_CMD_TERMINATE:\n\t\treturn ecore_q_send_terminate(sc, params);\n\tcase ECORE_Q_CMD_EMPTY:\n\t\treturn ecore_q_send_empty(sc, params);\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Unknown command: %d\", params->cmd);\n\t\treturn ECORE_INVAL;\n\t}\n}\n\nstatic int ecore_queue_send_cmd_e1x(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_queue_state_params *params)\n{\n\tswitch (params->cmd) {\n\tcase ECORE_Q_CMD_SETUP:\n\t\treturn ecore_q_send_setup_e1x(sc, params);\n\tcase ECORE_Q_CMD_INIT:\n\tcase ECORE_Q_CMD_SETUP_TX_ONLY:\n\tcase ECORE_Q_CMD_DEACTIVATE:\n\tcase ECORE_Q_CMD_ACTIVATE:\n\tcase ECORE_Q_CMD_UPDATE:\n\tcase ECORE_Q_CMD_UPDATE_TPA:\n\tcase ECORE_Q_CMD_HALT:\n\tcase ECORE_Q_CMD_CFC_DEL:\n\tcase ECORE_Q_CMD_TERMINATE:\n\tcase ECORE_Q_CMD_EMPTY:\n\t\treturn ecore_queue_send_cmd_cmn(sc, params);\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Unknown command: %d\", params->cmd);\n\t\treturn ECORE_INVAL;\n\t}\n}\n\nstatic int ecore_queue_send_cmd_e2(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_queue_state_params *params)\n{\n\tswitch (params->cmd) {\n\tcase ECORE_Q_CMD_SETUP:\n\t\treturn ecore_q_send_setup_e2(sc, params);\n\tcase ECORE_Q_CMD_INIT:\n\tcase ECORE_Q_CMD_SETUP_TX_ONLY:\n\tcase ECORE_Q_CMD_DEACTIVATE:\n\tcase ECORE_Q_CMD_ACTIVATE:\n\tcase ECORE_Q_CMD_UPDATE:\n\tcase ECORE_Q_CMD_UPDATE_TPA:\n\tcase ECORE_Q_CMD_HALT:\n\tcase ECORE_Q_CMD_CFC_DEL:\n\tcase ECORE_Q_CMD_TERMINATE:\n\tcase ECORE_Q_CMD_EMPTY:\n\t\treturn ecore_queue_send_cmd_cmn(sc, params);\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Unknown command: %d\", params->cmd);\n\t\treturn ECORE_INVAL;\n\t}\n}\n\n/**\n * ecore_queue_chk_transition - check state machine of a regular Queue\n *\n * @sc:\t\tdevice handle\n * @o:\n * @params:\n *\n * (not Forwarding)\n * It both checks if the requested command is legal in a current\n * state and, if it's legal, sets a `next_state' in the object\n * that will be used in the completion flow to set the `state'\n * of the object.\n *\n * returns 0 if a requested command is a legal transition,\n * ECORE_INVAL otherwise.\n */\nstatic int ecore_queue_chk_transition(struct bnx2x_softc *sc __rte_unused,\n\t\t\t\t struct ecore_queue_sp_obj *o,\n\t\t\t\t struct ecore_queue_state_params *params)\n{\n\tenum ecore_q_state state = o->state, next_state = ECORE_Q_STATE_MAX;\n\tenum ecore_queue_cmd cmd = params->cmd;\n\tstruct ecore_queue_update_params *update_params =\n\t ¶ms->params.update;\n\tuint8_t next_tx_only = o->num_tx_only;\n\n\t/* Forget all pending for completion commands if a driver only state\n\t * transition has been requested.\n\t */\n\tif (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) {\n\t\to->pending = 0;\n\t\to->next_state = ECORE_Q_STATE_MAX;\n\t}\n\n\t/* Don't allow a next state transition if we are in the middle of\n\t * the previous one.\n\t */\n\tif (o->pending) {\n\t\tPMD_DRV_LOG(ERR, \"Blocking transition since pending was %lx\",\n\t\t\t o->pending);\n\t\treturn ECORE_BUSY;\n\t}\n\n\tswitch (state) {\n\tcase ECORE_Q_STATE_RESET:\n\t\tif (cmd == ECORE_Q_CMD_INIT)\n\t\t\tnext_state = ECORE_Q_STATE_INITIALIZED;\n\n\t\tbreak;\n\tcase ECORE_Q_STATE_INITIALIZED:\n\t\tif (cmd == ECORE_Q_CMD_SETUP) {\n\t\t\tif (ECORE_TEST_BIT(ECORE_Q_FLG_ACTIVE,\n\t\t\t\t\t ¶ms->params.setup.flags))\n\t\t\t\tnext_state = ECORE_Q_STATE_ACTIVE;\n\t\t\telse\n\t\t\t\tnext_state = ECORE_Q_STATE_INACTIVE;\n\t\t}\n\n\t\tbreak;\n\tcase ECORE_Q_STATE_ACTIVE:\n\t\tif (cmd == ECORE_Q_CMD_DEACTIVATE)\n\t\t\tnext_state = ECORE_Q_STATE_INACTIVE;\n\n\t\telse if ((cmd == ECORE_Q_CMD_EMPTY) ||\n\t\t\t (cmd == ECORE_Q_CMD_UPDATE_TPA))\n\t\t\tnext_state = ECORE_Q_STATE_ACTIVE;\n\n\t\telse if (cmd == ECORE_Q_CMD_SETUP_TX_ONLY) {\n\t\t\tnext_state = ECORE_Q_STATE_MULTI_COS;\n\t\t\tnext_tx_only = 1;\n\t\t}\n\n\t\telse if (cmd == ECORE_Q_CMD_HALT)\n\t\t\tnext_state = ECORE_Q_STATE_STOPPED;\n\n\t\telse if (cmd == ECORE_Q_CMD_UPDATE) {\n\t\t\t/* If \"active\" state change is requested, update the\n\t\t\t * state accordingly.\n\t\t\t */\n\t\t\tif (ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE_CHNG,\n\t\t\t\t\t &update_params->update_flags) &&\n\t\t\t !ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE,\n\t\t\t\t\t &update_params->update_flags))\n\t\t\t\tnext_state = ECORE_Q_STATE_INACTIVE;\n\t\t\telse\n\t\t\t\tnext_state = ECORE_Q_STATE_ACTIVE;\n\t\t}\n\n\t\tbreak;\n\tcase ECORE_Q_STATE_MULTI_COS:\n\t\tif (cmd == ECORE_Q_CMD_TERMINATE)\n\t\t\tnext_state = ECORE_Q_STATE_MCOS_TERMINATED;\n\n\t\telse if (cmd == ECORE_Q_CMD_SETUP_TX_ONLY) {\n\t\t\tnext_state = ECORE_Q_STATE_MULTI_COS;\n\t\t\tnext_tx_only = o->num_tx_only + 1;\n\t\t}\n\n\t\telse if ((cmd == ECORE_Q_CMD_EMPTY) ||\n\t\t\t (cmd == ECORE_Q_CMD_UPDATE_TPA))\n\t\t\tnext_state = ECORE_Q_STATE_MULTI_COS;\n\n\t\telse if (cmd == ECORE_Q_CMD_UPDATE) {\n\t\t\t/* If \"active\" state change is requested, update the\n\t\t\t * state accordingly.\n\t\t\t */\n\t\t\tif (ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE_CHNG,\n\t\t\t\t\t &update_params->update_flags) &&\n\t\t\t !ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE,\n\t\t\t\t\t &update_params->update_flags))\n\t\t\t\tnext_state = ECORE_Q_STATE_INACTIVE;\n\t\t\telse\n\t\t\t\tnext_state = ECORE_Q_STATE_MULTI_COS;\n\t\t}\n\n\t\tbreak;\n\tcase ECORE_Q_STATE_MCOS_TERMINATED:\n\t\tif (cmd == ECORE_Q_CMD_CFC_DEL) {\n\t\t\tnext_tx_only = o->num_tx_only - 1;\n\t\t\tif (next_tx_only == 0)\n\t\t\t\tnext_state = ECORE_Q_STATE_ACTIVE;\n\t\t\telse\n\t\t\t\tnext_state = ECORE_Q_STATE_MULTI_COS;\n\t\t}\n\n\t\tbreak;\n\tcase ECORE_Q_STATE_INACTIVE:\n\t\tif (cmd == ECORE_Q_CMD_ACTIVATE)\n\t\t\tnext_state = ECORE_Q_STATE_ACTIVE;\n\n\t\telse if ((cmd == ECORE_Q_CMD_EMPTY) ||\n\t\t\t (cmd == ECORE_Q_CMD_UPDATE_TPA))\n\t\t\tnext_state = ECORE_Q_STATE_INACTIVE;\n\n\t\telse if (cmd == ECORE_Q_CMD_HALT)\n\t\t\tnext_state = ECORE_Q_STATE_STOPPED;\n\n\t\telse if (cmd == ECORE_Q_CMD_UPDATE) {\n\t\t\t/* If \"active\" state change is requested, update the\n\t\t\t * state accordingly.\n\t\t\t */\n\t\t\tif (ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE_CHNG,\n\t\t\t\t\t &update_params->update_flags) &&\n\t\t\t ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE,\n\t\t\t\t\t &update_params->update_flags)) {\n\t\t\t\tif (o->num_tx_only == 0)\n\t\t\t\t\tnext_state = ECORE_Q_STATE_ACTIVE;\n\t\t\t\telse\t/* tx only queues exist for this queue */\n\t\t\t\t\tnext_state = ECORE_Q_STATE_MULTI_COS;\n\t\t\t} else\n\t\t\t\tnext_state = ECORE_Q_STATE_INACTIVE;\n\t\t}\n\n\t\tbreak;\n\tcase ECORE_Q_STATE_STOPPED:\n\t\tif (cmd == ECORE_Q_CMD_TERMINATE)\n\t\t\tnext_state = ECORE_Q_STATE_TERMINATED;\n\n\t\tbreak;\n\tcase ECORE_Q_STATE_TERMINATED:\n\t\tif (cmd == ECORE_Q_CMD_CFC_DEL)\n\t\t\tnext_state = ECORE_Q_STATE_RESET;\n\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Illegal state: %d\", state);\n\t}\n\n\t/* Transition is assured */\n\tif (next_state != ECORE_Q_STATE_MAX) {\n\t\tECORE_MSG(\"Good state transition: %d(%d)->%d\",\n\t\t\t state, cmd, next_state);\n\t\to->next_state = next_state;\n\t\to->next_tx_only = next_tx_only;\n\t\treturn ECORE_SUCCESS;\n\t}\n\n\tECORE_MSG(\"Bad state transition request: %d %d\", state, cmd);\n\n\treturn ECORE_INVAL;\n}\n\n/**\n * ecore_queue_chk_fwd_transition - check state machine of a Forwarding Queue.\n *\n * @sc:\t\tdevice handle\n * @o:\n * @params:\n *\n * It both checks if the requested command is legal in a current\n * state and, if it's legal, sets a `next_state' in the object\n * that will be used in the completion flow to set the `state'\n * of the object.\n *\n * returns 0 if a requested command is a legal transition,\n * ECORE_INVAL otherwise.\n */\nstatic int ecore_queue_chk_fwd_transition(struct bnx2x_softc *sc __rte_unused,\n\t\t\t\t\t struct ecore_queue_sp_obj *o,\n\t\t\t\t\t struct ecore_queue_state_params\n\t\t\t\t\t *params)\n{\n\tenum ecore_q_state state = o->state, next_state = ECORE_Q_STATE_MAX;\n\tenum ecore_queue_cmd cmd = params->cmd;\n\n\tswitch (state) {\n\tcase ECORE_Q_STATE_RESET:\n\t\tif (cmd == ECORE_Q_CMD_INIT)\n\t\t\tnext_state = ECORE_Q_STATE_INITIALIZED;\n\n\t\tbreak;\n\tcase ECORE_Q_STATE_INITIALIZED:\n\t\tif (cmd == ECORE_Q_CMD_SETUP_TX_ONLY) {\n\t\t\tif (ECORE_TEST_BIT(ECORE_Q_FLG_ACTIVE,\n\t\t\t\t\t ¶ms->params.tx_only.flags))\n\t\t\t\tnext_state = ECORE_Q_STATE_ACTIVE;\n\t\t\telse\n\t\t\t\tnext_state = ECORE_Q_STATE_INACTIVE;\n\t\t}\n\n\t\tbreak;\n\tcase ECORE_Q_STATE_ACTIVE:\n\tcase ECORE_Q_STATE_INACTIVE:\n\t\tif (cmd == ECORE_Q_CMD_CFC_DEL)\n\t\t\tnext_state = ECORE_Q_STATE_RESET;\n\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Illegal state: %d\", state);\n\t}\n\n\t/* Transition is assured */\n\tif (next_state != ECORE_Q_STATE_MAX) {\n\t\tECORE_MSG(\"Good state transition: %d(%d)->%d\",\n\t\t\t state, cmd, next_state);\n\t\to->next_state = next_state;\n\t\treturn ECORE_SUCCESS;\n\t}\n\n\tECORE_MSG(\"Bad state transition request: %d %d\", state, cmd);\n\treturn ECORE_INVAL;\n}\n\nvoid ecore_init_queue_obj(struct bnx2x_softc *sc,\n\t\t\t struct ecore_queue_sp_obj *obj,\n\t\t\t uint8_t cl_id, uint32_t * cids, uint8_t cid_cnt,\n\t\t\t uint8_t func_id, void *rdata,\n\t\t\t ecore_dma_addr_t rdata_mapping, unsigned long type)\n{\n\tECORE_MEMSET(obj, 0, sizeof(*obj));\n\n\t/* We support only ECORE_MULTI_TX_COS Tx CoS at the moment */\n\tECORE_BUG_ON(ECORE_MULTI_TX_COS < cid_cnt);\n\n\trte_memcpy(obj->cids, cids, sizeof(obj->cids[0]) * cid_cnt);\n\tobj->max_cos = cid_cnt;\n\tobj->cl_id = cl_id;\n\tobj->func_id = func_id;\n\tobj->rdata = rdata;\n\tobj->rdata_mapping = rdata_mapping;\n\tobj->type = type;\n\tobj->next_state = ECORE_Q_STATE_MAX;\n\n\tif (CHIP_IS_E1x(sc))\n\t\tobj->send_cmd = ecore_queue_send_cmd_e1x;\n\telse\n\t\tobj->send_cmd = ecore_queue_send_cmd_e2;\n\n\tif (ECORE_TEST_BIT(ECORE_Q_TYPE_FWD, &type))\n\t\tobj->check_transition = ecore_queue_chk_fwd_transition;\n\telse\n\t\tobj->check_transition = ecore_queue_chk_transition;\n\n\tobj->complete_cmd = ecore_queue_comp_cmd;\n\tobj->wait_comp = ecore_queue_wait_comp;\n\tobj->set_pending = ecore_queue_set_pending;\n}\n\n/********************** Function state object *********************************/\nenum ecore_func_state ecore_func_get_state(__rte_unused struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_func_sp_obj *o)\n{\n\t/* in the middle of transaction - return INVALID state */\n\tif (o->pending)\n\t\treturn ECORE_F_STATE_MAX;\n\n\t/* unsure the order of reading of o->pending and o->state\n\t * o->pending should be read first\n\t */\n\trmb();\n\n\treturn o->state;\n}\n\nstatic int ecore_func_wait_comp(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_func_sp_obj *o,\n\t\t\t\tenum ecore_func_cmd cmd)\n{\n\treturn ecore_state_wait(sc, cmd, &o->pending);\n}\n\n/**\n * ecore_func_state_change_comp - complete the state machine transition\n *\n * @sc:\t\tdevice handle\n * @o:\n * @cmd:\n *\n * Called on state change transition. Completes the state\n * machine transition only - no HW interaction.\n */\nstatic int\necore_func_state_change_comp(struct bnx2x_softc *sc __rte_unused,\n\t\t\t struct ecore_func_sp_obj *o,\n\t\t\t enum ecore_func_cmd cmd)\n{\n\tunsigned long cur_pending = o->pending;\n\n\tif (!ECORE_TEST_AND_CLEAR_BIT(cmd, &cur_pending)) {\n\t\tPMD_DRV_LOG(ERR,\n\t\t\t \"Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\",\n\t\t\t cmd, ECORE_FUNC_ID(sc), o->state, cur_pending,\n\t\t\t o->next_state);\n\t\treturn ECORE_INVAL;\n\t}\n\n\tECORE_MSG(\"Completing command %d for func %d, setting state to %d\",\n\t\t cmd, ECORE_FUNC_ID(sc), o->next_state);\n\n\to->state = o->next_state;\n\to->next_state = ECORE_F_STATE_MAX;\n\n\t/* It's important that o->state and o->next_state are\n\t * updated before o->pending.\n\t */\n\twmb();\n\n\tECORE_CLEAR_BIT(cmd, &o->pending);\n\tECORE_SMP_MB_AFTER_CLEAR_BIT();\n\n\treturn ECORE_SUCCESS;\n}\n\n/**\n * ecore_func_comp_cmd - complete the state change command\n *\n * @sc:\t\tdevice handle\n * @o:\n * @cmd:\n *\n * Checks that the arrived completion is expected.\n */\nstatic int ecore_func_comp_cmd(struct bnx2x_softc *sc,\n\t\t\t struct ecore_func_sp_obj *o,\n\t\t\t enum ecore_func_cmd cmd)\n{\n\t/* Complete the state machine part first, check if it's a\n\t * legal completion.\n\t */\n\tint rc = ecore_func_state_change_comp(sc, o, cmd);\n\treturn rc;\n}\n\n/**\n * ecore_func_chk_transition - perform function state machine transition\n *\n * @sc:\t\tdevice handle\n * @o:\n * @params:\n *\n * It both checks if the requested command is legal in a current\n * state and, if it's legal, sets a `next_state' in the object\n * that will be used in the completion flow to set the `state'\n * of the object.\n *\n * returns 0 if a requested command is a legal transition,\n * ECORE_INVAL otherwise.\n */\nstatic int ecore_func_chk_transition(struct bnx2x_softc *sc __rte_unused,\n\t\t\t\t struct ecore_func_sp_obj *o,\n\t\t\t\t struct ecore_func_state_params *params)\n{\n\tenum ecore_func_state state = o->state, next_state = ECORE_F_STATE_MAX;\n\tenum ecore_func_cmd cmd = params->cmd;\n\n\t/* Forget all pending for completion commands if a driver only state\n\t * transition has been requested.\n\t */\n\tif (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) {\n\t\to->pending = 0;\n\t\to->next_state = ECORE_F_STATE_MAX;\n\t}\n\n\t/* Don't allow a next state transition if we are in the middle of\n\t * the previous one.\n\t */\n\tif (o->pending)\n\t\treturn ECORE_BUSY;\n\n\tswitch (state) {\n\tcase ECORE_F_STATE_RESET:\n\t\tif (cmd == ECORE_F_CMD_HW_INIT)\n\t\t\tnext_state = ECORE_F_STATE_INITIALIZED;\n\n\t\tbreak;\n\tcase ECORE_F_STATE_INITIALIZED:\n\t\tif (cmd == ECORE_F_CMD_START)\n\t\t\tnext_state = ECORE_F_STATE_STARTED;\n\n\t\telse if (cmd == ECORE_F_CMD_HW_RESET)\n\t\t\tnext_state = ECORE_F_STATE_RESET;\n\n\t\tbreak;\n\tcase ECORE_F_STATE_STARTED:\n\t\tif (cmd == ECORE_F_CMD_STOP)\n\t\t\tnext_state = ECORE_F_STATE_INITIALIZED;\n\t\t/* afex ramrods can be sent only in started mode, and only\n\t\t * if not pending for function_stop ramrod completion\n\t\t * for these events - next state remained STARTED.\n\t\t */\n\t\telse if ((cmd == ECORE_F_CMD_AFEX_UPDATE) &&\n\t\t\t (!ECORE_TEST_BIT(ECORE_F_CMD_STOP, &o->pending)))\n\t\t\tnext_state = ECORE_F_STATE_STARTED;\n\n\t\telse if ((cmd == ECORE_F_CMD_AFEX_VIFLISTS) &&\n\t\t\t (!ECORE_TEST_BIT(ECORE_F_CMD_STOP, &o->pending)))\n\t\t\tnext_state = ECORE_F_STATE_STARTED;\n\n\t\t/* Switch_update ramrod can be sent in either started or\n\t\t * tx_stopped state, and it doesn't change the state.\n\t\t */\n\t\telse if ((cmd == ECORE_F_CMD_SWITCH_UPDATE) &&\n\t\t\t (!ECORE_TEST_BIT(ECORE_F_CMD_STOP, &o->pending)))\n\t\t\tnext_state = ECORE_F_STATE_STARTED;\n\n\t\telse if (cmd == ECORE_F_CMD_TX_STOP)\n\t\t\tnext_state = ECORE_F_STATE_TX_STOPPED;\n\n\t\tbreak;\n\tcase ECORE_F_STATE_TX_STOPPED:\n\t\tif ((cmd == ECORE_F_CMD_SWITCH_UPDATE) &&\n\t\t (!ECORE_TEST_BIT(ECORE_F_CMD_STOP, &o->pending)))\n\t\t\tnext_state = ECORE_F_STATE_TX_STOPPED;\n\n\t\telse if (cmd == ECORE_F_CMD_TX_START)\n\t\t\tnext_state = ECORE_F_STATE_STARTED;\n\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Unknown state: %d\", state);\n\t}\n\n\t/* Transition is assured */\n\tif (next_state != ECORE_F_STATE_MAX) {\n\t\tECORE_MSG(\"Good function state transition: %d(%d)->%d\",\n\t\t\t state, cmd, next_state);\n\t\to->next_state = next_state;\n\t\treturn ECORE_SUCCESS;\n\t}\n\n\tECORE_MSG(\"Bad function state transition request: %d %d\", state, cmd);\n\n\treturn ECORE_INVAL;\n}\n\n/**\n * ecore_func_init_func - performs HW init at function stage\n *\n * @sc:\t\tdevice handle\n * @drv:\n *\n * Init HW when the current phase is\n * FW_MSG_CODE_DRV_LOAD_FUNCTION: initialize only FUNCTION-only\n * HW blocks.\n */\nstatic int ecore_func_init_func(struct bnx2x_softc *sc,\n\t\t\t\tconst struct ecore_func_sp_drv_ops *drv)\n{\n\treturn drv->init_hw_func(sc);\n}\n\n/**\n * ecore_func_init_port - performs HW init at port stage\n *\n * @sc:\t\tdevice handle\n * @drv:\n *\n * Init HW when the current phase is\n * FW_MSG_CODE_DRV_LOAD_PORT: initialize PORT-only and\n * FUNCTION-only HW blocks.\n *\n */\nstatic int ecore_func_init_port(struct bnx2x_softc *sc,\n\t\t\t\tconst struct ecore_func_sp_drv_ops *drv)\n{\n\tint rc = drv->init_hw_port(sc);\n\tif (rc)\n\t\treturn rc;\n\n\treturn ecore_func_init_func(sc, drv);\n}\n\n/**\n * ecore_func_init_cmn_chip - performs HW init at chip-common stage\n *\n * @sc:\t\tdevice handle\n * @drv:\n *\n * Init HW when the current phase is\n * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON_CHIP,\n * PORT-only and FUNCTION-only HW blocks.\n */\nstatic int ecore_func_init_cmn_chip(struct bnx2x_softc *sc, const struct ecore_func_sp_drv_ops\n\t\t\t\t *drv)\n{\n\tint rc = drv->init_hw_cmn_chip(sc);\n\tif (rc)\n\t\treturn rc;\n\n\treturn ecore_func_init_port(sc, drv);\n}\n\n/**\n * ecore_func_init_cmn - performs HW init at common stage\n *\n * @sc:\t\tdevice handle\n * @drv:\n *\n * Init HW when the current phase is\n * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON,\n * PORT-only and FUNCTION-only HW blocks.\n */\nstatic int ecore_func_init_cmn(struct bnx2x_softc *sc,\n\t\t\t const struct ecore_func_sp_drv_ops *drv)\n{\n\tint rc = drv->init_hw_cmn(sc);\n\tif (rc)\n\t\treturn rc;\n\n\treturn ecore_func_init_port(sc, drv);\n}\n\nstatic int ecore_func_hw_init(struct bnx2x_softc *sc,\n\t\t\t struct ecore_func_state_params *params)\n{\n\tuint32_t load_code = params->params.hw_init.load_phase;\n\tstruct ecore_func_sp_obj *o = params->f_obj;\n\tconst struct ecore_func_sp_drv_ops *drv = o->drv;\n\tint rc = 0;\n\n\tECORE_MSG(\"function %d load_code %x\",\n\t\t ECORE_ABS_FUNC_ID(sc), load_code);\n\n\t/* Prepare FW */\n\trc = drv->init_fw(sc);\n\tif (rc) {\n\t\tPMD_DRV_LOG(ERR, \"Error loading firmware\");\n\t\tgoto init_err;\n\t}\n\n\t/* Handle the beginning of COMMON_XXX pases separately... */\n\tswitch (load_code) {\n\tcase FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:\n\t\trc = ecore_func_init_cmn_chip(sc, drv);\n\t\tif (rc)\n\t\t\tgoto init_err;\n\n\t\tbreak;\n\tcase FW_MSG_CODE_DRV_LOAD_COMMON:\n\t\trc = ecore_func_init_cmn(sc, drv);\n\t\tif (rc)\n\t\t\tgoto init_err;\n\n\t\tbreak;\n\tcase FW_MSG_CODE_DRV_LOAD_PORT:\n\t\trc = ecore_func_init_port(sc, drv);\n\t\tif (rc)\n\t\t\tgoto init_err;\n\n\t\tbreak;\n\tcase FW_MSG_CODE_DRV_LOAD_FUNCTION:\n\t\trc = ecore_func_init_func(sc, drv);\n\t\tif (rc)\n\t\t\tgoto init_err;\n\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Unknown load_code (0x%x) from MCP\",\n\t\t\t load_code);\n\t\trc = ECORE_INVAL;\n\t}\n\ninit_err:\n\t/* In case of success, complete the command immediately: no ramrods\n\t * have been sent.\n\t */\n\tif (!rc)\n\t\to->complete_cmd(sc, o, ECORE_F_CMD_HW_INIT);\n\n\treturn rc;\n}\n\n/**\n * ecore_func_reset_func - reset HW at function stage\n *\n * @sc:\t\tdevice handle\n * @drv:\n *\n * Reset HW at FW_MSG_CODE_DRV_UNLOAD_FUNCTION stage: reset only\n * FUNCTION-only HW blocks.\n */\nstatic void ecore_func_reset_func(struct bnx2x_softc *sc, const struct ecore_func_sp_drv_ops\n\t\t\t\t *drv)\n{\n\tdrv->reset_hw_func(sc);\n}\n\n/**\n * ecore_func_reset_port - reser HW at port stage\n *\n * @sc:\t\tdevice handle\n * @drv:\n *\n * Reset HW at FW_MSG_CODE_DRV_UNLOAD_PORT stage: reset\n * FUNCTION-only and PORT-only HW blocks.\n *\n * !!!IMPORTANT!!!\n *\n * It's important to call reset_port before reset_func() as the last thing\n * reset_func does is pf_disable() thus disabling PGLUE_B, which\n * makes impossible any DMAE transactions.\n */\nstatic void ecore_func_reset_port(struct bnx2x_softc *sc, const struct ecore_func_sp_drv_ops\n\t\t\t\t *drv)\n{\n\tdrv->reset_hw_port(sc);\n\tecore_func_reset_func(sc, drv);\n}\n\n/**\n * ecore_func_reset_cmn - reser HW at common stage\n *\n * @sc:\t\tdevice handle\n * @drv:\n *\n * Reset HW at FW_MSG_CODE_DRV_UNLOAD_COMMON and\n * FW_MSG_CODE_DRV_UNLOAD_COMMON_CHIP stages: reset COMMON,\n * COMMON_CHIP, FUNCTION-only and PORT-only HW blocks.\n */\nstatic void ecore_func_reset_cmn(struct bnx2x_softc *sc,\n\t\t\t\t const struct ecore_func_sp_drv_ops *drv)\n{\n\tecore_func_reset_port(sc, drv);\n\tdrv->reset_hw_cmn(sc);\n}\n\nstatic int ecore_func_hw_reset(struct bnx2x_softc *sc,\n\t\t\t struct ecore_func_state_params *params)\n{\n\tuint32_t reset_phase = params->params.hw_reset.reset_phase;\n\tstruct ecore_func_sp_obj *o = params->f_obj;\n\tconst struct ecore_func_sp_drv_ops *drv = o->drv;\n\n\tECORE_MSG(\"function %d reset_phase %x\", ECORE_ABS_FUNC_ID(sc),\n\t\t reset_phase);\n\n\tswitch (reset_phase) {\n\tcase FW_MSG_CODE_DRV_UNLOAD_COMMON:\n\t\tecore_func_reset_cmn(sc, drv);\n\t\tbreak;\n\tcase FW_MSG_CODE_DRV_UNLOAD_PORT:\n\t\tecore_func_reset_port(sc, drv);\n\t\tbreak;\n\tcase FW_MSG_CODE_DRV_UNLOAD_FUNCTION:\n\t\tecore_func_reset_func(sc, drv);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Unknown reset_phase (0x%x) from MCP\",\n\t\t\t reset_phase);\n\t\tbreak;\n\t}\n\n\t/* Complete the command immediately: no ramrods have been sent. */\n\to->complete_cmd(sc, o, ECORE_F_CMD_HW_RESET);\n\n\treturn ECORE_SUCCESS;\n}\n\nstatic int ecore_func_send_start(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_func_state_params *params)\n{\n\tstruct ecore_func_sp_obj *o = params->f_obj;\n\tstruct function_start_data *rdata =\n\t (struct function_start_data *)o->rdata;\n\tecore_dma_addr_t data_mapping = o->rdata_mapping;\n\tstruct ecore_func_start_params *start_params = ¶ms->params.start;\n\n\tECORE_MEMSET(rdata, 0, sizeof(*rdata));\n\n\t/* Fill the ramrod data with provided parameters */\n\trdata->function_mode = (uint8_t) start_params->mf_mode;\n\trdata->sd_vlan_tag = ECORE_CPU_TO_LE16(start_params->sd_vlan_tag);\n\trdata->path_id = ECORE_PATH_ID(sc);\n\trdata->network_cos_mode = start_params->network_cos_mode;\n\trdata->gre_tunnel_mode = start_params->gre_tunnel_mode;\n\trdata->gre_tunnel_rss = start_params->gre_tunnel_rss;\n\n\t/*\n\t * No need for an explicit memory barrier here as long we would\n\t * need to ensure the ordering of writing to the SPQ element\n\t * and updating of the SPQ producer which involves a memory\n\t * read and we will have to put a full memory barrier there\n\t * (inside ecore_sp_post()).\n\t */\n\n\treturn ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0,\n\t\t\t data_mapping, NONE_CONNECTION_TYPE);\n}\n\nstatic int ecore_func_send_switch_update(struct bnx2x_softc *sc, struct ecore_func_state_params\n\t\t\t\t\t *params)\n{\n\tstruct ecore_func_sp_obj *o = params->f_obj;\n\tstruct function_update_data *rdata =\n\t (struct function_update_data *)o->rdata;\n\tecore_dma_addr_t data_mapping = o->rdata_mapping;\n\tstruct ecore_func_switch_update_params *switch_update_params =\n\t ¶ms->params.switch_update;\n\n\tECORE_MEMSET(rdata, 0, sizeof(*rdata));\n\n\t/* Fill the ramrod data with provided parameters */\n\trdata->tx_switch_suspend_change_flg = 1;\n\trdata->tx_switch_suspend = switch_update_params->suspend;\n\trdata->echo = SWITCH_UPDATE;\n\n\treturn ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,\n\t\t\t data_mapping, NONE_CONNECTION_TYPE);\n}\n\nstatic int ecore_func_send_afex_update(struct bnx2x_softc *sc, struct ecore_func_state_params\n\t\t\t\t *params)\n{\n\tstruct ecore_func_sp_obj *o = params->f_obj;\n\tstruct function_update_data *rdata =\n\t (struct function_update_data *)o->afex_rdata;\n\tecore_dma_addr_t data_mapping = o->afex_rdata_mapping;\n\tstruct ecore_func_afex_update_params *afex_update_params =\n\t ¶ms->params.afex_update;\n\n\tECORE_MEMSET(rdata, 0, sizeof(*rdata));\n\n\t/* Fill the ramrod data with provided parameters */\n\trdata->vif_id_change_flg = 1;\n\trdata->vif_id = ECORE_CPU_TO_LE16(afex_update_params->vif_id);\n\trdata->afex_default_vlan_change_flg = 1;\n\trdata->afex_default_vlan =\n\t ECORE_CPU_TO_LE16(afex_update_params->afex_default_vlan);\n\trdata->allowed_priorities_change_flg = 1;\n\trdata->allowed_priorities = afex_update_params->allowed_priorities;\n\trdata->echo = AFEX_UPDATE;\n\n\t/* No need for an explicit memory barrier here as long we would\n\t * need to ensure the ordering of writing to the SPQ element\n\t * and updating of the SPQ producer which involves a memory\n\t * read and we will have to put a full memory barrier there\n\t * (inside ecore_sp_post()).\n\t */\n\tECORE_MSG(\"afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x\",\n\t\t rdata->vif_id,\n\t\t rdata->afex_default_vlan, rdata->allowed_priorities);\n\n\treturn ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,\n\t\t\t data_mapping, NONE_CONNECTION_TYPE);\n}\n\nstatic\ninline int ecore_func_send_afex_viflists(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_func_state_params *params)\n{\n\tstruct ecore_func_sp_obj *o = params->f_obj;\n\tstruct afex_vif_list_ramrod_data *rdata =\n\t (struct afex_vif_list_ramrod_data *)o->afex_rdata;\n\tstruct ecore_func_afex_viflists_params *afex_vif_params =\n\t ¶ms->params.afex_viflists;\n\tuint64_t *p_rdata = (uint64_t *) rdata;\n\n\tECORE_MEMSET(rdata, 0, sizeof(*rdata));\n\n\t/* Fill the ramrod data with provided parameters */\n\trdata->vif_list_index =\n\t ECORE_CPU_TO_LE16(afex_vif_params->vif_list_index);\n\trdata->func_bit_map = afex_vif_params->func_bit_map;\n\trdata->afex_vif_list_command = afex_vif_params->afex_vif_list_command;\n\trdata->func_to_clear = afex_vif_params->func_to_clear;\n\n\t/* send in echo type of sub command */\n\trdata->echo = afex_vif_params->afex_vif_list_command;\n\n\t/* No need for an explicit memory barrier here as long we would\n\t * need to ensure the ordering of writing to the SPQ element\n\t * and updating of the SPQ producer which involves a memory\n\t * read and we will have to put a full memory barrier there\n\t * (inside ecore_sp_post()).\n\t */\n\n\tECORE_MSG\n\t (\"afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x\",\n\t rdata->afex_vif_list_command, rdata->vif_list_index,\n\t rdata->func_bit_map, rdata->func_to_clear);\n\n\t/* this ramrod sends data directly and not through DMA mapping */\n\treturn ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 0,\n\t\t\t *p_rdata, NONE_CONNECTION_TYPE);\n}\n\nstatic int ecore_func_send_stop(struct bnx2x_softc *sc, __rte_unused struct\n\t\t\t\tecore_func_state_params *params)\n{\n\treturn ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0,\n\t\t\t NONE_CONNECTION_TYPE);\n}\n\nstatic int ecore_func_send_tx_stop(struct bnx2x_softc *sc, __rte_unused struct\n\t\t\t\t ecore_func_state_params *params)\n{\n\treturn ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 0, 0,\n\t\t\t NONE_CONNECTION_TYPE);\n}\n\nstatic int ecore_func_send_tx_start(struct bnx2x_softc *sc, struct ecore_func_state_params\n\t\t\t\t *params)\n{\n\tstruct ecore_func_sp_obj *o = params->f_obj;\n\tstruct flow_control_configuration *rdata =\n\t (struct flow_control_configuration *)o->rdata;\n\tecore_dma_addr_t data_mapping = o->rdata_mapping;\n\tstruct ecore_func_tx_start_params *tx_start_params =\n\t ¶ms->params.tx_start;\n\tuint32_t i;\n\n\tECORE_MEMSET(rdata, 0, sizeof(*rdata));\n\n\trdata->dcb_enabled = tx_start_params->dcb_enabled;\n\trdata->dcb_version = tx_start_params->dcb_version;\n\trdata->dont_add_pri_0 = tx_start_params->dont_add_pri_0;\n\n\tfor (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)\n\t\trdata->traffic_type_to_priority_cos[i] =\n\t\t tx_start_params->traffic_type_to_priority_cos[i];\n\n\treturn ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_START_TRAFFIC, 0,\n\t\t\t data_mapping, NONE_CONNECTION_TYPE);\n}\n\nstatic int ecore_func_send_cmd(struct bnx2x_softc *sc,\n\t\t\t struct ecore_func_state_params *params)\n{\n\tswitch (params->cmd) {\n\tcase ECORE_F_CMD_HW_INIT:\n\t\treturn ecore_func_hw_init(sc, params);\n\tcase ECORE_F_CMD_START:\n\t\treturn ecore_func_send_start(sc, params);\n\tcase ECORE_F_CMD_STOP:\n\t\treturn ecore_func_send_stop(sc, params);\n\tcase ECORE_F_CMD_HW_RESET:\n\t\treturn ecore_func_hw_reset(sc, params);\n\tcase ECORE_F_CMD_AFEX_UPDATE:\n\t\treturn ecore_func_send_afex_update(sc, params);\n\tcase ECORE_F_CMD_AFEX_VIFLISTS:\n\t\treturn ecore_func_send_afex_viflists(sc, params);\n\tcase ECORE_F_CMD_TX_STOP:\n\t\treturn ecore_func_send_tx_stop(sc, params);\n\tcase ECORE_F_CMD_TX_START:\n\t\treturn ecore_func_send_tx_start(sc, params);\n\tcase ECORE_F_CMD_SWITCH_UPDATE:\n\t\treturn ecore_func_send_switch_update(sc, params);\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Unknown command: %d\", params->cmd);\n\t\treturn ECORE_INVAL;\n\t}\n}\n\nvoid ecore_init_func_obj(__rte_unused struct bnx2x_softc *sc,\n\t\t\t struct ecore_func_sp_obj *obj,\n\t\t\t void *rdata, ecore_dma_addr_t rdata_mapping,\n\t\t\t void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping,\n\t\t\t struct ecore_func_sp_drv_ops *drv_iface)\n{\n\tECORE_MEMSET(obj, 0, sizeof(*obj));\n\n\tECORE_MUTEX_INIT(&obj->one_pending_mutex);\n\n\tobj->rdata = rdata;\n\tobj->rdata_mapping = rdata_mapping;\n\tobj->afex_rdata = afex_rdata;\n\tobj->afex_rdata_mapping = afex_rdata_mapping;\n\tobj->send_cmd = ecore_func_send_cmd;\n\tobj->check_transition = ecore_func_chk_transition;\n\tobj->complete_cmd = ecore_func_comp_cmd;\n\tobj->wait_comp = ecore_func_wait_comp;\n\tobj->drv = drv_iface;\n}\n\n/**\n * ecore_func_state_change - perform Function state change transition\n *\n * @sc:\t\tdevice handle\n * @params:\tparameters to perform the transaction\n *\n * returns 0 in case of successfully completed transition,\n * negative error code in case of failure, positive\n * (EBUSY) value if there is a completion to that is\n * still pending (possible only if RAMROD_COMP_WAIT is\n * not set in params->ramrod_flags for asynchronous\n * commands).\n */\nint ecore_func_state_change(struct bnx2x_softc *sc,\n\t\t\t struct ecore_func_state_params *params)\n{\n\tstruct ecore_func_sp_obj *o = params->f_obj;\n\tint rc, cnt = 300;\n\tenum ecore_func_cmd cmd = params->cmd;\n\tunsigned long *pending = &o->pending;\n\n\tECORE_MUTEX_LOCK(&o->one_pending_mutex);\n\n\t/* Check that the requested transition is legal */\n\trc = o->check_transition(sc, o, params);\n\tif ((rc == ECORE_BUSY) &&\n\t (ECORE_TEST_BIT(RAMROD_RETRY, ¶ms->ramrod_flags))) {\n\t\twhile ((rc == ECORE_BUSY) && (--cnt > 0)) {\n\t\t\tECORE_MUTEX_UNLOCK(&o->one_pending_mutex);\n\t\t\tECORE_MSLEEP(10);\n\t\t\tECORE_MUTEX_LOCK(&o->one_pending_mutex);\n\t\t\trc = o->check_transition(sc, o, params);\n\t\t}\n\t\tif (rc == ECORE_BUSY) {\n\t\t\tECORE_MUTEX_UNLOCK(&o->one_pending_mutex);\n\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t \"timeout waiting for previous ramrod completion\");\n\t\t\treturn rc;\n\t\t}\n\t} else if (rc) {\n\t\tECORE_MUTEX_UNLOCK(&o->one_pending_mutex);\n\t\treturn rc;\n\t}\n\n\t/* Set \"pending\" bit */\n\tECORE_SET_BIT(cmd, pending);\n\n\t/* Don't send a command if only driver cleanup was requested */\n\tif (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) {\n\t\tecore_func_state_change_comp(sc, o, cmd);\n\t\tECORE_MUTEX_UNLOCK(&o->one_pending_mutex);\n\t} else {\n\t\t/* Send a ramrod */\n\t\trc = o->send_cmd(sc, params);\n\n\t\tECORE_MUTEX_UNLOCK(&o->one_pending_mutex);\n\n\t\tif (rc) {\n\t\t\to->next_state = ECORE_F_STATE_MAX;\n\t\t\tECORE_CLEAR_BIT(cmd, pending);\n\t\t\tECORE_SMP_MB_AFTER_CLEAR_BIT();\n\t\t\treturn rc;\n\t\t}\n\n\t\tif (ECORE_TEST_BIT(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) {\n\t\t\trc = o->wait_comp(sc, o, cmd);\n\t\t\tif (rc)\n\t\t\t\treturn rc;\n\n\t\t\treturn ECORE_SUCCESS;\n\t\t}\n\t}\n\n\treturn ECORE_RET_PENDING(cmd, pending);\n}\n\n/******************************************************************************\n * Description:\n *\t Calculates crc 8 on a word value: polynomial 0-1-2-8\n *\t Code was translated from Verilog.\n * Return:\n *****************************************************************************/\nuint8_t ecore_calc_crc8(uint32_t data, uint8_t crc)\n{\n\tuint8_t D[32];\n\tuint8_t NewCRC[8];\n\tuint8_t C[8];\n\tuint8_t crc_res;\n\tuint8_t i;\n\n\t/* split the data into 31 bits */\n\tfor (i = 0; i < 32; i++) {\n\t\tD[i] = (uint8_t) (data & 1);\n\t\tdata = data >> 1;\n\t}\n\n\t/* split the crc into 8 bits */\n\tfor (i = 0; i < 8; i++) {\n\t\tC[i] = crc & 1;\n\t\tcrc = crc >> 1;\n\t}\n\n\tNewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^\n\t D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^\n\t C[6] ^ C[7];\n\tNewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^\n\t D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^\n\t D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];\n\tNewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^\n\t D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^\n\t C[0] ^ C[1] ^ C[4] ^ C[5];\n\tNewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^\n\t D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^\n\t C[1] ^ C[2] ^ C[5] ^ C[6];\n\tNewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^\n\t D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^\n\t C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];\n\tNewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^\n\t D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^\n\t C[3] ^ C[4] ^ C[7];\n\tNewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^\n\t D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ C[5];\n\tNewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^\n\t D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ C[6];\n\n\tcrc_res = 0;\n\tfor (i = 0; i < 8; i++) {\n\t\tcrc_res |= (NewCRC[i] << i);\n\t}\n\n\treturn crc_res;\n}\n\nuint32_t\necore_calc_crc32(uint32_t crc, uint8_t const *p, uint32_t len, uint32_t magic)\n{\n\tint i;\n\twhile (len--) {\n\t\tcrc ^= *p++;\n\t\tfor (i = 0; i < 8; i++)\n\t\t\tcrc = (crc >> 1) ^ ((crc & 1) ? magic : 0);\n\t}\n\treturn crc;\n}\n" }, { "path": "drivers/net/bnx2x/ecore_sp.h", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ECORE_SP_H\n#define ECORE_SP_H\n\n#if __BYTE_ORDER == __LITTLE_ENDIAN\n#ifndef LITTLE_ENDIAN\n#define LITTLE_ENDIAN\n#endif\n#ifndef __LITTLE_ENDIAN\n#define __LITTLE_ENDIAN\n#endif\n#undef BIG_ENDIAN\n#undef __BIG_ENDIAN\n#else /* _BIG_ENDIAN */\n#ifndef BIG_ENDIAN\n#define BIG_ENDIAN\n#endif\n#ifndef __BIG_ENDIAN\n#define __BIG_ENDIAN\n#endif\n#undef LITTLE_ENDIAN\n#undef __LITTLE_ENDIAN\n#endif\n\n#include \"ecore_mfw_req.h\"\n#include \"ecore_fw_defs.h\"\n#include \"ecore_hsi.h\"\n#include \"ecore_reg.h\"\n\nstruct bnx2x_softc;\ntypedef phys_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */\ntypedef volatile int ecore_atomic_t;\n\n\n#define ETH_ALEN ETHER_ADDR_LEN /* 6 */\n\n#define ECORE_SWCID_SHIFT 17\n#define ECORE_SWCID_MASK ((0x1 << ECORE_SWCID_SHIFT) - 1)\n\n#define ECORE_MC_HASH_SIZE 8\n#define ECORE_MC_HASH_OFFSET(sc, i) \\\n (BAR_TSTRORM_INTMEM + \\\n TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4)\n\n#define ECORE_MAX_MULTICAST 64\n#define ECORE_MAX_EMUL_MULTI 1\n\n#define IRO sc->iro_array\n\ntypedef rte_spinlock_t ECORE_MUTEX;\n#define ECORE_MUTEX_INIT(_mutex) rte_spinlock_init(_mutex)\n#define ECORE_MUTEX_LOCK(_mutex) rte_spinlock_lock(_mutex)\n#define ECORE_MUTEX_UNLOCK(_mutex) rte_spinlock_unlock(_mutex)\n\ntypedef rte_spinlock_t ECORE_MUTEX_SPIN;\n#define ECORE_SPIN_LOCK_INIT(_spin, _sc) rte_spinlock_init(_spin)\n#define ECORE_SPIN_LOCK_BH(_spin) rte_spinlock_lock(_spin) /* bh = bottom-half */\n#define ECORE_SPIN_UNLOCK_BH(_spin) rte_spinlock_unlock(_spin) /* bh = bottom-half */\n\n#define ECORE_SMP_MB_AFTER_CLEAR_BIT() mb()\n#define ECORE_SMP_MB_BEFORE_CLEAR_BIT() mb()\n#define ECORE_SMP_MB() mb()\n#define ECORE_SMP_RMB() rmb()\n#define ECORE_SMP_WMB() wmb()\n#define ECORE_MMIOWB() wmb()\n\n#define ECORE_SET_BIT_NA(bit, var) (*var |= (1 << bit))\n#define ECORE_CLEAR_BIT_NA(bit, var) (*var &= ~(1 << bit))\n\n#define ECORE_TEST_BIT(bit, var) bnx2x_test_bit(bit, var)\n#define ECORE_SET_BIT(bit, var) bnx2x_set_bit(bit, var)\n#define ECORE_CLEAR_BIT(bit, var) bnx2x_clear_bit(bit, var)\n#define ECORE_TEST_AND_CLEAR_BIT(bit, var) bnx2x_test_and_clear_bit(bit, var)\n\n#define atomic_load_acq_int (int)*\n#define atomic_store_rel_int(a, v) (*a = v)\n#define atomic_cmpset_acq_int(a, o, n) ((*a = (o & (n)) | (n)) ^ o)\n\n#define atomic_load_acq_long (long)*\n#define atomic_store_rel_long(a, v) (*a = v)\n#define atomic_set_acq_long(a, v) (*a |= v)\n#define atomic_clear_acq_long(a, v) (*a &= ~v)\n#define atomic_cmpset_acq_long(a, o, n) ((*a = (o & (n)) | (n)) ^ o)\n#define atomic_subtract_acq_long(a, v) (*a -= v)\n#define atomic_add_acq_long(a, v) (*a += v)\n\n#define ECORE_ATOMIC_READ(a) atomic_load_acq_int((volatile int *)a)\n#define ECORE_ATOMIC_SET(a, v) atomic_store_rel_int((volatile int *)a, v)\n#define ECORE_ATOMIC_CMPXCHG(a, o, n) bnx2x_cmpxchg((volatile int *)a, o, n)\n\n#define ECORE_RET_PENDING(pending_bit, pending) \\\n (ECORE_TEST_BIT(pending_bit, pending) ? ECORE_PENDING : ECORE_SUCCESS)\n\n#define ECORE_SET_FLAG(value, mask, flag) \\\n do { \\\n\t(value) &= ~(mask); \\\n\t(value) |= ((flag) << (mask##_SHIFT)); \\\n } while (0)\n\n#define ECORE_GET_FLAG(value, mask) \\\n (((value) &= (mask)) >> (mask##_SHIFT))\n\n#define ECORE_MIGHT_SLEEP()\n\n#define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id)\n\n#define ECORE_MEMCMP(_a, _b, _s) memcmp(_a, _b, _s)\n#define ECORE_MEMCPY(_a, _b, _s) (void)rte_memcpy(_a, _b, _s)\n#define ECORE_MEMSET(_a, _c, _s) memset(_a, _c, _s)\n\n#define ECORE_CPU_TO_LE16(x) htole16(x)\n#define ECORE_CPU_TO_LE32(x) htole32(x)\n\n#define ECORE_WAIT(_s, _t) DELAY(1000)\n#define ECORE_MSLEEP(_t) DELAY((_t) * 1000)\n\n#define ECORE_LIKELY(x) likely(x)\n#define ECORE_UNLIKELY(x) unlikely(x)\n\n#define ECORE_ZALLOC(_size, _flags, _sc) \\\n rte_zmalloc(\"\", _size, RTE_CACHE_LINE_SIZE)\n\n#define ECORE_CALLOC(_len, _size, _flags, _sc) \\\n rte_calloc(\"\", _len, _size, RTE_CACHE_LINE_SIZE)\n\n#define ECORE_FREE(_s, _buf, _size) \\\n rte_free(_buf)\n\n#define SC_ILT(sc) ((sc)->ilt)\n#define ILOG2(x) bnx2x_ilog2(x)\n\n#define ECORE_ILT_ZALLOC(x, y, size, str)\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\t\t\\\n\t\tx = rte_malloc(\"\", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \\\n\t\tif (x) {\t\t\t\t\t\t\\\n\t\t\tif (bnx2x_dma_alloc((struct bnx2x_softc *)sc,\t\\\n\t\t\t\t\t size, (struct bnx2x_dma *)x,\t\\\n\t\t\t\t\t str, RTE_CACHE_LINE_SIZE) != 0) { \\\n\t\t\t\trte_free(x);\t\t\t\t\\\n\t\t\t\tx = NULL;\t\t\t\t\\\n\t\t\t\t*y = 0;\t\t\t\t\t\\\n\t\t\t} else {\t\t\t\t\t\\\n\t\t\t\t*y = ((struct bnx2x_dma *)x)->paddr;\t\\\n\t\t\t}\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\\\n\t} while (0)\n\n#define ECORE_ILT_FREE(x, y, size) \\\n do { \\\n\tif (x) { \\\n\t rte_free(x); \\\n\t x = NULL; \\\n\t y = 0; \\\n\t} \\\n } while (0)\n\n#define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE\n\n#define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE\n#define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE\n#define ECORE_IS_MF_AFEX_MODE IS_MF_AFEX_MODE\n\n#define ECORE_SET_CTX_VALIDATION bnx2x_set_ctx_validation\n\n#define ECORE_UPDATE_COALESCE_SB_INDEX bnx2x_update_coalesce_sb_index\n\n#define ECORE_ALIGN(x, a) ((((x) + (a) - 1) / (a)) * (a))\n\n#define ECORE_REG_WR_DMAE_LEN REG_WR_DMAE_LEN\n\n#define ECORE_PATH_ID SC_PATH\n#define ECORE_PORT_ID SC_PORT\n#define ECORE_FUNC_ID SC_FUNC\n#define ECORE_ABS_FUNC_ID SC_ABS_FUNC\n\n#define CRCPOLY_LE 0xedb88320\nuint32_t ecore_calc_crc32(uint32_t crc, uint8_t const *p,\n\t\t\t uint32_t len, uint32_t magic);\n\nuint8_t ecore_calc_crc8(uint32_t data, uint8_t crc);\n\n\nstatic inline uint32_t\nECORE_CRC32_LE(uint32_t seed, uint8_t *mac, uint32_t len)\n{\n\treturn ecore_calc_crc32(seed, mac, len, CRCPOLY_LE);\n}\n\n#define ecore_sp_post(_sc, _a, _b, _c, _d) \\\n bnx2x_sp_post(_sc, _a, _b, U64_HI(_c), U64_LO(_c), _d)\n\n#define ECORE_DBG_BREAK_IF(exp) \\\n do { \\\n\tif (unlikely(exp)) { \\\n\t rte_panic(\"ECORE\"); \\\n\t} \\\n } while (0)\n\n#define ECORE_BUG() \\\n do { \\\n\trte_panic(\"BUG (%s:%d)\", __FILE__, __LINE__); \\\n } while(0);\n\n#define ECORE_BUG_ON(exp) \\\n do { \\\n\tif (likely(exp)) { \\\n\t rte_panic(\"BUG_ON (%s:%d)\", __FILE__, __LINE__); \\\n\t} \\\n } while (0)\n\n\n#define ECORE_MSG(m, ...) \\\n\tPMD_DRV_LOG(DEBUG, m, ##__VA_ARGS__)\n\ntypedef struct _ecore_list_entry_t\n{\n struct _ecore_list_entry_t *next, *prev;\n} ecore_list_entry_t;\n\ntypedef struct ecore_list_t\n{\n ecore_list_entry_t *head, *tail;\n unsigned long cnt;\n} ecore_list_t;\n\n/* initialize the list */\n#define ECORE_LIST_INIT(_list) \\\n do { \\\n\t(_list)->head = NULL; \\\n\t(_list)->tail = NULL; \\\n\t(_list)->cnt = 0; \\\n } while (0)\n\n/* return TRUE if the element is the last on the list */\n#define ECORE_LIST_IS_LAST(_elem, _list) \\\n (_elem == (_list)->tail)\n\n/* return TRUE if the list is empty */\n#define ECORE_LIST_IS_EMPTY(_list) \\\n ((_list)->cnt == 0)\n\n/* return the first element */\n#define ECORE_LIST_FIRST_ENTRY(_list, cast, _link) \\\n (cast *)((_list)->head)\n\n/* return the next element */\n#define ECORE_LIST_NEXT(_elem, _link, cast) \\\n (cast *)((&((_elem)->_link))->next)\n\n/* push an element on the head of the list */\n#define ECORE_LIST_PUSH_HEAD(_elem, _list) \\\n do { \\\n\t(_elem)->prev = (ecore_list_entry_t *)0; \\\n\t(_elem)->next = (_list)->head; \\\n\tif ((_list)->tail == (ecore_list_entry_t *)0) { \\\n\t (_list)->tail = (_elem); \\\n\t} else { \\\n\t (_list)->head->prev = (_elem); \\\n\t} \\\n\t(_list)->head = (_elem); \\\n\t(_list)->cnt++; \\\n } while (0)\n\n/* push an element on the tail of the list */\n#define ECORE_LIST_PUSH_TAIL(_elem, _list) \\\n do { \\\n\t(_elem)->next = (ecore_list_entry_t *)0; \\\n\t(_elem)->prev = (_list)->tail; \\\n\tif ((_list)->tail) { \\\n\t (_list)->tail->next = (_elem); \\\n\t} else { \\\n\t (_list)->head = (_elem); \\\n\t} \\\n\t(_list)->tail = (_elem); \\\n\t(_list)->cnt++; \\\n } while (0)\n\n/* push list1 on the head of list2 and return with list1 as empty */\n#define ECORE_LIST_SPLICE_INIT(_list1, _list2) \\\n do { \\\n\t(_list1)->tail->next = (_list2)->head; \\\n\tif ((_list2)->head) { \\\n\t (_list2)->head->prev = (_list1)->tail; \\\n\t} else { \\\n\t (_list2)->tail = (_list1)->tail; \\\n\t} \\\n\t(_list2)->head = (_list1)->head; \\\n\t(_list2)->cnt += (_list1)->cnt; \\\n\t(_list1)->head = NULL; \\\n\t(_list1)->tail = NULL; \\\n\t(_list1)->cnt = 0; \\\n } while (0)\n\n/* remove an element from the list */\n#define ECORE_LIST_REMOVE_ENTRY(_elem, _list) \\\n do { \\\n\tif ((_list)->head == (_elem)) { \\\n\t if ((_list)->head) { \\\n\t\t(_list)->head = (_list)->head->next; \\\n\t\tif ((_list)->head) { \\\n\t\t (_list)->head->prev = (ecore_list_entry_t *)0; \\\n\t\t} else { \\\n\t\t (_list)->tail = (ecore_list_entry_t *)0; \\\n\t\t} \\\n\t\t(_list)->cnt--; \\\n\t } \\\n\t} else if ((_list)->tail == (_elem)) { \\\n\t if ((_list)->tail) { \\\n\t\t(_list)->tail = (_list)->tail->prev; \\\n\t\tif ((_list)->tail) { \\\n\t\t (_list)->tail->next = (ecore_list_entry_t *)0; \\\n\t\t} else { \\\n\t\t (_list)->head = (ecore_list_entry_t *)0; \\\n\t\t} \\\n\t\t(_list)->cnt--; \\\n\t } \\\n\t} else { \\\n\t (_elem)->prev->next = (_elem)->next; \\\n\t (_elem)->next->prev = (_elem)->prev; \\\n\t (_list)->cnt--; \\\n\t} \\\n } while (0)\n\n/* walk the list */\n#define ECORE_LIST_FOR_EACH_ENTRY(pos, _list, _link, cast) \\\n for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _link); \\\n\t pos; \\\n\t pos = ECORE_LIST_NEXT(pos, _link, cast))\n\n/* walk the list (safely) */\n#define ECORE_LIST_FOR_EACH_ENTRY_SAFE(pos, n, _list, _link, cast) \\\n for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _lint), \\\n\t n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL; \\\n\t pos != NULL; \\\n\t pos = (cast *)n, \\\n\t n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL)\n\n\n/* Manipulate a bit vector defined as an array of uint64_t */\n\n/* Number of bits in one sge_mask array element */\n#define BIT_VEC64_ELEM_SZ 64\n#define BIT_VEC64_ELEM_SHIFT 6\n#define BIT_VEC64_ELEM_MASK ((uint64_t)BIT_VEC64_ELEM_SZ - 1)\n\n#define __BIT_VEC64_SET_BIT(el, bit) \\\n do { \\\n\tel = ((el) | ((uint64_t)0x1 << (bit))); \\\n } while (0)\n\n#define __BIT_VEC64_CLEAR_BIT(el, bit) \\\n do { \\\n\tel = ((el) & (~((uint64_t)0x1 << (bit)))); \\\n } while (0)\n\n#define BIT_VEC64_SET_BIT(vec64, idx) \\\n __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \\\n\t\t\t(idx) & BIT_VEC64_ELEM_MASK)\n\n#define BIT_VEC64_CLEAR_BIT(vec64, idx) \\\n __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \\\n\t\t\t (idx) & BIT_VEC64_ELEM_MASK)\n\n#define BIT_VEC64_TEST_BIT(vec64, idx) \\\n (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \\\n ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)\n\n/*\n * Creates a bitmask of all ones in less significant bits.\n * idx - index of the most significant bit in the created mask\n */\n#define BIT_VEC64_ONES_MASK(idx) \\\n (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)\n#define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0))\n\n/* fill in a MAC address the way the FW likes it */\nstatic inline void\necore_set_fw_mac_addr(uint16_t *fw_hi,\n\t\t uint16_t *fw_mid,\n\t\t uint16_t *fw_lo,\n\t\t uint8_t *mac)\n{\n ((uint8_t *)fw_hi)[0] = mac[1];\n ((uint8_t *)fw_hi)[1] = mac[0];\n ((uint8_t *)fw_mid)[0] = mac[3];\n ((uint8_t *)fw_mid)[1] = mac[2];\n ((uint8_t *)fw_lo)[0] = mac[5];\n ((uint8_t *)fw_lo)[1] = mac[4];\n}\n\n\nenum ecore_status_t {\n ECORE_EXISTS = -6,\n ECORE_IO = -5,\n ECORE_TIMEOUT = -4,\n ECORE_INVAL = -3,\n ECORE_BUSY = -2,\n ECORE_NOMEM = -1,\n ECORE_SUCCESS = 0,\n /* PENDING is not an error and should be positive */\n ECORE_PENDING = 1,\n};\n\nenum {\n SWITCH_UPDATE,\n AFEX_UPDATE,\n};\n\n\n\n\nstruct bnx2x_softc;\nstruct eth_context;\n\n/* Bits representing general command's configuration */\nenum {\n\tRAMROD_TX,\n\tRAMROD_RX,\n\t/* Wait until all pending commands complete */\n\tRAMROD_COMP_WAIT,\n\t/* Don't send a ramrod, only update a registry */\n\tRAMROD_DRV_CLR_ONLY,\n\t/* Configure HW according to the current object state */\n\tRAMROD_RESTORE,\n\t /* Execute the next command now */\n\tRAMROD_EXEC,\n\t/* Don't add a new command and continue execution of posponed\n\t * commands. If not set a new command will be added to the\n\t * pending commands list.\n\t */\n\tRAMROD_CONT,\n\t/* If there is another pending ramrod, wait until it finishes and\n\t * re-try to submit this one. This flag can be set only in sleepable\n\t * context, and should not be set from the context that completes the\n\t * ramrods as deadlock will occur.\n\t */\n\tRAMROD_RETRY,\n};\n\ntypedef enum {\n\tECORE_OBJ_TYPE_RX,\n\tECORE_OBJ_TYPE_TX,\n\tECORE_OBJ_TYPE_RX_TX,\n} ecore_obj_type;\n\n/* Public slow path states */\nenum {\n\tECORE_FILTER_MAC_PENDING,\n\tECORE_FILTER_VLAN_PENDING,\n\tECORE_FILTER_VLAN_MAC_PENDING,\n\tECORE_FILTER_RX_MODE_PENDING,\n\tECORE_FILTER_RX_MODE_SCHED,\n\tECORE_FILTER_ISCSI_ETH_START_SCHED,\n\tECORE_FILTER_ISCSI_ETH_STOP_SCHED,\n\tECORE_FILTER_FCOE_ETH_START_SCHED,\n\tECORE_FILTER_FCOE_ETH_STOP_SCHED,\n\tECORE_FILTER_MCAST_PENDING,\n\tECORE_FILTER_MCAST_SCHED,\n\tECORE_FILTER_RSS_CONF_PENDING,\n\tECORE_AFEX_FCOE_Q_UPDATE_PENDING,\n\tECORE_AFEX_PENDING_VIFSET_MCP_ACK\n};\n\nstruct ecore_raw_obj {\n\tuint8_t\t\tfunc_id;\n\n\t/* Queue params */\n\tuint8_t\t\tcl_id;\n\tuint32_t\t\tcid;\n\n\t/* Ramrod data buffer params */\n\tvoid\t\t*rdata;\n\tecore_dma_addr_t\trdata_mapping;\n\n\t/* Ramrod state params */\n\tint\t\tstate; /* \"ramrod is pending\" state bit */\n\tunsigned long\t*pstate; /* pointer to state buffer */\n\n\tecore_obj_type\tobj_type;\n\n\tint (*wait_comp)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_raw_obj *o);\n\n\tint (*check_pending)(struct ecore_raw_obj *o);\n\tvoid (*clear_pending)(struct ecore_raw_obj *o);\n\tvoid (*set_pending)(struct ecore_raw_obj *o);\n};\n\n/************************* VLAN-MAC commands related parameters ***************/\nstruct ecore_mac_ramrod_data {\n\tuint8_t mac[ETH_ALEN];\n\tuint8_t is_inner_mac;\n};\n\nstruct ecore_vlan_ramrod_data {\n\tuint16_t vlan;\n};\n\nstruct ecore_vlan_mac_ramrod_data {\n\tuint8_t mac[ETH_ALEN];\n\tuint8_t is_inner_mac;\n\tuint16_t vlan;\n};\n\nunion ecore_classification_ramrod_data {\n\tstruct ecore_mac_ramrod_data mac;\n\tstruct ecore_vlan_ramrod_data vlan;\n\tstruct ecore_vlan_mac_ramrod_data vlan_mac;\n};\n\n/* VLAN_MAC commands */\nenum ecore_vlan_mac_cmd {\n\tECORE_VLAN_MAC_ADD,\n\tECORE_VLAN_MAC_DEL,\n\tECORE_VLAN_MAC_MOVE,\n};\n\nstruct ecore_vlan_mac_data {\n\t/* Requested command: ECORE_VLAN_MAC_XX */\n\tenum ecore_vlan_mac_cmd cmd;\n\t/* used to contain the data related vlan_mac_flags bits from\n\t * ramrod parameters.\n\t */\n\tunsigned long vlan_mac_flags;\n\n\t/* Needed for MOVE command */\n\tstruct ecore_vlan_mac_obj *target_obj;\n\n\tunion ecore_classification_ramrod_data u;\n};\n\n/*************************** Exe Queue obj ************************************/\nunion ecore_exe_queue_cmd_data {\n\tstruct ecore_vlan_mac_data vlan_mac;\n\n\tstruct {\n\t} mcast;\n};\n\nstruct ecore_exeq_elem {\n\tecore_list_entry_t\t\tlink;\n\n\t/* Length of this element in the exe_chunk. */\n\tint\t\t\t\tcmd_len;\n\n\tunion ecore_exe_queue_cmd_data\tcmd_data;\n};\n\nunion ecore_qable_obj;\n\nunion ecore_exeq_comp_elem {\n\tunion event_ring_elem *elem;\n};\n\nstruct ecore_exe_queue_obj;\n\ntypedef int (*exe_q_validate)(struct bnx2x_softc *sc,\n\t\t\t union ecore_qable_obj *o,\n\t\t\t struct ecore_exeq_elem *elem);\n\ntypedef int (*exe_q_remove)(struct bnx2x_softc *sc,\n\t\t\t union ecore_qable_obj *o,\n\t\t\t struct ecore_exeq_elem *elem);\n\n/* Return positive if entry was optimized, 0 - if not, negative\n * in case of an error.\n */\ntypedef int (*exe_q_optimize)(struct bnx2x_softc *sc,\n\t\t\t union ecore_qable_obj *o,\n\t\t\t struct ecore_exeq_elem *elem);\ntypedef int (*exe_q_execute)(struct bnx2x_softc *sc,\n\t\t\t union ecore_qable_obj *o,\n\t\t\t ecore_list_t *exe_chunk,\n\t\t\t unsigned long *ramrod_flags);\ntypedef struct ecore_exeq_elem *\n\t\t\t(*exe_q_get)(struct ecore_exe_queue_obj *o,\n\t\t\t\t struct ecore_exeq_elem *elem);\n\nstruct ecore_exe_queue_obj {\n\t/* Commands pending for an execution. */\n\tecore_list_t\texe_queue;\n\n\t/* Commands pending for an completion. */\n\tecore_list_t\tpending_comp;\n\n\tECORE_MUTEX_SPIN\t\tlock;\n\n\t/* Maximum length of commands' list for one execution */\n\tint\t\t\texe_chunk_len;\n\n\tunion ecore_qable_obj\t*owner;\n\n\t/****** Virtual functions ******/\n\t/**\n\t * Called before commands execution for commands that are really\n\t * going to be executed (after 'optimize').\n\t *\n\t * Must run under exe_queue->lock\n\t */\n\texe_q_validate\t\tvalidate;\n\n\t/**\n\t * Called before removing pending commands, cleaning allocated\n\t * resources (e.g., credits from validate)\n\t */\n\t exe_q_remove\t\tremove;\n\n\t/**\n\t * This will try to cancel the current pending commands list\n\t * considering the new command.\n\t *\n\t * Returns the number of optimized commands or a negative error code\n\t *\n\t * Must run under exe_queue->lock\n\t */\n\texe_q_optimize\t\toptimize;\n\n\t/**\n\t * Run the next commands chunk (owner specific).\n\t */\n\texe_q_execute\t\texecute;\n\n\t/**\n\t * Return the exe_queue element containing the specific command\n\t * if any. Otherwise return NULL.\n\t */\n\texe_q_get\t\tget;\n};\n/***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/\n/*\n * Element in the VLAN_MAC registry list having all current configured\n * rules.\n */\nstruct ecore_vlan_mac_registry_elem {\n\tecore_list_entry_t\tlink;\n\n\t/* Used to store the cam offset used for the mac/vlan/vlan-mac.\n\t * Relevant for 57711 only. VLANs and MACs share the\n\t * same CAM for these chips.\n\t */\n\tint\t\t\tcam_offset;\n\n\t/* Needed for DEL and RESTORE flows */\n\tunsigned long\t\tvlan_mac_flags;\n\n\tunion ecore_classification_ramrod_data u;\n};\n\n/* Bits representing VLAN_MAC commands specific flags */\nenum {\n\tECORE_UC_LIST_MAC,\n\tECORE_ETH_MAC,\n\tECORE_ISCSI_ETH_MAC,\n\tECORE_NETQ_ETH_MAC,\n\tECORE_DONT_CONSUME_CAM_CREDIT,\n\tECORE_DONT_CONSUME_CAM_CREDIT_DEST,\n};\n\nstruct ecore_vlan_mac_ramrod_params {\n\t/* Object to run the command from */\n\tstruct ecore_vlan_mac_obj *vlan_mac_obj;\n\n\t/* General command flags: COMP_WAIT, etc. */\n\tunsigned long ramrod_flags;\n\n\t/* Command specific configuration request */\n\tstruct ecore_vlan_mac_data user_req;\n};\n\nstruct ecore_vlan_mac_obj {\n\tstruct ecore_raw_obj raw;\n\n\t/* Bookkeeping list: will prevent the addition of already existing\n\t * entries.\n\t */\n\tecore_list_t\t\thead;\n\t/* Implement a simple reader/writer lock on the head list.\n\t * all these fields should only be accessed under the exe_queue lock\n\t */\n\tuint8_t\t\thead_reader; /* Num. of readers accessing head list */\n\tint\t\thead_exe_request; /* Pending execution request. */\n\tunsigned long\tsaved_ramrod_flags; /* Ramrods of pending execution */\n\n\t/* Execution queue interface instance */\n\tstruct ecore_exe_queue_obj\texe_queue;\n\n\t/* MACs credit pool */\n\tstruct ecore_credit_pool_obj\t*macs_pool;\n\n\t/* VLANs credit pool */\n\tstruct ecore_credit_pool_obj\t*vlans_pool;\n\n\t/* RAMROD command to be used */\n\tint\t\t\t\tramrod_cmd;\n\n\t/* copy first n elements onto preallocated buffer\n\t *\n\t * @param n number of elements to get\n\t * @param buf buffer preallocated by caller into which elements\n\t * will be copied. Note elements are 4-byte aligned\n\t * so buffer size must be able to accommodate the\n\t * aligned elements.\n\t *\n\t * @return number of copied bytes\n\t */\n\n\tint (*get_n_elements)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_vlan_mac_obj *o, int n, uint8_t *base,\n\t\t\t uint8_t stride, uint8_t size);\n\n\t/**\n\t * Checks if ADD-ramrod with the given params may be performed.\n\t *\n\t * @return zero if the element may be added\n\t */\n\n\tint (*check_add)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t union ecore_classification_ramrod_data *data);\n\n\t/**\n\t * Checks if DEL-ramrod with the given params may be performed.\n\t *\n\t * @return TRUE if the element may be deleted\n\t */\n\tstruct ecore_vlan_mac_registry_elem *\n\t\t(*check_del)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t union ecore_classification_ramrod_data *data);\n\n\t/**\n\t * Checks if DEL-ramrod with the given params may be performed.\n\t *\n\t * @return TRUE if the element may be deleted\n\t */\n\tint (*check_move)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_vlan_mac_obj *src_o,\n\t\t\t struct ecore_vlan_mac_obj *dst_o,\n\t\t\t union ecore_classification_ramrod_data *data);\n\n\t/**\n\t * Update the relevant credit object(s) (consume/return\n\t * correspondingly).\n\t */\n\tint (*get_credit)(struct ecore_vlan_mac_obj *o);\n\tint (*put_credit)(struct ecore_vlan_mac_obj *o);\n\tint (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset);\n\tint (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset);\n\n\t/**\n\t * Configures one rule in the ramrod data buffer.\n\t */\n\tvoid (*set_one_rule)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t struct ecore_exeq_elem *elem, int rule_idx,\n\t\t\t int cam_offset);\n\n\t/**\n\t* Delete all configured elements having the given\n\t* vlan_mac_flags specification. Assumes no pending for\n\t* execution commands. Will schedule all all currently\n\t* configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags\n\t* specification for deletion and will use the given\n\t* ramrod_flags for the last DEL operation.\n\t *\n\t * @param sc\n\t * @param o\n\t * @param ramrod_flags RAMROD_XX flags\n\t *\n\t * @return 0 if the last operation has completed successfully\n\t * and there are no more elements left, positive value\n\t * if there are pending for completion commands,\n\t * negative value in case of failure.\n\t */\n\tint (*delete_all)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_vlan_mac_obj *o,\n\t\t\t unsigned long *vlan_mac_flags,\n\t\t\t unsigned long *ramrod_flags);\n\n\t/**\n\t * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously\n\t * configured elements list.\n\t *\n\t * @param sc\n\t * @param p Command parameters (RAMROD_COMP_WAIT bit in\n\t * ramrod_flags is only taken into an account)\n\t * @param ppos a pointer to the cookie that should be given back in the\n\t * next call to make function handle the next element. If\n\t * *ppos is set to NULL it will restart the iterator.\n\t * If returned *ppos == NULL this means that the last\n\t * element has been handled.\n\t *\n\t * @return int\n\t */\n\tint (*restore)(struct bnx2x_softc *sc,\n\t\t struct ecore_vlan_mac_ramrod_params *p,\n\t\t struct ecore_vlan_mac_registry_elem **ppos);\n\n\t/**\n\t * Should be called on a completion arrival.\n\t *\n\t * @param sc\n\t * @param o\n\t * @param cqe Completion element we are handling\n\t * @param ramrod_flags if RAMROD_CONT is set the next bulk of\n\t *\t\t pending commands will be executed.\n\t *\t\t RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE\n\t *\t\t may also be set if needed.\n\t *\n\t * @return 0 if there are neither pending nor waiting for\n\t * completion commands. Positive value if there are\n\t * pending for execution or for completion commands.\n\t * Negative value in case of an error (including an\n\t * error in the cqe).\n\t */\n\tint (*complete)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o,\n\t\t\tunion event_ring_elem *cqe,\n\t\t\tunsigned long *ramrod_flags);\n\n\t/**\n\t * Wait for completion of all commands. Don't schedule new ones,\n\t * just wait. It assumes that the completion code will schedule\n\t * for new commands.\n\t */\n\tint (*wait)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o);\n};\n\nenum {\n\tECORE_LLH_CAM_ISCSI_ETH_LINE = 0,\n\tECORE_LLH_CAM_ETH_LINE,\n\tECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2\n};\n\n/** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */\n\n/* RX_MODE ramrod special flags: set in rx_mode_flags field in\n * a ecore_rx_mode_ramrod_params.\n */\nenum {\n\tECORE_RX_MODE_FCOE_ETH,\n\tECORE_RX_MODE_ISCSI_ETH,\n};\n\nenum {\n\tECORE_ACCEPT_UNICAST,\n\tECORE_ACCEPT_MULTICAST,\n\tECORE_ACCEPT_ALL_UNICAST,\n\tECORE_ACCEPT_ALL_MULTICAST,\n\tECORE_ACCEPT_BROADCAST,\n\tECORE_ACCEPT_UNMATCHED,\n\tECORE_ACCEPT_ANY_VLAN\n};\n\nstruct ecore_rx_mode_ramrod_params {\n\tstruct ecore_rx_mode_obj *rx_mode_obj;\n\tunsigned long *pstate;\n\tint state;\n\tuint8_t cl_id;\n\tuint32_t cid;\n\tuint8_t func_id;\n\tunsigned long ramrod_flags;\n\tunsigned long rx_mode_flags;\n\n\t/* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to\n\t * a tstorm_eth_mac_filter_config (e1x).\n\t */\n\tvoid *rdata;\n\tecore_dma_addr_t rdata_mapping;\n\n\t/* Rx mode settings */\n\tunsigned long rx_accept_flags;\n\n\t/* internal switching settings */\n\tunsigned long tx_accept_flags;\n};\n\nstruct ecore_rx_mode_obj {\n\tint (*config_rx_mode)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_rx_mode_ramrod_params *p);\n\n\tint (*wait_comp)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_rx_mode_ramrod_params *p);\n};\n\n/********************** Set multicast group ***********************************/\n\nstruct ecore_mcast_list_elem {\n\tecore_list_entry_t link;\n\tuint8_t *mac;\n};\n\nunion ecore_mcast_config_data {\n\tuint8_t *mac;\n\tuint8_t bin; /* used in a RESTORE flow */\n};\n\nstruct ecore_mcast_ramrod_params {\n\tstruct ecore_mcast_obj *mcast_obj;\n\n\t/* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */\n\tunsigned long ramrod_flags;\n\n\tecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */\n\tint mcast_list_len;\n};\n\nenum ecore_mcast_cmd {\n\tECORE_MCAST_CMD_ADD,\n\tECORE_MCAST_CMD_CONT,\n\tECORE_MCAST_CMD_DEL,\n\tECORE_MCAST_CMD_RESTORE,\n};\n\nstruct ecore_mcast_obj {\n\tstruct ecore_raw_obj raw;\n\n\tunion {\n\t\tstruct {\n\t\t#define ECORE_MCAST_BINS_NUM\t256\n\t\t#define ECORE_MCAST_VEC_SZ\t(ECORE_MCAST_BINS_NUM / 64)\n\t\t\tuint64_t vec[ECORE_MCAST_VEC_SZ];\n\n\t\t\t/** Number of BINs to clear. Should be updated\n\t\t\t * immediately when a command arrives in order to\n\t\t\t * properly create DEL commands.\n\t\t\t */\n\t\t\tint num_bins_set;\n\t\t} aprox_match;\n\n\t\tstruct {\n\t\t\tecore_list_t macs;\n\t\t\tint num_macs_set;\n\t\t} exact_match;\n\t} registry;\n\n\t/* Pending commands */\n\tecore_list_t pending_cmds_head;\n\n\t/* A state that is set in raw.pstate, when there are pending commands */\n\tint sched_state;\n\n\t/* Maximal number of mcast MACs configured in one command */\n\tint max_cmd_len;\n\n\t/* Total number of currently pending MACs to configure: both\n\t * in the pending commands list and in the current command.\n\t */\n\tint total_pending_num;\n\n\tuint8_t engine_id;\n\n\t/**\n\t * @param cmd command to execute (ECORE_MCAST_CMD_X, see above)\n\t */\n\tint (*config_mcast)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_mcast_ramrod_params *p,\n\t\t\t enum ecore_mcast_cmd cmd);\n\n\t/**\n\t * Fills the ramrod data during the RESTORE flow.\n\t *\n\t * @param sc\n\t * @param o\n\t * @param start_idx Registry index to start from\n\t * @param rdata_idx Index in the ramrod data to start from\n\t *\n\t * @return -1 if we handled the whole registry or index of the last\n\t * handled registry element.\n\t */\n\tint (*hdl_restore)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o,\n\t\t\t int start_bin, int *rdata_idx);\n\n\tint (*enqueue_cmd)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o,\n\t\t\t struct ecore_mcast_ramrod_params *p,\n\t\t\t enum ecore_mcast_cmd cmd);\n\n\tvoid (*set_one_rule)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_mcast_obj *o, int idx,\n\t\t\t union ecore_mcast_config_data *cfg_data,\n\t\t\t enum ecore_mcast_cmd cmd);\n\n\t/** Checks if there are more mcast MACs to be set or a previous\n\t * command is still pending.\n\t */\n\tint (*check_pending)(struct ecore_mcast_obj *o);\n\n\t/**\n\t * Set/Clear/Check SCHEDULED state of the object\n\t */\n\tvoid (*set_sched)(struct ecore_mcast_obj *o);\n\tvoid (*clear_sched)(struct ecore_mcast_obj *o);\n\tint (*check_sched)(struct ecore_mcast_obj *o);\n\n\t/* Wait until all pending commands complete */\n\tint (*wait_comp)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o);\n\n\t/**\n\t * Handle the internal object counters needed for proper\n\t * commands handling. Checks that the provided parameters are\n\t * feasible.\n\t */\n\tint (*validate)(struct bnx2x_softc *sc,\n\t\t\tstruct ecore_mcast_ramrod_params *p,\n\t\t\tenum ecore_mcast_cmd cmd);\n\n\t/**\n\t * Restore the values of internal counters in case of a failure.\n\t */\n\tvoid (*revert)(struct bnx2x_softc *sc,\n\t\t struct ecore_mcast_ramrod_params *p,\n\t\t int old_num_bins);\n\n\tint (*get_registry_size)(struct ecore_mcast_obj *o);\n\tvoid (*set_registry_size)(struct ecore_mcast_obj *o, int n);\n};\n\n/*************************** Credit handling **********************************/\nstruct ecore_credit_pool_obj {\n\n\t/* Current amount of credit in the pool */\n\tecore_atomic_t\tcredit;\n\n\t/* Maximum allowed credit. put() will check against it. */\n\tint\t\tpool_sz;\n\n\t/* Allocate a pool table statically.\n\t *\n\t * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272)\n\t *\n\t * The set bit in the table will mean that the entry is available.\n\t */\n#define ECORE_POOL_VEC_SIZE\t(MAX_MAC_CREDIT_E2 / 64)\n\tuint64_t\t\tpool_mirror[ECORE_POOL_VEC_SIZE];\n\n\t/* Base pool offset (initialized differently */\n\tint\t\tbase_pool_offset;\n\n\t/**\n\t * Get the next free pool entry.\n\t *\n\t * @return TRUE if there was a free entry in the pool\n\t */\n\tint (*get_entry)(struct ecore_credit_pool_obj *o, int *entry);\n\n\t/**\n\t * Return the entry back to the pool.\n\t *\n\t * @return TRUE if entry is legal and has been successfully\n\t * returned to the pool.\n\t */\n\tint (*put_entry)(struct ecore_credit_pool_obj *o, int entry);\n\n\t/**\n\t * Get the requested amount of credit from the pool.\n\t *\n\t * @param cnt Amount of requested credit\n\t * @return TRUE if the operation is successful\n\t */\n\tint (*get)(struct ecore_credit_pool_obj *o, int cnt);\n\n\t/**\n\t * Returns the credit to the pool.\n\t *\n\t * @param cnt Amount of credit to return\n\t * @return TRUE if the operation is successful\n\t */\n\tint (*put)(struct ecore_credit_pool_obj *o, int cnt);\n\n\t/**\n\t * Reads the current amount of credit.\n\t */\n\tint (*check)(struct ecore_credit_pool_obj *o);\n};\n\n/*************************** RSS configuration ********************************/\nenum {\n\t/* RSS_MODE bits are mutually exclusive */\n\tECORE_RSS_MODE_DISABLED,\n\tECORE_RSS_MODE_REGULAR,\n\n\tECORE_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */\n\n\tECORE_RSS_IPV4,\n\tECORE_RSS_IPV4_TCP,\n\tECORE_RSS_IPV4_UDP,\n\tECORE_RSS_IPV6,\n\tECORE_RSS_IPV6_TCP,\n\tECORE_RSS_IPV6_UDP,\n\n\tECORE_RSS_TUNNELING,\n};\n\nstruct ecore_config_rss_params {\n\tstruct ecore_rss_config_obj *rss_obj;\n\n\t/* may have RAMROD_COMP_WAIT set only */\n\tunsigned long\tramrod_flags;\n\n\t/* ECORE_RSS_X bits */\n\tunsigned long\trss_flags;\n\n\t/* Number hash bits to take into an account */\n\tuint8_t\t\trss_result_mask;\n\n\t/* Indirection table */\n\tuint8_t\t\tind_table[T_ETH_INDIRECTION_TABLE_SIZE];\n\n\t/* RSS hash values */\n\tuint32_t\t\trss_key[10];\n\n\t/* valid only iff ECORE_RSS_UPDATE_TOE is set */\n\tuint16_t\t\ttoe_rss_bitmap;\n\n\t/* valid iff ECORE_RSS_TUNNELING is set */\n\tuint16_t\t\ttunnel_value;\n\tuint16_t\t\ttunnel_mask;\n};\n\nstruct ecore_rss_config_obj {\n\tstruct ecore_raw_obj\traw;\n\n\t/* RSS engine to use */\n\tuint8_t\t\t\tengine_id;\n\n\t/* Last configured indirection table */\n\tuint8_t\t\t\tind_table[T_ETH_INDIRECTION_TABLE_SIZE];\n\n\t/* flags for enabling 4-tupple hash on UDP */\n\tuint8_t\t\t\tudp_rss_v4;\n\tuint8_t\t\t\tudp_rss_v6;\n\n\tint (*config_rss)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_config_rss_params *p);\n};\n\n/*********************** Queue state update ***********************************/\n\n/* UPDATE command options */\nenum {\n\tECORE_Q_UPDATE_IN_VLAN_REM,\n\tECORE_Q_UPDATE_IN_VLAN_REM_CHNG,\n\tECORE_Q_UPDATE_OUT_VLAN_REM,\n\tECORE_Q_UPDATE_OUT_VLAN_REM_CHNG,\n\tECORE_Q_UPDATE_ANTI_SPOOF,\n\tECORE_Q_UPDATE_ANTI_SPOOF_CHNG,\n\tECORE_Q_UPDATE_ACTIVATE,\n\tECORE_Q_UPDATE_ACTIVATE_CHNG,\n\tECORE_Q_UPDATE_DEF_VLAN_EN,\n\tECORE_Q_UPDATE_DEF_VLAN_EN_CHNG,\n\tECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG,\n\tECORE_Q_UPDATE_SILENT_VLAN_REM,\n\tECORE_Q_UPDATE_TX_SWITCHING_CHNG,\n\tECORE_Q_UPDATE_TX_SWITCHING,\n};\n\n/* Allowed Queue states */\nenum ecore_q_state {\n\tECORE_Q_STATE_RESET,\n\tECORE_Q_STATE_INITIALIZED,\n\tECORE_Q_STATE_ACTIVE,\n\tECORE_Q_STATE_MULTI_COS,\n\tECORE_Q_STATE_MCOS_TERMINATED,\n\tECORE_Q_STATE_INACTIVE,\n\tECORE_Q_STATE_STOPPED,\n\tECORE_Q_STATE_TERMINATED,\n\tECORE_Q_STATE_FLRED,\n\tECORE_Q_STATE_MAX,\n};\n\n/* Allowed Queue states */\nenum ecore_q_logical_state {\n\tECORE_Q_LOGICAL_STATE_ACTIVE,\n\tECORE_Q_LOGICAL_STATE_STOPPED,\n};\n\n/* Allowed commands */\nenum ecore_queue_cmd {\n\tECORE_Q_CMD_INIT,\n\tECORE_Q_CMD_SETUP,\n\tECORE_Q_CMD_SETUP_TX_ONLY,\n\tECORE_Q_CMD_DEACTIVATE,\n\tECORE_Q_CMD_ACTIVATE,\n\tECORE_Q_CMD_UPDATE,\n\tECORE_Q_CMD_UPDATE_TPA,\n\tECORE_Q_CMD_HALT,\n\tECORE_Q_CMD_CFC_DEL,\n\tECORE_Q_CMD_TERMINATE,\n\tECORE_Q_CMD_EMPTY,\n\tECORE_Q_CMD_MAX,\n};\n\n/* queue SETUP + INIT flags */\nenum {\n\tECORE_Q_FLG_TPA,\n\tECORE_Q_FLG_TPA_IPV6,\n\tECORE_Q_FLG_TPA_GRO,\n\tECORE_Q_FLG_STATS,\n\tECORE_Q_FLG_ZERO_STATS,\n\tECORE_Q_FLG_ACTIVE,\n\tECORE_Q_FLG_OV,\n\tECORE_Q_FLG_VLAN,\n\tECORE_Q_FLG_COS,\n\tECORE_Q_FLG_HC,\n\tECORE_Q_FLG_HC_EN,\n\tECORE_Q_FLG_DHC,\n\tECORE_Q_FLG_OOO,\n\tECORE_Q_FLG_FCOE,\n\tECORE_Q_FLG_LEADING_RSS,\n\tECORE_Q_FLG_MCAST,\n\tECORE_Q_FLG_DEF_VLAN,\n\tECORE_Q_FLG_TX_SWITCH,\n\tECORE_Q_FLG_TX_SEC,\n\tECORE_Q_FLG_ANTI_SPOOF,\n\tECORE_Q_FLG_SILENT_VLAN_REM,\n\tECORE_Q_FLG_FORCE_DEFAULT_PRI,\n\tECORE_Q_FLG_REFUSE_OUTBAND_VLAN,\n\tECORE_Q_FLG_PCSUM_ON_PKT,\n\tECORE_Q_FLG_TUN_INC_INNER_IP_ID\n};\n\n/* Queue type options: queue type may be a combination of below. */\nenum ecore_q_type {\n\tECORE_Q_TYPE_FWD,\n\tECORE_Q_TYPE_HAS_RX,\n\tECORE_Q_TYPE_HAS_TX,\n};\n\n#define ECORE_PRIMARY_CID_INDEX\t\t\t0\n#define ECORE_MULTI_TX_COS_E1X\t\t\t3 /* QM only */\n#define ECORE_MULTI_TX_COS_E2_E3A0\t\t2\n#define ECORE_MULTI_TX_COS_E3B0\t\t\t3\n#define ECORE_MULTI_TX_COS\t\t\t3 /* Maximum possible */\n#define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN)\n\nstruct ecore_queue_init_params {\n\tstruct {\n\t\tunsigned long\tflags;\n\t\tuint16_t\t\thc_rate;\n\t\tuint8_t\t\tfw_sb_id;\n\t\tuint8_t\t\tsb_cq_index;\n\t} tx;\n\n\tstruct {\n\t\tunsigned long\tflags;\n\t\tuint16_t\t\thc_rate;\n\t\tuint8_t\t\tfw_sb_id;\n\t\tuint8_t\t\tsb_cq_index;\n\t} rx;\n\n\t/* CID context in the host memory */\n\tstruct eth_context *cxts[ECORE_MULTI_TX_COS];\n\n\t/* maximum number of cos supported by hardware */\n\tuint8_t max_cos;\n};\n\nstruct ecore_queue_terminate_params {\n\t/* index within the tx_only cids of this queue object */\n\tuint8_t cid_index;\n};\n\nstruct ecore_queue_cfc_del_params {\n\t/* index within the tx_only cids of this queue object */\n\tuint8_t cid_index;\n};\n\nstruct ecore_queue_update_params {\n\tunsigned long\tupdate_flags; /* ECORE_Q_UPDATE_XX bits */\n\tuint16_t\t\tdef_vlan;\n\tuint16_t\t\tsilent_removal_value;\n\tuint16_t\t\tsilent_removal_mask;\n/* index within the tx_only cids of this queue object */\n\tuint8_t\t\tcid_index;\n};\n\nstruct rxq_pause_params {\n\tuint16_t\t\tbd_th_lo;\n\tuint16_t\t\tbd_th_hi;\n\tuint16_t\t\trcq_th_lo;\n\tuint16_t\t\trcq_th_hi;\n\tuint16_t\t\tsge_th_lo; /* valid iff ECORE_Q_FLG_TPA */\n\tuint16_t\t\tsge_th_hi; /* valid iff ECORE_Q_FLG_TPA */\n\tuint16_t\t\tpri_map;\n};\n\n/* general */\nstruct ecore_general_setup_params {\n\t/* valid iff ECORE_Q_FLG_STATS */\n\tuint8_t\t\tstat_id;\n\n\tuint8_t\t\tspcl_id;\n\tuint16_t\t\tmtu;\n\tuint8_t\t\tcos;\n};\n\nstruct ecore_rxq_setup_params {\n\t/* dma */\n\tecore_dma_addr_t\tdscr_map;\n\tecore_dma_addr_t\trcq_map;\n\tecore_dma_addr_t\trcq_np_map;\n\n\tuint16_t\t\tdrop_flags;\n\tuint16_t\t\tbuf_sz;\n\tuint8_t\t\tfw_sb_id;\n\tuint8_t\t\tcl_qzone_id;\n\n\t/* valid iff ECORE_Q_FLG_TPA */\n\tuint16_t\t\ttpa_agg_sz;\n\tuint8_t\t\tmax_tpa_queues;\n\tuint8_t\t\trss_engine_id;\n\n\t/* valid iff ECORE_Q_FLG_MCAST */\n\tuint8_t\t\tmcast_engine_id;\n\n\tuint8_t\t\tcache_line_log;\n\n\tuint8_t\t\tsb_cq_index;\n\n\t/* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */\n\tuint16_t silent_removal_value;\n\tuint16_t silent_removal_mask;\n};\n\nstruct ecore_txq_setup_params {\n\t/* dma */\n\tecore_dma_addr_t\tdscr_map;\n\n\tuint8_t\t\tfw_sb_id;\n\tuint8_t\t\tsb_cq_index;\n\tuint8_t\t\tcos;\t\t/* valid iff ECORE_Q_FLG_COS */\n\tuint16_t\t\ttraffic_type;\n\t/* equals to the leading rss client id, used for TX classification*/\n\tuint8_t\t\ttss_leading_cl_id;\n\n\t/* valid iff ECORE_Q_FLG_DEF_VLAN */\n\tuint16_t\t\tdefault_vlan;\n};\n\nstruct ecore_queue_setup_params {\n\tstruct ecore_general_setup_params gen_params;\n\tstruct ecore_txq_setup_params txq_params;\n\tstruct ecore_rxq_setup_params rxq_params;\n\tstruct rxq_pause_params pause_params;\n\tunsigned long flags;\n};\n\nstruct ecore_queue_setup_tx_only_params {\n\tstruct ecore_general_setup_params\tgen_params;\n\tstruct ecore_txq_setup_params\t\ttxq_params;\n\tunsigned long\t\t\t\tflags;\n\t/* index within the tx_only cids of this queue object */\n\tuint8_t\t\t\t\t\tcid_index;\n};\n\nstruct ecore_queue_state_params {\n\tstruct ecore_queue_sp_obj *q_obj;\n\n\t/* Current command */\n\tenum ecore_queue_cmd cmd;\n\n\t/* may have RAMROD_COMP_WAIT set only */\n\tunsigned long ramrod_flags;\n\n\t/* Params according to the current command */\n\tunion {\n\t\tstruct ecore_queue_update_params\tupdate;\n\t\tstruct ecore_queue_setup_params\t\tsetup;\n\t\tstruct ecore_queue_init_params\t\tinit;\n\t\tstruct ecore_queue_setup_tx_only_params\ttx_only;\n\t\tstruct ecore_queue_terminate_params\tterminate;\n\t\tstruct ecore_queue_cfc_del_params\tcfc_del;\n\t} params;\n};\n\nstruct ecore_viflist_params {\n\tuint8_t echo_res;\n\tuint8_t func_bit_map_res;\n};\n\nstruct ecore_queue_sp_obj {\n\tuint32_t\t\tcids[ECORE_MULTI_TX_COS];\n\tuint8_t\t\tcl_id;\n\tuint8_t\t\tfunc_id;\n\n\t/* number of traffic classes supported by queue.\n\t * The primary connection of the queue supports the first traffic\n\t * class. Any further traffic class is supported by a tx-only\n\t * connection.\n\t *\n\t * Therefore max_cos is also a number of valid entries in the cids\n\t * array.\n\t */\n\tuint8_t max_cos;\n\tuint8_t num_tx_only, next_tx_only;\n\n\tenum ecore_q_state state, next_state;\n\n\t/* bits from enum ecore_q_type */\n\tunsigned long\ttype;\n\n\t/* ECORE_Q_CMD_XX bits. This object implements \"one\n\t * pending\" paradigm but for debug and tracing purposes it's\n\t * more convenient to have different bits for different\n\t * commands.\n\t */\n\tunsigned long\tpending;\n\n\t/* Buffer to use as a ramrod data and its mapping */\n\tvoid\t\t*rdata;\n\tecore_dma_addr_t\trdata_mapping;\n\n\t/**\n\t * Performs one state change according to the given parameters.\n\t *\n\t * @return 0 in case of success and negative value otherwise.\n\t */\n\tint (*send_cmd)(struct bnx2x_softc *sc,\n\t\t\tstruct ecore_queue_state_params *params);\n\n\t/**\n\t * Sets the pending bit according to the requested transition.\n\t */\n\tint (*set_pending)(struct ecore_queue_sp_obj *o,\n\t\t\t struct ecore_queue_state_params *params);\n\n\t/**\n\t * Checks that the requested state transition is legal.\n\t */\n\tint (*check_transition)(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_queue_sp_obj *o,\n\t\t\t\tstruct ecore_queue_state_params *params);\n\n\t/**\n\t * Completes the pending command.\n\t */\n\tint (*complete_cmd)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_queue_sp_obj *o,\n\t\t\t enum ecore_queue_cmd);\n\n\tint (*wait_comp)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_queue_sp_obj *o,\n\t\t\t enum ecore_queue_cmd cmd);\n};\n\n/********************** Function state update *********************************/\n/* Allowed Function states */\nenum ecore_func_state {\n\tECORE_F_STATE_RESET,\n\tECORE_F_STATE_INITIALIZED,\n\tECORE_F_STATE_STARTED,\n\tECORE_F_STATE_TX_STOPPED,\n\tECORE_F_STATE_MAX,\n};\n\n/* Allowed Function commands */\nenum ecore_func_cmd {\n\tECORE_F_CMD_HW_INIT,\n\tECORE_F_CMD_START,\n\tECORE_F_CMD_STOP,\n\tECORE_F_CMD_HW_RESET,\n\tECORE_F_CMD_AFEX_UPDATE,\n\tECORE_F_CMD_AFEX_VIFLISTS,\n\tECORE_F_CMD_TX_STOP,\n\tECORE_F_CMD_TX_START,\n\tECORE_F_CMD_SWITCH_UPDATE,\n\tECORE_F_CMD_MAX,\n};\n\nstruct ecore_func_hw_init_params {\n\t/* A load phase returned by MCP.\n\t *\n\t * May be:\n\t *\t\tFW_MSG_CODE_DRV_LOAD_COMMON_CHIP\n\t *\t\tFW_MSG_CODE_DRV_LOAD_COMMON\n\t *\t\tFW_MSG_CODE_DRV_LOAD_PORT\n\t *\t\tFW_MSG_CODE_DRV_LOAD_FUNCTION\n\t */\n\tuint32_t load_phase;\n};\n\nstruct ecore_func_hw_reset_params {\n\t/* A load phase returned by MCP.\n\t *\n\t * May be:\n\t *\t\tFW_MSG_CODE_DRV_LOAD_COMMON_CHIP\n\t *\t\tFW_MSG_CODE_DRV_LOAD_COMMON\n\t *\t\tFW_MSG_CODE_DRV_LOAD_PORT\n\t *\t\tFW_MSG_CODE_DRV_LOAD_FUNCTION\n\t */\n\tuint32_t reset_phase;\n};\n\nstruct ecore_func_start_params {\n\t/* Multi Function mode:\n\t *\t- Single Function\n\t *\t- Switch Dependent\n\t *\t- Switch Independent\n\t */\n\tuint16_t mf_mode;\n\n\t/* Switch Dependent mode outer VLAN tag */\n\tuint16_t sd_vlan_tag;\n\n\t/* Function cos mode */\n\tuint8_t network_cos_mode;\n\n\t/* NVGRE classification enablement */\n\tuint8_t nvgre_clss_en;\n\n\t/* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */\n\tuint8_t gre_tunnel_mode;\n\n\t/* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */\n\tuint8_t gre_tunnel_rss;\n\n};\n\nstruct ecore_func_switch_update_params {\n\tuint8_t suspend;\n};\n\nstruct ecore_func_afex_update_params {\n\tuint16_t vif_id;\n\tuint16_t afex_default_vlan;\n\tuint8_t allowed_priorities;\n};\n\nstruct ecore_func_afex_viflists_params {\n\tuint16_t vif_list_index;\n\tuint8_t func_bit_map;\n\tuint8_t afex_vif_list_command;\n\tuint8_t func_to_clear;\n};\nstruct ecore_func_tx_start_params {\n\tstruct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];\n\tuint8_t dcb_enabled;\n\tuint8_t dcb_version;\n\tuint8_t dont_add_pri_0;\n};\n\nstruct ecore_func_state_params {\n\tstruct ecore_func_sp_obj *f_obj;\n\n\t/* Current command */\n\tenum ecore_func_cmd cmd;\n\n\t/* may have RAMROD_COMP_WAIT set only */\n\tunsigned long\tramrod_flags;\n\n\t/* Params according to the current command */\n\tunion {\n\t\tstruct ecore_func_hw_init_params hw_init;\n\t\tstruct ecore_func_hw_reset_params hw_reset;\n\t\tstruct ecore_func_start_params start;\n\t\tstruct ecore_func_switch_update_params switch_update;\n\t\tstruct ecore_func_afex_update_params afex_update;\n\t\tstruct ecore_func_afex_viflists_params afex_viflists;\n\t\tstruct ecore_func_tx_start_params tx_start;\n\t} params;\n};\n\nstruct ecore_func_sp_drv_ops {\n\t/* Init tool + runtime initialization:\n\t * - Common Chip\n\t * - Common (per Path)\n\t * - Port\n\t * - Function phases\n\t */\n\tint (*init_hw_cmn_chip)(struct bnx2x_softc *sc);\n\tint (*init_hw_cmn)(struct bnx2x_softc *sc);\n\tint (*init_hw_port)(struct bnx2x_softc *sc);\n\tint (*init_hw_func)(struct bnx2x_softc *sc);\n\n\t/* Reset Function HW: Common, Port, Function phases. */\n\tvoid (*reset_hw_cmn)(struct bnx2x_softc *sc);\n\tvoid (*reset_hw_port)(struct bnx2x_softc *sc);\n\tvoid (*reset_hw_func)(struct bnx2x_softc *sc);\n\n\t/* Prepare/Release FW resources */\n\tint (*init_fw)(struct bnx2x_softc *sc);\n\tvoid (*release_fw)(struct bnx2x_softc *sc);\n};\n\nstruct ecore_func_sp_obj {\n\tenum ecore_func_state\tstate, next_state;\n\n\t/* ECORE_FUNC_CMD_XX bits. This object implements \"one\n\t * pending\" paradigm but for debug and tracing purposes it's\n\t * more convenient to have different bits for different\n\t * commands.\n\t */\n\tunsigned long\t\tpending;\n\n\t/* Buffer to use as a ramrod data and its mapping */\n\tvoid\t\t\t*rdata;\n\tecore_dma_addr_t\t\trdata_mapping;\n\n\t/* Buffer to use as a afex ramrod data and its mapping.\n\t * This can't be same rdata as above because afex ramrod requests\n\t * can arrive to the object in parallel to other ramrod requests.\n\t */\n\tvoid\t\t\t*afex_rdata;\n\tecore_dma_addr_t\t\tafex_rdata_mapping;\n\n\t/* this mutex validates that when pending flag is taken, the next\n\t * ramrod to be sent will be the one set the pending bit\n\t */\n\tECORE_MUTEX\t\tone_pending_mutex;\n\n\t/* Driver interface */\n\tstruct ecore_func_sp_drv_ops\t*drv;\n\n\t/**\n\t * Performs one state change according to the given parameters.\n\t *\n\t * @return 0 in case of success and negative value otherwise.\n\t */\n\tint (*send_cmd)(struct bnx2x_softc *sc,\n\t\t\tstruct ecore_func_state_params *params);\n\n\t/**\n\t * Checks that the requested state transition is legal.\n\t */\n\tint (*check_transition)(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_func_sp_obj *o,\n\t\t\t\tstruct ecore_func_state_params *params);\n\n\t/**\n\t * Completes the pending command.\n\t */\n\tint (*complete_cmd)(struct bnx2x_softc *sc,\n\t\t\t struct ecore_func_sp_obj *o,\n\t\t\t enum ecore_func_cmd cmd);\n\n\tint (*wait_comp)(struct bnx2x_softc *sc, struct ecore_func_sp_obj *o,\n\t\t\t enum ecore_func_cmd cmd);\n};\n\n/********************** Interfaces ********************************************/\n/* Queueable objects set */\nunion ecore_qable_obj {\n\tstruct ecore_vlan_mac_obj vlan_mac;\n};\n/************** Function state update *********/\nvoid ecore_init_func_obj(struct bnx2x_softc *sc,\n\t\t\t struct ecore_func_sp_obj *obj,\n\t\t\t void *rdata, ecore_dma_addr_t rdata_mapping,\n\t\t\t void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping,\n\t\t\t struct ecore_func_sp_drv_ops *drv_iface);\n\nint ecore_func_state_change(struct bnx2x_softc *sc,\n\t\t\t struct ecore_func_state_params *params);\n\nenum ecore_func_state ecore_func_get_state(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_func_sp_obj *o);\n/******************* Queue State **************/\nvoid ecore_init_queue_obj(struct bnx2x_softc *sc,\n\t\t\t struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids,\n\t\t\t uint8_t cid_cnt, uint8_t func_id, void *rdata,\n\t\t\t ecore_dma_addr_t rdata_mapping, unsigned long type);\n\nint ecore_queue_state_change(struct bnx2x_softc *sc,\n\t\t\t struct ecore_queue_state_params *params);\n\n/********************* VLAN-MAC ****************/\nvoid ecore_init_mac_obj(struct bnx2x_softc *sc,\n\t\t\tstruct ecore_vlan_mac_obj *mac_obj,\n\t\t\tuint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,\n\t\t\tecore_dma_addr_t rdata_mapping, int state,\n\t\t\tunsigned long *pstate, ecore_obj_type type,\n\t\t\tstruct ecore_credit_pool_obj *macs_pool);\n\nvoid ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_vlan_mac_obj *o);\nint ecore_vlan_mac_h_write_lock(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_vlan_mac_obj *o);\nvoid ecore_vlan_mac_h_write_unlock(struct bnx2x_softc *sc,\n\t\t\t\t\t struct ecore_vlan_mac_obj *o);\nint ecore_config_vlan_mac(struct bnx2x_softc *sc,\n\t\t\t struct ecore_vlan_mac_ramrod_params *p);\n\nint ecore_vlan_mac_move(struct bnx2x_softc *sc,\n\t\t\tstruct ecore_vlan_mac_ramrod_params *p,\n\t\t\tstruct ecore_vlan_mac_obj *dest_o);\n\n/********************* RX MODE ****************/\n\nvoid ecore_init_rx_mode_obj(struct bnx2x_softc *sc,\n\t\t\t struct ecore_rx_mode_obj *o);\n\n/**\n * ecore_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters.\n *\n * @p: Command parameters\n *\n * Return: 0 - if operation was successful and there is no pending completions,\n * positive number - if there are pending completions,\n * negative - if there were errors\n */\nint ecore_config_rx_mode(struct bnx2x_softc *sc,\n\t\t\t struct ecore_rx_mode_ramrod_params *p);\n\n/****************** MULTICASTS ****************/\n\nvoid ecore_init_mcast_obj(struct bnx2x_softc *sc,\n\t\t\t struct ecore_mcast_obj *mcast_obj,\n\t\t\t uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id,\n\t\t\t uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping,\n\t\t\t int state, unsigned long *pstate,\n\t\t\t ecore_obj_type type);\n\n/**\n * ecore_config_mcast - Configure multicast MACs list.\n *\n * @cmd: command to execute: BNX2X_MCAST_CMD_X\n *\n * May configure a new list\n * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up\n * (ECORE_MCAST_CMD_DEL) or restore (ECORE_MCAST_CMD_RESTORE) a current\n * configuration, continue to execute the pending commands\n * (ECORE_MCAST_CMD_CONT).\n *\n * If previous command is still pending or if number of MACs to\n * configure is more that maximum number of MACs in one command,\n * the current command will be enqueued to the tail of the\n * pending commands list.\n *\n * Return: 0 is operation was successfull and there are no pending completions,\n * negative if there were errors, positive if there are pending\n * completions.\n */\nint ecore_config_mcast(struct bnx2x_softc *sc,\n\t\t struct ecore_mcast_ramrod_params *p,\n\t\t enum ecore_mcast_cmd cmd);\n\n/****************** CREDIT POOL ****************/\nvoid ecore_init_mac_credit_pool(struct bnx2x_softc *sc,\n\t\t\t\tstruct ecore_credit_pool_obj *p, uint8_t func_id,\n\t\t\t\tuint8_t func_num);\nvoid ecore_init_vlan_credit_pool(struct bnx2x_softc *sc,\n\t\t\t\t struct ecore_credit_pool_obj *p, uint8_t func_id,\n\t\t\t\t uint8_t func_num);\n\n/****************** RSS CONFIGURATION ****************/\nvoid ecore_init_rss_config_obj(struct ecore_rss_config_obj *rss_obj,\n\t\t\t uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id,\n\t\t\t void *rdata, ecore_dma_addr_t rdata_mapping,\n\t\t\t int state, unsigned long *pstate,\n\t\t\t ecore_obj_type type);\n\n/**\n * ecore_config_rss - Updates RSS configuration according to provided parameters\n *\n * Return: 0 in case of success\n */\nint ecore_config_rss(struct bnx2x_softc *sc,\n\t\t struct ecore_config_rss_params *p);\n\n\n#endif /* ECORE_SP_H */\n" }, { "path": "drivers/net/bnx2x/elink.c", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"bnx2x.h\"\n#include \"elink.h\"\n#include \"ecore_mfw_req.h\"\n#include \"ecore_fw_defs.h\"\n#include \"ecore_hsi.h\"\n#include \"ecore_reg.h\"\n\nstatic elink_status_t elink_link_reset(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars,\n\t\t\t\t uint8_t reset_ext_phy);\nstatic elink_status_t elink_check_half_open_conn(struct elink_params *params,\n\t\t\t\t\t\t struct elink_vars *vars,\n\t\t\t\t\t\t uint8_t notify);\nstatic elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n\t\t\t\t\t\t struct elink_params *params);\n\n#define MDIO_REG_BANK_CL73_IEEEB0\t\t\t0x0\n#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL\t\t0x0\n#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN\t0x0200\n#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN\t\t0x1000\n#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST\t0x8000\n\n#define MDIO_REG_BANK_CL73_IEEEB1\t\t\t0x10\n#define MDIO_CL73_IEEEB1_AN_ADV1\t\t\t0x00\n#define\tMDIO_CL73_IEEEB1_AN_ADV1_PAUSE\t\t\t0x0400\n#define\tMDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC \t\t0x0800\n#define\tMDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH\t\t0x0C00\n#define\tMDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK\t\t0x0C00\n#define MDIO_CL73_IEEEB1_AN_ADV2\t\t\t\t0x01\n#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M\t\t0x0000\n#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX\t\t0x0020\n#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4\t\t0x0040\n#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR\t\t0x0080\n#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1\t\t\t0x03\n#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE\t\t0x0400\n#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC \t\t0x0800\n#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH\t\t0x0C00\n#define\tMDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK\t\t0x0C00\n#define\tMDIO_CL73_IEEEB1_AN_LP_ADV2\t\t\t0x04\n\n#define\tMDIO_REG_BANK_RX0\t\t\t\t0x80b0\n#define\tMDIO_RX0_RX_STATUS\t\t\t\t0x10\n#define\tMDIO_RX0_RX_STATUS_SIGDET\t\t\t0x8000\n#define\tMDIO_RX0_RX_STATUS_RX_SEQ_DONE\t\t\t0x1000\n#define\tMDIO_RX0_RX_EQ_BOOST\t\t\t\t0x1c\n#define\tMDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n#define\tMDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL\t\t0x10\n\n#define\tMDIO_REG_BANK_RX1\t\t\t\t0x80c0\n#define\tMDIO_RX1_RX_EQ_BOOST\t\t\t\t0x1c\n#define\tMDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n#define\tMDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL\t\t0x10\n\n#define\tMDIO_REG_BANK_RX2\t\t\t\t0x80d0\n#define\tMDIO_RX2_RX_EQ_BOOST\t\t\t\t0x1c\n#define\tMDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n#define\tMDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL\t\t0x10\n\n#define\tMDIO_REG_BANK_RX3\t\t\t\t0x80e0\n#define\tMDIO_RX3_RX_EQ_BOOST\t\t\t\t0x1c\n#define\tMDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n#define\tMDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL\t\t0x10\n\n#define\tMDIO_REG_BANK_RX_ALL\t\t\t\t0x80f0\n#define\tMDIO_RX_ALL_RX_EQ_BOOST\t\t\t\t0x1c\n#define\tMDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK\t0x7\n#define\tMDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL\t0x10\n\n#define\tMDIO_REG_BANK_TX0\t\t\t\t0x8060\n#define\tMDIO_TX0_TX_DRIVER\t\t\t\t0x17\n#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK\t\t0xf000\n#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT\t\t12\n#define\tMDIO_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t0x0f00\n#define\tMDIO_TX0_TX_DRIVER_IDRIVER_SHIFT\t\t8\n#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_MASK\t\t0x00f0\n#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT\t\t4\n#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_MASK\t\t0x000e\n#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT\t\t1\n#define\tMDIO_TX0_TX_DRIVER_ICBUF1T\t\t\t1\n\n#define\tMDIO_REG_BANK_TX1\t\t\t\t0x8070\n#define\tMDIO_TX1_TX_DRIVER\t\t\t\t0x17\n#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK\t\t0xf000\n#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT\t\t12\n#define\tMDIO_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t0x0f00\n#define\tMDIO_TX0_TX_DRIVER_IDRIVER_SHIFT\t\t8\n#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_MASK\t\t0x00f0\n#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT\t\t4\n#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_MASK\t\t0x000e\n#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT\t\t1\n#define\tMDIO_TX0_TX_DRIVER_ICBUF1T\t\t\t1\n\n#define\tMDIO_REG_BANK_TX2\t\t\t\t0x8080\n#define\tMDIO_TX2_TX_DRIVER\t\t\t\t0x17\n#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK\t\t0xf000\n#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT\t\t12\n#define\tMDIO_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t0x0f00\n#define\tMDIO_TX0_TX_DRIVER_IDRIVER_SHIFT\t\t8\n#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_MASK\t\t0x00f0\n#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT\t\t4\n#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_MASK\t\t0x000e\n#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT\t\t1\n#define\tMDIO_TX0_TX_DRIVER_ICBUF1T\t\t\t1\n\n#define\tMDIO_REG_BANK_TX3\t\t\t\t0x8090\n#define\tMDIO_TX3_TX_DRIVER\t\t\t\t0x17\n#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK\t\t0xf000\n#define\tMDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT\t\t12\n#define\tMDIO_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t0x0f00\n#define\tMDIO_TX0_TX_DRIVER_IDRIVER_SHIFT\t\t8\n#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_MASK\t\t0x00f0\n#define\tMDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT\t\t4\n#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_MASK\t\t0x000e\n#define\tMDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT\t\t1\n#define\tMDIO_TX0_TX_DRIVER_ICBUF1T\t\t\t1\n\n#define\tMDIO_REG_BANK_XGXS_BLOCK0\t\t\t0x8000\n#define\tMDIO_BLOCK0_XGXS_CONTROL\t\t\t0x10\n\n#define\tMDIO_REG_BANK_XGXS_BLOCK1\t\t\t0x8010\n#define\tMDIO_BLOCK1_LANE_CTRL0\t\t\t\t0x15\n#define\tMDIO_BLOCK1_LANE_CTRL1\t\t\t\t0x16\n#define\tMDIO_BLOCK1_LANE_CTRL2\t\t\t\t0x17\n#define\tMDIO_BLOCK1_LANE_PRBS\t\t\t\t0x19\n\n#define\tMDIO_REG_BANK_XGXS_BLOCK2\t\t\t0x8100\n#define\tMDIO_XGXS_BLOCK2_RX_LN_SWAP\t\t\t0x10\n#define\tMDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE\t\t0x8000\n#define\tMDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE\t0x4000\n#define\tMDIO_XGXS_BLOCK2_TX_LN_SWAP\t\t0x11\n#define\tMDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE\t\t0x8000\n#define\tMDIO_XGXS_BLOCK2_UNICORE_MODE_10G\t0x14\n#define\tMDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS\t0x0001\n#define\tMDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS\t0x0010\n#define\tMDIO_XGXS_BLOCK2_TEST_MODE_LANE\t\t0x15\n\n#define\tMDIO_REG_BANK_GP_STATUS\t\t\t\t0x8120\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1\t\t\t\t0x1B\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE\t0x0001\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE\t0x0002\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS\t\t0x0004\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS\t\t0x0008\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE\t0x0010\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE\t0x0020\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE\t0x0040\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE\t0x0080\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK\t\t0x3f00\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M\t\t0x0000\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M\t\t0x0100\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G\t\t0x0200\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G\t\t0x0300\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G\t\t0x0400\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G\t\t0x0500\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG\t0x0600\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4\t0x0700\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG\t0x0800\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G\t0x0900\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G\t\t0x0A00\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G\t\t0x0B00\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G\t\t0x0C00\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX\t0x0D00\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4\t0x0E00\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR\t0x0F00\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI\t0x1B00\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS\t0x1E00\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI\t0x1F00\n#define\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2\t0x3900\n\n#define\tMDIO_REG_BANK_10G_PARALLEL_DETECT\t\t0x8130\n#define\tMDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS\t\t0x10\n#define\tMDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK\t\t0x8000\n#define\tMDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL\t\t0x11\n#define\tMDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN\t0x1\n#define\tMDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK\t\t0x13\n#define\tMDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT\t\t(0xb71<<1)\n\n#define\tMDIO_REG_BANK_SERDES_DIGITAL\t\t\t0x8300\n#define\tMDIO_SERDES_DIGITAL_A_1000X_CONTROL1\t\t\t0x10\n#define\tMDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE\t\t\t0x0001\n#define\tMDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF\t\t\t0x0002\n#define\tMDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN\t\t0x0004\n#define\tMDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT\t0x0008\n#define\tMDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET\t\t\t0x0010\n#define\tMDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE\t\t\t0x0020\n#define\tMDIO_SERDES_DIGITAL_A_1000X_CONTROL2\t\t\t0x11\n#define\tMDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN\t\t\t0x0001\n#define\tMDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR\t\t\t0x0040\n#define\tMDIO_SERDES_DIGITAL_A_1000X_STATUS1\t\t\t0x14\n#define\tMDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII\t\t\t0x0001\n#define\tMDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK\t\t\t0x0002\n#define\tMDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX\t\t\t0x0004\n#define\tMDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK\t\t\t0x0018\n#define\tMDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT\t\t\t3\n#define\tMDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G\t\t\t0x0018\n#define\tMDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G\t\t\t0x0010\n#define\tMDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M\t\t\t0x0008\n#define\tMDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M\t\t\t0x0000\n#define\tMDIO_SERDES_DIGITAL_A_1000X_STATUS2\t\t\t0x15\n#define\tMDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED\t\t\t0x0002\n#define\tMDIO_SERDES_DIGITAL_MISC1\t\t\t\t0x18\n#define\tMDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK\t\t\t0xE000\n#define\tMDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M\t\t\t0x0000\n#define\tMDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M\t\t\t0x2000\n#define\tMDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M\t\t\t0x4000\n#define\tMDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M\t\t\t0x6000\n#define\tMDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M\t\t\t0x8000\n#define\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL\t\t\t0x0010\n#define\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK\t\t\t0x000f\n#define\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G\t\t\t0x0000\n#define\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G\t\t\t0x0001\n#define\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G\t\t\t0x0002\n#define\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG\t\t\t0x0003\n#define\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4\t\t\t0x0004\n#define\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G\t\t\t0x0005\n#define\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G\t\t\t0x0006\n#define\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G\t\t\t0x0007\n#define\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G\t\t\t0x0008\n#define\tMDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G\t\t\t0x0009\n\n#define\tMDIO_REG_BANK_OVER_1G\t\t\t\t0x8320\n#define\tMDIO_OVER_1G_DIGCTL_3_4\t\t\t\t\t0x14\n#define\tMDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK\t\t\t\t0xffe0\n#define\tMDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT\t\t\t\t5\n#define\tMDIO_OVER_1G_UP1\t\t\t\t\t0x19\n#define\tMDIO_OVER_1G_UP1_2_5G\t\t\t\t\t\t0x0001\n#define\tMDIO_OVER_1G_UP1_5G\t\t\t\t\t\t0x0002\n#define\tMDIO_OVER_1G_UP1_6G\t\t\t\t\t\t0x0004\n#define\tMDIO_OVER_1G_UP1_10G\t\t\t\t\t\t0x0010\n#define\tMDIO_OVER_1G_UP1_10GH\t\t\t\t\t\t0x0008\n#define\tMDIO_OVER_1G_UP1_12G\t\t\t\t\t\t0x0020\n#define\tMDIO_OVER_1G_UP1_12_5G\t\t\t\t\t\t0x0040\n#define\tMDIO_OVER_1G_UP1_13G\t\t\t\t\t\t0x0080\n#define\tMDIO_OVER_1G_UP1_15G\t\t\t\t\t\t0x0100\n#define\tMDIO_OVER_1G_UP1_16G\t\t\t\t\t\t0x0200\n#define\tMDIO_OVER_1G_UP2\t\t\t\t\t0x1A\n#define\tMDIO_OVER_1G_UP2_IPREDRIVER_MASK\t\t\t\t0x0007\n#define\tMDIO_OVER_1G_UP2_IDRIVER_MASK\t\t\t\t\t0x0038\n#define\tMDIO_OVER_1G_UP2_PREEMPHASIS_MASK\t\t\t\t0x03C0\n#define\tMDIO_OVER_1G_UP3\t\t\t\t\t0x1B\n#define\tMDIO_OVER_1G_UP3_HIGIG2\t\t\t\t\t\t0x0001\n#define\tMDIO_OVER_1G_LP_UP1\t\t\t\t\t0x1C\n#define\tMDIO_OVER_1G_LP_UP2\t\t\t\t\t0x1D\n#define\tMDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK\t\t\t\t0x03ff\n#define\tMDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK\t\t\t\t0x0780\n#define\tMDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT\t\t\t\t7\n#define\tMDIO_OVER_1G_LP_UP3\t\t\t\t\t\t0x1E\n\n#define\tMDIO_REG_BANK_REMOTE_PHY\t\t\t0x8330\n#define\tMDIO_REMOTE_PHY_MISC_RX_STATUS\t\t\t\t0x10\n#define\tMDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG\t0x0010\n#define\tMDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG\t0x0600\n\n#define\tMDIO_REG_BANK_BAM_NEXT_PAGE\t\t\t0x8350\n#define\tMDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL\t\t\t0x10\n#define\tMDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE\t\t\t0x0001\n#define\tMDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN\t\t\t0x0002\n\n#define\tMDIO_REG_BANK_CL73_USERB0\t\t0x8370\n#define\tMDIO_CL73_USERB0_CL73_UCTRL\t\t\t\t0x10\n#define\tMDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL\t\t\t0x0002\n#define\tMDIO_CL73_USERB0_CL73_USTAT1\t\t\t\t0x11\n#define\tMDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK\t\t\t0x0100\n#define\tMDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37\t\t0x0400\n#define\tMDIO_CL73_USERB0_CL73_BAM_CTRL1\t\t\t\t0x12\n#define\tMDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN\t\t\t\t0x8000\n#define\tMDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN\t\t0x4000\n#define\tMDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN\t\t0x2000\n#define\tMDIO_CL73_USERB0_CL73_BAM_CTRL3\t\t\t\t0x14\n#define\tMDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR\t\t\t0x0001\n\n#define\tMDIO_REG_BANK_AER_BLOCK\t\t\t0xFFD0\n#define\tMDIO_AER_BLOCK_AER_REG\t\t\t\t\t0x1E\n\n#define\tMDIO_REG_BANK_COMBO_IEEE0\t\t0xFFE0\n#define\tMDIO_COMBO_IEEE0_MII_CONTROL\t\t\t\t0x10\n#define\tMDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK\t\t\t0x2040\n#define\tMDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10\t\t\t0x0000\n#define\tMDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100\t\t\t0x2000\n#define\tMDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000\t\t\t0x0040\n#define\tMDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX\t\t\t\t0x0100\n#define\tMDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN\t\t\t\t0x0200\n#define\tMDIO_COMBO_IEEO_MII_CONTROL_AN_EN\t\t\t\t0x1000\n#define\tMDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK\t\t\t\t0x4000\n#define\tMDIO_COMBO_IEEO_MII_CONTROL_RESET\t\t\t\t0x8000\n#define\tMDIO_COMBO_IEEE0_MII_STATUS\t\t\t\t0x11\n#define\tMDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS\t\t\t\t0x0004\n#define\tMDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE\t\t\t0x0020\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV\t\t\t\t0x14\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX\t\t\t0x0020\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX\t\t\t0x0040\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK\t\t\t0x0180\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE\t\t\t0x0000\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC\t\t\t0x0080\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC\t\t\t0x0100\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH\t\t\t0x0180\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE\t\t\t\t0x8000\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1\t\t0x15\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE\t0x8000\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK\t\t0x4000\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK\t0x0180\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE\t0x0000\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH\t0x0180\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP\t0x0040\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP\t0x0020\n/*WhenthelinkpartnerisinSGMIImode(bit0=1),then\nbit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.\nTheotherbitsarereservedandshouldbezero*/\n#define\tMDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE\t0x0001\n\n#define\tMDIO_PMA_DEVAD\t\t\t0x1\n/*ieee*/\n#define\tMDIO_PMA_REG_CTRL\t\t0x0\n#define\tMDIO_PMA_REG_STATUS\t\t0x1\n#define\tMDIO_PMA_REG_10G_CTRL2\t\t0x7\n#define MDIO_PMA_REG_TX_DISABLE\t\t0x0009\n#define\tMDIO_PMA_REG_RX_SD\t\t0xa\n/*bnx2x*/\n#define\tMDIO_PMA_REG_BNX2X_CTRL\t\t0x0096\n#define MDIO_PMA_REG_FEC_CTRL\t\t0x00ab\n#define\tMDIO_PMA_LASI_RXCTRL\t\t0x9000\n#define\tMDIO_PMA_LASI_TXCTRL\t\t0x9001\n#define\tMDIO_PMA_LASI_CTRL\t\t0x9002\n#define\tMDIO_PMA_LASI_RXSTAT\t\t0x9003\n#define\tMDIO_PMA_LASI_TXSTAT\t\t0x9004\n#define\tMDIO_PMA_LASI_STAT\t\t0x9005\n#define\tMDIO_PMA_REG_PHY_IDENTIFIER\t0xc800\n#define\tMDIO_PMA_REG_DIGITAL_CTRL\t0xc808\n#define\tMDIO_PMA_REG_DIGITAL_STATUS\t0xc809\n#define\tMDIO_PMA_REG_TX_POWER_DOWN\t0xca02\n#define\tMDIO_PMA_REG_CMU_PLL_BYPASS\t0xca09\n#define\tMDIO_PMA_REG_MISC_CTRL\t\t0xca0a\n#define\tMDIO_PMA_REG_GEN_CTRL\t\t0xca10\n#define\tMDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP\t0x0188\n#define\tMDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET\t\t0x018a\n#define\tMDIO_PMA_REG_M8051_MSGIN_REG\t0xca12\n#define\tMDIO_PMA_REG_M8051_MSGOUT_REG\t0xca13\n#define\tMDIO_PMA_REG_ROM_VER1\t\t0xca19\n#define\tMDIO_PMA_REG_ROM_VER2\t\t0xca1a\n#define\tMDIO_PMA_REG_EDC_FFE_MAIN\t0xca1b\n#define\tMDIO_PMA_REG_PLL_BANDWIDTH\t0xca1d\n#define MDIO_PMA_REG_PLL_CTRL \t\t0xca1e\n#define MDIO_PMA_REG_MISC_CTRL0 \t0xca23\n#define MDIO_PMA_REG_LRM_MODE\t \t0xca3f\n#define\tMDIO_PMA_REG_CDR_BANDWIDTH \t0xca46\n#define\tMDIO_PMA_REG_MISC_CTRL1\t\t0xca85\n\n#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL\t\t0x8000\n#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK \t0x000c\n#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE \t\t0x0000\n#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE \t0x0004\n#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS \t0x0008\n#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED \t0x000c\n#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT \t0x8002\n#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR \t0x8003\n#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF\t0xc820\n#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff\n#define MDIO_PMA_REG_8726_TX_CTRL1\t\t0xca01\n#define MDIO_PMA_REG_8726_TX_CTRL2\t\t0xca05\n\n#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR\t0x8005\n#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF\t0x8007\n#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff\n#define MDIO_PMA_REG_8727_MISC_CTRL\t\t0x8309\n#define MDIO_PMA_REG_8727_TX_CTRL1\t\t0xca02\n#define MDIO_PMA_REG_8727_TX_CTRL2\t\t0xca05\n#define MDIO_PMA_REG_8727_PCS_OPT_CTRL\t\t0xc808\n#define MDIO_PMA_REG_8727_GPIO_CTRL\t\t0xc80e\n#define MDIO_PMA_REG_8727_PCS_GP\t\t0xc842\n#define MDIO_PMA_REG_8727_OPT_CFG_REG\t\t0xc8e4\n\n#define MDIO_AN_REG_8727_MISC_CTRL\t\t0x8309\n#define\tMDIO_PMA_REG_8073_CHIP_REV\t\t\t0xc801\n#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS\t\t0xc820\n#define MDIO_PMA_REG_8073_XAUI_WA \t\t\t0xc841\n#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL \t\t0xcd08\n\n#define MDIO_PMA_REG_7101_RESET\t\t0xc000\n#define\tMDIO_PMA_REG_7107_LED_CNTL\t0xc007\n#define\tMDIO_PMA_REG_7107_LINK_LED_CNTL\t0xc009\n#define\tMDIO_PMA_REG_7101_VER1\t\t0xc026\n#define\tMDIO_PMA_REG_7101_VER2\t\t0xc027\n\n#define MDIO_PMA_REG_8481_PMD_SIGNAL\t0xa811\n#define MDIO_PMA_REG_8481_LED1_MASK\t0xa82c\n#define MDIO_PMA_REG_8481_LED2_MASK\t0xa82f\n#define MDIO_PMA_REG_8481_LED3_MASK\t0xa832\n#define MDIO_PMA_REG_8481_LED3_BLINK\t0xa834\n#define MDIO_PMA_REG_8481_LED5_MASK\t 0xa838\n#define MDIO_PMA_REG_8481_SIGNAL_MASK\t0xa835\n#define MDIO_PMA_REG_8481_LINK_SIGNAL\t0xa83b\n#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK\t0x800\n#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT\t11\n\n#define\tMDIO_WIS_DEVAD\t\t\t0x2\n/*bnx2x*/\n#define\tMDIO_WIS_REG_LASI_CNTL\t\t0x9002\n#define\tMDIO_WIS_REG_LASI_STATUS\t0x9005\n\n#define\tMDIO_PCS_DEVAD\t\t\t0x3\n#define\tMDIO_PCS_REG_STATUS\t\t0x0020\n#define MDIO_PCS_REG_LASI_STATUS\t0x9005\n#define MDIO_PCS_REG_7101_DSP_ACCESS\t0xD000\n#define MDIO_PCS_REG_7101_SPI_MUX \t0xD008\n#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A\n#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)\n#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A\n#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)\n#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)\n#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)\n#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028\n\n#define\tMDIO_XS_DEVAD\t\t\t0x4\n#define\tMDIO_XS_REG_STATUS\t\t0x0001\n#define MDIO_XS_PLL_SEQUENCER \t\t0x8000\n#define\tMDIO_XS_SFX7101_XGXS_TEST1\t0xc00a\n\n#define MDIO_XS_8706_REG_BANK_RX0\t0x80bc\n#define MDIO_XS_8706_REG_BANK_RX1\t0x80cc\n#define MDIO_XS_8706_REG_BANK_RX2\t0x80dc\n#define MDIO_XS_8706_REG_BANK_RX3\t0x80ec\n#define MDIO_XS_8706_REG_BANK_RXA\t0x80fc\n\n#define MDIO_XS_REG_8073_RX_CTRL_PCIE\t0x80FA\n\n#define\tMDIO_AN_DEVAD\t\t\t0x7\n/*ieee*/\n#define\tMDIO_AN_REG_CTRL\t\t0x0000\n#define\tMDIO_AN_REG_STATUS\t\t0x0001\n#define\tMDIO_AN_REG_STATUS_AN_COMPLETE\t\t0x0020\n#define\tMDIO_AN_REG_ADV_PAUSE\t\t0x0010\n#define\tMDIO_AN_REG_ADV_PAUSE_PAUSE\t\t0x0400\n#define\tMDIO_AN_REG_ADV_PAUSE_ASYMMETRIC\t0x0800\n#define\tMDIO_AN_REG_ADV_PAUSE_BOTH\t\t0x0C00\n#define\tMDIO_AN_REG_ADV_PAUSE_MASK\t\t0x0C00\n#define\tMDIO_AN_REG_ADV\t\t\t0x0011\n#define MDIO_AN_REG_ADV2\t\t0x0012\n#define\tMDIO_AN_REG_LP_AUTO_NEG\t\t0x0013\n#define\tMDIO_AN_REG_LP_AUTO_NEG2\t0x0014\n#define\tMDIO_AN_REG_MASTER_STATUS\t0x0021\n#define\tMDIO_AN_REG_EEE_ADV\t\t0x003c\n#define\tMDIO_AN_REG_LP_EEE_ADV\t\t0x003d\n/*bnx2x*/\n#define\tMDIO_AN_REG_LINK_STATUS\t\t0x8304\n#define\tMDIO_AN_REG_CL37_CL73\t\t0x8370\n#define\tMDIO_AN_REG_CL37_AN\t\t0xffe0\n#define\tMDIO_AN_REG_CL37_FC_LD\t\t0xffe4\n#define \tMDIO_AN_REG_CL37_FC_LP\t\t0xffe5\n#define \tMDIO_AN_REG_1000T_STATUS\t0xffea\n\n#define MDIO_AN_REG_8073_2_5G\t\t0x8329\n#define MDIO_AN_REG_8073_BAM\t\t0x8350\n\n#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL\t0x0020\n#define MDIO_AN_REG_8481_LEGACY_MII_CTRL\t0xffe0\n#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G\t0x40\n#define MDIO_AN_REG_8481_LEGACY_MII_STATUS\t0xffe1\n#define MDIO_AN_REG_8481_LEGACY_AN_ADV\t\t0xffe4\n#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION\t0xffe6\n#define MDIO_AN_REG_8481_1000T_CTRL\t\t0xffe9\n#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL\t0xfff0\n#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF\t0x0008\n#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW\t0xfff5\n#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS\t0xfff7\n#define MDIO_AN_REG_8481_AUX_CTRL\t\t0xfff8\n#define MDIO_AN_REG_8481_LEGACY_SHADOW\t\t0xfffc\n\n/* BNX2X84823 only */\n#define\tMDIO_CTL_DEVAD\t\t\t0x1e\n#define MDIO_CTL_REG_84823_MEDIA\t\t0x401a\n#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK\t\t0x0018\n\t/* These pins configure the BNX2X84823 interface to MAC after reset. */\n#define MDIO_CTL_REG_84823_CTRL_MAC_XFI\t\t\t0x0008\n#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M\t\t0x0010\n\t/* These pins configure the BNX2X84823 interface to Line after reset. */\n#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK\t\t0x0060\n#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L\t\t0x0020\n#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI\t\t0x0040\n\t/* When this pin is active high during reset, 10GBASE-T core is power\n\t * down, When it is active low the 10GBASE-T is power up\n\t */\n#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN\t0x0080\n#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK\t\t0x0100\n#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER\t0x0000\n#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER\t\t0x0100\n#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G\t\t\t0x1000\n#define MDIO_CTL_REG_84823_USER_CTRL_REG\t\t\t0x4005\n#define MDIO_CTL_REG_84823_USER_CTRL_CMS\t\t\t0x0080\n#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH\t\t0xa82b\n#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ\t0x2f\n#define MDIO_PMA_REG_84823_CTL_LED_CTL_1\t\t\t0xa8e3\n#define MDIO_PMA_REG_84833_CTL_LED_CTL_1\t\t\t0xa8ec\n#define MDIO_PMA_REG_84823_LED3_STRETCH_EN\t\t\t0x0080\n\n/* BNX2X84833 only */\n#define MDIO_84833_TOP_CFG_FW_REV\t\t\t0x400f\n#define MDIO_84833_TOP_CFG_FW_EEE\t\t0x10b1\n#define MDIO_84833_TOP_CFG_FW_NO_EEE\t\t0x1f81\n#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 \t\t0x401a\n#define MDIO_84833_SUPER_ISOLATE \t\t0x8000\n/* These are mailbox register set used by 84833. */\n#define MDIO_84833_TOP_CFG_SCRATCH_REG0\t\t\t0x4005\n#define MDIO_84833_TOP_CFG_SCRATCH_REG1 \t\t0x4006\n#define MDIO_84833_TOP_CFG_SCRATCH_REG2\t\t\t0x4007\n#define MDIO_84833_TOP_CFG_SCRATCH_REG3\t\t\t0x4008\n#define MDIO_84833_TOP_CFG_SCRATCH_REG4\t\t\t0x4009\n#define MDIO_84833_TOP_CFG_SCRATCH_REG26\t\t0x4037\n#define MDIO_84833_TOP_CFG_SCRATCH_REG27\t\t0x4038\n#define MDIO_84833_TOP_CFG_SCRATCH_REG28\t\t0x4039\n#define MDIO_84833_TOP_CFG_SCRATCH_REG29\t\t0x403a\n#define MDIO_84833_TOP_CFG_SCRATCH_REG30\t\t0x403b\n#define MDIO_84833_TOP_CFG_SCRATCH_REG31\t\t0x403c\n#define MDIO_84833_CMD_HDLR_COMMAND\tMDIO_84833_TOP_CFG_SCRATCH_REG0\n#define MDIO_84833_CMD_HDLR_STATUS\tMDIO_84833_TOP_CFG_SCRATCH_REG26\n#define MDIO_84833_CMD_HDLR_DATA1\tMDIO_84833_TOP_CFG_SCRATCH_REG27\n#define MDIO_84833_CMD_HDLR_DATA2\tMDIO_84833_TOP_CFG_SCRATCH_REG28\n#define MDIO_84833_CMD_HDLR_DATA3\tMDIO_84833_TOP_CFG_SCRATCH_REG29\n#define MDIO_84833_CMD_HDLR_DATA4\tMDIO_84833_TOP_CFG_SCRATCH_REG30\n#define MDIO_84833_CMD_HDLR_DATA5\tMDIO_84833_TOP_CFG_SCRATCH_REG31\n\n/* Mailbox command set used by 84833. */\n#define PHY84833_CMD_SET_PAIR_SWAP\t\t\t0x8001\n#define PHY84833_CMD_GET_EEE_MODE\t\t\t0x8008\n#define PHY84833_CMD_SET_EEE_MODE\t\t\t0x8009\n#define PHY84833_CMD_GET_CURRENT_TEMP\t\t\t0x8031\n/* Mailbox status set used by 84833. */\n#define PHY84833_STATUS_CMD_RECEIVED\t\t\t0x0001\n#define PHY84833_STATUS_CMD_IN_PROGRESS\t\t\t0x0002\n#define PHY84833_STATUS_CMD_COMPLETE_PASS\t\t0x0004\n#define PHY84833_STATUS_CMD_COMPLETE_ERROR\t\t0x0008\n#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS\t\t0x0010\n#define PHY84833_STATUS_CMD_SYSTEM_BOOT\t\t\t0x0020\n#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS\t\t0x0040\n#define PHY84833_STATUS_CMD_CLEAR_COMPLETE\t\t0x0080\n#define PHY84833_STATUS_CMD_OPEN_OVERRIDE\t\t0xa5a5\n\n/* Warpcore clause 45 addressing */\n#define MDIO_WC_DEVAD\t\t\t\t\t0x3\n#define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0\n#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7\n#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10\n#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11\n#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12\n#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY\t0x4000\n#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ\t\t0x8000\n#define MDIO_WC_REG_PCS_STATUS2\t\t\t\t0x0021\n#define MDIO_WC_REG_PMD_KR_CONTROL\t\t\t0x0096\n#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000\n#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e\n#define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010\n#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015\n#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016\n#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017\n#define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018\n#define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a\n#define MDIO_WC_REG_TX0_ANA_CTRL0\t\t\t0x8061\n#define MDIO_WC_REG_TX1_ANA_CTRL0\t\t\t0x8071\n#define MDIO_WC_REG_TX2_ANA_CTRL0\t\t\t0x8081\n#define MDIO_WC_REG_TX3_ANA_CTRL0\t\t\t0x8091\n#define MDIO_WC_REG_TX0_TX_DRIVER\t\t\t0x8067\n#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET\t\t0x04\n#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK\t\t\t0x00f0\n#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET\t\t0x08\n#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK\t\t\t\t0x0f00\n#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET\t\t0x0c\n#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK\t\t\t0x7000\n#define MDIO_WC_REG_TX1_TX_DRIVER\t\t\t0x8077\n#define MDIO_WC_REG_TX2_TX_DRIVER\t\t\t0x8087\n#define MDIO_WC_REG_TX3_TX_DRIVER\t\t\t0x8097\n#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9\n#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9\n#define MDIO_WC_REG_RX0_PCI_CTRL\t\t\t0x80ba\n#define MDIO_WC_REG_RX1_PCI_CTRL\t\t\t0x80ca\n#define MDIO_WC_REG_RX2_PCI_CTRL\t\t\t0x80da\n#define MDIO_WC_REG_RX3_PCI_CTRL\t\t\t0x80ea\n#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G \t\t0x8104\n#define MDIO_WC_REG_XGXS_STATUS3\t\t\t0x8129\n#define MDIO_WC_REG_PAR_DET_10G_STATUS\t\t\t0x8130\n#define MDIO_WC_REG_PAR_DET_10G_CTRL\t\t\t0x8131\n#define MDIO_WC_REG_XGXS_STATUS4 0x813c\n#define MDIO_WC_REG_XGXS_X2_CONTROL2 \t\t 0x8141\n#define MDIO_WC_REG_XGXS_X2_CONTROL3 \t\t 0x8142\n#define MDIO_WC_REG_XGXS_RX_LN_SWAP1\t\t \t0x816B\n#define MDIO_WC_REG_XGXS_TX_LN_SWAP1\t\t \t0x8169\n#define MDIO_WC_REG_GP2_STATUS_GP_2_0\t\t\t0x81d0\n#define MDIO_WC_REG_GP2_STATUS_GP_2_1\t\t\t0x81d1\n#define MDIO_WC_REG_GP2_STATUS_GP_2_2\t\t\t0x81d2\n#define MDIO_WC_REG_GP2_STATUS_GP_2_3\t\t\t0x81d3\n#define MDIO_WC_REG_GP2_STATUS_GP_2_4\t\t\t0x81d4\n#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000\n#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100\n#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010\n#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1\n#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE\n#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0\n#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE\t\t0x81F2\n#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET\t0x0\n#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0\n#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1\n#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2\n#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3\n#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4\n#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET\t0x4\n#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET\t0x8\n#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET\t0xc\n#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE\n#define MDIO_WC_REG_DSC1B0_UC_CTRL\t\t\t\t0x820e\n#define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD\t\t\t(1<<7)\n#define MDIO_WC_REG_DSC_SMC\t\t\t\t0x8213\n#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0\t\t0x821e\n#define MDIO_WC_REG_TX_FIR_TAP\t\t\t\t0x82e2\n#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET\t\t0x00\n#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK\t\t\t0x000f\n#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET\t\t0x04\n#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK\t\t0x03f0\n#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET\t\t0x0a\n#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK\t\t0x7c00\n#define MDIO_WC_REG_TX_FIR_TAP_ENABLE\t\t0x8000\n#define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP\t\t0x82e2\n#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3\n#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL\t0x82e6\n#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL\t0x82e7\n#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL\t0x82e8\n#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec\n#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300\n#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301\n#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302\n#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304\n#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308\n#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309\n#define MDIO_WC_REG_DIGITAL3_UP1 0x8329\n#define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c\n#define MDIO_WC_REG_DIGITAL4_MISC3 0x833c\n#define MDIO_WC_REG_DIGITAL4_MISC5 0x833e\n#define MDIO_WC_REG_DIGITAL5_MISC6 0x8345\n#define MDIO_WC_REG_DIGITAL5_MISC7 0x8349\n#define MDIO_WC_REG_DIGITAL5_LINK_STATUS\t\t0x834d\n#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e\n#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350\n#define MDIO_WC_REG_CL49_USERB0_CTRL\t 0x8368\n#define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370\n#define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371\n#define MDIO_WC_REG_CL73_BAM_CTRL1\t\t\t0x8372\n#define MDIO_WC_REG_CL73_BAM_CTRL2\t\t\t0x8373\n#define MDIO_WC_REG_CL73_BAM_CTRL3\t\t\t0x8374\n#define MDIO_WC_REG_CL73_BAM_CODE_FIELD\t\t\t0x837b\n#define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390\n#define MDIO_WC_REG_TX66_CONTROL 0x83b0\n#define MDIO_WC_REG_RX66_CONTROL 0x83c0\n#define MDIO_WC_REG_RX66_SCW0 0x83c2\n#define MDIO_WC_REG_RX66_SCW1 0x83c3\n#define MDIO_WC_REG_RX66_SCW2 0x83c4\n#define MDIO_WC_REG_RX66_SCW3 0x83c5\n#define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6\n#define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7\n#define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8\n#define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9\n#define MDIO_WC_REG_FX100_CTRL1\t\t\t\t0x8400\n#define MDIO_WC_REG_FX100_CTRL3\t\t\t\t0x8402\n#define MDIO_WC_REG_CL82_USERB1_TX_CTRL5\t\t0x8436\n#define MDIO_WC_REG_CL82_USERB1_TX_CTRL6\t\t0x8437\n#define MDIO_WC_REG_CL82_USERB1_TX_CTRL7\t\t0x8438\n#define MDIO_WC_REG_CL82_USERB1_TX_CTRL9\t\t0x8439\n#define MDIO_WC_REG_CL82_USERB1_RX_CTRL10\t\t0x843a\n#define MDIO_WC_REG_CL82_USERB1_RX_CTRL11\t\t0x843b\n#define MDIO_WC_REG_ETA_CL73_OUI1\t\t\t0x8453\n#define MDIO_WC_REG_ETA_CL73_OUI2\t\t\t0x8454\n#define MDIO_WC_REG_ETA_CL73_OUI3\t\t\t0x8455\n#define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE\t\t0x8456\n#define MDIO_WC_REG_ETA_CL73_LD_UD_CODE\t\t\t0x8457\n#define MDIO_WC_REG_MICROBLK_CMD 0xffc2\n#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5\n#define MDIO_WC_REG_MICROBLK_CMD3 0xffcc\n\n#define MDIO_WC_REG_AERBLK_AER 0xffde\n#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL\t\t\t0xffe0\n#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1\n\n#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A\n#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT \t0\n#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT \t4\n\n#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141\n\n#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f\n\n/* 54618se */\n#define MDIO_REG_GPHY_MII_STATUS\t\t\t0x1\n#define MDIO_REG_GPHY_PHYID_LSB\t\t\t\t0x3\n#define MDIO_REG_GPHY_CL45_ADDR_REG\t\t\t0xd\n#define MDIO_REG_GPHY_CL45_REG_WRITE\t\t0x4000\n#define MDIO_REG_GPHY_CL45_REG_READ\t\t0xc000\n#define MDIO_REG_GPHY_CL45_DATA_REG\t\t\t0xe\n#define MDIO_REG_GPHY_EEE_RESOLVED\t\t0x803e\n#define MDIO_REG_GPHY_EXP_ACCESS_GATE\t\t\t0x15\n#define MDIO_REG_GPHY_EXP_ACCESS\t\t\t0x17\n#define MDIO_REG_GPHY_EXP_ACCESS_TOP\t\t0xd00\n#define MDIO_REG_GPHY_EXP_TOP_2K_BUF\t\t0x40\n#define MDIO_REG_GPHY_AUX_STATUS\t\t\t0x19\n#define MDIO_REG_INTR_STATUS\t\t\t\t0x1a\n#define MDIO_REG_INTR_MASK\t\t\t\t0x1b\n#define MDIO_REG_INTR_MASK_LINK_STATUS\t\t\t(0x1 << 1)\n#define MDIO_REG_GPHY_SHADOW\t\t\t\t0x1c\n#define MDIO_REG_GPHY_SHADOW_LED_SEL1\t\t\t(0x0d << 10)\n#define MDIO_REG_GPHY_SHADOW_LED_SEL2\t\t\t(0x0e << 10)\n#define MDIO_REG_GPHY_SHADOW_WR_ENA\t\t\t(0x1 << 15)\n#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED\t\t(0x1e << 10)\n#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD\t\t(0x1 << 8)\n\ntypedef elink_status_t(*read_sfp_module_eeprom_func_p) (struct elink_phy * phy,\n\t\t\t\t\t\t\tstruct elink_params *\n\t\t\t\t\t\t\tparams,\n\t\t\t\t\t\t\tuint8_t dev_addr,\n\t\t\t\t\t\t\tuint16_t addr,\n\t\t\t\t\t\t\tuint8_t byte_cnt,\n\t\t\t\t\t\t\tuint8_t * o_buf,\n\t\t\t\t\t\t\tuint8_t);\n/********************************************************/\n#define ELINK_ETH_HLEN\t\t\t14\n/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */\n#define ELINK_ETH_OVREHEAD\t\t\t(ELINK_ETH_HLEN + 8 + 8)\n#define ELINK_ETH_MIN_PACKET_SIZE\t\t60\n#define ELINK_ETH_MAX_PACKET_SIZE\t\t1500\n#define ELINK_ETH_MAX_JUMBO_PACKET_SIZE\t9600\n#define ELINK_MDIO_ACCESS_TIMEOUT\t\t1000\n#define WC_LANE_MAX\t\t\t4\n#define I2C_SWITCH_WIDTH\t\t2\n#define I2C_BSC0\t\t\t0\n#define I2C_BSC1\t\t\t1\n#define I2C_WA_RETRY_CNT\t\t3\n#define I2C_WA_PWR_ITER\t\t\t(I2C_WA_RETRY_CNT - 1)\n#define MCPR_IMC_COMMAND_READ_OP\t1\n#define MCPR_IMC_COMMAND_WRITE_OP\t2\n\n/* LED Blink rate that will achieve ~15.9Hz */\n#define LED_BLINK_RATE_VAL_E3\t\t354\n#define LED_BLINK_RATE_VAL_E1X_E2\t480\n/***********************************************************/\n/*\t\t\tShortcut definitions\t\t */\n/***********************************************************/\n\n#define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0\n\n#define ELINK_NIG_STATUS_EMAC0_MI_INT \\\n\t\tNIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT\n#define ELINK_NIG_STATUS_XGXS0_LINK10G \\\n\t\tNIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G\n#define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \\\n\t\tNIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS\n#define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \\\n\t\tNIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE\n#define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \\\n\t\tNIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS\n#define ELINK_NIG_MASK_MI_INT \\\n\t\tNIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT\n#define ELINK_NIG_MASK_XGXS0_LINK10G \\\n\t\tNIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G\n#define ELINK_NIG_MASK_XGXS0_LINK_STATUS \\\n\t\tNIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS\n#define ELINK_NIG_MASK_SERDES0_LINK_STATUS \\\n\t\tNIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS\n\n#define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \\\n\t\t(MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \\\n\t\t MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)\n\n#define ELINK_XGXS_RESET_BITS \\\n\t(MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \\\n\t MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \\\n\t MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \\\n\t MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \\\n\t MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)\n\n#define ELINK_SERDES_RESET_BITS \\\n\t(MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \\\n\t MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \\\n\t MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \\\n\t MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)\n\n#define ELINK_AUTONEG_CL37\t\tSHARED_HW_CFG_AN_ENABLE_CL37\n#define ELINK_AUTONEG_CL73\t\tSHARED_HW_CFG_AN_ENABLE_CL73\n#define ELINK_AUTONEG_BAM\t\tSHARED_HW_CFG_AN_ENABLE_BAM\n#define ELINK_AUTONEG_PARALLEL \\\n\t\t\t\tSHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION\n#define ELINK_AUTONEG_SGMII_FIBER_AUTODET \\\n\t\t\t\tSHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT\n#define ELINK_AUTONEG_REMOTE_PHY\tSHARED_HW_CFG_AN_ENABLE_REMOTE_PHY\n\n#define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \\\n\t\t\tMDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE\n#define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \\\n\t\t\tMDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE\n#define ELINK_GP_STATUS_SPEED_MASK \\\n\t\t\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK\n#define ELINK_GP_STATUS_10M\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M\n#define ELINK_GP_STATUS_100M\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M\n#define ELINK_GP_STATUS_1G\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G\n#define ELINK_GP_STATUS_2_5G\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G\n#define ELINK_GP_STATUS_5G\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G\n#define ELINK_GP_STATUS_6G\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G\n#define ELINK_GP_STATUS_10G_HIG \\\n\t\t\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG\n#define ELINK_GP_STATUS_10G_CX4 \\\n\t\t\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4\n#define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX\n#define ELINK_GP_STATUS_10G_KX4 \\\n\t\t\tMDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4\n#define\tELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR\n#define\tELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI\n#define\tELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS\n#define\tELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI\n#define\tELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2\n#define ELINK_LINK_10THD\t\tLINK_STATUS_SPEED_AND_DUPLEX_10THD\n#define ELINK_LINK_10TFD\t\tLINK_STATUS_SPEED_AND_DUPLEX_10TFD\n#define ELINK_LINK_100TXHD\t\tLINK_STATUS_SPEED_AND_DUPLEX_100TXHD\n#define ELINK_LINK_100T4\t\tLINK_STATUS_SPEED_AND_DUPLEX_100T4\n#define ELINK_LINK_100TXFD\t\tLINK_STATUS_SPEED_AND_DUPLEX_100TXFD\n#define ELINK_LINK_1000THD\t\tLINK_STATUS_SPEED_AND_DUPLEX_1000THD\n#define ELINK_LINK_1000TFD\t\tLINK_STATUS_SPEED_AND_DUPLEX_1000TFD\n#define ELINK_LINK_1000XFD\t\tLINK_STATUS_SPEED_AND_DUPLEX_1000XFD\n#define ELINK_LINK_2500THD\t\tLINK_STATUS_SPEED_AND_DUPLEX_2500THD\n#define ELINK_LINK_2500TFD\t\tLINK_STATUS_SPEED_AND_DUPLEX_2500TFD\n#define ELINK_LINK_2500XFD\t\tLINK_STATUS_SPEED_AND_DUPLEX_2500XFD\n#define ELINK_LINK_10GTFD\t\tLINK_STATUS_SPEED_AND_DUPLEX_10GTFD\n#define ELINK_LINK_10GXFD\t\tLINK_STATUS_SPEED_AND_DUPLEX_10GXFD\n#define ELINK_LINK_20GTFD\t\tLINK_STATUS_SPEED_AND_DUPLEX_20GTFD\n#define ELINK_LINK_20GXFD\t\tLINK_STATUS_SPEED_AND_DUPLEX_20GXFD\n\n#define ELINK_LINK_UPDATE_MASK \\\n\t\t\t(LINK_STATUS_SPEED_AND_DUPLEX_MASK | \\\n\t\t\t LINK_STATUS_LINK_UP | \\\n\t\t\t LINK_STATUS_PHYSICAL_LINK_FLAG | \\\n\t\t\t LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \\\n\t\t\t LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \\\n\t\t\t LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \\\n\t\t\t LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \\\n\t\t\t LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \\\n\t\t\t LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)\n\n#define ELINK_SFP_EEPROM_CON_TYPE_ADDR\t\t0x2\n#define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC\t0x7\n#define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER\t0x21\n#define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45\t0x22\n\n#define ELINK_SFP_EEPROM_COMP_CODE_ADDR\t\t0x3\n#define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK\t(1<<4)\n#define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK\t(1<<5)\n#define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK\t(1<<6)\n\n#define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR\t\t0x8\n#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4\n#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8\n\n#define ELINK_SFP_EEPROM_OPTIONS_ADDR\t\t\t0x40\n#define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1\n#define ELINK_SFP_EEPROM_OPTIONS_SIZE\t\t\t2\n\n#define ELINK_EDC_MODE_LINEAR\t\t\t\t0x0022\n#define ELINK_EDC_MODE_LIMITING\t\t\t\t0x0044\n#define ELINK_EDC_MODE_PASSIVE_DAC\t\t\t0x0055\n#define ELINK_EDC_MODE_ACTIVE_DAC\t\t\t0x0066\n\n/* ETS defines*/\n#define DCBX_INVALID_COS\t\t\t\t\t(0xFF)\n\n#define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND\t\t(0x5000)\n#define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT\t\t(0x5000)\n#define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS\t\t(1360)\n#define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS\t\t\t(2720)\n#define ELINK_ETS_E3B0_PBF_MIN_W_VAL\t\t\t\t(10000)\n\n#define ELINK_MAX_PACKET_SIZE\t\t\t\t\t(9700)\n#define MAX_KR_LINK_RETRY\t\t\t\t4\n\n/**********************************************************/\n/* INTERFACE */\n/**********************************************************/\n\n#define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \\\n\telink_cl45_write(_sc, _phy, \\\n\t\t(_phy)->def_md_devad, \\\n\t\t(_bank + (_addr & 0xf)), \\\n\t\t_val)\n\n#define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \\\n\telink_cl45_read(_sc, _phy, \\\n\t\t(_phy)->def_md_devad, \\\n\t\t(_bank + (_addr & 0xf)), \\\n\t\t_val)\n\nstatic uint32_t elink_bits_en(struct bnx2x_softc *sc, uint32_t reg, uint32_t bits)\n{\n\tuint32_t val = REG_RD(sc, reg);\n\n\tval |= bits;\n\tREG_WR(sc, reg, val);\n\treturn val;\n}\n\nstatic uint32_t elink_bits_dis(struct bnx2x_softc *sc, uint32_t reg,\n\t\t\t uint32_t bits)\n{\n\tuint32_t val = REG_RD(sc, reg);\n\n\tval &= ~bits;\n\tREG_WR(sc, reg, val);\n\treturn val;\n}\n\n/*\n * elink_check_lfa - This function checks if link reinitialization is required,\n * or link flap can be avoided.\n *\n * @params:\tlink parameters\n * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed\n * condition code.\n */\nstatic int elink_check_lfa(struct elink_params *params)\n{\n\tuint32_t link_status, cfg_idx, lfa_mask, cfg_size;\n\tuint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;\n\tuint32_t saved_val, req_val, eee_status;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tadditional_config =\n\t REG_RD(sc, params->lfa_base +\n\t\t offsetof(struct shmem_lfa, additional_config));\n\n\t/* NOTE: must be first condition checked -\n\t * to verify DCC bit is cleared in any case!\n\t */\n\tif (additional_config & NO_LFA_DUE_TO_DCC_MASK) {\n\t\tPMD_DRV_LOG(DEBUG, \"No LFA due to DCC flap after clp exit\");\n\t\tREG_WR(sc, params->lfa_base +\n\t\t offsetof(struct shmem_lfa, additional_config),\n\t\t additional_config & ~NO_LFA_DUE_TO_DCC_MASK);\n\t\treturn LFA_DCC_LFA_DISABLED;\n\t}\n\n\t/* Verify that link is up */\n\tlink_status = REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t port_mb[params->port].link_status));\n\tif (!(link_status & LINK_STATUS_LINK_UP))\n\t\treturn LFA_LINK_DOWN;\n\n\t/* if loaded after BOOT from SAN, don't flap the link in any case and\n\t * rely on link set by preboot driver\n\t */\n\tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN)\n\t\treturn 0;\n\n\t/* Verify that loopback mode is not set */\n\tif (params->loopback_mode)\n\t\treturn LFA_LOOPBACK_ENABLED;\n\n\t/* Verify that MFW supports LFA */\n\tif (!params->lfa_base)\n\t\treturn LFA_MFW_IS_TOO_OLD;\n\n\tif (params->num_phys == 3) {\n\t\tcfg_size = 2;\n\t\tlfa_mask = 0xffffffff;\n\t} else {\n\t\tcfg_size = 1;\n\t\tlfa_mask = 0xffff;\n\t}\n\n\t/* Compare Duplex */\n\tsaved_val = REG_RD(sc, params->lfa_base +\n\t\t\t offsetof(struct shmem_lfa, req_duplex));\n\treq_val = params->req_duplex[0] | (params->req_duplex[1] << 16);\n\tif ((saved_val & lfa_mask) != (req_val & lfa_mask)) {\n\t\tPMD_DRV_LOG(INFO, \"Duplex mismatch %x vs. %x\",\n\t\t\t (saved_val & lfa_mask), (req_val & lfa_mask));\n\t\treturn LFA_DUPLEX_MISMATCH;\n\t}\n\t/* Compare Flow Control */\n\tsaved_val = REG_RD(sc, params->lfa_base +\n\t\t\t offsetof(struct shmem_lfa, req_flow_ctrl));\n\treq_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);\n\tif ((saved_val & lfa_mask) != (req_val & lfa_mask)) {\n\t\tPMD_DRV_LOG(DEBUG, \"Flow control mismatch %x vs. %x\",\n\t\t\t (saved_val & lfa_mask), (req_val & lfa_mask));\n\t\treturn LFA_FLOW_CTRL_MISMATCH;\n\t}\n\t/* Compare Link Speed */\n\tsaved_val = REG_RD(sc, params->lfa_base +\n\t\t\t offsetof(struct shmem_lfa, req_line_speed));\n\treq_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);\n\tif ((saved_val & lfa_mask) != (req_val & lfa_mask)) {\n\t\tPMD_DRV_LOG(DEBUG, \"Link speed mismatch %x vs. %x\",\n\t\t\t (saved_val & lfa_mask), (req_val & lfa_mask));\n\t\treturn LFA_LINK_SPEED_MISMATCH;\n\t}\n\n\tfor (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {\n\t\tcur_speed_cap_mask = REG_RD(sc, params->lfa_base +\n\t\t\t\t\t offsetof(struct shmem_lfa,\n\t\t\t\t\t\t speed_cap_mask[cfg_idx]));\n\n\t\tif (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Speed Cap mismatch %x vs. %x\",\n\t\t\t\t cur_speed_cap_mask,\n\t\t\t\t params->speed_cap_mask[cfg_idx]);\n\t\t\treturn LFA_SPEED_CAP_MISMATCH;\n\t\t}\n\t}\n\n\tcur_req_fc_auto_adv =\n\t REG_RD(sc, params->lfa_base +\n\t\t offsetof(struct shmem_lfa, additional_config)) &\n\t REQ_FC_AUTO_ADV_MASK;\n\n\tif ((uint16_t) cur_req_fc_auto_adv != params->req_fc_auto_adv) {\n\t\tPMD_DRV_LOG(DEBUG, \"Flow Ctrl AN mismatch %x vs. %x\",\n\t\t\t cur_req_fc_auto_adv, params->req_fc_auto_adv);\n\t\treturn LFA_FLOW_CTRL_MISMATCH;\n\t}\n\n\teee_status = REG_RD(sc, params->shmem2_base +\n\t\t\t offsetof(struct shmem2_region,\n\t\t\t\t eee_status[params->port]));\n\n\tif (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^\n\t (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||\n\t ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^\n\t (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {\n\t\tPMD_DRV_LOG(DEBUG, \"EEE mismatch %x vs. %x\", params->eee_mode,\n\t\t\t eee_status);\n\t\treturn LFA_EEE_MISMATCH;\n\t}\n\n\t/* LFA conditions are met */\n\treturn 0;\n}\n\n/******************************************************************/\n/*\t\t\tEPIO/GPIO section\t\t\t */\n/******************************************************************/\nstatic void elink_get_epio(struct bnx2x_softc *sc, uint32_t epio_pin,\n\t\t\t uint32_t * en)\n{\n\tuint32_t epio_mask, gp_oenable;\n\t*en = 0;\n\t/* Sanity check */\n\tif (epio_pin > 31) {\n\t\tPMD_DRV_LOG(DEBUG, \"Invalid EPIO pin %d to get\", epio_pin);\n\t\treturn;\n\t}\n\n\tepio_mask = 1 << epio_pin;\n\t/* Set this EPIO to output */\n\tgp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);\n\tREG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);\n\n\t*en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;\n}\n\nstatic void elink_set_epio(struct bnx2x_softc *sc, uint32_t epio_pin, uint32_t en)\n{\n\tuint32_t epio_mask, gp_output, gp_oenable;\n\n\t/* Sanity check */\n\tif (epio_pin > 31) {\n\t\tPMD_DRV_LOG(DEBUG, \"Invalid EPIO pin %d to set\", epio_pin);\n\t\treturn;\n\t}\n\tPMD_DRV_LOG(DEBUG, \"Setting EPIO pin %d to %d\", epio_pin, en);\n\tepio_mask = 1 << epio_pin;\n\t/* Set this EPIO to output */\n\tgp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);\n\tif (en)\n\t\tgp_output |= epio_mask;\n\telse\n\t\tgp_output &= ~epio_mask;\n\n\tREG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);\n\n\t/* Set the value for this EPIO */\n\tgp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);\n\tREG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);\n}\n\nstatic void elink_set_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,\n\t\t\t uint32_t val)\n{\n\tif (pin_cfg == PIN_CFG_NA)\n\t\treturn;\n\tif (pin_cfg >= PIN_CFG_EPIO0) {\n\t\telink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);\n\t} else {\n\t\tuint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;\n\t\tuint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;\n\t\telink_cb_gpio_write(sc, gpio_num, (uint8_t) val, gpio_port);\n\t}\n}\n\nstatic uint32_t elink_get_cfg_pin(struct bnx2x_softc *sc, uint32_t pin_cfg,\n\t\t\t\t uint32_t * val)\n{\n\tif (pin_cfg == PIN_CFG_NA)\n\t\treturn ELINK_STATUS_ERROR;\n\tif (pin_cfg >= PIN_CFG_EPIO0) {\n\t\telink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);\n\t} else {\n\t\tuint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;\n\t\tuint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;\n\t\t*val = elink_cb_gpio_read(sc, gpio_num, gpio_port);\n\t}\n\treturn ELINK_STATUS_OK;\n\n}\n\n/******************************************************************/\n/*\t\t\tPFC section\t\t\t\t */\n/******************************************************************/\nstatic void elink_update_pfc_xmac(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t xmac_base;\n\tuint32_t pause_val, pfc0_val, pfc1_val;\n\n\t/* XMAC base adrr */\n\txmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;\n\n\t/* Initialize pause and pfc registers */\n\tpause_val = 0x18000;\n\tpfc0_val = 0xFFFF8000;\n\tpfc1_val = 0x2;\n\n\t/* No PFC support */\n\tif (!(params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)) {\n\n\t\t/* RX flow control - Process pause frame in receive direction\n\t\t */\n\t\tif (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)\n\t\t\tpause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;\n\n\t\t/* TX flow control - Send pause packet when buffer is full */\n\t\tif (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)\n\t\t\tpause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;\n\t} else {\t\t/* PFC support */\n\t\tpfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |\n\t\t XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |\n\t\t XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |\n\t\t XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |\n\t\t XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;\n\t\t/* Write pause and PFC registers */\n\t\tREG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);\n\t\tREG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);\n\t\tREG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);\n\t\tpfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;\n\n\t}\n\n\t/* Write pause and PFC registers */\n\tREG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);\n\tREG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);\n\tREG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);\n\n\t/* Set MAC address for source TX Pause/PFC frames */\n\tREG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,\n\t ((params->mac_addr[2] << 24) |\n\t\t(params->mac_addr[3] << 16) |\n\t\t(params->mac_addr[4] << 8) | (params->mac_addr[5])));\n\tREG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,\n\t ((params->mac_addr[0] << 8) | (params->mac_addr[1])));\n\n\tDELAY(30);\n}\n\n/******************************************************************/\n/*\t\t\tMAC/PBF section\t\t\t\t */\n/******************************************************************/\nstatic void elink_set_mdio_clk(struct bnx2x_softc *sc, uint32_t emac_base)\n{\n\tuint32_t new_mode, cur_mode;\n\tuint32_t clc_cnt;\n\t/* Set clause 45 mode, slow down the MDIO clock to 2.5MHz\n\t * (a value of 49==0x31) and make sure that the AUTO poll is off\n\t */\n\tcur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);\n\n\tif (USES_WARPCORE(sc))\n\t\tclc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;\n\telse\n\t\tclc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;\n\n\tif (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&\n\t (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))\n\t\treturn;\n\n\tnew_mode = cur_mode &\n\t ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);\n\tnew_mode |= clc_cnt;\n\tnew_mode |= (EMAC_MDIO_MODE_CLAUSE_45);\n\n\tPMD_DRV_LOG(DEBUG, \"Changing emac_mode from 0x%x to 0x%x\",\n\t\t cur_mode, new_mode);\n\tREG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);\n\tDELAY(40);\n}\n\nstatic void elink_set_mdio_emac_per_phy(struct bnx2x_softc *sc,\n\t\t\t\t\tstruct elink_params *params)\n{\n\tuint8_t phy_index;\n\t/* Set mdio clock per phy */\n\tfor (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;\n\t phy_index++)\n\t\telink_set_mdio_clk(sc, params->phy[phy_index].mdio_ctrl);\n}\n\nstatic uint8_t elink_is_4_port_mode(struct bnx2x_softc *sc)\n{\n\tuint32_t port4mode_ovwr_val;\n\t/* Check 4-port override enabled */\n\tport4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);\n\tif (port4mode_ovwr_val & (1 << 0)) {\n\t\t/* Return 4-port mode override value */\n\t\treturn ((port4mode_ovwr_val & (1 << 1)) == (1 << 1));\n\t}\n\t/* Return 4-port mode from input pin */\n\treturn (uint8_t) REG_RD(sc, MISC_REG_PORT4MODE_EN);\n}\n\nstatic void elink_emac_init(struct elink_params *params)\n{\n\t/* reset and unreset the emac core */\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port = params->port;\n\tuint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;\n\tuint32_t val;\n\tuint16_t timeout;\n\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,\n\t (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));\n\tDELAY(5);\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,\n\t (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));\n\n\t/* init emac - use read-modify-write */\n\t/* self clear reset */\n\tval = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);\n\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE,\n\t\t\t (val | EMAC_MODE_RESET));\n\n\ttimeout = 200;\n\tdo {\n\t\tval = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);\n\t\tPMD_DRV_LOG(DEBUG, \"EMAC reset reg is %u\", val);\n\t\tif (!timeout) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"EMAC timeout!\");\n\t\t\treturn;\n\t\t}\n\t\ttimeout--;\n\t} while (val & EMAC_MODE_RESET);\n\n\telink_set_mdio_emac_per_phy(sc, params);\n\t/* Set mac address */\n\tval = ((params->mac_addr[0] << 8) | params->mac_addr[1]);\n\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);\n\n\tval = ((params->mac_addr[2] << 24) |\n\t (params->mac_addr[3] << 16) |\n\t (params->mac_addr[4] << 8) | params->mac_addr[5]);\n\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);\n}\n\nstatic void elink_set_xumac_nig(struct elink_params *params,\n\t\t\t\tuint16_t tx_pause_en, uint8_t enable)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tREG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,\n\t enable);\n\tREG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,\n\t enable);\n\tREG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :\n\t NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);\n}\n\nstatic void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)\n{\n\tuint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;\n\tuint32_t val;\n\tstruct bnx2x_softc *sc = params->sc;\n\tif (!(REG_RD(sc, MISC_REG_RESET_REG_2) &\n\t (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))\n\t\treturn;\n\tval = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);\n\tif (en)\n\t\tval |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |\n\t\t\tUMAC_COMMAND_CONFIG_REG_RX_ENA);\n\telse\n\t\tval &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |\n\t\t\t UMAC_COMMAND_CONFIG_REG_RX_ENA);\n\t/* Disable RX and TX */\n\tREG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);\n}\n\nstatic void elink_umac_enable(struct elink_params *params,\n\t\t\t struct elink_vars *vars, uint8_t lb)\n{\n\tuint32_t val;\n\tuint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;\n\tstruct bnx2x_softc *sc = params->sc;\n\t/* Reset UMAC */\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,\n\t (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));\n\tDELAY(1000 * 1);\n\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,\n\t (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));\n\n\tPMD_DRV_LOG(DEBUG, \"enabling UMAC\");\n\n\t/* This register opens the gate for the UMAC despite its name */\n\tREG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);\n\n\tval = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |\n\t UMAC_COMMAND_CONFIG_REG_PAD_EN |\n\t UMAC_COMMAND_CONFIG_REG_SW_RESET |\n\t UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;\n\tswitch (vars->line_speed) {\n\tcase ELINK_SPEED_10:\n\t\tval |= (0 << 2);\n\t\tbreak;\n\tcase ELINK_SPEED_100:\n\t\tval |= (1 << 2);\n\t\tbreak;\n\tcase ELINK_SPEED_1000:\n\t\tval |= (2 << 2);\n\t\tbreak;\n\tcase ELINK_SPEED_2500:\n\t\tval |= (3 << 2);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(DEBUG, \"Invalid speed for UMAC %d\",\n\t\t\t vars->line_speed);\n\t\tbreak;\n\t}\n\tif (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))\n\t\tval |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;\n\n\tif (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))\n\t\tval |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;\n\n\tif (vars->duplex == DUPLEX_HALF)\n\t\tval |= UMAC_COMMAND_CONFIG_REG_HD_ENA;\n\n\tREG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);\n\tDELAY(50);\n\n\t/* Configure UMAC for EEE */\n\tif (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {\n\t\tPMD_DRV_LOG(DEBUG, \"configured UMAC for EEE\");\n\t\tREG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,\n\t\t UMAC_UMAC_EEE_CTRL_REG_EEE_EN);\n\t\tREG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);\n\t} else {\n\t\tREG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);\n\t}\n\n\t/* Set MAC address for source TX Pause/PFC frames (under SW reset) */\n\tREG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,\n\t ((params->mac_addr[2] << 24) |\n\t\t(params->mac_addr[3] << 16) |\n\t\t(params->mac_addr[4] << 8) | (params->mac_addr[5])));\n\tREG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,\n\t ((params->mac_addr[0] << 8) | (params->mac_addr[1])));\n\n\t/* Enable RX and TX */\n\tval &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;\n\tval |= UMAC_COMMAND_CONFIG_REG_TX_ENA | UMAC_COMMAND_CONFIG_REG_RX_ENA;\n\tREG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);\n\tDELAY(50);\n\n\t/* Remove SW Reset */\n\tval &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;\n\n\t/* Check loopback mode */\n\tif (lb)\n\t\tval |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;\n\tREG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);\n\n\t/* Maximum Frame Length (RW). Defines a 14-Bit maximum frame\n\t * length used by the MAC receive logic to check frames.\n\t */\n\tREG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);\n\telink_set_xumac_nig(params,\n\t\t\t ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);\n\tvars->mac_type = ELINK_MAC_TYPE_UMAC;\n\n}\n\n/* Define the XMAC mode */\nstatic void elink_xmac_init(struct elink_params *params, uint32_t max_speed)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t is_port4mode = elink_is_4_port_mode(sc);\n\n\t/* In 4-port mode, need to set the mode only once, so if XMAC is\n\t * already out of reset, it means the mode has already been set,\n\t * and it must not* reset the XMAC again, since it controls both\n\t * ports of the path\n\t */\n\n\tif (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) ||\n\t (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) ||\n\t (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) &&\n\t is_port4mode &&\n\t (REG_RD(sc, MISC_REG_RESET_REG_2) &\n\t MISC_REGISTERS_RESET_REG_2_XMAC)) {\n\t\tPMD_DRV_LOG(DEBUG, \"XMAC already out of reset in 4-port mode\");\n\t\treturn;\n\t}\n\n\t/* Hard reset */\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,\n\t MISC_REGISTERS_RESET_REG_2_XMAC);\n\tDELAY(1000 * 1);\n\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,\n\t MISC_REGISTERS_RESET_REG_2_XMAC);\n\tif (is_port4mode) {\n\t\tPMD_DRV_LOG(DEBUG, \"Init XMAC to 2 ports x 10G per path\");\n\n\t\t/* Set the number of ports on the system side to up to 2 */\n\t\tREG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);\n\n\t\t/* Set the number of ports on the Warp Core to 10G */\n\t\tREG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);\n\t} else {\n\t\t/* Set the number of ports on the system side to 1 */\n\t\tREG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);\n\t\tif (max_speed == ELINK_SPEED_10000) {\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"Init XMAC to 10G x 1 port per path\");\n\t\t\t/* Set the number of ports on the Warp Core to 10G */\n\t\t\tREG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);\n\t\t} else {\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"Init XMAC to 20G x 2 ports per path\");\n\t\t\t/* Set the number of ports on the Warp Core to 20G */\n\t\t\tREG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);\n\t\t}\n\t}\n\t/* Soft reset */\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,\n\t MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);\n\tDELAY(1000 * 1);\n\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,\n\t MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);\n\n}\n\nstatic void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)\n{\n\tuint8_t port = params->port;\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;\n\tuint32_t val;\n\n\tif (REG_RD(sc, MISC_REG_RESET_REG_2) & MISC_REGISTERS_RESET_REG_2_XMAC) {\n\t\t/* Send an indication to change the state in the NIG back to XON\n\t\t * Clearing this bit enables the next set of this bit to get\n\t\t * rising edge\n\t\t */\n\t\tpfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);\n\t\tREG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,\n\t\t (pfc_ctrl & ~(1 << 1)));\n\t\tREG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,\n\t\t (pfc_ctrl | (1 << 1)));\n\t\tPMD_DRV_LOG(DEBUG, \"Disable XMAC on port %x\", port);\n\t\tval = REG_RD(sc, xmac_base + XMAC_REG_CTRL);\n\t\tif (en)\n\t\t\tval |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);\n\t\telse\n\t\t\tval &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);\n\t\tREG_WR(sc, xmac_base + XMAC_REG_CTRL, val);\n\t}\n}\n\nstatic elink_status_t elink_xmac_enable(struct elink_params *params,\n\t\t\t\t\tstruct elink_vars *vars, uint8_t lb)\n{\n\tuint32_t val, xmac_base;\n\tstruct bnx2x_softc *sc = params->sc;\n\tPMD_DRV_LOG(DEBUG, \"enabling XMAC\");\n\n\txmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;\n\n\telink_xmac_init(params, vars->line_speed);\n\n\t/* This register determines on which events the MAC will assert\n\t * error on the i/f to the NIG along w/ EOP.\n\t */\n\n\t/* This register tells the NIG whether to send traffic to UMAC\n\t * or XMAC\n\t */\n\tREG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 0);\n\n\t/* When XMAC is in XLGMII mode, disable sending idles for fault\n\t * detection.\n\t */\n\tif (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {\n\t\tREG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL,\n\t\t (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |\n\t\t\tXMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));\n\t\tREG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);\n\t\tREG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,\n\t\t XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |\n\t\t XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);\n\t}\n\t/* Set Max packet size */\n\tREG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);\n\n\t/* CRC append for Tx packets */\n\tREG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);\n\n\t/* update PFC */\n\telink_update_pfc_xmac(params, vars);\n\n\tif (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {\n\t\tPMD_DRV_LOG(DEBUG, \"Setting XMAC for EEE\");\n\t\tREG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);\n\t\tREG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);\n\t} else {\n\t\tREG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);\n\t}\n\n\t/* Enable TX and RX */\n\tval = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;\n\n\t/* Set MAC in XLGMII mode for dual-mode */\n\tif ((vars->line_speed == ELINK_SPEED_20000) &&\n\t (params->phy[ELINK_INT_PHY].supported &\n\t ELINK_SUPPORTED_20000baseKR2_Full))\n\t\tval |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;\n\n\t/* Check loopback mode */\n\tif (lb)\n\t\tval |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;\n\tREG_WR(sc, xmac_base + XMAC_REG_CTRL, val);\n\telink_set_xumac_nig(params,\n\t\t\t ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);\n\n\tvars->mac_type = ELINK_MAC_TYPE_XMAC;\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_emac_enable(struct elink_params *params,\n\t\t\t\t\tstruct elink_vars *vars, uint8_t lb)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port = params->port;\n\tuint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;\n\tuint32_t val;\n\n\tPMD_DRV_LOG(DEBUG, \"enabling EMAC\");\n\n\t/* Disable BMAC */\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,\n\t (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));\n\n\t/* enable emac and not bmac */\n\tREG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 1);\n\n#ifdef ELINK_INCLUDE_EMUL\n\t/* for paladium */\n\tif (CHIP_REV_IS_EMUL(sc)) {\n\t\t/* Use lane 1 (of lanes 0-3) */\n\t\tREG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1);\n\t\tREG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);\n\t}\n\t/* for fpga */\n\telse\n#endif\n#ifdef ELINK_INCLUDE_FPGA\n\tif (CHIP_REV_IS_FPGA(sc)) {\n\t\t/* Use lane 1 (of lanes 0-3) */\n\t\tPMD_DRV_LOG(DEBUG, \"elink_emac_enable: Setting FPGA\");\n\n\t\tREG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 1);\n\t\tREG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);\n\t} else\n#endif\n\t\t/* ASIC */\n\tif (vars->phy_flags & PHY_XGXS_FLAG) {\n\t\tuint32_t ser_lane = ((params->lane_config &\n\t\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>\n\t\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);\n\n\t\tPMD_DRV_LOG(DEBUG, \"XGXS\");\n\t\t/* select the master lanes (out of 0-3) */\n\t\tREG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, ser_lane);\n\t\t/* select XGXS */\n\t\tREG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);\n\n\t} else {\t\t/* SerDes */\n\t\tPMD_DRV_LOG(DEBUG, \"SerDes\");\n\t\t/* select SerDes */\n\t\tREG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0);\n\t}\n\n\telink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE,\n\t\t EMAC_RX_MODE_RESET);\n\telink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,\n\t\t EMAC_TX_MODE_RESET);\n\n#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)\n\tif (CHIP_REV_IS_SLOW(sc)) {\n\t\t/* config GMII mode */\n\t\tval = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);\n\t\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE,\n\t\t\t\t (val | EMAC_MODE_PORT_GMII));\n\t} else {\t\t/* ASIC */\n#endif\n\t\t/* pause enable/disable */\n\t\telink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,\n\t\t\t EMAC_RX_MODE_FLOW_EN);\n\n\t\telink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,\n\t\t\t (EMAC_TX_MODE_EXT_PAUSE_EN |\n\t\t\t\tEMAC_TX_MODE_FLOW_EN));\n\t\tif (!(params->feature_config_flags &\n\t\t ELINK_FEATURE_CONFIG_PFC_ENABLED)) {\n\t\t\tif (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)\n\t\t\t\telink_bits_en(sc, emac_base +\n\t\t\t\t\t EMAC_REG_EMAC_RX_MODE,\n\t\t\t\t\t EMAC_RX_MODE_FLOW_EN);\n\n\t\t\tif (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)\n\t\t\t\telink_bits_en(sc, emac_base +\n\t\t\t\t\t EMAC_REG_EMAC_TX_MODE,\n\t\t\t\t\t (EMAC_TX_MODE_EXT_PAUSE_EN |\n\t\t\t\t\t EMAC_TX_MODE_FLOW_EN));\n\t\t} else\n\t\t\telink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,\n\t\t\t\t EMAC_TX_MODE_FLOW_EN);\n#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)\n\t}\n#endif\n\n\t/* KEEP_VLAN_TAG, promiscuous */\n\tval = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);\n\tval |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;\n\n\t/* Setting this bit causes MAC control frames (except for pause\n\t * frames) to be passed on for processing. This setting has no\n\t * affect on the operation of the pause frames. This bit effects\n\t * all packets regardless of RX Parser packet sorting logic.\n\t * Turn the PFC off to make sure we are in Xon state before\n\t * enabling it.\n\t */\n\telink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);\n\tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {\n\t\tPMD_DRV_LOG(DEBUG, \"PFC is enabled\");\n\t\t/* Enable PFC again */\n\t\telink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,\n\t\t\t\t EMAC_REG_RX_PFC_MODE_RX_EN |\n\t\t\t\t EMAC_REG_RX_PFC_MODE_TX_EN |\n\t\t\t\t EMAC_REG_RX_PFC_MODE_PRIORITIES);\n\n\t\telink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,\n\t\t\t\t ((0x0101 <<\n\t\t\t\t EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |\n\t\t\t\t (0x00ff <<\n\t\t\t\t EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));\n\t\tval |= EMAC_RX_MODE_KEEP_MAC_CONTROL;\n\t}\n\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);\n\n\t/* Set Loopback */\n\tval = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);\n\tif (lb)\n\t\tval |= 0x810;\n\telse\n\t\tval &= ~0x810;\n\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val);\n\n\t/* Enable emac */\n\tREG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 1);\n\n\t/* Enable emac for jumbo packets */\n\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,\n\t\t\t (EMAC_RX_MTU_SIZE_JUMBO_ENA |\n\t\t\t (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +\n\t\t\t ELINK_ETH_OVREHEAD)));\n\n\t/* Strip CRC */\n\tREG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port * 4, 0x1);\n\n\t/* Disable the NIG in/out to the bmac */\n\tREG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x0);\n\tREG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, 0x0);\n\tREG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x0);\n\n\t/* Enable the NIG in/out to the emac */\n\tREG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x1);\n\tval = 0;\n\tif ((params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_PFC_ENABLED) ||\n\t (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))\n\t\tval = 1;\n\n\tREG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, val);\n\tREG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x1);\n\n#ifdef ELINK_INCLUDE_EMUL\n\tif (CHIP_REV_IS_EMUL(sc)) {\n\t\t/* Take the BigMac out of reset */\n\t\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,\n\t\t (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));\n\n\t\t/* Enable access for bmac registers */\n\t\tREG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);\n\t} else\n#endif\n\t\tREG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x0);\n\n\tvars->mac_type = ELINK_MAC_TYPE_EMAC;\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_update_pfc_bmac1(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tuint32_t wb_data[2];\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :\n\t NIG_REG_INGRESS_BMAC0_MEM;\n\n\tuint32_t val = 0x14;\n\tif ((!(params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&\n\t (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))\n\t\t/* Enable BigMAC to react on received Pause packets */\n\t\tval |= (1 << 5);\n\twb_data[0] = val;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);\n\n\t/* TX control */\n\tval = 0xc0;\n\tif (!(params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_PFC_ENABLED) &&\n\t (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))\n\t\tval |= 0x800000;\n\twb_data[0] = val;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);\n}\n\nstatic void elink_update_pfc_bmac2(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars, uint8_t is_lb)\n{\n\t/* Set rx control: Strip CRC and enable BigMAC to relay\n\t * control packets to the system as well\n\t */\n\tuint32_t wb_data[2];\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :\n\t NIG_REG_INGRESS_BMAC0_MEM;\n\tuint32_t val = 0x14;\n\n\tif ((!(params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&\n\t (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))\n\t\t/* Enable BigMAC to react on received Pause packets */\n\t\tval |= (1 << 5);\n\twb_data[0] = val;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);\n\tDELAY(30);\n\n\t/* Tx control */\n\tval = 0xc0;\n\tif (!(params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_PFC_ENABLED) &&\n\t (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))\n\t\tval |= 0x800000;\n\twb_data[0] = val;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);\n\n\tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {\n\t\tPMD_DRV_LOG(DEBUG, \"PFC is enabled\");\n\t\t/* Enable PFC RX & TX & STATS and set 8 COS */\n\t\twb_data[0] = 0x0;\n\t\twb_data[0] |= (1 << 0);\t/* RX */\n\t\twb_data[0] |= (1 << 1);\t/* TX */\n\t\twb_data[0] |= (1 << 2);\t/* Force initial Xon */\n\t\twb_data[0] |= (1 << 3);\t/* 8 cos */\n\t\twb_data[0] |= (1 << 5);\t/* STATS */\n\t\twb_data[1] = 0;\n\t\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,\n\t\t\t wb_data, 2);\n\t\t/* Clear the force Xon */\n\t\twb_data[0] &= ~(1 << 2);\n\t} else {\n\t\tPMD_DRV_LOG(DEBUG, \"PFC is disabled\");\n\t\t/* Disable PFC RX & TX & STATS and set 8 COS */\n\t\twb_data[0] = 0x8;\n\t\twb_data[1] = 0;\n\t}\n\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);\n\n\t/* Set Time (based unit is 512 bit time) between automatic\n\t * re-sending of PP packets amd enable automatic re-send of\n\t * Per-Priroity Packet as long as pp_gen is asserted and\n\t * pp_disable is low.\n\t */\n\tval = 0x8000;\n\tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)\n\t\tval |= (1 << 16);\t/* enable automatic re-send */\n\n\twb_data[0] = val;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,\n\t\t wb_data, 2);\n\n\t/* mac control */\n\tval = 0x3;\t\t/* Enable RX and TX */\n\tif (is_lb) {\n\t\tval |= 0x4;\t/* Local loopback */\n\t\tPMD_DRV_LOG(DEBUG, \"enable bmac loopback\");\n\t}\n\t/* When PFC enabled, Pass pause frames towards the NIG. */\n\tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)\n\t\tval |= ((1 << 6) | (1 << 5));\n\n\twb_data[0] = val;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);\n}\n\n/******************************************************************************\n* Description:\n* This function is needed because NIG ARB_CREDIT_WEIGHT_X are\n* not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.\n******************************************************************************/\nstatic elink_status_t elink_pfc_nig_rx_priority_mask(struct bnx2x_softc *sc,\n\t\t\t\t\t\t uint8_t cos_entry,\n\t\t\t\t\t\t uint32_t priority_mask,\n\t\t\t\t\t\t uint8_t port)\n{\n\tuint32_t nig_reg_rx_priority_mask_add = 0;\n\n\tswitch (cos_entry) {\n\tcase 0:\n\t\tnig_reg_rx_priority_mask_add = (port) ?\n\t\t NIG_REG_P1_RX_COS0_PRIORITY_MASK :\n\t\t NIG_REG_P0_RX_COS0_PRIORITY_MASK;\n\t\tbreak;\n\tcase 1:\n\t\tnig_reg_rx_priority_mask_add = (port) ?\n\t\t NIG_REG_P1_RX_COS1_PRIORITY_MASK :\n\t\t NIG_REG_P0_RX_COS1_PRIORITY_MASK;\n\t\tbreak;\n\tcase 2:\n\t\tnig_reg_rx_priority_mask_add = (port) ?\n\t\t NIG_REG_P1_RX_COS2_PRIORITY_MASK :\n\t\t NIG_REG_P0_RX_COS2_PRIORITY_MASK;\n\t\tbreak;\n\tcase 3:\n\t\tif (port)\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\tnig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;\n\t\tbreak;\n\tcase 4:\n\t\tif (port)\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\tnig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;\n\t\tbreak;\n\tcase 5:\n\t\tif (port)\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\tnig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;\n\t\tbreak;\n\t}\n\n\tREG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask);\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_update_mng(struct elink_params *params, uint32_t link_status)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tREG_WR(sc, params->shmem_base +\n\t offsetof(struct shmem_region,\n\t\t\tport_mb[params->port].link_status), link_status);\n}\n\nstatic void elink_update_link_attr(struct elink_params *params,\n\t\t\t\t uint32_t link_attr)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tif (SHMEM2_HAS(sc, link_attr_sync))\n\t\tREG_WR(sc, params->shmem2_base +\n\t\t offsetof(struct shmem2_region,\n\t\t\t\tlink_attr_sync[params->port]), link_attr);\n}\n\nstatic void elink_update_pfc_nig(struct elink_params *params,\n\t\t\t\t struct elink_nig_brb_pfc_port_params\n\t\t\t\t *nig_params)\n{\n\tuint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en =\n\t 0;\n\tuint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;\n\tuint32_t pkt_priority_to_cos = 0;\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port = params->port;\n\n\tint set_pfc = params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_PFC_ENABLED;\n\tPMD_DRV_LOG(DEBUG, \"updating pfc nig parameters\");\n\n\t/* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set\n\t * MAC control frames (that are not pause packets)\n\t * will be forwarded to the XCM.\n\t */\n\txcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :\n\t\t\t NIG_REG_LLH0_XCM_MASK);\n\t/* NIG params will override non PFC params, since it's possible to\n\t * do transition from PFC to SAFC\n\t */\n\tif (set_pfc) {\n\t\tpause_enable = 0;\n\t\tllfc_out_en = 0;\n\t\tllfc_enable = 0;\n\t\tif (CHIP_IS_E3(sc))\n\t\t\tppp_enable = 0;\n\t\telse\n\t\t\tppp_enable = 1;\n\t\txcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :\n\t\t\t NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);\n\t\txcm_out_en = 0;\n\t\thwpfc_enable = 1;\n\t} else {\n\t\tif (nig_params) {\n\t\t\tllfc_out_en = nig_params->llfc_out_en;\n\t\t\tllfc_enable = nig_params->llfc_enable;\n\t\t\tpause_enable = nig_params->pause_enable;\n\t\t} else\t\t/* Default non PFC mode - PAUSE */\n\t\t\tpause_enable = 1;\n\n\t\txcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :\n\t\t\t NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);\n\t\txcm_out_en = 1;\n\t}\n\n\tif (CHIP_IS_E3(sc))\n\t\tREG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :\n\t\t NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);\n\tREG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :\n\t NIG_REG_LLFC_OUT_EN_0, llfc_out_en);\n\tREG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :\n\t NIG_REG_LLFC_ENABLE_0, llfc_enable);\n\tREG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :\n\t NIG_REG_PAUSE_ENABLE_0, pause_enable);\n\n\tREG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :\n\t NIG_REG_PPP_ENABLE_0, ppp_enable);\n\n\tREG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :\n\t NIG_REG_LLH0_XCM_MASK, xcm_mask);\n\n\tREG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :\n\t NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);\n\n\t/* Output enable for RX_XCM # IF */\n\tREG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :\n\t NIG_REG_XCM0_OUT_EN, xcm_out_en);\n\n\t/* HW PFC TX enable */\n\tREG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :\n\t NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);\n\n\tif (nig_params) {\n\t\tuint8_t i = 0;\n\t\tpkt_priority_to_cos = nig_params->pkt_priority_to_cos;\n\n\t\tfor (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)\n\t\t\telink_pfc_nig_rx_priority_mask(sc, i,\n\t\t\t\t\t\t nig_params->\n\t\t\t\t\t\t rx_cos_priority_mask[i],\n\t\t\t\t\t\t port);\n\n\t\tREG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :\n\t\t NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,\n\t\t nig_params->llfc_high_priority_classes);\n\n\t\tREG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :\n\t\t NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,\n\t\t nig_params->llfc_low_priority_classes);\n\t}\n\tREG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :\n\t NIG_REG_P0_PKT_PRIORITY_TO_COS, pkt_priority_to_cos);\n}\n\nelink_status_t elink_update_pfc(struct elink_params *params,\n\t\t\t\tstruct elink_vars *vars,\n\t\t\t\tstruct elink_nig_brb_pfc_port_params\n\t\t\t\t*pfc_params)\n{\n\t/* The PFC and pause are orthogonal to one another, meaning when\n\t * PFC is enabled, the pause are disabled, and when PFC is\n\t * disabled, pause are set according to the pause result.\n\t */\n\tuint32_t val;\n\tstruct bnx2x_softc *sc = params->sc;\n\telink_status_t elink_status = ELINK_STATUS_OK;\n\tuint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);\n\n\tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)\n\t\tvars->link_status |= LINK_STATUS_PFC_ENABLED;\n\telse\n\t\tvars->link_status &= ~LINK_STATUS_PFC_ENABLED;\n\n\telink_update_mng(params, vars->link_status);\n\n\t/* Update NIG params */\n\telink_update_pfc_nig(params, pfc_params);\n\n\tif (!vars->link_up)\n\t\treturn elink_status;\n\n\tPMD_DRV_LOG(DEBUG, \"About to update PFC in BMAC\");\n\n\tif (CHIP_IS_E3(sc)) {\n\t\tif (vars->mac_type == ELINK_MAC_TYPE_XMAC)\n\t\t\telink_update_pfc_xmac(params, vars);\n\t} else {\n\t\tval = REG_RD(sc, MISC_REG_RESET_REG_2);\n\t\tif ((val &\n\t\t (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))\n\t\t == 0) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"About to update PFC in EMAC\");\n\t\t\telink_emac_enable(params, vars, 0);\n\t\t\treturn elink_status;\n\t\t}\n\t\tif (CHIP_IS_E2(sc))\n\t\t\telink_update_pfc_bmac2(params, vars, bmac_loopback);\n\t\telse\n\t\t\telink_update_pfc_bmac1(params, vars);\n\n\t\tval = 0;\n\t\tif ((params->feature_config_flags &\n\t\t ELINK_FEATURE_CONFIG_PFC_ENABLED) ||\n\t\t (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))\n\t\t\tval = 1;\n\t\tREG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port * 4, val);\n\t}\n\treturn elink_status;\n}\n\nstatic elink_status_t elink_bmac1_enable(struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars, uint8_t is_lb)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port = params->port;\n\tuint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :\n\t NIG_REG_INGRESS_BMAC0_MEM;\n\tuint32_t wb_data[2];\n\tuint32_t val;\n\n\tPMD_DRV_LOG(DEBUG, \"Enabling BigMAC1\");\n\n\t/* XGXS control */\n\twb_data[0] = 0x3c;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,\n\t\t wb_data, 2);\n\n\t/* TX MAC SA */\n\twb_data[0] = ((params->mac_addr[2] << 24) |\n\t\t (params->mac_addr[3] << 16) |\n\t\t (params->mac_addr[4] << 8) | params->mac_addr[5]);\n\twb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);\n\n\t/* MAC control */\n\tval = 0x3;\n\tif (is_lb) {\n\t\tval |= 0x4;\n\t\tPMD_DRV_LOG(DEBUG, \"enable bmac loopback\");\n\t}\n\twb_data[0] = val;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);\n\n\t/* Set rx mtu */\n\twb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);\n\n\telink_update_pfc_bmac1(params, vars);\n\n\t/* Set tx mtu */\n\twb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);\n\n\t/* Set cnt max size */\n\twb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);\n\n\t/* Configure SAFC */\n\twb_data[0] = 0x1000200;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,\n\t\t wb_data, 2);\n#ifdef ELINK_INCLUDE_EMUL\n\t/* Fix for emulation */\n\tif (CHIP_REV_IS_EMUL(sc)) {\n\t\twb_data[0] = 0xf000;\n\t\twb_data[1] = 0;\n\t\tREG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,\n\t\t\t wb_data, 2);\n\t}\n#endif\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_bmac2_enable(struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars, uint8_t is_lb)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port = params->port;\n\tuint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :\n\t NIG_REG_INGRESS_BMAC0_MEM;\n\tuint32_t wb_data[2];\n\n\tPMD_DRV_LOG(DEBUG, \"Enabling BigMAC2\");\n\n\twb_data[0] = 0;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);\n\tDELAY(30);\n\n\t/* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */\n\twb_data[0] = 0x3c;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,\n\t\t wb_data, 2);\n\n\tDELAY(30);\n\n\t/* TX MAC SA */\n\twb_data[0] = ((params->mac_addr[2] << 24) |\n\t\t (params->mac_addr[3] << 16) |\n\t\t (params->mac_addr[4] << 8) | params->mac_addr[5]);\n\twb_data[1] = ((params->mac_addr[0] << 8) | params->mac_addr[1]);\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,\n\t\t wb_data, 2);\n\n\tDELAY(30);\n\n\t/* Configure SAFC */\n\twb_data[0] = 0x1000200;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,\n\t\t wb_data, 2);\n\tDELAY(30);\n\n\t/* Set RX MTU */\n\twb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);\n\tDELAY(30);\n\n\t/* Set TX MTU */\n\twb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);\n\tDELAY(30);\n\t/* Set cnt max size */\n\twb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;\n\twb_data[1] = 0;\n\tREG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);\n\tDELAY(30);\n\telink_update_pfc_bmac2(params, vars, is_lb);\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_bmac_enable(struct elink_params *params,\n\t\t\t\t\tstruct elink_vars *vars,\n\t\t\t\t\tuint8_t is_lb, uint8_t reset_bmac)\n{\n\telink_status_t rc = ELINK_STATUS_OK;\n\tuint8_t port = params->port;\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t val;\n\t/* Reset and unreset the BigMac */\n\tif (reset_bmac) {\n\t\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,\n\t\t (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));\n\t\tDELAY(1000 * 1);\n\t}\n\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,\n\t (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));\n\n\t/* Enable access for bmac registers */\n\tREG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4, 0x1);\n\n\t/* Enable BMAC according to BMAC type */\n\tif (CHIP_IS_E2(sc))\n\t\trc = elink_bmac2_enable(params, vars, is_lb);\n\telse\n\t\trc = elink_bmac1_enable(params, vars, is_lb);\n\tREG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 0x1);\n\tREG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port * 4, 0x0);\n\tREG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port * 4, 0x0);\n\tval = 0;\n\tif ((params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_PFC_ENABLED) ||\n\t (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))\n\t\tval = 1;\n\tREG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port * 4, val);\n\tREG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0x0);\n\tREG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0x0);\n\tREG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port * 4, 0x0);\n\tREG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0x1);\n\tREG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0x1);\n\n\tvars->mac_type = ELINK_MAC_TYPE_BMAC;\n\treturn rc;\n}\n\nstatic void elink_set_bmac_rx(struct bnx2x_softc *sc, uint8_t port, uint8_t en)\n{\n\tuint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :\n\t NIG_REG_INGRESS_BMAC0_MEM;\n\tuint32_t wb_data[2];\n\tuint32_t nig_bmac_enable =\n\t REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);\n\n\tif (CHIP_IS_E2(sc))\n\t\tbmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;\n\telse\n\t\tbmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;\n\t/* Only if the bmac is out of reset */\n\tif (REG_RD(sc, MISC_REG_RESET_REG_2) &\n\t (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && nig_bmac_enable) {\n\t\t/* Clear Rx Enable bit in BMAC_CONTROL register */\n\t\tREG_RD_DMAE(sc, bmac_addr, wb_data, 2);\n\t\tif (en)\n\t\t\twb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;\n\t\telse\n\t\t\twb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;\n\t\tREG_WR_DMAE(sc, bmac_addr, wb_data, 2);\n\t\tDELAY(1000 * 1);\n\t}\n}\n\nstatic elink_status_t elink_pbf_update(struct elink_params *params,\n\t\t\t\t uint32_t flow_ctrl, uint32_t line_speed)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port = params->port;\n\tuint32_t init_crd, crd;\n\tuint32_t count = 1000;\n\n\t/* Disable port */\n\tREG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x1);\n\n\t/* Wait for init credit */\n\tinit_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port * 4);\n\tcrd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);\n\tPMD_DRV_LOG(DEBUG, \"init_crd 0x%x crd 0x%x\", init_crd, crd);\n\n\twhile ((init_crd != crd) && count) {\n\t\tDELAY(1000 * 5);\n\t\tcrd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);\n\t\tcount--;\n\t}\n\tcrd = REG_RD(sc, PBF_REG_P0_CREDIT + port * 8);\n\tif (init_crd != crd) {\n\t\tPMD_DRV_LOG(DEBUG, \"BUG! init_crd 0x%x != crd 0x%x\",\n\t\t\t init_crd, crd);\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\n\tif (flow_ctrl & ELINK_FLOW_CTRL_RX ||\n\t line_speed == ELINK_SPEED_10 ||\n\t line_speed == ELINK_SPEED_100 ||\n\t line_speed == ELINK_SPEED_1000 || line_speed == ELINK_SPEED_2500) {\n\t\tREG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 1);\n\t\t/* Update threshold */\n\t\tREG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, 0);\n\t\t/* Update init credit */\n\t\tinit_crd = 778;\t/* (800-18-4) */\n\n\t} else {\n\t\tuint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +\n\t\t\t\t ELINK_ETH_OVREHEAD) / 16;\n\t\tREG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);\n\t\t/* Update threshold */\n\t\tREG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, thresh);\n\t\t/* Update init credit */\n\t\tswitch (line_speed) {\n\t\tcase ELINK_SPEED_10000:\n\t\t\tinit_crd = thresh + 553 - 22;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(DEBUG, \"Invalid line_speed 0x%x\",\n\t\t\t\t line_speed);\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t}\n\tREG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, init_crd);\n\tPMD_DRV_LOG(DEBUG, \"PBF updated to speed %d credit %d\",\n\t\t line_speed, init_crd);\n\n\t/* Probe the credit changes */\n\tREG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x1);\n\tDELAY(1000 * 5);\n\tREG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0x0);\n\n\t/* Enable port */\n\tREG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port * 4, 0x0);\n\treturn ELINK_STATUS_OK;\n}\n\n/**\n * elink_get_emac_base - retrive emac base address\n *\n * @bp:\t\t\tdriver handle\n * @mdc_mdio_access:\taccess type\n * @port:\t\tport id\n *\n * This function selects the MDC/MDIO access (through emac0 or\n * emac1) depend on the mdc_mdio_access, port, port swapped. Each\n * phy has a default access mode, which could also be overridden\n * by nvram configuration. This parameter, whether this is the\n * default phy configuration, or the nvram overrun\n * configuration, is passed here as mdc_mdio_access and selects\n * the emac_base for the CL45 read/writes operations\n */\nstatic uint32_t elink_get_emac_base(struct bnx2x_softc *sc,\n\t\t\t\t uint32_t mdc_mdio_access, uint8_t port)\n{\n\tuint32_t emac_base = 0;\n\tswitch (mdc_mdio_access) {\n\tcase SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:\n\t\tbreak;\n\tcase SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:\n\t\tif (REG_RD(sc, NIG_REG_PORT_SWAP))\n\t\t\temac_base = GRCBASE_EMAC1;\n\t\telse\n\t\t\temac_base = GRCBASE_EMAC0;\n\t\tbreak;\n\tcase SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:\n\t\tif (REG_RD(sc, NIG_REG_PORT_SWAP))\n\t\t\temac_base = GRCBASE_EMAC0;\n\t\telse\n\t\t\temac_base = GRCBASE_EMAC1;\n\t\tbreak;\n\tcase SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:\n\t\temac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;\n\t\tbreak;\n\tcase SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:\n\t\temac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn emac_base;\n\n}\n\n/******************************************************************/\n/*\t\t\tCL22 access functions\t\t\t */\n/******************************************************************/\nstatic elink_status_t elink_cl22_write(struct bnx2x_softc *sc,\n\t\t\t\t struct elink_phy *phy,\n\t\t\t\t uint16_t reg, uint16_t val)\n{\n\tuint32_t tmp, mode;\n\tuint8_t i;\n\telink_status_t rc = ELINK_STATUS_OK;\n\t/* Switch to CL22 */\n\tmode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);\n\tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,\n\t mode & ~EMAC_MDIO_MODE_CLAUSE_45);\n\n\t/* Address */\n\ttmp = ((phy->addr << 21) | (reg << 16) | val |\n\t EMAC_MDIO_COMM_COMMAND_WRITE_22 | EMAC_MDIO_COMM_START_BUSY);\n\tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);\n\n\tfor (i = 0; i < 50; i++) {\n\t\tDELAY(10);\n\n\t\ttmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);\n\t\tif (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {\n\t\t\tDELAY(5);\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (tmp & EMAC_MDIO_COMM_START_BUSY) {\n\t\tPMD_DRV_LOG(DEBUG, \"write phy register failed\");\n\t\trc = ELINK_STATUS_TIMEOUT;\n\t}\n\tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);\n\treturn rc;\n}\n\nstatic elink_status_t elink_cl22_read(struct bnx2x_softc *sc,\n\t\t\t\t struct elink_phy *phy,\n\t\t\t\t uint16_t reg, uint16_t * ret_val)\n{\n\tuint32_t val, mode;\n\tuint16_t i;\n\telink_status_t rc = ELINK_STATUS_OK;\n\n\t/* Switch to CL22 */\n\tmode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);\n\tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,\n\t mode & ~EMAC_MDIO_MODE_CLAUSE_45);\n\n\t/* Address */\n\tval = ((phy->addr << 21) | (reg << 16) |\n\t EMAC_MDIO_COMM_COMMAND_READ_22 | EMAC_MDIO_COMM_START_BUSY);\n\tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);\n\n\tfor (i = 0; i < 50; i++) {\n\t\tDELAY(10);\n\n\t\tval = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);\n\t\tif (!(val & EMAC_MDIO_COMM_START_BUSY)) {\n\t\t\t*ret_val = (uint16_t) (val & EMAC_MDIO_COMM_DATA);\n\t\t\tDELAY(5);\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (val & EMAC_MDIO_COMM_START_BUSY) {\n\t\tPMD_DRV_LOG(DEBUG, \"read phy register failed\");\n\n\t\t*ret_val = 0;\n\t\trc = ELINK_STATUS_TIMEOUT;\n\t}\n\tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);\n\treturn rc;\n}\n\n/******************************************************************/\n/*\t\t\tCL45 access functions\t\t\t */\n/******************************************************************/\nstatic elink_status_t elink_cl45_read(struct bnx2x_softc *sc,\n\t\t\t\t struct elink_phy *phy, uint8_t devad,\n\t\t\t\t uint16_t reg, uint16_t * ret_val)\n{\n\tuint32_t val;\n\tuint16_t i;\n\telink_status_t rc = ELINK_STATUS_OK;\n\tif (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {\n\t\telink_set_mdio_clk(sc, phy->mdio_ctrl);\n\t}\n\n\tif (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)\n\t\telink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,\n\t\t\t EMAC_MDIO_STATUS_10MB);\n\t/* Address */\n\tval = ((phy->addr << 21) | (devad << 16) | reg |\n\t EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);\n\tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);\n\n\tfor (i = 0; i < 50; i++) {\n\t\tDELAY(10);\n\n\t\tval = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);\n\t\tif (!(val & EMAC_MDIO_COMM_START_BUSY)) {\n\t\t\tDELAY(5);\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (val & EMAC_MDIO_COMM_START_BUSY) {\n\t\tPMD_DRV_LOG(DEBUG, \"read phy register failed\");\n\t\telink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);\t// \"MDC/MDIO access timeout\"\n\n\t\t*ret_val = 0;\n\t\trc = ELINK_STATUS_TIMEOUT;\n\t} else {\n\t\t/* Data */\n\t\tval = ((phy->addr << 21) | (devad << 16) |\n\t\t EMAC_MDIO_COMM_COMMAND_READ_45 |\n\t\t EMAC_MDIO_COMM_START_BUSY);\n\t\tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);\n\n\t\tfor (i = 0; i < 50; i++) {\n\t\t\tDELAY(10);\n\n\t\t\tval = REG_RD(sc, phy->mdio_ctrl +\n\t\t\t\t EMAC_REG_EMAC_MDIO_COMM);\n\t\t\tif (!(val & EMAC_MDIO_COMM_START_BUSY)) {\n\t\t\t\t*ret_val =\n\t\t\t\t (uint16_t) (val & EMAC_MDIO_COMM_DATA);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (val & EMAC_MDIO_COMM_START_BUSY) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"read phy register failed\");\n\t\t\telink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);\t// \"MDC/MDIO access timeout\"\n\n\t\t\t*ret_val = 0;\n\t\t\trc = ELINK_STATUS_TIMEOUT;\n\t\t}\n\t}\n\t/* Work around for E3 A0 */\n\tif (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {\n\t\tphy->flags ^= ELINK_FLAGS_DUMMY_READ;\n\t\tif (phy->flags & ELINK_FLAGS_DUMMY_READ) {\n\t\t\tuint16_t temp_val;\n\t\t\telink_cl45_read(sc, phy, devad, 0xf, &temp_val);\n\t\t}\n\t}\n\n\tif (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)\n\t\telink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,\n\t\t\t EMAC_MDIO_STATUS_10MB);\n\treturn rc;\n}\n\nstatic elink_status_t elink_cl45_write(struct bnx2x_softc *sc,\n\t\t\t\t struct elink_phy *phy, uint8_t devad,\n\t\t\t\t uint16_t reg, uint16_t val)\n{\n\tuint32_t tmp;\n\tuint8_t i;\n\telink_status_t rc = ELINK_STATUS_OK;\n\tif (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {\n\t\telink_set_mdio_clk(sc, phy->mdio_ctrl);\n\t}\n\n\tif (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)\n\t\telink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,\n\t\t\t EMAC_MDIO_STATUS_10MB);\n\n\t/* Address */\n\ttmp = ((phy->addr << 21) | (devad << 16) | reg |\n\t EMAC_MDIO_COMM_COMMAND_ADDRESS | EMAC_MDIO_COMM_START_BUSY);\n\tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);\n\n\tfor (i = 0; i < 50; i++) {\n\t\tDELAY(10);\n\n\t\ttmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);\n\t\tif (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {\n\t\t\tDELAY(5);\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (tmp & EMAC_MDIO_COMM_START_BUSY) {\n\t\tPMD_DRV_LOG(DEBUG, \"write phy register failed\");\n\t\telink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);\t// \"MDC/MDIO access timeout\"\n\n\t\trc = ELINK_STATUS_TIMEOUT;\n\t} else {\n\t\t/* Data */\n\t\ttmp = ((phy->addr << 21) | (devad << 16) | val |\n\t\t EMAC_MDIO_COMM_COMMAND_WRITE_45 |\n\t\t EMAC_MDIO_COMM_START_BUSY);\n\t\tREG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);\n\n\t\tfor (i = 0; i < 50; i++) {\n\t\t\tDELAY(10);\n\n\t\t\ttmp = REG_RD(sc, phy->mdio_ctrl +\n\t\t\t\t EMAC_REG_EMAC_MDIO_COMM);\n\t\t\tif (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {\n\t\t\t\tDELAY(5);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (tmp & EMAC_MDIO_COMM_START_BUSY) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"write phy register failed\");\n\t\t\telink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT);\t// \"MDC/MDIO access timeout\"\n\n\t\t\trc = ELINK_STATUS_TIMEOUT;\n\t\t}\n\t}\n\t/* Work around for E3 A0 */\n\tif (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {\n\t\tphy->flags ^= ELINK_FLAGS_DUMMY_READ;\n\t\tif (phy->flags & ELINK_FLAGS_DUMMY_READ) {\n\t\t\tuint16_t temp_val;\n\t\t\telink_cl45_read(sc, phy, devad, 0xf, &temp_val);\n\t\t}\n\t}\n\tif (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)\n\t\telink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,\n\t\t\t EMAC_MDIO_STATUS_10MB);\n\treturn rc;\n}\n\n/******************************************************************/\n/*\t\t\tEEE section\t\t\t\t */\n/******************************************************************/\nstatic uint8_t elink_eee_has_cap(struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tif (REG_RD(sc, params->shmem2_base) <=\n\t offsetof(struct shmem2_region, eee_status[params->port]))\n\t\t return 0;\n\n\treturn 1;\n}\n\nstatic elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode,\n\t\t\t\t\t uint32_t * idle_timer)\n{\n\tswitch (nvram_mode) {\n\tcase PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:\n\t\t*idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME;\n\t\tbreak;\n\tcase PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:\n\t\t*idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME;\n\t\tbreak;\n\tcase PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:\n\t\t*idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME;\n\t\tbreak;\n\tdefault:\n\t\t*idle_timer = 0;\n\t\tbreak;\n\t}\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer,\n\t\t\t\t\t uint32_t * nvram_mode)\n{\n\tswitch (idle_timer) {\n\tcase ELINK_EEE_MODE_NVRAM_BALANCED_TIME:\n\t\t*nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;\n\t\tbreak;\n\tcase ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME:\n\t\t*nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;\n\t\tbreak;\n\tcase ELINK_EEE_MODE_NVRAM_LATENCY_TIME:\n\t\t*nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;\n\t\tbreak;\n\tdefault:\n\t\t*nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;\n\t\tbreak;\n\t}\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic uint32_t elink_eee_calc_timer(struct elink_params *params)\n{\n\tuint32_t eee_mode, eee_idle;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tif (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {\n\t\tif (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {\n\t\t\t/* time value in eee_mode --> used directly */\n\t\t\teee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;\n\t\t} else {\n\t\t\t/* hsi value in eee_mode --> time */\n\t\t\tif (elink_eee_nvram_to_time(params->eee_mode &\n\t\t\t\t\t\t ELINK_EEE_MODE_NVRAM_MASK,\n\t\t\t\t\t\t &eee_idle))\n\t\t\t\treturn 0;\n\t\t}\n\t} else {\n\t\t/* hsi values in nvram --> time */\n\t\teee_mode = ((REG_RD(sc, params->shmem_base +\n\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t dev_info.port_feature_config\n\t\t\t\t\t [params->\n\t\t\t\t\t port].eee_power_mode)) &\n\t\t\t PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>\n\t\t\t PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);\n\n\t\tif (elink_eee_nvram_to_time(eee_mode, &eee_idle))\n\t\t\treturn 0;\n\t}\n\n\treturn eee_idle;\n}\n\nstatic elink_status_t elink_eee_set_timers(struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tuint32_t eee_idle = 0, eee_mode;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\teee_idle = elink_eee_calc_timer(params);\n\n\tif (eee_idle) {\n\t\tREG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),\n\t\t eee_idle);\n\t} else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&\n\t\t (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&\n\t\t (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {\n\t\tPMD_DRV_LOG(DEBUG, \"Error: Tx LPI is enabled with timer 0\");\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\n\tvars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);\n\tif (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {\n\t\t/* eee_idle in 1u --> eee_status in 16u */\n\t\teee_idle >>= 4;\n\t\tvars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |\n\t\t SHMEM_EEE_TIME_OUTPUT_BIT;\n\t} else {\n\t\tif (elink_eee_time_to_nvram(eee_idle, &eee_mode))\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\tvars->eee_status |= eee_mode;\n\t}\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_eee_initial_config(struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars,\n\t\t\t\t\t uint8_t mode)\n{\n\tvars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;\n\n\t/* Propogate params' bits --> vars (for migration exposure) */\n\tif (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)\n\t\tvars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;\n\telse\n\t\tvars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;\n\n\tif (params->eee_mode & ELINK_EEE_MODE_ADV_LPI)\n\t\tvars->eee_status |= SHMEM_EEE_REQUESTED_BIT;\n\telse\n\t\tvars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;\n\n\treturn elink_eee_set_timers(params, vars);\n}\n\nstatic elink_status_t elink_eee_disable(struct elink_phy *phy,\n\t\t\t\t\tstruct elink_params *params,\n\t\t\t\t\tstruct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\n\t/* Make Certain LPI is disabled */\n\tREG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);\n\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);\n\n\tvars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_eee_advertise(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars,\n\t\t\t\t\t uint8_t modes)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val = 0;\n\n\t/* Mask events preventing LPI generation */\n\tREG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);\n\n\tif (modes & SHMEM_EEE_10G_ADV) {\n\t\tPMD_DRV_LOG(DEBUG, \"Advertise 10GBase-T EEE\");\n\t\tval |= 0x8;\n\t}\n\tif (modes & SHMEM_EEE_1G_ADV) {\n\t\tPMD_DRV_LOG(DEBUG, \"Advertise 1GBase-T EEE\");\n\t\tval |= 0x4;\n\t}\n\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);\n\n\tvars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;\n\tvars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_update_mng_eee(struct elink_params *params,\n\t\t\t\t uint32_t eee_status)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tif (elink_eee_has_cap(params))\n\t\tREG_WR(sc, params->shmem2_base +\n\t\t offsetof(struct shmem2_region,\n\t\t\t\teee_status[params->port]), eee_status);\n}\n\nstatic void elink_eee_an_resolve(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t adv = 0, lp = 0;\n\tuint32_t lp_adv = 0;\n\tuint8_t neg = 0;\n\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);\n\n\tif (lp & 0x2) {\n\t\tlp_adv |= SHMEM_EEE_100M_ADV;\n\t\tif (adv & 0x2) {\n\t\t\tif (vars->line_speed == ELINK_SPEED_100)\n\t\t\t\tneg = 1;\n\t\t\tPMD_DRV_LOG(DEBUG, \"EEE negotiated - 100M\");\n\t\t}\n\t}\n\tif (lp & 0x14) {\n\t\tlp_adv |= SHMEM_EEE_1G_ADV;\n\t\tif (adv & 0x14) {\n\t\t\tif (vars->line_speed == ELINK_SPEED_1000)\n\t\t\t\tneg = 1;\n\t\t\tPMD_DRV_LOG(DEBUG, \"EEE negotiated - 1G\");\n\t\t}\n\t}\n\tif (lp & 0x68) {\n\t\tlp_adv |= SHMEM_EEE_10G_ADV;\n\t\tif (adv & 0x68) {\n\t\t\tif (vars->line_speed == ELINK_SPEED_10000)\n\t\t\t\tneg = 1;\n\t\t\tPMD_DRV_LOG(DEBUG, \"EEE negotiated - 10G\");\n\t\t}\n\t}\n\n\tvars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;\n\tvars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);\n\n\tif (neg) {\n\t\tPMD_DRV_LOG(DEBUG, \"EEE is active\");\n\t\tvars->eee_status |= SHMEM_EEE_ACTIVE_BIT;\n\t}\n}\n\n/******************************************************************/\n/*\t\t\tBSC access functions from E3\t */\n/******************************************************************/\nstatic void elink_bsc_module_sel(struct elink_params *params)\n{\n\tint idx;\n\tuint32_t board_cfg, sfp_ctrl;\n\tuint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port = params->port;\n\t/* Read I2C output PINs */\n\tboard_cfg = REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.shared_hw_config.board));\n\ti2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;\n\ti2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>\n\t SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;\n\n\t/* Read I2C output value */\n\tsfp_ctrl = REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_hw_config[port].\n\t\t\t\t e3_cmn_pin_cfg));\n\ti2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;\n\ti2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;\n\tPMD_DRV_LOG(DEBUG, \"Setting BSC switch\");\n\tfor (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)\n\t\telink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);\n}\n\nstatic elink_status_t elink_bsc_read(struct elink_params *params,\n\t\t\t\t struct bnx2x_softc *sc,\n\t\t\t\t uint8_t sl_devid,\n\t\t\t\t uint16_t sl_addr,\n\t\t\t\t uint8_t lc_addr,\n\t\t\t\t uint8_t xfer_cnt, uint32_t * data_array)\n{\n\tuint32_t val, i;\n\telink_status_t rc = ELINK_STATUS_OK;\n\n\tif (xfer_cnt > 16) {\n\t\tPMD_DRV_LOG(DEBUG, \"invalid xfer_cnt %d. Max is 16 bytes\",\n\t\t\t xfer_cnt);\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\tif (params)\n\t\telink_bsc_module_sel(params);\n\n\txfer_cnt = 16 - lc_addr;\n\n\t/* Enable the engine */\n\tval = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);\n\tval |= MCPR_IMC_COMMAND_ENABLE;\n\tREG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);\n\n\t/* Program slave device ID */\n\tval = (sl_devid << 16) | sl_addr;\n\tREG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);\n\n\t/* Start xfer with 0 byte to update the address pointer ??? */\n\tval = (MCPR_IMC_COMMAND_ENABLE) |\n\t (MCPR_IMC_COMMAND_WRITE_OP <<\n\t MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |\n\t (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);\n\tREG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);\n\n\t/* Poll for completion */\n\ti = 0;\n\tval = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);\n\twhile (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {\n\t\tDELAY(10);\n\t\tval = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);\n\t\tif (i++ > 1000) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"wr 0 byte timed out after %d try\",\n\t\t\t\t i);\n\t\t\trc = ELINK_STATUS_TIMEOUT;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (rc == ELINK_STATUS_TIMEOUT)\n\t\treturn rc;\n\n\t/* Start xfer with read op */\n\tval = (MCPR_IMC_COMMAND_ENABLE) |\n\t (MCPR_IMC_COMMAND_READ_OP <<\n\t MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |\n\t (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |\n\t (xfer_cnt);\n\tREG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);\n\n\t/* Poll for completion */\n\ti = 0;\n\tval = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);\n\twhile (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {\n\t\tDELAY(10);\n\t\tval = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);\n\t\tif (i++ > 1000) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"rd op timed out after %d try\", i);\n\t\t\trc = ELINK_STATUS_TIMEOUT;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (rc == ELINK_STATUS_TIMEOUT)\n\t\treturn rc;\n\n\tfor (i = (lc_addr >> 2); i < 4; i++) {\n\t\tdata_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i * 4));\n#ifdef __BIG_ENDIAN\n\t\tdata_array[i] = ((data_array[i] & 0x000000ff) << 24) |\n\t\t ((data_array[i] & 0x0000ff00) << 8) |\n\t\t ((data_array[i] & 0x00ff0000) >> 8) |\n\t\t ((data_array[i] & 0xff000000) >> 24);\n#endif\n\t}\n\treturn rc;\n}\n\nstatic void elink_cl45_read_or_write(struct bnx2x_softc *sc,\n\t\t\t\t struct elink_phy *phy, uint8_t devad,\n\t\t\t\t uint16_t reg, uint16_t or_val)\n{\n\tuint16_t val;\n\telink_cl45_read(sc, phy, devad, reg, &val);\n\telink_cl45_write(sc, phy, devad, reg, val | or_val);\n}\n\nstatic void elink_cl45_read_and_write(struct bnx2x_softc *sc,\n\t\t\t\t struct elink_phy *phy,\n\t\t\t\t uint8_t devad, uint16_t reg,\n\t\t\t\t uint16_t and_val)\n{\n\tuint16_t val;\n\telink_cl45_read(sc, phy, devad, reg, &val);\n\telink_cl45_write(sc, phy, devad, reg, val & and_val);\n}\n\nstatic uint8_t elink_get_warpcore_lane(struct elink_params *params)\n{\n\tuint8_t lane = 0;\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t path_swap, path_swap_ovr;\n\tuint8_t path, port;\n\n\tpath = SC_PATH(sc);\n\tport = params->port;\n\n\tif (elink_is_4_port_mode(sc)) {\n\t\tuint32_t port_swap, port_swap_ovr;\n\n\t\t/* Figure out path swap value */\n\t\tpath_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);\n\t\tif (path_swap_ovr & 0x1)\n\t\t\tpath_swap = (path_swap_ovr & 0x2);\n\t\telse\n\t\t\tpath_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);\n\n\t\tif (path_swap)\n\t\t\tpath = path ^ 1;\n\n\t\t/* Figure out port swap value */\n\t\tport_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);\n\t\tif (port_swap_ovr & 0x1)\n\t\t\tport_swap = (port_swap_ovr & 0x2);\n\t\telse\n\t\t\tport_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);\n\n\t\tif (port_swap)\n\t\t\tport = port ^ 1;\n\n\t\tlane = (port << 1) + path;\n\t} else {\t\t/* Two port mode - no port swap */\n\n\t\t/* Figure out path swap value */\n\t\tpath_swap_ovr = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);\n\t\tif (path_swap_ovr & 0x1) {\n\t\t\tpath_swap = (path_swap_ovr & 0x2);\n\t\t} else {\n\t\t\tpath_swap = REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);\n\t\t}\n\t\tif (path_swap)\n\t\t\tpath = path ^ 1;\n\n\t\tlane = path << 1;\n\t}\n\treturn lane;\n}\n\nstatic void elink_set_aer_mmd(struct elink_params *params,\n\t\t\t struct elink_phy *phy)\n{\n\tuint32_t ser_lane;\n\tuint16_t offset, aer_val;\n\tstruct bnx2x_softc *sc = params->sc;\n\tser_lane = ((params->lane_config &\n\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>\n\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);\n\n\toffset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?\n\t (phy->addr + ser_lane) : 0;\n\n\tif (USES_WARPCORE(sc)) {\n\t\taer_val = elink_get_warpcore_lane(params);\n\t\t/* In Dual-lane mode, two lanes are joined together,\n\t\t * so in order to configure them, the AER broadcast method is\n\t\t * used here.\n\t\t * 0x200 is the broadcast address for lanes 0,1\n\t\t * 0x201 is the broadcast address for lanes 2,3\n\t\t */\n\t\tif (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)\n\t\t\taer_val = (aer_val >> 1) | 0x200;\n\t} else if (CHIP_IS_E2(sc))\n\t\taer_val = 0x3800 + offset - 1;\n\telse\n\t\taer_val = 0x3800 + offset;\n\n\tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n\t\t\t MDIO_AER_BLOCK_AER_REG, aer_val);\n\n}\n\n/******************************************************************/\n/*\t\t\tInternal phy section\t\t\t */\n/******************************************************************/\n\nstatic void elink_set_serdes_access(struct bnx2x_softc *sc, uint8_t port)\n{\n\tuint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;\n\n\t/* Set Clause 22 */\n\tREG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 1);\n\tREG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);\n\tDELAY(500);\n\tREG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);\n\tDELAY(500);\n\t/* Set Clause 45 */\n\tREG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port * 0x10, 0);\n}\n\nstatic void elink_serdes_deassert(struct bnx2x_softc *sc, uint8_t port)\n{\n\tuint32_t val;\n\n\tPMD_DRV_LOG(DEBUG, \"elink_serdes_deassert\");\n\n\tval = ELINK_SERDES_RESET_BITS << (port * 16);\n\n\t/* Reset and unreset the SerDes/XGXS */\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);\n\tDELAY(500);\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);\n\n\telink_set_serdes_access(sc, port);\n\n\tREG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port * 0x10,\n\t ELINK_DEFAULT_PHY_DEV_ADDR);\n}\n\nstatic void elink_xgxs_specific_func(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t uint32_t action)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tswitch (action) {\n\tcase ELINK_PHY_INIT:\n\t\t/* Set correct devad */\n\t\tREG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port * 0x18, 0);\n\t\tREG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port * 0x18,\n\t\t phy->def_md_devad);\n\t\tbreak;\n\t}\n}\n\nstatic void elink_xgxs_deassert(struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port;\n\tuint32_t val;\n\tPMD_DRV_LOG(DEBUG, \"elink_xgxs_deassert\");\n\tport = params->port;\n\n\tval = ELINK_XGXS_RESET_BITS << (port * 16);\n\n\t/* Reset and unreset the SerDes/XGXS */\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);\n\tDELAY(500);\n\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);\n\telink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params,\n\t\t\t\t ELINK_PHY_INIT);\n}\n\nstatic void elink_calc_ieee_aneg_adv(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t uint16_t * ieee_fc)\n{\n\t*ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;\n\t/* Resolve pause mode and advertisement Please refer to Table\n\t * 28B-3 of the 802.3ab-1999 spec\n\t */\n\n\tswitch (phy->req_flow_ctrl) {\n\tcase ELINK_FLOW_CTRL_AUTO:\n\t\tswitch (params->req_fc_auto_adv) {\n\t\tcase ELINK_FLOW_CTRL_BOTH:\n\t\t\t*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;\n\t\t\tbreak;\n\t\tcase ELINK_FLOW_CTRL_RX:\n\t\tcase ELINK_FLOW_CTRL_TX:\n\t\t\t*ieee_fc |=\n\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase ELINK_FLOW_CTRL_TX:\n\t\t*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;\n\t\tbreak;\n\n\tcase ELINK_FLOW_CTRL_RX:\n\tcase ELINK_FLOW_CTRL_BOTH:\n\t\t*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;\n\t\tbreak;\n\n\tcase ELINK_FLOW_CTRL_NONE:\n\tdefault:\n\t\t*ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;\n\t\tbreak;\n\t}\n\tPMD_DRV_LOG(DEBUG, \"ieee_fc = 0x%x\", *ieee_fc);\n}\n\nstatic void set_phy_vars(struct elink_params *params, struct elink_vars *vars)\n{\n\tuint8_t actual_phy_idx, phy_index, link_cfg_idx;\n\tuint8_t phy_config_swapped = params->multi_phy_config &\n\t PORT_HW_CFG_PHY_SWAPPED_ENABLED;\n\tfor (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;\n\t phy_index++) {\n\t\tlink_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);\n\t\tactual_phy_idx = phy_index;\n\t\tif (phy_config_swapped) {\n\t\t\tif (phy_index == ELINK_EXT_PHY1)\n\t\t\t\tactual_phy_idx = ELINK_EXT_PHY2;\n\t\t\telse if (phy_index == ELINK_EXT_PHY2)\n\t\t\t\tactual_phy_idx = ELINK_EXT_PHY1;\n\t\t}\n\t\tparams->phy[actual_phy_idx].req_flow_ctrl =\n\t\t params->req_flow_ctrl[link_cfg_idx];\n\n\t\tparams->phy[actual_phy_idx].req_line_speed =\n\t\t params->req_line_speed[link_cfg_idx];\n\n\t\tparams->phy[actual_phy_idx].speed_cap_mask =\n\t\t params->speed_cap_mask[link_cfg_idx];\n\n\t\tparams->phy[actual_phy_idx].req_duplex =\n\t\t params->req_duplex[link_cfg_idx];\n\n\t\tif (params->req_line_speed[link_cfg_idx] ==\n\t\t ELINK_SPEED_AUTO_NEG)\n\t\t\tvars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;\n\n\t\tPMD_DRV_LOG(DEBUG, \"req_flow_ctrl %x, req_line_speed %x,\"\n\t\t\t \" speed_cap_mask %x\",\n\t\t\t params->phy[actual_phy_idx].req_flow_ctrl,\n\t\t\t params->phy[actual_phy_idx].req_line_speed,\n\t\t\t params->phy[actual_phy_idx].speed_cap_mask);\n\t}\n}\n\nstatic void elink_ext_phy_set_pause(struct elink_params *params,\n\t\t\t\t struct elink_phy *phy,\n\t\t\t\t struct elink_vars *vars)\n{\n\tuint16_t val;\n\tstruct bnx2x_softc *sc = params->sc;\n\t/* Read modify write pause advertizing */\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);\n\n\tval &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;\n\n\t/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */\n\telink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);\n\tif ((vars->ieee_fc &\n\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==\n\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {\n\t\tval |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;\n\t}\n\tif ((vars->ieee_fc &\n\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==\n\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {\n\t\tval |= MDIO_AN_REG_ADV_PAUSE_PAUSE;\n\t}\n\tPMD_DRV_LOG(DEBUG, \"Ext phy AN advertize 0x%x\", val);\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);\n}\n\nstatic void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result)\n{\t\t\t\t/* LD LP */\n\tswitch (pause_result) {\t/* ASYM P ASYM P */\n\tcase 0xb:\t\t/* 1 0 1 1 */\n\t\tvars->flow_ctrl = ELINK_FLOW_CTRL_TX;\n\t\tbreak;\n\n\tcase 0xe:\t\t/* 1 1 1 0 */\n\t\tvars->flow_ctrl = ELINK_FLOW_CTRL_RX;\n\t\tbreak;\n\n\tcase 0x5:\t\t/* 0 1 0 1 */\n\tcase 0x7:\t\t/* 0 1 1 1 */\n\tcase 0xd:\t\t/* 1 1 0 1 */\n\tcase 0xf:\t\t/* 1 1 1 1 */\n\t\tvars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\tif (pause_result & (1 << 0))\n\t\tvars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;\n\tif (pause_result & (1 << 1))\n\t\tvars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;\n\n}\n\nstatic void elink_ext_phy_update_adv_fc(struct elink_phy *phy,\n\t\t\t\t\tstruct elink_params *params,\n\t\t\t\t\tstruct elink_vars *vars)\n{\n\tuint16_t ld_pause;\t/* local */\n\tuint16_t lp_pause;\t/* link partner */\n\tuint16_t pause_result;\n\tstruct bnx2x_softc *sc = params->sc;\n\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) {\n\t\telink_cl22_read(sc, phy, 0x4, &ld_pause);\n\t\telink_cl22_read(sc, phy, 0x5, &lp_pause);\n\t} else if (CHIP_IS_E3(sc) && ELINK_SINGLE_MEDIA_DIRECT(params)) {\n\t\tuint8_t lane = elink_get_warpcore_lane(params);\n\t\tuint16_t gp_status, gp_mask;\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,\n\t\t\t\t&gp_status);\n\t\tgp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |\n\t\t\t MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<\n\t\t lane;\n\t\tif ((gp_status & gp_mask) == gp_mask) {\n\t\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\t\tMDIO_AN_REG_ADV_PAUSE, &ld_pause);\n\t\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\t\tMDIO_AN_REG_LP_AUTO_NEG, &lp_pause);\n\t\t} else {\n\t\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\t\tMDIO_AN_REG_CL37_FC_LD, &ld_pause);\n\t\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\t\tMDIO_AN_REG_CL37_FC_LP, &lp_pause);\n\t\t\tld_pause = ((ld_pause &\n\t\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)\n\t\t\t\t << 3);\n\t\t\tlp_pause = ((lp_pause &\n\t\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)\n\t\t\t\t << 3);\n\t\t}\n\t} else {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_AN_DEVAD,\n\t\t\t\tMDIO_AN_REG_ADV_PAUSE, &ld_pause);\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_AN_DEVAD,\n\t\t\t\tMDIO_AN_REG_LP_AUTO_NEG, &lp_pause);\n\t}\n\tpause_result = (ld_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;\n\tpause_result |= (lp_pause & MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;\n\tPMD_DRV_LOG(DEBUG, \"Ext PHY pause result 0x%x\", pause_result);\n\telink_pause_resolve(vars, pause_result);\n\n}\n\nstatic uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,\n\t\t\t\t\tstruct elink_params *params,\n\t\t\t\t\tstruct elink_vars *vars)\n{\n\tuint8_t ret = 0;\n\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\tif (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {\n\t\t/* Update the advertised flow-controled of LD/LP in AN */\n\t\tif (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)\n\t\t\telink_ext_phy_update_adv_fc(phy, params, vars);\n\t\t/* But set the flow-control result as the requested one */\n\t\tvars->flow_ctrl = phy->req_flow_ctrl;\n\t} else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)\n\t\tvars->flow_ctrl = params->req_fc_auto_adv;\n\telse if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {\n\t\tret = 1;\n\t\telink_ext_phy_update_adv_fc(phy, params, vars);\n\t}\n\treturn ret;\n}\n\n/******************************************************************/\n/*\t\t\tWarpcore section\t\t\t */\n/******************************************************************/\n/* The init_internal_warpcore should mirror the xgxs,\n * i.e. reset the lane (if needed), set aer for the\n * init configuration, and set/clear SGMII flag. Internal\n * phy init is done purely in phy_init stage.\n */\n#define WC_TX_DRIVER(post2, idriver, ipre) \\\n\t((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \\\n\t (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \\\n\t (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))\n\n#define WC_TX_FIR(post, main, pre) \\\n\t((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \\\n\t (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \\\n\t (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))\n\nstatic void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t i;\n\tstatic struct elink_reg_set reg_set[] = {\n\t\t/* Step 1 - Program the TX/RX alignment markers */\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},\n\t\t/* Step 2 - Configure the NP registers */\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}\n\t};\n\tPMD_DRV_LOG(DEBUG, \"Enabling 20G-KR2\");\n\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_CL49_USERB0_CTRL, (3 << 6));\n\n\tfor (i = 0; i < ARRAY_SIZE(reg_set); i++)\n\t\telink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,\n\t\t\t\t reg_set[i].val);\n\n\t/* Start KR2 work-around timer which handles BNX2X8073 link-parner */\n\tvars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;\n\telink_update_link_attr(params, vars->link_attr_sync);\n}\n\nstatic void elink_disable_kr2(struct elink_params *params,\n\t\t\t struct elink_vars *vars, struct elink_phy *phy)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t i;\n\tstatic struct elink_reg_set reg_set[] = {\n\t\t/* Step 1 - Program the TX/RX alignment markers */\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}\n\t};\n\tPMD_DRV_LOG(DEBUG, \"Disabling 20G-KR2\");\n\n\tfor (i = 0; i < ARRAY_SIZE(reg_set); i++)\n\t\telink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,\n\t\t\t\t reg_set[i].val);\n\tvars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;\n\telink_update_link_attr(params, vars->link_attr_sync);\n\n\tvars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;\n}\n\nstatic void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tPMD_DRV_LOG(DEBUG, \"Configure WC for LPI pass through\");\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);\n}\n\nstatic void elink_warpcore_restart_AN_KR(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params)\n{\n\t/* Restart autoneg on the leading lane only */\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t lane = elink_get_warpcore_lane(params);\n\tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n\t\t\t MDIO_AER_BLOCK_AER_REG, lane);\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n\t\t\t MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);\n\n\t/* Restore AER */\n\telink_set_aer_mmd(params, phy);\n}\n\nstatic void elink_warpcore_enable_AN_KR(struct elink_phy *phy,\n\t\t\t\t\tstruct elink_params *params,\n\t\t\t\t\tstruct elink_vars *vars)\n{\n\tuint16_t lane, i, cl72_ctrl, an_adv = 0;\n\tstruct bnx2x_softc *sc = params->sc;\n\tstatic struct elink_reg_set reg_set[] = {\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},\n\t\t{MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},\n\t\t/* Disable Autoneg: re-enable it after adv is done. */\n\t\t{MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},\n\t\t{MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},\n\t};\n\tPMD_DRV_LOG(DEBUG, \"Enable Auto Negotiation for KR\");\n\t/* Set to default registers that may be overriden by 10G force */\n\tfor (i = 0; i < ARRAY_SIZE(reg_set); i++)\n\t\telink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,\n\t\t\t\t reg_set[i].val);\n\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);\n\tcl72_ctrl &= 0x08ff;\n\tcl72_ctrl |= 0x3800;\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);\n\n\t/* Check adding advertisement for 1G KX */\n\tif (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&\n\t (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||\n\t (vars->line_speed == ELINK_SPEED_1000)) {\n\t\tuint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;\n\t\tan_adv |= (1 << 5);\n\n\t\t/* Enable CL37 1G Parallel Detect */\n\t\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);\n\t\tPMD_DRV_LOG(DEBUG, \"Advertize 1G\");\n\t}\n\tif (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&\n\t (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||\n\t (vars->line_speed == ELINK_SPEED_10000)) {\n\t\t/* Check adding advertisement for 10G KR */\n\t\tan_adv |= (1 << 7);\n\t\t/* Enable 10G Parallel Detect */\n\t\tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n\t\t\t\t MDIO_AER_BLOCK_AER_REG, 0);\n\n\t\telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\t MDIO_WC_REG_PAR_DET_10G_CTRL, 1);\n\t\telink_set_aer_mmd(params, phy);\n\t\tPMD_DRV_LOG(DEBUG, \"Advertize 10G\");\n\t}\n\n\t/* Set Transmit PMD settings */\n\tlane = elink_get_warpcore_lane(params);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,\n\t\t\t WC_TX_DRIVER(0x02, 0x06, 0x09));\n\t/* Configure the next lane if dual mode */\n\tif (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)\n\t\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * (lane + 1),\n\t\t\t\t WC_TX_DRIVER(0x02, 0x06, 0x09));\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 0x03f0);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 0x03f0);\n\n\t/* Advertised speeds */\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n\t\t\t MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);\n\n\t/* Advertised and set FEC (Forward Error Correction) */\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n\t\t\t MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,\n\t\t\t (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |\n\t\t\t MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));\n\n\t/* Enable CL37 BAM */\n\tif (REG_RD(sc, params->shmem_base +\n\t\t offsetof(struct shmem_region,\n\t\t\t dev_info.port_hw_config[params->port].\n\t\t\t default_cfg)) &\n\t PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {\n\t\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t\t MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,\n\t\t\t\t\t 1);\n\t\tPMD_DRV_LOG(DEBUG, \"Enable CL37 BAM on KR\");\n\t}\n\n\t/* Advertise pause */\n\telink_ext_phy_set_pause(params, phy, vars);\n\tvars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_DIGITAL5_MISC7, 0x100);\n\n\t/* Over 1G - AN local device user page 1 */\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_DIGITAL3_UP1, 0x1f);\n\n\tif (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n\t (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||\n\t (phy->req_line_speed == ELINK_SPEED_20000)) {\n\n\t\tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n\t\t\t\t MDIO_AER_BLOCK_AER_REG, lane);\n\n\t\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t\t MDIO_WC_REG_RX1_PCI_CTRL +\n\t\t\t\t\t (0x10 * lane), (1 << 11));\n\n\t\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);\n\t\telink_set_aer_mmd(params, phy);\n\n\t\telink_warpcore_enable_AN_KR2(phy, params, vars);\n\t} else {\n\t\telink_disable_kr2(params, vars, phy);\n\t}\n\n\t/* Enable Autoneg: only on the main lane */\n\telink_warpcore_restart_AN_KR(phy, params);\n}\n\nstatic void elink_warpcore_set_10G_KR(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val16, i, lane;\n\tstatic struct elink_reg_set reg_set[] = {\n\t\t/* Disable Autoneg */\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,\n\t\t 0x3f00},\n\t\t{MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},\n\t\t{MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},\n\t\t/* Leave cl72 training enable, needed for KR */\n\t\t{MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}\n\t};\n\n\tfor (i = 0; i < ARRAY_SIZE(reg_set); i++)\n\t\telink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,\n\t\t\t\t reg_set[i].val);\n\n\tlane = elink_get_warpcore_lane(params);\n\t/* Global registers */\n\tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n\t\t\t MDIO_AER_BLOCK_AER_REG, 0);\n\t/* Disable CL36 PCS Tx */\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);\n\tval16 &= ~(0x0011 << lane);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);\n\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);\n\tval16 |= (0x0303 << (lane << 1));\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);\n\t/* Restore AER */\n\telink_set_aer_mmd(params, phy);\n\t/* Set speed via PMA/PMD register */\n\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD,\n\t\t\t MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);\n\n\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD,\n\t\t\t MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);\n\n\t/* Enable encoded forced speed */\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);\n\n\t/* Turn TX scramble payload only the 64/66 scrambler */\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_TX66_CONTROL, 0x9);\n\n\t/* Turn RX scramble payload only the 64/66 scrambler */\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_RX66_CONTROL, 0xF9);\n\n\t/* Set and clear loopback to cause a reset to 64/66 decoder */\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);\n\n}\n\nstatic void elink_warpcore_set_10G_XFI(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t uint8_t is_xfi)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t misc1_val, tap_val, tx_driver_val, lane, val;\n\tuint32_t cfg_tap_val, tx_drv_brdct, tx_equal;\n\n\t/* Hold rxSeqStart */\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);\n\n\t/* Hold tx_fifo_reset */\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);\n\n\t/* Disable CL73 AN */\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);\n\n\t/* Disable 100FX Enable and Auto-Detect */\n\telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_FX100_CTRL1, 0xFFFA);\n\n\t/* Disable 100FX Idle detect */\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_FX100_CTRL3, 0x0080);\n\n\t/* Set Block address to Remote PHY & Clear forced_speed[5] */\n\telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);\n\n\t/* Turn off auto-detect & fiber mode */\n\telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,\n\t\t\t\t 0xFFEE);\n\n\t/* Set filter_force_link, disable_false_link and parallel_detect */\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,\n\t\t\t ((val | 0x0006) & 0xFFFE));\n\n\t/* Set XFI / SFI */\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);\n\n\tmisc1_val &= ~(0x1f);\n\n\tif (is_xfi) {\n\t\tmisc1_val |= 0x5;\n\t\ttap_val = WC_TX_FIR(0x08, 0x37, 0x00);\n\t\ttx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);\n\t} else {\n\t\tcfg_tap_val = REG_RD(sc, params->shmem_base +\n\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t dev_info.port_hw_config[params->\n\t\t\t\t\t\t\t\t port].sfi_tap_values));\n\n\t\ttx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;\n\n\t\ttx_drv_brdct = (cfg_tap_val &\n\t\t\t\tPORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>\n\t\t PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;\n\n\t\tmisc1_val |= 0x9;\n\n\t\t/* TAP values are controlled by nvram, if value there isn't 0 */\n\t\tif (tx_equal)\n\t\t\ttap_val = (uint16_t) tx_equal;\n\t\telse\n\t\t\ttap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);\n\n\t\tif (tx_drv_brdct)\n\t\t\ttx_driver_val =\n\t\t\t WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct, 0x06);\n\t\telse\n\t\t\ttx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);\n\t}\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);\n\n\t/* Set Transmit PMD settings */\n\tlane = elink_get_warpcore_lane(params);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_TX_FIR_TAP,\n\t\t\t tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,\n\t\t\t tx_driver_val);\n\n\t/* Enable fiber mode, enable and invert sig_det */\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);\n\n\t/* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);\n\n\telink_warpcore_set_lpi_passthrough(phy, params);\n\n\t/* 10G XFI Full Duplex */\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);\n\n\t/* Release tx_fifo_reset */\n\telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,\n\t\t\t\t 0xFFFE);\n\t/* Release rxSeqStart */\n\telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);\n}\n\nstatic void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params)\n{\n\tuint16_t val;\n\tstruct bnx2x_softc *sc = params->sc;\n\t/* Set global registers, so set AER lane to 0 */\n\tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n\t\t\t MDIO_AER_BLOCK_AER_REG, 0);\n\n\t/* Disable sequencer */\n\telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1 << 13));\n\n\telink_set_aer_mmd(params, phy);\n\n\telink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_WC_REG_PMD_KR_CONTROL, ~(1 << 1));\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);\n\t/* Turn off CL73 */\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_CL73_USERB0_CTRL, &val);\n\tval &= ~(1 << 5);\n\tval |= (1 << 6);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_CL73_USERB0_CTRL, val);\n\n\t/* Set 20G KR2 force speed */\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);\n\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_DIGITAL4_MISC3, (1 << 7));\n\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);\n\tval &= ~(3 << 14);\n\tval |= (1 << 15);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);\n\n\t/* Enable sequencer (over lane 0) */\n\tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n\t\t\t MDIO_AER_BLOCK_AER_REG, 0);\n\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1 << 13));\n\n\telink_set_aer_mmd(params, phy);\n}\n\nstatic void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc *sc,\n\t\t\t\t\t struct elink_phy *phy, uint16_t lane)\n{\n\t/* Rx0 anaRxControl1G */\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);\n\n\t/* Rx2 anaRxControl1G */\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);\n\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW0, 0xE070);\n\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW1, 0xC0D0);\n\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW2, 0xA0B0);\n\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_RX66_SCW3, 0x8090);\n\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);\n\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);\n\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);\n\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);\n\n\t/* Serdes Digital Misc1 */\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);\n\n\t/* Serdes Digital4 Misc3 */\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);\n\n\t/* Set Transmit PMD settings */\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_TX_FIR_TAP,\n\t\t\t (WC_TX_FIR(0x12, 0x2d, 0x00) |\n\t\t\t MDIO_WC_REG_TX_FIR_TAP_ENABLE));\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane,\n\t\t\t WC_TX_DRIVER(0x02, 0x02, 0x02));\n}\n\nstatic void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t uint8_t fiber_mode,\n\t\t\t\t\t uint8_t always_autoneg)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val16, digctrl_kx1, digctrl_kx2;\n\n\t/* Clear XFI clock comp in non-10G single lane mode. */\n\telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_RX66_CONTROL, ~(3 << 13));\n\n\telink_warpcore_set_lpi_passthrough(phy, params);\n\n\tif (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {\n\t\t/* SGMII Autoneg */\n\t\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t\t MDIO_WC_REG_COMBO_IEEE0_MIICTRL,\n\t\t\t\t\t 0x1000);\n\t\tPMD_DRV_LOG(DEBUG, \"set SGMII AUTONEG\");\n\t} else {\n\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\tMDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);\n\t\tval16 &= 0xcebf;\n\t\tswitch (phy->req_line_speed) {\n\t\tcase ELINK_SPEED_10:\n\t\t\tbreak;\n\t\tcase ELINK_SPEED_100:\n\t\t\tval16 |= 0x2000;\n\t\t\tbreak;\n\t\tcase ELINK_SPEED_1000:\n\t\t\tval16 |= 0x0040;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"Speed not supported: 0x%x\",\n\t\t\t\t phy->req_line_speed);\n\t\t\treturn;\n\t\t}\n\n\t\tif (phy->req_duplex == DUPLEX_FULL)\n\t\t\tval16 |= 0x0100;\n\n\t\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);\n\n\t\tPMD_DRV_LOG(DEBUG, \"set SGMII force speed %d\",\n\t\t\t phy->req_line_speed);\n\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\tMDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);\n\t\tPMD_DRV_LOG(DEBUG, \" (readback) %x\", val16);\n\t}\n\n\t/* SGMII Slave mode and disable signal detect */\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);\n\tif (fiber_mode)\n\t\tdigctrl_kx1 = 1;\n\telse\n\t\tdigctrl_kx1 &= 0xff4a;\n\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, digctrl_kx1);\n\n\t/* Turn off parallel detect */\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,\n\t\t\t (digctrl_kx2 & ~(1 << 2)));\n\n\t/* Re-enable parallel detect */\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,\n\t\t\t (digctrl_kx2 | (1 << 2)));\n\n\t/* Enable autodet */\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,\n\t\t\t (digctrl_kx1 | 0x10));\n}\n\nstatic void elink_warpcore_reset_lane(struct bnx2x_softc *sc,\n\t\t\t\t struct elink_phy *phy, uint8_t reset)\n{\n\tuint16_t val;\n\t/* Take lane out of reset after configuration is finished */\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_DIGITAL5_MISC6, &val);\n\tif (reset)\n\t\tval |= 0xC000;\n\telse\n\t\tval &= 0x3FFF;\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_DIGITAL5_MISC6, val);\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_DIGITAL5_MISC6, &val);\n}\n\n/* Clear SFI/XFI link settings registers */\nstatic void elink_warpcore_clear_regs(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t uint16_t lane)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t i;\n\tstatic struct elink_reg_set wc_regs[] = {\n\t\t{MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,\n\t\t 0x0195},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,\n\t\t 0x0007},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,\n\t\t 0x0002},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},\n\t\t{MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}\n\t};\n\t/* Set XFI clock comp as default. */\n\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_RX66_CONTROL, (3 << 13));\n\n\tfor (i = 0; i < ARRAY_SIZE(wc_regs); i++)\n\t\telink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,\n\t\t\t\t wc_regs[i].val);\n\n\tlane = elink_get_warpcore_lane(params);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_TX0_TX_DRIVER + 0x10 * lane, 0x0990);\n\n}\n\nstatic elink_status_t elink_get_mod_abs_int_cfg(struct bnx2x_softc *sc,\n\t\t\t\t\t\tuint32_t shmem_base,\n\t\t\t\t\t\tuint8_t port,\n\t\t\t\t\t\tuint8_t * gpio_num,\n\t\t\t\t\t\tuint8_t * gpio_port)\n{\n\tuint32_t cfg_pin;\n\t*gpio_num = 0;\n\t*gpio_port = 0;\n\tif (CHIP_IS_E3(sc)) {\n\t\tcfg_pin = (REG_RD(sc, shmem_base +\n\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t dev_info.port_hw_config[port].\n\t\t\t\t\t e3_sfp_ctrl)) &\n\t\t\t PORT_HW_CFG_E3_MOD_ABS_MASK) >>\n\t\t PORT_HW_CFG_E3_MOD_ABS_SHIFT;\n\n\t\t/* Should not happen. This function called upon interrupt\n\t\t * triggered by GPIO ( since EPIO can only generate interrupts\n\t\t * to MCP).\n\t\t * So if this function was called and none of the GPIOs was set,\n\t\t * it means the shit hit the fan.\n\t\t */\n\t\tif ((cfg_pin < PIN_CFG_GPIO0_P0) ||\n\t\t (cfg_pin > PIN_CFG_GPIO3_P1)) {\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"No cfg pin %x for module detect indication\",\n\t\t\t\t cfg_pin);\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\n\t\t*gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;\n\t\t*gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;\n\t} else {\n\t\t*gpio_num = MISC_REGISTERS_GPIO_3;\n\t\t*gpio_port = port;\n\t}\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic int elink_is_sfp_module_plugged(struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t gpio_num, gpio_port;\n\tuint32_t gpio_val;\n\tif (elink_get_mod_abs_int_cfg(sc,\n\t\t\t\t params->shmem_base, params->port,\n\t\t\t\t &gpio_num, &gpio_port) != ELINK_STATUS_OK)\n\t\treturn 0;\n\tgpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);\n\n\t/* Call the handling function in case module is detected */\n\tif (gpio_val == 0)\n\t\treturn 1;\n\telse\n\t\treturn 0;\n}\n\nstatic int elink_warpcore_get_sigdet(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tuint16_t gp2_status_reg0, lane;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tlane = elink_get_warpcore_lane(params);\n\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,\n\t\t\t&gp2_status_reg0);\n\n\treturn (gp2_status_reg0 >> (8 + lane)) & 0x1;\n}\n\nstatic void elink_warpcore_config_runtime(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t serdes_net_if;\n\tuint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0;\n\n\tvars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;\n\n\tif (!vars->turn_to_run_wc_rt)\n\t\treturn;\n\n\tif (vars->rx_tx_asic_rst) {\n\t\tuint16_t lane = elink_get_warpcore_lane(params);\n\t\tserdes_net_if = (REG_RD(sc, params->shmem_base +\n\t\t\t\t\toffsetof(struct shmem_region,\n\t\t\t\t\t\t dev_info.port_hw_config\n\t\t\t\t\t\t [params->port].\n\t\t\t\t\t\t default_cfg)) &\n\t\t\t\t PORT_HW_CFG_NET_SERDES_IF_MASK);\n\n\t\tswitch (serdes_net_if) {\n\t\tcase PORT_HW_CFG_NET_SERDES_IF_KR:\n\t\t\t/* Do we get link yet? */\n\t\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,\n\t\t\t\t\t&gp_status1);\n\t\t\tlnkup = (gp_status1 >> (8 + lane)) & 0x1;\t/* 1G */\n\t\t\t/*10G KR */\n\t\t\tlnkup_kr = (gp_status1 >> (12 + lane)) & 0x1;\n\n\t\t\tif (lnkup_kr || lnkup) {\n\t\t\t\tvars->rx_tx_asic_rst = 0;\n\t\t\t} else {\n\t\t\t\t/* Reset the lane to see if link comes up. */\n\t\t\t\telink_warpcore_reset_lane(sc, phy, 1);\n\t\t\t\telink_warpcore_reset_lane(sc, phy, 0);\n\n\t\t\t\t/* Restart Autoneg */\n\t\t\t\telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\t\t\t MDIO_WC_REG_IEEE0BLK_MIICNTL,\n\t\t\t\t\t\t 0x1200);\n\n\t\t\t\tvars->rx_tx_asic_rst--;\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"0x%x retry left\",\n\t\t\t\t\t vars->rx_tx_asic_rst);\n\t\t\t}\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t}\n\t/*params->rx_tx_asic_rst */\n}\n\nstatic void elink_warpcore_config_sfi(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tuint16_t lane = elink_get_warpcore_lane(params);\n\n\telink_warpcore_clear_regs(phy, params, lane);\n\tif ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==\n\t ELINK_SPEED_10000) &&\n\t (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {\n\t\tPMD_DRV_LOG(DEBUG, \"Setting 10G SFI\");\n\t\telink_warpcore_set_10G_XFI(phy, params, 0);\n\t} else {\n\t\tPMD_DRV_LOG(DEBUG, \"Setting 1G Fiber\");\n\t\telink_warpcore_set_sgmii_speed(phy, params, 1, 0);\n\t}\n}\n\nstatic void elink_sfp_e3_set_transmitter(struct elink_params *params,\n\t\t\t\t\t struct elink_phy *phy, uint8_t tx_en)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t cfg_pin;\n\tuint8_t port = params->port;\n\n\tcfg_pin = REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_hw_config[port].e3_sfp_ctrl)) &\n\t PORT_HW_CFG_E3_TX_LASER_MASK;\n\t/* Set the !tx_en since this pin is DISABLE_TX_LASER */\n\tPMD_DRV_LOG(DEBUG, \"Setting WC TX to %d\", tx_en);\n\n\t/* For 20G, the expected pin to be used is 3 pins after the current */\n\telink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);\n\tif (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)\n\t\telink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);\n}\n\nstatic void elink_warpcore_config_init(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t serdes_net_if;\n\tuint8_t fiber_mode;\n\tuint16_t lane = elink_get_warpcore_lane(params);\n\tserdes_net_if = (REG_RD(sc, params->shmem_base +\n\t\t\t\toffsetof(struct shmem_region,\n\t\t\t\t\t dev_info.port_hw_config[params->port].\n\t\t\t\t\t default_cfg)) &\n\t\t\t PORT_HW_CFG_NET_SERDES_IF_MASK);\n\tPMD_DRV_LOG(DEBUG,\n\t\t \"Begin Warpcore init, link_speed %d, \"\n\t\t \"serdes_net_if = 0x%x\", vars->line_speed, serdes_net_if);\n\telink_set_aer_mmd(params, phy);\n\telink_warpcore_reset_lane(sc, phy, 1);\n\tvars->phy_flags |= PHY_XGXS_FLAG;\n\tif ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||\n\t (phy->req_line_speed &&\n\t ((phy->req_line_speed == ELINK_SPEED_100) ||\n\t (phy->req_line_speed == ELINK_SPEED_10)))) {\n\t\tvars->phy_flags |= PHY_SGMII_FLAG;\n\t\tPMD_DRV_LOG(DEBUG, \"Setting SGMII mode\");\n\t\telink_warpcore_clear_regs(phy, params, lane);\n\t\telink_warpcore_set_sgmii_speed(phy, params, 0, 1);\n\t} else {\n\t\tswitch (serdes_net_if) {\n\t\tcase PORT_HW_CFG_NET_SERDES_IF_KR:\n\t\t\t/* Enable KR Auto Neg */\n\t\t\tif (params->loopback_mode != ELINK_LOOPBACK_EXT)\n\t\t\t\telink_warpcore_enable_AN_KR(phy, params, vars);\n\t\t\telse {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Setting KR 10G-Force\");\n\t\t\t\telink_warpcore_set_10G_KR(phy, params);\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase PORT_HW_CFG_NET_SERDES_IF_XFI:\n\t\t\telink_warpcore_clear_regs(phy, params, lane);\n\t\t\tif (vars->line_speed == ELINK_SPEED_10000) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Setting 10G XFI\");\n\t\t\t\telink_warpcore_set_10G_XFI(phy, params, 1);\n\t\t\t} else {\n\t\t\t\tif (ELINK_SINGLE_MEDIA_DIRECT(params)) {\n\t\t\t\t\tPMD_DRV_LOG(DEBUG, \"1G Fiber\");\n\t\t\t\t\tfiber_mode = 1;\n\t\t\t\t} else {\n\t\t\t\t\tPMD_DRV_LOG(DEBUG, \"10/100/1G SGMII\");\n\t\t\t\t\tfiber_mode = 0;\n\t\t\t\t}\n\t\t\t\telink_warpcore_set_sgmii_speed(phy,\n\t\t\t\t\t\t\t params,\n\t\t\t\t\t\t\t fiber_mode, 0);\n\t\t\t}\n\n\t\t\tbreak;\n\n\t\tcase PORT_HW_CFG_NET_SERDES_IF_SFI:\n\t\t\t/* Issue Module detection if module is plugged, or\n\t\t\t * enabled transmitter to avoid current leakage in case\n\t\t\t * no module is connected\n\t\t\t */\n\t\t\tif ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||\n\t\t\t (params->loopback_mode == ELINK_LOOPBACK_EXT)) {\n\t\t\t\tif (elink_is_sfp_module_plugged(params))\n\t\t\t\t\telink_sfp_module_detection(phy, params);\n\t\t\t\telse\n\t\t\t\t\telink_sfp_e3_set_transmitter(params,\n\t\t\t\t\t\t\t\t phy, 1);\n\t\t\t}\n\n\t\t\telink_warpcore_config_sfi(phy, params);\n\t\t\tbreak;\n\n\t\tcase PORT_HW_CFG_NET_SERDES_IF_DXGXS:\n\t\t\tif (vars->line_speed != ELINK_SPEED_20000) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Speed not supported yet\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tPMD_DRV_LOG(DEBUG, \"Setting 20G DXGXS\");\n\t\t\telink_warpcore_set_20G_DXGXS(sc, phy, lane);\n\t\t\t/* Issue Module detection */\n\n\t\t\telink_sfp_module_detection(phy, params);\n\t\t\tbreak;\n\t\tcase PORT_HW_CFG_NET_SERDES_IF_KR2:\n\t\t\tif (!params->loopback_mode) {\n\t\t\t\telink_warpcore_enable_AN_KR(phy, params, vars);\n\t\t\t} else {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Setting KR 20G-Force\");\n\t\t\t\telink_warpcore_set_20G_force_KR2(phy, params);\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"Unsupported Serdes Net Interface 0x%x\",\n\t\t\t\t serdes_net_if);\n\t\t\treturn;\n\t\t}\n\t}\n\n\t/* Take lane out of reset after configuration is finished */\n\telink_warpcore_reset_lane(sc, phy, 0);\n\tPMD_DRV_LOG(DEBUG, \"Exit config init\");\n}\n\nstatic void elink_warpcore_link_reset(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val16, lane;\n\telink_sfp_e3_set_transmitter(params, phy, 0);\n\telink_set_mdio_emac_per_phy(sc, params);\n\telink_set_aer_mmd(params, phy);\n\t/* Global register */\n\telink_warpcore_reset_lane(sc, phy, 1);\n\n\t/* Clear loopback settings (if any) */\n\t/* 10G & 20G */\n\telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);\n\n\telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);\n\n\t/* Update those 1-copy registers */\n\tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n\t\t\t MDIO_AER_BLOCK_AER_REG, 0);\n\t/* Enable 1G MDIO (1-copy) */\n\telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~0x10);\n\n\telink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);\n\tlane = elink_get_warpcore_lane(params);\n\t/* Disable CL36 PCS Tx */\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);\n\tval16 |= (0x11 << lane);\n\tif (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)\n\t\tval16 |= (0x22 << lane);\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);\n\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);\n\tval16 &= ~(0x0303 << (lane << 1));\n\tval16 |= (0x0101 << (lane << 1));\n\tif (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {\n\t\tval16 &= ~(0x0c0c << (lane << 1));\n\t\tval16 |= (0x0404 << (lane << 1));\n\t}\n\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);\n\t/* Restore AER */\n\telink_set_aer_mmd(params, phy);\n\n}\n\nstatic void elink_set_warpcore_loopback(struct elink_phy *phy,\n\t\t\t\t\tstruct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val16;\n\tuint32_t lane;\n\tPMD_DRV_LOG(DEBUG, \"Setting Warpcore loopback type %x, speed %d\",\n\t\t params->loopback_mode, phy->req_line_speed);\n\n\tif (phy->req_line_speed < ELINK_SPEED_10000 ||\n\t phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {\n\t\t/* 10/100/1000/20G-KR2 */\n\n\t\t/* Update those 1-copy registers */\n\t\tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n\t\t\t\t MDIO_AER_BLOCK_AER_REG, 0);\n\t\t/* Enable 1G MDIO (1-copy) */\n\t\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t\t MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,\n\t\t\t\t\t 0x10);\n\t\t/* Set 1G loopback based on lane (1-copy) */\n\t\tlane = elink_get_warpcore_lane(params);\n\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\tMDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);\n\t\tval16 |= (1 << lane);\n\t\tif (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)\n\t\t\tval16 |= (2 << lane);\n\t\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t MDIO_WC_REG_XGXSBLK1_LANECTRL2, val16);\n\n\t\t/* Switch back to 4-copy registers */\n\t\telink_set_aer_mmd(params, phy);\n\t} else {\n\t\t/* 10G / 20G-DXGXS */\n\t\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t\t MDIO_WC_REG_COMBO_IEEE0_MIICTRL,\n\t\t\t\t\t 0x4000);\n\t\telink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t\t MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);\n\t}\n}\n\nstatic void elink_sync_link(struct elink_params *params,\n\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t link_10g_plus;\n\tif (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)\n\t\tvars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;\n\tvars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);\n\tif (vars->link_up) {\n\t\tPMD_DRV_LOG(DEBUG, \"phy link up\");\n\n\t\tvars->phy_link_up = 1;\n\t\tvars->duplex = DUPLEX_FULL;\n\t\tswitch (vars->link_status & LINK_STATUS_SPEED_AND_DUPLEX_MASK) {\n\t\tcase ELINK_LINK_10THD:\n\t\t\tvars->duplex = DUPLEX_HALF;\n\t\t\t/* Fall thru */\n\t\tcase ELINK_LINK_10TFD:\n\t\t\tvars->line_speed = ELINK_SPEED_10;\n\t\t\tbreak;\n\n\t\tcase ELINK_LINK_100TXHD:\n\t\t\tvars->duplex = DUPLEX_HALF;\n\t\t\t/* Fall thru */\n\t\tcase ELINK_LINK_100T4:\n\t\tcase ELINK_LINK_100TXFD:\n\t\t\tvars->line_speed = ELINK_SPEED_100;\n\t\t\tbreak;\n\n\t\tcase ELINK_LINK_1000THD:\n\t\t\tvars->duplex = DUPLEX_HALF;\n\t\t\t/* Fall thru */\n\t\tcase ELINK_LINK_1000TFD:\n\t\t\tvars->line_speed = ELINK_SPEED_1000;\n\t\t\tbreak;\n\n\t\tcase ELINK_LINK_2500THD:\n\t\t\tvars->duplex = DUPLEX_HALF;\n\t\t\t/* Fall thru */\n\t\tcase ELINK_LINK_2500TFD:\n\t\t\tvars->line_speed = ELINK_SPEED_2500;\n\t\t\tbreak;\n\n\t\tcase ELINK_LINK_10GTFD:\n\t\t\tvars->line_speed = ELINK_SPEED_10000;\n\t\t\tbreak;\n\t\tcase ELINK_LINK_20GTFD:\n\t\t\tvars->line_speed = ELINK_SPEED_20000;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\tvars->flow_ctrl = 0;\n\t\tif (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)\n\t\t\tvars->flow_ctrl |= ELINK_FLOW_CTRL_TX;\n\n\t\tif (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)\n\t\t\tvars->flow_ctrl |= ELINK_FLOW_CTRL_RX;\n\n\t\tif (!vars->flow_ctrl)\n\t\t\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\n\t\tif (vars->line_speed &&\n\t\t ((vars->line_speed == ELINK_SPEED_10) ||\n\t\t (vars->line_speed == ELINK_SPEED_100))) {\n\t\t\tvars->phy_flags |= PHY_SGMII_FLAG;\n\t\t} else {\n\t\t\tvars->phy_flags &= ~PHY_SGMII_FLAG;\n\t\t}\n\t\tif (vars->line_speed &&\n\t\t USES_WARPCORE(sc) && (vars->line_speed == ELINK_SPEED_1000))\n\t\t\tvars->phy_flags |= PHY_SGMII_FLAG;\n\t\t/* Anything 10 and over uses the bmac */\n\t\tlink_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);\n\n\t\tif (link_10g_plus) {\n\t\t\tif (USES_WARPCORE(sc))\n\t\t\t\tvars->mac_type = ELINK_MAC_TYPE_XMAC;\n\t\t\telse\n\t\t\t\tvars->mac_type = ELINK_MAC_TYPE_BMAC;\n\t\t} else {\n\t\t\tif (USES_WARPCORE(sc))\n\t\t\t\tvars->mac_type = ELINK_MAC_TYPE_UMAC;\n\t\t\telse\n\t\t\t\tvars->mac_type = ELINK_MAC_TYPE_EMAC;\n\t\t}\n\t} else {\t\t/* Link down */\n\t\tPMD_DRV_LOG(DEBUG, \"phy link down\");\n\n\t\tvars->phy_link_up = 0;\n\n\t\tvars->line_speed = 0;\n\t\tvars->duplex = DUPLEX_FULL;\n\t\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\n\t\t/* Indicate no mac active */\n\t\tvars->mac_type = ELINK_MAC_TYPE_NONE;\n\t\tif (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)\n\t\t\tvars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;\n\t\tif (vars->link_status & LINK_STATUS_SFP_TX_FAULT)\n\t\t\tvars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;\n\t}\n}\n\nvoid elink_link_status_update(struct elink_params *params,\n\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port = params->port;\n\tuint32_t sync_offset, media_types;\n\t/* Update PHY configuration */\n\tset_phy_vars(params, vars);\n\n\tvars->link_status = REG_RD(sc, params->shmem_base +\n\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t port_mb[port].link_status));\n\n\t/* Force link UP in non LOOPBACK_EXT loopback mode(s) */\n\tif (params->loopback_mode != ELINK_LOOPBACK_NONE &&\n\t params->loopback_mode != ELINK_LOOPBACK_EXT)\n\t\tvars->link_status |= LINK_STATUS_LINK_UP;\n\n\tif (elink_eee_has_cap(params))\n\t\tvars->eee_status = REG_RD(sc, params->shmem2_base +\n\t\t\t\t\t offsetof(struct shmem2_region,\n\t\t\t\t\t\t eee_status[params->port]));\n\n\tvars->phy_flags = PHY_XGXS_FLAG;\n\telink_sync_link(params, vars);\n\t/* Sync media type */\n\tsync_offset = params->shmem_base +\n\t offsetof(struct shmem_region,\n\t\t dev_info.port_hw_config[port].media_type);\n\tmedia_types = REG_RD(sc, sync_offset);\n\n\tparams->phy[ELINK_INT_PHY].media_type =\n\t (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>\n\t PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;\n\tparams->phy[ELINK_EXT_PHY1].media_type =\n\t (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>\n\t PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;\n\tparams->phy[ELINK_EXT_PHY2].media_type =\n\t (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>\n\t PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;\n\tPMD_DRV_LOG(DEBUG, \"media_types = 0x%x\", media_types);\n\n\t/* Sync AEU offset */\n\tsync_offset = params->shmem_base +\n\t offsetof(struct shmem_region,\n\t\t dev_info.port_hw_config[port].aeu_int_mask);\n\n\tvars->aeu_int_mask = REG_RD(sc, sync_offset);\n\n\t/* Sync PFC status */\n\tif (vars->link_status & LINK_STATUS_PFC_ENABLED)\n\t\tparams->feature_config_flags |=\n\t\t ELINK_FEATURE_CONFIG_PFC_ENABLED;\n\telse\n\t\tparams->feature_config_flags &=\n\t\t ~ELINK_FEATURE_CONFIG_PFC_ENABLED;\n\n\tif (SHMEM2_HAS(sc, link_attr_sync))\n\t\tvars->link_attr_sync = SHMEM2_RD(sc,\n\t\t\t\t\t\t link_attr_sync[params->port]);\n\n\tPMD_DRV_LOG(DEBUG, \"link_status 0x%x phy_link_up %x int_mask 0x%x\",\n\t\t vars->link_status, vars->phy_link_up, vars->aeu_int_mask);\n\tPMD_DRV_LOG(DEBUG, \"line_speed %x duplex %x flow_ctrl 0x%x\",\n\t\t vars->line_speed, vars->duplex, vars->flow_ctrl);\n}\n\nstatic void elink_set_master_ln(struct elink_params *params,\n\t\t\t\tstruct elink_phy *phy)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t new_master_ln, ser_lane;\n\tser_lane = ((params->lane_config &\n\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>\n\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);\n\n\t/* Set the master_ln for AN */\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_XGXS_BLOCK2,\n\t\t\t MDIO_XGXS_BLOCK2_TEST_MODE_LANE, &new_master_ln);\n\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_XGXS_BLOCK2,\n\t\t\t MDIO_XGXS_BLOCK2_TEST_MODE_LANE,\n\t\t\t (new_master_ln | ser_lane));\n}\n\nstatic elink_status_t elink_reset_unicore(struct elink_params *params,\n\t\t\t\t\t struct elink_phy *phy,\n\t\t\t\t\t uint8_t set_serdes)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t mii_control;\n\tuint16_t i;\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);\n\n\t/* Reset the unicore */\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL,\n\t\t\t (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));\n\tif (set_serdes)\n\t\telink_set_serdes_access(sc, params->port);\n\n\t/* Wait for the reset to self clear */\n\tfor (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {\n\t\tDELAY(5);\n\n\t\t/* The reset erased the previous bank value */\n\t\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);\n\n\t\tif (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {\n\t\t\tDELAY(5);\n\t\t\treturn ELINK_STATUS_OK;\n\t\t}\n\t}\n\n\telink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port);\t// \"Warning: PHY was not initialized,\"\n\t// \" Port %d\",\n\n\tPMD_DRV_LOG(DEBUG, \"BUG! XGXS is still in reset!\");\n\treturn ELINK_STATUS_ERROR;\n\n}\n\nstatic void elink_set_swap_lanes(struct elink_params *params,\n\t\t\t\t struct elink_phy *phy)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\t/* Each two bits represents a lane number:\n\t * No swap is 0123 => 0x1b no need to enable the swap\n\t */\n\tuint16_t rx_lane_swap, tx_lane_swap;\n\n\trx_lane_swap = ((params->lane_config &\n\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>\n\t\t\tPORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);\n\ttx_lane_swap = ((params->lane_config &\n\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>\n\t\t\tPORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);\n\n\tif (rx_lane_swap != 0x1b) {\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_XGXS_BLOCK2,\n\t\t\t\t MDIO_XGXS_BLOCK2_RX_LN_SWAP,\n\t\t\t\t (rx_lane_swap |\n\t\t\t\t MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |\n\t\t\t\t MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));\n\t} else {\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_XGXS_BLOCK2,\n\t\t\t\t MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);\n\t}\n\n\tif (tx_lane_swap != 0x1b) {\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_XGXS_BLOCK2,\n\t\t\t\t MDIO_XGXS_BLOCK2_TX_LN_SWAP,\n\t\t\t\t (tx_lane_swap |\n\t\t\t\t MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));\n\t} else {\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_XGXS_BLOCK2,\n\t\t\t\t MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);\n\t}\n}\n\nstatic void elink_set_parallel_detection(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t control2;\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, &control2);\n\tif (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)\n\t\tcontrol2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;\n\telse\n\t\tcontrol2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;\n\tPMD_DRV_LOG(DEBUG, \"phy->speed_cap_mask = 0x%x, control2 = 0x%x\",\n\t\t phy->speed_cap_mask, control2);\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, control2);\n\n\tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&\n\t (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {\n\t\tPMD_DRV_LOG(DEBUG, \"XGXS\");\n\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_10G_PARALLEL_DETECT,\n\t\t\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,\n\t\t\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);\n\n\t\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_10G_PARALLEL_DETECT,\n\t\t\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,\n\t\t\t\t &control2);\n\n\t\tcontrol2 |=\n\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;\n\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_10G_PARALLEL_DETECT,\n\t\t\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,\n\t\t\t\t control2);\n\n\t\t/* Disable parallel detection of HiG */\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_XGXS_BLOCK2,\n\t\t\t\t MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,\n\t\t\t\t MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |\n\t\t\t\t MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);\n\t}\n}\n\nstatic void elink_set_autoneg(struct elink_phy *phy,\n\t\t\t struct elink_params *params,\n\t\t\t struct elink_vars *vars, uint8_t enable_cl73)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t reg_val;\n\n\t/* CL37 Autoneg */\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);\n\n\t/* CL37 Autoneg Enabled */\n\tif (vars->line_speed == ELINK_SPEED_AUTO_NEG)\n\t\treg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;\n\telse\t\t\t/* CL37 Autoneg Disabled */\n\t\treg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |\n\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);\n\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);\n\n\t/* Enable/Disable Autodetection */\n\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);\n\treg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |\n\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);\n\treg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;\n\tif (vars->line_speed == ELINK_SPEED_AUTO_NEG)\n\t\treg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;\n\telse\n\t\treg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;\n\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);\n\n\t/* Enable TetonII and BAM autoneg */\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_BAM_NEXT_PAGE,\n\t\t\t MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, ®_val);\n\tif (vars->line_speed == ELINK_SPEED_AUTO_NEG) {\n\t\t/* Enable BAM aneg Mode and TetonII aneg Mode */\n\t\treg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |\n\t\t\t MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);\n\t} else {\n\t\t/* TetonII and BAM Autoneg Disabled */\n\t\treg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |\n\t\t\t MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);\n\t}\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_BAM_NEXT_PAGE,\n\t\t\t MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, reg_val);\n\n\tif (enable_cl73) {\n\t\t/* Enable Cl73 FSM status bits */\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_CL73_USERB0,\n\t\t\t\t MDIO_CL73_USERB0_CL73_UCTRL, 0xe);\n\n\t\t/* Enable BAM Station Manager */\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_CL73_USERB0,\n\t\t\t\t MDIO_CL73_USERB0_CL73_BAM_CTRL1,\n\t\t\t\t MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |\n\t\t\t\t MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN\n\t\t\t\t |\n\t\t\t\t MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);\n\n\t\t/* Advertise CL73 link speeds */\n\t\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_CL73_IEEEB1,\n\t\t\t\t MDIO_CL73_IEEEB1_AN_ADV2, ®_val);\n\t\tif (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)\n\t\t\treg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;\n\t\tif (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)\n\t\t\treg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;\n\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_CL73_IEEEB1,\n\t\t\t\t MDIO_CL73_IEEEB1_AN_ADV2, reg_val);\n\n\t\t/* CL73 Autoneg Enabled */\n\t\treg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;\n\n\t} else\t\t\t/* CL73 Autoneg Disabled */\n\t\treg_val = 0;\n\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_CL73_IEEEB0,\n\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);\n}\n\n/* Program SerDes, forced speed */\nstatic void elink_program_serdes(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t reg_val;\n\n\t/* Program duplex, disable autoneg and sgmii */\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);\n\treg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |\n\t\t MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |\n\t\t MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);\n\tif (phy->req_duplex == DUPLEX_FULL)\n\t\treg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);\n\n\t/* Program speed\n\t * - needed only if the speed is greater than 1G (2.5G or 10G)\n\t */\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n\t\t\t MDIO_SERDES_DIGITAL_MISC1, ®_val);\n\t/* Clearing the speed value before setting the right speed */\n\tPMD_DRV_LOG(DEBUG, \"MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\", reg_val);\n\n\treg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |\n\t\t MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);\n\n\tif (!((vars->line_speed == ELINK_SPEED_1000) ||\n\t (vars->line_speed == ELINK_SPEED_100) ||\n\t (vars->line_speed == ELINK_SPEED_10))) {\n\n\t\treg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |\n\t\t\t MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);\n\t\tif (vars->line_speed == ELINK_SPEED_10000)\n\t\t\treg_val |=\n\t\t\t MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;\n\t}\n\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n\t\t\t MDIO_SERDES_DIGITAL_MISC1, reg_val);\n\n}\n\nstatic void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val = 0;\n\n\t/* Set extended capabilities */\n\tif (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)\n\t\tval |= MDIO_OVER_1G_UP1_2_5G;\n\tif (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)\n\t\tval |= MDIO_OVER_1G_UP1_10G;\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP1, val);\n\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_UP3, 0x400);\n}\n\nstatic void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t uint16_t ieee_fc)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val;\n\t/* For AN, we are always publishing full duplex */\n\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_CL73_IEEEB1,\n\t\t\t MDIO_CL73_IEEEB1_AN_ADV1, &val);\n\tval &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;\n\tval |= ((ieee_fc << 3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_CL73_IEEEB1,\n\t\t\t MDIO_CL73_IEEEB1_AN_ADV1, val);\n}\n\nstatic void elink_restart_autoneg(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t uint8_t enable_cl73)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t mii_control;\n\n\tPMD_DRV_LOG(DEBUG, \"elink_restart_autoneg\");\n\t/* Enable and restart BAM/CL37 aneg */\n\n\tif (enable_cl73) {\n\t\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_CL73_IEEEB0,\n\t\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL,\n\t\t\t\t &mii_control);\n\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_CL73_IEEEB0,\n\t\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL,\n\t\t\t\t (mii_control |\n\t\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |\n\t\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));\n\t} else {\n\n\t\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t \"elink_restart_autoneg mii_control before = 0x%x\",\n\t\t\t mii_control);\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL,\n\t\t\t\t (mii_control |\n\t\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |\n\t\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));\n\t}\n}\n\nstatic void elink_initialize_sgmii_process(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t control1;\n\n\t/* In SGMII mode, the unicore is always slave */\n\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &control1);\n\tcontrol1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;\n\t/* Set sgmii mode (and not fiber) */\n\tcontrol1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |\n\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |\n\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n\t\t\t MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, control1);\n\n\t/* If forced speed */\n\tif (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {\n\t\t/* Set speed, disable autoneg */\n\t\tuint16_t mii_control;\n\n\t\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);\n\t\tmii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |\n\t\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |\n\t\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);\n\n\t\tswitch (vars->line_speed) {\n\t\tcase ELINK_SPEED_100:\n\t\t\tmii_control |=\n\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;\n\t\t\tbreak;\n\t\tcase ELINK_SPEED_1000:\n\t\t\tmii_control |=\n\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;\n\t\t\tbreak;\n\t\tcase ELINK_SPEED_10:\n\t\t\t/* There is nothing to set for 10M */\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* Invalid speed for SGMII */\n\t\t\tPMD_DRV_LOG(DEBUG, \"Invalid line_speed 0x%x\",\n\t\t\t\t vars->line_speed);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Setting the full duplex */\n\t\tif (phy->req_duplex == DUPLEX_FULL)\n\t\t\tmii_control |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t\t MDIO_COMBO_IEEE0_MII_CONTROL, mii_control);\n\n\t} else {\t\t/* AN mode */\n\t\t/* Enable and restart AN */\n\t\telink_restart_autoneg(phy, params, 0);\n\t}\n}\n\n/* Link management\n */\nstatic elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,\n\t\t\t\t\t\t\tstruct elink_params\n\t\t\t\t\t\t\t*params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t pd_10g, status2_1000x;\n\tif (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)\n\t\treturn ELINK_STATUS_OK;\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n\t\t\t MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_SERDES_DIGITAL,\n\t\t\t MDIO_SERDES_DIGITAL_A_1000X_STATUS2, &status2_1000x);\n\tif (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {\n\t\tPMD_DRV_LOG(DEBUG, \"1G parallel detect link on port %d\",\n\t\t\t params->port);\n\t\treturn 1;\n\t}\n\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_10G_PARALLEL_DETECT,\n\t\t\t MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, &pd_10g);\n\n\tif (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {\n\t\tPMD_DRV_LOG(DEBUG, \"10G parallel detect link on port %d\",\n\t\t\t params->port);\n\t\treturn 1;\n\t}\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_update_adv_fc(struct elink_phy *phy,\n\t\t\t\tstruct elink_params *params,\n\t\t\t\tstruct elink_vars *vars, uint32_t gp_status)\n{\n\tuint16_t ld_pause;\t/* local driver */\n\tuint16_t lp_pause;\t/* link partner */\n\tuint16_t pause_result;\n\tstruct bnx2x_softc *sc = params->sc;\n\tif ((gp_status &\n\t (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |\n\t MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==\n\t (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |\n\t MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {\n\n\t\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_CL73_IEEEB1,\n\t\t\t\t MDIO_CL73_IEEEB1_AN_ADV1, &ld_pause);\n\t\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_CL73_IEEEB1,\n\t\t\t\t MDIO_CL73_IEEEB1_AN_LP_ADV1, &lp_pause);\n\t\tpause_result = (ld_pause &\n\t\t\t\tMDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;\n\t\tpause_result |= (lp_pause &\n\t\t\t\t MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;\n\t\tPMD_DRV_LOG(DEBUG, \"pause_result CL73 0x%x\", pause_result);\n\t} else {\n\t\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV, &ld_pause);\n\t\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_COMBO_IEEE0,\n\t\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,\n\t\t\t\t &lp_pause);\n\t\tpause_result = (ld_pause &\n\t\t\t\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 5;\n\t\tpause_result |= (lp_pause &\n\t\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) >> 7;\n\t\tPMD_DRV_LOG(DEBUG, \"pause_result CL37 0x%x\", pause_result);\n\t}\n\telink_pause_resolve(vars, pause_result);\n\n}\n\nstatic void elink_flow_ctrl_resolve(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars, uint32_t gp_status)\n{\n\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\n\t/* Resolve from gp_status in case of AN complete and not sgmii */\n\tif (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {\n\t\t/* Update the advertised flow-controled of LD/LP in AN */\n\t\tif (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)\n\t\t\telink_update_adv_fc(phy, params, vars, gp_status);\n\t\t/* But set the flow-control result as the requested one */\n\t\tvars->flow_ctrl = phy->req_flow_ctrl;\n\t} else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)\n\t\tvars->flow_ctrl = params->req_fc_auto_adv;\n\telse if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) &&\n\t\t (!(vars->phy_flags & PHY_SGMII_FLAG))) {\n\t\tif (elink_direct_parallel_detect_used(phy, params)) {\n\t\t\tvars->flow_ctrl = params->req_fc_auto_adv;\n\t\t\treturn;\n\t\t}\n\t\telink_update_adv_fc(phy, params, vars, gp_status);\n\t}\n\tPMD_DRV_LOG(DEBUG, \"flow_ctrl 0x%x\", vars->flow_ctrl);\n}\n\nstatic void elink_check_fallback_to_cl37(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t rx_status, ustat_val, cl37_fsm_received;\n\tPMD_DRV_LOG(DEBUG, \"elink_check_fallback_to_cl37\");\n\t/* Step 1: Make sure signal is detected */\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_RX0, MDIO_RX0_RX_STATUS, &rx_status);\n\tif ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=\n\t (MDIO_RX0_RX_STATUS_SIGDET)) {\n\t\tPMD_DRV_LOG(DEBUG, \"Signal is not detected. Restoring CL73.\"\n\t\t\t \"rx_status(0x80b0) = 0x%x\", rx_status);\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t MDIO_REG_BANK_CL73_IEEEB0,\n\t\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL,\n\t\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);\n\t\treturn;\n\t}\n\t/* Step 2: Check CL73 state machine */\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_CL73_USERB0,\n\t\t\t MDIO_CL73_USERB0_CL73_USTAT1, &ustat_val);\n\tif ((ustat_val &\n\t (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |\n\t MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=\n\t (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |\n\t MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {\n\t\tPMD_DRV_LOG(DEBUG, \"CL73 state-machine is not stable. \"\n\t\t\t \"ustat_val(0x8371) = 0x%x\", ustat_val);\n\t\treturn;\n\t}\n\t/* Step 3: Check CL37 Message Pages received to indicate LP\n\t * supports only CL37\n\t */\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_REMOTE_PHY,\n\t\t\t MDIO_REMOTE_PHY_MISC_RX_STATUS, &cl37_fsm_received);\n\tif ((cl37_fsm_received &\n\t (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |\n\t MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=\n\t (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |\n\t MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {\n\t\tPMD_DRV_LOG(DEBUG, \"No CL37 FSM were received. \"\n\t\t\t \"misc_rx_status(0x8330) = 0x%x\", cl37_fsm_received);\n\t\treturn;\n\t}\n\t/* The combined cl37/cl73 fsm state information indicating that\n\t * we are connected to a device which does not support cl73, but\n\t * does support cl37 BAM. In this case we disable cl73 and\n\t * restart cl37 auto-neg\n\t */\n\n\t/* Disable CL73 */\n\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_CL73_IEEEB0,\n\t\t\t MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 0);\n\t/* Restart CL37 autoneg */\n\telink_restart_autoneg(phy, params, 0);\n\tPMD_DRV_LOG(DEBUG, \"Disabling CL73, and restarting CL37 autoneg\");\n}\n\nstatic void elink_xgxs_an_resolve(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars, uint32_t gp_status)\n{\n\tif (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)\n\t\tvars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n\n\tif (elink_direct_parallel_detect_used(phy, params))\n\t\tvars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;\n}\n\nstatic elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,\n\t\t\t\t\t\t struct elink_params *params __rte_unused,\n\t\t\t\t\t\t struct elink_vars *vars,\n\t\t\t\t\t\t uint16_t is_link_up,\n\t\t\t\t\t\t uint16_t speed_mask,\n\t\t\t\t\t\t uint16_t is_duplex)\n{\n\tif (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)\n\t\tvars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;\n\tif (is_link_up) {\n\t\tPMD_DRV_LOG(DEBUG, \"phy link up\");\n\n\t\tvars->phy_link_up = 1;\n\t\tvars->link_status |= LINK_STATUS_LINK_UP;\n\n\t\tswitch (speed_mask) {\n\t\tcase ELINK_GP_STATUS_10M:\n\t\t\tvars->line_speed = ELINK_SPEED_10;\n\t\t\tif (is_duplex == DUPLEX_FULL)\n\t\t\t\tvars->link_status |= ELINK_LINK_10TFD;\n\t\t\telse\n\t\t\t\tvars->link_status |= ELINK_LINK_10THD;\n\t\t\tbreak;\n\n\t\tcase ELINK_GP_STATUS_100M:\n\t\t\tvars->line_speed = ELINK_SPEED_100;\n\t\t\tif (is_duplex == DUPLEX_FULL)\n\t\t\t\tvars->link_status |= ELINK_LINK_100TXFD;\n\t\t\telse\n\t\t\t\tvars->link_status |= ELINK_LINK_100TXHD;\n\t\t\tbreak;\n\n\t\tcase ELINK_GP_STATUS_1G:\n\t\tcase ELINK_GP_STATUS_1G_KX:\n\t\t\tvars->line_speed = ELINK_SPEED_1000;\n\t\t\tif (is_duplex == DUPLEX_FULL)\n\t\t\t\tvars->link_status |= ELINK_LINK_1000TFD;\n\t\t\telse\n\t\t\t\tvars->link_status |= ELINK_LINK_1000THD;\n\t\t\tbreak;\n\n\t\tcase ELINK_GP_STATUS_2_5G:\n\t\t\tvars->line_speed = ELINK_SPEED_2500;\n\t\t\tif (is_duplex == DUPLEX_FULL)\n\t\t\t\tvars->link_status |= ELINK_LINK_2500TFD;\n\t\t\telse\n\t\t\t\tvars->link_status |= ELINK_LINK_2500THD;\n\t\t\tbreak;\n\n\t\tcase ELINK_GP_STATUS_5G:\n\t\tcase ELINK_GP_STATUS_6G:\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"link speed unsupported gp_status 0x%x\",\n\t\t\t\t speed_mask);\n\t\t\treturn ELINK_STATUS_ERROR;\n\n\t\tcase ELINK_GP_STATUS_10G_KX4:\n\t\tcase ELINK_GP_STATUS_10G_HIG:\n\t\tcase ELINK_GP_STATUS_10G_CX4:\n\t\tcase ELINK_GP_STATUS_10G_KR:\n\t\tcase ELINK_GP_STATUS_10G_SFI:\n\t\tcase ELINK_GP_STATUS_10G_XFI:\n\t\t\tvars->line_speed = ELINK_SPEED_10000;\n\t\t\tvars->link_status |= ELINK_LINK_10GTFD;\n\t\t\tbreak;\n\t\tcase ELINK_GP_STATUS_20G_DXGXS:\n\t\tcase ELINK_GP_STATUS_20G_KR2:\n\t\t\tvars->line_speed = ELINK_SPEED_20000;\n\t\t\tvars->link_status |= ELINK_LINK_20GTFD;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"link speed unsupported gp_status 0x%x\",\n\t\t\t\t speed_mask);\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t} else {\t\t/* link_down */\n\t\tPMD_DRV_LOG(DEBUG, \"phy link down\");\n\n\t\tvars->phy_link_up = 0;\n\n\t\tvars->duplex = DUPLEX_FULL;\n\t\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\t\tvars->mac_type = ELINK_MAC_TYPE_NONE;\n\t}\n\tPMD_DRV_LOG(DEBUG, \" phy_link_up %x line_speed %d\",\n\t\t vars->phy_link_up, vars->line_speed);\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_link_settings_status(struct elink_phy *phy,\n\t\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tuint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;\n\telink_status_t rc = ELINK_STATUS_OK;\n\n\t/* Read gp_status */\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_GP_STATUS,\n\t\t\t MDIO_GP_STATUS_TOP_AN_STATUS1, &gp_status);\n\tif (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)\n\t\tduplex = DUPLEX_FULL;\n\tif (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)\n\t\tlink_up = 1;\n\tspeed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;\n\tPMD_DRV_LOG(DEBUG, \"gp_status 0x%x, is_link_up %d, speed_mask 0x%x\",\n\t\t gp_status, link_up, speed_mask);\n\trc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,\n\t\t\t\t\t duplex);\n\tif (rc == ELINK_STATUS_ERROR)\n\t\treturn rc;\n\n\tif (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {\n\t\tif (ELINK_SINGLE_MEDIA_DIRECT(params)) {\n\t\t\tvars->duplex = duplex;\n\t\t\telink_flow_ctrl_resolve(phy, params, vars, gp_status);\n\t\t\tif (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)\n\t\t\t\telink_xgxs_an_resolve(phy, params, vars,\n\t\t\t\t\t\t gp_status);\n\t\t}\n\t} else {\t\t/* Link_down */\n\t\tif ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n\t\t ELINK_SINGLE_MEDIA_DIRECT(params)) {\n\t\t\t/* Check signal is detected */\n\t\t\telink_check_fallback_to_cl37(phy, params);\n\t\t}\n\t}\n\n\t/* Read LP advertised speeds */\n\tif (ELINK_SINGLE_MEDIA_DIRECT(params) &&\n\t (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {\n\t\tuint16_t val;\n\n\t\tCL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,\n\t\t\t\t MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);\n\n\t\tif (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n\t\tif (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |\n\t\t\t MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n\n\t\tCL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,\n\t\t\t\t MDIO_OVER_1G_LP_UP1, &val);\n\n\t\tif (val & MDIO_OVER_1G_UP1_2_5G)\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;\n\t\tif (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"duplex %x flow_ctrl 0x%x link_status 0x%x\",\n\t\t vars->duplex, vars->flow_ctrl, vars->link_status);\n\treturn rc;\n}\n\nstatic elink_status_t elink_warpcore_read_status(struct elink_phy *phy,\n\t\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t lane;\n\tuint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;\n\telink_status_t rc = ELINK_STATUS_OK;\n\tlane = elink_get_warpcore_lane(params);\n\t/* Read gp_status */\n\tif ((params->loopback_mode) && (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {\n\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\tMDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);\n\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\tMDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);\n\t\tlink_up &= 0x1;\n\t} else if ((phy->req_line_speed > ELINK_SPEED_10000) &&\n\t\t (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {\n\t\tuint16_t temp_link_up;\n\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &temp_link_up);\n\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD, 1, &link_up);\n\t\tPMD_DRV_LOG(DEBUG, \"PCS RX link status = 0x%x-->0x%x\",\n\t\t\t temp_link_up, link_up);\n\t\tlink_up &= (1 << 2);\n\t\tif (link_up)\n\t\t\telink_ext_phy_resolve_fc(phy, params, vars);\n\t} else {\n\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\tMDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);\n\t\tPMD_DRV_LOG(DEBUG, \"0x81d1 = 0x%x\", gp_status1);\n\t\t/* Check for either KR, 1G, or AN up. */\n\t\tlink_up = ((gp_status1 >> 8) |\n\t\t\t (gp_status1 >> 12) | (gp_status1)) & (1 << lane);\n\t\tif (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {\n\t\t\tuint16_t an_link;\n\t\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\t\tMDIO_AN_REG_STATUS, &an_link);\n\t\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\t\tMDIO_AN_REG_STATUS, &an_link);\n\t\t\tlink_up |= (an_link & (1 << 2));\n\t\t}\n\t\tif (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {\n\t\t\tuint16_t pd, gp_status4;\n\t\t\tif (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {\n\t\t\t\t/* Check Autoneg complete */\n\t\t\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t\t\tMDIO_WC_REG_GP2_STATUS_GP_2_4,\n\t\t\t\t\t\t&gp_status4);\n\t\t\t\tif (gp_status4 & ((1 << 12) << lane))\n\t\t\t\t\tvars->link_status |=\n\t\t\t\t\t LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n\n\t\t\t\t/* Check parallel detect used */\n\t\t\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\t\t\tMDIO_WC_REG_PAR_DET_10G_STATUS,\n\t\t\t\t\t\t&pd);\n\t\t\t\tif (pd & (1 << 15))\n\t\t\t\t\tvars->link_status |=\n\t\t\t\t\t LINK_STATUS_PARALLEL_DETECTION_USED;\n\t\t\t}\n\t\t\telink_ext_phy_resolve_fc(phy, params, vars);\n\t\t\tvars->duplex = duplex;\n\t\t}\n\t}\n\n\tif ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&\n\t ELINK_SINGLE_MEDIA_DIRECT(params)) {\n\t\tuint16_t val;\n\n\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\tMDIO_AN_REG_LP_AUTO_NEG2, &val);\n\n\t\tif (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n\t\tif (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |\n\t\t\t MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n\n\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\tMDIO_WC_REG_DIGITAL3_LP_UP1, &val);\n\n\t\tif (val & MDIO_OVER_1G_UP1_2_5G)\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;\n\t\tif (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n\n\t}\n\n\tif (lane < 2) {\n\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\tMDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);\n\t} else {\n\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\tMDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);\n\t}\n\tPMD_DRV_LOG(DEBUG, \"lane %d gp_speed 0x%x\", lane, gp_speed);\n\n\tif ((lane & 1) == 0)\n\t\tgp_speed <<= 8;\n\tgp_speed &= 0x3f00;\n\tlink_up = ! !link_up;\n\n\t/* Reset the TX FIFO to fix SGMII issue */\n\trc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,\n\t\t\t\t\t duplex);\n\n\t/* In case of KR link down, start up the recovering procedure */\n\tif ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&\n\t (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))\n\t\tvars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;\n\n\tPMD_DRV_LOG(DEBUG, \"duplex %x flow_ctrl 0x%x link_status 0x%x\",\n\t\t vars->duplex, vars->flow_ctrl, vars->link_status);\n\treturn rc;\n}\n\nstatic void elink_set_gmii_tx_driver(struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tstruct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];\n\tuint16_t lp_up2;\n\tuint16_t tx_driver;\n\tuint16_t bank;\n\n\t/* Read precomp */\n\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t MDIO_REG_BANK_OVER_1G, MDIO_OVER_1G_LP_UP2, &lp_up2);\n\n\t/* Bits [10:7] at lp_up2, positioned at [15:12] */\n\tlp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>\n\t\t MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<\n\t\t MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);\n\n\tif (lp_up2 == 0)\n\t\treturn;\n\n\tfor (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;\n\t bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {\n\t\tCL22_RD_OVER_CL45(sc, phy,\n\t\t\t\t bank, MDIO_TX0_TX_DRIVER, &tx_driver);\n\n\t\t/* Replace tx_driver bits [15:12] */\n\t\tif (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {\n\t\t\ttx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;\n\t\t\ttx_driver |= lp_up2;\n\t\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t\t bank, MDIO_TX0_TX_DRIVER, tx_driver);\n\t\t}\n\t}\n}\n\nstatic elink_status_t elink_emac_program(struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port = params->port;\n\tuint16_t mode = 0;\n\n\tPMD_DRV_LOG(DEBUG, \"setting link speed & duplex\");\n\telink_bits_dis(sc, GRCBASE_EMAC0 + port * 0x400 +\n\t\t EMAC_REG_EMAC_MODE,\n\t\t (EMAC_MODE_25G_MODE |\n\t\t\tEMAC_MODE_PORT_MII_10M | EMAC_MODE_HALF_DUPLEX));\n\tswitch (vars->line_speed) {\n\tcase ELINK_SPEED_10:\n\t\tmode |= EMAC_MODE_PORT_MII_10M;\n\t\tbreak;\n\n\tcase ELINK_SPEED_100:\n\t\tmode |= EMAC_MODE_PORT_MII;\n\t\tbreak;\n\n\tcase ELINK_SPEED_1000:\n\t\tmode |= EMAC_MODE_PORT_GMII;\n\t\tbreak;\n\n\tcase ELINK_SPEED_2500:\n\t\tmode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);\n\t\tbreak;\n\n\tdefault:\n\t\t/* 10G not valid for EMAC */\n\t\tPMD_DRV_LOG(DEBUG, \"Invalid line_speed 0x%x\", vars->line_speed);\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\n\tif (vars->duplex == DUPLEX_HALF)\n\t\tmode |= EMAC_MODE_HALF_DUPLEX;\n\telink_bits_en(sc,\n\t\t GRCBASE_EMAC0 + port * 0x400 + EMAC_REG_EMAC_MODE, mode);\n\n\telink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_set_preemphasis(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\n\tuint16_t bank, i = 0;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tfor (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;\n\t bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0), i++) {\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t bank,\n\t\t\t\t MDIO_RX0_RX_EQ_BOOST, phy->rx_preemphasis[i]);\n\t}\n\n\tfor (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;\n\t bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {\n\t\tCL22_WR_OVER_CL45(sc, phy,\n\t\t\t\t bank,\n\t\t\t\t MDIO_TX0_TX_DRIVER, phy->tx_preemphasis[i]);\n\t}\n}\n\nstatic void elink_xgxs_config_init(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tuint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||\n\t\t\t (params->loopback_mode == ELINK_LOOPBACK_XGXS));\n\n\tif (!(vars->phy_flags & PHY_SGMII_FLAG)) {\n\t\tif (ELINK_SINGLE_MEDIA_DIRECT(params) &&\n\t\t (params->feature_config_flags &\n\t\t ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))\n\t\t\telink_set_preemphasis(phy, params);\n\n\t\t/* Forced speed requested? */\n\t\tif (vars->line_speed != ELINK_SPEED_AUTO_NEG ||\n\t\t (ELINK_SINGLE_MEDIA_DIRECT(params) &&\n\t\t params->loopback_mode == ELINK_LOOPBACK_EXT)) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"not SGMII, no AN\");\n\n\t\t\t/* Disable autoneg */\n\t\t\telink_set_autoneg(phy, params, vars, 0);\n\n\t\t\t/* Program speed and duplex */\n\t\t\telink_program_serdes(phy, params, vars);\n\n\t\t} else {\t/* AN_mode */\n\t\t\tPMD_DRV_LOG(DEBUG, \"not SGMII, AN\");\n\n\t\t\t/* AN enabled */\n\t\t\telink_set_brcm_cl37_advertisement(phy, params);\n\n\t\t\t/* Program duplex & pause advertisement (for aneg) */\n\t\t\telink_set_ieee_aneg_advertisement(phy, params,\n\t\t\t\t\t\t\t vars->ieee_fc);\n\n\t\t\t/* Enable autoneg */\n\t\t\telink_set_autoneg(phy, params, vars, enable_cl73);\n\n\t\t\t/* Enable and restart AN */\n\t\t\telink_restart_autoneg(phy, params, enable_cl73);\n\t\t}\n\n\t} else {\t\t/* SGMII mode */\n\t\tPMD_DRV_LOG(DEBUG, \"SGMII\");\n\n\t\telink_initialize_sgmii_process(phy, params, vars);\n\t}\n}\n\nstatic elink_status_t elink_prepare_xgxs(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\telink_status_t rc;\n\tvars->phy_flags |= PHY_XGXS_FLAG;\n\tif ((phy->req_line_speed &&\n\t ((phy->req_line_speed == ELINK_SPEED_100) ||\n\t (phy->req_line_speed == ELINK_SPEED_10))) ||\n\t (!phy->req_line_speed &&\n\t (phy->speed_cap_mask >=\n\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&\n\t (phy->speed_cap_mask <\n\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||\n\t (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))\n\t\tvars->phy_flags |= PHY_SGMII_FLAG;\n\telse\n\t\tvars->phy_flags &= ~PHY_SGMII_FLAG;\n\n\telink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);\n\telink_set_aer_mmd(params, phy);\n\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)\n\t\telink_set_master_ln(params, phy);\n\n\trc = elink_reset_unicore(params, phy, 0);\n\t/* Reset the SerDes and wait for reset bit return low */\n\tif (rc != ELINK_STATUS_OK)\n\t\treturn rc;\n\n\telink_set_aer_mmd(params, phy);\n\t/* Setting the masterLn_def again after the reset */\n\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {\n\t\telink_set_master_ln(params, phy);\n\t\telink_set_swap_lanes(params, phy);\n\t}\n\n\treturn rc;\n}\n\nstatic uint16_t elink_wait_reset_complete(struct bnx2x_softc *sc,\n\t\t\t\t\t struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params)\n{\n\tuint16_t cnt, ctrl;\n\t/* Wait for soft reset to get cleared up to 1 sec */\n\tfor (cnt = 0; cnt < 1000; cnt++) {\n\t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)\n\t\t\telink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &ctrl);\n\t\telse\n\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\t\tMDIO_PMA_REG_CTRL, &ctrl);\n\t\tif (!(ctrl & (1 << 15)))\n\t\t\tbreak;\n\t\tDELAY(1000 * 1);\n\t}\n\n\tif (cnt == 1000)\n\t\telink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port);\t// \"Warning: PHY was not initialized,\"\n\t// \" Port %d\",\n\n\tPMD_DRV_LOG(DEBUG, \"control reg 0x%x (after %d ms)\", ctrl, cnt);\n\treturn cnt;\n}\n\nstatic void elink_link_int_enable(struct elink_params *params)\n{\n\tuint8_t port = params->port;\n\tuint32_t mask;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\t/* Setting the status to report on link up for either XGXS or SerDes */\n\tif (CHIP_IS_E3(sc)) {\n\t\tmask = ELINK_NIG_MASK_XGXS0_LINK_STATUS;\n\t\tif (!(ELINK_SINGLE_MEDIA_DIRECT(params)))\n\t\t\tmask |= ELINK_NIG_MASK_MI_INT;\n\t} else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {\n\t\tmask = (ELINK_NIG_MASK_XGXS0_LINK10G |\n\t\t\tELINK_NIG_MASK_XGXS0_LINK_STATUS);\n\t\tPMD_DRV_LOG(DEBUG, \"enabled XGXS interrupt\");\n\t\tif (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&\n\t\t params->phy[ELINK_INT_PHY].type !=\n\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {\n\t\t\tmask |= ELINK_NIG_MASK_MI_INT;\n\t\t\tPMD_DRV_LOG(DEBUG, \"enabled external phy int\");\n\t\t}\n\n\t} else {\t\t/* SerDes */\n\t\tmask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;\n\t\tPMD_DRV_LOG(DEBUG, \"enabled SerDes interrupt\");\n\t\tif (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&\n\t\t params->phy[ELINK_INT_PHY].type !=\n\t\t PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {\n\t\t\tmask |= ELINK_NIG_MASK_MI_INT;\n\t\t\tPMD_DRV_LOG(DEBUG, \"enabled external phy int\");\n\t\t}\n\t}\n\telink_bits_en(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, mask);\n\n\tPMD_DRV_LOG(DEBUG, \"port %x, is_xgxs %x, int_status 0x%x\", port,\n\t\t (params->switch_cfg == ELINK_SWITCH_CFG_10G),\n\t\t REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));\n\tPMD_DRV_LOG(DEBUG, \" int_mask 0x%x, MI_INT %x, SERDES_LINK %x\",\n\t\t REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),\n\t\t REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port * 0x18),\n\t\t REG_RD(sc,\n\t\t\t NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));\n\tPMD_DRV_LOG(DEBUG, \" 10G %x, XGXS_LINK %x\",\n\t\t REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),\n\t\t REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));\n}\n\nstatic void elink_rearm_latch_signal(struct bnx2x_softc *sc, uint8_t port,\n\t\t\t\t uint8_t exp_mi_int)\n{\n\tuint32_t latch_status = 0;\n\n\t/* Disable the MI INT ( external phy int ) by writing 1 to the\n\t * status register. Link down indication is high-active-signal,\n\t * so in this case we need to write the status to clear the XOR\n\t */\n\t/* Read Latched signals */\n\tlatch_status = REG_RD(sc, NIG_REG_LATCH_STATUS_0 + port * 8);\n\tPMD_DRV_LOG(DEBUG, \"latch_status = 0x%x\", latch_status);\n\t/* Handle only those with latched-signal=up. */\n\tif (exp_mi_int)\n\t\telink_bits_en(sc,\n\t\t\t NIG_REG_STATUS_INTERRUPT_PORT0\n\t\t\t + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);\n\telse\n\t\telink_bits_dis(sc,\n\t\t\t NIG_REG_STATUS_INTERRUPT_PORT0\n\t\t\t + port * 4, ELINK_NIG_STATUS_EMAC0_MI_INT);\n\n\tif (latch_status & 1) {\n\n\t\t/* For all latched-signal=up : Re-Arm Latch signals */\n\t\tREG_WR(sc, NIG_REG_LATCH_STATUS_0 + port * 8,\n\t\t (latch_status & 0xfffe) | (latch_status & 1));\n\t}\n\t/* For all latched-signal=up,Write original_signal to status */\n}\n\nstatic void elink_link_int_ack(struct elink_params *params,\n\t\t\t struct elink_vars *vars, uint8_t is_10g_plus)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port = params->port;\n\tuint32_t mask;\n\t/* First reset all status we assume only one line will be\n\t * change at a time\n\t */\n\telink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4,\n\t\t (ELINK_NIG_STATUS_XGXS0_LINK10G |\n\t\t\tELINK_NIG_STATUS_XGXS0_LINK_STATUS |\n\t\t\tELINK_NIG_STATUS_SERDES0_LINK_STATUS));\n\tif (vars->phy_link_up) {\n\t\tif (USES_WARPCORE(sc))\n\t\t\tmask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS;\n\t\telse {\n\t\t\tif (is_10g_plus)\n\t\t\t\tmask = ELINK_NIG_STATUS_XGXS0_LINK10G;\n\t\t\telse if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {\n\t\t\t\t/* Disable the link interrupt by writing 1 to\n\t\t\t\t * the relevant lane in the status register\n\t\t\t\t */\n\t\t\t\tuint32_t ser_lane =\n\t\t\t\t ((params->lane_config &\n\t\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>\n\t\t\t\t PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);\n\t\t\t\tmask = ((1 << ser_lane) <<\n\t\t\t\t\tELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);\n\t\t\t} else\n\t\t\t\tmask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;\n\t\t}\n\t\tPMD_DRV_LOG(DEBUG, \"Ack link up interrupt with mask 0x%x\",\n\t\t\t mask);\n\t\telink_bits_en(sc,\n\t\t\t NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4, mask);\n\t}\n}\n\nstatic elink_status_t elink_format_ver(uint32_t num, uint8_t * str,\n\t\t\t\t uint16_t * len)\n{\n\tuint8_t *str_ptr = str;\n\tuint32_t mask = 0xf0000000;\n\tuint8_t shift = 8 * 4;\n\tuint8_t digit;\n\tuint8_t remove_leading_zeros = 1;\n\tif (*len < 10) {\n\t\t/* Need more than 10chars for this format */\n\t\t*str_ptr = '\\0';\n\t\t(*len)--;\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\twhile (shift > 0) {\n\n\t\tshift -= 4;\n\t\tdigit = ((num & mask) >> shift);\n\t\tif (digit == 0 && remove_leading_zeros) {\n\t\t\tmask = mask >> 4;\n\t\t\tcontinue;\n\t\t} else if (digit < 0xa)\n\t\t\t*str_ptr = digit + '0';\n\t\telse\n\t\t\t*str_ptr = digit - 0xa + 'a';\n\t\tremove_leading_zeros = 0;\n\t\tstr_ptr++;\n\t\t(*len)--;\n\t\tmask = mask >> 4;\n\t\tif (shift == 4 * 4) {\n\t\t\t*str_ptr = '.';\n\t\t\tstr_ptr++;\n\t\t\t(*len)--;\n\t\t\tremove_leading_zeros = 1;\n\t\t}\n\t}\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_null_format_ver(__rte_unused uint32_t spirom_ver,\n\t\t\t\t\t uint8_t * str, uint16_t * len)\n{\n\tstr[0] = '\\0';\n\t(*len)--;\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_set_xgxs_loopback(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tuint8_t port = params->port;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tif (phy->req_line_speed != ELINK_SPEED_1000) {\n\t\tuint32_t md_devad = 0;\n\n\t\tPMD_DRV_LOG(DEBUG, \"XGXS 10G loopback enable\");\n\n\t\tif (!CHIP_IS_E3(sc)) {\n\t\t\t/* Change the uni_phy_addr in the nig */\n\t\t\tmd_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +\n\t\t\t\t\t port * 0x18));\n\n\t\t\tREG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18,\n\t\t\t 0x5);\n\t\t}\n\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t 5,\n\t\t\t\t (MDIO_REG_BANK_AER_BLOCK +\n\t\t\t\t (MDIO_AER_BLOCK_AER_REG & 0xf)), 0x2800);\n\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t 5,\n\t\t\t\t (MDIO_REG_BANK_CL73_IEEEB0 +\n\t\t\t\t (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),\n\t\t\t\t 0x6041);\n\t\tDELAY(1000 * 200);\n\t\t/* Set aer mmd back */\n\t\telink_set_aer_mmd(params, phy);\n\n\t\tif (!CHIP_IS_E3(sc)) {\n\t\t\t/* And md_devad */\n\t\t\tREG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port * 0x18,\n\t\t\t md_devad);\n\t\t}\n\t} else {\n\t\tuint16_t mii_ctrl;\n\t\tPMD_DRV_LOG(DEBUG, \"XGXS 1G loopback enable\");\n\t\telink_cl45_read(sc, phy, 5,\n\t\t\t\t(MDIO_REG_BANK_COMBO_IEEE0 +\n\t\t\t\t (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),\n\t\t\t\t&mii_ctrl);\n\t\telink_cl45_write(sc, phy, 5,\n\t\t\t\t (MDIO_REG_BANK_COMBO_IEEE0 +\n\t\t\t\t (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),\n\t\t\t\t mii_ctrl |\n\t\t\t\t MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);\n\t}\n}\n\nelink_status_t elink_set_led(struct elink_params *params,\n\t\t\t struct elink_vars *vars, uint8_t mode,\n\t\t\t uint32_t speed)\n{\n\tuint8_t port = params->port;\n\tuint16_t hw_led_mode = params->hw_led_mode;\n\telink_status_t rc = ELINK_STATUS_OK;\n\tuint8_t phy_idx;\n\tuint32_t tmp;\n\tuint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;\n\tstruct bnx2x_softc *sc = params->sc;\n\tPMD_DRV_LOG(DEBUG, \"elink_set_led: port %x, mode %d\", port, mode);\n\tPMD_DRV_LOG(DEBUG, \"speed 0x%x, hw_led_mode 0x%x\", speed, hw_led_mode);\n\t/* In case */\n\tfor (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {\n\t\tif (params->phy[phy_idx].set_link_led) {\n\t\t\tparams->phy[phy_idx].set_link_led(¶ms->phy[phy_idx],\n\t\t\t\t\t\t\t params, mode);\n\t\t}\n\t}\n#ifdef ELINK_INCLUDE_EMUL\n\tif (params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)\n\t\treturn rc;\n#endif\n\n\tswitch (mode) {\n\tcase ELINK_LED_MODE_FRONT_PANEL_OFF:\n\tcase ELINK_LED_MODE_OFF:\n\t\tREG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 0);\n\t\tREG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,\n\t\t SHARED_HW_CFG_LED_MAC1);\n\n\t\ttmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);\n\t\tif (params->phy[ELINK_EXT_PHY1].type ==\n\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)\n\t\t\ttmp &= ~(EMAC_LED_1000MB_OVERRIDE |\n\t\t\t\t EMAC_LED_100MB_OVERRIDE |\n\t\t\t\t EMAC_LED_10MB_OVERRIDE);\n\t\telse\n\t\t\ttmp |= EMAC_LED_OVERRIDE;\n\n\t\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp);\n\t\tbreak;\n\n\tcase ELINK_LED_MODE_OPER:\n\t\t/* For all other phys, OPER mode is same as ON, so in case\n\t\t * link is down, do nothing\n\t\t */\n\t\tif (!vars->link_up)\n\t\t\tbreak;\n\tcase ELINK_LED_MODE_ON:\n\t\tif (((params->phy[ELINK_EXT_PHY1].type ==\n\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727) ||\n\t\t (params->phy[ELINK_EXT_PHY1].type ==\n\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722)) &&\n\t\t CHIP_IS_E2(sc) && params->num_phys == 2) {\n\t\t\t/* This is a work-around for E2+8727 Configurations */\n\t\t\tif (mode == ELINK_LED_MODE_ON ||\n\t\t\t speed == ELINK_SPEED_10000) {\n\t\t\t\tREG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);\n\t\t\t\tREG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);\n\n\t\t\t\ttmp =\n\t\t\t\t elink_cb_reg_read(sc,\n\t\t\t\t\t\t emac_base +\n\t\t\t\t\t\t EMAC_REG_EMAC_LED);\n\t\t\t\telink_cb_reg_write(sc,\n\t\t\t\t\t\t emac_base +\n\t\t\t\t\t\t EMAC_REG_EMAC_LED,\n\t\t\t\t\t\t (tmp | EMAC_LED_OVERRIDE));\n\t\t\t\t/* Return here without enabling traffic\n\t\t\t\t * LED blink and setting rate in ON mode.\n\t\t\t\t * In oper mode, enabling LED blink\n\t\t\t\t * and setting rate is needed.\n\t\t\t\t */\n\t\t\t\tif (mode == ELINK_LED_MODE_ON)\n\t\t\t\t\treturn rc;\n\t\t\t}\n\t\t} else if (ELINK_SINGLE_MEDIA_DIRECT(params)) {\n\t\t\t/* This is a work-around for HW issue found when link\n\t\t\t * is up in CL73\n\t\t\t */\n\t\t\tif ((!CHIP_IS_E3(sc)) ||\n\t\t\t (CHIP_IS_E3(sc) && mode == ELINK_LED_MODE_ON))\n\t\t\t\tREG_WR(sc, NIG_REG_LED_10G_P0 + port * 4, 1);\n\n\t\t\tif (CHIP_IS_E1x(sc) ||\n\t\t\t CHIP_IS_E2(sc) || (mode == ELINK_LED_MODE_ON))\n\t\t\t\tREG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);\n\t\t\telse\n\t\t\t\tREG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,\n\t\t\t\t hw_led_mode);\n\t\t} else if ((params->phy[ELINK_EXT_PHY1].type ==\n\t\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE) &&\n\t\t\t (mode == ELINK_LED_MODE_ON)) {\n\t\t\tREG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4, 0);\n\t\t\ttmp =\n\t\t\t elink_cb_reg_read(sc,\n\t\t\t\t\t emac_base + EMAC_REG_EMAC_LED);\n\t\t\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,\n\t\t\t\t\t tmp | EMAC_LED_OVERRIDE |\n\t\t\t\t\t EMAC_LED_1000MB_OVERRIDE);\n\t\t\t/* Break here; otherwise, it'll disable the\n\t\t\t * intended override.\n\t\t\t */\n\t\t\tbreak;\n\t\t} else {\n\t\t\tuint32_t nig_led_mode = ((params->hw_led_mode <<\n\t\t\t\t\t\t SHARED_HW_CFG_LED_MODE_SHIFT)\n\t\t\t\t\t\t ==\n\t\t\t\t\t\t SHARED_HW_CFG_LED_EXTPHY2)\n\t\t\t ? (SHARED_HW_CFG_LED_PHY1 >>\n\t\t\t SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;\n\t\t\tREG_WR(sc, NIG_REG_LED_MODE_P0 + port * 4,\n\t\t\t nig_led_mode);\n\t\t}\n\n\t\tREG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port * 4,\n\t\t 0);\n\t\t/* Set blinking rate to ~15.9Hz */\n\t\tif (CHIP_IS_E3(sc))\n\t\t\tREG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,\n\t\t\t LED_BLINK_RATE_VAL_E3);\n\t\telse\n\t\t\tREG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port * 4,\n\t\t\t LED_BLINK_RATE_VAL_E1X_E2);\n\t\tREG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port * 4, 1);\n\t\ttmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);\n\t\telink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,\n\t\t\t\t (tmp & (~EMAC_LED_OVERRIDE)));\n\n\t\tbreak;\n\n\tdefault:\n\t\trc = ELINK_STATUS_ERROR;\n\t\tPMD_DRV_LOG(DEBUG, \"elink_set_led: Invalid led mode %d\", mode);\n\t\tbreak;\n\t}\n\treturn rc;\n\n}\n\nstatic elink_status_t elink_link_initialize(struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\telink_status_t rc = ELINK_STATUS_OK;\n\tuint8_t phy_index, non_ext_phy;\n\tstruct bnx2x_softc *sc = params->sc;\n\t/* In case of external phy existence, the line speed would be the\n\t * line speed linked up by the external phy. In case it is direct\n\t * only, then the line_speed during initialization will be\n\t * equal to the req_line_speed\n\t */\n\tvars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;\n\n\t/* Initialize the internal phy in case this is a direct board\n\t * (no external phys), or this board has external phy which requires\n\t * to first.\n\t */\n\tif (!USES_WARPCORE(sc))\n\t\telink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars);\n\t/* init ext phy and enable link state int */\n\tnon_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) ||\n\t\t (params->loopback_mode == ELINK_LOOPBACK_XGXS));\n\n\tif (non_ext_phy ||\n\t (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||\n\t (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {\n\t\tstruct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];\n\t\tif (vars->line_speed == ELINK_SPEED_AUTO_NEG &&\n\t\t (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc)))\n\t\t\telink_set_parallel_detection(phy, params);\n\t\tif (params->phy[ELINK_INT_PHY].config_init)\n\t\t\tparams->phy[ELINK_INT_PHY].config_init(phy,\n\t\t\t\t\t\t\t params, vars);\n\t}\n\n\t/* Re-read this value in case it was changed inside config_init due to\n\t * limitations of optic module\n\t */\n\tvars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;\n\n\t/* Init external phy */\n\tif (non_ext_phy) {\n\t\tif (params->phy[ELINK_INT_PHY].supported &\n\t\t ELINK_SUPPORTED_FIBRE)\n\t\t\tvars->link_status |= LINK_STATUS_SERDES_LINK;\n\t} else {\n\t\tfor (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;\n\t\t phy_index++) {\n\t\t\t/* No need to initialize second phy in case of first\n\t\t\t * phy only selection. In case of second phy, we do\n\t\t\t * need to initialize the first phy, since they are\n\t\t\t * connected.\n\t\t\t */\n\t\t\tif (params->phy[phy_index].supported &\n\t\t\t ELINK_SUPPORTED_FIBRE)\n\t\t\t\tvars->link_status |= LINK_STATUS_SERDES_LINK;\n\n\t\t\tif (phy_index == ELINK_EXT_PHY2 &&\n\t\t\t (elink_phy_selection(params) ==\n\t\t\t PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {\n\t\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t\t \"Not initializing second phy\");\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tparams->phy[phy_index].config_init(¶ms->\n\t\t\t\t\t\t\t phy[phy_index],\n\t\t\t\t\t\t\t params, vars);\n\t\t}\n\t}\n\t/* Reset the interrupt indication after phy was initialized */\n\telink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +\n\t\t params->port * 4,\n\t\t (ELINK_NIG_STATUS_XGXS0_LINK10G |\n\t\t\tELINK_NIG_STATUS_XGXS0_LINK_STATUS |\n\t\t\tELINK_NIG_STATUS_SERDES0_LINK_STATUS |\n\t\t\tELINK_NIG_MASK_MI_INT));\n\treturn rc;\n}\n\nstatic void elink_int_link_reset(__rte_unused struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\t/* Reset the SerDes/XGXS */\n\tREG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,\n\t (0x1ff << (params->port * 16)));\n}\n\nstatic void elink_common_ext_link_reset(__rte_unused struct elink_phy *phy,\n\t\t\t\t\tstruct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t gpio_port;\n\t/* HW reset */\n\tif (CHIP_IS_E2(sc))\n\t\tgpio_port = SC_PATH(sc);\n\telse\n\t\tgpio_port = params->port;\n\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);\n\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);\n\tPMD_DRV_LOG(DEBUG, \"reset external PHY\");\n}\n\nstatic elink_status_t elink_update_link_down(struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port = params->port;\n\n\tPMD_DRV_LOG(DEBUG, \"Port %x: Link is down\", port);\n\telink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);\n\tvars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;\n\t/* Indicate no mac active */\n\tvars->mac_type = ELINK_MAC_TYPE_NONE;\n\n\t/* Update shared memory */\n\tvars->link_status &= ~ELINK_LINK_UPDATE_MASK;\n\tvars->line_speed = 0;\n\telink_update_mng(params, vars->link_status);\n\n\t/* Activate nig drain */\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);\n\n\t/* Disable emac */\n\tif (!CHIP_IS_E3(sc))\n\t\tREG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);\n\n\tDELAY(1000 * 10);\n\t/* Reset BigMac/Xmac */\n\tif (CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))\n\t\telink_set_bmac_rx(sc, params->port, 0);\n\n\tif (CHIP_IS_E3(sc)) {\n\t\t/* Prevent LPI Generation by chip */\n\t\tREG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),\n\t\t 0);\n\t\tREG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),\n\t\t 0);\n\t\tvars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |\n\t\t\t\t SHMEM_EEE_ACTIVE_BIT);\n\n\t\telink_update_mng_eee(params, vars->eee_status);\n\t\telink_set_xmac_rxtx(params, 0);\n\t\telink_set_umac_rxtx(params, 0);\n\t}\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_update_link_up(struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars,\n\t\t\t\t\t uint8_t link_10g)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t phy_idx, port = params->port;\n\telink_status_t rc = ELINK_STATUS_OK;\n\n\tvars->link_status |= (LINK_STATUS_LINK_UP |\n\t\t\t LINK_STATUS_PHYSICAL_LINK_FLAG);\n\tvars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;\n\n\tif (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)\n\t\tvars->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;\n\n\tif (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)\n\t\tvars->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;\n\tif (USES_WARPCORE(sc)) {\n\t\tif (link_10g) {\n\t\t\tif (elink_xmac_enable(params, vars, 0) ==\n\t\t\t ELINK_STATUS_NO_LINK) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Found errors on XMAC\");\n\t\t\t\tvars->link_up = 0;\n\t\t\t\tvars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;\n\t\t\t\tvars->link_status &= ~LINK_STATUS_LINK_UP;\n\t\t\t}\n\t\t} else\n\t\t\telink_umac_enable(params, vars, 0);\n\t\telink_set_led(params, vars,\n\t\t\t ELINK_LED_MODE_OPER, vars->line_speed);\n\n\t\tif ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&\n\t\t (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Enabling LPI assertion\");\n\t\t\tREG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +\n\t\t\t (params->port << 2), 1);\n\t\t\tREG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);\n\t\t\tREG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 +\n\t\t\t (params->port << 2), 0xfc20);\n\t\t}\n\t}\n\tif ((CHIP_IS_E1x(sc) || CHIP_IS_E2(sc))) {\n\t\tif (link_10g) {\n\t\t\tif (elink_bmac_enable(params, vars, 0, 1) ==\n\t\t\t ELINK_STATUS_NO_LINK) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Found errors on BMAC\");\n\t\t\t\tvars->link_up = 0;\n\t\t\t\tvars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;\n\t\t\t\tvars->link_status &= ~LINK_STATUS_LINK_UP;\n\t\t\t}\n\n\t\t\telink_set_led(params, vars,\n\t\t\t\t ELINK_LED_MODE_OPER, ELINK_SPEED_10000);\n\t\t} else {\n\t\t\trc = elink_emac_program(params, vars);\n\t\t\telink_emac_enable(params, vars, 0);\n\n\t\t\t/* AN complete? */\n\t\t\tif ((vars->link_status &\n\t\t\t LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)\n\t\t\t && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&\n\t\t\t ELINK_SINGLE_MEDIA_DIRECT(params))\n\t\t\t\telink_set_gmii_tx_driver(params);\n\t\t}\n\t}\n\n\t/* PBF - link up */\n\tif (CHIP_IS_E1x(sc))\n\t\trc |= elink_pbf_update(params, vars->flow_ctrl,\n\t\t\t\t vars->line_speed);\n\n\t/* Disable drain */\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 0);\n\n\t/* Update shared memory */\n\telink_update_mng(params, vars->link_status);\n\telink_update_mng_eee(params, vars->eee_status);\n\t/* Check remote fault */\n\tfor (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {\n\t\tif (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {\n\t\t\telink_check_half_open_conn(params, vars, 0);\n\t\t\tbreak;\n\t\t}\n\t}\n\tDELAY(1000 * 20);\n\treturn rc;\n}\n\n/* The elink_link_update function should be called upon link\n * interrupt.\n * Link is considered up as follows:\n * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs\n * to be up\n * - SINGLE_MEDIA - The link between the 577xx and the external\n * phy (XGXS) need to up as well as the external link of the\n * phy (PHY_EXT1)\n * - DUAL_MEDIA - The link between the 577xx and the first\n * external phy needs to be up, and at least one of the 2\n * external phy link must be up.\n */\nelink_status_t elink_link_update(struct elink_params * params,\n\t\t\t\t struct elink_vars * vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tstruct elink_vars phy_vars[ELINK_MAX_PHYS];\n\tuint8_t port = params->port;\n\tuint8_t link_10g_plus, phy_index;\n\tuint8_t ext_phy_link_up = 0, cur_link_up;\n\telink_status_t rc = ELINK_STATUS_OK;\n\t__rte_unused uint8_t is_mi_int = 0;\n\tuint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;\n\tuint8_t active_external_phy = ELINK_INT_PHY;\n\tvars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;\n\tvars->link_status &= ~ELINK_LINK_UPDATE_MASK;\n\tfor (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;\n\t phy_index++) {\n\t\tphy_vars[phy_index].flow_ctrl = 0;\n\t\tphy_vars[phy_index].link_status = 0;\n\t\tphy_vars[phy_index].line_speed = 0;\n\t\tphy_vars[phy_index].duplex = DUPLEX_FULL;\n\t\tphy_vars[phy_index].phy_link_up = 0;\n\t\tphy_vars[phy_index].link_up = 0;\n\t\tphy_vars[phy_index].fault_detected = 0;\n\t\t/* different consideration, since vars holds inner state */\n\t\tphy_vars[phy_index].eee_status = vars->eee_status;\n\t}\n\n\tif (USES_WARPCORE(sc))\n\t\telink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);\n\n\tPMD_DRV_LOG(DEBUG, \"port %x, XGXS?%x, int_status 0x%x\",\n\t\t port, (vars->phy_flags & PHY_XGXS_FLAG),\n\t\t REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port * 4));\n\n\tis_mi_int = (uint8_t) (REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +\n\t\t\t\t port * 0x18) > 0);\n\tPMD_DRV_LOG(DEBUG, \"int_mask 0x%x MI_INT %x, SERDES_LINK %x\",\n\t\t REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4),\n\t\t is_mi_int,\n\t\t REG_RD(sc,\n\t\t\t NIG_REG_SERDES0_STATUS_LINK_STATUS + port * 0x3c));\n\n\tPMD_DRV_LOG(DEBUG, \" 10G %x, XGXS_LINK %x\",\n\t\t REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port * 0x68),\n\t\t REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port * 0x68));\n\n\t/* Disable emac */\n\tif (!CHIP_IS_E3(sc))\n\t\tREG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);\n\n\t/* Step 1:\n\t * Check external link change only for external phys, and apply\n\t * priority selection between them in case the link on both phys\n\t * is up. Note that instead of the common vars, a temporary\n\t * vars argument is used since each phy may have different link/\n\t * speed/duplex result\n\t */\n\tfor (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;\n\t phy_index++) {\n\t\tstruct elink_phy *phy = ¶ms->phy[phy_index];\n\t\tif (!phy->read_status)\n\t\t\tcontinue;\n\t\t/* Read link status and params of this ext phy */\n\t\tcur_link_up = phy->read_status(phy, params,\n\t\t\t\t\t &phy_vars[phy_index]);\n\t\tif (cur_link_up) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"phy in index %d link is up\",\n\t\t\t\t phy_index);\n\t\t} else {\n\t\t\tPMD_DRV_LOG(DEBUG, \"phy in index %d link is down\",\n\t\t\t\t phy_index);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (!ext_phy_link_up) {\n\t\t\text_phy_link_up = 1;\n\t\t\tactive_external_phy = phy_index;\n\t\t} else {\n\t\t\tswitch (elink_phy_selection(params)) {\n\t\t\tcase PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:\n\t\t\tcase PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:\n\t\t\t\t/* In this option, the first PHY makes sure to pass the\n\t\t\t\t * traffic through itself only.\n\t\t\t\t * Its not clear how to reset the link on the second phy\n\t\t\t\t */\n\t\t\t\tactive_external_phy = ELINK_EXT_PHY1;\n\t\t\t\tbreak;\n\t\t\tcase PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:\n\t\t\t\t/* In this option, the first PHY makes sure to pass the\n\t\t\t\t * traffic through the second PHY.\n\t\t\t\t */\n\t\t\t\tactive_external_phy = ELINK_EXT_PHY2;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\t/* Link indication on both PHYs with the following cases\n\t\t\t\t * is invalid:\n\t\t\t\t * - FIRST_PHY means that second phy wasn't initialized,\n\t\t\t\t * hence its link is expected to be down\n\t\t\t\t * - SECOND_PHY means that first phy should not be able\n\t\t\t\t * to link up by itself (using configuration)\n\t\t\t\t * - DEFAULT should be overriden during initialiazation\n\t\t\t\t */\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Invalid link indication\"\n\t\t\t\t\t \"mpc=0x%x. DISABLING LINK !!!\",\n\t\t\t\t\t params->multi_phy_config);\n\t\t\t\text_phy_link_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tprev_line_speed = vars->line_speed;\n\t/* Step 2:\n\t * Read the status of the internal phy. In case of\n\t * DIRECT_SINGLE_MEDIA board, this link is the external link,\n\t * otherwise this is the link between the 577xx and the first\n\t * external phy\n\t */\n\tif (params->phy[ELINK_INT_PHY].read_status)\n\t\tparams->phy[ELINK_INT_PHY].read_status(¶ms->\n\t\t\t\t\t\t phy[ELINK_INT_PHY],\n\t\t\t\t\t\t params, vars);\n\t/* The INT_PHY flow control reside in the vars. This include the\n\t * case where the speed or flow control are not set to AUTO.\n\t * Otherwise, the active external phy flow control result is set\n\t * to the vars. The ext_phy_line_speed is needed to check if the\n\t * speed is different between the internal phy and external phy.\n\t * This case may be result of intermediate link speed change.\n\t */\n\tif (active_external_phy > ELINK_INT_PHY) {\n\t\tvars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;\n\t\t/* Link speed is taken from the XGXS. AN and FC result from\n\t\t * the external phy.\n\t\t */\n\t\tvars->link_status |= phy_vars[active_external_phy].link_status;\n\n\t\t/* if active_external_phy is first PHY and link is up - disable\n\t\t * disable TX on second external PHY\n\t\t */\n\t\tif (active_external_phy == ELINK_EXT_PHY1) {\n\t\t\tif (params->phy[ELINK_EXT_PHY2].phy_specific_func) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Disabling TX on EXT_PHY2\");\n\t\t\t\tparams->phy[ELINK_EXT_PHY2].\n\t\t\t\t phy_specific_func(¶ms->\n\t\t\t\t\t\t phy[ELINK_EXT_PHY2],\n\t\t\t\t\t\t params, ELINK_DISABLE_TX);\n\t\t\t}\n\t\t}\n\n\t\text_phy_line_speed = phy_vars[active_external_phy].line_speed;\n\t\tvars->duplex = phy_vars[active_external_phy].duplex;\n\t\tif (params->phy[active_external_phy].supported &\n\t\t ELINK_SUPPORTED_FIBRE)\n\t\t\tvars->link_status |= LINK_STATUS_SERDES_LINK;\n\t\telse\n\t\t\tvars->link_status &= ~LINK_STATUS_SERDES_LINK;\n\n\t\tvars->eee_status = phy_vars[active_external_phy].eee_status;\n\n\t\tPMD_DRV_LOG(DEBUG, \"Active external phy selected: %x\",\n\t\t\t active_external_phy);\n\t}\n\n\tfor (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;\n\t phy_index++) {\n\t\tif (params->phy[phy_index].flags &\n\t\t ELINK_FLAGS_REARM_LATCH_SIGNAL) {\n\t\t\telink_rearm_latch_signal(sc, port,\n\t\t\t\t\t\t phy_index ==\n\t\t\t\t\t\t active_external_phy);\n\t\t\tbreak;\n\t\t}\n\t}\n\tPMD_DRV_LOG(DEBUG, \"vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,\"\n\t\t \" ext_phy_line_speed = %d\", vars->flow_ctrl,\n\t\t vars->link_status, ext_phy_line_speed);\n\t/* Upon link speed change set the NIG into drain mode. Comes to\n\t * deals with possible FIFO glitch due to clk change when speed\n\t * is decreased without link down indicator\n\t */\n\n\tif (vars->phy_link_up) {\n\t\tif (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&\n\t\t (ext_phy_line_speed != vars->line_speed)) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Internal link speed %d is\"\n\t\t\t\t \" different than the external\"\n\t\t\t\t \" link speed %d\", vars->line_speed,\n\t\t\t\t ext_phy_line_speed);\n\t\t\tvars->phy_link_up = 0;\n\t\t} else if (prev_line_speed != vars->line_speed) {\n\t\t\tREG_WR(sc,\n\t\t\t NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4,\n\t\t\t 0);\n\t\t\tDELAY(1000 * 1);\n\t\t}\n\t}\n\n\t/* Anything 10 and over uses the bmac */\n\tlink_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);\n\n\telink_link_int_ack(params, vars, link_10g_plus);\n\n\t/* In case external phy link is up, and internal link is down\n\t * (not initialized yet probably after link initialization, it\n\t * needs to be initialized.\n\t * Note that after link down-up as result of cable plug, the xgxs\n\t * link would probably become up again without the need\n\t * initialize it\n\t */\n\tif (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {\n\t\tPMD_DRV_LOG(DEBUG, \"ext_phy_link_up = %d, int_link_up = %d,\"\n\t\t\t \" init_preceding = %d\", ext_phy_link_up,\n\t\t\t vars->phy_link_up,\n\t\t\t params->phy[ELINK_EXT_PHY1].flags &\n\t\t\t ELINK_FLAGS_INIT_XGXS_FIRST);\n\t\tif (!(params->phy[ELINK_EXT_PHY1].flags &\n\t\t ELINK_FLAGS_INIT_XGXS_FIRST)\n\t\t && ext_phy_link_up && !vars->phy_link_up) {\n\t\t\tvars->line_speed = ext_phy_line_speed;\n\t\t\tif (vars->line_speed < ELINK_SPEED_1000)\n\t\t\t\tvars->phy_flags |= PHY_SGMII_FLAG;\n\t\t\telse\n\t\t\t\tvars->phy_flags &= ~PHY_SGMII_FLAG;\n\n\t\t\tif (params->phy[ELINK_INT_PHY].config_init)\n\t\t\t\tparams->phy[ELINK_INT_PHY].config_init(¶ms->\n\t\t\t\t\t\t\t\t phy\n\t\t\t\t\t\t\t\t [ELINK_INT_PHY],\n\t\t\t\t\t\t\t\t params,\n\t\t\t\t\t\t\t\t vars);\n\t\t}\n\t}\n\t/* Link is up only if both local phy and external phy (in case of\n\t * non-direct board) are up and no fault detected on active PHY.\n\t */\n\tvars->link_up = (vars->phy_link_up &&\n\t\t\t (ext_phy_link_up ||\n\t\t\t ELINK_SINGLE_MEDIA_DIRECT(params)) &&\n\t\t\t (phy_vars[active_external_phy].fault_detected == 0));\n\n\t/* Update the PFC configuration in case it was changed */\n\tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)\n\t\tvars->link_status |= LINK_STATUS_PFC_ENABLED;\n\telse\n\t\tvars->link_status &= ~LINK_STATUS_PFC_ENABLED;\n\n\tif (vars->link_up)\n\t\trc = elink_update_link_up(params, vars, link_10g_plus);\n\telse\n\t\trc = elink_update_link_down(params, vars);\n\n\t/* Update MCP link status was changed */\n\tif (params->\n\t feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)\n\t\telink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);\n\n\treturn rc;\n}\n\n/*****************************************************************************/\n/*\t\t\t External Phy section\t\t\t */\n/*****************************************************************************/\nstatic void elink_ext_phy_hw_reset(struct bnx2x_softc *sc, uint8_t port)\n{\n\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, port);\n\tDELAY(1000 * 1);\n\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);\n}\n\nstatic void elink_save_spirom_version(struct bnx2x_softc *sc,\n\t\t\t\t __rte_unused uint8_t port,\n\t\t\t\t uint32_t spirom_ver, uint32_t ver_addr)\n{\n\tPMD_DRV_LOG(DEBUG, \"FW version 0x%x:0x%x for port %d\",\n\t\t (uint16_t) (spirom_ver >> 16), (uint16_t) spirom_ver, port);\n\n\tif (ver_addr)\n\t\tREG_WR(sc, ver_addr, spirom_ver);\n}\n\nstatic void elink_save_bnx2x_spirom_ver(struct bnx2x_softc *sc,\n\t\t\t\t struct elink_phy *phy, uint8_t port)\n{\n\tuint16_t fw_ver1, fw_ver2;\n\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n\t\t\tMDIO_PMA_REG_ROM_VER1, &fw_ver1);\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n\t\t\tMDIO_PMA_REG_ROM_VER2, &fw_ver2);\n\telink_save_spirom_version(sc, port,\n\t\t\t\t (uint32_t) (fw_ver1 << 16 | fw_ver2),\n\t\t\t\t phy->ver_addr);\n}\n\nstatic void elink_ext_phy_10G_an_resolve(struct bnx2x_softc *sc,\n\t\t\t\t\t struct elink_phy *phy,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tuint16_t val;\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_STATUS, &val);\n\tif (val & (1 << 5))\n\t\tvars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n\tif ((val & (1 << 0)) == 0)\n\t\tvars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;\n}\n\n/******************************************************************/\n/*\t\tcommon BNX2X8073/BNX2X8727 PHY SECTION\t\t */\n/******************************************************************/\nstatic void elink_8073_resolve_fc(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tif (phy->req_line_speed == ELINK_SPEED_10 ||\n\t phy->req_line_speed == ELINK_SPEED_100) {\n\t\tvars->flow_ctrl = phy->req_flow_ctrl;\n\t\treturn;\n\t}\n\n\tif (elink_ext_phy_resolve_fc(phy, params, vars) &&\n\t (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {\n\t\tuint16_t pause_result;\n\t\tuint16_t ld_pause;\t/* local */\n\t\tuint16_t lp_pause;\t/* link partner */\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_AN_DEVAD,\n\t\t\t\tMDIO_AN_REG_CL37_FC_LD, &ld_pause);\n\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_AN_DEVAD,\n\t\t\t\tMDIO_AN_REG_CL37_FC_LP, &lp_pause);\n\t\tpause_result = (ld_pause &\n\t\t\t\tMDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;\n\t\tpause_result |= (lp_pause &\n\t\t\t\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;\n\n\t\telink_pause_resolve(vars, pause_result);\n\t\tPMD_DRV_LOG(DEBUG, \"Ext PHY CL37 pause result 0x%x\",\n\t\t\t pause_result);\n\t}\n}\n\nstatic elink_status_t elink_8073_8727_external_rom_boot(struct bnx2x_softc *sc,\n\t\t\t\t\t\t\tstruct elink_phy *phy,\n\t\t\t\t\t\t\tuint8_t port)\n{\n\tuint32_t count = 0;\n\tuint16_t fw_ver1, fw_msgout;\n\telink_status_t rc = ELINK_STATUS_OK;\n\n\t/* Boot port from external ROM */\n\t/* EDC grst */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);\n\n\t/* Ucode reboot and rst */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x008c);\n\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);\n\n\t/* Reset internal microprocessor */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD,\n\t\t\t MDIO_PMA_REG_GEN_CTRL,\n\t\t\t MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);\n\n\t/* Release srst bit */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD,\n\t\t\t MDIO_PMA_REG_GEN_CTRL,\n\t\t\t MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);\n\n\t/* Delay 100ms per the PHY specifications */\n\tDELAY(1000 * 100);\n\n\t/* 8073 sometimes taking longer to download */\n\tdo {\n\t\tcount++;\n\t\tif (count > 300) {\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"elink_8073_8727_external_rom_boot port %x:\"\n\t\t\t\t \"Download failed. fw version = 0x%x\",\n\t\t\t\t port, fw_ver1);\n\t\t\trc = ELINK_STATUS_ERROR;\n\t\t\tbreak;\n\t\t}\n\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_ROM_VER1, &fw_ver1);\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);\n\n\t\tDELAY(1000 * 1);\n\t} while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||\n\t\t ((fw_msgout & 0xff) != 0x03 && (phy->type ==\n\t\t\t\t\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073)));\n\n\t/* Clear ser_boot_ctl bit */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);\n\telink_save_bnx2x_spirom_ver(sc, phy, port);\n\n\tPMD_DRV_LOG(DEBUG,\n\t\t \"elink_8073_8727_external_rom_boot port %x:\"\n\t\t \"Download complete. fw version = 0x%x\", port, fw_ver1);\n\n\treturn rc;\n}\n\n/******************************************************************/\n/*\t\t\tBNX2X8073 PHY SECTION\t\t\t */\n/******************************************************************/\nstatic elink_status_t elink_8073_is_snr_needed(struct bnx2x_softc *sc,\n\t\t\t\t\t struct elink_phy *phy)\n{\n\t/* This is only required for 8073A1, version 102 only */\n\tuint16_t val;\n\n\t/* Read 8073 HW revision */\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);\n\n\tif (val != 1) {\n\t\t/* No need to workaround in 8073 A1 */\n\t\treturn ELINK_STATUS_OK;\n\t}\n\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &val);\n\n\t/* SNR should be applied only for version 0x102 */\n\tif (val != 0x102)\n\t\treturn ELINK_STATUS_OK;\n\n\treturn 1;\n}\n\nstatic elink_status_t elink_8073_xaui_wa(struct bnx2x_softc *sc,\n\t\t\t\t\t struct elink_phy *phy)\n{\n\tuint16_t val, cnt, cnt1;\n\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);\n\n\tif (val > 0) {\n\t\t/* No need to workaround in 8073 A1 */\n\t\treturn ELINK_STATUS_OK;\n\t}\n\t/* XAUI workaround in 8073 A0: */\n\n\t/* After loading the boot ROM and restarting Autoneg, poll\n\t * Dev1, Reg $C820:\n\t */\n\n\tfor (cnt = 0; cnt < 1000; cnt++) {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_8073_SPEED_LINK_STATUS, &val);\n\t\t/* If bit [14] = 0 or bit [13] = 0, continue on with\n\t\t * system initialization (XAUI work-around not required, as\n\t\t * these bits indicate 2.5G or 1G link up).\n\t\t */\n\t\tif (!(val & (1 << 14)) || !(val & (1 << 13))) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"XAUI work-around not required\");\n\t\t\treturn ELINK_STATUS_OK;\n\t\t} else if (!(val & (1 << 15))) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"bit 15 went off\");\n\t\t\t/* If bit 15 is 0, then poll Dev1, Reg $C841 until it's\n\t\t\t * MSB (bit15) goes to 1 (indicating that the XAUI\n\t\t\t * workaround has completed), then continue on with\n\t\t\t * system initialization.\n\t\t\t */\n\t\t\tfor (cnt1 = 0; cnt1 < 1000; cnt1++) {\n\t\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\t\t\tMDIO_PMA_REG_8073_XAUI_WA,\n\t\t\t\t\t\t&val);\n\t\t\t\tif (val & (1 << 15)) {\n\t\t\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t\t\t \"XAUI workaround has completed\");\n\t\t\t\t\treturn ELINK_STATUS_OK;\n\t\t\t\t}\n\t\t\t\tDELAY(1000 * 3);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\tDELAY(1000 * 3);\n\t}\n\tPMD_DRV_LOG(DEBUG, \"Warning: XAUI work-around timeout !!!\");\n\treturn ELINK_STATUS_ERROR;\n}\n\nstatic void elink_807x_force_10G(struct bnx2x_softc *sc, struct elink_phy *phy)\n{\n\t/* Force KR or KX */\n\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0000);\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);\n}\n\nstatic void elink_8073_set_pause_cl37(struct elink_params *params,\n\t\t\t\t struct elink_phy *phy,\n\t\t\t\t struct elink_vars *vars)\n{\n\tuint16_t cl37_val;\n\tstruct bnx2x_softc *sc = params->sc;\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);\n\n\tcl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;\n\t/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */\n\telink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);\n\tif ((vars->ieee_fc &\n\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==\n\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {\n\t\tcl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;\n\t}\n\tif ((vars->ieee_fc &\n\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==\n\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {\n\t\tcl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;\n\t}\n\tif ((vars->ieee_fc &\n\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==\n\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {\n\t\tcl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;\n\t}\n\tPMD_DRV_LOG(DEBUG, \"Ext phy AN advertize cl37 0x%x\", cl37_val);\n\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);\n\tDELAY(1000 * 500);\n}\n\nstatic void elink_8073_specific_func(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t uint32_t action)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tswitch (action) {\n\tcase ELINK_PHY_INIT:\n\t\t/* Enable LASI */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,\n\t\t\t\t (1 << 2));\n\t\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,\n\t\t\t\t 0x0004);\n\t\tbreak;\n\t}\n}\n\nstatic elink_status_t elink_8073_config_init(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val = 0, tmp1;\n\tuint8_t gpio_port;\n\tPMD_DRV_LOG(DEBUG, \"Init 8073\");\n\n\tif (CHIP_IS_E2(sc))\n\t\tgpio_port = SC_PATH(sc);\n\telse\n\t\tgpio_port = params->port;\n\t/* Restore normal power mode */\n\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);\n\n\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);\n\n\telink_8073_specific_func(phy, params, ELINK_PHY_INIT);\n\telink_8073_set_pause_cl37(params, phy, vars);\n\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);\n\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);\n\n\tPMD_DRV_LOG(DEBUG, \"Before rom RX_ALARM(port1): 0x%x\", tmp1);\n\n\t/* Swap polarity if required - Must be done only in non-1G mode */\n\tif (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {\n\t\t/* Configure the 8073 to swap _P and _N of the KR lines */\n\t\tPMD_DRV_LOG(DEBUG, \"Swapping polarity for the 8073\");\n\t\t/* 10G Rx/Tx and 1G Tx signal polarity swap */\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,\n\t\t\t\t (val | (3 << 9)));\n\t}\n\n\t/* Enable CL37 BAM */\n\tif (REG_RD(sc, params->shmem_base +\n\t\t offsetof(struct shmem_region,\n\t\t\t dev_info.port_hw_config[params->port].\n\t\t\t default_cfg)) &\n\t PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {\n\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, &val);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_8073_BAM, val | 1);\n\t\tPMD_DRV_LOG(DEBUG, \"Enable CL37 BAM on KR\");\n\t}\n\tif (params->loopback_mode == ELINK_LOOPBACK_EXT) {\n\t\telink_807x_force_10G(sc, phy);\n\t\tPMD_DRV_LOG(DEBUG, \"Forced speed 10G on 807X\");\n\t\treturn ELINK_STATUS_OK;\n\t} else {\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_BNX2X_CTRL, 0x0002);\n\t}\n\tif (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {\n\t\tif (phy->req_line_speed == ELINK_SPEED_10000) {\n\t\t\tval = (1 << 7);\n\t\t} else if (phy->req_line_speed == ELINK_SPEED_2500) {\n\t\t\tval = (1 << 5);\n\t\t\t/* Note that 2.5G works only when used with 1G\n\t\t\t * advertisement\n\t\t\t */\n\t\t} else\n\t\t\tval = (1 << 5);\n\t} else {\n\t\tval = 0;\n\t\tif (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)\n\t\t\tval |= (1 << 7);\n\n\t\t/* Note that 2.5G works only when used with 1G advertisement */\n\t\tif (phy->speed_cap_mask &\n\t\t (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))\n\t\t\tval |= (1 << 5);\n\t\tPMD_DRV_LOG(DEBUG, \"807x autoneg val = 0x%x\", val);\n\t}\n\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);\n\n\tif (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&\n\t (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||\n\t (phy->req_line_speed == ELINK_SPEED_2500)) {\n\t\tuint16_t phy_ver;\n\t\t/* Allow 2.5G for A1 and above */\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,\n\t\t\t\t&phy_ver);\n\t\tPMD_DRV_LOG(DEBUG, \"Add 2.5G\");\n\t\tif (phy_ver > 0)\n\t\t\ttmp1 |= 1;\n\t\telse\n\t\t\ttmp1 &= 0xfffe;\n\t} else {\n\t\tPMD_DRV_LOG(DEBUG, \"Disable 2.5G\");\n\t\ttmp1 &= 0xfffe;\n\t}\n\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);\n\t/* Add support for CL37 (passive mode) II */\n\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,\n\t\t\t (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?\n\t\t\t\t 0x20 : 0x40)));\n\n\t/* Add support for CL37 (passive mode) III */\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);\n\n\t/* The SNR will improve about 2db by changing BW and FEE main\n\t * tap. Rest commands are executed after link is up\n\t * Change FFE main cursor to 5 in EDC register\n\t */\n\tif (elink_8073_is_snr_needed(sc, phy))\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,\n\t\t\t\t 0xFB0C);\n\n\t/* Enable FEC (Forware Error Correction) Request in the AN */\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);\n\ttmp1 |= (1 << 15);\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);\n\n\telink_ext_phy_set_pause(params, phy, vars);\n\n\t/* Restart autoneg */\n\tDELAY(1000 * 500);\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);\n\tPMD_DRV_LOG(DEBUG, \"807x Autoneg Restart: Advertise 1G=%x, 10G=%x\",\n\t\t ((val & (1 << 5)) > 0), ((val & (1 << 7)) > 0));\n\treturn ELINK_STATUS_OK;\n}\n\nstatic uint8_t elink_8073_read_status(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t link_up = 0;\n\tuint16_t val1, val2;\n\tuint16_t link_status = 0;\n\tuint16_t an1000_status = 0;\n\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);\n\n\tPMD_DRV_LOG(DEBUG, \"8703 LASI status 0x%x\", val1);\n\n\t/* Clear the interrupt LASI status register */\n\telink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);\n\telink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);\n\tPMD_DRV_LOG(DEBUG, \"807x PCS status 0x%x->0x%x\", val2, val1);\n\t/* Clear MSG-OUT */\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);\n\n\t/* Check the LASI */\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);\n\n\tPMD_DRV_LOG(DEBUG, \"KR 0x9003 0x%x\", val2);\n\n\t/* Check the link status */\n\telink_cl45_read(sc, phy, MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);\n\tPMD_DRV_LOG(DEBUG, \"KR PCS status 0x%x\", val2);\n\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);\n\tlink_up = ((val1 & 4) == 4);\n\tPMD_DRV_LOG(DEBUG, \"PMA_REG_STATUS=0x%x\", val1);\n\n\tif (link_up && ((phy->req_line_speed != ELINK_SPEED_10000))) {\n\t\tif (elink_8073_xaui_wa(sc, phy) != 0)\n\t\t\treturn 0;\n\t}\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);\n\n\t/* Check the link status on 1.1.2 */\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);\n\tPMD_DRV_LOG(DEBUG, \"KR PMA status 0x%x->0x%x,\"\n\t\t \"an_link_status=0x%x\", val2, val1, an1000_status);\n\n\tlink_up = (((val1 & 4) == 4) || (an1000_status & (1 << 1)));\n\tif (link_up && elink_8073_is_snr_needed(sc, phy)) {\n\t\t/* The SNR will improve about 2dbby changing the BW and FEE main\n\t\t * tap. The 1st write to change FFE main tap is set before\n\t\t * restart AN. Change PLL Bandwidth in EDC register\n\t\t */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,\n\t\t\t\t 0x26BC);\n\n\t\t/* Change CDR Bandwidth in EDC register */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,\n\t\t\t\t 0x0333);\n\t}\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,\n\t\t\t&link_status);\n\n\t/* Bits 0..2 --> speed detected, bits 13..15--> link is down */\n\tif ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {\n\t\tlink_up = 1;\n\t\tvars->line_speed = ELINK_SPEED_10000;\n\t\tPMD_DRV_LOG(DEBUG, \"port %x: External link up in 10G\",\n\t\t\t params->port);\n\t} else if ((link_status & (1 << 1)) && (!(link_status & (1 << 14)))) {\n\t\tlink_up = 1;\n\t\tvars->line_speed = ELINK_SPEED_2500;\n\t\tPMD_DRV_LOG(DEBUG, \"port %x: External link up in 2.5G\",\n\t\t\t params->port);\n\t} else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {\n\t\tlink_up = 1;\n\t\tvars->line_speed = ELINK_SPEED_1000;\n\t\tPMD_DRV_LOG(DEBUG, \"port %x: External link up in 1G\",\n\t\t\t params->port);\n\t} else {\n\t\tlink_up = 0;\n\t\tPMD_DRV_LOG(DEBUG, \"port %x: External link is down\",\n\t\t\t params->port);\n\t}\n\n\tif (link_up) {\n\t\t/* Swap polarity if required */\n\t\tif (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {\n\t\t\t/* Configure the 8073 to swap P and N of the KR lines */\n\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\tMDIO_XS_DEVAD,\n\t\t\t\t\tMDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);\n\t\t\t/* Set bit 3 to invert Rx in 1G mode and clear this bit\n\t\t\t * when it`s in 10G mode.\n\t\t\t */\n\t\t\tif (vars->line_speed == ELINK_SPEED_1000) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Swapping 1G polarity for\"\n\t\t\t\t\t \"the 8073\");\n\t\t\t\tval1 |= (1 << 3);\n\t\t\t} else\n\t\t\t\tval1 &= ~(1 << 3);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_XS_DEVAD,\n\t\t\t\t\t MDIO_XS_REG_8073_RX_CTRL_PCIE, val1);\n\t\t}\n\t\telink_ext_phy_10G_an_resolve(sc, phy, vars);\n\t\telink_8073_resolve_fc(phy, params, vars);\n\t\tvars->duplex = DUPLEX_FULL;\n\t}\n\n\tif (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {\n\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\tMDIO_AN_REG_LP_AUTO_NEG2, &val1);\n\n\t\tif (val1 & (1 << 5))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n\t\tif (val1 & (1 << 7))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n\t}\n\n\treturn link_up;\n}\n\nstatic void elink_8073_link_reset(__rte_unused struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t gpio_port;\n\tif (CHIP_IS_E2(sc))\n\t\tgpio_port = SC_PATH(sc);\n\telse\n\t\tgpio_port = params->port;\n\tPMD_DRV_LOG(DEBUG, \"Setting 8073 port %d into low power mode\",\n\t\t gpio_port);\n\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, gpio_port);\n}\n\n/******************************************************************/\n/*\t\t\tBNX2X8705 PHY SECTION\t\t\t */\n/******************************************************************/\nstatic elink_status_t elink_8705_config_init(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t __rte_unused struct elink_vars\n\t\t\t\t\t *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tPMD_DRV_LOG(DEBUG, \"init 8705\");\n\t/* Restore normal power mode */\n\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);\n\t/* HW reset */\n\telink_ext_phy_hw_reset(sc, params->port);\n\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);\n\telink_wait_reset_complete(sc, phy, params);\n\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);\n\telink_cl45_write(sc, phy, MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);\n\t/* BNX2X8705 doesn't have microcode, hence the 0 */\n\telink_save_spirom_version(sc, params->port, params->shmem_base, 0);\n\treturn ELINK_STATUS_OK;\n}\n\nstatic uint8_t elink_8705_read_status(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tuint8_t link_up = 0;\n\tuint16_t val1, rx_sd;\n\tstruct bnx2x_softc *sc = params->sc;\n\tPMD_DRV_LOG(DEBUG, \"read status 8705\");\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);\n\tPMD_DRV_LOG(DEBUG, \"8705 LASI status 0x%x\", val1);\n\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);\n\tPMD_DRV_LOG(DEBUG, \"8705 LASI status 0x%x\", val1);\n\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);\n\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xc809, &val1);\n\n\tPMD_DRV_LOG(DEBUG, \"8705 1.c809 val=0x%x\", val1);\n\tlink_up = ((rx_sd & 0x1) && (val1 & (1 << 9))\n\t\t && ((val1 & (1 << 8)) == 0));\n\tif (link_up) {\n\t\tvars->line_speed = ELINK_SPEED_10000;\n\t\telink_ext_phy_resolve_fc(phy, params, vars);\n\t}\n\treturn link_up;\n}\n\n/******************************************************************/\n/*\t\t\tSFP+ module Section\t\t\t */\n/******************************************************************/\nstatic void elink_set_disable_pmd_transmit(struct elink_params *params,\n\t\t\t\t\t struct elink_phy *phy,\n\t\t\t\t\t uint8_t pmd_dis)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\t/* Disable transmitter only for bootcodes which can enable it afterwards\n\t * (for D3 link)\n\t */\n\tif (pmd_dis) {\n\t\tif (params->feature_config_flags &\n\t\t ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Disabling PMD transmitter\");\n\t\t} else {\n\t\t\tPMD_DRV_LOG(DEBUG, \"NOT disabling PMD transmitter\");\n\t\t\treturn;\n\t\t}\n\t} else {\n\t\tPMD_DRV_LOG(DEBUG, \"Enabling PMD transmitter\");\n\t}\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, pmd_dis);\n}\n\nstatic uint8_t elink_get_gpio_port(struct elink_params *params)\n{\n\tuint8_t gpio_port;\n\tuint32_t swap_val, swap_override;\n\tstruct bnx2x_softc *sc = params->sc;\n\tif (CHIP_IS_E2(sc)) {\n\t\tgpio_port = SC_PATH(sc);\n\t} else {\n\t\tgpio_port = params->port;\n\t}\n\tswap_val = REG_RD(sc, NIG_REG_PORT_SWAP);\n\tswap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);\n\treturn gpio_port ^ (swap_val && swap_override);\n}\n\nstatic void elink_sfp_e1e2_set_transmitter(struct elink_params *params,\n\t\t\t\t\t struct elink_phy *phy, uint8_t tx_en)\n{\n\tuint16_t val;\n\tuint8_t port = params->port;\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t tx_en_mode;\n\n\t/* Disable/Enable transmitter ( TX laser of the SFP+ module.) */\n\ttx_en_mode = REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_hw_config[port].sfp_ctrl)) &\n\t PORT_HW_CFG_TX_LASER_MASK;\n\tPMD_DRV_LOG(DEBUG, \"Setting transmitter tx_en=%x for port %x \"\n\t\t \"mode = %x\", tx_en, port, tx_en_mode);\n\tswitch (tx_en_mode) {\n\tcase PORT_HW_CFG_TX_LASER_MDIO:\n\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_PHY_IDENTIFIER, &val);\n\n\t\tif (tx_en)\n\t\t\tval &= ~(1 << 15);\n\t\telse\n\t\t\tval |= (1 << 15);\n\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_PHY_IDENTIFIER, val);\n\t\tbreak;\n\tcase PORT_HW_CFG_TX_LASER_GPIO0:\n\tcase PORT_HW_CFG_TX_LASER_GPIO1:\n\tcase PORT_HW_CFG_TX_LASER_GPIO2:\n\tcase PORT_HW_CFG_TX_LASER_GPIO3:\n\t\t{\n\t\t\tuint16_t gpio_pin;\n\t\t\tuint8_t gpio_port, gpio_mode;\n\t\t\tif (tx_en)\n\t\t\t\tgpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;\n\t\t\telse\n\t\t\t\tgpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;\n\n\t\t\tgpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;\n\t\t\tgpio_port = elink_get_gpio_port(params);\n\t\t\telink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);\n\t\t\tbreak;\n\t\t}\n\tdefault:\n\t\tPMD_DRV_LOG(DEBUG, \"Invalid TX_LASER_MDIO 0x%x\", tx_en_mode);\n\t\tbreak;\n\t}\n}\n\nstatic void elink_sfp_set_transmitter(struct elink_params *params,\n\t\t\t\t struct elink_phy *phy, uint8_t tx_en)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tPMD_DRV_LOG(DEBUG, \"Setting SFP+ transmitter to %d\", tx_en);\n\tif (CHIP_IS_E3(sc))\n\t\telink_sfp_e3_set_transmitter(params, phy, tx_en);\n\telse\n\t\telink_sfp_e1e2_set_transmitter(params, phy, tx_en);\n}\n\nstatic elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,\n\t\t\t\t\t\t\tstruct elink_params\n\t\t\t\t\t\t\t*params,\n\t\t\t\t\t\t\tuint8_t dev_addr,\n\t\t\t\t\t\t\tuint16_t addr,\n\t\t\t\t\t\t\tuint8_t byte_cnt,\n\t\t\t\t\t\t\tuint8_t * o_buf,\n\t\t\t\t\t\t\t__rte_unused uint8_t\n\t\t\t\t\t\t\tis_init)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val = 0;\n\tuint16_t i;\n\tif (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {\n\t\tPMD_DRV_LOG(DEBUG, \"Reading from eeprom is limited to 0xf\");\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\t/* Set the read command byte count */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,\n\t\t\t (byte_cnt | (dev_addr << 8)));\n\n\t/* Set the read command address */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,\n\t\t\t addr);\n\n\t/* Activate read command */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,\n\t\t\t 0x2c0f);\n\n\t/* Wait up to 500us for command complete status */\n\tfor (i = 0; i < 100; i++) {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);\n\t\tif ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==\n\t\t MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)\n\t\t\tbreak;\n\t\tDELAY(5);\n\t}\n\n\tif ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=\n\t MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t \"Got bad status 0x%x when reading from SFP+ EEPROM\",\n\t\t\t (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\n\t/* Read the buffer */\n\tfor (i = 0; i < byte_cnt; i++) {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);\n\t\to_buf[i] =\n\t\t (uint8_t) (val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);\n\t}\n\n\tfor (i = 0; i < 100; i++) {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);\n\t\tif ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==\n\t\t MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)\n\t\t\treturn ELINK_STATUS_OK;\n\t\tDELAY(1000 * 1);\n\t}\n\treturn ELINK_STATUS_ERROR;\n}\n\nstatic void elink_warpcore_power_module(struct elink_params *params,\n\t\t\t\t\tuint8_t power)\n{\n\tuint32_t pin_cfg;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tpin_cfg = (REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_hw_config[params->port].\n\t\t\t\t e3_sfp_ctrl)) & PORT_HW_CFG_E3_PWR_DIS_MASK)\n\t >> PORT_HW_CFG_E3_PWR_DIS_SHIFT;\n\n\tif (pin_cfg == PIN_CFG_NA)\n\t\treturn;\n\tPMD_DRV_LOG(DEBUG, \"Setting SFP+ module power to %d using pin cfg %d\",\n\t\t power, pin_cfg);\n\t/* Low ==> corresponding SFP+ module is powered\n\t * high ==> the SFP+ module is powered down\n\t */\n\telink_set_cfg_pin(sc, pin_cfg, power ^ 1);\n}\n\nstatic elink_status_t elink_warpcore_read_sfp_module_eeprom(__rte_unused struct\n\t\t\t\t\t\t\t elink_phy *phy,\n\t\t\t\t\t\t\t struct elink_params\n\t\t\t\t\t\t\t *params,\n\t\t\t\t\t\t\t uint8_t dev_addr,\n\t\t\t\t\t\t\t uint16_t addr,\n\t\t\t\t\t\t\t uint8_t byte_cnt,\n\t\t\t\t\t\t\t uint8_t * o_buf,\n\t\t\t\t\t\t\t uint8_t is_init)\n{\n\telink_status_t rc = ELINK_STATUS_OK;\n\tuint8_t i, j = 0, cnt = 0;\n\tuint32_t data_array[4];\n\tuint16_t addr32;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tif (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t \"Reading from eeprom is limited to 16 bytes\");\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\n\t/* 4 byte aligned address */\n\taddr32 = addr & (~0x3);\n\tdo {\n\t\tif ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {\n\t\t\telink_warpcore_power_module(params, 0);\n\t\t\t/* Note that 100us are not enough here */\n\t\t\tDELAY(1000 * 1);\n\t\t\telink_warpcore_power_module(params, 1);\n\t\t}\n\t\trc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt,\n\t\t\t\t data_array);\n\t} while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));\n\n\tif (rc == ELINK_STATUS_OK) {\n\t\tfor (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {\n\t\t\to_buf[j] = *((uint8_t *) data_array + i);\n\t\t\tj++;\n\t\t}\n\t}\n\n\treturn rc;\n}\n\nstatic elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,\n\t\t\t\t\t\t\tstruct elink_params\n\t\t\t\t\t\t\t*params,\n\t\t\t\t\t\t\tuint8_t dev_addr,\n\t\t\t\t\t\t\tuint16_t addr,\n\t\t\t\t\t\t\tuint8_t byte_cnt,\n\t\t\t\t\t\t\tuint8_t * o_buf,\n\t\t\t\t\t\t\t__rte_unused uint8_t\n\t\t\t\t\t\t\tis_init)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val, i;\n\n\tif (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {\n\t\tPMD_DRV_LOG(DEBUG, \"Reading from eeprom is limited to 0xf\");\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\n\t/* Set 2-wire transfer rate of SFP+ module EEPROM\n\t * to 100Khz since some DACs(direct attached cables) do\n\t * not work at 400Khz.\n\t */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD,\n\t\t\t MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,\n\t\t\t ((dev_addr << 8) | 1));\n\n\t/* Need to read from 1.8000 to clear it */\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);\n\n\t/* Set the read command byte count */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD,\n\t\t\t MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,\n\t\t\t ((byte_cnt < 2) ? 2 : byte_cnt));\n\n\t/* Set the read command address */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD,\n\t\t\t MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, addr);\n\t/* Set the destination address */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD,\n\t\t\t 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);\n\n\t/* Activate read command */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD,\n\t\t\t MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 0x8002);\n\t/* Wait appropriate time for two-wire command to finish before\n\t * polling the status register\n\t */\n\tDELAY(1000 * 1);\n\n\t/* Wait up to 500us for command complete status */\n\tfor (i = 0; i < 100; i++) {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);\n\t\tif ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==\n\t\t MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)\n\t\t\tbreak;\n\t\tDELAY(5);\n\t}\n\n\tif ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=\n\t MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t \"Got bad status 0x%x when reading from SFP+ EEPROM\",\n\t\t\t (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));\n\t\treturn ELINK_STATUS_TIMEOUT;\n\t}\n\n\t/* Read the buffer */\n\tfor (i = 0; i < byte_cnt; i++) {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);\n\t\to_buf[i] =\n\t\t (uint8_t) (val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);\n\t}\n\n\tfor (i = 0; i < 100; i++) {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);\n\t\tif ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==\n\t\t MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)\n\t\t\treturn ELINK_STATUS_OK;\n\t\tDELAY(1000 * 1);\n\t}\n\n\treturn ELINK_STATUS_ERROR;\n}\n\nstatic elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,\n\t\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t\t uint8_t dev_addr,\n\t\t\t\t\t\t uint16_t addr,\n\t\t\t\t\t\t uint16_t byte_cnt,\n\t\t\t\t\t\t uint8_t * o_buf)\n{\n\telink_status_t rc = 0;\n\tuint8_t xfer_size;\n\tuint8_t *user_data = o_buf;\n\tread_sfp_module_eeprom_func_p read_func;\n\n\tif ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {\n\t\tPMD_DRV_LOG(DEBUG, \"invalid dev_addr 0x%x\", dev_addr);\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\n\tswitch (phy->type) {\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:\n\t\tread_func = elink_8726_read_sfp_module_eeprom;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:\n\t\tread_func = elink_8727_read_sfp_module_eeprom;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:\n\t\tread_func = elink_warpcore_read_sfp_module_eeprom;\n\t\tbreak;\n\tdefault:\n\t\treturn ELINK_OP_NOT_SUPPORTED;\n\t}\n\n\twhile (!rc && (byte_cnt > 0)) {\n\t\txfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?\n\t\t ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;\n\t\trc = read_func(phy, params, dev_addr, addr, xfer_size,\n\t\t\t user_data, 0);\n\t\tbyte_cnt -= xfer_size;\n\t\tuser_data += xfer_size;\n\t\taddr += xfer_size;\n\t}\n\treturn rc;\n}\n\nstatic elink_status_t elink_get_edc_mode(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t uint16_t * edc_mode)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t sync_offset = 0, phy_idx, media_types;\n\tuint8_t gport, val[2], check_limiting_mode = 0;\n\t*edc_mode = ELINK_EDC_MODE_LIMITING;\n\tphy->media_type = ELINK_ETH_PHY_UNSPECIFIED;\n\t/* First check for copper cable */\n\tif (elink_read_sfp_module_eeprom(phy,\n\t\t\t\t\t params,\n\t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n\t\t\t\t\t ELINK_SFP_EEPROM_CON_TYPE_ADDR,\n\t\t\t\t\t 2, (uint8_t *) val) != 0) {\n\t\tPMD_DRV_LOG(DEBUG, \"Failed to read from SFP+ module EEPROM\");\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\n\tswitch (val[0]) {\n\tcase ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:\n\t\t{\n\t\t\tuint8_t copper_module_type;\n\t\t\tphy->media_type = ELINK_ETH_PHY_DA_TWINAX;\n\t\t\t/* Check if its active cable (includes SFP+ module)\n\t\t\t * of passive cable\n\t\t\t */\n\t\t\tif (elink_read_sfp_module_eeprom(phy,\n\t\t\t\t\t\t\t params,\n\t\t\t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n\t\t\t\t\t\t\t ELINK_SFP_EEPROM_FC_TX_TECH_ADDR,\n\t\t\t\t\t\t\t 1,\n\t\t\t\t\t\t\t &copper_module_type) !=\n\t\t\t 0) {\n\t\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t\t \"Failed to read copper-cable-type\"\n\t\t\t\t\t \" from SFP+ EEPROM\");\n\t\t\t\treturn ELINK_STATUS_ERROR;\n\t\t\t}\n\n\t\t\tif (copper_module_type &\n\t\t\t ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {\n\t\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t\t \"Active Copper cable detected\");\n\t\t\t\tif (phy->type ==\n\t\t\t\t PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)\n\t\t\t\t\t*edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;\n\t\t\t\telse\n\t\t\t\t\tcheck_limiting_mode = 1;\n\t\t\t} else if (copper_module_type &\n\t\t\t\t ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE)\n\t\t\t{\n\t\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t\t \"Passive Copper cable detected\");\n\t\t\t\t*edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;\n\t\t\t} else {\n\t\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t\t \"Unknown copper-cable-type 0x%x !!!\",\n\t\t\t\t\t copper_module_type);\n\t\t\t\treturn ELINK_STATUS_ERROR;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\tcase ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:\n\tcase ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:\n\t\tcheck_limiting_mode = 1;\n\t\tif ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |\n\t\t\t ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |\n\t\t\t ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"1G SFP module detected\");\n\t\t\tgport = params->port;\n\t\t\tphy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;\n\t\t\tif (phy->req_line_speed != ELINK_SPEED_1000) {\n\t\t\t\tphy->req_line_speed = ELINK_SPEED_1000;\n\t\t\t\tif (!CHIP_IS_E1x(sc)) {\n\t\t\t\t\tgport = SC_PATH(sc) +\n\t\t\t\t\t (params->port << 1);\n\t\t\t\t}\n\t\t\t\telink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport);\t//\"Warning: Link speed was forced to 1000Mbps.\"\n\t\t\t\t// \" Current SFP module in port %d is not\"\n\t\t\t\t// \" compliant with 10G Ethernet\",\n\n\t\t\t}\n\t\t} else {\n\t\t\tint idx, cfg_idx = 0;\n\t\t\tPMD_DRV_LOG(DEBUG, \"10G Optic module detected\");\n\t\t\tfor (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {\n\t\t\t\tif (params->phy[idx].type == phy->type) {\n\t\t\t\t\tcfg_idx = ELINK_LINK_CONFIG_IDX(idx);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tphy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;\n\t\t\tphy->req_line_speed = params->req_line_speed[cfg_idx];\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(DEBUG, \"Unable to determine module type 0x%x !!!\",\n\t\t\t val[0]);\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\tsync_offset = params->shmem_base +\n\t offsetof(struct shmem_region,\n\t\t dev_info.port_hw_config[params->port].media_type);\n\tmedia_types = REG_RD(sc, sync_offset);\n\t/* Update media type for non-PMF sync */\n\tfor (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {\n\t\tif (&(params->phy[phy_idx]) == phy) {\n\t\t\tmedia_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<\n\t\t\t\t\t (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *\n\t\t\t\t\t phy_idx));\n\t\t\tmedia_types |=\n\t\t\t ((phy->\n\t\t\t media_type & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<\n\t\t\t (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));\n\t\t\tbreak;\n\t\t}\n\t}\n\tREG_WR(sc, sync_offset, media_types);\n\tif (check_limiting_mode) {\n\t\tuint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE];\n\t\tif (elink_read_sfp_module_eeprom(phy,\n\t\t\t\t\t\t params,\n\t\t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n\t\t\t\t\t\t ELINK_SFP_EEPROM_OPTIONS_ADDR,\n\t\t\t\t\t\t ELINK_SFP_EEPROM_OPTIONS_SIZE,\n\t\t\t\t\t\t options) != 0) {\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"Failed to read Option field from module EEPROM\");\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t\tif ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))\n\t\t\t*edc_mode = ELINK_EDC_MODE_LINEAR;\n\t\telse\n\t\t\t*edc_mode = ELINK_EDC_MODE_LIMITING;\n\t}\n\tPMD_DRV_LOG(DEBUG, \"EDC mode is set to 0x%x\", *edc_mode);\n\treturn ELINK_STATUS_OK;\n}\n\n/* This function read the relevant field from the module (SFP+), and verify it\n * is compliant with this board\n */\nstatic elink_status_t elink_verify_sfp_module(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t val, cmd;\n\tuint32_t fw_resp, fw_cmd_param;\n\tchar vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE + 1];\n\tchar vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE + 1];\n\tphy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;\n\tval = REG_RD(sc, params->shmem_base +\n\t\t offsetof(struct shmem_region,\n\t\t\t dev_info.port_feature_config[params->port].\n\t\t\t config));\n\tif ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==\n\t PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {\n\t\tPMD_DRV_LOG(DEBUG, \"NOT enforcing module verification\");\n\t\treturn ELINK_STATUS_OK;\n\t}\n\n\tif (params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {\n\t\t/* Use specific phy request */\n\t\tcmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;\n\t} else if (params->feature_config_flags &\n\t\t ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {\n\t\t/* Use first phy request only in case of non-dual media */\n\t\tif (ELINK_DUAL_MEDIA(params)) {\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"FW does not support OPT MDL verification\");\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t\tcmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;\n\t} else {\n\t\t/* No support in OPT MDL detection */\n\t\tPMD_DRV_LOG(DEBUG, \"FW does not support OPT MDL verification\");\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\n\tfw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);\n\tfw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);\n\tif (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {\n\t\tPMD_DRV_LOG(DEBUG, \"Approved module\");\n\t\treturn ELINK_STATUS_OK;\n\t}\n\n\t/* Format the warning message */\n\tif (elink_read_sfp_module_eeprom(phy,\n\t\t\t\t\t params,\n\t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n\t\t\t\t\t ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,\n\t\t\t\t\t ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,\n\t\t\t\t\t (uint8_t *) vendor_name))\n\t\tvendor_name[0] = '\\0';\n\telse\n\t\tvendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\\0';\n\tif (elink_read_sfp_module_eeprom(phy,\n\t\t\t\t\t params,\n\t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n\t\t\t\t\t ELINK_SFP_EEPROM_PART_NO_ADDR,\n\t\t\t\t\t ELINK_SFP_EEPROM_PART_NO_SIZE,\n\t\t\t\t\t (uint8_t *) vendor_pn))\n\t\tvendor_pn[0] = '\\0';\n\telse\n\t\tvendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\\0';\n\n\telink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn);\t// \"Warning: Unqualified SFP+ module detected,\"\n\t// \" Port %d from %s part number %s\",\n\n\tif ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=\n\t PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)\n\t\tphy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;\n\treturn ELINK_STATUS_ERROR;\n}\n\nstatic elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy\n\t\t\t\t\t\t\t *phy,\n\t\t\t\t\t\t\t struct elink_params\n\t\t\t\t\t\t\t *params)\n{\n\tuint8_t val;\n\telink_status_t rc;\n\tuint16_t timeout;\n\t/* Initialization time after hot-plug may take up to 300ms for\n\t * some phys type ( e.g. JDSU )\n\t */\n\n\tfor (timeout = 0; timeout < 60; timeout++) {\n\t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)\n\t\t\trc = elink_warpcore_read_sfp_module_eeprom(phy, params,\n\t\t\t\t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n\t\t\t\t\t\t\t\t 1, 1, &val,\n\t\t\t\t\t\t\t\t 1);\n\t\telse\n\t\t\trc = elink_read_sfp_module_eeprom(phy, params,\n\t\t\t\t\t\t\t ELINK_I2C_DEV_ADDR_A0,\n\t\t\t\t\t\t\t 1, 1, &val);\n\t\tif (rc == 0) {\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"SFP+ module initialization took %d ms\",\n\t\t\t\t timeout * 5);\n\t\t\treturn ELINK_STATUS_OK;\n\t\t}\n\t\tDELAY(1000 * 5);\n\t}\n\trc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,\n\t\t\t\t\t 1, 1, &val);\n\treturn rc;\n}\n\nstatic void elink_8727_power_module(struct bnx2x_softc *sc,\n\t\t\t\t struct elink_phy *phy, uint8_t is_power_up)\n{\n\t/* Make sure GPIOs are not using for LED mode */\n\tuint16_t val;\n\t/* In the GPIO register, bit 4 is use to determine if the GPIOs are\n\t * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for\n\t * output\n\t * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0\n\t * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1\n\t * where the 1st bit is the over-current(only input), and 2nd bit is\n\t * for power( only output )\n\t *\n\t * In case of NOC feature is disabled and power is up, set GPIO control\n\t * as input to enable listening of over-current indication\n\t */\n\tif (phy->flags & ELINK_FLAGS_NOC)\n\t\treturn;\n\tif (is_power_up)\n\t\tval = (1 << 4);\n\telse\n\t\t/* Set GPIO control to OUTPUT, and set the power bit\n\t\t * to according to the is_power_up\n\t\t */\n\t\tval = (1 << 1);\n\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);\n}\n\nstatic elink_status_t elink_8726_set_limiting_mode(struct bnx2x_softc *sc,\n\t\t\t\t\t\t struct elink_phy *phy,\n\t\t\t\t\t\t uint16_t edc_mode)\n{\n\tuint16_t cur_limiting_mode;\n\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD,\n\t\t\tMDIO_PMA_REG_ROM_VER2, &cur_limiting_mode);\n\tPMD_DRV_LOG(DEBUG, \"Current Limiting mode is 0x%x\", cur_limiting_mode);\n\n\tif (edc_mode == ELINK_EDC_MODE_LIMITING) {\n\t\tPMD_DRV_LOG(DEBUG, \"Setting LIMITING MODE\");\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_ROM_VER2,\n\t\t\t\t ELINK_EDC_MODE_LIMITING);\n\t} else {\t\t/* LRM mode ( default ) */\n\n\t\tPMD_DRV_LOG(DEBUG, \"Setting LRM MODE\");\n\n\t\t/* Changing to LRM mode takes quite few seconds. So do it only\n\t\t * if current mode is limiting (default is LRM)\n\t\t */\n\t\tif (cur_limiting_mode != ELINK_EDC_MODE_LIMITING)\n\t\t\treturn ELINK_STATUS_OK;\n\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, 0x128);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_MISC_CTRL0, 0x4008);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_LRM_MODE, 0xaaaa);\n\t}\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_8727_set_limiting_mode(struct bnx2x_softc *sc,\n\t\t\t\t\t\t struct elink_phy *phy,\n\t\t\t\t\t\t uint16_t edc_mode)\n{\n\tuint16_t phy_identifier;\n\tuint16_t rom_ver2_val;\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD,\n\t\t\tMDIO_PMA_REG_PHY_IDENTIFIER, &phy_identifier);\n\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD,\n\t\t\t MDIO_PMA_REG_PHY_IDENTIFIER,\n\t\t\t (phy_identifier & ~(1 << 9)));\n\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER2, &rom_ver2_val);\n\t/* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD,\n\t\t\t MDIO_PMA_REG_ROM_VER2,\n\t\t\t (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));\n\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD,\n\t\t\t MDIO_PMA_REG_PHY_IDENTIFIER,\n\t\t\t (phy_identifier | (1 << 9)));\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_8727_specific_func(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t uint32_t action)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val;\n\tswitch (action) {\n\tcase ELINK_DISABLE_TX:\n\t\telink_sfp_set_transmitter(params, phy, 0);\n\t\tbreak;\n\tcase ELINK_ENABLE_TX:\n\t\tif (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))\n\t\t\telink_sfp_set_transmitter(params, phy, 1);\n\t\tbreak;\n\tcase ELINK_PHY_INIT:\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,\n\t\t\t\t (1 << 2) | (1 << 5));\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);\n\t\t/* Make MOD_ABS give interrupt on change */\n\t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);\n\t\tval |= (1 << 12);\n\t\tif (phy->flags & ELINK_FLAGS_NOC)\n\t\t\tval |= (3 << 5);\n\t\t/* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0\n\t\t * status which reflect SFP+ module over-current\n\t\t */\n\t\tif (!(phy->flags & ELINK_FLAGS_NOC))\n\t\t\tval &= 0xff8f;\t/* Reset bits 4-6 */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,\n\t\t\t\t val);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(DEBUG, \"Function 0x%x not supported by 8727\",\n\t\t\t action);\n\t\treturn;\n\t}\n}\n\nstatic void elink_set_e1e2_module_fault_led(struct elink_params *params,\n\t\t\t\t\t uint8_t gpio_mode)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tuint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +\n\t\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t\t dev_info.\n\t\t\t\t\t\t port_hw_config[params->port].\n\t\t\t\t\t\t sfp_ctrl)) &\n\t PORT_HW_CFG_FAULT_MODULE_LED_MASK;\n\tswitch (fault_led_gpio) {\n\tcase PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:\n\t\treturn;\n\tcase PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:\n\tcase PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:\n\tcase PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:\n\tcase PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:\n\t\t{\n\t\t\tuint8_t gpio_port = elink_get_gpio_port(params);\n\t\t\tuint16_t gpio_pin = fault_led_gpio -\n\t\t\t PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;\n\t\t\tPMD_DRV_LOG(DEBUG, \"Set fault module-detected led \"\n\t\t\t\t \"pin %x port %x mode %x\",\n\t\t\t\t gpio_pin, gpio_port, gpio_mode);\n\t\t\telink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(DEBUG, \"Error: Invalid fault led mode 0x%x\",\n\t\t\t fault_led_gpio);\n\t}\n}\n\nstatic void elink_set_e3_module_fault_led(struct elink_params *params,\n\t\t\t\t\t uint8_t gpio_mode)\n{\n\tuint32_t pin_cfg;\n\tuint8_t port = params->port;\n\tstruct bnx2x_softc *sc = params->sc;\n\tpin_cfg = (REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_hw_config[port].e3_sfp_ctrl)) &\n\t\t PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>\n\t PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;\n\tPMD_DRV_LOG(DEBUG, \"Setting Fault LED to %d using pin cfg %d\",\n\t\t gpio_mode, pin_cfg);\n\telink_set_cfg_pin(sc, pin_cfg, gpio_mode);\n}\n\nstatic void elink_set_sfp_module_fault_led(struct elink_params *params,\n\t\t\t\t\t uint8_t gpio_mode)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tPMD_DRV_LOG(DEBUG, \"Setting SFP+ module fault LED to %d\", gpio_mode);\n\tif (CHIP_IS_E3(sc)) {\n\t\t/* Low ==> if SFP+ module is supported otherwise\n\t\t * High ==> if SFP+ module is not on the approved vendor list\n\t\t */\n\t\telink_set_e3_module_fault_led(params, gpio_mode);\n\t} else\n\t\telink_set_e1e2_module_fault_led(params, gpio_mode);\n}\n\nstatic void elink_warpcore_hw_reset(__rte_unused struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\telink_warpcore_power_module(params, 0);\n\t/* Put Warpcore in low power mode */\n\tREG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);\n\n\t/* Put LCPLL in low power mode */\n\tREG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1);\n\tREG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);\n\tREG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);\n}\n\nstatic void elink_power_sfp_module(struct elink_params *params,\n\t\t\t\t struct elink_phy *phy, uint8_t power)\n{\n\tPMD_DRV_LOG(DEBUG, \"Setting SFP+ power to %x\", power);\n\n\tswitch (phy->type) {\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:\n\t\telink_8727_power_module(params->sc, phy, power);\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:\n\t\telink_warpcore_power_module(params, power);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nstatic void elink_warpcore_set_limiting_mode(struct elink_params *params,\n\t\t\t\t\t struct elink_phy *phy,\n\t\t\t\t\t uint16_t edc_mode)\n{\n\tuint16_t val = 0;\n\tuint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\tuint8_t lane = elink_get_warpcore_lane(params);\n\t/* This is a global register which controls all lanes */\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);\n\tval &= ~(0xf << (lane << 2));\n\n\tswitch (edc_mode) {\n\tcase ELINK_EDC_MODE_LINEAR:\n\tcase ELINK_EDC_MODE_LIMITING:\n\t\tmode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;\n\t\tbreak;\n\tcase ELINK_EDC_MODE_PASSIVE_DAC:\n\tcase ELINK_EDC_MODE_ACTIVE_DAC:\n\t\tmode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tval |= (mode << (lane << 2));\n\telink_cl45_write(sc, phy, MDIO_WC_DEVAD,\n\t\t\t MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);\n\t/* A must read */\n\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\tMDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);\n\n\t/* Restart microcode to re-read the new mode */\n\telink_warpcore_reset_lane(sc, phy, 1);\n\telink_warpcore_reset_lane(sc, phy, 0);\n\n}\n\nstatic void elink_set_limiting_mode(struct elink_params *params,\n\t\t\t\t struct elink_phy *phy, uint16_t edc_mode)\n{\n\tswitch (phy->type) {\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:\n\t\telink_8726_set_limiting_mode(params->sc, phy, edc_mode);\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:\n\t\telink_8727_set_limiting_mode(params->sc, phy, edc_mode);\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:\n\t\telink_warpcore_set_limiting_mode(params, phy, edc_mode);\n\t\tbreak;\n\t}\n}\n\nstatic elink_status_t elink_sfp_module_detection(struct elink_phy *phy,\n\t\t\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t edc_mode;\n\telink_status_t rc = ELINK_STATUS_OK;\n\n\tuint32_t val = REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_feature_config[params->\n\t\t\t\t\t\t\t\t port].\n\t\t\t\t config));\n\t/* Enabled transmitter by default */\n\telink_sfp_set_transmitter(params, phy, 1);\n\tPMD_DRV_LOG(DEBUG, \"SFP+ module plugged in/out detected on port %d\",\n\t\t params->port);\n\t/* Power up module */\n\telink_power_sfp_module(params, phy, 1);\n\tif (elink_get_edc_mode(phy, params, &edc_mode) != 0) {\n\t\tPMD_DRV_LOG(DEBUG, \"Failed to get valid module type\");\n\t\treturn ELINK_STATUS_ERROR;\n\t} else if (elink_verify_sfp_module(phy, params) != 0) {\n\t\t/* Check SFP+ module compatibility */\n\t\tPMD_DRV_LOG(DEBUG, \"Module verification failed!!\");\n\t\trc = ELINK_STATUS_ERROR;\n\t\t/* Turn on fault module-detected led */\n\t\telink_set_sfp_module_fault_led(params,\n\t\t\t\t\t MISC_REGISTERS_GPIO_HIGH);\n\n\t\t/* Check if need to power down the SFP+ module */\n\t\tif ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==\n\t\t PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Shutdown SFP+ module!!\");\n\t\t\telink_power_sfp_module(params, phy, 0);\n\t\t\treturn rc;\n\t\t}\n\t} else {\n\t\t/* Turn off fault module-detected led */\n\t\telink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);\n\t}\n\n\t/* Check and set limiting mode / LRM mode on 8726. On 8727 it\n\t * is done automatically\n\t */\n\telink_set_limiting_mode(params, phy, edc_mode);\n\n\t/* Disable transmit for this module if the module is not approved, and\n\t * laser needs to be disabled.\n\t */\n\tif ((rc != 0) &&\n\t ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==\n\t PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))\n\t\telink_sfp_set_transmitter(params, phy, 0);\n\n\treturn rc;\n}\n\nvoid elink_handle_module_detect_int(struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tstruct elink_phy *phy;\n\tuint32_t gpio_val;\n\tuint8_t gpio_num, gpio_port;\n\tif (CHIP_IS_E3(sc)) {\n\t\tphy = ¶ms->phy[ELINK_INT_PHY];\n\t\t/* Always enable TX laser,will be disabled in case of fault */\n\t\telink_sfp_set_transmitter(params, phy, 1);\n\t} else {\n\t\tphy = ¶ms->phy[ELINK_EXT_PHY1];\n\t}\n\tif (elink_get_mod_abs_int_cfg(sc, params->shmem_base,\n\t\t\t\t params->port, &gpio_num, &gpio_port) ==\n\t ELINK_STATUS_ERROR) {\n\t\tPMD_DRV_LOG(DEBUG, \"Failed to get MOD_ABS interrupt config\");\n\t\treturn;\n\t}\n\n\t/* Set valid module led off */\n\telink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);\n\n\t/* Get current gpio val reflecting module plugged in / out */\n\tgpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);\n\n\t/* Call the handling function in case module is detected */\n\tif (gpio_val == 0) {\n\t\telink_set_mdio_emac_per_phy(sc, params);\n\t\telink_set_aer_mmd(params, phy);\n\n\t\telink_power_sfp_module(params, phy, 1);\n\t\telink_cb_gpio_int_write(sc, gpio_num,\n\t\t\t\t\tMISC_REGISTERS_GPIO_INT_OUTPUT_CLR,\n\t\t\t\t\tgpio_port);\n\t\tif (elink_wait_for_sfp_module_initialized(phy, params) == 0) {\n\t\t\telink_sfp_module_detection(phy, params);\n\t\t\tif (CHIP_IS_E3(sc)) {\n\t\t\t\tuint16_t rx_tx_in_reset;\n\t\t\t\t/* In case WC is out of reset, reconfigure the\n\t\t\t\t * link speed while taking into account 1G\n\t\t\t\t * module limitation.\n\t\t\t\t */\n\t\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\t\tMDIO_WC_DEVAD,\n\t\t\t\t\t\tMDIO_WC_REG_DIGITAL5_MISC6,\n\t\t\t\t\t\t&rx_tx_in_reset);\n\t\t\t\tif ((!rx_tx_in_reset) &&\n\t\t\t\t (params->link_flags &\n\t\t\t\t ELINK_PHY_INITIALIZED)) {\n\t\t\t\t\telink_warpcore_reset_lane(sc, phy, 1);\n\t\t\t\t\telink_warpcore_config_sfi(phy, params);\n\t\t\t\t\telink_warpcore_reset_lane(sc, phy, 0);\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tPMD_DRV_LOG(DEBUG, \"SFP+ module is not initialized\");\n\t\t}\n\t} else {\n\t\telink_cb_gpio_int_write(sc, gpio_num,\n\t\t\t\t\tMISC_REGISTERS_GPIO_INT_OUTPUT_SET,\n\t\t\t\t\tgpio_port);\n\t\t/* Module was plugged out.\n\t\t * Disable transmit for this module\n\t\t */\n\t\tphy->media_type = ELINK_ETH_PHY_NOT_PRESENT;\n\t}\n}\n\n/******************************************************************/\n/*\t\tUsed by 8706 and 8727 */\n/******************************************************************/\nstatic void elink_sfp_mask_fault(struct bnx2x_softc *sc,\n\t\t\t\t struct elink_phy *phy,\n\t\t\t\t uint16_t alarm_status_offset,\n\t\t\t\t uint16_t alarm_ctrl_offset)\n{\n\tuint16_t alarm_status, val;\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, alarm_status_offset, &alarm_status);\n\t/* Mask or enable the fault event. */\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);\n\tif (alarm_status & (1 << 0))\n\t\tval &= ~(1 << 0);\n\telse\n\t\tval |= (1 << 0);\n\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);\n}\n\n/******************************************************************/\n/*\t\tcommon BNX2X8706/BNX2X8726 PHY SECTION\t\t */\n/******************************************************************/\nstatic uint8_t elink_8706_8726_read_status(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tuint8_t link_up = 0;\n\tuint16_t val1, val2, rx_sd, pcs_status;\n\tstruct bnx2x_softc *sc = params->sc;\n\tPMD_DRV_LOG(DEBUG, \"XGXS 8706/8726\");\n\t/* Clear RX Alarm */\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);\n\n\telink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,\n\t\t\t MDIO_PMA_LASI_TXCTRL);\n\n\t/* Clear LASI indication */\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);\n\tPMD_DRV_LOG(DEBUG, \"8706/8726 LASI status 0x%x--> 0x%x\", val1, val2);\n\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);\n\n\tPMD_DRV_LOG(DEBUG, \"8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps\"\n\t\t \" link_status 0x%x\", rx_sd, pcs_status, val2);\n\t/* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status\n\t * are set, or if the autoneg bit 1 is set\n\t */\n\tlink_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1 << 1)));\n\tif (link_up) {\n\t\tif (val2 & (1 << 1))\n\t\t\tvars->line_speed = ELINK_SPEED_1000;\n\t\telse\n\t\t\tvars->line_speed = ELINK_SPEED_10000;\n\t\telink_ext_phy_resolve_fc(phy, params, vars);\n\t\tvars->duplex = DUPLEX_FULL;\n\t}\n\n\t/* Capture 10G link fault. Read twice to clear stale value. */\n\tif (vars->line_speed == ELINK_SPEED_10000) {\n\t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_LASI_TXSTAT, &val1);\n\t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_LASI_TXSTAT, &val1);\n\t\tif (val1 & (1 << 0))\n\t\t\tvars->fault_detected = 1;\n\t}\n\n\treturn link_up;\n}\n\n/******************************************************************/\n/*\t\t\tBNX2X8706 PHY SECTION\t\t\t */\n/******************************************************************/\nstatic uint8_t elink_8706_config_init(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t __rte_unused struct elink_vars *vars)\n{\n\tuint32_t tx_en_mode;\n\tuint16_t cnt, val, tmp1;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);\n\t/* HW reset */\n\telink_ext_phy_hw_reset(sc, params->port);\n\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);\n\telink_wait_reset_complete(sc, phy, params);\n\n\t/* Wait until fw is loaded */\n\tfor (cnt = 0; cnt < 100; cnt++) {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);\n\t\tif (val)\n\t\t\tbreak;\n\t\tDELAY(1000 * 10);\n\t}\n\tPMD_DRV_LOG(DEBUG, \"XGXS 8706 is initialized after %d ms\", cnt);\n\tif ((params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {\n\t\tuint8_t i;\n\t\tuint16_t reg;\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\treg = MDIO_XS_8706_REG_BANK_RX0 +\n\t\t\t i * (MDIO_XS_8706_REG_BANK_RX1 -\n\t\t\t\t MDIO_XS_8706_REG_BANK_RX0);\n\t\t\telink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);\n\t\t\t/* Clear first 3 bits of the control */\n\t\t\tval &= ~0x7;\n\t\t\t/* Set control bits according to configuration */\n\t\t\tval |= (phy->rx_preemphasis[i] & 0x7);\n\t\t\tPMD_DRV_LOG(DEBUG, \"Setting RX Equalizer to BNX2X8706\"\n\t\t\t\t \" reg 0x%x <-- val 0x%x\", reg, val);\n\t\t\telink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);\n\t\t}\n\t}\n\t/* Force speed */\n\tif (phy->req_line_speed == ELINK_SPEED_10000) {\n\t\tPMD_DRV_LOG(DEBUG, \"XGXS 8706 force 10Gbps\");\n\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_DIGITAL_CTRL, 0x400);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 0);\n\t\t/* Arm LASI for link and Tx fault. */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);\n\t} else {\n\t\t/* Force 1Gbps using autoneg with 1G advertisement */\n\n\t\t/* Allow CL37 through CL73 */\n\t\tPMD_DRV_LOG(DEBUG, \"XGXS 8706 AutoNeg\");\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);\n\n\t\t/* Enable Full-Duplex advertisement on CL37 */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);\n\t\t/* Enable CL37 AN */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);\n\t\t/* 1G support */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1 << 5));\n\n\t\t/* Enable clause 73 AN */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x0400);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);\n\t}\n\telink_save_bnx2x_spirom_ver(sc, phy, params->port);\n\n\t/* If TX Laser is controlled by GPIO_0, do not let PHY go into low\n\t * power mode, if TX Laser is disabled\n\t */\n\n\ttx_en_mode = REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_hw_config[params->port].\n\t\t\t\t sfp_ctrl))\n\t& PORT_HW_CFG_TX_LASER_MASK;\n\n\tif (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {\n\t\tPMD_DRV_LOG(DEBUG, \"Enabling TXONOFF_PWRDN_DIS\");\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,\n\t\t\t\t&tmp1);\n\t\ttmp1 |= 0x1;\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL,\n\t\t\t\t tmp1);\n\t}\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_8706_read_status(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\treturn elink_8706_8726_read_status(phy, params, vars);\n}\n\n/******************************************************************/\n/*\t\t\tBNX2X8726 PHY SECTION\t\t\t */\n/******************************************************************/\nstatic void elink_8726_config_loopback(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tPMD_DRV_LOG(DEBUG, \"PMA/PMD ext_phy_loopback: 8726\");\n\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);\n}\n\nstatic void elink_8726_external_rom_boot(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\t/* Need to wait 100ms after reset */\n\tDELAY(1000 * 100);\n\n\t/* Micro controller re-boot */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);\n\n\t/* Set soft reset */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD,\n\t\t\t MDIO_PMA_REG_GEN_CTRL,\n\t\t\t MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);\n\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0001);\n\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD,\n\t\t\t MDIO_PMA_REG_GEN_CTRL,\n\t\t\t MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);\n\n\t/* Wait for 150ms for microcode load */\n\tDELAY(1000 * 150);\n\n\t/* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL1, 0x0000);\n\n\tDELAY(1000 * 200);\n\telink_save_bnx2x_spirom_ver(sc, phy, params->port);\n}\n\nstatic uint8_t elink_8726_read_status(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val1;\n\tuint8_t link_up = elink_8706_8726_read_status(phy, params, vars);\n\tif (link_up) {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,\n\t\t\t\t&val1);\n\t\tif (val1 & (1 << 15)) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Tx is disabled\");\n\t\t\tlink_up = 0;\n\t\t\tvars->line_speed = 0;\n\t\t}\n\t}\n\treturn link_up;\n}\n\nstatic elink_status_t elink_8726_config_init(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tPMD_DRV_LOG(DEBUG, \"Initializing BNX2X8726\");\n\n\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);\n\telink_wait_reset_complete(sc, phy, params);\n\n\telink_8726_external_rom_boot(phy, params);\n\n\t/* Need to call module detected on initialization since the module\n\t * detection triggered by actual module insertion might occur before\n\t * driver is loaded, and when driver is loaded, it reset all\n\t * registers, including the transmitter\n\t */\n\telink_sfp_module_detection(phy, params);\n\n\tif (phy->req_line_speed == ELINK_SPEED_1000) {\n\t\tPMD_DRV_LOG(DEBUG, \"Setting 1G force\");\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);\n\t} else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n\t\t (phy->speed_cap_mask &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&\n\t\t ((phy->speed_cap_mask &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {\n\t\tPMD_DRV_LOG(DEBUG, \"Setting 1G clause37\");\n\t\t/* Set Flow control */\n\t\telink_ext_phy_set_pause(params, phy, vars);\n\t\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);\n\t\t/* Enable RX-ALARM control to receive interrupt for 1G speed\n\t\t * change\n\t\t */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 0x400);\n\n\t} else {\t\t/* Default 10G. Set only LASI control */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);\n\t}\n\n\t/* Set TX PreEmphasis if needed */\n\tif ((params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t \"Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\",\n\t\t\t phy->tx_preemphasis[0], phy->tx_preemphasis[1]);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_8726_TX_CTRL1,\n\t\t\t\t phy->tx_preemphasis[0]);\n\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_8726_TX_CTRL2,\n\t\t\t\t phy->tx_preemphasis[1]);\n\t}\n\n\treturn ELINK_STATUS_OK;\n\n}\n\nstatic void elink_8726_link_reset(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tPMD_DRV_LOG(DEBUG, \"elink_8726_link_reset port %d\", params->port);\n\t/* Set serial boot control for external load */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);\n}\n\n/******************************************************************/\n/*\t\t\tBNX2X8727 PHY SECTION\t\t\t */\n/******************************************************************/\n\nstatic void elink_8727_set_link_led(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params, uint8_t mode)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t led_mode_bitmask = 0;\n\tuint16_t gpio_pins_bitmask = 0;\n\tuint16_t val;\n\t/* Only NOC flavor requires to set the LED specifically */\n\tif (!(phy->flags & ELINK_FLAGS_NOC))\n\t\treturn;\n\tswitch (mode) {\n\tcase ELINK_LED_MODE_FRONT_PANEL_OFF:\n\tcase ELINK_LED_MODE_OFF:\n\t\tled_mode_bitmask = 0;\n\t\tgpio_pins_bitmask = 0x03;\n\t\tbreak;\n\tcase ELINK_LED_MODE_ON:\n\t\tled_mode_bitmask = 0;\n\t\tgpio_pins_bitmask = 0x02;\n\t\tbreak;\n\tcase ELINK_LED_MODE_OPER:\n\t\tled_mode_bitmask = 0x60;\n\t\tgpio_pins_bitmask = 0x11;\n\t\tbreak;\n\t}\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, &val);\n\tval &= 0xff8f;\n\tval |= led_mode_bitmask;\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, &val);\n\tval &= 0xffe0;\n\tval |= gpio_pins_bitmask;\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, val);\n}\n\nstatic void elink_8727_hw_reset(__rte_unused struct elink_phy *phy,\n\t\t\t\tstruct elink_params *params)\n{\n\tuint32_t swap_val, swap_override;\n\tuint8_t port;\n\t/* The PHY reset is controlled by GPIO 1. Fake the port number\n\t * to cancel the swap done in set_gpio()\n\t */\n\tstruct bnx2x_softc *sc = params->sc;\n\tswap_val = REG_RD(sc, NIG_REG_PORT_SWAP);\n\tswap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);\n\tport = (swap_val && swap_override) ^ 1;\n\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, port);\n}\n\nstatic void elink_8727_config_speed(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t tmp1, val;\n\t/* Set option 1G speed */\n\tif ((phy->req_line_speed == ELINK_SPEED_1000) ||\n\t (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {\n\t\tPMD_DRV_LOG(DEBUG, \"Setting 1G force\");\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);\n\t\tPMD_DRV_LOG(DEBUG, \"1.7 = 0x%x\", tmp1);\n\t\t/* Power down the XAUI until link is up in case of dual-media\n\t\t * and 1G\n\t\t */\n\t\tif (ELINK_DUAL_MEDIA(params)) {\n\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\t\tMDIO_PMA_REG_8727_PCS_GP, &val);\n\t\t\tval |= (3 << 10);\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8727_PCS_GP, val);\n\t\t}\n\t} else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n\t\t ((phy->speed_cap_mask &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&\n\t\t ((phy->speed_cap_mask &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {\n\n\t\tPMD_DRV_LOG(DEBUG, \"Setting 1G clause37\");\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);\n\t} else {\n\t\t/* Since the 8727 has only single reset pin, need to set the 10G\n\t\t * registers although it is default\n\t\t */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,\n\t\t\t\t 0x0020);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,\n\t\t\t\t 0x0008);\n\t}\n}\n\nstatic elink_status_t elink_8727_config_init(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t __rte_unused struct elink_vars\n\t\t\t\t\t *vars)\n{\n\tuint32_t tx_en_mode;\n\tuint16_t tmp1, mod_abs, tmp2;\n\tstruct bnx2x_softc *sc = params->sc;\n\t/* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */\n\n\telink_wait_reset_complete(sc, phy, params);\n\n\tPMD_DRV_LOG(DEBUG, \"Initializing BNX2X8727\");\n\n\telink_8727_specific_func(phy, params, ELINK_PHY_INIT);\n\t/* Initially configure MOD_ABS to interrupt when module is\n\t * presence( bit 8)\n\t */\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);\n\t/* Set EDC off by setting OPTXLOS signal input to low (bit 9).\n\t * When the EDC is off it locks onto a reference clock and avoids\n\t * becoming 'lost'\n\t */\n\tmod_abs &= ~(1 << 8);\n\tif (!(phy->flags & ELINK_FLAGS_NOC))\n\t\tmod_abs &= ~(1 << 9);\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);\n\n\t/* Enable/Disable PHY transmitter output */\n\telink_set_disable_pmd_transmit(params, phy, 0);\n\n\telink_8727_power_module(sc, phy, 1);\n\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);\n\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);\n\n\telink_8727_config_speed(phy, params);\n\n\t/* Set TX PreEmphasis if needed */\n\tif ((params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {\n\t\tPMD_DRV_LOG(DEBUG, \"Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\",\n\t\t\t phy->tx_preemphasis[0], phy->tx_preemphasis[1]);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,\n\t\t\t\t phy->tx_preemphasis[0]);\n\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,\n\t\t\t\t phy->tx_preemphasis[1]);\n\t}\n\n\t/* If TX Laser is controlled by GPIO_0, do not let PHY go into low\n\t * power mode, if TX Laser is disabled\n\t */\n\ttx_en_mode = REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_hw_config[params->port].\n\t\t\t\t sfp_ctrl))\n\t& PORT_HW_CFG_TX_LASER_MASK;\n\n\tif (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {\n\n\t\tPMD_DRV_LOG(DEBUG, \"Enabling TXONOFF_PWRDN_DIS\");\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,\n\t\t\t\t&tmp2);\n\t\ttmp2 |= 0x1000;\n\t\ttmp2 &= 0xFFEF;\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG,\n\t\t\t\t tmp2);\n\t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_PHY_IDENTIFIER, &tmp2);\n\t\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_PHY_IDENTIFIER, (tmp2 & 0x7fff));\n\t}\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_8727_handle_mod_abs(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t mod_abs, rx_alarm_status;\n\tuint32_t val = REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_feature_config[params->\n\t\t\t\t\t\t\t\t port].config));\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,\n\t\t\t&mod_abs);\n\tif (mod_abs & (1 << 8)) {\n\n\t\t/* Module is absent */\n\t\tPMD_DRV_LOG(DEBUG, \"MOD_ABS indication show module is absent\");\n\t\tphy->media_type = ELINK_ETH_PHY_NOT_PRESENT;\n\t\t/* 1. Set mod_abs to detect next module\n\t\t * presence event\n\t\t * 2. Set EDC off by setting OPTXLOS signal input to low\n\t\t * (bit 9).\n\t\t * When the EDC is off it locks onto a reference clock and\n\t\t * avoids becoming 'lost'.\n\t\t */\n\t\tmod_abs &= ~(1 << 8);\n\t\tif (!(phy->flags & ELINK_FLAGS_NOC))\n\t\t\tmod_abs &= ~(1 << 9);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);\n\n\t\t/* Clear RX alarm since it stays up as long as\n\t\t * the mod_abs wasn't changed\n\t\t */\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_LASI_RXSTAT, &rx_alarm_status);\n\n\t} else {\n\t\t/* Module is present */\n\t\tPMD_DRV_LOG(DEBUG, \"MOD_ABS indication show module is present\");\n\t\t/* First disable transmitter, and if the module is ok, the\n\t\t * module_detection will enable it\n\t\t * 1. Set mod_abs to detect next module absent event ( bit 8)\n\t\t * 2. Restore the default polarity of the OPRXLOS signal and\n\t\t * this signal will then correctly indicate the presence or\n\t\t * absence of the Rx signal. (bit 9)\n\t\t */\n\t\tmod_abs |= (1 << 8);\n\t\tif (!(phy->flags & ELINK_FLAGS_NOC))\n\t\t\tmod_abs |= (1 << 9);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);\n\n\t\t/* Clear RX alarm since it stays up as long as the mod_abs\n\t\t * wasn't changed. This is need to be done before calling the\n\t\t * module detection, otherwise it will clear* the link update\n\t\t * alarm\n\t\t */\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_LASI_RXSTAT, &rx_alarm_status);\n\n\t\tif ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==\n\t\t PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)\n\t\t\telink_sfp_set_transmitter(params, phy, 0);\n\n\t\tif (elink_wait_for_sfp_module_initialized(phy, params) == 0) {\n\t\t\telink_sfp_module_detection(phy, params);\n\t\t} else {\n\t\t\tPMD_DRV_LOG(DEBUG, \"SFP+ module is not initialized\");\n\t\t}\n\n\t\t/* Reconfigure link speed based on module type limitations */\n\t\telink_8727_config_speed(phy, params);\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"8727 RX_ALARM_STATUS 0x%x\", rx_alarm_status);\n\t/* No need to check link status in case of module plugged in/out */\n}\n\nstatic uint8_t elink_8727_read_status(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t link_up = 0, oc_port = params->port;\n\tuint16_t link_status = 0;\n\tuint16_t rx_alarm_status, lasi_ctrl, val1;\n\n\t/* If PHY is not initialized, do not check link status */\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, &lasi_ctrl);\n\tif (!lasi_ctrl)\n\t\treturn 0;\n\n\t/* Check the LASI on Rx */\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);\n\tvars->line_speed = 0;\n\tPMD_DRV_LOG(DEBUG, \"8727 RX_ALARM_STATUS 0x%x\", rx_alarm_status);\n\n\telink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,\n\t\t\t MDIO_PMA_LASI_TXCTRL);\n\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);\n\n\tPMD_DRV_LOG(DEBUG, \"8727 LASI status 0x%x\", val1);\n\n\t/* Clear MSG-OUT */\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);\n\n\t/* If a module is present and there is need to check\n\t * for over current\n\t */\n\tif (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1 << 5))) {\n\t\t/* Check over-current using 8727 GPIO0 input */\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,\n\t\t\t\t&val1);\n\n\t\tif ((val1 & (1 << 8)) == 0) {\n\t\t\tif (!CHIP_IS_E1x(sc))\n\t\t\t\toc_port = SC_PATH(sc) + (params->port << 1);\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"8727 Power fault has been detected on port %d\",\n\t\t\t\t oc_port);\n\t\t\telink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port);\t//\"Error: Power fault on Port %d has \"\n\t\t\t// \"been detected and the power to \"\n\t\t\t// \"that SFP+ module has been removed \"\n\t\t\t// \"to prevent failure of the card. \"\n\t\t\t// \"Please remove the SFP+ module and \"\n\t\t\t// \"restart the system to clear this \"\n\t\t\t// \"error.\",\n\t\t\t/* Disable all RX_ALARMs except for mod_abs */\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_LASI_RXCTRL, (1 << 5));\n\n\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\t\tMDIO_PMA_REG_PHY_IDENTIFIER, &val1);\n\t\t\t/* Wait for module_absent_event */\n\t\t\tval1 |= (1 << 8);\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_PHY_IDENTIFIER, val1);\n\t\t\t/* Clear RX alarm */\n\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\t\tMDIO_PMA_LASI_RXSTAT, &rx_alarm_status);\n\t\t\telink_8727_power_module(params->sc, phy, 0);\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Over current check */\n\t/* When module absent bit is set, check module */\n\tif (rx_alarm_status & (1 << 5)) {\n\t\telink_8727_handle_mod_abs(phy, params);\n\t\t/* Enable all mod_abs and link detection bits */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,\n\t\t\t\t ((1 << 5) | (1 << 2)));\n\t}\n\n\tif (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {\n\t\tPMD_DRV_LOG(DEBUG, \"Enabling 8727 TX laser\");\n\t\telink_sfp_set_transmitter(params, phy, 1);\n\t} else {\n\t\tPMD_DRV_LOG(DEBUG, \"Tx is disabled\");\n\t\treturn 0;\n\t}\n\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD,\n\t\t\tMDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);\n\n\t/* Bits 0..2 --> speed detected,\n\t * Bits 13..15--> link is down\n\t */\n\tif ((link_status & (1 << 2)) && (!(link_status & (1 << 15)))) {\n\t\tlink_up = 1;\n\t\tvars->line_speed = ELINK_SPEED_10000;\n\t\tPMD_DRV_LOG(DEBUG, \"port %x: External link up in 10G\",\n\t\t\t params->port);\n\t} else if ((link_status & (1 << 0)) && (!(link_status & (1 << 13)))) {\n\t\tlink_up = 1;\n\t\tvars->line_speed = ELINK_SPEED_1000;\n\t\tPMD_DRV_LOG(DEBUG, \"port %x: External link up in 1G\",\n\t\t\t params->port);\n\t} else {\n\t\tlink_up = 0;\n\t\tPMD_DRV_LOG(DEBUG, \"port %x: External link is down\",\n\t\t\t params->port);\n\t}\n\n\t/* Capture 10G link fault. */\n\tif (vars->line_speed == ELINK_SPEED_10000) {\n\t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_LASI_TXSTAT, &val1);\n\n\t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_LASI_TXSTAT, &val1);\n\n\t\tif (val1 & (1 << 0)) {\n\t\t\tvars->fault_detected = 1;\n\t\t}\n\t}\n\n\tif (link_up) {\n\t\telink_ext_phy_resolve_fc(phy, params, vars);\n\t\tvars->duplex = DUPLEX_FULL;\n\t\tPMD_DRV_LOG(DEBUG, \"duplex = 0x%x\", vars->duplex);\n\t}\n\n\tif ((ELINK_DUAL_MEDIA(params)) &&\n\t (phy->req_line_speed == ELINK_SPEED_1000)) {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_8727_PCS_GP, &val1);\n\t\t/* In case of dual-media board and 1G, power up the XAUI side,\n\t\t * otherwise power it down. For 10G it is done automatically\n\t\t */\n\t\tif (link_up)\n\t\t\tval1 &= ~(3 << 10);\n\t\telse\n\t\t\tval1 |= (3 << 10);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_8727_PCS_GP, val1);\n\t}\n\treturn link_up;\n}\n\nstatic void elink_8727_link_reset(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\n\t/* Enable/Disable PHY transmitter output */\n\telink_set_disable_pmd_transmit(params, phy, 1);\n\n\t/* Disable Transmitter */\n\telink_sfp_set_transmitter(params, phy, 0);\n\t/* Clear LASI */\n\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);\n\n}\n\n/******************************************************************/\n/*\t\tBNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION\t */\n/******************************************************************/\nstatic void elink_save_848xx_spirom_version(struct elink_phy *phy,\n\t\t\t\t\t struct bnx2x_softc *sc, uint8_t port)\n{\n\tuint16_t val, fw_ver2, cnt, i;\n\tstatic struct elink_reg_set reg_set[] = {\n\t\t{MDIO_PMA_DEVAD, 0xA819, 0x0014},\n\t\t{MDIO_PMA_DEVAD, 0xA81A, 0xc200},\n\t\t{MDIO_PMA_DEVAD, 0xA81B, 0x0000},\n\t\t{MDIO_PMA_DEVAD, 0xA81C, 0x0300},\n\t\t{MDIO_PMA_DEVAD, 0xA817, 0x0009}\n\t};\n\tuint16_t fw_ver1;\n\n\tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n\t (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {\n\t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);\n\t\telink_save_spirom_version(sc, port, fw_ver1 & 0xfff,\n\t\t\t\t\t phy->ver_addr);\n\t} else {\n\t\t/* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */\n\t\t/* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */\n\t\tfor (i = 0; i < ARRAY_SIZE(reg_set); i++)\n\t\t\telink_cl45_write(sc, phy, reg_set[i].devad,\n\t\t\t\t\t reg_set[i].reg, reg_set[i].val);\n\n\t\tfor (cnt = 0; cnt < 100; cnt++) {\n\t\t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);\n\t\t\tif (val & 1)\n\t\t\t\tbreak;\n\t\t\tDELAY(5);\n\t\t}\n\t\tif (cnt == 100) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Unable to read 848xx \"\n\t\t\t\t \"phy fw version(1)\");\n\t\t\telink_save_spirom_version(sc, port, 0, phy->ver_addr);\n\t\t\treturn;\n\t\t}\n\n\t\t/* 2) read register 0xc200_0000 (SPI_FW_STATUS) */\n\t\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);\n\t\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);\n\t\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);\n\t\tfor (cnt = 0; cnt < 100; cnt++) {\n\t\t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);\n\t\t\tif (val & 1)\n\t\t\t\tbreak;\n\t\t\tDELAY(5);\n\t\t}\n\t\tif (cnt == 100) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Unable to read 848xx phy fw \"\n\t\t\t\t \"version(2)\");\n\t\t\telink_save_spirom_version(sc, port, 0, phy->ver_addr);\n\t\t\treturn;\n\t\t}\n\n\t\t/* lower 16 bits of the register SPI_FW_STATUS */\n\t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);\n\t\t/* upper 16 bits of register SPI_FW_STATUS */\n\t\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);\n\n\t\telink_save_spirom_version(sc, port, (fw_ver2 << 16) | fw_ver1,\n\t\t\t\t\t phy->ver_addr);\n\t}\n\n}\n\nstatic void elink_848xx_set_led(struct bnx2x_softc *sc, struct elink_phy *phy)\n{\n\tuint16_t val, offset, i;\n\tstatic struct elink_reg_set reg_set[] = {\n\t\t{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},\n\t\t{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},\n\t\t{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},\n\t\t{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},\n\t\t{MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,\n\t\t MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},\n\t\t{MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}\n\t};\n\t/* PHYC_CTL_LED_CTL */\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, &val);\n\tval &= 0xFE00;\n\tval |= 0x0092;\n\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LINK_SIGNAL, val);\n\n\tfor (i = 0; i < ARRAY_SIZE(reg_set); i++)\n\t\telink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,\n\t\t\t\t reg_set[i].val);\n\n\tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n\t (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))\n\t\toffset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;\n\telse\n\t\toffset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;\n\n\t/* stretch_en for LED3 */\n\telink_cl45_read_or_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, offset,\n\t\t\t\t MDIO_PMA_REG_84823_LED3_STRETCH_EN);\n}\n\nstatic void elink_848xx_specific_func(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t uint32_t action)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tswitch (action) {\n\tcase ELINK_PHY_INIT:\n\t\tif ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&\n\t\t (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {\n\t\t\t/* Save spirom version */\n\t\t\telink_save_848xx_spirom_version(phy, sc, params->port);\n\t\t}\n\t\t/* This phy uses the NIG latch mechanism since link indication\n\t\t * arrives through its LED4 and not via its LASI signal, so we\n\t\t * get steady signal instead of clear on read\n\t\t */\n\t\telink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port * 4,\n\t\t\t 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);\n\n\t\telink_848xx_set_led(sc, phy);\n\t\tbreak;\n\t}\n}\n\nstatic elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,\n\t\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t autoneg_val, an_1000_val, an_10_100_val;\n\n\telink_848xx_specific_func(phy, params, ELINK_PHY_INIT);\n\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);\n\n\t/* set 1000 speed advertisement */\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,\n\t\t\t&an_1000_val);\n\n\telink_ext_phy_set_pause(params, phy, vars);\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_AN_DEVAD,\n\t\t\tMDIO_AN_REG_8481_LEGACY_AN_ADV, &an_10_100_val);\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,\n\t\t\t&autoneg_val);\n\t/* Disable forced speed */\n\tautoneg_val &=\n\t ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));\n\tan_10_100_val &= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8));\n\n\tif (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n\t (phy->speed_cap_mask &\n\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||\n\t (phy->req_line_speed == ELINK_SPEED_1000)) {\n\t\tan_1000_val |= (1 << 8);\n\t\tautoneg_val |= (1 << 9 | 1 << 12);\n\t\tif (phy->req_duplex == DUPLEX_FULL)\n\t\t\tan_1000_val |= (1 << 9);\n\t\tPMD_DRV_LOG(DEBUG, \"Advertising 1G\");\n\t} else\n\t\tan_1000_val &= ~((1 << 8) | (1 << 9));\n\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,\n\t\t\t an_1000_val);\n\n\t/* Set 10/100 speed advertisement */\n\tif (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {\n\t\tif (phy->speed_cap_mask &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {\n\t\t\t/* Enable autoneg and restart autoneg for legacy speeds\n\t\t\t */\n\t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n\t\t\tan_10_100_val |= (1 << 8);\n\t\t\tPMD_DRV_LOG(DEBUG, \"Advertising 100M-FD\");\n\t\t}\n\n\t\tif (phy->speed_cap_mask &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {\n\t\t\t/* Enable autoneg and restart autoneg for legacy speeds\n\t\t\t */\n\t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n\t\t\tan_10_100_val |= (1 << 7);\n\t\t\tPMD_DRV_LOG(DEBUG, \"Advertising 100M-HD\");\n\t\t}\n\n\t\tif ((phy->speed_cap_mask &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&\n\t\t (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {\n\t\t\tan_10_100_val |= (1 << 6);\n\t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n\t\t\tPMD_DRV_LOG(DEBUG, \"Advertising 10M-FD\");\n\t\t}\n\n\t\tif ((phy->speed_cap_mask &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&\n\t\t (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {\n\t\t\tan_10_100_val |= (1 << 5);\n\t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n\t\t\tPMD_DRV_LOG(DEBUG, \"Advertising 10M-HD\");\n\t\t}\n\t}\n\n\t/* Only 10/100 are allowed to work in FORCE mode */\n\tif ((phy->req_line_speed == ELINK_SPEED_100) &&\n\t (phy->supported &\n\t (ELINK_SUPPORTED_100baseT_Half | ELINK_SUPPORTED_100baseT_Full))) {\n\t\tautoneg_val |= (1 << 13);\n\t\t/* Enabled AUTO-MDIX when autoneg is disabled */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,\n\t\t\t\t (1 << 15 | 1 << 9 | 7 << 0));\n\t\t/* The PHY needs this set even for forced link. */\n\t\tan_10_100_val |= (1 << 8) | (1 << 7);\n\t\tPMD_DRV_LOG(DEBUG, \"Setting 100M force\");\n\t}\n\tif ((phy->req_line_speed == ELINK_SPEED_10) &&\n\t (phy->supported &\n\t (ELINK_SUPPORTED_10baseT_Half | ELINK_SUPPORTED_10baseT_Full))) {\n\t\t/* Enabled AUTO-MDIX when autoneg is disabled */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,\n\t\t\t\t (1 << 15 | 1 << 9 | 7 << 0));\n\t\tPMD_DRV_LOG(DEBUG, \"Setting 10M force\");\n\t}\n\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,\n\t\t\t an_10_100_val);\n\n\tif (phy->req_duplex == DUPLEX_FULL)\n\t\tautoneg_val |= (1 << 8);\n\n\t/* Always write this if this is not 84833/4.\n\t * For 84833/4, write it only when it's a forced speed.\n\t */\n\tif (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&\n\t (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) ||\n\t ((autoneg_val & (1 << 12)) == 0))\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD,\n\t\t\t\t MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);\n\n\tif (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n\t (phy->speed_cap_mask &\n\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||\n\t (phy->req_line_speed == ELINK_SPEED_10000)) {\n\t\tPMD_DRV_LOG(DEBUG, \"Advertising 10G\");\n\t\t/* Restart autoneg for 10G */\n\n\t\telink_cl45_read_or_write(sc, phy,\n\t\t\t\t\t MDIO_AN_DEVAD,\n\t\t\t\t\t MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,\n\t\t\t\t\t 0x1000);\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x3200);\n\t} else\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD,\n\t\t\t\t MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 1);\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_8481_config_init(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\t/* Restore normal power mode */\n\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);\n\n\t/* HW reset */\n\telink_ext_phy_hw_reset(sc, params->port);\n\telink_wait_reset_complete(sc, phy, params);\n\n\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);\n\treturn elink_848xx_cmn_config_init(phy, params, vars);\n}\n\n#define PHY84833_CMDHDLR_WAIT 300\n#define PHY84833_CMDHDLR_MAX_ARGS 5\nstatic elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t uint16_t fw_cmd, uint16_t cmd_args[],\n\t\t\t\t\t int argc)\n{\n\tint idx;\n\tuint16_t val;\n\tstruct bnx2x_softc *sc = params->sc;\n\t/* Write CMD_OPEN_OVERRIDE to STATUS reg */\n\telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n\t\t\t MDIO_84833_CMD_HDLR_STATUS,\n\t\t\t PHY84833_STATUS_CMD_OPEN_OVERRIDE);\n\tfor (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {\n\t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n\t\t\t\tMDIO_84833_CMD_HDLR_STATUS, &val);\n\t\tif (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)\n\t\t\tbreak;\n\t\tDELAY(1000 * 1);\n\t}\n\tif (idx >= PHY84833_CMDHDLR_WAIT) {\n\t\tPMD_DRV_LOG(DEBUG, \"FW cmd: FW not ready.\");\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\n\t/* Prepare argument(s) and issue command */\n\tfor (idx = 0; idx < argc; idx++) {\n\t\telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n\t\t\t\t MDIO_84833_CMD_HDLR_DATA1 + idx,\n\t\t\t\t cmd_args[idx]);\n\t}\n\telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n\t\t\t MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);\n\tfor (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {\n\t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n\t\t\t\tMDIO_84833_CMD_HDLR_STATUS, &val);\n\t\tif ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||\n\t\t (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))\n\t\t\tbreak;\n\t\tDELAY(1000 * 1);\n\t}\n\tif ((idx >= PHY84833_CMDHDLR_WAIT) ||\n\t (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {\n\t\tPMD_DRV_LOG(DEBUG, \"FW cmd failed.\");\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\t/* Gather returning data */\n\tfor (idx = 0; idx < argc; idx++) {\n\t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n\t\t\t\tMDIO_84833_CMD_HDLR_DATA1 + idx,\n\t\t\t\t&cmd_args[idx]);\n\t}\n\telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n\t\t\t MDIO_84833_CMD_HDLR_STATUS,\n\t\t\t PHY84833_STATUS_CMD_CLEAR_COMPLETE);\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,\n\t\t\t\t\t\tstruct elink_params *params,\n\t\t\t\t\t\t__rte_unused struct elink_vars\n\t\t\t\t\t\t*vars)\n{\n\tuint32_t pair_swap;\n\tuint16_t data[PHY84833_CMDHDLR_MAX_ARGS];\n\telink_status_t status;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\t/* Check for configuration. */\n\tpair_swap = REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_hw_config[params->port].\n\t\t\t\t xgbt_phy_cfg)) &\n\t PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;\n\n\tif (pair_swap == 0)\n\t\treturn ELINK_STATUS_OK;\n\n\t/* Only the second argument is used for this command */\n\tdata[1] = (uint16_t) pair_swap;\n\n\tstatus = elink_84833_cmd_hdlr(phy, params,\n\t\t\t\t PHY84833_CMD_SET_PAIR_SWAP, data,\n\t\t\t\t PHY84833_CMDHDLR_MAX_ARGS);\n\tif (status == ELINK_STATUS_OK) {\n\t\tPMD_DRV_LOG(DEBUG, \"Pairswap OK, val=0x%x\", data[1]);\n\t}\n\n\treturn status;\n}\n\nstatic uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc *sc,\n\t\t\t\t\t uint32_t shmem_base_path[],\n\t\t\t\t\t __rte_unused uint32_t chip_id)\n{\n\tuint32_t reset_pin[2];\n\tuint32_t idx;\n\tuint8_t reset_gpios;\n\tif (CHIP_IS_E3(sc)) {\n\t\t/* Assume that these will be GPIOs, not EPIOs. */\n\t\tfor (idx = 0; idx < 2; idx++) {\n\t\t\t/* Map config param to register bit. */\n\t\t\treset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +\n\t\t\t\t\t\toffsetof(struct shmem_region,\n\t\t\t\t\t\t\t dev_info.\n\t\t\t\t\t\t\t port_hw_config[0].\n\t\t\t\t\t\t\t e3_cmn_pin_cfg));\n\t\t\treset_pin[idx] =\n\t\t\t (reset_pin[idx] & PORT_HW_CFG_E3_PHY_RESET_MASK) >>\n\t\t\t PORT_HW_CFG_E3_PHY_RESET_SHIFT;\n\t\t\treset_pin[idx] -= PIN_CFG_GPIO0_P0;\n\t\t\treset_pin[idx] = (1 << reset_pin[idx]);\n\t\t}\n\t\treset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);\n\t} else {\n\t\t/* E2, look from diff place of shmem. */\n\t\tfor (idx = 0; idx < 2; idx++) {\n\t\t\treset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +\n\t\t\t\t\t\toffsetof(struct shmem_region,\n\t\t\t\t\t\t\t dev_info.\n\t\t\t\t\t\t\t port_hw_config[0].\n\t\t\t\t\t\t\t default_cfg));\n\t\t\treset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;\n\t\t\treset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;\n\t\t\treset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;\n\t\t\treset_pin[idx] = (1 << reset_pin[idx]);\n\t\t}\n\t\treset_gpios = (uint8_t) (reset_pin[0] | reset_pin[1]);\n\t}\n\n\treturn reset_gpios;\n}\n\nstatic elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t reset_gpios;\n\tuint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +\n\t\t\t\t\t\toffsetof(struct shmem2_region,\n\t\t\t\t\t\t\t other_shmem_base_addr));\n\n\tuint32_t shmem_base_path[2];\n\n\t/* Work around for 84833 LED failure inside RESET status */\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n\t\t\t MDIO_AN_REG_8481_LEGACY_MII_CTRL,\n\t\t\t MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n\t\t\t MDIO_AN_REG_8481_1G_100T_EXT_CTRL,\n\t\t\t MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);\n\n\tshmem_base_path[0] = params->shmem_base;\n\tshmem_base_path[1] = other_shmem_base_addr;\n\n\treset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path,\n\t\t\t\t\t\t params->chip_id);\n\n\telink_cb_gpio_mult_write(sc, reset_gpios,\n\t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW);\n\tDELAY(10);\n\tPMD_DRV_LOG(DEBUG, \"84833 hw reset on pin values 0x%x\", reset_gpios);\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\telink_status_t rc;\n\tuint16_t cmd_args = 0;\n\n\tPMD_DRV_LOG(DEBUG, \"Don't Advertise 10GBase-T EEE\");\n\n\t/* Prevent Phy from working in EEE and advertising it */\n\trc = elink_84833_cmd_hdlr(phy, params,\n\t\t\t\t PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);\n\tif (rc != ELINK_STATUS_OK) {\n\t\tPMD_DRV_LOG(DEBUG, \"EEE disable failed.\");\n\t\treturn rc;\n\t}\n\n\treturn elink_eee_disable(phy, params, vars);\n}\n\nstatic elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\telink_status_t rc;\n\tuint16_t cmd_args = 1;\n\n\trc = elink_84833_cmd_hdlr(phy, params,\n\t\t\t\t PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);\n\tif (rc != ELINK_STATUS_OK) {\n\t\tPMD_DRV_LOG(DEBUG, \"EEE enable failed.\");\n\t\treturn rc;\n\t}\n\n\treturn elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);\n}\n\n#define PHY84833_CONSTANT_LATENCY 1193\nstatic elink_status_t elink_848x3_config_init(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port, initialize = 1;\n\tuint16_t val;\n\tuint32_t actual_phy_selection;\n\tuint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS];\n\telink_status_t rc = ELINK_STATUS_OK;\n\n\tDELAY(1000 * 1);\n\n\tif (!(CHIP_IS_E1x(sc)))\n\t\tport = SC_PATH(sc);\n\telse\n\t\tport = params->port;\n\n\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {\n\t\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,\n\t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);\n\t} else {\n\t\t/* MDIO reset */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x8000);\n\t}\n\n\telink_wait_reset_complete(sc, phy, params);\n\n\t/* Wait for GPHY to come out of reset */\n\tDELAY(1000 * 50);\n\tif ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) &&\n\t (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {\n\t\t/* BNX2X84823 requires that XGXS links up first @ 10G for normal\n\t\t * behavior.\n\t\t */\n\t\tuint16_t temp;\n\t\ttemp = vars->line_speed;\n\t\tvars->line_speed = ELINK_SPEED_10000;\n\t\telink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0);\n\t\telink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);\n\t\tvars->line_speed = temp;\n\t}\n\n\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n\t\t\tMDIO_CTL_REG_84823_MEDIA, &val);\n\tval &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |\n\t\t MDIO_CTL_REG_84823_MEDIA_LINE_MASK |\n\t\t MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |\n\t\t MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |\n\t\t MDIO_CTL_REG_84823_MEDIA_FIBER_1G);\n\n\tif (CHIP_IS_E3(sc)) {\n\t\tval &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |\n\t\t\t MDIO_CTL_REG_84823_MEDIA_LINE_MASK);\n\t} else {\n\t\tval |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |\n\t\t\tMDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);\n\t}\n\n\tactual_phy_selection = elink_phy_selection(params);\n\n\tswitch (actual_phy_selection) {\n\tcase PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:\n\t\t/* Do nothing. Essentially this is like the priority copper */\n\t\tbreak;\n\tcase PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:\n\t\tval |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;\n\t\tbreak;\n\tcase PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:\n\t\tval |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;\n\t\tbreak;\n\tcase PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:\n\t\t/* Do nothing here. The first PHY won't be initialized at all */\n\t\tbreak;\n\tcase PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:\n\t\tval |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;\n\t\tinitialize = 0;\n\t\tbreak;\n\t}\n\tif (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)\n\t\tval |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;\n\n\telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n\t\t\t MDIO_CTL_REG_84823_MEDIA, val);\n\tPMD_DRV_LOG(DEBUG, \"Multi_phy config = 0x%x, Media control = 0x%x\",\n\t\t params->multi_phy_config, val);\n\n\tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n\t (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {\n\t\telink_84833_pair_swap_cfg(phy, params, vars);\n\n\t\t/* Keep AutogrEEEn disabled. */\n\t\tcmd_args[0] = 0x0;\n\t\tcmd_args[1] = 0x0;\n\t\tcmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;\n\t\tcmd_args[3] = PHY84833_CONSTANT_LATENCY;\n\t\trc = elink_84833_cmd_hdlr(phy, params,\n\t\t\t\t\t PHY84833_CMD_SET_EEE_MODE, cmd_args,\n\t\t\t\t\t PHY84833_CMDHDLR_MAX_ARGS);\n\t\tif (rc != ELINK_STATUS_OK) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Cfg AutogrEEEn failed.\");\n\t\t}\n\t}\n\tif (initialize) {\n\t\trc = elink_848xx_cmn_config_init(phy, params, vars);\n\t} else {\n\t\telink_save_848xx_spirom_version(phy, sc, params->port);\n\t}\n\t/* 84833 PHY has a better feature and doesn't need to support this. */\n\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {\n\t\tuint32_t cms_enable = REG_RD(sc, params->shmem_base +\n\t\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t\t dev_info.\n\t\t\t\t\t\t port_hw_config[params->\n\t\t\t\t\t\t\t\t port].\n\t\t\t\t\t\t default_cfg)) &\n\t\t PORT_HW_CFG_ENABLE_CMS_MASK;\n\n\t\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n\t\t\t\tMDIO_CTL_REG_84823_USER_CTRL_REG, &val);\n\t\tif (cms_enable)\n\t\t\tval |= MDIO_CTL_REG_84823_USER_CTRL_CMS;\n\t\telse\n\t\t\tval &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;\n\t\telink_cl45_write(sc, phy, MDIO_CTL_DEVAD,\n\t\t\t\t MDIO_CTL_REG_84823_USER_CTRL_REG, val);\n\t}\n\n\telink_cl45_read(sc, phy, MDIO_CTL_DEVAD,\n\t\t\tMDIO_84833_TOP_CFG_FW_REV, &val);\n\n\t/* Configure EEE support */\n\tif ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&\n\t (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&\n\t elink_eee_has_cap(params)) {\n\t\trc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);\n\t\tif (rc != ELINK_STATUS_OK) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Failed to configure EEE timers\");\n\t\t\telink_8483x_disable_eee(phy, params, vars);\n\t\t\treturn rc;\n\t\t}\n\n\t\tif ((phy->req_duplex == DUPLEX_FULL) &&\n\t\t (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&\n\t\t (elink_eee_calc_timer(params) ||\n\t\t !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)))\n\t\t\trc = elink_8483x_enable_eee(phy, params, vars);\n\t\telse\n\t\t\trc = elink_8483x_disable_eee(phy, params, vars);\n\t\tif (rc != ELINK_STATUS_OK) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Failed to set EEE advertisement\");\n\t\t\treturn rc;\n\t\t}\n\t} else {\n\t\tvars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;\n\t}\n\n\tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n\t (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) {\n\t\t/* Bring PHY out of super isolate mode as the final step. */\n\t\telink_cl45_read_and_write(sc, phy,\n\t\t\t\t\t MDIO_CTL_DEVAD,\n\t\t\t\t\t MDIO_84833_TOP_CFG_XGPHY_STRAP1,\n\t\t\t\t\t (uint16_t) ~\n\t\t\t\t\t MDIO_84833_SUPER_ISOLATE);\n\t}\n\treturn rc;\n}\n\nstatic uint8_t elink_848xx_read_status(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val, val1, val2;\n\tuint8_t link_up = 0;\n\n\t/* Check 10G-BaseT link status */\n\t/* Check PMD signal ok */\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, 0xFFFA, &val1);\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, &val2);\n\tPMD_DRV_LOG(DEBUG, \"BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x\", val2);\n\n\t/* Check link 10G */\n\tif (val2 & (1 << 11)) {\n\t\tvars->line_speed = ELINK_SPEED_10000;\n\t\tvars->duplex = DUPLEX_FULL;\n\t\tlink_up = 1;\n\t\telink_ext_phy_10G_an_resolve(sc, phy, vars);\n\t} else {\t\t/* Check Legacy speed link */\n\t\tuint16_t legacy_status, legacy_speed, mii_ctrl;\n\n\t\t/* Enable expansion register 0x42 (Operation mode status) */\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_AN_DEVAD,\n\t\t\t\t MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);\n\n\t\t/* Get legacy speed operation status */\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_AN_DEVAD,\n\t\t\t\tMDIO_AN_REG_8481_EXPANSION_REG_RD_RW,\n\t\t\t\t&legacy_status);\n\n\t\tPMD_DRV_LOG(DEBUG, \"Legacy speed status = 0x%x\", legacy_status);\n\t\tlink_up = ((legacy_status & (1 << 11)) == (1 << 11));\n\t\tlegacy_speed = (legacy_status & (3 << 9));\n\t\tif (legacy_speed == (0 << 9))\n\t\t\tvars->line_speed = ELINK_SPEED_10;\n\t\telse if (legacy_speed == (1 << 9))\n\t\t\tvars->line_speed = ELINK_SPEED_100;\n\t\telse if (legacy_speed == (2 << 9))\n\t\t\tvars->line_speed = ELINK_SPEED_1000;\n\t\telse {\t\t/* Should not happen: Treat as link down */\n\t\t\tvars->line_speed = 0;\n\t\t\tlink_up = 0;\n\t\t}\n\n\t\tif (params->feature_config_flags &\n\t\t ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {\n\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\tMDIO_AN_DEVAD,\n\t\t\t\t\tMDIO_AN_REG_8481_LEGACY_MII_CTRL,\n\t\t\t\t\t&mii_ctrl);\n\t\t\t/* For IEEE testing, check for a fake link. */\n\t\t\tlink_up |= ((mii_ctrl & 0x3040) == 0x40);\n\t\t}\n\n\t\tif (link_up) {\n\t\t\tif (legacy_status & (1 << 8))\n\t\t\t\tvars->duplex = DUPLEX_FULL;\n\t\t\telse\n\t\t\t\tvars->duplex = DUPLEX_HALF;\n\n\t\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t\t \"Link is up in %dMbps, is_duplex_full= %d\",\n\t\t\t\t vars->line_speed,\n\t\t\t\t (vars->duplex == DUPLEX_FULL));\n\t\t\t/* Check legacy speed AN resolution */\n\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\tMDIO_AN_DEVAD,\n\t\t\t\t\tMDIO_AN_REG_8481_LEGACY_MII_STATUS,\n\t\t\t\t\t&val);\n\t\t\tif (val & (1 << 5))\n\t\t\t\tvars->link_status |=\n\t\t\t\t LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\tMDIO_AN_DEVAD,\n\t\t\t\t\tMDIO_AN_REG_8481_LEGACY_AN_EXPANSION,\n\t\t\t\t\t&val);\n\t\t\tif ((val & (1 << 0)) == 0)\n\t\t\t\tvars->link_status |=\n\t\t\t\t LINK_STATUS_PARALLEL_DETECTION_USED;\n\t\t}\n\t}\n\tif (link_up) {\n\t\tPMD_DRV_LOG(DEBUG, \"BNX2X848x3: link speed is %d\",\n\t\t\t vars->line_speed);\n\t\telink_ext_phy_resolve_fc(phy, params, vars);\n\n\t\t/* Read LP advertised speeds */\n\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\tMDIO_AN_REG_CL37_FC_LP, &val);\n\t\tif (val & (1 << 5))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;\n\t\tif (val & (1 << 6))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;\n\t\tif (val & (1 << 7))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;\n\t\tif (val & (1 << 8))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;\n\t\tif (val & (1 << 9))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;\n\n\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\tMDIO_AN_REG_1000T_STATUS, &val);\n\n\t\tif (val & (1 << 10))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;\n\t\tif (val & (1 << 11))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n\n\t\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\tMDIO_AN_REG_MASTER_STATUS, &val);\n\n\t\tif (val & (1 << 11))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n\n\t\t/* Determine if EEE was negotiated */\n\t\tif ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n\t\t (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834))\n\t\t\telink_eee_an_resolve(phy, params, vars);\n\t}\n\n\treturn link_up;\n}\n\nstatic elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t * str,\n\t\t\t\t\t uint16_t * len)\n{\n\telink_status_t status = ELINK_STATUS_OK;\n\tuint32_t spirom_ver;\n\tspirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);\n\tstatus = elink_format_ver(spirom_ver, str, len);\n\treturn status;\n}\n\nstatic void elink_8481_hw_reset(__rte_unused struct elink_phy *phy,\n\t\t\t\tstruct elink_params *params)\n{\n\telink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);\n\telink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);\n}\n\nstatic void elink_8481_link_reset(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\telink_cl45_write(params->sc, phy,\n\t\t\t MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);\n\telink_cl45_write(params->sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);\n}\n\nstatic void elink_848x3_link_reset(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port;\n\tuint16_t val16;\n\n\tif (!(CHIP_IS_E1x(sc)))\n\t\tport = SC_PATH(sc);\n\telse\n\t\tport = params->port;\n\n\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823) {\n\t\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,\n\t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, port);\n\t} else {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_CTL_DEVAD,\n\t\t\t\tMDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);\n\t\tval16 |= MDIO_84833_SUPER_ISOLATE;\n\t\telink_cl45_write(sc, phy,\n\t\t\t\t MDIO_CTL_DEVAD,\n\t\t\t\t MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);\n\t}\n}\n\nstatic void elink_848xx_set_link_led(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params, uint8_t mode)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val;\n\t__rte_unused uint8_t port;\n\n\tif (!(CHIP_IS_E1x(sc)))\n\t\tport = SC_PATH(sc);\n\telse\n\t\tport = params->port;\n\n\tswitch (mode) {\n\tcase ELINK_LED_MODE_OFF:\n\n\t\tPMD_DRV_LOG(DEBUG, \"Port 0x%x: LED MODE OFF\", port);\n\n\t\tif ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==\n\t\t SHARED_HW_CFG_LED_EXTPHY1) {\n\n\t\t\t/* Set LED masks */\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x0);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED2_MASK, 0x0);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED3_MASK, 0x0);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED5_MASK, 0x0);\n\n\t\t} else {\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x0);\n\t\t}\n\t\tbreak;\n\tcase ELINK_LED_MODE_FRONT_PANEL_OFF:\n\n\t\tPMD_DRV_LOG(DEBUG, \"Port 0x%x: LED MODE FRONT PANEL OFF\", port);\n\n\t\tif ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==\n\t\t SHARED_HW_CFG_LED_EXTPHY1) {\n\n\t\t\t/* Set LED masks */\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x0);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED2_MASK, 0x0);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED3_MASK, 0x0);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED5_MASK, 0x20);\n\n\t\t} else {\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x0);\n\t\t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {\n\t\t\t\t/* Disable MI_INT interrupt before setting LED4\n\t\t\t\t * source to constant off.\n\t\t\t\t */\n\t\t\t\tif (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +\n\t\t\t\t\t params->port * 4) &\n\t\t\t\t ELINK_NIG_MASK_MI_INT) {\n\t\t\t\t\tparams->link_flags |=\n\t\t\t\t\t ELINK_LINK_FLAGS_INT_DISABLED;\n\n\t\t\t\t\telink_bits_dis(sc,\n\t\t\t\t\t\t NIG_REG_MASK_INTERRUPT_PORT0\n\t\t\t\t\t\t + params->port * 4,\n\t\t\t\t\t\t ELINK_NIG_MASK_MI_INT);\n\t\t\t\t}\n\t\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t\t MDIO_PMA_REG_8481_SIGNAL_MASK,\n\t\t\t\t\t\t 0x0);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tcase ELINK_LED_MODE_ON:\n\n\t\tPMD_DRV_LOG(DEBUG, \"Port 0x%x: LED MODE ON\", port);\n\n\t\tif ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==\n\t\t SHARED_HW_CFG_LED_EXTPHY1) {\n\t\t\t/* Set control reg */\n\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\t\tMDIO_PMA_REG_8481_LINK_SIGNAL, &val);\n\t\t\tval &= 0x8000;\n\t\t\tval |= 0x2492;\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL, val);\n\n\t\t\t/* Set LED masks */\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x0);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED2_MASK, 0x20);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED3_MASK, 0x20);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED5_MASK, 0x0);\n\t\t} else {\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x20);\n\t\t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {\n\t\t\t\t/* Disable MI_INT interrupt before setting LED4\n\t\t\t\t * source to constant on.\n\t\t\t\t */\n\t\t\t\tif (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +\n\t\t\t\t\t params->port * 4) &\n\t\t\t\t ELINK_NIG_MASK_MI_INT) {\n\t\t\t\t\tparams->link_flags |=\n\t\t\t\t\t ELINK_LINK_FLAGS_INT_DISABLED;\n\n\t\t\t\t\telink_bits_dis(sc,\n\t\t\t\t\t\t NIG_REG_MASK_INTERRUPT_PORT0\n\t\t\t\t\t\t + params->port * 4,\n\t\t\t\t\t\t ELINK_NIG_MASK_MI_INT);\n\t\t\t\t}\n\t\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t\t MDIO_PMA_REG_8481_SIGNAL_MASK,\n\t\t\t\t\t\t 0x20);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tcase ELINK_LED_MODE_OPER:\n\n\t\tPMD_DRV_LOG(DEBUG, \"Port 0x%x: LED MODE OPER\", port);\n\n\t\tif ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==\n\t\t SHARED_HW_CFG_LED_EXTPHY1) {\n\n\t\t\t/* Set control reg */\n\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\t\tMDIO_PMA_REG_8481_LINK_SIGNAL, &val);\n\n\t\t\tif (!((val &\n\t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)\n\t\t\t >>\n\t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT))\n\t\t\t{\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Setting LINK_SIGNAL\");\n\t\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL,\n\t\t\t\t\t\t 0xa492);\n\t\t\t}\n\n\t\t\t/* Set LED masks */\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, 0x10);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED2_MASK, 0x80);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED3_MASK, 0x98);\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED5_MASK, 0x40);\n\n\t\t} else {\n\t\t\t/* EXTPHY2 LED mode indicate that the 100M/1G/10G LED\n\t\t\t * sources are all wired through LED1, rather than only\n\t\t\t * 10G in other modes.\n\t\t\t */\n\t\t\tval = ((params->hw_led_mode <<\n\t\t\t\tSHARED_HW_CFG_LED_MODE_SHIFT) ==\n\t\t\t SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;\n\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LED1_MASK, val);\n\n\t\t\t/* Tell LED3 to blink on source */\n\t\t\telink_cl45_read(sc, phy,\n\t\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\t\tMDIO_PMA_REG_8481_LINK_SIGNAL, &val);\n\t\t\tval &= ~(7 << 6);\n\t\t\tval |= (1 << 6);\t/* A83B[8:6]= 1 */\n\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t MDIO_PMA_REG_8481_LINK_SIGNAL, val);\n\t\t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834) {\n\t\t\t\t/* Restore LED4 source to external link,\n\t\t\t\t * and re-enable interrupts.\n\t\t\t\t */\n\t\t\t\telink_cl45_write(sc, phy,\n\t\t\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t\t\t MDIO_PMA_REG_8481_SIGNAL_MASK,\n\t\t\t\t\t\t 0x40);\n\t\t\t\tif (params->link_flags &\n\t\t\t\t ELINK_LINK_FLAGS_INT_DISABLED) {\n\t\t\t\t\telink_link_int_enable(params);\n\t\t\t\t\tparams->link_flags &=\n\t\t\t\t\t ~ELINK_LINK_FLAGS_INT_DISABLED;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tbreak;\n\t}\n\n\t/* This is a workaround for E3+84833 until autoneg\n\t * restart is fixed in f/w\n\t */\n\tif (CHIP_IS_E3(sc)) {\n\t\telink_cl45_read(sc, phy, MDIO_WC_DEVAD,\n\t\t\t\tMDIO_WC_REG_GP2_STATUS_GP_2_1, &val);\n\t}\n}\n\n/******************************************************************/\n/*\t\t\t54618SE PHY SECTION\t\t\t */\n/******************************************************************/\nstatic void elink_54618se_specific_func(struct elink_phy *phy,\n\t\t\t\t\tstruct elink_params *params,\n\t\t\t\t\tuint32_t action)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t temp;\n\tswitch (action) {\n\tcase ELINK_PHY_INIT:\n\t\t/* Configure LED4: set to INTR (0x6). */\n\t\t/* Accessing shadow register 0xe. */\n\t\telink_cl22_write(sc, phy,\n\t\t\t\t MDIO_REG_GPHY_SHADOW,\n\t\t\t\t MDIO_REG_GPHY_SHADOW_LED_SEL2);\n\t\telink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);\n\t\ttemp &= ~(0xf << 4);\n\t\ttemp |= (0x6 << 4);\n\t\telink_cl22_write(sc, phy,\n\t\t\t\t MDIO_REG_GPHY_SHADOW,\n\t\t\t\t MDIO_REG_GPHY_SHADOW_WR_ENA | temp);\n\t\t/* Configure INTR based on link status change. */\n\t\telink_cl22_write(sc, phy,\n\t\t\t\t MDIO_REG_INTR_MASK,\n\t\t\t\t ~MDIO_REG_INTR_MASK_LINK_STATUS);\n\t\tbreak;\n\t}\n}\n\nstatic elink_status_t elink_54618se_config_init(struct elink_phy *phy,\n\t\t\t\t\t\tstruct elink_params *params,\n\t\t\t\t\t\tstruct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t port;\n\tuint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;\n\tuint32_t cfg_pin;\n\n\tPMD_DRV_LOG(DEBUG, \"54618SE cfg init\");\n\tDELAY(1000 * 1);\n\n\t/* This works with E3 only, no need to check the chip\n\t * before determining the port.\n\t */\n\tport = params->port;\n\n\tcfg_pin = (REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_hw_config[port].\n\t\t\t\t e3_cmn_pin_cfg)) &\n\t\t PORT_HW_CFG_E3_PHY_RESET_MASK) >>\n\t PORT_HW_CFG_E3_PHY_RESET_SHIFT;\n\n\t/* Drive pin high to bring the GPHY out of reset. */\n\telink_set_cfg_pin(sc, cfg_pin, 1);\n\n\t/* wait for GPHY to reset */\n\tDELAY(1000 * 50);\n\n\t/* reset phy */\n\telink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x8000);\n\telink_wait_reset_complete(sc, phy, params);\n\n\t/* Wait for GPHY to reset */\n\tDELAY(1000 * 50);\n\n\telink_54618se_specific_func(phy, params, ELINK_PHY_INIT);\n\t/* Flip the signal detect polarity (set 0x1c.0x1e[8]). */\n\telink_cl22_write(sc, phy,\n\t\t\t MDIO_REG_GPHY_SHADOW,\n\t\t\t MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);\n\telink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);\n\ttemp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;\n\telink_cl22_write(sc, phy,\n\t\t\t MDIO_REG_GPHY_SHADOW,\n\t\t\t MDIO_REG_GPHY_SHADOW_WR_ENA | temp);\n\n\t/* Set up fc */\n\t/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */\n\telink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);\n\tfc_val = 0;\n\tif ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==\n\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)\n\t\tfc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;\n\n\tif ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==\n\t MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)\n\t\tfc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;\n\n\t/* Read all advertisement */\n\telink_cl22_read(sc, phy, 0x09, &an_1000_val);\n\n\telink_cl22_read(sc, phy, 0x04, &an_10_100_val);\n\n\telink_cl22_read(sc, phy, MDIO_PMA_REG_CTRL, &autoneg_val);\n\n\t/* Disable forced speed */\n\tautoneg_val &=\n\t ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));\n\tan_10_100_val &=\n\t ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) |\n\t (1 << 11));\n\n\tif (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&\n\t (phy->speed_cap_mask &\n\t PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||\n\t (phy->req_line_speed == ELINK_SPEED_1000)) {\n\t\tan_1000_val |= (1 << 8);\n\t\tautoneg_val |= (1 << 9 | 1 << 12);\n\t\tif (phy->req_duplex == DUPLEX_FULL)\n\t\t\tan_1000_val |= (1 << 9);\n\t\tPMD_DRV_LOG(DEBUG, \"Advertising 1G\");\n\t} else\n\t\tan_1000_val &= ~((1 << 8) | (1 << 9));\n\n\telink_cl22_write(sc, phy, 0x09, an_1000_val);\n\telink_cl22_read(sc, phy, 0x09, &an_1000_val);\n\n\t/* Advertise 10/100 link speed */\n\tif (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {\n\t\tif (phy->speed_cap_mask &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {\n\t\t\tan_10_100_val |= (1 << 5);\n\t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n\t\t\tPMD_DRV_LOG(DEBUG, \"Advertising 10M-HD\");\n\t\t}\n\t\tif (phy->speed_cap_mask &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {\n\t\t\tan_10_100_val |= (1 << 6);\n\t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n\t\t\tPMD_DRV_LOG(DEBUG, \"Advertising 10M-FD\");\n\t\t}\n\t\tif (phy->speed_cap_mask &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {\n\t\t\tan_10_100_val |= (1 << 7);\n\t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n\t\t\tPMD_DRV_LOG(DEBUG, \"Advertising 100M-HD\");\n\t\t}\n\t\tif (phy->speed_cap_mask &\n\t\t PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {\n\t\t\tan_10_100_val |= (1 << 8);\n\t\t\tautoneg_val |= (1 << 9 | 1 << 12);\n\t\t\tPMD_DRV_LOG(DEBUG, \"Advertising 100M-FD\");\n\t\t}\n\t}\n\n\t/* Only 10/100 are allowed to work in FORCE mode */\n\tif (phy->req_line_speed == ELINK_SPEED_100) {\n\t\tautoneg_val |= (1 << 13);\n\t\t/* Enabled AUTO-MDIX when autoneg is disabled */\n\t\telink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));\n\t\tPMD_DRV_LOG(DEBUG, \"Setting 100M force\");\n\t}\n\tif (phy->req_line_speed == ELINK_SPEED_10) {\n\t\t/* Enabled AUTO-MDIX when autoneg is disabled */\n\t\telink_cl22_write(sc, phy, 0x18, (1 << 15 | 1 << 9 | 7 << 0));\n\t\tPMD_DRV_LOG(DEBUG, \"Setting 10M force\");\n\t}\n\n\tif ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {\n\t\telink_status_t rc;\n\n\t\telink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,\n\t\t\t\t MDIO_REG_GPHY_EXP_ACCESS_TOP |\n\t\t\t\t MDIO_REG_GPHY_EXP_TOP_2K_BUF);\n\t\telink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);\n\t\ttemp &= 0xfffe;\n\t\telink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);\n\n\t\trc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);\n\t\tif (rc != ELINK_STATUS_OK) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Failed to configure EEE timers\");\n\t\t\telink_eee_disable(phy, params, vars);\n\t\t} else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&\n\t\t\t (phy->req_duplex == DUPLEX_FULL) &&\n\t\t\t (elink_eee_calc_timer(params) ||\n\t\t\t !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) {\n\t\t\t/* Need to advertise EEE only when requested,\n\t\t\t * and either no LPI assertion was requested,\n\t\t\t * or it was requested and a valid timer was set.\n\t\t\t * Also notice full duplex is required for EEE.\n\t\t\t */\n\t\t\telink_eee_advertise(phy, params, vars,\n\t\t\t\t\t SHMEM_EEE_1G_ADV);\n\t\t} else {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Don't Advertise 1GBase-T EEE\");\n\t\t\telink_eee_disable(phy, params, vars);\n\t\t}\n\t} else {\n\t\tvars->eee_status &= ~SHMEM_EEE_1G_ADV <<\n\t\t SHMEM_EEE_SUPPORTED_SHIFT;\n\n\t\tif (phy->flags & ELINK_FLAGS_EEE) {\n\t\t\t/* Handle legacy auto-grEEEn */\n\t\t\tif (params->feature_config_flags &\n\t\t\t ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {\n\t\t\t\ttemp = 6;\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Enabling Auto-GrEEEn\");\n\t\t\t} else {\n\t\t\t\ttemp = 0;\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Don't Adv. EEE\");\n\t\t\t}\n\t\t\telink_cl45_write(sc, phy, MDIO_AN_DEVAD,\n\t\t\t\t\t MDIO_AN_REG_EEE_ADV, temp);\n\t\t}\n\t}\n\n\telink_cl22_write(sc, phy, 0x04, an_10_100_val | fc_val);\n\n\tif (phy->req_duplex == DUPLEX_FULL)\n\t\tautoneg_val |= (1 << 8);\n\n\telink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, autoneg_val);\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_5461x_set_link_led(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params, uint8_t mode)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t temp;\n\n\telink_cl22_write(sc, phy,\n\t\t\t MDIO_REG_GPHY_SHADOW, MDIO_REG_GPHY_SHADOW_LED_SEL1);\n\telink_cl22_read(sc, phy, MDIO_REG_GPHY_SHADOW, &temp);\n\ttemp &= 0xff00;\n\n\tPMD_DRV_LOG(DEBUG, \"54618x set link led (mode=%x)\", mode);\n\tswitch (mode) {\n\tcase ELINK_LED_MODE_FRONT_PANEL_OFF:\n\tcase ELINK_LED_MODE_OFF:\n\t\ttemp |= 0x00ee;\n\t\tbreak;\n\tcase ELINK_LED_MODE_OPER:\n\t\ttemp |= 0x0001;\n\t\tbreak;\n\tcase ELINK_LED_MODE_ON:\n\t\ttemp |= 0x00ff;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\telink_cl22_write(sc, phy,\n\t\t\t MDIO_REG_GPHY_SHADOW,\n\t\t\t MDIO_REG_GPHY_SHADOW_WR_ENA | temp);\n\treturn;\n}\n\nstatic void elink_54618se_link_reset(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t cfg_pin;\n\tuint8_t port;\n\n\t/* In case of no EPIO routed to reset the GPHY, put it\n\t * in low power mode.\n\t */\n\telink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);\n\t/* This works with E3 only, no need to check the chip\n\t * before determining the port.\n\t */\n\tport = params->port;\n\tcfg_pin = (REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_hw_config[port].\n\t\t\t\t e3_cmn_pin_cfg)) &\n\t\t PORT_HW_CFG_E3_PHY_RESET_MASK) >>\n\t PORT_HW_CFG_E3_PHY_RESET_SHIFT;\n\n\t/* Drive pin low to put GPHY in reset. */\n\telink_set_cfg_pin(sc, cfg_pin, 0);\n}\n\nstatic uint8_t elink_54618se_read_status(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val;\n\tuint8_t link_up = 0;\n\tuint16_t legacy_status, legacy_speed;\n\n\t/* Get speed operation status */\n\telink_cl22_read(sc, phy, MDIO_REG_GPHY_AUX_STATUS, &legacy_status);\n\tPMD_DRV_LOG(DEBUG, \"54618SE read_status: 0x%x\", legacy_status);\n\n\t/* Read status to clear the PHY interrupt. */\n\telink_cl22_read(sc, phy, MDIO_REG_INTR_STATUS, &val);\n\n\tlink_up = ((legacy_status & (1 << 2)) == (1 << 2));\n\n\tif (link_up) {\n\t\tlegacy_speed = (legacy_status & (7 << 8));\n\t\tif (legacy_speed == (7 << 8)) {\n\t\t\tvars->line_speed = ELINK_SPEED_1000;\n\t\t\tvars->duplex = DUPLEX_FULL;\n\t\t} else if (legacy_speed == (6 << 8)) {\n\t\t\tvars->line_speed = ELINK_SPEED_1000;\n\t\t\tvars->duplex = DUPLEX_HALF;\n\t\t} else if (legacy_speed == (5 << 8)) {\n\t\t\tvars->line_speed = ELINK_SPEED_100;\n\t\t\tvars->duplex = DUPLEX_FULL;\n\t\t}\n\t\t/* Omitting 100Base-T4 for now */\n\t\telse if (legacy_speed == (3 << 8)) {\n\t\t\tvars->line_speed = ELINK_SPEED_100;\n\t\t\tvars->duplex = DUPLEX_HALF;\n\t\t} else if (legacy_speed == (2 << 8)) {\n\t\t\tvars->line_speed = ELINK_SPEED_10;\n\t\t\tvars->duplex = DUPLEX_FULL;\n\t\t} else if (legacy_speed == (1 << 8)) {\n\t\t\tvars->line_speed = ELINK_SPEED_10;\n\t\t\tvars->duplex = DUPLEX_HALF;\n\t\t} else\t\t/* Should not happen */\n\t\t\tvars->line_speed = 0;\n\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t \"Link is up in %dMbps, is_duplex_full= %d\",\n\t\t\t vars->line_speed, (vars->duplex == DUPLEX_FULL));\n\n\t\t/* Check legacy speed AN resolution */\n\t\telink_cl22_read(sc, phy, 0x01, &val);\n\t\tif (val & (1 << 5))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;\n\t\telink_cl22_read(sc, phy, 0x06, &val);\n\t\tif ((val & (1 << 0)) == 0)\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_PARALLEL_DETECTION_USED;\n\n\t\tPMD_DRV_LOG(DEBUG, \"BNX2X54618SE: link speed is %d\",\n\t\t\t vars->line_speed);\n\n\t\telink_ext_phy_resolve_fc(phy, params, vars);\n\n\t\tif (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {\n\t\t\t/* Report LP advertised speeds */\n\t\t\telink_cl22_read(sc, phy, 0x5, &val);\n\n\t\t\tif (val & (1 << 5))\n\t\t\t\tvars->link_status |=\n\t\t\t\t LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;\n\t\t\tif (val & (1 << 6))\n\t\t\t\tvars->link_status |=\n\t\t\t\t LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;\n\t\t\tif (val & (1 << 7))\n\t\t\t\tvars->link_status |=\n\t\t\t\t LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;\n\t\t\tif (val & (1 << 8))\n\t\t\t\tvars->link_status |=\n\t\t\t\t LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;\n\t\t\tif (val & (1 << 9))\n\t\t\t\tvars->link_status |=\n\t\t\t\t LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;\n\n\t\t\telink_cl22_read(sc, phy, 0xa, &val);\n\t\t\tif (val & (1 << 10))\n\t\t\t\tvars->link_status |=\n\t\t\t\t LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;\n\t\t\tif (val & (1 << 11))\n\t\t\t\tvars->link_status |=\n\t\t\t\t LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;\n\n\t\t\tif ((phy->flags & ELINK_FLAGS_EEE) &&\n\t\t\t elink_eee_has_cap(params))\n\t\t\t\telink_eee_an_resolve(phy, params, vars);\n\t\t}\n\t}\n\treturn link_up;\n}\n\nstatic void elink_54618se_config_loopback(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t val;\n\tuint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;\n\n\tPMD_DRV_LOG(DEBUG, \"2PMA/PMD ext_phy_loopback: 54618se\");\n\n\t/* Enable master/slave manual mmode and set to master */\n\t/* mii write 9 [bits set 11 12] */\n\telink_cl22_write(sc, phy, 0x09, 3 << 11);\n\n\t/* forced 1G and disable autoneg */\n\t/* set val [mii read 0] */\n\t/* set val [expr $val & [bits clear 6 12 13]] */\n\t/* set val [expr $val | [bits set 6 8]] */\n\t/* mii write 0 $val */\n\telink_cl22_read(sc, phy, 0x00, &val);\n\tval &= ~((1 << 6) | (1 << 12) | (1 << 13));\n\tval |= (1 << 6) | (1 << 8);\n\telink_cl22_write(sc, phy, 0x00, val);\n\n\t/* Set external loopback and Tx using 6dB coding */\n\t/* mii write 0x18 7 */\n\t/* set val [mii read 0x18] */\n\t/* mii write 0x18 [expr $val | [bits set 10 15]] */\n\telink_cl22_write(sc, phy, 0x18, 7);\n\telink_cl22_read(sc, phy, 0x18, &val);\n\telink_cl22_write(sc, phy, 0x18, val | (1 << 10) | (1 << 15));\n\n\t/* This register opens the gate for the UMAC despite its name */\n\tREG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4, 1);\n\n\t/* Maximum Frame Length (RW). Defines a 14-Bit maximum frame\n\t * length used by the MAC receive logic to check frames.\n\t */\n\tREG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);\n}\n\n/******************************************************************/\n/*\t\t\tSFX7101 PHY SECTION\t\t\t */\n/******************************************************************/\nstatic void elink_7101_config_loopback(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\t/* SFX7101_XGXS_TEST1 */\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);\n}\n\nstatic elink_status_t elink_7101_config_init(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tuint16_t fw_ver1, fw_ver2, val;\n\tstruct bnx2x_softc *sc = params->sc;\n\tPMD_DRV_LOG(DEBUG, \"Setting the SFX7101 LASI indication\");\n\n\t/* Restore normal power mode */\n\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);\n\t/* HW reset */\n\telink_ext_phy_hw_reset(sc, params->port);\n\telink_wait_reset_complete(sc, phy, params);\n\n\telink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);\n\tPMD_DRV_LOG(DEBUG, \"Setting the SFX7101 LED to blink on traffic\");\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1 << 3));\n\n\telink_ext_phy_set_pause(params, phy, vars);\n\t/* Restart autoneg */\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);\n\tval |= 0x200;\n\telink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);\n\n\t/* Save spirom version */\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);\n\n\telink_cl45_read(sc, phy,\n\t\t\tMDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);\n\telink_save_spirom_version(sc, params->port,\n\t\t\t\t (uint32_t) (fw_ver1 << 16 | fw_ver2),\n\t\t\t\t phy->ver_addr);\n\treturn ELINK_STATUS_OK;\n}\n\nstatic uint8_t elink_7101_read_status(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t link_up;\n\tuint16_t val1, val2;\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);\n\tPMD_DRV_LOG(DEBUG, \"10G-base-T LASI status 0x%x->0x%x\", val2, val1);\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);\n\telink_cl45_read(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);\n\tPMD_DRV_LOG(DEBUG, \"10G-base-T PMA status 0x%x->0x%x\", val2, val1);\n\tlink_up = ((val1 & 4) == 4);\n\t/* If link is up print the AN outcome of the SFX7101 PHY */\n\tif (link_up) {\n\t\telink_cl45_read(sc, phy,\n\t\t\t\tMDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,\n\t\t\t\t&val2);\n\t\tvars->line_speed = ELINK_SPEED_10000;\n\t\tvars->duplex = DUPLEX_FULL;\n\t\tPMD_DRV_LOG(DEBUG, \"SFX7101 AN status 0x%x->Master=%x\",\n\t\t\t val2, (val2 & (1 << 14)));\n\t\telink_ext_phy_10G_an_resolve(sc, phy, vars);\n\t\telink_ext_phy_resolve_fc(phy, params, vars);\n\n\t\t/* Read LP advertised speeds */\n\t\tif (val2 & (1 << 11))\n\t\t\tvars->link_status |=\n\t\t\t LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;\n\t}\n\treturn link_up;\n}\n\nstatic elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t * str,\n\t\t\t\t\t uint16_t * len)\n{\n\tif (*len < 5)\n\t\treturn ELINK_STATUS_ERROR;\n\tstr[0] = (spirom_ver & 0xFF);\n\tstr[1] = (spirom_ver & 0xFF00) >> 8;\n\tstr[2] = (spirom_ver & 0xFF0000) >> 16;\n\tstr[3] = (spirom_ver & 0xFF000000) >> 24;\n\tstr[4] = '\\0';\n\t*len -= 5;\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_7101_hw_reset(__rte_unused struct elink_phy *phy,\n\t\t\t\tstruct elink_params *params)\n{\n\t/* Low power mode is controlled by GPIO 2 */\n\telink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);\n\t/* The PHY reset is controlled by GPIO 1 */\n\telink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,\n\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);\n}\n\nstatic void elink_7101_set_link_led(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params, uint8_t mode)\n{\n\tuint16_t val = 0;\n\tstruct bnx2x_softc *sc = params->sc;\n\tswitch (mode) {\n\tcase ELINK_LED_MODE_FRONT_PANEL_OFF:\n\tcase ELINK_LED_MODE_OFF:\n\t\tval = 2;\n\t\tbreak;\n\tcase ELINK_LED_MODE_ON:\n\t\tval = 1;\n\t\tbreak;\n\tcase ELINK_LED_MODE_OPER:\n\t\tval = 0;\n\t\tbreak;\n\t}\n\telink_cl45_write(sc, phy,\n\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LINK_LED_CNTL, val);\n}\n\n/******************************************************************/\n/*\t\t\tSTATIC PHY DECLARATION\t\t\t */\n/******************************************************************/\n\nstatic const struct elink_phy phy_null = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,\n\t.addr = 0,\n\t.def_md_devad = 0,\n\t.flags = ELINK_FLAGS_INIT_XGXS_FIRST,\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = 0,\n\t.media_type = ELINK_ETH_PHY_NOT_PRESENT,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) NULL,\n\t.read_status = (read_status_t) NULL,\n\t.link_reset = (link_reset_t) NULL,\n\t.config_loopback = (config_loopback_t) NULL,\n\t.format_fw_ver = (format_fw_ver_t) NULL,\n\t.hw_reset = (hw_reset_t) NULL,\n\t.set_link_led = (set_link_led_t) NULL,\n\t.phy_specific_func = (phy_specific_func_t) NULL\n};\n\nstatic const struct elink_phy phy_serdes = {\n\t.type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = 0,\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_10baseT_Half |\n\t\t ELINK_SUPPORTED_10baseT_Full |\n\t\t ELINK_SUPPORTED_100baseT_Half |\n\t\t ELINK_SUPPORTED_100baseT_Full |\n\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t ELINK_SUPPORTED_2500baseX_Full |\n\t\t ELINK_SUPPORTED_TP |\n\t\t ELINK_SUPPORTED_Autoneg |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_BASE_T,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) elink_xgxs_config_init,\n\t.read_status = (read_status_t) elink_link_settings_status,\n\t.link_reset = (link_reset_t) elink_int_link_reset,\n\t.config_loopback = (config_loopback_t) NULL,\n\t.format_fw_ver = (format_fw_ver_t) NULL,\n\t.hw_reset = (hw_reset_t) NULL,\n\t.set_link_led = (set_link_led_t) NULL,\n\t.phy_specific_func = (phy_specific_func_t) NULL\n};\n\nstatic const struct elink_phy phy_xgxs = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = 0,\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_10baseT_Half |\n\t\t ELINK_SUPPORTED_10baseT_Full |\n\t\t ELINK_SUPPORTED_100baseT_Half |\n\t\t ELINK_SUPPORTED_100baseT_Full |\n\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t ELINK_SUPPORTED_2500baseX_Full |\n\t\t ELINK_SUPPORTED_10000baseT_Full |\n\t\t ELINK_SUPPORTED_FIBRE |\n\t\t ELINK_SUPPORTED_Autoneg |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_CX4,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) elink_xgxs_config_init,\n\t.read_status = (read_status_t) elink_link_settings_status,\n\t.link_reset = (link_reset_t) elink_int_link_reset,\n\t.config_loopback = (config_loopback_t) elink_set_xgxs_loopback,\n\t.format_fw_ver = (format_fw_ver_t) NULL,\n\t.hw_reset = (hw_reset_t) NULL,\n\t.set_link_led = (set_link_led_t) NULL,\n\t.phy_specific_func = (phy_specific_func_t) elink_xgxs_specific_func\n};\n\nstatic const struct elink_phy phy_warpcore = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = ELINK_FLAGS_TX_ERROR_CHECK,\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_10baseT_Half |\n\t\t ELINK_SUPPORTED_10baseT_Full |\n\t\t ELINK_SUPPORTED_100baseT_Half |\n\t\t ELINK_SUPPORTED_100baseT_Full |\n\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t ELINK_SUPPORTED_10000baseT_Full |\n\t\t ELINK_SUPPORTED_20000baseKR2_Full |\n\t\t ELINK_SUPPORTED_20000baseMLD2_Full |\n\t\t ELINK_SUPPORTED_FIBRE |\n\t\t ELINK_SUPPORTED_Autoneg |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_UNSPECIFIED,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t/* req_duplex = */ 0,\n\t/* rsrv = */ 0,\n\t.config_init = (config_init_t) elink_warpcore_config_init,\n\t.read_status = (read_status_t) elink_warpcore_read_status,\n\t.link_reset = (link_reset_t) elink_warpcore_link_reset,\n\t.config_loopback = (config_loopback_t) elink_set_warpcore_loopback,\n\t.format_fw_ver = (format_fw_ver_t) NULL,\n\t.hw_reset = (hw_reset_t) elink_warpcore_hw_reset,\n\t.set_link_led = (set_link_led_t) NULL,\n\t.phy_specific_func = (phy_specific_func_t) NULL\n};\n\nstatic const struct elink_phy phy_7101 = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_10000baseT_Full |\n\t\t ELINK_SUPPORTED_TP |\n\t\t ELINK_SUPPORTED_Autoneg |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_BASE_T,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) elink_7101_config_init,\n\t.read_status = (read_status_t) elink_7101_read_status,\n\t.link_reset = (link_reset_t) elink_common_ext_link_reset,\n\t.config_loopback = (config_loopback_t) elink_7101_config_loopback,\n\t.format_fw_ver = (format_fw_ver_t) elink_7101_format_ver,\n\t.hw_reset = (hw_reset_t) elink_7101_hw_reset,\n\t.set_link_led = (set_link_led_t) elink_7101_set_link_led,\n\t.phy_specific_func = (phy_specific_func_t) NULL\n};\n\nstatic const struct elink_phy phy_8073 = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = 0,\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_10000baseT_Full |\n\t\t ELINK_SUPPORTED_2500baseX_Full |\n\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t ELINK_SUPPORTED_FIBRE |\n\t\t ELINK_SUPPORTED_Autoneg |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_KR,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) elink_8073_config_init,\n\t.read_status = (read_status_t) elink_8073_read_status,\n\t.link_reset = (link_reset_t) elink_8073_link_reset,\n\t.config_loopback = (config_loopback_t) NULL,\n\t.format_fw_ver = (format_fw_ver_t) elink_format_ver,\n\t.hw_reset = (hw_reset_t) NULL,\n\t.set_link_led = (set_link_led_t) NULL,\n\t.phy_specific_func = (phy_specific_func_t) elink_8073_specific_func\n};\n\nstatic const struct elink_phy phy_8705 = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = ELINK_FLAGS_INIT_XGXS_FIRST,\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_10000baseT_Full |\n\t\t ELINK_SUPPORTED_FIBRE |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_XFP_FIBER,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) elink_8705_config_init,\n\t.read_status = (read_status_t) elink_8705_read_status,\n\t.link_reset = (link_reset_t) elink_common_ext_link_reset,\n\t.config_loopback = (config_loopback_t) NULL,\n\t.format_fw_ver = (format_fw_ver_t) elink_null_format_ver,\n\t.hw_reset = (hw_reset_t) NULL,\n\t.set_link_led = (set_link_led_t) NULL,\n\t.phy_specific_func = (phy_specific_func_t) NULL\n};\n\nstatic const struct elink_phy phy_8706 = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = ELINK_FLAGS_INIT_XGXS_FIRST,\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_10000baseT_Full |\n\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t ELINK_SUPPORTED_FIBRE |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) elink_8706_config_init,\n\t.read_status = (read_status_t) elink_8706_read_status,\n\t.link_reset = (link_reset_t) elink_common_ext_link_reset,\n\t.config_loopback = (config_loopback_t) NULL,\n\t.format_fw_ver = (format_fw_ver_t) elink_format_ver,\n\t.hw_reset = (hw_reset_t) NULL,\n\t.set_link_led = (set_link_led_t) NULL,\n\t.phy_specific_func = (phy_specific_func_t) NULL\n};\n\nstatic const struct elink_phy phy_8726 = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = (ELINK_FLAGS_INIT_XGXS_FIRST | ELINK_FLAGS_TX_ERROR_CHECK),\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_10000baseT_Full |\n\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t ELINK_SUPPORTED_Autoneg |\n\t\t ELINK_SUPPORTED_FIBRE |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_NOT_PRESENT,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) elink_8726_config_init,\n\t.read_status = (read_status_t) elink_8726_read_status,\n\t.link_reset = (link_reset_t) elink_8726_link_reset,\n\t.config_loopback = (config_loopback_t) elink_8726_config_loopback,\n\t.format_fw_ver = (format_fw_ver_t) elink_format_ver,\n\t.hw_reset = (hw_reset_t) NULL,\n\t.set_link_led = (set_link_led_t) NULL,\n\t.phy_specific_func = (phy_specific_func_t) NULL\n};\n\nstatic const struct elink_phy phy_8727 = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | ELINK_FLAGS_TX_ERROR_CHECK),\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_10000baseT_Full |\n\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t ELINK_SUPPORTED_FIBRE |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_NOT_PRESENT,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) elink_8727_config_init,\n\t.read_status = (read_status_t) elink_8727_read_status,\n\t.link_reset = (link_reset_t) elink_8727_link_reset,\n\t.config_loopback = (config_loopback_t) NULL,\n\t.format_fw_ver = (format_fw_ver_t) elink_format_ver,\n\t.hw_reset = (hw_reset_t) elink_8727_hw_reset,\n\t.set_link_led = (set_link_led_t) elink_8727_set_link_led,\n\t.phy_specific_func = (phy_specific_func_t) elink_8727_specific_func\n};\n\nstatic const struct elink_phy phy_8481 = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n\t ELINK_FLAGS_REARM_LATCH_SIGNAL,\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_10baseT_Half |\n\t\t ELINK_SUPPORTED_10baseT_Full |\n\t\t ELINK_SUPPORTED_100baseT_Half |\n\t\t ELINK_SUPPORTED_100baseT_Full |\n\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t ELINK_SUPPORTED_10000baseT_Full |\n\t\t ELINK_SUPPORTED_TP |\n\t\t ELINK_SUPPORTED_Autoneg |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_BASE_T,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) elink_8481_config_init,\n\t.read_status = (read_status_t) elink_848xx_read_status,\n\t.link_reset = (link_reset_t) elink_8481_link_reset,\n\t.config_loopback = (config_loopback_t) NULL,\n\t.format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver,\n\t.hw_reset = (hw_reset_t) elink_8481_hw_reset,\n\t.set_link_led = (set_link_led_t) elink_848xx_set_link_led,\n\t.phy_specific_func = (phy_specific_func_t) NULL\n};\n\nstatic const struct elink_phy phy_84823 = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n\t\t ELINK_FLAGS_REARM_LATCH_SIGNAL | ELINK_FLAGS_TX_ERROR_CHECK),\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_10baseT_Half |\n\t\t ELINK_SUPPORTED_10baseT_Full |\n\t\t ELINK_SUPPORTED_100baseT_Half |\n\t\t ELINK_SUPPORTED_100baseT_Full |\n\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t ELINK_SUPPORTED_10000baseT_Full |\n\t\t ELINK_SUPPORTED_TP |\n\t\t ELINK_SUPPORTED_Autoneg |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_BASE_T,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) elink_848x3_config_init,\n\t.read_status = (read_status_t) elink_848xx_read_status,\n\t.link_reset = (link_reset_t) elink_848x3_link_reset,\n\t.config_loopback = (config_loopback_t) NULL,\n\t.format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver,\n\t.hw_reset = (hw_reset_t) NULL,\n\t.set_link_led = (set_link_led_t) elink_848xx_set_link_led,\n\t.phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func\n};\n\nstatic const struct elink_phy phy_84833 = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n\t\t ELINK_FLAGS_REARM_LATCH_SIGNAL |\n\t\t ELINK_FLAGS_TX_ERROR_CHECK | ELINK_FLAGS_TEMPERATURE),\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_100baseT_Half |\n\t\t ELINK_SUPPORTED_100baseT_Full |\n\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t ELINK_SUPPORTED_10000baseT_Full |\n\t\t ELINK_SUPPORTED_TP |\n\t\t ELINK_SUPPORTED_Autoneg |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_BASE_T,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) elink_848x3_config_init,\n\t.read_status = (read_status_t) elink_848xx_read_status,\n\t.link_reset = (link_reset_t) elink_848x3_link_reset,\n\t.config_loopback = (config_loopback_t) NULL,\n\t.format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver,\n\t.hw_reset = (hw_reset_t) elink_84833_hw_reset_phy,\n\t.set_link_led = (set_link_led_t) elink_848xx_set_link_led,\n\t.phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func\n};\n\nstatic const struct elink_phy phy_84834 = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |\n\t ELINK_FLAGS_REARM_LATCH_SIGNAL,\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_100baseT_Half |\n\t\t ELINK_SUPPORTED_100baseT_Full |\n\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t ELINK_SUPPORTED_10000baseT_Full |\n\t\t ELINK_SUPPORTED_TP |\n\t\t ELINK_SUPPORTED_Autoneg |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_BASE_T,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t.req_duplex = 0,\n\t.rsrv = 0,\n\t.config_init = (config_init_t) elink_848x3_config_init,\n\t.read_status = (read_status_t) elink_848xx_read_status,\n\t.link_reset = (link_reset_t) elink_848x3_link_reset,\n\t.config_loopback = (config_loopback_t) NULL,\n\t.format_fw_ver = (format_fw_ver_t) elink_848xx_format_ver,\n\t.hw_reset = (hw_reset_t) elink_84833_hw_reset_phy,\n\t.set_link_led = (set_link_led_t) elink_848xx_set_link_led,\n\t.phy_specific_func = (phy_specific_func_t) elink_848xx_specific_func\n};\n\nstatic const struct elink_phy phy_54618se = {\n\t.type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE,\n\t.addr = 0xff,\n\t.def_md_devad = 0,\n\t.flags = ELINK_FLAGS_INIT_XGXS_FIRST,\n\t.rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},\n\t.mdio_ctrl = 0,\n\t.supported = (ELINK_SUPPORTED_10baseT_Half |\n\t\t ELINK_SUPPORTED_10baseT_Full |\n\t\t ELINK_SUPPORTED_100baseT_Half |\n\t\t ELINK_SUPPORTED_100baseT_Full |\n\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t ELINK_SUPPORTED_TP |\n\t\t ELINK_SUPPORTED_Autoneg |\n\t\t ELINK_SUPPORTED_Pause | ELINK_SUPPORTED_Asym_Pause),\n\t.media_type = ELINK_ETH_PHY_BASE_T,\n\t.ver_addr = 0,\n\t.req_flow_ctrl = 0,\n\t.req_line_speed = 0,\n\t.speed_cap_mask = 0,\n\t/* req_duplex = */ 0,\n\t/* rsrv = */ 0,\n\t.config_init = (config_init_t) elink_54618se_config_init,\n\t.read_status = (read_status_t) elink_54618se_read_status,\n\t.link_reset = (link_reset_t) elink_54618se_link_reset,\n\t.config_loopback = (config_loopback_t) elink_54618se_config_loopback,\n\t.format_fw_ver = (format_fw_ver_t) NULL,\n\t.hw_reset = (hw_reset_t) NULL,\n\t.set_link_led = (set_link_led_t) elink_5461x_set_link_led,\n\t.phy_specific_func = (phy_specific_func_t) elink_54618se_specific_func\n};\n\n/*****************************************************************/\n/* */\n/* Populate the phy according. Main function: elink_populate_phy */\n/* */\n/*****************************************************************/\n\nstatic void elink_populate_preemphasis(struct bnx2x_softc *sc,\n\t\t\t\t uint32_t shmem_base,\n\t\t\t\t struct elink_phy *phy, uint8_t port,\n\t\t\t\t uint8_t phy_index)\n{\n\t/* Get the 4 lanes xgxs config rx and tx */\n\tuint32_t rx = 0, tx = 0, i;\n\tfor (i = 0; i < 2; i++) {\n\t\t/* INT_PHY and ELINK_EXT_PHY1 share the same value location in\n\t\t * the shmem. When num_phys is greater than 1, than this value\n\t\t * applies only to ELINK_EXT_PHY1\n\t\t */\n\t\tif (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {\n\t\t\trx = REG_RD(sc, shmem_base +\n\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t dev_info.port_hw_config[port].\n\t\t\t\t\t xgxs_config_rx[i << 1]));\n\n\t\t\ttx = REG_RD(sc, shmem_base +\n\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t dev_info.port_hw_config[port].\n\t\t\t\t\t xgxs_config_tx[i << 1]));\n\t\t} else {\n\t\t\trx = REG_RD(sc, shmem_base +\n\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t dev_info.port_hw_config[port].\n\t\t\t\t\t xgxs_config2_rx[i << 1]));\n\n\t\t\ttx = REG_RD(sc, shmem_base +\n\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t dev_info.port_hw_config[port].\n\t\t\t\t\t xgxs_config2_rx[i << 1]));\n\t\t}\n\n\t\tphy->rx_preemphasis[i << 1] = ((rx >> 16) & 0xffff);\n\t\tphy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);\n\n\t\tphy->tx_preemphasis[i << 1] = ((tx >> 16) & 0xffff);\n\t\tphy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);\n\t}\n}\n\nstatic uint32_t elink_get_ext_phy_config(struct bnx2x_softc *sc,\n\t\t\t\t\t uint32_t shmem_base, uint8_t phy_index,\n\t\t\t\t\t uint8_t port)\n{\n\tuint32_t ext_phy_config = 0;\n\tswitch (phy_index) {\n\tcase ELINK_EXT_PHY1:\n\t\text_phy_config = REG_RD(sc, shmem_base +\n\t\t\t\t\toffsetof(struct shmem_region,\n\t\t\t\t\t\t dev_info.port_hw_config[port].\n\t\t\t\t\t\t external_phy_config));\n\t\tbreak;\n\tcase ELINK_EXT_PHY2:\n\t\text_phy_config = REG_RD(sc, shmem_base +\n\t\t\t\t\toffsetof(struct shmem_region,\n\t\t\t\t\t\t dev_info.port_hw_config[port].\n\t\t\t\t\t\t external_phy_config2));\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(DEBUG, \"Invalid phy_index %d\", phy_index);\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\n\treturn ext_phy_config;\n}\n\nstatic elink_status_t elink_populate_int_phy(struct bnx2x_softc *sc,\n\t\t\t\t\t uint32_t shmem_base, uint8_t port,\n\t\t\t\t\t struct elink_phy *phy)\n{\n\tuint32_t phy_addr;\n\t__rte_unused uint32_t chip_id;\n\tuint32_t switch_cfg = (REG_RD(sc, shmem_base +\n\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t dev_info.\n\t\t\t\t\t port_feature_config[port].\n\t\t\t\t\t link_config)) &\n\t\t\t PORT_FEATURE_CONNECTED_SWITCH_MASK);\n\tchip_id =\n\t (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |\n\t ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);\n\n\tPMD_DRV_LOG(DEBUG, \":chip_id = 0x%x\", chip_id);\n\tif (USES_WARPCORE(sc)) {\n\t\tuint32_t serdes_net_if;\n\t\tphy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);\n\t\t*phy = phy_warpcore;\n\t\tif (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)\n\t\t\tphy->flags |= ELINK_FLAGS_4_PORT_MODE;\n\t\telse\n\t\t\tphy->flags &= ~ELINK_FLAGS_4_PORT_MODE;\n\t\t/* Check Dual mode */\n\t\tserdes_net_if = (REG_RD(sc, shmem_base +\n\t\t\t\t\toffsetof(struct shmem_region,\n\t\t\t\t\t\t dev_info.port_hw_config[port].\n\t\t\t\t\t\t default_cfg)) &\n\t\t\t\t PORT_HW_CFG_NET_SERDES_IF_MASK);\n\t\t/* Set the appropriate supported and flags indications per\n\t\t * interface type of the chip\n\t\t */\n\t\tswitch (serdes_net_if) {\n\t\tcase PORT_HW_CFG_NET_SERDES_IF_SGMII:\n\t\t\tphy->supported &= (ELINK_SUPPORTED_10baseT_Half |\n\t\t\t\t\t ELINK_SUPPORTED_10baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_100baseT_Half |\n\t\t\t\t\t ELINK_SUPPORTED_100baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_FIBRE |\n\t\t\t\t\t ELINK_SUPPORTED_Autoneg |\n\t\t\t\t\t ELINK_SUPPORTED_Pause |\n\t\t\t\t\t ELINK_SUPPORTED_Asym_Pause);\n\t\t\tphy->media_type = ELINK_ETH_PHY_BASE_T;\n\t\t\tbreak;\n\t\tcase PORT_HW_CFG_NET_SERDES_IF_XFI:\n\t\t\tphy->supported &= (ELINK_SUPPORTED_1000baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_FIBRE |\n\t\t\t\t\t ELINK_SUPPORTED_Pause |\n\t\t\t\t\t ELINK_SUPPORTED_Asym_Pause);\n\t\t\tphy->media_type = ELINK_ETH_PHY_XFP_FIBER;\n\t\t\tbreak;\n\t\tcase PORT_HW_CFG_NET_SERDES_IF_SFI:\n\t\t\tphy->supported &= (ELINK_SUPPORTED_1000baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_FIBRE |\n\t\t\t\t\t ELINK_SUPPORTED_Pause |\n\t\t\t\t\t ELINK_SUPPORTED_Asym_Pause);\n\t\t\tphy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;\n\t\t\tbreak;\n\t\tcase PORT_HW_CFG_NET_SERDES_IF_KR:\n\t\t\tphy->media_type = ELINK_ETH_PHY_KR;\n\t\t\tphy->supported &= (ELINK_SUPPORTED_1000baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_FIBRE |\n\t\t\t\t\t ELINK_SUPPORTED_Autoneg |\n\t\t\t\t\t ELINK_SUPPORTED_Pause |\n\t\t\t\t\t ELINK_SUPPORTED_Asym_Pause);\n\t\t\tbreak;\n\t\tcase PORT_HW_CFG_NET_SERDES_IF_DXGXS:\n\t\t\tphy->media_type = ELINK_ETH_PHY_KR;\n\t\t\tphy->flags |= ELINK_FLAGS_WC_DUAL_MODE;\n\t\t\tphy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |\n\t\t\t\t\t ELINK_SUPPORTED_FIBRE |\n\t\t\t\t\t ELINK_SUPPORTED_Pause |\n\t\t\t\t\t ELINK_SUPPORTED_Asym_Pause);\n\t\t\tbreak;\n\t\tcase PORT_HW_CFG_NET_SERDES_IF_KR2:\n\t\t\tphy->media_type = ELINK_ETH_PHY_KR;\n\t\t\tphy->flags |= ELINK_FLAGS_WC_DUAL_MODE;\n\t\t\tphy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |\n\t\t\t\t\t ELINK_SUPPORTED_10000baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_1000baseT_Full |\n\t\t\t\t\t ELINK_SUPPORTED_Autoneg |\n\t\t\t\t\t ELINK_SUPPORTED_FIBRE |\n\t\t\t\t\t ELINK_SUPPORTED_Pause |\n\t\t\t\t\t ELINK_SUPPORTED_Asym_Pause);\n\t\t\tphy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(DEBUG, \"Unknown WC interface type 0x%x\",\n\t\t\t\t serdes_net_if);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Enable MDC/MDIO work-around for E3 A0 since free running MDC\n\t\t * was not set as expected. For B0, ECO will be enabled so there\n\t\t * won't be an issue there\n\t\t */\n\t\tif (CHIP_REV(sc) == CHIP_REV_Ax)\n\t\t\tphy->flags |= ELINK_FLAGS_MDC_MDIO_WA;\n\t\telse\n\t\t\tphy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;\n\t} else {\n\t\tswitch (switch_cfg) {\n\t\tcase ELINK_SWITCH_CFG_1G:\n\t\t\tphy_addr = REG_RD(sc,\n\t\t\t\t\t NIG_REG_SERDES0_CTRL_PHY_ADDR +\n\t\t\t\t\t port * 0x10);\n\t\t\t*phy = phy_serdes;\n\t\t\tbreak;\n\t\tcase ELINK_SWITCH_CFG_10G:\n\t\t\tphy_addr = REG_RD(sc,\n\t\t\t\t\t NIG_REG_XGXS0_CTRL_PHY_ADDR +\n\t\t\t\t\t port * 0x18);\n\t\t\t*phy = phy_xgxs;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(DEBUG, \"Invalid switch_cfg\");\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t}\n\tphy->addr = (uint8_t) phy_addr;\n\tphy->mdio_ctrl = elink_get_emac_base(sc,\n\t\t\t\t\t SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,\n\t\t\t\t\t port);\n\tif (CHIP_IS_E2(sc))\n\t\tphy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;\n\telse\n\t\tphy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;\n\n\tPMD_DRV_LOG(DEBUG, \"Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\",\n\t\t port, phy->addr, phy->mdio_ctrl);\n\n\telink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_populate_ext_phy(struct bnx2x_softc *sc,\n\t\t\t\t\t uint8_t phy_index,\n\t\t\t\t\t uint32_t shmem_base,\n\t\t\t\t\t uint32_t shmem2_base,\n\t\t\t\t\t uint8_t port,\n\t\t\t\t\t struct elink_phy *phy)\n{\n\tuint32_t ext_phy_config, phy_type, config2;\n\tuint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;\n\text_phy_config = elink_get_ext_phy_config(sc, shmem_base,\n\t\t\t\t\t\t phy_index, port);\n\tphy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);\n\t/* Select the phy type */\n\tswitch (phy_type) {\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073:\n\t\tmdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;\n\t\t*phy = phy_8073;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705:\n\t\t*phy = phy_8705;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706:\n\t\t*phy = phy_8706;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:\n\t\tmdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;\n\t\t*phy = phy_8726;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC:\n\t\t/* BNX2X8727_NOC => BNX2X8727 no over current */\n\t\tmdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;\n\t\t*phy = phy_8727;\n\t\tphy->flags |= ELINK_FLAGS_NOC;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:\n\t\tmdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;\n\t\t*phy = phy_8727;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481:\n\t\t*phy = phy_8481;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823:\n\t\t*phy = phy_84823;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:\n\t\t*phy = phy_84833;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:\n\t\t*phy = phy_84834;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616:\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE:\n\t\t*phy = phy_54618se;\n\t\tif (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE)\n\t\t\tphy->flags |= ELINK_FLAGS_EEE;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:\n\t\t*phy = phy_7101;\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:\n\t\t*phy = phy_null;\n\t\treturn ELINK_STATUS_ERROR;\n\tdefault:\n\t\t*phy = phy_null;\n\t\t/* In case external PHY wasn't found */\n\t\tif ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&\n\t\t (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\treturn ELINK_STATUS_OK;\n\t}\n\n\tphy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);\n\telink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);\n\n\t/* The shmem address of the phy version is located on different\n\t * structures. In case this structure is too old, do not set\n\t * the address\n\t */\n\tconfig2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,\n\t\t\t\t\t\t dev_info.shared_hw_config.\n\t\t\t\t\t\t config2));\n\tif (phy_index == ELINK_EXT_PHY1) {\n\t\tphy->ver_addr = shmem_base + offsetof(struct shmem_region,\n\t\t\t\t\t\t port_mb[port].\n\t\t\t\t\t\t ext_phy_fw_version);\n\n\t\t/* Check specific mdc mdio settings */\n\t\tif (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)\n\t\t\tmdc_mdio_access = config2 &\n\t\t\t SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;\n\t} else {\n\t\tuint32_t size = REG_RD(sc, shmem2_base);\n\n\t\tif (size > offsetof(struct shmem2_region, ext_phy_fw_version2)) {\n\t\t\tphy->ver_addr = shmem2_base +\n\t\t\t offsetof(struct shmem2_region,\n\t\t\t\t ext_phy_fw_version2[port]);\n\t\t}\n\t\t/* Check specific mdc mdio settings */\n\t\tif (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)\n\t\t\tmdc_mdio_access = (config2 &\n\t\t\t\t\t SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)\n\t\t\t >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -\n\t\t\t\tSHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);\n\t}\n\tphy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);\n\n\tif (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833) ||\n\t (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834)) &&\n\t (phy->ver_addr)) {\n\t\t/* Remove 100Mb link supported for BNX2X84833/4 when phy fw\n\t\t * version lower than or equal to 1.39\n\t\t */\n\t\tuint32_t raw_ver = REG_RD(sc, phy->ver_addr);\n\t\tif (((raw_ver & 0x7F) <= 39) && (((raw_ver & 0xF80) >> 7) <= 1))\n\t\t\tphy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |\n\t\t\t\t\t ELINK_SUPPORTED_100baseT_Full);\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"phy_type 0x%x port %d found in index %d\",\n\t\t phy_type, port, phy_index);\n\tPMD_DRV_LOG(DEBUG, \" addr=0x%x, mdio_ctl=0x%x\",\n\t\t phy->addr, phy->mdio_ctrl);\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_populate_phy(struct bnx2x_softc *sc,\n\t\t\t\t\t uint8_t phy_index, uint32_t shmem_base,\n\t\t\t\t\t uint32_t shmem2_base, uint8_t port,\n\t\t\t\t\t struct elink_phy *phy)\n{\n\telink_status_t status = ELINK_STATUS_OK;\n\tphy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;\n\tif (phy_index == ELINK_INT_PHY)\n\t\treturn elink_populate_int_phy(sc, shmem_base, port, phy);\n\tstatus = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base,\n\t\t\t\t\tport, phy);\n\treturn status;\n}\n\nstatic void elink_phy_def_cfg(struct elink_params *params,\n\t\t\t struct elink_phy *phy, uint8_t phy_index)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t link_config;\n\t/* Populate the default phy configuration for MF mode */\n\tif (phy_index == ELINK_EXT_PHY2) {\n\t\tlink_config = REG_RD(sc, params->shmem_base +\n\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t dev_info.port_feature_config\n\t\t\t\t\t [params->port].link_config2));\n\t\tphy->speed_cap_mask =\n\t\t REG_RD(sc,\n\t\t\t params->shmem_base + offsetof(struct shmem_region,\n\t\t\t\t\t\t\t dev_info.port_hw_config\n\t\t\t\t\t\t\t [params->port].\n\t\t\t\t\t\t\t speed_capability_mask2));\n\t} else {\n\t\tlink_config = REG_RD(sc, params->shmem_base +\n\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t dev_info.port_feature_config\n\t\t\t\t\t [params->port].link_config));\n\t\tphy->speed_cap_mask =\n\t\t REG_RD(sc,\n\t\t\t params->shmem_base + offsetof(struct shmem_region,\n\t\t\t\t\t\t\t dev_info.port_hw_config\n\t\t\t\t\t\t\t [params->port].\n\t\t\t\t\t\t\t speed_capability_mask));\n\t}\n\n\tPMD_DRV_LOG(DEBUG,\n\t\t \"Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\",\n\t\t phy_index, link_config, phy->speed_cap_mask);\n\n\tphy->req_duplex = DUPLEX_FULL;\n\tswitch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {\n\tcase PORT_FEATURE_LINK_SPEED_10M_HALF:\n\t\tphy->req_duplex = DUPLEX_HALF;\n\tcase PORT_FEATURE_LINK_SPEED_10M_FULL:\n\t\tphy->req_line_speed = ELINK_SPEED_10;\n\t\tbreak;\n\tcase PORT_FEATURE_LINK_SPEED_100M_HALF:\n\t\tphy->req_duplex = DUPLEX_HALF;\n\tcase PORT_FEATURE_LINK_SPEED_100M_FULL:\n\t\tphy->req_line_speed = ELINK_SPEED_100;\n\t\tbreak;\n\tcase PORT_FEATURE_LINK_SPEED_1G:\n\t\tphy->req_line_speed = ELINK_SPEED_1000;\n\t\tbreak;\n\tcase PORT_FEATURE_LINK_SPEED_2_5G:\n\t\tphy->req_line_speed = ELINK_SPEED_2500;\n\t\tbreak;\n\tcase PORT_FEATURE_LINK_SPEED_10G_CX4:\n\t\tphy->req_line_speed = ELINK_SPEED_10000;\n\t\tbreak;\n\tdefault:\n\t\tphy->req_line_speed = ELINK_SPEED_AUTO_NEG;\n\t\tbreak;\n\t}\n\n\tswitch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {\n\tcase PORT_FEATURE_FLOW_CONTROL_AUTO:\n\t\tphy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;\n\t\tbreak;\n\tcase PORT_FEATURE_FLOW_CONTROL_TX:\n\t\tphy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;\n\t\tbreak;\n\tcase PORT_FEATURE_FLOW_CONTROL_RX:\n\t\tphy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;\n\t\tbreak;\n\tcase PORT_FEATURE_FLOW_CONTROL_BOTH:\n\t\tphy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;\n\t\tbreak;\n\tdefault:\n\t\tphy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\t\tbreak;\n\t}\n}\n\nuint32_t elink_phy_selection(struct elink_params *params)\n{\n\tuint32_t phy_config_swapped, prio_cfg;\n\tuint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;\n\n\tphy_config_swapped = params->multi_phy_config &\n\t PORT_HW_CFG_PHY_SWAPPED_ENABLED;\n\n\tprio_cfg = params->multi_phy_config & PORT_HW_CFG_PHY_SELECTION_MASK;\n\n\tif (phy_config_swapped) {\n\t\tswitch (prio_cfg) {\n\t\tcase PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:\n\t\t\treturn_cfg =\n\t\t\t PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;\n\t\t\tbreak;\n\t\tcase PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:\n\t\t\treturn_cfg =\n\t\t\t PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;\n\t\t\tbreak;\n\t\tcase PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:\n\t\t\treturn_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;\n\t\t\tbreak;\n\t\tcase PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:\n\t\t\treturn_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;\n\t\t\tbreak;\n\t\t}\n\t} else\n\t\treturn_cfg = prio_cfg;\n\n\treturn return_cfg;\n}\n\nelink_status_t elink_phy_probe(struct elink_params * params)\n{\n\tuint8_t phy_index, actual_phy_idx;\n\tuint32_t phy_config_swapped, sync_offset, media_types;\n\tstruct bnx2x_softc *sc = params->sc;\n\tstruct elink_phy *phy;\n\tparams->num_phys = 0;\n\tPMD_DRV_LOG(DEBUG, \"Begin phy probe\");\n#ifdef ELINK_INCLUDE_EMUL\n\tif (CHIP_REV_IS_EMUL(sc))\n\t\treturn ELINK_STATUS_OK;\n#endif\n\tphy_config_swapped = params->multi_phy_config &\n\t PORT_HW_CFG_PHY_SWAPPED_ENABLED;\n\n\tfor (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {\n\t\tactual_phy_idx = phy_index;\n\t\tif (phy_config_swapped) {\n\t\t\tif (phy_index == ELINK_EXT_PHY1)\n\t\t\t\tactual_phy_idx = ELINK_EXT_PHY2;\n\t\t\telse if (phy_index == ELINK_EXT_PHY2)\n\t\t\t\tactual_phy_idx = ELINK_EXT_PHY1;\n\t\t}\n\t\tPMD_DRV_LOG(DEBUG, \"phy_config_swapped %x, phy_index %x,\"\n\t\t\t \" actual_phy_idx %x\", phy_config_swapped,\n\t\t\t phy_index, actual_phy_idx);\n\t\tphy = ¶ms->phy[actual_phy_idx];\n\t\tif (elink_populate_phy(sc, phy_index, params->shmem_base,\n\t\t\t\t params->shmem2_base, params->port,\n\t\t\t\t phy) != ELINK_STATUS_OK) {\n\t\t\tparams->num_phys = 0;\n\t\t\tPMD_DRV_LOG(DEBUG, \"phy probe failed in phy index %d\",\n\t\t\t\t phy_index);\n\t\t\tfor (phy_index = ELINK_INT_PHY;\n\t\t\t phy_index < ELINK_MAX_PHYS; phy_index++)\n\t\t\t\t*phy = phy_null;\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t\tif (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)\n\t\t\tbreak;\n\n\t\tif (params->feature_config_flags &\n\t\t ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)\n\t\t\tphy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;\n\n\t\tif (!(params->feature_config_flags &\n\t\t ELINK_FEATURE_CONFIG_MT_SUPPORT))\n\t\t\tphy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;\n\n\t\tsync_offset = params->shmem_base +\n\t\t offsetof(struct shmem_region,\n\t\t\t dev_info.port_hw_config[params->port].media_type);\n\t\tmedia_types = REG_RD(sc, sync_offset);\n\n\t\t/* Update media type for non-PMF sync only for the first time\n\t\t * In case the media type changes afterwards, it will be updated\n\t\t * using the update_status function\n\t\t */\n\t\tif ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<\n\t\t\t\t (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *\n\t\t\t\t actual_phy_idx))) == 0) {\n\t\t\tmedia_types |= ((phy->media_type &\n\t\t\t\t\t PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<\n\t\t\t\t\t(PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *\n\t\t\t\t\t actual_phy_idx));\n\t\t}\n\t\tREG_WR(sc, sync_offset, media_types);\n\n\t\telink_phy_def_cfg(params, phy, phy_index);\n\t\tparams->num_phys++;\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"End phy probe. #phys found %x\", params->num_phys);\n\treturn ELINK_STATUS_OK;\n}\n\n#ifdef ELINK_INCLUDE_EMUL\nstatic elink_status_t elink_init_e3_emul_mac(struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tvars->line_speed = params->req_line_speed[0];\n\t/* In case link speed is auto, set speed the highest as possible */\n\tif (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {\n\t\tif (params->feature_config_flags &\n\t\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)\n\t\t\tvars->line_speed = ELINK_SPEED_2500;\n\t\telse if (elink_is_4_port_mode(sc))\n\t\t\tvars->line_speed = ELINK_SPEED_10000;\n\t\telse\n\t\t\tvars->line_speed = ELINK_SPEED_20000;\n\t}\n\tif (vars->line_speed < ELINK_SPEED_10000) {\n\t\tif ((params->feature_config_flags &\n\t\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Invalid line speed %d while UMAC is\"\n\t\t\t\t \" disabled!\", params->req_line_speed[0]);\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t\tswitch (vars->line_speed) {\n\t\tcase ELINK_SPEED_10:\n\t\t\tvars->link_status = ELINK_LINK_10TFD;\n\t\t\tbreak;\n\t\tcase ELINK_SPEED_100:\n\t\t\tvars->link_status = ELINK_LINK_100TXFD;\n\t\t\tbreak;\n\t\tcase ELINK_SPEED_1000:\n\t\t\tvars->link_status = ELINK_LINK_1000TFD;\n\t\t\tbreak;\n\t\tcase ELINK_SPEED_2500:\n\t\t\tvars->link_status = ELINK_LINK_2500TFD;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(DEBUG, \"Invalid line speed %d for UMAC\",\n\t\t\t\t vars->line_speed);\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t\tvars->link_status |= LINK_STATUS_LINK_UP;\n\n\t\tif (params->loopback_mode == ELINK_LOOPBACK_UMAC)\n\t\t\telink_umac_enable(params, vars, 1);\n\t\telse\n\t\t\telink_umac_enable(params, vars, 0);\n\t} else {\n\t\t/* Link speed >= 10000 requires XMAC enabled */\n\t\tif (params->feature_config_flags &\n\t\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Invalid line speed %d while XMAC is\"\n\t\t\t\t \" disabled!\", params->req_line_speed[0]);\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t\t/* Check link speed */\n\t\tswitch (vars->line_speed) {\n\t\tcase ELINK_SPEED_10000:\n\t\t\tvars->link_status = ELINK_LINK_10GTFD;\n\t\t\tbreak;\n\t\tcase ELINK_SPEED_20000:\n\t\t\tvars->link_status = ELINK_LINK_20GTFD;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(DEBUG, \"Invalid line speed %d for XMAC\",\n\t\t\t\t vars->line_speed);\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t\tvars->link_status |= LINK_STATUS_LINK_UP;\n\t\tif (params->loopback_mode == ELINK_LOOPBACK_XMAC)\n\t\t\telink_xmac_enable(params, vars, 1);\n\t\telse\n\t\t\telink_xmac_enable(params, vars, 0);\n\t}\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_init_emul(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tif (CHIP_IS_E3(sc)) {\n\t\tif (elink_init_e3_emul_mac(params, vars) != ELINK_STATUS_OK)\n\t\t\treturn ELINK_STATUS_ERROR;\n\t} else {\n\t\tif (params->feature_config_flags &\n\t\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) {\n\t\t\tvars->line_speed = ELINK_SPEED_1000;\n\t\t\tvars->link_status = (LINK_STATUS_LINK_UP |\n\t\t\t\t\t ELINK_LINK_1000XFD);\n\t\t\tif (params->loopback_mode == ELINK_LOOPBACK_EMAC)\n\t\t\t\telink_emac_enable(params, vars, 1);\n\t\t\telse\n\t\t\t\telink_emac_enable(params, vars, 0);\n\t\t} else {\n\t\t\tvars->line_speed = ELINK_SPEED_10000;\n\t\t\tvars->link_status = (LINK_STATUS_LINK_UP |\n\t\t\t\t\t ELINK_LINK_10GTFD);\n\t\t\tif (params->loopback_mode == ELINK_LOOPBACK_BMAC)\n\t\t\t\telink_bmac_enable(params, vars, 1, 1);\n\t\t\telse\n\t\t\t\telink_bmac_enable(params, vars, 0, 1);\n\t\t}\n\t}\n\tvars->link_up = 1;\n\tvars->duplex = DUPLEX_FULL;\n\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\n\tif (CHIP_IS_E1x(sc))\n\t\telink_pbf_update(params, vars->flow_ctrl, vars->line_speed);\n\t/* Disable drain */\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n\n\t/* update shared memory */\n\telink_update_mng(params, vars->link_status);\n\treturn ELINK_STATUS_OK;\n}\n#endif\n#ifdef ELINK_INCLUDE_FPGA\nstatic elink_status_t elink_init_fpga(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\t/* Enable on E1.5 FPGA */\n\tstruct bnx2x_softc *sc = params->sc;\n\tvars->duplex = DUPLEX_FULL;\n\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\tvars->flow_ctrl = (ELINK_FLOW_CTRL_TX | ELINK_FLOW_CTRL_RX);\n\tvars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |\n\t\t\t LINK_STATUS_RX_FLOW_CONTROL_ENABLED);\n\tif (CHIP_IS_E3(sc)) {\n\t\tvars->line_speed = params->req_line_speed[0];\n\t\tswitch (vars->line_speed) {\n\t\tcase ELINK_SPEED_AUTO_NEG:\n\t\t\tvars->line_speed = ELINK_SPEED_2500;\n\t\tcase ELINK_SPEED_2500:\n\t\t\tvars->link_status = ELINK_LINK_2500TFD;\n\t\t\tbreak;\n\t\tcase ELINK_SPEED_1000:\n\t\t\tvars->link_status = ELINK_LINK_1000XFD;\n\t\t\tbreak;\n\t\tcase ELINK_SPEED_100:\n\t\t\tvars->link_status = ELINK_LINK_100TXFD;\n\t\t\tbreak;\n\t\tcase ELINK_SPEED_10:\n\t\t\tvars->link_status = ELINK_LINK_10TFD;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(DEBUG, \"Invalid link speed %d\",\n\t\t\t\t params->req_line_speed[0]);\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t\tvars->link_status |= LINK_STATUS_LINK_UP;\n\t\tif (params->loopback_mode == ELINK_LOOPBACK_UMAC)\n\t\t\telink_umac_enable(params, vars, 1);\n\t\telse\n\t\t\telink_umac_enable(params, vars, 0);\n\t} else {\n\t\tvars->line_speed = ELINK_SPEED_10000;\n\t\tvars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD);\n\t\tif (params->loopback_mode == ELINK_LOOPBACK_EMAC)\n\t\t\telink_emac_enable(params, vars, 1);\n\t\telse\n\t\t\telink_emac_enable(params, vars, 0);\n\t}\n\tvars->link_up = 1;\n\n\tif (CHIP_IS_E1x(sc))\n\t\telink_pbf_update(params, vars->flow_ctrl, vars->line_speed);\n\t/* Disable drain */\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n\n\t/* Update shared memory */\n\telink_update_mng(params, vars->link_status);\n\treturn ELINK_STATUS_OK;\n}\n#endif\nstatic void elink_init_bmac_loopback(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tvars->link_up = 1;\n\tvars->line_speed = ELINK_SPEED_10000;\n\tvars->duplex = DUPLEX_FULL;\n\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\tvars->mac_type = ELINK_MAC_TYPE_BMAC;\n\n\tvars->phy_flags = PHY_XGXS_FLAG;\n\n\telink_xgxs_deassert(params);\n\n\t/* Set bmac loopback */\n\telink_bmac_enable(params, vars, 1, 1);\n\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n}\n\nstatic void elink_init_emac_loopback(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tvars->link_up = 1;\n\tvars->line_speed = ELINK_SPEED_1000;\n\tvars->duplex = DUPLEX_FULL;\n\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\tvars->mac_type = ELINK_MAC_TYPE_EMAC;\n\n\tvars->phy_flags = PHY_XGXS_FLAG;\n\n\telink_xgxs_deassert(params);\n\t/* Set bmac loopback */\n\telink_emac_enable(params, vars, 1);\n\telink_emac_program(params, vars);\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n}\n\nstatic void elink_init_xmac_loopback(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tvars->link_up = 1;\n\tif (!params->req_line_speed[0])\n\t\tvars->line_speed = ELINK_SPEED_10000;\n\telse\n\t\tvars->line_speed = params->req_line_speed[0];\n\tvars->duplex = DUPLEX_FULL;\n\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\tvars->mac_type = ELINK_MAC_TYPE_XMAC;\n\tvars->phy_flags = PHY_XGXS_FLAG;\n\t/* Set WC to loopback mode since link is required to provide clock\n\t * to the XMAC in 20G mode\n\t */\n\telink_set_aer_mmd(params, ¶ms->phy[0]);\n\telink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);\n\tparams->phy[ELINK_INT_PHY].config_loopback(¶ms->phy[ELINK_INT_PHY],\n\t\t\t\t\t\t params);\n\n\telink_xmac_enable(params, vars, 1);\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n}\n\nstatic void elink_init_umac_loopback(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tvars->link_up = 1;\n\tvars->line_speed = ELINK_SPEED_1000;\n\tvars->duplex = DUPLEX_FULL;\n\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\tvars->mac_type = ELINK_MAC_TYPE_UMAC;\n\tvars->phy_flags = PHY_XGXS_FLAG;\n\telink_umac_enable(params, vars, 1);\n\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n}\n\nstatic void elink_init_xgxs_loopback(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tstruct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];\n\tvars->link_up = 1;\n\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\tvars->duplex = DUPLEX_FULL;\n\tif (params->req_line_speed[0] == ELINK_SPEED_1000)\n\t\tvars->line_speed = ELINK_SPEED_1000;\n\telse if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||\n\t\t (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE))\n\t\tvars->line_speed = ELINK_SPEED_20000;\n\telse\n\t\tvars->line_speed = ELINK_SPEED_10000;\n\n\tif (!USES_WARPCORE(sc))\n\t\telink_xgxs_deassert(params);\n\telink_link_initialize(params, vars);\n\n\tif (params->req_line_speed[0] == ELINK_SPEED_1000) {\n\t\tif (USES_WARPCORE(sc))\n\t\t\telink_umac_enable(params, vars, 0);\n\t\telse {\n\t\t\telink_emac_program(params, vars);\n\t\t\telink_emac_enable(params, vars, 0);\n\t\t}\n\t} else {\n\t\tif (USES_WARPCORE(sc))\n\t\t\telink_xmac_enable(params, vars, 0);\n\t\telse\n\t\t\telink_bmac_enable(params, vars, 0, 1);\n\t}\n\n\tif (params->loopback_mode == ELINK_LOOPBACK_XGXS) {\n\t\t/* Set 10G XGXS loopback */\n\t\tint_phy->config_loopback(int_phy, params);\n\t} else {\n\t\t/* Set external phy loopback */\n\t\tuint8_t phy_index;\n\t\tfor (phy_index = ELINK_EXT_PHY1;\n\t\t phy_index < params->num_phys; phy_index++)\n\t\t\tif (params->phy[phy_index].config_loopback)\n\t\t\t\tparams->phy[phy_index].config_loopback(¶ms->\n\t\t\t\t\t\t\t\t phy\n\t\t\t\t\t\t\t\t [phy_index],\n\t\t\t\t\t\t\t\t params);\n\t}\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n\n\telink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);\n}\n\nvoid elink_set_rx_filter(struct elink_params *params, uint8_t en)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t val = en * 0x1F;\n\n\t/* Open / close the gate between the NIG and the BRB */\n\tif (!CHIP_IS_E1x(sc))\n\t\tval |= en * 0x20;\n\tREG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port * 4, val);\n\n\tREG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port * 4, en * 0x3);\n\n\tREG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :\n\t\t NIG_REG_LLH0_BRB1_NOT_MCP), en);\n}\n\nstatic elink_status_t elink_avoid_link_flap(struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tuint32_t phy_idx;\n\tuint32_t dont_clear_stat, lfa_sts;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\t/* Sync the link parameters */\n\telink_link_status_update(params, vars);\n\n\t/*\n\t * The module verification was already done by previous link owner,\n\t * so this call is meant only to get warning message\n\t */\n\n\tfor (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {\n\t\tstruct elink_phy *phy = ¶ms->phy[phy_idx];\n\t\tif (phy->phy_specific_func) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Calling PHY specific func\");\n\t\t\tphy->phy_specific_func(phy, params, ELINK_PHY_INIT);\n\t\t}\n\t\tif ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||\n\t\t (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||\n\t\t (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))\n\t\t\telink_verify_sfp_module(phy, params);\n\t}\n\tlfa_sts = REG_RD(sc, params->lfa_base +\n\t\t\t offsetof(struct shmem_lfa, lfa_sts));\n\n\tdont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;\n\n\t/* Re-enable the NIG/MAC */\n\tif (CHIP_IS_E3(sc)) {\n\t\tif (!dont_clear_stat) {\n\t\t\tREG_WR(sc, GRCBASE_MISC +\n\t\t\t MISC_REGISTERS_RESET_REG_2_CLEAR,\n\t\t\t (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<\n\t\t\t\tparams->port));\n\t\t\tREG_WR(sc, GRCBASE_MISC +\n\t\t\t MISC_REGISTERS_RESET_REG_2_SET,\n\t\t\t (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<\n\t\t\t\tparams->port));\n\t\t}\n\t\tif (vars->line_speed < ELINK_SPEED_10000)\n\t\t\telink_umac_enable(params, vars, 0);\n\t\telse\n\t\t\telink_xmac_enable(params, vars, 0);\n\t} else {\n\t\tif (vars->line_speed < ELINK_SPEED_10000)\n\t\t\telink_emac_enable(params, vars, 0);\n\t\telse\n\t\t\telink_bmac_enable(params, vars, 0, !dont_clear_stat);\n\t}\n\n\t/* Increment LFA count */\n\tlfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |\n\t\t (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>\n\t\t LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)\n\t\t << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));\n\t/* Clear link flap reason */\n\tlfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;\n\n\tREG_WR(sc, params->lfa_base +\n\t offsetof(struct shmem_lfa, lfa_sts), lfa_sts);\n\n\t/* Disable NIG DRAIN */\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n\n\t/* Enable interrupts */\n\telink_link_int_enable(params);\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_cannot_avoid_link_flap(struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars,\n\t\t\t\t\t int lfa_status)\n{\n\tuint32_t lfa_sts, cfg_idx, tmp_val;\n\tstruct bnx2x_softc *sc = params->sc;\n\n\telink_link_reset(params, vars, 1);\n\n\tif (!params->lfa_base)\n\t\treturn;\n\t/* Store the new link parameters */\n\tREG_WR(sc, params->lfa_base +\n\t offsetof(struct shmem_lfa, req_duplex),\n\t params->req_duplex[0] | (params->req_duplex[1] << 16));\n\n\tREG_WR(sc, params->lfa_base +\n\t offsetof(struct shmem_lfa, req_flow_ctrl),\n\t params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));\n\n\tREG_WR(sc, params->lfa_base +\n\t offsetof(struct shmem_lfa, req_line_speed),\n\t params->req_line_speed[0] | (params->req_line_speed[1] << 16));\n\n\tfor (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {\n\t\tREG_WR(sc, params->lfa_base +\n\t\t offsetof(struct shmem_lfa,\n\t\t\t\tspeed_cap_mask[cfg_idx]),\n\t\t params->speed_cap_mask[cfg_idx]);\n\t}\n\n\ttmp_val = REG_RD(sc, params->lfa_base +\n\t\t\t offsetof(struct shmem_lfa, additional_config));\n\ttmp_val &= ~REQ_FC_AUTO_ADV_MASK;\n\ttmp_val |= params->req_fc_auto_adv;\n\n\tREG_WR(sc, params->lfa_base +\n\t offsetof(struct shmem_lfa, additional_config), tmp_val);\n\n\tlfa_sts = REG_RD(sc, params->lfa_base +\n\t\t\t offsetof(struct shmem_lfa, lfa_sts));\n\n\t/* Clear the \"Don't Clear Statistics\" bit, and set reason */\n\tlfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;\n\n\t/* Set link flap reason */\n\tlfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;\n\tlfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<\n\t\t LFA_LINK_FLAP_REASON_OFFSET);\n\n\t/* Increment link flap counter */\n\tlfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |\n\t\t (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>\n\t\t LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)\n\t\t << LINK_FLAP_COUNT_OFFSET));\n\tREG_WR(sc, params->lfa_base +\n\t offsetof(struct shmem_lfa, lfa_sts), lfa_sts);\n\t/* Proceed with regular link initialization */\n}\n\nelink_status_t elink_phy_init(struct elink_params *params,\n\t\t\t struct elink_vars *vars)\n{\n\tint lfa_status;\n\tstruct bnx2x_softc *sc = params->sc;\n\tPMD_DRV_LOG(DEBUG, \"Phy Initialization started\");\n\tPMD_DRV_LOG(DEBUG, \"(1) req_speed %d, req_flowctrl %d\",\n\t\t params->req_line_speed[0], params->req_flow_ctrl[0]);\n\tPMD_DRV_LOG(DEBUG, \"(2) req_speed %d, req_flowctrl %d\",\n\t\t params->req_line_speed[1], params->req_flow_ctrl[1]);\n\tPMD_DRV_LOG(DEBUG, \"req_adv_flow_ctrl 0x%x\", params->req_fc_auto_adv);\n\tvars->link_status = 0;\n\tvars->phy_link_up = 0;\n\tvars->link_up = 0;\n\tvars->line_speed = 0;\n\tvars->duplex = DUPLEX_FULL;\n\tvars->flow_ctrl = ELINK_FLOW_CTRL_NONE;\n\tvars->mac_type = ELINK_MAC_TYPE_NONE;\n\tvars->phy_flags = 0;\n\tvars->check_kr2_recovery_cnt = 0;\n\tparams->link_flags = ELINK_PHY_INITIALIZED;\n\t/* Driver opens NIG-BRB filters */\n\telink_set_rx_filter(params, 1);\n\t/* Check if link flap can be avoided */\n\tlfa_status = elink_check_lfa(params);\n\n\tif (lfa_status == 0) {\n\t\tPMD_DRV_LOG(DEBUG, \"Link Flap Avoidance in progress\");\n\t\treturn elink_avoid_link_flap(params, vars);\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"Cannot avoid link flap lfa_sta=0x%x\", lfa_status);\n\telink_cannot_avoid_link_flap(params, vars, lfa_status);\n\n\t/* Disable attentions */\n\telink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,\n\t\t (ELINK_NIG_MASK_XGXS0_LINK_STATUS |\n\t\t\tELINK_NIG_MASK_XGXS0_LINK10G |\n\t\t\tELINK_NIG_MASK_SERDES0_LINK_STATUS |\n\t\t\tELINK_NIG_MASK_MI_INT));\n#ifdef ELINK_INCLUDE_EMUL\n\tif (!(params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC))\n#endif\n\n\t\telink_emac_init(params);\n\n\tif (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)\n\t\tvars->link_status |= LINK_STATUS_PFC_ENABLED;\n\n\tif ((params->num_phys == 0) && !CHIP_REV_IS_SLOW(sc)) {\n\t\tPMD_DRV_LOG(DEBUG, \"No phy found for initialization !!\");\n\t\treturn ELINK_STATUS_ERROR;\n\t}\n\tset_phy_vars(params, vars);\n\n\tPMD_DRV_LOG(DEBUG, \"Num of phys on board: %d\", params->num_phys);\n#ifdef ELINK_INCLUDE_FPGA\n\tif (CHIP_REV_IS_FPGA(sc)) {\n\t\treturn elink_init_fpga(params, vars);\n\t} else\n#endif\n#ifdef ELINK_INCLUDE_EMUL\n\tif (CHIP_REV_IS_EMUL(sc)) {\n\t\treturn elink_init_emul(params, vars);\n\t} else\n#endif\n\t\tswitch (params->loopback_mode) {\n\t\tcase ELINK_LOOPBACK_BMAC:\n\t\t\telink_init_bmac_loopback(params, vars);\n\t\t\tbreak;\n\t\tcase ELINK_LOOPBACK_EMAC:\n\t\t\telink_init_emac_loopback(params, vars);\n\t\t\tbreak;\n\t\tcase ELINK_LOOPBACK_XMAC:\n\t\t\telink_init_xmac_loopback(params, vars);\n\t\t\tbreak;\n\t\tcase ELINK_LOOPBACK_UMAC:\n\t\t\telink_init_umac_loopback(params, vars);\n\t\t\tbreak;\n\t\tcase ELINK_LOOPBACK_XGXS:\n\t\tcase ELINK_LOOPBACK_EXT_PHY:\n\t\t\telink_init_xgxs_loopback(params, vars);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tif (!CHIP_IS_E3(sc)) {\n\t\t\t\tif (params->switch_cfg == ELINK_SWITCH_CFG_10G)\n\t\t\t\t\telink_xgxs_deassert(params);\n\t\t\t\telse\n\t\t\t\t\telink_serdes_deassert(sc, params->port);\n\t\t\t}\n\t\t\telink_link_initialize(params, vars);\n\t\t\tDELAY(1000 * 30);\n\t\t\telink_link_int_enable(params);\n\t\t\tbreak;\n\t\t}\n\telink_update_mng(params, vars->link_status);\n\n\telink_update_mng_eee(params, vars->eee_status);\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_link_reset(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars,\n\t\t\t\t uint8_t reset_ext_phy)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint8_t phy_index, port = params->port, clear_latch_ind = 0;\n\tPMD_DRV_LOG(DEBUG, \"Resetting the link of port %d\", port);\n\t/* Disable attentions */\n\tvars->link_status = 0;\n\telink_update_mng(params, vars->link_status);\n\tvars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |\n\t\t\t SHMEM_EEE_ACTIVE_BIT);\n\telink_update_mng_eee(params, vars->eee_status);\n\telink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4,\n\t\t (ELINK_NIG_MASK_XGXS0_LINK_STATUS |\n\t\t\tELINK_NIG_MASK_XGXS0_LINK10G |\n\t\t\tELINK_NIG_MASK_SERDES0_LINK_STATUS |\n\t\t\tELINK_NIG_MASK_MI_INT));\n\n\t/* Activate nig drain */\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port * 4, 1);\n\n\t/* Disable nig egress interface */\n\tif (!CHIP_IS_E3(sc)) {\n\t\tREG_WR(sc, NIG_REG_BMAC0_OUT_EN + port * 4, 0);\n\t\tREG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port * 4, 0);\n\t}\n#ifdef ELINK_INCLUDE_EMUL\n\t/* Stop BigMac rx */\n\tif (!(params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC))\n#endif\n\t\tif (!CHIP_IS_E3(sc))\n\t\t\telink_set_bmac_rx(sc, port, 0);\n#ifdef ELINK_INCLUDE_EMUL\n\t/* Stop XMAC/UMAC rx */\n\tif (!(params->feature_config_flags &\n\t ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC))\n#endif\n\t\tif (CHIP_IS_E3(sc) && !CHIP_REV_IS_FPGA(sc)) {\n\t\t\telink_set_xmac_rxtx(params, 0);\n\t\t\telink_set_umac_rxtx(params, 0);\n\t\t}\n\t/* Disable emac */\n\tif (!CHIP_IS_E3(sc))\n\t\tREG_WR(sc, NIG_REG_NIG_EMAC0_EN + port * 4, 0);\n\n\tDELAY(1000 * 10);\n\t/* The PHY reset is controlled by GPIO 1\n\t * Hold it as vars low\n\t */\n\t/* Clear link led */\n\telink_set_mdio_emac_per_phy(sc, params);\n\telink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);\n\n\tif (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {\n\t\tfor (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;\n\t\t phy_index++) {\n\t\t\tif (params->phy[phy_index].link_reset) {\n\t\t\t\telink_set_aer_mmd(params,\n\t\t\t\t\t\t ¶ms->phy[phy_index]);\n\t\t\t\tparams->phy[phy_index].link_reset(¶ms->\n\t\t\t\t\t\t\t\t phy\n\t\t\t\t\t\t\t\t [phy_index],\n\t\t\t\t\t\t\t\t params);\n\t\t\t}\n\t\t\tif (params->phy[phy_index].flags &\n\t\t\t ELINK_FLAGS_REARM_LATCH_SIGNAL)\n\t\t\t\tclear_latch_ind = 1;\n\t\t}\n\t}\n\n\tif (clear_latch_ind) {\n\t\t/* Clear latching indication */\n\t\telink_rearm_latch_signal(sc, port, 0);\n\t\telink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port * 4,\n\t\t\t 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);\n\t}\n#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)\n\tif (!CHIP_REV_IS_SLOW(sc))\n#endif\n\t\tif (params->phy[ELINK_INT_PHY].link_reset)\n\t\t\tparams->phy[ELINK_INT_PHY].link_reset(¶ms->\n\t\t\t\t\t\t\t phy\n\t\t\t\t\t\t\t [ELINK_INT_PHY],\n\t\t\t\t\t\t\t params);\n\n\t/* Disable nig ingress interface */\n\tif (!CHIP_IS_E3(sc)) {\n\t\t/* Reset BigMac */\n\t\tREG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,\n\t\t (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));\n\t\tREG_WR(sc, NIG_REG_BMAC0_IN_EN + port * 4, 0);\n\t\tREG_WR(sc, NIG_REG_EMAC0_IN_EN + port * 4, 0);\n\t} else {\n\t\tuint32_t xmac_base =\n\t\t (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;\n\t\telink_set_xumac_nig(params, 0, 0);\n\t\tif (REG_RD(sc, MISC_REG_RESET_REG_2) &\n\t\t MISC_REGISTERS_RESET_REG_2_XMAC)\n\t\t\tREG_WR(sc, xmac_base + XMAC_REG_CTRL,\n\t\t\t XMAC_CTRL_REG_SOFT_RESET);\n\t}\n\tvars->link_up = 0;\n\tvars->phy_flags = 0;\n\treturn ELINK_STATUS_OK;\n}\n\nelink_status_t elink_lfa_reset(struct elink_params * params,\n\t\t\t struct elink_vars * vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tvars->link_up = 0;\n\tvars->phy_flags = 0;\n\tparams->link_flags &= ~ELINK_PHY_INITIALIZED;\n\tif (!params->lfa_base)\n\t\treturn elink_link_reset(params, vars, 1);\n\t/*\n\t * Activate NIG drain so that during this time the device won't send\n\t * anything while it is unable to response.\n\t */\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1);\n\n\t/*\n\t * Close gracefully the gate from BMAC to NIG such that no half packets\n\t * are passed.\n\t */\n\tif (!CHIP_IS_E3(sc))\n\t\telink_set_bmac_rx(sc, params->port, 0);\n\n\tif (CHIP_IS_E3(sc)) {\n\t\telink_set_xmac_rxtx(params, 0);\n\t\telink_set_umac_rxtx(params, 0);\n\t}\n\t/* Wait 10ms for the pipe to clean up */\n\tDELAY(1000 * 10);\n\n\t/* Clean the NIG-BRB using the network filters in a way that will\n\t * not cut a packet in the middle.\n\t */\n\telink_set_rx_filter(params, 0);\n\n\t/*\n\t * Re-open the gate between the BMAC and the NIG, after verifying the\n\t * gate to the BRB is closed, otherwise packets may arrive to the\n\t * firmware before driver had initialized it. The target is to achieve\n\t * minimum management protocol down time.\n\t */\n\tif (!CHIP_IS_E3(sc))\n\t\telink_set_bmac_rx(sc, params->port, 1);\n\n\tif (CHIP_IS_E3(sc)) {\n\t\telink_set_xmac_rxtx(params, 1);\n\t\telink_set_umac_rxtx(params, 1);\n\t}\n\t/* Disable NIG drain */\n\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n\treturn ELINK_STATUS_OK;\n}\n\n/****************************************************************************/\n/*\t\t\t\tCommon function\t\t\t\t */\n/****************************************************************************/\nstatic elink_status_t elink_8073_common_init_phy(struct bnx2x_softc *sc,\n\t\t\t\t\t\t uint32_t shmem_base_path[],\n\t\t\t\t\t\t uint32_t shmem2_base_path[],\n\t\t\t\t\t\t uint8_t phy_index,\n\t\t\t\t\t\t __rte_unused uint32_t chip_id)\n{\n\tstruct elink_phy phy[PORT_MAX];\n\tstruct elink_phy *phy_blk[PORT_MAX];\n\tuint16_t val;\n\tint8_t port = 0;\n\tint8_t port_of_path = 0;\n\tuint32_t swap_val, swap_override;\n\tswap_val = REG_RD(sc, NIG_REG_PORT_SWAP);\n\tswap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);\n\tport ^= (swap_val && swap_override);\n\telink_ext_phy_hw_reset(sc, port);\n\t/* PART1 - Reset both phys */\n\tfor (port = PORT_MAX - 1; port >= PORT_0; port--) {\n\t\tuint32_t shmem_base, shmem2_base;\n\t\t/* In E2, same phy is using for port0 of the two paths */\n\t\tif (CHIP_IS_E1x(sc)) {\n\t\t\tshmem_base = shmem_base_path[0];\n\t\t\tshmem2_base = shmem2_base_path[0];\n\t\t\tport_of_path = port;\n\t\t} else {\n\t\t\tshmem_base = shmem_base_path[port];\n\t\t\tshmem2_base = shmem2_base_path[port];\n\t\t\tport_of_path = 0;\n\t\t}\n\n\t\t/* Extract the ext phy address for the port */\n\t\tif (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,\n\t\t\t\t port_of_path, &phy[port]) !=\n\t\t ELINK_STATUS_OK) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"populate_phy failed\");\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t\t/* Disable attentions */\n\t\telink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +\n\t\t\t port_of_path * 4,\n\t\t\t (ELINK_NIG_MASK_XGXS0_LINK_STATUS |\n\t\t\t\tELINK_NIG_MASK_XGXS0_LINK10G |\n\t\t\t\tELINK_NIG_MASK_SERDES0_LINK_STATUS |\n\t\t\t\tELINK_NIG_MASK_MI_INT));\n\n\t\t/* Need to take the phy out of low power mode in order\n\t\t * to write to access its registers\n\t\t */\n\t\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n\t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);\n\n\t\t/* Reset the phy */\n\t\telink_cl45_write(sc, &phy[port],\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);\n\t}\n\n\t/* Add delay of 150ms after reset */\n\tDELAY(1000 * 150);\n\n\tif (phy[PORT_0].addr & 0x1) {\n\t\tphy_blk[PORT_0] = &(phy[PORT_1]);\n\t\tphy_blk[PORT_1] = &(phy[PORT_0]);\n\t} else {\n\t\tphy_blk[PORT_0] = &(phy[PORT_0]);\n\t\tphy_blk[PORT_1] = &(phy[PORT_1]);\n\t}\n\n\t/* PART2 - Download firmware to both phys */\n\tfor (port = PORT_MAX - 1; port >= PORT_0; port--) {\n\t\tif (CHIP_IS_E1x(sc))\n\t\t\tport_of_path = port;\n\t\telse\n\t\t\tport_of_path = 0;\n\n\t\tPMD_DRV_LOG(DEBUG, \"Loading spirom for phy address 0x%x\",\n\t\t\t phy_blk[port]->addr);\n\t\tif (elink_8073_8727_external_rom_boot(sc, phy_blk[port],\n\t\t\t\t\t\t port_of_path))\n\t\t\treturn ELINK_STATUS_ERROR;\n\n\t\t/* Only set bit 10 = 1 (Tx power down) */\n\t\telink_cl45_read(sc, phy_blk[port],\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_TX_POWER_DOWN, &val);\n\n\t\t/* Phase1 of TX_POWER_DOWN reset */\n\t\telink_cl45_write(sc, phy_blk[port],\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_TX_POWER_DOWN, (val | 1 << 10));\n\t}\n\n\t/* Toggle Transmitter: Power down and then up with 600ms delay\n\t * between\n\t */\n\tDELAY(1000 * 600);\n\n\t/* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */\n\tfor (port = PORT_MAX - 1; port >= PORT_0; port--) {\n\t\t/* Phase2 of POWER_DOWN_RESET */\n\t\t/* Release bit 10 (Release Tx power down) */\n\t\telink_cl45_read(sc, phy_blk[port],\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_TX_POWER_DOWN, &val);\n\n\t\telink_cl45_write(sc, phy_blk[port],\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_TX_POWER_DOWN,\n\t\t\t\t (val & (~(1 << 10))));\n\t\tDELAY(1000 * 15);\n\n\t\t/* Read modify write the SPI-ROM version select register */\n\t\telink_cl45_read(sc, phy_blk[port],\n\t\t\t\tMDIO_PMA_DEVAD,\n\t\t\t\tMDIO_PMA_REG_EDC_FFE_MAIN, &val);\n\t\telink_cl45_write(sc, phy_blk[port],\n\t\t\t\t MDIO_PMA_DEVAD,\n\t\t\t\t MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1 << 12)));\n\n\t\t/* set GPIO2 back to LOW */\n\t\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,\n\t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW, port);\n\t}\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_8726_common_init_phy(struct bnx2x_softc *sc,\n\t\t\t\t\t\t uint32_t shmem_base_path[],\n\t\t\t\t\t\t uint32_t shmem2_base_path[],\n\t\t\t\t\t\t uint8_t phy_index,\n\t\t\t\t\t\t __rte_unused uint32_t chip_id)\n{\n\tuint32_t val;\n\tint8_t port;\n\tstruct elink_phy phy;\n\t/* Use port1 because of the static port-swap */\n\t/* Enable the module detection interrupt */\n\tval = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);\n\tval |= ((1 << MISC_REGISTERS_GPIO_3) |\n\t\t(1 <<\n\t\t (MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));\n\tREG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);\n\n\telink_ext_phy_hw_reset(sc, 0);\n\tDELAY(1000 * 5);\n\tfor (port = 0; port < PORT_MAX; port++) {\n\t\tuint32_t shmem_base, shmem2_base;\n\n\t\t/* In E2, same phy is using for port0 of the two paths */\n\t\tif (CHIP_IS_E1x(sc)) {\n\t\t\tshmem_base = shmem_base_path[0];\n\t\t\tshmem2_base = shmem2_base_path[0];\n\t\t} else {\n\t\t\tshmem_base = shmem_base_path[port];\n\t\t\tshmem2_base = shmem2_base_path[port];\n\t\t}\n\t\t/* Extract the ext phy address for the port */\n\t\tif (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,\n\t\t\t\t port, &phy) != ELINK_STATUS_OK) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"populate phy failed\");\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\n\t\t/* Reset phy */\n\t\telink_cl45_write(sc, &phy,\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);\n\n\t\t/* Set fault module detected LED on */\n\t\telink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,\n\t\t\t\t MISC_REGISTERS_GPIO_HIGH, port);\n\t}\n\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_get_ext_phy_reset_gpio(struct bnx2x_softc *sc,\n\t\t\t\t\t uint32_t shmem_base, uint8_t * io_gpio,\n\t\t\t\t\t uint8_t * io_port)\n{\n\n\tuint32_t phy_gpio_reset = REG_RD(sc, shmem_base +\n\t\t\t\t\t offsetof(struct shmem_region,\n\t\t\t\t\t\t dev_info.\n\t\t\t\t\t\t port_hw_config[PORT_0].\n\t\t\t\t\t\t default_cfg));\n\tswitch (phy_gpio_reset) {\n\tcase PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:\n\t\t*io_gpio = 0;\n\t\t*io_port = 0;\n\t\tbreak;\n\tcase PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:\n\t\t*io_gpio = 1;\n\t\t*io_port = 0;\n\t\tbreak;\n\tcase PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:\n\t\t*io_gpio = 2;\n\t\t*io_port = 0;\n\t\tbreak;\n\tcase PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:\n\t\t*io_gpio = 3;\n\t\t*io_port = 0;\n\t\tbreak;\n\tcase PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:\n\t\t*io_gpio = 0;\n\t\t*io_port = 1;\n\t\tbreak;\n\tcase PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:\n\t\t*io_gpio = 1;\n\t\t*io_port = 1;\n\t\tbreak;\n\tcase PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:\n\t\t*io_gpio = 2;\n\t\t*io_port = 1;\n\t\tbreak;\n\tcase PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:\n\t\t*io_gpio = 3;\n\t\t*io_port = 1;\n\t\tbreak;\n\tdefault:\n\t\t/* Don't override the io_gpio and io_port */\n\t\tbreak;\n\t}\n}\n\nstatic elink_status_t elink_8727_common_init_phy(struct bnx2x_softc *sc,\n\t\t\t\t\t\t uint32_t shmem_base_path[],\n\t\t\t\t\t\t uint32_t shmem2_base_path[],\n\t\t\t\t\t\t uint8_t phy_index,\n\t\t\t\t\t\t __rte_unused uint32_t chip_id)\n{\n\tint8_t port, reset_gpio;\n\tuint32_t swap_val, swap_override;\n\tstruct elink_phy phy[PORT_MAX];\n\tstruct elink_phy *phy_blk[PORT_MAX];\n\tint8_t port_of_path;\n\tswap_val = REG_RD(sc, NIG_REG_PORT_SWAP);\n\tswap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);\n\n\treset_gpio = MISC_REGISTERS_GPIO_1;\n\tport = 1;\n\n\t/* Retrieve the reset gpio/port which control the reset.\n\t * Default is GPIO1, PORT1\n\t */\n\telink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],\n\t\t\t\t (uint8_t *) & reset_gpio,\n\t\t\t\t (uint8_t *) & port);\n\n\t/* Calculate the port based on port swap */\n\tport ^= (swap_val && swap_override);\n\n\t/* Initiate PHY reset */\n\telink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,\n\t\t\t port);\n\tDELAY(1000 * 1);\n\telink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,\n\t\t\t port);\n\n\tDELAY(1000 * 5);\n\n\t/* PART1 - Reset both phys */\n\tfor (port = PORT_MAX - 1; port >= PORT_0; port--) {\n\t\tuint32_t shmem_base, shmem2_base;\n\n\t\t/* In E2, same phy is using for port0 of the two paths */\n\t\tif (CHIP_IS_E1x(sc)) {\n\t\t\tshmem_base = shmem_base_path[0];\n\t\t\tshmem2_base = shmem2_base_path[0];\n\t\t\tport_of_path = port;\n\t\t} else {\n\t\t\tshmem_base = shmem_base_path[port];\n\t\t\tshmem2_base = shmem2_base_path[port];\n\t\t\tport_of_path = 0;\n\t\t}\n\n\t\t/* Extract the ext phy address for the port */\n\t\tif (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,\n\t\t\t\t port_of_path, &phy[port]) !=\n\t\t ELINK_STATUS_OK) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"populate phy failed\");\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t}\n\t\t/* disable attentions */\n\t\telink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +\n\t\t\t port_of_path * 4,\n\t\t\t (ELINK_NIG_MASK_XGXS0_LINK_STATUS |\n\t\t\t\tELINK_NIG_MASK_XGXS0_LINK10G |\n\t\t\t\tELINK_NIG_MASK_SERDES0_LINK_STATUS |\n\t\t\t\tELINK_NIG_MASK_MI_INT));\n\n\t\t/* Reset the phy */\n\t\telink_cl45_write(sc, &phy[port],\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1 << 15);\n\t}\n\n\t/* Add delay of 150ms after reset */\n\tDELAY(1000 * 150);\n\tif (phy[PORT_0].addr & 0x1) {\n\t\tphy_blk[PORT_0] = &(phy[PORT_1]);\n\t\tphy_blk[PORT_1] = &(phy[PORT_0]);\n\t} else {\n\t\tphy_blk[PORT_0] = &(phy[PORT_0]);\n\t\tphy_blk[PORT_1] = &(phy[PORT_1]);\n\t}\n\t/* PART2 - Download firmware to both phys */\n\tfor (port = PORT_MAX - 1; port >= PORT_0; port--) {\n\t\tif (CHIP_IS_E1x(sc))\n\t\t\tport_of_path = port;\n\t\telse\n\t\t\tport_of_path = 0;\n\t\tPMD_DRV_LOG(DEBUG, \"Loading spirom for phy address 0x%x\",\n\t\t\t phy_blk[port]->addr);\n\t\tif (elink_8073_8727_external_rom_boot(sc, phy_blk[port],\n\t\t\t\t\t\t port_of_path))\n\t\t\treturn ELINK_STATUS_ERROR;\n\t\t/* Disable PHY transmitter output */\n\t\telink_cl45_write(sc, phy_blk[port],\n\t\t\t\t MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_DISABLE, 1);\n\n\t}\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_84833_common_init_phy(struct bnx2x_softc *sc,\n\t\t\t\t\t\t uint32_t shmem_base_path[],\n\t\t\t\t\t\t __rte_unused uint32_t\n\t\t\t\t\t\t shmem2_base_path[],\n\t\t\t\t\t\t __rte_unused uint8_t\n\t\t\t\t\t\t phy_index, uint32_t chip_id)\n{\n\tuint8_t reset_gpios;\n\treset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);\n\telink_cb_gpio_mult_write(sc, reset_gpios,\n\t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_LOW);\n\tDELAY(10);\n\telink_cb_gpio_mult_write(sc, reset_gpios,\n\t\t\t\t MISC_REGISTERS_GPIO_OUTPUT_HIGH);\n\tPMD_DRV_LOG(DEBUG, \"84833 reset pulse on pin values 0x%x\", reset_gpios);\n\treturn ELINK_STATUS_OK;\n}\n\nstatic elink_status_t elink_ext_phy_common_init(struct bnx2x_softc *sc,\n\t\t\t\t\t\tuint32_t shmem_base_path[],\n\t\t\t\t\t\tuint32_t shmem2_base_path[],\n\t\t\t\t\t\tuint8_t phy_index,\n\t\t\t\t\t\tuint32_t ext_phy_type,\n\t\t\t\t\t\tuint32_t chip_id)\n{\n\telink_status_t rc = ELINK_STATUS_OK;\n\n\tswitch (ext_phy_type) {\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073:\n\t\trc = elink_8073_common_init_phy(sc, shmem_base_path,\n\t\t\t\t\t\tshmem2_base_path,\n\t\t\t\t\t\tphy_index, chip_id);\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722:\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727:\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC:\n\t\trc = elink_8727_common_init_phy(sc, shmem_base_path,\n\t\t\t\t\t\tshmem2_base_path,\n\t\t\t\t\t\tphy_index, chip_id);\n\t\tbreak;\n\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726:\n\t\t/* GPIO1 affects both ports, so there's need to pull\n\t\t * it for single port alone\n\t\t */\n\t\trc = elink_8726_common_init_phy(sc, shmem_base_path,\n\t\t\t\t\t\tshmem2_base_path,\n\t\t\t\t\t\tphy_index, chip_id);\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833:\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834:\n\t\t/* GPIO3's are linked, and so both need to be toggled\n\t\t * to obtain required 2us pulse.\n\t\t */\n\t\trc = elink_84833_common_init_phy(sc, shmem_base_path,\n\t\t\t\t\t\t shmem2_base_path,\n\t\t\t\t\t\t phy_index, chip_id);\n\t\tbreak;\n\tcase PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:\n\t\trc = ELINK_STATUS_ERROR;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(DEBUG,\n\t\t\t \"ext_phy 0x%x common init not required\",\n\t\t\t ext_phy_type);\n\t\tbreak;\n\t}\n\n\tif (rc != ELINK_STATUS_OK)\n\t\telink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0);\t// \"Warning: PHY was not initialized,\"\n\t// \" Port %d\",\n\n\treturn rc;\n}\n\nelink_status_t elink_common_init_phy(struct bnx2x_softc * sc,\n\t\t\t\t uint32_t shmem_base_path[],\n\t\t\t\t uint32_t shmem2_base_path[],\n\t\t\t\t uint32_t chip_id,\n\t\t\t\t __rte_unused uint8_t one_port_enabled)\n{\n\telink_status_t rc = ELINK_STATUS_OK;\n\tuint32_t phy_ver, val;\n\tuint8_t phy_index = 0;\n\tuint32_t ext_phy_type, ext_phy_config;\n#if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)\n\tif (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc))\n\t\treturn ELINK_STATUS_OK;\n#endif\n\n\telink_set_mdio_clk(sc, GRCBASE_EMAC0);\n\telink_set_mdio_clk(sc, GRCBASE_EMAC1);\n\tPMD_DRV_LOG(DEBUG, \"Begin common phy init\");\n\tif (CHIP_IS_E3(sc)) {\n\t\t/* Enable EPIO */\n\t\tval = REG_RD(sc, MISC_REG_GEN_PURP_HWG);\n\t\tREG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1);\n\t}\n\t/* Check if common init was already done */\n\tphy_ver = REG_RD(sc, shmem_base_path[0] +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t port_mb[PORT_0].ext_phy_fw_version));\n\tif (phy_ver) {\n\t\tPMD_DRV_LOG(DEBUG, \"Not doing common init; phy ver is 0x%x\",\n\t\t\t phy_ver);\n\t\treturn ELINK_STATUS_OK;\n\t}\n\n\t/* Read the ext_phy_type for arbitrary port(0) */\n\tfor (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;\n\t phy_index++) {\n\t\text_phy_config = elink_get_ext_phy_config(sc,\n\t\t\t\t\t\t\t shmem_base_path[0],\n\t\t\t\t\t\t\t phy_index, 0);\n\t\text_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);\n\t\trc |= elink_ext_phy_common_init(sc, shmem_base_path,\n\t\t\t\t\t\tshmem2_base_path,\n\t\t\t\t\t\tphy_index, ext_phy_type,\n\t\t\t\t\t\tchip_id);\n\t}\n\treturn rc;\n}\n\nstatic void elink_check_over_curr(struct elink_params *params,\n\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t cfg_pin;\n\tuint8_t port = params->port;\n\tuint32_t pin_val;\n\n\tcfg_pin = (REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_hw_config[port].\n\t\t\t\t e3_cmn_pin_cfg1)) &\n\t\t PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>\n\t PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;\n\n\t/* Ignore check if no external input PIN available */\n\tif (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)\n\t\treturn;\n\n\tif (!pin_val) {\n\t\tif ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {\n\t\t\telink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port);\t//\"Error: Power fault on Port %d has\"\n\t\t\t// \" been detected and the power to \"\n\t\t\t// \"that SFP+ module has been removed\"\n\t\t\t// \" to prevent failure of the card.\"\n\t\t\t// \" Please remove the SFP+ module and\"\n\t\t\t// \" restart the system to clear this\"\n\t\t\t// \" error.\",\n\t\t\tvars->phy_flags |= PHY_OVER_CURRENT_FLAG;\n\t\t\telink_warpcore_power_module(params, 0);\n\t\t}\n\t} else\n\t\tvars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;\n}\n\n/* Returns 0 if no change occured since last check; 1 otherwise. */\nstatic uint8_t elink_analyze_link_error(struct elink_params *params,\n\t\t\t\t\tstruct elink_vars *vars,\n\t\t\t\t\tuint32_t status, uint32_t phy_flag,\n\t\t\t\t\tuint32_t link_flag, uint8_t notify)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\t/* Compare new value with previous value */\n\tuint8_t led_mode;\n\tuint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0;\n\n\tif ((status ^ old_status) == 0)\n\t\treturn 0;\n\n\t/* If values differ */\n\tswitch (phy_flag) {\n\tcase PHY_HALF_OPEN_CONN_FLAG:\n\t\tPMD_DRV_LOG(DEBUG, \"Analyze Remote Fault\");\n\t\tbreak;\n\tcase PHY_SFP_TX_FAULT_FLAG:\n\t\tPMD_DRV_LOG(DEBUG, \"Analyze TX Fault\");\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(DEBUG, \"Analyze UNKNOWN\");\n\t}\n\tPMD_DRV_LOG(DEBUG, \"Link changed:[%x %x]->%x\", vars->link_up,\n\t\t old_status, status);\n\n\t/* a. Update shmem->link_status accordingly\n\t * b. Update elink_vars->link_up\n\t */\n\tif (status) {\n\t\tvars->link_status &= ~LINK_STATUS_LINK_UP;\n\t\tvars->link_status |= link_flag;\n\t\tvars->link_up = 0;\n\t\tvars->phy_flags |= phy_flag;\n\n\t\t/* activate nig drain */\n\t\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 1);\n\t\t/* Set LED mode to off since the PHY doesn't know about these\n\t\t * errors\n\t\t */\n\t\tled_mode = ELINK_LED_MODE_OFF;\n\t} else {\n\t\tvars->link_status |= LINK_STATUS_LINK_UP;\n\t\tvars->link_status &= ~link_flag;\n\t\tvars->link_up = 1;\n\t\tvars->phy_flags &= ~phy_flag;\n\t\tled_mode = ELINK_LED_MODE_OPER;\n\n\t\t/* Clear nig drain */\n\t\tREG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);\n\t}\n\telink_sync_link(params, vars);\n\t/* Update the LED according to the link state */\n\telink_set_led(params, vars, led_mode, ELINK_SPEED_10000);\n\n\t/* Update link status in the shared memory */\n\telink_update_mng(params, vars->link_status);\n\n\t/* C. Trigger General Attention */\n\tvars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT;\n\tif (notify)\n\t\telink_cb_notify_link_changed(sc);\n\n\treturn 1;\n}\n\n/******************************************************************************\n* Description:\n*\tThis function checks for half opened connection change indication.\n*\tWhen such change occurs, it calls the elink_analyze_link_error\n*\tto check if Remote Fault is set or cleared. Reception of remote fault\n*\tstatus message in the MAC indicates that the peer's MAC has detected\n*\ta fault, for example, due to break in the TX side of fiber.\n*\n******************************************************************************/\nstatic elink_status_t elink_check_half_open_conn(struct elink_params *params,\n\t\t\t\t\t\t struct elink_vars *vars,\n\t\t\t\t\t\t uint8_t notify)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t lss_status = 0;\n\tuint32_t mac_base;\n\t/* In case link status is physically up @ 10G do */\n\tif (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||\n\t (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port * 4)))\n\t\treturn ELINK_STATUS_OK;\n\n\tif (CHIP_IS_E3(sc) &&\n\t (REG_RD(sc, MISC_REG_RESET_REG_2) &\n\t (MISC_REGISTERS_RESET_REG_2_XMAC))) {\n\t\t/* Check E3 XMAC */\n\t\t/* Note that link speed cannot be queried here, since it may be\n\t\t * zero while link is down. In case UMAC is active, LSS will\n\t\t * simply not be set\n\t\t */\n\t\tmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;\n\n\t\t/* Clear stick bits (Requires rising edge) */\n\t\tREG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);\n\t\tREG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,\n\t\t XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |\n\t\t XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);\n\t\tif (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))\n\t\t\tlss_status = 1;\n\n\t\telink_analyze_link_error(params, vars, lss_status,\n\t\t\t\t\t PHY_HALF_OPEN_CONN_FLAG,\n\t\t\t\t\t LINK_STATUS_NONE, notify);\n\t} else if (REG_RD(sc, MISC_REG_RESET_REG_2) &\n\t\t (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {\n\t\t/* Check E1X / E2 BMAC */\n\t\tuint32_t lss_status_reg;\n\t\tuint32_t wb_data[2];\n\t\tmac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :\n\t\t NIG_REG_INGRESS_BMAC0_MEM;\n\t\t/* Read BIGMAC_REGISTER_RX_LSS_STATUS */\n\t\tif (CHIP_IS_E2(sc))\n\t\t\tlss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;\n\t\telse\n\t\t\tlss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;\n\n\t\tREG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);\n\t\tlss_status = (wb_data[0] > 0);\n\n\t\telink_analyze_link_error(params, vars, lss_status,\n\t\t\t\t\t PHY_HALF_OPEN_CONN_FLAG,\n\t\t\t\t\t LINK_STATUS_NONE, notify);\n\t}\n\treturn ELINK_STATUS_OK;\n}\n\nstatic void elink_sfp_tx_fault_detection(struct elink_phy *phy,\n\t\t\t\t\t struct elink_params *params,\n\t\t\t\t\t struct elink_vars *vars)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint32_t cfg_pin, value = 0;\n\tuint8_t led_change, port = params->port;\n\n\t/* Get The SFP+ TX_Fault controlling pin ([eg]pio) */\n\tcfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,\n\t\t\t\t\t\t\t dev_info.\n\t\t\t\t\t\t\t port_hw_config\n\t\t\t\t\t\t\t [port].\n\t\t\t\t\t\t\t e3_cmn_pin_cfg)) &\n\t\t PORT_HW_CFG_E3_TX_FAULT_MASK) >>\n\t PORT_HW_CFG_E3_TX_FAULT_SHIFT;\n\n\tif (elink_get_cfg_pin(sc, cfg_pin, &value)) {\n\t\tPMD_DRV_LOG(DEBUG, \"Failed to read pin 0x%02x\", cfg_pin);\n\t\treturn;\n\t}\n\n\tled_change = elink_analyze_link_error(params, vars, value,\n\t\t\t\t\t PHY_SFP_TX_FAULT_FLAG,\n\t\t\t\t\t LINK_STATUS_SFP_TX_FAULT, 1);\n\n\tif (led_change) {\n\t\t/* Change TX_Fault led, set link status for further syncs */\n\t\tuint8_t led_mode;\n\n\t\tif (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {\n\t\t\tled_mode = MISC_REGISTERS_GPIO_HIGH;\n\t\t\tvars->link_status |= LINK_STATUS_SFP_TX_FAULT;\n\t\t} else {\n\t\t\tled_mode = MISC_REGISTERS_GPIO_LOW;\n\t\t\tvars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;\n\t\t}\n\n\t\t/* If module is unapproved, led should be on regardless */\n\t\tif (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Change TX_Fault LED: ->%x\",\n\t\t\t\t led_mode);\n\t\t\telink_set_e3_module_fault_led(params, led_mode);\n\t\t}\n\t}\n}\n\nstatic void elink_kr2_recovery(struct elink_params *params,\n\t\t\t struct elink_vars *vars, struct elink_phy *phy)\n{\n\tPMD_DRV_LOG(DEBUG, \"KR2 recovery\");\n\n\telink_warpcore_enable_AN_KR2(phy, params, vars);\n\telink_warpcore_restart_AN_KR(phy, params);\n}\n\nstatic void elink_check_kr2_wa(struct elink_params *params,\n\t\t\t struct elink_vars *vars, struct elink_phy *phy)\n{\n\tstruct bnx2x_softc *sc = params->sc;\n\tuint16_t base_page, next_page, not_kr2_device, lane;\n\tint sigdet;\n\n\t/* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery\n\t * Since some switches tend to reinit the AN process and clear the\n\t * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled\n\t * and recovered many times\n\t */\n\tif (vars->check_kr2_recovery_cnt > 0) {\n\t\tvars->check_kr2_recovery_cnt--;\n\t\treturn;\n\t}\n\n\tsigdet = elink_warpcore_get_sigdet(phy, params);\n\tif (!sigdet) {\n\t\tif (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {\n\t\t\telink_kr2_recovery(params, vars, phy);\n\t\t\tPMD_DRV_LOG(DEBUG, \"No sigdet\");\n\t\t}\n\t\treturn;\n\t}\n\n\tlane = elink_get_warpcore_lane(params);\n\tCL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,\n\t\t\t MDIO_AER_BLOCK_AER_REG, lane);\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\tMDIO_AN_REG_LP_AUTO_NEG, &base_page);\n\telink_cl45_read(sc, phy, MDIO_AN_DEVAD,\n\t\t\tMDIO_AN_REG_LP_AUTO_NEG2, &next_page);\n\telink_set_aer_mmd(params, phy);\n\n\t/* CL73 has not begun yet */\n\tif (base_page == 0) {\n\t\tif (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {\n\t\t\telink_kr2_recovery(params, vars, phy);\n\t\t\tPMD_DRV_LOG(DEBUG, \"No BP\");\n\t\t}\n\t\treturn;\n\t}\n\n\t/* In case NP bit is not set in the BasePage, or it is set,\n\t * but only KX is advertised, declare this link partner as non-KR2\n\t * device.\n\t */\n\tnot_kr2_device = (((base_page & 0x8000) == 0) ||\n\t\t\t (((base_page & 0x8000) &&\n\t\t\t ((next_page & 0xe0) == 0x2))));\n\n\t/* In case KR2 is already disabled, check if we need to re-enable it */\n\tif (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {\n\t\tif (!not_kr2_device) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"BP=0x%x, NP=0x%x\", base_page,\n\t\t\t\t next_page);\n\t\t\telink_kr2_recovery(params, vars, phy);\n\t\t}\n\t\treturn;\n\t}\n\t/* KR2 is enabled, but not KR2 device */\n\tif (not_kr2_device) {\n\t\t/* Disable KR2 on both lanes */\n\t\tPMD_DRV_LOG(DEBUG, \"BP=0x%x, NP=0x%x\", base_page, next_page);\n\t\telink_disable_kr2(params, vars, phy);\n\t\t/* Restart AN on leading lane */\n\t\telink_warpcore_restart_AN_KR(phy, params);\n\t\treturn;\n\t}\n}\n\nvoid elink_period_func(struct elink_params *params, struct elink_vars *vars)\n{\n\tuint16_t phy_idx;\n\tstruct bnx2x_softc *sc = params->sc;\n\tfor (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {\n\t\tif (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {\n\t\t\telink_set_aer_mmd(params, ¶ms->phy[phy_idx]);\n\t\t\tif (elink_check_half_open_conn(params, vars, 1) !=\n\t\t\t ELINK_STATUS_OK) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"Fault detection failed\");\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (CHIP_IS_E3(sc)) {\n\t\tstruct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];\n\t\telink_set_aer_mmd(params, phy);\n\t\tif ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&\n\t\t (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))\n\t\t\telink_check_kr2_wa(params, vars, phy);\n\t\telink_check_over_curr(params, vars);\n\t\tif (vars->rx_tx_asic_rst)\n\t\t\telink_warpcore_config_runtime(phy, params, vars);\n\n\t\tif ((REG_RD(sc, params->shmem_base +\n\t\t\t offsetof(struct shmem_region,\n\t\t\t\t dev_info.port_hw_config[params->port].\n\t\t\t\t default_cfg))\n\t\t & PORT_HW_CFG_NET_SERDES_IF_MASK) ==\n\t\t PORT_HW_CFG_NET_SERDES_IF_SFI) {\n\t\t\tif (elink_is_sfp_module_plugged(params)) {\n\t\t\t\telink_sfp_tx_fault_detection(phy, params, vars);\n\t\t\t} else if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) {\n\t\t\t\t/* Clean trail, interrupt corrects the leds */\n\t\t\t\tvars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;\n\t\t\t\tvars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;\n\t\t\t\t/* Update link status in the shared memory */\n\t\t\t\telink_update_mng(params, vars->link_status);\n\t\t\t}\n\t\t}\n\t}\n}\n\nuint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc,\n\t\t\t\t uint32_t shmem_base,\n\t\t\t\t uint32_t shmem2_base, uint8_t port)\n{\n\tuint8_t phy_index, fan_failure_det_req = 0;\n\tstruct elink_phy phy;\n\tfor (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;\n\t phy_index++) {\n\t\tif (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,\n\t\t\t\t port, &phy)\n\t\t != ELINK_STATUS_OK) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"populate phy failed\");\n\t\t\treturn 0;\n\t\t}\n\t\tfan_failure_det_req |= (phy.flags &\n\t\t\t\t\tELINK_FLAGS_FAN_FAILURE_DET_REQ);\n\t}\n\treturn fan_failure_det_req;\n}\n\nvoid elink_hw_reset_phy(struct elink_params *params)\n{\n\tuint8_t phy_index;\n\tstruct bnx2x_softc *sc = params->sc;\n\telink_update_mng(params, 0);\n\telink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port * 4,\n\t\t (ELINK_NIG_MASK_XGXS0_LINK_STATUS |\n\t\t\tELINK_NIG_MASK_XGXS0_LINK10G |\n\t\t\tELINK_NIG_MASK_SERDES0_LINK_STATUS |\n\t\t\tELINK_NIG_MASK_MI_INT));\n\n\tfor (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; phy_index++) {\n\t\tif (params->phy[phy_index].hw_reset) {\n\t\t\tparams->phy[phy_index].hw_reset(¶ms->phy[phy_index],\n\t\t\t\t\t\t\tparams);\n\t\t\tparams->phy[phy_index] = phy_null;\n\t\t}\n\t}\n}\n\nvoid elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,\n\t\t\t __rte_unused uint32_t chip_id, uint32_t shmem_base,\n\t\t\t uint32_t shmem2_base, uint8_t port)\n{\n\tuint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;\n\tuint32_t val;\n\tuint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;\n\tif (CHIP_IS_E3(sc)) {\n\t\tif (elink_get_mod_abs_int_cfg(sc,\n\t\t\t\t\t shmem_base,\n\t\t\t\t\t port,\n\t\t\t\t\t &gpio_num,\n\t\t\t\t\t &gpio_port) != ELINK_STATUS_OK)\n\t\t\treturn;\n\t} else {\n\t\tstruct elink_phy phy;\n\t\tfor (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;\n\t\t phy_index++) {\n\t\t\tif (elink_populate_phy(sc, phy_index, shmem_base,\n\t\t\t\t\t shmem2_base, port, &phy)\n\t\t\t != ELINK_STATUS_OK) {\n\t\t\t\tPMD_DRV_LOG(DEBUG, \"populate phy failed\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t\tif (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726) {\n\t\t\t\tgpio_num = MISC_REGISTERS_GPIO_3;\n\t\t\t\tgpio_port = port;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (gpio_num == 0xff)\n\t\treturn;\n\n\t/* Set GPIO3 to trigger SFP+ module insertion/removal */\n\telink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z,\n\t\t\t gpio_port);\n\n\tswap_val = REG_RD(sc, NIG_REG_PORT_SWAP);\n\tswap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);\n\tgpio_port ^= (swap_val && swap_override);\n\n\tvars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<\n\t (gpio_num + (gpio_port << 2));\n\n\tsync_offset = shmem_base +\n\t offsetof(struct shmem_region,\n\t\t dev_info.port_hw_config[port].aeu_int_mask);\n\tREG_WR(sc, sync_offset, vars->aeu_int_mask);\n\n\tPMD_DRV_LOG(DEBUG, \"Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\",\n\t\t gpio_num, gpio_port, vars->aeu_int_mask);\n\n\tif (port == 0)\n\t\toffset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;\n\telse\n\t\toffset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;\n\n\t/* Open appropriate AEU for interrupts */\n\taeu_mask = REG_RD(sc, offset);\n\taeu_mask |= vars->aeu_int_mask;\n\tREG_WR(sc, offset, aeu_mask);\n\n\t/* Enable the GPIO to trigger interrupt */\n\tval = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);\n\tval |= 1 << (gpio_num + (gpio_port << 2));\n\tREG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);\n}\n" }, { "path": "drivers/net/bnx2x/elink.h", "content": "/*-\n * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved.\n *\n * Eric Davis \n * David Christensen \n * Gary Zambrano \n *\n * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. Neither the name of Broadcom Corporation nor the name of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written consent.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS'\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef ELINK_H\n#define ELINK_H\n\n#define ELINK_DEBUG\n\n\n\n\n\n\n/***********************************************************/\n/* CLC Call backs functions */\n/***********************************************************/\n/* CLC device structure */\nstruct bnx2x_softc;\n\nextern uint32_t elink_cb_reg_read(struct bnx2x_softc *sc, uint32_t reg_addr);\nextern void elink_cb_reg_write(struct bnx2x_softc *sc, uint32_t reg_addr, uint32_t val);\n\n/* mode - 0( LOW ) /1(HIGH)*/\nextern uint8_t elink_cb_gpio_write(struct bnx2x_softc *sc,\n\t\t\t uint16_t gpio_num,\n\t\t\t uint8_t mode, uint8_t port);\nextern uint8_t elink_cb_gpio_mult_write(struct bnx2x_softc *sc,\n\t\t\t uint8_t pins,\n\t\t\t uint8_t mode);\n\nextern uint32_t elink_cb_gpio_read(struct bnx2x_softc *sc, uint16_t gpio_num, uint8_t port);\nextern uint8_t elink_cb_gpio_int_write(struct bnx2x_softc *sc,\n\t\t\t\tuint16_t gpio_num,\n\t\t\t\tuint8_t mode, uint8_t port);\n\nextern uint32_t elink_cb_fw_command(struct bnx2x_softc *sc, uint32_t command, uint32_t param);\n\n/* This function is called every 1024 bytes downloading of phy firmware.\nDriver can use it to print to screen indication for download progress */\nextern void elink_cb_download_progress(struct bnx2x_softc *sc, uint32_t cur, uint32_t total);\n\n/* Each log type has its own parameters */\ntypedef enum elink_log_id {\n\tELINK_LOG_ID_UNQUAL_IO_MODULE\t= 0, /* uint8_t port, const char* vendor_name, const char* vendor_pn */\n\tELINK_LOG_ID_OVER_CURRENT\t= 1, /* uint8_t port */\n\tELINK_LOG_ID_PHY_UNINITIALIZED\t= 2, /* uint8_t port */\n\tELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */\n\tELINK_LOG_ID_NON_10G_MODULE\t= 4, /* uint8_t port */\n}elink_log_id_t;\n\ntypedef enum elink_status {\n\tELINK_STATUS_OK = 0,\n\tELINK_STATUS_ERROR,\n\tELINK_STATUS_TIMEOUT,\n\tELINK_STATUS_NO_LINK,\n\tELINK_STATUS_INVALID_IMAGE,\n\tELINK_OP_NOT_SUPPORTED = 122\n} elink_status_t;\nextern void elink_cb_event_log(struct bnx2x_softc *sc, const elink_log_id_t log_id, ...);\nextern void elink_cb_load_warpcore_microcode(void);\n\nextern void elink_cb_notify_link_changed(struct bnx2x_softc *sc);\n\n#define ELINK_EVENT_LOG_LEVEL_ERROR \t1\n#define ELINK_EVENT_LOG_LEVEL_WARNING \t2\n#define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE \t1\n#define ELINK_EVENT_ID_SFP_POWER_FAULT \t\t2\n\n#define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))\n/* Debug prints */\n\n/***********************************************************/\n/* Defines */\n/***********************************************************/\n#define ELINK_DEFAULT_PHY_DEV_ADDR\t3\n#define ELINK_E2_DEFAULT_PHY_DEV_ADDR\t5\n\n\n#define DUPLEX_FULL\t\t\t1\n#define DUPLEX_HALF\t\t\t2\n\n#define ELINK_FLOW_CTRL_AUTO\t\tPORT_FEATURE_FLOW_CONTROL_AUTO\n#define ELINK_FLOW_CTRL_TX\t\tPORT_FEATURE_FLOW_CONTROL_TX\n#define ELINK_FLOW_CTRL_RX\t\tPORT_FEATURE_FLOW_CONTROL_RX\n#define ELINK_FLOW_CTRL_BOTH\t\tPORT_FEATURE_FLOW_CONTROL_BOTH\n#define ELINK_FLOW_CTRL_NONE\t\tPORT_FEATURE_FLOW_CONTROL_NONE\n\n#define ELINK_NET_SERDES_IF_XFI\t\t1\n#define ELINK_NET_SERDES_IF_SFI\t\t2\n#define ELINK_NET_SERDES_IF_KR\t\t3\n#define ELINK_NET_SERDES_IF_DXGXS\t4\n\n#define ELINK_SPEED_AUTO_NEG\t\t0\n#define ELINK_SPEED_10\t\t\t10\n#define ELINK_SPEED_100\t\t\t100\n#define ELINK_SPEED_1000\t\t1000\n#define ELINK_SPEED_2500\t\t2500\n#define ELINK_SPEED_10000\t\t10000\n#define ELINK_SPEED_20000\t\t20000\n\n#define ELINK_I2C_DEV_ADDR_A0\t\t\t0xa0\n#define ELINK_I2C_DEV_ADDR_A2\t\t\t0xa2\n\n#define ELINK_SFP_EEPROM_PAGE_SIZE\t\t\t16\n#define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR\t\t0x14\n#define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE\t\t16\n#define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR\t\t0x25\n#define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE\t\t3\n#define ELINK_SFP_EEPROM_PART_NO_ADDR\t\t\t0x28\n#define ELINK_SFP_EEPROM_PART_NO_SIZE\t\t\t16\n#define ELINK_SFP_EEPROM_REVISION_ADDR\t\t0x38\n#define ELINK_SFP_EEPROM_REVISION_SIZE\t\t4\n#define ELINK_SFP_EEPROM_SERIAL_ADDR\t\t\t0x44\n#define ELINK_SFP_EEPROM_SERIAL_SIZE\t\t\t16\n#define ELINK_SFP_EEPROM_DATE_ADDR\t\t\t0x54 /* ASCII YYMMDD */\n#define ELINK_SFP_EEPROM_DATE_SIZE\t\t\t6\n#define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR\t\t\t0x5c\n#define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE\t\t\t1\n#define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ\t\t(1<<2)\n#define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR\t\t0x5e\n#define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE\t\t1\n\n#define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE\t\t0x5e\n#define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR\t\t\t0x5f\n\n#define ELINK_PWR_FLT_ERR_MSG_LEN\t\t\t250\n\n#define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \\\n\t\t((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)\n#define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \\\n\t\t(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \\\n\t\t PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)\n#define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \\\n\t\t((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)\n\n/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */\n#define ELINK_SINGLE_MEDIA_DIRECT(params)\t(params->num_phys == 1)\n/* Single Media board contains single external phy */\n#define ELINK_SINGLE_MEDIA(params)\t\t(params->num_phys == 2)\n/* Dual Media board contains two external phy with different media */\n#define ELINK_DUAL_MEDIA(params)\t\t(params->num_phys == 3)\n\n#define ELINK_FW_PARAM_PHY_ADDR_MASK\t\t0x000000FF\n#define ELINK_FW_PARAM_PHY_TYPE_MASK\t\t0x0000FF00\n#define ELINK_FW_PARAM_MDIO_CTRL_MASK\t\t0xFFFF0000\n#define ELINK_FW_PARAM_MDIO_CTRL_OFFSET\t\t16\n#define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \\\n\t\t\t\t\t ELINK_FW_PARAM_PHY_ADDR_MASK)\n#define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \\\n\t\t\t\t\t ELINK_FW_PARAM_PHY_TYPE_MASK)\n#define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \\\n\t\t\t\t\t ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \\\n\t\t\t\t\t ELINK_FW_PARAM_MDIO_CTRL_OFFSET)\n#define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \\\n\t(phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET)\n\n\n#define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD\t\t\t\t170\n#define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD\t\t\t\t250\n\n#define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b))\n\n#define ELINK_BMAC_CONTROL_RX_ENABLE\t\t2\n/***********************************************************/\n/* Structs */\n/***********************************************************/\n#define ELINK_INT_PHY\t\t0\n#define ELINK_EXT_PHY1\t1\n#define ELINK_EXT_PHY2\t2\n#define ELINK_MAX_PHYS\t3\n\n/* Same configuration is shared between the XGXS and the first external phy */\n#define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1)\n#define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \\\n\t\t\t\t\t 0 : (_phy_idx - 1))\n/***********************************************************/\n/* elink_phy struct */\n/* Defines the required arguments and function per phy */\n/***********************************************************/\nstruct elink_vars;\nstruct elink_params;\nstruct elink_phy;\n\ntypedef uint8_t (*config_init_t)(struct elink_phy *phy, struct elink_params *params,\n\t\t\t struct elink_vars *vars);\ntypedef uint8_t (*read_status_t)(struct elink_phy *phy, struct elink_params *params,\n\t\t\t struct elink_vars *vars);\ntypedef void (*link_reset_t)(struct elink_phy *phy,\n\t\t\t struct elink_params *params);\ntypedef void (*config_loopback_t)(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params);\ntypedef uint8_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len);\ntypedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params);\ntypedef void (*set_link_led_t)(struct elink_phy *phy,\n\t\t\t struct elink_params *params, uint8_t mode);\ntypedef void (*phy_specific_func_t)(struct elink_phy *phy,\n\t\t\t\t struct elink_params *params, uint32_t action);\nstruct elink_reg_set {\n\tuint8_t devad;\n\tuint16_t reg;\n\tuint16_t val;\n};\n\nstruct elink_phy {\n\tuint32_t type;\n\n\t/* Loaded during init */\n\tuint8_t addr;\n\tuint8_t def_md_devad;\n\tuint16_t flags;\n\t/* No Over-Current detection */\n#define ELINK_FLAGS_NOC\t\t\t(1<<1)\n\t/* Fan failure detection required */\n#define ELINK_FLAGS_FAN_FAILURE_DET_REQ\t(1<<2)\n\t/* Initialize first the XGXS and only then the phy itself */\n#define ELINK_FLAGS_INIT_XGXS_FIRST\t\t(1<<3)\n#define ELINK_FLAGS_WC_DUAL_MODE\t\t(1<<4)\n#define ELINK_FLAGS_4_PORT_MODE\t\t(1<<5)\n#define ELINK_FLAGS_REARM_LATCH_SIGNAL\t\t(1<<6)\n#define ELINK_FLAGS_SFP_NOT_APPROVED\t\t(1<<7)\n#define ELINK_FLAGS_MDC_MDIO_WA\t\t(1<<8)\n#define ELINK_FLAGS_DUMMY_READ\t\t\t(1<<9)\n#define ELINK_FLAGS_MDC_MDIO_WA_B0\t\t(1<<10)\n#define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC\t(1<<11)\n#define ELINK_FLAGS_TX_ERROR_CHECK\t\t(1<<12)\n#define ELINK_FLAGS_EEE\t\t\t(1<<13)\n#define ELINK_FLAGS_TEMPERATURE\t\t(1<<14)\n#define ELINK_FLAGS_MDC_MDIO_WA_G\t\t(1<<15)\n\n\t/* preemphasis values for the rx side */\n\tuint16_t rx_preemphasis[4];\n\n\t/* preemphasis values for the tx side */\n\tuint16_t tx_preemphasis[4];\n\n\t/* EMAC address for access MDIO */\n\tuint32_t mdio_ctrl;\n\n\tuint32_t supported;\n#define ELINK_SUPPORTED_10baseT_Half\t\t(1<<0)\n#define ELINK_SUPPORTED_10baseT_Full\t\t(1<<1)\n#define ELINK_SUPPORTED_100baseT_Half\t\t(1<<2)\n#define ELINK_SUPPORTED_100baseT_Full \t\t(1<<3)\n#define ELINK_SUPPORTED_1000baseT_Full \t(1<<4)\n#define ELINK_SUPPORTED_2500baseX_Full \t(1<<5)\n#define ELINK_SUPPORTED_10000baseT_Full \t(1<<6)\n#define ELINK_SUPPORTED_TP \t\t\t(1<<7)\n#define ELINK_SUPPORTED_FIBRE \t\t\t(1<<8)\n#define ELINK_SUPPORTED_Autoneg \t\t(1<<9)\n#define ELINK_SUPPORTED_Pause \t\t\t(1<<10)\n#define ELINK_SUPPORTED_Asym_Pause\t\t(1<<11)\n#define ELINK_SUPPORTED_20000baseMLD2_Full\t(1<<21)\n#define ELINK_SUPPORTED_20000baseKR2_Full\t(1<<22)\n\n\tuint32_t media_type;\n#define\tELINK_ETH_PHY_UNSPECIFIED\t0x0\n#define\tELINK_ETH_PHY_SFPP_10G_FIBER\t0x1\n#define\tELINK_ETH_PHY_XFP_FIBER\t\t0x2\n#define\tELINK_ETH_PHY_DA_TWINAX\t\t0x3\n#define\tELINK_ETH_PHY_BASE_T\t\t0x4\n#define ELINK_ETH_PHY_SFP_1G_FIBER\t0x5\n#define\tELINK_ETH_PHY_KR\t\t0xf0\n#define\tELINK_ETH_PHY_CX4\t\t0xf1\n#define\tELINK_ETH_PHY_NOT_PRESENT\t0xff\n\n\t/* The address in which version is located*/\n\tuint32_t ver_addr;\n\n\tuint16_t req_flow_ctrl;\n\n\tuint16_t req_line_speed;\n\n\tuint32_t speed_cap_mask;\n\n\tuint16_t req_duplex;\n\tuint16_t rsrv;\n\t/* Called per phy/port init, and it configures LASI, speed, autoneg,\n\t duplex, flow control negotiation, etc. */\n\tconfig_init_t config_init;\n\n\t/* Called due to interrupt. It determines the link, speed */\n\tread_status_t read_status;\n\n\t/* Called when driver is unloading. Should reset the phy */\n\tlink_reset_t link_reset;\n\n\t/* Set the loopback configuration for the phy */\n\tconfig_loopback_t config_loopback;\n\n\t/* Format the given raw number into str up to len */\n\tformat_fw_ver_t format_fw_ver;\n\n\t/* Reset the phy (both ports) */\n\thw_reset_t hw_reset;\n\n\t/* Set link led mode (on/off/oper)*/\n\tset_link_led_t set_link_led;\n\n\t/* PHY Specific tasks */\n\tphy_specific_func_t phy_specific_func;\n#define ELINK_DISABLE_TX\t1\n#define ELINK_ENABLE_TX\t2\n#define ELINK_PHY_INIT\t3\n};\n\n/* Inputs parameters to the CLC */\nstruct elink_params {\n\n\tuint8_t port;\n\n\t/* Default / User Configuration */\n\tuint8_t loopback_mode;\n#define ELINK_LOOPBACK_NONE\t\t0\n#define ELINK_LOOPBACK_EMAC\t\t1\n#define ELINK_LOOPBACK_BMAC\t\t2\n#define ELINK_LOOPBACK_XGXS\t\t3\n#define ELINK_LOOPBACK_EXT_PHY\t\t4\n#define ELINK_LOOPBACK_EXT\t\t5\n#define ELINK_LOOPBACK_UMAC\t\t6\n#define ELINK_LOOPBACK_XMAC\t\t7\n\n\t/* Device parameters */\n\tuint8_t mac_addr[6];\n\n\tuint16_t req_duplex[ELINK_LINK_CONFIG_SIZE];\n\tuint16_t req_flow_ctrl[ELINK_LINK_CONFIG_SIZE];\n\n\tuint16_t req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */\n\n\t/* shmem parameters */\n\tuint32_t shmem_base;\n\tuint32_t shmem2_base;\n\tuint32_t speed_cap_mask[ELINK_LINK_CONFIG_SIZE];\n\tuint32_t switch_cfg;\n#define ELINK_SWITCH_CFG_1G\t\tPORT_FEATURE_CON_SWITCH_1G_SWITCH\n#define ELINK_SWITCH_CFG_10G\t\tPORT_FEATURE_CON_SWITCH_10G_SWITCH\n#define ELINK_SWITCH_CFG_AUTO_DETECT\tPORT_FEATURE_CON_SWITCH_AUTO_DETECT\n\n\tuint32_t lane_config;\n\n\t/* Phy register parameter */\n\tuint32_t chip_id;\n\n\t/* features */\n\tuint32_t feature_config_flags;\n#define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED\t(1<<0)\n#define ELINK_FEATURE_CONFIG_PFC_ENABLED\t\t\t(1<<1)\n#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY\t\t(1<<2)\n#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY\t(1<<3)\n#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC\t\t\t(1<<4)\n#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC\t\t\t(1<<5)\n#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC\t\t\t(1<<6)\n#define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC\t\t\t(1<<7)\n#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX\t\t\t(1<<8)\n#define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED\t\t(1<<9)\n#define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED\t(1<<10)\n#define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET\t\t(1<<11)\n#define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST\t\t\t(1<<12)\n#define ELINK_FEATURE_CONFIG_MT_SUPPORT\t\t\t(1<<13)\n#define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN\t\t\t(1<<14)\n\n\t/* Will be populated during common init */\n\tstruct elink_phy phy[ELINK_MAX_PHYS];\n\n\t/* Will be populated during common init */\n\tuint8_t num_phys;\n\n\tuint8_t rsrv;\n\n\t/* Used to configure the EEE Tx LPI timer, has several modes of\n\t * operation, according to bits 29:28 -\n\t * 2'b00: Timer will be configured by nvram, output will be the value\n\t * from nvram.\n\t * 2'b01: Timer will be configured by nvram, output will be in\n\t * microseconds.\n\t * 2'b10: bits 1:0 contain an nvram value which will be used instead\n\t * of the one located in the nvram. Output will be that value.\n\t * 2'b11: bits 19:0 contain the idle timer in microseconds; output\n\t * will be in microseconds.\n\t * Bits 31:30 should be 2'b11 in order for EEE to be enabled.\n\t */\n\tuint32_t eee_mode;\n#define ELINK_EEE_MODE_NVRAM_BALANCED_TIME\t\t(0xa00)\n#define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME\t\t(0x100)\n#define ELINK_EEE_MODE_NVRAM_LATENCY_TIME\t\t(0x6000)\n#define ELINK_EEE_MODE_NVRAM_MASK\t\t(0x3)\n#define ELINK_EEE_MODE_TIMER_MASK\t\t(0xfffff)\n#define ELINK_EEE_MODE_OUTPUT_TIME\t\t(1<<28)\n#define ELINK_EEE_MODE_OVERRIDE_NVRAM\t\t(1<<29)\n#define ELINK_EEE_MODE_ENABLE_LPI\t\t(1<<30)\n#define ELINK_EEE_MODE_ADV_LPI\t\t\t(1<<31)\n\n\tuint16_t hw_led_mode; /* part of the hw_config read from the shmem */\n\tuint32_t multi_phy_config;\n\n\t/* Device pointer passed to all callback functions */\n\tstruct bnx2x_softc *sc;\n\tuint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when\n\t\t\t\treq_flow_ctrl is set to AUTO */\n\tuint16_t link_flags;\n#define ELINK_LINK_FLAGS_INT_DISABLED\t\t(1<<0)\n#define ELINK_PHY_INITIALIZED\t\t(1<<1)\n\tuint32_t lfa_base;\n};\n\n/* Output parameters */\nstruct elink_vars {\n\tuint8_t phy_flags;\n#define PHY_XGXS_FLAG\t\t\t(1<<0)\n#define PHY_SGMII_FLAG\t\t\t(1<<1)\n#define PHY_PHYSICAL_LINK_FLAG\t\t(1<<2)\n#define PHY_HALF_OPEN_CONN_FLAG\t\t(1<<3)\n#define PHY_OVER_CURRENT_FLAG\t\t(1<<4)\n#define PHY_SFP_TX_FAULT_FLAG\t\t(1<<5)\n\n\tuint8_t mac_type;\n#define ELINK_MAC_TYPE_NONE\t\t0\n#define ELINK_MAC_TYPE_EMAC\t\t1\n#define ELINK_MAC_TYPE_BMAC\t\t2\n#define ELINK_MAC_TYPE_UMAC\t\t3\n#define ELINK_MAC_TYPE_XMAC\t\t4\n\n\tuint8_t phy_link_up; /* internal phy link indication */\n\tuint8_t link_up;\n\n\tuint16_t line_speed;\n\tuint16_t duplex;\n\n\tuint16_t flow_ctrl;\n\tuint16_t ieee_fc;\n\n\t/* The same definitions as the shmem parameter */\n\tuint32_t link_status;\n\tuint32_t eee_status;\n\tuint8_t fault_detected;\n\tuint8_t check_kr2_recovery_cnt;\n#define ELINK_CHECK_KR2_RECOVERY_CNT\t5\n\tuint16_t periodic_flags;\n#define ELINK_PERIODIC_FLAGS_LINK_EVENT\t0x0001\n\n\tuint32_t aeu_int_mask;\n\tuint8_t rx_tx_asic_rst;\n\tuint8_t turn_to_run_wc_rt;\n\tuint16_t rsrv2;\n\t/* The same definitions as the shmem2 parameter */\n\tuint32_t link_attr_sync;\n};\n\n/***********************************************************/\n/* Functions */\n/***********************************************************/\nelink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars);\n\n/* Reset the link. Should be called when driver or interface goes down\n Before calling phy firmware upgrade, the reset_ext_phy should be set\n to 0 */\nelink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars);\n/* elink_link_update should be called upon link interrupt */\nelink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars);\n\n/* Reads the link_status from the shmem,\n and update the link vars accordingly */\nvoid elink_link_status_update(struct elink_params *input,\n\t\t\t struct elink_vars *output);\n\n/* Set/Unset the led\n Basically, the CLC takes care of the led for the link, but in case one needs\n to set/unset the led unnaturally, set the \"mode\" to ELINK_LED_MODE_OPER to\n blink the led, and ELINK_LED_MODE_OFF to set the led off.*/\nelink_status_t elink_set_led(struct elink_params *params,\n\t\t struct elink_vars *vars, uint8_t mode, uint32_t speed);\n#define ELINK_LED_MODE_OFF\t\t\t0\n#define ELINK_LED_MODE_ON\t\t\t1\n#define ELINK_LED_MODE_OPER\t\t\t2\n#define ELINK_LED_MODE_FRONT_PANEL_OFF\t3\n\n/* elink_handle_module_detect_int should be called upon module detection\n interrupt */\nvoid elink_handle_module_detect_int(struct elink_params *params);\n\n/* One-time initialization for external phy after power up */\nelink_status_t elink_common_init_phy(struct bnx2x_softc *sc, uint32_t shmem_base_path[],\n\t\t\t uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled);\n\nvoid elink_hw_reset_phy(struct elink_params *params);\n\n/* Check swap bit and adjust PHY order */\nuint32_t elink_phy_selection(struct elink_params *params);\n\n/* Probe the phys on board, and populate them in \"params\" */\nelink_status_t elink_phy_probe(struct elink_params *params);\n\n/* Checks if fan failure detection is required on one of the phys on board */\nuint8_t elink_fan_failure_det_req(struct bnx2x_softc *sc, uint32_t shmem_base,\n\t\t\t uint32_t shmem2_base, uint8_t port);\n\n/* Open / close the gate between the NIG and the BRB */\nvoid elink_set_rx_filter(struct elink_params *params, uint8_t en);\n\n/* DCBX structs */\n\n/* Number of maximum COS per chip */\n#define ELINK_DCBX_E2E3_MAX_NUM_COS\t\t(2)\n#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0\t(6)\n#define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1\t(3)\n#define ELINK_DCBX_E3B0_MAX_NUM_COS\t\t( \\\n\t\t\tELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \\\n\t\t\t ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1))\n\n#define ELINK_DCBX_MAX_NUM_COS\t\t\t( \\\n\t\t\tELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \\\n\t\t\t ELINK_DCBX_E2E3_MAX_NUM_COS))\n\n/* PFC port configuration params */\nstruct elink_nig_brb_pfc_port_params {\n\t/* NIG */\n\tuint32_t pause_enable;\n\tuint32_t llfc_out_en;\n\tuint32_t llfc_enable;\n\tuint32_t pkt_priority_to_cos;\n\tuint8_t num_of_rx_cos_priority_mask;\n\tuint32_t rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS];\n\tuint32_t llfc_high_priority_classes;\n\tuint32_t llfc_low_priority_classes;\n};\n\n\n/* ETS port configuration params */\nstruct elink_ets_bw_params {\n\tuint8_t bw;\n};\n\nstruct elink_ets_sp_params {\n\t/**\n\t * valid values are 0 - 5. 0 is highest strict priority.\n\t * There can't be two COS's with the same pri.\n\t */\n\tuint8_t pri;\n};\n\nenum elink_cos_state {\n\telink_cos_state_strict = 0,\n\telink_cos_state_bw = 1,\n};\n\nstruct elink_ets_cos_params {\n\tenum elink_cos_state state ;\n\tunion {\n\t\tstruct elink_ets_bw_params bw_params;\n\t\tstruct elink_ets_sp_params sp_params;\n\t} params;\n};\n\nstruct elink_ets_params {\n\tuint8_t num_of_cos; /* Number of valid COS entries*/\n\tstruct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS];\n};\n\n/* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB\n * when link is already up\n */\nelink_status_t elink_update_pfc(struct elink_params *params,\n\t\t struct elink_vars *vars,\n\t\t struct elink_nig_brb_pfc_port_params *pfc_params);\n\nvoid elink_init_mod_abs_int(struct bnx2x_softc *sc, struct elink_vars *vars,\n\t\t\t uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,\n\t\t\t uint8_t port);\n\nvoid elink_period_func(struct elink_params *params, struct elink_vars *vars);\n\nvoid elink_enable_pmd_tx(struct elink_params *params);\n\n\n\n#endif /* ELINK_H */\n" }, { "path": "drivers/net/bonding/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_bond.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_eth_bond_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += rte_eth_bond_api.c\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += rte_eth_bond_pmd.c\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += rte_eth_bond_args.c\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += rte_eth_bond_8023ad.c\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += rte_eth_bond_alb.c\n\n#\n# Export include files\n#\nSYMLINK-y-include += rte_eth_bond.h\nSYMLINK-y-include += rte_eth_bond_8023ad.h\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += lib/librte_eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += lib/librte_kvargs\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/bonding/rte_eth_bond.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ETH_BOND_H_\n#define _RTE_ETH_BOND_H_\n\n/**\n * @file rte_eth_bond.h\n *\n * RTE Link Bonding Ethernet Device\n * Link Bonding for 1GbE and 10GbE ports to allow the aggregation of multiple\n * (slave) NICs into a single logical interface. The bonded device processes\n * these interfaces based on the mode of operation specified and supported.\n * This implementation supports 4 modes of operation round robin, active backup\n * balance and broadcast. Providing redundant links, fault tolerance and/or\n * load balancing of network ports\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n/* Supported modes of operation of link bonding library */\n\n#define BONDING_MODE_ROUND_ROBIN\t\t(0)\n/**< Round Robin (Mode 0).\n * In this mode all transmitted packets will be balanced equally across all\n * active slaves of the bonded in a round robin fashion. */\n#define BONDING_MODE_ACTIVE_BACKUP\t\t(1)\n/**< Active Backup (Mode 1).\n * In this mode all packets transmitted will be transmitted on the primary\n * slave until such point as the primary slave is no longer available and then\n * transmitted packets will be sent on the next available slaves. The primary\n * slave can be defined by the user but defaults to the first active slave\n * available if not specified. */\n#define BONDING_MODE_BALANCE\t\t\t(2)\n/**< Balance (Mode 2).\n * In this mode all packets transmitted will be balanced across the available\n * slaves using one of three available transmit policies - l2, l2+3 or l3+4.\n * See BALANCE_XMIT_POLICY macros definitions for further details on transmit\n * policies. */\n#define BONDING_MODE_BROADCAST\t\t\t(3)\n/**< Broadcast (Mode 3).\n * In this mode all transmitted packets will be transmitted on all available\n * active slaves of the bonded. */\n#define BONDING_MODE_8023AD\t\t\t\t(4)\n/**< 802.3AD (Mode 4).\n *\n * This mode provides auto negotiation/configuration\n * of peers and well as link status changes monitoring using out of band\n * LACP (link aggregation control protocol) messages. For further details of\n * LACP specification see the IEEE 802.3ad/802.1AX standards. It is also\n * described here\n * https://www.kernel.org/doc/Documentation/networking/bonding.txt.\n *\n * Important Usage Notes:\n * - for LACP mode to work the rx/tx burst functions must be invoked\n * at least once every 100ms, otherwise the out-of-band LACP messages will not\n * be handled with the expected latency and this may cause the link status to be\n * incorrectly marked as down or failure to correctly negotiate with peers.\n * - For optimal performance during initial handshaking the array of mbufs provided\n * to rx_burst should be at least 2 times the slave count size.\n *\n */\n#define BONDING_MODE_TLB\t(5)\n/**< Adaptive TLB (Mode 5)\n * This mode provides an adaptive transmit load balancing. It dynamically\n * changes the transmitting slave, according to the computed load. Statistics\n * are collected in 100ms intervals and scheduled every 10ms */\n#define BONDING_MODE_ALB\t(6)\n/**< Adaptive Load Balancing (Mode 6)\n * This mode includes adaptive TLB and receive load balancing (RLB). In RLB the\n * bonding driver intercepts ARP replies send by local system and overwrites its\n * source MAC address, so that different peers send data to the server on\n * different slave interfaces. When local system sends ARP request, it saves IP\n * information from it. When ARP reply from that peer is received, its MAC is\n * stored, one of slave MACs assigned and ARP reply send to that peer.\n */\n\n/* Balance Mode Transmit Policies */\n#define BALANCE_XMIT_POLICY_LAYER2\t\t(0)\n/**< Layer 2 (Ethernet MAC) */\n#define BALANCE_XMIT_POLICY_LAYER23\t\t(1)\n/**< Layer 2+3 (Ethernet MAC + IP Addresses) transmit load balancing */\n#define BALANCE_XMIT_POLICY_LAYER34\t\t(2)\n/**< Layer 3+4 (IP Addresses + UDP Ports) transmit load balancing */\n\n/**\n * Create a bonded rte_eth_dev device\n *\n * @param name\t\t\tName of new link bonding device.\n * @param mode\t\t\tMode to initialize bonding device in.\n * @param socket_id\t\tSocket Id on which to allocate eth_dev resources.\n *\n * @return\n *\tPort Id of created rte_eth_dev on success, negative value otherwise\n */\nint\nrte_eth_bond_create(const char *name, uint8_t mode, uint8_t socket_id);\n\n/**\n * Free a bonded rte_eth_dev device\n *\n * @param name\t\t\tName of the link bonding device.\n *\n * @return\n *\t0 on success, negative value otherwise\n */\nint\nrte_eth_bond_free(const char *name);\n\n/**\n * Add a rte_eth_dev device as a slave to the bonded device\n *\n * @param bonded_port_id\tPort ID of bonded device.\n * @param slave_port_id\t\tPort ID of slave device.\n *\n * @return\n *\t0 on success, negative value otherwise\n */\nint\nrte_eth_bond_slave_add(uint8_t bonded_port_id, uint8_t slave_port_id);\n\n/**\n * Remove a slave rte_eth_dev device from the bonded device\n *\n * @param bonded_port_id\tPort ID of bonded device.\n * @param slave_port_id\t\tPort ID of slave device.\n *\n * @return\n *\t0 on success, negative value otherwise\n */\nint\nrte_eth_bond_slave_remove(uint8_t bonded_port_id, uint8_t slave_port_id);\n\n/**\n * Set link bonding mode of bonded device\n *\n * @param bonded_port_id\tPort ID of bonded device.\n * @param mode\t\t\t\tBonding mode to set\n *\n * @return\n *\t0 on success, negative value otherwise\n */\nint\nrte_eth_bond_mode_set(uint8_t bonded_port_id, uint8_t mode);\n\n/**\n * Get link bonding mode of bonded device\n *\n * @param bonded_port_id\tPort ID of bonded device.\n *\n * @return\n *\tlink bonding mode on success, negative value otherwise\n */\nint\nrte_eth_bond_mode_get(uint8_t bonded_port_id);\n\n/**\n * Set slave rte_eth_dev as primary slave of bonded device\n *\n * @param bonded_port_id\tPort ID of bonded device.\n * @param slave_port_id\t\tPort ID of slave device.\n *\n * @return\n *\t0 on success, negative value otherwise\n */\nint\nrte_eth_bond_primary_set(uint8_t bonded_port_id, uint8_t slave_port_id);\n\n/**\n * Get primary slave of bonded device\n *\n * @param bonded_port_id\tPort ID of bonded device.\n *\n * @return\n *\tPort Id of primary slave on success, -1 on failure\n */\nint\nrte_eth_bond_primary_get(uint8_t bonded_port_id);\n\n/**\n * Populate an array with list of the slaves port id's of the bonded device\n *\n * @param bonded_port_id\tPort ID of bonded eth_dev to interrogate\n * @param slaves\t\t\tArray to be populated with the current active slaves\n * @param len\t\t\t\tLength of slaves array\n *\n * @return\n *\tNumber of slaves associated with bonded device on success,\n *\tnegative value otherwise\n */\nint\nrte_eth_bond_slaves_get(uint8_t bonded_port_id, uint8_t slaves[], uint8_t len);\n\n/**\n * Populate an array with list of the active slaves port id's of the bonded\n * device.\n *\n * @param bonded_port_id\tPort ID of bonded eth_dev to interrogate\n * @param slaves\t\t\tArray to be populated with the current active slaves\n * @param len\t\t\t\tLength of slaves array\n *\n * @return\n *\tNumber of active slaves associated with bonded device on success,\n *\tnegative value otherwise\n */\nint\nrte_eth_bond_active_slaves_get(uint8_t bonded_port_id, uint8_t slaves[],\n\t\tuint8_t len);\n\n/**\n * Set explicit MAC address to use on bonded device and it's slaves.\n *\n * @param bonded_port_id\tPort ID of bonded device.\n * @param mac_addr\t\t\tMAC Address to use on bonded device overriding\n *\t\t\t\t\t\t\tslaves MAC addresses\n *\n * @return\n *\t0 on success, negative value otherwise\n */\nint\nrte_eth_bond_mac_address_set(uint8_t bonded_port_id,\n\t\tstruct ether_addr *mac_addr);\n\n/**\n * Reset bonded device to use MAC from primary slave on bonded device and it's\n * slaves.\n *\n * @param bonded_port_id\tPort ID of bonded device.\n *\n * @return\n *\t0 on success, negative value otherwise\n */\nint\nrte_eth_bond_mac_address_reset(uint8_t bonded_port_id);\n\n/**\n * Set the transmit policy for bonded device to use when it is operating in\n * balance mode, this parameter is otherwise ignored in other modes of\n * operation.\n *\n * @param bonded_port_id\tPort ID of bonded device.\n * @param policy\t\t\tBalance mode transmission policy.\n *\n * @return\n *\t0 on success, negative value otherwise.\n */\nint\nrte_eth_bond_xmit_policy_set(uint8_t bonded_port_id, uint8_t policy);\n\n/**\n * Get the transmit policy set on bonded device for balance mode operation\n *\n * @param bonded_port_id\tPort ID of bonded device.\n *\n * @return\n *\tBalance transmit policy on success, negative value otherwise.\n */\nint\nrte_eth_bond_xmit_policy_get(uint8_t bonded_port_id);\n\n/**\n * Set the link monitoring frequency (in ms) for monitoring the link status of\n * slave devices\n *\n * @param bonded_port_id\tPort ID of bonded device.\n * @param internal_ms\t\tMonitoring interval in milliseconds\n *\n * @return\n *\t0 on success, negative value otherwise.\n */\n\nint\nrte_eth_bond_link_monitoring_set(uint8_t bonded_port_id, uint32_t internal_ms);\n\n/**\n * Get the current link monitoring frequency (in ms) for monitoring of the link\n * status of slave devices\n *\n * @param bonded_port_id\tPort ID of bonded device.\n *\n * @return\n *\tMonitoring interval on success, negative value otherwise.\n */\nint\nrte_eth_bond_link_monitoring_get(uint8_t bonded_port_id);\n\n\n/**\n * Set the period in milliseconds for delaying the disabling of a bonded link\n * when the link down status has been detected\n *\n * @param bonded_port_id\tPort ID of bonded device.\n * @param delay_ms\t\t\tDelay period in milliseconds.\n *\n * @return\n * 0 on success, negative value otherwise.\n */\nint\nrte_eth_bond_link_down_prop_delay_set(uint8_t bonded_port_id, uint32_t delay_ms);\n\n/**\n * Get the period in milliseconds set for delaying the disabling of a bonded\n * link when the link down status has been detected\n *\n * @param bonded_port_id\tPort ID of bonded device.\n *\n * @return\n * Delay period on success, negative value otherwise.\n */\nint\nrte_eth_bond_link_down_prop_delay_get(uint8_t bonded_port_id);\n\n/**\n * Set the period in milliseconds for delaying the enabling of a bonded link\n * when the link up status has been detected\n *\n * @param bonded_port_id\tPort ID of bonded device.\n * @param delay_ms\t\t\tDelay period in milliseconds.\n *\n * @return\n * 0 on success, negative value otherwise.\n */\nint\nrte_eth_bond_link_up_prop_delay_set(uint8_t bonded_port_id, uint32_t delay_ms);\n\n/**\n * Get the period in milliseconds set for delaying the enabling of a bonded\n * link when the link up status has been detected\n *\n * @param bonded_port_id\tPort ID of bonded device.\n *\n * @return\n * Delay period on success, negative value otherwise.\n */\nint\nrte_eth_bond_link_up_prop_delay_get(uint8_t bonded_port_id);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "drivers/net/bonding/rte_eth_bond_8023ad.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"rte_eth_bond_private.h\"\n\n#ifdef RTE_LIBRTE_BOND_DEBUG_8023AD\n#define MODE4_DEBUG(fmt, ...) RTE_LOG(DEBUG, PMD, \"%6u [Port %u: %s] \" fmt, \\\n\t\t\tbond_dbg_get_time_diff_ms(), slave_id, \\\n\t\t\t__func__, ##__VA_ARGS__)\n\nstatic uint64_t start_time;\n\nstatic unsigned\nbond_dbg_get_time_diff_ms(void)\n{\n\tuint64_t now;\n\n\tnow = rte_rdtsc();\n\tif (start_time == 0)\n\t\tstart_time = now;\n\n\treturn ((now - start_time) * 1000) / rte_get_tsc_hz();\n}\n\nstatic void\nbond_print_lacp(struct lacpdu *l)\n{\n\tchar a_address[18];\n\tchar p_address[18];\n\tchar a_state[256] = { 0 };\n\tchar p_state[256] = { 0 };\n\n\tstatic const char * const state_labels[] = {\n\t\t\"ACT\", \"TIMEOUT\", \"AGG\", \"SYNC\", \"COL\", \"DIST\", \"DEF\", \"EXP\"\n\t};\n\n\tint a_len = 0;\n\tint p_len = 0;\n\tuint8_t i;\n\tuint8_t *addr;\n\n\taddr = l->actor.port_params.system.addr_bytes;\n\tsnprintf(a_address, sizeof(a_address), \"%02X:%02X:%02X:%02X:%02X:%02X\",\n\t\taddr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);\n\n\taddr = l->partner.port_params.system.addr_bytes;\n\tsnprintf(p_address, sizeof(p_address), \"%02X:%02X:%02X:%02X:%02X:%02X\",\n\t\taddr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);\n\n\tfor (i = 0; i < 8; i++) {\n\t\tif ((l->actor.state >> i) & 1) {\n\t\t\ta_len += snprintf(&a_state[a_len], RTE_DIM(a_state) - a_len, \"%s \",\n\t\t\t\tstate_labels[i]);\n\t\t}\n\n\t\tif ((l->partner.state >> i) & 1) {\n\t\t\tp_len += snprintf(&p_state[p_len], RTE_DIM(p_state) - p_len, \"%s \",\n\t\t\t\tstate_labels[i]);\n\t\t}\n\t}\n\n\tif (a_len && a_state[a_len-1] == ' ')\n\t\ta_state[a_len-1] = '\\0';\n\n\tif (p_len && p_state[p_len-1] == ' ')\n\t\tp_state[p_len-1] = '\\0';\n\n\tRTE_LOG(DEBUG, PMD, \"LACP: {\\n\"\\\n\t\t\t\" subtype= %02X\\n\"\\\n\t\t\t\" ver_num=%02X\\n\"\\\n\t\t\t\" actor={ tlv=%02X, len=%02X\\n\"\\\n\t\t\t\" pri=%04X, system=%s, key=%04X, p_pri=%04X p_num=%04X\\n\"\\\n\t\t\t\" state={ %s }\\n\"\\\n\t\t\t\" }\\n\"\\\n\t\t\t\" partner={ tlv=%02X, len=%02X\\n\"\\\n\t\t\t\" pri=%04X, system=%s, key=%04X, p_pri=%04X p_num=%04X\\n\"\\\n\t\t\t\" state={ %s }\\n\"\\\n\t\t\t\" }\\n\"\\\n\t\t\t\" collector={info=%02X, length=%02X, max_delay=%04X\\n, \" \\\n\t\t\t\t\t\t\t\"type_term=%02X, terminator_length = %02X}\\n\",\\\n\t\t\tl->subtype,\\\n\t\t\tl->version_number,\\\n\t\t\tl->actor.tlv_type_info,\\\n\t\t\tl->actor.info_length,\\\n\t\t\tl->actor.port_params.system_priority,\\\n\t\t\ta_address,\\\n\t\t\tl->actor.port_params.key,\\\n\t\t\tl->actor.port_params.port_priority,\\\n\t\t\tl->actor.port_params.port_number,\\\n\t\t\ta_state,\\\n\t\t\tl->partner.tlv_type_info,\\\n\t\t\tl->partner.info_length,\\\n\t\t\tl->partner.port_params.system_priority,\\\n\t\t\tp_address,\\\n\t\t\tl->partner.port_params.key,\\\n\t\t\tl->partner.port_params.port_priority,\\\n\t\t\tl->partner.port_params.port_number,\\\n\t\t\tp_state,\\\n\t\t\tl->tlv_type_collector_info,\\\n\t\t\tl->collector_info_length,\\\n\t\t\tl->collector_max_delay,\\\n\t\t\tl->tlv_type_terminator,\\\n\t\t\tl->terminator_length);\n\n}\n#define BOND_PRINT_LACP(lacpdu) bond_print_lacp(lacpdu)\n#else\n#define BOND_PRINT_LACP(lacpdu) do { } while (0)\n#define MODE4_DEBUG(fmt, ...) do { } while (0)\n#endif\n\nstatic const struct ether_addr lacp_mac_addr = {\n\t.addr_bytes = { 0x01, 0x80, 0xC2, 0x00, 0x00, 0x02 }\n};\n\nstruct port mode_8023ad_ports[RTE_MAX_ETHPORTS];\n\nstatic void\ntimer_cancel(uint64_t *timer)\n{\n\t*timer = 0;\n}\n\nstatic void\ntimer_set(uint64_t *timer, uint64_t timeout)\n{\n\t*timer = rte_rdtsc() + timeout;\n}\n\n/* Forces given timer to be in expired state. */\nstatic void\ntimer_force_expired(uint64_t *timer)\n{\n\t*timer = rte_rdtsc();\n}\n\nstatic bool\ntimer_is_stopped(uint64_t *timer)\n{\n\treturn *timer == 0;\n}\n\nstatic bool\ntimer_is_expired(uint64_t *timer)\n{\n\treturn *timer < rte_rdtsc();\n}\n\n/* Timer is in running state if it is not stopped nor expired */\nstatic bool\ntimer_is_running(uint64_t *timer)\n{\n\treturn !timer_is_stopped(timer) && !timer_is_expired(timer);\n}\n\nstatic void\nset_warning_flags(struct port *port, uint16_t flags)\n{\n\tint retval;\n\tuint16_t old;\n\tuint16_t new_flag = 0;\n\n\tdo {\n\t\told = port->warnings_to_show;\n\t\tnew_flag = old | flags;\n\t\tretval = rte_atomic16_cmpset(&port->warnings_to_show, old, new_flag);\n\t} while (unlikely(retval == 0));\n}\n\nstatic void\nshow_warnings(uint8_t slave_id)\n{\n\tstruct port *port = &mode_8023ad_ports[slave_id];\n\tuint8_t warnings;\n\n\tdo {\n\t\twarnings = port->warnings_to_show;\n\t} while (rte_atomic16_cmpset(&port->warnings_to_show, warnings, 0) == 0);\n\n\tif (!warnings)\n\t\treturn;\n\n\tif (!timer_is_expired(&port->warning_timer))\n\t\treturn;\n\n\n\ttimer_set(&port->warning_timer, BOND_8023AD_WARNINGS_PERIOD_MS *\n\t\t\trte_get_tsc_hz() / 1000);\n\n\tif (warnings & WRN_RX_QUEUE_FULL) {\n\t\tRTE_LOG(DEBUG, PMD,\n\t\t\t\"Slave %u: failed to enqueue LACP packet into RX ring.\\n\"\n\t\t\t\"Receive and transmit functions must be invoked on bonded\\n\"\n\t\t\t\"interface at least 10 times per second or LACP will not\\n\"\n\t\t\t\"work correctly\\n\", slave_id);\n\t}\n\n\tif (warnings & WRN_TX_QUEUE_FULL) {\n\t\tRTE_LOG(DEBUG, PMD,\n\t\t\t\"Slave %u: failed to enqueue LACP packet into TX ring.\\n\"\n\t\t\t\"Receive and transmit functions must be invoked on bonded\\n\"\n\t\t\t\"interface at least 10 times per second or LACP will not\\n\"\n\t\t\t\"work correctly\\n\", slave_id);\n\t}\n\n\tif (warnings & WRN_RX_MARKER_TO_FAST)\n\t\tRTE_LOG(INFO, PMD, \"Slave %u: marker to early - ignoring.\\n\", slave_id);\n\n\tif (warnings & WRN_UNKNOWN_SLOW_TYPE) {\n\t\tRTE_LOG(INFO, PMD,\n\t\t\t\"Slave %u: ignoring unknown slow protocol frame type\", slave_id);\n\t}\n\n\tif (warnings & WRN_UNKNOWN_MARKER_TYPE)\n\t\tRTE_LOG(INFO, PMD, \"Slave %u: ignoring unknown marker type\", slave_id);\n\n\tif (warnings & WRN_NOT_LACP_CAPABLE)\n\t\tMODE4_DEBUG(\"Port %u is not LACP capable!\\n\", slave_id);\n}\n\nstatic void\nrecord_default(struct port *port)\n{\n\t/* Record default parameters for partner. Partner admin parameters\n\t * are not implemented so set them to arbitrary default (last known) and\n\t * mark actor that parner is in defaulted state. */\n\tport->partner_state = STATE_LACP_ACTIVE;\n\tACTOR_STATE_SET(port, DEFAULTED);\n}\n\n/** Function handles rx state machine.\n *\n * This function implements Receive State Machine from point 5.4.12 in\n * 802.1AX documentation. It should be called periodically.\n *\n * @param lacpdu\t\tLACPDU received.\n * @param port\t\t\tPort on which LACPDU was received.\n */\nstatic void\nrx_machine(struct bond_dev_private *internals, uint8_t slave_id,\n\t\tstruct lacpdu *lacp)\n{\n\tstruct port *agg, *port = &mode_8023ad_ports[slave_id];\n\tuint64_t timeout;\n\n\tif (SM_FLAG(port, BEGIN)) {\n\t\t/* Initialize stuff */\n\t\tMODE4_DEBUG(\"-> INITIALIZE\\n\");\n\t\tSM_FLAG_CLR(port, MOVED);\n\t\tport->selected = UNSELECTED;\n\n\t\trecord_default(port);\n\n\t\tACTOR_STATE_CLR(port, EXPIRED);\n\t\ttimer_cancel(&port->current_while_timer);\n\n\t\t/* DISABLED: On initialization partner is out of sync */\n\t\tPARTNER_STATE_CLR(port, SYNCHRONIZATION);\n\n\t\t/* LACP DISABLED stuff if LACP not enabled on this port */\n\t\tif (!SM_FLAG(port, LACP_ENABLED))\n\t\t\tPARTNER_STATE_CLR(port, AGGREGATION);\n\t\telse\n\t\t\tPARTNER_STATE_SET(port, AGGREGATION);\n\t}\n\n\tif (!SM_FLAG(port, LACP_ENABLED)) {\n\t\t/* Update parameters only if state changed */\n\t\tif (!timer_is_stopped(&port->current_while_timer)) {\n\t\t\tport->selected = UNSELECTED;\n\t\t\trecord_default(port);\n\t\t\tPARTNER_STATE_CLR(port, AGGREGATION);\n\t\t\tACTOR_STATE_CLR(port, EXPIRED);\n\t\t\ttimer_cancel(&port->current_while_timer);\n\t\t}\n\t\treturn;\n\t}\n\n\tif (lacp) {\n\t\tMODE4_DEBUG(\"LACP -> CURRENT\\n\");\n\t\tBOND_PRINT_LACP(lacp);\n\t\t/* Update selected flag. If partner parameters are defaulted assume they\n\t\t * are match. If not defaulted compare LACP actor with ports parner\n\t\t * params. */\n\t\tif (!ACTOR_STATE(port, DEFAULTED) &&\n\t\t\t(ACTOR_STATE(port, AGGREGATION) != PARTNER_STATE(port, AGGREGATION)\n\t\t\t|| memcmp(&port->partner, &lacp->actor.port_params,\n\t\t\t\tsizeof(port->partner)) != 0)) {\n\t\t\tMODE4_DEBUG(\"selected <- UNSELECTED\\n\");\n\t\t\tport->selected = UNSELECTED;\n\t\t}\n\n\t\t/* Record this PDU actor params as partner params */\n\t\tmemcpy(&port->partner, &lacp->actor.port_params,\n\t\t\tsizeof(struct port_params));\n\t\tport->partner_state = lacp->actor.state;\n\n\t\t/* Partner parameters are not defaulted any more */\n\t\tACTOR_STATE_CLR(port, DEFAULTED);\n\n\t\t/* If LACP partner params match this port actor params */\n\t\tagg = &mode_8023ad_ports[port->aggregator_port_id];\n\t\tbool match = port->actor.system_priority ==\n\t\t\tlacp->partner.port_params.system_priority &&\n\t\t\tis_same_ether_addr(&agg->actor.system,\n\t\t\t&lacp->partner.port_params.system) &&\n\t\t\tport->actor.port_priority ==\n\t\t\tlacp->partner.port_params.port_priority &&\n\t\t\tport->actor.port_number ==\n\t\t\tlacp->partner.port_params.port_number;\n\n\t\t/* Update NTT if partners information are outdated (xored and masked\n\t\t * bits are set)*/\n\t\tuint8_t state_mask = STATE_LACP_ACTIVE | STATE_LACP_SHORT_TIMEOUT |\n\t\t\tSTATE_SYNCHRONIZATION | STATE_AGGREGATION;\n\n\t\tif (((port->actor_state ^ lacp->partner.state) & state_mask) ||\n\t\t\t\tmatch == false) {\n\t\t\tSM_FLAG_SET(port, NTT);\n\t\t}\n\n\t\t/* If LACP partner params match this port actor params */\n\t\tif (match == true && ACTOR_STATE(port, AGGREGATION) ==\n\t\t\t\tPARTNER_STATE(port,\tAGGREGATION))\n\t\t\tPARTNER_STATE_SET(port, SYNCHRONIZATION);\n\t\telse if (!PARTNER_STATE(port, AGGREGATION) && ACTOR_STATE(port,\n\t\t\t\tAGGREGATION))\n\t\t\tPARTNER_STATE_SET(port, SYNCHRONIZATION);\n\t\telse\n\t\t\tPARTNER_STATE_CLR(port, SYNCHRONIZATION);\n\n\t\tif (ACTOR_STATE(port, LACP_SHORT_TIMEOUT))\n\t\t\ttimeout = internals->mode4.short_timeout;\n\t\telse\n\t\t\ttimeout = internals->mode4.long_timeout;\n\n\t\ttimer_set(&port->current_while_timer, timeout);\n\t\tACTOR_STATE_CLR(port, EXPIRED);\n\t\treturn; /* No state change */\n\t}\n\n\t/* If CURRENT state timer is not running (stopped or expired)\n\t * transit to EXPIRED state from DISABLED or CURRENT */\n\tif (!timer_is_running(&port->current_while_timer)) {\n\t\tACTOR_STATE_SET(port, EXPIRED);\n\t\tPARTNER_STATE_CLR(port, SYNCHRONIZATION);\n\t\tPARTNER_STATE_SET(port, LACP_SHORT_TIMEOUT);\n\t\ttimer_set(&port->current_while_timer, internals->mode4.short_timeout);\n\t}\n}\n\n/**\n * Function handles periodic tx state machine.\n *\n * Function implements Periodic Transmission state machine from point 5.4.13\n * in 802.1AX documentation. It should be called periodically.\n *\n * @param port\t\t\tPort to handle state machine.\n */\nstatic void\nperiodic_machine(struct bond_dev_private *internals, uint8_t slave_id)\n{\n\tstruct port *port = &mode_8023ad_ports[slave_id];\n\t/* Calculate if either site is LACP enabled */\n\tuint64_t timeout;\n\tuint8_t active = ACTOR_STATE(port, LACP_ACTIVE) ||\n\t\tPARTNER_STATE(port, LACP_ACTIVE);\n\n\tuint8_t is_partner_fast, was_partner_fast;\n\t/* No periodic is on BEGIN, LACP DISABLE or when both sides are pasive */\n\tif (SM_FLAG(port, BEGIN) || !SM_FLAG(port, LACP_ENABLED) || !active) {\n\t\ttimer_cancel(&port->periodic_timer);\n\t\ttimer_force_expired(&port->tx_machine_timer);\n\t\tSM_FLAG_CLR(port, PARTNER_SHORT_TIMEOUT);\n\n\t\tMODE4_DEBUG(\"-> NO_PERIODIC ( %s%s%s)\\n\",\n\t\t\tSM_FLAG(port, BEGIN) ? \"begind \" : \"\",\n\t\t\tSM_FLAG(port, LACP_ENABLED) ? \"\" : \"LACP disabled \",\n\t\t\tactive ? \"LACP active \" : \"LACP pasive \");\n\t\treturn;\n\t}\n\n\tis_partner_fast = PARTNER_STATE(port, LACP_SHORT_TIMEOUT);\n\twas_partner_fast = SM_FLAG(port, PARTNER_SHORT_TIMEOUT);\n\n\t/* If periodic timer is not started, transit from NO PERIODIC to FAST/SLOW.\n\t * Other case: check if timer expire or partners settings changed. */\n\tif (!timer_is_stopped(&port->periodic_timer)) {\n\t\tif (timer_is_expired(&port->periodic_timer)) {\n\t\t\tSM_FLAG_SET(port, NTT);\n\t\t} else if (is_partner_fast != was_partner_fast) {\n\t\t\t/* Partners timeout was slow and now it is fast -> send LACP.\n\t\t\t * In other case (was fast and now it is slow) just switch\n\t\t\t * timeout to slow without forcing send of LACP (because standard\n\t\t\t * say so)*/\n\t\t\tif (!is_partner_fast)\n\t\t\t\tSM_FLAG_SET(port, NTT);\n\t\t} else\n\t\t\treturn; /* Nothing changed */\n\t}\n\n\t/* Handle state transition to FAST/SLOW LACP timeout */\n\tif (is_partner_fast) {\n\t\ttimeout = internals->mode4.fast_periodic_timeout;\n\t\tSM_FLAG_SET(port, PARTNER_SHORT_TIMEOUT);\n\t} else {\n\t\ttimeout = internals->mode4.slow_periodic_timeout;\n\t\tSM_FLAG_CLR(port, PARTNER_SHORT_TIMEOUT);\n\t}\n\n\ttimer_set(&port->periodic_timer, timeout);\n}\n\n/**\n * Function handles mux state machine.\n *\n * Function implements Mux Machine from point 5.4.15 in 802.1AX documentation.\n * It should be called periodically.\n *\n * @param port\t\t\tPort to handle state machine.\n */\nstatic void\nmux_machine(struct bond_dev_private *internals, uint8_t slave_id)\n{\n\tstruct port *port = &mode_8023ad_ports[slave_id];\n\n\t/* Save current state for later use */\n\tconst uint8_t state_mask = STATE_SYNCHRONIZATION | STATE_DISTRIBUTING |\n\t\tSTATE_COLLECTING;\n\n\t/* Enter DETACHED state on BEGIN condition or from any other state if\n\t * port was unselected */\n\tif (SM_FLAG(port, BEGIN) ||\n\t\t\tport->selected == UNSELECTED || (port->selected == STANDBY &&\n\t\t\t\t(port->actor_state & state_mask) != 0)) {\n\t\t/* detach mux from aggregator */\n\t\tport->actor_state &= ~state_mask;\n\t\t/* Set ntt to true if BEGIN condition or transition from any other state\n\t\t * which is indicated that wait_while_timer was started */\n\t\tif (SM_FLAG(port, BEGIN) ||\n\t\t\t\t!timer_is_stopped(&port->wait_while_timer)) {\n\t\t\tSM_FLAG_SET(port, NTT);\n\t\t\tMODE4_DEBUG(\"-> DETACHED\\n\");\n\t\t}\n\t\ttimer_cancel(&port->wait_while_timer);\n\t}\n\n\tif (timer_is_stopped(&port->wait_while_timer)) {\n\t\tif (port->selected == SELECTED || port->selected == STANDBY) {\n\t\t\ttimer_set(&port->wait_while_timer,\n\t\t\t\tinternals->mode4.aggregate_wait_timeout);\n\n\t\t\tMODE4_DEBUG(\"DETACHED -> WAITING\\n\");\n\t\t}\n\t\t/* Waiting state entered */\n\t\treturn;\n\t}\n\n\t/* Transit next state if port is ready */\n\tif (!timer_is_expired(&port->wait_while_timer))\n\t\treturn;\n\n\tif ((ACTOR_STATE(port, DISTRIBUTING) || ACTOR_STATE(port, COLLECTING)) &&\n\t\t!PARTNER_STATE(port, SYNCHRONIZATION)) {\n\t\t/* If in COLLECTING or DISTRIBUTING state and partner becomes out of\n\t\t * sync transit to ATACHED state. */\n\t\tACTOR_STATE_CLR(port, DISTRIBUTING);\n\t\tACTOR_STATE_CLR(port, COLLECTING);\n\t\t/* Clear actor sync to activate transit ATACHED in condition bellow */\n\t\tACTOR_STATE_CLR(port, SYNCHRONIZATION);\n\t\tMODE4_DEBUG(\"Out of sync -> ATTACHED\\n\");\n\t}\n\n\tif (!ACTOR_STATE(port, SYNCHRONIZATION)) {\n\t\t/* attach mux to aggregator */\n\t\tRTE_VERIFY((port->actor_state & (STATE_COLLECTING |\n\t\t\tSTATE_DISTRIBUTING)) == 0);\n\n\t\tACTOR_STATE_SET(port, SYNCHRONIZATION);\n\t\tSM_FLAG_SET(port, NTT);\n\t\tMODE4_DEBUG(\"ATTACHED Entered\\n\");\n\t} else if (!ACTOR_STATE(port, COLLECTING)) {\n\t\t/* Start collecting if in sync */\n\t\tif (PARTNER_STATE(port, SYNCHRONIZATION)) {\n\t\t\tMODE4_DEBUG(\"ATTACHED -> COLLECTING\\n\");\n\t\t\tACTOR_STATE_SET(port, COLLECTING);\n\t\t\tSM_FLAG_SET(port, NTT);\n\t\t}\n\t} else if (ACTOR_STATE(port, COLLECTING)) {\n\t\t/* Check if partner is in COLLECTING state. If so this port can\n\t\t * distribute frames to it */\n\t\tif (!ACTOR_STATE(port, DISTRIBUTING)) {\n\t\t\tif (PARTNER_STATE(port, COLLECTING)) {\n\t\t\t\t/* Enable DISTRIBUTING if partner is collecting */\n\t\t\t\tACTOR_STATE_SET(port, DISTRIBUTING);\n\t\t\t\tSM_FLAG_SET(port, NTT);\n\t\t\t\tMODE4_DEBUG(\"COLLECTING -> DISTRIBUTING\\n\");\n\t\t\t\tRTE_LOG(INFO, PMD,\n\t\t\t\t\t\"Bond %u: slave id %u distributing started.\\n\",\n\t\t\t\t\tinternals->port_id, slave_id);\n\t\t\t}\n\t\t} else {\n\t\t\tif (!PARTNER_STATE(port, COLLECTING)) {\n\t\t\t\t/* Disable DISTRIBUTING (enter COLLECTING state) if partner\n\t\t\t\t * is not collecting */\n\t\t\t\tACTOR_STATE_CLR(port, DISTRIBUTING);\n\t\t\t\tSM_FLAG_SET(port, NTT);\n\t\t\t\tMODE4_DEBUG(\"DISTRIBUTING -> COLLECTING\\n\");\n\t\t\t\tRTE_LOG(INFO, PMD,\n\t\t\t\t\t\"Bond %u: slave id %u distributing stopped.\\n\",\n\t\t\t\t\tinternals->port_id, slave_id);\n\t\t\t}\n\t\t}\n\t}\n}\n\n/**\n * Function handles transmit state machine.\n *\n * Function implements Transmit Machine from point 5.4.16 in 802.1AX\n * documentation.\n *\n * @param port\n */\nstatic void\ntx_machine(struct bond_dev_private *internals, uint8_t slave_id)\n{\n\tstruct port *agg, *port = &mode_8023ad_ports[slave_id];\n\n\tstruct rte_mbuf *lacp_pkt = NULL;\n\tstruct lacpdu_header *hdr;\n\tstruct lacpdu *lacpdu;\n\n\t/* If periodic timer is not running periodic machine is in NO PERIODIC and\n\t * according to 802.3ax standard tx machine should not transmit any frames\n\t * and set ntt to false. */\n\tif (timer_is_stopped(&port->periodic_timer))\n\t\tSM_FLAG_CLR(port, NTT);\n\n\tif (!SM_FLAG(port, NTT))\n\t\treturn;\n\n\tif (!timer_is_expired(&port->tx_machine_timer))\n\t\treturn;\n\n\tlacp_pkt = rte_pktmbuf_alloc(port->mbuf_pool);\n\tif (lacp_pkt == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"Failed to allocate LACP packet from pool\\n\");\n\t\treturn;\n\t}\n\n\tlacp_pkt->data_len = sizeof(*hdr);\n\tlacp_pkt->pkt_len = sizeof(*hdr);\n\n\thdr = rte_pktmbuf_mtod(lacp_pkt, struct lacpdu_header *);\n\n\t/* Source and destination MAC */\n\tether_addr_copy(&lacp_mac_addr, &hdr->eth_hdr.d_addr);\n\trte_eth_macaddr_get(slave_id, &hdr->eth_hdr.s_addr);\n\thdr->eth_hdr.ether_type = rte_cpu_to_be_16(ETHER_TYPE_SLOW);\n\n\tlacpdu = &hdr->lacpdu;\n\tmemset(lacpdu, 0, sizeof(*lacpdu));\n\n\t/* Initialize LACP part */\n\tlacpdu->subtype = SLOW_SUBTYPE_LACP;\n\tlacpdu->version_number = 1;\n\n\t/* ACTOR */\n\tlacpdu->actor.tlv_type_info = TLV_TYPE_ACTOR_INFORMATION;\n\tlacpdu->actor.info_length = sizeof(struct lacpdu_actor_partner_params);\n\tmemcpy(&hdr->lacpdu.actor.port_params, &port->actor,\n\t\t\tsizeof(port->actor));\n\tagg = &mode_8023ad_ports[port->aggregator_port_id];\n\tether_addr_copy(&agg->actor.system, &hdr->lacpdu.actor.port_params.system);\n\tlacpdu->actor.state = port->actor_state;\n\n\t/* PARTNER */\n\tlacpdu->partner.tlv_type_info = TLV_TYPE_PARTNER_INFORMATION;\n\tlacpdu->partner.info_length = sizeof(struct lacpdu_actor_partner_params);\n\tmemcpy(&lacpdu->partner.port_params, &port->partner,\n\t\t\tsizeof(struct port_params));\n\tlacpdu->partner.state = port->partner_state;\n\n\t/* Other fields */\n\tlacpdu->tlv_type_collector_info = TLV_TYPE_COLLECTOR_INFORMATION;\n\tlacpdu->collector_info_length = 0x10;\n\tlacpdu->collector_max_delay = 0;\n\n\tlacpdu->tlv_type_terminator = TLV_TYPE_TERMINATOR_INFORMATION;\n\tlacpdu->terminator_length = 0;\n\n\tif (rte_ring_enqueue(port->tx_ring, lacp_pkt) == -ENOBUFS) {\n\t\t/* If TX ring full, drop packet and free message. Retransmission\n\t\t * will happen in next function call. */\n\t\trte_pktmbuf_free(lacp_pkt);\n\t\tset_warning_flags(port, WRN_TX_QUEUE_FULL);\n\t\treturn;\n\t}\n\n\tMODE4_DEBUG(\"sending LACP frame\\n\");\n\tBOND_PRINT_LACP(lacpdu);\n\n\ttimer_set(&port->tx_machine_timer, internals->mode4.tx_period_timeout);\n\tSM_FLAG_CLR(port, NTT);\n}\n\n/**\n * Function assigns port to aggregator.\n *\n * @param bond_dev_private\tPointer to bond_dev_private structure.\n * @param port_pos\t\t\tPort to assign.\n */\nstatic void\nselection_logic(struct bond_dev_private *internals, uint8_t slave_id)\n{\n\tstruct port *agg, *port;\n\tuint8_t slaves_count, new_agg_id, i;\n\tuint8_t *slaves;\n\n\tslaves = internals->active_slaves;\n\tslaves_count = internals->active_slave_count;\n\tport = &mode_8023ad_ports[slave_id];\n\n\t/* Search for aggregator suitable for this port */\n\tfor (i = 0; i < slaves_count; ++i) {\n\t\tagg = &mode_8023ad_ports[slaves[i]];\n\t\t/* Skip ports that are not aggreagators */\n\t\tif (agg->aggregator_port_id != slaves[i])\n\t\t\tcontinue;\n\n\t\t/* Actors system ID is not checked since all slave device have the same\n\t\t * ID (MAC address). */\n\t\tif ((agg->actor.key == port->actor.key &&\n\t\t\tagg->partner.system_priority == port->partner.system_priority &&\n\t\t\tis_same_ether_addr(&agg->partner.system, &port->partner.system) == 1\n\t\t\t&& (agg->partner.key == port->partner.key)) &&\n\t\t\tis_zero_ether_addr(&port->partner.system) != 1 &&\n\t\t\t(agg->actor.key &\n\t\t\t\trte_cpu_to_be_16(BOND_LINK_FULL_DUPLEX_KEY)) != 0) {\n\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* By default, port uses it self as agregator */\n\tif (i == slaves_count)\n\t\tnew_agg_id = slave_id;\n\telse\n\t\tnew_agg_id = slaves[i];\n\n\tif (new_agg_id != port->aggregator_port_id) {\n\t\tport->aggregator_port_id = new_agg_id;\n\n\t\tMODE4_DEBUG(\"-> SELECTED: ID=%3u\\n\"\n\t\t\t\"\\t%s aggregator ID=%3u\\n\",\n\t\t\tport->aggregator_port_id,\n\t\t\tport->aggregator_port_id == slave_id ?\n\t\t\t\t\"aggregator not found, using default\" : \"aggregator found\",\n\t\t\tport->aggregator_port_id);\n\t}\n\n\tport->selected = SELECTED;\n}\n\n/* Function maps DPDK speed to bonding speed stored in key field */\nstatic uint16_t\nlink_speed_key(uint16_t speed) {\n\tuint16_t key_speed;\n\n\tswitch (speed) {\n\tcase ETH_LINK_SPEED_AUTONEG:\n\t\tkey_speed = 0x00;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_10:\n\t\tkey_speed = BOND_LINK_SPEED_KEY_10M;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_100:\n\t\tkey_speed = BOND_LINK_SPEED_KEY_100M;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_1000:\n\t\tkey_speed = BOND_LINK_SPEED_KEY_1000M;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_10G:\n\t\tkey_speed = BOND_LINK_SPEED_KEY_10G;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_20G:\n\t\tkey_speed = BOND_LINK_SPEED_KEY_20G;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_40G:\n\t\tkey_speed = BOND_LINK_SPEED_KEY_40G;\n\t\tbreak;\n\tdefault:\n\t\t/* Unknown speed*/\n\t\tkey_speed = 0xFFFF;\n\t}\n\n\treturn key_speed;\n}\n\nstatic void\nbond_mode_8023ad_periodic_cb(void *arg)\n{\n\tstruct rte_eth_dev *bond_dev = arg;\n\tstruct bond_dev_private *internals = bond_dev->data->dev_private;\n\tstruct port *port;\n\tstruct rte_eth_link link_info;\n\tstruct ether_addr slave_addr;\n\n\tvoid *pkt = NULL;\n\tuint8_t i, slave_id;\n\n\n\t/* Update link status on each port */\n\tfor (i = 0; i < internals->active_slave_count; i++) {\n\t\tuint16_t key;\n\n\t\tslave_id = internals->active_slaves[i];\n\t\trte_eth_link_get(slave_id, &link_info);\n\t\trte_eth_macaddr_get(slave_id, &slave_addr);\n\n\t\tif (link_info.link_status != 0) {\n\t\t\tkey = link_speed_key(link_info.link_speed) << 1;\n\t\t\tif (link_info.link_duplex == ETH_LINK_FULL_DUPLEX)\n\t\t\t\tkey |= BOND_LINK_FULL_DUPLEX_KEY;\n\t\t} else\n\t\t\tkey = 0;\n\n\t\tport = &mode_8023ad_ports[slave_id];\n\n\t\tkey = rte_cpu_to_be_16(key);\n\t\tif (key != port->actor.key) {\n\t\t\tif (!(key & rte_cpu_to_be_16(BOND_LINK_FULL_DUPLEX_KEY)))\n\t\t\t\tset_warning_flags(port, WRN_NOT_LACP_CAPABLE);\n\n\t\t\tport->actor.key = key;\n\t\t\tSM_FLAG_SET(port, NTT);\n\t\t}\n\n\t\tif (!is_same_ether_addr(&port->actor.system, &slave_addr)) {\n\t\t\tether_addr_copy(&slave_addr, &port->actor.system);\n\t\t\tif (port->aggregator_port_id == slave_id)\n\t\t\t\tSM_FLAG_SET(port, NTT);\n\t\t}\n\t}\n\n\tfor (i = 0; i < internals->active_slave_count; i++) {\n\t\tslave_id = internals->active_slaves[i];\n\t\tport = &mode_8023ad_ports[slave_id];\n\n\t\tif ((port->actor.key &\n\t\t\t\trte_cpu_to_be_16(BOND_LINK_FULL_DUPLEX_KEY)) == 0) {\n\n\t\t\tSM_FLAG_SET(port, BEGIN);\n\n\t\t\t/* LACP is disabled on half duples or link is down */\n\t\t\tif (SM_FLAG(port, LACP_ENABLED)) {\n\t\t\t\t/* If port was enabled set it to BEGIN state */\n\t\t\t\tSM_FLAG_CLR(port, LACP_ENABLED);\n\t\t\t\tACTOR_STATE_CLR(port, DISTRIBUTING);\n\t\t\t\tACTOR_STATE_CLR(port, COLLECTING);\n\t\t\t}\n\n\t\t\t/* Skip this port processing */\n\t\t\tcontinue;\n\t\t}\n\n\t\tSM_FLAG_SET(port, LACP_ENABLED);\n\n\t\t/* Find LACP packet to this port. Do not check subtype, it is done in\n\t\t * function that queued packet */\n\t\tif (rte_ring_dequeue(port->rx_ring, &pkt) == 0) {\n\t\t\tstruct rte_mbuf *lacp_pkt = pkt;\n\t\t\tstruct lacpdu_header *lacp;\n\n\t\t\tlacp = rte_pktmbuf_mtod(lacp_pkt, struct lacpdu_header *);\n\t\t\tRTE_VERIFY(lacp->lacpdu.subtype == SLOW_SUBTYPE_LACP);\n\n\t\t\t/* This is LACP frame so pass it to rx_machine */\n\t\t\trx_machine(internals, slave_id, &lacp->lacpdu);\n\t\t\trte_pktmbuf_free(lacp_pkt);\n\t\t} else\n\t\t\trx_machine(internals, slave_id, NULL);\n\n\t\tperiodic_machine(internals, slave_id);\n\t\tmux_machine(internals, slave_id);\n\t\ttx_machine(internals, slave_id);\n\t\tselection_logic(internals, slave_id);\n\n\t\tSM_FLAG_CLR(port, BEGIN);\n\t\tshow_warnings(slave_id);\n\t}\n\n\trte_eal_alarm_set(internals->mode4.update_timeout_us,\n\t\t\tbond_mode_8023ad_periodic_cb, arg);\n}\n\nvoid\nbond_mode_8023ad_activate_slave(struct rte_eth_dev *bond_dev, uint8_t slave_id)\n{\n\tstruct bond_dev_private *internals = bond_dev->data->dev_private;\n\n\tstruct port *port = &mode_8023ad_ports[slave_id];\n\tstruct port_params initial = {\n\t\t\t.system = { { 0 } },\n\t\t\t.system_priority = rte_cpu_to_be_16(0xFFFF),\n\t\t\t.key = rte_cpu_to_be_16(BOND_LINK_FULL_DUPLEX_KEY),\n\t\t\t.port_priority = rte_cpu_to_be_16(0x00FF),\n\t\t\t.port_number = 0,\n\t};\n\n\tchar mem_name[RTE_ETH_NAME_MAX_LEN];\n\tint socket_id;\n\tunsigned element_size;\n\n\t/* Given slave mus not be in active list */\n\tRTE_VERIFY(find_slave_by_id(internals->active_slaves,\n\tinternals->active_slave_count, slave_id) == internals->active_slave_count);\n\n\tmemcpy(&port->actor, &initial, sizeof(struct port_params));\n\t/* Standard requires that port ID must be grater than 0.\n\t * Add 1 do get corresponding port_number */\n\tport->actor.port_number = rte_cpu_to_be_16((uint16_t)slave_id + 1);\n\n\tmemcpy(&port->partner, &initial, sizeof(struct port_params));\n\n\t/* default states */\n\tport->actor_state = STATE_AGGREGATION | STATE_LACP_ACTIVE | STATE_DEFAULTED;\n\tport->partner_state = STATE_LACP_ACTIVE;\n\tport->sm_flags = SM_FLAGS_BEGIN;\n\n\t/* use this port as agregator */\n\tport->aggregator_port_id = slave_id;\n\trte_eth_promiscuous_enable(slave_id);\n\n\ttimer_cancel(&port->warning_timer);\n\n\tif (port->mbuf_pool != NULL)\n\t\treturn;\n\n\tRTE_VERIFY(port->rx_ring == NULL);\n\tRTE_VERIFY(port->tx_ring == NULL);\n\tsocket_id = rte_eth_devices[slave_id].pci_dev->numa_node;\n\n\telement_size = sizeof(struct slow_protocol_frame) + sizeof(struct rte_mbuf)\n\t\t\t\t+ RTE_PKTMBUF_HEADROOM;\n\n\t /* How big memory pool should be? If driver will not\n\t * free packets quick enough there will be ENOMEM in tx_machine.\n\t * For now give 511 pkts * max number of queued TX packets per slave.\n\t * Hope it will be enough. */\n\tsnprintf(mem_name, RTE_DIM(mem_name), \"slave_port%u_pool\", slave_id);\n\tport->mbuf_pool = rte_mempool_create(mem_name,\n\t\tBOND_MODE_8023AX_SLAVE_TX_PKTS * 512 - 1,\n\t\telement_size,\n\t\tRTE_MEMPOOL_CACHE_MAX_SIZE >= 32 ? 32 : RTE_MEMPOOL_CACHE_MAX_SIZE,\n\t\tsizeof(struct rte_pktmbuf_pool_private), rte_pktmbuf_pool_init,\n\t\tNULL, rte_pktmbuf_init, NULL, socket_id, MEMPOOL_F_NO_SPREAD);\n\n\t/* Any memory allocation failure in initalization is critical because\n\t * resources can't be free, so reinitialization is impossible. */\n\tif (port->mbuf_pool == NULL) {\n\t\trte_panic(\"Slave %u: Failed to create memory pool '%s': %s\\n\",\n\t\t\tslave_id, mem_name, rte_strerror(rte_errno));\n\t}\n\n\tsnprintf(mem_name, RTE_DIM(mem_name), \"slave_%u_rx\", slave_id);\n\tport->rx_ring = rte_ring_create(mem_name,\n\t\t\trte_align32pow2(BOND_MODE_8023AX_SLAVE_RX_PKTS), socket_id, 0);\n\n\tif (port->rx_ring == NULL) {\n\t\trte_panic(\"Slave %u: Failed to create rx ring '%s': %s\\n\", slave_id,\n\t\t\tmem_name, rte_strerror(rte_errno));\n\t}\n\n\t/* TX ring is at least one pkt longer to make room for marker packet. */\n\tsnprintf(mem_name, RTE_DIM(mem_name), \"slave_%u_tx\", slave_id);\n\tport->tx_ring = rte_ring_create(mem_name,\n\t\t\trte_align32pow2(BOND_MODE_8023AX_SLAVE_TX_PKTS + 1), socket_id, 0);\n\n\tif (port->tx_ring == NULL) {\n\t\trte_panic(\"Slave %u: Failed to create tx ring '%s': %s\\n\", slave_id,\n\t\t\tmem_name, rte_strerror(rte_errno));\n\t}\n}\n\nint\nbond_mode_8023ad_deactivate_slave(struct rte_eth_dev *bond_dev,\n\t\tuint8_t slave_id)\n{\n\tstruct bond_dev_private *internals = bond_dev->data->dev_private;\n\tvoid *pkt = NULL;\n\tstruct port *port;\n\tuint8_t i;\n\n\t/* Given slave mus be in active list */\n\tRTE_VERIFY(find_slave_by_id(internals->active_slaves,\n\tinternals->active_slave_count, slave_id) < internals->active_slave_count);\n\n\t/* Exclude slave from transmit policy. If this slave is an aggregator\n\t * make all aggregated slaves unselected to force sellection logic\n\t * to select suitable aggregator for this port. */\n\tfor (i = 0; i < internals->active_slave_count; i++) {\n\t\tport = &mode_8023ad_ports[internals->active_slaves[i]];\n\t\tif (port->aggregator_port_id != slave_id)\n\t\t\tcontinue;\n\n\t\tport->selected = UNSELECTED;\n\n\t\t/* Use default aggregator */\n\t\tport->aggregator_port_id = internals->active_slaves[i];\n\t}\n\n\tport = &mode_8023ad_ports[slave_id];\n\tport->selected = UNSELECTED;\n\tport->actor_state &= ~(STATE_SYNCHRONIZATION | STATE_DISTRIBUTING |\n\t\t\tSTATE_COLLECTING);\n\n\twhile (rte_ring_dequeue(port->rx_ring, &pkt) == 0)\n\t\trte_pktmbuf_free((struct rte_mbuf *)pkt);\n\n\twhile (rte_ring_dequeue(port->tx_ring, &pkt) == 0)\n\t\t\trte_pktmbuf_free((struct rte_mbuf *)pkt);\n\treturn 0;\n}\n\nvoid\nbond_mode_8023ad_mac_address_update(struct rte_eth_dev *bond_dev)\n{\n\tstruct bond_dev_private *internals = bond_dev->data->dev_private;\n\tstruct ether_addr slave_addr;\n\tstruct port *slave, *agg_slave;\n\tuint8_t slave_id, i, j;\n\n\tbond_mode_8023ad_stop(bond_dev);\n\n\tfor (i = 0; i < internals->active_slave_count; i++) {\n\t\tslave_id = internals->active_slaves[i];\n\t\tslave = &mode_8023ad_ports[slave_id];\n\t\trte_eth_macaddr_get(slave_id, &slave_addr);\n\n\t\tif (is_same_ether_addr(&slave_addr, &slave->actor.system))\n\t\t\tcontinue;\n\n\t\tether_addr_copy(&slave_addr, &slave->actor.system);\n\t\t/* Do nothing if this port is not an aggregator. In other case\n\t\t * Set NTT flag on every port that use this aggregator. */\n\t\tif (slave->aggregator_port_id != slave_id)\n\t\t\tcontinue;\n\n\t\tfor (j = 0; j < internals->active_slave_count; j++) {\n\t\t\tagg_slave = &mode_8023ad_ports[internals->active_slaves[j]];\n\t\t\tif (agg_slave->aggregator_port_id == slave_id)\n\t\t\t\tSM_FLAG_SET(agg_slave, NTT);\n\t\t}\n\t}\n\n\tif (bond_dev->data->dev_started)\n\t\tbond_mode_8023ad_start(bond_dev);\n}\n\nvoid\nbond_mode_8023ad_conf_get(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_bond_8023ad_conf *conf)\n{\n\tstruct bond_dev_private *internals = dev->data->dev_private;\n\tstruct mode8023ad_private *mode4 = &internals->mode4;\n\tuint64_t ms_ticks = rte_get_tsc_hz() / 1000;\n\n\tconf->fast_periodic_ms = mode4->fast_periodic_timeout / ms_ticks;\n\tconf->slow_periodic_ms = mode4->slow_periodic_timeout / ms_ticks;\n\tconf->short_timeout_ms = mode4->short_timeout / ms_ticks;\n\tconf->long_timeout_ms = mode4->long_timeout / ms_ticks;\n\tconf->aggregate_wait_timeout_ms = mode4->aggregate_wait_timeout / ms_ticks;\n\tconf->tx_period_ms = mode4->tx_period_timeout / ms_ticks;\n\tconf->update_timeout_ms = mode4->update_timeout_us / 1000;\n}\n\nvoid\nbond_mode_8023ad_setup(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_bond_8023ad_conf *conf)\n{\n\tstruct rte_eth_bond_8023ad_conf def_conf;\n\tstruct bond_dev_private *internals = dev->data->dev_private;\n\tstruct mode8023ad_private *mode4 = &internals->mode4;\n\tuint64_t ms_ticks = rte_get_tsc_hz() / 1000;\n\n\tif (conf == NULL) {\n\t\tconf = &def_conf;\n\t\tconf->fast_periodic_ms = BOND_8023AD_FAST_PERIODIC_MS;\n\t\tconf->slow_periodic_ms = BOND_8023AD_SLOW_PERIODIC_MS;\n\t\tconf->short_timeout_ms = BOND_8023AD_SHORT_TIMEOUT_MS;\n\t\tconf->long_timeout_ms = BOND_8023AD_LONG_TIMEOUT_MS;\n\t\tconf->aggregate_wait_timeout_ms = BOND_8023AD_AGGREGATE_WAIT_TIMEOUT_MS;\n\t\tconf->tx_period_ms = BOND_8023AD_TX_MACHINE_PERIOD_MS;\n\t\tconf->rx_marker_period_ms = BOND_8023AD_RX_MARKER_PERIOD_MS;\n\t\tconf->update_timeout_ms = BOND_MODE_8023AX_UPDATE_TIMEOUT_MS;\n\t}\n\n\tmode4->fast_periodic_timeout = conf->fast_periodic_ms * ms_ticks;\n\tmode4->slow_periodic_timeout = conf->slow_periodic_ms * ms_ticks;\n\tmode4->short_timeout = conf->short_timeout_ms * ms_ticks;\n\tmode4->long_timeout = conf->long_timeout_ms * ms_ticks;\n\tmode4->aggregate_wait_timeout = conf->aggregate_wait_timeout_ms * ms_ticks;\n\tmode4->tx_period_timeout = conf->tx_period_ms * ms_ticks;\n\tmode4->rx_marker_timeout = conf->rx_marker_period_ms * ms_ticks;\n\tmode4->update_timeout_us = conf->update_timeout_ms * 1000;\n}\n\nint\nbond_mode_8023ad_enable(struct rte_eth_dev *bond_dev)\n{\n\tstruct bond_dev_private *internals = bond_dev->data->dev_private;\n\tuint8_t i;\n\n\tfor (i = 0; i < internals->active_slave_count; i++)\n\t\tbond_mode_8023ad_activate_slave(bond_dev, i);\n\n\treturn 0;\n}\n\nint\nbond_mode_8023ad_start(struct rte_eth_dev *bond_dev)\n{\n\treturn rte_eal_alarm_set(BOND_MODE_8023AX_UPDATE_TIMEOUT_MS * 1000,\n\t\t\t&bond_mode_8023ad_periodic_cb, bond_dev);\n}\n\nvoid\nbond_mode_8023ad_stop(struct rte_eth_dev *bond_dev)\n{\n\trte_eal_alarm_cancel(&bond_mode_8023ad_periodic_cb, bond_dev);\n}\n\nvoid\nbond_mode_8023ad_handle_slow_pkt(struct bond_dev_private *internals,\n\tuint8_t slave_id, struct rte_mbuf *pkt)\n{\n\tstruct mode8023ad_private *mode4 = &internals->mode4;\n\tstruct port *port = &mode_8023ad_ports[slave_id];\n\tstruct marker_header *m_hdr;\n\tuint64_t marker_timer, old_marker_timer;\n\tint retval;\n\tuint8_t wrn, subtype;\n\t/* If packet is a marker, we send response now by reusing given packet\n\t * and update only source MAC, destination MAC is multicast so don't\n\t * update it. Other frames will be handled later by state machines */\n\tsubtype = rte_pktmbuf_mtod(pkt,\n\t\t\tstruct slow_protocol_frame *)->slow_protocol.subtype;\n\n\tif (subtype == SLOW_SUBTYPE_MARKER) {\n\t\tm_hdr = rte_pktmbuf_mtod(pkt, struct marker_header *);\n\n\t\tif (likely(m_hdr->marker.tlv_type_marker != MARKER_TLV_TYPE_INFO)) {\n\t\t\twrn = WRN_UNKNOWN_MARKER_TYPE;\n\t\t\tgoto free_out;\n\t\t}\n\n\t\t/* Setup marker timer. Do it in loop in case concurent access. */\n\t\tdo {\n\t\t\told_marker_timer = port->rx_marker_timer;\n\t\t\tif (!timer_is_expired(&old_marker_timer)) {\n\t\t\t\twrn = WRN_RX_MARKER_TO_FAST;\n\t\t\t\tgoto free_out;\n\t\t\t}\n\n\t\t\ttimer_set(&marker_timer, mode4->rx_marker_timeout);\n\t\t\tretval = rte_atomic64_cmpset(&port->rx_marker_timer,\n\t\t\t\told_marker_timer, marker_timer);\n\t\t} while (unlikely(retval == 0));\n\n\t\tm_hdr->marker.tlv_type_marker = MARKER_TLV_TYPE_RESP;\n\t\trte_eth_macaddr_get(slave_id, &m_hdr->eth_hdr.s_addr);\n\n\t\tif (unlikely(rte_ring_enqueue(port->tx_ring, pkt) == -ENOBUFS)) {\n\t\t\t/* reset timer */\n\t\t\tport->rx_marker_timer = 0;\n\t\t\twrn = WRN_TX_QUEUE_FULL;\n\t\t\tgoto free_out;\n\t\t}\n\t} else if (likely(subtype == SLOW_SUBTYPE_LACP)) {\n\t\tif (unlikely(rte_ring_enqueue(port->rx_ring, pkt) == -ENOBUFS)) {\n\t\t\t/* If RX fing full free lacpdu message and drop packet */\n\t\t\twrn = WRN_RX_QUEUE_FULL;\n\t\t\tgoto free_out;\n\t\t}\n\t} else {\n\t\twrn = WRN_UNKNOWN_SLOW_TYPE;\n\t\tgoto free_out;\n\t}\n\n\treturn;\n\nfree_out:\n\tset_warning_flags(port, wrn);\n\trte_pktmbuf_free(pkt);\n}\n\nint\nrte_eth_bond_8023ad_conf_get(uint8_t port_id,\n\t\tstruct rte_eth_bond_8023ad_conf *conf)\n{\n\tstruct rte_eth_dev *bond_dev;\n\n\tif (valid_bonded_port_id(port_id) != 0)\n\t\treturn -EINVAL;\n\n\tif (conf == NULL)\n\t\treturn -EINVAL;\n\n\tbond_dev = &rte_eth_devices[port_id];\n\tbond_mode_8023ad_conf_get(bond_dev, conf);\n\treturn 0;\n}\n\nint\nrte_eth_bond_8023ad_setup(uint8_t port_id,\n\t\tstruct rte_eth_bond_8023ad_conf *conf)\n{\n\tstruct rte_eth_dev *bond_dev;\n\n\tif (valid_bonded_port_id(port_id) != 0)\n\t\treturn -EINVAL;\n\n\tif (conf != NULL) {\n\t\t/* Basic sanity check */\n\t\tif (conf->slow_periodic_ms == 0 ||\n\t\t\t\tconf->fast_periodic_ms >= conf->slow_periodic_ms ||\n\t\t\t\tconf->long_timeout_ms == 0 ||\n\t\t\t\tconf->short_timeout_ms >= conf->long_timeout_ms ||\n\t\t\t\tconf->aggregate_wait_timeout_ms == 0 ||\n\t\t\t\tconf->tx_period_ms == 0 ||\n\t\t\t\tconf->rx_marker_period_ms == 0 ||\n\t\t\t\tconf->update_timeout_ms == 0) {\n\t\t\tRTE_LOG(ERR, PMD, \"given mode 4 configuration is invalid\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\tbond_dev = &rte_eth_devices[port_id];\n\tbond_mode_8023ad_setup(bond_dev, conf);\n\n\treturn 0;\n}\n\nint\nrte_eth_bond_8023ad_slave_info(uint8_t port_id, uint8_t slave_id,\n\t\tstruct rte_eth_bond_8023ad_slave_info *info)\n{\n\tstruct rte_eth_dev *bond_dev;\n\tstruct bond_dev_private *internals;\n\tstruct port *port;\n\n\tif (info == NULL || valid_bonded_port_id(port_id) != 0 ||\n\t\t\trte_eth_bond_mode_get(port_id) != BONDING_MODE_8023AD)\n\t\treturn -EINVAL;\n\n\tbond_dev = &rte_eth_devices[port_id];\n\n\tinternals = bond_dev->data->dev_private;\n\tif (find_slave_by_id(internals->active_slaves,\n\t\t\tinternals->active_slave_count, slave_id) ==\n\t\t\t\tinternals->active_slave_count)\n\t\treturn -EINVAL;\n\n\tport = &mode_8023ad_ports[slave_id];\n\tinfo->selected = port->selected;\n\n\tinfo->actor_state = port->actor_state;\n\trte_memcpy(&info->actor, &port->actor, sizeof(port->actor));\n\n\tinfo->partner_state = port->partner_state;\n\trte_memcpy(&info->partner, &port->partner, sizeof(port->partner));\n\n\tinfo->agg_port_id = port->aggregator_port_id;\n\treturn 0;\n}\n" }, { "path": "drivers/net/bonding/rte_eth_bond_8023ad.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef RTE_ETH_BOND_8023AD_H_\n#define RTE_ETH_BOND_8023AD_H_\n\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Actor/partner states\n */\n#define STATE_LACP_ACTIVE 0x01\n#define STATE_LACP_SHORT_TIMEOUT 0x02\n#define STATE_AGGREGATION 0x04\n#define STATE_SYNCHRONIZATION 0x08\n#define STATE_COLLECTING 0x10\n#define STATE_DISTRIBUTING 0x20\n/** Partners parameters are defaulted */\n#define STATE_DEFAULTED 0x40\n#define STATE_EXPIRED 0x80\n\n#define TLV_TYPE_ACTOR_INFORMATION 0x01\n#define TLV_TYPE_PARTNER_INFORMATION 0x02\n#define TLV_TYPE_COLLECTOR_INFORMATION 0x03\n#define TLV_TYPE_TERMINATOR_INFORMATION 0x00\n\n#define SLOW_SUBTYPE_LACP 0x01\n#define SLOW_SUBTYPE_MARKER 0x02\n\n#define MARKER_TLV_TYPE_INFO 0x01\n#define MARKER_TLV_TYPE_RESP 0x02\n\nenum rte_bond_8023ad_selection {\n\tUNSELECTED,\n\tSTANDBY,\n\tSELECTED\n};\n\n/** Generic slow protocol structure */\nstruct slow_protocol {\n\tuint8_t subtype;\n\tuint8_t reserved_119[119];\n} __attribute__((__packed__));\n\n/** Generic slow protocol frame type structure */\nstruct slow_protocol_frame {\n\tstruct ether_hdr eth_hdr;\n\tstruct slow_protocol slow_protocol;\n} __attribute__((__packed__));\n\nstruct port_params {\n\tuint16_t system_priority;\n\t/**< System priority (unused in current implementation) */\n\tstruct ether_addr system;\n\t/**< System ID - Slave MAC address, same as bonding MAC address */\n\tuint16_t key;\n\t/**< Speed information (implementation dependednt) and duplex. */\n\tuint16_t port_priority;\n\t/**< Priority of this (unused in current implementation) */\n\tuint16_t port_number;\n\t/**< Port number. It corresponds to slave port id. */\n} __attribute__((__packed__));\n\nstruct lacpdu_actor_partner_params {\n\tuint8_t tlv_type_info;\n\tuint8_t info_length;\n\tstruct port_params port_params;\n\tuint8_t state;\n\tuint8_t reserved_3[3];\n} __attribute__((__packed__));\n\n/** LACPDU structure (5.4.2 in 802.1AX documentation). */\nstruct lacpdu {\n\tuint8_t subtype;\n\tuint8_t version_number;\n\n\tstruct lacpdu_actor_partner_params actor;\n\tstruct lacpdu_actor_partner_params partner;\n\n\tuint8_t tlv_type_collector_info;\n\tuint8_t collector_info_length;\n\tuint16_t collector_max_delay;\n\tuint8_t reserved_12[12];\n\n\tuint8_t tlv_type_terminator;\n\tuint8_t terminator_length;\n\tuint8_t reserved_50[50];\n} __attribute__((__packed__));\n\n/** LACPDU frame: Contains ethernet header and LACPDU. */\nstruct lacpdu_header {\n\tstruct ether_hdr eth_hdr;\n\tstruct lacpdu lacpdu;\n} __attribute__((__packed__));\n\nstruct marker {\n\tuint8_t subtype;\n\tuint8_t version_number;\n\n\tuint8_t tlv_type_marker;\n\tuint8_t info_length;\n\tuint16_t requester_port;\n\tstruct ether_addr requester_system;\n\tuint32_t requester_transaction_id;\n\tuint8_t reserved_2[2];\n\n\tuint8_t tlv_type_terminator;\n\tuint8_t terminator_length;\n\tuint8_t reserved_90[90];\n} __attribute__((__packed__));\n\nstruct marker_header {\n\tstruct ether_hdr eth_hdr;\n\tstruct marker marker;\n} __attribute__((__packed__));\n\nstruct rte_eth_bond_8023ad_conf {\n\tuint32_t fast_periodic_ms;\n\tuint32_t slow_periodic_ms;\n\tuint32_t short_timeout_ms;\n\tuint32_t long_timeout_ms;\n\tuint32_t aggregate_wait_timeout_ms;\n\tuint32_t tx_period_ms;\n\tuint32_t rx_marker_period_ms;\n\tuint32_t update_timeout_ms;\n};\n\nstruct rte_eth_bond_8023ad_slave_info {\n\tenum rte_bond_8023ad_selection selected;\n\tuint8_t actor_state;\n\tstruct port_params actor;\n\tuint8_t partner_state;\n\tstruct port_params partner;\n\tuint8_t agg_port_id;\n};\n\n/**\n * @internal\n *\n * Function returns current configuration of 802.3AX mode.\n *\n * @param port_id Bonding device id\n * @param conf\t\tPointer to timeout structure.\n *\n * @return\n * 0 - if ok\n * -EINVAL if conf is NULL\n */\nint\nrte_eth_bond_8023ad_conf_get(uint8_t port_id,\n\t\tstruct rte_eth_bond_8023ad_conf *conf);\n\n/**\n * @internal\n *\n * Function set new configuration of 802.3AX mode.\n *\n * @param port_id Bonding device id\n * @param conf\t\tConfiguration, if NULL set default configuration.\n * @return\n * 0 - if ok\n * -EINVAL if configuration is invalid.\n */\nint\nrte_eth_bond_8023ad_setup(uint8_t port_id,\n\t\tstruct rte_eth_bond_8023ad_conf *conf);\n\n/**\n * @internal\n *\n * Function returns current state of given slave device.\n *\n * @param slave_id Port id of valid slave.\n * @param conf\t\tbuffer for configuration\n * @return\n * 0 - if ok\n * -EINVAL if conf is NULL or slave id is invalid (not a slave of given\n * bonded device or is not inactive).\n */\nint\nrte_eth_bond_8023ad_slave_info(uint8_t port_id, uint8_t slave_id,\n\t\tstruct rte_eth_bond_8023ad_slave_info *conf);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* RTE_ETH_BOND_8023AD_H_ */\n" }, { "path": "drivers/net/bonding/rte_eth_bond_8023ad_private.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef RTE_ETH_BOND_8023AD_PRIVATE_H_\n#define RTE_ETH_BOND_8023AD_PRIVATE_H_\n\n#include \n\n#include \n#include \n#include \n\n#include \"rte_eth_bond_8023ad.h\"\n\n#define BOND_MODE_8023AX_UPDATE_TIMEOUT_MS 100\n/** Maximum number of packets to one slave queued in TX ring. */\n#define BOND_MODE_8023AX_SLAVE_RX_PKTS 3\n/** Maximum number of LACP packets from one slave queued in TX ring. */\n#define BOND_MODE_8023AX_SLAVE_TX_PKTS 1\n/**\n * Timeouts deffinitions (5.4.4 in 802.1AX documentation).\n */\n#define BOND_8023AD_FAST_PERIODIC_MS 900\n#define BOND_8023AD_SLOW_PERIODIC_MS 29000\n#define BOND_8023AD_SHORT_TIMEOUT_MS 3000\n#define BOND_8023AD_LONG_TIMEOUT_MS 90000\n#define BOND_8023AD_CHURN_DETECTION_TIMEOUT_MS 60000\n#define BOND_8023AD_AGGREGATE_WAIT_TIMEOUT_MS 2000\n#define BOND_8023AD_TX_MACHINE_PERIOD_MS 500\n#define BOND_8023AD_RX_MARKER_PERIOD_MS 2000\n\n/**\n * Interval of showing warning message from state machines. All messages will\n * be held (and gathered together) to prevent flooding.\n * This is no parto of 802.1AX standard.\n */\n#define BOND_8023AD_WARNINGS_PERIOD_MS 1000\n\n\n\n/**\n * State machine flags\n */\n#define SM_FLAGS_BEGIN 0x0001\n#define SM_FLAGS_LACP_ENABLED 0x0002\n#define SM_FLAGS_ACTOR_CHURN 0x0004\n#define SM_FLAGS_PARTNER_CHURN 0x0008\n#define SM_FLAGS_MOVED 0x0100\n#define SM_FLAGS_PARTNER_SHORT_TIMEOUT 0x0200\n#define SM_FLAGS_NTT 0x0400\n\n#define BOND_LINK_FULL_DUPLEX_KEY 0x01\n#define BOND_LINK_SPEED_KEY_10M 0x02\n#define BOND_LINK_SPEED_KEY_100M 0x04\n#define BOND_LINK_SPEED_KEY_1000M 0x08\n#define BOND_LINK_SPEED_KEY_10G 0x10\n#define BOND_LINK_SPEED_KEY_20G 0x11\n#define BOND_LINK_SPEED_KEY_40G 0x12\n\n#define WRN_RX_MARKER_TO_FAST 0x01\n#define WRN_UNKNOWN_SLOW_TYPE 0x02\n#define WRN_UNKNOWN_MARKER_TYPE 0x04\n#define WRN_NOT_LACP_CAPABLE 0x08\n#define WRN_RX_QUEUE_FULL 0x10\n#define WRN_TX_QUEUE_FULL 0x20\n\n#define CHECK_FLAGS(_variable, _f) ((_variable) & (_f))\n#define SET_FLAGS(_variable, _f) ((_variable) |= (_f))\n#define CLEAR_FLAGS(_variable, _f) ((_variable) &= ~(_f))\n\n#define SM_FLAG(_p, _f) (!!CHECK_FLAGS((_p)->sm_flags, SM_FLAGS_ ## _f))\n#define SM_FLAG_SET(_p, _f) SET_FLAGS((_p)->sm_flags, SM_FLAGS_ ## _f)\n#define SM_FLAG_CLR(_p, _f) CLEAR_FLAGS((_p)->sm_flags, SM_FLAGS_ ## _f)\n\n#define ACTOR_STATE(_p, _f) (!!CHECK_FLAGS((_p)->actor_state, STATE_ ## _f))\n#define ACTOR_STATE_SET(_p, _f) SET_FLAGS((_p)->actor_state, STATE_ ## _f)\n#define ACTOR_STATE_CLR(_p, _f) CLEAR_FLAGS((_p)->actor_state, STATE_ ## _f)\n\n#define PARTNER_STATE(_p, _f) (!!CHECK_FLAGS((_p)->partner_state, STATE_ ## _f))\n#define PARTNER_STATE_SET(_p, _f) SET_FLAGS((_p)->partner_state, STATE_ ## _f)\n#define PARTNER_STATE_CLR(_p, _f) CLEAR_FLAGS((_p)->partner_state, STATE_ ## _f)\n\n/** Variables associated with each port (5.4.7 in 802.1AX documentation). */\nstruct port {\n\t/**\n\t * The operational values of the Actor's state parameters. Bitmask\n\t * of port states.\n\t */\n\tuint8_t actor_state;\n\n\t/** The operational Actor's port parameters */\n\tstruct port_params actor;\n\n\t/**\n\t * The operational value of the Actor's view of the current values of\n\t * the Partner's state parameters. The Actor sets this variable either\n\t * to the value received from the Partner in an LACPDU, or to the value\n\t * of Partner_Admin_Port_State. Bitmask of port states.\n\t */\n\tuint8_t partner_state;\n\n\t/** The operational Partner's port parameters */\n\tstruct port_params partner;\n\n\t/* Additional port parameters not listed in documentation */\n\t/** State machine flags */\n\tuint16_t sm_flags;\n\tenum rte_bond_8023ad_selection selected;\n\n\tuint64_t current_while_timer;\n\tuint64_t periodic_timer;\n\tuint64_t wait_while_timer;\n\tuint64_t tx_machine_timer;\n\tuint64_t tx_marker_timer;\n\t/* Agregator parameters */\n\t/** Used aggregator port ID */\n\tuint16_t aggregator_port_id;\n\n\t/** Memory pool used to allocate rings */\n\tstruct rte_mempool *mbuf_pool;\n\n\t/** Ring of LACP packets from RX burst function */\n\tstruct rte_ring *rx_ring;\n\n\t/** Ring of slow protocol packets (LACP and MARKERS) to TX burst function */\n\tstruct rte_ring *tx_ring;\n\n\t/** Timer which is also used as mutex. If is 0 (not running) RX marker\n\t * packet might be responded. Otherwise shall be dropped. It is zeroed in\n\t * mode 4 callback function after expire. */\n\tvolatile uint64_t rx_marker_timer;\n\n\tuint64_t warning_timer;\n\tvolatile uint16_t warnings_to_show;\n};\n\nstruct mode8023ad_private {\n\tuint64_t fast_periodic_timeout;\n\tuint64_t slow_periodic_timeout;\n\tuint64_t short_timeout;\n\tuint64_t long_timeout;\n\tuint64_t aggregate_wait_timeout;\n\tuint64_t tx_period_timeout;\n\tuint64_t rx_marker_timeout;\n\tuint64_t update_timeout_us;\n};\n\n/**\n * @internal\n * The pool of *port* structures. The size of the pool\n * is configured at compile-time in the file.\n */\nextern struct port mode_8023ad_ports[];\n\n/* Forward declaration */\nstruct bond_dev_private;\n\n/**\n * @internal\n *\n * Get configuration of bonded interface.\n *\n *\n * @param dev Bonded interface\n * @param conf returned configuration\n */\nvoid\nbond_mode_8023ad_conf_get(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_bond_8023ad_conf *conf);\n\n/**\n * @internal\n *\n * Set mode 4 configuration of bonded interface.\n *\n * @pre Bonded interface must be stopped.\n *\n * @param dev Bonded interface\n * @param conf new configuration. If NULL set default configuration.\n */\nvoid\nbond_mode_8023ad_setup(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_bond_8023ad_conf *conf);\n\n/**\n * @internal\n *\n * Enables 802.1AX mode and all active slaves on bonded interface.\n *\n * @param dev Bonded interface\n * @return\n * 0 on success, negative value otherwise.\n */\nint\nbond_mode_8023ad_enable(struct rte_eth_dev *dev);\n\n/**\n * @internal\n *\n * Disables 802.1AX mode of the bonded interface and slaves.\n *\n * @param dev Bonded interface\n * @return\n * 0 on success, negative value otherwise.\n */\nint bond_mode_8023ad_disable(struct rte_eth_dev *dev);\n\n/**\n * @internal\n *\n * Starts 802.3AX state machines management logic.\n * @param dev Bonded interface\n * @return\n * 0 if machines was started, 1 if machines was already running,\n * negative value otherwise.\n */\nint\nbond_mode_8023ad_start(struct rte_eth_dev *dev);\n\n/**\n * @internal\n *\n * Stops 802.3AX state machines management logic.\n * @param dev Bonded interface\n * @return\n * 0 if this call stopped state machines, -ENOENT if alarm was not set.\n */\nvoid\nbond_mode_8023ad_stop(struct rte_eth_dev *dev);\n\n/**\n * @internal\n *\n * Passes given slow packet to state machines management logic.\n * @param internals Bonded device private data.\n * @param slave_id Slave port id.\n * @param slot_pkt Slow packet.\n */\nvoid\nbond_mode_8023ad_handle_slow_pkt(struct bond_dev_private *internals,\n\tuint8_t slave_id, struct rte_mbuf *pkt);\n\n/**\n * @internal\n *\n * Appends given slave used slave\n *\n * @param dev Bonded interface.\n * @param port_id Slave port ID to be added\n *\n * @return\n * 0 on success, negative value otherwise.\n */\nvoid\nbond_mode_8023ad_activate_slave(struct rte_eth_dev *dev, uint8_t port_id);\n\n/**\n * @internal\n *\n * Denitializes and removes given slave from 802.1AX mode.\n *\n * @param dev Bonded interface.\n * @param slave_num Position of slave in active_slaves array\n *\n * @return\n * 0 on success, negative value otherwise.\n */\nint\nbond_mode_8023ad_deactivate_slave(struct rte_eth_dev *dev, uint8_t slave_pos);\n\n/**\n * Updates state when MAC was changed on bonded device or one of its slaves.\n * @param bond_dev Bonded device\n */\nvoid\nbond_mode_8023ad_mac_address_update(struct rte_eth_dev *bond_dev);\n\n#endif /* RTE_ETH_BOND_8023AD_H_ */\n" }, { "path": "drivers/net/bonding/rte_eth_bond_alb.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"rte_eth_bond_private.h\"\n#include \"rte_eth_bond_alb.h\"\n\nstatic inline uint8_t\nsimple_hash(uint8_t *hash_start, int hash_size)\n{\n\tint i;\n\tuint8_t hash;\n\n\thash = 0;\n\tfor (i = 0; i < hash_size; ++i)\n\t\thash ^= hash_start[i];\n\n\treturn hash;\n}\n\nstatic uint8_t\ncalculate_slave(struct bond_dev_private *internals)\n{\n\tuint8_t idx;\n\n\tidx = (internals->mode6.last_slave + 1) % internals->active_slave_count;\n\tinternals->mode6.last_slave = idx;\n\treturn internals->active_slaves[idx];\n}\n\nint\nbond_mode_alb_enable(struct rte_eth_dev *bond_dev)\n{\n\tstruct bond_dev_private *internals = bond_dev->data->dev_private;\n\tstruct client_data *hash_table = internals->mode6.client_table;\n\n\tuint16_t data_size;\n\tchar mem_name[RTE_ETH_NAME_MAX_LEN];\n\tint socket_id = bond_dev->pci_dev->numa_node;\n\n\t/* Fill hash table with initial values */\n\tmemset(hash_table, 0, sizeof(struct client_data) * ALB_HASH_TABLE_SIZE);\n\trte_spinlock_init(&internals->mode6.lock);\n\tinternals->mode6.last_slave = ALB_NULL_INDEX;\n\tinternals->mode6.ntt = 0;\n\n\t/* Initialize memory pool for ARP packets to send */\n\tif (internals->mode6.mempool == NULL) {\n\t\t/*\n\t\t * 256 is size of ETH header, ARP header and nested VLAN headers.\n\t\t * The value is chosen to be cache aligned.\n\t\t */\n\t\tdata_size = 256 + RTE_PKTMBUF_HEADROOM;\n\t\tsnprintf(mem_name, sizeof(mem_name), \"%s_MODE6\", bond_dev->data->name);\n\t\tinternals->mode6.mempool = rte_pktmbuf_pool_create(mem_name,\n\t\t\t512 * RTE_MAX_ETHPORTS,\n\t\t\tRTE_MEMPOOL_CACHE_MAX_SIZE >= 32 ?\n\t\t\t\t32 : RTE_MEMPOOL_CACHE_MAX_SIZE,\n\t\t\t0, data_size, socket_id);\n\n\t\tif (internals->mode6.mempool == NULL) {\n\t\t\tRTE_LOG(ERR, PMD, \"%s: Failed to initialize ALB mempool.\\n\",\n\t\t\t\t\tbond_dev->data->name);\n\t\t\trte_panic(\n\t\t\t\t\t\"Failed to allocate memory pool ('%s')\\n\"\n\t\t\t\t\t\"for bond device '%s'\\n\",\n\t\t\t\t\tmem_name, bond_dev->data->name);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nvoid bond_mode_alb_arp_recv(struct ether_hdr *eth_h, uint16_t offset,\n\t\tstruct bond_dev_private *internals) {\n\tstruct arp_hdr *arp;\n\n\tstruct client_data *hash_table = internals->mode6.client_table;\n\tstruct client_data *client_info;\n\n\tuint8_t hash_index;\n\n\tarp = (struct arp_hdr *) ((char *) (eth_h + 1) + offset);\n\n\t/* ARP Requests are forwarded to the application with no changes */\n\tif (arp->arp_op != rte_cpu_to_be_16(ARP_OP_REPLY))\n\t\treturn;\n\n\t/* From now on, we analyze only ARP Reply packets */\n\thash_index = simple_hash((uint8_t *) &arp->arp_data.arp_sip,\n\t\t\tsizeof(arp->arp_data.arp_sip));\n\tclient_info = &hash_table[hash_index];\n\n\t/*\n\t * We got reply for ARP Request send by the application. We need to\n\t * update client table when received data differ from what is stored\n\t * in ALB table and issue sending update packet to that slave.\n\t */\n\trte_spinlock_lock(&internals->mode6.lock);\n\tif (client_info->in_use == 0 ||\n\t\t\tclient_info->app_ip != arp->arp_data.arp_tip ||\n\t\t\tclient_info->cli_ip != arp->arp_data.arp_sip ||\n\t\t\t!is_same_ether_addr(&client_info->cli_mac, &arp->arp_data.arp_sha) ||\n\t\t\tclient_info->vlan_count != offset / sizeof(struct vlan_hdr) ||\n\t\t\tmemcmp(client_info->vlan, eth_h + 1, offset) != 0\n\t) {\n\t\tclient_info->in_use = 1;\n\t\tclient_info->app_ip = arp->arp_data.arp_tip;\n\t\tclient_info->cli_ip = arp->arp_data.arp_sip;\n\t\tether_addr_copy(&arp->arp_data.arp_sha, &client_info->cli_mac);\n\t\tclient_info->slave_idx = calculate_slave(internals);\n\t\trte_eth_macaddr_get(client_info->slave_idx, &client_info->app_mac);\n\t\tether_addr_copy(&client_info->app_mac, &arp->arp_data.arp_tha);\n\t\tmemcpy(client_info->vlan, eth_h + 1, offset);\n\t\tclient_info->vlan_count = offset / sizeof(struct vlan_hdr);\n\t}\n\tinternals->mode6.ntt = 1;\n\trte_spinlock_unlock(&internals->mode6.lock);\n}\n\nuint8_t\nbond_mode_alb_arp_xmit(struct ether_hdr *eth_h, uint16_t offset,\n\t\tstruct bond_dev_private *internals)\n{\n\tstruct arp_hdr *arp;\n\n\tstruct client_data *hash_table = internals->mode6.client_table;\n\tstruct client_data *client_info;\n\n\tuint8_t hash_index;\n\n\tstruct ether_addr bonding_mac;\n\n\tarp = (struct arp_hdr *)((char *)(eth_h + 1) + offset);\n\n\t/*\n\t * Traffic with src MAC other than bonding should be sent on\n\t * current primary port.\n\t */\n\trte_eth_macaddr_get(internals->port_id, &bonding_mac);\n\tif (!is_same_ether_addr(&bonding_mac, &arp->arp_data.arp_sha)) {\n\t\trte_eth_macaddr_get(internals->current_primary_port,\n\t\t\t\t&arp->arp_data.arp_sha);\n\t\treturn internals->current_primary_port;\n\t}\n\n\thash_index = simple_hash((uint8_t *)&arp->arp_data.arp_tip,\n\t\t\tsizeof(uint32_t));\n\tclient_info = &hash_table[hash_index];\n\n\trte_spinlock_lock(&internals->mode6.lock);\n\tif (arp->arp_op == rte_cpu_to_be_16(ARP_OP_REPLY)) {\n\t\tif (client_info->in_use) {\n\t\t\tif (client_info->app_ip == arp->arp_data.arp_sip &&\n\t\t\t\tclient_info->cli_ip == arp->arp_data.arp_tip) {\n\t\t\t\t/* Entry is already assigned to this client */\n\t\t\t\tif (!is_broadcast_ether_addr(&arp->arp_data.arp_tha)) {\n\t\t\t\t\tether_addr_copy(&arp->arp_data.arp_tha,\n\t\t\t\t\t\t\t&client_info->cli_mac);\n\t\t\t\t}\n\t\t\t\trte_eth_macaddr_get(client_info->slave_idx,\n\t\t\t\t\t\t&client_info->app_mac);\n\t\t\t\tether_addr_copy(&client_info->app_mac, &arp->arp_data.arp_sha);\n\t\t\t\tmemcpy(client_info->vlan, eth_h + 1, offset);\n\t\t\t\tclient_info->vlan_count = offset / sizeof(struct vlan_hdr);\n\t\t\t\trte_spinlock_unlock(&internals->mode6.lock);\n\t\t\t\treturn client_info->slave_idx;\n\t\t\t}\n\t\t}\n\n\t\t/* Assign new slave to this client and update src mac in ARP */\n\t\tclient_info->in_use = 1;\n\t\tclient_info->ntt = 0;\n\t\tclient_info->app_ip = arp->arp_data.arp_sip;\n\t\tether_addr_copy(&arp->arp_data.arp_tha, &client_info->cli_mac);\n\t\tclient_info->cli_ip = arp->arp_data.arp_tip;\n\t\tclient_info->slave_idx = calculate_slave(internals);\n\t\trte_eth_macaddr_get(client_info->slave_idx, &client_info->app_mac);\n\t\tether_addr_copy(&client_info->app_mac, &arp->arp_data.arp_sha);\n\t\tmemcpy(client_info->vlan, eth_h + 1, offset);\n\t\tclient_info->vlan_count = offset / sizeof(struct vlan_hdr);\n\t\trte_spinlock_unlock(&internals->mode6.lock);\n\t\treturn client_info->slave_idx;\n\t}\n\n\t/* If packet is not ARP Reply, send it on current primary port. */\n\trte_spinlock_unlock(&internals->mode6.lock);\n\trte_eth_macaddr_get(internals->current_primary_port,\n\t\t\t&arp->arp_data.arp_sha);\n\treturn internals->current_primary_port;\n}\n\nuint8_t\nbond_mode_alb_arp_upd(struct client_data *client_info,\n\t\tstruct rte_mbuf *pkt, struct bond_dev_private *internals)\n{\n\tstruct ether_hdr *eth_h;\n\tstruct arp_hdr *arp_h;\n\tuint8_t slave_idx;\n\n\trte_spinlock_lock(&internals->mode6.lock);\n\teth_h = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\n\tether_addr_copy(&client_info->app_mac, ð_h->s_addr);\n\tether_addr_copy(&client_info->cli_mac, ð_h->d_addr);\n\tif (client_info->vlan_count > 0)\n\t\teth_h->ether_type = rte_cpu_to_be_16(ETHER_TYPE_VLAN);\n\telse\n\t\teth_h->ether_type = rte_cpu_to_be_16(ETHER_TYPE_ARP);\n\n\tarp_h = (struct arp_hdr *)((char *)eth_h + sizeof(struct ether_hdr)\n\t\t\t+ client_info->vlan_count * sizeof(struct vlan_hdr));\n\n\tmemcpy(eth_h + 1, client_info->vlan,\n\t\t\tclient_info->vlan_count * sizeof(struct vlan_hdr));\n\n\tether_addr_copy(&client_info->app_mac, &arp_h->arp_data.arp_sha);\n\tarp_h->arp_data.arp_sip = client_info->app_ip;\n\tether_addr_copy(&client_info->cli_mac, &arp_h->arp_data.arp_tha);\n\tarp_h->arp_data.arp_tip = client_info->cli_ip;\n\n\tarp_h->arp_hrd = rte_cpu_to_be_16(ARP_HRD_ETHER);\n\tarp_h->arp_pro = rte_cpu_to_be_16(ETHER_TYPE_IPv4);\n\tarp_h->arp_hln = ETHER_ADDR_LEN;\n\tarp_h->arp_pln = sizeof(uint32_t);\n\tarp_h->arp_op = rte_cpu_to_be_16(ARP_OP_REPLY);\n\n\tslave_idx = client_info->slave_idx;\n\trte_spinlock_unlock(&internals->mode6.lock);\n\n\treturn slave_idx;\n}\n\nvoid\nbond_mode_alb_client_list_upd(struct rte_eth_dev *bond_dev)\n{\n\tstruct bond_dev_private *internals = bond_dev->data->dev_private;\n\tstruct client_data *client_info;\n\n\tint i;\n\n\t/* If active slave count is 0, it's pointless to refresh alb table */\n\tif (internals->active_slave_count <= 0)\n\t\treturn;\n\n\trte_spinlock_lock(&internals->mode6.lock);\n\tinternals->mode6.last_slave = ALB_NULL_INDEX;\n\n\tfor (i = 0; i < ALB_HASH_TABLE_SIZE; i++) {\n\t\tclient_info = &internals->mode6.client_table[i];\n\t\tif (client_info->in_use) {\n\t\t\tclient_info->slave_idx = calculate_slave(internals);\n\t\t\trte_eth_macaddr_get(client_info->slave_idx, &client_info->app_mac);\n\t\t\tinternals->mode6.ntt = 1;\n\t\t}\n\t}\n\trte_spinlock_unlock(&internals->mode6.lock);\n}\n" }, { "path": "drivers/net/bonding/rte_eth_bond_alb.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef RTE_ETH_BOND_ALB_H_\n#define RTE_ETH_BOND_ALB_H_\n\n#include \n#include \n\n#define ALB_HASH_TABLE_SIZE\t256\n#define ALB_NULL_INDEX\t\t0xFFFFFFFF\n\nstruct client_data {\n\t/** ARP data of single client */\n\tstruct ether_addr app_mac;\n\t/**< MAC address of application running DPDK */\n\tuint32_t app_ip;\n\t/**< IP address of application running DPDK */\n\tstruct ether_addr cli_mac;\n\t/**< Client MAC address */\n\tuint32_t cli_ip;\n\t/**< Client IP address */\n\n\tuint8_t slave_idx;\n\t/**< Index of slave on which we connect with that client */\n\tuint8_t in_use;\n\t/**< Flag indicating if entry in client table is currently used */\n\tuint8_t ntt;\n\t/**< Flag indicating if we need to send update to this client on next tx */\n\n\tstruct vlan_hdr vlan[2];\n\t/**< Content of vlan headers */\n\tuint8_t vlan_count;\n\t/**< Number of nested vlan headers */\n};\n\nstruct mode_alb_private {\n\tstruct client_data client_table[ALB_HASH_TABLE_SIZE];\n\t/**< Hash table storing ARP data of every client connected */\n\tstruct rte_mempool *mempool;\n\t/**< Mempool for creating ARP update packets */\n\tuint8_t ntt;\n\t/**< Flag indicating if we need to send update to any client on next tx */\n\tuint32_t last_slave;\n\t/**< Index of last used slave in client table */\n\trte_spinlock_t lock;\n};\n\n/**\n * ALB mode initialization.\n *\n * @param bond_dev\t\tPointer to bonding device.\n *\n * @return\n * Error code - 0 on success.\n */\nint\nbond_mode_alb_enable(struct rte_eth_dev *bond_dev);\n\n/**\n * Function handles ARP packet reception. If received ARP request, it is\n * forwarded to application without changes. If it is ARP reply, client table\n * is updated.\n *\n * @param eth_h\t\t\tETH header of received packet.\n * @param offset\t\tVlan header offset.\n * @param internals\t\tBonding data.\n */\nvoid\nbond_mode_alb_arp_recv(struct ether_hdr *eth_h, uint16_t offset,\n\t\tstruct bond_dev_private *internals);\n\n/**\n * Function handles ARP packet transmission. It also decides on which slave\n * send that packet. If packet is ARP Request, it is send on primary slave.\n * If it is ARP Reply, it is send on slave stored in client table for that\n * connection. On Reply function also updates data in client table.\n *\n * @param eth_h\t\t\tETH header of transmitted packet.\n * @param offset\t\tVlan header offset.\n * @param internals\t\tBonding data.\n *\n * @return\n * Index of slave on which packet should be sent.\n */\nuint8_t\nbond_mode_alb_arp_xmit(struct ether_hdr *eth_h, uint16_t offset,\n\t\tstruct bond_dev_private *internals);\n\n/**\n * Function fills packet with ARP data from client_info.\n *\n * @param client_info\tData of client to which packet is sent.\n * @param pkt\t\t\tPointer to packet which is sent.\n * @param internals\t\tBonding data.\n *\n * @return\n * Index of slawe on which packet should be sent.\n */\nuint8_t\nbond_mode_alb_arp_upd(struct client_data *client_info,\n\t\tstruct rte_mbuf *pkt, struct bond_dev_private *internals);\n\n/**\n * Function updates slave indexes of active connections.\n *\n * @param bond_dev\t\tPointer to bonded device struct.\n */\nvoid\nbond_mode_alb_client_list_upd(struct rte_eth_dev *bond_dev);\n\n#endif /* RTE_ETH_BOND_ALB_H_ */\n" }, { "path": "drivers/net/bonding/rte_eth_bond_api.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n\n#include \"rte_eth_bond.h\"\n#include \"rte_eth_bond_private.h\"\n#include \"rte_eth_bond_8023ad_private.h\"\n\n#define DEFAULT_POLLING_INTERVAL_10_MS (10)\n\nint\nvalid_bonded_ethdev(const struct rte_eth_dev *eth_dev)\n{\n\t/* Check valid pointer */\n\tif (eth_dev->driver->pci_drv.name == NULL)\n\t\treturn -1;\n\n\t/* return 0 if driver name matches */\n\treturn eth_dev->driver->pci_drv.name != pmd_bond_driver_name;\n}\n\nint\nvalid_bonded_port_id(uint8_t port_id)\n{\n\tif (!rte_eth_dev_is_valid_port(port_id))\n\t\treturn -1;\n\n\treturn valid_bonded_ethdev(&rte_eth_devices[port_id]);\n}\n\nint\nvalid_slave_port_id(uint8_t port_id)\n{\n\t/* Verify that port id's are valid */\n\tif (!rte_eth_dev_is_valid_port(port_id))\n\t\treturn -1;\n\n\t/* Verify that port_id refers to a non bonded port */\n\tif (!valid_bonded_ethdev(&rte_eth_devices[port_id]))\n\t\treturn -1;\n\n\treturn 0;\n}\n\nvoid\nactivate_slave(struct rte_eth_dev *eth_dev, uint8_t port_id)\n{\n\tstruct bond_dev_private *internals = eth_dev->data->dev_private;\n\tuint8_t active_count = internals->active_slave_count;\n\n\tif (internals->mode == BONDING_MODE_8023AD)\n\t\tbond_mode_8023ad_activate_slave(eth_dev, port_id);\n\n\tif (internals->mode == BONDING_MODE_TLB\n\t\t\t|| internals->mode == BONDING_MODE_ALB) {\n\n\t\tinternals->tlb_slaves_order[active_count] = port_id;\n\t}\n\n\tRTE_VERIFY(internals->active_slave_count <\n\t\t\t(RTE_DIM(internals->active_slaves) - 1));\n\n\tinternals->active_slaves[internals->active_slave_count] = port_id;\n\tinternals->active_slave_count++;\n\n\tif (internals->mode == BONDING_MODE_TLB)\n\t\tbond_tlb_activate_slave(internals);\n\tif (internals->mode == BONDING_MODE_ALB)\n\t\tbond_mode_alb_client_list_upd(eth_dev);\n}\n\nvoid\ndeactivate_slave(struct rte_eth_dev *eth_dev, uint8_t port_id)\n{\n\tuint8_t slave_pos;\n\tstruct bond_dev_private *internals = eth_dev->data->dev_private;\n\tuint8_t active_count = internals->active_slave_count;\n\n\tif (internals->mode == BONDING_MODE_8023AD) {\n\t\tbond_mode_8023ad_stop(eth_dev);\n\t\tbond_mode_8023ad_deactivate_slave(eth_dev, port_id);\n\t} else if (internals->mode == BONDING_MODE_TLB\n\t\t\t|| internals->mode == BONDING_MODE_ALB)\n\t\tbond_tlb_disable(internals);\n\n\tslave_pos = find_slave_by_id(internals->active_slaves, active_count,\n\t\t\tport_id);\n\n\t/* If slave was not at the end of the list\n\t * shift active slaves up active array list */\n\tif (slave_pos < active_count) {\n\t\tactive_count--;\n\t\tmemmove(internals->active_slaves + slave_pos,\n\t\t\t\tinternals->active_slaves + slave_pos + 1,\n\t\t\t\t(active_count - slave_pos) *\n\t\t\t\t\tsizeof(internals->active_slaves[0]));\n\t}\n\n\tRTE_VERIFY(active_count < RTE_DIM(internals->active_slaves));\n\tinternals->active_slave_count = active_count;\n\n\tif (eth_dev->data->dev_started) {\n\t\tif (internals->mode == BONDING_MODE_8023AD) {\n\t\t\tbond_mode_8023ad_start(eth_dev);\n\t\t} else if (internals->mode == BONDING_MODE_TLB) {\n\t\t\tbond_tlb_enable(internals);\n\t\t} else if (internals->mode == BONDING_MODE_ALB) {\n\t\t\tbond_tlb_enable(internals);\n\t\t\tbond_mode_alb_client_list_upd(eth_dev);\n\t\t}\n\t}\n}\n\nuint8_t\nnumber_of_sockets(void)\n{\n\tint sockets = 0;\n\tint i;\n\tconst struct rte_memseg *ms = rte_eal_get_physmem_layout();\n\n\tfor (i = 0; ((i < RTE_MAX_MEMSEG) && (ms[i].addr != NULL)); i++) {\n\t\tif (sockets < ms[i].socket_id)\n\t\t\tsockets = ms[i].socket_id;\n\t}\n\n\t/* Number of sockets = maximum socket_id + 1 */\n\treturn ++sockets;\n}\n\nconst char pmd_bond_driver_name[] = \"rte_bond_pmd\";\n\nstatic struct rte_pci_id pci_id_table = {\n\t.device_id = PCI_ANY_ID,\n\t.subsystem_device_id = PCI_ANY_ID,\n\t.vendor_id = PCI_ANY_ID,\n\t.subsystem_vendor_id = PCI_ANY_ID,\n};\n\nstatic struct eth_driver rte_bond_pmd = {\n\t.pci_drv = {\n\t\t.name = pmd_bond_driver_name,\n\t\t.drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_DETACHABLE,\n\t\t.id_table = &pci_id_table,\n\t},\n};\n\nint\nrte_eth_bond_create(const char *name, uint8_t mode, uint8_t socket_id)\n{\n\tstruct rte_pci_device *pci_dev = NULL;\n\tstruct bond_dev_private *internals = NULL;\n\tstruct rte_eth_dev *eth_dev = NULL;\n\tstruct rte_pci_driver *pci_drv = NULL;\n\n\t/* now do all data allocation - for eth_dev structure, dummy pci driver\n\t * and internal (private) data\n\t */\n\n\tif (name == NULL) {\n\t\tRTE_BOND_LOG(ERR, \"Invalid name specified\");\n\t\tgoto err;\n\t}\n\n\tif (socket_id >= number_of_sockets()) {\n\t\tRTE_BOND_LOG(ERR,\n\t\t\t\t\"Invalid socket id specified to create bonded device on.\");\n\t\tgoto err;\n\t}\n\n\tpci_dev = rte_zmalloc_socket(name, sizeof(*pci_dev), 0, socket_id);\n\tif (pci_dev == NULL) {\n\t\tRTE_BOND_LOG(ERR, \"Unable to malloc pci dev on socket\");\n\t\tgoto err;\n\t}\n\n\tpci_drv = &rte_bond_pmd.pci_drv;\n\n\tinternals = rte_zmalloc_socket(name, sizeof(*internals), 0, socket_id);\n\tif (internals == NULL) {\n\t\tRTE_BOND_LOG(ERR, \"Unable to malloc internals on socket\");\n\t\tgoto err;\n\t}\n\n\t/* reserve an ethdev entry */\n\teth_dev = rte_eth_dev_allocate(name, RTE_ETH_DEV_VIRTUAL);\n\tif (eth_dev == NULL) {\n\t\tRTE_BOND_LOG(ERR, \"Unable to allocate rte_eth_dev\");\n\t\tgoto err;\n\t}\n\n\tpci_dev->numa_node = socket_id;\n\tpci_drv->name = pmd_bond_driver_name;\n\tpci_dev->driver = pci_drv;\n\n\teth_dev->driver = &rte_bond_pmd;\n\teth_dev->data->dev_private = internals;\n\teth_dev->data->nb_rx_queues = (uint16_t)1;\n\teth_dev->data->nb_tx_queues = (uint16_t)1;\n\n\tTAILQ_INIT(&(eth_dev->link_intr_cbs));\n\n\teth_dev->data->dev_link.link_status = 0;\n\n\teth_dev->data->mac_addrs = rte_zmalloc_socket(name, ETHER_ADDR_LEN, 0,\n\t\t\tsocket_id);\n\tif (eth_dev->data->mac_addrs == NULL) {\n\t\tRTE_BOND_LOG(ERR, \"Unable to malloc mac_addrs\");\n\t\tgoto err;\n\t}\n\n\teth_dev->data->dev_started = 0;\n\teth_dev->data->promiscuous = 0;\n\teth_dev->data->scattered_rx = 0;\n\teth_dev->data->all_multicast = 0;\n\n\teth_dev->dev_ops = &default_dev_ops;\n\teth_dev->pci_dev = pci_dev;\n\n\trte_spinlock_init(&internals->lock);\n\n\tinternals->port_id = eth_dev->data->port_id;\n\tinternals->mode = BONDING_MODE_INVALID;\n\tinternals->current_primary_port = 0;\n\tinternals->balance_xmit_policy = BALANCE_XMIT_POLICY_LAYER2;\n\tinternals->xmit_hash = xmit_l2_hash;\n\tinternals->user_defined_mac = 0;\n\tinternals->link_props_set = 0;\n\n\tinternals->link_status_polling_enabled = 0;\n\n\tinternals->link_status_polling_interval_ms = DEFAULT_POLLING_INTERVAL_10_MS;\n\tinternals->link_down_delay_ms = 0;\n\tinternals->link_up_delay_ms = 0;\n\n\tinternals->slave_count = 0;\n\tinternals->active_slave_count = 0;\n\tinternals->rx_offload_capa = 0;\n\tinternals->tx_offload_capa = 0;\n\n\tmemset(internals->active_slaves, 0, sizeof(internals->active_slaves));\n\tmemset(internals->slaves, 0, sizeof(internals->slaves));\n\n\t/* Set mode 4 default configuration */\n\tbond_mode_8023ad_setup(eth_dev, NULL);\n\tif (bond_ethdev_mode_set(eth_dev, mode)) {\n\t\tRTE_BOND_LOG(ERR, \"Failed to set bonded device %d mode too %d\",\n\t\t\t\t eth_dev->data->port_id, mode);\n\t\tgoto err;\n\t}\n\n\treturn eth_dev->data->port_id;\n\nerr:\n\trte_free(pci_dev);\n\trte_free(internals);\n\tif (eth_dev != NULL) {\n\t\trte_free(eth_dev->data->mac_addrs);\n\t\trte_eth_dev_release_port(eth_dev);\n\t}\n\treturn -1;\n}\n\nint\nrte_eth_bond_free(const char *name)\n{\n\tstruct rte_eth_dev *eth_dev = NULL;\n\n\t/* now free all data allocation - for eth_dev structure,\n\t * dummy pci driver and internal (private) data\n\t */\n\n\t/* find an ethdev entry */\n\teth_dev = rte_eth_dev_allocated(name);\n\tif (eth_dev == NULL)\n\t\treturn -ENODEV;\n\n\tif (eth_dev->data->dev_started == 1) {\n\t\tbond_ethdev_stop(eth_dev);\n\t\tbond_ethdev_close(eth_dev);\n\t}\n\n\teth_dev->dev_ops = NULL;\n\teth_dev->rx_pkt_burst = NULL;\n\teth_dev->tx_pkt_burst = NULL;\n\n\trte_free(eth_dev->pci_dev);\n\trte_free(eth_dev->data->dev_private);\n\trte_free(eth_dev->data->mac_addrs);\n\n\trte_eth_dev_release_port(eth_dev);\n\n\treturn 0;\n}\n\nstatic int\n__eth_bond_slave_add_lock_free(uint8_t bonded_port_id, uint8_t slave_port_id)\n{\n\tstruct rte_eth_dev *bonded_eth_dev, *slave_eth_dev;\n\tstruct bond_dev_private *internals;\n\tstruct bond_dev_private *temp_internals;\n\tstruct rte_eth_link link_props;\n\tstruct rte_eth_dev_info dev_info;\n\n\tint i, j;\n\n\tif (valid_slave_port_id(slave_port_id) != 0)\n\t\treturn -1;\n\n\tbonded_eth_dev = &rte_eth_devices[bonded_port_id];\n\tinternals = bonded_eth_dev->data->dev_private;\n\n\t/* Verify that new slave device is not already a slave of another\n\t * bonded device */\n\tfor (i = rte_eth_dev_count()-1; i >= 0; i--) {\n\t\tif (valid_bonded_ethdev(&rte_eth_devices[i]) == 0) {\n\t\t\ttemp_internals = rte_eth_devices[i].data->dev_private;\n\n\t\t\tfor (j = 0; j < temp_internals->slave_count; j++) {\n\t\t\t\t/* Device already a slave of a bonded device */\n\t\t\t\tif (temp_internals->slaves[j].port_id == slave_port_id) {\n\t\t\t\t\tRTE_BOND_LOG(ERR, \"Slave port %d is already a slave\",\n\t\t\t\t\t\t\tslave_port_id);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tslave_eth_dev = &rte_eth_devices[slave_port_id];\n\n\t/* Add slave details to bonded device */\n\tslave_add(internals, slave_eth_dev);\n\n\trte_eth_dev_info_get(slave_port_id, &dev_info);\n\n\tif (internals->slave_count < 1) {\n\t\t/* if MAC is not user defined then use MAC of first slave add to\n\t\t * bonded device */\n\t\tif (!internals->user_defined_mac)\n\t\t\tmac_address_set(bonded_eth_dev, slave_eth_dev->data->mac_addrs);\n\n\t\t/* Inherit eth dev link properties from first slave */\n\t\tlink_properties_set(bonded_eth_dev,\n\t\t\t\t&(slave_eth_dev->data->dev_link));\n\n\t\t/* Make primary slave */\n\t\tinternals->primary_port = slave_port_id;\n\n\t\t/* Take the first dev's offload capabilities */\n\t\tinternals->rx_offload_capa = dev_info.rx_offload_capa;\n\t\tinternals->tx_offload_capa = dev_info.tx_offload_capa;\n\n\t} else {\n\t\t/* Check slave link properties are supported if props are set,\n\t\t * all slaves must be the same */\n\t\tif (internals->link_props_set) {\n\t\t\tif (link_properties_valid(&(bonded_eth_dev->data->dev_link),\n\t\t\t\t\t\t\t\t\t &(slave_eth_dev->data->dev_link))) {\n\t\t\t\tRTE_BOND_LOG(ERR,\n\t\t\t\t\t\t\"Slave port %d link speed/duplex not supported\",\n\t\t\t\t\t\tslave_port_id);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t} else {\n\t\t\tlink_properties_set(bonded_eth_dev,\n\t\t\t\t\t&(slave_eth_dev->data->dev_link));\n\t\t}\n\t\tinternals->rx_offload_capa &= dev_info.rx_offload_capa;\n\t\tinternals->tx_offload_capa &= dev_info.tx_offload_capa;\n\t}\n\n\tinternals->slave_count++;\n\n\t/* Update all slave devices MACs*/\n\tmac_address_slaves_update(bonded_eth_dev);\n\n\tif (bonded_eth_dev->data->dev_started) {\n\t\tif (slave_configure(bonded_eth_dev, slave_eth_dev) != 0) {\n\t\t\tRTE_BOND_LOG(ERR, \"rte_bond_slaves_configure: port=%d\",\n\t\t\t\t\tslave_port_id);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* Register link status change callback with bonded device pointer as\n\t * argument*/\n\trte_eth_dev_callback_register(slave_port_id, RTE_ETH_EVENT_INTR_LSC,\n\t\t\tbond_ethdev_lsc_event_callback, &bonded_eth_dev->data->port_id);\n\n\t/* If bonded device is started then we can add the slave to our active\n\t * slave array */\n\tif (bonded_eth_dev->data->dev_started) {\n\t\trte_eth_link_get_nowait(slave_port_id, &link_props);\n\n\t\t if (link_props.link_status == 1)\n\t\t\tactivate_slave(bonded_eth_dev, slave_port_id);\n\t}\n\treturn 0;\n\n}\n\nint\nrte_eth_bond_slave_add(uint8_t bonded_port_id, uint8_t slave_port_id)\n{\n\tstruct rte_eth_dev *bonded_eth_dev;\n\tstruct bond_dev_private *internals;\n\n\tint retval;\n\n\t/* Verify that port id's are valid bonded and slave ports */\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tbonded_eth_dev = &rte_eth_devices[bonded_port_id];\n\tinternals = bonded_eth_dev->data->dev_private;\n\n\trte_spinlock_lock(&internals->lock);\n\n\tretval = __eth_bond_slave_add_lock_free(bonded_port_id, slave_port_id);\n\n\trte_spinlock_unlock(&internals->lock);\n\n\treturn retval;\n}\n\nstatic int\n__eth_bond_slave_remove_lock_free(uint8_t bonded_port_id, uint8_t slave_port_id)\n{\n\tstruct rte_eth_dev *bonded_eth_dev;\n\tstruct bond_dev_private *internals;\n\n\tint i, slave_idx;\n\n\tif (valid_slave_port_id(slave_port_id) != 0)\n\t\treturn -1;\n\n\tbonded_eth_dev = &rte_eth_devices[bonded_port_id];\n\tinternals = bonded_eth_dev->data->dev_private;\n\n\t/* first remove from active slave list */\n\tslave_idx = find_slave_by_id(internals->active_slaves,\n\t\tinternals->active_slave_count, slave_port_id);\n\n\tif (slave_idx < internals->active_slave_count)\n\t\tdeactivate_slave(bonded_eth_dev, slave_port_id);\n\n\tslave_idx = -1;\n\t/* now find in slave list */\n\tfor (i = 0; i < internals->slave_count; i++)\n\t\tif (internals->slaves[i].port_id == slave_port_id) {\n\t\t\tslave_idx = i;\n\t\t\tbreak;\n\t\t}\n\n\tif (slave_idx < 0) {\n\t\tRTE_BOND_LOG(ERR, \"Couldn't find slave in port list, slave count %d\",\n\t\t\t\tinternals->slave_count);\n\t\treturn -1;\n\t}\n\n\t/* Un-register link status change callback with bonded device pointer as\n\t * argument*/\n\trte_eth_dev_callback_unregister(slave_port_id, RTE_ETH_EVENT_INTR_LSC,\n\t\t\tbond_ethdev_lsc_event_callback,\n\t\t\t&rte_eth_devices[bonded_port_id].data->port_id);\n\n\t/* Restore original MAC address of slave device */\n\tmac_address_set(&rte_eth_devices[slave_port_id],\n\t\t\t&(internals->slaves[slave_idx].persisted_mac_addr));\n\n\tslave_remove(internals, &rte_eth_devices[slave_port_id]);\n\n\t/* first slave in the active list will be the primary by default,\n\t * otherwise use first device in list */\n\tif (internals->current_primary_port == slave_port_id) {\n\t\tif (internals->active_slave_count > 0)\n\t\t\tinternals->current_primary_port = internals->active_slaves[0];\n\t\telse if (internals->slave_count > 0)\n\t\t\tinternals->current_primary_port = internals->slaves[0].port_id;\n\t\telse\n\t\t\tinternals->primary_port = 0;\n\t}\n\n\tif (internals->active_slave_count < 1) {\n\t\t/* reset device link properties as no slaves are active */\n\t\tlink_properties_reset(&rte_eth_devices[bonded_port_id]);\n\n\t\t/* if no slaves are any longer attached to bonded device and MAC is not\n\t\t * user defined then clear MAC of bonded device as it will be reset\n\t\t * when a new slave is added */\n\t\tif (internals->slave_count < 1 && !internals->user_defined_mac)\n\t\t\tmemset(rte_eth_devices[bonded_port_id].data->mac_addrs, 0,\n\t\t\t\t\tsizeof(*(rte_eth_devices[bonded_port_id].data->mac_addrs)));\n\t}\n\tif (internals->slave_count == 0) {\n\t\tinternals->rx_offload_capa = 0;\n\t\tinternals->tx_offload_capa = 0;\n\t}\n\treturn 0;\n}\n\nint\nrte_eth_bond_slave_remove(uint8_t bonded_port_id, uint8_t slave_port_id)\n{\n\tstruct rte_eth_dev *bonded_eth_dev;\n\tstruct bond_dev_private *internals;\n\tint retval;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tbonded_eth_dev = &rte_eth_devices[bonded_port_id];\n\tinternals = bonded_eth_dev->data->dev_private;\n\n\trte_spinlock_lock(&internals->lock);\n\n\tretval = __eth_bond_slave_remove_lock_free(bonded_port_id, slave_port_id);\n\n\trte_spinlock_unlock(&internals->lock);\n\n\treturn retval;\n}\n\nint\nrte_eth_bond_mode_set(uint8_t bonded_port_id, uint8_t mode)\n{\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\treturn bond_ethdev_mode_set(&rte_eth_devices[bonded_port_id], mode);\n}\n\nint\nrte_eth_bond_mode_get(uint8_t bonded_port_id)\n{\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\n\treturn internals->mode;\n}\n\nint\nrte_eth_bond_primary_set(uint8_t bonded_port_id, uint8_t slave_port_id)\n{\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tif (valid_slave_port_id(slave_port_id) != 0)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\n\tinternals->user_defined_primary_port = 1;\n\tinternals->primary_port = slave_port_id;\n\n\tbond_ethdev_primary_set(internals, slave_port_id);\n\n\treturn 0;\n}\n\nint\nrte_eth_bond_primary_get(uint8_t bonded_port_id)\n{\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\n\tif (internals->slave_count < 1)\n\t\treturn -1;\n\n\treturn internals->current_primary_port;\n}\n\nint\nrte_eth_bond_slaves_get(uint8_t bonded_port_id, uint8_t slaves[], uint8_t len)\n{\n\tstruct bond_dev_private *internals;\n\tuint8_t i;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tif (slaves == NULL)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\n\tif (internals->slave_count > len)\n\t\treturn -1;\n\n\tfor (i = 0; i < internals->slave_count; i++)\n\t\tslaves[i] = internals->slaves[i].port_id;\n\n\treturn internals->slave_count;\n}\n\nint\nrte_eth_bond_active_slaves_get(uint8_t bonded_port_id, uint8_t slaves[],\n\t\tuint8_t len)\n{\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tif (slaves == NULL)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\n\tif (internals->active_slave_count > len)\n\t\treturn -1;\n\n\tmemcpy(slaves, internals->active_slaves, internals->active_slave_count);\n\n\treturn internals->active_slave_count;\n}\n\nint\nrte_eth_bond_mac_address_set(uint8_t bonded_port_id,\n\t\tstruct ether_addr *mac_addr)\n{\n\tstruct rte_eth_dev *bonded_eth_dev;\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tbonded_eth_dev = &rte_eth_devices[bonded_port_id];\n\tinternals = bonded_eth_dev->data->dev_private;\n\n\t/* Set MAC Address of Bonded Device */\n\tif (mac_address_set(bonded_eth_dev, mac_addr))\n\t\treturn -1;\n\n\tinternals->user_defined_mac = 1;\n\n\t/* Update all slave devices MACs*/\n\tif (internals->slave_count > 0)\n\t\treturn mac_address_slaves_update(bonded_eth_dev);\n\n\treturn 0;\n}\n\nint\nrte_eth_bond_mac_address_reset(uint8_t bonded_port_id)\n{\n\tstruct rte_eth_dev *bonded_eth_dev;\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tbonded_eth_dev = &rte_eth_devices[bonded_port_id];\n\tinternals = bonded_eth_dev->data->dev_private;\n\n\tinternals->user_defined_mac = 0;\n\n\tif (internals->slave_count > 0) {\n\t\t/* Set MAC Address of Bonded Device */\n\t\tif (mac_address_set(bonded_eth_dev,\n\t\t\t\t&internals->slaves[internals->primary_port].persisted_mac_addr)\n\t\t\t\t!= 0) {\n\t\t\tRTE_BOND_LOG(ERR, \"Failed to set MAC address on bonded device\");\n\t\t\treturn -1;\n\t\t}\n\t\t/* Update all slave devices MAC addresses */\n\t\treturn mac_address_slaves_update(bonded_eth_dev);\n\t}\n\t/* No need to update anything as no slaves present */\n\treturn 0;\n}\n\nint\nrte_eth_bond_xmit_policy_set(uint8_t bonded_port_id, uint8_t policy)\n{\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\n\tswitch (policy) {\n\tcase BALANCE_XMIT_POLICY_LAYER2:\n\t\tinternals->balance_xmit_policy = policy;\n\t\tinternals->xmit_hash = xmit_l2_hash;\n\t\tbreak;\n\tcase BALANCE_XMIT_POLICY_LAYER23:\n\t\tinternals->balance_xmit_policy = policy;\n\t\tinternals->xmit_hash = xmit_l23_hash;\n\t\tbreak;\n\tcase BALANCE_XMIT_POLICY_LAYER34:\n\t\tinternals->balance_xmit_policy = policy;\n\t\tinternals->xmit_hash = xmit_l34_hash;\n\t\tbreak;\n\n\tdefault:\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nint\nrte_eth_bond_xmit_policy_get(uint8_t bonded_port_id)\n{\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\n\treturn internals->balance_xmit_policy;\n}\n\nint\nrte_eth_bond_link_monitoring_set(uint8_t bonded_port_id, uint32_t internal_ms)\n{\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\tinternals->link_status_polling_interval_ms = internal_ms;\n\n\treturn 0;\n}\n\nint\nrte_eth_bond_link_monitoring_get(uint8_t bonded_port_id)\n{\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\n\treturn internals->link_status_polling_interval_ms;\n}\n\nint\nrte_eth_bond_link_down_prop_delay_set(uint8_t bonded_port_id, uint32_t delay_ms)\n\n{\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\tinternals->link_down_delay_ms = delay_ms;\n\n\treturn 0;\n}\n\nint\nrte_eth_bond_link_down_prop_delay_get(uint8_t bonded_port_id)\n{\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\n\treturn internals->link_down_delay_ms;\n}\n\nint\nrte_eth_bond_link_up_prop_delay_set(uint8_t bonded_port_id, uint32_t delay_ms)\n\n{\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\tinternals->link_up_delay_ms = delay_ms;\n\n\treturn 0;\n}\n\nint\nrte_eth_bond_link_up_prop_delay_get(uint8_t bonded_port_id)\n{\n\tstruct bond_dev_private *internals;\n\n\tif (valid_bonded_port_id(bonded_port_id) != 0)\n\t\treturn -1;\n\n\tinternals = rte_eth_devices[bonded_port_id].data->dev_private;\n\n\treturn internals->link_up_delay_ms;\n}\n" }, { "path": "drivers/net/bonding/rte_eth_bond_args.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n\n#include \"rte_eth_bond.h\"\n#include \"rte_eth_bond_private.h\"\n\nconst char *pmd_bond_init_valid_arguments[] = {\n\tPMD_BOND_SLAVE_PORT_KVARG,\n\tPMD_BOND_PRIMARY_SLAVE_KVARG,\n\tPMD_BOND_MODE_KVARG,\n\tPMD_BOND_XMIT_POLICY_KVARG,\n\tPMD_BOND_SOCKET_ID_KVARG,\n\tPMD_BOND_MAC_ADDR_KVARG,\n\n\tNULL\n};\n\nstatic inline int\nfind_port_id_by_pci_addr(const struct rte_pci_addr *pci_addr)\n{\n\tstruct rte_pci_addr *eth_pci_addr;\n\tunsigned i;\n\n\tfor (i = 0; i < rte_eth_dev_count(); i++) {\n\n\t\tif (rte_eth_devices[i].pci_dev == NULL)\n\t\t\tcontinue;\n\n\t\teth_pci_addr = &(rte_eth_devices[i].pci_dev->addr);\n\n\t\tif (pci_addr->bus == eth_pci_addr->bus &&\n\t\t\tpci_addr->devid == eth_pci_addr->devid &&\n\t\t\tpci_addr->domain == eth_pci_addr->domain &&\n\t\t\tpci_addr->function == eth_pci_addr->function)\n\t\t\treturn i;\n\t}\n\treturn -1;\n}\n\nstatic inline int\nfind_port_id_by_dev_name(const char *name)\n{\n\tunsigned i;\n\n\tfor (i = 0; i < rte_eth_dev_count(); i++) {\n\t\tif (rte_eth_devices[i].data == NULL)\n\t\t\tcontinue;\n\n\t\tif (strcmp(rte_eth_devices[i].data->name, name) == 0)\n\t\t\treturn i;\n\t}\n\treturn -1;\n}\n\n/**\n * Parses a port identifier string to a port id by pci address, then by name,\n * and finally port id.\n */\nstatic inline int\nparse_port_id(const char *port_str)\n{\n\tstruct rte_pci_addr dev_addr;\n\tint port_id;\n\n\t/* try parsing as pci address, physical devices */\n\tif (eal_parse_pci_DomBDF(port_str, &dev_addr) == 0) {\n\t\tport_id = find_port_id_by_pci_addr(&dev_addr);\n\t\tif (port_id < 0)\n\t\t\treturn -1;\n\t} else {\n\t\t/* try parsing as device name, virtual devices */\n\t\tport_id = find_port_id_by_dev_name(port_str);\n\t\tif (port_id < 0) {\n\t\t\tchar *end;\n\t\t\terrno = 0;\n\n\t\t\t/* try parsing as port id */\n\t\t\tport_id = strtol(port_str, &end, 10);\n\t\t\tif (*end != 0 || errno != 0)\n\t\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (port_id < 0 || port_id > RTE_MAX_ETHPORTS) {\n\t\tRTE_BOND_LOG(ERR, \"Slave port specified (%s) outside expected range\",\n\t\t\t\tport_str);\n\t\treturn -1;\n\t}\n\treturn port_id;\n}\n\nint\nbond_ethdev_parse_slave_port_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args)\n{\n\tstruct bond_ethdev_slave_ports *slave_ports;\n\n\tif (value == NULL || extra_args == NULL)\n\t\treturn -1;\n\n\tslave_ports = extra_args;\n\n\tif (strcmp(key, PMD_BOND_SLAVE_PORT_KVARG) == 0) {\n\t\tint port_id = parse_port_id(value);\n\t\tif (port_id < 0) {\n\t\t\tRTE_BOND_LOG(ERR, \"Invalid slave port value (%s) specified\", value);\n\t\t\treturn -1;\n\t\t} else\n\t\t\tslave_ports->slaves[slave_ports->slave_count++] =\n\t\t\t\t\t(uint8_t)port_id;\n\t}\n\treturn 0;\n}\n\nint\nbond_ethdev_parse_slave_mode_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args)\n{\n\tuint8_t *mode;\n\tchar *endptr;\n\n\tif (value == NULL || extra_args == NULL)\n\t\treturn -1;\n\n\tmode = extra_args;\n\n\terrno = 0;\n\t*mode = strtol(value, &endptr, 10);\n\tif (*endptr != 0 || errno != 0)\n\t\treturn -1;\n\n\t/* validate mode value */\n\tswitch (*mode) {\n\tcase BONDING_MODE_ROUND_ROBIN:\n\tcase BONDING_MODE_ACTIVE_BACKUP:\n\tcase BONDING_MODE_BALANCE:\n\tcase BONDING_MODE_BROADCAST:\n\tcase BONDING_MODE_8023AD:\n\tcase BONDING_MODE_TLB:\n\tcase BONDING_MODE_ALB:\n\t\treturn 0;\n\tdefault:\n\t\tRTE_BOND_LOG(ERR, \"Invalid slave mode value (%s) specified\", value);\n\t\treturn -1;\n\t}\n}\n\nint\nbond_ethdev_parse_socket_id_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args)\n{\n\tint socket_id;\n\tchar *endptr;\n\n\tif (value == NULL || extra_args == NULL)\n\t\treturn -1;\n\n\terrno = 0;\n\tsocket_id = (uint8_t)strtol(value, &endptr, 10);\n\tif (*endptr != 0 || errno != 0)\n\t\treturn -1;\n\n\t/* validate mode value */\n\tif (socket_id >= 0 && socket_id < number_of_sockets()) {\n\t\t*(uint8_t *)extra_args = (uint8_t)socket_id;\n\t\treturn 0;\n\t}\n\treturn -1;\n}\n\nint\nbond_ethdev_parse_primary_slave_port_id_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args)\n{\n\tint primary_slave_port_id;\n\n\tif (value == NULL || extra_args == NULL)\n\t\treturn -1;\n\n\tprimary_slave_port_id = parse_port_id(value);\n\tif (primary_slave_port_id < 0)\n\t\treturn -1;\n\n\t*(uint8_t *)extra_args = (uint8_t)primary_slave_port_id;\n\n\treturn 0;\n}\n\nint\nbond_ethdev_parse_balance_xmit_policy_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args)\n{\n\tuint8_t *xmit_policy;\n\n\tif (value == NULL || extra_args == NULL)\n\t\treturn -1;\n\n\txmit_policy = extra_args;\n\n\tif (strcmp(PMD_BOND_XMIT_POLICY_LAYER2_KVARG, value) == 0)\n\t\t*xmit_policy = BALANCE_XMIT_POLICY_LAYER2;\n\telse if (strcmp(PMD_BOND_XMIT_POLICY_LAYER23_KVARG, value) == 0)\n\t\t*xmit_policy = BALANCE_XMIT_POLICY_LAYER23;\n\telse if (strcmp(PMD_BOND_XMIT_POLICY_LAYER34_KVARG, value) == 0)\n\t\t*xmit_policy = BALANCE_XMIT_POLICY_LAYER34;\n\telse\n\t\treturn -1;\n\n\treturn 0;\n}\n\nint\nbond_ethdev_parse_bond_mac_addr_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args)\n{\n\tif (value == NULL || extra_args == NULL)\n\t\treturn -1;\n\n\t/* Parse MAC */\n\treturn cmdline_parse_etheraddr(NULL, value, extra_args,\n\t\tsizeof(struct ether_addr));\n}\n\nint\nbond_ethdev_parse_time_ms_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args)\n{\n\tuint32_t time_ms;\n\tchar *endptr;\n\n\tif (value == NULL || extra_args == NULL)\n\t\treturn -1;\n\n\terrno = 0;\n\ttime_ms = (uint32_t)strtol(value, &endptr, 10);\n\tif (*endptr != 0 || errno != 0)\n\t\treturn -1;\n\n\t*(uint32_t *)extra_args = time_ms;\n\n\treturn 0;\n}\n" }, { "path": "drivers/net/bonding/rte_eth_bond_pmd.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_eth_bond.h\"\n#include \"rte_eth_bond_private.h\"\n#include \"rte_eth_bond_8023ad_private.h\"\n\n#define REORDER_PERIOD_MS 10\n\n#define HASH_L4_PORTS(h) ((h)->src_port ^ (h)->dst_port)\n\n/* Table for statistics in mode 5 TLB */\nstatic uint64_t tlb_last_obytets[RTE_MAX_ETHPORTS];\n\nstatic inline size_t\nget_vlan_offset(struct ether_hdr *eth_hdr, uint16_t *proto)\n{\n\tsize_t vlan_offset = 0;\n\n\tif (rte_cpu_to_be_16(ETHER_TYPE_VLAN) == *proto) {\n\t\tstruct vlan_hdr *vlan_hdr = (struct vlan_hdr *)(eth_hdr + 1);\n\n\t\tvlan_offset = sizeof(struct vlan_hdr);\n\t\t*proto = vlan_hdr->eth_proto;\n\n\t\tif (rte_cpu_to_be_16(ETHER_TYPE_VLAN) == *proto) {\n\t\t\tvlan_hdr = vlan_hdr + 1;\n\t\t\t*proto = vlan_hdr->eth_proto;\n\t\t\tvlan_offset += sizeof(struct vlan_hdr);\n\t\t}\n\t}\n\treturn vlan_offset;\n}\n\nstatic uint16_t\nbond_ethdev_rx_burst(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n{\n\tstruct bond_dev_private *internals;\n\n\tuint16_t num_rx_slave = 0;\n\tuint16_t num_rx_total = 0;\n\n\tint i;\n\n\t/* Cast to structure, containing bonded device's port id and queue id */\n\tstruct bond_rx_queue *bd_rx_q = (struct bond_rx_queue *)queue;\n\n\tinternals = bd_rx_q->dev_private;\n\n\n\tfor (i = 0; i < internals->active_slave_count && nb_pkts; i++) {\n\t\t/* Offset of pointer to *bufs increases as packets are received\n\t\t * from other slaves */\n\t\tnum_rx_slave = rte_eth_rx_burst(internals->active_slaves[i],\n\t\t\t\tbd_rx_q->queue_id, bufs + num_rx_total, nb_pkts);\n\t\tif (num_rx_slave) {\n\t\t\tnum_rx_total += num_rx_slave;\n\t\t\tnb_pkts -= num_rx_slave;\n\t\t}\n\t}\n\n\treturn num_rx_total;\n}\n\nstatic uint16_t\nbond_ethdev_rx_burst_active_backup(void *queue, struct rte_mbuf **bufs,\n\t\tuint16_t nb_pkts)\n{\n\tstruct bond_dev_private *internals;\n\n\t/* Cast to structure, containing bonded device's port id and queue id */\n\tstruct bond_rx_queue *bd_rx_q = (struct bond_rx_queue *)queue;\n\n\tinternals = bd_rx_q->dev_private;\n\n\treturn rte_eth_rx_burst(internals->current_primary_port,\n\t\t\tbd_rx_q->queue_id, bufs, nb_pkts);\n}\n\nstatic uint16_t\nbond_ethdev_rx_burst_8023ad(void *queue, struct rte_mbuf **bufs,\n\t\tuint16_t nb_pkts)\n{\n\t/* Cast to structure, containing bonded device's port id and queue id */\n\tstruct bond_rx_queue *bd_rx_q = (struct bond_rx_queue *)queue;\n\tstruct bond_dev_private *internals = bd_rx_q->dev_private;\n\tstruct ether_addr bond_mac;\n\n\tstruct ether_hdr *hdr;\n\n\tconst uint16_t ether_type_slow_be = rte_be_to_cpu_16(ETHER_TYPE_SLOW);\n\tuint16_t num_rx_total = 0;\t/* Total number of received packets */\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\tuint8_t slave_count;\n\n\tuint8_t collecting; /* current slave collecting status */\n\tconst uint8_t promisc = internals->promiscuous_en;\n\tuint8_t i, j, k;\n\n\trte_eth_macaddr_get(internals->port_id, &bond_mac);\n\t/* Copy slave list to protect against slave up/down changes during tx\n\t * bursting */\n\tslave_count = internals->active_slave_count;\n\tmemcpy(slaves, internals->active_slaves,\n\t\t\tsizeof(internals->active_slaves[0]) * slave_count);\n\n\tfor (i = 0; i < slave_count && num_rx_total < nb_pkts; i++) {\n\t\tj = num_rx_total;\n\t\tcollecting = ACTOR_STATE(&mode_8023ad_ports[slaves[i]], COLLECTING);\n\n\t\t/* Read packets from this slave */\n\t\tnum_rx_total += rte_eth_rx_burst(slaves[i], bd_rx_q->queue_id,\n\t\t\t\t&bufs[num_rx_total], nb_pkts - num_rx_total);\n\n\t\tfor (k = j; k < 2 && k < num_rx_total; k++)\n\t\t\trte_prefetch0(rte_pktmbuf_mtod(bufs[k], void *));\n\n\t\t/* Handle slow protocol packets. */\n\t\twhile (j < num_rx_total) {\n\t\t\tif (j + 3 < num_rx_total)\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(bufs[j + 3], void *));\n\n\t\t\thdr = rte_pktmbuf_mtod(bufs[j], struct ether_hdr *);\n\t\t\t/* Remove packet from array if it is slow packet or slave is not\n\t\t\t * in collecting state or bondign interface is not in promiscus\n\t\t\t * mode and packet address does not match. */\n\t\t\tif (unlikely(hdr->ether_type == ether_type_slow_be ||\n\t\t\t\t!collecting || (!promisc &&\n\t\t\t\t\t!is_same_ether_addr(&bond_mac, &hdr->d_addr)))) {\n\n\t\t\t\tif (hdr->ether_type == ether_type_slow_be) {\n\t\t\t\t\tbond_mode_8023ad_handle_slow_pkt(internals, slaves[i],\n\t\t\t\t\t\tbufs[j]);\n\t\t\t\t} else\n\t\t\t\t\trte_pktmbuf_free(bufs[j]);\n\n\t\t\t\t/* Packet is managed by mode 4 or dropped, shift the array */\n\t\t\t\tnum_rx_total--;\n\t\t\t\tif (j < num_rx_total) {\n\t\t\t\t\tmemmove(&bufs[j], &bufs[j + 1], sizeof(bufs[0]) *\n\t\t\t\t\t\t(num_rx_total - j));\n\t\t\t\t}\n\t\t\t} else\n\t\t\t\tj++;\n\t\t}\n\t}\n\n\treturn num_rx_total;\n}\n\n#if defined(RTE_LIBRTE_BOND_DEBUG_ALB) || defined(RTE_LIBRTE_BOND_DEBUG_ALB_L1)\nuint32_t burstnumberRX;\nuint32_t burstnumberTX;\n\n#ifdef RTE_LIBRTE_BOND_DEBUG_ALB\n\nstatic void\narp_op_name(uint16_t arp_op, char *buf)\n{\n\tswitch (arp_op) {\n\tcase ARP_OP_REQUEST:\n\t\tsnprintf(buf, sizeof(\"ARP Request\"), \"%s\", \"ARP Request\");\n\t\treturn;\n\tcase ARP_OP_REPLY:\n\t\tsnprintf(buf, sizeof(\"ARP Reply\"), \"%s\", \"ARP Reply\");\n\t\treturn;\n\tcase ARP_OP_REVREQUEST:\n\t\tsnprintf(buf, sizeof(\"Reverse ARP Request\"), \"%s\",\n\t\t\t\t\"Reverse ARP Request\");\n\t\treturn;\n\tcase ARP_OP_REVREPLY:\n\t\tsnprintf(buf, sizeof(\"Reverse ARP Reply\"), \"%s\",\n\t\t\t\t\"Reverse ARP Reply\");\n\t\treturn;\n\tcase ARP_OP_INVREQUEST:\n\t\tsnprintf(buf, sizeof(\"Peer Identify Request\"), \"%s\",\n\t\t\t\t\"Peer Identify Request\");\n\t\treturn;\n\tcase ARP_OP_INVREPLY:\n\t\tsnprintf(buf, sizeof(\"Peer Identify Reply\"), \"%s\",\n\t\t\t\t\"Peer Identify Reply\");\n\t\treturn;\n\tdefault:\n\t\tbreak;\n\t}\n\tsnprintf(buf, sizeof(\"Unknown\"), \"%s\", \"Unknown\");\n\treturn;\n}\n#endif\n#define MaxIPv4String\t16\nstatic void\nipv4_addr_to_dot(uint32_t be_ipv4_addr, char *buf, uint8_t buf_size)\n{\n\tuint32_t ipv4_addr;\n\n\tipv4_addr = rte_be_to_cpu_32(be_ipv4_addr);\n\tsnprintf(buf, buf_size, \"%d.%d.%d.%d\", (ipv4_addr >> 24) & 0xFF,\n\t\t(ipv4_addr >> 16) & 0xFF, (ipv4_addr >> 8) & 0xFF,\n\t\tipv4_addr & 0xFF);\n}\n\n#define MAX_CLIENTS_NUMBER\t128\nuint8_t active_clients;\nstruct client_stats_t {\n\tuint8_t port;\n\tuint32_t ipv4_addr;\n\tuint32_t ipv4_rx_packets;\n\tuint32_t ipv4_tx_packets;\n};\nstruct client_stats_t client_stats[MAX_CLIENTS_NUMBER];\n\nstatic void\nupdate_client_stats(uint32_t addr, uint8_t port, uint32_t *TXorRXindicator)\n{\n\tint i = 0;\n\n\tfor (; i < MAX_CLIENTS_NUMBER; i++)\t{\n\t\tif ((client_stats[i].ipv4_addr == addr) && (client_stats[i].port == port))\t{\n\t\t\t/* Just update RX packets number for this client */\n\t\t\tif (TXorRXindicator == &burstnumberRX)\n\t\t\t\tclient_stats[i].ipv4_rx_packets++;\n\t\t\telse\n\t\t\t\tclient_stats[i].ipv4_tx_packets++;\n\t\t\treturn;\n\t\t}\n\t}\n\t/* We have a new client. Insert him to the table, and increment stats */\n\tif (TXorRXindicator == &burstnumberRX)\n\t\tclient_stats[active_clients].ipv4_rx_packets++;\n\telse\n\t\tclient_stats[active_clients].ipv4_tx_packets++;\n\tclient_stats[active_clients].ipv4_addr = addr;\n\tclient_stats[active_clients].port = port;\n\tactive_clients++;\n\n}\n\n#ifdef RTE_LIBRTE_BOND_DEBUG_ALB\n#define MODE6_DEBUG(info, src_ip, dst_ip, eth_h, arp_op, port, burstnumber)\t\\\n\t\tRTE_LOG(DEBUG, PMD, \\\n\t\t\"%s \" \\\n\t\t\"port:%d \" \\\n\t\t\"SrcMAC:%02X:%02X:%02X:%02X:%02X:%02X \" \\\n\t\t\"SrcIP:%s \" \\\n\t\t\"DstMAC:%02X:%02X:%02X:%02X:%02X:%02X \" \\\n\t\t\"DstIP:%s \" \\\n\t\t\"%s \" \\\n\t\t\"%d\\n\", \\\n\t\tinfo, \\\n\t\tport, \\\n\t\teth_h->s_addr.addr_bytes[0], \\\n\t\teth_h->s_addr.addr_bytes[1], \\\n\t\teth_h->s_addr.addr_bytes[2], \\\n\t\teth_h->s_addr.addr_bytes[3], \\\n\t\teth_h->s_addr.addr_bytes[4], \\\n\t\teth_h->s_addr.addr_bytes[5], \\\n\t\tsrc_ip, \\\n\t\teth_h->d_addr.addr_bytes[0], \\\n\t\teth_h->d_addr.addr_bytes[1], \\\n\t\teth_h->d_addr.addr_bytes[2], \\\n\t\teth_h->d_addr.addr_bytes[3], \\\n\t\teth_h->d_addr.addr_bytes[4], \\\n\t\teth_h->d_addr.addr_bytes[5], \\\n\t\tdst_ip, \\\n\t\tarp_op, \\\n\t\t++burstnumber)\n#endif\n\nstatic void\nmode6_debug(const char __attribute__((unused)) *info, struct ether_hdr *eth_h,\n\t\tuint8_t port, uint32_t __attribute__((unused)) *burstnumber)\n{\n\tstruct ipv4_hdr *ipv4_h;\n#ifdef RTE_LIBRTE_BOND_DEBUG_ALB\n\tstruct arp_hdr *arp_h;\n\tchar dst_ip[16];\n\tchar ArpOp[24];\n\tchar buf[16];\n#endif\n\tchar src_ip[16];\n\n\tuint16_t ether_type = eth_h->ether_type;\n\tuint16_t offset = get_vlan_offset(eth_h, ðer_type);\n\n#ifdef RTE_LIBRTE_BOND_DEBUG_ALB\n\tsnprintf(buf, 16, \"%s\", info);\n#endif\n\n\tif (ether_type == rte_cpu_to_be_16(ETHER_TYPE_IPv4)) {\n\t\tipv4_h = (struct ipv4_hdr *)((char *)(eth_h + 1) + offset);\n\t\tipv4_addr_to_dot(ipv4_h->src_addr, src_ip, MaxIPv4String);\n#ifdef RTE_LIBRTE_BOND_DEBUG_ALB\n\t\tipv4_addr_to_dot(ipv4_h->dst_addr, dst_ip, MaxIPv4String);\n\t\tMODE6_DEBUG(buf, src_ip, dst_ip, eth_h, \"\", port, *burstnumber);\n#endif\n\t\tupdate_client_stats(ipv4_h->src_addr, port, burstnumber);\n\t}\n#ifdef RTE_LIBRTE_BOND_DEBUG_ALB\n\telse if (ether_type == rte_cpu_to_be_16(ETHER_TYPE_ARP)) {\n\t\tarp_h = (struct arp_hdr *)((char *)(eth_h + 1) + offset);\n\t\tipv4_addr_to_dot(arp_h->arp_data.arp_sip, src_ip, MaxIPv4String);\n\t\tipv4_addr_to_dot(arp_h->arp_data.arp_tip, dst_ip, MaxIPv4String);\n\t\tarp_op_name(rte_be_to_cpu_16(arp_h->arp_op), ArpOp);\n\t\tMODE6_DEBUG(buf, src_ip, dst_ip, eth_h, ArpOp, port, *burstnumber);\n\t}\n#endif\n}\n#endif\n\nstatic uint16_t\nbond_ethdev_rx_burst_alb(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n{\n\tstruct bond_tx_queue *bd_tx_q = (struct bond_tx_queue *)queue;\n\tstruct bond_dev_private *internals = bd_tx_q->dev_private;\n\tstruct ether_hdr *eth_h;\n\tuint16_t ether_type, offset;\n\tuint16_t nb_recv_pkts;\n\tint i;\n\n\tnb_recv_pkts = bond_ethdev_rx_burst(queue, bufs, nb_pkts);\n\n\tfor (i = 0; i < nb_recv_pkts; i++) {\n\t\teth_h = rte_pktmbuf_mtod(bufs[i], struct ether_hdr *);\n\t\tether_type = eth_h->ether_type;\n\t\toffset = get_vlan_offset(eth_h, ðer_type);\n\n\t\tif (ether_type == rte_cpu_to_be_16(ETHER_TYPE_ARP)) {\n#if defined(RTE_LIBRTE_BOND_DEBUG_ALB) || defined(RTE_LIBRTE_BOND_DEBUG_ALB_L1)\n\t\t\tmode6_debug(\"RX ARP:\", eth_h, bufs[i]->port, &burstnumberRX);\n#endif\n\t\t\tbond_mode_alb_arp_recv(eth_h, offset, internals);\n\t\t}\n#if defined(RTE_LIBRTE_BOND_DEBUG_ALB) || defined(RTE_LIBRTE_BOND_DEBUG_ALB_L1)\n\t\telse if (ether_type == rte_cpu_to_be_16(ETHER_TYPE_IPv4))\n\t\t\tmode6_debug(\"RX IPv4:\", eth_h, bufs[i]->port, &burstnumberRX);\n#endif\n\t}\n\n\treturn nb_recv_pkts;\n}\n\nstatic uint16_t\nbond_ethdev_tx_burst_round_robin(void *queue, struct rte_mbuf **bufs,\n\t\tuint16_t nb_pkts)\n{\n\tstruct bond_dev_private *internals;\n\tstruct bond_tx_queue *bd_tx_q;\n\n\tstruct rte_mbuf *slave_bufs[RTE_MAX_ETHPORTS][nb_pkts];\n\tuint16_t slave_nb_pkts[RTE_MAX_ETHPORTS] = { 0 };\n\n\tuint8_t num_of_slaves;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tuint16_t num_tx_total = 0, num_tx_slave;\n\n\tstatic int slave_idx = 0;\n\tint i, cslave_idx = 0, tx_fail_total = 0;\n\n\tbd_tx_q = (struct bond_tx_queue *)queue;\n\tinternals = bd_tx_q->dev_private;\n\n\t/* Copy slave list to protect against slave up/down changes during tx\n\t * bursting */\n\tnum_of_slaves = internals->active_slave_count;\n\tmemcpy(slaves, internals->active_slaves,\n\t\t\tsizeof(internals->active_slaves[0]) * num_of_slaves);\n\n\tif (num_of_slaves < 1)\n\t\treturn num_tx_total;\n\n\t/* Populate slaves mbuf with which packets are to be sent on it */\n\tfor (i = 0; i < nb_pkts; i++) {\n\t\tcslave_idx = (slave_idx + i) % num_of_slaves;\n\t\tslave_bufs[cslave_idx][(slave_nb_pkts[cslave_idx])++] = bufs[i];\n\t}\n\n\t/* increment current slave index so the next call to tx burst starts on the\n\t * next slave */\n\tslave_idx = ++cslave_idx;\n\n\t/* Send packet burst on each slave device */\n\tfor (i = 0; i < num_of_slaves; i++) {\n\t\tif (slave_nb_pkts[i] > 0) {\n\t\t\tnum_tx_slave = rte_eth_tx_burst(slaves[i], bd_tx_q->queue_id,\n\t\t\t\t\tslave_bufs[i], slave_nb_pkts[i]);\n\n\t\t\t/* if tx burst fails move packets to end of bufs */\n\t\t\tif (unlikely(num_tx_slave < slave_nb_pkts[i])) {\n\t\t\t\tint tx_fail_slave = slave_nb_pkts[i] - num_tx_slave;\n\n\t\t\t\ttx_fail_total += tx_fail_slave;\n\n\t\t\t\tmemcpy(&bufs[nb_pkts - tx_fail_total],\n\t\t\t\t\t\t&slave_bufs[i][num_tx_slave],\n\t\t\t\t\t\ttx_fail_slave * sizeof(bufs[0]));\n\t\t\t}\n\t\t\tnum_tx_total += num_tx_slave;\n\t\t}\n\t}\n\n\treturn num_tx_total;\n}\n\nstatic uint16_t\nbond_ethdev_tx_burst_active_backup(void *queue,\n\t\tstruct rte_mbuf **bufs, uint16_t nb_pkts)\n{\n\tstruct bond_dev_private *internals;\n\tstruct bond_tx_queue *bd_tx_q;\n\n\tbd_tx_q = (struct bond_tx_queue *)queue;\n\tinternals = bd_tx_q->dev_private;\n\n\tif (internals->active_slave_count < 1)\n\t\treturn 0;\n\n\treturn rte_eth_tx_burst(internals->current_primary_port, bd_tx_q->queue_id,\n\t\t\tbufs, nb_pkts);\n}\n\nstatic inline uint16_t\nether_hash(struct ether_hdr *eth_hdr)\n{\n\tunaligned_uint16_t *word_src_addr =\n\t\t(unaligned_uint16_t *)eth_hdr->s_addr.addr_bytes;\n\tunaligned_uint16_t *word_dst_addr =\n\t\t(unaligned_uint16_t *)eth_hdr->d_addr.addr_bytes;\n\n\treturn (word_src_addr[0] ^ word_dst_addr[0]) ^\n\t\t\t(word_src_addr[1] ^ word_dst_addr[1]) ^\n\t\t\t(word_src_addr[2] ^ word_dst_addr[2]);\n}\n\nstatic inline uint32_t\nipv4_hash(struct ipv4_hdr *ipv4_hdr)\n{\n\treturn (ipv4_hdr->src_addr ^ ipv4_hdr->dst_addr);\n}\n\nstatic inline uint32_t\nipv6_hash(struct ipv6_hdr *ipv6_hdr)\n{\n\tunaligned_uint32_t *word_src_addr =\n\t\t(unaligned_uint32_t *)&(ipv6_hdr->src_addr[0]);\n\tunaligned_uint32_t *word_dst_addr =\n\t\t(unaligned_uint32_t *)&(ipv6_hdr->dst_addr[0]);\n\n\treturn (word_src_addr[0] ^ word_dst_addr[0]) ^\n\t\t\t(word_src_addr[1] ^ word_dst_addr[1]) ^\n\t\t\t(word_src_addr[2] ^ word_dst_addr[2]) ^\n\t\t\t(word_src_addr[3] ^ word_dst_addr[3]);\n}\n\nuint16_t\nxmit_l2_hash(const struct rte_mbuf *buf, uint8_t slave_count)\n{\n\tstruct ether_hdr *eth_hdr = rte_pktmbuf_mtod(buf, struct ether_hdr *);\n\n\tuint32_t hash = ether_hash(eth_hdr);\n\n\treturn (hash ^= hash >> 8) % slave_count;\n}\n\nuint16_t\nxmit_l23_hash(const struct rte_mbuf *buf, uint8_t slave_count)\n{\n\tstruct ether_hdr *eth_hdr = rte_pktmbuf_mtod(buf, struct ether_hdr *);\n\tuint16_t proto = eth_hdr->ether_type;\n\tsize_t vlan_offset = get_vlan_offset(eth_hdr, &proto);\n\tuint32_t hash, l3hash = 0;\n\n\thash = ether_hash(eth_hdr);\n\n\tif (rte_cpu_to_be_16(ETHER_TYPE_IPv4) == proto) {\n\t\tstruct ipv4_hdr *ipv4_hdr = (struct ipv4_hdr *)\n\t\t\t\t((char *)(eth_hdr + 1) + vlan_offset);\n\t\tl3hash = ipv4_hash(ipv4_hdr);\n\n\t} else if (rte_cpu_to_be_16(ETHER_TYPE_IPv6) == proto) {\n\t\tstruct ipv6_hdr *ipv6_hdr = (struct ipv6_hdr *)\n\t\t\t\t((char *)(eth_hdr + 1) + vlan_offset);\n\t\tl3hash = ipv6_hash(ipv6_hdr);\n\t}\n\n\thash = hash ^ l3hash;\n\thash ^= hash >> 16;\n\thash ^= hash >> 8;\n\n\treturn hash % slave_count;\n}\n\nuint16_t\nxmit_l34_hash(const struct rte_mbuf *buf, uint8_t slave_count)\n{\n\tstruct ether_hdr *eth_hdr = rte_pktmbuf_mtod(buf, struct ether_hdr *);\n\tuint16_t proto = eth_hdr->ether_type;\n\tsize_t vlan_offset = get_vlan_offset(eth_hdr, &proto);\n\n\tstruct udp_hdr *udp_hdr = NULL;\n\tstruct tcp_hdr *tcp_hdr = NULL;\n\tuint32_t hash, l3hash = 0, l4hash = 0;\n\n\tif (rte_cpu_to_be_16(ETHER_TYPE_IPv4) == proto) {\n\t\tstruct ipv4_hdr *ipv4_hdr = (struct ipv4_hdr *)\n\t\t\t\t((char *)(eth_hdr + 1) + vlan_offset);\n\t\tsize_t ip_hdr_offset;\n\n\t\tl3hash = ipv4_hash(ipv4_hdr);\n\n\t\tip_hdr_offset = (ipv4_hdr->version_ihl & IPV4_HDR_IHL_MASK) *\n\t\t\t\tIPV4_IHL_MULTIPLIER;\n\n\t\tif (ipv4_hdr->next_proto_id == IPPROTO_TCP) {\n\t\t\ttcp_hdr = (struct tcp_hdr *)((char *)ipv4_hdr +\n\t\t\t\t\tip_hdr_offset);\n\t\t\tl4hash = HASH_L4_PORTS(tcp_hdr);\n\t\t} else if (ipv4_hdr->next_proto_id == IPPROTO_UDP) {\n\t\t\tudp_hdr = (struct udp_hdr *)((char *)ipv4_hdr +\n\t\t\t\t\tip_hdr_offset);\n\t\t\tl4hash = HASH_L4_PORTS(udp_hdr);\n\t\t}\n\t} else if (rte_cpu_to_be_16(ETHER_TYPE_IPv6) == proto) {\n\t\tstruct ipv6_hdr *ipv6_hdr = (struct ipv6_hdr *)\n\t\t\t\t((char *)(eth_hdr + 1) + vlan_offset);\n\t\tl3hash = ipv6_hash(ipv6_hdr);\n\n\t\tif (ipv6_hdr->proto == IPPROTO_TCP) {\n\t\t\ttcp_hdr = (struct tcp_hdr *)(ipv6_hdr + 1);\n\t\t\tl4hash = HASH_L4_PORTS(tcp_hdr);\n\t\t} else if (ipv6_hdr->proto == IPPROTO_UDP) {\n\t\t\tudp_hdr = (struct udp_hdr *)(ipv6_hdr + 1);\n\t\t\tl4hash = HASH_L4_PORTS(udp_hdr);\n\t\t}\n\t}\n\n\thash = l3hash ^ l4hash;\n\thash ^= hash >> 16;\n\thash ^= hash >> 8;\n\n\treturn hash % slave_count;\n}\n\nstruct bwg_slave {\n\tuint64_t bwg_left_int;\n\tuint64_t bwg_left_remainder;\n\tuint8_t slave;\n};\n\nvoid\nbond_tlb_activate_slave(struct bond_dev_private *internals) {\n\tint i;\n\n\tfor (i = 0; i < internals->active_slave_count; i++) {\n\t\ttlb_last_obytets[internals->active_slaves[i]] = 0;\n\t}\n}\n\nstatic int\nbandwidth_cmp(const void *a, const void *b)\n{\n\tconst struct bwg_slave *bwg_a = a;\n\tconst struct bwg_slave *bwg_b = b;\n\tint64_t diff = (int64_t)bwg_b->bwg_left_int - (int64_t)bwg_a->bwg_left_int;\n\tint64_t diff2 = (int64_t)bwg_b->bwg_left_remainder -\n\t\t\t(int64_t)bwg_a->bwg_left_remainder;\n\tif (diff > 0)\n\t\treturn 1;\n\telse if (diff < 0)\n\t\treturn -1;\n\telse if (diff2 > 0)\n\t\treturn 1;\n\telse if (diff2 < 0)\n\t\treturn -1;\n\telse\n\t\treturn 0;\n}\n\nstatic void\nbandwidth_left(uint8_t port_id, uint64_t load, uint8_t update_idx,\n\t\tstruct bwg_slave *bwg_slave)\n{\n\tstruct rte_eth_link link_status;\n\n\trte_eth_link_get(port_id, &link_status);\n\tuint64_t link_bwg = link_status.link_speed * 1000000ULL / 8;\n\tif (link_bwg == 0)\n\t\treturn;\n\tlink_bwg = link_bwg * (update_idx+1) * REORDER_PERIOD_MS;\n\tbwg_slave->bwg_left_int = (link_bwg - 1000*load) / link_bwg;\n\tbwg_slave->bwg_left_remainder = (link_bwg - 1000*load) % link_bwg;\n}\n\nstatic void\nbond_ethdev_update_tlb_slave_cb(void *arg)\n{\n\tstruct bond_dev_private *internals = arg;\n\tstruct rte_eth_stats slave_stats;\n\tstruct bwg_slave bwg_array[RTE_MAX_ETHPORTS];\n\tuint8_t slave_count;\n\tuint64_t tx_bytes;\n\n\tuint8_t update_stats = 0;\n\tuint8_t i, slave_id;\n\n\tinternals->slave_update_idx++;\n\n\n\tif (internals->slave_update_idx >= REORDER_PERIOD_MS)\n\t\tupdate_stats = 1;\n\n\tfor (i = 0; i < internals->active_slave_count; i++) {\n\t\tslave_id = internals->active_slaves[i];\n\t\trte_eth_stats_get(slave_id, &slave_stats);\n\t\ttx_bytes = slave_stats.obytes - tlb_last_obytets[slave_id];\n\t\tbandwidth_left(slave_id, tx_bytes,\n\t\t\t\tinternals->slave_update_idx, &bwg_array[i]);\n\t\tbwg_array[i].slave = slave_id;\n\n\t\tif (update_stats) {\n\t\t\ttlb_last_obytets[slave_id] = slave_stats.obytes;\n\t\t}\n\t}\n\n\tif (update_stats == 1)\n\t\tinternals->slave_update_idx = 0;\n\n\tslave_count = i;\n\tqsort(bwg_array, slave_count, sizeof(bwg_array[0]), bandwidth_cmp);\n\tfor (i = 0; i < slave_count; i++)\n\t\tinternals->tlb_slaves_order[i] = bwg_array[i].slave;\n\n\trte_eal_alarm_set(REORDER_PERIOD_MS * 1000, bond_ethdev_update_tlb_slave_cb,\n\t\t\t(struct bond_dev_private *)internals);\n}\n\nstatic uint16_t\nbond_ethdev_tx_burst_tlb(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n{\n\tstruct bond_tx_queue *bd_tx_q = (struct bond_tx_queue *)queue;\n\tstruct bond_dev_private *internals = bd_tx_q->dev_private;\n\n\tstruct rte_eth_dev *primary_port =\n\t\t\t&rte_eth_devices[internals->primary_port];\n\tuint16_t num_tx_total = 0;\n\tuint8_t i, j;\n\n\tuint8_t num_of_slaves = internals->active_slave_count;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tstruct ether_hdr *ether_hdr;\n\tstruct ether_addr primary_slave_addr;\n\tstruct ether_addr active_slave_addr;\n\n\tif (num_of_slaves < 1)\n\t\treturn num_tx_total;\n\n\tmemcpy(slaves, internals->tlb_slaves_order,\n\t\t\t\tsizeof(internals->tlb_slaves_order[0]) * num_of_slaves);\n\n\n\tether_addr_copy(primary_port->data->mac_addrs, &primary_slave_addr);\n\n\tif (nb_pkts > 3) {\n\t\tfor (i = 0; i < 3; i++)\n\t\t\trte_prefetch0(rte_pktmbuf_mtod(bufs[i], void*));\n\t}\n\n\tfor (i = 0; i < num_of_slaves; i++) {\n\t\trte_eth_macaddr_get(slaves[i], &active_slave_addr);\n\t\tfor (j = num_tx_total; j < nb_pkts; j++) {\n\t\t\tif (j + 3 < nb_pkts)\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(bufs[j+3], void*));\n\n\t\t\tether_hdr = rte_pktmbuf_mtod(bufs[j], struct ether_hdr *);\n\t\t\tif (is_same_ether_addr(ðer_hdr->s_addr, &primary_slave_addr))\n\t\t\t\tether_addr_copy(&active_slave_addr, ðer_hdr->s_addr);\n#if defined(RTE_LIBRTE_BOND_DEBUG_ALB) || defined(RTE_LIBRTE_BOND_DEBUG_ALB_L1)\n\t\t\t\t\tmode6_debug(\"TX IPv4:\", ether_hdr, slaves[i], &burstnumberTX);\n#endif\n\t\t}\n\n\t\tnum_tx_total += rte_eth_tx_burst(slaves[i], bd_tx_q->queue_id,\n\t\t\t\tbufs + num_tx_total, nb_pkts - num_tx_total);\n\n\t\tif (num_tx_total == nb_pkts)\n\t\t\tbreak;\n\t}\n\n\treturn num_tx_total;\n}\n\nvoid\nbond_tlb_disable(struct bond_dev_private *internals)\n{\n\trte_eal_alarm_cancel(bond_ethdev_update_tlb_slave_cb, internals);\n}\n\nvoid\nbond_tlb_enable(struct bond_dev_private *internals)\n{\n\tbond_ethdev_update_tlb_slave_cb(internals);\n}\n\nstatic uint16_t\nbond_ethdev_tx_burst_alb(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n{\n\tstruct bond_tx_queue *bd_tx_q = (struct bond_tx_queue *)queue;\n\tstruct bond_dev_private *internals = bd_tx_q->dev_private;\n\n\tstruct ether_hdr *eth_h;\n\tuint16_t ether_type, offset;\n\n\tstruct client_data *client_info;\n\n\t/*\n\t * We create transmit buffers for every slave and one additional to send\n\t * through tlb. In worst case every packet will be send on one port.\n\t */\n\tstruct rte_mbuf *slave_bufs[RTE_MAX_ETHPORTS + 1][nb_pkts];\n\tuint16_t slave_bufs_pkts[RTE_MAX_ETHPORTS + 1] = { 0 };\n\n\t/*\n\t * We create separate transmit buffers for update packets as they wont be\n\t * counted in num_tx_total.\n\t */\n\tstruct rte_mbuf *update_bufs[RTE_MAX_ETHPORTS][ALB_HASH_TABLE_SIZE];\n\tuint16_t update_bufs_pkts[RTE_MAX_ETHPORTS] = { 0 };\n\n\tstruct rte_mbuf *upd_pkt;\n\tsize_t pkt_size;\n\n\tuint16_t num_send, num_not_send = 0;\n\tuint16_t num_tx_total = 0;\n\tuint8_t slave_idx;\n\n\tint i, j;\n\n\t/* Search tx buffer for ARP packets and forward them to alb */\n\tfor (i = 0; i < nb_pkts; i++) {\n\t\teth_h = rte_pktmbuf_mtod(bufs[i], struct ether_hdr *);\n\t\tether_type = eth_h->ether_type;\n\t\toffset = get_vlan_offset(eth_h, ðer_type);\n\n\t\tif (ether_type == rte_cpu_to_be_16(ETHER_TYPE_ARP)) {\n\t\t\tslave_idx = bond_mode_alb_arp_xmit(eth_h, offset, internals);\n\n\t\t\t/* Change src mac in eth header */\n\t\t\trte_eth_macaddr_get(slave_idx, ð_h->s_addr);\n\n\t\t\t/* Add packet to slave tx buffer */\n\t\t\tslave_bufs[slave_idx][slave_bufs_pkts[slave_idx]] = bufs[i];\n\t\t\tslave_bufs_pkts[slave_idx]++;\n\t\t} else {\n\t\t\t/* If packet is not ARP, send it with TLB policy */\n\t\t\tslave_bufs[RTE_MAX_ETHPORTS][slave_bufs_pkts[RTE_MAX_ETHPORTS]] =\n\t\t\t\t\tbufs[i];\n\t\t\tslave_bufs_pkts[RTE_MAX_ETHPORTS]++;\n\t\t}\n\t}\n\n\t/* Update connected client ARP tables */\n\tif (internals->mode6.ntt) {\n\t\tfor (i = 0; i < ALB_HASH_TABLE_SIZE; i++) {\n\t\t\tclient_info = &internals->mode6.client_table[i];\n\n\t\t\tif (client_info->in_use) {\n\t\t\t\t/* Allocate new packet to send ARP update on current slave */\n\t\t\t\tupd_pkt = rte_pktmbuf_alloc(internals->mode6.mempool);\n\t\t\t\tif (upd_pkt == NULL) {\n\t\t\t\t\tRTE_LOG(ERR, PMD, \"Failed to allocate ARP packet from pool\\n\");\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tpkt_size = sizeof(struct ether_hdr) + sizeof(struct arp_hdr)\n\t\t\t\t\t\t+ client_info->vlan_count * sizeof(struct vlan_hdr);\n\t\t\t\tupd_pkt->data_len = pkt_size;\n\t\t\t\tupd_pkt->pkt_len = pkt_size;\n\n\t\t\t\tslave_idx = bond_mode_alb_arp_upd(client_info, upd_pkt,\n\t\t\t\t\t\tinternals);\n\n\t\t\t\t/* Add packet to update tx buffer */\n\t\t\t\tupdate_bufs[slave_idx][update_bufs_pkts[slave_idx]] = upd_pkt;\n\t\t\t\tupdate_bufs_pkts[slave_idx]++;\n\t\t\t}\n\t\t}\n\t\tinternals->mode6.ntt = 0;\n\t}\n\n\t/* Send ARP packets on proper slaves */\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif (slave_bufs_pkts[i] > 0) {\n\t\t\tnum_send = rte_eth_tx_burst(i, bd_tx_q->queue_id,\n\t\t\t\t\tslave_bufs[i], slave_bufs_pkts[i]);\n\t\t\tfor (j = 0; j < slave_bufs_pkts[i] - num_send; j++) {\n\t\t\t\tbufs[nb_pkts - 1 - num_not_send - j] =\n\t\t\t\t\t\tslave_bufs[i][nb_pkts - 1 - j];\n\t\t\t}\n\n\t\t\tnum_tx_total += num_send;\n\t\t\tnum_not_send += slave_bufs_pkts[i] - num_send;\n\n#if defined(RTE_LIBRTE_BOND_DEBUG_ALB) || defined(RTE_LIBRTE_BOND_DEBUG_ALB_L1)\n\t/* Print TX stats including update packets */\n\t\t\tfor (j = 0; j < slave_bufs_pkts[i]; j++) {\n\t\t\t\teth_h = rte_pktmbuf_mtod(slave_bufs[i][j], struct ether_hdr *);\n\t\t\t\tmode6_debug(\"TX ARP:\", eth_h, i, &burstnumberTX);\n\t\t\t}\n#endif\n\t\t}\n\t}\n\n\t/* Send update packets on proper slaves */\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif (update_bufs_pkts[i] > 0) {\n\t\t\tnum_send = rte_eth_tx_burst(i, bd_tx_q->queue_id, update_bufs[i],\n\t\t\t\t\tupdate_bufs_pkts[i]);\n\t\t\tfor (j = num_send; j < update_bufs_pkts[i]; j++) {\n\t\t\t\trte_pktmbuf_free(update_bufs[i][j]);\n\t\t\t}\n#if defined(RTE_LIBRTE_BOND_DEBUG_ALB) || defined(RTE_LIBRTE_BOND_DEBUG_ALB_L1)\n\t\t\tfor (j = 0; j < update_bufs_pkts[i]; j++) {\n\t\t\t\teth_h = rte_pktmbuf_mtod(update_bufs[i][j], struct ether_hdr *);\n\t\t\t\tmode6_debug(\"TX ARPupd:\", eth_h, i, &burstnumberTX);\n\t\t\t}\n#endif\n\t\t}\n\t}\n\n\t/* Send non-ARP packets using tlb policy */\n\tif (slave_bufs_pkts[RTE_MAX_ETHPORTS] > 0) {\n\t\tnum_send = bond_ethdev_tx_burst_tlb(queue,\n\t\t\t\tslave_bufs[RTE_MAX_ETHPORTS],\n\t\t\t\tslave_bufs_pkts[RTE_MAX_ETHPORTS]);\n\n\t\tfor (j = 0; j < slave_bufs_pkts[RTE_MAX_ETHPORTS]; j++) {\n\t\t\tbufs[nb_pkts - 1 - num_not_send - j] =\n\t\t\t\t\tslave_bufs[RTE_MAX_ETHPORTS][nb_pkts - 1 - j];\n\t\t}\n\n\t\tnum_tx_total += num_send;\n\t\tnum_not_send += slave_bufs_pkts[RTE_MAX_ETHPORTS] - num_send;\n\t}\n\n\treturn num_tx_total;\n}\n\nstatic uint16_t\nbond_ethdev_tx_burst_balance(void *queue, struct rte_mbuf **bufs,\n\t\tuint16_t nb_pkts)\n{\n\tstruct bond_dev_private *internals;\n\tstruct bond_tx_queue *bd_tx_q;\n\n\tuint8_t num_of_slaves;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tuint16_t num_tx_total = 0, num_tx_slave = 0, tx_fail_total = 0;\n\n\tint i, op_slave_id;\n\n\tstruct rte_mbuf *slave_bufs[RTE_MAX_ETHPORTS][nb_pkts];\n\tuint16_t slave_nb_pkts[RTE_MAX_ETHPORTS] = { 0 };\n\n\tbd_tx_q = (struct bond_tx_queue *)queue;\n\tinternals = bd_tx_q->dev_private;\n\n\t/* Copy slave list to protect against slave up/down changes during tx\n\t * bursting */\n\tnum_of_slaves = internals->active_slave_count;\n\tmemcpy(slaves, internals->active_slaves,\n\t\t\tsizeof(internals->active_slaves[0]) * num_of_slaves);\n\n\tif (num_of_slaves < 1)\n\t\treturn num_tx_total;\n\n\t/* Populate slaves mbuf with the packets which are to be sent on it */\n\tfor (i = 0; i < nb_pkts; i++) {\n\t\t/* Select output slave using hash based on xmit policy */\n\t\top_slave_id = internals->xmit_hash(bufs[i], num_of_slaves);\n\n\t\t/* Populate slave mbuf arrays with mbufs for that slave */\n\t\tslave_bufs[op_slave_id][slave_nb_pkts[op_slave_id]++] = bufs[i];\n\t}\n\n\t/* Send packet burst on each slave device */\n\tfor (i = 0; i < num_of_slaves; i++) {\n\t\tif (slave_nb_pkts[i] > 0) {\n\t\t\tnum_tx_slave = rte_eth_tx_burst(slaves[i], bd_tx_q->queue_id,\n\t\t\t\t\tslave_bufs[i], slave_nb_pkts[i]);\n\n\t\t\t/* if tx burst fails move packets to end of bufs */\n\t\t\tif (unlikely(num_tx_slave < slave_nb_pkts[i])) {\n\t\t\t\tint slave_tx_fail_count = slave_nb_pkts[i] - num_tx_slave;\n\n\t\t\t\ttx_fail_total += slave_tx_fail_count;\n\t\t\t\tmemcpy(&bufs[nb_pkts - tx_fail_total],\n\t\t\t\t\t\t&slave_bufs[i][num_tx_slave],\n\t\t\t\t\t\tslave_tx_fail_count * sizeof(bufs[0]));\n\t\t\t}\n\n\t\t\tnum_tx_total += num_tx_slave;\n\t\t}\n\t}\n\n\treturn num_tx_total;\n}\n\nstatic uint16_t\nbond_ethdev_tx_burst_8023ad(void *queue, struct rte_mbuf **bufs,\n\t\tuint16_t nb_pkts)\n{\n\tstruct bond_dev_private *internals;\n\tstruct bond_tx_queue *bd_tx_q;\n\n\tuint8_t num_of_slaves;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\t /* positions in slaves, not ID */\n\tuint8_t distributing_offsets[RTE_MAX_ETHPORTS];\n\tuint8_t distributing_count;\n\n\tuint16_t num_tx_slave, num_tx_total = 0, num_tx_fail_total = 0;\n\tuint16_t i, j, op_slave_idx;\n\tconst uint16_t buffs_size = nb_pkts + BOND_MODE_8023AX_SLAVE_TX_PKTS + 1;\n\n\t/* Allocate additional packets in case 8023AD mode. */\n\tstruct rte_mbuf *slave_bufs[RTE_MAX_ETHPORTS][buffs_size];\n\tvoid *slow_pkts[BOND_MODE_8023AX_SLAVE_TX_PKTS] = { NULL };\n\n\t/* Total amount of packets in slave_bufs */\n\tuint16_t slave_nb_pkts[RTE_MAX_ETHPORTS] = { 0 };\n\t/* Slow packets placed in each slave */\n\tuint8_t slave_slow_nb_pkts[RTE_MAX_ETHPORTS] = { 0 };\n\n\tbd_tx_q = (struct bond_tx_queue *)queue;\n\tinternals = bd_tx_q->dev_private;\n\n\t/* Copy slave list to protect against slave up/down changes during tx\n\t * bursting */\n\tnum_of_slaves = internals->active_slave_count;\n\tif (num_of_slaves < 1)\n\t\treturn num_tx_total;\n\n\tmemcpy(slaves, internals->active_slaves, sizeof(slaves[0]) * num_of_slaves);\n\n\tdistributing_count = 0;\n\tfor (i = 0; i < num_of_slaves; i++) {\n\t\tstruct port *port = &mode_8023ad_ports[slaves[i]];\n\n\t\tslave_slow_nb_pkts[i] = rte_ring_dequeue_burst(port->tx_ring,\n\t\t\t\tslow_pkts, BOND_MODE_8023AX_SLAVE_TX_PKTS);\n\t\tslave_nb_pkts[i] = slave_slow_nb_pkts[i];\n\n\t\tfor (j = 0; j < slave_slow_nb_pkts[i]; j++)\n\t\t\tslave_bufs[i][j] = slow_pkts[j];\n\n\t\tif (ACTOR_STATE(port, DISTRIBUTING))\n\t\t\tdistributing_offsets[distributing_count++] = i;\n\t}\n\n\tif (likely(distributing_count > 0)) {\n\t\t/* Populate slaves mbuf with the packets which are to be sent on it */\n\t\tfor (i = 0; i < nb_pkts; i++) {\n\t\t\t/* Select output slave using hash based on xmit policy */\n\t\t\top_slave_idx = internals->xmit_hash(bufs[i], distributing_count);\n\n\t\t\t/* Populate slave mbuf arrays with mbufs for that slave. Use only\n\t\t\t * slaves that are currently distributing. */\n\t\t\tuint8_t slave_offset = distributing_offsets[op_slave_idx];\n\t\t\tslave_bufs[slave_offset][slave_nb_pkts[slave_offset]] = bufs[i];\n\t\t\tslave_nb_pkts[slave_offset]++;\n\t\t}\n\t}\n\n\t/* Send packet burst on each slave device */\n\tfor (i = 0; i < num_of_slaves; i++) {\n\t\tif (slave_nb_pkts[i] == 0)\n\t\t\tcontinue;\n\n\t\tnum_tx_slave = rte_eth_tx_burst(slaves[i], bd_tx_q->queue_id,\n\t\t\t\tslave_bufs[i], slave_nb_pkts[i]);\n\n\t\t/* If tx burst fails drop slow packets */\n\t\tfor ( ; num_tx_slave < slave_slow_nb_pkts[i]; num_tx_slave++)\n\t\t\trte_pktmbuf_free(slave_bufs[i][num_tx_slave]);\n\n\t\tnum_tx_total += num_tx_slave - slave_slow_nb_pkts[i];\n\t\tnum_tx_fail_total += slave_nb_pkts[i] - num_tx_slave;\n\n\t\t/* If tx burst fails move packets to end of bufs */\n\t\tif (unlikely(num_tx_slave < slave_nb_pkts[i])) {\n\t\t\tuint16_t j = nb_pkts - num_tx_fail_total;\n\t\t\tfor ( ; num_tx_slave < slave_nb_pkts[i]; j++, num_tx_slave++)\n\t\t\t\tbufs[j] = slave_bufs[i][num_tx_slave];\n\t\t}\n\t}\n\n\treturn num_tx_total;\n}\n\nstatic uint16_t\nbond_ethdev_tx_burst_broadcast(void *queue, struct rte_mbuf **bufs,\n\t\tuint16_t nb_pkts)\n{\n\tstruct bond_dev_private *internals;\n\tstruct bond_tx_queue *bd_tx_q;\n\n\tuint8_t tx_failed_flag = 0, num_of_slaves;\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\n\n\tuint16_t max_nb_of_tx_pkts = 0;\n\n\tint slave_tx_total[RTE_MAX_ETHPORTS];\n\tint i, most_successful_tx_slave = -1;\n\n\tbd_tx_q = (struct bond_tx_queue *)queue;\n\tinternals = bd_tx_q->dev_private;\n\n\t/* Copy slave list to protect against slave up/down changes during tx\n\t * bursting */\n\tnum_of_slaves = internals->active_slave_count;\n\tmemcpy(slaves, internals->active_slaves,\n\t\t\tsizeof(internals->active_slaves[0]) * num_of_slaves);\n\n\tif (num_of_slaves < 1)\n\t\treturn 0;\n\n\t/* Increment reference count on mbufs */\n\tfor (i = 0; i < nb_pkts; i++)\n\t\trte_mbuf_refcnt_update(bufs[i], num_of_slaves - 1);\n\n\t/* Transmit burst on each active slave */\n\tfor (i = 0; i < num_of_slaves; i++) {\n\t\tslave_tx_total[i] = rte_eth_tx_burst(slaves[i], bd_tx_q->queue_id,\n\t\t\t\t\tbufs, nb_pkts);\n\n\t\tif (unlikely(slave_tx_total[i] < nb_pkts))\n\t\t\ttx_failed_flag = 1;\n\n\t\t/* record the value and slave index for the slave which transmits the\n\t\t * maximum number of packets */\n\t\tif (slave_tx_total[i] > max_nb_of_tx_pkts) {\n\t\t\tmax_nb_of_tx_pkts = slave_tx_total[i];\n\t\t\tmost_successful_tx_slave = i;\n\t\t}\n\t}\n\n\t/* if slaves fail to transmit packets from burst, the calling application\n\t * is not expected to know about multiple references to packets so we must\n\t * handle failures of all packets except those of the most successful slave\n\t */\n\tif (unlikely(tx_failed_flag))\n\t\tfor (i = 0; i < num_of_slaves; i++)\n\t\t\tif (i != most_successful_tx_slave)\n\t\t\t\twhile (slave_tx_total[i] < nb_pkts)\n\t\t\t\t\trte_pktmbuf_free(bufs[slave_tx_total[i]++]);\n\n\treturn max_nb_of_tx_pkts;\n}\n\nvoid\nlink_properties_set(struct rte_eth_dev *bonded_eth_dev,\n\t\tstruct rte_eth_link *slave_dev_link)\n{\n\tstruct rte_eth_link *bonded_dev_link = &bonded_eth_dev->data->dev_link;\n\tstruct bond_dev_private *internals = bonded_eth_dev->data->dev_private;\n\n\tif (slave_dev_link->link_status &&\n\t\tbonded_eth_dev->data->dev_started) {\n\t\tbonded_dev_link->link_duplex = slave_dev_link->link_duplex;\n\t\tbonded_dev_link->link_speed = slave_dev_link->link_speed;\n\n\t\tinternals->link_props_set = 1;\n\t}\n}\n\nvoid\nlink_properties_reset(struct rte_eth_dev *bonded_eth_dev)\n{\n\tstruct bond_dev_private *internals = bonded_eth_dev->data->dev_private;\n\n\tmemset(&(bonded_eth_dev->data->dev_link), 0,\n\t\t\tsizeof(bonded_eth_dev->data->dev_link));\n\n\tinternals->link_props_set = 0;\n}\n\nint\nlink_properties_valid(struct rte_eth_link *bonded_dev_link,\n\t\tstruct rte_eth_link *slave_dev_link)\n{\n\tif (bonded_dev_link->link_duplex != slave_dev_link->link_duplex ||\n\t\tbonded_dev_link->link_speed != slave_dev_link->link_speed)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nint\nmac_address_get(struct rte_eth_dev *eth_dev, struct ether_addr *dst_mac_addr)\n{\n\tstruct ether_addr *mac_addr;\n\n\tif (eth_dev == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"%s: NULL pointer eth_dev specified\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\tif (dst_mac_addr == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"%s: NULL pointer MAC specified\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\tmac_addr = eth_dev->data->mac_addrs;\n\n\tether_addr_copy(mac_addr, dst_mac_addr);\n\treturn 0;\n}\n\nint\nmac_address_set(struct rte_eth_dev *eth_dev, struct ether_addr *new_mac_addr)\n{\n\tstruct ether_addr *mac_addr;\n\n\tif (eth_dev == NULL) {\n\t\tRTE_BOND_LOG(ERR, \"NULL pointer eth_dev specified\");\n\t\treturn -1;\n\t}\n\n\tif (new_mac_addr == NULL) {\n\t\tRTE_BOND_LOG(ERR, \"NULL pointer MAC specified\");\n\t\treturn -1;\n\t}\n\n\tmac_addr = eth_dev->data->mac_addrs;\n\n\t/* If new MAC is different to current MAC then update */\n\tif (memcmp(mac_addr, new_mac_addr, sizeof(*mac_addr)) != 0)\n\t\tmemcpy(mac_addr, new_mac_addr, sizeof(*mac_addr));\n\n\treturn 0;\n}\n\nint\nmac_address_slaves_update(struct rte_eth_dev *bonded_eth_dev)\n{\n\tstruct bond_dev_private *internals = bonded_eth_dev->data->dev_private;\n\tint i;\n\n\t/* Update slave devices MAC addresses */\n\tif (internals->slave_count < 1)\n\t\treturn -1;\n\n\tswitch (internals->mode) {\n\tcase BONDING_MODE_ROUND_ROBIN:\n\tcase BONDING_MODE_BALANCE:\n\tcase BONDING_MODE_BROADCAST:\n\t\tfor (i = 0; i < internals->slave_count; i++) {\n\t\t\tif (mac_address_set(&rte_eth_devices[internals->slaves[i].port_id],\n\t\t\t\t\tbonded_eth_dev->data->mac_addrs)) {\n\t\t\t\tRTE_BOND_LOG(ERR, \"Failed to update port Id %d MAC address\",\n\t\t\t\t\t\tinternals->slaves[i].port_id);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tcase BONDING_MODE_8023AD:\n\t\tbond_mode_8023ad_mac_address_update(bonded_eth_dev);\n\t\tbreak;\n\tcase BONDING_MODE_ACTIVE_BACKUP:\n\tcase BONDING_MODE_TLB:\n\tcase BONDING_MODE_ALB:\n\tdefault:\n\t\tfor (i = 0; i < internals->slave_count; i++) {\n\t\t\tif (internals->slaves[i].port_id ==\n\t\t\t\t\tinternals->current_primary_port) {\n\t\t\t\tif (mac_address_set(&rte_eth_devices[internals->primary_port],\n\t\t\t\t\t\tbonded_eth_dev->data->mac_addrs)) {\n\t\t\t\t\tRTE_BOND_LOG(ERR, \"Failed to update port Id %d MAC address\",\n\t\t\t\t\t\t\tinternals->current_primary_port);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (mac_address_set(\n\t\t\t\t\t\t&rte_eth_devices[internals->slaves[i].port_id],\n\t\t\t\t\t\t&internals->slaves[i].persisted_mac_addr)) {\n\t\t\t\t\tRTE_BOND_LOG(ERR, \"Failed to update port Id %d MAC address\",\n\t\t\t\t\t\t\tinternals->slaves[i].port_id);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nint\nbond_ethdev_mode_set(struct rte_eth_dev *eth_dev, int mode)\n{\n\tstruct bond_dev_private *internals;\n\n\tinternals = eth_dev->data->dev_private;\n\n\tswitch (mode) {\n\tcase BONDING_MODE_ROUND_ROBIN:\n\t\teth_dev->tx_pkt_burst = bond_ethdev_tx_burst_round_robin;\n\t\teth_dev->rx_pkt_burst = bond_ethdev_rx_burst;\n\t\tbreak;\n\tcase BONDING_MODE_ACTIVE_BACKUP:\n\t\teth_dev->tx_pkt_burst = bond_ethdev_tx_burst_active_backup;\n\t\teth_dev->rx_pkt_burst = bond_ethdev_rx_burst_active_backup;\n\t\tbreak;\n\tcase BONDING_MODE_BALANCE:\n\t\teth_dev->tx_pkt_burst = bond_ethdev_tx_burst_balance;\n\t\teth_dev->rx_pkt_burst = bond_ethdev_rx_burst;\n\t\tbreak;\n\tcase BONDING_MODE_BROADCAST:\n\t\teth_dev->tx_pkt_burst = bond_ethdev_tx_burst_broadcast;\n\t\teth_dev->rx_pkt_burst = bond_ethdev_rx_burst;\n\t\tbreak;\n\tcase BONDING_MODE_8023AD:\n\t\tif (bond_mode_8023ad_enable(eth_dev) != 0)\n\t\t\treturn -1;\n\n\t\teth_dev->rx_pkt_burst = bond_ethdev_rx_burst_8023ad;\n\t\teth_dev->tx_pkt_burst = bond_ethdev_tx_burst_8023ad;\n\t\tRTE_LOG(WARNING, PMD,\n\t\t\t\t\"Using mode 4, it is necessary to do TX burst and RX burst \"\n\t\t\t\t\"at least every 100ms.\\n\");\n\t\tbreak;\n\tcase BONDING_MODE_TLB:\n\t\teth_dev->tx_pkt_burst = bond_ethdev_tx_burst_tlb;\n\t\teth_dev->rx_pkt_burst = bond_ethdev_rx_burst_active_backup;\n\t\tbreak;\n\tcase BONDING_MODE_ALB:\n\t\tif (bond_mode_alb_enable(eth_dev) != 0)\n\t\t\treturn -1;\n\n\t\teth_dev->tx_pkt_burst = bond_ethdev_tx_burst_alb;\n\t\teth_dev->rx_pkt_burst = bond_ethdev_rx_burst_alb;\n\t\tbreak;\n\tdefault:\n\t\treturn -1;\n\t}\n\n\tinternals->mode = mode;\n\n\treturn 0;\n}\n\nint\nslave_configure(struct rte_eth_dev *bonded_eth_dev,\n\t\tstruct rte_eth_dev *slave_eth_dev)\n{\n\tstruct bond_rx_queue *bd_rx_q;\n\tstruct bond_tx_queue *bd_tx_q;\n\n\tint errval;\n\tuint16_t q_id;\n\n\t/* Stop slave */\n\trte_eth_dev_stop(slave_eth_dev->data->port_id);\n\n\t/* Enable interrupts on slave device if supported */\n\tif (slave_eth_dev->driver->pci_drv.drv_flags & RTE_PCI_DRV_INTR_LSC)\n\t\tslave_eth_dev->data->dev_conf.intr_conf.lsc = 1;\n\n\t/* Configure device */\n\terrval = rte_eth_dev_configure(slave_eth_dev->data->port_id,\n\t\t\tbonded_eth_dev->data->nb_rx_queues,\n\t\t\tbonded_eth_dev->data->nb_tx_queues,\n\t\t\t&(slave_eth_dev->data->dev_conf));\n\tif (errval != 0) {\n\t\tRTE_BOND_LOG(ERR, \"Cannot configure slave device: port %u , err (%d)\",\n\t\t\t\tslave_eth_dev->data->port_id, errval);\n\t\treturn errval;\n\t}\n\n\t/* Setup Rx Queues */\n\tfor (q_id = 0; q_id < bonded_eth_dev->data->nb_rx_queues; q_id++) {\n\t\tbd_rx_q = (struct bond_rx_queue *)bonded_eth_dev->data->rx_queues[q_id];\n\n\t\terrval = rte_eth_rx_queue_setup(slave_eth_dev->data->port_id, q_id,\n\t\t\t\tbd_rx_q->nb_rx_desc,\n\t\t\t\trte_eth_dev_socket_id(slave_eth_dev->data->port_id),\n\t\t\t\t&(bd_rx_q->rx_conf), bd_rx_q->mb_pool);\n\t\tif (errval != 0) {\n\t\t\tRTE_BOND_LOG(ERR,\n\t\t\t\t\t\"rte_eth_rx_queue_setup: port=%d queue_id %d, err (%d)\",\n\t\t\t\t\tslave_eth_dev->data->port_id, q_id, errval);\n\t\t\treturn errval;\n\t\t}\n\t}\n\n\t/* Setup Tx Queues */\n\tfor (q_id = 0; q_id < bonded_eth_dev->data->nb_tx_queues; q_id++) {\n\t\tbd_tx_q = (struct bond_tx_queue *)bonded_eth_dev->data->tx_queues[q_id];\n\n\t\terrval = rte_eth_tx_queue_setup(slave_eth_dev->data->port_id, q_id,\n\t\t\t\tbd_tx_q->nb_tx_desc,\n\t\t\t\trte_eth_dev_socket_id(slave_eth_dev->data->port_id),\n\t\t\t\t&bd_tx_q->tx_conf);\n\t\tif (errval != 0) {\n\t\t\tRTE_BOND_LOG(ERR,\n\t\t\t\t\t\"rte_eth_tx_queue_setup: port=%d queue_id %d, err (%d)\",\n\t\t\t\t\tslave_eth_dev->data->port_id, q_id, errval);\n\t\t\treturn errval;\n\t\t}\n\t}\n\n\t/* Start device */\n\terrval = rte_eth_dev_start(slave_eth_dev->data->port_id);\n\tif (errval != 0) {\n\t\tRTE_BOND_LOG(ERR, \"rte_eth_dev_start: port=%u, err (%d)\",\n\t\t\t\tslave_eth_dev->data->port_id, errval);\n\t\treturn -1;\n\t}\n\n\t/* If lsc interrupt is set, check initial slave's link status */\n\tif (slave_eth_dev->driver->pci_drv.drv_flags & RTE_PCI_DRV_INTR_LSC)\n\t\tbond_ethdev_lsc_event_callback(slave_eth_dev->data->port_id,\n\t\t\t\tRTE_ETH_EVENT_INTR_LSC, &bonded_eth_dev->data->port_id);\n\n\treturn 0;\n}\n\nvoid\nslave_remove(struct bond_dev_private *internals,\n\t\tstruct rte_eth_dev *slave_eth_dev)\n{\n\tuint8_t i;\n\n\tfor (i = 0; i < internals->slave_count; i++)\n\t\tif (internals->slaves[i].port_id ==\n\t\t\t\tslave_eth_dev->data->port_id)\n\t\t\tbreak;\n\n\tif (i < (internals->slave_count - 1))\n\t\tmemmove(&internals->slaves[i], &internals->slaves[i + 1],\n\t\t\t\tsizeof(internals->slaves[0]) *\n\t\t\t\t(internals->slave_count - i - 1));\n\n\tinternals->slave_count--;\n}\n\nstatic void\nbond_ethdev_slave_link_status_change_monitor(void *cb_arg);\n\nvoid\nslave_add(struct bond_dev_private *internals,\n\t\tstruct rte_eth_dev *slave_eth_dev)\n{\n\tstruct bond_slave_details *slave_details =\n\t\t\t&internals->slaves[internals->slave_count];\n\n\tslave_details->port_id = slave_eth_dev->data->port_id;\n\tslave_details->last_link_status = 0;\n\n\t/* If slave device doesn't support interrupts then we need to enabled\n\t * polling to monitor link status */\n\tif (!(slave_eth_dev->pci_dev->driver->drv_flags & RTE_PCI_DRV_INTR_LSC)) {\n\t\tslave_details->link_status_poll_enabled = 1;\n\n\t\tif (!internals->link_status_polling_enabled) {\n\t\t\tinternals->link_status_polling_enabled = 1;\n\n\t\t\trte_eal_alarm_set(internals->link_status_polling_interval_ms * 1000,\n\t\t\t\t\tbond_ethdev_slave_link_status_change_monitor,\n\t\t\t\t\t(void *)&rte_eth_devices[internals->port_id]);\n\t\t}\n\t}\n\n\tslave_details->link_status_wait_to_complete = 0;\n\t/* clean tlb_last_obytes when adding port for bonding device */\n\tmemcpy(&(slave_details->persisted_mac_addr), slave_eth_dev->data->mac_addrs,\n\t\t\tsizeof(struct ether_addr));\n}\n\nvoid\nbond_ethdev_primary_set(struct bond_dev_private *internals,\n\t\tuint8_t slave_port_id)\n{\n\tint i;\n\n\tif (internals->active_slave_count < 1)\n\t\tinternals->current_primary_port = slave_port_id;\n\telse\n\t\t/* Search bonded device slave ports for new proposed primary port */\n\t\tfor (i = 0; i < internals->active_slave_count; i++) {\n\t\t\tif (internals->active_slaves[i] == slave_port_id)\n\t\t\t\tinternals->current_primary_port = slave_port_id;\n\t\t}\n}\n\nstatic void\nbond_ethdev_promiscuous_enable(struct rte_eth_dev *eth_dev);\n\nstatic int\nbond_ethdev_start(struct rte_eth_dev *eth_dev)\n{\n\tstruct bond_dev_private *internals;\n\tint i;\n\n\t/* slave eth dev will be started by bonded device */\n\tif (valid_bonded_ethdev(eth_dev)) {\n\t\tRTE_BOND_LOG(ERR, \"User tried to explicitly start a slave eth_dev (%d)\",\n\t\t\t\teth_dev->data->port_id);\n\t\treturn -1;\n\t}\n\n\teth_dev->data->dev_link.link_status = 0;\n\teth_dev->data->dev_started = 1;\n\n\tinternals = eth_dev->data->dev_private;\n\n\tif (internals->slave_count == 0) {\n\t\tRTE_BOND_LOG(ERR, \"Cannot start port since there are no slave devices\");\n\t\treturn -1;\n\t}\n\n\tif (internals->user_defined_mac == 0) {\n\t\tstruct ether_addr *new_mac_addr = NULL;\n\n\t\tfor (i = 0; i < internals->slave_count; i++)\n\t\t\tif (internals->slaves[i].port_id == internals->primary_port)\n\t\t\t\tnew_mac_addr = &internals->slaves[i].persisted_mac_addr;\n\n\t\tif (new_mac_addr == NULL)\n\t\t\treturn -1;\n\n\t\tif (mac_address_set(eth_dev, new_mac_addr) != 0) {\n\t\t\tRTE_BOND_LOG(ERR, \"bonded port (%d) failed to update MAC address\",\n\t\t\t\t\teth_dev->data->port_id);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* Update all slave devices MACs*/\n\tif (mac_address_slaves_update(eth_dev) != 0)\n\t\treturn -1;\n\n\t/* If bonded device is configure in promiscuous mode then re-apply config */\n\tif (internals->promiscuous_en)\n\t\tbond_ethdev_promiscuous_enable(eth_dev);\n\n\t/* Reconfigure each slave device if starting bonded device */\n\tfor (i = 0; i < internals->slave_count; i++) {\n\t\tif (slave_configure(eth_dev,\n\t\t\t\t&(rte_eth_devices[internals->slaves[i].port_id])) != 0) {\n\t\t\tRTE_BOND_LOG(ERR,\n\t\t\t\t\t\"bonded port (%d) failed to reconfigure slave device (%d)\",\n\t\t\t\t\teth_dev->data->port_id, internals->slaves[i].port_id);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (internals->user_defined_primary_port)\n\t\tbond_ethdev_primary_set(internals, internals->primary_port);\n\n\tif (internals->mode == BONDING_MODE_8023AD)\n\t\tbond_mode_8023ad_start(eth_dev);\n\n\tif (internals->mode == BONDING_MODE_TLB ||\n\t\t\tinternals->mode == BONDING_MODE_ALB)\n\t\tbond_tlb_enable(internals);\n\n\treturn 0;\n}\n\nstatic void\nbond_ethdev_free_queues(struct rte_eth_dev *dev)\n{\n\tuint8_t i;\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\trte_free(dev->data->rx_queues[i]);\n\t\tdev->data->rx_queues[i] = NULL;\n\t}\n\tdev->data->nb_rx_queues = 0;\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\trte_free(dev->data->tx_queues[i]);\n\t\tdev->data->tx_queues[i] = NULL;\n\t}\n\tdev->data->nb_tx_queues = 0;\n}\n\nvoid\nbond_ethdev_stop(struct rte_eth_dev *eth_dev)\n{\n\tstruct bond_dev_private *internals = eth_dev->data->dev_private;\n\tuint8_t i;\n\n\tif (internals->mode == BONDING_MODE_8023AD) {\n\t\tstruct port *port;\n\t\tvoid *pkt = NULL;\n\n\t\tbond_mode_8023ad_stop(eth_dev);\n\n\t\t/* Discard all messages to/from mode 4 state machines */\n\t\tfor (i = 0; i < internals->active_slave_count; i++) {\n\t\t\tport = &mode_8023ad_ports[internals->active_slaves[i]];\n\n\t\t\tRTE_VERIFY(port->rx_ring != NULL);\n\t\t\twhile (rte_ring_dequeue(port->rx_ring, &pkt) != -ENOENT)\n\t\t\t\trte_pktmbuf_free(pkt);\n\n\t\t\tRTE_VERIFY(port->tx_ring != NULL);\n\t\t\twhile (rte_ring_dequeue(port->tx_ring, &pkt) != -ENOENT)\n\t\t\t\trte_pktmbuf_free(pkt);\n\t\t}\n\t}\n\n\tif (internals->mode == BONDING_MODE_TLB ||\n\t\t\tinternals->mode == BONDING_MODE_ALB) {\n\t\tbond_tlb_disable(internals);\n\t\tfor (i = 0; i < internals->active_slave_count; i++)\n\t\t\ttlb_last_obytets[internals->active_slaves[i]] = 0;\n\t}\n\n\tinternals->active_slave_count = 0;\n\tinternals->link_status_polling_enabled = 0;\n\n\teth_dev->data->dev_link.link_status = 0;\n\teth_dev->data->dev_started = 0;\n}\n\nvoid\nbond_ethdev_close(struct rte_eth_dev *dev)\n{\n\tbond_ethdev_free_queues(dev);\n}\n\n/* forward declaration */\nstatic int bond_ethdev_configure(struct rte_eth_dev *dev);\n\nstatic void\nbond_ethdev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n{\n\tstruct bond_dev_private *internals = dev->data->dev_private;\n\n\tdev_info->max_mac_addrs = 1;\n\n\tdev_info->max_rx_pktlen = (uint32_t)2048;\n\n\tdev_info->max_rx_queues = (uint16_t)128;\n\tdev_info->max_tx_queues = (uint16_t)512;\n\n\tdev_info->min_rx_bufsize = 0;\n\tdev_info->pci_dev = dev->pci_dev;\n\n\tdev_info->rx_offload_capa = internals->rx_offload_capa;\n\tdev_info->tx_offload_capa = internals->tx_offload_capa;\n}\n\nstatic int\nbond_ethdev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n\t\tuint16_t nb_rx_desc, unsigned int socket_id __rte_unused,\n\t\tconst struct rte_eth_rxconf *rx_conf, struct rte_mempool *mb_pool)\n{\n\tstruct bond_rx_queue *bd_rx_q = (struct bond_rx_queue *)\n\t\t\trte_zmalloc_socket(NULL, sizeof(struct bond_rx_queue),\n\t\t\t\t\t0, dev->pci_dev->numa_node);\n\tif (bd_rx_q == NULL)\n\t\treturn -1;\n\n\tbd_rx_q->queue_id = rx_queue_id;\n\tbd_rx_q->dev_private = dev->data->dev_private;\n\n\tbd_rx_q->nb_rx_desc = nb_rx_desc;\n\n\tmemcpy(&(bd_rx_q->rx_conf), rx_conf, sizeof(struct rte_eth_rxconf));\n\tbd_rx_q->mb_pool = mb_pool;\n\n\tdev->data->rx_queues[rx_queue_id] = bd_rx_q;\n\n\treturn 0;\n}\n\nstatic int\nbond_ethdev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n\t\tuint16_t nb_tx_desc, unsigned int socket_id __rte_unused,\n\t\tconst struct rte_eth_txconf *tx_conf)\n{\n\tstruct bond_tx_queue *bd_tx_q = (struct bond_tx_queue *)\n\t\t\trte_zmalloc_socket(NULL, sizeof(struct bond_tx_queue),\n\t\t\t\t\t0, dev->pci_dev->numa_node);\n\n\tif (bd_tx_q == NULL)\n\t\treturn -1;\n\n\tbd_tx_q->queue_id = tx_queue_id;\n\tbd_tx_q->dev_private = dev->data->dev_private;\n\n\tbd_tx_q->nb_tx_desc = nb_tx_desc;\n\tmemcpy(&(bd_tx_q->tx_conf), tx_conf, sizeof(bd_tx_q->tx_conf));\n\n\tdev->data->tx_queues[tx_queue_id] = bd_tx_q;\n\n\treturn 0;\n}\n\nstatic void\nbond_ethdev_rx_queue_release(void *queue)\n{\n\tif (queue == NULL)\n\t\treturn;\n\n\trte_free(queue);\n}\n\nstatic void\nbond_ethdev_tx_queue_release(void *queue)\n{\n\tif (queue == NULL)\n\t\treturn;\n\n\trte_free(queue);\n}\n\nstatic void\nbond_ethdev_slave_link_status_change_monitor(void *cb_arg)\n{\n\tstruct rte_eth_dev *bonded_ethdev, *slave_ethdev;\n\tstruct bond_dev_private *internals;\n\n\t/* Default value for polling slave found is true as we don't want to\n\t * disable the polling thread if we cannot get the lock */\n\tint i, polling_slave_found = 1;\n\n\tif (cb_arg == NULL)\n\t\treturn;\n\n\tbonded_ethdev = (struct rte_eth_dev *)cb_arg;\n\tinternals = (struct bond_dev_private *)bonded_ethdev->data->dev_private;\n\n\tif (!bonded_ethdev->data->dev_started ||\n\t\t!internals->link_status_polling_enabled)\n\t\treturn;\n\n\t/* If device is currently being configured then don't check slaves link\n\t * status, wait until next period */\n\tif (rte_spinlock_trylock(&internals->lock)) {\n\t\tif (internals->slave_count > 0)\n\t\t\tpolling_slave_found = 0;\n\n\t\tfor (i = 0; i < internals->slave_count; i++) {\n\t\t\tif (!internals->slaves[i].link_status_poll_enabled)\n\t\t\t\tcontinue;\n\n\t\t\tslave_ethdev = &rte_eth_devices[internals->slaves[i].port_id];\n\t\t\tpolling_slave_found = 1;\n\n\t\t\t/* Update slave link status */\n\t\t\t(*slave_ethdev->dev_ops->link_update)(slave_ethdev,\n\t\t\t\t\tinternals->slaves[i].link_status_wait_to_complete);\n\n\t\t\t/* if link status has changed since last checked then call lsc\n\t\t\t * event callback */\n\t\t\tif (slave_ethdev->data->dev_link.link_status !=\n\t\t\t\t\tinternals->slaves[i].last_link_status) {\n\t\t\t\tinternals->slaves[i].last_link_status =\n\t\t\t\t\t\tslave_ethdev->data->dev_link.link_status;\n\n\t\t\t\tbond_ethdev_lsc_event_callback(internals->slaves[i].port_id,\n\t\t\t\t\t\tRTE_ETH_EVENT_INTR_LSC,\n\t\t\t\t\t\t&bonded_ethdev->data->port_id);\n\t\t\t}\n\t\t}\n\t\trte_spinlock_unlock(&internals->lock);\n\t}\n\n\tif (polling_slave_found)\n\t\t/* Set alarm to continue monitoring link status of slave ethdev's */\n\t\trte_eal_alarm_set(internals->link_status_polling_interval_ms * 1000,\n\t\t\t\tbond_ethdev_slave_link_status_change_monitor, cb_arg);\n}\n\nstatic int\nbond_ethdev_link_update(struct rte_eth_dev *bonded_eth_dev,\n\t\tint wait_to_complete)\n{\n\tstruct bond_dev_private *internals = bonded_eth_dev->data->dev_private;\n\n\tif (!bonded_eth_dev->data->dev_started ||\n\t\tinternals->active_slave_count == 0) {\n\t\tbonded_eth_dev->data->dev_link.link_status = 0;\n\t\treturn 0;\n\t} else {\n\t\tstruct rte_eth_dev *slave_eth_dev;\n\t\tint i, link_up = 0;\n\n\t\tfor (i = 0; i < internals->active_slave_count; i++) {\n\t\t\tslave_eth_dev = &rte_eth_devices[internals->active_slaves[i]];\n\n\t\t\t(*slave_eth_dev->dev_ops->link_update)(slave_eth_dev,\n\t\t\t\t\twait_to_complete);\n\t\t\tif (slave_eth_dev->data->dev_link.link_status == 1) {\n\t\t\t\tlink_up = 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tbonded_eth_dev->data->dev_link.link_status = link_up;\n\t}\n\n\treturn 0;\n}\n\nstatic void\nbond_ethdev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tstruct bond_dev_private *internals = dev->data->dev_private;\n\tstruct rte_eth_stats slave_stats;\n\tint i;\n\n\tfor (i = 0; i < internals->slave_count; i++) {\n\t\trte_eth_stats_get(internals->slaves[i].port_id, &slave_stats);\n\n\t\tstats->ipackets += slave_stats.ipackets;\n\t\tstats->opackets += slave_stats.opackets;\n\t\tstats->ibytes += slave_stats.ibytes;\n\t\tstats->obytes += slave_stats.obytes;\n\t\tstats->ierrors += slave_stats.ierrors;\n\t\tstats->oerrors += slave_stats.oerrors;\n\t\tstats->imcasts += slave_stats.imcasts;\n\t\tstats->rx_nombuf += slave_stats.rx_nombuf;\n\t\tstats->fdirmatch += slave_stats.fdirmatch;\n\t\tstats->fdirmiss += slave_stats.fdirmiss;\n\t\tstats->tx_pause_xon += slave_stats.tx_pause_xon;\n\t\tstats->rx_pause_xon += slave_stats.rx_pause_xon;\n\t\tstats->tx_pause_xoff += slave_stats.tx_pause_xoff;\n\t\tstats->rx_pause_xoff += slave_stats.rx_pause_xoff;\n\t}\n}\n\nstatic void\nbond_ethdev_stats_reset(struct rte_eth_dev *dev)\n{\n\tstruct bond_dev_private *internals = dev->data->dev_private;\n\tint i;\n\n\tfor (i = 0; i < internals->slave_count; i++)\n\t\trte_eth_stats_reset(internals->slaves[i].port_id);\n}\n\nstatic void\nbond_ethdev_promiscuous_enable(struct rte_eth_dev *eth_dev)\n{\n\tstruct bond_dev_private *internals = eth_dev->data->dev_private;\n\tint i;\n\n\tinternals->promiscuous_en = 1;\n\n\tswitch (internals->mode) {\n\t/* Promiscuous mode is propagated to all slaves */\n\tcase BONDING_MODE_ROUND_ROBIN:\n\tcase BONDING_MODE_BALANCE:\n\tcase BONDING_MODE_BROADCAST:\n\t\tfor (i = 0; i < internals->slave_count; i++)\n\t\t\trte_eth_promiscuous_enable(internals->slaves[i].port_id);\n\t\tbreak;\n\t/* In mode4 promiscus mode is managed when slave is added/removed */\n\tcase BONDING_MODE_8023AD:\n\t\tbreak;\n\t/* Promiscuous mode is propagated only to primary slave */\n\tcase BONDING_MODE_ACTIVE_BACKUP:\n\tcase BONDING_MODE_TLB:\n\tcase BONDING_MODE_ALB:\n\tdefault:\n\t\trte_eth_promiscuous_enable(internals->current_primary_port);\n\t}\n}\n\nstatic void\nbond_ethdev_promiscuous_disable(struct rte_eth_dev *dev)\n{\n\tstruct bond_dev_private *internals = dev->data->dev_private;\n\tint i;\n\n\tinternals->promiscuous_en = 0;\n\n\tswitch (internals->mode) {\n\t/* Promiscuous mode is propagated to all slaves */\n\tcase BONDING_MODE_ROUND_ROBIN:\n\tcase BONDING_MODE_BALANCE:\n\tcase BONDING_MODE_BROADCAST:\n\t\tfor (i = 0; i < internals->slave_count; i++)\n\t\t\trte_eth_promiscuous_disable(internals->slaves[i].port_id);\n\t\tbreak;\n\t/* In mode4 promiscus mode is set managed when slave is added/removed */\n\tcase BONDING_MODE_8023AD:\n\t\tbreak;\n\t/* Promiscuous mode is propagated only to primary slave */\n\tcase BONDING_MODE_ACTIVE_BACKUP:\n\tcase BONDING_MODE_TLB:\n\tcase BONDING_MODE_ALB:\n\tdefault:\n\t\trte_eth_promiscuous_disable(internals->current_primary_port);\n\t}\n}\n\nstatic void\nbond_ethdev_delayed_lsc_propagation(void *arg)\n{\n\tif (arg == NULL)\n\t\treturn;\n\n\t_rte_eth_dev_callback_process((struct rte_eth_dev *)arg,\n\t\t\tRTE_ETH_EVENT_INTR_LSC);\n}\n\nvoid\nbond_ethdev_lsc_event_callback(uint8_t port_id, enum rte_eth_event_type type,\n\t\tvoid *param)\n{\n\tstruct rte_eth_dev *bonded_eth_dev, *slave_eth_dev;\n\tstruct bond_dev_private *internals;\n\tstruct rte_eth_link link;\n\n\tint i, valid_slave = 0;\n\tuint8_t active_pos;\n\tuint8_t lsc_flag = 0;\n\n\tif (type != RTE_ETH_EVENT_INTR_LSC || param == NULL)\n\t\treturn;\n\n\tbonded_eth_dev = &rte_eth_devices[*(uint8_t *)param];\n\tslave_eth_dev = &rte_eth_devices[port_id];\n\n\tif (valid_bonded_ethdev(bonded_eth_dev))\n\t\treturn;\n\n\tinternals = bonded_eth_dev->data->dev_private;\n\n\t/* If the device isn't started don't handle interrupts */\n\tif (!bonded_eth_dev->data->dev_started)\n\t\treturn;\n\n\t/* verify that port_id is a valid slave of bonded port */\n\tfor (i = 0; i < internals->slave_count; i++) {\n\t\tif (internals->slaves[i].port_id == port_id) {\n\t\t\tvalid_slave = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!valid_slave)\n\t\treturn;\n\n\t/* Search for port in active port list */\n\tactive_pos = find_slave_by_id(internals->active_slaves,\n\t\t\tinternals->active_slave_count, port_id);\n\n\trte_eth_link_get_nowait(port_id, &link);\n\tif (link.link_status) {\n\t\tif (active_pos < internals->active_slave_count)\n\t\t\treturn;\n\n\t\t/* if no active slave ports then set this port to be primary port */\n\t\tif (internals->active_slave_count < 1) {\n\t\t\t/* If first active slave, then change link status */\n\t\t\tbonded_eth_dev->data->dev_link.link_status = 1;\n\t\t\tinternals->current_primary_port = port_id;\n\t\t\tlsc_flag = 1;\n\n\t\t\tmac_address_slaves_update(bonded_eth_dev);\n\n\t\t\t/* Inherit eth dev link properties from first active slave */\n\t\t\tlink_properties_set(bonded_eth_dev,\n\t\t\t\t\t&(slave_eth_dev->data->dev_link));\n\t\t}\n\n\t\tactivate_slave(bonded_eth_dev, port_id);\n\n\t\t/* If user has defined the primary port then default to using it */\n\t\tif (internals->user_defined_primary_port &&\n\t\t\t\tinternals->primary_port == port_id)\n\t\t\tbond_ethdev_primary_set(internals, port_id);\n\t} else {\n\t\tif (active_pos == internals->active_slave_count)\n\t\t\treturn;\n\n\t\t/* Remove from active slave list */\n\t\tdeactivate_slave(bonded_eth_dev, port_id);\n\n\t\t/* No active slaves, change link status to down and reset other\n\t\t * link properties */\n\t\tif (internals->active_slave_count < 1) {\n\t\t\tlsc_flag = 1;\n\t\t\tbonded_eth_dev->data->dev_link.link_status = 0;\n\n\t\t\tlink_properties_reset(bonded_eth_dev);\n\t\t}\n\n\t\t/* Update primary id, take first active slave from list or if none\n\t\t * available set to -1 */\n\t\tif (port_id == internals->current_primary_port) {\n\t\t\tif (internals->active_slave_count > 0)\n\t\t\t\tbond_ethdev_primary_set(internals,\n\t\t\t\t\t\tinternals->active_slaves[0]);\n\t\t\telse\n\t\t\t\tinternals->current_primary_port = internals->primary_port;\n\t\t}\n\t}\n\n\tif (lsc_flag) {\n\t\t/* Cancel any possible outstanding interrupts if delays are enabled */\n\t\tif (internals->link_up_delay_ms > 0 ||\n\t\t\tinternals->link_down_delay_ms > 0)\n\t\t\trte_eal_alarm_cancel(bond_ethdev_delayed_lsc_propagation,\n\t\t\t\t\tbonded_eth_dev);\n\n\t\tif (bonded_eth_dev->data->dev_link.link_status) {\n\t\t\tif (internals->link_up_delay_ms > 0)\n\t\t\t\trte_eal_alarm_set(internals->link_up_delay_ms * 1000,\n\t\t\t\t\t\tbond_ethdev_delayed_lsc_propagation,\n\t\t\t\t\t\t(void *)bonded_eth_dev);\n\t\t\telse\n\t\t\t\t_rte_eth_dev_callback_process(bonded_eth_dev,\n\t\t\t\t\t\tRTE_ETH_EVENT_INTR_LSC);\n\n\t\t} else {\n\t\t\tif (internals->link_down_delay_ms > 0)\n\t\t\t\trte_eal_alarm_set(internals->link_down_delay_ms * 1000,\n\t\t\t\t\t\tbond_ethdev_delayed_lsc_propagation,\n\t\t\t\t\t\t(void *)bonded_eth_dev);\n\t\t\telse\n\t\t\t\t_rte_eth_dev_callback_process(bonded_eth_dev,\n\t\t\t\t\t\tRTE_ETH_EVENT_INTR_LSC);\n\t\t}\n\t}\n}\n\nstruct eth_dev_ops default_dev_ops = {\n\t\t.dev_start = bond_ethdev_start,\n\t\t.dev_stop = bond_ethdev_stop,\n\t\t.dev_close = bond_ethdev_close,\n\t\t.dev_configure = bond_ethdev_configure,\n\t\t.dev_infos_get = bond_ethdev_info,\n\t\t.rx_queue_setup = bond_ethdev_rx_queue_setup,\n\t\t.tx_queue_setup = bond_ethdev_tx_queue_setup,\n\t\t.rx_queue_release = bond_ethdev_rx_queue_release,\n\t\t.tx_queue_release = bond_ethdev_tx_queue_release,\n\t\t.link_update = bond_ethdev_link_update,\n\t\t.stats_get = bond_ethdev_stats_get,\n\t\t.stats_reset = bond_ethdev_stats_reset,\n\t\t.promiscuous_enable = bond_ethdev_promiscuous_enable,\n\t\t.promiscuous_disable = bond_ethdev_promiscuous_disable\n};\n\nstatic int\nbond_init(const char *name, const char *params)\n{\n\tstruct bond_dev_private *internals;\n\tstruct rte_kvargs *kvlist;\n\tuint8_t bonding_mode, socket_id;\n\tint arg_count, port_id;\n\n\tRTE_LOG(INFO, EAL, \"Initializing pmd_bond for %s\\n\", name);\n\n\tkvlist = rte_kvargs_parse(params, pmd_bond_init_valid_arguments);\n\tif (kvlist == NULL)\n\t\treturn -1;\n\n\t/* Parse link bonding mode */\n\tif (rte_kvargs_count(kvlist, PMD_BOND_MODE_KVARG) == 1) {\n\t\tif (rte_kvargs_process(kvlist, PMD_BOND_MODE_KVARG,\n\t\t\t\t&bond_ethdev_parse_slave_mode_kvarg,\n\t\t\t\t&bonding_mode) != 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"Invalid mode for bonded device %s\\n\",\n\t\t\t\t\tname);\n\t\t\tgoto parse_error;\n\t\t}\n\t} else {\n\t\tRTE_LOG(ERR, EAL, \"Mode must be specified only once for bonded \"\n\t\t\t\t\"device %s\\n\", name);\n\t\tgoto parse_error;\n\t}\n\n\t/* Parse socket id to create bonding device on */\n\targ_count = rte_kvargs_count(kvlist, PMD_BOND_SOCKET_ID_KVARG);\n\tif (arg_count == 1) {\n\t\tif (rte_kvargs_process(kvlist, PMD_BOND_SOCKET_ID_KVARG,\n\t\t\t\t&bond_ethdev_parse_socket_id_kvarg, &socket_id)\n\t\t\t\t!= 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"Invalid socket Id specified for \"\n\t\t\t\t\t\"bonded device %s\\n\", name);\n\t\t\tgoto parse_error;\n\t\t}\n\t} else if (arg_count > 1) {\n\t\tRTE_LOG(ERR, EAL, \"Socket Id can be specified only once for \"\n\t\t\t\t\"bonded device %s\\n\", name);\n\t\tgoto parse_error;\n\t} else {\n\t\tsocket_id = rte_socket_id();\n\t}\n\n\t/* Create link bonding eth device */\n\tport_id = rte_eth_bond_create(name, bonding_mode, socket_id);\n\tif (port_id < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Failed to create socket %s in mode %u on \"\n\t\t\t\t\"socket %u.\\n\",\tname, bonding_mode, socket_id);\n\t\tgoto parse_error;\n\t}\n\tinternals = rte_eth_devices[port_id].data->dev_private;\n\tinternals->kvlist = kvlist;\n\n\tRTE_LOG(INFO, EAL, \"Create bonded device %s on port %d in mode %u on \"\n\t\t\t\"socket %u.\\n\",\tname, port_id, bonding_mode, socket_id);\n\treturn 0;\n\nparse_error:\n\trte_kvargs_free(kvlist);\n\n\treturn -1;\n}\n\nstatic int\nbond_uninit(const char *name)\n{\n\tint ret;\n\n\tif (name == NULL)\n\t\treturn -EINVAL;\n\n\tRTE_LOG(INFO, EAL, \"Uninitializing pmd_bond for %s\\n\", name);\n\n\t/* free link bonding eth device */\n\tret = rte_eth_bond_free(name);\n\tif (ret < 0)\n\t\tRTE_LOG(ERR, EAL, \"Failed to free %s\\n\", name);\n\n\treturn ret;\n}\n\n/* this part will resolve the slave portids after all the other pdev and vdev\n * have been allocated */\nstatic int\nbond_ethdev_configure(struct rte_eth_dev *dev)\n{\n\tchar *name = dev->data->name;\n\tstruct bond_dev_private *internals = dev->data->dev_private;\n\tstruct rte_kvargs *kvlist = internals->kvlist;\n\tint arg_count;\n\tuint8_t port_id = dev - rte_eth_devices;\n\n\t/*\n\t * if no kvlist, it means that this bonded device has been created\n\t * through the bonding api.\n\t */\n\tif (!kvlist)\n\t\treturn 0;\n\n\t/* Parse MAC address for bonded device */\n\targ_count = rte_kvargs_count(kvlist, PMD_BOND_MAC_ADDR_KVARG);\n\tif (arg_count == 1) {\n\t\tstruct ether_addr bond_mac;\n\n\t\tif (rte_kvargs_process(kvlist, PMD_BOND_MAC_ADDR_KVARG,\n\t\t\t\t&bond_ethdev_parse_bond_mac_addr_kvarg, &bond_mac) < 0) {\n\t\t\tRTE_LOG(INFO, EAL, \"Invalid mac address for bonded device %s\\n\",\n\t\t\t\t\tname);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Set MAC address */\n\t\tif (rte_eth_bond_mac_address_set(port_id, &bond_mac) != 0) {\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\t\"Failed to set mac address on bonded device %s\\n\",\n\t\t\t\t\tname);\n\t\t\treturn -1;\n\t\t}\n\t} else if (arg_count > 1) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\"MAC address can be specified only once for bonded device %s\\n\",\n\t\t\t\tname);\n\t\treturn -1;\n\t}\n\n\t/* Parse/set balance mode transmit policy */\n\targ_count = rte_kvargs_count(kvlist, PMD_BOND_XMIT_POLICY_KVARG);\n\tif (arg_count == 1) {\n\t\tuint8_t xmit_policy;\n\n\t\tif (rte_kvargs_process(kvlist, PMD_BOND_XMIT_POLICY_KVARG,\n\t\t\t\t&bond_ethdev_parse_balance_xmit_policy_kvarg, &xmit_policy) !=\n\t\t\t\t\t\t0) {\n\t\t\tRTE_LOG(INFO, EAL,\n\t\t\t\t\t\"Invalid xmit policy specified for bonded device %s\\n\",\n\t\t\t\t\tname);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Set balance mode transmit policy*/\n\t\tif (rte_eth_bond_xmit_policy_set(port_id, xmit_policy) != 0) {\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\t\"Failed to set balance xmit policy on bonded device %s\\n\",\n\t\t\t\t\tname);\n\t\t\treturn -1;\n\t\t}\n\t} else if (arg_count > 1) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\"Transmit policy can be specified only once for bonded device\"\n\t\t\t\t\" %s\\n\", name);\n\t\treturn -1;\n\t}\n\n\t/* Parse/add slave ports to bonded device */\n\tif (rte_kvargs_count(kvlist, PMD_BOND_SLAVE_PORT_KVARG) > 0) {\n\t\tstruct bond_ethdev_slave_ports slave_ports;\n\t\tunsigned i;\n\n\t\tmemset(&slave_ports, 0, sizeof(slave_ports));\n\n\t\tif (rte_kvargs_process(kvlist, PMD_BOND_SLAVE_PORT_KVARG,\n\t\t\t\t&bond_ethdev_parse_slave_port_kvarg, &slave_ports) != 0) {\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\t\"Failed to parse slave ports for bonded device %s\\n\",\n\t\t\t\t\tname);\n\t\t\treturn -1;\n\t\t}\n\n\t\tfor (i = 0; i < slave_ports.slave_count; i++) {\n\t\t\tif (rte_eth_bond_slave_add(port_id, slave_ports.slaves[i]) != 0) {\n\t\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\t\t\"Failed to add port %d as slave to bonded device %s\\n\",\n\t\t\t\t\t\tslave_ports.slaves[i], name);\n\t\t\t}\n\t\t}\n\n\t} else {\n\t\tRTE_LOG(INFO, EAL, \"No slaves specified for bonded device %s\\n\", name);\n\t\treturn -1;\n\t}\n\n\t/* Parse/set primary slave port id*/\n\targ_count = rte_kvargs_count(kvlist, PMD_BOND_PRIMARY_SLAVE_KVARG);\n\tif (arg_count == 1) {\n\t\tuint8_t primary_slave_port_id;\n\n\t\tif (rte_kvargs_process(kvlist,\n\t\t\t\tPMD_BOND_PRIMARY_SLAVE_KVARG,\n\t\t\t\t&bond_ethdev_parse_primary_slave_port_id_kvarg,\n\t\t\t\t&primary_slave_port_id) < 0) {\n\t\t\tRTE_LOG(INFO, EAL,\n\t\t\t\t\t\"Invalid primary slave port id specified for bonded device\"\n\t\t\t\t\t\" %s\\n\", name);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Set balance mode transmit policy*/\n\t\tif (rte_eth_bond_primary_set(port_id, (uint8_t)primary_slave_port_id)\n\t\t\t\t!= 0) {\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\t\"Failed to set primary slave port %d on bonded device %s\\n\",\n\t\t\t\t\tprimary_slave_port_id, name);\n\t\t\treturn -1;\n\t\t}\n\t} else if (arg_count > 1) {\n\t\tRTE_LOG(INFO, EAL,\n\t\t\t\t\"Primary slave can be specified only once for bonded device\"\n\t\t\t\t\" %s\\n\", name);\n\t\treturn -1;\n\t}\n\n\t/* Parse link status monitor polling interval */\n\targ_count = rte_kvargs_count(kvlist, PMD_BOND_LSC_POLL_PERIOD_KVARG);\n\tif (arg_count == 1) {\n\t\tuint32_t lsc_poll_interval_ms;\n\n\t\tif (rte_kvargs_process(kvlist,\n\t\t\t\tPMD_BOND_LSC_POLL_PERIOD_KVARG,\n\t\t\t\t&bond_ethdev_parse_time_ms_kvarg,\n\t\t\t\t&lsc_poll_interval_ms) < 0) {\n\t\t\tRTE_LOG(INFO, EAL,\n\t\t\t\t\t\"Invalid lsc polling interval value specified for bonded\"\n\t\t\t\t\t\" device %s\\n\", name);\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (rte_eth_bond_link_monitoring_set(port_id, lsc_poll_interval_ms)\n\t\t\t\t!= 0) {\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\t\"Failed to set lsc monitor polling interval (%u ms) on\"\n\t\t\t\t\t\" bonded device %s\\n\", lsc_poll_interval_ms, name);\n\t\t\treturn -1;\n\t\t}\n\t} else if (arg_count > 1) {\n\t\tRTE_LOG(INFO, EAL,\n\t\t\t\t\"LSC polling interval can be specified only once for bonded\"\n\t\t\t\t\" device %s\\n\", name);\n\t\treturn -1;\n\t}\n\n\t/* Parse link up interrupt propagation delay */\n\targ_count = rte_kvargs_count(kvlist, PMD_BOND_LINK_UP_PROP_DELAY_KVARG);\n\tif (arg_count == 1) {\n\t\tuint32_t link_up_delay_ms;\n\n\t\tif (rte_kvargs_process(kvlist,\n\t\t\t\tPMD_BOND_LINK_UP_PROP_DELAY_KVARG,\n\t\t\t\t&bond_ethdev_parse_time_ms_kvarg,\n\t\t\t\t&link_up_delay_ms) < 0) {\n\t\t\tRTE_LOG(INFO, EAL,\n\t\t\t\t\t\"Invalid link up propagation delay value specified for\"\n\t\t\t\t\t\" bonded device %s\\n\", name);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Set balance mode transmit policy*/\n\t\tif (rte_eth_bond_link_up_prop_delay_set(port_id, link_up_delay_ms)\n\t\t\t\t!= 0) {\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\t\"Failed to set link up propagation delay (%u ms) on bonded\"\n\t\t\t\t\t\" device %s\\n\", link_up_delay_ms, name);\n\t\t\treturn -1;\n\t\t}\n\t} else if (arg_count > 1) {\n\t\tRTE_LOG(INFO, EAL,\n\t\t\t\t\"Link up propagation delay can be specified only once for\"\n\t\t\t\t\" bonded device %s\\n\", name);\n\t\treturn -1;\n\t}\n\n\t/* Parse link down interrupt propagation delay */\n\targ_count = rte_kvargs_count(kvlist, PMD_BOND_LINK_DOWN_PROP_DELAY_KVARG);\n\tif (arg_count == 1) {\n\t\tuint32_t link_down_delay_ms;\n\n\t\tif (rte_kvargs_process(kvlist,\n\t\t\t\tPMD_BOND_LINK_DOWN_PROP_DELAY_KVARG,\n\t\t\t\t&bond_ethdev_parse_time_ms_kvarg,\n\t\t\t\t&link_down_delay_ms) < 0) {\n\t\t\tRTE_LOG(INFO, EAL,\n\t\t\t\t\t\"Invalid link down propagation delay value specified for\"\n\t\t\t\t\t\" bonded device %s\\n\", name);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Set balance mode transmit policy*/\n\t\tif (rte_eth_bond_link_down_prop_delay_set(port_id, link_down_delay_ms)\n\t\t\t\t!= 0) {\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\t\"Failed to set link down propagation delay (%u ms) on\"\n\t\t\t\t\t\" bonded device %s\\n\", link_down_delay_ms, name);\n\t\t\treturn -1;\n\t\t}\n\t} else if (arg_count > 1) {\n\t\tRTE_LOG(INFO, EAL,\n\t\t\t\t\"Link down propagation delay can be specified only once for\"\n\t\t\t\t\" bonded device %s\\n\", name);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic struct rte_driver bond_drv = {\n\t.name = \"eth_bond\",\n\t.type = PMD_VDEV,\n\t.init = bond_init,\n\t.uninit = bond_uninit,\n};\n\nPMD_REGISTER_DRIVER(bond_drv);\n" }, { "path": "drivers/net/bonding/rte_eth_bond_private.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ETH_BOND_PRIVATE_H_\n#define _RTE_ETH_BOND_PRIVATE_H_\n\n#include \n#include \n\n#include \"rte_eth_bond.h\"\n#include \"rte_eth_bond_8023ad_private.h\"\n#include \"rte_eth_bond_alb.h\"\n\n#define PMD_BOND_SLAVE_PORT_KVARG\t\t\t(\"slave\")\n#define PMD_BOND_PRIMARY_SLAVE_KVARG\t\t(\"primary\")\n#define PMD_BOND_MODE_KVARG\t\t\t\t\t(\"mode\")\n#define PMD_BOND_XMIT_POLICY_KVARG\t\t\t(\"xmit_policy\")\n#define PMD_BOND_SOCKET_ID_KVARG\t\t\t(\"socket_id\")\n#define PMD_BOND_MAC_ADDR_KVARG\t\t\t\t(\"mac\")\n#define PMD_BOND_LSC_POLL_PERIOD_KVARG\t\t(\"lsc_poll_period_ms\")\n#define PMD_BOND_LINK_UP_PROP_DELAY_KVARG\t(\"up_delay\")\n#define PMD_BOND_LINK_DOWN_PROP_DELAY_KVARG\t(\"down_delay\")\n\n#define PMD_BOND_XMIT_POLICY_LAYER2_KVARG\t(\"l2\")\n#define PMD_BOND_XMIT_POLICY_LAYER23_KVARG\t(\"l23\")\n#define PMD_BOND_XMIT_POLICY_LAYER34_KVARG\t(\"l34\")\n\n#define RTE_BOND_LOG(lvl, msg, ...)\t\t\\\n\tRTE_LOG(lvl, PMD, \"%s(%d) - \" msg \"\\n\", __func__, __LINE__, ##__VA_ARGS__)\n\n#define BONDING_MODE_INVALID 0xFF\n\nextern const char *pmd_bond_init_valid_arguments[];\n\nextern const char pmd_bond_driver_name[];\n\n/** Port Queue Mapping Structure */\nstruct bond_rx_queue {\n\tuint16_t queue_id;\n\t/**< Queue Id */\n\tstruct bond_dev_private *dev_private;\n\t/**< Reference to eth_dev private structure */\n\tuint16_t nb_rx_desc;\n\t/**< Number of RX descriptors available for the queue */\n\tstruct rte_eth_rxconf rx_conf;\n\t/**< Copy of RX configuration structure for queue */\n\tstruct rte_mempool *mb_pool;\n\t/**< Reference to mbuf pool to use for RX queue */\n};\n\nstruct bond_tx_queue {\n\tuint16_t queue_id;\n\t/**< Queue Id */\n\tstruct bond_dev_private *dev_private;\n\t/**< Reference to dev private structure */\n\tuint16_t nb_tx_desc;\n\t/**< Number of TX descriptors available for the queue */\n\tstruct rte_eth_txconf tx_conf;\n\t/**< Copy of TX configuration structure for queue */\n};\n\n/** Bonded slave devices structure */\nstruct bond_ethdev_slave_ports {\n\tuint8_t slaves[RTE_MAX_ETHPORTS];\t/**< Slave port id array */\n\tuint8_t slave_count;\t\t\t\t/**< Number of slaves */\n};\n\nstruct bond_slave_details {\n\tuint8_t port_id;\n\n\tuint8_t link_status_poll_enabled;\n\tuint8_t link_status_wait_to_complete;\n\tuint8_t last_link_status;\n\t/**< Port Id of slave eth_dev */\n\tstruct ether_addr persisted_mac_addr;\n};\n\n\ntypedef uint16_t (*xmit_hash_t)(const struct rte_mbuf *buf, uint8_t slave_count);\n\n/** Link Bonding PMD device private configuration Structure */\nstruct bond_dev_private {\n\tuint8_t port_id;\t\t\t\t\t/**< Port Id of Bonded Port */\n\tuint8_t mode;\t\t\t\t\t\t/**< Link Bonding Mode */\n\n\trte_spinlock_t lock;\n\n\tuint8_t primary_port;\t\t\t\t/**< Primary Slave Port */\n\tuint8_t current_primary_port;\t\t/**< Primary Slave Port */\n\tuint8_t user_defined_primary_port;\n\t/**< Flag for whether primary port is user defined or not */\n\n\tuint8_t balance_xmit_policy;\n\t/**< Transmit policy - l2 / l23 / l34 for operation in balance mode */\n\txmit_hash_t xmit_hash;\n\t/**< Transmit policy hash function */\n\n\tuint8_t user_defined_mac;\n\t/**< Flag for whether MAC address is user defined or not */\n\tuint8_t promiscuous_en;\n\t/**< Enabled/disable promiscuous mode on bonding device */\n\tuint8_t link_props_set;\n\t/**< flag to denote if the link properties are set */\n\n\tuint8_t link_status_polling_enabled;\n\tuint32_t link_status_polling_interval_ms;\n\n\tuint32_t link_down_delay_ms;\n\tuint32_t link_up_delay_ms;\n\n\tuint16_t nb_rx_queues;\t\t\t/**< Total number of rx queues */\n\tuint16_t nb_tx_queues;\t\t\t/**< Total number of tx queues*/\n\n\tuint8_t active_slave_count;\t\t/**< Number of active slaves */\n\tuint8_t active_slaves[RTE_MAX_ETHPORTS];\t/**< Active slave list */\n\n\tuint8_t slave_count;\t\t\t/**< Number of bonded slaves */\n\tstruct bond_slave_details slaves[RTE_MAX_ETHPORTS];\n\t/**< Arary of bonded slaves details */\n\n\tstruct mode8023ad_private mode4;\n\tuint8_t tlb_slaves_order[RTE_MAX_ETHPORTS]; /* TLB active slaves send order */\n\tstruct mode_alb_private mode6;\n\n\tuint32_t rx_offload_capa; /** Rx offload capability */\n\tuint32_t tx_offload_capa; /** Tx offload capability */\n\n\tstruct rte_kvargs *kvlist;\n\tuint8_t slave_update_idx;\n};\n\nextern struct eth_dev_ops default_dev_ops;\n\nint\nvalid_bonded_ethdev(const struct rte_eth_dev *eth_dev);\n\n/* Search given slave array to find possition of given id.\n * Return slave pos or slaves_count if not found. */\nstatic inline uint8_t\nfind_slave_by_id(uint8_t *slaves, uint8_t slaves_count, uint8_t slave_id) {\n\n\tuint8_t pos;\n\tfor (pos = 0; pos < slaves_count; pos++) {\n\t\tif (slave_id == slaves[pos])\n\t\t\tbreak;\n\t}\n\n\treturn pos;\n}\n\nint\nvalid_port_id(uint8_t port_id);\n\nint\nvalid_bonded_port_id(uint8_t port_id);\n\nint\nvalid_slave_port_id(uint8_t port_id);\n\nvoid\ndeactivate_slave(struct rte_eth_dev *eth_dev, uint8_t port_id);\n\nvoid\nactivate_slave(struct rte_eth_dev *eth_dev, uint8_t port_id);\n\nvoid\nlink_properties_set(struct rte_eth_dev *bonded_eth_dev,\n\t\tstruct rte_eth_link *slave_dev_link);\nvoid\nlink_properties_reset(struct rte_eth_dev *bonded_eth_dev);\n\nint\nlink_properties_valid(struct rte_eth_link *bonded_dev_link,\n\t\tstruct rte_eth_link *slave_dev_link);\n\nint\nmac_address_set(struct rte_eth_dev *eth_dev, struct ether_addr *new_mac_addr);\n\nint\nmac_address_get(struct rte_eth_dev *eth_dev, struct ether_addr *dst_mac_addr);\n\nint\nmac_address_slaves_update(struct rte_eth_dev *bonded_eth_dev);\n\nuint8_t\nnumber_of_sockets(void);\n\nint\nbond_ethdev_mode_set(struct rte_eth_dev *eth_dev, int mode);\n\nint\nslave_configure(struct rte_eth_dev *bonded_eth_dev,\n\t\tstruct rte_eth_dev *slave_eth_dev);\n\nvoid\nslave_remove(struct bond_dev_private *internals,\n\t\tstruct rte_eth_dev *slave_eth_dev);\n\nvoid\nslave_add(struct bond_dev_private *internals,\n\t\tstruct rte_eth_dev *slave_eth_dev);\n\nuint16_t\nxmit_l2_hash(const struct rte_mbuf *buf, uint8_t slave_count);\n\nuint16_t\nxmit_l23_hash(const struct rte_mbuf *buf, uint8_t slave_count);\n\nuint16_t\nxmit_l34_hash(const struct rte_mbuf *buf, uint8_t slave_count);\n\nvoid\nbond_ethdev_primary_set(struct bond_dev_private *internals,\n\t\tuint8_t slave_port_id);\n\nvoid\nbond_ethdev_lsc_event_callback(uint8_t port_id, enum rte_eth_event_type type,\n\t\tvoid *param);\n\nint\nbond_ethdev_parse_slave_port_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args);\n\nint\nbond_ethdev_parse_slave_mode_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args);\n\nint\nbond_ethdev_parse_socket_id_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args);\n\nint\nbond_ethdev_parse_primary_slave_port_id_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args);\n\nint\nbond_ethdev_parse_balance_xmit_policy_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args);\n\nint\nbond_ethdev_parse_bond_mac_addr_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args);\n\nint\nbond_ethdev_parse_time_ms_kvarg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args);\n\nvoid\nbond_tlb_disable(struct bond_dev_private *internals);\n\nvoid\nbond_tlb_enable(struct bond_dev_private *internals);\n\nvoid\nbond_tlb_activate_slave(struct bond_dev_private *internals);\n\nvoid\nbond_ethdev_stop(struct rte_eth_dev *eth_dev);\n\nvoid\nbond_ethdev_close(struct rte_eth_dev *dev);\n\n#endif\n" }, { "path": "drivers/net/cxgbe/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2014-2015 Chelsio Communications.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Chelsio Communications nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_cxgbe.a\n\nCFLAGS += -I$(SRCDIR)/base/\nCFLAGS += -I$(SRCDIR)\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_pmd_cxgbe_version.map\n\nLIBABIVER := 1\n\nifeq ($(CC), icc)\n#\n# CFLAGS for icc\n#\nCFLAGS_BASE_DRIVER = -wd188\nelse\n#\n# CFLAGS for gcc/clang\n#\nifeq ($(shell test $(CC) = gcc && test $(GCC_VERSION) -ge 44 && echo 1), 1)\nCFLAGS += -Wno-deprecated\nendif\nCFLAGS_BASE_DRIVER =\n\nendif\n\n#\n# Add extra flags for base driver files (also known as shared code)\n# to disable warnings in them\n#\nBASE_DRIVER_OBJS=$(patsubst %.c,%.o,$(notdir $(wildcard $(SRCDIR)/base/*.c)))\n$(foreach obj, $(BASE_DRIVER_OBJS), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER)))\n\nVPATH += $(SRCDIR)/base\n\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += cxgbe_ethdev.c\nSRCS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += cxgbe_main.c\nSRCS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += sge.c\nSRCS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += t4_hw.c\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += lib/librte_eal lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += lib/librte_mempool lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += lib/librte_net lib/librte_malloc\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/cxgbe/base/adapter.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/* This file should not be included directly. Include common.h instead. */\n\n#ifndef __T4_ADAPTER_H__\n#define __T4_ADAPTER_H__\n\n#include \n\n#include \"cxgbe_compat.h\"\n#include \"t4_regs_values.h\"\n\nenum {\n\tMAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */\n};\n\nstruct adapter;\nstruct sge_rspq;\n\nenum {\n\tPORT_RSS_DONE = (1 << 0),\n};\n\nstruct port_info {\n\tstruct adapter *adapter; /* adapter that this port belongs to */\n\tstruct rte_eth_dev *eth_dev; /* associated rte eth device */\n\tstruct port_stats stats_base; /* port statistics base */\n\tstruct link_config link_cfg; /* link configuration info */\n\n\tunsigned long flags; /* port related flags */\n\tshort int xact_addr_filt; /* index of exact MAC address filter */\n\n\tu16 viid; /* associated virtual interface id */\n\ts8 mdio_addr; /* address of the PHY */\n\tu8 port_type; /* firmware port type */\n\tu8 mod_type; /* firmware module type */\n\tu8 port_id; /* physical port ID */\n\tu8 tx_chan; /* associated channel */\n\n\tu8 n_rx_qsets; /* # of rx qsets */\n\tu8 n_tx_qsets; /* # of tx qsets */\n\tu8 first_qset; /* index of first qset */\n\n\tu16 *rss; /* rss table */\n\tu8 rss_mode; /* rss mode */\n\tu16 rss_size; /* size of VI's RSS table slice */\n};\n\n/* Enable or disable autonegotiation. If this is set to enable,\n * the forced link modes above are completely ignored.\n */\n#define AUTONEG_DISABLE 0x00\n#define AUTONEG_ENABLE 0x01\n\nenum { /* adapter flags */\n\tFULL_INIT_DONE = (1 << 0),\n\tUSING_MSI = (1 << 1),\n\tUSING_MSIX = (1 << 2),\n\tFW_QUEUE_BOUND = (1 << 3),\n\tFW_OK = (1 << 4),\n\tCFG_QUEUES\t = (1 << 5),\n\tMASTER_PF = (1 << 6),\n};\n\nstruct rx_sw_desc { /* SW state per Rx descriptor */\n\tvoid *buf; /* struct page or mbuf */\n\tdma_addr_t dma_addr;\n};\n\nstruct sge_fl { /* SGE free-buffer queue state */\n\t/* RO fields */\n\tstruct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */\n\n\tdma_addr_t addr; /* bus address of HW ring start */\n\t__be64 *desc; /* address of HW Rx descriptor ring */\n\n\tvoid __iomem *bar2_addr; /* address of BAR2 Queue registers */\n\tunsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */\n\n\tunsigned int cntxt_id; /* SGE relative QID for the free list */\n\tunsigned int size; /* capacity of free list */\n\n\tunsigned int avail; /* # of available Rx buffers */\n\tunsigned int pend_cred; /* new buffers since last FL DB ring */\n\tunsigned int cidx; /* consumer index */\n\tunsigned int pidx; /* producer index */\n\n\tunsigned long alloc_failed; /* # of times buffer allocation failed */\n\tunsigned long low; /* # of times momentarily starving */\n};\n\n#define MAX_MBUF_FRAGS (16384 / 512 + 2)\n\n/* A packet gather list */\nstruct pkt_gl {\n\tunion {\n\t\tstruct rte_mbuf *mbufs[MAX_MBUF_FRAGS];\n\t} /* UNNAMED */;\n\tvoid *va; /* virtual address of first byte */\n\tunsigned int nfrags; /* # of fragments */\n\tunsigned int tot_len; /* total length of fragments */\n\tbool usembufs; /* use mbufs for fragments */\n};\n\ntypedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,\n\t\t\t const struct pkt_gl *gl);\n\nstruct sge_rspq { /* state for an SGE response queue */\n\tstruct adapter *adapter; /* adapter that this queue belongs to */\n\tstruct rte_eth_dev *eth_dev; /* associated rte eth device */\n\tstruct rte_mempool *mb_pool; /* associated mempool */\n\n\tdma_addr_t phys_addr; /* physical address of the ring */\n\t__be64 *desc; /* address of HW response ring */\n\tconst __be64 *cur_desc; /* current descriptor in queue */\n\n\tvoid __iomem *bar2_addr; /* address of BAR2 Queue registers */\n\tunsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */\n\n\tunsigned int cidx; /* consumer index */\n\tunsigned int gts_idx;\t /* last gts write sent */\n\tunsigned int iqe_len; /* entry size */\n\tunsigned int size; /* capacity of response queue */\n\tint offset; /* offset into current Rx buffer */\n\n\tu8 gen; /* current generation bit */\n\tu8 intr_params; /* interrupt holdoff parameters */\n\tu8 next_intr_params; /* holdoff params for next interrupt */\n\tu8 pktcnt_idx; /* interrupt packet threshold */\n\tu8 port_id;\t\t /* associated port-id */\n\tu8 idx; /* queue index within its group */\n\tu16 cntxt_id; /* SGE relative QID for the response Q */\n\tu16 abs_id; /* absolute SGE id for the response q */\n\n\trspq_handler_t handler; /* associated handler for this response q */\n};\n\nstruct sge_eth_rx_stats {\t/* Ethernet rx queue statistics */\n\tu64 pkts;\t\t/* # of ethernet packets */\n\tu64 rx_bytes;\t\t/* # of ethernet bytes */\n\tu64 rx_cso;\t\t/* # of Rx checksum offloads */\n\tu64 vlan_ex;\t\t/* # of Rx VLAN extractions */\n\tu64 rx_drops;\t\t/* # of packets dropped due to no mem */\n};\n\nstruct sge_eth_rxq { /* a SW Ethernet Rx queue */\n\tstruct sge_rspq rspq;\n\tstruct sge_fl fl;\n\tstruct sge_eth_rx_stats stats;\n\tbool usembufs; /* one ingress packet per mbuf FL buffer */\n} __rte_cache_aligned;\n\n/*\n * Currently there are two types of coalesce WR. Type 0 needs 48 bytes per\n * packet (if one sgl is present) and type 1 needs 32 bytes. This means\n * that type 0 can fit a maximum of 10 packets per WR and type 1 can fit\n * 15 packets. We need to keep track of the mbuf pointers in a coalesce WR\n * to be able to free those mbufs when we get completions back from the FW.\n * Allocating the maximum number of pointers in every tx desc is a waste\n * of memory resources so we only store 2 pointers per tx desc which should\n * be enough since a tx desc can only fit 2 packets in the best case\n * scenario where a packet needs 32 bytes.\n */\n#define ETH_COALESCE_PKT_NUM 15\n#define ETH_COALESCE_PKT_PER_DESC 2\n\nstruct tx_eth_coal_desc {\n\tstruct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];\n\tstruct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];\n\tint idx;\n};\n\nstruct tx_desc {\n\t__be64 flit[8];\n};\n\nstruct tx_sw_desc { /* SW state per Tx descriptor */\n\tstruct rte_mbuf *mbuf;\n\tstruct ulptx_sgl *sgl;\n\tstruct tx_eth_coal_desc coalesce;\n};\n\nenum {\n\tEQ_STOPPED = (1 << 0),\n};\n\nstruct eth_coalesce {\n\tunsigned char *ptr;\n\tunsigned char type;\n\tunsigned int idx;\n\tunsigned int len;\n\tunsigned int flits;\n\tunsigned int max;\n};\n\nstruct sge_txq {\n\tstruct tx_desc *desc; /* address of HW Tx descriptor ring */\n\tstruct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */\n\tstruct sge_qstat *stat; /* queue status entry */\n\tstruct eth_coalesce coalesce; /* coalesce info */\n\n\tuint64_t phys_addr; /* physical address of the ring */\n\n\tvoid __iomem *bar2_addr; /* address of BAR2 Queue registers */\n\tunsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */\n\n\tunsigned int cntxt_id; /* SGE relative QID for the Tx Q */\n\tunsigned int in_use; /* # of in-use Tx descriptors */\n\tunsigned int size; /* # of descriptors */\n\tunsigned int cidx; /* SW consumer index */\n\tunsigned int pidx; /* producer index */\n\tunsigned int dbidx;\t /* last idx when db ring was done */\n\tunsigned int equeidx;\t /* last sent credit request */\n\tunsigned int last_pidx;\t /* last pidx recorded by tx monitor */\n\tunsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */\n\n\tint db_disabled; /* doorbell state */\n\tunsigned short db_pidx; /* doorbell producer index */\n\tunsigned short db_pidx_inc; /* doorbell producer increment */\n};\n\nstruct sge_eth_tx_stats {\t/* Ethernet tx queue statistics */\n\tu64 pkts;\t\t/* # of ethernet packets */\n\tu64 tx_bytes;\t\t/* # of ethernet bytes */\n\tu64 tso;\t\t/* # of TSO requests */\n\tu64 tx_cso;\t\t/* # of Tx checksum offloads */\n\tu64 vlan_ins;\t\t/* # of Tx VLAN insertions */\n\tu64 mapping_err;\t/* # of I/O MMU packet mapping errors */\n\tu64 coal_wr; /* # of coalesced wr */\n\tu64 coal_pkts; /* # of coalesced packets */\n};\n\nstruct sge_eth_txq { /* state for an SGE Ethernet Tx queue */\n\tstruct sge_txq q;\n\tstruct rte_eth_dev *eth_dev; /* port that this queue belongs to */\n\tstruct sge_eth_tx_stats stats; /* queue statistics */\n\trte_spinlock_t txq_lock;\n\n\tunsigned int flags; /* flags for state of the queue */\n} __rte_cache_aligned;\n\nstruct sge {\n\tstruct sge_eth_txq ethtxq[MAX_ETH_QSETS];\n\tstruct sge_eth_rxq ethrxq[MAX_ETH_QSETS];\n\tstruct sge_rspq fw_evtq __rte_cache_aligned;\n\n\tu16 max_ethqsets; /* # of available Ethernet queue sets */\n\tu32 stat_len; /* length of status page at ring end */\n\tu32 pktshift; /* padding between CPL & packet data */\n\n\t/* response queue interrupt parameters */\n\tu16 timer_val[SGE_NTIMERS];\n\tu8 counter_val[SGE_NCOUNTERS];\n\n\tu32 fl_align; /* response queue message alignment */\n\tu32 fl_pg_order; /* large page allocation size */\n\tu32 fl_starve_thres; /* Free List starvation threshold */\n};\n\n#define T4_OS_NEEDS_MBOX_LOCKING 1\n\n/*\n * OS Lock/List primitives for those interfaces in the Common Code which\n * need this.\n */\n\nstruct mbox_entry {\n\tTAILQ_ENTRY(mbox_entry) next;\n};\n\nTAILQ_HEAD(mbox_list, mbox_entry);\n\nstruct adapter {\n\tstruct rte_pci_device *pdev; /* associated rte pci device */\n\tstruct rte_eth_dev *eth_dev; /* first port's rte eth device */\n\tstruct adapter_params params; /* adapter parameters */\n\tstruct port_info port[MAX_NPORTS]; /* ports belonging to this adapter */\n\tstruct sge sge; /* associated SGE */\n\n\t/* support for single-threading access to adapter mailbox registers */\n\tstruct mbox_list mbox_list;\n\trte_spinlock_t mbox_lock;\n\n\tu8 *regs; /* pointer to registers region */\n\tu8 *bar2; /* pointer to bar2 region */\n\tunsigned long flags; /* adapter flags */\n\tunsigned int mbox; /* associated mailbox */\n\tunsigned int pf; /* associated physical function id */\n\n\tint use_unpacked_mode; /* unpacked rx mode state */\n};\n\n#define CXGBE_PCI_REG(reg) (*((volatile uint32_t *)(reg)))\n\nstatic inline uint64_t cxgbe_read_addr64(volatile void *addr)\n{\n\tuint64_t val = CXGBE_PCI_REG(addr);\n\tuint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));\n\n\tval2 = (uint64_t)(val2 << 32);\n\tval += val2;\n\treturn val;\n}\n\nstatic inline uint32_t cxgbe_read_addr(volatile void *addr)\n{\n\treturn CXGBE_PCI_REG(addr);\n}\n\n#define CXGBE_PCI_REG_ADDR(adap, reg) \\\n\t((volatile uint32_t *)((char *)(adap)->regs + (reg)))\n\n#define CXGBE_READ_REG(adap, reg) \\\n\tcxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))\n\n#define CXGBE_READ_REG64(adap, reg) \\\n\tcxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))\n\n#define CXGBE_PCI_REG_WRITE(reg, value) ({ \\\n\tCXGBE_PCI_REG((reg)) = (value); })\n\n#define CXGBE_WRITE_REG(adap, reg, value) \\\n\tCXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))\n\nstatic inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)\n{\n\tCXGBE_PCI_REG(addr) = val;\n\tCXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4)) = (val >> 32);\n\treturn val;\n}\n\n#define CXGBE_WRITE_REG64(adap, reg, value) \\\n\tcxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))\n\n/**\n * t4_read_reg - read a HW register\n * @adapter: the adapter\n * @reg_addr: the register address\n *\n * Returns the 32-bit value of the given HW register.\n */\nstatic inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)\n{\n\tu32 val = CXGBE_READ_REG(adapter, reg_addr);\n\n\tCXGBE_DEBUG_REG(adapter, \"read register 0x%x value 0x%x\\n\", reg_addr,\n\t\t\tval);\n\treturn val;\n}\n\n/**\n * t4_write_reg - write a HW register\n * @adapter: the adapter\n * @reg_addr: the register address\n * @val: the value to write\n *\n * Write a 32-bit value into the given HW register.\n */\nstatic inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)\n{\n\tCXGBE_DEBUG_REG(adapter, \"setting register 0x%x to 0x%x\\n\", reg_addr,\n\t\t\tval);\n\tCXGBE_WRITE_REG(adapter, reg_addr, val);\n}\n\n/**\n * t4_read_reg64 - read a 64-bit HW register\n * @adapter: the adapter\n * @reg_addr: the register address\n *\n * Returns the 64-bit value of the given HW register.\n */\nstatic inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)\n{\n\tu64 val = CXGBE_READ_REG64(adapter, reg_addr);\n\n\tCXGBE_DEBUG_REG(adapter, \"64-bit read register %#x value %#llx\\n\",\n\t\t\treg_addr, (unsigned long long)val);\n\treturn val;\n}\n\n/**\n * t4_write_reg64 - write a 64-bit HW register\n * @adapter: the adapter\n * @reg_addr: the register address\n * @val: the value to write\n *\n * Write a 64-bit value into the given HW register.\n */\nstatic inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,\n\t\t\t\t u64 val)\n{\n\tCXGBE_DEBUG_REG(adapter, \"setting register %#x to %#llx\\n\", reg_addr,\n\t\t\t(unsigned long long)val);\n\n\tCXGBE_WRITE_REG64(adapter, reg_addr, val);\n}\n\n/**\n * t4_os_set_hw_addr - store a port's MAC address in SW\n * @adapter: the adapter\n * @port_idx: the port index\n * @hw_addr: the Ethernet address\n *\n * Store the Ethernet address of the given port in SW. Called by the\n * common code when it retrieves a port's Ethernet address from EEPROM.\n */\nstatic inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,\n\t\t\t\t u8 hw_addr[])\n{\n\tstruct port_info *pi = &adapter->port[port_idx];\n\n\tether_addr_copy((struct ether_addr *)hw_addr,\n\t\t\t&pi->eth_dev->data->mac_addrs[0]);\n}\n\n/**\n * t4_os_lock_init - initialize spinlock\n * @lock: the spinlock\n */\nstatic inline void t4_os_lock_init(rte_spinlock_t *lock)\n{\n\trte_spinlock_init(lock);\n}\n\n/**\n * t4_os_lock - spin until lock is acquired\n * @lock: the spinlock\n */\nstatic inline void t4_os_lock(rte_spinlock_t *lock)\n{\n\trte_spinlock_lock(lock);\n}\n\n/**\n * t4_os_unlock - unlock a spinlock\n * @lock: the spinlock\n */\nstatic inline void t4_os_unlock(rte_spinlock_t *lock)\n{\n\trte_spinlock_unlock(lock);\n}\n\n/**\n * t4_os_init_list_head - initialize\n * @head: head of list to initialize [to empty]\n */\nstatic inline void t4_os_init_list_head(struct mbox_list *head)\n{\n\tTAILQ_INIT(head);\n}\n\nstatic inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)\n{\n\treturn TAILQ_FIRST(head);\n}\n\n/**\n * t4_os_atomic_add_tail - Enqueue list element atomically onto list\n * @new: the entry to be addded to the queue\n * @head: current head of the linked list\n * @lock: lock to use to guarantee atomicity\n */\nstatic inline void t4_os_atomic_add_tail(struct mbox_entry *entry,\n\t\t\t\t\t struct mbox_list *head,\n\t\t\t\t\t rte_spinlock_t *lock)\n{\n\tt4_os_lock(lock);\n\tTAILQ_INSERT_TAIL(head, entry, next);\n\tt4_os_unlock(lock);\n}\n\n/**\n * t4_os_atomic_list_del - Dequeue list element atomically from list\n * @entry: the entry to be remove/dequeued from the list.\n * @lock: the spinlock\n */\nstatic inline void t4_os_atomic_list_del(struct mbox_entry *entry,\n\t\t\t\t\t struct mbox_list *head,\n\t\t\t\t\t rte_spinlock_t *lock)\n{\n\tt4_os_lock(lock);\n\tTAILQ_REMOVE(head, entry, next);\n\tt4_os_unlock(lock);\n}\n\n/**\n * adap2pinfo - return the port_info of a port\n * @adap: the adapter\n * @idx: the port index\n *\n * Return the port_info structure for the port of the given index.\n */\nstatic inline struct port_info *adap2pinfo(struct adapter *adap, int idx)\n{\n\treturn &adap->port[idx];\n}\n\nvoid *t4_alloc_mem(size_t size);\nvoid t4_free_mem(void *addr);\n#define t4_os_alloc(_size) t4_alloc_mem((_size))\n#define t4_os_free(_ptr) t4_free_mem((_ptr))\n\nvoid t4_os_portmod_changed(const struct adapter *adap, int port_id);\nvoid t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);\n\nvoid reclaim_completed_tx(struct sge_txq *q);\nvoid t4_free_sge_resources(struct adapter *adap);\nvoid t4_sge_tx_monitor_start(struct adapter *adap);\nvoid t4_sge_tx_monitor_stop(struct adapter *adap);\nint t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf);\nint t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,\n\t\t const struct pkt_gl *gl);\nint t4_sge_init(struct adapter *adap);\nint t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,\n\t\t\t struct rte_eth_dev *eth_dev, uint16_t queue_id,\n\t\t\t unsigned int iqid, int socket_id);\nint t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,\n\t\t struct rte_eth_dev *eth_dev, int intr_idx,\n\t\t struct sge_fl *fl, rspq_handler_t handler,\n\t\t int cong, struct rte_mempool *mp, int queue_id,\n\t\t int socket_id);\nint t4_sge_eth_txq_start(struct sge_eth_txq *txq);\nint t4_sge_eth_txq_stop(struct sge_eth_txq *txq);\nvoid t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);\nint t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq);\nint t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq);\nvoid t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);\nvoid t4_sge_eth_clear_queues(struct port_info *pi);\nint cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,\n\t\t\t unsigned int cnt);\nint cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,\n\t unsigned int budget, unsigned int *work_done);\nint cxgb4_write_rss(const struct port_info *pi, const u16 *queues);\n\n#endif /* __T4_ADAPTER_H__ */\n" }, { "path": "drivers/net/cxgbe/base/common.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __CHELSIO_COMMON_H\n#define __CHELSIO_COMMON_H\n\n#include \"cxgbe_compat.h\"\n#include \"t4_hw.h\"\n#include \"t4_chip_type.h\"\n#include \"t4fw_interface.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define CXGBE_PAGE_SIZE RTE_PGSIZE_4K\n\nenum {\n\tMAX_NPORTS = 4, /* max # of ports */\n};\n\nenum {\n\tMEMWIN0_APERTURE = 2048,\n\tMEMWIN0_BASE = 0x1b800,\n};\n\nenum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };\n\nenum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };\n\nenum {\n\tPAUSE_RX = 1 << 0,\n\tPAUSE_TX = 1 << 1,\n\tPAUSE_AUTONEG = 1 << 2\n};\n\nstruct port_stats {\n\tu64 tx_octets; /* total # of octets in good frames */\n\tu64 tx_frames; /* all good frames */\n\tu64 tx_bcast_frames; /* all broadcast frames */\n\tu64 tx_mcast_frames; /* all multicast frames */\n\tu64 tx_ucast_frames; /* all unicast frames */\n\tu64 tx_error_frames; /* all error frames */\n\n\tu64 tx_frames_64; /* # of Tx frames in a particular range */\n\tu64 tx_frames_65_127;\n\tu64 tx_frames_128_255;\n\tu64 tx_frames_256_511;\n\tu64 tx_frames_512_1023;\n\tu64 tx_frames_1024_1518;\n\tu64 tx_frames_1519_max;\n\n\tu64 tx_drop; /* # of dropped Tx frames */\n\tu64 tx_pause; /* # of transmitted pause frames */\n\tu64 tx_ppp0; /* # of transmitted PPP prio 0 frames */\n\tu64 tx_ppp1; /* # of transmitted PPP prio 1 frames */\n\tu64 tx_ppp2; /* # of transmitted PPP prio 2 frames */\n\tu64 tx_ppp3; /* # of transmitted PPP prio 3 frames */\n\tu64 tx_ppp4; /* # of transmitted PPP prio 4 frames */\n\tu64 tx_ppp5; /* # of transmitted PPP prio 5 frames */\n\tu64 tx_ppp6; /* # of transmitted PPP prio 6 frames */\n\tu64 tx_ppp7; /* # of transmitted PPP prio 7 frames */\n\n\tu64 rx_octets; /* total # of octets in good frames */\n\tu64 rx_frames; /* all good frames */\n\tu64 rx_bcast_frames; /* all broadcast frames */\n\tu64 rx_mcast_frames; /* all multicast frames */\n\tu64 rx_ucast_frames; /* all unicast frames */\n\tu64 rx_too_long; /* # of frames exceeding MTU */\n\tu64 rx_jabber; /* # of jabber frames */\n\tu64 rx_fcs_err; /* # of received frames with bad FCS */\n\tu64 rx_len_err; /* # of received frames with length error */\n\tu64 rx_symbol_err; /* symbol errors */\n\tu64 rx_runt; /* # of short frames */\n\n\tu64 rx_frames_64; /* # of Rx frames in a particular range */\n\tu64 rx_frames_65_127;\n\tu64 rx_frames_128_255;\n\tu64 rx_frames_256_511;\n\tu64 rx_frames_512_1023;\n\tu64 rx_frames_1024_1518;\n\tu64 rx_frames_1519_max;\n\n\tu64 rx_pause; /* # of received pause frames */\n\tu64 rx_ppp0; /* # of received PPP prio 0 frames */\n\tu64 rx_ppp1; /* # of received PPP prio 1 frames */\n\tu64 rx_ppp2; /* # of received PPP prio 2 frames */\n\tu64 rx_ppp3; /* # of received PPP prio 3 frames */\n\tu64 rx_ppp4; /* # of received PPP prio 4 frames */\n\tu64 rx_ppp5; /* # of received PPP prio 5 frames */\n\tu64 rx_ppp6; /* # of received PPP prio 6 frames */\n\tu64 rx_ppp7; /* # of received PPP prio 7 frames */\n\n\tu64 rx_ovflow0; /* drops due to buffer-group 0 overflows */\n\tu64 rx_ovflow1; /* drops due to buffer-group 1 overflows */\n\tu64 rx_ovflow2; /* drops due to buffer-group 2 overflows */\n\tu64 rx_ovflow3; /* drops due to buffer-group 3 overflows */\n\tu64 rx_trunc0; /* buffer-group 0 truncated packets */\n\tu64 rx_trunc1; /* buffer-group 1 truncated packets */\n\tu64 rx_trunc2; /* buffer-group 2 truncated packets */\n\tu64 rx_trunc3; /* buffer-group 3 truncated packets */\n};\n\nstruct sge_params {\n\tu32 hps; /* host page size for our PF/VF */\n\tu32 eq_qpp; /* egress queues/page for our PF/VF */\n\tu32 iq_qpp; /* egress queues/page for our PF/VF */\n};\n\nstruct tp_params {\n\tunsigned int ntxchan; /* # of Tx channels */\n\tunsigned int tre; /* log2 of core clocks per TP tick */\n\tunsigned int dack_re; /* DACK timer resolution */\n\tunsigned int la_mask; /* what events are recorded by TP LA */\n\tunsigned short tx_modq[NCHAN]; /* channel to modulation queue map */\n\n\tu32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */\n\tu32 ingress_config; /* cached TP_INGRESS_CONFIG */\n\n\t/*\n\t * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a\n\t * subset of the set of fields which may be present in the Compressed\n\t * Filter Tuple portion of filters and TCP TCB connections. The\n\t * fields which are present are controlled by the TP_VLAN_PRI_MAP.\n\t * Since a variable number of fields may or may not be present, their\n\t * shifted field positions within the Compressed Filter Tuple may\n\t * vary, or not even be present if the field isn't selected in\n\t * TP_VLAN_PRI_MAP. Since some of these fields are needed in various\n\t * places we store their offsets here, or a -1 if the field isn't\n\t * present.\n\t */\n\tint vlan_shift;\n\tint vnic_shift;\n\tint port_shift;\n\tint protocol_shift;\n};\n\nstruct vpd_params {\n\tunsigned int cclk;\n};\n\nstruct pci_params {\n\tuint16_t vendor_id;\n\tuint16_t device_id;\n\tuint32_t vpd_cap_addr;\n\tuint16_t speed;\n\tuint8_t width;\n};\n\n/*\n * Firmware device log.\n */\nstruct devlog_params {\n\tu32 memtype; /* which memory (EDC0, EDC1, MC) */\n\tu32 start; /* start of log in firmware memory */\n\tu32 size; /* size of log */\n};\n\nstruct arch_specific_params {\n\tu8 nchan;\n\tu16 mps_rplc_size;\n\tu16 vfcount;\n\tu32 sge_fl_db;\n\tu16 mps_tcam_size;\n};\n\nstruct adapter_params {\n\tstruct sge_params sge;\n\tstruct tp_params tp;\n\tstruct vpd_params vpd;\n\tstruct pci_params pci;\n\tstruct devlog_params devlog;\n\tenum pcie_memwin drv_memwin;\n\n\tunsigned int sf_size; /* serial flash size in bytes */\n\tunsigned int sf_nsec; /* # of flash sectors */\n\n\tunsigned int fw_vers;\n\tunsigned int tp_vers;\n\n\tunsigned short mtus[NMTUS];\n\tunsigned short a_wnd[NCCTRL_WIN];\n\tunsigned short b_wnd[NCCTRL_WIN];\n\n\tunsigned int mc_size; /* MC memory size */\n\tunsigned int cim_la_size;\n\n\tunsigned char nports; /* # of ethernet ports */\n\tunsigned char portvec;\n\n\tenum chip_type chip; /* chip code */\n\tstruct arch_specific_params arch; /* chip specific params */\n\n\tbool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */\n};\n\nstruct link_config {\n\tunsigned short supported; /* link capabilities */\n\tunsigned short advertising; /* advertised capabilities */\n\tunsigned short requested_speed; /* speed user has requested */\n\tunsigned short speed; /* actual link speed */\n\tunsigned char requested_fc; /* flow control user has requested */\n\tunsigned char fc; /* actual link flow control */\n\tunsigned char autoneg; /* autonegotiating? */\n\tunsigned char link_ok; /* link up? */\n};\n\n#include \"adapter.h\"\n\nvoid t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,\n\t\t u32 val);\nint t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,\n\t\t\tint polarity,\n\t\t\tint attempts, int delay, u32 *valp);\n\nstatic inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,\n\t\t\t\t int polarity, int attempts, int delay)\n{\n\treturn t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,\n\t\t\t\t delay, NULL);\n}\n\n#define for_each_port(adapter, iter) \\\n\tfor (iter = 0; iter < (adapter)->params.nports; ++iter)\n\nvoid t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);\nvoid t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,\n\t\t\t unsigned int mask, unsigned int val);\nvoid t4_intr_enable(struct adapter *adapter);\nvoid t4_intr_disable(struct adapter *adapter);\nint t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,\n\t\t struct link_config *lc);\nvoid t4_load_mtus(struct adapter *adap, const unsigned short *mtus,\n\t\t const unsigned short *alpha, const unsigned short *beta);\nint t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,\n\t\tenum dev_master master, enum dev_state *state);\nint t4_fw_bye(struct adapter *adap, unsigned int mbox);\nint t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);\nint t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset);\nint t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);\nint t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size,\n\t\t\t\tunsigned int cache_line_size,\n\t\t\t\tenum chip_type chip_compat);\nint t4_fixup_host_params(struct adapter *adap, unsigned int page_size,\n\t\t\t unsigned int cache_line_size);\nint t4_fw_initialize(struct adapter *adap, unsigned int mbox);\nint t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,\n\t\t unsigned int vf, unsigned int nparams, const u32 *params,\n\t\t u32 *val);\nint t4_set_params_timeout(struct adapter *adap, unsigned int mbox,\n\t\t\t unsigned int pf, unsigned int vf,\n\t\t\t unsigned int nparams, const u32 *params,\n\t\t\t const u32 *val, int timeout);\nint t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,\n\t\t unsigned int vf, unsigned int nparams, const u32 *params,\n\t\t const u32 *val);\nint t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,\n\t\t unsigned int port, unsigned int pf, unsigned int vf,\n\t\t unsigned int nmac, u8 *mac, unsigned int *rss_size,\n\t\t unsigned int portfunc, unsigned int idstype);\nint t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,\n\t\tunsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,\n\t\tunsigned int *rss_size);\nint t4_free_vi(struct adapter *adap, unsigned int mbox,\n\t unsigned int pf, unsigned int vf,\n\t unsigned int viid);\nint t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,\n\t\t int mtu, int promisc, int all_multi, int bcast, int vlanex,\n\t\t bool sleep_ok);\nint t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,\n\t\t int idx, const u8 *addr, bool persist, bool add_smt);\nint t4_enable_vi_params(struct adapter *adap, unsigned int mbox,\n\t\t\tunsigned int viid, bool rx_en, bool tx_en, bool dcb_en);\nint t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,\n\t\t bool rx_en, bool tx_en);\nint t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,\n\t\t unsigned int pf, unsigned int vf, unsigned int iqid,\n\t\t unsigned int fl0id, unsigned int fl1id);\nint t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,\n\t unsigned int vf, unsigned int iqtype, unsigned int iqid,\n\t unsigned int fl0id, unsigned int fl1id);\nint t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,\n\t\t unsigned int vf, unsigned int eqid);\n\nstatic inline unsigned int core_ticks_per_usec(const struct adapter *adap)\n{\n\treturn adap->params.vpd.cclk / 1000;\n}\n\nstatic inline unsigned int us_to_core_ticks(const struct adapter *adap,\n\t\t\t\t\t unsigned int us)\n{\n\treturn (us * adap->params.vpd.cclk) / 1000;\n}\n\nstatic inline unsigned int core_ticks_to_us(const struct adapter *adapter,\n\t\t\t\t\t unsigned int ticks)\n{\n\t/* add Core Clock / 2 to round ticks to nearest uS */\n\treturn ((ticks * 1000 + adapter->params.vpd.cclk / 2) /\n\t\tadapter->params.vpd.cclk);\n}\n\nint t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,\n\t\t\t int size, void *rpl, bool sleep_ok, int timeout);\nint t4_wr_mbox_meat(struct adapter *adap, int mbox,\n\t\t const void __attribute__((__may_alias__)) *cmd, int size,\n\t\t void *rpl, bool sleep_ok);\n\nstatic inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,\n\t\t\t\t const void *cmd, int size, void *rpl,\n\t\t\t\t int timeout)\n{\n\treturn t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,\n\t\t\t\t timeout);\n}\n\nint t4_get_core_clock(struct adapter *adapter, struct vpd_params *p);\n\nstatic inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,\n\t\t\t int size, void *rpl)\n{\n\treturn t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);\n}\n\nstatic inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,\n\t\t\t\tint size, void *rpl)\n{\n\treturn t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);\n}\n\nvoid t4_read_indirect(struct adapter *adap, unsigned int addr_reg,\n\t\t unsigned int data_reg, u32 *vals, unsigned int nregs,\n\t\t unsigned int start_idx);\nvoid t4_write_indirect(struct adapter *adap, unsigned int addr_reg,\n\t\t unsigned int data_reg, const u32 *vals,\n\t\t unsigned int nregs, unsigned int start_idx);\n\nint t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);\nint t4_read_flash(struct adapter *adapter, unsigned int addr,\n\t\t unsigned int nwords, u32 *data, int byte_oriented);\nint t4_flash_cfg_addr(struct adapter *adapter);\nunsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);\nconst char *t4_get_port_type_description(enum fw_port_type port_type);\nvoid t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);\nvoid t4_get_port_stats_offset(struct adapter *adap, int idx,\n\t\t\t struct port_stats *stats,\n\t\t\t struct port_stats *offset);\nvoid t4_clr_port_stats(struct adapter *adap, int idx);\nvoid t4_reset_link_config(struct adapter *adap, int idx);\nint t4_get_fw_version(struct adapter *adapter, u32 *vers);\nint t4_get_tp_version(struct adapter *adapter, u32 *vers);\nint t4_get_flash_params(struct adapter *adapter);\nint t4_prep_adapter(struct adapter *adapter);\nint t4_port_init(struct adapter *adap, int mbox, int pf, int vf);\nint t4_init_rss_mode(struct adapter *adap, int mbox);\nint t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,\n\t\t\tint start, int n, const u16 *rspq, unsigned int nrspq);\nint t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,\n\t\t unsigned int flags, unsigned int defq);\n\nenum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };\nint t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,\n\t\t unsigned int qtype, u64 *pbar2_qoffset,\n\t\t unsigned int *pbar2_qid);\n\nint t4_init_sge_params(struct adapter *adapter);\nint t4_init_tp_params(struct adapter *adap);\nint t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel);\nint t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);\n#endif /* __CHELSIO_COMMON_H */\n" }, { "path": "drivers/net/cxgbe/base/t4_chip_type.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __T4_CHIP_TYPE_H__\n#define __T4_CHIP_TYPE_H__\n\n/*\n * All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:\n *\n * V = \"4\" for T4; \"5\" for T5, etc. or\n * F = \"0\" for PF 0..3; \"4\"..\"7\" for PF4..7; and \"8\" for VFs\n * PP = adapter product designation\n *\n * We use the \"version\" (V) of the adpater to code the Chip Version above.\n */\n#define CHELSIO_PCI_ID_VER(devid) ((devid) >> 12)\n#define CHELSIO_PCI_ID_FUNC(devid) (((devid) >> 8) & 0xf)\n#define CHELSIO_PCI_ID_PROD(devid) ((devid) & 0xff)\n\n#define CHELSIO_T4 0x4\n#define CHELSIO_T5 0x5\n\n#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))\n#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)\n#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)\n\nenum chip_type {\n\tT4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),\n\tT4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),\n\tT4_FIRST_REV\t= T4_A1,\n\tT4_LAST_REV\t= T4_A2,\n\n\tT5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),\n\tT5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),\n\tT5_FIRST_REV\t= T5_A0,\n\tT5_LAST_REV\t= T5_A1,\n};\n\nstatic inline int is_t4(enum chip_type chip)\n{\n\treturn (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4);\n}\n\nstatic inline int is_t5(enum chip_type chip)\n{\n\treturn (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);\n}\n\n#endif /* __T4_CHIP_TYPE_H__ */\n" }, { "path": "drivers/net/cxgbe/base/t4_hw.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"common.h\"\n#include \"t4_regs.h\"\n#include \"t4_regs_values.h\"\n#include \"t4fw_interface.h\"\n\nstatic void init_link_config(struct link_config *lc, unsigned int caps);\n\n/**\n * t4_read_mtu_tbl - returns the values in the HW path MTU table\n * @adap: the adapter\n * @mtus: where to store the MTU values\n * @mtu_log: where to store the MTU base-2 log (may be %NULL)\n *\n * Reads the HW path MTU table.\n */\nvoid t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)\n{\n\tu32 v;\n\tint i;\n\n\tfor (i = 0; i < NMTUS; ++i) {\n\t\tt4_write_reg(adap, A_TP_MTU_TABLE,\n\t\t\t V_MTUINDEX(0xff) | V_MTUVALUE(i));\n\t\tv = t4_read_reg(adap, A_TP_MTU_TABLE);\n\t\tmtus[i] = G_MTUVALUE(v);\n\t\tif (mtu_log)\n\t\t\tmtu_log[i] = G_MTUWIDTH(v);\n\t}\n}\n\n/**\n * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register\n * @adap: the adapter\n * @addr: the indirect TP register address\n * @mask: specifies the field within the register to modify\n * @val: new value for the field\n *\n * Sets a field of an indirect TP register to the given value.\n */\nvoid t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,\n\t\t\t unsigned int mask, unsigned int val)\n{\n\tt4_write_reg(adap, A_TP_PIO_ADDR, addr);\n\tval |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;\n\tt4_write_reg(adap, A_TP_PIO_DATA, val);\n}\n\n/* The minimum additive increment value for the congestion control table */\n#define CC_MIN_INCR 2U\n\n/**\n * t4_load_mtus - write the MTU and congestion control HW tables\n * @adap: the adapter\n * @mtus: the values for the MTU table\n * @alpha: the values for the congestion control alpha parameter\n * @beta: the values for the congestion control beta parameter\n *\n * Write the HW MTU table with the supplied MTUs and the high-speed\n * congestion control table with the supplied alpha, beta, and MTUs.\n * We write the two tables together because the additive increments\n * depend on the MTUs.\n */\nvoid t4_load_mtus(struct adapter *adap, const unsigned short *mtus,\n\t\t const unsigned short *alpha, const unsigned short *beta)\n{\n\tstatic const unsigned int avg_pkts[NCCTRL_WIN] = {\n\t\t2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,\n\t\t896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,\n\t\t28672, 40960, 57344, 81920, 114688, 163840, 229376\n\t};\n\n\tunsigned int i, w;\n\n\tfor (i = 0; i < NMTUS; ++i) {\n\t\tunsigned int mtu = mtus[i];\n\t\tunsigned int log2 = cxgbe_fls(mtu);\n\n\t\tif (!(mtu & ((1 << log2) >> 2))) /* round */\n\t\t\tlog2--;\n\t\tt4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |\n\t\t\t V_MTUWIDTH(log2) | V_MTUVALUE(mtu));\n\n\t\tfor (w = 0; w < NCCTRL_WIN; ++w) {\n\t\t\tunsigned int inc;\n\n\t\t\tinc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],\n\t\t\t\t CC_MIN_INCR);\n\n\t\t\tt4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |\n\t\t\t\t (w << 16) | (beta[w] << 13) | inc);\n\t\t}\n\t}\n}\n\n/**\n * t4_wait_op_done_val - wait until an operation is completed\n * @adapter: the adapter performing the operation\n * @reg: the register to check for completion\n * @mask: a single-bit field within @reg that indicates completion\n * @polarity: the value of the field when the operation is completed\n * @attempts: number of check iterations\n * @delay: delay in usecs between iterations\n * @valp: where to store the value of the register at completion time\n *\n * Wait until an operation is completed by checking a bit in a register\n * up to @attempts times. If @valp is not NULL the value of the register\n * at the time it indicated completion is stored there. Returns 0 if the\n * operation completes and -EAGAIN otherwise.\n */\nint t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,\n\t\t\tint polarity, int attempts, int delay, u32 *valp)\n{\n\twhile (1) {\n\t\tu32 val = t4_read_reg(adapter, reg);\n\n\t\tif (!!(val & mask) == polarity) {\n\t\t\tif (valp)\n\t\t\t\t*valp = val;\n\t\t\treturn 0;\n\t\t}\n\t\tif (--attempts == 0)\n\t\t\treturn -EAGAIN;\n\t\tif (delay)\n\t\t\tudelay(delay);\n\t}\n}\n\n/**\n * t4_set_reg_field - set a register field to a value\n * @adapter: the adapter to program\n * @addr: the register address\n * @mask: specifies the portion of the register to modify\n * @val: the new value for the register field\n *\n * Sets a register field specified by the supplied mask to the\n * given value.\n */\nvoid t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,\n\t\t u32 val)\n{\n\tu32 v = t4_read_reg(adapter, addr) & ~mask;\n\n\tt4_write_reg(adapter, addr, v | val);\n\t(void)t4_read_reg(adapter, addr); /* flush */\n}\n\n/**\n * t4_read_indirect - read indirectly addressed registers\n * @adap: the adapter\n * @addr_reg: register holding the indirect address\n * @data_reg: register holding the value of the indirect register\n * @vals: where the read register values are stored\n * @nregs: how many indirect registers to read\n * @start_idx: index of first indirect register to read\n *\n * Reads registers that are accessed indirectly through an address/data\n * register pair.\n */\nvoid t4_read_indirect(struct adapter *adap, unsigned int addr_reg,\n\t\t unsigned int data_reg, u32 *vals, unsigned int nregs,\n\t\t unsigned int start_idx)\n{\n\twhile (nregs--) {\n\t\tt4_write_reg(adap, addr_reg, start_idx);\n\t\t*vals++ = t4_read_reg(adap, data_reg);\n\t\tstart_idx++;\n\t}\n}\n\n/**\n * t4_write_indirect - write indirectly addressed registers\n * @adap: the adapter\n * @addr_reg: register holding the indirect addresses\n * @data_reg: register holding the value for the indirect registers\n * @vals: values to write\n * @nregs: how many indirect registers to write\n * @start_idx: address of first indirect register to write\n *\n * Writes a sequential block of registers that are accessed indirectly\n * through an address/data register pair.\n */\nvoid t4_write_indirect(struct adapter *adap, unsigned int addr_reg,\n\t\t unsigned int data_reg, const u32 *vals,\n\t\t unsigned int nregs, unsigned int start_idx)\n{\n\twhile (nregs--) {\n\t\tt4_write_reg(adap, addr_reg, start_idx++);\n\t\tt4_write_reg(adap, data_reg, *vals++);\n\t}\n}\n\n/**\n * t4_report_fw_error - report firmware error\n * @adap: the adapter\n *\n * The adapter firmware can indicate error conditions to the host.\n * If the firmware has indicated an error, print out the reason for\n * the firmware error.\n */\nstatic void t4_report_fw_error(struct adapter *adap)\n{\n\tstatic const char * const reason[] = {\n\t\t\"Crash\",\t\t\t/* PCIE_FW_EVAL_CRASH */\n\t\t\"During Device Preparation\",\t/* PCIE_FW_EVAL_PREP */\n\t\t\"During Device Configuration\",\t/* PCIE_FW_EVAL_CONF */\n\t\t\"During Device Initialization\",\t/* PCIE_FW_EVAL_INIT */\n\t\t\"Unexpected Event\",\t/* PCIE_FW_EVAL_UNEXPECTEDEVENT */\n\t\t\"Insufficient Airflow\",\t\t/* PCIE_FW_EVAL_OVERHEAT */\n\t\t\"Device Shutdown\",\t/* PCIE_FW_EVAL_DEVICESHUTDOWN */\n\t\t\"Reserved\",\t\t\t/* reserved */\n\t};\n\tu32 pcie_fw;\n\n\tpcie_fw = t4_read_reg(adap, A_PCIE_FW);\n\tif (pcie_fw & F_PCIE_FW_ERR)\n\t\tpr_err(\"%s: Firmware reports adapter error: %s\\n\",\n\t\t __func__, reason[G_PCIE_FW_EVAL(pcie_fw)]);\n}\n\n/*\n * Get the reply to a mailbox command and store it in @rpl in big-endian order.\n */\nstatic void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,\n\t\t\t u32 mbox_addr)\n{\n\tfor ( ; nflit; nflit--, mbox_addr += 8)\n\t\t*rpl++ = htobe64(t4_read_reg64(adap, mbox_addr));\n}\n\n/*\n * Handle a FW assertion reported in a mailbox.\n */\nstatic void fw_asrt(struct adapter *adap, u32 mbox_addr)\n{\n\tstruct fw_debug_cmd asrt;\n\n\tget_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);\n\tpr_warn(\"FW assertion at %.16s:%u, val0 %#x, val1 %#x\\n\",\n\t\tasrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),\n\t\tbe32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));\n}\n\n#define X_CIM_PF_NOACCESS 0xeeeeeeee\n\n/*\n * If the Host OS Driver needs locking arround accesses to the mailbox, this\n * can be turned on via the T4_OS_NEEDS_MBOX_LOCKING CPP define ...\n */\n/* makes single-statement usage a bit cleaner ... */\n#ifdef T4_OS_NEEDS_MBOX_LOCKING\n#define T4_OS_MBOX_LOCKING(x) x\n#else\n#define T4_OS_MBOX_LOCKING(x) do {} while (0)\n#endif\n\n/**\n * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox\n * @adap: the adapter\n * @mbox: index of the mailbox to use\n * @cmd: the command to write\n * @size: command length in bytes\n * @rpl: where to optionally store the reply\n * @sleep_ok: if true we may sleep while awaiting command completion\n * @timeout: time to wait for command to finish before timing out\n *\t (negative implies @sleep_ok=false)\n *\n * Sends the given command to FW through the selected mailbox and waits\n * for the FW to execute the command. If @rpl is not %NULL it is used to\n * store the FW's reply to the command. The command and its optional\n * reply are of the same length. Some FW commands like RESET and\n * INITIALIZE can take a considerable amount of time to execute.\n * @sleep_ok determines whether we may sleep while awaiting the response.\n * If sleeping is allowed we use progressive backoff otherwise we spin.\n * Note that passing in a negative @timeout is an alternate mechanism\n * for specifying @sleep_ok=false. This is useful when a higher level\n * interface allows for specification of @timeout but not @sleep_ok ...\n *\n * Returns 0 on success or a negative errno on failure. A\n * failure can happen either because we are not able to execute the\n * command or FW executes it but signals an error. In the latter case\n * the return value is the error code indicated by FW (negated).\n */\nint t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox,\n\t\t\t const void __attribute__((__may_alias__)) *cmd,\n\t\t\t int size, void *rpl, bool sleep_ok, int timeout)\n{\n\t/*\n\t * We delay in small increments at first in an effort to maintain\n\t * responsiveness for simple, fast executing commands but then back\n\t * off to larger delays to a maximum retry delay.\n\t */\n\tstatic const int delay[] = {\n\t\t1, 1, 3, 5, 10, 10, 20, 50, 100\n\t};\n\n\tu32 v;\n\tu64 res;\n\tint i, ms;\n\tunsigned int delay_idx;\n\t__be64 *temp = (__be64 *)malloc(size * sizeof(char));\n\t__be64 *p = temp;\n\tu32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);\n\tu32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);\n\tu32 ctl;\n\tstruct mbox_entry entry;\n\tu32 pcie_fw = 0;\n\n\tif ((size & 15) || size > MBOX_LEN) {\n\t\tfree(temp);\n\t\treturn -EINVAL;\n\t}\n\n\tbzero(p, size);\n\tmemcpy(p, (const __be64 *)cmd, size);\n\n\t/*\n\t * If we have a negative timeout, that implies that we can't sleep.\n\t */\n\tif (timeout < 0) {\n\t\tsleep_ok = false;\n\t\ttimeout = -timeout;\n\t}\n\n#ifdef T4_OS_NEEDS_MBOX_LOCKING\n\t/*\n\t * Queue ourselves onto the mailbox access list. When our entry is at\n\t * the front of the list, we have rights to access the mailbox. So we\n\t * wait [for a while] till we're at the front [or bail out with an\n\t * EBUSY] ...\n\t */\n\tt4_os_atomic_add_tail(&entry, &adap->mbox_list, &adap->mbox_lock);\n\n\tdelay_idx = 0;\n\tms = delay[0];\n\n\tfor (i = 0; ; i += ms) {\n\t\t/*\n\t\t * If we've waited too long, return a busy indication. This\n\t\t * really ought to be based on our initial position in the\n\t\t * mailbox access list but this is a start. We very rarely\n\t\t * contend on access to the mailbox ... Also check for a\n\t\t * firmware error which we'll report as a device error.\n\t\t */\n\t\tpcie_fw = t4_read_reg(adap, A_PCIE_FW);\n\t\tif (i > 4 * timeout || (pcie_fw & F_PCIE_FW_ERR)) {\n\t\t\tt4_os_atomic_list_del(&entry, &adap->mbox_list,\n\t\t\t\t\t &adap->mbox_lock);\n\t\t\tt4_report_fw_error(adap);\n\t\t\treturn (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -EBUSY;\n\t\t}\n\n\t\t/*\n\t\t * If we're at the head, break out and start the mailbox\n\t\t * protocol.\n\t\t */\n\t\tif (t4_os_list_first_entry(&adap->mbox_list) == &entry)\n\t\t\tbreak;\n\n\t\t/*\n\t\t * Delay for a bit before checking again ...\n\t\t */\n\t\tif (sleep_ok) {\n\t\t\tms = delay[delay_idx]; /* last element may repeat */\n\t\t\tif (delay_idx < ARRAY_SIZE(delay) - 1)\n\t\t\t\tdelay_idx++;\n\t\t\tmsleep(ms);\n\t\t} else {\n\t\t\trte_delay_ms(ms);\n\t\t}\n\t}\n#endif /* T4_OS_NEEDS_MBOX_LOCKING */\n\n\t/*\n\t * Attempt to gain access to the mailbox.\n\t */\n\tfor (i = 0; i < 4; i++) {\n\t\tctl = t4_read_reg(adap, ctl_reg);\n\t\tv = G_MBOWNER(ctl);\n\t\tif (v != X_MBOWNER_NONE)\n\t\t\tbreak;\n\t}\n\n\t/*\n\t * If we were unable to gain access, dequeue ourselves from the\n\t * mailbox atomic access list and report the error to our caller.\n\t */\n\tif (v != X_MBOWNER_PL) {\n\t\tT4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,\n\t\t\t\t\t\t\t &adap->mbox_list,\n\t\t\t\t\t\t\t &adap->mbox_lock));\n\t\tt4_report_fw_error(adap);\n\t\treturn (v == X_MBOWNER_FW ? -EBUSY : -ETIMEDOUT);\n\t}\n\n\t/*\n\t * If we gain ownership of the mailbox and there's a \"valid\" message\n\t * in it, this is likely an asynchronous error message from the\n\t * firmware. So we'll report that and then proceed on with attempting\n\t * to issue our own command ... which may well fail if the error\n\t * presaged the firmware crashing ...\n\t */\n\tif (ctl & F_MBMSGVALID) {\n\t\tdev_err(adap, \"found VALID command in mbox %u: \"\n\t\t\t\"%llx %llx %llx %llx %llx %llx %llx %llx\\n\", mbox,\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 8),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 16),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 24),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 32),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 40),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 48),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 56));\n\t}\n\n\t/*\n\t * Copy in the new mailbox command and send it on its way ...\n\t */\n\tfor (i = 0; i < size; i += 8, p++)\n\t\tt4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));\n\n\tCXGBE_DEBUG_MBOX(adap, \"%s: mbox %u: %016llx %016llx %016llx %016llx \"\n\t\t\t\"%016llx %016llx %016llx %016llx\\n\", __func__, (mbox),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 8),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 16),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 24),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 32),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 40),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 48),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 56));\n\n\tt4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));\n\tt4_read_reg(adap, ctl_reg); /* flush write */\n\n\tdelay_idx = 0;\n\tms = delay[0];\n\n\t/*\n\t * Loop waiting for the reply; bail out if we time out or the firmware\n\t * reports an error.\n\t */\n\tpcie_fw = t4_read_reg(adap, A_PCIE_FW);\n\tfor (i = 0; i < timeout && !(pcie_fw & F_PCIE_FW_ERR); i += ms) {\n\t\tif (sleep_ok) {\n\t\t\tms = delay[delay_idx]; /* last element may repeat */\n\t\t\tif (delay_idx < ARRAY_SIZE(delay) - 1)\n\t\t\t\tdelay_idx++;\n\t\t\tmsleep(ms);\n\t\t} else {\n\t\t\tmsleep(ms);\n\t\t}\n\n\t\tpcie_fw = t4_read_reg(adap, A_PCIE_FW);\n\t\tv = t4_read_reg(adap, ctl_reg);\n\t\tif (v == X_CIM_PF_NOACCESS)\n\t\t\tcontinue;\n\t\tif (G_MBOWNER(v) == X_MBOWNER_PL) {\n\t\t\tif (!(v & F_MBMSGVALID)) {\n\t\t\t\tt4_write_reg(adap, ctl_reg,\n\t\t\t\t\t V_MBOWNER(X_MBOWNER_NONE));\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tCXGBE_DEBUG_MBOX(adap,\n\t\t\t\"%s: mbox %u: %016llx %016llx %016llx %016llx \"\n\t\t\t\"%016llx %016llx %016llx %016llx\\n\", __func__, (mbox),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 8),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 16),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 24),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 32),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 40),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 48),\n\t\t\t(unsigned long long)t4_read_reg64(adap, data_reg + 56));\n\n\t\t\tCXGBE_DEBUG_MBOX(adap,\n\t\t\t\t\"command %#x completed in %d ms (%ssleeping)\\n\",\n\t\t\t\t*(const u8 *)cmd,\n\t\t\t\ti + ms, sleep_ok ? \"\" : \"non-\");\n\n\t\t\tres = t4_read_reg64(adap, data_reg);\n\t\t\tif (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {\n\t\t\t\tfw_asrt(adap, data_reg);\n\t\t\t\tres = V_FW_CMD_RETVAL(EIO);\n\t\t\t} else if (rpl) {\n\t\t\t\tget_mbox_rpl(adap, rpl, size / 8, data_reg);\n\t\t\t}\n\t\t\tt4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));\n\t\t\tT4_OS_MBOX_LOCKING(\n\t\t\t\tt4_os_atomic_list_del(&entry, &adap->mbox_list,\n\t\t\t\t\t\t &adap->mbox_lock));\n\t\t\treturn -G_FW_CMD_RETVAL((int)res);\n\t\t}\n\t}\n\n\t/*\n\t * We timed out waiting for a reply to our mailbox command. Report\n\t * the error and also check to see if the firmware reported any\n\t * errors ...\n\t */\n\tdev_err(adap, \"command %#x in mailbox %d timed out\\n\",\n\t\t*(const u8 *)cmd, mbox);\n\tT4_OS_MBOX_LOCKING(t4_os_atomic_list_del(&entry,\n\t\t\t\t\t\t &adap->mbox_list,\n\t\t\t\t\t\t &adap->mbox_lock));\n\tt4_report_fw_error(adap);\n\tfree(temp);\n\treturn (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;\n}\n\nint t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,\n\t\t void *rpl, bool sleep_ok)\n{\n\treturn t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,\n\t\t\t\t FW_CMD_MAX_TIMEOUT);\n}\n\n/**\n * t4_config_rss_range - configure a portion of the RSS mapping table\n * @adapter: the adapter\n * @mbox: mbox to use for the FW command\n * @viid: virtual interface whose RSS subtable is to be written\n * @start: start entry in the table to write\n * @n: how many table entries to write\n * @rspq: values for the \"response queue\" (Ingress Queue) lookup table\n * @nrspq: number of values in @rspq\n *\n * Programs the selected part of the VI's RSS mapping table with the\n * provided values. If @nrspq < @n the supplied values are used repeatedly\n * until the full table range is populated.\n *\n * The caller must ensure the values in @rspq are in the range allowed for\n * @viid.\n */\nint t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,\n\t\t\tint start, int n, const u16 *rspq, unsigned int nrspq)\n{\n\tint ret;\n\tconst u16 *rsp = rspq;\n\tconst u16 *rsp_end = rspq + nrspq;\n\tstruct fw_rss_ind_tbl_cmd cmd;\n\n\tmemset(&cmd, 0, sizeof(cmd));\n\tcmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |\n\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_WRITE |\n\t\t\t\t V_FW_RSS_IND_TBL_CMD_VIID(viid));\n\tcmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));\n\n\t/*\n\t * Each firmware RSS command can accommodate up to 32 RSS Ingress\n\t * Queue Identifiers. These Ingress Queue IDs are packed three to\n\t * a 32-bit word as 10-bit values with the upper remaining 2 bits\n\t * reserved.\n\t */\n\twhile (n > 0) {\n\t\tint nq = min(n, 32);\n\t\tint nq_packed = 0;\n\t\t__be32 *qp = &cmd.iq0_to_iq2;\n\n\t\t/*\n\t\t * Set up the firmware RSS command header to send the next\n\t\t * \"nq\" Ingress Queue IDs to the firmware.\n\t\t */\n\t\tcmd.niqid = cpu_to_be16(nq);\n\t\tcmd.startidx = cpu_to_be16(start);\n\n\t\t/*\n\t\t * \"nq\" more done for the start of the next loop.\n\t\t */\n\t\tstart += nq;\n\t\tn -= nq;\n\n\t\t/*\n\t\t * While there are still Ingress Queue IDs to stuff into the\n\t\t * current firmware RSS command, retrieve them from the\n\t\t * Ingress Queue ID array and insert them into the command.\n\t\t */\n\t\twhile (nq > 0) {\n\t\t\t/*\n\t\t\t * Grab up to the next 3 Ingress Queue IDs (wrapping\n\t\t\t * around the Ingress Queue ID array if necessary) and\n\t\t\t * insert them into the firmware RSS command at the\n\t\t\t * current 3-tuple position within the commad.\n\t\t\t */\n\t\t\tu16 qbuf[3];\n\t\t\tu16 *qbp = qbuf;\n\t\t\tint nqbuf = min(3, nq);\n\n\t\t\tnq -= nqbuf;\n\t\t\tqbuf[0] = 0;\n\t\t\tqbuf[1] = 0;\n\t\t\tqbuf[2] = 0;\n\t\t\twhile (nqbuf && nq_packed < 32) {\n\t\t\t\tnqbuf--;\n\t\t\t\tnq_packed++;\n\t\t\t\t*qbp++ = *rsp++;\n\t\t\t\tif (rsp >= rsp_end)\n\t\t\t\t\trsp = rspq;\n\t\t\t}\n\t\t\t*qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |\n\t\t\t\t\t V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |\n\t\t\t\t\t V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));\n\t\t}\n\n\t\t/*\n\t\t * Send this portion of the RRS table update to the firmware;\n\t\t * bail out on any errors.\n\t\t */\n\t\tret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\n/**\n * t4_config_vi_rss - configure per VI RSS settings\n * @adapter: the adapter\n * @mbox: mbox to use for the FW command\n * @viid: the VI id\n * @flags: RSS flags\n * @defq: id of the default RSS queue for the VI.\n *\n * Configures VI-specific RSS properties.\n */\nint t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,\n\t\t unsigned int flags, unsigned int defq)\n{\n\tstruct fw_rss_vi_config_cmd c;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |\n\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_WRITE |\n\t\t\t\t V_FW_RSS_VI_CONFIG_CMD_VIID(viid));\n\tc.retval_len16 = cpu_to_be32(FW_LEN16(c));\n\tc.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |\n\t\t\tV_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));\n\treturn t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);\n}\n\n/**\n * init_cong_ctrl - initialize congestion control parameters\n * @a: the alpha values for congestion control\n * @b: the beta values for congestion control\n *\n * Initialize the congestion control parameters.\n */\nstatic void init_cong_ctrl(unsigned short *a, unsigned short *b)\n{\n\tint i;\n\n\tfor (i = 0; i < 9; i++) {\n\t\ta[i] = 1;\n\t\tb[i] = 0;\n\t}\n\n\ta[9] = 2;\n\ta[10] = 3;\n\ta[11] = 4;\n\ta[12] = 5;\n\ta[13] = 6;\n\ta[14] = 7;\n\ta[15] = 8;\n\ta[16] = 9;\n\ta[17] = 10;\n\ta[18] = 14;\n\ta[19] = 17;\n\ta[20] = 21;\n\ta[21] = 25;\n\ta[22] = 30;\n\ta[23] = 35;\n\ta[24] = 45;\n\ta[25] = 60;\n\ta[26] = 80;\n\ta[27] = 100;\n\ta[28] = 200;\n\ta[29] = 300;\n\ta[30] = 400;\n\ta[31] = 500;\n\n\tb[9] = 1;\n\tb[10] = 1;\n\tb[11] = 2;\n\tb[12] = 2;\n\tb[13] = 3;\n\tb[14] = 3;\n\tb[15] = 3;\n\tb[16] = 3;\n\tb[17] = 4;\n\tb[18] = 4;\n\tb[19] = 4;\n\tb[20] = 4;\n\tb[21] = 4;\n\tb[22] = 5;\n\tb[23] = 5;\n\tb[24] = 5;\n\tb[25] = 5;\n\tb[26] = 5;\n\tb[27] = 5;\n\tb[28] = 6;\n\tb[29] = 6;\n\tb[30] = 7;\n\tb[31] = 7;\n}\n\n#define INIT_CMD(var, cmd, rd_wr) do { \\\n\t(var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \\\n\t\t\tF_FW_CMD_REQUEST | F_FW_CMD_##rd_wr); \\\n\t(var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \\\n} while (0)\n\nint t4_get_core_clock(struct adapter *adapter, struct vpd_params *p)\n{\n\tu32 cclk_param, cclk_val;\n\tint ret;\n\n\t/*\n\t * Ask firmware for the Core Clock since it knows how to translate the\n\t * Reference Clock ('V2') VPD field into a Core Clock value ...\n\t */\n\tcclk_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |\n\t\t V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));\n\tret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,\n\t\t\t 1, &cclk_param, &cclk_val);\n\tif (ret) {\n\t\tdev_err(adapter, \"%s: error in fetching from coreclock - %d\\n\",\n\t\t\t__func__, ret);\n\t\treturn ret;\n\t}\n\n\tp->cclk = cclk_val;\n\tdev_debug(adapter, \"%s: p->cclk = %u\\n\", __func__, p->cclk);\n\treturn 0;\n}\n\n/* serial flash and firmware constants and flash config file constants */\nenum {\n\tSF_ATTEMPTS = 10, /* max retries for SF operations */\n\n\t/* flash command opcodes */\n\tSF_PROG_PAGE = 2, /* program page */\n\tSF_WR_DISABLE = 4, /* disable writes */\n\tSF_RD_STATUS = 5, /* read status register */\n\tSF_WR_ENABLE = 6, /* enable writes */\n\tSF_RD_DATA_FAST = 0xb, /* read flash */\n\tSF_RD_ID = 0x9f, /* read ID */\n\tSF_ERASE_SECTOR = 0xd8, /* erase sector */\n};\n\n/**\n * sf1_read - read data from the serial flash\n * @adapter: the adapter\n * @byte_cnt: number of bytes to read\n * @cont: whether another operation will be chained\n * @lock: whether to lock SF for PL access only\n * @valp: where to store the read data\n *\n * Reads up to 4 bytes of data from the serial flash. The location of\n * the read needs to be specified prior to calling this by issuing the\n * appropriate commands to the serial flash.\n */\nstatic int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,\n\t\t int lock, u32 *valp)\n{\n\tint ret;\n\n\tif (!byte_cnt || byte_cnt > 4)\n\t\treturn -EINVAL;\n\tif (t4_read_reg(adapter, A_SF_OP) & F_BUSY)\n\t\treturn -EBUSY;\n\tt4_write_reg(adapter, A_SF_OP,\n\t\t V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));\n\tret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);\n\tif (!ret)\n\t\t*valp = t4_read_reg(adapter, A_SF_DATA);\n\treturn ret;\n}\n\n/**\n * sf1_write - write data to the serial flash\n * @adapter: the adapter\n * @byte_cnt: number of bytes to write\n * @cont: whether another operation will be chained\n * @lock: whether to lock SF for PL access only\n * @val: value to write\n *\n * Writes up to 4 bytes of data to the serial flash. The location of\n * the write needs to be specified prior to calling this by issuing the\n * appropriate commands to the serial flash.\n */\nstatic int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,\n\t\t int lock, u32 val)\n{\n\tif (!byte_cnt || byte_cnt > 4)\n\t\treturn -EINVAL;\n\tif (t4_read_reg(adapter, A_SF_OP) & F_BUSY)\n\t\treturn -EBUSY;\n\tt4_write_reg(adapter, A_SF_DATA, val);\n\tt4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |\n\t\t V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));\n\treturn t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);\n}\n\n/**\n * t4_read_flash - read words from serial flash\n * @adapter: the adapter\n * @addr: the start address for the read\n * @nwords: how many 32-bit words to read\n * @data: where to store the read data\n * @byte_oriented: whether to store data as bytes or as words\n *\n * Read the specified number of 32-bit words from the serial flash.\n * If @byte_oriented is set the read data is stored as a byte array\n * (i.e., big-endian), otherwise as 32-bit words in the platform's\n * natural endianness.\n */\nint t4_read_flash(struct adapter *adapter, unsigned int addr,\n\t\t unsigned int nwords, u32 *data, int byte_oriented)\n{\n\tint ret;\n\n\tif (((addr + nwords * sizeof(u32)) > adapter->params.sf_size) ||\n\t (addr & 3))\n\t\treturn -EINVAL;\n\n\taddr = rte_constant_bswap32(addr) | SF_RD_DATA_FAST;\n\n\tret = sf1_write(adapter, 4, 1, 0, addr);\n\tif (ret != 0)\n\t\treturn ret;\n\n\tret = sf1_read(adapter, 1, 1, 0, data);\n\tif (ret != 0)\n\t\treturn ret;\n\n\tfor ( ; nwords; nwords--, data++) {\n\t\tret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);\n\t\tif (nwords == 1)\n\t\t\tt4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */\n\t\tif (ret)\n\t\t\treturn ret;\n\t\tif (byte_oriented)\n\t\t\t*data = cpu_to_be32(*data);\n\t}\n\treturn 0;\n}\n\n/**\n * t4_get_fw_version - read the firmware version\n * @adapter: the adapter\n * @vers: where to place the version\n *\n * Reads the FW version from flash.\n */\nint t4_get_fw_version(struct adapter *adapter, u32 *vers)\n{\n\treturn t4_read_flash(adapter, FLASH_FW_START +\n\t\t\t offsetof(struct fw_hdr, fw_ver), 1, vers, 0);\n}\n\n/**\n * t4_get_tp_version - read the TP microcode version\n * @adapter: the adapter\n * @vers: where to place the version\n *\n * Reads the TP microcode version from flash.\n */\nint t4_get_tp_version(struct adapter *adapter, u32 *vers)\n{\n\treturn t4_read_flash(adapter, FLASH_FW_START +\n\t\t\t offsetof(struct fw_hdr, tp_microcode_ver),\n\t\t\t 1, vers, 0);\n}\n\n#define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\\\n\t\tFW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \\\n\t\tFW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG)\n\n/**\n * t4_link_l1cfg - apply link configuration to MAC/PHY\n * @phy: the PHY to setup\n * @mac: the MAC to setup\n * @lc: the requested link configuration\n *\n * Set up a port's MAC and PHY according to a desired link configuration.\n * - If the PHY can auto-negotiate first decide what to advertise, then\n * enable/disable auto-negotiation as desired, and reset.\n * - If the PHY does not auto-negotiate just reset it.\n * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,\n * otherwise do it later based on the outcome of auto-negotiation.\n */\nint t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,\n\t\t struct link_config *lc)\n{\n\tstruct fw_port_cmd c;\n\tunsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);\n\n\tlc->link_ok = 0;\n\tif (lc->requested_fc & PAUSE_RX)\n\t\tfc |= FW_PORT_CAP_FC_RX;\n\tif (lc->requested_fc & PAUSE_TX)\n\t\tfc |= FW_PORT_CAP_FC_TX;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |\n\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_EXEC |\n\t\t\t\t V_FW_PORT_CMD_PORTID(port));\n\tc.action_to_len16 =\n\t\tcpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |\n\t\t\t FW_LEN16(c));\n\n\tif (!(lc->supported & FW_PORT_CAP_ANEG)) {\n\t\tc.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |\n\t\t\t\t\t fc);\n\t\tlc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);\n\t} else if (lc->autoneg == AUTONEG_DISABLE) {\n\t\tc.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);\n\t\tlc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);\n\t} else {\n\t\tc.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);\n\t}\n\n\treturn t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);\n}\n\n/**\n * t4_flash_cfg_addr - return the address of the flash configuration file\n * @adapter: the adapter\n *\n * Return the address within the flash where the Firmware Configuration\n * File is stored, or an error if the device FLASH is too small to contain\n * a Firmware Configuration File.\n */\nint t4_flash_cfg_addr(struct adapter *adapter)\n{\n\t/*\n\t * If the device FLASH isn't large enough to hold a Firmware\n\t * Configuration File, return an error.\n\t */\n\tif (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)\n\t\treturn -ENOSPC;\n\n\treturn FLASH_CFG_START;\n}\n\n#define PF_INTR_MASK (F_PFSW | F_PFCIM)\n\n/**\n * t4_intr_enable - enable interrupts\n * @adapter: the adapter whose interrupts should be enabled\n *\n * Enable PF-specific interrupts for the calling function and the top-level\n * interrupt concentrator for global interrupts. Interrupts are already\n * enabled at each module, here we just enable the roots of the interrupt\n * hierarchies.\n *\n * Note: this function should be called only when the driver manages\n * non PF-specific interrupts from the various HW modules. Only one PCI\n * function at a time should be doing this.\n */\nvoid t4_intr_enable(struct adapter *adapter)\n{\n\tu32 val = 0;\n\tu32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));\n\n\tif (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)\n\t\tval = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;\n\tt4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |\n\t\t F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |\n\t\t F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |\n\t\t F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |\n\t\t F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |\n\t\t F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |\n\t\t F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);\n\tt4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);\n\tt4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);\n}\n\n/**\n * t4_intr_disable - disable interrupts\n * @adapter: the adapter whose interrupts should be disabled\n *\n * Disable interrupts. We only disable the top-level interrupt\n * concentrators. The caller must be a PCI function managing global\n * interrupts.\n */\nvoid t4_intr_disable(struct adapter *adapter)\n{\n\tu32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));\n\n\tt4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);\n\tt4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);\n}\n\n/**\n * t4_get_port_type_description - return Port Type string description\n * @port_type: firmware Port Type enumeration\n */\nconst char *t4_get_port_type_description(enum fw_port_type port_type)\n{\n\tstatic const char * const port_type_description[] = {\n\t\t\"Fiber_XFI\",\n\t\t\"Fiber_XAUI\",\n\t\t\"BT_SGMII\",\n\t\t\"BT_XFI\",\n\t\t\"BT_XAUI\",\n\t\t\"KX4\",\n\t\t\"CX4\",\n\t\t\"KX\",\n\t\t\"KR\",\n\t\t\"SFP\",\n\t\t\"BP_AP\",\n\t\t\"BP4_AP\",\n\t\t\"QSFP_10G\",\n\t\t\"QSA\",\n\t\t\"QSFP\",\n\t\t\"BP40_BA\",\n\t};\n\n\tif (port_type < ARRAY_SIZE(port_type_description))\n\t\treturn port_type_description[port_type];\n\treturn \"UNKNOWN\";\n}\n\n/**\n * t4_get_mps_bg_map - return the buffer groups associated with a port\n * @adap: the adapter\n * @idx: the port index\n *\n * Returns a bitmap indicating which MPS buffer groups are associated\n * with the given port. Bit i is set if buffer group i is used by the\n * port.\n */\nunsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)\n{\n\tu32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));\n\n\tif (n == 0)\n\t\treturn idx == 0 ? 0xf : 0;\n\tif (n == 1)\n\t\treturn idx < 2 ? (3 << (2 * idx)) : 0;\n\treturn 1 << idx;\n}\n\n/**\n * t4_get_port_stats - collect port statistics\n * @adap: the adapter\n * @idx: the port index\n * @p: the stats structure to fill\n *\n * Collect statistics related to the given port from HW.\n */\nvoid t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)\n{\n\tu32 bgmap = t4_get_mps_bg_map(adap, idx);\n\n#define GET_STAT(name) \\\n\tt4_read_reg64(adap, \\\n\t\t (is_t4(adap->params.chip) ? \\\n\t\t PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) :\\\n\t\t T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))\n#define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)\n\n\tp->tx_octets = GET_STAT(TX_PORT_BYTES);\n\tp->tx_frames = GET_STAT(TX_PORT_FRAMES);\n\tp->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);\n\tp->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);\n\tp->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);\n\tp->tx_error_frames = GET_STAT(TX_PORT_ERROR);\n\tp->tx_frames_64 = GET_STAT(TX_PORT_64B);\n\tp->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);\n\tp->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);\n\tp->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);\n\tp->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);\n\tp->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);\n\tp->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);\n\tp->tx_drop = GET_STAT(TX_PORT_DROP);\n\tp->tx_pause = GET_STAT(TX_PORT_PAUSE);\n\tp->tx_ppp0 = GET_STAT(TX_PORT_PPP0);\n\tp->tx_ppp1 = GET_STAT(TX_PORT_PPP1);\n\tp->tx_ppp2 = GET_STAT(TX_PORT_PPP2);\n\tp->tx_ppp3 = GET_STAT(TX_PORT_PPP3);\n\tp->tx_ppp4 = GET_STAT(TX_PORT_PPP4);\n\tp->tx_ppp5 = GET_STAT(TX_PORT_PPP5);\n\tp->tx_ppp6 = GET_STAT(TX_PORT_PPP6);\n\tp->tx_ppp7 = GET_STAT(TX_PORT_PPP7);\n\n\tp->rx_octets = GET_STAT(RX_PORT_BYTES);\n\tp->rx_frames = GET_STAT(RX_PORT_FRAMES);\n\tp->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);\n\tp->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);\n\tp->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);\n\tp->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);\n\tp->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);\n\tp->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);\n\tp->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);\n\tp->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);\n\tp->rx_runt = GET_STAT(RX_PORT_LESS_64B);\n\tp->rx_frames_64 = GET_STAT(RX_PORT_64B);\n\tp->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);\n\tp->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);\n\tp->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);\n\tp->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);\n\tp->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);\n\tp->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);\n\tp->rx_pause = GET_STAT(RX_PORT_PAUSE);\n\tp->rx_ppp0 = GET_STAT(RX_PORT_PPP0);\n\tp->rx_ppp1 = GET_STAT(RX_PORT_PPP1);\n\tp->rx_ppp2 = GET_STAT(RX_PORT_PPP2);\n\tp->rx_ppp3 = GET_STAT(RX_PORT_PPP3);\n\tp->rx_ppp4 = GET_STAT(RX_PORT_PPP4);\n\tp->rx_ppp5 = GET_STAT(RX_PORT_PPP5);\n\tp->rx_ppp6 = GET_STAT(RX_PORT_PPP6);\n\tp->rx_ppp7 = GET_STAT(RX_PORT_PPP7);\n\tp->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;\n\tp->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;\n\tp->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;\n\tp->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;\n\tp->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;\n\tp->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;\n\tp->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;\n\tp->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;\n\n#undef GET_STAT\n#undef GET_STAT_COM\n}\n\n/**\n * t4_get_port_stats_offset - collect port stats relative to a previous snapshot\n * @adap: The adapter\n * @idx: The port\n * @stats: Current stats to fill\n * @offset: Previous stats snapshot\n */\nvoid t4_get_port_stats_offset(struct adapter *adap, int idx,\n\t\t\t struct port_stats *stats,\n\t\t\t struct port_stats *offset)\n{\n\tu64 *s, *o;\n\tunsigned int i;\n\n\tt4_get_port_stats(adap, idx, stats);\n\tfor (i = 0, s = (u64 *)stats, o = (u64 *)offset;\n\t i < (sizeof(struct port_stats) / sizeof(u64));\n\t i++, s++, o++)\n\t\t*s -= *o;\n}\n\n/**\n * t4_clr_port_stats - clear port statistics\n * @adap: the adapter\n * @idx: the port index\n *\n * Clear HW statistics for the given port.\n */\nvoid t4_clr_port_stats(struct adapter *adap, int idx)\n{\n\tunsigned int i;\n\tu32 bgmap = t4_get_mps_bg_map(adap, idx);\n\tu32 port_base_addr;\n\n\tif (is_t4(adap->params.chip))\n\t\tport_base_addr = PORT_BASE(idx);\n\telse\n\t\tport_base_addr = T5_PORT_BASE(idx);\n\n\tfor (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;\n\t i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)\n\t\tt4_write_reg(adap, port_base_addr + i, 0);\n\tfor (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;\n\t i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)\n\t\tt4_write_reg(adap, port_base_addr + i, 0);\n\tfor (i = 0; i < 4; i++)\n\t\tif (bgmap & (1 << i)) {\n\t\t\tt4_write_reg(adap,\n\t\t\t\t A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +\n\t\t\t\t i * 8, 0);\n\t\t\tt4_write_reg(adap,\n\t\t\t\t A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +\n\t\t\t\t i * 8, 0);\n\t\t}\n}\n\n/**\n * t4_fw_hello - establish communication with FW\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @evt_mbox: mailbox to receive async FW events\n * @master: specifies the caller's willingness to be the device master\n * @state: returns the current device state (if non-NULL)\n *\n * Issues a command to establish communication with FW. Returns either\n * an error (negative integer) or the mailbox of the Master PF.\n */\nint t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,\n\t\tenum dev_master master, enum dev_state *state)\n{\n\tint ret;\n\tstruct fw_hello_cmd c;\n\tu32 v;\n\tunsigned int master_mbox;\n\tint retries = FW_CMD_HELLO_RETRIES;\n\nretry:\n\tmemset(&c, 0, sizeof(c));\n\tINIT_CMD(c, HELLO, WRITE);\n\tc.err_to_clearinit = cpu_to_be32(\n\t\t\tV_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |\n\t\t\tV_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |\n\t\t\tV_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :\n\t\t\t\t\t\tM_FW_HELLO_CMD_MBMASTER) |\n\t\t\tV_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |\n\t\t\tV_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |\n\t\t\tF_FW_HELLO_CMD_CLEARINIT);\n\n\t/*\n\t * Issue the HELLO command to the firmware. If it's not successful\n\t * but indicates that we got a \"busy\" or \"timeout\" condition, retry\n\t * the HELLO until we exhaust our retry limit. If we do exceed our\n\t * retry limit, check to see if the firmware left us any error\n\t * information and report that if so ...\n\t */\n\tret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);\n\tif (ret != FW_SUCCESS) {\n\t\tif ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)\n\t\t\tgoto retry;\n\t\tif (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)\n\t\t\tt4_report_fw_error(adap);\n\t\treturn ret;\n\t}\n\n\tv = be32_to_cpu(c.err_to_clearinit);\n\tmaster_mbox = G_FW_HELLO_CMD_MBMASTER(v);\n\tif (state) {\n\t\tif (v & F_FW_HELLO_CMD_ERR)\n\t\t\t*state = DEV_STATE_ERR;\n\t\telse if (v & F_FW_HELLO_CMD_INIT)\n\t\t\t*state = DEV_STATE_INIT;\n\t\telse\n\t\t\t*state = DEV_STATE_UNINIT;\n\t}\n\n\t/*\n\t * If we're not the Master PF then we need to wait around for the\n\t * Master PF Driver to finish setting up the adapter.\n\t *\n\t * Note that we also do this wait if we're a non-Master-capable PF and\n\t * there is no current Master PF; a Master PF may show up momentarily\n\t * and we wouldn't want to fail pointlessly. (This can happen when an\n\t * OS loads lots of different drivers rapidly at the same time). In\n\t * this case, the Master PF returned by the firmware will be\n\t * M_PCIE_FW_MASTER so the test below will work ...\n\t */\n\tif ((v & (F_FW_HELLO_CMD_ERR | F_FW_HELLO_CMD_INIT)) == 0 &&\n\t master_mbox != mbox) {\n\t\tint waiting = FW_CMD_HELLO_TIMEOUT;\n\n\t\t/*\n\t\t * Wait for the firmware to either indicate an error or\n\t\t * initialized state. If we see either of these we bail out\n\t\t * and report the issue to the caller. If we exhaust the\n\t\t * \"hello timeout\" and we haven't exhausted our retries, try\n\t\t * again. Otherwise bail with a timeout error.\n\t\t */\n\t\tfor (;;) {\n\t\t\tu32 pcie_fw;\n\n\t\t\tmsleep(50);\n\t\t\twaiting -= 50;\n\n\t\t\t/*\n\t\t\t * If neither Error nor Initialialized are indicated\n\t\t\t * by the firmware keep waiting till we exaust our\n\t\t\t * timeout ... and then retry if we haven't exhausted\n\t\t\t * our retries ...\n\t\t\t */\n\t\t\tpcie_fw = t4_read_reg(adap, A_PCIE_FW);\n\t\t\tif (!(pcie_fw & (F_PCIE_FW_ERR | F_PCIE_FW_INIT))) {\n\t\t\t\tif (waiting <= 0) {\n\t\t\t\t\tif (retries-- > 0)\n\t\t\t\t\t\tgoto retry;\n\n\t\t\t\t\treturn -ETIMEDOUT;\n\t\t\t\t}\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * We either have an Error or Initialized condition\n\t\t\t * report errors preferentially.\n\t\t\t */\n\t\t\tif (state) {\n\t\t\t\tif (pcie_fw & F_PCIE_FW_ERR)\n\t\t\t\t\t*state = DEV_STATE_ERR;\n\t\t\t\telse if (pcie_fw & F_PCIE_FW_INIT)\n\t\t\t\t\t*state = DEV_STATE_INIT;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * If we arrived before a Master PF was selected and\n\t\t\t * there's not a valid Master PF, grab its identity\n\t\t\t * for our caller.\n\t\t\t */\n\t\t\tif (master_mbox == M_PCIE_FW_MASTER &&\n\t\t\t (pcie_fw & F_PCIE_FW_MASTER_VLD))\n\t\t\t\tmaster_mbox = G_PCIE_FW_MASTER(pcie_fw);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn master_mbox;\n}\n\n/**\n * t4_fw_bye - end communication with FW\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n *\n * Issues a command to terminate communication with FW.\n */\nint t4_fw_bye(struct adapter *adap, unsigned int mbox)\n{\n\tstruct fw_bye_cmd c;\n\n\tmemset(&c, 0, sizeof(c));\n\tINIT_CMD(c, BYE, WRITE);\n\treturn t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);\n}\n\n/**\n * t4_fw_reset - issue a reset to FW\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @reset: specifies the type of reset to perform\n *\n * Issues a reset command of the specified type to FW.\n */\nint t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)\n{\n\tstruct fw_reset_cmd c;\n\n\tmemset(&c, 0, sizeof(c));\n\tINIT_CMD(c, RESET, WRITE);\n\tc.val = cpu_to_be32(reset);\n\treturn t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);\n}\n\n/**\n * t4_fw_halt - issue a reset/halt to FW and put uP into RESET\n * @adap: the adapter\n * @mbox: mailbox to use for the FW RESET command (if desired)\n * @force: force uP into RESET even if FW RESET command fails\n *\n * Issues a RESET command to firmware (if desired) with a HALT indication\n * and then puts the microprocessor into RESET state. The RESET command\n * will only be issued if a legitimate mailbox is provided (mbox <=\n * M_PCIE_FW_MASTER).\n *\n * This is generally used in order for the host to safely manipulate the\n * adapter without fear of conflicting with whatever the firmware might\n * be doing. The only way out of this state is to RESTART the firmware\n * ...\n */\nint t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)\n{\n\tint ret = 0;\n\n\t/*\n\t * If a legitimate mailbox is provided, issue a RESET command\n\t * with a HALT indication.\n\t */\n\tif (mbox <= M_PCIE_FW_MASTER) {\n\t\tstruct fw_reset_cmd c;\n\n\t\tmemset(&c, 0, sizeof(c));\n\t\tINIT_CMD(c, RESET, WRITE);\n\t\tc.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);\n\t\tc.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);\n\t\tret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);\n\t}\n\n\t/*\n\t * Normally we won't complete the operation if the firmware RESET\n\t * command fails but if our caller insists we'll go ahead and put the\n\t * uP into RESET. This can be useful if the firmware is hung or even\n\t * missing ... We'll have to take the risk of putting the uP into\n\t * RESET without the cooperation of firmware in that case.\n\t *\n\t * We also force the firmware's HALT flag to be on in case we bypassed\n\t * the firmware RESET command above or we're dealing with old firmware\n\t * which doesn't have the HALT capability. This will serve as a flag\n\t * for the incoming firmware to know that it's coming out of a HALT\n\t * rather than a RESET ... if it's new enough to understand that ...\n\t */\n\tif (ret == 0 || force) {\n\t\tt4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);\n\t\tt4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,\n\t\t\t\t F_PCIE_FW_HALT);\n\t}\n\n\t/*\n\t * And we always return the result of the firmware RESET command\n\t * even when we force the uP into RESET ...\n\t */\n\treturn ret;\n}\n\n/**\n * t4_fw_restart - restart the firmware by taking the uP out of RESET\n * @adap: the adapter\n * @mbox: mailbox to use for the FW RESET command (if desired)\n * @reset: if we want to do a RESET to restart things\n *\n * Restart firmware previously halted by t4_fw_halt(). On successful\n * return the previous PF Master remains as the new PF Master and there\n * is no need to issue a new HELLO command, etc.\n *\n * We do this in two ways:\n *\n * 1. If we're dealing with newer firmware we'll simply want to take\n * the chip's microprocessor out of RESET. This will cause the\n * firmware to start up from its start vector. And then we'll loop\n * until the firmware indicates it's started again (PCIE_FW.HALT\n * reset to 0) or we timeout.\n *\n * 2. If we're dealing with older firmware then we'll need to RESET\n * the chip since older firmware won't recognize the PCIE_FW.HALT\n * flag and automatically RESET itself on startup.\n */\nint t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)\n{\n\tif (reset) {\n\t\t/*\n\t\t * Since we're directing the RESET instead of the firmware\n\t\t * doing it automatically, we need to clear the PCIE_FW.HALT\n\t\t * bit.\n\t\t */\n\t\tt4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);\n\n\t\t/*\n\t\t * If we've been given a valid mailbox, first try to get the\n\t\t * firmware to do the RESET. If that works, great and we can\n\t\t * return success. Otherwise, if we haven't been given a\n\t\t * valid mailbox or the RESET command failed, fall back to\n\t\t * hitting the chip with a hammer.\n\t\t */\n\t\tif (mbox <= M_PCIE_FW_MASTER) {\n\t\t\tt4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);\n\t\t\tmsleep(100);\n\t\t\tif (t4_fw_reset(adap, mbox,\n\t\t\t\t\tF_PIORST | F_PIORSTMODE) == 0)\n\t\t\t\treturn 0;\n\t\t}\n\n\t\tt4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);\n\t\tmsleep(2000);\n\t} else {\n\t\tint ms;\n\n\t\tt4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);\n\t\tfor (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {\n\t\t\tif (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))\n\t\t\t\treturn FW_SUCCESS;\n\t\t\tmsleep(100);\n\t\t\tms += 100;\n\t\t}\n\t\treturn -ETIMEDOUT;\n\t}\n\treturn 0;\n}\n\n/**\n * t4_fixup_host_params_compat - fix up host-dependent parameters\n * @adap: the adapter\n * @page_size: the host's Base Page Size\n * @cache_line_size: the host's Cache Line Size\n * @chip_compat: maintain compatibility with designated chip\n *\n * Various registers in the chip contain values which are dependent on the\n * host's Base Page and Cache Line Sizes. This function will fix all of\n * those registers with the appropriate values as passed in ...\n *\n * @chip_compat is used to limit the set of changes that are made\n * to be compatible with the indicated chip release. This is used by\n * drivers to maintain compatibility with chip register settings when\n * the drivers haven't [yet] been updated with new chip support.\n */\nint t4_fixup_host_params_compat(struct adapter *adap,\n\t\t\t\tunsigned int page_size,\n\t\t\t\tunsigned int cache_line_size,\n\t\t\t\tenum chip_type chip_compat)\n{\n\tunsigned int page_shift = cxgbe_fls(page_size) - 1;\n\tunsigned int sge_hps = page_shift - 10;\n\tunsigned int stat_len = cache_line_size > 64 ? 128 : 64;\n\tunsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;\n\tunsigned int fl_align_log = cxgbe_fls(fl_align) - 1;\n\n\tt4_write_reg(adap, A_SGE_HOST_PAGE_SIZE,\n\t\t V_HOSTPAGESIZEPF0(sge_hps) |\n\t\t V_HOSTPAGESIZEPF1(sge_hps) |\n\t\t V_HOSTPAGESIZEPF2(sge_hps) |\n\t\t V_HOSTPAGESIZEPF3(sge_hps) |\n\t\t V_HOSTPAGESIZEPF4(sge_hps) |\n\t\t V_HOSTPAGESIZEPF5(sge_hps) |\n\t\t V_HOSTPAGESIZEPF6(sge_hps) |\n\t\t V_HOSTPAGESIZEPF7(sge_hps));\n\n\tif (is_t4(adap->params.chip) || is_t4(chip_compat))\n\t\tt4_set_reg_field(adap, A_SGE_CONTROL,\n\t\t\t\t V_INGPADBOUNDARY(M_INGPADBOUNDARY) |\n\t\t\t\t F_EGRSTATUSPAGESIZE,\n\t\t\t\t V_INGPADBOUNDARY(fl_align_log -\n\t\t\t\t\t\t X_INGPADBOUNDARY_SHIFT) |\n\t\t\t\tV_EGRSTATUSPAGESIZE(stat_len != 64));\n\telse {\n\t\t/*\n\t\t * T5 introduced the separation of the Free List Padding and\n\t\t * Packing Boundaries. Thus, we can select a smaller Padding\n\t\t * Boundary to avoid uselessly chewing up PCIe Link and Memory\n\t\t * Bandwidth, and use a Packing Boundary which is large enough\n\t\t * to avoid false sharing between CPUs, etc.\n\t\t *\n\t\t * For the PCI Link, the smaller the Padding Boundary the\n\t\t * better. For the Memory Controller, a smaller Padding\n\t\t * Boundary is better until we cross under the Memory Line\n\t\t * Size (the minimum unit of transfer to/from Memory). If we\n\t\t * have a Padding Boundary which is smaller than the Memory\n\t\t * Line Size, that'll involve a Read-Modify-Write cycle on the\n\t\t * Memory Controller which is never good. For T5 the smallest\n\t\t * Padding Boundary which we can select is 32 bytes which is\n\t\t * larger than any known Memory Controller Line Size so we'll\n\t\t * use that.\n\t\t */\n\n\t\t/*\n\t\t * N.B. T5 has a different interpretation of the \"0\" value for\n\t\t * the Packing Boundary. This corresponds to 16 bytes instead\n\t\t * of the expected 32 bytes. We never have a Packing Boundary\n\t\t * less than 32 bytes so we can't use that special value but\n\t\t * on the other hand, if we wanted 32 bytes, the best we can\n\t\t * really do is 64 bytes ...\n\t\t */\n\t\tif (fl_align <= 32) {\n\t\t\tfl_align = 64;\n\t\t\tfl_align_log = 6;\n\t\t}\n\t\tt4_set_reg_field(adap, A_SGE_CONTROL,\n\t\t\t\t V_INGPADBOUNDARY(M_INGPADBOUNDARY) |\n\t\t\t\t F_EGRSTATUSPAGESIZE,\n\t\t\t\t V_INGPADBOUNDARY(X_INGPCIEBOUNDARY_32B) |\n\t\t\t\t V_EGRSTATUSPAGESIZE(stat_len != 64));\n\t\tt4_set_reg_field(adap, A_SGE_CONTROL2,\n\t\t\t\t V_INGPACKBOUNDARY(M_INGPACKBOUNDARY),\n\t\t\t\t V_INGPACKBOUNDARY(fl_align_log -\n\t\t\t\t\t\t X_INGPACKBOUNDARY_SHIFT));\n\t}\n\n\t/*\n\t * Adjust various SGE Free List Host Buffer Sizes.\n\t *\n\t * The first four entries are:\n\t *\n\t * 0: Host Page Size\n\t * 1: 64KB\n\t * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)\n\t * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)\n\t *\n\t * For the single-MTU buffers in unpacked mode we need to include\n\t * space for the SGE Control Packet Shift, 14 byte Ethernet header,\n\t * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet\n\t * Padding boundary. All of these are accommodated in the Factory\n\t * Default Firmware Configuration File but we need to adjust it for\n\t * this host's cache line size.\n\t */\n\tt4_write_reg(adap, A_SGE_FL_BUFFER_SIZE0, page_size);\n\tt4_write_reg(adap, A_SGE_FL_BUFFER_SIZE2,\n\t\t (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE2) + fl_align - 1)\n\t\t & ~(fl_align - 1));\n\tt4_write_reg(adap, A_SGE_FL_BUFFER_SIZE3,\n\t\t (t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE3) + fl_align - 1)\n\t\t & ~(fl_align - 1));\n\n\tt4_write_reg(adap, A_ULP_RX_TDDP_PSZ, V_HPZ0(page_shift - 12));\n\n\treturn 0;\n}\n\n/**\n * t4_fixup_host_params - fix up host-dependent parameters (T4 compatible)\n * @adap: the adapter\n * @page_size: the host's Base Page Size\n * @cache_line_size: the host's Cache Line Size\n *\n * Various registers in T4 contain values which are dependent on the\n * host's Base Page and Cache Line Sizes. This function will fix all of\n * those registers with the appropriate values as passed in ...\n *\n * This routine makes changes which are compatible with T4 chips.\n */\nint t4_fixup_host_params(struct adapter *adap, unsigned int page_size,\n\t\t\t unsigned int cache_line_size)\n{\n\treturn t4_fixup_host_params_compat(adap, page_size, cache_line_size,\n\t\t\t\t\t T4_LAST_REV);\n}\n\n/**\n * t4_fw_initialize - ask FW to initialize the device\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n *\n * Issues a command to FW to partially initialize the device. This\n * performs initialization that generally doesn't depend on user input.\n */\nint t4_fw_initialize(struct adapter *adap, unsigned int mbox)\n{\n\tstruct fw_initialize_cmd c;\n\n\tmemset(&c, 0, sizeof(c));\n\tINIT_CMD(c, INITIALIZE, WRITE);\n\treturn t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);\n}\n\n/**\n * t4_query_params_rw - query FW or device parameters\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @pf: the PF\n * @vf: the VF\n * @nparams: the number of parameters\n * @params: the parameter names\n * @val: the parameter values\n * @rw: Write and read flag\n *\n * Reads the value of FW or device parameters. Up to 7 parameters can be\n * queried at once.\n */\nstatic int t4_query_params_rw(struct adapter *adap, unsigned int mbox,\n\t\t\t unsigned int pf, unsigned int vf,\n\t\t\t unsigned int nparams, const u32 *params,\n\t\t\t u32 *val, int rw)\n{\n\tunsigned int i;\n\tint ret;\n\tstruct fw_params_cmd c;\n\t__be32 *p = &c.param[0].mnem;\n\n\tif (nparams > 7)\n\t\treturn -EINVAL;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |\n\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_READ |\n\t\t\t\t V_FW_PARAMS_CMD_PFN(pf) |\n\t\t\t\t V_FW_PARAMS_CMD_VFN(vf));\n\tc.retval_len16 = cpu_to_be32(FW_LEN16(c));\n\n\tfor (i = 0; i < nparams; i++) {\n\t\t*p++ = cpu_to_be32(*params++);\n\t\tif (rw)\n\t\t\t*p = cpu_to_be32(*(val + i));\n\t\tp++;\n\t}\n\n\tret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);\n\tif (ret == 0)\n\t\tfor (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)\n\t\t\t*val++ = be32_to_cpu(*p);\n\treturn ret;\n}\n\nint t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,\n\t\t unsigned int vf, unsigned int nparams, const u32 *params,\n\t\t u32 *val)\n{\n\treturn t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);\n}\n\n/**\n * t4_set_params_timeout - sets FW or device parameters\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @pf: the PF\n * @vf: the VF\n * @nparams: the number of parameters\n * @params: the parameter names\n * @val: the parameter values\n * @timeout: the timeout time\n *\n * Sets the value of FW or device parameters. Up to 7 parameters can be\n * specified at once.\n */\nint t4_set_params_timeout(struct adapter *adap, unsigned int mbox,\n\t\t\t unsigned int pf, unsigned int vf,\n\t\t\t unsigned int nparams, const u32 *params,\n\t\t\t const u32 *val, int timeout)\n{\n\tstruct fw_params_cmd c;\n\t__be32 *p = &c.param[0].mnem;\n\n\tif (nparams > 7)\n\t\treturn -EINVAL;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |\n\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_WRITE |\n\t\t\t\t V_FW_PARAMS_CMD_PFN(pf) |\n\t\t\t\t V_FW_PARAMS_CMD_VFN(vf));\n\tc.retval_len16 = cpu_to_be32(FW_LEN16(c));\n\n\twhile (nparams--) {\n\t\t*p++ = cpu_to_be32(*params++);\n\t\t*p++ = cpu_to_be32(*val++);\n\t}\n\n\treturn t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);\n}\n\nint t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,\n\t\t unsigned int vf, unsigned int nparams, const u32 *params,\n\t\t const u32 *val)\n{\n\treturn t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,\n\t\t\t\t FW_CMD_MAX_TIMEOUT);\n}\n\n/**\n * t4_alloc_vi_func - allocate a virtual interface\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @port: physical port associated with the VI\n * @pf: the PF owning the VI\n * @vf: the VF owning the VI\n * @nmac: number of MAC addresses needed (1 to 5)\n * @mac: the MAC addresses of the VI\n * @rss_size: size of RSS table slice associated with this VI\n * @portfunc: which Port Application Function MAC Address is desired\n * @idstype: Intrusion Detection Type\n *\n * Allocates a virtual interface for the given physical port. If @mac is\n * not %NULL it contains the MAC addresses of the VI as assigned by FW.\n * @mac should be large enough to hold @nmac Ethernet addresses, they are\n * stored consecutively so the space needed is @nmac * 6 bytes.\n * Returns a negative error number or the non-negative VI id.\n */\nint t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,\n\t\t unsigned int port, unsigned int pf, unsigned int vf,\n\t\t unsigned int nmac, u8 *mac, unsigned int *rss_size,\n\t\t unsigned int portfunc, unsigned int idstype)\n{\n\tint ret;\n\tstruct fw_vi_cmd c;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |\n\t\t\t\t F_FW_CMD_WRITE | F_FW_CMD_EXEC |\n\t\t\t\t V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));\n\tc.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));\n\tc.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |\n\t\t\t\t V_FW_VI_CMD_FUNC(portfunc));\n\tc.portid_pkd = V_FW_VI_CMD_PORTID(port);\n\tc.nmac = nmac - 1;\n\n\tret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);\n\tif (ret)\n\t\treturn ret;\n\n\tif (mac) {\n\t\tmemcpy(mac, c.mac, sizeof(c.mac));\n\t\tswitch (nmac) {\n\t\tcase 5:\n\t\t\tmemcpy(mac + 24, c.nmac3, sizeof(c.nmac3));\n\t\t\t/* FALLTHROUGH */\n\t\tcase 4:\n\t\t\tmemcpy(mac + 18, c.nmac2, sizeof(c.nmac2));\n\t\t\t/* FALLTHROUGH */\n\t\tcase 3:\n\t\t\tmemcpy(mac + 12, c.nmac1, sizeof(c.nmac1));\n\t\t\t/* FALLTHROUGH */\n\t\tcase 2:\n\t\t\tmemcpy(mac + 6, c.nmac0, sizeof(c.nmac0));\n\t\t\t/* FALLTHROUGH */\n\t\t}\n\t}\n\tif (rss_size)\n\t\t*rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));\n\treturn G_FW_VI_CMD_VIID(cpu_to_be16(c.type_to_viid));\n}\n\n/**\n * t4_alloc_vi - allocate an [Ethernet Function] virtual interface\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @port: physical port associated with the VI\n * @pf: the PF owning the VI\n * @vf: the VF owning the VI\n * @nmac: number of MAC addresses needed (1 to 5)\n * @mac: the MAC addresses of the VI\n * @rss_size: size of RSS table slice associated with this VI\n *\n * Backwards compatible and convieniance routine to allocate a Virtual\n * Interface with a Ethernet Port Application Function and Intrustion\n * Detection System disabled.\n */\nint t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,\n\t\tunsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,\n\t\tunsigned int *rss_size)\n{\n\treturn t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,\n\t\t\t\tFW_VI_FUNC_ETH, 0);\n}\n\n/**\n * t4_free_vi - free a virtual interface\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @pf: the PF owning the VI\n * @vf: the VF owning the VI\n * @viid: virtual interface identifiler\n *\n * Free a previously allocated virtual interface.\n */\nint t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,\n\t unsigned int vf, unsigned int viid)\n{\n\tstruct fw_vi_cmd c;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |\n\t\t\t\t F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) |\n\t\t\t\t V_FW_VI_CMD_VFN(vf));\n\tc.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));\n\tc.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));\n\n\treturn t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);\n}\n\n/**\n * t4_set_rxmode - set Rx properties of a virtual interface\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @viid: the VI id\n * @mtu: the new MTU or -1\n * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change\n * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change\n * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change\n * @vlanex: 1 to enable hardware VLAN Tag extraction, 0 to disable it,\n * -1 no change\n * @sleep_ok: if true we may sleep while awaiting command completion\n *\n * Sets Rx properties of a virtual interface.\n */\nint t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,\n\t\t int mtu, int promisc, int all_multi, int bcast, int vlanex,\n\t\t bool sleep_ok)\n{\n\tstruct fw_vi_rxmode_cmd c;\n\n\t/* convert to FW values */\n\tif (mtu < 0)\n\t\tmtu = M_FW_VI_RXMODE_CMD_MTU;\n\tif (promisc < 0)\n\t\tpromisc = M_FW_VI_RXMODE_CMD_PROMISCEN;\n\tif (all_multi < 0)\n\t\tall_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;\n\tif (bcast < 0)\n\t\tbcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;\n\tif (vlanex < 0)\n\t\tvlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |\n\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_WRITE |\n\t\t\t\t V_FW_VI_RXMODE_CMD_VIID(viid));\n\tc.retval_len16 = cpu_to_be32(FW_LEN16(c));\n\tc.mtu_to_vlanexen = cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |\n\t\t\t V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |\n\t\t\t V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |\n\t\t\t V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |\n\t\t\t V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));\n\treturn t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);\n}\n\n/**\n * t4_change_mac - modifies the exact-match filter for a MAC address\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @viid: the VI id\n * @idx: index of existing filter for old value of MAC address, or -1\n * @addr: the new MAC address value\n * @persist: whether a new MAC allocation should be persistent\n * @add_smt: if true also add the address to the HW SMT\n *\n * Modifies an exact-match filter and sets it to the new MAC address if\n * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the\n * latter case the address is added persistently if @persist is %true.\n *\n * Note that in general it is not possible to modify the value of a given\n * filter so the generic way to modify an address filter is to free the one\n * being used by the old address value and allocate a new filter for the\n * new address value.\n *\n * Returns a negative error number or the index of the filter with the new\n * MAC value. Note that this index may differ from @idx.\n */\nint t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,\n\t\t int idx, const u8 *addr, bool persist, bool add_smt)\n{\n\tint ret, mode;\n\tstruct fw_vi_mac_cmd c;\n\tstruct fw_vi_mac_exact *p = c.u.exact;\n\tint max_mac_addr = adap->params.arch.mps_tcam_size;\n\n\tif (idx < 0) /* new allocation */\n\t\tidx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;\n\tmode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |\n\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_WRITE |\n\t\t\t\t V_FW_VI_MAC_CMD_VIID(viid));\n\tc.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));\n\tp->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |\n\t\t\t\t V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |\n\t\t\t\t V_FW_VI_MAC_CMD_IDX(idx));\n\tmemcpy(p->macaddr, addr, sizeof(p->macaddr));\n\n\tret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);\n\tif (ret == 0) {\n\t\tret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));\n\t\tif (ret >= max_mac_addr)\n\t\t\tret = -ENOMEM;\n\t}\n\treturn ret;\n}\n\n/**\n * t4_enable_vi_params - enable/disable a virtual interface\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @viid: the VI id\n * @rx_en: 1=enable Rx, 0=disable Rx\n * @tx_en: 1=enable Tx, 0=disable Tx\n * @dcb_en: 1=enable delivery of Data Center Bridging messages.\n *\n * Enables/disables a virtual interface. Note that setting DCB Enable\n * only makes sense when enabling a Virtual Interface ...\n */\nint t4_enable_vi_params(struct adapter *adap, unsigned int mbox,\n\t\t\tunsigned int viid, bool rx_en, bool tx_en, bool dcb_en)\n{\n\tstruct fw_vi_enable_cmd c;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |\n\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_EXEC |\n\t\t\t\t V_FW_VI_ENABLE_CMD_VIID(viid));\n\tc.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |\n\t\t\t\t V_FW_VI_ENABLE_CMD_EEN(tx_en) |\n\t\t\t\t V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |\n\t\t\t\t FW_LEN16(c));\n\treturn t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);\n}\n\n/**\n * t4_enable_vi - enable/disable a virtual interface\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @viid: the VI id\n * @rx_en: 1=enable Rx, 0=disable Rx\n * @tx_en: 1=enable Tx, 0=disable Tx\n *\n * Enables/disables a virtual interface. Note that setting DCB Enable\n * only makes sense when enabling a Virtual Interface ...\n */\nint t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,\n\t\t bool rx_en, bool tx_en)\n{\n\treturn t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);\n}\n\n/**\n * t4_iq_start_stop - enable/disable an ingress queue and its FLs\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @start: %true to enable the queues, %false to disable them\n * @pf: the PF owning the queues\n * @vf: the VF owning the queues\n * @iqid: ingress queue id\n * @fl0id: FL0 queue id or 0xffff if no attached FL0\n * @fl1id: FL1 queue id or 0xffff if no attached FL1\n *\n * Starts or stops an ingress queue and its associated FLs, if any.\n */\nint t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,\n\t\t unsigned int pf, unsigned int vf, unsigned int iqid,\n\t\t unsigned int fl0id, unsigned int fl1id)\n{\n\tstruct fw_iq_cmd c;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |\n\t\t\t\t F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |\n\t\t\t\t V_FW_IQ_CMD_VFN(vf));\n\tc.alloc_to_len16 = cpu_to_be32(V_FW_IQ_CMD_IQSTART(start) |\n\t\t\t\t V_FW_IQ_CMD_IQSTOP(!start) |\n\t\t\t\t FW_LEN16(c));\n\tc.iqid = cpu_to_be16(iqid);\n\tc.fl0id = cpu_to_be16(fl0id);\n\tc.fl1id = cpu_to_be16(fl1id);\n\treturn t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);\n}\n\n/**\n * t4_iq_free - free an ingress queue and its FLs\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @pf: the PF owning the queues\n * @vf: the VF owning the queues\n * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)\n * @iqid: ingress queue id\n * @fl0id: FL0 queue id or 0xffff if no attached FL0\n * @fl1id: FL1 queue id or 0xffff if no attached FL1\n *\n * Frees an ingress queue and its associated FLs, if any.\n */\nint t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,\n\t unsigned int vf, unsigned int iqtype, unsigned int iqid,\n\t unsigned int fl0id, unsigned int fl1id)\n{\n\tstruct fw_iq_cmd c;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |\n\t\t\t\t F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |\n\t\t\t\t V_FW_IQ_CMD_VFN(vf));\n\tc.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));\n\tc.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));\n\tc.iqid = cpu_to_be16(iqid);\n\tc.fl0id = cpu_to_be16(fl0id);\n\tc.fl1id = cpu_to_be16(fl1id);\n\treturn t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);\n}\n\n/**\n * t4_eth_eq_free - free an Ethernet egress queue\n * @adap: the adapter\n * @mbox: mailbox to use for the FW command\n * @pf: the PF owning the queue\n * @vf: the VF owning the queue\n * @eqid: egress queue id\n *\n * Frees an Ethernet egress queue.\n */\nint t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,\n\t\t unsigned int vf, unsigned int eqid)\n{\n\tstruct fw_eq_eth_cmd c;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |\n\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_EXEC |\n\t\t\t\t V_FW_EQ_ETH_CMD_PFN(pf) |\n\t\t\t\t V_FW_EQ_ETH_CMD_VFN(vf));\n\tc.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));\n\tc.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));\n\treturn t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);\n}\n\n/**\n * t4_handle_fw_rpl - process a FW reply message\n * @adap: the adapter\n * @rpl: start of the FW message\n *\n * Processes a FW message, such as link state change messages.\n */\nint t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)\n{\n\tu8 opcode = *(const u8 *)rpl;\n\n\t/*\n\t * This might be a port command ... this simplifies the following\n\t * conditionals ... We can get away with pre-dereferencing\n\t * action_to_len16 because it's in the first 16 bytes and all messages\n\t * will be at least that long.\n\t */\n\tconst struct fw_port_cmd *p = (const void *)rpl;\n\tunsigned int action =\n\t\tG_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));\n\n\tif (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {\n\t\t/* link/module state change message */\n\t\tint speed = 0, fc = 0, i;\n\t\tint chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));\n\t\tstruct port_info *pi = NULL;\n\t\tstruct link_config *lc;\n\t\tu32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);\n\t\tint link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;\n\t\tu32 mod = G_FW_PORT_CMD_MODTYPE(stat);\n\n\t\tif (stat & F_FW_PORT_CMD_RXPAUSE)\n\t\t\tfc |= PAUSE_RX;\n\t\tif (stat & F_FW_PORT_CMD_TXPAUSE)\n\t\t\tfc |= PAUSE_TX;\n\t\tif (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))\n\t\t\tspeed = ETH_LINK_SPEED_100;\n\t\telse if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))\n\t\t\tspeed = ETH_LINK_SPEED_1000;\n\t\telse if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))\n\t\t\tspeed = ETH_LINK_SPEED_10000;\n\t\telse if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))\n\t\t\tspeed = ETH_LINK_SPEED_40G;\n\n\t\tfor_each_port(adap, i) {\n\t\t\tpi = adap2pinfo(adap, i);\n\t\t\tif (pi->tx_chan == chan)\n\t\t\t\tbreak;\n\t\t}\n\t\tlc = &pi->link_cfg;\n\n\t\tif (mod != pi->mod_type) {\n\t\t\tpi->mod_type = mod;\n\t\t\tt4_os_portmod_changed(adap, i);\n\t\t}\n\t\tif (link_ok != lc->link_ok || speed != lc->speed ||\n\t\t fc != lc->fc) { /* something changed */\n\t\t\tif (!link_ok && lc->link_ok) {\n\t\t\t\tstatic const char * const reason[] = {\n\t\t\t\t\t\"Link Down\",\n\t\t\t\t\t\"Remote Fault\",\n\t\t\t\t\t\"Auto-negotiation Failure\",\n\t\t\t\t\t\"Reserved\",\n\t\t\t\t\t\"Insufficient Airflow\",\n\t\t\t\t\t\"Unable To Determine Reason\",\n\t\t\t\t\t\"No RX Signal Detected\",\n\t\t\t\t\t\"Reserved\",\n\t\t\t\t};\n\t\t\t\tunsigned int rc = G_FW_PORT_CMD_LINKDNRC(stat);\n\n\t\t\t\tdev_warn(adap, \"Port %d link down, reason: %s\\n\",\n\t\t\t\t\t chan, reason[rc]);\n\t\t\t}\n\t\t\tlc->link_ok = link_ok;\n\t\t\tlc->speed = speed;\n\t\t\tlc->fc = fc;\n\t\t\tlc->supported = be16_to_cpu(p->u.info.pcap);\n\t\t}\n\t} else {\n\t\tdev_warn(adap, \"Unknown firmware reply %d\\n\", opcode);\n\t\treturn -EINVAL;\n\t}\n\treturn 0;\n}\n\nvoid t4_reset_link_config(struct adapter *adap, int idx)\n{\n\tstruct port_info *pi = adap2pinfo(adap, idx);\n\tstruct link_config *lc = &pi->link_cfg;\n\n\tlc->link_ok = 0;\n\tlc->requested_speed = 0;\n\tlc->requested_fc = 0;\n\tlc->speed = 0;\n\tlc->fc = 0;\n}\n\n/**\n * init_link_config - initialize a link's SW state\n * @lc: structure holding the link state\n * @caps: link capabilities\n *\n * Initializes the SW state maintained for each link, including the link's\n * capabilities and default speed/flow-control/autonegotiation settings.\n */\nstatic void init_link_config(struct link_config *lc,\n\t\t\t unsigned int caps)\n{\n\tlc->supported = caps;\n\tlc->requested_speed = 0;\n\tlc->speed = 0;\n\tlc->requested_fc = 0;\n\tlc->fc = 0;\n\tif (lc->supported & FW_PORT_CAP_ANEG) {\n\t\tlc->advertising = lc->supported & ADVERT_MASK;\n\t\tlc->autoneg = AUTONEG_ENABLE;\n\t} else {\n\t\tlc->advertising = 0;\n\t\tlc->autoneg = AUTONEG_DISABLE;\n\t}\n}\n\n/**\n * t4_wait_dev_ready - wait till to reads of registers work\n *\n * Right after the device is RESET is can take a small amount of time\n * for it to respond to register reads. Until then, all reads will\n * return either 0xff...ff or 0xee...ee. Return an error if reads\n * don't work within a reasonable time frame.\n */\nstatic int t4_wait_dev_ready(struct adapter *adapter)\n{\n\tu32 whoami;\n\n\twhoami = t4_read_reg(adapter, A_PL_WHOAMI);\n\n\tif (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS)\n\t\treturn 0;\n\n\tmsleep(500);\n\twhoami = t4_read_reg(adapter, A_PL_WHOAMI);\n\treturn (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS\n\t\t\t? 0 : -EIO);\n}\n\nstruct flash_desc {\n\tu32 vendor_and_model_id;\n\tu32 size_mb;\n};\n\nint t4_get_flash_params(struct adapter *adapter)\n{\n\t/*\n\t * Table for non-Numonix supported flash parts. Numonix parts are left\n\t * to the preexisting well-tested code. All flash parts have 64KB\n\t * sectors.\n\t */\n\tstatic struct flash_desc supported_flash[] = {\n\t\t{ 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */\n\t};\n\n\tint ret;\n\tunsigned int i;\n\tu32 info = 0;\n\n\tret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);\n\tif (!ret)\n\t\tret = sf1_read(adapter, 3, 0, 1, &info);\n\tt4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */\n\tif (ret < 0)\n\t\treturn ret;\n\n\tfor (i = 0; i < ARRAY_SIZE(supported_flash); ++i)\n\t\tif (supported_flash[i].vendor_and_model_id == info) {\n\t\t\tadapter->params.sf_size = supported_flash[i].size_mb;\n\t\t\tadapter->params.sf_nsec =\n\t\t\t\tadapter->params.sf_size / SF_SEC_SIZE;\n\t\t\treturn 0;\n\t\t}\n\n\tif ((info & 0xff) != 0x20) /* not a Numonix flash */\n\t\treturn -EINVAL;\n\tinfo >>= 16; /* log2 of size */\n\tif (info >= 0x14 && info < 0x18)\n\t\tadapter->params.sf_nsec = 1 << (info - 16);\n\telse if (info == 0x18)\n\t\tadapter->params.sf_nsec = 64;\n\telse\n\t\treturn -EINVAL;\n\tadapter->params.sf_size = 1 << info;\n\n\t/*\n\t * We should reject adapters with FLASHes which are too small. So, emit\n\t * a warning.\n\t */\n\tif (adapter->params.sf_size < FLASH_MIN_SIZE) {\n\t\tdev_warn(adapter, \"WARNING!!! FLASH size %#x < %#x!!!\\n\",\n\t\t\t adapter->params.sf_size, FLASH_MIN_SIZE);\n\t}\n\n\treturn 0;\n}\n\n/**\n * t4_prep_adapter - prepare SW and HW for operation\n * @adapter: the adapter\n *\n * Initialize adapter SW state for the various HW modules, set initial\n * values for some adapter tunables, take PHYs out of reset, and\n * initialize the MDIO interface.\n */\nint t4_prep_adapter(struct adapter *adapter)\n{\n\tint ret, ver;\n\tu32 pl_rev;\n\n\tret = t4_wait_dev_ready(adapter);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tpl_rev = G_REV(t4_read_reg(adapter, A_PL_REV));\n\tadapter->params.pci.device_id = adapter->pdev->id.device_id;\n\tadapter->params.pci.vendor_id = adapter->pdev->id.vendor_id;\n\n\t/*\n\t * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS\n\t * ADAPTER (VERSION << 4 | REVISION)\n\t */\n\tver = CHELSIO_PCI_ID_VER(adapter->params.pci.device_id);\n\tadapter->params.chip = 0;\n\tswitch (ver) {\n\tcase CHELSIO_T5:\n\t\tadapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);\n\t\tadapter->params.arch.sge_fl_db = F_DBPRIO | F_DBTYPE;\n\t\tadapter->params.arch.mps_tcam_size =\n\t\t\t\t\t\tNUM_MPS_T5_CLS_SRAM_L_INSTANCES;\n\t\tadapter->params.arch.mps_rplc_size = 128;\n\t\tadapter->params.arch.nchan = NCHAN;\n\t\tadapter->params.arch.vfcount = 128;\n\t\tbreak;\n\tdefault:\n\t\tdev_err(adapter, \"%s: Device %d is not supported\\n\",\n\t\t\t__func__, adapter->params.pci.device_id);\n\t\treturn -EINVAL;\n\t}\n\n\tret = t4_get_flash_params(adapter);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tadapter->params.cim_la_size = CIMLA_SIZE;\n\n\tinit_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);\n\n\t/*\n\t * Default port and clock for debugging in case we can't reach FW.\n\t */\n\tadapter->params.nports = 1;\n\tadapter->params.portvec = 1;\n\tadapter->params.vpd.cclk = 50000;\n\n\treturn 0;\n}\n\n/**\n * t4_bar2_sge_qregs - return BAR2 SGE Queue register information\n * @adapter: the adapter\n * @qid: the Queue ID\n * @qtype: the Ingress or Egress type for @qid\n * @pbar2_qoffset: BAR2 Queue Offset\n * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues\n *\n * Returns the BAR2 SGE Queue Registers information associated with the\n * indicated Absolute Queue ID. These are passed back in return value\n * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue\n * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.\n *\n * This may return an error which indicates that BAR2 SGE Queue\n * registers aren't available. If an error is not returned, then the\n * following values are returned:\n *\n * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers\n * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid\n *\n * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which\n * require the \"Inferred Queue ID\" ability may be used. E.g. the\n * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,\n * then these \"Inferred Queue ID\" register may not be used.\n */\nint t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,\n\t\t enum t4_bar2_qtype qtype, u64 *pbar2_qoffset,\n\t\t unsigned int *pbar2_qid)\n{\n\tunsigned int page_shift, page_size, qpp_shift, qpp_mask;\n\tu64 bar2_page_offset, bar2_qoffset;\n\tunsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;\n\n\t/*\n\t * T4 doesn't support BAR2 SGE Queue registers.\n\t */\n\tif (is_t4(adapter->params.chip))\n\t\treturn -EINVAL;\n\n\t/*\n\t * Get our SGE Page Size parameters.\n\t */\n\tpage_shift = adapter->params.sge.hps + 10;\n\tpage_size = 1 << page_shift;\n\n\t/*\n\t * Get the right Queues per Page parameters for our Queue.\n\t */\n\tqpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS ?\n\t\t\t adapter->params.sge.eq_qpp :\n\t\t\t adapter->params.sge.iq_qpp);\n\tqpp_mask = (1 << qpp_shift) - 1;\n\n\t/*\n\t * Calculate the basics of the BAR2 SGE Queue register area:\n\t * o The BAR2 page the Queue registers will be in.\n\t * o The BAR2 Queue ID.\n\t * o The BAR2 Queue ID Offset into the BAR2 page.\n\t */\n\tbar2_page_offset = ((qid >> qpp_shift) << page_shift);\n\tbar2_qid = qid & qpp_mask;\n\tbar2_qid_offset = bar2_qid * SGE_UDB_SIZE;\n\n\t/*\n\t * If the BAR2 Queue ID Offset is less than the Page Size, then the\n\t * hardware will infer the Absolute Queue ID simply from the writes to\n\t * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a\n\t * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply\n\t * write to the first BAR2 SGE Queue Area within the BAR2 Page with\n\t * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID\n\t * from the BAR2 Page and BAR2 Queue ID.\n\t *\n\t * One important censequence of this is that some BAR2 SGE registers\n\t * have a \"Queue ID\" field and we can write the BAR2 SGE Queue ID\n\t * there. But other registers synthesize the SGE Queue ID purely\n\t * from the writes to the registers -- the Write Combined Doorbell\n\t * Buffer is a good example. These BAR2 SGE Registers are only\n\t * available for those BAR2 SGE Register areas where the SGE Absolute\n\t * Queue ID can be inferred from simple writes.\n\t */\n\tbar2_qoffset = bar2_page_offset;\n\tbar2_qinferred = (bar2_qid_offset < page_size);\n\tif (bar2_qinferred) {\n\t\tbar2_qoffset += bar2_qid_offset;\n\t\tbar2_qid = 0;\n\t}\n\n\t*pbar2_qoffset = bar2_qoffset;\n\t*pbar2_qid = bar2_qid;\n\treturn 0;\n}\n\n/**\n * t4_init_sge_params - initialize adap->params.sge\n * @adapter: the adapter\n *\n * Initialize various fields of the adapter's SGE Parameters structure.\n */\nint t4_init_sge_params(struct adapter *adapter)\n{\n\tstruct sge_params *sge_params = &adapter->params.sge;\n\tu32 hps, qpp;\n\tunsigned int s_hps, s_qpp;\n\n\t/*\n\t * Extract the SGE Page Size for our PF.\n\t */\n\thps = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);\n\ts_hps = (S_HOSTPAGESIZEPF0 + (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) *\n\t\t adapter->pf);\n\tsge_params->hps = ((hps >> s_hps) & M_HOSTPAGESIZEPF0);\n\n\t/*\n\t * Extract the SGE Egress and Ingess Queues Per Page for our PF.\n\t */\n\ts_qpp = (S_QUEUESPERPAGEPF0 +\n\t\t (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf);\n\tqpp = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);\n\tsge_params->eq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);\n\tqpp = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);\n\tsge_params->iq_qpp = ((qpp >> s_qpp) & M_QUEUESPERPAGEPF0);\n\n\treturn 0;\n}\n\n/**\n * t4_init_tp_params - initialize adap->params.tp\n * @adap: the adapter\n *\n * Initialize various fields of the adapter's TP Parameters structure.\n */\nint t4_init_tp_params(struct adapter *adap)\n{\n\tint chan;\n\tu32 v;\n\n\tv = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);\n\tadap->params.tp.tre = G_TIMERRESOLUTION(v);\n\tadap->params.tp.dack_re = G_DELAYEDACKRESOLUTION(v);\n\n\t/* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */\n\tfor (chan = 0; chan < NCHAN; chan++)\n\t\tadap->params.tp.tx_modq[chan] = chan;\n\n\t/*\n\t * Cache the adapter's Compressed Filter Mode and global Incress\n\t * Configuration.\n\t */\n\tt4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,\n\t\t\t &adap->params.tp.vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);\n\tt4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,\n\t\t\t &adap->params.tp.ingress_config, 1,\n\t\t\t A_TP_INGRESS_CONFIG);\n\n\t/*\n\t * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field\n\t * shift positions of several elements of the Compressed Filter Tuple\n\t * for this adapter which we need frequently ...\n\t */\n\tadap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN);\n\tadap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);\n\tadap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT);\n\tadap->params.tp.protocol_shift = t4_filter_field_shift(adap,\n\t\t\t\t\t\t\t F_PROTOCOL);\n\n\t/*\n\t * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID\n\t * represents the presense of an Outer VLAN instead of a VNIC ID.\n\t */\n\tif ((adap->params.tp.ingress_config & F_VNIC) == 0)\n\t\tadap->params.tp.vnic_shift = -1;\n\n\treturn 0;\n}\n\n/**\n * t4_filter_field_shift - calculate filter field shift\n * @adap: the adapter\n * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)\n *\n * Return the shift position of a filter field within the Compressed\n * Filter Tuple. The filter field is specified via its selection bit\n * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.\n */\nint t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel)\n{\n\tunsigned int filter_mode = adap->params.tp.vlan_pri_map;\n\tunsigned int sel;\n\tint field_shift;\n\n\tif ((filter_mode & filter_sel) == 0)\n\t\treturn -1;\n\n\tfor (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {\n\t\tswitch (filter_mode & sel) {\n\t\tcase F_FCOE:\n\t\t\tfield_shift += W_FT_FCOE;\n\t\t\tbreak;\n\t\tcase F_PORT:\n\t\t\tfield_shift += W_FT_PORT;\n\t\t\tbreak;\n\t\tcase F_VNIC_ID:\n\t\t\tfield_shift += W_FT_VNIC_ID;\n\t\t\tbreak;\n\t\tcase F_VLAN:\n\t\t\tfield_shift += W_FT_VLAN;\n\t\t\tbreak;\n\t\tcase F_TOS:\n\t\t\tfield_shift += W_FT_TOS;\n\t\t\tbreak;\n\t\tcase F_PROTOCOL:\n\t\t\tfield_shift += W_FT_PROTOCOL;\n\t\t\tbreak;\n\t\tcase F_ETHERTYPE:\n\t\t\tfield_shift += W_FT_ETHERTYPE;\n\t\t\tbreak;\n\t\tcase F_MACMATCH:\n\t\t\tfield_shift += W_FT_MACMATCH;\n\t\t\tbreak;\n\t\tcase F_MPSHITTYPE:\n\t\t\tfield_shift += W_FT_MPSHITTYPE;\n\t\t\tbreak;\n\t\tcase F_FRAGMENTATION:\n\t\t\tfield_shift += W_FT_FRAGMENTATION;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn field_shift;\n}\n\nint t4_init_rss_mode(struct adapter *adap, int mbox)\n{\n\tint i, ret;\n\tstruct fw_rss_vi_config_cmd rvc;\n\n\tmemset(&rvc, 0, sizeof(rvc));\n\n\tfor_each_port(adap, i) {\n\t\tstruct port_info *p = adap2pinfo(adap, i);\n\n\t\trvc.op_to_viid = htonl(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |\n\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_READ |\n\t\t\t\t V_FW_RSS_VI_CONFIG_CMD_VIID(p->viid));\n\t\trvc.retval_len16 = htonl(FW_LEN16(rvc));\n\t\tret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);\n\t\tif (ret)\n\t\t\treturn ret;\n\t\tp->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);\n\t}\n\treturn 0;\n}\n\nint t4_port_init(struct adapter *adap, int mbox, int pf, int vf)\n{\n\tu8 addr[6];\n\tint ret, i, j = 0;\n\tstruct fw_port_cmd c;\n\n\tmemset(&c, 0, sizeof(c));\n\n\tfor_each_port(adap, i) {\n\t\tunsigned int rss_size = 0;\n\t\tstruct port_info *p = adap2pinfo(adap, i);\n\n\t\twhile ((adap->params.portvec & (1 << j)) == 0)\n\t\t\tj++;\n\n\t\tc.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |\n\t\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_READ |\n\t\t\t\t\t V_FW_PORT_CMD_PORTID(j));\n\t\tc.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(\n\t\t\t\t\t\tFW_PORT_ACTION_GET_PORT_INFO) |\n\t\t\t\t\t\tFW_LEN16(c));\n\t\tret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\tp->viid = ret;\n\t\tp->tx_chan = j;\n\t\tp->rss_size = rss_size;\n\t\tt4_os_set_hw_addr(adap, i, addr);\n\n\t\tret = be32_to_cpu(c.u.info.lstatus_to_modtype);\n\t\tp->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?\n\t\t\t\tG_FW_PORT_CMD_MDIOADDR(ret) : -1;\n\t\tp->port_type = G_FW_PORT_CMD_PTYPE(ret);\n\t\tp->mod_type = FW_PORT_MOD_TYPE_NA;\n\n\t\tinit_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));\n\t\tj++;\n\t}\n\treturn 0;\n}\n" }, { "path": "drivers/net/cxgbe/base/t4_hw.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __T4_HW_H\n#define __T4_HW_H\n\nenum {\n\tNCHAN = 4, /* # of HW channels */\n\tNMTUS = 16, /* size of MTU table */\n\tNCCTRL_WIN = 32, /* # of congestion control windows */\n\tMBOX_LEN = 64, /* mailbox size in bytes */\n\tUDBS_SEG_SIZE = 128, /* segment size for BAR2 user doorbells */\n};\n\nenum {\n\tCIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */\n};\n\nenum {\n\tSF_SEC_SIZE = 64 * 1024, /* serial flash sector size */\n};\n\nenum {\n\tSGE_NTIMERS = 6, /* # of interrupt holdoff timer values */\n\tSGE_NCOUNTERS = 4, /* # of interrupt packet counter values */\n};\n\n/* PCI-e memory window access */\nenum pcie_memwin {\n\tMEMWIN_NIC = 0,\n};\n\nenum {\n\tSGE_MAX_WR_LEN = 512, /* max WR size in bytes */\n\tSGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */\n\t/* max no. of desc allowed in WR */\n\tSGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / SGE_EQ_IDXSIZE,\n};\n\nstruct sge_qstat { /* data written to SGE queue status entries */\n\t__be32 qid;\n\t__be16 cidx;\n\t__be16 pidx;\n};\n\n/*\n * Structure for last 128 bits of response descriptors\n */\nstruct rsp_ctrl {\n\t__be32 hdrbuflen_pidx;\n\t__be32 pldbuflen_qid;\n\tunion {\n\t\tu8 type_gen;\n\t\t__be64 last_flit;\n\t} u;\n};\n\n#define S_RSPD_NEWBUF 31\n#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)\n#define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U)\n\n#define S_RSPD_LEN 0\n#define M_RSPD_LEN 0x7fffffff\n#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)\n#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)\n\n#define S_RSPD_GEN 7\n#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)\n#define F_RSPD_GEN V_RSPD_GEN(1U)\n\n#define S_RSPD_TYPE 4\n#define M_RSPD_TYPE 0x3\n#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)\n#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)\n\n/* Rx queue interrupt deferral field: timer index */\n#define S_QINTR_CNT_EN 0\n#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)\n#define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U)\n\n#define S_QINTR_TIMER_IDX 1\n#define M_QINTR_TIMER_IDX 0x7\n#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)\n#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)\n\n/*\n * Flash layout.\n */\n#define FLASH_START(start) ((start) * SF_SEC_SIZE)\n#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)\n\nenum {\n\t/*\n\t * Location of firmware image in FLASH.\n\t */\n\tFLASH_FW_START_SEC = 8,\n\tFLASH_FW_NSECS = 16,\n\tFLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),\n\tFLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),\n\n\t/*\n\t * Location of Firmware Configuration File in FLASH.\n\t */\n\tFLASH_CFG_START_SEC = 31,\n\tFLASH_CFG_NSECS = 1,\n\tFLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),\n\tFLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),\n\n\t/*\n\t * We don't support FLASH devices which can't support the full\n\t * standard set of sections which we need for normal operations.\n\t */\n\tFLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,\n};\n\n#undef FLASH_START\n#undef FLASH_MAX_SIZE\n\n#endif /* __T4_HW_H */\n" }, { "path": "drivers/net/cxgbe/base/t4_msg.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef T4_MSG_H\n#define T4_MSG_H\n\nenum {\n\tCPL_SGE_EGR_UPDATE = 0xA5,\n\tCPL_FW4_MSG = 0xC0,\n\tCPL_FW6_MSG = 0xE0,\n\tCPL_TX_PKT_LSO = 0xED,\n\tCPL_TX_PKT_XT = 0xEE,\n};\n\nenum { /* TX_PKT_XT checksum types */\n\tTX_CSUM_TCPIP = 8,\n\tTX_CSUM_UDPIP = 9,\n\tTX_CSUM_TCPIP6 = 10,\n};\n\nunion opcode_tid {\n\t__be32 opcode_tid;\n\t__u8 opcode;\n};\n\nstruct rss_header {\n\t__u8 opcode;\n#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n\t__u8 channel:2;\n\t__u8 filter_hit:1;\n\t__u8 filter_tid:1;\n\t__u8 hash_type:2;\n\t__u8 ipv6:1;\n\t__u8 send2fw:1;\n#else\n\t__u8 send2fw:1;\n\t__u8 ipv6:1;\n\t__u8 hash_type:2;\n\t__u8 filter_tid:1;\n\t__u8 filter_hit:1;\n\t__u8 channel:2;\n#endif\n\t__be16 qid;\n\t__be32 hash_val;\n};\n\n#if defined(RSS_HDR_VLD) || defined(CHELSIO_FW)\n#define RSS_HDR struct rss_header rss_hdr\n#else\n#define RSS_HDR\n#endif\n\n#ifndef CHELSIO_FW\nstruct work_request_hdr {\n\t__be32 wr_hi;\n\t__be32 wr_mid;\n\t__be64 wr_lo;\n};\n\n#define WR_HDR struct work_request_hdr wr\n#define WR_HDR_SIZE sizeof(struct work_request_hdr)\n#else\n#define WR_HDR\n#define WR_HDR_SIZE 0\n#endif\n\nstruct cpl_tx_data {\n\tunion opcode_tid ot;\n\t__be32 len;\n\t__be32 rsvd;\n\t__be32 flags;\n};\n\nstruct cpl_tx_pkt_core {\n\t__be32 ctrl0;\n\t__be16 pack;\n\t__be16 len;\n\t__be64 ctrl1;\n};\n\nstruct cpl_tx_pkt {\n\tWR_HDR;\n\tstruct cpl_tx_pkt_core c;\n};\n\n/* cpl_tx_pkt_core.ctrl0 fields */\n#define S_TXPKT_PF 8\n#define M_TXPKT_PF 0x7\n#define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)\n#define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)\n\n#define S_TXPKT_INTF 16\n#define M_TXPKT_INTF 0xF\n#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)\n#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)\n\n#define S_TXPKT_OPCODE 24\n#define M_TXPKT_OPCODE 0xFF\n#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)\n#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)\n\n/* cpl_tx_pkt_core.ctrl1 fields */\n#define S_TXPKT_IPHDR_LEN 20\n#define M_TXPKT_IPHDR_LEN 0x3FFF\n#define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)\n#define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)\n\n#define S_TXPKT_ETHHDR_LEN 34\n#define M_TXPKT_ETHHDR_LEN 0x3F\n#define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)\n#define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)\n\n#define S_T6_TXPKT_ETHHDR_LEN 32\n#define M_T6_TXPKT_ETHHDR_LEN 0xFF\n#define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)\n#define G_T6_TXPKT_ETHHDR_LEN(x) \\\n\t(((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN)\n\n#define S_TXPKT_CSUM_TYPE 40\n#define M_TXPKT_CSUM_TYPE 0xF\n#define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)\n#define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)\n\n#define S_TXPKT_VLAN 44\n#define M_TXPKT_VLAN 0xFFFF\n#define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)\n#define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)\n\n#define S_TXPKT_VLAN_VLD 60\n#define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)\n#define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)\n\n#define S_TXPKT_IPCSUM_DIS 62\n#define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)\n#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)\n\n#define S_TXPKT_L4CSUM_DIS 63\n#define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)\n#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)\n\nstruct cpl_tx_pkt_lso_core {\n\t__be32 lso_ctrl;\n\t__be16 ipid_ofst;\n\t__be16 mss;\n\t__be32 seqno_offset;\n\t__be32 len;\n\t/* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */\n};\n\nstruct cpl_tx_pkt_lso {\n\tWR_HDR;\n\tstruct cpl_tx_pkt_lso_core c;\n\t/* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */\n};\n\n/* cpl_tx_pkt_lso_core.lso_ctrl fields */\n#define S_LSO_TCPHDR_LEN 0\n#define M_LSO_TCPHDR_LEN 0xF\n#define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)\n#define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)\n\n#define S_LSO_IPHDR_LEN 4\n#define M_LSO_IPHDR_LEN 0xFFF\n#define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)\n#define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)\n\n#define S_LSO_ETHHDR_LEN 16\n#define M_LSO_ETHHDR_LEN 0xF\n#define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)\n#define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)\n\n#define S_LSO_IPV6 20\n#define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)\n#define F_LSO_IPV6 V_LSO_IPV6(1U)\n\n#define S_LSO_LAST_SLICE 22\n#define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)\n#define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)\n\n#define S_LSO_FIRST_SLICE 23\n#define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)\n#define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)\n\n#define S_LSO_OPCODE 24\n#define M_LSO_OPCODE 0xFF\n#define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)\n#define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)\n\n#define S_LSO_T5_XFER_SIZE\t 0\n#define M_LSO_T5_XFER_SIZE 0xFFFFFFF\n#define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)\n#define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)\n\nstruct cpl_rx_pkt {\n\tRSS_HDR;\n\t__u8 opcode;\n#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n\t__u8 iff:4;\n\t__u8 csum_calc:1;\n\t__u8 ipmi_pkt:1;\n\t__u8 vlan_ex:1;\n\t__u8 ip_frag:1;\n#else\n\t__u8 ip_frag:1;\n\t__u8 vlan_ex:1;\n\t__u8 ipmi_pkt:1;\n\t__u8 csum_calc:1;\n\t__u8 iff:4;\n#endif\n\t__be16 csum;\n\t__be16 vlan;\n\t__be16 len;\n\t__be32 l2info;\n\t__be16 hdr_len;\n\t__be16 err_vec;\n};\n\n/* rx_pkt.l2info fields */\n#define S_RXF_UDP 22\n#define V_RXF_UDP(x) ((x) << S_RXF_UDP)\n#define F_RXF_UDP V_RXF_UDP(1U)\n\n#define S_RXF_TCP 23\n#define V_RXF_TCP(x) ((x) << S_RXF_TCP)\n#define F_RXF_TCP V_RXF_TCP(1U)\n\n#define S_RXF_IP 24\n#define V_RXF_IP(x) ((x) << S_RXF_IP)\n#define F_RXF_IP V_RXF_IP(1U)\n\n#define S_RXF_IP6 25\n#define V_RXF_IP6(x) ((x) << S_RXF_IP6)\n#define F_RXF_IP6 V_RXF_IP6(1U)\n\n/* cpl_fw*.type values */\nenum {\n\tFW_TYPE_RSSCPL = 4,\n};\n\nstruct cpl_fw4_msg {\n\tRSS_HDR;\n\tu8 opcode;\n\tu8 type;\n\t__be16 rsvd0;\n\t__be32 rsvd1;\n\t__be64 data[2];\n};\n\nstruct cpl_fw6_msg {\n\tRSS_HDR;\n\tu8 opcode;\n\tu8 type;\n\t__be16 rsvd0;\n\t__be32 rsvd1;\n\t__be64 data[4];\n};\n\nenum {\n\tULP_TX_SC_IMM = 0x81,\n\tULP_TX_SC_DSGL = 0x82,\n\tULP_TX_SC_ISGL = 0x83\n};\n\n#define S_ULPTX_CMD 24\n#define M_ULPTX_CMD 0xFF\n#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)\n\n#define S_ULP_TX_SC_MORE 23\n#define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)\n#define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)\n\nstruct ulptx_sge_pair {\n\t__be32 len[2];\n\t__be64 addr[2];\n};\n\nstruct ulptx_sgl {\n\t__be32 cmd_nsge;\n\t__be32 len0;\n\t__be64 addr0;\n\n#if !(defined C99_NOT_SUPPORTED)\n\tstruct ulptx_sge_pair sge[0];\n#endif\n\n};\n\nstruct ulptx_idata {\n\t__be32 cmd_more;\n\t__be32 len;\n};\n\n#define S_ULPTX_NSGE 0\n#define M_ULPTX_NSGE 0xFFFF\n#define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)\n\nstruct ulp_txpkt {\n\t__be32 cmd_dest;\n\t__be32 len;\n};\n\n/* ulp_txpkt.cmd_dest fields */\n#define S_ULP_TXPKT_DEST 16\n#define M_ULP_TXPKT_DEST 0x3\n#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)\n\n#define S_ULP_TXPKT_FID\t 4\n#define M_ULP_TXPKT_FID 0x7ff\n#define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)\n\n#define S_ULP_TXPKT_RO 3\n#define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)\n#define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)\n\n#endif /* T4_MSG_H */\n" }, { "path": "drivers/net/cxgbe/base/t4_pci_id_tbl.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __T4_PCI_ID_TBL_H__\n#define __T4_PCI_ID_TBL_H__\n\n/*\n * The Os-Dependent code can defined cpp macros for creating a PCI Device ID\n * Table. This is useful because it allows the PCI ID Table to be maintained\n * in a single place and all supporting OSes to get new PCI Device IDs\n * automatically.\n *\n * The macros are:\n *\n * CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN\n * -- Used to start the definition of the PCI ID Table.\n *\n * CH_PCI_DEVICE_ID_FUNCTION\n * -- The PCI Function Number to use in the PCI Device ID Table. \"0\"\n * -- for drivers attaching to PF0-3, \"4\" for drivers attaching to PF4,\n * -- \"8\" for drivers attaching to SR-IOV Virtual Functions, etc.\n *\n * CH_PCI_DEVICE_ID_FUNCTION2 [optional]\n * -- If defined, create a PCI Device ID Table with both\n * -- CH_PCI_DEVICE_ID_FUNCTION and CH_PCI_DEVICE_ID_FUNCTION2 populated.\n *\n * CH_PCI_ID_TABLE_ENTRY(DeviceID)\n * -- Used for the individual PCI Device ID entries. Note that we will\n * -- be adding a trailing comma (\",\") after all of the entries (and\n * -- between the pairs of entries if CH_PCI_DEVICE_ID_FUNCTION2 is defined).\n *\n * CH_PCI_DEVICE_ID_TABLE_DEFINE_END\n * -- Used to finish the definition of the PCI ID Table. Note that we\n * -- will be adding a trailing semi-colon (\";\") here.\n *\n * CH_PCI_DEVICE_ID_BYPASS_SUPPORTED [optional]\n * -- If defined, indicates that the OS Driver has support for Bypass\n * -- Adapters.\n */\n#ifdef CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN\n\n/*\n * Some sanity checks ...\n */\n#ifndef CH_PCI_DEVICE_ID_FUNCTION\n#error CH_PCI_DEVICE_ID_FUNCTION not defined!\n#endif\n#ifndef CH_PCI_ID_TABLE_ENTRY\n#error CH_PCI_ID_TABLE_ENTRY not defined!\n#endif\n#ifndef CH_PCI_DEVICE_ID_TABLE_DEFINE_END\n#error CH_PCI_DEVICE_ID_TABLE_DEFINE_END not defined!\n#endif\n\n/*\n * T4 and later ASICs use a PCI Device ID scheme of 0xVFPP where:\n *\n * V = \"4\" for T4; \"5\" for T5, etc.\n * F = \"0\" for PF 0..3; \"4\"..\"7\" for PF4..7; and \"8\" for VFs\n * PP = adapter product designation\n *\n * We use this consistency in order to create the proper PCI Device IDs\n * for the specified CH_PCI_DEVICE_ID_FUNCTION.\n */\n#ifndef CH_PCI_DEVICE_ID_FUNCTION2\n#define CH_PCI_ID_TABLE_FENTRY(devid) \\\n\tCH_PCI_ID_TABLE_ENTRY((devid) | \\\n\t\t\t ((CH_PCI_DEVICE_ID_FUNCTION) << 8))\n#else\n#define CH_PCI_ID_TABLE_FENTRY(devid) \\\n\tCH_PCI_ID_TABLE_ENTRY((devid) | \\\n\t\t\t ((CH_PCI_DEVICE_ID_FUNCTION) << 8)), \\\n\tCH_PCI_ID_TABLE_ENTRY((devid) | \\\n\t\t\t ((CH_PCI_DEVICE_ID_FUNCTION2) << 8))\n#endif\n\nCH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN\n\t/*\n\t * T5 adapters:\n\t */\n\tCH_PCI_ID_TABLE_FENTRY(0x5000),\t/* T580-dbg */\n\tCH_PCI_ID_TABLE_FENTRY(0x5001),\t/* T520-cr */\n\tCH_PCI_ID_TABLE_FENTRY(0x5002),\t/* T522-cr */\n\tCH_PCI_ID_TABLE_FENTRY(0x5003),\t/* T540-cr */\n\tCH_PCI_ID_TABLE_FENTRY(0x5004),\t/* T520-bch */\n\tCH_PCI_ID_TABLE_FENTRY(0x5005),\t/* T540-bch */\n\tCH_PCI_ID_TABLE_FENTRY(0x5006),\t/* T540-ch */\n\tCH_PCI_ID_TABLE_FENTRY(0x5007),\t/* T520-so */\n\tCH_PCI_ID_TABLE_FENTRY(0x5008),\t/* T520-cx */\n\tCH_PCI_ID_TABLE_FENTRY(0x5009),\t/* T520-bt */\n\tCH_PCI_ID_TABLE_FENTRY(0x500a),\t/* T504-bt */\n#ifdef CH_PCI_DEVICE_ID_BYPASS_SUPPORTED\n\tCH_PCI_ID_TABLE_FENTRY(0x500b),\t/* B520-sr */\n\tCH_PCI_ID_TABLE_FENTRY(0x500c),\t/* B504-bt */\n#endif\n\tCH_PCI_ID_TABLE_FENTRY(0x500d),\t/* T580-cr */\n\tCH_PCI_ID_TABLE_FENTRY(0x500e),\t/* T540-LP-cr */\n\tCH_PCI_ID_TABLE_FENTRY(0x5010),\t/* T580-LP-cr */\n\tCH_PCI_ID_TABLE_FENTRY(0x5011),\t/* T520-LL-cr */\n\tCH_PCI_ID_TABLE_FENTRY(0x5012),\t/* T560-cr */\n\tCH_PCI_ID_TABLE_FENTRY(0x5013),\t/* T580-chr */\n\tCH_PCI_ID_TABLE_FENTRY(0x5014),\t/* T580-so */\n\tCH_PCI_ID_TABLE_FENTRY(0x5015),\t/* T502-bt */\n\tCH_PCI_ID_TABLE_FENTRY(0x5080),\t/* Custom T540-cr */\n\tCH_PCI_ID_TABLE_FENTRY(0x5081),\t/* Custom T540-LL-cr */\n\tCH_PCI_ID_TABLE_FENTRY(0x5082),\t/* Custom T504-cr */\n\tCH_PCI_ID_TABLE_FENTRY(0x5083),\t/* Custom T540-LP-CR */\n\tCH_PCI_ID_TABLE_FENTRY(0x5084),\t/* Custom T580-cr */\n\tCH_PCI_ID_TABLE_FENTRY(0x5085),\t/* Custom 3x T580-CR */\n\tCH_PCI_ID_TABLE_FENTRY(0x5086),\t/* Custom 2x T580-CR */\n\tCH_PCI_ID_TABLE_FENTRY(0x5087),\t/* Custom T580-CR */\n\tCH_PCI_ID_TABLE_FENTRY(0x5088),\t/* Custom T570-CR */\n\tCH_PCI_ID_TABLE_FENTRY(0x5089),\t/* Custom T520-CR */\n\tCH_PCI_ID_TABLE_FENTRY(0x5090), /* Custom T540-CR */\n\tCH_PCI_ID_TABLE_FENTRY(0x5091), /* Custom T522-CR */\n\tCH_PCI_ID_TABLE_FENTRY(0x5092), /* Custom T520-CR */\nCH_PCI_DEVICE_ID_TABLE_DEFINE_END;\n\n#endif /* CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN */\n\n#endif /* __T4_PCI_ID_TBL_H__ */\n" }, { "path": "drivers/net/cxgbe/base/t4_regs.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#define MYPF_BASE 0x1b000\n#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))\n\n#define PF0_BASE 0x1e000\n#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))\n\n#define PF_STRIDE 0x400\n#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)\n#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))\n\n#define MYPORT_BASE 0x1c000\n#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))\n\n#define PORT0_BASE 0x20000\n#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))\n\n#define PORT_STRIDE 0x2000\n#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)\n#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))\n\n#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)\n#define NUM_PCIE_MEM_ACCESS_INSTANCES 8\n\n#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)\n#define NUM_PCIE_FW_INSTANCES 8\n\n#define T5_MYPORT_BASE 0x2c000\n#define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))\n\n#define T5_PORT0_BASE 0x30000\n#define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))\n\n#define T5_PORT_STRIDE 0x4000\n#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)\n#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))\n\n#define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)\n#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512\n\n#define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)\n#define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512\n\n/* registers for module SGE */\n#define SGE_BASE_ADDR 0x1000\n\n#define A_SGE_PF_KDOORBELL 0x0\n\n#define S_QID 15\n#define M_QID 0x1ffffU\n#define V_QID(x) ((x) << S_QID)\n#define G_QID(x) (((x) >> S_QID) & M_QID)\n\n#define S_DBPRIO 14\n#define V_DBPRIO(x) ((x) << S_DBPRIO)\n#define F_DBPRIO V_DBPRIO(1U)\n\n#define S_PIDX 0\n#define M_PIDX 0x3fffU\n#define V_PIDX(x) ((x) << S_PIDX)\n#define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)\n\n#define S_DBTYPE 13\n#define V_DBTYPE(x) ((x) << S_DBTYPE)\n#define F_DBTYPE V_DBTYPE(1U)\n\n#define S_PIDX_T5 0\n#define M_PIDX_T5 0x1fffU\n#define V_PIDX_T5(x) ((x) << S_PIDX_T5)\n#define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)\n\n#define A_SGE_PF_GTS 0x4\n\n#define S_INGRESSQID 16\n#define M_INGRESSQID 0xffffU\n#define V_INGRESSQID(x) ((x) << S_INGRESSQID)\n#define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)\n\n#define S_SEINTARM 12\n#define V_SEINTARM(x) ((x) << S_SEINTARM)\n#define F_SEINTARM V_SEINTARM(1U)\n\n#define S_CIDXINC 0\n#define M_CIDXINC 0xfffU\n#define V_CIDXINC(x) ((x) << S_CIDXINC)\n#define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)\n\n#define A_SGE_CONTROL 0x1008\n\n#define S_RXPKTCPLMODE 18\n#define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)\n#define F_RXPKTCPLMODE V_RXPKTCPLMODE(1U)\n\n#define S_EGRSTATUSPAGESIZE 17\n#define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)\n#define F_EGRSTATUSPAGESIZE V_EGRSTATUSPAGESIZE(1U)\n\n#define S_PKTSHIFT 10\n#define M_PKTSHIFT 0x7U\n#define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)\n#define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)\n\n#define S_INGPADBOUNDARY 4\n#define M_INGPADBOUNDARY 0x7U\n#define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)\n#define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)\n\n#define A_SGE_HOST_PAGE_SIZE 0x100c\n\n#define S_HOSTPAGESIZEPF7 28\n#define M_HOSTPAGESIZEPF7 0xfU\n#define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)\n#define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)\n\n#define S_HOSTPAGESIZEPF6 24\n#define M_HOSTPAGESIZEPF6 0xfU\n#define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)\n#define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)\n\n#define S_HOSTPAGESIZEPF5 20\n#define M_HOSTPAGESIZEPF5 0xfU\n#define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)\n#define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)\n\n#define S_HOSTPAGESIZEPF4 16\n#define M_HOSTPAGESIZEPF4 0xfU\n#define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)\n#define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)\n\n#define S_HOSTPAGESIZEPF3 12\n#define M_HOSTPAGESIZEPF3 0xfU\n#define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)\n#define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)\n\n#define S_HOSTPAGESIZEPF2 8\n#define M_HOSTPAGESIZEPF2 0xfU\n#define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)\n#define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)\n\n#define S_HOSTPAGESIZEPF1 4\n#define M_HOSTPAGESIZEPF1 0xfU\n#define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)\n#define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)\n\n#define S_HOSTPAGESIZEPF0 0\n#define M_HOSTPAGESIZEPF0 0xfU\n#define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)\n#define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)\n\n#define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010\n\n#define S_QUEUESPERPAGEPF1 4\n#define M_QUEUESPERPAGEPF1 0xfU\n#define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)\n#define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)\n\n#define S_QUEUESPERPAGEPF0 0\n#define M_QUEUESPERPAGEPF0 0xfU\n#define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)\n#define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)\n\n#define S_ERR_CPL_EXCEED_IQE_SIZE 22\n#define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)\n#define F_ERR_CPL_EXCEED_IQE_SIZE V_ERR_CPL_EXCEED_IQE_SIZE(1U)\n\n#define S_ERR_INVALID_CIDX_INC 21\n#define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)\n#define F_ERR_INVALID_CIDX_INC V_ERR_INVALID_CIDX_INC(1U)\n\n#define S_ERR_CPL_OPCODE_0 19\n#define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)\n#define F_ERR_CPL_OPCODE_0 V_ERR_CPL_OPCODE_0(1U)\n\n#define S_ERR_DROPPED_DB 18\n#define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)\n#define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U)\n\n#define S_ERR_DATA_CPL_ON_HIGH_QID1 17\n#define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)\n#define F_ERR_DATA_CPL_ON_HIGH_QID1 V_ERR_DATA_CPL_ON_HIGH_QID1(1U)\n\n#define S_ERR_DATA_CPL_ON_HIGH_QID0 16\n#define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)\n#define F_ERR_DATA_CPL_ON_HIGH_QID0 V_ERR_DATA_CPL_ON_HIGH_QID0(1U)\n\n#define S_ERR_BAD_DB_PIDX3 15\n#define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)\n#define F_ERR_BAD_DB_PIDX3 V_ERR_BAD_DB_PIDX3(1U)\n\n#define S_ERR_BAD_DB_PIDX2 14\n#define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)\n#define F_ERR_BAD_DB_PIDX2 V_ERR_BAD_DB_PIDX2(1U)\n\n#define S_ERR_BAD_DB_PIDX1 13\n#define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)\n#define F_ERR_BAD_DB_PIDX1 V_ERR_BAD_DB_PIDX1(1U)\n\n#define S_ERR_BAD_DB_PIDX0 12\n#define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)\n#define F_ERR_BAD_DB_PIDX0 V_ERR_BAD_DB_PIDX0(1U)\n\n#define S_ERR_ING_PCIE_CHAN 11\n#define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)\n#define F_ERR_ING_PCIE_CHAN V_ERR_ING_PCIE_CHAN(1U)\n\n#define S_ERR_ING_CTXT_PRIO 10\n#define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)\n#define F_ERR_ING_CTXT_PRIO V_ERR_ING_CTXT_PRIO(1U)\n\n#define S_ERR_EGR_CTXT_PRIO 9\n#define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)\n#define F_ERR_EGR_CTXT_PRIO V_ERR_EGR_CTXT_PRIO(1U)\n\n#define S_DBFIFO_HP_INT 8\n#define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)\n#define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U)\n\n#define S_DBFIFO_LP_INT 7\n#define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)\n#define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U)\n\n#define S_INGRESS_SIZE_ERR 5\n#define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)\n#define F_INGRESS_SIZE_ERR V_INGRESS_SIZE_ERR(1U)\n\n#define S_EGRESS_SIZE_ERR 4\n#define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)\n#define F_EGRESS_SIZE_ERR V_EGRESS_SIZE_ERR(1U)\n\n#define A_SGE_INT_ENABLE3 0x1040\n\n#define A_SGE_FL_BUFFER_SIZE0 0x1044\n#define A_SGE_FL_BUFFER_SIZE1 0x1048\n#define A_SGE_FL_BUFFER_SIZE2 0x104c\n#define A_SGE_FL_BUFFER_SIZE3 0x1050\n\n#define A_SGE_CONM_CTRL 0x1094\n\n#define S_EGRTHRESHOLD 8\n#define M_EGRTHRESHOLD 0x3fU\n#define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)\n#define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)\n\n#define S_EGRTHRESHOLDPACKING 14\n#define M_EGRTHRESHOLDPACKING 0x3fU\n#define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)\n#define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & \\\n\t\t\t\t M_EGRTHRESHOLDPACKING)\n\n#define S_INGTHRESHOLD 2\n#define M_INGTHRESHOLD 0x3fU\n#define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)\n#define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)\n\n#define A_SGE_INGRESS_RX_THRESHOLD 0x10a0\n\n#define S_THRESHOLD_0 24\n#define M_THRESHOLD_0 0x3fU\n#define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)\n#define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)\n\n#define S_THRESHOLD_1 16\n#define M_THRESHOLD_1 0x3fU\n#define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)\n#define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)\n\n#define S_THRESHOLD_2 8\n#define M_THRESHOLD_2 0x3fU\n#define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)\n#define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)\n\n#define S_THRESHOLD_3 0\n#define M_THRESHOLD_3 0x3fU\n#define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)\n#define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)\n\n#define A_SGE_TIMER_VALUE_0_AND_1 0x10b8\n\n#define S_TIMERVALUE0 16\n#define M_TIMERVALUE0 0xffffU\n#define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)\n#define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)\n\n#define S_TIMERVALUE1 0\n#define M_TIMERVALUE1 0xffffU\n#define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)\n#define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)\n\n#define A_SGE_TIMER_VALUE_2_AND_3 0x10bc\n\n#define S_TIMERVALUE2 16\n#define M_TIMERVALUE2 0xffffU\n#define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)\n#define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)\n\n#define S_TIMERVALUE3 0\n#define M_TIMERVALUE3 0xffffU\n#define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)\n#define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)\n\n#define A_SGE_TIMER_VALUE_4_AND_5 0x10c0\n\n#define S_TIMERVALUE4 16\n#define M_TIMERVALUE4 0xffffU\n#define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)\n#define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)\n\n#define S_TIMERVALUE5 0\n#define M_TIMERVALUE5 0xffffU\n#define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)\n#define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)\n\n#define A_SGE_DEBUG_INDEX 0x10cc\n#define A_SGE_DEBUG_DATA_HIGH 0x10d0\n#define A_SGE_DEBUG_DATA_LOW 0x10d4\n#define A_SGE_STAT_CFG 0x10ec\n\n#define S_STATMODE 2\n#define M_STATMODE 0x3U\n#define V_STATMODE(x) ((x) << S_STATMODE)\n#define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)\n\n#define S_STATSOURCE_T5 9\n#define M_STATSOURCE_T5 0xfU\n#define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)\n#define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)\n\n#define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4\n\n#define A_SGE_CONTROL2 0x1124\n\n#define S_INGPACKBOUNDARY 16\n#define M_INGPACKBOUNDARY 0x7U\n#define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)\n#define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)\n\n#define S_BUSY 31\n#define V_BUSY(x) ((x) << S_BUSY)\n#define F_BUSY V_BUSY(1U)\n\n#define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8\n#define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8\n#define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc\n\n/* registers for module PCIE */\n#define PCIE_BASE_ADDR 0x3000\n\n#define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068\n\n#define S_PCIEOFST 10\n#define M_PCIEOFST 0x3fffffU\n#define V_PCIEOFST(x) ((x) << S_PCIEOFST)\n#define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)\n\n#define S_BIR 8\n#define M_BIR 0x3U\n#define V_BIR(x) ((x) << S_BIR)\n#define G_BIR(x) (((x) >> S_BIR) & M_BIR)\n\n#define S_WINDOW 0\n#define M_WINDOW 0xffU\n#define V_WINDOW(x) ((x) << S_WINDOW)\n#define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)\n\n#define A_PCIE_MEM_ACCESS_OFFSET 0x306c\n\n#define S_PFNUM 0\n#define M_PFNUM 0x7U\n#define V_PFNUM(x) ((x) << S_PFNUM)\n#define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)\n\n#define A_PCIE_FW 0x30b8\n#define A_PCIE_FW_PF 0x30bc\n\n/* registers for module CIM */\n#define CIM_BASE_ADDR 0x7b00\n\n#define A_CIM_PF_MAILBOX_DATA 0x240\n#define A_CIM_PF_MAILBOX_CTRL 0x280\n\n#define S_MBMSGVALID 3\n#define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)\n#define F_MBMSGVALID V_MBMSGVALID(1U)\n\n#define S_MBOWNER 0\n#define M_MBOWNER 0x3U\n#define V_MBOWNER(x) ((x) << S_MBOWNER)\n#define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)\n\n#define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290\n#define A_CIM_BOOT_CFG 0x7b00\n\n#define S_UPCRST 0\n#define V_UPCRST(x) ((x) << S_UPCRST)\n#define F_UPCRST V_UPCRST(1U)\n\n/* registers for module TP */\n#define TP_BASE_ADDR 0x7d00\n\n#define A_TP_TIMER_RESOLUTION 0x7d90\n\n#define S_TIMERRESOLUTION 16\n#define M_TIMERRESOLUTION 0xffU\n#define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)\n#define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)\n\n#define S_DELAYEDACKRESOLUTION 0\n#define M_DELAYEDACKRESOLUTION 0xffU\n#define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)\n#define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & \\\n\t\t\t\t M_DELAYEDACKRESOLUTION)\n\n#define A_TP_CCTRL_TABLE 0x7ddc\n\n#define A_TP_MTU_TABLE 0x7de4\n\n#define S_MTUINDEX 24\n#define M_MTUINDEX 0xffU\n#define V_MTUINDEX(x) ((x) << S_MTUINDEX)\n#define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)\n\n#define S_MTUWIDTH 16\n#define M_MTUWIDTH 0xfU\n#define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)\n#define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)\n\n#define S_MTUVALUE 0\n#define M_MTUVALUE 0x3fffU\n#define V_MTUVALUE(x) ((x) << S_MTUVALUE)\n#define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)\n\n#define A_TP_PIO_ADDR 0x7e40\n#define A_TP_PIO_DATA 0x7e44\n\n#define A_TP_VLAN_PRI_MAP 0x140\n\n#define S_FRAGMENTATION 9\n#define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)\n#define F_FRAGMENTATION V_FRAGMENTATION(1U)\n\n#define S_MPSHITTYPE 8\n#define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)\n#define F_MPSHITTYPE V_MPSHITTYPE(1U)\n\n#define S_MACMATCH 7\n#define V_MACMATCH(x) ((x) << S_MACMATCH)\n#define F_MACMATCH V_MACMATCH(1U)\n\n#define S_ETHERTYPE 6\n#define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)\n#define F_ETHERTYPE V_ETHERTYPE(1U)\n\n#define S_PROTOCOL 5\n#define V_PROTOCOL(x) ((x) << S_PROTOCOL)\n#define F_PROTOCOL V_PROTOCOL(1U)\n\n#define S_TOS 4\n#define V_TOS(x) ((x) << S_TOS)\n#define F_TOS V_TOS(1U)\n\n#define S_VLAN 3\n#define V_VLAN(x) ((x) << S_VLAN)\n#define F_VLAN V_VLAN(1U)\n\n#define S_VNIC_ID 2\n#define V_VNIC_ID(x) ((x) << S_VNIC_ID)\n#define F_VNIC_ID V_VNIC_ID(1U)\n\n#define S_PORT 1\n#define V_PORT(x) ((x) << S_PORT)\n#define F_PORT V_PORT(1U)\n\n#define S_FCOE 0\n#define V_FCOE(x) ((x) << S_FCOE)\n#define F_FCOE V_FCOE(1U)\n\n#define A_TP_INGRESS_CONFIG 0x141\n\n#define S_VNIC 11\n#define V_VNIC(x) ((x) << S_VNIC)\n#define F_VNIC V_VNIC(1U)\n\n#define S_CSUM_HAS_PSEUDO_HDR 10\n#define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)\n#define F_CSUM_HAS_PSEUDO_HDR V_CSUM_HAS_PSEUDO_HDR(1U)\n\n/* registers for module MPS */\n#define MPS_BASE_ADDR 0x9000\n\n#define S_REPLICATE 11\n#define V_REPLICATE(x) ((x) << S_REPLICATE)\n#define F_REPLICATE V_REPLICATE(1U)\n\n#define S_PF 8\n#define M_PF 0x7U\n#define V_PF(x) ((x) << S_PF)\n#define G_PF(x) (((x) >> S_PF) & M_PF)\n\n#define S_VF_VALID 7\n#define V_VF_VALID(x) ((x) << S_VF_VALID)\n#define F_VF_VALID V_VF_VALID(1U)\n\n#define S_VF 0\n#define M_VF 0x7fU\n#define V_VF(x) ((x) << S_VF)\n#define G_VF(x) (((x) >> S_VF) & M_VF)\n\n#define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400\n#define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404\n#define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408\n#define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c\n#define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410\n#define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414\n#define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418\n#define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c\n#define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420\n#define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424\n#define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428\n#define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c\n#define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430\n#define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434\n#define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438\n#define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c\n#define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440\n#define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444\n#define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448\n#define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c\n#define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450\n#define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454\n#define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458\n#define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c\n#define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460\n#define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464\n#define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468\n#define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c\n#define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470\n#define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474\n#define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478\n#define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c\n#define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480\n#define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484\n#define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488\n#define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c\n#define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490\n#define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494\n#define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498\n#define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c\n#define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0\n#define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4\n#define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8\n#define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac\n#define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0\n#define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4\n#define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0\n#define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4\n#define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8\n#define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc\n#define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0\n#define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4\n#define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8\n#define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc\n#define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0\n#define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4\n#define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8\n#define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec\n#define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0\n#define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4\n#define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8\n#define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc\n#define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500\n#define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504\n#define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508\n#define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c\n#define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510\n#define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514\n#define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518\n#define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c\n#define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520\n#define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524\n#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528\n#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528\n#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c\n#define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540\n#define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544\n#define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548\n#define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c\n#define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550\n#define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554\n#define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558\n#define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c\n#define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560\n#define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564\n#define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568\n#define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c\n#define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570\n#define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574\n#define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578\n#define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c\n#define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580\n#define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584\n#define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588\n#define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c\n#define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590\n#define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594\n#define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598\n#define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c\n#define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0\n#define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4\n#define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8\n#define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac\n#define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0\n#define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4\n#define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8\n#define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc\n#define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0\n#define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4\n#define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8\n#define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc\n#define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0\n#define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4\n#define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8\n#define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc\n#define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0\n#define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4\n#define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8\n#define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec\n#define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0\n#define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4\n#define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8\n#define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc\n#define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600\n#define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604\n#define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608\n#define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c\n#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610\n#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614\n#define A_MPS_CMN_CTL 0x9000\n\n#define S_NUMPORTS 0\n#define M_NUMPORTS 0x3U\n#define V_NUMPORTS(x) ((x) << S_NUMPORTS)\n#define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)\n\n#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640\n#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644\n#define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648\n#define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c\n#define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650\n#define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654\n#define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658\n#define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c\n#define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660\n#define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664\n#define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668\n#define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c\n#define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670\n#define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674\n#define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678\n#define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c\n#define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680\n#define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684\n#define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688\n#define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c\n#define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690\n#define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694\n#define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698\n#define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c\n#define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0\n#define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4\n#define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8\n#define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac\n#define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0\n#define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4\n#define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8\n#define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc\n\n/* registers for module ULP_RX */\n#define ULP_RX_BASE_ADDR 0x19150\n\n#define S_HPZ0 0\n#define M_HPZ0 0xfU\n#define V_HPZ0(x) ((x) << S_HPZ0)\n#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)\n\n#define A_ULP_RX_TDDP_PSZ 0x19178\n\n/* registers for module SF */\n#define SF_BASE_ADDR 0x193f8\n\n#define A_SF_DATA 0x193f8\n#define A_SF_OP 0x193fc\n\n#define S_SF_LOCK 4\n#define V_SF_LOCK(x) ((x) << S_SF_LOCK)\n#define F_SF_LOCK V_SF_LOCK(1U)\n\n#define S_CONT 3\n#define V_CONT(x) ((x) << S_CONT)\n#define F_CONT V_CONT(1U)\n\n#define S_BYTECNT 1\n#define M_BYTECNT 0x3U\n#define V_BYTECNT(x) ((x) << S_BYTECNT)\n#define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)\n\n#define S_OP 0\n#define V_OP(x) ((x) << S_OP)\n#define F_OP V_OP(1U)\n\n/* registers for module PL */\n#define PL_BASE_ADDR 0x19400\n\n#define S_SOURCEPF 8\n#define M_SOURCEPF 0x7U\n#define V_SOURCEPF(x) ((x) << S_SOURCEPF)\n#define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)\n\n#define A_PL_PF_INT_ENABLE 0x3c4\n\n#define S_PFSW 3\n#define V_PFSW(x) ((x) << S_PFSW)\n#define F_PFSW V_PFSW(1U)\n\n#define S_PFCIM 1\n#define V_PFCIM(x) ((x) << S_PFCIM)\n#define F_PFCIM V_PFCIM(1U)\n\n#define A_PL_WHOAMI 0x19400\n\n#define A_PL_RST 0x19428\n\n#define A_PL_INT_MAP0 0x19414\n\n#define S_PIORST 1\n#define V_PIORST(x) ((x) << S_PIORST)\n#define F_PIORST V_PIORST(1U)\n\n#define S_PIORSTMODE 0\n#define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)\n#define F_PIORSTMODE V_PIORSTMODE(1U)\n\n#define A_PL_REV 0x1943c\n\n#define S_REV 0\n#define M_REV 0xfU\n#define V_REV(x) ((x) << S_REV)\n#define G_REV(x) (((x) >> S_REV) & M_REV)\n" }, { "path": "drivers/net/cxgbe/base/t4_regs_values.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __T4_REGS_VALUES_H__\n#define __T4_REGS_VALUES_H__\n\n/*\n * This file contains definitions for various T4 register value hardware\n * constants. The types of values encoded here are predominantly those for\n * register fields which control \"modal\" behavior. For the most part, we do\n * not include definitions for register fields which are simple numeric\n * metrics, etc.\n */\n\n/*\n * SGE definitions.\n * ================\n */\n\n/*\n * SGE register field values.\n */\n\n/* CONTROL register */\n#define X_RXPKTCPLMODE_SPLIT\t\t1\n#define X_INGPCIEBOUNDARY_32B\t\t0\n#define X_INGPADBOUNDARY_SHIFT\t\t5\n\n/* CONTROL2 register */\n#define X_INGPACKBOUNDARY_SHIFT\t\t5\n#define X_INGPACKBOUNDARY_16B\t\t0\n\n/* GTS register */\n#define X_TIMERREG_RESTART_COUNTER\t6\n#define X_TIMERREG_UPDATE_CIDX\t\t7\n\n/*\n * Egress Context field values\n */\n#define X_FETCHBURSTMIN_64B\t\t2\n#define X_FETCHBURSTMIN_128B\t\t3\n#define X_FETCHBURSTMAX_256B\t\t2\n#define X_FETCHBURSTMAX_512B\t\t3\n\n#define X_HOSTFCMODE_NONE\t\t0\n\n/*\n * Ingress Context field values\n */\n#define X_UPDATEDELIVERY_INTERRUPT\t1\n\n#define X_RSPD_TYPE_FLBUF\t\t0\n#define X_RSPD_TYPE_CPL\t\t\t1\n\n/*\n * Context field definitions. This is by no means a complete list of SGE\n * Context fields. In the vast majority of cases the firmware initializes\n * things the way they need to be set up. But in a few small cases, we need\n * to compute new values and ship them off to the firmware to be applied to\n * the SGE Conexts ...\n */\n\n/*\n * Congestion Manager Definitions.\n */\n#define S_CONMCTXT_CNGTPMODE\t\t19\n#define M_CONMCTXT_CNGTPMODE\t\t0x3\n#define V_CONMCTXT_CNGTPMODE(x)\t\t((x) << S_CONMCTXT_CNGTPMODE)\n#define G_CONMCTXT_CNGTPMODE(x) \\\n\t(((x) >> S_CONMCTXT_CNGTPMODE) & M_CONMCTXT_CNGTPMODE)\n#define S_CONMCTXT_CNGCHMAP\t\t0\n#define M_CONMCTXT_CNGCHMAP\t\t0xffff\n#define V_CONMCTXT_CNGCHMAP(x)\t\t((x) << S_CONMCTXT_CNGCHMAP)\n#define G_CONMCTXT_CNGCHMAP(x) \\\n\t(((x) >> S_CONMCTXT_CNGCHMAP) & M_CONMCTXT_CNGCHMAP)\n\n#define X_CONMCTXT_CNGTPMODE_QUEUE\t1\n#define X_CONMCTXT_CNGTPMODE_CHANNEL\t2\n\n/*\n * T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.\n * The User Doorbells are each 128 bytes in length with a Simple Doorbell at\n * offsets 8x and a Write Combining single 64-byte Egress Queue Unit\n * (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64. For Ingress Queues,\n * we have a Going To Sleep register at offsets 8x+4.\n *\n * As noted above, we have many instances of the Simple Doorbell and Going To\n * Sleep registers at offsets 8x and 8x+4, respectively. We want to use a\n * non-64-byte aligned offset for the Simple Doorbell in order to attempt to\n * avoid buffering of the writes to the Simple Doorbell and we want to use a\n * non-contiguous offset for the Going To Sleep writes in order to avoid\n * possible combining between them.\n */\n#define SGE_UDB_SIZE\t\t128\n#define SGE_UDB_KDOORBELL\t8\n#define SGE_UDB_GTS\t\t20\n\n/*\n * CIM definitions.\n * ================\n */\n\n/*\n * CIM register field values.\n */\n#define X_MBOWNER_NONE\t\t\t0\n#define X_MBOWNER_FW\t\t\t1\n#define X_MBOWNER_PL\t\t\t2\n\n/*\n * PCI-E definitions.\n * ==================\n */\n#define X_WINDOW_SHIFT\t\t\t10\n#define X_PCIEOFST_SHIFT\t\t10\n\n/*\n * TP definitions.\n * ===============\n */\n\n/*\n * TP_VLAN_PRI_MAP controls which subset of fields will be present in the\n * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP\n * selects for a particular field being present. These fields, when present\n * in the Compressed Filter Tuple, have the following widths in bits.\n */\n#define W_FT_FCOE\t\t\t1\n#define W_FT_PORT\t\t\t3\n#define W_FT_VNIC_ID\t\t\t17\n#define W_FT_VLAN\t\t\t17\n#define W_FT_TOS\t\t\t8\n#define W_FT_PROTOCOL\t\t\t8\n#define W_FT_ETHERTYPE\t\t\t16\n#define W_FT_MACMATCH\t\t\t9\n#define W_FT_MPSHITTYPE\t\t\t3\n#define W_FT_FRAGMENTATION\t\t1\n\n#endif /* __T4_REGS_VALUES_H__ */\n" }, { "path": "drivers/net/cxgbe/base/t4fw_interface.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _T4FW_INTERFACE_H_\n#define _T4FW_INTERFACE_H_\n\n/******************************************************************************\n * R E T U R N V A L U E S\n ********************************/\n\nenum fw_retval {\n\tFW_SUCCESS\t\t= 0,\t/* completed successfully */\n\tFW_EPERM\t\t= 1,\t/* operation not permitted */\n\tFW_ENOENT\t\t= 2,\t/* no such file or directory */\n\tFW_EIO\t\t\t= 5,\t/* input/output error; hw bad */\n\tFW_ENOEXEC\t\t= 8,\t/* exec format error; inv microcode */\n\tFW_EAGAIN\t\t= 11,\t/* try again */\n\tFW_ENOMEM\t\t= 12,\t/* out of memory */\n\tFW_EFAULT\t\t= 14,\t/* bad address; fw bad */\n\tFW_EBUSY\t\t= 16,\t/* resource busy */\n\tFW_EEXIST\t\t= 17,\t/* file exists */\n\tFW_ENODEV\t\t= 19,\t/* no such device */\n\tFW_EINVAL\t\t= 22,\t/* invalid argument */\n\tFW_ENOSPC\t\t= 28,\t/* no space left on device */\n\tFW_ENOSYS\t\t= 38,\t/* functionality not implemented */\n\tFW_ENODATA\t\t= 61,\t/* no data available */\n\tFW_EPROTO\t\t= 71,\t/* protocol error */\n\tFW_EADDRINUSE\t\t= 98,\t/* address already in use */\n\tFW_EADDRNOTAVAIL\t= 99,\t/* cannot assigned requested address */\n\tFW_ENETDOWN\t\t= 100,\t/* network is down */\n\tFW_ENETUNREACH\t\t= 101,\t/* network is unreachable */\n\tFW_ENOBUFS\t\t= 105,\t/* no buffer space available */\n\tFW_ETIMEDOUT\t\t= 110,\t/* timeout */\n\tFW_EINPROGRESS\t\t= 115,\t/* fw internal */\n};\n\n/******************************************************************************\n * M E M O R Y T Y P E s\n ******************************/\n\nenum fw_memtype {\n\tFW_MEMTYPE_EDC0\t\t= 0x0,\n\tFW_MEMTYPE_EDC1\t\t= 0x1,\n\tFW_MEMTYPE_EXTMEM\t= 0x2,\n\tFW_MEMTYPE_FLASH\t= 0x4,\n\tFW_MEMTYPE_INTERNAL\t= 0x5,\n\tFW_MEMTYPE_EXTMEM1\t= 0x6,\n};\n\n/******************************************************************************\n * W O R K R E Q U E S T s\n ********************************/\n\nenum fw_wr_opcodes {\n\tFW_ETH_TX_PKT_WR\t= 0x08,\n\tFW_ETH_TX_PKTS_WR\t= 0x09,\n};\n\n/*\n * Generic work request header flit0\n */\nstruct fw_wr_hdr {\n\t__be32 hi;\n\t__be32 lo;\n};\n\n/* work request opcode (hi)\n */\n#define S_FW_WR_OP\t\t24\n#define M_FW_WR_OP\t\t0xff\n#define V_FW_WR_OP(x)\t\t((x) << S_FW_WR_OP)\n#define G_FW_WR_OP(x)\t\t(((x) >> S_FW_WR_OP) & M_FW_WR_OP)\n\n/* work request immediate data length (hi)\n */\n#define S_FW_WR_IMMDLEN\t0\n#define M_FW_WR_IMMDLEN\t0xff\n#define V_FW_WR_IMMDLEN(x)\t((x) << S_FW_WR_IMMDLEN)\n#define G_FW_WR_IMMDLEN(x)\t\\\n\t(((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)\n\n/* egress queue status update to egress queue status entry (lo)\n */\n#define S_FW_WR_EQUEQ\t\t30\n#define M_FW_WR_EQUEQ\t\t0x1\n#define V_FW_WR_EQUEQ(x)\t((x) << S_FW_WR_EQUEQ)\n#define G_FW_WR_EQUEQ(x)\t(((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)\n#define F_FW_WR_EQUEQ\t\tV_FW_WR_EQUEQ(1U)\n\n/* length in units of 16-bytes (lo)\n */\n#define S_FW_WR_LEN16\t\t0\n#define M_FW_WR_LEN16\t\t0xff\n#define V_FW_WR_LEN16(x)\t((x) << S_FW_WR_LEN16)\n#define G_FW_WR_LEN16(x)\t(((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)\n\nstruct fw_eth_tx_pkt_wr {\n\t__be32 op_immdlen;\n\t__be32 equiq_to_len16;\n\t__be64 r3;\n};\n\n#define S_FW_ETH_TX_PKT_WR_IMMDLEN\t0\n#define M_FW_ETH_TX_PKT_WR_IMMDLEN\t0x1ff\n#define V_FW_ETH_TX_PKT_WR_IMMDLEN(x)\t((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)\n#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x)\t\\\n\t(((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)\n\nstruct fw_eth_tx_pkts_wr {\n\t__be32 op_pkd;\n\t__be32 equiq_to_len16;\n\t__be32 r3;\n\t__be16 plen;\n\t__u8 npkt;\n\t__u8 type;\n};\n\n/******************************************************************************\n * C O M M A N D s\n *********************/\n\n/*\n * The maximum length of time, in miliseconds, that we expect any firmware\n * command to take to execute and return a reply to the host. The RESET\n * and INITIALIZE commands can take a fair amount of time to execute but\n * most execute in far less time than this maximum. This constant is used\n * by host software to determine how long to wait for a firmware command\n * reply before declaring the firmware as dead/unreachable ...\n */\n#define FW_CMD_MAX_TIMEOUT\t10000\n\n/*\n * If a host driver does a HELLO and discovers that there's already a MASTER\n * selected, we may have to wait for that MASTER to finish issuing RESET,\n * configuration and INITIALIZE commands. Also, there's a possibility that\n * our own HELLO may get lost if it happens right as the MASTER is issuign a\n * RESET command, so we need to be willing to make a few retries of our HELLO.\n */\n#define FW_CMD_HELLO_TIMEOUT\t(3 * FW_CMD_MAX_TIMEOUT)\n#define FW_CMD_HELLO_RETRIES\t3\n\nenum fw_cmd_opcodes {\n\tFW_RESET_CMD = 0x03,\n\tFW_HELLO_CMD = 0x04,\n\tFW_BYE_CMD = 0x05,\n\tFW_INITIALIZE_CMD = 0x06,\n\tFW_CAPS_CONFIG_CMD = 0x07,\n\tFW_PARAMS_CMD = 0x08,\n\tFW_IQ_CMD = 0x10,\n\tFW_EQ_ETH_CMD = 0x12,\n\tFW_VI_CMD = 0x14,\n\tFW_VI_MAC_CMD = 0x15,\n\tFW_VI_RXMODE_CMD = 0x16,\n\tFW_VI_ENABLE_CMD = 0x17,\n\tFW_PORT_CMD = 0x1b,\n\tFW_RSS_IND_TBL_CMD = 0x20,\n\tFW_RSS_VI_CONFIG_CMD = 0x23,\n\tFW_DEBUG_CMD = 0x81,\n};\n\n/*\n * Generic command header flit0\n */\nstruct fw_cmd_hdr {\n\t__be32 hi;\n\t__be32 lo;\n};\n\n#define S_FW_CMD_OP\t\t24\n#define M_FW_CMD_OP\t\t0xff\n#define V_FW_CMD_OP(x)\t\t((x) << S_FW_CMD_OP)\n#define G_FW_CMD_OP(x)\t\t(((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)\n\n#define S_FW_CMD_REQUEST\t23\n#define M_FW_CMD_REQUEST\t0x1\n#define V_FW_CMD_REQUEST(x)\t((x) << S_FW_CMD_REQUEST)\n#define G_FW_CMD_REQUEST(x)\t(((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)\n#define F_FW_CMD_REQUEST\tV_FW_CMD_REQUEST(1U)\n\n#define S_FW_CMD_READ\t\t22\n#define M_FW_CMD_READ\t\t0x1\n#define V_FW_CMD_READ(x)\t((x) << S_FW_CMD_READ)\n#define G_FW_CMD_READ(x)\t(((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)\n#define F_FW_CMD_READ\t\tV_FW_CMD_READ(1U)\n\n#define S_FW_CMD_WRITE\t\t21\n#define M_FW_CMD_WRITE\t\t0x1\n#define V_FW_CMD_WRITE(x)\t((x) << S_FW_CMD_WRITE)\n#define G_FW_CMD_WRITE(x)\t(((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)\n#define F_FW_CMD_WRITE\t\tV_FW_CMD_WRITE(1U)\n\n#define S_FW_CMD_EXEC\t\t20\n#define M_FW_CMD_EXEC\t\t0x1\n#define V_FW_CMD_EXEC(x)\t((x) << S_FW_CMD_EXEC)\n#define G_FW_CMD_EXEC(x)\t(((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)\n#define F_FW_CMD_EXEC\t\tV_FW_CMD_EXEC(1U)\n\n#define S_FW_CMD_RETVAL\t\t8\n#define M_FW_CMD_RETVAL\t\t0xff\n#define V_FW_CMD_RETVAL(x)\t((x) << S_FW_CMD_RETVAL)\n#define G_FW_CMD_RETVAL(x)\t(((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)\n\n#define S_FW_CMD_LEN16\t\t0\n#define M_FW_CMD_LEN16\t\t0xff\n#define V_FW_CMD_LEN16(x)\t((x) << S_FW_CMD_LEN16)\n#define G_FW_CMD_LEN16(x)\t(((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)\n\n#define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)\n\nstruct fw_reset_cmd {\n\t__be32 op_to_write;\n\t__be32 retval_len16;\n\t__be32 val;\n\t__be32 halt_pkd;\n};\n\n#define S_FW_RESET_CMD_HALT\t31\n#define M_FW_RESET_CMD_HALT\t0x1\n#define V_FW_RESET_CMD_HALT(x)\t((x) << S_FW_RESET_CMD_HALT)\n#define G_FW_RESET_CMD_HALT(x)\t\\\n\t(((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)\n#define F_FW_RESET_CMD_HALT\tV_FW_RESET_CMD_HALT(1U)\n\nenum {\n\tFW_HELLO_CMD_STAGE_OS\t\t= 0,\n};\n\nstruct fw_hello_cmd {\n\t__be32 op_to_write;\n\t__be32 retval_len16;\n\t__be32 err_to_clearinit;\n\t__be32 fwrev;\n};\n\n#define S_FW_HELLO_CMD_ERR\t31\n#define M_FW_HELLO_CMD_ERR\t0x1\n#define V_FW_HELLO_CMD_ERR(x)\t((x) << S_FW_HELLO_CMD_ERR)\n#define G_FW_HELLO_CMD_ERR(x)\t\\\n\t(((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)\n#define F_FW_HELLO_CMD_ERR\tV_FW_HELLO_CMD_ERR(1U)\n\n#define S_FW_HELLO_CMD_INIT\t30\n#define M_FW_HELLO_CMD_INIT\t0x1\n#define V_FW_HELLO_CMD_INIT(x)\t((x) << S_FW_HELLO_CMD_INIT)\n#define G_FW_HELLO_CMD_INIT(x)\t\\\n\t(((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)\n#define F_FW_HELLO_CMD_INIT\tV_FW_HELLO_CMD_INIT(1U)\n\n#define S_FW_HELLO_CMD_MASTERDIS\t29\n#define M_FW_HELLO_CMD_MASTERDIS\t0x1\n#define V_FW_HELLO_CMD_MASTERDIS(x)\t((x) << S_FW_HELLO_CMD_MASTERDIS)\n#define G_FW_HELLO_CMD_MASTERDIS(x)\t\\\n\t(((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)\n#define F_FW_HELLO_CMD_MASTERDIS\tV_FW_HELLO_CMD_MASTERDIS(1U)\n\n#define S_FW_HELLO_CMD_MASTERFORCE\t28\n#define M_FW_HELLO_CMD_MASTERFORCE\t0x1\n#define V_FW_HELLO_CMD_MASTERFORCE(x)\t((x) << S_FW_HELLO_CMD_MASTERFORCE)\n#define G_FW_HELLO_CMD_MASTERFORCE(x)\t\\\n\t(((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)\n#define F_FW_HELLO_CMD_MASTERFORCE\tV_FW_HELLO_CMD_MASTERFORCE(1U)\n\n#define S_FW_HELLO_CMD_MBMASTER\t\t24\n#define M_FW_HELLO_CMD_MBMASTER\t\t0xf\n#define V_FW_HELLO_CMD_MBMASTER(x)\t((x) << S_FW_HELLO_CMD_MBMASTER)\n#define G_FW_HELLO_CMD_MBMASTER(x)\t\\\n\t(((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)\n\n#define S_FW_HELLO_CMD_MBASYNCNOT\t20\n#define M_FW_HELLO_CMD_MBASYNCNOT\t0x7\n#define V_FW_HELLO_CMD_MBASYNCNOT(x)\t((x) << S_FW_HELLO_CMD_MBASYNCNOT)\n#define G_FW_HELLO_CMD_MBASYNCNOT(x)\t\\\n\t(((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)\n\n#define S_FW_HELLO_CMD_STAGE\t17\n#define M_FW_HELLO_CMD_STAGE\t0x7\n#define V_FW_HELLO_CMD_STAGE(x)\t((x) << S_FW_HELLO_CMD_STAGE)\n#define G_FW_HELLO_CMD_STAGE(x)\t\\\n\t(((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)\n\n#define S_FW_HELLO_CMD_CLEARINIT\t16\n#define M_FW_HELLO_CMD_CLEARINIT\t0x1\n#define V_FW_HELLO_CMD_CLEARINIT(x)\t((x) << S_FW_HELLO_CMD_CLEARINIT)\n#define G_FW_HELLO_CMD_CLEARINIT(x)\t\\\n\t(((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)\n#define F_FW_HELLO_CMD_CLEARINIT\tV_FW_HELLO_CMD_CLEARINIT(1U)\n\nstruct fw_bye_cmd {\n\t__be32 op_to_write;\n\t__be32 retval_len16;\n\t__be64 r3;\n};\n\nstruct fw_initialize_cmd {\n\t__be32 op_to_write;\n\t__be32 retval_len16;\n\t__be64 r3;\n};\n\nenum fw_caps_config_nic {\n\tFW_CAPS_CONFIG_NIC_HASHFILTER\t= 0x00000020,\n\tFW_CAPS_CONFIG_NIC_ETHOFLD\t= 0x00000040,\n};\n\nenum fw_memtype_cf {\n\tFW_MEMTYPE_CF_FLASH\t\t= FW_MEMTYPE_FLASH,\n};\n\nstruct fw_caps_config_cmd {\n\t__be32 op_to_write;\n\t__be32 cfvalid_to_len16;\n\t__be32 r2;\n\t__be32 hwmbitmap;\n\t__be16 nbmcaps;\n\t__be16 linkcaps;\n\t__be16 switchcaps;\n\t__be16 r3;\n\t__be16 niccaps;\n\t__be16 toecaps;\n\t__be16 rdmacaps;\n\t__be16 r4;\n\t__be16 iscsicaps;\n\t__be16 fcoecaps;\n\t__be32 cfcsum;\n\t__be32 finiver;\n\t__be32 finicsum;\n};\n\n#define S_FW_CAPS_CONFIG_CMD_CFVALID\t27\n#define M_FW_CAPS_CONFIG_CMD_CFVALID\t0x1\n#define V_FW_CAPS_CONFIG_CMD_CFVALID(x)\t((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)\n#define G_FW_CAPS_CONFIG_CMD_CFVALID(x)\t\\\n\t(((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)\n#define F_FW_CAPS_CONFIG_CMD_CFVALID\tV_FW_CAPS_CONFIG_CMD_CFVALID(1U)\n\n#define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF\t\t24\n#define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF\t\t0x7\n#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x)\t\\\n\t((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)\n#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x)\t\\\n\t(((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \\\n\t M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)\n\n#define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF\t16\n#define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF\t0xff\n#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x)\t\\\n\t((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)\n#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x)\t\\\n\t(((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \\\n\t M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)\n\n/*\n * params command mnemonics\n */\nenum fw_params_mnem {\n\tFW_PARAMS_MNEM_DEV\t\t= 1,\t/* device params */\n\tFW_PARAMS_MNEM_PFVF\t\t= 2,\t/* function params */\n\tFW_PARAMS_MNEM_DMAQ\t\t= 4,\t/* dma queue params */\n};\n\n/*\n * device parameters\n */\nenum fw_params_param_dev {\n\tFW_PARAMS_PARAM_DEV_CCLK\t= 0x00, /* chip core clock in khz */\n\tFW_PARAMS_PARAM_DEV_PORTVEC\t= 0x01, /* the port vector */\n\tFW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,\n};\n\n/*\n * physical and virtual function parameters\n */\nenum fw_params_param_pfvf {\n\tFW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31\n};\n\n/*\n * dma queue parameters\n */\nenum fw_params_param_dmaq {\n\tFW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,\n\tFW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,\n};\n\n#define S_FW_PARAMS_MNEM\t24\n#define M_FW_PARAMS_MNEM\t0xff\n#define V_FW_PARAMS_MNEM(x)\t((x) << S_FW_PARAMS_MNEM)\n#define G_FW_PARAMS_MNEM(x)\t\\\n\t(((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)\n\n#define S_FW_PARAMS_PARAM_X\t16\n#define M_FW_PARAMS_PARAM_X\t0xff\n#define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)\n#define G_FW_PARAMS_PARAM_X(x) \\\n\t(((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)\n\n#define S_FW_PARAMS_PARAM_Y\t8\n#define M_FW_PARAMS_PARAM_Y\t0xff\n#define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)\n#define G_FW_PARAMS_PARAM_Y(x) \\\n\t(((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)\n\n#define S_FW_PARAMS_PARAM_Z\t0\n#define M_FW_PARAMS_PARAM_Z\t0xff\n#define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)\n#define G_FW_PARAMS_PARAM_Z(x) \\\n\t(((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)\n\n#define S_FW_PARAMS_PARAM_YZ\t0\n#define M_FW_PARAMS_PARAM_YZ\t0xffff\n#define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)\n#define G_FW_PARAMS_PARAM_YZ(x) \\\n\t(((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)\n\nstruct fw_params_cmd {\n\t__be32 op_to_vfn;\n\t__be32 retval_len16;\n\tstruct fw_params_param {\n\t\t__be32 mnem;\n\t\t__be32 val;\n\t} param[7];\n};\n\n#define S_FW_PARAMS_CMD_PFN\t8\n#define M_FW_PARAMS_CMD_PFN\t0x7\n#define V_FW_PARAMS_CMD_PFN(x)\t((x) << S_FW_PARAMS_CMD_PFN)\n#define G_FW_PARAMS_CMD_PFN(x)\t\\\n\t(((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)\n\n#define S_FW_PARAMS_CMD_VFN\t0\n#define M_FW_PARAMS_CMD_VFN\t0xff\n#define V_FW_PARAMS_CMD_VFN(x)\t((x) << S_FW_PARAMS_CMD_VFN)\n#define G_FW_PARAMS_CMD_VFN(x)\t\\\n\t(((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)\n\n/*\n * ingress queue type; the first 1K ingress queues can have associated 0,\n * 1 or 2 free lists and an interrupt, all other ingress queues lack these\n * capabilities\n */\nenum fw_iq_type {\n\tFW_IQ_TYPE_FL_INT_CAP,\n};\n\nstruct fw_iq_cmd {\n\t__be32 op_to_vfn;\n\t__be32 alloc_to_len16;\n\t__be16 physiqid;\n\t__be16 iqid;\n\t__be16 fl0id;\n\t__be16 fl1id;\n\t__be32 type_to_iqandstindex;\n\t__be16 iqdroprss_to_iqesize;\n\t__be16 iqsize;\n\t__be64 iqaddr;\n\t__be32 iqns_to_fl0congen;\n\t__be16 fl0dcaen_to_fl0cidxfthresh;\n\t__be16 fl0size;\n\t__be64 fl0addr;\n\t__be32 fl1cngchmap_to_fl1congen;\n\t__be16 fl1dcaen_to_fl1cidxfthresh;\n\t__be16 fl1size;\n\t__be64 fl1addr;\n};\n\n#define S_FW_IQ_CMD_PFN\t\t8\n#define M_FW_IQ_CMD_PFN\t\t0x7\n#define V_FW_IQ_CMD_PFN(x)\t((x) << S_FW_IQ_CMD_PFN)\n#define G_FW_IQ_CMD_PFN(x)\t(((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)\n\n#define S_FW_IQ_CMD_VFN\t\t0\n#define M_FW_IQ_CMD_VFN\t\t0xff\n#define V_FW_IQ_CMD_VFN(x)\t((x) << S_FW_IQ_CMD_VFN)\n#define G_FW_IQ_CMD_VFN(x)\t(((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)\n\n#define S_FW_IQ_CMD_ALLOC\t31\n#define M_FW_IQ_CMD_ALLOC\t0x1\n#define V_FW_IQ_CMD_ALLOC(x)\t((x) << S_FW_IQ_CMD_ALLOC)\n#define G_FW_IQ_CMD_ALLOC(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)\n#define F_FW_IQ_CMD_ALLOC\tV_FW_IQ_CMD_ALLOC(1U)\n\n#define S_FW_IQ_CMD_FREE\t30\n#define M_FW_IQ_CMD_FREE\t0x1\n#define V_FW_IQ_CMD_FREE(x)\t((x) << S_FW_IQ_CMD_FREE)\n#define G_FW_IQ_CMD_FREE(x)\t(((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)\n#define F_FW_IQ_CMD_FREE\tV_FW_IQ_CMD_FREE(1U)\n\n#define S_FW_IQ_CMD_IQSTART\t28\n#define M_FW_IQ_CMD_IQSTART\t0x1\n#define V_FW_IQ_CMD_IQSTART(x)\t((x) << S_FW_IQ_CMD_IQSTART)\n#define G_FW_IQ_CMD_IQSTART(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)\n#define F_FW_IQ_CMD_IQSTART\tV_FW_IQ_CMD_IQSTART(1U)\n\n#define S_FW_IQ_CMD_IQSTOP\t27\n#define M_FW_IQ_CMD_IQSTOP\t0x1\n#define V_FW_IQ_CMD_IQSTOP(x)\t((x) << S_FW_IQ_CMD_IQSTOP)\n#define G_FW_IQ_CMD_IQSTOP(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)\n#define F_FW_IQ_CMD_IQSTOP\tV_FW_IQ_CMD_IQSTOP(1U)\n\n#define S_FW_IQ_CMD_TYPE\t29\n#define M_FW_IQ_CMD_TYPE\t0x7\n#define V_FW_IQ_CMD_TYPE(x)\t((x) << S_FW_IQ_CMD_TYPE)\n#define G_FW_IQ_CMD_TYPE(x)\t(((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)\n\n#define S_FW_IQ_CMD_IQASYNCH\t28\n#define M_FW_IQ_CMD_IQASYNCH\t0x1\n#define V_FW_IQ_CMD_IQASYNCH(x)\t((x) << S_FW_IQ_CMD_IQASYNCH)\n#define G_FW_IQ_CMD_IQASYNCH(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)\n#define F_FW_IQ_CMD_IQASYNCH\tV_FW_IQ_CMD_IQASYNCH(1U)\n\n#define S_FW_IQ_CMD_VIID\t16\n#define M_FW_IQ_CMD_VIID\t0xfff\n#define V_FW_IQ_CMD_VIID(x)\t((x) << S_FW_IQ_CMD_VIID)\n#define G_FW_IQ_CMD_VIID(x)\t(((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)\n\n#define S_FW_IQ_CMD_IQANDST\t15\n#define M_FW_IQ_CMD_IQANDST\t0x1\n#define V_FW_IQ_CMD_IQANDST(x)\t((x) << S_FW_IQ_CMD_IQANDST)\n#define G_FW_IQ_CMD_IQANDST(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)\n#define F_FW_IQ_CMD_IQANDST\tV_FW_IQ_CMD_IQANDST(1U)\n\n#define S_FW_IQ_CMD_IQANUD\t12\n#define M_FW_IQ_CMD_IQANUD\t0x3\n#define V_FW_IQ_CMD_IQANUD(x)\t((x) << S_FW_IQ_CMD_IQANUD)\n#define G_FW_IQ_CMD_IQANUD(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)\n\n#define S_FW_IQ_CMD_IQANDSTINDEX\t0\n#define M_FW_IQ_CMD_IQANDSTINDEX\t0xfff\n#define V_FW_IQ_CMD_IQANDSTINDEX(x)\t((x) << S_FW_IQ_CMD_IQANDSTINDEX)\n#define G_FW_IQ_CMD_IQANDSTINDEX(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)\n\n#define S_FW_IQ_CMD_IQGTSMODE\t\t14\n#define M_FW_IQ_CMD_IQGTSMODE\t\t0x1\n#define V_FW_IQ_CMD_IQGTSMODE(x)\t((x) << S_FW_IQ_CMD_IQGTSMODE)\n#define G_FW_IQ_CMD_IQGTSMODE(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)\n#define F_FW_IQ_CMD_IQGTSMODE\tV_FW_IQ_CMD_IQGTSMODE(1U)\n\n#define S_FW_IQ_CMD_IQPCIECH\t12\n#define M_FW_IQ_CMD_IQPCIECH\t0x3\n#define V_FW_IQ_CMD_IQPCIECH(x)\t((x) << S_FW_IQ_CMD_IQPCIECH)\n#define G_FW_IQ_CMD_IQPCIECH(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)\n\n#define S_FW_IQ_CMD_IQINTCNTTHRESH\t4\n#define M_FW_IQ_CMD_IQINTCNTTHRESH\t0x3\n#define V_FW_IQ_CMD_IQINTCNTTHRESH(x)\t((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)\n#define G_FW_IQ_CMD_IQINTCNTTHRESH(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)\n\n#define S_FW_IQ_CMD_IQESIZE\t0\n#define M_FW_IQ_CMD_IQESIZE\t0x3\n#define V_FW_IQ_CMD_IQESIZE(x)\t((x) << S_FW_IQ_CMD_IQESIZE)\n#define G_FW_IQ_CMD_IQESIZE(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)\n\n#define S_FW_IQ_CMD_IQFLINTCONGEN\t27\n#define M_FW_IQ_CMD_IQFLINTCONGEN\t0x1\n#define V_FW_IQ_CMD_IQFLINTCONGEN(x)\t((x) << S_FW_IQ_CMD_IQFLINTCONGEN)\n#define G_FW_IQ_CMD_IQFLINTCONGEN(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)\n#define F_FW_IQ_CMD_IQFLINTCONGEN\tV_FW_IQ_CMD_IQFLINTCONGEN(1U)\n\n#define S_FW_IQ_CMD_FL0CNGCHMAP\t\t20\n#define M_FW_IQ_CMD_FL0CNGCHMAP\t\t0xf\n#define V_FW_IQ_CMD_FL0CNGCHMAP(x)\t((x) << S_FW_IQ_CMD_FL0CNGCHMAP)\n#define G_FW_IQ_CMD_FL0CNGCHMAP(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)\n\n#define S_FW_IQ_CMD_FL0DATARO\t\t12\n#define M_FW_IQ_CMD_FL0DATARO\t\t0x1\n#define V_FW_IQ_CMD_FL0DATARO(x)\t((x) << S_FW_IQ_CMD_FL0DATARO)\n#define G_FW_IQ_CMD_FL0DATARO(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)\n#define F_FW_IQ_CMD_FL0DATARO\tV_FW_IQ_CMD_FL0DATARO(1U)\n\n#define S_FW_IQ_CMD_FL0CONGCIF\t\t11\n#define M_FW_IQ_CMD_FL0CONGCIF\t\t0x1\n#define V_FW_IQ_CMD_FL0CONGCIF(x)\t((x) << S_FW_IQ_CMD_FL0CONGCIF)\n#define G_FW_IQ_CMD_FL0CONGCIF(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)\n#define F_FW_IQ_CMD_FL0CONGCIF\tV_FW_IQ_CMD_FL0CONGCIF(1U)\n\n#define S_FW_IQ_CMD_FL0FETCHRO\t\t6\n#define M_FW_IQ_CMD_FL0FETCHRO\t\t0x1\n#define V_FW_IQ_CMD_FL0FETCHRO(x)\t((x) << S_FW_IQ_CMD_FL0FETCHRO)\n#define G_FW_IQ_CMD_FL0FETCHRO(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)\n#define F_FW_IQ_CMD_FL0FETCHRO\tV_FW_IQ_CMD_FL0FETCHRO(1U)\n\n#define S_FW_IQ_CMD_FL0HOSTFCMODE\t4\n#define M_FW_IQ_CMD_FL0HOSTFCMODE\t0x3\n#define V_FW_IQ_CMD_FL0HOSTFCMODE(x)\t((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)\n#define G_FW_IQ_CMD_FL0HOSTFCMODE(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)\n\n#define S_FW_IQ_CMD_FL0PADEN\t2\n#define M_FW_IQ_CMD_FL0PADEN\t0x1\n#define V_FW_IQ_CMD_FL0PADEN(x)\t((x) << S_FW_IQ_CMD_FL0PADEN)\n#define G_FW_IQ_CMD_FL0PADEN(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)\n#define F_FW_IQ_CMD_FL0PADEN\tV_FW_IQ_CMD_FL0PADEN(1U)\n\n#define S_FW_IQ_CMD_FL0PACKEN\t\t1\n#define M_FW_IQ_CMD_FL0PACKEN\t\t0x1\n#define V_FW_IQ_CMD_FL0PACKEN(x)\t((x) << S_FW_IQ_CMD_FL0PACKEN)\n#define G_FW_IQ_CMD_FL0PACKEN(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)\n#define F_FW_IQ_CMD_FL0PACKEN\tV_FW_IQ_CMD_FL0PACKEN(1U)\n\n#define S_FW_IQ_CMD_FL0CONGEN\t\t0\n#define M_FW_IQ_CMD_FL0CONGEN\t\t0x1\n#define V_FW_IQ_CMD_FL0CONGEN(x)\t((x) << S_FW_IQ_CMD_FL0CONGEN)\n#define G_FW_IQ_CMD_FL0CONGEN(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)\n#define F_FW_IQ_CMD_FL0CONGEN\tV_FW_IQ_CMD_FL0CONGEN(1U)\n\n#define S_FW_IQ_CMD_FL0FBMIN\t7\n#define M_FW_IQ_CMD_FL0FBMIN\t0x7\n#define V_FW_IQ_CMD_FL0FBMIN(x)\t((x) << S_FW_IQ_CMD_FL0FBMIN)\n#define G_FW_IQ_CMD_FL0FBMIN(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)\n\n#define S_FW_IQ_CMD_FL0FBMAX\t4\n#define M_FW_IQ_CMD_FL0FBMAX\t0x7\n#define V_FW_IQ_CMD_FL0FBMAX(x)\t((x) << S_FW_IQ_CMD_FL0FBMAX)\n#define G_FW_IQ_CMD_FL0FBMAX(x)\t\\\n\t(((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)\n\nstruct fw_eq_eth_cmd {\n\t__be32 op_to_vfn;\n\t__be32 alloc_to_len16;\n\t__be32 eqid_pkd;\n\t__be32 physeqid_pkd;\n\t__be32 fetchszm_to_iqid;\n\t__be32 dcaen_to_eqsize;\n\t__be64 eqaddr;\n\t__be32 autoequiqe_to_viid;\n\t__be32 r8_lo;\n\t__be64 r9;\n};\n\n#define S_FW_EQ_ETH_CMD_PFN\t8\n#define M_FW_EQ_ETH_CMD_PFN\t0x7\n#define V_FW_EQ_ETH_CMD_PFN(x)\t((x) << S_FW_EQ_ETH_CMD_PFN)\n#define G_FW_EQ_ETH_CMD_PFN(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)\n\n#define S_FW_EQ_ETH_CMD_VFN\t0\n#define M_FW_EQ_ETH_CMD_VFN\t0xff\n#define V_FW_EQ_ETH_CMD_VFN(x)\t((x) << S_FW_EQ_ETH_CMD_VFN)\n#define G_FW_EQ_ETH_CMD_VFN(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)\n\n#define S_FW_EQ_ETH_CMD_ALLOC\t\t31\n#define M_FW_EQ_ETH_CMD_ALLOC\t\t0x1\n#define V_FW_EQ_ETH_CMD_ALLOC(x)\t((x) << S_FW_EQ_ETH_CMD_ALLOC)\n#define G_FW_EQ_ETH_CMD_ALLOC(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)\n#define F_FW_EQ_ETH_CMD_ALLOC\tV_FW_EQ_ETH_CMD_ALLOC(1U)\n\n#define S_FW_EQ_ETH_CMD_FREE\t30\n#define M_FW_EQ_ETH_CMD_FREE\t0x1\n#define V_FW_EQ_ETH_CMD_FREE(x)\t((x) << S_FW_EQ_ETH_CMD_FREE)\n#define G_FW_EQ_ETH_CMD_FREE(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)\n#define F_FW_EQ_ETH_CMD_FREE\tV_FW_EQ_ETH_CMD_FREE(1U)\n\n#define S_FW_EQ_ETH_CMD_EQSTART\t\t28\n#define M_FW_EQ_ETH_CMD_EQSTART\t\t0x1\n#define V_FW_EQ_ETH_CMD_EQSTART(x)\t((x) << S_FW_EQ_ETH_CMD_EQSTART)\n#define G_FW_EQ_ETH_CMD_EQSTART(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)\n#define F_FW_EQ_ETH_CMD_EQSTART\tV_FW_EQ_ETH_CMD_EQSTART(1U)\n\n#define S_FW_EQ_ETH_CMD_EQID\t0\n#define M_FW_EQ_ETH_CMD_EQID\t0xfffff\n#define V_FW_EQ_ETH_CMD_EQID(x)\t((x) << S_FW_EQ_ETH_CMD_EQID)\n#define G_FW_EQ_ETH_CMD_EQID(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)\n\n#define S_FW_EQ_ETH_CMD_FETCHRO\t\t22\n#define M_FW_EQ_ETH_CMD_FETCHRO\t\t0x1\n#define V_FW_EQ_ETH_CMD_FETCHRO(x)\t((x) << S_FW_EQ_ETH_CMD_FETCHRO)\n#define G_FW_EQ_ETH_CMD_FETCHRO(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)\n#define F_FW_EQ_ETH_CMD_FETCHRO\tV_FW_EQ_ETH_CMD_FETCHRO(1U)\n\n#define S_FW_EQ_ETH_CMD_HOSTFCMODE\t20\n#define M_FW_EQ_ETH_CMD_HOSTFCMODE\t0x3\n#define V_FW_EQ_ETH_CMD_HOSTFCMODE(x)\t((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)\n#define G_FW_EQ_ETH_CMD_HOSTFCMODE(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)\n\n#define S_FW_EQ_ETH_CMD_PCIECHN\t\t16\n#define M_FW_EQ_ETH_CMD_PCIECHN\t\t0x3\n#define V_FW_EQ_ETH_CMD_PCIECHN(x)\t((x) << S_FW_EQ_ETH_CMD_PCIECHN)\n#define G_FW_EQ_ETH_CMD_PCIECHN(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)\n\n#define S_FW_EQ_ETH_CMD_IQID\t0\n#define M_FW_EQ_ETH_CMD_IQID\t0xffff\n#define V_FW_EQ_ETH_CMD_IQID(x)\t((x) << S_FW_EQ_ETH_CMD_IQID)\n#define G_FW_EQ_ETH_CMD_IQID(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)\n\n#define S_FW_EQ_ETH_CMD_FBMIN\t\t23\n#define M_FW_EQ_ETH_CMD_FBMIN\t\t0x7\n#define V_FW_EQ_ETH_CMD_FBMIN(x)\t((x) << S_FW_EQ_ETH_CMD_FBMIN)\n#define G_FW_EQ_ETH_CMD_FBMIN(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)\n\n#define S_FW_EQ_ETH_CMD_FBMAX\t\t20\n#define M_FW_EQ_ETH_CMD_FBMAX\t\t0x7\n#define V_FW_EQ_ETH_CMD_FBMAX(x)\t((x) << S_FW_EQ_ETH_CMD_FBMAX)\n#define G_FW_EQ_ETH_CMD_FBMAX(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)\n\n#define S_FW_EQ_ETH_CMD_CIDXFTHRESH\t16\n#define M_FW_EQ_ETH_CMD_CIDXFTHRESH\t0x7\n#define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x)\t((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)\n#define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)\n\n#define S_FW_EQ_ETH_CMD_EQSIZE\t\t0\n#define M_FW_EQ_ETH_CMD_EQSIZE\t\t0xffff\n#define V_FW_EQ_ETH_CMD_EQSIZE(x)\t((x) << S_FW_EQ_ETH_CMD_EQSIZE)\n#define G_FW_EQ_ETH_CMD_EQSIZE(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)\n\n#define S_FW_EQ_ETH_CMD_AUTOEQUEQE\t30\n#define M_FW_EQ_ETH_CMD_AUTOEQUEQE\t0x1\n#define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x)\t((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)\n#define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)\n#define F_FW_EQ_ETH_CMD_AUTOEQUEQE\tV_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)\n\n#define S_FW_EQ_ETH_CMD_VIID\t16\n#define M_FW_EQ_ETH_CMD_VIID\t0xfff\n#define V_FW_EQ_ETH_CMD_VIID(x)\t((x) << S_FW_EQ_ETH_CMD_VIID)\n#define G_FW_EQ_ETH_CMD_VIID(x)\t\\\n\t(((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)\n\nenum fw_vi_func {\n\tFW_VI_FUNC_ETH,\n};\n\nstruct fw_vi_cmd {\n\t__be32 op_to_vfn;\n\t__be32 alloc_to_len16;\n\t__be16 type_to_viid;\n\t__u8 mac[6];\n\t__u8 portid_pkd;\n\t__u8 nmac;\n\t__u8 nmac0[6];\n\t__be16 norss_rsssize;\n\t__u8 nmac1[6];\n\t__be16 idsiiq_pkd;\n\t__u8 nmac2[6];\n\t__be16 idseiq_pkd;\n\t__u8 nmac3[6];\n\t__be64 r9;\n\t__be64 r10;\n};\n\n#define S_FW_VI_CMD_PFN\t\t8\n#define M_FW_VI_CMD_PFN\t\t0x7\n#define V_FW_VI_CMD_PFN(x)\t((x) << S_FW_VI_CMD_PFN)\n#define G_FW_VI_CMD_PFN(x)\t(((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)\n\n#define S_FW_VI_CMD_VFN\t\t0\n#define M_FW_VI_CMD_VFN\t\t0xff\n#define V_FW_VI_CMD_VFN(x)\t((x) << S_FW_VI_CMD_VFN)\n#define G_FW_VI_CMD_VFN(x)\t(((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)\n\n#define S_FW_VI_CMD_ALLOC\t31\n#define M_FW_VI_CMD_ALLOC\t0x1\n#define V_FW_VI_CMD_ALLOC(x)\t((x) << S_FW_VI_CMD_ALLOC)\n#define G_FW_VI_CMD_ALLOC(x)\t\\\n\t(((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)\n#define F_FW_VI_CMD_ALLOC\tV_FW_VI_CMD_ALLOC(1U)\n\n#define S_FW_VI_CMD_FREE\t30\n#define M_FW_VI_CMD_FREE\t0x1\n#define V_FW_VI_CMD_FREE(x)\t((x) << S_FW_VI_CMD_FREE)\n#define G_FW_VI_CMD_FREE(x)\t(((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)\n#define F_FW_VI_CMD_FREE\tV_FW_VI_CMD_FREE(1U)\n\n#define S_FW_VI_CMD_TYPE\t15\n#define M_FW_VI_CMD_TYPE\t0x1\n#define V_FW_VI_CMD_TYPE(x)\t((x) << S_FW_VI_CMD_TYPE)\n#define G_FW_VI_CMD_TYPE(x)\t(((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)\n#define F_FW_VI_CMD_TYPE\tV_FW_VI_CMD_TYPE(1U)\n\n#define S_FW_VI_CMD_FUNC\t12\n#define M_FW_VI_CMD_FUNC\t0x7\n#define V_FW_VI_CMD_FUNC(x)\t((x) << S_FW_VI_CMD_FUNC)\n#define G_FW_VI_CMD_FUNC(x)\t(((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)\n\n#define S_FW_VI_CMD_VIID\t0\n#define M_FW_VI_CMD_VIID\t0xfff\n#define V_FW_VI_CMD_VIID(x)\t((x) << S_FW_VI_CMD_VIID)\n#define G_FW_VI_CMD_VIID(x)\t(((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)\n\n#define S_FW_VI_CMD_PORTID\t4\n#define M_FW_VI_CMD_PORTID\t0xf\n#define V_FW_VI_CMD_PORTID(x)\t((x) << S_FW_VI_CMD_PORTID)\n#define G_FW_VI_CMD_PORTID(x)\t\\\n\t(((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)\n\n#define S_FW_VI_CMD_RSSSIZE\t0\n#define M_FW_VI_CMD_RSSSIZE\t0x7ff\n#define V_FW_VI_CMD_RSSSIZE(x)\t((x) << S_FW_VI_CMD_RSSSIZE)\n#define G_FW_VI_CMD_RSSSIZE(x)\t\\\n\t(((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)\n\n/* Special VI_MAC command index ids */\n#define FW_VI_MAC_ADD_MAC\t\t0x3FF\n#define FW_VI_MAC_ADD_PERSIST_MAC\t0x3FE\n\nenum fw_vi_mac_smac {\n\tFW_VI_MAC_MPS_TCAM_ENTRY,\n\tFW_VI_MAC_SMT_AND_MPSTCAM\n};\n\nstruct fw_vi_mac_cmd {\n\t__be32 op_to_viid;\n\t__be32 freemacs_to_len16;\n\tunion fw_vi_mac {\n\t\tstruct fw_vi_mac_exact {\n\t\t\t__be16 valid_to_idx;\n\t\t\t__u8 macaddr[6];\n\t\t} exact[7];\n\t\tstruct fw_vi_mac_hash {\n\t\t\t__be64 hashvec;\n\t\t} hash;\n\t} u;\n};\n\n#define S_FW_VI_MAC_CMD_VIID\t0\n#define M_FW_VI_MAC_CMD_VIID\t0xfff\n#define V_FW_VI_MAC_CMD_VIID(x)\t((x) << S_FW_VI_MAC_CMD_VIID)\n#define G_FW_VI_MAC_CMD_VIID(x)\t\\\n\t(((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)\n\n#define S_FW_VI_MAC_CMD_VALID\t\t15\n#define M_FW_VI_MAC_CMD_VALID\t\t0x1\n#define V_FW_VI_MAC_CMD_VALID(x)\t((x) << S_FW_VI_MAC_CMD_VALID)\n#define G_FW_VI_MAC_CMD_VALID(x)\t\\\n\t(((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)\n#define F_FW_VI_MAC_CMD_VALID\tV_FW_VI_MAC_CMD_VALID(1U)\n\n#define S_FW_VI_MAC_CMD_SMAC_RESULT\t10\n#define M_FW_VI_MAC_CMD_SMAC_RESULT\t0x3\n#define V_FW_VI_MAC_CMD_SMAC_RESULT(x)\t((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)\n#define G_FW_VI_MAC_CMD_SMAC_RESULT(x)\t\\\n\t(((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)\n\n#define S_FW_VI_MAC_CMD_IDX\t0\n#define M_FW_VI_MAC_CMD_IDX\t0x3ff\n#define V_FW_VI_MAC_CMD_IDX(x)\t((x) << S_FW_VI_MAC_CMD_IDX)\n#define G_FW_VI_MAC_CMD_IDX(x)\t\\\n\t(((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)\n\nstruct fw_vi_rxmode_cmd {\n\t__be32 op_to_viid;\n\t__be32 retval_len16;\n\t__be32 mtu_to_vlanexen;\n\t__be32 r4_lo;\n};\n\n#define S_FW_VI_RXMODE_CMD_VIID\t\t0\n#define M_FW_VI_RXMODE_CMD_VIID\t\t0xfff\n#define V_FW_VI_RXMODE_CMD_VIID(x)\t((x) << S_FW_VI_RXMODE_CMD_VIID)\n#define G_FW_VI_RXMODE_CMD_VIID(x)\t\\\n\t(((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)\n\n#define S_FW_VI_RXMODE_CMD_MTU\t\t16\n#define M_FW_VI_RXMODE_CMD_MTU\t\t0xffff\n#define V_FW_VI_RXMODE_CMD_MTU(x)\t((x) << S_FW_VI_RXMODE_CMD_MTU)\n#define G_FW_VI_RXMODE_CMD_MTU(x)\t\\\n\t(((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)\n\n#define S_FW_VI_RXMODE_CMD_PROMISCEN\t14\n#define M_FW_VI_RXMODE_CMD_PROMISCEN\t0x3\n#define V_FW_VI_RXMODE_CMD_PROMISCEN(x)\t((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)\n#define G_FW_VI_RXMODE_CMD_PROMISCEN(x)\t\\\n\t(((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)\n\n#define S_FW_VI_RXMODE_CMD_ALLMULTIEN\t\t12\n#define M_FW_VI_RXMODE_CMD_ALLMULTIEN\t\t0x3\n#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x)\t\\\n\t((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)\n#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x)\t\\\n\t(((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)\n\n#define S_FW_VI_RXMODE_CMD_BROADCASTEN\t\t10\n#define M_FW_VI_RXMODE_CMD_BROADCASTEN\t\t0x3\n#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x)\t\\\n\t((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)\n#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x)\t\\\n\t(((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \\\n\t M_FW_VI_RXMODE_CMD_BROADCASTEN)\n\n#define S_FW_VI_RXMODE_CMD_VLANEXEN\t8\n#define M_FW_VI_RXMODE_CMD_VLANEXEN\t0x3\n#define V_FW_VI_RXMODE_CMD_VLANEXEN(x)\t((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)\n#define G_FW_VI_RXMODE_CMD_VLANEXEN(x)\t\\\n\t(((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)\n\nstruct fw_vi_enable_cmd {\n\t__be32 op_to_viid;\n\t__be32 ien_to_len16;\n\t__be16 blinkdur;\n\t__be16 r3;\n\t__be32 r4;\n};\n\n#define S_FW_VI_ENABLE_CMD_VIID\t\t0\n#define M_FW_VI_ENABLE_CMD_VIID\t\t0xfff\n#define V_FW_VI_ENABLE_CMD_VIID(x)\t((x) << S_FW_VI_ENABLE_CMD_VIID)\n#define G_FW_VI_ENABLE_CMD_VIID(x)\t\\\n\t(((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)\n\n#define S_FW_VI_ENABLE_CMD_IEN\t\t31\n#define M_FW_VI_ENABLE_CMD_IEN\t\t0x1\n#define V_FW_VI_ENABLE_CMD_IEN(x)\t((x) << S_FW_VI_ENABLE_CMD_IEN)\n#define G_FW_VI_ENABLE_CMD_IEN(x)\t\\\n\t(((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)\n#define F_FW_VI_ENABLE_CMD_IEN\tV_FW_VI_ENABLE_CMD_IEN(1U)\n\n#define S_FW_VI_ENABLE_CMD_EEN\t\t30\n#define M_FW_VI_ENABLE_CMD_EEN\t\t0x1\n#define V_FW_VI_ENABLE_CMD_EEN(x)\t((x) << S_FW_VI_ENABLE_CMD_EEN)\n#define G_FW_VI_ENABLE_CMD_EEN(x)\t\\\n\t(((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)\n#define F_FW_VI_ENABLE_CMD_EEN\tV_FW_VI_ENABLE_CMD_EEN(1U)\n\n#define S_FW_VI_ENABLE_CMD_DCB_INFO\t28\n#define M_FW_VI_ENABLE_CMD_DCB_INFO\t0x1\n#define V_FW_VI_ENABLE_CMD_DCB_INFO(x)\t((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)\n#define G_FW_VI_ENABLE_CMD_DCB_INFO(x)\t\\\n\t(((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)\n#define F_FW_VI_ENABLE_CMD_DCB_INFO\tV_FW_VI_ENABLE_CMD_DCB_INFO(1U)\n\n/* VI PF stats offset definitions */\n#define VI_PF_NUM_STATS\t17\nenum fw_vi_stats_pf_index {\n\tFW_VI_PF_STAT_TX_BCAST_BYTES_IX,\n\tFW_VI_PF_STAT_TX_BCAST_FRAMES_IX,\n\tFW_VI_PF_STAT_TX_MCAST_BYTES_IX,\n\tFW_VI_PF_STAT_TX_MCAST_FRAMES_IX,\n\tFW_VI_PF_STAT_TX_UCAST_BYTES_IX,\n\tFW_VI_PF_STAT_TX_UCAST_FRAMES_IX,\n\tFW_VI_PF_STAT_TX_OFLD_BYTES_IX,\n\tFW_VI_PF_STAT_TX_OFLD_FRAMES_IX,\n\tFW_VI_PF_STAT_RX_BYTES_IX,\n\tFW_VI_PF_STAT_RX_FRAMES_IX,\n\tFW_VI_PF_STAT_RX_BCAST_BYTES_IX,\n\tFW_VI_PF_STAT_RX_BCAST_FRAMES_IX,\n\tFW_VI_PF_STAT_RX_MCAST_BYTES_IX,\n\tFW_VI_PF_STAT_RX_MCAST_FRAMES_IX,\n\tFW_VI_PF_STAT_RX_UCAST_BYTES_IX,\n\tFW_VI_PF_STAT_RX_UCAST_FRAMES_IX,\n\tFW_VI_PF_STAT_RX_ERR_FRAMES_IX\n};\n\nstruct fw_vi_stats_cmd {\n\t__be32 op_to_viid;\n\t__be32 retval_len16;\n\tunion fw_vi_stats {\n\t\tstruct fw_vi_stats_ctl {\n\t\t\t__be16 nstats_ix;\n\t\t\t__be16 r6;\n\t\t\t__be32 r7;\n\t\t\t__be64 stat0;\n\t\t\t__be64 stat1;\n\t\t\t__be64 stat2;\n\t\t\t__be64 stat3;\n\t\t\t__be64 stat4;\n\t\t\t__be64 stat5;\n\t\t} ctl;\n\t\tstruct fw_vi_stats_pf {\n\t\t\t__be64 tx_bcast_bytes;\n\t\t\t__be64 tx_bcast_frames;\n\t\t\t__be64 tx_mcast_bytes;\n\t\t\t__be64 tx_mcast_frames;\n\t\t\t__be64 tx_ucast_bytes;\n\t\t\t__be64 tx_ucast_frames;\n\t\t\t__be64 tx_offload_bytes;\n\t\t\t__be64 tx_offload_frames;\n\t\t\t__be64 rx_pf_bytes;\n\t\t\t__be64 rx_pf_frames;\n\t\t\t__be64 rx_bcast_bytes;\n\t\t\t__be64 rx_bcast_frames;\n\t\t\t__be64 rx_mcast_bytes;\n\t\t\t__be64 rx_mcast_frames;\n\t\t\t__be64 rx_ucast_bytes;\n\t\t\t__be64 rx_ucast_frames;\n\t\t\t__be64 rx_err_frames;\n\t\t} pf;\n\t\tstruct fw_vi_stats_vf {\n\t\t\t__be64 tx_bcast_bytes;\n\t\t\t__be64 tx_bcast_frames;\n\t\t\t__be64 tx_mcast_bytes;\n\t\t\t__be64 tx_mcast_frames;\n\t\t\t__be64 tx_ucast_bytes;\n\t\t\t__be64 tx_ucast_frames;\n\t\t\t__be64 tx_drop_frames;\n\t\t\t__be64 tx_offload_bytes;\n\t\t\t__be64 tx_offload_frames;\n\t\t\t__be64 rx_bcast_bytes;\n\t\t\t__be64 rx_bcast_frames;\n\t\t\t__be64 rx_mcast_bytes;\n\t\t\t__be64 rx_mcast_frames;\n\t\t\t__be64 rx_ucast_bytes;\n\t\t\t__be64 rx_ucast_frames;\n\t\t\t__be64 rx_err_frames;\n\t\t} vf;\n\t} u;\n};\n\n/* port capabilities bitmap */\nenum fw_port_cap {\n\tFW_PORT_CAP_SPEED_100M\t\t= 0x0001,\n\tFW_PORT_CAP_SPEED_1G\t\t= 0x0002,\n\tFW_PORT_CAP_SPEED_2_5G\t\t= 0x0004,\n\tFW_PORT_CAP_SPEED_10G\t\t= 0x0008,\n\tFW_PORT_CAP_SPEED_40G\t\t= 0x0010,\n\tFW_PORT_CAP_SPEED_100G\t\t= 0x0020,\n\tFW_PORT_CAP_FC_RX\t\t= 0x0040,\n\tFW_PORT_CAP_FC_TX\t\t= 0x0080,\n\tFW_PORT_CAP_ANEG\t\t= 0x0100,\n\tFW_PORT_CAP_MDIX\t\t= 0x0200,\n\tFW_PORT_CAP_MDIAUTO\t\t= 0x0400,\n\tFW_PORT_CAP_FEC\t\t\t= 0x0800,\n\tFW_PORT_CAP_TECHKR\t\t= 0x1000,\n\tFW_PORT_CAP_TECHKX4\t\t= 0x2000,\n\tFW_PORT_CAP_802_3_PAUSE\t\t= 0x4000,\n\tFW_PORT_CAP_802_3_ASM_DIR\t= 0x8000,\n};\n\nenum fw_port_mdi {\n\tFW_PORT_CAP_MDI_AUTO,\n};\n\n#define S_FW_PORT_CAP_MDI 9\n#define M_FW_PORT_CAP_MDI 3\n#define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)\n#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)\n\nenum fw_port_action {\n\tFW_PORT_ACTION_L1_CFG\t\t= 0x0001,\n\tFW_PORT_ACTION_GET_PORT_INFO\t= 0x0003,\n};\n\nstruct fw_port_cmd {\n\t__be32 op_to_portid;\n\t__be32 action_to_len16;\n\tunion fw_port {\n\t\tstruct fw_port_l1cfg {\n\t\t\t__be32 rcap;\n\t\t\t__be32 r;\n\t\t} l1cfg;\n\t\tstruct fw_port_l2cfg {\n\t\t\t__u8 ctlbf;\n\t\t\t__u8 ovlan3_to_ivlan0;\n\t\t\t__be16 ivlantype;\n\t\t\t__be16 txipg_force_pinfo;\n\t\t\t__be16 mtu;\n\t\t\t__be16 ovlan0mask;\n\t\t\t__be16 ovlan0type;\n\t\t\t__be16 ovlan1mask;\n\t\t\t__be16 ovlan1type;\n\t\t\t__be16 ovlan2mask;\n\t\t\t__be16 ovlan2type;\n\t\t\t__be16 ovlan3mask;\n\t\t\t__be16 ovlan3type;\n\t\t} l2cfg;\n\t\tstruct fw_port_info {\n\t\t\t__be32 lstatus_to_modtype;\n\t\t\t__be16 pcap;\n\t\t\t__be16 acap;\n\t\t\t__be16 mtu;\n\t\t\t__u8 cbllen;\n\t\t\t__u8 auxlinfo;\n\t\t\t__u8 dcbxdis_pkd;\n\t\t\t__u8 r8_lo;\n\t\t\t__be16 lpacap;\n\t\t\t__be64 r9;\n\t\t} info;\n\t\tstruct fw_port_diags {\n\t\t\t__u8 diagop;\n\t\t\t__u8 r[3];\n\t\t\t__be32 diagval;\n\t\t} diags;\n\t\tunion fw_port_dcb {\n\t\t\tstruct fw_port_dcb_pgid {\n\t\t\t\t__u8 type;\n\t\t\t\t__u8 apply_pkd;\n\t\t\t\t__u8 r10_lo[2];\n\t\t\t\t__be32 pgid;\n\t\t\t\t__be64 r11;\n\t\t\t} pgid;\n\t\t\tstruct fw_port_dcb_pgrate {\n\t\t\t\t__u8 type;\n\t\t\t\t__u8 apply_pkd;\n\t\t\t\t__u8 r10_lo[5];\n\t\t\t\t__u8 num_tcs_supported;\n\t\t\t\t__u8 pgrate[8];\n\t\t\t\t__u8 tsa[8];\n\t\t\t} pgrate;\n\t\t\tstruct fw_port_dcb_priorate {\n\t\t\t\t__u8 type;\n\t\t\t\t__u8 apply_pkd;\n\t\t\t\t__u8 r10_lo[6];\n\t\t\t\t__u8 strict_priorate[8];\n\t\t\t} priorate;\n\t\t\tstruct fw_port_dcb_pfc {\n\t\t\t\t__u8 type;\n\t\t\t\t__u8 pfcen;\n\t\t\t\t__u8 r10[5];\n\t\t\t\t__u8 max_pfc_tcs;\n\t\t\t\t__be64 r11;\n\t\t\t} pfc;\n\t\t\tstruct fw_port_app_priority {\n\t\t\t\t__u8 type;\n\t\t\t\t__u8 r10[2];\n\t\t\t\t__u8 idx;\n\t\t\t\t__u8 user_prio_map;\n\t\t\t\t__u8 sel_field;\n\t\t\t\t__be16 protocolid;\n\t\t\t\t__be64 r12;\n\t\t\t} app_priority;\n\t\t\tstruct fw_port_dcb_control {\n\t\t\t\t__u8 type;\n\t\t\t\t__u8 all_syncd_pkd;\n\t\t\t\t__be16 dcb_version_to_app_state;\n\t\t\t\t__be32 r11;\n\t\t\t\t__be64 r12;\n\t\t\t} control;\n\t\t} dcb;\n\t} u;\n};\n\n#define S_FW_PORT_CMD_PORTID\t0\n#define M_FW_PORT_CMD_PORTID\t0xf\n#define V_FW_PORT_CMD_PORTID(x)\t((x) << S_FW_PORT_CMD_PORTID)\n#define G_FW_PORT_CMD_PORTID(x)\t\\\n\t(((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)\n\n#define S_FW_PORT_CMD_ACTION\t16\n#define M_FW_PORT_CMD_ACTION\t0xffff\n#define V_FW_PORT_CMD_ACTION(x)\t((x) << S_FW_PORT_CMD_ACTION)\n#define G_FW_PORT_CMD_ACTION(x)\t\\\n\t(((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)\n\n#define S_FW_PORT_CMD_LSTATUS\t\t31\n#define M_FW_PORT_CMD_LSTATUS\t\t0x1\n#define V_FW_PORT_CMD_LSTATUS(x)\t((x) << S_FW_PORT_CMD_LSTATUS)\n#define G_FW_PORT_CMD_LSTATUS(x)\t\\\n\t(((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)\n#define F_FW_PORT_CMD_LSTATUS\tV_FW_PORT_CMD_LSTATUS(1U)\n\n#define S_FW_PORT_CMD_LSPEED\t24\n#define M_FW_PORT_CMD_LSPEED\t0x3f\n#define V_FW_PORT_CMD_LSPEED(x)\t((x) << S_FW_PORT_CMD_LSPEED)\n#define G_FW_PORT_CMD_LSPEED(x)\t\\\n\t(((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)\n\n#define S_FW_PORT_CMD_TXPAUSE\t\t23\n#define M_FW_PORT_CMD_TXPAUSE\t\t0x1\n#define V_FW_PORT_CMD_TXPAUSE(x)\t((x) << S_FW_PORT_CMD_TXPAUSE)\n#define G_FW_PORT_CMD_TXPAUSE(x)\t\\\n\t(((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)\n#define F_FW_PORT_CMD_TXPAUSE\tV_FW_PORT_CMD_TXPAUSE(1U)\n\n#define S_FW_PORT_CMD_RXPAUSE\t\t22\n#define M_FW_PORT_CMD_RXPAUSE\t\t0x1\n#define V_FW_PORT_CMD_RXPAUSE(x)\t((x) << S_FW_PORT_CMD_RXPAUSE)\n#define G_FW_PORT_CMD_RXPAUSE(x)\t\\\n\t(((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)\n#define F_FW_PORT_CMD_RXPAUSE\tV_FW_PORT_CMD_RXPAUSE(1U)\n\n#define S_FW_PORT_CMD_MDIOCAP\t\t21\n#define M_FW_PORT_CMD_MDIOCAP\t\t0x1\n#define V_FW_PORT_CMD_MDIOCAP(x)\t((x) << S_FW_PORT_CMD_MDIOCAP)\n#define G_FW_PORT_CMD_MDIOCAP(x)\t\\\n\t(((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)\n#define F_FW_PORT_CMD_MDIOCAP\tV_FW_PORT_CMD_MDIOCAP(1U)\n\n#define S_FW_PORT_CMD_MDIOADDR\t\t16\n#define M_FW_PORT_CMD_MDIOADDR\t\t0x1f\n#define V_FW_PORT_CMD_MDIOADDR(x)\t((x) << S_FW_PORT_CMD_MDIOADDR)\n#define G_FW_PORT_CMD_MDIOADDR(x)\t\\\n\t(((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)\n\n#define S_FW_PORT_CMD_PTYPE\t8\n#define M_FW_PORT_CMD_PTYPE\t0x1f\n#define V_FW_PORT_CMD_PTYPE(x)\t((x) << S_FW_PORT_CMD_PTYPE)\n#define G_FW_PORT_CMD_PTYPE(x)\t\\\n\t(((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)\n\n#define S_FW_PORT_CMD_LINKDNRC\t\t5\n#define M_FW_PORT_CMD_LINKDNRC\t\t0x7\n#define V_FW_PORT_CMD_LINKDNRC(x)\t((x) << S_FW_PORT_CMD_LINKDNRC)\n#define G_FW_PORT_CMD_LINKDNRC(x)\t\\\n\t(((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)\n\n#define S_FW_PORT_CMD_MODTYPE\t\t0\n#define M_FW_PORT_CMD_MODTYPE\t\t0x1f\n#define V_FW_PORT_CMD_MODTYPE(x)\t((x) << S_FW_PORT_CMD_MODTYPE)\n#define G_FW_PORT_CMD_MODTYPE(x)\t\\\n\t(((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)\n\n/*\n * These are configured into the VPD and hence tools that generate\n * VPD may use this enumeration.\n * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed\n *\n * REMEMBER:\n * Update the Common Code t4_hw.c:t4_get_port_type_description()\n * with any new Firmware Port Technology Types!\n */\nenum fw_port_type {\n\tFW_PORT_TYPE_FIBER_XFI\t= 0, /* Y, 1, N, Y, N, N, 10G */\n\tFW_PORT_TYPE_FIBER_XAUI\t= 1, /* Y, 4, N, Y, N, N, 10G */\n\tFW_PORT_TYPE_BT_SGMII\t= 2, /* Y, 1, No, No, No, No, 1G/100M */\n\tFW_PORT_TYPE_BT_XFI\t= 3, /* Y, 1, No, No, No, No, 10G */\n\tFW_PORT_TYPE_BT_XAUI\t= 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */\n\tFW_PORT_TYPE_KX4\t= 5, /* No, 4, No, No, Yes, Yes, 10G */\n\tFW_PORT_TYPE_CX4\t= 6, /* No, 4, No, No, No, No, 10G */\n\tFW_PORT_TYPE_KX\t\t= 7, /* No, 1, No, No, Yes, No, 1G */\n\tFW_PORT_TYPE_KR\t\t= 8, /* No, 1, No, No, Yes, Yes, 10G */\n\tFW_PORT_TYPE_SFP\t= 9, /* No, 1, Yes, No, No, No, 10G */\n\tFW_PORT_TYPE_BP_AP\t= 10,\n\t/* No, 1, No, No, Yes, Yes, 10G, BP ANGE */\n\tFW_PORT_TYPE_BP4_AP\t= 11,\n\t/* No, 4, No, No, Yes, Yes, 10G, BP ANGE */\n\tFW_PORT_TYPE_QSFP_10G\t= 12, /* No, 1, Yes, No, No, No, 10G */\n\tFW_PORT_TYPE_QSA\t= 13, /* No, 1, Yes, No, No, No, 10G */\n\tFW_PORT_TYPE_QSFP\t= 14, /* No, 4, Yes, No, No, No, 40G */\n\tFW_PORT_TYPE_BP40_BA\t= 15,\n\t/* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */\n\n\tFW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE\n};\n\n/* These are read from module's EEPROM and determined once the\n * module is inserted.\n */\nenum fw_port_module_type {\n\tFW_PORT_MOD_TYPE_NA\t\t= 0x0,\n\tFW_PORT_MOD_TYPE_LR\t\t= 0x1,\n\tFW_PORT_MOD_TYPE_SR\t\t= 0x2,\n\tFW_PORT_MOD_TYPE_ER\t\t= 0x3,\n\tFW_PORT_MOD_TYPE_TWINAX_PASSIVE\t= 0x4,\n\tFW_PORT_MOD_TYPE_TWINAX_ACTIVE\t= 0x5,\n\tFW_PORT_MOD_TYPE_LRM\t\t= 0x6,\n\tFW_PORT_MOD_TYPE_ERROR\t\t= M_FW_PORT_CMD_MODTYPE - 3,\n\tFW_PORT_MOD_TYPE_UNKNOWN\t= M_FW_PORT_CMD_MODTYPE - 2,\n\tFW_PORT_MOD_TYPE_NOTSUPPORTED\t= M_FW_PORT_CMD_MODTYPE - 1,\n\tFW_PORT_MOD_TYPE_NONE\t\t= M_FW_PORT_CMD_MODTYPE\n};\n\n/* used by FW and tools may use this to generate VPD */\nenum fw_port_mod_sub_type {\n\tFW_PORT_MOD_SUB_TYPE_NA,\n\tFW_PORT_MOD_SUB_TYPE_MV88E114X\t= 0x1,\n\tFW_PORT_MOD_SUB_TYPE_TN8022\t= 0x2,\n\tFW_PORT_MOD_SUB_TYPE_AQ1202\t= 0x3,\n\tFW_PORT_MOD_SUB_TYPE_88x3120\t= 0x4,\n\tFW_PORT_MOD_SUB_TYPE_BCM84834\t= 0x5,\n\tFW_PORT_MOD_SUB_TYPE_BCM5482\t= 0x6,\n\tFW_PORT_MOD_SUB_TYPE_BCM84856\t= 0x7,\n\tFW_PORT_MOD_SUB_TYPE_BT_VSC8634\t= 0x8,\n\n\t/*\n\t * The following will never been in the VPD. They are TWINAX cable\n\t * lengths decoded from SFP+ module i2c PROMs. These should almost\n\t * certainly go somewhere else ...\n\t */\n\tFW_PORT_MOD_SUB_TYPE_TWINAX_1\t= 0x9,\n\tFW_PORT_MOD_SUB_TYPE_TWINAX_3\t= 0xA,\n\tFW_PORT_MOD_SUB_TYPE_TWINAX_5\t= 0xB,\n\tFW_PORT_MOD_SUB_TYPE_TWINAX_7\t= 0xC,\n};\n\n/* link down reason codes (3b) */\nenum fw_port_link_dn_rc {\n\tFW_PORT_LINK_DN_RC_NONE,\n\tFW_PORT_LINK_DN_RC_REMFLT,\t/* Remote fault detected */\n\tFW_PORT_LINK_DN_ANEG_F,\t\t/* Auto-negotiation fault */\n\tFW_PORT_LINK_DN_RESERVED3,\n\tFW_PORT_LINK_DN_OVERHEAT,\t/* Port overheated */\n\tFW_PORT_LINK_DN_UNKNOWN,\t/* Unable to determine reason */\n\tFW_PORT_LINK_DN_RX_LOS,\t\t/* No RX signal detected */\n\tFW_PORT_LINK_DN_RESERVED7\n};\n\n/* port stats */\n#define FW_NUM_PORT_STATS 50\n#define FW_NUM_PORT_TX_STATS 23\n#define FW_NUM_PORT_RX_STATS 27\n\nenum fw_port_stats_tx_index {\n\tFW_STAT_TX_PORT_BYTES_IX,\n\tFW_STAT_TX_PORT_FRAMES_IX,\n\tFW_STAT_TX_PORT_BCAST_IX,\n\tFW_STAT_TX_PORT_MCAST_IX,\n\tFW_STAT_TX_PORT_UCAST_IX,\n\tFW_STAT_TX_PORT_ERROR_IX,\n\tFW_STAT_TX_PORT_64B_IX,\n\tFW_STAT_TX_PORT_65B_127B_IX,\n\tFW_STAT_TX_PORT_128B_255B_IX,\n\tFW_STAT_TX_PORT_256B_511B_IX,\n\tFW_STAT_TX_PORT_512B_1023B_IX,\n\tFW_STAT_TX_PORT_1024B_1518B_IX,\n\tFW_STAT_TX_PORT_1519B_MAX_IX,\n\tFW_STAT_TX_PORT_DROP_IX,\n\tFW_STAT_TX_PORT_PAUSE_IX,\n\tFW_STAT_TX_PORT_PPP0_IX,\n\tFW_STAT_TX_PORT_PPP1_IX,\n\tFW_STAT_TX_PORT_PPP2_IX,\n\tFW_STAT_TX_PORT_PPP3_IX,\n\tFW_STAT_TX_PORT_PPP4_IX,\n\tFW_STAT_TX_PORT_PPP5_IX,\n\tFW_STAT_TX_PORT_PPP6_IX,\n\tFW_STAT_TX_PORT_PPP7_IX\n};\n\nenum fw_port_stat_rx_index {\n\tFW_STAT_RX_PORT_BYTES_IX,\n\tFW_STAT_RX_PORT_FRAMES_IX,\n\tFW_STAT_RX_PORT_BCAST_IX,\n\tFW_STAT_RX_PORT_MCAST_IX,\n\tFW_STAT_RX_PORT_UCAST_IX,\n\tFW_STAT_RX_PORT_MTU_ERROR_IX,\n\tFW_STAT_RX_PORT_MTU_CRC_ERROR_IX,\n\tFW_STAT_RX_PORT_CRC_ERROR_IX,\n\tFW_STAT_RX_PORT_LEN_ERROR_IX,\n\tFW_STAT_RX_PORT_SYM_ERROR_IX,\n\tFW_STAT_RX_PORT_64B_IX,\n\tFW_STAT_RX_PORT_65B_127B_IX,\n\tFW_STAT_RX_PORT_128B_255B_IX,\n\tFW_STAT_RX_PORT_256B_511B_IX,\n\tFW_STAT_RX_PORT_512B_1023B_IX,\n\tFW_STAT_RX_PORT_1024B_1518B_IX,\n\tFW_STAT_RX_PORT_1519B_MAX_IX,\n\tFW_STAT_RX_PORT_PAUSE_IX,\n\tFW_STAT_RX_PORT_PPP0_IX,\n\tFW_STAT_RX_PORT_PPP1_IX,\n\tFW_STAT_RX_PORT_PPP2_IX,\n\tFW_STAT_RX_PORT_PPP3_IX,\n\tFW_STAT_RX_PORT_PPP4_IX,\n\tFW_STAT_RX_PORT_PPP5_IX,\n\tFW_STAT_RX_PORT_PPP6_IX,\n\tFW_STAT_RX_PORT_PPP7_IX,\n\tFW_STAT_RX_PORT_LESS_64B_IX\n};\n\nstruct fw_port_stats_cmd {\n\t__be32 op_to_portid;\n\t__be32 retval_len16;\n\tunion fw_port_stats {\n\t\tstruct fw_port_stats_ctl {\n\t\t\t__u8 nstats_bg_bm;\n\t\t\t__u8 tx_ix;\n\t\t\t__be16 r6;\n\t\t\t__be32 r7;\n\t\t\t__be64 stat0;\n\t\t\t__be64 stat1;\n\t\t\t__be64 stat2;\n\t\t\t__be64 stat3;\n\t\t\t__be64 stat4;\n\t\t\t__be64 stat5;\n\t\t} ctl;\n\t\tstruct fw_port_stats_all {\n\t\t\t__be64 tx_bytes;\n\t\t\t__be64 tx_frames;\n\t\t\t__be64 tx_bcast;\n\t\t\t__be64 tx_mcast;\n\t\t\t__be64 tx_ucast;\n\t\t\t__be64 tx_error;\n\t\t\t__be64 tx_64b;\n\t\t\t__be64 tx_65b_127b;\n\t\t\t__be64 tx_128b_255b;\n\t\t\t__be64 tx_256b_511b;\n\t\t\t__be64 tx_512b_1023b;\n\t\t\t__be64 tx_1024b_1518b;\n\t\t\t__be64 tx_1519b_max;\n\t\t\t__be64 tx_drop;\n\t\t\t__be64 tx_pause;\n\t\t\t__be64 tx_ppp0;\n\t\t\t__be64 tx_ppp1;\n\t\t\t__be64 tx_ppp2;\n\t\t\t__be64 tx_ppp3;\n\t\t\t__be64 tx_ppp4;\n\t\t\t__be64 tx_ppp5;\n\t\t\t__be64 tx_ppp6;\n\t\t\t__be64 tx_ppp7;\n\t\t\t__be64 rx_bytes;\n\t\t\t__be64 rx_frames;\n\t\t\t__be64 rx_bcast;\n\t\t\t__be64 rx_mcast;\n\t\t\t__be64 rx_ucast;\n\t\t\t__be64 rx_mtu_error;\n\t\t\t__be64 rx_mtu_crc_error;\n\t\t\t__be64 rx_crc_error;\n\t\t\t__be64 rx_len_error;\n\t\t\t__be64 rx_sym_error;\n\t\t\t__be64 rx_64b;\n\t\t\t__be64 rx_65b_127b;\n\t\t\t__be64 rx_128b_255b;\n\t\t\t__be64 rx_256b_511b;\n\t\t\t__be64 rx_512b_1023b;\n\t\t\t__be64 rx_1024b_1518b;\n\t\t\t__be64 rx_1519b_max;\n\t\t\t__be64 rx_pause;\n\t\t\t__be64 rx_ppp0;\n\t\t\t__be64 rx_ppp1;\n\t\t\t__be64 rx_ppp2;\n\t\t\t__be64 rx_ppp3;\n\t\t\t__be64 rx_ppp4;\n\t\t\t__be64 rx_ppp5;\n\t\t\t__be64 rx_ppp6;\n\t\t\t__be64 rx_ppp7;\n\t\t\t__be64 rx_less_64b;\n\t\t\t__be64 rx_bg_drop;\n\t\t\t__be64 rx_bg_trunc;\n\t\t} all;\n\t} u;\n};\n\nstruct fw_rss_ind_tbl_cmd {\n\t__be32 op_to_viid;\n\t__be32 retval_len16;\n\t__be16 niqid;\n\t__be16 startidx;\n\t__be32 r3;\n\t__be32 iq0_to_iq2;\n\t__be32 iq3_to_iq5;\n\t__be32 iq6_to_iq8;\n\t__be32 iq9_to_iq11;\n\t__be32 iq12_to_iq14;\n\t__be32 iq15_to_iq17;\n\t__be32 iq18_to_iq20;\n\t__be32 iq21_to_iq23;\n\t__be32 iq24_to_iq26;\n\t__be32 iq27_to_iq29;\n\t__be32 iq30_iq31;\n\t__be32 r15_lo;\n};\n\n#define S_FW_RSS_IND_TBL_CMD_VIID\t0\n#define M_FW_RSS_IND_TBL_CMD_VIID\t0xfff\n#define V_FW_RSS_IND_TBL_CMD_VIID(x)\t((x) << S_FW_RSS_IND_TBL_CMD_VIID)\n#define G_FW_RSS_IND_TBL_CMD_VIID(x)\t\\\n\t(((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)\n\n#define S_FW_RSS_IND_TBL_CMD_IQ0\t20\n#define M_FW_RSS_IND_TBL_CMD_IQ0\t0x3ff\n#define V_FW_RSS_IND_TBL_CMD_IQ0(x)\t((x) << S_FW_RSS_IND_TBL_CMD_IQ0)\n#define G_FW_RSS_IND_TBL_CMD_IQ0(x)\t\\\n\t(((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)\n\n#define S_FW_RSS_IND_TBL_CMD_IQ1\t10\n#define M_FW_RSS_IND_TBL_CMD_IQ1\t0x3ff\n#define V_FW_RSS_IND_TBL_CMD_IQ1(x)\t((x) << S_FW_RSS_IND_TBL_CMD_IQ1)\n#define G_FW_RSS_IND_TBL_CMD_IQ1(x)\t\\\n\t(((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)\n\n#define S_FW_RSS_IND_TBL_CMD_IQ2\t0\n#define M_FW_RSS_IND_TBL_CMD_IQ2\t0x3ff\n#define V_FW_RSS_IND_TBL_CMD_IQ2(x)\t((x) << S_FW_RSS_IND_TBL_CMD_IQ2)\n#define G_FW_RSS_IND_TBL_CMD_IQ2(x)\t\\\n\t(((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)\n\nstruct fw_rss_vi_config_cmd {\n\t__be32 op_to_viid;\n\t__be32 retval_len16;\n\tunion fw_rss_vi_config {\n\t\tstruct fw_rss_vi_config_manual {\n\t\t\t__be64 r3;\n\t\t\t__be64 r4;\n\t\t\t__be64 r5;\n\t\t} manual;\n\t\tstruct fw_rss_vi_config_basicvirtual {\n\t\t\t__be32 r6;\n\t\t\t__be32 defaultq_to_udpen;\n\t\t\t__be64 r9;\n\t\t\t__be64 r10;\n\t\t} basicvirtual;\n\t} u;\n};\n\n#define S_FW_RSS_VI_CONFIG_CMD_VIID\t0\n#define M_FW_RSS_VI_CONFIG_CMD_VIID\t0xfff\n#define V_FW_RSS_VI_CONFIG_CMD_VIID(x)\t((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)\n#define G_FW_RSS_VI_CONFIG_CMD_VIID(x)\t\\\n\t(((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)\n\n#define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ\t\t16\n#define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ\t\t0x3ff\n#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x)\t\\\n\t((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)\n#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x)\t\\\n\t(((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \\\n\t M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)\n\n#define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN\t4\n#define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN\t0x1\n#define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x)\t\\\n\t((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)\n#define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x)\t\\\n\t(((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \\\n\t M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)\n#define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN\t\\\n\tV_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)\n\n#define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN\t3\n#define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN\t0x1\n#define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x)\t\\\n\t((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)\n#define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x)\t\\\n\t(((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \\\n\t M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)\n#define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN\t\\\n\tV_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)\n\n#define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN\t2\n#define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN\t0x1\n#define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x)\t\\\n\t((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)\n#define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x)\t\\\n\t(((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \\\n\t M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)\n#define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN\t\\\n\tV_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)\n\n#define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN\t1\n#define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN\t0x1\n#define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x)\t\\\n\t((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)\n#define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x)\t\\\n\t(((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \\\n\t M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)\n#define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN\t\\\n\tV_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)\n\n#define S_FW_RSS_VI_CONFIG_CMD_UDPEN\t0\n#define M_FW_RSS_VI_CONFIG_CMD_UDPEN\t0x1\n#define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x)\t((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)\n#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x)\t\\\n\t(((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)\n#define F_FW_RSS_VI_CONFIG_CMD_UDPEN\tV_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)\n\n/******************************************************************************\n * D E B U G C O M M A N D s\n ******************************************************/\n\nstruct fw_debug_cmd {\n\t__be32 op_type;\n\t__be32 len16_pkd;\n\tunion fw_debug {\n\t\tstruct fw_debug_assert {\n\t\t\t__be32 fcid;\n\t\t\t__be32 line;\n\t\t\t__be32 x;\n\t\t\t__be32 y;\n\t\t\t__u8 filename_0_7[8];\n\t\t\t__u8 filename_8_15[8];\n\t\t\t__be64 r3;\n\t\t} assert;\n\t\tstruct fw_debug_prt {\n\t\t\t__be16 dprtstridx;\n\t\t\t__be16 r3[3];\n\t\t\t__be32 dprtstrparam0;\n\t\t\t__be32 dprtstrparam1;\n\t\t\t__be32 dprtstrparam2;\n\t\t\t__be32 dprtstrparam3;\n\t\t} prt;\n\t} u;\n};\n\n#define S_FW_DEBUG_CMD_TYPE\t0\n#define M_FW_DEBUG_CMD_TYPE\t0xff\n#define V_FW_DEBUG_CMD_TYPE(x)\t((x) << S_FW_DEBUG_CMD_TYPE)\n#define G_FW_DEBUG_CMD_TYPE(x)\t\\\n\t(((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)\n\n/******************************************************************************\n * P C I E F W R E G I S T E R\n **************************************/\n\n/*\n * Register definitions for the PCIE_FW register which the firmware uses\n * to retain status across RESETs. This register should be considered\n * as a READ-ONLY register for Host Software and only to be used to\n * track firmware initialization/error state, etc.\n */\n#define S_PCIE_FW_ERR\t\t31\n#define M_PCIE_FW_ERR\t\t0x1\n#define V_PCIE_FW_ERR(x)\t((x) << S_PCIE_FW_ERR)\n#define G_PCIE_FW_ERR(x)\t(((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)\n#define F_PCIE_FW_ERR\t\tV_PCIE_FW_ERR(1U)\n\n#define S_PCIE_FW_INIT\t\t30\n#define M_PCIE_FW_INIT\t\t0x1\n#define V_PCIE_FW_INIT(x)\t((x) << S_PCIE_FW_INIT)\n#define G_PCIE_FW_INIT(x)\t(((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)\n#define F_PCIE_FW_INIT\t\tV_PCIE_FW_INIT(1U)\n\n#define S_PCIE_FW_HALT 29\n#define M_PCIE_FW_HALT 0x1\n#define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)\n#define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)\n#define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)\n\n#define S_PCIE_FW_EVAL\t\t24\n#define M_PCIE_FW_EVAL\t\t0x7\n#define V_PCIE_FW_EVAL(x)\t((x) << S_PCIE_FW_EVAL)\n#define G_PCIE_FW_EVAL(x)\t(((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)\n\n#define S_PCIE_FW_MASTER_VLD\t15\n#define M_PCIE_FW_MASTER_VLD\t0x1\n#define V_PCIE_FW_MASTER_VLD(x)\t((x) << S_PCIE_FW_MASTER_VLD)\n#define G_PCIE_FW_MASTER_VLD(x)\t\\\n\t(((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)\n#define F_PCIE_FW_MASTER_VLD\tV_PCIE_FW_MASTER_VLD(1U)\n\n#define S_PCIE_FW_MASTER\t12\n#define M_PCIE_FW_MASTER\t0x7\n#define V_PCIE_FW_MASTER(x)\t((x) << S_PCIE_FW_MASTER)\n#define G_PCIE_FW_MASTER(x)\t(((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)\n\n/******************************************************************************\n * B I N A R Y H E A D E R F O R M A T\n **********************************************/\n\n/*\n * firmware binary header format\n */\nstruct fw_hdr {\n\t__u8\tver;\n\t__u8\tchip;\t\t\t/* terminator chip family */\n\t__be16\tlen512;\t\t\t/* bin length in units of 512-bytes */\n\t__be32\tfw_ver;\t\t\t/* firmware version */\n\t__be32\ttp_microcode_ver;\t/* tcp processor microcode version */\n\t__u8\tintfver_nic;\n\t__u8\tintfver_vnic;\n\t__u8\tintfver_ofld;\n\t__u8\tintfver_ri;\n\t__u8\tintfver_iscsipdu;\n\t__u8\tintfver_iscsi;\n\t__u8\tintfver_fcoepdu;\n\t__u8\tintfver_fcoe;\n\t__u32\treserved2;\n\t__u32\treserved3;\n\t__u32\tmagic;\t\t\t/* runtime or bootstrap fw */\n\t__be32\tflags;\n\t__be32\treserved6[23];\n};\n\n#define S_FW_HDR_FW_VER_MAJOR\t24\n#define M_FW_HDR_FW_VER_MAJOR\t0xff\n#define V_FW_HDR_FW_VER_MAJOR(x) \\\n\t((x) << S_FW_HDR_FW_VER_MAJOR)\n#define G_FW_HDR_FW_VER_MAJOR(x) \\\n\t(((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)\n\n#define S_FW_HDR_FW_VER_MINOR\t16\n#define M_FW_HDR_FW_VER_MINOR\t0xff\n#define V_FW_HDR_FW_VER_MINOR(x) \\\n\t((x) << S_FW_HDR_FW_VER_MINOR)\n#define G_FW_HDR_FW_VER_MINOR(x) \\\n\t(((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)\n\n#define S_FW_HDR_FW_VER_MICRO\t8\n#define M_FW_HDR_FW_VER_MICRO\t0xff\n#define V_FW_HDR_FW_VER_MICRO(x) \\\n\t((x) << S_FW_HDR_FW_VER_MICRO)\n#define G_FW_HDR_FW_VER_MICRO(x) \\\n\t(((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)\n\n#define S_FW_HDR_FW_VER_BUILD\t0\n#define M_FW_HDR_FW_VER_BUILD\t0xff\n#define V_FW_HDR_FW_VER_BUILD(x) \\\n\t((x) << S_FW_HDR_FW_VER_BUILD)\n#define G_FW_HDR_FW_VER_BUILD(x) \\\n\t(((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)\n\n#endif /* _T4FW_INTERFACE_H_ */\n" }, { "path": "drivers/net/cxgbe/cxgbe.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _CXGBE_H_\n#define _CXGBE_H_\n\n#include \"common.h\"\n#include \"t4_regs.h\"\n\n#define CXGBE_MIN_RING_DESC_SIZE 1024 /* Min TX/RX descriptor ring size */\n#define CXGBE_MAX_RING_DESC_SIZE 4096 /* Max TX/RX descriptor ring size */\n\n#define CXGBE_DEFAULT_TX_DESC_SIZE 1024 /* Default TX ring size */\n#define CXGBE_DEFAULT_RX_DESC_SIZE 1024 /* Default RX ring size */\n\nint cxgbe_probe(struct adapter *adapter);\nint cxgbe_up(struct adapter *adap);\nint cxgbe_down(struct port_info *pi);\nvoid cxgbe_close(struct adapter *adapter);\nvoid cxgbe_stats_get(struct port_info *pi, struct port_stats *stats);\nvoid cxgbe_stats_reset(struct port_info *pi);\nint link_start(struct port_info *pi);\nvoid init_rspq(struct adapter *adap, struct sge_rspq *q, unsigned int us,\n\t unsigned int cnt, unsigned int size, unsigned int iqe_size);\nint setup_sge_fwevtq(struct adapter *adapter);\nvoid cfg_queues(struct rte_eth_dev *eth_dev);\nint cfg_queue_count(struct rte_eth_dev *eth_dev);\nint setup_rss(struct port_info *pi);\n\n#endif /* _CXGBE_H_ */\n" }, { "path": "drivers/net/cxgbe/cxgbe_compat.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _CXGBE_COMPAT_H_\n#define _CXGBE_COMPAT_H_\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#define dev_printf(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"rte_cxgbe_pmd: \" fmt, ## args)\n\n#define dev_err(x, args...) dev_printf(ERR, args)\n#define dev_info(x, args...) dev_printf(INFO, args)\n#define dev_warn(x, args...) dev_printf(WARNING, args)\n\n#ifdef RTE_LIBRTE_CXGBE_DEBUG\n#define dev_debug(x, args...) dev_printf(DEBUG, args)\n#else\n#define dev_debug(x, args...) do { } while (0)\n#endif\n\n#ifdef RTE_LIBRTE_CXGBE_DEBUG_REG\n#define CXGBE_DEBUG_REG(x, args...) dev_printf(DEBUG, \"REG:\" args)\n#else\n#define CXGBE_DEBUG_REG(x, args...) do { } while (0)\n#endif\n\n#ifdef RTE_LIBRTE_CXGBE_DEBUG_MBOX\n#define CXGBE_DEBUG_MBOX(x, args...) dev_printf(DEBUG, \"MBOX:\" args)\n#else\n#define CXGBE_DEBUG_MBOX(x, args...) do { } while (0)\n#endif\n\n#ifdef RTE_LIBRTE_CXGBE_DEBUG_TX\n#define CXGBE_DEBUG_TX(x, args...) dev_printf(DEBUG, \"TX:\" args)\n#else\n#define CXGBE_DEBUG_TX(x, args...) do { } while (0)\n#endif\n\n#ifdef RTE_LIBRTE_CXGBE_DEBUG_RX\n#define CXGBE_DEBUG_RX(x, args...) dev_printf(DEBUG, \"RX:\" args)\n#else\n#define CXGBE_DEBUG_RX(x, args...) do { } while (0)\n#endif\n\n#ifdef RTE_LIBRTE_CXGBE_DEBUG\n#define CXGBE_FUNC_TRACE() \\\n\tRTE_LOG(DEBUG, PMD, \"CXGBE trace: %s\\n\", __func__)\n#else\n#define CXGBE_FUNC_TRACE() do { } while (0)\n#endif\n\n#define pr_err(y, args...) dev_err(0, y, ##args)\n#define pr_warn(y, args...) dev_warn(0, y, ##args)\n#define pr_info(y, args...) dev_info(0, y, ##args)\n#define BUG() pr_err(\"BUG at %s:%d\", __func__, __LINE__)\n\n#define ASSERT(x) do {\\\n\tif (!(x)) \\\n\t\trte_panic(\"CXGBE: x\"); \\\n} while (0)\n#define BUG_ON(x) ASSERT(!(x))\n\n#ifndef WARN_ON\n#define WARN_ON(x) do { \\\n\tint ret = !!(x); \\\n\tif (unlikely(ret)) \\\n\t\tpr_warn(\"WARN_ON: \\\"\" #x \"\\\" at %s:%d\\n\", __func__, __LINE__); \\\n} while (0)\n#endif\n\n#define __iomem\n\n#ifndef BIT\n#define BIT(n) (1 << (n))\n#endif\n\n#define L1_CACHE_SHIFT 6\n#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)\n\n#define PAGE_SHIFT 12\n#define CXGBE_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))\n#define PTR_ALIGN(p, a) ((typeof(p))CXGBE_ALIGN((unsigned long)(p), (a)))\n\n#define VLAN_HLEN 4\n\n#define rmb() rte_rmb() /* dpdk rte provided rmb */\n#define wmb() rte_wmb() /* dpdk rte provided wmb */\n\ntypedef uint8_t u8;\ntypedef int8_t s8;\ntypedef uint16_t u16;\ntypedef uint32_t u32;\ntypedef int32_t s32;\ntypedef uint64_t u64;\ntypedef int bool;\ntypedef uint64_t dma_addr_t;\n\n#ifndef __le16\n#define __le16\tuint16_t\n#endif\n#ifndef __le32\n#define __le32\tuint32_t\n#endif\n#ifndef __le64\n#define __le64\tuint64_t\n#endif\n#ifndef __be16\n#define __be16\tuint16_t\n#endif\n#ifndef __be32\n#define __be32\tuint32_t\n#endif\n#ifndef __be64\n#define __be64\tuint64_t\n#endif\n#ifndef __u8\n#define __u8\tuint8_t\n#endif\n#ifndef __u16\n#define __u16\tuint16_t\n#endif\n#ifndef __u32\n#define __u32\tuint32_t\n#endif\n#ifndef __u64\n#define __u64\tuint64_t\n#endif\n\n#define FALSE\t0\n#define TRUE\t1\n#define false\t0\n#define true\t1\n\n#define min(a, b) RTE_MIN(a, b)\n#define max(a, b) RTE_MAX(a, b)\n\n/*\n * round up val _p to a power of 2 size _s\n */\n#define cxgbe_roundup(_p, _s) (((unsigned long)(_p) + (_s - 1)) & ~(_s - 1))\n\n#undef container_of\n#define container_of(ptr, type, member) ({ \\\n\t\ttypeof(((type *)0)->member)(*__mptr) = (ptr); \\\n\t\t(type *)((char *)__mptr - offsetof(type, member)); })\n\n#define ARRAY_SIZE(arr) RTE_DIM(arr)\n\n#define cpu_to_be16(o) rte_cpu_to_be_16(o)\n#define cpu_to_be32(o) rte_cpu_to_be_32(o)\n#define cpu_to_be64(o) rte_cpu_to_be_64(o)\n#define cpu_to_le32(o) rte_cpu_to_le_32(o)\n#define be16_to_cpu(o) rte_be_to_cpu_16(o)\n#define be32_to_cpu(o) rte_be_to_cpu_32(o)\n#define be64_to_cpu(o) rte_be_to_cpu_64(o)\n#define le32_to_cpu(o) rte_le_to_cpu_32(o)\n\n#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n#define DELAY(x) rte_delay_us(x)\n#define udelay(x) DELAY(x)\n#define msleep(x) DELAY(1000 * (x))\n#define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))\n\nstatic inline uint8_t hweight32(uint32_t word32)\n{\n\tuint32_t res = word32 - ((word32 >> 1) & 0x55555555);\n\n\tres = (res & 0x33333333) + ((res >> 2) & 0x33333333);\n\tres = (res + (res >> 4)) & 0x0F0F0F0F;\n\tres = res + (res >> 8);\n\treturn (res + (res >> 16)) & 0x000000FF;\n\n} /* weight32 */\n\n/**\n * cxgbe_fls - find last (most-significant) bit set\n * @x: the word to search\n *\n * This is defined the same way as ffs.\n * Note cxgbe_fls(0) = 0, cxgbe_fls(1) = 1, cxgbe_fls(0x80000000) = 32.\n */\nstatic inline int cxgbe_fls(int x)\n{\n\treturn x ? sizeof(x) * 8 - __builtin_clz(x) : 0;\n}\n\nstatic inline unsigned long ilog2(unsigned long n)\n{\n\tunsigned int e = 0;\n\n\twhile (n) {\n\t\tif (n & ~((1 << 8) - 1)) {\n\t\t\te += 8;\n\t\t\tn >>= 8;\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (n & ~((1 << 4) - 1)) {\n\t\t\te += 4;\n\t\t\tn >>= 4;\n\t\t}\n\n\t\tfor (;;) {\n\t\t\tn >>= 1;\n\t\t\tif (n == 0)\n\t\t\t\tbreak;\n\t\t\te++;\n\t\t}\n\t}\n\n\treturn e;\n}\n\nstatic inline void writel(unsigned int val, volatile void __iomem *addr)\n{\n\t*(volatile unsigned int *)addr = val;\n}\n\nstatic inline void writeq(u64 val, volatile void __iomem *addr)\n{\n\twritel(val, addr);\n\twritel(val >> 32, (void *)((uintptr_t)addr + 4));\n}\n\n#endif /* _CXGBE_COMPAT_H_ */\n" }, { "path": "drivers/net/cxgbe/cxgbe_ethdev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"cxgbe.h\"\n\n/*\n * Macros needed to support the PCI Device ID Table ...\n */\n#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \\\n\tstatic struct rte_pci_id cxgb4_pci_tbl[] = {\n#define CH_PCI_DEVICE_ID_FUNCTION 0x4\n\n#define PCI_VENDOR_ID_CHELSIO 0x1425\n\n#define CH_PCI_ID_TABLE_ENTRY(devid) \\\n\t\t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }\n\n#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \\\n\t\t{ .vendor_id = 0, } \\\n\t}\n\n/*\n *... and the PCI ID Table itself ...\n */\n#include \"t4_pci_id_tbl.h\"\n\nstatic uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t\t\t\tuint16_t nb_pkts)\n{\n\tstruct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;\n\tuint16_t pkts_sent, pkts_remain;\n\tuint16_t total_sent = 0;\n\tint ret = 0;\n\n\tCXGBE_DEBUG_TX(adapter, \"%s: txq = %p; tx_pkts = %p; nb_pkts = %d\\n\",\n\t\t __func__, txq, tx_pkts, nb_pkts);\n\n\tt4_os_lock(&txq->txq_lock);\n\t/* free up desc from already completed tx */\n\treclaim_completed_tx(&txq->q);\n\twhile (total_sent < nb_pkts) {\n\t\tpkts_remain = nb_pkts - total_sent;\n\n\t\tfor (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {\n\t\t\tret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent]);\n\t\t\tif (ret < 0)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (!pkts_sent)\n\t\t\tbreak;\n\t\ttotal_sent += pkts_sent;\n\t\t/* reclaim as much as possible */\n\t\treclaim_completed_tx(&txq->q);\n\t}\n\n\tt4_os_unlock(&txq->txq_lock);\n\treturn total_sent;\n}\n\nstatic uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\t\t\tuint16_t nb_pkts)\n{\n\tstruct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;\n\tunsigned int work_done;\n\n\tCXGBE_DEBUG_RX(adapter, \"%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\\n\",\n\t\t __func__, rxq->rspq.cntxt_id, nb_pkts);\n\n\tif (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))\n\t\tdev_err(adapter, \"error in cxgbe poll\\n\");\n\n\tCXGBE_DEBUG_RX(adapter, \"%s: work_done = %u\\n\", __func__, work_done);\n\treturn work_done;\n}\n\nstatic void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,\n\t\t\t struct rte_eth_dev_info *device_info)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\tint max_queues = adapter->sge.max_ethqsets / adapter->params.nports;\n\n\tdevice_info->min_rx_bufsize = 68; /* XXX: Smallest pkt size */\n\tdevice_info->max_rx_pktlen = 1500; /* XXX: For now we support mtu */\n\tdevice_info->max_rx_queues = max_queues;\n\tdevice_info->max_tx_queues = max_queues;\n\tdevice_info->max_mac_addrs = 1;\n\t/* XXX: For now we support one MAC/port */\n\tdevice_info->max_vfs = adapter->params.arch.vfcount;\n\tdevice_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */\n\n\tdevice_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |\n\t\t\t\t DEV_RX_OFFLOAD_IPV4_CKSUM |\n\t\t\t\t DEV_RX_OFFLOAD_UDP_CKSUM |\n\t\t\t\t DEV_RX_OFFLOAD_TCP_CKSUM;\n\n\tdevice_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |\n\t\t\t\t DEV_TX_OFFLOAD_IPV4_CKSUM |\n\t\t\t\t DEV_TX_OFFLOAD_UDP_CKSUM |\n\t\t\t\t DEV_TX_OFFLOAD_TCP_CKSUM |\n\t\t\t\t DEV_TX_OFFLOAD_TCP_TSO;\n\n\tdevice_info->reta_size = pi->rss_size;\n}\n\nstatic void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\n\tt4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,\n\t\t 1, -1, 1, -1, false);\n}\n\nstatic void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\n\tt4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,\n\t\t 0, -1, 1, -1, false);\n}\n\nstatic void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\n\t/* TODO: address filters ?? */\n\n\tt4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,\n\t\t -1, 1, 1, -1, false);\n}\n\nstatic void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\n\t/* TODO: address filters ?? */\n\n\tt4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,\n\t\t -1, 0, 1, -1, false);\n}\n\nstatic int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,\n\t\t\t\t __rte_unused int wait_to_complete)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\tstruct sge *s = &adapter->sge;\n\tstruct rte_eth_link *old_link = ð_dev->data->dev_link;\n\tunsigned int work_done, budget = 4;\n\n\tcxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);\n\tif (old_link->link_status == pi->link_cfg.link_ok)\n\t\treturn -1; /* link not changed */\n\n\teth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;\n\teth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;\n\teth_dev->data->dev_link.link_speed = pi->link_cfg.speed;\n\n\t/* link has changed */\n\treturn 0;\n}\n\nstatic int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev,\n\t\t\t\t uint16_t tx_queue_id);\nstatic int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev,\n\t\t\t\t uint16_t tx_queue_id);\nstatic void cxgbe_dev_tx_queue_release(void *q);\nstatic void cxgbe_dev_rx_queue_release(void *q);\n\n/*\n * Stop device.\n */\nstatic void cxgbe_dev_close(struct rte_eth_dev *eth_dev)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\tint i, dev_down = 0;\n\n\tCXGBE_FUNC_TRACE();\n\n\tif (!(adapter->flags & FULL_INIT_DONE))\n\t\treturn;\n\n\tcxgbe_down(pi);\n\n\t/*\n\t * We clear queues only if both tx and rx path of the port\n\t * have been disabled\n\t */\n\tt4_sge_eth_clear_queues(pi);\n\n\t/* See if all ports are down */\n\tfor_each_port(adapter, i) {\n\t\tpi = adap2pinfo(adapter, i);\n\t\t/*\n\t\t * Skip first port of the adapter since it will be closed\n\t\t * by DPDK\n\t\t */\n\t\tif (i == 0)\n\t\t\tcontinue;\n\t\tdev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;\n\t}\n\n\t/* If rest of the ports are stopped, then free up resources */\n\tif (dev_down == (adapter->params.nports - 1))\n\t\tcxgbe_close(adapter);\n}\n\n/* Start the device.\n * It returns 0 on success.\n */\nstatic int cxgbe_dev_start(struct rte_eth_dev *eth_dev)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\tint err = 0, i;\n\n\tCXGBE_FUNC_TRACE();\n\n\t/*\n\t * If we don't have a connection to the firmware there's nothing we\n\t * can do.\n\t */\n\tif (!(adapter->flags & FW_OK)) {\n\t\terr = -ENXIO;\n\t\tgoto out;\n\t}\n\n\tif (!(adapter->flags & FULL_INIT_DONE)) {\n\t\terr = cxgbe_up(adapter);\n\t\tif (err < 0)\n\t\t\tgoto out;\n\t}\n\n\terr = setup_rss(pi);\n\tif (err)\n\t\tgoto out;\n\n\tfor (i = 0; i < pi->n_tx_qsets; i++) {\n\t\terr = cxgbe_dev_tx_queue_start(eth_dev, i);\n\t\tif (err)\n\t\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < pi->n_rx_qsets; i++) {\n\t\terr = cxgbe_dev_rx_queue_start(eth_dev, i);\n\t\tif (err)\n\t\t\tgoto out;\n\t}\n\n\terr = link_start(pi);\n\tif (err)\n\t\tgoto out;\n\nout:\n\treturn err;\n}\n\n/*\n * Stop device: disable rx and tx functions to allow for reconfiguring.\n */\nstatic void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\n\tCXGBE_FUNC_TRACE();\n\n\tif (!(adapter->flags & FULL_INIT_DONE))\n\t\treturn;\n\n\tcxgbe_down(pi);\n\n\t/*\n\t * We clear queues only if both tx and rx path of the port\n\t * have been disabled\n\t */\n\tt4_sge_eth_clear_queues(pi);\n}\n\nstatic int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\tint err;\n\n\tCXGBE_FUNC_TRACE();\n\n\tif (!(adapter->flags & FW_QUEUE_BOUND)) {\n\t\terr = setup_sge_fwevtq(adapter);\n\t\tif (err)\n\t\t\treturn err;\n\t\tadapter->flags |= FW_QUEUE_BOUND;\n\t}\n\n\terr = cfg_queue_count(eth_dev);\n\tif (err)\n\t\treturn err;\n\n\treturn 0;\n}\n\nstatic int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev,\n\t\t\t\t uint16_t tx_queue_id)\n{\n\tstruct sge_eth_txq *txq = (struct sge_eth_txq *)\n\t\t\t\t (eth_dev->data->tx_queues[tx_queue_id]);\n\n\tdev_debug(NULL, \"%s: tx_queue_id = %d\\n\", __func__, tx_queue_id);\n\n\treturn t4_sge_eth_txq_start(txq);\n}\n\nstatic int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev,\n\t\t\t\t uint16_t tx_queue_id)\n{\n\tstruct sge_eth_txq *txq = (struct sge_eth_txq *)\n\t\t\t\t (eth_dev->data->tx_queues[tx_queue_id]);\n\n\tdev_debug(NULL, \"%s: tx_queue_id = %d\\n\", __func__, tx_queue_id);\n\n\treturn t4_sge_eth_txq_stop(txq);\n}\n\nstatic int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,\n\t\t\t\t uint16_t queue_idx,\tuint16_t nb_desc,\n\t\t\t\t unsigned int socket_id,\n\t\t\t\t const struct rte_eth_txconf *tx_conf)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\tstruct sge *s = &adapter->sge;\n\tstruct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];\n\tint err = 0;\n\tunsigned int temp_nb_desc;\n\n\tRTE_SET_USED(tx_conf);\n\n\tdev_debug(adapter, \"%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\\n\",\n\t\t __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,\n\t\t socket_id, pi->first_qset);\n\n\t/* Free up the existing queue */\n\tif (eth_dev->data->tx_queues[queue_idx]) {\n\t\tcxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);\n\t\teth_dev->data->tx_queues[queue_idx] = NULL;\n\t}\n\n\teth_dev->data->tx_queues[queue_idx] = (void *)txq;\n\n\t/* Sanity Checking\n\t *\n\t * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE\n\t */\n\ttemp_nb_desc = nb_desc;\n\tif (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {\n\t\tdev_warn(adapter, \"%s: number of descriptors must be >= %d. Using default [%d]\\n\",\n\t\t\t __func__, CXGBE_MIN_RING_DESC_SIZE,\n\t\t\t CXGBE_DEFAULT_TX_DESC_SIZE);\n\t\ttemp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;\n\t} else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {\n\t\tdev_err(adapter, \"%s: number of descriptors must be between %d and %d inclusive. Default [%d]\\n\",\n\t\t\t__func__, CXGBE_MIN_RING_DESC_SIZE,\n\t\t\tCXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);\n\t\treturn -(EINVAL);\n\t}\n\n\ttxq->q.size = temp_nb_desc;\n\n\terr = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,\n\t\t\t\t s->fw_evtq.cntxt_id, socket_id);\n\n\tdev_debug(adapter, \"%s: txq->q.cntxt_id= %d err = %d\\n\",\n\t\t __func__, txq->q.cntxt_id, err);\n\n\treturn err;\n}\n\nstatic void cxgbe_dev_tx_queue_release(void *q)\n{\n\tstruct sge_eth_txq *txq = (struct sge_eth_txq *)q;\n\n\tif (txq) {\n\t\tstruct port_info *pi = (struct port_info *)\n\t\t\t\t (txq->eth_dev->data->dev_private);\n\t\tstruct adapter *adap = pi->adapter;\n\n\t\tdev_debug(adapter, \"%s: pi->port_id = %d; tx_queue_id = %d\\n\",\n\t\t\t __func__, pi->port_id, txq->q.cntxt_id);\n\n\t\tt4_sge_eth_txq_release(adap, txq);\n\t}\n}\n\nstatic int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev,\n\t\t\t\t uint16_t rx_queue_id)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adap = pi->adapter;\n\tstruct sge_rspq *q;\n\n\tdev_debug(adapter, \"%s: pi->port_id = %d; rx_queue_id = %d\\n\",\n\t\t __func__, pi->port_id, rx_queue_id);\n\n\tq = eth_dev->data->rx_queues[rx_queue_id];\n\treturn t4_sge_eth_rxq_start(adap, q);\n}\n\nstatic int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev,\n\t\t\t\t uint16_t rx_queue_id)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adap = pi->adapter;\n\tstruct sge_rspq *q;\n\n\tdev_debug(adapter, \"%s: pi->port_id = %d; rx_queue_id = %d\\n\",\n\t\t __func__, pi->port_id, rx_queue_id);\n\n\tq = eth_dev->data->rx_queues[rx_queue_id];\n\treturn t4_sge_eth_rxq_stop(adap, q);\n}\n\nstatic int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,\n\t\t\t\t uint16_t queue_idx,\tuint16_t nb_desc,\n\t\t\t\t unsigned int socket_id,\n\t\t\t\t const struct rte_eth_rxconf *rx_conf,\n\t\t\t\t struct rte_mempool *mp)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\tstruct sge *s = &adapter->sge;\n\tstruct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];\n\tint err = 0;\n\tint msi_idx = 0;\n\tunsigned int temp_nb_desc;\n\n\tRTE_SET_USED(rx_conf);\n\n\tdev_debug(adapter, \"%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\\n\",\n\t\t __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,\n\t\t socket_id, mp);\n\n\t/* Free up the existing queue */\n\tif (eth_dev->data->rx_queues[queue_idx]) {\n\t\tcxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);\n\t\teth_dev->data->rx_queues[queue_idx] = NULL;\n\t}\n\n\teth_dev->data->rx_queues[queue_idx] = (void *)rxq;\n\n\t/* Sanity Checking\n\t *\n\t * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE\n\t */\n\ttemp_nb_desc = nb_desc;\n\tif (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {\n\t\tdev_warn(adapter, \"%s: number of descriptors must be >= %d. Using default [%d]\\n\",\n\t\t\t __func__, CXGBE_MIN_RING_DESC_SIZE,\n\t\t\t CXGBE_DEFAULT_RX_DESC_SIZE);\n\t\ttemp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;\n\t} else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {\n\t\tdev_err(adapter, \"%s: number of descriptors must be between %d and %d inclusive. Default [%d]\\n\",\n\t\t\t__func__, CXGBE_MIN_RING_DESC_SIZE,\n\t\t\tCXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);\n\t\treturn -(EINVAL);\n\t}\n\n\trxq->rspq.size = temp_nb_desc;\n\tif ((&rxq->fl) != NULL)\n\t\trxq->fl.size = temp_nb_desc;\n\n\terr = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,\n\t\t\t &rxq->fl, t4_ethrx_handler,\n\t\t\t t4_get_mps_bg_map(adapter, pi->tx_chan), mp,\n\t\t\t queue_idx, socket_id);\n\n\tdev_debug(adapter, \"%s: err = %d; port_id = %d; cntxt_id = %u\\n\",\n\t\t __func__, err, pi->port_id, rxq->rspq.cntxt_id);\n\treturn err;\n}\n\nstatic void cxgbe_dev_rx_queue_release(void *q)\n{\n\tstruct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;\n\tstruct sge_rspq *rq = &rxq->rspq;\n\n\tif (rq) {\n\t\tstruct port_info *pi = (struct port_info *)\n\t\t\t\t (rq->eth_dev->data->dev_private);\n\t\tstruct adapter *adap = pi->adapter;\n\n\t\tdev_debug(adapter, \"%s: pi->port_id = %d; rx_queue_id = %d\\n\",\n\t\t\t __func__, pi->port_id, rxq->rspq.cntxt_id);\n\n\t\tt4_sge_eth_rxq_release(adap, rxq);\n\t}\n}\n\n/*\n * Get port statistics.\n */\nstatic void cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,\n\t\t\t\tstruct rte_eth_stats *eth_stats)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\tstruct sge *s = &adapter->sge;\n\tstruct port_stats ps;\n\tunsigned int i;\n\n\tcxgbe_stats_get(pi, &ps);\n\n\t/* RX Stats */\n\teth_stats->ipackets = ps.rx_frames;\n\teth_stats->ibytes = ps.rx_octets;\n\teth_stats->imcasts = ps.rx_mcast_frames;\n\teth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +\n\t\t\t ps.rx_ovflow2 + ps.rx_ovflow3 +\n\t\t\t ps.rx_trunc0 + ps.rx_trunc1 +\n\t\t\t ps.rx_trunc2 + ps.rx_trunc3;\n\teth_stats->ibadcrc = ps.rx_fcs_err;\n\teth_stats->ibadlen = ps.rx_jabber + ps.rx_too_long + ps.rx_runt;\n\teth_stats->ierrors = ps.rx_symbol_err + eth_stats->ibadcrc +\n\t\t\t eth_stats->ibadlen + ps.rx_len_err +\n\t\t\t eth_stats->imissed;\n\teth_stats->rx_pause_xon = ps.rx_pause;\n\n\t/* TX Stats */\n\teth_stats->opackets = ps.tx_frames;\n\teth_stats->obytes = ps.tx_octets;\n\teth_stats->oerrors = ps.tx_error_frames;\n\teth_stats->tx_pause_xon = ps.tx_pause;\n\n\tfor (i = 0; i < pi->n_rx_qsets; i++) {\n\t\tstruct sge_eth_rxq *rxq =\n\t\t\t&s->ethrxq[pi->first_qset + i];\n\n\t\teth_stats->q_ipackets[i] = rxq->stats.pkts;\n\t\teth_stats->q_ibytes[i] = rxq->stats.rx_bytes;\n\t}\n\n\tfor (i = 0; i < pi->n_tx_qsets; i++) {\n\t\tstruct sge_eth_txq *txq =\n\t\t\t&s->ethtxq[pi->first_qset + i];\n\n\t\teth_stats->q_opackets[i] = txq->stats.pkts;\n\t\teth_stats->q_obytes[i] = txq->stats.tx_bytes;\n\t\teth_stats->q_errors[i] = txq->stats.mapping_err;\n\t}\n}\n\n/*\n * Reset port statistics.\n */\nstatic void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\tstruct sge *s = &adapter->sge;\n\tunsigned int i;\n\n\tcxgbe_stats_reset(pi);\n\tfor (i = 0; i < pi->n_rx_qsets; i++) {\n\t\tstruct sge_eth_rxq *rxq =\n\t\t\t&s->ethrxq[pi->first_qset + i];\n\n\t\trxq->stats.pkts = 0;\n\t\trxq->stats.rx_bytes = 0;\n\t}\n\tfor (i = 0; i < pi->n_tx_qsets; i++) {\n\t\tstruct sge_eth_txq *txq =\n\t\t\t&s->ethtxq[pi->first_qset + i];\n\n\t\ttxq->stats.pkts = 0;\n\t\ttxq->stats.tx_bytes = 0;\n\t\ttxq->stats.mapping_err = 0;\n\t}\n}\n\nstatic int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,\n\t\t\t struct rte_eth_fc_conf *fc_conf)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct link_config *lc = &pi->link_cfg;\n\tint rx_pause, tx_pause;\n\n\tfc_conf->autoneg = lc->fc & PAUSE_AUTONEG;\n\trx_pause = lc->fc & PAUSE_RX;\n\ttx_pause = lc->fc & PAUSE_TX;\n\n\tif (rx_pause && tx_pause)\n\t\tfc_conf->mode = RTE_FC_FULL;\n\telse if (rx_pause)\n\t\tfc_conf->mode = RTE_FC_RX_PAUSE;\n\telse if (tx_pause)\n\t\tfc_conf->mode = RTE_FC_TX_PAUSE;\n\telse\n\t\tfc_conf->mode = RTE_FC_NONE;\n\treturn 0;\n}\n\nstatic int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n\t\t\t struct rte_eth_fc_conf *fc_conf)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = pi->adapter;\n\tstruct link_config *lc = &pi->link_cfg;\n\n\tif (lc->supported & FW_PORT_CAP_ANEG) {\n\t\tif (fc_conf->autoneg)\n\t\t\tlc->requested_fc |= PAUSE_AUTONEG;\n\t\telse\n\t\t\tlc->requested_fc &= ~PAUSE_AUTONEG;\n\t}\n\n\tif (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||\n\t (fc_conf->mode & RTE_FC_RX_PAUSE))\n\t\tlc->requested_fc |= PAUSE_RX;\n\telse\n\t\tlc->requested_fc &= ~PAUSE_RX;\n\n\tif (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||\n\t (fc_conf->mode & RTE_FC_TX_PAUSE))\n\t\tlc->requested_fc |= PAUSE_TX;\n\telse\n\t\tlc->requested_fc &= ~PAUSE_TX;\n\n\treturn t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,\n\t\t\t &pi->link_cfg);\n}\n\nstatic struct eth_dev_ops cxgbe_eth_dev_ops = {\n\t.dev_start\t\t= cxgbe_dev_start,\n\t.dev_stop\t\t= cxgbe_dev_stop,\n\t.dev_close\t\t= cxgbe_dev_close,\n\t.promiscuous_enable\t= cxgbe_dev_promiscuous_enable,\n\t.promiscuous_disable\t= cxgbe_dev_promiscuous_disable,\n\t.allmulticast_enable\t= cxgbe_dev_allmulticast_enable,\n\t.allmulticast_disable\t= cxgbe_dev_allmulticast_disable,\n\t.dev_configure\t\t= cxgbe_dev_configure,\n\t.dev_infos_get\t\t= cxgbe_dev_info_get,\n\t.link_update\t\t= cxgbe_dev_link_update,\n\t.tx_queue_setup = cxgbe_dev_tx_queue_setup,\n\t.tx_queue_start\t\t= cxgbe_dev_tx_queue_start,\n\t.tx_queue_stop\t\t= cxgbe_dev_tx_queue_stop,\n\t.tx_queue_release\t= cxgbe_dev_tx_queue_release,\n\t.rx_queue_setup = cxgbe_dev_rx_queue_setup,\n\t.rx_queue_start\t\t= cxgbe_dev_rx_queue_start,\n\t.rx_queue_stop\t\t= cxgbe_dev_rx_queue_stop,\n\t.rx_queue_release\t= cxgbe_dev_rx_queue_release,\n\t.stats_get\t\t= cxgbe_dev_stats_get,\n\t.stats_reset\t\t= cxgbe_dev_stats_reset,\n\t.flow_ctrl_get\t\t= cxgbe_flow_ctrl_get,\n\t.flow_ctrl_set\t\t= cxgbe_flow_ctrl_set,\n};\n\n/*\n * Initialize driver\n * It returns 0 on success.\n */\nstatic int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)\n{\n\tstruct rte_pci_device *pci_dev;\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adapter = NULL;\n\tchar name[RTE_ETH_NAME_MAX_LEN];\n\tint err = 0;\n\n\tCXGBE_FUNC_TRACE();\n\n\teth_dev->dev_ops = &cxgbe_eth_dev_ops;\n\teth_dev->rx_pkt_burst = &cxgbe_recv_pkts;\n\teth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;\n\n\t/* for secondary processes, we don't initialise any further as primary\n\t * has already done this work.\n\t */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn 0;\n\n\tpci_dev = eth_dev->pci_dev;\n\tsnprintf(name, sizeof(name), \"cxgbeadapter%d\", eth_dev->data->port_id);\n\tadapter = rte_zmalloc(name, sizeof(*adapter), 0);\n\tif (!adapter)\n\t\treturn -1;\n\n\tadapter->use_unpacked_mode = 1;\n\tadapter->regs = (void *)pci_dev->mem_resource[0].addr;\n\tif (!adapter->regs) {\n\t\tdev_err(adapter, \"%s: cannot map device registers\\n\", __func__);\n\t\terr = -ENOMEM;\n\t\tgoto out_free_adapter;\n\t}\n\tadapter->pdev = pci_dev;\n\tadapter->eth_dev = eth_dev;\n\tpi->adapter = adapter;\n\n\terr = cxgbe_probe(adapter);\n\tif (err)\n\t\tdev_err(adapter, \"%s: cxgbe probe failed with err %d\\n\",\n\t\t\t__func__, err);\n\nout_free_adapter:\n\treturn err;\n}\n\nstatic struct eth_driver rte_cxgbe_pmd = {\n\t{\n\t\t.name = \"rte_cxgbe_pmd\",\n\t\t.id_table = cxgb4_pci_tbl,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,\n\t},\n\t.eth_dev_init = eth_cxgbe_dev_init,\n\t.dev_private_size = sizeof(struct port_info),\n};\n\n/*\n * Driver initialization routine.\n * Invoked once at EAL init time.\n * Register itself as the [Poll Mode] Driver of PCI CXGBE devices.\n */\nstatic int rte_cxgbe_pmd_init(const char *name __rte_unused,\n\t\t\t const char *params __rte_unused)\n{\n\tCXGBE_FUNC_TRACE();\n\n\trte_eth_driver_register(&rte_cxgbe_pmd);\n\treturn 0;\n}\n\nstatic struct rte_driver rte_cxgbe_driver = {\n\t.name = \"cxgbe_driver\",\n\t.type = PMD_PDEV,\n\t.init = rte_cxgbe_pmd_init,\n};\n\nPMD_REGISTER_DRIVER(rte_cxgbe_driver);\n" }, { "path": "drivers/net/cxgbe/cxgbe_main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"common.h\"\n#include \"t4_regs.h\"\n#include \"t4_msg.h\"\n#include \"cxgbe.h\"\n\n/*\n * Response queue handler for the FW event queue.\n */\nstatic int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,\n\t\t\t __rte_unused const struct pkt_gl *gl)\n{\n\tu8 opcode = ((const struct rss_header *)rsp)->opcode;\n\n\trsp++; /* skip RSS header */\n\n\t/*\n\t * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.\n\t */\n\tif (unlikely(opcode == CPL_FW4_MSG &&\n\t\t ((const struct cpl_fw4_msg *)rsp)->type ==\n\t\t FW_TYPE_RSSCPL)) {\n\t\trsp++;\n\t\topcode = ((const struct rss_header *)rsp)->opcode;\n\t\trsp++;\n\t\tif (opcode != CPL_SGE_EGR_UPDATE) {\n\t\t\tdev_err(q->adapter, \"unexpected FW4/CPL %#x on FW event queue\\n\",\n\t\t\t\topcode);\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\tif (likely(opcode == CPL_SGE_EGR_UPDATE)) {\n\t\t/* do nothing */\n\t} else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {\n\t\tconst struct cpl_fw6_msg *msg = (const void *)rsp;\n\n\t\tt4_handle_fw_rpl(q->adapter, msg->data);\n\t} else {\n\t\tdev_err(adapter, \"unexpected CPL %#x on FW event queue\\n\",\n\t\t\topcode);\n\t}\nout:\n\treturn 0;\n}\n\nint setup_sge_fwevtq(struct adapter *adapter)\n{\n\tstruct sge *s = &adapter->sge;\n\tint err = 0;\n\tint msi_idx = 0;\n\n\terr = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,\n\t\t\t msi_idx, NULL, fwevtq_handler, -1, NULL, 0,\n\t\t\t rte_socket_id());\n\treturn err;\n}\n\nstatic int closest_timer(const struct sge *s, int time)\n{\n\tunsigned int i, match = 0;\n\tint delta, min_delta = INT_MAX;\n\n\tfor (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {\n\t\tdelta = time - s->timer_val[i];\n\t\tif (delta < 0)\n\t\t\tdelta = -delta;\n\t\tif (delta < min_delta) {\n\t\t\tmin_delta = delta;\n\t\t\tmatch = i;\n\t\t}\n\t}\n\treturn match;\n}\n\nstatic int closest_thres(const struct sge *s, int thres)\n{\n\tunsigned int i, match = 0;\n\tint delta, min_delta = INT_MAX;\n\n\tfor (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {\n\t\tdelta = thres - s->counter_val[i];\n\t\tif (delta < 0)\n\t\t\tdelta = -delta;\n\t\tif (delta < min_delta) {\n\t\t\tmin_delta = delta;\n\t\t\tmatch = i;\n\t\t}\n\t}\n\treturn match;\n}\n\n/**\n * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters\n * @q: the Rx queue\n * @us: the hold-off time in us, or 0 to disable timer\n * @cnt: the hold-off packet count, or 0 to disable counter\n *\n * Sets an Rx queue's interrupt hold-off time and packet count. At least\n * one of the two needs to be enabled for the queue to generate interrupts.\n */\nint cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,\n\t\t\t unsigned int cnt)\n{\n\tstruct adapter *adap = q->adapter;\n\tunsigned int timer_val;\n\n\tif (cnt) {\n\t\tint err;\n\t\tu32 v, new_idx;\n\n\t\tnew_idx = closest_thres(&adap->sge, cnt);\n\t\tif (q->desc && q->pktcnt_idx != new_idx) {\n\t\t\t/* the queue has already been created, update it */\n\t\t\tv = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |\n\t\t\t V_FW_PARAMS_PARAM_X(\n\t\t\t FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |\n\t\t\t V_FW_PARAMS_PARAM_YZ(q->cntxt_id);\n\t\t\terr = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,\n\t\t\t\t\t &v, &new_idx);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t}\n\t\tq->pktcnt_idx = new_idx;\n\t}\n\n\ttimer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :\n\t\t\t\tclosest_timer(&adap->sge, us);\n\n\tif ((us | cnt) == 0)\n\t\tq->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);\n\telse\n\t\tq->intr_params = V_QINTR_TIMER_IDX(timer_val) |\n\t\t\t\t V_QINTR_CNT_EN(cnt > 0);\n\treturn 0;\n}\n\nstatic inline bool is_x_1g_port(const struct link_config *lc)\n{\n\treturn ((lc->supported & FW_PORT_CAP_SPEED_1G) != 0);\n}\n\nstatic inline bool is_x_10g_port(const struct link_config *lc)\n{\n\treturn ((lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||\n\t\t(lc->supported & FW_PORT_CAP_SPEED_40G) != 0 ||\n\t\t(lc->supported & FW_PORT_CAP_SPEED_100G) != 0);\n}\n\ninline void init_rspq(struct adapter *adap, struct sge_rspq *q,\n\t\t unsigned int us, unsigned int cnt,\n\t\t unsigned int size, unsigned int iqe_size)\n{\n\tq->adapter = adap;\n\tcxgb4_set_rspq_intr_params(q, us, cnt);\n\tq->iqe_len = iqe_size;\n\tq->size = size;\n}\n\nint cfg_queue_count(struct rte_eth_dev *eth_dev)\n{\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adap = pi->adapter;\n\tstruct sge *s = &adap->sge;\n\tunsigned int max_queues = s->max_ethqsets / adap->params.nports;\n\n\tif ((eth_dev->data->nb_rx_queues < 1) ||\n\t (eth_dev->data->nb_tx_queues < 1))\n\t\treturn -EINVAL;\n\n\tif ((eth_dev->data->nb_rx_queues > max_queues) ||\n\t (eth_dev->data->nb_tx_queues > max_queues))\n\t\treturn -EINVAL;\n\n\tif (eth_dev->data->nb_rx_queues > pi->rss_size)\n\t\treturn -EINVAL;\n\n\t/* We must configure RSS, since config has changed*/\n\tpi->flags &= ~PORT_RSS_DONE;\n\n\tpi->n_rx_qsets = eth_dev->data->nb_rx_queues;\n\tpi->n_tx_qsets = eth_dev->data->nb_tx_queues;\n\n\treturn 0;\n}\n\nvoid cfg_queues(struct rte_eth_dev *eth_dev)\n{\n\tstruct rte_config *config = rte_eal_get_configuration();\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tstruct adapter *adap = pi->adapter;\n\tstruct sge *s = &adap->sge;\n\tunsigned int i, nb_ports = 0, qidx = 0;\n\tunsigned int q_per_port = 0;\n\n\tif (!(adap->flags & CFG_QUEUES)) {\n\t\tfor_each_port(adap, i) {\n\t\t\tstruct port_info *tpi = adap2pinfo(adap, i);\n\n\t\t\tnb_ports += (is_x_10g_port(&tpi->link_cfg)) ||\n\t\t\t\t is_x_1g_port(&tpi->link_cfg) ? 1 : 0;\n\t\t}\n\n\t\t/*\n\t\t * We default up to # of cores queues per 1G/10G port.\n\t\t */\n\t\tif (nb_ports)\n\t\t\tq_per_port = (MAX_ETH_QSETS -\n\t\t\t\t (adap->params.nports - nb_ports)) /\n\t\t\t\t nb_ports;\n\n\t\tif (q_per_port > config->lcore_count)\n\t\t\tq_per_port = config->lcore_count;\n\n\t\tfor_each_port(adap, i) {\n\t\t\tstruct port_info *pi = adap2pinfo(adap, i);\n\n\t\t\tpi->first_qset = qidx;\n\n\t\t\t/* Initially n_rx_qsets == n_tx_qsets */\n\t\t\tpi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||\n\t\t\t\t\t is_x_1g_port(&pi->link_cfg)) ?\n\t\t\t\t\t q_per_port : 1;\n\t\t\tpi->n_tx_qsets = pi->n_rx_qsets;\n\n\t\t\tif (pi->n_rx_qsets > pi->rss_size)\n\t\t\t\tpi->n_rx_qsets = pi->rss_size;\n\n\t\t\tqidx += pi->n_rx_qsets;\n\t\t}\n\n\t\ts->max_ethqsets = qidx;\n\n\t\tfor (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {\n\t\t\tstruct sge_eth_rxq *r = &s->ethrxq[i];\n\n\t\t\tinit_rspq(adap, &r->rspq, 0, 0, 1024, 64);\n\t\t\tr->usembufs = 1;\n\t\t\tr->fl.size = (r->usembufs ? 1024 : 72);\n\t\t}\n\n\t\tfor (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)\n\t\t\ts->ethtxq[i].q.size = 1024;\n\n\t\tinit_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);\n\t\tadap->flags |= CFG_QUEUES;\n\t}\n}\n\nvoid cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)\n{\n\tt4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,\n\t\t\t\t &pi->stats_base);\n}\n\nvoid cxgbe_stats_reset(struct port_info *pi)\n{\n\tt4_clr_port_stats(pi->adapter, pi->tx_chan);\n}\n\nstatic void setup_memwin(struct adapter *adap)\n{\n\tu32 mem_win0_base;\n\n\t/* For T5, only relative offset inside the PCIe BAR is passed */\n\tmem_win0_base = MEMWIN0_BASE;\n\n\t/*\n\t * Set up memory window for accessing adapter memory ranges. (Read\n\t * back MA register to ensure that changes propagate before we attempt\n\t * to use the new values.)\n\t */\n\tt4_write_reg(adap,\n\t\t PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,\n\t\t\t\t\t MEMWIN_NIC),\n\t\t mem_win0_base | V_BIR(0) |\n\t\t V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));\n\tt4_read_reg(adap,\n\t\t PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,\n\t\t\t\t\tMEMWIN_NIC));\n}\n\nstatic int init_rss(struct adapter *adap)\n{\n\tunsigned int i;\n\tint err;\n\n\terr = t4_init_rss_mode(adap, adap->mbox);\n\tif (err)\n\t\treturn err;\n\n\tfor_each_port(adap, i) {\n\t\tstruct port_info *pi = adap2pinfo(adap, i);\n\n\t\tpi->rss = rte_zmalloc(NULL, pi->rss_size, 0);\n\t\tif (!pi->rss)\n\t\t\treturn -ENOMEM;\n\t}\n\treturn 0;\n}\n\nstatic void print_port_info(struct adapter *adap)\n{\n\tint i;\n\tchar buf[80];\n\tstruct rte_pci_addr *loc = &adap->pdev->addr;\n\n\tfor_each_port(adap, i) {\n\t\tconst struct port_info *pi = &adap->port[i];\n\t\tchar *bufp = buf;\n\n\t\tif (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)\n\t\t\tbufp += sprintf(bufp, \"100/\");\n\t\tif (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)\n\t\t\tbufp += sprintf(bufp, \"1000/\");\n\t\tif (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)\n\t\t\tbufp += sprintf(bufp, \"10G/\");\n\t\tif (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)\n\t\t\tbufp += sprintf(bufp, \"40G/\");\n\t\tif (bufp != buf)\n\t\t\t--bufp;\n\t\tsprintf(bufp, \"BASE-%s\",\n\t\t\tt4_get_port_type_description(\n\t\t\t\t\t(enum fw_port_type)pi->port_type));\n\n\t\tdev_info(adap,\n\t\t\t \" \" PCI_PRI_FMT \" Chelsio rev %d %s %s\\n\",\n\t\t\t loc->domain, loc->bus, loc->devid, loc->function,\n\t\t\t CHELSIO_CHIP_RELEASE(adap->params.chip), buf,\n\t\t\t (adap->flags & USING_MSIX) ? \" MSI-X\" :\n\t\t\t (adap->flags & USING_MSI) ? \" MSI\" : \"\");\n\t}\n}\n\n/*\n * Tweak configuration based on system architecture, etc. Most of these have\n * defaults assigned to them by Firmware Configuration Files (if we're using\n * them) but need to be explicitly set if we're using hard-coded\n * initialization. So these are essentially common tweaks/settings for\n * Configuration Files and hard-coded initialization ...\n */\nstatic int adap_init0_tweaks(struct adapter *adapter)\n{\n\tu8 rx_dma_offset;\n\n\t/*\n\t * Fix up various Host-Dependent Parameters like Page Size, Cache\n\t * Line Size, etc. The firmware default is for a 4KB Page Size and\n\t * 64B Cache Line Size ...\n\t */\n\tt4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,\n\t\t\t\t T5_LAST_REV);\n\n\t/*\n\t * Keep the chip default offset to deliver Ingress packets into our\n\t * DMA buffers to zero\n\t */\n\trx_dma_offset = 0;\n\tt4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),\n\t\t\t V_PKTSHIFT(rx_dma_offset));\n\n\t/*\n\t * Don't include the \"IP Pseudo Header\" in CPL_RX_PKT checksums: Linux\n\t * adds the pseudo header itself.\n\t */\n\tt4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,\n\t\t\t F_CSUM_HAS_PSEUDO_HDR, 0);\n\n\treturn 0;\n}\n\n/*\n * Attempt to initialize the adapter via a Firmware Configuration File.\n */\nstatic int adap_init0_config(struct adapter *adapter, int reset)\n{\n\tstruct fw_caps_config_cmd caps_cmd;\n\tunsigned long mtype = 0, maddr = 0;\n\tu32 finiver, finicsum, cfcsum;\n\tint ret;\n\tint config_issued = 0;\n\tint cfg_addr;\n\tchar config_name[20];\n\n\t/*\n\t * Reset device if necessary.\n\t */\n\tif (reset) {\n\t\tret = t4_fw_reset(adapter, adapter->mbox,\n\t\t\t\t F_PIORSTMODE | F_PIORST);\n\t\tif (ret < 0) {\n\t\t\tdev_warn(adapter, \"Firmware reset failed, error %d\\n\",\n\t\t\t\t -ret);\n\t\t\tgoto bye;\n\t\t}\n\t}\n\n\tcfg_addr = t4_flash_cfg_addr(adapter);\n\tif (cfg_addr < 0) {\n\t\tret = cfg_addr;\n\t\tdev_warn(adapter, \"Finding address for firmware config file in flash failed, error %d\\n\",\n\t\t\t -ret);\n\t\tgoto bye;\n\t}\n\n\tstrcpy(config_name, \"On Flash\");\n\tmtype = FW_MEMTYPE_CF_FLASH;\n\tmaddr = cfg_addr;\n\n\t/*\n\t * Issue a Capability Configuration command to the firmware to get it\n\t * to parse the Configuration File. We don't use t4_fw_config_file()\n\t * because we want the ability to modify various features after we've\n\t * processed the configuration file ...\n\t */\n\tmemset(&caps_cmd, 0, sizeof(caps_cmd));\n\tcaps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |\n\t\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_READ);\n\tcaps_cmd.cfvalid_to_len16 =\n\t\tcpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |\n\t\t\t V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |\n\t\t\t V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |\n\t\t\t FW_LEN16(caps_cmd));\n\tret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),\n\t\t\t &caps_cmd);\n\t/*\n\t * If the CAPS_CONFIG failed with an ENOENT (for a Firmware\n\t * Configuration File in FLASH), our last gasp effort is to use the\n\t * Firmware Configuration File which is embedded in the firmware. A\n\t * very few early versions of the firmware didn't have one embedded\n\t * but we can ignore those.\n\t */\n\tif (ret == -ENOENT) {\n\t\tdev_info(adapter, \"%s: Going for embedded config in firmware..\\n\",\n\t\t\t __func__);\n\n\t\tmemset(&caps_cmd, 0, sizeof(caps_cmd));\n\t\tcaps_cmd.op_to_write =\n\t\t\tcpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |\n\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_READ);\n\t\tcaps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));\n\t\tret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,\n\t\t\t\t sizeof(caps_cmd), &caps_cmd);\n\t\tstrcpy(config_name, \"Firmware Default\");\n\t}\n\n\tconfig_issued = 1;\n\tif (ret < 0)\n\t\tgoto bye;\n\n\tfiniver = be32_to_cpu(caps_cmd.finiver);\n\tfinicsum = be32_to_cpu(caps_cmd.finicsum);\n\tcfcsum = be32_to_cpu(caps_cmd.cfcsum);\n\tif (finicsum != cfcsum)\n\t\tdev_warn(adapter, \"Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\\n\",\n\t\t\t finicsum, cfcsum);\n\n\t/*\n\t * If we're a pure NIC driver then disable all offloading facilities.\n\t * This will allow the firmware to optimize aspects of the hardware\n\t * configuration which will result in improved performance.\n\t */\n\tcaps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |\n\t\t\t\t\t FW_CAPS_CONFIG_NIC_ETHOFLD));\n\tcaps_cmd.toecaps = 0;\n\tcaps_cmd.iscsicaps = 0;\n\tcaps_cmd.rdmacaps = 0;\n\tcaps_cmd.fcoecaps = 0;\n\n\t/*\n\t * And now tell the firmware to use the configuration we just loaded.\n\t */\n\tcaps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |\n\t\t\t\t\t F_FW_CMD_REQUEST | F_FW_CMD_WRITE);\n\tcaps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));\n\tret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),\n\t\t\t NULL);\n\tif (ret < 0) {\n\t\tdev_warn(adapter, \"Unable to finalize Firmware Capabilities %d\\n\",\n\t\t\t -ret);\n\t\tgoto bye;\n\t}\n\n\t/*\n\t * Tweak configuration based on system architecture, etc.\n\t */\n\tret = adap_init0_tweaks(adapter);\n\tif (ret < 0) {\n\t\tdev_warn(adapter, \"Unable to do init0-tweaks %d\\n\", -ret);\n\t\tgoto bye;\n\t}\n\n\t/*\n\t * And finally tell the firmware to initialize itself using the\n\t * parameters from the Configuration File.\n\t */\n\tret = t4_fw_initialize(adapter, adapter->mbox);\n\tif (ret < 0) {\n\t\tdev_warn(adapter, \"Initializing Firmware failed, error %d\\n\",\n\t\t\t -ret);\n\t\tgoto bye;\n\t}\n\n\t/*\n\t * Return successfully and note that we're operating with parameters\n\t * not supplied by the driver, rather than from hard-wired\n\t * initialization constants burried in the driver.\n\t */\n\tdev_info(adapter,\n\t\t \"Successfully configured using Firmware Configuration File \\\"%s\\\", version %#x, computed checksum %#x\\n\",\n\t\t config_name, finiver, cfcsum);\n\n\treturn 0;\n\n\t/*\n\t * Something bad happened. Return the error ... (If the \"error\"\n\t * is that there's no Configuration File on the adapter we don't\n\t * want to issue a warning since this is fairly common.)\n\t */\nbye:\n\tif (config_issued && ret != -ENOENT)\n\t\tdev_warn(adapter, \"\\\"%s\\\" configuration file error %d\\n\",\n\t\t\t config_name, -ret);\n\n\tdev_debug(adapter, \"%s: returning ret = %d ..\\n\", __func__, ret);\n\treturn ret;\n}\n\nstatic int adap_init0(struct adapter *adap)\n{\n\tint ret = 0;\n\tu32 v, port_vec;\n\tenum dev_state state;\n\tu32 params[7], val[7];\n\tint reset = 1;\n\tint mbox = adap->mbox;\n\n\t/*\n\t * Contact FW, advertising Master capability.\n\t */\n\tret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);\n\tif (ret < 0) {\n\t\tdev_err(adap, \"%s: could not connect to FW, error %d\\n\",\n\t\t\t__func__, -ret);\n\t\tgoto bye;\n\t}\n\n\tCXGBE_DEBUG_MBOX(adap, \"%s: adap->mbox = %d; ret = %d\\n\", __func__,\n\t\t\t adap->mbox, ret);\n\n\tif (ret == mbox)\n\t\tadap->flags |= MASTER_PF;\n\n\tif (state == DEV_STATE_INIT) {\n\t\t/*\n\t\t * Force halt and reset FW because a previous instance may have\n\t\t * exited abnormally without properly shutting down\n\t\t */\n\t\tret = t4_fw_halt(adap, adap->mbox, reset);\n\t\tif (ret < 0) {\n\t\t\tdev_err(adap, \"Failed to halt. Exit.\\n\");\n\t\t\tgoto bye;\n\t\t}\n\n\t\tret = t4_fw_restart(adap, adap->mbox, reset);\n\t\tif (ret < 0) {\n\t\t\tdev_err(adap, \"Failed to restart. Exit.\\n\");\n\t\t\tgoto bye;\n\t\t}\n\t\tstate = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);\n\t}\n\n\tt4_get_fw_version(adap, &adap->params.fw_vers);\n\tt4_get_tp_version(adap, &adap->params.tp_vers);\n\n\tdev_info(adap, \"fw: %u.%u.%u.%u, TP: %u.%u.%u.%u\\n\",\n\t\t G_FW_HDR_FW_VER_MAJOR(adap->params.fw_vers),\n\t\t G_FW_HDR_FW_VER_MINOR(adap->params.fw_vers),\n\t\t G_FW_HDR_FW_VER_MICRO(adap->params.fw_vers),\n\t\t G_FW_HDR_FW_VER_BUILD(adap->params.fw_vers),\n\t\t G_FW_HDR_FW_VER_MAJOR(adap->params.tp_vers),\n\t\t G_FW_HDR_FW_VER_MINOR(adap->params.tp_vers),\n\t\t G_FW_HDR_FW_VER_MICRO(adap->params.tp_vers),\n\t\t G_FW_HDR_FW_VER_BUILD(adap->params.tp_vers));\n\n\tret = t4_get_core_clock(adap, &adap->params.vpd);\n\tif (ret < 0) {\n\t\tdev_err(adap, \"%s: could not get core clock, error %d\\n\",\n\t\t\t__func__, -ret);\n\t\tgoto bye;\n\t}\n\n\t/*\n\t * Find out what ports are available to us. Note that we need to do\n\t * this before calling adap_init0_no_config() since it needs nports\n\t * and portvec ...\n\t */\n\tv = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |\n\t V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);\n\tret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);\n\tif (ret < 0) {\n\t\tdev_err(adap, \"%s: failure in t4_queury_params; error = %d\\n\",\n\t\t\t__func__, ret);\n\t\tgoto bye;\n\t}\n\n\tadap->params.nports = hweight32(port_vec);\n\tadap->params.portvec = port_vec;\n\n\tdev_debug(adap, \"%s: adap->params.nports = %u\\n\", __func__,\n\t\t adap->params.nports);\n\n\t/*\n\t * If the firmware is initialized already (and we're not forcing a\n\t * master initialization), note that we're living with existing\n\t * adapter parameters. Otherwise, it's time to try initializing the\n\t * adapter ...\n\t */\n\tif (state == DEV_STATE_INIT) {\n\t\tdev_info(adap, \"Coming up as %s: Adapter already initialized\\n\",\n\t\t\t adap->flags & MASTER_PF ? \"MASTER\" : \"SLAVE\");\n\t} else {\n\t\tdev_info(adap, \"Coming up as MASTER: Initializing adapter\\n\");\n\n\t\tret = adap_init0_config(adap, reset);\n\t\tif (ret == -ENOENT) {\n\t\t\tdev_err(adap,\n\t\t\t\t\"No Configuration File present on adapter. Using hard-wired configuration parameters.\\n\");\n\t\t\tgoto bye;\n\t\t}\n\t}\n\tif (ret < 0) {\n\t\tdev_err(adap, \"could not initialize adapter, error %d\\n\", -ret);\n\t\tgoto bye;\n\t}\n\n\t/*\n\t * Give the SGE code a chance to pull in anything that it needs ...\n\t * Note that this must be called after we retrieve our VPD parameters\n\t * in order to know how to convert core ticks to seconds, etc.\n\t */\n\tret = t4_sge_init(adap);\n\tif (ret < 0) {\n\t\tdev_err(adap, \"t4_sge_init failed with error %d\\n\",\n\t\t\t-ret);\n\t\tgoto bye;\n\t}\n\n\t/*\n\t * Grab some of our basic fundamental operating parameters.\n\t */\n#define FW_PARAM_DEV(param) \\\n\t(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \\\n\t V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))\n\n#define FW_PARAM_PFVF(param) \\\n\t(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \\\n\t V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \\\n\t V_FW_PARAMS_PARAM_Y(0) | \\\n\t V_FW_PARAMS_PARAM_Z(0))\n\n\t/* If we're running on newer firmware, let it know that we're\n\t * prepared to deal with encapsulated CPL messages. Older\n\t * firmware won't understand this and we'll just get\n\t * unencapsulated messages ...\n\t */\n\tparams[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);\n\tval[0] = 1;\n\t(void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);\n\n\t/*\n\t * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL\n\t * capability. Earlier versions of the firmware didn't have the\n\t * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no\n\t * permission to use ULPTX MEMWRITE DSGL.\n\t */\n\tif (is_t4(adap->params.chip)) {\n\t\tadap->params.ulptx_memwrite_dsgl = false;\n\t} else {\n\t\tparams[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);\n\t\tret = t4_query_params(adap, adap->mbox, adap->pf, 0,\n\t\t\t\t 1, params, val);\n\t\tadap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);\n\t}\n\n\t/*\n\t * The MTU/MSS Table is initialized by now, so load their values. If\n\t * we're initializing the adapter, then we'll make any modifications\n\t * we want to the MTU/MSS Table and also initialize the congestion\n\t * parameters.\n\t */\n\tt4_read_mtu_tbl(adap, adap->params.mtus, NULL);\n\tif (state != DEV_STATE_INIT) {\n\t\tint i;\n\n\t\t/*\n\t\t * The default MTU Table contains values 1492 and 1500.\n\t\t * However, for TCP, it's better to have two values which are\n\t\t * a multiple of 8 +/- 4 bytes apart near this popular MTU.\n\t\t * This allows us to have a TCP Data Payload which is a\n\t\t * multiple of 8 regardless of what combination of TCP Options\n\t\t * are in use (always a multiple of 4 bytes) which is\n\t\t * important for performance reasons. For instance, if no\n\t\t * options are in use, then we have a 20-byte IP header and a\n\t\t * 20-byte TCP header. In this case, a 1500-byte MSS would\n\t\t * result in a TCP Data Payload of 1500 - 40 == 1460 bytes\n\t\t * which is not a multiple of 8. So using an MSS of 1488 in\n\t\t * this case results in a TCP Data Payload of 1448 bytes which\n\t\t * is a multiple of 8. On the other hand, if 12-byte TCP Time\n\t\t * Stamps have been negotiated, then an MTU of 1500 bytes\n\t\t * results in a TCP Data Payload of 1448 bytes which, as\n\t\t * above, is a multiple of 8 bytes ...\n\t\t */\n\t\tfor (i = 0; i < NMTUS; i++)\n\t\t\tif (adap->params.mtus[i] == 1492) {\n\t\t\t\tadap->params.mtus[i] = 1488;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\tt4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,\n\t\t\t adap->params.b_wnd);\n\t}\n\tt4_init_sge_params(adap);\n\tt4_init_tp_params(adap);\n\n\tadap->params.drv_memwin = MEMWIN_NIC;\n\tadap->flags |= FW_OK;\n\tdev_debug(adap, \"%s: returning zero..\\n\", __func__);\n\treturn 0;\n\n\t/*\n\t * Something bad happened. If a command timed out or failed with EIO\n\t * FW does not operate within its spec or something catastrophic\n\t * happened to HW/FW, stop issuing commands.\n\t */\nbye:\n\tif (ret != -ETIMEDOUT && ret != -EIO)\n\t\tt4_fw_bye(adap, adap->mbox);\n\treturn ret;\n}\n\n/**\n * t4_os_portmod_changed - handle port module changes\n * @adap: the adapter associated with the module change\n * @port_id: the port index whose module status has changed\n *\n * This is the OS-dependent handler for port module changes. It is\n * invoked when a port module is removed or inserted for any OS-specific\n * processing.\n */\nvoid t4_os_portmod_changed(const struct adapter *adap, int port_id)\n{\n\tstatic const char * const mod_str[] = {\n\t\tNULL, \"LR\", \"SR\", \"ER\", \"passive DA\", \"active DA\", \"LRM\"\n\t};\n\n\tconst struct port_info *pi = &adap->port[port_id];\n\n\tif (pi->mod_type == FW_PORT_MOD_TYPE_NONE)\n\t\tdev_info(adap, \"Port%d: port module unplugged\\n\", pi->port_id);\n\telse if (pi->mod_type < ARRAY_SIZE(mod_str))\n\t\tdev_info(adap, \"Port%d: %s port module inserted\\n\", pi->port_id,\n\t\t\t mod_str[pi->mod_type]);\n\telse if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)\n\t\tdev_info(adap, \"Port%d: unsupported optical port module inserted\\n\",\n\t\t\t pi->port_id);\n\telse if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)\n\t\tdev_info(adap, \"Port%d: unknown port module inserted, forcing TWINAX\\n\",\n\t\t\t pi->port_id);\n\telse if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)\n\t\tdev_info(adap, \"Port%d: transceiver module error\\n\",\n\t\t\t pi->port_id);\n\telse\n\t\tdev_info(adap, \"Port%d: unknown module type %d inserted\\n\",\n\t\t\t pi->port_id, pi->mod_type);\n}\n\n/**\n * link_start - enable a port\n * @dev: the port to enable\n *\n * Performs the MAC and PHY actions needed to enable a port.\n */\nint link_start(struct port_info *pi)\n{\n\tstruct adapter *adapter = pi->adapter;\n\tint ret;\n\n\t/*\n\t * We do not set address filters and promiscuity here, the stack does\n\t * that step explicitly.\n\t */\n\tret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, 1500, -1, -1,\n\t\t\t -1, 1, true);\n\tif (ret == 0) {\n\t\tret = t4_change_mac(adapter, adapter->mbox, pi->viid,\n\t\t\t\t pi->xact_addr_filt,\n\t\t\t\t (u8 *)&pi->eth_dev->data->mac_addrs[0],\n\t\t\t\t true, true);\n\t\tif (ret >= 0) {\n\t\t\tpi->xact_addr_filt = ret;\n\t\t\tret = 0;\n\t\t}\n\t}\n\tif (ret == 0)\n\t\tret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,\n\t\t\t\t &pi->link_cfg);\n\tif (ret == 0) {\n\t\t/*\n\t\t * Enabling a Virtual Interface can result in an interrupt\n\t\t * during the processing of the VI Enable command and, in some\n\t\t * paths, result in an attempt to issue another command in the\n\t\t * interrupt context. Thus, we disable interrupts during the\n\t\t * course of the VI Enable command ...\n\t\t */\n\t\tret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,\n\t\t\t\t\t true, true, false);\n\t}\n\treturn ret;\n}\n\n/**\n * cxgb4_write_rss - write the RSS table for a given port\n * @pi: the port\n * @queues: array of queue indices for RSS\n *\n * Sets up the portion of the HW RSS table for the port's VI to distribute\n * packets to the Rx queues in @queues.\n */\nint cxgb4_write_rss(const struct port_info *pi, const u16 *queues)\n{\n\tu16 *rss;\n\tint i, err;\n\tstruct adapter *adapter = pi->adapter;\n\tconst struct sge_eth_rxq *rxq;\n\n\t/* Should never be called before setting up sge eth rx queues */\n\tBUG_ON(!(adapter->flags & FULL_INIT_DONE));\n\n\trxq = &adapter->sge.ethrxq[pi->first_qset];\n\trss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);\n\tif (!rss)\n\t\treturn -ENOMEM;\n\n\t/* map the queue indices to queue ids */\n\tfor (i = 0; i < pi->rss_size; i++, queues++)\n\t\trss[i] = rxq[*queues].rspq.abs_id;\n\n\terr = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,\n\t\t\t\t pi->rss_size, rss, pi->rss_size);\n\t/*\n\t * If Tunnel All Lookup isn't specified in the global RSS\n\t * Configuration, then we need to specify a default Ingress\n\t * Queue for any ingress packets which aren't hashed. We'll\n\t * use our first ingress queue ...\n\t */\n\tif (!err)\n\t\terr = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,\n\t\t\t\t F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |\n\t\t\t\t F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |\n\t\t\t\t F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |\n\t\t\t\t F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN |\n\t\t\t\t F_FW_RSS_VI_CONFIG_CMD_UDPEN,\n\t\t\t\t rss[0]);\n\trte_free(rss);\n\treturn err;\n}\n\n/**\n * setup_rss - configure RSS\n * @adapter: the adapter\n *\n * Sets up RSS to distribute packets to multiple receive queues. We\n * configure the RSS CPU lookup table to distribute to the number of HW\n * receive queues, and the response queue lookup table to narrow that\n * down to the response queues actually configured for each port.\n * We always configure the RSS mapping for all ports since the mapping\n * table has plenty of entries.\n */\nint setup_rss(struct port_info *pi)\n{\n\tint j, err;\n\tstruct adapter *adapter = pi->adapter;\n\n\tdev_debug(adapter, \"%s: pi->rss_size = %u; pi->n_rx_qsets = %u\\n\",\n\t\t __func__, pi->rss_size, pi->n_rx_qsets);\n\n\tif (!pi->flags & PORT_RSS_DONE) {\n\t\tif (adapter->flags & FULL_INIT_DONE) {\n\t\t\t/* Fill default values with equal distribution */\n\t\t\tfor (j = 0; j < pi->rss_size; j++)\n\t\t\t\tpi->rss[j] = j % pi->n_rx_qsets;\n\n\t\t\terr = cxgb4_write_rss(pi, pi->rss);\n\t\t\tif (err)\n\t\t\t\treturn err;\n\t\t\tpi->flags |= PORT_RSS_DONE;\n\t\t}\n\t}\n\treturn 0;\n}\n\n/*\n * Enable NAPI scheduling and interrupt generation for all Rx queues.\n */\nstatic void enable_rx(struct adapter *adap)\n{\n\tstruct sge *s = &adap->sge;\n\tstruct sge_rspq *q = &s->fw_evtq;\n\tint i, j;\n\n\t/* 0-increment GTS to start the timer and enable interrupts */\n\tt4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS),\n\t\t V_SEINTARM(q->intr_params) |\n\t\t V_INGRESSQID(q->cntxt_id));\n\n\tfor_each_port(adap, i) {\n\t\tconst struct port_info *pi = &adap->port[i];\n\t\tstruct rte_eth_dev *eth_dev = pi->eth_dev;\n\n\t\tfor (j = 0; j < eth_dev->data->nb_rx_queues; j++) {\n\t\t\tq = eth_dev->data->rx_queues[j];\n\n\t\t\t/*\n\t\t\t * 0-increment GTS to start the timer and enable\n\t\t\t * interrupts\n\t\t\t */\n\t\t\tt4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS),\n\t\t\t\t V_SEINTARM(q->intr_params) |\n\t\t\t\t V_INGRESSQID(q->cntxt_id));\n\t\t}\n\t}\n}\n\n/**\n * cxgb_up - enable the adapter\n * @adap: adapter being enabled\n *\n * Called when the first port is enabled, this function performs the\n * actions necessary to make an adapter operational, such as completing\n * the initialization of HW modules, and enabling interrupts.\n */\nint cxgbe_up(struct adapter *adap)\n{\n\tenable_rx(adap);\n\tt4_sge_tx_monitor_start(adap);\n\tt4_intr_enable(adap);\n\tadap->flags |= FULL_INIT_DONE;\n\n\t/* TODO: deadman watchdog ?? */\n\treturn 0;\n}\n\n/*\n * Close the port\n */\nint cxgbe_down(struct port_info *pi)\n{\n\tstruct adapter *adapter = pi->adapter;\n\tint err = 0;\n\n\terr = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);\n\tif (err) {\n\t\tdev_err(adapter, \"%s: disable_vi failed: %d\\n\", __func__, err);\n\t\treturn err;\n\t}\n\n\tt4_reset_link_config(adapter, pi->port_id);\n\treturn 0;\n}\n\n/*\n * Release resources when all the ports have been stopped.\n */\nvoid cxgbe_close(struct adapter *adapter)\n{\n\tstruct port_info *pi;\n\tint i;\n\n\tif (adapter->flags & FULL_INIT_DONE) {\n\t\tt4_intr_disable(adapter);\n\t\tt4_sge_tx_monitor_stop(adapter);\n\t\tt4_free_sge_resources(adapter);\n\t\tfor_each_port(adapter, i) {\n\t\t\tpi = adap2pinfo(adapter, i);\n\t\t\tif (pi->viid != 0)\n\t\t\t\tt4_free_vi(adapter, adapter->mbox,\n\t\t\t\t\t adapter->pf, 0, pi->viid);\n\t\t\trte_free(pi->eth_dev->data->mac_addrs);\n\t\t}\n\t\tadapter->flags &= ~FULL_INIT_DONE;\n\t}\n\n\tif (adapter->flags & FW_OK)\n\t\tt4_fw_bye(adapter, adapter->mbox);\n}\n\nint cxgbe_probe(struct adapter *adapter)\n{\n\tstruct port_info *pi;\n\tint func, i;\n\tint err = 0;\n\n\tfunc = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));\n\tadapter->mbox = func;\n\tadapter->pf = func;\n\n\tt4_os_lock_init(&adapter->mbox_lock);\n\tTAILQ_INIT(&adapter->mbox_list);\n\n\terr = t4_prep_adapter(adapter);\n\tif (err)\n\t\treturn err;\n\n\tsetup_memwin(adapter);\n\terr = adap_init0(adapter);\n\tif (err) {\n\t\tdev_err(adapter, \"%s: Adapter initialization failed, error %d\\n\",\n\t\t\t__func__, err);\n\t\tgoto out_free;\n\t}\n\n\tif (!is_t4(adapter->params.chip)) {\n\t\t/*\n\t\t * The userspace doorbell BAR is split evenly into doorbell\n\t\t * regions, each associated with an egress queue. If this\n\t\t * per-queue region is large enough (at least UDBS_SEG_SIZE)\n\t\t * then it can be used to submit a tx work request with an\n\t\t * implied doorbell. Enable write combining on the BAR if\n\t\t * there is room for such work requests.\n\t\t */\n\t\tint s_qpp, qpp, num_seg;\n\n\t\ts_qpp = (S_QUEUESPERPAGEPF0 +\n\t\t\t(S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *\n\t\t\tadapter->pf);\n\t\tqpp = 1 << ((t4_read_reg(adapter,\n\t\t\t\tA_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)\n\t\t\t\t& M_QUEUESPERPAGEPF0);\n\t\tnum_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;\n\t\tif (qpp > num_seg)\n\t\t\tdev_warn(adapter, \"Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\\n\");\n\n\t\tadapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;\n\t\tif (!adapter->bar2) {\n\t\t\tdev_err(adapter, \"cannot map device bar2 region\\n\");\n\t\t\terr = -ENOMEM;\n\t\t\tgoto out_free;\n\t\t}\n\t\tt4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |\n\t\t\t V_STATMODE(0));\n\t}\n\n\tfor_each_port(adapter, i) {\n\t\tchar name[RTE_ETH_NAME_MAX_LEN];\n\t\tstruct rte_eth_dev_data *data = NULL;\n\t\tconst unsigned int numa_node = rte_socket_id();\n\n\t\tpi = &adapter->port[i];\n\t\tpi->adapter = adapter;\n\t\tpi->xact_addr_filt = -1;\n\t\tpi->port_id = i;\n\n\t\tsnprintf(name, sizeof(name), \"cxgbe%d\",\n\t\t\t adapter->eth_dev->data->port_id + i);\n\n\t\tif (i == 0) {\n\t\t\t/* First port is already allocated by DPDK */\n\t\t\tpi->eth_dev = adapter->eth_dev;\n\t\t\tgoto allocate_mac;\n\t\t}\n\n\t\t/*\n\t\t * now do all data allocation - for eth_dev structure,\n\t\t * and internal (private) data for the remaining ports\n\t\t */\n\n\t\t/* reserve an ethdev entry */\n\t\tpi->eth_dev = rte_eth_dev_allocate(name, RTE_ETH_DEV_PCI);\n\t\tif (!pi->eth_dev)\n\t\t\tgoto out_free;\n\n\t\tdata = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node);\n\t\tif (!data)\n\t\t\tgoto out_free;\n\n\t\tdata->port_id = adapter->eth_dev->data->port_id + i;\n\n\t\tpi->eth_dev->data = data;\n\nallocate_mac:\n\t\tpi->eth_dev->pci_dev = adapter->pdev;\n\t\tpi->eth_dev->data->dev_private = pi;\n\t\tpi->eth_dev->driver = adapter->eth_dev->driver;\n\t\tpi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;\n\t\tpi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;\n\t\tpi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;\n\t\tTAILQ_INIT(&pi->eth_dev->link_intr_cbs);\n\n\t\tpi->eth_dev->data->mac_addrs = rte_zmalloc(name,\n\t\t\t\t\t\t\t ETHER_ADDR_LEN, 0);\n\t\tif (!pi->eth_dev->data->mac_addrs) {\n\t\t\tdev_err(adapter, \"%s: Mem allocation failed for storing mac addr, aborting\\n\",\n\t\t\t\t__func__);\n\t\t\terr = -1;\n\t\t\tgoto out_free;\n\t\t}\n\t}\n\n\tif (adapter->flags & FW_OK) {\n\t\terr = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);\n\t\tif (err) {\n\t\t\tdev_err(adapter, \"%s: t4_port_init failed with err %d\\n\",\n\t\t\t\t__func__, err);\n\t\t\tgoto out_free;\n\t\t}\n\t}\n\n\tcfg_queues(adapter->eth_dev);\n\n\tprint_port_info(adapter);\n\n\terr = init_rss(adapter);\n\tif (err)\n\t\tgoto out_free;\n\n\treturn 0;\n\nout_free:\n\tfor_each_port(adapter, i) {\n\t\tpi = adap2pinfo(adapter, i);\n\t\tif (pi->viid != 0)\n\t\t\tt4_free_vi(adapter, adapter->mbox, adapter->pf,\n\t\t\t\t 0, pi->viid);\n\t\t/* Skip first port since it'll be de-allocated by DPDK */\n\t\tif (i == 0)\n\t\t\tcontinue;\n\t\tif (pi->eth_dev->data)\n\t\t\trte_free(pi->eth_dev->data);\n\t}\n\n\tif (adapter->flags & FW_OK)\n\t\tt4_fw_bye(adapter, adapter->mbox);\n\treturn -err;\n}\n" }, { "path": "drivers/net/cxgbe/sge.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014-2015 Chelsio Communications.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Chelsio Communications nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"common.h\"\n#include \"t4_regs.h\"\n#include \"t4_msg.h\"\n#include \"cxgbe.h\"\n\nstatic inline void ship_tx_pkt_coalesce_wr(struct adapter *adap,\n\t\t\t\t\t struct sge_eth_txq *txq);\n\n/*\n * Max number of Rx buffers we replenish at a time.\n */\n#define MAX_RX_REFILL 64U\n\n#define NOMEM_TMR_IDX (SGE_NTIMERS - 1)\n\n/*\n * Max Tx descriptor space we allow for an Ethernet packet to be inlined\n * into a WR.\n */\n#define MAX_IMM_TX_PKT_LEN 256\n\n/*\n * Rx buffer sizes for \"usembufs\" Free List buffers (one ingress packet\n * per mbuf buffer). We currently only support two sizes for 1500- and\n * 9000-byte MTUs. We could easily support more but there doesn't seem to be\n * much need for that ...\n */\n#define FL_MTU_SMALL 1500\n#define FL_MTU_LARGE 9000\n\nstatic inline unsigned int fl_mtu_bufsize(struct adapter *adapter,\n\t\t\t\t\t unsigned int mtu)\n{\n\tstruct sge *s = &adapter->sge;\n\n\treturn CXGBE_ALIGN(s->pktshift + ETHER_HDR_LEN + VLAN_HLEN + mtu,\n\t\t\t s->fl_align);\n}\n\n#define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL)\n#define FL_MTU_LARGE_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_LARGE)\n\n/*\n * Bits 0..3 of rx_sw_desc.dma_addr have special meaning. The hardware uses\n * these to specify the buffer size as an index into the SGE Free List Buffer\n * Size register array. We also use bit 4, when the buffer has been unmapped\n * for DMA, but this is of course never sent to the hardware and is only used\n * to prevent double unmappings. All of the above requires that the Free List\n * Buffers which we allocate have the bottom 5 bits free (0) -- i.e. are\n * 32-byte or or a power of 2 greater in alignment. Since the SGE's minimal\n * Free List Buffer alignment is 32 bytes, this works out for us ...\n */\nenum {\n\tRX_BUF_FLAGS = 0x1f, /* bottom five bits are special */\n\tRX_BUF_SIZE = 0x0f, /* bottom three bits are for buf sizes */\n\tRX_UNMAPPED_BUF = 0x10, /* buffer is not mapped */\n\n\t/*\n\t * XXX We shouldn't depend on being able to use these indices.\n\t * XXX Especially when some other Master PF has initialized the\n\t * XXX adapter or we use the Firmware Configuration File. We\n\t * XXX should really search through the Host Buffer Size register\n\t * XXX array for the appropriately sized buffer indices.\n\t */\n\tRX_SMALL_PG_BUF = 0x0, /* small (PAGE_SIZE) page buffer */\n\tRX_LARGE_PG_BUF = 0x1, /* buffer large page buffer */\n\n\tRX_SMALL_MTU_BUF = 0x2, /* small MTU buffer */\n\tRX_LARGE_MTU_BUF = 0x3, /* large MTU buffer */\n};\n\n/**\n * txq_avail - return the number of available slots in a Tx queue\n * @q: the Tx queue\n *\n * Returns the number of descriptors in a Tx queue available to write new\n * packets.\n */\nstatic inline unsigned int txq_avail(const struct sge_txq *q)\n{\n\treturn q->size - 1 - q->in_use;\n}\n\nstatic int map_mbuf(struct rte_mbuf *mbuf, dma_addr_t *addr)\n{\n\tstruct rte_mbuf *m = mbuf;\n\n\tfor (; m; m = m->next, addr++) {\n\t\t*addr = m->buf_physaddr + rte_pktmbuf_headroom(m);\n\t\tif (*addr == 0)\n\t\t\tgoto out_err;\n\t}\n\treturn 0;\n\nout_err:\n\treturn -ENOMEM;\n}\n\n/**\n * free_tx_desc - reclaims Tx descriptors and their buffers\n * @q: the Tx queue to reclaim descriptors from\n * @n: the number of descriptors to reclaim\n *\n * Reclaims Tx descriptors from an SGE Tx queue and frees the associated\n * Tx buffers. Called with the Tx queue lock held.\n */\nstatic void free_tx_desc(struct sge_txq *q, unsigned int n)\n{\n\tstruct tx_sw_desc *d;\n\tunsigned int cidx = 0;\n\n\td = &q->sdesc[cidx];\n\twhile (n--) {\n\t\tif (d->mbuf) { /* an SGL is present */\n\t\t\trte_pktmbuf_free(d->mbuf);\n\t\t\td->mbuf = NULL;\n\t\t}\n\t\tif (d->coalesce.idx) {\n\t\t\tint i;\n\n\t\t\tfor (i = 0; i < d->coalesce.idx; i++) {\n\t\t\t\trte_pktmbuf_free(d->coalesce.mbuf[i]);\n\t\t\t\td->coalesce.mbuf[i] = NULL;\n\t\t\t}\n\t\t\td->coalesce.idx = 0;\n\t\t}\n\t\t++d;\n\t\tif (++cidx == q->size) {\n\t\t\tcidx = 0;\n\t\t\td = q->sdesc;\n\t\t}\n\t\tRTE_MBUF_PREFETCH_TO_FREE(&q->sdesc->mbuf->pool);\n\t}\n}\n\nstatic void reclaim_tx_desc(struct sge_txq *q, unsigned int n)\n{\n\tunsigned int cidx = q->cidx;\n\n\twhile (n--) {\n\t\tif (++cidx == q->size)\n\t\t\tcidx = 0;\n\t}\n\tq->cidx = cidx;\n}\n\n/**\n * fl_cap - return the capacity of a free-buffer list\n * @fl: the FL\n *\n * Returns the capacity of a free-buffer list. The capacity is less than\n * the size because one descriptor needs to be left unpopulated, otherwise\n * HW will think the FL is empty.\n */\nstatic inline unsigned int fl_cap(const struct sge_fl *fl)\n{\n\treturn fl->size - 8; /* 1 descriptor = 8 buffers */\n}\n\n/**\n * fl_starving - return whether a Free List is starving.\n * @adapter: pointer to the adapter\n * @fl: the Free List\n *\n * Tests specified Free List to see whether the number of buffers\n * available to the hardware has falled below our \"starvation\"\n * threshold.\n */\nstatic inline bool fl_starving(const struct adapter *adapter,\n\t\t\t const struct sge_fl *fl)\n{\n\tconst struct sge *s = &adapter->sge;\n\n\treturn fl->avail - fl->pend_cred <= s->fl_starve_thres;\n}\n\n/**\n * free_rx_bufs - free the Rx buffers on an SGE free list\n * @q: the SGE free list to free buffers from\n * @n: how many buffers to free\n *\n * Release the next @n buffers on an SGE free-buffer Rx queue. The\n * buffers must be made inaccessible to HW before calling this function.\n */\nstatic void free_rx_bufs(struct sge_fl *q, int n)\n{\n\tunsigned int cidx = q->cidx;\n\tstruct rx_sw_desc *d;\n\n\td = &q->sdesc[cidx];\n\twhile (n--) {\n\t\tif (d->buf) {\n\t\t\trte_pktmbuf_free(d->buf);\n\t\t\td->buf = NULL;\n\t\t}\n\t\t++d;\n\t\tif (++cidx == q->size) {\n\t\t\tcidx = 0;\n\t\t\td = q->sdesc;\n\t\t}\n\t\tq->avail--;\n\t}\n\tq->cidx = cidx;\n}\n\n/**\n * unmap_rx_buf - unmap the current Rx buffer on an SGE free list\n * @q: the SGE free list\n *\n * Unmap the current buffer on an SGE free-buffer Rx queue. The\n * buffer must be made inaccessible to HW before calling this function.\n *\n * This is similar to @free_rx_bufs above but does not free the buffer.\n * Do note that the FL still loses any further access to the buffer.\n */\nstatic void unmap_rx_buf(struct sge_fl *q)\n{\n\tif (++q->cidx == q->size)\n\t\tq->cidx = 0;\n\tq->avail--;\n}\n\nstatic inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)\n{\n\t/* see if we have exceeded q->size / 4 */\n\tif (q->pend_cred >= (q->size / 4)) {\n\t\tu32 val = adap->params.arch.sge_fl_db;\n\n\t\tif (is_t4(adap->params.chip))\n\t\t\tval |= V_PIDX(q->pend_cred / 8);\n\t\telse\n\t\t\tval |= V_PIDX_T5(q->pend_cred / 8);\n\n\t\t/*\n\t\t * Make sure all memory writes to the Free List queue are\n\t\t * committed before we tell the hardware about them.\n\t\t */\n\t\twmb();\n\n\t\t/*\n\t\t * If we don't have access to the new User Doorbell (T5+), use\n\t\t * the old doorbell mechanism; otherwise use the new BAR2\n\t\t * mechanism.\n\t\t */\n\t\tif (unlikely(!q->bar2_addr)) {\n\t\t\tt4_write_reg(adap, MYPF_REG(A_SGE_PF_KDOORBELL),\n\t\t\t\t val | V_QID(q->cntxt_id));\n\t\t} else {\n\t\t\twritel(val | V_QID(q->bar2_qid),\n\t\t\t (void *)((uintptr_t)q->bar2_addr +\n\t\t\t SGE_UDB_KDOORBELL));\n\n\t\t\t/*\n\t\t\t * This Write memory Barrier will force the write to\n\t\t\t * the User Doorbell area to be flushed.\n\t\t\t */\n\t\t\twmb();\n\t\t}\n\t\tq->pend_cred &= 7;\n\t}\n}\n\nstatic inline void set_rx_sw_desc(struct rx_sw_desc *sd, void *buf,\n\t\t\t\t dma_addr_t mapping)\n{\n\tsd->buf = buf;\n\tsd->dma_addr = mapping; /* includes size low bits */\n}\n\n/**\n * refill_fl_usembufs - refill an SGE Rx buffer ring with mbufs\n * @adap: the adapter\n * @q: the ring to refill\n * @n: the number of new buffers to allocate\n *\n * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,\n * allocated with the supplied gfp flags. The caller must assure that\n * @n does not exceed the queue's capacity. If afterwards the queue is\n * found critically low mark it as starving in the bitmap of starving FLs.\n *\n * Returns the number of buffers allocated.\n */\nstatic unsigned int refill_fl_usembufs(struct adapter *adap, struct sge_fl *q,\n\t\t\t\t int n)\n{\n\tstruct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, fl);\n\tunsigned int cred = q->avail;\n\t__be64 *d = &q->desc[q->pidx];\n\tstruct rx_sw_desc *sd = &q->sdesc[q->pidx];\n\tunsigned int buf_size_idx = RX_SMALL_MTU_BUF;\n\tstruct rte_mbuf *buf_bulk[n];\n\tint ret, i;\n\n\tret = rte_mempool_get_bulk(rxq->rspq.mb_pool, (void *)buf_bulk, n);\n\tif (unlikely(ret != 0)) {\n\t\tdev_debug(adap, \"%s: failed to allocated fl entries in bulk ..\\n\",\n\t\t\t __func__);\n\t\tq->alloc_failed++;\n\t\trxq->rspq.eth_dev->data->rx_mbuf_alloc_failed++;\n\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < n; i++) {\n\t\tstruct rte_mbuf *mbuf = buf_bulk[i];\n\t\tdma_addr_t mapping;\n\n\t\tif (!mbuf) {\n\t\t\tdev_debug(adap, \"%s: mbuf alloc failed\\n\", __func__);\n\t\t\tq->alloc_failed++;\n\t\t\trxq->rspq.eth_dev->data->rx_mbuf_alloc_failed++;\n\t\t\tgoto out;\n\t\t}\n\n\t\trte_mbuf_refcnt_set(mbuf, 1);\n\t\tmbuf->data_off = RTE_PKTMBUF_HEADROOM;\n\t\tmbuf->next = NULL;\n\t\tmbuf->nb_segs = 1;\n\t\tmbuf->port = rxq->rspq.port_id;\n\n\t\tmapping = (dma_addr_t)(mbuf->buf_physaddr + mbuf->data_off);\n\t\tmapping |= buf_size_idx;\n\t\t*d++ = cpu_to_be64(mapping);\n\t\tset_rx_sw_desc(sd, mbuf, mapping);\n\t\tsd++;\n\n\t\tq->avail++;\n\t\tif (++q->pidx == q->size) {\n\t\t\tq->pidx = 0;\n\t\t\tsd = q->sdesc;\n\t\t\td = q->desc;\n\t\t}\n\t}\n\nout: cred = q->avail - cred;\n\tq->pend_cred += cred;\n\tring_fl_db(adap, q);\n\n\tif (unlikely(fl_starving(adap, q))) {\n\t\t/*\n\t\t * Make sure data has been written to free list\n\t\t */\n\t\twmb();\n\t\tq->low++;\n\t}\n\n\treturn cred;\n}\n\n/**\n * refill_fl - refill an SGE Rx buffer ring with mbufs\n * @adap: the adapter\n * @q: the ring to refill\n * @n: the number of new buffers to allocate\n *\n * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,\n * allocated with the supplied gfp flags. The caller must assure that\n * @n does not exceed the queue's capacity. Returns the number of buffers\n * allocated.\n */\nstatic unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n)\n{\n\treturn refill_fl_usembufs(adap, q, n);\n}\n\nstatic inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)\n{\n\trefill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail));\n}\n\n/*\n * Return the number of reclaimable descriptors in a Tx queue.\n */\nstatic inline int reclaimable(const struct sge_txq *q)\n{\n\tint hw_cidx = ntohs(q->stat->cidx);\n\n\thw_cidx -= q->cidx;\n\tif (hw_cidx < 0)\n\t\treturn hw_cidx + q->size;\n\treturn hw_cidx;\n}\n\n/**\n * reclaim_completed_tx - reclaims completed Tx descriptors\n * @q: the Tx queue to reclaim completed descriptors from\n *\n * Reclaims Tx descriptors that the SGE has indicated it has processed.\n */\nvoid reclaim_completed_tx(struct sge_txq *q)\n{\n\tunsigned int avail = reclaimable(q);\n\n\tdo {\n\t\t/* reclaim as much as possible */\n\t\treclaim_tx_desc(q, avail);\n\t\tq->in_use -= avail;\n\t\tavail = reclaimable(q);\n\t} while (avail);\n}\n\n/**\n * sgl_len - calculates the size of an SGL of the given capacity\n * @n: the number of SGL entries\n *\n * Calculates the number of flits needed for a scatter/gather list that\n * can hold the given number of entries.\n */\nstatic inline unsigned int sgl_len(unsigned int n)\n{\n\t/*\n\t * A Direct Scatter Gather List uses 32-bit lengths and 64-bit PCI DMA\n\t * addresses. The DSGL Work Request starts off with a 32-bit DSGL\n\t * ULPTX header, then Length0, then Address0, then, for 1 <= i <= N,\n\t * repeated sequences of { Length[i], Length[i+1], Address[i],\n\t * Address[i+1] } (this ensures that all addresses are on 64-bit\n\t * boundaries). If N is even, then Length[N+1] should be set to 0 and\n\t * Address[N+1] is omitted.\n\t *\n\t * The following calculation incorporates all of the above. It's\n\t * somewhat hard to follow but, briefly: the \"+2\" accounts for the\n\t * first two flits which include the DSGL header, Length0 and\n\t * Address0; the \"(3*(n-1))/2\" covers the main body of list entries (3\n\t * flits for every pair of the remaining N) +1 if (n-1) is odd; and\n\t * finally the \"+((n-1)&1)\" adds the one remaining flit needed if\n\t * (n-1) is odd ...\n\t */\n\tn--;\n\treturn (3 * n) / 2 + (n & 1) + 2;\n}\n\n/**\n * flits_to_desc - returns the num of Tx descriptors for the given flits\n * @n: the number of flits\n *\n * Returns the number of Tx descriptors needed for the supplied number\n * of flits.\n */\nstatic inline unsigned int flits_to_desc(unsigned int n)\n{\n\treturn DIV_ROUND_UP(n, 8);\n}\n\n/**\n * is_eth_imm - can an Ethernet packet be sent as immediate data?\n * @m: the packet\n *\n * Returns whether an Ethernet packet is small enough to fit as\n * immediate data. Return value corresponds to the headroom required.\n */\nstatic inline int is_eth_imm(const struct rte_mbuf *m)\n{\n\tunsigned int hdrlen = (m->ol_flags & PKT_TX_TCP_SEG) ?\n\t\t\t sizeof(struct cpl_tx_pkt_lso_core) : 0;\n\n\thdrlen += sizeof(struct cpl_tx_pkt);\n\tif (m->pkt_len <= MAX_IMM_TX_PKT_LEN - hdrlen)\n\t\treturn hdrlen;\n\n\treturn 0;\n}\n\n/**\n * calc_tx_flits - calculate the number of flits for a packet Tx WR\n * @m: the packet\n *\n * Returns the number of flits needed for a Tx WR for the given Ethernet\n * packet, including the needed WR and CPL headers.\n */\nstatic inline unsigned int calc_tx_flits(const struct rte_mbuf *m)\n{\n\tunsigned int flits;\n\tint hdrlen;\n\n\t/*\n\t * If the mbuf is small enough, we can pump it out as a work request\n\t * with only immediate data. In that case we just have to have the\n\t * TX Packet header plus the mbuf data in the Work Request.\n\t */\n\n\thdrlen = is_eth_imm(m);\n\tif (hdrlen)\n\t\treturn DIV_ROUND_UP(m->pkt_len + hdrlen, sizeof(__be64));\n\n\t/*\n\t * Otherwise, we're going to have to construct a Scatter gather list\n\t * of the mbuf body and fragments. We also include the flits necessary\n\t * for the TX Packet Work Request and CPL. We always have a firmware\n\t * Write Header (incorporated as part of the cpl_tx_pkt_lso and\n\t * cpl_tx_pkt structures), followed by either a TX Packet Write CPL\n\t * message or, if we're doing a Large Send Offload, an LSO CPL message\n\t * with an embeded TX Packet Write CPL message.\n\t */\n\tflits = sgl_len(m->nb_segs);\n\tif (m->tso_segsz)\n\t\tflits += (sizeof(struct fw_eth_tx_pkt_wr) +\n\t\t\t sizeof(struct cpl_tx_pkt_lso_core) +\n\t\t\t sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);\n\telse\n\t\tflits += (sizeof(struct fw_eth_tx_pkt_wr) +\n\t\t\t sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);\n\treturn flits;\n}\n\n/**\n * write_sgl - populate a scatter/gather list for a packet\n * @mbuf: the packet\n * @q: the Tx queue we are writing into\n * @sgl: starting location for writing the SGL\n * @end: points right after the end of the SGL\n * @start: start offset into mbuf main-body data to include in the SGL\n * @addr: address of mapped region\n *\n * Generates a scatter/gather list for the buffers that make up a packet.\n * The caller must provide adequate space for the SGL that will be written.\n * The SGL includes all of the packet's page fragments and the data in its\n * main body except for the first @start bytes. @sgl must be 16-byte\n * aligned and within a Tx descriptor with available space. @end points\n * write after the end of the SGL but does not account for any potential\n * wrap around, i.e., @end > @sgl.\n */\nstatic void write_sgl(struct rte_mbuf *mbuf, struct sge_txq *q,\n\t\t struct ulptx_sgl *sgl, u64 *end, unsigned int start,\n\t\t const dma_addr_t *addr)\n{\n\tunsigned int i, len;\n\tstruct ulptx_sge_pair *to;\n\tstruct rte_mbuf *m = mbuf;\n\tunsigned int nfrags = m->nb_segs;\n\tstruct ulptx_sge_pair buf[nfrags / 2];\n\n\tlen = m->data_len - start;\n\tsgl->len0 = htonl(len);\n\tsgl->addr0 = rte_cpu_to_be_64(addr[0]);\n\n\tsgl->cmd_nsge = htonl(V_ULPTX_CMD(ULP_TX_SC_DSGL) |\n\t\t\t V_ULPTX_NSGE(nfrags));\n\tif (likely(--nfrags == 0))\n\t\treturn;\n\t/*\n\t * Most of the complexity below deals with the possibility we hit the\n\t * end of the queue in the middle of writing the SGL. For this case\n\t * only we create the SGL in a temporary buffer and then copy it.\n\t */\n\tto = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge;\n\n\tfor (i = 0; nfrags >= 2; nfrags -= 2, to++) {\n\t\tm = m->next;\n\t\tto->len[0] = rte_cpu_to_be_32(m->data_len);\n\t\tto->addr[0] = rte_cpu_to_be_64(addr[++i]);\n\t\tm = m->next;\n\t\tto->len[1] = rte_cpu_to_be_32(m->data_len);\n\t\tto->addr[1] = rte_cpu_to_be_64(addr[++i]);\n\t}\n\tif (nfrags) {\n\t\tm = m->next;\n\t\tto->len[0] = rte_cpu_to_be_32(m->data_len);\n\t\tto->len[1] = rte_cpu_to_be_32(0);\n\t\tto->addr[0] = rte_cpu_to_be_64(addr[i + 1]);\n\t}\n\tif (unlikely((u8 *)end > (u8 *)q->stat)) {\n\t\tunsigned int part0 = RTE_PTR_DIFF((u8 *)q->stat,\n\t\t\t\t\t\t (u8 *)sgl->sge);\n\t\tunsigned int part1;\n\n\t\tif (likely(part0))\n\t\t\tmemcpy(sgl->sge, buf, part0);\n\t\tpart1 = RTE_PTR_DIFF((u8 *)end, (u8 *)q->stat);\n\t\trte_memcpy(q->desc, RTE_PTR_ADD((u8 *)buf, part0), part1);\n\t\tend = RTE_PTR_ADD((void *)q->desc, part1);\n\t}\n\tif ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */\n\t\t*(u64 *)end = 0;\n}\n\n#define IDXDIFF(head, tail, wrap) \\\n\t((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))\n\n#define Q_IDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->size)\n#define R_IDXDIFF(q, idx) IDXDIFF((q)->cidx, (q)->idx, (q)->size)\n\n/**\n * ring_tx_db - ring a Tx queue's doorbell\n * @adap: the adapter\n * @q: the Tx queue\n * @n: number of new descriptors to give to HW\n *\n * Ring the doorbel for a Tx queue.\n */\nstatic inline void ring_tx_db(struct adapter *adap, struct sge_txq *q)\n{\n\tint n = Q_IDXDIFF(q, dbidx);\n\n\t/*\n\t * Make sure that all writes to the TX Descriptors are committed\n\t * before we tell the hardware about them.\n\t */\n\trte_wmb();\n\n\t/*\n\t * If we don't have access to the new User Doorbell (T5+), use the old\n\t * doorbell mechanism; otherwise use the new BAR2 mechanism.\n\t */\n\tif (unlikely(!q->bar2_addr)) {\n\t\tu32 val = V_PIDX(n);\n\n\t\t/*\n\t\t * For T4 we need to participate in the Doorbell Recovery\n\t\t * mechanism.\n\t\t */\n\t\tif (!q->db_disabled)\n\t\t\tt4_write_reg(adap, MYPF_REG(A_SGE_PF_KDOORBELL),\n\t\t\t\t V_QID(q->cntxt_id) | val);\n\t\telse\n\t\t\tq->db_pidx_inc += n;\n\t\tq->db_pidx = q->pidx;\n\t} else {\n\t\tu32 val = V_PIDX_T5(n);\n\n\t\t/*\n\t\t * T4 and later chips share the same PIDX field offset within\n\t\t * the doorbell, but T5 and later shrank the field in order to\n\t\t * gain a bit for Doorbell Priority. The field was absurdly\n\t\t * large in the first place (14 bits) so we just use the T5\n\t\t * and later limits and warn if a Queue ID is too large.\n\t\t */\n\t\tWARN_ON(val & F_DBPRIO);\n\n\t\twritel(val | V_QID(q->bar2_qid),\n\t\t (void *)((uintptr_t)q->bar2_addr + SGE_UDB_KDOORBELL));\n\n\t\t/*\n\t\t * This Write Memory Barrier will force the write to the User\n\t\t * Doorbell area to be flushed. This is needed to prevent\n\t\t * writes on different CPUs for the same queue from hitting\n\t\t * the adapter out of order. This is required when some Work\n\t\t * Requests take the Write Combine Gather Buffer path (user\n\t\t * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some\n\t\t * take the traditional path where we simply increment the\n\t\t * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the\n\t\t * hardware DMA read the actual Work Request.\n\t\t */\n\t\trte_wmb();\n\t}\n\tq->dbidx = q->pidx;\n}\n\n/*\n * Figure out what HW csum a packet wants and return the appropriate control\n * bits.\n */\nstatic u64 hwcsum(enum chip_type chip, const struct rte_mbuf *m)\n{\n\tint csum_type;\n\n\tif (m->ol_flags & PKT_TX_IP_CKSUM) {\n\t\tswitch (m->ol_flags & PKT_TX_L4_MASK) {\n\t\tcase PKT_TX_TCP_CKSUM:\n\t\t\tcsum_type = TX_CSUM_TCPIP;\n\t\t\tbreak;\n\t\tcase PKT_TX_UDP_CKSUM:\n\t\t\tcsum_type = TX_CSUM_UDPIP;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tgoto nocsum;\n\t\t}\n\t} else {\n\t\tgoto nocsum;\n\t}\n\n\tif (likely(csum_type >= TX_CSUM_TCPIP)) {\n\t\tint hdr_len = V_TXPKT_IPHDR_LEN(m->l3_len);\n\t\tint eth_hdr_len = m->l2_len;\n\n\t\tif (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)\n\t\t\thdr_len |= V_TXPKT_ETHHDR_LEN(eth_hdr_len);\n\t\telse\n\t\t\thdr_len |= V_T6_TXPKT_ETHHDR_LEN(eth_hdr_len);\n\t\treturn V_TXPKT_CSUM_TYPE(csum_type) | hdr_len;\n\t}\nnocsum:\n\t/*\n\t * unknown protocol, disable HW csum\n\t * and hope a bad packet is detected\n\t */\n\treturn F_TXPKT_L4CSUM_DIS;\n}\n\nstatic inline void txq_advance(struct sge_txq *q, unsigned int n)\n{\n\tq->in_use += n;\n\tq->pidx += n;\n\tif (q->pidx >= q->size)\n\t\tq->pidx -= q->size;\n}\n\n#define MAX_COALESCE_LEN 64000\n\nstatic inline int wraps_around(struct sge_txq *q, int ndesc)\n{\n\treturn (q->pidx + ndesc) > q->size ? 1 : 0;\n}\n\nstatic void tx_timer_cb(void *data)\n{\n\tstruct adapter *adap = (struct adapter *)data;\n\tstruct sge_eth_txq *txq = &adap->sge.ethtxq[0];\n\tint i;\n\n\t/* monitor any pending tx */\n\tfor (i = 0; i < adap->sge.max_ethqsets; i++, txq++) {\n\t\tt4_os_lock(&txq->txq_lock);\n\t\tif (txq->q.coalesce.idx) {\n\t\t\tif (txq->q.coalesce.idx == txq->q.last_coal_idx &&\n\t\t\t txq->q.pidx == txq->q.last_pidx) {\n\t\t\t\tship_tx_pkt_coalesce_wr(adap, txq);\n\t\t\t} else {\n\t\t\t\ttxq->q.last_coal_idx = txq->q.coalesce.idx;\n\t\t\t\ttxq->q.last_pidx = txq->q.pidx;\n\t\t\t}\n\t\t}\n\t\tt4_os_unlock(&txq->txq_lock);\n\t}\n\trte_eal_alarm_set(50, tx_timer_cb, (void *)adap);\n}\n\n/**\n * ship_tx_pkt_coalesce_wr - finalizes and ships a coalesce WR\n * @ adap: adapter structure\n * @txq: tx queue\n *\n * writes the different fields of the pkts WR and sends it.\n */\nstatic inline void ship_tx_pkt_coalesce_wr(struct adapter *adap,\n\t\t\t\t\t struct sge_eth_txq *txq)\n{\n\tu32 wr_mid;\n\tstruct sge_txq *q = &txq->q;\n\tstruct fw_eth_tx_pkts_wr *wr;\n\tunsigned int ndesc;\n\n\t/* fill the pkts WR header */\n\twr = (void *)&q->desc[q->pidx];\n\twr->op_pkd = htonl(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));\n\n\twr_mid = V_FW_WR_LEN16(DIV_ROUND_UP(q->coalesce.flits, 2));\n\tndesc = flits_to_desc(q->coalesce.flits);\n\twr->equiq_to_len16 = htonl(wr_mid);\n\twr->plen = cpu_to_be16(q->coalesce.len);\n\twr->npkt = q->coalesce.idx;\n\twr->r3 = 0;\n\twr->type = q->coalesce.type;\n\n\t/* zero out coalesce structure members */\n\tq->coalesce.idx = 0;\n\tq->coalesce.flits = 0;\n\tq->coalesce.len = 0;\n\n\ttxq_advance(q, ndesc);\n\ttxq->stats.coal_wr++;\n\ttxq->stats.coal_pkts += wr->npkt;\n\n\tif (Q_IDXDIFF(q, equeidx) >= q->size / 2) {\n\t\tq->equeidx = q->pidx;\n\t\twr_mid |= F_FW_WR_EQUEQ;\n\t\twr->equiq_to_len16 = htonl(wr_mid);\n\t}\n\tring_tx_db(adap, q);\n}\n\n/**\n * should_tx_packet_coalesce - decides wether to coalesce an mbuf or not\n * @txq: tx queue where the mbuf is sent\n * @mbuf: mbuf to be sent\n * @nflits: return value for number of flits needed\n * @adap: adapter structure\n *\n * This function decides if a packet should be coalesced or not.\n */\nstatic inline int should_tx_packet_coalesce(struct sge_eth_txq *txq,\n\t\t\t\t\t struct rte_mbuf *mbuf,\n\t\t\t\t\t unsigned int *nflits,\n\t\t\t\t\t struct adapter *adap)\n{\n\tstruct sge_txq *q = &txq->q;\n\tunsigned int flits, ndesc;\n\tunsigned char type = 0;\n\tint credits, hw_cidx = ntohs(q->stat->cidx);\n\tint in_use = q->pidx - hw_cidx + flits_to_desc(q->coalesce.flits);\n\n\t/* use coal WR type 1 when no frags are present */\n\ttype = (mbuf->nb_segs == 1) ? 1 : 0;\n\n\tif (in_use < 0)\n\t\tin_use += q->size;\n\n\tif (unlikely(type != q->coalesce.type && q->coalesce.idx))\n\t\tship_tx_pkt_coalesce_wr(adap, txq);\n\n\t/* calculate the number of flits required for coalescing this packet\n\t * without the 2 flits of the WR header. These are added further down\n\t * if we are just starting in new PKTS WR. sgl_len doesn't account for\n\t * the possible 16 bytes alignment ULP TX commands so we do it here.\n\t */\n\tflits = (sgl_len(mbuf->nb_segs) + 1) & ~1U;\n\tif (type == 0)\n\t\tflits += (sizeof(struct ulp_txpkt) +\n\t\t\t sizeof(struct ulptx_idata)) / sizeof(__be64);\n\tflits += sizeof(struct cpl_tx_pkt_core) / sizeof(__be64);\n\t*nflits = flits;\n\n\t/* If coalescing is on, the mbuf is added to a pkts WR */\n\tif (q->coalesce.idx) {\n\t\tndesc = DIV_ROUND_UP(q->coalesce.flits + flits, 8);\n\t\tcredits = txq_avail(q) - ndesc;\n\n\t\t/* If we are wrapping or this is last mbuf then, send the\n\t\t * already coalesced mbufs and let the non-coalesce pass\n\t\t * handle the mbuf.\n\t\t */\n\t\tif (unlikely(credits < 0 || wraps_around(q, ndesc))) {\n\t\t\tship_tx_pkt_coalesce_wr(adap, txq);\n\t\t\treturn 0;\n\t\t}\n\n\t\t/* If the max coalesce len or the max WR len is reached\n\t\t * ship the WR and keep coalescing on.\n\t\t */\n\t\tif (unlikely((q->coalesce.len + mbuf->pkt_len >\n\t\t\t\t\t\tMAX_COALESCE_LEN) ||\n\t\t\t (q->coalesce.flits + flits >\n\t\t\t q->coalesce.max))) {\n\t\t\tship_tx_pkt_coalesce_wr(adap, txq);\n\t\t\tgoto new;\n\t\t}\n\t\treturn 1;\n\t}\n\nnew:\n\t/* start a new pkts WR, the WR header is not filled below */\n\tflits += sizeof(struct fw_eth_tx_pkts_wr) / sizeof(__be64);\n\tndesc = flits_to_desc(q->coalesce.flits + flits);\n\tcredits = txq_avail(q) - ndesc;\n\n\tif (unlikely(credits < 0 || wraps_around(q, ndesc)))\n\t\treturn 0;\n\tq->coalesce.flits += 2;\n\tq->coalesce.type = type;\n\tq->coalesce.ptr = (unsigned char *)&q->desc[q->pidx] +\n\t\t\t 2 * sizeof(__be64);\n\treturn 1;\n}\n\n/**\n * tx_do_packet_coalesce - add an mbuf to a coalesce WR\n * @txq: sge_eth_txq used send the mbuf\n * @mbuf: mbuf to be sent\n * @flits: flits needed for this mbuf\n * @adap: adapter structure\n * @pi: port_info structure\n * @addr: mapped address of the mbuf\n *\n * Adds an mbuf to be sent as part of a coalesce WR by filling a\n * ulp_tx_pkt command, ulp_tx_sc_imm command, cpl message and\n * ulp_tx_sc_dsgl command.\n */\nstatic inline int tx_do_packet_coalesce(struct sge_eth_txq *txq,\n\t\t\t\t\tstruct rte_mbuf *mbuf,\n\t\t\t\t\tint flits, struct adapter *adap,\n\t\t\t\t\tconst struct port_info *pi,\n\t\t\t\t\tdma_addr_t *addr)\n{\n\tu64 cntrl, *end;\n\tstruct sge_txq *q = &txq->q;\n\tstruct ulp_txpkt *mc;\n\tstruct ulptx_idata *sc_imm;\n\tstruct cpl_tx_pkt_core *cpl;\n\tstruct tx_sw_desc *sd;\n\tunsigned int idx = q->coalesce.idx, len = mbuf->pkt_len;\n\n\tif (q->coalesce.type == 0) {\n\t\tmc = (struct ulp_txpkt *)q->coalesce.ptr;\n\t\tmc->cmd_dest = htonl(V_ULPTX_CMD(4) | V_ULP_TXPKT_DEST(0) |\n\t\t\t\t V_ULP_TXPKT_FID(adap->sge.fw_evtq.cntxt_id) |\n\t\t\t\t F_ULP_TXPKT_RO);\n\t\tmc->len = htonl(DIV_ROUND_UP(flits, 2));\n\t\tsc_imm = (struct ulptx_idata *)(mc + 1);\n\t\tsc_imm->cmd_more = htonl(V_ULPTX_CMD(ULP_TX_SC_IMM) |\n\t\t\t\t\t F_ULP_TX_SC_MORE);\n\t\tsc_imm->len = htonl(sizeof(*cpl));\n\t\tend = (u64 *)mc + flits;\n\t\tcpl = (struct cpl_tx_pkt_core *)(sc_imm + 1);\n\t} else {\n\t\tend = (u64 *)q->coalesce.ptr + flits;\n\t\tcpl = (struct cpl_tx_pkt_core *)q->coalesce.ptr;\n\t}\n\n\t/* update coalesce structure for this txq */\n\tq->coalesce.flits += flits;\n\tq->coalesce.ptr += flits * sizeof(__be64);\n\tq->coalesce.len += mbuf->pkt_len;\n\n\t/* fill the cpl message, same as in t4_eth_xmit, this should be kept\n\t * similar to t4_eth_xmit\n\t */\n\tif (mbuf->ol_flags & PKT_TX_IP_CKSUM) {\n\t\tcntrl = hwcsum(adap->params.chip, mbuf) |\n\t\t\t F_TXPKT_IPCSUM_DIS;\n\t\ttxq->stats.tx_cso++;\n\t} else {\n\t\tcntrl = F_TXPKT_L4CSUM_DIS | F_TXPKT_IPCSUM_DIS;\n\t}\n\n\tif (mbuf->ol_flags & PKT_TX_VLAN_PKT) {\n\t\ttxq->stats.vlan_ins++;\n\t\tcntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(mbuf->vlan_tci);\n\t}\n\n\tcpl->ctrl0 = htonl(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |\n\t\t\t V_TXPKT_INTF(pi->tx_chan) |\n\t\t\t V_TXPKT_PF(adap->pf));\n\tcpl->pack = htons(0);\n\tcpl->len = htons(len);\n\tcpl->ctrl1 = cpu_to_be64(cntrl);\n\twrite_sgl(mbuf, q, (struct ulptx_sgl *)(cpl + 1), end, 0, addr);\n\ttxq->stats.pkts++;\n\ttxq->stats.tx_bytes += len;\n\n\tsd = &q->sdesc[q->pidx + (idx >> 1)];\n\tif (!(idx & 1)) {\n\t\tif (sd->coalesce.idx) {\n\t\t\tint i;\n\n\t\t\tfor (i = 0; i < sd->coalesce.idx; i++) {\n\t\t\t\trte_pktmbuf_free(sd->coalesce.mbuf[i]);\n\t\t\t\tsd->coalesce.mbuf[i] = NULL;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* store pointers to the mbuf and the sgl used in free_tx_desc.\n\t * each tx desc can hold two pointers corresponding to the value\n\t * of ETH_COALESCE_PKT_PER_DESC\n\t */\n\tsd->coalesce.mbuf[idx & 1] = mbuf;\n\tsd->coalesce.sgl[idx & 1] = (struct ulptx_sgl *)(cpl + 1);\n\tsd->coalesce.idx = (idx & 1) + 1;\n\n\t/* send the coaelsced work request if max reached */\n\tif (++q->coalesce.idx == ETH_COALESCE_PKT_NUM)\n\t\tship_tx_pkt_coalesce_wr(adap, txq);\n\treturn 0;\n}\n\n/**\n * t4_eth_xmit - add a packet to an Ethernet Tx queue\n * @txq: the egress queue\n * @mbuf: the packet\n *\n * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled.\n */\nint t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf)\n{\n\tconst struct port_info *pi;\n\tstruct cpl_tx_pkt_lso_core *lso;\n\tstruct adapter *adap;\n\tstruct rte_mbuf *m = mbuf;\n\tstruct fw_eth_tx_pkt_wr *wr;\n\tstruct cpl_tx_pkt_core *cpl;\n\tstruct tx_sw_desc *d;\n\tdma_addr_t addr[m->nb_segs];\n\tunsigned int flits, ndesc, cflits;\n\tint l3hdr_len, l4hdr_len, eth_xtra_len;\n\tint len, last_desc;\n\tint credits;\n\tu32 wr_mid;\n\tu64 cntrl, *end;\n\tbool v6;\n\n\t/* Reject xmit if queue is stopped */\n\tif (unlikely(txq->flags & EQ_STOPPED))\n\t\treturn -(EBUSY);\n\n\t/*\n\t * The chip min packet length is 10 octets but play safe and reject\n\t * anything shorter than an Ethernet header.\n\t */\n\tif (unlikely(m->pkt_len < ETHER_HDR_LEN)) {\nout_free:\n\t\trte_pktmbuf_free(m);\n\t\treturn 0;\n\t}\n\n\trte_prefetch0(&((&txq->q)->sdesc->mbuf->pool));\n\tpi = (struct port_info *)txq->eth_dev->data->dev_private;\n\tadap = pi->adapter;\n\n\tcntrl = F_TXPKT_L4CSUM_DIS | F_TXPKT_IPCSUM_DIS;\n\t/* align the end of coalesce WR to a 512 byte boundary */\n\ttxq->q.coalesce.max = (8 - (txq->q.pidx & 7)) * 8;\n\n\tif (!(m->ol_flags & PKT_TX_TCP_SEG)) {\n\t\tif (should_tx_packet_coalesce(txq, mbuf, &cflits, adap)) {\n\t\t\tif (unlikely(map_mbuf(mbuf, addr) < 0)) {\n\t\t\t\tdev_warn(adap, \"%s: mapping err for coalesce\\n\",\n\t\t\t\t\t __func__);\n\t\t\t\ttxq->stats.mapping_err++;\n\t\t\t\tgoto out_free;\n\t\t\t}\n\t\t\treturn tx_do_packet_coalesce(txq, mbuf, cflits, adap,\n\t\t\t\t\t\t pi, addr);\n\t\t} else {\n\t\t\treturn -EBUSY;\n\t\t}\n\t}\n\n\tif (txq->q.coalesce.idx)\n\t\tship_tx_pkt_coalesce_wr(adap, txq);\n\n\tflits = calc_tx_flits(m);\n\tndesc = flits_to_desc(flits);\n\tcredits = txq_avail(&txq->q) - ndesc;\n\n\tif (unlikely(credits < 0)) {\n\t\tdev_debug(adap, \"%s: Tx ring %u full; credits = %d\\n\",\n\t\t\t __func__, txq->q.cntxt_id, credits);\n\t\treturn -EBUSY;\n\t}\n\n\tif (unlikely(map_mbuf(m, addr) < 0)) {\n\t\ttxq->stats.mapping_err++;\n\t\tgoto out_free;\n\t}\n\n\twr_mid = V_FW_WR_LEN16(DIV_ROUND_UP(flits, 2));\n\tif (Q_IDXDIFF(&txq->q, equeidx) >= 64) {\n\t\ttxq->q.equeidx = txq->q.pidx;\n\t\twr_mid |= F_FW_WR_EQUEQ;\n\t}\n\n\twr = (void *)&txq->q.desc[txq->q.pidx];\n\twr->equiq_to_len16 = htonl(wr_mid);\n\twr->r3 = rte_cpu_to_be_64(0);\n\tend = (u64 *)wr + flits;\n\n\tlen = 0;\n\tlen += sizeof(*cpl);\n\tlso = (void *)(wr + 1);\n\tv6 = (m->ol_flags & PKT_TX_IPV6) != 0;\n\tl3hdr_len = m->l3_len;\n\tl4hdr_len = m->l4_len;\n\teth_xtra_len = m->l2_len - ETHER_HDR_LEN;\n\tlen += sizeof(*lso);\n\twr->op_immdlen = htonl(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |\n\t\t\t V_FW_WR_IMMDLEN(len));\n\tlso->lso_ctrl = htonl(V_LSO_OPCODE(CPL_TX_PKT_LSO) |\n\t\t\t F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |\n\t\t\t V_LSO_IPV6(v6) |\n\t\t\t V_LSO_ETHHDR_LEN(eth_xtra_len / 4) |\n\t\t\t V_LSO_IPHDR_LEN(l3hdr_len / 4) |\n\t\t\t V_LSO_TCPHDR_LEN(l4hdr_len / 4));\n\tlso->ipid_ofst = htons(0);\n\tlso->mss = htons(m->tso_segsz);\n\tlso->seqno_offset = htonl(0);\n\tif (is_t4(adap->params.chip))\n\t\tlso->len = htonl(m->pkt_len);\n\telse\n\t\tlso->len = htonl(V_LSO_T5_XFER_SIZE(m->pkt_len));\n\tcpl = (void *)(lso + 1);\n\tcntrl = V_TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |\n\t\t\t\t V_TXPKT_IPHDR_LEN(l3hdr_len) |\n\t\t\t\t V_TXPKT_ETHHDR_LEN(eth_xtra_len);\n\ttxq->stats.tso++;\n\ttxq->stats.tx_cso += m->tso_segsz;\n\n\tif (m->ol_flags & PKT_TX_VLAN_PKT) {\n\t\ttxq->stats.vlan_ins++;\n\t\tcntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->vlan_tci);\n\t}\n\n\tcpl->ctrl0 = htonl(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |\n\t\t\t V_TXPKT_INTF(pi->tx_chan) |\n\t\t\t V_TXPKT_PF(adap->pf));\n\tcpl->pack = htons(0);\n\tcpl->len = htons(m->pkt_len);\n\tcpl->ctrl1 = cpu_to_be64(cntrl);\n\n\ttxq->stats.pkts++;\n\ttxq->stats.tx_bytes += m->pkt_len;\n\tlast_desc = txq->q.pidx + ndesc - 1;\n\tif (last_desc >= (int)txq->q.size)\n\t\tlast_desc -= txq->q.size;\n\n\td = &txq->q.sdesc[last_desc];\n\tif (d->mbuf) {\n\t\trte_pktmbuf_free(d->mbuf);\n\t\td->mbuf = NULL;\n\t}\n\twrite_sgl(m, &txq->q, (struct ulptx_sgl *)(cpl + 1), end, 0,\n\t\t addr);\n\ttxq->q.sdesc[last_desc].mbuf = m;\n\ttxq->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)(cpl + 1);\n\ttxq_advance(&txq->q, ndesc);\n\tring_tx_db(adap, &txq->q);\n\treturn 0;\n}\n\n/**\n * alloc_ring - allocate resources for an SGE descriptor ring\n * @dev: the PCI device's core device\n * @nelem: the number of descriptors\n * @elem_size: the size of each descriptor\n * @sw_size: the size of the SW state associated with each ring element\n * @phys: the physical address of the allocated ring\n * @metadata: address of the array holding the SW state for the ring\n * @stat_size: extra space in HW ring for status information\n * @node: preferred node for memory allocations\n *\n * Allocates resources for an SGE descriptor ring, such as Tx queues,\n * free buffer lists, or response queues. Each SGE ring requires\n * space for its HW descriptors plus, optionally, space for the SW state\n * associated with each HW entry (the metadata). The function returns\n * three values: the virtual address for the HW ring (the return value\n * of the function), the bus address of the HW ring, and the address\n * of the SW ring.\n */\nstatic void *alloc_ring(size_t nelem, size_t elem_size,\n\t\t\tsize_t sw_size, dma_addr_t *phys, void *metadata,\n\t\t\tsize_t stat_size, __rte_unused uint16_t queue_id,\n\t\t\tint socket_id, const char *z_name,\n\t\t\tconst char *z_name_sw)\n{\n\tsize_t len = CXGBE_MAX_RING_DESC_SIZE * elem_size + stat_size;\n\tconst struct rte_memzone *tz;\n\tvoid *s = NULL;\n\n\tdev_debug(adapter, \"%s: nelem = %zu; elem_size = %zu; sw_size = %zu; \"\n\t\t \"stat_size = %zu; queue_id = %u; socket_id = %d; z_name = %s;\"\n\t\t \" z_name_sw = %s\\n\", __func__, nelem, elem_size, sw_size,\n\t\t stat_size, queue_id, socket_id, z_name, z_name_sw);\n\n\ttz = rte_memzone_lookup(z_name);\n\tif (tz) {\n\t\tdev_debug(adapter, \"%s: tz exists...returning existing..\\n\",\n\t\t\t __func__);\n\t\tgoto alloc_sw_ring;\n\t}\n\n\t/*\n\t * Allocate TX/RX ring hardware descriptors. A memzone large enough to\n\t * handle the maximum ring size is allocated in order to allow for\n\t * resizing in later calls to the queue setup function.\n\t */\n\ttz = rte_memzone_reserve_aligned(z_name, len, socket_id, 0, 4096);\n\tif (!tz)\n\t\treturn NULL;\n\nalloc_sw_ring:\n\tmemset(tz->addr, 0, len);\n\tif (sw_size) {\n\t\ts = rte_zmalloc_socket(z_name_sw, nelem * sw_size,\n\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n\n\t\tif (!s) {\n\t\t\tdev_err(adapter, \"%s: failed to get sw_ring memory\\n\",\n\t\t\t\t__func__);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\tif (metadata)\n\t\t*(void **)metadata = s;\n\n\t*phys = (uint64_t)tz->phys_addr;\n\treturn tz->addr;\n}\n\n/**\n * t4_pktgl_to_mbuf_usembufs - build an mbuf from a packet gather list\n * @gl: the gather list\n *\n * Builds an mbuf from the given packet gather list. Returns the mbuf or\n * %NULL if mbuf allocation failed.\n */\nstatic struct rte_mbuf *t4_pktgl_to_mbuf_usembufs(const struct pkt_gl *gl)\n{\n\t/*\n\t * If there's only one mbuf fragment, just return that.\n\t */\n\tif (likely(gl->nfrags == 1))\n\t\treturn gl->mbufs[0];\n\n\treturn NULL;\n}\n\n/**\n * t4_pktgl_to_mbuf - build an mbuf from a packet gather list\n * @gl: the gather list\n *\n * Builds an mbuf from the given packet gather list. Returns the mbuf or\n * %NULL if mbuf allocation failed.\n */\nstatic struct rte_mbuf *t4_pktgl_to_mbuf(const struct pkt_gl *gl)\n{\n\treturn t4_pktgl_to_mbuf_usembufs(gl);\n}\n\n#define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \\\n\t((dma_addr_t) ((mb)->buf_physaddr + (mb)->data_off))\n\n/**\n * t4_ethrx_handler - process an ingress ethernet packet\n * @q: the response queue that received the packet\n * @rsp: the response queue descriptor holding the RX_PKT message\n * @si: the gather list of packet fragments\n *\n * Process an ingress ethernet packet and deliver it to the stack.\n */\nint t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,\n\t\t const struct pkt_gl *si)\n{\n\tstruct rte_mbuf *mbuf;\n\tconst struct cpl_rx_pkt *pkt;\n\tconst struct rss_header *rss_hdr;\n\tbool csum_ok;\n\tstruct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);\n\n\trss_hdr = (const void *)rsp;\n\tpkt = (const void *)&rsp[1];\n\tcsum_ok = pkt->csum_calc && !pkt->err_vec;\n\n\tmbuf = t4_pktgl_to_mbuf(si);\n\tif (unlikely(!mbuf)) {\n\t\trxq->stats.rx_drops++;\n\t\treturn 0;\n\t}\n\n\tmbuf->port = pkt->iff;\n\tif (pkt->l2info & htonl(F_RXF_IP)) {\n#ifdef RTE_NEXT_ABI\n\t\tmbuf->packet_type = RTE_PTYPE_L3_IPV4;\n#else\n\t\tmbuf->ol_flags |= PKT_RX_IPV4_HDR;\n#endif\n\t\tif (unlikely(!csum_ok))\n\t\t\tmbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;\n\n\t\tif ((pkt->l2info & htonl(F_RXF_UDP | F_RXF_TCP)) && !csum_ok)\n\t\t\tmbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;\n\t} else if (pkt->l2info & htonl(F_RXF_IP6)) {\n#ifdef RTE_NEXT_ABI\n\t\tmbuf->packet_type = RTE_PTYPE_L3_IPV6;\n#else\n\t\tmbuf->ol_flags |= PKT_RX_IPV6_HDR;\n#endif\n\t}\n\n\tmbuf->port = pkt->iff;\n\n\tif (!rss_hdr->filter_tid && rss_hdr->hash_type) {\n\t\tmbuf->ol_flags |= PKT_RX_RSS_HASH;\n\t\tmbuf->hash.rss = ntohl(rss_hdr->hash_val);\n\t}\n\n\tif (pkt->vlan_ex) {\n\t\tmbuf->ol_flags |= PKT_RX_VLAN_PKT;\n\t\tmbuf->vlan_tci = ntohs(pkt->vlan);\n\t}\n\trxq->stats.pkts++;\n\trxq->stats.rx_bytes += mbuf->pkt_len;\n\n\treturn 0;\n}\n\n/**\n * is_new_response - check if a response is newly written\n * @r: the response descriptor\n * @q: the response queue\n *\n * Returns true if a response descriptor contains a yet unprocessed\n * response.\n */\nstatic inline bool is_new_response(const struct rsp_ctrl *r,\n\t\t\t\t const struct sge_rspq *q)\n{\n\treturn (r->u.type_gen >> S_RSPD_GEN) == q->gen;\n}\n\n#define CXGB4_MSG_AN ((void *)1)\n\n/**\n * rspq_next - advance to the next entry in a response queue\n * @q: the queue\n *\n * Updates the state of a response queue to advance it to the next entry.\n */\nstatic inline void rspq_next(struct sge_rspq *q)\n{\n\tq->cur_desc = (const __be64 *)((const char *)q->cur_desc + q->iqe_len);\n\tif (unlikely(++q->cidx == q->size)) {\n\t\tq->cidx = 0;\n\t\tq->gen ^= 1;\n\t\tq->cur_desc = q->desc;\n\t}\n}\n\n/**\n * process_responses - process responses from an SGE response queue\n * @q: the ingress queue to process\n * @budget: how many responses can be processed in this round\n * @rx_pkts: mbuf to put the pkts\n *\n * Process responses from an SGE response queue up to the supplied budget.\n * Responses include received packets as well as control messages from FW\n * or HW.\n *\n * Additionally choose the interrupt holdoff time for the next interrupt\n * on this queue. If the system is under memory shortage use a fairly\n * long delay to help recovery.\n */\nstatic int process_responses(struct sge_rspq *q, int budget,\n\t\t\t struct rte_mbuf **rx_pkts)\n{\n\tint ret = 0, rsp_type;\n\tint budget_left = budget;\n\tconst struct rsp_ctrl *rc;\n\tstruct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);\n\n\twhile (likely(budget_left)) {\n\t\trc = (const struct rsp_ctrl *)\n\t\t ((const char *)q->cur_desc + (q->iqe_len - sizeof(*rc)));\n\n\t\tif (!is_new_response(rc, q))\n\t\t\tbreak;\n\n\t\t/*\n\t\t * Ensure response has been read\n\t\t */\n\t\trmb();\n\t\trsp_type = G_RSPD_TYPE(rc->u.type_gen);\n\n\t\tif (likely(rsp_type == X_RSPD_TYPE_FLBUF)) {\n\t\t\tconst struct rx_sw_desc *rsd =\n\t\t\t\t\t\t&rxq->fl.sdesc[rxq->fl.cidx];\n\t\t\tconst struct rss_header *rss_hdr =\n\t\t\t\t\t\t(const void *)q->cur_desc;\n\t\t\tconst struct cpl_rx_pkt *cpl =\n\t\t\t\t\t\t(const void *)&q->cur_desc[1];\n\t\t\tbool csum_ok = cpl->csum_calc && !cpl->err_vec;\n\t\t\tstruct rte_mbuf *pkt;\n\t\t\tu32 len = ntohl(rc->pldbuflen_qid);\n\n\t\t\tBUG_ON(!(len & F_RSPD_NEWBUF));\n\t\t\tpkt = rsd->buf;\n\t\t\tpkt->data_len = G_RSPD_LEN(len);\n\t\t\tpkt->pkt_len = pkt->data_len;\n\t\t\tunmap_rx_buf(&rxq->fl);\n\n\t\t\tif (cpl->l2info & htonl(F_RXF_IP)) {\n#ifdef RTE_NEXT_ABI\n\t\t\t\tpkt->packet_type = RTE_PTYPE_L3_IPV4;\n#else\n\t\t\t\tpkt->ol_flags |= PKT_RX_IPV4_HDR;\n#endif\n\t\t\t\tif (unlikely(!csum_ok))\n\t\t\t\t\tpkt->ol_flags |= PKT_RX_IP_CKSUM_BAD;\n\n\t\t\t\tif ((cpl->l2info &\n\t\t\t\t htonl(F_RXF_UDP | F_RXF_TCP)) && !csum_ok)\n\t\t\t\t\tpkt->ol_flags |= PKT_RX_L4_CKSUM_BAD;\n\t\t\t} else if (cpl->l2info & htonl(F_RXF_IP6)) {\n#ifdef RTE_NEXT_ABI\n\t\t\t\tpkt->packet_type = RTE_PTYPE_L3_IPV6;\n#else\n\t\t\t\tpkt->ol_flags |= PKT_RX_IPV6_HDR;\n#endif\n\t\t\t}\n\n\t\t\tif (!rss_hdr->filter_tid && rss_hdr->hash_type) {\n\t\t\t\tpkt->ol_flags |= PKT_RX_RSS_HASH;\n\t\t\t\tpkt->hash.rss = ntohl(rss_hdr->hash_val);\n\t\t\t}\n\n\t\t\tif (cpl->vlan_ex) {\n\t\t\t\tpkt->ol_flags |= PKT_RX_VLAN_PKT;\n\t\t\t\tpkt->vlan_tci = ntohs(cpl->vlan);\n\t\t\t}\n\t\t\trxq->stats.pkts++;\n\t\t\trxq->stats.rx_bytes += pkt->pkt_len;\n\t\t\trx_pkts[budget - budget_left] = pkt;\n\t\t} else if (likely(rsp_type == X_RSPD_TYPE_CPL)) {\n\t\t\tret = q->handler(q, q->cur_desc, NULL);\n\t\t} else {\n\t\t\tret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN);\n\t\t}\n\n\t\tif (unlikely(ret)) {\n\t\t\t/* couldn't process descriptor, back off for recovery */\n\t\t\tq->next_intr_params = V_QINTR_TIMER_IDX(NOMEM_TMR_IDX);\n\t\t\tbreak;\n\t\t}\n\n\t\trspq_next(q);\n\t\tbudget_left--;\n\n\t\tif (R_IDXDIFF(q, gts_idx) >= 64) {\n\t\t\tunsigned int cidx_inc = R_IDXDIFF(q, gts_idx);\n\t\t\tunsigned int params;\n\t\t\tu32 val;\n\n\t\t\t__refill_fl(q->adapter, &rxq->fl);\n\t\t\tparams = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);\n\t\t\tq->next_intr_params = params;\n\t\t\tval = V_CIDXINC(cidx_inc) | V_SEINTARM(params);\n\n\t\t\tif (unlikely(!q->bar2_addr))\n\t\t\t\tt4_write_reg(q->adapter, MYPF_REG(A_SGE_PF_GTS),\n\t\t\t\t\t val |\n\t\t\t\t\t V_INGRESSQID((u32)q->cntxt_id));\n\t\t\telse {\n\t\t\t\twritel(val | V_INGRESSQID(q->bar2_qid),\n\t\t\t\t (void *)((uintptr_t)q->bar2_addr +\n\t\t\t\t SGE_UDB_GTS));\n\t\t\t\t/*\n\t\t\t\t * This Write memory Barrier will force the\n\t\t\t\t * write to the User Doorbell area to be\n\t\t\t\t * flushed.\n\t\t\t\t */\n\t\t\t\twmb();\n\t\t\t}\n\t\t\tq->gts_idx = q->cidx;\n\t\t}\n\t}\n\n\t/*\n\t * If this is a Response Queue with an associated Free List and\n\t * there's room for another chunk of new Free List buffer pointers,\n\t * refill the Free List.\n\t */\n\n\tif (q->offset >= 0 && fl_cap(&rxq->fl) - rxq->fl.avail >= 64)\n\t\t__refill_fl(q->adapter, &rxq->fl);\n\n\treturn budget - budget_left;\n}\n\nint cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,\n\t unsigned int budget, unsigned int *work_done)\n{\n\tint err = 0;\n\n\t*work_done = process_responses(q, budget, rx_pkts);\n\treturn err;\n}\n\n/**\n * bar2_address - return the BAR2 address for an SGE Queue's Registers\n * @adapter: the adapter\n * @qid: the SGE Queue ID\n * @qtype: the SGE Queue Type (Egress or Ingress)\n * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues\n *\n * Returns the BAR2 address for the SGE Queue Registers associated with\n * @qid. If BAR2 SGE Registers aren't available, returns NULL. Also\n * returns the BAR2 Queue ID to be used with writes to the BAR2 SGE\n * Queue Registers. If the BAR2 Queue ID is 0, then \"Inferred Queue ID\"\n * Registers are supported (e.g. the Write Combining Doorbell Buffer).\n */\nstatic void __iomem *bar2_address(struct adapter *adapter, unsigned int qid,\n\t\t\t\t enum t4_bar2_qtype qtype,\n\t\t\t\t unsigned int *pbar2_qid)\n{\n\tu64 bar2_qoffset;\n\tint ret;\n\n\tret = t4_bar2_sge_qregs(adapter, qid, qtype, &bar2_qoffset, pbar2_qid);\n\tif (ret)\n\t\treturn NULL;\n\n\treturn adapter->bar2 + bar2_qoffset;\n}\n\nint t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq)\n{\n\tstruct sge_eth_rxq *rxq = container_of(rq, struct sge_eth_rxq, rspq);\n\tunsigned int fl_id = rxq->fl.size ? rxq->fl.cntxt_id : 0xffff;\n\n\treturn t4_iq_start_stop(adap, adap->mbox, true, adap->pf, 0,\n\t\t\t\trq->cntxt_id, fl_id, 0xffff);\n}\n\nint t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq)\n{\n\tstruct sge_eth_rxq *rxq = container_of(rq, struct sge_eth_rxq, rspq);\n\tunsigned int fl_id = rxq->fl.size ? rxq->fl.cntxt_id : 0xffff;\n\n\treturn t4_iq_start_stop(adap, adap->mbox, false, adap->pf, 0,\n\t\t\t\trq->cntxt_id, fl_id, 0xffff);\n}\n\n/*\n * @intr_idx: MSI/MSI-X vector if >=0, -(absolute qid + 1) if < 0\n * @cong: < 0 -> no congestion feedback, >= 0 -> congestion channel map\n */\nint t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,\n\t\t struct rte_eth_dev *eth_dev, int intr_idx,\n\t\t struct sge_fl *fl, rspq_handler_t hnd, int cong,\n\t\t struct rte_mempool *mp, int queue_id, int socket_id)\n{\n\tint ret, flsz = 0;\n\tstruct fw_iq_cmd c;\n\tstruct sge *s = &adap->sge;\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tchar z_name[RTE_MEMZONE_NAMESIZE];\n\tchar z_name_sw[RTE_MEMZONE_NAMESIZE];\n\tunsigned int nb_refill;\n\n\t/* Size needs to be multiple of 16, including status entry. */\n\tiq->size = cxgbe_roundup(iq->size, 16);\n\n\tsnprintf(z_name, sizeof(z_name), \"%s_%s_%d_%d\",\n\t\t eth_dev->driver->pci_drv.name, fwevtq ? \"fwq_ring\" : \"rx_ring\",\n\t\t eth_dev->data->port_id, queue_id);\n\tsnprintf(z_name_sw, sizeof(z_name_sw), \"%s_sw_ring\", z_name);\n\n\tiq->desc = alloc_ring(iq->size, iq->iqe_len, 0, &iq->phys_addr, NULL, 0,\n\t\t\t queue_id, socket_id, z_name, z_name_sw);\n\tif (!iq->desc)\n\t\treturn -ENOMEM;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_vfn = htonl(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |\n\t\t\t F_FW_CMD_WRITE | F_FW_CMD_EXEC |\n\t\t\t V_FW_IQ_CMD_PFN(adap->pf) | V_FW_IQ_CMD_VFN(0));\n\tc.alloc_to_len16 = htonl(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |\n\t\t\t\t (sizeof(c) / 16));\n\tc.type_to_iqandstindex =\n\t\thtonl(V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |\n\t\t V_FW_IQ_CMD_IQASYNCH(fwevtq) |\n\t\t V_FW_IQ_CMD_VIID(pi->viid) |\n\t\t V_FW_IQ_CMD_IQANDST(intr_idx < 0) |\n\t\t V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT) |\n\t\t V_FW_IQ_CMD_IQANDSTINDEX(intr_idx >= 0 ? intr_idx :\n\t\t\t\t\t\t\t -intr_idx - 1));\n\tc.iqdroprss_to_iqesize =\n\t\thtons(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |\n\t\t F_FW_IQ_CMD_IQGTSMODE |\n\t\t V_FW_IQ_CMD_IQINTCNTTHRESH(iq->pktcnt_idx) |\n\t\t V_FW_IQ_CMD_IQESIZE(ilog2(iq->iqe_len) - 4));\n\tc.iqsize = htons(iq->size);\n\tc.iqaddr = cpu_to_be64(iq->phys_addr);\n\tif (cong >= 0)\n\t\tc.iqns_to_fl0congen = htonl(F_FW_IQ_CMD_IQFLINTCONGEN);\n\n\tif (fl) {\n\t\tstruct sge_eth_rxq *rxq = container_of(fl, struct sge_eth_rxq,\n\t\t\t\t\t\t fl);\n\t\tenum chip_type chip = (enum chip_type)CHELSIO_CHIP_VERSION(\n\t\t\t\tadap->params.chip);\n\n\t\t/*\n\t\t * Allocate the ring for the hardware free list (with space\n\t\t * for its status page) along with the associated software\n\t\t * descriptor ring. The free list size needs to be a multiple\n\t\t * of the Egress Queue Unit and at least 2 Egress Units larger\n\t\t * than the SGE's Egress Congrestion Threshold\n\t\t * (fl_starve_thres - 1).\n\t\t */\n\t\tif (fl->size < s->fl_starve_thres - 1 + 2 * 8)\n\t\t\tfl->size = s->fl_starve_thres - 1 + 2 * 8;\n\t\tfl->size = cxgbe_roundup(fl->size, 8);\n\n\t\tsnprintf(z_name, sizeof(z_name), \"%s_%s_%d_%d\",\n\t\t\t eth_dev->driver->pci_drv.name,\n\t\t\t fwevtq ? \"fwq_ring\" : \"fl_ring\",\n\t\t\t eth_dev->data->port_id, queue_id);\n\t\tsnprintf(z_name_sw, sizeof(z_name_sw), \"%s_sw_ring\", z_name);\n\n\t\tfl->desc = alloc_ring(fl->size, sizeof(__be64),\n\t\t\t\t sizeof(struct rx_sw_desc),\n\t\t\t\t &fl->addr, &fl->sdesc, s->stat_len,\n\t\t\t\t queue_id, socket_id, z_name, z_name_sw);\n\n\t\tif (!fl->desc)\n\t\t\tgoto fl_nomem;\n\n\t\tflsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);\n\t\tc.iqns_to_fl0congen |=\n\t\t\thtonl(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |\n\t\t\t (unlikely(rxq->usembufs) ?\n\t\t\t 0 : F_FW_IQ_CMD_FL0PACKEN) |\n\t\t\t F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |\n\t\t\t F_FW_IQ_CMD_FL0PADEN);\n\t\tif (cong >= 0)\n\t\t\tc.iqns_to_fl0congen |=\n\t\t\t\thtonl(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |\n\t\t\t\t F_FW_IQ_CMD_FL0CONGCIF |\n\t\t\t\t F_FW_IQ_CMD_FL0CONGEN);\n\n\t\t/* In T6, for egress queue type FL there is internal overhead\n\t\t * of 16B for header going into FLM module.\n\t\t * Hence maximum allowed burst size will be 448 bytes.\n\t\t */\n\t\tc.fl0dcaen_to_fl0cidxfthresh =\n\t\t\thtons(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) |\n\t\t\t V_FW_IQ_CMD_FL0FBMAX((chip <= CHELSIO_T5) ?\n\t\t\t X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));\n\t\tc.fl0size = htons(flsz);\n\t\tc.fl0addr = cpu_to_be64(fl->addr);\n\t}\n\n\tret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);\n\tif (ret)\n\t\tgoto err;\n\n\tiq->cur_desc = iq->desc;\n\tiq->cidx = 0;\n\tiq->gts_idx = 0;\n\tiq->gen = 1;\n\tiq->next_intr_params = iq->intr_params;\n\tiq->cntxt_id = ntohs(c.iqid);\n\tiq->abs_id = ntohs(c.physiqid);\n\tiq->bar2_addr = bar2_address(adap, iq->cntxt_id, T4_BAR2_QTYPE_INGRESS,\n\t\t\t\t &iq->bar2_qid);\n\tiq->size--; /* subtract status entry */\n\tiq->eth_dev = eth_dev;\n\tiq->handler = hnd;\n\tiq->port_id = pi->port_id;\n\tiq->mb_pool = mp;\n\n\t/* set offset to -1 to distinguish ingress queues without FL */\n\tiq->offset = fl ? 0 : -1;\n\n\tif (fl) {\n\t\tfl->cntxt_id = ntohs(c.fl0id);\n\t\tfl->avail = 0;\n\t\tfl->pend_cred = 0;\n\t\tfl->pidx = 0;\n\t\tfl->cidx = 0;\n\t\tfl->alloc_failed = 0;\n\n\t\t/*\n\t\t * Note, we must initialize the BAR2 Free List User Doorbell\n\t\t * information before refilling the Free List!\n\t\t */\n\t\tfl->bar2_addr = bar2_address(adap, fl->cntxt_id,\n\t\t\t\t\t T4_BAR2_QTYPE_EGRESS,\n\t\t\t\t\t &fl->bar2_qid);\n\n\t\tnb_refill = refill_fl(adap, fl, fl_cap(fl));\n\t\tif (nb_refill != fl_cap(fl)) {\n\t\t\tret = -ENOMEM;\n\t\t\tdev_err(adap, \"%s: mbuf alloc failed with error: %d\\n\",\n\t\t\t\t__func__, ret);\n\t\t\tgoto refill_fl_err;\n\t\t}\n\t}\n\n\t/*\n\t * For T5 and later we attempt to set up the Congestion Manager values\n\t * of the new RX Ethernet Queue. This should really be handled by\n\t * firmware because it's more complex than any host driver wants to\n\t * get involved with and it's different per chip and this is almost\n\t * certainly wrong. Formware would be wrong as well, but it would be\n\t * a lot easier to fix in one place ... For now we do something very\n\t * simple (and hopefully less wrong).\n\t */\n\tif (!is_t4(adap->params.chip) && cong >= 0) {\n\t\tu32 param, val;\n\t\tint i;\n\n\t\tparam = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |\n\t\t\t V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |\n\t\t\t V_FW_PARAMS_PARAM_YZ(iq->cntxt_id));\n\t\tif (cong == 0) {\n\t\t\tval = V_CONMCTXT_CNGTPMODE(X_CONMCTXT_CNGTPMODE_QUEUE);\n\t\t} else {\n\t\t\tval = V_CONMCTXT_CNGTPMODE(\n\t\t\t\t\tX_CONMCTXT_CNGTPMODE_CHANNEL);\n\t\t\tfor (i = 0; i < 4; i++) {\n\t\t\t\tif (cong & (1 << i))\n\t\t\t\t\tval |= V_CONMCTXT_CNGCHMAP(1 <<\n\t\t\t\t\t\t\t\t (i << 2));\n\t\t\t}\n\t\t}\n\t\tret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,\n\t\t\t\t ¶m, &val);\n\t\tif (ret)\n\t\t\tdev_warn(adap->pdev_dev, \"Failed to set Congestion Manager Context for Ingress Queue %d: %d\\n\",\n\t\t\t\t iq->cntxt_id, -ret);\n\t}\n\n\treturn 0;\n\nrefill_fl_err:\n\tt4_iq_free(adap, adap->mbox, adap->pf, 0, FW_IQ_TYPE_FL_INT_CAP,\n\t\t iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff);\nfl_nomem:\n\tret = -ENOMEM;\nerr:\n\tiq->cntxt_id = 0;\n\tiq->abs_id = 0;\n\tif (iq->desc)\n\t\tiq->desc = NULL;\n\n\tif (fl && fl->desc) {\n\t\trte_free(fl->sdesc);\n\t\tfl->cntxt_id = 0;\n\t\tfl->sdesc = NULL;\n\t\tfl->desc = NULL;\n\t}\n\treturn ret;\n}\n\nstatic void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id)\n{\n\tq->cntxt_id = id;\n\tq->bar2_addr = bar2_address(adap, q->cntxt_id, T4_BAR2_QTYPE_EGRESS,\n\t\t\t\t &q->bar2_qid);\n\tq->cidx = 0;\n\tq->pidx = 0;\n\tq->dbidx = 0;\n\tq->in_use = 0;\n\tq->equeidx = 0;\n\tq->coalesce.idx = 0;\n\tq->coalesce.len = 0;\n\tq->coalesce.flits = 0;\n\tq->last_coal_idx = 0;\n\tq->last_pidx = 0;\n\tq->stat = (void *)&q->desc[q->size];\n}\n\nint t4_sge_eth_txq_start(struct sge_eth_txq *txq)\n{\n\t/*\n\t * TODO: For flow-control, queue may be stopped waiting to reclaim\n\t * credits.\n\t * Ensure queue is in EQ_STOPPED state before starting it.\n\t */\n\tif (!(txq->flags & EQ_STOPPED))\n\t\treturn -(EBUSY);\n\n\ttxq->flags &= ~EQ_STOPPED;\n\n\treturn 0;\n}\n\nint t4_sge_eth_txq_stop(struct sge_eth_txq *txq)\n{\n\ttxq->flags |= EQ_STOPPED;\n\n\treturn 0;\n}\n\nint t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,\n\t\t\t struct rte_eth_dev *eth_dev, uint16_t queue_id,\n\t\t\t unsigned int iqid, int socket_id)\n{\n\tint ret, nentries;\n\tstruct fw_eq_eth_cmd c;\n\tstruct sge *s = &adap->sge;\n\tstruct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);\n\tchar z_name[RTE_MEMZONE_NAMESIZE];\n\tchar z_name_sw[RTE_MEMZONE_NAMESIZE];\n\n\t/* Add status entries */\n\tnentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);\n\n\tsnprintf(z_name, sizeof(z_name), \"%s_%s_%d_%d\",\n\t\t eth_dev->driver->pci_drv.name, \"tx_ring\",\n\t\t eth_dev->data->port_id, queue_id);\n\tsnprintf(z_name_sw, sizeof(z_name_sw), \"%s_sw_ring\", z_name);\n\n\ttxq->q.desc = alloc_ring(txq->q.size, sizeof(struct tx_desc),\n\t\t\t\t sizeof(struct tx_sw_desc), &txq->q.phys_addr,\n\t\t\t\t &txq->q.sdesc, s->stat_len, queue_id,\n\t\t\t\t socket_id, z_name, z_name_sw);\n\tif (!txq->q.desc)\n\t\treturn -ENOMEM;\n\n\tmemset(&c, 0, sizeof(c));\n\tc.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |\n\t\t\t F_FW_CMD_WRITE | F_FW_CMD_EXEC |\n\t\t\t V_FW_EQ_ETH_CMD_PFN(adap->pf) |\n\t\t\t V_FW_EQ_ETH_CMD_VFN(0));\n\tc.alloc_to_len16 = htonl(F_FW_EQ_ETH_CMD_ALLOC |\n\t\t\t\t F_FW_EQ_ETH_CMD_EQSTART | (sizeof(c) / 16));\n\tc.autoequiqe_to_viid = htonl(F_FW_EQ_ETH_CMD_AUTOEQUEQE |\n\t\t\t\t V_FW_EQ_ETH_CMD_VIID(pi->viid));\n\tc.fetchszm_to_iqid =\n\t\thtonl(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |\n\t\t V_FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) |\n\t\t F_FW_EQ_ETH_CMD_FETCHRO | V_FW_EQ_ETH_CMD_IQID(iqid));\n\tc.dcaen_to_eqsize =\n\t\thtonl(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |\n\t\t V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |\n\t\t V_FW_EQ_ETH_CMD_EQSIZE(nentries));\n\tc.eqaddr = rte_cpu_to_be_64(txq->q.phys_addr);\n\n\tret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);\n\tif (ret) {\n\t\trte_free(txq->q.sdesc);\n\t\ttxq->q.sdesc = NULL;\n\t\ttxq->q.desc = NULL;\n\t\treturn ret;\n\t}\n\n\tinit_txq(adap, &txq->q, G_FW_EQ_ETH_CMD_EQID(ntohl(c.eqid_pkd)));\n\ttxq->stats.tso = 0;\n\ttxq->stats.pkts = 0;\n\ttxq->stats.tx_cso = 0;\n\ttxq->stats.coal_wr = 0;\n\ttxq->stats.vlan_ins = 0;\n\ttxq->stats.tx_bytes = 0;\n\ttxq->stats.coal_pkts = 0;\n\ttxq->stats.mapping_err = 0;\n\ttxq->flags |= EQ_STOPPED;\n\ttxq->eth_dev = eth_dev;\n\tt4_os_lock_init(&txq->txq_lock);\n\treturn 0;\n}\n\nstatic void free_txq(struct sge_txq *q)\n{\n\tq->cntxt_id = 0;\n\tq->sdesc = NULL;\n\tq->desc = NULL;\n}\n\nstatic void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq,\n\t\t\t struct sge_fl *fl)\n{\n\tunsigned int fl_id = fl ? fl->cntxt_id : 0xffff;\n\n\tt4_iq_free(adap, adap->mbox, adap->pf, 0, FW_IQ_TYPE_FL_INT_CAP,\n\t\t rq->cntxt_id, fl_id, 0xffff);\n\trq->cntxt_id = 0;\n\trq->abs_id = 0;\n\trq->desc = NULL;\n\n\tif (fl) {\n\t\tfree_rx_bufs(fl, fl->avail);\n\t\trte_free(fl->sdesc);\n\t\tfl->sdesc = NULL;\n\t\tfl->cntxt_id = 0;\n\t\tfl->desc = NULL;\n\t}\n}\n\n/*\n * Clear all queues of the port\n *\n * Note: This function must only be called after rx and tx path\n * of the port have been disabled.\n */\nvoid t4_sge_eth_clear_queues(struct port_info *pi)\n{\n\tint i;\n\tstruct adapter *adap = pi->adapter;\n\tstruct sge_eth_rxq *rxq = &adap->sge.ethrxq[pi->first_qset];\n\tstruct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];\n\n\tfor (i = 0; i < pi->n_rx_qsets; i++, rxq++) {\n\t\tif (rxq->rspq.desc)\n\t\t\tt4_sge_eth_rxq_stop(adap, &rxq->rspq);\n\t}\n\tfor (i = 0; i < pi->n_tx_qsets; i++, txq++) {\n\t\tif (txq->q.desc) {\n\t\t\tstruct sge_txq *q = &txq->q;\n\n\t\t\tt4_sge_eth_txq_stop(txq);\n\t\t\treclaim_completed_tx(q);\n\t\t\tfree_tx_desc(q, q->size);\n\t\t\tq->equeidx = q->pidx;\n\t\t}\n\t}\n}\n\nvoid t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq)\n{\n\tif (rxq->rspq.desc) {\n\t\tt4_sge_eth_rxq_stop(adap, &rxq->rspq);\n\t\tfree_rspq_fl(adap, &rxq->rspq, rxq->fl.size ? &rxq->fl : NULL);\n\t}\n}\n\nvoid t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq)\n{\n\tif (txq->q.desc) {\n\t\tt4_sge_eth_txq_stop(txq);\n\t\treclaim_completed_tx(&txq->q);\n\t\tt4_eth_eq_free(adap, adap->mbox, adap->pf, 0, txq->q.cntxt_id);\n\t\tfree_tx_desc(&txq->q, txq->q.size);\n\t\trte_free(txq->q.sdesc);\n\t\tfree_txq(&txq->q);\n\t}\n}\n\nvoid t4_sge_tx_monitor_start(struct adapter *adap)\n{\n\trte_eal_alarm_set(50, tx_timer_cb, (void *)adap);\n}\n\nvoid t4_sge_tx_monitor_stop(struct adapter *adap)\n{\n\trte_eal_alarm_cancel(tx_timer_cb, (void *)adap);\n}\n\n/**\n * t4_free_sge_resources - free SGE resources\n * @adap: the adapter\n *\n * Frees resources used by the SGE queue sets.\n */\nvoid t4_free_sge_resources(struct adapter *adap)\n{\n\tint i;\n\tstruct sge_eth_rxq *rxq = &adap->sge.ethrxq[0];\n\tstruct sge_eth_txq *txq = &adap->sge.ethtxq[0];\n\n\t/* clean up Ethernet Tx/Rx queues */\n\tfor (i = 0; i < adap->sge.max_ethqsets; i++, rxq++, txq++) {\n\t\t/* Free only the queues allocated */\n\t\tif (rxq->rspq.desc) {\n\t\t\tt4_sge_eth_rxq_release(adap, rxq);\n\t\t\trxq->rspq.eth_dev = NULL;\n\t\t}\n\t\tif (txq->q.desc) {\n\t\t\tt4_sge_eth_txq_release(adap, txq);\n\t\t\ttxq->eth_dev = NULL;\n\t\t}\n\t}\n\n\tif (adap->sge.fw_evtq.desc)\n\t\tfree_rspq_fl(adap, &adap->sge.fw_evtq, NULL);\n}\n\n/**\n * t4_sge_init - initialize SGE\n * @adap: the adapter\n *\n * Performs SGE initialization needed every time after a chip reset.\n * We do not initialize any of the queues here, instead the driver\n * top-level must request those individually.\n *\n * Called in two different modes:\n *\n * 1. Perform actual hardware initialization and record hard-coded\n * parameters which were used. This gets used when we're the\n * Master PF and the Firmware Configuration File support didn't\n * work for some reason.\n *\n * 2. We're not the Master PF or initialization was performed with\n * a Firmware Configuration File. In this case we need to grab\n * any of the SGE operating parameters that we need to have in\n * order to do our job and make sure we can live with them ...\n */\nstatic int t4_sge_init_soft(struct adapter *adap)\n{\n\tstruct sge *s = &adap->sge;\n\tu32 fl_small_pg, fl_large_pg, fl_small_mtu, fl_large_mtu;\n\tu32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5;\n\tu32 ingress_rx_threshold;\n\n\t/*\n\t * Verify that CPL messages are going to the Ingress Queue for\n\t * process_responses() and that only packet data is going to the\n\t * Free Lists.\n\t */\n\tif ((t4_read_reg(adap, A_SGE_CONTROL) & F_RXPKTCPLMODE) !=\n\t V_RXPKTCPLMODE(X_RXPKTCPLMODE_SPLIT)) {\n\t\tdev_err(adap, \"bad SGE CPL MODE\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/*\n\t * Validate the Host Buffer Register Array indices that we want to\n\t * use ...\n\t *\n\t * XXX Note that we should really read through the Host Buffer Size\n\t * XXX register array and find the indices of the Buffer Sizes which\n\t * XXX meet our needs!\n\t */\n#define READ_FL_BUF(x) \\\n\tt4_read_reg(adap, A_SGE_FL_BUFFER_SIZE0 + (x) * sizeof(u32))\n\n\tfl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF);\n\tfl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF);\n\tfl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF);\n\tfl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF);\n\n\t/*\n\t * We only bother using the Large Page logic if the Large Page Buffer\n\t * is larger than our Page Size Buffer.\n\t */\n\tif (fl_large_pg <= fl_small_pg)\n\t\tfl_large_pg = 0;\n\n#undef READ_FL_BUF\n\n\t/*\n\t * The Page Size Buffer must be exactly equal to our Page Size and the\n\t * Large Page Size Buffer should be 0 (per above) or a power of 2.\n\t */\n\tif (fl_small_pg != CXGBE_PAGE_SIZE ||\n\t (fl_large_pg & (fl_large_pg - 1)) != 0) {\n\t\tdev_err(adap, \"bad SGE FL page buffer sizes [%d, %d]\\n\",\n\t\t\tfl_small_pg, fl_large_pg);\n\t\treturn -EINVAL;\n\t}\n\tif (fl_large_pg)\n\t\ts->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT;\n\n\tif (adap->use_unpacked_mode) {\n\t\tint err = 0;\n\n\t\tif (fl_small_mtu < FL_MTU_SMALL_BUFSIZE(adap)) {\n\t\t\tdev_err(adap, \"bad SGE FL small MTU %d\\n\",\n\t\t\t\tfl_small_mtu);\n\t\t\terr = -EINVAL;\n\t\t}\n\t\tif (fl_large_mtu < FL_MTU_LARGE_BUFSIZE(adap)) {\n\t\t\tdev_err(adap, \"bad SGE FL large MTU %d\\n\",\n\t\t\t\tfl_large_mtu);\n\t\t\terr = -EINVAL;\n\t\t}\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\t/*\n\t * Retrieve our RX interrupt holdoff timer values and counter\n\t * threshold values from the SGE parameters.\n\t */\n\ttimer_value_0_and_1 = t4_read_reg(adap, A_SGE_TIMER_VALUE_0_AND_1);\n\ttimer_value_2_and_3 = t4_read_reg(adap, A_SGE_TIMER_VALUE_2_AND_3);\n\ttimer_value_4_and_5 = t4_read_reg(adap, A_SGE_TIMER_VALUE_4_AND_5);\n\ts->timer_val[0] = core_ticks_to_us(adap,\n\t\t\t\t\t G_TIMERVALUE0(timer_value_0_and_1));\n\ts->timer_val[1] = core_ticks_to_us(adap,\n\t\t\t\t\t G_TIMERVALUE1(timer_value_0_and_1));\n\ts->timer_val[2] = core_ticks_to_us(adap,\n\t\t\t\t\t G_TIMERVALUE2(timer_value_2_and_3));\n\ts->timer_val[3] = core_ticks_to_us(adap,\n\t\t\t\t\t G_TIMERVALUE3(timer_value_2_and_3));\n\ts->timer_val[4] = core_ticks_to_us(adap,\n\t\t\t\t\t G_TIMERVALUE4(timer_value_4_and_5));\n\ts->timer_val[5] = core_ticks_to_us(adap,\n\t\t\t\t\t G_TIMERVALUE5(timer_value_4_and_5));\n\n\tingress_rx_threshold = t4_read_reg(adap, A_SGE_INGRESS_RX_THRESHOLD);\n\ts->counter_val[0] = G_THRESHOLD_0(ingress_rx_threshold);\n\ts->counter_val[1] = G_THRESHOLD_1(ingress_rx_threshold);\n\ts->counter_val[2] = G_THRESHOLD_2(ingress_rx_threshold);\n\ts->counter_val[3] = G_THRESHOLD_3(ingress_rx_threshold);\n\n\treturn 0;\n}\n\nint t4_sge_init(struct adapter *adap)\n{\n\tstruct sge *s = &adap->sge;\n\tu32 sge_control, sge_control2, sge_conm_ctrl;\n\tunsigned int ingpadboundary, ingpackboundary;\n\tint ret, egress_threshold;\n\n\t/*\n\t * Ingress Padding Boundary and Egress Status Page Size are set up by\n\t * t4_fixup_host_params().\n\t */\n\tsge_control = t4_read_reg(adap, A_SGE_CONTROL);\n\ts->pktshift = G_PKTSHIFT(sge_control);\n\ts->stat_len = (sge_control & F_EGRSTATUSPAGESIZE) ? 128 : 64;\n\n\t/*\n\t * T4 uses a single control field to specify both the PCIe Padding and\n\t * Packing Boundary. T5 introduced the ability to specify these\n\t * separately. The actual Ingress Packet Data alignment boundary\n\t * within Packed Buffer Mode is the maximum of these two\n\t * specifications.\n\t */\n\tingpadboundary = 1 << (G_INGPADBOUNDARY(sge_control) +\n\t\t\t X_INGPADBOUNDARY_SHIFT);\n\ts->fl_align = ingpadboundary;\n\n\tif (!is_t4(adap->params.chip) && !adap->use_unpacked_mode) {\n\t\t/*\n\t\t * T5 has a weird interpretation of one of the PCIe Packing\n\t\t * Boundary values. No idea why ...\n\t\t */\n\t\tsge_control2 = t4_read_reg(adap, A_SGE_CONTROL2);\n\t\tingpackboundary = G_INGPACKBOUNDARY(sge_control2);\n\t\tif (ingpackboundary == X_INGPACKBOUNDARY_16B)\n\t\t\tingpackboundary = 16;\n\t\telse\n\t\t\tingpackboundary = 1 << (ingpackboundary +\n\t\t\t\t\t X_INGPACKBOUNDARY_SHIFT);\n\n\t\ts->fl_align = max(ingpadboundary, ingpackboundary);\n\t}\n\n\tret = t4_sge_init_soft(adap);\n\tif (ret < 0) {\n\t\tdev_err(adap, \"%s: t4_sge_init_soft failed, error %d\\n\",\n\t\t\t__func__, -ret);\n\t\treturn ret;\n\t}\n\n\t/*\n\t * A FL with <= fl_starve_thres buffers is starving and a periodic\n\t * timer will attempt to refill it. This needs to be larger than the\n\t * SGE's Egress Congestion Threshold. If it isn't, then we can get\n\t * stuck waiting for new packets while the SGE is waiting for us to\n\t * give it more Free List entries. (Note that the SGE's Egress\n\t * Congestion Threshold is in units of 2 Free List pointers.) For T4,\n\t * there was only a single field to control this. For T5 there's the\n\t * original field which now only applies to Unpacked Mode Free List\n\t * buffers and a new field which only applies to Packed Mode Free List\n\t * buffers.\n\t */\n\tsge_conm_ctrl = t4_read_reg(adap, A_SGE_CONM_CTRL);\n\tif (is_t4(adap->params.chip) || adap->use_unpacked_mode)\n\t\tegress_threshold = G_EGRTHRESHOLD(sge_conm_ctrl);\n\telse\n\t\tegress_threshold = G_EGRTHRESHOLDPACKING(sge_conm_ctrl);\n\ts->fl_starve_thres = 2 * egress_threshold + 1;\n\n\treturn 0;\n}\n" }, { "path": "drivers/net/e1000/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_e1000.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_pmd_e1000_version.map\n\nLIBABIVER := 1\n\nifeq ($(CC), icc)\n#\n# CFLAGS for icc\n#\nCFLAGS_BASE_DRIVER = -wd177 -wd181 -wd188 -wd869 -wd2259\nelse\n#\n# CFLAGS for gcc\n#\nCFLAGS_BASE_DRIVER = -Wno-uninitialized -Wno-unused-parameter\nCFLAGS_BASE_DRIVER += -Wno-unused-variable\nendif\n\n#\n# Add extra flags for base driver files (also known as shared code)\n# to disable warnings in them\n#\nBASE_DRIVER_OBJS=$(patsubst %.c,%.o,$(notdir $(wildcard $(SRCDIR)/base/*.c)))\n$(foreach obj, $(BASE_DRIVER_OBJS), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER)))\n\nVPATH += $(SRCDIR)/base\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_80003es2lan.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_82540.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_82541.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_82542.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_82543.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_82571.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_82575.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_i210.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_api.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_ich8lan.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_mac.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_manage.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_mbx.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_nvm.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_osdep.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_phy.c\nSRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_vf.c\nSRCS-$(CONFIG_RTE_LIBRTE_IGB_PMD) += igb_ethdev.c\nSRCS-$(CONFIG_RTE_LIBRTE_IGB_PMD) += igb_rxtx.c\nSRCS-$(CONFIG_RTE_LIBRTE_IGB_PMD) += igb_pf.c\nSRCS-$(CONFIG_RTE_LIBRTE_EM_PMD) += em_ethdev.c\nSRCS-$(CONFIG_RTE_LIBRTE_EM_PMD) += em_rxtx.c\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += lib/librte_eal lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += lib/librte_mempool lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += lib/librte_net\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/e1000/base/README", "content": "..\n BSD LICENSE\n \n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n \n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n \n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nThis directory contains source code of FreeBSD em & igb drivers of version\ncid-shared-code.2014.04.21 released by LAD. The sub-directory of lad/\ncontains the original source package.\n\nUpdating the driver\n===================\n\nNOTE: The source code in this directory should not be modified apart from\nthe following file(s):\n\n e1000_osdep.c\n e1000_osdep.h\n" }, { "path": "drivers/net/e1000/base/e1000_80003es2lan.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n/* 80003ES2LAN Gigabit Ethernet Controller (Copper)\n * 80003ES2LAN Gigabit Ethernet Controller (Serdes)\n */\n\n#include \"e1000_api.h\"\n\nSTATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);\nSTATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw);\nSTATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);\nSTATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);\nSTATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,\n\t\t\t\t\t\t u32 offset,\n\t\t\t\t\t\t u16 *data);\nSTATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,\n\t\t\t\t\t\t u32 offset,\n\t\t\t\t\t\t u16 data);\nSTATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,\n\t\t\t\t\tu16 words, u16 *data);\nSTATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);\nSTATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);\nSTATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);\nSTATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\t u16 *duplex);\nSTATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);\nSTATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);\nSTATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);\nSTATIC s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);\nSTATIC s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);\nSTATIC s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);\nSTATIC s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);\nSTATIC s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 *data);\nSTATIC s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 data);\nSTATIC void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);\nSTATIC void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);\nSTATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);\nSTATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);\n\n/* A table for the GG82563 cable length where the range is defined\n * with a lower bound at \"index\" and the upper bound at\n * \"index + 5\".\n */\nSTATIC const u16 e1000_gg82563_cable_length_table[] = {\n\t0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };\n#define GG82563_CABLE_LENGTH_TABLE_SIZE \\\n\t\t(sizeof(e1000_gg82563_cable_length_table) / \\\n\t\t sizeof(e1000_gg82563_cable_length_table[0]))\n\n/**\n * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_init_phy_params_80003es2lan\");\n\n\tif (hw->phy.media_type != e1000_media_type_copper) {\n\t\tphy->type = e1000_phy_none;\n\t\treturn E1000_SUCCESS;\n\t} else {\n\t\tphy->ops.power_up = e1000_power_up_phy_copper;\n\t\tphy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;\n\t}\n\n\tphy->addr\t\t= 1;\n\tphy->autoneg_mask\t= AUTONEG_ADVERTISE_SPEED_DEFAULT;\n\tphy->reset_delay_us\t= 100;\n\tphy->type\t\t= e1000_phy_gg82563;\n\n\tphy->ops.acquire\t= e1000_acquire_phy_80003es2lan;\n\tphy->ops.check_polarity\t= e1000_check_polarity_m88;\n\tphy->ops.check_reset_block = e1000_check_reset_block_generic;\n\tphy->ops.commit\t\t= e1000_phy_sw_reset_generic;\n\tphy->ops.get_cfg_done\t= e1000_get_cfg_done_80003es2lan;\n\tphy->ops.get_info\t= e1000_get_phy_info_m88;\n\tphy->ops.release\t= e1000_release_phy_80003es2lan;\n\tphy->ops.reset\t\t= e1000_phy_hw_reset_generic;\n\tphy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;\n\n\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;\n\tphy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;\n\tphy->ops.read_reg\t= e1000_read_phy_reg_gg82563_80003es2lan;\n\tphy->ops.write_reg\t= e1000_write_phy_reg_gg82563_80003es2lan;\n\n\tphy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;\n\n\t/* This can only be done after all function pointers are setup. */\n\tret_val = e1000_get_phy_id(hw);\n\n\t/* Verify phy id */\n\tif (phy->id != GG82563_E_PHY_ID)\n\t\treturn -E1000_ERR_PHY;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\tu16 size;\n\n\tDEBUGFUNC(\"e1000_init_nvm_params_80003es2lan\");\n\n\tnvm->opcode_bits = 8;\n\tnvm->delay_usec = 1;\n\tswitch (nvm->override) {\n\tcase e1000_nvm_override_spi_large:\n\t\tnvm->page_size = 32;\n\t\tnvm->address_bits = 16;\n\t\tbreak;\n\tcase e1000_nvm_override_spi_small:\n\t\tnvm->page_size = 8;\n\t\tnvm->address_bits = 8;\n\t\tbreak;\n\tdefault:\n\t\tnvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;\n\t\tnvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;\n\t\tbreak;\n\t}\n\n\tnvm->type = e1000_nvm_eeprom_spi;\n\n\tsize = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>\n\t\t E1000_EECD_SIZE_EX_SHIFT);\n\n\t/* Added to a constant, \"size\" becomes the left-shift value\n\t * for setting word_size.\n\t */\n\tsize += NVM_WORD_SIZE_BASE_SHIFT;\n\n\t/* EEPROM access above 16k is unsupported */\n\tif (size > 14)\n\t\tsize = 14;\n\tnvm->word_size = 1 << size;\n\n\t/* Function Pointers */\n\tnvm->ops.acquire\t= e1000_acquire_nvm_80003es2lan;\n\tnvm->ops.read\t\t= e1000_read_nvm_eerd;\n\tnvm->ops.release\t= e1000_release_nvm_80003es2lan;\n\tnvm->ops.update\t\t= e1000_update_nvm_checksum_generic;\n\tnvm->ops.valid_led_default = e1000_valid_led_default_generic;\n\tnvm->ops.validate\t= e1000_validate_nvm_checksum_generic;\n\tnvm->ops.write\t\t= e1000_write_nvm_80003es2lan;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"e1000_init_mac_params_80003es2lan\");\n\n\t/* Set media type and media-dependent function pointers */\n\tswitch (hw->device_id) {\n\tcase E1000_DEV_ID_80003ES2LAN_SERDES_DPT:\n\t\thw->phy.media_type = e1000_media_type_internal_serdes;\n\t\tmac->ops.check_for_link = e1000_check_for_serdes_link_generic;\n\t\tmac->ops.setup_physical_interface =\n\t\t\t\t\te1000_setup_fiber_serdes_link_generic;\n\t\tbreak;\n\tdefault:\n\t\thw->phy.media_type = e1000_media_type_copper;\n\t\tmac->ops.check_for_link = e1000_check_for_copper_link_generic;\n\t\tmac->ops.setup_physical_interface =\n\t\t\t\t\te1000_setup_copper_link_80003es2lan;\n\t\tbreak;\n\t}\n\n\t/* Set mta register count */\n\tmac->mta_reg_count = 128;\n\t/* Set rar entry count */\n\tmac->rar_entry_count = E1000_RAR_ENTRIES;\n\t/* Set if part includes ASF firmware */\n\tmac->asf_firmware_present = true;\n\t/* FWSM register */\n\tmac->has_fwsm = true;\n\t/* ARC supported; valid only if manageability features are enabled. */\n\tmac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &\n\t\t\t\t E1000_FWSM_MODE_MASK);\n\t/* Adaptive IFS not supported */\n\tmac->adaptive_ifs = false;\n\n\t/* Function pointers */\n\n\t/* bus type/speed/width */\n\tmac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;\n\t/* reset */\n\tmac->ops.reset_hw = e1000_reset_hw_80003es2lan;\n\t/* hw initialization */\n\tmac->ops.init_hw = e1000_init_hw_80003es2lan;\n\t/* link setup */\n\tmac->ops.setup_link = e1000_setup_link_generic;\n\t/* check management mode */\n\tmac->ops.check_mng_mode = e1000_check_mng_mode_generic;\n\t/* multicast address update */\n\tmac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;\n\t/* writing VFTA */\n\tmac->ops.write_vfta = e1000_write_vfta_generic;\n\t/* clearing VFTA */\n\tmac->ops.clear_vfta = e1000_clear_vfta_generic;\n\t/* read mac address */\n\tmac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan;\n\t/* ID LED init */\n\tmac->ops.id_led_init = e1000_id_led_init_generic;\n\t/* blink LED */\n\tmac->ops.blink_led = e1000_blink_led_generic;\n\t/* setup LED */\n\tmac->ops.setup_led = e1000_setup_led_generic;\n\t/* cleanup LED */\n\tmac->ops.cleanup_led = e1000_cleanup_led_generic;\n\t/* turn on/off LED */\n\tmac->ops.led_on = e1000_led_on_generic;\n\tmac->ops.led_off = e1000_led_off_generic;\n\t/* clear hardware counters */\n\tmac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;\n\t/* link info */\n\tmac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;\n\n\t/* set lan id for port to determine which phy lock to use */\n\thw->mac.ops.set_lan_id(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.\n * @hw: pointer to the HW structure\n *\n * Called to initialize all function pointers and parameters.\n **/\nvoid e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_function_pointers_80003es2lan\");\n\n\thw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;\n\thw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;\n\thw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;\n}\n\n/**\n * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY\n * @hw: pointer to the HW structure\n *\n * A wrapper to acquire access rights to the correct PHY.\n **/\nSTATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)\n{\n\tu16 mask;\n\n\tDEBUGFUNC(\"e1000_acquire_phy_80003es2lan\");\n\n\tmask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;\n\treturn e1000_acquire_swfw_sync_80003es2lan(hw, mask);\n}\n\n/**\n * e1000_release_phy_80003es2lan - Release rights to access PHY\n * @hw: pointer to the HW structure\n *\n * A wrapper to release access rights to the correct PHY.\n **/\nSTATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw)\n{\n\tu16 mask;\n\n\tDEBUGFUNC(\"e1000_release_phy_80003es2lan\");\n\n\tmask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;\n\te1000_release_swfw_sync_80003es2lan(hw, mask);\n}\n\n/**\n * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register\n * @hw: pointer to the HW structure\n *\n * Acquire the semaphore to access the Kumeran interface.\n *\n **/\nSTATIC s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)\n{\n\tu16 mask;\n\n\tDEBUGFUNC(\"e1000_acquire_mac_csr_80003es2lan\");\n\n\tmask = E1000_SWFW_CSR_SM;\n\n\treturn e1000_acquire_swfw_sync_80003es2lan(hw, mask);\n}\n\n/**\n * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register\n * @hw: pointer to the HW structure\n *\n * Release the semaphore used to access the Kumeran interface\n **/\nSTATIC void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)\n{\n\tu16 mask;\n\n\tDEBUGFUNC(\"e1000_release_mac_csr_80003es2lan\");\n\n\tmask = E1000_SWFW_CSR_SM;\n\n\te1000_release_swfw_sync_80003es2lan(hw, mask);\n}\n\n/**\n * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM\n * @hw: pointer to the HW structure\n *\n * Acquire the semaphore to access the EEPROM.\n **/\nSTATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_acquire_nvm_80003es2lan\");\n\n\tret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_acquire_nvm_generic(hw);\n\n\tif (ret_val)\n\t\te1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM\n * @hw: pointer to the HW structure\n *\n * Release the semaphore used to access the EEPROM.\n **/\nSTATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_release_nvm_80003es2lan\");\n\n\te1000_release_nvm_generic(hw);\n\te1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);\n}\n\n/**\n * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore\n * @hw: pointer to the HW structure\n * @mask: specifies which semaphore to acquire\n *\n * Acquire the SW/FW semaphore to access the PHY or NVM. The mask\n * will also specify which port we're acquiring the lock for.\n **/\nSTATIC s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)\n{\n\tu32 swfw_sync;\n\tu32 swmask = mask;\n\tu32 fwmask = mask << 16;\n\ts32 i = 0;\n\ts32 timeout = 50;\n\n\tDEBUGFUNC(\"e1000_acquire_swfw_sync_80003es2lan\");\n\n\twhile (i < timeout) {\n\t\tif (e1000_get_hw_semaphore_generic(hw))\n\t\t\treturn -E1000_ERR_SWFW_SYNC;\n\n\t\tswfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);\n\t\tif (!(swfw_sync & (fwmask | swmask)))\n\t\t\tbreak;\n\n\t\t/* Firmware currently using resource (fwmask)\n\t\t * or other software thread using resource (swmask)\n\t\t */\n\t\te1000_put_hw_semaphore_generic(hw);\n\t\tmsec_delay_irq(5);\n\t\ti++;\n\t}\n\n\tif (i == timeout) {\n\t\tDEBUGOUT(\"Driver can't access resource, SW_FW_SYNC timeout.\\n\");\n\t\treturn -E1000_ERR_SWFW_SYNC;\n\t}\n\n\tswfw_sync |= swmask;\n\tE1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);\n\n\te1000_put_hw_semaphore_generic(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore\n * @hw: pointer to the HW structure\n * @mask: specifies which semaphore to acquire\n *\n * Release the SW/FW semaphore used to access the PHY or NVM. The mask\n * will also specify which port we're releasing the lock for.\n **/\nSTATIC void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)\n{\n\tu32 swfw_sync;\n\n\tDEBUGFUNC(\"e1000_release_swfw_sync_80003es2lan\");\n\n\twhile (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)\n\t\t; /* Empty */\n\n\tswfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);\n\tswfw_sync &= ~mask;\n\tE1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);\n\n\te1000_put_hw_semaphore_generic(hw);\n}\n\n/**\n * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register\n * @hw: pointer to the HW structure\n * @offset: offset of the register to read\n * @data: pointer to the data returned from the operation\n *\n * Read the GG82563 PHY register.\n **/\nSTATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,\n\t\t\t\t\t\t u32 offset, u16 *data)\n{\n\ts32 ret_val;\n\tu32 page_select;\n\tu16 temp;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_gg82563_80003es2lan\");\n\n\tret_val = e1000_acquire_phy_80003es2lan(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Select Configuration Page */\n\tif ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {\n\t\tpage_select = GG82563_PHY_PAGE_SELECT;\n\t} else {\n\t\t/* Use Alternative Page Select register to access\n\t\t * registers 30 and 31\n\t\t */\n\t\tpage_select = GG82563_PHY_PAGE_SELECT_ALT;\n\t}\n\n\ttemp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);\n\tret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);\n\tif (ret_val) {\n\t\te1000_release_phy_80003es2lan(hw);\n\t\treturn ret_val;\n\t}\n\n\tif (hw->dev_spec._80003es2lan.mdic_wa_enable) {\n\t\t/* The \"ready\" bit in the MDIC register may be incorrectly set\n\t\t * before the device has completed the \"Page Select\" MDI\n\t\t * transaction. So we wait 200us after each MDI command...\n\t\t */\n\t\tusec_delay(200);\n\n\t\t/* ...and verify the command was successful. */\n\t\tret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);\n\n\t\tif (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {\n\t\t\te1000_release_phy_80003es2lan(hw);\n\t\t\treturn -E1000_ERR_PHY;\n\t\t}\n\n\t\tusec_delay(200);\n\n\t\tret_val = e1000_read_phy_reg_mdic(hw,\n\t\t\t\t\t\t MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t\t data);\n\n\t\tusec_delay(200);\n\t} else {\n\t\tret_val = e1000_read_phy_reg_mdic(hw,\n\t\t\t\t\t\t MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t\t data);\n\t}\n\n\te1000_release_phy_80003es2lan(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register\n * @hw: pointer to the HW structure\n * @offset: offset of the register to read\n * @data: value to write to the register\n *\n * Write to the GG82563 PHY register.\n **/\nSTATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,\n\t\t\t\t\t\t u32 offset, u16 data)\n{\n\ts32 ret_val;\n\tu32 page_select;\n\tu16 temp;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_gg82563_80003es2lan\");\n\n\tret_val = e1000_acquire_phy_80003es2lan(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Select Configuration Page */\n\tif ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {\n\t\tpage_select = GG82563_PHY_PAGE_SELECT;\n\t} else {\n\t\t/* Use Alternative Page Select register to access\n\t\t * registers 30 and 31\n\t\t */\n\t\tpage_select = GG82563_PHY_PAGE_SELECT_ALT;\n\t}\n\n\ttemp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);\n\tret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);\n\tif (ret_val) {\n\t\te1000_release_phy_80003es2lan(hw);\n\t\treturn ret_val;\n\t}\n\n\tif (hw->dev_spec._80003es2lan.mdic_wa_enable) {\n\t\t/* The \"ready\" bit in the MDIC register may be incorrectly set\n\t\t * before the device has completed the \"Page Select\" MDI\n\t\t * transaction. So we wait 200us after each MDI command...\n\t\t */\n\t\tusec_delay(200);\n\n\t\t/* ...and verify the command was successful. */\n\t\tret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);\n\n\t\tif (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {\n\t\t\te1000_release_phy_80003es2lan(hw);\n\t\t\treturn -E1000_ERR_PHY;\n\t\t}\n\n\t\tusec_delay(200);\n\n\t\tret_val = e1000_write_phy_reg_mdic(hw,\n\t\t\t\t\t\t MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t\t data);\n\n\t\tusec_delay(200);\n\t} else {\n\t\tret_val = e1000_write_phy_reg_mdic(hw,\n\t\t\t\t\t\t MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t\t data);\n\t}\n\n\te1000_release_phy_80003es2lan(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_nvm_80003es2lan - Write to ESB2 NVM\n * @hw: pointer to the HW structure\n * @offset: offset of the register to read\n * @words: number of words to write\n * @data: buffer of data to write to the NVM\n *\n * Write \"words\" of data to the ESB2 NVM.\n **/\nSTATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data)\n{\n\tDEBUGFUNC(\"e1000_write_nvm_80003es2lan\");\n\n\treturn e1000_write_nvm_spi(hw, offset, words, data);\n}\n\n/**\n * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete\n * @hw: pointer to the HW structure\n *\n * Wait a specific amount of time for manageability processes to complete.\n * This is a function pointer entry point called by the phy module.\n **/\nSTATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)\n{\n\ts32 timeout = PHY_CFG_TIMEOUT;\n\tu32 mask = E1000_NVM_CFG_DONE_PORT_0;\n\n\tDEBUGFUNC(\"e1000_get_cfg_done_80003es2lan\");\n\n\tif (hw->bus.func == 1)\n\t\tmask = E1000_NVM_CFG_DONE_PORT_1;\n\n\twhile (timeout) {\n\t\tif (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t\ttimeout--;\n\t}\n\tif (!timeout) {\n\t\tDEBUGOUT(\"MNG configuration cycle has not completed.\\n\");\n\t\treturn -E1000_ERR_RESET;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex\n * @hw: pointer to the HW structure\n *\n * Force the speed and duplex settings onto the PHY. This is a\n * function pointer entry point called by the phy module.\n **/\nSTATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 phy_data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_phy_force_speed_duplex_80003es2lan\");\n\n\tif (!(hw->phy.ops.read_reg))\n\t\treturn E1000_SUCCESS;\n\n\t/* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI\n\t * forced whenever speed and duplex are forced.\n\t */\n\tret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;\n\tret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tDEBUGOUT1(\"GG82563 PSCR: %X\\n\", phy_data);\n\n\tret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\te1000_phy_force_speed_duplex_setup(hw, &phy_data);\n\n\t/* Reset the phy to commit changes. */\n\tphy_data |= MII_CR_RESET;\n\n\tret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tusec_delay(1);\n\n\tif (hw->phy.autoneg_wait_to_complete) {\n\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on GG82563 phy.\\n\");\n\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (!link) {\n\t\t\t/* We didn't get link.\n\t\t\t * Reset the DSP and cross our fingers.\n\t\t\t */\n\t\t\tret_val = e1000_phy_reset_dsp_generic(hw);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t}\n\n\t\t/* Try once more */\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,\n\t\t\t\t &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Resetting the phy means we need to verify the TX_CLK corresponds\n\t * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.\n\t */\n\tphy_data &= ~GG82563_MSCR_TX_CLK_MASK;\n\tif (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)\n\t\tphy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;\n\telse\n\t\tphy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;\n\n\t/* In addition, we must re-enable CRS on Tx for both half and full\n\t * duplex.\n\t */\n\tphy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;\n\tret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,\n\t\t\t\t\tphy_data);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_cable_length_80003es2lan - Set approximate cable length\n * @hw: pointer to the HW structure\n *\n * Find the approximate cable length as measured by the GG82563 PHY.\n * This is a function pointer entry point called by the phy module.\n **/\nSTATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, index;\n\n\tDEBUGFUNC(\"e1000_get_cable_length_80003es2lan\");\n\n\tif (!(hw->phy.ops.read_reg))\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tindex = phy_data & GG82563_DSPD_CABLE_LENGTH;\n\n\tif (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)\n\t\treturn -E1000_ERR_PHY;\n\n\tphy->min_cable_length = e1000_gg82563_cable_length_table[index];\n\tphy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];\n\n\tphy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_link_up_info_80003es2lan - Report speed and duplex\n * @hw: pointer to the HW structure\n * @speed: pointer to speed buffer\n * @duplex: pointer to duplex buffer\n *\n * Retrieve the current speed and duplex configuration.\n **/\nSTATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\t u16 *duplex)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_get_link_up_info_80003es2lan\");\n\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\t\tret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,\n\t\t\t\t\t\t\t\t duplex);\n\t\thw->phy.ops.cfg_on_link_up(hw);\n\t} else {\n\t\tret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,\n\t\t\t\t\t\t\t\t speed,\n\t\t\t\t\t\t\t\t duplex);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_reset_hw_80003es2lan - Reset the ESB2 controller\n * @hw: pointer to the HW structure\n *\n * Perform a global reset to the ESB2 controller.\n **/\nSTATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\tu16 kum_reg_data;\n\n\tDEBUGFUNC(\"e1000_reset_hw_80003es2lan\");\n\n\t/* Prevent the PCI-E bus from sticking if there is no TLP connection\n\t * on the last TLP read/write transaction when MAC is reset.\n\t */\n\tret_val = e1000_disable_pcie_master_generic(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"PCI-E Master disable polling has failed.\\n\");\n\n\tDEBUGOUT(\"Masking off all interrupts\\n\");\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\n\tE1000_WRITE_REG(hw, E1000_RCTL, 0);\n\tE1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);\n\tE1000_WRITE_FLUSH(hw);\n\n\tmsec_delay(10);\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\tret_val = e1000_acquire_phy_80003es2lan(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tDEBUGOUT(\"Issuing a global reset to MAC\\n\");\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);\n\te1000_release_phy_80003es2lan(hw);\n\n\t/* Disable IBIST slave mode (far-end loopback) */\n\tret_val = e1000_read_kmrn_reg_80003es2lan(hw,\n\t\t\t\tE1000_KMRNCTRLSTA_INBAND_PARAM, &kum_reg_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\tkum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;\n\te1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,\n\t\t\t\t\tkum_reg_data);\n\n\tret_val = e1000_get_auto_rd_done_generic(hw);\n\tif (ret_val)\n\t\t/* We don't want to continue accessing MAC registers. */\n\t\treturn ret_val;\n\n\t/* Clear any pending interrupt events. */\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\tE1000_READ_REG(hw, E1000_ICR);\n\n\treturn e1000_check_alt_mac_addr_generic(hw);\n}\n\n/**\n * e1000_init_hw_80003es2lan - Initialize the ESB2 controller\n * @hw: pointer to the HW structure\n *\n * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.\n **/\nSTATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 reg_data;\n\ts32 ret_val;\n\tu16 kum_reg_data;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_init_hw_80003es2lan\");\n\n\te1000_initialize_hw_bits_80003es2lan(hw);\n\n\t/* Initialize identification LED */\n\tret_val = mac->ops.id_led_init(hw);\n\t/* An error is not fatal and we should not stop init due to this */\n\tif (ret_val)\n\t\tDEBUGOUT(\"Error initializing identification LED\\n\");\n\n\t/* Disabling VLAN filtering */\n\tDEBUGOUT(\"Initializing the IEEE VLAN\\n\");\n\tmac->ops.clear_vfta(hw);\n\n\t/* Setup the receive address. */\n\te1000_init_rx_addrs_generic(hw, mac->rar_entry_count);\n\n\t/* Zero out the Multicast HASH table */\n\tDEBUGOUT(\"Zeroing the MTA\\n\");\n\tfor (i = 0; i < mac->mta_reg_count; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);\n\n\t/* Setup link and flow control */\n\tret_val = mac->ops.setup_link(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Disable IBIST slave mode (far-end loopback) */\n\te1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,\n\t\t\t\t\t&kum_reg_data);\n\tkum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;\n\te1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,\n\t\t\t\t\t kum_reg_data);\n\n\t/* Set the transmit descriptor write-back policy */\n\treg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));\n\treg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |\n\t\t E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);\n\n\t/* ...for both queues. */\n\treg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));\n\treg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |\n\t\t E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);\n\n\t/* Enable retransmit on late collisions */\n\treg_data = E1000_READ_REG(hw, E1000_TCTL);\n\treg_data |= E1000_TCTL_RTLC;\n\tE1000_WRITE_REG(hw, E1000_TCTL, reg_data);\n\n\t/* Configure Gigabit Carry Extend Padding */\n\treg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);\n\treg_data &= ~E1000_TCTL_EXT_GCEX_MASK;\n\treg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;\n\tE1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data);\n\n\t/* Configure Transmit Inter-Packet Gap */\n\treg_data = E1000_READ_REG(hw, E1000_TIPG);\n\treg_data &= ~E1000_TIPG_IPGT_MASK;\n\treg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;\n\tE1000_WRITE_REG(hw, E1000_TIPG, reg_data);\n\n\treg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);\n\treg_data &= ~0x00100000;\n\tE1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);\n\n\t/* default to true to enable the MDIC W/A */\n\thw->dev_spec._80003es2lan.mdic_wa_enable = true;\n\n\tret_val =\n\t e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>\n\t\t\t\t\t E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);\n\tif (!ret_val) {\n\t\tif ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==\n\t\t E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)\n\t\t\thw->dev_spec._80003es2lan.mdic_wa_enable = false;\n\t}\n\n\t/* Clear all of the statistics registers (clear on read). It is\n\t * important that we do this after we have tried to establish link\n\t * because the symbol error count will increment wildly if there\n\t * is no link.\n\t */\n\te1000_clear_hw_cntrs_80003es2lan(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2\n * @hw: pointer to the HW structure\n *\n * Initializes required hardware-dependent bits needed for normal operation.\n **/\nSTATIC void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)\n{\n\tu32 reg;\n\n\tDEBUGFUNC(\"e1000_initialize_hw_bits_80003es2lan\");\n\n\t/* Transmit Descriptor Control 0 */\n\treg = E1000_READ_REG(hw, E1000_TXDCTL(0));\n\treg |= (1 << 22);\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);\n\n\t/* Transmit Descriptor Control 1 */\n\treg = E1000_READ_REG(hw, E1000_TXDCTL(1));\n\treg |= (1 << 22);\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);\n\n\t/* Transmit Arbitration Control 0 */\n\treg = E1000_READ_REG(hw, E1000_TARC(0));\n\treg &= ~(0xF << 27); /* 30:27 */\n\tif (hw->phy.media_type != e1000_media_type_copper)\n\t\treg &= ~(1 << 20);\n\tE1000_WRITE_REG(hw, E1000_TARC(0), reg);\n\n\t/* Transmit Arbitration Control 1 */\n\treg = E1000_READ_REG(hw, E1000_TARC(1));\n\tif (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)\n\t\treg &= ~(1 << 28);\n\telse\n\t\treg |= (1 << 28);\n\tE1000_WRITE_REG(hw, E1000_TARC(1), reg);\n\n\t/* Disable IPv6 extension header parsing because some malformed\n\t * IPv6 headers can hang the Rx.\n\t */\n\treg = E1000_READ_REG(hw, E1000_RFCTL);\n\treg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);\n\tE1000_WRITE_REG(hw, E1000_RFCTL, reg);\n\n\treturn;\n}\n\n/**\n * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link\n * @hw: pointer to the HW structure\n *\n * Setup some GG82563 PHY registers for obtaining link\n **/\nSTATIC s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu32 reg;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_copper_link_setup_gg82563_80003es2lan\");\n\n\tret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tdata |= GG82563_MSCR_ASSERT_CRS_ON_TX;\n\t/* Use 25MHz for both link down and 1000Base-T for Tx clock. */\n\tdata |= GG82563_MSCR_TX_CLK_1000MBPS_25;\n\n\tret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Options:\n\t * MDI/MDI-X = 0 (default)\n\t * 0 - Auto for all speeds\n\t * 1 - MDI mode\n\t * 2 - MDI-X mode\n\t * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)\n\t */\n\tret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tdata &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;\n\n\tswitch (phy->mdix) {\n\tcase 1:\n\t\tdata |= GG82563_PSCR_CROSSOVER_MODE_MDI;\n\t\tbreak;\n\tcase 2:\n\t\tdata |= GG82563_PSCR_CROSSOVER_MODE_MDIX;\n\t\tbreak;\n\tcase 0:\n\tdefault:\n\t\tdata |= GG82563_PSCR_CROSSOVER_MODE_AUTO;\n\t\tbreak;\n\t}\n\n\t/* Options:\n\t * disable_polarity_correction = 0 (default)\n\t * Automatic Correction for Reversed Cable Polarity\n\t * 0 - Disabled\n\t * 1 - Enabled\n\t */\n\tdata &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;\n\tif (phy->disable_polarity_correction)\n\t\tdata |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;\n\n\tret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* SW Reset the PHY so all changes take effect */\n\tret_val = hw->phy.ops.commit(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error Resetting the PHY\\n\");\n\t\treturn ret_val;\n\t}\n\n\t/* Bypass Rx and Tx FIFO's */\n\treg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;\n\tdata = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |\n\t\tE1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);\n\tret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;\n\tret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\tdata |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;\n\tret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tdata &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;\n\tret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\treg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);\n\n\tret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Do not init these registers when the HW is in IAMT mode, since the\n\t * firmware will have already initialized them. We only initialize\n\t * them if the HW is not in IAMT mode.\n\t */\n\tif (!hw->mac.ops.check_mng_mode(hw)) {\n\t\t/* Enable Electrical Idle on the PHY */\n\t\tdata |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;\n\t\tret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,\n\t\t\t\t\t\tdata);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,\n\t\t\t\t\t &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tdata &= ~GG82563_KMCR_PASS_FALSE_CARRIER;\n\t\tret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,\n\t\t\t\t\t\tdata);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* Workaround: Disable padding in Kumeran interface in the MAC\n\t * and in the PHY to avoid CRC errors.\n\t */\n\tret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tdata |= GG82563_ICR_DIS_PADDING;\n\tret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2\n * @hw: pointer to the HW structure\n *\n * Essentially a wrapper for setting up all things \"copper\" related.\n * This is a function pointer entry point called by the mac module.\n **/\nSTATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\tu16 reg_data;\n\n\tDEBUGFUNC(\"e1000_setup_copper_link_80003es2lan\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= E1000_CTRL_SLU;\n\tctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\t/* Set the mac to wait the maximum time between each\n\t * iteration and increase the max iterations when\n\t * polling the phy; this fixes erroneous timeouts at 10Mbps.\n\t */\n\tret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),\n\t\t\t\t\t\t 0xFFFF);\n\tif (ret_val)\n\t\treturn ret_val;\n\tret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),\n\t\t\t\t\t\t ®_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\treg_data |= 0x3F;\n\tret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),\n\t\t\t\t\t\t reg_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\tret_val =\n\t e1000_read_kmrn_reg_80003es2lan(hw,\n\t\t\t\t\t E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,\n\t\t\t\t\t ®_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\treg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;\n\tret_val =\n\t e1000_write_kmrn_reg_80003es2lan(hw,\n\t\t\t\t\t E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,\n\t\t\t\t\t reg_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn e1000_setup_copper_link_generic(hw);\n}\n\n/**\n * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up\n * @hw: pointer to the HW structure\n * @duplex: current duplex setting\n *\n * Configure the KMRN interface by applying last minute quirks for\n * 10/100 operation.\n **/\nSTATIC s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 speed;\n\tu16 duplex;\n\n\tDEBUGFUNC(\"e1000_configure_on_link_up\");\n\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\t\tret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,\n\t\t\t\t\t\t\t\t &duplex);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (speed == SPEED_1000)\n\t\t\tret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);\n\t\telse\n\t\t\tret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_cfg_kmrn_10_100_80003es2lan - Apply \"quirks\" for 10/100 operation\n * @hw: pointer to the HW structure\n * @duplex: current duplex setting\n *\n * Configure the KMRN interface by applying last minute quirks for\n * 10/100 operation.\n **/\nSTATIC s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)\n{\n\ts32 ret_val;\n\tu32 tipg;\n\tu32 i = 0;\n\tu16 reg_data, reg_data2;\n\n\tDEBUGFUNC(\"e1000_configure_kmrn_for_10_100\");\n\n\treg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;\n\tret_val =\n\t e1000_write_kmrn_reg_80003es2lan(hw,\n\t\t\t\t\t E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,\n\t\t\t\t\t reg_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Configure Transmit Inter-Packet Gap */\n\ttipg = E1000_READ_REG(hw, E1000_TIPG);\n\ttipg &= ~E1000_TIPG_IPGT_MASK;\n\ttipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;\n\tE1000_WRITE_REG(hw, E1000_TIPG, tipg);\n\n\tdo {\n\t\tret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,\n\t\t\t\t\t ®_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,\n\t\t\t\t\t ®_data2);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\ti++;\n\t} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));\n\n\tif (duplex == HALF_DUPLEX)\n\t\treg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;\n\telse\n\t\treg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;\n\n\treturn hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);\n}\n\n/**\n * e1000_cfg_kmrn_1000_80003es2lan - Apply \"quirks\" for gigabit operation\n * @hw: pointer to the HW structure\n *\n * Configure the KMRN interface by applying last minute quirks for\n * gigabit operation.\n **/\nSTATIC s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 reg_data, reg_data2;\n\tu32 tipg;\n\tu32 i = 0;\n\n\tDEBUGFUNC(\"e1000_configure_kmrn_for_1000\");\n\n\treg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;\n\tret_val =\n\t e1000_write_kmrn_reg_80003es2lan(hw,\n\t\t\t\t\t E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,\n\t\t\t\t\t reg_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Configure Transmit Inter-Packet Gap */\n\ttipg = E1000_READ_REG(hw, E1000_TIPG);\n\ttipg &= ~E1000_TIPG_IPGT_MASK;\n\ttipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;\n\tE1000_WRITE_REG(hw, E1000_TIPG, tipg);\n\n\tdo {\n\t\tret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,\n\t\t\t\t\t ®_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,\n\t\t\t\t\t ®_data2);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\ti++;\n\t} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));\n\n\treg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;\n\n\treturn hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);\n}\n\n/**\n * e1000_read_kmrn_reg_80003es2lan - Read kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Acquire semaphore, then read the PHY register at offset\n * using the kumeran interface. The information retrieved is stored in data.\n * Release the semaphore before exiting.\n **/\nSTATIC s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 *data)\n{\n\tu32 kmrnctrlsta;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_read_kmrn_reg_80003es2lan\");\n\n\tret_val = e1000_acquire_mac_csr_80003es2lan(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tkmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &\n\t\t E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;\n\tE1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);\n\tE1000_WRITE_FLUSH(hw);\n\n\tusec_delay(2);\n\n\tkmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);\n\t*data = (u16)kmrnctrlsta;\n\n\te1000_release_mac_csr_80003es2lan(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_kmrn_reg_80003es2lan - Write kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Acquire semaphore, then write the data to PHY register\n * at the offset using the kumeran interface. Release semaphore\n * before exiting.\n **/\nSTATIC s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 data)\n{\n\tu32 kmrnctrlsta;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_write_kmrn_reg_80003es2lan\");\n\n\tret_val = e1000_acquire_mac_csr_80003es2lan(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tkmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &\n\t\t E1000_KMRNCTRLSTA_OFFSET) | data;\n\tE1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);\n\tE1000_WRITE_FLUSH(hw);\n\n\tusec_delay(2);\n\n\te1000_release_mac_csr_80003es2lan(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_mac_addr_80003es2lan - Read device MAC address\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_read_mac_addr_80003es2lan\");\n\n\t/* If there's an alternate MAC address place it in RAR0\n\t * so that it will override the Si installed default perm\n\t * address.\n\t */\n\tret_val = e1000_check_alt_mac_addr_generic(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn e1000_read_mac_addr_generic(hw);\n}\n\n/**\n * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down\n * @hw: pointer to the HW structure\n *\n * In the case of a PHY power down to save power, or to turn off link during a\n * driver unload, or wake on lan is not enabled, remove the link.\n **/\nSTATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)\n{\n\t/* If the management interface is not enabled, then power down */\n\tif (!(hw->mac.ops.check_mng_mode(hw) ||\n\t hw->phy.ops.check_reset_block(hw)))\n\t\te1000_power_down_phy_copper(hw);\n\n\treturn;\n}\n\n/**\n * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters\n * @hw: pointer to the HW structure\n *\n * Clears the hardware counters by reading the counter registers.\n **/\nSTATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_clear_hw_cntrs_80003es2lan\");\n\n\te1000_clear_hw_cntrs_base_generic(hw);\n\n\tE1000_READ_REG(hw, E1000_PRC64);\n\tE1000_READ_REG(hw, E1000_PRC127);\n\tE1000_READ_REG(hw, E1000_PRC255);\n\tE1000_READ_REG(hw, E1000_PRC511);\n\tE1000_READ_REG(hw, E1000_PRC1023);\n\tE1000_READ_REG(hw, E1000_PRC1522);\n\tE1000_READ_REG(hw, E1000_PTC64);\n\tE1000_READ_REG(hw, E1000_PTC127);\n\tE1000_READ_REG(hw, E1000_PTC255);\n\tE1000_READ_REG(hw, E1000_PTC511);\n\tE1000_READ_REG(hw, E1000_PTC1023);\n\tE1000_READ_REG(hw, E1000_PTC1522);\n\n\tE1000_READ_REG(hw, E1000_ALGNERRC);\n\tE1000_READ_REG(hw, E1000_RXERRC);\n\tE1000_READ_REG(hw, E1000_TNCRS);\n\tE1000_READ_REG(hw, E1000_CEXTERR);\n\tE1000_READ_REG(hw, E1000_TSCTC);\n\tE1000_READ_REG(hw, E1000_TSCTFC);\n\n\tE1000_READ_REG(hw, E1000_MGTPRC);\n\tE1000_READ_REG(hw, E1000_MGTPDC);\n\tE1000_READ_REG(hw, E1000_MGTPTC);\n\n\tE1000_READ_REG(hw, E1000_IAC);\n\tE1000_READ_REG(hw, E1000_ICRXOC);\n\n\tE1000_READ_REG(hw, E1000_ICRXPTC);\n\tE1000_READ_REG(hw, E1000_ICRXATC);\n\tE1000_READ_REG(hw, E1000_ICTXPTC);\n\tE1000_READ_REG(hw, E1000_ICTXATC);\n\tE1000_READ_REG(hw, E1000_ICTXQEC);\n\tE1000_READ_REG(hw, E1000_ICTXQMTC);\n\tE1000_READ_REG(hw, E1000_ICRXDMTC);\n}\n" }, { "path": "drivers/net/e1000/base/e1000_80003es2lan.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_80003ES2LAN_H_\n#define _E1000_80003ES2LAN_H_\n\n#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL\t0x00\n#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL\t0x02\n#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL\t0x10\n#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE\t0x1F\n\n#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS\t0x0008\n#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS\t0x0800\n#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING\t0x0010\n\n#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004\n#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT\t0x0000\n#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE\t\t0x2000\n\n#define E1000_KMRNCTRLSTA_OPMODE_MASK\t\t0x000C\n#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO\t0x0004\n\n#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */\n#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN\t0x00010000\n\n#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN\t0x8\n#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN\t0x9\n\n/* GG82563 PHY Specific Status Register (Page 0, Register 16 */\n#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE\t0x0002 /* 1=Reversal Dis */\n#define GG82563_PSCR_CROSSOVER_MODE_MASK\t0x0060\n#define GG82563_PSCR_CROSSOVER_MODE_MDI\t\t0x0000 /* 00=Manual MDI */\n#define GG82563_PSCR_CROSSOVER_MODE_MDIX\t0x0020 /* 01=Manual MDIX */\n#define GG82563_PSCR_CROSSOVER_MODE_AUTO\t0x0060 /* 11=Auto crossover */\n\n/* PHY Specific Control Register 2 (Page 0, Register 26) */\n#define GG82563_PSCR2_REVERSE_AUTO_NEG\t\t0x2000 /* 1=Reverse Auto-Neg */\n\n/* MAC Specific Control Register (Page 2, Register 21) */\n/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */\n#define GG82563_MSCR_TX_CLK_MASK\t\t0x0007\n#define GG82563_MSCR_TX_CLK_10MBPS_2_5\t\t0x0004\n#define GG82563_MSCR_TX_CLK_100MBPS_25\t\t0x0005\n#define GG82563_MSCR_TX_CLK_1000MBPS_25\t\t0x0007\n\n#define GG82563_MSCR_ASSERT_CRS_ON_TX\t\t0x0010 /* 1=Assert */\n\n/* DSP Distance Register (Page 5, Register 26)\n * 0 = <50M\n * 1 = 50-80M\n * 2 = 80-100M\n * 3 = 110-140M\n * 4 = >140M\n */\n#define GG82563_DSPD_CABLE_LENGTH\t\t0x0007\n\n/* Kumeran Mode Control Register (Page 193, Register 16) */\n#define GG82563_KMCR_PASS_FALSE_CARRIER\t\t0x0800\n\n/* Max number of times Kumeran read/write should be validated */\n#define GG82563_MAX_KMRN_RETRY\t\t\t0x5\n\n/* Power Management Control Register (Page 193, Register 20) */\n/* 1=Enable SERDES Electrical Idle */\n#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE\t0x0001\n\n/* In-Band Control Register (Page 194, Register 18) */\n#define GG82563_ICR_DIS_PADDING\t\t\t0x0010 /* Disable Padding */\n\n#endif\n" }, { "path": "drivers/net/e1000/base/e1000_82540.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n/*\n * 82540EM Gigabit Ethernet Controller\n * 82540EP Gigabit Ethernet Controller\n * 82545EM Gigabit Ethernet Controller (Copper)\n * 82545EM Gigabit Ethernet Controller (Fiber)\n * 82545GM Gigabit Ethernet Controller\n * 82546EB Gigabit Ethernet Controller (Copper)\n * 82546EB Gigabit Ethernet Controller (Fiber)\n * 82546GB Gigabit Ethernet Controller\n */\n\n#include \"e1000_api.h\"\n\nSTATIC s32 e1000_init_phy_params_82540(struct e1000_hw *hw);\nSTATIC s32 e1000_init_nvm_params_82540(struct e1000_hw *hw);\nSTATIC s32 e1000_init_mac_params_82540(struct e1000_hw *hw);\nSTATIC s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);\nSTATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);\nSTATIC s32 e1000_init_hw_82540(struct e1000_hw *hw);\nSTATIC s32 e1000_reset_hw_82540(struct e1000_hw *hw);\nSTATIC s32 e1000_set_phy_mode_82540(struct e1000_hw *hw);\nSTATIC s32 e1000_set_vco_speed_82540(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_copper_link_82540(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);\nSTATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);\nSTATIC s32 e1000_read_mac_addr_82540(struct e1000_hw *hw);\n\n/**\n * e1000_init_phy_params_82540 - Init PHY func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_phy_params_82540(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\n\tphy->addr\t\t= 1;\n\tphy->autoneg_mask\t= AUTONEG_ADVERTISE_SPEED_DEFAULT;\n\tphy->reset_delay_us\t= 10000;\n\tphy->type\t\t= e1000_phy_m88;\n\n\t/* Function Pointers */\n\tphy->ops.check_polarity\t= e1000_check_polarity_m88;\n\tphy->ops.commit\t\t= e1000_phy_sw_reset_generic;\n\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;\n\tphy->ops.get_cable_length = e1000_get_cable_length_m88;\n\tphy->ops.get_cfg_done\t= e1000_get_cfg_done_generic;\n\tphy->ops.read_reg\t= e1000_read_phy_reg_m88;\n\tphy->ops.reset\t\t= e1000_phy_hw_reset_generic;\n\tphy->ops.write_reg\t= e1000_write_phy_reg_m88;\n\tphy->ops.get_info\t= e1000_get_phy_info_m88;\n\tphy->ops.power_up\t= e1000_power_up_phy_copper;\n\tphy->ops.power_down\t= e1000_power_down_phy_copper_82540;\n\n\tret_val = e1000_get_phy_id(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/* Verify phy id */\n\tswitch (hw->mac.type) {\n\tcase e1000_82540:\n\tcase e1000_82545:\n\tcase e1000_82545_rev_3:\n\tcase e1000_82546:\n\tcase e1000_82546_rev_3:\n\t\tif (phy->id == M88E1011_I_PHY_ID)\n\t\t\tbreak;\n\t\t/* Fall Through */\n\tdefault:\n\t\tret_val = -E1000_ERR_PHY;\n\t\tgoto out;\n\t\tbreak;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_nvm_params_82540 - Init NVM func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\n\tDEBUGFUNC(\"e1000_init_nvm_params_82540\");\n\n\tnvm->type = e1000_nvm_eeprom_microwire;\n\tnvm->delay_usec = 50;\n\tnvm->opcode_bits = 3;\n\tswitch (nvm->override) {\n\tcase e1000_nvm_override_microwire_large:\n\t\tnvm->address_bits = 8;\n\t\tnvm->word_size = 256;\n\t\tbreak;\n\tcase e1000_nvm_override_microwire_small:\n\t\tnvm->address_bits = 6;\n\t\tnvm->word_size = 64;\n\t\tbreak;\n\tdefault:\n\t\tnvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;\n\t\tnvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;\n\t\tbreak;\n\t}\n\n\t/* Function Pointers */\n\tnvm->ops.acquire\t= e1000_acquire_nvm_generic;\n\tnvm->ops.read\t\t= e1000_read_nvm_microwire;\n\tnvm->ops.release\t= e1000_release_nvm_generic;\n\tnvm->ops.update\t\t= e1000_update_nvm_checksum_generic;\n\tnvm->ops.valid_led_default = e1000_valid_led_default_generic;\n\tnvm->ops.validate\t= e1000_validate_nvm_checksum_generic;\n\tnvm->ops.write\t\t= e1000_write_nvm_microwire;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_mac_params_82540 - Init MAC func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_mac_params_82540(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_init_mac_params_82540\");\n\n\t/* Set media type */\n\tswitch (hw->device_id) {\n\tcase E1000_DEV_ID_82545EM_FIBER:\n\tcase E1000_DEV_ID_82545GM_FIBER:\n\tcase E1000_DEV_ID_82546EB_FIBER:\n\tcase E1000_DEV_ID_82546GB_FIBER:\n\t\thw->phy.media_type = e1000_media_type_fiber;\n\t\tbreak;\n\tcase E1000_DEV_ID_82545GM_SERDES:\n\tcase E1000_DEV_ID_82546GB_SERDES:\n\t\thw->phy.media_type = e1000_media_type_internal_serdes;\n\t\tbreak;\n\tdefault:\n\t\thw->phy.media_type = e1000_media_type_copper;\n\t\tbreak;\n\t}\n\n\t/* Set mta register count */\n\tmac->mta_reg_count = 128;\n\t/* Set rar entry count */\n\tmac->rar_entry_count = E1000_RAR_ENTRIES;\n\n\t/* Function pointers */\n\n\t/* bus type/speed/width */\n\tmac->ops.get_bus_info = e1000_get_bus_info_pci_generic;\n\t/* function id */\n\tmac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;\n\t/* reset */\n\tmac->ops.reset_hw = e1000_reset_hw_82540;\n\t/* hw initialization */\n\tmac->ops.init_hw = e1000_init_hw_82540;\n\t/* link setup */\n\tmac->ops.setup_link = e1000_setup_link_generic;\n\t/* physical interface setup */\n\tmac->ops.setup_physical_interface =\n\t\t(hw->phy.media_type == e1000_media_type_copper)\n\t\t\t? e1000_setup_copper_link_82540\n\t\t\t: e1000_setup_fiber_serdes_link_82540;\n\t/* check for link */\n\tswitch (hw->phy.media_type) {\n\tcase e1000_media_type_copper:\n\t\tmac->ops.check_for_link = e1000_check_for_copper_link_generic;\n\t\tbreak;\n\tcase e1000_media_type_fiber:\n\t\tmac->ops.check_for_link = e1000_check_for_fiber_link_generic;\n\t\tbreak;\n\tcase e1000_media_type_internal_serdes:\n\t\tmac->ops.check_for_link = e1000_check_for_serdes_link_generic;\n\t\tbreak;\n\tdefault:\n\t\tret_val = -E1000_ERR_CONFIG;\n\t\tgoto out;\n\t\tbreak;\n\t}\n\t/* link info */\n\tmac->ops.get_link_up_info =\n\t\t(hw->phy.media_type == e1000_media_type_copper)\n\t\t\t? e1000_get_speed_and_duplex_copper_generic\n\t\t\t: e1000_get_speed_and_duplex_fiber_serdes_generic;\n\t/* multicast address update */\n\tmac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;\n\t/* writing VFTA */\n\tmac->ops.write_vfta = e1000_write_vfta_generic;\n\t/* clearing VFTA */\n\tmac->ops.clear_vfta = e1000_clear_vfta_generic;\n\t/* read mac address */\n\tmac->ops.read_mac_addr = e1000_read_mac_addr_82540;\n\t/* ID LED init */\n\tmac->ops.id_led_init = e1000_id_led_init_generic;\n\t/* setup LED */\n\tmac->ops.setup_led = e1000_setup_led_generic;\n\t/* cleanup LED */\n\tmac->ops.cleanup_led = e1000_cleanup_led_generic;\n\t/* turn on/off LED */\n\tmac->ops.led_on = e1000_led_on_generic;\n\tmac->ops.led_off = e1000_led_off_generic;\n\t/* clear hardware counters */\n\tmac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_function_pointers_82540 - Init func ptrs.\n * @hw: pointer to the HW structure\n *\n * Called to initialize all function pointers and parameters.\n **/\nvoid e1000_init_function_pointers_82540(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_function_pointers_82540\");\n\n\thw->mac.ops.init_params = e1000_init_mac_params_82540;\n\thw->nvm.ops.init_params = e1000_init_nvm_params_82540;\n\thw->phy.ops.init_params = e1000_init_phy_params_82540;\n}\n\n/**\n * e1000_reset_hw_82540 - Reset hardware\n * @hw: pointer to the HW structure\n *\n * This resets the hardware into a known state.\n **/\nSTATIC s32 e1000_reset_hw_82540(struct e1000_hw *hw)\n{\n\tu32 ctrl, manc;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_reset_hw_82540\");\n\n\tDEBUGOUT(\"Masking off all interrupts\\n\");\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);\n\n\tE1000_WRITE_REG(hw, E1000_RCTL, 0);\n\tE1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/*\n\t * Delay to allow any outstanding PCI transactions to complete\n\t * before resetting the device.\n\t */\n\tmsec_delay(10);\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\tDEBUGOUT(\"Issuing a global reset to 82540/82545/82546 MAC\\n\");\n\tswitch (hw->mac.type) {\n\tcase e1000_82545_rev_3:\n\tcase e1000_82546_rev_3:\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);\n\t\tbreak;\n\tdefault:\n\t\t/*\n\t\t * These controllers can't ack the 64-bit write when\n\t\t * issuing the reset, so we use IO-mapping as a\n\t\t * workaround to issue the reset.\n\t\t */\n\t\tE1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);\n\t\tbreak;\n\t}\n\n\t/* Wait for EEPROM reload */\n\tmsec_delay(5);\n\n\t/* Disable HW ARPs on ASF enabled adapters */\n\tmanc = E1000_READ_REG(hw, E1000_MANC);\n\tmanc &= ~E1000_MANC_ARP_EN;\n\tE1000_WRITE_REG(hw, E1000_MANC, manc);\n\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\tE1000_READ_REG(hw, E1000_ICR);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_hw_82540 - Initialize hardware\n * @hw: pointer to the HW structure\n *\n * This inits the hardware readying it for operation.\n **/\nSTATIC s32 e1000_init_hw_82540(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 txdctl, ctrl_ext;\n\ts32 ret_val;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_init_hw_82540\");\n\n\t/* Initialize identification LED */\n\tret_val = mac->ops.id_led_init(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error initializing identification LED\\n\");\n\t\t/* This is not fatal and we should not stop init due to this */\n\t}\n\n\t/* Disabling VLAN filtering */\n\tDEBUGOUT(\"Initializing the IEEE VLAN\\n\");\n\tif (mac->type < e1000_82545_rev_3)\n\t\tE1000_WRITE_REG(hw, E1000_VET, 0);\n\n\tmac->ops.clear_vfta(hw);\n\n\t/* Setup the receive address. */\n\te1000_init_rx_addrs_generic(hw, mac->rar_entry_count);\n\n\t/* Zero out the Multicast HASH table */\n\tDEBUGOUT(\"Zeroing the MTA\\n\");\n\tfor (i = 0; i < mac->mta_reg_count; i++) {\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);\n\t\t/*\n\t\t * Avoid back to back register writes by adding the register\n\t\t * read (flush). This is to protect against some strange\n\t\t * bridge configurations that may issue Memory Write Block\n\t\t * (MWB) to our register space. The *_rev_3 hardware at\n\t\t * least doesn't respond correctly to every other dword in an\n\t\t * MWB to our register space.\n\t\t */\n\t\tE1000_WRITE_FLUSH(hw);\n\t}\n\n\tif (mac->type < e1000_82545_rev_3)\n\t\te1000_pcix_mmrbc_workaround_generic(hw);\n\n\t/* Setup link and flow control */\n\tret_val = mac->ops.setup_link(hw);\n\n\ttxdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));\n\ttxdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |\n\t\t E1000_TXDCTL_FULL_TX_DESC_WB;\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);\n\n\t/*\n\t * Clear all of the statistics registers (clear on read). It is\n\t * important that we do this after we have tried to establish link\n\t * because the symbol error count will increment wildly if there\n\t * is no link.\n\t */\n\te1000_clear_hw_cntrs_82540(hw);\n\n\tif ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||\n\t (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {\n\t\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\t/*\n\t\t * Relaxed ordering must be disabled to avoid a parity\n\t\t * error crash in a PCI slot.\n\t\t */\n\t\tctrl_ext |= E1000_CTRL_EXT_RO_DIS;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_copper_link_82540 - Configure copper link settings\n * @hw: pointer to the HW structure\n *\n * Calls the appropriate function to configure the link for auto-neg or forced\n * speed and duplex. Then we check for link, once link is established calls\n * to configure collision distance and flow control are called. If link is\n * not established, we return -E1000_ERR_PHY (-2).\n **/\nSTATIC s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_setup_copper_link_82540\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= E1000_CTRL_SLU;\n\tctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\tret_val = e1000_set_phy_mode_82540(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (hw->mac.type == e1000_82545_rev_3 ||\n\t hw->mac.type == e1000_82546_rev_3) {\n\t\tret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,\n\t\t\t\t\t &data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t\tdata |= 0x00000008;\n\t\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,\n\t\t\t\t\t\tdata);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t}\n\n\tret_val = e1000_copper_link_setup_m88(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_setup_copper_link_generic(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes\n * @hw: pointer to the HW structure\n *\n * Set the output amplitude to the value in the EEPROM and adjust the VCO\n * speed to improve Bit Error Rate (BER) performance. Configures collision\n * distance and flow control for fiber and serdes links. Upon successful\n * setup, poll for link.\n **/\nSTATIC s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_setup_fiber_serdes_link_82540\");\n\n\tswitch (mac->type) {\n\tcase e1000_82545_rev_3:\n\tcase e1000_82546_rev_3:\n\t\tif (hw->phy.media_type == e1000_media_type_internal_serdes) {\n\t\t\t/*\n\t\t\t * If we're on serdes media, adjust the output\n\t\t\t * amplitude to value set in the EEPROM.\n\t\t\t */\n\t\t\tret_val = e1000_adjust_serdes_amplitude_82540(hw);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t}\n\t\t/* Adjust VCO speed to improve BER performance */\n\t\tret_val = e1000_set_vco_speed_82540(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tret_val = e1000_setup_fiber_serdes_link_generic(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM\n * @hw: pointer to the HW structure\n *\n * Adjust the SERDES output amplitude based on the EEPROM settings.\n **/\nSTATIC s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 nvm_data;\n\n\tDEBUGFUNC(\"e1000_adjust_serdes_amplitude_82540\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (nvm_data != NVM_RESERVED_WORD) {\n\t\t/* Adjust serdes output amplitude only. */\n\t\tnvm_data &= NVM_SERDES_AMPLITUDE_MASK;\n\t\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,\n\t\t\t\t\t\tnvm_data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_set_vco_speed_82540 - Set VCO speed for better performance\n * @hw: pointer to the HW structure\n *\n * Set the VCO speed to improve Bit Error Rate (BER) performance.\n **/\nSTATIC s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 default_page = 0;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_set_vco_speed_82540\");\n\n\t/* Set PHY register 30, page 5, bit 8 to 0 */\n\n\tret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,\n\t\t\t\t &default_page);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);\n\tif (ret_val)\n\t\tgoto out;\n\n\tphy_data &= ~M88E1000_PHY_VCO_REG_BIT8;\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/* Set PHY register 30, page 4, bit 11 to 1 */\n\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);\n\tif (ret_val)\n\t\tgoto out;\n\n\tphy_data |= M88E1000_PHY_VCO_REG_BIT11;\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,\n\t\t\t\t\tdefault_page);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_set_phy_mode_82540 - Set PHY to class A mode\n * @hw: pointer to the HW structure\n *\n * Sets the PHY to class A mode and assumes the following operations will\n * follow to enable the new class mode:\n * 1. Do a PHY soft reset.\n * 2. Restart auto-negotiation or force link.\n **/\nSTATIC s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 nvm_data;\n\n\tDEBUGFUNC(\"e1000_set_phy_mode_82540\");\n\n\tif (hw->mac.type != e1000_82545_rev_3)\n\t\tgoto out;\n\n\tret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);\n\tif (ret_val) {\n\t\tret_val = -E1000_ERR_PHY;\n\t\tgoto out;\n\t}\n\n\tif ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {\n\t\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,\n\t\t\t\t\t\t0x000B);\n\t\tif (ret_val) {\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\t\tgoto out;\n\t\t}\n\t\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,\n\t\t\t\t\t\t0x8104);\n\t\tif (ret_val) {\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\t\tgoto out;\n\t\t}\n\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down\n * @hw: pointer to the HW structure\n *\n * In the case of a PHY power down to save power, or to turn off link during a\n * driver unload, or wake on lan is not enabled, remove the link.\n **/\nSTATIC void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)\n{\n\t/* If the management interface is not enabled, then power down */\n\tif (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))\n\t\te1000_power_down_phy_copper(hw);\n\n\treturn;\n}\n\n/**\n * e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters\n * @hw: pointer to the HW structure\n *\n * Clears the hardware counters by reading the counter registers.\n **/\nSTATIC void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_clear_hw_cntrs_82540\");\n\n\te1000_clear_hw_cntrs_base_generic(hw);\n\n\tE1000_READ_REG(hw, E1000_PRC64);\n\tE1000_READ_REG(hw, E1000_PRC127);\n\tE1000_READ_REG(hw, E1000_PRC255);\n\tE1000_READ_REG(hw, E1000_PRC511);\n\tE1000_READ_REG(hw, E1000_PRC1023);\n\tE1000_READ_REG(hw, E1000_PRC1522);\n\tE1000_READ_REG(hw, E1000_PTC64);\n\tE1000_READ_REG(hw, E1000_PTC127);\n\tE1000_READ_REG(hw, E1000_PTC255);\n\tE1000_READ_REG(hw, E1000_PTC511);\n\tE1000_READ_REG(hw, E1000_PTC1023);\n\tE1000_READ_REG(hw, E1000_PTC1522);\n\n\tE1000_READ_REG(hw, E1000_ALGNERRC);\n\tE1000_READ_REG(hw, E1000_RXERRC);\n\tE1000_READ_REG(hw, E1000_TNCRS);\n\tE1000_READ_REG(hw, E1000_CEXTERR);\n\tE1000_READ_REG(hw, E1000_TSCTC);\n\tE1000_READ_REG(hw, E1000_TSCTFC);\n\n\tE1000_READ_REG(hw, E1000_MGTPRC);\n\tE1000_READ_REG(hw, E1000_MGTPDC);\n\tE1000_READ_REG(hw, E1000_MGTPTC);\n}\n\n/**\n * e1000_read_mac_addr_82540 - Read device MAC address\n * @hw: pointer to the HW structure\n *\n * Reads the device MAC address from the EEPROM and stores the value.\n * Since devices with two ports use the same EEPROM, we increment the\n * last bit in the MAC address for the second port.\n *\n * This version is being used over generic because of customer issues\n * with VmWare and Virtual Box when using generic. It seems in\n * the emulated 82545, RAR[0] does NOT have a valid address after a\n * reset, this older method works and using this breaks nothing for\n * these legacy adapters.\n **/\ns32 e1000_read_mac_addr_82540(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 offset, nvm_data, i;\n\n\tDEBUGFUNC(\"e1000_read_mac_addr\");\n\n\tfor (i = 0; i < ETH_ADDR_LEN; i += 2) {\n\t\toffset = i >> 1;\n\t\tret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\tgoto out;\n\t\t}\n\t\thw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);\n\t\thw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);\n\t}\n\n\t/* Flip last bit of mac address if we're on second port */\n\tif (hw->bus.func == E1000_FUNC_1)\n\t\thw->mac.perm_addr[5] ^= 1;\n\n\tfor (i = 0; i < ETH_ADDR_LEN; i++)\n\t\thw->mac.addr[i] = hw->mac.perm_addr[i];\n\nout:\n\treturn ret_val;\n}\n" }, { "path": "drivers/net/e1000/base/e1000_82541.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n/*\n * 82541EI Gigabit Ethernet Controller\n * 82541ER Gigabit Ethernet Controller\n * 82541GI Gigabit Ethernet Controller\n * 82541PI Gigabit Ethernet Controller\n * 82547EI Gigabit Ethernet Controller\n * 82547GI Gigabit Ethernet Controller\n */\n\n#include \"e1000_api.h\"\n\nSTATIC s32 e1000_init_phy_params_82541(struct e1000_hw *hw);\nSTATIC s32 e1000_init_nvm_params_82541(struct e1000_hw *hw);\nSTATIC s32 e1000_init_mac_params_82541(struct e1000_hw *hw);\nSTATIC s32 e1000_reset_hw_82541(struct e1000_hw *hw);\nSTATIC s32 e1000_init_hw_82541(struct e1000_hw *hw);\nSTATIC s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\t u16 *duplex);\nSTATIC s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_copper_link_82541(struct e1000_hw *hw);\nSTATIC s32 e1000_check_for_link_82541(struct e1000_hw *hw);\nSTATIC s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw);\nSTATIC s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,\n\t\t\t\t\t bool active);\nSTATIC s32 e1000_setup_led_82541(struct e1000_hw *hw);\nSTATIC s32 e1000_cleanup_led_82541(struct e1000_hw *hw);\nSTATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);\nSTATIC s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,\n\t\t\t\t\t\t bool link_up);\nSTATIC s32 e1000_phy_init_script_82541(struct e1000_hw *hw);\nSTATIC void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);\n\nSTATIC const u16 e1000_igp_cable_length_table[] = {\n\t5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10,\n\t10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 25, 25, 25, 25, 30, 30, 30, 30,\n\t40, 40, 40, 40, 40, 40, 40, 40, 40, 50, 50, 50, 50, 50, 50, 50, 60, 60,\n\t60, 60, 60, 60, 60, 60, 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80,\n\t80, 90, 90, 90, 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100,\n\t100, 100, 100, 100, 100, 100, 100, 100, 110, 110, 110, 110, 110, 110,\n\t110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 120, 120,\n\t120, 120, 120, 120, 120, 120, 120, 120};\n#define IGP01E1000_AGC_LENGTH_TABLE_SIZE \\\n\t\t(sizeof(e1000_igp_cable_length_table) / \\\n\t\t sizeof(e1000_igp_cable_length_table[0]))\n\n/**\n * e1000_init_phy_params_82541 - Init PHY func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_phy_params_82541(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_init_phy_params_82541\");\n\n\tphy->addr\t\t= 1;\n\tphy->autoneg_mask\t= AUTONEG_ADVERTISE_SPEED_DEFAULT;\n\tphy->reset_delay_us\t= 10000;\n\tphy->type\t\t= e1000_phy_igp;\n\n\t/* Function Pointers */\n\tphy->ops.check_polarity\t= e1000_check_polarity_igp;\n\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;\n\tphy->ops.get_cable_length = e1000_get_cable_length_igp_82541;\n\tphy->ops.get_cfg_done\t= e1000_get_cfg_done_generic;\n\tphy->ops.get_info\t= e1000_get_phy_info_igp;\n\tphy->ops.read_reg\t= e1000_read_phy_reg_igp;\n\tphy->ops.reset\t\t= e1000_phy_hw_reset_82541;\n\tphy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;\n\tphy->ops.write_reg\t= e1000_write_phy_reg_igp;\n\tphy->ops.power_up\t= e1000_power_up_phy_copper;\n\tphy->ops.power_down\t= e1000_power_down_phy_copper_82541;\n\n\tret_val = e1000_get_phy_id(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/* Verify phy id */\n\tif (phy->id != IGP01E1000_I_PHY_ID) {\n\t\tret_val = -E1000_ERR_PHY;\n\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_nvm_params_82541 - Init NVM func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\tu16 size;\n\n\tDEBUGFUNC(\"e1000_init_nvm_params_82541\");\n\n\tswitch (nvm->override) {\n\tcase e1000_nvm_override_spi_large:\n\t\tnvm->type = e1000_nvm_eeprom_spi;\n\t\teecd |= E1000_EECD_ADDR_BITS;\n\t\tbreak;\n\tcase e1000_nvm_override_spi_small:\n\t\tnvm->type = e1000_nvm_eeprom_spi;\n\t\teecd &= ~E1000_EECD_ADDR_BITS;\n\t\tbreak;\n\tcase e1000_nvm_override_microwire_large:\n\t\tnvm->type = e1000_nvm_eeprom_microwire;\n\t\teecd |= E1000_EECD_SIZE;\n\t\tbreak;\n\tcase e1000_nvm_override_microwire_small:\n\t\tnvm->type = e1000_nvm_eeprom_microwire;\n\t\teecd &= ~E1000_EECD_SIZE;\n\t\tbreak;\n\tdefault:\n\t\tnvm->type = eecd & E1000_EECD_TYPE ? e1000_nvm_eeprom_spi\n\t\t\t : e1000_nvm_eeprom_microwire;\n\t\tbreak;\n\t}\n\n\tif (nvm->type == e1000_nvm_eeprom_spi) {\n\t\tnvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 16 : 8;\n\t\tnvm->delay_usec = 1;\n\t\tnvm->opcode_bits = 8;\n\t\tnvm->page_size = (eecd & E1000_EECD_ADDR_BITS) ? 32 : 8;\n\n\t\t/* Function Pointers */\n\t\tnvm->ops.acquire\t= e1000_acquire_nvm_generic;\n\t\tnvm->ops.read\t\t= e1000_read_nvm_spi;\n\t\tnvm->ops.release\t= e1000_release_nvm_generic;\n\t\tnvm->ops.update\t\t= e1000_update_nvm_checksum_generic;\n\t\tnvm->ops.valid_led_default = e1000_valid_led_default_generic;\n\t\tnvm->ops.validate\t= e1000_validate_nvm_checksum_generic;\n\t\tnvm->ops.write\t\t= e1000_write_nvm_spi;\n\n\t\t/*\n\t\t * nvm->word_size must be discovered after the pointers\n\t\t * are set so we can verify the size from the nvm image\n\t\t * itself. Temporarily set it to a dummy value so the\n\t\t * read will work.\n\t\t */\n\t\tnvm->word_size = 64;\n\t\tret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t\tsize = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;\n\t\t/*\n\t\t * if size != 0, it can be added to a constant and become\n\t\t * the left-shift value to set the word_size. Otherwise,\n\t\t * word_size stays at 64.\n\t\t */\n\t\tif (size) {\n\t\t\tsize += NVM_WORD_SIZE_BASE_SHIFT_82541;\n\t\t\tnvm->word_size = 1 << size;\n\t\t}\n\t} else {\n\t\tnvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 8 : 6;\n\t\tnvm->delay_usec = 50;\n\t\tnvm->opcode_bits = 3;\n\t\tnvm->word_size = (eecd & E1000_EECD_ADDR_BITS) ? 256 : 64;\n\n\t\t/* Function Pointers */\n\t\tnvm->ops.acquire\t= e1000_acquire_nvm_generic;\n\t\tnvm->ops.read\t\t= e1000_read_nvm_microwire;\n\t\tnvm->ops.release\t= e1000_release_nvm_generic;\n\t\tnvm->ops.update\t\t= e1000_update_nvm_checksum_generic;\n\t\tnvm->ops.valid_led_default = e1000_valid_led_default_generic;\n\t\tnvm->ops.validate\t= e1000_validate_nvm_checksum_generic;\n\t\tnvm->ops.write\t\t= e1000_write_nvm_microwire;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_mac_params_82541 - Init MAC func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_mac_params_82541(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"e1000_init_mac_params_82541\");\n\n\t/* Set media type */\n\thw->phy.media_type = e1000_media_type_copper;\n\t/* Set mta register count */\n\tmac->mta_reg_count = 128;\n\t/* Set rar entry count */\n\tmac->rar_entry_count = E1000_RAR_ENTRIES;\n\t/* Set if part includes ASF firmware */\n\tmac->asf_firmware_present = true;\n\n\t/* Function Pointers */\n\n\t/* bus type/speed/width */\n\tmac->ops.get_bus_info = e1000_get_bus_info_pci_generic;\n\t/* function id */\n\tmac->ops.set_lan_id = e1000_set_lan_id_single_port;\n\t/* reset */\n\tmac->ops.reset_hw = e1000_reset_hw_82541;\n\t/* hw initialization */\n\tmac->ops.init_hw = e1000_init_hw_82541;\n\t/* link setup */\n\tmac->ops.setup_link = e1000_setup_link_generic;\n\t/* physical interface link setup */\n\tmac->ops.setup_physical_interface = e1000_setup_copper_link_82541;\n\t/* check for link */\n\tmac->ops.check_for_link = e1000_check_for_link_82541;\n\t/* link info */\n\tmac->ops.get_link_up_info = e1000_get_link_up_info_82541;\n\t/* multicast address update */\n\tmac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;\n\t/* writing VFTA */\n\tmac->ops.write_vfta = e1000_write_vfta_generic;\n\t/* clearing VFTA */\n\tmac->ops.clear_vfta = e1000_clear_vfta_generic;\n\t/* ID LED init */\n\tmac->ops.id_led_init = e1000_id_led_init_generic;\n\t/* setup LED */\n\tmac->ops.setup_led = e1000_setup_led_82541;\n\t/* cleanup LED */\n\tmac->ops.cleanup_led = e1000_cleanup_led_82541;\n\t/* turn on/off LED */\n\tmac->ops.led_on = e1000_led_on_generic;\n\tmac->ops.led_off = e1000_led_off_generic;\n\t/* clear hardware counters */\n\tmac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_function_pointers_82541 - Init func ptrs.\n * @hw: pointer to the HW structure\n *\n * Called to initialize all function pointers and parameters.\n **/\nvoid e1000_init_function_pointers_82541(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_function_pointers_82541\");\n\n\thw->mac.ops.init_params = e1000_init_mac_params_82541;\n\thw->nvm.ops.init_params = e1000_init_nvm_params_82541;\n\thw->phy.ops.init_params = e1000_init_phy_params_82541;\n}\n\n/**\n * e1000_reset_hw_82541 - Reset hardware\n * @hw: pointer to the HW structure\n *\n * This resets the hardware into a known state.\n **/\nSTATIC s32 e1000_reset_hw_82541(struct e1000_hw *hw)\n{\n\tu32 ledctl, ctrl, manc;\n\n\tDEBUGFUNC(\"e1000_reset_hw_82541\");\n\n\tDEBUGOUT(\"Masking off all interrupts\\n\");\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);\n\n\tE1000_WRITE_REG(hw, E1000_RCTL, 0);\n\tE1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/*\n\t * Delay to allow any outstanding PCI transactions to complete\n\t * before resetting the device.\n\t */\n\tmsec_delay(10);\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\t/* Must reset the Phy before resetting the MAC */\n\tif ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tmsec_delay(5);\n\t}\n\n\tDEBUGOUT(\"Issuing a global reset to 82541/82547 MAC\\n\");\n\tswitch (hw->mac.type) {\n\tcase e1000_82541:\n\tcase e1000_82541_rev_2:\n\t\t/*\n\t\t * These controllers can't ack the 64-bit write when\n\t\t * issuing the reset, so we use IO-mapping as a\n\t\t * workaround to issue the reset.\n\t\t */\n\t\tE1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);\n\t\tbreak;\n\tdefault:\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);\n\t\tbreak;\n\t}\n\n\t/* Wait for NVM reload */\n\tmsec_delay(20);\n\n\t/* Disable HW ARPs on ASF enabled adapters */\n\tmanc = E1000_READ_REG(hw, E1000_MANC);\n\tmanc &= ~E1000_MANC_ARP_EN;\n\tE1000_WRITE_REG(hw, E1000_MANC, manc);\n\n\tif ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {\n\t\te1000_phy_init_script_82541(hw);\n\n\t\t/* Configure activity LED after Phy reset */\n\t\tledctl = E1000_READ_REG(hw, E1000_LEDCTL);\n\t\tledctl &= IGP_ACTIVITY_LED_MASK;\n\t\tledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);\n\t\tE1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);\n\t}\n\n\t/* Once again, mask the interrupts */\n\tDEBUGOUT(\"Masking off all interrupts\\n\");\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);\n\n\t/* Clear any pending interrupt events. */\n\tE1000_READ_REG(hw, E1000_ICR);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_hw_82541 - Initialize hardware\n * @hw: pointer to the HW structure\n *\n * This inits the hardware readying it for operation.\n **/\nSTATIC s32 e1000_init_hw_82541(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tstruct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;\n\tu32 i, txdctl;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_init_hw_82541\");\n\n\t/* Initialize identification LED */\n\tret_val = mac->ops.id_led_init(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error initializing identification LED\\n\");\n\t\t/* This is not fatal and we should not stop init due to this */\n\t}\n\n\t/* Storing the Speed Power Down value for later use */\n\tret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,\n\t\t\t\t &dev_spec->spd_default);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/* Disabling VLAN filtering */\n\tDEBUGOUT(\"Initializing the IEEE VLAN\\n\");\n\tmac->ops.clear_vfta(hw);\n\n\t/* Setup the receive address. */\n\te1000_init_rx_addrs_generic(hw, mac->rar_entry_count);\n\n\t/* Zero out the Multicast HASH table */\n\tDEBUGOUT(\"Zeroing the MTA\\n\");\n\tfor (i = 0; i < mac->mta_reg_count; i++) {\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);\n\t\t/*\n\t\t * Avoid back to back register writes by adding the register\n\t\t * read (flush). This is to protect against some strange\n\t\t * bridge configurations that may issue Memory Write Block\n\t\t * (MWB) to our register space.\n\t\t */\n\t\tE1000_WRITE_FLUSH(hw);\n\t}\n\n\t/* Setup link and flow control */\n\tret_val = mac->ops.setup_link(hw);\n\n\ttxdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));\n\ttxdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |\n\t\t E1000_TXDCTL_FULL_TX_DESC_WB;\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);\n\n\t/*\n\t * Clear all of the statistics registers (clear on read). It is\n\t * important that we do this after we have tried to establish link\n\t * because the symbol error count will increment wildly if there\n\t * is no link.\n\t */\n\te1000_clear_hw_cntrs_82541(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_get_link_up_info_82541 - Report speed and duplex\n * @hw: pointer to the HW structure\n * @speed: pointer to speed buffer\n * @duplex: pointer to duplex buffer\n *\n * Retrieve the current speed and duplex configuration.\n **/\nSTATIC s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\tu16 *duplex)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_get_link_up_info_82541\");\n\n\tret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (!phy->speed_downgraded)\n\t\tgoto out;\n\n\t/*\n\t * IGP01 PHY may advertise full duplex operation after speed\n\t * downgrade even if it is operating at half duplex.\n\t * Here we set the duplex settings to match the duplex in the\n\t * link partner's capabilities.\n\t */\n\tret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (!(data & NWAY_ER_LP_NWAY_CAPS)) {\n\t\t*duplex = HALF_DUPLEX;\n\t} else {\n\t\tret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tif (*speed == SPEED_100) {\n\t\t\tif (!(data & NWAY_LPAR_100TX_FD_CAPS))\n\t\t\t\t*duplex = HALF_DUPLEX;\n\t\t} else if (*speed == SPEED_10) {\n\t\t\tif (!(data & NWAY_LPAR_10T_FD_CAPS))\n\t\t\t\t*duplex = HALF_DUPLEX;\n\t\t}\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_hw_reset_82541 - PHY hardware reset\n * @hw: pointer to the HW structure\n *\n * Verify the reset block is not blocking us from resetting. Acquire\n * semaphore (if necessary) and read/set/write the device control reset\n * bit in the PHY. Wait the appropriate delay time for the device to\n * reset and release the semaphore (if necessary).\n **/\nSTATIC s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu32 ledctl;\n\n\tDEBUGFUNC(\"e1000_phy_hw_reset_82541\");\n\n\tret_val = e1000_phy_hw_reset_generic(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\te1000_phy_init_script_82541(hw);\n\n\tif ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {\n\t\t/* Configure activity LED after PHY reset */\n\t\tledctl = E1000_READ_REG(hw, E1000_LEDCTL);\n\t\tledctl &= IGP_ACTIVITY_LED_MASK;\n\t\tledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);\n\t\tE1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_copper_link_82541 - Configure copper link settings\n * @hw: pointer to the HW structure\n *\n * Calls the appropriate function to configure the link for auto-neg or forced\n * speed and duplex. Then we check for link, once link is established calls\n * to configure collision distance and flow control are called. If link is\n * not established, we return -E1000_ERR_PHY (-2).\n **/\nSTATIC s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tstruct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;\n\ts32 ret_val;\n\tu32 ctrl, ledctl;\n\n\tDEBUGFUNC(\"e1000_setup_copper_link_82541\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= E1000_CTRL_SLU;\n\tctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\n\t/* Earlier revs of the IGP phy require us to force MDI. */\n\tif (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {\n\t\tdev_spec->dsp_config = e1000_dsp_config_disabled;\n\t\tphy->mdix = 1;\n\t} else {\n\t\tdev_spec->dsp_config = e1000_dsp_config_enabled;\n\t}\n\n\tret_val = e1000_copper_link_setup_igp(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (hw->mac.autoneg) {\n\t\tif (dev_spec->ffe_config == e1000_ffe_config_active)\n\t\t\tdev_spec->ffe_config = e1000_ffe_config_enabled;\n\t}\n\n\t/* Configure activity LED after Phy reset */\n\tledctl = E1000_READ_REG(hw, E1000_LEDCTL);\n\tledctl &= IGP_ACTIVITY_LED_MASK;\n\tledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);\n\tE1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);\n\n\tret_val = e1000_setup_copper_link_generic(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_link_82541 - Check/Store link connection\n * @hw: pointer to the HW structure\n *\n * This checks the link condition of the adapter and stores the\n * results in the hw->mac structure.\n **/\nSTATIC s32 e1000_check_for_link_82541(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_check_for_link_82541\");\n\n\t/*\n\t * We only want to go out to the PHY registers to see if Auto-Neg\n\t * has completed and/or if our link status has changed. The\n\t * get_link_status flag is set upon receiving a Link Status\n\t * Change or Rx Sequence Error interrupt.\n\t */\n\tif (!mac->get_link_status) {\n\t\tret_val = E1000_SUCCESS;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * First we want to see if the MII Status Register reports\n\t * link. If so, then we want to get the current speed/duplex\n\t * of the PHY.\n\t */\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (!link) {\n\t\tret_val = e1000_config_dsp_after_link_change_82541(hw, false);\n\t\tgoto out; /* No link detected */\n\t}\n\n\tmac->get_link_status = false;\n\n\t/*\n\t * Check if there was DownShift, must be checked\n\t * immediately after link-up\n\t */\n\te1000_check_downshift_generic(hw);\n\n\t/*\n\t * If we are forcing speed/duplex, then we simply return since\n\t * we have already determined whether we have link or not.\n\t */\n\tif (!mac->autoneg) {\n\t\tret_val = -E1000_ERR_CONFIG;\n\t\tgoto out;\n\t}\n\n\tret_val = e1000_config_dsp_after_link_change_82541(hw, true);\n\n\t/*\n\t * Auto-Neg is enabled. Auto Speed Detection takes care\n\t * of MAC speed/duplex configuration. So we only need to\n\t * configure Collision Distance in the MAC.\n\t */\n\tmac->ops.config_collision_dist(hw);\n\n\t/*\n\t * Configure Flow Control now that Auto-Neg has completed.\n\t * First, we need to restore the desired flow control\n\t * settings because we may have had to re-autoneg with a\n\t * different link partner.\n\t */\n\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_config_dsp_after_link_change_82541 - Config DSP after link\n * @hw: pointer to the HW structure\n * @link_up: boolean flag for link up status\n *\n * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS\n * at any other case.\n *\n * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a\n * gigabit link is achieved to improve link quality.\n **/\nSTATIC s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,\n\t\t\t\t\t\t bool link_up)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tstruct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;\n\ts32 ret_val;\n\tu32 idle_errs = 0;\n\tu16 phy_data, phy_saved_data, speed, duplex, i;\n\tu16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;\n\tu16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {\n\t\t\t\t\t\tIGP01E1000_PHY_AGC_PARAM_A,\n\t\t\t\t\t\tIGP01E1000_PHY_AGC_PARAM_B,\n\t\t\t\t\t\tIGP01E1000_PHY_AGC_PARAM_C,\n\t\t\t\t\t\tIGP01E1000_PHY_AGC_PARAM_D};\n\n\tDEBUGFUNC(\"e1000_config_dsp_after_link_change_82541\");\n\n\tif (link_up) {\n\t\tret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error getting link speed and duplex\\n\");\n\t\t\tgoto out;\n\t\t}\n\n\t\tif (speed != SPEED_1000) {\n\t\t\tret_val = E1000_SUCCESS;\n\t\t\tgoto out;\n\t\t}\n\n\t\tret_val = phy->ops.get_cable_length(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tif ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&\n\t\t phy->min_cable_length >= 50) {\n\n\t\t\tfor (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {\n\t\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t\t dsp_reg_array[i],\n\t\t\t\t\t\t\t &phy_data);\n\t\t\t\tif (ret_val)\n\t\t\t\t\tgoto out;\n\n\t\t\t\tphy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;\n\n\t\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t\t dsp_reg_array[i],\n\t\t\t\t\t\t\t phy_data);\n\t\t\t\tif (ret_val)\n\t\t\t\t\tgoto out;\n\t\t\t}\n\t\t\tdev_spec->dsp_config = e1000_dsp_config_activated;\n\t\t}\n\n\t\tif ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||\n\t\t (phy->min_cable_length >= 50)) {\n\t\t\tret_val = E1000_SUCCESS;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/* clear previous idle error counts */\n\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tfor (i = 0; i < ffe_idle_err_timeout; i++) {\n\t\t\tusec_delay(1000);\n\t\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS,\n\t\t\t\t\t\t &phy_data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tidle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);\n\t\t\tif (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {\n\t\t\t\tdev_spec->ffe_config = e1000_ffe_config_active;\n\n\t\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_DSP_FFE,\n\t\t\t\t\t\t IGP01E1000_PHY_DSP_FFE_CM_CP);\n\t\t\t\tif (ret_val)\n\t\t\t\t\tgoto out;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif (idle_errs)\n\t\t\t\tffe_idle_err_timeout =\n\t\t\t\t\t\t FFE_IDLE_ERR_COUNT_TIMEOUT_100;\n\t\t}\n\t} else {\n\t\tif (dev_spec->dsp_config == e1000_dsp_config_activated) {\n\t\t\t/*\n\t\t\t * Save off the current value of register 0x2F5B\n\t\t\t * to be restored at the end of the routines.\n\t\t\t */\n\t\t\tret_val = phy->ops.read_reg(hw, 0x2F5B,\n\t\t\t\t\t\t &phy_saved_data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\t/* Disable the PHY transmitter */\n\t\t\tret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tmsec_delay_irq(20);\n\n\t\t\tret_val = phy->ops.write_reg(hw, 0x0000,\n\t\t\t\t\t\t IGP01E1000_IEEE_FORCE_GIG);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t\tfor (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {\n\t\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t\t dsp_reg_array[i],\n\t\t\t\t\t\t\t &phy_data);\n\t\t\t\tif (ret_val)\n\t\t\t\t\tgoto out;\n\n\t\t\t\tphy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;\n\t\t\t\tphy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;\n\n\t\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t\t dsp_reg_array[i],\n\t\t\t\t\t\t\t phy_data);\n\t\t\t\tif (ret_val)\n\t\t\t\t\tgoto out;\n\t\t\t}\n\n\t\t\tret_val = phy->ops.write_reg(hw, 0x0000,\n\t\t\t\t\t IGP01E1000_IEEE_RESTART_AUTONEG);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tmsec_delay_irq(20);\n\n\t\t\t/* Now enable the transmitter */\n\t\t\tret_val = phy->ops.write_reg(hw, 0x2F5B,\n\t\t\t\t\t\t phy_saved_data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tdev_spec->dsp_config = e1000_dsp_config_enabled;\n\t\t}\n\n\t\tif (dev_spec->ffe_config != e1000_ffe_config_active) {\n\t\t\tret_val = E1000_SUCCESS;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/*\n\t\t * Save off the current value of register 0x2F5B\n\t\t * to be restored at the end of the routines.\n\t\t */\n\t\tret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\t/* Disable the PHY transmitter */\n\t\tret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tmsec_delay_irq(20);\n\n\t\tret_val = phy->ops.write_reg(hw, 0x0000,\n\t\t\t\t\t IGP01E1000_IEEE_FORCE_GIG);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE,\n\t\t\t\t\t IGP01E1000_PHY_DSP_FFE_DEFAULT);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tret_val = phy->ops.write_reg(hw, 0x0000,\n\t\t\t\t\t IGP01E1000_IEEE_RESTART_AUTONEG);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tmsec_delay_irq(20);\n\n\t\t/* Now enable the transmitter */\n\t\tret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);\n\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tdev_spec->ffe_config = e1000_ffe_config_enabled;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY\n * @hw: pointer to the HW structure\n *\n * The automatic gain control (agc) normalizes the amplitude of the\n * received signal, adjusting for the attenuation produced by the\n * cable. By reading the AGC registers, which represent the\n * combination of coarse and fine gain value, the value can be put\n * into a lookup table to obtain the approximate cable length\n * for each channel.\n **/\nSTATIC s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 i, data;\n\tu16 cur_agc_value, agc_value = 0;\n\tu16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;\n\tu16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_A,\n\t\t\t\t\t\t\t IGP01E1000_PHY_AGC_B,\n\t\t\t\t\t\t\t IGP01E1000_PHY_AGC_C,\n\t\t\t\t\t\t\t IGP01E1000_PHY_AGC_D};\n\n\tDEBUGFUNC(\"e1000_get_cable_length_igp_82541\");\n\n\t/* Read the AGC registers for all channels */\n\tfor (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {\n\t\tret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tcur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;\n\n\t\t/* Bounds checking */\n\t\tif ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||\n\t\t (cur_agc_value == 0)) {\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\t\tgoto out;\n\t\t}\n\n\t\tagc_value += cur_agc_value;\n\n\t\tif (min_agc_value > cur_agc_value)\n\t\t\tmin_agc_value = cur_agc_value;\n\t}\n\n\t/* Remove the minimal AGC result for length < 50m */\n\tif (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {\n\t\tagc_value -= min_agc_value;\n\t\t/* Average the three remaining channels for the length. */\n\t\tagc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);\n\t} else {\n\t\t/* Average the channels for the length. */\n\t\tagc_value /= IGP01E1000_PHY_CHANNEL_NUM;\n\t}\n\n\tphy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >\n\t\t\t\t IGP01E1000_AGC_RANGE)\n\t\t\t\t? (e1000_igp_cable_length_table[agc_value] -\n\t\t\t\t IGP01E1000_AGC_RANGE)\n\t\t\t\t: 0;\n\tphy->max_cable_length = e1000_igp_cable_length_table[agc_value] +\n\t\t\t\tIGP01E1000_AGC_RANGE;\n\n\tphy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3\n * @hw: pointer to the HW structure\n * @active: boolean used to enable/disable lplu\n *\n * Success returns 0, Failure returns 1\n *\n * The low power link up (lplu) state is set to the power management level D3\n * and SmartSpeed is disabled when active is true, else clear lplu for D3\n * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU\n * is used during Dx states where the power conservation is most important.\n * During driver activity, SmartSpeed should be enabled so performance is\n * maintained.\n **/\nSTATIC s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_set_d3_lplu_state_82541\");\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82541_rev_2:\n\tcase e1000_82547_rev_2:\n\t\tbreak;\n\tdefault:\n\t\tret_val = e1000_set_d3_lplu_state_generic(hw, active);\n\t\tgoto out;\n\t\tbreak;\n\t}\n\n\tret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (!active) {\n\t\tdata &= ~IGP01E1000_GMII_FLEX_SPD;\n\t\tret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\t/*\n\t\t * LPLU and SmartSpeed are mutually exclusive. LPLU is used\n\t\t * during Dx states where the power conservation is most\n\t\t * important. During driver activity we should enable\n\t\t * SmartSpeed, so performance is maintained.\n\t\t */\n\t\tif (phy->smart_speed == e1000_smart_speed_on) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tdata |= IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t} else if (phy->smart_speed == e1000_smart_speed_off) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t}\n\t} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||\n\t\t (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||\n\t\t (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {\n\t\tdata |= IGP01E1000_GMII_FLEX_SPD;\n\t\tret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n\t\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t &data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\tret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t data);\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_led_82541 - Configures SW controllable LED\n * @hw: pointer to the HW structure\n *\n * This prepares the SW controllable LED for use and saves the current state\n * of the LED so it can be later restored.\n **/\nSTATIC s32 e1000_setup_led_82541(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_setup_led_82541\");\n\n\tret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO,\n\t\t\t\t &dev_spec->spd_default);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,\n\t\t\t\t\t(u16)(dev_spec->spd_default &\n\t\t\t\t\t~IGP01E1000_GMII_SPD));\n\tif (ret_val)\n\t\tgoto out;\n\n\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_cleanup_led_82541 - Set LED config to default operation\n * @hw: pointer to the HW structure\n *\n * Remove the current LED configuration and set the LED configuration\n * to the default value, saved from the EEPROM.\n **/\nSTATIC s32 e1000_cleanup_led_82541(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_cleanup_led_82541\");\n\n\tret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO,\n\t\t\t\t\tdev_spec->spd_default);\n\tif (ret_val)\n\t\tgoto out;\n\n\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_init_script_82541 - Initialize GbE PHY\n * @hw: pointer to the HW structure\n *\n * Initializes the IGP PHY.\n **/\nSTATIC s32 e1000_phy_init_script_82541(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;\n\tu32 ret_val;\n\tu16 phy_saved_data;\n\n\tDEBUGFUNC(\"e1000_phy_init_script_82541\");\n\n\tif (!dev_spec->phy_init_script) {\n\t\tret_val = E1000_SUCCESS;\n\t\tgoto out;\n\t}\n\n\t/* Delay after phy reset to enable NVM configuration to load */\n\tmsec_delay(20);\n\n\t/*\n\t * Save off the current value of register 0x2F5B to be restored at\n\t * the end of this routine.\n\t */\n\tret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);\n\n\t/* Disabled the PHY transmitter */\n\thw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);\n\n\tmsec_delay(20);\n\n\thw->phy.ops.write_reg(hw, 0x0000, 0x0140);\n\n\tmsec_delay(5);\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82541:\n\tcase e1000_82547:\n\t\thw->phy.ops.write_reg(hw, 0x1F95, 0x0001);\n\n\t\thw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);\n\n\t\thw->phy.ops.write_reg(hw, 0x1F79, 0x0018);\n\n\t\thw->phy.ops.write_reg(hw, 0x1F30, 0x1600);\n\n\t\thw->phy.ops.write_reg(hw, 0x1F31, 0x0014);\n\n\t\thw->phy.ops.write_reg(hw, 0x1F32, 0x161C);\n\n\t\thw->phy.ops.write_reg(hw, 0x1F94, 0x0003);\n\n\t\thw->phy.ops.write_reg(hw, 0x1F96, 0x003F);\n\n\t\thw->phy.ops.write_reg(hw, 0x2010, 0x0008);\n\t\tbreak;\n\tcase e1000_82541_rev_2:\n\tcase e1000_82547_rev_2:\n\t\thw->phy.ops.write_reg(hw, 0x1F73, 0x0099);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\thw->phy.ops.write_reg(hw, 0x0000, 0x3300);\n\n\tmsec_delay(20);\n\n\t/* Now enable the transmitter */\n\thw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);\n\n\tif (hw->mac.type == e1000_82547) {\n\t\tu16 fused, fine, coarse;\n\n\t\t/* Move to analog registers page */\n\t\thw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS,\n\t\t\t\t &fused);\n\n\t\tif (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {\n\t\t\thw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS,\n\t\t\t\t\t &fused);\n\n\t\t\tfine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;\n\t\t\tcoarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;\n\n\t\t\tif (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {\n\t\t\t\tcoarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;\n\t\t\t\tfine -= IGP01E1000_ANALOG_FUSE_FINE_1;\n\t\t\t} else if (coarse ==\n\t\t\t\t IGP01E1000_ANALOG_FUSE_COARSE_THRESH)\n\t\t\t\tfine -= IGP01E1000_ANALOG_FUSE_FINE_10;\n\n\t\t\tfused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |\n\t\t\t\t(fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |\n\t\t\t\t(coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);\n\n\t\t\thw->phy.ops.write_reg(hw,\n\t\t\t\t\t IGP01E1000_ANALOG_FUSE_CONTROL,\n\t\t\t\t\t fused);\n\t\t\thw->phy.ops.write_reg(hw,\n\t\t\t\t IGP01E1000_ANALOG_FUSE_BYPASS,\n\t\t\t\t IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);\n\t\t}\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_script_state_82541 - Enable/Disable PHY init script\n * @hw: pointer to the HW structure\n * @state: boolean value used to enable/disable PHY init script\n *\n * Allows the driver to enable/disable the PHY init script, if the PHY is an\n * IGP PHY.\n **/\nvoid e1000_init_script_state_82541(struct e1000_hw *hw, bool state)\n{\n\tstruct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;\n\n\tDEBUGFUNC(\"e1000_init_script_state_82541\");\n\n\tif (hw->phy.type != e1000_phy_igp) {\n\t\tDEBUGOUT(\"Initialization script not necessary.\\n\");\n\t\tgoto out;\n\t}\n\n\tdev_spec->phy_init_script = state;\n\nout:\n\treturn;\n}\n\n/**\n * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down\n * @hw: pointer to the HW structure\n *\n * In the case of a PHY power down to save power, or to turn off link during a\n * driver unload, or wake on lan is not enabled, remove the link.\n **/\nSTATIC void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)\n{\n\t/* If the management interface is not enabled, then power down */\n\tif (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))\n\t\te1000_power_down_phy_copper(hw);\n\n\treturn;\n}\n\n/**\n * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters\n * @hw: pointer to the HW structure\n *\n * Clears the hardware counters by reading the counter registers.\n **/\nSTATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_clear_hw_cntrs_82541\");\n\n\te1000_clear_hw_cntrs_base_generic(hw);\n\n\tE1000_READ_REG(hw, E1000_PRC64);\n\tE1000_READ_REG(hw, E1000_PRC127);\n\tE1000_READ_REG(hw, E1000_PRC255);\n\tE1000_READ_REG(hw, E1000_PRC511);\n\tE1000_READ_REG(hw, E1000_PRC1023);\n\tE1000_READ_REG(hw, E1000_PRC1522);\n\tE1000_READ_REG(hw, E1000_PTC64);\n\tE1000_READ_REG(hw, E1000_PTC127);\n\tE1000_READ_REG(hw, E1000_PTC255);\n\tE1000_READ_REG(hw, E1000_PTC511);\n\tE1000_READ_REG(hw, E1000_PTC1023);\n\tE1000_READ_REG(hw, E1000_PTC1522);\n\n\tE1000_READ_REG(hw, E1000_ALGNERRC);\n\tE1000_READ_REG(hw, E1000_RXERRC);\n\tE1000_READ_REG(hw, E1000_TNCRS);\n\tE1000_READ_REG(hw, E1000_CEXTERR);\n\tE1000_READ_REG(hw, E1000_TSCTC);\n\tE1000_READ_REG(hw, E1000_TSCTFC);\n\n\tE1000_READ_REG(hw, E1000_MGTPRC);\n\tE1000_READ_REG(hw, E1000_MGTPDC);\n\tE1000_READ_REG(hw, E1000_MGTPTC);\n}\n" }, { "path": "drivers/net/e1000/base/e1000_82541.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_82541_H_\n#define _E1000_82541_H_\n\n#define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1)\n\n#define IGP01E1000_PHY_CHANNEL_NUM\t\t4\n\n#define IGP01E1000_PHY_AGC_A\t\t\t0x1172\n#define IGP01E1000_PHY_AGC_B\t\t\t0x1272\n#define IGP01E1000_PHY_AGC_C\t\t\t0x1472\n#define IGP01E1000_PHY_AGC_D\t\t\t0x1872\n\n#define IGP01E1000_PHY_AGC_PARAM_A\t\t0x1171\n#define IGP01E1000_PHY_AGC_PARAM_B\t\t0x1271\n#define IGP01E1000_PHY_AGC_PARAM_C\t\t0x1471\n#define IGP01E1000_PHY_AGC_PARAM_D\t\t0x1871\n\n#define IGP01E1000_PHY_EDAC_MU_INDEX\t\t0xC000\n#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS\t0x8000\n\n#define IGP01E1000_PHY_DSP_RESET\t\t0x1F33\n\n#define IGP01E1000_PHY_DSP_FFE\t\t\t0x1F35\n#define IGP01E1000_PHY_DSP_FFE_CM_CP\t\t0x0069\n#define IGP01E1000_PHY_DSP_FFE_DEFAULT\t\t0x002A\n\n#define IGP01E1000_IEEE_FORCE_GIG\t\t0x0140\n#define IGP01E1000_IEEE_RESTART_AUTONEG\t\t0x3300\n\n#define IGP01E1000_AGC_LENGTH_SHIFT\t\t7\n#define IGP01E1000_AGC_RANGE\t\t\t10\n\n#define FFE_IDLE_ERR_COUNT_TIMEOUT_20\t\t20\n#define FFE_IDLE_ERR_COUNT_TIMEOUT_100\t\t100\n\n#define IGP01E1000_ANALOG_FUSE_STATUS\t\t0x20D0\n#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS\t0x20D1\n#define IGP01E1000_ANALOG_FUSE_CONTROL\t\t0x20DC\n#define IGP01E1000_ANALOG_FUSE_BYPASS\t\t0x20DE\n\n#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED\t0x0100\n#define IGP01E1000_ANALOG_FUSE_FINE_MASK\t0x0F80\n#define IGP01E1000_ANALOG_FUSE_COARSE_MASK\t0x0070\n#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH\t0x0040\n#define IGP01E1000_ANALOG_FUSE_COARSE_10\t0x0010\n#define IGP01E1000_ANALOG_FUSE_FINE_1\t\t0x0080\n#define IGP01E1000_ANALOG_FUSE_FINE_10\t\t0x0500\n#define IGP01E1000_ANALOG_FUSE_POLY_MASK\t0xF000\n#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002\n\n#define IGP01E1000_MSE_CHANNEL_D\t\t0x000F\n#define IGP01E1000_MSE_CHANNEL_C\t\t0x00F0\n#define IGP01E1000_MSE_CHANNEL_B\t\t0x0F00\n#define IGP01E1000_MSE_CHANNEL_A\t\t0xF000\n\n\nvoid e1000_init_script_state_82541(struct e1000_hw *hw, bool state);\n#endif\n" }, { "path": "drivers/net/e1000/base/e1000_82542.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n/*\n * 82542 Gigabit Ethernet Controller\n */\n\n#include \"e1000_api.h\"\n\nSTATIC s32 e1000_init_phy_params_82542(struct e1000_hw *hw);\nSTATIC s32 e1000_init_nvm_params_82542(struct e1000_hw *hw);\nSTATIC s32 e1000_init_mac_params_82542(struct e1000_hw *hw);\nSTATIC s32 e1000_get_bus_info_82542(struct e1000_hw *hw);\nSTATIC s32 e1000_reset_hw_82542(struct e1000_hw *hw);\nSTATIC s32 e1000_init_hw_82542(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_link_82542(struct e1000_hw *hw);\nSTATIC s32 e1000_led_on_82542(struct e1000_hw *hw);\nSTATIC s32 e1000_led_off_82542(struct e1000_hw *hw);\nSTATIC void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);\nSTATIC void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);\nSTATIC s32 e1000_read_mac_addr_82542(struct e1000_hw *hw);\n\n/**\n * e1000_init_phy_params_82542 - Init PHY func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_phy_params_82542(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_init_phy_params_82542\");\n\n\tphy->type = e1000_phy_none;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_nvm_params_82542 - Init NVM func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\n\tDEBUGFUNC(\"e1000_init_nvm_params_82542\");\n\n\tnvm->address_bits\t= 6;\n\tnvm->delay_usec\t\t= 50;\n\tnvm->opcode_bits\t= 3;\n\tnvm->type\t\t= e1000_nvm_eeprom_microwire;\n\tnvm->word_size\t\t= 64;\n\n\t/* Function Pointers */\n\tnvm->ops.read\t\t= e1000_read_nvm_microwire;\n\tnvm->ops.release\t= e1000_stop_nvm;\n\tnvm->ops.write\t\t= e1000_write_nvm_microwire;\n\tnvm->ops.update\t\t= e1000_update_nvm_checksum_generic;\n\tnvm->ops.validate\t= e1000_validate_nvm_checksum_generic;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_mac_params_82542 - Init MAC func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_mac_params_82542(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"e1000_init_mac_params_82542\");\n\n\t/* Set media type */\n\thw->phy.media_type = e1000_media_type_fiber;\n\n\t/* Set mta register count */\n\tmac->mta_reg_count = 128;\n\t/* Set rar entry count */\n\tmac->rar_entry_count = E1000_RAR_ENTRIES;\n\n\t/* Function pointers */\n\n\t/* bus type/speed/width */\n\tmac->ops.get_bus_info = e1000_get_bus_info_82542;\n\t/* function id */\n\tmac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;\n\t/* reset */\n\tmac->ops.reset_hw = e1000_reset_hw_82542;\n\t/* hw initialization */\n\tmac->ops.init_hw = e1000_init_hw_82542;\n\t/* link setup */\n\tmac->ops.setup_link = e1000_setup_link_82542;\n\t/* phy/fiber/serdes setup */\n\tmac->ops.setup_physical_interface =\n\t\t\t\t\te1000_setup_fiber_serdes_link_generic;\n\t/* check for link */\n\tmac->ops.check_for_link = e1000_check_for_fiber_link_generic;\n\t/* multicast address update */\n\tmac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;\n\t/* writing VFTA */\n\tmac->ops.write_vfta = e1000_write_vfta_generic;\n\t/* clearing VFTA */\n\tmac->ops.clear_vfta = e1000_clear_vfta_generic;\n\t/* read mac address */\n\tmac->ops.read_mac_addr = e1000_read_mac_addr_82542;\n\t/* set RAR */\n\tmac->ops.rar_set = e1000_rar_set_82542;\n\t/* turn on/off LED */\n\tmac->ops.led_on = e1000_led_on_82542;\n\tmac->ops.led_off = e1000_led_off_82542;\n\t/* clear hardware counters */\n\tmac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;\n\t/* link info */\n\tmac->ops.get_link_up_info =\n\t\t\t\te1000_get_speed_and_duplex_fiber_serdes_generic;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_function_pointers_82542 - Init func ptrs.\n * @hw: pointer to the HW structure\n *\n * Called to initialize all function pointers and parameters.\n **/\nvoid e1000_init_function_pointers_82542(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_function_pointers_82542\");\n\n\thw->mac.ops.init_params = e1000_init_mac_params_82542;\n\thw->nvm.ops.init_params = e1000_init_nvm_params_82542;\n\thw->phy.ops.init_params = e1000_init_phy_params_82542;\n}\n\n/**\n * e1000_get_bus_info_82542 - Obtain bus information for adapter\n * @hw: pointer to the HW structure\n *\n * This will obtain information about the HW bus for which the\n * adapter is attached and stores it in the hw structure.\n **/\nSTATIC s32 e1000_get_bus_info_82542(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_get_bus_info_82542\");\n\n\thw->bus.type = e1000_bus_type_pci;\n\thw->bus.speed = e1000_bus_speed_unknown;\n\thw->bus.width = e1000_bus_width_unknown;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_reset_hw_82542 - Reset hardware\n * @hw: pointer to the HW structure\n *\n * This resets the hardware into a known state.\n **/\nSTATIC s32 e1000_reset_hw_82542(struct e1000_hw *hw)\n{\n\tstruct e1000_bus_info *bus = &hw->bus;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 ctrl;\n\n\tDEBUGFUNC(\"e1000_reset_hw_82542\");\n\n\tif (hw->revision_id == E1000_REVISION_2) {\n\t\tDEBUGOUT(\"Disabling MWI on 82542 rev 2\\n\");\n\t\te1000_pci_clear_mwi(hw);\n\t}\n\n\tDEBUGOUT(\"Masking off all interrupts\\n\");\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\n\tE1000_WRITE_REG(hw, E1000_RCTL, 0);\n\tE1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/*\n\t * Delay to allow any outstanding PCI transactions to complete before\n\t * resetting the device\n\t */\n\tmsec_delay(10);\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\tDEBUGOUT(\"Issuing a global reset to 82542/82543 MAC\\n\");\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);\n\n\thw->nvm.ops.reload(hw);\n\tmsec_delay(2);\n\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\tE1000_READ_REG(hw, E1000_ICR);\n\n\tif (hw->revision_id == E1000_REVISION_2) {\n\t\tif (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)\n\t\t\te1000_pci_set_mwi(hw);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_hw_82542 - Initialize hardware\n * @hw: pointer to the HW structure\n *\n * This inits the hardware readying it for operation.\n **/\nSTATIC s32 e1000_init_hw_82542(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tstruct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 ctrl;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_init_hw_82542\");\n\n\t/* Disabling VLAN filtering */\n\tE1000_WRITE_REG(hw, E1000_VET, 0);\n\tmac->ops.clear_vfta(hw);\n\n\t/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */\n\tif (hw->revision_id == E1000_REVISION_2) {\n\t\tDEBUGOUT(\"Disabling MWI on 82542 rev 2.0\\n\");\n\t\te1000_pci_clear_mwi(hw);\n\t\tE1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tmsec_delay(5);\n\t}\n\n\t/* Setup the receive address. */\n\te1000_init_rx_addrs_generic(hw, mac->rar_entry_count);\n\n\t/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */\n\tif (hw->revision_id == E1000_REVISION_2) {\n\t\tE1000_WRITE_REG(hw, E1000_RCTL, 0);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tmsec_delay(1);\n\t\tif (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)\n\t\t\te1000_pci_set_mwi(hw);\n\t}\n\n\t/* Zero out the Multicast HASH table */\n\tDEBUGOUT(\"Zeroing the MTA\\n\");\n\tfor (i = 0; i < mac->mta_reg_count; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);\n\n\t/*\n\t * Set the PCI priority bit correctly in the CTRL register. This\n\t * determines if the adapter gives priority to receives, or if it\n\t * gives equal priority to transmits and receives.\n\t */\n\tif (dev_spec->dma_fairness) {\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);\n\t}\n\n\t/* Setup link and flow control */\n\tret_val = e1000_setup_link_82542(hw);\n\n\t/*\n\t * Clear all of the statistics registers (clear on read). It is\n\t * important that we do this after we have tried to establish link\n\t * because the symbol error count will increment wildly if there\n\t * is no link.\n\t */\n\te1000_clear_hw_cntrs_82542(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_link_82542 - Setup flow control and link settings\n * @hw: pointer to the HW structure\n *\n * Determines which flow control settings to use, then configures flow\n * control. Calls the appropriate media-specific link configuration\n * function. Assuming the adapter has a valid link partner, a valid link\n * should be established. Assumes the hardware has previously been reset\n * and the transmitter and receiver are not enabled.\n **/\nSTATIC s32 e1000_setup_link_82542(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_setup_link_82542\");\n\n\tret_val = e1000_set_default_fc_generic(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\thw->fc.requested_mode &= ~e1000_fc_tx_pause;\n\n\tif (mac->report_tx_early)\n\t\thw->fc.requested_mode &= ~e1000_fc_rx_pause;\n\n\t/*\n\t * Save off the requested flow control mode for use later. Depending\n\t * on the link partner's capabilities, we may or may not use this mode.\n\t */\n\thw->fc.current_mode = hw->fc.requested_mode;\n\n\tDEBUGOUT1(\"After fix-ups FlowControl is now = %x\\n\",\n\t\t hw->fc.current_mode);\n\n\t/* Call the necessary subroutine to configure the link. */\n\tret_val = mac->ops.setup_physical_interface(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/*\n\t * Initialize the flow control address, type, and PAUSE timer\n\t * registers to their default values. This is done even if flow\n\t * control is disabled, because it does not hurt anything to\n\t * initialize these registers.\n\t */\n\tDEBUGOUT(\"Initializing Flow Control address, type and timer regs\\n\");\n\n\tE1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);\n\tE1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);\n\tE1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);\n\n\tE1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);\n\n\tret_val = e1000_set_fc_watermarks_generic(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_led_on_82542 - Turn on SW controllable LED\n * @hw: pointer to the HW structure\n *\n * Turns the SW defined LED on.\n **/\nSTATIC s32 e1000_led_on_82542(struct e1000_hw *hw)\n{\n\tu32 ctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\tDEBUGFUNC(\"e1000_led_on_82542\");\n\n\tctrl |= E1000_CTRL_SWDPIN0;\n\tctrl |= E1000_CTRL_SWDPIO0;\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_led_off_82542 - Turn off SW controllable LED\n * @hw: pointer to the HW structure\n *\n * Turns the SW defined LED off.\n **/\nSTATIC s32 e1000_led_off_82542(struct e1000_hw *hw)\n{\n\tu32 ctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\tDEBUGFUNC(\"e1000_led_off_82542\");\n\n\tctrl &= ~E1000_CTRL_SWDPIN0;\n\tctrl |= E1000_CTRL_SWDPIO0;\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_rar_set_82542 - Set receive address register\n * @hw: pointer to the HW structure\n * @addr: pointer to the receive address\n * @index: receive address array register\n *\n * Sets the receive address array register at index to the address passed\n * in by addr.\n **/\nSTATIC void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)\n{\n\tu32 rar_low, rar_high;\n\n\tDEBUGFUNC(\"e1000_rar_set_82542\");\n\n\t/*\n\t * HW expects these in little endian so we reverse the byte order\n\t * from network order (big endian) to little endian\n\t */\n\trar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |\n\t\t ((u32) addr[2] << 16) | ((u32) addr[3] << 24));\n\n\trar_high = ((u32) addr[4] | ((u32) addr[5] << 8));\n\n\t/* If MAC address zero, no need to set the AV bit */\n\tif (rar_low || rar_high)\n\t\trar_high |= E1000_RAH_AV;\n\n\tE1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);\n\tE1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);\n}\n\n/**\n * e1000_translate_register_82542 - Translate the proper register offset\n * @reg: e1000 register to be read\n *\n * Registers in 82542 are located in different offsets than other adapters\n * even though they function in the same manner. This function takes in\n * the name of the register to read and returns the correct offset for\n * 82542 silicon.\n **/\nu32 e1000_translate_register_82542(u32 reg)\n{\n\t/*\n\t * Some of the 82542 registers are located at different\n\t * offsets than they are in newer adapters.\n\t * Despite the difference in location, the registers\n\t * function in the same manner.\n\t */\n\tswitch (reg) {\n\tcase E1000_RA:\n\t\treg = 0x00040;\n\t\tbreak;\n\tcase E1000_RDTR:\n\t\treg = 0x00108;\n\t\tbreak;\n\tcase E1000_RDBAL(0):\n\t\treg = 0x00110;\n\t\tbreak;\n\tcase E1000_RDBAH(0):\n\t\treg = 0x00114;\n\t\tbreak;\n\tcase E1000_RDLEN(0):\n\t\treg = 0x00118;\n\t\tbreak;\n\tcase E1000_RDH(0):\n\t\treg = 0x00120;\n\t\tbreak;\n\tcase E1000_RDT(0):\n\t\treg = 0x00128;\n\t\tbreak;\n\tcase E1000_RDBAL(1):\n\t\treg = 0x00138;\n\t\tbreak;\n\tcase E1000_RDBAH(1):\n\t\treg = 0x0013C;\n\t\tbreak;\n\tcase E1000_RDLEN(1):\n\t\treg = 0x00140;\n\t\tbreak;\n\tcase E1000_RDH(1):\n\t\treg = 0x00148;\n\t\tbreak;\n\tcase E1000_RDT(1):\n\t\treg = 0x00150;\n\t\tbreak;\n\tcase E1000_FCRTH:\n\t\treg = 0x00160;\n\t\tbreak;\n\tcase E1000_FCRTL:\n\t\treg = 0x00168;\n\t\tbreak;\n\tcase E1000_MTA:\n\t\treg = 0x00200;\n\t\tbreak;\n\tcase E1000_TDBAL(0):\n\t\treg = 0x00420;\n\t\tbreak;\n\tcase E1000_TDBAH(0):\n\t\treg = 0x00424;\n\t\tbreak;\n\tcase E1000_TDLEN(0):\n\t\treg = 0x00428;\n\t\tbreak;\n\tcase E1000_TDH(0):\n\t\treg = 0x00430;\n\t\tbreak;\n\tcase E1000_TDT(0):\n\t\treg = 0x00438;\n\t\tbreak;\n\tcase E1000_TIDV:\n\t\treg = 0x00440;\n\t\tbreak;\n\tcase E1000_VFTA:\n\t\treg = 0x00600;\n\t\tbreak;\n\tcase E1000_TDFH:\n\t\treg = 0x08010;\n\t\tbreak;\n\tcase E1000_TDFT:\n\t\treg = 0x08018;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn reg;\n}\n\n/**\n * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters\n * @hw: pointer to the HW structure\n *\n * Clears the hardware counters by reading the counter registers.\n **/\nSTATIC void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_clear_hw_cntrs_82542\");\n\n\te1000_clear_hw_cntrs_base_generic(hw);\n\n\tE1000_READ_REG(hw, E1000_PRC64);\n\tE1000_READ_REG(hw, E1000_PRC127);\n\tE1000_READ_REG(hw, E1000_PRC255);\n\tE1000_READ_REG(hw, E1000_PRC511);\n\tE1000_READ_REG(hw, E1000_PRC1023);\n\tE1000_READ_REG(hw, E1000_PRC1522);\n\tE1000_READ_REG(hw, E1000_PTC64);\n\tE1000_READ_REG(hw, E1000_PTC127);\n\tE1000_READ_REG(hw, E1000_PTC255);\n\tE1000_READ_REG(hw, E1000_PTC511);\n\tE1000_READ_REG(hw, E1000_PTC1023);\n\tE1000_READ_REG(hw, E1000_PTC1522);\n}\n\n/**\n * e1000_read_mac_addr_82542 - Read device MAC address\n * @hw: pointer to the HW structure\n *\n * Reads the device MAC address from the EEPROM and stores the value.\n **/\ns32 e1000_read_mac_addr_82542(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 offset, nvm_data, i;\n\n\tDEBUGFUNC(\"e1000_read_mac_addr\");\n\n\tfor (i = 0; i < ETH_ADDR_LEN; i += 2) {\n\t\toffset = i >> 1;\n\t\tret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\tgoto out;\n\t\t}\n\t\thw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);\n\t\thw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);\n\t}\n\n\tfor (i = 0; i < ETH_ADDR_LEN; i++)\n\t\thw->mac.addr[i] = hw->mac.perm_addr[i];\n\nout:\n\treturn ret_val;\n}\n" }, { "path": "drivers/net/e1000/base/e1000_82543.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n/*\n * 82543GC Gigabit Ethernet Controller (Fiber)\n * 82543GC Gigabit Ethernet Controller (Copper)\n * 82544EI Gigabit Ethernet Controller (Copper)\n * 82544EI Gigabit Ethernet Controller (Fiber)\n * 82544GC Gigabit Ethernet Controller (Copper)\n * 82544GC Gigabit Ethernet Controller (LOM)\n */\n\n#include \"e1000_api.h\"\n\nSTATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,\n\t\t\t\t u16 *data);\nSTATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,\n\t\t\t\t u16 data);\nSTATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_init_hw_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_link_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_led_on_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_led_off_82543(struct e1000_hw *hw);\nSTATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,\n\t\t\t\t u32 value);\nSTATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);\nSTATIC s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);\nSTATIC bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);\nSTATIC void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);\nSTATIC s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);\nSTATIC void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);\nSTATIC u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);\nSTATIC void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,\n\t\t\t\t\t u16 count);\nSTATIC bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);\nSTATIC void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);\n\n/**\n * e1000_init_phy_params_82543 - Init PHY func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_phy_params_82543(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_init_phy_params_82543\");\n\n\tif (hw->phy.media_type != e1000_media_type_copper) {\n\t\tphy->type = e1000_phy_none;\n\t\tgoto out;\n\t} else {\n\t\tphy->ops.power_up = e1000_power_up_phy_copper;\n\t\tphy->ops.power_down = e1000_power_down_phy_copper;\n\t}\n\n\tphy->addr\t\t= 1;\n\tphy->autoneg_mask\t= AUTONEG_ADVERTISE_SPEED_DEFAULT;\n\tphy->reset_delay_us\t= 10000;\n\tphy->type\t\t= e1000_phy_m88;\n\n\t/* Function Pointers */\n\tphy->ops.check_polarity\t= e1000_check_polarity_m88;\n\tphy->ops.commit\t\t= e1000_phy_sw_reset_generic;\n\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;\n\tphy->ops.get_cable_length = e1000_get_cable_length_m88;\n\tphy->ops.get_cfg_done\t= e1000_get_cfg_done_generic;\n\tphy->ops.read_reg\t= (hw->mac.type == e1000_82543)\n\t\t\t\t ? e1000_read_phy_reg_82543\n\t\t\t\t : e1000_read_phy_reg_m88;\n\tphy->ops.reset\t\t= (hw->mac.type == e1000_82543)\n\t\t\t\t ? e1000_phy_hw_reset_82543\n\t\t\t\t : e1000_phy_hw_reset_generic;\n\tphy->ops.write_reg\t= (hw->mac.type == e1000_82543)\n\t\t\t\t ? e1000_write_phy_reg_82543\n\t\t\t\t : e1000_write_phy_reg_m88;\n\tphy->ops.get_info\t= e1000_get_phy_info_m88;\n\n\t/*\n\t * The external PHY of the 82543 can be in a funky state.\n\t * Resetting helps us read the PHY registers for acquiring\n\t * the PHY ID.\n\t */\n\tif (!e1000_init_phy_disabled_82543(hw)) {\n\t\tret_val = phy->ops.reset(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Resetting PHY during init failed.\\n\");\n\t\t\tgoto out;\n\t\t}\n\t\tmsec_delay(20);\n\t}\n\n\tret_val = e1000_get_phy_id(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/* Verify phy id */\n\tswitch (hw->mac.type) {\n\tcase e1000_82543:\n\t\tif (phy->id != M88E1000_E_PHY_ID) {\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\t\tgoto out;\n\t\t}\n\t\tbreak;\n\tcase e1000_82544:\n\t\tif (phy->id != M88E1000_I_PHY_ID) {\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\t\tgoto out;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tret_val = -E1000_ERR_PHY;\n\t\tgoto out;\n\t\tbreak;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_nvm_params_82543 - Init NVM func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\n\tDEBUGFUNC(\"e1000_init_nvm_params_82543\");\n\n\tnvm->type\t\t= e1000_nvm_eeprom_microwire;\n\tnvm->word_size\t\t= 64;\n\tnvm->delay_usec\t\t= 50;\n\tnvm->address_bits\t= 6;\n\tnvm->opcode_bits\t= 3;\n\n\t/* Function Pointers */\n\tnvm->ops.read\t\t= e1000_read_nvm_microwire;\n\tnvm->ops.update\t\t= e1000_update_nvm_checksum_generic;\n\tnvm->ops.valid_led_default = e1000_valid_led_default_generic;\n\tnvm->ops.validate\t= e1000_validate_nvm_checksum_generic;\n\tnvm->ops.write\t\t= e1000_write_nvm_microwire;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_mac_params_82543 - Init MAC func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_mac_params_82543(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"e1000_init_mac_params_82543\");\n\n\t/* Set media type */\n\tswitch (hw->device_id) {\n\tcase E1000_DEV_ID_82543GC_FIBER:\n\tcase E1000_DEV_ID_82544EI_FIBER:\n\t\thw->phy.media_type = e1000_media_type_fiber;\n\t\tbreak;\n\tdefault:\n\t\thw->phy.media_type = e1000_media_type_copper;\n\t\tbreak;\n\t}\n\n\t/* Set mta register count */\n\tmac->mta_reg_count = 128;\n\t/* Set rar entry count */\n\tmac->rar_entry_count = E1000_RAR_ENTRIES;\n\n\t/* Function pointers */\n\n\t/* bus type/speed/width */\n\tmac->ops.get_bus_info = e1000_get_bus_info_pci_generic;\n\t/* function id */\n\tmac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;\n\t/* reset */\n\tmac->ops.reset_hw = e1000_reset_hw_82543;\n\t/* hw initialization */\n\tmac->ops.init_hw = e1000_init_hw_82543;\n\t/* link setup */\n\tmac->ops.setup_link = e1000_setup_link_82543;\n\t/* physical interface setup */\n\tmac->ops.setup_physical_interface =\n\t\t(hw->phy.media_type == e1000_media_type_copper)\n\t\t ? e1000_setup_copper_link_82543 : e1000_setup_fiber_link_82543;\n\t/* check for link */\n\tmac->ops.check_for_link =\n\t\t(hw->phy.media_type == e1000_media_type_copper)\n\t\t ? e1000_check_for_copper_link_82543\n\t\t : e1000_check_for_fiber_link_82543;\n\t/* link info */\n\tmac->ops.get_link_up_info =\n\t\t(hw->phy.media_type == e1000_media_type_copper)\n\t\t ? e1000_get_speed_and_duplex_copper_generic\n\t\t : e1000_get_speed_and_duplex_fiber_serdes_generic;\n\t/* multicast address update */\n\tmac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;\n\t/* writing VFTA */\n\tmac->ops.write_vfta = e1000_write_vfta_82543;\n\t/* clearing VFTA */\n\tmac->ops.clear_vfta = e1000_clear_vfta_generic;\n\t/* turn on/off LED */\n\tmac->ops.led_on = e1000_led_on_82543;\n\tmac->ops.led_off = e1000_led_off_82543;\n\t/* clear hardware counters */\n\tmac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543;\n\n\t/* Set tbi compatibility */\n\tif ((hw->mac.type != e1000_82543) ||\n\t (hw->phy.media_type == e1000_media_type_fiber))\n\t\te1000_set_tbi_compatibility_82543(hw, false);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_function_pointers_82543 - Init func ptrs.\n * @hw: pointer to the HW structure\n *\n * Called to initialize all function pointers and parameters.\n **/\nvoid e1000_init_function_pointers_82543(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_function_pointers_82543\");\n\n\thw->mac.ops.init_params = e1000_init_mac_params_82543;\n\thw->nvm.ops.init_params = e1000_init_nvm_params_82543;\n\thw->phy.ops.init_params = e1000_init_phy_params_82543;\n}\n\n/**\n * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status\n * @hw: pointer to the HW structure\n *\n * Returns the current status of 10-bit Interface (TBI) compatibility\n * (enabled/disabled).\n **/\nSTATIC bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;\n\tbool state = false;\n\n\tDEBUGFUNC(\"e1000_tbi_compatibility_enabled_82543\");\n\n\tif (hw->mac.type != e1000_82543) {\n\t\tDEBUGOUT(\"TBI compatibility workaround for 82543 only.\\n\");\n\t\tgoto out;\n\t}\n\n\tstate = !!(dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED);\n\nout:\n\treturn state;\n}\n\n/**\n * e1000_set_tbi_compatibility_82543 - Set TBI compatibility\n * @hw: pointer to the HW structure\n * @state: enable/disable TBI compatibility\n *\n * Enables or disabled 10-bit Interface (TBI) compatibility.\n **/\nvoid e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)\n{\n\tstruct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;\n\n\tDEBUGFUNC(\"e1000_set_tbi_compatibility_82543\");\n\n\tif (hw->mac.type != e1000_82543) {\n\t\tDEBUGOUT(\"TBI compatibility workaround for 82543 only.\\n\");\n\t\tgoto out;\n\t}\n\n\tif (state)\n\t\tdev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED;\n\telse\n\t\tdev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED;\n\nout:\n\treturn;\n}\n\n/**\n * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status\n * @hw: pointer to the HW structure\n *\n * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)\n * (enabled/disabled).\n **/\nbool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;\n\tbool state = false;\n\n\tDEBUGFUNC(\"e1000_tbi_sbp_enabled_82543\");\n\n\tif (hw->mac.type != e1000_82543) {\n\t\tDEBUGOUT(\"TBI compatibility workaround for 82543 only.\\n\");\n\t\tgoto out;\n\t}\n\n\tstate = !!(dev_spec->tbi_compatibility & TBI_SBP_ENABLED);\n\nout:\n\treturn state;\n}\n\n/**\n * e1000_set_tbi_sbp_82543 - Set TBI SBP\n * @hw: pointer to the HW structure\n * @state: enable/disable TBI store bad packet\n *\n * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).\n **/\nSTATIC void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)\n{\n\tstruct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;\n\n\tDEBUGFUNC(\"e1000_set_tbi_sbp_82543\");\n\n\tif (state && e1000_tbi_compatibility_enabled_82543(hw))\n\t\tdev_spec->tbi_compatibility |= TBI_SBP_ENABLED;\n\telse\n\t\tdev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED;\n\n\treturn;\n}\n\n/**\n * e1000_init_phy_disabled_82543 - Returns init PHY status\n * @hw: pointer to the HW structure\n *\n * Returns the current status of whether PHY initialization is disabled.\n * True if PHY initialization is disabled else false.\n **/\nSTATIC bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;\n\tbool ret_val;\n\n\tDEBUGFUNC(\"e1000_init_phy_disabled_82543\");\n\n\tif (hw->mac.type != e1000_82543) {\n\t\tret_val = false;\n\t\tgoto out;\n\t}\n\n\tret_val = dev_spec->init_phy_disabled;\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled\n * @hw: pointer to the HW structure\n * @stats: Struct containing statistic register values\n * @frame_len: The length of the frame in question\n * @mac_addr: The Ethernet destination address of the frame in question\n * @max_frame_size: The maximum frame size\n *\n * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT\n **/\nvoid e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,\n\t\t\t\t struct e1000_hw_stats *stats, u32 frame_len,\n\t\t\t\t u8 *mac_addr, u32 max_frame_size)\n{\n\tif (!(e1000_tbi_sbp_enabled_82543(hw)))\n\t\tgoto out;\n\n\t/* First adjust the frame length. */\n\tframe_len--;\n\t/*\n\t * We need to adjust the statistics counters, since the hardware\n\t * counters overcount this packet as a CRC error and undercount\n\t * the packet as a good packet\n\t */\n\t/* This packet should not be counted as a CRC error. */\n\tstats->crcerrs--;\n\t/* This packet does count as a Good Packet Received. */\n\tstats->gprc++;\n\n\t/* Adjust the Good Octets received counters */\n\tstats->gorc += frame_len;\n\n\t/*\n\t * Is this a broadcast or multicast? Check broadcast first,\n\t * since the test for a multicast frame will test positive on\n\t * a broadcast frame.\n\t */\n\tif ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff))\n\t\t/* Broadcast packet */\n\t\tstats->bprc++;\n\telse if (*mac_addr & 0x01)\n\t\t/* Multicast packet */\n\t\tstats->mprc++;\n\n\t/*\n\t * In this case, the hardware has over counted the number of\n\t * oversize frames.\n\t */\n\tif ((frame_len == max_frame_size) && (stats->roc > 0))\n\t\tstats->roc--;\n\n\t/*\n\t * Adjust the bin counters when the extra byte put the frame in the\n\t * wrong bin. Remember that the frame_len was adjusted above.\n\t */\n\tif (frame_len == 64) {\n\t\tstats->prc64++;\n\t\tstats->prc127--;\n\t} else if (frame_len == 127) {\n\t\tstats->prc127++;\n\t\tstats->prc255--;\n\t} else if (frame_len == 255) {\n\t\tstats->prc255++;\n\t\tstats->prc511--;\n\t} else if (frame_len == 511) {\n\t\tstats->prc511++;\n\t\tstats->prc1023--;\n\t} else if (frame_len == 1023) {\n\t\tstats->prc1023++;\n\t\tstats->prc1522--;\n\t} else if (frame_len == 1522) {\n\t\tstats->prc1522++;\n\t}\n\nout:\n\treturn;\n}\n\n/**\n * e1000_read_phy_reg_82543 - Read PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the PHY at offset and stores the information read to data.\n **/\nSTATIC s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\tu32 mdic;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_82543\");\n\n\tif (offset > MAX_PHY_REG_ADDRESS) {\n\t\tDEBUGOUT1(\"PHY Address %d is out of range\\n\", offset);\n\t\tret_val = -E1000_ERR_PARAM;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * We must first send a preamble through the MDIO pin to signal the\n\t * beginning of an MII instruction. This is done by sending 32\n\t * consecutive \"1\" bits.\n\t */\n\te1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);\n\n\t/*\n\t * Now combine the next few fields that are required for a read\n\t * operation. We use this method instead of calling the\n\t * e1000_shift_out_mdi_bits routine five different times. The format\n\t * of an MII read instruction consists of a shift out of 14 bits and\n\t * is defined as follows:\n\t * \n\t * followed by a shift in of 18 bits. This first two bits shifted in\n\t * are TurnAround bits used to avoid contention on the MDIO pin when a\n\t * READ operation is performed. These two bits are thrown away\n\t * followed by a shift in of 16 bits which contains the desired data.\n\t */\n\tmdic = (offset | (hw->phy.addr << 5) |\n\t\t(PHY_OP_READ << 10) | (PHY_SOF << 12));\n\n\te1000_shift_out_mdi_bits_82543(hw, mdic, 14);\n\n\t/*\n\t * Now that we've shifted out the read command to the MII, we need to\n\t * \"shift in\" the 16-bit value (18 total bits) of the requested PHY\n\t * register address.\n\t */\n\t*data = e1000_shift_in_mdi_bits_82543(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_write_phy_reg_82543 - Write PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be written\n * @data: pointer to the data to be written at offset\n *\n * Writes data to the PHY at offset.\n **/\nSTATIC s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\tu32 mdic;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_82543\");\n\n\tif (offset > MAX_PHY_REG_ADDRESS) {\n\t\tDEBUGOUT1(\"PHY Address %d is out of range\\n\", offset);\n\t\tret_val = -E1000_ERR_PARAM;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * We'll need to use the SW defined pins to shift the write command\n\t * out to the PHY. We first send a preamble to the PHY to signal the\n\t * beginning of the MII instruction. This is done by sending 32\n\t * consecutive \"1\" bits.\n\t */\n\te1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);\n\n\t/*\n\t * Now combine the remaining required fields that will indicate a\n\t * write operation. We use this method instead of calling the\n\t * e1000_shift_out_mdi_bits routine for each field in the command. The\n\t * format of a MII write instruction is as follows:\n\t * .\n\t */\n\tmdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |\n\t\t(PHY_OP_WRITE << 12) | (PHY_SOF << 14));\n\tmdic <<= 16;\n\tmdic |= (u32)data;\n\n\te1000_shift_out_mdi_bits_82543(hw, mdic, 32);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock\n * @hw: pointer to the HW structure\n * @ctrl: pointer to the control register\n *\n * Raise the management data input clock by setting the MDC bit in the control\n * register.\n **/\nSTATIC void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)\n{\n\t/*\n\t * Raise the clock input to the Management Data Clock (by setting the\n\t * MDC bit), and then delay a sufficient amount of time.\n\t */\n\tE1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));\n\tE1000_WRITE_FLUSH(hw);\n\tusec_delay(10);\n}\n\n/**\n * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock\n * @hw: pointer to the HW structure\n * @ctrl: pointer to the control register\n *\n * Lower the management data input clock by clearing the MDC bit in the\n * control register.\n **/\nSTATIC void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)\n{\n\t/*\n\t * Lower the clock input to the Management Data Clock (by clearing the\n\t * MDC bit), and then delay a sufficient amount of time.\n\t */\n\tE1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));\n\tE1000_WRITE_FLUSH(hw);\n\tusec_delay(10);\n}\n\n/**\n * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY\n * @hw: pointer to the HW structure\n * @data: data to send to the PHY\n * @count: number of bits to shift out\n *\n * We need to shift 'count' bits out to the PHY. So, the value in the\n * \"data\" parameter will be shifted out to the PHY one bit at a time.\n * In order to do this, \"data\" must be broken down into bits.\n **/\nSTATIC void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,\n\t\t\t\t\t u16 count)\n{\n\tu32 ctrl, mask;\n\n\t/*\n\t * We need to shift \"count\" number of bits out to the PHY. So, the\n\t * value in the \"data\" parameter will be shifted out to the PHY one\n\t * bit at a time. In order to do this, \"data\" must be broken down\n\t * into bits.\n\t */\n\tmask = 0x01;\n\tmask <<= (count - 1);\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\t/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */\n\tctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);\n\n\twhile (mask) {\n\t\t/*\n\t\t * A \"1\" is shifted out to the PHY by setting the MDIO bit to\n\t\t * \"1\" and then raising and lowering the Management Data Clock.\n\t\t * A \"0\" is shifted out to the PHY by setting the MDIO bit to\n\t\t * \"0\" and then raising and lowering the clock.\n\t\t */\n\t\tif (data & mask)\n\t\t\tctrl |= E1000_CTRL_MDIO;\n\t\telse\n\t\t\tctrl &= ~E1000_CTRL_MDIO;\n\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\t\tE1000_WRITE_FLUSH(hw);\n\n\t\tusec_delay(10);\n\n\t\te1000_raise_mdi_clk_82543(hw, &ctrl);\n\t\te1000_lower_mdi_clk_82543(hw, &ctrl);\n\n\t\tmask >>= 1;\n\t}\n}\n\n/**\n * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY\n * @hw: pointer to the HW structure\n *\n * In order to read a register from the PHY, we need to shift 18 bits\n * in from the PHY. Bits are \"shifted in\" by raising the clock input to\n * the PHY (setting the MDC bit), and then reading the value of the data out\n * MDIO bit.\n **/\nSTATIC u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\tu16 data = 0;\n\tu8 i;\n\n\t/*\n\t * In order to read a register from the PHY, we need to shift in a\n\t * total of 18 bits from the PHY. The first two bit (turnaround)\n\t * times are used to avoid contention on the MDIO pin when a read\n\t * operation is performed. These two bits are ignored by us and\n\t * thrown away. Bits are \"shifted in\" by raising the input to the\n\t * Management Data Clock (setting the MDC bit) and then reading the\n\t * value of the MDIO bit.\n\t */\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\t/*\n\t * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as\n\t * input.\n\t */\n\tctrl &= ~E1000_CTRL_MDIO_DIR;\n\tctrl &= ~E1000_CTRL_MDIO;\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/*\n\t * Raise and lower the clock before reading in the data. This accounts\n\t * for the turnaround bits. The first clock occurred when we clocked\n\t * out the last bit of the Register Address.\n\t */\n\te1000_raise_mdi_clk_82543(hw, &ctrl);\n\te1000_lower_mdi_clk_82543(hw, &ctrl);\n\n\tfor (data = 0, i = 0; i < 16; i++) {\n\t\tdata <<= 1;\n\t\te1000_raise_mdi_clk_82543(hw, &ctrl);\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\t/* Check to see if we shifted in a \"1\". */\n\t\tif (ctrl & E1000_CTRL_MDIO)\n\t\t\tdata |= 1;\n\t\te1000_lower_mdi_clk_82543(hw, &ctrl);\n\t}\n\n\te1000_raise_mdi_clk_82543(hw, &ctrl);\n\te1000_lower_mdi_clk_82543(hw, &ctrl);\n\n\treturn data;\n}\n\n/**\n * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY\n * @hw: pointer to the HW structure\n *\n * Calls the function to force speed and duplex for the m88 PHY, and\n * if the PHY is not auto-negotiating and the speed is forced to 10Mbit,\n * then call the function for polarity reversal workaround.\n **/\nSTATIC s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_phy_force_speed_duplex_82543\");\n\n\tret_val = e1000_phy_force_speed_duplex_m88(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (!hw->mac.autoneg && (hw->mac.forced_speed_duplex &\n\t E1000_ALL_10_SPEED))\n\t\tret_val = e1000_polarity_reversal_workaround_82543(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal\n * @hw: pointer to the HW structure\n *\n * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity\n * inadvertently. To workaround the issue, we disable the transmitter on\n * the PHY until we have established the link partner's link parameters.\n **/\nSTATIC s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 mii_status_reg;\n\tu16 i;\n\tbool link;\n\n\tif (!(hw->phy.ops.write_reg))\n\t\tgoto out;\n\n\t/* Polarity reversal workaround for forced 10F/10H links. */\n\n\t/* Disable the transmitter on the PHY */\n\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);\n\tif (ret_val)\n\t\tgoto out;\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/*\n\t * This loop will early-out if the NO link condition has been met.\n\t * In other words, DO NOT use e1000_phy_has_link_generic() here.\n\t */\n\tfor (i = PHY_FORCE_TIME; i > 0; i--) {\n\t\t/*\n\t\t * Read the MII Status Register and wait for Link Status bit\n\t\t * to be clear.\n\t\t */\n\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tif (!(mii_status_reg & ~MII_SR_LINK_STATUS))\n\t\t\tbreak;\n\t\tmsec_delay_irq(100);\n\t}\n\n\t/* Recommended delay time after link has been lost */\n\tmsec_delay_irq(1000);\n\n\t/* Now we will re-enable the transmitter on the PHY */\n\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);\n\tif (ret_val)\n\t\tgoto out;\n\tmsec_delay_irq(50);\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);\n\tif (ret_val)\n\t\tgoto out;\n\tmsec_delay_irq(50);\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);\n\tif (ret_val)\n\t\tgoto out;\n\tmsec_delay_irq(50);\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/*\n\t * Read the MII Status Register and wait for Link Status bit\n\t * to be set.\n\t */\n\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);\n\tif (ret_val)\n\t\tgoto out;\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_hw_reset_82543 - PHY hardware reset\n * @hw: pointer to the HW structure\n *\n * Sets the PHY_RESET_DIR bit in the extended device control register\n * to put the PHY into a reset and waits for completion. Once the reset\n * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out\n * of reset.\n **/\nSTATIC s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)\n{\n\tu32 ctrl_ext;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_phy_hw_reset_82543\");\n\n\t/*\n\t * Read the Extended Device Control Register, assert the PHY_RESET_DIR\n\t * bit to put the PHY into reset...\n\t */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;\n\tctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\tE1000_WRITE_FLUSH(hw);\n\n\tmsec_delay(10);\n\n\t/* ...then take it out of reset. */\n\tctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\tE1000_WRITE_FLUSH(hw);\n\n\tusec_delay(150);\n\n\tif (!(hw->phy.ops.get_cfg_done))\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->phy.ops.get_cfg_done(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_reset_hw_82543 - Reset hardware\n * @hw: pointer to the HW structure\n *\n * This resets the hardware into a known state.\n **/\nSTATIC s32 e1000_reset_hw_82543(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_reset_hw_82543\");\n\n\tDEBUGOUT(\"Masking off all interrupts\\n\");\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\n\tE1000_WRITE_REG(hw, E1000_RCTL, 0);\n\tE1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);\n\tE1000_WRITE_FLUSH(hw);\n\n\te1000_set_tbi_sbp_82543(hw, false);\n\n\t/*\n\t * Delay to allow any outstanding PCI transactions to complete before\n\t * resetting the device\n\t */\n\tmsec_delay(10);\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\tDEBUGOUT(\"Issuing a global reset to 82543/82544 MAC\\n\");\n\tif (hw->mac.type == e1000_82543) {\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);\n\t} else {\n\t\t/*\n\t\t * The 82544 can't ACK the 64-bit write when issuing the\n\t\t * reset, so use IO-mapping as a workaround.\n\t\t */\n\t\tE1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);\n\t}\n\n\t/*\n\t * After MAC reset, force reload of NVM to restore power-on\n\t * settings to device.\n\t */\n\thw->nvm.ops.reload(hw);\n\tmsec_delay(2);\n\n\t/* Masking off and clearing any pending interrupts */\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\tE1000_READ_REG(hw, E1000_ICR);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_hw_82543 - Initialize hardware\n * @hw: pointer to the HW structure\n *\n * This inits the hardware readying it for operation.\n **/\nSTATIC s32 e1000_init_hw_82543(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tstruct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;\n\tu32 ctrl;\n\ts32 ret_val;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_init_hw_82543\");\n\n\t/* Disabling VLAN filtering */\n\tE1000_WRITE_REG(hw, E1000_VET, 0);\n\tmac->ops.clear_vfta(hw);\n\n\t/* Setup the receive address. */\n\te1000_init_rx_addrs_generic(hw, mac->rar_entry_count);\n\n\t/* Zero out the Multicast HASH table */\n\tDEBUGOUT(\"Zeroing the MTA\\n\");\n\tfor (i = 0; i < mac->mta_reg_count; i++) {\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);\n\t\tE1000_WRITE_FLUSH(hw);\n\t}\n\n\t/*\n\t * Set the PCI priority bit correctly in the CTRL register. This\n\t * determines if the adapter gives priority to receives, or if it\n\t * gives equal priority to transmits and receives.\n\t */\n\tif (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);\n\t}\n\n\te1000_pcix_mmrbc_workaround_generic(hw);\n\n\t/* Setup link and flow control */\n\tret_val = mac->ops.setup_link(hw);\n\n\t/*\n\t * Clear all of the statistics registers (clear on read). It is\n\t * important that we do this after we have tried to establish link\n\t * because the symbol error count will increment wildly if there\n\t * is no link.\n\t */\n\te1000_clear_hw_cntrs_82543(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_link_82543 - Setup flow control and link settings\n * @hw: pointer to the HW structure\n *\n * Read the EEPROM to determine the initial polarity value and write the\n * extended device control register with the information before calling\n * the generic setup link function, which does the following:\n * Determines which flow control settings to use, then configures flow\n * control. Calls the appropriate media-specific link configuration\n * function. Assuming the adapter has a valid link partner, a valid link\n * should be established. Assumes the hardware has previously been reset\n * and the transmitter and receiver are not enabled.\n **/\nSTATIC s32 e1000_setup_link_82543(struct e1000_hw *hw)\n{\n\tu32 ctrl_ext;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_setup_link_82543\");\n\n\t/*\n\t * Take the 4 bits from NVM word 0xF that determine the initial\n\t * polarity value for the SW controlled pins, and setup the\n\t * Extended Device Control reg with that info.\n\t * This is needed because one of the SW controlled pins is used for\n\t * signal detection. So this should be done before phy setup.\n\t */\n\tif (hw->mac.type == e1000_82543) {\n\t\tret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\tret_val = -E1000_ERR_NVM;\n\t\t\tgoto out;\n\t\t}\n\t\tctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<\n\t\t\t NVM_SWDPIO_EXT_SHIFT);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\t}\n\n\tret_val = e1000_setup_link_generic(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_copper_link_82543 - Configure copper link settings\n * @hw: pointer to the HW structure\n *\n * Configures the link for auto-neg or forced speed and duplex. Then we check\n * for link, once link is established calls to configure collision distance\n * and flow control are called.\n **/\nSTATIC s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_setup_copper_link_82543\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;\n\t/*\n\t * With 82543, we need to force speed and duplex on the MAC\n\t * equal to what the PHY speed and duplex configuration is.\n\t * In addition, we need to perform a hardware reset on the\n\t * PHY to take it out of reset.\n\t */\n\tif (hw->mac.type == e1000_82543) {\n\t\tctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\t\tret_val = hw->phy.ops.reset(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t} else {\n\t\tctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\t}\n\n\t/* Set MDI/MDI-X, Polarity Reversal, and downshift settings */\n\tret_val = e1000_copper_link_setup_m88(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (hw->mac.autoneg) {\n\t\t/*\n\t\t * Setup autoneg and flow control advertisement and perform\n\t\t * autonegotiation.\n\t\t */\n\t\tret_val = e1000_copper_link_autoneg(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t} else {\n\t\t/*\n\t\t * PHY will be set to 10H, 10F, 100H or 100F\n\t\t * depending on user settings.\n\t\t */\n\t\tDEBUGOUT(\"Forcing Speed and Duplex\\n\");\n\t\tret_val = e1000_phy_force_speed_duplex_82543(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error Forcing Speed and Duplex\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\t/*\n\t * Check link status. Wait up to 100 microseconds for link to become\n\t * valid.\n\t */\n\tret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,\n\t\t\t\t\t &link);\n\tif (ret_val)\n\t\tgoto out;\n\n\n\tif (link) {\n\t\tDEBUGOUT(\"Valid link established!!!\\n\");\n\t\t/* Config the MAC and PHY after link is up */\n\t\tif (hw->mac.type == e1000_82544) {\n\t\t\thw->mac.ops.config_collision_dist(hw);\n\t\t} else {\n\t\t\tret_val = e1000_config_mac_to_phy_82543(hw);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t}\n\t\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\t} else {\n\t\tDEBUGOUT(\"Unable to establish link!!!\\n\");\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_fiber_link_82543 - Setup link for fiber\n * @hw: pointer to the HW structure\n *\n * Configures collision distance and flow control for fiber links. Upon\n * successful setup, poll for link.\n **/\nSTATIC s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_setup_fiber_link_82543\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\t/* Take the link out of reset */\n\tctrl &= ~E1000_CTRL_LRST;\n\n\thw->mac.ops.config_collision_dist(hw);\n\n\tret_val = e1000_commit_fc_settings_generic(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tDEBUGOUT(\"Auto-negotiation enabled\\n\");\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\tE1000_WRITE_FLUSH(hw);\n\tmsec_delay(1);\n\n\t/*\n\t * For these adapters, the SW definable pin 1 is cleared when the\n\t * optics detect a signal. If we have a signal, then poll for a\n\t * \"Link-Up\" indication.\n\t */\n\tif (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1))\n\t\tret_val = e1000_poll_fiber_serdes_link_generic(hw);\n\telse\n\t\tDEBUGOUT(\"No signal detected\\n\");\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_copper_link_82543 - Check for link (Copper)\n * @hw: pointer to the HW structure\n *\n * Checks the phy for link, if link exists, do the following:\n * - check for downshift\n * - do polarity workaround (if necessary)\n * - configure collision distance\n * - configure flow control after link up\n * - configure tbi compatibility\n **/\nSTATIC s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 icr, rctl;\n\ts32 ret_val;\n\tu16 speed, duplex;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_check_for_copper_link_82543\");\n\n\tif (!mac->get_link_status) {\n\t\tret_val = E1000_SUCCESS;\n\t\tgoto out;\n\t}\n\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (!link)\n\t\tgoto out; /* No link detected */\n\n\tmac->get_link_status = false;\n\n\te1000_check_downshift_generic(hw);\n\n\t/*\n\t * If we are forcing speed/duplex, then we can return since\n\t * we have already determined whether we have link or not.\n\t */\n\tif (!mac->autoneg) {\n\t\t/*\n\t\t * If speed and duplex are forced to 10H or 10F, then we will\n\t\t * implement the polarity reversal workaround. We disable\n\t\t * interrupts first, and upon returning, place the devices\n\t\t * interrupt state to its previous value except for the link\n\t\t * status change interrupt which will happened due to the\n\t\t * execution of this workaround.\n\t\t */\n\t\tif (mac->forced_speed_duplex & E1000_ALL_10_SPEED) {\n\t\t\tE1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);\n\t\t\tret_val = e1000_polarity_reversal_workaround_82543(hw);\n\t\t\ticr = E1000_READ_REG(hw, E1000_ICR);\n\t\t\tE1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));\n\t\t\tE1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);\n\t\t}\n\n\t\tret_val = -E1000_ERR_CONFIG;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * We have a M88E1000 PHY and Auto-Neg is enabled. If we\n\t * have Si on board that is 82544 or newer, Auto\n\t * Speed Detection takes care of MAC speed/duplex\n\t * configuration. So we only need to configure Collision\n\t * Distance in the MAC. Otherwise, we need to force\n\t * speed/duplex on the MAC to the current PHY speed/duplex\n\t * settings.\n\t */\n\tif (mac->type == e1000_82544)\n\t\thw->mac.ops.config_collision_dist(hw);\n\telse {\n\t\tret_val = e1000_config_mac_to_phy_82543(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error configuring MAC to PHY settings\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\t/*\n\t * Configure Flow Control now that Auto-Neg has completed.\n\t * First, we need to restore the desired flow control\n\t * settings because we may have had to re-autoneg with a\n\t * different link partner.\n\t */\n\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n\n\t/*\n\t * At this point we know that we are on copper and we have\n\t * auto-negotiated link. These are conditions for checking the link\n\t * partner capability register. We use the link speed to determine if\n\t * TBI compatibility needs to be turned on or off. If the link is not\n\t * at gigabit speed, then TBI compatibility is not needed. If we are\n\t * at gigabit speed, we turn on TBI compatibility.\n\t */\n\tif (e1000_tbi_compatibility_enabled_82543(hw)) {\n\t\tret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error getting link speed and duplex\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t\tif (speed != SPEED_1000) {\n\t\t\t/*\n\t\t\t * If link speed is not set to gigabit speed,\n\t\t\t * we do not need to enable TBI compatibility.\n\t\t\t */\n\t\t\tif (e1000_tbi_sbp_enabled_82543(hw)) {\n\t\t\t\t/*\n\t\t\t\t * If we previously were in the mode,\n\t\t\t\t * turn it off.\n\t\t\t\t */\n\t\t\t\te1000_set_tbi_sbp_82543(hw, false);\n\t\t\t\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\t\t\t\trctl &= ~E1000_RCTL_SBP;\n\t\t\t\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\t\t\t}\n\t\t} else {\n\t\t\t/*\n\t\t\t * If TBI compatibility is was previously off,\n\t\t\t * turn it on. For compatibility with a TBI link\n\t\t\t * partner, we will store bad packets. Some\n\t\t\t * frames have an additional byte on the end and\n\t\t\t * will look like CRC errors to to the hardware.\n\t\t\t */\n\t\t\tif (!e1000_tbi_sbp_enabled_82543(hw)) {\n\t\t\t\te1000_set_tbi_sbp_82543(hw, true);\n\t\t\t\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\t\t\t\trctl |= E1000_RCTL_SBP;\n\t\t\t\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\t\t\t}\n\t\t}\n\t}\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_fiber_link_82543 - Check for link (Fiber)\n * @hw: pointer to the HW structure\n *\n * Checks for link up on the hardware. If link is not up and we have\n * a signal, then we need to force link up.\n **/\nSTATIC s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 rxcw, ctrl, status;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_check_for_fiber_link_82543\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\trxcw = E1000_READ_REG(hw, E1000_RXCW);\n\n\t/*\n\t * If we don't have link (auto-negotiation failed or link partner\n\t * cannot auto-negotiate), the cable is plugged in (we have signal),\n\t * and our link partner is not trying to auto-negotiate with us (we\n\t * are receiving idles or data), we need to force link up. We also\n\t * need to give auto-negotiation time to complete, in case the cable\n\t * was just plugged in. The autoneg_failed flag does this.\n\t */\n\t/* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */\n\tif ((!(ctrl & E1000_CTRL_SWDPIN1)) &&\n\t (!(status & E1000_STATUS_LU)) &&\n\t (!(rxcw & E1000_RXCW_C))) {\n\t\tif (!mac->autoneg_failed) {\n\t\t\tmac->autoneg_failed = true;\n\t\t\tret_val = 0;\n\t\t\tgoto out;\n\t\t}\n\t\tDEBUGOUT(\"NOT RXing /C/, disable AutoNeg and force link.\\n\");\n\n\t\t/* Disable auto-negotiation in the TXCW register */\n\t\tE1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));\n\n\t\t/* Force link-up and also force full-duplex. */\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\t\t/* Configure Flow Control after forcing link up. */\n\t\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n\t\t\tgoto out;\n\t\t}\n\t} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {\n\t\t/*\n\t\t * If we are forcing link and we are receiving /C/ ordered\n\t\t * sets, re-enable auto-negotiation in the TXCW register\n\t\t * and disable forced link in the Device Control register\n\t\t * in an attempt to auto-negotiate with our link partner.\n\t\t */\n\t\tDEBUGOUT(\"RXing /C/, enable AutoNeg and stop forcing link.\\n\");\n\t\tE1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));\n\n\t\tmac->serdes_has_link = true;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings\n * @hw: pointer to the HW structure\n *\n * For the 82543 silicon, we need to set the MAC to match the settings\n * of the PHY, even if the PHY is auto-negotiating.\n **/\nSTATIC s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_config_mac_to_phy_82543\");\n\n\tif (!(hw->phy.ops.read_reg))\n\t\tgoto out;\n\n\t/* Set the bits to force speed and duplex */\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\tctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);\n\n\t/*\n\t * Set up duplex in the Device Control and Transmit Control\n\t * registers depending on negotiated values.\n\t */\n\tret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);\n\tif (ret_val)\n\t\tgoto out;\n\n\tctrl &= ~E1000_CTRL_FD;\n\tif (phy_data & M88E1000_PSSR_DPLX)\n\t\tctrl |= E1000_CTRL_FD;\n\n\thw->mac.ops.config_collision_dist(hw);\n\n\t/*\n\t * Set up speed in the Device Control register depending on\n\t * negotiated values.\n\t */\n\tif ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)\n\t\tctrl |= E1000_CTRL_SPD_1000;\n\telse if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)\n\t\tctrl |= E1000_CTRL_SPD_100;\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_write_vfta_82543 - Write value to VLAN filter table\n * @hw: pointer to the HW structure\n * @offset: the 32-bit offset in which to write the value to.\n * @value: the 32-bit value to write at location offset.\n *\n * This writes a 32-bit value to a 32-bit offset in the VLAN filter\n * table.\n **/\nSTATIC void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)\n{\n\tu32 temp;\n\n\tDEBUGFUNC(\"e1000_write_vfta_82543\");\n\n\tif ((hw->mac.type == e1000_82544) && (offset & 1)) {\n\t\ttemp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);\n\t\tE1000_WRITE_FLUSH(hw);\n\t} else {\n\t\te1000_write_vfta_generic(hw, offset, value);\n\t}\n}\n\n/**\n * e1000_led_on_82543 - Turn on SW controllable LED\n * @hw: pointer to the HW structure\n *\n * Turns the SW defined LED on.\n **/\nSTATIC s32 e1000_led_on_82543(struct e1000_hw *hw)\n{\n\tu32 ctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\tDEBUGFUNC(\"e1000_led_on_82543\");\n\n\tif (hw->mac.type == e1000_82544 &&\n\t hw->phy.media_type == e1000_media_type_copper) {\n\t\t/* Clear SW-definable Pin 0 to turn on the LED */\n\t\tctrl &= ~E1000_CTRL_SWDPIN0;\n\t\tctrl |= E1000_CTRL_SWDPIO0;\n\t} else {\n\t\t/* Fiber 82544 and all 82543 use this method */\n\t\tctrl |= E1000_CTRL_SWDPIN0;\n\t\tctrl |= E1000_CTRL_SWDPIO0;\n\t}\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_led_off_82543 - Turn off SW controllable LED\n * @hw: pointer to the HW structure\n *\n * Turns the SW defined LED off.\n **/\nSTATIC s32 e1000_led_off_82543(struct e1000_hw *hw)\n{\n\tu32 ctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\tDEBUGFUNC(\"e1000_led_off_82543\");\n\n\tif (hw->mac.type == e1000_82544 &&\n\t hw->phy.media_type == e1000_media_type_copper) {\n\t\t/* Set SW-definable Pin 0 to turn off the LED */\n\t\tctrl |= E1000_CTRL_SWDPIN0;\n\t\tctrl |= E1000_CTRL_SWDPIO0;\n\t} else {\n\t\tctrl &= ~E1000_CTRL_SWDPIN0;\n\t\tctrl |= E1000_CTRL_SWDPIO0;\n\t}\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters\n * @hw: pointer to the HW structure\n *\n * Clears the hardware counters by reading the counter registers.\n **/\nSTATIC void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_clear_hw_cntrs_82543\");\n\n\te1000_clear_hw_cntrs_base_generic(hw);\n\n\tE1000_READ_REG(hw, E1000_PRC64);\n\tE1000_READ_REG(hw, E1000_PRC127);\n\tE1000_READ_REG(hw, E1000_PRC255);\n\tE1000_READ_REG(hw, E1000_PRC511);\n\tE1000_READ_REG(hw, E1000_PRC1023);\n\tE1000_READ_REG(hw, E1000_PRC1522);\n\tE1000_READ_REG(hw, E1000_PTC64);\n\tE1000_READ_REG(hw, E1000_PTC127);\n\tE1000_READ_REG(hw, E1000_PTC255);\n\tE1000_READ_REG(hw, E1000_PTC511);\n\tE1000_READ_REG(hw, E1000_PTC1023);\n\tE1000_READ_REG(hw, E1000_PTC1522);\n\n\tE1000_READ_REG(hw, E1000_ALGNERRC);\n\tE1000_READ_REG(hw, E1000_RXERRC);\n\tE1000_READ_REG(hw, E1000_TNCRS);\n\tE1000_READ_REG(hw, E1000_CEXTERR);\n\tE1000_READ_REG(hw, E1000_TSCTC);\n\tE1000_READ_REG(hw, E1000_TSCTFC);\n}\n" }, { "path": "drivers/net/e1000/base/e1000_82543.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_82543_H_\n#define _E1000_82543_H_\n\n#define PHY_PREAMBLE\t\t0xFFFFFFFF\n#define PHY_PREAMBLE_SIZE\t32\n#define PHY_SOF\t\t\t0x1\n#define PHY_OP_READ\t\t0x2\n#define PHY_OP_WRITE\t\t0x1\n#define PHY_TURNAROUND\t\t0x2\n\n#define TBI_COMPAT_ENABLED\t0x1 /* Global \"knob\" for the workaround */\n/* If TBI_COMPAT_ENABLED, then this is the current state (on/off) */\n#define TBI_SBP_ENABLED\t\t0x2\n\nvoid e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,\n\t\t\t\t struct e1000_hw_stats *stats,\n\t\t\t\t u32 frame_len, u8 *mac_addr,\n\t\t\t\t u32 max_frame_size);\nvoid e1000_set_tbi_compatibility_82543(struct e1000_hw *hw,\n\t\t\t\t bool state);\nbool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw);\n\n#endif\n" }, { "path": "drivers/net/e1000/base/e1000_82571.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n/* 82571EB Gigabit Ethernet Controller\n * 82571EB Gigabit Ethernet Controller (Copper)\n * 82571EB Gigabit Ethernet Controller (Fiber)\n * 82571EB Dual Port Gigabit Mezzanine Adapter\n * 82571EB Quad Port Gigabit Mezzanine Adapter\n * 82571PT Gigabit PT Quad Port Server ExpressModule\n * 82572EI Gigabit Ethernet Controller (Copper)\n * 82572EI Gigabit Ethernet Controller (Fiber)\n * 82572EI Gigabit Ethernet Controller\n * 82573V Gigabit Ethernet Controller (Copper)\n * 82573E Gigabit Ethernet Controller (Copper)\n * 82573L Gigabit Ethernet Controller\n * 82574L Gigabit Network Connection\n * 82583V Gigabit Network Connection\n */\n\n#include \"e1000_api.h\"\n\nSTATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);\nSTATIC void e1000_release_nvm_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data);\nSTATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,\n\t\t\t\t\t bool active);\nSTATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_init_hw_82571(struct e1000_hw *hw);\nSTATIC void e1000_clear_vfta_82571(struct e1000_hw *hw);\nSTATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw);\nSTATIC s32 e1000_led_on_82574(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_link_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);\nSTATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw);\nSTATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);\nSTATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);\nSTATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);\nSTATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);\nSTATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,\n\t\t\t\t\t bool active);\nSTATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,\n\t\t\t\t\t bool active);\nSTATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);\nSTATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data);\nSTATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);\nSTATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);\n\n/**\n * e1000_init_phy_params_82571 - Init PHY func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_init_phy_params_82571\");\n\n\tif (hw->phy.media_type != e1000_media_type_copper) {\n\t\tphy->type = e1000_phy_none;\n\t\treturn E1000_SUCCESS;\n\t}\n\n\tphy->addr\t\t\t= 1;\n\tphy->autoneg_mask\t\t= AUTONEG_ADVERTISE_SPEED_DEFAULT;\n\tphy->reset_delay_us\t\t= 100;\n\n\tphy->ops.check_reset_block\t= e1000_check_reset_block_generic;\n\tphy->ops.reset\t\t\t= e1000_phy_hw_reset_generic;\n\tphy->ops.set_d0_lplu_state\t= e1000_set_d0_lplu_state_82571;\n\tphy->ops.set_d3_lplu_state\t= e1000_set_d3_lplu_state_generic;\n\tphy->ops.power_up\t\t= e1000_power_up_phy_copper;\n\tphy->ops.power_down\t\t= e1000_power_down_phy_copper_82571;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82571:\n\tcase e1000_82572:\n\t\tphy->type\t\t= e1000_phy_igp_2;\n\t\tphy->ops.get_cfg_done\t= e1000_get_cfg_done_82571;\n\t\tphy->ops.get_info\t= e1000_get_phy_info_igp;\n\t\tphy->ops.check_polarity\t= e1000_check_polarity_igp;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;\n\t\tphy->ops.get_cable_length = e1000_get_cable_length_igp_2;\n\t\tphy->ops.read_reg\t= e1000_read_phy_reg_igp;\n\t\tphy->ops.write_reg\t= e1000_write_phy_reg_igp;\n\t\tphy->ops.acquire\t= e1000_get_hw_semaphore_82571;\n\t\tphy->ops.release\t= e1000_put_hw_semaphore_82571;\n\t\tbreak;\n\tcase e1000_82573:\n\t\tphy->type\t\t= e1000_phy_m88;\n\t\tphy->ops.get_cfg_done\t= e1000_get_cfg_done_generic;\n\t\tphy->ops.get_info\t= e1000_get_phy_info_m88;\n\t\tphy->ops.check_polarity\t= e1000_check_polarity_m88;\n\t\tphy->ops.commit\t\t= e1000_phy_sw_reset_generic;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;\n\t\tphy->ops.get_cable_length = e1000_get_cable_length_m88;\n\t\tphy->ops.read_reg\t= e1000_read_phy_reg_m88;\n\t\tphy->ops.write_reg\t= e1000_write_phy_reg_m88;\n\t\tphy->ops.acquire\t= e1000_get_hw_semaphore_82571;\n\t\tphy->ops.release\t= e1000_put_hw_semaphore_82571;\n\t\tbreak;\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\tE1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);\n\n\t\tphy->type\t\t= e1000_phy_bm;\n\t\tphy->ops.get_cfg_done\t= e1000_get_cfg_done_generic;\n\t\tphy->ops.get_info\t= e1000_get_phy_info_m88;\n\t\tphy->ops.check_polarity\t= e1000_check_polarity_m88;\n\t\tphy->ops.commit\t\t= e1000_phy_sw_reset_generic;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;\n\t\tphy->ops.get_cable_length = e1000_get_cable_length_m88;\n\t\tphy->ops.read_reg\t= e1000_read_phy_reg_bm2;\n\t\tphy->ops.write_reg\t= e1000_write_phy_reg_bm2;\n\t\tphy->ops.acquire\t= e1000_get_hw_semaphore_82574;\n\t\tphy->ops.release\t= e1000_put_hw_semaphore_82574;\n\t\tphy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;\n\t\tphy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;\n\t\tbreak;\n\tdefault:\n\t\treturn -E1000_ERR_PHY;\n\t\tbreak;\n\t}\n\n\t/* This can only be done after all function pointers are setup. */\n\tret_val = e1000_get_phy_id_82571(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error getting PHY ID\\n\");\n\t\treturn ret_val;\n\t}\n\n\t/* Verify phy id */\n\tswitch (hw->mac.type) {\n\tcase e1000_82571:\n\tcase e1000_82572:\n\t\tif (phy->id != IGP01E1000_I_PHY_ID)\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\tbreak;\n\tcase e1000_82573:\n\t\tif (phy->id != M88E1111_I_PHY_ID)\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\tbreak;\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\tif (phy->id != BME1000_E_PHY_ID_R2)\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\tbreak;\n\tdefault:\n\t\tret_val = -E1000_ERR_PHY;\n\t\tbreak;\n\t}\n\n\tif (ret_val)\n\t\tDEBUGOUT1(\"PHY ID unknown: type = 0x%08x\\n\", phy->id);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_nvm_params_82571 - Init NVM func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\tu16 size;\n\n\tDEBUGFUNC(\"e1000_init_nvm_params_82571\");\n\n\tnvm->opcode_bits = 8;\n\tnvm->delay_usec = 1;\n\tswitch (nvm->override) {\n\tcase e1000_nvm_override_spi_large:\n\t\tnvm->page_size = 32;\n\t\tnvm->address_bits = 16;\n\t\tbreak;\n\tcase e1000_nvm_override_spi_small:\n\t\tnvm->page_size = 8;\n\t\tnvm->address_bits = 8;\n\t\tbreak;\n\tdefault:\n\t\tnvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;\n\t\tnvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;\n\t\tbreak;\n\t}\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82573:\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\tif (((eecd >> 15) & 0x3) == 0x3) {\n\t\t\tnvm->type = e1000_nvm_flash_hw;\n\t\t\tnvm->word_size = 2048;\n\t\t\t/* Autonomous Flash update bit must be cleared due\n\t\t\t * to Flash update issue.\n\t\t\t */\n\t\t\teecd &= ~E1000_EECD_AUPDEN;\n\t\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\t\tbreak;\n\t\t}\n\t\t/* Fall Through */\n\tdefault:\n\t\tnvm->type = e1000_nvm_eeprom_spi;\n\t\tsize = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>\n\t\t\t E1000_EECD_SIZE_EX_SHIFT);\n\t\t/* Added to a constant, \"size\" becomes the left-shift value\n\t\t * for setting word_size.\n\t\t */\n\t\tsize += NVM_WORD_SIZE_BASE_SHIFT;\n\n\t\t/* EEPROM access above 16k is unsupported */\n\t\tif (size > 14)\n\t\t\tsize = 14;\n\t\tnvm->word_size = 1 << size;\n\t\tbreak;\n\t}\n\n\t/* Function Pointers */\n\tswitch (hw->mac.type) {\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\tnvm->ops.acquire = e1000_get_hw_semaphore_82574;\n\t\tnvm->ops.release = e1000_put_hw_semaphore_82574;\n\t\tbreak;\n\tdefault:\n\t\tnvm->ops.acquire = e1000_acquire_nvm_82571;\n\t\tnvm->ops.release = e1000_release_nvm_82571;\n\t\tbreak;\n\t}\n\tnvm->ops.read = e1000_read_nvm_eerd;\n\tnvm->ops.update = e1000_update_nvm_checksum_82571;\n\tnvm->ops.validate = e1000_validate_nvm_checksum_82571;\n\tnvm->ops.valid_led_default = e1000_valid_led_default_82571;\n\tnvm->ops.write = e1000_write_nvm_82571;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_mac_params_82571 - Init MAC func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 swsm = 0;\n\tu32 swsm2 = 0;\n\tbool force_clear_smbi = false;\n\n\tDEBUGFUNC(\"e1000_init_mac_params_82571\");\n\n\t/* Set media type and media-dependent function pointers */\n\tswitch (hw->device_id) {\n\tcase E1000_DEV_ID_82571EB_FIBER:\n\tcase E1000_DEV_ID_82572EI_FIBER:\n\tcase E1000_DEV_ID_82571EB_QUAD_FIBER:\n\t\thw->phy.media_type = e1000_media_type_fiber;\n\t\tmac->ops.setup_physical_interface =\n\t\t\te1000_setup_fiber_serdes_link_82571;\n\t\tmac->ops.check_for_link = e1000_check_for_fiber_link_generic;\n\t\tmac->ops.get_link_up_info =\n\t\t\te1000_get_speed_and_duplex_fiber_serdes_generic;\n\t\tbreak;\n\tcase E1000_DEV_ID_82571EB_SERDES:\n\tcase E1000_DEV_ID_82571EB_SERDES_DUAL:\n\tcase E1000_DEV_ID_82571EB_SERDES_QUAD:\n\tcase E1000_DEV_ID_82572EI_SERDES:\n\t\thw->phy.media_type = e1000_media_type_internal_serdes;\n\t\tmac->ops.setup_physical_interface =\n\t\t\te1000_setup_fiber_serdes_link_82571;\n\t\tmac->ops.check_for_link = e1000_check_for_serdes_link_82571;\n\t\tmac->ops.get_link_up_info =\n\t\t\te1000_get_speed_and_duplex_fiber_serdes_generic;\n\t\tbreak;\n\tdefault:\n\t\thw->phy.media_type = e1000_media_type_copper;\n\t\tmac->ops.setup_physical_interface =\n\t\t\te1000_setup_copper_link_82571;\n\t\tmac->ops.check_for_link = e1000_check_for_copper_link_generic;\n\t\tmac->ops.get_link_up_info =\n\t\t\te1000_get_speed_and_duplex_copper_generic;\n\t\tbreak;\n\t}\n\n\t/* Set mta register count */\n\tmac->mta_reg_count = 128;\n\t/* Set rar entry count */\n\tmac->rar_entry_count = E1000_RAR_ENTRIES;\n\t/* Set if part includes ASF firmware */\n\tmac->asf_firmware_present = true;\n\t/* Adaptive IFS supported */\n\tmac->adaptive_ifs = true;\n\n\t/* Function pointers */\n\n\t/* bus type/speed/width */\n\tmac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;\n\t/* reset */\n\tmac->ops.reset_hw = e1000_reset_hw_82571;\n\t/* hw initialization */\n\tmac->ops.init_hw = e1000_init_hw_82571;\n\t/* link setup */\n\tmac->ops.setup_link = e1000_setup_link_82571;\n\t/* multicast address update */\n\tmac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;\n\t/* writing VFTA */\n\tmac->ops.write_vfta = e1000_write_vfta_generic;\n\t/* clearing VFTA */\n\tmac->ops.clear_vfta = e1000_clear_vfta_82571;\n\t/* read mac address */\n\tmac->ops.read_mac_addr = e1000_read_mac_addr_82571;\n\t/* ID LED init */\n\tmac->ops.id_led_init = e1000_id_led_init_generic;\n\t/* setup LED */\n\tmac->ops.setup_led = e1000_setup_led_generic;\n\t/* cleanup LED */\n\tmac->ops.cleanup_led = e1000_cleanup_led_generic;\n\t/* turn off LED */\n\tmac->ops.led_off = e1000_led_off_generic;\n\t/* clear hardware counters */\n\tmac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;\n\n\t/* MAC-specific function pointers */\n\tswitch (hw->mac.type) {\n\tcase e1000_82573:\n\t\tmac->ops.set_lan_id = e1000_set_lan_id_single_port;\n\t\tmac->ops.check_mng_mode = e1000_check_mng_mode_generic;\n\t\tmac->ops.led_on = e1000_led_on_generic;\n\t\tmac->ops.blink_led = e1000_blink_led_generic;\n\n\t\t/* FWSM register */\n\t\tmac->has_fwsm = true;\n\t\t/* ARC supported; valid only if manageability features are\n\t\t * enabled.\n\t\t */\n\t\tmac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &\n\t\t\t\t\t E1000_FWSM_MODE_MASK);\n\t\tbreak;\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\tmac->ops.set_lan_id = e1000_set_lan_id_single_port;\n\t\tmac->ops.check_mng_mode = e1000_check_mng_mode_82574;\n\t\tmac->ops.led_on = e1000_led_on_82574;\n\t\tbreak;\n\tdefault:\n\t\tmac->ops.check_mng_mode = e1000_check_mng_mode_generic;\n\t\tmac->ops.led_on = e1000_led_on_generic;\n\t\tmac->ops.blink_led = e1000_blink_led_generic;\n\n\t\t/* FWSM register */\n\t\tmac->has_fwsm = true;\n\t\tbreak;\n\t}\n\n\t/* Ensure that the inter-port SWSM.SMBI lock bit is clear before\n\t * first NVM or PHY access. This should be done for single-port\n\t * devices, and for one port only on dual-port devices so that\n\t * for those devices we can still use the SMBI lock to synchronize\n\t * inter-port accesses to the PHY & NVM.\n\t */\n\tswitch (hw->mac.type) {\n\tcase e1000_82571:\n\tcase e1000_82572:\n\t\tswsm2 = E1000_READ_REG(hw, E1000_SWSM2);\n\n\t\tif (!(swsm2 & E1000_SWSM2_LOCK)) {\n\t\t\t/* Only do this for the first interface on this card */\n\t\t\tE1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |\n\t\t\t\t\tE1000_SWSM2_LOCK);\n\t\t\tforce_clear_smbi = true;\n\t\t} else {\n\t\t\tforce_clear_smbi = false;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tforce_clear_smbi = true;\n\t\tbreak;\n\t}\n\n\tif (force_clear_smbi) {\n\t\t/* Make sure SWSM.SMBI is clear */\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tif (swsm & E1000_SWSM_SMBI) {\n\t\t\t/* This bit should not be set on a first interface, and\n\t\t\t * indicates that the bootagent or EFI code has\n\t\t\t * improperly left this bit enabled\n\t\t\t */\n\t\t\tDEBUGOUT(\"Please update your 82571 Bootagent\\n\");\n\t\t}\n\t\tE1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);\n\t}\n\n\t/* Initialze device specific counter of SMBI acquisition timeouts. */\n\t hw->dev_spec._82571.smb_counter = 0;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_function_pointers_82571 - Init func ptrs.\n * @hw: pointer to the HW structure\n *\n * Called to initialize all function pointers and parameters.\n **/\nvoid e1000_init_function_pointers_82571(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_function_pointers_82571\");\n\n\thw->mac.ops.init_params = e1000_init_mac_params_82571;\n\thw->nvm.ops.init_params = e1000_init_nvm_params_82571;\n\thw->phy.ops.init_params = e1000_init_phy_params_82571;\n}\n\n/**\n * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision\n * @hw: pointer to the HW structure\n *\n * Reads the PHY registers and stores the PHY ID and possibly the PHY\n * revision in the hardware structure.\n **/\nSTATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_id = 0;\n\n\tDEBUGFUNC(\"e1000_get_phy_id_82571\");\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82571:\n\tcase e1000_82572:\n\t\t/* The 82571 firmware may still be configuring the PHY.\n\t\t * In this case, we cannot access the PHY until the\n\t\t * configuration is done. So we explicitly set the\n\t\t * PHY ID.\n\t\t */\n\t\tphy->id = IGP01E1000_I_PHY_ID;\n\t\tbreak;\n\tcase e1000_82573:\n\t\treturn e1000_get_phy_id(hw);\n\t\tbreak;\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\tret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy->id = (u32)(phy_id << 16);\n\t\tusec_delay(20);\n\t\tret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy->id |= (u32)(phy_id);\n\t\tphy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);\n\t\tbreak;\n\tdefault:\n\t\treturn -E1000_ERR_PHY;\n\t\tbreak;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore\n * @hw: pointer to the HW structure\n *\n * Acquire the HW semaphore to access the PHY or NVM\n **/\nSTATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)\n{\n\tu32 swsm;\n\ts32 sw_timeout = hw->nvm.word_size + 1;\n\ts32 fw_timeout = hw->nvm.word_size + 1;\n\ts32 i = 0;\n\n\tDEBUGFUNC(\"e1000_get_hw_semaphore_82571\");\n\n\t/* If we have timedout 3 times on trying to acquire\n\t * the inter-port SMBI semaphore, there is old code\n\t * operating on the other port, and it is not\n\t * releasing SMBI. Modify the number of times that\n\t * we try for the semaphore to interwork with this\n\t * older code.\n\t */\n\tif (hw->dev_spec._82571.smb_counter > 2)\n\t\tsw_timeout = 1;\n\n\t/* Get the SW semaphore */\n\twhile (i < sw_timeout) {\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tif (!(swsm & E1000_SWSM_SMBI))\n\t\t\tbreak;\n\n\t\tusec_delay(50);\n\t\ti++;\n\t}\n\n\tif (i == sw_timeout) {\n\t\tDEBUGOUT(\"Driver can't access device - SMBI bit is set.\\n\");\n\t\thw->dev_spec._82571.smb_counter++;\n\t}\n\t/* Get the FW semaphore. */\n\tfor (i = 0; i < fw_timeout; i++) {\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tE1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);\n\n\t\t/* Semaphore acquired if bit latched */\n\t\tif (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)\n\t\t\tbreak;\n\n\t\tusec_delay(50);\n\t}\n\n\tif (i == fw_timeout) {\n\t\t/* Release semaphores */\n\t\te1000_put_hw_semaphore_82571(hw);\n\t\tDEBUGOUT(\"Driver can't access the NVM\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_put_hw_semaphore_82571 - Release hardware semaphore\n * @hw: pointer to the HW structure\n *\n * Release hardware semaphore used to access the PHY or NVM\n **/\nSTATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)\n{\n\tu32 swsm;\n\n\tDEBUGFUNC(\"e1000_put_hw_semaphore_generic\");\n\n\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\n\tswsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);\n\n\tE1000_WRITE_REG(hw, E1000_SWSM, swsm);\n}\n\n/**\n * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore\n * @hw: pointer to the HW structure\n *\n * Acquire the HW semaphore during reset.\n *\n **/\nSTATIC s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)\n{\n\tu32 extcnf_ctrl;\n\ts32 i = 0;\n\n\tDEBUGFUNC(\"e1000_get_hw_semaphore_82573\");\n\n\textcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);\n\tdo {\n\t\textcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;\n\t\tE1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);\n\t\textcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);\n\n\t\tif (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)\n\t\t\tbreak;\n\n\t\tmsec_delay(2);\n\t\ti++;\n\t} while (i < MDIO_OWNERSHIP_TIMEOUT);\n\n\tif (i == MDIO_OWNERSHIP_TIMEOUT) {\n\t\t/* Release semaphores */\n\t\te1000_put_hw_semaphore_82573(hw);\n\t\tDEBUGOUT(\"Driver can't access the PHY\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_put_hw_semaphore_82573 - Release hardware semaphore\n * @hw: pointer to the HW structure\n *\n * Release hardware semaphore used during reset.\n *\n **/\nSTATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)\n{\n\tu32 extcnf_ctrl;\n\n\tDEBUGFUNC(\"e1000_put_hw_semaphore_82573\");\n\n\textcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);\n\textcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;\n\tE1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);\n}\n\n/**\n * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore\n * @hw: pointer to the HW structure\n *\n * Acquire the HW semaphore to access the PHY or NVM.\n *\n **/\nSTATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_get_hw_semaphore_82574\");\n\n\tE1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);\n\tret_val = e1000_get_hw_semaphore_82573(hw);\n\tif (ret_val)\n\t\tE1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);\n\treturn ret_val;\n}\n\n/**\n * e1000_put_hw_semaphore_82574 - Release hardware semaphore\n * @hw: pointer to the HW structure\n *\n * Release hardware semaphore used to access the PHY or NVM\n *\n **/\nSTATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_put_hw_semaphore_82574\");\n\n\te1000_put_hw_semaphore_82573(hw);\n\tE1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);\n}\n\n/**\n * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state\n * @hw: pointer to the HW structure\n * @active: true to enable LPLU, false to disable\n *\n * Sets the LPLU D0 state according to the active flag.\n * LPLU will not be activated unless the\n * device autonegotiation advertisement meets standards of\n * either 10 or 10/100 or 10/100/1000 at all duplexes.\n * This is a function pointer entry point only called by\n * PHY setup routines.\n **/\nSTATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)\n{\n\tu32 data = E1000_READ_REG(hw, E1000_POEMB);\n\n\tDEBUGFUNC(\"e1000_set_d0_lplu_state_82574\");\n\n\tif (active)\n\t\tdata |= E1000_PHY_CTRL_D0A_LPLU;\n\telse\n\t\tdata &= ~E1000_PHY_CTRL_D0A_LPLU;\n\n\tE1000_WRITE_REG(hw, E1000_POEMB, data);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3\n * @hw: pointer to the HW structure\n * @active: boolean used to enable/disable lplu\n *\n * The low power link up (lplu) state is set to the power management level D3\n * when active is true, else clear lplu for D3. LPLU\n * is used during Dx states where the power conservation is most important.\n * During driver activity, SmartSpeed should be enabled so performance is\n * maintained.\n **/\nSTATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)\n{\n\tu32 data = E1000_READ_REG(hw, E1000_POEMB);\n\n\tDEBUGFUNC(\"e1000_set_d3_lplu_state_82574\");\n\n\tif (!active) {\n\t\tdata &= ~E1000_PHY_CTRL_NOND0A_LPLU;\n\t} else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||\n\t\t (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||\n\t\t (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {\n\t\tdata |= E1000_PHY_CTRL_NOND0A_LPLU;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_POEMB, data);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_acquire_nvm_82571 - Request for access to the EEPROM\n * @hw: pointer to the HW structure\n *\n * To gain access to the EEPROM, first we must obtain a hardware semaphore.\n * Then for non-82573 hardware, set the EEPROM access request bit and wait\n * for EEPROM access grant bit. If the access grant bit is not set, release\n * hardware semaphore.\n **/\nSTATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_acquire_nvm_82571\");\n\n\tret_val = e1000_get_hw_semaphore_82571(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82573:\n\t\tbreak;\n\tdefault:\n\t\tret_val = e1000_acquire_nvm_generic(hw);\n\t\tbreak;\n\t}\n\n\tif (ret_val)\n\t\te1000_put_hw_semaphore_82571(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_release_nvm_82571 - Release exclusive access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Stop any current commands to the EEPROM and clear the EEPROM request bit.\n **/\nSTATIC void e1000_release_nvm_82571(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_release_nvm_82571\");\n\n\te1000_release_nvm_generic(hw);\n\te1000_put_hw_semaphore_82571(hw);\n}\n\n/**\n * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface\n * @hw: pointer to the HW structure\n * @offset: offset within the EEPROM to be written to\n * @words: number of words to write\n * @data: 16 bit word(s) to be written to the EEPROM\n *\n * For non-82573 silicon, write data to EEPROM at offset using SPI interface.\n *\n * If e1000_update_nvm_checksum is not called after this function, the\n * EEPROM will most likely contain an invalid checksum.\n **/\nSTATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t\t u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_write_nvm_82571\");\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82573:\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\tret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);\n\t\tbreak;\n\tcase e1000_82571:\n\tcase e1000_82572:\n\t\tret_val = e1000_write_nvm_spi(hw, offset, words, data);\n\t\tbreak;\n\tdefault:\n\t\tret_val = -E1000_ERR_NVM;\n\t\tbreak;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_update_nvm_checksum_82571 - Update EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Updates the EEPROM checksum by reading/adding each word of the EEPROM\n * up to the checksum. Then calculates the EEPROM checksum and writes the\n * value to the EEPROM.\n **/\nSTATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)\n{\n\tu32 eecd;\n\ts32 ret_val;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_update_nvm_checksum_82571\");\n\n\tret_val = e1000_update_nvm_checksum_generic(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* If our nvm is an EEPROM, then we're done\n\t * otherwise, commit the checksum to the flash NVM.\n\t */\n\tif (hw->nvm.type != e1000_nvm_flash_hw)\n\t\treturn E1000_SUCCESS;\n\n\t/* Check for pending operations. */\n\tfor (i = 0; i < E1000_FLASH_UPDATES; i++) {\n\t\tmsec_delay(1);\n\t\tif (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))\n\t\t\tbreak;\n\t}\n\n\tif (i == E1000_FLASH_UPDATES)\n\t\treturn -E1000_ERR_NVM;\n\n\t/* Reset the firmware if using STM opcode. */\n\tif ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {\n\t\t/* The enabling of and the actual reset must be done\n\t\t * in two write cycles.\n\t\t */\n\t\tE1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tE1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);\n\t}\n\n\t/* Commit the write to flash */\n\teecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;\n\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\n\tfor (i = 0; i < E1000_FLASH_UPDATES; i++) {\n\t\tmsec_delay(1);\n\t\tif (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))\n\t\t\tbreak;\n\t}\n\n\tif (i == E1000_FLASH_UPDATES)\n\t\treturn -E1000_ERR_NVM;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Calculates the EEPROM checksum by reading/adding each word of the EEPROM\n * and then verifies that the sum of the EEPROM is equal to 0xBABA.\n **/\nSTATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_validate_nvm_checksum_82571\");\n\n\tif (hw->nvm.type == e1000_nvm_flash_hw)\n\t\te1000_fix_nvm_checksum_82571(hw);\n\n\treturn e1000_validate_nvm_checksum_generic(hw);\n}\n\n/**\n * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon\n * @hw: pointer to the HW structure\n * @offset: offset within the EEPROM to be written to\n * @words: number of words to write\n * @data: 16 bit word(s) to be written to the EEPROM\n *\n * After checking for invalid values, poll the EEPROM to ensure the previous\n * command has completed before trying to write the next word. After write\n * poll for completion.\n *\n * If e1000_update_nvm_checksum is not called after this function, the\n * EEPROM will most likely contain an invalid checksum.\n **/\nSTATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 i, eewr = 0;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_write_nvm_eewr_82571\");\n\n\t/* A check for invalid values: offset too large, too many words,\n\t * and not enough words.\n\t */\n\tif ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\tfor (i = 0; i < words; i++) {\n\t\teewr = ((data[i] << E1000_NVM_RW_REG_DATA) |\n\t\t\t((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |\n\t\t\tE1000_NVM_RW_REG_START);\n\n\t\tret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);\n\t\tif (ret_val)\n\t\t\tbreak;\n\n\t\tE1000_WRITE_REG(hw, E1000_EEWR, eewr);\n\n\t\tret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);\n\t\tif (ret_val)\n\t\t\tbreak;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_cfg_done_82571 - Poll for configuration done\n * @hw: pointer to the HW structure\n *\n * Reads the management control register for the config done bit to be set.\n **/\nSTATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)\n{\n\ts32 timeout = PHY_CFG_TIMEOUT;\n\n\tDEBUGFUNC(\"e1000_get_cfg_done_82571\");\n\n\twhile (timeout) {\n\t\tif (E1000_READ_REG(hw, E1000_EEMNGCTL) &\n\t\t E1000_NVM_CFG_DONE_PORT_0)\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t\ttimeout--;\n\t}\n\tif (!timeout) {\n\t\tDEBUGOUT(\"MNG configuration cycle has not completed.\\n\");\n\t\treturn -E1000_ERR_RESET;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state\n * @hw: pointer to the HW structure\n * @active: true to enable LPLU, false to disable\n *\n * Sets the LPLU D0 state according to the active flag. When activating LPLU\n * this function also disables smart speed and vice versa. LPLU will not be\n * activated unless the device autonegotiation advertisement meets standards\n * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function\n * pointer entry point only called by PHY setup routines.\n **/\nSTATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_set_d0_lplu_state_82571\");\n\n\tif (!(phy->ops.read_reg))\n\t\treturn E1000_SUCCESS;\n\n\tret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (active) {\n\t\tdata |= IGP02E1000_PM_D0_LPLU;\n\t\tret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,\n\t\t\t\t\t data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n\t\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\tret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\tdata &= ~IGP02E1000_PM_D0_LPLU;\n\t\tret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,\n\t\t\t\t\t data);\n\t\t/* LPLU and SmartSpeed are mutually exclusive. LPLU is used\n\t\t * during Dx states where the power conservation is most\n\t\t * important. During driver activity we should enable\n\t\t * SmartSpeed, so performance is maintained.\n\t\t */\n\t\tif (phy->smart_speed == e1000_smart_speed_on) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata |= IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t} else if (phy->smart_speed == e1000_smart_speed_off) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_reset_hw_82571 - Reset hardware\n * @hw: pointer to the HW structure\n *\n * This resets the hardware into a known state.\n **/\nSTATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw)\n{\n\tu32 ctrl, ctrl_ext, eecd, tctl;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_reset_hw_82571\");\n\n\t/* Prevent the PCI-E bus from sticking if there is no TLP connection\n\t * on the last TLP read/write transaction when MAC is reset.\n\t */\n\tret_val = e1000_disable_pcie_master_generic(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"PCI-E Master disable polling has failed.\\n\");\n\n\tDEBUGOUT(\"Masking off all interrupts\\n\");\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\n\tE1000_WRITE_REG(hw, E1000_RCTL, 0);\n\ttctl = E1000_READ_REG(hw, E1000_TCTL);\n\ttctl &= ~E1000_TCTL_EN;\n\tE1000_WRITE_REG(hw, E1000_TCTL, tctl);\n\tE1000_WRITE_FLUSH(hw);\n\n\tmsec_delay(10);\n\n\t/* Must acquire the MDIO ownership before MAC reset.\n\t * Ownership defaults to firmware after a reset.\n\t */\n\tswitch (hw->mac.type) {\n\tcase e1000_82573:\n\t\tret_val = e1000_get_hw_semaphore_82573(hw);\n\t\tbreak;\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\tret_val = e1000_get_hw_semaphore_82574(hw);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\tDEBUGOUT(\"Issuing a global reset to MAC\\n\");\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);\n\n\t/* Must release MDIO ownership and mutex after MAC reset. */\n\tswitch (hw->mac.type) {\n\tcase e1000_82573:\n\t\t/* Release mutex only if the hw semaphore is acquired */\n\t\tif (!ret_val)\n\t\t\te1000_put_hw_semaphore_82573(hw);\n\t\tbreak;\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\t/* Release mutex only if the hw semaphore is acquired */\n\t\tif (!ret_val)\n\t\t\te1000_put_hw_semaphore_82574(hw);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (hw->nvm.type == e1000_nvm_flash_hw) {\n\t\tusec_delay(10);\n\t\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\tctrl_ext |= E1000_CTRL_EXT_EE_RST;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\t\tE1000_WRITE_FLUSH(hw);\n\t}\n\n\tret_val = e1000_get_auto_rd_done_generic(hw);\n\tif (ret_val)\n\t\t/* We don't want to continue accessing MAC registers. */\n\t\treturn ret_val;\n\n\t/* Phy configuration from NVM just starts after EECD_AUTO_RD is set.\n\t * Need to wait for Phy configuration completion before accessing\n\t * NVM and Phy.\n\t */\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82571:\n\tcase e1000_82572:\n\t\t/* REQ and GNT bits need to be cleared when using AUTO_RD\n\t\t * to access the EEPROM.\n\t\t */\n\t\teecd = E1000_READ_REG(hw, E1000_EECD);\n\t\teecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tbreak;\n\tcase e1000_82573:\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\tmsec_delay(25);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Clear any pending interrupt events. */\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\tE1000_READ_REG(hw, E1000_ICR);\n\n\tif (hw->mac.type == e1000_82571) {\n\t\t/* Install any alternate MAC address into RAR0 */\n\t\tret_val = e1000_check_alt_mac_addr_generic(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\te1000_set_laa_state_82571(hw, true);\n\t}\n\n\t/* Reinitialize the 82571 serdes link state machine */\n\tif (hw->phy.media_type == e1000_media_type_internal_serdes)\n\t\thw->mac.serdes_link_state = e1000_serdes_link_down;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_hw_82571 - Initialize hardware\n * @hw: pointer to the HW structure\n *\n * This inits the hardware readying it for operation.\n **/\nSTATIC s32 e1000_init_hw_82571(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 reg_data;\n\ts32 ret_val;\n\tu16 i, rar_count = mac->rar_entry_count;\n\n\tDEBUGFUNC(\"e1000_init_hw_82571\");\n\n\te1000_initialize_hw_bits_82571(hw);\n\n\t/* Initialize identification LED */\n\tret_val = mac->ops.id_led_init(hw);\n\t/* An error is not fatal and we should not stop init due to this */\n\tif (ret_val)\n\t\tDEBUGOUT(\"Error initializing identification LED\\n\");\n\n\t/* Disabling VLAN filtering */\n\tDEBUGOUT(\"Initializing the IEEE VLAN\\n\");\n\tmac->ops.clear_vfta(hw);\n\n\t/* Setup the receive address.\n\t * If, however, a locally administered address was assigned to the\n\t * 82571, we must reserve a RAR for it to work around an issue where\n\t * resetting one port will reload the MAC on the other port.\n\t */\n\tif (e1000_get_laa_state_82571(hw))\n\t\trar_count--;\n\te1000_init_rx_addrs_generic(hw, rar_count);\n\n\t/* Zero out the Multicast HASH table */\n\tDEBUGOUT(\"Zeroing the MTA\\n\");\n\tfor (i = 0; i < mac->mta_reg_count; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);\n\n\t/* Setup link and flow control */\n\tret_val = mac->ops.setup_link(hw);\n\n\t/* Set the transmit descriptor write-back policy */\n\treg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));\n\treg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |\n\t\t E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);\n\n\t/* ...for both queues. */\n\tswitch (mac->type) {\n\tcase e1000_82573:\n\t\te1000_enable_tx_pkt_filtering_generic(hw);\n\t\t/* fall through */\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\treg_data = E1000_READ_REG(hw, E1000_GCR);\n\t\treg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;\n\t\tE1000_WRITE_REG(hw, E1000_GCR, reg_data);\n\t\tbreak;\n\tdefault:\n\t\treg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));\n\t\treg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |\n\t\t\t E1000_TXDCTL_FULL_TX_DESC_WB |\n\t\t\t E1000_TXDCTL_COUNT_DESC);\n\t\tE1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);\n\t\tbreak;\n\t}\n\n\t/* Clear all of the statistics registers (clear on read). It is\n\t * important that we do this after we have tried to establish link\n\t * because the symbol error count will increment wildly if there\n\t * is no link.\n\t */\n\te1000_clear_hw_cntrs_82571(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits\n * @hw: pointer to the HW structure\n *\n * Initializes required hardware-dependent bits needed for normal operation.\n **/\nSTATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)\n{\n\tu32 reg;\n\n\tDEBUGFUNC(\"e1000_initialize_hw_bits_82571\");\n\n\t/* Transmit Descriptor Control 0 */\n\treg = E1000_READ_REG(hw, E1000_TXDCTL(0));\n\treg |= (1 << 22);\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);\n\n\t/* Transmit Descriptor Control 1 */\n\treg = E1000_READ_REG(hw, E1000_TXDCTL(1));\n\treg |= (1 << 22);\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);\n\n\t/* Transmit Arbitration Control 0 */\n\treg = E1000_READ_REG(hw, E1000_TARC(0));\n\treg &= ~(0xF << 27); /* 30:27 */\n\tswitch (hw->mac.type) {\n\tcase e1000_82571:\n\tcase e1000_82572:\n\t\treg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);\n\t\tbreak;\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\treg |= (1 << 26);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\tE1000_WRITE_REG(hw, E1000_TARC(0), reg);\n\n\t/* Transmit Arbitration Control 1 */\n\treg = E1000_READ_REG(hw, E1000_TARC(1));\n\tswitch (hw->mac.type) {\n\tcase e1000_82571:\n\tcase e1000_82572:\n\t\treg &= ~((1 << 29) | (1 << 30));\n\t\treg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);\n\t\tif (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)\n\t\t\treg &= ~(1 << 28);\n\t\telse\n\t\t\treg |= (1 << 28);\n\t\tE1000_WRITE_REG(hw, E1000_TARC(1), reg);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Device Control */\n\tswitch (hw->mac.type) {\n\tcase e1000_82573:\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\treg = E1000_READ_REG(hw, E1000_CTRL);\n\t\treg &= ~(1 << 29);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, reg);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Extended Device Control */\n\tswitch (hw->mac.type) {\n\tcase e1000_82573:\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\treg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\treg &= ~(1 << 23);\n\t\treg |= (1 << 22);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (hw->mac.type == e1000_82571) {\n\t\treg = E1000_READ_REG(hw, E1000_PBA_ECC);\n\t\treg |= E1000_PBA_ECC_CORR_EN;\n\t\tE1000_WRITE_REG(hw, E1000_PBA_ECC, reg);\n\t}\n\n\t/* Workaround for hardware errata.\n\t * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572\n\t */\n\tif ((hw->mac.type == e1000_82571) ||\n\t (hw->mac.type == e1000_82572)) {\n\t\treg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\treg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);\n\t}\n\n\t/* Disable IPv6 extension header parsing because some malformed\n\t * IPv6 headers can hang the Rx.\n\t */\n\tif (hw->mac.type <= e1000_82573) {\n\t\treg = E1000_READ_REG(hw, E1000_RFCTL);\n\t\treg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);\n\t\tE1000_WRITE_REG(hw, E1000_RFCTL, reg);\n\t}\n\n\t/* PCI-Ex Control Registers */\n\tswitch (hw->mac.type) {\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\treg = E1000_READ_REG(hw, E1000_GCR);\n\t\treg |= (1 << 22);\n\t\tE1000_WRITE_REG(hw, E1000_GCR, reg);\n\n\t\t/* Workaround for hardware errata.\n\t\t * apply workaround for hardware errata documented in errata\n\t\t * docs Fixes issue where some error prone or unreliable PCIe\n\t\t * completions are occurring, particularly with ASPM enabled.\n\t\t * Without fix, issue can cause Tx timeouts.\n\t\t */\n\t\treg = E1000_READ_REG(hw, E1000_GCR2);\n\t\treg |= 1;\n\t\tE1000_WRITE_REG(hw, E1000_GCR2, reg);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn;\n}\n\n/**\n * e1000_clear_vfta_82571 - Clear VLAN filter table\n * @hw: pointer to the HW structure\n *\n * Clears the register array which contains the VLAN filter table by\n * setting all the values to 0.\n **/\nSTATIC void e1000_clear_vfta_82571(struct e1000_hw *hw)\n{\n\tu32 offset;\n\tu32 vfta_value = 0;\n\tu32 vfta_offset = 0;\n\tu32 vfta_bit_in_reg = 0;\n\n\tDEBUGFUNC(\"e1000_clear_vfta_82571\");\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82573:\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\tif (hw->mng_cookie.vlan_id != 0) {\n\t\t\t/* The VFTA is a 4096b bit-field, each identifying\n\t\t\t * a single VLAN ID. The following operations\n\t\t\t * determine which 32b entry (i.e. offset) into the\n\t\t\t * array we want to set the VLAN ID (i.e. bit) of\n\t\t\t * the manageability unit.\n\t\t\t */\n\t\t\tvfta_offset = (hw->mng_cookie.vlan_id >>\n\t\t\t\t E1000_VFTA_ENTRY_SHIFT) &\n\t\t\t E1000_VFTA_ENTRY_MASK;\n\t\t\tvfta_bit_in_reg =\n\t\t\t 1 << (hw->mng_cookie.vlan_id &\n\t\t\t\t E1000_VFTA_ENTRY_BIT_SHIFT_MASK);\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\tfor (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {\n\t\t/* If the offset we want to clear is the same offset of the\n\t\t * manageability VLAN ID, then clear all bits except that of\n\t\t * the manageability unit.\n\t\t */\n\t\tvfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);\n\t\tE1000_WRITE_FLUSH(hw);\n\t}\n}\n\n/**\n * e1000_check_mng_mode_82574 - Check manageability is enabled\n * @hw: pointer to the HW structure\n *\n * Reads the NVM Initialization Control Word 2 and returns true\n * (>0) if any manageability is enabled, else false (0).\n **/\nSTATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw)\n{\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_check_mng_mode_82574\");\n\n\thw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);\n\treturn (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;\n}\n\n/**\n * e1000_led_on_82574 - Turn LED on\n * @hw: pointer to the HW structure\n *\n * Turn LED on.\n **/\nSTATIC s32 e1000_led_on_82574(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\tu32 i;\n\n\tDEBUGFUNC(\"e1000_led_on_82574\");\n\n\tctrl = hw->mac.ledctl_mode2;\n\tif (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {\n\t\t/* If no link, then turn LED on by setting the invert bit\n\t\t * for each LED that's \"on\" (0x0E) in ledctl_mode2.\n\t\t */\n\t\tfor (i = 0; i < 4; i++)\n\t\t\tif (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==\n\t\t\t E1000_LEDCTL_MODE_LED_ON)\n\t\t\t\tctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));\n\t}\n\tE1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_check_phy_82574 - check 82574 phy hung state\n * @hw: pointer to the HW structure\n *\n * Returns whether phy is hung or not\n **/\nbool e1000_check_phy_82574(struct e1000_hw *hw)\n{\n\tu16 status_1kbt = 0;\n\tu16 receive_errors = 0;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_check_phy_82574\");\n\n\t/* Read PHY Receive Error counter first, if its is max - all F's then\n\t * read the Base1000T status register If both are max then PHY is hung.\n\t */\n\tret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,\n\t\t\t\t &receive_errors);\n\tif (ret_val)\n\t\treturn false;\n\tif (receive_errors == E1000_RECEIVE_ERROR_MAX) {\n\t\tret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,\n\t\t\t\t\t &status_1kbt);\n\t\tif (ret_val)\n\t\t\treturn false;\n\t\tif ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==\n\t\t E1000_IDLE_ERROR_COUNT_MASK)\n\t\t\treturn true;\n\t}\n\n\treturn false;\n}\n\n\n/**\n * e1000_setup_link_82571 - Setup flow control and link settings\n * @hw: pointer to the HW structure\n *\n * Determines which flow control settings to use, then configures flow\n * control. Calls the appropriate media-specific link configuration\n * function. Assuming the adapter has a valid link partner, a valid link\n * should be established. Assumes the hardware has previously been reset\n * and the transmitter and receiver are not enabled.\n **/\nSTATIC s32 e1000_setup_link_82571(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_setup_link_82571\");\n\n\t/* 82573 does not have a word in the NVM to determine\n\t * the default flow control setting, so we explicitly\n\t * set it to full.\n\t */\n\tswitch (hw->mac.type) {\n\tcase e1000_82573:\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\tif (hw->fc.requested_mode == e1000_fc_default)\n\t\t\thw->fc.requested_mode = e1000_fc_full;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn e1000_setup_link_generic(hw);\n}\n\n/**\n * e1000_setup_copper_link_82571 - Configure copper link settings\n * @hw: pointer to the HW structure\n *\n * Configures the link for auto-neg or forced speed and duplex. Then we check\n * for link, once link is established calls to configure collision distance\n * and flow control are called.\n **/\nSTATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_setup_copper_link_82571\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= E1000_CTRL_SLU;\n\tctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\tswitch (hw->phy.type) {\n\tcase e1000_phy_m88:\n\tcase e1000_phy_bm:\n\t\tret_val = e1000_copper_link_setup_m88(hw);\n\t\tbreak;\n\tcase e1000_phy_igp_2:\n\t\tret_val = e1000_copper_link_setup_igp(hw);\n\t\tbreak;\n\tdefault:\n\t\treturn -E1000_ERR_PHY;\n\t\tbreak;\n\t}\n\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn e1000_setup_copper_link_generic(hw);\n}\n\n/**\n * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes\n * @hw: pointer to the HW structure\n *\n * Configures collision distance and flow control for fiber and serdes links.\n * Upon successful setup, poll for link.\n **/\nSTATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_setup_fiber_serdes_link_82571\");\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82571:\n\tcase e1000_82572:\n\t\t/* If SerDes loopback mode is entered, there is no form\n\t\t * of reset to take the adapter out of that mode. So we\n\t\t * have to explicitly take the adapter out of loopback\n\t\t * mode. This prevents drivers from twiddling their thumbs\n\t\t * if another tool failed to take it out of loopback mode.\n\t\t */\n\t\tE1000_WRITE_REG(hw, E1000_SCTL,\n\t\t\t\tE1000_SCTL_DISABLE_SERDES_LOOPBACK);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn e1000_setup_fiber_serdes_link_generic(hw);\n}\n\n/**\n * e1000_check_for_serdes_link_82571 - Check for link (Serdes)\n * @hw: pointer to the HW structure\n *\n * Reports the link state as up or down.\n *\n * If autonegotiation is supported by the link partner, the link state is\n * determined by the result of autonegotiation. This is the most likely case.\n * If autonegotiation is not supported by the link partner, and the link\n * has a valid signal, force the link up.\n *\n * The link state is represented internally here by 4 states:\n *\n * 1) down\n * 2) autoneg_progress\n * 3) autoneg_complete (the link successfully autonegotiated)\n * 4) forced_up (the link has been forced up, it did not autonegotiate)\n *\n **/\nSTATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 rxcw;\n\tu32 ctrl;\n\tu32 status;\n\tu32 txcw;\n\tu32 i;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_check_for_serdes_link_82571\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\tE1000_READ_REG(hw, E1000_RXCW);\n\t/* SYNCH bit and IV bit are sticky */\n\tusec_delay(10);\n\trxcw = E1000_READ_REG(hw, E1000_RXCW);\n\n\tif ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {\n\t\t/* Receiver is synchronized with no invalid bits. */\n\t\tswitch (mac->serdes_link_state) {\n\t\tcase e1000_serdes_link_autoneg_complete:\n\t\t\tif (!(status & E1000_STATUS_LU)) {\n\t\t\t\t/* We have lost link, retry autoneg before\n\t\t\t\t * reporting link failure\n\t\t\t\t */\n\t\t\t\tmac->serdes_link_state =\n\t\t\t\t e1000_serdes_link_autoneg_progress;\n\t\t\t\tmac->serdes_has_link = false;\n\t\t\t\tDEBUGOUT(\"AN_UP -> AN_PROG\\n\");\n\t\t\t} else {\n\t\t\t\tmac->serdes_has_link = true;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase e1000_serdes_link_forced_up:\n\t\t\t/* If we are receiving /C/ ordered sets, re-enable\n\t\t\t * auto-negotiation in the TXCW register and disable\n\t\t\t * forced link in the Device Control register in an\n\t\t\t * attempt to auto-negotiate with our link partner.\n\t\t\t */\n\t\t\tif (rxcw & E1000_RXCW_C) {\n\t\t\t\t/* Enable autoneg, and unforce link up */\n\t\t\t\tE1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);\n\t\t\t\tE1000_WRITE_REG(hw, E1000_CTRL,\n\t\t\t\t (ctrl & ~E1000_CTRL_SLU));\n\t\t\t\tmac->serdes_link_state =\n\t\t\t\t e1000_serdes_link_autoneg_progress;\n\t\t\t\tmac->serdes_has_link = false;\n\t\t\t\tDEBUGOUT(\"FORCED_UP -> AN_PROG\\n\");\n\t\t\t} else {\n\t\t\t\tmac->serdes_has_link = true;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase e1000_serdes_link_autoneg_progress:\n\t\t\tif (rxcw & E1000_RXCW_C) {\n\t\t\t\t/* We received /C/ ordered sets, meaning the\n\t\t\t\t * link partner has autonegotiated, and we can\n\t\t\t\t * trust the Link Up (LU) status bit.\n\t\t\t\t */\n\t\t\t\tif (status & E1000_STATUS_LU) {\n\t\t\t\t\tmac->serdes_link_state =\n\t\t\t\t\t e1000_serdes_link_autoneg_complete;\n\t\t\t\t\tDEBUGOUT(\"AN_PROG -> AN_UP\\n\");\n\t\t\t\t\tmac->serdes_has_link = true;\n\t\t\t\t} else {\n\t\t\t\t\t/* Autoneg completed, but failed. */\n\t\t\t\t\tmac->serdes_link_state =\n\t\t\t\t\t e1000_serdes_link_down;\n\t\t\t\t\tDEBUGOUT(\"AN_PROG -> DOWN\\n\");\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\t/* The link partner did not autoneg.\n\t\t\t\t * Force link up and full duplex, and change\n\t\t\t\t * state to forced.\n\t\t\t\t */\n\t\t\t\tE1000_WRITE_REG(hw, E1000_TXCW,\n\t\t\t\t(mac->txcw & ~E1000_TXCW_ANE));\n\t\t\t\tctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);\n\t\t\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\t\t\t\t/* Configure Flow Control after link up. */\n\t\t\t\tret_val =\n\t\t\t\t e1000_config_fc_after_link_up_generic(hw);\n\t\t\t\tif (ret_val) {\n\t\t\t\t\tDEBUGOUT(\"Error config flow control\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tmac->serdes_link_state =\n\t\t\t\t\t\te1000_serdes_link_forced_up;\n\t\t\t\tmac->serdes_has_link = true;\n\t\t\t\tDEBUGOUT(\"AN_PROG -> FORCED_UP\\n\");\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase e1000_serdes_link_down:\n\t\tdefault:\n\t\t\t/* The link was down but the receiver has now gained\n\t\t\t * valid sync, so lets see if we can bring the link\n\t\t\t * up.\n\t\t\t */\n\t\t\tE1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);\n\t\t\tE1000_WRITE_REG(hw, E1000_CTRL, (ctrl &\n\t\t\t\t\t~E1000_CTRL_SLU));\n\t\t\tmac->serdes_link_state =\n\t\t\t\t\te1000_serdes_link_autoneg_progress;\n\t\t\tmac->serdes_has_link = false;\n\t\t\tDEBUGOUT(\"DOWN -> AN_PROG\\n\");\n\t\t\tbreak;\n\t\t}\n\t} else {\n\t\tif (!(rxcw & E1000_RXCW_SYNCH)) {\n\t\t\tmac->serdes_has_link = false;\n\t\t\tmac->serdes_link_state = e1000_serdes_link_down;\n\t\t\tDEBUGOUT(\"ANYSTATE -> DOWN\\n\");\n\t\t} else {\n\t\t\t/* Check several times, if SYNCH bit and CONFIG\n\t\t\t * bit both are consistently 1 then simply ignore\n\t\t\t * the IV bit and restart Autoneg\n\t\t\t */\n\t\t\tfor (i = 0; i < AN_RETRY_COUNT; i++) {\n\t\t\t\tusec_delay(10);\n\t\t\t\trxcw = E1000_READ_REG(hw, E1000_RXCW);\n\t\t\t\tif ((rxcw & E1000_RXCW_SYNCH) &&\n\t\t\t\t (rxcw & E1000_RXCW_C))\n\t\t\t\t\tcontinue;\n\n\t\t\t\tif (rxcw & E1000_RXCW_IV) {\n\t\t\t\t\tmac->serdes_has_link = false;\n\t\t\t\t\tmac->serdes_link_state =\n\t\t\t\t\t\t\te1000_serdes_link_down;\n\t\t\t\t\tDEBUGOUT(\"ANYSTATE -> DOWN\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (i == AN_RETRY_COUNT) {\n\t\t\t\ttxcw = E1000_READ_REG(hw, E1000_TXCW);\n\t\t\t\ttxcw |= E1000_TXCW_ANE;\n\t\t\t\tE1000_WRITE_REG(hw, E1000_TXCW, txcw);\n\t\t\t\tmac->serdes_link_state =\n\t\t\t\t\te1000_serdes_link_autoneg_progress;\n\t\t\t\tmac->serdes_has_link = false;\n\t\t\t\tDEBUGOUT(\"ANYSTATE -> AN_PROG\\n\");\n\t\t\t}\n\t\t}\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_valid_led_default_82571 - Verify a valid default LED config\n * @hw: pointer to the HW structure\n * @data: pointer to the NVM (EEPROM)\n *\n * Read the EEPROM for the current default LED configuration. If the\n * LED configuration is not valid, set to a valid LED configuration.\n **/\nSTATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_valid_led_default_82571\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82573:\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\tif (*data == ID_LED_RESERVED_F746)\n\t\t\t*data = ID_LED_DEFAULT_82573;\n\t\tbreak;\n\tdefault:\n\t\tif (*data == ID_LED_RESERVED_0000 ||\n\t\t *data == ID_LED_RESERVED_FFFF)\n\t\t\t*data = ID_LED_DEFAULT;\n\t\tbreak;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_laa_state_82571 - Get locally administered address state\n * @hw: pointer to the HW structure\n *\n * Retrieve and return the current locally administered address state.\n **/\nbool e1000_get_laa_state_82571(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_get_laa_state_82571\");\n\n\tif (hw->mac.type != e1000_82571)\n\t\treturn false;\n\n\treturn hw->dev_spec._82571.laa_is_present;\n}\n\n/**\n * e1000_set_laa_state_82571 - Set locally administered address state\n * @hw: pointer to the HW structure\n * @state: enable/disable locally administered address\n *\n * Enable/Disable the current locally administered address state.\n **/\nvoid e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)\n{\n\tDEBUGFUNC(\"e1000_set_laa_state_82571\");\n\n\tif (hw->mac.type != e1000_82571)\n\t\treturn;\n\n\thw->dev_spec._82571.laa_is_present = state;\n\n\t/* If workaround is activated... */\n\tif (state)\n\t\t/* Hold a copy of the LAA in RAR[14] This is done so that\n\t\t * between the time RAR[0] gets clobbered and the time it\n\t\t * gets fixed, the actual LAA is in one of the RARs and no\n\t\t * incoming packets directed to this port are dropped.\n\t\t * Eventually the LAA will be in RAR[0] and RAR[14].\n\t\t */\n\t\thw->mac.ops.rar_set(hw, hw->mac.addr,\n\t\t\t\t hw->mac.rar_entry_count - 1);\n\treturn;\n}\n\n/**\n * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Verifies that the EEPROM has completed the update. After updating the\n * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If\n * the checksum fix is not implemented, we need to set the bit and update\n * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,\n * we need to return bad checksum.\n **/\nSTATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_fix_nvm_checksum_82571\");\n\n\tif (nvm->type != e1000_nvm_flash_hw)\n\t\treturn E1000_SUCCESS;\n\n\t/* Check bit 4 of word 10h. If it is 0, firmware is done updating\n\t * 10h-12h. Checksum may need to be fixed.\n\t */\n\tret_val = nvm->ops.read(hw, 0x10, 1, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!(data & 0x10)) {\n\t\t/* Read 0x23 and check bit 15. This bit is a 1\n\t\t * when the checksum has already been fixed. If\n\t\t * the checksum is still wrong and this bit is a\n\t\t * 1, we need to return bad checksum. Otherwise,\n\t\t * we need to set this bit to a 1 and update the\n\t\t * checksum.\n\t\t */\n\t\tret_val = nvm->ops.read(hw, 0x23, 1, &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (!(data & 0x8000)) {\n\t\t\tdata |= 0x8000;\n\t\t\tret_val = nvm->ops.write(hw, 0x23, 1, &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t\tret_val = nvm->ops.update(hw);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n\n/**\n * e1000_read_mac_addr_82571 - Read device MAC address\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_read_mac_addr_82571\");\n\n\tif (hw->mac.type == e1000_82571) {\n\t\ts32 ret_val;\n\n\t\t/* If there's an alternate MAC address place it in RAR0\n\t\t * so that it will override the Si installed default perm\n\t\t * address.\n\t\t */\n\t\tret_val = e1000_check_alt_mac_addr_generic(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\treturn e1000_read_mac_addr_generic(hw);\n}\n\n/**\n * e1000_power_down_phy_copper_82571 - Remove link during PHY power down\n * @hw: pointer to the HW structure\n *\n * In the case of a PHY power down to save power, or to turn off link during a\n * driver unload, or wake on lan is not enabled, remove the link.\n **/\nSTATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tstruct e1000_mac_info *mac = &hw->mac;\n\n\tif (!phy->ops.check_reset_block)\n\t\treturn;\n\n\t/* If the management interface is not enabled, then power down */\n\tif (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))\n\t\te1000_power_down_phy_copper(hw);\n\n\treturn;\n}\n\n/**\n * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters\n * @hw: pointer to the HW structure\n *\n * Clears the hardware counters by reading the counter registers.\n **/\nSTATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_clear_hw_cntrs_82571\");\n\n\te1000_clear_hw_cntrs_base_generic(hw);\n\n\tE1000_READ_REG(hw, E1000_PRC64);\n\tE1000_READ_REG(hw, E1000_PRC127);\n\tE1000_READ_REG(hw, E1000_PRC255);\n\tE1000_READ_REG(hw, E1000_PRC511);\n\tE1000_READ_REG(hw, E1000_PRC1023);\n\tE1000_READ_REG(hw, E1000_PRC1522);\n\tE1000_READ_REG(hw, E1000_PTC64);\n\tE1000_READ_REG(hw, E1000_PTC127);\n\tE1000_READ_REG(hw, E1000_PTC255);\n\tE1000_READ_REG(hw, E1000_PTC511);\n\tE1000_READ_REG(hw, E1000_PTC1023);\n\tE1000_READ_REG(hw, E1000_PTC1522);\n\n\tE1000_READ_REG(hw, E1000_ALGNERRC);\n\tE1000_READ_REG(hw, E1000_RXERRC);\n\tE1000_READ_REG(hw, E1000_TNCRS);\n\tE1000_READ_REG(hw, E1000_CEXTERR);\n\tE1000_READ_REG(hw, E1000_TSCTC);\n\tE1000_READ_REG(hw, E1000_TSCTFC);\n\n\tE1000_READ_REG(hw, E1000_MGTPRC);\n\tE1000_READ_REG(hw, E1000_MGTPDC);\n\tE1000_READ_REG(hw, E1000_MGTPTC);\n\n\tE1000_READ_REG(hw, E1000_IAC);\n\tE1000_READ_REG(hw, E1000_ICRXOC);\n\n\tE1000_READ_REG(hw, E1000_ICRXPTC);\n\tE1000_READ_REG(hw, E1000_ICRXATC);\n\tE1000_READ_REG(hw, E1000_ICTXPTC);\n\tE1000_READ_REG(hw, E1000_ICTXATC);\n\tE1000_READ_REG(hw, E1000_ICTXQEC);\n\tE1000_READ_REG(hw, E1000_ICTXQMTC);\n\tE1000_READ_REG(hw, E1000_ICRXDMTC);\n}\n" }, { "path": "drivers/net/e1000/base/e1000_82571.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_82571_H_\n#define _E1000_82571_H_\n\n#define ID_LED_RESERVED_F746\t0xF746\n#define ID_LED_DEFAULT_82573\t((ID_LED_DEF1_DEF2 << 12) | \\\n\t\t\t\t (ID_LED_OFF1_ON2 << 8) | \\\n\t\t\t\t (ID_LED_DEF1_DEF2 << 4) | \\\n\t\t\t\t (ID_LED_DEF1_DEF2))\n\n#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX\t0x08000000\n#define AN_RETRY_COUNT\t\t5 /* Autoneg Retry Count value */\n\n/* Intr Throttling - RW */\n#define E1000_EITR_82574(_n)\t(0x000E8 + (0x4 * (_n)))\n\n#define E1000_EIAC_82574\t0x000DC /* Ext. Interrupt Auto Clear - RW */\n#define E1000_EIAC_MASK_82574\t0x01F00000\n\n#define E1000_IVAR_INT_ALLOC_VALID\t0x8\n\n/* Manageability Operation Mode mask */\n#define E1000_NVM_INIT_CTRL2_MNGM\t0x6000\n\n#define E1000_BASE1000T_STATUS\t\t10\n#define E1000_IDLE_ERROR_COUNT_MASK\t0xFF\n#define E1000_RECEIVE_ERROR_COUNTER\t21\n#define E1000_RECEIVE_ERROR_MAX\t\t0xFFFF\nbool e1000_check_phy_82574(struct e1000_hw *hw);\nbool e1000_get_laa_state_82571(struct e1000_hw *hw);\nvoid e1000_set_laa_state_82571(struct e1000_hw *hw, bool state);\n\n#endif\n" }, { "path": "drivers/net/e1000/base/e1000_82575.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n/*\n * 82575EB Gigabit Network Connection\n * 82575EB Gigabit Backplane Connection\n * 82575GB Gigabit Network Connection\n * 82576 Gigabit Network Connection\n * 82576 Quad Port Gigabit Mezzanine Adapter\n * 82580 Gigabit Network Connection\n * I350 Gigabit Network Connection\n */\n\n#include \"e1000_api.h\"\n#include \"e1000_i210.h\"\n\nSTATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw);\nSTATIC void e1000_release_phy_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);\nSTATIC void e1000_release_nvm_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);\nSTATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\t u16 *duplex);\nSTATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 *data);\nSTATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw);\nSTATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,\n\t\t\t\t u32 offset, u16 *data);\nSTATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,\n\t\t\t\t u32 offset, u16 data);\nSTATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,\n\t\t\t\t\t bool active);\nSTATIC s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,\n\t\t\t\t\t bool active);\nSTATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,\n\t\t\t\t\t bool active);\nSTATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);\nSTATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,\n\t\t\t\t\t u32 offset, u16 data);\nSTATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);\nSTATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,\n\t\t\t\t\t\t u16 *speed, u16 *duplex);\nSTATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw);\nSTATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);\nSTATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);\nSTATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw);\nSTATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);\nSTATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);\nSTATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);\nSTATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);\nSTATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);\nSTATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);\nSTATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);\nSTATIC s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,\n\t\t\t\t\t\t u16 offset);\nSTATIC s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,\n\t\t\t\t\t\t u16 offset);\nSTATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);\nSTATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);\nSTATIC void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);\nSTATIC void e1000_clear_vfta_i350(struct e1000_hw *hw);\n\nSTATIC void e1000_i2c_start(struct e1000_hw *hw);\nSTATIC void e1000_i2c_stop(struct e1000_hw *hw);\nSTATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);\nSTATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);\nSTATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw);\nSTATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);\nSTATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);\nSTATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);\nSTATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);\nSTATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);\nSTATIC bool e1000_get_i2c_data(u32 *i2cctl);\n\nSTATIC const u16 e1000_82580_rxpbs_table[] = {\n\t36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };\n#define E1000_82580_RXPBS_TABLE_SIZE \\\n\t(sizeof(e1000_82580_rxpbs_table) / \\\n\t sizeof(e1000_82580_rxpbs_table[0]))\n\n\n/**\n * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO\n * @hw: pointer to the HW structure\n *\n * Called to determine if the I2C pins are being used for I2C or as an\n * external MDIO interface since the two options are mutually exclusive.\n **/\nSTATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)\n{\n\tu32 reg = 0;\n\tbool ext_mdio = false;\n\n\tDEBUGFUNC(\"e1000_sgmii_uses_mdio_82575\");\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82575:\n\tcase e1000_82576:\n\t\treg = E1000_READ_REG(hw, E1000_MDIC);\n\t\text_mdio = !!(reg & E1000_MDIC_DEST);\n\t\tbreak;\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\treg = E1000_READ_REG(hw, E1000_MDICNFG);\n\t\text_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ext_mdio;\n}\n\n/**\n * e1000_init_phy_params_82575 - Init PHY func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 ctrl_ext;\n\n\tDEBUGFUNC(\"e1000_init_phy_params_82575\");\n\n\tphy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;\n\tphy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;\n\n\tif (hw->phy.media_type != e1000_media_type_copper) {\n\t\tphy->type = e1000_phy_none;\n\t\tgoto out;\n\t}\n\n\tphy->ops.power_up = e1000_power_up_phy_copper;\n\tphy->ops.power_down = e1000_power_down_phy_copper_82575;\n\n\tphy->autoneg_mask\t= AUTONEG_ADVERTISE_SPEED_DEFAULT;\n\tphy->reset_delay_us\t= 100;\n\n\tphy->ops.acquire\t= e1000_acquire_phy_82575;\n\tphy->ops.check_reset_block = e1000_check_reset_block_generic;\n\tphy->ops.commit\t\t= e1000_phy_sw_reset_generic;\n\tphy->ops.get_cfg_done\t= e1000_get_cfg_done_82575;\n\tphy->ops.release\t= e1000_release_phy_82575;\n\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\n\tif (e1000_sgmii_active_82575(hw)) {\n\t\tphy->ops.reset = e1000_phy_hw_reset_sgmii_82575;\n\t\tctrl_ext |= E1000_CTRL_I2C_ENA;\n\t} else {\n\t\tphy->ops.reset = e1000_phy_hw_reset_generic;\n\t\tctrl_ext &= ~E1000_CTRL_I2C_ENA;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\te1000_reset_mdicnfg_82580(hw);\n\n\tif (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {\n\t\tphy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;\n\t\tphy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;\n\t} else {\n\t\tswitch (hw->mac.type) {\n\t\tcase e1000_82580:\n\t\tcase e1000_i350:\n\t\tcase e1000_i354:\n\t\t\tphy->ops.read_reg = e1000_read_phy_reg_82580;\n\t\t\tphy->ops.write_reg = e1000_write_phy_reg_82580;\n\t\t\tbreak;\n\t\tcase e1000_i210:\n\t\tcase e1000_i211:\n\t\t\tphy->ops.read_reg = e1000_read_phy_reg_gs40g;\n\t\t\tphy->ops.write_reg = e1000_write_phy_reg_gs40g;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tphy->ops.read_reg = e1000_read_phy_reg_igp;\n\t\t\tphy->ops.write_reg = e1000_write_phy_reg_igp;\n\t\t}\n\t}\n\n\t/* Set phy->phy_addr and phy->id. */\n\tret_val = e1000_get_phy_id_82575(hw);\n\n\t/* Verify phy id and set remaining function pointers */\n\tswitch (phy->id) {\n\tcase M88E1543_E_PHY_ID:\n\tcase M88E1512_E_PHY_ID:\n\tcase I347AT4_E_PHY_ID:\n\tcase M88E1112_E_PHY_ID:\n\tcase M88E1340M_E_PHY_ID:\n\tcase M88E1111_I_PHY_ID:\n\t\tphy->type\t\t= e1000_phy_m88;\n\t\tphy->ops.check_polarity\t= e1000_check_polarity_m88;\n\t\tphy->ops.get_info\t= e1000_get_phy_info_m88;\n\t\tif (phy->id == I347AT4_E_PHY_ID ||\n\t\t phy->id == M88E1112_E_PHY_ID ||\n\t\t phy->id == M88E1340M_E_PHY_ID)\n\t\t\tphy->ops.get_cable_length =\n\t\t\t\t\t e1000_get_cable_length_m88_gen2;\n\t\telse if (phy->id == M88E1543_E_PHY_ID ||\n\t\t\t phy->id == M88E1512_E_PHY_ID)\n\t\t\tphy->ops.get_cable_length =\n\t\t\t\t\t e1000_get_cable_length_m88_gen2;\n\t\telse\n\t\t\tphy->ops.get_cable_length = e1000_get_cable_length_m88;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;\n\t\t/* Check if this PHY is confgured for media swap. */\n\t\tif (phy->id == M88E1112_E_PHY_ID) {\n\t\t\tu16 data;\n\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t E1000_M88E1112_PAGE_ADDR,\n\t\t\t\t\t\t 2);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t E1000_M88E1112_MAC_CTRL_1,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tdata = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>\n\t\t\t E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;\n\t\t\tif (data == E1000_M88E1112_AUTO_COPPER_SGMII ||\n\t\t\t data == E1000_M88E1112_AUTO_COPPER_BASEX)\n\t\t\t\thw->mac.ops.check_for_link =\n\t\t\t\t\t\te1000_check_for_link_media_swap;\n\t\t}\n\t\tif (phy->id == M88E1512_E_PHY_ID) {\n\t\t\tret_val = e1000_initialize_M88E1512_phy(hw);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t}\n\t\tbreak;\n\tcase IGP03E1000_E_PHY_ID:\n\tcase IGP04E1000_E_PHY_ID:\n\t\tphy->type = e1000_phy_igp_3;\n\t\tphy->ops.check_polarity = e1000_check_polarity_igp;\n\t\tphy->ops.get_info = e1000_get_phy_info_igp;\n\t\tphy->ops.get_cable_length = e1000_get_cable_length_igp_2;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;\n\t\tphy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;\n\t\tphy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;\n\t\tbreak;\n\tcase I82580_I_PHY_ID:\n\tcase I350_I_PHY_ID:\n\t\tphy->type = e1000_phy_82580;\n\t\tphy->ops.check_polarity = e1000_check_polarity_82577;\n\t\tphy->ops.force_speed_duplex =\n\t\t\t\t\t e1000_phy_force_speed_duplex_82577;\n\t\tphy->ops.get_cable_length = e1000_get_cable_length_82577;\n\t\tphy->ops.get_info = e1000_get_phy_info_82577;\n\t\tphy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;\n\t\tphy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;\n\t\tbreak;\n\tcase I210_I_PHY_ID:\n\t\tphy->type\t\t= e1000_phy_i210;\n\t\tphy->ops.check_polarity\t= e1000_check_polarity_m88;\n\t\tphy->ops.get_info\t= e1000_get_phy_info_m88;\n\t\tphy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;\n\t\tphy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;\n\t\tphy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;\n\t\tbreak;\n\tdefault:\n\t\tret_val = -E1000_ERR_PHY;\n\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_nvm_params_82575 - Init NVM func ptrs.\n * @hw: pointer to the HW structure\n **/\ns32 e1000_init_nvm_params_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\tu16 size;\n\n\tDEBUGFUNC(\"e1000_init_nvm_params_82575\");\n\n\tsize = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>\n\t\t E1000_EECD_SIZE_EX_SHIFT);\n\t/*\n\t * Added to a constant, \"size\" becomes the left-shift value\n\t * for setting word_size.\n\t */\n\tsize += NVM_WORD_SIZE_BASE_SHIFT;\n\n\t/* Just in case size is out of range, cap it to the largest\n\t * EEPROM size supported\n\t */\n\tif (size > 15)\n\t\tsize = 15;\n\n\tnvm->word_size = 1 << size;\n\tif (hw->mac.type < e1000_i210) {\n\t\tnvm->opcode_bits = 8;\n\t\tnvm->delay_usec = 1;\n\n\t\tswitch (nvm->override) {\n\t\tcase e1000_nvm_override_spi_large:\n\t\t\tnvm->page_size = 32;\n\t\t\tnvm->address_bits = 16;\n\t\t\tbreak;\n\t\tcase e1000_nvm_override_spi_small:\n\t\t\tnvm->page_size = 8;\n\t\t\tnvm->address_bits = 8;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tnvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;\n\t\t\tnvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?\n\t\t\t\t\t 16 : 8;\n\t\t\tbreak;\n\t\t}\n\t\tif (nvm->word_size == (1 << 15))\n\t\t\tnvm->page_size = 128;\n\n\t\tnvm->type = e1000_nvm_eeprom_spi;\n\t} else {\n\t\tnvm->type = e1000_nvm_flash_hw;\n\t}\n\n\t/* Function Pointers */\n\tnvm->ops.acquire = e1000_acquire_nvm_82575;\n\tnvm->ops.release = e1000_release_nvm_82575;\n\tif (nvm->word_size < (1 << 15))\n\t\tnvm->ops.read = e1000_read_nvm_eerd;\n\telse\n\t\tnvm->ops.read = e1000_read_nvm_spi;\n\n\tnvm->ops.write = e1000_write_nvm_spi;\n\tnvm->ops.validate = e1000_validate_nvm_checksum_generic;\n\tnvm->ops.update = e1000_update_nvm_checksum_generic;\n\tnvm->ops.valid_led_default = e1000_valid_led_default_82575;\n\n\t/* override generic family function pointers for specific descendants */\n\tswitch (hw->mac.type) {\n\tcase e1000_82580:\n\t\tnvm->ops.validate = e1000_validate_nvm_checksum_82580;\n\t\tnvm->ops.update = e1000_update_nvm_checksum_82580;\n\t\tbreak;\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\tnvm->ops.validate = e1000_validate_nvm_checksum_i350;\n\t\tnvm->ops.update = e1000_update_nvm_checksum_i350;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_mac_params_82575 - Init MAC func ptrs.\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tstruct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;\n\n\tDEBUGFUNC(\"e1000_init_mac_params_82575\");\n\n\t/* Derives media type */\n\te1000_get_media_type_82575(hw);\n\t/* Set mta register count */\n\tmac->mta_reg_count = 128;\n\t/* Set uta register count */\n\tmac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;\n\t/* Set rar entry count */\n\tmac->rar_entry_count = E1000_RAR_ENTRIES_82575;\n\tif (mac->type == e1000_82576)\n\t\tmac->rar_entry_count = E1000_RAR_ENTRIES_82576;\n\tif (mac->type == e1000_82580)\n\t\tmac->rar_entry_count = E1000_RAR_ENTRIES_82580;\n\tif (mac->type == e1000_i350 || mac->type == e1000_i354)\n\t\tmac->rar_entry_count = E1000_RAR_ENTRIES_I350;\n\n\t/* Enable EEE default settings for EEE supported devices */\n\tif (mac->type >= e1000_i350)\n\t\tdev_spec->eee_disable = false;\n\n\t/* Allow a single clear of the SW semaphore on I210 and newer */\n\tif (mac->type >= e1000_i210)\n\t\tdev_spec->clear_semaphore_once = true;\n\n\t/* Set if part includes ASF firmware */\n\tmac->asf_firmware_present = true;\n\t/* FWSM register */\n\tmac->has_fwsm = true;\n\t/* ARC supported; valid only if manageability features are enabled. */\n\tmac->arc_subsystem_valid =\n\t\t!!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);\n\n\t/* Function pointers */\n\n\t/* bus type/speed/width */\n\tmac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;\n\t/* reset */\n\tif (mac->type >= e1000_82580)\n\t\tmac->ops.reset_hw = e1000_reset_hw_82580;\n\telse\n\tmac->ops.reset_hw = e1000_reset_hw_82575;\n\t/* hw initialization */\n\tif ((mac->type == e1000_i210) || (mac->type == e1000_i211))\n\t\tmac->ops.init_hw = e1000_init_hw_i210;\n\telse\n\tmac->ops.init_hw = e1000_init_hw_82575;\n\t/* link setup */\n\tmac->ops.setup_link = e1000_setup_link_generic;\n\t/* physical interface link setup */\n\tmac->ops.setup_physical_interface =\n\t\t(hw->phy.media_type == e1000_media_type_copper)\n\t\t? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;\n\t/* physical interface shutdown */\n\tmac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;\n\t/* physical interface power up */\n\tmac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;\n\t/* check for link */\n\tmac->ops.check_for_link = e1000_check_for_link_82575;\n\t/* read mac address */\n\tmac->ops.read_mac_addr = e1000_read_mac_addr_82575;\n\t/* configure collision distance */\n\tmac->ops.config_collision_dist = e1000_config_collision_dist_82575;\n\t/* multicast address update */\n\tmac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;\n\tif (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {\n\t\t/* writing VFTA */\n\t\tmac->ops.write_vfta = e1000_write_vfta_i350;\n\t\t/* clearing VFTA */\n\t\tmac->ops.clear_vfta = e1000_clear_vfta_i350;\n\t} else {\n\t\t/* writing VFTA */\n\t\tmac->ops.write_vfta = e1000_write_vfta_generic;\n\t\t/* clearing VFTA */\n\t\tmac->ops.clear_vfta = e1000_clear_vfta_generic;\n\t}\n\tif (hw->mac.type >= e1000_82580)\n\t\tmac->ops.validate_mdi_setting =\n\t\t\t\te1000_validate_mdi_setting_crossover_generic;\n\t/* ID LED init */\n\tmac->ops.id_led_init = e1000_id_led_init_generic;\n\t/* blink LED */\n\tmac->ops.blink_led = e1000_blink_led_generic;\n\t/* setup LED */\n\tmac->ops.setup_led = e1000_setup_led_generic;\n\t/* cleanup LED */\n\tmac->ops.cleanup_led = e1000_cleanup_led_generic;\n\t/* turn on/off LED */\n\tmac->ops.led_on = e1000_led_on_generic;\n\tmac->ops.led_off = e1000_led_off_generic;\n\t/* clear hardware counters */\n\tmac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;\n\t/* link info */\n\tmac->ops.get_link_up_info = e1000_get_link_up_info_82575;\n\t/* acquire SW_FW sync */\n\tmac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;\n\tmac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;\n\tif (mac->type >= e1000_i210) {\n\t\tmac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;\n\t\tmac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;\n\t}\n\n\t/* set lan id for port to determine which phy lock to use */\n\thw->mac.ops.set_lan_id(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_function_pointers_82575 - Init func ptrs.\n * @hw: pointer to the HW structure\n *\n * Called to initialize all function pointers and parameters.\n **/\nvoid e1000_init_function_pointers_82575(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_function_pointers_82575\");\n\n\thw->mac.ops.init_params = e1000_init_mac_params_82575;\n\thw->nvm.ops.init_params = e1000_init_nvm_params_82575;\n\thw->phy.ops.init_params = e1000_init_phy_params_82575;\n\thw->mbx.ops.init_params = e1000_init_mbx_params_pf;\n}\n\n/**\n * e1000_acquire_phy_82575 - Acquire rights to access PHY\n * @hw: pointer to the HW structure\n *\n * Acquire access rights to the correct PHY.\n **/\nSTATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw)\n{\n\tu16 mask = E1000_SWFW_PHY0_SM;\n\n\tDEBUGFUNC(\"e1000_acquire_phy_82575\");\n\n\tif (hw->bus.func == E1000_FUNC_1)\n\t\tmask = E1000_SWFW_PHY1_SM;\n\telse if (hw->bus.func == E1000_FUNC_2)\n\t\tmask = E1000_SWFW_PHY2_SM;\n\telse if (hw->bus.func == E1000_FUNC_3)\n\t\tmask = E1000_SWFW_PHY3_SM;\n\n\treturn hw->mac.ops.acquire_swfw_sync(hw, mask);\n}\n\n/**\n * e1000_release_phy_82575 - Release rights to access PHY\n * @hw: pointer to the HW structure\n *\n * A wrapper to release access rights to the correct PHY.\n **/\nSTATIC void e1000_release_phy_82575(struct e1000_hw *hw)\n{\n\tu16 mask = E1000_SWFW_PHY0_SM;\n\n\tDEBUGFUNC(\"e1000_release_phy_82575\");\n\n\tif (hw->bus.func == E1000_FUNC_1)\n\t\tmask = E1000_SWFW_PHY1_SM;\n\telse if (hw->bus.func == E1000_FUNC_2)\n\t\tmask = E1000_SWFW_PHY2_SM;\n\telse if (hw->bus.func == E1000_FUNC_3)\n\t\tmask = E1000_SWFW_PHY3_SM;\n\n\thw->mac.ops.release_swfw_sync(hw, mask);\n}\n\n/**\n * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the PHY register at offset using the serial gigabit media independent\n * interface and stores the retrieved information in data.\n **/\nSTATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 *data)\n{\n\ts32 ret_val = -E1000_ERR_PARAM;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_sgmii_82575\");\n\n\tif (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {\n\t\tDEBUGOUT1(\"PHY Address %u is out of range\\n\", offset);\n\t\tgoto out;\n\t}\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_read_phy_reg_i2c(hw, offset, data);\n\n\thw->phy.ops.release(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Writes the data to PHY register at the offset using the serial gigabit\n * media independent interface.\n **/\nSTATIC s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 data)\n{\n\ts32 ret_val = -E1000_ERR_PARAM;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_sgmii_82575\");\n\n\tif (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {\n\t\tDEBUGOUT1(\"PHY Address %d is out of range\\n\", offset);\n\t\tgoto out;\n\t}\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_write_phy_reg_i2c(hw, offset, data);\n\n\thw->phy.ops.release(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_get_phy_id_82575 - Retrieve PHY addr and id\n * @hw: pointer to the HW structure\n *\n * Retrieves the PHY address and ID for both PHY's which do and do not use\n * sgmi interface.\n **/\nSTATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 phy_id;\n\tu32 ctrl_ext;\n\tu32 mdic;\n\n\tDEBUGFUNC(\"e1000_get_phy_id_82575\");\n\n\t/* some i354 devices need an extra read for phy id */\n\tif (hw->mac.type == e1000_i354)\n\t\te1000_get_phy_id(hw);\n\n\t/*\n\t * For SGMII PHYs, we try the list of possible addresses until\n\t * we find one that works. For non-SGMII PHYs\n\t * (e.g. integrated copper PHYs), an address of 1 should\n\t * work. The result of this function should mean phy->phy_addr\n\t * and phy->id are set correctly.\n\t */\n\tif (!e1000_sgmii_active_82575(hw)) {\n\t\tphy->addr = 1;\n\t\tret_val = e1000_get_phy_id(hw);\n\t\tgoto out;\n\t}\n\n\tif (e1000_sgmii_uses_mdio_82575(hw)) {\n\t\tswitch (hw->mac.type) {\n\t\tcase e1000_82575:\n\t\tcase e1000_82576:\n\t\t\tmdic = E1000_READ_REG(hw, E1000_MDIC);\n\t\t\tmdic &= E1000_MDIC_PHY_MASK;\n\t\t\tphy->addr = mdic >> E1000_MDIC_PHY_SHIFT;\n\t\t\tbreak;\n\t\tcase e1000_82580:\n\t\tcase e1000_i350:\n\t\tcase e1000_i354:\n\t\tcase e1000_i210:\n\t\tcase e1000_i211:\n\t\t\tmdic = E1000_READ_REG(hw, E1000_MDICNFG);\n\t\t\tmdic &= E1000_MDICNFG_PHY_MASK;\n\t\t\tphy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\t\tgoto out;\n\t\t\tbreak;\n\t\t}\n\t\tret_val = e1000_get_phy_id(hw);\n\t\tgoto out;\n\t}\n\n\t/* Power on sgmii phy if it is disabled */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT,\n\t\t\tctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);\n\tE1000_WRITE_FLUSH(hw);\n\tmsec_delay(300);\n\n\t/*\n\t * The address field in the I2CCMD register is 3 bits and 0 is invalid.\n\t * Therefore, we need to test 1-7\n\t */\n\tfor (phy->addr = 1; phy->addr < 8; phy->addr++) {\n\t\tret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);\n\t\tif (ret_val == E1000_SUCCESS) {\n\t\t\tDEBUGOUT2(\"Vendor ID 0x%08X read at address %u\\n\",\n\t\t\t\t phy_id, phy->addr);\n\t\t\t/*\n\t\t\t * At the time of this writing, The M88 part is\n\t\t\t * the only supported SGMII PHY product.\n\t\t\t */\n\t\t\tif (phy_id == M88_VENDOR)\n\t\t\t\tbreak;\n\t\t} else {\n\t\t\tDEBUGOUT1(\"PHY address %u was unreadable\\n\",\n\t\t\t\t phy->addr);\n\t\t}\n\t}\n\n\t/* A valid PHY type couldn't be found. */\n\tif (phy->addr == 8) {\n\t\tphy->addr = 0;\n\t\tret_val = -E1000_ERR_PHY;\n\t} else {\n\t\tret_val = e1000_get_phy_id(hw);\n\t}\n\n\t/* restore previous sfp cage power state */\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset\n * @hw: pointer to the HW structure\n *\n * Resets the PHY using the serial gigabit media independent interface.\n **/\nSTATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tstruct e1000_phy_info *phy = &hw->phy;\n\n\tDEBUGFUNC(\"e1000_phy_hw_reset_sgmii_82575\");\n\n\t/*\n\t * This isn't a true \"hard\" reset, but is the only reset\n\t * available to us at this time.\n\t */\n\n\tDEBUGOUT(\"Soft resetting SGMII attached PHY...\\n\");\n\n\tif (!(hw->phy.ops.write_reg))\n\t\tgoto out;\n\n\t/*\n\t * SFP documentation requires the following to configure the SPF module\n\t * to work on SGMII. No further documentation is given.\n\t */\n\tret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = hw->phy.ops.commit(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (phy->id == M88E1512_E_PHY_ID)\n\t\tret_val = e1000_initialize_M88E1512_phy(hw);\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state\n * @hw: pointer to the HW structure\n * @active: true to enable LPLU, false to disable\n *\n * Sets the LPLU D0 state according to the active flag. When\n * activating LPLU this function also disables smart speed\n * and vice versa. LPLU will not be activated unless the\n * device autonegotiation advertisement meets standards of\n * either 10 or 10/100 or 10/100/1000 at all duplexes.\n * This is a function pointer entry point only called by\n * PHY setup routines.\n **/\nSTATIC s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_set_d0_lplu_state_82575\");\n\n\tif (!(hw->phy.ops.read_reg))\n\t\tgoto out;\n\n\tret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (active) {\n\t\tdata |= IGP02E1000_PM_D0_LPLU;\n\t\tret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,\n\t\t\t\t\t data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n\t\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t &data);\n\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\tret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t} else {\n\t\tdata &= ~IGP02E1000_PM_D0_LPLU;\n\t\tret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,\n\t\t\t\t\t data);\n\t\t/*\n\t\t * LPLU and SmartSpeed are mutually exclusive. LPLU is used\n\t\t * during Dx states where the power conservation is most\n\t\t * important. During driver activity we should enable\n\t\t * SmartSpeed, so performance is maintained.\n\t\t */\n\t\tif (phy->smart_speed == e1000_smart_speed_on) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tdata |= IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t} else if (phy->smart_speed == e1000_smart_speed_off) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state\n * @hw: pointer to the HW structure\n * @active: true to enable LPLU, false to disable\n *\n * Sets the LPLU D0 state according to the active flag. When\n * activating LPLU this function also disables smart speed\n * and vice versa. LPLU will not be activated unless the\n * device autonegotiation advertisement meets standards of\n * either 10 or 10/100 or 10/100/1000 at all duplexes.\n * This is a function pointer entry point only called by\n * PHY setup routines.\n **/\nSTATIC s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 data;\n\n\tDEBUGFUNC(\"e1000_set_d0_lplu_state_82580\");\n\n\tdata = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);\n\n\tif (active) {\n\t\tdata |= E1000_82580_PM_D0_LPLU;\n\n\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n\t\tdata &= ~E1000_82580_PM_SPD;\n\t} else {\n\t\tdata &= ~E1000_82580_PM_D0_LPLU;\n\n\t\t/*\n\t\t * LPLU and SmartSpeed are mutually exclusive. LPLU is used\n\t\t * during Dx states where the power conservation is most\n\t\t * important. During driver activity we should enable\n\t\t * SmartSpeed, so performance is maintained.\n\t\t */\n\t\tif (phy->smart_speed == e1000_smart_speed_on)\n\t\t\tdata |= E1000_82580_PM_SPD;\n\t\telse if (phy->smart_speed == e1000_smart_speed_off)\n\t\t\tdata &= ~E1000_82580_PM_SPD;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);\n\treturn ret_val;\n}\n\n/**\n * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3\n * @hw: pointer to the HW structure\n * @active: boolean used to enable/disable lplu\n *\n * Success returns 0, Failure returns 1\n *\n * The low power link up (lplu) state is set to the power management level D3\n * and SmartSpeed is disabled when active is true, else clear lplu for D3\n * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU\n * is used during Dx states where the power conservation is most important.\n * During driver activity, SmartSpeed should be enabled so performance is\n * maintained.\n **/\ns32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 data;\n\n\tDEBUGFUNC(\"e1000_set_d3_lplu_state_82580\");\n\n\tdata = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);\n\n\tif (!active) {\n\t\tdata &= ~E1000_82580_PM_D3_LPLU;\n\t\t/*\n\t\t * LPLU and SmartSpeed are mutually exclusive. LPLU is used\n\t\t * during Dx states where the power conservation is most\n\t\t * important. During driver activity we should enable\n\t\t * SmartSpeed, so performance is maintained.\n\t\t */\n\t\tif (phy->smart_speed == e1000_smart_speed_on)\n\t\t\tdata |= E1000_82580_PM_SPD;\n\t\telse if (phy->smart_speed == e1000_smart_speed_off)\n\t\t\tdata &= ~E1000_82580_PM_SPD;\n\t} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||\n\t\t (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||\n\t\t (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {\n\t\tdata |= E1000_82580_PM_D3_LPLU;\n\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n\t\tdata &= ~E1000_82580_PM_SPD;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);\n\treturn ret_val;\n}\n\n/**\n * e1000_acquire_nvm_82575 - Request for access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Acquire the necessary semaphores for exclusive access to the EEPROM.\n * Set the EEPROM access request bit and wait for EEPROM access grant bit.\n * Return successful if access grant bit set, else clear the request for\n * EEPROM access and return -E1000_ERR_NVM (-1).\n **/\nSTATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_acquire_nvm_82575\");\n\n\tret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/*\n\t * Check if there is some access\n\t * error this access may hook on\n\t */\n\tif (hw->mac.type == e1000_i350) {\n\t\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\t\tif (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |\n\t\t E1000_EECD_TIMEOUT)) {\n\t\t\t/* Clear all access error flags */\n\t\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd |\n\t\t\t\t\tE1000_EECD_ERROR_CLR);\n\t\t\tDEBUGOUT(\"Nvm bit banging access error detected and cleared.\\n\");\n\t\t}\n\t}\n\tif (hw->mac.type == e1000_82580) {\n\t\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\t\tif (eecd & E1000_EECD_BLOCKED) {\n\t\t\t/* Clear access error flag */\n\t\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd |\n\t\t\t\t\tE1000_EECD_BLOCKED);\n\t\t\tDEBUGOUT(\"Nvm bit banging access error detected and cleared.\\n\");\n\t\t}\n\t}\n\n\n\tret_val = e1000_acquire_nvm_generic(hw);\n\tif (ret_val)\n\t\te1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_release_nvm_82575 - Release exclusive access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Stop any current commands to the EEPROM and clear the EEPROM request bit,\n * then release the semaphores acquired.\n **/\nSTATIC void e1000_release_nvm_82575(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_release_nvm_82575\");\n\n\te1000_release_nvm_generic(hw);\n\n\te1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);\n}\n\n/**\n * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore\n * @hw: pointer to the HW structure\n * @mask: specifies which semaphore to acquire\n *\n * Acquire the SW/FW semaphore to access the PHY or NVM. The mask\n * will also specify which port we're acquiring the lock for.\n **/\nSTATIC s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)\n{\n\tu32 swfw_sync;\n\tu32 swmask = mask;\n\tu32 fwmask = mask << 16;\n\ts32 ret_val = E1000_SUCCESS;\n\ts32 i = 0, timeout = 200; /* FIXME: find real value to use here */\n\n\tDEBUGFUNC(\"e1000_acquire_swfw_sync_82575\");\n\n\twhile (i < timeout) {\n\t\tif (e1000_get_hw_semaphore_generic(hw)) {\n\t\t\tret_val = -E1000_ERR_SWFW_SYNC;\n\t\t\tgoto out;\n\t\t}\n\n\t\tswfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);\n\t\tif (!(swfw_sync & (fwmask | swmask)))\n\t\t\tbreak;\n\n\t\t/*\n\t\t * Firmware currently using resource (fwmask)\n\t\t * or other software thread using resource (swmask)\n\t\t */\n\t\te1000_put_hw_semaphore_generic(hw);\n\t\tmsec_delay_irq(5);\n\t\ti++;\n\t}\n\n\tif (i == timeout) {\n\t\tDEBUGOUT(\"Driver can't access resource, SW_FW_SYNC timeout.\\n\");\n\t\tret_val = -E1000_ERR_SWFW_SYNC;\n\t\tgoto out;\n\t}\n\n\tswfw_sync |= swmask;\n\tE1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);\n\n\te1000_put_hw_semaphore_generic(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_release_swfw_sync_82575 - Release SW/FW semaphore\n * @hw: pointer to the HW structure\n * @mask: specifies which semaphore to acquire\n *\n * Release the SW/FW semaphore used to access the PHY or NVM. The mask\n * will also specify which port we're releasing the lock for.\n **/\nSTATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)\n{\n\tu32 swfw_sync;\n\n\tDEBUGFUNC(\"e1000_release_swfw_sync_82575\");\n\n\twhile (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)\n\t\t; /* Empty */\n\n\tswfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);\n\tswfw_sync &= ~mask;\n\tE1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);\n\n\te1000_put_hw_semaphore_generic(hw);\n}\n\n/**\n * e1000_get_cfg_done_82575 - Read config done bit\n * @hw: pointer to the HW structure\n *\n * Read the management control register for the config done bit for\n * completion status. NOTE: silicon which is EEPROM-less will fail trying\n * to read the config done bit, so an error is *ONLY* logged and returns\n * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon\n * would not be able to be reset or change link.\n **/\nSTATIC s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)\n{\n\ts32 timeout = PHY_CFG_TIMEOUT;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 mask = E1000_NVM_CFG_DONE_PORT_0;\n\n\tDEBUGFUNC(\"e1000_get_cfg_done_82575\");\n\n\tif (hw->bus.func == E1000_FUNC_1)\n\t\tmask = E1000_NVM_CFG_DONE_PORT_1;\n\telse if (hw->bus.func == E1000_FUNC_2)\n\t\tmask = E1000_NVM_CFG_DONE_PORT_2;\n\telse if (hw->bus.func == E1000_FUNC_3)\n\t\tmask = E1000_NVM_CFG_DONE_PORT_3;\n\twhile (timeout) {\n\t\tif (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t\ttimeout--;\n\t}\n\tif (!timeout)\n\t\tDEBUGOUT(\"MNG configuration cycle has not completed.\\n\");\n\n\t/* If EEPROM is not marked present, init the PHY manually */\n\tif (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&\n\t (hw->phy.type == e1000_phy_igp_3))\n\t\te1000_phy_init_script_igp3(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_link_up_info_82575 - Get link speed/duplex info\n * @hw: pointer to the HW structure\n * @speed: stores the current speed\n * @duplex: stores the current duplex\n *\n * This is a wrapper function, if using the serial gigabit media independent\n * interface, use PCS to retrieve the link speed and duplex information.\n * Otherwise, use the generic function to get the link speed and duplex info.\n **/\nSTATIC s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\tu16 *duplex)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_get_link_up_info_82575\");\n\n\tif (hw->phy.media_type != e1000_media_type_copper)\n\t\tret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,\n\t\t\t\t\t\t\t duplex);\n\telse\n\t\tret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,\n\t\t\t\t\t\t\t\t duplex);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_link_82575 - Check for link\n * @hw: pointer to the HW structure\n *\n * If sgmii is enabled, then use the pcs register to determine link, otherwise\n * use the generic interface for determining link.\n **/\nSTATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 speed, duplex;\n\n\tDEBUGFUNC(\"e1000_check_for_link_82575\");\n\n\tif (hw->phy.media_type != e1000_media_type_copper) {\n\t\tret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,\n\t\t\t\t\t\t\t &duplex);\n\t\t/*\n\t\t * Use this flag to determine if link needs to be checked or\n\t\t * not. If we have link clear the flag so that we do not\n\t\t * continue to check for link.\n\t\t */\n\t\thw->mac.get_link_status = !hw->mac.serdes_has_link;\n\n\t\t/*\n\t\t * Configure Flow Control now that Auto-Neg has completed.\n\t\t * First, we need to restore the desired flow control\n\t\t * settings because we may have had to re-autoneg with a\n\t\t * different link partner.\n\t\t */\n\t\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\t\tif (ret_val)\n\t\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n\t} else {\n\t\tret_val = e1000_check_for_copper_link_generic(hw);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_link_media_swap - Check which M88E1112 interface linked\n * @hw: pointer to the HW structure\n *\n * Poll the M88E1112 interfaces to see which interface achieved link.\n */\nSTATIC s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\tu8 port = 0;\n\n\tDEBUGFUNC(\"e1000_check_for_link_media_swap\");\n\n\t/* Check the copper medium. */\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (data & E1000_M88E1112_STATUS_LINK)\n\t\tport = E1000_MEDIA_PORT_COPPER;\n\n\t/* Check the other medium. */\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* reset page to 0 */\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (data & E1000_M88E1112_STATUS_LINK)\n\t\tport = E1000_MEDIA_PORT_OTHER;\n\n\t/* Determine if a swap needs to happen. */\n\tif (port && (hw->dev_spec._82575.media_port != port)) {\n\t\thw->dev_spec._82575.media_port = port;\n\t\thw->dev_spec._82575.media_changed = true;\n\t} else {\n\t\tret_val = e1000_check_for_link_82575(hw);\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown\n * @hw: pointer to the HW structure\n **/\nSTATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)\n{\n\tu32 reg;\n\n\tDEBUGFUNC(\"e1000_power_up_serdes_link_82575\");\n\n\tif ((hw->phy.media_type != e1000_media_type_internal_serdes) &&\n\t !e1000_sgmii_active_82575(hw))\n\t\treturn;\n\n\t/* Enable PCS to turn on link */\n\treg = E1000_READ_REG(hw, E1000_PCS_CFG0);\n\treg |= E1000_PCS_CFG_PCS_EN;\n\tE1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);\n\n\t/* Power up the laser */\n\treg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\treg &= ~E1000_CTRL_EXT_SDP3_DATA;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);\n\n\t/* flush the write to verify completion */\n\tE1000_WRITE_FLUSH(hw);\n\tmsec_delay(1);\n}\n\n/**\n * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex\n * @hw: pointer to the HW structure\n * @speed: stores the current speed\n * @duplex: stores the current duplex\n *\n * Using the physical coding sub-layer (PCS), retrieve the current speed and\n * duplex, then store the values in the pointers provided.\n **/\nSTATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,\n\t\t\t\t\t\tu16 *speed, u16 *duplex)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 pcs;\n\tu32 status;\n\n\tDEBUGFUNC(\"e1000_get_pcs_speed_and_duplex_82575\");\n\n\t/*\n\t * Read the PCS Status register for link state. For non-copper mode,\n\t * the status register is not accurate. The PCS status register is\n\t * used instead.\n\t */\n\tpcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);\n\n\t/*\n\t * The link up bit determines when link is up on autoneg.\n\t */\n\tif (pcs & E1000_PCS_LSTS_LINK_OK) {\n\t\tmac->serdes_has_link = true;\n\n\t\t/* Detect and store PCS speed */\n\t\tif (pcs & E1000_PCS_LSTS_SPEED_1000)\n\t\t\t*speed = SPEED_1000;\n\t\telse if (pcs & E1000_PCS_LSTS_SPEED_100)\n\t\t\t*speed = SPEED_100;\n\t\telse\n\t\t\t*speed = SPEED_10;\n\n\t\t/* Detect and store PCS duplex */\n\t\tif (pcs & E1000_PCS_LSTS_DUPLEX_FULL)\n\t\t\t*duplex = FULL_DUPLEX;\n\t\telse\n\t\t\t*duplex = HALF_DUPLEX;\n\n\t\t/* Check if it is an I354 2.5Gb backplane connection. */\n\t\tif (mac->type == e1000_i354) {\n\t\t\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\t\t\tif ((status & E1000_STATUS_2P5_SKU) &&\n\t\t\t !(status & E1000_STATUS_2P5_SKU_OVER)) {\n\t\t\t\t*speed = SPEED_2500;\n\t\t\t\t*duplex = FULL_DUPLEX;\n\t\t\t\tDEBUGOUT(\"2500 Mbs, \");\n\t\t\t\tDEBUGOUT(\"Full Duplex\\n\");\n\t\t\t}\n\t\t}\n\n\t} else {\n\t\tmac->serdes_has_link = false;\n\t\t*speed = 0;\n\t\t*duplex = 0;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_shutdown_serdes_link_82575 - Remove link during power down\n * @hw: pointer to the HW structure\n *\n * In the case of serdes shut down sfp and PCS on driver unload\n * when management pass thru is not enabled.\n **/\nvoid e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)\n{\n\tu32 reg;\n\n\tDEBUGFUNC(\"e1000_shutdown_serdes_link_82575\");\n\n\tif ((hw->phy.media_type != e1000_media_type_internal_serdes) &&\n\t !e1000_sgmii_active_82575(hw))\n\t\treturn;\n\n\tif (!e1000_enable_mng_pass_thru(hw)) {\n\t\t/* Disable PCS to turn off link */\n\t\treg = E1000_READ_REG(hw, E1000_PCS_CFG0);\n\t\treg &= ~E1000_PCS_CFG_PCS_EN;\n\t\tE1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);\n\n\t\t/* shutdown the laser */\n\t\treg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\treg |= E1000_CTRL_EXT_SDP3_DATA;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);\n\n\t\t/* flush the write to verify completion */\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tmsec_delay(1);\n\t}\n\n\treturn;\n}\n\n/**\n * e1000_reset_hw_82575 - Reset hardware\n * @hw: pointer to the HW structure\n *\n * This resets the hardware into a known state.\n **/\nSTATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_reset_hw_82575\");\n\n\t/*\n\t * Prevent the PCI-E bus from sticking if there is no TLP connection\n\t * on the last TLP read/write transaction when MAC is reset.\n\t */\n\tret_val = e1000_disable_pcie_master_generic(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"PCI-E Master disable polling has failed.\\n\");\n\n\t/* set the completion timeout for interface */\n\tret_val = e1000_set_pcie_completion_timeout(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"PCI-E Set completion timeout has failed.\\n\");\n\n\tDEBUGOUT(\"Masking off all interrupts\\n\");\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\n\tE1000_WRITE_REG(hw, E1000_RCTL, 0);\n\tE1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);\n\tE1000_WRITE_FLUSH(hw);\n\n\tmsec_delay(10);\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\tDEBUGOUT(\"Issuing a global reset to MAC\\n\");\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);\n\n\tret_val = e1000_get_auto_rd_done_generic(hw);\n\tif (ret_val) {\n\t\t/*\n\t\t * When auto config read does not complete, do not\n\t\t * return with an error. This can happen in situations\n\t\t * where there is no eeprom and prevents getting link.\n\t\t */\n\t\tDEBUGOUT(\"Auto Read Done did not complete\\n\");\n\t}\n\n\t/* If EEPROM is not present, run manual init scripts */\n\tif (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))\n\t\te1000_reset_init_script_82575(hw);\n\n\t/* Clear any pending interrupt events. */\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\tE1000_READ_REG(hw, E1000_ICR);\n\n\t/* Install any alternate MAC address into RAR0 */\n\tret_val = e1000_check_alt_mac_addr_generic(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_hw_82575 - Initialize hardware\n * @hw: pointer to the HW structure\n *\n * This inits the hardware readying it for operation.\n **/\ns32 e1000_init_hw_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val;\n\tu16 i, rar_count = mac->rar_entry_count;\n\n\tDEBUGFUNC(\"e1000_init_hw_82575\");\n\n\t/* Initialize identification LED */\n\tret_val = mac->ops.id_led_init(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error initializing identification LED\\n\");\n\t\t/* This is not fatal and we should not stop init due to this */\n\t}\n\n\t/* Disabling VLAN filtering */\n\tDEBUGOUT(\"Initializing the IEEE VLAN\\n\");\n\tmac->ops.clear_vfta(hw);\n\n\t/* Setup the receive address */\n\te1000_init_rx_addrs_generic(hw, rar_count);\n\n\t/* Zero out the Multicast HASH table */\n\tDEBUGOUT(\"Zeroing the MTA\\n\");\n\tfor (i = 0; i < mac->mta_reg_count; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);\n\n\t/* Zero out the Unicast HASH table */\n\tDEBUGOUT(\"Zeroing the UTA\\n\");\n\tfor (i = 0; i < mac->uta_reg_count; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);\n\n\t/* Setup link and flow control */\n\tret_val = mac->ops.setup_link(hw);\n\n\t/* Set the default MTU size */\n\thw->dev_spec._82575.mtu = 1500;\n\n\t/*\n\t * Clear all of the statistics registers (clear on read). It is\n\t * important that we do this after we have tried to establish link\n\t * because the symbol error count will increment wildly if there\n\t * is no link.\n\t */\n\te1000_clear_hw_cntrs_82575(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_copper_link_82575 - Configure copper link settings\n * @hw: pointer to the HW structure\n *\n * Configures the link for auto-neg or forced speed and duplex. Then we check\n * for link, once link is established calls to configure collision distance\n * and flow control are called.\n **/\nSTATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\tu32 phpm_reg;\n\n\tDEBUGFUNC(\"e1000_setup_copper_link_82575\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= E1000_CTRL_SLU;\n\tctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\t/* Clear Go Link Disconnect bit on supported devices */\n\tswitch (hw->mac.type) {\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\tphpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);\n\t\tphpm_reg &= ~E1000_82580_PM_GO_LINKD;\n\t\tE1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tret_val = e1000_setup_serdes_link_82575(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (e1000_sgmii_active_82575(hw)) {\n\t\t/* allow time for SFP cage time to power up phy */\n\t\tmsec_delay(300);\n\n\t\tret_val = hw->phy.ops.reset(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error resetting the PHY.\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\tswitch (hw->phy.type) {\n\tcase e1000_phy_i210:\n\tcase e1000_phy_m88:\n\t\tswitch (hw->phy.id) {\n\t\tcase I347AT4_E_PHY_ID:\n\t\tcase M88E1112_E_PHY_ID:\n\t\tcase M88E1340M_E_PHY_ID:\n\t\tcase M88E1543_E_PHY_ID:\n\t\tcase M88E1512_E_PHY_ID:\n\t\tcase I210_I_PHY_ID:\n\t\t\tret_val = e1000_copper_link_setup_m88_gen2(hw);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tret_val = e1000_copper_link_setup_m88(hw);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase e1000_phy_igp_3:\n\t\tret_val = e1000_copper_link_setup_igp(hw);\n\t\tbreak;\n\tcase e1000_phy_82580:\n\t\tret_val = e1000_copper_link_setup_82577(hw);\n\t\tbreak;\n\tdefault:\n\t\tret_val = -E1000_ERR_PHY;\n\t\tbreak;\n\t}\n\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_setup_copper_link_generic(hw);\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_serdes_link_82575 - Setup link for serdes\n * @hw: pointer to the HW structure\n *\n * Configure the physical coding sub-layer (PCS) link. The PCS link is\n * used on copper connections where the serialized gigabit media independent\n * interface (sgmii), or serdes fiber is being used. Configures the link\n * for auto-negotiation or forces speed/duplex.\n **/\nSTATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)\n{\n\tu32 ctrl_ext, ctrl_reg, reg, anadv_reg;\n\tbool pcs_autoneg;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_setup_serdes_link_82575\");\n\n\tif ((hw->phy.media_type != e1000_media_type_internal_serdes) &&\n\t !e1000_sgmii_active_82575(hw))\n\t\treturn ret_val;\n\n\t/*\n\t * On the 82575, SerDes loopback mode persists until it is\n\t * explicitly turned off or a power cycle is performed. A read to\n\t * the register does not indicate its status. Therefore, we ensure\n\t * loopback mode is disabled during initialization.\n\t */\n\tE1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);\n\n\t/* power on the sfp cage if present */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\n\tctrl_reg = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl_reg |= E1000_CTRL_SLU;\n\n\t/* set both sw defined pins on 82575/82576*/\n\tif (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)\n\t\tctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;\n\n\treg = E1000_READ_REG(hw, E1000_PCS_LCTL);\n\n\t/* default pcs_autoneg to the same setting as mac autoneg */\n\tpcs_autoneg = hw->mac.autoneg;\n\n\tswitch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {\n\tcase E1000_CTRL_EXT_LINK_MODE_SGMII:\n\t\t/* sgmii mode lets the phy handle forcing speed/duplex */\n\t\tpcs_autoneg = true;\n\t\t/* autoneg time out should be disabled for SGMII mode */\n\t\treg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);\n\t\tbreak;\n\tcase E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:\n\t\t/* disable PCS autoneg and support parallel detect only */\n\t\tpcs_autoneg = false;\n\t\t/* fall through to default case */\n\tdefault:\n\t\tif (hw->mac.type == e1000_82575 ||\n\t\t hw->mac.type == e1000_82576) {\n\t\t\tret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);\n\t\t\tif (ret_val) {\n\t\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\t\treturn ret_val;\n\t\t\t}\n\n\t\t\tif (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)\n\t\t\t\tpcs_autoneg = false;\n\t\t}\n\n\t\t/*\n\t\t * non-SGMII modes only supports a speed of 1000/Full for the\n\t\t * link so it is best to just force the MAC and let the pcs\n\t\t * link either autoneg or be forced to 1000/Full\n\t\t */\n\t\tctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |\n\t\t\t E1000_CTRL_FD | E1000_CTRL_FRCDPX;\n\n\t\t/* set speed of 1000/Full if speed/duplex is forced */\n\t\treg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;\n\t\tbreak;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);\n\n\t/*\n\t * New SerDes mode allows for forcing speed or autonegotiating speed\n\t * at 1gb. Autoneg should be default set by most drivers. This is the\n\t * mode that will be compatible with older link partners and switches.\n\t * However, both are supported by the hardware and some drivers/tools.\n\t */\n\treg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |\n\t\t E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);\n\n\tif (pcs_autoneg) {\n\t\t/* Set PCS register for autoneg */\n\t\treg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */\n\t\t E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */\n\n\t\t/* Disable force flow control for autoneg */\n\t\treg &= ~E1000_PCS_LCTL_FORCE_FCTRL;\n\n\t\t/* Configure flow control advertisement for autoneg */\n\t\tanadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);\n\t\tanadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);\n\n\t\tswitch (hw->fc.requested_mode) {\n\t\tcase e1000_fc_full:\n\t\tcase e1000_fc_rx_pause:\n\t\t\tanadv_reg |= E1000_TXCW_ASM_DIR;\n\t\t\tanadv_reg |= E1000_TXCW_PAUSE;\n\t\t\tbreak;\n\t\tcase e1000_fc_tx_pause:\n\t\t\tanadv_reg |= E1000_TXCW_ASM_DIR;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tE1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);\n\n\t\tDEBUGOUT1(\"Configuring Autoneg:PCS_LCTL=0x%08X\\n\", reg);\n\t} else {\n\t\t/* Set PCS register for forced link */\n\t\treg |= E1000_PCS_LCTL_FSD;\t/* Force Speed */\n\n\t\t/* Force flow control for forced link */\n\t\treg |= E1000_PCS_LCTL_FORCE_FCTRL;\n\n\t\tDEBUGOUT1(\"Configuring Forced Link:PCS_LCTL=0x%08X\\n\", reg);\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);\n\n\tif (!pcs_autoneg && !e1000_sgmii_active_82575(hw))\n\t\te1000_force_mac_fc_generic(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_media_type_82575 - derives current media type.\n * @hw: pointer to the HW structure\n *\n * The media type is chosen reflecting few settings.\n * The following are taken into account:\n * - link mode set in the current port Init Control Word #3\n * - current link mode settings in CSR register\n * - MDIO vs. I2C PHY control interface chosen\n * - SFP module media type\n **/\nSTATIC s32 e1000_get_media_type_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 ctrl_ext = 0;\n\tu32 link_mode = 0;\n\n\t/* Set internal phy as default */\n\tdev_spec->sgmii_active = false;\n\tdev_spec->module_plugged = false;\n\n\t/* Get CSR setting */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\n\t/* extract link mode setting */\n\tlink_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;\n\n\tswitch (link_mode) {\n\tcase E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:\n\t\thw->phy.media_type = e1000_media_type_internal_serdes;\n\t\tbreak;\n\tcase E1000_CTRL_EXT_LINK_MODE_GMII:\n\t\thw->phy.media_type = e1000_media_type_copper;\n\t\tbreak;\n\tcase E1000_CTRL_EXT_LINK_MODE_SGMII:\n\t\t/* Get phy control interface type set (MDIO vs. I2C)*/\n\t\tif (e1000_sgmii_uses_mdio_82575(hw)) {\n\t\t\thw->phy.media_type = e1000_media_type_copper;\n\t\t\tdev_spec->sgmii_active = true;\n\t\t\tbreak;\n\t\t}\n\t\t/* fall through for I2C based SGMII */\n\tcase E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:\n\t\t/* read media type from SFP EEPROM */\n\t\tret_val = e1000_set_sfp_media_type_82575(hw);\n\t\tif ((ret_val != E1000_SUCCESS) ||\n\t\t (hw->phy.media_type == e1000_media_type_unknown)) {\n\t\t\t/*\n\t\t\t * If media type was not identified then return media\n\t\t\t * type defined by the CTRL_EXT settings.\n\t\t\t */\n\t\t\thw->phy.media_type = e1000_media_type_internal_serdes;\n\n\t\t\tif (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {\n\t\t\t\thw->phy.media_type = e1000_media_type_copper;\n\t\t\t\tdev_spec->sgmii_active = true;\n\t\t\t}\n\n\t\t\tbreak;\n\t\t}\n\n\t\t/* do not change link mode for 100BaseFX */\n\t\tif (dev_spec->eth_flags.e100_base_fx)\n\t\t\tbreak;\n\n\t\t/* change current link mode setting */\n\t\tctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;\n\n\t\tif (hw->phy.media_type == e1000_media_type_copper)\n\t\t\tctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;\n\t\telse\n\t\t\tctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;\n\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\n\t\tbreak;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_set_sfp_media_type_82575 - derives SFP module media type.\n * @hw: pointer to the HW structure\n *\n * The media type is chosen based on SFP module.\n * compatibility flags retrieved from SFP ID EEPROM.\n **/\nSTATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_ERR_CONFIG;\n\tu32 ctrl_ext = 0;\n\tstruct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;\n\tstruct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;\n\tu8 tranceiver_type = 0;\n\ts32 timeout = 3;\n\n\t/* Turn I2C interface ON and power on sfp cage */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);\n\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* Read SFP module data */\n\twhile (timeout) {\n\t\tret_val = e1000_read_sfp_data_byte(hw,\n\t\t\tE1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),\n\t\t\t&tranceiver_type);\n\t\tif (ret_val == E1000_SUCCESS)\n\t\t\tbreak;\n\t\tmsec_delay(100);\n\t\ttimeout--;\n\t}\n\tif (ret_val != E1000_SUCCESS)\n\t\tgoto out;\n\n\tret_val = e1000_read_sfp_data_byte(hw,\n\t\t\tE1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),\n\t\t\t(u8 *)eth_flags);\n\tif (ret_val != E1000_SUCCESS)\n\t\tgoto out;\n\n\t/* Check if there is some SFP module plugged and powered */\n\tif ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||\n\t (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {\n\t\tdev_spec->module_plugged = true;\n\t\tif (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {\n\t\t\thw->phy.media_type = e1000_media_type_internal_serdes;\n\t\t} else if (eth_flags->e100_base_fx) {\n\t\t\tdev_spec->sgmii_active = true;\n\t\t\thw->phy.media_type = e1000_media_type_internal_serdes;\n\t\t} else if (eth_flags->e1000_base_t) {\n\t\t\tdev_spec->sgmii_active = true;\n\t\t\thw->phy.media_type = e1000_media_type_copper;\n\t\t} else {\n\t\t\thw->phy.media_type = e1000_media_type_unknown;\n\t\t\tDEBUGOUT(\"PHY module has not been recognized\\n\");\n\t\t\tgoto out;\n\t\t}\n\t} else {\n\t\thw->phy.media_type = e1000_media_type_unknown;\n\t}\n\tret_val = E1000_SUCCESS;\nout:\n\t/* Restore I2C interface setting */\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\treturn ret_val;\n}\n\n/**\n * e1000_valid_led_default_82575 - Verify a valid default LED config\n * @hw: pointer to the HW structure\n * @data: pointer to the NVM (EEPROM)\n *\n * Read the EEPROM for the current default LED configuration. If the\n * LED configuration is not valid, set to a valid LED configuration.\n **/\nSTATIC s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_valid_led_default_82575\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\tgoto out;\n\t}\n\n\tif (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {\n\t\tswitch (hw->phy.media_type) {\n\t\tcase e1000_media_type_internal_serdes:\n\t\t\t*data = ID_LED_DEFAULT_82575_SERDES;\n\t\t\tbreak;\n\t\tcase e1000_media_type_copper:\n\t\tdefault:\n\t\t\t*data = ID_LED_DEFAULT;\n\t\t\tbreak;\n\t\t}\n\t}\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_sgmii_active_82575 - Return sgmii state\n * @hw: pointer to the HW structure\n *\n * 82575 silicon has a serialized gigabit media independent interface (sgmii)\n * which can be enabled for use in the embedded applications. Simply\n * return the current state of the sgmii interface.\n **/\nSTATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;\n\treturn dev_spec->sgmii_active;\n}\n\n/**\n * e1000_reset_init_script_82575 - Inits HW defaults after reset\n * @hw: pointer to the HW structure\n *\n * Inits recommended HW defaults after a reset when there is no EEPROM\n * detected. This is only for the 82575.\n **/\nSTATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_reset_init_script_82575\");\n\n\tif (hw->mac.type == e1000_82575) {\n\t\tDEBUGOUT(\"Running reset init script for 82575\\n\");\n\t\t/* SerDes configuration via SERDESCTRL */\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);\n\n\t\t/* CCM configuration via CCMCTL register */\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);\n\n\t\t/* PCIe lanes configuration */\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);\n\n\t\t/* PCIe PLL Configuration */\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_mac_addr_82575 - Read device MAC address\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_read_mac_addr_82575\");\n\n\t/*\n\t * If there's an alternate MAC address place it in RAR0\n\t * so that it will override the Si installed default perm\n\t * address.\n\t */\n\tret_val = e1000_check_alt_mac_addr_generic(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_read_mac_addr_generic(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_config_collision_dist_82575 - Configure collision distance\n * @hw: pointer to the HW structure\n *\n * Configures the collision distance to the default value and is used\n * during link setup.\n **/\nSTATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw)\n{\n\tu32 tctl_ext;\n\n\tDEBUGFUNC(\"e1000_config_collision_dist_82575\");\n\n\ttctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);\n\n\ttctl_ext &= ~E1000_TCTL_EXT_COLD;\n\ttctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;\n\n\tE1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * e1000_power_down_phy_copper_82575 - Remove link during PHY power down\n * @hw: pointer to the HW structure\n *\n * In the case of a PHY power down to save power, or to turn off link during a\n * driver unload, or wake on lan is not enabled, remove the link.\n **/\nSTATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\n\tif (!(phy->ops.check_reset_block))\n\t\treturn;\n\n\t/* If the management interface is not enabled, then power down */\n\tif (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))\n\t\te1000_power_down_phy_copper(hw);\n\n\treturn;\n}\n\n/**\n * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters\n * @hw: pointer to the HW structure\n *\n * Clears the hardware counters by reading the counter registers.\n **/\nSTATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_clear_hw_cntrs_82575\");\n\n\te1000_clear_hw_cntrs_base_generic(hw);\n\n\tE1000_READ_REG(hw, E1000_PRC64);\n\tE1000_READ_REG(hw, E1000_PRC127);\n\tE1000_READ_REG(hw, E1000_PRC255);\n\tE1000_READ_REG(hw, E1000_PRC511);\n\tE1000_READ_REG(hw, E1000_PRC1023);\n\tE1000_READ_REG(hw, E1000_PRC1522);\n\tE1000_READ_REG(hw, E1000_PTC64);\n\tE1000_READ_REG(hw, E1000_PTC127);\n\tE1000_READ_REG(hw, E1000_PTC255);\n\tE1000_READ_REG(hw, E1000_PTC511);\n\tE1000_READ_REG(hw, E1000_PTC1023);\n\tE1000_READ_REG(hw, E1000_PTC1522);\n\n\tE1000_READ_REG(hw, E1000_ALGNERRC);\n\tE1000_READ_REG(hw, E1000_RXERRC);\n\tE1000_READ_REG(hw, E1000_TNCRS);\n\tE1000_READ_REG(hw, E1000_CEXTERR);\n\tE1000_READ_REG(hw, E1000_TSCTC);\n\tE1000_READ_REG(hw, E1000_TSCTFC);\n\n\tE1000_READ_REG(hw, E1000_MGTPRC);\n\tE1000_READ_REG(hw, E1000_MGTPDC);\n\tE1000_READ_REG(hw, E1000_MGTPTC);\n\n\tE1000_READ_REG(hw, E1000_IAC);\n\tE1000_READ_REG(hw, E1000_ICRXOC);\n\n\tE1000_READ_REG(hw, E1000_ICRXPTC);\n\tE1000_READ_REG(hw, E1000_ICRXATC);\n\tE1000_READ_REG(hw, E1000_ICTXPTC);\n\tE1000_READ_REG(hw, E1000_ICTXATC);\n\tE1000_READ_REG(hw, E1000_ICTXQEC);\n\tE1000_READ_REG(hw, E1000_ICTXQMTC);\n\tE1000_READ_REG(hw, E1000_ICRXDMTC);\n\n\tE1000_READ_REG(hw, E1000_CBTMPC);\n\tE1000_READ_REG(hw, E1000_HTDPMC);\n\tE1000_READ_REG(hw, E1000_CBRMPC);\n\tE1000_READ_REG(hw, E1000_RPTHC);\n\tE1000_READ_REG(hw, E1000_HGPTC);\n\tE1000_READ_REG(hw, E1000_HTCBDPC);\n\tE1000_READ_REG(hw, E1000_HGORCL);\n\tE1000_READ_REG(hw, E1000_HGORCH);\n\tE1000_READ_REG(hw, E1000_HGOTCL);\n\tE1000_READ_REG(hw, E1000_HGOTCH);\n\tE1000_READ_REG(hw, E1000_LENERRS);\n\n\t/* This register should not be read in copper configurations */\n\tif ((hw->phy.media_type == e1000_media_type_internal_serdes) ||\n\t e1000_sgmii_active_82575(hw))\n\t\tE1000_READ_REG(hw, E1000_SCVPC);\n}\n\n/**\n * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable\n * @hw: pointer to the HW structure\n *\n * After rx enable if managability is enabled then there is likely some\n * bad data at the start of the fifo and possibly in the DMA fifo. This\n * function clears the fifos and flushes any packets that came in as rx was\n * being enabled.\n **/\nvoid e1000_rx_fifo_flush_82575(struct e1000_hw *hw)\n{\n\tu32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;\n\tint i, ms_wait;\n\n\tDEBUGFUNC(\"e1000_rx_fifo_workaround_82575\");\n\tif (hw->mac.type != e1000_82575 ||\n\t !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))\n\t\treturn;\n\n\t/* Disable all Rx queues */\n\tfor (i = 0; i < 4; i++) {\n\t\trxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));\n\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(i),\n\t\t\t\trxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);\n\t}\n\t/* Poll all queues to verify they have shut down */\n\tfor (ms_wait = 0; ms_wait < 10; ms_wait++) {\n\t\tmsec_delay(1);\n\t\trx_enabled = 0;\n\t\tfor (i = 0; i < 4; i++)\n\t\t\trx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));\n\t\tif (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))\n\t\t\tbreak;\n\t}\n\n\tif (ms_wait == 10)\n\t\tDEBUGOUT(\"Queue disable timed out after 10ms\\n\");\n\n\t/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all\n\t * incoming packets are rejected. Set enable and wait 2ms so that\n\t * any packet that was coming in as RCTL.EN was set is flushed\n\t */\n\trfctl = E1000_READ_REG(hw, E1000_RFCTL);\n\tE1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);\n\n\trlpml = E1000_READ_REG(hw, E1000_RLPML);\n\tE1000_WRITE_REG(hw, E1000_RLPML, 0);\n\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\ttemp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);\n\ttemp_rctl |= E1000_RCTL_LPE;\n\n\tE1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);\n\tE1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);\n\tE1000_WRITE_FLUSH(hw);\n\tmsec_delay(2);\n\n\t/* Enable Rx queues that were previously enabled and restore our\n\t * previous state\n\t */\n\tfor (i = 0; i < 4; i++)\n\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\tE1000_WRITE_FLUSH(hw);\n\n\tE1000_WRITE_REG(hw, E1000_RLPML, rlpml);\n\tE1000_WRITE_REG(hw, E1000_RFCTL, rfctl);\n\n\t/* Flush receive errors generated by workaround */\n\tE1000_READ_REG(hw, E1000_ROC);\n\tE1000_READ_REG(hw, E1000_RNBC);\n\tE1000_READ_REG(hw, E1000_MPC);\n}\n\n/**\n * e1000_set_pcie_completion_timeout - set pci-e completion timeout\n * @hw: pointer to the HW structure\n *\n * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,\n * however the hardware default for these parts is 500us to 1ms which is less\n * than the 10ms recommended by the pci-e spec. To address this we need to\n * increase the value to either 10ms to 200ms for capability version 1 config,\n * or 16ms to 55ms for version 2.\n **/\nSTATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)\n{\n\tu32 gcr = E1000_READ_REG(hw, E1000_GCR);\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 pcie_devctl2;\n\n\t/* only take action if timeout value is defaulted to 0 */\n\tif (gcr & E1000_GCR_CMPL_TMOUT_MASK)\n\t\tgoto out;\n\n\t/*\n\t * if capababilities version is type 1 we can write the\n\t * timeout of 10ms to 200ms through the GCR register\n\t */\n\tif (!(gcr & E1000_GCR_CAP_VER2)) {\n\t\tgcr |= E1000_GCR_CMPL_TMOUT_10ms;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * for version 2 capabilities we need to write the config space\n\t * directly in order to set the completion timeout value for\n\t * 16ms to 55ms\n\t */\n\tret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,\n\t\t\t\t\t &pcie_devctl2);\n\tif (ret_val)\n\t\tgoto out;\n\n\tpcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;\n\n\tret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,\n\t\t\t\t\t &pcie_devctl2);\nout:\n\t/* disable completion timeout resend */\n\tgcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;\n\n\tE1000_WRITE_REG(hw, E1000_GCR, gcr);\n\treturn ret_val;\n}\n\n/**\n * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing\n * @hw: pointer to the hardware struct\n * @enable: state to enter, either enabled or disabled\n * @pf: Physical Function pool - do not set anti-spoofing for the PF\n *\n * enables/disables L2 switch anti-spoofing functionality.\n **/\nvoid e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)\n{\n\tu32 reg_val, reg_offset;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82576:\n\t\treg_offset = E1000_DTXSWC;\n\t\tbreak;\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\treg_offset = E1000_TXSWC;\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\treg_val = E1000_READ_REG(hw, reg_offset);\n\tif (enable) {\n\t\treg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |\n\t\t\t E1000_DTXSWC_VLAN_SPOOF_MASK);\n\t\t/* The PF can spoof - it has to in order to\n\t\t * support emulation mode NICs\n\t\t */\n\t\treg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));\n\t} else {\n\t\treg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |\n\t\t\t E1000_DTXSWC_VLAN_SPOOF_MASK);\n\t}\n\tE1000_WRITE_REG(hw, reg_offset, reg_val);\n}\n\n/**\n * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback\n * @hw: pointer to the hardware struct\n * @enable: state to enter, either enabled or disabled\n *\n * enables/disables L2 switch loopback functionality.\n **/\nvoid e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)\n{\n\tu32 dtxswc;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82576:\n\t\tdtxswc = E1000_READ_REG(hw, E1000_DTXSWC);\n\t\tif (enable)\n\t\t\tdtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;\n\t\telse\n\t\t\tdtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;\n\t\tE1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);\n\t\tbreak;\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\tdtxswc = E1000_READ_REG(hw, E1000_TXSWC);\n\t\tif (enable)\n\t\t\tdtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;\n\t\telse\n\t\t\tdtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;\n\t\tE1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);\n\t\tbreak;\n\tdefault:\n\t\t/* Currently no other hardware supports loopback */\n\t\tbreak;\n\t}\n\n\n}\n\n/**\n * e1000_vmdq_set_replication_pf - enable or disable vmdq replication\n * @hw: pointer to the hardware struct\n * @enable: state to enter, either enabled or disabled\n *\n * enables/disables replication of packets across multiple pools.\n **/\nvoid e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)\n{\n\tu32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);\n\n\tif (enable)\n\t\tvt_ctl |= E1000_VT_CTL_VM_REPL_EN;\n\telse\n\t\tvt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;\n\n\tE1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);\n}\n\n/**\n * e1000_read_phy_reg_82580 - Read 82580 MDI control register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the MDI control register in the PHY at offset and stores the\n * information read to data.\n **/\nSTATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_82580\");\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_read_phy_reg_mdic(hw, offset, data);\n\n\thw->phy.ops.release(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_write_phy_reg_82580 - Write 82580 MDI control register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write to register at offset\n *\n * Writes data to MDI control register in the PHY at offset.\n **/\nSTATIC s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_82580\");\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_write_phy_reg_mdic(hw, offset, data);\n\n\thw->phy.ops.release(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits\n * @hw: pointer to the HW structure\n *\n * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on\n * the values found in the EEPROM. This addresses an issue in which these\n * bits are not restored from EEPROM after reset.\n **/\nSTATIC s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 mdicnfg;\n\tu16 nvm_data = 0;\n\n\tDEBUGFUNC(\"e1000_reset_mdicnfg_82580\");\n\n\tif (hw->mac.type != e1000_82580)\n\t\tgoto out;\n\tif (!e1000_sgmii_active_82575(hw))\n\t\tgoto out;\n\n\tret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +\n\t\t\t\t NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,\n\t\t\t\t &nvm_data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\tgoto out;\n\t}\n\n\tmdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);\n\tif (nvm_data & NVM_WORD24_EXT_MDIO)\n\t\tmdicnfg |= E1000_MDICNFG_EXT_MDIO;\n\tif (nvm_data & NVM_WORD24_COM_MDIO)\n\t\tmdicnfg |= E1000_MDICNFG_COM_MDIO;\n\tE1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_reset_hw_82580 - Reset hardware\n * @hw: pointer to the HW structure\n *\n * This resets function or entire device (all ports, etc.)\n * to a known state.\n **/\nSTATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\t/* BH SW mailbox bit in SW_FW_SYNC */\n\tu16 swmbsw_mask = E1000_SW_SYNCH_MB;\n\tu32 ctrl;\n\tbool global_device_reset = hw->dev_spec._82575.global_device_reset;\n\n\tDEBUGFUNC(\"e1000_reset_hw_82580\");\n\n\thw->dev_spec._82575.global_device_reset = false;\n\n\t/* 82580 does not reliably do global_device_reset due to hw errata */\n\tif (hw->mac.type == e1000_82580)\n\t\tglobal_device_reset = false;\n\n\t/* Get current control state. */\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\t/*\n\t * Prevent the PCI-E bus from sticking if there is no TLP connection\n\t * on the last TLP read/write transaction when MAC is reset.\n\t */\n\tret_val = e1000_disable_pcie_master_generic(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"PCI-E Master disable polling has failed.\\n\");\n\n\tDEBUGOUT(\"Masking off all interrupts\\n\");\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\tE1000_WRITE_REG(hw, E1000_RCTL, 0);\n\tE1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);\n\tE1000_WRITE_FLUSH(hw);\n\n\tmsec_delay(10);\n\n\t/* Determine whether or not a global dev reset is requested */\n\tif (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,\n\t swmbsw_mask))\n\t\t\tglobal_device_reset = false;\n\n\tif (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &\n\t E1000_STAT_DEV_RST_SET))\n\t\tctrl |= E1000_CTRL_DEV_RST;\n\telse\n\t\tctrl |= E1000_CTRL_RST;\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* Add delay to insure DEV_RST has time to complete */\n\tif (global_device_reset)\n\t\tmsec_delay(5);\n\n\tret_val = e1000_get_auto_rd_done_generic(hw);\n\tif (ret_val) {\n\t\t/*\n\t\t * When auto config read does not complete, do not\n\t\t * return with an error. This can happen in situations\n\t\t * where there is no eeprom and prevents getting link.\n\t\t */\n\t\tDEBUGOUT(\"Auto Read Done did not complete\\n\");\n\t}\n\n\t/* clear global device reset status bit */\n\tE1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);\n\n\t/* Clear any pending interrupt events. */\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\tE1000_READ_REG(hw, E1000_ICR);\n\n\tret_val = e1000_reset_mdicnfg_82580(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"Could not reset MDICNFG based on EEPROM\\n\");\n\n\t/* Install any alternate MAC address into RAR0 */\n\tret_val = e1000_check_alt_mac_addr_generic(hw);\n\n\t/* Release semaphore */\n\tif (global_device_reset)\n\t\thw->mac.ops.release_swfw_sync(hw, swmbsw_mask);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size\n * @data: data received by reading RXPBS register\n *\n * The 82580 uses a table based approach for packet buffer allocation sizes.\n * This function converts the retrieved value into the correct table value\n * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7\n * 0x0 36 72 144 1 2 4 8 16\n * 0x8 35 70 140 rsv rsv rsv rsv rsv\n */\nu16 e1000_rxpbs_adjust_82580(u32 data)\n{\n\tu16 ret_val = 0;\n\n\tif (data < E1000_82580_RXPBS_TABLE_SIZE)\n\t\tret_val = e1000_82580_rxpbs_table[data];\n\n\treturn ret_val;\n}\n\n/**\n * e1000_validate_nvm_checksum_with_offset - Validate EEPROM\n * checksum\n * @hw: pointer to the HW structure\n * @offset: offset in words of the checksum protected region\n *\n * Calculates the EEPROM checksum by reading/adding each word of the EEPROM\n * and then verifies that the sum of the EEPROM is equal to 0xBABA.\n **/\ns32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 checksum = 0;\n\tu16 i, nvm_data;\n\n\tDEBUGFUNC(\"e1000_validate_nvm_checksum_with_offset\");\n\n\tfor (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {\n\t\tret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\tgoto out;\n\t\t}\n\t\tchecksum += nvm_data;\n\t}\n\n\tif (checksum != (u16) NVM_SUM) {\n\t\tDEBUGOUT(\"NVM Checksum Invalid\\n\");\n\t\tret_val = -E1000_ERR_NVM;\n\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_update_nvm_checksum_with_offset - Update EEPROM\n * checksum\n * @hw: pointer to the HW structure\n * @offset: offset in words of the checksum protected region\n *\n * Updates the EEPROM checksum by reading/adding each word of the EEPROM\n * up to the checksum. Then calculates the EEPROM checksum and writes the\n * value to the EEPROM.\n **/\ns32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)\n{\n\ts32 ret_val;\n\tu16 checksum = 0;\n\tu16 i, nvm_data;\n\n\tDEBUGFUNC(\"e1000_update_nvm_checksum_with_offset\");\n\n\tfor (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {\n\t\tret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error while updating checksum.\\n\");\n\t\t\tgoto out;\n\t\t}\n\t\tchecksum += nvm_data;\n\t}\n\tchecksum = (u16) NVM_SUM - checksum;\n\tret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,\n\t\t\t\t &checksum);\n\tif (ret_val)\n\t\tDEBUGOUT(\"NVM Write Error while updating checksum.\\n\");\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Calculates the EEPROM section checksum by reading/adding each word of\n * the EEPROM and then verifies that the sum of the EEPROM is\n * equal to 0xBABA.\n **/\nSTATIC s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 eeprom_regions_count = 1;\n\tu16 j, nvm_data;\n\tu16 nvm_offset;\n\n\tDEBUGFUNC(\"e1000_validate_nvm_checksum_82580\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\tgoto out;\n\t}\n\n\tif (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {\n\t\t/* if chekcsums compatibility bit is set validate checksums\n\t\t * for all 4 ports. */\n\t\teeprom_regions_count = 4;\n\t}\n\n\tfor (j = 0; j < eeprom_regions_count; j++) {\n\t\tnvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);\n\t\tret_val = e1000_validate_nvm_checksum_with_offset(hw,\n\t\t\t\t\t\t\t\t nvm_offset);\n\t\tif (ret_val != E1000_SUCCESS)\n\t\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_update_nvm_checksum_82580 - Update EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Updates the EEPROM section checksums for all 4 ports by reading/adding\n * each word of the EEPROM up to the checksum. Then calculates the EEPROM\n * checksum and writes the value to the EEPROM.\n **/\nSTATIC s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 j, nvm_data;\n\tu16 nvm_offset;\n\n\tDEBUGFUNC(\"e1000_update_nvm_checksum_82580\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error while updating checksum compatibility bit.\\n\");\n\t\tgoto out;\n\t}\n\n\tif (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {\n\t\t/* set compatibility bit to validate checksums appropriately */\n\t\tnvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;\n\t\tret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,\n\t\t\t\t\t &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Write Error while updating checksum compatibility bit.\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\tfor (j = 0; j < 4; j++) {\n\t\tnvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);\n\t\tret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Calculates the EEPROM section checksum by reading/adding each word of\n * the EEPROM and then verifies that the sum of the EEPROM is\n * equal to 0xBABA.\n **/\nSTATIC s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 j;\n\tu16 nvm_offset;\n\n\tDEBUGFUNC(\"e1000_validate_nvm_checksum_i350\");\n\n\tfor (j = 0; j < 4; j++) {\n\t\tnvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);\n\t\tret_val = e1000_validate_nvm_checksum_with_offset(hw,\n\t\t\t\t\t\t\t\t nvm_offset);\n\t\tif (ret_val != E1000_SUCCESS)\n\t\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_update_nvm_checksum_i350 - Update EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Updates the EEPROM section checksums for all 4 ports by reading/adding\n * each word of the EEPROM up to the checksum. Then calculates the EEPROM\n * checksum and writes the value to the EEPROM.\n **/\nSTATIC s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 j;\n\tu16 nvm_offset;\n\n\tDEBUGFUNC(\"e1000_update_nvm_checksum_i350\");\n\n\tfor (j = 0; j < 4; j++) {\n\t\tnvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);\n\t\tret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);\n\t\tif (ret_val != E1000_SUCCESS)\n\t\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * __e1000_access_emi_reg - Read/write EMI register\n * @hw: pointer to the HW structure\n * @addr: EMI address to program\n * @data: pointer to value to read/write from/to the EMI address\n * @read: boolean flag to indicate read or write\n **/\nSTATIC s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,\n\t\t\t\t u16 *data, bool read)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"__e1000_access_emi_reg\");\n\n\tret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (read)\n\t\tret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);\n\telse\n\t\tret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_emi_reg - Read Extended Management Interface register\n * @hw: pointer to the HW structure\n * @addr: EMI address to program\n * @data: value to be read from the EMI address\n **/\ns32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)\n{\n\tDEBUGFUNC(\"e1000_read_emi_reg\");\n\n\treturn __e1000_access_emi_reg(hw, addr, data, true);\n}\n\n/**\n * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY\n * @hw: pointer to the HW structure\n *\n * Initialize Marverl 1512 to work correctly with Avoton.\n **/\ns32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_initialize_M88E1512_phy\");\n\n\t/* Check if this is correct PHY. */\n\tif (phy->id != M88E1512_E_PHY_ID)\n\t\tgoto out;\n\n\t/* Switch to PHY page 0xFF. */\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/* Switch to PHY page 0xFB. */\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/* Switch to PHY page 0x12. */\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/* Change mode to SGMII-to-Copper */\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/* Return the PHY to page 0. */\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = phy->ops.commit(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error committing the PHY changes\\n\");\n\t\treturn ret_val;\n\t}\n\n\tmsec_delay(1000);\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_set_eee_i350 - Enable/disable EEE support\n * @hw: pointer to the HW structure\n *\n * Enable/disable EEE based on setting in dev_spec structure.\n *\n **/\ns32 e1000_set_eee_i350(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 ipcnfg, eeer;\n\n\tDEBUGFUNC(\"e1000_set_eee_i350\");\n\n\tif ((hw->mac.type < e1000_i350) ||\n\t (hw->phy.media_type != e1000_media_type_copper))\n\t\tgoto out;\n\tipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);\n\teeer = E1000_READ_REG(hw, E1000_EEER);\n\n\t/* enable or disable per user setting */\n\tif (!(hw->dev_spec._82575.eee_disable)) {\n\t\tu32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);\n\n\t\tipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);\n\t\teeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |\n\t\t\t E1000_EEER_LPI_FC);\n\n\t\t/* This bit should not be set in normal operation. */\n\t\tif (eee_su & E1000_EEE_SU_LPI_CLK_STP)\n\t\t\tDEBUGOUT(\"LPI Clock Stop Bit should not be set!\\n\");\n\t} else {\n\t\tipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);\n\t\teeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |\n\t\t\t E1000_EEER_LPI_FC);\n\t}\n\tE1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);\n\tE1000_WRITE_REG(hw, E1000_EEER, eeer);\n\tE1000_READ_REG(hw, E1000_IPCNFG);\n\tE1000_READ_REG(hw, E1000_EEER);\nout:\n\n\treturn ret_val;\n}\n\n/**\n * e1000_set_eee_i354 - Enable/disable EEE support\n * @hw: pointer to the HW structure\n *\n * Enable/disable EEE legacy mode based on setting in dev_spec structure.\n *\n **/\ns32 e1000_set_eee_i354(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_set_eee_i354\");\n\n\tif ((hw->phy.media_type != e1000_media_type_copper) ||\n\t ((phy->id != M88E1543_E_PHY_ID) &&\n\t (phy->id != M88E1512_E_PHY_ID)))\n\t\tgoto out;\n\n\tif (!hw->dev_spec._82575.eee_disable) {\n\t\t/* Switch to PHY page 18. */\n\t\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tphy_data |= E1000_M88E1543_EEE_CTRL_1_MS;\n\t\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,\n\t\t\t\t\t phy_data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\t/* Return the PHY to page 0. */\n\t\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\t/* Turn on EEE advertisement. */\n\t\tret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,\n\t\t\t\t\t E1000_EEE_ADV_DEV_I354,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tphy_data |= E1000_EEE_ADV_100_SUPPORTED |\n\t\t\t E1000_EEE_ADV_1000_SUPPORTED;\n\t\tret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,\n\t\t\t\t\t\tE1000_EEE_ADV_DEV_I354,\n\t\t\t\t\t\tphy_data);\n\t} else {\n\t\t/* Turn off EEE advertisement. */\n\t\tret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,\n\t\t\t\t\t E1000_EEE_ADV_DEV_I354,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tphy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |\n\t\t\t E1000_EEE_ADV_1000_SUPPORTED);\n\t\tret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,\n\t\t\t\t\t\tE1000_EEE_ADV_DEV_I354,\n\t\t\t\t\t\tphy_data);\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_get_eee_status_i354 - Get EEE status\n * @hw: pointer to the HW structure\n * @status: EEE status\n *\n * Get EEE status by guessing based on whether Tx or Rx LPI indications have\n * been received.\n **/\ns32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_get_eee_status_i354\");\n\n\t/* Check if EEE is supported on this device. */\n\tif ((hw->phy.media_type != e1000_media_type_copper) ||\n\t ((phy->id != M88E1543_E_PHY_ID) &&\n\t (phy->id != M88E1512_E_PHY_ID)))\n\t\tgoto out;\n\n\tret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,\n\t\t\t\t E1000_PCS_STATUS_DEV_I354,\n\t\t\t\t &phy_data);\n\tif (ret_val)\n\t\tgoto out;\n\n\t*status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |\n\t\t\t E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;\n\nout:\n\treturn ret_val;\n}\n\n/* Due to a hw errata, if the host tries to configure the VFTA register\n * while performing queries from the BMC or DMA, then the VFTA in some\n * cases won't be written.\n */\n\n/**\n * e1000_clear_vfta_i350 - Clear VLAN filter table\n * @hw: pointer to the HW structure\n *\n * Clears the register array which contains the VLAN filter table by\n * setting all the values to 0.\n **/\nvoid e1000_clear_vfta_i350(struct e1000_hw *hw)\n{\n\tu32 offset;\n\tint i;\n\n\tDEBUGFUNC(\"e1000_clear_vfta_350\");\n\n\tfor (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {\n\t\tfor (i = 0; i < 10; i++)\n\t\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);\n\n\t\tE1000_WRITE_FLUSH(hw);\n\t}\n}\n\n/**\n * e1000_write_vfta_i350 - Write value to VLAN filter table\n * @hw: pointer to the HW structure\n * @offset: register offset in VLAN filter table\n * @value: register value written to VLAN filter table\n *\n * Writes value at the given offset in the register array which stores\n * the VLAN filter table.\n **/\nvoid e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)\n{\n\tint i;\n\n\tDEBUGFUNC(\"e1000_write_vfta_350\");\n\n\tfor (i = 0; i < 10; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);\n\n\tE1000_WRITE_FLUSH(hw);\n}\n\n\n/**\n * e1000_set_i2c_bb - Enable I2C bit-bang\n * @hw: pointer to the HW structure\n *\n * Enable I2C bit-bang interface\n *\n **/\ns32 e1000_set_i2c_bb(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 ctrl_ext, i2cparams;\n\n\tDEBUGFUNC(\"e1000_set_i2c_bb\");\n\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tctrl_ext |= E1000_CTRL_I2C_ENA;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\tE1000_WRITE_FLUSH(hw);\n\n\ti2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\ti2cparams |= E1000_I2CBB_EN;\n\ti2cparams |= E1000_I2C_DATA_OE_N;\n\ti2cparams |= E1000_I2C_CLK_OE_N;\n\tE1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);\n\tE1000_WRITE_FLUSH(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to read\n * @dev_addr: device address\n * @data: value read\n *\n * Performs byte read operation over I2C interface at\n * a specified device address.\n **/\ns32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t\tu8 dev_addr, u8 *data)\n{\n\ts32 status = E1000_SUCCESS;\n\tu32 max_retry = 10;\n\tu32 retry = 1;\n\tu16 swfw_mask = 0;\n\n\tbool nack = true;\n\n\tDEBUGFUNC(\"e1000_read_i2c_byte_generic\");\n\n\tswfw_mask = E1000_SWFW_PHY0_SM;\n\n\tdo {\n\t\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)\n\t\t != E1000_SUCCESS) {\n\t\t\tstatus = E1000_ERR_SWFW_SYNC;\n\t\t\tgoto read_byte_out;\n\t\t}\n\n\t\te1000_i2c_start(hw);\n\n\t\t/* Device Address and write indication */\n\t\tstatus = e1000_clock_out_i2c_byte(hw, dev_addr);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_get_i2c_ack(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_clock_out_i2c_byte(hw, byte_offset);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_get_i2c_ack(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\te1000_i2c_start(hw);\n\n\t\t/* Device Address and read indication */\n\t\tstatus = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_get_i2c_ack(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_clock_in_i2c_byte(hw, data);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_clock_out_i2c_bit(hw, nack);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\te1000_i2c_stop(hw);\n\t\tbreak;\n\nfail:\n\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\t\tmsec_delay(100);\n\t\te1000_i2c_bus_clear(hw);\n\t\tretry++;\n\t\tif (retry < max_retry)\n\t\t\tDEBUGOUT(\"I2C byte read error - Retrying.\\n\");\n\t\telse\n\t\t\tDEBUGOUT(\"I2C byte read error.\\n\");\n\n\t} while (retry < max_retry);\n\n\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\nread_byte_out:\n\n\treturn status;\n}\n\n/**\n * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @dev_addr: device address\n * @data: value to write\n *\n * Performs byte write operation over I2C interface at\n * a specified device address.\n **/\ns32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data)\n{\n\ts32 status = E1000_SUCCESS;\n\tu32 max_retry = 1;\n\tu32 retry = 0;\n\tu16 swfw_mask = 0;\n\n\tDEBUGFUNC(\"e1000_write_i2c_byte_generic\");\n\n\tswfw_mask = E1000_SWFW_PHY0_SM;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {\n\t\tstatus = E1000_ERR_SWFW_SYNC;\n\t\tgoto write_byte_out;\n\t}\n\n\tdo {\n\t\te1000_i2c_start(hw);\n\n\t\tstatus = e1000_clock_out_i2c_byte(hw, dev_addr);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_get_i2c_ack(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_clock_out_i2c_byte(hw, byte_offset);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_get_i2c_ack(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_clock_out_i2c_byte(hw, data);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_get_i2c_ack(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\te1000_i2c_stop(hw);\n\t\tbreak;\n\nfail:\n\t\te1000_i2c_bus_clear(hw);\n\t\tretry++;\n\t\tif (retry < max_retry)\n\t\t\tDEBUGOUT(\"I2C byte write error - Retrying.\\n\");\n\t\telse\n\t\t\tDEBUGOUT(\"I2C byte write error.\\n\");\n\t} while (retry < max_retry);\n\n\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\nwrite_byte_out:\n\n\treturn status;\n}\n\n/**\n * e1000_i2c_start - Sets I2C start condition\n * @hw: pointer to hardware structure\n *\n * Sets I2C start condition (High -> Low on SDA while SCL is High)\n **/\nSTATIC void e1000_i2c_start(struct e1000_hw *hw)\n{\n\tu32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\tDEBUGFUNC(\"e1000_i2c_start\");\n\n\t/* Start condition must begin with data and clock high */\n\te1000_set_i2c_data(hw, &i2cctl, 1);\n\te1000_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Setup time for start condition (4.7us) */\n\tusec_delay(E1000_I2C_T_SU_STA);\n\n\te1000_set_i2c_data(hw, &i2cctl, 0);\n\n\t/* Hold time for start condition (4us) */\n\tusec_delay(E1000_I2C_T_HD_STA);\n\n\te1000_lower_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum low period of clock is 4.7 us */\n\tusec_delay(E1000_I2C_T_LOW);\n\n}\n\n/**\n * e1000_i2c_stop - Sets I2C stop condition\n * @hw: pointer to hardware structure\n *\n * Sets I2C stop condition (Low -> High on SDA while SCL is High)\n **/\nSTATIC void e1000_i2c_stop(struct e1000_hw *hw)\n{\n\tu32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\tDEBUGFUNC(\"e1000_i2c_stop\");\n\n\t/* Stop condition must begin with data low and clock high */\n\te1000_set_i2c_data(hw, &i2cctl, 0);\n\te1000_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Setup time for stop condition (4us) */\n\tusec_delay(E1000_I2C_T_SU_STO);\n\n\te1000_set_i2c_data(hw, &i2cctl, 1);\n\n\t/* bus free time between stop and start (4.7us)*/\n\tusec_delay(E1000_I2C_T_BUF);\n}\n\n/**\n * e1000_clock_in_i2c_byte - Clocks in one byte via I2C\n * @hw: pointer to hardware structure\n * @data: data byte to clock in\n *\n * Clocks in one byte data via I2C data/clock\n **/\nSTATIC s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)\n{\n\ts32 i;\n\tbool bit = 0;\n\n\tDEBUGFUNC(\"e1000_clock_in_i2c_byte\");\n\n\t*data = 0;\n\tfor (i = 7; i >= 0; i--) {\n\t\te1000_clock_in_i2c_bit(hw, &bit);\n\t\t*data |= bit << i;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_clock_out_i2c_byte - Clocks out one byte via I2C\n * @hw: pointer to hardware structure\n * @data: data byte clocked out\n *\n * Clocks out one byte data via I2C data/clock\n **/\nSTATIC s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)\n{\n\ts32 status = E1000_SUCCESS;\n\ts32 i;\n\tu32 i2cctl;\n\tbool bit = 0;\n\n\tDEBUGFUNC(\"e1000_clock_out_i2c_byte\");\n\n\tfor (i = 7; i >= 0; i--) {\n\t\tbit = (data >> i) & 0x1;\n\t\tstatus = e1000_clock_out_i2c_bit(hw, bit);\n\n\t\tif (status != E1000_SUCCESS)\n\t\t\tbreak;\n\t}\n\n\t/* Release SDA line (set high) */\n\ti2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\ti2cctl |= E1000_I2C_DATA_OE_N;\n\tE1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);\n\tE1000_WRITE_FLUSH(hw);\n\n\treturn status;\n}\n\n/**\n * e1000_get_i2c_ack - Polls for I2C ACK\n * @hw: pointer to hardware structure\n *\n * Clocks in/out one bit via I2C data/clock\n **/\nSTATIC s32 e1000_get_i2c_ack(struct e1000_hw *hw)\n{\n\ts32 status = E1000_SUCCESS;\n\tu32 i = 0;\n\tu32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\tu32 timeout = 10;\n\tbool ack = true;\n\n\tDEBUGFUNC(\"e1000_get_i2c_ack\");\n\n\te1000_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum high period of clock is 4us */\n\tusec_delay(E1000_I2C_T_HIGH);\n\n\t/* Wait until SCL returns high */\n\tfor (i = 0; i < timeout; i++) {\n\t\tusec_delay(1);\n\t\ti2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\t\tif (i2cctl & E1000_I2C_CLK_IN)\n\t\t\tbreak;\n\t}\n\tif (!(i2cctl & E1000_I2C_CLK_IN))\n\t\treturn E1000_ERR_I2C;\n\n\tack = e1000_get_i2c_data(&i2cctl);\n\tif (ack) {\n\t\tDEBUGOUT(\"I2C ack was not received.\\n\");\n\t\tstatus = E1000_ERR_I2C;\n\t}\n\n\te1000_lower_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum low period of clock is 4.7 us */\n\tusec_delay(E1000_I2C_T_LOW);\n\n\treturn status;\n}\n\n/**\n * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock\n * @hw: pointer to hardware structure\n * @data: read data value\n *\n * Clocks in one bit via I2C data/clock\n **/\nSTATIC s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)\n{\n\tu32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\tDEBUGFUNC(\"e1000_clock_in_i2c_bit\");\n\n\te1000_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum high period of clock is 4us */\n\tusec_delay(E1000_I2C_T_HIGH);\n\n\ti2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\t*data = e1000_get_i2c_data(&i2cctl);\n\n\te1000_lower_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum low period of clock is 4.7 us */\n\tusec_delay(E1000_I2C_T_LOW);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock\n * @hw: pointer to hardware structure\n * @data: data value to write\n *\n * Clocks out one bit via I2C data/clock\n **/\nSTATIC s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)\n{\n\ts32 status;\n\tu32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\tDEBUGFUNC(\"e1000_clock_out_i2c_bit\");\n\n\tstatus = e1000_set_i2c_data(hw, &i2cctl, data);\n\tif (status == E1000_SUCCESS) {\n\t\te1000_raise_i2c_clk(hw, &i2cctl);\n\n\t\t/* Minimum high period of clock is 4us */\n\t\tusec_delay(E1000_I2C_T_HIGH);\n\n\t\te1000_lower_i2c_clk(hw, &i2cctl);\n\n\t\t/* Minimum low period of clock is 4.7 us.\n\t\t * This also takes care of the data hold time.\n\t\t */\n\t\tusec_delay(E1000_I2C_T_LOW);\n\t} else {\n\t\tstatus = E1000_ERR_I2C;\n\t\tDEBUGOUT1(\"I2C data was not set to %X\\n\", data);\n\t}\n\n\treturn status;\n}\n/**\n * e1000_raise_i2c_clk - Raises the I2C SCL clock\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Raises the I2C clock line '0'->'1'\n **/\nSTATIC void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)\n{\n\tDEBUGFUNC(\"e1000_raise_i2c_clk\");\n\n\t*i2cctl |= E1000_I2C_CLK_OUT;\n\t*i2cctl &= ~E1000_I2C_CLK_OE_N;\n\tE1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* SCL rise time (1000ns) */\n\tusec_delay(E1000_I2C_T_RISE);\n}\n\n/**\n * e1000_lower_i2c_clk - Lowers the I2C SCL clock\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Lowers the I2C clock line '1'->'0'\n **/\nSTATIC void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)\n{\n\n\tDEBUGFUNC(\"e1000_lower_i2c_clk\");\n\n\t*i2cctl &= ~E1000_I2C_CLK_OUT;\n\t*i2cctl &= ~E1000_I2C_CLK_OE_N;\n\tE1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* SCL fall time (300ns) */\n\tusec_delay(E1000_I2C_T_FALL);\n}\n\n/**\n * e1000_set_i2c_data - Sets the I2C data bit\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n * @data: I2C data value (0 or 1) to set\n *\n * Sets the I2C data bit\n **/\nSTATIC s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)\n{\n\ts32 status = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_set_i2c_data\");\n\n\tif (data)\n\t\t*i2cctl |= E1000_I2C_DATA_OUT;\n\telse\n\t\t*i2cctl &= ~E1000_I2C_DATA_OUT;\n\n\t*i2cctl &= ~E1000_I2C_DATA_OE_N;\n\t*i2cctl |= E1000_I2C_CLK_OE_N;\n\tE1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */\n\tusec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);\n\n\t*i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\tif (data != e1000_get_i2c_data(i2cctl)) {\n\t\tstatus = E1000_ERR_I2C;\n\t\tDEBUGOUT1(\"Error - I2C data was not set to %X.\\n\", data);\n\t}\n\n\treturn status;\n}\n\n/**\n * e1000_get_i2c_data - Reads the I2C SDA data bit\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Returns the I2C data bit value\n **/\nSTATIC bool e1000_get_i2c_data(u32 *i2cctl)\n{\n\tbool data;\n\n\tDEBUGFUNC(\"e1000_get_i2c_data\");\n\n\tif (*i2cctl & E1000_I2C_DATA_IN)\n\t\tdata = 1;\n\telse\n\t\tdata = 0;\n\n\treturn data;\n}\n\n/**\n * e1000_i2c_bus_clear - Clears the I2C bus\n * @hw: pointer to hardware structure\n *\n * Clears the I2C bus by sending nine clock pulses.\n * Used when data line is stuck low.\n **/\nvoid e1000_i2c_bus_clear(struct e1000_hw *hw)\n{\n\tu32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\tu32 i;\n\n\tDEBUGFUNC(\"e1000_i2c_bus_clear\");\n\n\te1000_i2c_start(hw);\n\n\te1000_set_i2c_data(hw, &i2cctl, 1);\n\n\tfor (i = 0; i < 9; i++) {\n\t\te1000_raise_i2c_clk(hw, &i2cctl);\n\n\t\t/* Min high period of clock is 4us */\n\t\tusec_delay(E1000_I2C_T_HIGH);\n\n\t\te1000_lower_i2c_clk(hw, &i2cctl);\n\n\t\t/* Min low period of clock is 4.7us*/\n\t\tusec_delay(E1000_I2C_T_LOW);\n\t}\n\n\te1000_i2c_start(hw);\n\n\t/* Put the i2c bus back to default state */\n\te1000_i2c_stop(hw);\n}\n\n" }, { "path": "drivers/net/e1000/base/e1000_82575.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_82575_H_\n#define _E1000_82575_H_\n\n#define ID_LED_DEFAULT_82575_SERDES\t((ID_LED_DEF1_DEF2 << 12) | \\\n\t\t\t\t\t (ID_LED_DEF1_DEF2 << 8) | \\\n\t\t\t\t\t (ID_LED_DEF1_DEF2 << 4) | \\\n\t\t\t\t\t (ID_LED_OFF1_ON2))\n/*\n * Receive Address Register Count\n * Number of high/low register pairs in the RAR. The RAR (Receive Address\n * Registers) holds the directed and multicast addresses that we monitor.\n * These entries are also used for MAC-based filtering.\n */\n/*\n * For 82576, there are an additional set of RARs that begin at an offset\n * separate from the first set of RARs.\n */\n#define E1000_RAR_ENTRIES_82575\t16\n#define E1000_RAR_ENTRIES_82576\t24\n#define E1000_RAR_ENTRIES_82580\t24\n#define E1000_RAR_ENTRIES_I350\t32\n#define E1000_SW_SYNCH_MB\t0x00000100\n#define E1000_STAT_DEV_RST_SET\t0x00100000\n#define E1000_CTRL_DEV_RST\t0x20000000\n\n#ifdef E1000_BIT_FIELDS\nstruct e1000_adv_data_desc {\n\t__le64 buffer_addr; /* Address of the descriptor's data buffer */\n\tunion {\n\t\tu32 data;\n\t\tstruct {\n\t\t\tu32 datalen:16; /* Data buffer length */\n\t\t\tu32 rsvd:4;\n\t\t\tu32 dtyp:4; /* Descriptor type */\n\t\t\tu32 dcmd:8; /* Descriptor command */\n\t\t} config;\n\t} lower;\n\tunion {\n\t\tu32 data;\n\t\tstruct {\n\t\t\tu32 status:4; /* Descriptor status */\n\t\t\tu32 idx:4;\n\t\t\tu32 popts:6; /* Packet Options */\n\t\t\tu32 paylen:18; /* Payload length */\n\t\t} options;\n\t} upper;\n};\n\n#define E1000_TXD_DTYP_ADV_C\t0x2 /* Advanced Context Descriptor */\n#define E1000_TXD_DTYP_ADV_D\t0x3 /* Advanced Data Descriptor */\n#define E1000_ADV_TXD_CMD_DEXT\t0x20 /* Descriptor extension (0 = legacy) */\n#define E1000_ADV_TUCMD_IPV4\t0x2 /* IP Packet Type: 1=IPv4 */\n#define E1000_ADV_TUCMD_IPV6\t0x0 /* IP Packet Type: 0=IPv6 */\n#define E1000_ADV_TUCMD_L4T_UDP\t0x0 /* L4 Packet TYPE of UDP */\n#define E1000_ADV_TUCMD_L4T_TCP\t0x4 /* L4 Packet TYPE of TCP */\n#define E1000_ADV_TUCMD_MKRREQ\t0x10 /* Indicates markers are required */\n#define E1000_ADV_DCMD_EOP\t0x1 /* End of Packet */\n#define E1000_ADV_DCMD_IFCS\t0x2 /* Insert FCS (Ethernet CRC) */\n#define E1000_ADV_DCMD_RS\t0x8 /* Report Status */\n#define E1000_ADV_DCMD_VLE\t0x40 /* Add VLAN tag */\n#define E1000_ADV_DCMD_TSE\t0x80 /* TCP Seg enable */\n/* Extended Device Control */\n#define E1000_CTRL_EXT_NSICR\t0x00000001 /* Disable Intr Clear all on read */\n\nstruct e1000_adv_context_desc {\n\tunion {\n\t\tu32 ip_config;\n\t\tstruct {\n\t\t\tu32 iplen:9;\n\t\t\tu32 maclen:7;\n\t\t\tu32 vlan_tag:16;\n\t\t} fields;\n\t} ip_setup;\n\tu32 seq_num;\n\tunion {\n\t\tu64 l4_config;\n\t\tstruct {\n\t\t\tu32 mkrloc:9;\n\t\t\tu32 tucmd:11;\n\t\t\tu32 dtyp:4;\n\t\t\tu32 adv:8;\n\t\t\tu32 rsvd:4;\n\t\t\tu32 idx:4;\n\t\t\tu32 l4len:8;\n\t\t\tu32 mss:16;\n\t\t} fields;\n\t} l4_setup;\n};\n#endif\n\n/* SRRCTL bit definitions */\n#define E1000_SRRCTL_BSIZEPKT_SHIFT\t\t10 /* Shift _right_ */\n#define E1000_SRRCTL_BSIZEHDRSIZE_MASK\t\t0x00000F00\n#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT\t\t2 /* Shift _left_ */\n#define E1000_SRRCTL_DESCTYPE_LEGACY\t\t0x00000000\n#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF\t0x02000000\n#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT\t\t0x04000000\n#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS\t0x0A000000\n#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION\t0x06000000\n#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000\n#define E1000_SRRCTL_DESCTYPE_MASK\t\t0x0E000000\n#define E1000_SRRCTL_TIMESTAMP\t\t\t0x40000000\n#define E1000_SRRCTL_DROP_EN\t\t\t0x80000000\n\n#define E1000_SRRCTL_BSIZEPKT_MASK\t\t0x0000007F\n#define E1000_SRRCTL_BSIZEHDR_MASK\t\t0x00003F00\n\n#define E1000_TX_HEAD_WB_ENABLE\t\t0x1\n#define E1000_TX_SEQNUM_WB_ENABLE\t0x2\n\n#define E1000_MRQC_ENABLE_RSS_4Q\t\t0x00000002\n#define E1000_MRQC_ENABLE_VMDQ\t\t\t0x00000003\n#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q\t\t0x00000005\n#define E1000_MRQC_RSS_FIELD_IPV4_UDP\t\t0x00400000\n#define E1000_MRQC_RSS_FIELD_IPV6_UDP\t\t0x00800000\n#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX\t0x01000000\n#define E1000_MRQC_ENABLE_RSS_8Q\t\t0x00000002\n\n#define E1000_VMRCTL_MIRROR_PORT_SHIFT\t\t8\n#define E1000_VMRCTL_MIRROR_DSTPORT_MASK\t(7 << \\\n\t\t\t\t\t\t E1000_VMRCTL_MIRROR_PORT_SHIFT)\n#define E1000_VMRCTL_POOL_MIRROR_ENABLE\t\t(1 << 0)\n#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE\t(1 << 1)\n#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE\t(1 << 2)\n\n#define E1000_EICR_TX_QUEUE ( \\\n\tE1000_EICR_TX_QUEUE0 | \\\n\tE1000_EICR_TX_QUEUE1 | \\\n\tE1000_EICR_TX_QUEUE2 | \\\n\tE1000_EICR_TX_QUEUE3)\n\n#define E1000_EICR_RX_QUEUE ( \\\n\tE1000_EICR_RX_QUEUE0 | \\\n\tE1000_EICR_RX_QUEUE1 | \\\n\tE1000_EICR_RX_QUEUE2 | \\\n\tE1000_EICR_RX_QUEUE3)\n\n#define E1000_EIMS_RX_QUEUE\tE1000_EICR_RX_QUEUE\n#define E1000_EIMS_TX_QUEUE\tE1000_EICR_TX_QUEUE\n\n#define EIMS_ENABLE_MASK ( \\\n\tE1000_EIMS_RX_QUEUE | \\\n\tE1000_EIMS_TX_QUEUE | \\\n\tE1000_EIMS_TCP_TIMER | \\\n\tE1000_EIMS_OTHER)\n\n/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */\n#define E1000_IMIR_PORT_IM_EN\t0x00010000 /* TCP port enable */\n#define E1000_IMIR_PORT_BP\t0x00020000 /* TCP port check bypass */\n#define E1000_IMIREXT_SIZE_BP\t0x00001000 /* Packet size bypass */\n#define E1000_IMIREXT_CTRL_URG\t0x00002000 /* Check URG bit in header */\n#define E1000_IMIREXT_CTRL_ACK\t0x00004000 /* Check ACK bit in header */\n#define E1000_IMIREXT_CTRL_PSH\t0x00008000 /* Check PSH bit in header */\n#define E1000_IMIREXT_CTRL_RST\t0x00010000 /* Check RST bit in header */\n#define E1000_IMIREXT_CTRL_SYN\t0x00020000 /* Check SYN bit in header */\n#define E1000_IMIREXT_CTRL_FIN\t0x00040000 /* Check FIN bit in header */\n#define E1000_IMIREXT_CTRL_BP\t0x00080000 /* Bypass check of ctrl bits */\n\n/* Receive Descriptor - Advanced */\nunion e1000_adv_rx_desc {\n\tstruct {\n\t\t__le64 pkt_addr; /* Packet buffer address */\n\t\t__le64 hdr_addr; /* Header buffer address */\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\t__le32 data;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 pkt_info; /*RSS type, Pkt type*/\n\t\t\t\t\t/* Split Header, header buffer len */\n\t\t\t\t\t__le16 hdr_info;\n\t\t\t\t} hs_rss;\n\t\t\t} lo_dword;\n\t\t\tunion {\n\t\t\t\t__le32 rss; /* RSS Hash */\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id; /* IP id */\n\t\t\t\t\t__le16 csum; /* Packet Checksum */\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error; /* ext status/error */\n\t\t\t__le16 length; /* Packet length */\n\t\t\t__le16 vlan; /* VLAN tag */\n\t\t} upper;\n\t} wb; /* writeback */\n};\n\n#define E1000_RXDADV_RSSTYPE_MASK\t0x0000000F\n#define E1000_RXDADV_RSSTYPE_SHIFT\t12\n#define E1000_RXDADV_HDRBUFLEN_MASK\t0x7FE0\n#define E1000_RXDADV_HDRBUFLEN_SHIFT\t5\n#define E1000_RXDADV_SPLITHEADER_EN\t0x00001000\n#define E1000_RXDADV_SPH\t\t0x8000\n#define E1000_RXDADV_STAT_TS\t\t0x10000 /* Pkt was time stamped */\n#define E1000_RXDADV_STAT_TSIP\t\t0x08000 /* timestamp in packet */\n#define E1000_RXDADV_ERR_HBO\t\t0x00800000\n\n/* RSS Hash results */\n#define E1000_RXDADV_RSSTYPE_NONE\t0x00000000\n#define E1000_RXDADV_RSSTYPE_IPV4_TCP\t0x00000001\n#define E1000_RXDADV_RSSTYPE_IPV4\t0x00000002\n#define E1000_RXDADV_RSSTYPE_IPV6_TCP\t0x00000003\n#define E1000_RXDADV_RSSTYPE_IPV6_EX\t0x00000004\n#define E1000_RXDADV_RSSTYPE_IPV6\t0x00000005\n#define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006\n#define E1000_RXDADV_RSSTYPE_IPV4_UDP\t0x00000007\n#define E1000_RXDADV_RSSTYPE_IPV6_UDP\t0x00000008\n#define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009\n\n/* RSS Packet Types as indicated in the receive descriptor */\n#define E1000_RXDADV_PKTTYPE_ILMASK\t0x000000F0\n#define E1000_RXDADV_PKTTYPE_TLMASK\t0x00000F00\n#define E1000_RXDADV_PKTTYPE_NONE\t0x00000000\n#define E1000_RXDADV_PKTTYPE_IPV4\t0x00000010 /* IPV4 hdr present */\n#define E1000_RXDADV_PKTTYPE_IPV4_EX\t0x00000020 /* IPV4 hdr + extensions */\n#define E1000_RXDADV_PKTTYPE_IPV6\t0x00000040 /* IPV6 hdr present */\n#define E1000_RXDADV_PKTTYPE_IPV6_EX\t0x00000080 /* IPV6 hdr + extensions */\n#define E1000_RXDADV_PKTTYPE_TCP\t0x00000100 /* TCP hdr present */\n#define E1000_RXDADV_PKTTYPE_UDP\t0x00000200 /* UDP hdr present */\n#define E1000_RXDADV_PKTTYPE_SCTP\t0x00000400 /* SCTP hdr present */\n#define E1000_RXDADV_PKTTYPE_NFS\t0x00000800 /* NFS hdr present */\n\n#define E1000_RXDADV_PKTTYPE_IPSEC_ESP\t0x00001000 /* IPSec ESP */\n#define E1000_RXDADV_PKTTYPE_IPSEC_AH\t0x00002000 /* IPSec AH */\n#define E1000_RXDADV_PKTTYPE_LINKSEC\t0x00004000 /* LinkSec Encap */\n#define E1000_RXDADV_PKTTYPE_ETQF\t0x00008000 /* PKTTYPE is ETQF index */\n#define E1000_RXDADV_PKTTYPE_ETQF_MASK\t0x00000070 /* ETQF has 8 indices */\n#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT\t4 /* Right-shift 4 bits */\n\n/* LinkSec results */\n/* Security Processing bit Indication */\n#define E1000_RXDADV_LNKSEC_STATUS_SECP\t\t0x00020000\n#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK\t0x18000000\n#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH\t0x08000000\n#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR\t0x10000000\n#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG\t0x18000000\n\n#define E1000_RXDADV_IPSEC_STATUS_SECP\t\t\t0x00020000\n#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK\t\t0x18000000\n#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL\t0x08000000\n#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH\t\t0x10000000\n#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED\t0x18000000\n\n/* Transmit Descriptor - Advanced */\nunion e1000_adv_tx_desc {\n\tstruct {\n\t\t__le64 buffer_addr; /* Address of descriptor's data buf */\n\t\t__le32 cmd_type_len;\n\t\t__le32 olinfo_status;\n\t} read;\n\tstruct {\n\t\t__le64 rsvd; /* Reserved */\n\t\t__le32 nxtseq_seed;\n\t\t__le32 status;\n\t} wb;\n};\n\n/* Adv Transmit Descriptor Config Masks */\n#define E1000_ADVTXD_DTYP_CTXT\t0x00200000 /* Advanced Context Descriptor */\n#define E1000_ADVTXD_DTYP_DATA\t0x00300000 /* Advanced Data Descriptor */\n#define E1000_ADVTXD_DCMD_EOP\t0x01000000 /* End of Packet */\n#define E1000_ADVTXD_DCMD_IFCS\t0x02000000 /* Insert FCS (Ethernet CRC) */\n#define E1000_ADVTXD_DCMD_RS\t0x08000000 /* Report Status */\n#define E1000_ADVTXD_DCMD_DDTYP_ISCSI\t0x10000000 /* DDP hdr type or iSCSI */\n#define E1000_ADVTXD_DCMD_DEXT\t0x20000000 /* Descriptor extension (1=Adv) */\n#define E1000_ADVTXD_DCMD_VLE\t0x40000000 /* VLAN pkt enable */\n#define E1000_ADVTXD_DCMD_TSE\t0x80000000 /* TCP Seg enable */\n#define E1000_ADVTXD_MAC_LINKSEC\t0x00040000 /* Apply LinkSec on pkt */\n#define E1000_ADVTXD_MAC_TSTAMP\t\t0x00080000 /* IEEE1588 Timestamp pkt */\n#define E1000_ADVTXD_STAT_SN_CRC\t0x00000002 /* NXTSEQ/SEED prsnt in WB */\n#define E1000_ADVTXD_IDX_SHIFT\t\t4 /* Adv desc Index shift */\n#define E1000_ADVTXD_POPTS_ISCO_1ST\t0x00000000 /* 1st TSO of iSCSI PDU */\n#define E1000_ADVTXD_POPTS_ISCO_MDL\t0x00000800 /* Middle TSO of iSCSI PDU */\n#define E1000_ADVTXD_POPTS_ISCO_LAST\t0x00001000 /* Last TSO of iSCSI PDU */\n/* 1st & Last TSO-full iSCSI PDU*/\n#define E1000_ADVTXD_POPTS_ISCO_FULL\t0x00001800\n#define E1000_ADVTXD_POPTS_IPSEC\t0x00000400 /* IPSec offload request */\n#define E1000_ADVTXD_PAYLEN_SHIFT\t14 /* Adv desc PAYLEN shift */\n\n/* Context descriptors */\nstruct e1000_adv_tx_context_desc {\n\t__le32 vlan_macip_lens;\n\t__le32 seqnum_seed;\n\t__le32 type_tucmd_mlhl;\n\t__le32 mss_l4len_idx;\n};\n\n#define E1000_ADVTXD_MACLEN_SHIFT\t9 /* Adv ctxt desc mac len shift */\n#define E1000_ADVTXD_VLAN_SHIFT\t\t16 /* Adv ctxt vlan tag shift */\n#define E1000_ADVTXD_TUCMD_IPV4\t\t0x00000400 /* IP Packet Type: 1=IPv4 */\n#define E1000_ADVTXD_TUCMD_IPV6\t\t0x00000000 /* IP Packet Type: 0=IPv6 */\n#define E1000_ADVTXD_TUCMD_L4T_UDP\t0x00000000 /* L4 Packet TYPE of UDP */\n#define E1000_ADVTXD_TUCMD_L4T_TCP\t0x00000800 /* L4 Packet TYPE of TCP */\n#define E1000_ADVTXD_TUCMD_L4T_SCTP\t0x00001000 /* L4 Packet TYPE of SCTP */\n#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP\t0x00002000 /* IPSec Type ESP */\n/* IPSec Encrypt Enable for ESP */\n#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN\t0x00004000\n/* Req requires Markers and CRC */\n#define E1000_ADVTXD_TUCMD_MKRREQ\t0x00002000\n#define E1000_ADVTXD_L4LEN_SHIFT\t8 /* Adv ctxt L4LEN shift */\n#define E1000_ADVTXD_MSS_SHIFT\t\t16 /* Adv ctxt MSS shift */\n/* Adv ctxt IPSec SA IDX mask */\n#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK\t0x000000FF\n/* Adv ctxt IPSec ESP len mask */\n#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK\t\t0x000000FF\n\n/* Additional Transmit Descriptor Control definitions */\n#define E1000_TXDCTL_QUEUE_ENABLE\t0x02000000 /* Ena specific Tx Queue */\n#define E1000_TXDCTL_SWFLSH\t\t0x04000000 /* Tx Desc. wbk flushing */\n/* Tx Queue Arbitration Priority 0=low, 1=high */\n#define E1000_TXDCTL_PRIORITY\t\t0x08000000\n\n/* Additional Receive Descriptor Control definitions */\n#define E1000_RXDCTL_QUEUE_ENABLE\t0x02000000 /* Ena specific Rx Queue */\n#define E1000_RXDCTL_SWFLSH\t\t0x04000000 /* Rx Desc. wbk flushing */\n\n/* Direct Cache Access (DCA) definitions */\n#define E1000_DCA_CTRL_DCA_ENABLE\t0x00000000 /* DCA Enable */\n#define E1000_DCA_CTRL_DCA_DISABLE\t0x00000001 /* DCA Disable */\n\n#define E1000_DCA_CTRL_DCA_MODE_CB1\t0x00 /* DCA Mode CB1 */\n#define E1000_DCA_CTRL_DCA_MODE_CB2\t0x02 /* DCA Mode CB2 */\n\n#define E1000_DCA_RXCTRL_CPUID_MASK\t0x0000001F /* Rx CPUID Mask */\n#define E1000_DCA_RXCTRL_DESC_DCA_EN\t(1 << 5) /* DCA Rx Desc enable */\n#define E1000_DCA_RXCTRL_HEAD_DCA_EN\t(1 << 6) /* DCA Rx Desc header ena */\n#define E1000_DCA_RXCTRL_DATA_DCA_EN\t(1 << 7) /* DCA Rx Desc payload ena */\n#define E1000_DCA_RXCTRL_DESC_RRO_EN\t(1 << 9) /* DCA Rx Desc Relax Order */\n\n#define E1000_DCA_TXCTRL_CPUID_MASK\t0x0000001F /* Tx CPUID Mask */\n#define E1000_DCA_TXCTRL_DESC_DCA_EN\t(1 << 5) /* DCA Tx Desc enable */\n#define E1000_DCA_TXCTRL_DESC_RRO_EN\t(1 << 9) /* Tx rd Desc Relax Order */\n#define E1000_DCA_TXCTRL_TX_WB_RO_EN\t(1 << 11) /* Tx Desc writeback RO bit */\n#define E1000_DCA_TXCTRL_DATA_RRO_EN\t(1 << 13) /* Tx rd data Relax Order */\n\n#define E1000_DCA_TXCTRL_CPUID_MASK_82576\t0xFF000000 /* Tx CPUID Mask */\n#define E1000_DCA_RXCTRL_CPUID_MASK_82576\t0xFF000000 /* Rx CPUID Mask */\n#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576\t24 /* Tx CPUID */\n#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576\t24 /* Rx CPUID */\n\n/* Additional interrupt register bit definitions */\n#define E1000_ICR_LSECPNS\t0x00000020 /* PN threshold - server */\n#define E1000_IMS_LSECPNS\tE1000_ICR_LSECPNS /* PN threshold - server */\n#define E1000_ICS_LSECPNS\tE1000_ICR_LSECPNS /* PN threshold - server */\n\n/* ETQF register bit definitions */\n#define E1000_ETQF_FILTER_ENABLE\t(1 << 26)\n#define E1000_ETQF_IMM_INT\t\t(1 << 29)\n#define E1000_ETQF_1588\t\t\t(1 << 30)\n#define E1000_ETQF_QUEUE_ENABLE\t\t(1 << 31)\n/*\n * ETQF filter list: one static filter per filter consumer. This is\n * to avoid filter collisions later. Add new filters\n * here!!\n *\n * Current filters:\n * EAPOL 802.1x (0x888e): Filter 0\n */\n#define E1000_ETQF_FILTER_EAPOL\t\t0\n\n#define E1000_FTQF_VF_BP\t\t0x00008000\n#define E1000_FTQF_1588_TIME_STAMP\t0x08000000\n#define E1000_FTQF_MASK\t\t\t0xF0000000\n#define E1000_FTQF_MASK_PROTO_BP\t0x10000000\n#define E1000_FTQF_MASK_SOURCE_ADDR_BP\t0x20000000\n#define E1000_FTQF_MASK_DEST_ADDR_BP\t0x40000000\n#define E1000_FTQF_MASK_SOURCE_PORT_BP\t0x80000000\n\n#define E1000_NVM_APME_82575\t\t0x0400\n#define MAX_NUM_VFS\t\t\t7\n\n#define E1000_DTXSWC_MAC_SPOOF_MASK\t0x000000FF /* Per VF MAC spoof cntrl */\n#define E1000_DTXSWC_VLAN_SPOOF_MASK\t0x0000FF00 /* Per VF VLAN spoof cntrl */\n#define E1000_DTXSWC_LLE_MASK\t\t0x00FF0000 /* Per VF Local LB enables */\n#define E1000_DTXSWC_VLAN_SPOOF_SHIFT\t8\n#define E1000_DTXSWC_LLE_SHIFT\t\t16\n#define E1000_DTXSWC_VMDQ_LOOPBACK_EN\t(1 << 31) /* global VF LB enable */\n\n/* Easy defines for setting default pool, would normally be left a zero */\n#define E1000_VT_CTL_DEFAULT_POOL_SHIFT\t7\n#define E1000_VT_CTL_DEFAULT_POOL_MASK\t(0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)\n\n/* Other useful VMD_CTL register defines */\n#define E1000_VT_CTL_IGNORE_MAC\t\t(1 << 28)\n#define E1000_VT_CTL_DISABLE_DEF_POOL\t(1 << 29)\n#define E1000_VT_CTL_VM_REPL_EN\t\t(1 << 30)\n\n/* Per VM Offload register setup */\n#define E1000_VMOLR_RLPML_MASK\t0x00003FFF /* Long Packet Maximum Length mask */\n#define E1000_VMOLR_LPE\t\t0x00010000 /* Accept Long packet */\n#define E1000_VMOLR_RSSE\t0x00020000 /* Enable RSS */\n#define E1000_VMOLR_AUPE\t0x01000000 /* Accept untagged packets */\n#define E1000_VMOLR_ROMPE\t0x02000000 /* Accept overflow multicast */\n#define E1000_VMOLR_ROPE\t0x04000000 /* Accept overflow unicast */\n#define E1000_VMOLR_BAM\t\t0x08000000 /* Accept Broadcast packets */\n#define E1000_VMOLR_MPME\t0x10000000 /* Multicast promiscuous mode */\n#define E1000_VMOLR_STRVLAN\t0x40000000 /* Vlan stripping enable */\n#define E1000_VMOLR_STRCRC\t0x80000000 /* CRC stripping enable */\n\n#define E1000_VMOLR_VPE\t\t0x00800000 /* VLAN promiscuous enable */\n#define E1000_VMOLR_UPE\t\t0x20000000 /* Unicast promisuous enable */\n#define E1000_DVMOLR_HIDVLAN\t0x20000000 /* Vlan hiding enable */\n#define E1000_DVMOLR_STRVLAN\t0x40000000 /* Vlan stripping enable */\n#define E1000_DVMOLR_STRCRC\t0x80000000 /* CRC stripping enable */\n\n#define E1000_PBRWAC_WALPB\t0x00000007 /* Wrap around event on LAN Rx PB */\n#define E1000_PBRWAC_PBE\t0x00000008 /* Rx packet buffer empty */\n\n#define E1000_VLVF_ARRAY_SIZE\t\t32\n#define E1000_VLVF_VLANID_MASK\t\t0x00000FFF\n#define E1000_VLVF_POOLSEL_SHIFT\t12\n#define E1000_VLVF_POOLSEL_MASK\t\t(0xFF << E1000_VLVF_POOLSEL_SHIFT)\n#define E1000_VLVF_LVLAN\t\t0x00100000\n#define E1000_VLVF_VLANID_ENABLE\t0x80000000\n\n#define E1000_VMVIR_VLANA_DEFAULT\t0x40000000 /* Always use default VLAN */\n#define E1000_VMVIR_VLANA_NEVER\t\t0x80000000 /* Never insert VLAN tag */\n\n#define E1000_VF_INIT_TIMEOUT\t200 /* Number of retries to clear RSTI */\n\n#define E1000_IOVCTL\t\t0x05BBC\n#define E1000_IOVCTL_REUSE_VFQ\t0x00000001\n\n#define E1000_RPLOLR_STRVLAN\t0x40000000\n#define E1000_RPLOLR_STRCRC\t0x80000000\n\n#define E1000_TCTL_EXT_COLD\t0x000FFC00\n#define E1000_TCTL_EXT_COLD_SHIFT\t10\n\n#define E1000_DTXCTL_8023LL\t0x0004\n#define E1000_DTXCTL_VLAN_ADDED\t0x0008\n#define E1000_DTXCTL_OOS_ENABLE\t0x0010\n#define E1000_DTXCTL_MDP_EN\t0x0020\n#define E1000_DTXCTL_SPOOF_INT\t0x0040\n\n#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT\t(1 << 14)\n\n#define ALL_QUEUES\t\t0xFFFF\n\n/* Rx packet buffer size defines */\n#define E1000_RXPBS_SIZE_MASK_82576\t0x0000007F\nvoid e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);\nvoid e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf);\nvoid e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);\ns32 e1000_init_nvm_params_82575(struct e1000_hw *hw);\ns32 e1000_init_hw_82575(struct e1000_hw *hw);\n\nenum e1000_promisc_type {\n\te1000_promisc_disabled = 0, /* all promisc modes disabled */\n\te1000_promisc_unicast = 1, /* unicast promiscuous enabled */\n\te1000_promisc_multicast = 2, /* multicast promiscuous enabled */\n\te1000_promisc_enabled = 3, /* both uni and multicast promisc */\n\te1000_num_promisc_types\n};\n\nvoid e1000_vfta_set_vf(struct e1000_hw *, u16, bool);\nvoid e1000_rlpml_set_vf(struct e1000_hw *, u16);\ns32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type);\nu16 e1000_rxpbs_adjust_82580(u32 data);\ns32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data);\ns32 e1000_set_eee_i350(struct e1000_hw *);\ns32 e1000_set_eee_i354(struct e1000_hw *);\ns32 e1000_get_eee_status_i354(struct e1000_hw *, bool *);\ns32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw);\n\n/* I2C SDA and SCL timing parameters for standard mode */\n#define E1000_I2C_T_HD_STA\t4\n#define E1000_I2C_T_LOW\t\t5\n#define E1000_I2C_T_HIGH\t4\n#define E1000_I2C_T_SU_STA\t5\n#define E1000_I2C_T_HD_DATA\t5\n#define E1000_I2C_T_SU_DATA\t1\n#define E1000_I2C_T_RISE\t1\n#define E1000_I2C_T_FALL\t1\n#define E1000_I2C_T_SU_STO\t4\n#define E1000_I2C_T_BUF\t\t5\n\ns32 e1000_set_i2c_bb(struct e1000_hw *hw);\ns32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t\tu8 dev_addr, u8 *data);\ns32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data);\nvoid e1000_i2c_bus_clear(struct e1000_hw *hw);\n#endif /* _E1000_82575_H_ */\n" }, { "path": "drivers/net/e1000/base/e1000_api.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"e1000_api.h\"\n\n/**\n * e1000_init_mac_params - Initialize MAC function pointers\n * @hw: pointer to the HW structure\n *\n * This function initializes the function pointers for the MAC\n * set of functions. Called by drivers or by e1000_setup_init_funcs.\n **/\ns32 e1000_init_mac_params(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tif (hw->mac.ops.init_params) {\n\t\tret_val = hw->mac.ops.init_params(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"MAC Initialization Error\\n\");\n\t\t\tgoto out;\n\t\t}\n\t} else {\n\t\tDEBUGOUT(\"mac.init_mac_params was NULL\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_nvm_params - Initialize NVM function pointers\n * @hw: pointer to the HW structure\n *\n * This function initializes the function pointers for the NVM\n * set of functions. Called by drivers or by e1000_setup_init_funcs.\n **/\ns32 e1000_init_nvm_params(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tif (hw->nvm.ops.init_params) {\n\t\tret_val = hw->nvm.ops.init_params(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Initialization Error\\n\");\n\t\t\tgoto out;\n\t\t}\n\t} else {\n\t\tDEBUGOUT(\"nvm.init_nvm_params was NULL\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_phy_params - Initialize PHY function pointers\n * @hw: pointer to the HW structure\n *\n * This function initializes the function pointers for the PHY\n * set of functions. Called by drivers or by e1000_setup_init_funcs.\n **/\ns32 e1000_init_phy_params(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tif (hw->phy.ops.init_params) {\n\t\tret_val = hw->phy.ops.init_params(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"PHY Initialization Error\\n\");\n\t\t\tgoto out;\n\t\t}\n\t} else {\n\t\tDEBUGOUT(\"phy.init_phy_params was NULL\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_mbx_params - Initialize mailbox function pointers\n * @hw: pointer to the HW structure\n *\n * This function initializes the function pointers for the PHY\n * set of functions. Called by drivers or by e1000_setup_init_funcs.\n **/\ns32 e1000_init_mbx_params(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tif (hw->mbx.ops.init_params) {\n\t\tret_val = hw->mbx.ops.init_params(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Mailbox Initialization Error\\n\");\n\t\t\tgoto out;\n\t\t}\n\t} else {\n\t\tDEBUGOUT(\"mbx.init_mbx_params was NULL\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_set_mac_type - Sets MAC type\n * @hw: pointer to the HW structure\n *\n * This function sets the mac type of the adapter based on the\n * device ID stored in the hw structure.\n * MUST BE FIRST FUNCTION CALLED (explicitly or through\n * e1000_setup_init_funcs()).\n **/\ns32 e1000_set_mac_type(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_set_mac_type\");\n\n\tswitch (hw->device_id) {\n\tcase E1000_DEV_ID_82542:\n\t\tmac->type = e1000_82542;\n\t\tbreak;\n\tcase E1000_DEV_ID_82543GC_FIBER:\n\tcase E1000_DEV_ID_82543GC_COPPER:\n\t\tmac->type = e1000_82543;\n\t\tbreak;\n\tcase E1000_DEV_ID_82544EI_COPPER:\n\tcase E1000_DEV_ID_82544EI_FIBER:\n\tcase E1000_DEV_ID_82544GC_COPPER:\n\tcase E1000_DEV_ID_82544GC_LOM:\n\t\tmac->type = e1000_82544;\n\t\tbreak;\n\tcase E1000_DEV_ID_82540EM:\n\tcase E1000_DEV_ID_82540EM_LOM:\n\tcase E1000_DEV_ID_82540EP:\n\tcase E1000_DEV_ID_82540EP_LOM:\n\tcase E1000_DEV_ID_82540EP_LP:\n\t\tmac->type = e1000_82540;\n\t\tbreak;\n\tcase E1000_DEV_ID_82545EM_COPPER:\n\tcase E1000_DEV_ID_82545EM_FIBER:\n\t\tmac->type = e1000_82545;\n\t\tbreak;\n\tcase E1000_DEV_ID_82545GM_COPPER:\n\tcase E1000_DEV_ID_82545GM_FIBER:\n\tcase E1000_DEV_ID_82545GM_SERDES:\n\t\tmac->type = e1000_82545_rev_3;\n\t\tbreak;\n\tcase E1000_DEV_ID_82546EB_COPPER:\n\tcase E1000_DEV_ID_82546EB_FIBER:\n\tcase E1000_DEV_ID_82546EB_QUAD_COPPER:\n\t\tmac->type = e1000_82546;\n\t\tbreak;\n\tcase E1000_DEV_ID_82546GB_COPPER:\n\tcase E1000_DEV_ID_82546GB_FIBER:\n\tcase E1000_DEV_ID_82546GB_SERDES:\n\tcase E1000_DEV_ID_82546GB_PCIE:\n\tcase E1000_DEV_ID_82546GB_QUAD_COPPER:\n\tcase E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:\n\t\tmac->type = e1000_82546_rev_3;\n\t\tbreak;\n\tcase E1000_DEV_ID_82541EI:\n\tcase E1000_DEV_ID_82541EI_MOBILE:\n\tcase E1000_DEV_ID_82541ER_LOM:\n\t\tmac->type = e1000_82541;\n\t\tbreak;\n\tcase E1000_DEV_ID_82541ER:\n\tcase E1000_DEV_ID_82541GI:\n\tcase E1000_DEV_ID_82541GI_LF:\n\tcase E1000_DEV_ID_82541GI_MOBILE:\n\t\tmac->type = e1000_82541_rev_2;\n\t\tbreak;\n\tcase E1000_DEV_ID_82547EI:\n\tcase E1000_DEV_ID_82547EI_MOBILE:\n\t\tmac->type = e1000_82547;\n\t\tbreak;\n\tcase E1000_DEV_ID_82547GI:\n\t\tmac->type = e1000_82547_rev_2;\n\t\tbreak;\n\tcase E1000_DEV_ID_82571EB_COPPER:\n\tcase E1000_DEV_ID_82571EB_FIBER:\n\tcase E1000_DEV_ID_82571EB_SERDES:\n\tcase E1000_DEV_ID_82571EB_SERDES_DUAL:\n\tcase E1000_DEV_ID_82571EB_SERDES_QUAD:\n\tcase E1000_DEV_ID_82571EB_QUAD_COPPER:\n\tcase E1000_DEV_ID_82571PT_QUAD_COPPER:\n\tcase E1000_DEV_ID_82571EB_QUAD_FIBER:\n\tcase E1000_DEV_ID_82571EB_QUAD_COPPER_LP:\n\t\tmac->type = e1000_82571;\n\t\tbreak;\n\tcase E1000_DEV_ID_82572EI:\n\tcase E1000_DEV_ID_82572EI_COPPER:\n\tcase E1000_DEV_ID_82572EI_FIBER:\n\tcase E1000_DEV_ID_82572EI_SERDES:\n\t\tmac->type = e1000_82572;\n\t\tbreak;\n\tcase E1000_DEV_ID_82573E:\n\tcase E1000_DEV_ID_82573E_IAMT:\n\tcase E1000_DEV_ID_82573L:\n\t\tmac->type = e1000_82573;\n\t\tbreak;\n\tcase E1000_DEV_ID_82574L:\n\tcase E1000_DEV_ID_82574LA:\n\t\tmac->type = e1000_82574;\n\t\tbreak;\n\tcase E1000_DEV_ID_82583V:\n\t\tmac->type = e1000_82583;\n\t\tbreak;\n\tcase E1000_DEV_ID_80003ES2LAN_COPPER_DPT:\n\tcase E1000_DEV_ID_80003ES2LAN_SERDES_DPT:\n\tcase E1000_DEV_ID_80003ES2LAN_COPPER_SPT:\n\tcase E1000_DEV_ID_80003ES2LAN_SERDES_SPT:\n\t\tmac->type = e1000_80003es2lan;\n\t\tbreak;\n\tcase E1000_DEV_ID_ICH8_IFE:\n\tcase E1000_DEV_ID_ICH8_IFE_GT:\n\tcase E1000_DEV_ID_ICH8_IFE_G:\n\tcase E1000_DEV_ID_ICH8_IGP_M:\n\tcase E1000_DEV_ID_ICH8_IGP_M_AMT:\n\tcase E1000_DEV_ID_ICH8_IGP_AMT:\n\tcase E1000_DEV_ID_ICH8_IGP_C:\n\tcase E1000_DEV_ID_ICH8_82567V_3:\n\t\tmac->type = e1000_ich8lan;\n\t\tbreak;\n\tcase E1000_DEV_ID_ICH9_IFE:\n\tcase E1000_DEV_ID_ICH9_IFE_GT:\n\tcase E1000_DEV_ID_ICH9_IFE_G:\n\tcase E1000_DEV_ID_ICH9_IGP_M:\n\tcase E1000_DEV_ID_ICH9_IGP_M_AMT:\n\tcase E1000_DEV_ID_ICH9_IGP_M_V:\n\tcase E1000_DEV_ID_ICH9_IGP_AMT:\n\tcase E1000_DEV_ID_ICH9_BM:\n\tcase E1000_DEV_ID_ICH9_IGP_C:\n\tcase E1000_DEV_ID_ICH10_R_BM_LM:\n\tcase E1000_DEV_ID_ICH10_R_BM_LF:\n\tcase E1000_DEV_ID_ICH10_R_BM_V:\n\t\tmac->type = e1000_ich9lan;\n\t\tbreak;\n\tcase E1000_DEV_ID_ICH10_D_BM_LM:\n\tcase E1000_DEV_ID_ICH10_D_BM_LF:\n\tcase E1000_DEV_ID_ICH10_D_BM_V:\n\t\tmac->type = e1000_ich10lan;\n\t\tbreak;\n\tcase E1000_DEV_ID_PCH_D_HV_DM:\n\tcase E1000_DEV_ID_PCH_D_HV_DC:\n\tcase E1000_DEV_ID_PCH_M_HV_LM:\n\tcase E1000_DEV_ID_PCH_M_HV_LC:\n\t\tmac->type = e1000_pchlan;\n\t\tbreak;\n\tcase E1000_DEV_ID_PCH2_LV_LM:\n\tcase E1000_DEV_ID_PCH2_LV_V:\n\t\tmac->type = e1000_pch2lan;\n\t\tbreak;\n\tcase E1000_DEV_ID_PCH_LPT_I217_LM:\n\tcase E1000_DEV_ID_PCH_LPT_I217_V:\n\tcase E1000_DEV_ID_PCH_LPTLP_I218_LM:\n\tcase E1000_DEV_ID_PCH_LPTLP_I218_V:\n\t\tmac->type = e1000_pch_lpt;\n\t\tbreak;\n\tcase E1000_DEV_ID_82575EB_COPPER:\n\tcase E1000_DEV_ID_82575EB_FIBER_SERDES:\n\tcase E1000_DEV_ID_82575GB_QUAD_COPPER:\n\t\tmac->type = e1000_82575;\n\t\tbreak;\n\tcase E1000_DEV_ID_82576:\n\tcase E1000_DEV_ID_82576_FIBER:\n\tcase E1000_DEV_ID_82576_SERDES:\n\tcase E1000_DEV_ID_82576_QUAD_COPPER:\n\tcase E1000_DEV_ID_82576_QUAD_COPPER_ET2:\n\tcase E1000_DEV_ID_82576_NS:\n\tcase E1000_DEV_ID_82576_NS_SERDES:\n\tcase E1000_DEV_ID_82576_SERDES_QUAD:\n\t\tmac->type = e1000_82576;\n\t\tbreak;\n\tcase E1000_DEV_ID_82580_COPPER:\n\tcase E1000_DEV_ID_82580_FIBER:\n\tcase E1000_DEV_ID_82580_SERDES:\n\tcase E1000_DEV_ID_82580_SGMII:\n\tcase E1000_DEV_ID_82580_COPPER_DUAL:\n\tcase E1000_DEV_ID_82580_QUAD_FIBER:\n\tcase E1000_DEV_ID_DH89XXCC_SGMII:\n\tcase E1000_DEV_ID_DH89XXCC_SERDES:\n\tcase E1000_DEV_ID_DH89XXCC_BACKPLANE:\n\tcase E1000_DEV_ID_DH89XXCC_SFP:\n\t\tmac->type = e1000_82580;\n\t\tbreak;\n\tcase E1000_DEV_ID_I350_COPPER:\n\tcase E1000_DEV_ID_I350_FIBER:\n\tcase E1000_DEV_ID_I350_SERDES:\n\tcase E1000_DEV_ID_I350_SGMII:\n\tcase E1000_DEV_ID_I350_DA4:\n\t\tmac->type = e1000_i350;\n\t\tbreak;\n\tcase E1000_DEV_ID_I210_COPPER_FLASHLESS:\n\tcase E1000_DEV_ID_I210_SERDES_FLASHLESS:\n\tcase E1000_DEV_ID_I210_COPPER:\n\tcase E1000_DEV_ID_I210_COPPER_OEM1:\n\tcase E1000_DEV_ID_I210_COPPER_IT:\n\tcase E1000_DEV_ID_I210_FIBER:\n\tcase E1000_DEV_ID_I210_SERDES:\n\tcase E1000_DEV_ID_I210_SGMII:\n\t\tmac->type = e1000_i210;\n\t\tbreak;\n\tcase E1000_DEV_ID_I211_COPPER:\n\t\tmac->type = e1000_i211;\n\t\tbreak;\n\tcase E1000_DEV_ID_82576_VF:\n\tcase E1000_DEV_ID_82576_VF_HV:\n\t\tmac->type = e1000_vfadapt;\n\t\tbreak;\n\tcase E1000_DEV_ID_I350_VF:\n\tcase E1000_DEV_ID_I350_VF_HV:\n\t\tmac->type = e1000_vfadapt_i350;\n\t\tbreak;\n\n\tcase E1000_DEV_ID_I354_BACKPLANE_1GBPS:\n\tcase E1000_DEV_ID_I354_SGMII:\n\tcase E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:\n\t\tmac->type = e1000_i354;\n\t\tbreak;\n\tdefault:\n\t\t/* Should never have loaded on this device */\n\t\tret_val = -E1000_ERR_MAC_INIT;\n\t\tbreak;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_init_funcs - Initializes function pointers\n * @hw: pointer to the HW structure\n * @init_device: true will initialize the rest of the function pointers\n *\t\t getting the device ready for use. false will only set\n *\t\t MAC type and the function pointers for the other init\n *\t\t functions. Passing false will not generate any hardware\n *\t\t reads or writes.\n *\n * This function must be called by a driver in order to use the rest\n * of the 'shared' code files. Called by drivers only.\n **/\ns32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)\n{\n\ts32 ret_val;\n\n\t/* Can't do much good without knowing the MAC type. */\n\tret_val = e1000_set_mac_type(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"ERROR: MAC type could not be set properly.\\n\");\n\t\tgoto out;\n\t}\n\n\tif (!hw->hw_addr) {\n\t\tDEBUGOUT(\"ERROR: Registers not mapped\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * Init function pointers to generic implementations. We do this first\n\t * allowing a driver module to override it afterward.\n\t */\n\te1000_init_mac_ops_generic(hw);\n\te1000_init_phy_ops_generic(hw);\n\te1000_init_nvm_ops_generic(hw);\n\te1000_init_mbx_ops_generic(hw);\n\n\t/*\n\t * Set up the init function pointers. These are functions within the\n\t * adapter family file that sets up function pointers for the rest of\n\t * the functions in that family.\n\t */\n\tswitch (hw->mac.type) {\n\tcase e1000_82542:\n\t\te1000_init_function_pointers_82542(hw);\n\t\tbreak;\n\tcase e1000_82543:\n\tcase e1000_82544:\n\t\te1000_init_function_pointers_82543(hw);\n\t\tbreak;\n\tcase e1000_82540:\n\tcase e1000_82545:\n\tcase e1000_82545_rev_3:\n\tcase e1000_82546:\n\tcase e1000_82546_rev_3:\n\t\te1000_init_function_pointers_82540(hw);\n\t\tbreak;\n\tcase e1000_82541:\n\tcase e1000_82541_rev_2:\n\tcase e1000_82547:\n\tcase e1000_82547_rev_2:\n\t\te1000_init_function_pointers_82541(hw);\n\t\tbreak;\n\tcase e1000_82571:\n\tcase e1000_82572:\n\tcase e1000_82573:\n\tcase e1000_82574:\n\tcase e1000_82583:\n\t\te1000_init_function_pointers_82571(hw);\n\t\tbreak;\n\tcase e1000_80003es2lan:\n\t\te1000_init_function_pointers_80003es2lan(hw);\n\t\tbreak;\n\tcase e1000_ich8lan:\n\tcase e1000_ich9lan:\n\tcase e1000_ich10lan:\n\tcase e1000_pchlan:\n\tcase e1000_pch2lan:\n\tcase e1000_pch_lpt:\n\t\te1000_init_function_pointers_ich8lan(hw);\n\t\tbreak;\n\tcase e1000_82575:\n\tcase e1000_82576:\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\te1000_init_function_pointers_82575(hw);\n\t\tbreak;\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\te1000_init_function_pointers_i210(hw);\n\t\tbreak;\n\tcase e1000_vfadapt:\n\t\te1000_init_function_pointers_vf(hw);\n\t\tbreak;\n\tcase e1000_vfadapt_i350:\n\t\te1000_init_function_pointers_vf(hw);\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\"Hardware not supported\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t\tbreak;\n\t}\n\n\t/*\n\t * Initialize the rest of the function pointers. These require some\n\t * register reads/writes in some cases.\n\t */\n\tif (!(ret_val) && init_device) {\n\t\tret_val = e1000_init_mac_params(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tret_val = e1000_init_nvm_params(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tret_val = e1000_init_phy_params(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tret_val = e1000_init_mbx_params(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_get_bus_info - Obtain bus information for adapter\n * @hw: pointer to the HW structure\n *\n * This will obtain information about the HW bus for which the\n * adapter is attached and stores it in the hw structure. This is a\n * function pointer entry point called by drivers.\n **/\ns32 e1000_get_bus_info(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.get_bus_info)\n\t\treturn hw->mac.ops.get_bus_info(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_clear_vfta - Clear VLAN filter table\n * @hw: pointer to the HW structure\n *\n * This clears the VLAN filter table on the adapter. This is a function\n * pointer entry point called by drivers.\n **/\nvoid e1000_clear_vfta(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.clear_vfta)\n\t\thw->mac.ops.clear_vfta(hw);\n}\n\n/**\n * e1000_write_vfta - Write value to VLAN filter table\n * @hw: pointer to the HW structure\n * @offset: the 32-bit offset in which to write the value to.\n * @value: the 32-bit value to write at location offset.\n *\n * This writes a 32-bit value to a 32-bit offset in the VLAN filter\n * table. This is a function pointer entry point called by drivers.\n **/\nvoid e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)\n{\n\tif (hw->mac.ops.write_vfta)\n\t\thw->mac.ops.write_vfta(hw, offset, value);\n}\n\n/**\n * e1000_update_mc_addr_list - Update Multicast addresses\n * @hw: pointer to the HW structure\n * @mc_addr_list: array of multicast addresses to program\n * @mc_addr_count: number of multicast addresses to program\n *\n * Updates the Multicast Table Array.\n * The caller must have a packed mc_addr_list of multicast addresses.\n **/\nvoid e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,\n\t\t\t u32 mc_addr_count)\n{\n\tif (hw->mac.ops.update_mc_addr_list)\n\t\thw->mac.ops.update_mc_addr_list(hw, mc_addr_list,\n\t\t\t\t\t\tmc_addr_count);\n}\n\n/**\n * e1000_force_mac_fc - Force MAC flow control\n * @hw: pointer to the HW structure\n *\n * Force the MAC's flow control settings. Currently no func pointer exists\n * and all implementations are handled in the generic version of this\n * function.\n **/\ns32 e1000_force_mac_fc(struct e1000_hw *hw)\n{\n\treturn e1000_force_mac_fc_generic(hw);\n}\n\n/**\n * e1000_check_for_link - Check/Store link connection\n * @hw: pointer to the HW structure\n *\n * This checks the link condition of the adapter and stores the\n * results in the hw->mac structure. This is a function pointer entry\n * point called by drivers.\n **/\ns32 e1000_check_for_link(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.check_for_link)\n\t\treturn hw->mac.ops.check_for_link(hw);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_check_mng_mode - Check management mode\n * @hw: pointer to the HW structure\n *\n * This checks if the adapter has manageability enabled.\n * This is a function pointer entry point called by drivers.\n **/\nbool e1000_check_mng_mode(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.check_mng_mode)\n\t\treturn hw->mac.ops.check_mng_mode(hw);\n\n\treturn false;\n}\n\n/**\n * e1000_mng_write_dhcp_info - Writes DHCP info to host interface\n * @hw: pointer to the HW structure\n * @buffer: pointer to the host interface\n * @length: size of the buffer\n *\n * Writes the DHCP information to the host interface.\n **/\ns32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)\n{\n\treturn e1000_mng_write_dhcp_info_generic(hw, buffer, length);\n}\n\n/**\n * e1000_reset_hw - Reset hardware\n * @hw: pointer to the HW structure\n *\n * This resets the hardware into a known state. This is a function pointer\n * entry point called by drivers.\n **/\ns32 e1000_reset_hw(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.reset_hw)\n\t\treturn hw->mac.ops.reset_hw(hw);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_init_hw - Initialize hardware\n * @hw: pointer to the HW structure\n *\n * This inits the hardware readying it for operation. This is a function\n * pointer entry point called by drivers.\n **/\ns32 e1000_init_hw(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.init_hw)\n\t\treturn hw->mac.ops.init_hw(hw);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_setup_link - Configures link and flow control\n * @hw: pointer to the HW structure\n *\n * This configures link and flow control settings for the adapter. This\n * is a function pointer entry point called by drivers. While modules can\n * also call this, they probably call their own version of this function.\n **/\ns32 e1000_setup_link(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.setup_link)\n\t\treturn hw->mac.ops.setup_link(hw);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_get_speed_and_duplex - Returns current speed and duplex\n * @hw: pointer to the HW structure\n * @speed: pointer to a 16-bit value to store the speed\n * @duplex: pointer to a 16-bit value to store the duplex.\n *\n * This returns the speed and duplex of the adapter in the two 'out'\n * variables passed in. This is a function pointer entry point called\n * by drivers.\n **/\ns32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)\n{\n\tif (hw->mac.ops.get_link_up_info)\n\t\treturn hw->mac.ops.get_link_up_info(hw, speed, duplex);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_setup_led - Configures SW controllable LED\n * @hw: pointer to the HW structure\n *\n * This prepares the SW controllable LED for use and saves the current state\n * of the LED so it can be later restored. This is a function pointer entry\n * point called by drivers.\n **/\ns32 e1000_setup_led(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.setup_led)\n\t\treturn hw->mac.ops.setup_led(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_cleanup_led - Restores SW controllable LED\n * @hw: pointer to the HW structure\n *\n * This restores the SW controllable LED to the value saved off by\n * e1000_setup_led. This is a function pointer entry point called by drivers.\n **/\ns32 e1000_cleanup_led(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.cleanup_led)\n\t\treturn hw->mac.ops.cleanup_led(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_blink_led - Blink SW controllable LED\n * @hw: pointer to the HW structure\n *\n * This starts the adapter LED blinking. Request the LED to be setup first\n * and cleaned up after. This is a function pointer entry point called by\n * drivers.\n **/\ns32 e1000_blink_led(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.blink_led)\n\t\treturn hw->mac.ops.blink_led(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_id_led_init - store LED configurations in SW\n * @hw: pointer to the HW structure\n *\n * Initializes the LED config in SW. This is a function pointer entry point\n * called by drivers.\n **/\ns32 e1000_id_led_init(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.id_led_init)\n\t\treturn hw->mac.ops.id_led_init(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_led_on - Turn on SW controllable LED\n * @hw: pointer to the HW structure\n *\n * Turns the SW defined LED on. This is a function pointer entry point\n * called by drivers.\n **/\ns32 e1000_led_on(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.led_on)\n\t\treturn hw->mac.ops.led_on(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_led_off - Turn off SW controllable LED\n * @hw: pointer to the HW structure\n *\n * Turns the SW defined LED off. This is a function pointer entry point\n * called by drivers.\n **/\ns32 e1000_led_off(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.led_off)\n\t\treturn hw->mac.ops.led_off(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_reset_adaptive - Reset adaptive IFS\n * @hw: pointer to the HW structure\n *\n * Resets the adaptive IFS. Currently no func pointer exists and all\n * implementations are handled in the generic version of this function.\n **/\nvoid e1000_reset_adaptive(struct e1000_hw *hw)\n{\n\te1000_reset_adaptive_generic(hw);\n}\n\n/**\n * e1000_update_adaptive - Update adaptive IFS\n * @hw: pointer to the HW structure\n *\n * Updates adapter IFS. Currently no func pointer exists and all\n * implementations are handled in the generic version of this function.\n **/\nvoid e1000_update_adaptive(struct e1000_hw *hw)\n{\n\te1000_update_adaptive_generic(hw);\n}\n\n/**\n * e1000_disable_pcie_master - Disable PCI-Express master access\n * @hw: pointer to the HW structure\n *\n * Disables PCI-Express master access and verifies there are no pending\n * requests. Currently no func pointer exists and all implementations are\n * handled in the generic version of this function.\n **/\ns32 e1000_disable_pcie_master(struct e1000_hw *hw)\n{\n\treturn e1000_disable_pcie_master_generic(hw);\n}\n\n/**\n * e1000_config_collision_dist - Configure collision distance\n * @hw: pointer to the HW structure\n *\n * Configures the collision distance to the default value and is used\n * during link setup.\n **/\nvoid e1000_config_collision_dist(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.config_collision_dist)\n\t\thw->mac.ops.config_collision_dist(hw);\n}\n\n/**\n * e1000_rar_set - Sets a receive address register\n * @hw: pointer to the HW structure\n * @addr: address to set the RAR to\n * @index: the RAR to set\n *\n * Sets a Receive Address Register (RAR) to the specified address.\n **/\nvoid e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)\n{\n\tif (hw->mac.ops.rar_set)\n\t\thw->mac.ops.rar_set(hw, addr, index);\n}\n\n/**\n * e1000_validate_mdi_setting - Ensures valid MDI/MDIX SW state\n * @hw: pointer to the HW structure\n *\n * Ensures that the MDI/MDIX SW state is valid.\n **/\ns32 e1000_validate_mdi_setting(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.validate_mdi_setting)\n\t\treturn hw->mac.ops.validate_mdi_setting(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_hash_mc_addr - Determines address location in multicast table\n * @hw: pointer to the HW structure\n * @mc_addr: Multicast address to hash.\n *\n * This hashes an address to determine its location in the multicast\n * table. Currently no func pointer exists and all implementations\n * are handled in the generic version of this function.\n **/\nu32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)\n{\n\treturn e1000_hash_mc_addr_generic(hw, mc_addr);\n}\n\n/**\n * e1000_enable_tx_pkt_filtering - Enable packet filtering on TX\n * @hw: pointer to the HW structure\n *\n * Enables packet filtering on transmit packets if manageability is enabled\n * and host interface is enabled.\n * Currently no func pointer exists and all implementations are handled in the\n * generic version of this function.\n **/\nbool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)\n{\n\treturn e1000_enable_tx_pkt_filtering_generic(hw);\n}\n\n/**\n * e1000_mng_host_if_write - Writes to the manageability host interface\n * @hw: pointer to the HW structure\n * @buffer: pointer to the host interface buffer\n * @length: size of the buffer\n * @offset: location in the buffer to write to\n * @sum: sum of the data (not checksum)\n *\n * This function writes the buffer content at the offset given on the host if.\n * It also does alignment considerations to do the writes in most efficient\n * way. Also fills up the sum of the buffer in *buffer parameter.\n **/\ns32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,\n\t\t\t u16 offset, u8 *sum)\n{\n\treturn e1000_mng_host_if_write_generic(hw, buffer, length, offset, sum);\n}\n\n/**\n * e1000_mng_write_cmd_header - Writes manageability command header\n * @hw: pointer to the HW structure\n * @hdr: pointer to the host interface command header\n *\n * Writes the command header after does the checksum calculation.\n **/\ns32 e1000_mng_write_cmd_header(struct e1000_hw *hw,\n\t\t\t struct e1000_host_mng_command_header *hdr)\n{\n\treturn e1000_mng_write_cmd_header_generic(hw, hdr);\n}\n\n/**\n * e1000_mng_enable_host_if - Checks host interface is enabled\n * @hw: pointer to the HW structure\n *\n * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND\n *\n * This function checks whether the HOST IF is enabled for command operation\n * and also checks whether the previous command is completed. It busy waits\n * in case of previous command is not completed.\n **/\ns32 e1000_mng_enable_host_if(struct e1000_hw *hw)\n{\n\treturn e1000_mng_enable_host_if_generic(hw);\n}\n\n/**\n * e1000_check_reset_block - Verifies PHY can be reset\n * @hw: pointer to the HW structure\n *\n * Checks if the PHY is in a state that can be reset or if manageability\n * has it tied up. This is a function pointer entry point called by drivers.\n **/\ns32 e1000_check_reset_block(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.check_reset_block)\n\t\treturn hw->phy.ops.check_reset_block(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_phy_reg - Reads PHY register\n * @hw: pointer to the HW structure\n * @offset: the register to read\n * @data: the buffer to store the 16-bit read.\n *\n * Reads the PHY register and returns the value in data.\n * This is a function pointer entry point called by drivers.\n **/\ns32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\tif (hw->phy.ops.read_reg)\n\t\treturn hw->phy.ops.read_reg(hw, offset, data);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_phy_reg - Writes PHY register\n * @hw: pointer to the HW structure\n * @offset: the register to write\n * @data: the value to write.\n *\n * Writes the PHY register at offset with the value in data.\n * This is a function pointer entry point called by drivers.\n **/\ns32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\tif (hw->phy.ops.write_reg)\n\t\treturn hw->phy.ops.write_reg(hw, offset, data);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_release_phy - Generic release PHY\n * @hw: pointer to the HW structure\n *\n * Return if silicon family does not require a semaphore when accessing the\n * PHY.\n **/\nvoid e1000_release_phy(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.release)\n\t\thw->phy.ops.release(hw);\n}\n\n/**\n * e1000_acquire_phy - Generic acquire PHY\n * @hw: pointer to the HW structure\n *\n * Return success if silicon family does not require a semaphore when\n * accessing the PHY.\n **/\ns32 e1000_acquire_phy(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.acquire)\n\t\treturn hw->phy.ops.acquire(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_cfg_on_link_up - Configure PHY upon link up\n * @hw: pointer to the HW structure\n **/\ns32 e1000_cfg_on_link_up(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.cfg_on_link_up)\n\t\treturn hw->phy.ops.cfg_on_link_up(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_kmrn_reg - Reads register using Kumeran interface\n * @hw: pointer to the HW structure\n * @offset: the register to read\n * @data: the location to store the 16-bit value read.\n *\n * Reads a register out of the Kumeran interface. Currently no func pointer\n * exists and all implementations are handled in the generic version of\n * this function.\n **/\ns32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn e1000_read_kmrn_reg_generic(hw, offset, data);\n}\n\n/**\n * e1000_write_kmrn_reg - Writes register using Kumeran interface\n * @hw: pointer to the HW structure\n * @offset: the register to write\n * @data: the value to write.\n *\n * Writes a register to the Kumeran interface. Currently no func pointer\n * exists and all implementations are handled in the generic version of\n * this function.\n **/\ns32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn e1000_write_kmrn_reg_generic(hw, offset, data);\n}\n\n/**\n * e1000_get_cable_length - Retrieves cable length estimation\n * @hw: pointer to the HW structure\n *\n * This function estimates the cable length and stores them in\n * hw->phy.min_length and hw->phy.max_length. This is a function pointer\n * entry point called by drivers.\n **/\ns32 e1000_get_cable_length(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.get_cable_length)\n\t\treturn hw->phy.ops.get_cable_length(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_phy_info - Retrieves PHY information from registers\n * @hw: pointer to the HW structure\n *\n * This function gets some information from various PHY registers and\n * populates hw->phy values with it. This is a function pointer entry\n * point called by drivers.\n **/\ns32 e1000_get_phy_info(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.get_info)\n\t\treturn hw->phy.ops.get_info(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_hw_reset - Hard PHY reset\n * @hw: pointer to the HW structure\n *\n * Performs a hard PHY reset. This is a function pointer entry point called\n * by drivers.\n **/\ns32 e1000_phy_hw_reset(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.reset)\n\t\treturn hw->phy.ops.reset(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_commit - Soft PHY reset\n * @hw: pointer to the HW structure\n *\n * Performs a soft PHY reset on those that apply. This is a function pointer\n * entry point called by drivers.\n **/\ns32 e1000_phy_commit(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.commit)\n\t\treturn hw->phy.ops.commit(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_d0_lplu_state - Sets low power link up state for D0\n * @hw: pointer to the HW structure\n * @active: boolean used to enable/disable lplu\n *\n * Success returns 0, Failure returns 1\n *\n * The low power link up (lplu) state is set to the power management level D0\n * and SmartSpeed is disabled when active is true, else clear lplu for D0\n * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU\n * is used during Dx states where the power conservation is most important.\n * During driver activity, SmartSpeed should be enabled so performance is\n * maintained. This is a function pointer entry point called by drivers.\n **/\ns32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)\n{\n\tif (hw->phy.ops.set_d0_lplu_state)\n\t\treturn hw->phy.ops.set_d0_lplu_state(hw, active);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_d3_lplu_state - Sets low power link up state for D3\n * @hw: pointer to the HW structure\n * @active: boolean used to enable/disable lplu\n *\n * Success returns 0, Failure returns 1\n *\n * The low power link up (lplu) state is set to the power management level D3\n * and SmartSpeed is disabled when active is true, else clear lplu for D3\n * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU\n * is used during Dx states where the power conservation is most important.\n * During driver activity, SmartSpeed should be enabled so performance is\n * maintained. This is a function pointer entry point called by drivers.\n **/\ns32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)\n{\n\tif (hw->phy.ops.set_d3_lplu_state)\n\t\treturn hw->phy.ops.set_d3_lplu_state(hw, active);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_mac_addr - Reads MAC address\n * @hw: pointer to the HW structure\n *\n * Reads the MAC address out of the adapter and stores it in the HW structure.\n * Currently no func pointer exists and all implementations are handled in the\n * generic version of this function.\n **/\ns32 e1000_read_mac_addr(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.read_mac_addr)\n\t\treturn hw->mac.ops.read_mac_addr(hw);\n\n\treturn e1000_read_mac_addr_generic(hw);\n}\n\n/**\n * e1000_read_pba_string - Read device part number string\n * @hw: pointer to the HW structure\n * @pba_num: pointer to device part number\n * @pba_num_size: size of part number buffer\n *\n * Reads the product board assembly (PBA) number from the EEPROM and stores\n * the value in pba_num.\n * Currently no func pointer exists and all implementations are handled in the\n * generic version of this function.\n **/\ns32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size)\n{\n\treturn e1000_read_pba_string_generic(hw, pba_num, pba_num_size);\n}\n\n/**\n * e1000_read_pba_length - Read device part number string length\n * @hw: pointer to the HW structure\n * @pba_num_size: size of part number buffer\n *\n * Reads the product board assembly (PBA) number length from the EEPROM and\n * stores the value in pba_num.\n * Currently no func pointer exists and all implementations are handled in the\n * generic version of this function.\n **/\ns32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size)\n{\n\treturn e1000_read_pba_length_generic(hw, pba_num_size);\n}\n\n/**\n * e1000_read_pba_num - Read device part number\n * @hw: pointer to the HW structure\n * @pba_num: pointer to device part number\n *\n * Reads the product board assembly (PBA) number from the EEPROM and stores\n * the value in pba_num.\n * Currently no func pointer exists and all implementations are handled in the\n * generic version of this function.\n **/\ns32 e1000_read_pba_num(struct e1000_hw *hw, u32 *pba_num)\n{\n\treturn e1000_read_pba_num_generic(hw, pba_num);\n}\n\n/**\n * e1000_validate_nvm_checksum - Verifies NVM (EEPROM) checksum\n * @hw: pointer to the HW structure\n *\n * Validates the NVM checksum is correct. This is a function pointer entry\n * point called by drivers.\n **/\ns32 e1000_validate_nvm_checksum(struct e1000_hw *hw)\n{\n\tif (hw->nvm.ops.validate)\n\t\treturn hw->nvm.ops.validate(hw);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_update_nvm_checksum - Updates NVM (EEPROM) checksum\n * @hw: pointer to the HW structure\n *\n * Updates the NVM checksum. Currently no func pointer exists and all\n * implementations are handled in the generic version of this function.\n **/\ns32 e1000_update_nvm_checksum(struct e1000_hw *hw)\n{\n\tif (hw->nvm.ops.update)\n\t\treturn hw->nvm.ops.update(hw);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_reload_nvm - Reloads EEPROM\n * @hw: pointer to the HW structure\n *\n * Reloads the EEPROM by setting the \"Reinitialize from EEPROM\" bit in the\n * extended control register.\n **/\nvoid e1000_reload_nvm(struct e1000_hw *hw)\n{\n\tif (hw->nvm.ops.reload)\n\t\thw->nvm.ops.reload(hw);\n}\n\n/**\n * e1000_read_nvm - Reads NVM (EEPROM)\n * @hw: pointer to the HW structure\n * @offset: the word offset to read\n * @words: number of 16-bit words to read\n * @data: pointer to the properly sized buffer for the data.\n *\n * Reads 16-bit chunks of data from the NVM (EEPROM). This is a function\n * pointer entry point called by drivers.\n **/\ns32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)\n{\n\tif (hw->nvm.ops.read)\n\t\treturn hw->nvm.ops.read(hw, offset, words, data);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_write_nvm - Writes to NVM (EEPROM)\n * @hw: pointer to the HW structure\n * @offset: the word offset to read\n * @words: number of 16-bit words to write\n * @data: pointer to the properly sized buffer for the data.\n *\n * Writes 16-bit chunks of data to the NVM (EEPROM). This is a function\n * pointer entry point called by drivers.\n **/\ns32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)\n{\n\tif (hw->nvm.ops.write)\n\t\treturn hw->nvm.ops.write(hw, offset, words, data);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_8bit_ctrl_reg - Writes 8bit Control register\n * @hw: pointer to the HW structure\n * @reg: 32bit register offset\n * @offset: the register to write\n * @data: the value to write.\n *\n * Writes the PHY register at offset with the value in data.\n * This is a function pointer entry point called by drivers.\n **/\ns32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,\n\t\t\t u8 data)\n{\n\treturn e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data);\n}\n\n/**\n * e1000_power_up_phy - Restores link in case of PHY power down\n * @hw: pointer to the HW structure\n *\n * The phy may be powered down to save power, to turn off link when the\n * driver is unloaded, or wake on lan is not enabled (among others).\n **/\nvoid e1000_power_up_phy(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.power_up)\n\t\thw->phy.ops.power_up(hw);\n\n\te1000_setup_link(hw);\n}\n\n/**\n * e1000_power_down_phy - Power down PHY\n * @hw: pointer to the HW structure\n *\n * The phy may be powered down to save power, to turn off link when the\n * driver is unloaded, or wake on lan is not enabled (among others).\n **/\nvoid e1000_power_down_phy(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.power_down)\n\t\thw->phy.ops.power_down(hw);\n}\n\n/**\n * e1000_power_up_fiber_serdes_link - Power up serdes link\n * @hw: pointer to the HW structure\n *\n * Power on the optics and PCS.\n **/\nvoid e1000_power_up_fiber_serdes_link(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.power_up_serdes)\n\t\thw->mac.ops.power_up_serdes(hw);\n}\n\n/**\n * e1000_shutdown_fiber_serdes_link - Remove link during power down\n * @hw: pointer to the HW structure\n *\n * Shutdown the optics and PCS on driver unload.\n **/\nvoid e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.shutdown_serdes)\n\t\thw->mac.ops.shutdown_serdes(hw);\n}\n\n" }, { "path": "drivers/net/e1000/base/e1000_api.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_API_H_\n#define _E1000_API_H_\n\n#include \"e1000_hw.h\"\n\nextern void e1000_init_function_pointers_82542(struct e1000_hw *hw);\nextern void e1000_init_function_pointers_82543(struct e1000_hw *hw);\nextern void e1000_init_function_pointers_82540(struct e1000_hw *hw);\nextern void e1000_init_function_pointers_82571(struct e1000_hw *hw);\nextern void e1000_init_function_pointers_82541(struct e1000_hw *hw);\nextern void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw);\nextern void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw);\nextern void e1000_init_function_pointers_82575(struct e1000_hw *hw);\nextern void e1000_rx_fifo_flush_82575(struct e1000_hw *hw);\nextern void e1000_init_function_pointers_vf(struct e1000_hw *hw);\nextern void e1000_power_up_fiber_serdes_link(struct e1000_hw *hw);\nextern void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw);\nextern void e1000_init_function_pointers_i210(struct e1000_hw *hw);\n\ns32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr);\ns32 e1000_set_mac_type(struct e1000_hw *hw);\ns32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device);\ns32 e1000_init_mac_params(struct e1000_hw *hw);\ns32 e1000_init_nvm_params(struct e1000_hw *hw);\ns32 e1000_init_phy_params(struct e1000_hw *hw);\ns32 e1000_init_mbx_params(struct e1000_hw *hw);\ns32 e1000_get_bus_info(struct e1000_hw *hw);\nvoid e1000_clear_vfta(struct e1000_hw *hw);\nvoid e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);\ns32 e1000_force_mac_fc(struct e1000_hw *hw);\ns32 e1000_check_for_link(struct e1000_hw *hw);\ns32 e1000_reset_hw(struct e1000_hw *hw);\ns32 e1000_init_hw(struct e1000_hw *hw);\ns32 e1000_setup_link(struct e1000_hw *hw);\ns32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex);\ns32 e1000_disable_pcie_master(struct e1000_hw *hw);\nvoid e1000_config_collision_dist(struct e1000_hw *hw);\nvoid e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);\nu32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);\nvoid e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,\n\t\t\t u32 mc_addr_count);\ns32 e1000_setup_led(struct e1000_hw *hw);\ns32 e1000_cleanup_led(struct e1000_hw *hw);\ns32 e1000_check_reset_block(struct e1000_hw *hw);\ns32 e1000_blink_led(struct e1000_hw *hw);\ns32 e1000_led_on(struct e1000_hw *hw);\ns32 e1000_led_off(struct e1000_hw *hw);\ns32 e1000_id_led_init(struct e1000_hw *hw);\nvoid e1000_reset_adaptive(struct e1000_hw *hw);\nvoid e1000_update_adaptive(struct e1000_hw *hw);\ns32 e1000_get_cable_length(struct e1000_hw *hw);\ns32 e1000_validate_mdi_setting(struct e1000_hw *hw);\ns32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,\n\t\t\t u8 data);\ns32 e1000_get_phy_info(struct e1000_hw *hw);\nvoid e1000_release_phy(struct e1000_hw *hw);\ns32 e1000_acquire_phy(struct e1000_hw *hw);\ns32 e1000_cfg_on_link_up(struct e1000_hw *hw);\ns32 e1000_phy_hw_reset(struct e1000_hw *hw);\ns32 e1000_phy_commit(struct e1000_hw *hw);\nvoid e1000_power_up_phy(struct e1000_hw *hw);\nvoid e1000_power_down_phy(struct e1000_hw *hw);\ns32 e1000_read_mac_addr(struct e1000_hw *hw);\ns32 e1000_read_pba_num(struct e1000_hw *hw, u32 *part_num);\ns32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size);\ns32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size);\nvoid e1000_reload_nvm(struct e1000_hw *hw);\ns32 e1000_update_nvm_checksum(struct e1000_hw *hw);\ns32 e1000_validate_nvm_checksum(struct e1000_hw *hw);\ns32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);\ns32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);\ns32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);\ns32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);\nbool e1000_check_mng_mode(struct e1000_hw *hw);\nbool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);\ns32 e1000_mng_enable_host_if(struct e1000_hw *hw);\ns32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,\n\t\t\t u16 offset, u8 *sum);\ns32 e1000_mng_write_cmd_header(struct e1000_hw *hw,\n\t\t\t struct e1000_host_mng_command_header *hdr);\ns32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);\nu32 e1000_translate_register_82542(u32 reg);\n\n\n\n/*\n * TBI_ACCEPT macro definition:\n *\n * This macro requires:\n * adapter = a pointer to struct e1000_hw\n * status = the 8 bit status field of the Rx descriptor with EOP set\n * error = the 8 bit error field of the Rx descriptor with EOP set\n * length = the sum of all the length fields of the Rx descriptors that\n * make up the current frame\n * last_byte = the last byte of the frame DMAed by the hardware\n * max_frame_length = the maximum frame length we want to accept.\n * min_frame_length = the minimum frame length we want to accept.\n *\n * This macro is a conditional that should be used in the interrupt\n * handler's Rx processing routine when RxErrors have been detected.\n *\n * Typical use:\n * ...\n * if (TBI_ACCEPT) {\n * accept_frame = true;\n * e1000_tbi_adjust_stats(adapter, MacAddress);\n * frame_length--;\n * } else {\n * accept_frame = false;\n * }\n * ...\n */\n\n/* The carrier extension symbol, as received by the NIC. */\n#define CARRIER_EXTENSION 0x0F\n\n#define TBI_ACCEPT(a, status, errors, length, last_byte, \\\n\t\t min_frame_size, max_frame_size) \\\n\t(e1000_tbi_sbp_enabled_82543(a) && \\\n\t (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \\\n\t ((last_byte) == CARRIER_EXTENSION) && \\\n\t (((status) & E1000_RXD_STAT_VP) ? \\\n\t (((length) > (min_frame_size - VLAN_TAG_SIZE)) && \\\n\t ((length) <= (max_frame_size + 1))) : \\\n\t (((length) > min_frame_size) && \\\n\t ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1)))))\n\n#define E1000_MAX(a, b) ((a) > (b) ? (a) : (b))\n#define E1000_DIVIDE_ROUND_UP(a, b)\t(((a) + (b) - 1) / (b)) /* ceil(a/b) */\n#endif /* _E1000_API_H_ */\n" }, { "path": "drivers/net/e1000/base/e1000_defines.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_DEFINES_H_\n#define _E1000_DEFINES_H_\n\n/* Number of Transmit and Receive Descriptors must be a multiple of 8 */\n#define REQ_TX_DESCRIPTOR_MULTIPLE 8\n#define REQ_RX_DESCRIPTOR_MULTIPLE 8\n\n/* Definitions for power management and wakeup registers */\n/* Wake Up Control */\n#define E1000_WUC_APME\t\t0x00000001 /* APM Enable */\n#define E1000_WUC_PME_EN\t0x00000002 /* PME Enable */\n#define E1000_WUC_PME_STATUS\t0x00000004 /* PME Status */\n#define E1000_WUC_APMPME\t0x00000008 /* Assert PME on APM Wakeup */\n#define E1000_WUC_PHY_WAKE\t0x00000100 /* if PHY supports wakeup */\n\n/* Wake Up Filter Control */\n#define E1000_WUFC_LNKC\t0x00000001 /* Link Status Change Wakeup Enable */\n#define E1000_WUFC_MAG\t0x00000002 /* Magic Packet Wakeup Enable */\n#define E1000_WUFC_EX\t0x00000004 /* Directed Exact Wakeup Enable */\n#define E1000_WUFC_MC\t0x00000008 /* Directed Multicast Wakeup Enable */\n#define E1000_WUFC_BC\t0x00000010 /* Broadcast Wakeup Enable */\n#define E1000_WUFC_ARP\t0x00000020 /* ARP Request Packet Wakeup Enable */\n#define E1000_WUFC_IPV4\t0x00000040 /* Directed IPv4 Packet Wakeup Enable */\n#define E1000_WUFC_FLX0\t\t0x00010000 /* Flexible Filter 0 Enable */\n\n/* Wake Up Status */\n#define E1000_WUS_LNKC\t\tE1000_WUFC_LNKC\n#define E1000_WUS_MAG\t\tE1000_WUFC_MAG\n#define E1000_WUS_EX\t\tE1000_WUFC_EX\n#define E1000_WUS_MC\t\tE1000_WUFC_MC\n#define E1000_WUS_BC\t\tE1000_WUFC_BC\n\n/* Extended Device Control */\n#define E1000_CTRL_EXT_LPCD\t\t0x00000004 /* LCD Power Cycle Done */\n#define E1000_CTRL_EXT_SDP4_DATA\t0x00000010 /* SW Definable Pin 4 data */\n#define E1000_CTRL_EXT_SDP6_DATA\t0x00000040 /* SW Definable Pin 6 data */\n#define E1000_CTRL_EXT_SDP3_DATA\t0x00000080 /* SW Definable Pin 3 data */\n/* SDP 4/5 (bits 8,9) are reserved in >= 82575 */\n#define E1000_CTRL_EXT_SDP4_DIR\t0x00000100 /* Direction of SDP4 0=in 1=out */\n#define E1000_CTRL_EXT_SDP6_DIR\t0x00000400 /* Direction of SDP6 0=in 1=out */\n#define E1000_CTRL_EXT_SDP3_DIR\t0x00000800 /* Direction of SDP3 0=in 1=out */\n#define E1000_CTRL_EXT_FORCE_SMBUS\t0x00000800 /* Force SMBus mode */\n#define E1000_CTRL_EXT_EE_RST\t0x00002000 /* Reinitialize from EEPROM */\n/* Physical Func Reset Done Indication */\n#define E1000_CTRL_EXT_PFRSTD\t0x00004000\n#define E1000_CTRL_EXT_SDLPE\t0X00040000 /* SerDes Low Power Enable */\n#define E1000_CTRL_EXT_SPD_BYPS\t0x00008000 /* Speed Select Bypass */\n#define E1000_CTRL_EXT_RO_DIS\t0x00020000 /* Relaxed Ordering disable */\n#define E1000_CTRL_EXT_DMA_DYN_CLK_EN\t0x00080000 /* DMA Dynamic Clk Gating */\n#define E1000_CTRL_EXT_LINK_MODE_MASK\t0x00C00000\n/* Offset of the link mode field in Ctrl Ext register */\n#define E1000_CTRL_EXT_LINK_MODE_OFFSET\t22\n#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX\t0x00400000\n#define E1000_CTRL_EXT_LINK_MODE_GMII\t0x00000000\n#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES\t0x00C00000\n#define E1000_CTRL_EXT_LINK_MODE_SGMII\t0x00800000\n#define E1000_CTRL_EXT_EIAME\t\t0x01000000\n#define E1000_CTRL_EXT_IRCA\t\t0x00000001\n#define E1000_CTRL_EXT_DRV_LOAD\t\t0x10000000 /* Drv loaded bit for FW */\n#define E1000_CTRL_EXT_IAME\t\t0x08000000 /* Int ACK Auto-mask */\n#define E1000_CTRL_EXT_PBA_CLR\t\t0x80000000 /* PBA Clear */\n#define E1000_CTRL_EXT_LSECCK\t\t0x00001000\n#define E1000_CTRL_EXT_PHYPDEN\t\t0x00100000\n#define E1000_I2CCMD_REG_ADDR_SHIFT\t16\n#define E1000_I2CCMD_PHY_ADDR_SHIFT\t24\n#define E1000_I2CCMD_OPCODE_READ\t0x08000000\n#define E1000_I2CCMD_OPCODE_WRITE\t0x00000000\n#define E1000_I2CCMD_READY\t\t0x20000000\n#define E1000_I2CCMD_ERROR\t\t0x80000000\n#define E1000_I2CCMD_SFP_DATA_ADDR(a)\t(0x0000 + (a))\n#define E1000_I2CCMD_SFP_DIAG_ADDR(a)\t(0x0100 + (a))\n#define E1000_MAX_SGMII_PHY_REG_ADDR\t255\n#define E1000_I2CCMD_PHY_TIMEOUT\t200\n#define E1000_IVAR_VALID\t0x80\n#define E1000_GPIE_NSICR\t0x00000001\n#define E1000_GPIE_MSIX_MODE\t0x00000010\n#define E1000_GPIE_EIAME\t0x40000000\n#define E1000_GPIE_PBA\t\t0x80000000\n\n/* Receive Descriptor bit definitions */\n#define E1000_RXD_STAT_DD\t0x01 /* Descriptor Done */\n#define E1000_RXD_STAT_EOP\t0x02 /* End of Packet */\n#define E1000_RXD_STAT_IXSM\t0x04 /* Ignore checksum */\n#define E1000_RXD_STAT_VP\t0x08 /* IEEE VLAN Packet */\n#define E1000_RXD_STAT_UDPCS\t0x10 /* UDP xsum calculated */\n#define E1000_RXD_STAT_TCPCS\t0x20 /* TCP xsum calculated */\n#define E1000_RXD_STAT_IPCS\t0x40 /* IP xsum calculated */\n#define E1000_RXD_STAT_PIF\t0x80 /* passed in-exact filter */\n#define E1000_RXD_STAT_IPIDV\t0x200 /* IP identification valid */\n#define E1000_RXD_STAT_UDPV\t0x400 /* Valid UDP checksum */\n#define E1000_RXD_STAT_DYNINT\t0x800 /* Pkt caused INT via DYNINT */\n#define E1000_RXD_ERR_CE\t0x01 /* CRC Error */\n#define E1000_RXD_ERR_SE\t0x02 /* Symbol Error */\n#define E1000_RXD_ERR_SEQ\t0x04 /* Sequence Error */\n#define E1000_RXD_ERR_CXE\t0x10 /* Carrier Extension Error */\n#define E1000_RXD_ERR_TCPE\t0x20 /* TCP/UDP Checksum Error */\n#define E1000_RXD_ERR_IPE\t0x40 /* IP Checksum Error */\n#define E1000_RXD_ERR_RXE\t0x80 /* Rx Data Error */\n#define E1000_RXD_SPC_VLAN_MASK\t0x0FFF /* VLAN ID is in lower 12 bits */\n\n#define E1000_RXDEXT_STATERR_TST\t0x00000100 /* Time Stamp taken */\n#define E1000_RXDEXT_STATERR_LB\t\t0x00040000\n#define E1000_RXDEXT_STATERR_CE\t\t0x01000000\n#define E1000_RXDEXT_STATERR_SE\t\t0x02000000\n#define E1000_RXDEXT_STATERR_SEQ\t0x04000000\n#define E1000_RXDEXT_STATERR_CXE\t0x10000000\n#define E1000_RXDEXT_STATERR_TCPE\t0x20000000\n#define E1000_RXDEXT_STATERR_IPE\t0x40000000\n#define E1000_RXDEXT_STATERR_RXE\t0x80000000\n\n/* mask to determine if packets should be dropped due to frame errors */\n#define E1000_RXD_ERR_FRAME_ERR_MASK ( \\\n\tE1000_RXD_ERR_CE |\t\t\\\n\tE1000_RXD_ERR_SE |\t\t\\\n\tE1000_RXD_ERR_SEQ |\t\t\\\n\tE1000_RXD_ERR_CXE |\t\t\\\n\tE1000_RXD_ERR_RXE)\n\n/* Same mask, but for extended and packet split descriptors */\n#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \\\n\tE1000_RXDEXT_STATERR_CE |\t\\\n\tE1000_RXDEXT_STATERR_SE |\t\\\n\tE1000_RXDEXT_STATERR_SEQ |\t\\\n\tE1000_RXDEXT_STATERR_CXE |\t\\\n\tE1000_RXDEXT_STATERR_RXE)\n\n#if !defined(EXTERNAL_RELEASE) || defined(E1000E_MQ)\n#define E1000_MRQC_ENABLE_RSS_2Q\t\t0x00000001\n#endif /* !EXTERNAL_RELEASE || E1000E_MQ */\n#define E1000_MRQC_RSS_FIELD_MASK\t\t0xFFFF0000\n#define E1000_MRQC_RSS_FIELD_IPV4_TCP\t\t0x00010000\n#define E1000_MRQC_RSS_FIELD_IPV4\t\t0x00020000\n#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX\t0x00040000\n#define E1000_MRQC_RSS_FIELD_IPV6\t\t0x00100000\n#define E1000_MRQC_RSS_FIELD_IPV6_TCP\t\t0x00200000\n\n#define E1000_RXDPS_HDRSTAT_HDRSP\t\t0x00008000\n\n/* Management Control */\n#define E1000_MANC_SMBUS_EN\t0x00000001 /* SMBus Enabled - RO */\n#define E1000_MANC_ASF_EN\t0x00000002 /* ASF Enabled - RO */\n#define E1000_MANC_ARP_EN\t0x00002000 /* Enable ARP Request Filtering */\n#define E1000_MANC_RCV_TCO_EN\t0x00020000 /* Receive TCO Packets Enabled */\n#define E1000_MANC_BLK_PHY_RST_ON_IDE\t0x00040000 /* Block phy resets */\n/* Enable MAC address filtering */\n#define E1000_MANC_EN_MAC_ADDR_FILTER\t0x00100000\n/* Enable MNG packets to host memory */\n#define E1000_MANC_EN_MNG2HOST\t\t0x00200000\n\n#define E1000_MANC2H_PORT_623\t\t0x00000020 /* Port 0x26f */\n#define E1000_MANC2H_PORT_664\t\t0x00000040 /* Port 0x298 */\n#define E1000_MDEF_PORT_623\t\t0x00000800 /* Port 0x26f */\n#define E1000_MDEF_PORT_664\t\t0x00000400 /* Port 0x298 */\n\n/* Receive Control */\n#define E1000_RCTL_RST\t\t0x00000001 /* Software reset */\n#define E1000_RCTL_EN\t\t0x00000002 /* enable */\n#define E1000_RCTL_SBP\t\t0x00000004 /* store bad packet */\n#define E1000_RCTL_UPE\t\t0x00000008 /* unicast promisc enable */\n#define E1000_RCTL_MPE\t\t0x00000010 /* multicast promisc enable */\n#define E1000_RCTL_LPE\t\t0x00000020 /* long packet enable */\n#define E1000_RCTL_LBM_NO\t0x00000000 /* no loopback mode */\n#define E1000_RCTL_LBM_MAC\t0x00000040 /* MAC loopback mode */\n#define E1000_RCTL_LBM_TCVR\t0x000000C0 /* tcvr loopback mode */\n#define E1000_RCTL_DTYP_PS\t0x00000400 /* Packet Split descriptor */\n#define E1000_RCTL_RDMTS_HALF\t0x00000000 /* Rx desc min thresh size */\n#define E1000_RCTL_MO_SHIFT\t12 /* multicast offset shift */\n#define E1000_RCTL_MO_3\t\t0x00003000 /* multicast offset 15:4 */\n#define E1000_RCTL_BAM\t\t0x00008000 /* broadcast enable */\n/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */\n#define E1000_RCTL_SZ_2048\t0x00000000 /* Rx buffer size 2048 */\n#define E1000_RCTL_SZ_1024\t0x00010000 /* Rx buffer size 1024 */\n#define E1000_RCTL_SZ_512\t0x00020000 /* Rx buffer size 512 */\n#define E1000_RCTL_SZ_256\t0x00030000 /* Rx buffer size 256 */\n/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */\n#define E1000_RCTL_SZ_16384\t0x00010000 /* Rx buffer size 16384 */\n#define E1000_RCTL_SZ_8192\t0x00020000 /* Rx buffer size 8192 */\n#define E1000_RCTL_SZ_4096\t0x00030000 /* Rx buffer size 4096 */\n#define E1000_RCTL_VFE\t\t0x00040000 /* vlan filter enable */\n#define E1000_RCTL_CFIEN\t0x00080000 /* canonical form enable */\n#define E1000_RCTL_CFI\t\t0x00100000 /* canonical form indicator */\n#define E1000_RCTL_DPF\t\t0x00400000 /* discard pause frames */\n#define E1000_RCTL_PMCF\t\t0x00800000 /* pass MAC control frames */\n#define E1000_RCTL_BSEX\t\t0x02000000 /* Buffer size extension */\n#define E1000_RCTL_SECRC\t0x04000000 /* Strip Ethernet CRC */\n\n/* Use byte values for the following shift parameters\n * Usage:\n * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &\n *\t\t E1000_PSRCTL_BSIZE0_MASK) |\n *\t\t((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &\n *\t\t E1000_PSRCTL_BSIZE1_MASK) |\n *\t\t((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &\n *\t\t E1000_PSRCTL_BSIZE2_MASK) |\n *\t\t((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;\n *\t\t E1000_PSRCTL_BSIZE3_MASK))\n * where value0 = [128..16256], default=256\n * value1 = [1024..64512], default=4096\n * value2 = [0..64512], default=4096\n * value3 = [0..64512], default=0\n */\n\n#define E1000_PSRCTL_BSIZE0_MASK\t0x0000007F\n#define E1000_PSRCTL_BSIZE1_MASK\t0x00003F00\n#define E1000_PSRCTL_BSIZE2_MASK\t0x003F0000\n#define E1000_PSRCTL_BSIZE3_MASK\t0x3F000000\n\n#define E1000_PSRCTL_BSIZE0_SHIFT\t7 /* Shift _right_ 7 */\n#define E1000_PSRCTL_BSIZE1_SHIFT\t2 /* Shift _right_ 2 */\n#define E1000_PSRCTL_BSIZE2_SHIFT\t6 /* Shift _left_ 6 */\n#define E1000_PSRCTL_BSIZE3_SHIFT\t14 /* Shift _left_ 14 */\n\n/* SWFW_SYNC Definitions */\n#define E1000_SWFW_EEP_SM\t0x01\n#define E1000_SWFW_PHY0_SM\t0x02\n#define E1000_SWFW_PHY1_SM\t0x04\n#define E1000_SWFW_CSR_SM\t0x08\n#define E1000_SWFW_PHY2_SM\t0x20\n#define E1000_SWFW_PHY3_SM\t0x40\n#define E1000_SWFW_SW_MNG_SM\t0x400\n\n/* Device Control */\n#define E1000_CTRL_FD\t\t0x00000001 /* Full duplex.0=half; 1=full */\n#define E1000_CTRL_PRIOR\t0x00000004 /* Priority on PCI. 0=rx,1=fair */\n#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */\n#define E1000_CTRL_LRST\t\t0x00000008 /* Link reset. 0=normal,1=reset */\n#define E1000_CTRL_ASDE\t\t0x00000020 /* Auto-speed detect enable */\n#define E1000_CTRL_SLU\t\t0x00000040 /* Set link up (Force Link) */\n#define E1000_CTRL_ILOS\t\t0x00000080 /* Invert Loss-Of Signal */\n#define E1000_CTRL_SPD_SEL\t0x00000300 /* Speed Select Mask */\n#define E1000_CTRL_SPD_10\t0x00000000 /* Force 10Mb */\n#define E1000_CTRL_SPD_100\t0x00000100 /* Force 100Mb */\n#define E1000_CTRL_SPD_1000\t0x00000200 /* Force 1Gb */\n#define E1000_CTRL_FRCSPD\t0x00000800 /* Force Speed */\n#define E1000_CTRL_FRCDPX\t0x00001000 /* Force Duplex */\n#define E1000_CTRL_LANPHYPC_OVERRIDE\t0x00010000 /* SW control of LANPHYPC */\n#define E1000_CTRL_LANPHYPC_VALUE\t0x00020000 /* SW value of LANPHYPC */\n#define E1000_CTRL_MEHE\t\t0x00080000 /* Memory Error Handling Enable */\n#define E1000_CTRL_SWDPIN0\t0x00040000 /* SWDPIN 0 value */\n#define E1000_CTRL_SWDPIN1\t0x00080000 /* SWDPIN 1 value */\n#define E1000_CTRL_SWDPIN2\t0x00100000 /* SWDPIN 2 value */\n#define E1000_CTRL_ADVD3WUC\t0x00100000 /* D3 WUC */\n#define E1000_CTRL_EN_PHY_PWR_MGMT\t0x00200000 /* PHY PM enable */\n#define E1000_CTRL_SWDPIN3\t0x00200000 /* SWDPIN 3 value */\n#define E1000_CTRL_SWDPIO0\t0x00400000 /* SWDPIN 0 Input or output */\n#define E1000_CTRL_SWDPIO2\t0x01000000 /* SWDPIN 2 input or output */\n#define E1000_CTRL_SWDPIO3\t0x02000000 /* SWDPIN 3 input or output */\n#define E1000_CTRL_RST\t\t0x04000000 /* Global reset */\n#define E1000_CTRL_RFCE\t\t0x08000000 /* Receive Flow Control enable */\n#define E1000_CTRL_TFCE\t\t0x10000000 /* Transmit flow control enable */\n#define E1000_CTRL_VME\t\t0x40000000 /* IEEE VLAN mode enable */\n#define E1000_CTRL_PHY_RST\t0x80000000 /* PHY Reset */\n#define E1000_CTRL_I2C_ENA\t0x02000000 /* I2C enable */\n\n#define E1000_CTRL_MDIO_DIR\t\tE1000_CTRL_SWDPIO2\n#define E1000_CTRL_MDIO\t\t\tE1000_CTRL_SWDPIN2\n#define E1000_CTRL_MDC_DIR\t\tE1000_CTRL_SWDPIO3\n#define E1000_CTRL_MDC\t\t\tE1000_CTRL_SWDPIN3\n\n#define E1000_CONNSW_ENRGSRC\t\t0x4\n#define E1000_CONNSW_PHYSD\t\t0x400\n#define E1000_CONNSW_PHY_PDN\t\t0x800\n#define E1000_CONNSW_SERDESD\t\t0x200\n#define E1000_CONNSW_AUTOSENSE_CONF\t0x2\n#define E1000_CONNSW_AUTOSENSE_EN\t0x1\n#define E1000_PCS_CFG_PCS_EN\t\t8\n#define E1000_PCS_LCTL_FLV_LINK_UP\t1\n#define E1000_PCS_LCTL_FSV_10\t\t0\n#define E1000_PCS_LCTL_FSV_100\t\t2\n#define E1000_PCS_LCTL_FSV_1000\t\t4\n#define E1000_PCS_LCTL_FDV_FULL\t\t8\n#define E1000_PCS_LCTL_FSD\t\t0x10\n#define E1000_PCS_LCTL_FORCE_LINK\t0x20\n#define E1000_PCS_LCTL_FORCE_FCTRL\t0x80\n#define E1000_PCS_LCTL_AN_ENABLE\t0x10000\n#define E1000_PCS_LCTL_AN_RESTART\t0x20000\n#define E1000_PCS_LCTL_AN_TIMEOUT\t0x40000\n#define E1000_ENABLE_SERDES_LOOPBACK\t0x0410\n\n#define E1000_PCS_LSTS_LINK_OK\t\t1\n#define E1000_PCS_LSTS_SPEED_100\t2\n#define E1000_PCS_LSTS_SPEED_1000\t4\n#define E1000_PCS_LSTS_DUPLEX_FULL\t8\n#define E1000_PCS_LSTS_SYNK_OK\t\t0x10\n#define E1000_PCS_LSTS_AN_COMPLETE\t0x10000\n\n/* Device Status */\n#define E1000_STATUS_FD\t\t\t0x00000001 /* Duplex 0=half 1=full */\n#define E1000_STATUS_LU\t\t\t0x00000002 /* Link up.0=no,1=link */\n#define E1000_STATUS_FUNC_MASK\t\t0x0000000C /* PCI Function Mask */\n#define E1000_STATUS_FUNC_SHIFT\t\t2\n#define E1000_STATUS_FUNC_1\t\t0x00000004 /* Function 1 */\n#define E1000_STATUS_TXOFF\t\t0x00000010 /* transmission paused */\n#define E1000_STATUS_SPEED_MASK\t0x000000C0\n#define E1000_STATUS_SPEED_10\t\t0x00000000 /* Speed 10Mb/s */\n#define E1000_STATUS_SPEED_100\t\t0x00000040 /* Speed 100Mb/s */\n#define E1000_STATUS_SPEED_1000\t\t0x00000080 /* Speed 1000Mb/s */\n#define E1000_STATUS_LAN_INIT_DONE\t0x00000200 /* Lan Init Compltn by NVM */\n#define E1000_STATUS_PHYRA\t\t0x00000400 /* PHY Reset Asserted */\n#define E1000_STATUS_GIO_MASTER_ENABLE\t0x00080000 /* Master request status */\n#define E1000_STATUS_PCI66\t\t0x00000800 /* In 66Mhz slot */\n#define E1000_STATUS_BUS64\t\t0x00001000 /* In 64 bit slot */\n#define E1000_STATUS_2P5_SKU\t\t0x00001000 /* Val of 2.5GBE SKU strap */\n#define E1000_STATUS_2P5_SKU_OVER\t0x00002000 /* Val of 2.5GBE SKU Over */\n#define E1000_STATUS_PCIX_MODE\t\t0x00002000 /* PCI-X mode */\n#define E1000_STATUS_PCIX_SPEED\t\t0x0000C000 /* PCI-X bus speed */\n\n/* Constants used to interpret the masked PCI-X bus speed. */\n#define E1000_STATUS_PCIX_SPEED_66\t0x00000000 /* PCI-X bus spd 50-66MHz */\n#define E1000_STATUS_PCIX_SPEED_100\t0x00004000 /* PCI-X bus spd 66-100MHz */\n#define E1000_STATUS_PCIX_SPEED_133\t0x00008000 /* PCI-X bus spd 100-133MHz*/\n\n#define SPEED_10\t10\n#define SPEED_100\t100\n#define SPEED_1000\t1000\n#define SPEED_2500\t2500\n#define HALF_DUPLEX\t1\n#define FULL_DUPLEX\t2\n\n#define PHY_FORCE_TIME\t20\n\n#define ADVERTISE_10_HALF\t\t0x0001\n#define ADVERTISE_10_FULL\t\t0x0002\n#define ADVERTISE_100_HALF\t\t0x0004\n#define ADVERTISE_100_FULL\t\t0x0008\n#define ADVERTISE_1000_HALF\t\t0x0010 /* Not used, just FYI */\n#define ADVERTISE_1000_FULL\t\t0x0020\n\n/* 1000/H is not supported, nor spec-compliant. */\n#define E1000_ALL_SPEED_DUPLEX\t( \\\n\tADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \\\n\tADVERTISE_100_FULL | ADVERTISE_1000_FULL)\n#define E1000_ALL_NOT_GIG\t( \\\n\tADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \\\n\tADVERTISE_100_FULL)\n#define E1000_ALL_100_SPEED\t(ADVERTISE_100_HALF | ADVERTISE_100_FULL)\n#define E1000_ALL_10_SPEED\t(ADVERTISE_10_HALF | ADVERTISE_10_FULL)\n#define E1000_ALL_HALF_DUPLEX\t(ADVERTISE_10_HALF | ADVERTISE_100_HALF)\n\n#define AUTONEG_ADVERTISE_SPEED_DEFAULT\t\tE1000_ALL_SPEED_DUPLEX\n\n/* LED Control */\n#define E1000_PHY_LED0_MODE_MASK\t0x00000007\n#define E1000_PHY_LED0_IVRT\t\t0x00000008\n#define E1000_PHY_LED0_MASK\t\t0x0000001F\n\n#define E1000_LEDCTL_LED0_MODE_MASK\t0x0000000F\n#define E1000_LEDCTL_LED0_MODE_SHIFT\t0\n#define E1000_LEDCTL_LED0_IVRT\t\t0x00000040\n#define E1000_LEDCTL_LED0_BLINK\t\t0x00000080\n\n#define E1000_LEDCTL_MODE_LINK_UP\t0x2\n#define E1000_LEDCTL_MODE_LED_ON\t0xE\n#define E1000_LEDCTL_MODE_LED_OFF\t0xF\n\n/* Transmit Descriptor bit definitions */\n#define E1000_TXD_DTYP_D\t0x00100000 /* Data Descriptor */\n#define E1000_TXD_DTYP_C\t0x00000000 /* Context Descriptor */\n#define E1000_TXD_POPTS_IXSM\t0x01 /* Insert IP checksum */\n#define E1000_TXD_POPTS_TXSM\t0x02 /* Insert TCP/UDP checksum */\n#define E1000_TXD_CMD_EOP\t0x01000000 /* End of Packet */\n#define E1000_TXD_CMD_IFCS\t0x02000000 /* Insert FCS (Ethernet CRC) */\n#define E1000_TXD_CMD_IC\t0x04000000 /* Insert Checksum */\n#define E1000_TXD_CMD_RS\t0x08000000 /* Report Status */\n#define E1000_TXD_CMD_RPS\t0x10000000 /* Report Packet Sent */\n#define E1000_TXD_CMD_DEXT\t0x20000000 /* Desc extension (0 = legacy) */\n#define E1000_TXD_CMD_VLE\t0x40000000 /* Add VLAN tag */\n#define E1000_TXD_CMD_IDE\t0x80000000 /* Enable Tidv register */\n#define E1000_TXD_STAT_DD\t0x00000001 /* Descriptor Done */\n#define E1000_TXD_STAT_EC\t0x00000002 /* Excess Collisions */\n#define E1000_TXD_STAT_LC\t0x00000004 /* Late Collisions */\n#define E1000_TXD_STAT_TU\t0x00000008 /* Transmit underrun */\n#define E1000_TXD_CMD_TCP\t0x01000000 /* TCP packet */\n#define E1000_TXD_CMD_IP\t0x02000000 /* IP packet */\n#define E1000_TXD_CMD_TSE\t0x04000000 /* TCP Seg enable */\n#define E1000_TXD_STAT_TC\t0x00000004 /* Tx Underrun */\n#define E1000_TXD_EXTCMD_TSTAMP\t0x00000010 /* IEEE1588 Timestamp packet */\n\n/* Transmit Control */\n#define E1000_TCTL_EN\t\t0x00000002 /* enable Tx */\n#define E1000_TCTL_PSP\t\t0x00000008 /* pad short packets */\n#define E1000_TCTL_CT\t\t0x00000ff0 /* collision threshold */\n#define E1000_TCTL_COLD\t\t0x003ff000 /* collision distance */\n#define E1000_TCTL_RTLC\t\t0x01000000 /* Re-transmit on late collision */\n#define E1000_TCTL_MULR\t\t0x10000000 /* Multiple request support */\n\n/* Transmit Arbitration Count */\n#define E1000_TARC0_ENABLE\t0x00000400 /* Enable Tx Queue 0 */\n\n/* SerDes Control */\n#define E1000_SCTL_DISABLE_SERDES_LOOPBACK\t0x0400\n#define E1000_SCTL_ENABLE_SERDES_LOOPBACK\t0x0410\n\n/* Receive Checksum Control */\n#define E1000_RXCSUM_IPOFL\t0x00000100 /* IPv4 checksum offload */\n#define E1000_RXCSUM_TUOFL\t0x00000200 /* TCP / UDP checksum offload */\n#define E1000_RXCSUM_CRCOFL\t0x00000800 /* CRC32 offload enable */\n#define E1000_RXCSUM_IPPCSE\t0x00001000 /* IP payload checksum enable */\n#define E1000_RXCSUM_PCSD\t0x00002000 /* packet checksum disabled */\n\n/* Header split receive */\n#define E1000_RFCTL_NFSW_DIS\t\t0x00000040\n#define E1000_RFCTL_NFSR_DIS\t\t0x00000080\n#define E1000_RFCTL_ACK_DIS\t\t0x00001000\n#define E1000_RFCTL_EXTEN\t\t0x00008000\n#define E1000_RFCTL_IPV6_EX_DIS\t\t0x00010000\n#define E1000_RFCTL_NEW_IPV6_EXT_DIS\t0x00020000\n#define E1000_RFCTL_LEF\t\t\t0x00040000\n\n/* Collision related configuration parameters */\n#define E1000_COLLISION_THRESHOLD\t15\n#define E1000_CT_SHIFT\t\t\t4\n#define E1000_COLLISION_DISTANCE\t63\n#define E1000_COLD_SHIFT\t\t12\n\n/* Default values for the transmit IPG register */\n#define DEFAULT_82542_TIPG_IPGT\t\t10\n#define DEFAULT_82543_TIPG_IPGT_FIBER\t9\n#define DEFAULT_82543_TIPG_IPGT_COPPER\t8\n\n#define E1000_TIPG_IPGT_MASK\t\t0x000003FF\n\n#define DEFAULT_82542_TIPG_IPGR1\t2\n#define DEFAULT_82543_TIPG_IPGR1\t8\n#define E1000_TIPG_IPGR1_SHIFT\t\t10\n\n#define DEFAULT_82542_TIPG_IPGR2\t10\n#define DEFAULT_82543_TIPG_IPGR2\t6\n#define DEFAULT_80003ES2LAN_TIPG_IPGR2\t7\n#define E1000_TIPG_IPGR2_SHIFT\t\t20\n\n/* Ethertype field values */\n#define ETHERNET_IEEE_VLAN_TYPE\t\t0x8100 /* 802.3ac packet */\n\n#define ETHERNET_FCS_SIZE\t\t4\n#define MAX_JUMBO_FRAME_SIZE\t\t0x3F00\n\n/* Extended Configuration Control and Size */\n#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP\t0x00000020\n#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE\t0x00000001\n#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE\t0x00000008\n#define E1000_EXTCNF_CTRL_SWFLAG\t\t0x00000020\n#define E1000_EXTCNF_CTRL_GATE_PHY_CFG\t\t0x00000080\n#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK\t0x00FF0000\n#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT\t16\n#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK\t0x0FFF0000\n#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT\t16\n\n#define E1000_PHY_CTRL_D0A_LPLU\t\t\t0x00000002\n#define E1000_PHY_CTRL_NOND0A_LPLU\t\t0x00000004\n#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE\t0x00000008\n#define E1000_PHY_CTRL_GBE_DISABLE\t\t0x00000040\n\n#define E1000_KABGTXD_BGSQLBIAS\t\t\t0x00050000\n\n/* Low Power IDLE Control */\n#define E1000_LPIC_LPIET_SHIFT\t\t24\t/* Low Power Idle Entry Time */\n\n/* PBA constants */\n#define E1000_PBA_8K\t\t0x0008 /* 8KB */\n#define E1000_PBA_10K\t\t0x000A /* 10KB */\n#define E1000_PBA_12K\t\t0x000C /* 12KB */\n#define E1000_PBA_14K\t\t0x000E /* 14KB */\n#define E1000_PBA_16K\t\t0x0010 /* 16KB */\n#define E1000_PBA_18K\t\t0x0012\n#define E1000_PBA_20K\t\t0x0014\n#define E1000_PBA_22K\t\t0x0016\n#define E1000_PBA_24K\t\t0x0018\n#define E1000_PBA_26K\t\t0x001A\n#define E1000_PBA_30K\t\t0x001E\n#define E1000_PBA_32K\t\t0x0020\n#define E1000_PBA_34K\t\t0x0022\n#define E1000_PBA_35K\t\t0x0023\n#define E1000_PBA_38K\t\t0x0026\n#define E1000_PBA_40K\t\t0x0028\n#define E1000_PBA_48K\t\t0x0030 /* 48KB */\n#define E1000_PBA_64K\t\t0x0040 /* 64KB */\n\n#define E1000_PBA_RXA_MASK\t0xFFFF\n\n#define E1000_PBS_16K\t\tE1000_PBA_16K\n\n/* Uncorrectable/correctable ECC Error counts and enable bits */\n#define E1000_PBECCSTS_CORR_ERR_CNT_MASK\t0x000000FF\n#define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK\t0x0000FF00\n#define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT\t8\n#define E1000_PBECCSTS_ECC_ENABLE\t\t0x00010000\n\n#define IFS_MAX\t\t\t80\n#define IFS_MIN\t\t\t40\n#define IFS_RATIO\t\t4\n#define IFS_STEP\t\t10\n#define MIN_NUM_XMITS\t\t1000\n\n/* SW Semaphore Register */\n#define E1000_SWSM_SMBI\t\t0x00000001 /* Driver Semaphore bit */\n#define E1000_SWSM_SWESMBI\t0x00000002 /* FW Semaphore bit */\n#define E1000_SWSM_DRV_LOAD\t0x00000008 /* Driver Loaded Bit */\n\n#define E1000_SWSM2_LOCK\t0x00000002 /* Secondary driver semaphore bit */\n\n/* Interrupt Cause Read */\n#define E1000_ICR_TXDW\t\t0x00000001 /* Transmit desc written back */\n#define E1000_ICR_TXQE\t\t0x00000002 /* Transmit Queue empty */\n#define E1000_ICR_LSC\t\t0x00000004 /* Link Status Change */\n#define E1000_ICR_RXSEQ\t\t0x00000008 /* Rx sequence error */\n#define E1000_ICR_RXDMT0\t0x00000010 /* Rx desc min. threshold (0) */\n#define E1000_ICR_RXO\t\t0x00000040 /* Rx overrun */\n#define E1000_ICR_RXT0\t\t0x00000080 /* Rx timer intr (ring 0) */\n#define E1000_ICR_VMMB\t\t0x00000100 /* VM MB event */\n#define E1000_ICR_RXCFG\t\t0x00000400 /* Rx /c/ ordered set */\n#define E1000_ICR_GPI_EN0\t0x00000800 /* GP Int 0 */\n#define E1000_ICR_GPI_EN1\t0x00001000 /* GP Int 1 */\n#define E1000_ICR_GPI_EN2\t0x00002000 /* GP Int 2 */\n#define E1000_ICR_GPI_EN3\t0x00004000 /* GP Int 3 */\n#define E1000_ICR_TXD_LOW\t0x00008000\n#define E1000_ICR_MNG\t\t0x00040000 /* Manageability event */\n#define E1000_ICR_ECCER\t\t0x00400000 /* Uncorrectable ECC Error */\n#define E1000_ICR_TS\t\t0x00080000 /* Time Sync Interrupt */\n#define E1000_ICR_DRSTA\t\t0x40000000 /* Device Reset Asserted */\n/* If this bit asserted, the driver should claim the interrupt */\n#define E1000_ICR_INT_ASSERTED\t0x80000000\n#define E1000_ICR_DOUTSYNC\t0x10000000 /* NIC DMA out of sync */\n#define E1000_ICR_RXQ0\t\t0x00100000 /* Rx Queue 0 Interrupt */\n#define E1000_ICR_RXQ1\t\t0x00200000 /* Rx Queue 1 Interrupt */\n#define E1000_ICR_TXQ0\t\t0x00400000 /* Tx Queue 0 Interrupt */\n#define E1000_ICR_TXQ1\t\t0x00800000 /* Tx Queue 1 Interrupt */\n#define E1000_ICR_OTHER\t\t0x01000000 /* Other Interrupts */\n#define E1000_ICR_FER\t\t0x00400000 /* Fatal Error */\n\n#define E1000_ICR_THS\t\t0x00800000 /* ICR.THS: Thermal Sensor Event*/\n#define E1000_ICR_MDDET\t\t0x10000000 /* Malicious Driver Detect */\n\n/* PBA ECC Register */\n#define E1000_PBA_ECC_COUNTER_MASK\t0xFFF00000 /* ECC counter mask */\n#define E1000_PBA_ECC_COUNTER_SHIFT\t20 /* ECC counter shift value */\n#define E1000_PBA_ECC_CORR_EN\t0x00000001 /* Enable ECC error correction */\n#define E1000_PBA_ECC_STAT_CLR\t0x00000002 /* Clear ECC error counter */\n#define E1000_PBA_ECC_INT_EN\t0x00000004 /* Enable ICR bit 5 on ECC error */\n\n/* Extended Interrupt Cause Read */\n#define E1000_EICR_RX_QUEUE0\t0x00000001 /* Rx Queue 0 Interrupt */\n#define E1000_EICR_RX_QUEUE1\t0x00000002 /* Rx Queue 1 Interrupt */\n#define E1000_EICR_RX_QUEUE2\t0x00000004 /* Rx Queue 2 Interrupt */\n#define E1000_EICR_RX_QUEUE3\t0x00000008 /* Rx Queue 3 Interrupt */\n#define E1000_EICR_TX_QUEUE0\t0x00000100 /* Tx Queue 0 Interrupt */\n#define E1000_EICR_TX_QUEUE1\t0x00000200 /* Tx Queue 1 Interrupt */\n#define E1000_EICR_TX_QUEUE2\t0x00000400 /* Tx Queue 2 Interrupt */\n#define E1000_EICR_TX_QUEUE3\t0x00000800 /* Tx Queue 3 Interrupt */\n#define E1000_EICR_TCP_TIMER\t0x40000000 /* TCP Timer */\n#define E1000_EICR_OTHER\t0x80000000 /* Interrupt Cause Active */\n/* TCP Timer */\n#define E1000_TCPTIMER_KS\t0x00000100 /* KickStart */\n#define E1000_TCPTIMER_COUNT_ENABLE\t0x00000200 /* Count Enable */\n#define E1000_TCPTIMER_COUNT_FINISH\t0x00000400 /* Count finish */\n#define E1000_TCPTIMER_LOOP\t0x00000800 /* Loop */\n\n/* This defines the bits that are set in the Interrupt Mask\n * Set/Read Register. Each bit is documented below:\n * o RXT0 = Receiver Timer Interrupt (ring 0)\n * o TXDW = Transmit Descriptor Written Back\n * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)\n * o RXSEQ = Receive Sequence Error\n * o LSC = Link Status Change\n */\n#define IMS_ENABLE_MASK ( \\\n\tE1000_IMS_RXT0 | \\\n\tE1000_IMS_TXDW | \\\n\tE1000_IMS_RXDMT0 | \\\n\tE1000_IMS_RXSEQ | \\\n\tE1000_IMS_LSC)\n\n/* Interrupt Mask Set */\n#define E1000_IMS_TXDW\t\tE1000_ICR_TXDW /* Tx desc written back */\n#define E1000_IMS_TXQE\t\tE1000_ICR_TXQE /* Transmit Queue empty */\n#define E1000_IMS_LSC\t\tE1000_ICR_LSC /* Link Status Change */\n#define E1000_IMS_VMMB\t\tE1000_ICR_VMMB /* Mail box activity */\n#define E1000_IMS_RXSEQ\t\tE1000_ICR_RXSEQ /* Rx sequence error */\n#define E1000_IMS_RXDMT0\tE1000_ICR_RXDMT0 /* Rx desc min. threshold */\n#define E1000_IMS_RXO\t\tE1000_ICR_RXO /* Rx overrun */\n#define E1000_IMS_RXT0\t\tE1000_ICR_RXT0 /* Rx timer intr */\n#define E1000_IMS_TXD_LOW\tE1000_ICR_TXD_LOW\n#define E1000_IMS_ECCER\t\tE1000_ICR_ECCER /* Uncorrectable ECC Error */\n#define E1000_IMS_TS\t\tE1000_ICR_TS /* Time Sync Interrupt */\n#define E1000_IMS_DRSTA\t\tE1000_ICR_DRSTA /* Device Reset Asserted */\n#define E1000_IMS_DOUTSYNC\tE1000_ICR_DOUTSYNC /* NIC DMA out of sync */\n#define E1000_IMS_RXQ0\t\tE1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */\n#define E1000_IMS_RXQ1\t\tE1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */\n#define E1000_IMS_TXQ0\t\tE1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */\n#define E1000_IMS_TXQ1\t\tE1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */\n#define E1000_IMS_OTHER\t\tE1000_ICR_OTHER /* Other Interrupts */\n#define E1000_IMS_FER\t\tE1000_ICR_FER /* Fatal Error */\n\n#define E1000_IMS_THS\t\tE1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/\n#define E1000_IMS_MDDET\t\tE1000_ICR_MDDET /* Malicious Driver Detect */\n/* Extended Interrupt Mask Set */\n#define E1000_EIMS_RX_QUEUE0\tE1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */\n#define E1000_EIMS_RX_QUEUE1\tE1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */\n#define E1000_EIMS_RX_QUEUE2\tE1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */\n#define E1000_EIMS_RX_QUEUE3\tE1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */\n#define E1000_EIMS_TX_QUEUE0\tE1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */\n#define E1000_EIMS_TX_QUEUE1\tE1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */\n#define E1000_EIMS_TX_QUEUE2\tE1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */\n#define E1000_EIMS_TX_QUEUE3\tE1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */\n#define E1000_EIMS_TCP_TIMER\tE1000_EICR_TCP_TIMER /* TCP Timer */\n#define E1000_EIMS_OTHER\tE1000_EICR_OTHER /* Interrupt Cause Active */\n\n/* Interrupt Cause Set */\n#define E1000_ICS_LSC\t\tE1000_ICR_LSC /* Link Status Change */\n#define E1000_ICS_RXSEQ\t\tE1000_ICR_RXSEQ /* Rx sequence error */\n#define E1000_ICS_RXDMT0\tE1000_ICR_RXDMT0 /* Rx desc min. threshold */\n\n/* Extended Interrupt Cause Set */\n#define E1000_EICS_RX_QUEUE0\tE1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */\n#define E1000_EICS_RX_QUEUE1\tE1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */\n#define E1000_EICS_RX_QUEUE2\tE1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */\n#define E1000_EICS_RX_QUEUE3\tE1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */\n#define E1000_EICS_TX_QUEUE0\tE1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */\n#define E1000_EICS_TX_QUEUE1\tE1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */\n#define E1000_EICS_TX_QUEUE2\tE1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */\n#define E1000_EICS_TX_QUEUE3\tE1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */\n#define E1000_EICS_TCP_TIMER\tE1000_EICR_TCP_TIMER /* TCP Timer */\n#define E1000_EICS_OTHER\tE1000_EICR_OTHER /* Interrupt Cause Active */\n\n#define E1000_EITR_ITR_INT_MASK\t0x0000FFFF\n/* E1000_EITR_CNT_IGNR is only for 82576 and newer */\n#define E1000_EITR_CNT_IGNR\t0x80000000 /* Don't reset counters on write */\n#define E1000_EITR_INTERVAL 0x00007FFC\n\n/* Transmit Descriptor Control */\n#define E1000_TXDCTL_PTHRESH\t0x0000003F /* TXDCTL Prefetch Threshold */\n#define E1000_TXDCTL_HTHRESH\t0x00003F00 /* TXDCTL Host Threshold */\n#define E1000_TXDCTL_WTHRESH\t0x003F0000 /* TXDCTL Writeback Threshold */\n#define E1000_TXDCTL_GRAN\t0x01000000 /* TXDCTL Granularity */\n#define E1000_TXDCTL_FULL_TX_DESC_WB\t0x01010000 /* GRAN=1, WTHRESH=1 */\n#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */\n/* Enable the counting of descriptors still to be processed. */\n#define E1000_TXDCTL_COUNT_DESC\t0x00400000\n\n/* Flow Control Constants */\n#define FLOW_CONTROL_ADDRESS_LOW\t0x00C28001\n#define FLOW_CONTROL_ADDRESS_HIGH\t0x00000100\n#define FLOW_CONTROL_TYPE\t\t0x8808\n\n/* 802.1q VLAN Packet Size */\n#define VLAN_TAG_SIZE\t\t\t4 /* 802.3ac tag (not DMA'd) */\n#define E1000_VLAN_FILTER_TBL_SIZE\t128 /* VLAN Filter Table (4096 bits) */\n\n/* Receive Address\n * Number of high/low register pairs in the RAR. The RAR (Receive Address\n * Registers) holds the directed and multicast addresses that we monitor.\n * Technically, we have 16 spots. However, we reserve one of these spots\n * (RAR[15]) for our directed address used by controllers with\n * manageability enabled, allowing us room for 15 multicast addresses.\n */\n#define E1000_RAR_ENTRIES\t15\n#define E1000_RAH_AV\t\t0x80000000 /* Receive descriptor valid */\n#define E1000_RAL_MAC_ADDR_LEN\t4\n#define E1000_RAH_MAC_ADDR_LEN\t2\n#define E1000_RAH_QUEUE_MASK_82575\t0x000C0000\n#define E1000_RAH_POOL_1\t0x00040000\n\n/* Error Codes */\n#define E1000_SUCCESS\t\t\t0\n#define E1000_ERR_NVM\t\t\t1\n#define E1000_ERR_PHY\t\t\t2\n#define E1000_ERR_CONFIG\t\t3\n#define E1000_ERR_PARAM\t\t\t4\n#define E1000_ERR_MAC_INIT\t\t5\n#define E1000_ERR_PHY_TYPE\t\t6\n#define E1000_ERR_RESET\t\t\t9\n#define E1000_ERR_MASTER_REQUESTS_PENDING\t10\n#define E1000_ERR_HOST_INTERFACE_COMMAND\t11\n#define E1000_BLK_PHY_RESET\t\t12\n#define E1000_ERR_SWFW_SYNC\t\t13\n#define E1000_NOT_IMPLEMENTED\t\t14\n#define E1000_ERR_MBX\t\t\t15\n#define E1000_ERR_INVALID_ARGUMENT\t16\n#define E1000_ERR_NO_SPACE\t\t17\n#define E1000_ERR_NVM_PBA_SECTION\t18\n#define E1000_ERR_I2C\t\t\t19\n#define E1000_ERR_INVM_VALUE_NOT_FOUND\t20\n\n/* Loop limit on how long we wait for auto-negotiation to complete */\n#define FIBER_LINK_UP_LIMIT\t\t50\n#define COPPER_LINK_UP_LIMIT\t\t10\n#define PHY_AUTO_NEG_LIMIT\t\t45\n#define PHY_FORCE_LIMIT\t\t\t20\n/* Number of 100 microseconds we wait for PCI Express master disable */\n#define MASTER_DISABLE_TIMEOUT\t\t800\n/* Number of milliseconds we wait for PHY configuration done after MAC reset */\n#define PHY_CFG_TIMEOUT\t\t\t100\n/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */\n#define MDIO_OWNERSHIP_TIMEOUT\t\t10\n/* Number of milliseconds for NVM auto read done after MAC reset. */\n#define AUTO_READ_DONE_TIMEOUT\t\t10\n\n/* Flow Control */\n#define E1000_FCRTH_RTH\t\t0x0000FFF8 /* Mask Bits[15:3] for RTH */\n#define E1000_FCRTL_RTL\t\t0x0000FFF8 /* Mask Bits[15:3] for RTL */\n#define E1000_FCRTL_XONE\t0x80000000 /* Enable XON frame transmission */\n\n/* Transmit Configuration Word */\n#define E1000_TXCW_FD\t\t0x00000020 /* TXCW full duplex */\n#define E1000_TXCW_PAUSE\t0x00000080 /* TXCW sym pause request */\n#define E1000_TXCW_ASM_DIR\t0x00000100 /* TXCW astm pause direction */\n#define E1000_TXCW_PAUSE_MASK\t0x00000180 /* TXCW pause request mask */\n#define E1000_TXCW_ANE\t\t0x80000000 /* Auto-neg enable */\n\n/* Receive Configuration Word */\n#define E1000_RXCW_CW\t\t0x0000ffff /* RxConfigWord mask */\n#define E1000_RXCW_IV\t\t0x08000000 /* Receive config invalid */\n#define E1000_RXCW_C\t\t0x20000000 /* Receive config */\n#define E1000_RXCW_SYNCH\t0x40000000 /* Receive config synch */\n\n#define E1000_TSYNCTXCTL_VALID\t\t0x00000001 /* Tx timestamp valid */\n#define E1000_TSYNCTXCTL_ENABLED\t0x00000010 /* enable Tx timestamping */\n\n#define E1000_TSYNCRXCTL_VALID\t\t0x00000001 /* Rx timestamp valid */\n#define E1000_TSYNCRXCTL_TYPE_MASK\t0x0000000E /* Rx type mask */\n#define E1000_TSYNCRXCTL_TYPE_L2_V2\t0x00\n#define E1000_TSYNCRXCTL_TYPE_L4_V1\t0x02\n#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2\t0x04\n#define E1000_TSYNCRXCTL_TYPE_ALL\t0x08\n#define E1000_TSYNCRXCTL_TYPE_EVENT_V2\t0x0A\n#define E1000_TSYNCRXCTL_ENABLED\t0x00000010 /* enable Rx timestamping */\n#define E1000_TSYNCRXCTL_SYSCFI\t\t0x00000020 /* Sys clock frequency */\n\n#define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE\t0x00000000\n#define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE\t0x00010000\n\n#define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE\t0x00000000\n#define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE\t0x01000000\n\n#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK\t\t0x000000FF\n#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE\t\t0x00\n#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE\t0x01\n#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE\t0x02\n#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE\t0x03\n#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE\t0x04\n\n#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK\t\t0x00000F00\n#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE\t\t0x0000\n#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE\t0x0100\n#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE\t0x0200\n#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE\t0x0300\n#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE\t0x0800\n#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE\t0x0900\n#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00\n#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE\t0x0B00\n#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE\t0x0C00\n#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE\t0x0D00\n\n#define E1000_TIMINCA_16NS_SHIFT\t24\n#define E1000_TIMINCA_INCPERIOD_SHIFT\t24\n#define E1000_TIMINCA_INCVALUE_MASK\t0x00FFFFFF\n\n#define E1000_TSICR_TXTS\t\t0x00000002\n#define E1000_TSIM_TXTS\t\t\t0x00000002\n/* TUPLE Filtering Configuration */\n#define E1000_TTQF_DISABLE_MASK\t\t0xF0008000 /* TTQF Disable Mask */\n#define E1000_TTQF_QUEUE_ENABLE\t\t0x100 /* TTQF Queue Enable Bit */\n#define E1000_TTQF_PROTOCOL_MASK\t0xFF /* TTQF Protocol Mask */\n/* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */\n#define E1000_TTQF_PROTOCOL_TCP\t\t0x0\n/* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */\n#define E1000_TTQF_PROTOCOL_UDP\t\t0x1\n/* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */\n#define E1000_TTQF_PROTOCOL_SCTP\t0x2\n#define E1000_TTQF_PROTOCOL_SHIFT\t5 /* TTQF Protocol Shift */\n#define E1000_TTQF_QUEUE_SHIFT\t\t16 /* TTQF Queue Shfit */\n#define E1000_TTQF_RX_QUEUE_MASK\t0x70000 /* TTQF Queue Mask */\n#define E1000_TTQF_MASK_ENABLE\t\t0x10000000 /* TTQF Mask Enable Bit */\n#define E1000_IMIR_CLEAR_MASK\t\t0xF001FFFF /* IMIR Reg Clear Mask */\n#define E1000_IMIR_PORT_BYPASS\t\t0x20000 /* IMIR Port Bypass Bit */\n#define E1000_IMIR_PRIORITY_SHIFT\t29 /* IMIR Priority Shift */\n#define E1000_IMIREXT_CLEAR_MASK\t0x7FFFF /* IMIREXT Reg Clear Mask */\n\n#define E1000_MDICNFG_EXT_MDIO\t\t0x80000000 /* MDI ext/int destination */\n#define E1000_MDICNFG_COM_MDIO\t\t0x40000000 /* MDI shared w/ lan 0 */\n#define E1000_MDICNFG_PHY_MASK\t\t0x03E00000\n#define E1000_MDICNFG_PHY_SHIFT\t\t21\n\n#define E1000_MEDIA_PORT_COPPER\t\t\t1\n#define E1000_MEDIA_PORT_OTHER\t\t\t2\n#define E1000_M88E1112_AUTO_COPPER_SGMII\t0x2\n#define E1000_M88E1112_AUTO_COPPER_BASEX\t0x3\n#define E1000_M88E1112_STATUS_LINK\t\t0x0004 /* Interface Link Bit */\n#define E1000_M88E1112_MAC_CTRL_1\t\t0x10\n#define E1000_M88E1112_MAC_CTRL_1_MODE_MASK\t0x0380 /* Mode Select */\n#define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT\t7\n#define E1000_M88E1112_PAGE_ADDR\t\t0x16\n#define E1000_M88E1112_STATUS\t\t\t0x01\n\n#define E1000_THSTAT_LOW_EVENT\t\t0x20000000 /* Low thermal threshold */\n#define E1000_THSTAT_MID_EVENT\t\t0x00200000 /* Mid thermal threshold */\n#define E1000_THSTAT_HIGH_EVENT\t\t0x00002000 /* High thermal threshold */\n#define E1000_THSTAT_PWR_DOWN\t\t0x00000001 /* Power Down Event */\n#define E1000_THSTAT_LINK_THROTTLE\t0x00000002 /* Link Spd Throttle Event */\n\n/* I350 EEE defines */\n#define E1000_IPCNFG_EEE_1G_AN\t\t0x00000008 /* IPCNFG EEE Ena 1G AN */\n#define E1000_IPCNFG_EEE_100M_AN\t0x00000004 /* IPCNFG EEE Ena 100M AN */\n#define E1000_EEER_TX_LPI_EN\t\t0x00010000 /* EEER Tx LPI Enable */\n#define E1000_EEER_RX_LPI_EN\t\t0x00020000 /* EEER Rx LPI Enable */\n#define E1000_EEER_LPI_FC\t\t0x00040000 /* EEER Ena on Flow Cntrl */\n/* EEE status */\n#define E1000_EEER_EEE_NEG\t\t0x20000000 /* EEE capability nego */\n#define E1000_EEER_RX_LPI_STATUS\t0x40000000 /* Rx in LPI state */\n#define E1000_EEER_TX_LPI_STATUS\t0x80000000 /* Tx in LPI state */\n#define E1000_EEE_LP_ADV_ADDR_I350\t0x040F /* EEE LP Advertisement */\n#define E1000_M88E1543_PAGE_ADDR\t0x16 /* Page Offset Register */\n#define E1000_M88E1543_EEE_CTRL_1\t0x0\n#define E1000_M88E1543_EEE_CTRL_1_MS\t0x0001 /* EEE Master/Slave */\n#define E1000_EEE_ADV_DEV_I354\t\t7\n#define E1000_EEE_ADV_ADDR_I354\t\t60\n#define E1000_EEE_ADV_100_SUPPORTED\t(1 << 1) /* 100BaseTx EEE Supported */\n#define E1000_EEE_ADV_1000_SUPPORTED\t(1 << 2) /* 1000BaseT EEE Supported */\n#define E1000_PCS_STATUS_DEV_I354\t3\n#define E1000_PCS_STATUS_ADDR_I354\t1\n#define E1000_PCS_STATUS_RX_LPI_RCVD\t0x0400\n#define E1000_PCS_STATUS_TX_LPI_RCVD\t0x0800\n#define E1000_M88E1512_CFG_REG_1\t0x0010\n#define E1000_M88E1512_CFG_REG_2\t0x0011\n#define E1000_M88E1512_CFG_REG_3\t0x0007\n#define E1000_M88E1512_MODE\t\t0x0014\n#define E1000_EEE_SU_LPI_CLK_STP\t0x00800000 /* EEE LPI Clock Stop */\n#define E1000_EEE_LP_ADV_DEV_I210\t7 /* EEE LP Adv Device */\n#define E1000_EEE_LP_ADV_ADDR_I210\t61 /* EEE LP Adv Register */\n/* PCI Express Control */\n#define E1000_GCR_RXD_NO_SNOOP\t\t0x00000001\n#define E1000_GCR_RXDSCW_NO_SNOOP\t0x00000002\n#define E1000_GCR_RXDSCR_NO_SNOOP\t0x00000004\n#define E1000_GCR_TXD_NO_SNOOP\t\t0x00000008\n#define E1000_GCR_TXDSCW_NO_SNOOP\t0x00000010\n#define E1000_GCR_TXDSCR_NO_SNOOP\t0x00000020\n#define E1000_GCR_CMPL_TMOUT_MASK\t0x0000F000\n#define E1000_GCR_CMPL_TMOUT_10ms\t0x00001000\n#define E1000_GCR_CMPL_TMOUT_RESEND\t0x00010000\n#define E1000_GCR_CAP_VER2\t\t0x00040000\n\n#define PCIE_NO_SNOOP_ALL\t(E1000_GCR_RXD_NO_SNOOP | \\\n\t\t\t\t E1000_GCR_RXDSCW_NO_SNOOP | \\\n\t\t\t\t E1000_GCR_RXDSCR_NO_SNOOP | \\\n\t\t\t\t E1000_GCR_TXD_NO_SNOOP | \\\n\t\t\t\t E1000_GCR_TXDSCW_NO_SNOOP | \\\n\t\t\t\t E1000_GCR_TXDSCR_NO_SNOOP)\n\n#define E1000_MMDAC_FUNC_DATA\t0x4000 /* Data, no post increment */\n\n/* mPHY address control and data registers */\n#define E1000_MPHY_ADDR_CTL\t\t0x0024 /* Address Control Reg */\n#define E1000_MPHY_ADDR_CTL_OFFSET_MASK\t0xFFFF0000\n#define E1000_MPHY_DATA\t\t\t0x0E10 /* Data Register */\n\n/* AFE CSR Offset for PCS CLK */\n#define E1000_MPHY_PCS_CLK_REG_OFFSET\t0x0004\n/* Override for near end digital loopback. */\n#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN\t0x10\n\n/* PHY Control Register */\n#define MII_CR_SPEED_SELECT_MSB\t0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */\n#define MII_CR_COLL_TEST_ENABLE\t0x0080 /* Collision test enable */\n#define MII_CR_FULL_DUPLEX\t0x0100 /* FDX =1, half duplex =0 */\n#define MII_CR_RESTART_AUTO_NEG\t0x0200 /* Restart auto negotiation */\n#define MII_CR_ISOLATE\t\t0x0400 /* Isolate PHY from MII */\n#define MII_CR_POWER_DOWN\t0x0800 /* Power down */\n#define MII_CR_AUTO_NEG_EN\t0x1000 /* Auto Neg Enable */\n#define MII_CR_SPEED_SELECT_LSB\t0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */\n#define MII_CR_LOOPBACK\t\t0x4000 /* 0 = normal, 1 = loopback */\n#define MII_CR_RESET\t\t0x8000 /* 0 = normal, 1 = PHY reset */\n#define MII_CR_SPEED_1000\t0x0040\n#define MII_CR_SPEED_100\t0x2000\n#define MII_CR_SPEED_10\t\t0x0000\n\n/* PHY Status Register */\n#define MII_SR_EXTENDED_CAPS\t0x0001 /* Extended register capabilities */\n#define MII_SR_JABBER_DETECT\t0x0002 /* Jabber Detected */\n#define MII_SR_LINK_STATUS\t0x0004 /* Link Status 1 = link */\n#define MII_SR_AUTONEG_CAPS\t0x0008 /* Auto Neg Capable */\n#define MII_SR_REMOTE_FAULT\t0x0010 /* Remote Fault Detect */\n#define MII_SR_AUTONEG_COMPLETE\t0x0020 /* Auto Neg Complete */\n#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */\n#define MII_SR_EXTENDED_STATUS\t0x0100 /* Ext. status info in Reg 0x0F */\n#define MII_SR_100T2_HD_CAPS\t0x0200 /* 100T2 Half Duplex Capable */\n#define MII_SR_100T2_FD_CAPS\t0x0400 /* 100T2 Full Duplex Capable */\n#define MII_SR_10T_HD_CAPS\t0x0800 /* 10T Half Duplex Capable */\n#define MII_SR_10T_FD_CAPS\t0x1000 /* 10T Full Duplex Capable */\n#define MII_SR_100X_HD_CAPS\t0x2000 /* 100X Half Duplex Capable */\n#define MII_SR_100X_FD_CAPS\t0x4000 /* 100X Full Duplex Capable */\n#define MII_SR_100T4_CAPS\t0x8000 /* 100T4 Capable */\n\n/* Autoneg Advertisement Register */\n#define NWAY_AR_SELECTOR_FIELD\t0x0001 /* indicates IEEE 802.3 CSMA/CD */\n#define NWAY_AR_10T_HD_CAPS\t0x0020 /* 10T Half Duplex Capable */\n#define NWAY_AR_10T_FD_CAPS\t0x0040 /* 10T Full Duplex Capable */\n#define NWAY_AR_100TX_HD_CAPS\t0x0080 /* 100TX Half Duplex Capable */\n#define NWAY_AR_100TX_FD_CAPS\t0x0100 /* 100TX Full Duplex Capable */\n#define NWAY_AR_100T4_CAPS\t0x0200 /* 100T4 Capable */\n#define NWAY_AR_PAUSE\t\t0x0400 /* Pause operation desired */\n#define NWAY_AR_ASM_DIR\t\t0x0800 /* Asymmetric Pause Direction bit */\n#define NWAY_AR_REMOTE_FAULT\t0x2000 /* Remote Fault detected */\n#define NWAY_AR_NEXT_PAGE\t0x8000 /* Next Page ability supported */\n\n/* Link Partner Ability Register (Base Page) */\n#define NWAY_LPAR_SELECTOR_FIELD\t0x0000 /* LP protocol selector field */\n#define NWAY_LPAR_10T_HD_CAPS\t\t0x0020 /* LP 10T Half Dplx Capable */\n#define NWAY_LPAR_10T_FD_CAPS\t\t0x0040 /* LP 10T Full Dplx Capable */\n#define NWAY_LPAR_100TX_HD_CAPS\t\t0x0080 /* LP 100TX Half Dplx Capable */\n#define NWAY_LPAR_100TX_FD_CAPS\t\t0x0100 /* LP 100TX Full Dplx Capable */\n#define NWAY_LPAR_100T4_CAPS\t\t0x0200 /* LP is 100T4 Capable */\n#define NWAY_LPAR_PAUSE\t\t\t0x0400 /* LP Pause operation desired */\n#define NWAY_LPAR_ASM_DIR\t\t0x0800 /* LP Asym Pause Direction bit */\n#define NWAY_LPAR_REMOTE_FAULT\t\t0x2000 /* LP detected Remote Fault */\n#define NWAY_LPAR_ACKNOWLEDGE\t\t0x4000 /* LP rx'd link code word */\n#define NWAY_LPAR_NEXT_PAGE\t\t0x8000 /* Next Page ability supported */\n\n/* Autoneg Expansion Register */\n#define NWAY_ER_LP_NWAY_CAPS\t\t0x0001 /* LP has Auto Neg Capability */\n#define NWAY_ER_PAGE_RXD\t\t0x0002 /* LP 10T Half Dplx Capable */\n#define NWAY_ER_NEXT_PAGE_CAPS\t\t0x0004 /* LP 10T Full Dplx Capable */\n#define NWAY_ER_LP_NEXT_PAGE_CAPS\t0x0008 /* LP 100TX Half Dplx Capable */\n#define NWAY_ER_PAR_DETECT_FAULT\t0x0010 /* LP 100TX Full Dplx Capable */\n\n/* 1000BASE-T Control Register */\n#define CR_1000T_ASYM_PAUSE\t0x0080 /* Advertise asymmetric pause bit */\n#define CR_1000T_HD_CAPS\t0x0100 /* Advertise 1000T HD capability */\n#define CR_1000T_FD_CAPS\t0x0200 /* Advertise 1000T FD capability */\n/* 1=Repeater/switch device port 0=DTE device */\n#define CR_1000T_REPEATER_DTE\t0x0400\n/* 1=Configure PHY as Master 0=Configure PHY as Slave */\n#define CR_1000T_MS_VALUE\t0x0800\n/* 1=Master/Slave manual config value 0=Automatic Master/Slave config */\n#define CR_1000T_MS_ENABLE\t0x1000\n#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */\n#define CR_1000T_TEST_MODE_1\t0x2000 /* Transmit Waveform test */\n#define CR_1000T_TEST_MODE_2\t0x4000 /* Master Transmit Jitter test */\n#define CR_1000T_TEST_MODE_3\t0x6000 /* Slave Transmit Jitter test */\n#define CR_1000T_TEST_MODE_4\t0x8000 /* Transmitter Distortion test */\n\n/* 1000BASE-T Status Register */\n#define SR_1000T_IDLE_ERROR_CNT\t\t0x00FF /* Num idle err since last rd */\n#define SR_1000T_ASYM_PAUSE_DIR\t\t0x0100 /* LP asym pause direction bit */\n#define SR_1000T_LP_HD_CAPS\t\t0x0400 /* LP is 1000T HD capable */\n#define SR_1000T_LP_FD_CAPS\t\t0x0800 /* LP is 1000T FD capable */\n#define SR_1000T_REMOTE_RX_STATUS\t0x1000 /* Remote receiver OK */\n#define SR_1000T_LOCAL_RX_STATUS\t0x2000 /* Local receiver OK */\n#define SR_1000T_MS_CONFIG_RES\t\t0x4000 /* 1=Local Tx Master, 0=Slave */\n#define SR_1000T_MS_CONFIG_FAULT\t0x8000 /* Master/Slave config fault */\n\n#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT\t5\n\n/* PHY 1000 MII Register/Bit Definitions */\n/* PHY Registers defined by IEEE */\n#define PHY_CONTROL\t\t0x00 /* Control Register */\n#define PHY_STATUS\t\t0x01 /* Status Register */\n#define PHY_ID1\t\t\t0x02 /* Phy Id Reg (word 1) */\n#define PHY_ID2\t\t\t0x03 /* Phy Id Reg (word 2) */\n#define PHY_AUTONEG_ADV\t\t0x04 /* Autoneg Advertisement */\n#define PHY_LP_ABILITY\t\t0x05 /* Link Partner Ability (Base Page) */\n#define PHY_AUTONEG_EXP\t\t0x06 /* Autoneg Expansion Reg */\n#define PHY_NEXT_PAGE_TX\t0x07 /* Next Page Tx */\n#define PHY_LP_NEXT_PAGE\t0x08 /* Link Partner Next Page */\n#define PHY_1000T_CTRL\t\t0x09 /* 1000Base-T Control Reg */\n#define PHY_1000T_STATUS\t0x0A /* 1000Base-T Status Reg */\n#define PHY_EXT_STATUS\t\t0x0F /* Extended Status Reg */\n\n#define PHY_CONTROL_LB\t\t0x4000 /* PHY Loopback bit */\n\n/* NVM Control */\n#define E1000_EECD_SK\t\t0x00000001 /* NVM Clock */\n#define E1000_EECD_CS\t\t0x00000002 /* NVM Chip Select */\n#define E1000_EECD_DI\t\t0x00000004 /* NVM Data In */\n#define E1000_EECD_DO\t\t0x00000008 /* NVM Data Out */\n#define E1000_EECD_REQ\t\t0x00000040 /* NVM Access Request */\n#define E1000_EECD_GNT\t\t0x00000080 /* NVM Access Grant */\n#define E1000_EECD_PRES\t\t0x00000100 /* NVM Present */\n#define E1000_EECD_SIZE\t\t0x00000200 /* NVM Size (0=64 word 1=256 word) */\n#define E1000_EECD_BLOCKED\t0x00008000 /* Bit banging access blocked flag */\n#define E1000_EECD_ABORT\t0x00010000 /* NVM operation aborted flag */\n#define E1000_EECD_TIMEOUT\t0x00020000 /* NVM read operation timeout flag */\n#define E1000_EECD_ERROR_CLR\t0x00040000 /* NVM error status clear bit */\n/* NVM Addressing bits based on type 0=small, 1=large */\n#define E1000_EECD_ADDR_BITS\t0x00000400\n#define E1000_EECD_TYPE\t\t0x00002000 /* NVM Type (1-SPI, 0-Microwire) */\n#ifndef E1000_NVM_GRANT_ATTEMPTS\n#define E1000_NVM_GRANT_ATTEMPTS\t1000 /* NVM # attempts to gain grant */\n#endif\n#define E1000_EECD_AUTO_RD\t\t0x00000200 /* NVM Auto Read done */\n#define E1000_EECD_SIZE_EX_MASK\t\t0x00007800 /* NVM Size */\n#define E1000_EECD_SIZE_EX_SHIFT\t11\n#define E1000_EECD_FLUPD\t\t0x00080000 /* Update FLASH */\n#define E1000_EECD_AUPDEN\t\t0x00100000 /* Ena Auto FLASH update */\n#define E1000_EECD_SEC1VAL\t\t0x00400000 /* Sector One Valid */\n#define E1000_EECD_SEC1VAL_VALID_MASK\t(E1000_EECD_AUTO_RD | E1000_EECD_PRES)\n#define E1000_EECD_FLUPD_I210\t\t0x00800000 /* Update FLASH */\n#define E1000_EECD_FLUDONE_I210\t\t0x04000000 /* Update FLASH done */\n#define E1000_EECD_FLASH_DETECTED_I210\t0x00080000 /* FLASH detected */\n#define E1000_EECD_SEC1VAL_I210\t\t0x02000000 /* Sector One Valid */\n#define E1000_FLUDONE_ATTEMPTS\t\t20000\n#define E1000_EERD_EEWR_MAX_COUNT\t512 /* buffered EEPROM words rw */\n#define E1000_I210_FIFO_SEL_RX\t\t0x00\n#define E1000_I210_FIFO_SEL_TX_QAV(_i)\t(0x02 + (_i))\n#define E1000_I210_FIFO_SEL_TX_LEGACY\tE1000_I210_FIFO_SEL_TX_QAV(0)\n#define E1000_I210_FIFO_SEL_BMC2OS_TX\t0x06\n#define E1000_I210_FIFO_SEL_BMC2OS_RX\t0x01\n\n#define E1000_I210_FLASH_SECTOR_SIZE\t0x1000 /* 4KB FLASH sector unit size */\n/* Secure FLASH mode requires removing MSb */\n#define E1000_I210_FW_PTR_MASK\t\t0x7FFF\n/* Firmware code revision field word offset*/\n#define E1000_I210_FW_VER_OFFSET\t328\n\n#define E1000_NVM_RW_REG_DATA\t16 /* Offset to data in NVM read/write regs */\n#define E1000_NVM_RW_REG_DONE\t2 /* Offset to READ/WRITE done bit */\n#define E1000_NVM_RW_REG_START\t1 /* Start operation */\n#define E1000_NVM_RW_ADDR_SHIFT\t2 /* Shift to the address bits */\n#define E1000_NVM_POLL_WRITE\t1 /* Flag for polling for write complete */\n#define E1000_NVM_POLL_READ\t0 /* Flag for polling for read complete */\n#define E1000_FLASH_UPDATES\t2000\n\n/* NVM Word Offsets */\n#define NVM_COMPAT\t\t\t0x0003\n#define NVM_ID_LED_SETTINGS\t\t0x0004\n#define NVM_VERSION\t\t\t0x0005\n#define NVM_SERDES_AMPLITUDE\t\t0x0006 /* SERDES output amplitude */\n#define NVM_PHY_CLASS_WORD\t\t0x0007\n#define E1000_I210_NVM_FW_MODULE_PTR\t0x0010\n#define E1000_I350_NVM_FW_MODULE_PTR\t0x0051\n#define NVM_FUTURE_INIT_WORD1\t\t0x0019\n#define NVM_ETRACK_WORD\t\t\t0x0042\n#define NVM_ETRACK_HIWORD\t\t0x0043\n#define NVM_COMB_VER_OFF\t\t0x0083\n#define NVM_COMB_VER_PTR\t\t0x003d\n\n/* NVM version defines */\n#define NVM_MAJOR_MASK\t\t\t0xF000\n#define NVM_MINOR_MASK\t\t\t0x0FF0\n#define NVM_IMAGE_ID_MASK\t\t0x000F\n#define NVM_COMB_VER_MASK\t\t0x00FF\n#define NVM_MAJOR_SHIFT\t\t\t12\n#define NVM_MINOR_SHIFT\t\t\t4\n#define NVM_COMB_VER_SHFT\t\t8\n#define NVM_VER_INVALID\t\t\t0xFFFF\n#define NVM_ETRACK_SHIFT\t\t16\n#define NVM_ETRACK_VALID\t\t0x8000\n#define NVM_NEW_DEC_MASK\t\t0x0F00\n#define NVM_HEX_CONV\t\t\t16\n#define NVM_HEX_TENS\t\t\t10\n\n/* FW version defines */\n/* Offset of \"Loader patch ptr\" in Firmware Header */\n#define E1000_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET\t0x01\n/* Patch generation hour & minutes */\n#define E1000_I350_NVM_FW_VER_WORD1_OFFSET\t\t0x04\n/* Patch generation month & day */\n#define E1000_I350_NVM_FW_VER_WORD2_OFFSET\t\t0x05\n/* Patch generation year */\n#define E1000_I350_NVM_FW_VER_WORD3_OFFSET\t\t0x06\n/* Patch major & minor numbers */\n#define E1000_I350_NVM_FW_VER_WORD4_OFFSET\t\t0x07\n\n#define NVM_MAC_ADDR\t\t\t0x0000\n#define NVM_SUB_DEV_ID\t\t\t0x000B\n#define NVM_SUB_VEN_ID\t\t\t0x000C\n#define NVM_DEV_ID\t\t\t0x000D\n#define NVM_VEN_ID\t\t\t0x000E\n#define NVM_INIT_CTRL_2\t\t\t0x000F\n#define NVM_INIT_CTRL_4\t\t\t0x0013\n#define NVM_LED_1_CFG\t\t\t0x001C\n#define NVM_LED_0_2_CFG\t\t\t0x001F\n\n#define NVM_COMPAT_VALID_CSUM\t\t0x0001\n#define NVM_FUTURE_INIT_WORD1_VALID_CSUM\t0x0040\n\n#define NVM_INIT_CONTROL2_REG\t\t0x000F\n#define NVM_INIT_CONTROL3_PORT_B\t0x0014\n#define NVM_INIT_3GIO_3\t\t\t0x001A\n#define NVM_SWDEF_PINS_CTRL_PORT_0\t0x0020\n#define NVM_INIT_CONTROL3_PORT_A\t0x0024\n#define NVM_CFG\t\t\t\t0x0012\n#define NVM_ALT_MAC_ADDR_PTR\t\t0x0037\n#define NVM_CHECKSUM_REG\t\t0x003F\n#define NVM_COMPATIBILITY_REG_3\t\t0x0003\n#define NVM_COMPATIBILITY_BIT_MASK\t0x8000\n\n#define E1000_NVM_CFG_DONE_PORT_0\t0x040000 /* MNG config cycle done */\n#define E1000_NVM_CFG_DONE_PORT_1\t0x080000 /* ...for second port */\n#define E1000_NVM_CFG_DONE_PORT_2\t0x100000 /* ...for third port */\n#define E1000_NVM_CFG_DONE_PORT_3\t0x200000 /* ...for fourth port */\n\n#define NVM_82580_LAN_FUNC_OFFSET(a)\t((a) ? (0x40 + (0x40 * (a))) : 0)\n\n/* Mask bits for fields in Word 0x24 of the NVM */\n#define NVM_WORD24_COM_MDIO\t\t0x0008 /* MDIO interface shared */\n#define NVM_WORD24_EXT_MDIO\t\t0x0004 /* MDIO accesses routed extrnl */\n/* Offset of Link Mode bits for 82575/82576 */\n#define NVM_WORD24_LNK_MODE_OFFSET\t8\n/* Offset of Link Mode bits for 82580 up */\n#define NVM_WORD24_82580_LNK_MODE_OFFSET\t4\n\n\n/* Mask bits for fields in Word 0x0f of the NVM */\n#define NVM_WORD0F_PAUSE_MASK\t\t0x3000\n#define NVM_WORD0F_PAUSE\t\t0x1000\n#define NVM_WORD0F_ASM_DIR\t\t0x2000\n#define NVM_WORD0F_SWPDIO_EXT_MASK\t0x00F0\n\n/* Mask bits for fields in Word 0x1a of the NVM */\n#define NVM_WORD1A_ASPM_MASK\t\t0x000C\n\n/* Mask bits for fields in Word 0x03 of the EEPROM */\n#define NVM_COMPAT_LOM\t\t\t0x0800\n\n/* length of string needed to store PBA number */\n#define E1000_PBANUM_LENGTH\t\t11\n\n/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */\n#define NVM_SUM\t\t\t\t0xBABA\n\n/* PBA (printed board assembly) number words */\n#define NVM_PBA_OFFSET_0\t\t8\n#define NVM_PBA_OFFSET_1\t\t9\n#define NVM_PBA_PTR_GUARD\t\t0xFAFA\n#define NVM_RESERVED_WORD\t\t0xFFFF\n#define NVM_PHY_CLASS_A\t\t\t0x8000\n#define NVM_SERDES_AMPLITUDE_MASK\t0x000F\n#define NVM_SIZE_MASK\t\t\t0x1C00\n#define NVM_SIZE_SHIFT\t\t\t10\n#define NVM_WORD_SIZE_BASE_SHIFT\t6\n#define NVM_SWDPIO_EXT_SHIFT\t\t4\n\n/* NVM Commands - Microwire */\n#define NVM_READ_OPCODE_MICROWIRE\t0x6 /* NVM read opcode */\n#define NVM_WRITE_OPCODE_MICROWIRE\t0x5 /* NVM write opcode */\n#define NVM_ERASE_OPCODE_MICROWIRE\t0x7 /* NVM erase opcode */\n#define NVM_EWEN_OPCODE_MICROWIRE\t0x13 /* NVM erase/write enable */\n#define NVM_EWDS_OPCODE_MICROWIRE\t0x10 /* NVM erase/write disable */\n\n/* NVM Commands - SPI */\n#define NVM_MAX_RETRY_SPI\t5000 /* Max wait of 5ms, for RDY signal */\n#define NVM_READ_OPCODE_SPI\t0x03 /* NVM read opcode */\n#define NVM_WRITE_OPCODE_SPI\t0x02 /* NVM write opcode */\n#define NVM_A8_OPCODE_SPI\t0x08 /* opcode bit-3 = address bit-8 */\n#define NVM_WREN_OPCODE_SPI\t0x06 /* NVM set Write Enable latch */\n#define NVM_RDSR_OPCODE_SPI\t0x05 /* NVM read Status register */\n\n/* SPI NVM Status Register */\n#define NVM_STATUS_RDY_SPI\t0x01\n\n/* Word definitions for ID LED Settings */\n#define ID_LED_RESERVED_0000\t0x0000\n#define ID_LED_RESERVED_FFFF\t0xFFFF\n#define ID_LED_DEFAULT\t\t((ID_LED_OFF1_ON2 << 12) | \\\n\t\t\t\t (ID_LED_OFF1_OFF2 << 8) | \\\n\t\t\t\t (ID_LED_DEF1_DEF2 << 4) | \\\n\t\t\t\t (ID_LED_DEF1_DEF2))\n#define ID_LED_DEF1_DEF2\t0x1\n#define ID_LED_DEF1_ON2\t\t0x2\n#define ID_LED_DEF1_OFF2\t0x3\n#define ID_LED_ON1_DEF2\t\t0x4\n#define ID_LED_ON1_ON2\t\t0x5\n#define ID_LED_ON1_OFF2\t\t0x6\n#define ID_LED_OFF1_DEF2\t0x7\n#define ID_LED_OFF1_ON2\t\t0x8\n#define ID_LED_OFF1_OFF2\t0x9\n\n#define IGP_ACTIVITY_LED_MASK\t0xFFFFF0FF\n#define IGP_ACTIVITY_LED_ENABLE\t0x0300\n#define IGP_LED3_MODE\t\t0x07000000\n\n/* PCI/PCI-X/PCI-EX Config space */\n#define PCIX_COMMAND_REGISTER\t\t0xE6\n#define PCIX_STATUS_REGISTER_LO\t\t0xE8\n#define PCIX_STATUS_REGISTER_HI\t\t0xEA\n#define PCI_HEADER_TYPE_REGISTER\t0x0E\n#define PCIE_LINK_STATUS\t\t0x12\n#define PCIE_DEVICE_CONTROL2\t\t0x28\n\n#define PCIX_COMMAND_MMRBC_MASK\t\t0x000C\n#define PCIX_COMMAND_MMRBC_SHIFT\t0x2\n#define PCIX_STATUS_HI_MMRBC_MASK\t0x0060\n#define PCIX_STATUS_HI_MMRBC_SHIFT\t0x5\n#define PCIX_STATUS_HI_MMRBC_4K\t\t0x3\n#define PCIX_STATUS_HI_MMRBC_2K\t\t0x2\n#define PCIX_STATUS_LO_FUNC_MASK\t0x7\n#define PCI_HEADER_TYPE_MULTIFUNC\t0x80\n#define PCIE_LINK_WIDTH_MASK\t\t0x3F0\n#define PCIE_LINK_WIDTH_SHIFT\t\t4\n#define PCIE_LINK_SPEED_MASK\t\t0x0F\n#define PCIE_LINK_SPEED_2500\t\t0x01\n#define PCIE_LINK_SPEED_5000\t\t0x02\n#define PCIE_DEVICE_CONTROL2_16ms\t0x0005\n\n#ifndef ETH_ADDR_LEN\n#define ETH_ADDR_LEN\t\t\t6\n#endif\n\n#define PHY_REVISION_MASK\t\t0xFFFFFFF0\n#define MAX_PHY_REG_ADDRESS\t\t0x1F /* 5 bit address bus (0-0x1F) */\n#define MAX_PHY_MULTI_PAGE_REG\t\t0xF\n\n/* Bit definitions for valid PHY IDs.\n * I = Integrated\n * E = External\n */\n#define M88E1000_E_PHY_ID\t0x01410C50\n#define M88E1000_I_PHY_ID\t0x01410C30\n#define M88E1011_I_PHY_ID\t0x01410C20\n#define IGP01E1000_I_PHY_ID\t0x02A80380\n#define M88E1111_I_PHY_ID\t0x01410CC0\n#define M88E1543_E_PHY_ID\t0x01410EA0\n#define M88E1512_E_PHY_ID\t0x01410DD0\n#define M88E1112_E_PHY_ID\t0x01410C90\n#define I347AT4_E_PHY_ID\t0x01410DC0\n#define M88E1340M_E_PHY_ID\t0x01410DF0\n#define GG82563_E_PHY_ID\t0x01410CA0\n#define IGP03E1000_E_PHY_ID\t0x02A80390\n#define IFE_E_PHY_ID\t\t0x02A80330\n#define IFE_PLUS_E_PHY_ID\t0x02A80320\n#define IFE_C_E_PHY_ID\t\t0x02A80310\n#define BME1000_E_PHY_ID\t0x01410CB0\n#define BME1000_E_PHY_ID_R2\t0x01410CB1\n#define I82577_E_PHY_ID\t\t0x01540050\n#define I82578_E_PHY_ID\t\t0x004DD040\n#define I82579_E_PHY_ID\t\t0x01540090\n#define I217_E_PHY_ID\t\t0x015400A0\n#define I82580_I_PHY_ID\t\t0x015403A0\n#define I350_I_PHY_ID\t\t0x015403B0\n#define I210_I_PHY_ID\t\t0x01410C00\n#define IGP04E1000_E_PHY_ID\t0x02A80391\n#define M88_VENDOR\t\t0x0141\n\n/* M88E1000 Specific Registers */\n#define M88E1000_PHY_SPEC_CTRL\t\t0x10 /* PHY Specific Control Reg */\n#define M88E1000_PHY_SPEC_STATUS\t0x11 /* PHY Specific Status Reg */\n#define M88E1000_EXT_PHY_SPEC_CTRL\t0x14 /* Extended PHY Specific Cntrl */\n#define M88E1000_RX_ERR_CNTR\t\t0x15 /* Receive Error Counter */\n\n#define M88E1000_PHY_EXT_CTRL\t\t0x1A /* PHY extend control register */\n#define M88E1000_PHY_PAGE_SELECT\t0x1D /* Reg 29 for pg number setting */\n#define M88E1000_PHY_GEN_CONTROL\t0x1E /* meaning depends on reg 29 */\n#define M88E1000_PHY_VCO_REG_BIT8\t0x100 /* Bits 8 & 11 are adjusted for */\n#define M88E1000_PHY_VCO_REG_BIT11\t0x800 /* improved BER performance */\n\n/* M88E1000 PHY Specific Control Register */\n#define M88E1000_PSCR_POLARITY_REVERSAL\t0x0002 /* 1=Polarity Reverse enabled */\n/* MDI Crossover Mode bits 6:5 Manual MDI configuration */\n#define M88E1000_PSCR_MDI_MANUAL_MODE\t0x0000\n#define M88E1000_PSCR_MDIX_MANUAL_MODE\t0x0020 /* Manual MDIX configuration */\n/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */\n#define M88E1000_PSCR_AUTO_X_1000T\t0x0040\n/* Auto crossover enabled all speeds */\n#define M88E1000_PSCR_AUTO_X_MODE\t0x0060\n#define M88E1000_PSCR_ASSERT_CRS_ON_TX\t0x0800 /* 1=Assert CRS on Tx */\n\n/* M88E1000 PHY Specific Status Register */\n#define M88E1000_PSSR_REV_POLARITY\t0x0002 /* 1=Polarity reversed */\n#define M88E1000_PSSR_DOWNSHIFT\t\t0x0020 /* 1=Downshifted */\n#define M88E1000_PSSR_MDIX\t\t0x0040 /* 1=MDIX; 0=MDI */\n/* 0 = <50M\n * 1 = 50-80M\n * 2 = 80-110M\n * 3 = 110-140M\n * 4 = >140M\n */\n#define M88E1000_PSSR_CABLE_LENGTH\t0x0380\n#define M88E1000_PSSR_LINK\t\t0x0400 /* 1=Link up, 0=Link down */\n#define M88E1000_PSSR_SPD_DPLX_RESOLVED\t0x0800 /* 1=Speed & Duplex resolved */\n#define M88E1000_PSSR_DPLX\t\t0x2000 /* 1=Duplex 0=Half Duplex */\n#define M88E1000_PSSR_SPEED\t\t0xC000 /* Speed, bits 14:15 */\n#define M88E1000_PSSR_100MBS\t\t0x4000 /* 01=100Mbs */\n#define M88E1000_PSSR_1000MBS\t\t0x8000 /* 10=1000Mbs */\n\n#define M88E1000_PSSR_CABLE_LENGTH_SHIFT\t7\n\n/* Number of times we will attempt to autonegotiate before downshifting if we\n * are the master\n */\n#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK\t0x0C00\n#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X\t0x0000\n/* Number of times we will attempt to autonegotiate before downshifting if we\n * are the slave\n */\n#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK\t0x0300\n#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X\t0x0100\n#define M88E1000_EPSCR_TX_CLK_25\t0x0070 /* 25 MHz TX_CLK */\n\n/* Intel I347AT4 Registers */\n#define I347AT4_PCDL\t\t0x10 /* PHY Cable Diagnostics Length */\n#define I347AT4_PCDC\t\t0x15 /* PHY Cable Diagnostics Control */\n#define I347AT4_PAGE_SELECT\t0x16\n\n/* I347AT4 Extended PHY Specific Control Register */\n\n/* Number of times we will attempt to autonegotiate before downshifting if we\n * are the master\n */\n#define I347AT4_PSCR_DOWNSHIFT_ENABLE\t0x0800\n#define I347AT4_PSCR_DOWNSHIFT_MASK\t0x7000\n#define I347AT4_PSCR_DOWNSHIFT_1X\t0x0000\n#define I347AT4_PSCR_DOWNSHIFT_2X\t0x1000\n#define I347AT4_PSCR_DOWNSHIFT_3X\t0x2000\n#define I347AT4_PSCR_DOWNSHIFT_4X\t0x3000\n#define I347AT4_PSCR_DOWNSHIFT_5X\t0x4000\n#define I347AT4_PSCR_DOWNSHIFT_6X\t0x5000\n#define I347AT4_PSCR_DOWNSHIFT_7X\t0x6000\n#define I347AT4_PSCR_DOWNSHIFT_8X\t0x7000\n\n/* I347AT4 PHY Cable Diagnostics Control */\n#define I347AT4_PCDC_CABLE_LENGTH_UNIT\t0x0400 /* 0=cm 1=meters */\n\n/* M88E1112 only registers */\n#define M88E1112_VCT_DSP_DISTANCE\t0x001A\n\n/* M88EC018 Rev 2 specific DownShift settings */\n#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK\t0x0E00\n#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X\t0x0800\n\n#define I82578_EPSCR_DOWNSHIFT_ENABLE\t\t0x0020\n#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK\t0x001C\n\n/* BME1000 PHY Specific Control Register */\n#define BME1000_PSCR_ENABLE_DOWNSHIFT\t0x0800 /* 1 = enable downshift */\n\n/* Bits...\n * 15-5: page\n * 4-0: register offset\n */\n#define GG82563_PAGE_SHIFT\t5\n#define GG82563_REG(page, reg)\t\\\n\t(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))\n#define GG82563_MIN_ALT_REG\t30\n\n/* GG82563 Specific Registers */\n#define GG82563_PHY_SPEC_CTRL\t\tGG82563_REG(0, 16) /* PHY Spec Cntrl */\n#define GG82563_PHY_PAGE_SELECT\t\tGG82563_REG(0, 22) /* Page Select */\n#define GG82563_PHY_SPEC_CTRL_2\t\tGG82563_REG(0, 26) /* PHY Spec Cntrl2 */\n#define GG82563_PHY_PAGE_SELECT_ALT\tGG82563_REG(0, 29) /* Alt Page Select */\n\n/* MAC Specific Control Register */\n#define GG82563_PHY_MAC_SPEC_CTRL\tGG82563_REG(2, 21)\n\n#define GG82563_PHY_DSP_DISTANCE\tGG82563_REG(5, 26) /* DSP Distance */\n\n/* Page 193 - Port Control Registers */\n/* Kumeran Mode Control */\n#define GG82563_PHY_KMRN_MODE_CTRL\tGG82563_REG(193, 16)\n#define GG82563_PHY_PWR_MGMT_CTRL\tGG82563_REG(193, 20) /* Pwr Mgt Ctrl */\n\n/* Page 194 - KMRN Registers */\n#define GG82563_PHY_INBAND_CTRL\t\tGG82563_REG(194, 18) /* Inband Ctrl */\n\n/* MDI Control */\n#define E1000_MDIC_REG_MASK\t0x001F0000\n#define E1000_MDIC_REG_SHIFT\t16\n#define E1000_MDIC_PHY_MASK\t0x03E00000\n#define E1000_MDIC_PHY_SHIFT\t21\n#define E1000_MDIC_OP_WRITE\t0x04000000\n#define E1000_MDIC_OP_READ\t0x08000000\n#define E1000_MDIC_READY\t0x10000000\n#define E1000_MDIC_ERROR\t0x40000000\n#define E1000_MDIC_DEST\t\t0x80000000\n\n/* SerDes Control */\n#define E1000_GEN_CTL_READY\t\t0x80000000\n#define E1000_GEN_CTL_ADDRESS_SHIFT\t8\n#define E1000_GEN_POLL_TIMEOUT\t\t640\n\n/* LinkSec register fields */\n#define E1000_LSECTXCAP_SUM_MASK\t0x00FF0000\n#define E1000_LSECTXCAP_SUM_SHIFT\t16\n#define E1000_LSECRXCAP_SUM_MASK\t0x00FF0000\n#define E1000_LSECRXCAP_SUM_SHIFT\t16\n\n#define E1000_LSECTXCTRL_EN_MASK\t0x00000003\n#define E1000_LSECTXCTRL_DISABLE\t0x0\n#define E1000_LSECTXCTRL_AUTH\t\t0x1\n#define E1000_LSECTXCTRL_AUTH_ENCRYPT\t0x2\n#define E1000_LSECTXCTRL_AISCI\t\t0x00000020\n#define E1000_LSECTXCTRL_PNTHRSH_MASK\t0xFFFFFF00\n#define E1000_LSECTXCTRL_RSV_MASK\t0x000000D8\n\n#define E1000_LSECRXCTRL_EN_MASK\t0x0000000C\n#define E1000_LSECRXCTRL_EN_SHIFT\t2\n#define E1000_LSECRXCTRL_DISABLE\t0x0\n#define E1000_LSECRXCTRL_CHECK\t\t0x1\n#define E1000_LSECRXCTRL_STRICT\t\t0x2\n#define E1000_LSECRXCTRL_DROP\t\t0x3\n#define E1000_LSECRXCTRL_PLSH\t\t0x00000040\n#define E1000_LSECRXCTRL_RP\t\t0x00000080\n#define E1000_LSECRXCTRL_RSV_MASK\t0xFFFFFF33\n\n/* Tx Rate-Scheduler Config fields */\n#define E1000_RTTBCNRC_RS_ENA\t\t0x80000000\n#define E1000_RTTBCNRC_RF_DEC_MASK\t0x00003FFF\n#define E1000_RTTBCNRC_RF_INT_SHIFT\t14\n#define E1000_RTTBCNRC_RF_INT_MASK\t\\\n\t(E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)\n\n/* DMA Coalescing register fields */\n/* DMA Coalescing Watchdog Timer */\n#define E1000_DMACR_DMACWT_MASK\t\t0x00003FFF\n/* DMA Coalescing Rx Threshold */\n#define E1000_DMACR_DMACTHR_MASK\t0x00FF0000\n#define E1000_DMACR_DMACTHR_SHIFT\t16\n/* Lx when no PCIe transactions */\n#define E1000_DMACR_DMAC_LX_MASK\t0x30000000\n#define E1000_DMACR_DMAC_LX_SHIFT\t28\n#define E1000_DMACR_DMAC_EN\t\t0x80000000 /* Enable DMA Coalescing */\n/* DMA Coalescing BMC-to-OS Watchdog Enable */\n#define E1000_DMACR_DC_BMC2OSW_EN\t0x00008000\n\n/* DMA Coalescing Transmit Threshold */\n#define E1000_DMCTXTH_DMCTTHR_MASK\t0x00000FFF\n\n#define E1000_DMCTLX_TTLX_MASK\t\t0x00000FFF /* Time to LX request */\n\n/* Rx Traffic Rate Threshold */\n#define E1000_DMCRTRH_UTRESH_MASK\t0x0007FFFF\n/* Rx packet rate in current window */\n#define E1000_DMCRTRH_LRPRCW\t\t0x80000000\n\n/* DMA Coal Rx Traffic Current Count */\n#define E1000_DMCCNT_CCOUNT_MASK\t0x01FFFFFF\n\n/* Flow ctrl Rx Threshold High val */\n#define E1000_FCRTC_RTH_COAL_MASK\t0x0003FFF0\n#define E1000_FCRTC_RTH_COAL_SHIFT\t4\n/* Lx power decision based on DMA coal */\n#define E1000_PCIEMISC_LX_DECISION\t0x00000080\n\n#define E1000_RXPBS_CFG_TS_EN\t\t0x80000000 /* Timestamp in Rx buffer */\n#define E1000_RXPBS_SIZE_I210_MASK\t0x0000003F /* Rx packet buffer size */\n#define E1000_TXPB0S_SIZE_I210_MASK\t0x0000003F /* Tx packet buffer 0 size */\n\n/* Proxy Filter Control */\n#define E1000_PROXYFC_D0\t\t0x00000001 /* Enable offload in D0 */\n#define E1000_PROXYFC_EX\t\t0x00000004 /* Directed exact proxy */\n#define E1000_PROXYFC_MC\t\t0x00000008 /* Directed MC Proxy */\n#define E1000_PROXYFC_BC\t\t0x00000010 /* Broadcast Proxy Enable */\n#define E1000_PROXYFC_ARP_DIRECTED\t0x00000020 /* Directed ARP Proxy Ena */\n#define E1000_PROXYFC_IPV4\t\t0x00000040 /* Directed IPv4 Enable */\n#define E1000_PROXYFC_IPV6\t\t0x00000080 /* Directed IPv6 Enable */\n#define E1000_PROXYFC_NS\t\t0x00000200 /* IPv6 Neighbor Solicitation */\n#define E1000_PROXYFC_ARP\t\t0x00000800 /* ARP Request Proxy Ena */\n/* Proxy Status */\n#define E1000_PROXYS_CLEAR\t\t0xFFFFFFFF /* Clear */\n\n/* Firmware Status */\n#define E1000_FWSTS_FWRI\t\t0x80000000 /* FW Reset Indication */\n/* VF Control */\n#define E1000_VTCTRL_RST\t\t0x04000000 /* Reset VF */\n\n#define E1000_STATUS_LAN_ID_MASK\t0x00000000C /* Mask for Lan ID field */\n/* Lan ID bit field offset in status register */\n#define E1000_STATUS_LAN_ID_OFFSET\t2\n#define E1000_VFTA_ENTRIES\t\t128\n#ifndef E1000_UNUSEDARG\n#define E1000_UNUSEDARG\n#endif /* E1000_UNUSEDARG */\n#ifndef ERROR_REPORT\n#define ERROR_REPORT(fmt)\tdo { } while (0)\n#endif /* ERROR_REPORT */\n#endif /* _E1000_DEFINES_H_ */\n" }, { "path": "drivers/net/e1000/base/e1000_hw.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_HW_H_\n#define _E1000_HW_H_\n\n#include \"e1000_osdep.h\"\n#include \"e1000_regs.h\"\n#include \"e1000_defines.h\"\n\nstruct e1000_hw;\n\n#define E1000_DEV_ID_82542\t\t\t0x1000\n#define E1000_DEV_ID_82543GC_FIBER\t\t0x1001\n#define E1000_DEV_ID_82543GC_COPPER\t\t0x1004\n#define E1000_DEV_ID_82544EI_COPPER\t\t0x1008\n#define E1000_DEV_ID_82544EI_FIBER\t\t0x1009\n#define E1000_DEV_ID_82544GC_COPPER\t\t0x100C\n#define E1000_DEV_ID_82544GC_LOM\t\t0x100D\n#define E1000_DEV_ID_82540EM\t\t\t0x100E\n#define E1000_DEV_ID_82540EM_LOM\t\t0x1015\n#define E1000_DEV_ID_82540EP_LOM\t\t0x1016\n#define E1000_DEV_ID_82540EP\t\t\t0x1017\n#define E1000_DEV_ID_82540EP_LP\t\t\t0x101E\n#define E1000_DEV_ID_82545EM_COPPER\t\t0x100F\n#define E1000_DEV_ID_82545EM_FIBER\t\t0x1011\n#define E1000_DEV_ID_82545GM_COPPER\t\t0x1026\n#define E1000_DEV_ID_82545GM_FIBER\t\t0x1027\n#define E1000_DEV_ID_82545GM_SERDES\t\t0x1028\n#define E1000_DEV_ID_82546EB_COPPER\t\t0x1010\n#define E1000_DEV_ID_82546EB_FIBER\t\t0x1012\n#define E1000_DEV_ID_82546EB_QUAD_COPPER\t0x101D\n#define E1000_DEV_ID_82546GB_COPPER\t\t0x1079\n#define E1000_DEV_ID_82546GB_FIBER\t\t0x107A\n#define E1000_DEV_ID_82546GB_SERDES\t\t0x107B\n#define E1000_DEV_ID_82546GB_PCIE\t\t0x108A\n#define E1000_DEV_ID_82546GB_QUAD_COPPER\t0x1099\n#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3\t0x10B5\n#define E1000_DEV_ID_82541EI\t\t\t0x1013\n#define E1000_DEV_ID_82541EI_MOBILE\t\t0x1018\n#define E1000_DEV_ID_82541ER_LOM\t\t0x1014\n#define E1000_DEV_ID_82541ER\t\t\t0x1078\n#define E1000_DEV_ID_82541GI\t\t\t0x1076\n#define E1000_DEV_ID_82541GI_LF\t\t\t0x107C\n#define E1000_DEV_ID_82541GI_MOBILE\t\t0x1077\n#define E1000_DEV_ID_82547EI\t\t\t0x1019\n#define E1000_DEV_ID_82547EI_MOBILE\t\t0x101A\n#define E1000_DEV_ID_82547GI\t\t\t0x1075\n#define E1000_DEV_ID_82571EB_COPPER\t\t0x105E\n#define E1000_DEV_ID_82571EB_FIBER\t\t0x105F\n#define E1000_DEV_ID_82571EB_SERDES\t\t0x1060\n#define E1000_DEV_ID_82571EB_SERDES_DUAL\t0x10D9\n#define E1000_DEV_ID_82571EB_SERDES_QUAD\t0x10DA\n#define E1000_DEV_ID_82571EB_QUAD_COPPER\t0x10A4\n#define E1000_DEV_ID_82571PT_QUAD_COPPER\t0x10D5\n#define E1000_DEV_ID_82571EB_QUAD_FIBER\t\t0x10A5\n#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP\t0x10BC\n#define E1000_DEV_ID_82572EI_COPPER\t\t0x107D\n#define E1000_DEV_ID_82572EI_FIBER\t\t0x107E\n#define E1000_DEV_ID_82572EI_SERDES\t\t0x107F\n#define E1000_DEV_ID_82572EI\t\t\t0x10B9\n#define E1000_DEV_ID_82573E\t\t\t0x108B\n#define E1000_DEV_ID_82573E_IAMT\t\t0x108C\n#define E1000_DEV_ID_82573L\t\t\t0x109A\n#define E1000_DEV_ID_82574L\t\t\t0x10D3\n#define E1000_DEV_ID_82574LA\t\t\t0x10F6\n#define E1000_DEV_ID_82583V\t\t\t0x150C\n#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT\t0x1096\n#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT\t0x1098\n#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT\t0x10BA\n#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT\t0x10BB\n#define E1000_DEV_ID_ICH8_82567V_3\t\t0x1501\n#define E1000_DEV_ID_ICH8_IGP_M_AMT\t\t0x1049\n#define E1000_DEV_ID_ICH8_IGP_AMT\t\t0x104A\n#define E1000_DEV_ID_ICH8_IGP_C\t\t\t0x104B\n#define E1000_DEV_ID_ICH8_IFE\t\t\t0x104C\n#define E1000_DEV_ID_ICH8_IFE_GT\t\t0x10C4\n#define E1000_DEV_ID_ICH8_IFE_G\t\t\t0x10C5\n#define E1000_DEV_ID_ICH8_IGP_M\t\t\t0x104D\n#define E1000_DEV_ID_ICH9_IGP_M\t\t\t0x10BF\n#define E1000_DEV_ID_ICH9_IGP_M_AMT\t\t0x10F5\n#define E1000_DEV_ID_ICH9_IGP_M_V\t\t0x10CB\n#define E1000_DEV_ID_ICH9_IGP_AMT\t\t0x10BD\n#define E1000_DEV_ID_ICH9_BM\t\t\t0x10E5\n#define E1000_DEV_ID_ICH9_IGP_C\t\t\t0x294C\n#define E1000_DEV_ID_ICH9_IFE\t\t\t0x10C0\n#define E1000_DEV_ID_ICH9_IFE_GT\t\t0x10C3\n#define E1000_DEV_ID_ICH9_IFE_G\t\t\t0x10C2\n#define E1000_DEV_ID_ICH10_R_BM_LM\t\t0x10CC\n#define E1000_DEV_ID_ICH10_R_BM_LF\t\t0x10CD\n#define E1000_DEV_ID_ICH10_R_BM_V\t\t0x10CE\n#define E1000_DEV_ID_ICH10_D_BM_LM\t\t0x10DE\n#define E1000_DEV_ID_ICH10_D_BM_LF\t\t0x10DF\n#define E1000_DEV_ID_ICH10_D_BM_V\t\t0x1525\n#define E1000_DEV_ID_PCH_M_HV_LM\t\t0x10EA\n#define E1000_DEV_ID_PCH_M_HV_LC\t\t0x10EB\n#define E1000_DEV_ID_PCH_D_HV_DM\t\t0x10EF\n#define E1000_DEV_ID_PCH_D_HV_DC\t\t0x10F0\n#define E1000_DEV_ID_PCH2_LV_LM\t\t\t0x1502\n#define E1000_DEV_ID_PCH2_LV_V\t\t\t0x1503\n#define E1000_DEV_ID_PCH_LPT_I217_LM\t\t0x153A\n#define E1000_DEV_ID_PCH_LPT_I217_V\t\t0x153B\n#define E1000_DEV_ID_PCH_LPTLP_I218_LM\t\t0x155A\n#define E1000_DEV_ID_PCH_LPTLP_I218_V\t\t0x1559\n#define E1000_DEV_ID_82576\t\t\t0x10C9\n#define E1000_DEV_ID_82576_FIBER\t\t0x10E6\n#define E1000_DEV_ID_82576_SERDES\t\t0x10E7\n#define E1000_DEV_ID_82576_QUAD_COPPER\t\t0x10E8\n#define E1000_DEV_ID_82576_QUAD_COPPER_ET2\t0x1526\n#define E1000_DEV_ID_82576_NS\t\t\t0x150A\n#define E1000_DEV_ID_82576_NS_SERDES\t\t0x1518\n#define E1000_DEV_ID_82576_SERDES_QUAD\t\t0x150D\n#define E1000_DEV_ID_82576_VF\t\t\t0x10CA\n#define E1000_DEV_ID_82576_VF_HV\t\t0x152D\n#define E1000_DEV_ID_I350_VF\t\t\t0x1520\n#define E1000_DEV_ID_I350_VF_HV\t\t\t0x152F\n#define E1000_DEV_ID_82575EB_COPPER\t\t0x10A7\n#define E1000_DEV_ID_82575EB_FIBER_SERDES\t0x10A9\n#define E1000_DEV_ID_82575GB_QUAD_COPPER\t0x10D6\n#define E1000_DEV_ID_82580_COPPER\t\t0x150E\n#define E1000_DEV_ID_82580_FIBER\t\t0x150F\n#define E1000_DEV_ID_82580_SERDES\t\t0x1510\n#define E1000_DEV_ID_82580_SGMII\t\t0x1511\n#define E1000_DEV_ID_82580_COPPER_DUAL\t\t0x1516\n#define E1000_DEV_ID_82580_QUAD_FIBER\t\t0x1527\n#define E1000_DEV_ID_I350_COPPER\t\t0x1521\n#define E1000_DEV_ID_I350_FIBER\t\t\t0x1522\n#define E1000_DEV_ID_I350_SERDES\t\t0x1523\n#define E1000_DEV_ID_I350_SGMII\t\t\t0x1524\n#define E1000_DEV_ID_I350_DA4\t\t\t0x1546\n#define E1000_DEV_ID_I210_COPPER\t\t0x1533\n#define E1000_DEV_ID_I210_COPPER_OEM1\t\t0x1534\n#define E1000_DEV_ID_I210_COPPER_IT\t\t0x1535\n#define E1000_DEV_ID_I210_FIBER\t\t\t0x1536\n#define E1000_DEV_ID_I210_SERDES\t\t0x1537\n#define E1000_DEV_ID_I210_SGMII\t\t\t0x1538\n#define E1000_DEV_ID_I210_COPPER_FLASHLESS\t0x157B\n#define E1000_DEV_ID_I210_SERDES_FLASHLESS\t0x157C\n#define E1000_DEV_ID_I211_COPPER\t\t0x1539\n#define E1000_DEV_ID_I354_BACKPLANE_1GBPS\t0x1F40\n#define E1000_DEV_ID_I354_SGMII\t\t\t0x1F41\n#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS\t0x1F45\n#define E1000_DEV_ID_DH89XXCC_SGMII\t\t0x0438\n#define E1000_DEV_ID_DH89XXCC_SERDES\t\t0x043A\n#define E1000_DEV_ID_DH89XXCC_BACKPLANE\t\t0x043C\n#define E1000_DEV_ID_DH89XXCC_SFP\t\t0x0440\n\n#define E1000_REVISION_0\t0\n#define E1000_REVISION_1\t1\n#define E1000_REVISION_2\t2\n#define E1000_REVISION_3\t3\n#define E1000_REVISION_4\t4\n\n#define E1000_FUNC_0\t\t0\n#define E1000_FUNC_1\t\t1\n#define E1000_FUNC_2\t\t2\n#define E1000_FUNC_3\t\t3\n\n#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0\t0\n#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1\t3\n#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2\t6\n#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3\t9\n\nenum e1000_mac_type {\n\te1000_undefined = 0,\n\te1000_82542,\n\te1000_82543,\n\te1000_82544,\n\te1000_82540,\n\te1000_82545,\n\te1000_82545_rev_3,\n\te1000_82546,\n\te1000_82546_rev_3,\n\te1000_82541,\n\te1000_82541_rev_2,\n\te1000_82547,\n\te1000_82547_rev_2,\n\te1000_82571,\n\te1000_82572,\n\te1000_82573,\n\te1000_82574,\n\te1000_82583,\n\te1000_80003es2lan,\n\te1000_ich8lan,\n\te1000_ich9lan,\n\te1000_ich10lan,\n\te1000_pchlan,\n\te1000_pch2lan,\n\te1000_pch_lpt,\n\te1000_82575,\n\te1000_82576,\n\te1000_82580,\n\te1000_i350,\n\te1000_i354,\n\te1000_i210,\n\te1000_i211,\n\te1000_vfadapt,\n\te1000_vfadapt_i350,\n\te1000_num_macs /* List is 1-based, so subtract 1 for true count. */\n};\n\nenum e1000_media_type {\n\te1000_media_type_unknown = 0,\n\te1000_media_type_copper = 1,\n\te1000_media_type_fiber = 2,\n\te1000_media_type_internal_serdes = 3,\n\te1000_num_media_types\n};\n\nenum e1000_nvm_type {\n\te1000_nvm_unknown = 0,\n\te1000_nvm_none,\n\te1000_nvm_eeprom_spi,\n\te1000_nvm_eeprom_microwire,\n\te1000_nvm_flash_hw,\n\te1000_nvm_invm,\n\te1000_nvm_flash_sw\n};\n\nenum e1000_nvm_override {\n\te1000_nvm_override_none = 0,\n\te1000_nvm_override_spi_small,\n\te1000_nvm_override_spi_large,\n\te1000_nvm_override_microwire_small,\n\te1000_nvm_override_microwire_large\n};\n\nenum e1000_phy_type {\n\te1000_phy_unknown = 0,\n\te1000_phy_none,\n\te1000_phy_m88,\n\te1000_phy_igp,\n\te1000_phy_igp_2,\n\te1000_phy_gg82563,\n\te1000_phy_igp_3,\n\te1000_phy_ife,\n\te1000_phy_bm,\n\te1000_phy_82578,\n\te1000_phy_82577,\n\te1000_phy_82579,\n\te1000_phy_i217,\n\te1000_phy_82580,\n\te1000_phy_vf,\n\te1000_phy_i210,\n};\n\nenum e1000_bus_type {\n\te1000_bus_type_unknown = 0,\n\te1000_bus_type_pci,\n\te1000_bus_type_pcix,\n\te1000_bus_type_pci_express,\n\te1000_bus_type_reserved\n};\n\nenum e1000_bus_speed {\n\te1000_bus_speed_unknown = 0,\n\te1000_bus_speed_33,\n\te1000_bus_speed_66,\n\te1000_bus_speed_100,\n\te1000_bus_speed_120,\n\te1000_bus_speed_133,\n\te1000_bus_speed_2500,\n\te1000_bus_speed_5000,\n\te1000_bus_speed_reserved\n};\n\nenum e1000_bus_width {\n\te1000_bus_width_unknown = 0,\n\te1000_bus_width_pcie_x1,\n\te1000_bus_width_pcie_x2,\n\te1000_bus_width_pcie_x4 = 4,\n\te1000_bus_width_pcie_x8 = 8,\n\te1000_bus_width_32,\n\te1000_bus_width_64,\n\te1000_bus_width_reserved\n};\n\nenum e1000_1000t_rx_status {\n\te1000_1000t_rx_status_not_ok = 0,\n\te1000_1000t_rx_status_ok,\n\te1000_1000t_rx_status_undefined = 0xFF\n};\n\nenum e1000_rev_polarity {\n\te1000_rev_polarity_normal = 0,\n\te1000_rev_polarity_reversed,\n\te1000_rev_polarity_undefined = 0xFF\n};\n\nenum e1000_fc_mode {\n\te1000_fc_none = 0,\n\te1000_fc_rx_pause,\n\te1000_fc_tx_pause,\n\te1000_fc_full,\n\te1000_fc_default = 0xFF\n};\n\nenum e1000_ffe_config {\n\te1000_ffe_config_enabled = 0,\n\te1000_ffe_config_active,\n\te1000_ffe_config_blocked\n};\n\nenum e1000_dsp_config {\n\te1000_dsp_config_disabled = 0,\n\te1000_dsp_config_enabled,\n\te1000_dsp_config_activated,\n\te1000_dsp_config_undefined = 0xFF\n};\n\nenum e1000_ms_type {\n\te1000_ms_hw_default = 0,\n\te1000_ms_force_master,\n\te1000_ms_force_slave,\n\te1000_ms_auto\n};\n\nenum e1000_smart_speed {\n\te1000_smart_speed_default = 0,\n\te1000_smart_speed_on,\n\te1000_smart_speed_off\n};\n\nenum e1000_serdes_link_state {\n\te1000_serdes_link_down = 0,\n\te1000_serdes_link_autoneg_progress,\n\te1000_serdes_link_autoneg_complete,\n\te1000_serdes_link_forced_up\n};\n\n#define __le16 u16\n#define __le32 u32\n#define __le64 u64\n/* Receive Descriptor */\nstruct e1000_rx_desc {\n\t__le64 buffer_addr; /* Address of the descriptor's data buffer */\n\t__le16 length; /* Length of data DMAed into data buffer */\n\t__le16 csum; /* Packet checksum */\n\tu8 status; /* Descriptor status */\n\tu8 errors; /* Descriptor Errors */\n\t__le16 special;\n};\n\n/* Receive Descriptor - Extended */\nunion e1000_rx_desc_extended {\n\tstruct {\n\t\t__le64 buffer_addr;\n\t\t__le64 reserved;\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq; /* Multiple Rx Queues */\n\t\t\tunion {\n\t\t\t\t__le32 rss; /* RSS Hash */\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id; /* IP id */\n\t\t\t\t\t__le16 csum; /* Packet Checksum */\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error; /* ext status/error */\n\t\t\t__le16 length;\n\t\t\t__le16 vlan; /* VLAN tag */\n\t\t} upper;\n\t} wb; /* writeback */\n};\n\n#define MAX_PS_BUFFERS 4\n\n/* Number of packet split data buffers (not including the header buffer) */\n#define PS_PAGE_BUFFERS\t(MAX_PS_BUFFERS - 1)\n\n/* Receive Descriptor - Packet Split */\nunion e1000_rx_desc_packet_split {\n\tstruct {\n\t\t/* one buffer for protocol header(s), three data buffers */\n\t\t__le64 buffer_addr[MAX_PS_BUFFERS];\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq; /* Multiple Rx Queues */\n\t\t\tunion {\n\t\t\t\t__le32 rss; /* RSS Hash */\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id; /* IP id */\n\t\t\t\t\t__le16 csum; /* Packet Checksum */\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error; /* ext status/error */\n\t\t\t__le16 length0; /* length of buffer 0 */\n\t\t\t__le16 vlan; /* VLAN tag */\n\t\t} middle;\n\t\tstruct {\n\t\t\t__le16 header_status;\n\t\t\t/* length of buffers 1-3 */\n\t\t\t__le16 length[PS_PAGE_BUFFERS];\n\t\t} upper;\n\t\t__le64 reserved;\n\t} wb; /* writeback */\n};\n\n/* Transmit Descriptor */\nstruct e1000_tx_desc {\n\t__le64 buffer_addr; /* Address of the descriptor's data buffer */\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\t__le16 length; /* Data buffer length */\n\t\t\tu8 cso; /* Checksum offset */\n\t\t\tu8 cmd; /* Descriptor control */\n\t\t} flags;\n\t} lower;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status; /* Descriptor status */\n\t\t\tu8 css; /* Checksum start */\n\t\t\t__le16 special;\n\t\t} fields;\n\t} upper;\n};\n\n/* Offload Context Descriptor */\nstruct e1000_context_desc {\n\tunion {\n\t\t__le32 ip_config;\n\t\tstruct {\n\t\t\tu8 ipcss; /* IP checksum start */\n\t\t\tu8 ipcso; /* IP checksum offset */\n\t\t\t__le16 ipcse; /* IP checksum end */\n\t\t} ip_fields;\n\t} lower_setup;\n\tunion {\n\t\t__le32 tcp_config;\n\t\tstruct {\n\t\t\tu8 tucss; /* TCP checksum start */\n\t\t\tu8 tucso; /* TCP checksum offset */\n\t\t\t__le16 tucse; /* TCP checksum end */\n\t\t} tcp_fields;\n\t} upper_setup;\n\t__le32 cmd_and_length;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status; /* Descriptor status */\n\t\t\tu8 hdr_len; /* Header length */\n\t\t\t__le16 mss; /* Maximum segment size */\n\t\t} fields;\n\t} tcp_seg_setup;\n};\n\n/* Offload data descriptor */\nstruct e1000_data_desc {\n\t__le64 buffer_addr; /* Address of the descriptor's buffer address */\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\t__le16 length; /* Data buffer length */\n\t\t\tu8 typ_len_ext;\n\t\t\tu8 cmd;\n\t\t} flags;\n\t} lower;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status; /* Descriptor status */\n\t\t\tu8 popts; /* Packet Options */\n\t\t\t__le16 special;\n\t\t} fields;\n\t} upper;\n};\n\n/* Statistics counters collected by the MAC */\nstruct e1000_hw_stats {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 tor;\n\tu64 tot;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n\tu64 cbtmpc;\n\tu64 htdpmc;\n\tu64 cbrdpc;\n\tu64 cbrmpc;\n\tu64 rpthc;\n\tu64 hgptc;\n\tu64 htcbdpc;\n\tu64 hgorc;\n\tu64 hgotc;\n\tu64 lenerrs;\n\tu64 scvpc;\n\tu64 hrmpc;\n\tu64 doosync;\n\tu64 o2bgptc;\n\tu64 o2bspc;\n\tu64 b2ospc;\n\tu64 b2ogprc;\n};\n\nstruct e1000_vf_stats {\n\tu64 base_gprc;\n\tu64 base_gptc;\n\tu64 base_gorc;\n\tu64 base_gotc;\n\tu64 base_mprc;\n\tu64 base_gotlbc;\n\tu64 base_gptlbc;\n\tu64 base_gorlbc;\n\tu64 base_gprlbc;\n\n\tu32 last_gprc;\n\tu32 last_gptc;\n\tu32 last_gorc;\n\tu32 last_gotc;\n\tu32 last_mprc;\n\tu32 last_gotlbc;\n\tu32 last_gptlbc;\n\tu32 last_gorlbc;\n\tu32 last_gprlbc;\n\n\tu64 gprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 mprc;\n\tu64 gotlbc;\n\tu64 gptlbc;\n\tu64 gorlbc;\n\tu64 gprlbc;\n};\n\nstruct e1000_phy_stats {\n\tu32 idle_errors;\n\tu32 receive_errors;\n};\n\nstruct e1000_host_mng_dhcp_cookie {\n\tu32 signature;\n\tu8 status;\n\tu8 reserved0;\n\tu16 vlan_id;\n\tu32 reserved1;\n\tu16 reserved2;\n\tu8 reserved3;\n\tu8 checksum;\n};\n\n/* Host Interface \"Rev 1\" */\nstruct e1000_host_command_header {\n\tu8 command_id;\n\tu8 command_length;\n\tu8 command_options;\n\tu8 checksum;\n};\n\n#define E1000_HI_MAX_DATA_LENGTH\t252\nstruct e1000_host_command_info {\n\tstruct e1000_host_command_header command_header;\n\tu8 command_data[E1000_HI_MAX_DATA_LENGTH];\n};\n\n/* Host Interface \"Rev 2\" */\nstruct e1000_host_mng_command_header {\n\tu8 command_id;\n\tu8 checksum;\n\tu16 reserved1;\n\tu16 reserved2;\n\tu16 command_length;\n};\n\n#define E1000_HI_MAX_MNG_DATA_LENGTH\t0x6F8\nstruct e1000_host_mng_command_info {\n\tstruct e1000_host_mng_command_header command_header;\n\tu8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];\n};\n\n#include \"e1000_mac.h\"\n#include \"e1000_phy.h\"\n#include \"e1000_nvm.h\"\n#include \"e1000_manage.h\"\n#include \"e1000_mbx.h\"\n\n/* Function pointers for the MAC. */\nstruct e1000_mac_operations {\n\ts32 (*init_params)(struct e1000_hw *);\n\ts32 (*id_led_init)(struct e1000_hw *);\n\ts32 (*blink_led)(struct e1000_hw *);\n\tbool (*check_mng_mode)(struct e1000_hw *);\n\ts32 (*check_for_link)(struct e1000_hw *);\n\ts32 (*cleanup_led)(struct e1000_hw *);\n\tvoid (*clear_hw_cntrs)(struct e1000_hw *);\n\tvoid (*clear_vfta)(struct e1000_hw *);\n\ts32 (*get_bus_info)(struct e1000_hw *);\n\tvoid (*set_lan_id)(struct e1000_hw *);\n\ts32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);\n\ts32 (*led_on)(struct e1000_hw *);\n\ts32 (*led_off)(struct e1000_hw *);\n\tvoid (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);\n\ts32 (*reset_hw)(struct e1000_hw *);\n\ts32 (*init_hw)(struct e1000_hw *);\n\tvoid (*shutdown_serdes)(struct e1000_hw *);\n\tvoid (*power_up_serdes)(struct e1000_hw *);\n\ts32 (*setup_link)(struct e1000_hw *);\n\ts32 (*setup_physical_interface)(struct e1000_hw *);\n\ts32 (*setup_led)(struct e1000_hw *);\n\tvoid (*write_vfta)(struct e1000_hw *, u32, u32);\n\tvoid (*config_collision_dist)(struct e1000_hw *);\n\tvoid (*rar_set)(struct e1000_hw *, u8*, u32);\n\ts32 (*read_mac_addr)(struct e1000_hw *);\n\ts32 (*validate_mdi_setting)(struct e1000_hw *);\n\ts32 (*acquire_swfw_sync)(struct e1000_hw *, u16);\n\tvoid (*release_swfw_sync)(struct e1000_hw *, u16);\n};\n\n/* When to use various PHY register access functions:\n *\n * Func Caller\n * Function Does Does When to use\n * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n * X_reg L,P,A n/a for simple PHY reg accesses\n * X_reg_locked P,A L for multiple accesses of different regs\n * on different pages\n * X_reg_page A L,P for multiple accesses of different regs\n * on the same page\n *\n * Where X=[read|write], L=locking, P=sets page, A=register access\n *\n */\nstruct e1000_phy_operations {\n\ts32 (*init_params)(struct e1000_hw *);\n\ts32 (*acquire)(struct e1000_hw *);\n\ts32 (*cfg_on_link_up)(struct e1000_hw *);\n\ts32 (*check_polarity)(struct e1000_hw *);\n\ts32 (*check_reset_block)(struct e1000_hw *);\n\ts32 (*commit)(struct e1000_hw *);\n\ts32 (*force_speed_duplex)(struct e1000_hw *);\n\ts32 (*get_cfg_done)(struct e1000_hw *hw);\n\ts32 (*get_cable_length)(struct e1000_hw *);\n\ts32 (*get_info)(struct e1000_hw *);\n\ts32 (*set_page)(struct e1000_hw *, u16);\n\ts32 (*read_reg)(struct e1000_hw *, u32, u16 *);\n\ts32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);\n\ts32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);\n\tvoid (*release)(struct e1000_hw *);\n\ts32 (*reset)(struct e1000_hw *);\n\ts32 (*set_d0_lplu_state)(struct e1000_hw *, bool);\n\ts32 (*set_d3_lplu_state)(struct e1000_hw *, bool);\n\ts32 (*write_reg)(struct e1000_hw *, u32, u16);\n\ts32 (*write_reg_locked)(struct e1000_hw *, u32, u16);\n\ts32 (*write_reg_page)(struct e1000_hw *, u32, u16);\n\tvoid (*power_up)(struct e1000_hw *);\n\tvoid (*power_down)(struct e1000_hw *);\n\ts32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);\n\ts32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);\n};\n\n/* Function pointers for the NVM. */\nstruct e1000_nvm_operations {\n\ts32 (*init_params)(struct e1000_hw *);\n\ts32 (*acquire)(struct e1000_hw *);\n\ts32 (*read)(struct e1000_hw *, u16, u16, u16 *);\n\tvoid (*release)(struct e1000_hw *);\n\tvoid (*reload)(struct e1000_hw *);\n\ts32 (*update)(struct e1000_hw *);\n\ts32 (*valid_led_default)(struct e1000_hw *, u16 *);\n\ts32 (*validate)(struct e1000_hw *);\n\ts32 (*write)(struct e1000_hw *, u16, u16, u16 *);\n};\n\nstruct e1000_mac_info {\n\tstruct e1000_mac_operations ops;\n\tu8 addr[ETH_ADDR_LEN];\n\tu8 perm_addr[ETH_ADDR_LEN];\n\n\tenum e1000_mac_type type;\n\n\tu32 collision_delta;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tu32 mc_filter_type;\n\tu32 tx_packet_delta;\n\tu32 txcw;\n\n\tu16 current_ifs_val;\n\tu16 ifs_max_val;\n\tu16 ifs_min_val;\n\tu16 ifs_ratio;\n\tu16 ifs_step_size;\n\tu16 mta_reg_count;\n\tu16 uta_reg_count;\n\n\t/* Maximum size of the MTA register table in all supported adapters */\n\t#define MAX_MTA_REG 128\n\tu32 mta_shadow[MAX_MTA_REG];\n\tu16 rar_entry_count;\n\n\tu8 forced_speed_duplex;\n\n\tbool adaptive_ifs;\n\tbool has_fwsm;\n\tbool arc_subsystem_valid;\n\tbool asf_firmware_present;\n\tbool autoneg;\n\tbool autoneg_failed;\n\tbool get_link_status;\n\tbool in_ifs_mode;\n\tbool report_tx_early;\n\tenum e1000_serdes_link_state serdes_link_state;\n\tbool serdes_has_link;\n\tbool tx_pkt_filtering;\n};\n\nstruct e1000_phy_info {\n\tstruct e1000_phy_operations ops;\n\tenum e1000_phy_type type;\n\n\tenum e1000_1000t_rx_status local_rx;\n\tenum e1000_1000t_rx_status remote_rx;\n\tenum e1000_ms_type ms_type;\n\tenum e1000_ms_type original_ms_type;\n\tenum e1000_rev_polarity cable_polarity;\n\tenum e1000_smart_speed smart_speed;\n\n\tu32 addr;\n\tu32 id;\n\tu32 reset_delay_us; /* in usec */\n\tu32 revision;\n\n\tenum e1000_media_type media_type;\n\n\tu16 autoneg_advertised;\n\tu16 autoneg_mask;\n\tu16 cable_length;\n\tu16 max_cable_length;\n\tu16 min_cable_length;\n\n\tu8 mdix;\n\n\tbool disable_polarity_correction;\n\tbool is_mdix;\n\tbool polarity_correction;\n\tbool speed_downgraded;\n\tbool autoneg_wait_to_complete;\n};\n\nstruct e1000_nvm_info {\n\tstruct e1000_nvm_operations ops;\n\tenum e1000_nvm_type type;\n\tenum e1000_nvm_override override;\n\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\n\tu16 word_size;\n\tu16 delay_usec;\n\tu16 address_bits;\n\tu16 opcode_bits;\n\tu16 page_size;\n};\n\nstruct e1000_bus_info {\n\tenum e1000_bus_type type;\n\tenum e1000_bus_speed speed;\n\tenum e1000_bus_width width;\n\n\tu16 func;\n\tu16 pci_cmd_word;\n};\n\nstruct e1000_fc_info {\n\tu32 high_water; /* Flow control high-water mark */\n\tu32 low_water; /* Flow control low-water mark */\n\tu16 pause_time; /* Flow control pause timer */\n\tu16 refresh_time; /* Flow control refresh timer */\n\tbool send_xon; /* Flow control send XON */\n\tbool strict_ieee; /* Strict IEEE mode */\n\tenum e1000_fc_mode current_mode; /* FC mode in effect */\n\tenum e1000_fc_mode requested_mode; /* FC mode requested by caller */\n};\n\nstruct e1000_mbx_operations {\n\ts32 (*init_params)(struct e1000_hw *hw);\n\ts32 (*read)(struct e1000_hw *, u32 *, u16, u16);\n\ts32 (*write)(struct e1000_hw *, u32 *, u16, u16);\n\ts32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);\n\ts32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);\n\ts32 (*check_for_msg)(struct e1000_hw *, u16);\n\ts32 (*check_for_ack)(struct e1000_hw *, u16);\n\ts32 (*check_for_rst)(struct e1000_hw *, u16);\n};\n\nstruct e1000_mbx_stats {\n\tu32 msgs_tx;\n\tu32 msgs_rx;\n\n\tu32 acks;\n\tu32 reqs;\n\tu32 rsts;\n};\n\nstruct e1000_mbx_info {\n\tstruct e1000_mbx_operations ops;\n\tstruct e1000_mbx_stats stats;\n\tu32 timeout;\n\tu32 usec_delay;\n\tu16 size;\n};\n\nstruct e1000_dev_spec_82541 {\n\tenum e1000_dsp_config dsp_config;\n\tenum e1000_ffe_config ffe_config;\n\tu16 spd_default;\n\tbool phy_init_script;\n};\n\nstruct e1000_dev_spec_82542 {\n\tbool dma_fairness;\n};\n\nstruct e1000_dev_spec_82543 {\n\tu32 tbi_compatibility;\n\tbool dma_fairness;\n\tbool init_phy_disabled;\n};\n\nstruct e1000_dev_spec_82571 {\n\tbool laa_is_present;\n\tu32 smb_counter;\n\tE1000_MUTEX swflag_mutex;\n};\n\nstruct e1000_dev_spec_80003es2lan {\n\tbool mdic_wa_enable;\n};\n\nstruct e1000_shadow_ram {\n\tu16 value;\n\tbool modified;\n};\n\n#define E1000_SHADOW_RAM_WORDS\t\t2048\n\n#if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)\n/* I218 PHY Ultra Low Power (ULP) states */\nenum e1000_ulp_state {\n\te1000_ulp_state_unknown,\n\te1000_ulp_state_off,\n\te1000_ulp_state_on,\n};\n\n#endif /* NAHUM6LP_HW && ULP_SUPPORT */\nstruct e1000_dev_spec_ich8lan {\n\tbool kmrn_lock_loss_workaround_enabled;\n\tstruct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];\n\tE1000_MUTEX nvm_mutex;\n\tE1000_MUTEX swflag_mutex;\n\tbool nvm_k1_enabled;\n\tbool eee_disable;\n\tu16 eee_lp_ability;\n#if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)\n\tenum e1000_ulp_state ulp_state;\n#endif /* NAHUM6LP_HW && ULP_SUPPORT */\n\tu16 lat_enc;\n\tu16 max_ltr_enc;\n\tbool smbus_disable;\n};\n\nstruct e1000_dev_spec_82575 {\n\tbool sgmii_active;\n\tbool global_device_reset;\n\tbool eee_disable;\n\tbool module_plugged;\n\tbool clear_semaphore_once;\n\tu32 mtu;\n\tstruct sfp_e1000_flags eth_flags;\n\tu8 media_port;\n\tbool media_changed;\n};\n\nstruct e1000_dev_spec_vf {\n\tu32 vf_number;\n\tu32 v2p_mailbox;\n};\n\nstruct e1000_hw {\n\tvoid *back;\n\n\tu8 *hw_addr;\n\tu8 *flash_address;\n\tunsigned long io_base;\n\n\tstruct e1000_mac_info mac;\n\tstruct e1000_fc_info fc;\n\tstruct e1000_phy_info phy;\n\tstruct e1000_nvm_info nvm;\n\tstruct e1000_bus_info bus;\n\tstruct e1000_mbx_info mbx;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\n\tunion {\n\t\tstruct e1000_dev_spec_82541 _82541;\n\t\tstruct e1000_dev_spec_82542 _82542;\n\t\tstruct e1000_dev_spec_82543 _82543;\n\t\tstruct e1000_dev_spec_82571 _82571;\n\t\tstruct e1000_dev_spec_80003es2lan _80003es2lan;\n\t\tstruct e1000_dev_spec_ich8lan ich8lan;\n\t\tstruct e1000_dev_spec_82575 _82575;\n\t\tstruct e1000_dev_spec_vf vf;\n\t} dev_spec;\n\n\tu16 device_id;\n\tu16 subsystem_vendor_id;\n\tu16 subsystem_device_id;\n\tu16 vendor_id;\n\n\tu8 revision_id;\n};\n\n#include \"e1000_82541.h\"\n#include \"e1000_82543.h\"\n#include \"e1000_82571.h\"\n#include \"e1000_80003es2lan.h\"\n#include \"e1000_ich8lan.h\"\n#include \"e1000_82575.h\"\n#include \"e1000_i210.h\"\n\n/* These functions must be implemented by drivers */\nvoid e1000_pci_clear_mwi(struct e1000_hw *hw);\nvoid e1000_pci_set_mwi(struct e1000_hw *hw);\ns32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);\ns32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);\nvoid e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);\nvoid e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);\n\n#endif\n" }, { "path": "drivers/net/e1000/base/e1000_i210.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"e1000_api.h\"\n\n\nSTATIC s32 e1000_acquire_nvm_i210(struct e1000_hw *hw);\nSTATIC void e1000_release_nvm_i210(struct e1000_hw *hw);\nSTATIC s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw);\nSTATIC s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t\tu16 *data);\nSTATIC s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw);\nSTATIC s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data);\n\n/**\n * e1000_acquire_nvm_i210 - Request for access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Acquire the necessary semaphores for exclusive access to the EEPROM.\n * Set the EEPROM access request bit and wait for EEPROM access grant bit.\n * Return successful if access grant bit set, else clear the request for\n * EEPROM access and return -E1000_ERR_NVM (-1).\n **/\nSTATIC s32 e1000_acquire_nvm_i210(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_acquire_nvm_i210\");\n\n\tret_val = e1000_acquire_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_release_nvm_i210 - Release exclusive access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Stop any current commands to the EEPROM and clear the EEPROM request bit,\n * then release the semaphores acquired.\n **/\nSTATIC void e1000_release_nvm_i210(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_release_nvm_i210\");\n\n\te1000_release_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);\n}\n\n/**\n * e1000_acquire_swfw_sync_i210 - Acquire SW/FW semaphore\n * @hw: pointer to the HW structure\n * @mask: specifies which semaphore to acquire\n *\n * Acquire the SW/FW semaphore to access the PHY or NVM. The mask\n * will also specify which port we're acquiring the lock for.\n **/\ns32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask)\n{\n\tu32 swfw_sync;\n\tu32 swmask = mask;\n\tu32 fwmask = mask << 16;\n\ts32 ret_val = E1000_SUCCESS;\n\ts32 i = 0, timeout = 200; /* FIXME: find real value to use here */\n\n\tDEBUGFUNC(\"e1000_acquire_swfw_sync_i210\");\n\n\twhile (i < timeout) {\n\t\tif (e1000_get_hw_semaphore_i210(hw)) {\n\t\t\tret_val = -E1000_ERR_SWFW_SYNC;\n\t\t\tgoto out;\n\t\t}\n\n\t\tswfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);\n\t\tif (!(swfw_sync & (fwmask | swmask)))\n\t\t\tbreak;\n\n\t\t/*\n\t\t * Firmware currently using resource (fwmask)\n\t\t * or other software thread using resource (swmask)\n\t\t */\n\t\te1000_put_hw_semaphore_generic(hw);\n\t\tmsec_delay_irq(5);\n\t\ti++;\n\t}\n\n\tif (i == timeout) {\n\t\tDEBUGOUT(\"Driver can't access resource, SW_FW_SYNC timeout.\\n\");\n\t\tret_val = -E1000_ERR_SWFW_SYNC;\n\t\tgoto out;\n\t}\n\n\tswfw_sync |= swmask;\n\tE1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);\n\n\te1000_put_hw_semaphore_generic(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_release_swfw_sync_i210 - Release SW/FW semaphore\n * @hw: pointer to the HW structure\n * @mask: specifies which semaphore to acquire\n *\n * Release the SW/FW semaphore used to access the PHY or NVM. The mask\n * will also specify which port we're releasing the lock for.\n **/\nvoid e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask)\n{\n\tu32 swfw_sync;\n\n\tDEBUGFUNC(\"e1000_release_swfw_sync_i210\");\n\n\twhile (e1000_get_hw_semaphore_i210(hw) != E1000_SUCCESS)\n\t\t; /* Empty */\n\n\tswfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);\n\tswfw_sync &= ~mask;\n\tE1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);\n\n\te1000_put_hw_semaphore_generic(hw);\n}\n\n/**\n * e1000_get_hw_semaphore_i210 - Acquire hardware semaphore\n * @hw: pointer to the HW structure\n *\n * Acquire the HW semaphore to access the PHY or NVM\n **/\nSTATIC s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw)\n{\n\tu32 swsm;\n\ts32 timeout = hw->nvm.word_size + 1;\n\ts32 i = 0;\n\n\tDEBUGFUNC(\"e1000_get_hw_semaphore_i210\");\n\n\t/* Get the SW semaphore */\n\twhile (i < timeout) {\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tif (!(swsm & E1000_SWSM_SMBI))\n\t\t\tbreak;\n\n\t\tusec_delay(50);\n\t\ti++;\n\t}\n\n\tif (i == timeout) {\n\t\t/* In rare circumstances, the SW semaphore may already be held\n\t\t * unintentionally. Clear the semaphore once before giving up.\n\t\t */\n\t\tif (hw->dev_spec._82575.clear_semaphore_once) {\n\t\t\thw->dev_spec._82575.clear_semaphore_once = false;\n\t\t\te1000_put_hw_semaphore_generic(hw);\n\t\t\tfor (i = 0; i < timeout; i++) {\n\t\t\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\t\t\tif (!(swsm & E1000_SWSM_SMBI))\n\t\t\t\t\tbreak;\n\n\t\t\t\tusec_delay(50);\n\t\t\t}\n\t\t}\n\n\t\t/* If we do not have the semaphore here, we have to give up. */\n\t\tif (i == timeout) {\n\t\t\tDEBUGOUT(\"Driver can't access device - SMBI bit is set.\\n\");\n\t\t\treturn -E1000_ERR_NVM;\n\t\t}\n\t}\n\n\t/* Get the FW semaphore. */\n\tfor (i = 0; i < timeout; i++) {\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tE1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);\n\n\t\t/* Semaphore acquired if bit latched */\n\t\tif (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)\n\t\t\tbreak;\n\n\t\tusec_delay(50);\n\t}\n\n\tif (i == timeout) {\n\t\t/* Release semaphores */\n\t\te1000_put_hw_semaphore_generic(hw);\n\t\tDEBUGOUT(\"Driver can't access the NVM\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register\n * @hw: pointer to the HW structure\n * @offset: offset of word in the Shadow Ram to read\n * @words: number of words to read\n * @data: word read from the Shadow Ram\n *\n * Reads a 16 bit word from the Shadow Ram using the EERD register.\n * Uses necessary synchronization semaphores.\n **/\ns32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t u16 *data)\n{\n\ts32 status = E1000_SUCCESS;\n\tu16 i, count;\n\n\tDEBUGFUNC(\"e1000_read_nvm_srrd_i210\");\n\n\t/* We cannot hold synchronization semaphores for too long,\n\t * because of forceful takeover procedure. However it is more efficient\n\t * to read in bursts than synchronizing access for each word. */\n\tfor (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {\n\t\tcount = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?\n\t\t\tE1000_EERD_EEWR_MAX_COUNT : (words - i);\n\t\tif (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {\n\t\t\tstatus = e1000_read_nvm_eerd(hw, offset, count,\n\t\t\t\t\t\t data + i);\n\t\t\thw->nvm.ops.release(hw);\n\t\t} else {\n\t\t\tstatus = E1000_ERR_SWFW_SYNC;\n\t\t}\n\n\t\tif (status != E1000_SUCCESS)\n\t\t\tbreak;\n\t}\n\n\treturn status;\n}\n\n/**\n * e1000_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR\n * @hw: pointer to the HW structure\n * @offset: offset within the Shadow RAM to be written to\n * @words: number of words to write\n * @data: 16 bit word(s) to be written to the Shadow RAM\n *\n * Writes data to Shadow RAM at offset using EEWR register.\n *\n * If e1000_update_nvm_checksum is not called after this function , the\n * data will not be committed to FLASH and also Shadow RAM will most likely\n * contain an invalid checksum.\n *\n * If error code is returned, data and Shadow RAM may be inconsistent - buffer\n * partially written.\n **/\ns32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t u16 *data)\n{\n\ts32 status = E1000_SUCCESS;\n\tu16 i, count;\n\n\tDEBUGFUNC(\"e1000_write_nvm_srwr_i210\");\n\n\t/* We cannot hold synchronization semaphores for too long,\n\t * because of forceful takeover procedure. However it is more efficient\n\t * to write in bursts than synchronizing access for each word. */\n\tfor (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {\n\t\tcount = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?\n\t\t\tE1000_EERD_EEWR_MAX_COUNT : (words - i);\n\t\tif (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {\n\t\t\tstatus = e1000_write_nvm_srwr(hw, offset, count,\n\t\t\t\t\t\t data + i);\n\t\t\thw->nvm.ops.release(hw);\n\t\t} else {\n\t\t\tstatus = E1000_ERR_SWFW_SYNC;\n\t\t}\n\n\t\tif (status != E1000_SUCCESS)\n\t\t\tbreak;\n\t}\n\n\treturn status;\n}\n\n/**\n * e1000_write_nvm_srwr - Write to Shadow Ram using EEWR\n * @hw: pointer to the HW structure\n * @offset: offset within the Shadow Ram to be written to\n * @words: number of words to write\n * @data: 16 bit word(s) to be written to the Shadow Ram\n *\n * Writes data to Shadow Ram at offset using EEWR register.\n *\n * If e1000_update_nvm_checksum is not called after this function , the\n * Shadow Ram will most likely contain an invalid checksum.\n **/\nSTATIC s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t\tu16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 i, k, eewr = 0;\n\tu32 attempts = 100000;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_write_nvm_srwr\");\n\n\t/*\n\t * A check for invalid values: offset too large, too many words,\n\t * too many words for the offset, and not enough words.\n\t */\n\tif ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\tret_val = -E1000_ERR_NVM;\n\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < words; i++) {\n\t\teewr = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |\n\t\t\t(data[i] << E1000_NVM_RW_REG_DATA) |\n\t\t\tE1000_NVM_RW_REG_START;\n\n\t\tE1000_WRITE_REG(hw, E1000_SRWR, eewr);\n\n\t\tfor (k = 0; k < attempts; k++) {\n\t\t\tif (E1000_NVM_RW_REG_DONE &\n\t\t\t E1000_READ_REG(hw, E1000_SRWR)) {\n\t\t\t\tret_val = E1000_SUCCESS;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tusec_delay(5);\n\t\t}\n\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\tDEBUGOUT(\"Shadow RAM write EEWR timed out\\n\");\n\t\t\tbreak;\n\t\t}\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/** e1000_read_invm_word_i210 - Reads OTP\n * @hw: pointer to the HW structure\n * @address: the word address (aka eeprom offset) to read\n * @data: pointer to the data read\n *\n * Reads 16-bit words from the OTP. Return error when the word is not\n * stored in OTP.\n **/\nSTATIC s32 e1000_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data)\n{\n\ts32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;\n\tu32 invm_dword;\n\tu16 i;\n\tu8 record_type, word_address;\n\n\tDEBUGFUNC(\"e1000_read_invm_word_i210\");\n\n\tfor (i = 0; i < E1000_INVM_SIZE; i++) {\n\t\tinvm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));\n\t\t/* Get record type */\n\t\trecord_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);\n\t\tif (record_type == E1000_INVM_UNINITIALIZED_STRUCTURE)\n\t\t\tbreak;\n\t\tif (record_type == E1000_INVM_CSR_AUTOLOAD_STRUCTURE)\n\t\t\ti += E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;\n\t\tif (record_type == E1000_INVM_RSA_KEY_SHA256_STRUCTURE)\n\t\t\ti += E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;\n\t\tif (record_type == E1000_INVM_WORD_AUTOLOAD_STRUCTURE) {\n\t\t\tword_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);\n\t\t\tif (word_address == address) {\n\t\t\t\t*data = INVM_DWORD_TO_WORD_DATA(invm_dword);\n\t\t\t\tDEBUGOUT2(\"Read INVM Word 0x%02x = %x\",\n\t\t\t\t\t address, *data);\n\t\t\t\tstatus = E1000_SUCCESS;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tif (status != E1000_SUCCESS)\n\t\tDEBUGOUT1(\"Requested word 0x%02x not found in OTP\\n\", address);\n\treturn status;\n}\n\n/** e1000_read_invm_i210 - Read invm wrapper function for I210/I211\n * @hw: pointer to the HW structure\n * @address: the word address (aka eeprom offset) to read\n * @data: pointer to the data read\n *\n * Wrapper function to return data formerly found in the NVM.\n **/\nSTATIC s32 e1000_read_invm_i210(struct e1000_hw *hw, u16 offset,\n\t\t\t\tu16 E1000_UNUSEDARG words, u16 *data)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tUNREFERENCED_1PARAMETER(words);\n\n\tDEBUGFUNC(\"e1000_read_invm_i210\");\n\n\t/* Only the MAC addr is required to be present in the iNVM */\n\tswitch (offset) {\n\tcase NVM_MAC_ADDR:\n\t\tret_val = e1000_read_invm_word_i210(hw, (u8)offset, &data[0]);\n\t\tret_val |= e1000_read_invm_word_i210(hw, (u8)offset+1,\n\t\t\t\t\t\t &data[1]);\n\t\tret_val |= e1000_read_invm_word_i210(hw, (u8)offset+2,\n\t\t\t\t\t\t &data[2]);\n\t\tif (ret_val != E1000_SUCCESS)\n\t\t\tDEBUGOUT(\"MAC Addr not found in iNVM\\n\");\n\t\tbreak;\n\tcase NVM_INIT_CTRL_2:\n\t\tret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\t*data = NVM_INIT_CTRL_2_DEFAULT_I211;\n\t\t\tret_val = E1000_SUCCESS;\n\t\t}\n\t\tbreak;\n\tcase NVM_INIT_CTRL_4:\n\t\tret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\t*data = NVM_INIT_CTRL_4_DEFAULT_I211;\n\t\t\tret_val = E1000_SUCCESS;\n\t\t}\n\t\tbreak;\n\tcase NVM_LED_1_CFG:\n\t\tret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\t*data = NVM_LED_1_CFG_DEFAULT_I211;\n\t\t\tret_val = E1000_SUCCESS;\n\t\t}\n\t\tbreak;\n\tcase NVM_LED_0_2_CFG:\n\t\tret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\t*data = NVM_LED_0_2_CFG_DEFAULT_I211;\n\t\t\tret_val = E1000_SUCCESS;\n\t\t}\n\t\tbreak;\n\tcase NVM_ID_LED_SETTINGS:\n\t\tret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\t*data = ID_LED_RESERVED_FFFF;\n\t\t\tret_val = E1000_SUCCESS;\n\t\t}\n\t\tbreak;\n\tcase NVM_SUB_DEV_ID:\n\t\t*data = hw->subsystem_device_id;\n\t\tbreak;\n\tcase NVM_SUB_VEN_ID:\n\t\t*data = hw->subsystem_vendor_id;\n\t\tbreak;\n\tcase NVM_DEV_ID:\n\t\t*data = hw->device_id;\n\t\tbreak;\n\tcase NVM_VEN_ID:\n\t\t*data = hw->vendor_id;\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT1(\"NVM word 0x%02x is not mapped.\\n\", offset);\n\t\t*data = NVM_RESERVED_WORD;\n\t\tbreak;\n\t}\n\treturn ret_val;\n}\n\n/**\n * e1000_read_invm_version - Reads iNVM version and image type\n * @hw: pointer to the HW structure\n * @invm_ver: version structure for the version read\n *\n * Reads iNVM version and image type.\n **/\ns32 e1000_read_invm_version(struct e1000_hw *hw,\n\t\t\t struct e1000_fw_version *invm_ver)\n{\n\tu32 *record = NULL;\n\tu32 *next_record = NULL;\n\tu32 i = 0;\n\tu32 invm_dword = 0;\n\tu32 invm_blocks = E1000_INVM_SIZE - (E1000_INVM_ULT_BYTES_SIZE /\n\t\t\t\t\t E1000_INVM_RECORD_SIZE_IN_BYTES);\n\tu32 buffer[E1000_INVM_SIZE];\n\ts32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;\n\tu16 version = 0;\n\n\tDEBUGFUNC(\"e1000_read_invm_version\");\n\n\t/* Read iNVM memory */\n\tfor (i = 0; i < E1000_INVM_SIZE; i++) {\n\t\tinvm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));\n\t\tbuffer[i] = invm_dword;\n\t}\n\n\t/* Read version number */\n\tfor (i = 1; i < invm_blocks; i++) {\n\t\trecord = &buffer[invm_blocks - i];\n\t\tnext_record = &buffer[invm_blocks - i + 1];\n\n\t\t/* Check if we have first version location used */\n\t\tif ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) {\n\t\t\tversion = 0;\n\t\t\tstatus = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\t/* Check if we have second version location used */\n\t\telse if ((i == 1) &&\n\t\t\t ((*record & E1000_INVM_VER_FIELD_TWO) == 0)) {\n\t\t\tversion = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;\n\t\t\tstatus = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\t/*\n\t\t * Check if we have odd version location\n\t\t * used and it is the last one used\n\t\t */\n\t\telse if ((((*record & E1000_INVM_VER_FIELD_ONE) == 0) &&\n\t\t\t ((*record & 0x3) == 0)) || (((*record & 0x3) != 0) &&\n\t\t\t (i != 1))) {\n\t\t\tversion = (*next_record & E1000_INVM_VER_FIELD_TWO)\n\t\t\t\t >> 13;\n\t\t\tstatus = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\t/*\n\t\t * Check if we have even version location\n\t\t * used and it is the last one used\n\t\t */\n\t\telse if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) &&\n\t\t\t ((*record & 0x3) == 0)) {\n\t\t\tversion = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;\n\t\t\tstatus = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (status == E1000_SUCCESS) {\n\t\tinvm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK)\n\t\t\t\t\t>> E1000_INVM_MAJOR_SHIFT;\n\t\tinvm_ver->invm_minor = version & E1000_INVM_MINOR_MASK;\n\t}\n\t/* Read Image Type */\n\tfor (i = 1; i < invm_blocks; i++) {\n\t\trecord = &buffer[invm_blocks - i];\n\t\tnext_record = &buffer[invm_blocks - i + 1];\n\n\t\t/* Check if we have image type in first location used */\n\t\tif ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) {\n\t\t\tinvm_ver->invm_img_type = 0;\n\t\t\tstatus = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\t/* Check if we have image type in first location used */\n\t\telse if ((((*record & 0x3) == 0) &&\n\t\t\t ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) ||\n\t\t\t ((((*record & 0x3) != 0) && (i != 1)))) {\n\t\t\tinvm_ver->invm_img_type =\n\t\t\t\t(*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23;\n\t\t\tstatus = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn status;\n}\n\n/**\n * e1000_validate_nvm_checksum_i210 - Validate EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Calculates the EEPROM checksum by reading/adding each word of the EEPROM\n * and then verifies that the sum of the EEPROM is equal to 0xBABA.\n **/\ns32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw)\n{\n\ts32 status = E1000_SUCCESS;\n\ts32 (*read_op_ptr)(struct e1000_hw *, u16, u16, u16 *);\n\n\tDEBUGFUNC(\"e1000_validate_nvm_checksum_i210\");\n\n\tif (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {\n\n\t\t/*\n\t\t * Replace the read function with semaphore grabbing with\n\t\t * the one that skips this for a while.\n\t\t * We have semaphore taken already here.\n\t\t */\n\t\tread_op_ptr = hw->nvm.ops.read;\n\t\thw->nvm.ops.read = e1000_read_nvm_eerd;\n\n\t\tstatus = e1000_validate_nvm_checksum_generic(hw);\n\n\t\t/* Revert original read operation. */\n\t\thw->nvm.ops.read = read_op_ptr;\n\n\t\thw->nvm.ops.release(hw);\n\t} else {\n\t\tstatus = E1000_ERR_SWFW_SYNC;\n\t}\n\n\treturn status;\n}\n\n\n/**\n * e1000_update_nvm_checksum_i210 - Update EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Updates the EEPROM checksum by reading/adding each word of the EEPROM\n * up to the checksum. Then calculates the EEPROM checksum and writes the\n * value to the EEPROM. Next commit EEPROM data onto the Flash.\n **/\ns32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 checksum = 0;\n\tu16 i, nvm_data;\n\n\tDEBUGFUNC(\"e1000_update_nvm_checksum_i210\");\n\n\t/*\n\t * Read the first word from the EEPROM. If this times out or fails, do\n\t * not continue or we could be in for a very long wait while every\n\t * EEPROM read fails\n\t */\n\tret_val = e1000_read_nvm_eerd(hw, 0, 1, &nvm_data);\n\tif (ret_val != E1000_SUCCESS) {\n\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\tgoto out;\n\t}\n\n\tif (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {\n\t\t/*\n\t\t * Do not use hw->nvm.ops.write, hw->nvm.ops.read\n\t\t * because we do not want to take the synchronization\n\t\t * semaphores twice here.\n\t\t */\n\n\t\tfor (i = 0; i < NVM_CHECKSUM_REG; i++) {\n\t\t\tret_val = e1000_read_nvm_eerd(hw, i, 1, &nvm_data);\n\t\t\tif (ret_val) {\n\t\t\t\thw->nvm.ops.release(hw);\n\t\t\t\tDEBUGOUT(\"NVM Read Error while updating checksum.\\n\");\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t\tchecksum += nvm_data;\n\t\t}\n\t\tchecksum = (u16) NVM_SUM - checksum;\n\t\tret_val = e1000_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,\n\t\t\t\t\t\t&checksum);\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\thw->nvm.ops.release(hw);\n\t\t\tDEBUGOUT(\"NVM Write Error while updating checksum.\\n\");\n\t\t\tgoto out;\n\t\t}\n\n\t\thw->nvm.ops.release(hw);\n\n\t\tret_val = e1000_update_flash_i210(hw);\n\t} else {\n\t\tret_val = E1000_ERR_SWFW_SYNC;\n\t}\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_get_flash_presence_i210 - Check if flash device is detected.\n * @hw: pointer to the HW structure\n *\n **/\nbool e1000_get_flash_presence_i210(struct e1000_hw *hw)\n{\n\tu32 eec = 0;\n\tbool ret_val = false;\n\n\tDEBUGFUNC(\"e1000_get_flash_presence_i210\");\n\n\teec = E1000_READ_REG(hw, E1000_EECD);\n\n\tif (eec & E1000_EECD_FLASH_DETECTED_I210)\n\t\tret_val = true;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_update_flash_i210 - Commit EEPROM to the flash\n * @hw: pointer to the HW structure\n *\n **/\ns32 e1000_update_flash_i210(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu32 flup;\n\n\tDEBUGFUNC(\"e1000_update_flash_i210\");\n\n\tret_val = e1000_pool_flash_update_done_i210(hw);\n\tif (ret_val == -E1000_ERR_NVM) {\n\t\tDEBUGOUT(\"Flash update time out\\n\");\n\t\tgoto out;\n\t}\n\n\tflup = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD_I210;\n\tE1000_WRITE_REG(hw, E1000_EECD, flup);\n\n\tret_val = e1000_pool_flash_update_done_i210(hw);\n\tif (ret_val == E1000_SUCCESS)\n\t\tDEBUGOUT(\"Flash update complete\\n\");\n\telse\n\t\tDEBUGOUT(\"Flash update time out\\n\");\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.\n * @hw: pointer to the HW structure\n *\n **/\ns32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw)\n{\n\ts32 ret_val = -E1000_ERR_NVM;\n\tu32 i, reg;\n\n\tDEBUGFUNC(\"e1000_pool_flash_update_done_i210\");\n\n\tfor (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {\n\t\treg = E1000_READ_REG(hw, E1000_EECD);\n\t\tif (reg & E1000_EECD_FLUDONE_I210) {\n\t\t\tret_val = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\tusec_delay(5);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_nvm_params_i210 - Initialize i210 NVM function pointers\n * @hw: pointer to the HW structure\n *\n * Initialize the i210/i211 NVM parameters and function pointers.\n **/\nSTATIC s32 e1000_init_nvm_params_i210(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\n\tDEBUGFUNC(\"e1000_init_nvm_params_i210\");\n\n\tret_val = e1000_init_nvm_params_82575(hw);\n\tnvm->ops.acquire = e1000_acquire_nvm_i210;\n\tnvm->ops.release = e1000_release_nvm_i210;\n\tnvm->ops.valid_led_default = e1000_valid_led_default_i210;\n\tif (e1000_get_flash_presence_i210(hw)) {\n\t\thw->nvm.type = e1000_nvm_flash_hw;\n\t\tnvm->ops.read = e1000_read_nvm_srrd_i210;\n\t\tnvm->ops.write = e1000_write_nvm_srwr_i210;\n\t\tnvm->ops.validate = e1000_validate_nvm_checksum_i210;\n\t\tnvm->ops.update = e1000_update_nvm_checksum_i210;\n\t} else {\n\t\thw->nvm.type = e1000_nvm_invm;\n\t\tnvm->ops.read = e1000_read_invm_i210;\n\t\tnvm->ops.write = e1000_null_write_nvm;\n\t\tnvm->ops.validate = e1000_null_ops_generic;\n\t\tnvm->ops.update = e1000_null_ops_generic;\n\t}\n\treturn ret_val;\n}\n\n/**\n * e1000_init_function_pointers_i210 - Init func ptrs.\n * @hw: pointer to the HW structure\n *\n * Called to initialize all function pointers and parameters.\n **/\nvoid e1000_init_function_pointers_i210(struct e1000_hw *hw)\n{\n\te1000_init_function_pointers_82575(hw);\n\thw->nvm.ops.init_params = e1000_init_nvm_params_i210;\n\n\treturn;\n}\n\n/**\n * e1000_valid_led_default_i210 - Verify a valid default LED config\n * @hw: pointer to the HW structure\n * @data: pointer to the NVM (EEPROM)\n *\n * Read the EEPROM for the current default LED configuration. If the\n * LED configuration is not valid, set to a valid LED configuration.\n **/\nSTATIC s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_valid_led_default_i210\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\tgoto out;\n\t}\n\n\tif (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {\n\t\tswitch (hw->phy.media_type) {\n\t\tcase e1000_media_type_internal_serdes:\n\t\t\t*data = ID_LED_DEFAULT_I210_SERDES;\n\t\t\tbreak;\n\t\tcase e1000_media_type_copper:\n\t\tdefault:\n\t\t\t*data = ID_LED_DEFAULT_I210;\n\t\t\tbreak;\n\t\t}\n\t}\nout:\n\treturn ret_val;\n}\n\n/**\n * __e1000_access_xmdio_reg - Read/write XMDIO register\n * @hw: pointer to the HW structure\n * @address: XMDIO address to program\n * @dev_addr: device address to program\n * @data: pointer to value to read/write from/to the XMDIO address\n * @read: boolean flag to indicate read or write\n **/\nSTATIC s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,\n\t\t\t\t u8 dev_addr, u16 *data, bool read)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"__e1000_access_xmdio_reg\");\n\n\tret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |\n\t\t\t\t\t\t\t dev_addr);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (read)\n\t\tret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);\n\telse\n\t\tret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Recalibrate the device back to 0 */\n\tret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_xmdio_reg - Read XMDIO register\n * @hw: pointer to the HW structure\n * @addr: XMDIO address to program\n * @dev_addr: device address to program\n * @data: value to be read from the EMI address\n **/\ns32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)\n{\n\tDEBUGFUNC(\"e1000_read_xmdio_reg\");\n\n\treturn __e1000_access_xmdio_reg(hw, addr, dev_addr, data, true);\n}\n\n/**\n * e1000_write_xmdio_reg - Write XMDIO register\n * @hw: pointer to the HW structure\n * @addr: XMDIO address to program\n * @dev_addr: device address to program\n * @data: value to be written to the XMDIO address\n **/\ns32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)\n{\n\tDEBUGFUNC(\"e1000_read_xmdio_reg\");\n\n\treturn __e1000_access_xmdio_reg(hw, addr, dev_addr, &data, false);\n}\n\n/**\n * e1000_pll_workaround_i210\n * @hw: pointer to the HW structure\n *\n * Works around an errata in the PLL circuit where it occasionally\n * provides the wrong clock frequency after power up.\n **/\nSTATIC s32 e1000_pll_workaround_i210(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu32 wuc, mdicnfg, ctrl_ext, reg_val;\n\tu16 nvm_word, phy_word, pci_word, tmp_nvm;\n\tint i;\n\n\t/* Get and set needed register values */\n\twuc = E1000_READ_REG(hw, E1000_WUC);\n\tmdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);\n\treg_val = mdicnfg & ~E1000_MDICNFG_EXT_MDIO;\n\tE1000_WRITE_REG(hw, E1000_MDICNFG, reg_val);\n\n\t/* Get data from NVM, or set default */\n\tret_val = e1000_read_invm_word_i210(hw, E1000_INVM_AUTOLOAD,\n\t\t\t\t\t &nvm_word);\n\tif (ret_val != E1000_SUCCESS)\n\t\tnvm_word = E1000_INVM_DEFAULT_AL;\n\ttmp_nvm = nvm_word | E1000_INVM_PLL_WO_VAL;\n\tfor (i = 0; i < E1000_MAX_PLL_TRIES; i++) {\n\t\t/* check current state */\n\t\thw->phy.ops.read_reg(hw, (E1000_PHY_PLL_FREQ_PAGE |\n\t\t\t\t E1000_PHY_PLL_FREQ_REG), &phy_word);\n\t\tif ((phy_word & E1000_PHY_PLL_UNCONF)\n\t\t != E1000_PHY_PLL_UNCONF) {\n\t\t\tret_val = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t} else {\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\t}\n\t\thw->phy.ops.reset(hw);\n\t\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\tctrl_ext |= (E1000_CTRL_EXT_PHYPDEN | E1000_CTRL_EXT_SDLPE);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\n\t\tE1000_WRITE_REG(hw, E1000_WUC, 0);\n\t\treg_val = (E1000_INVM_AUTOLOAD << 4) | (tmp_nvm << 16);\n\t\tE1000_WRITE_REG(hw, E1000_EEARBC, reg_val);\n\n\t\te1000_read_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);\n\t\tpci_word |= E1000_PCI_PMCSR_D3;\n\t\te1000_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);\n\t\tmsec_delay(1);\n\t\tpci_word &= ~E1000_PCI_PMCSR_D3;\n\t\te1000_write_pci_cfg(hw, E1000_PCI_PMCSR, &pci_word);\n\t\treg_val = (E1000_INVM_AUTOLOAD << 4) | (nvm_word << 16);\n\t\tE1000_WRITE_REG(hw, E1000_EEARBC, reg_val);\n\n\t\t/* restore WUC register */\n\t\tE1000_WRITE_REG(hw, E1000_WUC, wuc);\n\t}\n\t/* restore MDICNFG setting */\n\tE1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);\n\treturn ret_val;\n}\n\n/**\n * e1000_init_hw_i210 - Init hw for I210/I211\n * @hw: pointer to the HW structure\n *\n * Called to initialize hw for i210 hw family.\n **/\ns32 e1000_init_hw_i210(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_init_hw_i210\");\n\tif ((hw->mac.type >= e1000_i210) &&\n\t !(e1000_get_flash_presence_i210(hw))) {\n\t\tret_val = e1000_pll_workaround_i210(hw);\n\t\tif (ret_val != E1000_SUCCESS)\n\t\t\treturn ret_val;\n\t}\n\tret_val = e1000_init_hw_82575(hw);\n\treturn ret_val;\n}\n" }, { "path": "drivers/net/e1000/base/e1000_i210.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_I210_H_\n#define _E1000_I210_H_\n\nbool e1000_get_flash_presence_i210(struct e1000_hw *hw);\ns32 e1000_update_flash_i210(struct e1000_hw *hw);\ns32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw);\ns32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw);\ns32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset,\n\t\t\t u16 words, u16 *data);\ns32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset,\n\t\t\t u16 words, u16 *data);\ns32 e1000_read_invm_version(struct e1000_hw *hw,\n\t\t\t struct e1000_fw_version *invm_ver);\ns32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);\nvoid e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);\ns32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,\n\t\t\t u16 *data);\ns32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,\n\t\t\t u16 data);\ns32 e1000_init_hw_i210(struct e1000_hw *hw);\n\n#define E1000_STM_OPCODE\t\t0xDB00\n#define E1000_EEPROM_FLASH_SIZE_WORD\t0x11\n\n#define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \\\n\t(u8)((invm_dword) & 0x7)\n#define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \\\n\t(u8)(((invm_dword) & 0x0000FE00) >> 9)\n#define INVM_DWORD_TO_WORD_DATA(invm_dword) \\\n\t(u16)(((invm_dword) & 0xFFFF0000) >> 16)\n\nenum E1000_INVM_STRUCTURE_TYPE {\n\tE1000_INVM_UNINITIALIZED_STRUCTURE\t\t= 0x00,\n\tE1000_INVM_WORD_AUTOLOAD_STRUCTURE\t\t= 0x01,\n\tE1000_INVM_CSR_AUTOLOAD_STRUCTURE\t\t= 0x02,\n\tE1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE\t= 0x03,\n\tE1000_INVM_RSA_KEY_SHA256_STRUCTURE\t\t= 0x04,\n\tE1000_INVM_INVALIDATED_STRUCTURE\t\t= 0x0F,\n};\n\n#define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS\t8\n#define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS\t1\n#define E1000_INVM_ULT_BYTES_SIZE\t8\n#define E1000_INVM_RECORD_SIZE_IN_BYTES\t4\n#define E1000_INVM_VER_FIELD_ONE\t0x1FF8\n#define E1000_INVM_VER_FIELD_TWO\t0x7FE000\n#define E1000_INVM_IMGTYPE_FIELD\t0x1F800000\n\n#define E1000_INVM_MAJOR_MASK\t0x3F0\n#define E1000_INVM_MINOR_MASK\t0xF\n#define E1000_INVM_MAJOR_SHIFT\t4\n\n#define ID_LED_DEFAULT_I210\t\t((ID_LED_OFF1_ON2 << 8) | \\\n\t\t\t\t\t (ID_LED_DEF1_DEF2 << 4) | \\\n\t\t\t\t\t (ID_LED_OFF1_OFF2))\n#define ID_LED_DEFAULT_I210_SERDES\t((ID_LED_DEF1_DEF2 << 8) | \\\n\t\t\t\t\t (ID_LED_DEF1_DEF2 << 4) | \\\n\t\t\t\t\t (ID_LED_OFF1_ON2))\n\n/* NVM offset defaults for I211 devices */\n#define NVM_INIT_CTRL_2_DEFAULT_I211\t0X7243\n#define NVM_INIT_CTRL_4_DEFAULT_I211\t0x00C1\n#define NVM_LED_1_CFG_DEFAULT_I211\t0x0184\n#define NVM_LED_0_2_CFG_DEFAULT_I211\t0x200C\n\n/* PLL Defines */\n#define E1000_PCI_PMCSR\t\t\t0x44\n#define E1000_PCI_PMCSR_D3\t\t0x03\n#define E1000_MAX_PLL_TRIES\t\t5\n#define E1000_PHY_PLL_UNCONF\t\t0xFF\n#define E1000_PHY_PLL_FREQ_PAGE\t\t0xFC0000\n#define E1000_PHY_PLL_FREQ_REG\t\t0x000E\n#define E1000_INVM_DEFAULT_AL\t\t0x202F\n#define E1000_INVM_AUTOLOAD\t\t0x0A\n#define E1000_INVM_PLL_WO_VAL\t\t0x0010\n\n#endif\n" }, { "path": "drivers/net/e1000/base/e1000_ich8lan.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n/* 82562G 10/100 Network Connection\n * 82562G-2 10/100 Network Connection\n * 82562GT 10/100 Network Connection\n * 82562GT-2 10/100 Network Connection\n * 82562V 10/100 Network Connection\n * 82562V-2 10/100 Network Connection\n * 82566DC-2 Gigabit Network Connection\n * 82566DC Gigabit Network Connection\n * 82566DM-2 Gigabit Network Connection\n * 82566DM Gigabit Network Connection\n * 82566MC Gigabit Network Connection\n * 82566MM Gigabit Network Connection\n * 82567LM Gigabit Network Connection\n * 82567LF Gigabit Network Connection\n * 82567V Gigabit Network Connection\n * 82567LM-2 Gigabit Network Connection\n * 82567LF-2 Gigabit Network Connection\n * 82567V-2 Gigabit Network Connection\n * 82567LF-3 Gigabit Network Connection\n * 82567LM-3 Gigabit Network Connection\n * 82567LM-4 Gigabit Network Connection\n * 82577LM Gigabit Network Connection\n * 82577LC Gigabit Network Connection\n * 82578DM Gigabit Network Connection\n * 82578DC Gigabit Network Connection\n * 82579LM Gigabit Network Connection\n * 82579V Gigabit Network Connection\n * Ethernet Connection I217-LM\n * Ethernet Connection I217-V\n * Ethernet Connection I218-V\n * Ethernet Connection I218-LM\n */\n\n#include \"e1000_api.h\"\n\nSTATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);\nSTATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);\nSTATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);\nSTATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw);\nSTATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);\nSTATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);\nSTATIC void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);\nSTATIC void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);\nSTATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);\n#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT\nSTATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,\n\t\t\t\t\t u8 *mc_addr_list,\n\t\t\t\t\t u32 mc_addr_count);\n#endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */\nSTATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);\nSTATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,\n\t\t\t\t\t bool active);\nSTATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,\n\t\t\t\t\t bool active);\nSTATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data);\nSTATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data);\nSTATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,\n\t\t\t\t\t u16 *data);\nSTATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);\nSTATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);\nSTATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,\n\t\t\t\t\t u16 *speed, u16 *duplex);\nSTATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);\nSTATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw);\nSTATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);\nSTATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw);\nSTATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw);\nSTATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);\nSTATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,\n\t\t\t\t\t u32 offset, u8 *data);\nSTATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u8 size, u16 *data);\nSTATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,\n\t\t\t\t\t u32 offset, u16 *data);\nSTATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,\n\t\t\t\t\t\t u32 offset, u8 byte);\nSTATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);\nSTATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);\nSTATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);\nSTATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);\nSTATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);\n\n/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */\n/* Offset 04h HSFSTS */\nunion ich8_hws_flash_status {\n\tstruct ich8_hsfsts {\n\t\tu16 flcdone:1; /* bit 0 Flash Cycle Done */\n\t\tu16 flcerr:1; /* bit 1 Flash Cycle Error */\n\t\tu16 dael:1; /* bit 2 Direct Access error Log */\n\t\tu16 berasesz:2; /* bit 4:3 Sector Erase Size */\n\t\tu16 flcinprog:1; /* bit 5 flash cycle in Progress */\n\t\tu16 reserved1:2; /* bit 13:6 Reserved */\n\t\tu16 reserved2:6; /* bit 13:6 Reserved */\n\t\tu16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */\n\t\tu16 flockdn:1; /* bit 15 Flash Config Lock-Down */\n\t} hsf_status;\n\tu16 regval;\n};\n\n/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */\n/* Offset 06h FLCTL */\nunion ich8_hws_flash_ctrl {\n\tstruct ich8_hsflctl {\n\t\tu16 flcgo:1; /* 0 Flash Cycle Go */\n\t\tu16 flcycle:2; /* 2:1 Flash Cycle */\n\t\tu16 reserved:5; /* 7:3 Reserved */\n\t\tu16 fldbcount:2; /* 9:8 Flash Data Byte Count */\n\t\tu16 flockdn:6; /* 15:10 Reserved */\n\t} hsf_ctrl;\n\tu16 regval;\n};\n\n/* ICH Flash Region Access Permissions */\nunion ich8_hws_flash_regacc {\n\tstruct ich8_flracc {\n\t\tu32 grra:8; /* 0:7 GbE region Read Access */\n\t\tu32 grwa:8; /* 8:15 GbE region Write Access */\n\t\tu32 gmrag:8; /* 23:16 GbE Master Read Access Grant */\n\t\tu32 gmwag:8; /* 31:24 GbE Master Write Access Grant */\n\t} hsf_flregacc;\n\tu16 regval;\n};\n\n/**\n * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers\n * @hw: pointer to the HW structure\n *\n * Test access to the PHY registers by reading the PHY ID registers. If\n * the PHY ID is already known (e.g. resume path) compare it with known ID,\n * otherwise assume the read PHY ID is correct if it is valid.\n *\n * Assumes the sw/fw/hw semaphore is already acquired.\n **/\nSTATIC bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)\n{\n\tu16 phy_reg = 0;\n\tu32 phy_id = 0;\n\ts32 ret_val = 0;\n\tu16 retry_count;\n\tu32 mac_reg = 0;\n\n\tfor (retry_count = 0; retry_count < 2; retry_count++) {\n\t\tret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg);\n\t\tif (ret_val || (phy_reg == 0xFFFF))\n\t\t\tcontinue;\n\t\tphy_id = (u32)(phy_reg << 16);\n\n\t\tret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg);\n\t\tif (ret_val || (phy_reg == 0xFFFF)) {\n\t\t\tphy_id = 0;\n\t\t\tcontinue;\n\t\t}\n\t\tphy_id |= (u32)(phy_reg & PHY_REVISION_MASK);\n\t\tbreak;\n\t}\n\n\tif (hw->phy.id) {\n\t\tif (hw->phy.id == phy_id)\n\t\t\tgoto out;\n\t} else if (phy_id) {\n\t\thw->phy.id = phy_id;\n\t\thw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);\n\t\tgoto out;\n\t}\n\n\t/* In case the PHY needs to be in mdio slow mode,\n\t * set slow mode and try to get the PHY id again.\n\t */\n\tif (hw->mac.type < e1000_pch_lpt) {\n\t\thw->phy.ops.release(hw);\n\t\tret_val = e1000_set_mdio_slow_mode_hv(hw);\n\t\tif (!ret_val)\n\t\t\tret_val = e1000_get_phy_id(hw);\n\t\thw->phy.ops.acquire(hw);\n\t}\n\n\tif (ret_val)\n\t\treturn false;\nout:\n\tif (hw->mac.type == e1000_pch_lpt) {\n\t\t/* Unforce SMBus mode in PHY */\n\t\thw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg);\n\t\tphy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;\n\t\thw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg);\n\n\t\t/* Unforce SMBus mode in MAC */\n\t\tmac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\tmac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);\n\t}\n\n\treturn true;\n}\n\n/**\n * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value\n * @hw: pointer to the HW structure\n *\n * Toggling the LANPHYPC pin value fully power-cycles the PHY and is\n * used to reset the PHY to a quiescent state when necessary.\n **/\nSTATIC void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)\n{\n\tu32 mac_reg;\n\n\tDEBUGFUNC(\"e1000_toggle_lanphypc_pch_lpt\");\n\n\t/* Set Phy Config Counter to 50msec */\n\tmac_reg = E1000_READ_REG(hw, E1000_FEXTNVM3);\n\tmac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;\n\tmac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;\n\tE1000_WRITE_REG(hw, E1000_FEXTNVM3, mac_reg);\n\n\t/* Toggle LANPHYPC Value bit */\n\tmac_reg = E1000_READ_REG(hw, E1000_CTRL);\n\tmac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;\n\tmac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;\n\tE1000_WRITE_REG(hw, E1000_CTRL, mac_reg);\n\tE1000_WRITE_FLUSH(hw);\n\tusec_delay(10);\n\tmac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;\n\tE1000_WRITE_REG(hw, E1000_CTRL, mac_reg);\n\tE1000_WRITE_FLUSH(hw);\n\n\tif (hw->mac.type < e1000_pch_lpt) {\n\t\tmsec_delay(50);\n\t} else {\n\t\tu16 count = 20;\n\n\t\tdo {\n\t\t\tmsec_delay(5);\n\t\t} while (!(E1000_READ_REG(hw, E1000_CTRL_EXT) &\n\t\t\t E1000_CTRL_EXT_LPCD) && count--);\n\n\t\tmsec_delay(30);\n\t}\n}\n\n/**\n * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds\n * @hw: pointer to the HW structure\n *\n * Workarounds/flow necessary for PHY initialization during driver load\n * and resume paths.\n **/\nSTATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)\n{\n\tu32 mac_reg, fwsm = E1000_READ_REG(hw, E1000_FWSM);\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_init_phy_workarounds_pchlan\");\n\n\t/* Gate automatic PHY configuration by hardware on managed and\n\t * non-managed 82579 and newer adapters.\n\t */\n\te1000_gate_hw_phy_config_ich8lan(hw, true);\n\n#if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)\n\t/* It is not possible to be certain of the current state of ULP\n\t * so forcibly disable it.\n\t */\n\thw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;\n\n#endif /* NAHUM6LP_HW && ULP_SUPPORT */\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Failed to initialize PHY flow\\n\");\n\t\tgoto out;\n\t}\n\n\t/* The MAC-PHY interconnect may be in SMBus mode. If the PHY is\n\t * inaccessible and resetting the PHY is not blocked, toggle the\n\t * LANPHYPC Value bit to force the interconnect to PCIe mode.\n\t */\n\tswitch (hw->mac.type) {\n\tcase e1000_pch_lpt:\n\t\tif (e1000_phy_is_accessible_pchlan(hw))\n\t\t\tbreak;\n\n\t\t/* Before toggling LANPHYPC, see if PHY is accessible by\n\t\t * forcing MAC to SMBus mode first.\n\t\t */\n\t\tmac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\tmac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);\n\n\t\t/* Wait 50 milliseconds for MAC to finish any retries\n\t\t * that it might be trying to perform from previous\n\t\t * attempts to acknowledge any phy read requests.\n\t\t */\n\t\t msec_delay(50);\n\n\t\t/* fall-through */\n\tcase e1000_pch2lan:\n\t\tif (e1000_phy_is_accessible_pchlan(hw))\n\t\t\tbreak;\n\n\t\t/* fall-through */\n\tcase e1000_pchlan:\n\t\tif ((hw->mac.type == e1000_pchlan) &&\n\t\t (fwsm & E1000_ICH_FWSM_FW_VALID))\n\t\t\tbreak;\n\n\t\tif (hw->phy.ops.check_reset_block(hw)) {\n\t\t\tDEBUGOUT(\"Required LANPHYPC toggle blocked by ME\\n\");\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Toggle LANPHYPC Value bit */\n\t\te1000_toggle_lanphypc_pch_lpt(hw);\n\t\tif (hw->mac.type >= e1000_pch_lpt) {\n\t\t\tif (e1000_phy_is_accessible_pchlan(hw))\n\t\t\t\tbreak;\n\n\t\t\t/* Toggling LANPHYPC brings the PHY out of SMBus mode\n\t\t\t * so ensure that the MAC is also out of SMBus mode\n\t\t\t */\n\t\t\tmac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\t\tmac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;\n\t\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);\n\n\t\t\tif (e1000_phy_is_accessible_pchlan(hw))\n\t\t\t\tbreak;\n\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\thw->phy.ops.release(hw);\n\tif (!ret_val) {\n\n\t\t/* Check to see if able to reset PHY. Print error if not */\n\t\tif (hw->phy.ops.check_reset_block(hw)) {\n\t\t\tERROR_REPORT(\"Reset blocked by ME\\n\");\n\t\t\tgoto out;\n\t\t}\n\n\t\t/* Reset the PHY before any access to it. Doing so, ensures\n\t\t * that the PHY is in a known good state before we read/write\n\t\t * PHY registers. The generic reset is sufficient here,\n\t\t * because we haven't determined the PHY type yet.\n\t\t */\n\t\tret_val = e1000_phy_hw_reset_generic(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\t/* On a successful reset, possibly need to wait for the PHY\n\t\t * to quiesce to an accessible state before returning control\n\t\t * to the calling function. If the PHY does not quiesce, then\n\t\t * return E1000E_BLK_PHY_RESET, as this is the condition that\n\t\t * the PHY is in.\n\t\t */\n\t\tret_val = hw->phy.ops.check_reset_block(hw);\n\t\tif (ret_val)\n\t\t\tERROR_REPORT(\"ME blocked access to PHY after reset\\n\");\n\t}\n\nout:\n\t/* Ungate automatic PHY configuration on non-managed 82579 */\n\tif ((hw->mac.type == e1000_pch2lan) &&\n\t !(fwsm & E1000_ICH_FWSM_FW_VALID)) {\n\t\tmsec_delay(10);\n\t\te1000_gate_hw_phy_config_ich8lan(hw, false);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_phy_params_pchlan - Initialize PHY function pointers\n * @hw: pointer to the HW structure\n *\n * Initialize family-specific PHY parameters and function pointers.\n **/\nSTATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_init_phy_params_pchlan\");\n\n\tphy->addr\t\t= 1;\n\tphy->reset_delay_us\t= 100;\n\n\tphy->ops.acquire\t= e1000_acquire_swflag_ich8lan;\n\tphy->ops.check_reset_block = e1000_check_reset_block_ich8lan;\n\tphy->ops.get_cfg_done\t= e1000_get_cfg_done_ich8lan;\n\tphy->ops.set_page\t= e1000_set_page_igp;\n\tphy->ops.read_reg\t= e1000_read_phy_reg_hv;\n\tphy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;\n\tphy->ops.read_reg_page\t= e1000_read_phy_reg_page_hv;\n\tphy->ops.release\t= e1000_release_swflag_ich8lan;\n\tphy->ops.reset\t\t= e1000_phy_hw_reset_ich8lan;\n\tphy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;\n\tphy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;\n\tphy->ops.write_reg\t= e1000_write_phy_reg_hv;\n\tphy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;\n\tphy->ops.write_reg_page\t= e1000_write_phy_reg_page_hv;\n\tphy->ops.power_up\t= e1000_power_up_phy_copper;\n\tphy->ops.power_down\t= e1000_power_down_phy_copper_ich8lan;\n\tphy->autoneg_mask\t= AUTONEG_ADVERTISE_SPEED_DEFAULT;\n\n\tphy->id = e1000_phy_unknown;\n\n\tret_val = e1000_init_phy_workarounds_pchlan(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (phy->id == e1000_phy_unknown)\n\t\tswitch (hw->mac.type) {\n\t\tdefault:\n\t\t\tret_val = e1000_get_phy_id(hw);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t\tif ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))\n\t\t\t\tbreak;\n\t\t\t/* fall-through */\n\t\tcase e1000_pch2lan:\n\t\tcase e1000_pch_lpt:\n\t\t\t/* In case the PHY needs to be in mdio slow mode,\n\t\t\t * set slow mode and try to get the PHY id again.\n\t\t\t */\n\t\t\tret_val = e1000_set_mdio_slow_mode_hv(hw);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t\tret_val = e1000_get_phy_id(hw);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t\tbreak;\n\t\t}\n\tphy->type = e1000_get_phy_type_from_id(phy->id);\n\n\tswitch (phy->type) {\n\tcase e1000_phy_82577:\n\tcase e1000_phy_82579:\n\tcase e1000_phy_i217:\n\t\tphy->ops.check_polarity = e1000_check_polarity_82577;\n\t\tphy->ops.force_speed_duplex =\n\t\t\te1000_phy_force_speed_duplex_82577;\n\t\tphy->ops.get_cable_length = e1000_get_cable_length_82577;\n\t\tphy->ops.get_info = e1000_get_phy_info_82577;\n\t\tphy->ops.commit = e1000_phy_sw_reset_generic;\n\t\tbreak;\n\tcase e1000_phy_82578:\n\t\tphy->ops.check_polarity = e1000_check_polarity_m88;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;\n\t\tphy->ops.get_cable_length = e1000_get_cable_length_m88;\n\t\tphy->ops.get_info = e1000_get_phy_info_m88;\n\t\tbreak;\n\tdefault:\n\t\tret_val = -E1000_ERR_PHY;\n\t\tbreak;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_phy_params_ich8lan - Initialize PHY function pointers\n * @hw: pointer to the HW structure\n *\n * Initialize family-specific PHY parameters and function pointers.\n **/\nSTATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 i = 0;\n\n\tDEBUGFUNC(\"e1000_init_phy_params_ich8lan\");\n\n\tphy->addr\t\t= 1;\n\tphy->reset_delay_us\t= 100;\n\n\tphy->ops.acquire\t= e1000_acquire_swflag_ich8lan;\n\tphy->ops.check_reset_block = e1000_check_reset_block_ich8lan;\n\tphy->ops.get_cable_length = e1000_get_cable_length_igp_2;\n\tphy->ops.get_cfg_done\t= e1000_get_cfg_done_ich8lan;\n\tphy->ops.read_reg\t= e1000_read_phy_reg_igp;\n\tphy->ops.release\t= e1000_release_swflag_ich8lan;\n\tphy->ops.reset\t\t= e1000_phy_hw_reset_ich8lan;\n\tphy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;\n\tphy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;\n\tphy->ops.write_reg\t= e1000_write_phy_reg_igp;\n\tphy->ops.power_up\t= e1000_power_up_phy_copper;\n\tphy->ops.power_down\t= e1000_power_down_phy_copper_ich8lan;\n\n\t/* We may need to do this twice - once for IGP and if that fails,\n\t * we'll set BM func pointers and try again\n\t */\n\tret_val = e1000_determine_phy_address(hw);\n\tif (ret_val) {\n\t\tphy->ops.write_reg = e1000_write_phy_reg_bm;\n\t\tphy->ops.read_reg = e1000_read_phy_reg_bm;\n\t\tret_val = e1000_determine_phy_address(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Cannot determine PHY addr. Erroring out\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\tphy->id = 0;\n\twhile ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&\n\t (i++ < 100)) {\n\t\tmsec_delay(1);\n\t\tret_val = e1000_get_phy_id(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* Verify phy id */\n\tswitch (phy->id) {\n\tcase IGP03E1000_E_PHY_ID:\n\t\tphy->type = e1000_phy_igp_3;\n\t\tphy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;\n\t\tphy->ops.read_reg_locked = e1000_read_phy_reg_igp_locked;\n\t\tphy->ops.write_reg_locked = e1000_write_phy_reg_igp_locked;\n\t\tphy->ops.get_info = e1000_get_phy_info_igp;\n\t\tphy->ops.check_polarity = e1000_check_polarity_igp;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;\n\t\tbreak;\n\tcase IFE_E_PHY_ID:\n\tcase IFE_PLUS_E_PHY_ID:\n\tcase IFE_C_E_PHY_ID:\n\t\tphy->type = e1000_phy_ife;\n\t\tphy->autoneg_mask = E1000_ALL_NOT_GIG;\n\t\tphy->ops.get_info = e1000_get_phy_info_ife;\n\t\tphy->ops.check_polarity = e1000_check_polarity_ife;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;\n\t\tbreak;\n\tcase BME1000_E_PHY_ID:\n\t\tphy->type = e1000_phy_bm;\n\t\tphy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;\n\t\tphy->ops.read_reg = e1000_read_phy_reg_bm;\n\t\tphy->ops.write_reg = e1000_write_phy_reg_bm;\n\t\tphy->ops.commit = e1000_phy_sw_reset_generic;\n\t\tphy->ops.get_info = e1000_get_phy_info_m88;\n\t\tphy->ops.check_polarity = e1000_check_polarity_m88;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;\n\t\tbreak;\n\tdefault:\n\t\treturn -E1000_ERR_PHY;\n\t\tbreak;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers\n * @hw: pointer to the HW structure\n *\n * Initialize family-specific NVM parameters and function\n * pointers.\n **/\nSTATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tstruct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;\n\tu32 gfpreg, sector_base_addr, sector_end_addr;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_init_nvm_params_ich8lan\");\n\n\t/* Can't read flash registers if the register set isn't mapped. */\n\tnvm->type = e1000_nvm_flash_sw;\n\tif (!hw->flash_address) {\n\t\tDEBUGOUT(\"ERROR: Flash registers not mapped\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tgfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);\n\n\t/* sector_X_addr is a \"sector\"-aligned address (4096 bytes)\n\t * Add 1 to sector_end_addr since this sector is included in\n\t * the overall size.\n\t */\n\tsector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;\n\tsector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;\n\n\t/* flash_base_addr is byte-aligned */\n\tnvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;\n\n\t/* find total size of the NVM, then cut in half since the total\n\t * size represents two separate NVM banks.\n\t */\n\tnvm->flash_bank_size = ((sector_end_addr - sector_base_addr)\n\t\t\t\t<< FLASH_SECTOR_ADDR_SHIFT);\n\tnvm->flash_bank_size /= 2;\n\t/* Adjust to word count */\n\tnvm->flash_bank_size /= sizeof(u16);\n\n\tnvm->word_size = E1000_SHADOW_RAM_WORDS;\n\n\t/* Clear shadow ram */\n\tfor (i = 0; i < nvm->word_size; i++) {\n\t\tdev_spec->shadow_ram[i].modified = false;\n\t\tdev_spec->shadow_ram[i].value = 0xFFFF;\n\t}\n\n\tE1000_MUTEX_INIT(&dev_spec->nvm_mutex);\n\tE1000_MUTEX_INIT(&dev_spec->swflag_mutex);\n\n\t/* Function Pointers */\n\tnvm->ops.acquire\t= e1000_acquire_nvm_ich8lan;\n\tnvm->ops.release\t= e1000_release_nvm_ich8lan;\n\tnvm->ops.read\t\t= e1000_read_nvm_ich8lan;\n\tnvm->ops.update\t\t= e1000_update_nvm_checksum_ich8lan;\n\tnvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;\n\tnvm->ops.validate\t= e1000_validate_nvm_checksum_ich8lan;\n\tnvm->ops.write\t\t= e1000_write_nvm_ich8lan;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_mac_params_ich8lan - Initialize MAC function pointers\n * @hw: pointer to the HW structure\n *\n * Initialize family-specific MAC parameters and function\n * pointers.\n **/\nSTATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)\n\tu16 pci_cfg;\n#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */\n\n\tDEBUGFUNC(\"e1000_init_mac_params_ich8lan\");\n\n\t/* Set media type function pointer */\n\thw->phy.media_type = e1000_media_type_copper;\n\n\t/* Set mta register count */\n\tmac->mta_reg_count = 32;\n\t/* Set rar entry count */\n\tmac->rar_entry_count = E1000_ICH_RAR_ENTRIES;\n\tif (mac->type == e1000_ich8lan)\n\t\tmac->rar_entry_count--;\n\t/* Set if part includes ASF firmware */\n\tmac->asf_firmware_present = true;\n\t/* FWSM register */\n\tmac->has_fwsm = true;\n\t/* ARC subsystem not supported */\n\tmac->arc_subsystem_valid = false;\n\t/* Adaptive IFS supported */\n\tmac->adaptive_ifs = true;\n\n\t/* Function pointers */\n\n\t/* bus type/speed/width */\n\tmac->ops.get_bus_info = e1000_get_bus_info_ich8lan;\n\t/* function id */\n\tmac->ops.set_lan_id = e1000_set_lan_id_single_port;\n\t/* reset */\n\tmac->ops.reset_hw = e1000_reset_hw_ich8lan;\n\t/* hw initialization */\n\tmac->ops.init_hw = e1000_init_hw_ich8lan;\n\t/* link setup */\n\tmac->ops.setup_link = e1000_setup_link_ich8lan;\n\t/* physical interface setup */\n\tmac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;\n\t/* check for link */\n\tmac->ops.check_for_link = e1000_check_for_copper_link_ich8lan;\n\t/* link info */\n\tmac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;\n\t/* multicast address update */\n\tmac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;\n\t/* clear hardware counters */\n\tmac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;\n\n\t/* LED and other operations */\n\tswitch (mac->type) {\n\tcase e1000_ich8lan:\n\tcase e1000_ich9lan:\n\tcase e1000_ich10lan:\n\t\t/* check management mode */\n\t\tmac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;\n\t\t/* ID LED init */\n\t\tmac->ops.id_led_init = e1000_id_led_init_generic;\n\t\t/* blink LED */\n\t\tmac->ops.blink_led = e1000_blink_led_generic;\n\t\t/* setup LED */\n\t\tmac->ops.setup_led = e1000_setup_led_generic;\n\t\t/* cleanup LED */\n\t\tmac->ops.cleanup_led = e1000_cleanup_led_ich8lan;\n\t\t/* turn on/off LED */\n\t\tmac->ops.led_on = e1000_led_on_ich8lan;\n\t\tmac->ops.led_off = e1000_led_off_ich8lan;\n\t\tbreak;\n\tcase e1000_pch2lan:\n\t\tmac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;\n\t\tmac->ops.rar_set = e1000_rar_set_pch2lan;\n\t\t/* fall-through */\n\tcase e1000_pch_lpt:\n#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT\n\t\t/* multicast address update for pch2 */\n\t\tmac->ops.update_mc_addr_list =\n\t\t\te1000_update_mc_addr_list_pch2lan;\n#endif\n\tcase e1000_pchlan:\n#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)\n\t\t/* save PCH revision_id */\n\t\te1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg);\n\t\thw->revision_id = (u8)(pci_cfg &= 0x000F);\n#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */\n\t\t/* check management mode */\n\t\tmac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;\n\t\t/* ID LED init */\n\t\tmac->ops.id_led_init = e1000_id_led_init_pchlan;\n\t\t/* setup LED */\n\t\tmac->ops.setup_led = e1000_setup_led_pchlan;\n\t\t/* cleanup LED */\n\t\tmac->ops.cleanup_led = e1000_cleanup_led_pchlan;\n\t\t/* turn on/off LED */\n\t\tmac->ops.led_on = e1000_led_on_pchlan;\n\t\tmac->ops.led_off = e1000_led_off_pchlan;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (mac->type == e1000_pch_lpt) {\n\t\tmac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;\n\t\tmac->ops.rar_set = e1000_rar_set_pch_lpt;\n\t\tmac->ops.setup_physical_interface = e1000_setup_copper_link_pch_lpt;\n\t}\n\n\t/* Enable PCS Lock-loss workaround for ICH8 */\n\tif (mac->type == e1000_ich8lan)\n\t\te1000_set_kmrn_lock_loss_workaround_ich8lan(hw, true);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * __e1000_access_emi_reg_locked - Read/write EMI register\n * @hw: pointer to the HW structure\n * @addr: EMI address to program\n * @data: pointer to value to read/write from/to the EMI address\n * @read: boolean flag to indicate read or write\n *\n * This helper function assumes the SW/FW/HW Semaphore is already acquired.\n **/\nSTATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,\n\t\t\t\t\t u16 *data, bool read)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"__e1000_access_emi_reg_locked\");\n\n\tret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR, address);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (read)\n\t\tret_val = hw->phy.ops.read_reg_locked(hw, I82579_EMI_DATA,\n\t\t\t\t\t\t data);\n\telse\n\t\tret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,\n\t\t\t\t\t\t *data);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_emi_reg_locked - Read Extended Management Interface register\n * @hw: pointer to the HW structure\n * @addr: EMI address to program\n * @data: value to be read from the EMI address\n *\n * Assumes the SW/FW/HW Semaphore is already acquired.\n **/\ns32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)\n{\n\tDEBUGFUNC(\"e1000_read_emi_reg_locked\");\n\n\treturn __e1000_access_emi_reg_locked(hw, addr, data, true);\n}\n\n/**\n * e1000_write_emi_reg_locked - Write Extended Management Interface register\n * @hw: pointer to the HW structure\n * @addr: EMI address to program\n * @data: value to be written to the EMI address\n *\n * Assumes the SW/FW/HW Semaphore is already acquired.\n **/\ns32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)\n{\n\tDEBUGFUNC(\"e1000_read_emi_reg_locked\");\n\n\treturn __e1000_access_emi_reg_locked(hw, addr, &data, false);\n}\n\n/**\n * e1000_set_eee_pchlan - Enable/disable EEE support\n * @hw: pointer to the HW structure\n *\n * Enable/disable EEE based on setting in dev_spec structure, the duplex of\n * the link and the EEE capabilities of the link partner. The LPI Control\n * register bits will remain set only if/when link is up.\n *\n * EEE LPI must not be asserted earlier than one second after link is up.\n * On 82579, EEE LPI should not be enabled until such time otherwise there\n * can be link issues with some switches. Other devices can have EEE LPI\n * enabled immediately upon link up since they have a timer in hardware which\n * prevents LPI from being asserted too early.\n **/\ns32 e1000_set_eee_pchlan(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;\n\ts32 ret_val;\n\tu16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;\n\n\tDEBUGFUNC(\"e1000_set_eee_pchlan\");\n\n\tswitch (hw->phy.type) {\n\tcase e1000_phy_82579:\n\t\tlpa = I82579_EEE_LP_ABILITY;\n\t\tpcs_status = I82579_EEE_PCS_STATUS;\n\t\tadv_addr = I82579_EEE_ADVERTISEMENT;\n\t\tbreak;\n\tcase e1000_phy_i217:\n\t\tlpa = I217_EEE_LP_ABILITY;\n\t\tpcs_status = I217_EEE_PCS_STATUS;\n\t\tadv_addr = I217_EEE_ADVERTISEMENT;\n\t\tbreak;\n\tdefault:\n\t\treturn E1000_SUCCESS;\n\t}\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = hw->phy.ops.read_reg_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);\n\tif (ret_val)\n\t\tgoto release;\n\n\t/* Clear bits that enable EEE in various speeds */\n\tlpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;\n\n\t/* Enable EEE if not disabled by user */\n\tif (!dev_spec->eee_disable) {\n\t\t/* Save off link partner's EEE ability */\n\t\tret_val = e1000_read_emi_reg_locked(hw, lpa,\n\t\t\t\t\t\t &dev_spec->eee_lp_ability);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\n\t\t/* Read EEE advertisement */\n\t\tret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\n\t\t/* Enable EEE only for speeds in which the link partner is\n\t\t * EEE capable and for which we advertise EEE.\n\t\t */\n\t\tif (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)\n\t\t\tlpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;\n\n\t\tif (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {\n\t\t\thw->phy.ops.read_reg_locked(hw, PHY_LP_ABILITY, &data);\n\t\t\tif (data & NWAY_LPAR_100TX_FD_CAPS)\n\t\t\t\tlpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;\n\t\t\telse\n\t\t\t\t/* EEE is not supported in 100Half, so ignore\n\t\t\t\t * partner's EEE in 100 ability if full-duplex\n\t\t\t\t * is not advertised.\n\t\t\t\t */\n\t\t\t\tdev_spec->eee_lp_ability &=\n\t\t\t\t ~I82579_EEE_100_SUPPORTED;\n\t\t}\n\t}\n\n\t/* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */\n\tret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);\n\tif (ret_val)\n\t\tgoto release;\n\n\tret_val = hw->phy.ops.write_reg_locked(hw, I82579_LPI_CTRL, lpi_ctrl);\nrelease:\n\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP\n * @hw: pointer to the HW structure\n * @link: link up bool flag\n *\n * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications\n * preventing further DMA write requests. Workaround the issue by disabling\n * the de-assertion of the clock request when in 1Gpbs mode.\n * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link\n * speeds in order to avoid Tx hangs.\n **/\nSTATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)\n{\n\tu32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);\n\tu32 status = E1000_READ_REG(hw, E1000_STATUS);\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 reg;\n\n\tif (link && (status & E1000_STATUS_SPEED_1000)) {\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val =\n\t\t e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,\n\t\t\t\t\t ®);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\n\t\tret_val =\n\t\t e1000_write_kmrn_reg_locked(hw,\n\t\t\t\t\t\tE1000_KMRNCTRLSTA_K1_CONFIG,\n\t\t\t\t\t\treg &\n\t\t\t\t\t\t~E1000_KMRNCTRLSTA_K1_ENABLE);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\n\t\tusec_delay(10);\n\n\t\tE1000_WRITE_REG(hw, E1000_FEXTNVM6,\n\t\t\t\tfextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);\n\n\t\tret_val =\n\t\t e1000_write_kmrn_reg_locked(hw,\n\t\t\t\t\t\tE1000_KMRNCTRLSTA_K1_CONFIG,\n\t\t\t\t\t\treg);\nrelease:\n\t\thw->phy.ops.release(hw);\n\t} else {\n\t\t/* clear FEXTNVM6 bit 8 on link down or 10/100 */\n\t\tfextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;\n\n\t\tif (!link || ((status & E1000_STATUS_SPEED_100) &&\n\t\t\t (status & E1000_STATUS_FD)))\n\t\t\tgoto update_fextnvm6;\n\n\t\tret_val = hw->phy.ops.read_reg(hw, I217_INBAND_CTRL, ®);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Clear link status transmit timeout */\n\t\treg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;\n\n\t\tif (status & E1000_STATUS_SPEED_100) {\n\t\t\t/* Set inband Tx timeout to 5x10us for 100Half */\n\t\t\treg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;\n\n\t\t\t/* Do not extend the K1 entry latency for 100Half */\n\t\t\tfextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;\n\t\t} else {\n\t\t\t/* Set inband Tx timeout to 50x10us for 10Full/Half */\n\t\t\treg |= 50 <<\n\t\t\t I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;\n\n\t\t\t/* Extend the K1 entry latency for 10 Mbps */\n\t\t\tfextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;\n\t\t}\n\n\t\tret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\nupdate_fextnvm6:\n\t\tE1000_WRITE_REG(hw, E1000_FEXTNVM6, fextnvm6);\n\t}\n\n\treturn ret_val;\n}\n\n#if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)\n/**\n * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP\n * @hw: pointer to the HW structure\n * @to_sx: boolean indicating a system power state transition to Sx\n *\n * When link is down, configure ULP mode to significantly reduce the power\n * to the PHY. If on a Manageability Engine (ME) enabled system, tell the\n * ME firmware to start the ULP configuration. If not on an ME enabled\n * system, configure the ULP mode by software.\n */\ns32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)\n{\n\tu32 mac_reg;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 phy_reg;\n\n\tif ((hw->mac.type < e1000_pch_lpt) ||\n\t (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||\n\t (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||\n\t (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))\n\t\treturn 0;\n\n\tif (!to_sx) {\n\t\tint i = 0;\n\n\t\t/* Poll up to 5 seconds for Cable Disconnected indication */\n\t\twhile (!(E1000_READ_REG(hw, E1000_FEXT) &\n\t\t\t E1000_FEXT_PHY_CABLE_DISCONNECTED)) {\n\t\t\t/* Bail if link is re-acquired */\n\t\t\tif (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)\n\t\t\t\treturn -E1000_ERR_PHY;\n\n\t\t\tif (i++ == 100)\n\t\t\t\tbreak;\n\n\t\t\tmsec_delay(50);\n\t\t}\n\t\tDEBUGOUT2(\"CABLE_DISCONNECTED %s set after %dmsec\\n\",\n\t\t\t (E1000_READ_REG(hw, E1000_FEXT) &\n\t\t\t E1000_FEXT_PHY_CABLE_DISCONNECTED) ? \"\" : \"not\",\n\t\t\t i * 50);\n\t}\n\n\tif (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {\n\t\t/* Request ME configure ULP mode in the PHY */\n\t\tmac_reg = E1000_READ_REG(hw, E1000_H2ME);\n\t\tmac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;\n\t\tE1000_WRITE_REG(hw, E1000_H2ME, mac_reg);\n\n\t\tgoto out;\n\t}\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/* During S0 Idle keep the phy in PCI-E mode */\n\tif (hw->dev_spec.ich8lan.smbus_disable)\n\t\tgoto skip_smbus;\n\n\t/* Force SMBus mode in PHY */\n\tret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);\n\tif (ret_val)\n\t\tgoto release;\n\tphy_reg |= CV_SMB_CTRL_FORCE_SMBUS;\n\te1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);\n\n\t/* Force SMBus mode in MAC */\n\tmac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tmac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);\n\nskip_smbus:\n\tif (!to_sx) {\n\t\t/* Change the 'Link Status Change' interrupt to trigger\n\t\t * on 'Cable Status Change'\n\t\t */\n\t\tret_val = e1000_read_kmrn_reg_locked(hw,\n\t\t\t\t\t\t E1000_KMRNCTRLSTA_OP_MODES,\n\t\t\t\t\t\t &phy_reg);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t\tphy_reg |= E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;\n\t\te1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,\n\t\t\t\t\t phy_reg);\n\t}\n\n\t/* Set Inband ULP Exit, Reset to SMBus mode and\n\t * Disable SMBus Release on PERST# in PHY\n\t */\n\tret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);\n\tif (ret_val)\n\t\tgoto release;\n\tphy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |\n\t\t I218_ULP_CONFIG1_DISABLE_SMB_PERST);\n\tif (to_sx) {\n\t\tif (E1000_READ_REG(hw, E1000_WUFC) & E1000_WUFC_LNKC)\n\t\t\tphy_reg |= I218_ULP_CONFIG1_WOL_HOST;\n\n\t\tphy_reg |= I218_ULP_CONFIG1_STICKY_ULP;\n\t} else {\n\t\tphy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;\n\t}\n\te1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);\n\n\t/* Set Disable SMBus Release on PERST# in MAC */\n\tmac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);\n\tmac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;\n\tE1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);\n\n\t/* Commit ULP changes in PHY by starting auto ULP configuration */\n\tphy_reg |= I218_ULP_CONFIG1_START;\n\te1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);\n\n\tif (!to_sx) {\n\t\t/* Disable Tx so that the MAC doesn't send any (buffered)\n\t\t * packets to the PHY.\n\t\t */\n\t\tmac_reg = E1000_READ_REG(hw, E1000_TCTL);\n\t\tmac_reg &= ~E1000_TCTL_EN;\n\t\tE1000_WRITE_REG(hw, E1000_TCTL, mac_reg);\n\t}\nrelease:\n\thw->phy.ops.release(hw);\nout:\n\tif (ret_val)\n\t\tDEBUGOUT1(\"Error in ULP enable flow: %d\\n\", ret_val);\n\telse\n\t\thw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP\n * @hw: pointer to the HW structure\n * @force: boolean indicating whether or not to force disabling ULP\n *\n * Un-configure ULP mode when link is up, the system is transitioned from\n * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled\n * system, poll for an indication from ME that ULP has been un-configured.\n * If not on an ME enabled system, un-configure the ULP mode by software.\n *\n * During nominal operation, this function is called when link is acquired\n * to disable ULP mode (force=false); otherwise, for example when unloading\n * the driver or during Sx->S0 transitions, this is called with force=true\n * to forcibly disable ULP.\n\n * When the cable is plugged in while the device is in D0, a Cable Status\n * Change interrupt is generated which causes this function to be called\n * to partially disable ULP mode and restart autonegotiation. This function\n * is then called again due to the resulting Link Status Change interrupt\n * to finish cleaning up after the ULP flow.\n */\ns32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 mac_reg;\n\tu16 phy_reg;\n\tint i = 0;\n\n\tif ((hw->mac.type < e1000_pch_lpt) ||\n\t (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||\n\t (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V) ||\n\t (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))\n\t\treturn 0;\n\n\tif (E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID) {\n\t\tif (force) {\n\t\t\t/* Request ME un-configure ULP mode in the PHY */\n\t\t\tmac_reg = E1000_READ_REG(hw, E1000_H2ME);\n\t\t\tmac_reg &= ~E1000_H2ME_ULP;\n\t\t\tmac_reg |= E1000_H2ME_ENFORCE_SETTINGS;\n\t\t\tE1000_WRITE_REG(hw, E1000_H2ME, mac_reg);\n\t\t}\n\n\t\t/* Poll up to 100msec for ME to clear ULP_CFG_DONE */\n\t\twhile (E1000_READ_REG(hw, E1000_FWSM) &\n\t\t E1000_FWSM_ULP_CFG_DONE) {\n\t\t\tif (i++ == 10) {\n\t\t\t\tret_val = -E1000_ERR_PHY;\n\t\t\t\tgoto out;\n\t\t\t}\n\n\t\t\tmsec_delay(10);\n\t\t}\n\t\tDEBUGOUT1(\"ULP_CONFIG_DONE cleared after %dmsec\\n\", i * 10);\n\n\t\tif (force) {\n\t\t\tmac_reg = E1000_READ_REG(hw, E1000_H2ME);\n\t\t\tmac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;\n\t\t\tE1000_WRITE_REG(hw, E1000_H2ME, mac_reg);\n\t\t} else {\n\t\t\t/* Clear H2ME.ULP after ME ULP configuration */\n\t\t\tmac_reg = E1000_READ_REG(hw, E1000_H2ME);\n\t\t\tmac_reg &= ~E1000_H2ME_ULP;\n\t\t\tE1000_WRITE_REG(hw, E1000_H2ME, mac_reg);\n\n\t\t\t/* Restore link speed advertisements and restart\n\t\t\t * Auto-negotiation\n\t\t\t */\n\t\t\tret_val = e1000_phy_setup_autoneg(hw);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tret_val = e1000_oem_bits_config_ich8lan(hw, true);\n\t\t}\n\n\t\tgoto out;\n\t}\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/* Revert the change to the 'Link Status Change'\n\t * interrupt to trigger on 'Cable Status Change'\n\t */\n\tret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES,\n\t\t\t\t\t &phy_reg);\n\tif (ret_val)\n\t\tgoto release;\n\tphy_reg &= ~E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC;\n\te1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_OP_MODES, phy_reg);\n\n\tif (force)\n\t\t/* Toggle LANPHYPC Value bit */\n\t\te1000_toggle_lanphypc_pch_lpt(hw);\n\n\t/* Unforce SMBus mode in PHY */\n\tret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);\n\tif (ret_val) {\n\t\t/* The MAC might be in PCIe mode, so temporarily force to\n\t\t * SMBus mode in order to access the PHY.\n\t\t */\n\t\tmac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\tmac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);\n\n\t\tmsec_delay(50);\n\n\t\tret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,\n\t\t\t\t\t\t &phy_reg);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t}\n\tphy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;\n\te1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);\n\n\t/* Unforce SMBus mode in MAC */\n\tmac_reg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tmac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, mac_reg);\n\n\t/* When ULP mode was previously entered, K1 was disabled by the\n\t * hardware. Re-Enable K1 in the PHY when exiting ULP.\n\t */\n\tret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);\n\tif (ret_val)\n\t\tgoto release;\n\tphy_reg |= HV_PM_CTRL_K1_ENABLE;\n\te1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);\n\n\t/* Clear ULP enabled configuration */\n\tret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);\n\tif (ret_val)\n\t\tgoto release;\n\t/* CSC interrupt received due to ULP Indication */\n\tif ((phy_reg & I218_ULP_CONFIG1_IND) || force) {\n\t\tphy_reg &= ~(I218_ULP_CONFIG1_IND |\n\t\t\t I218_ULP_CONFIG1_STICKY_ULP |\n\t\t\t I218_ULP_CONFIG1_RESET_TO_SMBUS |\n\t\t\t I218_ULP_CONFIG1_WOL_HOST |\n\t\t\t I218_ULP_CONFIG1_INBAND_EXIT |\n\t\t\t I218_ULP_CONFIG1_DISABLE_SMB_PERST);\n\t\te1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);\n\n\t\t/* Commit ULP changes by starting auto ULP configuration */\n\t\tphy_reg |= I218_ULP_CONFIG1_START;\n\t\te1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);\n\n\t\t/* Clear Disable SMBus Release on PERST# in MAC */\n\t\tmac_reg = E1000_READ_REG(hw, E1000_FEXTNVM7);\n\t\tmac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;\n\t\tE1000_WRITE_REG(hw, E1000_FEXTNVM7, mac_reg);\n\n\t\tif (!force) {\n\t\t\thw->phy.ops.release(hw);\n\n\t\t\tif (hw->mac.autoneg)\n\t\t\t\te1000_phy_setup_autoneg(hw);\n\n\t\t\te1000_sw_lcd_config_ich8lan(hw);\n\n\t\t\te1000_oem_bits_config_ich8lan(hw, true);\n\n\t\t\t/* Set ULP state to unknown and return non-zero to\n\t\t\t * indicate no link (yet) and re-enter on the next LSC\n\t\t\t * to finish disabling ULP flow.\n\t\t\t */\n\t\t\thw->dev_spec.ich8lan.ulp_state =\n\t\t\t e1000_ulp_state_unknown;\n\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\t/* Re-enable Tx */\n\tmac_reg = E1000_READ_REG(hw, E1000_TCTL);\n\tmac_reg |= E1000_TCTL_EN;\n\tE1000_WRITE_REG(hw, E1000_TCTL, mac_reg);\n\nrelease:\n\thw->phy.ops.release(hw);\n\tif (force) {\n\t\thw->phy.ops.reset(hw);\n\t\tmsec_delay(50);\n\t}\nout:\n\tif (ret_val)\n\t\tDEBUGOUT1(\"Error in ULP disable flow: %d\\n\", ret_val);\n\telse\n\t\thw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;\n\n\treturn ret_val;\n}\n\n#endif /* NAHUM6LP_HW && ULP_SUPPORT */\n/**\n * e1000_check_for_copper_link_ich8lan - Check for link (Copper)\n * @hw: pointer to the HW structure\n *\n * Checks to see of the link status of the hardware has changed. If a\n * change in link status has been detected, then we read the PHY registers\n * to get the current speed/duplex if link exists.\n **/\nSTATIC s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val;\n\tbool link = false;\n\tu16 phy_reg;\n\n\tDEBUGFUNC(\"e1000_check_for_copper_link_ich8lan\");\n\n\t/* We only want to go out to the PHY registers to see if Auto-Neg\n\t * has completed and/or if our link status has changed. The\n\t * get_link_status flag is set upon receiving a Link Status\n\t * Change or Rx Sequence Error interrupt.\n\t */\n\tif (!mac->get_link_status)\n\t\treturn E1000_SUCCESS;\n\n\tif ((hw->mac.type < e1000_pch_lpt) ||\n\t (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM) ||\n\t (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V)) {\n\t\t/* First we want to see if the MII Status Register reports\n\t\t * link. If so, then we want to get the current speed/duplex\n\t\t * of the PHY.\n\t\t */\n\t\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\t/* Check the MAC's STATUS register to determine link state\n\t\t * since the PHY could be inaccessible while in ULP mode.\n\t\t */\n\t\tlink = !!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);\n\t\tif (link)\n\t\t\tret_val = e1000_disable_ulp_lpt_lp(hw, false);\n\t\telse\n\t\t\tret_val = e1000_enable_ulp_lpt_lp(hw, false);\n\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tif (hw->mac.type == e1000_pchlan) {\n\t\tret_val = e1000_k1_gig_workaround_hv(hw, link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* When connected at 10Mbps half-duplex, some parts are excessively\n\t * aggressive resulting in many collisions. To avoid this, increase\n\t * the IPG and reduce Rx latency in the PHY.\n\t */\n\tif (((hw->mac.type == e1000_pch2lan) ||\n\t (hw->mac.type == e1000_pch_lpt)) && link) {\n\t\tu32 reg;\n\t\treg = E1000_READ_REG(hw, E1000_STATUS);\n\t\tif (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {\n\t\t\tu16 emi_addr;\n\n\t\t\treg = E1000_READ_REG(hw, E1000_TIPG);\n\t\t\treg &= ~E1000_TIPG_IPGT_MASK;\n\t\t\treg |= 0xFF;\n\t\t\tE1000_WRITE_REG(hw, E1000_TIPG, reg);\n\n\t\t\t/* Reduce Rx latency in analog PHY */\n\t\t\tret_val = hw->phy.ops.acquire(hw);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tif (hw->mac.type == e1000_pch2lan)\n\t\t\t\temi_addr = I82579_RX_CONFIG;\n\t\t\telse\n\t\t\t\temi_addr = I217_RX_CONFIG;\n\t\t\tret_val = e1000_write_emi_reg_locked(hw, emi_addr, 0);\n\n\t\t\thw->phy.ops.release(hw);\n\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\t/* Work-around I218 hang issue */\n\tif ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||\n\t (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) {\n\t\tret_val = e1000_k1_workaround_lpt_lp(hw, link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* Clear link partner's EEE ability */\n\thw->dev_spec.ich8lan.eee_lp_ability = 0;\n\n\tif (!link)\n\t\treturn E1000_SUCCESS; /* No link detected */\n\n\tmac->get_link_status = false;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_pch2lan:\n\t\tret_val = e1000_k1_workaround_lv(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\t/* fall-thru */\n\tcase e1000_pchlan:\n\t\tif (hw->phy.type == e1000_phy_82578) {\n\t\t\tret_val = e1000_link_stall_workaround_hv(hw);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t}\n\n\t\t/* Workaround for PCHx parts in half-duplex:\n\t\t * Set the number of preambles removed from the packet\n\t\t * when it is passed from the PHY to the MAC to prevent\n\t\t * the MAC from misinterpreting the packet type.\n\t\t */\n\t\thw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);\n\t\tphy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;\n\n\t\tif ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=\n\t\t E1000_STATUS_FD)\n\t\t\tphy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);\n\n\t\thw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Check if there was DownShift, must be checked\n\t * immediately after link-up\n\t */\n\te1000_check_downshift_generic(hw);\n\n\t/* Enable/Disable EEE after link up */\n\tif (hw->phy.type > e1000_phy_82579) {\n\t\tret_val = e1000_set_eee_pchlan(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* If we are forcing speed/duplex, then we simply return since\n\t * we have already determined whether we have link or not.\n\t */\n\tif (!mac->autoneg)\n\t\treturn -E1000_ERR_CONFIG;\n\n\t/* Auto-Neg is enabled. Auto Speed Detection takes care\n\t * of MAC speed/duplex configuration. So we only need to\n\t * configure Collision Distance in the MAC.\n\t */\n\tmac->ops.config_collision_dist(hw);\n\n\t/* Configure Flow Control now that Auto-Neg has completed.\n\t * First, we need to restore the desired flow control\n\t * settings because we may have had to re-autoneg with a\n\t * different link partner.\n\t */\n\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers\n * @hw: pointer to the HW structure\n *\n * Initialize family-specific function pointers for PHY, MAC, and NVM.\n **/\nvoid e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_function_pointers_ich8lan\");\n\n\thw->mac.ops.init_params = e1000_init_mac_params_ich8lan;\n\thw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;\n\tswitch (hw->mac.type) {\n\tcase e1000_ich8lan:\n\tcase e1000_ich9lan:\n\tcase e1000_ich10lan:\n\t\thw->phy.ops.init_params = e1000_init_phy_params_ich8lan;\n\t\tbreak;\n\tcase e1000_pchlan:\n\tcase e1000_pch2lan:\n\tcase e1000_pch_lpt:\n\t\thw->phy.ops.init_params = e1000_init_phy_params_pchlan;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n/**\n * e1000_acquire_nvm_ich8lan - Acquire NVM mutex\n * @hw: pointer to the HW structure\n *\n * Acquires the mutex for performing NVM operations.\n **/\nSTATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_acquire_nvm_ich8lan\");\n\n\tE1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.nvm_mutex);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_release_nvm_ich8lan - Release NVM mutex\n * @hw: pointer to the HW structure\n *\n * Releases the mutex used while performing NVM operations.\n **/\nSTATIC void e1000_release_nvm_ich8lan(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_release_nvm_ich8lan\");\n\n\tE1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.nvm_mutex);\n\n\treturn;\n}\n\n/**\n * e1000_acquire_swflag_ich8lan - Acquire software control flag\n * @hw: pointer to the HW structure\n *\n * Acquires the software control flag for performing PHY and select\n * MAC CSR accesses.\n **/\nSTATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)\n{\n\tu32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_acquire_swflag_ich8lan\");\n\n\tE1000_MUTEX_LOCK(&hw->dev_spec.ich8lan.swflag_mutex);\n\n\twhile (timeout) {\n\t\textcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);\n\t\tif (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))\n\t\t\tbreak;\n\n\t\tmsec_delay_irq(1);\n\t\ttimeout--;\n\t}\n\n\tif (!timeout) {\n\t\tDEBUGOUT(\"SW has already locked the resource.\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t\tgoto out;\n\t}\n\n\ttimeout = SW_FLAG_TIMEOUT;\n\n\textcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;\n\tE1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);\n\n\twhile (timeout) {\n\t\textcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);\n\t\tif (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)\n\t\t\tbreak;\n\n\t\tmsec_delay_irq(1);\n\t\ttimeout--;\n\t}\n\n\tif (!timeout) {\n\t\tDEBUGOUT2(\"Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\\n\",\n\t\t\t E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);\n\t\textcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;\n\t\tE1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);\n\t\tret_val = -E1000_ERR_CONFIG;\n\t\tgoto out;\n\t}\n\nout:\n\tif (ret_val)\n\t\tE1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_release_swflag_ich8lan - Release software control flag\n * @hw: pointer to the HW structure\n *\n * Releases the software control flag for performing PHY and select\n * MAC CSR accesses.\n **/\nSTATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw)\n{\n\tu32 extcnf_ctrl;\n\n\tDEBUGFUNC(\"e1000_release_swflag_ich8lan\");\n\n\textcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);\n\n\tif (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {\n\t\textcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;\n\t\tE1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);\n\t} else {\n\t\tDEBUGOUT(\"Semaphore unexpectedly released by sw/fw/hw\\n\");\n\t}\n\n\tE1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);\n\n\treturn;\n}\n\n/**\n * e1000_check_mng_mode_ich8lan - Checks management mode\n * @hw: pointer to the HW structure\n *\n * This checks if the adapter has any manageability enabled.\n * This is a function pointer entry point only called by read/write\n * routines for the PHY and NVM parts.\n **/\nSTATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)\n{\n\tu32 fwsm;\n\n\tDEBUGFUNC(\"e1000_check_mng_mode_ich8lan\");\n\n\tfwsm = E1000_READ_REG(hw, E1000_FWSM);\n\n\treturn (fwsm & E1000_ICH_FWSM_FW_VALID) &&\n\t ((fwsm & E1000_FWSM_MODE_MASK) ==\n\t\t(E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));\n}\n\n/**\n * e1000_check_mng_mode_pchlan - Checks management mode\n * @hw: pointer to the HW structure\n *\n * This checks if the adapter has iAMT enabled.\n * This is a function pointer entry point only called by read/write\n * routines for the PHY and NVM parts.\n **/\nSTATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)\n{\n\tu32 fwsm;\n\n\tDEBUGFUNC(\"e1000_check_mng_mode_pchlan\");\n\n\tfwsm = E1000_READ_REG(hw, E1000_FWSM);\n\n\treturn (fwsm & E1000_ICH_FWSM_FW_VALID) &&\n\t (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));\n}\n\n/**\n * e1000_rar_set_pch2lan - Set receive address register\n * @hw: pointer to the HW structure\n * @addr: pointer to the receive address\n * @index: receive address array register\n *\n * Sets the receive address array register at index to the address passed\n * in by addr. For 82579, RAR[0] is the base address register that is to\n * contain the MAC address but RAR[1-6] are reserved for manageability (ME).\n * Use SHRA[0-3] in place of those reserved for ME.\n **/\nSTATIC void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)\n{\n\tu32 rar_low, rar_high;\n\n\tDEBUGFUNC(\"e1000_rar_set_pch2lan\");\n\n\t/* HW expects these in little endian so we reverse the byte order\n\t * from network order (big endian) to little endian\n\t */\n\trar_low = ((u32) addr[0] |\n\t\t ((u32) addr[1] << 8) |\n\t\t ((u32) addr[2] << 16) | ((u32) addr[3] << 24));\n\n\trar_high = ((u32) addr[4] | ((u32) addr[5] << 8));\n\n\t/* If MAC address zero, no need to set the AV bit */\n\tif (rar_low || rar_high)\n\t\trar_high |= E1000_RAH_AV;\n\n\tif (index == 0) {\n\t\tE1000_WRITE_REG(hw, E1000_RAL(index), rar_low);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tE1000_WRITE_REG(hw, E1000_RAH(index), rar_high);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\treturn;\n\t}\n\n\t/* RAR[1-6] are owned by manageability. Skip those and program the\n\t * next address into the SHRA register array.\n\t */\n\tif (index < (u32) (hw->mac.rar_entry_count)) {\n\t\ts32 ret_val;\n\n\t\tret_val = e1000_acquire_swflag_ich8lan(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tE1000_WRITE_REG(hw, E1000_SHRAL(index - 1), rar_low);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tE1000_WRITE_REG(hw, E1000_SHRAH(index - 1), rar_high);\n\t\tE1000_WRITE_FLUSH(hw);\n\n\t\te1000_release_swflag_ich8lan(hw);\n\n\t\t/* verify the register updates */\n\t\tif ((E1000_READ_REG(hw, E1000_SHRAL(index - 1)) == rar_low) &&\n\t\t (E1000_READ_REG(hw, E1000_SHRAH(index - 1)) == rar_high))\n\t\t\treturn;\n\n\t\tDEBUGOUT2(\"SHRA[%d] might be locked by ME - FWSM=0x%8.8x\\n\",\n\t\t\t (index - 1), E1000_READ_REG(hw, E1000_FWSM));\n\t}\n\nout:\n\tDEBUGOUT1(\"Failed to write receive address at index %d\\n\", index);\n}\n\n/**\n * e1000_rar_set_pch_lpt - Set receive address registers\n * @hw: pointer to the HW structure\n * @addr: pointer to the receive address\n * @index: receive address array register\n *\n * Sets the receive address register array at index to the address passed\n * in by addr. For LPT, RAR[0] is the base address register that is to\n * contain the MAC address. SHRA[0-10] are the shared receive address\n * registers that are shared between the Host and manageability engine (ME).\n **/\nSTATIC void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)\n{\n\tu32 rar_low, rar_high;\n\tu32 wlock_mac;\n\n\tDEBUGFUNC(\"e1000_rar_set_pch_lpt\");\n\n\t/* HW expects these in little endian so we reverse the byte order\n\t * from network order (big endian) to little endian\n\t */\n\trar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |\n\t\t ((u32) addr[2] << 16) | ((u32) addr[3] << 24));\n\n\trar_high = ((u32) addr[4] | ((u32) addr[5] << 8));\n\n\t/* If MAC address zero, no need to set the AV bit */\n\tif (rar_low || rar_high)\n\t\trar_high |= E1000_RAH_AV;\n\n\tif (index == 0) {\n\t\tE1000_WRITE_REG(hw, E1000_RAL(index), rar_low);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tE1000_WRITE_REG(hw, E1000_RAH(index), rar_high);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\treturn;\n\t}\n\n\t/* The manageability engine (ME) can lock certain SHRAR registers that\n\t * it is using - those registers are unavailable for use.\n\t */\n\tif (index < hw->mac.rar_entry_count) {\n\t\twlock_mac = E1000_READ_REG(hw, E1000_FWSM) &\n\t\t\t E1000_FWSM_WLOCK_MAC_MASK;\n\t\twlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;\n\n\t\t/* Check if all SHRAR registers are locked */\n\t\tif (wlock_mac == 1)\n\t\t\tgoto out;\n\n\t\tif ((wlock_mac == 0) || (index <= wlock_mac)) {\n\t\t\ts32 ret_val;\n\n\t\t\tret_val = e1000_acquire_swflag_ich8lan(hw);\n\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tE1000_WRITE_REG(hw, E1000_SHRAL_PCH_LPT(index - 1),\n\t\t\t\t\trar_low);\n\t\t\tE1000_WRITE_FLUSH(hw);\n\t\t\tE1000_WRITE_REG(hw, E1000_SHRAH_PCH_LPT(index - 1),\n\t\t\t\t\trar_high);\n\t\t\tE1000_WRITE_FLUSH(hw);\n\n\t\t\te1000_release_swflag_ich8lan(hw);\n\n\t\t\t/* verify the register updates */\n\t\t\tif ((E1000_READ_REG(hw, E1000_SHRAL_PCH_LPT(index - 1)) == rar_low) &&\n\t\t\t (E1000_READ_REG(hw, E1000_SHRAH_PCH_LPT(index - 1)) == rar_high))\n\t\t\t\treturn;\n\t\t}\n\t}\n\nout:\n\tDEBUGOUT1(\"Failed to write receive address at index %d\\n\", index);\n}\n\n#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT\n/**\n * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses\n * @hw: pointer to the HW structure\n * @mc_addr_list: array of multicast addresses to program\n * @mc_addr_count: number of multicast addresses to program\n *\n * Updates entire Multicast Table Array of the PCH2 MAC and PHY.\n * The caller must have a packed mc_addr_list of multicast addresses.\n **/\nSTATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,\n\t\t\t\t\t u8 *mc_addr_list,\n\t\t\t\t\t u32 mc_addr_count)\n{\n\tu16 phy_reg = 0;\n\tint i;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_update_mc_addr_list_pch2lan\");\n\n\te1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn;\n\n\tret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);\n\tif (ret_val)\n\t\tgoto release;\n\n\tfor (i = 0; i < hw->mac.mta_reg_count; i++) {\n\t\thw->phy.ops.write_reg_page(hw, BM_MTA(i),\n\t\t\t\t\t (u16)(hw->mac.mta_shadow[i] &\n\t\t\t\t\t\t 0xFFFF));\n\t\thw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),\n\t\t\t\t\t (u16)((hw->mac.mta_shadow[i] >> 16) &\n\t\t\t\t\t\t 0xFFFF));\n\t}\n\n\te1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);\n\nrelease:\n\thw->phy.ops.release(hw);\n}\n\n#endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */\n/**\n * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked\n * @hw: pointer to the HW structure\n *\n * Checks if firmware is blocking the reset of the PHY.\n * This is a function pointer entry point only called by\n * reset routines.\n **/\nSTATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)\n{\n\tu32 fwsm;\n\tbool blocked = false;\n\tint i = 0;\n\n\tDEBUGFUNC(\"e1000_check_reset_block_ich8lan\");\n\n\tdo {\n\t\tfwsm = E1000_READ_REG(hw, E1000_FWSM);\n\t\tif (!(fwsm & E1000_ICH_FWSM_RSPCIPHY)) {\n\t\t\tblocked = true;\n\t\t\tmsec_delay(10);\n\t\t\tcontinue;\n\t\t}\n\t\tblocked = false;\n\t} while (blocked && (i++ < 10));\n\treturn blocked ? E1000_BLK_PHY_RESET : E1000_SUCCESS;\n}\n\n/**\n * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states\n * @hw: pointer to the HW structure\n *\n * Assumes semaphore already acquired.\n *\n **/\nSTATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)\n{\n\tu16 phy_data;\n\tu32 strap = E1000_READ_REG(hw, E1000_STRAP);\n\tu32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>\n\t\tE1000_STRAP_SMT_FREQ_SHIFT;\n\ts32 ret_val;\n\n\tstrap &= E1000_STRAP_SMBUS_ADDRESS_MASK;\n\n\tret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_data &= ~HV_SMB_ADDR_MASK;\n\tphy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);\n\tphy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;\n\n\tif (hw->phy.type == e1000_phy_i217) {\n\t\t/* Restore SMBus frequency */\n\t\tif (freq--) {\n\t\t\tphy_data &= ~HV_SMB_ADDR_FREQ_MASK;\n\t\t\tphy_data |= (freq & (1 << 0)) <<\n\t\t\t\tHV_SMB_ADDR_FREQ_LOW_SHIFT;\n\t\t\tphy_data |= (freq & (1 << 1)) <<\n\t\t\t\t(HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);\n\t\t} else {\n\t\t\tDEBUGOUT(\"Unsupported SMB frequency in PHY\\n\");\n\t\t}\n\t}\n\n\treturn e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);\n}\n\n/**\n * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration\n * @hw: pointer to the HW structure\n *\n * SW should configure the LCD from the NVM extended configuration region\n * as a workaround for certain parts.\n **/\nSTATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tu32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 word_addr, reg_data, reg_addr, phy_page = 0;\n\n\tDEBUGFUNC(\"e1000_sw_lcd_config_ich8lan\");\n\n\t/* Initialize the PHY from the NVM on ICH platforms. This\n\t * is needed due to an issue where the NVM configuration is\n\t * not properly autoloaded after power transitions.\n\t * Therefore, after each PHY reset, we will load the\n\t * configuration data out of the NVM manually.\n\t */\n\tswitch (hw->mac.type) {\n\tcase e1000_ich8lan:\n\t\tif (phy->type != e1000_phy_igp_3)\n\t\t\treturn ret_val;\n\n\t\tif ((hw->device_id == E1000_DEV_ID_ICH8_IGP_AMT) ||\n\t\t (hw->device_id == E1000_DEV_ID_ICH8_IGP_C)) {\n\t\t\tsw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;\n\t\t\tbreak;\n\t\t}\n\t\t/* Fall-thru */\n\tcase e1000_pchlan:\n\tcase e1000_pch2lan:\n\tcase e1000_pch_lpt:\n\t\tsw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;\n\t\tbreak;\n\tdefault:\n\t\treturn ret_val;\n\t}\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tdata = E1000_READ_REG(hw, E1000_FEXTNVM);\n\tif (!(data & sw_cfg_mask))\n\t\tgoto release;\n\n\t/* Make sure HW does not configure LCD from PHY\n\t * extended configuration before SW configuration\n\t */\n\tdata = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);\n\tif ((hw->mac.type < e1000_pch2lan) &&\n\t (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))\n\t\t\tgoto release;\n\n\tcnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);\n\tcnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;\n\tcnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;\n\tif (!cnf_size)\n\t\tgoto release;\n\n\tcnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;\n\tcnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;\n\n\tif (((hw->mac.type == e1000_pchlan) &&\n\t !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||\n\t (hw->mac.type > e1000_pchlan)) {\n\t\t/* HW configures the SMBus address and LEDs when the\n\t\t * OEM and LCD Write Enable bits are set in the NVM.\n\t\t * When both NVM bits are cleared, SW will configure\n\t\t * them instead.\n\t\t */\n\t\tret_val = e1000_write_smbus_addr(hw);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\n\t\tdata = E1000_READ_REG(hw, E1000_LEDCTL);\n\t\tret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,\n\t\t\t\t\t\t\t(u16)data);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t}\n\n\t/* Configure LCD from extended configuration region. */\n\n\t/* cnf_base_addr is in DWORD */\n\tword_addr = (u16)(cnf_base_addr << 1);\n\n\tfor (i = 0; i < cnf_size; i++) {\n\t\tret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,\n\t\t\t\t\t ®_data);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\n\t\tret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),\n\t\t\t\t\t 1, ®_addr);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\n\t\t/* Save off the PHY page for future writes. */\n\t\tif (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {\n\t\t\tphy_page = reg_data;\n\t\t\tcontinue;\n\t\t}\n\n\t\treg_addr &= PHY_REG_MASK;\n\t\treg_addr |= phy_page;\n\n\t\tret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,\n\t\t\t\t\t\t reg_data);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t}\n\nrelease:\n\thw->phy.ops.release(hw);\n\treturn ret_val;\n}\n\n/**\n * e1000_k1_gig_workaround_hv - K1 Si workaround\n * @hw: pointer to the HW structure\n * @link: link up bool flag\n *\n * If K1 is enabled for 1Gbps, the MAC might stall when transitioning\n * from a lower speed. This workaround disables K1 whenever link is at 1Gig\n * If link is down, the function will restore the default K1 setting located\n * in the NVM.\n **/\nSTATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 status_reg = 0;\n\tbool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;\n\n\tDEBUGFUNC(\"e1000_k1_gig_workaround_hv\");\n\n\tif (hw->mac.type != e1000_pchlan)\n\t\treturn E1000_SUCCESS;\n\n\t/* Wrap the whole flow with the sw flag */\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Disable K1 when link is 1Gbps, otherwise use the NVM setting */\n\tif (link) {\n\t\tif (hw->phy.type == e1000_phy_82578) {\n\t\t\tret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,\n\t\t\t\t\t\t\t &status_reg);\n\t\t\tif (ret_val)\n\t\t\t\tgoto release;\n\n\t\t\tstatus_reg &= (BM_CS_STATUS_LINK_UP |\n\t\t\t\t BM_CS_STATUS_RESOLVED |\n\t\t\t\t BM_CS_STATUS_SPEED_MASK);\n\n\t\t\tif (status_reg == (BM_CS_STATUS_LINK_UP |\n\t\t\t\t\t BM_CS_STATUS_RESOLVED |\n\t\t\t\t\t BM_CS_STATUS_SPEED_1000))\n\t\t\t\tk1_enable = false;\n\t\t}\n\n\t\tif (hw->phy.type == e1000_phy_82577) {\n\t\t\tret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,\n\t\t\t\t\t\t\t &status_reg);\n\t\t\tif (ret_val)\n\t\t\t\tgoto release;\n\n\t\t\tstatus_reg &= (HV_M_STATUS_LINK_UP |\n\t\t\t\t HV_M_STATUS_AUTONEG_COMPLETE |\n\t\t\t\t HV_M_STATUS_SPEED_MASK);\n\n\t\t\tif (status_reg == (HV_M_STATUS_LINK_UP |\n\t\t\t\t\t HV_M_STATUS_AUTONEG_COMPLETE |\n\t\t\t\t\t HV_M_STATUS_SPEED_1000))\n\t\t\t\tk1_enable = false;\n\t\t}\n\n\t\t/* Link stall fix for link up */\n\t\tret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),\n\t\t\t\t\t\t 0x0100);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\n\t} else {\n\t\t/* Link stall fix for link down */\n\t\tret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),\n\t\t\t\t\t\t 0x4100);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t}\n\n\tret_val = e1000_configure_k1_ich8lan(hw, k1_enable);\n\nrelease:\n\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_configure_k1_ich8lan - Configure K1 power state\n * @hw: pointer to the HW structure\n * @enable: K1 state to configure\n *\n * Configure the K1 power state based on the provided parameter.\n * Assumes semaphore already acquired.\n *\n * Success returns 0, Failure returns -E1000_ERR_PHY (-2)\n **/\ns32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)\n{\n\ts32 ret_val;\n\tu32 ctrl_reg = 0;\n\tu32 ctrl_ext = 0;\n\tu32 reg = 0;\n\tu16 kmrn_reg = 0;\n\n\tDEBUGFUNC(\"e1000_configure_k1_ich8lan\");\n\n\tret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,\n\t\t\t\t\t &kmrn_reg);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (k1_enable)\n\t\tkmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;\n\telse\n\t\tkmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;\n\n\tret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,\n\t\t\t\t\t kmrn_reg);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tusec_delay(20);\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tctrl_reg = E1000_READ_REG(hw, E1000_CTRL);\n\n\treg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);\n\treg |= E1000_CTRL_FRCSPD;\n\tE1000_WRITE_REG(hw, E1000_CTRL, reg);\n\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);\n\tE1000_WRITE_FLUSH(hw);\n\tusec_delay(20);\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\tE1000_WRITE_FLUSH(hw);\n\tusec_delay(20);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration\n * @hw: pointer to the HW structure\n * @d0_state: boolean if entering d0 or d3 device state\n *\n * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are\n * collectively called OEM bits. The OEM Write Enable bit and SW Config bit\n * in NVM determines whether HW should configure LPLU and Gbe Disable.\n **/\nSTATIC s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)\n{\n\ts32 ret_val = 0;\n\tu32 mac_reg;\n\tu16 oem_reg;\n\n\tDEBUGFUNC(\"e1000_oem_bits_config_ich8lan\");\n\n\tif (hw->mac.type < e1000_pchlan)\n\t\treturn ret_val;\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (hw->mac.type == e1000_pchlan) {\n\t\tmac_reg = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);\n\t\tif (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)\n\t\t\tgoto release;\n\t}\n\n\tmac_reg = E1000_READ_REG(hw, E1000_FEXTNVM);\n\tif (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))\n\t\tgoto release;\n\n\tmac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL);\n\n\tret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);\n\tif (ret_val)\n\t\tgoto release;\n\n\toem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);\n\n\tif (d0_state) {\n\t\tif (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)\n\t\t\toem_reg |= HV_OEM_BITS_GBE_DIS;\n\n\t\tif (mac_reg & E1000_PHY_CTRL_D0A_LPLU)\n\t\t\toem_reg |= HV_OEM_BITS_LPLU;\n\t} else {\n\t\tif (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |\n\t\t E1000_PHY_CTRL_NOND0A_GBE_DISABLE))\n\t\t\toem_reg |= HV_OEM_BITS_GBE_DIS;\n\n\t\tif (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |\n\t\t E1000_PHY_CTRL_NOND0A_LPLU))\n\t\t\toem_reg |= HV_OEM_BITS_LPLU;\n\t}\n\n\t/* Set Restart auto-neg to activate the bits */\n\tif ((d0_state || (hw->mac.type != e1000_pchlan)) &&\n\t !hw->phy.ops.check_reset_block(hw))\n\t\toem_reg |= HV_OEM_BITS_RESTART_AN;\n\n\tret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);\n\nrelease:\n\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n\n/**\n * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_set_mdio_slow_mode_hv\");\n\n\tret_val = hw->phy.ops.read_reg(hw, HV_KMRN_MODE_CTRL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tdata |= HV_KMRN_MDIO_SLOW;\n\n\tret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be\n * done after every PHY reset.\n **/\nSTATIC s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_hv_phy_workarounds_ich8lan\");\n\n\tif (hw->mac.type != e1000_pchlan)\n\t\treturn E1000_SUCCESS;\n\n\t/* Set MDIO slow mode before any other MDIO access */\n\tif (hw->phy.type == e1000_phy_82577) {\n\t\tret_val = e1000_set_mdio_slow_mode_hv(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tif (((hw->phy.type == e1000_phy_82577) &&\n\t ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||\n\t ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {\n\t\t/* Disable generation of early preamble */\n\t\tret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Preamble tuning for SSC */\n\t\tret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,\n\t\t\t\t\t\t0xA204);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tif (hw->phy.type == e1000_phy_82578) {\n\t\t/* Return registers to default by doing a soft reset then\n\t\t * writing 0x3140 to the control register.\n\t\t */\n\t\tif (hw->phy.revision < 2) {\n\t\t\te1000_phy_sw_reset_generic(hw);\n\t\t\tret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,\n\t\t\t\t\t\t\t0x3140);\n\t\t}\n\t}\n\n\t/* Select page 0 */\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\thw->phy.addr = 1;\n\tret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);\n\thw->phy.ops.release(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Configure the K1 Si workaround during phy reset assuming there is\n\t * link so that it disables K1 if link is in 1Gbps.\n\t */\n\tret_val = e1000_k1_gig_workaround_hv(hw, true);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Workaround for link disconnects on a busy hub in half duplex */\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\tret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);\n\tif (ret_val)\n\t\tgoto release;\n\tret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,\n\t\t\t\t\t phy_data & 0x00FF);\n\tif (ret_val)\n\t\tgoto release;\n\n\t/* set MSE higher to enable link to stay up when noise is high */\n\tret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);\nrelease:\n\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY\n * @hw: pointer to the HW structure\n **/\nvoid e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)\n{\n\tu32 mac_reg;\n\tu16 i, phy_reg = 0;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_copy_rx_addrs_to_phy_ich8lan\");\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn;\n\tret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);\n\tif (ret_val)\n\t\tgoto release;\n\n\t/* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */\n\tfor (i = 0; i < (hw->mac.rar_entry_count); i++) {\n\t\tmac_reg = E1000_READ_REG(hw, E1000_RAL(i));\n\t\thw->phy.ops.write_reg_page(hw, BM_RAR_L(i),\n\t\t\t\t\t (u16)(mac_reg & 0xFFFF));\n\t\thw->phy.ops.write_reg_page(hw, BM_RAR_M(i),\n\t\t\t\t\t (u16)((mac_reg >> 16) & 0xFFFF));\n\n\t\tmac_reg = E1000_READ_REG(hw, E1000_RAH(i));\n\t\thw->phy.ops.write_reg_page(hw, BM_RAR_H(i),\n\t\t\t\t\t (u16)(mac_reg & 0xFFFF));\n\t\thw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),\n\t\t\t\t\t (u16)((mac_reg & E1000_RAH_AV)\n\t\t\t\t\t\t >> 16));\n\t}\n\n\te1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);\n\nrelease:\n\thw->phy.ops.release(hw);\n}\n\n#ifndef CRC32_OS_SUPPORT\nSTATIC u32 e1000_calc_rx_da_crc(u8 mac[])\n{\n\tu32 poly = 0xEDB88320;\t/* Polynomial for 802.3 CRC calculation */\n\tu32 i, j, mask, crc;\n\n\tDEBUGFUNC(\"e1000_calc_rx_da_crc\");\n\n\tcrc = 0xffffffff;\n\tfor (i = 0; i < 6; i++) {\n\t\tcrc = crc ^ mac[i];\n\t\tfor (j = 8; j > 0; j--) {\n\t\t\tmask = (crc & 1) * (-1);\n\t\t\tcrc = (crc >> 1) ^ (poly & mask);\n\t\t}\n\t}\n\treturn ~crc;\n}\n\n#endif /* CRC32_OS_SUPPORT */\n/**\n * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation\n * with 82579 PHY\n * @hw: pointer to the HW structure\n * @enable: flag to enable/disable workaround when enabling/disabling jumbos\n **/\ns32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 phy_reg, data;\n\tu32 mac_reg;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_lv_jumbo_workaround_ich8lan\");\n\n\tif (hw->mac.type < e1000_pch2lan)\n\t\treturn E1000_SUCCESS;\n\n\t/* disable Rx path while enabling/disabling workaround */\n\thw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);\n\tret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),\n\t\t\t\t\tphy_reg | (1 << 14));\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (enable) {\n\t\t/* Write Rx addresses (rar_entry_count for RAL/H, and\n\t\t * SHRAL/H) and initial CRC values to the MAC\n\t\t */\n\t\tfor (i = 0; i < hw->mac.rar_entry_count; i++) {\n\t\t\tu8 mac_addr[ETH_ADDR_LEN] = {0};\n\t\t\tu32 addr_high, addr_low;\n\n\t\t\taddr_high = E1000_READ_REG(hw, E1000_RAH(i));\n\t\t\tif (!(addr_high & E1000_RAH_AV))\n\t\t\t\tcontinue;\n\t\t\taddr_low = E1000_READ_REG(hw, E1000_RAL(i));\n\t\t\tmac_addr[0] = (addr_low & 0xFF);\n\t\t\tmac_addr[1] = ((addr_low >> 8) & 0xFF);\n\t\t\tmac_addr[2] = ((addr_low >> 16) & 0xFF);\n\t\t\tmac_addr[3] = ((addr_low >> 24) & 0xFF);\n\t\t\tmac_addr[4] = (addr_high & 0xFF);\n\t\t\tmac_addr[5] = ((addr_high >> 8) & 0xFF);\n\n#ifndef CRC32_OS_SUPPORT\n\t\t\tE1000_WRITE_REG(hw, E1000_PCH_RAICC(i),\n\t\t\t\t\te1000_calc_rx_da_crc(mac_addr));\n#else /* CRC32_OS_SUPPORT */\n\t\t\tE1000_WRITE_REG(hw, E1000_PCH_RAICC(i),\n\t\t\t\t\tE1000_CRC32(ETH_ADDR_LEN, mac_addr));\n#endif /* CRC32_OS_SUPPORT */\n\t\t}\n\n\t\t/* Write Rx addresses to the PHY */\n\t\te1000_copy_rx_addrs_to_phy_ich8lan(hw);\n\n\t\t/* Enable jumbo frame workaround in the MAC */\n\t\tmac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);\n\t\tmac_reg &= ~(1 << 14);\n\t\tmac_reg |= (7 << 15);\n\t\tE1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);\n\n\t\tmac_reg = E1000_READ_REG(hw, E1000_RCTL);\n\t\tmac_reg |= E1000_RCTL_SECRC;\n\t\tE1000_WRITE_REG(hw, E1000_RCTL, mac_reg);\n\n\t\tret_val = e1000_read_kmrn_reg_generic(hw,\n\t\t\t\t\t\tE1000_KMRNCTRLSTA_CTRL_OFFSET,\n\t\t\t\t\t\t&data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tret_val = e1000_write_kmrn_reg_generic(hw,\n\t\t\t\t\t\tE1000_KMRNCTRLSTA_CTRL_OFFSET,\n\t\t\t\t\t\tdata | (1 << 0));\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tret_val = e1000_read_kmrn_reg_generic(hw,\n\t\t\t\t\t\tE1000_KMRNCTRLSTA_HD_CTRL,\n\t\t\t\t\t\t&data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tdata &= ~(0xF << 8);\n\t\tdata |= (0xB << 8);\n\t\tret_val = e1000_write_kmrn_reg_generic(hw,\n\t\t\t\t\t\tE1000_KMRNCTRLSTA_HD_CTRL,\n\t\t\t\t\t\tdata);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Enable jumbo frame workaround in the PHY */\n\t\thw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);\n\t\tdata &= ~(0x7F << 5);\n\t\tdata |= (0x37 << 5);\n\t\tret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\thw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);\n\t\tdata &= ~(1 << 13);\n\t\tret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\thw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);\n\t\tdata &= ~(0x3FF << 2);\n\t\tdata |= (0x1A << 2);\n\t\tret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\thw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);\n\t\tret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |\n\t\t\t\t\t\t(1 << 10));\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\t/* Write MAC register values back to h/w defaults */\n\t\tmac_reg = E1000_READ_REG(hw, E1000_FFLT_DBG);\n\t\tmac_reg &= ~(0xF << 14);\n\t\tE1000_WRITE_REG(hw, E1000_FFLT_DBG, mac_reg);\n\n\t\tmac_reg = E1000_READ_REG(hw, E1000_RCTL);\n\t\tmac_reg &= ~E1000_RCTL_SECRC;\n\t\tE1000_WRITE_REG(hw, E1000_RCTL, mac_reg);\n\n\t\tret_val = e1000_read_kmrn_reg_generic(hw,\n\t\t\t\t\t\tE1000_KMRNCTRLSTA_CTRL_OFFSET,\n\t\t\t\t\t\t&data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tret_val = e1000_write_kmrn_reg_generic(hw,\n\t\t\t\t\t\tE1000_KMRNCTRLSTA_CTRL_OFFSET,\n\t\t\t\t\t\tdata & ~(1 << 0));\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tret_val = e1000_read_kmrn_reg_generic(hw,\n\t\t\t\t\t\tE1000_KMRNCTRLSTA_HD_CTRL,\n\t\t\t\t\t\t&data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tdata &= ~(0xF << 8);\n\t\tdata |= (0xB << 8);\n\t\tret_val = e1000_write_kmrn_reg_generic(hw,\n\t\t\t\t\t\tE1000_KMRNCTRLSTA_HD_CTRL,\n\t\t\t\t\t\tdata);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Write PHY register values back to h/w defaults */\n\t\thw->phy.ops.read_reg(hw, PHY_REG(769, 23), &data);\n\t\tdata &= ~(0x7F << 5);\n\t\tret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 23), data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\thw->phy.ops.read_reg(hw, PHY_REG(769, 16), &data);\n\t\tdata |= (1 << 13);\n\t\tret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 16), data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\thw->phy.ops.read_reg(hw, PHY_REG(776, 20), &data);\n\t\tdata &= ~(0x3FF << 2);\n\t\tdata |= (0x8 << 2);\n\t\tret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0x7E00);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\thw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);\n\t\tret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &\n\t\t\t\t\t\t~(1 << 10));\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* re-enable Rx path after enabling/disabling workaround */\n\treturn hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &\n\t\t\t\t ~(1 << 14));\n}\n\n/**\n * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be\n * done after every PHY reset.\n **/\nSTATIC s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_lv_phy_workarounds_ich8lan\");\n\n\tif (hw->mac.type != e1000_pch2lan)\n\t\treturn E1000_SUCCESS;\n\n\t/* Set MDIO slow mode before any other MDIO access */\n\tret_val = e1000_set_mdio_slow_mode_hv(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\t/* set MSE higher to enable link to stay up when noise is high */\n\tret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);\n\tif (ret_val)\n\t\tgoto release;\n\t/* drop link after 5 times MSE threshold was reached */\n\tret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);\nrelease:\n\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_k1_gig_workaround_lv - K1 Si workaround\n * @hw: pointer to the HW structure\n *\n * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps\n * Disable K1 for 1000 and 100 speeds\n **/\nSTATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 status_reg = 0;\n\n\tDEBUGFUNC(\"e1000_k1_workaround_lv\");\n\n\tif (hw->mac.type != e1000_pch2lan)\n\t\treturn E1000_SUCCESS;\n\n\t/* Set K1 beacon duration based on 10Mbs speed */\n\tret_val = hw->phy.ops.read_reg(hw, HV_M_STATUS, &status_reg);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))\n\t == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {\n\t\tif (status_reg &\n\t\t (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {\n\t\t\tu16 pm_phy_reg;\n\n\t\t\t/* LV 1G/100 Packet drop issue wa */\n\t\t\tret_val = hw->phy.ops.read_reg(hw, HV_PM_CTRL,\n\t\t\t\t\t\t &pm_phy_reg);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t\tpm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;\n\t\t\tret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL,\n\t\t\t\t\t\t\tpm_phy_reg);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t} else {\n\t\t\tu32 mac_reg;\n\t\t\tmac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);\n\t\t\tmac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;\n\t\t\tmac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;\n\t\t\tE1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);\n\t\t}\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware\n * @hw: pointer to the HW structure\n * @gate: boolean set to true to gate, false to ungate\n *\n * Gate/ungate the automatic PHY configuration via hardware; perform\n * the configuration via software instead.\n **/\nSTATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)\n{\n\tu32 extcnf_ctrl;\n\n\tDEBUGFUNC(\"e1000_gate_hw_phy_config_ich8lan\");\n\n\tif (hw->mac.type < e1000_pch2lan)\n\t\treturn;\n\n\textcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);\n\n\tif (gate)\n\t\textcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;\n\telse\n\t\textcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;\n\n\tE1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);\n}\n\n/**\n * e1000_lan_init_done_ich8lan - Check for PHY config completion\n * @hw: pointer to the HW structure\n *\n * Check the appropriate indication the MAC has finished configuring the\n * PHY after a software reset.\n **/\nSTATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)\n{\n\tu32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;\n\n\tDEBUGFUNC(\"e1000_lan_init_done_ich8lan\");\n\n\t/* Wait for basic configuration completes before proceeding */\n\tdo {\n\t\tdata = E1000_READ_REG(hw, E1000_STATUS);\n\t\tdata &= E1000_STATUS_LAN_INIT_DONE;\n\t\tusec_delay(100);\n\t} while ((!data) && --loop);\n\n\t/* If basic configuration is incomplete before the above loop\n\t * count reaches 0, loading the configuration from NVM will\n\t * leave the PHY in a bad state possibly resulting in no link.\n\t */\n\tif (loop == 0)\n\t\tDEBUGOUT(\"LAN_INIT_DONE not set, increase timeout\\n\");\n\n\t/* Clear the Init Done bit for the next init event */\n\tdata = E1000_READ_REG(hw, E1000_STATUS);\n\tdata &= ~E1000_STATUS_LAN_INIT_DONE;\n\tE1000_WRITE_REG(hw, E1000_STATUS, data);\n}\n\n/**\n * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 reg;\n\n\tDEBUGFUNC(\"e1000_post_phy_reset_ich8lan\");\n\n\tif (hw->phy.ops.check_reset_block(hw))\n\t\treturn E1000_SUCCESS;\n\n\t/* Allow time for h/w to get to quiescent state after reset */\n\tmsec_delay(10);\n\n\t/* Perform any necessary post-reset workarounds */\n\tswitch (hw->mac.type) {\n\tcase e1000_pchlan:\n\t\tret_val = e1000_hv_phy_workarounds_ich8lan(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tbreak;\n\tcase e1000_pch2lan:\n\t\tret_val = e1000_lv_phy_workarounds_ich8lan(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Clear the host wakeup bit after lcd reset */\n\tif (hw->mac.type >= e1000_pchlan) {\n\t\thw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, ®);\n\t\treg &= ~BM_WUC_HOST_WU_BIT;\n\t\thw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);\n\t}\n\n\t/* Configure the LCD with the extended configuration region in NVM */\n\tret_val = e1000_sw_lcd_config_ich8lan(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Configure the LCD with the OEM bits in NVM */\n\tret_val = e1000_oem_bits_config_ich8lan(hw, true);\n\n\tif (hw->mac.type == e1000_pch2lan) {\n\t\t/* Ungate automatic PHY configuration on non-managed 82579 */\n\t\tif (!(E1000_READ_REG(hw, E1000_FWSM) &\n\t\t E1000_ICH_FWSM_FW_VALID)) {\n\t\t\tmsec_delay(10);\n\t\t\te1000_gate_hw_phy_config_ich8lan(hw, false);\n\t\t}\n\n\t\t/* Set EEE LPI Update Timer to 200usec */\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tret_val = e1000_write_emi_reg_locked(hw,\n\t\t\t\t\t\t I82579_LPI_UPDATE_TIMER,\n\t\t\t\t\t\t 0x1387);\n\t\thw->phy.ops.release(hw);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_hw_reset_ich8lan - Performs a PHY reset\n * @hw: pointer to the HW structure\n *\n * Resets the PHY\n * This is a function pointer entry point called by drivers\n * or other shared routines.\n **/\nSTATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_phy_hw_reset_ich8lan\");\n\n\t/* Gate automatic PHY configuration by hardware on non-managed 82579 */\n\tif ((hw->mac.type == e1000_pch2lan) &&\n\t !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))\n\t\te1000_gate_hw_phy_config_ich8lan(hw, true);\n\n\tret_val = e1000_phy_hw_reset_generic(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn e1000_post_phy_reset_ich8lan(hw);\n}\n\n/**\n * e1000_set_lplu_state_pchlan - Set Low Power Link Up state\n * @hw: pointer to the HW structure\n * @active: true to enable LPLU, false to disable\n *\n * Sets the LPLU state according to the active flag. For PCH, if OEM write\n * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set\n * the phy speed. This function will manually set the LPLU bit and restart\n * auto-neg as hw would do. D3 and D0 LPLU will call the same function\n * since it configures the same bit.\n **/\nSTATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)\n{\n\ts32 ret_val;\n\tu16 oem_reg;\n\n\tDEBUGFUNC(\"e1000_set_lplu_state_pchlan\");\n\n\tret_val = hw->phy.ops.read_reg(hw, HV_OEM_BITS, &oem_reg);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (active)\n\t\toem_reg |= HV_OEM_BITS_LPLU;\n\telse\n\t\toem_reg &= ~HV_OEM_BITS_LPLU;\n\n\tif (!hw->phy.ops.check_reset_block(hw))\n\t\toem_reg |= HV_OEM_BITS_RESTART_AN;\n\n\treturn hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);\n}\n\n/**\n * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state\n * @hw: pointer to the HW structure\n * @active: true to enable LPLU, false to disable\n *\n * Sets the LPLU D0 state according to the active flag. When\n * activating LPLU this function also disables smart speed\n * and vice versa. LPLU will not be activated unless the\n * device autonegotiation advertisement meets standards of\n * either 10 or 10/100 or 10/100/1000 at all duplexes.\n * This is a function pointer entry point only called by\n * PHY setup routines.\n **/\nSTATIC s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tu32 phy_ctrl;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_set_d0_lplu_state_ich8lan\");\n\n\tif (phy->type == e1000_phy_ife)\n\t\treturn E1000_SUCCESS;\n\n\tphy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);\n\n\tif (active) {\n\t\tphy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;\n\t\tE1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);\n\n\t\tif (phy->type != e1000_phy_igp_3)\n\t\t\treturn E1000_SUCCESS;\n\n\t\t/* Call gig speed drop workaround on LPLU before accessing\n\t\t * any PHY registers\n\t\t */\n\t\tif (hw->mac.type == e1000_ich8lan)\n\t\t\te1000_gig_downshift_workaround_ich8lan(hw);\n\n\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\tphy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;\n\t\tE1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);\n\n\t\tif (phy->type != e1000_phy_igp_3)\n\t\t\treturn E1000_SUCCESS;\n\n\t\t/* LPLU and SmartSpeed are mutually exclusive. LPLU is used\n\t\t * during Dx states where the power conservation is most\n\t\t * important. During driver activity we should enable\n\t\t * SmartSpeed, so performance is maintained.\n\t\t */\n\t\tif (phy->smart_speed == e1000_smart_speed_on) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata |= IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t} else if (phy->smart_speed == e1000_smart_speed_off) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state\n * @hw: pointer to the HW structure\n * @active: true to enable LPLU, false to disable\n *\n * Sets the LPLU D3 state according to the active flag. When\n * activating LPLU this function also disables smart speed\n * and vice versa. LPLU will not be activated unless the\n * device autonegotiation advertisement meets standards of\n * either 10 or 10/100 or 10/100/1000 at all duplexes.\n * This is a function pointer entry point only called by\n * PHY setup routines.\n **/\nSTATIC s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tu32 phy_ctrl;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_set_d3_lplu_state_ich8lan\");\n\n\tphy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);\n\n\tif (!active) {\n\t\tphy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;\n\t\tE1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);\n\n\t\tif (phy->type != e1000_phy_igp_3)\n\t\t\treturn E1000_SUCCESS;\n\n\t\t/* LPLU and SmartSpeed are mutually exclusive. LPLU is used\n\t\t * during Dx states where the power conservation is most\n\t\t * important. During driver activity we should enable\n\t\t * SmartSpeed, so performance is maintained.\n\t\t */\n\t\tif (phy->smart_speed == e1000_smart_speed_on) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata |= IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t} else if (phy->smart_speed == e1000_smart_speed_off) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t}\n\t} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||\n\t\t (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||\n\t\t (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {\n\t\tphy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;\n\t\tE1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);\n\n\t\tif (phy->type != e1000_phy_igp_3)\n\t\t\treturn E1000_SUCCESS;\n\n\t\t/* Call gig speed drop workaround on LPLU before accessing\n\t\t * any PHY registers\n\t\t */\n\t\tif (hw->mac.type == e1000_ich8lan)\n\t\t\te1000_gig_downshift_workaround_ich8lan(hw);\n\n\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t data);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1\n * @hw: pointer to the HW structure\n * @bank: pointer to the variable that returns the active bank\n *\n * Reads signature byte from the NVM using the flash access registers.\n * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.\n **/\nSTATIC s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)\n{\n\tu32 eecd;\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 bank1_offset = nvm->flash_bank_size * sizeof(u16);\n\tu32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;\n\tu8 sig_byte = 0;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_valid_nvm_bank_detect_ich8lan\");\n\n\tswitch (hw->mac.type) {\n\tcase e1000_ich8lan:\n\tcase e1000_ich9lan:\n\t\teecd = E1000_READ_REG(hw, E1000_EECD);\n\t\tif ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==\n\t\t E1000_EECD_SEC1VAL_VALID_MASK) {\n\t\t\tif (eecd & E1000_EECD_SEC1VAL)\n\t\t\t\t*bank = 1;\n\t\t\telse\n\t\t\t\t*bank = 0;\n\n\t\t\treturn E1000_SUCCESS;\n\t\t}\n\t\tDEBUGOUT(\"Unable to determine valid NVM bank via EEC - reading flash signature\\n\");\n\t\t/* fall-thru */\n\tdefault:\n\t\t/* set bank to 0 in case flash read fails */\n\t\t*bank = 0;\n\n\t\t/* Check bank 0 */\n\t\tret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,\n\t\t\t\t\t\t\t&sig_byte);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tif ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==\n\t\t E1000_ICH_NVM_SIG_VALUE) {\n\t\t\t*bank = 0;\n\t\t\treturn E1000_SUCCESS;\n\t\t}\n\n\t\t/* Check bank 1 */\n\t\tret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +\n\t\t\t\t\t\t\tbank1_offset,\n\t\t\t\t\t\t\t&sig_byte);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tif ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==\n\t\t E1000_ICH_NVM_SIG_VALUE) {\n\t\t\t*bank = 1;\n\t\t\treturn E1000_SUCCESS;\n\t\t}\n\n\t\tDEBUGOUT(\"ERROR: No valid NVM bank present\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n}\n\n/**\n * e1000_read_nvm_ich8lan - Read word(s) from the NVM\n * @hw: pointer to the HW structure\n * @offset: The offset (in bytes) of the word(s) to read.\n * @words: Size of data to read in words\n * @data: Pointer to the word(s) to read at offset.\n *\n * Reads a word(s) from the NVM using the flash access registers.\n **/\nSTATIC s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t\t u16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tstruct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;\n\tu32 act_offset;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 bank = 0;\n\tu16 i, word;\n\n\tDEBUGFUNC(\"e1000_read_nvm_ich8lan\");\n\n\tif ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\tret_val = -E1000_ERR_NVM;\n\t\tgoto out;\n\t}\n\n\tnvm->ops.acquire(hw);\n\n\tret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);\n\tif (ret_val != E1000_SUCCESS) {\n\t\tDEBUGOUT(\"Could not detect valid bank, assuming bank 0\\n\");\n\t\tbank = 0;\n\t}\n\n\tact_offset = (bank) ? nvm->flash_bank_size : 0;\n\tact_offset += offset;\n\n\tret_val = E1000_SUCCESS;\n\tfor (i = 0; i < words; i++) {\n\t\tif (dev_spec->shadow_ram[offset+i].modified) {\n\t\t\tdata[i] = dev_spec->shadow_ram[offset+i].value;\n\t\t} else {\n\t\t\tret_val = e1000_read_flash_word_ich8lan(hw,\n\t\t\t\t\t\t\t\tact_offset + i,\n\t\t\t\t\t\t\t\t&word);\n\t\t\tif (ret_val)\n\t\t\t\tbreak;\n\t\t\tdata[i] = word;\n\t\t}\n\t}\n\n\tnvm->ops.release(hw);\n\nout:\n\tif (ret_val)\n\t\tDEBUGOUT1(\"NVM read error: %d\\n\", ret_val);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_flash_cycle_init_ich8lan - Initialize flash\n * @hw: pointer to the HW structure\n *\n * This function does initial flash setup so that a new read/write/erase cycle\n * can be started.\n **/\nSTATIC s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)\n{\n\tunion ich8_hws_flash_status hsfsts;\n\ts32 ret_val = -E1000_ERR_NVM;\n\n\tDEBUGFUNC(\"e1000_flash_cycle_init_ich8lan\");\n\n\thsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);\n\n\t/* Check if the flash descriptor is valid */\n\tif (!hsfsts.hsf_status.fldesvalid) {\n\t\tDEBUGOUT(\"Flash descriptor invalid. SW Sequencing must be used.\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\t/* Clear FCERR and DAEL in hw status by writing 1 */\n\thsfsts.hsf_status.flcerr = 1;\n\thsfsts.hsf_status.dael = 1;\n\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);\n\n\t/* Either we should have a hardware SPI cycle in progress\n\t * bit to check against, in order to start a new cycle or\n\t * FDONE bit should be changed in the hardware so that it\n\t * is 1 after hardware reset, which can then be used as an\n\t * indication whether a cycle is in progress or has been\n\t * completed.\n\t */\n\n\tif (!hsfsts.hsf_status.flcinprog) {\n\t\t/* There is no cycle running at present,\n\t\t * so we can start a cycle.\n\t\t * Begin by setting Flash Cycle Done.\n\t\t */\n\t\thsfsts.hsf_status.flcdone = 1;\n\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);\n\t\tret_val = E1000_SUCCESS;\n\t} else {\n\t\ts32 i;\n\n\t\t/* Otherwise poll for sometime so the current\n\t\t * cycle has a chance to end before giving up.\n\t\t */\n\t\tfor (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {\n\t\t\thsfsts.regval = E1000_READ_FLASH_REG16(hw,\n\t\t\t\t\t\t\t ICH_FLASH_HSFSTS);\n\t\t\tif (!hsfsts.hsf_status.flcinprog) {\n\t\t\t\tret_val = E1000_SUCCESS;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tusec_delay(1);\n\t\t}\n\t\tif (ret_val == E1000_SUCCESS) {\n\t\t\t/* Successful in waiting for previous cycle to timeout,\n\t\t\t * now set the Flash Cycle Done.\n\t\t\t */\n\t\t\thsfsts.hsf_status.flcdone = 1;\n\t\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,\n\t\t\t\t\t\thsfsts.regval);\n\t\t} else {\n\t\t\tDEBUGOUT(\"Flash controller busy, cannot get access\\n\");\n\t\t}\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)\n * @hw: pointer to the HW structure\n * @timeout: maximum time to wait for completion\n *\n * This function starts a flash cycle and waits for its completion.\n **/\nSTATIC s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)\n{\n\tunion ich8_hws_flash_ctrl hsflctl;\n\tunion ich8_hws_flash_status hsfsts;\n\tu32 i = 0;\n\n\tDEBUGFUNC(\"e1000_flash_cycle_ich8lan\");\n\n\t/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */\n\thsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);\n\thsflctl.hsf_ctrl.flcgo = 1;\n\n\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);\n\n\t/* wait till FDONE bit is set to 1 */\n\tdo {\n\t\thsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);\n\t\tif (hsfsts.hsf_status.flcdone)\n\t\t\tbreak;\n\t\tusec_delay(1);\n\t} while (i++ < timeout);\n\n\tif (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)\n\t\treturn E1000_SUCCESS;\n\n\treturn -E1000_ERR_NVM;\n}\n\n/**\n * e1000_read_flash_word_ich8lan - Read word from flash\n * @hw: pointer to the HW structure\n * @offset: offset to data location\n * @data: pointer to the location for storing the data\n *\n * Reads the flash word at offset into data. Offset is converted\n * to bytes before read.\n **/\nSTATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 *data)\n{\n\tDEBUGFUNC(\"e1000_read_flash_word_ich8lan\");\n\n\tif (!data)\n\t\treturn -E1000_ERR_NVM;\n\n\t/* Must convert offset into bytes. */\n\toffset <<= 1;\n\n\treturn e1000_read_flash_data_ich8lan(hw, offset, 2, data);\n}\n\n/**\n * e1000_read_flash_byte_ich8lan - Read byte from flash\n * @hw: pointer to the HW structure\n * @offset: The offset of the byte to read.\n * @data: Pointer to a byte to store the value read.\n *\n * Reads a single byte from the NVM using the flash access registers.\n **/\nSTATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u8 *data)\n{\n\ts32 ret_val;\n\tu16 word = 0;\n\n\tret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);\n\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t*data = (u8)word;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_flash_data_ich8lan - Read byte or word from NVM\n * @hw: pointer to the HW structure\n * @offset: The offset (in bytes) of the byte or word to read.\n * @size: Size of data to read, 1=byte 2=word\n * @data: Pointer to the word to store the value read.\n *\n * Reads a byte or word from the NVM using the flash access registers.\n **/\nSTATIC s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u8 size, u16 *data)\n{\n\tunion ich8_hws_flash_status hsfsts;\n\tunion ich8_hws_flash_ctrl hsflctl;\n\tu32 flash_linear_addr;\n\tu32 flash_data = 0;\n\ts32 ret_val = -E1000_ERR_NVM;\n\tu8 count = 0;\n\n\tDEBUGFUNC(\"e1000_read_flash_data_ich8lan\");\n\n\tif (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)\n\t\treturn -E1000_ERR_NVM;\n\tflash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +\n\t\t\t hw->nvm.flash_base_addr);\n\n\tdo {\n\t\tusec_delay(1);\n\t\t/* Steps */\n\t\tret_val = e1000_flash_cycle_init_ich8lan(hw);\n\t\tif (ret_val != E1000_SUCCESS)\n\t\t\tbreak;\n\t\thsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);\n\n\t\t/* 0b/1b corresponds to 1 or 2 byte size, respectively. */\n\t\thsflctl.hsf_ctrl.fldbcount = size - 1;\n\t\thsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;\n\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);\n\n\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);\n\n\t\tret_val =\n\t\t e1000_flash_cycle_ich8lan(hw,\n\t\t\t\t\t ICH_FLASH_READ_COMMAND_TIMEOUT);\n\n\t\t/* Check if FCERR is set to 1, if set to 1, clear it\n\t\t * and try the whole sequence a few more times, else\n\t\t * read in (shift in) the Flash Data0, the order is\n\t\t * least significant byte first msb to lsb\n\t\t */\n\t\tif (ret_val == E1000_SUCCESS) {\n\t\t\tflash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);\n\t\t\tif (size == 1)\n\t\t\t\t*data = (u8)(flash_data & 0x000000FF);\n\t\t\telse if (size == 2)\n\t\t\t\t*data = (u16)(flash_data & 0x0000FFFF);\n\t\t\tbreak;\n\t\t} else {\n\t\t\t/* If we've gotten here, then things are probably\n\t\t\t * completely hosed, but if the error condition is\n\t\t\t * detected, it won't hurt to give it another try...\n\t\t\t * ICH_FLASH_CYCLE_REPEAT_COUNT times.\n\t\t\t */\n\t\t\thsfsts.regval = E1000_READ_FLASH_REG16(hw,\n\t\t\t\t\t\t\t ICH_FLASH_HSFSTS);\n\t\t\tif (hsfsts.hsf_status.flcerr) {\n\t\t\t\t/* Repeat for some time before giving up. */\n\t\t\t\tcontinue;\n\t\t\t} else if (!hsfsts.hsf_status.flcdone) {\n\t\t\t\tDEBUGOUT(\"Timeout error - flash cycle did not complete.\\n\");\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_nvm_ich8lan - Write word(s) to the NVM\n * @hw: pointer to the HW structure\n * @offset: The offset (in bytes) of the word(s) to write.\n * @words: Size of data to write in words\n * @data: Pointer to the word(s) to write at offset.\n *\n * Writes a byte or word to the NVM using the flash access registers.\n **/\nSTATIC s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t\t u16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tstruct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_write_nvm_ich8lan\");\n\n\tif ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\tnvm->ops.acquire(hw);\n\n\tfor (i = 0; i < words; i++) {\n\t\tdev_spec->shadow_ram[offset+i].modified = true;\n\t\tdev_spec->shadow_ram[offset+i].value = data[i];\n\t}\n\n\tnvm->ops.release(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM\n * @hw: pointer to the HW structure\n *\n * The NVM checksum is updated by calling the generic update_nvm_checksum,\n * which writes the checksum to the shadow ram. The changes in the shadow\n * ram are then committed to the EEPROM by processing each bank at a time\n * checking for the modified bit and writing only the pending changes.\n * After a successful commit, the shadow ram is cleared and is ready for\n * future writes.\n **/\nSTATIC s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tstruct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;\n\tu32 i, act_offset, new_bank_offset, old_bank_offset, bank;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_update_nvm_checksum_ich8lan\");\n\n\tret_val = e1000_update_nvm_checksum_generic(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (nvm->type != e1000_nvm_flash_sw)\n\t\tgoto out;\n\n\tnvm->ops.acquire(hw);\n\n\t/* We're writing to the opposite bank so if we're on bank 1,\n\t * write to bank 0 etc. We also need to erase the segment that\n\t * is going to be written\n\t */\n\tret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);\n\tif (ret_val != E1000_SUCCESS) {\n\t\tDEBUGOUT(\"Could not detect valid bank, assuming bank 0\\n\");\n\t\tbank = 0;\n\t}\n\n\tif (bank == 0) {\n\t\tnew_bank_offset = nvm->flash_bank_size;\n\t\told_bank_offset = 0;\n\t\tret_val = e1000_erase_flash_bank_ich8lan(hw, 1);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t} else {\n\t\told_bank_offset = nvm->flash_bank_size;\n\t\tnew_bank_offset = 0;\n\t\tret_val = e1000_erase_flash_bank_ich8lan(hw, 0);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t}\n\n\tfor (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {\n\t\t/* Determine whether to write the value stored\n\t\t * in the other NVM bank or a modified value stored\n\t\t * in the shadow RAM\n\t\t */\n\t\tif (dev_spec->shadow_ram[i].modified) {\n\t\t\tdata = dev_spec->shadow_ram[i].value;\n\t\t} else {\n\t\t\tret_val = e1000_read_flash_word_ich8lan(hw, i +\n\t\t\t\t\t\t\t\told_bank_offset,\n\t\t\t\t\t\t\t\t&data);\n\t\t\tif (ret_val)\n\t\t\t\tbreak;\n\t\t}\n\n\t\t/* If the word is 0x13, then make sure the signature bits\n\t\t * (15:14) are 11b until the commit has completed.\n\t\t * This will allow us to write 10b which indicates the\n\t\t * signature is valid. We want to do this after the write\n\t\t * has completed so that we don't mark the segment valid\n\t\t * while the write is still in progress\n\t\t */\n\t\tif (i == E1000_ICH_NVM_SIG_WORD)\n\t\t\tdata |= E1000_ICH_NVM_SIG_MASK;\n\n\t\t/* Convert offset to bytes. */\n\t\tact_offset = (i + new_bank_offset) << 1;\n\n\t\tusec_delay(100);\n\t\t/* Write the bytes to the new bank. */\n\t\tret_val = e1000_retry_write_flash_byte_ich8lan(hw,\n\t\t\t\t\t\t\t act_offset,\n\t\t\t\t\t\t\t (u8)data);\n\t\tif (ret_val)\n\t\t\tbreak;\n\n\t\tusec_delay(100);\n\t\tret_val = e1000_retry_write_flash_byte_ich8lan(hw,\n\t\t\t\t\t\t\t act_offset + 1,\n\t\t\t\t\t\t\t (u8)(data >> 8));\n\t\tif (ret_val)\n\t\t\tbreak;\n\t}\n\n\t/* Don't bother writing the segment valid bits if sector\n\t * programming failed.\n\t */\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Flash commit failed.\\n\");\n\t\tgoto release;\n\t}\n\n\t/* Finally validate the new segment by setting bit 15:14\n\t * to 10b in word 0x13 , this can be done without an\n\t * erase as well since these bits are 11 to start with\n\t * and we need to change bit 14 to 0b\n\t */\n\tact_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;\n\tret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);\n\tif (ret_val)\n\t\tgoto release;\n\n\tdata &= 0xBFFF;\n\tret_val = e1000_retry_write_flash_byte_ich8lan(hw,\n\t\t\t\t\t\t act_offset * 2 + 1,\n\t\t\t\t\t\t (u8)(data >> 8));\n\tif (ret_val)\n\t\tgoto release;\n\n\t/* And invalidate the previously valid segment by setting\n\t * its signature word (0x13) high_byte to 0b. This can be\n\t * done without an erase because flash erase sets all bits\n\t * to 1's. We can write 1's to 0's without an erase\n\t */\n\tact_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;\n\tret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);\n\tif (ret_val)\n\t\tgoto release;\n\n\t/* Great! Everything worked, we can now clear the cached entries. */\n\tfor (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {\n\t\tdev_spec->shadow_ram[i].modified = false;\n\t\tdev_spec->shadow_ram[i].value = 0xFFFF;\n\t}\n\nrelease:\n\tnvm->ops.release(hw);\n\n\t/* Reload the EEPROM, or else modifications will not appear\n\t * until after the next adapter reset.\n\t */\n\tif (!ret_val) {\n\t\tnvm->ops.reload(hw);\n\t\tmsec_delay(10);\n\t}\n\nout:\n\tif (ret_val)\n\t\tDEBUGOUT1(\"NVM update error: %d\\n\", ret_val);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.\n * If the bit is 0, that the EEPROM had been modified, but the checksum was not\n * calculated, in which case we need to calculate the checksum and set bit 6.\n **/\nSTATIC s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 data;\n\tu16 word;\n\tu16 valid_csum_mask;\n\n\tDEBUGFUNC(\"e1000_validate_nvm_checksum_ich8lan\");\n\n\t/* Read NVM and check Invalid Image CSUM bit. If this bit is 0,\n\t * the checksum needs to be fixed. This bit is an indication that\n\t * the NVM was prepared by OEM software and did not calculate\n\t * the checksum...a likely scenario.\n\t */\n\tswitch (hw->mac.type) {\n\tcase e1000_pch_lpt:\n\t\tword = NVM_COMPAT;\n\t\tvalid_csum_mask = NVM_COMPAT_VALID_CSUM;\n\t\tbreak;\n\tdefault:\n\t\tword = NVM_FUTURE_INIT_WORD1;\n\t\tvalid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;\n\t\tbreak;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, word, 1, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!(data & valid_csum_mask)) {\n\t\tdata |= valid_csum_mask;\n\t\tret_val = hw->nvm.ops.write(hw, word, 1, &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tret_val = hw->nvm.ops.update(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\treturn e1000_validate_nvm_checksum_generic(hw);\n}\n\n/**\n * e1000_write_flash_data_ich8lan - Writes bytes to the NVM\n * @hw: pointer to the HW structure\n * @offset: The offset (in bytes) of the byte/word to read.\n * @size: Size of data to read, 1=byte 2=word\n * @data: The byte(s) to write to the NVM.\n *\n * Writes one/two bytes to the NVM using the flash access registers.\n **/\nSTATIC s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u8 size, u16 data)\n{\n\tunion ich8_hws_flash_status hsfsts;\n\tunion ich8_hws_flash_ctrl hsflctl;\n\tu32 flash_linear_addr;\n\tu32 flash_data = 0;\n\ts32 ret_val;\n\tu8 count = 0;\n\n\tDEBUGFUNC(\"e1000_write_ich8_data\");\n\n\tif (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)\n\t\treturn -E1000_ERR_NVM;\n\n\tflash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +\n\t\t\t hw->nvm.flash_base_addr);\n\n\tdo {\n\t\tusec_delay(1);\n\t\t/* Steps */\n\t\tret_val = e1000_flash_cycle_init_ich8lan(hw);\n\t\tif (ret_val != E1000_SUCCESS)\n\t\t\tbreak;\n\t\thsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);\n\n\t\t/* 0b/1b corresponds to 1 or 2 byte size, respectively. */\n\t\thsflctl.hsf_ctrl.fldbcount = size - 1;\n\t\thsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;\n\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);\n\n\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);\n\n\t\tif (size == 1)\n\t\t\tflash_data = (u32)data & 0x00FF;\n\t\telse\n\t\t\tflash_data = (u32)data;\n\n\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);\n\n\t\t/* check if FCERR is set to 1 , if set to 1, clear it\n\t\t * and try the whole sequence a few more times else done\n\t\t */\n\t\tret_val =\n\t\t e1000_flash_cycle_ich8lan(hw,\n\t\t\t\t\t ICH_FLASH_WRITE_COMMAND_TIMEOUT);\n\t\tif (ret_val == E1000_SUCCESS)\n\t\t\tbreak;\n\n\t\t/* If we're here, then things are most likely\n\t\t * completely hosed, but if the error condition\n\t\t * is detected, it won't hurt to give it another\n\t\t * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.\n\t\t */\n\t\thsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);\n\t\tif (hsfsts.hsf_status.flcerr)\n\t\t\t/* Repeat for some time before giving up. */\n\t\t\tcontinue;\n\t\tif (!hsfsts.hsf_status.flcdone) {\n\t\t\tDEBUGOUT(\"Timeout error - flash cycle did not complete.\\n\");\n\t\t\tbreak;\n\t\t}\n\t} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_flash_byte_ich8lan - Write a single byte to NVM\n * @hw: pointer to the HW structure\n * @offset: The index of the byte to read.\n * @data: The byte to write to the NVM.\n *\n * Writes a single byte to the NVM using the flash access registers.\n **/\nSTATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u8 data)\n{\n\tu16 word = (u16)data;\n\n\tDEBUGFUNC(\"e1000_write_flash_byte_ich8lan\");\n\n\treturn e1000_write_flash_data_ich8lan(hw, offset, 1, word);\n}\n\n/**\n * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM\n * @hw: pointer to the HW structure\n * @offset: The offset of the byte to write.\n * @byte: The byte to write to the NVM.\n *\n * Writes a single byte to the NVM using the flash access registers.\n * Goes through a retry algorithm before giving up.\n **/\nSTATIC s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,\n\t\t\t\t\t\tu32 offset, u8 byte)\n{\n\ts32 ret_val;\n\tu16 program_retries;\n\n\tDEBUGFUNC(\"e1000_retry_write_flash_byte_ich8lan\");\n\n\tret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);\n\tif (!ret_val)\n\t\treturn ret_val;\n\n\tfor (program_retries = 0; program_retries < 100; program_retries++) {\n\t\tDEBUGOUT2(\"Retrying Byte %2.2X at offset %u\\n\", byte, offset);\n\t\tusec_delay(100);\n\t\tret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);\n\t\tif (ret_val == E1000_SUCCESS)\n\t\t\tbreak;\n\t}\n\tif (program_retries == 100)\n\t\treturn -E1000_ERR_NVM;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM\n * @hw: pointer to the HW structure\n * @bank: 0 for first bank, 1 for second bank, etc.\n *\n * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.\n * bank N is 4096 * N + flash_reg_addr.\n **/\nSTATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tunion ich8_hws_flash_status hsfsts;\n\tunion ich8_hws_flash_ctrl hsflctl;\n\tu32 flash_linear_addr;\n\t/* bank size is in 16bit words - adjust to bytes */\n\tu32 flash_bank_size = nvm->flash_bank_size * 2;\n\ts32 ret_val;\n\ts32 count = 0;\n\ts32 j, iteration, sector_size;\n\n\tDEBUGFUNC(\"e1000_erase_flash_bank_ich8lan\");\n\n\thsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);\n\n\t/* Determine HW Sector size: Read BERASE bits of hw flash status\n\t * register\n\t * 00: The Hw sector is 256 bytes, hence we need to erase 16\n\t * consecutive sectors. The start index for the nth Hw sector\n\t * can be calculated as = bank * 4096 + n * 256\n\t * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.\n\t * The start index for the nth Hw sector can be calculated\n\t * as = bank * 4096\n\t * 10: The Hw sector is 8K bytes, nth sector = bank * 8192\n\t * (ich9 only, otherwise error condition)\n\t * 11: The Hw sector is 64K bytes, nth sector = bank * 65536\n\t */\n\tswitch (hsfsts.hsf_status.berasesz) {\n\tcase 0:\n\t\t/* Hw sector size 256 */\n\t\tsector_size = ICH_FLASH_SEG_SIZE_256;\n\t\titeration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;\n\t\tbreak;\n\tcase 1:\n\t\tsector_size = ICH_FLASH_SEG_SIZE_4K;\n\t\titeration = 1;\n\t\tbreak;\n\tcase 2:\n\t\tsector_size = ICH_FLASH_SEG_SIZE_8K;\n\t\titeration = 1;\n\t\tbreak;\n\tcase 3:\n\t\tsector_size = ICH_FLASH_SEG_SIZE_64K;\n\t\titeration = 1;\n\t\tbreak;\n\tdefault:\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\t/* Start with the base address, then add the sector offset. */\n\tflash_linear_addr = hw->nvm.flash_base_addr;\n\tflash_linear_addr += (bank) ? flash_bank_size : 0;\n\n\tfor (j = 0; j < iteration; j++) {\n\t\tdo {\n\t\t\tu32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;\n\n\t\t\t/* Steps */\n\t\t\tret_val = e1000_flash_cycle_init_ich8lan(hw);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\t/* Write a value 11 (block Erase) in Flash\n\t\t\t * Cycle field in hw flash control\n\t\t\t */\n\t\t\thsflctl.regval =\n\t\t\t E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);\n\n\t\t\thsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;\n\t\t\tE1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,\n\t\t\t\t\t\thsflctl.regval);\n\n\t\t\t/* Write the last 24 bits of an index within the\n\t\t\t * block into Flash Linear address field in Flash\n\t\t\t * Address.\n\t\t\t */\n\t\t\tflash_linear_addr += (j * sector_size);\n\t\t\tE1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,\n\t\t\t\t\t flash_linear_addr);\n\n\t\t\tret_val = e1000_flash_cycle_ich8lan(hw, timeout);\n\t\t\tif (ret_val == E1000_SUCCESS)\n\t\t\t\tbreak;\n\n\t\t\t/* Check if FCERR is set to 1. If 1,\n\t\t\t * clear it and try the whole sequence\n\t\t\t * a few more times else Done\n\t\t\t */\n\t\t\thsfsts.regval = E1000_READ_FLASH_REG16(hw,\n\t\t\t\t\t\t ICH_FLASH_HSFSTS);\n\t\t\tif (hsfsts.hsf_status.flcerr)\n\t\t\t\t/* repeat for some time before giving up */\n\t\t\t\tcontinue;\n\t\t\telse if (!hsfsts.hsf_status.flcdone)\n\t\t\t\treturn ret_val;\n\t\t} while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_valid_led_default_ich8lan - Set the default LED settings\n * @hw: pointer to the HW structure\n * @data: Pointer to the LED settings\n *\n * Reads the LED default settings from the NVM to data. If the NVM LED\n * settings is all 0's or F's, set the LED default to a valid LED default\n * setting.\n **/\nSTATIC s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_valid_led_default_ich8lan\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)\n\t\t*data = ID_LED_DEFAULT_ICH8LAN;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_id_led_init_pchlan - store LED configurations\n * @hw: pointer to the HW structure\n *\n * PCH does not control LEDs via the LEDCTL register, rather it uses\n * the PHY LED configuration register.\n *\n * PCH also does not have an \"always on\" or \"always off\" mode which\n * complicates the ID feature. Instead of using the \"on\" mode to indicate\n * in ledctl_mode2 the LEDs to use for ID (see e1000_id_led_init_generic()),\n * use \"link_up\" mode. The LEDs will still ID on request if there is no\n * link based on logic in e1000_led_[on|off]_pchlan().\n **/\nSTATIC s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val;\n\tconst u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;\n\tconst u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;\n\tu16 data, i, temp, shift;\n\n\tDEBUGFUNC(\"e1000_id_led_init_pchlan\");\n\n\t/* Get default ID LED modes */\n\tret_val = hw->nvm.ops.valid_led_default(hw, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tmac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);\n\tmac->ledctl_mode1 = mac->ledctl_default;\n\tmac->ledctl_mode2 = mac->ledctl_default;\n\n\tfor (i = 0; i < 4; i++) {\n\t\ttemp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;\n\t\tshift = (i * 5);\n\t\tswitch (temp) {\n\t\tcase ID_LED_ON1_DEF2:\n\t\tcase ID_LED_ON1_ON2:\n\t\tcase ID_LED_ON1_OFF2:\n\t\t\tmac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);\n\t\t\tmac->ledctl_mode1 |= (ledctl_on << shift);\n\t\t\tbreak;\n\t\tcase ID_LED_OFF1_DEF2:\n\t\tcase ID_LED_OFF1_ON2:\n\t\tcase ID_LED_OFF1_OFF2:\n\t\t\tmac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);\n\t\t\tmac->ledctl_mode1 |= (ledctl_off << shift);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* Do nothing */\n\t\t\tbreak;\n\t\t}\n\t\tswitch (temp) {\n\t\tcase ID_LED_DEF1_ON2:\n\t\tcase ID_LED_ON1_ON2:\n\t\tcase ID_LED_OFF1_ON2:\n\t\t\tmac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);\n\t\t\tmac->ledctl_mode2 |= (ledctl_on << shift);\n\t\t\tbreak;\n\t\tcase ID_LED_DEF1_OFF2:\n\t\tcase ID_LED_ON1_OFF2:\n\t\tcase ID_LED_OFF1_OFF2:\n\t\t\tmac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);\n\t\t\tmac->ledctl_mode2 |= (ledctl_off << shift);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* Do nothing */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_bus_info_ich8lan - Get/Set the bus type and width\n * @hw: pointer to the HW structure\n *\n * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability\n * register, so the the bus width is hard coded.\n **/\nSTATIC s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)\n{\n\tstruct e1000_bus_info *bus = &hw->bus;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_get_bus_info_ich8lan\");\n\n\tret_val = e1000_get_bus_info_pcie_generic(hw);\n\n\t/* ICH devices are \"PCI Express\"-ish. They have\n\t * a configuration space, but do not contain\n\t * PCI Express Capability registers, so bus width\n\t * must be hardcoded.\n\t */\n\tif (bus->width == e1000_bus_width_unknown)\n\t\tbus->width = e1000_bus_width_pcie_x1;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_reset_hw_ich8lan - Reset the hardware\n * @hw: pointer to the HW structure\n *\n * Does a full reset of the hardware which includes a reset of the PHY and\n * MAC.\n **/\nSTATIC s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;\n\tu16 kum_cfg;\n\tu32 ctrl, reg;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_reset_hw_ich8lan\");\n\n\t/* Prevent the PCI-E bus from sticking if there is no TLP connection\n\t * on the last TLP read/write transaction when MAC is reset.\n\t */\n\tret_val = e1000_disable_pcie_master_generic(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"PCI-E Master disable polling has failed.\\n\");\n\n\tDEBUGOUT(\"Masking off all interrupts\\n\");\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\n\t/* Disable the Transmit and Receive units. Then delay to allow\n\t * any pending transactions to complete before we hit the MAC\n\t * with the global reset.\n\t */\n\tE1000_WRITE_REG(hw, E1000_RCTL, 0);\n\tE1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);\n\tE1000_WRITE_FLUSH(hw);\n\n\tmsec_delay(10);\n\n\t/* Workaround for ICH8 bit corruption issue in FIFO memory */\n\tif (hw->mac.type == e1000_ich8lan) {\n\t\t/* Set Tx and Rx buffer allocation to 8k apiece. */\n\t\tE1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);\n\t\t/* Set Packet Buffer Size to 16k. */\n\t\tE1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);\n\t}\n\n\tif (hw->mac.type == e1000_pchlan) {\n\t\t/* Save the NVM K1 bit setting*/\n\t\tret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (kum_cfg & E1000_NVM_K1_ENABLE)\n\t\t\tdev_spec->nvm_k1_enabled = true;\n\t\telse\n\t\t\tdev_spec->nvm_k1_enabled = false;\n\t}\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\tif (!hw->phy.ops.check_reset_block(hw)) {\n\t\t/* Full-chip reset requires MAC and PHY reset at the same\n\t\t * time to make sure the interface between MAC and the\n\t\t * external PHY is reset.\n\t\t */\n\t\tctrl |= E1000_CTRL_PHY_RST;\n\n\t\t/* Gate automatic PHY configuration by hardware on\n\t\t * non-managed 82579\n\t\t */\n\t\tif ((hw->mac.type == e1000_pch2lan) &&\n\t\t !(E1000_READ_REG(hw, E1000_FWSM) & E1000_ICH_FWSM_FW_VALID))\n\t\t\te1000_gate_hw_phy_config_ich8lan(hw, true);\n\t}\n\tret_val = e1000_acquire_swflag_ich8lan(hw);\n\tDEBUGOUT(\"Issuing a global reset to ich8lan\\n\");\n\tE1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));\n\t/* cannot issue a flush here because it hangs the hardware */\n\tmsec_delay(20);\n\n\t/* Set Phy Config Counter to 50msec */\n\tif (hw->mac.type == e1000_pch2lan) {\n\t\treg = E1000_READ_REG(hw, E1000_FEXTNVM3);\n\t\treg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;\n\t\treg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;\n\t\tE1000_WRITE_REG(hw, E1000_FEXTNVM3, reg);\n\t}\n\n\tif (!ret_val)\n\t\tE1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);\n\n\tif (ctrl & E1000_CTRL_PHY_RST) {\n\t\tret_val = hw->phy.ops.get_cfg_done(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = e1000_post_phy_reset_ich8lan(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* For PCH, this write will make sure that any noise\n\t * will be detected as a CRC error and be dropped rather than show up\n\t * as a bad packet to the DMA engine.\n\t */\n\tif (hw->mac.type == e1000_pchlan)\n\t\tE1000_WRITE_REG(hw, E1000_CRC_OFFSET, 0x65656565);\n\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\tE1000_READ_REG(hw, E1000_ICR);\n\n\treg = E1000_READ_REG(hw, E1000_KABGTXD);\n\treg |= E1000_KABGTXD_BGSQLBIAS;\n\tE1000_WRITE_REG(hw, E1000_KABGTXD, reg);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_hw_ich8lan - Initialize the hardware\n * @hw: pointer to the HW structure\n *\n * Prepares the hardware for transmit and receive by doing the following:\n * - initialize hardware bits\n * - initialize LED identification\n * - setup receive address registers\n * - setup flow control\n * - setup transmit descriptors\n * - clear statistics\n **/\nSTATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 ctrl_ext, txdctl, snoop;\n\ts32 ret_val;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_init_hw_ich8lan\");\n\n\te1000_initialize_hw_bits_ich8lan(hw);\n\n\t/* Initialize identification LED */\n\tret_val = mac->ops.id_led_init(hw);\n\t/* An error is not fatal and we should not stop init due to this */\n\tif (ret_val)\n\t\tDEBUGOUT(\"Error initializing identification LED\\n\");\n\n\t/* Setup the receive address. */\n\te1000_init_rx_addrs_generic(hw, mac->rar_entry_count);\n\n\t/* Zero out the Multicast HASH table */\n\tDEBUGOUT(\"Zeroing the MTA\\n\");\n\tfor (i = 0; i < mac->mta_reg_count; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);\n\n\t/* The 82578 Rx buffer will stall if wakeup is enabled in host and\n\t * the ME. Disable wakeup by clearing the host wakeup bit.\n\t * Reset the phy after disabling host wakeup to reset the Rx buffer.\n\t */\n\tif (hw->phy.type == e1000_phy_82578) {\n\t\thw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);\n\t\ti &= ~BM_WUC_HOST_WU_BIT;\n\t\thw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);\n\t\tret_val = e1000_phy_hw_reset_ich8lan(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* Setup link and flow control */\n\tret_val = mac->ops.setup_link(hw);\n\n\t/* Set the transmit descriptor write-back policy for both queues */\n\ttxdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));\n\ttxdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |\n\t\t E1000_TXDCTL_FULL_TX_DESC_WB);\n\ttxdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |\n\t\t E1000_TXDCTL_MAX_TX_DESC_PREFETCH);\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);\n\ttxdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));\n\ttxdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |\n\t\t E1000_TXDCTL_FULL_TX_DESC_WB);\n\ttxdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |\n\t\t E1000_TXDCTL_MAX_TX_DESC_PREFETCH);\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);\n\n\t/* ICH8 has opposite polarity of no_snoop bits.\n\t * By default, we should use snoop behavior.\n\t */\n\tif (mac->type == e1000_ich8lan)\n\t\tsnoop = PCIE_ICH8_SNOOP_ALL;\n\telse\n\t\tsnoop = (u32) ~(PCIE_NO_SNOOP_ALL);\n\te1000_set_pcie_no_snoop_generic(hw, snoop);\n\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tctrl_ext |= E1000_CTRL_EXT_RO_DIS;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\n\t/* Clear all of the statistics registers (clear on read). It is\n\t * important that we do this after we have tried to establish link\n\t * because the symbol error count will increment wildly if there\n\t * is no link.\n\t */\n\te1000_clear_hw_cntrs_ich8lan(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits\n * @hw: pointer to the HW structure\n *\n * Sets/Clears required hardware bits necessary for correctly setting up the\n * hardware for transmit and receive.\n **/\nSTATIC void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)\n{\n\tu32 reg;\n\n\tDEBUGFUNC(\"e1000_initialize_hw_bits_ich8lan\");\n\n\t/* Extended Device Control */\n\treg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\treg |= (1 << 22);\n\t/* Enable PHY low-power state when MAC is at D3 w/o WoL */\n\tif (hw->mac.type >= e1000_pchlan)\n\t\treg |= E1000_CTRL_EXT_PHYPDEN;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);\n\n\t/* Transmit Descriptor Control 0 */\n\treg = E1000_READ_REG(hw, E1000_TXDCTL(0));\n\treg |= (1 << 22);\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);\n\n\t/* Transmit Descriptor Control 1 */\n\treg = E1000_READ_REG(hw, E1000_TXDCTL(1));\n\treg |= (1 << 22);\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);\n\n\t/* Transmit Arbitration Control 0 */\n\treg = E1000_READ_REG(hw, E1000_TARC(0));\n\tif (hw->mac.type == e1000_ich8lan)\n\t\treg |= (1 << 28) | (1 << 29);\n\treg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);\n\tE1000_WRITE_REG(hw, E1000_TARC(0), reg);\n\n\t/* Transmit Arbitration Control 1 */\n\treg = E1000_READ_REG(hw, E1000_TARC(1));\n\tif (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)\n\t\treg &= ~(1 << 28);\n\telse\n\t\treg |= (1 << 28);\n\treg |= (1 << 24) | (1 << 26) | (1 << 30);\n\tE1000_WRITE_REG(hw, E1000_TARC(1), reg);\n\n\t/* Device Status */\n\tif (hw->mac.type == e1000_ich8lan) {\n\t\treg = E1000_READ_REG(hw, E1000_STATUS);\n\t\treg &= ~(1 << 31);\n\t\tE1000_WRITE_REG(hw, E1000_STATUS, reg);\n\t}\n\n\t/* work-around descriptor data corruption issue during nfs v2 udp\n\t * traffic, just disable the nfs filtering capability\n\t */\n\treg = E1000_READ_REG(hw, E1000_RFCTL);\n\treg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);\n\n\t/* Disable IPv6 extension header parsing because some malformed\n\t * IPv6 headers can hang the Rx.\n\t */\n\tif (hw->mac.type == e1000_ich8lan)\n\t\treg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);\n\tE1000_WRITE_REG(hw, E1000_RFCTL, reg);\n\n\t/* Enable ECC on Lynxpoint */\n\tif (hw->mac.type == e1000_pch_lpt) {\n\t\treg = E1000_READ_REG(hw, E1000_PBECCSTS);\n\t\treg |= E1000_PBECCSTS_ECC_ENABLE;\n\t\tE1000_WRITE_REG(hw, E1000_PBECCSTS, reg);\n\n\t\treg = E1000_READ_REG(hw, E1000_CTRL);\n\t\treg |= E1000_CTRL_MEHE;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, reg);\n\t}\n\n\treturn;\n}\n\n/**\n * e1000_setup_link_ich8lan - Setup flow control and link settings\n * @hw: pointer to the HW structure\n *\n * Determines which flow control settings to use, then configures flow\n * control. Calls the appropriate media-specific link configuration\n * function. Assuming the adapter has a valid link partner, a valid link\n * should be established. Assumes the hardware has previously been reset\n * and the transmitter and receiver are not enabled.\n **/\nSTATIC s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_setup_link_ich8lan\");\n\n\tif (hw->phy.ops.check_reset_block(hw))\n\t\treturn E1000_SUCCESS;\n\n\t/* ICH parts do not have a word in the NVM to determine\n\t * the default flow control setting, so we explicitly\n\t * set it to full.\n\t */\n\tif (hw->fc.requested_mode == e1000_fc_default)\n\t\thw->fc.requested_mode = e1000_fc_full;\n\n\t/* Save off the requested flow control mode for use later. Depending\n\t * on the link partner's capabilities, we may or may not use this mode.\n\t */\n\thw->fc.current_mode = hw->fc.requested_mode;\n\n\tDEBUGOUT1(\"After fix-ups FlowControl is now = %x\\n\",\n\t\thw->fc.current_mode);\n\n\t/* Continue to configure the copper link. */\n\tret_val = hw->mac.ops.setup_physical_interface(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tE1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);\n\tif ((hw->phy.type == e1000_phy_82578) ||\n\t (hw->phy.type == e1000_phy_82579) ||\n\t (hw->phy.type == e1000_phy_i217) ||\n\t (hw->phy.type == e1000_phy_82577)) {\n\t\tE1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);\n\n\t\tret_val = hw->phy.ops.write_reg(hw,\n\t\t\t\t\t PHY_REG(BM_PORT_CTRL_PAGE, 27),\n\t\t\t\t\t hw->fc.pause_time);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\treturn e1000_set_fc_watermarks_generic(hw);\n}\n\n/**\n * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface\n * @hw: pointer to the HW structure\n *\n * Configures the kumeran interface to the PHY to wait the appropriate time\n * when polling the PHY, then call the generic setup_copper_link to finish\n * configuring the copper link.\n **/\nSTATIC s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\tu16 reg_data;\n\n\tDEBUGFUNC(\"e1000_setup_copper_link_ich8lan\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= E1000_CTRL_SLU;\n\tctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\t/* Set the mac to wait the maximum time between each iteration\n\t * and increase the max iterations when polling the phy;\n\t * this fixes erroneous timeouts at 10Mbps.\n\t */\n\tret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,\n\t\t\t\t\t 0xFFFF);\n\tif (ret_val)\n\t\treturn ret_val;\n\tret_val = e1000_read_kmrn_reg_generic(hw,\n\t\t\t\t\t E1000_KMRNCTRLSTA_INBAND_PARAM,\n\t\t\t\t\t ®_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\treg_data |= 0x3F;\n\tret_val = e1000_write_kmrn_reg_generic(hw,\n\t\t\t\t\t E1000_KMRNCTRLSTA_INBAND_PARAM,\n\t\t\t\t\t reg_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tswitch (hw->phy.type) {\n\tcase e1000_phy_igp_3:\n\t\tret_val = e1000_copper_link_setup_igp(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tbreak;\n\tcase e1000_phy_bm:\n\tcase e1000_phy_82578:\n\t\tret_val = e1000_copper_link_setup_m88(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tbreak;\n\tcase e1000_phy_82577:\n\tcase e1000_phy_82579:\n\t\tret_val = e1000_copper_link_setup_82577(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tbreak;\n\tcase e1000_phy_ife:\n\t\tret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,\n\t\t\t\t\t ®_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\treg_data &= ~IFE_PMC_AUTO_MDIX;\n\n\t\tswitch (hw->phy.mdix) {\n\t\tcase 1:\n\t\t\treg_data &= ~IFE_PMC_FORCE_MDIX;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\treg_data |= IFE_PMC_FORCE_MDIX;\n\t\t\tbreak;\n\t\tcase 0:\n\t\tdefault:\n\t\t\treg_data |= IFE_PMC_AUTO_MDIX;\n\t\t\tbreak;\n\t\t}\n\t\tret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,\n\t\t\t\t\t\treg_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn e1000_setup_copper_link_generic(hw);\n}\n\n/**\n * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface\n * @hw: pointer to the HW structure\n *\n * Calls the PHY specific link setup function and then calls the\n * generic setup_copper_link to finish configuring the link for\n * Lynxpoint PCH devices\n **/\nSTATIC s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_setup_copper_link_pch_lpt\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= E1000_CTRL_SLU;\n\tctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\tret_val = e1000_copper_link_setup_82577(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn e1000_setup_copper_link_generic(hw);\n}\n\n/**\n * e1000_get_link_up_info_ich8lan - Get current link speed and duplex\n * @hw: pointer to the HW structure\n * @speed: pointer to store current link speed\n * @duplex: pointer to store the current link duplex\n *\n * Calls the generic get_speed_and_duplex to retrieve the current link\n * information and then calls the Kumeran lock loss workaround for links at\n * gigabit speeds.\n **/\nSTATIC s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\t u16 *duplex)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_get_link_up_info_ich8lan\");\n\n\tret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif ((hw->mac.type == e1000_ich8lan) &&\n\t (hw->phy.type == e1000_phy_igp_3) &&\n\t (*speed == SPEED_1000)) {\n\t\tret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround\n * @hw: pointer to the HW structure\n *\n * Work-around for 82566 Kumeran PCS lock loss:\n * On link status change (i.e. PCI reset, speed change) and link is up and\n * speed is gigabit-\n * 0) if workaround is optionally disabled do nothing\n * 1) wait 1ms for Kumeran link to come up\n * 2) check Kumeran Diagnostic register PCS lock loss bit\n * 3) if not set the link is locked (all is good), otherwise...\n * 4) reset the PHY\n * 5) repeat up to 10 times\n * Note: this is only called for IGP3 copper when speed is 1gb.\n **/\nSTATIC s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;\n\tu32 phy_ctrl;\n\ts32 ret_val;\n\tu16 i, data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_kmrn_lock_loss_workaround_ich8lan\");\n\n\tif (!dev_spec->kmrn_lock_loss_workaround_enabled)\n\t\treturn E1000_SUCCESS;\n\n\t/* Make sure link is up before proceeding. If not just return.\n\t * Attempting this while link is negotiating fouled up link\n\t * stability\n\t */\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (!link)\n\t\treturn E1000_SUCCESS;\n\n\tfor (i = 0; i < 10; i++) {\n\t\t/* read once to clear */\n\t\tret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\t/* and again to get new status */\n\t\tret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* check for PCS lock */\n\t\tif (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))\n\t\t\treturn E1000_SUCCESS;\n\n\t\t/* Issue PHY reset */\n\t\thw->phy.ops.reset(hw);\n\t\tmsec_delay_irq(5);\n\t}\n\t/* Disable GigE link negotiation */\n\tphy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);\n\tphy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |\n\t\t E1000_PHY_CTRL_NOND0A_GBE_DISABLE);\n\tE1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);\n\n\t/* Call gig speed drop workaround on Gig disable before accessing\n\t * any PHY registers\n\t */\n\te1000_gig_downshift_workaround_ich8lan(hw);\n\n\t/* unable to acquire PCS lock */\n\treturn -E1000_ERR_PHY;\n}\n\n/**\n * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state\n * @hw: pointer to the HW structure\n * @state: boolean value used to set the current Kumeran workaround state\n *\n * If ICH8, set the current Kumeran workaround state (enabled - true\n * /disabled - false).\n **/\nvoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,\n\t\t\t\t\t\t bool state)\n{\n\tstruct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;\n\n\tDEBUGFUNC(\"e1000_set_kmrn_lock_loss_workaround_ich8lan\");\n\n\tif (hw->mac.type != e1000_ich8lan) {\n\t\tDEBUGOUT(\"Workaround applies to ICH8 only.\\n\");\n\t\treturn;\n\t}\n\n\tdev_spec->kmrn_lock_loss_workaround_enabled = state;\n\n\treturn;\n}\n\n/**\n * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3\n * @hw: pointer to the HW structure\n *\n * Workaround for 82566 power-down on D3 entry:\n * 1) disable gigabit link\n * 2) write VR power-down enable\n * 3) read it back\n * Continue if successful, else issue LCD reset and repeat\n **/\nvoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)\n{\n\tu32 reg;\n\tu16 data;\n\tu8 retry = 0;\n\n\tDEBUGFUNC(\"e1000_igp3_phy_powerdown_workaround_ich8lan\");\n\n\tif (hw->phy.type != e1000_phy_igp_3)\n\t\treturn;\n\n\t/* Try the workaround twice (if needed) */\n\tdo {\n\t\t/* Disable link */\n\t\treg = E1000_READ_REG(hw, E1000_PHY_CTRL);\n\t\treg |= (E1000_PHY_CTRL_GBE_DISABLE |\n\t\t\tE1000_PHY_CTRL_NOND0A_GBE_DISABLE);\n\t\tE1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);\n\n\t\t/* Call gig speed drop workaround on Gig disable before\n\t\t * accessing any PHY registers\n\t\t */\n\t\tif (hw->mac.type == e1000_ich8lan)\n\t\t\te1000_gig_downshift_workaround_ich8lan(hw);\n\n\t\t/* Write VR power-down enable */\n\t\thw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);\n\t\tdata &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;\n\t\thw->phy.ops.write_reg(hw, IGP3_VR_CTRL,\n\t\t\t\t data | IGP3_VR_CTRL_MODE_SHUTDOWN);\n\n\t\t/* Read it back and test */\n\t\thw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);\n\t\tdata &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;\n\t\tif ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)\n\t\t\tbreak;\n\n\t\t/* Issue PHY reset and repeat at most one more time */\n\t\treg = E1000_READ_REG(hw, E1000_CTRL);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);\n\t\tretry++;\n\t} while (retry);\n}\n\n/**\n * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working\n * @hw: pointer to the HW structure\n *\n * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),\n * LPLU, Gig disable, MDIC PHY reset):\n * 1) Set Kumeran Near-end loopback\n * 2) Clear Kumeran Near-end loopback\n * Should only be called for ICH8[m] devices with any 1G Phy.\n **/\nvoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 reg_data;\n\n\tDEBUGFUNC(\"e1000_gig_downshift_workaround_ich8lan\");\n\n\tif ((hw->mac.type != e1000_ich8lan) ||\n\t (hw->phy.type == e1000_phy_ife))\n\t\treturn;\n\n\tret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,\n\t\t\t\t\t ®_data);\n\tif (ret_val)\n\t\treturn;\n\treg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;\n\tret_val = e1000_write_kmrn_reg_generic(hw,\n\t\t\t\t\t E1000_KMRNCTRLSTA_DIAG_OFFSET,\n\t\t\t\t\t reg_data);\n\tif (ret_val)\n\t\treturn;\n\treg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;\n\te1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,\n\t\t\t\t reg_data);\n}\n\n/**\n * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx\n * @hw: pointer to the HW structure\n *\n * During S0 to Sx transition, it is possible the link remains at gig\n * instead of negotiating to a lower speed. Before going to Sx, set\n * 'Gig Disable' to force link speed negotiation to a lower speed based on\n * the LPLU setting in the NVM or custom setting. For PCH and newer parts,\n * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also\n * needs to be written.\n * Parts that support (and are linked to a partner which support) EEE in\n * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power\n * than 10Mbps w/o EEE.\n **/\nvoid e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;\n\tu32 phy_ctrl;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_suspend_workarounds_ich8lan\");\n\n\tphy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);\n\tphy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;\n\n\tif (hw->phy.type == e1000_phy_i217) {\n\t\tu16 phy_reg, device_id = hw->device_id;\n\n\t\tif ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||\n\t\t (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V)) {\n\t\t\tu32 fextnvm6 = E1000_READ_REG(hw, E1000_FEXTNVM6);\n\n\t\t\tE1000_WRITE_REG(hw, E1000_FEXTNVM6,\n\t\t\t\t\tfextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);\n\t\t}\n\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tif (!dev_spec->eee_disable) {\n\t\t\tu16 eee_advert;\n\n\t\t\tret_val =\n\t\t\t e1000_read_emi_reg_locked(hw,\n\t\t\t\t\t\t I217_EEE_ADVERTISEMENT,\n\t\t\t\t\t\t &eee_advert);\n\t\t\tif (ret_val)\n\t\t\t\tgoto release;\n\n\t\t\t/* Disable LPLU if both link partners support 100BaseT\n\t\t\t * EEE and 100Full is advertised on both ends of the\n\t\t\t * link, and enable Auto Enable LPI since there will\n\t\t\t * be no driver to enable LPI while in Sx.\n\t\t\t */\n\t\t\tif ((eee_advert & I82579_EEE_100_SUPPORTED) &&\n\t\t\t (dev_spec->eee_lp_ability &\n\t\t\t I82579_EEE_100_SUPPORTED) &&\n\t\t\t (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {\n\t\t\t\tphy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |\n\t\t\t\t\t E1000_PHY_CTRL_NOND0A_LPLU);\n\n\t\t\t\t/* Set Auto Enable LPI after link up */\n\t\t\t\thw->phy.ops.read_reg_locked(hw,\n\t\t\t\t\t\t\t I217_LPI_GPIO_CTRL,\n\t\t\t\t\t\t\t &phy_reg);\n\t\t\t\tphy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;\n\t\t\t\thw->phy.ops.write_reg_locked(hw,\n\t\t\t\t\t\t\t I217_LPI_GPIO_CTRL,\n\t\t\t\t\t\t\t phy_reg);\n\t\t\t}\n\t\t}\n\n\t\t/* For i217 Intel Rapid Start Technology support,\n\t\t * when the system is going into Sx and no manageability engine\n\t\t * is present, the driver must configure proxy to reset only on\n\t\t * power good. LPI (Low Power Idle) state must also reset only\n\t\t * on power good, as well as the MTA (Multicast table array).\n\t\t * The SMBus release must also be disabled on LCD reset.\n\t\t */\n\t\tif (!(E1000_READ_REG(hw, E1000_FWSM) &\n\t\t E1000_ICH_FWSM_FW_VALID)) {\n\t\t\t/* Enable proxy to reset only on power good. */\n\t\t\thw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,\n\t\t\t\t\t\t &phy_reg);\n\t\t\tphy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;\n\t\t\thw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL,\n\t\t\t\t\t\t phy_reg);\n\n\t\t\t/* Set bit enable LPI (EEE) to reset only on\n\t\t\t * power good.\n\t\t\t*/\n\t\t\thw->phy.ops.read_reg_locked(hw, I217_SxCTRL, &phy_reg);\n\t\t\tphy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;\n\t\t\thw->phy.ops.write_reg_locked(hw, I217_SxCTRL, phy_reg);\n\n\t\t\t/* Disable the SMB release on LCD reset. */\n\t\t\thw->phy.ops.read_reg_locked(hw, I217_MEMPWR, &phy_reg);\n\t\t\tphy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;\n\t\t\thw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);\n\t\t}\n\n\t\t/* Enable MTA to reset for Intel Rapid Start Technology\n\t\t * Support\n\t\t */\n\t\thw->phy.ops.read_reg_locked(hw, I217_CGFREG, &phy_reg);\n\t\tphy_reg |= I217_CGFREG_ENABLE_MTA_RESET;\n\t\thw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);\n\nrelease:\n\t\thw->phy.ops.release(hw);\n\t}\nout:\n\tE1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);\n\n\tif (hw->mac.type == e1000_ich8lan)\n\t\te1000_gig_downshift_workaround_ich8lan(hw);\n\n\tif (hw->mac.type >= e1000_pchlan) {\n\t\te1000_oem_bits_config_ich8lan(hw, false);\n\n\t\t/* Reset PHY to activate OEM bits on 82577/8 */\n\t\tif (hw->mac.type == e1000_pchlan)\n\t\t\te1000_phy_hw_reset_generic(hw);\n\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn;\n\t\te1000_write_smbus_addr(hw);\n\t\thw->phy.ops.release(hw);\n\t}\n\n\treturn;\n}\n\n/**\n * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0\n * @hw: pointer to the HW structure\n *\n * During Sx to S0 transitions on non-managed devices or managed devices\n * on which PHY resets are not blocked, if the PHY registers cannot be\n * accessed properly by the s/w toggle the LANPHYPC value to power cycle\n * the PHY.\n * On i217, setup Intel Rapid Start Technology.\n **/\nvoid e1000_resume_workarounds_pchlan(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_resume_workarounds_pchlan\");\n\n\tif (hw->mac.type < e1000_pch2lan)\n\t\treturn;\n\n\tret_val = e1000_init_phy_workarounds_pchlan(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT1(\"Failed to init PHY flow ret_val=%d\\n\", ret_val);\n\t\treturn;\n\t}\n\n\t/* For i217 Intel Rapid Start Technology support when the system\n\t * is transitioning from Sx and no manageability engine is present\n\t * configure SMBus to restore on reset, disable proxy, and enable\n\t * the reset on MTA (Multicast table array).\n\t */\n\tif (hw->phy.type == e1000_phy_i217) {\n\t\tu16 phy_reg;\n\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Failed to setup iRST\\n\");\n\t\t\treturn;\n\t\t}\n\n\t\t/* Clear Auto Enable LPI after link up */\n\t\thw->phy.ops.read_reg_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);\n\t\tphy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;\n\t\thw->phy.ops.write_reg_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);\n\n\t\tif (!(E1000_READ_REG(hw, E1000_FWSM) &\n\t\t E1000_ICH_FWSM_FW_VALID)) {\n\t\t\t/* Restore clear on SMB if no manageability engine\n\t\t\t * is present\n\t\t\t */\n\t\t\tret_val = hw->phy.ops.read_reg_locked(hw, I217_MEMPWR,\n\t\t\t\t\t\t\t &phy_reg);\n\t\t\tif (ret_val)\n\t\t\t\tgoto release;\n\t\t\tphy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;\n\t\t\thw->phy.ops.write_reg_locked(hw, I217_MEMPWR, phy_reg);\n\n\t\t\t/* Disable Proxy */\n\t\t\thw->phy.ops.write_reg_locked(hw, I217_PROXY_CTRL, 0);\n\t\t}\n\t\t/* Enable reset on MTA */\n\t\tret_val = hw->phy.ops.read_reg_locked(hw, I217_CGFREG,\n\t\t\t\t\t\t &phy_reg);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t\tphy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;\n\t\thw->phy.ops.write_reg_locked(hw, I217_CGFREG, phy_reg);\nrelease:\n\t\tif (ret_val)\n\t\t\tDEBUGOUT1(\"Error %d in resume workarounds\\n\", ret_val);\n\t\thw->phy.ops.release(hw);\n\t}\n}\n\n/**\n * e1000_cleanup_led_ich8lan - Restore the default LED operation\n * @hw: pointer to the HW structure\n *\n * Return the LED back to the default configuration.\n **/\nSTATIC s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_cleanup_led_ich8lan\");\n\n\tif (hw->phy.type == e1000_phy_ife)\n\t\treturn hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,\n\t\t\t\t\t 0);\n\n\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_led_on_ich8lan - Turn LEDs on\n * @hw: pointer to the HW structure\n *\n * Turn on the LEDs.\n **/\nSTATIC s32 e1000_led_on_ich8lan(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_led_on_ich8lan\");\n\n\tif (hw->phy.type == e1000_phy_ife)\n\t\treturn hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,\n\t\t\t\t(IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));\n\n\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_led_off_ich8lan - Turn LEDs off\n * @hw: pointer to the HW structure\n *\n * Turn off the LEDs.\n **/\nSTATIC s32 e1000_led_off_ich8lan(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_led_off_ich8lan\");\n\n\tif (hw->phy.type == e1000_phy_ife)\n\t\treturn hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,\n\t\t\t (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));\n\n\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_setup_led_pchlan - Configures SW controllable LED\n * @hw: pointer to the HW structure\n *\n * This prepares the SW controllable LED for use.\n **/\nSTATIC s32 e1000_setup_led_pchlan(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_setup_led_pchlan\");\n\n\treturn hw->phy.ops.write_reg(hw, HV_LED_CONFIG,\n\t\t\t\t (u16)hw->mac.ledctl_mode1);\n}\n\n/**\n * e1000_cleanup_led_pchlan - Restore the default LED operation\n * @hw: pointer to the HW structure\n *\n * Return the LED back to the default configuration.\n **/\nSTATIC s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_cleanup_led_pchlan\");\n\n\treturn hw->phy.ops.write_reg(hw, HV_LED_CONFIG,\n\t\t\t\t (u16)hw->mac.ledctl_default);\n}\n\n/**\n * e1000_led_on_pchlan - Turn LEDs on\n * @hw: pointer to the HW structure\n *\n * Turn on the LEDs.\n **/\nSTATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw)\n{\n\tu16 data = (u16)hw->mac.ledctl_mode2;\n\tu32 i, led;\n\n\tDEBUGFUNC(\"e1000_led_on_pchlan\");\n\n\t/* If no link, then turn LED on by setting the invert bit\n\t * for each LED that's mode is \"link_up\" in ledctl_mode2.\n\t */\n\tif (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {\n\t\tfor (i = 0; i < 3; i++) {\n\t\t\tled = (data >> (i * 5)) & E1000_PHY_LED0_MASK;\n\t\t\tif ((led & E1000_PHY_LED0_MODE_MASK) !=\n\t\t\t E1000_LEDCTL_MODE_LINK_UP)\n\t\t\t\tcontinue;\n\t\t\tif (led & E1000_PHY_LED0_IVRT)\n\t\t\t\tdata &= ~(E1000_PHY_LED0_IVRT << (i * 5));\n\t\t\telse\n\t\t\t\tdata |= (E1000_PHY_LED0_IVRT << (i * 5));\n\t\t}\n\t}\n\n\treturn hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);\n}\n\n/**\n * e1000_led_off_pchlan - Turn LEDs off\n * @hw: pointer to the HW structure\n *\n * Turn off the LEDs.\n **/\nSTATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw)\n{\n\tu16 data = (u16)hw->mac.ledctl_mode1;\n\tu32 i, led;\n\n\tDEBUGFUNC(\"e1000_led_off_pchlan\");\n\n\t/* If no link, then turn LED off by clearing the invert bit\n\t * for each LED that's mode is \"link_up\" in ledctl_mode1.\n\t */\n\tif (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {\n\t\tfor (i = 0; i < 3; i++) {\n\t\t\tled = (data >> (i * 5)) & E1000_PHY_LED0_MASK;\n\t\t\tif ((led & E1000_PHY_LED0_MODE_MASK) !=\n\t\t\t E1000_LEDCTL_MODE_LINK_UP)\n\t\t\t\tcontinue;\n\t\t\tif (led & E1000_PHY_LED0_IVRT)\n\t\t\t\tdata &= ~(E1000_PHY_LED0_IVRT << (i * 5));\n\t\t\telse\n\t\t\t\tdata |= (E1000_PHY_LED0_IVRT << (i * 5));\n\t\t}\n\t}\n\n\treturn hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);\n}\n\n/**\n * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset\n * @hw: pointer to the HW structure\n *\n * Read appropriate register for the config done bit for completion status\n * and configure the PHY through s/w for EEPROM-less parts.\n *\n * NOTE: some silicon which is EEPROM-less will fail trying to read the\n * config done bit, so only an error is logged and continues. If we were\n * to return with error, EEPROM-less silicon would not be able to be reset\n * or change link.\n **/\nSTATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 bank = 0;\n\tu32 status;\n\n\tDEBUGFUNC(\"e1000_get_cfg_done_ich8lan\");\n\n\te1000_get_cfg_done_generic(hw);\n\n\t/* Wait for indication from h/w that it has completed basic config */\n\tif (hw->mac.type >= e1000_ich10lan) {\n\t\te1000_lan_init_done_ich8lan(hw);\n\t} else {\n\t\tret_val = e1000_get_auto_rd_done_generic(hw);\n\t\tif (ret_val) {\n\t\t\t/* When auto config read does not complete, do not\n\t\t\t * return with an error. This can happen in situations\n\t\t\t * where there is no eeprom and prevents getting link.\n\t\t\t */\n\t\t\tDEBUGOUT(\"Auto Read Done did not complete\\n\");\n\t\t\tret_val = E1000_SUCCESS;\n\t\t}\n\t}\n\n\t/* Clear PHY Reset Asserted bit */\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\tif (status & E1000_STATUS_PHYRA)\n\t\tE1000_WRITE_REG(hw, E1000_STATUS, status & ~E1000_STATUS_PHYRA);\n\telse\n\t\tDEBUGOUT(\"PHY Reset Asserted not set - needs delay\\n\");\n\n\t/* If EEPROM is not marked present, init the IGP 3 PHY manually */\n\tif (hw->mac.type <= e1000_ich9lan) {\n\t\tif (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&\n\t\t (hw->phy.type == e1000_phy_igp_3)) {\n\t\t\te1000_phy_init_script_igp3(hw);\n\t\t}\n\t} else {\n\t\tif (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {\n\t\t\t/* Maybe we should do a basic PHY config */\n\t\t\tDEBUGOUT(\"EEPROM not present\\n\");\n\t\t\tret_val = -E1000_ERR_CONFIG;\n\t\t}\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down\n * @hw: pointer to the HW structure\n *\n * In the case of a PHY power down to save power, or to turn off link during a\n * driver unload, or wake on lan is not enabled, remove the link.\n **/\nSTATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)\n{\n\t/* If the management interface is not enabled, then power down */\n\tif (!(hw->mac.ops.check_mng_mode(hw) ||\n\t hw->phy.ops.check_reset_block(hw)))\n\t\te1000_power_down_phy_copper(hw);\n\n\treturn;\n}\n\n/**\n * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters\n * @hw: pointer to the HW structure\n *\n * Clears hardware counters specific to the silicon family and calls\n * clear_hw_cntrs_generic to clear all general purpose counters.\n **/\nSTATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)\n{\n\tu16 phy_data;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_clear_hw_cntrs_ich8lan\");\n\n\te1000_clear_hw_cntrs_base_generic(hw);\n\n\tE1000_READ_REG(hw, E1000_ALGNERRC);\n\tE1000_READ_REG(hw, E1000_RXERRC);\n\tE1000_READ_REG(hw, E1000_TNCRS);\n\tE1000_READ_REG(hw, E1000_CEXTERR);\n\tE1000_READ_REG(hw, E1000_TSCTC);\n\tE1000_READ_REG(hw, E1000_TSCTFC);\n\n\tE1000_READ_REG(hw, E1000_MGTPRC);\n\tE1000_READ_REG(hw, E1000_MGTPDC);\n\tE1000_READ_REG(hw, E1000_MGTPTC);\n\n\tE1000_READ_REG(hw, E1000_IAC);\n\tE1000_READ_REG(hw, E1000_ICRXOC);\n\n\t/* Clear PHY statistics registers */\n\tif ((hw->phy.type == e1000_phy_82578) ||\n\t (hw->phy.type == e1000_phy_82579) ||\n\t (hw->phy.type == e1000_phy_i217) ||\n\t (hw->phy.type == e1000_phy_82577)) {\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn;\n\t\tret_val = hw->phy.ops.set_page(hw,\n\t\t\t\t\t HV_STATS_PAGE << IGP_PAGE_SHIFT);\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t\thw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);\n\t\thw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);\nrelease:\n\t\thw->phy.ops.release(hw);\n\t}\n}\n\n" }, { "path": "drivers/net/e1000/base/e1000_ich8lan.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_ICH8LAN_H_\n#define _E1000_ICH8LAN_H_\n\n#define ICH_FLASH_GFPREG\t\t0x0000\n#define ICH_FLASH_HSFSTS\t\t0x0004\n#define ICH_FLASH_HSFCTL\t\t0x0006\n#define ICH_FLASH_FADDR\t\t\t0x0008\n#define ICH_FLASH_FDATA0\t\t0x0010\n\n/* Requires up to 10 seconds when MNG might be accessing part. */\n#define ICH_FLASH_READ_COMMAND_TIMEOUT\t10000000\n#define ICH_FLASH_WRITE_COMMAND_TIMEOUT\t10000000\n#define ICH_FLASH_ERASE_COMMAND_TIMEOUT\t10000000\n#define ICH_FLASH_LINEAR_ADDR_MASK\t0x00FFFFFF\n#define ICH_FLASH_CYCLE_REPEAT_COUNT\t10\n\n#define ICH_CYCLE_READ\t\t\t0\n#define ICH_CYCLE_WRITE\t\t\t2\n#define ICH_CYCLE_ERASE\t\t\t3\n\n#define FLASH_GFPREG_BASE_MASK\t\t0x1FFF\n#define FLASH_SECTOR_ADDR_SHIFT\t\t12\n\n#define ICH_FLASH_SEG_SIZE_256\t\t256\n#define ICH_FLASH_SEG_SIZE_4K\t\t4096\n#define ICH_FLASH_SEG_SIZE_8K\t\t8192\n#define ICH_FLASH_SEG_SIZE_64K\t\t65536\n\n#define E1000_ICH_FWSM_RSPCIPHY\t0x00000040 /* Reset PHY on PCI Reset */\n/* FW established a valid mode */\n#define E1000_ICH_FWSM_FW_VALID\t0x00008000\n#define E1000_ICH_FWSM_PCIM2PCI\t0x01000000 /* ME PCIm-to-PCI active */\n#define E1000_ICH_FWSM_PCIM2PCI_COUNT\t2000\n\n#define E1000_ICH_MNG_IAMT_MODE\t\t0x2\n\n#define E1000_FWSM_WLOCK_MAC_MASK\t0x0380\n#define E1000_FWSM_WLOCK_MAC_SHIFT\t7\n#if !defined(EXTERNAL_RELEASE) || (defined(NAHUM6LP_HW) && defined(ULP_SUPPORT))\n#define E1000_FWSM_ULP_CFG_DONE\t\t0x00000400 /* Low power cfg done */\n#endif /* !EXTERNAL_RELEASE || (NAHUM6LP_HW && ULP_SUPPORT) */\n\n/* Shared Receive Address Registers */\n#define E1000_SHRAL_PCH_LPT(_i)\t\t(0x05408 + ((_i) * 8))\n#define E1000_SHRAH_PCH_LPT(_i)\t\t(0x0540C + ((_i) * 8))\n\n#if !defined(EXTERNAL_RELEASE) || (defined(NAHUM6LP_HW) && defined(ULP_SUPPORT))\n#define E1000_H2ME\t\t0x05B50 /* Host to ME */\n#endif /* !EXTERNAL_RELEASE || (NAHUM6LP_HW && ULP_SUPPORT) */\n#if !defined(EXTERNAL_RELEASE) || (defined(NAHUM6LP_HW) && defined(ULP_SUPPORT))\n#define E1000_H2ME_ULP\t\t0x00000800 /* ULP Indication Bit */\n#define E1000_H2ME_ENFORCE_SETTINGS\t0x00001000 /* Enforce Settings */\n\n#endif /* !EXTERNAL_RELEASE || (NAHUM6LP_HW && ULP_SUPPORT) */\n#define ID_LED_DEFAULT_ICH8LAN\t((ID_LED_DEF1_DEF2 << 12) | \\\n\t\t\t\t (ID_LED_OFF1_OFF2 << 8) | \\\n\t\t\t\t (ID_LED_OFF1_ON2 << 4) | \\\n\t\t\t\t (ID_LED_DEF1_DEF2))\n\n#define E1000_ICH_NVM_SIG_WORD\t\t0x13\n#define E1000_ICH_NVM_SIG_MASK\t\t0xC000\n#define E1000_ICH_NVM_VALID_SIG_MASK\t0xC0\n#define E1000_ICH_NVM_SIG_VALUE\t\t0x80\n\n#define E1000_ICH8_LAN_INIT_TIMEOUT\t1500\n\n#if !defined(EXTERNAL_RELEASE) || (defined(NAHUM6LP_HW) && defined(ULP_SUPPORT))\n/* FEXT register bit definition */\n#define E1000_FEXT_PHY_CABLE_DISCONNECTED\t0x00000004\n\n#endif /* !EXTERNAL_RELEASE || (NAHUM6LP_HW && ULP_SUPPORT) */\n#define E1000_FEXTNVM_SW_CONFIG\t\t1\n#define E1000_FEXTNVM_SW_CONFIG_ICH8M\t(1 << 27) /* different on ICH8M */\n\n#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK\t0x0C000000\n#define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC\t0x08000000\n\n#define E1000_FEXTNVM4_BEACON_DURATION_MASK\t0x7\n#define E1000_FEXTNVM4_BEACON_DURATION_8USEC\t0x7\n#define E1000_FEXTNVM4_BEACON_DURATION_16USEC\t0x3\n\n#define E1000_FEXTNVM6_REQ_PLL_CLK\t0x00000100\n#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION\t0x00000200\n\n#if !defined(EXTERNAL_RELEASE) || (defined(NAHUM6LP_HW) && defined(ULP_SUPPORT))\n#define E1000_FEXTNVM7_DISABLE_SMB_PERST\t0x00000020\n\n#endif /* !EXTERNAL_RELEASE || (NAHUM6LP_HW && ULP_SUPPORT) */\n#define PCIE_ICH8_SNOOP_ALL\tPCIE_NO_SNOOP_ALL\n\n#define E1000_ICH_RAR_ENTRIES\t7\n#define E1000_PCH2_RAR_ENTRIES\t5 /* RAR[0], SHRA[0-3] */\n#define E1000_PCH_LPT_RAR_ENTRIES\t12 /* RAR[0], SHRA[0-10] */\n\n#define PHY_PAGE_SHIFT\t\t5\n#define PHY_REG(page, reg)\t(((page) << PHY_PAGE_SHIFT) | \\\n\t\t\t\t ((reg) & MAX_PHY_REG_ADDRESS))\n#define IGP3_KMRN_DIAG\tPHY_REG(770, 19) /* KMRN Diagnostic */\n#define IGP3_VR_CTRL\tPHY_REG(776, 18) /* Voltage Regulator Control */\n\n#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS\t\t0x0002\n#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK\t0x0300\n#define IGP3_VR_CTRL_MODE_SHUTDOWN\t\t0x0200\n\n/* PHY Wakeup Registers and defines */\n#define BM_PORT_GEN_CFG\t\tPHY_REG(BM_PORT_CTRL_PAGE, 17)\n#define BM_RCTL\t\t\tPHY_REG(BM_WUC_PAGE, 0)\n#define BM_WUC\t\t\tPHY_REG(BM_WUC_PAGE, 1)\n#define BM_WUFC\t\t\tPHY_REG(BM_WUC_PAGE, 2)\n#define BM_WUS\t\t\tPHY_REG(BM_WUC_PAGE, 3)\n#define BM_RAR_L(_i)\t\t(BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))\n#define BM_RAR_M(_i)\t\t(BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))\n#define BM_RAR_H(_i)\t\t(BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))\n#define BM_RAR_CTRL(_i)\t\t(BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))\n#define BM_MTA(_i)\t\t(BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))\n\n#define BM_RCTL_UPE\t\t0x0001 /* Unicast Promiscuous Mode */\n#define BM_RCTL_MPE\t\t0x0002 /* Multicast Promiscuous Mode */\n#define BM_RCTL_MO_SHIFT\t3 /* Multicast Offset Shift */\n#define BM_RCTL_MO_MASK\t\t(3 << 3) /* Multicast Offset Mask */\n#define BM_RCTL_BAM\t\t0x0020 /* Broadcast Accept Mode */\n#define BM_RCTL_PMCF\t\t0x0040 /* Pass MAC Control Frames */\n#define BM_RCTL_RFCE\t\t0x0080 /* Rx Flow Control Enable */\n\n#define HV_LED_CONFIG\t\tPHY_REG(768, 30) /* LED Configuration */\n#define HV_MUX_DATA_CTRL\tPHY_REG(776, 16)\n#define HV_MUX_DATA_CTRL_GEN_TO_MAC\t0x0400\n#define HV_MUX_DATA_CTRL_FORCE_SPEED\t0x0004\n#define HV_STATS_PAGE\t778\n/* Half-duplex collision counts */\n#define HV_SCC_UPPER\tPHY_REG(HV_STATS_PAGE, 16) /* Single Collision */\n#define HV_SCC_LOWER\tPHY_REG(HV_STATS_PAGE, 17)\n#define HV_ECOL_UPPER\tPHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */\n#define HV_ECOL_LOWER\tPHY_REG(HV_STATS_PAGE, 19)\n#define HV_MCC_UPPER\tPHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */\n#define HV_MCC_LOWER\tPHY_REG(HV_STATS_PAGE, 21)\n#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */\n#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)\n#define HV_COLC_UPPER\tPHY_REG(HV_STATS_PAGE, 25) /* Collision */\n#define HV_COLC_LOWER\tPHY_REG(HV_STATS_PAGE, 26)\n#define HV_DC_UPPER\tPHY_REG(HV_STATS_PAGE, 27) /* Defer Count */\n#define HV_DC_LOWER\tPHY_REG(HV_STATS_PAGE, 28)\n#define HV_TNCRS_UPPER\tPHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */\n#define HV_TNCRS_LOWER\tPHY_REG(HV_STATS_PAGE, 30)\n\n#define E1000_FCRTV_PCH\t0x05F40 /* PCH Flow Control Refresh Timer Value */\n\n#define E1000_NVM_K1_CONFIG\t0x1B /* NVM K1 Config Word */\n#define E1000_NVM_K1_ENABLE\t0x1 /* NVM Enable K1 bit */\n\n/* SMBus Control Phy Register */\n#define CV_SMB_CTRL\t\tPHY_REG(769, 23)\n#define CV_SMB_CTRL_FORCE_SMBUS\t0x0001\n\n#if !defined(EXTERNAL_RELEASE) || (defined(NAHUM6LP_HW) && defined(ULP_SUPPORT))\n/* I218 Ultra Low Power Configuration 1 Register */\n#define I218_ULP_CONFIG1\t\tPHY_REG(779, 16)\n#define I218_ULP_CONFIG1_START\t\t0x0001 /* Start auto ULP config */\n#define I218_ULP_CONFIG1_IND\t\t0x0004 /* Pwr up from ULP indication */\n#define I218_ULP_CONFIG1_STICKY_ULP\t0x0010 /* Set sticky ULP mode */\n#define I218_ULP_CONFIG1_INBAND_EXIT\t0x0020 /* Inband on ULP exit */\n#define I218_ULP_CONFIG1_WOL_HOST\t0x0040 /* WoL Host on ULP exit */\n#define I218_ULP_CONFIG1_RESET_TO_SMBUS\t0x0100 /* Reset to SMBus mode */\n#define I218_ULP_CONFIG1_DISABLE_SMB_PERST\t0x1000 /* Disable on PERST# */\n\n#endif /* !EXTERNAL_RELEASE || (NAHUM6LP_HW && ULP_SUPPORT) */\n/* SMBus Address Phy Register */\n#define HV_SMB_ADDR\t\tPHY_REG(768, 26)\n#define HV_SMB_ADDR_MASK\t0x007F\n#define HV_SMB_ADDR_PEC_EN\t0x0200\n#define HV_SMB_ADDR_VALID\t0x0080\n#define HV_SMB_ADDR_FREQ_MASK\t\t0x1100\n#define HV_SMB_ADDR_FREQ_LOW_SHIFT\t8\n#define HV_SMB_ADDR_FREQ_HIGH_SHIFT\t12\n\n/* Strapping Option Register - RO */\n#define E1000_STRAP\t\t\t0x0000C\n#define E1000_STRAP_SMBUS_ADDRESS_MASK\t0x00FE0000\n#define E1000_STRAP_SMBUS_ADDRESS_SHIFT\t17\n#define E1000_STRAP_SMT_FREQ_MASK\t0x00003000\n#define E1000_STRAP_SMT_FREQ_SHIFT\t12\n\n/* OEM Bits Phy Register */\n#define HV_OEM_BITS\t\tPHY_REG(768, 25)\n#define HV_OEM_BITS_LPLU\t0x0004 /* Low Power Link Up */\n#define HV_OEM_BITS_GBE_DIS\t0x0040 /* Gigabit Disable */\n#define HV_OEM_BITS_RESTART_AN\t0x0400 /* Restart Auto-negotiation */\n\n/* KMRN Mode Control */\n#define HV_KMRN_MODE_CTRL\tPHY_REG(769, 16)\n#define HV_KMRN_MDIO_SLOW\t0x0400\n\n/* KMRN FIFO Control and Status */\n#define HV_KMRN_FIFO_CTRLSTA\t\t\tPHY_REG(770, 16)\n#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK\t0x7000\n#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT\t12\n\n/* PHY Power Management Control */\n#define HV_PM_CTRL\t\tPHY_REG(770, 17)\n#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA\t0x100\n#define HV_PM_CTRL_K1_ENABLE\t\t0x4000\n\n#define SW_FLAG_TIMEOUT\t\t1000 /* SW Semaphore flag timeout in ms */\n\n/* Inband Control */\n#define I217_INBAND_CTRL\t\t\t\tPHY_REG(770, 18)\n#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK\t0x3F00\n#define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT\t8\n\n/* Low Power Idle GPIO Control */\n#define I217_LPI_GPIO_CTRL\t\t\tPHY_REG(772, 18)\n#define I217_LPI_GPIO_CTRL_AUTO_EN_LPI\t\t0x0800\n\n/* PHY Low Power Idle Control */\n#define I82579_LPI_CTRL\t\t\t\tPHY_REG(772, 20)\n#define I82579_LPI_CTRL_100_ENABLE\t\t0x2000\n#define I82579_LPI_CTRL_1000_ENABLE\t\t0x4000\n#define I82579_LPI_CTRL_ENABLE_MASK\t\t0x6000\n\n/* 82579 DFT Control */\n#define I82579_DFT_CTRL\t\t\tPHY_REG(769, 20)\n#define I82579_DFT_CTRL_GATE_PHY_RESET\t0x0040 /* Gate PHY Reset on MAC Reset */\n\n/* Extended Management Interface (EMI) Registers */\n#define I82579_EMI_ADDR\t\t0x10\n#define I82579_EMI_DATA\t\t0x11\n#define I82579_LPI_UPDATE_TIMER\t0x4805 /* in 40ns units + 40 ns base value */\n#define I82579_MSE_THRESHOLD\t0x084F /* 82579 Mean Square Error Threshold */\n#define I82577_MSE_THRESHOLD\t0x0887 /* 82577 Mean Square Error Threshold */\n#define I82579_MSE_LINK_DOWN\t0x2411 /* MSE count before dropping link */\n#define I82579_RX_CONFIG\t\t0x3412 /* Receive configuration */\n#define I82579_EEE_PCS_STATUS\t\t0x182E\t/* IEEE MMD Register 3.1 >> 8 */\n#define I82579_EEE_CAPABILITY\t\t0x0410 /* IEEE MMD Register 3.20 */\n#define I82579_EEE_ADVERTISEMENT\t0x040E /* IEEE MMD Register 7.60 */\n#define I82579_EEE_LP_ABILITY\t\t0x040F /* IEEE MMD Register 7.61 */\n#define I82579_EEE_100_SUPPORTED\t(1 << 1) /* 100BaseTx EEE */\n#define I82579_EEE_1000_SUPPORTED\t(1 << 2) /* 1000BaseTx EEE */\n#define I217_EEE_PCS_STATUS\t0x9401 /* IEEE MMD Register 3.1 */\n#define I217_EEE_CAPABILITY\t0x8000 /* IEEE MMD Register 3.20 */\n#define I217_EEE_ADVERTISEMENT\t0x8001 /* IEEE MMD Register 7.60 */\n#define I217_EEE_LP_ABILITY\t0x8002 /* IEEE MMD Register 7.61 */\n#define I217_RX_CONFIG\t\t0xB20C /* Receive configuration */\n\n#define E1000_EEE_RX_LPI_RCVD\t0x0400\t/* Tx LP idle received */\n#define E1000_EEE_TX_LPI_RCVD\t0x0800\t/* Rx LP idle received */\n\n/* Intel Rapid Start Technology Support */\n#define I217_PROXY_CTRL\t\tBM_PHY_REG(BM_WUC_PAGE, 70)\n#define I217_PROXY_CTRL_AUTO_DISABLE\t0x0080\n#define I217_SxCTRL\t\t\tPHY_REG(BM_PORT_CTRL_PAGE, 28)\n#define I217_SxCTRL_ENABLE_LPI_RESET\t0x1000\n#define I217_CGFREG\t\t\tPHY_REG(772, 29)\n#define I217_CGFREG_ENABLE_MTA_RESET\t0x0002\n#define I217_MEMPWR\t\t\tPHY_REG(772, 26)\n#define I217_MEMPWR_DISABLE_SMB_RELEASE\t0x0010\n\n/* Receive Address Initial CRC Calculation */\n#define E1000_PCH_RAICC(_n)\t(0x05F50 + ((_n) * 4))\n\n#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)\n#define E1000_PCI_REVISION_ID_REG\t0x08\n#endif /* defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) */\nvoid e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,\n\t\t\t\t\t\t bool state);\nvoid e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);\nvoid e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);\nvoid e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);\nvoid e1000_resume_workarounds_pchlan(struct e1000_hw *hw);\ns32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);\nvoid e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);\ns32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);\ns32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);\ns32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data);\ns32 e1000_set_eee_pchlan(struct e1000_hw *hw);\n#if defined(NAHUM6LP_HW) && defined(ULP_SUPPORT)\ns32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx);\ns32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);\n#endif /* NAHUM6LP_HW && ULP_SUPPORT */\n#endif /* _E1000_ICH8LAN_H_ */\nvoid e1000_demote_ltr(struct e1000_hw *hw, bool demote, bool link);\n" }, { "path": "drivers/net/e1000/base/e1000_mac.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"e1000_api.h\"\n\nSTATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);\nSTATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);\nSTATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw);\nSTATIC void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);\n\n/**\n * e1000_init_mac_ops_generic - Initialize MAC function pointers\n * @hw: pointer to the HW structure\n *\n * Setups up the function pointers to no-op functions\n **/\nvoid e1000_init_mac_ops_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tDEBUGFUNC(\"e1000_init_mac_ops_generic\");\n\n\t/* General Setup */\n\tmac->ops.init_params = e1000_null_ops_generic;\n\tmac->ops.init_hw = e1000_null_ops_generic;\n\tmac->ops.reset_hw = e1000_null_ops_generic;\n\tmac->ops.setup_physical_interface = e1000_null_ops_generic;\n\tmac->ops.get_bus_info = e1000_null_ops_generic;\n\tmac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;\n\tmac->ops.read_mac_addr = e1000_read_mac_addr_generic;\n\tmac->ops.config_collision_dist = e1000_config_collision_dist_generic;\n\tmac->ops.clear_hw_cntrs = e1000_null_mac_generic;\n\t/* LED */\n\tmac->ops.cleanup_led = e1000_null_ops_generic;\n\tmac->ops.setup_led = e1000_null_ops_generic;\n\tmac->ops.blink_led = e1000_null_ops_generic;\n\tmac->ops.led_on = e1000_null_ops_generic;\n\tmac->ops.led_off = e1000_null_ops_generic;\n\t/* LINK */\n\tmac->ops.setup_link = e1000_null_ops_generic;\n\tmac->ops.get_link_up_info = e1000_null_link_info;\n\tmac->ops.check_for_link = e1000_null_ops_generic;\n\t/* Management */\n\tmac->ops.check_mng_mode = e1000_null_mng_mode;\n\t/* VLAN, MC, etc. */\n\tmac->ops.update_mc_addr_list = e1000_null_update_mc;\n\tmac->ops.clear_vfta = e1000_null_mac_generic;\n\tmac->ops.write_vfta = e1000_null_write_vfta;\n\tmac->ops.rar_set = e1000_rar_set_generic;\n\tmac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;\n}\n\n/**\n * e1000_null_ops_generic - No-op function, returns 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_null_ops_generic\");\n\tUNREFERENCED_1PARAMETER(hw);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_mac_generic - No-op function, return void\n * @hw: pointer to the HW structure\n **/\nvoid e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_null_mac_generic\");\n\tUNREFERENCED_1PARAMETER(hw);\n\treturn;\n}\n\n/**\n * e1000_null_link_info - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d)\n{\n\tDEBUGFUNC(\"e1000_null_link_info\");\n\tUNREFERENCED_3PARAMETER(hw, s, d);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_mng_mode - No-op function, return false\n * @hw: pointer to the HW structure\n **/\nbool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_null_mng_mode\");\n\tUNREFERENCED_1PARAMETER(hw);\n\treturn false;\n}\n\n/**\n * e1000_null_update_mc - No-op function, return void\n * @hw: pointer to the HW structure\n **/\nvoid e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)\n{\n\tDEBUGFUNC(\"e1000_null_update_mc\");\n\tUNREFERENCED_3PARAMETER(hw, h, a);\n\treturn;\n}\n\n/**\n * e1000_null_write_vfta - No-op function, return void\n * @hw: pointer to the HW structure\n **/\nvoid e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)\n{\n\tDEBUGFUNC(\"e1000_null_write_vfta\");\n\tUNREFERENCED_3PARAMETER(hw, a, b);\n\treturn;\n}\n\n/**\n * e1000_null_rar_set - No-op function, return void\n * @hw: pointer to the HW structure\n **/\nvoid e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\tu8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)\n{\n\tDEBUGFUNC(\"e1000_null_rar_set\");\n\tUNREFERENCED_3PARAMETER(hw, h, a);\n\treturn;\n}\n\n/**\n * e1000_get_bus_info_pci_generic - Get PCI(x) bus information\n * @hw: pointer to the HW structure\n *\n * Determines and stores the system bus information for a particular\n * network interface. The following bus information is determined and stored:\n * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.\n **/\ns32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tstruct e1000_bus_info *bus = &hw->bus;\n\tu32 status = E1000_READ_REG(hw, E1000_STATUS);\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_get_bus_info_pci_generic\");\n\n\t/* PCI or PCI-X? */\n\tbus->type = (status & E1000_STATUS_PCIX_MODE)\n\t\t\t? e1000_bus_type_pcix\n\t\t\t: e1000_bus_type_pci;\n\n\t/* Bus speed */\n\tif (bus->type == e1000_bus_type_pci) {\n\t\tbus->speed = (status & E1000_STATUS_PCI66)\n\t\t\t ? e1000_bus_speed_66\n\t\t\t : e1000_bus_speed_33;\n\t} else {\n\t\tswitch (status & E1000_STATUS_PCIX_SPEED) {\n\t\tcase E1000_STATUS_PCIX_SPEED_66:\n\t\t\tbus->speed = e1000_bus_speed_66;\n\t\t\tbreak;\n\t\tcase E1000_STATUS_PCIX_SPEED_100:\n\t\t\tbus->speed = e1000_bus_speed_100;\n\t\t\tbreak;\n\t\tcase E1000_STATUS_PCIX_SPEED_133:\n\t\t\tbus->speed = e1000_bus_speed_133;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbus->speed = e1000_bus_speed_reserved;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Bus width */\n\tbus->width = (status & E1000_STATUS_BUS64)\n\t\t ? e1000_bus_width_64\n\t\t : e1000_bus_width_32;\n\n\t/* Which PCI(-X) function? */\n\tmac->ops.set_lan_id(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_bus_info_pcie_generic - Get PCIe bus information\n * @hw: pointer to the HW structure\n *\n * Determines and stores the system bus information for a particular\n * network interface. The following bus information is determined and stored:\n * bus speed, bus width, type (PCIe), and PCIe function.\n **/\ns32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tstruct e1000_bus_info *bus = &hw->bus;\n\ts32 ret_val;\n\tu16 pcie_link_status;\n\n\tDEBUGFUNC(\"e1000_get_bus_info_pcie_generic\");\n\n\tbus->type = e1000_bus_type_pci_express;\n\n\tret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,\n\t\t\t\t\t &pcie_link_status);\n\tif (ret_val) {\n\t\tbus->width = e1000_bus_width_unknown;\n\t\tbus->speed = e1000_bus_speed_unknown;\n\t} else {\n\t\tswitch (pcie_link_status & PCIE_LINK_SPEED_MASK) {\n\t\tcase PCIE_LINK_SPEED_2500:\n\t\t\tbus->speed = e1000_bus_speed_2500;\n\t\t\tbreak;\n\t\tcase PCIE_LINK_SPEED_5000:\n\t\t\tbus->speed = e1000_bus_speed_5000;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbus->speed = e1000_bus_speed_unknown;\n\t\t\tbreak;\n\t\t}\n\n\t\tbus->width = (enum e1000_bus_width)((pcie_link_status &\n\t\t\t PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);\n\t}\n\n\tmac->ops.set_lan_id(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices\n *\n * @hw: pointer to the HW structure\n *\n * Determines the LAN function id by reading memory-mapped registers\n * and swaps the port value if requested.\n **/\nSTATIC void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)\n{\n\tstruct e1000_bus_info *bus = &hw->bus;\n\tu32 reg;\n\n\t/* The status register reports the correct function number\n\t * for the device regardless of function swap state.\n\t */\n\treg = E1000_READ_REG(hw, E1000_STATUS);\n\tbus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;\n}\n\n/**\n * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices\n * @hw: pointer to the HW structure\n *\n * Determines the LAN function id by reading PCI config space.\n **/\nvoid e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)\n{\n\tstruct e1000_bus_info *bus = &hw->bus;\n\tu16 pci_header_type;\n\tu32 status;\n\n\te1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);\n\tif (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {\n\t\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\t\tbus->func = (status & E1000_STATUS_FUNC_MASK)\n\t\t\t >> E1000_STATUS_FUNC_SHIFT;\n\t} else {\n\t\tbus->func = 0;\n\t}\n}\n\n/**\n * e1000_set_lan_id_single_port - Set LAN id for a single port device\n * @hw: pointer to the HW structure\n *\n * Sets the LAN function id to zero for a single port device.\n **/\nvoid e1000_set_lan_id_single_port(struct e1000_hw *hw)\n{\n\tstruct e1000_bus_info *bus = &hw->bus;\n\n\tbus->func = 0;\n}\n\n/**\n * e1000_clear_vfta_generic - Clear VLAN filter table\n * @hw: pointer to the HW structure\n *\n * Clears the register array which contains the VLAN filter table by\n * setting all the values to 0.\n **/\nvoid e1000_clear_vfta_generic(struct e1000_hw *hw)\n{\n\tu32 offset;\n\n\tDEBUGFUNC(\"e1000_clear_vfta_generic\");\n\n\tfor (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);\n\t\tE1000_WRITE_FLUSH(hw);\n\t}\n}\n\n/**\n * e1000_write_vfta_generic - Write value to VLAN filter table\n * @hw: pointer to the HW structure\n * @offset: register offset in VLAN filter table\n * @value: register value written to VLAN filter table\n *\n * Writes value at the given offset in the register array which stores\n * the VLAN filter table.\n **/\nvoid e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)\n{\n\tDEBUGFUNC(\"e1000_write_vfta_generic\");\n\n\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * e1000_init_rx_addrs_generic - Initialize receive address's\n * @hw: pointer to the HW structure\n * @rar_count: receive address registers\n *\n * Setup the receive address registers by setting the base receive address\n * register to the devices MAC address and clearing all the other receive\n * address registers to 0.\n **/\nvoid e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)\n{\n\tu32 i;\n\tu8 mac_addr[ETH_ADDR_LEN] = {0};\n\n\tDEBUGFUNC(\"e1000_init_rx_addrs_generic\");\n\n\t/* Setup the receive address */\n\tDEBUGOUT(\"Programming MAC Address into RAR[0]\\n\");\n\n\thw->mac.ops.rar_set(hw, hw->mac.addr, 0);\n\n\t/* Zero out the other (rar_entry_count - 1) receive addresses */\n\tDEBUGOUT1(\"Clearing RAR[1-%u]\\n\", rar_count-1);\n\tfor (i = 1; i < rar_count; i++)\n\t\thw->mac.ops.rar_set(hw, mac_addr, i);\n}\n\n/**\n * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr\n * @hw: pointer to the HW structure\n *\n * Checks the nvm for an alternate MAC address. An alternate MAC address\n * can be setup by pre-boot software and must be treated like a permanent\n * address and must override the actual permanent MAC address. If an\n * alternate MAC address is found it is programmed into RAR0, replacing\n * the permanent address that was installed into RAR0 by the Si on reset.\n * This function will return SUCCESS unless it encounters an error while\n * reading the EEPROM.\n **/\ns32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)\n{\n\tu32 i;\n\ts32 ret_val;\n\tu16 offset, nvm_alt_mac_addr_offset, nvm_data;\n\tu8 alt_mac_addr[ETH_ADDR_LEN];\n\n\tDEBUGFUNC(\"e1000_check_alt_mac_addr_generic\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* not supported on older hardware or 82573 */\n\tif ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))\n\t\treturn E1000_SUCCESS;\n\n\t/* Alternate MAC address is handled by the option ROM for 82580\n\t * and newer. SW support not required.\n\t */\n\tif (hw->mac.type >= e1000_82580)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,\n\t\t\t\t &nvm_alt_mac_addr_offset);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif ((nvm_alt_mac_addr_offset == 0xFFFF) ||\n\t (nvm_alt_mac_addr_offset == 0x0000))\n\t\t/* There is no Alternate MAC Address */\n\t\treturn E1000_SUCCESS;\n\n\tif (hw->bus.func == E1000_FUNC_1)\n\t\tnvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;\n\tif (hw->bus.func == E1000_FUNC_2)\n\t\tnvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;\n\n\tif (hw->bus.func == E1000_FUNC_3)\n\t\tnvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;\n\tfor (i = 0; i < ETH_ADDR_LEN; i += 2) {\n\t\toffset = nvm_alt_mac_addr_offset + (i >> 1);\n\t\tret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\n\t\talt_mac_addr[i] = (u8)(nvm_data & 0xFF);\n\t\talt_mac_addr[i + 1] = (u8)(nvm_data >> 8);\n\t}\n\n\t/* if multicast bit is set, the alternate address will not be used */\n\tif (alt_mac_addr[0] & 0x01) {\n\t\tDEBUGOUT(\"Ignoring Alternate Mac Address with MC bit set\\n\");\n\t\treturn E1000_SUCCESS;\n\t}\n\n\t/* We have a valid alternate MAC address, and we want to treat it the\n\t * same as the normal permanent MAC address stored by the HW into the\n\t * RAR. Do this by mapping this address into RAR0.\n\t */\n\thw->mac.ops.rar_set(hw, alt_mac_addr, 0);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_rar_set_generic - Set receive address register\n * @hw: pointer to the HW structure\n * @addr: pointer to the receive address\n * @index: receive address array register\n *\n * Sets the receive address array register at index to the address passed\n * in by addr.\n **/\nSTATIC void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)\n{\n\tu32 rar_low, rar_high;\n\n\tDEBUGFUNC(\"e1000_rar_set_generic\");\n\n\t/* HW expects these in little endian so we reverse the byte order\n\t * from network order (big endian) to little endian\n\t */\n\trar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |\n\t\t ((u32) addr[2] << 16) | ((u32) addr[3] << 24));\n\n\trar_high = ((u32) addr[4] | ((u32) addr[5] << 8));\n\n\t/* If MAC address zero, no need to set the AV bit */\n\tif (rar_low || rar_high)\n\t\trar_high |= E1000_RAH_AV;\n\n\t/* Some bridges will combine consecutive 32-bit writes into\n\t * a single burst write, which will malfunction on some parts.\n\t * The flushes avoid this.\n\t */\n\tE1000_WRITE_REG(hw, E1000_RAL(index), rar_low);\n\tE1000_WRITE_FLUSH(hw);\n\tE1000_WRITE_REG(hw, E1000_RAH(index), rar_high);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * e1000_hash_mc_addr_generic - Generate a multicast hash value\n * @hw: pointer to the HW structure\n * @mc_addr: pointer to a multicast address\n *\n * Generates a multicast address hash value which is used to determine\n * the multicast filter table array address and new table value.\n **/\nu32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)\n{\n\tu32 hash_value, hash_mask;\n\tu8 bit_shift = 0;\n\n\tDEBUGFUNC(\"e1000_hash_mc_addr_generic\");\n\n\t/* Register count multiplied by bits per register */\n\thash_mask = (hw->mac.mta_reg_count * 32) - 1;\n\n\t/* For a mc_filter_type of 0, bit_shift is the number of left-shifts\n\t * where 0xFF would still fall within the hash mask.\n\t */\n\twhile (hash_mask >> bit_shift != 0xFF)\n\t\tbit_shift++;\n\n\t/* The portion of the address that is used for the hash table\n\t * is determined by the mc_filter_type setting.\n\t * The algorithm is such that there is a total of 8 bits of shifting.\n\t * The bit_shift for a mc_filter_type of 0 represents the number of\n\t * left-shifts where the MSB of mc_addr[5] would still fall within\n\t * the hash_mask. Case 0 does this exactly. Since there are a total\n\t * of 8 bits of shifting, then mc_addr[4] will shift right the\n\t * remaining number of bits. Thus 8 - bit_shift. The rest of the\n\t * cases are a variation of this algorithm...essentially raising the\n\t * number of bits to shift mc_addr[5] left, while still keeping the\n\t * 8-bit shifting total.\n\t *\n\t * For example, given the following Destination MAC Address and an\n\t * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),\n\t * we can see that the bit_shift for case 0 is 4. These are the hash\n\t * values resulting from each mc_filter_type...\n\t * [0] [1] [2] [3] [4] [5]\n\t * 01 AA 00 12 34 56\n\t * LSB\t\t MSB\n\t *\n\t * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563\n\t * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6\n\t * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163\n\t * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634\n\t */\n\tswitch (hw->mac.mc_filter_type) {\n\tdefault:\n\tcase 0:\n\t\tbreak;\n\tcase 1:\n\t\tbit_shift += 1;\n\t\tbreak;\n\tcase 2:\n\t\tbit_shift += 2;\n\t\tbreak;\n\tcase 3:\n\t\tbit_shift += 4;\n\t\tbreak;\n\t}\n\n\thash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |\n\t\t\t\t (((u16) mc_addr[5]) << bit_shift)));\n\n\treturn hash_value;\n}\n\n/**\n * e1000_update_mc_addr_list_generic - Update Multicast addresses\n * @hw: pointer to the HW structure\n * @mc_addr_list: array of multicast addresses to program\n * @mc_addr_count: number of multicast addresses to program\n *\n * Updates entire Multicast Table Array.\n * The caller must have a packed mc_addr_list of multicast addresses.\n **/\nvoid e1000_update_mc_addr_list_generic(struct e1000_hw *hw,\n\t\t\t\t u8 *mc_addr_list, u32 mc_addr_count)\n{\n\tu32 hash_value, hash_bit, hash_reg;\n\tint i;\n\n\tDEBUGFUNC(\"e1000_update_mc_addr_list_generic\");\n\n\t/* clear mta_shadow */\n\tmemset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));\n\n\t/* update mta_shadow from mc_addr_list */\n\tfor (i = 0; (u32) i < mc_addr_count; i++) {\n\t\thash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);\n\n\t\thash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);\n\t\thash_bit = hash_value & 0x1F;\n\n\t\thw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);\n\t\tmc_addr_list += (ETH_ADDR_LEN);\n\t}\n\n\t/* replace the entire MTA table */\n\tfor (i = hw->mac.mta_reg_count - 1; i >= 0; i--)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value\n * @hw: pointer to the HW structure\n *\n * In certain situations, a system BIOS may report that the PCIx maximum\n * memory read byte count (MMRBC) value is higher than than the actual\n * value. We check the PCIx command register with the current PCIx status\n * register.\n **/\nvoid e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)\n{\n\tu16 cmd_mmrbc;\n\tu16 pcix_cmd;\n\tu16 pcix_stat_hi_word;\n\tu16 stat_mmrbc;\n\n\tDEBUGFUNC(\"e1000_pcix_mmrbc_workaround_generic\");\n\n\t/* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */\n\tif (hw->bus.type != e1000_bus_type_pcix)\n\t\treturn;\n\n\te1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);\n\te1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);\n\tcmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>\n\t\t PCIX_COMMAND_MMRBC_SHIFT;\n\tstat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>\n\t\t PCIX_STATUS_HI_MMRBC_SHIFT;\n\tif (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)\n\t\tstat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;\n\tif (cmd_mmrbc > stat_mmrbc) {\n\t\tpcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;\n\t\tpcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;\n\t\te1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);\n\t}\n}\n\n/**\n * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters\n * @hw: pointer to the HW structure\n *\n * Clears the base hardware counters by reading the counter registers.\n **/\nvoid e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_clear_hw_cntrs_base_generic\");\n\n\tE1000_READ_REG(hw, E1000_CRCERRS);\n\tE1000_READ_REG(hw, E1000_SYMERRS);\n\tE1000_READ_REG(hw, E1000_MPC);\n\tE1000_READ_REG(hw, E1000_SCC);\n\tE1000_READ_REG(hw, E1000_ECOL);\n\tE1000_READ_REG(hw, E1000_MCC);\n\tE1000_READ_REG(hw, E1000_LATECOL);\n\tE1000_READ_REG(hw, E1000_COLC);\n\tE1000_READ_REG(hw, E1000_DC);\n\tE1000_READ_REG(hw, E1000_SEC);\n\tE1000_READ_REG(hw, E1000_RLEC);\n\tE1000_READ_REG(hw, E1000_XONRXC);\n\tE1000_READ_REG(hw, E1000_XONTXC);\n\tE1000_READ_REG(hw, E1000_XOFFRXC);\n\tE1000_READ_REG(hw, E1000_XOFFTXC);\n\tE1000_READ_REG(hw, E1000_FCRUC);\n\tE1000_READ_REG(hw, E1000_GPRC);\n\tE1000_READ_REG(hw, E1000_BPRC);\n\tE1000_READ_REG(hw, E1000_MPRC);\n\tE1000_READ_REG(hw, E1000_GPTC);\n\tE1000_READ_REG(hw, E1000_GORCL);\n\tE1000_READ_REG(hw, E1000_GORCH);\n\tE1000_READ_REG(hw, E1000_GOTCL);\n\tE1000_READ_REG(hw, E1000_GOTCH);\n\tE1000_READ_REG(hw, E1000_RNBC);\n\tE1000_READ_REG(hw, E1000_RUC);\n\tE1000_READ_REG(hw, E1000_RFC);\n\tE1000_READ_REG(hw, E1000_ROC);\n\tE1000_READ_REG(hw, E1000_RJC);\n\tE1000_READ_REG(hw, E1000_TORL);\n\tE1000_READ_REG(hw, E1000_TORH);\n\tE1000_READ_REG(hw, E1000_TOTL);\n\tE1000_READ_REG(hw, E1000_TOTH);\n\tE1000_READ_REG(hw, E1000_TPR);\n\tE1000_READ_REG(hw, E1000_TPT);\n\tE1000_READ_REG(hw, E1000_MPTC);\n\tE1000_READ_REG(hw, E1000_BPTC);\n}\n\n/**\n * e1000_check_for_copper_link_generic - Check for link (Copper)\n * @hw: pointer to the HW structure\n *\n * Checks to see of the link status of the hardware has changed. If a\n * change in link status has been detected, then we read the PHY registers\n * to get the current speed/duplex if link exists.\n **/\ns32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_check_for_copper_link\");\n\n\t/* We only want to go out to the PHY registers to see if Auto-Neg\n\t * has completed and/or if our link status has changed. The\n\t * get_link_status flag is set upon receiving a Link Status\n\t * Change or Rx Sequence Error interrupt.\n\t */\n\tif (!mac->get_link_status)\n\t\treturn E1000_SUCCESS;\n\n\t/* First we want to see if the MII Status Register reports\n\t * link. If so, then we want to get the current speed/duplex\n\t * of the PHY.\n\t */\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!link)\n\t\treturn E1000_SUCCESS; /* No link detected */\n\n\tmac->get_link_status = false;\n\n\t/* Check if there was DownShift, must be checked\n\t * immediately after link-up\n\t */\n\te1000_check_downshift_generic(hw);\n\n\t/* If we are forcing speed/duplex, then we simply return since\n\t * we have already determined whether we have link or not.\n\t */\n\tif (!mac->autoneg)\n\t\treturn -E1000_ERR_CONFIG;\n\n\t/* Auto-Neg is enabled. Auto Speed Detection takes care\n\t * of MAC speed/duplex configuration. So we only need to\n\t * configure Collision Distance in the MAC.\n\t */\n\tmac->ops.config_collision_dist(hw);\n\n\t/* Configure Flow Control now that Auto-Neg has completed.\n\t * First, we need to restore the desired flow control\n\t * settings because we may have had to re-autoneg with a\n\t * different link partner.\n\t */\n\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_fiber_link_generic - Check for link (Fiber)\n * @hw: pointer to the HW structure\n *\n * Checks for link up on the hardware. If link is not up and we have\n * a signal, then we need to force link up.\n **/\ns32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 rxcw;\n\tu32 ctrl;\n\tu32 status;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_check_for_fiber_link_generic\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\trxcw = E1000_READ_REG(hw, E1000_RXCW);\n\n\t/* If we don't have link (auto-negotiation failed or link partner\n\t * cannot auto-negotiate), the cable is plugged in (we have signal),\n\t * and our link partner is not trying to auto-negotiate with us (we\n\t * are receiving idles or data), we need to force link up. We also\n\t * need to give auto-negotiation time to complete, in case the cable\n\t * was just plugged in. The autoneg_failed flag does this.\n\t */\n\t/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */\n\tif ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&\n\t !(rxcw & E1000_RXCW_C)) {\n\t\tif (!mac->autoneg_failed) {\n\t\t\tmac->autoneg_failed = true;\n\t\t\treturn E1000_SUCCESS;\n\t\t}\n\t\tDEBUGOUT(\"NOT Rx'ing /C/, disable AutoNeg and force link.\\n\");\n\n\t\t/* Disable auto-negotiation in the TXCW register */\n\t\tE1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));\n\n\t\t/* Force link-up and also force full-duplex. */\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\t\t/* Configure Flow Control after forcing link up. */\n\t\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {\n\t\t/* If we are forcing link and we are receiving /C/ ordered\n\t\t * sets, re-enable auto-negotiation in the TXCW register\n\t\t * and disable forced link in the Device Control register\n\t\t * in an attempt to auto-negotiate with our link partner.\n\t\t */\n\t\tDEBUGOUT(\"Rx'ing /C/, enable AutoNeg and stop forcing link.\\n\");\n\t\tE1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));\n\n\t\tmac->serdes_has_link = true;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_check_for_serdes_link_generic - Check for link (Serdes)\n * @hw: pointer to the HW structure\n *\n * Checks for link up on the hardware. If link is not up and we have\n * a signal, then we need to force link up.\n **/\ns32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 rxcw;\n\tu32 ctrl;\n\tu32 status;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_check_for_serdes_link_generic\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\trxcw = E1000_READ_REG(hw, E1000_RXCW);\n\n\t/* If we don't have link (auto-negotiation failed or link partner\n\t * cannot auto-negotiate), and our link partner is not trying to\n\t * auto-negotiate with us (we are receiving idles or data),\n\t * we need to force link up. We also need to give auto-negotiation\n\t * time to complete.\n\t */\n\t/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */\n\tif (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {\n\t\tif (!mac->autoneg_failed) {\n\t\t\tmac->autoneg_failed = true;\n\t\t\treturn E1000_SUCCESS;\n\t\t}\n\t\tDEBUGOUT(\"NOT Rx'ing /C/, disable AutoNeg and force link.\\n\");\n\n\t\t/* Disable auto-negotiation in the TXCW register */\n\t\tE1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));\n\n\t\t/* Force link-up and also force full-duplex. */\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\t\t/* Configure Flow Control after forcing link up. */\n\t\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {\n\t\t/* If we are forcing link and we are receiving /C/ ordered\n\t\t * sets, re-enable auto-negotiation in the TXCW register\n\t\t * and disable forced link in the Device Control register\n\t\t * in an attempt to auto-negotiate with our link partner.\n\t\t */\n\t\tDEBUGOUT(\"Rx'ing /C/, enable AutoNeg and stop forcing link.\\n\");\n\t\tE1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));\n\n\t\tmac->serdes_has_link = true;\n\t} else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {\n\t\t/* If we force link for non-auto-negotiation switch, check\n\t\t * link status based on MAC synchronization for internal\n\t\t * serdes media type.\n\t\t */\n\t\t/* SYNCH bit and IV bit are sticky. */\n\t\tusec_delay(10);\n\t\trxcw = E1000_READ_REG(hw, E1000_RXCW);\n\t\tif (rxcw & E1000_RXCW_SYNCH) {\n\t\t\tif (!(rxcw & E1000_RXCW_IV)) {\n\t\t\t\tmac->serdes_has_link = true;\n\t\t\t\tDEBUGOUT(\"SERDES: Link up - forced.\\n\");\n\t\t\t}\n\t\t} else {\n\t\t\tmac->serdes_has_link = false;\n\t\t\tDEBUGOUT(\"SERDES: Link down - force failed.\\n\");\n\t\t}\n\t}\n\n\tif (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {\n\t\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\t\tif (status & E1000_STATUS_LU) {\n\t\t\t/* SYNCH bit and IV bit are sticky, so reread rxcw. */\n\t\t\tusec_delay(10);\n\t\t\trxcw = E1000_READ_REG(hw, E1000_RXCW);\n\t\t\tif (rxcw & E1000_RXCW_SYNCH) {\n\t\t\t\tif (!(rxcw & E1000_RXCW_IV)) {\n\t\t\t\t\tmac->serdes_has_link = true;\n\t\t\t\t\tDEBUGOUT(\"SERDES: Link up - autoneg completed successfully.\\n\");\n\t\t\t\t} else {\n\t\t\t\t\tmac->serdes_has_link = false;\n\t\t\t\t\tDEBUGOUT(\"SERDES: Link down - invalid codewords detected in autoneg.\\n\");\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tmac->serdes_has_link = false;\n\t\t\t\tDEBUGOUT(\"SERDES: Link down - no sync.\\n\");\n\t\t\t}\n\t\t} else {\n\t\t\tmac->serdes_has_link = false;\n\t\t\tDEBUGOUT(\"SERDES: Link down - autoneg failed\\n\");\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_default_fc_generic - Set flow control default values\n * @hw: pointer to the HW structure\n *\n * Read the EEPROM for the default values for flow control and store the\n * values.\n **/\ns32 e1000_set_default_fc_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 nvm_data;\n\tu16 nvm_offset = 0;\n\n\tDEBUGFUNC(\"e1000_set_default_fc_generic\");\n\n\t/* Read and store word 0x0F of the EEPROM. This word contains bits\n\t * that determine the hardware's default PAUSE (flow control) mode,\n\t * a bit that determines whether the HW defaults to enabling or\n\t * disabling auto-negotiation, and the direction of the\n\t * SW defined pins. If there is no SW over-ride of the flow\n\t * control setting, then the variable hw->fc will\n\t * be initialized based on a value in the EEPROM.\n\t */\n\tif (hw->mac.type == e1000_i350) {\n\t\tnvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);\n\t\tret_val = hw->nvm.ops.read(hw,\n\t\t\t\t\t NVM_INIT_CONTROL2_REG +\n\t\t\t\t\t nvm_offset,\n\t\t\t\t\t 1, &nvm_data);\n\t} else {\n\t\tret_val = hw->nvm.ops.read(hw,\n\t\t\t\t\t NVM_INIT_CONTROL2_REG,\n\t\t\t\t\t 1, &nvm_data);\n\t}\n\n\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif (!(nvm_data & NVM_WORD0F_PAUSE_MASK))\n\t\thw->fc.requested_mode = e1000_fc_none;\n\telse if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==\n\t\t NVM_WORD0F_ASM_DIR)\n\t\thw->fc.requested_mode = e1000_fc_tx_pause;\n\telse\n\t\thw->fc.requested_mode = e1000_fc_full;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_setup_link_generic - Setup flow control and link settings\n * @hw: pointer to the HW structure\n *\n * Determines which flow control settings to use, then configures flow\n * control. Calls the appropriate media-specific link configuration\n * function. Assuming the adapter has a valid link partner, a valid link\n * should be established. Assumes the hardware has previously been reset\n * and the transmitter and receiver are not enabled.\n **/\ns32 e1000_setup_link_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_setup_link_generic\");\n\n\t/* In the case of the phy reset being blocked, we already have a link.\n\t * We do not need to set it up again.\n\t */\n\tif (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))\n\t\treturn E1000_SUCCESS;\n\n\t/* If requested flow control is set to default, set flow control\n\t * based on the EEPROM flow control settings.\n\t */\n\tif (hw->fc.requested_mode == e1000_fc_default) {\n\t\tret_val = e1000_set_default_fc_generic(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* Save off the requested flow control mode for use later. Depending\n\t * on the link partner's capabilities, we may or may not use this mode.\n\t */\n\thw->fc.current_mode = hw->fc.requested_mode;\n\n\tDEBUGOUT1(\"After fix-ups FlowControl is now = %x\\n\",\n\t\thw->fc.current_mode);\n\n\t/* Call the necessary media_type subroutine to configure the link. */\n\tret_val = hw->mac.ops.setup_physical_interface(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Initialize the flow control address, type, and PAUSE timer\n\t * registers to their default values. This is done even if flow\n\t * control is disabled, because it does not hurt anything to\n\t * initialize these registers.\n\t */\n\tDEBUGOUT(\"Initializing the Flow Control address, type and timer regs\\n\");\n\tE1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);\n\tE1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);\n\tE1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);\n\n\tE1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);\n\n\treturn e1000_set_fc_watermarks_generic(hw);\n}\n\n/**\n * e1000_commit_fc_settings_generic - Configure flow control\n * @hw: pointer to the HW structure\n *\n * Write the flow control settings to the Transmit Config Word Register (TXCW)\n * base on the flow control settings in e1000_mac_info.\n **/\ns32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 txcw;\n\n\tDEBUGFUNC(\"e1000_commit_fc_settings_generic\");\n\n\t/* Check for a software override of the flow control settings, and\n\t * setup the device accordingly. If auto-negotiation is enabled, then\n\t * software will have to set the \"PAUSE\" bits to the correct value in\n\t * the Transmit Config Word Register (TXCW) and re-start auto-\n\t * negotiation. However, if auto-negotiation is disabled, then\n\t * software will have to manually configure the two flow control enable\n\t * bits in the CTRL register.\n\t *\n\t * The possible values of the \"fc\" parameter are:\n\t * 0: Flow control is completely disabled\n\t * 1: Rx flow control is enabled (we can receive pause frames,\n\t * but not send pause frames).\n\t * 2: Tx flow control is enabled (we can send pause frames but we\n\t * do not support receiving pause frames).\n\t * 3: Both Rx and Tx flow control (symmetric) are enabled.\n\t */\n\tswitch (hw->fc.current_mode) {\n\tcase e1000_fc_none:\n\t\t/* Flow control completely disabled by a software over-ride. */\n\t\ttxcw = (E1000_TXCW_ANE | E1000_TXCW_FD);\n\t\tbreak;\n\tcase e1000_fc_rx_pause:\n\t\t/* Rx Flow control is enabled and Tx Flow control is disabled\n\t\t * by a software over-ride. Since there really isn't a way to\n\t\t * advertise that we are capable of Rx Pause ONLY, we will\n\t\t * advertise that we support both symmetric and asymmetric Rx\n\t\t * PAUSE. Later, we will disable the adapter's ability to send\n\t\t * PAUSE frames.\n\t\t */\n\t\ttxcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);\n\t\tbreak;\n\tcase e1000_fc_tx_pause:\n\t\t/* Tx Flow control is enabled, and Rx Flow control is disabled,\n\t\t * by a software over-ride.\n\t\t */\n\t\ttxcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);\n\t\tbreak;\n\tcase e1000_fc_full:\n\t\t/* Flow control (both Rx and Tx) is enabled by a software\n\t\t * over-ride.\n\t\t */\n\t\ttxcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\"Flow control param set incorrectly\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t\tbreak;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_TXCW, txcw);\n\tmac->txcw = txcw;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_poll_fiber_serdes_link_generic - Poll for link up\n * @hw: pointer to the HW structure\n *\n * Polls for link up by reading the status register, if link fails to come\n * up with auto-negotiation, then the link is forced if a signal is detected.\n **/\ns32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 i, status;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_poll_fiber_serdes_link_generic\");\n\n\t/* If we have a signal (the cable is plugged in, or assumed true for\n\t * serdes media) then poll for a \"Link-Up\" indication in the Device\n\t * Status Register. Time-out if a link isn't seen in 500 milliseconds\n\t * seconds (Auto-negotiation should complete in less than 500\n\t * milliseconds even if the other end is doing it in SW).\n\t */\n\tfor (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {\n\t\tmsec_delay(10);\n\t\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\t\tif (status & E1000_STATUS_LU)\n\t\t\tbreak;\n\t}\n\tif (i == FIBER_LINK_UP_LIMIT) {\n\t\tDEBUGOUT(\"Never got a valid link from auto-neg!!!\\n\");\n\t\tmac->autoneg_failed = true;\n\t\t/* AutoNeg failed to achieve a link, so we'll call\n\t\t * mac->check_for_link. This routine will force the\n\t\t * link up if we detect a signal. This will allow us to\n\t\t * communicate with non-autonegotiating link partners.\n\t\t */\n\t\tret_val = mac->ops.check_for_link(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error while checking for link\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t\tmac->autoneg_failed = false;\n\t} else {\n\t\tmac->autoneg_failed = false;\n\t\tDEBUGOUT(\"Valid Link Found\\n\");\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes\n * @hw: pointer to the HW structure\n *\n * Configures collision distance and flow control for fiber and serdes\n * links. Upon successful setup, poll for link.\n **/\ns32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_setup_fiber_serdes_link_generic\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\t/* Take the link out of reset */\n\tctrl &= ~E1000_CTRL_LRST;\n\n\thw->mac.ops.config_collision_dist(hw);\n\n\tret_val = e1000_commit_fc_settings_generic(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Since auto-negotiation is enabled, take the link out of reset (the\n\t * link will be in reset, because we previously reset the chip). This\n\t * will restart auto-negotiation. If auto-negotiation is successful\n\t * then the link-up status bit will be set and the flow control enable\n\t * bits (RFCE and TFCE) will be set according to their negotiated value.\n\t */\n\tDEBUGOUT(\"Auto-negotiation enabled\\n\");\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\tE1000_WRITE_FLUSH(hw);\n\tmsec_delay(1);\n\n\t/* For these adapters, the SW definable pin 1 is set when the optics\n\t * detect a signal. If we have a signal, then poll for a \"Link-Up\"\n\t * indication.\n\t */\n\tif (hw->phy.media_type == e1000_media_type_internal_serdes ||\n\t (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {\n\t\tret_val = e1000_poll_fiber_serdes_link_generic(hw);\n\t} else {\n\t\tDEBUGOUT(\"No signal detected\\n\");\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_config_collision_dist_generic - Configure collision distance\n * @hw: pointer to the HW structure\n *\n * Configures the collision distance to the default value and is used\n * during link setup.\n **/\nSTATIC void e1000_config_collision_dist_generic(struct e1000_hw *hw)\n{\n\tu32 tctl;\n\n\tDEBUGFUNC(\"e1000_config_collision_dist_generic\");\n\n\ttctl = E1000_READ_REG(hw, E1000_TCTL);\n\n\ttctl &= ~E1000_TCTL_COLD;\n\ttctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;\n\n\tE1000_WRITE_REG(hw, E1000_TCTL, tctl);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks\n * @hw: pointer to the HW structure\n *\n * Sets the flow control high/low threshold (watermark) registers. If\n * flow control XON frame transmission is enabled, then set XON frame\n * transmission as well.\n **/\ns32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)\n{\n\tu32 fcrtl = 0, fcrth = 0;\n\n\tDEBUGFUNC(\"e1000_set_fc_watermarks_generic\");\n\n\t/* Set the flow control receive threshold registers. Normally,\n\t * these registers will be set to a default threshold that may be\n\t * adjusted later by the driver's runtime code. However, if the\n\t * ability to transmit pause frames is not enabled, then these\n\t * registers will be set to 0.\n\t */\n\tif (hw->fc.current_mode & e1000_fc_tx_pause) {\n\t\t/* We need to set up the Receive Threshold high and low water\n\t\t * marks as well as (optionally) enabling the transmission of\n\t\t * XON frames.\n\t\t */\n\t\tfcrtl = hw->fc.low_water;\n\t\tif (hw->fc.send_xon)\n\t\t\tfcrtl |= E1000_FCRTL_XONE;\n\n\t\tfcrth = hw->fc.high_water;\n\t}\n\tE1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);\n\tE1000_WRITE_REG(hw, E1000_FCRTH, fcrth);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_force_mac_fc_generic - Force the MAC's flow control settings\n * @hw: pointer to the HW structure\n *\n * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the\n * device control register to reflect the adapter settings. TFCE and RFCE\n * need to be explicitly set by software when a copper PHY is used because\n * autonegotiation is managed by the PHY rather than the MAC. Software must\n * also configure these bits when link is forced on a fiber connection.\n **/\ns32 e1000_force_mac_fc_generic(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\n\tDEBUGFUNC(\"e1000_force_mac_fc_generic\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\t/* Because we didn't get link via the internal auto-negotiation\n\t * mechanism (we either forced link or we got link via PHY\n\t * auto-neg), we have to manually enable/disable transmit an\n\t * receive flow control.\n\t *\n\t * The \"Case\" statement below enables/disable flow control\n\t * according to the \"hw->fc.current_mode\" parameter.\n\t *\n\t * The possible values of the \"fc\" parameter are:\n\t * 0: Flow control is completely disabled\n\t * 1: Rx flow control is enabled (we can receive pause\n\t * frames but not send pause frames).\n\t * 2: Tx flow control is enabled (we can send pause frames\n\t * frames but we do not receive pause frames).\n\t * 3: Both Rx and Tx flow control (symmetric) is enabled.\n\t * other: No other values should be possible at this point.\n\t */\n\tDEBUGOUT1(\"hw->fc.current_mode = %u\\n\", hw->fc.current_mode);\n\n\tswitch (hw->fc.current_mode) {\n\tcase e1000_fc_none:\n\t\tctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));\n\t\tbreak;\n\tcase e1000_fc_rx_pause:\n\t\tctrl &= (~E1000_CTRL_TFCE);\n\t\tctrl |= E1000_CTRL_RFCE;\n\t\tbreak;\n\tcase e1000_fc_tx_pause:\n\t\tctrl &= (~E1000_CTRL_RFCE);\n\t\tctrl |= E1000_CTRL_TFCE;\n\t\tbreak;\n\tcase e1000_fc_full:\n\t\tctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\"Flow control param set incorrectly\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_config_fc_after_link_up_generic - Configures flow control after link\n * @hw: pointer to the HW structure\n *\n * Checks the status of auto-negotiation after link up to ensure that the\n * speed and duplex were not forced. If the link needed to be forced, then\n * flow control needs to be forced also. If auto-negotiation is enabled\n * and did not fail, then we configure flow control based on our link\n * partner.\n **/\ns32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;\n\tu16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;\n\tu16 speed, duplex;\n\n\tDEBUGFUNC(\"e1000_config_fc_after_link_up_generic\");\n\n\t/* Check for the case where we have fiber media and auto-neg failed\n\t * so we had to force link. In this case, we need to force the\n\t * configuration of the MAC to match the \"fc\" parameter.\n\t */\n\tif (mac->autoneg_failed) {\n\t\tif (hw->phy.media_type == e1000_media_type_fiber ||\n\t\t hw->phy.media_type == e1000_media_type_internal_serdes)\n\t\t\tret_val = e1000_force_mac_fc_generic(hw);\n\t} else {\n\t\tif (hw->phy.media_type == e1000_media_type_copper)\n\t\t\tret_val = e1000_force_mac_fc_generic(hw);\n\t}\n\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error forcing flow control settings\\n\");\n\t\treturn ret_val;\n\t}\n\n\t/* Check for the case where we have copper media and auto-neg is\n\t * enabled. In this case, we need to check and see if Auto-Neg\n\t * has completed, and if so, how the PHY and link partner has\n\t * flow control configured.\n\t */\n\tif ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {\n\t\t/* Read the MII Status Register and check to see if AutoNeg\n\t\t * has completed. We read this twice because this reg has\n\t\t * some \"sticky\" (latched) bits.\n\t\t */\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {\n\t\t\tDEBUGOUT(\"Copper PHY and Auto Neg has not completed.\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\n\t\t/* The AutoNeg process has completed, so we now need to\n\t\t * read both the Auto Negotiation Advertisement\n\t\t * Register (Address 4) and the Auto_Negotiation Base\n\t\t * Page Ability Register (Address 5) to determine how\n\t\t * flow control was negotiated.\n\t\t */\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,\n\t\t\t\t\t &mii_nway_adv_reg);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,\n\t\t\t\t\t &mii_nway_lp_ability_reg);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Two bits in the Auto Negotiation Advertisement Register\n\t\t * (Address 4) and two bits in the Auto Negotiation Base\n\t\t * Page Ability Register (Address 5) determine flow control\n\t\t * for both the PHY and the link partner. The following\n\t\t * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,\n\t\t * 1999, describes these PAUSE resolution bits and how flow\n\t\t * control is determined based upon these settings.\n\t\t * NOTE: DC = Don't Care\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 0 | 0 | DC | DC | e1000_fc_none\n\t\t * 0 | 1 | 0 | DC | e1000_fc_none\n\t\t * 0 | 1 | 1 | 0 | e1000_fc_none\n\t\t * 0 | 1 | 1 | 1 | e1000_fc_tx_pause\n\t\t * 1 | 0 | 0 | DC | e1000_fc_none\n\t\t * 1 | DC | 1 | DC | e1000_fc_full\n\t\t * 1 | 1 | 0 | 0 | e1000_fc_none\n\t\t * 1 | 1 | 0 | 1 | e1000_fc_rx_pause\n\t\t *\n\t\t * Are both PAUSE bits set to 1? If so, this implies\n\t\t * Symmetric Flow Control is enabled at both ends. The\n\t\t * ASM_DIR bits are irrelevant per the spec.\n\t\t *\n\t\t * For Symmetric Flow Control:\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 1 | DC | 1 | DC | E1000_fc_full\n\t\t *\n\t\t */\n\t\tif ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&\n\t\t (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {\n\t\t\t/* Now we need to check if the user selected Rx ONLY\n\t\t\t * of pause frames. In this case, we had to advertise\n\t\t\t * FULL flow control because we could not advertise Rx\n\t\t\t * ONLY. Hence, we must now check to see if we need to\n\t\t\t * turn OFF the TRANSMISSION of PAUSE frames.\n\t\t\t */\n\t\t\tif (hw->fc.requested_mode == e1000_fc_full) {\n\t\t\t\thw->fc.current_mode = e1000_fc_full;\n\t\t\t\tDEBUGOUT(\"Flow Control = FULL.\\n\");\n\t\t\t} else {\n\t\t\t\thw->fc.current_mode = e1000_fc_rx_pause;\n\t\t\t\tDEBUGOUT(\"Flow Control = Rx PAUSE frames only.\\n\");\n\t\t\t}\n\t\t}\n\t\t/* For receiving PAUSE frames ONLY.\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 0 | 1 | 1 | 1 | e1000_fc_tx_pause\n\t\t */\n\t\telse if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&\n\t\t\t (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&\n\t\t\t (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&\n\t\t\t (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {\n\t\t\thw->fc.current_mode = e1000_fc_tx_pause;\n\t\t\tDEBUGOUT(\"Flow Control = Tx PAUSE frames only.\\n\");\n\t\t}\n\t\t/* For transmitting PAUSE frames ONLY.\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 1 | 1 | 0 | 1 | e1000_fc_rx_pause\n\t\t */\n\t\telse if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&\n\t\t\t (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&\n\t\t\t !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&\n\t\t\t (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {\n\t\t\thw->fc.current_mode = e1000_fc_rx_pause;\n\t\t\tDEBUGOUT(\"Flow Control = Rx PAUSE frames only.\\n\");\n\t\t} else {\n\t\t\t/* Per the IEEE spec, at this point flow control\n\t\t\t * should be disabled.\n\t\t\t */\n\t\t\thw->fc.current_mode = e1000_fc_none;\n\t\t\tDEBUGOUT(\"Flow Control = NONE.\\n\");\n\t\t}\n\n\t\t/* Now we need to do one last check... If we auto-\n\t\t * negotiated to HALF DUPLEX, flow control should not be\n\t\t * enabled per IEEE 802.3 spec.\n\t\t */\n\t\tret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error getting link speed and duplex\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\n\t\tif (duplex == HALF_DUPLEX)\n\t\t\thw->fc.current_mode = e1000_fc_none;\n\n\t\t/* Now we call a subroutine to actually force the MAC\n\t\t * controller to use the correct flow control settings.\n\t\t */\n\t\tret_val = e1000_force_mac_fc_generic(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error forcing flow control settings\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\t/* Check for the case where we have SerDes media and auto-neg is\n\t * enabled. In this case, we need to check and see if Auto-Neg\n\t * has completed, and if so, how the PHY and link partner has\n\t * flow control configured.\n\t */\n\tif ((hw->phy.media_type == e1000_media_type_internal_serdes) &&\n\t mac->autoneg) {\n\t\t/* Read the PCS_LSTS and check to see if AutoNeg\n\t\t * has completed.\n\t\t */\n\t\tpcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);\n\n\t\tif (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {\n\t\t\tDEBUGOUT(\"PCS Auto Neg has not completed.\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\n\t\t/* The AutoNeg process has completed, so we now need to\n\t\t * read both the Auto Negotiation Advertisement\n\t\t * Register (PCS_ANADV) and the Auto_Negotiation Base\n\t\t * Page Ability Register (PCS_LPAB) to determine how\n\t\t * flow control was negotiated.\n\t\t */\n\t\tpcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);\n\t\tpcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);\n\n\t\t/* Two bits in the Auto Negotiation Advertisement Register\n\t\t * (PCS_ANADV) and two bits in the Auto Negotiation Base\n\t\t * Page Ability Register (PCS_LPAB) determine flow control\n\t\t * for both the PHY and the link partner. The following\n\t\t * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,\n\t\t * 1999, describes these PAUSE resolution bits and how flow\n\t\t * control is determined based upon these settings.\n\t\t * NOTE: DC = Don't Care\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 0 | 0 | DC | DC | e1000_fc_none\n\t\t * 0 | 1 | 0 | DC | e1000_fc_none\n\t\t * 0 | 1 | 1 | 0 | e1000_fc_none\n\t\t * 0 | 1 | 1 | 1 | e1000_fc_tx_pause\n\t\t * 1 | 0 | 0 | DC | e1000_fc_none\n\t\t * 1 | DC | 1 | DC | e1000_fc_full\n\t\t * 1 | 1 | 0 | 0 | e1000_fc_none\n\t\t * 1 | 1 | 0 | 1 | e1000_fc_rx_pause\n\t\t *\n\t\t * Are both PAUSE bits set to 1? If so, this implies\n\t\t * Symmetric Flow Control is enabled at both ends. The\n\t\t * ASM_DIR bits are irrelevant per the spec.\n\t\t *\n\t\t * For Symmetric Flow Control:\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 1 | DC | 1 | DC | e1000_fc_full\n\t\t *\n\t\t */\n\t\tif ((pcs_adv_reg & E1000_TXCW_PAUSE) &&\n\t\t (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {\n\t\t\t/* Now we need to check if the user selected Rx ONLY\n\t\t\t * of pause frames. In this case, we had to advertise\n\t\t\t * FULL flow control because we could not advertise Rx\n\t\t\t * ONLY. Hence, we must now check to see if we need to\n\t\t\t * turn OFF the TRANSMISSION of PAUSE frames.\n\t\t\t */\n\t\t\tif (hw->fc.requested_mode == e1000_fc_full) {\n\t\t\t\thw->fc.current_mode = e1000_fc_full;\n\t\t\t\tDEBUGOUT(\"Flow Control = FULL.\\n\");\n\t\t\t} else {\n\t\t\t\thw->fc.current_mode = e1000_fc_rx_pause;\n\t\t\t\tDEBUGOUT(\"Flow Control = Rx PAUSE frames only.\\n\");\n\t\t\t}\n\t\t}\n\t\t/* For receiving PAUSE frames ONLY.\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 0 | 1 | 1 | 1 | e1000_fc_tx_pause\n\t\t */\n\t\telse if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&\n\t\t\t (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&\n\t\t\t (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&\n\t\t\t (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {\n\t\t\thw->fc.current_mode = e1000_fc_tx_pause;\n\t\t\tDEBUGOUT(\"Flow Control = Tx PAUSE frames only.\\n\");\n\t\t}\n\t\t/* For transmitting PAUSE frames ONLY.\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 1 | 1 | 0 | 1 | e1000_fc_rx_pause\n\t\t */\n\t\telse if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&\n\t\t\t (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&\n\t\t\t !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&\n\t\t\t (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {\n\t\t\thw->fc.current_mode = e1000_fc_rx_pause;\n\t\t\tDEBUGOUT(\"Flow Control = Rx PAUSE frames only.\\n\");\n\t\t} else {\n\t\t\t/* Per the IEEE spec, at this point flow control\n\t\t\t * should be disabled.\n\t\t\t */\n\t\t\thw->fc.current_mode = e1000_fc_none;\n\t\t\tDEBUGOUT(\"Flow Control = NONE.\\n\");\n\t\t}\n\n\t\t/* Now we call a subroutine to actually force the MAC\n\t\t * controller to use the correct flow control settings.\n\t\t */\n\t\tpcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);\n\t\tpcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;\n\t\tE1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);\n\n\t\tret_val = e1000_force_mac_fc_generic(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error forcing flow control settings\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex\n * @hw: pointer to the HW structure\n * @speed: stores the current speed\n * @duplex: stores the current duplex\n *\n * Read the status register for the current speed/duplex and store the current\n * speed and duplex for copper connections.\n **/\ns32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\t u16 *duplex)\n{\n\tu32 status;\n\n\tDEBUGFUNC(\"e1000_get_speed_and_duplex_copper_generic\");\n\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\tif (status & E1000_STATUS_SPEED_1000) {\n\t\t*speed = SPEED_1000;\n\t\tDEBUGOUT(\"1000 Mbs, \");\n\t} else if (status & E1000_STATUS_SPEED_100) {\n\t\t*speed = SPEED_100;\n\t\tDEBUGOUT(\"100 Mbs, \");\n\t} else {\n\t\t*speed = SPEED_10;\n\t\tDEBUGOUT(\"10 Mbs, \");\n\t}\n\n\tif (status & E1000_STATUS_FD) {\n\t\t*duplex = FULL_DUPLEX;\n\t\tDEBUGOUT(\"Full Duplex\\n\");\n\t} else {\n\t\t*duplex = HALF_DUPLEX;\n\t\tDEBUGOUT(\"Half Duplex\\n\");\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex\n * @hw: pointer to the HW structure\n * @speed: stores the current speed\n * @duplex: stores the current duplex\n *\n * Sets the speed and duplex to gigabit full duplex (the only possible option)\n * for fiber/serdes links.\n **/\ns32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t\t\t\t u16 *speed, u16 *duplex)\n{\n\tDEBUGFUNC(\"e1000_get_speed_and_duplex_fiber_serdes_generic\");\n\tUNREFERENCED_1PARAMETER(hw);\n\n\t*speed = SPEED_1000;\n\t*duplex = FULL_DUPLEX;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_hw_semaphore_generic - Acquire hardware semaphore\n * @hw: pointer to the HW structure\n *\n * Acquire the HW semaphore to access the PHY or NVM\n **/\ns32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)\n{\n\tu32 swsm;\n\ts32 timeout = hw->nvm.word_size + 1;\n\ts32 i = 0;\n\n\tDEBUGFUNC(\"e1000_get_hw_semaphore_generic\");\n\n\t/* Get the SW semaphore */\n\twhile (i < timeout) {\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tif (!(swsm & E1000_SWSM_SMBI))\n\t\t\tbreak;\n\n\t\tusec_delay(50);\n\t\ti++;\n\t}\n\n\tif (i == timeout) {\n\t\tDEBUGOUT(\"Driver can't access device - SMBI bit is set.\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\t/* Get the FW semaphore. */\n\tfor (i = 0; i < timeout; i++) {\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tE1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);\n\n\t\t/* Semaphore acquired if bit latched */\n\t\tif (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)\n\t\t\tbreak;\n\n\t\tusec_delay(50);\n\t}\n\n\tif (i == timeout) {\n\t\t/* Release semaphores */\n\t\te1000_put_hw_semaphore_generic(hw);\n\t\tDEBUGOUT(\"Driver can't access the NVM\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_put_hw_semaphore_generic - Release hardware semaphore\n * @hw: pointer to the HW structure\n *\n * Release hardware semaphore used to access the PHY or NVM\n **/\nvoid e1000_put_hw_semaphore_generic(struct e1000_hw *hw)\n{\n\tu32 swsm;\n\n\tDEBUGFUNC(\"e1000_put_hw_semaphore_generic\");\n\n\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\n\tswsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);\n\n\tE1000_WRITE_REG(hw, E1000_SWSM, swsm);\n}\n\n/**\n * e1000_get_auto_rd_done_generic - Check for auto read completion\n * @hw: pointer to the HW structure\n *\n * Check EEPROM for Auto Read done bit.\n **/\ns32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)\n{\n\ts32 i = 0;\n\n\tDEBUGFUNC(\"e1000_get_auto_rd_done_generic\");\n\n\twhile (i < AUTO_READ_DONE_TIMEOUT) {\n\t\tif (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t\ti++;\n\t}\n\n\tif (i == AUTO_READ_DONE_TIMEOUT) {\n\t\tDEBUGOUT(\"Auto read by HW from NVM has not completed.\\n\");\n\t\treturn -E1000_ERR_RESET;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_valid_led_default_generic - Verify a valid default LED config\n * @hw: pointer to the HW structure\n * @data: pointer to the NVM (EEPROM)\n *\n * Read the EEPROM for the current default LED configuration. If the\n * LED configuration is not valid, set to a valid LED configuration.\n **/\ns32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_valid_led_default_generic\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)\n\t\t*data = ID_LED_DEFAULT;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_id_led_init_generic -\n * @hw: pointer to the HW structure\n *\n **/\ns32 e1000_id_led_init_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val;\n\tconst u32 ledctl_mask = 0x000000FF;\n\tconst u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;\n\tconst u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;\n\tu16 data, i, temp;\n\tconst u16 led_mask = 0x0F;\n\n\tDEBUGFUNC(\"e1000_id_led_init_generic\");\n\n\tret_val = hw->nvm.ops.valid_led_default(hw, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tmac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);\n\tmac->ledctl_mode1 = mac->ledctl_default;\n\tmac->ledctl_mode2 = mac->ledctl_default;\n\n\tfor (i = 0; i < 4; i++) {\n\t\ttemp = (data >> (i << 2)) & led_mask;\n\t\tswitch (temp) {\n\t\tcase ID_LED_ON1_DEF2:\n\t\tcase ID_LED_ON1_ON2:\n\t\tcase ID_LED_ON1_OFF2:\n\t\t\tmac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));\n\t\t\tmac->ledctl_mode1 |= ledctl_on << (i << 3);\n\t\t\tbreak;\n\t\tcase ID_LED_OFF1_DEF2:\n\t\tcase ID_LED_OFF1_ON2:\n\t\tcase ID_LED_OFF1_OFF2:\n\t\t\tmac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));\n\t\t\tmac->ledctl_mode1 |= ledctl_off << (i << 3);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* Do nothing */\n\t\t\tbreak;\n\t\t}\n\t\tswitch (temp) {\n\t\tcase ID_LED_DEF1_ON2:\n\t\tcase ID_LED_ON1_ON2:\n\t\tcase ID_LED_OFF1_ON2:\n\t\t\tmac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));\n\t\t\tmac->ledctl_mode2 |= ledctl_on << (i << 3);\n\t\t\tbreak;\n\t\tcase ID_LED_DEF1_OFF2:\n\t\tcase ID_LED_ON1_OFF2:\n\t\tcase ID_LED_OFF1_OFF2:\n\t\t\tmac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));\n\t\t\tmac->ledctl_mode2 |= ledctl_off << (i << 3);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* Do nothing */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_setup_led_generic - Configures SW controllable LED\n * @hw: pointer to the HW structure\n *\n * This prepares the SW controllable LED for use and saves the current state\n * of the LED so it can be later restored.\n **/\ns32 e1000_setup_led_generic(struct e1000_hw *hw)\n{\n\tu32 ledctl;\n\n\tDEBUGFUNC(\"e1000_setup_led_generic\");\n\n\tif (hw->mac.ops.setup_led != e1000_setup_led_generic)\n\t\treturn -E1000_ERR_CONFIG;\n\n\tif (hw->phy.media_type == e1000_media_type_fiber) {\n\t\tledctl = E1000_READ_REG(hw, E1000_LEDCTL);\n\t\thw->mac.ledctl_default = ledctl;\n\t\t/* Turn off LED0 */\n\t\tledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |\n\t\t\t E1000_LEDCTL_LED0_MODE_MASK);\n\t\tledctl |= (E1000_LEDCTL_MODE_LED_OFF <<\n\t\t\t E1000_LEDCTL_LED0_MODE_SHIFT);\n\t\tE1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);\n\t} else if (hw->phy.media_type == e1000_media_type_copper) {\n\t\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_cleanup_led_generic - Set LED config to default operation\n * @hw: pointer to the HW structure\n *\n * Remove the current LED configuration and set the LED configuration\n * to the default value, saved from the EEPROM.\n **/\ns32 e1000_cleanup_led_generic(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_cleanup_led_generic\");\n\n\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_blink_led_generic - Blink LED\n * @hw: pointer to the HW structure\n *\n * Blink the LEDs which are set to be on.\n **/\ns32 e1000_blink_led_generic(struct e1000_hw *hw)\n{\n\tu32 ledctl_blink = 0;\n\tu32 i;\n\n\tDEBUGFUNC(\"e1000_blink_led_generic\");\n\n\tif (hw->phy.media_type == e1000_media_type_fiber) {\n\t\t/* always blink LED0 for PCI-E fiber */\n\t\tledctl_blink = E1000_LEDCTL_LED0_BLINK |\n\t\t (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);\n\t} else {\n\t\t/* Set the blink bit for each LED that's \"on\" (0x0E)\n\t\t * (or \"off\" if inverted) in ledctl_mode2. The blink\n\t\t * logic in hardware only works when mode is set to \"on\"\n\t\t * so it must be changed accordingly when the mode is\n\t\t * \"off\" and inverted.\n\t\t */\n\t\tledctl_blink = hw->mac.ledctl_mode2;\n\t\tfor (i = 0; i < 32; i += 8) {\n\t\t\tu32 mode = (hw->mac.ledctl_mode2 >> i) &\n\t\t\t E1000_LEDCTL_LED0_MODE_MASK;\n\t\t\tu32 led_default = hw->mac.ledctl_default >> i;\n\n\t\t\tif ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&\n\t\t\t (mode == E1000_LEDCTL_MODE_LED_ON)) ||\n\t\t\t ((led_default & E1000_LEDCTL_LED0_IVRT) &&\n\t\t\t (mode == E1000_LEDCTL_MODE_LED_OFF))) {\n\t\t\t\tledctl_blink &=\n\t\t\t\t ~(E1000_LEDCTL_LED0_MODE_MASK << i);\n\t\t\t\tledctl_blink |= (E1000_LEDCTL_LED0_BLINK |\n\t\t\t\t\t\t E1000_LEDCTL_MODE_LED_ON) << i;\n\t\t\t}\n\t\t}\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_led_on_generic - Turn LED on\n * @hw: pointer to the HW structure\n *\n * Turn LED on.\n **/\ns32 e1000_led_on_generic(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\n\tDEBUGFUNC(\"e1000_led_on_generic\");\n\n\tswitch (hw->phy.media_type) {\n\tcase e1000_media_type_fiber:\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tctrl &= ~E1000_CTRL_SWDPIN0;\n\t\tctrl |= E1000_CTRL_SWDPIO0;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\t\tbreak;\n\tcase e1000_media_type_copper:\n\t\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_led_off_generic - Turn LED off\n * @hw: pointer to the HW structure\n *\n * Turn LED off.\n **/\ns32 e1000_led_off_generic(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\n\tDEBUGFUNC(\"e1000_led_off_generic\");\n\n\tswitch (hw->phy.media_type) {\n\tcase e1000_media_type_fiber:\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tctrl |= E1000_CTRL_SWDPIN0;\n\t\tctrl |= E1000_CTRL_SWDPIO0;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\t\tbreak;\n\tcase e1000_media_type_copper:\n\t\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities\n * @hw: pointer to the HW structure\n * @no_snoop: bitmap of snoop events\n *\n * Set the PCI-express register to snoop for events enabled in 'no_snoop'.\n **/\nvoid e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)\n{\n\tu32 gcr;\n\n\tDEBUGFUNC(\"e1000_set_pcie_no_snoop_generic\");\n\n\tif (hw->bus.type != e1000_bus_type_pci_express)\n\t\treturn;\n\n\tif (no_snoop) {\n\t\tgcr = E1000_READ_REG(hw, E1000_GCR);\n\t\tgcr &= ~(PCIE_NO_SNOOP_ALL);\n\t\tgcr |= no_snoop;\n\t\tE1000_WRITE_REG(hw, E1000_GCR, gcr);\n\t}\n}\n\n/**\n * e1000_disable_pcie_master_generic - Disables PCI-express master access\n * @hw: pointer to the HW structure\n *\n * Returns E1000_SUCCESS if successful, else returns -10\n * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused\n * the master requests to be disabled.\n *\n * Disables PCI-Express master access and verifies there are no pending\n * requests.\n **/\ns32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 timeout = MASTER_DISABLE_TIMEOUT;\n\n\tDEBUGFUNC(\"e1000_disable_pcie_master_generic\");\n\n\tif (hw->bus.type != e1000_bus_type_pci_express)\n\t\treturn E1000_SUCCESS;\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= E1000_CTRL_GIO_MASTER_DISABLE;\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\twhile (timeout) {\n\t\tif (!(E1000_READ_REG(hw, E1000_STATUS) &\n\t\t E1000_STATUS_GIO_MASTER_ENABLE) ||\n\t\t\t\tE1000_REMOVED(hw->hw_addr))\n\t\t\tbreak;\n\t\tusec_delay(100);\n\t\ttimeout--;\n\t}\n\n\tif (!timeout) {\n\t\tDEBUGOUT(\"Master requests are pending.\\n\");\n\t\treturn -E1000_ERR_MASTER_REQUESTS_PENDING;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing\n * @hw: pointer to the HW structure\n *\n * Reset the Adaptive Interframe Spacing throttle to default values.\n **/\nvoid e1000_reset_adaptive_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"e1000_reset_adaptive_generic\");\n\n\tif (!mac->adaptive_ifs) {\n\t\tDEBUGOUT(\"Not in Adaptive IFS mode!\\n\");\n\t\treturn;\n\t}\n\n\tmac->current_ifs_val = 0;\n\tmac->ifs_min_val = IFS_MIN;\n\tmac->ifs_max_val = IFS_MAX;\n\tmac->ifs_step_size = IFS_STEP;\n\tmac->ifs_ratio = IFS_RATIO;\n\n\tmac->in_ifs_mode = false;\n\tE1000_WRITE_REG(hw, E1000_AIT, 0);\n}\n\n/**\n * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing\n * @hw: pointer to the HW structure\n *\n * Update the Adaptive Interframe Spacing Throttle value based on the\n * time between transmitted packets and time between collisions.\n **/\nvoid e1000_update_adaptive_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"e1000_update_adaptive_generic\");\n\n\tif (!mac->adaptive_ifs) {\n\t\tDEBUGOUT(\"Not in Adaptive IFS mode!\\n\");\n\t\treturn;\n\t}\n\n\tif ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {\n\t\tif (mac->tx_packet_delta > MIN_NUM_XMITS) {\n\t\t\tmac->in_ifs_mode = true;\n\t\t\tif (mac->current_ifs_val < mac->ifs_max_val) {\n\t\t\t\tif (!mac->current_ifs_val)\n\t\t\t\t\tmac->current_ifs_val = mac->ifs_min_val;\n\t\t\t\telse\n\t\t\t\t\tmac->current_ifs_val +=\n\t\t\t\t\t\tmac->ifs_step_size;\n\t\t\t\tE1000_WRITE_REG(hw, E1000_AIT,\n\t\t\t\t\t\tmac->current_ifs_val);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif (mac->in_ifs_mode &&\n\t\t (mac->tx_packet_delta <= MIN_NUM_XMITS)) {\n\t\t\tmac->current_ifs_val = 0;\n\t\t\tmac->in_ifs_mode = false;\n\t\t\tE1000_WRITE_REG(hw, E1000_AIT, 0);\n\t\t}\n\t}\n}\n\n/**\n * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings\n * @hw: pointer to the HW structure\n *\n * Verify that when not using auto-negotiation that MDI/MDIx is correctly\n * set, which is forced to MDI mode only.\n **/\nSTATIC s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_validate_mdi_setting_generic\");\n\n\tif (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {\n\t\tDEBUGOUT(\"Invalid MDI setting detected\\n\");\n\t\thw->phy.mdix = 1;\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings\n * @hw: pointer to the HW structure\n *\n * Validate the MDI/MDIx setting, allowing for auto-crossover during forced\n * operation.\n **/\ns32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_validate_mdi_setting_crossover_generic\");\n\tUNREFERENCED_1PARAMETER(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register\n * @hw: pointer to the HW structure\n * @reg: 32bit register offset such as E1000_SCTL\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Writes an address/data control type register. There are several of these\n * and they all have the format address << 8 | data and bit 31 is polled for\n * completion.\n **/\ns32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,\n\t\t\t\t u32 offset, u8 data)\n{\n\tu32 i, regvalue = 0;\n\n\tDEBUGFUNC(\"e1000_write_8bit_ctrl_reg_generic\");\n\n\t/* Set up the address and data */\n\tregvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);\n\tE1000_WRITE_REG(hw, reg, regvalue);\n\n\t/* Poll the ready bit to see if the MDI read completed */\n\tfor (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {\n\t\tusec_delay(5);\n\t\tregvalue = E1000_READ_REG(hw, reg);\n\t\tif (regvalue & E1000_GEN_CTL_READY)\n\t\t\tbreak;\n\t}\n\tif (!(regvalue & E1000_GEN_CTL_READY)) {\n\t\tDEBUGOUT1(\"Reg %08x did not indicate ready\\n\", reg);\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n" }, { "path": "drivers/net/e1000/base/e1000_mac.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_MAC_H_\n#define _E1000_MAC_H_\n\nvoid e1000_init_mac_ops_generic(struct e1000_hw *hw);\n#ifndef E1000_REMOVED\n#define E1000_REMOVED(a) (0)\n#endif /* E1000_REMOVED */\nvoid e1000_null_mac_generic(struct e1000_hw *hw);\ns32 e1000_null_ops_generic(struct e1000_hw *hw);\ns32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d);\nbool e1000_null_mng_mode(struct e1000_hw *hw);\nvoid e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a);\nvoid e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b);\nvoid e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a);\ns32 e1000_blink_led_generic(struct e1000_hw *hw);\ns32 e1000_check_for_copper_link_generic(struct e1000_hw *hw);\ns32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw);\ns32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw);\ns32 e1000_cleanup_led_generic(struct e1000_hw *hw);\ns32 e1000_commit_fc_settings_generic(struct e1000_hw *hw);\ns32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw);\ns32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw);\ns32 e1000_disable_pcie_master_generic(struct e1000_hw *hw);\ns32 e1000_force_mac_fc_generic(struct e1000_hw *hw);\ns32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw);\ns32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw);\ns32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw);\nvoid e1000_set_lan_id_single_port(struct e1000_hw *hw);\nvoid e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw);\ns32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw);\ns32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\t u16 *duplex);\ns32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,\n\t\t\t\t\t\t u16 *speed, u16 *duplex);\ns32 e1000_id_led_init_generic(struct e1000_hw *hw);\ns32 e1000_led_on_generic(struct e1000_hw *hw);\ns32 e1000_led_off_generic(struct e1000_hw *hw);\nvoid e1000_update_mc_addr_list_generic(struct e1000_hw *hw,\n\t\t\t\t u8 *mc_addr_list, u32 mc_addr_count);\ns32 e1000_set_default_fc_generic(struct e1000_hw *hw);\ns32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw);\ns32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw);\ns32 e1000_setup_led_generic(struct e1000_hw *hw);\ns32 e1000_setup_link_generic(struct e1000_hw *hw);\ns32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw);\ns32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,\n\t\t\t\t u32 offset, u8 data);\n\nu32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr);\n\nvoid e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw);\nvoid e1000_clear_vfta_generic(struct e1000_hw *hw);\nvoid e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count);\nvoid e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw);\nvoid e1000_put_hw_semaphore_generic(struct e1000_hw *hw);\ns32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);\nvoid e1000_reset_adaptive_generic(struct e1000_hw *hw);\nvoid e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop);\nvoid e1000_update_adaptive_generic(struct e1000_hw *hw);\nvoid e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);\n\n#endif\n" }, { "path": "drivers/net/e1000/base/e1000_manage.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"e1000_api.h\"\n\n/**\n * e1000_calculate_checksum - Calculate checksum for buffer\n * @buffer: pointer to EEPROM\n * @length: size of EEPROM to calculate a checksum for\n *\n * Calculates the checksum for some buffer on a specified length. The\n * checksum calculated is returned.\n **/\nu8 e1000_calculate_checksum(u8 *buffer, u32 length)\n{\n\tu32 i;\n\tu8 sum = 0;\n\n\tDEBUGFUNC(\"e1000_calculate_checksum\");\n\n\tif (!buffer)\n\t\treturn 0;\n\n\tfor (i = 0; i < length; i++)\n\t\tsum += buffer[i];\n\n\treturn (u8) (0 - sum);\n}\n\n/**\n * e1000_mng_enable_host_if_generic - Checks host interface is enabled\n * @hw: pointer to the HW structure\n *\n * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND\n *\n * This function checks whether the HOST IF is enabled for command operation\n * and also checks whether the previous command is completed. It busy waits\n * in case of previous command is not completed.\n **/\ns32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)\n{\n\tu32 hicr;\n\tu8 i;\n\n\tDEBUGFUNC(\"e1000_mng_enable_host_if_generic\");\n\n\tif (!hw->mac.arc_subsystem_valid) {\n\t\tDEBUGOUT(\"ARC subsystem not valid.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\t/* Check that the host interface is enabled. */\n\thicr = E1000_READ_REG(hw, E1000_HICR);\n\tif (!(hicr & E1000_HICR_EN)) {\n\t\tDEBUGOUT(\"E1000_HOST_EN bit disabled.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\t/* check the previous command is completed */\n\tfor (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {\n\t\thicr = E1000_READ_REG(hw, E1000_HICR);\n\t\tif (!(hicr & E1000_HICR_C))\n\t\t\tbreak;\n\t\tmsec_delay_irq(1);\n\t}\n\n\tif (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {\n\t\tDEBUGOUT(\"Previous command timeout failed .\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_check_mng_mode_generic - Generic check management mode\n * @hw: pointer to the HW structure\n *\n * Reads the firmware semaphore register and returns true (>0) if\n * manageability is enabled, else false (0).\n **/\nbool e1000_check_mng_mode_generic(struct e1000_hw *hw)\n{\n\tu32 fwsm = E1000_READ_REG(hw, E1000_FWSM);\n\n\tDEBUGFUNC(\"e1000_check_mng_mode_generic\");\n\n\n\treturn (fwsm & E1000_FWSM_MODE_MASK) ==\n\t\t(E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);\n}\n\n/**\n * e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx\n * @hw: pointer to the HW structure\n *\n * Enables packet filtering on transmit packets if manageability is enabled\n * and host interface is enabled.\n **/\nbool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;\n\tu32 *buffer = (u32 *)&hw->mng_cookie;\n\tu32 offset;\n\ts32 ret_val, hdr_csum, csum;\n\tu8 i, len;\n\n\tDEBUGFUNC(\"e1000_enable_tx_pkt_filtering_generic\");\n\n\thw->mac.tx_pkt_filtering = true;\n\n\t/* No manageability, no filtering */\n\tif (!hw->mac.ops.check_mng_mode(hw)) {\n\t\thw->mac.tx_pkt_filtering = false;\n\t\treturn hw->mac.tx_pkt_filtering;\n\t}\n\n\t/* If we can't read from the host interface for whatever\n\t * reason, disable filtering.\n\t */\n\tret_val = e1000_mng_enable_host_if_generic(hw);\n\tif (ret_val != E1000_SUCCESS) {\n\t\thw->mac.tx_pkt_filtering = false;\n\t\treturn hw->mac.tx_pkt_filtering;\n\t}\n\n\t/* Read in the header. Length and offset are in dwords. */\n\tlen = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;\n\toffset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;\n\tfor (i = 0; i < len; i++)\n\t\t*(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,\n\t\t\t\t\t\t\t offset + i);\n\thdr_csum = hdr->checksum;\n\thdr->checksum = 0;\n\tcsum = e1000_calculate_checksum((u8 *)hdr,\n\t\t\t\t\tE1000_MNG_DHCP_COOKIE_LENGTH);\n\t/* If either the checksums or signature don't match, then\n\t * the cookie area isn't considered valid, in which case we\n\t * take the safe route of assuming Tx filtering is enabled.\n\t */\n\tif ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {\n\t\thw->mac.tx_pkt_filtering = true;\n\t\treturn hw->mac.tx_pkt_filtering;\n\t}\n\n\t/* Cookie area is valid, make the final check for filtering. */\n\tif (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))\n\t\thw->mac.tx_pkt_filtering = false;\n\n\treturn hw->mac.tx_pkt_filtering;\n}\n\n/**\n * e1000_mng_write_cmd_header_generic - Writes manageability command header\n * @hw: pointer to the HW structure\n * @hdr: pointer to the host interface command header\n *\n * Writes the command header after does the checksum calculation.\n **/\ns32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,\n\t\t\t\t struct e1000_host_mng_command_header *hdr)\n{\n\tu16 i, length = sizeof(struct e1000_host_mng_command_header);\n\n\tDEBUGFUNC(\"e1000_mng_write_cmd_header_generic\");\n\n\t/* Write the whole command header structure with new checksum. */\n\n\thdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);\n\n\tlength >>= 2;\n\t/* Write the relevant command block into the ram area. */\n\tfor (i = 0; i < length; i++) {\n\t\tE1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,\n\t\t\t\t\t *((u32 *) hdr + i));\n\t\tE1000_WRITE_FLUSH(hw);\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_mng_host_if_write_generic - Write to the manageability host interface\n * @hw: pointer to the HW structure\n * @buffer: pointer to the host interface buffer\n * @length: size of the buffer\n * @offset: location in the buffer to write to\n * @sum: sum of the data (not checksum)\n *\n * This function writes the buffer content at the offset given on the host if.\n * It also does alignment considerations to do the writes in most efficient\n * way. Also fills up the sum of the buffer in *buffer parameter.\n **/\ns32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,\n\t\t\t\t u16 length, u16 offset, u8 *sum)\n{\n\tu8 *tmp;\n\tu8 *bufptr = buffer;\n\tu32 data = 0;\n\tu16 remaining, i, j, prev_bytes;\n\n\tDEBUGFUNC(\"e1000_mng_host_if_write_generic\");\n\n\t/* sum = only sum of the data and it is not checksum */\n\n\tif (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)\n\t\treturn -E1000_ERR_PARAM;\n\n\ttmp = (u8 *)&data;\n\tprev_bytes = offset & 0x3;\n\toffset >>= 2;\n\n\tif (prev_bytes) {\n\t\tdata = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);\n\t\tfor (j = prev_bytes; j < sizeof(u32); j++) {\n\t\t\t*(tmp + j) = *bufptr++;\n\t\t\t*sum += *(tmp + j);\n\t\t}\n\t\tE1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);\n\t\tlength -= j - prev_bytes;\n\t\toffset++;\n\t}\n\n\tremaining = length & 0x3;\n\tlength -= remaining;\n\n\t/* Calculate length in DWORDs */\n\tlength >>= 2;\n\n\t/* The device driver writes the relevant command block into the\n\t * ram area.\n\t */\n\tfor (i = 0; i < length; i++) {\n\t\tfor (j = 0; j < sizeof(u32); j++) {\n\t\t\t*(tmp + j) = *bufptr++;\n\t\t\t*sum += *(tmp + j);\n\t\t}\n\n\t\tE1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,\n\t\t\t\t\t data);\n\t}\n\tif (remaining) {\n\t\tfor (j = 0; j < sizeof(u32); j++) {\n\t\t\tif (j < remaining)\n\t\t\t\t*(tmp + j) = *bufptr++;\n\t\t\telse\n\t\t\t\t*(tmp + j) = 0;\n\n\t\t\t*sum += *(tmp + j);\n\t\t}\n\t\tE1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,\n\t\t\t\t\t data);\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface\n * @hw: pointer to the HW structure\n * @buffer: pointer to the host interface\n * @length: size of the buffer\n *\n * Writes the DHCP information to the host interface.\n **/\ns32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,\n\t\t\t\t u16 length)\n{\n\tstruct e1000_host_mng_command_header hdr;\n\ts32 ret_val;\n\tu32 hicr;\n\n\tDEBUGFUNC(\"e1000_mng_write_dhcp_info_generic\");\n\n\thdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;\n\thdr.command_length = length;\n\thdr.reserved1 = 0;\n\thdr.reserved2 = 0;\n\thdr.checksum = 0;\n\n\t/* Enable the host interface */\n\tret_val = e1000_mng_enable_host_if_generic(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Populate the host interface with the contents of \"buffer\". */\n\tret_val = e1000_mng_host_if_write_generic(hw, buffer, length,\n\t\t\t\t\t\t sizeof(hdr), &(hdr.checksum));\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Write the manageability command header */\n\tret_val = e1000_mng_write_cmd_header_generic(hw, &hdr);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Tell the ARC a new command is pending. */\n\thicr = E1000_READ_REG(hw, E1000_HICR);\n\tE1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_enable_mng_pass_thru - Check if management passthrough is needed\n * @hw: pointer to the HW structure\n *\n * Verifies the hardware needs to leave interface enabled so that frames can\n * be directed to and from the management interface.\n **/\nbool e1000_enable_mng_pass_thru(struct e1000_hw *hw)\n{\n\tu32 manc;\n\tu32 fwsm, factps;\n\n\tDEBUGFUNC(\"e1000_enable_mng_pass_thru\");\n\n\tif (!hw->mac.asf_firmware_present)\n\t\treturn false;\n\n\tmanc = E1000_READ_REG(hw, E1000_MANC);\n\n\tif (!(manc & E1000_MANC_RCV_TCO_EN))\n\t\treturn false;\n\n\tif (hw->mac.has_fwsm) {\n\t\tfwsm = E1000_READ_REG(hw, E1000_FWSM);\n\t\tfactps = E1000_READ_REG(hw, E1000_FACTPS);\n\n\t\tif (!(factps & E1000_FACTPS_MNGCG) &&\n\t\t ((fwsm & E1000_FWSM_MODE_MASK) ==\n\t\t (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))\n\t\t\treturn true;\n\t} else if ((hw->mac.type == e1000_82574) ||\n\t\t (hw->mac.type == e1000_82583)) {\n\t\tu16 data;\n\n\t\tfactps = E1000_READ_REG(hw, E1000_FACTPS);\n\t\te1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);\n\n\t\tif (!(factps & E1000_FACTPS_MNGCG) &&\n\t\t ((data & E1000_NVM_INIT_CTRL2_MNGM) ==\n\t\t (e1000_mng_mode_pt << 13)))\n\t\t\treturn true;\n\t} else if ((manc & E1000_MANC_SMBUS_EN) &&\n\t\t !(manc & E1000_MANC_ASF_EN)) {\n\t\treturn true;\n\t}\n\n\treturn false;\n}\n\n/**\n * e1000_host_interface_command - Writes buffer to host interface\n * @hw: pointer to the HW structure\n * @buffer: contains a command to write\n * @length: the byte length of the buffer, must be multiple of 4 bytes\n *\n * Writes a buffer to the Host Interface. Upon success, returns E1000_SUCCESS\n * else returns E1000_ERR_HOST_INTERFACE_COMMAND.\n **/\ns32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)\n{\n\tu32 hicr, i;\n\n\tDEBUGFUNC(\"e1000_host_interface_command\");\n\n\tif (!(hw->mac.arc_subsystem_valid)) {\n\t\tDEBUGOUT(\"Hardware doesn't support host interface command.\\n\");\n\t\treturn E1000_SUCCESS;\n\t}\n\n\tif (!hw->mac.asf_firmware_present) {\n\t\tDEBUGOUT(\"Firmware is not present.\\n\");\n\t\treturn E1000_SUCCESS;\n\t}\n\n\tif (length == 0 || length & 0x3 ||\n\t length > E1000_HI_MAX_BLOCK_BYTE_LENGTH) {\n\t\tDEBUGOUT(\"Buffer length failure.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\t/* Check that the host interface is enabled. */\n\thicr = E1000_READ_REG(hw, E1000_HICR);\n\tif (!(hicr & E1000_HICR_EN)) {\n\t\tDEBUGOUT(\"E1000_HOST_EN bit disabled.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\t/* Calculate length in DWORDs */\n\tlength >>= 2;\n\n\t/* The device driver writes the relevant command block\n\t * into the ram area.\n\t */\n\tfor (i = 0; i < length; i++)\n\t\tE1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,\n\t\t\t\t\t *((u32 *)buffer + i));\n\n\t/* Setting this bit tells the ARC that a new command is pending. */\n\tE1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);\n\n\tfor (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {\n\t\thicr = E1000_READ_REG(hw, E1000_HICR);\n\t\tif (!(hicr & E1000_HICR_C))\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t}\n\n\t/* Check command successful completion. */\n\tif (i == E1000_HI_COMMAND_TIMEOUT ||\n\t (!(E1000_READ_REG(hw, E1000_HICR) & E1000_HICR_SV))) {\n\t\tDEBUGOUT(\"Command has failed with no status valid.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\tfor (i = 0; i < length; i++)\n\t\t*((u32 *)buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,\n\t\t\t\t\t\t\t\t E1000_HOST_IF,\n\t\t\t\t\t\t\t\t i);\n\n\treturn E1000_SUCCESS;\n}\n/**\n * e1000_load_firmware - Writes proxy FW code buffer to host interface\n * and execute.\n * @hw: pointer to the HW structure\n * @buffer: contains a firmware to write\n * @length: the byte length of the buffer, must be multiple of 4 bytes\n *\n * Upon success returns E1000_SUCCESS, returns E1000_ERR_CONFIG if not enabled\n * in HW else returns E1000_ERR_HOST_INTERFACE_COMMAND.\n **/\ns32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)\n{\n\tu32 hicr, hibba, fwsm, icr, i;\n\n\tDEBUGFUNC(\"e1000_load_firmware\");\n\n\tif (hw->mac.type < e1000_i210) {\n\t\tDEBUGOUT(\"Hardware doesn't support loading FW by the driver\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\t/* Check that the host interface is enabled. */\n\thicr = E1000_READ_REG(hw, E1000_HICR);\n\tif (!(hicr & E1000_HICR_EN)) {\n\t\tDEBUGOUT(\"E1000_HOST_EN bit disabled.\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\tif (!(hicr & E1000_HICR_MEMORY_BASE_EN)) {\n\t\tDEBUGOUT(\"E1000_HICR_MEMORY_BASE_EN bit disabled.\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tif (length == 0 || length & 0x3 || length > E1000_HI_FW_MAX_LENGTH) {\n\t\tDEBUGOUT(\"Buffer length failure.\\n\");\n\t\treturn -E1000_ERR_INVALID_ARGUMENT;\n\t}\n\n\t/* Clear notification from ROM-FW by reading ICR register */\n\ticr = E1000_READ_REG(hw, E1000_ICR_V2);\n\n\t/* Reset ROM-FW */\n\thicr = E1000_READ_REG(hw, E1000_HICR);\n\thicr |= E1000_HICR_FW_RESET_ENABLE;\n\tE1000_WRITE_REG(hw, E1000_HICR, hicr);\n\thicr |= E1000_HICR_FW_RESET;\n\tE1000_WRITE_REG(hw, E1000_HICR, hicr);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* Wait till MAC notifies about its readiness after ROM-FW reset */\n\tfor (i = 0; i < (E1000_HI_COMMAND_TIMEOUT * 2); i++) {\n\t\ticr = E1000_READ_REG(hw, E1000_ICR_V2);\n\t\tif (icr & E1000_ICR_MNG)\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t}\n\n\t/* Check for timeout */\n\tif (i == E1000_HI_COMMAND_TIMEOUT) {\n\t\tDEBUGOUT(\"FW reset failed.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\t/* Wait till MAC is ready to accept new FW code */\n\tfor (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {\n\t\tfwsm = E1000_READ_REG(hw, E1000_FWSM);\n\t\tif ((fwsm & E1000_FWSM_FW_VALID) &&\n\t\t ((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT ==\n\t\t E1000_FWSM_HI_EN_ONLY_MODE))\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t}\n\n\t/* Check for timeout */\n\tif (i == E1000_HI_COMMAND_TIMEOUT) {\n\t\tDEBUGOUT(\"FW reset failed.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\t/* Calculate length in DWORDs */\n\tlength >>= 2;\n\n\t/* The device driver writes the relevant FW code block\n\t * into the ram area in DWORDs via 1kB ram addressing window.\n\t */\n\tfor (i = 0; i < length; i++) {\n\t\tif (!(i % E1000_HI_FW_BLOCK_DWORD_LENGTH)) {\n\t\t\t/* Point to correct 1kB ram window */\n\t\t\thibba = E1000_HI_FW_BASE_ADDRESS +\n\t\t\t\t((E1000_HI_FW_BLOCK_DWORD_LENGTH << 2) *\n\t\t\t\t(i / E1000_HI_FW_BLOCK_DWORD_LENGTH));\n\n\t\t\tE1000_WRITE_REG(hw, E1000_HIBBA, hibba);\n\t\t}\n\n\t\tE1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF,\n\t\t\t\t\t i % E1000_HI_FW_BLOCK_DWORD_LENGTH,\n\t\t\t\t\t *((u32 *)buffer + i));\n\t}\n\n\t/* Setting this bit tells the ARC that a new FW is ready to execute. */\n\thicr = E1000_READ_REG(hw, E1000_HICR);\n\tE1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);\n\n\tfor (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {\n\t\thicr = E1000_READ_REG(hw, E1000_HICR);\n\t\tif (!(hicr & E1000_HICR_C))\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t}\n\n\t/* Check for successful FW start. */\n\tif (i == E1000_HI_COMMAND_TIMEOUT) {\n\t\tDEBUGOUT(\"New FW did not start within timeout period.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n\n" }, { "path": "drivers/net/e1000/base/e1000_manage.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_MANAGE_H_\n#define _E1000_MANAGE_H_\n\nbool e1000_check_mng_mode_generic(struct e1000_hw *hw);\nbool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);\ns32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw);\ns32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,\n\t\t\t\t u16 length, u16 offset, u8 *sum);\ns32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,\n\t\t\t\t struct e1000_host_mng_command_header *hdr);\ns32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,\n\t\t\t\t u8 *buffer, u16 length);\nbool e1000_enable_mng_pass_thru(struct e1000_hw *hw);\nu8 e1000_calculate_checksum(u8 *buffer, u32 length);\ns32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length);\ns32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length);\n\nenum e1000_mng_mode {\n\te1000_mng_mode_none = 0,\n\te1000_mng_mode_asf,\n\te1000_mng_mode_pt,\n\te1000_mng_mode_ipmi,\n\te1000_mng_mode_host_if_only\n};\n\n#define E1000_FACTPS_MNGCG\t\t\t0x20000000\n\n#define E1000_FWSM_MODE_MASK\t\t\t0xE\n#define E1000_FWSM_MODE_SHIFT\t\t\t1\n#define E1000_FWSM_FW_VALID\t\t\t0x00008000\n#define E1000_FWSM_HI_EN_ONLY_MODE\t\t0x4\n\n#define E1000_MNG_IAMT_MODE\t\t\t0x3\n#define E1000_MNG_DHCP_COOKIE_LENGTH\t\t0x10\n#define E1000_MNG_DHCP_COOKIE_OFFSET\t\t0x6F0\n#define E1000_MNG_DHCP_COMMAND_TIMEOUT\t\t10\n#define E1000_MNG_DHCP_TX_PAYLOAD_CMD\t\t64\n#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING\t0x1\n#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN\t0x2\n\n#define E1000_VFTA_ENTRY_SHIFT\t\t\t5\n#define E1000_VFTA_ENTRY_MASK\t\t\t0x7F\n#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK\t\t0x1F\n\n#define E1000_HI_MAX_BLOCK_BYTE_LENGTH\t\t1792 /* Num of bytes in range */\n#define E1000_HI_MAX_BLOCK_DWORD_LENGTH\t\t448 /* Num of dwords in range */\n#define E1000_HI_COMMAND_TIMEOUT\t\t500 /* Process HI cmd limit */\n#define E1000_HI_FW_BASE_ADDRESS\t\t0x10000\n#define E1000_HI_FW_MAX_LENGTH\t\t\t(64 * 1024) /* Num of bytes */\n#define E1000_HI_FW_BLOCK_DWORD_LENGTH\t\t256 /* Num of DWORDs per page */\n#define E1000_HICR_MEMORY_BASE_EN\t\t0x200 /* MB Enable bit - RO */\n#define E1000_HICR_EN\t\t\t0x01 /* Enable bit - RO */\n/* Driver sets this bit when done to put command in RAM */\n#define E1000_HICR_C\t\t\t0x02\n#define E1000_HICR_SV\t\t\t0x04 /* Status Validity */\n#define E1000_HICR_FW_RESET_ENABLE\t0x40\n#define E1000_HICR_FW_RESET\t\t0x80\n\n/* Intel(R) Active Management Technology signature */\n#define E1000_IAMT_SIGNATURE\t\t0x544D4149\n\n#endif\n" }, { "path": "drivers/net/e1000/base/e1000_mbx.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"e1000_mbx.h\"\n\n/**\n * e1000_null_mbx_check_for_flag - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_null_mbx_check_for_flag(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t\t\t u16 E1000_UNUSEDARG mbx_id)\n{\n\tDEBUGFUNC(\"e1000_null_mbx_check_flag\");\n\tUNREFERENCED_2PARAMETER(hw, mbx_id);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_mbx_transact - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_null_mbx_transact(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t\t u32 E1000_UNUSEDARG *msg,\n\t\t\t\t u16 E1000_UNUSEDARG size,\n\t\t\t\t u16 E1000_UNUSEDARG mbx_id)\n{\n\tDEBUGFUNC(\"e1000_null_mbx_rw_msg\");\n\tUNREFERENCED_4PARAMETER(hw, msg, size, mbx_id);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_mbx - Reads a message from the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to read\n *\n * returns SUCCESS if it successfully read message from buffer\n **/\ns32 e1000_read_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_read_mbx\");\n\n\t/* limit read to size of mailbox */\n\tif (size > mbx->size)\n\t\tsize = mbx->size;\n\n\tif (mbx->ops.read)\n\t\tret_val = mbx->ops.read(hw, msg, size, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_mbx - Write a message to the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully copied message into the buffer\n **/\ns32 e1000_write_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_write_mbx\");\n\n\tif (size > mbx->size)\n\t\tret_val = -E1000_ERR_MBX;\n\n\telse if (mbx->ops.write)\n\t\tret_val = mbx->ops.write(hw, msg, size, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_msg - checks to see if someone sent us mail\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the Status bit was found or else ERR_MBX\n **/\ns32 e1000_check_for_msg(struct e1000_hw *hw, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_check_for_msg\");\n\n\tif (mbx->ops.check_for_msg)\n\t\tret_val = mbx->ops.check_for_msg(hw, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_ack - checks to see if someone sent us ACK\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the Status bit was found or else ERR_MBX\n **/\ns32 e1000_check_for_ack(struct e1000_hw *hw, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_check_for_ack\");\n\n\tif (mbx->ops.check_for_ack)\n\t\tret_val = mbx->ops.check_for_ack(hw, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_rst - checks to see if other side has reset\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the Status bit was found or else ERR_MBX\n **/\ns32 e1000_check_for_rst(struct e1000_hw *hw, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_check_for_rst\");\n\n\tif (mbx->ops.check_for_rst)\n\t\tret_val = mbx->ops.check_for_rst(hw, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_poll_for_msg - Wait for message notification\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully received a message notification\n **/\nSTATIC s32 e1000_poll_for_msg(struct e1000_hw *hw, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tint countdown = mbx->timeout;\n\n\tDEBUGFUNC(\"e1000_poll_for_msg\");\n\n\tif (!countdown || !mbx->ops.check_for_msg)\n\t\tgoto out;\n\n\twhile (countdown && mbx->ops.check_for_msg(hw, mbx_id)) {\n\t\tcountdown--;\n\t\tif (!countdown)\n\t\t\tbreak;\n\t\tusec_delay(mbx->usec_delay);\n\t}\n\n\t/* if we failed, all future posted messages fail until reset */\n\tif (!countdown)\n\t\tmbx->timeout = 0;\nout:\n\treturn countdown ? E1000_SUCCESS : -E1000_ERR_MBX;\n}\n\n/**\n * e1000_poll_for_ack - Wait for message acknowledgement\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully received a message acknowledgement\n **/\nSTATIC s32 e1000_poll_for_ack(struct e1000_hw *hw, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tint countdown = mbx->timeout;\n\n\tDEBUGFUNC(\"e1000_poll_for_ack\");\n\n\tif (!countdown || !mbx->ops.check_for_ack)\n\t\tgoto out;\n\n\twhile (countdown && mbx->ops.check_for_ack(hw, mbx_id)) {\n\t\tcountdown--;\n\t\tif (!countdown)\n\t\t\tbreak;\n\t\tusec_delay(mbx->usec_delay);\n\t}\n\n\t/* if we failed, all future posted messages fail until reset */\n\tif (!countdown)\n\t\tmbx->timeout = 0;\nout:\n\treturn countdown ? E1000_SUCCESS : -E1000_ERR_MBX;\n}\n\n/**\n * e1000_read_posted_mbx - Wait for message notification and receive message\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully received a message notification and\n * copied it into the receive buffer.\n **/\ns32 e1000_read_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_read_posted_mbx\");\n\n\tif (!mbx->ops.read)\n\t\tgoto out;\n\n\tret_val = e1000_poll_for_msg(hw, mbx_id);\n\n\t/* if ack received read message, otherwise we timed out */\n\tif (!ret_val)\n\t\tret_val = mbx->ops.read(hw, msg, size, mbx_id);\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_write_posted_mbx - Write a message to the mailbox, wait for ack\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully copied message into the buffer and\n * received an ack to that message within delay * timeout period\n **/\ns32 e1000_write_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_write_posted_mbx\");\n\n\t/* exit if either we can't write or there isn't a defined timeout */\n\tif (!mbx->ops.write || !mbx->timeout)\n\t\tgoto out;\n\n\t/* send msg */\n\tret_val = mbx->ops.write(hw, msg, size, mbx_id);\n\n\t/* if msg sent wait until we receive an ack */\n\tif (!ret_val)\n\t\tret_val = e1000_poll_for_ack(hw, mbx_id);\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_mbx_ops_generic - Initialize mbx function pointers\n * @hw: pointer to the HW structure\n *\n * Sets the function pointers to no-op functions\n **/\nvoid e1000_init_mbx_ops_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tmbx->ops.init_params = e1000_null_ops_generic;\n\tmbx->ops.read = e1000_null_mbx_transact;\n\tmbx->ops.write = e1000_null_mbx_transact;\n\tmbx->ops.check_for_msg = e1000_null_mbx_check_for_flag;\n\tmbx->ops.check_for_ack = e1000_null_mbx_check_for_flag;\n\tmbx->ops.check_for_rst = e1000_null_mbx_check_for_flag;\n\tmbx->ops.read_posted = e1000_read_posted_mbx;\n\tmbx->ops.write_posted = e1000_write_posted_mbx;\n}\n\n/**\n * e1000_read_v2p_mailbox - read v2p mailbox\n * @hw: pointer to the HW structure\n *\n * This function is used to read the v2p mailbox without losing the read to\n * clear status bits.\n **/\nSTATIC u32 e1000_read_v2p_mailbox(struct e1000_hw *hw)\n{\n\tu32 v2p_mailbox = E1000_READ_REG(hw, E1000_V2PMAILBOX(0));\n\n\tv2p_mailbox |= hw->dev_spec.vf.v2p_mailbox;\n\thw->dev_spec.vf.v2p_mailbox |= v2p_mailbox & E1000_V2PMAILBOX_R2C_BITS;\n\n\treturn v2p_mailbox;\n}\n\n/**\n * e1000_check_for_bit_vf - Determine if a status bit was set\n * @hw: pointer to the HW structure\n * @mask: bitmask for bits to be tested and cleared\n *\n * This function is used to check for the read to clear bits within\n * the V2P mailbox.\n **/\nSTATIC s32 e1000_check_for_bit_vf(struct e1000_hw *hw, u32 mask)\n{\n\tu32 v2p_mailbox = e1000_read_v2p_mailbox(hw);\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tif (v2p_mailbox & mask)\n\t\tret_val = E1000_SUCCESS;\n\n\thw->dev_spec.vf.v2p_mailbox &= ~mask;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_msg_vf - checks to see if the PF has sent mail\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the PF has set the Status bit or else ERR_MBX\n **/\nSTATIC s32 e1000_check_for_msg_vf(struct e1000_hw *hw,\n\t\t\t\t u16 E1000_UNUSEDARG mbx_id)\n{\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tUNREFERENCED_1PARAMETER(mbx_id);\n\tDEBUGFUNC(\"e1000_check_for_msg_vf\");\n\n\tif (!e1000_check_for_bit_vf(hw, E1000_V2PMAILBOX_PFSTS)) {\n\t\tret_val = E1000_SUCCESS;\n\t\thw->mbx.stats.reqs++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_ack_vf - checks to see if the PF has ACK'd\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the PF has set the ACK bit or else ERR_MBX\n **/\nSTATIC s32 e1000_check_for_ack_vf(struct e1000_hw *hw,\n\t\t\t\t u16 E1000_UNUSEDARG mbx_id)\n{\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tUNREFERENCED_1PARAMETER(mbx_id);\n\tDEBUGFUNC(\"e1000_check_for_ack_vf\");\n\n\tif (!e1000_check_for_bit_vf(hw, E1000_V2PMAILBOX_PFACK)) {\n\t\tret_val = E1000_SUCCESS;\n\t\thw->mbx.stats.acks++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_rst_vf - checks to see if the PF has reset\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns true if the PF has set the reset done bit or else false\n **/\nSTATIC s32 e1000_check_for_rst_vf(struct e1000_hw *hw,\n\t\t\t\t u16 E1000_UNUSEDARG mbx_id)\n{\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tUNREFERENCED_1PARAMETER(mbx_id);\n\tDEBUGFUNC(\"e1000_check_for_rst_vf\");\n\n\tif (!e1000_check_for_bit_vf(hw, (E1000_V2PMAILBOX_RSTD |\n\t\t\t\t\t E1000_V2PMAILBOX_RSTI))) {\n\t\tret_val = E1000_SUCCESS;\n\t\thw->mbx.stats.rsts++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_obtain_mbx_lock_vf - obtain mailbox lock\n * @hw: pointer to the HW structure\n *\n * return SUCCESS if we obtained the mailbox lock\n **/\nSTATIC s32 e1000_obtain_mbx_lock_vf(struct e1000_hw *hw)\n{\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_obtain_mbx_lock_vf\");\n\n\t/* Take ownership of the buffer */\n\tE1000_WRITE_REG(hw, E1000_V2PMAILBOX(0), E1000_V2PMAILBOX_VFU);\n\n\t/* reserve mailbox for vf use */\n\tif (e1000_read_v2p_mailbox(hw) & E1000_V2PMAILBOX_VFU)\n\t\tret_val = E1000_SUCCESS;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_mbx_vf - Write a message to the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully copied message into the buffer\n **/\nSTATIC s32 e1000_write_mbx_vf(struct e1000_hw *hw, u32 *msg, u16 size,\n\t\t\t u16 E1000_UNUSEDARG mbx_id)\n{\n\ts32 ret_val;\n\tu16 i;\n\n\tUNREFERENCED_1PARAMETER(mbx_id);\n\n\tDEBUGFUNC(\"e1000_write_mbx_vf\");\n\n\t/* lock the mailbox to prevent pf/vf race condition */\n\tret_val = e1000_obtain_mbx_lock_vf(hw);\n\tif (ret_val)\n\t\tgoto out_no_write;\n\n\t/* flush msg and acks as we are overwriting the message buffer */\n\te1000_check_for_msg_vf(hw, 0);\n\te1000_check_for_ack_vf(hw, 0);\n\n\t/* copy the caller specified message to the mailbox memory buffer */\n\tfor (i = 0; i < size; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VMBMEM(0), i, msg[i]);\n\n\t/* update stats */\n\thw->mbx.stats.msgs_tx++;\n\n\t/* Drop VFU and interrupt the PF to tell it a message has been sent */\n\tE1000_WRITE_REG(hw, E1000_V2PMAILBOX(0), E1000_V2PMAILBOX_REQ);\n\nout_no_write:\n\treturn ret_val;\n}\n\n/**\n * e1000_read_mbx_vf - Reads a message from the inbox intended for vf\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to read\n *\n * returns SUCCESS if it successfully read message from buffer\n **/\nSTATIC s32 e1000_read_mbx_vf(struct e1000_hw *hw, u32 *msg, u16 size,\n\t\t\t u16 E1000_UNUSEDARG mbx_id)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_read_mbx_vf\");\n\tUNREFERENCED_1PARAMETER(mbx_id);\n\n\t/* lock the mailbox to prevent pf/vf race condition */\n\tret_val = e1000_obtain_mbx_lock_vf(hw);\n\tif (ret_val)\n\t\tgoto out_no_read;\n\n\t/* copy the message from the mailbox memory buffer */\n\tfor (i = 0; i < size; i++)\n\t\tmsg[i] = E1000_READ_REG_ARRAY(hw, E1000_VMBMEM(0), i);\n\n\t/* Acknowledge receipt and release mailbox, then we're done */\n\tE1000_WRITE_REG(hw, E1000_V2PMAILBOX(0), E1000_V2PMAILBOX_ACK);\n\n\t/* update stats */\n\thw->mbx.stats.msgs_rx++;\n\nout_no_read:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_mbx_params_vf - set initial values for vf mailbox\n * @hw: pointer to the HW structure\n *\n * Initializes the hw->mbx struct to correct values for vf mailbox\n */\ns32 e1000_init_mbx_params_vf(struct e1000_hw *hw)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\n\t/* start mailbox as timed out and let the reset_hw call set the timeout\n\t * value to begin communications */\n\tmbx->timeout = 0;\n\tmbx->usec_delay = E1000_VF_MBX_INIT_DELAY;\n\n\tmbx->size = E1000_VFMAILBOX_SIZE;\n\n\tmbx->ops.read = e1000_read_mbx_vf;\n\tmbx->ops.write = e1000_write_mbx_vf;\n\tmbx->ops.read_posted = e1000_read_posted_mbx;\n\tmbx->ops.write_posted = e1000_write_posted_mbx;\n\tmbx->ops.check_for_msg = e1000_check_for_msg_vf;\n\tmbx->ops.check_for_ack = e1000_check_for_ack_vf;\n\tmbx->ops.check_for_rst = e1000_check_for_rst_vf;\n\n\tmbx->stats.msgs_tx = 0;\n\tmbx->stats.msgs_rx = 0;\n\tmbx->stats.reqs = 0;\n\tmbx->stats.acks = 0;\n\tmbx->stats.rsts = 0;\n\n\treturn E1000_SUCCESS;\n}\n\nSTATIC s32 e1000_check_for_bit_pf(struct e1000_hw *hw, u32 mask)\n{\n\tu32 mbvficr = E1000_READ_REG(hw, E1000_MBVFICR);\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tif (mbvficr & mask) {\n\t\tret_val = E1000_SUCCESS;\n\t\tE1000_WRITE_REG(hw, E1000_MBVFICR, mask);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_msg_pf - checks to see if the VF has sent mail\n * @hw: pointer to the HW structure\n * @vf_number: the VF index\n *\n * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n **/\nSTATIC s32 e1000_check_for_msg_pf(struct e1000_hw *hw, u16 vf_number)\n{\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_check_for_msg_pf\");\n\n\tif (!e1000_check_for_bit_pf(hw, E1000_MBVFICR_VFREQ_VF1 << vf_number)) {\n\t\tret_val = E1000_SUCCESS;\n\t\thw->mbx.stats.reqs++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_ack_pf - checks to see if the VF has ACKed\n * @hw: pointer to the HW structure\n * @vf_number: the VF index\n *\n * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n **/\nSTATIC s32 e1000_check_for_ack_pf(struct e1000_hw *hw, u16 vf_number)\n{\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_check_for_ack_pf\");\n\n\tif (!e1000_check_for_bit_pf(hw, E1000_MBVFICR_VFACK_VF1 << vf_number)) {\n\t\tret_val = E1000_SUCCESS;\n\t\thw->mbx.stats.acks++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_rst_pf - checks to see if the VF has reset\n * @hw: pointer to the HW structure\n * @vf_number: the VF index\n *\n * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n **/\nSTATIC s32 e1000_check_for_rst_pf(struct e1000_hw *hw, u16 vf_number)\n{\n\tu32 vflre = E1000_READ_REG(hw, E1000_VFLRE);\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_check_for_rst_pf\");\n\n\tif (vflre & (1 << vf_number)) {\n\t\tret_val = E1000_SUCCESS;\n\t\tE1000_WRITE_REG(hw, E1000_VFLRE, (1 << vf_number));\n\t\thw->mbx.stats.rsts++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_obtain_mbx_lock_pf - obtain mailbox lock\n * @hw: pointer to the HW structure\n * @vf_number: the VF index\n *\n * return SUCCESS if we obtained the mailbox lock\n **/\nSTATIC s32 e1000_obtain_mbx_lock_pf(struct e1000_hw *hw, u16 vf_number)\n{\n\ts32 ret_val = -E1000_ERR_MBX;\n\tu32 p2v_mailbox;\n\n\tDEBUGFUNC(\"e1000_obtain_mbx_lock_pf\");\n\n\t/* Take ownership of the buffer */\n\tE1000_WRITE_REG(hw, E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_PFU);\n\n\t/* reserve mailbox for vf use */\n\tp2v_mailbox = E1000_READ_REG(hw, E1000_P2VMAILBOX(vf_number));\n\tif (p2v_mailbox & E1000_P2VMAILBOX_PFU)\n\t\tret_val = E1000_SUCCESS;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_mbx_pf - Places a message in the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @vf_number: the VF index\n *\n * returns SUCCESS if it successfully copied message into the buffer\n **/\nSTATIC s32 e1000_write_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size,\n\t\t\t u16 vf_number)\n{\n\ts32 ret_val;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_write_mbx_pf\");\n\n\t/* lock the mailbox to prevent pf/vf race condition */\n\tret_val = e1000_obtain_mbx_lock_pf(hw, vf_number);\n\tif (ret_val)\n\t\tgoto out_no_write;\n\n\t/* flush msg and acks as we are overwriting the message buffer */\n\te1000_check_for_msg_pf(hw, vf_number);\n\te1000_check_for_ack_pf(hw, vf_number);\n\n\t/* copy the caller specified message to the mailbox memory buffer */\n\tfor (i = 0; i < size; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VMBMEM(vf_number), i, msg[i]);\n\n\t/* Interrupt VF to tell it a message has been sent and release buffer*/\n\tE1000_WRITE_REG(hw, E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS);\n\n\t/* update stats */\n\thw->mbx.stats.msgs_tx++;\n\nout_no_write:\n\treturn ret_val;\n\n}\n\n/**\n * e1000_read_mbx_pf - Read a message from the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @vf_number: the VF index\n *\n * This function copies a message from the mailbox buffer to the caller's\n * memory buffer. The presumption is that the caller knows that there was\n * a message due to a VF request so no polling for message is needed.\n **/\nSTATIC s32 e1000_read_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size,\n\t\t\t u16 vf_number)\n{\n\ts32 ret_val;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_read_mbx_pf\");\n\n\t/* lock the mailbox to prevent pf/vf race condition */\n\tret_val = e1000_obtain_mbx_lock_pf(hw, vf_number);\n\tif (ret_val)\n\t\tgoto out_no_read;\n\n\t/* copy the message to the mailbox memory buffer */\n\tfor (i = 0; i < size; i++)\n\t\tmsg[i] = E1000_READ_REG_ARRAY(hw, E1000_VMBMEM(vf_number), i);\n\n\t/* Acknowledge the message and release buffer */\n\tE1000_WRITE_REG(hw, E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK);\n\n\t/* update stats */\n\thw->mbx.stats.msgs_rx++;\n\nout_no_read:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_mbx_params_pf - set initial values for pf mailbox\n * @hw: pointer to the HW structure\n *\n * Initializes the hw->mbx struct to correct values for pf mailbox\n */\ns32 e1000_init_mbx_params_pf(struct e1000_hw *hw)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82576:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\tmbx->timeout = 0;\n\t\tmbx->usec_delay = 0;\n\n\t\tmbx->size = E1000_VFMAILBOX_SIZE;\n\n\t\tmbx->ops.read = e1000_read_mbx_pf;\n\t\tmbx->ops.write = e1000_write_mbx_pf;\n\t\tmbx->ops.read_posted = e1000_read_posted_mbx;\n\t\tmbx->ops.write_posted = e1000_write_posted_mbx;\n\t\tmbx->ops.check_for_msg = e1000_check_for_msg_pf;\n\t\tmbx->ops.check_for_ack = e1000_check_for_ack_pf;\n\t\tmbx->ops.check_for_rst = e1000_check_for_rst_pf;\n\n\t\tmbx->stats.msgs_tx = 0;\n\t\tmbx->stats.msgs_rx = 0;\n\t\tmbx->stats.reqs = 0;\n\t\tmbx->stats.acks = 0;\n\t\tmbx->stats.rsts = 0;\n\tdefault:\n\t\treturn E1000_SUCCESS;\n\t}\n}\n\n" }, { "path": "drivers/net/e1000/base/e1000_mbx.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_MBX_H_\n#define _E1000_MBX_H_\n\n#include \"e1000_api.h\"\n\n/* Define mailbox register bits */\n#define E1000_V2PMAILBOX_REQ\t0x00000001 /* Request for PF Ready bit */\n#define E1000_V2PMAILBOX_ACK\t0x00000002 /* Ack PF message received */\n#define E1000_V2PMAILBOX_VFU\t0x00000004 /* VF owns the mailbox buffer */\n#define E1000_V2PMAILBOX_PFU\t0x00000008 /* PF owns the mailbox buffer */\n#define E1000_V2PMAILBOX_PFSTS\t0x00000010 /* PF wrote a message in the MB */\n#define E1000_V2PMAILBOX_PFACK\t0x00000020 /* PF ack the previous VF msg */\n#define E1000_V2PMAILBOX_RSTI\t0x00000040 /* PF has reset indication */\n#define E1000_V2PMAILBOX_RSTD\t0x00000080 /* PF has indicated reset done */\n#define E1000_V2PMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */\n\n#define E1000_P2VMAILBOX_STS\t0x00000001 /* Initiate message send to VF */\n#define E1000_P2VMAILBOX_ACK\t0x00000002 /* Ack message recv'd from VF */\n#define E1000_P2VMAILBOX_VFU\t0x00000004 /* VF owns the mailbox buffer */\n#define E1000_P2VMAILBOX_PFU\t0x00000008 /* PF owns the mailbox buffer */\n#define E1000_P2VMAILBOX_RVFU\t0x00000010 /* Reset VFU - used when VF stuck */\n\n#define E1000_MBVFICR_VFREQ_MASK 0x000000FF /* bits for VF messages */\n#define E1000_MBVFICR_VFREQ_VF1\t0x00000001 /* bit for VF 1 message */\n#define E1000_MBVFICR_VFACK_MASK 0x00FF0000 /* bits for VF acks */\n#define E1000_MBVFICR_VFACK_VF1\t0x00010000 /* bit for VF 1 ack */\n\n#define E1000_VFMAILBOX_SIZE\t16 /* 16 32 bit words - 64 bytes */\n\n/* If it's a E1000_VF_* msg then it originates in the VF and is sent to the\n * PF. The reverse is true if it is E1000_PF_*.\n * Message ACK's are the value or'd with 0xF0000000\n */\n/* Msgs below or'd with this are the ACK */\n#define E1000_VT_MSGTYPE_ACK\t0x80000000\n/* Msgs below or'd with this are the NACK */\n#define E1000_VT_MSGTYPE_NACK\t0x40000000\n/* Indicates that VF is still clear to send requests */\n#define E1000_VT_MSGTYPE_CTS\t0x20000000\n#define E1000_VT_MSGINFO_SHIFT\t16\n/* bits 23:16 are used for extra info for certain messages */\n#define E1000_VT_MSGINFO_MASK\t(0xFF << E1000_VT_MSGINFO_SHIFT)\n\n#define E1000_VF_RESET\t\t\t0x01 /* VF requests reset */\n#define E1000_VF_SET_MAC_ADDR\t\t0x02 /* VF requests to set MAC addr */\n#define E1000_VF_SET_MULTICAST\t\t0x03 /* VF requests to set MC addr */\n#define E1000_VF_SET_MULTICAST_COUNT_MASK (0x1F << E1000_VT_MSGINFO_SHIFT)\n#define E1000_VF_SET_MULTICAST_OVERFLOW\t(0x80 << E1000_VT_MSGINFO_SHIFT)\n#define E1000_VF_SET_VLAN\t\t0x04 /* VF requests to set VLAN */\n#define E1000_VF_SET_VLAN_ADD\t\t(0x01 << E1000_VT_MSGINFO_SHIFT)\n#define E1000_VF_SET_LPE\t\t0x05 /* reqs to set VMOLR.LPE */\n#define E1000_VF_SET_PROMISC\t\t0x06 /* reqs to clear VMOLR.ROPE/MPME*/\n#define E1000_VF_SET_PROMISC_UNICAST\t(0x01 << E1000_VT_MSGINFO_SHIFT)\n#define E1000_VF_SET_PROMISC_MULTICAST\t(0x02 << E1000_VT_MSGINFO_SHIFT)\n\n#define E1000_PF_CONTROL_MSG\t\t0x0100 /* PF control message */\n\n#define E1000_VF_MBX_INIT_TIMEOUT\t2000 /* number of retries on mailbox */\n#define E1000_VF_MBX_INIT_DELAY\t\t500 /* microseconds between retries */\n\ns32 e1000_read_mbx(struct e1000_hw *, u32 *, u16, u16);\ns32 e1000_write_mbx(struct e1000_hw *, u32 *, u16, u16);\ns32 e1000_read_posted_mbx(struct e1000_hw *, u32 *, u16, u16);\ns32 e1000_write_posted_mbx(struct e1000_hw *, u32 *, u16, u16);\ns32 e1000_check_for_msg(struct e1000_hw *, u16);\ns32 e1000_check_for_ack(struct e1000_hw *, u16);\ns32 e1000_check_for_rst(struct e1000_hw *, u16);\nvoid e1000_init_mbx_ops_generic(struct e1000_hw *hw);\ns32 e1000_init_mbx_params_vf(struct e1000_hw *);\ns32 e1000_init_mbx_params_pf(struct e1000_hw *);\n\n#endif /* _E1000_MBX_H_ */\n" }, { "path": "drivers/net/e1000/base/e1000_nvm.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"e1000_api.h\"\n\nSTATIC void e1000_reload_nvm_generic(struct e1000_hw *hw);\n\n/**\n * e1000_init_nvm_ops_generic - Initialize NVM function pointers\n * @hw: pointer to the HW structure\n *\n * Setups up the function pointers to no-op functions\n **/\nvoid e1000_init_nvm_ops_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tDEBUGFUNC(\"e1000_init_nvm_ops_generic\");\n\n\t/* Initialize function pointers */\n\tnvm->ops.init_params = e1000_null_ops_generic;\n\tnvm->ops.acquire = e1000_null_ops_generic;\n\tnvm->ops.read = e1000_null_read_nvm;\n\tnvm->ops.release = e1000_null_nvm_generic;\n\tnvm->ops.reload = e1000_reload_nvm_generic;\n\tnvm->ops.update = e1000_null_ops_generic;\n\tnvm->ops.valid_led_default = e1000_null_led_default;\n\tnvm->ops.validate = e1000_null_ops_generic;\n\tnvm->ops.write = e1000_null_write_nvm;\n}\n\n/**\n * e1000_null_nvm_read - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\tu16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,\n\t\t\tu16 E1000_UNUSEDARG *c)\n{\n\tDEBUGFUNC(\"e1000_null_read_nvm\");\n\tUNREFERENCED_4PARAMETER(hw, a, b, c);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_nvm_generic - No-op function, return void\n * @hw: pointer to the HW structure\n **/\nvoid e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_null_nvm_generic\");\n\tUNREFERENCED_1PARAMETER(hw);\n\treturn;\n}\n\n/**\n * e1000_null_led_default - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u16 E1000_UNUSEDARG *data)\n{\n\tDEBUGFUNC(\"e1000_null_led_default\");\n\tUNREFERENCED_2PARAMETER(hw, data);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_write_nvm - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,\n\t\t\t u16 E1000_UNUSEDARG *c)\n{\n\tDEBUGFUNC(\"e1000_null_write_nvm\");\n\tUNREFERENCED_4PARAMETER(hw, a, b, c);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_raise_eec_clk - Raise EEPROM clock\n * @hw: pointer to the HW structure\n * @eecd: pointer to the EEPROM\n *\n * Enable/Raise the EEPROM clock bit.\n **/\nSTATIC void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)\n{\n\t*eecd = *eecd | E1000_EECD_SK;\n\tE1000_WRITE_REG(hw, E1000_EECD, *eecd);\n\tE1000_WRITE_FLUSH(hw);\n\tusec_delay(hw->nvm.delay_usec);\n}\n\n/**\n * e1000_lower_eec_clk - Lower EEPROM clock\n * @hw: pointer to the HW structure\n * @eecd: pointer to the EEPROM\n *\n * Clear/Lower the EEPROM clock bit.\n **/\nSTATIC void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)\n{\n\t*eecd = *eecd & ~E1000_EECD_SK;\n\tE1000_WRITE_REG(hw, E1000_EECD, *eecd);\n\tE1000_WRITE_FLUSH(hw);\n\tusec_delay(hw->nvm.delay_usec);\n}\n\n/**\n * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM\n * @hw: pointer to the HW structure\n * @data: data to send to the EEPROM\n * @count: number of bits to shift out\n *\n * We need to shift 'count' bits out to the EEPROM. So, the value in the\n * \"data\" parameter will be shifted out to the EEPROM one bit at a time.\n * In order to do this, \"data\" must be broken down into bits.\n **/\nSTATIC void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\tu32 mask;\n\n\tDEBUGFUNC(\"e1000_shift_out_eec_bits\");\n\n\tmask = 0x01 << (count - 1);\n\tif (nvm->type == e1000_nvm_eeprom_microwire)\n\t\teecd &= ~E1000_EECD_DO;\n\telse\n\tif (nvm->type == e1000_nvm_eeprom_spi)\n\t\teecd |= E1000_EECD_DO;\n\n\tdo {\n\t\teecd &= ~E1000_EECD_DI;\n\n\t\tif (data & mask)\n\t\t\teecd |= E1000_EECD_DI;\n\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tE1000_WRITE_FLUSH(hw);\n\n\t\tusec_delay(nvm->delay_usec);\n\n\t\te1000_raise_eec_clk(hw, &eecd);\n\t\te1000_lower_eec_clk(hw, &eecd);\n\n\t\tmask >>= 1;\n\t} while (mask);\n\n\teecd &= ~E1000_EECD_DI;\n\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n}\n\n/**\n * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM\n * @hw: pointer to the HW structure\n * @count: number of bits to shift in\n *\n * In order to read a register from the EEPROM, we need to shift 'count' bits\n * in from the EEPROM. Bits are \"shifted in\" by raising the clock input to\n * the EEPROM (setting the SK bit), and then reading the value of the data out\n * \"DO\" bit. During this \"shifting in\" process the data in \"DI\" bit should\n * always be clear.\n **/\nSTATIC u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)\n{\n\tu32 eecd;\n\tu32 i;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_shift_in_eec_bits\");\n\n\teecd = E1000_READ_REG(hw, E1000_EECD);\n\n\teecd &= ~(E1000_EECD_DO | E1000_EECD_DI);\n\tdata = 0;\n\n\tfor (i = 0; i < count; i++) {\n\t\tdata <<= 1;\n\t\te1000_raise_eec_clk(hw, &eecd);\n\n\t\teecd = E1000_READ_REG(hw, E1000_EECD);\n\n\t\teecd &= ~E1000_EECD_DI;\n\t\tif (eecd & E1000_EECD_DO)\n\t\t\tdata |= 1;\n\n\t\te1000_lower_eec_clk(hw, &eecd);\n\t}\n\n\treturn data;\n}\n\n/**\n * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion\n * @hw: pointer to the HW structure\n * @ee_reg: EEPROM flag for polling\n *\n * Polls the EEPROM status bit for either read or write completion based\n * upon the value of 'ee_reg'.\n **/\ns32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)\n{\n\tu32 attempts = 100000;\n\tu32 i, reg = 0;\n\n\tDEBUGFUNC(\"e1000_poll_eerd_eewr_done\");\n\n\tfor (i = 0; i < attempts; i++) {\n\t\tif (ee_reg == E1000_NVM_POLL_READ)\n\t\t\treg = E1000_READ_REG(hw, E1000_EERD);\n\t\telse\n\t\t\treg = E1000_READ_REG(hw, E1000_EEWR);\n\n\t\tif (reg & E1000_NVM_RW_REG_DONE)\n\t\t\treturn E1000_SUCCESS;\n\n\t\tusec_delay(5);\n\t}\n\n\treturn -E1000_ERR_NVM;\n}\n\n/**\n * e1000_acquire_nvm_generic - Generic request for access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Set the EEPROM access request bit and wait for EEPROM access grant bit.\n * Return successful if access grant bit set, else clear the request for\n * EEPROM access and return -E1000_ERR_NVM (-1).\n **/\ns32 e1000_acquire_nvm_generic(struct e1000_hw *hw)\n{\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\ts32 timeout = E1000_NVM_GRANT_ATTEMPTS;\n\n\tDEBUGFUNC(\"e1000_acquire_nvm_generic\");\n\n\tE1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);\n\teecd = E1000_READ_REG(hw, E1000_EECD);\n\n\twhile (timeout) {\n\t\tif (eecd & E1000_EECD_GNT)\n\t\t\tbreak;\n\t\tusec_delay(5);\n\t\teecd = E1000_READ_REG(hw, E1000_EECD);\n\t\ttimeout--;\n\t}\n\n\tif (!timeout) {\n\t\teecd &= ~E1000_EECD_REQ;\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tDEBUGOUT(\"Could not acquire NVM grant\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_standby_nvm - Return EEPROM to standby state\n * @hw: pointer to the HW structure\n *\n * Return the EEPROM to a standby state.\n **/\nSTATIC void e1000_standby_nvm(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\n\tDEBUGFUNC(\"e1000_standby_nvm\");\n\n\tif (nvm->type == e1000_nvm_eeprom_microwire) {\n\t\teecd &= ~(E1000_EECD_CS | E1000_EECD_SK);\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tusec_delay(nvm->delay_usec);\n\n\t\te1000_raise_eec_clk(hw, &eecd);\n\n\t\t/* Select EEPROM */\n\t\teecd |= E1000_EECD_CS;\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tusec_delay(nvm->delay_usec);\n\n\t\te1000_lower_eec_clk(hw, &eecd);\n\t} else if (nvm->type == e1000_nvm_eeprom_spi) {\n\t\t/* Toggle CS to flush commands */\n\t\teecd |= E1000_EECD_CS;\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tusec_delay(nvm->delay_usec);\n\t\teecd &= ~E1000_EECD_CS;\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tusec_delay(nvm->delay_usec);\n\t}\n}\n\n/**\n * e1000_stop_nvm - Terminate EEPROM command\n * @hw: pointer to the HW structure\n *\n * Terminates the current command by inverting the EEPROM's chip select pin.\n **/\nvoid e1000_stop_nvm(struct e1000_hw *hw)\n{\n\tu32 eecd;\n\n\tDEBUGFUNC(\"e1000_stop_nvm\");\n\n\teecd = E1000_READ_REG(hw, E1000_EECD);\n\tif (hw->nvm.type == e1000_nvm_eeprom_spi) {\n\t\t/* Pull CS high */\n\t\teecd |= E1000_EECD_CS;\n\t\te1000_lower_eec_clk(hw, &eecd);\n\t} else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {\n\t\t/* CS on Microwire is active-high */\n\t\teecd &= ~(E1000_EECD_CS | E1000_EECD_DI);\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\te1000_raise_eec_clk(hw, &eecd);\n\t\te1000_lower_eec_clk(hw, &eecd);\n\t}\n}\n\n/**\n * e1000_release_nvm_generic - Release exclusive access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Stop any current commands to the EEPROM and clear the EEPROM request bit.\n **/\nvoid e1000_release_nvm_generic(struct e1000_hw *hw)\n{\n\tu32 eecd;\n\n\tDEBUGFUNC(\"e1000_release_nvm_generic\");\n\n\te1000_stop_nvm(hw);\n\n\teecd = E1000_READ_REG(hw, E1000_EECD);\n\teecd &= ~E1000_EECD_REQ;\n\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n}\n\n/**\n * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write\n * @hw: pointer to the HW structure\n *\n * Setups the EEPROM for reading and writing.\n **/\nSTATIC s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\tu8 spi_stat_reg;\n\n\tDEBUGFUNC(\"e1000_ready_nvm_eeprom\");\n\n\tif (nvm->type == e1000_nvm_eeprom_microwire) {\n\t\t/* Clear SK and DI */\n\t\teecd &= ~(E1000_EECD_DI | E1000_EECD_SK);\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\t/* Set CS */\n\t\teecd |= E1000_EECD_CS;\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t} else if (nvm->type == e1000_nvm_eeprom_spi) {\n\t\tu16 timeout = NVM_MAX_RETRY_SPI;\n\n\t\t/* Clear SK and CS */\n\t\teecd &= ~(E1000_EECD_CS | E1000_EECD_SK);\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tusec_delay(1);\n\n\t\t/* Read \"Status Register\" repeatedly until the LSB is cleared.\n\t\t * The EEPROM will signal that the command has been completed\n\t\t * by clearing bit 0 of the internal status register. If it's\n\t\t * not cleared within 'timeout', then error out.\n\t\t */\n\t\twhile (timeout) {\n\t\t\te1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,\n\t\t\t\t\t\t hw->nvm.opcode_bits);\n\t\t\tspi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);\n\t\t\tif (!(spi_stat_reg & NVM_STATUS_RDY_SPI))\n\t\t\t\tbreak;\n\n\t\t\tusec_delay(5);\n\t\t\te1000_standby_nvm(hw);\n\t\t\ttimeout--;\n\t\t}\n\n\t\tif (!timeout) {\n\t\t\tDEBUGOUT(\"SPI NVM Status error\\n\");\n\t\t\treturn -E1000_ERR_NVM;\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_nvm_spi - Read EEPROM's using SPI\n * @hw: pointer to the HW structure\n * @offset: offset of word in the EEPROM to read\n * @words: number of words to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM.\n **/\ns32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 i = 0;\n\ts32 ret_val;\n\tu16 word_in;\n\tu8 read_opcode = NVM_READ_OPCODE_SPI;\n\n\tDEBUGFUNC(\"e1000_read_nvm_spi\");\n\n\t/* A check for invalid values: offset too large, too many words,\n\t * and not enough words.\n\t */\n\tif ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\tret_val = nvm->ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_ready_nvm_eeprom(hw);\n\tif (ret_val)\n\t\tgoto release;\n\n\te1000_standby_nvm(hw);\n\n\tif ((nvm->address_bits == 8) && (offset >= 128))\n\t\tread_opcode |= NVM_A8_OPCODE_SPI;\n\n\t/* Send the READ command (opcode + addr) */\n\te1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);\n\te1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);\n\n\t/* Read the data. SPI NVMs increment the address with each byte\n\t * read and will roll over if reading beyond the end. This allows\n\t * us to read the whole NVM from any offset\n\t */\n\tfor (i = 0; i < words; i++) {\n\t\tword_in = e1000_shift_in_eec_bits(hw, 16);\n\t\tdata[i] = (word_in >> 8) | (word_in << 8);\n\t}\n\nrelease:\n\tnvm->ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_nvm_microwire - Reads EEPROM's using microwire\n * @hw: pointer to the HW structure\n * @offset: offset of word in the EEPROM to read\n * @words: number of words to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM.\n **/\ns32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t u16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 i = 0;\n\ts32 ret_val;\n\tu8 read_opcode = NVM_READ_OPCODE_MICROWIRE;\n\n\tDEBUGFUNC(\"e1000_read_nvm_microwire\");\n\n\t/* A check for invalid values: offset too large, too many words,\n\t * and not enough words.\n\t */\n\tif ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\tret_val = nvm->ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_ready_nvm_eeprom(hw);\n\tif (ret_val)\n\t\tgoto release;\n\n\tfor (i = 0; i < words; i++) {\n\t\t/* Send the READ command (opcode + addr) */\n\t\te1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);\n\t\te1000_shift_out_eec_bits(hw, (u16)(offset + i),\n\t\t\t\t\tnvm->address_bits);\n\n\t\t/* Read the data. For microwire, each word requires the\n\t\t * overhead of setup and tear-down.\n\t\t */\n\t\tdata[i] = e1000_shift_in_eec_bits(hw, 16);\n\t\te1000_standby_nvm(hw);\n\t}\n\nrelease:\n\tnvm->ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_nvm_eerd - Reads EEPROM using EERD register\n * @hw: pointer to the HW structure\n * @offset: offset of word in the EEPROM to read\n * @words: number of words to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM using the EERD register.\n **/\ns32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 i, eerd = 0;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_read_nvm_eerd\");\n\n\t/* A check for invalid values: offset too large, too many words,\n\t * too many words for the offset, and not enough words.\n\t */\n\tif ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\tfor (i = 0; i < words; i++) {\n\t\teerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +\n\t\t E1000_NVM_RW_REG_START;\n\n\t\tE1000_WRITE_REG(hw, E1000_EERD, eerd);\n\t\tret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);\n\t\tif (ret_val)\n\t\t\tbreak;\n\n\t\tdata[i] = (E1000_READ_REG(hw, E1000_EERD) >>\n\t\t\t E1000_NVM_RW_REG_DATA);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_nvm_spi - Write to EEPROM using SPI\n * @hw: pointer to the HW structure\n * @offset: offset within the EEPROM to be written to\n * @words: number of words to write\n * @data: 16 bit word(s) to be written to the EEPROM\n *\n * Writes data to EEPROM at offset using SPI interface.\n *\n * If e1000_update_nvm_checksum is not called after this function , the\n * EEPROM will most likely contain an invalid checksum.\n **/\ns32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\ts32 ret_val = -E1000_ERR_NVM;\n\tu16 widx = 0;\n\n\tDEBUGFUNC(\"e1000_write_nvm_spi\");\n\n\t/* A check for invalid values: offset too large, too many words,\n\t * and not enough words.\n\t */\n\tif ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\twhile (widx < words) {\n\t\tu8 write_opcode = NVM_WRITE_OPCODE_SPI;\n\n\t\tret_val = nvm->ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = e1000_ready_nvm_eeprom(hw);\n\t\tif (ret_val) {\n\t\t\tnvm->ops.release(hw);\n\t\t\treturn ret_val;\n\t\t}\n\n\t\te1000_standby_nvm(hw);\n\n\t\t/* Send the WRITE ENABLE command (8 bit opcode) */\n\t\te1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,\n\t\t\t\t\t nvm->opcode_bits);\n\n\t\te1000_standby_nvm(hw);\n\n\t\t/* Some SPI eeproms use the 8th address bit embedded in the\n\t\t * opcode\n\t\t */\n\t\tif ((nvm->address_bits == 8) && (offset >= 128))\n\t\t\twrite_opcode |= NVM_A8_OPCODE_SPI;\n\n\t\t/* Send the Write command (8-bit opcode + addr) */\n\t\te1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);\n\t\te1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),\n\t\t\t\t\t nvm->address_bits);\n\n\t\t/* Loop to allow for up to whole page write of eeprom */\n\t\twhile (widx < words) {\n\t\t\tu16 word_out = data[widx];\n\t\t\tword_out = (word_out >> 8) | (word_out << 8);\n\t\t\te1000_shift_out_eec_bits(hw, word_out, 16);\n\t\t\twidx++;\n\n\t\t\tif ((((offset + widx) * 2) % nvm->page_size) == 0) {\n\t\t\t\te1000_standby_nvm(hw);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tmsec_delay(10);\n\t\tnvm->ops.release(hw);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_nvm_microwire - Writes EEPROM using microwire\n * @hw: pointer to the HW structure\n * @offset: offset within the EEPROM to be written to\n * @words: number of words to write\n * @data: 16 bit word(s) to be written to the EEPROM\n *\n * Writes data to EEPROM at offset using microwire interface.\n *\n * If e1000_update_nvm_checksum is not called after this function , the\n * EEPROM will most likely contain an invalid checksum.\n **/\ns32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t u16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\ts32 ret_val;\n\tu32 eecd;\n\tu16 words_written = 0;\n\tu16 widx = 0;\n\n\tDEBUGFUNC(\"e1000_write_nvm_microwire\");\n\n\t/* A check for invalid values: offset too large, too many words,\n\t * and not enough words.\n\t */\n\tif ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\tret_val = nvm->ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_ready_nvm_eeprom(hw);\n\tif (ret_val)\n\t\tgoto release;\n\n\te1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,\n\t\t\t\t (u16)(nvm->opcode_bits + 2));\n\n\te1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));\n\n\te1000_standby_nvm(hw);\n\n\twhile (words_written < words) {\n\t\te1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,\n\t\t\t\t\t nvm->opcode_bits);\n\n\t\te1000_shift_out_eec_bits(hw, (u16)(offset + words_written),\n\t\t\t\t\t nvm->address_bits);\n\n\t\te1000_shift_out_eec_bits(hw, data[words_written], 16);\n\n\t\te1000_standby_nvm(hw);\n\n\t\tfor (widx = 0; widx < 200; widx++) {\n\t\t\teecd = E1000_READ_REG(hw, E1000_EECD);\n\t\t\tif (eecd & E1000_EECD_DO)\n\t\t\t\tbreak;\n\t\t\tusec_delay(50);\n\t\t}\n\n\t\tif (widx == 200) {\n\t\t\tDEBUGOUT(\"NVM Write did not complete\\n\");\n\t\t\tret_val = -E1000_ERR_NVM;\n\t\t\tgoto release;\n\t\t}\n\n\t\te1000_standby_nvm(hw);\n\n\t\twords_written++;\n\t}\n\n\te1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,\n\t\t\t\t (u16)(nvm->opcode_bits + 2));\n\n\te1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));\n\nrelease:\n\tnvm->ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_pba_string_generic - Read device part number\n * @hw: pointer to the HW structure\n * @pba_num: pointer to device part number\n * @pba_num_size: size of part number buffer\n *\n * Reads the product board assembly (PBA) number from the EEPROM and stores\n * the value in pba_num.\n **/\ns32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,\n\t\t\t\t u32 pba_num_size)\n{\n\ts32 ret_val;\n\tu16 nvm_data;\n\tu16 pba_ptr;\n\tu16 offset;\n\tu16 length;\n\n\tDEBUGFUNC(\"e1000_read_pba_string_generic\");\n\n\tif ((hw->mac.type >= e1000_i210) &&\n\t !e1000_get_flash_presence_i210(hw)) {\n\t\tDEBUGOUT(\"Flashless no PBA string\\n\");\n\t\treturn -E1000_ERR_NVM_PBA_SECTION;\n\t}\n\n\tif (pba_num == NULL) {\n\t\tDEBUGOUT(\"PBA string buffer was null\\n\");\n\t\treturn -E1000_ERR_INVALID_ARGUMENT;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\t/* if nvm_data is not ptr guard the PBA must be in legacy format which\n\t * means pba_ptr is actually our second data word for the PBA number\n\t * and we can decode it into an ascii string\n\t */\n\tif (nvm_data != NVM_PBA_PTR_GUARD) {\n\t\tDEBUGOUT(\"NVM PBA number is not stored as string\\n\");\n\n\t\t/* make sure callers buffer is big enough to store the PBA */\n\t\tif (pba_num_size < E1000_PBANUM_LENGTH) {\n\t\t\tDEBUGOUT(\"PBA string buffer too small\\n\");\n\t\t\treturn E1000_ERR_NO_SPACE;\n\t\t}\n\n\t\t/* extract hex string from data and pba_ptr */\n\t\tpba_num[0] = (nvm_data >> 12) & 0xF;\n\t\tpba_num[1] = (nvm_data >> 8) & 0xF;\n\t\tpba_num[2] = (nvm_data >> 4) & 0xF;\n\t\tpba_num[3] = nvm_data & 0xF;\n\t\tpba_num[4] = (pba_ptr >> 12) & 0xF;\n\t\tpba_num[5] = (pba_ptr >> 8) & 0xF;\n\t\tpba_num[6] = '-';\n\t\tpba_num[7] = 0;\n\t\tpba_num[8] = (pba_ptr >> 4) & 0xF;\n\t\tpba_num[9] = pba_ptr & 0xF;\n\n\t\t/* put a null character on the end of our string */\n\t\tpba_num[10] = '\\0';\n\n\t\t/* switch all the data but the '-' to hex char */\n\t\tfor (offset = 0; offset < 10; offset++) {\n\t\t\tif (pba_num[offset] < 0xA)\n\t\t\t\tpba_num[offset] += '0';\n\t\t\telse if (pba_num[offset] < 0x10)\n\t\t\t\tpba_num[offset] += 'A' - 0xA;\n\t\t}\n\n\t\treturn E1000_SUCCESS;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif (length == 0xFFFF || length == 0) {\n\t\tDEBUGOUT(\"NVM PBA number section invalid length\\n\");\n\t\treturn -E1000_ERR_NVM_PBA_SECTION;\n\t}\n\t/* check if pba_num buffer is big enough */\n\tif (pba_num_size < (((u32)length * 2) - 1)) {\n\t\tDEBUGOUT(\"PBA string buffer too small\\n\");\n\t\treturn -E1000_ERR_NO_SPACE;\n\t}\n\n\t/* trim pba length from start of string */\n\tpba_ptr++;\n\tlength--;\n\n\tfor (offset = 0; offset < length; offset++) {\n\t\tret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t\tpba_num[offset * 2] = (u8)(nvm_data >> 8);\n\t\tpba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);\n\t}\n\tpba_num[offset * 2] = '\\0';\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_pba_length_generic - Read device part number length\n * @hw: pointer to the HW structure\n * @pba_num_size: size of part number buffer\n *\n * Reads the product board assembly (PBA) number length from the EEPROM and\n * stores the value in pba_num_size.\n **/\ns32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)\n{\n\ts32 ret_val;\n\tu16 nvm_data;\n\tu16 pba_ptr;\n\tu16 length;\n\n\tDEBUGFUNC(\"e1000_read_pba_length_generic\");\n\n\tif (pba_num_size == NULL) {\n\t\tDEBUGOUT(\"PBA buffer size was null\\n\");\n\t\treturn -E1000_ERR_INVALID_ARGUMENT;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\t /* if data is not ptr guard the PBA must be in legacy format */\n\tif (nvm_data != NVM_PBA_PTR_GUARD) {\n\t\t*pba_num_size = E1000_PBANUM_LENGTH;\n\t\treturn E1000_SUCCESS;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif (length == 0xFFFF || length == 0) {\n\t\tDEBUGOUT(\"NVM PBA number section invalid length\\n\");\n\t\treturn -E1000_ERR_NVM_PBA_SECTION;\n\t}\n\n\t/* Convert from length in u16 values to u8 chars, add 1 for NULL,\n\t * and subtract 2 because length field is included in length.\n\t */\n\t*pba_num_size = ((u32)length * 2) - 1;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_pba_num_generic - Read device part number\n * @hw: pointer to the HW structure\n * @pba_num: pointer to device part number\n *\n * Reads the product board assembly (PBA) number from the EEPROM and stores\n * the value in pba_num.\n **/\ns32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)\n{\n\ts32 ret_val;\n\tu16 nvm_data;\n\n\tDEBUGFUNC(\"e1000_read_pba_num_generic\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t} else if (nvm_data == NVM_PBA_PTR_GUARD) {\n\t\tDEBUGOUT(\"NVM Not Supported\\n\");\n\t\treturn -E1000_NOT_IMPLEMENTED;\n\t}\n\t*pba_num = (u32)(nvm_data << 16);\n\n\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\t*pba_num |= nvm_data;\n\n\treturn E1000_SUCCESS;\n}\n\n\n/**\n * e1000_read_pba_raw\n * @hw: pointer to the HW structure\n * @eeprom_buf: optional pointer to EEPROM image\n * @eeprom_buf_size: size of EEPROM image in words\n * @max_pba_block_size: PBA block size limit\n * @pba: pointer to output PBA structure\n *\n * Reads PBA from EEPROM image when eeprom_buf is not NULL.\n * Reads PBA from physical EEPROM device when eeprom_buf is NULL.\n *\n **/\ns32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,\n\t\t u32 eeprom_buf_size, u16 max_pba_block_size,\n\t\t struct e1000_pba *pba)\n{\n\ts32 ret_val;\n\tu16 pba_block_size;\n\n\tif (pba == NULL)\n\t\treturn -E1000_ERR_PARAM;\n\n\tif (eeprom_buf == NULL) {\n\t\tret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2,\n\t\t\t\t\t &pba->word[0]);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\tif (eeprom_buf_size > NVM_PBA_OFFSET_1) {\n\t\t\tpba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];\n\t\t\tpba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];\n\t\t} else {\n\t\t\treturn -E1000_ERR_PARAM;\n\t\t}\n\t}\n\n\tif (pba->word[0] == NVM_PBA_PTR_GUARD) {\n\t\tif (pba->pba_block == NULL)\n\t\t\treturn -E1000_ERR_PARAM;\n\n\t\tret_val = e1000_get_pba_block_size(hw, eeprom_buf,\n\t\t\t\t\t\t eeprom_buf_size,\n\t\t\t\t\t\t &pba_block_size);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (pba_block_size > max_pba_block_size)\n\t\t\treturn -E1000_ERR_PARAM;\n\n\t\tif (eeprom_buf == NULL) {\n\t\t\tret_val = e1000_read_nvm(hw, pba->word[1],\n\t\t\t\t\t\t pba_block_size,\n\t\t\t\t\t\t pba->pba_block);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t} else {\n\t\t\tif (eeprom_buf_size > (u32)(pba->word[1] +\n\t\t\t\t\t pba_block_size)) {\n\t\t\t\tmemcpy(pba->pba_block,\n\t\t\t\t &eeprom_buf[pba->word[1]],\n\t\t\t\t pba_block_size * sizeof(u16));\n\t\t\t} else {\n\t\t\t\treturn -E1000_ERR_PARAM;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_pba_raw\n * @hw: pointer to the HW structure\n * @eeprom_buf: optional pointer to EEPROM image\n * @eeprom_buf_size: size of EEPROM image in words\n * @pba: pointer to PBA structure\n *\n * Writes PBA to EEPROM image when eeprom_buf is not NULL.\n * Writes PBA to physical EEPROM device when eeprom_buf is NULL.\n *\n **/\ns32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,\n\t\t\tu32 eeprom_buf_size, struct e1000_pba *pba)\n{\n\ts32 ret_val;\n\n\tif (pba == NULL)\n\t\treturn -E1000_ERR_PARAM;\n\n\tif (eeprom_buf == NULL) {\n\t\tret_val = e1000_write_nvm(hw, NVM_PBA_OFFSET_0, 2,\n\t\t\t\t\t &pba->word[0]);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\tif (eeprom_buf_size > NVM_PBA_OFFSET_1) {\n\t\t\teeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];\n\t\t\teeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];\n\t\t} else {\n\t\t\treturn -E1000_ERR_PARAM;\n\t\t}\n\t}\n\n\tif (pba->word[0] == NVM_PBA_PTR_GUARD) {\n\t\tif (pba->pba_block == NULL)\n\t\t\treturn -E1000_ERR_PARAM;\n\n\t\tif (eeprom_buf == NULL) {\n\t\t\tret_val = e1000_write_nvm(hw, pba->word[1],\n\t\t\t\t\t\t pba->pba_block[0],\n\t\t\t\t\t\t pba->pba_block);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t} else {\n\t\t\tif (eeprom_buf_size > (u32)(pba->word[1] +\n\t\t\t\t\t pba->pba_block[0])) {\n\t\t\t\tmemcpy(&eeprom_buf[pba->word[1]],\n\t\t\t\t pba->pba_block,\n\t\t\t\t pba->pba_block[0] * sizeof(u16));\n\t\t\t} else {\n\t\t\t\treturn -E1000_ERR_PARAM;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_pba_block_size\n * @hw: pointer to the HW structure\n * @eeprom_buf: optional pointer to EEPROM image\n * @eeprom_buf_size: size of EEPROM image in words\n * @pba_data_size: pointer to output variable\n *\n * Returns the size of the PBA block in words. Function operates on EEPROM\n * image if the eeprom_buf pointer is not NULL otherwise it accesses physical\n * EEPROM device.\n *\n **/\ns32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,\n\t\t\t u32 eeprom_buf_size, u16 *pba_block_size)\n{\n\ts32 ret_val;\n\tu16 pba_word[2];\n\tu16 length;\n\n\tDEBUGFUNC(\"e1000_get_pba_block_size\");\n\n\tif (eeprom_buf == NULL) {\n\t\tret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\tif (eeprom_buf_size > NVM_PBA_OFFSET_1) {\n\t\t\tpba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];\n\t\t\tpba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];\n\t\t} else {\n\t\t\treturn -E1000_ERR_PARAM;\n\t\t}\n\t}\n\n\tif (pba_word[0] == NVM_PBA_PTR_GUARD) {\n\t\tif (eeprom_buf == NULL) {\n\t\t\tret_val = e1000_read_nvm(hw, pba_word[1] + 0, 1,\n\t\t\t\t\t\t &length);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t} else {\n\t\t\tif (eeprom_buf_size > pba_word[1])\n\t\t\t\tlength = eeprom_buf[pba_word[1] + 0];\n\t\t\telse\n\t\t\t\treturn -E1000_ERR_PARAM;\n\t\t}\n\n\t\tif (length == 0xFFFF || length == 0)\n\t\t\treturn -E1000_ERR_NVM_PBA_SECTION;\n\t} else {\n\t\t/* PBA number in legacy format, there is no PBA Block. */\n\t\tlength = 0;\n\t}\n\n\tif (pba_block_size != NULL)\n\t\t*pba_block_size = length;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_mac_addr_generic - Read device MAC address\n * @hw: pointer to the HW structure\n *\n * Reads the device MAC address from the EEPROM and stores the value.\n * Since devices with two ports use the same EEPROM, we increment the\n * last bit in the MAC address for the second port.\n **/\ns32 e1000_read_mac_addr_generic(struct e1000_hw *hw)\n{\n\tu32 rar_high;\n\tu32 rar_low;\n\tu16 i;\n\n\trar_high = E1000_READ_REG(hw, E1000_RAH(0));\n\trar_low = E1000_READ_REG(hw, E1000_RAL(0));\n\n\tfor (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)\n\t\thw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));\n\n\tfor (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)\n\t\thw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));\n\n\tfor (i = 0; i < ETH_ADDR_LEN; i++)\n\t\thw->mac.addr[i] = hw->mac.perm_addr[i];\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Calculates the EEPROM checksum by reading/adding each word of the EEPROM\n * and then verifies that the sum of the EEPROM is equal to 0xBABA.\n **/\ns32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 checksum = 0;\n\tu16 i, nvm_data;\n\n\tDEBUGFUNC(\"e1000_validate_nvm_checksum_generic\");\n\n\tfor (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {\n\t\tret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t\tchecksum += nvm_data;\n\t}\n\n\tif (checksum != (u16) NVM_SUM) {\n\t\tDEBUGOUT(\"NVM Checksum Invalid\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_update_nvm_checksum_generic - Update EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Updates the EEPROM checksum by reading/adding each word of the EEPROM\n * up to the checksum. Then calculates the EEPROM checksum and writes the\n * value to the EEPROM.\n **/\ns32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 checksum = 0;\n\tu16 i, nvm_data;\n\n\tDEBUGFUNC(\"e1000_update_nvm_checksum\");\n\n\tfor (i = 0; i < NVM_CHECKSUM_REG; i++) {\n\t\tret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error while updating checksum.\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t\tchecksum += nvm_data;\n\t}\n\tchecksum = (u16) NVM_SUM - checksum;\n\tret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);\n\tif (ret_val)\n\t\tDEBUGOUT(\"NVM Write Error while updating checksum.\\n\");\n\n\treturn ret_val;\n}\n\n/**\n * e1000_reload_nvm_generic - Reloads EEPROM\n * @hw: pointer to the HW structure\n *\n * Reloads the EEPROM by setting the \"Reinitialize from EEPROM\" bit in the\n * extended control register.\n **/\nSTATIC void e1000_reload_nvm_generic(struct e1000_hw *hw)\n{\n\tu32 ctrl_ext;\n\n\tDEBUGFUNC(\"e1000_reload_nvm_generic\");\n\n\tusec_delay(10);\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tctrl_ext |= E1000_CTRL_EXT_EE_RST;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * e1000_get_fw_version - Get firmware version information\n * @hw: pointer to the HW structure\n * @fw_vers: pointer to output version structure\n *\n * unsupported/not present features return 0 in version structure\n **/\nvoid e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)\n{\n\tu16 eeprom_verh, eeprom_verl, etrack_test, fw_version;\n\tu8 q, hval, rem, result;\n\tu16 comb_verh, comb_verl, comb_offset;\n\n\tmemset(fw_vers, 0, sizeof(struct e1000_fw_version));\n\n\t/* basic eeprom version numbers, bits used vary by part and by tool\n\t * used to create the nvm images */\n\t/* Check which data format we have */\n\tswitch (hw->mac.type) {\n\tcase e1000_i211:\n\t\te1000_read_invm_version(hw, fw_vers);\n\t\treturn;\n\tcase e1000_82575:\n\tcase e1000_82576:\n\tcase e1000_82580:\n\t\thw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);\n\t\t/* Use this format, unless EETRACK ID exists,\n\t\t * then use alternate format\n\t\t */\n\t\tif ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {\n\t\t\thw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);\n\t\t\tfw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)\n\t\t\t\t\t >> NVM_MAJOR_SHIFT;\n\t\t\tfw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)\n\t\t\t\t\t >> NVM_MINOR_SHIFT;\n\t\t\tfw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);\n\t\t\tgoto etrack_id;\n\t\t}\n\t\tbreak;\n\tcase e1000_i210:\n\t\tif (!(e1000_get_flash_presence_i210(hw))) {\n\t\t\te1000_read_invm_version(hw, fw_vers);\n\t\t\treturn;\n\t\t}\n\t\t/* fall through */\n\tcase e1000_i350:\n\t\thw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);\n\t\t/* find combo image version */\n\t\thw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);\n\t\tif ((comb_offset != 0x0) &&\n\t\t (comb_offset != NVM_VER_INVALID)) {\n\n\t\t\thw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset\n\t\t\t\t\t + 1), 1, &comb_verh);\n\t\t\thw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),\n\t\t\t\t\t 1, &comb_verl);\n\n\t\t\t/* get Option Rom version if it exists and is valid */\n\t\t\tif ((comb_verh && comb_verl) &&\n\t\t\t ((comb_verh != NVM_VER_INVALID) &&\n\t\t\t (comb_verl != NVM_VER_INVALID))) {\n\n\t\t\t\tfw_vers->or_valid = true;\n\t\t\t\tfw_vers->or_major =\n\t\t\t\t\tcomb_verl >> NVM_COMB_VER_SHFT;\n\t\t\t\tfw_vers->or_build =\n\t\t\t\t\t(comb_verl << NVM_COMB_VER_SHFT)\n\t\t\t\t\t| (comb_verh >> NVM_COMB_VER_SHFT);\n\t\t\t\tfw_vers->or_patch =\n\t\t\t\t\tcomb_verh & NVM_COMB_VER_MASK;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\thw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);\n\t\treturn;\n\t}\n\thw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);\n\tfw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)\n\t\t\t >> NVM_MAJOR_SHIFT;\n\n\t/* check for old style version format in newer images*/\n\tif ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {\n\t\teeprom_verl = (fw_version & NVM_COMB_VER_MASK);\n\t} else {\n\t\teeprom_verl = (fw_version & NVM_MINOR_MASK)\n\t\t\t\t>> NVM_MINOR_SHIFT;\n\t}\n\t/* Convert minor value to hex before assigning to output struct\n\t * Val to be converted will not be higher than 99, per tool output\n\t */\n\tq = eeprom_verl / NVM_HEX_CONV;\n\thval = q * NVM_HEX_TENS;\n\trem = eeprom_verl % NVM_HEX_CONV;\n\tresult = hval + rem;\n\tfw_vers->eep_minor = result;\n\netrack_id:\n\tif ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {\n\t\thw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);\n\t\thw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);\n\t\tfw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)\n\t\t\t| eeprom_verl;\n\t}\n\treturn;\n}\n\n\n" }, { "path": "drivers/net/e1000/base/e1000_nvm.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_NVM_H_\n#define _E1000_NVM_H_\n\nstruct e1000_pba {\n\tu16 word[2];\n\tu16 *pba_block;\n};\n\nstruct e1000_fw_version {\n\tu32 etrack_id;\n\tu16 eep_major;\n\tu16 eep_minor;\n\tu16 eep_build;\n\n\tu8 invm_major;\n\tu8 invm_minor;\n\tu8 invm_img_type;\n\n\tbool or_valid;\n\tu16 or_major;\n\tu16 or_build;\n\tu16 or_patch;\n};\n\n\nvoid e1000_init_nvm_ops_generic(struct e1000_hw *hw);\ns32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c);\nvoid e1000_null_nvm_generic(struct e1000_hw *hw);\ns32 e1000_null_led_default(struct e1000_hw *hw, u16 *data);\ns32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c);\ns32 e1000_acquire_nvm_generic(struct e1000_hw *hw);\n\ns32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);\ns32 e1000_read_mac_addr_generic(struct e1000_hw *hw);\ns32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num);\ns32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,\n\t\t\t\t u32 pba_num_size);\ns32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size);\ns32 e1000_read_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,\n\t\t u32 eeprom_buf_size, u16 max_pba_block_size,\n\t\t struct e1000_pba *pba);\ns32 e1000_write_pba_raw(struct e1000_hw *hw, u16 *eeprom_buf,\n\t\t\tu32 eeprom_buf_size, struct e1000_pba *pba);\ns32 e1000_get_pba_block_size(struct e1000_hw *hw, u16 *eeprom_buf,\n\t\t\t u32 eeprom_buf_size, u16 *pba_block_size);\ns32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);\ns32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset,\n\t\t\t u16 words, u16 *data);\ns32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t u16 *data);\ns32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data);\ns32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw);\ns32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset,\n\t\t\t u16 words, u16 *data);\ns32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t u16 *data);\ns32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw);\nvoid e1000_stop_nvm(struct e1000_hw *hw);\nvoid e1000_release_nvm_generic(struct e1000_hw *hw);\nvoid e1000_get_fw_version(struct e1000_hw *hw,\n\t\t\t struct e1000_fw_version *fw_vers);\n\n#define E1000_STM_OPCODE\t0xDB00\n\n#endif\n" }, { "path": "drivers/net/e1000/base/e1000_osdep.c", "content": "/******************************************************************************\n\n Copyright (c) 2001-2014, Intel Corporation \n All rights reserved.\n \n Redistribution and use in source and binary forms, with or without \n modification, are permitted provided that the following conditions are met:\n \n 1. Redistributions of source code must retain the above copyright notice, \n this list of conditions and the following disclaimer.\n \n 2. Redistributions in binary form must reproduce the above copyright \n notice, this list of conditions and the following disclaimer in the \n documentation and/or other materials provided with the distribution.\n \n 3. Neither the name of the Intel Corporation nor the names of its \n contributors may be used to endorse or promote products derived from \n this software without specific prior written permission.\n \n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE \n ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE \n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR \n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF \n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n\n******************************************************************************/\n/*$FreeBSD$*/\n\n#include \"e1000_api.h\"\n\n/*\n * NOTE: the following routines using the e1000 \n * \tnaming style are provided to the shared\n *\tcode but are OS specific\n */\n\nvoid\ne1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)\n{\n\treturn;\n}\n\nvoid\ne1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)\n{\n\t*value = 0;\n\treturn;\n}\n\nvoid\ne1000_pci_set_mwi(struct e1000_hw *hw)\n{\n}\n\nvoid\ne1000_pci_clear_mwi(struct e1000_hw *hw)\n{\n}\n\n\n/*\n * Read the PCI Express capabilities\n */\nint32_t\ne1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)\n{\n\treturn E1000_NOT_IMPLEMENTED;\n}\n\n/*\n * Write the PCI Express capabilities\n */\nint32_t\ne1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)\n{\n\treturn E1000_NOT_IMPLEMENTED;\n}\n" }, { "path": "drivers/net/e1000/base/e1000_osdep.h", "content": "/******************************************************************************\n\n Copyright (c) 2001-2014, Intel Corporation \n All rights reserved.\n \n Redistribution and use in source and binary forms, with or without \n modification, are permitted provided that the following conditions are met:\n \n 1. Redistributions of source code must retain the above copyright notice, \n this list of conditions and the following disclaimer.\n \n 2. Redistributions in binary form must reproduce the above copyright \n notice, this list of conditions and the following disclaimer in the \n documentation and/or other materials provided with the distribution.\n \n 3. Neither the name of the Intel Corporation nor the names of its \n contributors may be used to endorse or promote products derived from \n this software without specific prior written permission.\n \n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE \n ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE \n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR \n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF \n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n\n******************************************************************************/\n/*$FreeBSD$*/\n\n#ifndef _E1000_OSDEP_H_\n#define _E1000_OSDEP_H_\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"../e1000_logs.h\"\n\n#define DELAY(x) rte_delay_us(x)\n#define usec_delay(x) DELAY(x)\n#define usec_delay_irq(x) DELAY(x)\n#define msec_delay(x) DELAY(1000*(x))\n#define msec_delay_irq(x) DELAY(1000*(x))\n\n#define DEBUGFUNC(F) DEBUGOUT(F \"\\n\");\n#define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)\n#define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)\n#define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)\n#define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)\n#define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)\n#define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)\n\n#define UNREFERENCED_PARAMETER(_p)\n#define UNREFERENCED_1PARAMETER(_p)\n#define UNREFERENCED_2PARAMETER(_p, _q)\n#define UNREFERENCED_3PARAMETER(_p, _q, _r)\n#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)\n\n#define FALSE\t\t\t0\n#define TRUE\t\t\t1\n\n#define\tCMD_MEM_WRT_INVALIDATE\t0x0010 /* BIT_4 */\n\n/* Mutex used in the shared code */\n#define E1000_MUTEX uintptr_t\n#define E1000_MUTEX_INIT(mutex) (*(mutex) = 0)\n#define E1000_MUTEX_LOCK(mutex) (*(mutex) = 1)\n#define E1000_MUTEX_UNLOCK(mutex) (*(mutex) = 0)\n\ntypedef uint64_t\tu64;\ntypedef uint32_t\tu32;\ntypedef uint16_t\tu16;\ntypedef uint8_t\t\tu8;\ntypedef int64_t\t\ts64;\ntypedef int32_t\t\ts32;\ntypedef int16_t\t\ts16;\ntypedef int8_t\t\ts8;\ntypedef int\t\tbool;\n\n#define __le16\t\tu16\n#define __le32\t\tu32\n#define __le64\t\tu64\n\n#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)\n\n#define E1000_PCI_REG(reg) (*((volatile uint32_t *)(reg)))\n\n#define E1000_PCI_REG_WRITE(reg, value) do { \\\n\tE1000_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \\\n} while (0)\n\n#define E1000_PCI_REG_ADDR(hw, reg) \\\n\t((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))\n\n#define E1000_PCI_REG_ARRAY_ADDR(hw, reg, index) \\\n\tE1000_PCI_REG_ADDR((hw), (reg) + ((index) << 2))\n\nstatic inline uint32_t e1000_read_addr(volatile void* addr)\n{\n\treturn rte_le_to_cpu_32(E1000_PCI_REG(addr));\n}\n\n/* Necessary defines */\n#define E1000_MRQC_ENABLE_MASK 0x00000007\n#define E1000_MRQC_RSS_FIELD_IPV6_EX\t\t0x00080000\n#define E1000_ALL_FULL_DUPLEX ( \\\n ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL)\n\n#define M88E1543_E_PHY_ID 0x01410EA0\n#define NAHUM6LP_HW \n#define ULP_SUPPORT\n\n#define E1000_RCTL_DTYP_MASK\t0x00000C00 /* Descriptor type mask */\n#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000\n\n/* Register READ/WRITE macros */\n\n#define E1000_READ_REG(hw, reg) \\\n\te1000_read_addr(E1000_PCI_REG_ADDR((hw), (reg)))\n\n#define E1000_WRITE_REG(hw, reg, value) \\\n\tE1000_PCI_REG_WRITE(E1000_PCI_REG_ADDR((hw), (reg)), (value))\n\n#define E1000_READ_REG_ARRAY(hw, reg, index) \\\n\tE1000_PCI_REG(E1000_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))\n\n#define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \\\n\tE1000_PCI_REG_WRITE(E1000_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))\n\n#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY\n#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY\n\n#define\tE1000_ACCESS_PANIC(x, hw, reg, value) \\\n\trte_panic(\"%s:%u\\t\" RTE_STR(x) \"(%p, 0x%x, 0x%x)\", \\\n\t\t__FILE__, __LINE__, (hw), (reg), (unsigned int)(value))\n\n/*\n * To be able to do IO write, we need to map IO BAR\n * (bar 2/4 depending on device).\n * Right now mapping multiple BARs is not supported by DPDK.\n * Fortunatelly we need it only for legacy hw support.\n */\n\n#define E1000_WRITE_REG_IO(hw, reg, value) \\\n\tE1000_WRITE_REG(hw, reg, value)\n\n/*\n * Not implemented.\n */\n\n#define E1000_READ_FLASH_REG(hw, reg) \\\n\t(E1000_ACCESS_PANIC(E1000_READ_FLASH_REG, hw, reg, 0), 0)\n\n#define E1000_READ_FLASH_REG16(hw, reg) \\\n\t(E1000_ACCESS_PANIC(E1000_READ_FLASH_REG16, hw, reg, 0), 0)\n\n#define E1000_WRITE_FLASH_REG(hw, reg, value) \\\n\tE1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG, hw, reg, value)\n\n#define E1000_WRITE_FLASH_REG16(hw, reg, value) \\\n\tE1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG16, hw, reg, value)\n\n#define STATIC static\n\n#ifndef ETH_ADDR_LEN\n#define ETH_ADDR_LEN 6\n#endif\n\n#define false FALSE\n#define true TRUE\n\n#endif /* _E1000_OSDEP_H_ */\n" }, { "path": "drivers/net/e1000/base/e1000_phy.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"e1000_api.h\"\n\nSTATIC s32 e1000_wait_autoneg(struct e1000_hw *hw);\nSTATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 *data, bool read, bool page_set);\nSTATIC u32 e1000_get_phy_addr_for_hv_page(u32 page);\nSTATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 *data, bool read);\n\n/* Cable length tables */\nSTATIC const u16 e1000_m88_cable_length_table[] = {\n\t0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };\n#define M88E1000_CABLE_LENGTH_TABLE_SIZE \\\n\t\t(sizeof(e1000_m88_cable_length_table) / \\\n\t\t sizeof(e1000_m88_cable_length_table[0]))\n\nSTATIC const u16 e1000_igp_2_cable_length_table[] = {\n\t0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,\n\t6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,\n\t26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,\n\t44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,\n\t66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,\n\t87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,\n\t100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,\n\t124};\n#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \\\n\t\t(sizeof(e1000_igp_2_cable_length_table) / \\\n\t\t sizeof(e1000_igp_2_cable_length_table[0]))\n\n/**\n * e1000_init_phy_ops_generic - Initialize PHY function pointers\n * @hw: pointer to the HW structure\n *\n * Setups up the function pointers to no-op functions\n **/\nvoid e1000_init_phy_ops_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tDEBUGFUNC(\"e1000_init_phy_ops_generic\");\n\n\t/* Initialize function pointers */\n\tphy->ops.init_params = e1000_null_ops_generic;\n\tphy->ops.acquire = e1000_null_ops_generic;\n\tphy->ops.check_polarity = e1000_null_ops_generic;\n\tphy->ops.check_reset_block = e1000_null_ops_generic;\n\tphy->ops.commit = e1000_null_ops_generic;\n\tphy->ops.force_speed_duplex = e1000_null_ops_generic;\n\tphy->ops.get_cfg_done = e1000_null_ops_generic;\n\tphy->ops.get_cable_length = e1000_null_ops_generic;\n\tphy->ops.get_info = e1000_null_ops_generic;\n\tphy->ops.set_page = e1000_null_set_page;\n\tphy->ops.read_reg = e1000_null_read_reg;\n\tphy->ops.read_reg_locked = e1000_null_read_reg;\n\tphy->ops.read_reg_page = e1000_null_read_reg;\n\tphy->ops.release = e1000_null_phy_generic;\n\tphy->ops.reset = e1000_null_ops_generic;\n\tphy->ops.set_d0_lplu_state = e1000_null_lplu_state;\n\tphy->ops.set_d3_lplu_state = e1000_null_lplu_state;\n\tphy->ops.write_reg = e1000_null_write_reg;\n\tphy->ops.write_reg_locked = e1000_null_write_reg;\n\tphy->ops.write_reg_page = e1000_null_write_reg;\n\tphy->ops.power_up = e1000_null_phy_generic;\n\tphy->ops.power_down = e1000_null_phy_generic;\n\tphy->ops.read_i2c_byte = e1000_read_i2c_byte_null;\n\tphy->ops.write_i2c_byte = e1000_write_i2c_byte_null;\n\tphy->ops.cfg_on_link_up = e1000_null_ops_generic;\n}\n\n/**\n * e1000_null_set_page - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\tu16 E1000_UNUSEDARG data)\n{\n\tDEBUGFUNC(\"e1000_null_set_page\");\n\tUNREFERENCED_2PARAMETER(hw, data);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_read_reg - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\tu32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)\n{\n\tDEBUGFUNC(\"e1000_null_read_reg\");\n\tUNREFERENCED_3PARAMETER(hw, offset, data);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_phy_generic - No-op function, return void\n * @hw: pointer to the HW structure\n **/\nvoid e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_null_phy_generic\");\n\tUNREFERENCED_1PARAMETER(hw);\n\treturn;\n}\n\n/**\n * e1000_null_lplu_state - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t bool E1000_UNUSEDARG active)\n{\n\tDEBUGFUNC(\"e1000_null_lplu_state\");\n\tUNREFERENCED_2PARAMETER(hw, active);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_write_reg - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)\n{\n\tDEBUGFUNC(\"e1000_null_write_reg\");\n\tUNREFERENCED_3PARAMETER(hw, offset, data);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_i2c_byte_null - No-op function, return 0\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @dev_addr: device address\n * @data: data value read\n *\n **/\ns32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u8 E1000_UNUSEDARG byte_offset,\n\t\t\t u8 E1000_UNUSEDARG dev_addr,\n\t\t\t u8 E1000_UNUSEDARG *data)\n{\n\tDEBUGFUNC(\"e1000_read_i2c_byte_null\");\n\tUNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_i2c_byte_null - No-op function, return 0\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @dev_addr: device address\n * @data: data value to write\n *\n **/\ns32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u8 E1000_UNUSEDARG byte_offset,\n\t\t\t u8 E1000_UNUSEDARG dev_addr,\n\t\t\t u8 E1000_UNUSEDARG data)\n{\n\tDEBUGFUNC(\"e1000_write_i2c_byte_null\");\n\tUNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_check_reset_block_generic - Check if PHY reset is blocked\n * @hw: pointer to the HW structure\n *\n * Read the PHY management control register and check whether a PHY reset\n * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise\n * return E1000_BLK_PHY_RESET (12).\n **/\ns32 e1000_check_reset_block_generic(struct e1000_hw *hw)\n{\n\tu32 manc;\n\n\tDEBUGFUNC(\"e1000_check_reset_block\");\n\n\tmanc = E1000_READ_REG(hw, E1000_MANC);\n\n\treturn (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?\n\t E1000_BLK_PHY_RESET : E1000_SUCCESS;\n}\n\n/**\n * e1000_get_phy_id - Retrieve the PHY ID and revision\n * @hw: pointer to the HW structure\n *\n * Reads the PHY registers and stores the PHY ID and possibly the PHY\n * revision in the hardware structure.\n **/\ns32 e1000_get_phy_id(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 phy_id;\n\tu16 retry_count = 0;\n\n\tDEBUGFUNC(\"e1000_get_phy_id\");\n\n\tif (!phy->ops.read_reg)\n\t\treturn E1000_SUCCESS;\n\n\twhile (retry_count < 2) {\n\t\tret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy->id = (u32)(phy_id << 16);\n\t\tusec_delay(20);\n\t\tret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy->id |= (u32)(phy_id & PHY_REVISION_MASK);\n\t\tphy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);\n\n\t\tif (phy->id != 0 && phy->id != PHY_REVISION_MASK)\n\t\t\treturn E1000_SUCCESS;\n\n\t\tretry_count++;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_reset_dsp_generic - Reset PHY DSP\n * @hw: pointer to the HW structure\n *\n * Reset the digital signal processor.\n **/\ns32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_phy_reset_dsp_generic\");\n\n\tif (!hw->phy.ops.write_reg)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);\n}\n\n/**\n * e1000_read_phy_reg_mdic - Read MDI control register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the MDI control register in the PHY at offset and stores the\n * information read to data.\n **/\ns32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tu32 i, mdic = 0;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_mdic\");\n\n\tif (offset > MAX_PHY_REG_ADDRESS) {\n\t\tDEBUGOUT1(\"PHY Address %d is out of range\\n\", offset);\n\t\treturn -E1000_ERR_PARAM;\n\t}\n\n\t/* Set up Op-code, Phy Address, and register offset in the MDI\n\t * Control register. The MAC will take care of interfacing with the\n\t * PHY to retrieve the desired data.\n\t */\n\tmdic = ((offset << E1000_MDIC_REG_SHIFT) |\n\t\t(phy->addr << E1000_MDIC_PHY_SHIFT) |\n\t\t(E1000_MDIC_OP_READ));\n\n\tE1000_WRITE_REG(hw, E1000_MDIC, mdic);\n\n\t/* Poll the ready bit to see if the MDI read completed\n\t * Increasing the time out as testing showed failures with\n\t * the lower time out\n\t */\n\tfor (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {\n\t\tusec_delay_irq(50);\n\t\tmdic = E1000_READ_REG(hw, E1000_MDIC);\n\t\tif (mdic & E1000_MDIC_READY)\n\t\t\tbreak;\n\t}\n\tif (!(mdic & E1000_MDIC_READY)) {\n\t\tDEBUGOUT(\"MDI Read did not complete\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (mdic & E1000_MDIC_ERROR) {\n\t\tDEBUGOUT(\"MDI Error\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {\n\t\tDEBUGOUT2(\"MDI Read offset error - requested %d, returned %d\\n\",\n\t\t\t offset,\n\t\t\t (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);\n\t\treturn -E1000_ERR_PHY;\n\t}\n\t*data = (u16) mdic;\n\n\t/* Allow some time after each MDIC transaction to avoid\n\t * reading duplicate data in the next MDIC transaction.\n\t */\n\tif (hw->mac.type == e1000_pch2lan)\n\t\tusec_delay_irq(100);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_phy_reg_mdic - Write MDI control register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write to register at offset\n *\n * Writes data to MDI control register in the PHY at offset.\n **/\ns32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tu32 i, mdic = 0;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_mdic\");\n\n\tif (offset > MAX_PHY_REG_ADDRESS) {\n\t\tDEBUGOUT1(\"PHY Address %d is out of range\\n\", offset);\n\t\treturn -E1000_ERR_PARAM;\n\t}\n\n\t/* Set up Op-code, Phy Address, and register offset in the MDI\n\t * Control register. The MAC will take care of interfacing with the\n\t * PHY to retrieve the desired data.\n\t */\n\tmdic = (((u32)data) |\n\t\t(offset << E1000_MDIC_REG_SHIFT) |\n\t\t(phy->addr << E1000_MDIC_PHY_SHIFT) |\n\t\t(E1000_MDIC_OP_WRITE));\n\n\tE1000_WRITE_REG(hw, E1000_MDIC, mdic);\n\n\t/* Poll the ready bit to see if the MDI read completed\n\t * Increasing the time out as testing showed failures with\n\t * the lower time out\n\t */\n\tfor (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {\n\t\tusec_delay_irq(50);\n\t\tmdic = E1000_READ_REG(hw, E1000_MDIC);\n\t\tif (mdic & E1000_MDIC_READY)\n\t\t\tbreak;\n\t}\n\tif (!(mdic & E1000_MDIC_READY)) {\n\t\tDEBUGOUT(\"MDI Write did not complete\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (mdic & E1000_MDIC_ERROR) {\n\t\tDEBUGOUT(\"MDI Error\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {\n\t\tDEBUGOUT2(\"MDI Write offset error - requested %d, returned %d\\n\",\n\t\t\t offset,\n\t\t\t (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\t/* Allow some time after each MDIC transaction to avoid\n\t * reading duplicate data in the next MDIC transaction.\n\t */\n\tif (hw->mac.type == e1000_pch2lan)\n\t\tusec_delay_irq(100);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_phy_reg_i2c - Read PHY register using i2c\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the PHY register at offset using the i2c interface and stores the\n * retrieved information in data.\n **/\ns32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tu32 i, i2ccmd = 0;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_i2c\");\n\n\t/* Set up Op-code, Phy Address, and register address in the I2CCMD\n\t * register. The MAC will take care of interfacing with the\n\t * PHY to retrieve the desired data.\n\t */\n\ti2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |\n\t\t (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |\n\t\t (E1000_I2CCMD_OPCODE_READ));\n\n\tE1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);\n\n\t/* Poll the ready bit to see if the I2C read completed */\n\tfor (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {\n\t\tusec_delay(50);\n\t\ti2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);\n\t\tif (i2ccmd & E1000_I2CCMD_READY)\n\t\t\tbreak;\n\t}\n\tif (!(i2ccmd & E1000_I2CCMD_READY)) {\n\t\tDEBUGOUT(\"I2CCMD Read did not complete\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (i2ccmd & E1000_I2CCMD_ERROR) {\n\t\tDEBUGOUT(\"I2CCMD Error bit set\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\t/* Need to byte-swap the 16-bit value. */\n\t*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_phy_reg_i2c - Write PHY register using i2c\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Writes the data to PHY register at the offset using the i2c interface.\n **/\ns32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tu32 i, i2ccmd = 0;\n\tu16 phy_data_swapped;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_i2c\");\n\n\t/* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/\n\tif ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {\n\t\tDEBUGOUT1(\"PHY I2C Address %d is out of range.\\n\",\n\t\t\t hw->phy.addr);\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\t/* Swap the data bytes for the I2C interface */\n\tphy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);\n\n\t/* Set up Op-code, Phy Address, and register address in the I2CCMD\n\t * register. The MAC will take care of interfacing with the\n\t * PHY to retrieve the desired data.\n\t */\n\ti2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |\n\t\t (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |\n\t\t E1000_I2CCMD_OPCODE_WRITE |\n\t\t phy_data_swapped);\n\n\tE1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);\n\n\t/* Poll the ready bit to see if the I2C read completed */\n\tfor (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {\n\t\tusec_delay(50);\n\t\ti2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);\n\t\tif (i2ccmd & E1000_I2CCMD_READY)\n\t\t\tbreak;\n\t}\n\tif (!(i2ccmd & E1000_I2CCMD_READY)) {\n\t\tDEBUGOUT(\"I2CCMD Write did not complete\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (i2ccmd & E1000_I2CCMD_ERROR) {\n\t\tDEBUGOUT(\"I2CCMD Error bit set\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_sfp_data_byte - Reads SFP module data.\n * @hw: pointer to the HW structure\n * @offset: byte location offset to be read\n * @data: read data buffer pointer\n *\n * Reads one byte from SFP module data stored\n * in SFP resided EEPROM memory or SFP diagnostic area.\n * Function should be called with\n * E1000_I2CCMD_SFP_DATA_ADDR() for SFP module database access\n * E1000_I2CCMD_SFP_DIAG_ADDR() for SFP diagnostics parameters\n * access\n **/\ns32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)\n{\n\tu32 i = 0;\n\tu32 i2ccmd = 0;\n\tu32 data_local = 0;\n\n\tDEBUGFUNC(\"e1000_read_sfp_data_byte\");\n\n\tif (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {\n\t\tDEBUGOUT(\"I2CCMD command address exceeds upper limit\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\t/* Set up Op-code, EEPROM Address,in the I2CCMD\n\t * register. The MAC will take care of interfacing with the\n\t * EEPROM to retrieve the desired data.\n\t */\n\ti2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |\n\t\t E1000_I2CCMD_OPCODE_READ);\n\n\tE1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);\n\n\t/* Poll the ready bit to see if the I2C read completed */\n\tfor (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {\n\t\tusec_delay(50);\n\t\tdata_local = E1000_READ_REG(hw, E1000_I2CCMD);\n\t\tif (data_local & E1000_I2CCMD_READY)\n\t\t\tbreak;\n\t}\n\tif (!(data_local & E1000_I2CCMD_READY)) {\n\t\tDEBUGOUT(\"I2CCMD Read did not complete\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (data_local & E1000_I2CCMD_ERROR) {\n\t\tDEBUGOUT(\"I2CCMD Error bit set\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\t*data = (u8) data_local & 0xFF;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_sfp_data_byte - Writes SFP module data.\n * @hw: pointer to the HW structure\n * @offset: byte location offset to write to\n * @data: data to write\n *\n * Writes one byte to SFP module data stored\n * in SFP resided EEPROM memory or SFP diagnostic area.\n * Function should be called with\n * E1000_I2CCMD_SFP_DATA_ADDR() for SFP module database access\n * E1000_I2CCMD_SFP_DIAG_ADDR() for SFP diagnostics parameters\n * access\n **/\ns32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)\n{\n\tu32 i = 0;\n\tu32 i2ccmd = 0;\n\tu32 data_local = 0;\n\n\tDEBUGFUNC(\"e1000_write_sfp_data_byte\");\n\n\tif (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {\n\t\tDEBUGOUT(\"I2CCMD command address exceeds upper limit\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\t/* The programming interface is 16 bits wide\n\t * so we need to read the whole word first\n\t * then update appropriate byte lane and write\n\t * the updated word back.\n\t */\n\t/* Set up Op-code, EEPROM Address,in the I2CCMD\n\t * register. The MAC will take care of interfacing\n\t * with an EEPROM to write the data given.\n\t */\n\ti2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |\n\t\t E1000_I2CCMD_OPCODE_READ);\n\t/* Set a command to read single word */\n\tE1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);\n\tfor (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {\n\t\tusec_delay(50);\n\t\t/* Poll the ready bit to see if lastly\n\t\t * launched I2C operation completed\n\t\t */\n\t\ti2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);\n\t\tif (i2ccmd & E1000_I2CCMD_READY) {\n\t\t\t/* Check if this is READ or WRITE phase */\n\t\t\tif ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==\n\t\t\t E1000_I2CCMD_OPCODE_READ) {\n\t\t\t\t/* Write the selected byte\n\t\t\t\t * lane and update whole word\n\t\t\t\t */\n\t\t\t\tdata_local = i2ccmd & 0xFF00;\n\t\t\t\tdata_local |= data;\n\t\t\t\ti2ccmd = ((offset <<\n\t\t\t\t\tE1000_I2CCMD_REG_ADDR_SHIFT) |\n\t\t\t\t\tE1000_I2CCMD_OPCODE_WRITE | data_local);\n\t\t\t\tE1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);\n\t\t\t} else {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tif (!(i2ccmd & E1000_I2CCMD_READY)) {\n\t\tDEBUGOUT(\"I2CCMD Write did not complete\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (i2ccmd & E1000_I2CCMD_ERROR) {\n\t\tDEBUGOUT(\"I2CCMD Error bit set\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_phy_reg_m88 - Read m88 PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Acquires semaphore, if necessary, then reads the PHY register at offset\n * and storing the retrieved information in data. Release any acquired\n * semaphores before exiting.\n **/\ns32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_m88\");\n\n\tif (!hw->phy.ops.acquire)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t data);\n\n\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_phy_reg_m88 - Write m88 PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Acquires semaphore, if necessary, then writes the data to PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\ns32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_m88\");\n\n\tif (!hw->phy.ops.acquire)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t data);\n\n\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_set_page_igp - Set page as on IGP-like PHY(s)\n * @hw: pointer to the HW structure\n * @page: page to set (shifted left when necessary)\n *\n * Sets PHY page required for PHY register access. Assumes semaphore is\n * already acquired. Note, this function sets phy.addr to 1 so the caller\n * must set it appropriately (if necessary) after this function returns.\n **/\ns32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)\n{\n\tDEBUGFUNC(\"e1000_set_page_igp\");\n\n\tDEBUGOUT1(\"Setting page 0x%x\\n\", page);\n\n\thw->phy.addr = 1;\n\n\treturn e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);\n}\n\n/**\n * __e1000_read_phy_reg_igp - Read igp PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n * @locked: semaphore has already been acquired or not\n *\n * Acquires semaphore, if necessary, then reads the PHY register at offset\n * and stores the retrieved information in data. Release any acquired\n * semaphores before exiting.\n **/\nSTATIC s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,\n\t\t\t\t bool locked)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"__e1000_read_phy_reg_igp\");\n\n\tif (!locked) {\n\t\tif (!hw->phy.ops.acquire)\n\t\t\treturn E1000_SUCCESS;\n\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tif (offset > MAX_PHY_MULTI_PAGE_REG)\n\t\tret_val = e1000_write_phy_reg_mdic(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PAGE_SELECT,\n\t\t\t\t\t\t (u16)offset);\n\tif (!ret_val)\n\t\tret_val = e1000_read_phy_reg_mdic(hw,\n\t\t\t\t\t\t MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t\t data);\n\tif (!locked)\n\t\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_phy_reg_igp - Read igp PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Acquires semaphore then reads the PHY register at offset and stores the\n * retrieved information in data.\n * Release the acquired semaphore before exiting.\n **/\ns32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn __e1000_read_phy_reg_igp(hw, offset, data, false);\n}\n\n/**\n * e1000_read_phy_reg_igp_locked - Read igp PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the PHY register at offset and stores the retrieved information\n * in data. Assumes semaphore already acquired.\n **/\ns32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn __e1000_read_phy_reg_igp(hw, offset, data, true);\n}\n\n/**\n * e1000_write_phy_reg_igp - Write igp PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n * @locked: semaphore has already been acquired or not\n *\n * Acquires semaphore, if necessary, then writes the data to PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\nSTATIC s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,\n\t\t\t\t bool locked)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_igp\");\n\n\tif (!locked) {\n\t\tif (!hw->phy.ops.acquire)\n\t\t\treturn E1000_SUCCESS;\n\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tif (offset > MAX_PHY_MULTI_PAGE_REG)\n\t\tret_val = e1000_write_phy_reg_mdic(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PAGE_SELECT,\n\t\t\t\t\t\t (u16)offset);\n\tif (!ret_val)\n\t\tret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &\n\t\t\t\t\t\t offset,\n\t\t\t\t\t\t data);\n\tif (!locked)\n\t\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_phy_reg_igp - Write igp PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Acquires semaphore then writes the data to PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\ns32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn __e1000_write_phy_reg_igp(hw, offset, data, false);\n}\n\n/**\n * e1000_write_phy_reg_igp_locked - Write igp PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Writes the data to PHY register at the offset.\n * Assumes semaphore already acquired.\n **/\ns32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn __e1000_write_phy_reg_igp(hw, offset, data, true);\n}\n\n/**\n * __e1000_read_kmrn_reg - Read kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n * @locked: semaphore has already been acquired or not\n *\n * Acquires semaphore, if necessary. Then reads the PHY register at offset\n * using the kumeran interface. The information retrieved is stored in data.\n * Release any acquired semaphores before exiting.\n **/\nSTATIC s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,\n\t\t\t\t bool locked)\n{\n\tu32 kmrnctrlsta;\n\n\tDEBUGFUNC(\"__e1000_read_kmrn_reg\");\n\n\tif (!locked) {\n\t\ts32 ret_val = E1000_SUCCESS;\n\n\t\tif (!hw->phy.ops.acquire)\n\t\t\treturn E1000_SUCCESS;\n\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tkmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &\n\t\t E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;\n\tE1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);\n\tE1000_WRITE_FLUSH(hw);\n\n\tusec_delay(2);\n\n\tkmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);\n\t*data = (u16)kmrnctrlsta;\n\n\tif (!locked)\n\t\thw->phy.ops.release(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_kmrn_reg_generic - Read kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Acquires semaphore then reads the PHY register at offset using the\n * kumeran interface. The information retrieved is stored in data.\n * Release the acquired semaphore before exiting.\n **/\ns32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn __e1000_read_kmrn_reg(hw, offset, data, false);\n}\n\n/**\n * e1000_read_kmrn_reg_locked - Read kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the PHY register at offset using the kumeran interface. The\n * information retrieved is stored in data.\n * Assumes semaphore already acquired.\n **/\ns32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn __e1000_read_kmrn_reg(hw, offset, data, true);\n}\n\n/**\n * __e1000_write_kmrn_reg - Write kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n * @locked: semaphore has already been acquired or not\n *\n * Acquires semaphore, if necessary. Then write the data to PHY register\n * at the offset using the kumeran interface. Release any acquired semaphores\n * before exiting.\n **/\nSTATIC s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,\n\t\t\t\t bool locked)\n{\n\tu32 kmrnctrlsta;\n\n\tDEBUGFUNC(\"e1000_write_kmrn_reg_generic\");\n\n\tif (!locked) {\n\t\ts32 ret_val = E1000_SUCCESS;\n\n\t\tif (!hw->phy.ops.acquire)\n\t\t\treturn E1000_SUCCESS;\n\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tkmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &\n\t\t E1000_KMRNCTRLSTA_OFFSET) | data;\n\tE1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);\n\tE1000_WRITE_FLUSH(hw);\n\n\tusec_delay(2);\n\n\tif (!locked)\n\t\thw->phy.ops.release(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_kmrn_reg_generic - Write kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Acquires semaphore then writes the data to the PHY register at the offset\n * using the kumeran interface. Release the acquired semaphore before exiting.\n **/\ns32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn __e1000_write_kmrn_reg(hw, offset, data, false);\n}\n\n/**\n * e1000_write_kmrn_reg_locked - Write kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Write the data to PHY register at the offset using the kumeran interface.\n * Assumes semaphore already acquired.\n **/\ns32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn __e1000_write_kmrn_reg(hw, offset, data, true);\n}\n\n/**\n * e1000_set_master_slave_mode - Setup PHY for Master/slave mode\n * @hw: pointer to the HW structure\n *\n * Sets up Master/slave mode\n **/\nSTATIC s32 e1000_set_master_slave_mode(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 phy_data;\n\n\t/* Resolve Master/Slave mode */\n\tret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* load defaults for future use */\n\thw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?\n\t\t\t\t ((phy_data & CR_1000T_MS_VALUE) ?\n\t\t\t\t e1000_ms_force_master :\n\t\t\t\t e1000_ms_force_slave) : e1000_ms_auto;\n\n\tswitch (hw->phy.ms_type) {\n\tcase e1000_ms_force_master:\n\t\tphy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);\n\t\tbreak;\n\tcase e1000_ms_force_slave:\n\t\tphy_data |= CR_1000T_MS_ENABLE;\n\t\tphy_data &= ~(CR_1000T_MS_VALUE);\n\t\tbreak;\n\tcase e1000_ms_auto:\n\t\tphy_data &= ~CR_1000T_MS_ENABLE;\n\t\t/* fall-through */\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);\n}\n\n/**\n * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link\n * @hw: pointer to the HW structure\n *\n * Sets up Carrier-sense on Transmit and downshift values.\n **/\ns32 e1000_copper_link_setup_82577(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_copper_link_setup_82577\");\n\n\tif (hw->phy.type == e1000_phy_82580) {\n\t\tret_val = hw->phy.ops.reset(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error resetting the PHY.\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\t/* Enable CRS on Tx. This must be set for half-duplex operation. */\n\tret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_data |= I82577_CFG_ASSERT_CRS_ON_TX;\n\n\t/* Enable downshift */\n\tphy_data |= I82577_CFG_ENABLE_DOWNSHIFT;\n\n\tret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Set MDI/MDIX mode */\n\tret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\tphy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;\n\t/* Options:\n\t * 0 - Auto (default)\n\t * 1 - MDI mode\n\t * 2 - MDI-X mode\n\t */\n\tswitch (hw->phy.mdix) {\n\tcase 1:\n\t\tbreak;\n\tcase 2:\n\t\tphy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;\n\t\tbreak;\n\tcase 0:\n\tdefault:\n\t\tphy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;\n\t\tbreak;\n\t}\n\tret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn e1000_set_master_slave_mode(hw);\n}\n\n/**\n * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link\n * @hw: pointer to the HW structure\n *\n * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock\n * and downshift values are set also.\n **/\ns32 e1000_copper_link_setup_m88(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_copper_link_setup_m88\");\n\n\n\t/* Enable CRS on Tx. This must be set for half-duplex operation. */\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* For BM PHY this bit is downshift enable */\n\tif (phy->type != e1000_phy_bm)\n\t\tphy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;\n\n\t/* Options:\n\t * MDI/MDI-X = 0 (default)\n\t * 0 - Auto for all speeds\n\t * 1 - MDI mode\n\t * 2 - MDI-X mode\n\t * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)\n\t */\n\tphy_data &= ~M88E1000_PSCR_AUTO_X_MODE;\n\n\tswitch (phy->mdix) {\n\tcase 1:\n\t\tphy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;\n\t\tbreak;\n\tcase 2:\n\t\tphy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;\n\t\tbreak;\n\tcase 3:\n\t\tphy_data |= M88E1000_PSCR_AUTO_X_1000T;\n\t\tbreak;\n\tcase 0:\n\tdefault:\n\t\tphy_data |= M88E1000_PSCR_AUTO_X_MODE;\n\t\tbreak;\n\t}\n\n\t/* Options:\n\t * disable_polarity_correction = 0 (default)\n\t * Automatic Correction for Reversed Cable Polarity\n\t * 0 - Disabled\n\t * 1 - Enabled\n\t */\n\tphy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;\n\tif (phy->disable_polarity_correction)\n\t\tphy_data |= M88E1000_PSCR_POLARITY_REVERSAL;\n\n\t/* Enable downshift on BM (disabled by default) */\n\tif (phy->type == e1000_phy_bm) {\n\t\t/* For 82574/82583, first disable then enable downshift */\n\t\tif (phy->id == BME1000_E_PHY_ID_R2) {\n\t\t\tphy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;\n\t\t\tret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,\n\t\t\t\t\t\t phy_data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t\t/* Commit the changes. */\n\t\t\tret_val = phy->ops.commit(hw);\n\t\t\tif (ret_val) {\n\t\t\t\tDEBUGOUT(\"Error committing the PHY changes\\n\");\n\t\t\t\treturn ret_val;\n\t\t\t}\n\t\t}\n\n\t\tphy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;\n\t}\n\n\tret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif ((phy->type == e1000_phy_m88) &&\n\t (phy->revision < E1000_REVISION_4) &&\n\t (phy->id != BME1000_E_PHY_ID_R2)) {\n\t\t/* Force TX_CLK in the Extended PHY Specific Control Register\n\t\t * to 25MHz clock.\n\t\t */\n\t\tret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy_data |= M88E1000_EPSCR_TX_CLK_25;\n\n\t\tif ((phy->revision == E1000_REVISION_2) &&\n\t\t (phy->id == M88E1111_I_PHY_ID)) {\n\t\t\t/* 82573L PHY - set the downshift counter to 5x. */\n\t\t\tphy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;\n\t\t\tphy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;\n\t\t} else {\n\t\t\t/* Configure Master and Slave downshift values */\n\t\t\tphy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |\n\t\t\t\t M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);\n\t\t\tphy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |\n\t\t\t\t M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);\n\t\t}\n\t\tret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,\n\t\t\t\t\t phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tif ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {\n\t\t/* Set PHY page 0, register 29 to 0x0003 */\n\t\tret_val = phy->ops.write_reg(hw, 29, 0x0003);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Set PHY page 0, register 30 to 0x0000 */\n\t\tret_val = phy->ops.write_reg(hw, 30, 0x0000);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* Commit the changes. */\n\tret_val = phy->ops.commit(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error committing the PHY changes\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif (phy->type == e1000_phy_82578) {\n\t\tret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* 82578 PHY - set the downshift count to 1x. */\n\t\tphy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;\n\t\tphy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;\n\t\tret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,\n\t\t\t\t\t phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link\n * @hw: pointer to the HW structure\n *\n * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.\n * Also enables and sets the downshift parameters.\n **/\ns32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_copper_link_setup_m88_gen2\");\n\n\n\t/* Enable CRS on Tx. This must be set for half-duplex operation. */\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Options:\n\t * MDI/MDI-X = 0 (default)\n\t * 0 - Auto for all speeds\n\t * 1 - MDI mode\n\t * 2 - MDI-X mode\n\t * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)\n\t */\n\tphy_data &= ~M88E1000_PSCR_AUTO_X_MODE;\n\n\tswitch (phy->mdix) {\n\tcase 1:\n\t\tphy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;\n\t\tbreak;\n\tcase 2:\n\t\tphy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;\n\t\tbreak;\n\tcase 3:\n\t\t/* M88E1112 does not support this mode) */\n\t\tif (phy->id != M88E1112_E_PHY_ID) {\n\t\t\tphy_data |= M88E1000_PSCR_AUTO_X_1000T;\n\t\t\tbreak;\n\t\t}\n\tcase 0:\n\tdefault:\n\t\tphy_data |= M88E1000_PSCR_AUTO_X_MODE;\n\t\tbreak;\n\t}\n\n\t/* Options:\n\t * disable_polarity_correction = 0 (default)\n\t * Automatic Correction for Reversed Cable Polarity\n\t * 0 - Disabled\n\t * 1 - Enabled\n\t */\n\tphy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;\n\tif (phy->disable_polarity_correction)\n\t\tphy_data |= M88E1000_PSCR_POLARITY_REVERSAL;\n\n\t/* Enable downshift and setting it to X6 */\n\tif (phy->id == M88E1543_E_PHY_ID) {\n\t\tphy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;\n\t\tret_val =\n\t\t phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.commit(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error committing the PHY changes\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\tphy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;\n\tphy_data |= I347AT4_PSCR_DOWNSHIFT_6X;\n\tphy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;\n\n\tret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Commit the changes. */\n\tret_val = phy->ops.commit(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error committing the PHY changes\\n\");\n\t\treturn ret_val;\n\t}\n\n\tret_val = e1000_set_master_slave_mode(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_copper_link_setup_igp - Setup igp PHY's for copper link\n * @hw: pointer to the HW structure\n *\n * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for\n * igp PHY's.\n **/\ns32 e1000_copper_link_setup_igp(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_copper_link_setup_igp\");\n\n\n\tret_val = hw->phy.ops.reset(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error resetting the PHY.\\n\");\n\t\treturn ret_val;\n\t}\n\n\t/* Wait 100ms for MAC to configure PHY from NVM settings, to avoid\n\t * timeout issues when LFS is enabled.\n\t */\n\tmsec_delay(100);\n\n\t/* The NVM settings will configure LPLU in D3 for\n\t * non-IGP1 PHYs.\n\t */\n\tif (phy->type == e1000_phy_igp) {\n\t\t/* disable lplu d3 during driver init */\n\t\tret_val = hw->phy.ops.set_d3_lplu_state(hw, false);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error Disabling LPLU D3\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\t/* disable lplu d0 during driver init */\n\tif (hw->phy.ops.set_d0_lplu_state) {\n\t\tret_val = hw->phy.ops.set_d0_lplu_state(hw, false);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error Disabling LPLU D0\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\t/* Configure mdi-mdix settings */\n\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tdata &= ~IGP01E1000_PSCR_AUTO_MDIX;\n\n\tswitch (phy->mdix) {\n\tcase 1:\n\t\tdata &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;\n\t\tbreak;\n\tcase 2:\n\t\tdata |= IGP01E1000_PSCR_FORCE_MDI_MDIX;\n\t\tbreak;\n\tcase 0:\n\tdefault:\n\t\tdata |= IGP01E1000_PSCR_AUTO_MDIX;\n\t\tbreak;\n\t}\n\tret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* set auto-master slave resolution settings */\n\tif (hw->mac.autoneg) {\n\t\t/* when autonegotiation advertisement is only 1000Mbps then we\n\t\t * should disable SmartSpeed and enable Auto MasterSlave\n\t\t * resolution as hardware default.\n\t\t */\n\t\tif (phy->autoneg_advertised == ADVERTISE_1000_FULL) {\n\t\t\t/* Disable SmartSpeed */\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\t/* Set auto Master/Slave resolution process */\n\t\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata &= ~CR_1000T_MS_ENABLE;\n\t\t\tret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t}\n\n\t\tret_val = e1000_set_master_slave_mode(hw);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation\n * @hw: pointer to the HW structure\n *\n * Reads the MII auto-neg advertisement register and/or the 1000T control\n * register and if the PHY is already setup for auto-negotiation, then\n * return successful. Otherwise, setup advertisement and flow control to\n * the appropriate values for the wanted auto-negotiation.\n **/\ns32 e1000_phy_setup_autoneg(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 mii_autoneg_adv_reg;\n\tu16 mii_1000t_ctrl_reg = 0;\n\n\tDEBUGFUNC(\"e1000_phy_setup_autoneg\");\n\n\tphy->autoneg_advertised &= phy->autoneg_mask;\n\n\t/* Read the MII Auto-Neg Advertisement Register (Address 4). */\n\tret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (phy->autoneg_mask & ADVERTISE_1000_FULL) {\n\t\t/* Read the MII 1000Base-T Control Register (Address 9). */\n\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,\n\t\t\t\t\t &mii_1000t_ctrl_reg);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* Need to parse both autoneg_advertised and fc and set up\n\t * the appropriate PHY registers. First we will parse for\n\t * autoneg_advertised software override. Since we can advertise\n\t * a plethora of combinations, we need to check each bit\n\t * individually.\n\t */\n\n\t/* First we clear all the 10/100 mb speed bits in the Auto-Neg\n\t * Advertisement Register (Address 4) and the 1000 mb speed bits in\n\t * the 1000Base-T Control Register (Address 9).\n\t */\n\tmii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |\n\t\t\t\t NWAY_AR_100TX_HD_CAPS |\n\t\t\t\t NWAY_AR_10T_FD_CAPS |\n\t\t\t\t NWAY_AR_10T_HD_CAPS);\n\tmii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);\n\n\tDEBUGOUT1(\"autoneg_advertised %x\\n\", phy->autoneg_advertised);\n\n\t/* Do we want to advertise 10 Mb Half Duplex? */\n\tif (phy->autoneg_advertised & ADVERTISE_10_HALF) {\n\t\tDEBUGOUT(\"Advertise 10mb Half duplex\\n\");\n\t\tmii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;\n\t}\n\n\t/* Do we want to advertise 10 Mb Full Duplex? */\n\tif (phy->autoneg_advertised & ADVERTISE_10_FULL) {\n\t\tDEBUGOUT(\"Advertise 10mb Full duplex\\n\");\n\t\tmii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;\n\t}\n\n\t/* Do we want to advertise 100 Mb Half Duplex? */\n\tif (phy->autoneg_advertised & ADVERTISE_100_HALF) {\n\t\tDEBUGOUT(\"Advertise 100mb Half duplex\\n\");\n\t\tmii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;\n\t}\n\n\t/* Do we want to advertise 100 Mb Full Duplex? */\n\tif (phy->autoneg_advertised & ADVERTISE_100_FULL) {\n\t\tDEBUGOUT(\"Advertise 100mb Full duplex\\n\");\n\t\tmii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;\n\t}\n\n\t/* We do not allow the Phy to advertise 1000 Mb Half Duplex */\n\tif (phy->autoneg_advertised & ADVERTISE_1000_HALF)\n\t\tDEBUGOUT(\"Advertise 1000mb Half duplex request denied!\\n\");\n\n\t/* Do we want to advertise 1000 Mb Full Duplex? */\n\tif (phy->autoneg_advertised & ADVERTISE_1000_FULL) {\n\t\tDEBUGOUT(\"Advertise 1000mb Full duplex\\n\");\n\t\tmii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;\n\t}\n\n\t/* Check for a software override of the flow control settings, and\n\t * setup the PHY advertisement registers accordingly. If\n\t * auto-negotiation is enabled, then software will have to set the\n\t * \"PAUSE\" bits to the correct value in the Auto-Negotiation\n\t * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-\n\t * negotiation.\n\t *\n\t * The possible values of the \"fc\" parameter are:\n\t * 0: Flow control is completely disabled\n\t * 1: Rx flow control is enabled (we can receive pause frames\n\t * but not send pause frames).\n\t * 2: Tx flow control is enabled (we can send pause frames\n\t * but we do not support receiving pause frames).\n\t * 3: Both Rx and Tx flow control (symmetric) are enabled.\n\t * other: No software override. The flow control configuration\n\t * in the EEPROM is used.\n\t */\n\tswitch (hw->fc.current_mode) {\n\tcase e1000_fc_none:\n\t\t/* Flow control (Rx & Tx) is completely disabled by a\n\t\t * software over-ride.\n\t\t */\n\t\tmii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);\n\t\tbreak;\n\tcase e1000_fc_rx_pause:\n\t\t/* Rx Flow control is enabled, and Tx Flow control is\n\t\t * disabled, by a software over-ride.\n\t\t *\n\t\t * Since there really isn't a way to advertise that we are\n\t\t * capable of Rx Pause ONLY, we will advertise that we\n\t\t * support both symmetric and asymmetric Rx PAUSE. Later\n\t\t * (in e1000_config_fc_after_link_up) we will disable the\n\t\t * hw's ability to send PAUSE frames.\n\t\t */\n\t\tmii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);\n\t\tbreak;\n\tcase e1000_fc_tx_pause:\n\t\t/* Tx Flow control is enabled, and Rx Flow control is\n\t\t * disabled, by a software over-ride.\n\t\t */\n\t\tmii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;\n\t\tmii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;\n\t\tbreak;\n\tcase e1000_fc_full:\n\t\t/* Flow control (both Rx and Tx) is enabled by a software\n\t\t * over-ride.\n\t\t */\n\t\tmii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\"Flow control param set incorrectly\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tDEBUGOUT1(\"Auto-Neg Advertising %x\\n\", mii_autoneg_adv_reg);\n\n\tif (phy->autoneg_mask & ADVERTISE_1000_FULL)\n\t\tret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,\n\t\t\t\t\t mii_1000t_ctrl_reg);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link\n * @hw: pointer to the HW structure\n *\n * Performs initial bounds checking on autoneg advertisement parameter, then\n * configure to advertise the full capability. Setup the PHY to autoneg\n * and restart the negotiation process between the link partner. If\n * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.\n **/\ns32 e1000_copper_link_autoneg(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_ctrl;\n\n\tDEBUGFUNC(\"e1000_copper_link_autoneg\");\n\n\t/* Perform some bounds checking on the autoneg advertisement\n\t * parameter.\n\t */\n\tphy->autoneg_advertised &= phy->autoneg_mask;\n\n\t/* If autoneg_advertised is zero, we assume it was not defaulted\n\t * by the calling code so we set to advertise full capability.\n\t */\n\tif (!phy->autoneg_advertised)\n\t\tphy->autoneg_advertised = phy->autoneg_mask;\n\n\tDEBUGOUT(\"Reconfiguring auto-neg advertisement params\\n\");\n\tret_val = e1000_phy_setup_autoneg(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error Setting up Auto-Negotiation\\n\");\n\t\treturn ret_val;\n\t}\n\tDEBUGOUT(\"Restarting Auto-Neg\\n\");\n\n\t/* Restart auto-negotiation by setting the Auto Neg Enable bit and\n\t * the Auto Neg Restart bit in the PHY control register.\n\t */\n\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);\n\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Does the user want to wait for Auto-Neg to complete here, or\n\t * check at a later time (for example, callback routine).\n\t */\n\tif (phy->autoneg_wait_to_complete) {\n\t\tret_val = e1000_wait_autoneg(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error while waiting for autoneg to complete\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\thw->mac.get_link_status = true;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_copper_link_generic - Configure copper link settings\n * @hw: pointer to the HW structure\n *\n * Calls the appropriate function to configure the link for auto-neg or forced\n * speed and duplex. Then we check for link, once link is established calls\n * to configure collision distance and flow control are called. If link is\n * not established, we return -E1000_ERR_PHY (-2).\n **/\ns32 e1000_setup_copper_link_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_setup_copper_link_generic\");\n\n\tif (hw->mac.autoneg) {\n\t\t/* Setup autoneg and flow control advertisement and perform\n\t\t * autonegotiation.\n\t\t */\n\t\tret_val = e1000_copper_link_autoneg(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\t/* PHY will be set to 10H, 10F, 100H or 100F\n\t\t * depending on user settings.\n\t\t */\n\t\tDEBUGOUT(\"Forcing Speed and Duplex\\n\");\n\t\tret_val = hw->phy.ops.force_speed_duplex(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error Forcing Speed and Duplex\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\t/* Check link status. Wait up to 100 microseconds for link to become\n\t * valid.\n\t */\n\tret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,\n\t\t\t\t\t &link);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (link) {\n\t\tDEBUGOUT(\"Valid link established!!!\\n\");\n\t\thw->mac.ops.config_collision_dist(hw);\n\t\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\t} else {\n\t\tDEBUGOUT(\"Unable to establish link!!!\\n\");\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY\n * @hw: pointer to the HW structure\n *\n * Calls the PHY setup function to force speed and duplex. Clears the\n * auto-crossover to force MDI manually. Waits for link and returns\n * successful if link up is successful, else -E1000_ERR_PHY (-2).\n **/\ns32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_phy_force_speed_duplex_igp\");\n\n\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\te1000_phy_force_speed_duplex_setup(hw, &phy_data);\n\n\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Clear Auto-Crossover to force MDI manually. IGP requires MDI\n\t * forced whenever speed and duplex are forced.\n\t */\n\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;\n\tphy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;\n\n\tret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tDEBUGOUT1(\"IGP PSCR: %X\\n\", phy_data);\n\n\tusec_delay(1);\n\n\tif (phy->autoneg_wait_to_complete) {\n\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on IGP phy.\\n\");\n\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (!link)\n\t\t\tDEBUGOUT(\"Link taking longer than expected.\\n\");\n\n\t\t/* Try once more */\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY\n * @hw: pointer to the HW structure\n *\n * Calls the PHY setup function to force speed and duplex. Clears the\n * auto-crossover to force MDI manually. Resets the PHY to commit the\n * changes. If time expires while waiting for link up, we reset the DSP.\n * After reset, TX_CLK and CRS on Tx must be set. Return successful upon\n * successful completion, else return corresponding error code.\n **/\ns32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_phy_force_speed_duplex_m88\");\n\n\t/* I210 and I211 devices support Auto-Crossover in forced operation. */\n\tif (phy->type != e1000_phy_i210) {\n\t\t/* Clear Auto-Crossover to force MDI manually. M88E1000\n\t\t * requires MDI forced whenever speed and duplex are forced.\n\t\t */\n\t\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy_data &= ~M88E1000_PSCR_AUTO_X_MODE;\n\t\tret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,\n\t\t\t\t\t phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tDEBUGOUT1(\"M88E1000 PSCR: %X\\n\", phy_data);\n\n\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\te1000_phy_force_speed_duplex_setup(hw, &phy_data);\n\n\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Reset the phy to commit changes. */\n\tret_val = hw->phy.ops.commit(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (phy->autoneg_wait_to_complete) {\n\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on M88 phy.\\n\");\n\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (!link) {\n\t\t\tbool reset_dsp = true;\n\n\t\t\tswitch (hw->phy.id) {\n\t\t\tcase I347AT4_E_PHY_ID:\n\t\t\tcase M88E1340M_E_PHY_ID:\n\t\t\tcase M88E1112_E_PHY_ID:\n\t\t\tcase M88E1543_E_PHY_ID:\n\t\t\tcase M88E1512_E_PHY_ID:\n\t\t\tcase I210_I_PHY_ID:\n\t\t\t\treset_dsp = false;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tif (hw->phy.type != e1000_phy_m88)\n\t\t\t\t\treset_dsp = false;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif (!reset_dsp) {\n\t\t\t\tDEBUGOUT(\"Link taking longer than expected.\\n\");\n\t\t\t} else {\n\t\t\t\t/* We didn't get link.\n\t\t\t\t * Reset the DSP and cross our fingers.\n\t\t\t\t */\n\t\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\tM88E1000_PHY_PAGE_SELECT,\n\t\t\t\t\t\t0x001d);\n\t\t\t\tif (ret_val)\n\t\t\t\t\treturn ret_val;\n\t\t\t\tret_val = e1000_phy_reset_dsp_generic(hw);\n\t\t\t\tif (ret_val)\n\t\t\t\t\treturn ret_val;\n\t\t\t}\n\t\t}\n\n\t\t/* Try once more */\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tif (hw->phy.type != e1000_phy_m88)\n\t\treturn E1000_SUCCESS;\n\n\tif (hw->phy.id == I347AT4_E_PHY_ID ||\n\t\thw->phy.id == M88E1340M_E_PHY_ID ||\n\t\thw->phy.id == M88E1112_E_PHY_ID)\n\t\treturn E1000_SUCCESS;\n\tif (hw->phy.id == I210_I_PHY_ID)\n\t\treturn E1000_SUCCESS;\n\tif ((hw->phy.id == M88E1543_E_PHY_ID) ||\n\t (hw->phy.id == M88E1512_E_PHY_ID))\n\t\treturn E1000_SUCCESS;\n\tret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Resetting the phy means we need to re-force TX_CLK in the\n\t * Extended PHY Specific Control Register to 25MHz clock from\n\t * the reset value of 2.5MHz.\n\t */\n\tphy_data |= M88E1000_EPSCR_TX_CLK_25;\n\tret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* In addition, we must re-enable CRS on Tx for both half and full\n\t * duplex.\n\t */\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;\n\tret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex\n * @hw: pointer to the HW structure\n *\n * Forces the speed and duplex settings of the PHY.\n * This is a function pointer entry point only called by\n * PHY setup routines.\n **/\ns32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_phy_force_speed_duplex_ife\");\n\n\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\te1000_phy_force_speed_duplex_setup(hw, &data);\n\n\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Disable MDI-X support for 10/100 */\n\tret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tdata &= ~IFE_PMC_AUTO_MDIX;\n\tdata &= ~IFE_PMC_FORCE_MDIX;\n\n\tret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tDEBUGOUT1(\"IFE PMC: %X\\n\", data);\n\n\tusec_delay(1);\n\n\tif (phy->autoneg_wait_to_complete) {\n\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on IFE phy.\\n\");\n\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (!link)\n\t\t\tDEBUGOUT(\"Link taking longer than expected.\\n\");\n\n\t\t/* Try once more */\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex\n * @hw: pointer to the HW structure\n * @phy_ctrl: pointer to current value of PHY_CONTROL\n *\n * Forces speed and duplex on the PHY by doing the following: disable flow\n * control, force speed/duplex on the MAC, disable auto speed detection,\n * disable auto-negotiation, configure duplex, configure speed, configure\n * the collision distance, write configuration to CTRL register. The\n * caller must write to the PHY_CONTROL register for these settings to\n * take affect.\n **/\nvoid e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 ctrl;\n\n\tDEBUGFUNC(\"e1000_phy_force_speed_duplex_setup\");\n\n\t/* Turn off flow control when forcing speed/duplex */\n\thw->fc.current_mode = e1000_fc_none;\n\n\t/* Force speed/duplex on the mac */\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\tctrl &= ~E1000_CTRL_SPD_SEL;\n\n\t/* Disable Auto Speed Detection */\n\tctrl &= ~E1000_CTRL_ASDE;\n\n\t/* Disable autoneg on the phy */\n\t*phy_ctrl &= ~MII_CR_AUTO_NEG_EN;\n\n\t/* Forcing Full or Half Duplex? */\n\tif (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {\n\t\tctrl &= ~E1000_CTRL_FD;\n\t\t*phy_ctrl &= ~MII_CR_FULL_DUPLEX;\n\t\tDEBUGOUT(\"Half Duplex\\n\");\n\t} else {\n\t\tctrl |= E1000_CTRL_FD;\n\t\t*phy_ctrl |= MII_CR_FULL_DUPLEX;\n\t\tDEBUGOUT(\"Full Duplex\\n\");\n\t}\n\n\t/* Forcing 10mb or 100mb? */\n\tif (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {\n\t\tctrl |= E1000_CTRL_SPD_100;\n\t\t*phy_ctrl |= MII_CR_SPEED_100;\n\t\t*phy_ctrl &= ~MII_CR_SPEED_1000;\n\t\tDEBUGOUT(\"Forcing 100mb\\n\");\n\t} else {\n\t\tctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);\n\t\t*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);\n\t\tDEBUGOUT(\"Forcing 10mb\\n\");\n\t}\n\n\thw->mac.ops.config_collision_dist(hw);\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n}\n\n/**\n * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3\n * @hw: pointer to the HW structure\n * @active: boolean used to enable/disable lplu\n *\n * Success returns 0, Failure returns 1\n *\n * The low power link up (lplu) state is set to the power management level D3\n * and SmartSpeed is disabled when active is true, else clear lplu for D3\n * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU\n * is used during Dx states where the power conservation is most important.\n * During driver activity, SmartSpeed should be enabled so performance is\n * maintained.\n **/\ns32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_set_d3_lplu_state_generic\");\n\n\tif (!hw->phy.ops.read_reg)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!active) {\n\t\tdata &= ~IGP02E1000_PM_D3_LPLU;\n\t\tret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,\n\t\t\t\t\t data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\t/* LPLU and SmartSpeed are mutually exclusive. LPLU is used\n\t\t * during Dx states where the power conservation is most\n\t\t * important. During driver activity we should enable\n\t\t * SmartSpeed, so performance is maintained.\n\t\t */\n\t\tif (phy->smart_speed == e1000_smart_speed_on) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata |= IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t} else if (phy->smart_speed == e1000_smart_speed_off) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t}\n\t} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||\n\t\t (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||\n\t\t (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {\n\t\tdata |= IGP02E1000_PM_D3_LPLU;\n\t\tret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,\n\t\t\t\t\t data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n\t\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\tret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t data);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_downshift_generic - Checks whether a downshift in speed occurred\n * @hw: pointer to the HW structure\n *\n * Success returns 0, Failure returns 1\n *\n * A downshift is detected by querying the PHY link health.\n **/\ns32 e1000_check_downshift_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, offset, mask;\n\n\tDEBUGFUNC(\"e1000_check_downshift_generic\");\n\n\tswitch (phy->type) {\n\tcase e1000_phy_i210:\n\tcase e1000_phy_m88:\n\tcase e1000_phy_gg82563:\n\tcase e1000_phy_bm:\n\tcase e1000_phy_82578:\n\t\toffset = M88E1000_PHY_SPEC_STATUS;\n\t\tmask = M88E1000_PSSR_DOWNSHIFT;\n\t\tbreak;\n\tcase e1000_phy_igp:\n\tcase e1000_phy_igp_2:\n\tcase e1000_phy_igp_3:\n\t\toffset = IGP01E1000_PHY_LINK_HEALTH;\n\t\tmask = IGP01E1000_PLHR_SS_DOWNGRADE;\n\t\tbreak;\n\tdefault:\n\t\t/* speed downshift not supported */\n\t\tphy->speed_downgraded = false;\n\t\treturn E1000_SUCCESS;\n\t}\n\n\tret_val = phy->ops.read_reg(hw, offset, &phy_data);\n\n\tif (!ret_val)\n\t\tphy->speed_downgraded = !!(phy_data & mask);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_polarity_m88 - Checks the polarity.\n * @hw: pointer to the HW structure\n *\n * Success returns 0, Failure returns -E1000_ERR_PHY (-2)\n *\n * Polarity is determined based on the PHY specific status register.\n **/\ns32 e1000_check_polarity_m88(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_check_polarity_m88\");\n\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);\n\n\tif (!ret_val)\n\t\tphy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)\n\t\t\t\t ? e1000_rev_polarity_reversed\n\t\t\t\t : e1000_rev_polarity_normal);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_polarity_igp - Checks the polarity.\n * @hw: pointer to the HW structure\n *\n * Success returns 0, Failure returns -E1000_ERR_PHY (-2)\n *\n * Polarity is determined based on the PHY port status register, and the\n * current speed (since there is no polarity at 100Mbps).\n **/\ns32 e1000_check_polarity_igp(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data, offset, mask;\n\n\tDEBUGFUNC(\"e1000_check_polarity_igp\");\n\n\t/* Polarity is determined based on the speed of\n\t * our connection.\n\t */\n\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif ((data & IGP01E1000_PSSR_SPEED_MASK) ==\n\t IGP01E1000_PSSR_SPEED_1000MBPS) {\n\t\toffset = IGP01E1000_PHY_PCS_INIT_REG;\n\t\tmask = IGP01E1000_PHY_POLARITY_MASK;\n\t} else {\n\t\t/* This really only applies to 10Mbps since\n\t\t * there is no polarity for 100Mbps (always 0).\n\t\t */\n\t\toffset = IGP01E1000_PHY_PORT_STATUS;\n\t\tmask = IGP01E1000_PSSR_POLARITY_REVERSED;\n\t}\n\n\tret_val = phy->ops.read_reg(hw, offset, &data);\n\n\tif (!ret_val)\n\t\tphy->cable_polarity = ((data & mask)\n\t\t\t\t ? e1000_rev_polarity_reversed\n\t\t\t\t : e1000_rev_polarity_normal);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_polarity_ife - Check cable polarity for IFE PHY\n * @hw: pointer to the HW structure\n *\n * Polarity is determined on the polarity reversal feature being enabled.\n **/\ns32 e1000_check_polarity_ife(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, offset, mask;\n\n\tDEBUGFUNC(\"e1000_check_polarity_ife\");\n\n\t/* Polarity is determined based on the reversal feature being enabled.\n\t */\n\tif (phy->polarity_correction) {\n\t\toffset = IFE_PHY_EXTENDED_STATUS_CONTROL;\n\t\tmask = IFE_PESC_POLARITY_REVERSED;\n\t} else {\n\t\toffset = IFE_PHY_SPECIAL_CONTROL;\n\t\tmask = IFE_PSC_FORCE_POLARITY;\n\t}\n\n\tret_val = phy->ops.read_reg(hw, offset, &phy_data);\n\n\tif (!ret_val)\n\t\tphy->cable_polarity = ((phy_data & mask)\n\t\t\t\t ? e1000_rev_polarity_reversed\n\t\t\t\t : e1000_rev_polarity_normal);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_wait_autoneg - Wait for auto-neg completion\n * @hw: pointer to the HW structure\n *\n * Waits for auto-negotiation to complete or for the auto-negotiation time\n * limit to expire, which ever happens first.\n **/\nSTATIC s32 e1000_wait_autoneg(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 i, phy_status;\n\n\tDEBUGFUNC(\"e1000_wait_autoneg\");\n\n\tif (!hw->phy.ops.read_reg)\n\t\treturn E1000_SUCCESS;\n\n\t/* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */\n\tfor (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);\n\t\tif (ret_val)\n\t\t\tbreak;\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);\n\t\tif (ret_val)\n\t\t\tbreak;\n\t\tif (phy_status & MII_SR_AUTONEG_COMPLETE)\n\t\t\tbreak;\n\t\tmsec_delay(100);\n\t}\n\n\t/* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation\n\t * has completed.\n\t */\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_has_link_generic - Polls PHY for link\n * @hw: pointer to the HW structure\n * @iterations: number of times to poll for link\n * @usec_interval: delay between polling attempts\n * @success: pointer to whether polling was successful or not\n *\n * Polls the PHY status register for link, 'iterations' number of times.\n **/\ns32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,\n\t\t\t u32 usec_interval, bool *success)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 i, phy_status;\n\n\tDEBUGFUNC(\"e1000_phy_has_link_generic\");\n\n\tif (!hw->phy.ops.read_reg)\n\t\treturn E1000_SUCCESS;\n\n\tfor (i = 0; i < iterations; i++) {\n\t\t/* Some PHYs require the PHY_STATUS register to be read\n\t\t * twice due to the link bit being sticky. No harm doing\n\t\t * it across the board.\n\t\t */\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);\n\t\tif (ret_val) {\n\t\t\t/* If the first read fails, another entity may have\n\t\t\t * ownership of the resources, wait and try again to\n\t\t\t * see if they have relinquished the resources yet.\n\t\t\t */\n\t\t\tif (usec_interval >= 1000)\n\t\t\t\tmsec_delay(usec_interval/1000);\n\t\t\telse\n\t\t\t\tusec_delay(usec_interval);\n\t\t}\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);\n\t\tif (ret_val)\n\t\t\tbreak;\n\t\tif (phy_status & MII_SR_LINK_STATUS)\n\t\t\tbreak;\n\t\tif (usec_interval >= 1000)\n\t\t\tmsec_delay(usec_interval/1000);\n\t\telse\n\t\t\tusec_delay(usec_interval);\n\t}\n\n\t*success = (i < iterations);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_cable_length_m88 - Determine cable length for m88 PHY\n * @hw: pointer to the HW structure\n *\n * Reads the PHY specific status register to retrieve the cable length\n * information. The cable length is determined by averaging the minimum and\n * maximum values to get the \"average\" cable length. The m88 PHY has four\n * possible cable length values, which are:\n *\tRegister Value\t\tCable Length\n *\t0\t\t\t< 50 meters\n *\t1\t\t\t50 - 80 meters\n *\t2\t\t\t80 - 110 meters\n *\t3\t\t\t110 - 140 meters\n *\t4\t\t\t> 140 meters\n **/\ns32 e1000_get_cable_length_m88(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, index;\n\n\tDEBUGFUNC(\"e1000_get_cable_length_m88\");\n\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tindex = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>\n\t\t M88E1000_PSSR_CABLE_LENGTH_SHIFT);\n\n\tif (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)\n\t\treturn -E1000_ERR_PHY;\n\n\tphy->min_cable_length = e1000_m88_cable_length_table[index];\n\tphy->max_cable_length = e1000_m88_cable_length_table[index + 1];\n\n\tphy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;\n\n\treturn E1000_SUCCESS;\n}\n\ns32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, phy_data2, is_cm;\n\tu16 index, default_page;\n\n\tDEBUGFUNC(\"e1000_get_cable_length_m88_gen2\");\n\n\tswitch (hw->phy.id) {\n\tcase I210_I_PHY_ID:\n\t\t/* Get cable length from PHY Cable Diagnostics Control Reg */\n\t\tret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +\n\t\t\t\t\t (I347AT4_PCDL + phy->addr),\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Check if the unit of cable length is meters or cm */\n\t\tret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +\n\t\t\t\t\t I347AT4_PCDC, &phy_data2);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tis_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);\n\n\t\t/* Populate the phy structure with cable length in meters */\n\t\tphy->min_cable_length = phy_data / (is_cm ? 100 : 1);\n\t\tphy->max_cable_length = phy_data / (is_cm ? 100 : 1);\n\t\tphy->cable_length = phy_data / (is_cm ? 100 : 1);\n\t\tbreak;\n\tcase M88E1543_E_PHY_ID:\n\tcase M88E1512_E_PHY_ID:\n\tcase M88E1340M_E_PHY_ID:\n\tcase I347AT4_E_PHY_ID:\n\t\t/* Remember the original page select and set it to 7 */\n\t\tret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,\n\t\t\t\t\t &default_page);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Get cable length from PHY Cable Diagnostics Control Reg */\n\t\tret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Check if the unit of cable length is meters or cm */\n\t\tret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tis_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);\n\n\t\t/* Populate the phy structure with cable length in meters */\n\t\tphy->min_cable_length = phy_data / (is_cm ? 100 : 1);\n\t\tphy->max_cable_length = phy_data / (is_cm ? 100 : 1);\n\t\tphy->cable_length = phy_data / (is_cm ? 100 : 1);\n\n\t\t/* Reset the page select to its original value */\n\t\tret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,\n\t\t\t\t\t default_page);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tbreak;\n\n\tcase M88E1112_E_PHY_ID:\n\t\t/* Remember the original page select and set it to 5 */\n\t\tret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,\n\t\t\t\t\t &default_page);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tindex = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>\n\t\t\tM88E1000_PSSR_CABLE_LENGTH_SHIFT;\n\n\t\tif (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)\n\t\t\treturn -E1000_ERR_PHY;\n\n\t\tphy->min_cable_length = e1000_m88_cable_length_table[index];\n\t\tphy->max_cable_length = e1000_m88_cable_length_table[index + 1];\n\n\t\tphy->cable_length = (phy->min_cable_length +\n\t\t\t\t phy->max_cable_length) / 2;\n\n\t\t/* Reset the page select to its original value */\n\t\tret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,\n\t\t\t\t\t default_page);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tbreak;\n\tdefault:\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY\n * @hw: pointer to the HW structure\n *\n * The automatic gain control (agc) normalizes the amplitude of the\n * received signal, adjusting for the attenuation produced by the\n * cable. By reading the AGC registers, which represent the\n * combination of coarse and fine gain value, the value can be put\n * into a lookup table to obtain the approximate cable length\n * for each channel.\n **/\ns32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, i, agc_value = 0;\n\tu16 cur_agc_index, max_agc_index = 0;\n\tu16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;\n\tstatic const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {\n\t\tIGP02E1000_PHY_AGC_A,\n\t\tIGP02E1000_PHY_AGC_B,\n\t\tIGP02E1000_PHY_AGC_C,\n\t\tIGP02E1000_PHY_AGC_D\n\t};\n\n\tDEBUGFUNC(\"e1000_get_cable_length_igp_2\");\n\n\t/* Read the AGC registers for all channels */\n\tfor (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {\n\t\tret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Getting bits 15:9, which represent the combination of\n\t\t * coarse and fine gain values. The result is a number\n\t\t * that can be put into the lookup table to obtain the\n\t\t * approximate cable length.\n\t\t */\n\t\tcur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &\n\t\t\t\t IGP02E1000_AGC_LENGTH_MASK);\n\n\t\t/* Array index bound check. */\n\t\tif ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||\n\t\t (cur_agc_index == 0))\n\t\t\treturn -E1000_ERR_PHY;\n\n\t\t/* Remove min & max AGC values from calculation. */\n\t\tif (e1000_igp_2_cable_length_table[min_agc_index] >\n\t\t e1000_igp_2_cable_length_table[cur_agc_index])\n\t\t\tmin_agc_index = cur_agc_index;\n\t\tif (e1000_igp_2_cable_length_table[max_agc_index] <\n\t\t e1000_igp_2_cable_length_table[cur_agc_index])\n\t\t\tmax_agc_index = cur_agc_index;\n\n\t\tagc_value += e1000_igp_2_cable_length_table[cur_agc_index];\n\t}\n\n\tagc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +\n\t\t e1000_igp_2_cable_length_table[max_agc_index]);\n\tagc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);\n\n\t/* Calculate cable length with the error range of +/- 10 meters. */\n\tphy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?\n\t\t\t\t (agc_value - IGP02E1000_AGC_RANGE) : 0);\n\tphy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;\n\n\tphy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_phy_info_m88 - Retrieve PHY information\n * @hw: pointer to the HW structure\n *\n * Valid for only copper links. Read the PHY status register (sticky read)\n * to verify that link is up. Read the PHY special control register to\n * determine the polarity and 10base-T extended distance. Read the PHY\n * special status register to determine MDI/MDIx and current speed. If\n * speed is 1000, then determine cable length, local and remote receiver.\n **/\ns32 e1000_get_phy_info_m88(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_get_phy_info_m88\");\n\n\tif (phy->media_type != e1000_media_type_copper) {\n\t\tDEBUGOUT(\"Phy info is only valid for copper media\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!link) {\n\t\tDEBUGOUT(\"Phy info is only valid if link is up\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy->polarity_correction = !!(phy_data &\n\t\t\t\t M88E1000_PSCR_POLARITY_REVERSAL);\n\n\tret_val = e1000_check_polarity_m88(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);\n\n\tif ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {\n\t\tret_val = hw->phy.ops.get_cable_length(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)\n\t\t\t\t? e1000_1000t_rx_status_ok\n\t\t\t\t: e1000_1000t_rx_status_not_ok;\n\n\t\tphy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)\n\t\t\t\t ? e1000_1000t_rx_status_ok\n\t\t\t\t : e1000_1000t_rx_status_not_ok;\n\t} else {\n\t\t/* Set values to \"undefined\" */\n\t\tphy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;\n\t\tphy->local_rx = e1000_1000t_rx_status_undefined;\n\t\tphy->remote_rx = e1000_1000t_rx_status_undefined;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_phy_info_igp - Retrieve igp PHY information\n * @hw: pointer to the HW structure\n *\n * Read PHY status to determine if link is up. If link is up, then\n * set/determine 10base-T extended distance and polarity correction. Read\n * PHY port status to determine MDI/MDIx and speed. Based on the speed,\n * determine on the cable length, local and remote receiver.\n **/\ns32 e1000_get_phy_info_igp(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_get_phy_info_igp\");\n\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!link) {\n\t\tDEBUGOUT(\"Phy info is only valid if link is up\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tphy->polarity_correction = true;\n\n\tret_val = e1000_check_polarity_igp(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);\n\n\tif ((data & IGP01E1000_PSSR_SPEED_MASK) ==\n\t IGP01E1000_PSSR_SPEED_1000MBPS) {\n\t\tret_val = phy->ops.get_cable_length(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)\n\t\t\t\t? e1000_1000t_rx_status_ok\n\t\t\t\t: e1000_1000t_rx_status_not_ok;\n\n\t\tphy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)\n\t\t\t\t ? e1000_1000t_rx_status_ok\n\t\t\t\t : e1000_1000t_rx_status_not_ok;\n\t} else {\n\t\tphy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;\n\t\tphy->local_rx = e1000_1000t_rx_status_undefined;\n\t\tphy->remote_rx = e1000_1000t_rx_status_undefined;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_phy_info_ife - Retrieves various IFE PHY states\n * @hw: pointer to the HW structure\n *\n * Populates \"phy\" structure with various feature states.\n **/\ns32 e1000_get_phy_info_ife(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_get_phy_info_ife\");\n\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!link) {\n\t\tDEBUGOUT(\"Phy info is only valid if link is up\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\tphy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);\n\n\tif (phy->polarity_correction) {\n\t\tret_val = e1000_check_polarity_ife(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\t/* Polarity is forced */\n\t\tphy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)\n\t\t\t\t ? e1000_rev_polarity_reversed\n\t\t\t\t : e1000_rev_polarity_normal);\n\t}\n\n\tret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);\n\n\t/* The following parameters are undefined for 10/100 operation. */\n\tphy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;\n\tphy->local_rx = e1000_1000t_rx_status_undefined;\n\tphy->remote_rx = e1000_1000t_rx_status_undefined;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_sw_reset_generic - PHY software reset\n * @hw: pointer to the HW structure\n *\n * Does a software reset of the PHY by reading the PHY control register and\n * setting/write the control register reset bit to the PHY.\n **/\ns32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 phy_ctrl;\n\n\tDEBUGFUNC(\"e1000_phy_sw_reset_generic\");\n\n\tif (!hw->phy.ops.read_reg)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_ctrl |= MII_CR_RESET;\n\tret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tusec_delay(1);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_hw_reset_generic - PHY hardware reset\n * @hw: pointer to the HW structure\n *\n * Verify the reset block is not blocking us from resetting. Acquire\n * semaphore (if necessary) and read/set/write the device control reset\n * bit in the PHY. Wait the appropriate delay time for the device to\n * reset and release the semaphore (if necessary).\n **/\ns32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu32 ctrl;\n\n\tDEBUGFUNC(\"e1000_phy_hw_reset_generic\");\n\n\tif (phy->ops.check_reset_block) {\n\t\tret_val = phy->ops.check_reset_block(hw);\n\t\tif (ret_val)\n\t\t\treturn E1000_SUCCESS;\n\t}\n\n\tret_val = phy->ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);\n\tE1000_WRITE_FLUSH(hw);\n\n\tusec_delay(phy->reset_delay_us);\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\tE1000_WRITE_FLUSH(hw);\n\n\tusec_delay(150);\n\n\tphy->ops.release(hw);\n\n\treturn phy->ops.get_cfg_done(hw);\n}\n\n/**\n * e1000_get_cfg_done_generic - Generic configuration done\n * @hw: pointer to the HW structure\n *\n * Generic function to wait 10 milli-seconds for configuration to complete\n * and return success.\n **/\ns32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_get_cfg_done_generic\");\n\tUNREFERENCED_1PARAMETER(hw);\n\n\tmsec_delay_irq(10);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_init_script_igp3 - Inits the IGP3 PHY\n * @hw: pointer to the HW structure\n *\n * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.\n **/\ns32 e1000_phy_init_script_igp3(struct e1000_hw *hw)\n{\n\tDEBUGOUT(\"Running IGP 3 PHY init script\\n\");\n\n\t/* PHY init IGP 3 */\n\t/* Enable rise/fall, 10-mode work in class-A */\n\thw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);\n\t/* Remove all caps from Replica path filter */\n\thw->phy.ops.write_reg(hw, 0x2F52, 0x0000);\n\t/* Bias trimming for ADC, AFE and Driver (Default) */\n\thw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);\n\t/* Increase Hybrid poly bias */\n\thw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);\n\t/* Add 4% to Tx amplitude in Gig mode */\n\thw->phy.ops.write_reg(hw, 0x2010, 0x10B0);\n\t/* Disable trimming (TTT) */\n\thw->phy.ops.write_reg(hw, 0x2011, 0x0000);\n\t/* Poly DC correction to 94.6% + 2% for all channels */\n\thw->phy.ops.write_reg(hw, 0x20DD, 0x249A);\n\t/* ABS DC correction to 95.9% */\n\thw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);\n\t/* BG temp curve trim */\n\thw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);\n\t/* Increasing ADC OPAMP stage 1 currents to max */\n\thw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);\n\t/* Force 1000 ( required for enabling PHY regs configuration) */\n\thw->phy.ops.write_reg(hw, 0x0000, 0x0140);\n\t/* Set upd_freq to 6 */\n\thw->phy.ops.write_reg(hw, 0x1F30, 0x1606);\n\t/* Disable NPDFE */\n\thw->phy.ops.write_reg(hw, 0x1F31, 0xB814);\n\t/* Disable adaptive fixed FFE (Default) */\n\thw->phy.ops.write_reg(hw, 0x1F35, 0x002A);\n\t/* Enable FFE hysteresis */\n\thw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);\n\t/* Fixed FFE for short cable lengths */\n\thw->phy.ops.write_reg(hw, 0x1F54, 0x0065);\n\t/* Fixed FFE for medium cable lengths */\n\thw->phy.ops.write_reg(hw, 0x1F55, 0x002A);\n\t/* Fixed FFE for long cable lengths */\n\thw->phy.ops.write_reg(hw, 0x1F56, 0x002A);\n\t/* Enable Adaptive Clip Threshold */\n\thw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);\n\t/* AHT reset limit to 1 */\n\thw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);\n\t/* Set AHT master delay to 127 msec */\n\thw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);\n\t/* Set scan bits for AHT */\n\thw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);\n\t/* Set AHT Preset bits */\n\thw->phy.ops.write_reg(hw, 0x1F79, 0x0210);\n\t/* Change integ_factor of channel A to 3 */\n\thw->phy.ops.write_reg(hw, 0x1895, 0x0003);\n\t/* Change prop_factor of channels BCD to 8 */\n\thw->phy.ops.write_reg(hw, 0x1796, 0x0008);\n\t/* Change cg_icount + enable integbp for channels BCD */\n\thw->phy.ops.write_reg(hw, 0x1798, 0xD008);\n\t/* Change cg_icount + enable integbp + change prop_factor_master\n\t * to 8 for channel A\n\t */\n\thw->phy.ops.write_reg(hw, 0x1898, 0xD918);\n\t/* Disable AHT in Slave mode on channel A */\n\thw->phy.ops.write_reg(hw, 0x187A, 0x0800);\n\t/* Enable LPLU and disable AN to 1000 in non-D0a states,\n\t * Enable SPD+B2B\n\t */\n\thw->phy.ops.write_reg(hw, 0x0019, 0x008D);\n\t/* Enable restart AN on an1000_dis change */\n\thw->phy.ops.write_reg(hw, 0x001B, 0x2080);\n\t/* Enable wh_fifo read clock in 10/100 modes */\n\thw->phy.ops.write_reg(hw, 0x0014, 0x0045);\n\t/* Restart AN, Speed selection is 1000 */\n\thw->phy.ops.write_reg(hw, 0x0000, 0x1340);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_phy_type_from_id - Get PHY type from id\n * @phy_id: phy_id read from the phy\n *\n * Returns the phy type from the id.\n **/\nenum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)\n{\n\tenum e1000_phy_type phy_type = e1000_phy_unknown;\n\n\tswitch (phy_id) {\n\tcase M88E1000_I_PHY_ID:\n\tcase M88E1000_E_PHY_ID:\n\tcase M88E1111_I_PHY_ID:\n\tcase M88E1011_I_PHY_ID:\n\tcase M88E1543_E_PHY_ID:\n\tcase M88E1512_E_PHY_ID:\n\tcase I347AT4_E_PHY_ID:\n\tcase M88E1112_E_PHY_ID:\n\tcase M88E1340M_E_PHY_ID:\n\t\tphy_type = e1000_phy_m88;\n\t\tbreak;\n\tcase IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */\n\t\tphy_type = e1000_phy_igp_2;\n\t\tbreak;\n\tcase GG82563_E_PHY_ID:\n\t\tphy_type = e1000_phy_gg82563;\n\t\tbreak;\n\tcase IGP03E1000_E_PHY_ID:\n\t\tphy_type = e1000_phy_igp_3;\n\t\tbreak;\n\tcase IFE_E_PHY_ID:\n\tcase IFE_PLUS_E_PHY_ID:\n\tcase IFE_C_E_PHY_ID:\n\t\tphy_type = e1000_phy_ife;\n\t\tbreak;\n\tcase BME1000_E_PHY_ID:\n\tcase BME1000_E_PHY_ID_R2:\n\t\tphy_type = e1000_phy_bm;\n\t\tbreak;\n\tcase I82578_E_PHY_ID:\n\t\tphy_type = e1000_phy_82578;\n\t\tbreak;\n\tcase I82577_E_PHY_ID:\n\t\tphy_type = e1000_phy_82577;\n\t\tbreak;\n\tcase I82579_E_PHY_ID:\n\t\tphy_type = e1000_phy_82579;\n\t\tbreak;\n\tcase I217_E_PHY_ID:\n\t\tphy_type = e1000_phy_i217;\n\t\tbreak;\n\tcase I82580_I_PHY_ID:\n\t\tphy_type = e1000_phy_82580;\n\t\tbreak;\n\tcase I210_I_PHY_ID:\n\t\tphy_type = e1000_phy_i210;\n\t\tbreak;\n\tdefault:\n\t\tphy_type = e1000_phy_unknown;\n\t\tbreak;\n\t}\n\treturn phy_type;\n}\n\n/**\n * e1000_determine_phy_address - Determines PHY address.\n * @hw: pointer to the HW structure\n *\n * This uses a trial and error method to loop through possible PHY\n * addresses. It tests each by reading the PHY ID registers and\n * checking for a match.\n **/\ns32 e1000_determine_phy_address(struct e1000_hw *hw)\n{\n\tu32 phy_addr = 0;\n\tu32 i;\n\tenum e1000_phy_type phy_type = e1000_phy_unknown;\n\n\thw->phy.id = phy_type;\n\n\tfor (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {\n\t\thw->phy.addr = phy_addr;\n\t\ti = 0;\n\n\t\tdo {\n\t\t\te1000_get_phy_id(hw);\n\t\t\tphy_type = e1000_get_phy_type_from_id(hw->phy.id);\n\n\t\t\t/* If phy_type is valid, break - we found our\n\t\t\t * PHY address\n\t\t\t */\n\t\t\tif (phy_type != e1000_phy_unknown)\n\t\t\t\treturn E1000_SUCCESS;\n\n\t\t\tmsec_delay(1);\n\t\t\ti++;\n\t\t} while (i < 10);\n\t}\n\n\treturn -E1000_ERR_PHY_TYPE;\n}\n\n/**\n * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address\n * @page: page to access\n *\n * Returns the phy address for the page requested.\n **/\nSTATIC u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)\n{\n\tu32 phy_addr = 2;\n\n\tif ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))\n\t\tphy_addr = 1;\n\n\treturn phy_addr;\n}\n\n/**\n * e1000_write_phy_reg_bm - Write BM PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Acquires semaphore, if necessary, then writes the data to PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\ns32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\ts32 ret_val;\n\tu32 page = offset >> IGP_PAGE_SHIFT;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_bm\");\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Page 800 works differently than the rest so it has its own func */\n\tif (page == BM_WUC_PAGE) {\n\t\tret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,\n\t\t\t\t\t\t\t false, false);\n\t\tgoto release;\n\t}\n\n\thw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);\n\n\tif (offset > MAX_PHY_MULTI_PAGE_REG) {\n\t\tu32 page_shift, page_select;\n\n\t\t/* Page select is register 31 for phy address 1 and 22 for\n\t\t * phy address 2 and 3. Page select is shifted only for\n\t\t * phy address 1.\n\t\t */\n\t\tif (hw->phy.addr == 1) {\n\t\t\tpage_shift = IGP_PAGE_SHIFT;\n\t\t\tpage_select = IGP01E1000_PHY_PAGE_SELECT;\n\t\t} else {\n\t\t\tpage_shift = 0;\n\t\t\tpage_select = BM_PHY_PAGE_SELECT;\n\t\t}\n\n\t\t/* Page is shifted left, PHY expects (page x 32) */\n\t\tret_val = e1000_write_phy_reg_mdic(hw, page_select,\n\t\t\t\t\t\t (page << page_shift));\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t}\n\n\tret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t data);\n\nrelease:\n\thw->phy.ops.release(hw);\n\treturn ret_val;\n}\n\n/**\n * e1000_read_phy_reg_bm - Read BM PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Acquires semaphore, if necessary, then reads the PHY register at offset\n * and storing the retrieved information in data. Release any acquired\n * semaphores before exiting.\n **/\ns32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\ts32 ret_val;\n\tu32 page = offset >> IGP_PAGE_SHIFT;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_bm\");\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Page 800 works differently than the rest so it has its own func */\n\tif (page == BM_WUC_PAGE) {\n\t\tret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,\n\t\t\t\t\t\t\t true, false);\n\t\tgoto release;\n\t}\n\n\thw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);\n\n\tif (offset > MAX_PHY_MULTI_PAGE_REG) {\n\t\tu32 page_shift, page_select;\n\n\t\t/* Page select is register 31 for phy address 1 and 22 for\n\t\t * phy address 2 and 3. Page select is shifted only for\n\t\t * phy address 1.\n\t\t */\n\t\tif (hw->phy.addr == 1) {\n\t\t\tpage_shift = IGP_PAGE_SHIFT;\n\t\t\tpage_select = IGP01E1000_PHY_PAGE_SELECT;\n\t\t} else {\n\t\t\tpage_shift = 0;\n\t\t\tpage_select = BM_PHY_PAGE_SELECT;\n\t\t}\n\n\t\t/* Page is shifted left, PHY expects (page x 32) */\n\t\tret_val = e1000_write_phy_reg_mdic(hw, page_select,\n\t\t\t\t\t\t (page << page_shift));\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t}\n\n\tret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t data);\nrelease:\n\thw->phy.ops.release(hw);\n\treturn ret_val;\n}\n\n/**\n * e1000_read_phy_reg_bm2 - Read BM PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Acquires semaphore, if necessary, then reads the PHY register at offset\n * and storing the retrieved information in data. Release any acquired\n * semaphores before exiting.\n **/\ns32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\ts32 ret_val;\n\tu16 page = (u16)(offset >> IGP_PAGE_SHIFT);\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_bm2\");\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Page 800 works differently than the rest so it has its own func */\n\tif (page == BM_WUC_PAGE) {\n\t\tret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,\n\t\t\t\t\t\t\t true, false);\n\t\tgoto release;\n\t}\n\n\thw->phy.addr = 1;\n\n\tif (offset > MAX_PHY_MULTI_PAGE_REG) {\n\t\t/* Page is shifted left, PHY expects (page x 32) */\n\t\tret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,\n\t\t\t\t\t\t page);\n\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t}\n\n\tret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t data);\nrelease:\n\thw->phy.ops.release(hw);\n\treturn ret_val;\n}\n\n/**\n * e1000_write_phy_reg_bm2 - Write BM PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Acquires semaphore, if necessary, then writes the data to PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\ns32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\ts32 ret_val;\n\tu16 page = (u16)(offset >> IGP_PAGE_SHIFT);\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_bm2\");\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Page 800 works differently than the rest so it has its own func */\n\tif (page == BM_WUC_PAGE) {\n\t\tret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,\n\t\t\t\t\t\t\t false, false);\n\t\tgoto release;\n\t}\n\n\thw->phy.addr = 1;\n\n\tif (offset > MAX_PHY_MULTI_PAGE_REG) {\n\t\t/* Page is shifted left, PHY expects (page x 32) */\n\t\tret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,\n\t\t\t\t\t\t page);\n\n\t\tif (ret_val)\n\t\t\tgoto release;\n\t}\n\n\tret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t data);\n\nrelease:\n\thw->phy.ops.release(hw);\n\treturn ret_val;\n}\n\n/**\n * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers\n * @hw: pointer to the HW structure\n * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG\n *\n * Assumes semaphore already acquired and phy_reg points to a valid memory\n * address to store contents of the BM_WUC_ENABLE_REG register.\n **/\ns32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)\n{\n\ts32 ret_val;\n\tu16 temp;\n\n\tDEBUGFUNC(\"e1000_enable_phy_wakeup_reg_access_bm\");\n\n\tif (!phy_reg)\n\t\treturn -E1000_ERR_PARAM;\n\n\t/* All page select, port ctrl and wakeup registers use phy address 1 */\n\thw->phy.addr = 1;\n\n\t/* Select Port Control Registers page */\n\tret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Could not set Port Control page\\n\");\n\t\treturn ret_val;\n\t}\n\n\tret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);\n\tif (ret_val) {\n\t\tDEBUGOUT2(\"Could not read PHY register %d.%d\\n\",\n\t\t\t BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);\n\t\treturn ret_val;\n\t}\n\n\t/* Enable both PHY wakeup mode and Wakeup register page writes.\n\t * Prevent a power state change by disabling ME and Host PHY wakeup.\n\t */\n\ttemp = *phy_reg;\n\ttemp |= BM_WUC_ENABLE_BIT;\n\ttemp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);\n\n\tret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);\n\tif (ret_val) {\n\t\tDEBUGOUT2(\"Could not write PHY register %d.%d\\n\",\n\t\t\t BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);\n\t\treturn ret_val;\n\t}\n\n\t/* Select Host Wakeup Registers page - caller now able to write\n\t * registers on the Wakeup registers page\n\t */\n\treturn e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));\n}\n\n/**\n * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs\n * @hw: pointer to the HW structure\n * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG\n *\n * Restore BM_WUC_ENABLE_REG to its original value.\n *\n * Assumes semaphore already acquired and *phy_reg is the contents of the\n * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by\n * caller.\n **/\ns32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_disable_phy_wakeup_reg_access_bm\");\n\n\tif (!phy_reg)\n\t\treturn -E1000_ERR_PARAM;\n\n\t/* Select Port Control Registers page */\n\tret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Could not set Port Control page\\n\");\n\t\treturn ret_val;\n\t}\n\n\t/* Restore 769.17 to its original value */\n\tret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);\n\tif (ret_val)\n\t\tDEBUGOUT2(\"Could not restore PHY register %d.%d\\n\",\n\t\t\t BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read or written\n * @data: pointer to the data to read or write\n * @read: determines if operation is read or write\n * @page_set: BM_WUC_PAGE already set and access enabled\n *\n * Read the PHY register at offset and store the retrieved information in\n * data, or write data to PHY register at offset. Note the procedure to\n * access the PHY wakeup registers is different than reading the other PHY\n * registers. It works as such:\n * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1\n * 2) Set page to 800 for host (801 if we were manageability)\n * 3) Write the address using the address opcode (0x11)\n * 4) Read or write the data using the data opcode (0x12)\n * 5) Restore 769.17.2 to its original value\n *\n * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and\n * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().\n *\n * Assumes semaphore is already acquired. When page_set==true, assumes\n * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack\n * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).\n **/\nSTATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 *data, bool read, bool page_set)\n{\n\ts32 ret_val;\n\tu16 reg = BM_PHY_REG_NUM(offset);\n\tu16 page = BM_PHY_REG_PAGE(offset);\n\tu16 phy_reg = 0;\n\n\tDEBUGFUNC(\"e1000_access_phy_wakeup_reg_bm\");\n\n\t/* Gig must be disabled for MDIO accesses to Host Wakeup reg page */\n\tif ((hw->mac.type == e1000_pchlan) &&\n\t (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))\n\t\tDEBUGOUT1(\"Attempting to access page %d while gig enabled.\\n\",\n\t\t\t page);\n\n\tif (!page_set) {\n\t\t/* Enable access to PHY wakeup registers */\n\t\tret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Could not enable PHY wakeup reg access\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\tDEBUGOUT2(\"Accessing PHY page %d reg 0x%x\\n\", page, reg);\n\n\t/* Write the Wakeup register page offset value using opcode 0x11 */\n\tret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);\n\tif (ret_val) {\n\t\tDEBUGOUT1(\"Could not write address opcode to page %d\\n\", page);\n\t\treturn ret_val;\n\t}\n\n\tif (read) {\n\t\t/* Read the Wakeup register page value using opcode 0x12 */\n\t\tret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,\n\t\t\t\t\t\t data);\n\t} else {\n\t\t/* Write the Wakeup register page value using opcode 0x12 */\n\t\tret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,\n\t\t\t\t\t\t *data);\n\t}\n\n\tif (ret_val) {\n\t\tDEBUGOUT2(\"Could not access PHY reg %d.%d\\n\", page, reg);\n\t\treturn ret_val;\n\t}\n\n\tif (!page_set)\n\t\tret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_power_up_phy_copper - Restore copper link in case of PHY power down\n * @hw: pointer to the HW structure\n *\n * In the case of a PHY power down to save power, or to turn off link during a\n * driver unload, or wake on lan is not enabled, restore the link to previous\n * settings.\n **/\nvoid e1000_power_up_phy_copper(struct e1000_hw *hw)\n{\n\tu16 mii_reg = 0;\n\tu16 power_reg = 0;\n\n\t/* The PHY will retain its settings across a power down/up cycle */\n\thw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);\n\tmii_reg &= ~MII_CR_POWER_DOWN;\n\tif (hw->phy.type == e1000_phy_i210) {\n\t\thw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);\n\t\tpower_reg &= ~GS40G_CS_POWER_DOWN;\n\t\thw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);\n\t}\n\thw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);\n}\n\n/**\n * e1000_power_down_phy_copper - Restore copper link in case of PHY power down\n * @hw: pointer to the HW structure\n *\n * In the case of a PHY power down to save power, or to turn off link during a\n * driver unload, or wake on lan is not enabled, restore the link to previous\n * settings.\n **/\nvoid e1000_power_down_phy_copper(struct e1000_hw *hw)\n{\n\tu16 mii_reg = 0;\n\tu16 power_reg = 0;\n\n\t/* The PHY will retain its settings across a power down/up cycle */\n\thw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);\n\tmii_reg |= MII_CR_POWER_DOWN;\n\t/* i210 Phy requires an additional bit for power up/down */\n\tif (hw->phy.type == e1000_phy_i210) {\n\t\thw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);\n\t\tpower_reg |= GS40G_CS_POWER_DOWN;\n\t\thw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);\n\t}\n\thw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);\n\tmsec_delay(1);\n}\n\n/**\n * __e1000_read_phy_reg_hv - Read HV PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n * @locked: semaphore has already been acquired or not\n *\n * Acquires semaphore, if necessary, then reads the PHY register at offset\n * and stores the retrieved information in data. Release any acquired\n * semaphore before exiting.\n **/\nSTATIC s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,\n\t\t\t\t bool locked, bool page_set)\n{\n\ts32 ret_val;\n\tu16 page = BM_PHY_REG_PAGE(offset);\n\tu16 reg = BM_PHY_REG_NUM(offset);\n\tu32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);\n\n\tDEBUGFUNC(\"__e1000_read_phy_reg_hv\");\n\n\tif (!locked) {\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* Page 800 works differently than the rest so it has its own func */\n\tif (page == BM_WUC_PAGE) {\n\t\tret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,\n\t\t\t\t\t\t\t true, page_set);\n\t\tgoto out;\n\t}\n\n\tif (page > 0 && page < HV_INTC_FC_PAGE_START) {\n\t\tret_val = e1000_access_phy_debug_regs_hv(hw, offset,\n\t\t\t\t\t\t\t data, true);\n\t\tgoto out;\n\t}\n\n\tif (!page_set) {\n\t\tif (page == HV_INTC_FC_PAGE_START)\n\t\t\tpage = 0;\n\n\t\tif (reg > MAX_PHY_MULTI_PAGE_REG) {\n\t\t\t/* Page is shifted left, PHY expects (page x 32) */\n\t\t\tret_val = e1000_set_page_igp(hw,\n\t\t\t\t\t\t (page << IGP_PAGE_SHIFT));\n\n\t\t\thw->phy.addr = phy_addr;\n\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\n\tDEBUGOUT3(\"reading PHY page %d (or 0x%x shifted) reg 0x%x\\n\", page,\n\t\t page << IGP_PAGE_SHIFT, reg);\n\n\tret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,\n\t\t\t\t\t data);\nout:\n\tif (!locked)\n\t\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_phy_reg_hv - Read HV PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Acquires semaphore then reads the PHY register at offset and stores\n * the retrieved information in data. Release the acquired semaphore\n * before exiting.\n **/\ns32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn __e1000_read_phy_reg_hv(hw, offset, data, false, false);\n}\n\n/**\n * e1000_read_phy_reg_hv_locked - Read HV PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the PHY register at offset and stores the retrieved information\n * in data. Assumes semaphore already acquired.\n **/\ns32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn __e1000_read_phy_reg_hv(hw, offset, data, true, false);\n}\n\n/**\n * e1000_read_phy_reg_page_hv - Read HV PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Reads the PHY register at offset and stores the retrieved information\n * in data. Assumes semaphore already acquired and page already set.\n **/\ns32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn __e1000_read_phy_reg_hv(hw, offset, data, true, true);\n}\n\n/**\n * __e1000_write_phy_reg_hv - Write HV PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n * @locked: semaphore has already been acquired or not\n *\n * Acquires semaphore, if necessary, then writes the data to PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\nSTATIC s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,\n\t\t\t\t bool locked, bool page_set)\n{\n\ts32 ret_val;\n\tu16 page = BM_PHY_REG_PAGE(offset);\n\tu16 reg = BM_PHY_REG_NUM(offset);\n\tu32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);\n\n\tDEBUGFUNC(\"__e1000_write_phy_reg_hv\");\n\n\tif (!locked) {\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* Page 800 works differently than the rest so it has its own func */\n\tif (page == BM_WUC_PAGE) {\n\t\tret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,\n\t\t\t\t\t\t\t false, page_set);\n\t\tgoto out;\n\t}\n\n\tif (page > 0 && page < HV_INTC_FC_PAGE_START) {\n\t\tret_val = e1000_access_phy_debug_regs_hv(hw, offset,\n\t\t\t\t\t\t\t &data, false);\n\t\tgoto out;\n\t}\n\n\tif (!page_set) {\n\t\tif (page == HV_INTC_FC_PAGE_START)\n\t\t\tpage = 0;\n\n\t\t/* Workaround MDIO accesses being disabled after entering IEEE\n\t\t * Power Down (when bit 11 of the PHY Control register is set)\n\t\t */\n\t\tif ((hw->phy.type == e1000_phy_82578) &&\n\t\t (hw->phy.revision >= 1) &&\n\t\t (hw->phy.addr == 2) &&\n\t\t !(MAX_PHY_REG_ADDRESS & reg) &&\n\t\t (data & (1 << 11))) {\n\t\t\tu16 data2 = 0x7EFF;\n\t\t\tret_val = e1000_access_phy_debug_regs_hv(hw,\n\t\t\t\t\t\t\t\t (1 << 6) | 0x3,\n\t\t\t\t\t\t\t\t &data2, false);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t}\n\n\t\tif (reg > MAX_PHY_MULTI_PAGE_REG) {\n\t\t\t/* Page is shifted left, PHY expects (page x 32) */\n\t\t\tret_val = e1000_set_page_igp(hw,\n\t\t\t\t\t\t (page << IGP_PAGE_SHIFT));\n\n\t\t\thw->phy.addr = phy_addr;\n\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\n\tDEBUGOUT3(\"writing PHY page %d (or 0x%x shifted) reg 0x%x\\n\", page,\n\t\t page << IGP_PAGE_SHIFT, reg);\n\n\tret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,\n\t\t\t\t\t data);\n\nout:\n\tif (!locked)\n\t\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_phy_reg_hv - Write HV PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Acquires semaphore then writes the data to PHY register at the offset.\n * Release the acquired semaphores before exiting.\n **/\ns32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn __e1000_write_phy_reg_hv(hw, offset, data, false, false);\n}\n\n/**\n * e1000_write_phy_reg_hv_locked - Write HV PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Writes the data to PHY register at the offset. Assumes semaphore\n * already acquired.\n **/\ns32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn __e1000_write_phy_reg_hv(hw, offset, data, true, false);\n}\n\n/**\n * e1000_write_phy_reg_page_hv - Write HV PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Writes the data to PHY register at the offset. Assumes semaphore\n * already acquired and page already set.\n **/\ns32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn __e1000_write_phy_reg_hv(hw, offset, data, true, true);\n}\n\n/**\n * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page\n * @page: page to be accessed\n **/\nSTATIC u32 e1000_get_phy_addr_for_hv_page(u32 page)\n{\n\tu32 phy_addr = 2;\n\n\tif (page >= HV_INTC_FC_PAGE_START)\n\t\tphy_addr = 1;\n\n\treturn phy_addr;\n}\n\n/**\n * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers\n * @hw: pointer to the HW structure\n * @offset: register offset to be read or written\n * @data: pointer to the data to be read or written\n * @read: determines if operation is read or write\n *\n * Reads the PHY register at offset and stores the retreived information\n * in data. Assumes semaphore already acquired. Note that the procedure\n * to access these regs uses the address port and data port to read/write.\n * These accesses done with PHY address 2 and without using pages.\n **/\nSTATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 *data, bool read)\n{\n\ts32 ret_val;\n\tu32 addr_reg;\n\tu32 data_reg;\n\n\tDEBUGFUNC(\"e1000_access_phy_debug_regs_hv\");\n\n\t/* This takes care of the difference with desktop vs mobile phy */\n\taddr_reg = ((hw->phy.type == e1000_phy_82578) ?\n\t\t I82578_ADDR_REG : I82577_ADDR_REG);\n\tdata_reg = addr_reg + 1;\n\n\t/* All operations in this function are phy address 2 */\n\thw->phy.addr = 2;\n\n\t/* masking with 0x3F to remove the page from offset */\n\tret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Could not write the Address Offset port register\\n\");\n\t\treturn ret_val;\n\t}\n\n\t/* Read or write the data value next */\n\tif (read)\n\t\tret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);\n\telse\n\t\tret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);\n\n\tif (ret_val)\n\t\tDEBUGOUT(\"Could not access the Data port register\\n\");\n\n\treturn ret_val;\n}\n\n/**\n * e1000_link_stall_workaround_hv - Si workaround\n * @hw: pointer to the HW structure\n *\n * This function works around a Si bug where the link partner can get\n * a link up indication before the PHY does. If small packets are sent\n * by the link partner they can be placed in the packet buffer without\n * being properly accounted for by the PHY and will stall preventing\n * further packets from being received. The workaround is to clear the\n * packet buffer after the PHY detects link up.\n **/\ns32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_link_stall_workaround_hv\");\n\n\tif (hw->phy.type != e1000_phy_82578)\n\t\treturn E1000_SUCCESS;\n\n\t/* Do not apply workaround if in PHY loopback bit 14 set */\n\thw->phy.ops.read_reg(hw, PHY_CONTROL, &data);\n\tif (data & PHY_CONTROL_LB)\n\t\treturn E1000_SUCCESS;\n\n\t/* check if link is up and at 1Gbps */\n\tret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tdata &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |\n\t\t BM_CS_STATUS_SPEED_MASK);\n\n\tif (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |\n\t\t BM_CS_STATUS_SPEED_1000))\n\t\treturn E1000_SUCCESS;\n\n\tmsec_delay(200);\n\n\t/* flush the packets in the fifo buffer */\n\tret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,\n\t\t\t\t\t(HV_MUX_DATA_CTRL_GEN_TO_MAC |\n\t\t\t\t\t HV_MUX_DATA_CTRL_FORCE_SPEED));\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,\n\t\t\t\t HV_MUX_DATA_CTRL_GEN_TO_MAC);\n}\n\n/**\n * e1000_check_polarity_82577 - Checks the polarity.\n * @hw: pointer to the HW structure\n *\n * Success returns 0, Failure returns -E1000_ERR_PHY (-2)\n *\n * Polarity is determined based on the PHY specific status register.\n **/\ns32 e1000_check_polarity_82577(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_check_polarity_82577\");\n\n\tret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);\n\n\tif (!ret_val)\n\t\tphy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)\n\t\t\t\t ? e1000_rev_polarity_reversed\n\t\t\t\t : e1000_rev_polarity_normal);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY\n * @hw: pointer to the HW structure\n *\n * Calls the PHY setup function to force speed and duplex.\n **/\ns32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_phy_force_speed_duplex_82577\");\n\n\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\te1000_phy_force_speed_duplex_setup(hw, &phy_data);\n\n\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tusec_delay(1);\n\n\tif (phy->autoneg_wait_to_complete) {\n\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on 82577 phy\\n\");\n\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (!link)\n\t\t\tDEBUGOUT(\"Link taking longer than expected.\\n\");\n\n\t\t/* Try once more */\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_phy_info_82577 - Retrieve I82577 PHY information\n * @hw: pointer to the HW structure\n *\n * Read PHY status to determine if link is up. If link is up, then\n * set/determine 10base-T extended distance and polarity correction. Read\n * PHY port status to determine MDI/MDIx and speed. Based on the speed,\n * determine on the cable length, local and remote receiver.\n **/\ns32 e1000_get_phy_info_82577(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_get_phy_info_82577\");\n\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!link) {\n\t\tDEBUGOUT(\"Phy info is only valid if link is up\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tphy->polarity_correction = true;\n\n\tret_val = e1000_check_polarity_82577(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);\n\n\tif ((data & I82577_PHY_STATUS2_SPEED_MASK) ==\n\t I82577_PHY_STATUS2_SPEED_1000MBPS) {\n\t\tret_val = hw->phy.ops.get_cable_length(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)\n\t\t\t\t? e1000_1000t_rx_status_ok\n\t\t\t\t: e1000_1000t_rx_status_not_ok;\n\n\t\tphy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)\n\t\t\t\t ? e1000_1000t_rx_status_ok\n\t\t\t\t : e1000_1000t_rx_status_not_ok;\n\t} else {\n\t\tphy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;\n\t\tphy->local_rx = e1000_1000t_rx_status_undefined;\n\t\tphy->remote_rx = e1000_1000t_rx_status_undefined;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY\n * @hw: pointer to the HW structure\n *\n * Reads the diagnostic status register and verifies result is valid before\n * placing it in the phy_cable_length field.\n **/\ns32 e1000_get_cable_length_82577(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, length;\n\n\tDEBUGFUNC(\"e1000_get_cable_length_82577\");\n\n\tret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tlength = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>\n\t\t I82577_DSTATUS_CABLE_LENGTH_SHIFT);\n\n\tif (length == E1000_CABLE_LENGTH_UNDEFINED)\n\t\treturn -E1000_ERR_PHY;\n\n\tphy->cable_length = length;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_phy_reg_gs40g - Write GS40G PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Acquires semaphore, if necessary, then writes the data to PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\ns32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\ts32 ret_val;\n\tu16 page = offset >> GS40G_PAGE_SHIFT;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_gs40g\");\n\n\toffset = offset & GS40G_OFFSET_MASK;\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);\n\tif (ret_val)\n\t\tgoto release;\n\tret_val = e1000_write_phy_reg_mdic(hw, offset, data);\n\nrelease:\n\thw->phy.ops.release(hw);\n\treturn ret_val;\n}\n\n/**\n * e1000_read_phy_reg_gs40g - Read GS40G PHY register\n * @hw: pointer to the HW structure\n * @offset: lower half is register offset to read to\n * upper half is page to use.\n * @data: data to read at register offset\n *\n * Acquires semaphore, if necessary, then reads the data in the PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\ns32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\ts32 ret_val;\n\tu16 page = offset >> GS40G_PAGE_SHIFT;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_gs40g\");\n\n\toffset = offset & GS40G_OFFSET_MASK;\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);\n\tif (ret_val)\n\t\tgoto release;\n\tret_val = e1000_read_phy_reg_mdic(hw, offset, data);\n\nrelease:\n\thw->phy.ops.release(hw);\n\treturn ret_val;\n}\n\n/**\n * e1000_read_phy_reg_mphy - Read mPHY control register\n * @hw: pointer to the HW structure\n * @address: address to be read\n * @data: pointer to the read data\n *\n * Reads the mPHY control register in the PHY at offset and stores the\n * information read to data.\n **/\ns32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)\n{\n\tu32 mphy_ctrl = 0;\n\tbool locked = false;\n\tbool ready;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_mphy\");\n\n\t/* Check if mPHY is ready to read/write operations */\n\tready = e1000_is_mphy_ready(hw);\n\tif (!ready)\n\t\treturn -E1000_ERR_PHY;\n\n\t/* Check if mPHY access is disabled and enable it if so */\n\tmphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);\n\tif (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {\n\t\tlocked = true;\n\t\tready = e1000_is_mphy_ready(hw);\n\t\tif (!ready)\n\t\t\treturn -E1000_ERR_PHY;\n\t\tmphy_ctrl |= E1000_MPHY_ENA_ACCESS;\n\t\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);\n\t}\n\n\t/* Set the address that we want to read */\n\tready = e1000_is_mphy_ready(hw);\n\tif (!ready)\n\t\treturn -E1000_ERR_PHY;\n\n\t/* We mask address, because we want to use only current lane */\n\tmphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &\n\t\t~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |\n\t\t(address & E1000_MPHY_ADDRESS_MASK);\n\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);\n\n\t/* Read data from the address */\n\tready = e1000_is_mphy_ready(hw);\n\tif (!ready)\n\t\treturn -E1000_ERR_PHY;\n\t*data = E1000_READ_REG(hw, E1000_MPHY_DATA);\n\n\t/* Disable access to mPHY if it was originally disabled */\n\tif (locked)\n\t\tready = e1000_is_mphy_ready(hw);\n\t\tif (!ready)\n\t\t\treturn -E1000_ERR_PHY;\n\t\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,\n\t\t\t\tE1000_MPHY_DIS_ACCESS);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_phy_reg_mphy - Write mPHY control register\n * @hw: pointer to the HW structure\n * @address: address to write to\n * @data: data to write to register at offset\n * @line_override: used when we want to use different line than default one\n *\n * Writes data to mPHY control register.\n **/\ns32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,\n\t\t\t bool line_override)\n{\n\tu32 mphy_ctrl = 0;\n\tbool locked = false;\n\tbool ready;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_mphy\");\n\n\t/* Check if mPHY is ready to read/write operations */\n\tready = e1000_is_mphy_ready(hw);\n\tif (!ready)\n\t\treturn -E1000_ERR_PHY;\n\n\t/* Check if mPHY access is disabled and enable it if so */\n\tmphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);\n\tif (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {\n\t\tlocked = true;\n\t\tready = e1000_is_mphy_ready(hw);\n\t\tif (!ready)\n\t\t\treturn -E1000_ERR_PHY;\n\t\tmphy_ctrl |= E1000_MPHY_ENA_ACCESS;\n\t\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);\n\t}\n\n\t/* Set the address that we want to read */\n\tready = e1000_is_mphy_ready(hw);\n\tif (!ready)\n\t\treturn -E1000_ERR_PHY;\n\n\t/* We mask address, because we want to use only current lane */\n\tif (line_override)\n\t\tmphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;\n\telse\n\t\tmphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;\n\tmphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |\n\t\t(address & E1000_MPHY_ADDRESS_MASK);\n\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);\n\n\t/* Read data from the address */\n\tready = e1000_is_mphy_ready(hw);\n\tif (!ready)\n\t\treturn -E1000_ERR_PHY;\n\tE1000_WRITE_REG(hw, E1000_MPHY_DATA, data);\n\n\t/* Disable access to mPHY if it was originally disabled */\n\tif (locked)\n\t\tready = e1000_is_mphy_ready(hw);\n\t\tif (!ready)\n\t\t\treturn -E1000_ERR_PHY;\n\t\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,\n\t\t\t\tE1000_MPHY_DIS_ACCESS);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_is_mphy_ready - Check if mPHY control register is not busy\n * @hw: pointer to the HW structure\n *\n * Returns mPHY control register status.\n **/\nbool e1000_is_mphy_ready(struct e1000_hw *hw)\n{\n\tu16 retry_count = 0;\n\tu32 mphy_ctrl = 0;\n\tbool ready = false;\n\n\twhile (retry_count < 2) {\n\t\tmphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);\n\t\tif (mphy_ctrl & E1000_MPHY_BUSY) {\n\t\t\tusec_delay(20);\n\t\t\tretry_count++;\n\t\t\tcontinue;\n\t\t}\n\t\tready = true;\n\t\tbreak;\n\t}\n\n\tif (!ready)\n\t\tDEBUGOUT(\"ERROR READING mPHY control register, phy is busy.\\n\");\n\n\treturn ready;\n}\n" }, { "path": "drivers/net/e1000/base/e1000_phy.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_PHY_H_\n#define _E1000_PHY_H_\n\nvoid e1000_init_phy_ops_generic(struct e1000_hw *hw);\ns32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);\nvoid e1000_null_phy_generic(struct e1000_hw *hw);\ns32 e1000_null_lplu_state(struct e1000_hw *hw, bool active);\ns32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_null_set_page(struct e1000_hw *hw, u16 data);\ns32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t u8 dev_addr, u8 *data);\ns32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t u8 dev_addr, u8 data);\ns32 e1000_check_downshift_generic(struct e1000_hw *hw);\ns32 e1000_check_polarity_m88(struct e1000_hw *hw);\ns32 e1000_check_polarity_igp(struct e1000_hw *hw);\ns32 e1000_check_polarity_ife(struct e1000_hw *hw);\ns32 e1000_check_reset_block_generic(struct e1000_hw *hw);\ns32 e1000_phy_setup_autoneg(struct e1000_hw *hw);\ns32 e1000_copper_link_autoneg(struct e1000_hw *hw);\ns32 e1000_copper_link_setup_igp(struct e1000_hw *hw);\ns32 e1000_copper_link_setup_m88(struct e1000_hw *hw);\ns32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw);\ns32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);\ns32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);\ns32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);\ns32 e1000_get_cable_length_m88(struct e1000_hw *hw);\ns32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw);\ns32 e1000_get_cable_length_igp_2(struct e1000_hw *hw);\ns32 e1000_get_cfg_done_generic(struct e1000_hw *hw);\ns32 e1000_get_phy_id(struct e1000_hw *hw);\ns32 e1000_get_phy_info_igp(struct e1000_hw *hw);\ns32 e1000_get_phy_info_m88(struct e1000_hw *hw);\ns32 e1000_get_phy_info_ife(struct e1000_hw *hw);\ns32 e1000_phy_sw_reset_generic(struct e1000_hw *hw);\nvoid e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);\ns32 e1000_phy_hw_reset_generic(struct e1000_hw *hw);\ns32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw);\ns32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);\ns32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);\ns32 e1000_setup_copper_link_generic(struct e1000_hw *hw);\ns32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,\n\t\t\t\tu32 usec_interval, bool *success);\ns32 e1000_phy_init_script_igp3(struct e1000_hw *hw);\nenum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);\ns32 e1000_determine_phy_address(struct e1000_hw *hw);\ns32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);\ns32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);\ns32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);\nvoid e1000_power_up_phy_copper(struct e1000_hw *hw);\nvoid e1000_power_down_phy_copper(struct e1000_hw *hw);\ns32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);\ns32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data);\ns32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);\ns32 e1000_copper_link_setup_82577(struct e1000_hw *hw);\ns32 e1000_check_polarity_82577(struct e1000_hw *hw);\ns32 e1000_get_phy_info_82577(struct e1000_hw *hw);\ns32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);\ns32 e1000_get_cable_length_82577(struct e1000_hw *hw);\ns32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data);\ns32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,\n\t\t\t bool line_override);\nbool e1000_is_mphy_ready(struct e1000_hw *hw);\n\n#define E1000_MAX_PHY_ADDR\t\t8\n\n/* IGP01E1000 Specific Registers */\n#define IGP01E1000_PHY_PORT_CONFIG\t0x10 /* Port Config */\n#define IGP01E1000_PHY_PORT_STATUS\t0x11 /* Status */\n#define IGP01E1000_PHY_PORT_CTRL\t0x12 /* Control */\n#define IGP01E1000_PHY_LINK_HEALTH\t0x13 /* PHY Link Health */\n#define IGP01E1000_GMII_FIFO\t\t0x14 /* GMII FIFO */\n#define IGP02E1000_PHY_POWER_MGMT\t0x19 /* Power Management */\n#define IGP01E1000_PHY_PAGE_SELECT\t0x1F /* Page Select */\n#define BM_PHY_PAGE_SELECT\t\t22 /* Page Select for BM */\n#define IGP_PAGE_SHIFT\t\t\t5\n#define PHY_REG_MASK\t\t\t0x1F\n\n/* GS40G - I210 PHY defines */\n#define GS40G_PAGE_SELECT\t\t0x16\n#define GS40G_PAGE_SHIFT\t\t16\n#define GS40G_OFFSET_MASK\t\t0xFFFF\n#define GS40G_PAGE_2\t\t\t0x20000\n#define GS40G_MAC_REG2\t\t\t0x15\n#define GS40G_MAC_LB\t\t\t0x4140\n#define GS40G_MAC_SPEED_1G\t\t0X0006\n#define GS40G_COPPER_SPEC\t\t0x0010\n#define GS40G_CS_POWER_DOWN\t\t0x0002\n\n/* BM/HV Specific Registers */\n#define BM_PORT_CTRL_PAGE\t\t769\n#define BM_WUC_PAGE\t\t\t800\n#define BM_WUC_ADDRESS_OPCODE\t\t0x11\n#define BM_WUC_DATA_OPCODE\t\t0x12\n#define BM_WUC_ENABLE_PAGE\t\tBM_PORT_CTRL_PAGE\n#define BM_WUC_ENABLE_REG\t\t17\n#define BM_WUC_ENABLE_BIT\t\t(1 << 2)\n#define BM_WUC_HOST_WU_BIT\t\t(1 << 4)\n#define BM_WUC_ME_WU_BIT\t\t(1 << 5)\n\n#define PHY_UPPER_SHIFT\t\t\t21\n#define BM_PHY_REG(page, reg) \\\n\t(((reg) & MAX_PHY_REG_ADDRESS) |\\\n\t (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\\\n\t (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))\n#define BM_PHY_REG_PAGE(offset) \\\n\t((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))\n#define BM_PHY_REG_NUM(offset) \\\n\t((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\\\n\t (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\\\n\t\t~MAX_PHY_REG_ADDRESS)))\n\n#define HV_INTC_FC_PAGE_START\t\t768\n#define I82578_ADDR_REG\t\t\t29\n#define I82577_ADDR_REG\t\t\t16\n#define I82577_CFG_REG\t\t\t22\n#define I82577_CFG_ASSERT_CRS_ON_TX\t(1 << 15)\n#define I82577_CFG_ENABLE_DOWNSHIFT\t(3 << 10) /* auto downshift */\n#define I82577_CTRL_REG\t\t\t23\n\n/* 82577 specific PHY registers */\n#define I82577_PHY_CTRL_2\t\t18\n#define I82577_PHY_LBK_CTRL\t\t19\n#define I82577_PHY_STATUS_2\t\t26\n#define I82577_PHY_DIAG_STATUS\t\t31\n\n/* I82577 PHY Status 2 */\n#define I82577_PHY_STATUS2_REV_POLARITY\t\t0x0400\n#define I82577_PHY_STATUS2_MDIX\t\t\t0x0800\n#define I82577_PHY_STATUS2_SPEED_MASK\t\t0x0300\n#define I82577_PHY_STATUS2_SPEED_1000MBPS\t0x0200\n\n/* I82577 PHY Control 2 */\n#define I82577_PHY_CTRL2_MANUAL_MDIX\t\t0x0200\n#define I82577_PHY_CTRL2_AUTO_MDI_MDIX\t\t0x0400\n#define I82577_PHY_CTRL2_MDIX_CFG_MASK\t\t0x0600\n\n/* I82577 PHY Diagnostics Status */\n#define I82577_DSTATUS_CABLE_LENGTH\t\t0x03FC\n#define I82577_DSTATUS_CABLE_LENGTH_SHIFT\t2\n\n/* 82580 PHY Power Management */\n#define E1000_82580_PHY_POWER_MGMT\t0xE14\n#define E1000_82580_PM_SPD\t\t0x0001 /* Smart Power Down */\n#define E1000_82580_PM_D0_LPLU\t\t0x0002 /* For D0a states */\n#define E1000_82580_PM_D3_LPLU\t\t0x0004 /* For all other states */\n#define E1000_82580_PM_GO_LINKD\t\t0x0020 /* Go Link Disconnect */\n\n#define E1000_MPHY_DIS_ACCESS\t\t0x80000000 /* disable_access bit */\n#define E1000_MPHY_ENA_ACCESS\t\t0x40000000 /* enable_access bit */\n#define E1000_MPHY_BUSY\t\t\t0x00010000 /* busy bit */\n#define E1000_MPHY_ADDRESS_FNC_OVERRIDE\t0x20000000 /* fnc_override bit */\n#define E1000_MPHY_ADDRESS_MASK\t\t0x0000FFFF /* address mask */\n\n/* BM PHY Copper Specific Control 1 */\n#define BM_CS_CTRL1\t\t\t16\n\n/* BM PHY Copper Specific Status */\n#define BM_CS_STATUS\t\t\t17\n#define BM_CS_STATUS_LINK_UP\t\t0x0400\n#define BM_CS_STATUS_RESOLVED\t\t0x0800\n#define BM_CS_STATUS_SPEED_MASK\t\t0xC000\n#define BM_CS_STATUS_SPEED_1000\t\t0x8000\n\n/* 82577 Mobile Phy Status Register */\n#define HV_M_STATUS\t\t\t26\n#define HV_M_STATUS_AUTONEG_COMPLETE\t0x1000\n#define HV_M_STATUS_SPEED_MASK\t\t0x0300\n#define HV_M_STATUS_SPEED_1000\t\t0x0200\n#define HV_M_STATUS_SPEED_100\t\t0x0100\n#define HV_M_STATUS_LINK_UP\t\t0x0040\n\n#define IGP01E1000_PHY_PCS_INIT_REG\t0x00B4\n#define IGP01E1000_PHY_POLARITY_MASK\t0x0078\n\n#define IGP01E1000_PSCR_AUTO_MDIX\t0x1000\n#define IGP01E1000_PSCR_FORCE_MDI_MDIX\t0x2000 /* 0=MDI, 1=MDIX */\n\n#define IGP01E1000_PSCFR_SMART_SPEED\t0x0080\n\n/* Enable flexible speed on link-up */\n#define IGP01E1000_GMII_FLEX_SPD\t0x0010\n#define IGP01E1000_GMII_SPD\t\t0x0020 /* Enable SPD */\n\n#define IGP02E1000_PM_SPD\t\t0x0001 /* Smart Power Down */\n#define IGP02E1000_PM_D0_LPLU\t\t0x0002 /* For D0a states */\n#define IGP02E1000_PM_D3_LPLU\t\t0x0004 /* For all other states */\n\n#define IGP01E1000_PLHR_SS_DOWNGRADE\t0x8000\n\n#define IGP01E1000_PSSR_POLARITY_REVERSED\t0x0002\n#define IGP01E1000_PSSR_MDIX\t\t0x0800\n#define IGP01E1000_PSSR_SPEED_MASK\t0xC000\n#define IGP01E1000_PSSR_SPEED_1000MBPS\t0xC000\n\n#define IGP02E1000_PHY_CHANNEL_NUM\t4\n#define IGP02E1000_PHY_AGC_A\t\t0x11B1\n#define IGP02E1000_PHY_AGC_B\t\t0x12B1\n#define IGP02E1000_PHY_AGC_C\t\t0x14B1\n#define IGP02E1000_PHY_AGC_D\t\t0x18B1\n\n#define IGP02E1000_AGC_LENGTH_SHIFT\t9 /* Course=15:13, Fine=12:9 */\n#define IGP02E1000_AGC_LENGTH_MASK\t0x7F\n#define IGP02E1000_AGC_RANGE\t\t15\n\n#define E1000_CABLE_LENGTH_UNDEFINED\t0xFF\n\n#define E1000_KMRNCTRLSTA_OFFSET\t0x001F0000\n#define E1000_KMRNCTRLSTA_OFFSET_SHIFT\t16\n#define E1000_KMRNCTRLSTA_REN\t\t0x00200000\n#define E1000_KMRNCTRLSTA_CTRL_OFFSET\t0x1 /* Kumeran Control */\n#define E1000_KMRNCTRLSTA_DIAG_OFFSET\t0x3 /* Kumeran Diagnostic */\n#define E1000_KMRNCTRLSTA_TIMEOUTS\t0x4 /* Kumeran Timeouts */\n#define E1000_KMRNCTRLSTA_INBAND_PARAM\t0x9 /* Kumeran InBand Parameters */\n#define E1000_KMRNCTRLSTA_IBIST_DISABLE\t0x0200 /* Kumeran IBIST Disable */\n#define E1000_KMRNCTRLSTA_DIAG_NELPBK\t0x1000 /* Nearend Loopback mode */\n#define E1000_KMRNCTRLSTA_K1_CONFIG\t0x7\n#define E1000_KMRNCTRLSTA_K1_ENABLE\t0x0002 /* enable K1 */\n#define E1000_KMRNCTRLSTA_HD_CTRL\t0x10 /* Kumeran HD Control */\n#define E1000_KMRNCTRLSTA_OP_MODES\t0x1F /* Kumeran Modes of Operation */\n#define E1000_KMRNCTRLSTA_OP_MODES_LSC2CSC\t0x0002 /* change LSC to CSC */\n\n#define IFE_PHY_EXTENDED_STATUS_CONTROL\t0x10\n#define IFE_PHY_SPECIAL_CONTROL\t\t0x11 /* 100BaseTx PHY Special Ctrl */\n#define IFE_PHY_SPECIAL_CONTROL_LED\t0x1B /* PHY Special and LED Ctrl */\n#define IFE_PHY_MDIX_CONTROL\t\t0x1C /* MDI/MDI-X Control */\n\n/* IFE PHY Extended Status Control */\n#define IFE_PESC_POLARITY_REVERSED\t0x0100\n\n/* IFE PHY Special Control */\n#define IFE_PSC_AUTO_POLARITY_DISABLE\t0x0010\n#define IFE_PSC_FORCE_POLARITY\t\t0x0020\n\n/* IFE PHY Special Control and LED Control */\n#define IFE_PSCL_PROBE_MODE\t\t0x0020\n#define IFE_PSCL_PROBE_LEDS_OFF\t\t0x0006 /* Force LEDs 0 and 2 off */\n#define IFE_PSCL_PROBE_LEDS_ON\t\t0x0007 /* Force LEDs 0 and 2 on */\n\n/* IFE PHY MDIX Control */\n#define IFE_PMC_MDIX_STATUS\t\t0x0020 /* 1=MDI-X, 0=MDI */\n#define IFE_PMC_FORCE_MDIX\t\t0x0040 /* 1=force MDI-X, 0=force MDI */\n#define IFE_PMC_AUTO_MDIX\t\t0x0080 /* 1=enable auto, 0=disable */\n\n/* SFP modules ID memory locations */\n#define E1000_SFF_IDENTIFIER_OFFSET\t0x00\n#define E1000_SFF_IDENTIFIER_SFF\t0x02\n#define E1000_SFF_IDENTIFIER_SFP\t0x03\n\n#define E1000_SFF_ETH_FLAGS_OFFSET\t0x06\n/* Flags for SFP modules compatible with ETH up to 1Gb */\nstruct sfp_e1000_flags {\n\tu8 e1000_base_sx:1;\n\tu8 e1000_base_lx:1;\n\tu8 e1000_base_cx:1;\n\tu8 e1000_base_t:1;\n\tu8 e100_base_lx:1;\n\tu8 e100_base_fx:1;\n\tu8 e10_base_bx10:1;\n\tu8 e10_base_px:1;\n};\n\n/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */\n#define E1000_SFF_VENDOR_OUI_TYCO\t0x00407600\n#define E1000_SFF_VENDOR_OUI_FTL\t0x00906500\n#define E1000_SFF_VENDOR_OUI_AVAGO\t0x00176A00\n#define E1000_SFF_VENDOR_OUI_INTEL\t0x001B2100\n\n#endif\n" }, { "path": "drivers/net/e1000/base/e1000_regs.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_REGS_H_\n#define _E1000_REGS_H_\n\n#define E1000_CTRL\t0x00000 /* Device Control - RW */\n#define E1000_CTRL_DUP\t0x00004 /* Device Control Duplicate (Shadow) - RW */\n#define E1000_STATUS\t0x00008 /* Device Status - RO */\n#define E1000_EECD\t0x00010 /* EEPROM/Flash Control - RW */\n#define E1000_EERD\t0x00014 /* EEPROM Read - RW */\n#define E1000_CTRL_EXT\t0x00018 /* Extended Device Control - RW */\n#define E1000_FLA\t0x0001C /* Flash Access - RW */\n#define E1000_MDIC\t0x00020 /* MDI Control - RW */\n#define E1000_MDICNFG\t0x00E04 /* MDI Config - RW */\n#define E1000_REGISTER_SET_SIZE\t\t0x20000 /* CSR Size */\n#define E1000_EEPROM_INIT_CTRL_WORD_2\t0x0F /* EEPROM Init Ctrl Word 2 */\n#define E1000_EEPROM_PCIE_CTRL_WORD_2\t0x28 /* EEPROM PCIe Ctrl Word 2 */\n#define E1000_BARCTRL\t\t\t0x5BBC /* BAR ctrl reg */\n#define E1000_BARCTRL_FLSIZE\t\t0x0700 /* BAR ctrl Flsize */\n#define E1000_BARCTRL_CSRSIZE\t\t0x2000 /* BAR ctrl CSR size */\n#define E1000_MPHY_ADDR_CTRL\t0x0024 /* GbE MPHY Address Control */\n#define E1000_MPHY_DATA\t\t0x0E10 /* GBE MPHY Data */\n#define E1000_MPHY_STAT\t\t0x0E0C /* GBE MPHY Statistics */\n#define E1000_PPHY_CTRL\t\t0x5b48 /* PCIe PHY Control */\n#define E1000_I350_BARCTRL\t\t0x5BFC /* BAR ctrl reg */\n#define E1000_I350_DTXMXPKTSZ\t\t0x355C /* Maximum sent packet size reg*/\n#define E1000_SCTL\t0x00024 /* SerDes Control - RW */\n#define E1000_FCAL\t0x00028 /* Flow Control Address Low - RW */\n#define E1000_FCAH\t0x0002C /* Flow Control Address High -RW */\n#if !defined(EXTERNAL_RELEASE) || (defined(NAHUM6LP_HW) && defined(ULP_SUPPORT))\n#define E1000_FEXT\t0x0002C /* Future Extended - RW */\n#endif /* !EXTERNAL_RELEASE || (NAHUM6LP_HW && ULP_SUPPORT) */\n#define E1000_FEXTNVM\t0x00028 /* Future Extended NVM - RW */\n#define E1000_FEXTNVM3\t0x0003C /* Future Extended NVM 3 - RW */\n#define E1000_FEXTNVM4\t0x00024 /* Future Extended NVM 4 - RW */\n#define E1000_FEXTNVM6\t0x00010 /* Future Extended NVM 6 - RW */\n#define E1000_FEXTNVM7\t0x000E4 /* Future Extended NVM 7 - RW */\n#define E1000_FCT\t0x00030 /* Flow Control Type - RW */\n#define E1000_CONNSW\t0x00034 /* Copper/Fiber switch control - RW */\n#define E1000_VET\t0x00038 /* VLAN Ether Type - RW */\n#define E1000_ICR\t0x000C0 /* Interrupt Cause Read - R/clr */\n#define E1000_ITR\t0x000C4 /* Interrupt Throttling Rate - RW */\n#define E1000_ICS\t0x000C8 /* Interrupt Cause Set - WO */\n#define E1000_IMS\t0x000D0 /* Interrupt Mask Set - RW */\n#define E1000_IMC\t0x000D8 /* Interrupt Mask Clear - WO */\n#define E1000_IAM\t0x000E0 /* Interrupt Acknowledge Auto Mask */\n#define E1000_IVAR\t0x000E4 /* Interrupt Vector Allocation Register - RW */\n#define E1000_SVCR\t0x000F0\n#define E1000_SVT\t0x000F4\n#define E1000_LPIC\t0x000FC /* Low Power IDLE control */\n#define E1000_RCTL\t0x00100 /* Rx Control - RW */\n#define E1000_FCTTV\t0x00170 /* Flow Control Transmit Timer Value - RW */\n#define E1000_TXCW\t0x00178 /* Tx Configuration Word - RW */\n#define E1000_RXCW\t0x00180 /* Rx Configuration Word - RO */\n#define E1000_PBA_ECC\t0x01100 /* PBA ECC Register */\n#define E1000_EICR\t0x01580 /* Ext. Interrupt Cause Read - R/clr */\n#define E1000_EITR(_n)\t(0x01680 + (0x4 * (_n)))\n#define E1000_EICS\t0x01520 /* Ext. Interrupt Cause Set - W0 */\n#define E1000_EIMS\t0x01524 /* Ext. Interrupt Mask Set/Read - RW */\n#define E1000_EIMC\t0x01528 /* Ext. Interrupt Mask Clear - WO */\n#define E1000_EIAC\t0x0152C /* Ext. Interrupt Auto Clear - RW */\n#define E1000_EIAM\t0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */\n#define E1000_GPIE\t0x01514 /* General Purpose Interrupt Enable - RW */\n#define E1000_IVAR0\t0x01700 /* Interrupt Vector Allocation (array) - RW */\n#define E1000_IVAR_MISC\t0x01740 /* IVAR for \"other\" causes - RW */\n#define E1000_TCTL\t0x00400 /* Tx Control - RW */\n#define E1000_TCTL_EXT\t0x00404 /* Extended Tx Control - RW */\n#define E1000_TIPG\t0x00410 /* Tx Inter-packet gap -RW */\n#define E1000_TBT\t0x00448 /* Tx Burst Timer - RW */\n#define E1000_AIT\t0x00458 /* Adaptive Interframe Spacing Throttle - RW */\n#define E1000_LEDCTL\t0x00E00 /* LED Control - RW */\n#define E1000_LEDMUX\t0x08130 /* LED MUX Control */\n#define E1000_EXTCNF_CTRL\t0x00F00 /* Extended Configuration Control */\n#define E1000_EXTCNF_SIZE\t0x00F08 /* Extended Configuration Size */\n#define E1000_PHY_CTRL\t0x00F10 /* PHY Control Register in CSR */\n#define E1000_POEMB\tE1000_PHY_CTRL /* PHY OEM Bits */\n#define E1000_PBA\t0x01000 /* Packet Buffer Allocation - RW */\n#define E1000_PBS\t0x01008 /* Packet Buffer Size */\n#define E1000_PBECCSTS\t0x0100C /* Packet Buffer ECC Status - RW */\n#define E1000_EEMNGCTL\t0x01010 /* MNG EEprom Control */\n#define E1000_EEARBC\t0x01024 /* EEPROM Auto Read Bus Control */\n#define E1000_FLASHT\t0x01028 /* FLASH Timer Register */\n#define E1000_EEWR\t0x0102C /* EEPROM Write Register - RW */\n#define E1000_FLSWCTL\t0x01030 /* FLASH control register */\n#define E1000_FLSWDATA\t0x01034 /* FLASH data register */\n#define E1000_FLSWCNT\t0x01038 /* FLASH Access Counter */\n#define E1000_FLOP\t0x0103C /* FLASH Opcode Register */\n#define E1000_I2CCMD\t0x01028 /* SFPI2C Command Register - RW */\n#define E1000_I2CPARAMS\t0x0102C /* SFPI2C Parameters Register - RW */\n#define E1000_I2CBB_EN\t0x00000100 /* I2C - Bit Bang Enable */\n#define E1000_I2C_CLK_OUT\t0x00000200 /* I2C- Clock */\n#define E1000_I2C_DATA_OUT\t0x00000400 /* I2C- Data Out */\n#define E1000_I2C_DATA_OE_N\t0x00000800 /* I2C- Data Output Enable */\n#define E1000_I2C_DATA_IN\t0x00001000 /* I2C- Data In */\n#define E1000_I2C_CLK_OE_N\t0x00002000 /* I2C- Clock Output Enable */\n#define E1000_I2C_CLK_IN\t0x00004000 /* I2C- Clock In */\n#define E1000_I2C_CLK_STRETCH_DIS\t0x00008000 /* I2C- Dis Clk Stretching */\n#define E1000_WDSTP\t0x01040 /* Watchdog Setup - RW */\n#define E1000_SWDSTS\t0x01044 /* SW Device Status - RW */\n#define E1000_FRTIMER\t0x01048 /* Free Running Timer - RW */\n#define E1000_TCPTIMER\t0x0104C /* TCP Timer - RW */\n#define E1000_VPDDIAG\t0x01060 /* VPD Diagnostic - RO */\n#define E1000_ICR_V2\t0x01500 /* Intr Cause - new location - RC */\n#define E1000_ICS_V2\t0x01504 /* Intr Cause Set - new location - WO */\n#define E1000_IMS_V2\t0x01508 /* Intr Mask Set/Read - new location - RW */\n#define E1000_IMC_V2\t0x0150C /* Intr Mask Clear - new location - WO */\n#define E1000_IAM_V2\t0x01510 /* Intr Ack Auto Mask - new location - RW */\n#define E1000_ERT\t0x02008 /* Early Rx Threshold - RW */\n#define E1000_FCRTL\t0x02160 /* Flow Control Receive Threshold Low - RW */\n#define E1000_FCRTH\t0x02168 /* Flow Control Receive Threshold High - RW */\n#define E1000_PSRCTL\t0x02170 /* Packet Split Receive Control - RW */\n#define E1000_RDFH\t0x02410 /* Rx Data FIFO Head - RW */\n#define E1000_RDFT\t0x02418 /* Rx Data FIFO Tail - RW */\n#define E1000_RDFHS\t0x02420 /* Rx Data FIFO Head Saved - RW */\n#define E1000_RDFTS\t0x02428 /* Rx Data FIFO Tail Saved - RW */\n#define E1000_RDFPC\t0x02430 /* Rx Data FIFO Packet Count - RW */\n#define E1000_PBRTH\t0x02458 /* PB Rx Arbitration Threshold - RW */\n#define E1000_FCRTV\t0x02460 /* Flow Control Refresh Timer Value - RW */\n/* Split and Replication Rx Control - RW */\n#define E1000_RDPUMB\t0x025CC /* DMA Rx Descriptor uC Mailbox - RW */\n#define E1000_RDPUAD\t0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */\n#define E1000_RDPUWD\t0x025D4 /* DMA Rx Descriptor uC Data Write - RW */\n#define E1000_RDPURD\t0x025D8 /* DMA Rx Descriptor uC Data Read - RW */\n#define E1000_RDPUCTL\t0x025DC /* DMA Rx Descriptor uC Control - RW */\n#define E1000_PBDIAG\t0x02458 /* Packet Buffer Diagnostic - RW */\n#define E1000_RXPBS\t0x02404 /* Rx Packet Buffer Size - RW */\n#define E1000_IRPBS\t0x02404 /* Same as RXPBS, renamed for newer Si - RW */\n#define E1000_PBRWAC\t0x024E8 /* Rx packet buffer wrap around counter - RO */\n#define E1000_RDTR\t0x02820 /* Rx Delay Timer - RW */\n#define E1000_RADV\t0x0282C /* Rx Interrupt Absolute Delay Timer - RW */\n#define E1000_EMIADD\t0x10 /* Extended Memory Indirect Address */\n#define E1000_EMIDATA\t0x11 /* Extended Memory Indirect Data */\n#define E1000_SRWR\t\t0x12018 /* Shadow Ram Write Register - RW */\n#define E1000_I210_FLMNGCTL\t0x12038\n#define E1000_I210_FLMNGDATA\t0x1203C\n#define E1000_I210_FLMNGCNT\t0x12040\n\n#define E1000_I210_FLSWCTL\t0x12048\n#define E1000_I210_FLSWDATA\t0x1204C\n#define E1000_I210_FLSWCNT\t0x12050\n\n#define E1000_I210_FLA\t\t0x1201C\n\n#define E1000_INVM_DATA_REG(_n)\t(0x12120 + 4*(_n))\n#define E1000_INVM_SIZE\t\t64 /* Number of INVM Data Registers */\n\n/* QAV Tx mode control register */\n#define E1000_I210_TQAVCTRL\t0x3570\n\n/* QAV Tx mode control register bitfields masks */\n/* QAV enable */\n#define E1000_TQAVCTRL_MODE\t\t\t(1 << 0)\n/* Fetching arbitration type */\n#define E1000_TQAVCTRL_FETCH_ARB\t\t(1 << 4)\n/* Fetching timer enable */\n#define E1000_TQAVCTRL_FETCH_TIMER_ENABLE\t(1 << 5)\n/* Launch arbitration type */\n#define E1000_TQAVCTRL_LAUNCH_ARB\t\t(1 << 8)\n/* Launch timer enable */\n#define E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE\t(1 << 9)\n/* SP waits for SR enable */\n#define E1000_TQAVCTRL_SP_WAIT_SR\t\t(1 << 10)\n/* Fetching timer correction */\n#define E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET\t16\n#define E1000_TQAVCTRL_FETCH_TIMER_DELTA\t\\\n\t\t\t(0xFFFF << E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET)\n\n/* High credit registers where _n can be 0 or 1. */\n#define E1000_I210_TQAVHC(_n)\t\t\t(0x300C + 0x40 * (_n))\n\n/* Queues fetch arbitration priority control register */\n#define E1000_I210_TQAVARBCTRL\t\t\t0x3574\n/* Queues priority masks where _n and _p can be 0-3. */\n#define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p)\t((_p) << (2 * _n))\n/* QAV Tx mode control registers where _n can be 0 or 1. */\n#define E1000_I210_TQAVCC(_n)\t\t\t(0x3004 + 0x40 * (_n))\n\n/* QAV Tx mode control register bitfields masks */\n#define E1000_TQAVCC_IDLE_SLOPE\t\t0xFFFF /* Idle slope */\n#define E1000_TQAVCC_KEEP_CREDITS\t(1 << 30) /* Keep credits opt enable */\n#define E1000_TQAVCC_QUEUE_MODE\t\t(1 << 31) /* SP vs. SR Tx mode */\n\n/* Good transmitted packets counter registers */\n#define E1000_PQGPTC(_n)\t\t(0x010014 + (0x100 * (_n)))\n\n/* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */\n#define E1000_I210_TXPBS_SIZE(_n, _s)\t((_s) << (6 * _n))\n\n#define E1000_MMDAC\t\t\t13 /* MMD Access Control */\n#define E1000_MMDAAD\t\t\t14 /* MMD Access Address/Data */\n\n/* Convenience macros\n *\n * Note: \"_n\" is the queue number of the register to be written to.\n *\n * Example usage:\n * E1000_RDBAL_REG(current_rx_queue)\n */\n#define E1000_RDBAL(_n)\t((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C000 + ((_n) * 0x40)))\n#define E1000_RDBAH(_n)\t((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C004 + ((_n) * 0x40)))\n#define E1000_RDLEN(_n)\t((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C008 + ((_n) * 0x40)))\n#define E1000_SRRCTL(_n)\t((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \\\n\t\t\t\t (0x0C00C + ((_n) * 0x40)))\n#define E1000_RDH(_n)\t((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C010 + ((_n) * 0x40)))\n#define E1000_RXCTL(_n)\t((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C014 + ((_n) * 0x40)))\n#define E1000_DCA_RXCTRL(_n)\tE1000_RXCTL(_n)\n#define E1000_RDT(_n)\t((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C018 + ((_n) * 0x40)))\n#define E1000_RXDCTL(_n)\t((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \\\n\t\t\t\t (0x0C028 + ((_n) * 0x40)))\n#define E1000_RQDPC(_n)\t((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C030 + ((_n) * 0x40)))\n#define E1000_TDBAL(_n)\t((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \\\n\t\t\t (0x0E000 + ((_n) * 0x40)))\n#define E1000_TDBAH(_n)\t((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \\\n\t\t\t (0x0E004 + ((_n) * 0x40)))\n#define E1000_TDLEN(_n)\t((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \\\n\t\t\t (0x0E008 + ((_n) * 0x40)))\n#define E1000_TDH(_n)\t((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \\\n\t\t\t (0x0E010 + ((_n) * 0x40)))\n#define E1000_TXCTL(_n)\t((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \\\n\t\t\t (0x0E014 + ((_n) * 0x40)))\n#define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)\n#define E1000_TDT(_n)\t((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \\\n\t\t\t (0x0E018 + ((_n) * 0x40)))\n#define E1000_TXDCTL(_n)\t((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \\\n\t\t\t\t (0x0E028 + ((_n) * 0x40)))\n#define E1000_TDWBAL(_n)\t((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \\\n\t\t\t\t (0x0E038 + ((_n) * 0x40)))\n#define E1000_TDWBAH(_n)\t((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \\\n\t\t\t\t (0x0E03C + ((_n) * 0x40)))\n#define E1000_TARC(_n)\t\t(0x03840 + ((_n) * 0x100))\n#define E1000_RSRPD\t\t0x02C00 /* Rx Small Packet Detect - RW */\n#define E1000_RAID\t\t0x02C08 /* Receive Ack Interrupt Delay - RW */\n#define E1000_TXDMAC\t\t0x03000 /* Tx DMA Control - RW */\n#define E1000_KABGTXD\t\t0x03004 /* AFE Band Gap Transmit Ref Data */\n#define E1000_PSRTYPE(_i)\t(0x05480 + ((_i) * 4))\n#define E1000_RAL(_i)\t\t(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \\\n\t\t\t\t (0x054E0 + ((_i - 16) * 8)))\n#define E1000_RAH(_i)\t\t(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \\\n\t\t\t\t (0x054E4 + ((_i - 16) * 8)))\n#define E1000_SHRAL(_i)\t\t(0x05438 + ((_i) * 8))\n#define E1000_SHRAH(_i)\t\t(0x0543C + ((_i) * 8))\n#define E1000_IP4AT_REG(_i)\t(0x05840 + ((_i) * 8))\n#define E1000_IP6AT_REG(_i)\t(0x05880 + ((_i) * 4))\n#define E1000_WUPM_REG(_i)\t(0x05A00 + ((_i) * 4))\n#define E1000_FFMT_REG(_i)\t(0x09000 + ((_i) * 8))\n#define E1000_FFVT_REG(_i)\t(0x09800 + ((_i) * 8))\n#define E1000_FFLT_REG(_i)\t(0x05F00 + ((_i) * 8))\n#define E1000_PBSLAC\t\t0x03100 /* Pkt Buffer Slave Access Control */\n#define E1000_PBSLAD(_n)\t(0x03110 + (0x4 * (_n))) /* Pkt Buffer DWORD */\n#define E1000_TXPBS\t\t0x03404 /* Tx Packet Buffer Size - RW */\n/* Same as TXPBS, renamed for newer Si - RW */\n#define E1000_ITPBS\t\t0x03404\n#define E1000_TDFH\t\t0x03410 /* Tx Data FIFO Head - RW */\n#define E1000_TDFT\t\t0x03418 /* Tx Data FIFO Tail - RW */\n#define E1000_TDFHS\t\t0x03420 /* Tx Data FIFO Head Saved - RW */\n#define E1000_TDFTS\t\t0x03428 /* Tx Data FIFO Tail Saved - RW */\n#define E1000_TDFPC\t\t0x03430 /* Tx Data FIFO Packet Count - RW */\n#define E1000_TDPUMB\t\t0x0357C /* DMA Tx Desc uC Mail Box - RW */\n#define E1000_TDPUAD\t\t0x03580 /* DMA Tx Desc uC Addr Command - RW */\n#define E1000_TDPUWD\t\t0x03584 /* DMA Tx Desc uC Data Write - RW */\n#define E1000_TDPURD\t\t0x03588 /* DMA Tx Desc uC Data Read - RW */\n#define E1000_TDPUCTL\t\t0x0358C /* DMA Tx Desc uC Control - RW */\n#define E1000_DTXCTL\t\t0x03590 /* DMA Tx Control - RW */\n#define E1000_DTXTCPFLGL\t0x0359C /* DMA Tx Control flag low - RW */\n#define E1000_DTXTCPFLGH\t0x035A0 /* DMA Tx Control flag high - RW */\n/* DMA Tx Max Total Allow Size Reqs - RW */\n#define E1000_DTXMXSZRQ\t\t0x03540\n#define E1000_TIDV\t0x03820 /* Tx Interrupt Delay Value - RW */\n#define E1000_TADV\t0x0382C /* Tx Interrupt Absolute Delay Val - RW */\n#define E1000_TSPMT\t0x03830 /* TCP Segmentation PAD & Min Threshold - RW */\n#define E1000_CRCERRS\t0x04000 /* CRC Error Count - R/clr */\n#define E1000_ALGNERRC\t0x04004 /* Alignment Error Count - R/clr */\n#define E1000_SYMERRS\t0x04008 /* Symbol Error Count - R/clr */\n#define E1000_RXERRC\t0x0400C /* Receive Error Count - R/clr */\n#define E1000_MPC\t0x04010 /* Missed Packet Count - R/clr */\n#define E1000_SCC\t0x04014 /* Single Collision Count - R/clr */\n#define E1000_ECOL\t0x04018 /* Excessive Collision Count - R/clr */\n#define E1000_MCC\t0x0401C /* Multiple Collision Count - R/clr */\n#define E1000_LATECOL\t0x04020 /* Late Collision Count - R/clr */\n#define E1000_COLC\t0x04028 /* Collision Count - R/clr */\n#define E1000_DC\t0x04030 /* Defer Count - R/clr */\n#define E1000_TNCRS\t0x04034 /* Tx-No CRS - R/clr */\n#define E1000_SEC\t0x04038 /* Sequence Error Count - R/clr */\n#define E1000_CEXTERR\t0x0403C /* Carrier Extension Error Count - R/clr */\n#define E1000_RLEC\t0x04040 /* Receive Length Error Count - R/clr */\n#define E1000_XONRXC\t0x04048 /* XON Rx Count - R/clr */\n#define E1000_XONTXC\t0x0404C /* XON Tx Count - R/clr */\n#define E1000_XOFFRXC\t0x04050 /* XOFF Rx Count - R/clr */\n#define E1000_XOFFTXC\t0x04054 /* XOFF Tx Count - R/clr */\n#define E1000_FCRUC\t0x04058 /* Flow Control Rx Unsupported Count- R/clr */\n#define E1000_PRC64\t0x0405C /* Packets Rx (64 bytes) - R/clr */\n#define E1000_PRC127\t0x04060 /* Packets Rx (65-127 bytes) - R/clr */\n#define E1000_PRC255\t0x04064 /* Packets Rx (128-255 bytes) - R/clr */\n#define E1000_PRC511\t0x04068 /* Packets Rx (255-511 bytes) - R/clr */\n#define E1000_PRC1023\t0x0406C /* Packets Rx (512-1023 bytes) - R/clr */\n#define E1000_PRC1522\t0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */\n#define E1000_GPRC\t0x04074 /* Good Packets Rx Count - R/clr */\n#define E1000_BPRC\t0x04078 /* Broadcast Packets Rx Count - R/clr */\n#define E1000_MPRC\t0x0407C /* Multicast Packets Rx Count - R/clr */\n#define E1000_GPTC\t0x04080 /* Good Packets Tx Count - R/clr */\n#define E1000_GORCL\t0x04088 /* Good Octets Rx Count Low - R/clr */\n#define E1000_GORCH\t0x0408C /* Good Octets Rx Count High - R/clr */\n#define E1000_GOTCL\t0x04090 /* Good Octets Tx Count Low - R/clr */\n#define E1000_GOTCH\t0x04094 /* Good Octets Tx Count High - R/clr */\n#define E1000_RNBC\t0x040A0 /* Rx No Buffers Count - R/clr */\n#define E1000_RUC\t0x040A4 /* Rx Undersize Count - R/clr */\n#define E1000_RFC\t0x040A8 /* Rx Fragment Count - R/clr */\n#define E1000_ROC\t0x040AC /* Rx Oversize Count - R/clr */\n#define E1000_RJC\t0x040B0 /* Rx Jabber Count - R/clr */\n#define E1000_MGTPRC\t0x040B4 /* Management Packets Rx Count - R/clr */\n#define E1000_MGTPDC\t0x040B8 /* Management Packets Dropped Count - R/clr */\n#define E1000_MGTPTC\t0x040BC /* Management Packets Tx Count - R/clr */\n#define E1000_TORL\t0x040C0 /* Total Octets Rx Low - R/clr */\n#define E1000_TORH\t0x040C4 /* Total Octets Rx High - R/clr */\n#define E1000_TOTL\t0x040C8 /* Total Octets Tx Low - R/clr */\n#define E1000_TOTH\t0x040CC /* Total Octets Tx High - R/clr */\n#define E1000_TPR\t0x040D0 /* Total Packets Rx - R/clr */\n#define E1000_TPT\t0x040D4 /* Total Packets Tx - R/clr */\n#define E1000_PTC64\t0x040D8 /* Packets Tx (64 bytes) - R/clr */\n#define E1000_PTC127\t0x040DC /* Packets Tx (65-127 bytes) - R/clr */\n#define E1000_PTC255\t0x040E0 /* Packets Tx (128-255 bytes) - R/clr */\n#define E1000_PTC511\t0x040E4 /* Packets Tx (256-511 bytes) - R/clr */\n#define E1000_PTC1023\t0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */\n#define E1000_PTC1522\t0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */\n#define E1000_MPTC\t0x040F0 /* Multicast Packets Tx Count - R/clr */\n#define E1000_BPTC\t0x040F4 /* Broadcast Packets Tx Count - R/clr */\n#define E1000_TSCTC\t0x040F8 /* TCP Segmentation Context Tx - R/clr */\n#define E1000_TSCTFC\t0x040FC /* TCP Segmentation Context Tx Fail - R/clr */\n#define E1000_IAC\t0x04100 /* Interrupt Assertion Count */\n#define E1000_ICRXPTC\t0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */\n#define E1000_ICRXATC\t0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */\n#define E1000_ICTXPTC\t0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */\n#define E1000_ICTXATC\t0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */\n#define E1000_ICTXQEC\t0x04118 /* Interrupt Cause Tx Queue Empty Count */\n#define E1000_ICTXQMTC\t0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */\n#define E1000_ICRXDMTC\t0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */\n#define E1000_ICRXOC\t0x04124 /* Interrupt Cause Receiver Overrun Count */\n#define E1000_CRC_OFFSET\t0x05F50 /* CRC Offset register */\n\n#define E1000_VFGPRC\t0x00F10\n#define E1000_VFGORC\t0x00F18\n#define E1000_VFMPRC\t0x00F3C\n#define E1000_VFGPTC\t0x00F14\n#define E1000_VFGOTC\t0x00F34\n#define E1000_VFGOTLBC\t0x00F50\n#define E1000_VFGPTLBC\t0x00F44\n#define E1000_VFGORLBC\t0x00F48\n#define E1000_VFGPRLBC\t0x00F40\n/* Virtualization statistical counters */\n#define E1000_PFVFGPRC(_n)\t(0x010010 + (0x100 * (_n)))\n#define E1000_PFVFGPTC(_n)\t(0x010014 + (0x100 * (_n)))\n#define E1000_PFVFGORC(_n)\t(0x010018 + (0x100 * (_n)))\n#define E1000_PFVFGOTC(_n)\t(0x010034 + (0x100 * (_n)))\n#define E1000_PFVFMPRC(_n)\t(0x010038 + (0x100 * (_n)))\n#define E1000_PFVFGPRLBC(_n)\t(0x010040 + (0x100 * (_n)))\n#define E1000_PFVFGPTLBC(_n)\t(0x010044 + (0x100 * (_n)))\n#define E1000_PFVFGORLBC(_n)\t(0x010048 + (0x100 * (_n)))\n#define E1000_PFVFGOTLBC(_n)\t(0x010050 + (0x100 * (_n)))\n\n/* LinkSec */\n#define E1000_LSECTXUT\t\t0x04300 /* Tx Untagged Pkt Cnt */\n#define E1000_LSECTXPKTE\t0x04304 /* Encrypted Tx Pkts Cnt */\n#define E1000_LSECTXPKTP\t0x04308 /* Protected Tx Pkt Cnt */\n#define E1000_LSECTXOCTE\t0x0430C /* Encrypted Tx Octets Cnt */\n#define E1000_LSECTXOCTP\t0x04310 /* Protected Tx Octets Cnt */\n#define E1000_LSECRXUT\t\t0x04314 /* Untagged non-Strict Rx Pkt Cnt */\n#define E1000_LSECRXOCTD\t0x0431C /* Rx Octets Decrypted Count */\n#define E1000_LSECRXOCTV\t0x04320 /* Rx Octets Validated */\n#define E1000_LSECRXBAD\t\t0x04324 /* Rx Bad Tag */\n#define E1000_LSECRXNOSCI\t0x04328 /* Rx Packet No SCI Count */\n#define E1000_LSECRXUNSCI\t0x0432C /* Rx Packet Unknown SCI Count */\n#define E1000_LSECRXUNCH\t0x04330 /* Rx Unchecked Packets Count */\n#define E1000_LSECRXDELAY\t0x04340 /* Rx Delayed Packet Count */\n#define E1000_LSECRXLATE\t0x04350 /* Rx Late Packets Count */\n#define E1000_LSECRXOK(_n)\t(0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */\n#define E1000_LSECRXINV(_n)\t(0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */\n#define E1000_LSECRXNV(_n)\t(0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */\n#define E1000_LSECRXUNSA\t0x043C0 /* Rx Unused SA Count */\n#define E1000_LSECRXNUSA\t0x043D0 /* Rx Not Using SA Count */\n#define E1000_LSECTXCAP\t\t0x0B000 /* Tx Capabilities Register - RO */\n#define E1000_LSECRXCAP\t\t0x0B300 /* Rx Capabilities Register - RO */\n#define E1000_LSECTXCTRL\t0x0B004 /* Tx Control - RW */\n#define E1000_LSECRXCTRL\t0x0B304 /* Rx Control - RW */\n#define E1000_LSECTXSCL\t\t0x0B008 /* Tx SCI Low - RW */\n#define E1000_LSECTXSCH\t\t0x0B00C /* Tx SCI High - RW */\n#define E1000_LSECTXSA\t\t0x0B010 /* Tx SA0 - RW */\n#define E1000_LSECTXPN0\t\t0x0B018 /* Tx SA PN 0 - RW */\n#define E1000_LSECTXPN1\t\t0x0B01C /* Tx SA PN 1 - RW */\n#define E1000_LSECRXSCL\t\t0x0B3D0 /* Rx SCI Low - RW */\n#define E1000_LSECRXSCH\t\t0x0B3E0 /* Rx SCI High - RW */\n/* LinkSec Tx 128-bit Key 0 - WO */\n#define E1000_LSECTXKEY0(_n)\t(0x0B020 + (0x04 * (_n)))\n/* LinkSec Tx 128-bit Key 1 - WO */\n#define E1000_LSECTXKEY1(_n)\t(0x0B030 + (0x04 * (_n)))\n#define E1000_LSECRXSA(_n)\t(0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */\n#define E1000_LSECRXPN(_n)\t(0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */\n/* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit\n * key - RW.\n */\n#define E1000_LSECRXKEY(_n, _m)\t(0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))\n\n#define E1000_SSVPC\t\t0x041A0 /* Switch Security Violation Pkt Cnt */\n#define E1000_IPSCTRL\t\t0xB430 /* IpSec Control Register */\n#define E1000_IPSRXCMD\t\t0x0B408 /* IPSec Rx Command Register - RW */\n#define E1000_IPSRXIDX\t\t0x0B400 /* IPSec Rx Index - RW */\n/* IPSec Rx IPv4/v6 Address - RW */\n#define E1000_IPSRXIPADDR(_n)\t(0x0B420 + (0x04 * (_n)))\n/* IPSec Rx 128-bit Key - RW */\n#define E1000_IPSRXKEY(_n)\t(0x0B410 + (0x04 * (_n)))\n#define E1000_IPSRXSALT\t\t0x0B404 /* IPSec Rx Salt - RW */\n#define E1000_IPSRXSPI\t\t0x0B40C /* IPSec Rx SPI - RW */\n/* IPSec Tx 128-bit Key - RW */\n#define E1000_IPSTXKEY(_n)\t(0x0B460 + (0x04 * (_n)))\n#define E1000_IPSTXSALT\t\t0x0B454 /* IPSec Tx Salt - RW */\n#define E1000_IPSTXIDX\t\t0x0B450 /* IPSec Tx SA IDX - RW */\n#define E1000_PCS_CFG0\t0x04200 /* PCS Configuration 0 - RW */\n#define E1000_PCS_LCTL\t0x04208 /* PCS Link Control - RW */\n#define E1000_PCS_LSTAT\t0x0420C /* PCS Link Status - RO */\n#define E1000_CBTMPC\t0x0402C /* Circuit Breaker Tx Packet Count */\n#define E1000_HTDPMC\t0x0403C /* Host Transmit Discarded Packets */\n#define E1000_CBRDPC\t0x04044 /* Circuit Breaker Rx Dropped Count */\n#define E1000_CBRMPC\t0x040FC /* Circuit Breaker Rx Packet Count */\n#define E1000_RPTHC\t0x04104 /* Rx Packets To Host */\n#define E1000_HGPTC\t0x04118 /* Host Good Packets Tx Count */\n#define E1000_HTCBDPC\t0x04124 /* Host Tx Circuit Breaker Dropped Count */\n#define E1000_HGORCL\t0x04128 /* Host Good Octets Received Count Low */\n#define E1000_HGORCH\t0x0412C /* Host Good Octets Received Count High */\n#define E1000_HGOTCL\t0x04130 /* Host Good Octets Transmit Count Low */\n#define E1000_HGOTCH\t0x04134 /* Host Good Octets Transmit Count High */\n#define E1000_LENERRS\t0x04138 /* Length Errors Count */\n#define E1000_SCVPC\t0x04228 /* SerDes/SGMII Code Violation Pkt Count */\n#define E1000_HRMPC\t0x0A018 /* Header Redirection Missed Packet Count */\n#define E1000_PCS_ANADV\t0x04218 /* AN advertisement - RW */\n#define E1000_PCS_LPAB\t0x0421C /* Link Partner Ability - RW */\n#define E1000_PCS_NPTX\t0x04220 /* AN Next Page Transmit - RW */\n#define E1000_PCS_LPABNP\t0x04224 /* Link Partner Ability Next Pg - RW */\n#define E1000_RXCSUM\t0x05000 /* Rx Checksum Control - RW */\n#define E1000_RLPML\t0x05004 /* Rx Long Packet Max Length */\n#define E1000_RFCTL\t0x05008 /* Receive Filter Control*/\n#define E1000_MTA\t0x05200 /* Multicast Table Array - RW Array */\n#define E1000_RA\t0x05400 /* Receive Address - RW Array */\n#define E1000_RA2\t0x054E0 /* 2nd half of Rx address array - RW Array */\n#define E1000_VFTA\t0x05600 /* VLAN Filter Table Array - RW Array */\n#define E1000_VT_CTL\t0x0581C /* VMDq Control - RW */\n#define E1000_CIAA\t0x05B88 /* Config Indirect Access Address - RW */\n#define E1000_CIAD\t0x05B8C /* Config Indirect Access Data - RW */\n#define E1000_VFQA0\t0x0B000 /* VLAN Filter Queue Array 0 - RW Array */\n#define E1000_VFQA1\t0x0B200 /* VLAN Filter Queue Array 1 - RW Array */\n#define E1000_WUC\t0x05800 /* Wakeup Control - RW */\n#define E1000_WUFC\t0x05808 /* Wakeup Filter Control - RW */\n#define E1000_WUS\t0x05810 /* Wakeup Status - RO */\n#define E1000_MANC\t0x05820 /* Management Control - RW */\n#define E1000_IPAV\t0x05838 /* IP Address Valid - RW */\n#define E1000_IP4AT\t0x05840 /* IPv4 Address Table - RW Array */\n#define E1000_IP6AT\t0x05880 /* IPv6 Address Table - RW Array */\n#define E1000_WUPL\t0x05900 /* Wakeup Packet Length - RW */\n#define E1000_WUPM\t0x05A00 /* Wakeup Packet Memory - RO A */\n#define E1000_PBACL\t0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */\n#define E1000_FFLT\t0x05F00 /* Flexible Filter Length Table - RW Array */\n#define E1000_HOST_IF\t0x08800 /* Host Interface */\n#define E1000_HIBBA\t0x8F40 /* Host Interface Buffer Base Address */\n/* Flexible Host Filter Table */\n#define E1000_FHFT(_n)\t(0x09000 + ((_n) * 0x100))\n/* Ext Flexible Host Filter Table */\n#define E1000_FHFT_EXT(_n)\t(0x09A00 + ((_n) * 0x100))\n\n\n#define E1000_KMRNCTRLSTA\t0x00034 /* MAC-PHY interface - RW */\n#define E1000_MANC2H\t\t0x05860 /* Management Control To Host - RW */\n/* Management Decision Filters */\n#define E1000_MDEF(_n)\t\t(0x05890 + (4 * (_n)))\n#define E1000_SW_FW_SYNC\t0x05B5C /* SW-FW Synchronization - RW */\n#define E1000_CCMCTL\t0x05B48 /* CCM Control Register */\n#define E1000_GIOCTL\t0x05B44 /* GIO Analog Control Register */\n#define E1000_SCCTL\t0x05B4C /* PCIc PLL Configuration Register */\n#define E1000_GCR\t0x05B00 /* PCI-Ex Control */\n#define E1000_GCR2\t0x05B64 /* PCI-Ex Control #2 */\n#define E1000_GSCL_1\t0x05B10 /* PCI-Ex Statistic Control #1 */\n#define E1000_GSCL_2\t0x05B14 /* PCI-Ex Statistic Control #2 */\n#define E1000_GSCL_3\t0x05B18 /* PCI-Ex Statistic Control #3 */\n#define E1000_GSCL_4\t0x05B1C /* PCI-Ex Statistic Control #4 */\n#define E1000_FACTPS\t0x05B30 /* Function Active and Power State to MNG */\n#define E1000_SWSM\t0x05B50 /* SW Semaphore */\n#define E1000_FWSM\t0x05B54 /* FW Semaphore */\n/* Driver-only SW semaphore (not used by BOOT agents) */\n#define E1000_SWSM2\t0x05B58\n#define E1000_DCA_ID\t0x05B70 /* DCA Requester ID Information - RO */\n#define E1000_DCA_CTRL\t0x05B74 /* DCA Control - RW */\n#define E1000_UFUSE\t0x05B78 /* UFUSE - RO */\n#define E1000_FFLT_DBG\t0x05F04 /* Debug Register */\n#define E1000_HICR\t0x08F00 /* Host Interface Control */\n#define E1000_FWSTS\t0x08F0C /* FW Status */\n\n/* RSS registers */\n#define E1000_CPUVEC\t0x02C10 /* CPU Vector Register - RW */\n#define E1000_MRQC\t0x05818 /* Multiple Receive Control - RW */\n#define E1000_IMIR(_i)\t(0x05A80 + ((_i) * 4)) /* Immediate Interrupt */\n#define E1000_IMIREXT(_i)\t(0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/\n#define E1000_IMIRVP\t\t0x05AC0 /* Immediate INT Rx VLAN Priority -RW */\n#define E1000_MSIXBM(_i)\t(0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */\n#define E1000_RETA(_i)\t(0x05C00 + ((_i) * 4)) /* Redirection Table - RW */\n#define E1000_RSSRK(_i)\t(0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */\n#define E1000_RSSIM\t0x05864 /* RSS Interrupt Mask */\n#define E1000_RSSIR\t0x05868 /* RSS Interrupt Request */\n/* VT Registers */\n#define E1000_SWPBS\t0x03004 /* Switch Packet Buffer Size - RW */\n#define E1000_MBVFICR\t0x00C80 /* Mailbox VF Cause - RWC */\n#define E1000_MBVFIMR\t0x00C84 /* Mailbox VF int Mask - RW */\n#define E1000_VFLRE\t0x00C88 /* VF Register Events - RWC */\n#define E1000_VFRE\t0x00C8C /* VF Receive Enables */\n#define E1000_VFTE\t0x00C90 /* VF Transmit Enables */\n#define E1000_QDE\t0x02408 /* Queue Drop Enable - RW */\n#define E1000_DTXSWC\t0x03500 /* DMA Tx Switch Control - RW */\n#define E1000_WVBR\t0x03554 /* VM Wrong Behavior - RWS */\n#define E1000_RPLOLR\t0x05AF0 /* Replication Offload - RW */\n#define E1000_UTA\t0x0A000 /* Unicast Table Array - RW */\n#define E1000_IOVTCL\t0x05BBC /* IOV Control Register */\n#define E1000_VMRCTL\t0X05D80 /* Virtual Mirror Rule Control */\n#define E1000_VMRVLAN\t0x05D90 /* Virtual Mirror Rule VLAN */\n#define E1000_VMRVM\t0x05DA0 /* Virtual Mirror Rule VM */\n#define E1000_MDFB\t0x03558 /* Malicious Driver free block */\n#define E1000_LVMMC\t0x03548 /* Last VM Misbehavior cause */\n#define E1000_TXSWC\t0x05ACC /* Tx Switch Control */\n#define E1000_SCCRL\t0x05DB0 /* Storm Control Control */\n#define E1000_BSCTRH\t0x05DB8 /* Broadcast Storm Control Threshold */\n#define E1000_MSCTRH\t0x05DBC /* Multicast Storm Control Threshold */\n/* These act per VF so an array friendly macro is used */\n#define E1000_V2PMAILBOX(_n)\t(0x00C40 + (4 * (_n)))\n#define E1000_P2VMAILBOX(_n)\t(0x00C00 + (4 * (_n)))\n#define E1000_VMBMEM(_n)\t(0x00800 + (64 * (_n)))\n#define E1000_VFVMBMEM(_n)\t(0x00800 + (_n))\n#define E1000_VMOLR(_n)\t\t(0x05AD0 + (4 * (_n)))\n/* VLAN Virtual Machine Filter - RW */\n#define E1000_VLVF(_n)\t\t(0x05D00 + (4 * (_n)))\n#define E1000_VMVIR(_n)\t\t(0x03700 + (4 * (_n)))\n#define E1000_DVMOLR(_n)\t(0x0C038 + (0x40 * (_n))) /* DMA VM offload */\n#define E1000_VTCTRL(_n)\t(0x10000 + (0x100 * (_n))) /* VT Control */\n#define E1000_TSYNCRXCTL\t0x0B620 /* Rx Time Sync Control register - RW */\n#define E1000_TSYNCTXCTL\t0x0B614 /* Tx Time Sync Control register - RW */\n#define E1000_TSYNCRXCFG\t0x05F50 /* Time Sync Rx Configuration - RW */\n#define E1000_RXSTMPL\t0x0B624 /* Rx timestamp Low - RO */\n#define E1000_RXSTMPH\t0x0B628 /* Rx timestamp High - RO */\n#define E1000_RXSATRL\t0x0B62C /* Rx timestamp attribute low - RO */\n#define E1000_RXSATRH\t0x0B630 /* Rx timestamp attribute high - RO */\n#define E1000_TXSTMPL\t0x0B618 /* Tx timestamp value Low - RO */\n#define E1000_TXSTMPH\t0x0B61C /* Tx timestamp value High - RO */\n#define E1000_SYSTIML\t0x0B600 /* System time register Low - RO */\n#define E1000_SYSTIMH\t0x0B604 /* System time register High - RO */\n#define E1000_TIMINCA\t0x0B608 /* Increment attributes register - RW */\n#define E1000_TIMADJL\t0x0B60C /* Time sync time adjustment offset Low - RW */\n#define E1000_TIMADJH\t0x0B610 /* Time sync time adjustment offset High - RW */\n#define E1000_TSAUXC\t0x0B640 /* Timesync Auxiliary Control register */\n#define E1000_SYSTIMR\t0x0B6F8 /* System time register Residue */\n#define E1000_TSICR\t0x0B66C /* Interrupt Cause Register */\n#define E1000_TSIM\t0x0B674 /* Interrupt Mask Register */\n#define E1000_RXMTRL\t0x0B634 /* Time sync Rx EtherType and Msg Type - RW */\n#define E1000_RXUDP\t0x0B638 /* Time Sync Rx UDP Port - RW */\n\n/* Filtering Registers */\n#define E1000_SAQF(_n)\t(0x05980 + (4 * (_n))) /* Source Address Queue Fltr */\n#define E1000_DAQF(_n)\t(0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */\n#define E1000_SPQF(_n)\t(0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */\n#define E1000_FTQF(_n)\t(0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */\n#define E1000_TTQF(_n)\t(0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */\n#define E1000_SYNQF(_n)\t(0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */\n#define E1000_ETQF(_n)\t(0x05CB0 + (4 * (_n))) /* EType Queue Fltr */\n\n#define E1000_RTTDCS\t0x3600 /* Reedtown Tx Desc plane control and status */\n#define E1000_RTTPCS\t0x3474 /* Reedtown Tx Packet Plane control and status */\n#define E1000_RTRPCS\t0x2474 /* Rx packet plane control and status */\n#define E1000_RTRUP2TC\t0x05AC4 /* Rx User Priority to Traffic Class */\n#define E1000_RTTUP2TC\t0x0418 /* Transmit User Priority to Traffic Class */\n/* Tx Desc plane TC Rate-scheduler config */\n#define E1000_RTTDTCRC(_n)\t(0x3610 + ((_n) * 4))\n/* Tx Packet plane TC Rate-Scheduler Config */\n#define E1000_RTTPTCRC(_n)\t(0x3480 + ((_n) * 4))\n/* Rx Packet plane TC Rate-Scheduler Config */\n#define E1000_RTRPTCRC(_n)\t(0x2480 + ((_n) * 4))\n/* Tx Desc Plane TC Rate-Scheduler Status */\n#define E1000_RTTDTCRS(_n)\t(0x3630 + ((_n) * 4))\n/* Tx Desc Plane TC Rate-Scheduler MMW */\n#define E1000_RTTDTCRM(_n)\t(0x3650 + ((_n) * 4))\n/* Tx Packet plane TC Rate-Scheduler Status */\n#define E1000_RTTPTCRS(_n)\t(0x34A0 + ((_n) * 4))\n/* Tx Packet plane TC Rate-scheduler MMW */\n#define E1000_RTTPTCRM(_n)\t(0x34C0 + ((_n) * 4))\n/* Rx Packet plane TC Rate-Scheduler Status */\n#define E1000_RTRPTCRS(_n)\t(0x24A0 + ((_n) * 4))\n/* Rx Packet plane TC Rate-Scheduler MMW */\n#define E1000_RTRPTCRM(_n)\t(0x24C0 + ((_n) * 4))\n/* Tx Desc plane VM Rate-Scheduler MMW*/\n#define E1000_RTTDVMRM(_n)\t(0x3670 + ((_n) * 4))\n/* Tx BCN Rate-Scheduler MMW */\n#define E1000_RTTBCNRM(_n)\t(0x3690 + ((_n) * 4))\n#define E1000_RTTDQSEL\t0x3604 /* Tx Desc Plane Queue Select */\n#define E1000_RTTDVMRC\t0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */\n#define E1000_RTTDVMRS\t0x360C /* Tx Desc Plane VM Rate-Scheduler Status */\n#define E1000_RTTBCNRC\t0x36B0 /* Tx BCN Rate-Scheduler Config */\n#define E1000_RTTBCNRS\t0x36B4 /* Tx BCN Rate-Scheduler Status */\n#define E1000_RTTBCNCR\t0xB200 /* Tx BCN Control Register */\n#define E1000_RTTBCNTG\t0x35A4 /* Tx BCN Tagging */\n#define E1000_RTTBCNCP\t0xB208 /* Tx BCN Congestion point */\n#define E1000_RTRBCNCR\t0xB20C /* Rx BCN Control Register */\n#define E1000_RTTBCNRD\t0x36B8 /* Tx BCN Rate Drift */\n#define E1000_PFCTOP\t0x1080 /* Priority Flow Control Type and Opcode */\n#define E1000_RTTBCNIDX\t0xB204 /* Tx BCN Congestion Point */\n#define E1000_RTTBCNACH\t0x0B214 /* Tx BCN Control High */\n#define E1000_RTTBCNACL\t0x0B210 /* Tx BCN Control Low */\n\n/* DMA Coalescing registers */\n#define E1000_DMACR\t0x02508 /* Control Register */\n#define E1000_DMCTXTH\t0x03550 /* Transmit Threshold */\n#define E1000_DMCTLX\t0x02514 /* Time to Lx Request */\n#define E1000_DMCRTRH\t0x05DD0 /* Receive Packet Rate Threshold */\n#define E1000_DMCCNT\t0x05DD4 /* Current Rx Count */\n#define E1000_FCRTC\t0x02170 /* Flow Control Rx high watermark */\n#define E1000_PCIEMISC\t0x05BB8 /* PCIE misc config register */\n\n/* PCIe Parity Status Register */\n#define E1000_PCIEERRSTS\t0x05BA8\n\n#define E1000_PROXYS\t0x5F64 /* Proxying Status */\n#define E1000_PROXYFC\t0x5F60 /* Proxying Filter Control */\n/* Thermal sensor configuration and status registers */\n#define E1000_THMJT\t0x08100 /* Junction Temperature */\n#define E1000_THLOWTC\t0x08104 /* Low Threshold Control */\n#define E1000_THMIDTC\t0x08108 /* Mid Threshold Control */\n#define E1000_THHIGHTC\t0x0810C /* High Threshold Control */\n#define E1000_THSTAT\t0x08110 /* Thermal Sensor Status */\n\n/* Energy Efficient Ethernet \"EEE\" registers */\n#define E1000_IPCNFG\t0x0E38 /* Internal PHY Configuration */\n#define E1000_LTRC\t0x01A0 /* Latency Tolerance Reporting Control */\n#define E1000_EEER\t0x0E30 /* Energy Efficient Ethernet \"EEE\"*/\n#define E1000_EEE_SU\t0x0E34 /* EEE Setup */\n#define E1000_TLPIC\t0x4148 /* EEE Tx LPI Count - TLPIC */\n#define E1000_RLPIC\t0x414C /* EEE Rx LPI Count - RLPIC */\n\n/* OS2BMC Registers */\n#define E1000_B2OSPC\t0x08FE0 /* BMC2OS packets sent by BMC */\n#define E1000_B2OGPRC\t0x04158 /* BMC2OS packets received by host */\n#define E1000_O2BGPTC\t0x08FE4 /* OS2BMC packets received by BMC */\n#define E1000_O2BSPC\t0x0415C /* OS2BMC packets transmitted by host */\n\n\n\n#endif\n" }, { "path": "drivers/net/e1000/base/e1000_vf.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n\n#include \"e1000_api.h\"\n\n\nSTATIC s32 e1000_init_phy_params_vf(struct e1000_hw *hw);\nSTATIC s32 e1000_init_nvm_params_vf(struct e1000_hw *hw);\nSTATIC void e1000_release_vf(struct e1000_hw *hw);\nSTATIC s32 e1000_acquire_vf(struct e1000_hw *hw);\nSTATIC s32 e1000_setup_link_vf(struct e1000_hw *hw);\nSTATIC s32 e1000_get_bus_info_pcie_vf(struct e1000_hw *hw);\nSTATIC s32 e1000_init_mac_params_vf(struct e1000_hw *hw);\nSTATIC s32 e1000_check_for_link_vf(struct e1000_hw *hw);\nSTATIC s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t u16 *duplex);\nSTATIC s32 e1000_init_hw_vf(struct e1000_hw *hw);\nSTATIC s32 e1000_reset_hw_vf(struct e1000_hw *hw);\nSTATIC void e1000_update_mc_addr_list_vf(struct e1000_hw *hw, u8 *, u32);\nSTATIC void e1000_rar_set_vf(struct e1000_hw *, u8 *, u32);\nSTATIC s32 e1000_read_mac_addr_vf(struct e1000_hw *);\n\n/**\n * e1000_init_phy_params_vf - Inits PHY params\n * @hw: pointer to the HW structure\n *\n * Doesn't do much - there's no PHY available to the VF.\n **/\nSTATIC s32 e1000_init_phy_params_vf(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_phy_params_vf\");\n\thw->phy.type = e1000_phy_vf;\n\thw->phy.ops.acquire = e1000_acquire_vf;\n\thw->phy.ops.release = e1000_release_vf;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_nvm_params_vf - Inits NVM params\n * @hw: pointer to the HW structure\n *\n * Doesn't do much - there's no NVM available to the VF.\n **/\nSTATIC s32 e1000_init_nvm_params_vf(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_nvm_params_vf\");\n\thw->nvm.type = e1000_nvm_none;\n\thw->nvm.ops.acquire = e1000_acquire_vf;\n\thw->nvm.ops.release = e1000_release_vf;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_mac_params_vf - Inits MAC params\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_init_mac_params_vf(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"e1000_init_mac_params_vf\");\n\n\t/* Set media type */\n\t/*\n\t * Virtual functions don't care what they're media type is as they\n\t * have no direct access to the PHY, or the media. That is handled\n\t * by the physical function driver.\n\t */\n\thw->phy.media_type = e1000_media_type_unknown;\n\n\t/* No ASF features for the VF driver */\n\tmac->asf_firmware_present = false;\n\t/* ARC subsystem not supported */\n\tmac->arc_subsystem_valid = false;\n\t/* Disable adaptive IFS mode so the generic funcs don't do anything */\n\tmac->adaptive_ifs = false;\n\t/* VF's have no MTA Registers - PF feature only */\n\tmac->mta_reg_count = 128;\n\t/* VF's have no access to RAR entries */\n\tmac->rar_entry_count = 1;\n\n\t/* Function pointers */\n\t/* link setup */\n\tmac->ops.setup_link = e1000_setup_link_vf;\n\t/* bus type/speed/width */\n\tmac->ops.get_bus_info = e1000_get_bus_info_pcie_vf;\n\t/* reset */\n\tmac->ops.reset_hw = e1000_reset_hw_vf;\n\t/* hw initialization */\n\tmac->ops.init_hw = e1000_init_hw_vf;\n\t/* check for link */\n\tmac->ops.check_for_link = e1000_check_for_link_vf;\n\t/* link info */\n\tmac->ops.get_link_up_info = e1000_get_link_up_info_vf;\n\t/* multicast address update */\n\tmac->ops.update_mc_addr_list = e1000_update_mc_addr_list_vf;\n\t/* set mac address */\n\tmac->ops.rar_set = e1000_rar_set_vf;\n\t/* read mac address */\n\tmac->ops.read_mac_addr = e1000_read_mac_addr_vf;\n\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_function_pointers_vf - Inits function pointers\n * @hw: pointer to the HW structure\n **/\nvoid e1000_init_function_pointers_vf(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_function_pointers_vf\");\n\n\thw->mac.ops.init_params = e1000_init_mac_params_vf;\n\thw->nvm.ops.init_params = e1000_init_nvm_params_vf;\n\thw->phy.ops.init_params = e1000_init_phy_params_vf;\n\thw->mbx.ops.init_params = e1000_init_mbx_params_vf;\n}\n\n/**\n * e1000_acquire_vf - Acquire rights to access PHY or NVM.\n * @hw: pointer to the HW structure\n *\n * There is no PHY or NVM so we want all attempts to acquire these to fail.\n * In addition, the MAC registers to access PHY/NVM don't exist so we don't\n * even want any SW to attempt to use them.\n **/\nSTATIC s32 e1000_acquire_vf(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tUNREFERENCED_1PARAMETER(hw);\n\treturn -E1000_ERR_PHY;\n}\n\n/**\n * e1000_release_vf - Release PHY or NVM\n * @hw: pointer to the HW structure\n *\n * There is no PHY or NVM so we want all attempts to acquire these to fail.\n * In addition, the MAC registers to access PHY/NVM don't exist so we don't\n * even want any SW to attempt to use them.\n **/\nSTATIC void e1000_release_vf(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tUNREFERENCED_1PARAMETER(hw);\n\treturn;\n}\n\n/**\n * e1000_setup_link_vf - Sets up link.\n * @hw: pointer to the HW structure\n *\n * Virtual functions cannot change link.\n **/\nSTATIC s32 e1000_setup_link_vf(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_setup_link_vf\");\n\tUNREFERENCED_1PARAMETER(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_bus_info_pcie_vf - Gets the bus info.\n * @hw: pointer to the HW structure\n *\n * Virtual functions are not really on their own bus.\n **/\nSTATIC s32 e1000_get_bus_info_pcie_vf(struct e1000_hw *hw)\n{\n\tstruct e1000_bus_info *bus = &hw->bus;\n\n\tDEBUGFUNC(\"e1000_get_bus_info_pcie_vf\");\n\n\t/* Do not set type PCI-E because we don't want disable master to run */\n\tbus->type = e1000_bus_type_reserved;\n\tbus->speed = e1000_bus_speed_2500;\n\n\treturn 0;\n}\n\n/**\n * e1000_get_link_up_info_vf - Gets link info.\n * @hw: pointer to the HW structure\n * @speed: pointer to 16 bit value to store link speed.\n * @duplex: pointer to 16 bit value to store duplex.\n *\n * Since we cannot read the PHY and get accurate link info, we must rely upon\n * the status register's data which is often stale and inaccurate.\n **/\nSTATIC s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t u16 *duplex)\n{\n\ts32 status;\n\n\tDEBUGFUNC(\"e1000_get_link_up_info_vf\");\n\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\tif (status & E1000_STATUS_SPEED_1000) {\n\t\t*speed = SPEED_1000;\n\t\tDEBUGOUT(\"1000 Mbs, \");\n\t} else if (status & E1000_STATUS_SPEED_100) {\n\t\t*speed = SPEED_100;\n\t\tDEBUGOUT(\"100 Mbs, \");\n\t} else {\n\t\t*speed = SPEED_10;\n\t\tDEBUGOUT(\"10 Mbs, \");\n\t}\n\n\tif (status & E1000_STATUS_FD) {\n\t\t*duplex = FULL_DUPLEX;\n\t\tDEBUGOUT(\"Full Duplex\\n\");\n\t} else {\n\t\t*duplex = HALF_DUPLEX;\n\t\tDEBUGOUT(\"Half Duplex\\n\");\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_reset_hw_vf - Resets the HW\n * @hw: pointer to the HW structure\n *\n * VF's provide a function level reset. This is done using bit 26 of ctrl_reg.\n * This is all the reset we can perform on a VF.\n **/\nSTATIC s32 e1000_reset_hw_vf(struct e1000_hw *hw)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tu32 timeout = E1000_VF_INIT_TIMEOUT;\n\ts32 ret_val = -E1000_ERR_MAC_INIT;\n\tu32 ctrl, msgbuf[3];\n\tu8 *addr = (u8 *)(&msgbuf[1]);\n\n\tDEBUGFUNC(\"e1000_reset_hw_vf\");\n\n\tDEBUGOUT(\"Issuing a function level reset to MAC\\n\");\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);\n\n\t/* we cannot reset while the RSTI / RSTD bits are asserted */\n\twhile (!mbx->ops.check_for_rst(hw, 0) && timeout) {\n\t\ttimeout--;\n\t\tusec_delay(5);\n\t}\n\n\tif (timeout) {\n\t\t/* mailbox timeout can now become active */\n\t\tmbx->timeout = E1000_VF_MBX_INIT_TIMEOUT;\n\n\t\tmsgbuf[0] = E1000_VF_RESET;\n\t\tmbx->ops.write_posted(hw, msgbuf, 1, 0);\n\n\t\tmsec_delay(10);\n\n\t\t/* set our \"perm_addr\" based on info provided by PF */\n\t\tret_val = mbx->ops.read_posted(hw, msgbuf, 3, 0);\n\t\tif (!ret_val) {\n\t\t\tif (msgbuf[0] == (E1000_VF_RESET |\n\t\t\t E1000_VT_MSGTYPE_ACK))\n\t\t\t\tmemcpy(hw->mac.perm_addr, addr, 6);\n\t\t\telse\n\t\t\t\tret_val = -E1000_ERR_MAC_INIT;\n\t\t}\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_hw_vf - Inits the HW\n * @hw: pointer to the HW structure\n *\n * Not much to do here except clear the PF Reset indication if there is one.\n **/\nSTATIC s32 e1000_init_hw_vf(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_hw_vf\");\n\n\t/* attempt to set and restore our mac address */\n\te1000_rar_set_vf(hw, hw->mac.addr, 0);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_rar_set_vf - set device MAC address\n * @hw: pointer to the HW structure\n * @addr: pointer to the receive address\n * @index receive address array register\n **/\nSTATIC void e1000_rar_set_vf(struct e1000_hw *hw, u8 *addr,\n\t\t\t u32 E1000_UNUSEDARG index)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tu32 msgbuf[3];\n\tu8 *msg_addr = (u8 *)(&msgbuf[1]);\n\ts32 ret_val;\n\n\tUNREFERENCED_1PARAMETER(index);\n\tmemset(msgbuf, 0, 12);\n\tmsgbuf[0] = E1000_VF_SET_MAC_ADDR;\n\tmemcpy(msg_addr, addr, 6);\n\tret_val = mbx->ops.write_posted(hw, msgbuf, 3, 0);\n\n\tif (!ret_val)\n\t\tret_val = mbx->ops.read_posted(hw, msgbuf, 3, 0);\n\n\tmsgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;\n\n\t/* if nacked the address was rejected, use \"perm_addr\" */\n\tif (!ret_val &&\n\t (msgbuf[0] == (E1000_VF_SET_MAC_ADDR | E1000_VT_MSGTYPE_NACK)))\n\t\te1000_read_mac_addr_vf(hw);\n}\n\n/**\n * e1000_hash_mc_addr_vf - Generate a multicast hash value\n * @hw: pointer to the HW structure\n * @mc_addr: pointer to a multicast address\n *\n * Generates a multicast address hash value which is used to determine\n * the multicast filter table array address and new table value.\n **/\nSTATIC u32 e1000_hash_mc_addr_vf(struct e1000_hw *hw, u8 *mc_addr)\n{\n\tu32 hash_value, hash_mask;\n\tu8 bit_shift = 0;\n\n\tDEBUGFUNC(\"e1000_hash_mc_addr_generic\");\n\n\t/* Register count multiplied by bits per register */\n\thash_mask = (hw->mac.mta_reg_count * 32) - 1;\n\n\t/*\n\t * The bit_shift is the number of left-shifts\n\t * where 0xFF would still fall within the hash mask.\n\t */\n\twhile (hash_mask >> bit_shift != 0xFF)\n\t\tbit_shift++;\n\n\thash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |\n\t\t\t\t (((u16) mc_addr[5]) << bit_shift)));\n\n\treturn hash_value;\n}\n\nSTATIC void e1000_write_msg_read_ack(struct e1000_hw *hw,\n\t\t\t\t u32 *msg, u16 size)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tu32 retmsg[E1000_VFMAILBOX_SIZE];\n\ts32 retval = mbx->ops.write_posted(hw, msg, size, 0);\n\n\tif (!retval)\n\t\tmbx->ops.read_posted(hw, retmsg, E1000_VFMAILBOX_SIZE, 0);\n}\n\n/**\n * e1000_update_mc_addr_list_vf - Update Multicast addresses\n * @hw: pointer to the HW structure\n * @mc_addr_list: array of multicast addresses to program\n * @mc_addr_count: number of multicast addresses to program\n *\n * Updates the Multicast Table Array.\n * The caller must have a packed mc_addr_list of multicast addresses.\n **/\nvoid e1000_update_mc_addr_list_vf(struct e1000_hw *hw,\n\t\t\t\t u8 *mc_addr_list, u32 mc_addr_count)\n{\n\tu32 msgbuf[E1000_VFMAILBOX_SIZE];\n\tu16 *hash_list = (u16 *)&msgbuf[1];\n\tu32 hash_value;\n\tu32 i;\n\n\tDEBUGFUNC(\"e1000_update_mc_addr_list_vf\");\n\n\t/* Each entry in the list uses 1 16 bit word. We have 30\n\t * 16 bit words available in our HW msg buffer (minus 1 for the\n\t * msg type). That's 30 hash values if we pack 'em right. If\n\t * there are more than 30 MC addresses to add then punt the\n\t * extras for now and then add code to handle more than 30 later.\n\t * It would be unusual for a server to request that many multi-cast\n\t * addresses except for in large enterprise network environments.\n\t */\n\n\tDEBUGOUT1(\"MC Addr Count = %d\\n\", mc_addr_count);\n\n\tif (mc_addr_count > 30) {\n\t\tmsgbuf[0] |= E1000_VF_SET_MULTICAST_OVERFLOW;\n\t\tmc_addr_count = 30;\n\t}\n\n\tmsgbuf[0] = E1000_VF_SET_MULTICAST;\n\tmsgbuf[0] |= mc_addr_count << E1000_VT_MSGINFO_SHIFT;\n\n\tfor (i = 0; i < mc_addr_count; i++) {\n\t\thash_value = e1000_hash_mc_addr_vf(hw, mc_addr_list);\n\t\tDEBUGOUT1(\"Hash value = 0x%03X\\n\", hash_value);\n\t\thash_list[i] = hash_value & 0x0FFF;\n\t\tmc_addr_list += ETH_ADDR_LEN;\n\t}\n\n\te1000_write_msg_read_ack(hw, msgbuf, E1000_VFMAILBOX_SIZE);\n}\n\n/**\n * e1000_vfta_set_vf - Set/Unset vlan filter table address\n * @hw: pointer to the HW structure\n * @vid: determines the vfta register and bit to set/unset\n * @set: if true then set bit, else clear bit\n **/\nvoid e1000_vfta_set_vf(struct e1000_hw *hw, u16 vid, bool set)\n{\n\tu32 msgbuf[2];\n\n\tmsgbuf[0] = E1000_VF_SET_VLAN;\n\tmsgbuf[1] = vid;\n\t/* Setting the 8 bit field MSG INFO to TRUE indicates \"add\" */\n\tif (set)\n\t\tmsgbuf[0] |= E1000_VF_SET_VLAN_ADD;\n\n\te1000_write_msg_read_ack(hw, msgbuf, 2);\n}\n\n/** e1000_rlpml_set_vf - Set the maximum receive packet length\n * @hw: pointer to the HW structure\n * @max_size: value to assign to max frame size\n **/\nvoid e1000_rlpml_set_vf(struct e1000_hw *hw, u16 max_size)\n{\n\tu32 msgbuf[2];\n\n\tmsgbuf[0] = E1000_VF_SET_LPE;\n\tmsgbuf[1] = max_size;\n\n\te1000_write_msg_read_ack(hw, msgbuf, 2);\n}\n\n/**\n * e1000_promisc_set_vf - Set flags for Unicast or Multicast promisc\n * @hw: pointer to the HW structure\n * @uni: boolean indicating unicast promisc status\n * @multi: boolean indicating multicast promisc status\n **/\ns32 e1000_promisc_set_vf(struct e1000_hw *hw, enum e1000_promisc_type type)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tu32 msgbuf = E1000_VF_SET_PROMISC;\n\ts32 ret_val;\n\n\tswitch (type) {\n\tcase e1000_promisc_multicast:\n\t\tmsgbuf |= E1000_VF_SET_PROMISC_MULTICAST;\n\t\tbreak;\n\tcase e1000_promisc_enabled:\n\t\tmsgbuf |= E1000_VF_SET_PROMISC_MULTICAST;\n\tcase e1000_promisc_unicast:\n\t\tmsgbuf |= E1000_VF_SET_PROMISC_UNICAST;\n\tcase e1000_promisc_disabled:\n\t\tbreak;\n\tdefault:\n\t\treturn -E1000_ERR_MAC_INIT;\n\t}\n\n\t ret_val = mbx->ops.write_posted(hw, &msgbuf, 1, 0);\n\n\tif (!ret_val)\n\t\tret_val = mbx->ops.read_posted(hw, &msgbuf, 1, 0);\n\n\tif (!ret_val && !(msgbuf & E1000_VT_MSGTYPE_ACK))\n\t\tret_val = -E1000_ERR_MAC_INIT;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_mac_addr_vf - Read device MAC address\n * @hw: pointer to the HW structure\n **/\nSTATIC s32 e1000_read_mac_addr_vf(struct e1000_hw *hw)\n{\n\tint i;\n\n\tfor (i = 0; i < ETH_ADDR_LEN; i++)\n\t\thw->mac.addr[i] = hw->mac.perm_addr[i];\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_check_for_link_vf - Check for link for a virtual interface\n * @hw: pointer to the HW structure\n *\n * Checks to see if the underlying PF is still talking to the VF and\n * if it is then it reports the link state to the hardware, otherwise\n * it reports link down and returns an error.\n **/\nSTATIC s32 e1000_check_for_link_vf(struct e1000_hw *hw)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 in_msg = 0;\n\n\tDEBUGFUNC(\"e1000_check_for_link_vf\");\n\n\t/*\n\t * We only want to run this if there has been a rst asserted.\n\t * in this case that could mean a link change, device reset,\n\t * or a virtual function reset\n\t */\n\n\t/* If we were hit with a reset or timeout drop the link */\n\tif (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)\n\t\tmac->get_link_status = true;\n\n\tif (!mac->get_link_status)\n\t\tgoto out;\n\n\t/* if link status is down no point in checking to see if pf is up */\n\tif (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))\n\t\tgoto out;\n\n\t/* if the read failed it could just be a mailbox collision, best wait\n\t * until we are called again and don't report an error */\n\tif (mbx->ops.read(hw, &in_msg, 1, 0))\n\t\tgoto out;\n\n\t/* if incoming message isn't clear to send we are waiting on response */\n\tif (!(in_msg & E1000_VT_MSGTYPE_CTS)) {\n\t\t/* message is not CTS and is NACK we have lost CTS status */\n\t\tif (in_msg & E1000_VT_MSGTYPE_NACK)\n\t\t\tret_val = -E1000_ERR_MAC_INIT;\n\t\tgoto out;\n\t}\n\n\t/* at this point we know the PF is talking to us, check and see if\n\t * we are still accepting timeout or if we had a timeout failure.\n\t * if we failed then we will need to reinit */\n\tif (!mbx->timeout) {\n\t\tret_val = -E1000_ERR_MAC_INIT;\n\t\tgoto out;\n\t}\n\n\t/* if we passed all the tests above then the link is up and we no\n\t * longer need to check for link */\n\tmac->get_link_status = false;\n\nout:\n\treturn ret_val;\n}\n\n" }, { "path": "drivers/net/e1000/base/e1000_vf.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2014, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _E1000_VF_H_\n#define _E1000_VF_H_\n\n#include \"e1000_osdep.h\"\n#include \"e1000_regs.h\"\n#include \"e1000_defines.h\"\n\nstruct e1000_hw;\n\n#define E1000_DEV_ID_82576_VF\t\t0x10CA\n#define E1000_DEV_ID_I350_VF\t\t0x1520\n\n#define E1000_VF_INIT_TIMEOUT\t\t200 /* Num of retries to clear RSTI */\n\n/* Additional Descriptor Control definitions */\n#define E1000_TXDCTL_QUEUE_ENABLE\t0x02000000 /* Ena specific Tx Queue */\n#define E1000_RXDCTL_QUEUE_ENABLE\t0x02000000 /* Ena specific Rx Queue */\n\n/* SRRCTL bit definitions */\n#define E1000_SRRCTL(_n)\t((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \\\n\t\t\t\t (0x0C00C + ((_n) * 0x40)))\n#define E1000_SRRCTL_BSIZEPKT_SHIFT\t\t10 /* Shift _right_ */\n#define E1000_SRRCTL_BSIZEHDRSIZE_MASK\t\t0x00000F00\n#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT\t\t2 /* Shift _left_ */\n#define E1000_SRRCTL_DESCTYPE_LEGACY\t\t0x00000000\n#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF\t0x02000000\n#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT\t\t0x04000000\n#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS\t0x0A000000\n#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION\t0x06000000\n#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000\n#define E1000_SRRCTL_DESCTYPE_MASK\t\t0x0E000000\n#define E1000_SRRCTL_DROP_EN\t\t\t0x80000000\n\n#define E1000_SRRCTL_BSIZEPKT_MASK\t0x0000007F\n#define E1000_SRRCTL_BSIZEHDR_MASK\t0x00003F00\n\n/* Interrupt Defines */\n#define E1000_EICR\t\t0x01580 /* Ext. Interrupt Cause Read - R/clr */\n#define E1000_EITR(_n)\t\t(0x01680 + ((_n) << 2))\n#define E1000_EICS\t\t0x01520 /* Ext. Intr Cause Set -W0 */\n#define E1000_EIMS\t\t0x01524 /* Ext. Intr Mask Set/Read -RW */\n#define E1000_EIMC\t\t0x01528 /* Ext. Intr Mask Clear -WO */\n#define E1000_EIAC\t\t0x0152C /* Ext. Intr Auto Clear -RW */\n#define E1000_EIAM\t\t0x01530 /* Ext. Intr Ack Auto Clear Mask -RW */\n#define E1000_IVAR0\t\t0x01700 /* Intr Vector Alloc (array) -RW */\n#define E1000_IVAR_MISC\t\t0x01740 /* IVAR for \"other\" causes -RW */\n#define E1000_IVAR_VALID\t0x80\n\n/* Receive Descriptor - Advanced */\nunion e1000_adv_rx_desc {\n\tstruct {\n\t\tu64 pkt_addr; /* Packet buffer address */\n\t\tu64 hdr_addr; /* Header buffer address */\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tu32 data;\n\t\t\t\tstruct {\n\t\t\t\t\t/* RSS type, Packet type */\n\t\t\t\t\tu16 pkt_info;\n\t\t\t\t\t/* Split Header, header buffer len */\n\t\t\t\t\tu16 hdr_info;\n\t\t\t\t} hs_rss;\n\t\t\t} lo_dword;\n\t\t\tunion {\n\t\t\t\tu32 rss; /* RSS Hash */\n\t\t\t\tstruct {\n\t\t\t\t\tu16 ip_id; /* IP id */\n\t\t\t\t\tu16 csum; /* Packet Checksum */\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\tu32 status_error; /* ext status/error */\n\t\t\tu16 length; /* Packet length */\n\t\t\tu16 vlan; /* VLAN tag */\n\t\t} upper;\n\t} wb; /* writeback */\n};\n\n#define E1000_RXDADV_HDRBUFLEN_MASK\t0x7FE0\n#define E1000_RXDADV_HDRBUFLEN_SHIFT\t5\n\n/* Transmit Descriptor - Advanced */\nunion e1000_adv_tx_desc {\n\tstruct {\n\t\tu64 buffer_addr; /* Address of descriptor's data buf */\n\t\tu32 cmd_type_len;\n\t\tu32 olinfo_status;\n\t} read;\n\tstruct {\n\t\tu64 rsvd; /* Reserved */\n\t\tu32 nxtseq_seed;\n\t\tu32 status;\n\t} wb;\n};\n\n/* Adv Transmit Descriptor Config Masks */\n#define E1000_ADVTXD_DTYP_CTXT\t0x00200000 /* Advanced Context Descriptor */\n#define E1000_ADVTXD_DTYP_DATA\t0x00300000 /* Advanced Data Descriptor */\n#define E1000_ADVTXD_DCMD_EOP\t0x01000000 /* End of Packet */\n#define E1000_ADVTXD_DCMD_IFCS\t0x02000000 /* Insert FCS (Ethernet CRC) */\n#define E1000_ADVTXD_DCMD_RS\t0x08000000 /* Report Status */\n#define E1000_ADVTXD_DCMD_DEXT\t0x20000000 /* Descriptor extension (1=Adv) */\n#define E1000_ADVTXD_DCMD_VLE\t0x40000000 /* VLAN pkt enable */\n#define E1000_ADVTXD_DCMD_TSE\t0x80000000 /* TCP Seg enable */\n#define E1000_ADVTXD_PAYLEN_SHIFT\t14 /* Adv desc PAYLEN shift */\n\n/* Context descriptors */\nstruct e1000_adv_tx_context_desc {\n\tu32 vlan_macip_lens;\n\tu32 seqnum_seed;\n\tu32 type_tucmd_mlhl;\n\tu32 mss_l4len_idx;\n};\n\n#define E1000_ADVTXD_MACLEN_SHIFT\t9 /* Adv ctxt desc mac len shift */\n#define E1000_ADVTXD_TUCMD_IPV4\t\t0x00000400 /* IP Packet Type: 1=IPv4 */\n#define E1000_ADVTXD_TUCMD_L4T_TCP\t0x00000800 /* L4 Packet TYPE of TCP */\n#define E1000_ADVTXD_L4LEN_SHIFT\t8 /* Adv ctxt L4LEN shift */\n#define E1000_ADVTXD_MSS_SHIFT\t\t16 /* Adv ctxt MSS shift */\n\nenum e1000_mac_type {\n\te1000_undefined = 0,\n\te1000_vfadapt,\n\te1000_vfadapt_i350,\n\te1000_num_macs /* List is 1-based, so subtract 1 for true count. */\n};\n\nstruct e1000_vf_stats {\n\tu64 base_gprc;\n\tu64 base_gptc;\n\tu64 base_gorc;\n\tu64 base_gotc;\n\tu64 base_mprc;\n\tu64 base_gotlbc;\n\tu64 base_gptlbc;\n\tu64 base_gorlbc;\n\tu64 base_gprlbc;\n\n\tu32 last_gprc;\n\tu32 last_gptc;\n\tu32 last_gorc;\n\tu32 last_gotc;\n\tu32 last_mprc;\n\tu32 last_gotlbc;\n\tu32 last_gptlbc;\n\tu32 last_gorlbc;\n\tu32 last_gprlbc;\n\n\tu64 gprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 mprc;\n\tu64 gotlbc;\n\tu64 gptlbc;\n\tu64 gorlbc;\n\tu64 gprlbc;\n};\n\n#include \"e1000_mbx.h\"\n\nstruct e1000_mac_operations {\n\t/* Function pointers for the MAC. */\n\ts32 (*init_params)(struct e1000_hw *);\n\ts32 (*check_for_link)(struct e1000_hw *);\n\tvoid (*clear_vfta)(struct e1000_hw *);\n\ts32 (*get_bus_info)(struct e1000_hw *);\n\ts32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);\n\tvoid (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);\n\ts32 (*reset_hw)(struct e1000_hw *);\n\ts32 (*init_hw)(struct e1000_hw *);\n\ts32 (*setup_link)(struct e1000_hw *);\n\tvoid (*write_vfta)(struct e1000_hw *, u32, u32);\n\tvoid (*rar_set)(struct e1000_hw *, u8*, u32);\n\ts32 (*read_mac_addr)(struct e1000_hw *);\n};\n\nstruct e1000_mac_info {\n\tstruct e1000_mac_operations ops;\n\tu8 addr[6];\n\tu8 perm_addr[6];\n\n\tenum e1000_mac_type type;\n\n\tu16 mta_reg_count;\n\tu16 rar_entry_count;\n\n\tbool get_link_status;\n};\n\nstruct e1000_mbx_operations {\n\ts32 (*init_params)(struct e1000_hw *hw);\n\ts32 (*read)(struct e1000_hw *, u32 *, u16, u16);\n\ts32 (*write)(struct e1000_hw *, u32 *, u16, u16);\n\ts32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);\n\ts32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);\n\ts32 (*check_for_msg)(struct e1000_hw *, u16);\n\ts32 (*check_for_ack)(struct e1000_hw *, u16);\n\ts32 (*check_for_rst)(struct e1000_hw *, u16);\n};\n\nstruct e1000_mbx_stats {\n\tu32 msgs_tx;\n\tu32 msgs_rx;\n\n\tu32 acks;\n\tu32 reqs;\n\tu32 rsts;\n};\n\nstruct e1000_mbx_info {\n\tstruct e1000_mbx_operations ops;\n\tstruct e1000_mbx_stats stats;\n\tu32 timeout;\n\tu32 usec_delay;\n\tu16 size;\n};\n\nstruct e1000_dev_spec_vf {\n\tu32 vf_number;\n\tu32 v2p_mailbox;\n};\n\nstruct e1000_hw {\n\tvoid *back;\n\n\tu8 *hw_addr;\n\tu8 *flash_address;\n\tunsigned long io_base;\n\n\tstruct e1000_mac_info mac;\n\tstruct e1000_mbx_info mbx;\n\n\tunion {\n\t\tstruct e1000_dev_spec_vf vf;\n\t} dev_spec;\n\n\tu16 device_id;\n\tu16 subsystem_vendor_id;\n\tu16 subsystem_device_id;\n\tu16 vendor_id;\n\n\tu8 revision_id;\n};\n\nenum e1000_promisc_type {\n\te1000_promisc_disabled = 0, /* all promisc modes disabled */\n\te1000_promisc_unicast = 1, /* unicast promiscuous enabled */\n\te1000_promisc_multicast = 2, /* multicast promiscuous enabled */\n\te1000_promisc_enabled = 3, /* both uni and multicast promisc */\n\te1000_num_promisc_types\n};\n\n/* These functions must be implemented by drivers */\ns32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);\nvoid e1000_vfta_set_vf(struct e1000_hw *, u16, bool);\nvoid e1000_rlpml_set_vf(struct e1000_hw *, u16);\ns32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type);\n#endif /* _E1000_VF_H_ */\n" }, { "path": "drivers/net/e1000/e1000_ethdev.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _E1000_ETHDEV_H_\n#define _E1000_ETHDEV_H_\n\n/* need update link, bit flag */\n#define E1000_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)\n#define E1000_FLAG_MAILBOX (uint32_t)(1 << 1)\n\n/*\n * Defines that were not part of e1000_hw.h as they are not used by the FreeBSD\n * driver.\n */\n#define E1000_ADVTXD_POPTS_TXSM 0x00000200 /* L4 Checksum offload request */\n#define E1000_ADVTXD_POPTS_IXSM 0x00000100 /* IP Checksum offload request */\n#define E1000_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE of Reserved */\n#define E1000_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */\n#define E1000_RXD_ERR_CKSUM_BIT 29\n#define E1000_RXD_ERR_CKSUM_MSK 3\n#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */\n#define E1000_CTRL_EXT_EXTEND_VLAN (1<<26) /* EXTENDED VLAN */\n#define IGB_VFTA_SIZE 128\n\n#define IGB_MAX_RX_QUEUE_NUM 8\n#define IGB_MAX_RX_QUEUE_NUM_82576 16\n\n#define E1000_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */\n#define E1000_SYN_FILTER_QUEUE 0x0000000E /* syn filter queue field */\n#define E1000_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field */\n#define E1000_RFCTL_SYNQFP 0x00080000 /* SYNQFP in RFCTL register */\n\n#define E1000_ETQF_ETHERTYPE 0x0000FFFF\n#define E1000_ETQF_QUEUE 0x00070000\n#define E1000_ETQF_QUEUE_SHIFT 16\n#define E1000_MAX_ETQF_FILTERS 8\n\n#define E1000_IMIR_DSTPORT 0x0000FFFF\n#define E1000_IMIR_PRIORITY 0xE0000000\n#define E1000_MAX_TTQF_FILTERS 8\n#define E1000_2TUPLE_MAX_PRI 7\n\n#define E1000_MAX_FLEX_FILTERS 8\n#define E1000_MAX_FHFT 4\n#define E1000_MAX_FHFT_EXT 4\n#define E1000_FHFT_SIZE_IN_DWD 64\n#define E1000_MAX_FLEX_FILTER_PRI 7\n#define E1000_MAX_FLEX_FILTER_LEN 128\n#define E1000_MAX_FLEX_FILTER_DWDS \\\n\t(E1000_MAX_FLEX_FILTER_LEN / sizeof(uint32_t))\n#define E1000_FLEX_FILTERS_MASK_SIZE \\\n\t(E1000_MAX_FLEX_FILTER_DWDS / 4)\n#define E1000_FHFT_QUEUEING_LEN 0x0000007F\n#define E1000_FHFT_QUEUEING_QUEUE 0x00000700\n#define E1000_FHFT_QUEUEING_PRIO 0x00070000\n#define E1000_FHFT_QUEUEING_OFFSET 0xFC\n#define E1000_FHFT_QUEUEING_QUEUE_SHIFT 8\n#define E1000_FHFT_QUEUEING_PRIO_SHIFT 16\n#define E1000_WUFC_FLEX_HQ 0x00004000\n\n#define E1000_SPQF_SRCPORT 0x0000FFFF\n\n#define E1000_MAX_FTQF_FILTERS 8\n#define E1000_FTQF_PROTOCOL_MASK 0x000000FF\n#define E1000_FTQF_5TUPLE_MASK_SHIFT 28\n#define E1000_FTQF_QUEUE_MASK 0x03ff0000\n#define E1000_FTQF_QUEUE_SHIFT 16\n#define E1000_FTQF_QUEUE_ENABLE 0x00000100\n\n#define IGB_RSS_OFFLOAD_ALL ( \\\n\tETH_RSS_IPV4 | \\\n\tETH_RSS_NONFRAG_IPV4_TCP | \\\n\tETH_RSS_NONFRAG_IPV4_UDP | \\\n\tETH_RSS_IPV6 | \\\n\tETH_RSS_NONFRAG_IPV6_TCP | \\\n\tETH_RSS_NONFRAG_IPV6_UDP | \\\n\tETH_RSS_IPV6_EX | \\\n\tETH_RSS_IPV6_TCP_EX | \\\n\tETH_RSS_IPV6_UDP_EX)\n\n/* structure for interrupt relative data */\nstruct e1000_interrupt {\n\tuint32_t flags;\n\tuint32_t mask;\n};\n\n/* local vfta copy */\nstruct e1000_vfta {\n\tuint32_t vfta[IGB_VFTA_SIZE];\n};\n\n/*\n * VF data which used by PF host only\n */\n#define E1000_MAX_VF_MC_ENTRIES 30\nstruct e1000_vf_info {\n\tuint8_t vf_mac_addresses[ETHER_ADDR_LEN];\n\tuint16_t vf_mc_hashes[E1000_MAX_VF_MC_ENTRIES];\n\tuint16_t num_vf_mc_hashes;\n\tuint16_t default_vf_vlan_id;\n\tuint16_t vlans_enabled;\n\tuint16_t pf_qos;\n\tuint16_t vlan_count;\n\tuint16_t tx_rate;\n};\n\nTAILQ_HEAD(e1000_flex_filter_list, e1000_flex_filter);\n\nstruct e1000_flex_filter_info {\n\tuint16_t len;\n\tuint32_t dwords[E1000_MAX_FLEX_FILTER_DWDS]; /* flex bytes in dword. */\n\t/* if mask bit is 1b, do not compare corresponding byte in dwords. */\n\tuint8_t mask[E1000_FLEX_FILTERS_MASK_SIZE];\n\tuint8_t priority;\n};\n\n/* Flex filter structure */\nstruct e1000_flex_filter {\n\tTAILQ_ENTRY(e1000_flex_filter) entries;\n\tuint16_t index; /* index of flex filter */\n\tstruct e1000_flex_filter_info filter_info;\n\tuint16_t queue; /* rx queue assigned to */\n};\n\nTAILQ_HEAD(e1000_5tuple_filter_list, e1000_5tuple_filter);\nTAILQ_HEAD(e1000_2tuple_filter_list, e1000_2tuple_filter);\n\nstruct e1000_5tuple_filter_info {\n\tuint32_t dst_ip;\n\tuint32_t src_ip;\n\tuint16_t dst_port;\n\tuint16_t src_port;\n\tuint8_t proto; /* l4 protocol. */\n\t/* the packet matched above 5tuple and contain any set bit will hit this filter. */\n\tuint8_t tcp_flags;\n\tuint8_t priority; /* seven levels (001b-111b), 111b is highest,\n\t\t\t\t used when more than one filter matches. */\n\tuint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */\n\t\tsrc_ip_mask:1, /* if mask is 1b, do not compare src ip. */\n\t\tdst_port_mask:1, /* if mask is 1b, do not compare dst port. */\n\t\tsrc_port_mask:1, /* if mask is 1b, do not compare src port. */\n\t\tproto_mask:1; /* if mask is 1b, do not compare protocol. */\n};\n\nstruct e1000_2tuple_filter_info {\n\tuint16_t dst_port;\n\tuint8_t proto; /* l4 protocol. */\n\t/* the packet matched above 2tuple and contain any set bit will hit this filter. */\n\tuint8_t tcp_flags;\n\tuint8_t priority; /* seven levels (001b-111b), 111b is highest,\n\t\t\t\t used when more than one filter matches. */\n\tuint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */\n\t\tsrc_ip_mask:1, /* if mask is 1b, do not compare src ip. */\n\t\tdst_port_mask:1, /* if mask is 1b, do not compare dst port. */\n\t\tsrc_port_mask:1, /* if mask is 1b, do not compare src port. */\n\t\tproto_mask:1; /* if mask is 1b, do not compare protocol. */\n};\n\n/* 5tuple filter structure */\nstruct e1000_5tuple_filter {\n\tTAILQ_ENTRY(e1000_5tuple_filter) entries;\n\tuint16_t index; /* the index of 5tuple filter */\n\tstruct e1000_5tuple_filter_info filter_info;\n\tuint16_t queue; /* rx queue assigned to */\n};\n\n/* 2tuple filter structure */\nstruct e1000_2tuple_filter {\n\tTAILQ_ENTRY(e1000_2tuple_filter) entries;\n\tuint16_t index; /* the index of 2tuple filter */\n\tstruct e1000_2tuple_filter_info filter_info;\n\tuint16_t queue; /* rx queue assigned to */\n};\n\n/*\n * Structure to store filters' info.\n */\nstruct e1000_filter_info {\n\tuint8_t ethertype_mask; /* Bit mask for every used ethertype filter */\n\t/* store used ethertype filters*/\n\tuint16_t ethertype_filters[E1000_MAX_ETQF_FILTERS];\n\tuint8_t flex_mask;\t/* Bit mask for every used flex filter */\n\tstruct e1000_flex_filter_list flex_list;\n\t/* Bit mask for every used 5tuple filter */\n\tuint8_t fivetuple_mask;\n\tstruct e1000_5tuple_filter_list fivetuple_list;\n\t/* Bit mask for every used 2tuple filter */\n\tuint8_t twotuple_mask;\n\tstruct e1000_2tuple_filter_list twotuple_list;\n};\n\n/*\n * Structure to store private data for each driver instance (for each port).\n */\nstruct e1000_adapter {\n\tstruct e1000_hw hw;\n\tstruct e1000_hw_stats stats;\n\tstruct e1000_interrupt intr;\n\tstruct e1000_vfta shadow_vfta;\n\tstruct e1000_vf_info *vfdata;\n\tstruct e1000_filter_info filter;\n\tbool stopped;\n};\n\n#define E1000_DEV_PRIVATE(adapter) \\\n\t((struct e1000_adapter *)adapter)\n\n#define E1000_DEV_PRIVATE_TO_HW(adapter) \\\n\t(&((struct e1000_adapter *)adapter)->hw)\n\n#define E1000_DEV_PRIVATE_TO_STATS(adapter) \\\n\t(&((struct e1000_adapter *)adapter)->stats)\n\n#define E1000_DEV_PRIVATE_TO_INTR(adapter) \\\n\t(&((struct e1000_adapter *)adapter)->intr)\n\n#define E1000_DEV_PRIVATE_TO_VFTA(adapter) \\\n\t(&((struct e1000_adapter *)adapter)->shadow_vfta)\n\n#define E1000_DEV_PRIVATE_TO_P_VFDATA(adapter) \\\n (&((struct e1000_adapter *)adapter)->vfdata)\n\n#define E1000_DEV_PRIVATE_TO_FILTER_INFO(adapter) \\\n\t(&((struct e1000_adapter *)adapter)->filter)\n\n/*\n * RX/TX IGB function prototypes\n */\nvoid eth_igb_tx_queue_release(void *txq);\nvoid eth_igb_rx_queue_release(void *rxq);\nvoid igb_dev_clear_queues(struct rte_eth_dev *dev);\nvoid igb_dev_free_queues(struct rte_eth_dev *dev);\n\nint eth_igb_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n\t\tuint16_t nb_rx_desc, unsigned int socket_id,\n\t\tconst struct rte_eth_rxconf *rx_conf,\n\t\tstruct rte_mempool *mb_pool);\n\nuint32_t eth_igb_rx_queue_count(struct rte_eth_dev *dev,\n\t\tuint16_t rx_queue_id);\n\nint eth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset);\n\nint eth_igb_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n\t\tuint16_t nb_tx_desc, unsigned int socket_id,\n\t\tconst struct rte_eth_txconf *tx_conf);\n\nint eth_igb_rx_init(struct rte_eth_dev *dev);\n\nvoid eth_igb_tx_init(struct rte_eth_dev *dev);\n\nuint16_t eth_igb_xmit_pkts(void *txq, struct rte_mbuf **tx_pkts,\n\t\tuint16_t nb_pkts);\n\nuint16_t eth_igb_recv_pkts(void *rxq, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts);\n\nuint16_t eth_igb_recv_scattered_pkts(void *rxq,\n\t\tstruct rte_mbuf **rx_pkts, uint16_t nb_pkts);\n\nint eth_igb_rss_hash_update(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_conf *rss_conf);\n\nint eth_igb_rss_hash_conf_get(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_conf *rss_conf);\n\nint eth_igbvf_rx_init(struct rte_eth_dev *dev);\n\nvoid eth_igbvf_tx_init(struct rte_eth_dev *dev);\n\n/*\n * misc function prototypes\n */\nvoid igb_pf_host_init(struct rte_eth_dev *eth_dev);\n\nvoid igb_pf_mbx_process(struct rte_eth_dev *eth_dev);\n\nint igb_pf_host_configure(struct rte_eth_dev *eth_dev);\n\n/*\n * RX/TX EM function prototypes\n */\nvoid eth_em_tx_queue_release(void *txq);\nvoid eth_em_rx_queue_release(void *rxq);\n\nvoid em_dev_clear_queues(struct rte_eth_dev *dev);\nvoid em_dev_free_queues(struct rte_eth_dev *dev);\n\nint eth_em_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n\t\tuint16_t nb_rx_desc, unsigned int socket_id,\n\t\tconst struct rte_eth_rxconf *rx_conf,\n\t\tstruct rte_mempool *mb_pool);\n\nuint32_t eth_em_rx_queue_count(struct rte_eth_dev *dev,\n\t\tuint16_t rx_queue_id);\n\nint eth_em_rx_descriptor_done(void *rx_queue, uint16_t offset);\n\nint eth_em_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n\t\tuint16_t nb_tx_desc, unsigned int socket_id,\n\t\tconst struct rte_eth_txconf *tx_conf);\n\nint eth_em_rx_init(struct rte_eth_dev *dev);\n\nvoid eth_em_tx_init(struct rte_eth_dev *dev);\n\nuint16_t eth_em_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t\tuint16_t nb_pkts);\n\nuint16_t eth_em_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts);\n\nuint16_t eth_em_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts);\n\nvoid igb_pf_host_uninit(struct rte_eth_dev *dev);\n\n#endif /* _E1000_ETHDEV_H_ */\n" }, { "path": "drivers/net/e1000/e1000_logs.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _E1000_LOGS_H_\n#define _E1000_LOGS_H_\n\n#define PMD_INIT_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ##args)\n\n#ifdef RTE_LIBRTE_E1000_DEBUG_INIT\n#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, \" >>\")\n#else\n#define PMD_INIT_FUNC_TRACE() do { } while (0)\n#endif\n\n#ifdef RTE_LIBRTE_E1000_DEBUG_RX\n#define PMD_RX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_RX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_E1000_DEBUG_TX\n#define PMD_TX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_TX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_E1000_DEBUG_TX_FREE\n#define PMD_TX_FREE_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_TX_FREE_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_E1000_DEBUG_DRIVER\n#define PMD_DRV_LOG_RAW(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt, __func__, ## args)\n#else\n#define PMD_DRV_LOG_RAW(level, fmt, args...) do { } while (0)\n#endif\n\n#define PMD_DRV_LOG(level, fmt, args...) \\\n\tPMD_DRV_LOG_RAW(level, fmt \"\\n\", ## args)\n\n#endif /* _E1000_LOGS_H_ */\n" }, { "path": "drivers/net/e1000/em_ethdev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"e1000_logs.h\"\n#include \"base/e1000_api.h\"\n#include \"e1000_ethdev.h\"\n\n#define EM_EIAC\t\t\t0x000DC\n\n#define PMD_ROUNDUP(x,y)\t(((x) + (y) - 1)/(y) * (y))\n\n\nstatic int eth_em_configure(struct rte_eth_dev *dev);\nstatic int eth_em_start(struct rte_eth_dev *dev);\nstatic void eth_em_stop(struct rte_eth_dev *dev);\nstatic void eth_em_close(struct rte_eth_dev *dev);\nstatic void eth_em_promiscuous_enable(struct rte_eth_dev *dev);\nstatic void eth_em_promiscuous_disable(struct rte_eth_dev *dev);\nstatic void eth_em_allmulticast_enable(struct rte_eth_dev *dev);\nstatic void eth_em_allmulticast_disable(struct rte_eth_dev *dev);\nstatic int eth_em_link_update(struct rte_eth_dev *dev,\n\t\t\t\tint wait_to_complete);\nstatic void eth_em_stats_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_stats *rte_stats);\nstatic void eth_em_stats_reset(struct rte_eth_dev *dev);\nstatic void eth_em_infos_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_dev_info *dev_info);\nstatic int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_fc_conf *fc_conf);\nstatic int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_fc_conf *fc_conf);\nstatic int eth_em_interrupt_setup(struct rte_eth_dev *dev);\nstatic int eth_em_interrupt_get_status(struct rte_eth_dev *dev);\nstatic int eth_em_interrupt_action(struct rte_eth_dev *dev);\nstatic void eth_em_interrupt_handler(struct rte_intr_handle *handle,\n\t\t\t\t\t\t\tvoid *param);\n\nstatic int em_hw_init(struct e1000_hw *hw);\nstatic int em_hardware_init(struct e1000_hw *hw);\nstatic void em_hw_control_acquire(struct e1000_hw *hw);\nstatic void em_hw_control_release(struct e1000_hw *hw);\nstatic void em_init_manageability(struct e1000_hw *hw);\nstatic void em_release_manageability(struct e1000_hw *hw);\n\nstatic int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n\nstatic int eth_em_vlan_filter_set(struct rte_eth_dev *dev,\n\t\tuint16_t vlan_id, int on);\nstatic void eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);\nstatic void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);\nstatic void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);\nstatic void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);\nstatic void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);\n\n/*\nstatic void eth_em_vlan_filter_set(struct rte_eth_dev *dev,\n\t\t\t\t\tuint16_t vlan_id, int on);\n*/\nstatic int eth_em_led_on(struct rte_eth_dev *dev);\nstatic int eth_em_led_off(struct rte_eth_dev *dev);\n\nstatic void em_intr_disable(struct e1000_hw *hw);\nstatic int em_get_rx_buffer_size(struct e1000_hw *hw);\nstatic void eth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,\n\t\tuint32_t index, uint32_t pool);\nstatic void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);\n\nstatic int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,\n\t\t\t\t struct ether_addr *mc_addr_set,\n\t\t\t\t uint32_t nb_mc_addr);\n\n#define EM_FC_PAUSE_TIME 0x0680\n#define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */\n#define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */\n\nstatic enum e1000_fc_mode em_fc_setting = e1000_fc_full;\n\n/*\n * The set of PCI devices this driver supports\n */\nstatic const struct rte_pci_id pci_id_em_map[] = {\n\n#define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \"rte_pci_dev_ids.h\"\n\n{0},\n};\n\nstatic const struct eth_dev_ops eth_em_ops = {\n\t.dev_configure = eth_em_configure,\n\t.dev_start = eth_em_start,\n\t.dev_stop = eth_em_stop,\n\t.dev_close = eth_em_close,\n\t.promiscuous_enable = eth_em_promiscuous_enable,\n\t.promiscuous_disable = eth_em_promiscuous_disable,\n\t.allmulticast_enable = eth_em_allmulticast_enable,\n\t.allmulticast_disable = eth_em_allmulticast_disable,\n\t.link_update = eth_em_link_update,\n\t.stats_get = eth_em_stats_get,\n\t.stats_reset = eth_em_stats_reset,\n\t.dev_infos_get = eth_em_infos_get,\n\t.mtu_set = eth_em_mtu_set,\n\t.vlan_filter_set = eth_em_vlan_filter_set,\n\t.vlan_offload_set = eth_em_vlan_offload_set,\n\t.rx_queue_setup = eth_em_rx_queue_setup,\n\t.rx_queue_release = eth_em_rx_queue_release,\n\t.rx_queue_count = eth_em_rx_queue_count,\n\t.rx_descriptor_done = eth_em_rx_descriptor_done,\n\t.tx_queue_setup = eth_em_tx_queue_setup,\n\t.tx_queue_release = eth_em_tx_queue_release,\n\t.dev_led_on = eth_em_led_on,\n\t.dev_led_off = eth_em_led_off,\n\t.flow_ctrl_get = eth_em_flow_ctrl_get,\n\t.flow_ctrl_set = eth_em_flow_ctrl_set,\n\t.mac_addr_add = eth_em_rar_set,\n\t.mac_addr_remove = eth_em_rar_clear,\n\t.set_mc_addr_list = eth_em_set_mc_addr_list,\n};\n\n/**\n * Atomically reads the link status information from global\n * structure rte_eth_dev.\n *\n * @param dev\n * - Pointer to the structure rte_eth_dev to read from.\n * - Pointer to the buffer to be saved with the link status.\n *\n * @return\n * - On success, zero.\n * - On failure, negative value.\n */\nstatic inline int\nrte_em_dev_atomic_read_link_status(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = link;\n\tstruct rte_eth_link *src = &(dev->data->dev_link);\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * Atomically writes the link status information into global\n * structure rte_eth_dev.\n *\n * @param dev\n * - Pointer to the structure rte_eth_dev to read from.\n * - Pointer to the buffer to be saved with the link status.\n *\n * @return\n * - On success, zero.\n * - On failure, negative value.\n */\nstatic inline int\nrte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = &(dev->data->dev_link);\n\tstruct rte_eth_link *src = link;\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic int\neth_em_dev_init(struct rte_eth_dev *eth_dev)\n{\n\tstruct rte_pci_device *pci_dev;\n\tstruct e1000_adapter *adapter =\n\t\tE1000_DEV_PRIVATE(eth_dev->data->dev_private);\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\tstruct e1000_vfta * shadow_vfta =\n\t\tE1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);\n\n\tpci_dev = eth_dev->pci_dev;\n\teth_dev->dev_ops = ð_em_ops;\n\teth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;\n\teth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;\n\n\t/* for secondary processes, we don't initialise any further as primary\n\t * has already done this work. Only check we don't need a different\n\t * RX function */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY){\n\t\tif (eth_dev->data->scattered_rx)\n\t\t\teth_dev->rx_pkt_burst =\n\t\t\t\t(eth_rx_burst_t)ð_em_recv_scattered_pkts;\n\t\treturn 0;\n\t}\n\n\thw->hw_addr = (void *)pci_dev->mem_resource[0].addr;\n\thw->device_id = pci_dev->id.device_id;\n\tadapter->stopped = 0;\n\n\t/* For ICH8 support we'll need to map the flash memory BAR */\n\n\tif (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||\n\t\t\tem_hw_init(hw) != 0) {\n\t\tPMD_INIT_LOG(ERR, \"port_id %d vendorID=0x%x deviceID=0x%x: \"\n\t\t\t\"failed to init HW\",\n\t\t\teth_dev->data->port_id, pci_dev->id.vendor_id,\n\t\t\tpci_dev->id.device_id);\n\t\treturn -(ENODEV);\n\t}\n\n\t/* Allocate memory for storing MAC addresses */\n\teth_dev->data->mac_addrs = rte_zmalloc(\"e1000\", ETHER_ADDR_LEN *\n\t\t\thw->mac.rar_entry_count, 0);\n\tif (eth_dev->data->mac_addrs == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to allocate %d bytes needed to \"\n\t\t\t\"store MAC addresses\",\n\t\t\tETHER_ADDR_LEN * hw->mac.rar_entry_count);\n\t\treturn -(ENOMEM);\n\t}\n\n\t/* Copy the permanent MAC address */\n\tether_addr_copy((struct ether_addr *) hw->mac.addr,\n\t\teth_dev->data->mac_addrs);\n\n\t/* initialize the vfta */\n\tmemset(shadow_vfta, 0, sizeof(*shadow_vfta));\n\n\tPMD_INIT_LOG(DEBUG, \"port_id %d vendorID=0x%x deviceID=0x%x\",\n\t\t eth_dev->data->port_id, pci_dev->id.vendor_id,\n\t\t pci_dev->id.device_id);\n\n\trte_intr_callback_register(&(pci_dev->intr_handle),\n\t\teth_em_interrupt_handler, (void *)eth_dev);\n\n\treturn (0);\n}\n\nstatic int\neth_em_dev_uninit(struct rte_eth_dev *eth_dev)\n{\n\tstruct rte_pci_device *pci_dev;\n\tstruct e1000_adapter *adapter =\n\t\tE1000_DEV_PRIVATE(eth_dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn -EPERM;\n\n\tpci_dev = eth_dev->pci_dev;\n\n\tif (adapter->stopped == 0)\n\t\teth_em_close(eth_dev);\n\n\teth_dev->dev_ops = NULL;\n\teth_dev->rx_pkt_burst = NULL;\n\teth_dev->tx_pkt_burst = NULL;\n\n\trte_free(eth_dev->data->mac_addrs);\n\teth_dev->data->mac_addrs = NULL;\n\n\t/* disable uio intr before callback unregister */\n\trte_intr_disable(&(pci_dev->intr_handle));\n\trte_intr_callback_unregister(&(pci_dev->intr_handle),\n\t\teth_em_interrupt_handler, (void *)eth_dev);\n\n\treturn 0;\n}\n\nstatic struct eth_driver rte_em_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_em_pmd\",\n\t\t.id_table = pci_id_em_map,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |\n\t\t\tRTE_PCI_DRV_DETACHABLE,\n\t},\n\t.eth_dev_init = eth_em_dev_init,\n\t.eth_dev_uninit = eth_em_dev_uninit,\n\t.dev_private_size = sizeof(struct e1000_adapter),\n};\n\nstatic int\nrte_em_pmd_init(const char *name __rte_unused, const char *params __rte_unused)\n{\n\trte_eth_driver_register(&rte_em_pmd);\n\treturn 0;\n}\n\nstatic int\nem_hw_init(struct e1000_hw *hw)\n{\n\tint diag;\n\n\tdiag = hw->mac.ops.init_params(hw);\n\tif (diag != 0) {\n\t\tPMD_INIT_LOG(ERR, \"MAC Initialization Error\");\n\t\treturn diag;\n\t}\n\tdiag = hw->nvm.ops.init_params(hw);\n\tif (diag != 0) {\n\t\tPMD_INIT_LOG(ERR, \"NVM Initialization Error\");\n\t\treturn diag;\n\t}\n\tdiag = hw->phy.ops.init_params(hw);\n\tif (diag != 0) {\n\t\tPMD_INIT_LOG(ERR, \"PHY Initialization Error\");\n\t\treturn diag;\n\t}\n\t(void) e1000_get_bus_info(hw);\n\n\thw->mac.autoneg = 1;\n\thw->phy.autoneg_wait_to_complete = 0;\n\thw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;\n\n\te1000_init_script_state_82541(hw, TRUE);\n\te1000_set_tbi_compatibility_82543(hw, TRUE);\n\n\t/* Copper options */\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\t\thw->phy.mdix = 0; /* AUTO_ALL_MODES */\n\t\thw->phy.disable_polarity_correction = 0;\n\t\thw->phy.ms_type = e1000_ms_hw_default;\n\t}\n\n\t/*\n\t * Start from a known state, this is important in reading the nvm\n\t * and mac from that.\n\t */\n\te1000_reset_hw(hw);\n\n\t/* Make sure we have a good EEPROM before we read from it */\n\tif (e1000_validate_nvm_checksum(hw) < 0) {\n\t\t/*\n\t\t * Some PCI-E parts fail the first check due to\n\t\t * the link being in sleep state, call it again,\n\t\t * if it fails a second time its a real issue.\n\t\t */\n\t\tdiag = e1000_validate_nvm_checksum(hw);\n\t\tif (diag < 0) {\n\t\t\tPMD_INIT_LOG(ERR, \"EEPROM checksum invalid\");\n\t\t\tgoto error;\n\t\t}\n\t}\n\n\t/* Read the permanent MAC address out of the EEPROM */\n\tdiag = e1000_read_mac_addr(hw);\n\tif (diag != 0) {\n\t\tPMD_INIT_LOG(ERR, \"EEPROM error while reading MAC address\");\n\t\tgoto error;\n\t}\n\n\t/* Now initialize the hardware */\n\tdiag = em_hardware_init(hw);\n\tif (diag != 0) {\n\t\tPMD_INIT_LOG(ERR, \"Hardware initialization failed\");\n\t\tgoto error;\n\t}\n\n\thw->mac.get_link_status = 1;\n\n\t/* Indicate SOL/IDER usage */\n\tdiag = e1000_check_reset_block(hw);\n\tif (diag < 0) {\n\t\tPMD_INIT_LOG(ERR, \"PHY reset is blocked due to \"\n\t\t\t\"SOL/IDER session\");\n\t}\n\treturn (0);\n\nerror:\n\tem_hw_control_release(hw);\n\treturn (diag);\n}\n\nstatic int\neth_em_configure(struct rte_eth_dev *dev)\n{\n\tstruct e1000_interrupt *intr =\n\t\tE1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\tintr->flags |= E1000_FLAG_NEED_LINK_UPDATE;\n\tPMD_INIT_FUNC_TRACE();\n\n\treturn (0);\n}\n\nstatic void\nem_set_pba(struct e1000_hw *hw)\n{\n\tuint32_t pba;\n\n\t/*\n\t * Packet Buffer Allocation (PBA)\n\t * Writing PBA sets the receive portion of the buffer\n\t * the remainder is used for the transmit buffer.\n\t * Devices before the 82547 had a Packet Buffer of 64K.\n\t * After the 82547 the buffer was reduced to 40K.\n\t */\n\tswitch (hw->mac.type) {\n\t\tcase e1000_82547:\n\t\tcase e1000_82547_rev_2:\n\t\t/* 82547: Total Packet Buffer is 40K */\n\t\t\tpba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */\n\t\t\tbreak;\n\t\tcase e1000_82571:\n\t\tcase e1000_82572:\n\t\tcase e1000_80003es2lan:\n\t\t\tpba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */\n\t\t\tbreak;\n\t\tcase e1000_82573: /* 82573: Total Packet Buffer is 32K */\n\t\t\tpba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */\n\t\t\tbreak;\n\t\tcase e1000_82574:\n\t\tcase e1000_82583:\n\t\t\tpba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */\n\t\t\tbreak;\n\t\tcase e1000_ich8lan:\n\t\t\tpba = E1000_PBA_8K;\n\t\t\tbreak;\n\t\tcase e1000_ich9lan:\n\t\tcase e1000_ich10lan:\n\t\t\tpba = E1000_PBA_10K;\n\t\t\tbreak;\n\t\tcase e1000_pchlan:\n\t\tcase e1000_pch2lan:\n\t\t\tpba = E1000_PBA_26K;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tpba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_PBA, pba);\n}\n\nstatic int\neth_em_start(struct rte_eth_dev *dev)\n{\n\tstruct e1000_adapter *adapter =\n\t\tE1000_DEV_PRIVATE(dev->data->dev_private);\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint ret, mask;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\teth_em_stop(dev);\n\n\te1000_power_up_phy(hw);\n\n\t/* Set default PBA value */\n\tem_set_pba(hw);\n\n\t/* Put the address into the Receive Address Array */\n\te1000_rar_set(hw, hw->mac.addr, 0);\n\n\t/*\n\t * With the 82571 adapter, RAR[0] may be overwritten\n\t * when the other port is reset, we make a duplicate\n\t * in RAR[14] for that eventuality, this assures\n\t * the interface continues to function.\n\t */\n\tif (hw->mac.type == e1000_82571) {\n\t\te1000_set_laa_state_82571(hw, TRUE);\n\t\te1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);\n\t}\n\n\t/* Initialize the hardware */\n\tif (em_hardware_init(hw)) {\n\t\tPMD_INIT_LOG(ERR, \"Unable to initialize the hardware\");\n\t\treturn (-EIO);\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);\n\n\t/* Configure for OS presence */\n\tem_init_manageability(hw);\n\n\teth_em_tx_init(dev);\n\n\tret = eth_em_rx_init(dev);\n\tif (ret) {\n\t\tPMD_INIT_LOG(ERR, \"Unable to initialize RX hardware\");\n\t\tem_dev_clear_queues(dev);\n\t\treturn ret;\n\t}\n\n\te1000_clear_hw_cntrs_base_generic(hw);\n\n\tmask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \\\n\t\t\tETH_VLAN_EXTEND_MASK;\n\teth_em_vlan_offload_set(dev, mask);\n\n\t/* Set Interrupt Throttling Rate to maximum allowed value. */\n\tE1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);\n\n\t/* Setup link speed and duplex */\n\tswitch (dev->data->dev_conf.link_speed) {\n\tcase ETH_LINK_SPEED_AUTONEG:\n\t\tif (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;\n\t\telse if (dev->data->dev_conf.link_duplex ==\n\t\t\t\t\tETH_LINK_HALF_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;\n\t\telse if (dev->data->dev_conf.link_duplex ==\n\t\t\t\t\tETH_LINK_FULL_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;\n\t\telse\n\t\t\tgoto error_invalid_config;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_10:\n\t\tif (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = E1000_ALL_10_SPEED;\n\t\telse if (dev->data->dev_conf.link_duplex ==\n\t\t\t\t\tETH_LINK_HALF_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = ADVERTISE_10_HALF;\n\t\telse if (dev->data->dev_conf.link_duplex ==\n\t\t\t\t\tETH_LINK_FULL_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = ADVERTISE_10_FULL;\n\t\telse\n\t\t\tgoto error_invalid_config;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_100:\n\t\tif (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = E1000_ALL_100_SPEED;\n\t\telse if (dev->data->dev_conf.link_duplex ==\n\t\t\t\t\tETH_LINK_HALF_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = ADVERTISE_100_HALF;\n\t\telse if (dev->data->dev_conf.link_duplex ==\n\t\t\t\t\tETH_LINK_FULL_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = ADVERTISE_100_FULL;\n\t\telse\n\t\t\tgoto error_invalid_config;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_1000:\n\t\tif ((dev->data->dev_conf.link_duplex ==\n\t\t\t\tETH_LINK_AUTONEG_DUPLEX) ||\n\t\t\t(dev->data->dev_conf.link_duplex ==\n\t\t\t\t\tETH_LINK_FULL_DUPLEX))\n\t\t\thw->phy.autoneg_advertised = ADVERTISE_1000_FULL;\n\t\telse\n\t\t\tgoto error_invalid_config;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_10000:\n\tdefault:\n\t\tgoto error_invalid_config;\n\t}\n\te1000_setup_link(hw);\n\n\t/* check if lsc interrupt feature is enabled */\n\tif (dev->data->dev_conf.intr_conf.lsc != 0) {\n\t\tret = eth_em_interrupt_setup(dev);\n\t\tif (ret) {\n\t\t\tPMD_INIT_LOG(ERR, \"Unable to setup interrupts\");\n\t\t\tem_dev_clear_queues(dev);\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\tadapter->stopped = 0;\n\n\tPMD_INIT_LOG(DEBUG, \"<<\");\n\n\treturn (0);\n\nerror_invalid_config:\n\tPMD_INIT_LOG(ERR, \"Invalid link_speed/link_duplex (%u/%u) for port %u\",\n\t\t dev->data->dev_conf.link_speed,\n\t\t dev->data->dev_conf.link_duplex, dev->data->port_id);\n\tem_dev_clear_queues(dev);\n\treturn (-EINVAL);\n}\n\n/*********************************************************************\n *\n * This routine disables all traffic on the adapter by issuing a\n * global reset on the MAC.\n *\n **********************************************************************/\nstatic void\neth_em_stop(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_link link;\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tem_intr_disable(hw);\n\te1000_reset_hw(hw);\n\tif (hw->mac.type >= e1000_82544)\n\t\tE1000_WRITE_REG(hw, E1000_WUC, 0);\n\n\t/* Power down the phy. Needed to make the link go down */\n\te1000_power_down_phy(hw);\n\n\tem_dev_clear_queues(dev);\n\n\t/* clear the recorded link status */\n\tmemset(&link, 0, sizeof(link));\n\trte_em_dev_atomic_write_link_status(dev, &link);\n}\n\nstatic void\neth_em_close(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_adapter *adapter =\n\t\tE1000_DEV_PRIVATE(dev->data->dev_private);\n\n\teth_em_stop(dev);\n\tadapter->stopped = 1;\n\tem_dev_free_queues(dev);\n\te1000_phy_hw_reset(hw);\n\tem_release_manageability(hw);\n\tem_hw_control_release(hw);\n}\n\nstatic int\nem_get_rx_buffer_size(struct e1000_hw *hw)\n{\n\tuint32_t rx_buf_size;\n\n\trx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);\n\treturn rx_buf_size;\n}\n\n/*********************************************************************\n *\n * Initialize the hardware\n *\n **********************************************************************/\nstatic int\nem_hardware_init(struct e1000_hw *hw)\n{\n\tuint32_t rx_buf_size;\n\tint diag;\n\n\t/* Issue a global reset */\n\te1000_reset_hw(hw);\n\n\t/* Let the firmware know the OS is in control */\n\tem_hw_control_acquire(hw);\n\n\t/*\n\t * These parameters control the automatic generation (Tx) and\n\t * response (Rx) to Ethernet PAUSE frames.\n\t * - High water mark should allow for at least two standard size (1518)\n\t * frames to be received after sending an XOFF.\n\t * - Low water mark works best when it is very near the high water mark.\n\t * This allows the receiver to restart by sending XON when it has\n\t * drained a bit. Here we use an arbitrary value of 1500 which will\n\t * restart after one full frame is pulled from the buffer. There\n\t * could be several smaller frames in the buffer and if so they will\n\t * not trigger the XON until their total number reduces the buffer\n\t * by 1500.\n\t * - The pause time is fairly large at 1000 x 512ns = 512 usec.\n\t */\n\trx_buf_size = em_get_rx_buffer_size(hw);\n\n\thw->fc.high_water = rx_buf_size - PMD_ROUNDUP(ETHER_MAX_LEN * 2, 1024);\n\thw->fc.low_water = hw->fc.high_water - 1500;\n\n\tif (hw->mac.type == e1000_80003es2lan)\n\t\thw->fc.pause_time = UINT16_MAX;\n\telse\n\t\thw->fc.pause_time = EM_FC_PAUSE_TIME;\n\n\thw->fc.send_xon = 1;\n\n\t/* Set Flow control, use the tunable location if sane */\n\tif (em_fc_setting <= e1000_fc_full)\n\t\thw->fc.requested_mode = em_fc_setting;\n\telse\n\t\thw->fc.requested_mode = e1000_fc_none;\n\n\t/* Workaround: no TX flow ctrl for PCH */\n\tif (hw->mac.type == e1000_pchlan)\n\t\thw->fc.requested_mode = e1000_fc_rx_pause;\n\n\t/* Override - settings for PCH2LAN, ya its magic :) */\n\tif (hw->mac.type == e1000_pch2lan) {\n\t\thw->fc.high_water = 0x5C20;\n\t\thw->fc.low_water = 0x5048;\n\t\thw->fc.pause_time = 0x0650;\n\t\thw->fc.refresh_time = 0x0400;\n\t}\n\n\tdiag = e1000_init_hw(hw);\n\tif (diag < 0)\n\t\treturn (diag);\n\te1000_check_for_link(hw);\n\treturn (0);\n}\n\n/* This function is based on em_update_stats_counters() in e1000/if_em.c */\nstatic void\neth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_hw_stats *stats =\n\t\t\tE1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\tint pause_frames;\n\n\tif(hw->phy.media_type == e1000_media_type_copper ||\n\t\t\t(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {\n\t\tstats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);\n\t\tstats->sec += E1000_READ_REG(hw, E1000_SEC);\n\t}\n\n\tstats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);\n\tstats->mpc += E1000_READ_REG(hw, E1000_MPC);\n\tstats->scc += E1000_READ_REG(hw, E1000_SCC);\n\tstats->ecol += E1000_READ_REG(hw, E1000_ECOL);\n\n\tstats->mcc += E1000_READ_REG(hw, E1000_MCC);\n\tstats->latecol += E1000_READ_REG(hw, E1000_LATECOL);\n\tstats->colc += E1000_READ_REG(hw, E1000_COLC);\n\tstats->dc += E1000_READ_REG(hw, E1000_DC);\n\tstats->rlec += E1000_READ_REG(hw, E1000_RLEC);\n\tstats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);\n\tstats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);\n\n\t/*\n\t * For watchdog management we need to know if we have been\n\t * paused during the last interval, so capture that here.\n\t */\n\tpause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);\n\tstats->xoffrxc += pause_frames;\n\tstats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);\n\tstats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);\n\tstats->prc64 += E1000_READ_REG(hw, E1000_PRC64);\n\tstats->prc127 += E1000_READ_REG(hw, E1000_PRC127);\n\tstats->prc255 += E1000_READ_REG(hw, E1000_PRC255);\n\tstats->prc511 += E1000_READ_REG(hw, E1000_PRC511);\n\tstats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);\n\tstats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);\n\tstats->gprc += E1000_READ_REG(hw, E1000_GPRC);\n\tstats->bprc += E1000_READ_REG(hw, E1000_BPRC);\n\tstats->mprc += E1000_READ_REG(hw, E1000_MPRC);\n\tstats->gptc += E1000_READ_REG(hw, E1000_GPTC);\n\n\t/*\n\t * For the 64-bit byte counters the low dword must be read first.\n\t * Both registers clear on the read of the high dword.\n\t */\n\n\tstats->gorc += E1000_READ_REG(hw, E1000_GORCL);\n\tstats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);\n\tstats->gotc += E1000_READ_REG(hw, E1000_GOTCL);\n\tstats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);\n\n\tstats->rnbc += E1000_READ_REG(hw, E1000_RNBC);\n\tstats->ruc += E1000_READ_REG(hw, E1000_RUC);\n\tstats->rfc += E1000_READ_REG(hw, E1000_RFC);\n\tstats->roc += E1000_READ_REG(hw, E1000_ROC);\n\tstats->rjc += E1000_READ_REG(hw, E1000_RJC);\n\n\tstats->tor += E1000_READ_REG(hw, E1000_TORH);\n\tstats->tot += E1000_READ_REG(hw, E1000_TOTH);\n\n\tstats->tpr += E1000_READ_REG(hw, E1000_TPR);\n\tstats->tpt += E1000_READ_REG(hw, E1000_TPT);\n\tstats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);\n\tstats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);\n\tstats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);\n\tstats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);\n\tstats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);\n\tstats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);\n\tstats->mptc += E1000_READ_REG(hw, E1000_MPTC);\n\tstats->bptc += E1000_READ_REG(hw, E1000_BPTC);\n\n\t/* Interrupt Counts */\n\n\tif (hw->mac.type >= e1000_82571) {\n\t\tstats->iac += E1000_READ_REG(hw, E1000_IAC);\n\t\tstats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);\n\t\tstats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);\n\t\tstats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);\n\t\tstats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);\n\t\tstats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);\n\t\tstats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);\n\t\tstats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);\n\t\tstats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);\n\t}\n\n\tif (hw->mac.type >= e1000_82543) {\n\t\tstats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);\n\t\tstats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);\n\t\tstats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);\n\t\tstats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);\n\t\tstats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);\n\t\tstats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);\n\t}\n\n\tif (rte_stats == NULL)\n\t\treturn;\n\n\t/* Rx Errors */\n\trte_stats->ibadcrc = stats->crcerrs;\n\trte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;\n\trte_stats->imissed = stats->mpc;\n\trte_stats->ierrors = rte_stats->ibadcrc +\n\t rte_stats->ibadlen +\n\t rte_stats->imissed +\n\t stats->rxerrc + stats->algnerrc + stats->cexterr;\n\n\t/* Tx Errors */\n\trte_stats->oerrors = stats->ecol + stats->latecol;\n\n\trte_stats->ipackets = stats->gprc;\n\trte_stats->opackets = stats->gptc;\n\trte_stats->ibytes = stats->gorc;\n\trte_stats->obytes = stats->gotc;\n\n\t/* XON/XOFF pause frames stats registers */\n\trte_stats->tx_pause_xon = stats->xontxc;\n\trte_stats->rx_pause_xon = stats->xonrxc;\n\trte_stats->tx_pause_xoff = stats->xofftxc;\n\trte_stats->rx_pause_xoff = stats->xoffrxc;\n}\n\nstatic void\neth_em_stats_reset(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw_stats *hw_stats =\n\t\t\tE1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\n\t/* HW registers are cleared on read */\n\teth_em_stats_get(dev, NULL);\n\n\t/* Reset software totals */\n\tmemset(hw_stats, 0, sizeof(*hw_stats));\n}\n\nstatic uint32_t\nem_get_max_pktlen(const struct e1000_hw *hw)\n{\n\tswitch (hw->mac.type) {\n\tcase e1000_82571:\n\tcase e1000_82572:\n\tcase e1000_ich9lan:\n\tcase e1000_ich10lan:\n\tcase e1000_pch2lan:\n\tcase e1000_82574:\n\tcase e1000_80003es2lan: /* 9K Jumbo Frame size */\n\tcase e1000_82583:\n\t\treturn (0x2412);\n\tcase e1000_pchlan:\n\t\treturn (0x1000);\n\t/* Adapters that do not support jumbo frames */\n\tcase e1000_ich8lan:\n\t\treturn (ETHER_MAX_LEN);\n\tdefault:\n\t\treturn (MAX_JUMBO_FRAME_SIZE);\n\t}\n}\n\nstatic void\neth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tdev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */\n\tdev_info->max_rx_pktlen = em_get_max_pktlen(hw);\n\tdev_info->max_mac_addrs = hw->mac.rar_entry_count;\n\n\t/*\n\t * Starting with 631xESB hw supports 2 TX/RX queues per port.\n\t * Unfortunatelly, all these nics have just one TX context.\n\t * So we have few choises for TX:\n\t * - Use just one TX queue.\n\t * - Allow cksum offload only for one TX queue.\n\t * - Don't allow TX cksum offload at all.\n\t * For now, option #1 was chosen.\n\t * To use second RX queue we have to use extended RX descriptor\n\t * (Multiple Receive Queues are mutually exclusive with UDP\n\t * fragmentation and are not supported when a legacy receive\n\t * descriptor format is used).\n\t * Which means separate RX routinies - as legacy nics (82540, 82545)\n\t * don't support extended RXD.\n\t * To avoid it we support just one RX queue for now (no RSS).\n\t */\n\n\tdev_info->max_rx_queues = 1;\n\tdev_info->max_tx_queues = 1;\n}\n\n/* return 0 means link status changed, -1 means not changed */\nstatic int\neth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct rte_eth_link link, old;\n\tint link_check, count;\n\n\tlink_check = 0;\n\thw->mac.get_link_status = 1;\n\n\t/* possible wait-to-complete in up to 9 seconds */\n\tfor (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {\n\t\t/* Read the real link status */\n\t\tswitch (hw->phy.media_type) {\n\t\tcase e1000_media_type_copper:\n\t\t\t/* Do the work to read phy */\n\t\t\te1000_check_for_link(hw);\n\t\t\tlink_check = !hw->mac.get_link_status;\n\t\t\tbreak;\n\n\t\tcase e1000_media_type_fiber:\n\t\t\te1000_check_for_link(hw);\n\t\t\tlink_check = (E1000_READ_REG(hw, E1000_STATUS) &\n\t\t\t\t\tE1000_STATUS_LU);\n\t\t\tbreak;\n\n\t\tcase e1000_media_type_internal_serdes:\n\t\t\te1000_check_for_link(hw);\n\t\t\tlink_check = hw->mac.serdes_has_link;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\tif (link_check || wait_to_complete == 0)\n\t\t\tbreak;\n\t\trte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);\n\t}\n\tmemset(&link, 0, sizeof(link));\n\trte_em_dev_atomic_read_link_status(dev, &link);\n\told = link;\n\n\t/* Now we check if a transition has happened */\n\tif (link_check && (link.link_status == 0)) {\n\t\thw->mac.ops.get_link_up_info(hw, &link.link_speed,\n\t\t\t&link.link_duplex);\n\t\tlink.link_status = 1;\n\t} else if (!link_check && (link.link_status == 1)) {\n\t\tlink.link_speed = 0;\n\t\tlink.link_duplex = 0;\n\t\tlink.link_status = 0;\n\t}\n\trte_em_dev_atomic_write_link_status(dev, &link);\n\n\t/* not changed */\n\tif (old.link_status == link.link_status)\n\t\treturn -1;\n\n\t/* changed */\n\treturn 0;\n}\n\n/*\n * em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.\n * For ASF and Pass Through versions of f/w this means\n * that the driver is loaded. For AMT version type f/w\n * this means that the network i/f is open.\n */\nstatic void\nem_hw_control_acquire(struct e1000_hw *hw)\n{\n\tuint32_t ctrl_ext, swsm;\n\n\t/* Let firmware know the driver has taken over */\n\tif (hw->mac.type == e1000_82573) {\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tE1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);\n\n\t} else {\n\t\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT,\n\t\t\tctrl_ext | E1000_CTRL_EXT_DRV_LOAD);\n\t}\n}\n\n/*\n * em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.\n * For ASF and Pass Through versions of f/w this means that the\n * driver is no longer loaded. For AMT versions of the\n * f/w this means that the network i/f is closed.\n */\nstatic void\nem_hw_control_release(struct e1000_hw *hw)\n{\n\tuint32_t ctrl_ext, swsm;\n\n\t/* Let firmware taken over control of h/w */\n\tif (hw->mac.type == e1000_82573) {\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tE1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);\n\t} else {\n\t\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT,\n\t\t\tctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);\n\t}\n}\n\n/*\n * Bit of a misnomer, what this really means is\n * to enable OS management of the system... aka\n * to disable special hardware management features.\n */\nstatic void\nem_init_manageability(struct e1000_hw *hw)\n{\n\tif (e1000_enable_mng_pass_thru(hw)) {\n\t\tuint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);\n\t\tuint32_t manc = E1000_READ_REG(hw, E1000_MANC);\n\n\t\t/* disable hardware interception of ARP */\n\t\tmanc &= ~(E1000_MANC_ARP_EN);\n\n\t\t/* enable receiving management packets to the host */\n\t\tmanc |= E1000_MANC_EN_MNG2HOST;\n\t\tmanc2h |= 1 << 5; /* Mng Port 623 */\n\t\tmanc2h |= 1 << 6; /* Mng Port 664 */\n\t\tE1000_WRITE_REG(hw, E1000_MANC2H, manc2h);\n\t\tE1000_WRITE_REG(hw, E1000_MANC, manc);\n\t}\n}\n\n/*\n * Give control back to hardware management\n * controller if there is one.\n */\nstatic void\nem_release_manageability(struct e1000_hw *hw)\n{\n\tuint32_t manc;\n\n\tif (e1000_enable_mng_pass_thru(hw)) {\n\t\tmanc = E1000_READ_REG(hw, E1000_MANC);\n\n\t\t/* re-enable hardware interception of ARP */\n\t\tmanc |= E1000_MANC_ARP_EN;\n\t\tmanc &= ~E1000_MANC_EN_MNG2HOST;\n\n\t\tE1000_WRITE_REG(hw, E1000_MANC, manc);\n\t}\n}\n\nstatic void\neth_em_promiscuous_enable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t rctl;\n\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\trctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n}\n\nstatic void\neth_em_promiscuous_disable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t rctl;\n\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\trctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);\n\tif (dev->data->all_multicast == 1)\n\t\trctl |= E1000_RCTL_MPE;\n\telse\n\t\trctl &= (~E1000_RCTL_MPE);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n}\n\nstatic void\neth_em_allmulticast_enable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t rctl;\n\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\trctl |= E1000_RCTL_MPE;\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n}\n\nstatic void\neth_em_allmulticast_disable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t rctl;\n\n\tif (dev->data->promiscuous == 1)\n\t\treturn; /* must remain in all_multicast mode */\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\trctl &= (~E1000_RCTL_MPE);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n}\n\nstatic int\neth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_vfta * shadow_vfta =\n\t\tE1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);\n\tuint32_t vfta;\n\tuint32_t vid_idx;\n\tuint32_t vid_bit;\n\n\tvid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &\n\t\t\t E1000_VFTA_ENTRY_MASK);\n\tvid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));\n\tvfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);\n\tif (on)\n\t\tvfta |= vid_bit;\n\telse\n\t\tvfta &= ~vid_bit;\n\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);\n\n\t/* update local VFTA copy */\n\tshadow_vfta->vfta[vid_idx] = vfta;\n\n\treturn 0;\n}\n\nstatic void\nem_vlan_hw_filter_disable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t reg;\n\n\t/* Filter Table Disable */\n\treg = E1000_READ_REG(hw, E1000_RCTL);\n\treg &= ~E1000_RCTL_CFIEN;\n\treg &= ~E1000_RCTL_VFE;\n\tE1000_WRITE_REG(hw, E1000_RCTL, reg);\n}\n\nstatic void\nem_vlan_hw_filter_enable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_vfta * shadow_vfta =\n\t\tE1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);\n\tuint32_t reg;\n\tint i;\n\n\t/* Filter Table Enable, CFI not used for packet acceptance */\n\treg = E1000_READ_REG(hw, E1000_RCTL);\n\treg &= ~E1000_RCTL_CFIEN;\n\treg |= E1000_RCTL_VFE;\n\tE1000_WRITE_REG(hw, E1000_RCTL, reg);\n\n\t/* restore vfta from local copy */\n\tfor (i = 0; i < IGB_VFTA_SIZE; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);\n}\n\nstatic void\nem_vlan_hw_strip_disable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t reg;\n\n\t/* VLAN Mode Disable */\n\treg = E1000_READ_REG(hw, E1000_CTRL);\n\treg &= ~E1000_CTRL_VME;\n\tE1000_WRITE_REG(hw, E1000_CTRL, reg);\n\n}\n\nstatic void\nem_vlan_hw_strip_enable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t reg;\n\n\t/* VLAN Mode Enable */\n\treg = E1000_READ_REG(hw, E1000_CTRL);\n\treg |= E1000_CTRL_VME;\n\tE1000_WRITE_REG(hw, E1000_CTRL, reg);\n}\n\nstatic void\neth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)\n{\n\tif(mask & ETH_VLAN_STRIP_MASK){\n\t\tif (dev->data->dev_conf.rxmode.hw_vlan_strip)\n\t\t\tem_vlan_hw_strip_enable(dev);\n\t\telse\n\t\t\tem_vlan_hw_strip_disable(dev);\n\t}\n\n\tif(mask & ETH_VLAN_FILTER_MASK){\n\t\tif (dev->data->dev_conf.rxmode.hw_vlan_filter)\n\t\t\tem_vlan_hw_filter_enable(dev);\n\t\telse\n\t\t\tem_vlan_hw_filter_disable(dev);\n\t}\n}\n\nstatic void\nem_intr_disable(struct e1000_hw *hw)\n{\n\tE1000_WRITE_REG(hw, E1000_IMC, ~0);\n}\n\n/**\n * It enables the interrupt mask and then enable the interrupt.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\neth_em_interrupt_setup(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tE1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);\n\trte_intr_enable(&(dev->pci_dev->intr_handle));\n\treturn (0);\n}\n\n/*\n * It reads ICR and gets interrupt causes, check it and set a bit flag\n * to update link status.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\neth_em_interrupt_get_status(struct rte_eth_dev *dev)\n{\n\tuint32_t icr;\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_interrupt *intr =\n\t\tE1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\t/* read-on-clear nic registers here */\n\ticr = E1000_READ_REG(hw, E1000_ICR);\n\tif (icr & E1000_ICR_LSC) {\n\t\tintr->flags |= E1000_FLAG_NEED_LINK_UPDATE;\n\t}\n\n\treturn 0;\n}\n\n/*\n * It executes link_update after knowing an interrupt is prsent.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\neth_em_interrupt_action(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_interrupt *intr =\n\t\tE1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\tuint32_t tctl, rctl;\n\tstruct rte_eth_link link;\n\tint ret;\n\n\tif (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))\n\t\treturn -1;\n\n\tintr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;\n\trte_intr_enable(&(dev->pci_dev->intr_handle));\n\n\t/* set get_link_status to check register later */\n\thw->mac.get_link_status = 1;\n\tret = eth_em_link_update(dev, 0);\n\n\t/* check if link has changed */\n\tif (ret < 0)\n\t\treturn 0;\n\n\tmemset(&link, 0, sizeof(link));\n\trte_em_dev_atomic_read_link_status(dev, &link);\n\tif (link.link_status) {\n\t\tPMD_INIT_LOG(INFO, \" Port %d: Link Up - speed %u Mbps - %s\",\n\t\t\t dev->data->port_id, (unsigned)link.link_speed,\n\t\t\t link.link_duplex == ETH_LINK_FULL_DUPLEX ?\n\t\t\t \"full-duplex\" : \"half-duplex\");\n\t} else {\n\t\tPMD_INIT_LOG(INFO, \" Port %d: Link Down\", dev->data->port_id);\n\t}\n\tPMD_INIT_LOG(DEBUG, \"PCI Address: %04d:%02d:%02d:%d\",\n\t\t dev->pci_dev->addr.domain, dev->pci_dev->addr.bus,\n\t\t dev->pci_dev->addr.devid, dev->pci_dev->addr.function);\n\n\ttctl = E1000_READ_REG(hw, E1000_TCTL);\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\tif (link.link_status) {\n\t\t/* enable Tx/Rx */\n\t\ttctl |= E1000_TCTL_EN;\n\t\trctl |= E1000_RCTL_EN;\n\t} else {\n\t\t/* disable Tx/Rx */\n\t\ttctl &= ~E1000_TCTL_EN;\n\t\trctl &= ~E1000_RCTL_EN;\n\t}\n\tE1000_WRITE_REG(hw, E1000_TCTL, tctl);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\tE1000_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\n/**\n * Interrupt handler which shall be registered at first.\n *\n * @param handle\n * Pointer to interrupt handle.\n * @param param\n * The address of parameter (struct rte_eth_dev *) regsitered before.\n *\n * @return\n * void\n */\nstatic void\neth_em_interrupt_handler(__rte_unused struct rte_intr_handle *handle,\n\t\t\t\t\t\t\tvoid *param)\n{\n\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n\n\teth_em_interrupt_get_status(dev);\n\teth_em_interrupt_action(dev);\n\t_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);\n}\n\nstatic int\neth_em_led_on(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\treturn (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);\n}\n\nstatic int\neth_em_led_off(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\treturn (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);\n}\n\nstatic int\neth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n{\n\tstruct e1000_hw *hw;\n\tuint32_t ctrl;\n\tint tx_pause;\n\tint rx_pause;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tfc_conf->pause_time = hw->fc.pause_time;\n\tfc_conf->high_water = hw->fc.high_water;\n\tfc_conf->low_water = hw->fc.low_water;\n\tfc_conf->send_xon = hw->fc.send_xon;\n\tfc_conf->autoneg = hw->mac.autoneg;\n\n\t/*\n\t * Return rx_pause and tx_pause status according to actual setting of\n\t * the TFCE and RFCE bits in the CTRL register.\n\t */\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tif (ctrl & E1000_CTRL_TFCE)\n\t\ttx_pause = 1;\n\telse\n\t\ttx_pause = 0;\n\n\tif (ctrl & E1000_CTRL_RFCE)\n\t\trx_pause = 1;\n\telse\n\t\trx_pause = 0;\n\n\tif (rx_pause && tx_pause)\n\t\tfc_conf->mode = RTE_FC_FULL;\n\telse if (rx_pause)\n\t\tfc_conf->mode = RTE_FC_RX_PAUSE;\n\telse if (tx_pause)\n\t\tfc_conf->mode = RTE_FC_TX_PAUSE;\n\telse\n\t\tfc_conf->mode = RTE_FC_NONE;\n\n\treturn 0;\n}\n\nstatic int\neth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n{\n\tstruct e1000_hw *hw;\n\tint err;\n\tenum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {\n\t\te1000_fc_none,\n\t\te1000_fc_rx_pause,\n\t\te1000_fc_tx_pause,\n\t\te1000_fc_full\n\t};\n\tuint32_t rx_buf_size;\n\tuint32_t max_high_water;\n\tuint32_t rctl;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tif (fc_conf->autoneg != hw->mac.autoneg)\n\t\treturn -ENOTSUP;\n\trx_buf_size = em_get_rx_buffer_size(hw);\n\tPMD_INIT_LOG(DEBUG, \"Rx packet buffer size = 0x%x\", rx_buf_size);\n\n\t/* At least reserve one Ethernet frame for watermark */\n\tmax_high_water = rx_buf_size - ETHER_MAX_LEN;\n\tif ((fc_conf->high_water > max_high_water) ||\n\t (fc_conf->high_water < fc_conf->low_water)) {\n\t\tPMD_INIT_LOG(ERR, \"e1000 incorrect high/low water value\");\n\t\tPMD_INIT_LOG(ERR, \"high water must <= 0x%x\", max_high_water);\n\t\treturn (-EINVAL);\n\t}\n\n\thw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];\n\thw->fc.pause_time = fc_conf->pause_time;\n\thw->fc.high_water = fc_conf->high_water;\n\thw->fc.low_water = fc_conf->low_water;\n\thw->fc.send_xon\t = fc_conf->send_xon;\n\n\terr = e1000_setup_link_generic(hw);\n\tif (err == E1000_SUCCESS) {\n\n\t\t/* check if we want to forward MAC frames - driver doesn't have native\n\t\t * capability to do that, so we'll write the registers ourselves */\n\n\t\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\n\t\t/* set or clear MFLCN.PMCF bit depending on configuration */\n\t\tif (fc_conf->mac_ctrl_frame_fwd != 0)\n\t\t\trctl |= E1000_RCTL_PMCF;\n\t\telse\n\t\t\trctl &= ~E1000_RCTL_PMCF;\n\n\t\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\t\tE1000_WRITE_FLUSH(hw);\n\n\t\treturn 0;\n\t}\n\n\tPMD_INIT_LOG(ERR, \"e1000_setup_link_generic = 0x%x\", err);\n\treturn (-EIO);\n}\n\nstatic void\neth_em_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,\n\t\tuint32_t index, __rte_unused uint32_t pool)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\te1000_rar_set(hw, mac_addr->addr_bytes, index);\n}\n\nstatic void\neth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)\n{\n\tuint8_t addr[ETHER_ADDR_LEN];\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tmemset(addr, 0, sizeof(addr));\n\n\te1000_rar_set(hw, addr, index);\n}\n\nstatic int\neth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)\n{\n\tstruct rte_eth_dev_info dev_info;\n\tstruct e1000_hw *hw;\n\tuint32_t frame_size;\n\tuint32_t rctl;\n\n\teth_em_infos_get(dev, &dev_info);\n\tframe_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE;\n\n\t/* check that mtu is within the allowed range */\n\tif ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))\n\t\treturn -EINVAL;\n\n\t/* refuse mtu that requires the support of scattered packets when this\n\t * feature has not been enabled before. */\n\tif (!dev->data->scattered_rx &&\n\t frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)\n\t\treturn -EINVAL;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\n\t/* switch to jumbo mode if needed */\n\tif (frame_size > ETHER_MAX_LEN) {\n\t\tdev->data->dev_conf.rxmode.jumbo_frame = 1;\n\t\trctl |= E1000_RCTL_LPE;\n\t} else {\n\t\tdev->data->dev_conf.rxmode.jumbo_frame = 0;\n\t\trctl &= ~E1000_RCTL_LPE;\n\t}\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\n\t/* update max frame size */\n\tdev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;\n\treturn 0;\n}\n\nstatic int\neth_em_set_mc_addr_list(struct rte_eth_dev *dev,\n\t\t\tstruct ether_addr *mc_addr_set,\n\t\t\tuint32_t nb_mc_addr)\n{\n\tstruct e1000_hw *hw;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\te1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);\n\treturn 0;\n}\n\nstruct rte_driver em_pmd_drv = {\n\t.type = PMD_PDEV,\n\t.init = rte_em_pmd_init,\n};\n\nPMD_REGISTER_DRIVER(em_pmd_drv);\n" }, { "path": "drivers/net/e1000/em_rxtx.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"e1000_logs.h\"\n#include \"base/e1000_api.h\"\n#include \"e1000_ethdev.h\"\n#include \"base/e1000_osdep.h\"\n\n#define\tE1000_TXD_VLAN_SHIFT\t16\n\n#define E1000_RXDCTL_GRAN\t0x01000000 /* RXDCTL Granularity */\n\nstatic inline struct rte_mbuf *\nrte_rxmbuf_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\n\tm = __rte_mbuf_raw_alloc(mp);\n\t__rte_mbuf_sanity_check_raw(m, 0);\n\treturn (m);\n}\n\n#define RTE_MBUF_DATA_DMA_ADDR(mb) \\\n\t(uint64_t) ((mb)->buf_physaddr + (mb)->data_off)\n\n#define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \\\n\t(uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)\n\n/**\n * Structure associated with each descriptor of the RX ring of a RX queue.\n */\nstruct em_rx_entry {\n\tstruct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */\n};\n\n/**\n * Structure associated with each descriptor of the TX ring of a TX queue.\n */\nstruct em_tx_entry {\n\tstruct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */\n\tuint16_t next_id; /**< Index of next descriptor in ring. */\n\tuint16_t last_id; /**< Index of last scattered descriptor. */\n};\n\n/**\n * Structure associated with each RX queue.\n */\nstruct em_rx_queue {\n\tstruct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */\n\tvolatile struct e1000_rx_desc *rx_ring; /**< RX ring virtual address. */\n\tuint64_t rx_ring_phys_addr; /**< RX ring DMA address. */\n\tvolatile uint32_t *rdt_reg_addr; /**< RDT register address. */\n\tvolatile uint32_t *rdh_reg_addr; /**< RDH register address. */\n\tstruct em_rx_entry *sw_ring; /**< address of RX software ring. */\n\tstruct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */\n\tstruct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */\n\tuint16_t nb_rx_desc; /**< number of RX descriptors. */\n\tuint16_t rx_tail; /**< current value of RDT register. */\n\tuint16_t nb_rx_hold; /**< number of held free RX desc. */\n\tuint16_t rx_free_thresh; /**< max free RX desc to hold. */\n\tuint16_t queue_id; /**< RX queue index. */\n\tuint8_t port_id; /**< Device port identifier. */\n\tuint8_t pthresh; /**< Prefetch threshold register. */\n\tuint8_t hthresh; /**< Host threshold register. */\n\tuint8_t wthresh; /**< Write-back threshold register. */\n\tuint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */\n};\n\n/**\n * Hardware context number\n */\nenum {\n\tEM_CTX_0 = 0, /**< CTX0 */\n\tEM_CTX_NUM = 1, /**< CTX NUM */\n};\n\n/** Offload features */\nunion em_vlan_macip {\n\tuint32_t data;\n\tstruct {\n\t\tuint16_t l3_len:9; /**< L3 (IP) Header Length. */\n\t\tuint16_t l2_len:7; /**< L2 (MAC) Header Length. */\n\t\tuint16_t vlan_tci;\n\t\t/**< VLAN Tag Control Identifier (CPU order). */\n\t} f;\n};\n\n/*\n * Compare mask for vlan_macip_len.data,\n * should be in sync with em_vlan_macip.f layout.\n * */\n#define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */\n#define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */\n#define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */\n/** MAC+IP length. */\n#define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)\n\n/**\n * Structure to check if new context need be built\n */\nstruct em_ctx_info {\n\tuint64_t flags; /**< ol_flags related to context build. */\n\tuint32_t cmp_mask; /**< compare mask */\n\tunion em_vlan_macip hdrlen; /**< L2 and L3 header lenghts */\n};\n\n/**\n * Structure associated with each TX queue.\n */\nstruct em_tx_queue {\n\tvolatile struct e1000_data_desc *tx_ring; /**< TX ring address */\n\tuint64_t tx_ring_phys_addr; /**< TX ring DMA address. */\n\tstruct em_tx_entry *sw_ring; /**< virtual address of SW ring. */\n\tvolatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */\n\tuint16_t nb_tx_desc; /**< number of TX descriptors. */\n\tuint16_t tx_tail; /**< Current value of TDT register. */\n\t/**< Start freeing TX buffers if there are less free descriptors than\n\t this value. */\n\tuint16_t tx_free_thresh;\n\t/**< Number of TX descriptors to use before RS bit is set. */\n\tuint16_t tx_rs_thresh;\n\t/** Number of TX descriptors used since RS bit was set. */\n\tuint16_t nb_tx_used;\n\t/** Index to last TX descriptor to have been cleaned. */\n\tuint16_t\t last_desc_cleaned;\n\t/** Total number of TX descriptors ready to be allocated. */\n\tuint16_t nb_tx_free;\n\tuint16_t queue_id; /**< TX queue index. */\n\tuint8_t port_id; /**< Device port identifier. */\n\tuint8_t pthresh; /**< Prefetch threshold register. */\n\tuint8_t hthresh; /**< Host threshold register. */\n\tuint8_t wthresh; /**< Write-back threshold register. */\n\tstruct em_ctx_info ctx_cache;\n\t/**< Hardware context history.*/\n};\n\n#if 1\n#define RTE_PMD_USE_PREFETCH\n#endif\n\n#ifdef RTE_PMD_USE_PREFETCH\n#define rte_em_prefetch(p)\trte_prefetch0(p)\n#else\n#define rte_em_prefetch(p)\tdo {} while(0)\n#endif\n\n#ifdef RTE_PMD_PACKET_PREFETCH\n#define rte_packet_prefetch(p) rte_prefetch1(p)\n#else\n#define rte_packet_prefetch(p)\tdo {} while(0)\n#endif\n\n#ifndef DEFAULT_TX_FREE_THRESH\n#define DEFAULT_TX_FREE_THRESH 32\n#endif /* DEFAULT_TX_FREE_THRESH */\n\n#ifndef DEFAULT_TX_RS_THRESH\n#define DEFAULT_TX_RS_THRESH 32\n#endif /* DEFAULT_TX_RS_THRESH */\n\n\n/*********************************************************************\n *\n * TX function\n *\n **********************************************************************/\n\n/*\n * Populates TX context descriptor.\n */\nstatic inline void\nem_set_xmit_ctx(struct em_tx_queue* txq,\n\t\tvolatile struct e1000_context_desc *ctx_txd,\n\t\tuint64_t flags,\n\t\tunion em_vlan_macip hdrlen)\n{\n\tuint32_t cmp_mask, cmd_len;\n\tuint16_t ipcse, l2len;\n\tstruct e1000_context_desc ctx;\n\n\tcmp_mask = 0;\n\tcmd_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C;\n\n\tl2len = hdrlen.f.l2_len;\n\tipcse = (uint16_t)(l2len + hdrlen.f.l3_len);\n\n\t/* setup IPCS* fields */\n\tctx.lower_setup.ip_fields.ipcss = (uint8_t)l2len;\n\tctx.lower_setup.ip_fields.ipcso = (uint8_t)(l2len +\n\t\t\toffsetof(struct ipv4_hdr, hdr_checksum));\n\n\t/*\n\t * When doing checksum or TCP segmentation with IPv6 headers,\n\t * IPCSE field should be set t0 0.\n\t */\n\tif (flags & PKT_TX_IP_CKSUM) {\n\t\tctx.lower_setup.ip_fields.ipcse =\n\t\t\t(uint16_t)rte_cpu_to_le_16(ipcse - 1);\n\t\tcmd_len |= E1000_TXD_CMD_IP;\n\t\tcmp_mask |= TX_MACIP_LEN_CMP_MASK;\n\t} else {\n\t\tctx.lower_setup.ip_fields.ipcse = 0;\n\t}\n\n\t/* setup TUCS* fields */\n\tctx.upper_setup.tcp_fields.tucss = (uint8_t)ipcse;\n\tctx.upper_setup.tcp_fields.tucse = 0;\n\n\tswitch (flags & PKT_TX_L4_MASK) {\n\tcase PKT_TX_UDP_CKSUM:\n\t\tctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +\n\t\t\t\toffsetof(struct udp_hdr, dgram_cksum));\n\t\tcmp_mask |= TX_MACIP_LEN_CMP_MASK;\n\t\tbreak;\n\tcase PKT_TX_TCP_CKSUM:\n\t\tctx.upper_setup.tcp_fields.tucso = (uint8_t)(ipcse +\n\t\t\t\toffsetof(struct tcp_hdr, cksum));\n\t\tcmd_len |= E1000_TXD_CMD_TCP;\n\t\tcmp_mask |= TX_MACIP_LEN_CMP_MASK;\n\t\tbreak;\n\tdefault:\n\t\tctx.upper_setup.tcp_fields.tucso = 0;\n\t}\n\n\tctx.cmd_and_length = rte_cpu_to_le_32(cmd_len);\n\tctx.tcp_seg_setup.data = 0;\n\n\t*ctx_txd = ctx;\n\n\ttxq->ctx_cache.flags = flags;\n\ttxq->ctx_cache.cmp_mask = cmp_mask;\n\ttxq->ctx_cache.hdrlen = hdrlen;\n}\n\n/*\n * Check which hardware context can be used. Use the existing match\n * or create a new context descriptor.\n */\nstatic inline uint32_t\nwhat_ctx_update(struct em_tx_queue *txq, uint64_t flags,\n\t\tunion em_vlan_macip hdrlen)\n{\n\t/* If match with the current context */\n\tif (likely (txq->ctx_cache.flags == flags &&\n\t\t\t((txq->ctx_cache.hdrlen.data ^ hdrlen.data) &\n\t\t\ttxq->ctx_cache.cmp_mask) == 0))\n\t\treturn (EM_CTX_0);\n\n\t/* Mismatch */\n\treturn (EM_CTX_NUM);\n}\n\n/* Reset transmit descriptors after they have been used */\nstatic inline int\nem_xmit_cleanup(struct em_tx_queue *txq)\n{\n\tstruct em_tx_entry *sw_ring = txq->sw_ring;\n\tvolatile struct e1000_data_desc *txr = txq->tx_ring;\n\tuint16_t last_desc_cleaned = txq->last_desc_cleaned;\n\tuint16_t nb_tx_desc = txq->nb_tx_desc;\n\tuint16_t desc_to_clean_to;\n\tuint16_t nb_tx_to_clean;\n\n\t/* Determine the last descriptor needing to be cleaned */\n\tdesc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);\n\tif (desc_to_clean_to >= nb_tx_desc)\n\t\tdesc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);\n\n\t/* Check to make sure the last descriptor to clean is done */\n\tdesc_to_clean_to = sw_ring[desc_to_clean_to].last_id;\n\tif (! (txr[desc_to_clean_to].upper.fields.status & E1000_TXD_STAT_DD))\n\t{\n\t\tPMD_TX_FREE_LOG(DEBUG,\n\t\t\t\t\"TX descriptor %4u is not done\"\n\t\t\t\t\"(port=%d queue=%d)\", desc_to_clean_to,\n\t\t\t\ttxq->port_id, txq->queue_id);\n\t\t/* Failed to clean any descriptors, better luck next time */\n\t\treturn -(1);\n\t}\n\n\t/* Figure out how many descriptors will be cleaned */\n\tif (last_desc_cleaned > desc_to_clean_to)\n\t\tnb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +\n\t\t\t\t\t\t\tdesc_to_clean_to);\n\telse\n\t\tnb_tx_to_clean = (uint16_t)(desc_to_clean_to -\n\t\t\t\t\t\tlast_desc_cleaned);\n\n\tPMD_TX_FREE_LOG(DEBUG,\n\t\t\t\"Cleaning %4u TX descriptors: %4u to %4u \"\n\t\t\t\"(port=%d queue=%d)\", nb_tx_to_clean,\n\t\t\tlast_desc_cleaned, desc_to_clean_to, txq->port_id,\n\t\t\ttxq->queue_id);\n\n\t/*\n\t * The last descriptor to clean is done, so that means all the\n\t * descriptors from the last descriptor that was cleaned\n\t * up to the last descriptor with the RS bit set\n\t * are done. Only reset the threshold descriptor.\n\t */\n\ttxr[desc_to_clean_to].upper.fields.status = 0;\n\n\t/* Update the txq to reflect the last descriptor that was cleaned */\n\ttxq->last_desc_cleaned = desc_to_clean_to;\n\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);\n\n\t/* No Error */\n\treturn (0);\n}\n\nstatic inline uint32_t\ntx_desc_cksum_flags_to_upper(uint64_t ol_flags)\n{\n\tstatic const uint32_t l4_olinfo[2] = {0, E1000_TXD_POPTS_TXSM << 8};\n\tstatic const uint32_t l3_olinfo[2] = {0, E1000_TXD_POPTS_IXSM << 8};\n\tuint32_t tmp;\n\n\ttmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];\n\ttmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];\n\treturn (tmp);\n}\n\nuint16_t\neth_em_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t\tuint16_t nb_pkts)\n{\n\tstruct em_tx_queue *txq;\n\tstruct em_tx_entry *sw_ring;\n\tstruct em_tx_entry *txe, *txn;\n\tvolatile struct e1000_data_desc *txr;\n\tvolatile struct e1000_data_desc *txd;\n\tstruct rte_mbuf *tx_pkt;\n\tstruct rte_mbuf *m_seg;\n\tuint64_t buf_dma_addr;\n\tuint32_t popts_spec;\n\tuint32_t cmd_type_len;\n\tuint16_t slen;\n\tuint64_t ol_flags;\n\tuint16_t tx_id;\n\tuint16_t tx_last;\n\tuint16_t nb_tx;\n\tuint16_t nb_used;\n\tuint64_t tx_ol_req;\n\tuint32_t ctx;\n\tuint32_t new_ctx;\n\tunion em_vlan_macip hdrlen;\n\n\ttxq = tx_queue;\n\tsw_ring = txq->sw_ring;\n\ttxr = txq->tx_ring;\n\ttx_id = txq->tx_tail;\n\ttxe = &sw_ring[tx_id];\n\n\t/* Determine if the descriptor ring needs to be cleaned. */\n\t if (txq->nb_tx_free < txq->tx_free_thresh)\n\t\tem_xmit_cleanup(txq);\n\n\t/* TX loop */\n\tfor (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {\n\t\tnew_ctx = 0;\n\t\ttx_pkt = *tx_pkts++;\n\n\t\tRTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);\n\n\t\t/*\n\t\t * Determine how many (if any) context descriptors\n\t\t * are needed for offload functionality.\n\t\t */\n\t\tol_flags = tx_pkt->ol_flags;\n\n\t\t/* If hardware offload required */\n\t\ttx_ol_req = (ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK));\n\t\tif (tx_ol_req) {\n\t\t\thdrlen.f.vlan_tci = tx_pkt->vlan_tci;\n\t\t\thdrlen.f.l2_len = tx_pkt->l2_len;\n\t\t\thdrlen.f.l3_len = tx_pkt->l3_len;\n\t\t\t/* If new context to be built or reuse the exist ctx. */\n\t\t\tctx = what_ctx_update(txq, tx_ol_req, hdrlen);\n\n\t\t\t/* Only allocate context descriptor if required*/\n\t\t\tnew_ctx = (ctx == EM_CTX_NUM);\n\t\t}\n\n\t\t/*\n\t\t * Keep track of how many descriptors are used this loop\n\t\t * This will always be the number of segments + the number of\n\t\t * Context descriptors required to transmit the packet\n\t\t */\n\t\tnb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);\n\n\t\t/*\n\t\t * The number of descriptors that must be allocated for a\n\t\t * packet is the number of segments of that packet, plus 1\n\t\t * Context Descriptor for the hardware offload, if any.\n\t\t * Determine the last TX descriptor to allocate in the TX ring\n\t\t * for the packet, starting from the current position (tx_id)\n\t\t * in the ring.\n\t\t */\n\t\ttx_last = (uint16_t) (tx_id + nb_used - 1);\n\n\t\t/* Circular ring */\n\t\tif (tx_last >= txq->nb_tx_desc)\n\t\t\ttx_last = (uint16_t) (tx_last - txq->nb_tx_desc);\n\n\t\tPMD_TX_LOG(DEBUG, \"port_id=%u queue_id=%u pktlen=%u\"\n\t\t\t \" tx_first=%u tx_last=%u\",\n\t\t\t (unsigned) txq->port_id,\n\t\t\t (unsigned) txq->queue_id,\n\t\t\t (unsigned) tx_pkt->pkt_len,\n\t\t\t (unsigned) tx_id,\n\t\t\t (unsigned) tx_last);\n\n\t\t/*\n\t\t * Make sure there are enough TX descriptors available to\n\t\t * transmit the entire packet.\n\t\t * nb_used better be less than or equal to txq->tx_rs_thresh\n\t\t */\n\t\twhile (unlikely (nb_used > txq->nb_tx_free)) {\n\t\t\tPMD_TX_FREE_LOG(DEBUG, \"Not enough free TX descriptors \"\n\t\t\t\t\t\"nb_used=%4u nb_free=%4u \"\n\t\t\t\t\t\"(port=%d queue=%d)\",\n\t\t\t\t\tnb_used, txq->nb_tx_free,\n\t\t\t\t\ttxq->port_id, txq->queue_id);\n\n\t\t\tif (em_xmit_cleanup(txq) != 0) {\n\t\t\t\t/* Could not clean any descriptors */\n\t\t\t\tif (nb_tx == 0)\n\t\t\t\t\treturn (0);\n\t\t\t\tgoto end_of_tx;\n\t\t\t}\n\t\t}\n\n\t\t/*\n\t\t * By now there are enough free TX descriptors to transmit\n\t\t * the packet.\n\t\t */\n\n\t\t/*\n\t\t * Set common flags of all TX Data Descriptors.\n\t\t *\n\t\t * The following bits must be set in all Data Descriptors:\n\t\t * - E1000_TXD_DTYP_DATA\n\t\t * - E1000_TXD_DTYP_DEXT\n\t\t *\n\t\t * The following bits must be set in the first Data Descriptor\n\t\t * and are ignored in the other ones:\n\t\t * - E1000_TXD_POPTS_IXSM\n\t\t * - E1000_TXD_POPTS_TXSM\n\t\t *\n\t\t * The following bits must be set in the last Data Descriptor\n\t\t * and are ignored in the other ones:\n\t\t * - E1000_TXD_CMD_VLE\n\t\t * - E1000_TXD_CMD_IFCS\n\t\t *\n\t\t * The following bits must only be set in the last Data\n\t\t * Descriptor:\n\t\t * - E1000_TXD_CMD_EOP\n\t\t *\n\t\t * The following bits can be set in any Data Descriptor, but\n\t\t * are only set in the last Data Descriptor:\n\t\t * - E1000_TXD_CMD_RS\n\t\t */\n\t\tcmd_type_len = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |\n\t\t\tE1000_TXD_CMD_IFCS;\n\t\tpopts_spec = 0;\n\n\t\t/* Set VLAN Tag offload fields. */\n\t\tif (ol_flags & PKT_TX_VLAN_PKT) {\n\t\t\tcmd_type_len |= E1000_TXD_CMD_VLE;\n\t\t\tpopts_spec = tx_pkt->vlan_tci << E1000_TXD_VLAN_SHIFT;\n\t\t}\n\n\t\tif (tx_ol_req) {\n\t\t\t/*\n\t\t\t * Setup the TX Context Descriptor if required\n\t\t\t */\n\t\t\tif (new_ctx) {\n\t\t\t\tvolatile struct e1000_context_desc *ctx_txd;\n\n\t\t\t\tctx_txd = (volatile struct e1000_context_desc *)\n\t\t\t\t\t&txr[tx_id];\n\n\t\t\t\ttxn = &sw_ring[txe->next_id];\n\t\t\t\tRTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);\n\n\t\t\t\tif (txe->mbuf != NULL) {\n\t\t\t\t\trte_pktmbuf_free_seg(txe->mbuf);\n\t\t\t\t\ttxe->mbuf = NULL;\n\t\t\t\t}\n\n\t\t\t\tem_set_xmit_ctx(txq, ctx_txd, tx_ol_req,\n\t\t\t\t\thdrlen);\n\n\t\t\t\ttxe->last_id = tx_last;\n\t\t\t\ttx_id = txe->next_id;\n\t\t\t\ttxe = txn;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Setup the TX Data Descriptor,\n\t\t\t * This path will go through\n\t\t\t * whatever new/reuse the context descriptor\n\t\t\t */\n\t\t\tpopts_spec |= tx_desc_cksum_flags_to_upper(ol_flags);\n\t\t}\n\n\t\tm_seg = tx_pkt;\n\t\tdo {\n\t\t\ttxd = &txr[tx_id];\n\t\t\ttxn = &sw_ring[txe->next_id];\n\n\t\t\tif (txe->mbuf != NULL)\n\t\t\t\trte_pktmbuf_free_seg(txe->mbuf);\n\t\t\ttxe->mbuf = m_seg;\n\n\t\t\t/*\n\t\t\t * Set up Transmit Data Descriptor.\n\t\t\t */\n\t\t\tslen = m_seg->data_len;\n\t\t\tbuf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);\n\n\t\t\ttxd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);\n\t\t\ttxd->lower.data = rte_cpu_to_le_32(cmd_type_len | slen);\n\t\t\ttxd->upper.data = rte_cpu_to_le_32(popts_spec);\n\n\t\t\ttxe->last_id = tx_last;\n\t\t\ttx_id = txe->next_id;\n\t\t\ttxe = txn;\n\t\t\tm_seg = m_seg->next;\n\t\t} while (m_seg != NULL);\n\n\t\t/*\n\t\t * The last packet data descriptor needs End Of Packet (EOP)\n\t\t */\n\t\tcmd_type_len |= E1000_TXD_CMD_EOP;\n\t\ttxq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);\n\t\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);\n\n\t\t/* Set RS bit only on threshold packets' last descriptor */\n\t\tif (txq->nb_tx_used >= txq->tx_rs_thresh) {\n\t\t\tPMD_TX_FREE_LOG(DEBUG,\n\t\t\t\t\t\"Setting RS bit on TXD id=%4u \"\n\t\t\t\t\t\"(port=%d queue=%d)\",\n\t\t\t\t\ttx_last, txq->port_id, txq->queue_id);\n\n\t\t\tcmd_type_len |= E1000_TXD_CMD_RS;\n\n\t\t\t/* Update txq RS bit counters */\n\t\t\ttxq->nb_tx_used = 0;\n\t\t}\n\t\ttxd->lower.data |= rte_cpu_to_le_32(cmd_type_len);\n\t}\nend_of_tx:\n\trte_wmb();\n\n\t/*\n\t * Set the Transmit Descriptor Tail (TDT)\n\t */\n\tPMD_TX_LOG(DEBUG, \"port_id=%u queue_id=%u tx_tail=%u nb_tx=%u\",\n\t\t(unsigned) txq->port_id, (unsigned) txq->queue_id,\n\t\t(unsigned) tx_id, (unsigned) nb_tx);\n\tE1000_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);\n\ttxq->tx_tail = tx_id;\n\n\treturn (nb_tx);\n}\n\n/*********************************************************************\n *\n * RX functions\n *\n **********************************************************************/\n\nstatic inline uint64_t\nrx_desc_status_to_pkt_flags(uint32_t rx_status)\n{\n\tuint64_t pkt_flags;\n\n\t/* Check if VLAN present */\n\tpkt_flags = ((rx_status & E1000_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0);\n\n\treturn pkt_flags;\n}\n\nstatic inline uint64_t\nrx_desc_error_to_pkt_flags(uint32_t rx_error)\n{\n\tuint64_t pkt_flags = 0;\n\n\tif (rx_error & E1000_RXD_ERR_IPE)\n\t\tpkt_flags |= PKT_RX_IP_CKSUM_BAD;\n\tif (rx_error & E1000_RXD_ERR_TCPE)\n\t\tpkt_flags |= PKT_RX_L4_CKSUM_BAD;\n\treturn (pkt_flags);\n}\n\nuint16_t\neth_em_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts)\n{\n\tvolatile struct e1000_rx_desc *rx_ring;\n\tvolatile struct e1000_rx_desc *rxdp;\n\tstruct em_rx_queue *rxq;\n\tstruct em_rx_entry *sw_ring;\n\tstruct em_rx_entry *rxe;\n\tstruct rte_mbuf *rxm;\n\tstruct rte_mbuf *nmb;\n\tstruct e1000_rx_desc rxd;\n\tuint64_t dma_addr;\n\tuint16_t pkt_len;\n\tuint16_t rx_id;\n\tuint16_t nb_rx;\n\tuint16_t nb_hold;\n\tuint8_t status;\n\n\trxq = rx_queue;\n\n\tnb_rx = 0;\n\tnb_hold = 0;\n\trx_id = rxq->rx_tail;\n\trx_ring = rxq->rx_ring;\n\tsw_ring = rxq->sw_ring;\n\twhile (nb_rx < nb_pkts) {\n\t\t/*\n\t\t * The order of operations here is important as the DD status\n\t\t * bit must not be read after any other descriptor fields.\n\t\t * rx_ring and rxdp are pointing to volatile data so the order\n\t\t * of accesses cannot be reordered by the compiler. If they were\n\t\t * not volatile, they could be reordered which could lead to\n\t\t * using invalid descriptor fields when read from rxd.\n\t\t */\n\t\trxdp = &rx_ring[rx_id];\n\t\tstatus = rxdp->status;\n\t\tif (! (status & E1000_RXD_STAT_DD))\n\t\t\tbreak;\n\t\trxd = *rxdp;\n\n\t\t/*\n\t\t * End of packet.\n\t\t *\n\t\t * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is\n\t\t * likely to be invalid and to be dropped by the various\n\t\t * validation checks performed by the network stack.\n\t\t *\n\t\t * Allocate a new mbuf to replenish the RX ring descriptor.\n\t\t * If the allocation fails:\n\t\t * - arrange for that RX descriptor to be the first one\n\t\t * being parsed the next time the receive function is\n\t\t * invoked [on the same queue].\n\t\t *\n\t\t * - Stop parsing the RX ring and return immediately.\n\t\t *\n\t\t * This policy do not drop the packet received in the RX\n\t\t * descriptor for which the allocation of a new mbuf failed.\n\t\t * Thus, it allows that packet to be later retrieved if\n\t\t * mbuf have been freed in the mean time.\n\t\t * As a side effect, holding RX descriptors instead of\n\t\t * systematically giving them back to the NIC may lead to\n\t\t * RX ring exhaustion situations.\n\t\t * However, the NIC can gracefully prevent such situations\n\t\t * to happen by sending specific \"back-pressure\" flow control\n\t\t * frames to its peer(s).\n\t\t */\n\t\tPMD_RX_LOG(DEBUG, \"port_id=%u queue_id=%u rx_id=%u \"\n\t\t\t \"status=0x%x pkt_len=%u\",\n\t\t\t (unsigned) rxq->port_id, (unsigned) rxq->queue_id,\n\t\t\t (unsigned) rx_id, (unsigned) status,\n\t\t\t (unsigned) rte_le_to_cpu_16(rxd.length));\n\n\t\tnmb = rte_rxmbuf_alloc(rxq->mb_pool);\n\t\tif (nmb == NULL) {\n\t\t\tPMD_RX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u \"\n\t\t\t\t \"queue_id=%u\",\n\t\t\t\t (unsigned) rxq->port_id,\n\t\t\t\t (unsigned) rxq->queue_id);\n\t\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;\n\t\t\tbreak;\n\t\t}\n\n\t\tnb_hold++;\n\t\trxe = &sw_ring[rx_id];\n\t\trx_id++;\n\t\tif (rx_id == rxq->nb_rx_desc)\n\t\t\trx_id = 0;\n\n\t\t/* Prefetch next mbuf while processing current one. */\n\t\trte_em_prefetch(sw_ring[rx_id].mbuf);\n\n\t\t/*\n\t\t * When next RX descriptor is on a cache-line boundary,\n\t\t * prefetch the next 4 RX descriptors and the next 8 pointers\n\t\t * to mbufs.\n\t\t */\n\t\tif ((rx_id & 0x3) == 0) {\n\t\t\trte_em_prefetch(&rx_ring[rx_id]);\n\t\t\trte_em_prefetch(&sw_ring[rx_id]);\n\t\t}\n\n\t\t/* Rearm RXD: attach new mbuf and reset status to zero. */\n\n\t\trxm = rxe->mbuf;\n\t\trxe->mbuf = nmb;\n\t\tdma_addr =\n\t\t\trte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));\n\t\trxdp->buffer_addr = dma_addr;\n\t\trxdp->status = 0;\n\n\t\t/*\n\t\t * Initialize the returned mbuf.\n\t\t * 1) setup generic mbuf fields:\n\t\t * - number of segments,\n\t\t * - next segment,\n\t\t * - packet length,\n\t\t * - RX port identifier.\n\t\t * 2) integrate hardware offload data, if any:\n\t\t * - RSS flag & hash,\n\t\t * - IP checksum flag,\n\t\t * - VLAN TCI, if any,\n\t\t * - error flags.\n\t\t */\n\t\tpkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.length) -\n\t\t\t\trxq->crc_len);\n\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n\t\trte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);\n\t\trxm->nb_segs = 1;\n\t\trxm->next = NULL;\n\t\trxm->pkt_len = pkt_len;\n\t\trxm->data_len = pkt_len;\n\t\trxm->port = rxq->port_id;\n\n\t\trxm->ol_flags = rx_desc_status_to_pkt_flags(status);\n\t\trxm->ol_flags = rxm->ol_flags |\n\t\t\t\trx_desc_error_to_pkt_flags(rxd.errors);\n\n\t\t/* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */\n\t\trxm->vlan_tci = rte_le_to_cpu_16(rxd.special);\n\n\t\t/*\n\t\t * Store the mbuf address into the next entry of the array\n\t\t * of returned packets.\n\t\t */\n\t\trx_pkts[nb_rx++] = rxm;\n\t}\n\trxq->rx_tail = rx_id;\n\n\t/*\n\t * If the number of free RX descriptors is greater than the RX free\n\t * threshold of the queue, advance the Receive Descriptor Tail (RDT)\n\t * register.\n\t * Update the RDT with the value of the last processed RX descriptor\n\t * minus 1, to guarantee that the RDT register is never equal to the\n\t * RDH register, which creates a \"full\" ring situtation from the\n\t * hardware point of view...\n\t */\n\tnb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);\n\tif (nb_hold > rxq->rx_free_thresh) {\n\t\tPMD_RX_LOG(DEBUG, \"port_id=%u queue_id=%u rx_tail=%u \"\n\t\t\t \"nb_hold=%u nb_rx=%u\",\n\t\t\t (unsigned) rxq->port_id, (unsigned) rxq->queue_id,\n\t\t\t (unsigned) rx_id, (unsigned) nb_hold,\n\t\t\t (unsigned) nb_rx);\n\t\trx_id = (uint16_t) ((rx_id == 0) ?\n\t\t\t(rxq->nb_rx_desc - 1) : (rx_id - 1));\n\t\tE1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);\n\t\tnb_hold = 0;\n\t}\n\trxq->nb_rx_hold = nb_hold;\n\treturn (nb_rx);\n}\n\nuint16_t\neth_em_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\t\t uint16_t nb_pkts)\n{\n\tstruct em_rx_queue *rxq;\n\tvolatile struct e1000_rx_desc *rx_ring;\n\tvolatile struct e1000_rx_desc *rxdp;\n\tstruct em_rx_entry *sw_ring;\n\tstruct em_rx_entry *rxe;\n\tstruct rte_mbuf *first_seg;\n\tstruct rte_mbuf *last_seg;\n\tstruct rte_mbuf *rxm;\n\tstruct rte_mbuf *nmb;\n\tstruct e1000_rx_desc rxd;\n\tuint64_t dma; /* Physical address of mbuf data buffer */\n\tuint16_t rx_id;\n\tuint16_t nb_rx;\n\tuint16_t nb_hold;\n\tuint16_t data_len;\n\tuint8_t status;\n\n\trxq = rx_queue;\n\n\tnb_rx = 0;\n\tnb_hold = 0;\n\trx_id = rxq->rx_tail;\n\trx_ring = rxq->rx_ring;\n\tsw_ring = rxq->sw_ring;\n\n\t/*\n\t * Retrieve RX context of current packet, if any.\n\t */\n\tfirst_seg = rxq->pkt_first_seg;\n\tlast_seg = rxq->pkt_last_seg;\n\n\twhile (nb_rx < nb_pkts) {\n\tnext_desc:\n\t\t/*\n\t\t * The order of operations here is important as the DD status\n\t\t * bit must not be read after any other descriptor fields.\n\t\t * rx_ring and rxdp are pointing to volatile data so the order\n\t\t * of accesses cannot be reordered by the compiler. If they were\n\t\t * not volatile, they could be reordered which could lead to\n\t\t * using invalid descriptor fields when read from rxd.\n\t\t */\n\t\trxdp = &rx_ring[rx_id];\n\t\tstatus = rxdp->status;\n\t\tif (! (status & E1000_RXD_STAT_DD))\n\t\t\tbreak;\n\t\trxd = *rxdp;\n\n\t\t/*\n\t\t * Descriptor done.\n\t\t *\n\t\t * Allocate a new mbuf to replenish the RX ring descriptor.\n\t\t * If the allocation fails:\n\t\t * - arrange for that RX descriptor to be the first one\n\t\t * being parsed the next time the receive function is\n\t\t * invoked [on the same queue].\n\t\t *\n\t\t * - Stop parsing the RX ring and return immediately.\n\t\t *\n\t\t * This policy does not drop the packet received in the RX\n\t\t * descriptor for which the allocation of a new mbuf failed.\n\t\t * Thus, it allows that packet to be later retrieved if\n\t\t * mbuf have been freed in the mean time.\n\t\t * As a side effect, holding RX descriptors instead of\n\t\t * systematically giving them back to the NIC may lead to\n\t\t * RX ring exhaustion situations.\n\t\t * However, the NIC can gracefully prevent such situations\n\t\t * to happen by sending specific \"back-pressure\" flow control\n\t\t * frames to its peer(s).\n\t\t */\n\t\tPMD_RX_LOG(DEBUG, \"port_id=%u queue_id=%u rx_id=%u \"\n\t\t\t \"status=0x%x data_len=%u\",\n\t\t\t (unsigned) rxq->port_id, (unsigned) rxq->queue_id,\n\t\t\t (unsigned) rx_id, (unsigned) status,\n\t\t\t (unsigned) rte_le_to_cpu_16(rxd.length));\n\n\t\tnmb = rte_rxmbuf_alloc(rxq->mb_pool);\n\t\tif (nmb == NULL) {\n\t\t\tPMD_RX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u \"\n\t\t\t\t \"queue_id=%u\", (unsigned) rxq->port_id,\n\t\t\t\t (unsigned) rxq->queue_id);\n\t\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;\n\t\t\tbreak;\n\t\t}\n\n\t\tnb_hold++;\n\t\trxe = &sw_ring[rx_id];\n\t\trx_id++;\n\t\tif (rx_id == rxq->nb_rx_desc)\n\t\t\trx_id = 0;\n\n\t\t/* Prefetch next mbuf while processing current one. */\n\t\trte_em_prefetch(sw_ring[rx_id].mbuf);\n\n\t\t/*\n\t\t * When next RX descriptor is on a cache-line boundary,\n\t\t * prefetch the next 4 RX descriptors and the next 8 pointers\n\t\t * to mbufs.\n\t\t */\n\t\tif ((rx_id & 0x3) == 0) {\n\t\t\trte_em_prefetch(&rx_ring[rx_id]);\n\t\t\trte_em_prefetch(&sw_ring[rx_id]);\n\t\t}\n\n\t\t/*\n\t\t * Update RX descriptor with the physical address of the new\n\t\t * data buffer of the new allocated mbuf.\n\t\t */\n\t\trxm = rxe->mbuf;\n\t\trxe->mbuf = nmb;\n\t\tdma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));\n\t\trxdp->buffer_addr = dma;\n\t\trxdp->status = 0;\n\n\t\t/*\n\t\t * Set data length & data buffer address of mbuf.\n\t\t */\n\t\tdata_len = rte_le_to_cpu_16(rxd.length);\n\t\trxm->data_len = data_len;\n\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n\n\t\t/*\n\t\t * If this is the first buffer of the received packet,\n\t\t * set the pointer to the first mbuf of the packet and\n\t\t * initialize its context.\n\t\t * Otherwise, update the total length and the number of segments\n\t\t * of the current scattered packet, and update the pointer to\n\t\t * the last mbuf of the current packet.\n\t\t */\n\t\tif (first_seg == NULL) {\n\t\t\tfirst_seg = rxm;\n\t\t\tfirst_seg->pkt_len = data_len;\n\t\t\tfirst_seg->nb_segs = 1;\n\t\t} else {\n\t\t\tfirst_seg->pkt_len += data_len;\n\t\t\tfirst_seg->nb_segs++;\n\t\t\tlast_seg->next = rxm;\n\t\t}\n\n\t\t/*\n\t\t * If this is not the last buffer of the received packet,\n\t\t * update the pointer to the last mbuf of the current scattered\n\t\t * packet and continue to parse the RX ring.\n\t\t */\n\t\tif (! (status & E1000_RXD_STAT_EOP)) {\n\t\t\tlast_seg = rxm;\n\t\t\tgoto next_desc;\n\t\t}\n\n\t\t/*\n\t\t * This is the last buffer of the received packet.\n\t\t * If the CRC is not stripped by the hardware:\n\t\t * - Subtract the CRC\tlength from the total packet length.\n\t\t * - If the last buffer only contains the whole CRC or a part\n\t\t * of it, free the mbuf associated to the last buffer.\n\t\t * If part of the CRC is also contained in the previous\n\t\t * mbuf, subtract the length of that CRC part from the\n\t\t * data length of the previous mbuf.\n\t\t */\n\t\trxm->next = NULL;\n\t\tif (unlikely(rxq->crc_len > 0)) {\n\t\t\tfirst_seg->pkt_len -= ETHER_CRC_LEN;\n\t\t\tif (data_len <= ETHER_CRC_LEN) {\n\t\t\t\trte_pktmbuf_free_seg(rxm);\n\t\t\t\tfirst_seg->nb_segs--;\n\t\t\t\tlast_seg->data_len = (uint16_t)\n\t\t\t\t\t(last_seg->data_len -\n\t\t\t\t\t (ETHER_CRC_LEN - data_len));\n\t\t\t\tlast_seg->next = NULL;\n\t\t\t} else\n\t\t\t\trxm->data_len =\n\t\t\t\t\t(uint16_t) (data_len - ETHER_CRC_LEN);\n\t\t}\n\n\t\t/*\n\t\t * Initialize the first mbuf of the returned packet:\n\t\t * - RX port identifier,\n\t\t * - hardware offload data, if any:\n\t\t * - IP checksum flag,\n\t\t * - error flags.\n\t\t */\n\t\tfirst_seg->port = rxq->port_id;\n\n\t\tfirst_seg->ol_flags = rx_desc_status_to_pkt_flags(status);\n\t\tfirst_seg->ol_flags = first_seg->ol_flags |\n\t\t\t\t\trx_desc_error_to_pkt_flags(rxd.errors);\n\n\t\t/* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */\n\t\trxm->vlan_tci = rte_le_to_cpu_16(rxd.special);\n\n\t\t/* Prefetch data of first segment, if configured to do so. */\n\t\trte_packet_prefetch((char *)first_seg->buf_addr +\n\t\t\tfirst_seg->data_off);\n\n\t\t/*\n\t\t * Store the mbuf address into the next entry of the array\n\t\t * of returned packets.\n\t\t */\n\t\trx_pkts[nb_rx++] = first_seg;\n\n\t\t/*\n\t\t * Setup receipt context for a new packet.\n\t\t */\n\t\tfirst_seg = NULL;\n\t}\n\n\t/*\n\t * Record index of the next RX descriptor to probe.\n\t */\n\trxq->rx_tail = rx_id;\n\n\t/*\n\t * Save receive context.\n\t */\n\trxq->pkt_first_seg = first_seg;\n\trxq->pkt_last_seg = last_seg;\n\n\t/*\n\t * If the number of free RX descriptors is greater than the RX free\n\t * threshold of the queue, advance the Receive Descriptor Tail (RDT)\n\t * register.\n\t * Update the RDT with the value of the last processed RX descriptor\n\t * minus 1, to guarantee that the RDT register is never equal to the\n\t * RDH register, which creates a \"full\" ring situtation from the\n\t * hardware point of view...\n\t */\n\tnb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);\n\tif (nb_hold > rxq->rx_free_thresh) {\n\t\tPMD_RX_LOG(DEBUG, \"port_id=%u queue_id=%u rx_tail=%u \"\n\t\t\t \"nb_hold=%u nb_rx=%u\",\n\t\t\t (unsigned) rxq->port_id, (unsigned) rxq->queue_id,\n\t\t\t (unsigned) rx_id, (unsigned) nb_hold,\n\t\t\t (unsigned) nb_rx);\n\t\trx_id = (uint16_t) ((rx_id == 0) ?\n\t\t\t(rxq->nb_rx_desc - 1) : (rx_id - 1));\n\t\tE1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);\n\t\tnb_hold = 0;\n\t}\n\trxq->nb_rx_hold = nb_hold;\n\treturn (nb_rx);\n}\n\n/*\n * Rings setup and release.\n *\n * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be\n * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.\n * This will also optimize cache line size effect.\n * H/W supports up to cache line size 128.\n */\n#define EM_ALIGN 128\n\n/*\n * Maximum number of Ring Descriptors.\n *\n * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring\n * desscriptors should meet the following condition:\n * (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0\n */\n#define EM_MIN_RING_DESC 32\n#define EM_MAX_RING_DESC 4096\n\n#define\tEM_MAX_BUF_SIZE 16384\n#define EM_RCTL_FLXBUF_STEP 1024\n\nstatic const struct rte_memzone *\nring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,\n\t\tuint16_t queue_id, uint32_t ring_size, int socket_id)\n{\n\tconst struct rte_memzone *mz;\n\tchar z_name[RTE_MEMZONE_NAMESIZE];\n\n\tsnprintf(z_name, sizeof(z_name), \"%s_%s_%d_%d\",\n\t\tdev->driver->pci_drv.name, ring_name, dev->data->port_id,\n\t\tqueue_id);\n\n\tif ((mz = rte_memzone_lookup(z_name)) != 0)\n\t\treturn (mz);\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n\treturn rte_memzone_reserve_bounded(z_name, ring_size,\n\t\t\tsocket_id, 0, RTE_CACHE_LINE_SIZE, RTE_PGSIZE_2M);\n#else\n\treturn rte_memzone_reserve(z_name, ring_size, socket_id, 0);\n#endif\n}\n\nstatic void\nem_tx_queue_release_mbufs(struct em_tx_queue *txq)\n{\n\tunsigned i;\n\n\tif (txq->sw_ring != NULL) {\n\t\tfor (i = 0; i != txq->nb_tx_desc; i++) {\n\t\t\tif (txq->sw_ring[i].mbuf != NULL) {\n\t\t\t\trte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);\n\t\t\t\ttxq->sw_ring[i].mbuf = NULL;\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void\nem_tx_queue_release(struct em_tx_queue *txq)\n{\n\tif (txq != NULL) {\n\t\tem_tx_queue_release_mbufs(txq);\n\t\trte_free(txq->sw_ring);\n\t\trte_free(txq);\n\t}\n}\n\nvoid\neth_em_tx_queue_release(void *txq)\n{\n\tem_tx_queue_release(txq);\n}\n\n/* (Re)set dynamic em_tx_queue fields to defaults */\nstatic void\nem_reset_tx_queue(struct em_tx_queue *txq)\n{\n\tuint16_t i, nb_desc, prev;\n\tstatic const struct e1000_data_desc txd_init = {\n\t\t.upper.fields = {.status = E1000_TXD_STAT_DD},\n\t};\n\n\tnb_desc = txq->nb_tx_desc;\n\n\t/* Initialize ring entries */\n\n\tprev = (uint16_t) (nb_desc - 1);\n\n\tfor (i = 0; i < nb_desc; i++) {\n\t\ttxq->tx_ring[i] = txd_init;\n\t\ttxq->sw_ring[i].mbuf = NULL;\n\t\ttxq->sw_ring[i].last_id = i;\n\t\ttxq->sw_ring[prev].next_id = i;\n\t\tprev = i;\n\t}\n\n\t/*\n\t * Always allow 1 descriptor to be un-allocated to avoid\n\t * a H/W race condition\n\t */\n\ttxq->nb_tx_free = (uint16_t)(nb_desc - 1);\n\ttxq->last_desc_cleaned = (uint16_t)(nb_desc - 1);\n\ttxq->nb_tx_used = 0;\n\ttxq->tx_tail = 0;\n\n\tmemset((void*)&txq->ctx_cache, 0, sizeof (txq->ctx_cache));\n}\n\nint\neth_em_tx_queue_setup(struct rte_eth_dev *dev,\n\t\t\t uint16_t queue_idx,\n\t\t\t uint16_t nb_desc,\n\t\t\t unsigned int socket_id,\n\t\t\t const struct rte_eth_txconf *tx_conf)\n{\n\tconst struct rte_memzone *tz;\n\tstruct em_tx_queue *txq;\n\tstruct e1000_hw *hw;\n\tuint32_t tsize;\n\tuint16_t tx_rs_thresh, tx_free_thresh;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/*\n\t * Validate number of transmit descriptors.\n\t * It must not exceed hardware maximum, and must be multiple\n\t * of EM_ALIGN.\n\t */\n\tif (((nb_desc * sizeof(*txq->tx_ring)) % EM_ALIGN) != 0 ||\n\t\t\t(nb_desc > EM_MAX_RING_DESC) ||\n\t\t\t(nb_desc < EM_MIN_RING_DESC)) {\n\t\treturn -(EINVAL);\n\t}\n\n\ttx_free_thresh = tx_conf->tx_free_thresh;\n\tif (tx_free_thresh == 0)\n\t\ttx_free_thresh = (uint16_t)RTE_MIN(nb_desc / 4,\n\t\t\t\t\tDEFAULT_TX_FREE_THRESH);\n\n\ttx_rs_thresh = tx_conf->tx_rs_thresh;\n\tif (tx_rs_thresh == 0)\n\t\ttx_rs_thresh = (uint16_t)RTE_MIN(tx_free_thresh,\n\t\t\t\t\tDEFAULT_TX_RS_THRESH);\n\n\tif (tx_free_thresh >= (nb_desc - 3)) {\n\t\tPMD_INIT_LOG(ERR, \"tx_free_thresh must be less than the \"\n\t\t\t \"number of TX descriptors minus 3. \"\n\t\t\t \"(tx_free_thresh=%u port=%d queue=%d)\",\n\t\t\t (unsigned int)tx_free_thresh,\n\t\t\t (int)dev->data->port_id, (int)queue_idx);\n\t\treturn -(EINVAL);\n\t}\n\tif (tx_rs_thresh > tx_free_thresh) {\n\t\tPMD_INIT_LOG(ERR, \"tx_rs_thresh must be less than or equal to \"\n\t\t\t \"tx_free_thresh. (tx_free_thresh=%u \"\n\t\t\t \"tx_rs_thresh=%u port=%d queue=%d)\",\n\t\t\t (unsigned int)tx_free_thresh,\n\t\t\t (unsigned int)tx_rs_thresh,\n\t\t\t (int)dev->data->port_id,\n\t\t\t (int)queue_idx);\n\t\treturn -(EINVAL);\n\t}\n\n\t/*\n\t * If rs_bit_thresh is greater than 1, then TX WTHRESH should be\n\t * set to 0. If WTHRESH is greater than zero, the RS bit is ignored\n\t * by the NIC and all descriptors are written back after the NIC\n\t * accumulates WTHRESH descriptors.\n\t */\n\tif (tx_conf->tx_thresh.wthresh != 0 && tx_rs_thresh != 1) {\n\t\tPMD_INIT_LOG(ERR, \"TX WTHRESH must be set to 0 if \"\n\t\t\t \"tx_rs_thresh is greater than 1. (tx_rs_thresh=%u \"\n\t\t\t \"port=%d queue=%d)\", (unsigned int)tx_rs_thresh,\n\t\t\t (int)dev->data->port_id, (int)queue_idx);\n\t\treturn -(EINVAL);\n\t}\n\n\t/* Free memory prior to re-allocation if needed... */\n\tif (dev->data->tx_queues[queue_idx] != NULL) {\n\t\tem_tx_queue_release(dev->data->tx_queues[queue_idx]);\n\t\tdev->data->tx_queues[queue_idx] = NULL;\n\t}\n\n\t/*\n\t * Allocate TX ring hardware descriptors. A memzone large enough to\n\t * handle the maximum ring size is allocated in order to allow for\n\t * resizing in later calls to the queue setup function.\n\t */\n\ttsize = sizeof (txq->tx_ring[0]) * EM_MAX_RING_DESC;\n\tif ((tz = ring_dma_zone_reserve(dev, \"tx_ring\", queue_idx, tsize,\n\t\t\tsocket_id)) == NULL)\n\t\treturn (-ENOMEM);\n\n\t/* Allocate the tx queue data structure. */\n\tif ((txq = rte_zmalloc(\"ethdev TX queue\", sizeof(*txq),\n\t\t\tRTE_CACHE_LINE_SIZE)) == NULL)\n\t\treturn (-ENOMEM);\n\n\t/* Allocate software ring */\n\tif ((txq->sw_ring = rte_zmalloc(\"txq->sw_ring\",\n\t\t\tsizeof(txq->sw_ring[0]) * nb_desc,\n\t\t\tRTE_CACHE_LINE_SIZE)) == NULL) {\n\t\tem_tx_queue_release(txq);\n\t\treturn (-ENOMEM);\n\t}\n\n\ttxq->nb_tx_desc = nb_desc;\n\ttxq->tx_free_thresh = tx_free_thresh;\n\ttxq->tx_rs_thresh = tx_rs_thresh;\n\ttxq->pthresh = tx_conf->tx_thresh.pthresh;\n\ttxq->hthresh = tx_conf->tx_thresh.hthresh;\n\ttxq->wthresh = tx_conf->tx_thresh.wthresh;\n\ttxq->queue_id = queue_idx;\n\ttxq->port_id = dev->data->port_id;\n\n\ttxq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(queue_idx));\n#ifndef RTE_LIBRTE_XEN_DOM0\n\ttxq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;\n#else\n\ttxq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);\n#endif\n\ttxq->tx_ring = (struct e1000_data_desc *) tz->addr;\n\n\tPMD_INIT_LOG(DEBUG, \"sw_ring=%p hw_ring=%p dma_addr=0x%\"PRIx64,\n\t\t txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);\n\n\tem_reset_tx_queue(txq);\n\n\tdev->data->tx_queues[queue_idx] = txq;\n\treturn (0);\n}\n\nstatic void\nem_rx_queue_release_mbufs(struct em_rx_queue *rxq)\n{\n\tunsigned i;\n\n\tif (rxq->sw_ring != NULL) {\n\t\tfor (i = 0; i != rxq->nb_rx_desc; i++) {\n\t\t\tif (rxq->sw_ring[i].mbuf != NULL) {\n\t\t\t\trte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);\n\t\t\t\trxq->sw_ring[i].mbuf = NULL;\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void\nem_rx_queue_release(struct em_rx_queue *rxq)\n{\n\tif (rxq != NULL) {\n\t\tem_rx_queue_release_mbufs(rxq);\n\t\trte_free(rxq->sw_ring);\n\t\trte_free(rxq);\n\t}\n}\n\nvoid\neth_em_rx_queue_release(void *rxq)\n{\n\tem_rx_queue_release(rxq);\n}\n\n/* Reset dynamic em_rx_queue fields back to defaults */\nstatic void\nem_reset_rx_queue(struct em_rx_queue *rxq)\n{\n\trxq->rx_tail = 0;\n\trxq->nb_rx_hold = 0;\n\trxq->pkt_first_seg = NULL;\n\trxq->pkt_last_seg = NULL;\n}\n\nint\neth_em_rx_queue_setup(struct rte_eth_dev *dev,\n\t\tuint16_t queue_idx,\n\t\tuint16_t nb_desc,\n\t\tunsigned int socket_id,\n\t\tconst struct rte_eth_rxconf *rx_conf,\n\t\tstruct rte_mempool *mp)\n{\n\tconst struct rte_memzone *rz;\n\tstruct em_rx_queue *rxq;\n\tstruct e1000_hw *hw;\n\tuint32_t rsize;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/*\n\t * Validate number of receive descriptors.\n\t * It must not exceed hardware maximum, and must be multiple\n\t * of EM_ALIGN.\n\t */\n\tif (((nb_desc * sizeof(rxq->rx_ring[0])) % EM_ALIGN) != 0 ||\n\t\t\t(nb_desc > EM_MAX_RING_DESC) ||\n\t\t\t(nb_desc < EM_MIN_RING_DESC)) {\n\t\treturn (-EINVAL);\n\t}\n\n\t/*\n\t * EM devices don't support drop_en functionality\n\t */\n\tif (rx_conf->rx_drop_en) {\n\t\tPMD_INIT_LOG(ERR, \"drop_en functionality not supported by \"\n\t\t\t \"device\");\n\t\treturn (-EINVAL);\n\t}\n\n\t/* Free memory prior to re-allocation if needed. */\n\tif (dev->data->rx_queues[queue_idx] != NULL) {\n\t\tem_rx_queue_release(dev->data->rx_queues[queue_idx]);\n\t\tdev->data->rx_queues[queue_idx] = NULL;\n\t}\n\n\t/* Allocate RX ring for max possible mumber of hardware descriptors. */\n\trsize = sizeof (rxq->rx_ring[0]) * EM_MAX_RING_DESC;\n\tif ((rz = ring_dma_zone_reserve(dev, \"rx_ring\", queue_idx, rsize,\n\t\t\tsocket_id)) == NULL)\n\t\treturn (-ENOMEM);\n\n\t/* Allocate the RX queue data structure. */\n\tif ((rxq = rte_zmalloc(\"ethdev RX queue\", sizeof(*rxq),\n\t\t\tRTE_CACHE_LINE_SIZE)) == NULL)\n\t\treturn (-ENOMEM);\n\n\t/* Allocate software ring. */\n\tif ((rxq->sw_ring = rte_zmalloc(\"rxq->sw_ring\",\n\t\t\tsizeof (rxq->sw_ring[0]) * nb_desc,\n\t\t\tRTE_CACHE_LINE_SIZE)) == NULL) {\n\t\tem_rx_queue_release(rxq);\n\t\treturn (-ENOMEM);\n\t}\n\n\trxq->mb_pool = mp;\n\trxq->nb_rx_desc = nb_desc;\n\trxq->pthresh = rx_conf->rx_thresh.pthresh;\n\trxq->hthresh = rx_conf->rx_thresh.hthresh;\n\trxq->wthresh = rx_conf->rx_thresh.wthresh;\n\trxq->rx_free_thresh = rx_conf->rx_free_thresh;\n\trxq->queue_id = queue_idx;\n\trxq->port_id = dev->data->port_id;\n\trxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?\n\t\t\t\t0 : ETHER_CRC_LEN);\n\n\trxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(queue_idx));\n\trxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(queue_idx));\n#ifndef RTE_LIBRTE_XEN_DOM0\n\trxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;\n#else\n\trxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);\n#endif\n\trxq->rx_ring = (struct e1000_rx_desc *) rz->addr;\n\n\tPMD_INIT_LOG(DEBUG, \"sw_ring=%p hw_ring=%p dma_addr=0x%\"PRIx64,\n\t\t rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);\n\n\tdev->data->rx_queues[queue_idx] = rxq;\n\tem_reset_rx_queue(rxq);\n\n\treturn (0);\n}\n\nuint32_t\neth_em_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n{\n#define EM_RXQ_SCAN_INTERVAL 4\n\tvolatile struct e1000_rx_desc *rxdp;\n\tstruct em_rx_queue *rxq;\n\tuint32_t desc = 0;\n\n\tif (rx_queue_id >= dev->data->nb_rx_queues) {\n\t\tPMD_RX_LOG(DEBUG, \"Invalid RX queue_id=%d\", rx_queue_id);\n\t\treturn 0;\n\t}\n\n\trxq = dev->data->rx_queues[rx_queue_id];\n\trxdp = &(rxq->rx_ring[rxq->rx_tail]);\n\n\twhile ((desc < rxq->nb_rx_desc) &&\n\t\t(rxdp->status & E1000_RXD_STAT_DD)) {\n\t\tdesc += EM_RXQ_SCAN_INTERVAL;\n\t\trxdp += EM_RXQ_SCAN_INTERVAL;\n\t\tif (rxq->rx_tail + desc >= rxq->nb_rx_desc)\n\t\t\trxdp = &(rxq->rx_ring[rxq->rx_tail +\n\t\t\t\tdesc - rxq->nb_rx_desc]);\n\t}\n\n\treturn desc;\n}\n\nint\neth_em_rx_descriptor_done(void *rx_queue, uint16_t offset)\n{\n\tvolatile struct e1000_rx_desc *rxdp;\n\tstruct em_rx_queue *rxq = rx_queue;\n\tuint32_t desc;\n\n\tif (unlikely(offset >= rxq->nb_rx_desc))\n\t\treturn 0;\n\tdesc = rxq->rx_tail + offset;\n\tif (desc >= rxq->nb_rx_desc)\n\t\tdesc -= rxq->nb_rx_desc;\n\n\trxdp = &rxq->rx_ring[desc];\n\treturn !!(rxdp->status & E1000_RXD_STAT_DD);\n}\n\nvoid\nem_dev_clear_queues(struct rte_eth_dev *dev)\n{\n\tuint16_t i;\n\tstruct em_tx_queue *txq;\n\tstruct em_rx_queue *rxq;\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\ttxq = dev->data->tx_queues[i];\n\t\tif (txq != NULL) {\n\t\t\tem_tx_queue_release_mbufs(txq);\n\t\t\tem_reset_tx_queue(txq);\n\t\t}\n\t}\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\trxq = dev->data->rx_queues[i];\n\t\tif (rxq != NULL) {\n\t\t\tem_rx_queue_release_mbufs(rxq);\n\t\t\tem_reset_rx_queue(rxq);\n\t\t}\n\t}\n}\n\nvoid\nem_dev_free_queues(struct rte_eth_dev *dev)\n{\n\tuint16_t i;\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\teth_em_rx_queue_release(dev->data->rx_queues[i]);\n\t\tdev->data->rx_queues[i] = NULL;\n\t}\n\tdev->data->nb_rx_queues = 0;\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\teth_em_tx_queue_release(dev->data->tx_queues[i]);\n\t\tdev->data->tx_queues[i] = NULL;\n\t}\n\tdev->data->nb_tx_queues = 0;\n}\n\n/*\n * Takes as input/output parameter RX buffer size.\n * Returns (BSIZE | BSEX | FLXBUF) fields of RCTL register.\n */\nstatic uint32_t\nem_rctl_bsize(__rte_unused enum e1000_mac_type hwtyp, uint32_t *bufsz)\n{\n\t/*\n\t * For BSIZE & BSEX all configurable sizes are:\n\t * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);\n\t * 8192: rctl |= (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX);\n\t * 4096: rctl |= (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX);\n\t * 2048: rctl |= E1000_RCTL_SZ_2048;\n\t * 1024: rctl |= E1000_RCTL_SZ_1024;\n\t * 512: rctl |= E1000_RCTL_SZ_512;\n\t * 256: rctl |= E1000_RCTL_SZ_256;\n\t */\n\tstatic const struct {\n\t\tuint32_t bufsz;\n\t\tuint32_t rctl;\n\t} bufsz_to_rctl[] = {\n\t\t{16384, (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX)},\n\t\t{8192, (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX)},\n\t\t{4096, (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX)},\n\t\t{2048, E1000_RCTL_SZ_2048},\n\t\t{1024, E1000_RCTL_SZ_1024},\n\t\t{512, E1000_RCTL_SZ_512},\n\t\t{256, E1000_RCTL_SZ_256},\n\t};\n\n\tint i;\n\tuint32_t rctl_bsize;\n\n\trctl_bsize = *bufsz;\n\n\t/*\n\t * Starting from 82571 it is possible to specify RX buffer size\n\t * by RCTL.FLXBUF. When this field is different from zero, the\n\t * RX buffer size = RCTL.FLXBUF * 1K\n\t * (e.g. t is possible to specify RX buffer size 1,2,...,15KB).\n\t * It is working ok on real HW, but by some reason doesn't work\n\t * on VMware emulated 82574L.\n\t * So for now, always use BSIZE/BSEX to setup RX buffer size.\n\t * If you don't plan to use it on VMware emulated 82574L and\n\t * would like to specify RX buffer size in 1K granularity,\n\t * uncomment the following lines:\n\t * ***************************************************************\n\t * if (hwtyp >= e1000_82571 && hwtyp <= e1000_82574 &&\n\t *\t\trctl_bsize >= EM_RCTL_FLXBUF_STEP) {\n\t *\trctl_bsize /= EM_RCTL_FLXBUF_STEP;\n\t *\t*bufsz = rctl_bsize;\n\t *\treturn (rctl_bsize << E1000_RCTL_FLXBUF_SHIFT &\n\t *\t\tE1000_RCTL_FLXBUF_MASK);\n\t * }\n\t * ***************************************************************\n\t */\n\n\tfor (i = 0; i != sizeof(bufsz_to_rctl) / sizeof(bufsz_to_rctl[0]);\n\t\t\ti++) {\n\t\tif (rctl_bsize >= bufsz_to_rctl[i].bufsz) {\n\t\t\t*bufsz = bufsz_to_rctl[i].bufsz;\n\t\t\treturn (bufsz_to_rctl[i].rctl);\n\t\t}\n\t}\n\n\t/* Should never happen. */\n\treturn (-EINVAL);\n}\n\nstatic int\nem_alloc_rx_queue_mbufs(struct em_rx_queue *rxq)\n{\n\tstruct em_rx_entry *rxe = rxq->sw_ring;\n\tuint64_t dma_addr;\n\tunsigned i;\n\tstatic const struct e1000_rx_desc rxd_init = {\n\t\t.buffer_addr = 0,\n\t};\n\n\t/* Initialize software ring entries */\n\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n\t\tvolatile struct e1000_rx_desc *rxd;\n\t\tstruct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);\n\n\t\tif (mbuf == NULL) {\n\t\t\tPMD_INIT_LOG(ERR, \"RX mbuf alloc failed \"\n\t\t\t\t \"queue_id=%hu\", rxq->queue_id);\n\t\t\treturn (-ENOMEM);\n\t\t}\n\n\t\tdma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));\n\n\t\t/* Clear HW ring memory */\n\t\trxq->rx_ring[i] = rxd_init;\n\n\t\trxd = &rxq->rx_ring[i];\n\t\trxd->buffer_addr = dma_addr;\n\t\trxe[i].mbuf = mbuf;\n\t}\n\n\treturn 0;\n}\n\n/*********************************************************************\n *\n * Enable receive unit.\n *\n **********************************************************************/\nint\neth_em_rx_init(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw;\n\tstruct em_rx_queue *rxq;\n\tuint32_t rctl;\n\tuint32_t rfctl;\n\tuint32_t rxcsum;\n\tuint32_t rctl_bsize;\n\tuint16_t i;\n\tint ret;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/*\n\t * Make sure receives are disabled while setting\n\t * up the descriptor ring.\n\t */\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);\n\n\trfctl = E1000_READ_REG(hw, E1000_RFCTL);\n\n\t/* Disable extended descriptor type. */\n\trfctl &= ~E1000_RFCTL_EXTEN;\n\t/* Disable accelerated acknowledge */\n\tif (hw->mac.type == e1000_82574)\n\t\trfctl |= E1000_RFCTL_ACK_DIS;\n\n\tE1000_WRITE_REG(hw, E1000_RFCTL, rfctl);\n\n\t/*\n\t * XXX TEMPORARY WORKAROUND: on some systems with 82573\n\t * long latencies are observed, like Lenovo X60. This\n\t * change eliminates the problem, but since having positive\n\t * values in RDTR is a known source of problems on other\n\t * platforms another solution is being sought.\n\t */\n\tif (hw->mac.type == e1000_82573)\n\t\tE1000_WRITE_REG(hw, E1000_RDTR, 0x20);\n\n\tdev->rx_pkt_burst = (eth_rx_burst_t)eth_em_recv_pkts;\n\n\t/* Determine RX bufsize. */\n\trctl_bsize = EM_MAX_BUF_SIZE;\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tuint32_t buf_size;\n\n\t\trxq = dev->data->rx_queues[i];\n\t\tbuf_size = rte_pktmbuf_data_room_size(rxq->mb_pool) -\n\t\t\tRTE_PKTMBUF_HEADROOM;\n\t\trctl_bsize = RTE_MIN(rctl_bsize, buf_size);\n\t}\n\n\trctl |= em_rctl_bsize(hw->mac.type, &rctl_bsize);\n\n\t/* Configure and enable each RX queue. */\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tuint64_t bus_addr;\n\t\tuint32_t rxdctl;\n\n\t\trxq = dev->data->rx_queues[i];\n\n\t\t/* Allocate buffers for descriptor rings and setup queue */\n\t\tret = em_alloc_rx_queue_mbufs(rxq);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\t/*\n\t\t * Reset crc_len in case it was changed after queue setup by a\n\t\t * call to configure\n\t\t */\n\t\trxq->crc_len =\n\t\t\t(uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?\n\t\t\t\t\t\t\t0 : ETHER_CRC_LEN);\n\n\t\tbus_addr = rxq->rx_ring_phys_addr;\n\t\tE1000_WRITE_REG(hw, E1000_RDLEN(i),\n\t\t\t\trxq->nb_rx_desc *\n\t\t\t\tsizeof(*rxq->rx_ring));\n\t\tE1000_WRITE_REG(hw, E1000_RDBAH(i),\n\t\t\t\t(uint32_t)(bus_addr >> 32));\n\t\tE1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);\n\n\t\tE1000_WRITE_REG(hw, E1000_RDH(i), 0);\n\t\tE1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);\n\n\t\trxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));\n\t\trxdctl &= 0xFE000000;\n\t\trxdctl |= rxq->pthresh & 0x3F;\n\t\trxdctl |= (rxq->hthresh & 0x3F) << 8;\n\t\trxdctl |= (rxq->wthresh & 0x3F) << 16;\n\t\trxdctl |= E1000_RXDCTL_GRAN;\n\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);\n\n\t\t/*\n\t\t * Due to EM devices not having any sort of hardware\n\t\t * limit for packet length, jumbo frame of any size\n\t\t * can be accepted, thus we have to enable scattered\n\t\t * rx if jumbo frames are enabled (or if buffer size\n\t\t * is too small to accommodate non-jumbo packets)\n\t\t * to avoid splitting packets that don't fit into\n\t\t * one buffer.\n\t\t */\n\t\tif (dev->data->dev_conf.rxmode.jumbo_frame ||\n\t\t\t\trctl_bsize < ETHER_MAX_LEN) {\n\t\t\tif (!dev->data->scattered_rx)\n\t\t\t\tPMD_INIT_LOG(DEBUG, \"forcing scatter mode\");\n\t\t\tdev->rx_pkt_burst =\n\t\t\t\t(eth_rx_burst_t)eth_em_recv_scattered_pkts;\n\t\t\tdev->data->scattered_rx = 1;\n\t\t}\n\t}\n\n\tif (dev->data->dev_conf.rxmode.enable_scatter) {\n\t\tif (!dev->data->scattered_rx)\n\t\t\tPMD_INIT_LOG(DEBUG, \"forcing scatter mode\");\n\t\tdev->rx_pkt_burst = eth_em_recv_scattered_pkts;\n\t\tdev->data->scattered_rx = 1;\n\t}\n\n\t/*\n\t * Setup the Checksum Register.\n\t * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.\n\t */\n\trxcsum = E1000_READ_REG(hw, E1000_RXCSUM);\n\n\tif (dev->data->dev_conf.rxmode.hw_ip_checksum)\n\t\trxcsum |= E1000_RXCSUM_IPOFL;\n\telse\n\t\trxcsum &= ~E1000_RXCSUM_IPOFL;\n\tE1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);\n\n\t/* No MRQ or RSS support for now */\n\n\t/* Set early receive threshold on appropriate hw */\n\tif ((hw->mac.type == e1000_ich9lan ||\n\t\t\thw->mac.type == e1000_pch2lan ||\n\t\t\thw->mac.type == e1000_ich10lan) &&\n\t\t\tdev->data->dev_conf.rxmode.jumbo_frame == 1) {\n\t\tu32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));\n\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);\n\t\tE1000_WRITE_REG(hw, E1000_ERT, 0x100 | (1 << 13));\n\t}\n\n\tif (hw->mac.type == e1000_pch2lan) {\n\t\tif (dev->data->dev_conf.rxmode.jumbo_frame == 1)\n\t\t\te1000_lv_jumbo_workaround_ich8lan(hw, TRUE);\n\t\telse\n\t\t\te1000_lv_jumbo_workaround_ich8lan(hw, FALSE);\n\t}\n\n\t/* Setup the Receive Control Register. */\n\tif (dev->data->dev_conf.rxmode.hw_strip_crc)\n\t\trctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */\n\telse\n\t\trctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */\n\n\trctl &= ~(3 << E1000_RCTL_MO_SHIFT);\n\trctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |\n\t\tE1000_RCTL_RDMTS_HALF |\n\t\t(hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);\n\n\t/* Make sure VLAN Filters are off. */\n\trctl &= ~E1000_RCTL_VFE;\n\t/* Don't store bad packets. */\n\trctl &= ~E1000_RCTL_SBP;\n\t/* Legacy descriptor type. */\n\trctl &= ~E1000_RCTL_DTYP_MASK;\n\n\t/*\n\t * Configure support of jumbo frames, if any.\n\t */\n\tif (dev->data->dev_conf.rxmode.jumbo_frame == 1)\n\t\trctl |= E1000_RCTL_LPE;\n\telse\n\t\trctl &= ~E1000_RCTL_LPE;\n\n\t/* Enable Receives. */\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\n\treturn 0;\n}\n\n/*********************************************************************\n *\n * Enable transmit unit.\n *\n **********************************************************************/\nvoid\neth_em_tx_init(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw;\n\tstruct em_tx_queue *txq;\n\tuint32_t tctl;\n\tuint32_t txdctl;\n\tuint16_t i;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/* Setup the Base and Length of the Tx Descriptor Rings. */\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tuint64_t bus_addr;\n\n\t\ttxq = dev->data->tx_queues[i];\n\t\tbus_addr = txq->tx_ring_phys_addr;\n\t\tE1000_WRITE_REG(hw, E1000_TDLEN(i),\n\t\t\t\ttxq->nb_tx_desc *\n\t\t\t\tsizeof(*txq->tx_ring));\n\t\tE1000_WRITE_REG(hw, E1000_TDBAH(i),\n\t\t\t\t(uint32_t)(bus_addr >> 32));\n\t\tE1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);\n\n\t\t/* Setup the HW Tx Head and Tail descriptor pointers. */\n\t\tE1000_WRITE_REG(hw, E1000_TDT(i), 0);\n\t\tE1000_WRITE_REG(hw, E1000_TDH(i), 0);\n\n\t\t/* Setup Transmit threshold registers. */\n\t\ttxdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));\n\t\t/*\n\t\t * bit 22 is reserved, on some models should always be 0,\n\t\t * on others - always 1.\n\t\t */\n\t\ttxdctl &= E1000_TXDCTL_COUNT_DESC;\n\t\ttxdctl |= txq->pthresh & 0x3F;\n\t\ttxdctl |= (txq->hthresh & 0x3F) << 8;\n\t\ttxdctl |= (txq->wthresh & 0x3F) << 16;\n\t\ttxdctl |= E1000_TXDCTL_GRAN;\n\t\tE1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);\n\t}\n\n\t/* Program the Transmit Control Register. */\n\ttctl = E1000_READ_REG(hw, E1000_TCTL);\n\ttctl &= ~E1000_TCTL_CT;\n\ttctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |\n\t\t (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));\n\n\t/* This write will effectively turn on the transmit unit. */\n\tE1000_WRITE_REG(hw, E1000_TCTL, tctl);\n}\n" }, { "path": "drivers/net/e1000/igb_ethdev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"e1000_logs.h\"\n#include \"base/e1000_api.h\"\n#include \"e1000_ethdev.h\"\n#include \"igb_regs.h\"\n\n/*\n * Default values for port configuration\n */\n#define IGB_DEFAULT_RX_FREE_THRESH 32\n#define IGB_DEFAULT_RX_PTHRESH 8\n#define IGB_DEFAULT_RX_HTHRESH 8\n#define IGB_DEFAULT_RX_WTHRESH 0\n\n#define IGB_DEFAULT_TX_PTHRESH 32\n#define IGB_DEFAULT_TX_HTHRESH 0\n#define IGB_DEFAULT_TX_WTHRESH 0\n\n#define IGB_HKEY_MAX_INDEX 10\n\n/* Bit shift and mask */\n#define IGB_4_BIT_WIDTH (CHAR_BIT / 2)\n#define IGB_4_BIT_MASK RTE_LEN2MASK(IGB_4_BIT_WIDTH, uint8_t)\n#define IGB_8_BIT_WIDTH CHAR_BIT\n#define IGB_8_BIT_MASK UINT8_MAX\n\n/* Additional timesync values. */\n#define E1000_ETQF_FILTER_1588 3\n#define E1000_TIMINCA_INCVALUE 16000000\n#define E1000_TIMINCA_INIT ((0x02 << E1000_TIMINCA_16NS_SHIFT) \\\n\t\t\t\t| E1000_TIMINCA_INCVALUE)\n#define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000\n\nstatic int eth_igb_configure(struct rte_eth_dev *dev);\nstatic int eth_igb_start(struct rte_eth_dev *dev);\nstatic void eth_igb_stop(struct rte_eth_dev *dev);\nstatic void eth_igb_close(struct rte_eth_dev *dev);\nstatic void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);\nstatic void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);\nstatic void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);\nstatic void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);\nstatic int eth_igb_link_update(struct rte_eth_dev *dev,\n\t\t\t\tint wait_to_complete);\nstatic void eth_igb_stats_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_stats *rte_stats);\nstatic void eth_igb_stats_reset(struct rte_eth_dev *dev);\nstatic void eth_igb_infos_get(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_dev_info *dev_info);\nstatic void eth_igbvf_infos_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_dev_info *dev_info);\nstatic int eth_igb_flow_ctrl_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_fc_conf *fc_conf);\nstatic int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_fc_conf *fc_conf);\nstatic int eth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev);\n#ifdef RTE_NEXT_ABI\nstatic int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev);\n#endif\nstatic int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);\nstatic int eth_igb_interrupt_action(struct rte_eth_dev *dev);\nstatic void eth_igb_interrupt_handler(struct rte_intr_handle *handle,\n\t\t\t\t\t\t\tvoid *param);\nstatic int igb_hardware_init(struct e1000_hw *hw);\nstatic void igb_hw_control_acquire(struct e1000_hw *hw);\nstatic void igb_hw_control_release(struct e1000_hw *hw);\nstatic void igb_init_manageability(struct e1000_hw *hw);\nstatic void igb_release_manageability(struct e1000_hw *hw);\n\nstatic int eth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n\nstatic int eth_igb_vlan_filter_set(struct rte_eth_dev *dev,\n\t\tuint16_t vlan_id, int on);\nstatic void eth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);\nstatic void eth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask);\n\nstatic void igb_vlan_hw_filter_enable(struct rte_eth_dev *dev);\nstatic void igb_vlan_hw_filter_disable(struct rte_eth_dev *dev);\nstatic void igb_vlan_hw_strip_enable(struct rte_eth_dev *dev);\nstatic void igb_vlan_hw_strip_disable(struct rte_eth_dev *dev);\nstatic void igb_vlan_hw_extend_enable(struct rte_eth_dev *dev);\nstatic void igb_vlan_hw_extend_disable(struct rte_eth_dev *dev);\n\nstatic int eth_igb_led_on(struct rte_eth_dev *dev);\nstatic int eth_igb_led_off(struct rte_eth_dev *dev);\n\nstatic void igb_intr_disable(struct e1000_hw *hw);\nstatic int igb_get_rx_buffer_size(struct e1000_hw *hw);\nstatic void eth_igb_rar_set(struct rte_eth_dev *dev,\n\t\tstruct ether_addr *mac_addr,\n\t\tuint32_t index, uint32_t pool);\nstatic void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);\nstatic void eth_igb_default_mac_addr_set(struct rte_eth_dev *dev,\n\t\tstruct ether_addr *addr);\n\nstatic void igbvf_intr_disable(struct e1000_hw *hw);\nstatic int igbvf_dev_configure(struct rte_eth_dev *dev);\nstatic int igbvf_dev_start(struct rte_eth_dev *dev);\nstatic void igbvf_dev_stop(struct rte_eth_dev *dev);\nstatic void igbvf_dev_close(struct rte_eth_dev *dev);\nstatic int eth_igbvf_link_update(struct e1000_hw *hw);\nstatic void eth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats);\nstatic void eth_igbvf_stats_reset(struct rte_eth_dev *dev);\nstatic int igbvf_vlan_filter_set(struct rte_eth_dev *dev,\n\t\tuint16_t vlan_id, int on);\nstatic int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on);\nstatic void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on);\nstatic void igbvf_default_mac_addr_set(struct rte_eth_dev *dev,\n\t\tstruct ether_addr *addr);\nstatic int igbvf_get_reg_length(struct rte_eth_dev *dev);\nstatic int igbvf_get_regs(struct rte_eth_dev *dev,\n\t\tstruct rte_dev_reg_info *regs);\n\nstatic int eth_igb_rss_reta_update(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t\t uint16_t reta_size);\nstatic int eth_igb_rss_reta_query(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t\t uint16_t reta_size);\n\nstatic int eth_igb_syn_filter_set(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_syn_filter *filter,\n\t\t\tbool add);\nstatic int eth_igb_syn_filter_get(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_syn_filter *filter);\nstatic int eth_igb_syn_filter_handle(struct rte_eth_dev *dev,\n\t\t\tenum rte_filter_op filter_op,\n\t\t\tvoid *arg);\nstatic int igb_add_2tuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *ntuple_filter);\nstatic int igb_remove_2tuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *ntuple_filter);\nstatic int eth_igb_add_del_flex_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_flex_filter *filter,\n\t\t\tbool add);\nstatic int eth_igb_get_flex_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_flex_filter *filter);\nstatic int eth_igb_flex_filter_handle(struct rte_eth_dev *dev,\n\t\t\tenum rte_filter_op filter_op,\n\t\t\tvoid *arg);\nstatic int igb_add_5tuple_filter_82576(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *ntuple_filter);\nstatic int igb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *ntuple_filter);\nstatic int igb_add_del_ntuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *filter,\n\t\t\tbool add);\nstatic int igb_get_ntuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *filter);\nstatic int igb_ntuple_filter_handle(struct rte_eth_dev *dev,\n\t\t\t\tenum rte_filter_op filter_op,\n\t\t\t\tvoid *arg);\nstatic int igb_add_del_ethertype_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ethertype_filter *filter,\n\t\t\tbool add);\nstatic int igb_ethertype_filter_handle(struct rte_eth_dev *dev,\n\t\t\t\tenum rte_filter_op filter_op,\n\t\t\t\tvoid *arg);\nstatic int igb_get_ethertype_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ethertype_filter *filter);\nstatic int eth_igb_filter_ctrl(struct rte_eth_dev *dev,\n\t\t enum rte_filter_type filter_type,\n\t\t enum rte_filter_op filter_op,\n\t\t void *arg);\nstatic int eth_igb_get_reg_length(struct rte_eth_dev *dev);\nstatic int eth_igb_get_regs(struct rte_eth_dev *dev,\n\t\tstruct rte_dev_reg_info *regs);\nstatic int eth_igb_get_eeprom_length(struct rte_eth_dev *dev);\nstatic int eth_igb_get_eeprom(struct rte_eth_dev *dev,\n\t\tstruct rte_dev_eeprom_info *eeprom);\nstatic int eth_igb_set_eeprom(struct rte_eth_dev *dev,\n\t\tstruct rte_dev_eeprom_info *eeprom);\nstatic int eth_igb_set_mc_addr_list(struct rte_eth_dev *dev,\n\t\t\t\t struct ether_addr *mc_addr_set,\n\t\t\t\t uint32_t nb_mc_addr);\nstatic int igb_timesync_enable(struct rte_eth_dev *dev);\nstatic int igb_timesync_disable(struct rte_eth_dev *dev);\nstatic int igb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n\t\t\t\t\t struct timespec *timestamp,\n\t\t\t\t\t uint32_t flags);\nstatic int igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n\t\t\t\t\t struct timespec *timestamp);\n#ifdef RTE_NEXT_ABI\nstatic int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,\n\t\t\t\t\tuint16_t queue_id);\nstatic int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,\n\t\t\t\t\t uint16_t queue_id);\nstatic void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,\n\t\t\t\t uint8_t queue, uint8_t msix_vector);\nstatic void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,\n\t\t\t uint8_t index, uint8_t offset);\n#endif\nstatic void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);\n\n/*\n * Define VF Stats MACRO for Non \"cleared on read\" register\n */\n#define UPDATE_VF_STAT(reg, last, cur) \\\n{ \\\n\tu32 latest = E1000_READ_REG(hw, reg); \\\n\tcur += latest - last; \\\n\tlast = latest; \\\n}\n\n\n#define IGB_FC_PAUSE_TIME 0x0680\n#define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */\n#define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */\n\n#define IGBVF_PMD_NAME \"rte_igbvf_pmd\" /* PMD name */\n\nstatic enum e1000_fc_mode igb_fc_setting = e1000_fc_full;\n\n/*\n * The set of PCI devices this driver supports\n */\nstatic const struct rte_pci_id pci_id_igb_map[] = {\n\n#define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \"rte_pci_dev_ids.h\"\n\n{0},\n};\n\n/*\n * The set of PCI devices this driver supports (for 82576&I350 VF)\n */\nstatic const struct rte_pci_id pci_id_igbvf_map[] = {\n\n#define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \"rte_pci_dev_ids.h\"\n\n{0},\n};\n\nstatic const struct eth_dev_ops eth_igb_ops = {\n\t.dev_configure = eth_igb_configure,\n\t.dev_start = eth_igb_start,\n\t.dev_stop = eth_igb_stop,\n\t.dev_close = eth_igb_close,\n\t.promiscuous_enable = eth_igb_promiscuous_enable,\n\t.promiscuous_disable = eth_igb_promiscuous_disable,\n\t.allmulticast_enable = eth_igb_allmulticast_enable,\n\t.allmulticast_disable = eth_igb_allmulticast_disable,\n\t.link_update = eth_igb_link_update,\n\t.stats_get = eth_igb_stats_get,\n\t.stats_reset = eth_igb_stats_reset,\n\t.dev_infos_get = eth_igb_infos_get,\n\t.mtu_set = eth_igb_mtu_set,\n\t.vlan_filter_set = eth_igb_vlan_filter_set,\n\t.vlan_tpid_set = eth_igb_vlan_tpid_set,\n\t.vlan_offload_set = eth_igb_vlan_offload_set,\n\t.rx_queue_setup = eth_igb_rx_queue_setup,\n#ifdef RTE_NEXT_ABI\n\t.rx_queue_intr_enable = eth_igb_rx_queue_intr_enable,\n\t.rx_queue_intr_disable = eth_igb_rx_queue_intr_disable,\n#endif\n\t.rx_queue_release = eth_igb_rx_queue_release,\n\t.rx_queue_count = eth_igb_rx_queue_count,\n\t.rx_descriptor_done = eth_igb_rx_descriptor_done,\n\t.tx_queue_setup = eth_igb_tx_queue_setup,\n\t.tx_queue_release = eth_igb_tx_queue_release,\n\t.dev_led_on = eth_igb_led_on,\n\t.dev_led_off = eth_igb_led_off,\n\t.flow_ctrl_get = eth_igb_flow_ctrl_get,\n\t.flow_ctrl_set = eth_igb_flow_ctrl_set,\n\t.mac_addr_add = eth_igb_rar_set,\n\t.mac_addr_remove = eth_igb_rar_clear,\n\t.mac_addr_set = eth_igb_default_mac_addr_set,\n\t.reta_update = eth_igb_rss_reta_update,\n\t.reta_query = eth_igb_rss_reta_query,\n\t.rss_hash_update = eth_igb_rss_hash_update,\n\t.rss_hash_conf_get = eth_igb_rss_hash_conf_get,\n\t.filter_ctrl = eth_igb_filter_ctrl,\n\t.set_mc_addr_list = eth_igb_set_mc_addr_list,\n\t.timesync_enable = igb_timesync_enable,\n\t.timesync_disable = igb_timesync_disable,\n\t.timesync_read_rx_timestamp = igb_timesync_read_rx_timestamp,\n\t.timesync_read_tx_timestamp = igb_timesync_read_tx_timestamp,\n\t.get_reg_length = eth_igb_get_reg_length,\n\t.get_reg = eth_igb_get_regs,\n\t.get_eeprom_length = eth_igb_get_eeprom_length,\n\t.get_eeprom = eth_igb_get_eeprom,\n\t.set_eeprom = eth_igb_set_eeprom,\n};\n\n/*\n * dev_ops for virtual function, bare necessities for basic vf\n * operation have been implemented\n */\nstatic const struct eth_dev_ops igbvf_eth_dev_ops = {\n\t.dev_configure = igbvf_dev_configure,\n\t.dev_start = igbvf_dev_start,\n\t.dev_stop = igbvf_dev_stop,\n\t.dev_close = igbvf_dev_close,\n\t.link_update = eth_igb_link_update,\n\t.stats_get = eth_igbvf_stats_get,\n\t.stats_reset = eth_igbvf_stats_reset,\n\t.vlan_filter_set = igbvf_vlan_filter_set,\n\t.dev_infos_get = eth_igbvf_infos_get,\n\t.rx_queue_setup = eth_igb_rx_queue_setup,\n\t.rx_queue_release = eth_igb_rx_queue_release,\n\t.tx_queue_setup = eth_igb_tx_queue_setup,\n\t.tx_queue_release = eth_igb_tx_queue_release,\n\t.set_mc_addr_list = eth_igb_set_mc_addr_list,\n\t.mac_addr_set = igbvf_default_mac_addr_set,\n\t.get_reg_length = igbvf_get_reg_length,\n\t.get_reg = igbvf_get_regs,\n};\n\n/**\n * Atomically reads the link status information from global\n * structure rte_eth_dev.\n *\n * @param dev\n * - Pointer to the structure rte_eth_dev to read from.\n * - Pointer to the buffer to be saved with the link status.\n *\n * @return\n * - On success, zero.\n * - On failure, negative value.\n */\nstatic inline int\nrte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = link;\n\tstruct rte_eth_link *src = &(dev->data->dev_link);\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * Atomically writes the link status information into global\n * structure rte_eth_dev.\n *\n * @param dev\n * - Pointer to the structure rte_eth_dev to read from.\n * - Pointer to the buffer to be saved with the link status.\n *\n * @return\n * - On success, zero.\n * - On failure, negative value.\n */\nstatic inline int\nrte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = &(dev->data->dev_link);\n\tstruct rte_eth_link *src = link;\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic inline void\nigb_intr_enable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_interrupt *intr =\n\t\tE1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tE1000_WRITE_REG(hw, E1000_IMS, intr->mask);\n\tE1000_WRITE_FLUSH(hw);\n}\n\nstatic void\nigb_intr_disable(struct e1000_hw *hw)\n{\n\tE1000_WRITE_REG(hw, E1000_IMC, ~0);\n\tE1000_WRITE_FLUSH(hw);\n}\n\nstatic inline int32_t\nigb_pf_reset_hw(struct e1000_hw *hw)\n{\n\tuint32_t ctrl_ext;\n\tint32_t status;\n\n\tstatus = e1000_reset_hw(hw);\n\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t/* Set PF Reset Done bit so PF/VF Mail Ops can work */\n\tctrl_ext |= E1000_CTRL_EXT_PFRSTD;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\tE1000_WRITE_FLUSH(hw);\n\n\treturn status;\n}\n\nstatic void\nigb_identify_hardware(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\thw->vendor_id = dev->pci_dev->id.vendor_id;\n\thw->device_id = dev->pci_dev->id.device_id;\n\thw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;\n\thw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;\n\n\te1000_set_mac_type(hw);\n\n\t/* need to check if it is a vf device below */\n}\n\nstatic int\nigb_reset_swfw_lock(struct e1000_hw *hw)\n{\n\tint ret_val;\n\n\t/*\n\t * Do mac ops initialization manually here, since we will need\n\t * some function pointers set by this call.\n\t */\n\tret_val = e1000_init_mac_params(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/*\n\t * SMBI lock should not fail in this early stage. If this is the case,\n\t * it is due to an improper exit of the application.\n\t * So force the release of the faulty lock.\n\t */\n\tif (e1000_get_hw_semaphore_generic(hw) < 0) {\n\t\tPMD_DRV_LOG(DEBUG, \"SMBI lock released\");\n\t}\n\te1000_put_hw_semaphore_generic(hw);\n\n\tif (hw->mac.ops.acquire_swfw_sync != NULL) {\n\t\tuint16_t mask;\n\n\t\t/*\n\t\t * Phy lock should not fail in this early stage. If this is the case,\n\t\t * it is due to an improper exit of the application.\n\t\t * So force the release of the faulty lock.\n\t\t */\n\t\tmask = E1000_SWFW_PHY0_SM << hw->bus.func;\n\t\tif (hw->bus.func > E1000_FUNC_1)\n\t\t\tmask <<= 2;\n\t\tif (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"SWFW phy%d lock released\",\n\t\t\t\t hw->bus.func);\n\t\t}\n\t\thw->mac.ops.release_swfw_sync(hw, mask);\n\n\t\t/*\n\t\t * This one is more tricky since it is common to all ports; but\n\t\t * swfw_sync retries last long enough (1s) to be almost sure that if\n\t\t * lock can not be taken it is due to an improper lock of the\n\t\t * semaphore.\n\t\t */\n\t\tmask = E1000_SWFW_EEP_SM;\n\t\tif (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"SWFW common locks released\");\n\t\t}\n\t\thw->mac.ops.release_swfw_sync(hw, mask);\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\nstatic int\neth_igb_dev_init(struct rte_eth_dev *eth_dev)\n{\n\tint error = 0;\n\tstruct rte_pci_device *pci_dev;\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\tstruct e1000_vfta * shadow_vfta =\n\t\tE1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);\n\tstruct e1000_filter_info *filter_info =\n\t\tE1000_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);\n\tstruct e1000_adapter *adapter =\n\t\tE1000_DEV_PRIVATE(eth_dev->data->dev_private);\n\n\tuint32_t ctrl_ext;\n\n\tpci_dev = eth_dev->pci_dev;\n\teth_dev->dev_ops = ð_igb_ops;\n\teth_dev->rx_pkt_burst = ð_igb_recv_pkts;\n\teth_dev->tx_pkt_burst = ð_igb_xmit_pkts;\n\n\t/* for secondary processes, we don't initialise any further as primary\n\t * has already done this work. Only check we don't need a different\n\t * RX function */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY){\n\t\tif (eth_dev->data->scattered_rx)\n\t\t\teth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;\n\t\treturn 0;\n\t}\n\n\thw->hw_addr= (void *)pci_dev->mem_resource[0].addr;\n\n\tigb_identify_hardware(eth_dev);\n\tif (e1000_setup_init_funcs(hw, FALSE) != E1000_SUCCESS) {\n\t\terror = -EIO;\n\t\tgoto err_late;\n\t}\n\n\te1000_get_bus_info(hw);\n\n\t/* Reset any pending lock */\n\tif (igb_reset_swfw_lock(hw) != E1000_SUCCESS) {\n\t\terror = -EIO;\n\t\tgoto err_late;\n\t}\n\n\t/* Finish initialization */\n\tif (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {\n\t\terror = -EIO;\n\t\tgoto err_late;\n\t}\n\n\thw->mac.autoneg = 1;\n\thw->phy.autoneg_wait_to_complete = 0;\n\thw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;\n\n\t/* Copper options */\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\t\thw->phy.mdix = 0; /* AUTO_ALL_MODES */\n\t\thw->phy.disable_polarity_correction = 0;\n\t\thw->phy.ms_type = e1000_ms_hw_default;\n\t}\n\n\t/*\n\t * Start from a known state, this is important in reading the nvm\n\t * and mac from that.\n\t */\n\tigb_pf_reset_hw(hw);\n\n\t/* Make sure we have a good EEPROM before we read from it */\n\tif (e1000_validate_nvm_checksum(hw) < 0) {\n\t\t/*\n\t\t * Some PCI-E parts fail the first check due to\n\t\t * the link being in sleep state, call it again,\n\t\t * if it fails a second time its a real issue.\n\t\t */\n\t\tif (e1000_validate_nvm_checksum(hw) < 0) {\n\t\t\tPMD_INIT_LOG(ERR, \"EEPROM checksum invalid\");\n\t\t\terror = -EIO;\n\t\t\tgoto err_late;\n\t\t}\n\t}\n\n\t/* Read the permanent MAC address out of the EEPROM */\n\tif (e1000_read_mac_addr(hw) != 0) {\n\t\tPMD_INIT_LOG(ERR, \"EEPROM error while reading MAC address\");\n\t\terror = -EIO;\n\t\tgoto err_late;\n\t}\n\n\t/* Allocate memory for storing MAC addresses */\n\teth_dev->data->mac_addrs = rte_zmalloc(\"e1000\",\n\t\tETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);\n\tif (eth_dev->data->mac_addrs == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to allocate %d bytes needed to \"\n\t\t\t\t\t\t\"store MAC addresses\",\n\t\t\t\tETHER_ADDR_LEN * hw->mac.rar_entry_count);\n\t\terror = -ENOMEM;\n\t\tgoto err_late;\n\t}\n\n\t/* Copy the permanent MAC address */\n\tether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);\n\n\t/* initialize the vfta */\n\tmemset(shadow_vfta, 0, sizeof(*shadow_vfta));\n\n\t/* Now initialize the hardware */\n\tif (igb_hardware_init(hw) != 0) {\n\t\tPMD_INIT_LOG(ERR, \"Hardware initialization failed\");\n\t\trte_free(eth_dev->data->mac_addrs);\n\t\teth_dev->data->mac_addrs = NULL;\n\t\terror = -ENODEV;\n\t\tgoto err_late;\n\t}\n\thw->mac.get_link_status = 1;\n\tadapter->stopped = 0;\n\n\t/* Indicate SOL/IDER usage */\n\tif (e1000_check_reset_block(hw) < 0) {\n\t\tPMD_INIT_LOG(ERR, \"PHY reset is blocked due to\"\n\t\t\t\t\t\"SOL/IDER session\");\n\t}\n\n\t/* initialize PF if max_vfs not zero */\n\tigb_pf_host_init(eth_dev);\n\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t/* Set PF Reset Done bit so PF/VF Mail Ops can work */\n\tctrl_ext |= E1000_CTRL_EXT_PFRSTD;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\tE1000_WRITE_FLUSH(hw);\n\n\tPMD_INIT_LOG(DEBUG, \"port_id %d vendorID=0x%x deviceID=0x%x\",\n\t\t eth_dev->data->port_id, pci_dev->id.vendor_id,\n\t\t pci_dev->id.device_id);\n\n\t/* enable support intr */\n\tigb_intr_enable(eth_dev);\n\n\tTAILQ_INIT(&filter_info->flex_list);\n\tfilter_info->flex_mask = 0;\n\tTAILQ_INIT(&filter_info->twotuple_list);\n\tfilter_info->twotuple_mask = 0;\n\tTAILQ_INIT(&filter_info->fivetuple_list);\n\tfilter_info->fivetuple_mask = 0;\n\n\treturn 0;\n\nerr_late:\n\tigb_hw_control_release(hw);\n\n\treturn (error);\n}\n\nstatic int\neth_igb_dev_uninit(struct rte_eth_dev *eth_dev)\n{\n\tstruct rte_pci_device *pci_dev;\n\tstruct e1000_hw *hw;\n\tstruct e1000_adapter *adapter =\n\t\tE1000_DEV_PRIVATE(eth_dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn -EPERM;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\tpci_dev = eth_dev->pci_dev;\n\n\tif (adapter->stopped == 0)\n\t\teth_igb_close(eth_dev);\n\n\teth_dev->dev_ops = NULL;\n\teth_dev->rx_pkt_burst = NULL;\n\teth_dev->tx_pkt_burst = NULL;\n\n\t/* Reset any pending lock */\n\tigb_reset_swfw_lock(hw);\n\n\trte_free(eth_dev->data->mac_addrs);\n\teth_dev->data->mac_addrs = NULL;\n\n\t/* uninitialize PF if max_vfs not zero */\n\tigb_pf_host_uninit(eth_dev);\n\n\t/* disable uio intr before callback unregister */\n\trte_intr_disable(&(pci_dev->intr_handle));\n\trte_intr_callback_unregister(&(pci_dev->intr_handle),\n\t\teth_igb_interrupt_handler, (void *)eth_dev);\n\n\treturn 0;\n}\n\n/*\n * Virtual Function device init\n */\nstatic int\neth_igbvf_dev_init(struct rte_eth_dev *eth_dev)\n{\n\tstruct rte_pci_device *pci_dev;\n\tstruct e1000_adapter *adapter =\n\t\tE1000_DEV_PRIVATE(eth_dev->data->dev_private);\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\tint diag;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\teth_dev->dev_ops = &igbvf_eth_dev_ops;\n\teth_dev->rx_pkt_burst = ð_igb_recv_pkts;\n\teth_dev->tx_pkt_burst = ð_igb_xmit_pkts;\n\n\t/* for secondary processes, we don't initialise any further as primary\n\t * has already done this work. Only check we don't need a different\n\t * RX function */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY){\n\t\tif (eth_dev->data->scattered_rx)\n\t\t\teth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;\n\t\treturn 0;\n\t}\n\n\tpci_dev = eth_dev->pci_dev;\n\n\thw->device_id = pci_dev->id.device_id;\n\thw->vendor_id = pci_dev->id.vendor_id;\n\thw->hw_addr = (void *)pci_dev->mem_resource[0].addr;\n\tadapter->stopped = 0;\n\n\t/* Initialize the shared code (base driver) */\n\tdiag = e1000_setup_init_funcs(hw, TRUE);\n\tif (diag != 0) {\n\t\tPMD_INIT_LOG(ERR, \"Shared code init failed for igbvf: %d\",\n\t\t\tdiag);\n\t\treturn -EIO;\n\t}\n\n\t/* init_mailbox_params */\n\thw->mbx.ops.init_params(hw);\n\n\t/* Disable the interrupts for VF */\n\tigbvf_intr_disable(hw);\n\n\tdiag = hw->mac.ops.reset_hw(hw);\n\n\t/* Allocate memory for storing MAC addresses */\n\teth_dev->data->mac_addrs = rte_zmalloc(\"igbvf\", ETHER_ADDR_LEN *\n\t\thw->mac.rar_entry_count, 0);\n\tif (eth_dev->data->mac_addrs == NULL) {\n\t\tPMD_INIT_LOG(ERR,\n\t\t\t\"Failed to allocate %d bytes needed to store MAC \"\n\t\t\t\"addresses\",\n\t\t\tETHER_ADDR_LEN * hw->mac.rar_entry_count);\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Copy the permanent MAC address */\n\tether_addr_copy((struct ether_addr *) hw->mac.perm_addr,\n\t\t\tð_dev->data->mac_addrs[0]);\n\n\tPMD_INIT_LOG(DEBUG, \"port %d vendorID=0x%x deviceID=0x%x \"\n\t\t \"mac.type=%s\",\n\t\t eth_dev->data->port_id, pci_dev->id.vendor_id,\n\t\t pci_dev->id.device_id, \"igb_mac_82576_vf\");\n\n\treturn 0;\n}\n\nstatic int\neth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)\n{\n\tstruct e1000_adapter *adapter =\n\t\tE1000_DEV_PRIVATE(eth_dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn -EPERM;\n\n\tif (adapter->stopped == 0)\n\t\tigbvf_dev_close(eth_dev);\n\n\teth_dev->dev_ops = NULL;\n\teth_dev->rx_pkt_burst = NULL;\n\teth_dev->tx_pkt_burst = NULL;\n\n\trte_free(eth_dev->data->mac_addrs);\n\teth_dev->data->mac_addrs = NULL;\n\n\treturn 0;\n}\n\nstatic struct eth_driver rte_igb_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_igb_pmd\",\n\t\t.id_table = pci_id_igb_map,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |\n\t\t\tRTE_PCI_DRV_DETACHABLE,\n\t},\n\t.eth_dev_init = eth_igb_dev_init,\n\t.eth_dev_uninit = eth_igb_dev_uninit,\n\t.dev_private_size = sizeof(struct e1000_adapter),\n};\n\n/*\n * virtual function driver struct\n */\nstatic struct eth_driver rte_igbvf_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_igbvf_pmd\",\n\t\t.id_table = pci_id_igbvf_map,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,\n\t},\n\t.eth_dev_init = eth_igbvf_dev_init,\n\t.eth_dev_uninit = eth_igbvf_dev_uninit,\n\t.dev_private_size = sizeof(struct e1000_adapter),\n};\n\nstatic int\nrte_igb_pmd_init(const char *name __rte_unused, const char *params __rte_unused)\n{\n\trte_eth_driver_register(&rte_igb_pmd);\n\treturn 0;\n}\n\nstatic void\nigb_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\t/* RCTL: enable VLAN filter since VMDq always use VLAN filter */\n\tuint32_t rctl = E1000_READ_REG(hw, E1000_RCTL);\n\trctl |= E1000_RCTL_VFE;\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n}\n\n/*\n * VF Driver initialization routine.\n * Invoked one at EAL init time.\n * Register itself as the [Virtual Poll Mode] Driver of PCI IGB devices.\n */\nstatic int\nrte_igbvf_pmd_init(const char *name __rte_unused, const char *params __rte_unused)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\trte_eth_driver_register(&rte_igbvf_pmd);\n\treturn (0);\n}\n\nstatic int\neth_igb_configure(struct rte_eth_dev *dev)\n{\n\tstruct e1000_interrupt *intr =\n\t\tE1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\tintr->flags |= E1000_FLAG_NEED_LINK_UPDATE;\n\tPMD_INIT_FUNC_TRACE();\n\n\treturn (0);\n}\n\nstatic int\neth_igb_start(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_adapter *adapter =\n\t\tE1000_DEV_PRIVATE(dev->data->dev_private);\n\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n\tint ret, mask;\n#ifdef RTE_NEXT_ABI\n\tuint32_t intr_vector = 0;\n#endif\n\tuint32_t ctrl_ext;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* Power up the phy. Needed to make the link go Up */\n\te1000_power_up_phy(hw);\n\n\t/*\n\t * Packet Buffer Allocation (PBA)\n\t * Writing PBA sets the receive portion of the buffer\n\t * the remainder is used for the transmit buffer.\n\t */\n\tif (hw->mac.type == e1000_82575) {\n\t\tuint32_t pba;\n\n\t\tpba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */\n\t\tE1000_WRITE_REG(hw, E1000_PBA, pba);\n\t}\n\n\t/* Put the address into the Receive Address Array */\n\te1000_rar_set(hw, hw->mac.addr, 0);\n\n\t/* Initialize the hardware */\n\tif (igb_hardware_init(hw)) {\n\t\tPMD_INIT_LOG(ERR, \"Unable to initialize the hardware\");\n\t\treturn (-EIO);\n\t}\n\tadapter->stopped = 0;\n\n\tE1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);\n\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t/* Set PF Reset Done bit so PF/VF Mail Ops can work */\n\tctrl_ext |= E1000_CTRL_EXT_PFRSTD;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* configure PF module if SRIOV enabled */\n\tigb_pf_host_configure(dev);\n\n#ifdef RTE_NEXT_ABI\n\t/* check and configure queue intr-vector mapping */\n\tif (dev->data->dev_conf.intr_conf.rxq != 0)\n\t\tintr_vector = dev->data->nb_rx_queues;\n\n\tif (rte_intr_efd_enable(intr_handle, intr_vector))\n\t\treturn -1;\n\n\tif (rte_intr_dp_is_en(intr_handle)) {\n\t\tintr_handle->intr_vec =\n\t\t\trte_zmalloc(\"intr_vec\",\n\t\t\t\t dev->data->nb_rx_queues * sizeof(int), 0);\n\t\tif (intr_handle->intr_vec == NULL) {\n\t\t\tPMD_INIT_LOG(ERR, \"Failed to allocate %d rx_queues\"\n\t\t\t\t \" intr_vec\\n\", dev->data->nb_rx_queues);\n\t\t\treturn -ENOMEM;\n\t\t}\n\t}\n#endif\n\n\t/* confiugre msix for rx interrupt */\n\teth_igb_configure_msix_intr(dev);\n\n\t/* Configure for OS presence */\n\tigb_init_manageability(hw);\n\n\teth_igb_tx_init(dev);\n\n\t/* This can fail when allocating mbufs for descriptor rings */\n\tret = eth_igb_rx_init(dev);\n\tif (ret) {\n\t\tPMD_INIT_LOG(ERR, \"Unable to initialize RX hardware\");\n\t\tigb_dev_clear_queues(dev);\n\t\treturn ret;\n\t}\n\n\te1000_clear_hw_cntrs_base_generic(hw);\n\n\t/*\n\t * VLAN Offload Settings\n\t */\n\tmask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \\\n\t\t\tETH_VLAN_EXTEND_MASK;\n\teth_igb_vlan_offload_set(dev, mask);\n\n\tif (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {\n\t\t/* Enable VLAN filter since VMDq always use VLAN filter */\n\t\tigb_vmdq_vlan_hw_filter_enable(dev);\n\t}\n\n\tif ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||\n\t\t(hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i210) ||\n\t\t(hw->mac.type == e1000_i211)) {\n\t\t/* Configure EITR with the maximum possible value (0xFFFF) */\n\t\tE1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);\n\t}\n\n\t/* Setup link speed and duplex */\n\tswitch (dev->data->dev_conf.link_speed) {\n\tcase ETH_LINK_SPEED_AUTONEG:\n\t\tif (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;\n\t\telse if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;\n\t\telse if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;\n\t\telse\n\t\t\tgoto error_invalid_config;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_10:\n\t\tif (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = E1000_ALL_10_SPEED;\n\t\telse if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = ADVERTISE_10_HALF;\n\t\telse if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = ADVERTISE_10_FULL;\n\t\telse\n\t\t\tgoto error_invalid_config;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_100:\n\t\tif (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = E1000_ALL_100_SPEED;\n\t\telse if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = ADVERTISE_100_HALF;\n\t\telse if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)\n\t\t\thw->phy.autoneg_advertised = ADVERTISE_100_FULL;\n\t\telse\n\t\t\tgoto error_invalid_config;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_1000:\n\t\tif ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||\n\t\t\t\t(dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))\n\t\t\thw->phy.autoneg_advertised = ADVERTISE_1000_FULL;\n\t\telse\n\t\t\tgoto error_invalid_config;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_10000:\n\tdefault:\n\t\tgoto error_invalid_config;\n\t}\n\te1000_setup_link(hw);\n\n\t/* check if lsc interrupt feature is enabled */\n\tif (dev->data->dev_conf.intr_conf.lsc != 0) {\n\t\tif (rte_intr_allow_others(intr_handle)) {\n\t\t\trte_intr_callback_register(intr_handle,\n\t\t\t\t\t\t eth_igb_interrupt_handler,\n\t\t\t\t\t\t (void *)dev);\n\t\t\teth_igb_lsc_interrupt_setup(dev);\n\t\t} else\n\t\t\tPMD_INIT_LOG(INFO, \"lsc won't enable because of\"\n\t\t\t\t \" no intr multiplex\\n\");\n\t}\n\n#ifdef RTE_NEXT_ABI\n\t/* check if rxq interrupt is enabled */\n\tif (dev->data->dev_conf.intr_conf.rxq != 0)\n\t\teth_igb_rxq_interrupt_setup(dev);\n#endif\n\n\t/* enable uio/vfio intr/eventfd mapping */\n\trte_intr_enable(intr_handle);\n\n\t/* resume enabled intr since hw reset */\n\tigb_intr_enable(dev);\n\n\tPMD_INIT_LOG(DEBUG, \"<<\");\n\n\treturn (0);\n\nerror_invalid_config:\n\tPMD_INIT_LOG(ERR, \"Invalid link_speed/link_duplex (%u/%u) for port %u\",\n\t\t dev->data->dev_conf.link_speed,\n\t\t dev->data->dev_conf.link_duplex, dev->data->port_id);\n\tigb_dev_clear_queues(dev);\n\treturn (-EINVAL);\n}\n\n/*********************************************************************\n *\n * This routine disables all traffic on the adapter by issuing a\n * global reset on the MAC.\n *\n **********************************************************************/\nstatic void\neth_igb_stop(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_filter_info *filter_info =\n\t\tE1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tstruct rte_eth_link link;\n\tstruct e1000_flex_filter *p_flex;\n\tstruct e1000_5tuple_filter *p_5tuple, *p_5tuple_next;\n\tstruct e1000_2tuple_filter *p_2tuple, *p_2tuple_next;\n\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n\n\tigb_intr_disable(hw);\n\n\t/* disable intr eventfd mapping */\n\trte_intr_disable(intr_handle);\n\n\tigb_pf_reset_hw(hw);\n\tE1000_WRITE_REG(hw, E1000_WUC, 0);\n\n\t/* Set bit for Go Link disconnect */\n\tif (hw->mac.type >= e1000_82580) {\n\t\tuint32_t phpm_reg;\n\n\t\tphpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);\n\t\tphpm_reg |= E1000_82580_PM_GO_LINKD;\n\t\tE1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);\n\t}\n\n\t/* Power down the phy. Needed to make the link go Down */\n\tif (hw->phy.media_type == e1000_media_type_copper)\n\t\te1000_power_down_phy(hw);\n\telse\n\t\te1000_shutdown_fiber_serdes_link(hw);\n\n\tigb_dev_clear_queues(dev);\n\n\t/* clear the recorded link status */\n\tmemset(&link, 0, sizeof(link));\n\trte_igb_dev_atomic_write_link_status(dev, &link);\n\n\t/* Remove all flex filters of the device */\n\twhile ((p_flex = TAILQ_FIRST(&filter_info->flex_list))) {\n\t\tTAILQ_REMOVE(&filter_info->flex_list, p_flex, entries);\n\t\trte_free(p_flex);\n\t}\n\tfilter_info->flex_mask = 0;\n\n\t/* Remove all ntuple filters of the device */\n\tfor (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);\n\t p_5tuple != NULL; p_5tuple = p_5tuple_next) {\n\t\tp_5tuple_next = TAILQ_NEXT(p_5tuple, entries);\n\t\tTAILQ_REMOVE(&filter_info->fivetuple_list,\n\t\t\t p_5tuple, entries);\n\t\trte_free(p_5tuple);\n\t}\n\tfilter_info->fivetuple_mask = 0;\n\tfor (p_2tuple = TAILQ_FIRST(&filter_info->twotuple_list);\n\t p_2tuple != NULL; p_2tuple = p_2tuple_next) {\n\t\tp_2tuple_next = TAILQ_NEXT(p_2tuple, entries);\n\t\tTAILQ_REMOVE(&filter_info->twotuple_list,\n\t\t\t p_2tuple, entries);\n\t\trte_free(p_2tuple);\n\t}\n\tfilter_info->twotuple_mask = 0;\n\n#ifdef RTE_NEXT_ABI\n\t/* Clean datapath event and queue/vec mapping */\n\trte_intr_efd_disable(intr_handle);\n\tif (intr_handle->intr_vec != NULL) {\n\t\trte_free(intr_handle->intr_vec);\n\t\tintr_handle->intr_vec = NULL;\n\t}\n#endif\n}\n\nstatic void\neth_igb_close(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_adapter *adapter =\n\t\tE1000_DEV_PRIVATE(dev->data->dev_private);\n\tstruct rte_eth_link link;\n#ifdef RTE_NEXT_ABI\n\tstruct rte_pci_device *pci_dev;\n#endif\n\n\teth_igb_stop(dev);\n\tadapter->stopped = 1;\n\n\te1000_phy_hw_reset(hw);\n\tigb_release_manageability(hw);\n\tigb_hw_control_release(hw);\n\n\t/* Clear bit for Go Link disconnect */\n\tif (hw->mac.type >= e1000_82580) {\n\t\tuint32_t phpm_reg;\n\n\t\tphpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);\n\t\tphpm_reg &= ~E1000_82580_PM_GO_LINKD;\n\t\tE1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);\n\t}\n\n\tigb_dev_free_queues(dev);\n\n#ifdef RTE_NEXT_ABI\n\tpci_dev = dev->pci_dev;\n\tif (pci_dev->intr_handle.intr_vec) {\n\t\trte_free(pci_dev->intr_handle.intr_vec);\n\t\tpci_dev->intr_handle.intr_vec = NULL;\n\t}\n#endif\n\n\tmemset(&link, 0, sizeof(link));\n\trte_igb_dev_atomic_write_link_status(dev, &link);\n}\n\nstatic int\nigb_get_rx_buffer_size(struct e1000_hw *hw)\n{\n\tuint32_t rx_buf_size;\n\tif (hw->mac.type == e1000_82576) {\n\t\trx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;\n\t} else if (hw->mac.type == e1000_82580 || hw->mac.type == e1000_i350) {\n\t\t/* PBS needs to be translated according to a lookup table */\n\t\trx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);\n\t\trx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);\n\t\trx_buf_size = (rx_buf_size << 10);\n\t} else if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {\n\t\trx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0x3f) << 10;\n\t} else {\n\t\trx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;\n\t}\n\n\treturn rx_buf_size;\n}\n\n/*********************************************************************\n *\n * Initialize the hardware\n *\n **********************************************************************/\nstatic int\nigb_hardware_init(struct e1000_hw *hw)\n{\n\tuint32_t rx_buf_size;\n\tint diag;\n\n\t/* Let the firmware know the OS is in control */\n\tigb_hw_control_acquire(hw);\n\n\t/*\n\t * These parameters control the automatic generation (Tx) and\n\t * response (Rx) to Ethernet PAUSE frames.\n\t * - High water mark should allow for at least two standard size (1518)\n\t * frames to be received after sending an XOFF.\n\t * - Low water mark works best when it is very near the high water mark.\n\t * This allows the receiver to restart by sending XON when it has\n\t * drained a bit. Here we use an arbitrary value of 1500 which will\n\t * restart after one full frame is pulled from the buffer. There\n\t * could be several smaller frames in the buffer and if so they will\n\t * not trigger the XON until their total number reduces the buffer\n\t * by 1500.\n\t * - The pause time is fairly large at 1000 x 512ns = 512 usec.\n\t */\n\trx_buf_size = igb_get_rx_buffer_size(hw);\n\n\thw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);\n\thw->fc.low_water = hw->fc.high_water - 1500;\n\thw->fc.pause_time = IGB_FC_PAUSE_TIME;\n\thw->fc.send_xon = 1;\n\n\t/* Set Flow control, use the tunable location if sane */\n\tif ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))\n\t\thw->fc.requested_mode = igb_fc_setting;\n\telse\n\t\thw->fc.requested_mode = e1000_fc_none;\n\n\t/* Issue a global reset */\n\tigb_pf_reset_hw(hw);\n\tE1000_WRITE_REG(hw, E1000_WUC, 0);\n\n\tdiag = e1000_init_hw(hw);\n\tif (diag < 0)\n\t\treturn (diag);\n\n\tE1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN << 16 | ETHER_TYPE_VLAN);\n\te1000_get_phy_info(hw);\n\te1000_check_for_link(hw);\n\n\treturn (0);\n}\n\n/* This function is based on igb_update_stats_counters() in igb/if_igb.c */\nstatic void\neth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_hw_stats *stats =\n\t\t\tE1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\tint pause_frames;\n\n\tif(hw->phy.media_type == e1000_media_type_copper ||\n\t (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {\n\t\tstats->symerrs +=\n\t\t E1000_READ_REG(hw,E1000_SYMERRS);\n\t\tstats->sec += E1000_READ_REG(hw, E1000_SEC);\n\t}\n\n\tstats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);\n\tstats->mpc += E1000_READ_REG(hw, E1000_MPC);\n\tstats->scc += E1000_READ_REG(hw, E1000_SCC);\n\tstats->ecol += E1000_READ_REG(hw, E1000_ECOL);\n\n\tstats->mcc += E1000_READ_REG(hw, E1000_MCC);\n\tstats->latecol += E1000_READ_REG(hw, E1000_LATECOL);\n\tstats->colc += E1000_READ_REG(hw, E1000_COLC);\n\tstats->dc += E1000_READ_REG(hw, E1000_DC);\n\tstats->rlec += E1000_READ_REG(hw, E1000_RLEC);\n\tstats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);\n\tstats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);\n\t/*\n\t** For watchdog management we need to know if we have been\n\t** paused during the last interval, so capture that here.\n\t*/\n\tpause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);\n\tstats->xoffrxc += pause_frames;\n\tstats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);\n\tstats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);\n\tstats->prc64 += E1000_READ_REG(hw, E1000_PRC64);\n\tstats->prc127 += E1000_READ_REG(hw, E1000_PRC127);\n\tstats->prc255 += E1000_READ_REG(hw, E1000_PRC255);\n\tstats->prc511 += E1000_READ_REG(hw, E1000_PRC511);\n\tstats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);\n\tstats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);\n\tstats->gprc += E1000_READ_REG(hw, E1000_GPRC);\n\tstats->bprc += E1000_READ_REG(hw, E1000_BPRC);\n\tstats->mprc += E1000_READ_REG(hw, E1000_MPRC);\n\tstats->gptc += E1000_READ_REG(hw, E1000_GPTC);\n\n\t/* For the 64-bit byte counters the low dword must be read first. */\n\t/* Both registers clear on the read of the high dword */\n\n\tstats->gorc += E1000_READ_REG(hw, E1000_GORCL);\n\tstats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);\n\tstats->gotc += E1000_READ_REG(hw, E1000_GOTCL);\n\tstats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);\n\n\tstats->rnbc += E1000_READ_REG(hw, E1000_RNBC);\n\tstats->ruc += E1000_READ_REG(hw, E1000_RUC);\n\tstats->rfc += E1000_READ_REG(hw, E1000_RFC);\n\tstats->roc += E1000_READ_REG(hw, E1000_ROC);\n\tstats->rjc += E1000_READ_REG(hw, E1000_RJC);\n\n\tstats->tor += E1000_READ_REG(hw, E1000_TORH);\n\tstats->tot += E1000_READ_REG(hw, E1000_TOTH);\n\n\tstats->tpr += E1000_READ_REG(hw, E1000_TPR);\n\tstats->tpt += E1000_READ_REG(hw, E1000_TPT);\n\tstats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);\n\tstats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);\n\tstats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);\n\tstats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);\n\tstats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);\n\tstats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);\n\tstats->mptc += E1000_READ_REG(hw, E1000_MPTC);\n\tstats->bptc += E1000_READ_REG(hw, E1000_BPTC);\n\n\t/* Interrupt Counts */\n\n\tstats->iac += E1000_READ_REG(hw, E1000_IAC);\n\tstats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);\n\tstats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);\n\tstats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);\n\tstats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);\n\tstats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);\n\tstats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);\n\tstats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);\n\tstats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);\n\n\t/* Host to Card Statistics */\n\n\tstats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);\n\tstats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);\n\tstats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);\n\tstats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);\n\tstats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);\n\tstats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);\n\tstats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);\n\tstats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);\n\tstats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);\n\tstats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);\n\tstats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);\n\tstats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);\n\tstats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);\n\tstats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);\n\n\tstats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);\n\tstats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);\n\tstats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);\n\tstats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);\n\tstats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);\n\tstats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);\n\n\tif (rte_stats == NULL)\n\t\treturn;\n\n\t/* Rx Errors */\n\trte_stats->ibadcrc = stats->crcerrs;\n\trte_stats->ibadlen = stats->rlec + stats->ruc + stats->roc;\n\trte_stats->imissed = stats->mpc;\n\trte_stats->ierrors = rte_stats->ibadcrc +\n\t rte_stats->ibadlen +\n\t rte_stats->imissed +\n\t stats->rxerrc + stats->algnerrc + stats->cexterr;\n\n\t/* Tx Errors */\n\trte_stats->oerrors = stats->ecol + stats->latecol;\n\n\t/* XON/XOFF pause frames */\n\trte_stats->tx_pause_xon = stats->xontxc;\n\trte_stats->rx_pause_xon = stats->xonrxc;\n\trte_stats->tx_pause_xoff = stats->xofftxc;\n\trte_stats->rx_pause_xoff = stats->xoffrxc;\n\n\trte_stats->ipackets = stats->gprc;\n\trte_stats->opackets = stats->gptc;\n\trte_stats->ibytes = stats->gorc;\n\trte_stats->obytes = stats->gotc;\n}\n\nstatic void\neth_igb_stats_reset(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw_stats *hw_stats =\n\t\t\tE1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\n\t/* HW registers are cleared on read */\n\teth_igb_stats_get(dev, NULL);\n\n\t/* Reset software totals */\n\tmemset(hw_stats, 0, sizeof(*hw_stats));\n}\n\nstatic void\neth_igbvf_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)\n\t\t\t E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\n\t/* Good Rx packets, include VF loopback */\n\tUPDATE_VF_STAT(E1000_VFGPRC,\n\t hw_stats->last_gprc, hw_stats->gprc);\n\n\t/* Good Rx octets, include VF loopback */\n\tUPDATE_VF_STAT(E1000_VFGORC,\n\t hw_stats->last_gorc, hw_stats->gorc);\n\n\t/* Good Tx packets, include VF loopback */\n\tUPDATE_VF_STAT(E1000_VFGPTC,\n\t hw_stats->last_gptc, hw_stats->gptc);\n\n\t/* Good Tx octets, include VF loopback */\n\tUPDATE_VF_STAT(E1000_VFGOTC,\n\t hw_stats->last_gotc, hw_stats->gotc);\n\n\t/* Rx Multicst packets */\n\tUPDATE_VF_STAT(E1000_VFMPRC,\n\t hw_stats->last_mprc, hw_stats->mprc);\n\n\t/* Good Rx loopback packets */\n\tUPDATE_VF_STAT(E1000_VFGPRLBC,\n\t hw_stats->last_gprlbc, hw_stats->gprlbc);\n\n\t/* Good Rx loopback octets */\n\tUPDATE_VF_STAT(E1000_VFGORLBC,\n\t hw_stats->last_gorlbc, hw_stats->gorlbc);\n\n\t/* Good Tx loopback packets */\n\tUPDATE_VF_STAT(E1000_VFGPTLBC,\n\t hw_stats->last_gptlbc, hw_stats->gptlbc);\n\n\t/* Good Tx loopback octets */\n\tUPDATE_VF_STAT(E1000_VFGOTLBC,\n\t hw_stats->last_gotlbc, hw_stats->gotlbc);\n\n\tif (rte_stats == NULL)\n\t\treturn;\n\n\trte_stats->ipackets = hw_stats->gprc;\n\trte_stats->ibytes = hw_stats->gorc;\n\trte_stats->opackets = hw_stats->gptc;\n\trte_stats->obytes = hw_stats->gotc;\n\trte_stats->imcasts = hw_stats->mprc;\n\trte_stats->ilbpackets = hw_stats->gprlbc;\n\trte_stats->ilbbytes = hw_stats->gorlbc;\n\trte_stats->olbpackets = hw_stats->gptlbc;\n\trte_stats->olbbytes = hw_stats->gotlbc;\n\n}\n\nstatic void\neth_igbvf_stats_reset(struct rte_eth_dev *dev)\n{\n\tstruct e1000_vf_stats *hw_stats = (struct e1000_vf_stats*)\n\t\t\tE1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\n\t/* Sync HW register to the last stats */\n\teth_igbvf_stats_get(dev, NULL);\n\n\t/* reset HW current stats*/\n\tmemset(&hw_stats->gprc, 0, sizeof(*hw_stats) -\n\t offsetof(struct e1000_vf_stats, gprc));\n\n}\n\nstatic void\neth_igb_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tdev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */\n\tdev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */\n\tdev_info->max_mac_addrs = hw->mac.rar_entry_count;\n\tdev_info->rx_offload_capa =\n\t\tDEV_RX_OFFLOAD_VLAN_STRIP |\n\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n\t\tDEV_RX_OFFLOAD_TCP_CKSUM;\n\tdev_info->tx_offload_capa =\n\t\tDEV_TX_OFFLOAD_VLAN_INSERT |\n\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n\t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n\t\tDEV_TX_OFFLOAD_SCTP_CKSUM;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82575:\n\t\tdev_info->max_rx_queues = 4;\n\t\tdev_info->max_tx_queues = 4;\n\t\tdev_info->max_vmdq_pools = 0;\n\t\tbreak;\n\n\tcase e1000_82576:\n\t\tdev_info->max_rx_queues = 16;\n\t\tdev_info->max_tx_queues = 16;\n\t\tdev_info->max_vmdq_pools = ETH_8_POOLS;\n\t\tdev_info->vmdq_queue_num = 16;\n\t\tbreak;\n\n\tcase e1000_82580:\n\t\tdev_info->max_rx_queues = 8;\n\t\tdev_info->max_tx_queues = 8;\n\t\tdev_info->max_vmdq_pools = ETH_8_POOLS;\n\t\tdev_info->vmdq_queue_num = 8;\n\t\tbreak;\n\n\tcase e1000_i350:\n\t\tdev_info->max_rx_queues = 8;\n\t\tdev_info->max_tx_queues = 8;\n\t\tdev_info->max_vmdq_pools = ETH_8_POOLS;\n\t\tdev_info->vmdq_queue_num = 8;\n\t\tbreak;\n\n\tcase e1000_i354:\n\t\tdev_info->max_rx_queues = 8;\n\t\tdev_info->max_tx_queues = 8;\n\t\tbreak;\n\n\tcase e1000_i210:\n\t\tdev_info->max_rx_queues = 4;\n\t\tdev_info->max_tx_queues = 4;\n\t\tdev_info->max_vmdq_pools = 0;\n\t\tbreak;\n\n\tcase e1000_i211:\n\t\tdev_info->max_rx_queues = 2;\n\t\tdev_info->max_tx_queues = 2;\n\t\tdev_info->max_vmdq_pools = 0;\n\t\tbreak;\n\n\tdefault:\n\t\t/* Should not happen */\n\t\tbreak;\n\t}\n\tdev_info->hash_key_size = IGB_HKEY_MAX_INDEX * sizeof(uint32_t);\n\tdev_info->reta_size = ETH_RSS_RETA_SIZE_128;\n\tdev_info->flow_type_rss_offloads = IGB_RSS_OFFLOAD_ALL;\n\n\tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n\t\t.rx_thresh = {\n\t\t\t.pthresh = IGB_DEFAULT_RX_PTHRESH,\n\t\t\t.hthresh = IGB_DEFAULT_RX_HTHRESH,\n\t\t\t.wthresh = IGB_DEFAULT_RX_WTHRESH,\n\t\t},\n\t\t.rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,\n\t\t.rx_drop_en = 0,\n\t};\n\n\tdev_info->default_txconf = (struct rte_eth_txconf) {\n\t\t.tx_thresh = {\n\t\t\t.pthresh = IGB_DEFAULT_TX_PTHRESH,\n\t\t\t.hthresh = IGB_DEFAULT_TX_HTHRESH,\n\t\t\t.wthresh = IGB_DEFAULT_TX_WTHRESH,\n\t\t},\n\t\t.txq_flags = 0,\n\t};\n}\n\nstatic void\neth_igbvf_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tdev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */\n\tdev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */\n\tdev_info->max_mac_addrs = hw->mac.rar_entry_count;\n\tdev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |\n\t\t\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n\t\t\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n\t\t\t\tDEV_RX_OFFLOAD_TCP_CKSUM;\n\tdev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |\n\t\t\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n\t\t\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n\t\t\t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n\t\t\t\tDEV_TX_OFFLOAD_SCTP_CKSUM;\n\tswitch (hw->mac.type) {\n\tcase e1000_vfadapt:\n\t\tdev_info->max_rx_queues = 2;\n\t\tdev_info->max_tx_queues = 2;\n\t\tbreak;\n\tcase e1000_vfadapt_i350:\n\t\tdev_info->max_rx_queues = 1;\n\t\tdev_info->max_tx_queues = 1;\n\t\tbreak;\n\tdefault:\n\t\t/* Should not happen */\n\t\tbreak;\n\t}\n\n\tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n\t\t.rx_thresh = {\n\t\t\t.pthresh = IGB_DEFAULT_RX_PTHRESH,\n\t\t\t.hthresh = IGB_DEFAULT_RX_HTHRESH,\n\t\t\t.wthresh = IGB_DEFAULT_RX_WTHRESH,\n\t\t},\n\t\t.rx_free_thresh = IGB_DEFAULT_RX_FREE_THRESH,\n\t\t.rx_drop_en = 0,\n\t};\n\n\tdev_info->default_txconf = (struct rte_eth_txconf) {\n\t\t.tx_thresh = {\n\t\t\t.pthresh = IGB_DEFAULT_TX_PTHRESH,\n\t\t\t.hthresh = IGB_DEFAULT_TX_HTHRESH,\n\t\t\t.wthresh = IGB_DEFAULT_TX_WTHRESH,\n\t\t},\n\t\t.txq_flags = 0,\n\t};\n}\n\n/* return 0 means link status changed, -1 means not changed */\nstatic int\neth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct rte_eth_link link, old;\n\tint link_check, count;\n\n\tlink_check = 0;\n\thw->mac.get_link_status = 1;\n\n\t/* possible wait-to-complete in up to 9 seconds */\n\tfor (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {\n\t\t/* Read the real link status */\n\t\tswitch (hw->phy.media_type) {\n\t\tcase e1000_media_type_copper:\n\t\t\t/* Do the work to read phy */\n\t\t\te1000_check_for_link(hw);\n\t\t\tlink_check = !hw->mac.get_link_status;\n\t\t\tbreak;\n\n\t\tcase e1000_media_type_fiber:\n\t\t\te1000_check_for_link(hw);\n\t\t\tlink_check = (E1000_READ_REG(hw, E1000_STATUS) &\n\t\t\t\t E1000_STATUS_LU);\n\t\t\tbreak;\n\n\t\tcase e1000_media_type_internal_serdes:\n\t\t\te1000_check_for_link(hw);\n\t\t\tlink_check = hw->mac.serdes_has_link;\n\t\t\tbreak;\n\n\t\t/* VF device is type_unknown */\n\t\tcase e1000_media_type_unknown:\n\t\t\teth_igbvf_link_update(hw);\n\t\t\tlink_check = !hw->mac.get_link_status;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\tif (link_check || wait_to_complete == 0)\n\t\t\tbreak;\n\t\trte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);\n\t}\n\tmemset(&link, 0, sizeof(link));\n\trte_igb_dev_atomic_read_link_status(dev, &link);\n\told = link;\n\n\t/* Now we check if a transition has happened */\n\tif (link_check) {\n\t\thw->mac.ops.get_link_up_info(hw, &link.link_speed,\n\t\t\t\t\t &link.link_duplex);\n\t\tlink.link_status = 1;\n\t} else if (!link_check) {\n\t\tlink.link_speed = 0;\n\t\tlink.link_duplex = 0;\n\t\tlink.link_status = 0;\n\t}\n\trte_igb_dev_atomic_write_link_status(dev, &link);\n\n\t/* not changed */\n\tif (old.link_status == link.link_status)\n\t\treturn -1;\n\n\t/* changed */\n\treturn 0;\n}\n\n/*\n * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.\n * For ASF and Pass Through versions of f/w this means\n * that the driver is loaded.\n */\nstatic void\nigb_hw_control_acquire(struct e1000_hw *hw)\n{\n\tuint32_t ctrl_ext;\n\n\t/* Let firmware know the driver has taken over */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);\n}\n\n/*\n * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.\n * For ASF and Pass Through versions of f/w this means that the\n * driver is no longer loaded.\n */\nstatic void\nigb_hw_control_release(struct e1000_hw *hw)\n{\n\tuint32_t ctrl_ext;\n\n\t/* Let firmware taken over control of h/w */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT,\n\t\t\tctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);\n}\n\n/*\n * Bit of a misnomer, what this really means is\n * to enable OS management of the system... aka\n * to disable special hardware management features.\n */\nstatic void\nigb_init_manageability(struct e1000_hw *hw)\n{\n\tif (e1000_enable_mng_pass_thru(hw)) {\n\t\tuint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);\n\t\tuint32_t manc = E1000_READ_REG(hw, E1000_MANC);\n\n\t\t/* disable hardware interception of ARP */\n\t\tmanc &= ~(E1000_MANC_ARP_EN);\n\n\t\t/* enable receiving management packets to the host */\n\t\tmanc |= E1000_MANC_EN_MNG2HOST;\n\t\tmanc2h |= 1 << 5; /* Mng Port 623 */\n\t\tmanc2h |= 1 << 6; /* Mng Port 664 */\n\t\tE1000_WRITE_REG(hw, E1000_MANC2H, manc2h);\n\t\tE1000_WRITE_REG(hw, E1000_MANC, manc);\n\t}\n}\n\nstatic void\nigb_release_manageability(struct e1000_hw *hw)\n{\n\tif (e1000_enable_mng_pass_thru(hw)) {\n\t\tuint32_t manc = E1000_READ_REG(hw, E1000_MANC);\n\n\t\tmanc |= E1000_MANC_ARP_EN;\n\t\tmanc &= ~E1000_MANC_EN_MNG2HOST;\n\n\t\tE1000_WRITE_REG(hw, E1000_MANC, manc);\n\t}\n}\n\nstatic void\neth_igb_promiscuous_enable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t rctl;\n\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\trctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n}\n\nstatic void\neth_igb_promiscuous_disable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t rctl;\n\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\trctl &= (~E1000_RCTL_UPE);\n\tif (dev->data->all_multicast == 1)\n\t\trctl |= E1000_RCTL_MPE;\n\telse\n\t\trctl &= (~E1000_RCTL_MPE);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n}\n\nstatic void\neth_igb_allmulticast_enable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t rctl;\n\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\trctl |= E1000_RCTL_MPE;\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n}\n\nstatic void\neth_igb_allmulticast_disable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t rctl;\n\n\tif (dev->data->promiscuous == 1)\n\t\treturn; /* must remain in all_multicast mode */\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\trctl &= (~E1000_RCTL_MPE);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n}\n\nstatic int\neth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_vfta * shadow_vfta =\n\t\tE1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);\n\tuint32_t vfta;\n\tuint32_t vid_idx;\n\tuint32_t vid_bit;\n\n\tvid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &\n\t\t\t E1000_VFTA_ENTRY_MASK);\n\tvid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));\n\tvfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);\n\tif (on)\n\t\tvfta |= vid_bit;\n\telse\n\t\tvfta &= ~vid_bit;\n\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);\n\n\t/* update local VFTA copy */\n\tshadow_vfta->vfta[vid_idx] = vfta;\n\n\treturn 0;\n}\n\nstatic void\neth_igb_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t reg = ETHER_TYPE_VLAN ;\n\n\treg |= (tpid << 16);\n\tE1000_WRITE_REG(hw, E1000_VET, reg);\n}\n\nstatic void\nigb_vlan_hw_filter_disable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t reg;\n\n\t/* Filter Table Disable */\n\treg = E1000_READ_REG(hw, E1000_RCTL);\n\treg &= ~E1000_RCTL_CFIEN;\n\treg &= ~E1000_RCTL_VFE;\n\tE1000_WRITE_REG(hw, E1000_RCTL, reg);\n}\n\nstatic void\nigb_vlan_hw_filter_enable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_vfta * shadow_vfta =\n\t\tE1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);\n\tuint32_t reg;\n\tint i;\n\n\t/* Filter Table Enable, CFI not used for packet acceptance */\n\treg = E1000_READ_REG(hw, E1000_RCTL);\n\treg &= ~E1000_RCTL_CFIEN;\n\treg |= E1000_RCTL_VFE;\n\tE1000_WRITE_REG(hw, E1000_RCTL, reg);\n\n\t/* restore VFTA table */\n\tfor (i = 0; i < IGB_VFTA_SIZE; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);\n}\n\nstatic void\nigb_vlan_hw_strip_disable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t reg;\n\n\t/* VLAN Mode Disable */\n\treg = E1000_READ_REG(hw, E1000_CTRL);\n\treg &= ~E1000_CTRL_VME;\n\tE1000_WRITE_REG(hw, E1000_CTRL, reg);\n}\n\nstatic void\nigb_vlan_hw_strip_enable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t reg;\n\n\t/* VLAN Mode Enable */\n\treg = E1000_READ_REG(hw, E1000_CTRL);\n\treg |= E1000_CTRL_VME;\n\tE1000_WRITE_REG(hw, E1000_CTRL, reg);\n}\n\nstatic void\nigb_vlan_hw_extend_disable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t reg;\n\n\t/* CTRL_EXT: Extended VLAN */\n\treg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\treg &= ~E1000_CTRL_EXT_EXTEND_VLAN;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);\n\n\t/* Update maximum packet length */\n\tif (dev->data->dev_conf.rxmode.jumbo_frame == 1)\n\t\tE1000_WRITE_REG(hw, E1000_RLPML,\n\t\t\tdev->data->dev_conf.rxmode.max_rx_pkt_len +\n\t\t\t\t\t\tVLAN_TAG_SIZE);\n}\n\nstatic void\nigb_vlan_hw_extend_enable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t reg;\n\n\t/* CTRL_EXT: Extended VLAN */\n\treg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\treg |= E1000_CTRL_EXT_EXTEND_VLAN;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);\n\n\t/* Update maximum packet length */\n\tif (dev->data->dev_conf.rxmode.jumbo_frame == 1)\n\t\tE1000_WRITE_REG(hw, E1000_RLPML,\n\t\t\tdev->data->dev_conf.rxmode.max_rx_pkt_len +\n\t\t\t\t\t\t2 * VLAN_TAG_SIZE);\n}\n\nstatic void\neth_igb_vlan_offload_set(struct rte_eth_dev *dev, int mask)\n{\n\tif(mask & ETH_VLAN_STRIP_MASK){\n\t\tif (dev->data->dev_conf.rxmode.hw_vlan_strip)\n\t\t\tigb_vlan_hw_strip_enable(dev);\n\t\telse\n\t\t\tigb_vlan_hw_strip_disable(dev);\n\t}\n\n\tif(mask & ETH_VLAN_FILTER_MASK){\n\t\tif (dev->data->dev_conf.rxmode.hw_vlan_filter)\n\t\t\tigb_vlan_hw_filter_enable(dev);\n\t\telse\n\t\t\tigb_vlan_hw_filter_disable(dev);\n\t}\n\n\tif(mask & ETH_VLAN_EXTEND_MASK){\n\t\tif (dev->data->dev_conf.rxmode.hw_vlan_extend)\n\t\t\tigb_vlan_hw_extend_enable(dev);\n\t\telse\n\t\t\tigb_vlan_hw_extend_disable(dev);\n\t}\n}\n\n\n/**\n * It enables the interrupt mask and then enable the interrupt.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\neth_igb_lsc_interrupt_setup(struct rte_eth_dev *dev)\n{\n\tstruct e1000_interrupt *intr =\n\t\tE1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\tintr->mask |= E1000_ICR_LSC;\n\n\treturn 0;\n}\n\n#ifdef RTE_NEXT_ABI\n/* It clears the interrupt causes and enables the interrupt.\n * It will be called once only during nic initialized.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int eth_igb_rxq_interrupt_setup(struct rte_eth_dev *dev)\n{\n\tuint32_t mask, regval;\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct rte_eth_dev_info dev_info;\n\n\tmemset(&dev_info, 0, sizeof(dev_info));\n\teth_igb_infos_get(dev, &dev_info);\n\n\tmask = 0xFFFFFFFF >> (32 - dev_info.max_rx_queues);\n\tregval = E1000_READ_REG(hw, E1000_EIMS);\n\tE1000_WRITE_REG(hw, E1000_EIMS, regval | mask);\n\n\treturn 0;\n}\n#endif\n\n/*\n * It reads ICR and gets interrupt causes, check it and set a bit flag\n * to update link status.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\neth_igb_interrupt_get_status(struct rte_eth_dev *dev)\n{\n\tuint32_t icr;\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_interrupt *intr =\n\t\tE1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\tigb_intr_disable(hw);\n\n\t/* read-on-clear nic registers here */\n\ticr = E1000_READ_REG(hw, E1000_ICR);\n\n\tintr->flags = 0;\n\tif (icr & E1000_ICR_LSC) {\n\t\tintr->flags |= E1000_FLAG_NEED_LINK_UPDATE;\n\t}\n\n\tif (icr & E1000_ICR_VMMB)\n\t\tintr->flags |= E1000_FLAG_MAILBOX;\n\n\treturn 0;\n}\n\n/*\n * It executes link_update after knowing an interrupt is prsent.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\neth_igb_interrupt_action(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_interrupt *intr =\n\t\tE1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\tuint32_t tctl, rctl;\n\tstruct rte_eth_link link;\n\tint ret;\n\n\tif (intr->flags & E1000_FLAG_MAILBOX) {\n\t\tigb_pf_mbx_process(dev);\n\t\tintr->flags &= ~E1000_FLAG_MAILBOX;\n\t}\n\n\tigb_intr_enable(dev);\n\trte_intr_enable(&(dev->pci_dev->intr_handle));\n\n\tif (intr->flags & E1000_FLAG_NEED_LINK_UPDATE) {\n\t\tintr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;\n\n\t\t/* set get_link_status to check register later */\n\t\thw->mac.get_link_status = 1;\n\t\tret = eth_igb_link_update(dev, 0);\n\n\t\t/* check if link has changed */\n\t\tif (ret < 0)\n\t\t\treturn 0;\n\n\t\tmemset(&link, 0, sizeof(link));\n\t\trte_igb_dev_atomic_read_link_status(dev, &link);\n\t\tif (link.link_status) {\n\t\t\tPMD_INIT_LOG(INFO,\n\t\t\t\t \" Port %d: Link Up - speed %u Mbps - %s\",\n\t\t\t\t dev->data->port_id,\n\t\t\t\t (unsigned)link.link_speed,\n\t\t\t\t link.link_duplex == ETH_LINK_FULL_DUPLEX ?\n\t\t\t\t \"full-duplex\" : \"half-duplex\");\n\t\t} else {\n\t\t\tPMD_INIT_LOG(INFO, \" Port %d: Link Down\",\n\t\t\t\t dev->data->port_id);\n\t\t}\n\n\t\tPMD_INIT_LOG(DEBUG, \"PCI Address: %04d:%02d:%02d:%d\",\n\t\t\t dev->pci_dev->addr.domain,\n\t\t\t dev->pci_dev->addr.bus,\n\t\t\t dev->pci_dev->addr.devid,\n\t\t\t dev->pci_dev->addr.function);\n\t\ttctl = E1000_READ_REG(hw, E1000_TCTL);\n\t\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\t\tif (link.link_status) {\n\t\t\t/* enable Tx/Rx */\n\t\t\ttctl |= E1000_TCTL_EN;\n\t\t\trctl |= E1000_RCTL_EN;\n\t\t} else {\n\t\t\t/* disable Tx/Rx */\n\t\t\ttctl &= ~E1000_TCTL_EN;\n\t\t\trctl &= ~E1000_RCTL_EN;\n\t\t}\n\t\tE1000_WRITE_REG(hw, E1000_TCTL, tctl);\n\t\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\t_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);\n\t}\n\n\treturn 0;\n}\n\n/**\n * Interrupt handler which shall be registered at first.\n *\n * @param handle\n * Pointer to interrupt handle.\n * @param param\n * The address of parameter (struct rte_eth_dev *) regsitered before.\n *\n * @return\n * void\n */\nstatic void\neth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,\n\t\t\t\t\t\t\tvoid *param)\n{\n\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n\n\teth_igb_interrupt_get_status(dev);\n\teth_igb_interrupt_action(dev);\n}\n\nstatic int\neth_igb_led_on(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\treturn (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);\n}\n\nstatic int\neth_igb_led_off(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\treturn (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);\n}\n\nstatic int\neth_igb_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n{\n\tstruct e1000_hw *hw;\n\tuint32_t ctrl;\n\tint tx_pause;\n\tint rx_pause;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tfc_conf->pause_time = hw->fc.pause_time;\n\tfc_conf->high_water = hw->fc.high_water;\n\tfc_conf->low_water = hw->fc.low_water;\n\tfc_conf->send_xon = hw->fc.send_xon;\n\tfc_conf->autoneg = hw->mac.autoneg;\n\n\t/*\n\t * Return rx_pause and tx_pause status according to actual setting of\n\t * the TFCE and RFCE bits in the CTRL register.\n\t */\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tif (ctrl & E1000_CTRL_TFCE)\n\t\ttx_pause = 1;\n\telse\n\t\ttx_pause = 0;\n\n\tif (ctrl & E1000_CTRL_RFCE)\n\t\trx_pause = 1;\n\telse\n\t\trx_pause = 0;\n\n\tif (rx_pause && tx_pause)\n\t\tfc_conf->mode = RTE_FC_FULL;\n\telse if (rx_pause)\n\t\tfc_conf->mode = RTE_FC_RX_PAUSE;\n\telse if (tx_pause)\n\t\tfc_conf->mode = RTE_FC_TX_PAUSE;\n\telse\n\t\tfc_conf->mode = RTE_FC_NONE;\n\n\treturn 0;\n}\n\nstatic int\neth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n{\n\tstruct e1000_hw *hw;\n\tint err;\n\tenum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {\n\t\te1000_fc_none,\n\t\te1000_fc_rx_pause,\n\t\te1000_fc_tx_pause,\n\t\te1000_fc_full\n\t};\n\tuint32_t rx_buf_size;\n\tuint32_t max_high_water;\n\tuint32_t rctl;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tif (fc_conf->autoneg != hw->mac.autoneg)\n\t\treturn -ENOTSUP;\n\trx_buf_size = igb_get_rx_buffer_size(hw);\n\tPMD_INIT_LOG(DEBUG, \"Rx packet buffer size = 0x%x\", rx_buf_size);\n\n\t/* At least reserve one Ethernet frame for watermark */\n\tmax_high_water = rx_buf_size - ETHER_MAX_LEN;\n\tif ((fc_conf->high_water > max_high_water) ||\n\t (fc_conf->high_water < fc_conf->low_water)) {\n\t\tPMD_INIT_LOG(ERR, \"e1000 incorrect high/low water value\");\n\t\tPMD_INIT_LOG(ERR, \"high water must <= 0x%x\", max_high_water);\n\t\treturn (-EINVAL);\n\t}\n\n\thw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];\n\thw->fc.pause_time = fc_conf->pause_time;\n\thw->fc.high_water = fc_conf->high_water;\n\thw->fc.low_water = fc_conf->low_water;\n\thw->fc.send_xon\t = fc_conf->send_xon;\n\n\terr = e1000_setup_link_generic(hw);\n\tif (err == E1000_SUCCESS) {\n\n\t\t/* check if we want to forward MAC frames - driver doesn't have native\n\t\t * capability to do that, so we'll write the registers ourselves */\n\n\t\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\n\t\t/* set or clear MFLCN.PMCF bit depending on configuration */\n\t\tif (fc_conf->mac_ctrl_frame_fwd != 0)\n\t\t\trctl |= E1000_RCTL_PMCF;\n\t\telse\n\t\t\trctl &= ~E1000_RCTL_PMCF;\n\n\t\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\t\tE1000_WRITE_FLUSH(hw);\n\n\t\treturn 0;\n\t}\n\n\tPMD_INIT_LOG(ERR, \"e1000_setup_link_generic = 0x%x\", err);\n\treturn (-EIO);\n}\n\n#define E1000_RAH_POOLSEL_SHIFT (18)\nstatic void\neth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,\n\t uint32_t index, __rte_unused uint32_t pool)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t rah;\n\n\te1000_rar_set(hw, mac_addr->addr_bytes, index);\n\trah = E1000_READ_REG(hw, E1000_RAH(index));\n\trah |= (0x1 << (E1000_RAH_POOLSEL_SHIFT + pool));\n\tE1000_WRITE_REG(hw, E1000_RAH(index), rah);\n}\n\nstatic void\neth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)\n{\n\tuint8_t addr[ETHER_ADDR_LEN];\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tmemset(addr, 0, sizeof(addr));\n\n\te1000_rar_set(hw, addr, index);\n}\n\nstatic void\neth_igb_default_mac_addr_set(struct rte_eth_dev *dev,\n\t\t\t\tstruct ether_addr *addr)\n{\n\teth_igb_rar_clear(dev, 0);\n\n\teth_igb_rar_set(dev, (void *)addr, 0, 0);\n}\n/*\n * Virtual Function operations\n */\nstatic void\nigbvf_intr_disable(struct e1000_hw *hw)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* Clear interrupt mask to stop from interrupts being generated */\n\tE1000_WRITE_REG(hw, E1000_EIMC, 0xFFFF);\n\n\tE1000_WRITE_FLUSH(hw);\n}\n\nstatic void\nigbvf_stop_adapter(struct rte_eth_dev *dev)\n{\n\tu32 reg_val;\n\tu16 i;\n\tstruct rte_eth_dev_info dev_info;\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tmemset(&dev_info, 0, sizeof(dev_info));\n\teth_igbvf_infos_get(dev, &dev_info);\n\n\t/* Clear interrupt mask to stop from interrupts being generated */\n\tigbvf_intr_disable(hw);\n\n\t/* Clear any pending interrupts, flush previous writes */\n\tE1000_READ_REG(hw, E1000_EICR);\n\n\t/* Disable the transmit unit. Each queue must be disabled. */\n\tfor (i = 0; i < dev_info.max_tx_queues; i++)\n\t\tE1000_WRITE_REG(hw, E1000_TXDCTL(i), E1000_TXDCTL_SWFLSH);\n\n\t/* Disable the receive unit by stopping each queue */\n\tfor (i = 0; i < dev_info.max_rx_queues; i++) {\n\t\treg_val = E1000_READ_REG(hw, E1000_RXDCTL(i));\n\t\treg_val &= ~E1000_RXDCTL_QUEUE_ENABLE;\n\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(i), reg_val);\n\t\twhile (E1000_READ_REG(hw, E1000_RXDCTL(i)) & E1000_RXDCTL_QUEUE_ENABLE)\n\t\t\t;\n\t}\n\n\t/* flush all queues disables */\n\tE1000_WRITE_FLUSH(hw);\n\tmsec_delay(2);\n}\n\nstatic int eth_igbvf_link_update(struct e1000_hw *hw)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tint ret_val = E1000_SUCCESS;\n\n\tPMD_INIT_LOG(DEBUG, \"e1000_check_for_link_vf\");\n\n\t/*\n\t * We only want to run this if there has been a rst asserted.\n\t * in this case that could mean a link change, device reset,\n\t * or a virtual function reset\n\t */\n\n\t/* If we were hit with a reset or timeout drop the link */\n\tif (!e1000_check_for_rst(hw, 0) || !mbx->timeout)\n\t\tmac->get_link_status = TRUE;\n\n\tif (!mac->get_link_status)\n\t\tgoto out;\n\n\t/* if link status is down no point in checking to see if pf is up */\n\tif (!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU))\n\t\tgoto out;\n\n\t/* if we passed all the tests above then the link is up and we no\n\t * longer need to check for link */\n\tmac->get_link_status = FALSE;\n\nout:\n\treturn ret_val;\n}\n\n\nstatic int\nigbvf_dev_configure(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_conf* conf = &dev->data->dev_conf;\n\n\tPMD_INIT_LOG(DEBUG, \"Configured Virtual Function port id: %d\",\n\t\t dev->data->port_id);\n\n\t/*\n\t * VF has no ability to enable/disable HW CRC\n\t * Keep the persistent behavior the same as Host PF\n\t */\n#ifndef RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC\n\tif (!conf->rxmode.hw_strip_crc) {\n\t\tPMD_INIT_LOG(NOTICE, \"VF can't disable HW CRC Strip\");\n\t\tconf->rxmode.hw_strip_crc = 1;\n\t}\n#else\n\tif (conf->rxmode.hw_strip_crc) {\n\t\tPMD_INIT_LOG(NOTICE, \"VF can't enable HW CRC Strip\");\n\t\tconf->rxmode.hw_strip_crc = 0;\n\t}\n#endif\n\n\treturn 0;\n}\n\nstatic int\nigbvf_dev_start(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_adapter *adapter =\n\t\tE1000_DEV_PRIVATE(dev->data->dev_private);\n\tint ret;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\thw->mac.ops.reset_hw(hw);\n\tadapter->stopped = 0;\n\n\t/* Set all vfta */\n\tigbvf_set_vfta_all(dev,1);\n\n\teth_igbvf_tx_init(dev);\n\n\t/* This can fail when allocating mbufs for descriptor rings */\n\tret = eth_igbvf_rx_init(dev);\n\tif (ret) {\n\t\tPMD_INIT_LOG(ERR, \"Unable to initialize RX hardware\");\n\t\tigb_dev_clear_queues(dev);\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\nstatic void\nigbvf_dev_stop(struct rte_eth_dev *dev)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\tigbvf_stop_adapter(dev);\n\n\t/*\n\t * Clear what we set, but we still keep shadow_vfta to\n\t * restore after device starts\n\t */\n\tigbvf_set_vfta_all(dev,0);\n\n\tigb_dev_clear_queues(dev);\n}\n\nstatic void\nigbvf_dev_close(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_adapter *adapter =\n\t\tE1000_DEV_PRIVATE(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\te1000_reset_hw(hw);\n\n\tigbvf_dev_stop(dev);\n\tadapter->stopped = 1;\n\tigb_dev_free_queues(dev);\n}\n\nstatic int igbvf_set_vfta(struct e1000_hw *hw, uint16_t vid, bool on)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tuint32_t msgbuf[2];\n\n\t/* After set vlan, vlan strip will also be enabled in igb driver*/\n\tmsgbuf[0] = E1000_VF_SET_VLAN;\n\tmsgbuf[1] = vid;\n\t/* Setting the 8 bit field MSG INFO to TRUE indicates \"add\" */\n\tif (on)\n\t\tmsgbuf[0] |= E1000_VF_SET_VLAN_ADD;\n\n\treturn (mbx->ops.write_posted(hw, msgbuf, 2, 0));\n}\n\nstatic void igbvf_set_vfta_all(struct rte_eth_dev *dev, bool on)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_vfta * shadow_vfta =\n\t\tE1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);\n\tint i = 0, j = 0, vfta = 0, mask = 1;\n\n\tfor (i = 0; i < IGB_VFTA_SIZE; i++){\n\t\tvfta = shadow_vfta->vfta[i];\n\t\tif(vfta){\n\t\t\tmask = 1;\n\t\t\tfor (j = 0; j < 32; j++){\n\t\t\t\tif(vfta & mask)\n\t\t\t\t\tigbvf_set_vfta(hw,\n\t\t\t\t\t\t(uint16_t)((i<<5)+j), on);\n\t\t\t\tmask<<=1;\n\t\t\t}\n\t\t}\n\t}\n\n}\n\nstatic int\nigbvf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_vfta * shadow_vfta =\n\t\tE1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);\n\tuint32_t vid_idx = 0;\n\tuint32_t vid_bit = 0;\n\tint ret = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/*vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf*/\n\tret = igbvf_set_vfta(hw, vlan_id, !!on);\n\tif(ret){\n\t\tPMD_INIT_LOG(ERR, \"Unable to set VF vlan\");\n\t\treturn ret;\n\t}\n\tvid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);\n\tvid_bit = (uint32_t) (1 << (vlan_id & 0x1F));\n\n\t/*Save what we set and retore it after device reset*/\n\tif (on)\n\t\tshadow_vfta->vfta[vid_idx] |= vid_bit;\n\telse\n\t\tshadow_vfta->vfta[vid_idx] &= ~vid_bit;\n\n\treturn 0;\n}\n\nstatic void\nigbvf_default_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/* index is not used by rar_set() */\n\thw->mac.ops.rar_set(hw, (void *)addr, 0);\n}\n\n\nstatic int\neth_igb_rss_reta_update(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\tuint16_t reta_size)\n{\n\tuint8_t i, j, mask;\n\tuint32_t reta, r;\n\tuint16_t idx, shift;\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n\t\t\t\"(%d) doesn't match the number hardware can supported \"\n\t\t\t\"(%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_128);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {\n\t\tidx = i / RTE_RETA_GROUP_SIZE;\n\t\tshift = i % RTE_RETA_GROUP_SIZE;\n\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n\t\t\t\t\t\tIGB_4_BIT_MASK);\n\t\tif (!mask)\n\t\t\tcontinue;\n\t\tif (mask == IGB_4_BIT_MASK)\n\t\t\tr = 0;\n\t\telse\n\t\t\tr = E1000_READ_REG(hw, E1000_RETA(i >> 2));\n\t\tfor (j = 0, reta = 0; j < IGB_4_BIT_WIDTH; j++) {\n\t\t\tif (mask & (0x1 << j))\n\t\t\t\treta |= reta_conf[idx].reta[shift + j] <<\n\t\t\t\t\t\t\t(CHAR_BIT * j);\n\t\t\telse\n\t\t\t\treta |= r & (IGB_8_BIT_MASK << (CHAR_BIT * j));\n\t\t}\n\t\tE1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta);\n\t}\n\n\treturn 0;\n}\n\nstatic int\neth_igb_rss_reta_query(struct rte_eth_dev *dev,\n\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t uint16_t reta_size)\n{\n\tuint8_t i, j, mask;\n\tuint32_t reta;\n\tuint16_t idx, shift;\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n\t\t\t\"(%d) doesn't match the number hardware can supported \"\n\t\t\t\"(%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_128);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < reta_size; i += IGB_4_BIT_WIDTH) {\n\t\tidx = i / RTE_RETA_GROUP_SIZE;\n\t\tshift = i % RTE_RETA_GROUP_SIZE;\n\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n\t\t\t\t\t\tIGB_4_BIT_MASK);\n\t\tif (!mask)\n\t\t\tcontinue;\n\t\treta = E1000_READ_REG(hw, E1000_RETA(i >> 2));\n\t\tfor (j = 0; j < IGB_4_BIT_WIDTH; j++) {\n\t\t\tif (mask & (0x1 << j))\n\t\t\t\treta_conf[idx].reta[shift + j] =\n\t\t\t\t\t((reta >> (CHAR_BIT * j)) &\n\t\t\t\t\t\tIGB_8_BIT_MASK);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n#define MAC_TYPE_FILTER_SUP(type) do {\\\n\tif ((type) != e1000_82580 && (type) != e1000_i350 &&\\\n\t\t(type) != e1000_82576)\\\n\t\treturn -ENOTSUP;\\\n} while (0)\n\nstatic int\neth_igb_syn_filter_set(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_syn_filter *filter,\n\t\t\tbool add)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t synqf, rfctl;\n\n\tif (filter->queue >= IGB_MAX_RX_QUEUE_NUM)\n\t\treturn -EINVAL;\n\n\tsynqf = E1000_READ_REG(hw, E1000_SYNQF(0));\n\n\tif (add) {\n\t\tif (synqf & E1000_SYN_FILTER_ENABLE)\n\t\t\treturn -EINVAL;\n\n\t\tsynqf = (uint32_t)(((filter->queue << E1000_SYN_FILTER_QUEUE_SHIFT) &\n\t\t\tE1000_SYN_FILTER_QUEUE) | E1000_SYN_FILTER_ENABLE);\n\n\t\trfctl = E1000_READ_REG(hw, E1000_RFCTL);\n\t\tif (filter->hig_pri)\n\t\t\trfctl |= E1000_RFCTL_SYNQFP;\n\t\telse\n\t\t\trfctl &= ~E1000_RFCTL_SYNQFP;\n\n\t\tE1000_WRITE_REG(hw, E1000_RFCTL, rfctl);\n\t} else {\n\t\tif (!(synqf & E1000_SYN_FILTER_ENABLE))\n\t\t\treturn -ENOENT;\n\t\tsynqf = 0;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_SYNQF(0), synqf);\n\tE1000_WRITE_FLUSH(hw);\n\treturn 0;\n}\n\nstatic int\neth_igb_syn_filter_get(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_syn_filter *filter)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t synqf, rfctl;\n\n\tsynqf = E1000_READ_REG(hw, E1000_SYNQF(0));\n\tif (synqf & E1000_SYN_FILTER_ENABLE) {\n\t\trfctl = E1000_READ_REG(hw, E1000_RFCTL);\n\t\tfilter->hig_pri = (rfctl & E1000_RFCTL_SYNQFP) ? 1 : 0;\n\t\tfilter->queue = (uint8_t)((synqf & E1000_SYN_FILTER_QUEUE) >>\n\t\t\t\tE1000_SYN_FILTER_QUEUE_SHIFT);\n\t\treturn 0;\n\t}\n\n\treturn -ENOENT;\n}\n\nstatic int\neth_igb_syn_filter_handle(struct rte_eth_dev *dev,\n\t\t\tenum rte_filter_op filter_op,\n\t\t\tvoid *arg)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint ret;\n\n\tMAC_TYPE_FILTER_SUP(hw->mac.type);\n\n\tif (filter_op == RTE_ETH_FILTER_NOP)\n\t\treturn 0;\n\n\tif (arg == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"arg shouldn't be NULL for operation %u\",\n\t\t\t filter_op);\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_ADD:\n\t\tret = eth_igb_syn_filter_set(dev,\n\t\t\t\t(struct rte_eth_syn_filter *)arg,\n\t\t\t\tTRUE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_DELETE:\n\t\tret = eth_igb_syn_filter_set(dev,\n\t\t\t\t(struct rte_eth_syn_filter *)arg,\n\t\t\t\tFALSE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_GET:\n\t\tret = eth_igb_syn_filter_get(dev,\n\t\t\t\t(struct rte_eth_syn_filter *)arg);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unsupported operation %u\\n\", filter_op);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n#define MAC_TYPE_FILTER_SUP_EXT(type) do {\\\n\tif ((type) != e1000_82580 && (type) != e1000_i350)\\\n\t\treturn -ENOSYS; \\\n} while (0)\n\n/* translate elements in struct rte_eth_ntuple_filter to struct e1000_2tuple_filter_info*/\nstatic inline int\nntuple_filter_to_2tuple(struct rte_eth_ntuple_filter *filter,\n\t\t\tstruct e1000_2tuple_filter_info *filter_info)\n{\n\tif (filter->queue >= IGB_MAX_RX_QUEUE_NUM)\n\t\treturn -EINVAL;\n\tif (filter->priority > E1000_2TUPLE_MAX_PRI)\n\t\treturn -EINVAL; /* filter index is out of range. */\n\tif (filter->tcp_flags > TCP_FLAG_ALL)\n\t\treturn -EINVAL; /* flags is invalid. */\n\n\tswitch (filter->dst_port_mask) {\n\tcase UINT16_MAX:\n\t\tfilter_info->dst_port_mask = 0;\n\t\tfilter_info->dst_port = filter->dst_port;\n\t\tbreak;\n\tcase 0:\n\t\tfilter_info->dst_port_mask = 1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid dst_port mask.\");\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter->proto_mask) {\n\tcase UINT8_MAX:\n\t\tfilter_info->proto_mask = 0;\n\t\tfilter_info->proto = filter->proto;\n\t\tbreak;\n\tcase 0:\n\t\tfilter_info->proto_mask = 1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid protocol mask.\");\n\t\treturn -EINVAL;\n\t}\n\n\tfilter_info->priority = (uint8_t)filter->priority;\n\tif (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)\n\t\tfilter_info->tcp_flags = filter->tcp_flags;\n\telse\n\t\tfilter_info->tcp_flags = 0;\n\n\treturn 0;\n}\n\nstatic inline struct e1000_2tuple_filter *\nigb_2tuple_filter_lookup(struct e1000_2tuple_filter_list *filter_list,\n\t\t\tstruct e1000_2tuple_filter_info *key)\n{\n\tstruct e1000_2tuple_filter *it;\n\n\tTAILQ_FOREACH(it, filter_list, entries) {\n\t\tif (memcmp(key, &it->filter_info,\n\t\t\tsizeof(struct e1000_2tuple_filter_info)) == 0) {\n\t\t\treturn it;\n\t\t}\n\t}\n\treturn NULL;\n}\n\n/*\n * igb_add_2tuple_filter - add a 2tuple filter\n *\n * @param\n * dev: Pointer to struct rte_eth_dev.\n * ntuple_filter: ponter to the filter that will be added.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nigb_add_2tuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *ntuple_filter)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_filter_info *filter_info =\n\t\tE1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tstruct e1000_2tuple_filter *filter;\n\tuint32_t ttqf = E1000_TTQF_DISABLE_MASK;\n\tuint32_t imir, imir_ext = E1000_IMIREXT_SIZE_BP;\n\tint i, ret;\n\n\tfilter = rte_zmalloc(\"e1000_2tuple_filter\",\n\t\t\tsizeof(struct e1000_2tuple_filter), 0);\n\tif (filter == NULL)\n\t\treturn -ENOMEM;\n\n\tret = ntuple_filter_to_2tuple(ntuple_filter,\n\t\t\t\t &filter->filter_info);\n\tif (ret < 0) {\n\t\trte_free(filter);\n\t\treturn ret;\n\t}\n\tif (igb_2tuple_filter_lookup(&filter_info->twotuple_list,\n\t\t\t\t\t &filter->filter_info) != NULL) {\n\t\tPMD_DRV_LOG(ERR, \"filter exists.\");\n\t\trte_free(filter);\n\t\treturn -EEXIST;\n\t}\n\tfilter->queue = ntuple_filter->queue;\n\n\t/*\n\t * look for an unused 2tuple filter index,\n\t * and insert the filter to list.\n\t */\n\tfor (i = 0; i < E1000_MAX_TTQF_FILTERS; i++) {\n\t\tif (!(filter_info->twotuple_mask & (1 << i))) {\n\t\t\tfilter_info->twotuple_mask |= 1 << i;\n\t\t\tfilter->index = i;\n\t\t\tTAILQ_INSERT_TAIL(&filter_info->twotuple_list,\n\t\t\t\t\t filter,\n\t\t\t\t\t entries);\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (i >= E1000_MAX_TTQF_FILTERS) {\n\t\tPMD_DRV_LOG(ERR, \"2tuple filters are full.\");\n\t\trte_free(filter);\n\t\treturn -ENOSYS;\n\t}\n\n\timir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);\n\tif (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */\n\t\timir |= E1000_IMIR_PORT_BP;\n\telse\n\t\timir &= ~E1000_IMIR_PORT_BP;\n\n\timir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;\n\n\tttqf |= E1000_TTQF_QUEUE_ENABLE;\n\tttqf |= (uint32_t)(filter->queue << E1000_TTQF_QUEUE_SHIFT);\n\tttqf |= (uint32_t)(filter->filter_info.proto & E1000_TTQF_PROTOCOL_MASK);\n\tif (filter->filter_info.proto_mask == 0)\n\t\tttqf &= ~E1000_TTQF_MASK_ENABLE;\n\n\t/* tcp flags bits setting. */\n\tif (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {\n\t\tif (filter->filter_info.tcp_flags & TCP_URG_FLAG)\n\t\t\timir_ext |= E1000_IMIREXT_CTRL_URG;\n\t\tif (filter->filter_info.tcp_flags & TCP_ACK_FLAG)\n\t\t\timir_ext |= E1000_IMIREXT_CTRL_ACK;\n\t\tif (filter->filter_info.tcp_flags & TCP_PSH_FLAG)\n\t\t\timir_ext |= E1000_IMIREXT_CTRL_PSH;\n\t\tif (filter->filter_info.tcp_flags & TCP_RST_FLAG)\n\t\t\timir_ext |= E1000_IMIREXT_CTRL_RST;\n\t\tif (filter->filter_info.tcp_flags & TCP_SYN_FLAG)\n\t\t\timir_ext |= E1000_IMIREXT_CTRL_SYN;\n\t\tif (filter->filter_info.tcp_flags & TCP_FIN_FLAG)\n\t\t\timir_ext |= E1000_IMIREXT_CTRL_FIN;\n\t} else\n\t\timir_ext |= E1000_IMIREXT_CTRL_BP;\n\tE1000_WRITE_REG(hw, E1000_IMIR(i), imir);\n\tE1000_WRITE_REG(hw, E1000_TTQF(i), ttqf);\n\tE1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);\n\treturn 0;\n}\n\n/*\n * igb_remove_2tuple_filter - remove a 2tuple filter\n *\n * @param\n * dev: Pointer to struct rte_eth_dev.\n * ntuple_filter: ponter to the filter that will be removed.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nigb_remove_2tuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *ntuple_filter)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_filter_info *filter_info =\n\t\tE1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tstruct e1000_2tuple_filter_info filter_2tuple;\n\tstruct e1000_2tuple_filter *filter;\n\tint ret;\n\n\tmemset(&filter_2tuple, 0, sizeof(struct e1000_2tuple_filter_info));\n\tret = ntuple_filter_to_2tuple(ntuple_filter,\n\t\t\t\t &filter_2tuple);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tfilter = igb_2tuple_filter_lookup(&filter_info->twotuple_list,\n\t\t\t\t\t &filter_2tuple);\n\tif (filter == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"filter doesn't exist.\");\n\t\treturn -ENOENT;\n\t}\n\n\tfilter_info->twotuple_mask &= ~(1 << filter->index);\n\tTAILQ_REMOVE(&filter_info->twotuple_list, filter, entries);\n\trte_free(filter);\n\n\tE1000_WRITE_REG(hw, E1000_TTQF(filter->index), E1000_TTQF_DISABLE_MASK);\n\tE1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);\n\tE1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);\n\treturn 0;\n}\n\nstatic inline struct e1000_flex_filter *\neth_igb_flex_filter_lookup(struct e1000_flex_filter_list *filter_list,\n\t\t\tstruct e1000_flex_filter_info *key)\n{\n\tstruct e1000_flex_filter *it;\n\n\tTAILQ_FOREACH(it, filter_list, entries) {\n\t\tif (memcmp(key, &it->filter_info,\n\t\t\tsizeof(struct e1000_flex_filter_info)) == 0)\n\t\t\treturn it;\n\t}\n\n\treturn NULL;\n}\n\nstatic int\neth_igb_add_del_flex_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_flex_filter *filter,\n\t\t\tbool add)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_filter_info *filter_info =\n\t\tE1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tstruct e1000_flex_filter *flex_filter, *it;\n\tuint32_t wufc, queueing, mask;\n\tuint32_t reg_off;\n\tuint8_t shift, i, j = 0;\n\n\tflex_filter = rte_zmalloc(\"e1000_flex_filter\",\n\t\t\tsizeof(struct e1000_flex_filter), 0);\n\tif (flex_filter == NULL)\n\t\treturn -ENOMEM;\n\n\tflex_filter->filter_info.len = filter->len;\n\tflex_filter->filter_info.priority = filter->priority;\n\tmemcpy(flex_filter->filter_info.dwords, filter->bytes, filter->len);\n\tfor (i = 0; i < RTE_ALIGN(filter->len, CHAR_BIT) / CHAR_BIT; i++) {\n\t\tmask = 0;\n\t\t/* reverse bits in flex filter's mask*/\n\t\tfor (shift = 0; shift < CHAR_BIT; shift++) {\n\t\t\tif (filter->mask[i] & (0x01 << shift))\n\t\t\t\tmask |= (0x80 >> shift);\n\t\t}\n\t\tflex_filter->filter_info.mask[i] = mask;\n\t}\n\n\twufc = E1000_READ_REG(hw, E1000_WUFC);\n\tif (flex_filter->index < E1000_MAX_FHFT)\n\t\treg_off = E1000_FHFT(flex_filter->index);\n\telse\n\t\treg_off = E1000_FHFT_EXT(flex_filter->index - E1000_MAX_FHFT);\n\n\tif (add) {\n\t\tif (eth_igb_flex_filter_lookup(&filter_info->flex_list,\n\t\t\t\t&flex_filter->filter_info) != NULL) {\n\t\t\tPMD_DRV_LOG(ERR, \"filter exists.\");\n\t\t\trte_free(flex_filter);\n\t\t\treturn -EEXIST;\n\t\t}\n\t\tflex_filter->queue = filter->queue;\n\t\t/*\n\t\t * look for an unused flex filter index\n\t\t * and insert the filter into the list.\n\t\t */\n\t\tfor (i = 0; i < E1000_MAX_FLEX_FILTERS; i++) {\n\t\t\tif (!(filter_info->flex_mask & (1 << i))) {\n\t\t\t\tfilter_info->flex_mask |= 1 << i;\n\t\t\t\tflex_filter->index = i;\n\t\t\t\tTAILQ_INSERT_TAIL(&filter_info->flex_list,\n\t\t\t\t\tflex_filter,\n\t\t\t\t\tentries);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (i >= E1000_MAX_FLEX_FILTERS) {\n\t\t\tPMD_DRV_LOG(ERR, \"flex filters are full.\");\n\t\t\trte_free(flex_filter);\n\t\t\treturn -ENOSYS;\n\t\t}\n\n\t\tE1000_WRITE_REG(hw, E1000_WUFC, wufc | E1000_WUFC_FLEX_HQ |\n\t\t\t\t(E1000_WUFC_FLX0 << flex_filter->index));\n\t\tqueueing = filter->len |\n\t\t\t(filter->queue << E1000_FHFT_QUEUEING_QUEUE_SHIFT) |\n\t\t\t(filter->priority << E1000_FHFT_QUEUEING_PRIO_SHIFT);\n\t\tE1000_WRITE_REG(hw, reg_off + E1000_FHFT_QUEUEING_OFFSET,\n\t\t\t\tqueueing);\n\t\tfor (i = 0; i < E1000_FLEX_FILTERS_MASK_SIZE; i++) {\n\t\t\tE1000_WRITE_REG(hw, reg_off,\n\t\t\t\t\tflex_filter->filter_info.dwords[j]);\n\t\t\treg_off += sizeof(uint32_t);\n\t\t\tE1000_WRITE_REG(hw, reg_off,\n\t\t\t\t\tflex_filter->filter_info.dwords[++j]);\n\t\t\treg_off += sizeof(uint32_t);\n\t\t\tE1000_WRITE_REG(hw, reg_off,\n\t\t\t\t(uint32_t)flex_filter->filter_info.mask[i]);\n\t\t\treg_off += sizeof(uint32_t) * 2;\n\t\t\t++j;\n\t\t}\n\t} else {\n\t\tit = eth_igb_flex_filter_lookup(&filter_info->flex_list,\n\t\t\t\t&flex_filter->filter_info);\n\t\tif (it == NULL) {\n\t\t\tPMD_DRV_LOG(ERR, \"filter doesn't exist.\");\n\t\t\trte_free(flex_filter);\n\t\t\treturn -ENOENT;\n\t\t}\n\n\t\tfor (i = 0; i < E1000_FHFT_SIZE_IN_DWD; i++)\n\t\t\tE1000_WRITE_REG(hw, reg_off + i * sizeof(uint32_t), 0);\n\t\tE1000_WRITE_REG(hw, E1000_WUFC, wufc &\n\t\t\t(~(E1000_WUFC_FLX0 << it->index)));\n\n\t\tfilter_info->flex_mask &= ~(1 << it->index);\n\t\tTAILQ_REMOVE(&filter_info->flex_list, it, entries);\n\t\trte_free(it);\n\t\trte_free(flex_filter);\n\t}\n\n\treturn 0;\n}\n\nstatic int\neth_igb_get_flex_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_flex_filter *filter)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_filter_info *filter_info =\n\t\tE1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tstruct e1000_flex_filter flex_filter, *it;\n\tuint32_t wufc, queueing, wufc_en = 0;\n\n\tmemset(&flex_filter, 0, sizeof(struct e1000_flex_filter));\n\tflex_filter.filter_info.len = filter->len;\n\tflex_filter.filter_info.priority = filter->priority;\n\tmemcpy(flex_filter.filter_info.dwords, filter->bytes, filter->len);\n\tmemcpy(flex_filter.filter_info.mask, filter->mask,\n\t\t\tRTE_ALIGN(filter->len, sizeof(char)) / sizeof(char));\n\n\tit = eth_igb_flex_filter_lookup(&filter_info->flex_list,\n\t\t\t\t&flex_filter.filter_info);\n\tif (it == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"filter doesn't exist.\");\n\t\treturn -ENOENT;\n\t}\n\n\twufc = E1000_READ_REG(hw, E1000_WUFC);\n\twufc_en = E1000_WUFC_FLEX_HQ | (E1000_WUFC_FLX0 << it->index);\n\n\tif ((wufc & wufc_en) == wufc_en) {\n\t\tuint32_t reg_off = 0;\n\t\tif (it->index < E1000_MAX_FHFT)\n\t\t\treg_off = E1000_FHFT(it->index);\n\t\telse\n\t\t\treg_off = E1000_FHFT_EXT(it->index - E1000_MAX_FHFT);\n\n\t\tqueueing = E1000_READ_REG(hw,\n\t\t\t\treg_off + E1000_FHFT_QUEUEING_OFFSET);\n\t\tfilter->len = queueing & E1000_FHFT_QUEUEING_LEN;\n\t\tfilter->priority = (queueing & E1000_FHFT_QUEUEING_PRIO) >>\n\t\t\tE1000_FHFT_QUEUEING_PRIO_SHIFT;\n\t\tfilter->queue = (queueing & E1000_FHFT_QUEUEING_QUEUE) >>\n\t\t\tE1000_FHFT_QUEUEING_QUEUE_SHIFT;\n\t\treturn 0;\n\t}\n\treturn -ENOENT;\n}\n\nstatic int\neth_igb_flex_filter_handle(struct rte_eth_dev *dev,\n\t\t\tenum rte_filter_op filter_op,\n\t\t\tvoid *arg)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct rte_eth_flex_filter *filter;\n\tint ret = 0;\n\n\tMAC_TYPE_FILTER_SUP_EXT(hw->mac.type);\n\n\tif (filter_op == RTE_ETH_FILTER_NOP)\n\t\treturn ret;\n\n\tif (arg == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"arg shouldn't be NULL for operation %u\",\n\t\t\t filter_op);\n\t\treturn -EINVAL;\n\t}\n\n\tfilter = (struct rte_eth_flex_filter *)arg;\n\tif (filter->len == 0 || filter->len > E1000_MAX_FLEX_FILTER_LEN\n\t || filter->len % sizeof(uint64_t) != 0) {\n\t\tPMD_DRV_LOG(ERR, \"filter's length is out of range\");\n\t\treturn -EINVAL;\n\t}\n\tif (filter->priority > E1000_MAX_FLEX_FILTER_PRI) {\n\t\tPMD_DRV_LOG(ERR, \"filter's priority is out of range\");\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_ADD:\n\t\tret = eth_igb_add_del_flex_filter(dev, filter, TRUE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_DELETE:\n\t\tret = eth_igb_add_del_flex_filter(dev, filter, FALSE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_GET:\n\t\tret = eth_igb_get_flex_filter(dev, filter);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unsupported operation %u\", filter_op);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n/* translate elements in struct rte_eth_ntuple_filter to struct e1000_5tuple_filter_info*/\nstatic inline int\nntuple_filter_to_5tuple_82576(struct rte_eth_ntuple_filter *filter,\n\t\t\tstruct e1000_5tuple_filter_info *filter_info)\n{\n\tif (filter->queue >= IGB_MAX_RX_QUEUE_NUM_82576)\n\t\treturn -EINVAL;\n\tif (filter->priority > E1000_2TUPLE_MAX_PRI)\n\t\treturn -EINVAL; /* filter index is out of range. */\n\tif (filter->tcp_flags > TCP_FLAG_ALL)\n\t\treturn -EINVAL; /* flags is invalid. */\n\n\tswitch (filter->dst_ip_mask) {\n\tcase UINT32_MAX:\n\t\tfilter_info->dst_ip_mask = 0;\n\t\tfilter_info->dst_ip = filter->dst_ip;\n\t\tbreak;\n\tcase 0:\n\t\tfilter_info->dst_ip_mask = 1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid dst_ip mask.\");\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter->src_ip_mask) {\n\tcase UINT32_MAX:\n\t\tfilter_info->src_ip_mask = 0;\n\t\tfilter_info->src_ip = filter->src_ip;\n\t\tbreak;\n\tcase 0:\n\t\tfilter_info->src_ip_mask = 1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid src_ip mask.\");\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter->dst_port_mask) {\n\tcase UINT16_MAX:\n\t\tfilter_info->dst_port_mask = 0;\n\t\tfilter_info->dst_port = filter->dst_port;\n\t\tbreak;\n\tcase 0:\n\t\tfilter_info->dst_port_mask = 1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid dst_port mask.\");\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter->src_port_mask) {\n\tcase UINT16_MAX:\n\t\tfilter_info->src_port_mask = 0;\n\t\tfilter_info->src_port = filter->src_port;\n\t\tbreak;\n\tcase 0:\n\t\tfilter_info->src_port_mask = 1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid src_port mask.\");\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter->proto_mask) {\n\tcase UINT8_MAX:\n\t\tfilter_info->proto_mask = 0;\n\t\tfilter_info->proto = filter->proto;\n\t\tbreak;\n\tcase 0:\n\t\tfilter_info->proto_mask = 1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid protocol mask.\");\n\t\treturn -EINVAL;\n\t}\n\n\tfilter_info->priority = (uint8_t)filter->priority;\n\tif (filter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG)\n\t\tfilter_info->tcp_flags = filter->tcp_flags;\n\telse\n\t\tfilter_info->tcp_flags = 0;\n\n\treturn 0;\n}\n\nstatic inline struct e1000_5tuple_filter *\nigb_5tuple_filter_lookup_82576(struct e1000_5tuple_filter_list *filter_list,\n\t\t\tstruct e1000_5tuple_filter_info *key)\n{\n\tstruct e1000_5tuple_filter *it;\n\n\tTAILQ_FOREACH(it, filter_list, entries) {\n\t\tif (memcmp(key, &it->filter_info,\n\t\t\tsizeof(struct e1000_5tuple_filter_info)) == 0) {\n\t\t\treturn it;\n\t\t}\n\t}\n\treturn NULL;\n}\n\n/*\n * igb_add_5tuple_filter_82576 - add a 5tuple filter\n *\n * @param\n * dev: Pointer to struct rte_eth_dev.\n * ntuple_filter: ponter to the filter that will be added.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nigb_add_5tuple_filter_82576(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *ntuple_filter)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_filter_info *filter_info =\n\t\tE1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tstruct e1000_5tuple_filter *filter;\n\tuint32_t ftqf = E1000_FTQF_VF_BP | E1000_FTQF_MASK;\n\tuint32_t spqf, imir, imir_ext = E1000_IMIREXT_SIZE_BP;\n\tuint8_t i;\n\tint ret;\n\n\tfilter = rte_zmalloc(\"e1000_5tuple_filter\",\n\t\t\tsizeof(struct e1000_5tuple_filter), 0);\n\tif (filter == NULL)\n\t\treturn -ENOMEM;\n\n\tret = ntuple_filter_to_5tuple_82576(ntuple_filter,\n\t\t\t\t\t &filter->filter_info);\n\tif (ret < 0) {\n\t\trte_free(filter);\n\t\treturn ret;\n\t}\n\n\tif (igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,\n\t\t\t\t\t &filter->filter_info) != NULL) {\n\t\tPMD_DRV_LOG(ERR, \"filter exists.\");\n\t\trte_free(filter);\n\t\treturn -EEXIST;\n\t}\n\tfilter->queue = ntuple_filter->queue;\n\n\t/*\n\t * look for an unused 5tuple filter index,\n\t * and insert the filter to list.\n\t */\n\tfor (i = 0; i < E1000_MAX_FTQF_FILTERS; i++) {\n\t\tif (!(filter_info->fivetuple_mask & (1 << i))) {\n\t\t\tfilter_info->fivetuple_mask |= 1 << i;\n\t\t\tfilter->index = i;\n\t\t\tTAILQ_INSERT_TAIL(&filter_info->fivetuple_list,\n\t\t\t\t\t filter,\n\t\t\t\t\t entries);\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (i >= E1000_MAX_FTQF_FILTERS) {\n\t\tPMD_DRV_LOG(ERR, \"5tuple filters are full.\");\n\t\trte_free(filter);\n\t\treturn -ENOSYS;\n\t}\n\n\tftqf |= filter->filter_info.proto & E1000_FTQF_PROTOCOL_MASK;\n\tif (filter->filter_info.src_ip_mask == 0) /* 0b means compare. */\n\t\tftqf &= ~E1000_FTQF_MASK_SOURCE_ADDR_BP;\n\tif (filter->filter_info.dst_ip_mask == 0)\n\t\tftqf &= ~E1000_FTQF_MASK_DEST_ADDR_BP;\n\tif (filter->filter_info.src_port_mask == 0)\n\t\tftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;\n\tif (filter->filter_info.proto_mask == 0)\n\t\tftqf &= ~E1000_FTQF_MASK_PROTO_BP;\n\tftqf |= (filter->queue << E1000_FTQF_QUEUE_SHIFT) &\n\t\tE1000_FTQF_QUEUE_MASK;\n\tftqf |= E1000_FTQF_QUEUE_ENABLE;\n\tE1000_WRITE_REG(hw, E1000_FTQF(i), ftqf);\n\tE1000_WRITE_REG(hw, E1000_DAQF(i), filter->filter_info.dst_ip);\n\tE1000_WRITE_REG(hw, E1000_SAQF(i), filter->filter_info.src_ip);\n\n\tspqf = filter->filter_info.src_port & E1000_SPQF_SRCPORT;\n\tE1000_WRITE_REG(hw, E1000_SPQF(i), spqf);\n\n\timir = (uint32_t)(filter->filter_info.dst_port & E1000_IMIR_DSTPORT);\n\tif (filter->filter_info.dst_port_mask == 1) /* 1b means not compare. */\n\t\timir |= E1000_IMIR_PORT_BP;\n\telse\n\t\timir &= ~E1000_IMIR_PORT_BP;\n\timir |= filter->filter_info.priority << E1000_IMIR_PRIORITY_SHIFT;\n\n\t/* tcp flags bits setting. */\n\tif (filter->filter_info.tcp_flags & TCP_FLAG_ALL) {\n\t\tif (filter->filter_info.tcp_flags & TCP_URG_FLAG)\n\t\t\timir_ext |= E1000_IMIREXT_CTRL_URG;\n\t\tif (filter->filter_info.tcp_flags & TCP_ACK_FLAG)\n\t\t\timir_ext |= E1000_IMIREXT_CTRL_ACK;\n\t\tif (filter->filter_info.tcp_flags & TCP_PSH_FLAG)\n\t\t\timir_ext |= E1000_IMIREXT_CTRL_PSH;\n\t\tif (filter->filter_info.tcp_flags & TCP_RST_FLAG)\n\t\t\timir_ext |= E1000_IMIREXT_CTRL_RST;\n\t\tif (filter->filter_info.tcp_flags & TCP_SYN_FLAG)\n\t\t\timir_ext |= E1000_IMIREXT_CTRL_SYN;\n\t\tif (filter->filter_info.tcp_flags & TCP_FIN_FLAG)\n\t\t\timir_ext |= E1000_IMIREXT_CTRL_FIN;\n\t} else\n\t\timir_ext |= E1000_IMIREXT_CTRL_BP;\n\tE1000_WRITE_REG(hw, E1000_IMIR(i), imir);\n\tE1000_WRITE_REG(hw, E1000_IMIREXT(i), imir_ext);\n\treturn 0;\n}\n\n/*\n * igb_remove_5tuple_filter_82576 - remove a 5tuple filter\n *\n * @param\n * dev: Pointer to struct rte_eth_dev.\n * ntuple_filter: ponter to the filter that will be removed.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nigb_remove_5tuple_filter_82576(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_ntuple_filter *ntuple_filter)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_filter_info *filter_info =\n\t\tE1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tstruct e1000_5tuple_filter_info filter_5tuple;\n\tstruct e1000_5tuple_filter *filter;\n\tint ret;\n\n\tmemset(&filter_5tuple, 0, sizeof(struct e1000_5tuple_filter_info));\n\tret = ntuple_filter_to_5tuple_82576(ntuple_filter,\n\t\t\t\t\t &filter_5tuple);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tfilter = igb_5tuple_filter_lookup_82576(&filter_info->fivetuple_list,\n\t\t\t\t\t &filter_5tuple);\n\tif (filter == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"filter doesn't exist.\");\n\t\treturn -ENOENT;\n\t}\n\n\tfilter_info->fivetuple_mask &= ~(1 << filter->index);\n\tTAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);\n\trte_free(filter);\n\n\tE1000_WRITE_REG(hw, E1000_FTQF(filter->index),\n\t\t\tE1000_FTQF_VF_BP | E1000_FTQF_MASK);\n\tE1000_WRITE_REG(hw, E1000_DAQF(filter->index), 0);\n\tE1000_WRITE_REG(hw, E1000_SAQF(filter->index), 0);\n\tE1000_WRITE_REG(hw, E1000_SPQF(filter->index), 0);\n\tE1000_WRITE_REG(hw, E1000_IMIR(filter->index), 0);\n\tE1000_WRITE_REG(hw, E1000_IMIREXT(filter->index), 0);\n\treturn 0;\n}\n\nstatic int\neth_igb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)\n{\n\tuint32_t rctl;\n\tstruct e1000_hw *hw;\n\tstruct rte_eth_dev_info dev_info;\n\tuint32_t frame_size = mtu + (ETHER_HDR_LEN + ETHER_CRC_LEN +\n\t\t\t\t VLAN_TAG_SIZE);\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n#ifdef RTE_LIBRTE_82571_SUPPORT\n\t/* XXX: not bigger than max_rx_pktlen */\n\tif (hw->mac.type == e1000_82571)\n\t\treturn -ENOTSUP;\n#endif\n\teth_igb_infos_get(dev, &dev_info);\n\n\t/* check that mtu is within the allowed range */\n\tif ((mtu < ETHER_MIN_MTU) ||\n\t (frame_size > dev_info.max_rx_pktlen))\n\t\treturn -EINVAL;\n\n\t/* refuse mtu that requires the support of scattered packets when this\n\t * feature has not been enabled before. */\n\tif (!dev->data->scattered_rx &&\n\t frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)\n\t\treturn -EINVAL;\n\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\n\t/* switch to jumbo mode if needed */\n\tif (frame_size > ETHER_MAX_LEN) {\n\t\tdev->data->dev_conf.rxmode.jumbo_frame = 1;\n\t\trctl |= E1000_RCTL_LPE;\n\t} else {\n\t\tdev->data->dev_conf.rxmode.jumbo_frame = 0;\n\t\trctl &= ~E1000_RCTL_LPE;\n\t}\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\n\t/* update max frame size */\n\tdev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;\n\n\tE1000_WRITE_REG(hw, E1000_RLPML,\n\t\t\tdev->data->dev_conf.rxmode.max_rx_pkt_len);\n\n\treturn 0;\n}\n\n/*\n * igb_add_del_ntuple_filter - add or delete a ntuple filter\n *\n * @param\n * dev: Pointer to struct rte_eth_dev.\n * ntuple_filter: Pointer to struct rte_eth_ntuple_filter\n * add: if true, add filter, if false, remove filter\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nigb_add_del_ntuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *ntuple_filter,\n\t\t\tbool add)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint ret;\n\n\tswitch (ntuple_filter->flags) {\n\tcase RTE_5TUPLE_FLAGS:\n\tcase (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):\n\t\tif (hw->mac.type != e1000_82576)\n\t\t\treturn -ENOTSUP;\n\t\tif (add)\n\t\t\tret = igb_add_5tuple_filter_82576(dev,\n\t\t\t\t\t\t\t ntuple_filter);\n\t\telse\n\t\t\tret = igb_remove_5tuple_filter_82576(dev,\n\t\t\t\t\t\t\t ntuple_filter);\n\t\tbreak;\n\tcase RTE_2TUPLE_FLAGS:\n\tcase (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):\n\t\tif (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)\n\t\t\treturn -ENOTSUP;\n\t\tif (add)\n\t\t\tret = igb_add_2tuple_filter(dev, ntuple_filter);\n\t\telse\n\t\t\tret = igb_remove_2tuple_filter(dev, ntuple_filter);\n\t\tbreak;\n\tdefault:\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n/*\n * igb_get_ntuple_filter - get a ntuple filter\n *\n * @param\n * dev: Pointer to struct rte_eth_dev.\n * ntuple_filter: Pointer to struct rte_eth_ntuple_filter\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nigb_get_ntuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *ntuple_filter)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_filter_info *filter_info =\n\t\tE1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tstruct e1000_5tuple_filter_info filter_5tuple;\n\tstruct e1000_2tuple_filter_info filter_2tuple;\n\tstruct e1000_5tuple_filter *p_5tuple_filter;\n\tstruct e1000_2tuple_filter *p_2tuple_filter;\n\tint ret;\n\n\tswitch (ntuple_filter->flags) {\n\tcase RTE_5TUPLE_FLAGS:\n\tcase (RTE_5TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):\n\t\tif (hw->mac.type != e1000_82576)\n\t\t\treturn -ENOTSUP;\n\t\tmemset(&filter_5tuple,\n\t\t\t0,\n\t\t\tsizeof(struct e1000_5tuple_filter_info));\n\t\tret = ntuple_filter_to_5tuple_82576(ntuple_filter,\n\t\t\t\t\t\t &filter_5tuple);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\tp_5tuple_filter = igb_5tuple_filter_lookup_82576(\n\t\t\t\t\t&filter_info->fivetuple_list,\n\t\t\t\t\t&filter_5tuple);\n\t\tif (p_5tuple_filter == NULL) {\n\t\t\tPMD_DRV_LOG(ERR, \"filter doesn't exist.\");\n\t\t\treturn -ENOENT;\n\t\t}\n\t\tntuple_filter->queue = p_5tuple_filter->queue;\n\t\tbreak;\n\tcase RTE_2TUPLE_FLAGS:\n\tcase (RTE_2TUPLE_FLAGS | RTE_NTUPLE_FLAGS_TCP_FLAG):\n\t\tif (hw->mac.type != e1000_82580 && hw->mac.type != e1000_i350)\n\t\t\treturn -ENOTSUP;\n\t\tmemset(&filter_2tuple,\n\t\t\t0,\n\t\t\tsizeof(struct e1000_2tuple_filter_info));\n\t\tret = ntuple_filter_to_2tuple(ntuple_filter, &filter_2tuple);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t\tp_2tuple_filter = igb_2tuple_filter_lookup(\n\t\t\t\t\t&filter_info->twotuple_list,\n\t\t\t\t\t&filter_2tuple);\n\t\tif (p_2tuple_filter == NULL) {\n\t\t\tPMD_DRV_LOG(ERR, \"filter doesn't exist.\");\n\t\t\treturn -ENOENT;\n\t\t}\n\t\tntuple_filter->queue = p_2tuple_filter->queue;\n\t\tbreak;\n\tdefault:\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\n/*\n * igb_ntuple_filter_handle - Handle operations for ntuple filter.\n * @dev: pointer to rte_eth_dev structure\n * @filter_op:operation will be taken.\n * @arg: a pointer to specific structure corresponding to the filter_op\n */\nstatic int\nigb_ntuple_filter_handle(struct rte_eth_dev *dev,\n\t\t\t\tenum rte_filter_op filter_op,\n\t\t\t\tvoid *arg)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint ret;\n\n\tMAC_TYPE_FILTER_SUP(hw->mac.type);\n\n\tif (filter_op == RTE_ETH_FILTER_NOP)\n\t\treturn 0;\n\n\tif (arg == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"arg shouldn't be NULL for operation %u.\",\n\t\t\t filter_op);\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_ADD:\n\t\tret = igb_add_del_ntuple_filter(dev,\n\t\t\t(struct rte_eth_ntuple_filter *)arg,\n\t\t\tTRUE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_DELETE:\n\t\tret = igb_add_del_ntuple_filter(dev,\n\t\t\t(struct rte_eth_ntuple_filter *)arg,\n\t\t\tFALSE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_GET:\n\t\tret = igb_get_ntuple_filter(dev,\n\t\t\t(struct rte_eth_ntuple_filter *)arg);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unsupported operation %u.\", filter_op);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\nstatic inline int\nigb_ethertype_filter_lookup(struct e1000_filter_info *filter_info,\n\t\t\tuint16_t ethertype)\n{\n\tint i;\n\n\tfor (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {\n\t\tif (filter_info->ethertype_filters[i] == ethertype &&\n\t\t (filter_info->ethertype_mask & (1 << i)))\n\t\t\treturn i;\n\t}\n\treturn -1;\n}\n\nstatic inline int\nigb_ethertype_filter_insert(struct e1000_filter_info *filter_info,\n\t\t\tuint16_t ethertype)\n{\n\tint i;\n\n\tfor (i = 0; i < E1000_MAX_ETQF_FILTERS; i++) {\n\t\tif (!(filter_info->ethertype_mask & (1 << i))) {\n\t\t\tfilter_info->ethertype_mask |= 1 << i;\n\t\t\tfilter_info->ethertype_filters[i] = ethertype;\n\t\t\treturn i;\n\t\t}\n\t}\n\treturn -1;\n}\n\nstatic inline int\nigb_ethertype_filter_remove(struct e1000_filter_info *filter_info,\n\t\t\tuint8_t idx)\n{\n\tif (idx >= E1000_MAX_ETQF_FILTERS)\n\t\treturn -1;\n\tfilter_info->ethertype_mask &= ~(1 << idx);\n\tfilter_info->ethertype_filters[idx] = 0;\n\treturn idx;\n}\n\n\nstatic int\nigb_add_del_ethertype_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ethertype_filter *filter,\n\t\t\tbool add)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_filter_info *filter_info =\n\t\tE1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tuint32_t etqf = 0;\n\tint ret;\n\n\tif (filter->ether_type == ETHER_TYPE_IPv4 ||\n\t\tfilter->ether_type == ETHER_TYPE_IPv6) {\n\t\tPMD_DRV_LOG(ERR, \"unsupported ether_type(0x%04x) in\"\n\t\t\t\" ethertype filter.\", filter->ether_type);\n\t\treturn -EINVAL;\n\t}\n\n\tif (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {\n\t\tPMD_DRV_LOG(ERR, \"mac compare is unsupported.\");\n\t\treturn -EINVAL;\n\t}\n\tif (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {\n\t\tPMD_DRV_LOG(ERR, \"drop option is unsupported.\");\n\t\treturn -EINVAL;\n\t}\n\n\tret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);\n\tif (ret >= 0 && add) {\n\t\tPMD_DRV_LOG(ERR, \"ethertype (0x%04x) filter exists.\",\n\t\t\t filter->ether_type);\n\t\treturn -EEXIST;\n\t}\n\tif (ret < 0 && !add) {\n\t\tPMD_DRV_LOG(ERR, \"ethertype (0x%04x) filter doesn't exist.\",\n\t\t\t filter->ether_type);\n\t\treturn -ENOENT;\n\t}\n\n\tif (add) {\n\t\tret = igb_ethertype_filter_insert(filter_info,\n\t\t\tfilter->ether_type);\n\t\tif (ret < 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"ethertype filters are full.\");\n\t\t\treturn -ENOSYS;\n\t\t}\n\n\t\tetqf |= E1000_ETQF_FILTER_ENABLE | E1000_ETQF_QUEUE_ENABLE;\n\t\tetqf |= (uint32_t)(filter->ether_type & E1000_ETQF_ETHERTYPE);\n\t\tetqf |= filter->queue << E1000_ETQF_QUEUE_SHIFT;\n\t} else {\n\t\tret = igb_ethertype_filter_remove(filter_info, (uint8_t)ret);\n\t\tif (ret < 0)\n\t\t\treturn -ENOSYS;\n\t}\n\tE1000_WRITE_REG(hw, E1000_ETQF(ret), etqf);\n\tE1000_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\nstatic int\nigb_get_ethertype_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ethertype_filter *filter)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_filter_info *filter_info =\n\t\tE1000_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tuint32_t etqf;\n\tint ret;\n\n\tret = igb_ethertype_filter_lookup(filter_info, filter->ether_type);\n\tif (ret < 0) {\n\t\tPMD_DRV_LOG(ERR, \"ethertype (0x%04x) filter doesn't exist.\",\n\t\t\t filter->ether_type);\n\t\treturn -ENOENT;\n\t}\n\n\tetqf = E1000_READ_REG(hw, E1000_ETQF(ret));\n\tif (etqf & E1000_ETQF_FILTER_ENABLE) {\n\t\tfilter->ether_type = etqf & E1000_ETQF_ETHERTYPE;\n\t\tfilter->flags = 0;\n\t\tfilter->queue = (etqf & E1000_ETQF_QUEUE) >>\n\t\t\t\tE1000_ETQF_QUEUE_SHIFT;\n\t\treturn 0;\n\t}\n\n\treturn -ENOENT;\n}\n\n/*\n * igb_ethertype_filter_handle - Handle operations for ethertype filter.\n * @dev: pointer to rte_eth_dev structure\n * @filter_op:operation will be taken.\n * @arg: a pointer to specific structure corresponding to the filter_op\n */\nstatic int\nigb_ethertype_filter_handle(struct rte_eth_dev *dev,\n\t\t\t\tenum rte_filter_op filter_op,\n\t\t\t\tvoid *arg)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint ret;\n\n\tMAC_TYPE_FILTER_SUP(hw->mac.type);\n\n\tif (filter_op == RTE_ETH_FILTER_NOP)\n\t\treturn 0;\n\n\tif (arg == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"arg shouldn't be NULL for operation %u.\",\n\t\t\t filter_op);\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_ADD:\n\t\tret = igb_add_del_ethertype_filter(dev,\n\t\t\t(struct rte_eth_ethertype_filter *)arg,\n\t\t\tTRUE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_DELETE:\n\t\tret = igb_add_del_ethertype_filter(dev,\n\t\t\t(struct rte_eth_ethertype_filter *)arg,\n\t\t\tFALSE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_GET:\n\t\tret = igb_get_ethertype_filter(dev,\n\t\t\t(struct rte_eth_ethertype_filter *)arg);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unsupported operation %u.\", filter_op);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\nstatic int\neth_igb_filter_ctrl(struct rte_eth_dev *dev,\n\t\t enum rte_filter_type filter_type,\n\t\t enum rte_filter_op filter_op,\n\t\t void *arg)\n{\n\tint ret = -EINVAL;\n\n\tswitch (filter_type) {\n\tcase RTE_ETH_FILTER_NTUPLE:\n\t\tret = igb_ntuple_filter_handle(dev, filter_op, arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_ETHERTYPE:\n\t\tret = igb_ethertype_filter_handle(dev, filter_op, arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_SYN:\n\t\tret = eth_igb_syn_filter_handle(dev, filter_op, arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_FLEXIBLE:\n\t\tret = eth_igb_flex_filter_handle(dev, filter_op, arg);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(WARNING, \"Filter type (%d) not supported\",\n\t\t\t\t\t\t\tfilter_type);\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int\neth_igb_set_mc_addr_list(struct rte_eth_dev *dev,\n\t\t\t struct ether_addr *mc_addr_set,\n\t\t\t uint32_t nb_mc_addr)\n{\n\tstruct e1000_hw *hw;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\te1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);\n\treturn 0;\n}\n\nstatic int\nigb_timesync_enable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t tsync_ctl;\n\tuint32_t tsauxc;\n\n\t/* Enable system time for it isn't on by default. */\n\ttsauxc = E1000_READ_REG(hw, E1000_TSAUXC);\n\ttsauxc &= ~E1000_TSAUXC_DISABLE_SYSTIME;\n\tE1000_WRITE_REG(hw, E1000_TSAUXC, tsauxc);\n\n\t/* Start incrementing the register used to timestamp PTP packets. */\n\tE1000_WRITE_REG(hw, E1000_TIMINCA, E1000_TIMINCA_INIT);\n\n\t/* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */\n\tE1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588),\n\t\t\t(ETHER_TYPE_1588 |\n\t\t\t E1000_ETQF_FILTER_ENABLE |\n\t\t\t E1000_ETQF_1588));\n\n\t/* Enable timestamping of received PTP packets. */\n\ttsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);\n\ttsync_ctl |= E1000_TSYNCRXCTL_ENABLED;\n\tE1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);\n\n\t/* Enable Timestamping of transmitted PTP packets. */\n\ttsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);\n\ttsync_ctl |= E1000_TSYNCTXCTL_ENABLED;\n\tE1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);\n\n\treturn 0;\n}\n\nstatic int\nigb_timesync_disable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t tsync_ctl;\n\n\t/* Disable timestamping of transmitted PTP packets. */\n\ttsync_ctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);\n\ttsync_ctl &= ~E1000_TSYNCTXCTL_ENABLED;\n\tE1000_WRITE_REG(hw, E1000_TSYNCTXCTL, tsync_ctl);\n\n\t/* Disable timestamping of received PTP packets. */\n\ttsync_ctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);\n\ttsync_ctl &= ~E1000_TSYNCRXCTL_ENABLED;\n\tE1000_WRITE_REG(hw, E1000_TSYNCRXCTL, tsync_ctl);\n\n\t/* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */\n\tE1000_WRITE_REG(hw, E1000_ETQF(E1000_ETQF_FILTER_1588), 0);\n\n\t/* Stop incrementating the System Time registers. */\n\tE1000_WRITE_REG(hw, E1000_TIMINCA, 0);\n\n\treturn 0;\n}\n\nstatic int\nigb_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n\t\t\t struct timespec *timestamp,\n\t\t\t uint32_t flags __rte_unused)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t tsync_rxctl;\n\tuint32_t rx_stmpl;\n\tuint32_t rx_stmph;\n\n\ttsync_rxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);\n\tif ((tsync_rxctl & E1000_TSYNCRXCTL_VALID) == 0)\n\t\treturn -EINVAL;\n\n\trx_stmpl = E1000_READ_REG(hw, E1000_RXSTMPL);\n\trx_stmph = E1000_READ_REG(hw, E1000_RXSTMPH);\n\n\ttimestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);\n\ttimestamp->tv_nsec = 0;\n\n\treturn 0;\n}\n\nstatic int\nigb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n\t\t\t struct timespec *timestamp)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t tsync_txctl;\n\tuint32_t tx_stmpl;\n\tuint32_t tx_stmph;\n\n\ttsync_txctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);\n\tif ((tsync_txctl & E1000_TSYNCTXCTL_VALID) == 0)\n\t\treturn -EINVAL;\n\n\ttx_stmpl = E1000_READ_REG(hw, E1000_TXSTMPL);\n\ttx_stmph = E1000_READ_REG(hw, E1000_TXSTMPH);\n\n\ttimestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);\n\ttimestamp->tv_nsec = 0;\n\n\treturn 0;\n}\n\nstatic int\neth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)\n{\n\tint count = 0;\n\tint g_ind = 0;\n\tconst struct reg_info *reg_group;\n\n\twhile ((reg_group = igb_regs[g_ind++]))\n\t\tcount += igb_reg_group_count(reg_group);\n\n\treturn count;\n}\n\nstatic int\nigbvf_get_reg_length(struct rte_eth_dev *dev __rte_unused)\n{\n\tint count = 0;\n\tint g_ind = 0;\n\tconst struct reg_info *reg_group;\n\n\twhile ((reg_group = igbvf_regs[g_ind++]))\n\t\tcount += igb_reg_group_count(reg_group);\n\n\treturn count;\n}\n\nstatic int\neth_igb_get_regs(struct rte_eth_dev *dev,\n\tstruct rte_dev_reg_info *regs)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t *data = regs->data;\n\tint g_ind = 0;\n\tint count = 0;\n\tconst struct reg_info *reg_group;\n\n\t/* Support only full register dump */\n\tif ((regs->length == 0) ||\n\t (regs->length == (uint32_t)eth_igb_get_reg_length(dev))) {\n\t\tregs->version = hw->mac.type << 24 | hw->revision_id << 16 |\n\t\t\thw->device_id;\n\t\twhile ((reg_group = igb_regs[g_ind++]))\n\t\t\tcount += igb_read_regs_group(dev, &data[count],\n\t\t\t\t\t\t\treg_group);\n\t\treturn 0;\n\t}\n\n\treturn -ENOTSUP;\n}\n\nstatic int\nigbvf_get_regs(struct rte_eth_dev *dev,\n\tstruct rte_dev_reg_info *regs)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t *data = regs->data;\n\tint g_ind = 0;\n\tint count = 0;\n\tconst struct reg_info *reg_group;\n\n\t/* Support only full register dump */\n\tif ((regs->length == 0) ||\n\t (regs->length == (uint32_t)igbvf_get_reg_length(dev))) {\n\t\tregs->version = hw->mac.type << 24 | hw->revision_id << 16 |\n\t\t\thw->device_id;\n\t\twhile ((reg_group = igbvf_regs[g_ind++]))\n\t\t\tcount += igb_read_regs_group(dev, &data[count],\n\t\t\t\t\t\t\treg_group);\n\t\treturn 0;\n\t}\n\n\treturn -ENOTSUP;\n}\n\nstatic int\neth_igb_get_eeprom_length(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/* Return unit is byte count */\n\treturn hw->nvm.word_size * 2;\n}\n\nstatic int\neth_igb_get_eeprom(struct rte_eth_dev *dev,\n\tstruct rte_dev_eeprom_info *in_eeprom)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tuint16_t *data = in_eeprom->data;\n\tint first, length;\n\n\tfirst = in_eeprom->offset >> 1;\n\tlength = in_eeprom->length >> 1;\n\tif ((first >= hw->nvm.word_size) ||\n\t ((first + length) >= hw->nvm.word_size))\n\t\treturn -EINVAL;\n\n\tin_eeprom->magic = hw->vendor_id |\n\t\t((uint32_t)hw->device_id << 16);\n\n\tif ((nvm->ops.read) == NULL)\n\t\treturn -ENOTSUP;\n\n\treturn nvm->ops.read(hw, first, length, data);\n}\n\nstatic int\neth_igb_set_eeprom(struct rte_eth_dev *dev,\n\tstruct rte_dev_eeprom_info *in_eeprom)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tuint16_t *data = in_eeprom->data;\n\tint first, length;\n\n\tfirst = in_eeprom->offset >> 1;\n\tlength = in_eeprom->length >> 1;\n\tif ((first >= hw->nvm.word_size) ||\n\t ((first + length) >= hw->nvm.word_size))\n\t\treturn -EINVAL;\n\n\tin_eeprom->magic = (uint32_t)hw->vendor_id |\n\t\t((uint32_t)hw->device_id << 16);\n\n\tif ((nvm->ops.write) == NULL)\n\t\treturn -ENOTSUP;\n\treturn nvm->ops.write(hw, first, length, data);\n}\n\nstatic struct rte_driver pmd_igb_drv = {\n\t.type = PMD_PDEV,\n\t.init = rte_igb_pmd_init,\n};\n\nstatic struct rte_driver pmd_igbvf_drv = {\n\t.type = PMD_PDEV,\n\t.init = rte_igbvf_pmd_init,\n};\n\n#ifdef RTE_NEXT_ABI\nstatic int\neth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t mask = 1 << queue_id;\n\n\tE1000_WRITE_REG(hw, E1000_EIMC, mask);\n\tE1000_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\nstatic int\neth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t mask = 1 << queue_id;\n\tuint32_t regval;\n\n\tregval = E1000_READ_REG(hw, E1000_EIMS);\n\tE1000_WRITE_REG(hw, E1000_EIMS, regval | mask);\n\tE1000_WRITE_FLUSH(hw);\n\n\trte_intr_enable(&dev->pci_dev->intr_handle);\n\n\treturn 0;\n}\n\nstatic void\neth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,\n\t\t uint8_t index, uint8_t offset)\n{\n\tuint32_t val = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);\n\n\t/* clear bits */\n\tval &= ~((uint32_t)0xFF << offset);\n\n\t/* write vector and valid bit */\n\tval |= (msix_vector | E1000_IVAR_VALID) << offset;\n\n\tE1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, val);\n}\n\nstatic void\neth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,\n\t\t\t uint8_t queue, uint8_t msix_vector)\n{\n\tuint32_t tmp = 0;\n\n\tif (hw->mac.type == e1000_82575) {\n\t\tif (direction == 0)\n\t\t\ttmp = E1000_EICR_RX_QUEUE0 << queue;\n\t\telse if (direction == 1)\n\t\t\ttmp = E1000_EICR_TX_QUEUE0 << queue;\n\t\tE1000_WRITE_REG(hw, E1000_MSIXBM(msix_vector), tmp);\n\t} else if (hw->mac.type == e1000_82576) {\n\t\tif ((direction == 0) || (direction == 1))\n\t\t\teth_igb_write_ivar(hw, msix_vector, queue & 0x7,\n\t\t\t\t\t ((queue & 0x8) << 1) +\n\t\t\t\t\t 8 * direction);\n\t} else if ((hw->mac.type == e1000_82580) ||\n\t\t\t(hw->mac.type == e1000_i350) ||\n\t\t\t(hw->mac.type == e1000_i354) ||\n\t\t\t(hw->mac.type == e1000_i210) ||\n\t\t\t(hw->mac.type == e1000_i211)) {\n\t\tif ((direction == 0) || (direction == 1))\n\t\t\teth_igb_write_ivar(hw, msix_vector,\n\t\t\t\t\t queue >> 1,\n\t\t\t\t\t ((queue & 0x1) << 4) +\n\t\t\t\t\t 8 * direction);\n\t}\n}\n#endif\n\n/* Sets up the hardware to generate MSI-X interrupts properly\n * @hw\n * board private structure\n */\nstatic void\neth_igb_configure_msix_intr(struct rte_eth_dev *dev)\n{\n#ifdef RTE_NEXT_ABI\n\tint queue_id;\n\tuint32_t tmpval, regval, intr_mask;\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t vec = 0;\n#endif\n\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n\n\t/* won't configure msix register if no mapping is done\n\t * between intr vector and event fd\n\t */\n\tif (!rte_intr_dp_is_en(intr_handle))\n\t\treturn;\n\n#ifdef RTE_NEXT_ABI\n\t/* set interrupt vector for other causes */\n\tif (hw->mac.type == e1000_82575) {\n\t\ttmpval = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\t/* enable MSI-X PBA support */\n\t\ttmpval |= E1000_CTRL_EXT_PBA_CLR;\n\n\t\t/* Auto-Mask interrupts upon ICR read */\n\t\ttmpval |= E1000_CTRL_EXT_EIAME;\n\t\ttmpval |= E1000_CTRL_EXT_IRCA;\n\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, tmpval);\n\n\t\t/* enable msix_other interrupt */\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), 0, E1000_EIMS_OTHER);\n\t\tregval = E1000_READ_REG(hw, E1000_EIAC);\n\t\tE1000_WRITE_REG(hw, E1000_EIAC, regval | E1000_EIMS_OTHER);\n\t\tregval = E1000_READ_REG(hw, E1000_EIAM);\n\t\tE1000_WRITE_REG(hw, E1000_EIMS, regval | E1000_EIMS_OTHER);\n\t} else if ((hw->mac.type == e1000_82576) ||\n\t\t\t(hw->mac.type == e1000_82580) ||\n\t\t\t(hw->mac.type == e1000_i350) ||\n\t\t\t(hw->mac.type == e1000_i354) ||\n\t\t\t(hw->mac.type == e1000_i210) ||\n\t\t\t(hw->mac.type == e1000_i211)) {\n\t\t/* turn on MSI-X capability first */\n\t\tE1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |\n\t\t\t\t\tE1000_GPIE_PBA | E1000_GPIE_EIAME |\n\t\t\t\t\tE1000_GPIE_NSICR);\n\n\t\tintr_mask = (1 << intr_handle->max_intr) - 1;\n\t\tregval = E1000_READ_REG(hw, E1000_EIAC);\n\t\tE1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask);\n\n\t\t/* enable msix_other interrupt */\n\t\tregval = E1000_READ_REG(hw, E1000_EIMS);\n\t\tE1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask);\n\t\ttmpval = (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8;\n\t\tE1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval);\n\t}\n\n\t/* use EIAM to auto-mask when MSI-X interrupt\n\t * is asserted, this saves a register write for every interrupt\n\t */\n\tintr_mask = (1 << intr_handle->nb_efd) - 1;\n\tregval = E1000_READ_REG(hw, E1000_EIAM);\n\tE1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask);\n\n\tfor (queue_id = 0; queue_id < dev->data->nb_rx_queues; queue_id++) {\n\t\teth_igb_assign_msix_vector(hw, 0, queue_id, vec);\n\t\tintr_handle->intr_vec[queue_id] = vec;\n\t\tif (vec < intr_handle->nb_efd - 1)\n\t\t\tvec++;\n\t}\n\n\tE1000_WRITE_FLUSH(hw);\n#endif\n}\n\nPMD_REGISTER_DRIVER(pmd_igb_drv);\nPMD_REGISTER_DRIVER(pmd_igbvf_drv);\n" }, { "path": "drivers/net/e1000/igb_pf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"base/e1000_defines.h\"\n#include \"base/e1000_regs.h\"\n#include \"base/e1000_hw.h\"\n#include \"e1000_ethdev.h\"\n\nstatic inline uint16_t\ndev_num_vf(struct rte_eth_dev *eth_dev)\n{\n\treturn eth_dev->pci_dev->max_vfs;\n}\n\nstatic inline\nint igb_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)\n{\n\tunsigned char vf_mac_addr[ETHER_ADDR_LEN];\n\tstruct e1000_vf_info *vfinfo =\n\t\t*E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);\n\tuint16_t vfn;\n\n\tfor (vfn = 0; vfn < vf_num; vfn++) {\n\t\teth_random_addr(vf_mac_addr);\n\t\t/* keep the random address as default */\n\t\tmemcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,\n\t\t\t\tETHER_ADDR_LEN);\n\t}\n\n\treturn 0;\n}\n\nstatic inline int\nigb_mb_intr_setup(struct rte_eth_dev *dev)\n{\n\tstruct e1000_interrupt *intr =\n\t\tE1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\tintr->mask |= E1000_ICR_VMMB;\n\n\treturn 0;\n}\n\nvoid igb_pf_host_init(struct rte_eth_dev *eth_dev)\n{\n\tstruct e1000_vf_info **vfinfo =\n\t\tE1000_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\tuint16_t vf_num;\n\tuint8_t nb_queue;\n\n\tRTE_ETH_DEV_SRIOV(eth_dev).active = 0;\n\tif (0 == (vf_num = dev_num_vf(eth_dev)))\n\t\treturn;\n\n\tif (hw->mac.type == e1000_i350)\n\t\tnb_queue = 1;\n\telse if(hw->mac.type == e1000_82576)\n\t\t/* per datasheet, it should be 2, but 1 seems correct */\n\t\tnb_queue = 1;\n\telse\n\t\treturn;\n\n\t*vfinfo = rte_zmalloc(\"vf_info\", sizeof(struct e1000_vf_info) * vf_num, 0);\n\tif (*vfinfo == NULL)\n\t\trte_panic(\"Cannot allocate memory for private VF data\\n\");\n\n\tRTE_ETH_DEV_SRIOV(eth_dev).active = ETH_8_POOLS;\n\tRTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;\n\tRTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;\n\tRTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);\n\n\tigb_vf_perm_addr_gen(eth_dev, vf_num);\n\n\t/* set mb interrupt mask */\n\tigb_mb_intr_setup(eth_dev);\n\n\treturn;\n}\n\nvoid igb_pf_host_uninit(struct rte_eth_dev *dev)\n{\n\tstruct e1000_vf_info **vfinfo;\n\tuint16_t vf_num;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tvfinfo = E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);\n\n\tRTE_ETH_DEV_SRIOV(dev).active = 0;\n\tRTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 0;\n\tRTE_ETH_DEV_SRIOV(dev).def_vmdq_idx = 0;\n\tRTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 0;\n\n\tvf_num = dev_num_vf(dev);\n\tif (vf_num == 0)\n\t\treturn;\n\n\trte_free(*vfinfo);\n\t*vfinfo = NULL;\n}\n\n#define E1000_RAH_POOLSEL_SHIFT (18)\nint igb_pf_host_configure(struct rte_eth_dev *eth_dev)\n{\n\tuint32_t vtctl;\n\tuint16_t vf_num;\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\tuint32_t vlanctrl;\n\tint i;\n\tuint32_t rah;\n\n\tif (0 == (vf_num = dev_num_vf(eth_dev)))\n\t\treturn -1;\n\n\t/* enable VMDq and set the default pool for PF */\n\tvtctl = E1000_READ_REG(hw, E1000_VT_CTL);\n\tvtctl &= ~E1000_VT_CTL_DEFAULT_POOL_MASK;\n\tvtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx\n\t\t<< E1000_VT_CTL_DEFAULT_POOL_SHIFT;\n\tvtctl |= E1000_VT_CTL_VM_REPL_EN;\n\tE1000_WRITE_REG(hw, E1000_VT_CTL, vtctl);\n\n\t/* Enable pools reserved to PF only */\n\tE1000_WRITE_REG(hw, E1000_VFRE, (~0) << vf_num);\n\tE1000_WRITE_REG(hw, E1000_VFTE, (~0) << vf_num);\n\n\t/* PFDMA Tx General Switch Control Enables VMDQ loopback */\n\tif (hw->mac.type == e1000_i350)\n\t\tE1000_WRITE_REG(hw, E1000_TXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN);\n\telse\n\t\tE1000_WRITE_REG(hw, E1000_DTXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN);\n\n\t/* clear VMDq map to perment rar 0 */\n\trah = E1000_READ_REG(hw, E1000_RAH(0));\n\trah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT);\n\tE1000_WRITE_REG(hw, E1000_RAH(0), rah);\n\n\t/* clear VMDq map to scan rar 32 */\n\trah = E1000_READ_REG(hw, E1000_RAH(hw->mac.rar_entry_count));\n\trah &= ~ (0xFF << E1000_RAH_POOLSEL_SHIFT);\n\tE1000_WRITE_REG(hw, E1000_RAH(hw->mac.rar_entry_count), rah);\n\n\t/* set VMDq map to default PF pool */\n\trah = E1000_READ_REG(hw, E1000_RAH(0));\n\trah |= (0x1 << (RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx +\n\t\t\tE1000_RAH_POOLSEL_SHIFT));\n\tE1000_WRITE_REG(hw, E1000_RAH(0), rah);\n\n\t/*\n\t * enable vlan filtering and allow all vlan tags through\n\t */\n\tvlanctrl = E1000_READ_REG(hw, E1000_RCTL);\n\tvlanctrl |= E1000_RCTL_VFE ; /* enable vlan filters */\n\tE1000_WRITE_REG(hw, E1000_RCTL, vlanctrl);\n\n\t/* VFTA - enable all vlan filters */\n\tfor (i = 0; i < IGB_VFTA_SIZE; i++) {\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, 0xFFFFFFFF);\n\t}\n\n\t/* Enable/Disable MAC Anti-Spoofing */\n\te1000_vmdq_set_anti_spoofing_pf(hw, FALSE, vf_num);\n\n\treturn 0;\n}\n\nstatic void\nset_rx_mode(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_dev_data *dev_data =\n\t\t(struct rte_eth_dev_data*)dev->data->dev_private;\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t fctrl, vmolr = E1000_VMOLR_BAM | E1000_VMOLR_AUPE;\n\tuint16_t vfn = dev_num_vf(dev);\n\n\t/* Check for Promiscuous and All Multicast modes */\n\tfctrl = E1000_READ_REG(hw, E1000_RCTL);\n\n\t/* set all bits that we expect to always be set */\n\tfctrl &= ~E1000_RCTL_SBP; /* disable store-bad-packets */\n\tfctrl |= E1000_RCTL_BAM;;\n\n\t/* clear the bits we are changing the status of */\n\tfctrl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);\n\n\tif (dev_data->promiscuous) {\n\t\tfctrl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);\n\t\tvmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);\n\t} else {\n\t\tif (dev_data->all_multicast) {\n\t\t\tfctrl |= E1000_RCTL_MPE;\n\t\t\tvmolr |= E1000_VMOLR_MPME;\n\t\t} else {\n\t\t\tvmolr |= E1000_VMOLR_ROMPE;\n\t\t}\n\t}\n\n\tif ((hw->mac.type == e1000_82576) ||\n\t\t(hw->mac.type == e1000_i350)) {\n\t\tvmolr |= E1000_READ_REG(hw, E1000_VMOLR(vfn)) &\n\t\t\t ~(E1000_VMOLR_MPME | E1000_VMOLR_ROMPE |\n\t\t\t E1000_VMOLR_ROPE);\n\t\tE1000_WRITE_REG(hw, E1000_VMOLR(vfn), vmolr);\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_RCTL, fctrl);\n}\n\nstatic inline void\nigb_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_vf_info *vfinfo =\n\t\t*(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));\n\tuint32_t vmolr = E1000_READ_REG(hw, E1000_VMOLR(vf));\n\n\tvmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE |\n\t\t\tE1000_VMOLR_BAM | E1000_VMOLR_AUPE);\n\tE1000_WRITE_REG(hw, E1000_VMOLR(vf), vmolr);\n\n\tE1000_WRITE_REG(hw, E1000_VMVIR(vf), 0);\n\n\t/* reset multicast table array for vf */\n\tvfinfo[vf].num_vf_mc_hashes = 0;\n\n\t/* reset rx mode */\n\tset_rx_mode(dev);\n}\n\nstatic inline void\nigb_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t reg;\n\n\t/* enable transmit and receive for vf */\n\treg = E1000_READ_REG(hw, E1000_VFTE);\n\treg |= (reg | (1 << vf));\n\tE1000_WRITE_REG(hw, E1000_VFTE, reg);\n\n\treg = E1000_READ_REG(hw, E1000_VFRE);\n\treg |= (reg | (1 << vf));\n\tE1000_WRITE_REG(hw, E1000_VFRE, reg);\n\n\tigb_vf_reset_event(dev, vf);\n}\n\nstatic int\nigb_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_vf_info *vfinfo =\n\t\t*(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));\n\tunsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;\n\tint rar_entry = hw->mac.rar_entry_count - (vf + 1);\n\tuint8_t *new_mac = (uint8_t *)(&msgbuf[1]);\n\tuint32_t rah;\n\n\tigb_vf_reset_msg(dev, vf);\n\n\thw->mac.ops.rar_set(hw, vf_mac, rar_entry);\n\trah = E1000_READ_REG(hw, E1000_RAH(rar_entry));\n\trah |= (0x1 << (vf + E1000_RAH_POOLSEL_SHIFT));\n\tE1000_WRITE_REG(hw, E1000_RAH(rar_entry), rah);\n\n\t/* reply to reset with ack and vf mac address */\n\tmsgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;\n\trte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);\n\te1000_write_mbx(hw, msgbuf, 3, vf);\n\n\treturn 0;\n}\n\nstatic int\nigb_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_vf_info *vfinfo =\n\t\t*(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));\n\tint rar_entry = hw->mac.rar_entry_count - (vf + 1);\n\tuint8_t *new_mac = (uint8_t *)(&msgbuf[1]);\n\n\tif (is_valid_assigned_ether_addr((struct ether_addr*)new_mac)) {\n\t\trte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);\n\t\thw->mac.ops.rar_set(hw, new_mac, rar_entry);\n\t\treturn 0;\n\t}\n\treturn -1;\n}\n\nstatic int\nigb_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)\n{\n\tint i;\n\tuint32_t vector_bit;\n\tuint32_t vector_reg;\n\tuint32_t mta_reg;\n\tint entries = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >>\n\t\tE1000_VT_MSGINFO_SHIFT;\n\tuint16_t *hash_list = (uint16_t *)&msgbuf[1];\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_vf_info *vfinfo =\n\t\t*(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));\n\n\t/* only so many hash values supported */\n\tentries = RTE_MIN(entries, E1000_MAX_VF_MC_ENTRIES);\n\n\t/*\n\t * salt away the number of multi cast addresses assigned\n\t * to this VF for later use to restore when the PF multi cast\n\t * list changes\n\t */\n\tvfinfo->num_vf_mc_hashes = (uint16_t)entries;\n\n\t/*\n\t * VFs are limited to using the MTA hash table for their multicast\n\t * addresses\n\t */\n\tfor (i = 0; i < entries; i++) {\n\t\tvfinfo->vf_mc_hashes[i] = hash_list[i];\n\t}\n\n\tfor (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {\n\t\tvector_reg = (vfinfo->vf_mc_hashes[i] >> 5) & 0x7F;\n\t\tvector_bit = vfinfo->vf_mc_hashes[i] & 0x1F;\n\t\tmta_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, vector_reg);\n\t\tmta_reg |= (1 << vector_bit);\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, vector_reg, mta_reg);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nigb_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)\n{\n\tint add, vid;\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct e1000_vf_info *vfinfo =\n\t\t*(E1000_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));\n\tuint32_t vid_idx, vid_bit, vfta;\n\n\tadd = (msgbuf[0] & E1000_VT_MSGINFO_MASK)\n\t\t>> E1000_VT_MSGINFO_SHIFT;\n\tvid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);\n\n\tif (add)\n\t\tvfinfo[vf].vlan_count++;\n\telse if (vfinfo[vf].vlan_count)\n\t\tvfinfo[vf].vlan_count--;\n\n\tvid_idx = (uint32_t)((vid >> E1000_VFTA_ENTRY_SHIFT) &\n\t\t\t E1000_VFTA_ENTRY_MASK);\n\tvid_bit = (uint32_t)(1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));\n\tvfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);\n\tif (add)\n\t\tvfta |= vid_bit;\n\telse\n\t\tvfta &= ~vid_bit;\n\n\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);\n\tE1000_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\nstatic int\nigb_vf_set_rlpml(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)\n{\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint16_t rlpml = msgbuf[1] & E1000_VMOLR_RLPML_MASK;\n\tuint32_t max_frame = rlpml + ETHER_HDR_LEN + ETHER_CRC_LEN;\n\tuint32_t vmolr;\n\n\tif ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))\n\t\treturn -1;\n\n\tvmolr = E1000_READ_REG(hw, E1000_VMOLR(vf));\n\n\tvmolr &= ~E1000_VMOLR_RLPML_MASK;\n\tvmolr |= rlpml;\n\n\t/* Enable Long Packet support */\n\tvmolr |= E1000_VMOLR_LPE;\n\n\tE1000_WRITE_REG(hw, E1000_VMOLR(vf), vmolr);\n\tE1000_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\nstatic int\nigb_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)\n{\n\tuint16_t mbx_size = E1000_VFMAILBOX_SIZE;\n\tuint32_t msgbuf[E1000_VFMAILBOX_SIZE];\n\tint32_t retval;\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tretval = e1000_read_mbx(hw, msgbuf, mbx_size, vf);\n\tif (retval) {\n\t\tPMD_INIT_LOG(ERR, \"Error mbx recv msg from VF %d\", vf);\n\t\treturn retval;\n\t}\n\n\t/* do nothing with the message already processed */\n\tif (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))\n\t\treturn retval;\n\n\t/* flush the ack before we write any messages back */\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* perform VF reset */\n\tif (msgbuf[0] == E1000_VF_RESET) {\n\t\treturn igb_vf_reset(dev, vf, msgbuf);\n\t}\n\n\t/* check & process VF to PF mailbox message */\n\tswitch ((msgbuf[0] & 0xFFFF)) {\n\tcase E1000_VF_SET_MAC_ADDR:\n\t\tretval = igb_vf_set_mac_addr(dev, vf, msgbuf);\n\t\tbreak;\n\tcase E1000_VF_SET_MULTICAST:\n\t\tretval = igb_vf_set_multicast(dev, vf, msgbuf);\n\t\tbreak;\n\tcase E1000_VF_SET_LPE:\n\t\tretval = igb_vf_set_rlpml(dev, vf, msgbuf);\n\t\tbreak;\n\tcase E1000_VF_SET_VLAN:\n\t\tretval = igb_vf_set_vlan(dev, vf, msgbuf);\n\t\tbreak;\n\tdefault:\n\t\tPMD_INIT_LOG(DEBUG, \"Unhandled Msg %8.8x\",\n\t\t\t (unsigned) msgbuf[0]);\n\t\tretval = E1000_ERR_MBX;\n\t\tbreak;\n\t}\n\n\t/* response the VF according to the message process result */\n\tif (retval)\n\t\tmsgbuf[0] |= E1000_VT_MSGTYPE_NACK;\n\telse\n\t\tmsgbuf[0] |= E1000_VT_MSGTYPE_ACK;\n\n\tmsgbuf[0] |= E1000_VT_MSGTYPE_CTS;\n\n\te1000_write_mbx(hw, msgbuf, 1, vf);\n\n\treturn retval;\n}\n\nstatic inline void\nigb_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)\n{\n\tuint32_t msg = E1000_VT_MSGTYPE_NACK;\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\te1000_write_mbx(hw, &msg, 1, vf);\n}\n\nvoid igb_pf_mbx_process(struct rte_eth_dev *eth_dev)\n{\n\tuint16_t vf;\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\n\tfor (vf = 0; vf < dev_num_vf(eth_dev); vf++) {\n\t\t/* check & process vf function level reset */\n\t\tif (!e1000_check_for_rst(hw, vf))\n\t\t\tigb_vf_reset_event(eth_dev, vf);\n\n\t\t/* check & process vf mailbox messages */\n\t\tif (!e1000_check_for_msg(hw, vf))\n\t\t\tigb_rcv_msg_from_vf(eth_dev, vf);\n\n\t\t/* check & process acks from vf */\n\t\tif (!e1000_check_for_ack(hw, vf))\n\t\t\tigb_rcv_ack_from_vf(eth_dev, vf);\n\t}\n}\n" }, { "path": "drivers/net/e1000/igb_regs.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef _IGB_REGS_H_\n#define _IGB_REGS_H_\n\n#include \"e1000_ethdev.h\"\n\nstruct reg_info {\n\tuint32_t base_addr;\n\tuint32_t count;\n\tuint32_t stride;\n\tconst char *name;\n};\n\nstatic const struct reg_info igb_regs_general[] = {\n\t{E1000_CTRL, 1, 1, \"E1000_CTRL\"},\n\t{E1000_STATUS, 1, 1, \"E1000_STATUS\"},\n\t{E1000_CTRL_EXT, 1, 1, \"E1000_CTRL_EXT\"},\n\t{E1000_MDIC, 1, 1, \"E1000_MDIC\"},\n\t{E1000_SCTL, 1, 1, \"E1000_SCTL\"},\n\t{E1000_CONNSW, 1, 1, \"E1000_CONNSW\"},\n\t{E1000_VET, 1, 1, \"E1000_VET\"},\n\t{E1000_LEDCTL, 1, 1, \"E1000_LEDCTL\"},\n\t{E1000_PBA, 1, 1, \"E1000_PBA\"},\n\t{E1000_PBS, 1, 1, \"E1000_PBS\"},\n\t{E1000_FRTIMER, 1, 1, \"E1000_FRTIMER\"},\n\t{E1000_TCPTIMER, 1, 1, \"E1000_TCPTIMER\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info igb_regs_nvm[] = {\n\t{E1000_EECD, 1, 1, \"E1000_EECD\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info igb_regs_interrupt[] = {\n\t{E1000_EICS, 1, 1, \"E1000_EICS\"},\n\t{E1000_EIMS, 1, 1, \"E1000_EIMS\"},\n\t{E1000_EIMC, 1, 1, \"E1000_EIMC\"},\n\t{E1000_EIAC, 1, 1, \"E1000_EIAC\"},\n\t{E1000_EIAM, 1, 1, \"E1000_EIAM\"},\n\t{E1000_ICS, 1, 1, \"E1000_ICS\"},\n\t{E1000_IMS, 1, 1, \"E1000_IMS\"},\n\t{E1000_IMC, 1, 1, \"E1000_IMC\"},\n\t{E1000_IAC, 1, 1, \"E1000_IAC\"},\n\t{E1000_IAM, 1, 1, \"E1000_IAM\"},\n\t{E1000_IMIRVP, 1, 1, \"E1000_IMIRVP\"},\n\t{E1000_EITR(0), 10, 4, \"E1000_EITR\"},\n\t{E1000_IMIR(0), 8, 4, \"E1000_IMIR\"},\n\t{E1000_IMIREXT(0), 8, 4, \"E1000_IMIREXT\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info igb_regs_fctl[] = {\n\t{E1000_FCAL, 1, 1, \"E1000_FCAL\"},\n\t{E1000_FCAH, 1, 1, \"E1000_FCAH\"},\n\t{E1000_FCTTV, 1, 1, \"E1000_FCTTV\"},\n\t{E1000_FCRTL, 1, 1, \"E1000_FCRTL\"},\n\t{E1000_FCRTH, 1, 1, \"E1000_FCRTH\"},\n\t{E1000_FCRTV, 1, 1, \"E1000_FCRTV\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info igb_regs_rxdma[] = {\n\t{E1000_RDBAL(0), 4, 0x100, \"E1000_RDBAL\"},\n\t{E1000_RDBAH(0), 4, 0x100, \"E1000_RDBAH\"},\n\t{E1000_RDLEN(0), 4, 0x100, \"E1000_RDLEN\"},\n\t{E1000_RDH(0), 4, 0x100, \"E1000_RDH\"},\n\t{E1000_RDT(0), 4, 0x100, \"E1000_RDT\"},\n\t{E1000_RXCTL(0), 4, 0x100, \"E1000_RXCTL\"},\n\t{E1000_SRRCTL(0), 4, 0x100, \"E1000_SRRCTL\"},\n\t{E1000_DCA_RXCTRL(0), 4, 0x100, \"E1000_DCA_RXCTRL\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info igb_regs_rx[] = {\n\t{E1000_RCTL, 1, 1, \"E1000_RCTL\"},\n\t{E1000_RXCSUM, 1, 1, \"E1000_RXCSUM\"},\n\t{E1000_RLPML, 1, 1, \"E1000_RLPML\"},\n\t{E1000_RFCTL, 1, 1, \"E1000_RFCTL\"},\n\t{E1000_MRQC, 1, 1, \"E1000_MRQC\"},\n\t{E1000_VT_CTL, 1, 1, \"E1000_VT_CTL\"},\n\t{E1000_RAL(0), 16, 8, \"E1000_RAL\"},\n\t{E1000_RAH(0), 16, 8, \"E1000_RAH\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info igb_regs_tx[] = {\n\t{E1000_TCTL, 1, 1, \"E1000_TCTL\"},\n\t{E1000_TCTL_EXT, 1, 1, \"E1000_TCTL_EXT\"},\n\t{E1000_TIPG, 1, 1, \"E1000_TIPG\"},\n\t{E1000_DTXCTL, 1, 1, \"E1000_DTXCTL\"},\n\t{E1000_TDBAL(0), 4, 0x100, \"E1000_TDBAL\"},\n\t{E1000_TDBAH(0), 4, 0x100, \"E1000_TDBAH\"},\n\t{E1000_TDLEN(0), 4, 0x100, \"E1000_TDLEN\"},\n\t{E1000_TDH(0), 4, 0x100, \"E1000_TDLEN\"},\n\t{E1000_TDT(0), 4, 0x100, \"E1000_TDT\"},\n\t{E1000_TXDCTL(0), 4, 0x100, \"E1000_TXDCTL\"},\n\t{E1000_TDWBAL(0), 4, 0x100, \"E1000_TDWBAL\"},\n\t{E1000_TDWBAH(0), 4, 0x100, \"E1000_TDWBAH\"},\n\t{E1000_DCA_TXCTRL(0), 4, 0x100, \"E1000_DCA_TXCTRL\"},\n\t{E1000_TDFH, 1, 1, \"E1000_TDFH\"},\n\t{E1000_TDFT, 1, 1, \"E1000_TDFT\"},\n\t{E1000_TDFHS, 1, 1, \"E1000_TDFHS\"},\n\t{E1000_TDFPC, 1, 1, \"E1000_TDFPC\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info igb_regs_wakeup[] = {\n\t{E1000_WUC, 1, 1, \"E1000_WUC\"},\n\t{E1000_WUFC, 1, 1, \"E1000_WUFC\"},\n\t{E1000_WUS, 1, 1, \"E1000_WUS\"},\n\t{E1000_IPAV, 1, 1, \"E1000_IPAV\"},\n\t{E1000_WUPL, 1, 1, \"E1000_WUPL\"},\n\t{E1000_IP4AT_REG(0), 4, 8, \"E1000_IP4AT_REG\"},\n\t{E1000_IP6AT_REG(0), 4, 4, \"E1000_IP6AT_REG\"},\n\t{E1000_WUPM_REG(0), 4, 4, \"E1000_WUPM_REG\"},\n\t{E1000_FFMT_REG(0), 4, 8, \"E1000_FFMT_REG\"},\n\t{E1000_FFVT_REG(0), 4, 8, \"E1000_FFVT_REG\"},\n\t{E1000_FFLT_REG(0), 4, 8, \"E1000_FFLT_REG\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info igb_regs_mac[] = {\n\t{E1000_PCS_CFG0, 1, 1, \"E1000_PCS_CFG0\"},\n\t{E1000_PCS_LCTL, 1, 1, \"E1000_PCS_LCTL\"},\n\t{E1000_PCS_LSTAT, 1, 1, \"E1000_PCS_LSTAT\"},\n\t{E1000_PCS_ANADV, 1, 1, \"E1000_PCS_ANADV\"},\n\t{E1000_PCS_LPAB, 1, 1, \"E1000_PCS_LPAB\"},\n\t{E1000_PCS_NPTX, 1, 1, \"E1000_PCS_NPTX\"},\n\t{E1000_PCS_LPABNP, 1, 1, \"E1000_PCS_LPABNP\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info *igb_regs[] = {\n\t\t\t\tigb_regs_general,\n\t\t\t\tigb_regs_nvm,\n\t\t\t\tigb_regs_interrupt,\n\t\t\t\tigb_regs_fctl,\n\t\t\t\tigb_regs_rxdma,\n\t\t\t\tigb_regs_rx,\n\t\t\t\tigb_regs_tx,\n\t\t\t\tigb_regs_wakeup,\n\t\t\t\tigb_regs_mac,\n\t\t\t\tNULL};\n\n/* FIXME: reading igb_regs_interrupt results side-effect which doesn't\n * work with VFIO; re-install igb_regs_interrupt once issue is resolved.\n */\nstatic const struct reg_info *igbvf_regs[] = {\n\t\t\t\tigb_regs_general,\n\t\t\t\tigb_regs_rxdma,\n\t\t\t\tigb_regs_tx,\n\t\t\t\tNULL};\n\nstatic inline int\nigb_read_regs(struct e1000_hw *hw, const struct reg_info *reg,\n\tuint32_t *reg_buf)\n{\n\tunsigned int i;\n\n\tfor (i = 0; i < reg->count; i++) {\n\t\treg_buf[i] = E1000_READ_REG(hw,\n\t\t\t\treg->base_addr + i * reg->stride);\n\t}\n\treturn reg->count;\n};\n\nstatic inline int\nigb_reg_group_count(const struct reg_info *regs)\n{\n\tint count = 0;\n\tint i = 0;\n\n\twhile (regs[i].count)\n\t\tcount += regs[i++].count;\n\treturn count;\n};\n\nstatic inline int\nigb_read_regs_group(struct rte_eth_dev *dev, uint32_t *reg_buf,\n\t\tconst struct reg_info *regs)\n{\n\tint count = 0;\n\tint i = 0;\n\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\twhile (regs[i].count)\n\t\tcount += igb_read_regs(hw, ®s[i++], ®_buf[count]);\n\treturn count;\n};\n\n#endif /* _IGB_REGS_H_ */\n" }, { "path": "drivers/net/e1000/igb_rxtx.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"e1000_logs.h\"\n#include \"base/e1000_api.h\"\n#include \"e1000_ethdev.h\"\n\n/* Bit Mask to indicate what bits required for building TX context */\n#define IGB_TX_OFFLOAD_MASK (\t\t\t \\\n\t\tPKT_TX_VLAN_PKT |\t\t \\\n\t\tPKT_TX_IP_CKSUM |\t\t \\\n\t\tPKT_TX_L4_MASK)\n\nstatic inline struct rte_mbuf *\nrte_rxmbuf_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\n\tm = __rte_mbuf_raw_alloc(mp);\n\t__rte_mbuf_sanity_check_raw(m, 0);\n\treturn (m);\n}\n\n#define RTE_MBUF_DATA_DMA_ADDR(mb) \\\n\t(uint64_t) ((mb)->buf_physaddr + (mb)->data_off)\n\n#define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \\\n\t(uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)\n\n/**\n * Structure associated with each descriptor of the RX ring of a RX queue.\n */\nstruct igb_rx_entry {\n\tstruct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */\n};\n\n/**\n * Structure associated with each descriptor of the TX ring of a TX queue.\n */\nstruct igb_tx_entry {\n\tstruct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */\n\tuint16_t next_id; /**< Index of next descriptor in ring. */\n\tuint16_t last_id; /**< Index of last scattered descriptor. */\n};\n\n/**\n * Structure associated with each RX queue.\n */\nstruct igb_rx_queue {\n\tstruct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */\n\tvolatile union e1000_adv_rx_desc *rx_ring; /**< RX ring virtual address. */\n\tuint64_t rx_ring_phys_addr; /**< RX ring DMA address. */\n\tvolatile uint32_t *rdt_reg_addr; /**< RDT register address. */\n\tvolatile uint32_t *rdh_reg_addr; /**< RDH register address. */\n\tstruct igb_rx_entry *sw_ring; /**< address of RX software ring. */\n\tstruct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */\n\tstruct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */\n\tuint16_t nb_rx_desc; /**< number of RX descriptors. */\n\tuint16_t rx_tail; /**< current value of RDT register. */\n\tuint16_t nb_rx_hold; /**< number of held free RX desc. */\n\tuint16_t rx_free_thresh; /**< max free RX desc to hold. */\n\tuint16_t queue_id; /**< RX queue index. */\n\tuint16_t reg_idx; /**< RX queue register index. */\n\tuint8_t port_id; /**< Device port identifier. */\n\tuint8_t pthresh; /**< Prefetch threshold register. */\n\tuint8_t hthresh; /**< Host threshold register. */\n\tuint8_t wthresh; /**< Write-back threshold register. */\n\tuint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */\n\tuint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */\n};\n\n/**\n * Hardware context number\n */\nenum igb_advctx_num {\n\tIGB_CTX_0 = 0, /**< CTX0 */\n\tIGB_CTX_1 = 1, /**< CTX1 */\n\tIGB_CTX_NUM = 2, /**< CTX_NUM */\n};\n\n/** Offload features */\nunion igb_vlan_macip {\n\tuint32_t data;\n\tstruct {\n\t\tuint16_t l2_l3_len; /**< 7bit L2 and 9b L3 lengths combined */\n\t\tuint16_t vlan_tci;\n\t\t/**< VLAN Tag Control Identifier (CPU order). */\n\t} f;\n};\n\n/*\n * Compare mask for vlan_macip_len.data,\n * should be in sync with igb_vlan_macip.f layout.\n * */\n#define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */\n#define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */\n#define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */\n/** MAC+IP length. */\n#define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)\n\n/**\n * Strucutre to check if new context need be built\n */\nstruct igb_advctx_info {\n\tuint64_t flags; /**< ol_flags related to context build. */\n\tuint32_t cmp_mask; /**< compare mask for vlan_macip_lens */\n\tunion igb_vlan_macip vlan_macip_lens; /**< vlan, mac & ip length. */\n};\n\n/**\n * Structure associated with each TX queue.\n */\nstruct igb_tx_queue {\n\tvolatile union e1000_adv_tx_desc *tx_ring; /**< TX ring address */\n\tuint64_t tx_ring_phys_addr; /**< TX ring DMA address. */\n\tstruct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */\n\tvolatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */\n\tuint32_t txd_type; /**< Device-specific TXD type */\n\tuint16_t nb_tx_desc; /**< number of TX descriptors. */\n\tuint16_t tx_tail; /**< Current value of TDT register. */\n\tuint16_t tx_head;\n\t/**< Index of first used TX descriptor. */\n\tuint16_t queue_id; /**< TX queue index. */\n\tuint16_t reg_idx; /**< TX queue register index. */\n\tuint8_t port_id; /**< Device port identifier. */\n\tuint8_t pthresh; /**< Prefetch threshold register. */\n\tuint8_t hthresh; /**< Host threshold register. */\n\tuint8_t wthresh; /**< Write-back threshold register. */\n\tuint32_t ctx_curr;\n\t/**< Current used hardware descriptor. */\n\tuint32_t ctx_start;\n\t/**< Start context position for transmit queue. */\n\tstruct igb_advctx_info ctx_cache[IGB_CTX_NUM];\n\t/**< Hardware context history.*/\n};\n\n#if 1\n#define RTE_PMD_USE_PREFETCH\n#endif\n\n#ifdef RTE_PMD_USE_PREFETCH\n#define rte_igb_prefetch(p)\trte_prefetch0(p)\n#else\n#define rte_igb_prefetch(p)\tdo {} while(0)\n#endif\n\n#ifdef RTE_PMD_PACKET_PREFETCH\n#define rte_packet_prefetch(p) rte_prefetch1(p)\n#else\n#define rte_packet_prefetch(p)\tdo {} while(0)\n#endif\n\n/*\n * Macro for VMDq feature for 1 GbE NIC.\n */\n#define E1000_VMOLR_SIZE\t\t\t(8)\n\n/*********************************************************************\n *\n * TX function\n *\n **********************************************************************/\n\n/*\n * Advanced context descriptor are almost same between igb/ixgbe\n * This is a separate function, looking for optimization opportunity here\n * Rework required to go with the pre-defined values.\n */\n\nstatic inline void\nigbe_set_xmit_ctx(struct igb_tx_queue* txq,\n\t\tvolatile struct e1000_adv_tx_context_desc *ctx_txd,\n\t\tuint64_t ol_flags, uint32_t vlan_macip_lens)\n{\n\tuint32_t type_tucmd_mlhl;\n\tuint32_t mss_l4len_idx;\n\tuint32_t ctx_idx, ctx_curr;\n\tuint32_t cmp_mask;\n\n\tctx_curr = txq->ctx_curr;\n\tctx_idx = ctx_curr + txq->ctx_start;\n\n\tcmp_mask = 0;\n\ttype_tucmd_mlhl = 0;\n\n\tif (ol_flags & PKT_TX_VLAN_PKT) {\n\t\tcmp_mask |= TX_VLAN_CMP_MASK;\n\t}\n\n\tif (ol_flags & PKT_TX_IP_CKSUM) {\n\t\ttype_tucmd_mlhl = E1000_ADVTXD_TUCMD_IPV4;\n\t\tcmp_mask |= TX_MACIP_LEN_CMP_MASK;\n\t}\n\n\t/* Specify which HW CTX to upload. */\n\tmss_l4len_idx = (ctx_idx << E1000_ADVTXD_IDX_SHIFT);\n\tswitch (ol_flags & PKT_TX_L4_MASK) {\n\tcase PKT_TX_UDP_CKSUM:\n\t\ttype_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP |\n\t\t\t\tE1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;\n\t\tmss_l4len_idx |= sizeof(struct udp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;\n\t\tcmp_mask |= TX_MACIP_LEN_CMP_MASK;\n\t\tbreak;\n\tcase PKT_TX_TCP_CKSUM:\n\t\ttype_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP |\n\t\t\t\tE1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;\n\t\tmss_l4len_idx |= sizeof(struct tcp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;\n\t\tcmp_mask |= TX_MACIP_LEN_CMP_MASK;\n\t\tbreak;\n\tcase PKT_TX_SCTP_CKSUM:\n\t\ttype_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_SCTP |\n\t\t\t\tE1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;\n\t\tmss_l4len_idx |= sizeof(struct sctp_hdr) << E1000_ADVTXD_L4LEN_SHIFT;\n\t\tcmp_mask |= TX_MACIP_LEN_CMP_MASK;\n\t\tbreak;\n\tdefault:\n\t\ttype_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_RSV |\n\t\t\t\tE1000_ADVTXD_DTYP_CTXT | E1000_ADVTXD_DCMD_DEXT;\n\t\tbreak;\n\t}\n\n\ttxq->ctx_cache[ctx_curr].flags = ol_flags;\n\ttxq->ctx_cache[ctx_curr].cmp_mask = cmp_mask;\n\ttxq->ctx_cache[ctx_curr].vlan_macip_lens.data =\n\t\tvlan_macip_lens & cmp_mask;\n\n\tctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);\n\tctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);\n\tctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);\n\tctx_txd->seqnum_seed = 0;\n}\n\n/*\n * Check which hardware context can be used. Use the existing match\n * or create a new context descriptor.\n */\nstatic inline uint32_t\nwhat_advctx_update(struct igb_tx_queue *txq, uint64_t flags,\n\t\tuint32_t vlan_macip_lens)\n{\n\t/* If match with the current context */\n\tif (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&\n\t\t(txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==\n\t\t(txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {\n\t\t\treturn txq->ctx_curr;\n\t}\n\n\t/* If match with the second context */\n\ttxq->ctx_curr ^= 1;\n\tif (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&\n\t\t(txq->ctx_cache[txq->ctx_curr].vlan_macip_lens.data ==\n\t\t(txq->ctx_cache[txq->ctx_curr].cmp_mask & vlan_macip_lens)))) {\n\t\t\treturn txq->ctx_curr;\n\t}\n\n\t/* Mismatch, use the previous context */\n\treturn (IGB_CTX_NUM);\n}\n\nstatic inline uint32_t\ntx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)\n{\n\tstatic const uint32_t l4_olinfo[2] = {0, E1000_ADVTXD_POPTS_TXSM};\n\tstatic const uint32_t l3_olinfo[2] = {0, E1000_ADVTXD_POPTS_IXSM};\n\tuint32_t tmp;\n\n\ttmp = l4_olinfo[(ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM];\n\ttmp |= l3_olinfo[(ol_flags & PKT_TX_IP_CKSUM) != 0];\n\treturn tmp;\n}\n\nstatic inline uint32_t\ntx_desc_vlan_flags_to_cmdtype(uint64_t ol_flags)\n{\n\tstatic uint32_t vlan_cmd[2] = {0, E1000_ADVTXD_DCMD_VLE};\n\treturn vlan_cmd[(ol_flags & PKT_TX_VLAN_PKT) != 0];\n}\n\nuint16_t\neth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t uint16_t nb_pkts)\n{\n\tstruct igb_tx_queue *txq;\n\tstruct igb_tx_entry *sw_ring;\n\tstruct igb_tx_entry *txe, *txn;\n\tvolatile union e1000_adv_tx_desc *txr;\n\tvolatile union e1000_adv_tx_desc *txd;\n\tstruct rte_mbuf *tx_pkt;\n\tstruct rte_mbuf *m_seg;\n\tunion igb_vlan_macip vlan_macip_lens;\n\tunion {\n\t\tuint16_t u16;\n\t\tstruct {\n\t\t\tuint16_t l3_len:9;\n\t\t\tuint16_t l2_len:7;\n\t\t};\n\t} l2_l3_len;\n\tuint64_t buf_dma_addr;\n\tuint32_t olinfo_status;\n\tuint32_t cmd_type_len;\n\tuint32_t pkt_len;\n\tuint16_t slen;\n\tuint64_t ol_flags;\n\tuint16_t tx_end;\n\tuint16_t tx_id;\n\tuint16_t tx_last;\n\tuint16_t nb_tx;\n\tuint64_t tx_ol_req;\n\tuint32_t new_ctx = 0;\n\tuint32_t ctx = 0;\n\n\ttxq = tx_queue;\n\tsw_ring = txq->sw_ring;\n\ttxr = txq->tx_ring;\n\ttx_id = txq->tx_tail;\n\ttxe = &sw_ring[tx_id];\n\n\tfor (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {\n\t\ttx_pkt = *tx_pkts++;\n\t\tpkt_len = tx_pkt->pkt_len;\n\n\t\tRTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);\n\n\t\t/*\n\t\t * The number of descriptors that must be allocated for a\n\t\t * packet is the number of segments of that packet, plus 1\n\t\t * Context Descriptor for the VLAN Tag Identifier, if any.\n\t\t * Determine the last TX descriptor to allocate in the TX ring\n\t\t * for the packet, starting from the current position (tx_id)\n\t\t * in the ring.\n\t\t */\n\t\ttx_last = (uint16_t) (tx_id + tx_pkt->nb_segs - 1);\n\n\t\tol_flags = tx_pkt->ol_flags;\n\t\tl2_l3_len.l2_len = tx_pkt->l2_len;\n\t\tl2_l3_len.l3_len = tx_pkt->l3_len;\n\t\tvlan_macip_lens.f.vlan_tci = tx_pkt->vlan_tci;\n\t\tvlan_macip_lens.f.l2_l3_len = l2_l3_len.u16;\n\t\ttx_ol_req = ol_flags & IGB_TX_OFFLOAD_MASK;\n\n\t\t/* If a Context Descriptor need be built . */\n\t\tif (tx_ol_req) {\n\t\t\tctx = what_advctx_update(txq, tx_ol_req,\n\t\t\t\tvlan_macip_lens.data);\n\t\t\t/* Only allocate context descriptor if required*/\n\t\t\tnew_ctx = (ctx == IGB_CTX_NUM);\n\t\t\tctx = txq->ctx_curr;\n\t\t\ttx_last = (uint16_t) (tx_last + new_ctx);\n\t\t}\n\t\tif (tx_last >= txq->nb_tx_desc)\n\t\t\ttx_last = (uint16_t) (tx_last - txq->nb_tx_desc);\n\n\t\tPMD_TX_LOG(DEBUG, \"port_id=%u queue_id=%u pktlen=%u\"\n\t\t\t \" tx_first=%u tx_last=%u\",\n\t\t\t (unsigned) txq->port_id,\n\t\t\t (unsigned) txq->queue_id,\n\t\t\t (unsigned) pkt_len,\n\t\t\t (unsigned) tx_id,\n\t\t\t (unsigned) tx_last);\n\n\t\t/*\n\t\t * Check if there are enough free descriptors in the TX ring\n\t\t * to transmit the next packet.\n\t\t * This operation is based on the two following rules:\n\t\t *\n\t\t * 1- Only check that the last needed TX descriptor can be\n\t\t * allocated (by construction, if that descriptor is free,\n\t\t * all intermediate ones are also free).\n\t\t *\n\t\t * For this purpose, the index of the last TX descriptor\n\t\t * used for a packet (the \"last descriptor\" of a packet)\n\t\t * is recorded in the TX entries (the last one included)\n\t\t * that are associated with all TX descriptors allocated\n\t\t * for that packet.\n\t\t *\n\t\t * 2- Avoid to allocate the last free TX descriptor of the\n\t\t * ring, in order to never set the TDT register with the\n\t\t * same value stored in parallel by the NIC in the TDH\n\t\t * register, which makes the TX engine of the NIC enter\n\t\t * in a deadlock situation.\n\t\t *\n\t\t * By extension, avoid to allocate a free descriptor that\n\t\t * belongs to the last set of free descriptors allocated\n\t\t * to the same packet previously transmitted.\n\t\t */\n\n\t\t/*\n\t\t * The \"last descriptor\" of the previously sent packet, if any,\n\t\t * which used the last descriptor to allocate.\n\t\t */\n\t\ttx_end = sw_ring[tx_last].last_id;\n\n\t\t/*\n\t\t * The next descriptor following that \"last descriptor\" in the\n\t\t * ring.\n\t\t */\n\t\ttx_end = sw_ring[tx_end].next_id;\n\n\t\t/*\n\t\t * The \"last descriptor\" associated with that next descriptor.\n\t\t */\n\t\ttx_end = sw_ring[tx_end].last_id;\n\n\t\t/*\n\t\t * Check that this descriptor is free.\n\t\t */\n\t\tif (! (txr[tx_end].wb.status & E1000_TXD_STAT_DD)) {\n\t\t\tif (nb_tx == 0)\n\t\t\t\treturn (0);\n\t\t\tgoto end_of_tx;\n\t\t}\n\n\t\t/*\n\t\t * Set common flags of all TX Data Descriptors.\n\t\t *\n\t\t * The following bits must be set in all Data Descriptors:\n\t\t * - E1000_ADVTXD_DTYP_DATA\n\t\t * - E1000_ADVTXD_DCMD_DEXT\n\t\t *\n\t\t * The following bits must be set in the first Data Descriptor\n\t\t * and are ignored in the other ones:\n\t\t * - E1000_ADVTXD_DCMD_IFCS\n\t\t * - E1000_ADVTXD_MAC_1588\n\t\t * - E1000_ADVTXD_DCMD_VLE\n\t\t *\n\t\t * The following bits must only be set in the last Data\n\t\t * Descriptor:\n\t\t * - E1000_TXD_CMD_EOP\n\t\t *\n\t\t * The following bits can be set in any Data Descriptor, but\n\t\t * are only set in the last Data Descriptor:\n\t\t * - E1000_TXD_CMD_RS\n\t\t */\n\t\tcmd_type_len = txq->txd_type |\n\t\t\tE1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;\n\t\tolinfo_status = (pkt_len << E1000_ADVTXD_PAYLEN_SHIFT);\n#if defined(RTE_LIBRTE_IEEE1588)\n\t\tif (ol_flags & PKT_TX_IEEE1588_TMST)\n\t\t\tcmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;\n#endif\n\t\tif (tx_ol_req) {\n\t\t\t/* Setup TX Advanced context descriptor if required */\n\t\t\tif (new_ctx) {\n\t\t\t\tvolatile struct e1000_adv_tx_context_desc *\n\t\t\t\t ctx_txd;\n\n\t\t\t\tctx_txd = (volatile struct\n\t\t\t\t e1000_adv_tx_context_desc *)\n\t\t\t\t &txr[tx_id];\n\n\t\t\t\ttxn = &sw_ring[txe->next_id];\n\t\t\t\tRTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);\n\n\t\t\t\tif (txe->mbuf != NULL) {\n\t\t\t\t\trte_pktmbuf_free_seg(txe->mbuf);\n\t\t\t\t\ttxe->mbuf = NULL;\n\t\t\t\t}\n\n\t\t\t\tigbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,\n\t\t\t\t vlan_macip_lens.data);\n\n\t\t\t\ttxe->last_id = tx_last;\n\t\t\t\ttx_id = txe->next_id;\n\t\t\t\ttxe = txn;\n\t\t\t}\n\n\t\t\t/* Setup the TX Advanced Data Descriptor */\n\t\t\tcmd_type_len |= tx_desc_vlan_flags_to_cmdtype(ol_flags);\n\t\t\tolinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);\n\t\t\tolinfo_status |= (ctx << E1000_ADVTXD_IDX_SHIFT);\n\t\t}\n\n\t\tm_seg = tx_pkt;\n\t\tdo {\n\t\t\ttxn = &sw_ring[txe->next_id];\n\t\t\ttxd = &txr[tx_id];\n\n\t\t\tif (txe->mbuf != NULL)\n\t\t\t\trte_pktmbuf_free_seg(txe->mbuf);\n\t\t\ttxe->mbuf = m_seg;\n\n\t\t\t/*\n\t\t\t * Set up transmit descriptor.\n\t\t\t */\n\t\t\tslen = (uint16_t) m_seg->data_len;\n\t\t\tbuf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);\n\t\t\ttxd->read.buffer_addr =\n\t\t\t\trte_cpu_to_le_64(buf_dma_addr);\n\t\t\ttxd->read.cmd_type_len =\n\t\t\t\trte_cpu_to_le_32(cmd_type_len | slen);\n\t\t\ttxd->read.olinfo_status =\n\t\t\t\trte_cpu_to_le_32(olinfo_status);\n\t\t\ttxe->last_id = tx_last;\n\t\t\ttx_id = txe->next_id;\n\t\t\ttxe = txn;\n\t\t\tm_seg = m_seg->next;\n\t\t} while (m_seg != NULL);\n\n\t\t/*\n\t\t * The last packet data descriptor needs End Of Packet (EOP)\n\t\t * and Report Status (RS).\n\t\t */\n\t\ttxd->read.cmd_type_len |=\n\t\t\trte_cpu_to_le_32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);\n\t}\n end_of_tx:\n\trte_wmb();\n\n\t/*\n\t * Set the Transmit Descriptor Tail (TDT).\n\t */\n\tE1000_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);\n\tPMD_TX_LOG(DEBUG, \"port_id=%u queue_id=%u tx_tail=%u nb_tx=%u\",\n\t\t (unsigned) txq->port_id, (unsigned) txq->queue_id,\n\t\t (unsigned) tx_id, (unsigned) nb_tx);\n\ttxq->tx_tail = tx_id;\n\n\treturn (nb_tx);\n}\n\n/*********************************************************************\n *\n * RX functions\n *\n **********************************************************************/\n#ifdef RTE_NEXT_ABI\n#define IGB_PACKET_TYPE_IPV4 0X01\n#define IGB_PACKET_TYPE_IPV4_TCP 0X11\n#define IGB_PACKET_TYPE_IPV4_UDP 0X21\n#define IGB_PACKET_TYPE_IPV4_SCTP 0X41\n#define IGB_PACKET_TYPE_IPV4_EXT 0X03\n#define IGB_PACKET_TYPE_IPV4_EXT_SCTP 0X43\n#define IGB_PACKET_TYPE_IPV6 0X04\n#define IGB_PACKET_TYPE_IPV6_TCP 0X14\n#define IGB_PACKET_TYPE_IPV6_UDP 0X24\n#define IGB_PACKET_TYPE_IPV6_EXT 0X0C\n#define IGB_PACKET_TYPE_IPV6_EXT_TCP 0X1C\n#define IGB_PACKET_TYPE_IPV6_EXT_UDP 0X2C\n#define IGB_PACKET_TYPE_IPV4_IPV6 0X05\n#define IGB_PACKET_TYPE_IPV4_IPV6_TCP 0X15\n#define IGB_PACKET_TYPE_IPV4_IPV6_UDP 0X25\n#define IGB_PACKET_TYPE_IPV4_IPV6_EXT 0X0D\n#define IGB_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D\n#define IGB_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D\n#define IGB_PACKET_TYPE_MAX 0X80\n#define IGB_PACKET_TYPE_MASK 0X7F\n#define IGB_PACKET_TYPE_SHIFT 0X04\nstatic inline uint32_t\nigb_rxd_pkt_info_to_pkt_type(uint16_t pkt_info)\n{\n\tstatic const uint32_t\n\t\tptype_table[IGB_PACKET_TYPE_MAX] __rte_cache_aligned = {\n\t\t[IGB_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4,\n\t\t[IGB_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4_EXT,\n\t\t[IGB_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6,\n\t\t[IGB_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6,\n\t\t[IGB_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6_EXT,\n\t\t[IGB_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT,\n\t\t[IGB_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,\n\t\t[IGB_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,\n\t\t[IGB_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,\n\t\t[IGB_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,\n\t\t[IGB_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,\n\t\t[IGB_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,\n\t\t[IGB_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,\n\t\t[IGB_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,\n\t\t[IGB_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,\n\t\t[IGB_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,\n\t\t[IGB_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,\n\t\t[IGB_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,\n\t};\n\tif (unlikely(pkt_info & E1000_RXDADV_PKTTYPE_ETQF))\n\t\treturn RTE_PTYPE_UNKNOWN;\n\n\tpkt_info = (pkt_info >> IGB_PACKET_TYPE_SHIFT) & IGB_PACKET_TYPE_MASK;\n\n\treturn ptype_table[pkt_info];\n}\n\nstatic inline uint64_t\nrx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)\n{\n\tuint64_t pkt_flags = ((hl_tp_rs & 0x0F) == 0) ? 0 : PKT_RX_RSS_HASH;\n\n#if defined(RTE_LIBRTE_IEEE1588)\n\tstatic uint32_t ip_pkt_etqf_map[8] = {\n\t\t0, 0, 0, PKT_RX_IEEE1588_PTP,\n\t\t0, 0, 0, 0,\n\t};\n\n\tpkt_flags |= ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07];\n#endif\n\n\treturn pkt_flags;\n}\n#else /* RTE_NEXT_ABI */\nstatic inline uint64_t\nrx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)\n{\n\tuint64_t pkt_flags;\n\n\tstatic uint64_t ip_pkt_types_map[16] = {\n\t\t0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,\n\t\tPKT_RX_IPV6_HDR, 0, 0, 0,\n\t\tPKT_RX_IPV6_HDR_EXT, 0, 0, 0,\n\t\tPKT_RX_IPV6_HDR_EXT, 0, 0, 0,\n\t};\n\n#if defined(RTE_LIBRTE_IEEE1588)\n\tstatic uint32_t ip_pkt_etqf_map[8] = {\n\t\t0, 0, 0, PKT_RX_IEEE1588_PTP,\n\t\t0, 0, 0, 0,\n\t};\n\n\tpkt_flags = (hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ?\n\t\t\t\tip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :\n\t\t\t\tip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];\n#else\n\tpkt_flags = (hl_tp_rs & E1000_RXDADV_PKTTYPE_ETQF) ? 0 :\n\t\t\t\tip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];\n#endif\n\treturn pkt_flags | (((hl_tp_rs & 0x0F) == 0) ? 0 : PKT_RX_RSS_HASH);\n}\n#endif /* RTE_NEXT_ABI */\n\nstatic inline uint64_t\nrx_desc_status_to_pkt_flags(uint32_t rx_status)\n{\n\tuint64_t pkt_flags;\n\n\t/* Check if VLAN present */\n\tpkt_flags = (rx_status & E1000_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;\n\n#if defined(RTE_LIBRTE_IEEE1588)\n\tif (rx_status & E1000_RXD_STAT_TMST)\n\t\tpkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;\n#endif\n\treturn pkt_flags;\n}\n\nstatic inline uint64_t\nrx_desc_error_to_pkt_flags(uint32_t rx_status)\n{\n\t/*\n\t * Bit 30: IPE, IPv4 checksum error\n\t * Bit 29: L4I, L4I integrity error\n\t */\n\n\tstatic uint64_t error_to_pkt_flags_map[4] = {\n\t\t0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,\n\t\tPKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD\n\t};\n\treturn error_to_pkt_flags_map[(rx_status >>\n\t\tE1000_RXD_ERR_CKSUM_BIT) & E1000_RXD_ERR_CKSUM_MSK];\n}\n\nuint16_t\neth_igb_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t uint16_t nb_pkts)\n{\n\tstruct igb_rx_queue *rxq;\n\tvolatile union e1000_adv_rx_desc *rx_ring;\n\tvolatile union e1000_adv_rx_desc *rxdp;\n\tstruct igb_rx_entry *sw_ring;\n\tstruct igb_rx_entry *rxe;\n\tstruct rte_mbuf *rxm;\n\tstruct rte_mbuf *nmb;\n\tunion e1000_adv_rx_desc rxd;\n\tuint64_t dma_addr;\n\tuint32_t staterr;\n\tuint32_t hlen_type_rss;\n\tuint16_t pkt_len;\n\tuint16_t rx_id;\n\tuint16_t nb_rx;\n\tuint16_t nb_hold;\n\tuint64_t pkt_flags;\n\n\tnb_rx = 0;\n\tnb_hold = 0;\n\trxq = rx_queue;\n\trx_id = rxq->rx_tail;\n\trx_ring = rxq->rx_ring;\n\tsw_ring = rxq->sw_ring;\n\twhile (nb_rx < nb_pkts) {\n\t\t/*\n\t\t * The order of operations here is important as the DD status\n\t\t * bit must not be read after any other descriptor fields.\n\t\t * rx_ring and rxdp are pointing to volatile data so the order\n\t\t * of accesses cannot be reordered by the compiler. If they were\n\t\t * not volatile, they could be reordered which could lead to\n\t\t * using invalid descriptor fields when read from rxd.\n\t\t */\n\t\trxdp = &rx_ring[rx_id];\n\t\tstaterr = rxdp->wb.upper.status_error;\n\t\tif (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))\n\t\t\tbreak;\n\t\trxd = *rxdp;\n\n\t\t/*\n\t\t * End of packet.\n\t\t *\n\t\t * If the E1000_RXD_STAT_EOP flag is not set, the RX packet is\n\t\t * likely to be invalid and to be dropped by the various\n\t\t * validation checks performed by the network stack.\n\t\t *\n\t\t * Allocate a new mbuf to replenish the RX ring descriptor.\n\t\t * If the allocation fails:\n\t\t * - arrange for that RX descriptor to be the first one\n\t\t * being parsed the next time the receive function is\n\t\t * invoked [on the same queue].\n\t\t *\n\t\t * - Stop parsing the RX ring and return immediately.\n\t\t *\n\t\t * This policy do not drop the packet received in the RX\n\t\t * descriptor for which the allocation of a new mbuf failed.\n\t\t * Thus, it allows that packet to be later retrieved if\n\t\t * mbuf have been freed in the mean time.\n\t\t * As a side effect, holding RX descriptors instead of\n\t\t * systematically giving them back to the NIC may lead to\n\t\t * RX ring exhaustion situations.\n\t\t * However, the NIC can gracefully prevent such situations\n\t\t * to happen by sending specific \"back-pressure\" flow control\n\t\t * frames to its peer(s).\n\t\t */\n\t\tPMD_RX_LOG(DEBUG, \"port_id=%u queue_id=%u rx_id=%u \"\n\t\t\t \"staterr=0x%x pkt_len=%u\",\n\t\t\t (unsigned) rxq->port_id, (unsigned) rxq->queue_id,\n\t\t\t (unsigned) rx_id, (unsigned) staterr,\n\t\t\t (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));\n\n\t\tnmb = rte_rxmbuf_alloc(rxq->mb_pool);\n\t\tif (nmb == NULL) {\n\t\t\tPMD_RX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u \"\n\t\t\t\t \"queue_id=%u\", (unsigned) rxq->port_id,\n\t\t\t\t (unsigned) rxq->queue_id);\n\t\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;\n\t\t\tbreak;\n\t\t}\n\n\t\tnb_hold++;\n\t\trxe = &sw_ring[rx_id];\n\t\trx_id++;\n\t\tif (rx_id == rxq->nb_rx_desc)\n\t\t\trx_id = 0;\n\n\t\t/* Prefetch next mbuf while processing current one. */\n\t\trte_igb_prefetch(sw_ring[rx_id].mbuf);\n\n\t\t/*\n\t\t * When next RX descriptor is on a cache-line boundary,\n\t\t * prefetch the next 4 RX descriptors and the next 8 pointers\n\t\t * to mbufs.\n\t\t */\n\t\tif ((rx_id & 0x3) == 0) {\n\t\t\trte_igb_prefetch(&rx_ring[rx_id]);\n\t\t\trte_igb_prefetch(&sw_ring[rx_id]);\n\t\t}\n\n\t\trxm = rxe->mbuf;\n\t\trxe->mbuf = nmb;\n\t\tdma_addr =\n\t\t\trte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));\n\t\trxdp->read.hdr_addr = 0;\n\t\trxdp->read.pkt_addr = dma_addr;\n\n\t\t/*\n\t\t * Initialize the returned mbuf.\n\t\t * 1) setup generic mbuf fields:\n\t\t * - number of segments,\n\t\t * - next segment,\n\t\t * - packet length,\n\t\t * - RX port identifier.\n\t\t * 2) integrate hardware offload data, if any:\n\t\t * - RSS flag & hash,\n\t\t * - IP checksum flag,\n\t\t * - VLAN TCI, if any,\n\t\t * - error flags.\n\t\t */\n\t\tpkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -\n\t\t\t\t rxq->crc_len);\n\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n\t\trte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);\n\t\trxm->nb_segs = 1;\n\t\trxm->next = NULL;\n\t\trxm->pkt_len = pkt_len;\n\t\trxm->data_len = pkt_len;\n\t\trxm->port = rxq->port_id;\n\n\t\trxm->hash.rss = rxd.wb.lower.hi_dword.rss;\n\t\thlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);\n\t\t/* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */\n\t\trxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);\n\n\t\tpkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);\n\t\tpkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);\n\t\tpkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);\n\t\trxm->ol_flags = pkt_flags;\n#ifdef RTE_NEXT_ABI\n\t\trxm->packet_type = igb_rxd_pkt_info_to_pkt_type(rxd.wb.lower.\n\t\t\t\t\t\tlo_dword.hs_rss.pkt_info);\n#endif\n\n\t\t/*\n\t\t * Store the mbuf address into the next entry of the array\n\t\t * of returned packets.\n\t\t */\n\t\trx_pkts[nb_rx++] = rxm;\n\t}\n\trxq->rx_tail = rx_id;\n\n\t/*\n\t * If the number of free RX descriptors is greater than the RX free\n\t * threshold of the queue, advance the Receive Descriptor Tail (RDT)\n\t * register.\n\t * Update the RDT with the value of the last processed RX descriptor\n\t * minus 1, to guarantee that the RDT register is never equal to the\n\t * RDH register, which creates a \"full\" ring situtation from the\n\t * hardware point of view...\n\t */\n\tnb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);\n\tif (nb_hold > rxq->rx_free_thresh) {\n\t\tPMD_RX_LOG(DEBUG, \"port_id=%u queue_id=%u rx_tail=%u \"\n\t\t\t \"nb_hold=%u nb_rx=%u\",\n\t\t\t (unsigned) rxq->port_id, (unsigned) rxq->queue_id,\n\t\t\t (unsigned) rx_id, (unsigned) nb_hold,\n\t\t\t (unsigned) nb_rx);\n\t\trx_id = (uint16_t) ((rx_id == 0) ?\n\t\t\t\t (rxq->nb_rx_desc - 1) : (rx_id - 1));\n\t\tE1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);\n\t\tnb_hold = 0;\n\t}\n\trxq->nb_rx_hold = nb_hold;\n\treturn (nb_rx);\n}\n\nuint16_t\neth_igb_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\t\t uint16_t nb_pkts)\n{\n\tstruct igb_rx_queue *rxq;\n\tvolatile union e1000_adv_rx_desc *rx_ring;\n\tvolatile union e1000_adv_rx_desc *rxdp;\n\tstruct igb_rx_entry *sw_ring;\n\tstruct igb_rx_entry *rxe;\n\tstruct rte_mbuf *first_seg;\n\tstruct rte_mbuf *last_seg;\n\tstruct rte_mbuf *rxm;\n\tstruct rte_mbuf *nmb;\n\tunion e1000_adv_rx_desc rxd;\n\tuint64_t dma; /* Physical address of mbuf data buffer */\n\tuint32_t staterr;\n\tuint32_t hlen_type_rss;\n\tuint16_t rx_id;\n\tuint16_t nb_rx;\n\tuint16_t nb_hold;\n\tuint16_t data_len;\n\tuint64_t pkt_flags;\n\n\tnb_rx = 0;\n\tnb_hold = 0;\n\trxq = rx_queue;\n\trx_id = rxq->rx_tail;\n\trx_ring = rxq->rx_ring;\n\tsw_ring = rxq->sw_ring;\n\n\t/*\n\t * Retrieve RX context of current packet, if any.\n\t */\n\tfirst_seg = rxq->pkt_first_seg;\n\tlast_seg = rxq->pkt_last_seg;\n\n\twhile (nb_rx < nb_pkts) {\n\tnext_desc:\n\t\t/*\n\t\t * The order of operations here is important as the DD status\n\t\t * bit must not be read after any other descriptor fields.\n\t\t * rx_ring and rxdp are pointing to volatile data so the order\n\t\t * of accesses cannot be reordered by the compiler. If they were\n\t\t * not volatile, they could be reordered which could lead to\n\t\t * using invalid descriptor fields when read from rxd.\n\t\t */\n\t\trxdp = &rx_ring[rx_id];\n\t\tstaterr = rxdp->wb.upper.status_error;\n\t\tif (! (staterr & rte_cpu_to_le_32(E1000_RXD_STAT_DD)))\n\t\t\tbreak;\n\t\trxd = *rxdp;\n\n\t\t/*\n\t\t * Descriptor done.\n\t\t *\n\t\t * Allocate a new mbuf to replenish the RX ring descriptor.\n\t\t * If the allocation fails:\n\t\t * - arrange for that RX descriptor to be the first one\n\t\t * being parsed the next time the receive function is\n\t\t * invoked [on the same queue].\n\t\t *\n\t\t * - Stop parsing the RX ring and return immediately.\n\t\t *\n\t\t * This policy does not drop the packet received in the RX\n\t\t * descriptor for which the allocation of a new mbuf failed.\n\t\t * Thus, it allows that packet to be later retrieved if\n\t\t * mbuf have been freed in the mean time.\n\t\t * As a side effect, holding RX descriptors instead of\n\t\t * systematically giving them back to the NIC may lead to\n\t\t * RX ring exhaustion situations.\n\t\t * However, the NIC can gracefully prevent such situations\n\t\t * to happen by sending specific \"back-pressure\" flow control\n\t\t * frames to its peer(s).\n\t\t */\n\t\tPMD_RX_LOG(DEBUG, \"port_id=%u queue_id=%u rx_id=%u \"\n\t\t\t \"staterr=0x%x data_len=%u\",\n\t\t\t (unsigned) rxq->port_id, (unsigned) rxq->queue_id,\n\t\t\t (unsigned) rx_id, (unsigned) staterr,\n\t\t\t (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));\n\n\t\tnmb = rte_rxmbuf_alloc(rxq->mb_pool);\n\t\tif (nmb == NULL) {\n\t\t\tPMD_RX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u \"\n\t\t\t\t \"queue_id=%u\", (unsigned) rxq->port_id,\n\t\t\t\t (unsigned) rxq->queue_id);\n\t\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;\n\t\t\tbreak;\n\t\t}\n\n\t\tnb_hold++;\n\t\trxe = &sw_ring[rx_id];\n\t\trx_id++;\n\t\tif (rx_id == rxq->nb_rx_desc)\n\t\t\trx_id = 0;\n\n\t\t/* Prefetch next mbuf while processing current one. */\n\t\trte_igb_prefetch(sw_ring[rx_id].mbuf);\n\n\t\t/*\n\t\t * When next RX descriptor is on a cache-line boundary,\n\t\t * prefetch the next 4 RX descriptors and the next 8 pointers\n\t\t * to mbufs.\n\t\t */\n\t\tif ((rx_id & 0x3) == 0) {\n\t\t\trte_igb_prefetch(&rx_ring[rx_id]);\n\t\t\trte_igb_prefetch(&sw_ring[rx_id]);\n\t\t}\n\n\t\t/*\n\t\t * Update RX descriptor with the physical address of the new\n\t\t * data buffer of the new allocated mbuf.\n\t\t */\n\t\trxm = rxe->mbuf;\n\t\trxe->mbuf = nmb;\n\t\tdma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));\n\t\trxdp->read.pkt_addr = dma;\n\t\trxdp->read.hdr_addr = 0;\n\n\t\t/*\n\t\t * Set data length & data buffer address of mbuf.\n\t\t */\n\t\tdata_len = rte_le_to_cpu_16(rxd.wb.upper.length);\n\t\trxm->data_len = data_len;\n\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n\n\t\t/*\n\t\t * If this is the first buffer of the received packet,\n\t\t * set the pointer to the first mbuf of the packet and\n\t\t * initialize its context.\n\t\t * Otherwise, update the total length and the number of segments\n\t\t * of the current scattered packet, and update the pointer to\n\t\t * the last mbuf of the current packet.\n\t\t */\n\t\tif (first_seg == NULL) {\n\t\t\tfirst_seg = rxm;\n\t\t\tfirst_seg->pkt_len = data_len;\n\t\t\tfirst_seg->nb_segs = 1;\n\t\t} else {\n\t\t\tfirst_seg->pkt_len += data_len;\n\t\t\tfirst_seg->nb_segs++;\n\t\t\tlast_seg->next = rxm;\n\t\t}\n\n\t\t/*\n\t\t * If this is not the last buffer of the received packet,\n\t\t * update the pointer to the last mbuf of the current scattered\n\t\t * packet and continue to parse the RX ring.\n\t\t */\n\t\tif (! (staterr & E1000_RXD_STAT_EOP)) {\n\t\t\tlast_seg = rxm;\n\t\t\tgoto next_desc;\n\t\t}\n\n\t\t/*\n\t\t * This is the last buffer of the received packet.\n\t\t * If the CRC is not stripped by the hardware:\n\t\t * - Subtract the CRC\tlength from the total packet length.\n\t\t * - If the last buffer only contains the whole CRC or a part\n\t\t * of it, free the mbuf associated to the last buffer.\n\t\t * If part of the CRC is also contained in the previous\n\t\t * mbuf, subtract the length of that CRC part from the\n\t\t * data length of the previous mbuf.\n\t\t */\n\t\trxm->next = NULL;\n\t\tif (unlikely(rxq->crc_len > 0)) {\n\t\t\tfirst_seg->pkt_len -= ETHER_CRC_LEN;\n\t\t\tif (data_len <= ETHER_CRC_LEN) {\n\t\t\t\trte_pktmbuf_free_seg(rxm);\n\t\t\t\tfirst_seg->nb_segs--;\n\t\t\t\tlast_seg->data_len = (uint16_t)\n\t\t\t\t\t(last_seg->data_len -\n\t\t\t\t\t (ETHER_CRC_LEN - data_len));\n\t\t\t\tlast_seg->next = NULL;\n\t\t\t} else\n\t\t\t\trxm->data_len =\n\t\t\t\t\t(uint16_t) (data_len - ETHER_CRC_LEN);\n\t\t}\n\n\t\t/*\n\t\t * Initialize the first mbuf of the returned packet:\n\t\t * - RX port identifier,\n\t\t * - hardware offload data, if any:\n\t\t * - RSS flag & hash,\n\t\t * - IP checksum flag,\n\t\t * - VLAN TCI, if any,\n\t\t * - error flags.\n\t\t */\n\t\tfirst_seg->port = rxq->port_id;\n\t\tfirst_seg->hash.rss = rxd.wb.lower.hi_dword.rss;\n\n\t\t/*\n\t\t * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is\n\t\t * set in the pkt_flags field.\n\t\t */\n\t\tfirst_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);\n\t\thlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);\n\t\tpkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);\n\t\tpkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);\n\t\tpkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);\n\t\tfirst_seg->ol_flags = pkt_flags;\n#ifdef RTE_NEXT_ABI\n\t\tfirst_seg->packet_type = igb_rxd_pkt_info_to_pkt_type(rxd.wb.\n\t\t\t\t\tlower.lo_dword.hs_rss.pkt_info);\n#endif\n\n\t\t/* Prefetch data of first segment, if configured to do so. */\n\t\trte_packet_prefetch((char *)first_seg->buf_addr +\n\t\t\tfirst_seg->data_off);\n\n\t\t/*\n\t\t * Store the mbuf address into the next entry of the array\n\t\t * of returned packets.\n\t\t */\n\t\trx_pkts[nb_rx++] = first_seg;\n\n\t\t/*\n\t\t * Setup receipt context for a new packet.\n\t\t */\n\t\tfirst_seg = NULL;\n\t}\n\n\t/*\n\t * Record index of the next RX descriptor to probe.\n\t */\n\trxq->rx_tail = rx_id;\n\n\t/*\n\t * Save receive context.\n\t */\n\trxq->pkt_first_seg = first_seg;\n\trxq->pkt_last_seg = last_seg;\n\n\t/*\n\t * If the number of free RX descriptors is greater than the RX free\n\t * threshold of the queue, advance the Receive Descriptor Tail (RDT)\n\t * register.\n\t * Update the RDT with the value of the last processed RX descriptor\n\t * minus 1, to guarantee that the RDT register is never equal to the\n\t * RDH register, which creates a \"full\" ring situtation from the\n\t * hardware point of view...\n\t */\n\tnb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);\n\tif (nb_hold > rxq->rx_free_thresh) {\n\t\tPMD_RX_LOG(DEBUG, \"port_id=%u queue_id=%u rx_tail=%u \"\n\t\t\t \"nb_hold=%u nb_rx=%u\",\n\t\t\t (unsigned) rxq->port_id, (unsigned) rxq->queue_id,\n\t\t\t (unsigned) rx_id, (unsigned) nb_hold,\n\t\t\t (unsigned) nb_rx);\n\t\trx_id = (uint16_t) ((rx_id == 0) ?\n\t\t\t\t (rxq->nb_rx_desc - 1) : (rx_id - 1));\n\t\tE1000_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);\n\t\tnb_hold = 0;\n\t}\n\trxq->nb_rx_hold = nb_hold;\n\treturn (nb_rx);\n}\n\n/*\n * Rings setup and release.\n *\n * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be\n * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.\n * This will also optimize cache line size effect.\n * H/W supports up to cache line size 128.\n */\n#define IGB_ALIGN 128\n\n/*\n * Maximum number of Ring Descriptors.\n *\n * Since RDLEN/TDLEN should be multiple of 128bytes, the number of ring\n * desscriptors should meet the following condition:\n * (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0\n */\n#define IGB_MIN_RING_DESC 32\n#define IGB_MAX_RING_DESC 4096\n\nstatic const struct rte_memzone *\nring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,\n\t\t uint16_t queue_id, uint32_t ring_size, int socket_id)\n{\n\tchar z_name[RTE_MEMZONE_NAMESIZE];\n\tconst struct rte_memzone *mz;\n\n\tsnprintf(z_name, sizeof(z_name), \"%s_%s_%d_%d\",\n\t\t\tdev->driver->pci_drv.name, ring_name,\n\t\t\t\tdev->data->port_id, queue_id);\n\tmz = rte_memzone_lookup(z_name);\n\tif (mz)\n\t\treturn mz;\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n\treturn rte_memzone_reserve_bounded(z_name, ring_size,\n\t\t\tsocket_id, 0, IGB_ALIGN, RTE_PGSIZE_2M);\n#else\n\treturn rte_memzone_reserve_aligned(z_name, ring_size,\n\t\t\tsocket_id, 0, IGB_ALIGN);\n#endif\n}\n\nstatic void\nigb_tx_queue_release_mbufs(struct igb_tx_queue *txq)\n{\n\tunsigned i;\n\n\tif (txq->sw_ring != NULL) {\n\t\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n\t\t\tif (txq->sw_ring[i].mbuf != NULL) {\n\t\t\t\trte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);\n\t\t\t\ttxq->sw_ring[i].mbuf = NULL;\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void\nigb_tx_queue_release(struct igb_tx_queue *txq)\n{\n\tif (txq != NULL) {\n\t\tigb_tx_queue_release_mbufs(txq);\n\t\trte_free(txq->sw_ring);\n\t\trte_free(txq);\n\t}\n}\n\nvoid\neth_igb_tx_queue_release(void *txq)\n{\n\tigb_tx_queue_release(txq);\n}\n\nstatic void\nigb_reset_tx_queue_stat(struct igb_tx_queue *txq)\n{\n\ttxq->tx_head = 0;\n\ttxq->tx_tail = 0;\n\ttxq->ctx_curr = 0;\n\tmemset((void*)&txq->ctx_cache, 0,\n\t\tIGB_CTX_NUM * sizeof(struct igb_advctx_info));\n}\n\nstatic void\nigb_reset_tx_queue(struct igb_tx_queue *txq, struct rte_eth_dev *dev)\n{\n\tstatic const union e1000_adv_tx_desc zeroed_desc = {{0}};\n\tstruct igb_tx_entry *txe = txq->sw_ring;\n\tuint16_t i, prev;\n\tstruct e1000_hw *hw;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\t/* Zero out HW ring memory */\n\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n\t\ttxq->tx_ring[i] = zeroed_desc;\n\t}\n\n\t/* Initialize ring entries */\n\tprev = (uint16_t)(txq->nb_tx_desc - 1);\n\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n\t\tvolatile union e1000_adv_tx_desc *txd = &(txq->tx_ring[i]);\n\n\t\ttxd->wb.status = E1000_TXD_STAT_DD;\n\t\ttxe[i].mbuf = NULL;\n\t\ttxe[i].last_id = i;\n\t\ttxe[prev].next_id = i;\n\t\tprev = i;\n\t}\n\n\ttxq->txd_type = E1000_ADVTXD_DTYP_DATA;\n\t/* 82575 specific, each tx queue will use 2 hw contexts */\n\tif (hw->mac.type == e1000_82575)\n\t\ttxq->ctx_start = txq->queue_id * IGB_CTX_NUM;\n\n\tigb_reset_tx_queue_stat(txq);\n}\n\nint\neth_igb_tx_queue_setup(struct rte_eth_dev *dev,\n\t\t\t uint16_t queue_idx,\n\t\t\t uint16_t nb_desc,\n\t\t\t unsigned int socket_id,\n\t\t\t const struct rte_eth_txconf *tx_conf)\n{\n\tconst struct rte_memzone *tz;\n\tstruct igb_tx_queue *txq;\n\tstruct e1000_hw *hw;\n\tuint32_t size;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/*\n\t * Validate number of transmit descriptors.\n\t * It must not exceed hardware maximum, and must be multiple\n\t * of IGB_ALIGN.\n\t */\n\tif (((nb_desc * sizeof(union e1000_adv_tx_desc)) % IGB_ALIGN) != 0 ||\n\t (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {\n\t\treturn -EINVAL;\n\t}\n\n\t/*\n\t * The tx_free_thresh and tx_rs_thresh values are not used in the 1G\n\t * driver.\n\t */\n\tif (tx_conf->tx_free_thresh != 0)\n\t\tPMD_INIT_LOG(WARNING, \"The tx_free_thresh parameter is not \"\n\t\t\t \"used for the 1G driver.\");\n\tif (tx_conf->tx_rs_thresh != 0)\n\t\tPMD_INIT_LOG(WARNING, \"The tx_rs_thresh parameter is not \"\n\t\t\t \"used for the 1G driver.\");\n\tif (tx_conf->tx_thresh.wthresh == 0)\n\t\tPMD_INIT_LOG(WARNING, \"To improve 1G driver performance, \"\n\t\t\t \"consider setting the TX WTHRESH value to 4, 8, \"\n\t\t\t \"or 16.\");\n\n\t/* Free memory prior to re-allocation if needed */\n\tif (dev->data->tx_queues[queue_idx] != NULL) {\n\t\tigb_tx_queue_release(dev->data->tx_queues[queue_idx]);\n\t\tdev->data->tx_queues[queue_idx] = NULL;\n\t}\n\n\t/* First allocate the tx queue data structure */\n\ttxq = rte_zmalloc(\"ethdev TX queue\", sizeof(struct igb_tx_queue),\n\t\t\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n\tif (txq == NULL)\n\t\treturn (-ENOMEM);\n\n\t/*\n\t * Allocate TX ring hardware descriptors. A memzone large enough to\n\t * handle the maximum ring size is allocated in order to allow for\n\t * resizing in later calls to the queue setup function.\n\t */\n\tsize = sizeof(union e1000_adv_tx_desc) * IGB_MAX_RING_DESC;\n\ttz = ring_dma_zone_reserve(dev, \"tx_ring\", queue_idx,\n\t\t\t\t\tsize, socket_id);\n\tif (tz == NULL) {\n\t\tigb_tx_queue_release(txq);\n\t\treturn (-ENOMEM);\n\t}\n\n\ttxq->nb_tx_desc = nb_desc;\n\ttxq->pthresh = tx_conf->tx_thresh.pthresh;\n\ttxq->hthresh = tx_conf->tx_thresh.hthresh;\n\ttxq->wthresh = tx_conf->tx_thresh.wthresh;\n\tif (txq->wthresh > 0 && hw->mac.type == e1000_82576)\n\t\ttxq->wthresh = 1;\n\ttxq->queue_id = queue_idx;\n\ttxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?\n\t\tqueue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);\n\ttxq->port_id = dev->data->port_id;\n\n\ttxq->tdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(txq->reg_idx));\n#ifndef RTE_LIBRTE_XEN_DOM0\n\ttxq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;\n#else\n\ttxq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);\n#endif\n\t txq->tx_ring = (union e1000_adv_tx_desc *) tz->addr;\n\t/* Allocate software ring */\n\ttxq->sw_ring = rte_zmalloc(\"txq->sw_ring\",\n\t\t\t\t sizeof(struct igb_tx_entry) * nb_desc,\n\t\t\t\t RTE_CACHE_LINE_SIZE);\n\tif (txq->sw_ring == NULL) {\n\t\tigb_tx_queue_release(txq);\n\t\treturn (-ENOMEM);\n\t}\n\tPMD_INIT_LOG(DEBUG, \"sw_ring=%p hw_ring=%p dma_addr=0x%\"PRIx64,\n\t\t txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);\n\n\tigb_reset_tx_queue(txq, dev);\n\tdev->tx_pkt_burst = eth_igb_xmit_pkts;\n\tdev->data->tx_queues[queue_idx] = txq;\n\n\treturn (0);\n}\n\nstatic void\nigb_rx_queue_release_mbufs(struct igb_rx_queue *rxq)\n{\n\tunsigned i;\n\n\tif (rxq->sw_ring != NULL) {\n\t\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n\t\t\tif (rxq->sw_ring[i].mbuf != NULL) {\n\t\t\t\trte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);\n\t\t\t\trxq->sw_ring[i].mbuf = NULL;\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void\nigb_rx_queue_release(struct igb_rx_queue *rxq)\n{\n\tif (rxq != NULL) {\n\t\tigb_rx_queue_release_mbufs(rxq);\n\t\trte_free(rxq->sw_ring);\n\t\trte_free(rxq);\n\t}\n}\n\nvoid\neth_igb_rx_queue_release(void *rxq)\n{\n\tigb_rx_queue_release(rxq);\n}\n\nstatic void\nigb_reset_rx_queue(struct igb_rx_queue *rxq)\n{\n\tstatic const union e1000_adv_rx_desc zeroed_desc = {{0}};\n\tunsigned i;\n\n\t/* Zero out HW ring memory */\n\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n\t\trxq->rx_ring[i] = zeroed_desc;\n\t}\n\n\trxq->rx_tail = 0;\n\trxq->pkt_first_seg = NULL;\n\trxq->pkt_last_seg = NULL;\n}\n\nint\neth_igb_rx_queue_setup(struct rte_eth_dev *dev,\n\t\t\t uint16_t queue_idx,\n\t\t\t uint16_t nb_desc,\n\t\t\t unsigned int socket_id,\n\t\t\t const struct rte_eth_rxconf *rx_conf,\n\t\t\t struct rte_mempool *mp)\n{\n\tconst struct rte_memzone *rz;\n\tstruct igb_rx_queue *rxq;\n\tstruct e1000_hw *hw;\n\tunsigned int size;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/*\n\t * Validate number of receive descriptors.\n\t * It must not exceed hardware maximum, and must be multiple\n\t * of IGB_ALIGN.\n\t */\n\tif (((nb_desc * sizeof(union e1000_adv_rx_desc)) % IGB_ALIGN) != 0 ||\n\t (nb_desc > IGB_MAX_RING_DESC) || (nb_desc < IGB_MIN_RING_DESC)) {\n\t\treturn (-EINVAL);\n\t}\n\n\t/* Free memory prior to re-allocation if needed */\n\tif (dev->data->rx_queues[queue_idx] != NULL) {\n\t\tigb_rx_queue_release(dev->data->rx_queues[queue_idx]);\n\t\tdev->data->rx_queues[queue_idx] = NULL;\n\t}\n\n\t/* First allocate the RX queue data structure. */\n\trxq = rte_zmalloc(\"ethdev RX queue\", sizeof(struct igb_rx_queue),\n\t\t\t RTE_CACHE_LINE_SIZE);\n\tif (rxq == NULL)\n\t\treturn (-ENOMEM);\n\trxq->mb_pool = mp;\n\trxq->nb_rx_desc = nb_desc;\n\trxq->pthresh = rx_conf->rx_thresh.pthresh;\n\trxq->hthresh = rx_conf->rx_thresh.hthresh;\n\trxq->wthresh = rx_conf->rx_thresh.wthresh;\n\tif (rxq->wthresh > 0 && hw->mac.type == e1000_82576)\n\t\trxq->wthresh = 1;\n\trxq->drop_en = rx_conf->rx_drop_en;\n\trxq->rx_free_thresh = rx_conf->rx_free_thresh;\n\trxq->queue_id = queue_idx;\n\trxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?\n\t\tqueue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);\n\trxq->port_id = dev->data->port_id;\n\trxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :\n\t\t\t\t ETHER_CRC_LEN);\n\n\t/*\n\t * Allocate RX ring hardware descriptors. A memzone large enough to\n\t * handle the maximum ring size is allocated in order to allow for\n\t * resizing in later calls to the queue setup function.\n\t */\n\tsize = sizeof(union e1000_adv_rx_desc) * IGB_MAX_RING_DESC;\n\trz = ring_dma_zone_reserve(dev, \"rx_ring\", queue_idx, size, socket_id);\n\tif (rz == NULL) {\n\t\tigb_rx_queue_release(rxq);\n\t\treturn (-ENOMEM);\n\t}\n\trxq->rdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDT(rxq->reg_idx));\n\trxq->rdh_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_RDH(rxq->reg_idx));\n#ifndef RTE_LIBRTE_XEN_DOM0\n\trxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;\n#else\n\trxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);\n#endif\n\trxq->rx_ring = (union e1000_adv_rx_desc *) rz->addr;\n\n\t/* Allocate software ring. */\n\trxq->sw_ring = rte_zmalloc(\"rxq->sw_ring\",\n\t\t\t\t sizeof(struct igb_rx_entry) * nb_desc,\n\t\t\t\t RTE_CACHE_LINE_SIZE);\n\tif (rxq->sw_ring == NULL) {\n\t\tigb_rx_queue_release(rxq);\n\t\treturn (-ENOMEM);\n\t}\n\tPMD_INIT_LOG(DEBUG, \"sw_ring=%p hw_ring=%p dma_addr=0x%\"PRIx64,\n\t\t rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);\n\n\tdev->data->rx_queues[queue_idx] = rxq;\n\tigb_reset_rx_queue(rxq);\n\n\treturn 0;\n}\n\nuint32_t\neth_igb_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n{\n#define IGB_RXQ_SCAN_INTERVAL 4\n\tvolatile union e1000_adv_rx_desc *rxdp;\n\tstruct igb_rx_queue *rxq;\n\tuint32_t desc = 0;\n\n\tif (rx_queue_id >= dev->data->nb_rx_queues) {\n\t\tPMD_RX_LOG(ERR, \"Invalid RX queue id=%d\", rx_queue_id);\n\t\treturn 0;\n\t}\n\n\trxq = dev->data->rx_queues[rx_queue_id];\n\trxdp = &(rxq->rx_ring[rxq->rx_tail]);\n\n\twhile ((desc < rxq->nb_rx_desc) &&\n\t\t(rxdp->wb.upper.status_error & E1000_RXD_STAT_DD)) {\n\t\tdesc += IGB_RXQ_SCAN_INTERVAL;\n\t\trxdp += IGB_RXQ_SCAN_INTERVAL;\n\t\tif (rxq->rx_tail + desc >= rxq->nb_rx_desc)\n\t\t\trxdp = &(rxq->rx_ring[rxq->rx_tail +\n\t\t\t\tdesc - rxq->nb_rx_desc]);\n\t}\n\n\treturn 0;\n}\n\nint\neth_igb_rx_descriptor_done(void *rx_queue, uint16_t offset)\n{\n\tvolatile union e1000_adv_rx_desc *rxdp;\n\tstruct igb_rx_queue *rxq = rx_queue;\n\tuint32_t desc;\n\n\tif (unlikely(offset >= rxq->nb_rx_desc))\n\t\treturn 0;\n\tdesc = rxq->rx_tail + offset;\n\tif (desc >= rxq->nb_rx_desc)\n\t\tdesc -= rxq->nb_rx_desc;\n\n\trxdp = &rxq->rx_ring[desc];\n\treturn !!(rxdp->wb.upper.status_error & E1000_RXD_STAT_DD);\n}\n\nvoid\nigb_dev_clear_queues(struct rte_eth_dev *dev)\n{\n\tuint16_t i;\n\tstruct igb_tx_queue *txq;\n\tstruct igb_rx_queue *rxq;\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\ttxq = dev->data->tx_queues[i];\n\t\tif (txq != NULL) {\n\t\t\tigb_tx_queue_release_mbufs(txq);\n\t\t\tigb_reset_tx_queue(txq, dev);\n\t\t}\n\t}\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\trxq = dev->data->rx_queues[i];\n\t\tif (rxq != NULL) {\n\t\t\tigb_rx_queue_release_mbufs(rxq);\n\t\t\tigb_reset_rx_queue(rxq);\n\t\t}\n\t}\n}\n\nvoid\nigb_dev_free_queues(struct rte_eth_dev *dev)\n{\n\tuint16_t i;\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\teth_igb_rx_queue_release(dev->data->rx_queues[i]);\n\t\tdev->data->rx_queues[i] = NULL;\n\t}\n\tdev->data->nb_rx_queues = 0;\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\teth_igb_tx_queue_release(dev->data->tx_queues[i]);\n\t\tdev->data->tx_queues[i] = NULL;\n\t}\n\tdev->data->nb_tx_queues = 0;\n}\n\n/**\n * Receive Side Scaling (RSS).\n * See section 7.1.1.7 in the following document:\n * \"Intel 82576 GbE Controller Datasheet\" - Revision 2.45 October 2009\n *\n * Principles:\n * The source and destination IP addresses of the IP header and the source and\n * destination ports of TCP/UDP headers, if any, of received packets are hashed\n * against a configurable random key to compute a 32-bit RSS hash result.\n * The seven (7) LSBs of the 32-bit hash result are used as an index into a\n * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit\n * RSS output index which is used as the RX queue index where to store the\n * received packets.\n * The following output is supplied in the RX write-back descriptor:\n * - 32-bit result of the Microsoft RSS hash function,\n * - 4-bit RSS type field.\n */\n\n/*\n * RSS random key supplied in section 7.1.1.7.3 of the Intel 82576 datasheet.\n * Used as the default key.\n */\nstatic uint8_t rss_intel_key[40] = {\n\t0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,\n\t0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,\n\t0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,\n\t0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,\n\t0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,\n};\n\nstatic void\nigb_rss_disable(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw;\n\tuint32_t mrqc;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tmrqc = E1000_READ_REG(hw, E1000_MRQC);\n\tmrqc &= ~E1000_MRQC_ENABLE_MASK;\n\tE1000_WRITE_REG(hw, E1000_MRQC, mrqc);\n}\n\nstatic void\nigb_hw_rss_hash_set(struct e1000_hw *hw, struct rte_eth_rss_conf *rss_conf)\n{\n\tuint8_t *hash_key;\n\tuint32_t rss_key;\n\tuint32_t mrqc;\n\tuint64_t rss_hf;\n\tuint16_t i;\n\n\thash_key = rss_conf->rss_key;\n\tif (hash_key != NULL) {\n\t\t/* Fill in RSS hash key */\n\t\tfor (i = 0; i < 10; i++) {\n\t\t\trss_key = hash_key[(i * 4)];\n\t\t\trss_key |= hash_key[(i * 4) + 1] << 8;\n\t\t\trss_key |= hash_key[(i * 4) + 2] << 16;\n\t\t\trss_key |= hash_key[(i * 4) + 3] << 24;\n\t\t\tE1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key);\n\t\t}\n\t}\n\n\t/* Set configured hashing protocols in MRQC register */\n\trss_hf = rss_conf->rss_hf;\n\tmrqc = E1000_MRQC_ENABLE_RSS_4Q; /* RSS enabled. */\n\tif (rss_hf & ETH_RSS_IPV4)\n\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV4;\n\tif (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)\n\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV4_TCP;\n\tif (rss_hf & ETH_RSS_IPV6)\n\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV6;\n\tif (rss_hf & ETH_RSS_IPV6_EX)\n\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV6_EX;\n\tif (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)\n\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP;\n\tif (rss_hf & ETH_RSS_IPV6_TCP_EX)\n\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;\n\tif (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)\n\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;\n\tif (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)\n\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;\n\tif (rss_hf & ETH_RSS_IPV6_UDP_EX)\n\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP_EX;\n\tE1000_WRITE_REG(hw, E1000_MRQC, mrqc);\n}\n\nint\neth_igb_rss_hash_update(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_rss_conf *rss_conf)\n{\n\tstruct e1000_hw *hw;\n\tuint32_t mrqc;\n\tuint64_t rss_hf;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/*\n\t * Before changing anything, first check that the update RSS operation\n\t * does not attempt to disable RSS, if RSS was enabled at\n\t * initialization time, or does not attempt to enable RSS, if RSS was\n\t * disabled at initialization time.\n\t */\n\trss_hf = rss_conf->rss_hf & IGB_RSS_OFFLOAD_ALL;\n\tmrqc = E1000_READ_REG(hw, E1000_MRQC);\n\tif (!(mrqc & E1000_MRQC_ENABLE_MASK)) { /* RSS disabled */\n\t\tif (rss_hf != 0) /* Enable RSS */\n\t\t\treturn -(EINVAL);\n\t\treturn 0; /* Nothing to do */\n\t}\n\t/* RSS enabled */\n\tif (rss_hf == 0) /* Disable RSS */\n\t\treturn -(EINVAL);\n\tigb_hw_rss_hash_set(hw, rss_conf);\n\treturn 0;\n}\n\nint eth_igb_rss_hash_conf_get(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_conf *rss_conf)\n{\n\tstruct e1000_hw *hw;\n\tuint8_t *hash_key;\n\tuint32_t rss_key;\n\tuint32_t mrqc;\n\tuint64_t rss_hf;\n\tuint16_t i;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\thash_key = rss_conf->rss_key;\n\tif (hash_key != NULL) {\n\t\t/* Return RSS hash key */\n\t\tfor (i = 0; i < 10; i++) {\n\t\t\trss_key = E1000_READ_REG_ARRAY(hw, E1000_RSSRK(0), i);\n\t\t\thash_key[(i * 4)] = rss_key & 0x000000FF;\n\t\t\thash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;\n\t\t\thash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;\n\t\t\thash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;\n\t\t}\n\t}\n\n\t/* Get RSS functions configured in MRQC register */\n\tmrqc = E1000_READ_REG(hw, E1000_MRQC);\n\tif ((mrqc & E1000_MRQC_ENABLE_RSS_4Q) == 0) { /* RSS is disabled */\n\t\trss_conf->rss_hf = 0;\n\t\treturn 0;\n\t}\n\trss_hf = 0;\n\tif (mrqc & E1000_MRQC_RSS_FIELD_IPV4)\n\t\trss_hf |= ETH_RSS_IPV4;\n\tif (mrqc & E1000_MRQC_RSS_FIELD_IPV4_TCP)\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;\n\tif (mrqc & E1000_MRQC_RSS_FIELD_IPV6)\n\t\trss_hf |= ETH_RSS_IPV6;\n\tif (mrqc & E1000_MRQC_RSS_FIELD_IPV6_EX)\n\t\trss_hf |= ETH_RSS_IPV6_EX;\n\tif (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP)\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;\n\tif (mrqc & E1000_MRQC_RSS_FIELD_IPV6_TCP_EX)\n\t\trss_hf |= ETH_RSS_IPV6_TCP_EX;\n\tif (mrqc & E1000_MRQC_RSS_FIELD_IPV4_UDP)\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;\n\tif (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP)\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;\n\tif (mrqc & E1000_MRQC_RSS_FIELD_IPV6_UDP_EX)\n\t\trss_hf |= ETH_RSS_IPV6_UDP_EX;\n\trss_conf->rss_hf = rss_hf;\n\treturn 0;\n}\n\nstatic void\nigb_rss_configure(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_rss_conf rss_conf;\n\tstruct e1000_hw *hw;\n\tuint32_t shift;\n\tuint16_t i;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/* Fill in redirection table. */\n\tshift = (hw->mac.type == e1000_82575) ? 6 : 0;\n\tfor (i = 0; i < 128; i++) {\n\t\tunion e1000_reta {\n\t\t\tuint32_t dword;\n\t\t\tuint8_t bytes[4];\n\t\t} reta;\n\t\tuint8_t q_idx;\n\n\t\tq_idx = (uint8_t) ((dev->data->nb_rx_queues > 1) ?\n\t\t\t\t i % dev->data->nb_rx_queues : 0);\n\t\treta.bytes[i & 3] = (uint8_t) (q_idx << shift);\n\t\tif ((i & 3) == 3)\n\t\t\tE1000_WRITE_REG(hw, E1000_RETA(i >> 2), reta.dword);\n\t}\n\n\t/*\n\t * Configure the RSS key and the RSS protocols used to compute\n\t * the RSS hash of input packets.\n\t */\n\trss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;\n\tif ((rss_conf.rss_hf & IGB_RSS_OFFLOAD_ALL) == 0) {\n\t\tigb_rss_disable(dev);\n\t\treturn;\n\t}\n\tif (rss_conf.rss_key == NULL)\n\t\trss_conf.rss_key = rss_intel_key; /* Default hash key */\n\tigb_hw_rss_hash_set(hw, &rss_conf);\n}\n\n/*\n * Check if the mac type support VMDq or not.\n * Return 1 if it supports, otherwise, return 0.\n */\nstatic int\nigb_is_vmdq_supported(const struct rte_eth_dev *dev)\n{\n\tconst struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82576:\n\tcase e1000_82580:\n\tcase e1000_i350:\n\t\treturn 1;\n\tcase e1000_82540:\n\tcase e1000_82541:\n\tcase e1000_82542:\n\tcase e1000_82543:\n\tcase e1000_82544:\n\tcase e1000_82545:\n\tcase e1000_82546:\n\tcase e1000_82547:\n\tcase e1000_82571:\n\tcase e1000_82572:\n\tcase e1000_82573:\n\tcase e1000_82574:\n\tcase e1000_82583:\n\tcase e1000_i210:\n\tcase e1000_i211:\n\tdefault:\n\t\tPMD_INIT_LOG(ERR, \"Cannot support VMDq feature\");\n\t\treturn 0;\n\t}\n}\n\nstatic int\nigb_vmdq_rx_hw_configure(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_vmdq_rx_conf *cfg;\n\tstruct e1000_hw *hw;\n\tuint32_t mrqc, vt_ctl, vmolr, rctl;\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tcfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;\n\n\t/* Check if mac type can support VMDq, return value of 0 means NOT support */\n\tif (igb_is_vmdq_supported(dev) == 0)\n\t\treturn -1;\n\n\tigb_rss_disable(dev);\n\n\t/* RCTL: eanble VLAN filter */\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\trctl |= E1000_RCTL_VFE;\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\n\t/* MRQC: enable vmdq */\n\tmrqc = E1000_READ_REG(hw, E1000_MRQC);\n\tmrqc |= E1000_MRQC_ENABLE_VMDQ;\n\tE1000_WRITE_REG(hw, E1000_MRQC, mrqc);\n\n\t/* VTCTL: pool selection according to VLAN tag */\n\tvt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);\n\tif (cfg->enable_default_pool)\n\t\tvt_ctl |= (cfg->default_pool << E1000_VT_CTL_DEFAULT_POOL_SHIFT);\n\tvt_ctl |= E1000_VT_CTL_IGNORE_MAC;\n\tE1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);\n\n\tfor (i = 0; i < E1000_VMOLR_SIZE; i++) {\n\t\tvmolr = E1000_READ_REG(hw, E1000_VMOLR(i));\n\t\tvmolr &= ~(E1000_VMOLR_AUPE | E1000_VMOLR_ROMPE |\n\t\t\tE1000_VMOLR_ROPE | E1000_VMOLR_BAM |\n\t\t\tE1000_VMOLR_MPME);\n\n\t\tif (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG)\n\t\t\tvmolr |= E1000_VMOLR_AUPE;\n\t\tif (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC)\n\t\t\tvmolr |= E1000_VMOLR_ROMPE;\n\t\tif (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC)\n\t\t\tvmolr |= E1000_VMOLR_ROPE;\n\t\tif (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST)\n\t\t\tvmolr |= E1000_VMOLR_BAM;\n\t\tif (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST)\n\t\t\tvmolr |= E1000_VMOLR_MPME;\n\n\t\tE1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);\n\t}\n\n\t/*\n\t * VMOLR: set STRVLAN as 1 if IGMAC in VTCTL is set as 1\n\t * Both 82576 and 82580 support it\n\t */\n\tif (hw->mac.type != e1000_i350) {\n\t\tfor (i = 0; i < E1000_VMOLR_SIZE; i++) {\n\t\t\tvmolr = E1000_READ_REG(hw, E1000_VMOLR(i));\n\t\t\tvmolr |= E1000_VMOLR_STRVLAN;\n\t\t\tE1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);\n\t\t}\n\t}\n\n\t/* VFTA - enable all vlan filters */\n\tfor (i = 0; i < IGB_VFTA_SIZE; i++)\n\t\tE1000_WRITE_REG(hw, (E1000_VFTA+(i*4)), UINT32_MAX);\n\n\t/* VFRE: 8 pools enabling for rx, both 82576 and i350 support it */\n\tif (hw->mac.type != e1000_82580)\n\t\tE1000_WRITE_REG(hw, E1000_VFRE, E1000_MBVFICR_VFREQ_MASK);\n\n\t/*\n\t * RAH/RAL - allow pools to read specific mac addresses\n\t * In this case, all pools should be able to read from mac addr 0\n\t */\n\tE1000_WRITE_REG(hw, E1000_RAH(0), (E1000_RAH_AV | UINT16_MAX));\n\tE1000_WRITE_REG(hw, E1000_RAL(0), UINT32_MAX);\n\n\t/* VLVF: set up filters for vlan tags as configured */\n\tfor (i = 0; i < cfg->nb_pool_maps; i++) {\n\t\t/* set vlan id in VF register and set the valid bit */\n\t\tE1000_WRITE_REG(hw, E1000_VLVF(i), (E1000_VLVF_VLANID_ENABLE | \\\n (cfg->pool_map[i].vlan_id & ETH_VLAN_ID_MAX) | \\\n\t\t\t((cfg->pool_map[i].pools << E1000_VLVF_POOLSEL_SHIFT ) & \\\n\t\t\tE1000_VLVF_POOLSEL_MASK)));\n\t}\n\n\tE1000_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\n\n/*********************************************************************\n *\n * Enable receive unit.\n *\n **********************************************************************/\n\nstatic int\nigb_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)\n{\n\tstruct igb_rx_entry *rxe = rxq->sw_ring;\n\tuint64_t dma_addr;\n\tunsigned i;\n\n\t/* Initialize software ring entries. */\n\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n\t\tvolatile union e1000_adv_rx_desc *rxd;\n\t\tstruct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);\n\n\t\tif (mbuf == NULL) {\n\t\t\tPMD_INIT_LOG(ERR, \"RX mbuf alloc failed \"\n\t\t\t\t \"queue_id=%hu\", rxq->queue_id);\n\t\t\treturn (-ENOMEM);\n\t\t}\n\t\tdma_addr =\n\t\t\trte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));\n\t\trxd = &rxq->rx_ring[i];\n\t\trxd->read.hdr_addr = 0;\n\t\trxd->read.pkt_addr = dma_addr;\n\t\trxe[i].mbuf = mbuf;\n\t}\n\n\treturn 0;\n}\n\n#define E1000_MRQC_DEF_Q_SHIFT (3)\nstatic int\nigb_dev_mq_rx_configure(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw =\n\t\tE1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t mrqc;\n\n\tif (RTE_ETH_DEV_SRIOV(dev).active == ETH_8_POOLS) {\n\t\t/*\n\t\t * SRIOV active scheme\n\t\t * FIXME if support RSS together with VMDq & SRIOV\n\t\t */\n\t\tmrqc = E1000_MRQC_ENABLE_VMDQ;\n\t\t/* 011b Def_Q ignore, according to VT_CTL.DEF_PL */\n\t\tmrqc |= 0x3 << E1000_MRQC_DEF_Q_SHIFT;\n\t\tE1000_WRITE_REG(hw, E1000_MRQC, mrqc);\n\t} else if(RTE_ETH_DEV_SRIOV(dev).active == 0) {\n\t\t/*\n\t\t * SRIOV inactive scheme\n\t\t */\n\t\tswitch (dev->data->dev_conf.rxmode.mq_mode) {\n\t\t\tcase ETH_MQ_RX_RSS:\n\t\t\t\tigb_rss_configure(dev);\n\t\t\t\tbreak;\n\t\t\tcase ETH_MQ_RX_VMDQ_ONLY:\n\t\t\t\t/*Configure general VMDQ only RX parameters*/\n\t\t\t\tigb_vmdq_rx_hw_configure(dev);\n\t\t\t\tbreak;\n\t\t\tcase ETH_MQ_RX_NONE:\n\t\t\t\t/* if mq_mode is none, disable rss mode.*/\n\t\t\tdefault:\n\t\t\t\tigb_rss_disable(dev);\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nint\neth_igb_rx_init(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw;\n\tstruct igb_rx_queue *rxq;\n\tuint32_t rctl;\n\tuint32_t rxcsum;\n\tuint32_t srrctl;\n\tuint16_t buf_size;\n\tuint16_t rctl_bsize;\n\tuint16_t i;\n\tint ret;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tsrrctl = 0;\n\n\t/*\n\t * Make sure receives are disabled while setting\n\t * up the descriptor ring.\n\t */\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);\n\n\t/*\n\t * Configure support of jumbo frames, if any.\n\t */\n\tif (dev->data->dev_conf.rxmode.jumbo_frame == 1) {\n\t\trctl |= E1000_RCTL_LPE;\n\n\t\t/*\n\t\t * Set maximum packet length by default, and might be updated\n\t\t * together with enabling/disabling dual VLAN.\n\t\t */\n\t\tE1000_WRITE_REG(hw, E1000_RLPML,\n\t\t\tdev->data->dev_conf.rxmode.max_rx_pkt_len +\n\t\t\t\t\t\tVLAN_TAG_SIZE);\n\t} else\n\t\trctl &= ~E1000_RCTL_LPE;\n\n\t/* Configure and enable each RX queue. */\n\trctl_bsize = 0;\n\tdev->rx_pkt_burst = eth_igb_recv_pkts;\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tuint64_t bus_addr;\n\t\tuint32_t rxdctl;\n\n\t\trxq = dev->data->rx_queues[i];\n\n\t\t/* Allocate buffers for descriptor rings and set up queue */\n\t\tret = igb_alloc_rx_queue_mbufs(rxq);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\t/*\n\t\t * Reset crc_len in case it was changed after queue setup by a\n\t\t * call to configure\n\t\t */\n\t\trxq->crc_len =\n\t\t\t(uint8_t)(dev->data->dev_conf.rxmode.hw_strip_crc ?\n\t\t\t\t\t\t\t0 : ETHER_CRC_LEN);\n\n\t\tbus_addr = rxq->rx_ring_phys_addr;\n\t\tE1000_WRITE_REG(hw, E1000_RDLEN(rxq->reg_idx),\n\t\t\t\trxq->nb_rx_desc *\n\t\t\t\tsizeof(union e1000_adv_rx_desc));\n\t\tE1000_WRITE_REG(hw, E1000_RDBAH(rxq->reg_idx),\n\t\t\t\t(uint32_t)(bus_addr >> 32));\n\t\tE1000_WRITE_REG(hw, E1000_RDBAL(rxq->reg_idx), (uint32_t)bus_addr);\n\n\t\tsrrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;\n\n\t\t/*\n\t\t * Configure RX buffer size.\n\t\t */\n\t\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -\n\t\t\tRTE_PKTMBUF_HEADROOM);\n\t\tif (buf_size >= 1024) {\n\t\t\t/*\n\t\t\t * Configure the BSIZEPACKET field of the SRRCTL\n\t\t\t * register of the queue.\n\t\t\t * Value is in 1 KB resolution, from 1 KB to 127 KB.\n\t\t\t * If this field is equal to 0b, then RCTL.BSIZE\n\t\t\t * determines the RX packet buffer size.\n\t\t\t */\n\t\t\tsrrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &\n\t\t\t\t E1000_SRRCTL_BSIZEPKT_MASK);\n\t\t\tbuf_size = (uint16_t) ((srrctl &\n\t\t\t\t\t\tE1000_SRRCTL_BSIZEPKT_MASK) <<\n\t\t\t\t\t E1000_SRRCTL_BSIZEPKT_SHIFT);\n\n\t\t\t/* It adds dual VLAN length for supporting dual VLAN */\n\t\t\tif ((dev->data->dev_conf.rxmode.max_rx_pkt_len +\n\t\t\t\t\t\t2 * VLAN_TAG_SIZE) > buf_size){\n\t\t\t\tif (!dev->data->scattered_rx)\n\t\t\t\t\tPMD_INIT_LOG(DEBUG,\n\t\t\t\t\t\t \"forcing scatter mode\");\n\t\t\t\tdev->rx_pkt_burst = eth_igb_recv_scattered_pkts;\n\t\t\t\tdev->data->scattered_rx = 1;\n\t\t\t}\n\t\t} else {\n\t\t\t/*\n\t\t\t * Use BSIZE field of the device RCTL register.\n\t\t\t */\n\t\t\tif ((rctl_bsize == 0) || (rctl_bsize > buf_size))\n\t\t\t\trctl_bsize = buf_size;\n\t\t\tif (!dev->data->scattered_rx)\n\t\t\t\tPMD_INIT_LOG(DEBUG, \"forcing scatter mode\");\n\t\t\tdev->rx_pkt_burst = eth_igb_recv_scattered_pkts;\n\t\t\tdev->data->scattered_rx = 1;\n\t\t}\n\n\t\t/* Set if packets are dropped when no descriptors available */\n\t\tif (rxq->drop_en)\n\t\t\tsrrctl |= E1000_SRRCTL_DROP_EN;\n\n\t\tE1000_WRITE_REG(hw, E1000_SRRCTL(rxq->reg_idx), srrctl);\n\n\t\t/* Enable this RX queue. */\n\t\trxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rxq->reg_idx));\n\t\trxdctl |= E1000_RXDCTL_QUEUE_ENABLE;\n\t\trxdctl &= 0xFFF00000;\n\t\trxdctl |= (rxq->pthresh & 0x1F);\n\t\trxdctl |= ((rxq->hthresh & 0x1F) << 8);\n\t\trxdctl |= ((rxq->wthresh & 0x1F) << 16);\n\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(rxq->reg_idx), rxdctl);\n\t}\n\n\tif (dev->data->dev_conf.rxmode.enable_scatter) {\n\t\tif (!dev->data->scattered_rx)\n\t\t\tPMD_INIT_LOG(DEBUG, \"forcing scatter mode\");\n\t\tdev->rx_pkt_burst = eth_igb_recv_scattered_pkts;\n\t\tdev->data->scattered_rx = 1;\n\t}\n\n\t/*\n\t * Setup BSIZE field of RCTL register, if needed.\n\t * Buffer sizes >= 1024 are not [supposed to be] setup in the RCTL\n\t * register, since the code above configures the SRRCTL register of\n\t * the RX queue in such a case.\n\t * All configurable sizes are:\n\t * 16384: rctl |= (E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX);\n\t * 8192: rctl |= (E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX);\n\t * 4096: rctl |= (E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX);\n\t * 2048: rctl |= E1000_RCTL_SZ_2048;\n\t * 1024: rctl |= E1000_RCTL_SZ_1024;\n\t * 512: rctl |= E1000_RCTL_SZ_512;\n\t * 256: rctl |= E1000_RCTL_SZ_256;\n\t */\n\tif (rctl_bsize > 0) {\n\t\tif (rctl_bsize >= 512) /* 512 <= buf_size < 1024 - use 512 */\n\t\t\trctl |= E1000_RCTL_SZ_512;\n\t\telse /* 256 <= buf_size < 512 - use 256 */\n\t\t\trctl |= E1000_RCTL_SZ_256;\n\t}\n\n\t/*\n\t * Configure RSS if device configured with multiple RX queues.\n\t */\n\tigb_dev_mq_rx_configure(dev);\n\n\t/* Update the rctl since igb_dev_mq_rx_configure may change its value */\n\trctl |= E1000_READ_REG(hw, E1000_RCTL);\n\n\t/*\n\t * Setup the Checksum Register.\n\t * Receive Full-Packet Checksum Offload is mutually exclusive with RSS.\n\t */\n\trxcsum = E1000_READ_REG(hw, E1000_RXCSUM);\n\trxcsum |= E1000_RXCSUM_PCSD;\n\n\t/* Enable both L3/L4 rx checksum offload */\n\tif (dev->data->dev_conf.rxmode.hw_ip_checksum)\n\t\trxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);\n\telse\n\t\trxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);\n\tE1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);\n\n\t/* Setup the Receive Control Register. */\n\tif (dev->data->dev_conf.rxmode.hw_strip_crc) {\n\t\trctl |= E1000_RCTL_SECRC; /* Strip Ethernet CRC. */\n\n\t\t/* set STRCRC bit in all queues */\n\t\tif (hw->mac.type == e1000_i350 ||\n\t\t hw->mac.type == e1000_i210 ||\n\t\t hw->mac.type == e1000_i211 ||\n\t\t hw->mac.type == e1000_i354) {\n\t\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\t\t\trxq = dev->data->rx_queues[i];\n\t\t\t\tuint32_t dvmolr = E1000_READ_REG(hw,\n\t\t\t\t\tE1000_DVMOLR(rxq->reg_idx));\n\t\t\t\tdvmolr |= E1000_DVMOLR_STRCRC;\n\t\t\t\tE1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);\n\t\t\t}\n\t\t}\n\t} else {\n\t\trctl &= ~E1000_RCTL_SECRC; /* Do not Strip Ethernet CRC. */\n\n\t\t/* clear STRCRC bit in all queues */\n\t\tif (hw->mac.type == e1000_i350 ||\n\t\t hw->mac.type == e1000_i210 ||\n\t\t hw->mac.type == e1000_i211 ||\n\t\t hw->mac.type == e1000_i354) {\n\t\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\t\t\trxq = dev->data->rx_queues[i];\n\t\t\t\tuint32_t dvmolr = E1000_READ_REG(hw,\n\t\t\t\t\tE1000_DVMOLR(rxq->reg_idx));\n\t\t\t\tdvmolr &= ~E1000_DVMOLR_STRCRC;\n\t\t\t\tE1000_WRITE_REG(hw, E1000_DVMOLR(rxq->reg_idx), dvmolr);\n\t\t\t}\n\t\t}\n\t}\n\n\trctl &= ~(3 << E1000_RCTL_MO_SHIFT);\n\trctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |\n\t\tE1000_RCTL_RDMTS_HALF |\n\t\t(hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);\n\n\t/* Make sure VLAN Filters are off. */\n\tif (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_VMDQ_ONLY)\n\t\trctl &= ~E1000_RCTL_VFE;\n\t/* Don't store bad packets. */\n\trctl &= ~E1000_RCTL_SBP;\n\n\t/* Enable Receives. */\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\n\t/*\n\t * Setup the HW Rx Head and Tail Descriptor Pointers.\n\t * This needs to be done after enable.\n\t */\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\trxq = dev->data->rx_queues[i];\n\t\tE1000_WRITE_REG(hw, E1000_RDH(rxq->reg_idx), 0);\n\t\tE1000_WRITE_REG(hw, E1000_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);\n\t}\n\n\treturn 0;\n}\n\n/*********************************************************************\n *\n * Enable transmit unit.\n *\n **********************************************************************/\nvoid\neth_igb_tx_init(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw;\n\tstruct igb_tx_queue *txq;\n\tuint32_t tctl;\n\tuint32_t txdctl;\n\tuint16_t i;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/* Setup the Base and Length of the Tx Descriptor Rings. */\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tuint64_t bus_addr;\n\t\ttxq = dev->data->tx_queues[i];\n\t\tbus_addr = txq->tx_ring_phys_addr;\n\n\t\tE1000_WRITE_REG(hw, E1000_TDLEN(txq->reg_idx),\n\t\t\t\ttxq->nb_tx_desc *\n\t\t\t\tsizeof(union e1000_adv_tx_desc));\n\t\tE1000_WRITE_REG(hw, E1000_TDBAH(txq->reg_idx),\n\t\t\t\t(uint32_t)(bus_addr >> 32));\n\t\tE1000_WRITE_REG(hw, E1000_TDBAL(txq->reg_idx), (uint32_t)bus_addr);\n\n\t\t/* Setup the HW Tx Head and Tail descriptor pointers. */\n\t\tE1000_WRITE_REG(hw, E1000_TDT(txq->reg_idx), 0);\n\t\tE1000_WRITE_REG(hw, E1000_TDH(txq->reg_idx), 0);\n\n\t\t/* Setup Transmit threshold registers. */\n\t\ttxdctl = E1000_READ_REG(hw, E1000_TXDCTL(txq->reg_idx));\n\t\ttxdctl |= txq->pthresh & 0x1F;\n\t\ttxdctl |= ((txq->hthresh & 0x1F) << 8);\n\t\ttxdctl |= ((txq->wthresh & 0x1F) << 16);\n\t\ttxdctl |= E1000_TXDCTL_QUEUE_ENABLE;\n\t\tE1000_WRITE_REG(hw, E1000_TXDCTL(txq->reg_idx), txdctl);\n\t}\n\n\t/* Program the Transmit Control Register. */\n\ttctl = E1000_READ_REG(hw, E1000_TCTL);\n\ttctl &= ~E1000_TCTL_CT;\n\ttctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |\n\t\t (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));\n\n\te1000_config_collision_dist(hw);\n\n\t/* This write will effectively turn on the transmit unit. */\n\tE1000_WRITE_REG(hw, E1000_TCTL, tctl);\n}\n\n/*********************************************************************\n *\n * Enable VF receive unit.\n *\n **********************************************************************/\nint\neth_igbvf_rx_init(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw;\n\tstruct igb_rx_queue *rxq;\n\tuint32_t srrctl;\n\tuint16_t buf_size;\n\tuint16_t rctl_bsize;\n\tuint16_t i;\n\tint ret;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/* setup MTU */\n\te1000_rlpml_set_vf(hw,\n\t\t(uint16_t)(dev->data->dev_conf.rxmode.max_rx_pkt_len +\n\t\tVLAN_TAG_SIZE));\n\n\t/* Configure and enable each RX queue. */\n\trctl_bsize = 0;\n\tdev->rx_pkt_burst = eth_igb_recv_pkts;\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tuint64_t bus_addr;\n\t\tuint32_t rxdctl;\n\n\t\trxq = dev->data->rx_queues[i];\n\n\t\t/* Allocate buffers for descriptor rings and set up queue */\n\t\tret = igb_alloc_rx_queue_mbufs(rxq);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\tbus_addr = rxq->rx_ring_phys_addr;\n\t\tE1000_WRITE_REG(hw, E1000_RDLEN(i),\n\t\t\t\trxq->nb_rx_desc *\n\t\t\t\tsizeof(union e1000_adv_rx_desc));\n\t\tE1000_WRITE_REG(hw, E1000_RDBAH(i),\n\t\t\t\t(uint32_t)(bus_addr >> 32));\n\t\tE1000_WRITE_REG(hw, E1000_RDBAL(i), (uint32_t)bus_addr);\n\n\t\tsrrctl = E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;\n\n\t\t/*\n\t\t * Configure RX buffer size.\n\t\t */\n\t\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -\n\t\t\tRTE_PKTMBUF_HEADROOM);\n\t\tif (buf_size >= 1024) {\n\t\t\t/*\n\t\t\t * Configure the BSIZEPACKET field of the SRRCTL\n\t\t\t * register of the queue.\n\t\t\t * Value is in 1 KB resolution, from 1 KB to 127 KB.\n\t\t\t * If this field is equal to 0b, then RCTL.BSIZE\n\t\t\t * determines the RX packet buffer size.\n\t\t\t */\n\t\t\tsrrctl |= ((buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) &\n\t\t\t\t E1000_SRRCTL_BSIZEPKT_MASK);\n\t\t\tbuf_size = (uint16_t) ((srrctl &\n\t\t\t\t\t\tE1000_SRRCTL_BSIZEPKT_MASK) <<\n\t\t\t\t\t E1000_SRRCTL_BSIZEPKT_SHIFT);\n\n\t\t\t/* It adds dual VLAN length for supporting dual VLAN */\n\t\t\tif ((dev->data->dev_conf.rxmode.max_rx_pkt_len +\n\t\t\t\t\t\t2 * VLAN_TAG_SIZE) > buf_size){\n\t\t\t\tif (!dev->data->scattered_rx)\n\t\t\t\t\tPMD_INIT_LOG(DEBUG,\n\t\t\t\t\t\t \"forcing scatter mode\");\n\t\t\t\tdev->rx_pkt_burst = eth_igb_recv_scattered_pkts;\n\t\t\t\tdev->data->scattered_rx = 1;\n\t\t\t}\n\t\t} else {\n\t\t\t/*\n\t\t\t * Use BSIZE field of the device RCTL register.\n\t\t\t */\n\t\t\tif ((rctl_bsize == 0) || (rctl_bsize > buf_size))\n\t\t\t\trctl_bsize = buf_size;\n\t\t\tif (!dev->data->scattered_rx)\n\t\t\t\tPMD_INIT_LOG(DEBUG, \"forcing scatter mode\");\n\t\t\tdev->rx_pkt_burst = eth_igb_recv_scattered_pkts;\n\t\t\tdev->data->scattered_rx = 1;\n\t\t}\n\n\t\t/* Set if packets are dropped when no descriptors available */\n\t\tif (rxq->drop_en)\n\t\t\tsrrctl |= E1000_SRRCTL_DROP_EN;\n\n\t\tE1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);\n\n\t\t/* Enable this RX queue. */\n\t\trxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));\n\t\trxdctl |= E1000_RXDCTL_QUEUE_ENABLE;\n\t\trxdctl &= 0xFFF00000;\n\t\trxdctl |= (rxq->pthresh & 0x1F);\n\t\trxdctl |= ((rxq->hthresh & 0x1F) << 8);\n\t\tif (hw->mac.type == e1000_vfadapt) {\n\t\t\t/*\n\t\t\t * Workaround of 82576 VF Erratum\n\t\t\t * force set WTHRESH to 1\n\t\t\t * to avoid Write-Back not triggered sometimes\n\t\t\t */\n\t\t\trxdctl |= 0x10000;\n\t\t\tPMD_INIT_LOG(DEBUG, \"Force set RX WTHRESH to 1 !\");\n\t\t}\n\t\telse\n\t\t\trxdctl |= ((rxq->wthresh & 0x1F) << 16);\n\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);\n\t}\n\n\tif (dev->data->dev_conf.rxmode.enable_scatter) {\n\t\tif (!dev->data->scattered_rx)\n\t\t\tPMD_INIT_LOG(DEBUG, \"forcing scatter mode\");\n\t\tdev->rx_pkt_burst = eth_igb_recv_scattered_pkts;\n\t\tdev->data->scattered_rx = 1;\n\t}\n\n\t/*\n\t * Setup the HW Rx Head and Tail Descriptor Pointers.\n\t * This needs to be done after enable.\n\t */\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\trxq = dev->data->rx_queues[i];\n\t\tE1000_WRITE_REG(hw, E1000_RDH(i), 0);\n\t\tE1000_WRITE_REG(hw, E1000_RDT(i), rxq->nb_rx_desc - 1);\n\t}\n\n\treturn 0;\n}\n\n/*********************************************************************\n *\n * Enable VF transmit unit.\n *\n **********************************************************************/\nvoid\neth_igbvf_tx_init(struct rte_eth_dev *dev)\n{\n\tstruct e1000_hw *hw;\n\tstruct igb_tx_queue *txq;\n\tuint32_t txdctl;\n\tuint16_t i;\n\n\thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/* Setup the Base and Length of the Tx Descriptor Rings. */\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tuint64_t bus_addr;\n\n\t\ttxq = dev->data->tx_queues[i];\n\t\tbus_addr = txq->tx_ring_phys_addr;\n\t\tE1000_WRITE_REG(hw, E1000_TDLEN(i),\n\t\t\t\ttxq->nb_tx_desc *\n\t\t\t\tsizeof(union e1000_adv_tx_desc));\n\t\tE1000_WRITE_REG(hw, E1000_TDBAH(i),\n\t\t\t\t(uint32_t)(bus_addr >> 32));\n\t\tE1000_WRITE_REG(hw, E1000_TDBAL(i), (uint32_t)bus_addr);\n\n\t\t/* Setup the HW Tx Head and Tail descriptor pointers. */\n\t\tE1000_WRITE_REG(hw, E1000_TDT(i), 0);\n\t\tE1000_WRITE_REG(hw, E1000_TDH(i), 0);\n\n\t\t/* Setup Transmit threshold registers. */\n\t\ttxdctl = E1000_READ_REG(hw, E1000_TXDCTL(i));\n\t\ttxdctl |= txq->pthresh & 0x1F;\n\t\ttxdctl |= ((txq->hthresh & 0x1F) << 8);\n\t\tif (hw->mac.type == e1000_82576) {\n\t\t\t/*\n\t\t\t * Workaround of 82576 VF Erratum\n\t\t\t * force set WTHRESH to 1\n\t\t\t * to avoid Write-Back not triggered sometimes\n\t\t\t */\n\t\t\ttxdctl |= 0x10000;\n\t\t\tPMD_INIT_LOG(DEBUG, \"Force set TX WTHRESH to 1 !\");\n\t\t}\n\t\telse\n\t\t\ttxdctl |= ((txq->wthresh & 0x1F) << 16);\n\t\ttxdctl |= E1000_TXDCTL_QUEUE_ENABLE;\n\t\tE1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);\n\t}\n\n}\n" }, { "path": "drivers/net/enic/LICENSE", "content": " * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n" }, { "path": "drivers/net/enic/Makefile", "content": "#\n# Copyright 2008-2014 Cisco Systems, Inc. All rights reserved.\n# Copyright 2007 Nuova Systems, Inc. All rights reserved.\n#\n# Copyright (c) 2014, Cisco Systems, Inc.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# 1. Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n#\n# 2. Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n# POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_enic.a\n\nEXPORT_MAP := rte_pmd_enic_version.map\n\nLIBABIVER := 1\n\nCFLAGS += -I$(SRCDIR)/base/\nCFLAGS += -I$(SRCDIR)\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS) -Wno-strict-aliasing\n\nVPATH += $(SRCDIR)/src\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += enic_ethdev.c\nSRCS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += enic_main.c\nSRCS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += enic_clsf.c\nSRCS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += enic_res.c\nSRCS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += base/vnic_cq.c\nSRCS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += base/vnic_wq.c\nSRCS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += base/vnic_dev.c\nSRCS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += base/vnic_intr.c\nSRCS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += base/vnic_rq.c\nSRCS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += base/vnic_rss.c\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += lib/librte_eal lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += lib/librte_mempool lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += lib/librte_net\nDEPDIRS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += lib/librte_hash\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/enic/base/cq_desc.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: cq_desc.h 129574 2013-04-26 22:11:14Z rfaucett $\"\n\n#ifndef _CQ_DESC_H_\n#define _CQ_DESC_H_\n\n/*\n * Completion queue descriptor types\n */\nenum cq_desc_types {\n\tCQ_DESC_TYPE_WQ_ENET = 0,\n\tCQ_DESC_TYPE_DESC_COPY = 1,\n\tCQ_DESC_TYPE_WQ_EXCH = 2,\n\tCQ_DESC_TYPE_RQ_ENET = 3,\n\tCQ_DESC_TYPE_RQ_FCP = 4,\n\tCQ_DESC_TYPE_IOMMU_MISS = 5,\n\tCQ_DESC_TYPE_SGL = 6,\n\tCQ_DESC_TYPE_CLASSIFIER = 7,\n\tCQ_DESC_TYPE_TEST = 127,\n};\n\n/* Completion queue descriptor: 16B\n *\n * All completion queues have this basic layout. The\n * type_specfic area is unique for each completion\n * queue type.\n */\nstruct cq_desc {\n\t__le16 completed_index;\n\t__le16 q_number;\n\tu8 type_specfic[11];\n\tu8 type_color;\n};\n\n#define CQ_DESC_TYPE_BITS 4\n#define CQ_DESC_TYPE_MASK ((1 << CQ_DESC_TYPE_BITS) - 1)\n#define CQ_DESC_COLOR_MASK 1\n#define CQ_DESC_COLOR_SHIFT 7\n#define CQ_DESC_Q_NUM_BITS 10\n#define CQ_DESC_Q_NUM_MASK ((1 << CQ_DESC_Q_NUM_BITS) - 1)\n#define CQ_DESC_COMP_NDX_BITS 12\n#define CQ_DESC_COMP_NDX_MASK ((1 << CQ_DESC_COMP_NDX_BITS) - 1)\n\nstatic inline void cq_color_enc(struct cq_desc *desc, const u8 color)\n{\n\tif (color)\n\t\tdesc->type_color |= (1 << CQ_DESC_COLOR_SHIFT);\n\telse\n\t\tdesc->type_color &= ~(1 << CQ_DESC_COLOR_SHIFT);\n}\n\nstatic inline void cq_desc_enc(struct cq_desc *desc,\n\tconst u8 type, const u8 color, const u16 q_number,\n\tconst u16 completed_index)\n{\n\tdesc->type_color = (type & CQ_DESC_TYPE_MASK) |\n\t\t((color & CQ_DESC_COLOR_MASK) << CQ_DESC_COLOR_SHIFT);\n\tdesc->q_number = cpu_to_le16(q_number & CQ_DESC_Q_NUM_MASK);\n\tdesc->completed_index = cpu_to_le16(completed_index &\n\t\tCQ_DESC_COMP_NDX_MASK);\n}\n\nstatic inline void cq_desc_dec(const struct cq_desc *desc_arg,\n\tu8 *type, u8 *color, u16 *q_number, u16 *completed_index)\n{\n\tconst struct cq_desc *desc = desc_arg;\n\tconst u8 type_color = desc->type_color;\n\n\t*color = (type_color >> CQ_DESC_COLOR_SHIFT) & CQ_DESC_COLOR_MASK;\n\n\t/*\n\t * Make sure color bit is read from desc *before* other fields\n\t * are read from desc. Hardware guarantees color bit is last\n\t * bit (byte) written. Adding the rmb() prevents the compiler\n\t * and/or CPU from reordering the reads which would potentially\n\t * result in reading stale values.\n\t */\n\n\trmb();\n\n\t*type = type_color & CQ_DESC_TYPE_MASK;\n\t*q_number = le16_to_cpu(desc->q_number) & CQ_DESC_Q_NUM_MASK;\n\t*completed_index = le16_to_cpu(desc->completed_index) &\n\t\tCQ_DESC_COMP_NDX_MASK;\n}\n\nstatic inline void cq_color_dec(const struct cq_desc *desc_arg, u8 *color)\n{\n\tvolatile const struct cq_desc *desc = desc_arg;\n\n\t*color = (desc->type_color >> CQ_DESC_COLOR_SHIFT) & CQ_DESC_COLOR_MASK;\n}\n\n#endif /* _CQ_DESC_H_ */\n" }, { "path": "drivers/net/enic/base/cq_enet_desc.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: cq_enet_desc.h 160468 2014-02-18 09:50:15Z gvaradar $\"\n\n#ifndef _CQ_ENET_DESC_H_\n#define _CQ_ENET_DESC_H_\n\n#include \"cq_desc.h\"\n\n/* Ethernet completion queue descriptor: 16B */\nstruct cq_enet_wq_desc {\n\t__le16 completed_index;\n\t__le16 q_number;\n\tu8 reserved[11];\n\tu8 type_color;\n};\n\nstatic inline void cq_enet_wq_desc_enc(struct cq_enet_wq_desc *desc,\n\tu8 type, u8 color, u16 q_number, u16 completed_index)\n{\n\tcq_desc_enc((struct cq_desc *)desc, type,\n\t\tcolor, q_number, completed_index);\n}\n\nstatic inline void cq_enet_wq_desc_dec(struct cq_enet_wq_desc *desc,\n\tu8 *type, u8 *color, u16 *q_number, u16 *completed_index)\n{\n\tcq_desc_dec((struct cq_desc *)desc, type,\n\t\tcolor, q_number, completed_index);\n}\n\n/* Completion queue descriptor: Ethernet receive queue, 16B */\nstruct cq_enet_rq_desc {\n\t__le16 completed_index_flags;\n\t__le16 q_number_rss_type_flags;\n\t__le32 rss_hash;\n\t__le16 bytes_written_flags;\n\t__le16 vlan;\n\t__le16 checksum_fcoe;\n\tu8 flags;\n\tu8 type_color;\n};\n\n#define CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT (0x1 << 12)\n#define CQ_ENET_RQ_DESC_FLAGS_FCOE (0x1 << 13)\n#define CQ_ENET_RQ_DESC_FLAGS_EOP (0x1 << 14)\n#define CQ_ENET_RQ_DESC_FLAGS_SOP (0x1 << 15)\n\n#define CQ_ENET_RQ_DESC_RSS_TYPE_BITS 4\n#define CQ_ENET_RQ_DESC_RSS_TYPE_MASK \\\n\t((1 << CQ_ENET_RQ_DESC_RSS_TYPE_BITS) - 1)\n#define CQ_ENET_RQ_DESC_RSS_TYPE_NONE 0\n#define CQ_ENET_RQ_DESC_RSS_TYPE_IPv4 1\n#define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv4 2\n#define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6 3\n#define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6 4\n#define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6_EX 5\n#define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6_EX 6\n\n#define CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC (0x1 << 14)\n\n#define CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS 14\n#define CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK \\\n\t((1 << CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS) - 1)\n#define CQ_ENET_RQ_DESC_FLAGS_TRUNCATED (0x1 << 14)\n#define CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED (0x1 << 15)\n\n#define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS 12\n#define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_MASK \\\n\t((1 << CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS) - 1)\n#define CQ_ENET_RQ_DESC_VLAN_TCI_CFI_MASK (0x1 << 12)\n#define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS 3\n#define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_MASK \\\n\t((1 << CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS) - 1)\n#define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_SHIFT 13\n\n#define CQ_ENET_RQ_DESC_FCOE_SOF_BITS 8\n#define CQ_ENET_RQ_DESC_FCOE_SOF_MASK \\\n\t((1 << CQ_ENET_RQ_DESC_FCOE_SOF_BITS) - 1)\n#define CQ_ENET_RQ_DESC_FCOE_EOF_BITS 8\n#define CQ_ENET_RQ_DESC_FCOE_EOF_MASK \\\n\t((1 << CQ_ENET_RQ_DESC_FCOE_EOF_BITS) - 1)\n#define CQ_ENET_RQ_DESC_FCOE_EOF_SHIFT 8\n\n#define CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK (0x1 << 0)\n#define CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK (0x1 << 0)\n#define CQ_ENET_RQ_DESC_FLAGS_UDP (0x1 << 1)\n#define CQ_ENET_RQ_DESC_FCOE_ENC_ERROR (0x1 << 1)\n#define CQ_ENET_RQ_DESC_FLAGS_TCP (0x1 << 2)\n#define CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK (0x1 << 3)\n#define CQ_ENET_RQ_DESC_FLAGS_IPV6 (0x1 << 4)\n#define CQ_ENET_RQ_DESC_FLAGS_IPV4 (0x1 << 5)\n#define CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT (0x1 << 6)\n#define CQ_ENET_RQ_DESC_FLAGS_FCS_OK (0x1 << 7)\n\nstatic inline void cq_enet_rq_desc_enc(struct cq_enet_rq_desc *desc,\n\tu8 type, u8 color, u16 q_number, u16 completed_index,\n\tu8 ingress_port, u8 fcoe, u8 eop, u8 sop, u8 rss_type, u8 csum_not_calc,\n\tu32 rss_hash, u16 bytes_written, u8 packet_error, u8 vlan_stripped,\n\tu16 vlan, u16 checksum, u8 fcoe_sof, u8 fcoe_fc_crc_ok,\n\tu8 fcoe_enc_error, u8 fcoe_eof, u8 tcp_udp_csum_ok, u8 udp, u8 tcp,\n\tu8 ipv4_csum_ok, u8 ipv6, u8 ipv4, u8 ipv4_fragment, u8 fcs_ok)\n{\n\tcq_desc_enc((struct cq_desc *)desc, type,\n\t\tcolor, q_number, completed_index);\n\n\tdesc->completed_index_flags |= cpu_to_le16(\n\t\t(ingress_port ? CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT : 0) |\n\t\t(fcoe ? CQ_ENET_RQ_DESC_FLAGS_FCOE : 0) |\n\t\t(eop ? CQ_ENET_RQ_DESC_FLAGS_EOP : 0) |\n\t\t(sop ? CQ_ENET_RQ_DESC_FLAGS_SOP : 0));\n\n\tdesc->q_number_rss_type_flags |= cpu_to_le16(\n\t\t((rss_type & CQ_ENET_RQ_DESC_RSS_TYPE_MASK) <<\n\t\tCQ_DESC_Q_NUM_BITS) |\n\t\t(csum_not_calc ? CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC : 0));\n\n\tdesc->rss_hash = cpu_to_le32(rss_hash);\n\n\tdesc->bytes_written_flags = cpu_to_le16(\n\t\t(bytes_written & CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK) |\n\t\t(packet_error ? CQ_ENET_RQ_DESC_FLAGS_TRUNCATED : 0) |\n\t\t(vlan_stripped ? CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED : 0));\n\n\tdesc->vlan = cpu_to_le16(vlan);\n\n\tif (fcoe) {\n\t\tdesc->checksum_fcoe = cpu_to_le16(\n\t\t\t(fcoe_sof & CQ_ENET_RQ_DESC_FCOE_SOF_MASK) |\n\t\t\t((fcoe_eof & CQ_ENET_RQ_DESC_FCOE_EOF_MASK) <<\n\t\t\t\tCQ_ENET_RQ_DESC_FCOE_EOF_SHIFT));\n\t} else {\n\t\tdesc->checksum_fcoe = cpu_to_le16(checksum);\n\t}\n\n\tdesc->flags =\n\t\t(tcp_udp_csum_ok ? CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK : 0) |\n\t\t(udp ? CQ_ENET_RQ_DESC_FLAGS_UDP : 0) |\n\t\t(tcp ? CQ_ENET_RQ_DESC_FLAGS_TCP : 0) |\n\t\t(ipv4_csum_ok ? CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK : 0) |\n\t\t(ipv6 ? CQ_ENET_RQ_DESC_FLAGS_IPV6 : 0) |\n\t\t(ipv4 ? CQ_ENET_RQ_DESC_FLAGS_IPV4 : 0) |\n\t\t(ipv4_fragment ? CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT : 0) |\n\t\t(fcs_ok ? CQ_ENET_RQ_DESC_FLAGS_FCS_OK : 0) |\n\t\t(fcoe_fc_crc_ok ? CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK : 0) |\n\t\t(fcoe_enc_error ? CQ_ENET_RQ_DESC_FCOE_ENC_ERROR : 0);\n}\n\nstatic inline void cq_enet_rq_desc_dec(struct cq_enet_rq_desc *desc,\n\tu8 *type, u8 *color, u16 *q_number, u16 *completed_index,\n\tu8 *ingress_port, u8 *fcoe, u8 *eop, u8 *sop, u8 *rss_type,\n\tu8 *csum_not_calc, u32 *rss_hash, u16 *bytes_written, u8 *packet_error,\n\tu8 *vlan_stripped, u16 *vlan_tci, u16 *checksum, u8 *fcoe_sof,\n\tu8 *fcoe_fc_crc_ok, u8 *fcoe_enc_error, u8 *fcoe_eof,\n\tu8 *tcp_udp_csum_ok, u8 *udp, u8 *tcp, u8 *ipv4_csum_ok,\n\tu8 *ipv6, u8 *ipv4, u8 *ipv4_fragment, u8 *fcs_ok)\n{\n\tu16 completed_index_flags;\n\tu16 q_number_rss_type_flags;\n\tu16 bytes_written_flags;\n\n\tcq_desc_dec((struct cq_desc *)desc, type,\n\t\tcolor, q_number, completed_index);\n\n\tcompleted_index_flags = le16_to_cpu(desc->completed_index_flags);\n\tq_number_rss_type_flags =\n\t\tle16_to_cpu(desc->q_number_rss_type_flags);\n\tbytes_written_flags = le16_to_cpu(desc->bytes_written_flags);\n\n\t*ingress_port = (completed_index_flags &\n\t\tCQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT) ? 1 : 0;\n\t*fcoe = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_FCOE) ?\n\t\t1 : 0;\n\t*eop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_EOP) ?\n\t\t1 : 0;\n\t*sop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_SOP) ?\n\t\t1 : 0;\n\n\t*rss_type = (u8)((q_number_rss_type_flags >> CQ_DESC_Q_NUM_BITS) &\n\t\tCQ_ENET_RQ_DESC_RSS_TYPE_MASK);\n\t*csum_not_calc = (q_number_rss_type_flags &\n\t\tCQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ? 1 : 0;\n\n\t*rss_hash = le32_to_cpu(desc->rss_hash);\n\n\t*bytes_written = bytes_written_flags &\n\t\tCQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;\n\t*packet_error = (bytes_written_flags &\n\t\tCQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ? 1 : 0;\n\t*vlan_stripped = (bytes_written_flags &\n\t\tCQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) ? 1 : 0;\n\n\t/*\n\t * Tag Control Information(16) = user_priority(3) + cfi(1) + vlan(12)\n\t */\n\t*vlan_tci = le16_to_cpu(desc->vlan);\n\n\tif (*fcoe) {\n\t\t*fcoe_sof = (u8)(le16_to_cpu(desc->checksum_fcoe) &\n\t\t\tCQ_ENET_RQ_DESC_FCOE_SOF_MASK);\n\t\t*fcoe_fc_crc_ok = (desc->flags &\n\t\t\tCQ_ENET_RQ_DESC_FCOE_FC_CRC_OK) ? 1 : 0;\n\t\t*fcoe_enc_error = (desc->flags &\n\t\t\tCQ_ENET_RQ_DESC_FCOE_ENC_ERROR) ? 1 : 0;\n\t\t*fcoe_eof = (u8)((le16_to_cpu(desc->checksum_fcoe) >>\n\t\t\tCQ_ENET_RQ_DESC_FCOE_EOF_SHIFT) &\n\t\t\tCQ_ENET_RQ_DESC_FCOE_EOF_MASK);\n\t\t*checksum = 0;\n\t} else {\n\t\t*fcoe_sof = 0;\n\t\t*fcoe_fc_crc_ok = 0;\n\t\t*fcoe_enc_error = 0;\n\t\t*fcoe_eof = 0;\n\t\t*checksum = le16_to_cpu(desc->checksum_fcoe);\n\t}\n\n\t*tcp_udp_csum_ok =\n\t\t(desc->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ? 1 : 0;\n\t*udp = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_UDP) ? 1 : 0;\n\t*tcp = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_TCP) ? 1 : 0;\n\t*ipv4_csum_ok =\n\t\t(desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ? 1 : 0;\n\t*ipv6 = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV6) ? 1 : 0;\n\t*ipv4 = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4) ? 1 : 0;\n\t*ipv4_fragment =\n\t\t(desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT) ? 1 : 0;\n\t*fcs_ok = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_FCS_OK) ? 1 : 0;\n}\n\n#endif /* _CQ_ENET_DESC_H_ */\n" }, { "path": "drivers/net/enic/base/rq_enet_desc.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: rq_enet_desc.h 59839 2010-09-27 20:36:31Z roprabhu $\"\n\n#ifndef _RQ_ENET_DESC_H_\n#define _RQ_ENET_DESC_H_\n\n/* Ethernet receive queue descriptor: 16B */\nstruct rq_enet_desc {\n\t__le64 address;\n\t__le16 length_type;\n\tu8 reserved[6];\n};\n\nenum rq_enet_type_types {\n\tRQ_ENET_TYPE_ONLY_SOP = 0,\n\tRQ_ENET_TYPE_NOT_SOP = 1,\n\tRQ_ENET_TYPE_RESV2 = 2,\n\tRQ_ENET_TYPE_RESV3 = 3,\n};\n\n#define RQ_ENET_ADDR_BITS\t\t64\n#define RQ_ENET_LEN_BITS\t\t14\n#define RQ_ENET_LEN_MASK\t\t((1 << RQ_ENET_LEN_BITS) - 1)\n#define RQ_ENET_TYPE_BITS\t\t2\n#define RQ_ENET_TYPE_MASK\t\t((1 << RQ_ENET_TYPE_BITS) - 1)\n\nstatic inline void rq_enet_desc_enc(struct rq_enet_desc *desc,\n\tu64 address, u8 type, u16 length)\n{\n\tdesc->address = cpu_to_le64(address);\n\tdesc->length_type = cpu_to_le16((length & RQ_ENET_LEN_MASK) |\n\t\t((type & RQ_ENET_TYPE_MASK) << RQ_ENET_LEN_BITS));\n}\n\nstatic inline void rq_enet_desc_dec(struct rq_enet_desc *desc,\n\tu64 *address, u8 *type, u16 *length)\n{\n\t*address = le64_to_cpu(desc->address);\n\t*length = le16_to_cpu(desc->length_type) & RQ_ENET_LEN_MASK;\n\t*type = (u8)((le16_to_cpu(desc->length_type) >> RQ_ENET_LEN_BITS) &\n\t\tRQ_ENET_TYPE_MASK);\n}\n\n#endif /* _RQ_ENET_DESC_H_ */\n" }, { "path": "drivers/net/enic/base/vnic_cq.c", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_cq.c 171146 2014-05-02 07:08:20Z ssujith $\"\n\n#include \"vnic_dev.h\"\n#include \"vnic_cq.h\"\n\nint vnic_cq_mem_size(struct vnic_cq *cq, unsigned int desc_count,\n\tunsigned int desc_size)\n{\n\tint mem_size;\n\n\tmem_size = vnic_dev_desc_ring_size(&cq->ring, desc_count, desc_size);\n\n\treturn mem_size;\n}\n\nvoid vnic_cq_free(struct vnic_cq *cq)\n{\n\tvnic_dev_free_desc_ring(cq->vdev, &cq->ring);\n\n\tcq->ctrl = NULL;\n}\n\nint vnic_cq_alloc(struct vnic_dev *vdev, struct vnic_cq *cq, unsigned int index,\n\tunsigned int socket_id,\n\tunsigned int desc_count, unsigned int desc_size)\n{\n\tint err;\n\tchar res_name[NAME_MAX];\n\tstatic int instance;\n\n\tcq->index = index;\n\tcq->vdev = vdev;\n\n\tcq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_CQ, index);\n\tif (!cq->ctrl) {\n\t\tpr_err(\"Failed to hook CQ[%d] resource\\n\", index);\n\t\treturn -EINVAL;\n\t}\n\n\tsnprintf(res_name, sizeof(res_name), \"%d-cq-%d\", instance++, index);\n\terr = vnic_dev_alloc_desc_ring(vdev, &cq->ring, desc_count, desc_size,\n\t\tsocket_id, res_name);\n\tif (err)\n\t\treturn err;\n\n\treturn 0;\n}\n\nvoid vnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable,\n\tunsigned int color_enable, unsigned int cq_head, unsigned int cq_tail,\n\tunsigned int cq_tail_color, unsigned int interrupt_enable,\n\tunsigned int cq_entry_enable, unsigned int cq_message_enable,\n\tunsigned int interrupt_offset, u64 cq_message_addr)\n{\n\tu64 paddr;\n\n\tpaddr = (u64)cq->ring.base_addr | VNIC_PADDR_TARGET;\n\twriteq(paddr, &cq->ctrl->ring_base);\n\tiowrite32(cq->ring.desc_count, &cq->ctrl->ring_size);\n\tiowrite32(flow_control_enable, &cq->ctrl->flow_control_enable);\n\tiowrite32(color_enable, &cq->ctrl->color_enable);\n\tiowrite32(cq_head, &cq->ctrl->cq_head);\n\tiowrite32(cq_tail, &cq->ctrl->cq_tail);\n\tiowrite32(cq_tail_color, &cq->ctrl->cq_tail_color);\n\tiowrite32(interrupt_enable, &cq->ctrl->interrupt_enable);\n\tiowrite32(cq_entry_enable, &cq->ctrl->cq_entry_enable);\n\tiowrite32(cq_message_enable, &cq->ctrl->cq_message_enable);\n\tiowrite32(interrupt_offset, &cq->ctrl->interrupt_offset);\n\twriteq(cq_message_addr, &cq->ctrl->cq_message_addr);\n\n\tcq->interrupt_offset = interrupt_offset;\n}\n\nvoid vnic_cq_clean(struct vnic_cq *cq)\n{\n\tcq->to_clean = 0;\n\tcq->last_color = 0;\n\n\tiowrite32(0, &cq->ctrl->cq_head);\n\tiowrite32(0, &cq->ctrl->cq_tail);\n\tiowrite32(1, &cq->ctrl->cq_tail_color);\n\n\tvnic_dev_clear_desc_ring(&cq->ring);\n}\n" }, { "path": "drivers/net/enic/base/vnic_cq.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_cq.h 173398 2014-05-19 09:17:02Z gvaradar $\"\n\n#ifndef _VNIC_CQ_H_\n#define _VNIC_CQ_H_\n\n#include \n\n#include \"cq_desc.h\"\n#include \"vnic_dev.h\"\n\n/* Completion queue control */\nstruct vnic_cq_ctrl {\n\tu64 ring_base;\t\t\t/* 0x00 */\n\tu32 ring_size;\t\t\t/* 0x08 */\n\tu32 pad0;\n\tu32 flow_control_enable;\t/* 0x10 */\n\tu32 pad1;\n\tu32 color_enable;\t\t/* 0x18 */\n\tu32 pad2;\n\tu32 cq_head;\t\t\t/* 0x20 */\n\tu32 pad3;\n\tu32 cq_tail;\t\t\t/* 0x28 */\n\tu32 pad4;\n\tu32 cq_tail_color;\t\t/* 0x30 */\n\tu32 pad5;\n\tu32 interrupt_enable;\t\t/* 0x38 */\n\tu32 pad6;\n\tu32 cq_entry_enable;\t\t/* 0x40 */\n\tu32 pad7;\n\tu32 cq_message_enable;\t\t/* 0x48 */\n\tu32 pad8;\n\tu32 interrupt_offset;\t\t/* 0x50 */\n\tu32 pad9;\n\tu64 cq_message_addr;\t\t/* 0x58 */\n\tu32 pad10;\n};\n\n#ifdef ENIC_AIC\nstruct vnic_rx_bytes_counter {\n\tunsigned int small_pkt_bytes_cnt;\n\tunsigned int large_pkt_bytes_cnt;\n};\n#endif\n\nstruct vnic_cq {\n\tunsigned int index;\n\tstruct vnic_dev *vdev;\n\tstruct vnic_cq_ctrl __iomem *ctrl; /* memory-mapped */\n\tstruct vnic_dev_ring ring;\n\tunsigned int to_clean;\n\tunsigned int last_color;\n\tunsigned int interrupt_offset;\n#ifdef ENIC_AIC\n\tstruct vnic_rx_bytes_counter pkt_size_counter;\n\tunsigned int cur_rx_coal_timeval;\n\tunsigned int tobe_rx_coal_timeval;\n\tktime_t prev_ts;\n#endif\n};\n\nstatic inline unsigned int vnic_cq_service(struct vnic_cq *cq,\n\tunsigned int work_to_do,\n\tint (*q_service)(struct vnic_dev *vdev, struct cq_desc *cq_desc,\n\tu8 type, u16 q_number, u16 completed_index, void *opaque),\n\tvoid *opaque)\n{\n\tstruct cq_desc *cq_desc;\n\tunsigned int work_done = 0;\n\tu16 q_number, completed_index;\n\tu8 type, color;\n\tstruct rte_mbuf **rx_pkts = opaque;\n\tunsigned int ret;\n\n\tcq_desc = (struct cq_desc *)((u8 *)cq->ring.descs +\n\t\tcq->ring.desc_size * cq->to_clean);\n\tcq_desc_dec(cq_desc, &type, &color,\n\t\t&q_number, &completed_index);\n\n\twhile (color != cq->last_color) {\n\t\tif (opaque)\n\t\t\topaque = (void *)&(rx_pkts[work_done]);\n\n\t\tret = (*q_service)(cq->vdev, cq_desc, type,\n\t\t\tq_number, completed_index, opaque);\n\t\tcq->to_clean++;\n\t\tif (cq->to_clean == cq->ring.desc_count) {\n\t\t\tcq->to_clean = 0;\n\t\t\tcq->last_color = cq->last_color ? 0 : 1;\n\t\t}\n\n\t\tcq_desc = (struct cq_desc *)((u8 *)cq->ring.descs +\n\t\t\tcq->ring.desc_size * cq->to_clean);\n\t\tcq_desc_dec(cq_desc, &type, &color,\n\t\t\t&q_number, &completed_index);\n\n\t\tif (ret)\n\t\t\twork_done++;\n\t\tif (work_done >= work_to_do)\n\t\t\tbreak;\n\t}\n\n\treturn work_done;\n}\n\nvoid vnic_cq_free(struct vnic_cq *cq);\nint vnic_cq_alloc(struct vnic_dev *vdev, struct vnic_cq *cq, unsigned int index,\n\tunsigned int socket_id,\n\tunsigned int desc_count, unsigned int desc_size);\nvoid vnic_cq_init(struct vnic_cq *cq, unsigned int flow_control_enable,\n\tunsigned int color_enable, unsigned int cq_head, unsigned int cq_tail,\n\tunsigned int cq_tail_color, unsigned int interrupt_enable,\n\tunsigned int cq_entry_enable, unsigned int message_enable,\n\tunsigned int interrupt_offset, u64 message_addr);\nvoid vnic_cq_clean(struct vnic_cq *cq);\nint vnic_cq_mem_size(struct vnic_cq *cq, unsigned int desc_count,\n\tunsigned int desc_size);\n\n#endif /* _VNIC_CQ_H_ */\n" }, { "path": "drivers/net/enic/base/vnic_dev.c", "content": "/*\n * Copyright 2008-2014 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id$\"\n\n#include \n#include \n#include \n\n#include \"vnic_dev.h\"\n#include \"vnic_resource.h\"\n#include \"vnic_devcmd.h\"\n#include \"vnic_stats.h\"\n\n\nenum vnic_proxy_type {\n\tPROXY_NONE,\n\tPROXY_BY_BDF,\n\tPROXY_BY_INDEX,\n};\n\nstruct vnic_res {\n\tvoid __iomem *vaddr;\n\tdma_addr_t bus_addr;\n\tunsigned int count;\n};\n\nstruct vnic_intr_coal_timer_info {\n\tu32 mul;\n\tu32 div;\n\tu32 max_usec;\n};\n\nstruct vnic_dev {\n\tvoid *priv;\n\tstruct rte_pci_device *pdev;\n\tstruct vnic_res res[RES_TYPE_MAX];\n\tenum vnic_dev_intr_mode intr_mode;\n\tstruct vnic_devcmd __iomem *devcmd;\n\tstruct vnic_devcmd_notify *notify;\n\tstruct vnic_devcmd_notify notify_copy;\n\tdma_addr_t notify_pa;\n\tu32 notify_sz;\n\tdma_addr_t linkstatus_pa;\n\tstruct vnic_stats *stats;\n\tdma_addr_t stats_pa;\n\tstruct vnic_devcmd_fw_info *fw_info;\n\tdma_addr_t fw_info_pa;\n\tenum vnic_proxy_type proxy;\n\tu32 proxy_index;\n\tu64 args[VNIC_DEVCMD_NARGS];\n\tu16 split_hdr_size;\n\tint in_reset;\n\tstruct vnic_intr_coal_timer_info intr_coal_timer_info;\n\tvoid *(*alloc_consistent)(void *priv, size_t size,\n\t\tdma_addr_t *dma_handle, u8 *name);\n\tvoid (*free_consistent)(struct rte_pci_device *hwdev,\n\t\tsize_t size, void *vaddr,\n\t\tdma_addr_t dma_handle);\n};\n\n#define VNIC_MAX_RES_HDR_SIZE \\\n\t(sizeof(struct vnic_resource_header) + \\\n\tsizeof(struct vnic_resource) * RES_TYPE_MAX)\n#define VNIC_RES_STRIDE\t128\n\nvoid *vnic_dev_priv(struct vnic_dev *vdev)\n{\n\treturn vdev->priv;\n}\n\nvoid vnic_register_cbacks(struct vnic_dev *vdev,\n\tvoid *(*alloc_consistent)(void *priv, size_t size,\n\t dma_addr_t *dma_handle, u8 *name),\n\tvoid (*free_consistent)(struct rte_pci_device *hwdev,\n\t size_t size, void *vaddr,\n\t dma_addr_t dma_handle))\n{\n\tvdev->alloc_consistent = alloc_consistent;\n\tvdev->free_consistent = free_consistent;\n}\n\nstatic int vnic_dev_discover_res(struct vnic_dev *vdev,\n\tstruct vnic_dev_bar *bar, unsigned int num_bars)\n{\n\tstruct vnic_resource_header __iomem *rh;\n\tstruct mgmt_barmap_hdr __iomem *mrh;\n\tstruct vnic_resource __iomem *r;\n\tu8 type;\n\n\tif (num_bars == 0)\n\t\treturn -EINVAL;\n\n\tif (bar->len < VNIC_MAX_RES_HDR_SIZE) {\n\t\tpr_err(\"vNIC BAR0 res hdr length error\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\trh = bar->vaddr;\n\tmrh = bar->vaddr;\n\tif (!rh) {\n\t\tpr_err(\"vNIC BAR0 res hdr not mem-mapped\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* Check for mgmt vnic in addition to normal vnic */\n\tif ((ioread32(&rh->magic) != VNIC_RES_MAGIC) ||\n\t\t(ioread32(&rh->version) != VNIC_RES_VERSION)) {\n\t\tif ((ioread32(&mrh->magic) != MGMTVNIC_MAGIC) ||\n\t\t\t(ioread32(&mrh->version) != MGMTVNIC_VERSION)) {\n\t\t\tpr_err(\"vNIC BAR0 res magic/version error \" \\\n\t\t\t\t\"exp (%lx/%lx) or (%lx/%lx), curr (%x/%x)\\n\",\n\t\t\t\tVNIC_RES_MAGIC, VNIC_RES_VERSION,\n\t\t\t\tMGMTVNIC_MAGIC, MGMTVNIC_VERSION,\n\t\t\t\tioread32(&rh->magic), ioread32(&rh->version));\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\tif (ioread32(&mrh->magic) == MGMTVNIC_MAGIC)\n\t\tr = (struct vnic_resource __iomem *)(mrh + 1);\n\telse\n\t\tr = (struct vnic_resource __iomem *)(rh + 1);\n\n\n\twhile ((type = ioread8(&r->type)) != RES_TYPE_EOL) {\n\t\tu8 bar_num = ioread8(&r->bar);\n\t\tu32 bar_offset = ioread32(&r->bar_offset);\n\t\tu32 count = ioread32(&r->count);\n\t\tu32 len;\n\n\t\tr++;\n\n\t\tif (bar_num >= num_bars)\n\t\t\tcontinue;\n\n\t\tif (!bar[bar_num].len || !bar[bar_num].vaddr)\n\t\t\tcontinue;\n\n\t\tswitch (type) {\n\t\tcase RES_TYPE_WQ:\n\t\tcase RES_TYPE_RQ:\n\t\tcase RES_TYPE_CQ:\n\t\tcase RES_TYPE_INTR_CTRL:\n\t\t\t/* each count is stride bytes long */\n\t\t\tlen = count * VNIC_RES_STRIDE;\n\t\t\tif (len + bar_offset > bar[bar_num].len) {\n\t\t\t\tpr_err(\"vNIC BAR0 resource %d \" \\\n\t\t\t\t\t\"out-of-bounds, offset 0x%x + \" \\\n\t\t\t\t\t\"size 0x%x > bar len 0x%lx\\n\",\n\t\t\t\t\ttype, bar_offset,\n\t\t\t\t\tlen,\n\t\t\t\t\tbar[bar_num].len);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase RES_TYPE_INTR_PBA_LEGACY:\n\t\tcase RES_TYPE_DEVCMD:\n\t\t\tlen = count;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tcontinue;\n\t\t}\n\n\t\tvdev->res[type].count = count;\n\t\tvdev->res[type].vaddr = (char __iomem *)bar[bar_num].vaddr +\n\t\t bar_offset;\n\t\tvdev->res[type].bus_addr = bar[bar_num].bus_addr + bar_offset;\n\t}\n\n\treturn 0;\n}\n\nunsigned int vnic_dev_get_res_count(struct vnic_dev *vdev,\n\tenum vnic_res_type type)\n{\n\treturn vdev->res[type].count;\n}\n\nvoid __iomem *vnic_dev_get_res(struct vnic_dev *vdev, enum vnic_res_type type,\n\tunsigned int index)\n{\n\tif (!vdev->res[type].vaddr)\n\t\treturn NULL;\n\n\tswitch (type) {\n\tcase RES_TYPE_WQ:\n\tcase RES_TYPE_RQ:\n\tcase RES_TYPE_CQ:\n\tcase RES_TYPE_INTR_CTRL:\n\t\treturn (char __iomem *)vdev->res[type].vaddr +\n\t\t\tindex * VNIC_RES_STRIDE;\n\tdefault:\n\t\treturn (char __iomem *)vdev->res[type].vaddr;\n\t}\n}\n\nunsigned int vnic_dev_desc_ring_size(struct vnic_dev_ring *ring,\n\tunsigned int desc_count, unsigned int desc_size)\n{\n\t/* The base address of the desc rings must be 512 byte aligned.\n\t * Descriptor count is aligned to groups of 32 descriptors. A\n\t * count of 0 means the maximum 4096 descriptors. Descriptor\n\t * size is aligned to 16 bytes.\n\t */\n\n\tunsigned int count_align = 32;\n\tunsigned int desc_align = 16;\n\n\tring->base_align = 512;\n\n\tif (desc_count == 0)\n\t\tdesc_count = 4096;\n\n\tring->desc_count = VNIC_ALIGN(desc_count, count_align);\n\n\tring->desc_size = VNIC_ALIGN(desc_size, desc_align);\n\n\tring->size = ring->desc_count * ring->desc_size;\n\tring->size_unaligned = ring->size + ring->base_align;\n\n\treturn ring->size_unaligned;\n}\n\nvoid vnic_set_hdr_split_size(struct vnic_dev *vdev, u16 size)\n{\n\tvdev->split_hdr_size = size;\n}\n\nu16 vnic_get_hdr_split_size(struct vnic_dev *vdev)\n{\n\treturn vdev->split_hdr_size;\n}\n\nvoid vnic_dev_clear_desc_ring(struct vnic_dev_ring *ring)\n{\n\tmemset(ring->descs, 0, ring->size);\n}\n\nint vnic_dev_alloc_desc_ring(__attribute__((unused)) struct vnic_dev *vdev,\n\tstruct vnic_dev_ring *ring,\n\tunsigned int desc_count, unsigned int desc_size, unsigned int socket_id,\n\tchar *z_name)\n{\n\tconst struct rte_memzone *rz;\n\n\tvnic_dev_desc_ring_size(ring, desc_count, desc_size);\n\n\trz = rte_memzone_reserve_aligned(z_name,\n\t\tring->size_unaligned, socket_id,\n\t\t0, ENIC_ALIGN);\n\tif (!rz) {\n\t\tpr_err(\"Failed to allocate ring (size=%d), aborting\\n\",\n\t\t\t(int)ring->size);\n\t\treturn -ENOMEM;\n\t}\n\n\tring->descs_unaligned = rz->addr;\n\tif (!ring->descs_unaligned) {\n\t\tpr_err(\"Failed to map allocated ring (size=%d), aborting\\n\",\n\t\t\t(int)ring->size);\n\t\treturn -ENOMEM;\n\t}\n\n\tring->base_addr_unaligned = (dma_addr_t)rz->phys_addr;\n\n\tring->base_addr = VNIC_ALIGN(ring->base_addr_unaligned,\n\t\tring->base_align);\n\tring->descs = (u8 *)ring->descs_unaligned +\n\t (ring->base_addr - ring->base_addr_unaligned);\n\n\tvnic_dev_clear_desc_ring(ring);\n\n\tring->desc_avail = ring->desc_count - 1;\n\n\treturn 0;\n}\n\nvoid vnic_dev_free_desc_ring(__attribute__((unused)) struct vnic_dev *vdev,\n\tstruct vnic_dev_ring *ring)\n{\n\tif (ring->descs)\n\t\tring->descs = NULL;\n}\n\nstatic int _vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,\n\tint wait)\n{\n\tstruct vnic_devcmd __iomem *devcmd = vdev->devcmd;\n\tunsigned int i;\n\tint delay;\n\tu32 status;\n\tint err;\n\n\tstatus = ioread32(&devcmd->status);\n\tif (status == 0xFFFFFFFF) {\n\t\t/* PCI-e target device is gone */\n\t\treturn -ENODEV;\n\t}\n\tif (status & STAT_BUSY) {\n\n\t\tpr_err(\"Busy devcmd %d\\n\", _CMD_N(cmd));\n\t\treturn -EBUSY;\n\t}\n\n\tif (_CMD_DIR(cmd) & _CMD_DIR_WRITE) {\n\t\tfor (i = 0; i < VNIC_DEVCMD_NARGS; i++)\n\t\t\twriteq(vdev->args[i], &devcmd->args[i]);\n\t\twmb(); /* complete all writes initiated till now */\n\t}\n\n\tiowrite32(cmd, &devcmd->cmd);\n\n\tif ((_CMD_FLAGS(cmd) & _CMD_FLAGS_NOWAIT))\n\t\treturn 0;\n\n\tfor (delay = 0; delay < wait; delay++) {\n\n\t\tudelay(100);\n\n\t\tstatus = ioread32(&devcmd->status);\n\t\tif (status == 0xFFFFFFFF) {\n\t\t\t/* PCI-e target device is gone */\n\t\t\treturn -ENODEV;\n\t\t}\n\n\t\tif (!(status & STAT_BUSY)) {\n\t\t\tif (status & STAT_ERROR) {\n\t\t\t\terr = -(int)readq(&devcmd->args[0]);\n\t\t\t\tif (cmd != CMD_CAPABILITY)\n\t\t\t\t\tpr_err(\"Devcmd %d failed \" \\\n\t\t\t\t\t\t\"with error code %d\\n\",\n\t\t\t\t\t\t_CMD_N(cmd), err);\n\t\t\t\treturn err;\n\t\t\t}\n\n\t\t\tif (_CMD_DIR(cmd) & _CMD_DIR_READ) {\n\t\t\t\trmb();/* finish all reads initiated till now */\n\t\t\t\tfor (i = 0; i < VNIC_DEVCMD_NARGS; i++)\n\t\t\t\t\tvdev->args[i] = readq(&devcmd->args[i]);\n\t\t\t}\n\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\tpr_err(\"Timedout devcmd %d\\n\", _CMD_N(cmd));\n\treturn -ETIMEDOUT;\n}\n\nstatic int vnic_dev_cmd_proxy(struct vnic_dev *vdev,\n\tenum vnic_devcmd_cmd proxy_cmd, enum vnic_devcmd_cmd cmd,\n\tu64 *a0, u64 *a1, int wait)\n{\n\tu32 status;\n\tint err;\n\n\tmemset(vdev->args, 0, sizeof(vdev->args));\n\n\tvdev->args[0] = vdev->proxy_index;\n\tvdev->args[1] = cmd;\n\tvdev->args[2] = *a0;\n\tvdev->args[3] = *a1;\n\n\terr = _vnic_dev_cmd(vdev, proxy_cmd, wait);\n\tif (err)\n\t\treturn err;\n\n\tstatus = (u32)vdev->args[0];\n\tif (status & STAT_ERROR) {\n\t\terr = (int)vdev->args[1];\n\t\tif (err != ERR_ECMDUNKNOWN ||\n\t\t cmd != CMD_CAPABILITY)\n\t\t\tpr_err(\"Error %d proxy devcmd %d\\n\", err, _CMD_N(cmd));\n\t\treturn err;\n\t}\n\n\t*a0 = vdev->args[1];\n\t*a1 = vdev->args[2];\n\n\treturn 0;\n}\n\nstatic int vnic_dev_cmd_no_proxy(struct vnic_dev *vdev,\n\tenum vnic_devcmd_cmd cmd, u64 *a0, u64 *a1, int wait)\n{\n\tint err;\n\n\tvdev->args[0] = *a0;\n\tvdev->args[1] = *a1;\n\n\terr = _vnic_dev_cmd(vdev, cmd, wait);\n\n\t*a0 = vdev->args[0];\n\t*a1 = vdev->args[1];\n\n\treturn err;\n}\n\nvoid vnic_dev_cmd_proxy_by_index_start(struct vnic_dev *vdev, u16 index)\n{\n\tvdev->proxy = PROXY_BY_INDEX;\n\tvdev->proxy_index = index;\n}\n\nvoid vnic_dev_cmd_proxy_by_bdf_start(struct vnic_dev *vdev, u16 bdf)\n{\n\tvdev->proxy = PROXY_BY_BDF;\n\tvdev->proxy_index = bdf;\n}\n\nvoid vnic_dev_cmd_proxy_end(struct vnic_dev *vdev)\n{\n\tvdev->proxy = PROXY_NONE;\n\tvdev->proxy_index = 0;\n}\n\nint vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,\n\tu64 *a0, u64 *a1, int wait)\n{\n\tmemset(vdev->args, 0, sizeof(vdev->args));\n\n\tswitch (vdev->proxy) {\n\tcase PROXY_BY_INDEX:\n\t\treturn vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_INDEX, cmd,\n\t\t\t\ta0, a1, wait);\n\tcase PROXY_BY_BDF:\n\t\treturn vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_BDF, cmd,\n\t\t\t\ta0, a1, wait);\n\tcase PROXY_NONE:\n\tdefault:\n\t\treturn vnic_dev_cmd_no_proxy(vdev, cmd, a0, a1, wait);\n\t}\n}\n\nstatic int vnic_dev_capable(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd)\n{\n\tu64 a0 = (u32)cmd, a1 = 0;\n\tint wait = 1000;\n\tint err;\n\n\terr = vnic_dev_cmd(vdev, CMD_CAPABILITY, &a0, &a1, wait);\n\n\treturn !(err || a0);\n}\n\nint vnic_dev_spec(struct vnic_dev *vdev, unsigned int offset, size_t size,\n\tvoid *value)\n{\n\tu64 a0, a1;\n\tint wait = 1000;\n\tint err;\n\n\ta0 = offset;\n\ta1 = size;\n\n\terr = vnic_dev_cmd(vdev, CMD_DEV_SPEC, &a0, &a1, wait);\n\n\tswitch (size) {\n\tcase 1:\n\t\t*(u8 *)value = (u8)a0;\n\t\tbreak;\n\tcase 2:\n\t\t*(u16 *)value = (u16)a0;\n\t\tbreak;\n\tcase 4:\n\t\t*(u32 *)value = (u32)a0;\n\t\tbreak;\n\tcase 8:\n\t\t*(u64 *)value = a0;\n\t\tbreak;\n\tdefault:\n\t\tBUG();\n\t\tbreak;\n\t}\n\n\treturn err;\n}\n\nint vnic_dev_stats_clear(struct vnic_dev *vdev)\n{\n\tu64 a0 = 0, a1 = 0;\n\tint wait = 1000;\n\n\treturn vnic_dev_cmd(vdev, CMD_STATS_CLEAR, &a0, &a1, wait);\n}\n\nint vnic_dev_stats_dump(struct vnic_dev *vdev, struct vnic_stats **stats)\n{\n\tu64 a0, a1;\n\tint wait = 1000;\n\tstatic u32 instance;\n\tchar name[NAME_MAX];\n\n\tif (!vdev->stats) {\n\t\tsnprintf((char *)name, sizeof(name),\n\t\t\t\"vnic_stats-%d\", instance++);\n\t\tvdev->stats = vdev->alloc_consistent(vdev->priv,\n\t\t\tsizeof(struct vnic_stats), &vdev->stats_pa, (u8 *)name);\n\t\tif (!vdev->stats)\n\t\t\treturn -ENOMEM;\n\t}\n\n\t*stats = vdev->stats;\n\ta0 = vdev->stats_pa;\n\ta1 = sizeof(struct vnic_stats);\n\n\treturn vnic_dev_cmd(vdev, CMD_STATS_DUMP, &a0, &a1, wait);\n}\n\nint vnic_dev_close(struct vnic_dev *vdev)\n{\n\tu64 a0 = 0, a1 = 0;\n\tint wait = 1000;\n\n\treturn vnic_dev_cmd(vdev, CMD_CLOSE, &a0, &a1, wait);\n}\n\n/** Deprecated. @see vnic_dev_enable_wait */\nint vnic_dev_enable(struct vnic_dev *vdev)\n{\n\tu64 a0 = 0, a1 = 0;\n\tint wait = 1000;\n\n\treturn vnic_dev_cmd(vdev, CMD_ENABLE, &a0, &a1, wait);\n}\n\nint vnic_dev_enable_wait(struct vnic_dev *vdev)\n{\n\tu64 a0 = 0, a1 = 0;\n\tint wait = 1000;\n\n\tif (vnic_dev_capable(vdev, CMD_ENABLE_WAIT))\n\t\treturn vnic_dev_cmd(vdev, CMD_ENABLE_WAIT, &a0, &a1, wait);\n\telse\n\t\treturn vnic_dev_cmd(vdev, CMD_ENABLE, &a0, &a1, wait);\n}\n\nint vnic_dev_disable(struct vnic_dev *vdev)\n{\n\tu64 a0 = 0, a1 = 0;\n\tint wait = 1000;\n\n\treturn vnic_dev_cmd(vdev, CMD_DISABLE, &a0, &a1, wait);\n}\n\nint vnic_dev_open(struct vnic_dev *vdev, int arg)\n{\n\tu64 a0 = (u32)arg, a1 = 0;\n\tint wait = 1000;\n\n\treturn vnic_dev_cmd(vdev, CMD_OPEN, &a0, &a1, wait);\n}\n\nint vnic_dev_open_done(struct vnic_dev *vdev, int *done)\n{\n\tu64 a0 = 0, a1 = 0;\n\tint wait = 1000;\n\tint err;\n\n\t*done = 0;\n\n\terr = vnic_dev_cmd(vdev, CMD_OPEN_STATUS, &a0, &a1, wait);\n\tif (err)\n\t\treturn err;\n\n\t*done = (a0 == 0);\n\n\treturn 0;\n}\n\nint vnic_dev_soft_reset(struct vnic_dev *vdev, int arg)\n{\n\tu64 a0 = (u32)arg, a1 = 0;\n\tint wait = 1000;\n\n\treturn vnic_dev_cmd(vdev, CMD_SOFT_RESET, &a0, &a1, wait);\n}\n\nint vnic_dev_soft_reset_done(struct vnic_dev *vdev, int *done)\n{\n\tu64 a0 = 0, a1 = 0;\n\tint wait = 1000;\n\tint err;\n\n\t*done = 0;\n\n\terr = vnic_dev_cmd(vdev, CMD_SOFT_RESET_STATUS, &a0, &a1, wait);\n\tif (err)\n\t\treturn err;\n\n\t*done = (a0 == 0);\n\n\treturn 0;\n}\n\nint vnic_dev_get_mac_addr(struct vnic_dev *vdev, u8 *mac_addr)\n{\n\tu64 a0, a1 = 0;\n\tint wait = 1000;\n\tint err, i;\n\n\tfor (i = 0; i < ETH_ALEN; i++)\n\t\tmac_addr[i] = 0;\n\n\terr = vnic_dev_cmd(vdev, CMD_GET_MAC_ADDR, &a0, &a1, wait);\n\tif (err)\n\t\treturn err;\n\n\tfor (i = 0; i < ETH_ALEN; i++)\n\t\tmac_addr[i] = ((u8 *)&a0)[i];\n\n\treturn 0;\n}\n\nint vnic_dev_packet_filter(struct vnic_dev *vdev, int directed, int multicast,\n\tint broadcast, int promisc, int allmulti)\n{\n\tu64 a0, a1 = 0;\n\tint wait = 1000;\n\tint err;\n\n\ta0 = (directed ? CMD_PFILTER_DIRECTED : 0) |\n\t (multicast ? CMD_PFILTER_MULTICAST : 0) |\n\t (broadcast ? CMD_PFILTER_BROADCAST : 0) |\n\t (promisc ? CMD_PFILTER_PROMISCUOUS : 0) |\n\t (allmulti ? CMD_PFILTER_ALL_MULTICAST : 0);\n\n\terr = vnic_dev_cmd(vdev, CMD_PACKET_FILTER, &a0, &a1, wait);\n\tif (err)\n\t\tpr_err(\"Can't set packet filter\\n\");\n\n\treturn err;\n}\n\nint vnic_dev_add_addr(struct vnic_dev *vdev, u8 *addr)\n{\n\tu64 a0 = 0, a1 = 0;\n\tint wait = 1000;\n\tint err;\n\tint i;\n\n\tfor (i = 0; i < ETH_ALEN; i++)\n\t\t((u8 *)&a0)[i] = addr[i];\n\n\terr = vnic_dev_cmd(vdev, CMD_ADDR_ADD, &a0, &a1, wait);\n\tif (err)\n\t\tpr_err(\"Can't add addr [%02x:%02x:%02x:%02x:%02x:%02x], %d\\n\",\n\t\t\taddr[0], addr[1], addr[2], addr[3], addr[4], addr[5],\n\t\t\terr);\n\n\treturn err;\n}\n\nint vnic_dev_del_addr(struct vnic_dev *vdev, u8 *addr)\n{\n\tu64 a0 = 0, a1 = 0;\n\tint wait = 1000;\n\tint err;\n\tint i;\n\n\tfor (i = 0; i < ETH_ALEN; i++)\n\t\t((u8 *)&a0)[i] = addr[i];\n\n\terr = vnic_dev_cmd(vdev, CMD_ADDR_DEL, &a0, &a1, wait);\n\tif (err)\n\t\tpr_err(\"Can't del addr [%02x:%02x:%02x:%02x:%02x:%02x], %d\\n\",\n\t\t\taddr[0], addr[1], addr[2], addr[3], addr[4], addr[5],\n\t\t\terr);\n\n\treturn err;\n}\n\nint vnic_dev_set_ig_vlan_rewrite_mode(struct vnic_dev *vdev,\n\tu8 ig_vlan_rewrite_mode)\n{\n\tu64 a0 = ig_vlan_rewrite_mode, a1 = 0;\n\tint wait = 1000;\n\n\tif (vnic_dev_capable(vdev, CMD_IG_VLAN_REWRITE_MODE))\n\t\treturn vnic_dev_cmd(vdev, CMD_IG_VLAN_REWRITE_MODE,\n\t\t\t\t&a0, &a1, wait);\n\telse\n\t\treturn 0;\n}\n\nint vnic_dev_raise_intr(struct vnic_dev *vdev, u16 intr)\n{\n\tu64 a0 = intr, a1 = 0;\n\tint wait = 1000;\n\tint err;\n\n\terr = vnic_dev_cmd(vdev, CMD_IAR, &a0, &a1, wait);\n\tif (err)\n\t\tpr_err(\"Failed to raise INTR[%d], err %d\\n\", intr, err);\n\n\treturn err;\n}\n\nvoid vnic_dev_set_reset_flag(struct vnic_dev *vdev, int state)\n{\n\tvdev->in_reset = state;\n}\n\nstatic inline int vnic_dev_in_reset(struct vnic_dev *vdev)\n{\n\treturn vdev->in_reset;\n}\n\nint vnic_dev_notify_setcmd(struct vnic_dev *vdev,\n\tvoid *notify_addr, dma_addr_t notify_pa, u16 intr)\n{\n\tu64 a0, a1;\n\tint wait = 1000;\n\tint r;\n\n\tmemset(notify_addr, 0, sizeof(struct vnic_devcmd_notify));\n\tif (!vnic_dev_in_reset(vdev)) {\n\t\tvdev->notify = notify_addr;\n\t\tvdev->notify_pa = notify_pa;\n\t}\n\n\ta0 = (u64)notify_pa;\n\ta1 = ((u64)intr << 32) & 0x0000ffff00000000ULL;\n\ta1 += sizeof(struct vnic_devcmd_notify);\n\n\tr = vnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);\n\tif (!vnic_dev_in_reset(vdev))\n\t\tvdev->notify_sz = (r == 0) ? (u32)a1 : 0;\n\n\treturn r;\n}\n\nint vnic_dev_notify_set(struct vnic_dev *vdev, u16 intr)\n{\n\tvoid *notify_addr = NULL;\n\tdma_addr_t notify_pa = 0;\n\tchar name[NAME_MAX];\n\tstatic u32 instance;\n\n\tif (vdev->notify || vdev->notify_pa) {\n\t\tpr_warn(\"notify block %p still allocated.\\n\" \\\n\t\t\t\"Ignore if restarting port\\n\", vdev->notify);\n\t\treturn -EINVAL;\n\t}\n\n\tif (!vnic_dev_in_reset(vdev)) {\n\t\tsnprintf((char *)name, sizeof(name),\n\t\t\t\"vnic_notify-%d\", instance++);\n\t\tnotify_addr = vdev->alloc_consistent(vdev->priv,\n\t\t\tsizeof(struct vnic_devcmd_notify),\n\t\t\t¬ify_pa, (u8 *)name);\n\t\tif (!notify_addr)\n\t\t\treturn -ENOMEM;\n\t}\n\n\treturn vnic_dev_notify_setcmd(vdev, notify_addr, notify_pa, intr);\n}\n\nint vnic_dev_notify_unsetcmd(struct vnic_dev *vdev)\n{\n\tu64 a0, a1;\n\tint wait = 1000;\n\tint err;\n\n\ta0 = 0; /* paddr = 0 to unset notify buffer */\n\ta1 = 0x0000ffff00000000ULL; /* intr num = -1 to unreg for intr */\n\ta1 += sizeof(struct vnic_devcmd_notify);\n\n\terr = vnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);\n\tif (!vnic_dev_in_reset(vdev)) {\n\t\tvdev->notify = NULL;\n\t\tvdev->notify_pa = 0;\n\t\tvdev->notify_sz = 0;\n\t}\n\n\treturn err;\n}\n\nint vnic_dev_notify_unset(struct vnic_dev *vdev)\n{\n\tif (vdev->notify && !vnic_dev_in_reset(vdev)) {\n\t\tvdev->free_consistent(vdev->pdev,\n\t\t\tsizeof(struct vnic_devcmd_notify),\n\t\t\tvdev->notify,\n\t\t\tvdev->notify_pa);\n\t}\n\n\treturn vnic_dev_notify_unsetcmd(vdev);\n}\n\nstatic int vnic_dev_notify_ready(struct vnic_dev *vdev)\n{\n\tu32 *words;\n\tunsigned int nwords = vdev->notify_sz / 4;\n\tunsigned int i;\n\tu32 csum;\n\n\tif (!vdev->notify || !vdev->notify_sz)\n\t\treturn 0;\n\n\tdo {\n\t\tcsum = 0;\n\t\trte_memcpy(&vdev->notify_copy, vdev->notify, vdev->notify_sz);\n\t\twords = (u32 *)&vdev->notify_copy;\n\t\tfor (i = 1; i < nwords; i++)\n\t\t\tcsum += words[i];\n\t} while (csum != words[0]);\n\n\treturn 1;\n}\n\nint vnic_dev_init(struct vnic_dev *vdev, int arg)\n{\n\tu64 a0 = (u32)arg, a1 = 0;\n\tint wait = 1000;\n\tint r = 0;\n\n\tif (vnic_dev_capable(vdev, CMD_INIT))\n\t\tr = vnic_dev_cmd(vdev, CMD_INIT, &a0, &a1, wait);\n\telse {\n\t\tvnic_dev_cmd(vdev, CMD_INIT_v1, &a0, &a1, wait);\n\t\tif (a0 & CMD_INITF_DEFAULT_MAC) {\n\t\t\t/* Emulate these for old CMD_INIT_v1 which\n\t\t\t * didn't pass a0 so no CMD_INITF_*.\n\t\t\t */\n\t\t\tvnic_dev_cmd(vdev, CMD_GET_MAC_ADDR, &a0, &a1, wait);\n\t\t\tvnic_dev_cmd(vdev, CMD_ADDR_ADD, &a0, &a1, wait);\n\t\t}\n\t}\n\treturn r;\n}\n\nint vnic_dev_deinit(struct vnic_dev *vdev)\n{\n\tu64 a0 = 0, a1 = 0;\n\tint wait = 1000;\n\n\treturn vnic_dev_cmd(vdev, CMD_DEINIT, &a0, &a1, wait);\n}\n\nvoid vnic_dev_intr_coal_timer_info_default(struct vnic_dev *vdev)\n{\n\t/* Default: hardware intr coal timer is in units of 1.5 usecs */\n\tvdev->intr_coal_timer_info.mul = 2;\n\tvdev->intr_coal_timer_info.div = 3;\n\tvdev->intr_coal_timer_info.max_usec =\n\t\tvnic_dev_intr_coal_timer_hw_to_usec(vdev, 0xffff);\n}\n\nint vnic_dev_link_status(struct vnic_dev *vdev)\n{\n\tif (!vnic_dev_notify_ready(vdev))\n\t\treturn 0;\n\n\treturn vdev->notify_copy.link_state;\n}\n\nu32 vnic_dev_port_speed(struct vnic_dev *vdev)\n{\n\tif (!vnic_dev_notify_ready(vdev))\n\t\treturn 0;\n\n\treturn vdev->notify_copy.port_speed;\n}\n\nvoid vnic_dev_set_intr_mode(struct vnic_dev *vdev,\n\tenum vnic_dev_intr_mode intr_mode)\n{\n\tvdev->intr_mode = intr_mode;\n}\n\nenum vnic_dev_intr_mode vnic_dev_get_intr_mode(\n\tstruct vnic_dev *vdev)\n{\n\treturn vdev->intr_mode;\n}\n\nu32 vnic_dev_intr_coal_timer_usec_to_hw(struct vnic_dev *vdev, u32 usec)\n{\n\treturn (usec * vdev->intr_coal_timer_info.mul) /\n\t\tvdev->intr_coal_timer_info.div;\n}\n\nu32 vnic_dev_intr_coal_timer_hw_to_usec(struct vnic_dev *vdev, u32 hw_cycles)\n{\n\treturn (hw_cycles * vdev->intr_coal_timer_info.div) /\n\t\tvdev->intr_coal_timer_info.mul;\n}\n\nu32 vnic_dev_get_intr_coal_timer_max(struct vnic_dev *vdev)\n{\n\treturn vdev->intr_coal_timer_info.max_usec;\n}\n\nvoid vnic_dev_unregister(struct vnic_dev *vdev)\n{\n\tif (vdev) {\n\t\tif (vdev->notify)\n\t\t\tvdev->free_consistent(vdev->pdev,\n\t\t\t\tsizeof(struct vnic_devcmd_notify),\n\t\t\t\tvdev->notify,\n\t\t\t\tvdev->notify_pa);\n\t\tif (vdev->stats)\n\t\t\tvdev->free_consistent(vdev->pdev,\n\t\t\t\tsizeof(struct vnic_stats),\n\t\t\t\tvdev->stats, vdev->stats_pa);\n\t\tif (vdev->fw_info)\n\t\t\tvdev->free_consistent(vdev->pdev,\n\t\t\t\tsizeof(struct vnic_devcmd_fw_info),\n\t\t\t\tvdev->fw_info, vdev->fw_info_pa);\n\t\tkfree(vdev);\n\t}\n}\n\nstruct vnic_dev *vnic_dev_register(struct vnic_dev *vdev,\n\tvoid *priv, struct rte_pci_device *pdev, struct vnic_dev_bar *bar,\n\tunsigned int num_bars)\n{\n\tif (!vdev) {\n\t\tvdev = kzalloc(sizeof(struct vnic_dev), GFP_ATOMIC);\n\t\tif (!vdev)\n\t\t\treturn NULL;\n\t}\n\n\tvdev->priv = priv;\n\tvdev->pdev = pdev;\n\n\tif (vnic_dev_discover_res(vdev, bar, num_bars))\n\t\tgoto err_out;\n\n\tvdev->devcmd = vnic_dev_get_res(vdev, RES_TYPE_DEVCMD, 0);\n\tif (!vdev->devcmd)\n\t\tgoto err_out;\n\n\treturn vdev;\n\nerr_out:\n\tvnic_dev_unregister(vdev);\n\treturn NULL;\n}\n\nstruct rte_pci_device *vnic_dev_get_pdev(struct vnic_dev *vdev)\n{\n\treturn vdev->pdev;\n}\n\nint vnic_dev_set_mac_addr(struct vnic_dev *vdev, u8 *mac_addr)\n{\n\tu64 a0, a1 = 0;\n\tint wait = 1000;\n\tint i;\n\n\tfor (i = 0; i < ETH_ALEN; i++)\n\t\t((u8 *)&a0)[i] = mac_addr[i];\n\n\treturn vnic_dev_cmd(vdev, CMD_SET_MAC_ADDR, &a0, &a1, wait);\n}\n\n/*\n * vnic_dev_classifier: Add/Delete classifier entries\n * @vdev: vdev of the device\n * @cmd: CLSF_ADD for Add filter\n * CLSF_DEL for Delete filter\n * @entry: In case of ADD filter, the caller passes the RQ number in this\n * variable.\n * This function stores the filter_id returned by the\n * firmware in the same variable before return;\n *\n * In case of DEL filter, the caller passes the RQ number. Return\n * value is irrelevant.\n * @data: filter data\n */\nint vnic_dev_classifier(struct vnic_dev *vdev, u8 cmd, u16 *entry,\n\tstruct filter *data)\n{\n\tu64 a0, a1;\n\tint wait = 1000;\n\tdma_addr_t tlv_pa;\n\tint ret = -EINVAL;\n\tstruct filter_tlv *tlv, *tlv_va;\n\tstruct filter_action *action;\n\tu64 tlv_size;\n\tstatic unsigned int unique_id;\n\tchar z_name[RTE_MEMZONE_NAMESIZE];\n\n\tif (cmd == CLSF_ADD) {\n\t\ttlv_size = sizeof(struct filter) +\n\t\t sizeof(struct filter_action) +\n\t\t 2*sizeof(struct filter_tlv);\n\t\tsnprintf((char *)z_name, sizeof(z_name),\n\t\t\t\"vnic_clsf_%d\", unique_id++);\n\t\ttlv_va = vdev->alloc_consistent(vdev->priv,\n\t\t\ttlv_size, &tlv_pa, (u8 *)z_name);\n\t\tif (!tlv_va)\n\t\t\treturn -ENOMEM;\n\t\ttlv = tlv_va;\n\t\ta0 = tlv_pa;\n\t\ta1 = tlv_size;\n\t\tmemset(tlv, 0, tlv_size);\n\t\ttlv->type = CLSF_TLV_FILTER;\n\t\ttlv->length = sizeof(struct filter);\n\t\t*(struct filter *)&tlv->val = *data;\n\n\t\ttlv = (struct filter_tlv *)((char *)tlv +\n\t\t\t\t\t sizeof(struct filter_tlv) +\n\t\t\t\t\t sizeof(struct filter));\n\n\t\ttlv->type = CLSF_TLV_ACTION;\n\t\ttlv->length = sizeof(struct filter_action);\n\t\taction = (struct filter_action *)&tlv->val;\n\t\taction->type = FILTER_ACTION_RQ_STEERING;\n\t\taction->u.rq_idx = *entry;\n\n\t\tret = vnic_dev_cmd(vdev, CMD_ADD_FILTER, &a0, &a1, wait);\n\t\t*entry = (u16)a0;\n\t\tvdev->free_consistent(vdev->pdev, tlv_size, tlv_va, tlv_pa);\n\t} else if (cmd == CLSF_DEL) {\n\t\ta0 = *entry;\n\t\tret = vnic_dev_cmd(vdev, CMD_DEL_FILTER, &a0, &a1, wait);\n\t}\n\n\treturn ret;\n}\n" }, { "path": "drivers/net/enic/base/vnic_dev.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_dev.h 196958 2014-11-04 18:23:37Z xuywang $\"\n\n#ifndef _VNIC_DEV_H_\n#define _VNIC_DEV_H_\n\n#include \"enic_compat.h\"\n#include \"rte_pci.h\"\n#include \"vnic_resource.h\"\n#include \"vnic_devcmd.h\"\n\n#ifndef VNIC_PADDR_TARGET\n#define VNIC_PADDR_TARGET\t0x0000000000000000ULL\n#endif\n\n#ifndef readq\nstatic inline u64 readq(void __iomem *reg)\n{\n\treturn ((u64)readl((char *)reg + 0x4UL) << 32) |\n\t\t(u64)readl(reg);\n}\n\nstatic inline void writeq(u64 val, void __iomem *reg)\n{\n\twritel(val & 0xffffffff, reg);\n\twritel((u32)(val >> 32), (char *)reg + 0x4UL);\n}\n#endif\n\n#undef pr_fmt\n#define pr_fmt(fmt) KBUILD_MODNAME \": \" fmt\n\nenum vnic_dev_intr_mode {\n\tVNIC_DEV_INTR_MODE_UNKNOWN,\n\tVNIC_DEV_INTR_MODE_INTX,\n\tVNIC_DEV_INTR_MODE_MSI,\n\tVNIC_DEV_INTR_MODE_MSIX,\n};\n\nstruct vnic_dev_bar {\n\tvoid __iomem *vaddr;\n\tdma_addr_t bus_addr;\n\tunsigned long len;\n};\n\nstruct vnic_dev_ring {\n\tvoid *descs;\n\tsize_t size;\n\tdma_addr_t base_addr;\n\tsize_t base_align;\n\tvoid *descs_unaligned;\n\tsize_t size_unaligned;\n\tdma_addr_t base_addr_unaligned;\n\tunsigned int desc_size;\n\tunsigned int desc_count;\n\tunsigned int desc_avail;\n};\n\nstruct vnic_dev_iomap_info {\n\tdma_addr_t bus_addr;\n\tunsigned long len;\n\tvoid __iomem *vaddr;\n};\n\nstruct vnic_dev;\nstruct vnic_stats;\n\nvoid *vnic_dev_priv(struct vnic_dev *vdev);\nunsigned int vnic_dev_get_res_count(struct vnic_dev *vdev,\n\tenum vnic_res_type type);\nvoid vnic_register_cbacks(struct vnic_dev *vdev,\n\tvoid *(*alloc_consistent)(void *priv, size_t size,\n\t\tdma_addr_t *dma_handle, u8 *name),\n\tvoid (*free_consistent)(struct rte_pci_device *hwdev,\n\t\tsize_t size, void *vaddr,\n\t\tdma_addr_t dma_handle));\nvoid __iomem *vnic_dev_get_res(struct vnic_dev *vdev, enum vnic_res_type type,\n\tunsigned int index);\ndma_addr_t vnic_dev_get_res_bus_addr(struct vnic_dev *vdev,\n\tenum vnic_res_type type, unsigned int index);\nuint8_t vnic_dev_get_res_bar(struct vnic_dev *vdev,\n\tenum vnic_res_type type);\nuint32_t vnic_dev_get_res_offset(struct vnic_dev *vdev,\n\tenum vnic_res_type type, unsigned int index);\nunsigned long vnic_dev_get_res_type_len(struct vnic_dev *vdev,\n\t\t\t\t\tenum vnic_res_type type);\nunsigned int vnic_dev_desc_ring_size(struct vnic_dev_ring *ring,\n\tunsigned int desc_count, unsigned int desc_size);\nvoid vnic_dev_clear_desc_ring(struct vnic_dev_ring *ring);\nvoid vnic_set_hdr_split_size(struct vnic_dev *vdev, u16 size);\nu16 vnic_get_hdr_split_size(struct vnic_dev *vdev);\nint vnic_dev_alloc_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring,\n\tunsigned int desc_count, unsigned int desc_size, unsigned int socket_id,\n\tchar *z_name);\nvoid vnic_dev_free_desc_ring(struct vnic_dev *vdev,\n\tstruct vnic_dev_ring *ring);\nint vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,\n\tu64 *a0, u64 *a1, int wait);\nint vnic_dev_cmd_args(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,\n\tu64 *args, int nargs, int wait);\nvoid vnic_dev_cmd_proxy_by_index_start(struct vnic_dev *vdev, u16 index);\nvoid vnic_dev_cmd_proxy_by_bdf_start(struct vnic_dev *vdev, u16 bdf);\nvoid vnic_dev_cmd_proxy_end(struct vnic_dev *vdev);\nint vnic_dev_fw_info(struct vnic_dev *vdev,\n\tstruct vnic_devcmd_fw_info **fw_info);\nint vnic_dev_asic_info(struct vnic_dev *vdev, u16 *asic_type, u16 *asic_rev);\nint vnic_dev_spec(struct vnic_dev *vdev, unsigned int offset, size_t size,\n\tvoid *value);\nint vnic_dev_stats_clear(struct vnic_dev *vdev);\nint vnic_dev_stats_dump(struct vnic_dev *vdev, struct vnic_stats **stats);\nint vnic_dev_hang_notify(struct vnic_dev *vdev);\nint vnic_dev_packet_filter(struct vnic_dev *vdev, int directed, int multicast,\n\tint broadcast, int promisc, int allmulti);\nint vnic_dev_packet_filter_all(struct vnic_dev *vdev, int directed,\n\tint multicast, int broadcast, int promisc, int allmulti);\nint vnic_dev_add_addr(struct vnic_dev *vdev, u8 *addr);\nint vnic_dev_del_addr(struct vnic_dev *vdev, u8 *addr);\nint vnic_dev_get_mac_addr(struct vnic_dev *vdev, u8 *mac_addr);\nint vnic_dev_raise_intr(struct vnic_dev *vdev, u16 intr);\nint vnic_dev_notify_set(struct vnic_dev *vdev, u16 intr);\nvoid vnic_dev_set_reset_flag(struct vnic_dev *vdev, int state);\nint vnic_dev_notify_unset(struct vnic_dev *vdev);\nint vnic_dev_notify_setcmd(struct vnic_dev *vdev,\n\tvoid *notify_addr, dma_addr_t notify_pa, u16 intr);\nint vnic_dev_notify_unsetcmd(struct vnic_dev *vdev);\nint vnic_dev_link_status(struct vnic_dev *vdev);\nu32 vnic_dev_port_speed(struct vnic_dev *vdev);\nu32 vnic_dev_msg_lvl(struct vnic_dev *vdev);\nu32 vnic_dev_mtu(struct vnic_dev *vdev);\nu32 vnic_dev_link_down_cnt(struct vnic_dev *vdev);\nu32 vnic_dev_notify_status(struct vnic_dev *vdev);\nu32 vnic_dev_uif(struct vnic_dev *vdev);\nint vnic_dev_close(struct vnic_dev *vdev);\nint vnic_dev_enable(struct vnic_dev *vdev);\nint vnic_dev_enable_wait(struct vnic_dev *vdev);\nint vnic_dev_disable(struct vnic_dev *vdev);\nint vnic_dev_open(struct vnic_dev *vdev, int arg);\nint vnic_dev_open_done(struct vnic_dev *vdev, int *done);\nint vnic_dev_init(struct vnic_dev *vdev, int arg);\nint vnic_dev_init_done(struct vnic_dev *vdev, int *done, int *err);\nint vnic_dev_init_prov(struct vnic_dev *vdev, u8 *buf, u32 len);\nint vnic_dev_deinit(struct vnic_dev *vdev);\nvoid vnic_dev_intr_coal_timer_info_default(struct vnic_dev *vdev);\nint vnic_dev_intr_coal_timer_info(struct vnic_dev *vdev);\nint vnic_dev_soft_reset(struct vnic_dev *vdev, int arg);\nint vnic_dev_soft_reset_done(struct vnic_dev *vdev, int *done);\nint vnic_dev_hang_reset(struct vnic_dev *vdev, int arg);\nint vnic_dev_hang_reset_done(struct vnic_dev *vdev, int *done);\nvoid vnic_dev_set_intr_mode(struct vnic_dev *vdev,\n\tenum vnic_dev_intr_mode intr_mode);\nenum vnic_dev_intr_mode vnic_dev_get_intr_mode(struct vnic_dev *vdev);\nu32 vnic_dev_intr_coal_timer_usec_to_hw(struct vnic_dev *vdev, u32 usec);\nu32 vnic_dev_intr_coal_timer_hw_to_usec(struct vnic_dev *vdev, u32 hw_cycles);\nu32 vnic_dev_get_intr_coal_timer_max(struct vnic_dev *vdev);\nvoid vnic_dev_unregister(struct vnic_dev *vdev);\nint vnic_dev_set_ig_vlan_rewrite_mode(struct vnic_dev *vdev,\n\tu8 ig_vlan_rewrite_mode);\nstruct vnic_dev *vnic_dev_register(struct vnic_dev *vdev,\n\tvoid *priv, struct rte_pci_device *pdev, struct vnic_dev_bar *bar,\n\tunsigned int num_bars);\nstruct rte_pci_device *vnic_dev_get_pdev(struct vnic_dev *vdev);\nint vnic_dev_cmd_init(struct vnic_dev *vdev, int fallback);\nint vnic_dev_get_size(void);\nint vnic_dev_int13(struct vnic_dev *vdev, u64 arg, u32 op);\nint vnic_dev_perbi(struct vnic_dev *vdev, u64 arg, u32 op);\nu32 vnic_dev_perbi_rebuild_cnt(struct vnic_dev *vdev);\nint vnic_dev_init_prov2(struct vnic_dev *vdev, u8 *buf, u32 len);\nint vnic_dev_enable2(struct vnic_dev *vdev, int active);\nint vnic_dev_enable2_done(struct vnic_dev *vdev, int *status);\nint vnic_dev_deinit_done(struct vnic_dev *vdev, int *status);\nint vnic_dev_set_mac_addr(struct vnic_dev *vdev, u8 *mac_addr);\nint vnic_dev_classifier(struct vnic_dev *vdev, u8 cmd, u16 *entry,\n\tstruct filter *data);\n#ifdef ENIC_VXLAN\nint vnic_dev_overlay_offload_enable_disable(struct vnic_dev *vdev,\n\tu8 overlay, u8 config);\nint vnic_dev_overlay_offload_cfg(struct vnic_dev *vdev, u8 overlay,\n\tu16 vxlan_udp_port_number);\n#endif\n#endif /* _VNIC_DEV_H_ */\n" }, { "path": "drivers/net/enic/base/vnic_devcmd.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_devcmd.h 173135 2014-05-16 03:14:07Z sanpilla $\"\n\n#ifndef _VNIC_DEVCMD_H_\n#define _VNIC_DEVCMD_H_\n\n#define _CMD_NBITS 14\n#define _CMD_VTYPEBITS\t10\n#define _CMD_FLAGSBITS 6\n#define _CMD_DIRBITS\t2\n\n#define _CMD_NMASK ((1 << _CMD_NBITS)-1)\n#define _CMD_VTYPEMASK ((1 << _CMD_VTYPEBITS)-1)\n#define _CMD_FLAGSMASK ((1 << _CMD_FLAGSBITS)-1)\n#define _CMD_DIRMASK ((1 << _CMD_DIRBITS)-1)\n\n#define _CMD_NSHIFT 0\n#define _CMD_VTYPESHIFT (_CMD_NSHIFT+_CMD_NBITS)\n#define _CMD_FLAGSSHIFT (_CMD_VTYPESHIFT+_CMD_VTYPEBITS)\n#define _CMD_DIRSHIFT (_CMD_FLAGSSHIFT+_CMD_FLAGSBITS)\n\n/*\n * Direction bits (from host perspective).\n */\n#define _CMD_DIR_NONE 0U\n#define _CMD_DIR_WRITE 1U\n#define _CMD_DIR_READ 2U\n#define _CMD_DIR_RW (_CMD_DIR_WRITE | _CMD_DIR_READ)\n\n/*\n * Flag bits.\n */\n#define _CMD_FLAGS_NONE 0U\n#define _CMD_FLAGS_NOWAIT 1U\n\n/*\n * vNIC type bits.\n */\n#define _CMD_VTYPE_NONE 0U\n#define _CMD_VTYPE_ENET 1U\n#define _CMD_VTYPE_FC 2U\n#define _CMD_VTYPE_SCSI 4U\n#define _CMD_VTYPE_ALL (_CMD_VTYPE_ENET | _CMD_VTYPE_FC | _CMD_VTYPE_SCSI)\n\n/*\n * Used to create cmds..\n */\n#define _CMDCF(dir, flags, vtype, nr) \\\n\t(((dir) << _CMD_DIRSHIFT) | \\\n\t((flags) << _CMD_FLAGSSHIFT) | \\\n\t((vtype) << _CMD_VTYPESHIFT) | \\\n\t((nr) << _CMD_NSHIFT))\n#define _CMDC(dir, vtype, nr) _CMDCF(dir, 0, vtype, nr)\n#define _CMDCNW(dir, vtype, nr) _CMDCF(dir, _CMD_FLAGS_NOWAIT, vtype, nr)\n\n/*\n * Used to decode cmds..\n */\n#define _CMD_DIR(cmd) (((cmd) >> _CMD_DIRSHIFT) & _CMD_DIRMASK)\n#define _CMD_FLAGS(cmd) (((cmd) >> _CMD_FLAGSSHIFT) & _CMD_FLAGSMASK)\n#define _CMD_VTYPE(cmd) (((cmd) >> _CMD_VTYPESHIFT) & _CMD_VTYPEMASK)\n#define _CMD_N(cmd) (((cmd) >> _CMD_NSHIFT) & _CMD_NMASK)\n\nenum vnic_devcmd_cmd {\n\tCMD_NONE = _CMDC(_CMD_DIR_NONE, _CMD_VTYPE_NONE, 0),\n\n\t/*\n\t * mcpu fw info in mem:\n\t * in:\n\t * (u64)a0=paddr to struct vnic_devcmd_fw_info\n\t * action:\n\t * Fills in struct vnic_devcmd_fw_info (128 bytes)\n\t * note:\n\t * An old definition of CMD_MCPU_FW_INFO\n\t */\n\tCMD_MCPU_FW_INFO_OLD = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 1),\n\n\t/*\n\t * mcpu fw info in mem:\n\t * in:\n\t * (u64)a0=paddr to struct vnic_devcmd_fw_info\n\t * (u16)a1=size of the structure\n\t * out:\n\t *\t (u16)a1=0 for in:a1 = 0,\n\t *\t data size actually written for other values.\n\t * action:\n\t * Fills in first 128 bytes of vnic_devcmd_fw_info for in:a1 = 0,\n\t * first in:a1 bytes for 0 < in:a1 <= 132,\n\t * 132 bytes for other values of in:a1.\n\t * note:\n\t * CMD_MCPU_FW_INFO and CMD_MCPU_FW_INFO_OLD have the same enum 1\n\t * for source compatibility.\n\t */\n\tCMD_MCPU_FW_INFO = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 1),\n\n\t/* dev-specific block member:\n\t * in: (u16)a0=offset,(u8)a1=size\n\t * out: a0=value */\n\tCMD_DEV_SPEC = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 2),\n\n\t/* stats clear */\n\tCMD_STATS_CLEAR = _CMDCNW(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 3),\n\n\t/* stats dump in mem: (u64)a0=paddr to stats area,\n\t * (u16)a1=sizeof stats area */\n\tCMD_STATS_DUMP = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 4),\n\n\t/* set Rx packet filter: (u32)a0=filters (see CMD_PFILTER_*) */\n\tCMD_PACKET_FILTER\t= _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 7),\n\n\t/* set Rx packet filter for all: (u32)a0=filters (see CMD_PFILTER_*) */\n\tCMD_PACKET_FILTER_ALL = _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 7),\n\n\t/* hang detection notification */\n\tCMD_HANG_NOTIFY = _CMDC(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 8),\n\n\t/* MAC address in (u48)a0 */\n\tCMD_GET_MAC_ADDR\t= _CMDC(_CMD_DIR_READ,\n\t\t\t\t\t_CMD_VTYPE_ENET | _CMD_VTYPE_FC, 9),\n\n\t/* add addr from (u48)a0 */\n\tCMD_ADDR_ADD = _CMDCNW(_CMD_DIR_WRITE,\n\t\t\t\t\t_CMD_VTYPE_ENET | _CMD_VTYPE_FC, 12),\n\n\t/* del addr from (u48)a0 */\n\tCMD_ADDR_DEL = _CMDCNW(_CMD_DIR_WRITE,\n\t\t\t\t\t_CMD_VTYPE_ENET | _CMD_VTYPE_FC, 13),\n\n\t/* add VLAN id in (u16)a0 */\n\tCMD_VLAN_ADD = _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 14),\n\n\t/* del VLAN id in (u16)a0 */\n\tCMD_VLAN_DEL = _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 15),\n\n\t/* nic_cfg in (u32)a0 */\n\tCMD_NIC_CFG = _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 16),\n\n\t/* union vnic_rss_key in mem: (u64)a0=paddr, (u16)a1=len */\n\tCMD_RSS_KEY = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 17),\n\n\t/* union vnic_rss_cpu in mem: (u64)a0=paddr, (u16)a1=len */\n\tCMD_RSS_CPU = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 18),\n\n\t/* initiate softreset */\n\tCMD_SOFT_RESET = _CMDCNW(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 19),\n\n\t/* softreset status:\n\t * out: a0=0 reset complete, a0=1 reset in progress */\n\tCMD_SOFT_RESET_STATUS = _CMDC(_CMD_DIR_READ, _CMD_VTYPE_ALL, 20),\n\n\t/* set struct vnic_devcmd_notify buffer in mem:\n\t * in:\n\t * (u64)a0=paddr to notify (set paddr=0 to unset)\n\t * (u32)a1 & 0x00000000ffffffff=sizeof(struct vnic_devcmd_notify)\n\t * (u16)a1 & 0x0000ffff00000000=intr num (-1 for no intr)\n\t * out:\n\t * (u32)a1 = effective size\n\t */\n\tCMD_NOTIFY = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 21),\n\n\t/* UNDI API: (u64)a0=paddr to s_PXENV_UNDI_ struct,\n\t * (u8)a1=PXENV_UNDI_xxx */\n\tCMD_UNDI = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 22),\n\n\t/* initiate open sequence (u32)a0=flags (see CMD_OPENF_*) */\n\tCMD_OPEN\t\t= _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 23),\n\n\t/* open status:\n\t * out: a0=0 open complete, a0=1 open in progress */\n\tCMD_OPEN_STATUS\t\t= _CMDC(_CMD_DIR_READ, _CMD_VTYPE_ALL, 24),\n\n\t/* close vnic */\n\tCMD_CLOSE\t\t= _CMDC(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 25),\n\n\t/* initialize virtual link: (u32)a0=flags (see CMD_INITF_*) */\n/***** Replaced by CMD_INIT *****/\n\tCMD_INIT_v1\t\t= _CMDCNW(_CMD_DIR_READ, _CMD_VTYPE_ALL, 26),\n\n\t/* variant of CMD_INIT, with provisioning info\n\t * (u64)a0=paddr of vnic_devcmd_provinfo\n\t * (u32)a1=sizeof provision info */\n\tCMD_INIT_PROV_INFO\t= _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 27),\n\n\t/* enable virtual link */\n\tCMD_ENABLE\t\t= _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 28),\n\n\t/* enable virtual link, waiting variant. */\n\tCMD_ENABLE_WAIT\t\t= _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 28),\n\n\t/* disable virtual link */\n\tCMD_DISABLE\t\t= _CMDC(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 29),\n\n\t/* stats dump sum of all vnic stats on same uplink in mem:\n\t * (u64)a0=paddr\n\t * (u16)a1=sizeof stats area */\n\tCMD_STATS_DUMP_ALL\t= _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 30),\n\n\t/* init status:\n\t * out: a0=0 init complete, a0=1 init in progress\n\t * if a0=0, a1=errno */\n\tCMD_INIT_STATUS\t\t= _CMDC(_CMD_DIR_READ, _CMD_VTYPE_ALL, 31),\n\n\t/* INT13 API: (u64)a0=paddr to vnic_int13_params struct\n\t * (u32)a1=INT13_CMD_xxx */\n\tCMD_INT13 = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_FC, 32),\n\n\t/* logical uplink enable/disable: (u64)a0: 0/1=disable/enable */\n\tCMD_LOGICAL_UPLINK = _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 33),\n\n\t/* undo initialize of virtual link */\n\tCMD_DEINIT\t\t= _CMDCNW(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 34),\n\n\t/* initialize virtual link: (u32)a0=flags (see CMD_INITF_*) */\n\tCMD_INIT\t\t= _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 35),\n\n\t/* check fw capability of a cmd:\n\t * in: (u32)a0=cmd\n\t * out: (u32)a0=errno, 0:valid cmd, a1=supported VNIC_STF_* bits */\n\tCMD_CAPABILITY\t\t= _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 36),\n\n\t/* persistent binding info\n\t * in: (u64)a0=paddr of arg\n\t * (u32)a1=CMD_PERBI_XXX */\n\tCMD_PERBI\t\t= _CMDC(_CMD_DIR_RW, _CMD_VTYPE_FC, 37),\n\n\t/* Interrupt Assert Register functionality\n\t * in: (u16)a0=interrupt number to assert\n\t */\n\tCMD_IAR\t\t\t= _CMDCNW(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 38),\n\n\t/* initiate hangreset, like softreset after hang detected */\n\tCMD_HANG_RESET\t\t= _CMDC(_CMD_DIR_NONE, _CMD_VTYPE_ALL, 39),\n\n\t/* hangreset status:\n\t * out: a0=0 reset complete, a0=1 reset in progress */\n\tCMD_HANG_RESET_STATUS = _CMDC(_CMD_DIR_READ, _CMD_VTYPE_ALL, 40),\n\n\t/*\n\t * Set hw ingress packet vlan rewrite mode:\n\t * in: (u32)a0=new vlan rewrite mode\n\t * out: (u32)a0=old vlan rewrite mode */\n\tCMD_IG_VLAN_REWRITE_MODE = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ENET, 41),\n\n\t/*\n\t * in: (u16)a0=bdf of target vnic\n\t * (u32)a1=cmd to proxy\n\t * a2-a15=args to cmd in a1\n\t * out: (u32)a0=status of proxied cmd\n\t * a1-a15=out args of proxied cmd */\n\tCMD_PROXY_BY_BDF =\t_CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 42),\n\n\t/*\n\t * As for BY_BDF except a0 is index of hvnlink subordinate vnic\n\t * or SR-IOV virtual vnic\n\t */\n\tCMD_PROXY_BY_INDEX = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 43),\n\n\t/*\n\t * For HPP toggle:\n\t * adapter-info-get\n\t * in: (u64)a0=phsical address of buffer passed in from caller.\n\t * (u16)a1=size of buffer specified in a0.\n\t * out: (u64)a0=phsical address of buffer passed in from caller.\n\t * (u16)a1=actual bytes from VIF-CONFIG-INFO TLV, or\n\t * 0 if no VIF-CONFIG-INFO TLV was ever received. */\n\tCMD_CONFIG_INFO_GET = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 44),\n\n\t/*\n\t * INT13 API: (u64)a0=paddr to vnic_int13_params struct\n\t * (u32)a1=INT13_CMD_xxx\n\t */\n\tCMD_INT13_ALL = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 45),\n\n\t/*\n\t * Set default vlan:\n\t * in: (u16)a0=new default vlan\n\t * (u16)a1=zero for overriding vlan with param a0,\n\t *\t\t non-zero for resetting vlan to the default\n\t * out: (u16)a0=old default vlan\n\t */\n\tCMD_SET_DEFAULT_VLAN = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 46),\n\n\t/* init_prov_info2:\n\t * Variant of CMD_INIT_PROV_INFO, where it will not try to enable\n\t * the vnic until CMD_ENABLE2 is issued.\n\t * (u64)a0=paddr of vnic_devcmd_provinfo\n\t * (u32)a1=sizeof provision info */\n\tCMD_INIT_PROV_INFO2 = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 47),\n\n\t/* enable2:\n\t * (u32)a0=0 ==> standby\n\t * =CMD_ENABLE2_ACTIVE ==> active\n\t */\n\tCMD_ENABLE2 = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 48),\n\n\t/*\n\t * cmd_status:\n\t * Returns the status of the specified command\n\t * Input:\n\t * a0 = command for which status is being queried.\n\t * Possible values are:\n\t * CMD_SOFT_RESET\n\t * CMD_HANG_RESET\n\t * CMD_OPEN\n\t * CMD_INIT\n\t * CMD_INIT_PROV_INFO\n\t * CMD_DEINIT\n\t * CMD_INIT_PROV_INFO2\n\t * CMD_ENABLE2\n\t * Output:\n\t * if status == STAT_ERROR\n\t * a0 = ERR_ENOTSUPPORTED - status for command in a0 is\n\t * not supported\n\t * if status == STAT_NONE\n\t * a0 = status of the devcmd specified in a0 as follows.\n\t * ERR_SUCCESS - command in a0 completed successfully\n\t * ERR_EINPROGRESS - command in a0 is still in progress\n\t */\n\tCMD_STATUS = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 49),\n\n\t/*\n\t * Returns interrupt coalescing timer conversion factors.\n\t * After calling this devcmd, ENIC driver can convert\n\t * interrupt coalescing timer in usec into CPU cycles as follows:\n\t *\n\t * intr_timer_cycles = intr_timer_usec * multiplier / divisor\n\t *\n\t * Interrupt coalescing timer in usecs can be be converted/obtained\n\t * from CPU cycles as follows:\n\t *\n\t * intr_timer_usec = intr_timer_cycles * divisor / multiplier\n\t *\n\t * in: none\n\t * out: (u32)a0 = multiplier\n\t * (u32)a1 = divisor\n\t * (u32)a2 = maximum timer value in usec\n\t */\n\tCMD_INTR_COAL_CONVERT = _CMDC(_CMD_DIR_READ, _CMD_VTYPE_ALL, 50),\n\n\t/*\n\t * ISCSI DUMP API:\n\t * in: (u64)a0=paddr of the param or param itself\n\t * (u32)a1=ISCSI_CMD_xxx\n\t */\n\tCMD_ISCSI_DUMP_REQ = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 51),\n\n\t/*\n\t * ISCSI DUMP STATUS API:\n\t * in: (u32)a0=cmd tag\n\t * in: (u32)a1=ISCSI_CMD_xxx\n\t * out: (u32)a0=cmd status\n\t */\n\tCMD_ISCSI_DUMP_STATUS = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 52),\n\n\t/*\n\t * Subvnic migration from MQ <--> VF.\n\t * Enable the LIF migration from MQ to VF and vice versa. MQ and VF\n\t * indexes are statically bound at the time of initialization.\n\t * Based on the\n\t * direction of migration, the resources of either MQ or the VF shall\n\t * be attached to the LIF.\n\t * in: (u32)a0=Direction of Migration\n\t *\t\t\t\t\t0=> Migrate to VF\n\t *\t\t\t\t\t1=> Migrate to MQ\n\t * (u32)a1=VF index (MQ index)\n\t */\n\tCMD_MIGRATE_SUBVNIC = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 53),\n\n\n\t/*\n\t * Register / Deregister the notification block for MQ subvnics\n\t * in:\n\t * (u64)a0=paddr to notify (set paddr=0 to unset)\n\t * (u32)a1 & 0x00000000ffffffff=sizeof(struct vnic_devcmd_notify)\n\t * (u16)a1 & 0x0000ffff00000000=intr num (-1 for no intr)\n\t * out:\n\t * (u32)a1 = effective size\n\t */\n\tCMD_SUBVNIC_NOTIFY = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ALL, 54),\n\n\t/*\n\t * Set the predefined mac address as default\n\t * in:\n\t * (u48)a0=mac addr\n\t */\n\tCMD_SET_MAC_ADDR = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 55),\n\n\t/* Update the provisioning info of the given VIF\n\t * (u64)a0=paddr of vnic_devcmd_provinfo\n\t * (u32)a1=sizeof provision info */\n\tCMD_PROV_INFO_UPDATE = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 56),\n\n\t/*\n\t * Initialization for the devcmd2 interface.\n\t * in: (u64) a0=host result buffer physical address\n\t * in: (u16) a1=number of entries in result buffer\n\t */\n\tCMD_INITIALIZE_DEVCMD2 = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ALL, 57),\n\n\t/*\n\t * Add a filter.\n\t * in: (u64) a0= filter address\n\t * (u32) a1= size of filter\n\t * out: (u32) a0=filter identifier\n\t */\n\tCMD_ADD_FILTER = _CMDC(_CMD_DIR_RW, _CMD_VTYPE_ENET, 58),\n\n\t/*\n\t * Delete a filter.\n\t * in: (u32) a0=filter identifier\n\t */\n\tCMD_DEL_FILTER = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 59),\n\n\t/*\n\t * Enable a Queue Pair in User space NIC\n\t * in: (u32) a0=Queue Pair number\n\t * (u32) a1= command\n\t */\n\tCMD_QP_ENABLE = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 60),\n\n\t/*\n\t * Disable a Queue Pair in User space NIC\n\t * in: (u32) a0=Queue Pair number\n\t * (u32) a1= command\n\t */\n\tCMD_QP_DISABLE = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 61),\n\n\t/*\n\t * Stats dump Queue Pair in User space NIC\n\t * in: (u32) a0=Queue Pair number\n\t * (u64) a1=host buffer addr for status dump\n\t * (u32) a2=length of the buffer\n\t */\n\tCMD_QP_STATS_DUMP = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 62),\n\n\t/*\n\t * Clear stats for Queue Pair in User space NIC\n\t * in: (u32) a0=Queue Pair number\n\t */\n\tCMD_QP_STATS_CLEAR = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 63),\n\n\t/*\n\t * Enable/Disable overlay offloads on the given vnic\n\t * in: (u8) a0 = OVERLAY_FEATURE_NVGRE : NVGRE\n\t * a0 = OVERLAY_FEATURE_VXLAN : VxLAN\n\t * in: (u8) a1 = OVERLAY_OFFLOAD_ENABLE : Enable\n\t * a1 = OVERLAY_OFFLOAD_DISABLE : Disable\n\t */\n\tCMD_OVERLAY_OFFLOAD_ENABLE_DISABLE =\n\t\t_CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 72),\n\n\t/*\n\t * Configuration of overlay offloads feature on a given vNIC\n\t * in: (u8) a0 = DEVCMD_OVERLAY_NVGRE : NVGRE\n\t * a0 = DEVCMD_OVERLAY_VXLAN : VxLAN\n\t * in: (u8) a1 = VXLAN_PORT_UPDATE : VxLAN\n\t * in: (u16) a2 = unsigned short int port information\n\t */\n\tCMD_OVERLAY_OFFLOAD_CFG = _CMDC(_CMD_DIR_WRITE, _CMD_VTYPE_ENET, 73),\n};\n\n/* CMD_ENABLE2 flags */\n#define CMD_ENABLE2_STANDBY 0x0\n#define CMD_ENABLE2_ACTIVE 0x1\n\n/* flags for CMD_OPEN */\n#define CMD_OPENF_OPROM\t\t0x1\t/* open coming from option rom */\n\n/* flags for CMD_INIT */\n#define CMD_INITF_DEFAULT_MAC\t0x1\t/* init with default mac addr */\n\n/* flags for CMD_PACKET_FILTER */\n#define CMD_PFILTER_DIRECTED\t\t0x01\n#define CMD_PFILTER_MULTICAST\t\t0x02\n#define CMD_PFILTER_BROADCAST\t\t0x04\n#define CMD_PFILTER_PROMISCUOUS\t\t0x08\n#define CMD_PFILTER_ALL_MULTICAST\t0x10\n\n/* Commands for CMD_QP_ENABLE/CM_QP_DISABLE */\n#define CMD_QP_RQWQ 0x0\n\n/* rewrite modes for CMD_IG_VLAN_REWRITE_MODE */\n#define IG_VLAN_REWRITE_MODE_DEFAULT_TRUNK 0\n#define IG_VLAN_REWRITE_MODE_UNTAG_DEFAULT_VLAN 1\n#define IG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN 2\n#define IG_VLAN_REWRITE_MODE_PASS_THRU 3\n\nenum vnic_devcmd_status {\n\tSTAT_NONE = 0,\n\tSTAT_BUSY = 1 << 0,\t/* cmd in progress */\n\tSTAT_ERROR = 1 << 1,\t/* last cmd caused error (code in a0) */\n};\n\nenum vnic_devcmd_error {\n\tERR_SUCCESS = 0,\n\tERR_EINVAL = 1,\n\tERR_EFAULT = 2,\n\tERR_EPERM = 3,\n\tERR_EBUSY = 4,\n\tERR_ECMDUNKNOWN = 5,\n\tERR_EBADSTATE = 6,\n\tERR_ENOMEM = 7,\n\tERR_ETIMEDOUT = 8,\n\tERR_ELINKDOWN = 9,\n\tERR_EMAXRES = 10,\n\tERR_ENOTSUPPORTED = 11,\n\tERR_EINPROGRESS = 12,\n\tERR_MAX\n};\n\n/*\n * note: hw_version and asic_rev refer to the same thing,\n * but have different formats. hw_version is\n * a 32-byte string (e.g. \"A2\") and asic_rev is\n * a 16-bit integer (e.g. 0xA2).\n */\nstruct vnic_devcmd_fw_info {\n\tchar fw_version[32];\n\tchar fw_build[32];\n\tchar hw_version[32];\n\tchar hw_serial_number[32];\n\tu16 asic_type;\n\tu16 asic_rev;\n};\n\nenum fwinfo_asic_type {\n\tFWINFO_ASIC_TYPE_UNKNOWN,\n\tFWINFO_ASIC_TYPE_PALO,\n\tFWINFO_ASIC_TYPE_SERENO,\n};\n\n\nstruct vnic_devcmd_notify {\n\tu32 csum;\t\t/* checksum over following words */\n\n\tu32 link_state;\t\t/* link up == 1 */\n\tu32 port_speed;\t\t/* effective port speed (rate limit) */\n\tu32 mtu;\t\t/* MTU */\n\tu32 msglvl;\t\t/* requested driver msg lvl */\n\tu32 uif;\t\t/* uplink interface */\n\tu32 status;\t\t/* status bits (see VNIC_STF_*) */\n\tu32 error;\t\t/* error code (see ERR_*) for first ERR */\n\tu32 link_down_cnt;\t/* running count of link down transitions */\n\tu32 perbi_rebuild_cnt;\t/* running count of perbi rebuilds */\n};\n#define VNIC_STF_FATAL_ERR\t0x0001\t/* fatal fw error */\n#define VNIC_STF_STD_PAUSE\t0x0002\t/* standard link-level pause on */\n#define VNIC_STF_PFC_PAUSE\t0x0004\t/* priority flow control pause on */\n/* all supported status flags */\n#define VNIC_STF_ALL\t\t(VNIC_STF_FATAL_ERR |\\\n\t\t\t\t VNIC_STF_STD_PAUSE |\\\n\t\t\t\t VNIC_STF_PFC_PAUSE |\\\n\t\t\t\t 0)\n\nstruct vnic_devcmd_provinfo {\n\tu8 oui[3];\n\tu8 type;\n\tu8 data[0];\n};\n\n/*\n * These are used in flags field of different filters to denote\n * valid fields used.\n */\n#define FILTER_FIELD_VALID(fld) (1 << (fld - 1))\n\n#define FILTER_FIELDS_USNIC (FILTER_FIELD_VALID(1) | \\\n\t\t\t FILTER_FIELD_VALID(2) | \\\n\t\t\t FILTER_FIELD_VALID(3) | \\\n\t\t\t FILTER_FIELD_VALID(4))\n\n#define FILTER_FIELDS_IPV4_5TUPLE (FILTER_FIELD_VALID(1) | \\\n\t\t\t\t FILTER_FIELD_VALID(2) | \\\n\t\t\t\t FILTER_FIELD_VALID(3) | \\\n\t\t\t\t FILTER_FIELD_VALID(4) | \\\n\t\t\t\t FILTER_FIELD_VALID(5))\n\n#define FILTER_FIELDS_MAC_VLAN (FILTER_FIELD_VALID(1) | \\\n\t\t\t\tFILTER_FIELD_VALID(2))\n\n#define FILTER_FIELD_USNIC_VLAN FILTER_FIELD_VALID(1)\n#define FILTER_FIELD_USNIC_ETHTYPE FILTER_FIELD_VALID(2)\n#define FILTER_FIELD_USNIC_PROTO FILTER_FIELD_VALID(3)\n#define FILTER_FIELD_USNIC_ID FILTER_FIELD_VALID(4)\n\nstruct filter_usnic_id {\n\tu32 flags;\n\tu16 vlan;\n\tu16 ethtype;\n\tu8 proto_version;\n\tu32 usnic_id;\n} __attribute__((packed));\n\n#define FILTER_FIELD_5TUP_PROTO FILTER_FIELD_VALID(1)\n#define FILTER_FIELD_5TUP_SRC_AD FILTER_FIELD_VALID(2)\n#define FILTER_FIELD_5TUP_DST_AD FILTER_FIELD_VALID(3)\n#define FILTER_FIELD_5TUP_SRC_PT FILTER_FIELD_VALID(4)\n#define FILTER_FIELD_5TUP_DST_PT FILTER_FIELD_VALID(5)\n\n/* Enums for the protocol field. */\nenum protocol_e {\n\tPROTO_UDP = 0,\n\tPROTO_TCP = 1,\n};\n\nstruct filter_ipv4_5tuple {\n\tu32 flags;\n\tu32 protocol;\n\tu32 src_addr;\n\tu32 dst_addr;\n\tu16 src_port;\n\tu16 dst_port;\n} __attribute__((packed));\n\n#define FILTER_FIELD_VMQ_VLAN FILTER_FIELD_VALID(1)\n#define FILTER_FIELD_VMQ_MAC FILTER_FIELD_VALID(2)\n\nstruct filter_mac_vlan {\n\tu32 flags;\n\tu16 vlan;\n\tu8 mac_addr[6];\n} __attribute__((packed));\n\n/* Specifies the filter_action type. */\nenum {\n\tFILTER_ACTION_RQ_STEERING = 0,\n\tFILTER_ACTION_MAX\n};\n\nstruct filter_action {\n\tu32 type;\n\tunion {\n\t\tu32 rq_idx;\n\t} u;\n} __attribute__((packed));\n\n/* Specifies the filter type. */\nenum filter_type {\n\tFILTER_USNIC_ID = 0,\n\tFILTER_IPV4_5TUPLE = 1,\n\tFILTER_MAC_VLAN = 2,\n\tFILTER_MAX\n};\n\nstruct filter {\n\tu32 type;\n\tunion {\n\t\tstruct filter_usnic_id usnic;\n\t\tstruct filter_ipv4_5tuple ipv4;\n\t\tstruct filter_mac_vlan mac_vlan;\n\t} u;\n} __attribute__((packed));\n\nenum {\n\tCLSF_TLV_FILTER = 0,\n\tCLSF_TLV_ACTION = 1,\n};\n\n#define FILTER_MAX_BUF_SIZE 100 /* Maximum size of buffer to CMD_ADD_FILTER */\n\nstruct filter_tlv {\n\tuint32_t type;\n\tuint32_t length;\n\tuint32_t val[0];\n};\n\nenum {\n\tCLSF_ADD = 0,\n\tCLSF_DEL = 1,\n};\n\n/*\n * Writing cmd register causes STAT_BUSY to get set in status register.\n * When cmd completes, STAT_BUSY will be cleared.\n *\n * If cmd completed successfully STAT_ERROR will be clear\n * and args registers contain cmd-specific results.\n *\n * If cmd error, STAT_ERROR will be set and args[0] contains error code.\n *\n * status register is read-only. While STAT_BUSY is set,\n * all other register contents are read-only.\n */\n\n/* Make sizeof(vnic_devcmd) a power-of-2 for I/O BAR. */\n#define VNIC_DEVCMD_NARGS 15\nstruct vnic_devcmd {\n\tu32 status;\t\t\t/* RO */\n\tu32 cmd;\t\t\t/* RW */\n\tu64 args[VNIC_DEVCMD_NARGS];\t/* RW cmd args (little-endian) */\n};\n\n/*\n * Version 2 of the interface.\n *\n * Some things are carried over, notably the vnic_devcmd_cmd enum.\n */\n\n/*\n * Flags for vnic_devcmd2.flags\n */\n\n#define DEVCMD2_FNORESULT 0x1 /* Don't copy result to host */\n\n#define VNIC_DEVCMD2_NARGS VNIC_DEVCMD_NARGS\nstruct vnic_devcmd2 {\n\tu16 pad;\n\tu16 flags;\n\tu32 cmd; /* same command #defines as original */\n\tu64 args[VNIC_DEVCMD2_NARGS];\n};\n\n#define VNIC_DEVCMD2_NRESULTS VNIC_DEVCMD_NARGS\nstruct devcmd2_result {\n\tu64 results[VNIC_DEVCMD2_NRESULTS];\n\tu32 pad;\n\tu16 completed_index; /* into copy WQ */\n\tu8 error; /* same error codes as original */\n\tu8 color; /* 0 or 1 as with completion queues */\n};\n\n#define DEVCMD2_RING_SIZE 32\n#define DEVCMD2_DESC_SIZE 128\n\n#define DEVCMD2_RESULTS_SIZE_MAX ((1 << 16) - 1)\n\n/* Overlay related definitions */\n\n/*\n * This enum lists the flag associated with each of the overlay features\n */\ntypedef enum {\n\tOVERLAY_FEATURE_NVGRE = 1,\n\tOVERLAY_FEATURE_VXLAN,\n\tOVERLAY_FEATURE_MAX,\n} overlay_feature_t;\n\n#define OVERLAY_OFFLOAD_ENABLE 0\n#define OVERLAY_OFFLOAD_DISABLE 1\n\n#define OVERLAY_CFG_VXLAN_PORT_UPDATE 0\n#endif /* _VNIC_DEVCMD_H_ */\n" }, { "path": "drivers/net/enic/base/vnic_enet.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_enet.h 175806 2014-06-04 19:31:17Z rfaucett $\"\n\n#ifndef _VNIC_ENIC_H_\n#define _VNIC_ENIC_H_\n\n/* Device-specific region: enet configuration */\nstruct vnic_enet_config {\n\tu32 flags;\n\tu32 wq_desc_count;\n\tu32 rq_desc_count;\n\tu16 mtu;\n\tu16 intr_timer_deprecated;\n\tu8 intr_timer_type;\n\tu8 intr_mode;\n\tchar devname[16];\n\tu32 intr_timer_usec;\n\tu16 loop_tag;\n\tu16 vf_rq_count;\n\tu16 num_arfs;\n\tu64 mem_paddr;\n};\n\n#define VENETF_TSO\t\t0x1\t/* TSO enabled */\n#define VENETF_LRO\t\t0x2\t/* LRO enabled */\n#define VENETF_RXCSUM\t\t0x4\t/* RX csum enabled */\n#define VENETF_TXCSUM\t\t0x8\t/* TX csum enabled */\n#define VENETF_RSS\t\t0x10\t/* RSS enabled */\n#define VENETF_RSSHASH_IPV4\t0x20\t/* Hash on IPv4 fields */\n#define VENETF_RSSHASH_TCPIPV4\t0x40\t/* Hash on TCP + IPv4 fields */\n#define VENETF_RSSHASH_IPV6\t0x80\t/* Hash on IPv6 fields */\n#define VENETF_RSSHASH_TCPIPV6\t0x100\t/* Hash on TCP + IPv6 fields */\n#define VENETF_RSSHASH_IPV6_EX\t0x200\t/* Hash on IPv6 extended fields */\n#define VENETF_RSSHASH_TCPIPV6_EX 0x400\t/* Hash on TCP + IPv6 ext. fields */\n#define VENETF_LOOP\t\t0x800\t/* Loopback enabled */\n#define VENETF_VMQ\t\t0x4000 /* using VMQ flag for VMware NETQ */\n#define VENETF_VXLAN 0x10000 /* VxLAN offload */\n#define VENETF_NVGRE 0x20000 /* NVGRE offload */\n#define VENET_INTR_TYPE_MIN\t0\t/* Timer specs min interrupt spacing */\n#define VENET_INTR_TYPE_IDLE\t1\t/* Timer specs idle time before irq */\n\n#define VENET_INTR_MODE_ANY\t0\t/* Try MSI-X, then MSI, then INTx */\n#define VENET_INTR_MODE_MSI\t1\t/* Try MSI then INTx */\n#define VENET_INTR_MODE_INTX\t2\t/* Try INTx only */\n\n#endif /* _VNIC_ENIC_H_ */\n" }, { "path": "drivers/net/enic/base/vnic_intr.c", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_intr.c 171146 2014-05-02 07:08:20Z ssujith $\"\n\n#include \"vnic_dev.h\"\n#include \"vnic_intr.h\"\n\nvoid vnic_intr_free(struct vnic_intr *intr)\n{\n\tintr->ctrl = NULL;\n}\n\nint vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr,\n\tunsigned int index)\n{\n\tintr->index = index;\n\tintr->vdev = vdev;\n\n\tintr->ctrl = vnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index);\n\tif (!intr->ctrl) {\n\t\tpr_err(\"Failed to hook INTR[%d].ctrl resource\\n\", index);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nvoid vnic_intr_init(struct vnic_intr *intr, u32 coalescing_timer,\n\tunsigned int coalescing_type, unsigned int mask_on_assertion)\n{\n\tvnic_intr_coalescing_timer_set(intr, coalescing_timer);\n\tiowrite32(coalescing_type, &intr->ctrl->coalescing_type);\n\tiowrite32(mask_on_assertion, &intr->ctrl->mask_on_assertion);\n\tiowrite32(0, &intr->ctrl->int_credits);\n}\n\nvoid vnic_intr_coalescing_timer_set(struct vnic_intr *intr,\n\tu32 coalescing_timer)\n{\n\tiowrite32(vnic_dev_intr_coal_timer_usec_to_hw(intr->vdev,\n\t\tcoalescing_timer), &intr->ctrl->coalescing_timer);\n}\n\nvoid vnic_intr_clean(struct vnic_intr *intr)\n{\n\tiowrite32(0, &intr->ctrl->int_credits);\n}\n" }, { "path": "drivers/net/enic/base/vnic_intr.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_intr.h 171146 2014-05-02 07:08:20Z ssujith $\"\n\n#ifndef _VNIC_INTR_H_\n#define _VNIC_INTR_H_\n\n\n#include \"vnic_dev.h\"\n\n#define VNIC_INTR_TIMER_TYPE_ABS\t0\n#define VNIC_INTR_TIMER_TYPE_QUIET\t1\n\n/* Interrupt control */\nstruct vnic_intr_ctrl {\n\tu32 coalescing_timer;\t\t/* 0x00 */\n\tu32 pad0;\n\tu32 coalescing_value;\t\t/* 0x08 */\n\tu32 pad1;\n\tu32 coalescing_type;\t\t/* 0x10 */\n\tu32 pad2;\n\tu32 mask_on_assertion;\t\t/* 0x18 */\n\tu32 pad3;\n\tu32 mask;\t\t\t/* 0x20 */\n\tu32 pad4;\n\tu32 int_credits;\t\t/* 0x28 */\n\tu32 pad5;\n\tu32 int_credit_return;\t\t/* 0x30 */\n\tu32 pad6;\n};\n\nstruct vnic_intr {\n\tunsigned int index;\n\tstruct vnic_dev *vdev;\n\tstruct vnic_intr_ctrl __iomem *ctrl;\t\t/* memory-mapped */\n};\n\nstatic inline void vnic_intr_unmask(struct vnic_intr *intr)\n{\n\tiowrite32(0, &intr->ctrl->mask);\n}\n\nstatic inline void vnic_intr_mask(struct vnic_intr *intr)\n{\n\tiowrite32(1, &intr->ctrl->mask);\n}\n\nstatic inline int vnic_intr_masked(struct vnic_intr *intr)\n{\n\treturn ioread32(&intr->ctrl->mask);\n}\n\nstatic inline void vnic_intr_return_credits(struct vnic_intr *intr,\n\tunsigned int credits, int unmask, int reset_timer)\n{\n#define VNIC_INTR_UNMASK_SHIFT\t\t16\n#define VNIC_INTR_RESET_TIMER_SHIFT\t17\n\n\tu32 int_credit_return = (credits & 0xffff) |\n\t\t(unmask ? (1 << VNIC_INTR_UNMASK_SHIFT) : 0) |\n\t\t(reset_timer ? (1 << VNIC_INTR_RESET_TIMER_SHIFT) : 0);\n\n\tiowrite32(int_credit_return, &intr->ctrl->int_credit_return);\n}\n\nstatic inline unsigned int vnic_intr_credits(struct vnic_intr *intr)\n{\n\treturn ioread32(&intr->ctrl->int_credits);\n}\n\nstatic inline void vnic_intr_return_all_credits(struct vnic_intr *intr)\n{\n\tunsigned int credits = vnic_intr_credits(intr);\n\tint unmask = 1;\n\tint reset_timer = 1;\n\n\tvnic_intr_return_credits(intr, credits, unmask, reset_timer);\n}\n\nstatic inline u32 vnic_intr_legacy_pba(u32 __iomem *legacy_pba)\n{\n\t/* read PBA without clearing */\n\treturn ioread32(legacy_pba);\n}\n\nvoid vnic_intr_free(struct vnic_intr *intr);\nint vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr,\n\tunsigned int index);\nvoid vnic_intr_init(struct vnic_intr *intr, u32 coalescing_timer,\n\tunsigned int coalescing_type, unsigned int mask_on_assertion);\nvoid vnic_intr_coalescing_timer_set(struct vnic_intr *intr,\n\tu32 coalescing_timer);\nvoid vnic_intr_clean(struct vnic_intr *intr);\n\n#endif /* _VNIC_INTR_H_ */\n" }, { "path": "drivers/net/enic/base/vnic_nic.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_nic.h 59839 2010-09-27 20:36:31Z roprabhu $\"\n\n#ifndef _VNIC_NIC_H_\n#define _VNIC_NIC_H_\n\n#define NIC_CFG_RSS_DEFAULT_CPU_MASK_FIELD\t0xffUL\n#define NIC_CFG_RSS_DEFAULT_CPU_SHIFT\t\t0\n#define NIC_CFG_RSS_HASH_TYPE\t\t\t(0xffUL << 8)\n#define NIC_CFG_RSS_HASH_TYPE_MASK_FIELD\t0xffUL\n#define NIC_CFG_RSS_HASH_TYPE_SHIFT\t\t8\n#define NIC_CFG_RSS_HASH_BITS\t\t\t(7UL << 16)\n#define NIC_CFG_RSS_HASH_BITS_MASK_FIELD\t7UL\n#define NIC_CFG_RSS_HASH_BITS_SHIFT\t\t16\n#define NIC_CFG_RSS_BASE_CPU\t\t\t(7UL << 19)\n#define NIC_CFG_RSS_BASE_CPU_MASK_FIELD\t\t7UL\n#define NIC_CFG_RSS_BASE_CPU_SHIFT\t\t19\n#define NIC_CFG_RSS_ENABLE\t\t\t(1UL << 22)\n#define NIC_CFG_RSS_ENABLE_MASK_FIELD\t\t1UL\n#define NIC_CFG_RSS_ENABLE_SHIFT\t\t22\n#define NIC_CFG_TSO_IPID_SPLIT_EN\t\t(1UL << 23)\n#define NIC_CFG_TSO_IPID_SPLIT_EN_MASK_FIELD\t1UL\n#define NIC_CFG_TSO_IPID_SPLIT_EN_SHIFT\t\t23\n#define NIC_CFG_IG_VLAN_STRIP_EN\t\t(1UL << 24)\n#define NIC_CFG_IG_VLAN_STRIP_EN_MASK_FIELD\t1UL\n#define NIC_CFG_IG_VLAN_STRIP_EN_SHIFT\t\t24\n\n#define NIC_CFG_RSS_HASH_TYPE_IPV4\t\t(1 << 1)\n#define NIC_CFG_RSS_HASH_TYPE_TCP_IPV4\t\t(1 << 2)\n#define NIC_CFG_RSS_HASH_TYPE_IPV6\t\t(1 << 3)\n#define NIC_CFG_RSS_HASH_TYPE_TCP_IPV6\t\t(1 << 4)\n#define NIC_CFG_RSS_HASH_TYPE_IPV6_EX\t\t(1 << 5)\n#define NIC_CFG_RSS_HASH_TYPE_TCP_IPV6_EX\t(1 << 6)\n\nstatic inline void vnic_set_nic_cfg(u32 *nic_cfg,\n\tu8 rss_default_cpu, u8 rss_hash_type,\n\tu8 rss_hash_bits, u8 rss_base_cpu,\n\tu8 rss_enable, u8 tso_ipid_split_en,\n\tu8 ig_vlan_strip_en)\n{\n\t*nic_cfg = (rss_default_cpu & NIC_CFG_RSS_DEFAULT_CPU_MASK_FIELD) |\n\t\t((rss_hash_type & NIC_CFG_RSS_HASH_TYPE_MASK_FIELD)\n\t\t\t<< NIC_CFG_RSS_HASH_TYPE_SHIFT) |\n\t\t((rss_hash_bits & NIC_CFG_RSS_HASH_BITS_MASK_FIELD)\n\t\t\t<< NIC_CFG_RSS_HASH_BITS_SHIFT) |\n\t\t((rss_base_cpu & NIC_CFG_RSS_BASE_CPU_MASK_FIELD)\n\t\t\t<< NIC_CFG_RSS_BASE_CPU_SHIFT) |\n\t\t((rss_enable & NIC_CFG_RSS_ENABLE_MASK_FIELD)\n\t\t\t<< NIC_CFG_RSS_ENABLE_SHIFT) |\n\t\t((tso_ipid_split_en & NIC_CFG_TSO_IPID_SPLIT_EN_MASK_FIELD)\n\t\t\t<< NIC_CFG_TSO_IPID_SPLIT_EN_SHIFT) |\n\t\t((ig_vlan_strip_en & NIC_CFG_IG_VLAN_STRIP_EN_MASK_FIELD)\n\t\t\t<< NIC_CFG_IG_VLAN_STRIP_EN_SHIFT);\n}\n\n#endif /* _VNIC_NIC_H_ */\n" }, { "path": "drivers/net/enic/base/vnic_resource.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_resource.h 196958 2014-11-04 18:23:37Z xuywang $\"\n\n#ifndef _VNIC_RESOURCE_H_\n#define _VNIC_RESOURCE_H_\n\n#define VNIC_RES_MAGIC\t\t0x766E6963L\t/* 'vnic' */\n#define VNIC_RES_VERSION\t0x00000000L\n#define MGMTVNIC_MAGIC\t\t0x544d474dL\t/* 'MGMT' */\n#define MGMTVNIC_VERSION\t0x00000000L\n\n/* The MAC address assigned to the CFG vNIC is fixed. */\n#define MGMTVNIC_MAC\t\t{ 0x02, 0x00, 0x54, 0x4d, 0x47, 0x4d }\n\n/* vNIC resource types */\nenum vnic_res_type {\n\tRES_TYPE_EOL,\t\t\t/* End-of-list */\n\tRES_TYPE_WQ,\t\t\t/* Work queues */\n\tRES_TYPE_RQ,\t\t\t/* Receive queues */\n\tRES_TYPE_CQ,\t\t\t/* Completion queues */\n\tRES_TYPE_MEM,\t\t\t/* Window to dev memory */\n\tRES_TYPE_NIC_CFG,\t\t/* Enet NIC config registers */\n\tRES_TYPE_RSS_KEY,\t\t/* Enet RSS secret key */\n\tRES_TYPE_RSS_CPU,\t\t/* Enet RSS indirection table */\n\tRES_TYPE_TX_STATS,\t\t/* Netblock Tx statistic regs */\n\tRES_TYPE_RX_STATS,\t\t/* Netblock Rx statistic regs */\n\tRES_TYPE_INTR_CTRL,\t\t/* Interrupt ctrl table */\n\tRES_TYPE_INTR_TABLE,\t\t/* MSI/MSI-X Interrupt table */\n\tRES_TYPE_INTR_PBA,\t\t/* MSI/MSI-X PBA table */\n\tRES_TYPE_INTR_PBA_LEGACY,\t/* Legacy intr status */\n\tRES_TYPE_DEBUG,\t\t\t/* Debug-only info */\n\tRES_TYPE_DEV,\t\t\t/* Device-specific region */\n\tRES_TYPE_DEVCMD,\t\t/* Device command region */\n\tRES_TYPE_PASS_THRU_PAGE,\t/* Pass-thru page */\n\tRES_TYPE_SUBVNIC, /* subvnic resource type */\n\tRES_TYPE_MQ_WQ, /* MQ Work queues */\n\tRES_TYPE_MQ_RQ, /* MQ Receive queues */\n\tRES_TYPE_MQ_CQ, /* MQ Completion queues */\n\tRES_TYPE_DEPRECATED1, /* Old version of devcmd 2 */\n\tRES_TYPE_DEVCMD2, /* Device control region */\n\tRES_TYPE_MAX,\t\t\t/* Count of resource types */\n};\n\nstruct vnic_resource_header {\n\tu32 magic;\n\tu32 version;\n};\n\nstruct mgmt_barmap_hdr {\n\tu32 magic;\t\t\t/* magic number */\n\tu32 version;\t\t\t/* header format version */\n\tu16 lif;\t\t\t/* loopback lif for mgmt frames */\n\tu16 pci_slot;\t\t\t/* installed pci slot */\n\tchar serial[16];\t\t/* card serial number */\n};\n\nstruct vnic_resource {\n\tu8 type;\n\tu8 bar;\n\tu8 pad[2];\n\tu32 bar_offset;\n\tu32 count;\n};\n\n#endif /* _VNIC_RESOURCE_H_ */\n" }, { "path": "drivers/net/enic/base/vnic_rq.c", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_rq.c 171146 2014-05-02 07:08:20Z ssujith $\"\n\n#include \"vnic_dev.h\"\n#include \"vnic_rq.h\"\n\nstatic int vnic_rq_alloc_bufs(struct vnic_rq *rq)\n{\n\tstruct vnic_rq_buf *buf;\n\tunsigned int i, j, count = rq->ring.desc_count;\n\tunsigned int blks = VNIC_RQ_BUF_BLKS_NEEDED(count);\n\n\tfor (i = 0; i < blks; i++) {\n\t\trq->bufs[i] = kzalloc(VNIC_RQ_BUF_BLK_SZ(count), GFP_ATOMIC);\n\t\tif (!rq->bufs[i])\n\t\t\treturn -ENOMEM;\n\t}\n\n\tfor (i = 0; i < blks; i++) {\n\t\tbuf = rq->bufs[i];\n\t\tfor (j = 0; j < VNIC_RQ_BUF_BLK_ENTRIES(count); j++) {\n\t\t\tbuf->index = i * VNIC_RQ_BUF_BLK_ENTRIES(count) + j;\n\t\t\tbuf->desc = (u8 *)rq->ring.descs +\n\t\t\t\trq->ring.desc_size * buf->index;\n\t\t\tif (buf->index + 1 == count) {\n\t\t\t\tbuf->next = rq->bufs[0];\n\t\t\t\tbreak;\n\t\t\t} else if (j + 1 == VNIC_RQ_BUF_BLK_ENTRIES(count)) {\n\t\t\t\tbuf->next = rq->bufs[i + 1];\n\t\t\t} else {\n\t\t\t\tbuf->next = buf + 1;\n\t\t\t\tbuf++;\n\t\t\t}\n\t\t}\n\t}\n\n\trq->to_use = rq->to_clean = rq->bufs[0];\n\n\treturn 0;\n}\n\nint vnic_rq_mem_size(struct vnic_rq *rq, unsigned int desc_count,\n\tunsigned int desc_size)\n{\n\tint mem_size = 0;\n\n\tmem_size += vnic_dev_desc_ring_size(&rq->ring, desc_count, desc_size);\n\n\tmem_size += VNIC_RQ_BUF_BLKS_NEEDED(rq->ring.desc_count) *\n\t\tVNIC_RQ_BUF_BLK_SZ(rq->ring.desc_count);\n\n\treturn mem_size;\n}\n\nvoid vnic_rq_free(struct vnic_rq *rq)\n{\n\tstruct vnic_dev *vdev;\n\tunsigned int i;\n\n\tvdev = rq->vdev;\n\n\tvnic_dev_free_desc_ring(vdev, &rq->ring);\n\n\tfor (i = 0; i < VNIC_RQ_BUF_BLKS_MAX; i++) {\n\t\tif (rq->bufs[i]) {\n\t\t\tkfree(rq->bufs[i]);\n\t\t\trq->bufs[i] = NULL;\n\t\t}\n\t}\n\n\trq->ctrl = NULL;\n}\n\nint vnic_rq_alloc(struct vnic_dev *vdev, struct vnic_rq *rq, unsigned int index,\n\tunsigned int desc_count, unsigned int desc_size)\n{\n\tint err;\n\tchar res_name[NAME_MAX];\n\tstatic int instance;\n\n\trq->index = index;\n\trq->vdev = vdev;\n\n\trq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_RQ, index);\n\tif (!rq->ctrl) {\n\t\tpr_err(\"Failed to hook RQ[%d] resource\\n\", index);\n\t\treturn -EINVAL;\n\t}\n\n\tvnic_rq_disable(rq);\n\n\tsnprintf(res_name, sizeof(res_name), \"%d-rq-%d\", instance++, index);\n\terr = vnic_dev_alloc_desc_ring(vdev, &rq->ring, desc_count, desc_size,\n\t\trq->socket_id, res_name);\n\tif (err)\n\t\treturn err;\n\n\terr = vnic_rq_alloc_bufs(rq);\n\tif (err) {\n\t\tvnic_rq_free(rq);\n\t\treturn err;\n\t}\n\n\treturn 0;\n}\n\nvoid vnic_rq_init_start(struct vnic_rq *rq, unsigned int cq_index,\n\tunsigned int fetch_index, unsigned int posted_index,\n\tunsigned int error_interrupt_enable,\n\tunsigned int error_interrupt_offset)\n{\n\tu64 paddr;\n\tunsigned int count = rq->ring.desc_count;\n\n\tpaddr = (u64)rq->ring.base_addr | VNIC_PADDR_TARGET;\n\twriteq(paddr, &rq->ctrl->ring_base);\n\tiowrite32(count, &rq->ctrl->ring_size);\n\tiowrite32(cq_index, &rq->ctrl->cq_index);\n\tiowrite32(error_interrupt_enable, &rq->ctrl->error_interrupt_enable);\n\tiowrite32(error_interrupt_offset, &rq->ctrl->error_interrupt_offset);\n\tiowrite32(0, &rq->ctrl->dropped_packet_count);\n\tiowrite32(0, &rq->ctrl->error_status);\n\tiowrite32(fetch_index, &rq->ctrl->fetch_index);\n\tiowrite32(posted_index, &rq->ctrl->posted_index);\n\n\trq->to_use = rq->to_clean =\n\t\t&rq->bufs[fetch_index / VNIC_RQ_BUF_BLK_ENTRIES(count)]\n\t\t\t[fetch_index % VNIC_RQ_BUF_BLK_ENTRIES(count)];\n}\n\nvoid vnic_rq_init(struct vnic_rq *rq, unsigned int cq_index,\n\tunsigned int error_interrupt_enable,\n\tunsigned int error_interrupt_offset)\n{\n\tu32 fetch_index = 0;\n\t/* Use current fetch_index as the ring starting point */\n\tfetch_index = ioread32(&rq->ctrl->fetch_index);\n\n\tif (fetch_index == 0xFFFFFFFF) { /* check for hardware gone */\n\t\t/* Hardware surprise removal: reset fetch_index */\n\t\tfetch_index = 0;\n\t}\n\n\tvnic_rq_init_start(rq, cq_index,\n\t\tfetch_index, fetch_index,\n\t\terror_interrupt_enable,\n\t\terror_interrupt_offset);\n}\n\nvoid vnic_rq_error_out(struct vnic_rq *rq, unsigned int error)\n{\n\tiowrite32(error, &rq->ctrl->error_status);\n}\n\nunsigned int vnic_rq_error_status(struct vnic_rq *rq)\n{\n\treturn ioread32(&rq->ctrl->error_status);\n}\n\nvoid vnic_rq_enable(struct vnic_rq *rq)\n{\n\tiowrite32(1, &rq->ctrl->enable);\n}\n\nint vnic_rq_disable(struct vnic_rq *rq)\n{\n\tunsigned int wait;\n\n\tiowrite32(0, &rq->ctrl->enable);\n\n\t/* Wait for HW to ACK disable request */\n\tfor (wait = 0; wait < 1000; wait++) {\n\t\tif (!(ioread32(&rq->ctrl->running)))\n\t\t\treturn 0;\n\t\tudelay(10);\n\t}\n\n\tpr_err(\"Failed to disable RQ[%d]\\n\", rq->index);\n\n\treturn -ETIMEDOUT;\n}\n\nvoid vnic_rq_clean(struct vnic_rq *rq,\n\tvoid (*buf_clean)(struct vnic_rq *rq, struct vnic_rq_buf *buf))\n{\n\tstruct vnic_rq_buf *buf;\n\tu32 fetch_index;\n\tunsigned int count = rq->ring.desc_count;\n\n\tbuf = rq->to_clean;\n\n\twhile (vnic_rq_desc_used(rq) > 0) {\n\n\t\t(*buf_clean)(rq, buf);\n\n\t\tbuf = rq->to_clean = buf->next;\n\t\trq->ring.desc_avail++;\n\t}\n\n\t/* Use current fetch_index as the ring starting point */\n\tfetch_index = ioread32(&rq->ctrl->fetch_index);\n\n\tif (fetch_index == 0xFFFFFFFF) { /* check for hardware gone */\n\t\t/* Hardware surprise removal: reset fetch_index */\n\t\tfetch_index = 0;\n\t}\n\trq->to_use = rq->to_clean =\n\t\t&rq->bufs[fetch_index / VNIC_RQ_BUF_BLK_ENTRIES(count)]\n\t\t\t[fetch_index % VNIC_RQ_BUF_BLK_ENTRIES(count)];\n\tiowrite32(fetch_index, &rq->ctrl->posted_index);\n\n\tvnic_dev_clear_desc_ring(&rq->ring);\n}\n" }, { "path": "drivers/net/enic/base/vnic_rq.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_rq.h 180262 2014-07-02 07:57:43Z gvaradar $\"\n\n#ifndef _VNIC_RQ_H_\n#define _VNIC_RQ_H_\n\n\n#include \"vnic_dev.h\"\n#include \"vnic_cq.h\"\n\n/* Receive queue control */\nstruct vnic_rq_ctrl {\n\tu64 ring_base;\t\t\t/* 0x00 */\n\tu32 ring_size;\t\t\t/* 0x08 */\n\tu32 pad0;\n\tu32 posted_index;\t\t/* 0x10 */\n\tu32 pad1;\n\tu32 cq_index;\t\t\t/* 0x18 */\n\tu32 pad2;\n\tu32 enable;\t\t\t/* 0x20 */\n\tu32 pad3;\n\tu32 running;\t\t\t/* 0x28 */\n\tu32 pad4;\n\tu32 fetch_index;\t\t/* 0x30 */\n\tu32 pad5;\n\tu32 error_interrupt_enable;\t/* 0x38 */\n\tu32 pad6;\n\tu32 error_interrupt_offset;\t/* 0x40 */\n\tu32 pad7;\n\tu32 error_status;\t\t/* 0x48 */\n\tu32 pad8;\n\tu32 dropped_packet_count;\t/* 0x50 */\n\tu32 pad9;\n\tu32 dropped_packet_count_rc;\t/* 0x58 */\n\tu32 pad10;\n};\n\n/* Break the vnic_rq_buf allocations into blocks of 32/64 entries */\n#define VNIC_RQ_BUF_MIN_BLK_ENTRIES 32\n#define VNIC_RQ_BUF_DFLT_BLK_ENTRIES 64\n#define VNIC_RQ_BUF_BLK_ENTRIES(entries) \\\n\t((unsigned int)((entries < VNIC_RQ_BUF_DFLT_BLK_ENTRIES) ? \\\n\tVNIC_RQ_BUF_MIN_BLK_ENTRIES : VNIC_RQ_BUF_DFLT_BLK_ENTRIES))\n#define VNIC_RQ_BUF_BLK_SZ(entries) \\\n\t(VNIC_RQ_BUF_BLK_ENTRIES(entries) * sizeof(struct vnic_rq_buf))\n#define VNIC_RQ_BUF_BLKS_NEEDED(entries) \\\n\tDIV_ROUND_UP(entries, VNIC_RQ_BUF_BLK_ENTRIES(entries))\n#define VNIC_RQ_BUF_BLKS_MAX VNIC_RQ_BUF_BLKS_NEEDED(4096)\n\nstruct vnic_rq_buf {\n\tstruct vnic_rq_buf *next;\n\tdma_addr_t dma_addr;\n\tvoid *os_buf;\n\tunsigned int os_buf_index;\n\tunsigned int len;\n\tunsigned int index;\n\tvoid *desc;\n\tuint64_t wr_id;\n};\n\nstruct vnic_rq {\n\tunsigned int index;\n\tstruct vnic_dev *vdev;\n\tstruct vnic_rq_ctrl __iomem *ctrl; /* memory-mapped */\n\tstruct vnic_dev_ring ring;\n\tstruct vnic_rq_buf *bufs[VNIC_RQ_BUF_BLKS_MAX];\n\tstruct vnic_rq_buf *to_use;\n\tstruct vnic_rq_buf *to_clean;\n\tvoid *os_buf_head;\n\tunsigned int pkts_outstanding;\n\n\tunsigned int socket_id;\n\tstruct rte_mempool *mp;\n};\n\nstatic inline unsigned int vnic_rq_desc_avail(struct vnic_rq *rq)\n{\n\t/* how many does SW own? */\n\treturn rq->ring.desc_avail;\n}\n\nstatic inline unsigned int vnic_rq_desc_used(struct vnic_rq *rq)\n{\n\t/* how many does HW own? */\n\treturn rq->ring.desc_count - rq->ring.desc_avail - 1;\n}\n\nstatic inline void *vnic_rq_next_desc(struct vnic_rq *rq)\n{\n\treturn rq->to_use->desc;\n}\n\nstatic inline unsigned int vnic_rq_next_index(struct vnic_rq *rq)\n{\n\treturn rq->to_use->index;\n}\n\nstatic inline void vnic_rq_post(struct vnic_rq *rq,\n\tvoid *os_buf, unsigned int os_buf_index,\n\tdma_addr_t dma_addr, unsigned int len,\n\tuint64_t wrid)\n{\n\tstruct vnic_rq_buf *buf = rq->to_use;\n\n\tbuf->os_buf = os_buf;\n\tbuf->os_buf_index = os_buf_index;\n\tbuf->dma_addr = dma_addr;\n\tbuf->len = len;\n\tbuf->wr_id = wrid;\n\n\tbuf = buf->next;\n\trq->to_use = buf;\n\trq->ring.desc_avail--;\n\n\t/* Move the posted_index every nth descriptor\n\t */\n\n#ifndef VNIC_RQ_RETURN_RATE\n#define VNIC_RQ_RETURN_RATE\t\t0xf\t/* keep 2^n - 1 */\n#endif\n\n\tif ((buf->index & VNIC_RQ_RETURN_RATE) == 0) {\n\t\t/* Adding write memory barrier prevents compiler and/or CPU\n\t\t * reordering, thus avoiding descriptor posting before\n\t\t * descriptor is initialized. Otherwise, hardware can read\n\t\t * stale descriptor fields.\n\t\t */\n\t\twmb();\n\t\tiowrite32(buf->index, &rq->ctrl->posted_index);\n\t}\n}\n\nstatic inline void vnic_rq_post_commit(struct vnic_rq *rq,\n\tvoid *os_buf, unsigned int os_buf_index,\n\tdma_addr_t dma_addr, unsigned int len)\n{\n\tstruct vnic_rq_buf *buf = rq->to_use;\n\n\tbuf->os_buf = os_buf;\n\tbuf->os_buf_index = os_buf_index;\n\tbuf->dma_addr = dma_addr;\n\tbuf->len = len;\n\n\tbuf = buf->next;\n\trq->to_use = buf;\n\trq->ring.desc_avail--;\n\n\t/* Move the posted_index every descriptor\n\t */\n\n\t/* Adding write memory barrier prevents compiler and/or CPU\n\t * reordering, thus avoiding descriptor posting before\n\t * descriptor is initialized. Otherwise, hardware can read\n\t * stale descriptor fields.\n\t */\n\twmb();\n\tiowrite32(buf->index, &rq->ctrl->posted_index);\n}\n\nstatic inline void vnic_rq_return_descs(struct vnic_rq *rq, unsigned int count)\n{\n\trq->ring.desc_avail += count;\n}\n\nenum desc_return_options {\n\tVNIC_RQ_RETURN_DESC,\n\tVNIC_RQ_DEFER_RETURN_DESC,\n};\n\nstatic inline int vnic_rq_service(struct vnic_rq *rq,\n\tstruct cq_desc *cq_desc, u16 completed_index,\n\tint desc_return, int (*buf_service)(struct vnic_rq *rq,\n\tstruct cq_desc *cq_desc, struct vnic_rq_buf *buf,\n\tint skipped, void *opaque), void *opaque)\n{\n\tstruct vnic_rq_buf *buf;\n\tint skipped;\n\tint eop = 0;\n\n\tbuf = rq->to_clean;\n\twhile (1) {\n\n\t\tskipped = (buf->index != completed_index);\n\n\t\tif ((*buf_service)(rq, cq_desc, buf, skipped, opaque))\n\t\t\teop++;\n\n\t\tif (desc_return == VNIC_RQ_RETURN_DESC)\n\t\t\trq->ring.desc_avail++;\n\n\t\trq->to_clean = buf->next;\n\n\t\tif (!skipped)\n\t\t\tbreak;\n\n\t\tbuf = rq->to_clean;\n\t}\n\treturn eop;\n}\n\nstatic inline int vnic_rq_fill(struct vnic_rq *rq,\n\tint (*buf_fill)(struct vnic_rq *rq))\n{\n\tint err;\n\n\twhile (vnic_rq_desc_avail(rq) > 0) {\n\n\t\terr = (*buf_fill)(rq);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\treturn 0;\n}\n\nstatic inline int vnic_rq_fill_count(struct vnic_rq *rq,\n\tint (*buf_fill)(struct vnic_rq *rq), unsigned int count)\n{\n\tint err;\n\n\twhile ((vnic_rq_desc_avail(rq) > 0) && (count--)) {\n\n\t\terr = (*buf_fill)(rq);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\treturn 0;\n}\n\nvoid vnic_rq_free(struct vnic_rq *rq);\nint vnic_rq_alloc(struct vnic_dev *vdev, struct vnic_rq *rq, unsigned int index,\n\tunsigned int desc_count, unsigned int desc_size);\nvoid vnic_rq_init_start(struct vnic_rq *rq, unsigned int cq_index,\n\tunsigned int fetch_index, unsigned int posted_index,\n\tunsigned int error_interrupt_enable,\n\tunsigned int error_interrupt_offset);\nvoid vnic_rq_init(struct vnic_rq *rq, unsigned int cq_index,\n\tunsigned int error_interrupt_enable,\n\tunsigned int error_interrupt_offset);\nvoid vnic_rq_error_out(struct vnic_rq *rq, unsigned int error);\nunsigned int vnic_rq_error_status(struct vnic_rq *rq);\nvoid vnic_rq_enable(struct vnic_rq *rq);\nint vnic_rq_disable(struct vnic_rq *rq);\nvoid vnic_rq_clean(struct vnic_rq *rq,\n\tvoid (*buf_clean)(struct vnic_rq *rq, struct vnic_rq_buf *buf));\nint vnic_rq_mem_size(struct vnic_rq *rq, unsigned int desc_count,\n\tunsigned int desc_size);\n\n#endif /* _VNIC_RQ_H_ */\n" }, { "path": "drivers/net/enic/base/vnic_rss.c", "content": "/*\n * Copyright 2008 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id$\"\n\n#include \"enic_compat.h\"\n#include \"vnic_rss.h\"\n\nvoid vnic_set_rss_key(union vnic_rss_key *rss_key, u8 *key)\n{\n\tu32 i;\n\tu32 *p;\n\tu16 *q;\n\n\tfor (i = 0; i < 4; ++i) {\n\t\tp = (u32 *)(key + (10 * i));\n\t\tiowrite32(*p++, &rss_key->key[i].b[0]);\n\t\tiowrite32(*p++, &rss_key->key[i].b[4]);\n\t\tq = (u16 *)p;\n\t\tiowrite32(*q, &rss_key->key[i].b[8]);\n\t}\n}\n\nvoid vnic_set_rss_cpu(union vnic_rss_cpu *rss_cpu, u8 *cpu)\n{\n\tu32 i;\n\tu32 *p = (u32 *)cpu;\n\n\tfor (i = 0; i < 32; ++i)\n\t\tiowrite32(*p++, &rss_cpu->cpu[i].b[0]);\n}\n\nvoid vnic_get_rss_key(union vnic_rss_key *rss_key, u8 *key)\n{\n\tu32 i;\n\tu32 *p;\n\tu16 *q;\n\n\tfor (i = 0; i < 4; ++i) {\n\t\tp = (u32 *)(key + (10 * i));\n\t\t*p++ = ioread32(&rss_key->key[i].b[0]);\n\t\t*p++ = ioread32(&rss_key->key[i].b[4]);\n\t\tq = (u16 *)p;\n\t\t*q = (u16)ioread32(&rss_key->key[i].b[8]);\n\t}\n}\n\nvoid vnic_get_rss_cpu(union vnic_rss_cpu *rss_cpu, u8 *cpu)\n{\n\tu32 i;\n\tu32 *p = (u32 *)cpu;\n\n\tfor (i = 0; i < 32; ++i)\n\t\t*p++ = ioread32(&rss_cpu->cpu[i].b[0]);\n}\n" }, { "path": "drivers/net/enic/base/vnic_rss.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n */\n#ident \"$Id: vnic_rss.h 64224 2010-11-09 19:43:13Z vkolluri $\"\n\n#ifndef _VNIC_RSS_H_\n#define _VNIC_RSS_H_\n\n/* RSS key array */\nunion vnic_rss_key {\n\tstruct {\n\t\tu8 b[10];\n\t\tu8 b_pad[6];\n\t} key[4];\n\tu64 raw[8];\n};\n\n/* RSS cpu array */\nunion vnic_rss_cpu {\n\tstruct {\n\t\tu8 b[4];\n\t\tu8 b_pad[4];\n\t} cpu[32];\n\tu64 raw[32];\n};\n\nvoid vnic_set_rss_key(union vnic_rss_key *rss_key, u8 *key);\nvoid vnic_set_rss_cpu(union vnic_rss_cpu *rss_cpu, u8 *cpu);\nvoid vnic_get_rss_key(union vnic_rss_key *rss_key, u8 *key);\nvoid vnic_get_rss_cpu(union vnic_rss_cpu *rss_cpu, u8 *cpu);\n\n#endif /* _VNIC_RSS_H_ */\n" }, { "path": "drivers/net/enic/base/vnic_stats.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_stats.h 84040 2011-08-09 23:38:43Z dwang2 $\"\n\n#ifndef _VNIC_STATS_H_\n#define _VNIC_STATS_H_\n\n/* Tx statistics */\nstruct vnic_tx_stats {\n\tu64 tx_frames_ok;\n\tu64 tx_unicast_frames_ok;\n\tu64 tx_multicast_frames_ok;\n\tu64 tx_broadcast_frames_ok;\n\tu64 tx_bytes_ok;\n\tu64 tx_unicast_bytes_ok;\n\tu64 tx_multicast_bytes_ok;\n\tu64 tx_broadcast_bytes_ok;\n\tu64 tx_drops;\n\tu64 tx_errors;\n\tu64 tx_tso;\n\tu64 rsvd[16];\n};\n\n/* Rx statistics */\nstruct vnic_rx_stats {\n\tu64 rx_frames_ok;\n\tu64 rx_frames_total;\n\tu64 rx_unicast_frames_ok;\n\tu64 rx_multicast_frames_ok;\n\tu64 rx_broadcast_frames_ok;\n\tu64 rx_bytes_ok;\n\tu64 rx_unicast_bytes_ok;\n\tu64 rx_multicast_bytes_ok;\n\tu64 rx_broadcast_bytes_ok;\n\tu64 rx_drop;\n\tu64 rx_no_bufs;\n\tu64 rx_errors;\n\tu64 rx_rss;\n\tu64 rx_crc_errors;\n\tu64 rx_frames_64;\n\tu64 rx_frames_127;\n\tu64 rx_frames_255;\n\tu64 rx_frames_511;\n\tu64 rx_frames_1023;\n\tu64 rx_frames_1518;\n\tu64 rx_frames_to_max;\n\tu64 rsvd[16];\n};\n\nstruct vnic_stats {\n\tstruct vnic_tx_stats tx;\n\tstruct vnic_rx_stats rx;\n};\n\n#endif /* _VNIC_STATS_H_ */\n" }, { "path": "drivers/net/enic/base/vnic_wq.c", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_wq.c 183023 2014-07-22 23:47:25Z xuywang $\"\n\n#include \"vnic_dev.h\"\n#include \"vnic_wq.h\"\n\nstatic inline\nint vnic_wq_get_ctrl(struct vnic_dev *vdev, struct vnic_wq *wq,\n\t\t\t\tunsigned int index, enum vnic_res_type res_type)\n{\n\twq->ctrl = vnic_dev_get_res(vdev, res_type, index);\n\tif (!wq->ctrl)\n\t\treturn -EINVAL;\n\treturn 0;\n}\n\nstatic inline\nint vnic_wq_alloc_ring(struct vnic_dev *vdev, struct vnic_wq *wq,\n\t\t\t\tunsigned int desc_count, unsigned int desc_size)\n{\n\tchar res_name[NAME_MAX];\n\tstatic int instance;\n\n\tsnprintf(res_name, sizeof(res_name), \"%d-wq-%d\", instance++, wq->index);\n\treturn vnic_dev_alloc_desc_ring(vdev, &wq->ring, desc_count, desc_size,\n\t\twq->socket_id, res_name);\n}\n\nstatic int vnic_wq_alloc_bufs(struct vnic_wq *wq)\n{\n\tstruct vnic_wq_buf *buf;\n\tunsigned int i, j, count = wq->ring.desc_count;\n\tunsigned int blks = VNIC_WQ_BUF_BLKS_NEEDED(count);\n\n\tfor (i = 0; i < blks; i++) {\n\t\twq->bufs[i] = kzalloc(VNIC_WQ_BUF_BLK_SZ(count), GFP_ATOMIC);\n\t\tif (!wq->bufs[i])\n\t\t\treturn -ENOMEM;\n\t}\n\n\tfor (i = 0; i < blks; i++) {\n\t\tbuf = wq->bufs[i];\n\t\tfor (j = 0; j < VNIC_WQ_BUF_BLK_ENTRIES(count); j++) {\n\t\t\tbuf->index = i * VNIC_WQ_BUF_BLK_ENTRIES(count) + j;\n\t\t\tbuf->desc = (u8 *)wq->ring.descs +\n\t\t\t\twq->ring.desc_size * buf->index;\n\t\t\tif (buf->index + 1 == count) {\n\t\t\t\tbuf->next = wq->bufs[0];\n\t\t\t\tbreak;\n\t\t\t} else if (j + 1 == VNIC_WQ_BUF_BLK_ENTRIES(count)) {\n\t\t\t\tbuf->next = wq->bufs[i + 1];\n\t\t\t} else {\n\t\t\t\tbuf->next = buf + 1;\n\t\t\t\tbuf++;\n\t\t\t}\n\t\t}\n\t}\n\n\twq->to_use = wq->to_clean = wq->bufs[0];\n\n\treturn 0;\n}\n\nvoid vnic_wq_free(struct vnic_wq *wq)\n{\n\tstruct vnic_dev *vdev;\n\tunsigned int i;\n\n\tvdev = wq->vdev;\n\n\tvnic_dev_free_desc_ring(vdev, &wq->ring);\n\n\tfor (i = 0; i < VNIC_WQ_BUF_BLKS_MAX; i++) {\n\t\tif (wq->bufs[i]) {\n\t\t\tkfree(wq->bufs[i]);\n\t\t\twq->bufs[i] = NULL;\n\t\t}\n\t}\n\n\twq->ctrl = NULL;\n}\n\nint vnic_wq_mem_size(struct vnic_wq *wq, unsigned int desc_count,\n\tunsigned int desc_size)\n{\n\tint mem_size = 0;\n\n\tmem_size += vnic_dev_desc_ring_size(&wq->ring, desc_count, desc_size);\n\n\tmem_size += VNIC_WQ_BUF_BLKS_NEEDED(wq->ring.desc_count) *\n\t\tVNIC_WQ_BUF_BLK_SZ(wq->ring.desc_count);\n\n\treturn mem_size;\n}\n\n\nint vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,\n\tunsigned int desc_count, unsigned int desc_size)\n{\n\tint err;\n\n\twq->index = index;\n\twq->vdev = vdev;\n\n\terr = vnic_wq_get_ctrl(vdev, wq, index, RES_TYPE_WQ);\n\tif (err) {\n\t\tpr_err(\"Failed to hook WQ[%d] resource, err %d\\n\", index, err);\n\t\treturn err;\n\t}\n\n\tvnic_wq_disable(wq);\n\n\terr = vnic_wq_alloc_ring(vdev, wq, desc_count, desc_size);\n\tif (err)\n\t\treturn err;\n\n\terr = vnic_wq_alloc_bufs(wq);\n\tif (err) {\n\t\tvnic_wq_free(wq);\n\t\treturn err;\n\t}\n\n\treturn 0;\n}\n\nvoid vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,\n\tunsigned int fetch_index, unsigned int posted_index,\n\tunsigned int error_interrupt_enable,\n\tunsigned int error_interrupt_offset)\n{\n\tu64 paddr;\n\tunsigned int count = wq->ring.desc_count;\n\n\tpaddr = (u64)wq->ring.base_addr | VNIC_PADDR_TARGET;\n\twriteq(paddr, &wq->ctrl->ring_base);\n\tiowrite32(count, &wq->ctrl->ring_size);\n\tiowrite32(fetch_index, &wq->ctrl->fetch_index);\n\tiowrite32(posted_index, &wq->ctrl->posted_index);\n\tiowrite32(cq_index, &wq->ctrl->cq_index);\n\tiowrite32(error_interrupt_enable, &wq->ctrl->error_interrupt_enable);\n\tiowrite32(error_interrupt_offset, &wq->ctrl->error_interrupt_offset);\n\tiowrite32(0, &wq->ctrl->error_status);\n\n\twq->to_use = wq->to_clean =\n\t\t&wq->bufs[fetch_index / VNIC_WQ_BUF_BLK_ENTRIES(count)]\n\t\t\t[fetch_index % VNIC_WQ_BUF_BLK_ENTRIES(count)];\n}\n\nvoid vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,\n\tunsigned int error_interrupt_enable,\n\tunsigned int error_interrupt_offset)\n{\n\tvnic_wq_init_start(wq, cq_index, 0, 0,\n\t\terror_interrupt_enable,\n\t\terror_interrupt_offset);\n}\n\nvoid vnic_wq_error_out(struct vnic_wq *wq, unsigned int error)\n{\n\tiowrite32(error, &wq->ctrl->error_status);\n}\n\nunsigned int vnic_wq_error_status(struct vnic_wq *wq)\n{\n\treturn ioread32(&wq->ctrl->error_status);\n}\n\nvoid vnic_wq_enable(struct vnic_wq *wq)\n{\n\tiowrite32(1, &wq->ctrl->enable);\n}\n\nint vnic_wq_disable(struct vnic_wq *wq)\n{\n\tunsigned int wait;\n\n\tiowrite32(0, &wq->ctrl->enable);\n\n\t/* Wait for HW to ACK disable request */\n\tfor (wait = 0; wait < 1000; wait++) {\n\t\tif (!(ioread32(&wq->ctrl->running)))\n\t\t\treturn 0;\n\t\tudelay(10);\n\t}\n\n\tpr_err(\"Failed to disable WQ[%d]\\n\", wq->index);\n\n\treturn -ETIMEDOUT;\n}\n\nvoid vnic_wq_clean(struct vnic_wq *wq,\n\tvoid (*buf_clean)(struct vnic_wq *wq, struct vnic_wq_buf *buf))\n{\n\tstruct vnic_wq_buf *buf;\n\n\tbuf = wq->to_clean;\n\n\twhile (vnic_wq_desc_used(wq) > 0) {\n\n\t\t(*buf_clean)(wq, buf);\n\n\t\tbuf = wq->to_clean = buf->next;\n\t\twq->ring.desc_avail++;\n\t}\n\n\twq->to_use = wq->to_clean = wq->bufs[0];\n\n\tiowrite32(0, &wq->ctrl->fetch_index);\n\tiowrite32(0, &wq->ctrl->posted_index);\n\tiowrite32(0, &wq->ctrl->error_status);\n\n\tvnic_dev_clear_desc_ring(&wq->ring);\n}\n" }, { "path": "drivers/net/enic/base/vnic_wq.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: vnic_wq.h 183023 2014-07-22 23:47:25Z xuywang $\"\n\n#ifndef _VNIC_WQ_H_\n#define _VNIC_WQ_H_\n\n\n#include \"vnic_dev.h\"\n#include \"vnic_cq.h\"\n\n/* Work queue control */\nstruct vnic_wq_ctrl {\n\tu64 ring_base;\t\t\t/* 0x00 */\n\tu32 ring_size;\t\t\t/* 0x08 */\n\tu32 pad0;\n\tu32 posted_index;\t\t/* 0x10 */\n\tu32 pad1;\n\tu32 cq_index;\t\t\t/* 0x18 */\n\tu32 pad2;\n\tu32 enable;\t\t\t/* 0x20 */\n\tu32 pad3;\n\tu32 running;\t\t\t/* 0x28 */\n\tu32 pad4;\n\tu32 fetch_index;\t\t/* 0x30 */\n\tu32 pad5;\n\tu32 dca_value;\t\t\t/* 0x38 */\n\tu32 pad6;\n\tu32 error_interrupt_enable;\t/* 0x40 */\n\tu32 pad7;\n\tu32 error_interrupt_offset;\t/* 0x48 */\n\tu32 pad8;\n\tu32 error_status;\t\t/* 0x50 */\n\tu32 pad9;\n};\n\nstruct vnic_wq_buf {\n\tstruct vnic_wq_buf *next;\n\tdma_addr_t dma_addr;\n\tvoid *os_buf;\n\tunsigned int len;\n\tunsigned int index;\n\tint sop;\n\tvoid *desc;\n\tuint64_t wr_id; /* Cookie */\n\tuint8_t cq_entry; /* Gets completion event from hw */\n\tuint8_t desc_skip_cnt; /* Num descs to occupy */\n\tuint8_t compressed_send; /* Both hdr and payload in one desc */\n};\n\n/* Break the vnic_wq_buf allocations into blocks of 32/64 entries */\n#define VNIC_WQ_BUF_MIN_BLK_ENTRIES 32\n#define VNIC_WQ_BUF_DFLT_BLK_ENTRIES 64\n#define VNIC_WQ_BUF_BLK_ENTRIES(entries) \\\n\t((unsigned int)((entries < VNIC_WQ_BUF_DFLT_BLK_ENTRIES) ? \\\n\tVNIC_WQ_BUF_MIN_BLK_ENTRIES : VNIC_WQ_BUF_DFLT_BLK_ENTRIES))\n#define VNIC_WQ_BUF_BLK_SZ(entries) \\\n\t(VNIC_WQ_BUF_BLK_ENTRIES(entries) * sizeof(struct vnic_wq_buf))\n#define VNIC_WQ_BUF_BLKS_NEEDED(entries) \\\n\tDIV_ROUND_UP(entries, VNIC_WQ_BUF_BLK_ENTRIES(entries))\n#define VNIC_WQ_BUF_BLKS_MAX VNIC_WQ_BUF_BLKS_NEEDED(4096)\n\nstruct vnic_wq {\n\tunsigned int index;\n\tstruct vnic_dev *vdev;\n\tstruct vnic_wq_ctrl __iomem *ctrl; /* memory-mapped */\n\tstruct vnic_dev_ring ring;\n\tstruct vnic_wq_buf *bufs[VNIC_WQ_BUF_BLKS_MAX];\n\tstruct vnic_wq_buf *to_use;\n\tstruct vnic_wq_buf *to_clean;\n\tunsigned int pkts_outstanding;\n\tunsigned int socket_id;\n};\n\nstatic inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)\n{\n\t/* how many does SW own? */\n\treturn wq->ring.desc_avail;\n}\n\nstatic inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)\n{\n\t/* how many does HW own? */\n\treturn wq->ring.desc_count - wq->ring.desc_avail - 1;\n}\n\nstatic inline void *vnic_wq_next_desc(struct vnic_wq *wq)\n{\n\treturn wq->to_use->desc;\n}\n\n#define PI_LOG2_CACHE_LINE_SIZE 5\n#define PI_INDEX_BITS 12\n#define PI_INDEX_MASK ((1U << PI_INDEX_BITS) - 1)\n#define PI_PREFETCH_LEN_MASK ((1U << PI_LOG2_CACHE_LINE_SIZE) - 1)\n#define PI_PREFETCH_LEN_OFF 16\n#define PI_PREFETCH_ADDR_BITS 43\n#define PI_PREFETCH_ADDR_MASK ((1ULL << PI_PREFETCH_ADDR_BITS) - 1)\n#define PI_PREFETCH_ADDR_OFF 21\n\n/** How many cache lines are touched by buffer (addr, len). */\nstatic inline unsigned int num_cache_lines_touched(dma_addr_t addr,\n\t\t\t\t\t\t\tunsigned int len)\n{\n\tconst unsigned long mask = PI_PREFETCH_LEN_MASK;\n\tconst unsigned long laddr = (unsigned long)addr;\n\tunsigned long lines, equiv_len;\n\t/* A. If addr is aligned, our solution is just to round up len to the\n\tnext boundary.\n\n\te.g. addr = 0, len = 48\n\t+--------------------+\n\t|XXXXXXXXXXXXXXXXXXXX| 32-byte cacheline a\n\t+--------------------+\n\t|XXXXXXXXXX | cacheline b\n\t+--------------------+\n\n\tB. If addr is not aligned, however, we may use an extra\n\tcacheline. e.g. addr = 12, len = 22\n\n\t+--------------------+\n\t| XXXXXXXXXXXXX|\n\t+--------------------+\n\t|XX |\n\t+--------------------+\n\n\tOur solution is to make the problem equivalent to case A\n\tabove by adding the empty space in the first cacheline to the length:\n\tunsigned long len;\n\n\t+--------------------+\n\t|eeeeeeeXXXXXXXXXXXXX| \"e\" is empty space, which we add to len\n\t+--------------------+\n\t|XX |\n\t+--------------------+\n\n\t*/\n\tequiv_len = len + (laddr & mask);\n\n\t/* Now we can just round up this len to the next 32-byte boundary. */\n\tlines = (equiv_len + mask) & (~mask);\n\n\t/* Scale bytes -> cachelines. */\n\treturn lines >> PI_LOG2_CACHE_LINE_SIZE;\n}\n\nstatic inline u64 vnic_cached_posted_index(dma_addr_t addr, unsigned int len,\n\t\t\t\t\t\tunsigned int index)\n{\n\tunsigned int num_cache_lines = num_cache_lines_touched(addr, len);\n\t/* Wish we could avoid a branch here. We could have separate\n\t * vnic_wq_post() and vinc_wq_post_inline(), the latter\n\t * only supporting < 1k (2^5 * 2^5) sends, I suppose. This would\n\t * eliminate the if (eop) branch as well.\n\t */\n\tif (num_cache_lines > PI_PREFETCH_LEN_MASK)\n\t\tnum_cache_lines = 0;\n\treturn (index & PI_INDEX_MASK) |\n\t((num_cache_lines & PI_PREFETCH_LEN_MASK) << PI_PREFETCH_LEN_OFF) |\n\t\t(((addr >> PI_LOG2_CACHE_LINE_SIZE) &\n\tPI_PREFETCH_ADDR_MASK) << PI_PREFETCH_ADDR_OFF);\n}\n\nstatic inline void vnic_wq_post(struct vnic_wq *wq,\n\tvoid *os_buf, dma_addr_t dma_addr,\n\tunsigned int len, int sop, int eop,\n\tuint8_t desc_skip_cnt, uint8_t cq_entry,\n\tuint8_t compressed_send, uint64_t wrid)\n{\n\tstruct vnic_wq_buf *buf = wq->to_use;\n\n\tbuf->sop = sop;\n\tbuf->cq_entry = cq_entry;\n\tbuf->compressed_send = compressed_send;\n\tbuf->desc_skip_cnt = desc_skip_cnt;\n\tbuf->os_buf = os_buf;\n\tbuf->dma_addr = dma_addr;\n\tbuf->len = len;\n\tbuf->wr_id = wrid;\n\n\tbuf = buf->next;\n\tif (eop) {\n#ifdef DO_PREFETCH\n\t\tuint64_t wr = vnic_cached_posted_index(dma_addr, len,\n\t\t\t\t\t\t\tbuf->index);\n#endif\n\t\t/* Adding write memory barrier prevents compiler and/or CPU\n\t\t * reordering, thus avoiding descriptor posting before\n\t\t * descriptor is initialized. Otherwise, hardware can read\n\t\t * stale descriptor fields.\n\t\t */\n\t\twmb();\n#ifdef DO_PREFETCH\n\t\t/* Intel chipsets seem to limit the rate of PIOs that we can\n\t\t * push on the bus. Thus, it is very important to do a single\n\t\t * 64 bit write here. With two 32-bit writes, my maximum\n\t\t * pkt/sec rate was cut almost in half. -AJF\n\t\t */\n\t\tiowrite64((uint64_t)wr, &wq->ctrl->posted_index);\n#else\n\t\tiowrite32(buf->index, &wq->ctrl->posted_index);\n#endif\n\t}\n\twq->to_use = buf;\n\n\twq->ring.desc_avail -= desc_skip_cnt;\n}\n\nstatic inline void vnic_wq_service(struct vnic_wq *wq,\n\tstruct cq_desc *cq_desc, u16 completed_index,\n\tvoid (*buf_service)(struct vnic_wq *wq,\n\tstruct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque),\n\tvoid *opaque)\n{\n\tstruct vnic_wq_buf *buf;\n\n\tbuf = wq->to_clean;\n\twhile (1) {\n\n\t\t(*buf_service)(wq, cq_desc, buf, opaque);\n\n\t\twq->ring.desc_avail++;\n\n\t\twq->to_clean = buf->next;\n\n\t\tif (buf->index == completed_index)\n\t\t\tbreak;\n\n\t\tbuf = wq->to_clean;\n\t}\n}\n\nvoid vnic_wq_free(struct vnic_wq *wq);\nint vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,\n\tunsigned int desc_count, unsigned int desc_size);\nvoid vnic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,\n\tunsigned int fetch_index, unsigned int posted_index,\n\tunsigned int error_interrupt_enable,\n\tunsigned int error_interrupt_offset);\nvoid vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,\n\tunsigned int error_interrupt_enable,\n\tunsigned int error_interrupt_offset);\nvoid vnic_wq_error_out(struct vnic_wq *wq, unsigned int error);\nunsigned int vnic_wq_error_status(struct vnic_wq *wq);\nvoid vnic_wq_enable(struct vnic_wq *wq);\nint vnic_wq_disable(struct vnic_wq *wq);\nvoid vnic_wq_clean(struct vnic_wq *wq,\n\tvoid (*buf_clean)(struct vnic_wq *wq, struct vnic_wq_buf *buf));\nint vnic_wq_mem_size(struct vnic_wq *wq, unsigned int desc_count,\n\tunsigned int desc_size);\n\n#endif /* _VNIC_WQ_H_ */\n" }, { "path": "drivers/net/enic/base/wq_enet_desc.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: wq_enet_desc.h 59839 2010-09-27 20:36:31Z roprabhu $\"\n\n#ifndef _WQ_ENET_DESC_H_\n#define _WQ_ENET_DESC_H_\n\n/* Ethernet work queue descriptor: 16B */\nstruct wq_enet_desc {\n\t__le64 address;\n\t__le16 length;\n\t__le16 mss_loopback;\n\t__le16 header_length_flags;\n\t__le16 vlan_tag;\n};\n\n#define WQ_ENET_ADDR_BITS\t\t64\n#define WQ_ENET_LEN_BITS\t\t14\n#define WQ_ENET_LEN_MASK\t\t((1 << WQ_ENET_LEN_BITS) - 1)\n#define WQ_ENET_MSS_BITS\t\t14\n#define WQ_ENET_MSS_MASK\t\t((1 << WQ_ENET_MSS_BITS) - 1)\n#define WQ_ENET_MSS_SHIFT\t\t2\n#define WQ_ENET_LOOPBACK_SHIFT\t\t1\n#define WQ_ENET_HDRLEN_BITS\t\t10\n#define WQ_ENET_HDRLEN_MASK\t\t((1 << WQ_ENET_HDRLEN_BITS) - 1)\n#define WQ_ENET_FLAGS_OM_BITS\t\t2\n#define WQ_ENET_FLAGS_OM_MASK\t\t((1 << WQ_ENET_FLAGS_OM_BITS) - 1)\n#define WQ_ENET_FLAGS_EOP_SHIFT\t\t12\n#define WQ_ENET_FLAGS_CQ_ENTRY_SHIFT\t13\n#define WQ_ENET_FLAGS_FCOE_ENCAP_SHIFT\t14\n#define WQ_ENET_FLAGS_VLAN_TAG_INSERT_SHIFT\t15\n\n#define WQ_ENET_OFFLOAD_MODE_CSUM\t0\n#define WQ_ENET_OFFLOAD_MODE_RESERVED\t1\n#define WQ_ENET_OFFLOAD_MODE_CSUM_L4\t2\n#define WQ_ENET_OFFLOAD_MODE_TSO\t3\n\nstatic inline void wq_enet_desc_enc(struct wq_enet_desc *desc,\n\tu64 address, u16 length, u16 mss, u16 header_length,\n\tu8 offload_mode, u8 eop, u8 cq_entry, u8 fcoe_encap,\n\tu8 vlan_tag_insert, u16 vlan_tag, u8 loopback)\n{\n\tdesc->address = cpu_to_le64(address);\n\tdesc->length = cpu_to_le16(length & WQ_ENET_LEN_MASK);\n\tdesc->mss_loopback = cpu_to_le16((mss & WQ_ENET_MSS_MASK) <<\n\t\tWQ_ENET_MSS_SHIFT | (loopback & 1) << WQ_ENET_LOOPBACK_SHIFT);\n\tdesc->header_length_flags = cpu_to_le16(\n\t\t(header_length & WQ_ENET_HDRLEN_MASK) |\n\t\t(offload_mode & WQ_ENET_FLAGS_OM_MASK) << WQ_ENET_HDRLEN_BITS |\n\t\t(eop & 1) << WQ_ENET_FLAGS_EOP_SHIFT |\n\t\t(cq_entry & 1) << WQ_ENET_FLAGS_CQ_ENTRY_SHIFT |\n\t\t(fcoe_encap & 1) << WQ_ENET_FLAGS_FCOE_ENCAP_SHIFT |\n\t\t(vlan_tag_insert & 1) << WQ_ENET_FLAGS_VLAN_TAG_INSERT_SHIFT);\n\tdesc->vlan_tag = cpu_to_le16(vlan_tag);\n}\n\nstatic inline void wq_enet_desc_dec(struct wq_enet_desc *desc,\n\tu64 *address, u16 *length, u16 *mss, u16 *header_length,\n\tu8 *offload_mode, u8 *eop, u8 *cq_entry, u8 *fcoe_encap,\n\tu8 *vlan_tag_insert, u16 *vlan_tag, u8 *loopback)\n{\n\t*address = le64_to_cpu(desc->address);\n\t*length = le16_to_cpu(desc->length) & WQ_ENET_LEN_MASK;\n\t*mss = (le16_to_cpu(desc->mss_loopback) >> WQ_ENET_MSS_SHIFT) &\n\t\tWQ_ENET_MSS_MASK;\n\t*loopback = (u8)((le16_to_cpu(desc->mss_loopback) >>\n\t\tWQ_ENET_LOOPBACK_SHIFT) & 1);\n\t*header_length = le16_to_cpu(desc->header_length_flags) &\n\t\tWQ_ENET_HDRLEN_MASK;\n\t*offload_mode = (u8)((le16_to_cpu(desc->header_length_flags) >>\n\t\tWQ_ENET_HDRLEN_BITS) & WQ_ENET_FLAGS_OM_MASK);\n\t*eop = (u8)((le16_to_cpu(desc->header_length_flags) >>\n\t\tWQ_ENET_FLAGS_EOP_SHIFT) & 1);\n\t*cq_entry = (u8)((le16_to_cpu(desc->header_length_flags) >>\n\t\tWQ_ENET_FLAGS_CQ_ENTRY_SHIFT) & 1);\n\t*fcoe_encap = (u8)((le16_to_cpu(desc->header_length_flags) >>\n\t\tWQ_ENET_FLAGS_FCOE_ENCAP_SHIFT) & 1);\n\t*vlan_tag_insert = (u8)((le16_to_cpu(desc->header_length_flags) >>\n\t\tWQ_ENET_FLAGS_VLAN_TAG_INSERT_SHIFT) & 1);\n\t*vlan_tag = le16_to_cpu(desc->vlan_tag);\n}\n\n#endif /* _WQ_ENET_DESC_H_ */\n" }, { "path": "drivers/net/enic/enic.h", "content": "/*\n * Copyright 2008-2014 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id$\"\n\n#ifndef _ENIC_H_\n#define _ENIC_H_\n\n#include \"vnic_enet.h\"\n#include \"vnic_dev.h\"\n#include \"vnic_wq.h\"\n#include \"vnic_rq.h\"\n#include \"vnic_cq.h\"\n#include \"vnic_intr.h\"\n#include \"vnic_stats.h\"\n#include \"vnic_nic.h\"\n#include \"vnic_rss.h\"\n#include \"enic_res.h\"\n\n#define DRV_NAME\t\t\"enic_pmd\"\n#define DRV_DESCRIPTION\t\t\"Cisco VIC Ethernet NIC Poll-mode Driver\"\n#define DRV_VERSION\t\t\"1.0.0.5\"\n#define DRV_COPYRIGHT\t\t\"Copyright 2008-2015 Cisco Systems, Inc\"\n\n#define ENIC_WQ_MAX\t\t8\n#define ENIC_RQ_MAX\t\t8\n#define ENIC_CQ_MAX\t\t(ENIC_WQ_MAX + ENIC_RQ_MAX)\n#define ENIC_INTR_MAX\t\t(ENIC_CQ_MAX + 2)\n\n#define VLAN_ETH_HLEN 18\n\n#define ENICPMD_SETTING(enic, f) ((enic->config.flags & VENETF_##f) ? 1 : 0)\n\n#define ENICPMD_BDF_LENGTH 13 /* 0000:00:00.0'\\0' */\n#define PKT_TX_TCP_UDP_CKSUM 0x6000\n#define ENIC_CALC_IP_CKSUM 1\n#define ENIC_CALC_TCP_UDP_CKSUM 2\n#define ENIC_MAX_MTU 9000\n#define ENIC_PAGE_SIZE 4096\n#define PAGE_ROUND_UP(x) \\\n\t((((unsigned long)(x)) + ENIC_PAGE_SIZE-1) & (~(ENIC_PAGE_SIZE-1)))\n\n#define ENICPMD_VFIO_PATH \"/dev/vfio/vfio\"\n/*#define ENIC_DESC_COUNT_MAKE_ODD (x) do{if ((~(x)) & 1) { (x)--; } }while(0)*/\n\n#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */\n#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */\n\n\n#define ENICPMD_FDIR_MAX 64\n\nstruct enic_fdir_node {\n\tstruct rte_eth_fdir_filter filter;\n\tu16 fltr_id;\n\tu16 rq_index;\n};\n\nstruct enic_fdir {\n\tstruct rte_eth_fdir_stats stats;\n\tstruct rte_hash *hash;\n\tstruct enic_fdir_node *nodes[ENICPMD_FDIR_MAX];\n};\n\n/* Per-instance private data structure */\nstruct enic {\n\tstruct enic *next;\n\tstruct rte_pci_device *pdev;\n\tstruct vnic_enet_config config;\n\tstruct vnic_dev_bar bar0;\n\tstruct vnic_dev *vdev;\n\n\tunsigned int port_id;\n\tstruct rte_eth_dev *rte_dev;\n\tstruct enic_fdir fdir;\n\tchar bdf_name[ENICPMD_BDF_LENGTH];\n\tint dev_fd;\n\tint iommu_group_fd;\n\tint iommu_groupid;\n\tint eventfd;\n\tuint8_t mac_addr[ETH_ALEN];\n\tpthread_t err_intr_thread;\n\tint promisc;\n\tint allmulti;\n\tu8 ig_vlan_strip_en;\n\tint link_status;\n\tu8 hw_ip_checksum;\n\n\tunsigned int flags;\n\tunsigned int priv_flags;\n\n\t/* work queue */\n\tstruct vnic_wq wq[ENIC_WQ_MAX];\n\tunsigned int wq_count;\n\n\t/* receive queue */\n\tstruct vnic_rq rq[ENIC_RQ_MAX];\n\tunsigned int rq_count;\n\n\t/* completion queue */\n\tstruct vnic_cq cq[ENIC_CQ_MAX];\n\tunsigned int cq_count;\n\n\t/* interrupt resource */\n\tstruct vnic_intr intr;\n\tunsigned int intr_count;\n};\n\nstatic inline unsigned int enic_cq_rq(__rte_unused struct enic *enic, unsigned int rq)\n{\n\treturn rq;\n}\n\nstatic inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq)\n{\n\treturn enic->rq_count + wq;\n}\n\nstatic inline unsigned int enic_msix_err_intr(__rte_unused struct enic *enic)\n{\n\treturn 0;\n}\n\nstatic inline struct enic *pmd_priv(struct rte_eth_dev *eth_dev)\n{\n\treturn (struct enic *)eth_dev->data->dev_private;\n}\n\nextern void enic_fdir_stats_get(struct enic *enic,\n\tstruct rte_eth_fdir_stats *stats);\nextern int enic_fdir_add_fltr(struct enic *enic,\n\tstruct rte_eth_fdir_filter *params);\nextern int enic_fdir_del_fltr(struct enic *enic,\n\tstruct rte_eth_fdir_filter *params);\nextern void enic_free_wq(void *txq);\nextern int enic_alloc_intr_resources(struct enic *enic);\nextern int enic_setup_finish(struct enic *enic);\nextern int enic_alloc_wq(struct enic *enic, uint16_t queue_idx,\n\tunsigned int socket_id, uint16_t nb_desc);\nextern void enic_start_wq(struct enic *enic, uint16_t queue_idx);\nextern int enic_stop_wq(struct enic *enic, uint16_t queue_idx);\nextern void enic_start_rq(struct enic *enic, uint16_t queue_idx);\nextern int enic_stop_rq(struct enic *enic, uint16_t queue_idx);\nextern void enic_free_rq(void *rxq);\nextern int enic_alloc_rq(struct enic *enic, uint16_t queue_idx,\n\tunsigned int socket_id, struct rte_mempool *mp,\n\tuint16_t nb_desc);\nextern int enic_set_rss_nic_cfg(struct enic *enic);\nextern int enic_set_vnic_res(struct enic *enic);\nextern void enic_set_hdr_split_size(struct enic *enic, u16 split_hdr_size);\nextern int enic_enable(struct enic *enic);\nextern int enic_disable(struct enic *enic);\nextern void enic_remove(struct enic *enic);\nextern int enic_get_link_status(struct enic *enic);\nextern void enic_dev_stats_get(struct enic *enic,\n\tstruct rte_eth_stats *r_stats);\nextern void enic_dev_stats_clear(struct enic *enic);\nextern void enic_add_packet_filter(struct enic *enic);\nextern void enic_set_mac_address(struct enic *enic, uint8_t *mac_addr);\nextern void enic_del_mac_address(struct enic *enic);\nextern unsigned int enic_cleanup_wq(struct enic *enic, struct vnic_wq *wq);\nextern int enic_send_pkt(struct enic *enic, struct vnic_wq *wq,\n\tstruct rte_mbuf *tx_pkt, unsigned short len,\n\tuint8_t sop, uint8_t eop,\n\tuint16_t ol_flags, uint16_t vlan_tag);\nextern int enic_poll(struct vnic_rq *rq, struct rte_mbuf **rx_pkts,\n\tunsigned int budget, unsigned int *work_done);\nextern int enic_probe(struct enic *enic);\nextern int enic_clsf_init(struct enic *enic);\nextern void enic_clsf_destroy(struct enic *enic);\n#endif /* _ENIC_H_ */\n" }, { "path": "drivers/net/enic/enic_clsf.c", "content": "/*\n * Copyright 2008-2014 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id$\"\n\n#include \n\n#include \n#include \n#include \n#include \n\n#include \"enic_compat.h\"\n#include \"enic.h\"\n#include \"wq_enet_desc.h\"\n#include \"rq_enet_desc.h\"\n#include \"cq_enet_desc.h\"\n#include \"vnic_enet.h\"\n#include \"vnic_dev.h\"\n#include \"vnic_wq.h\"\n#include \"vnic_rq.h\"\n#include \"vnic_cq.h\"\n#include \"vnic_intr.h\"\n#include \"vnic_nic.h\"\n\n#ifdef RTE_MACHINE_CPUFLAG_SSE4_2\n#include \n#define DEFAULT_HASH_FUNC rte_hash_crc\n#else\n#include \n#define DEFAULT_HASH_FUNC rte_jhash\n#endif\n\n#define SOCKET_0 0\n#define ENICPMD_CLSF_HASH_ENTRIES ENICPMD_FDIR_MAX\n\nvoid enic_fdir_stats_get(struct enic *enic, struct rte_eth_fdir_stats *stats)\n{\n\t*stats = enic->fdir.stats;\n}\n\nint enic_fdir_del_fltr(struct enic *enic, struct rte_eth_fdir_filter *params)\n{\n\tint32_t pos;\n\tstruct enic_fdir_node *key;\n\t/* See if the key is in the table */\n\tpos = rte_hash_del_key(enic->fdir.hash, params);\n\tswitch (pos) {\n\tcase -EINVAL:\n\tcase -ENOENT:\n\t\tenic->fdir.stats.f_remove++;\n\t\treturn -EINVAL;\n\tdefault:\n\t\t/* The entry is present in the table */\n\t\tkey = enic->fdir.nodes[pos];\n\n\t\t/* Delete the filter */\n\t\tvnic_dev_classifier(enic->vdev, CLSF_DEL,\n\t\t\t&key->fltr_id, NULL);\n\t\trte_free(key);\n\t\tenic->fdir.nodes[pos] = NULL;\n\t\tenic->fdir.stats.free++;\n\t\tenic->fdir.stats.remove++;\n\t\tbreak;\n\t}\n\treturn 0;\n}\n\nint enic_fdir_add_fltr(struct enic *enic, struct rte_eth_fdir_filter *params)\n{\n\tstruct enic_fdir_node *key;\n\tstruct filter fltr = {0};\n\tint32_t pos;\n\tu8 do_free = 0;\n\tu16 old_fltr_id = 0;\n\tu32 flowtype_supported;\n\tu16 flex_bytes;\n\tu16 queue;\n\n\tflowtype_supported = (\n\t\t(RTE_ETH_FLOW_NONFRAG_IPV4_TCP == params->input.flow_type) ||\n\t\t(RTE_ETH_FLOW_NONFRAG_IPV4_UDP == params->input.flow_type));\n\n\tflex_bytes = ((params->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |\n\t\t(params->input.flow_ext.flexbytes[0] & 0xFF));\n\n\tif (!enic->fdir.hash ||\n\t\t(params->input.flow_ext.vlan_tci & 0xFFF) ||\n\t\t!flowtype_supported || flex_bytes ||\n\t\tparams->action.behavior /* drop */) {\n\t\tenic->fdir.stats.f_add++;\n\t\treturn -ENOTSUP;\n\t}\n\n\tqueue = params->action.rx_queue;\n\t/* See if the key is already there in the table */\n\tpos = rte_hash_del_key(enic->fdir.hash, params);\n\tswitch (pos) {\n\tcase -EINVAL:\n\t\tenic->fdir.stats.f_add++;\n\t\treturn -EINVAL;\n\tcase -ENOENT:\n\t\t/* Add a new classifier entry */\n\t\tif (!enic->fdir.stats.free) {\n\t\t\tenic->fdir.stats.f_add++;\n\t\t\treturn -ENOSPC;\n\t\t}\n\t\tkey = rte_zmalloc(\"enic_fdir_node\",\n\t\t\t\t sizeof(struct enic_fdir_node), 0);\n\t\tif (!key) {\n\t\t\tenic->fdir.stats.f_add++;\n\t\t\treturn -ENOMEM;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\t/* The entry is already present in the table.\n\t\t * Check if there is a change in queue\n\t\t */\n\t\tkey = enic->fdir.nodes[pos];\n\t\tenic->fdir.nodes[pos] = NULL;\n\t\tif (unlikely(key->rq_index == queue)) {\n\t\t\t/* Nothing to be done */\n\t\t\tpos = rte_hash_add_key(enic->fdir.hash, params);\n\t\t\tenic->fdir.nodes[pos] = key;\n\t\t\tenic->fdir.stats.f_add++;\n\t\t\tdev_warning(enic,\n\t\t\t\t\"FDIR rule is already present\\n\");\n\t\t\treturn 0;\n\t\t}\n\n\t\tif (likely(enic->fdir.stats.free)) {\n\t\t\t/* Add the filter and then delete the old one.\n\t\t\t * This is to avoid packets from going into the\n\t\t\t * default queue during the window between\n\t\t\t * delete and add\n\t\t\t */\n\t\t\tdo_free = 1;\n\t\t\told_fltr_id = key->fltr_id;\n\t\t} else {\n\t\t\t/* No free slots in the classifier.\n\t\t\t * Delete the filter and add the modified one later\n\t\t\t */\n\t\t\tvnic_dev_classifier(enic->vdev, CLSF_DEL,\n\t\t\t\t&key->fltr_id, NULL);\n\t\t\tenic->fdir.stats.free++;\n\t\t}\n\n\t\tbreak;\n\t}\n\n\tkey->filter = *params;\n\tkey->rq_index = queue;\n\n\tfltr.type = FILTER_IPV4_5TUPLE;\n\tfltr.u.ipv4.src_addr = rte_be_to_cpu_32(\n\t\tparams->input.flow.ip4_flow.src_ip);\n\tfltr.u.ipv4.dst_addr = rte_be_to_cpu_32(\n\t\tparams->input.flow.ip4_flow.dst_ip);\n\tfltr.u.ipv4.src_port = rte_be_to_cpu_16(\n\t\tparams->input.flow.udp4_flow.src_port);\n\tfltr.u.ipv4.dst_port = rte_be_to_cpu_16(\n\t\tparams->input.flow.udp4_flow.dst_port);\n\n\tif (RTE_ETH_FLOW_NONFRAG_IPV4_TCP == params->input.flow_type)\n\t\tfltr.u.ipv4.protocol = PROTO_TCP;\n\telse\n\t\tfltr.u.ipv4.protocol = PROTO_UDP;\n\n\tfltr.u.ipv4.flags = FILTER_FIELDS_IPV4_5TUPLE;\n\n\tif (!vnic_dev_classifier(enic->vdev, CLSF_ADD, &queue, &fltr)) {\n\t\tkey->fltr_id = queue;\n\t} else {\n\t\tdev_err(enic, \"Add classifier entry failed\\n\");\n\t\tenic->fdir.stats.f_add++;\n\t\trte_free(key);\n\t\treturn -1;\n\t}\n\n\tif (do_free)\n\t\tvnic_dev_classifier(enic->vdev, CLSF_DEL, &old_fltr_id, NULL);\n\telse{\n\t\tenic->fdir.stats.free--;\n\t\tenic->fdir.stats.add++;\n\t}\n\n\tpos = rte_hash_add_key(enic->fdir.hash, (void *)key);\n\tenic->fdir.nodes[pos] = key;\n\treturn 0;\n}\n\nvoid enic_clsf_destroy(struct enic *enic)\n{\n\tu32 index;\n\tstruct enic_fdir_node *key;\n\t/* delete classifier entries */\n\tfor (index = 0; index < ENICPMD_FDIR_MAX; index++) {\n\t\tkey = enic->fdir.nodes[index];\n\t\tif (key) {\n\t\t\tvnic_dev_classifier(enic->vdev, CLSF_DEL,\n\t\t\t\t&key->fltr_id, NULL);\n\t\t\trte_free(key);\n\t\t}\n\t}\n\n\tif (enic->fdir.hash) {\n\t\trte_hash_free(enic->fdir.hash);\n\t\tenic->fdir.hash = NULL;\n\t}\n}\n\nint enic_clsf_init(struct enic *enic)\n{\n\tstruct rte_hash_parameters hash_params = {\n\t\t.name = \"enicpmd_clsf_hash\",\n\t\t.entries = ENICPMD_CLSF_HASH_ENTRIES,\n\t\t.key_len = RTE_HASH_KEY_LENGTH_MAX,\n\t\t.hash_func = DEFAULT_HASH_FUNC,\n\t\t.hash_func_init_val = 0,\n\t\t.socket_id = SOCKET_0,\n\t};\n\n\tenic->fdir.hash = rte_hash_create(&hash_params);\n\tmemset(&enic->fdir.stats, 0, sizeof(enic->fdir.stats));\n\tenic->fdir.stats.free = ENICPMD_FDIR_MAX;\n\treturn (NULL == enic->fdir.hash);\n}\n" }, { "path": "drivers/net/enic/enic_compat.h", "content": "/*\n * Copyright 2008-2014 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id$\"\n\n#ifndef _ENIC_COMPAT_H_\n#define _ENIC_COMPAT_H_\n\n#include \n#include \n\n#include \n#include \n#include \n\n#define ENIC_PAGE_ALIGN 4096UL\n#define ENIC_ALIGN ENIC_PAGE_ALIGN\n#define NAME_MAX 255\n#define ETH_ALEN 6\n\n#define __iomem\n\n#define rmb() rte_rmb() /* dpdk rte provided rmb */\n#define wmb() rte_wmb() /* dpdk rte provided wmb */\n\n#define le16_to_cpu\n#define le32_to_cpu\n#define le64_to_cpu\n#define cpu_to_le16\n#define cpu_to_le32\n#define cpu_to_le64\n\n#ifndef offsetof\n#define offsetof(t, m) ((size_t) &((t *)0)->m)\n#endif\n\n#define pr_err(y, args...) dev_err(0, y, ##args)\n#define pr_warn(y, args...) dev_warning(0, y, ##args)\n#define BUG() pr_err(\"BUG at %s:%d\", __func__, __LINE__)\n\n#define VNIC_ALIGN(x, a) __ALIGN_MASK(x, (typeof(x))(a)-1)\n#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))\n#define udelay usleep\n#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n\n#define kzalloc(size, flags) calloc(1, size)\n#define kfree(x) free(x)\n\n#define dev_printk(level, fmt, args...)\t\\\n\tRTE_LOG(level, PMD, \"rte_enic_pmd: \" fmt, ## args)\n\n#define dev_err(x, args...) dev_printk(ERR, args)\n#define dev_info(x, args...) dev_printk(INFO, args)\n#define dev_warning(x, args...) dev_printk(WARNING, args)\n#define dev_debug(x, args...) dev_printk(DEBUG, args)\n\n#define __le16 u16\n#define __le32 u32\n#define __le64 u64\n\ntypedef\t\tunsigned char u8;\ntypedef\t\tunsigned short u16;\ntypedef\t\tunsigned int u32;\ntypedef unsigned long long u64;\ntypedef unsigned long long dma_addr_t;\n\nstatic inline uint32_t ioread32(volatile void *addr)\n{\n\treturn *(volatile uint32_t *)addr;\n}\n\nstatic inline uint16_t ioread16(volatile void *addr)\n{\n\treturn *(volatile uint16_t *)addr;\n}\n\nstatic inline uint8_t ioread8(volatile void *addr)\n{\n\treturn *(volatile uint8_t *)addr;\n}\n\nstatic inline void iowrite32(uint32_t val, volatile void *addr)\n{\n\t*(volatile uint32_t *)addr = val;\n}\n\nstatic inline void iowrite16(uint16_t val, volatile void *addr)\n{\n\t*(volatile uint16_t *)addr = val;\n}\n\nstatic inline void iowrite8(uint8_t val, volatile void *addr)\n{\n\t*(volatile uint8_t *)addr = val;\n}\n\nstatic inline unsigned int readl(volatile void __iomem *addr)\n{\n\treturn *(volatile unsigned int *)addr;\n}\n\nstatic inline void writel(unsigned int val, volatile void __iomem *addr)\n{\n\t*(volatile unsigned int *)addr = val;\n}\n\n#define min_t(type, x, y) ({ \\\n\ttype __min1 = (x); \\\n\ttype __min2 = (y); \\\n\t__min1 < __min2 ? __min1 : __min2; })\n\n#define max_t(type, x, y) ({ \\\n\ttype __max1 = (x); \\\n\ttype __max2 = (y); \\\n\t__max1 > __max2 ? __max1 : __max2; })\n\n#endif /* _ENIC_COMPAT_H_ */\n" }, { "path": "drivers/net/enic/enic_ethdev.c", "content": "/*\n * Copyright 2008-2014 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id$\"\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"vnic_intr.h\"\n#include \"vnic_cq.h\"\n#include \"vnic_wq.h\"\n#include \"vnic_rq.h\"\n#include \"vnic_enet.h\"\n#include \"enic.h\"\n\n#ifdef RTE_LIBRTE_ENIC_DEBUG\n#define ENICPMD_FUNC_TRACE() \\\n\tRTE_LOG(DEBUG, PMD, \"ENICPMD trace: %s\\n\", __func__)\n#else\n#define ENICPMD_FUNC_TRACE() (void)0\n#endif\n\n/*\n * The set of PCI devices this driver supports\n */\nstatic const struct rte_pci_id pci_id_enic_map[] = {\n#define RTE_PCI_DEV_ID_DECL_ENIC(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#ifndef PCI_VENDOR_ID_CISCO\n#define PCI_VENDOR_ID_CISCO\t0x1137\n#endif\n#include \"rte_pci_dev_ids.h\"\nRTE_PCI_DEV_ID_DECL_ENIC(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET)\nRTE_PCI_DEV_ID_DECL_ENIC(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)\n{.vendor_id = 0, /* Sentinal */},\n};\n\nstatic int\nenicpmd_fdir_ctrl_func(struct rte_eth_dev *eth_dev,\n\t\t\tenum rte_filter_op filter_op, void *arg)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\tint ret = 0;\n\n\tENICPMD_FUNC_TRACE();\n\tif (filter_op == RTE_ETH_FILTER_NOP)\n\t\treturn 0;\n\n\tif (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)\n\t\treturn -EINVAL;\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_ADD:\n\tcase RTE_ETH_FILTER_UPDATE:\n\t\tret = enic_fdir_add_fltr(enic,\n\t\t\t(struct rte_eth_fdir_filter *)arg);\n\t\tbreak;\n\n\tcase RTE_ETH_FILTER_DELETE:\n\t\tret = enic_fdir_del_fltr(enic,\n\t\t\t(struct rte_eth_fdir_filter *)arg);\n\t\tbreak;\n\n\tcase RTE_ETH_FILTER_STATS:\n\t\tenic_fdir_stats_get(enic, (struct rte_eth_fdir_stats *)arg);\n\t\tbreak;\n\n\tcase RTE_ETH_FILTER_FLUSH:\n\tcase RTE_ETH_FILTER_INFO:\n\t\tdev_warning(enic, \"unsupported operation %u\", filter_op);\n\t\tret = -ENOTSUP;\n\t\tbreak;\n\tdefault:\n\t\tdev_err(enic, \"unknown operation %u\", filter_op);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\nstatic int\nenicpmd_dev_filter_ctrl(struct rte_eth_dev *dev,\n\t\t enum rte_filter_type filter_type,\n\t\t enum rte_filter_op filter_op,\n\t\t void *arg)\n{\n\tint ret = -EINVAL;\n\n\tif (RTE_ETH_FILTER_FDIR == filter_type)\n\t\tret = enicpmd_fdir_ctrl_func(dev, filter_op, arg);\n\telse\n\t\tdev_warning(enic, \"Filter type (%d) not supported\",\n\t\t\tfilter_type);\n\n\treturn ret;\n}\n\nstatic void enicpmd_dev_tx_queue_release(void *txq)\n{\n\tENICPMD_FUNC_TRACE();\n\tenic_free_wq(txq);\n}\n\nstatic int enicpmd_dev_setup_intr(struct enic *enic)\n{\n\tint ret;\n\tunsigned int index;\n\n\tENICPMD_FUNC_TRACE();\n\n\t/* Are we done with the init of all the queues? */\n\tfor (index = 0; index < enic->cq_count; index++) {\n\t\tif (!enic->cq[index].ctrl)\n\t\t\tbreak;\n\t}\n\n\tif (enic->cq_count != index)\n\t\treturn 0;\n\n\tret = enic_alloc_intr_resources(enic);\n\tif (ret) {\n\t\tdev_err(enic, \"alloc intr failed\\n\");\n\t\treturn ret;\n\t}\n\tenic_init_vnic_resources(enic);\n\n\tret = enic_setup_finish(enic);\n\tif (ret)\n\t\tdev_err(enic, \"setup could not be finished\\n\");\n\n\treturn ret;\n}\n\nstatic int enicpmd_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,\n\tuint16_t queue_idx,\n\tuint16_t nb_desc,\n\tunsigned int socket_id,\n\t__rte_unused const struct rte_eth_txconf *tx_conf)\n{\n\tint ret;\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\teth_dev->data->tx_queues[queue_idx] = (void *)&enic->wq[queue_idx];\n\n\tret = enic_alloc_wq(enic, queue_idx, socket_id, nb_desc);\n\tif (ret) {\n\t\tdev_err(enic, \"error in allocating wq\\n\");\n\t\treturn ret;\n\t}\n\n\treturn enicpmd_dev_setup_intr(enic);\n}\n\nstatic int enicpmd_dev_tx_queue_start(struct rte_eth_dev *eth_dev,\n\tuint16_t queue_idx)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\n\tenic_start_wq(enic, queue_idx);\n\n\treturn 0;\n}\n\nstatic int enicpmd_dev_tx_queue_stop(struct rte_eth_dev *eth_dev,\n\tuint16_t queue_idx)\n{\n\tint ret;\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\n\tret = enic_stop_wq(enic, queue_idx);\n\tif (ret)\n\t\tdev_err(enic, \"error in stopping wq %d\\n\", queue_idx);\n\n\treturn ret;\n}\n\nstatic int enicpmd_dev_rx_queue_start(struct rte_eth_dev *eth_dev,\n\tuint16_t queue_idx)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\n\tenic_start_rq(enic, queue_idx);\n\n\treturn 0;\n}\n\nstatic int enicpmd_dev_rx_queue_stop(struct rte_eth_dev *eth_dev,\n\tuint16_t queue_idx)\n{\n\tint ret;\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\n\tret = enic_stop_rq(enic, queue_idx);\n\tif (ret)\n\t\tdev_err(enic, \"error in stopping rq %d\\n\", queue_idx);\n\n\treturn ret;\n}\n\nstatic void enicpmd_dev_rx_queue_release(void *rxq)\n{\n\tENICPMD_FUNC_TRACE();\n\tenic_free_rq(rxq);\n}\n\nstatic int enicpmd_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,\n\tuint16_t queue_idx,\n\tuint16_t nb_desc,\n\tunsigned int socket_id,\n\t__rte_unused const struct rte_eth_rxconf *rx_conf,\n\tstruct rte_mempool *mp)\n{\n\tint ret;\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\teth_dev->data->rx_queues[queue_idx] = (void *)&enic->rq[queue_idx];\n\n\tret = enic_alloc_rq(enic, queue_idx, socket_id, mp, nb_desc);\n\tif (ret) {\n\t\tdev_err(enic, \"error in allocating rq\\n\");\n\t\treturn ret;\n\t}\n\n\treturn enicpmd_dev_setup_intr(enic);\n}\n\nstatic int enicpmd_vlan_filter_set(struct rte_eth_dev *eth_dev,\n\tuint16_t vlan_id, int on)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tif (on)\n\t\tenic_add_vlan(enic, vlan_id);\n\telse\n\t\tenic_del_vlan(enic, vlan_id);\n\treturn 0;\n}\n\nstatic void enicpmd_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\n\tif (mask & ETH_VLAN_STRIP_MASK) {\n\t\tif (eth_dev->data->dev_conf.rxmode.hw_vlan_strip)\n\t\t\tenic->ig_vlan_strip_en = 1;\n\t\telse\n\t\t\tenic->ig_vlan_strip_en = 0;\n\t}\n\tenic_set_rss_nic_cfg(enic);\n\n\n\tif (mask & ETH_VLAN_FILTER_MASK) {\n\t\tdev_warning(enic,\n\t\t\t\"Configuration of VLAN filter is not supported\\n\");\n\t}\n\n\tif (mask & ETH_VLAN_EXTEND_MASK) {\n\t\tdev_warning(enic,\n\t\t\t\"Configuration of extended VLAN is not supported\\n\");\n\t}\n}\n\nstatic int enicpmd_dev_configure(struct rte_eth_dev *eth_dev)\n{\n\tint ret;\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tret = enic_set_vnic_res(enic);\n\tif (ret) {\n\t\tdev_err(enic, \"Set vNIC resource num failed, aborting\\n\");\n\t\treturn ret;\n\t}\n\n\tif (eth_dev->data->dev_conf.rxmode.split_hdr_size &&\n\t\teth_dev->data->dev_conf.rxmode.header_split) {\n\t\t/* Enable header-data-split */\n\t\tenic_set_hdr_split_size(enic,\n\t\t\teth_dev->data->dev_conf.rxmode.split_hdr_size);\n\t}\n\n\tenic->hw_ip_checksum = eth_dev->data->dev_conf.rxmode.hw_ip_checksum;\n\treturn 0;\n}\n\n/* Start the device.\n * It returns 0 on success.\n */\nstatic int enicpmd_dev_start(struct rte_eth_dev *eth_dev)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\treturn enic_enable(enic);\n}\n\n/*\n * Stop device: disable rx and tx functions to allow for reconfiguring.\n */\nstatic void enicpmd_dev_stop(struct rte_eth_dev *eth_dev)\n{\n\tstruct rte_eth_link link;\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tenic_disable(enic);\n\tmemset(&link, 0, sizeof(link));\n\trte_atomic64_cmpset((uint64_t *)ð_dev->data->dev_link,\n\t\t*(uint64_t *)ð_dev->data->dev_link,\n\t\t*(uint64_t *)&link);\n}\n\n/*\n * Stop device.\n */\nstatic void enicpmd_dev_close(struct rte_eth_dev *eth_dev)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tenic_remove(enic);\n}\n\nstatic int enicpmd_dev_link_update(struct rte_eth_dev *eth_dev,\n\t__rte_unused int wait_to_complete)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\tint ret;\n\tint link_status = 0;\n\n\tENICPMD_FUNC_TRACE();\n\tlink_status = enic_get_link_status(enic);\n\tret = (link_status == enic->link_status);\n\tenic->link_status = link_status;\n\teth_dev->data->dev_link.link_status = link_status;\n\teth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;\n\teth_dev->data->dev_link.link_speed = vnic_dev_port_speed(enic->vdev);\n\treturn ret;\n}\n\nstatic void enicpmd_dev_stats_get(struct rte_eth_dev *eth_dev,\n\tstruct rte_eth_stats *stats)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tenic_dev_stats_get(enic, stats);\n}\n\nstatic void enicpmd_dev_stats_reset(struct rte_eth_dev *eth_dev)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tenic_dev_stats_clear(enic);\n}\n\nstatic void enicpmd_dev_info_get(struct rte_eth_dev *eth_dev,\n\tstruct rte_eth_dev_info *device_info)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tdevice_info->max_rx_queues = enic->rq_count;\n\tdevice_info->max_tx_queues = enic->wq_count;\n\tdevice_info->min_rx_bufsize = ENIC_MIN_MTU;\n\tdevice_info->max_rx_pktlen = enic->config.mtu;\n\tdevice_info->max_mac_addrs = 1;\n\tdevice_info->rx_offload_capa =\n\t\tDEV_RX_OFFLOAD_VLAN_STRIP |\n\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n\t\tDEV_RX_OFFLOAD_TCP_CKSUM;\n\tdevice_info->tx_offload_capa =\n\t\tDEV_TX_OFFLOAD_VLAN_INSERT |\n\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n\t\tDEV_TX_OFFLOAD_TCP_CKSUM;\n}\n\nstatic void enicpmd_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tenic->promisc = 1;\n\tenic_add_packet_filter(enic);\n}\n\nstatic void enicpmd_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tenic->promisc = 0;\n\tenic_add_packet_filter(enic);\n}\n\nstatic void enicpmd_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tenic->allmulti = 1;\n\tenic_add_packet_filter(enic);\n}\n\nstatic void enicpmd_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tenic->allmulti = 0;\n\tenic_add_packet_filter(enic);\n}\n\nstatic void enicpmd_add_mac_addr(struct rte_eth_dev *eth_dev,\n\tstruct ether_addr *mac_addr,\n\t__rte_unused uint32_t index, __rte_unused uint32_t pool)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tenic_set_mac_address(enic, mac_addr->addr_bytes);\n}\n\nstatic void enicpmd_remove_mac_addr(struct rte_eth_dev *eth_dev, __rte_unused uint32_t index)\n{\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\tenic_del_mac_address(enic);\n}\n\n\nstatic uint16_t enicpmd_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\tuint16_t nb_pkts)\n{\n\tunsigned int index;\n\tunsigned int frags;\n\tunsigned int pkt_len;\n\tunsigned int seg_len;\n\tunsigned int inc_len;\n\tunsigned int nb_segs;\n\tstruct rte_mbuf *tx_pkt;\n\tstruct vnic_wq *wq = (struct vnic_wq *)tx_queue;\n\tstruct enic *enic = vnic_dev_priv(wq->vdev);\n\tunsigned short vlan_id;\n\tunsigned short ol_flags;\n\n\tfor (index = 0; index < nb_pkts; index++) {\n\t\ttx_pkt = *tx_pkts++;\n\t\tinc_len = 0;\n\t\tnb_segs = tx_pkt->nb_segs;\n\t\tif (nb_segs > vnic_wq_desc_avail(wq)) {\n\t\t\t/* wq cleanup and try again */\n\t\t\tif (!enic_cleanup_wq(enic, wq) ||\n\t\t\t\t(nb_segs > vnic_wq_desc_avail(wq)))\n\t\t\t\treturn index;\n\t\t}\n\t\tpkt_len = tx_pkt->pkt_len;\n\t\tvlan_id = tx_pkt->vlan_tci;\n\t\tol_flags = tx_pkt->ol_flags;\n\t\tfor (frags = 0; inc_len < pkt_len; frags++) {\n\t\t\tif (!tx_pkt)\n\t\t\t\tbreak;\n\t\t\tseg_len = tx_pkt->data_len;\n\t\t\tinc_len += seg_len;\n\t\t\tif (enic_send_pkt(enic, wq, tx_pkt,\n\t\t\t\t (unsigned short)seg_len, !frags,\n\t\t\t\t (pkt_len == inc_len), ol_flags, vlan_id)) {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\ttx_pkt = tx_pkt->next;\n\t\t}\n\t}\n\n\tenic_cleanup_wq(enic, wq);\n\treturn index;\n}\n\nstatic uint16_t enicpmd_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\tuint16_t nb_pkts)\n{\n\tstruct vnic_rq *rq = (struct vnic_rq *)rx_queue;\n\tunsigned int work_done;\n\n\tif (enic_poll(rq, rx_pkts, (unsigned int)nb_pkts, &work_done))\n\t\tdev_err(enic, \"error in enicpmd poll\\n\");\n\n\treturn work_done;\n}\n\nstatic const struct eth_dev_ops enicpmd_eth_dev_ops = {\n\t.dev_configure = enicpmd_dev_configure,\n\t.dev_start = enicpmd_dev_start,\n\t.dev_stop = enicpmd_dev_stop,\n\t.dev_set_link_up = NULL,\n\t.dev_set_link_down = NULL,\n\t.dev_close = enicpmd_dev_close,\n\t.promiscuous_enable = enicpmd_dev_promiscuous_enable,\n\t.promiscuous_disable = enicpmd_dev_promiscuous_disable,\n\t.allmulticast_enable = enicpmd_dev_allmulticast_enable,\n\t.allmulticast_disable = enicpmd_dev_allmulticast_disable,\n\t.link_update = enicpmd_dev_link_update,\n\t.stats_get = enicpmd_dev_stats_get,\n\t.stats_reset = enicpmd_dev_stats_reset,\n\t.queue_stats_mapping_set = NULL,\n\t.dev_infos_get = enicpmd_dev_info_get,\n\t.mtu_set = NULL,\n\t.vlan_filter_set = enicpmd_vlan_filter_set,\n\t.vlan_tpid_set = NULL,\n\t.vlan_offload_set = enicpmd_vlan_offload_set,\n\t.vlan_strip_queue_set = NULL,\n\t.rx_queue_start = enicpmd_dev_rx_queue_start,\n\t.rx_queue_stop = enicpmd_dev_rx_queue_stop,\n\t.tx_queue_start = enicpmd_dev_tx_queue_start,\n\t.tx_queue_stop = enicpmd_dev_tx_queue_stop,\n\t.rx_queue_setup = enicpmd_dev_rx_queue_setup,\n\t.rx_queue_release = enicpmd_dev_rx_queue_release,\n\t.rx_queue_count = NULL,\n\t.rx_descriptor_done = NULL,\n\t.tx_queue_setup = enicpmd_dev_tx_queue_setup,\n\t.tx_queue_release = enicpmd_dev_tx_queue_release,\n\t.dev_led_on = NULL,\n\t.dev_led_off = NULL,\n\t.flow_ctrl_get = NULL,\n\t.flow_ctrl_set = NULL,\n\t.priority_flow_ctrl_set = NULL,\n\t.mac_addr_add = enicpmd_add_mac_addr,\n\t.mac_addr_remove = enicpmd_remove_mac_addr,\n\t.fdir_set_masks = NULL,\n\t.filter_ctrl = enicpmd_dev_filter_ctrl,\n};\n\nstruct enic *enicpmd_list_head = NULL;\n/* Initialize the driver\n * It returns 0 on success.\n */\nstatic int eth_enicpmd_dev_init(struct rte_eth_dev *eth_dev)\n{\n\tstruct rte_pci_device *pdev;\n\tstruct rte_pci_addr *addr;\n\tstruct enic *enic = pmd_priv(eth_dev);\n\n\tENICPMD_FUNC_TRACE();\n\n\tenic->port_id = eth_dev->data->port_id;\n\tenic->rte_dev = eth_dev;\n\teth_dev->dev_ops = &enicpmd_eth_dev_ops;\n\teth_dev->rx_pkt_burst = &enicpmd_recv_pkts;\n\teth_dev->tx_pkt_burst = &enicpmd_xmit_pkts;\n\n\tpdev = eth_dev->pci_dev;\n\tenic->pdev = pdev;\n\taddr = &pdev->addr;\n\n\tsnprintf(enic->bdf_name, ENICPMD_BDF_LENGTH, \"%04x:%02x:%02x.%x\",\n\t\taddr->domain, addr->bus, addr->devid, addr->function);\n\n\treturn enic_probe(enic);\n}\n\nstatic struct eth_driver rte_enic_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_enic_pmd\",\n\t\t.id_table = pci_id_enic_map,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n\t},\n\t.eth_dev_init = eth_enicpmd_dev_init,\n\t.dev_private_size = sizeof(struct enic),\n};\n\n/* Driver initialization routine.\n * Invoked once at EAL init time.\n * Register as the [Poll Mode] Driver of Cisco ENIC device.\n */\nstatic int\nrte_enic_pmd_init(const char *name __rte_unused,\n\tconst char *params __rte_unused)\n{\n\tENICPMD_FUNC_TRACE();\n\n\trte_eth_driver_register(&rte_enic_pmd);\n\treturn 0;\n}\n\nstatic struct rte_driver rte_enic_driver = {\n\t.type = PMD_PDEV,\n\t.init = rte_enic_pmd_init,\n};\n\nPMD_REGISTER_DRIVER(rte_enic_driver);\n" }, { "path": "drivers/net/enic/enic_main.c", "content": "/*\n * Copyright 2008-2014 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id$\"\n\n#include \n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"enic_compat.h\"\n#include \"enic.h\"\n#include \"wq_enet_desc.h\"\n#include \"rq_enet_desc.h\"\n#include \"cq_enet_desc.h\"\n#include \"vnic_enet.h\"\n#include \"vnic_dev.h\"\n#include \"vnic_wq.h\"\n#include \"vnic_rq.h\"\n#include \"vnic_cq.h\"\n#include \"vnic_intr.h\"\n#include \"vnic_nic.h\"\n\nstatic inline int enic_is_sriov_vf(struct enic *enic)\n{\n\treturn enic->pdev->id.device_id == PCI_DEVICE_ID_CISCO_VIC_ENET_VF;\n}\n\nstatic int is_zero_addr(uint8_t *addr)\n{\n\treturn !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);\n}\n\nstatic int is_mcast_addr(uint8_t *addr)\n{\n\treturn addr[0] & 1;\n}\n\nstatic int is_eth_addr_valid(uint8_t *addr)\n{\n\treturn !is_mcast_addr(addr) && !is_zero_addr(addr);\n}\n\nstatic inline struct rte_mbuf *\nenic_rxmbuf_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\n\tm = __rte_mbuf_raw_alloc(mp);\n\t__rte_mbuf_sanity_check_raw(m, 0);\n\treturn m;\n}\n\nvoid enic_set_hdr_split_size(struct enic *enic, u16 split_hdr_size)\n{\n\tvnic_set_hdr_split_size(enic->vdev, split_hdr_size);\n}\n\nstatic void enic_free_wq_buf(__rte_unused struct vnic_wq *wq, struct vnic_wq_buf *buf)\n{\n\tstruct rte_mbuf *mbuf = (struct rte_mbuf *)buf->os_buf;\n\n\trte_mempool_put(mbuf->pool, mbuf);\n\tbuf->os_buf = NULL;\n}\n\nstatic void enic_wq_free_buf(struct vnic_wq *wq,\n\t__rte_unused struct cq_desc *cq_desc,\n\tstruct vnic_wq_buf *buf,\n\t__rte_unused void *opaque)\n{\n\tenic_free_wq_buf(wq, buf);\n}\n\nstatic int enic_wq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,\n\t__rte_unused u8 type, u16 q_number, u16 completed_index, void *opaque)\n{\n\tstruct enic *enic = vnic_dev_priv(vdev);\n\n\tvnic_wq_service(&enic->wq[q_number], cq_desc,\n\t\tcompleted_index, enic_wq_free_buf,\n\t\topaque);\n\n\treturn 0;\n}\n\nstatic void enic_log_q_error(struct enic *enic)\n{\n\tunsigned int i;\n\tu32 error_status;\n\n\tfor (i = 0; i < enic->wq_count; i++) {\n\t\terror_status = vnic_wq_error_status(&enic->wq[i]);\n\t\tif (error_status)\n\t\t\tdev_err(enic, \"WQ[%d] error_status %d\\n\", i,\n\t\t\t\terror_status);\n\t}\n\n\tfor (i = 0; i < enic->rq_count; i++) {\n\t\terror_status = vnic_rq_error_status(&enic->rq[i]);\n\t\tif (error_status)\n\t\t\tdev_err(enic, \"RQ[%d] error_status %d\\n\", i,\n\t\t\t\terror_status);\n\t}\n}\n\nunsigned int enic_cleanup_wq(struct enic *enic, struct vnic_wq *wq)\n{\n\tunsigned int cq = enic_cq_wq(enic, wq->index);\n\n\t/* Return the work done */\n\treturn vnic_cq_service(&enic->cq[cq],\n\t\t-1 /*wq_work_to_do*/, enic_wq_service, NULL);\n}\n\n\nint enic_send_pkt(struct enic *enic, struct vnic_wq *wq,\n\tstruct rte_mbuf *tx_pkt, unsigned short len,\n\tuint8_t sop, uint8_t eop,\n\tuint16_t ol_flags, uint16_t vlan_tag)\n{\n\tstruct wq_enet_desc *desc = vnic_wq_next_desc(wq);\n\tuint16_t mss = 0;\n\tuint8_t cq_entry = eop;\n\tuint8_t vlan_tag_insert = 0;\n\tuint64_t bus_addr = (dma_addr_t)\n\t (tx_pkt->buf_physaddr + RTE_PKTMBUF_HEADROOM);\n\n\tif (sop) {\n\t\tif (ol_flags & PKT_TX_VLAN_PKT)\n\t\t\tvlan_tag_insert = 1;\n\n\t\tif (enic->hw_ip_checksum) {\n\t\t\tif (ol_flags & PKT_TX_IP_CKSUM)\n\t\t\t\tmss |= ENIC_CALC_IP_CKSUM;\n\n\t\t\tif (ol_flags & PKT_TX_TCP_UDP_CKSUM)\n\t\t\t\tmss |= ENIC_CALC_TCP_UDP_CKSUM;\n\t\t}\n\t}\n\n\twq_enet_desc_enc(desc,\n\t\tbus_addr,\n\t\tlen,\n\t\tmss,\n\t\t0 /* header_length */,\n\t\t0 /* offload_mode WQ_ENET_OFFLOAD_MODE_CSUM */,\n\t\teop,\n\t\tcq_entry,\n\t\t0 /* fcoe_encap */,\n\t\tvlan_tag_insert,\n\t\tvlan_tag,\n\t\t0 /* loopback */);\n\n\tvnic_wq_post(wq, (void *)tx_pkt, bus_addr, len,\n\t\tsop, eop,\n\t\t1 /*desc_skip_cnt*/,\n\t\tcq_entry,\n\t\t0 /*compressed send*/,\n\t\t0 /*wrid*/);\n\n\treturn 0;\n}\n\nvoid enic_dev_stats_clear(struct enic *enic)\n{\n\tif (vnic_dev_stats_clear(enic->vdev))\n\t\tdev_err(enic, \"Error in clearing stats\\n\");\n}\n\nvoid enic_dev_stats_get(struct enic *enic, struct rte_eth_stats *r_stats)\n{\n\tstruct vnic_stats *stats;\n\n\tif (vnic_dev_stats_dump(enic->vdev, &stats)) {\n\t\tdev_err(enic, \"Error in getting stats\\n\");\n\t\treturn;\n\t}\n\n\tr_stats->ipackets = stats->rx.rx_frames_ok;\n\tr_stats->opackets = stats->tx.tx_frames_ok;\n\n\tr_stats->ibytes = stats->rx.rx_bytes_ok;\n\tr_stats->obytes = stats->tx.tx_bytes_ok;\n\n\tr_stats->ierrors = stats->rx.rx_errors;\n\tr_stats->oerrors = stats->tx.tx_errors;\n\n\tr_stats->imcasts = stats->rx.rx_multicast_frames_ok;\n\tr_stats->rx_nombuf = stats->rx.rx_no_bufs;\n}\n\nvoid enic_del_mac_address(struct enic *enic)\n{\n\tif (vnic_dev_del_addr(enic->vdev, enic->mac_addr))\n\t\tdev_err(enic, \"del mac addr failed\\n\");\n}\n\nvoid enic_set_mac_address(struct enic *enic, uint8_t *mac_addr)\n{\n\tint err;\n\n\tif (!is_eth_addr_valid(mac_addr)) {\n\t\tdev_err(enic, \"invalid mac address\\n\");\n\t\treturn;\n\t}\n\n\terr = vnic_dev_del_addr(enic->vdev, mac_addr);\n\tif (err) {\n\t\tdev_err(enic, \"del mac addr failed\\n\");\n\t\treturn;\n\t}\n\n\tether_addr_copy((struct ether_addr *)mac_addr,\n\t\t(struct ether_addr *)enic->mac_addr);\n\n\terr = vnic_dev_add_addr(enic->vdev, mac_addr);\n\tif (err) {\n\t\tdev_err(enic, \"add mac addr failed\\n\");\n\t\treturn;\n\t}\n}\n\nstatic void\nenic_free_rq_buf(__rte_unused struct vnic_rq *rq, struct vnic_rq_buf *buf)\n{\n\tif (!buf->os_buf)\n\t\treturn;\n\n\trte_pktmbuf_free((struct rte_mbuf *)buf->os_buf);\n\tbuf->os_buf = NULL;\n}\n\nvoid enic_init_vnic_resources(struct enic *enic)\n{\n\tunsigned int error_interrupt_enable = 1;\n\tunsigned int error_interrupt_offset = 0;\n\tunsigned int index = 0;\n\n\tfor (index = 0; index < enic->rq_count; index++) {\n\t\tvnic_rq_init(&enic->rq[index],\n\t\t\tenic_cq_rq(enic, index),\n\t\t\terror_interrupt_enable,\n\t\t\terror_interrupt_offset);\n\t}\n\n\tfor (index = 0; index < enic->wq_count; index++) {\n\t\tvnic_wq_init(&enic->wq[index],\n\t\t\tenic_cq_wq(enic, index),\n\t\t\terror_interrupt_enable,\n\t\t\terror_interrupt_offset);\n\t}\n\n\tvnic_dev_stats_clear(enic->vdev);\n\n\tfor (index = 0; index < enic->cq_count; index++) {\n\t\tvnic_cq_init(&enic->cq[index],\n\t\t\t0 /* flow_control_enable */,\n\t\t\t1 /* color_enable */,\n\t\t\t0 /* cq_head */,\n\t\t\t0 /* cq_tail */,\n\t\t\t1 /* cq_tail_color */,\n\t\t\t0 /* interrupt_enable */,\n\t\t\t1 /* cq_entry_enable */,\n\t\t\t0 /* cq_message_enable */,\n\t\t\t0 /* interrupt offset */,\n\t\t\t0 /* cq_message_addr */);\n\t}\n\n\tvnic_intr_init(&enic->intr,\n\t\tenic->config.intr_timer_usec,\n\t\tenic->config.intr_timer_type,\n\t\t/*mask_on_assertion*/1);\n}\n\n\nstatic int enic_rq_alloc_buf(struct vnic_rq *rq)\n{\n\tstruct enic *enic = vnic_dev_priv(rq->vdev);\n\tdma_addr_t dma_addr;\n\tstruct rq_enet_desc *desc = vnic_rq_next_desc(rq);\n\tuint8_t type = RQ_ENET_TYPE_ONLY_SOP;\n\tu16 split_hdr_size = vnic_get_hdr_split_size(enic->vdev);\n\tstruct rte_mbuf *mbuf = enic_rxmbuf_alloc(rq->mp);\n\tstruct rte_mbuf *hdr_mbuf = NULL;\n\n\tif (!mbuf) {\n\t\tdev_err(enic, \"mbuf alloc in enic_rq_alloc_buf failed\\n\");\n\t\treturn -1;\n\t}\n\n\tif (unlikely(split_hdr_size)) {\n\t\tif (vnic_rq_desc_avail(rq) < 2) {\n\t\t\trte_mempool_put(mbuf->pool, mbuf);\n\t\t\treturn -1;\n\t\t}\n\t\thdr_mbuf = enic_rxmbuf_alloc(rq->mp);\n\t\tif (!hdr_mbuf) {\n\t\t\trte_mempool_put(mbuf->pool, mbuf);\n\t\t\tdev_err(enic,\n\t\t\t\t\"hdr_mbuf alloc in enic_rq_alloc_buf failed\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\thdr_mbuf->data_off = RTE_PKTMBUF_HEADROOM;\n\n\t\thdr_mbuf->nb_segs = 2;\n\t\thdr_mbuf->port = enic->port_id;\n\t\thdr_mbuf->next = mbuf;\n\n\t\tdma_addr = (dma_addr_t)\n\t\t (hdr_mbuf->buf_physaddr + hdr_mbuf->data_off);\n\n\t\trq_enet_desc_enc(desc, dma_addr, type, split_hdr_size);\n\n\t\tvnic_rq_post(rq, (void *)hdr_mbuf, 0 /*os_buf_index*/, dma_addr,\n\t\t\t(unsigned int)split_hdr_size, 0 /*wrid*/);\n\n\t\tdesc = vnic_rq_next_desc(rq);\n\t\ttype = RQ_ENET_TYPE_NOT_SOP;\n\t} else {\n\t\tmbuf->nb_segs = 1;\n\t\tmbuf->port = enic->port_id;\n\t}\n\n\tmbuf->data_off = RTE_PKTMBUF_HEADROOM;\n\tmbuf->next = NULL;\n\n\tdma_addr = (dma_addr_t)\n\t (mbuf->buf_physaddr + mbuf->data_off);\n\n\trq_enet_desc_enc(desc, dma_addr, type, mbuf->buf_len);\n\n\tvnic_rq_post(rq, (void *)mbuf, 0 /*os_buf_index*/, dma_addr,\n\t\t(unsigned int)mbuf->buf_len, 0 /*wrid*/);\n\n\treturn 0;\n}\n\nstatic int enic_rq_indicate_buf(struct vnic_rq *rq,\n\tstruct cq_desc *cq_desc, struct vnic_rq_buf *buf,\n\tint skipped, void *opaque)\n{\n\tstruct enic *enic = vnic_dev_priv(rq->vdev);\n\tstruct rte_mbuf **rx_pkt_bucket = (struct rte_mbuf **)opaque;\n\tstruct rte_mbuf *rx_pkt = NULL;\n\tstruct rte_mbuf *hdr_rx_pkt = NULL;\n\n\tu8 type, color, eop, sop, ingress_port, vlan_stripped;\n\tu8 fcoe, fcoe_sof, fcoe_fc_crc_ok, fcoe_enc_error, fcoe_eof;\n\tu8 tcp_udp_csum_ok, udp, tcp, ipv4_csum_ok;\n\tu8 ipv6, ipv4, ipv4_fragment, fcs_ok, rss_type, csum_not_calc;\n\tu8 packet_error;\n\tu16 q_number, completed_index, bytes_written, vlan_tci, checksum;\n\tu32 rss_hash;\n\n\tcq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,\n\t\t&type, &color, &q_number, &completed_index,\n\t\t&ingress_port, &fcoe, &eop, &sop, &rss_type,\n\t\t&csum_not_calc, &rss_hash, &bytes_written,\n\t\t&packet_error, &vlan_stripped, &vlan_tci, &checksum,\n\t\t&fcoe_sof, &fcoe_fc_crc_ok, &fcoe_enc_error,\n\t\t&fcoe_eof, &tcp_udp_csum_ok, &udp, &tcp,\n\t\t&ipv4_csum_ok, &ipv6, &ipv4, &ipv4_fragment,\n\t\t&fcs_ok);\n\n\trx_pkt = (struct rte_mbuf *)buf->os_buf;\n\tbuf->os_buf = NULL;\n\n\tif (unlikely(packet_error)) {\n\t\tdev_err(enic, \"packet error\\n\");\n\t\trx_pkt->data_len = 0;\n\t\treturn 0;\n\t}\n\n\tif (unlikely(skipped)) {\n\t\trx_pkt->data_len = 0;\n\t\treturn 0;\n\t}\n\n\tif (likely(!vnic_get_hdr_split_size(enic->vdev))) {\n\t\t/* No header split configured */\n\t\t*rx_pkt_bucket = rx_pkt;\n\t\trx_pkt->pkt_len = bytes_written;\n\n\t\tif (ipv4) {\n#ifdef RTE_NEXT_ABI\n\t\t\trx_pkt->packet_type = RTE_PTYPE_L3_IPV4;\n#else\n\t\t\trx_pkt->ol_flags |= PKT_RX_IPV4_HDR;\n#endif\n\t\t\tif (!csum_not_calc) {\n\t\t\t\tif (unlikely(!ipv4_csum_ok))\n\t\t\t\t\trx_pkt->ol_flags |= PKT_RX_IP_CKSUM_BAD;\n\n\t\t\t\tif ((tcp || udp) && (!tcp_udp_csum_ok))\n\t\t\t\t\trx_pkt->ol_flags |= PKT_RX_L4_CKSUM_BAD;\n\t\t\t}\n\t\t} else if (ipv6)\n#ifdef RTE_NEXT_ABI\n\t\t\trx_pkt->packet_type = RTE_PTYPE_L3_IPV6;\n#else\n\t\t\trx_pkt->ol_flags |= PKT_RX_IPV6_HDR;\n#endif\n\t} else {\n\t\t/* Header split */\n\t\tif (sop && !eop) {\n\t\t\t/* This piece is header */\n\t\t\t*rx_pkt_bucket = rx_pkt;\n\t\t\trx_pkt->pkt_len = bytes_written;\n\t\t} else {\n\t\t\tif (sop && eop) {\n\t\t\t\t/* The packet is smaller than split_hdr_size */\n\t\t\t\t*rx_pkt_bucket = rx_pkt;\n\t\t\t\trx_pkt->pkt_len = bytes_written;\n\t\t\t\tif (ipv4) {\n#ifdef RTE_NEXT_ABI\n\t\t\t\t\trx_pkt->packet_type = RTE_PTYPE_L3_IPV4;\n#else\n\t\t\t\t\trx_pkt->ol_flags |= PKT_RX_IPV4_HDR;\n#endif\n\t\t\t\t\tif (!csum_not_calc) {\n\t\t\t\t\t\tif (unlikely(!ipv4_csum_ok))\n\t\t\t\t\t\t\trx_pkt->ol_flags |=\n\t\t\t\t\t\t\t PKT_RX_IP_CKSUM_BAD;\n\n\t\t\t\t\t\tif ((tcp || udp) &&\n\t\t\t\t\t\t (!tcp_udp_csum_ok))\n\t\t\t\t\t\t\trx_pkt->ol_flags |=\n\t\t\t\t\t\t\t PKT_RX_L4_CKSUM_BAD;\n\t\t\t\t\t}\n\t\t\t\t} else if (ipv6)\n#ifdef RTE_NEXT_ABI\n\t\t\t\t\trx_pkt->packet_type = RTE_PTYPE_L3_IPV6;\n#else\n\t\t\t\t\trx_pkt->ol_flags |= PKT_RX_IPV6_HDR;\n#endif\n\t\t\t} else {\n\t\t\t\t/* Payload */\n\t\t\t\thdr_rx_pkt = *rx_pkt_bucket;\n\t\t\t\thdr_rx_pkt->pkt_len += bytes_written;\n\t\t\t\tif (ipv4) {\n#ifdef RTE_NEXT_ABI\n\t\t\t\t\thdr_rx_pkt->packet_type =\n\t\t\t\t\t\tRTE_PTYPE_L3_IPV4;\n#else\n\t\t\t\t\thdr_rx_pkt->ol_flags |= PKT_RX_IPV4_HDR;\n#endif\n\t\t\t\t\tif (!csum_not_calc) {\n\t\t\t\t\t\tif (unlikely(!ipv4_csum_ok))\n\t\t\t\t\t\t\thdr_rx_pkt->ol_flags |=\n\t\t\t\t\t\t\t PKT_RX_IP_CKSUM_BAD;\n\n\t\t\t\t\t\tif ((tcp || udp) &&\n\t\t\t\t\t\t (!tcp_udp_csum_ok))\n\t\t\t\t\t\t\thdr_rx_pkt->ol_flags |=\n\t\t\t\t\t\t\t PKT_RX_L4_CKSUM_BAD;\n\t\t\t\t\t}\n\t\t\t\t} else if (ipv6)\n#ifdef RTE_NEXT_ABI\n\t\t\t\t\thdr_rx_pkt->packet_type =\n\t\t\t\t\t\tRTE_PTYPE_L3_IPV6;\n#else\n\t\t\t\t\thdr_rx_pkt->ol_flags |= PKT_RX_IPV6_HDR;\n#endif\n\n\t\t\t}\n\t\t}\n\t}\n\n\trx_pkt->data_len = bytes_written;\n\n\tif (rss_hash) {\n\t\trx_pkt->ol_flags |= PKT_RX_RSS_HASH;\n\t\trx_pkt->hash.rss = rss_hash;\n\t}\n\n\tif (vlan_tci) {\n\t\trx_pkt->ol_flags |= PKT_RX_VLAN_PKT;\n\t\trx_pkt->vlan_tci = vlan_tci;\n\t}\n\n\treturn eop;\n}\n\nstatic int enic_rq_service(struct vnic_dev *vdev, struct cq_desc *cq_desc,\n\t__rte_unused u8 type, u16 q_number, u16 completed_index, void *opaque)\n{\n\tstruct enic *enic = vnic_dev_priv(vdev);\n\n\treturn vnic_rq_service(&enic->rq[q_number], cq_desc,\n\t\tcompleted_index, VNIC_RQ_RETURN_DESC,\n\t\tenic_rq_indicate_buf, opaque);\n\n}\n\nint enic_poll(struct vnic_rq *rq, struct rte_mbuf **rx_pkts,\n\tunsigned int budget, unsigned int *work_done)\n{\n\tstruct enic *enic = vnic_dev_priv(rq->vdev);\n\tunsigned int cq = enic_cq_rq(enic, rq->index);\n\tint err = 0;\n\n\t*work_done = vnic_cq_service(&enic->cq[cq],\n\t\tbudget, enic_rq_service, (void *)rx_pkts);\n\n\tif (*work_done) {\n\t\tvnic_rq_fill(rq, enic_rq_alloc_buf);\n\n\t\t/* Need at least one buffer on ring to get going */\n\t\tif (vnic_rq_desc_used(rq) == 0) {\n\t\t\tdev_err(enic, \"Unable to alloc receive buffers\\n\");\n\t\t\terr = -1;\n\t\t}\n\t}\n\treturn err;\n}\n\nstatic void *\nenic_alloc_consistent(__rte_unused void *priv, size_t size,\n\tdma_addr_t *dma_handle, u8 *name)\n{\n\tvoid *vaddr;\n\tconst struct rte_memzone *rz;\n\t*dma_handle = 0;\n\n\trz = rte_memzone_reserve_aligned((const char *)name,\n\t\tsize, 0, 0, ENIC_ALIGN);\n\tif (!rz) {\n\t\tpr_err(\"%s : Failed to allocate memory requested for %s\",\n\t\t\t__func__, name);\n\t\treturn NULL;\n\t}\n\n\tvaddr = rz->addr;\n\t*dma_handle = (dma_addr_t)rz->phys_addr;\n\n\treturn vaddr;\n}\n\nstatic void\nenic_free_consistent(__rte_unused struct rte_pci_device *hwdev,\n\t__rte_unused size_t size,\n\t__rte_unused void *vaddr,\n\t__rte_unused dma_addr_t dma_handle)\n{\n\t/* Nothing to be done */\n}\n\nstatic void\nenic_intr_handler(__rte_unused struct rte_intr_handle *handle,\n\tvoid *arg)\n{\n\tstruct enic *enic = pmd_priv((struct rte_eth_dev *)arg);\n\n\tvnic_intr_return_all_credits(&enic->intr);\n\n\tenic_log_q_error(enic);\n}\n\nint enic_enable(struct enic *enic)\n{\n\tunsigned int index;\n\tstruct rte_eth_dev *eth_dev = enic->rte_dev;\n\n\teth_dev->data->dev_link.link_speed = vnic_dev_port_speed(enic->vdev);\n\teth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;\n\tvnic_dev_notify_set(enic->vdev, -1); /* No Intr for notify */\n\n\tif (enic_clsf_init(enic))\n\t\tdev_warning(enic, \"Init of hash table for clsf failed.\"\\\n\t\t\t\"Flow director feature will not work\\n\");\n\n\t/* Fill RQ bufs */\n\tfor (index = 0; index < enic->rq_count; index++) {\n\t\tvnic_rq_fill(&enic->rq[index], enic_rq_alloc_buf);\n\n\t\t/* Need at least one buffer on ring to get going\n\t\t*/\n\t\tif (vnic_rq_desc_used(&enic->rq[index]) == 0) {\n\t\t\tdev_err(enic, \"Unable to alloc receive buffers\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tfor (index = 0; index < enic->wq_count; index++)\n\t\tvnic_wq_enable(&enic->wq[index]);\n\tfor (index = 0; index < enic->rq_count; index++)\n\t\tvnic_rq_enable(&enic->rq[index]);\n\n\tvnic_dev_enable_wait(enic->vdev);\n\n\t/* Register and enable error interrupt */\n\trte_intr_callback_register(&(enic->pdev->intr_handle),\n\t\tenic_intr_handler, (void *)enic->rte_dev);\n\n\trte_intr_enable(&(enic->pdev->intr_handle));\n\tvnic_intr_unmask(&enic->intr);\n\n\treturn 0;\n}\n\nint enic_alloc_intr_resources(struct enic *enic)\n{\n\tint err;\n\n\tdev_info(enic, \"vNIC resources used: \"\\\n\t\t\"wq %d rq %d cq %d intr %d\\n\",\n\t\tenic->wq_count, enic->rq_count,\n\t\tenic->cq_count, enic->intr_count);\n\n\terr = vnic_intr_alloc(enic->vdev, &enic->intr, 0);\n\tif (err)\n\t\tenic_free_vnic_resources(enic);\n\n\treturn err;\n}\n\nvoid enic_free_rq(void *rxq)\n{\n\tstruct vnic_rq *rq = (struct vnic_rq *)rxq;\n\tstruct enic *enic = vnic_dev_priv(rq->vdev);\n\n\tvnic_rq_free(rq);\n\tvnic_cq_free(&enic->cq[rq->index]);\n}\n\nvoid enic_start_wq(struct enic *enic, uint16_t queue_idx)\n{\n\tvnic_wq_enable(&enic->wq[queue_idx]);\n}\n\nint enic_stop_wq(struct enic *enic, uint16_t queue_idx)\n{\n\treturn vnic_wq_disable(&enic->wq[queue_idx]);\n}\n\nvoid enic_start_rq(struct enic *enic, uint16_t queue_idx)\n{\n\tvnic_rq_enable(&enic->rq[queue_idx]);\n}\n\nint enic_stop_rq(struct enic *enic, uint16_t queue_idx)\n{\n\treturn vnic_rq_disable(&enic->rq[queue_idx]);\n}\n\nint enic_alloc_rq(struct enic *enic, uint16_t queue_idx,\n\tunsigned int socket_id, struct rte_mempool *mp,\n\tuint16_t nb_desc)\n{\n\tint err;\n\tstruct vnic_rq *rq = &enic->rq[queue_idx];\n\n\trq->socket_id = socket_id;\n\trq->mp = mp;\n\n\tif (nb_desc) {\n\t\tif (nb_desc > enic->config.rq_desc_count) {\n\t\t\tdev_warning(enic,\n\t\t\t\t\"RQ %d - number of rx desc in cmd line (%d)\"\\\n\t\t\t\t\"is greater than that in the UCSM/CIMC adapter\"\\\n\t\t\t\t\"policy. Applying the value in the adapter \"\\\n\t\t\t\t\"policy (%d).\\n\",\n\t\t\t\tqueue_idx, nb_desc, enic->config.rq_desc_count);\n\t\t} else if (nb_desc != enic->config.rq_desc_count) {\n\t\t\tenic->config.rq_desc_count = nb_desc;\n\t\t\tdev_info(enic,\n\t\t\t\t\"RX Queues - effective number of descs:%d\\n\",\n\t\t\t\tnb_desc);\n\t\t}\n\t}\n\n\t/* Allocate queue resources */\n\terr = vnic_rq_alloc(enic->vdev, &enic->rq[queue_idx], queue_idx,\n\t\tenic->config.rq_desc_count,\n\t\tsizeof(struct rq_enet_desc));\n\tif (err) {\n\t\tdev_err(enic, \"error in allocation of rq\\n\");\n\t\treturn err;\n\t}\n\n\terr = vnic_cq_alloc(enic->vdev, &enic->cq[queue_idx], queue_idx,\n\t\tsocket_id, enic->config.rq_desc_count,\n\t\tsizeof(struct cq_enet_rq_desc));\n\tif (err) {\n\t\tvnic_rq_free(rq);\n\t\tdev_err(enic, \"error in allocation of cq for rq\\n\");\n\t}\n\n\treturn err;\n}\n\nvoid enic_free_wq(void *txq)\n{\n\tstruct vnic_wq *wq = (struct vnic_wq *)txq;\n\tstruct enic *enic = vnic_dev_priv(wq->vdev);\n\n\tvnic_wq_free(wq);\n\tvnic_cq_free(&enic->cq[enic->rq_count + wq->index]);\n}\n\nint enic_alloc_wq(struct enic *enic, uint16_t queue_idx,\n\tunsigned int socket_id, uint16_t nb_desc)\n{\n\tint err;\n\tstruct vnic_wq *wq = &enic->wq[queue_idx];\n\tunsigned int cq_index = enic_cq_wq(enic, queue_idx);\n\n\twq->socket_id = socket_id;\n\tif (nb_desc) {\n\t\tif (nb_desc > enic->config.wq_desc_count) {\n\t\t\tdev_warning(enic,\n\t\t\t\t\"WQ %d - number of tx desc in cmd line (%d)\"\\\n\t\t\t\t\"is greater than that in the UCSM/CIMC adapter\"\\\n\t\t\t\t\"policy. Applying the value in the adapter \"\\\n\t\t\t\t\"policy (%d)\\n\",\n\t\t\t\tqueue_idx, nb_desc, enic->config.wq_desc_count);\n\t\t} else if (nb_desc != enic->config.wq_desc_count) {\n\t\t\tenic->config.wq_desc_count = nb_desc;\n\t\t\tdev_info(enic,\n\t\t\t\t\"TX Queues - effective number of descs:%d\\n\",\n\t\t\t\tnb_desc);\n\t\t}\n\t}\n\n\t/* Allocate queue resources */\n\terr = vnic_wq_alloc(enic->vdev, &enic->wq[queue_idx], queue_idx,\n\t\tenic->config.wq_desc_count,\n\t\tsizeof(struct wq_enet_desc));\n\tif (err) {\n\t\tdev_err(enic, \"error in allocation of wq\\n\");\n\t\treturn err;\n\t}\n\n\terr = vnic_cq_alloc(enic->vdev, &enic->cq[cq_index], cq_index,\n\t\tsocket_id, enic->config.wq_desc_count,\n\t\tsizeof(struct cq_enet_wq_desc));\n\tif (err) {\n\t\tvnic_wq_free(wq);\n\t\tdev_err(enic, \"error in allocation of cq for wq\\n\");\n\t}\n\n\treturn err;\n}\n\nint enic_disable(struct enic *enic)\n{\n\tunsigned int i;\n\tint err;\n\n\tvnic_intr_mask(&enic->intr);\n\t(void)vnic_intr_masked(&enic->intr); /* flush write */\n\n\tvnic_dev_disable(enic->vdev);\n\n\tenic_clsf_destroy(enic);\n\n\tif (!enic_is_sriov_vf(enic))\n\t\tvnic_dev_del_addr(enic->vdev, enic->mac_addr);\n\n\tfor (i = 0; i < enic->wq_count; i++) {\n\t\terr = vnic_wq_disable(&enic->wq[i]);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\tfor (i = 0; i < enic->rq_count; i++) {\n\t\terr = vnic_rq_disable(&enic->rq[i]);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\tvnic_dev_set_reset_flag(enic->vdev, 1);\n\tvnic_dev_notify_unset(enic->vdev);\n\n\tfor (i = 0; i < enic->wq_count; i++)\n\t\tvnic_wq_clean(&enic->wq[i], enic_free_wq_buf);\n\tfor (i = 0; i < enic->rq_count; i++)\n\t\tvnic_rq_clean(&enic->rq[i], enic_free_rq_buf);\n\tfor (i = 0; i < enic->cq_count; i++)\n\t\tvnic_cq_clean(&enic->cq[i]);\n\tvnic_intr_clean(&enic->intr);\n\n\treturn 0;\n}\n\nstatic int enic_dev_wait(struct vnic_dev *vdev,\n\tint (*start)(struct vnic_dev *, int),\n\tint (*finished)(struct vnic_dev *, int *),\n\tint arg)\n{\n\tint done;\n\tint err;\n\tint i;\n\n\terr = start(vdev, arg);\n\tif (err)\n\t\treturn err;\n\n\t/* Wait for func to complete...2 seconds max */\n\tfor (i = 0; i < 2000; i++) {\n\t\terr = finished(vdev, &done);\n\t\tif (err)\n\t\t\treturn err;\n\t\tif (done)\n\t\t\treturn 0;\n\t\tusleep(1000);\n\t}\n\treturn -ETIMEDOUT;\n}\n\nstatic int enic_dev_open(struct enic *enic)\n{\n\tint err;\n\n\terr = enic_dev_wait(enic->vdev, vnic_dev_open,\n\t\tvnic_dev_open_done, 0);\n\tif (err)\n\t\tdev_err(enic_get_dev(enic),\n\t\t\t\"vNIC device open failed, err %d\\n\", err);\n\n\treturn err;\n}\n\nstatic int enic_set_rsskey(struct enic *enic)\n{\n\tdma_addr_t rss_key_buf_pa;\n\tunion vnic_rss_key *rss_key_buf_va = NULL;\n\tstatic union vnic_rss_key rss_key = {\n\t\t.key = {\n\t\t\t[0] = {.b = {85, 67, 83, 97, 119, 101, 115, 111, 109, 101}},\n\t\t\t[1] = {.b = {80, 65, 76, 79, 117, 110, 105, 113, 117, 101}},\n\t\t\t[2] = {.b = {76, 73, 78, 85, 88, 114, 111, 99, 107, 115}},\n\t\t\t[3] = {.b = {69, 78, 73, 67, 105, 115, 99, 111, 111, 108}},\n\t\t}\n\t};\n\tint err;\n\tu8 name[NAME_MAX];\n\n\tsnprintf((char *)name, NAME_MAX, \"rss_key-%s\", enic->bdf_name);\n\trss_key_buf_va = enic_alloc_consistent(enic, sizeof(union vnic_rss_key),\n\t\t&rss_key_buf_pa, name);\n\tif (!rss_key_buf_va)\n\t\treturn -ENOMEM;\n\n\trte_memcpy(rss_key_buf_va, &rss_key, sizeof(union vnic_rss_key));\n\n\terr = enic_set_rss_key(enic,\n\t\trss_key_buf_pa,\n\t\tsizeof(union vnic_rss_key));\n\n\tenic_free_consistent(enic->pdev, sizeof(union vnic_rss_key),\n\t\trss_key_buf_va, rss_key_buf_pa);\n\n\treturn err;\n}\n\nstatic int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)\n{\n\tdma_addr_t rss_cpu_buf_pa;\n\tunion vnic_rss_cpu *rss_cpu_buf_va = NULL;\n\tint i;\n\tint err;\n\tu8 name[NAME_MAX];\n\n\tsnprintf((char *)name, NAME_MAX, \"rss_cpu-%s\", enic->bdf_name);\n\trss_cpu_buf_va = enic_alloc_consistent(enic, sizeof(union vnic_rss_cpu),\n\t\t&rss_cpu_buf_pa, name);\n\tif (!rss_cpu_buf_va)\n\t\treturn -ENOMEM;\n\n\tfor (i = 0; i < (1 << rss_hash_bits); i++)\n\t\t(*rss_cpu_buf_va).cpu[i/4].b[i%4] = i % enic->rq_count;\n\n\terr = enic_set_rss_cpu(enic,\n\t\trss_cpu_buf_pa,\n\t\tsizeof(union vnic_rss_cpu));\n\n\tenic_free_consistent(enic->pdev, sizeof(union vnic_rss_cpu),\n\t\trss_cpu_buf_va, rss_cpu_buf_pa);\n\n\treturn err;\n}\n\nstatic int enic_set_niccfg(struct enic *enic, u8 rss_default_cpu,\n\tu8 rss_hash_type, u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable)\n{\n\tconst u8 tso_ipid_split_en = 0;\n\tint err;\n\n\t/* Enable VLAN tag stripping */\n\n\terr = enic_set_nic_cfg(enic,\n\t\trss_default_cpu, rss_hash_type,\n\t\trss_hash_bits, rss_base_cpu,\n\t\trss_enable, tso_ipid_split_en,\n\t\tenic->ig_vlan_strip_en);\n\n\treturn err;\n}\n\nint enic_set_rss_nic_cfg(struct enic *enic)\n{\n\tconst u8 rss_default_cpu = 0;\n\tconst u8 rss_hash_type = NIC_CFG_RSS_HASH_TYPE_IPV4 |\n\t NIC_CFG_RSS_HASH_TYPE_TCP_IPV4 |\n\t NIC_CFG_RSS_HASH_TYPE_IPV6 |\n\t NIC_CFG_RSS_HASH_TYPE_TCP_IPV6;\n\tconst u8 rss_hash_bits = 7;\n\tconst u8 rss_base_cpu = 0;\n\tu8 rss_enable = ENIC_SETTING(enic, RSS) && (enic->rq_count > 1);\n\n\tif (rss_enable) {\n\t\tif (!enic_set_rsskey(enic)) {\n\t\t\tif (enic_set_rsscpu(enic, rss_hash_bits)) {\n\t\t\t\trss_enable = 0;\n\t\t\t\tdev_warning(enic, \"RSS disabled, \"\\\n\t\t\t\t\t\"Failed to set RSS cpu indirection table.\");\n\t\t\t}\n\t\t} else {\n\t\t\trss_enable = 0;\n\t\t\tdev_warning(enic,\n\t\t\t\t\"RSS disabled, Failed to set RSS key.\\n\");\n\t\t}\n\t}\n\n\treturn enic_set_niccfg(enic, rss_default_cpu, rss_hash_type,\n\t\trss_hash_bits, rss_base_cpu, rss_enable);\n}\n\nint enic_setup_finish(struct enic *enic)\n{\n\tint ret;\n\n\tret = enic_set_rss_nic_cfg(enic);\n\tif (ret) {\n\t\tdev_err(enic, \"Failed to config nic, aborting.\\n\");\n\t\treturn -1;\n\t}\n\n\tvnic_dev_add_addr(enic->vdev, enic->mac_addr);\n\n\t/* Default conf */\n\tvnic_dev_packet_filter(enic->vdev,\n\t\t1 /* directed */,\n\t\t1 /* multicast */,\n\t\t1 /* broadcast */,\n\t\t0 /* promisc */,\n\t\t1 /* allmulti */);\n\n\tenic->promisc = 0;\n\tenic->allmulti = 1;\n\n\treturn 0;\n}\n\nvoid enic_add_packet_filter(struct enic *enic)\n{\n\t/* Args -> directed, multicast, broadcast, promisc, allmulti */\n\tvnic_dev_packet_filter(enic->vdev, 1, 1, 1,\n\t\tenic->promisc, enic->allmulti);\n}\n\nint enic_get_link_status(struct enic *enic)\n{\n\treturn vnic_dev_link_status(enic->vdev);\n}\n\nstatic void enic_dev_deinit(struct enic *enic)\n{\n\tstruct rte_eth_dev *eth_dev = enic->rte_dev;\n\n\trte_free(eth_dev->data->mac_addrs);\n}\n\n\nint enic_set_vnic_res(struct enic *enic)\n{\n\tstruct rte_eth_dev *eth_dev = enic->rte_dev;\n\n\tif ((enic->rq_count < eth_dev->data->nb_rx_queues) ||\n\t\t(enic->wq_count < eth_dev->data->nb_tx_queues)) {\n\t\tdev_err(dev, \"Not enough resources configured, aborting\\n\");\n\t\treturn -1;\n\t}\n\n\tenic->rq_count = eth_dev->data->nb_rx_queues;\n\tenic->wq_count = eth_dev->data->nb_tx_queues;\n\tif (enic->cq_count < (enic->rq_count + enic->wq_count)) {\n\t\tdev_err(dev, \"Not enough resources configured, aborting\\n\");\n\t\treturn -1;\n\t}\n\n\tenic->cq_count = enic->rq_count + enic->wq_count;\n\treturn 0;\n}\n\nstatic int enic_dev_init(struct enic *enic)\n{\n\tint err;\n\tstruct rte_eth_dev *eth_dev = enic->rte_dev;\n\n\tvnic_dev_intr_coal_timer_info_default(enic->vdev);\n\n\t/* Get vNIC configuration\n\t*/\n\terr = enic_get_vnic_config(enic);\n\tif (err) {\n\t\tdev_err(dev, \"Get vNIC configuration failed, aborting\\n\");\n\t\treturn err;\n\t}\n\n\teth_dev->data->mac_addrs = rte_zmalloc(\"enic_mac_addr\", ETH_ALEN, 0);\n\tif (!eth_dev->data->mac_addrs) {\n\t\tdev_err(enic, \"mac addr storage alloc failed, aborting.\\n\");\n\t\treturn -1;\n\t}\n\tether_addr_copy((struct ether_addr *) enic->mac_addr,\n\t\tð_dev->data->mac_addrs[0]);\n\n\n\t/* Get available resource counts\n\t*/\n\tenic_get_res_counts(enic);\n\n\tvnic_dev_set_reset_flag(enic->vdev, 0);\n\n\treturn 0;\n\n}\n\nint enic_probe(struct enic *enic)\n{\n\tstruct rte_pci_device *pdev = enic->pdev;\n\tint err = -1;\n\n\tdev_debug(enic, \" Initializing ENIC PMD version %s\\n\", DRV_VERSION);\n\n\tenic->bar0.vaddr = (void *)pdev->mem_resource[0].addr;\n\tenic->bar0.len = pdev->mem_resource[0].len;\n\n\t/* Register vNIC device */\n\tenic->vdev = vnic_dev_register(NULL, enic, enic->pdev, &enic->bar0, 1);\n\tif (!enic->vdev) {\n\t\tdev_err(enic, \"vNIC registration failed, aborting\\n\");\n\t\tgoto err_out;\n\t}\n\n\tvnic_register_cbacks(enic->vdev,\n\t\tenic_alloc_consistent,\n\t\tenic_free_consistent);\n\n\t/* Issue device open to get device in known state */\n\terr = enic_dev_open(enic);\n\tif (err) {\n\t\tdev_err(enic, \"vNIC dev open failed, aborting\\n\");\n\t\tgoto err_out_unregister;\n\t}\n\n\t/* Set ingress vlan rewrite mode before vnic initialization */\n\terr = vnic_dev_set_ig_vlan_rewrite_mode(enic->vdev,\n\t\tIG_VLAN_REWRITE_MODE_PRIORITY_TAG_DEFAULT_VLAN);\n\tif (err) {\n\t\tdev_err(enic,\n\t\t\t\"Failed to set ingress vlan rewrite mode, aborting.\\n\");\n\t\tgoto err_out_dev_close;\n\t}\n\n\t/* Issue device init to initialize the vnic-to-switch link.\n\t * We'll start with carrier off and wait for link UP\n\t * notification later to turn on carrier. We don't need\n\t * to wait here for the vnic-to-switch link initialization\n\t * to complete; link UP notification is the indication that\n\t * the process is complete.\n\t */\n\n\terr = vnic_dev_init(enic->vdev, 0);\n\tif (err) {\n\t\tdev_err(enic, \"vNIC dev init failed, aborting\\n\");\n\t\tgoto err_out_dev_close;\n\t}\n\n\terr = enic_dev_init(enic);\n\tif (err) {\n\t\tdev_err(enic, \"Device initialization failed, aborting\\n\");\n\t\tgoto err_out_dev_close;\n\t}\n\n\treturn 0;\n\nerr_out_dev_close:\n\tvnic_dev_close(enic->vdev);\nerr_out_unregister:\n\tvnic_dev_unregister(enic->vdev);\nerr_out:\n\treturn err;\n}\n\nvoid enic_remove(struct enic *enic)\n{\n\tenic_dev_deinit(enic);\n\tvnic_dev_close(enic->vdev);\n\tvnic_dev_unregister(enic->vdev);\n}\n" }, { "path": "drivers/net/enic/enic_res.c", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: enic_res.c 171146 2014-05-02 07:08:20Z ssujith $\"\n\n#include \"enic_compat.h\"\n#include \"rte_ethdev.h\"\n#include \"wq_enet_desc.h\"\n#include \"rq_enet_desc.h\"\n#include \"cq_enet_desc.h\"\n#include \"vnic_resource.h\"\n#include \"vnic_enet.h\"\n#include \"vnic_dev.h\"\n#include \"vnic_wq.h\"\n#include \"vnic_rq.h\"\n#include \"vnic_cq.h\"\n#include \"vnic_intr.h\"\n#include \"vnic_stats.h\"\n#include \"vnic_nic.h\"\n#include \"vnic_rss.h\"\n#include \"enic_res.h\"\n#include \"enic.h\"\n\nint enic_get_vnic_config(struct enic *enic)\n{\n\tstruct vnic_enet_config *c = &enic->config;\n\tint err;\n\n\terr = vnic_dev_get_mac_addr(enic->vdev, enic->mac_addr);\n\tif (err) {\n\t\tdev_err(enic_get_dev(enic),\n\t\t\t\"Error getting MAC addr, %d\\n\", err);\n\t\treturn err;\n\t}\n\n#define GET_CONFIG(m) \\\n\tdo { \\\n\t\terr = vnic_dev_spec(enic->vdev, \\\n\t\t\toffsetof(struct vnic_enet_config, m), \\\n\t\t\tsizeof(c->m), &c->m); \\\n\t\tif (err) { \\\n\t\t\tdev_err(enic_get_dev(enic), \\\n\t\t\t\t\"Error getting %s, %d\\n\", #m, err); \\\n\t\t\treturn err; \\\n\t\t} \\\n\t} while (0)\n\n\tGET_CONFIG(flags);\n\tGET_CONFIG(wq_desc_count);\n\tGET_CONFIG(rq_desc_count);\n\tGET_CONFIG(mtu);\n\tGET_CONFIG(intr_timer_type);\n\tGET_CONFIG(intr_mode);\n\tGET_CONFIG(intr_timer_usec);\n\tGET_CONFIG(loop_tag);\n\tGET_CONFIG(num_arfs);\n\n\tc->wq_desc_count =\n\t\tmin_t(u32, ENIC_MAX_WQ_DESCS,\n\t\tmax_t(u32, ENIC_MIN_WQ_DESCS,\n\t\tc->wq_desc_count));\n\tc->wq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */\n\n\tc->rq_desc_count =\n\t\tmin_t(u32, ENIC_MAX_RQ_DESCS,\n\t\tmax_t(u32, ENIC_MIN_RQ_DESCS,\n\t\tc->rq_desc_count));\n\tc->rq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */\n\n\tif (c->mtu == 0)\n\t\tc->mtu = 1500;\n\tc->mtu = min_t(u16, ENIC_MAX_MTU,\n\t\tmax_t(u16, ENIC_MIN_MTU,\n\t\tc->mtu));\n\n\tc->intr_timer_usec = min_t(u32, c->intr_timer_usec,\n\t\tvnic_dev_get_intr_coal_timer_max(enic->vdev));\n\n\tdev_info(enic_get_dev(enic),\n\t\t\"vNIC MAC addr %02x:%02x:%02x:%02x:%02x:%02x \"\n\t\t\"wq/rq %d/%d mtu %d\\n\",\n\t\tenic->mac_addr[0], enic->mac_addr[1], enic->mac_addr[2],\n\t\tenic->mac_addr[3], enic->mac_addr[4], enic->mac_addr[5],\n\t\tc->wq_desc_count, c->rq_desc_count, c->mtu);\n\tdev_info(enic_get_dev(enic), \"vNIC csum tx/rx %s/%s \"\n\t\t\"rss %s intr mode %s type %s timer %d usec \"\n\t\t\"loopback tag 0x%04x\\n\",\n\t\tENIC_SETTING(enic, TXCSUM) ? \"yes\" : \"no\",\n\t\tENIC_SETTING(enic, RXCSUM) ? \"yes\" : \"no\",\n\t\tENIC_SETTING(enic, RSS) ? \"yes\" : \"no\",\n\t\tc->intr_mode == VENET_INTR_MODE_INTX ? \"INTx\" :\n\t\tc->intr_mode == VENET_INTR_MODE_MSI ? \"MSI\" :\n\t\tc->intr_mode == VENET_INTR_MODE_ANY ? \"any\" :\n\t\t\"unknown\",\n\t\tc->intr_timer_type == VENET_INTR_TYPE_MIN ? \"min\" :\n\t\tc->intr_timer_type == VENET_INTR_TYPE_IDLE ? \"idle\" :\n\t\t\"unknown\",\n\t\tc->intr_timer_usec,\n\t\tc->loop_tag);\n\n\treturn 0;\n}\n\nint enic_add_vlan(struct enic *enic, u16 vlanid)\n{\n\tu64 a0 = vlanid, a1 = 0;\n\tint wait = 1000;\n\tint err;\n\n\terr = vnic_dev_cmd(enic->vdev, CMD_VLAN_ADD, &a0, &a1, wait);\n\tif (err)\n\t\tdev_err(enic_get_dev(enic), \"Can't add vlan id, %d\\n\", err);\n\n\treturn err;\n}\n\nint enic_del_vlan(struct enic *enic, u16 vlanid)\n{\n\tu64 a0 = vlanid, a1 = 0;\n\tint wait = 1000;\n\tint err;\n\n\terr = vnic_dev_cmd(enic->vdev, CMD_VLAN_DEL, &a0, &a1, wait);\n\tif (err)\n\t\tdev_err(enic_get_dev(enic), \"Can't delete vlan id, %d\\n\", err);\n\n\treturn err;\n}\n\nint enic_set_nic_cfg(struct enic *enic, u8 rss_default_cpu, u8 rss_hash_type,\n\tu8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable, u8 tso_ipid_split_en,\n\tu8 ig_vlan_strip_en)\n{\n\tu64 a0, a1;\n\tu32 nic_cfg;\n\tint wait = 1000;\n\n\tvnic_set_nic_cfg(&nic_cfg, rss_default_cpu,\n\t\trss_hash_type, rss_hash_bits, rss_base_cpu,\n\t\trss_enable, tso_ipid_split_en, ig_vlan_strip_en);\n\n\ta0 = nic_cfg;\n\ta1 = 0;\n\n\treturn vnic_dev_cmd(enic->vdev, CMD_NIC_CFG, &a0, &a1, wait);\n}\n\nint enic_set_rss_key(struct enic *enic, dma_addr_t key_pa, u64 len)\n{\n\tu64 a0 = (u64)key_pa, a1 = len;\n\tint wait = 1000;\n\n\treturn vnic_dev_cmd(enic->vdev, CMD_RSS_KEY, &a0, &a1, wait);\n}\n\nint enic_set_rss_cpu(struct enic *enic, dma_addr_t cpu_pa, u64 len)\n{\n\tu64 a0 = (u64)cpu_pa, a1 = len;\n\tint wait = 1000;\n\n\treturn vnic_dev_cmd(enic->vdev, CMD_RSS_CPU, &a0, &a1, wait);\n}\n\nvoid enic_free_vnic_resources(struct enic *enic)\n{\n\tunsigned int i;\n\n\tfor (i = 0; i < enic->wq_count; i++)\n\t\tvnic_wq_free(&enic->wq[i]);\n\tfor (i = 0; i < enic->rq_count; i++)\n\t\tvnic_rq_free(&enic->rq[i]);\n\tfor (i = 0; i < enic->cq_count; i++)\n\t\tvnic_cq_free(&enic->cq[i]);\n\tvnic_intr_free(&enic->intr);\n}\n\nvoid enic_get_res_counts(struct enic *enic)\n{\n\tenic->wq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ);\n\tenic->rq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_RQ);\n\tenic->cq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_CQ);\n\tenic->intr_count = vnic_dev_get_res_count(enic->vdev,\n\t\tRES_TYPE_INTR_CTRL);\n\n\tdev_info(enic_get_dev(enic),\n\t\t\"vNIC resources avail: wq %d rq %d cq %d intr %d\\n\",\n\t\tenic->wq_count, enic->rq_count,\n\t\tenic->cq_count, enic->intr_count);\n}\n" }, { "path": "drivers/net/enic/enic_res.h", "content": "/*\n * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.\n * Copyright 2007 Nuova Systems, Inc. All rights reserved.\n *\n * Copyright (c) 2014, Cisco Systems, Inc.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ident \"$Id: enic_res.h 173137 2014-05-16 03:27:22Z sanpilla $\"\n\n#ifndef _ENIC_RES_H_\n#define _ENIC_RES_H_\n\n#include \"wq_enet_desc.h\"\n#include \"rq_enet_desc.h\"\n#include \"vnic_wq.h\"\n#include \"vnic_rq.h\"\n\n#define ENIC_MIN_WQ_DESCS\t\t64\n#define ENIC_MAX_WQ_DESCS\t\t4096\n#define ENIC_MIN_RQ_DESCS\t\t64\n#define ENIC_MAX_RQ_DESCS\t\t4096\n\n#define ENIC_MIN_MTU\t\t\t68\n#define ENIC_MAX_MTU\t\t\t9000\n\n#define ENIC_MULTICAST_PERFECT_FILTERS\t32\n#define ENIC_UNICAST_PERFECT_FILTERS\t32\n\n#define ENIC_NON_TSO_MAX_DESC\t\t16\n\n#define ENIC_SETTING(enic, f) ((enic->config.flags & VENETF_##f) ? 1 : 0)\n\nstatic inline void enic_queue_wq_desc_ex(struct vnic_wq *wq,\n\tvoid *os_buf, dma_addr_t dma_addr, unsigned int len,\n\tunsigned int mss_or_csum_offset, unsigned int hdr_len,\n\tint vlan_tag_insert, unsigned int vlan_tag,\n\tint offload_mode, int cq_entry, int sop, int eop, int loopback)\n{\n\tstruct wq_enet_desc *desc = vnic_wq_next_desc(wq);\n\tu8 desc_skip_cnt = 1;\n\tu8 compressed_send = 0;\n\tu64 wrid = 0;\n\n\twq_enet_desc_enc(desc,\n\t\t(u64)dma_addr | VNIC_PADDR_TARGET,\n\t\t(u16)len,\n\t\t(u16)mss_or_csum_offset,\n\t\t(u16)hdr_len, (u8)offload_mode,\n\t\t(u8)eop, (u8)cq_entry,\n\t\t0, /* fcoe_encap */\n\t\t(u8)vlan_tag_insert,\n\t\t(u16)vlan_tag,\n\t\t(u8)loopback);\n\n\tvnic_wq_post(wq, os_buf, dma_addr, len, sop, eop, desc_skip_cnt,\n\t\t\t(u8)cq_entry, compressed_send, wrid);\n}\n\nstatic inline void enic_queue_wq_desc_cont(struct vnic_wq *wq,\n\tvoid *os_buf, dma_addr_t dma_addr, unsigned int len,\n\tint eop, int loopback)\n{\n\tenic_queue_wq_desc_ex(wq, os_buf, dma_addr, len,\n\t\t0, 0, 0, 0, 0,\n\t\teop, 0 /* !SOP */, eop, loopback);\n}\n\nstatic inline void enic_queue_wq_desc(struct vnic_wq *wq, void *os_buf,\n\tdma_addr_t dma_addr, unsigned int len, int vlan_tag_insert,\n\tunsigned int vlan_tag, int eop, int loopback)\n{\n\tenic_queue_wq_desc_ex(wq, os_buf, dma_addr, len,\n\t\t0, 0, vlan_tag_insert, vlan_tag,\n\t\tWQ_ENET_OFFLOAD_MODE_CSUM,\n\t\teop, 1 /* SOP */, eop, loopback);\n}\n\nstatic inline void enic_queue_wq_desc_csum(struct vnic_wq *wq,\n\tvoid *os_buf, dma_addr_t dma_addr, unsigned int len,\n\tint ip_csum, int tcpudp_csum, int vlan_tag_insert,\n\tunsigned int vlan_tag, int eop, int loopback)\n{\n\tenic_queue_wq_desc_ex(wq, os_buf, dma_addr, len,\n\t\t(ip_csum ? 1 : 0) + (tcpudp_csum ? 2 : 0),\n\t\t0, vlan_tag_insert, vlan_tag,\n\t\tWQ_ENET_OFFLOAD_MODE_CSUM,\n\t\teop, 1 /* SOP */, eop, loopback);\n}\n\nstatic inline void enic_queue_wq_desc_csum_l4(struct vnic_wq *wq,\n\tvoid *os_buf, dma_addr_t dma_addr, unsigned int len,\n\tunsigned int csum_offset, unsigned int hdr_len,\n\tint vlan_tag_insert, unsigned int vlan_tag, int eop, int loopback)\n{\n\tenic_queue_wq_desc_ex(wq, os_buf, dma_addr, len,\n\t\tcsum_offset, hdr_len, vlan_tag_insert, vlan_tag,\n\t\tWQ_ENET_OFFLOAD_MODE_CSUM_L4,\n\t\teop, 1 /* SOP */, eop, loopback);\n}\n\nstatic inline void enic_queue_wq_desc_tso(struct vnic_wq *wq,\n\tvoid *os_buf, dma_addr_t dma_addr, unsigned int len,\n\tunsigned int mss, unsigned int hdr_len, int vlan_tag_insert,\n\tunsigned int vlan_tag, int eop, int loopback)\n{\n\tenic_queue_wq_desc_ex(wq, os_buf, dma_addr, len,\n\t\tmss, hdr_len, vlan_tag_insert, vlan_tag,\n\t\tWQ_ENET_OFFLOAD_MODE_TSO,\n\t\teop, 1 /* SOP */, eop, loopback);\n}\nstatic inline void enic_queue_rq_desc(struct vnic_rq *rq,\n\tvoid *os_buf, unsigned int os_buf_index,\n\tdma_addr_t dma_addr, unsigned int len)\n{\n\tstruct rq_enet_desc *desc = vnic_rq_next_desc(rq);\n\tu64 wrid = 0;\n\tu8 type = os_buf_index ?\n\t\tRQ_ENET_TYPE_NOT_SOP : RQ_ENET_TYPE_ONLY_SOP;\n\n\trq_enet_desc_enc(desc,\n\t\t(u64)dma_addr | VNIC_PADDR_TARGET,\n\t\ttype, (u16)len);\n\n\tvnic_rq_post(rq, os_buf, os_buf_index, dma_addr, len, wrid);\n}\n\nstruct enic;\n\nint enic_get_vnic_config(struct enic *);\nint enic_add_vlan(struct enic *enic, u16 vlanid);\nint enic_del_vlan(struct enic *enic, u16 vlanid);\nint enic_set_nic_cfg(struct enic *enic, u8 rss_default_cpu, u8 rss_hash_type,\n\tu8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable, u8 tso_ipid_split_en,\n\tu8 ig_vlan_strip_en);\nint enic_set_rss_key(struct enic *enic, dma_addr_t key_pa, u64 len);\nint enic_set_rss_cpu(struct enic *enic, dma_addr_t cpu_pa, u64 len);\nvoid enic_get_res_counts(struct enic *enic);\nvoid enic_init_vnic_resources(struct enic *enic);\nint enic_alloc_vnic_resources(struct enic *);\nvoid enic_free_vnic_resources(struct enic *);\n\n#endif /* _ENIC_RES_H_ */\n" }, { "path": "drivers/net/fm10k/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2013-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_fm10k.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_pmd_fm10k_version.map\n\nLIBABIVER := 1\n\nifeq ($(CC), icc)\n#\n# CFLAGS for icc\n#\nCFLAGS_BASE_DRIVER = -wd174 -wd593 -wd869 -wd981 -wd2259\n\nelse ifeq ($(CC), clang)\n#\n## CFLAGS for clang\n#\nCFLAGS_BASE_DRIVER = -Wno-unused-parameter -Wno-unused-value\nCFLAGS_BASE_DRIVER += -Wno-strict-aliasing -Wno-format-extra-args\nCFLAGS_BASE_DRIVER += -Wno-unused-variable\nCFLAGS_BASE_DRIVER += -Wno-missing-field-initializers\n\nelse\n#\n# CFLAGS for gcc\n#\nCFLAGS_BASE_DRIVER = -Wno-unused-parameter -Wno-unused-value\nCFLAGS_BASE_DRIVER += -Wno-strict-aliasing -Wno-format-extra-args\nCFLAGS_BASE_DRIVER += -Wno-unused-variable\nCFLAGS_BASE_DRIVER += -Wno-missing-field-initializers\n\nifeq ($(shell test $(GCC_VERSION) -ge 44 && echo 1), 1)\nCFLAGS += -Wno-deprecated\nCFLAGS_BASE_DRIVER += -Wno-unused-but-set-variable\nendif\nendif\n\n#\n# Add extra flags for base driver source files to disable warnings in them\n#\nBASE_DRIVER_OBJS=$(patsubst %.c,%.o,$(notdir $(wildcard $(SRCDIR)/base/*.c)))\n$(foreach obj, $(BASE_DRIVER_OBJS), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER)))\n\nVPATH += $(SRCDIR)/base\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_ethdev.c\nSRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_rxtx.c\n\nSRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_pf.c\nSRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_tlv.c\nSRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_common.c\nSRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_mbx.c\nSRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_vf.c\nSRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_api.c\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += lib/librte_eal lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += lib/librte_mempool lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += lib/librte_net\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/fm10k/base/fm10k_api.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"fm10k_api.h\"\n#include \"fm10k_common.h\"\n\n/**\n * fm10k_set_mac_type - Sets MAC type\n * @hw: pointer to the HW structure\n *\n * This function sets the mac type of the adapter based on the\n * vendor ID and device ID stored in the hw structure.\n **/\ns32 fm10k_set_mac_type(struct fm10k_hw *hw)\n{\n\ts32 ret_val = FM10K_SUCCESS;\n\n\tDEBUGFUNC(\"fm10k_set_mac_type\");\n\n\tif (hw->vendor_id != FM10K_INTEL_VENDOR_ID) {\n\t\tERROR_REPORT2(FM10K_ERROR_UNSUPPORTED,\n\t\t\t \"Unsupported vendor id: %x\\n\", hw->vendor_id);\n\t\treturn FM10K_ERR_DEVICE_NOT_SUPPORTED;\n\t}\n\n\tswitch (hw->device_id) {\n\tcase FM10K_DEV_ID_PF:\n\t\thw->mac.type = fm10k_mac_pf;\n\t\tbreak;\n\tcase FM10K_DEV_ID_VF:\n\t\thw->mac.type = fm10k_mac_vf;\n\t\tbreak;\n\tdefault:\n\t\tret_val = FM10K_ERR_DEVICE_NOT_SUPPORTED;\n\t\tERROR_REPORT2(FM10K_ERROR_UNSUPPORTED,\n\t\t\t \"Unsupported device id: %x\\n\",\n\t\t\t hw->device_id);\n\t\tbreak;\n\t}\n\n\tDEBUGOUT2(\"fm10k_set_mac_type found mac: %d, returns: %d\\n\",\n\t\t hw->mac.type, ret_val);\n\n\treturn ret_val;\n}\n\n/**\n * fm10k_init_shared_code - Initialize the shared code\n * @hw: pointer to hardware structure\n *\n * This will assign function pointers and assign the MAC type and PHY code.\n * Does not touch the hardware. This function must be called prior to any\n * other function in the shared code. The fm10k_hw structure should be\n * memset to 0 prior to calling this function. The following fields in\n * hw structure should be filled in prior to calling this function:\n * hw_addr, back, device_id, vendor_id, subsystem_device_id,\n * subsystem_vendor_id, and revision_id\n **/\ns32 fm10k_init_shared_code(struct fm10k_hw *hw)\n{\n\ts32 status;\n\n\tDEBUGFUNC(\"fm10k_init_shared_code\");\n\n\t/* Set the mac type */\n\tfm10k_set_mac_type(hw);\n\n\tswitch (hw->mac.type) {\n\tcase fm10k_mac_pf:\n\t\tstatus = fm10k_init_ops_pf(hw);\n\t\tbreak;\n\tcase fm10k_mac_vf:\n\t\tstatus = fm10k_init_ops_vf(hw);\n\t\tbreak;\n\tdefault:\n\t\tstatus = FM10K_ERR_DEVICE_NOT_SUPPORTED;\n\t\tbreak;\n\t}\n\n\treturn status;\n}\n\n#define fm10k_call_func(hw, func, params, error) \\\n\t\t ((func) ? (func params) : (error))\n\n/**\n * fm10k_reset_hw - Reset the hardware to known good state\n * @hw: pointer to hardware structure\n *\n * This function should return the hardware to a state similar to the\n * one it is in after being powered on.\n **/\ns32 fm10k_reset_hw(struct fm10k_hw *hw)\n{\n\treturn fm10k_call_func(hw, hw->mac.ops.reset_hw, (hw),\n\t\t\t FM10K_NOT_IMPLEMENTED);\n}\n\n/**\n * fm10k_init_hw - Initialize the hardware\n * @hw: pointer to hardware structure\n *\n * Initialize the hardware by resetting and then starting the hardware\n **/\ns32 fm10k_init_hw(struct fm10k_hw *hw)\n{\n\treturn fm10k_call_func(hw, hw->mac.ops.init_hw, (hw),\n\t\t\t FM10K_NOT_IMPLEMENTED);\n}\n\n/**\n * fm10k_stop_hw - Prepares hardware to shutdown Rx/Tx\n * @hw: pointer to hardware structure\n *\n * Disables Rx/Tx queues and disables the DMA engine.\n **/\ns32 fm10k_stop_hw(struct fm10k_hw *hw)\n{\n\treturn fm10k_call_func(hw, hw->mac.ops.stop_hw, (hw),\n\t\t\t FM10K_NOT_IMPLEMENTED);\n}\n\n/**\n * fm10k_start_hw - Prepares hardware for Rx/Tx\n * @hw: pointer to hardware structure\n *\n * This function sets the flags indicating that the hardware is ready to\n * begin operation.\n **/\ns32 fm10k_start_hw(struct fm10k_hw *hw)\n{\n\treturn fm10k_call_func(hw, hw->mac.ops.start_hw, (hw),\n\t\t\t FM10K_NOT_IMPLEMENTED);\n}\n\n/**\n * fm10k_get_bus_info - Set PCI bus info\n * @hw: pointer to hardware structure\n *\n * Sets the PCI bus info (speed, width, type) within the fm10k_hw structure\n **/\ns32 fm10k_get_bus_info(struct fm10k_hw *hw)\n{\n\treturn fm10k_call_func(hw, hw->mac.ops.get_bus_info, (hw),\n\t\t\t FM10K_NOT_IMPLEMENTED);\n}\n\n/**\n * fm10k_is_slot_appropriate - Indicate appropriate slot for this SKU\n * @hw: pointer to hardware structure\n *\n * Looks at the PCIe bus info to confirm whether or not this slot can support\n * the necessary bandwidth for this device.\n **/\nbool fm10k_is_slot_appropriate(struct fm10k_hw *hw)\n{\n\tif (hw->mac.ops.is_slot_appropriate)\n\t\treturn hw->mac.ops.is_slot_appropriate(hw);\n\treturn true;\n}\n\n/**\n * fm10k_update_vlan - Clear VLAN ID to VLAN filter table\n * @hw: pointer to hardware structure\n * @vid: VLAN ID to add to table\n * @idx: Index indicating VF ID or PF ID in table\n * @set: Indicates if this is a set or clear operation\n *\n * This function adds or removes the corresponding VLAN ID from the VLAN\n * filter table for the corresponding function.\n **/\ns32 fm10k_update_vlan(struct fm10k_hw *hw, u32 vid, u8 idx, bool set)\n{\n\treturn fm10k_call_func(hw, hw->mac.ops.update_vlan, (hw, vid, idx, set),\n\t\t\t FM10K_NOT_IMPLEMENTED);\n}\n\n/**\n * fm10k_read_mac_addr - Reads MAC address\n * @hw: pointer to hardware structure\n *\n * Reads the MAC address out of the interface and stores it in the HW\n * structures.\n **/\ns32 fm10k_read_mac_addr(struct fm10k_hw *hw)\n{\n\treturn fm10k_call_func(hw, hw->mac.ops.read_mac_addr, (hw),\n\t\t\t FM10K_NOT_IMPLEMENTED);\n}\n\n/**\n * fm10k_update_hw_stats - Update hw statistics\n * @hw: pointer to hardware structure\n *\n * This function updates statistics that are related to hardware.\n * */\nvoid fm10k_update_hw_stats(struct fm10k_hw *hw, struct fm10k_hw_stats *stats)\n{\n\tif (hw->mac.ops.update_hw_stats)\n\t\thw->mac.ops.update_hw_stats(hw, stats);\n}\n\n/**\n * fm10k_rebind_hw_stats - Reset base for hw statistics\n * @hw: pointer to hardware structure\n *\n * This function resets the base for statistics that are related to hardware.\n * */\nvoid fm10k_rebind_hw_stats(struct fm10k_hw *hw, struct fm10k_hw_stats *stats)\n{\n\tif (hw->mac.ops.rebind_hw_stats)\n\t\thw->mac.ops.rebind_hw_stats(hw, stats);\n}\n\n/**\n * fm10k_configure_dglort_map - Configures GLORT entry and queues\n * @hw: pointer to hardware structure\n * @dglort: pointer to dglort configuration structure\n *\n * Reads the configuration structure contained in dglort_cfg and uses\n * that information to then populate a DGLORTMAP/DEC entry and the queues\n * to which it has been assigned.\n **/\ns32 fm10k_configure_dglort_map(struct fm10k_hw *hw,\n\t\t\t struct fm10k_dglort_cfg *dglort)\n{\n\treturn fm10k_call_func(hw, hw->mac.ops.configure_dglort_map,\n\t\t\t (hw, dglort), FM10K_NOT_IMPLEMENTED);\n}\n\n/**\n * fm10k_set_dma_mask - Configures PhyAddrSpace to limit DMA to system\n * @hw: pointer to hardware structure\n * @dma_mask: 64 bit DMA mask required for platform\n *\n * This function configures the endpoint to limit the access to memory\n * beyond what is physically in the system.\n **/\nvoid fm10k_set_dma_mask(struct fm10k_hw *hw, u64 dma_mask)\n{\n\tif (hw->mac.ops.set_dma_mask)\n\t\thw->mac.ops.set_dma_mask(hw, dma_mask);\n}\n\n/**\n * fm10k_get_fault - Record a fault in one of the interface units\n * @hw: pointer to hardware structure\n * @type: pointer to fault type register offset\n * @fault: pointer to memory location to record the fault\n *\n * Record the fault register contents to the fault data structure and\n * clear the entry from the register.\n *\n * Returns ERR_PARAM if invalid register is specified or no error is present.\n **/\ns32 fm10k_get_fault(struct fm10k_hw *hw, int type, struct fm10k_fault *fault)\n{\n\treturn fm10k_call_func(hw, hw->mac.ops.get_fault, (hw, type, fault),\n\t\t\t FM10K_NOT_IMPLEMENTED);\n}\n\n/**\n * fm10k_update_uc_addr - Update device unicast address\n * @hw: pointer to the HW structure\n * @lport: logical port ID to update - unused\n * @mac: MAC address to add/remove from table\n * @vid: VLAN ID to add/remove from table\n * @add: Indicates if this is an add or remove operation\n * @flags: flags field to indicate add and secure - unused\n *\n * This function is used to add or remove unicast MAC addresses\n **/\ns32 fm10k_update_uc_addr(struct fm10k_hw *hw, u16 lport,\n\t\t\t const u8 *mac, u16 vid, bool add, u8 flags)\n{\n\treturn fm10k_call_func(hw, hw->mac.ops.update_uc_addr,\n\t\t\t (hw, lport, mac, vid, add, flags),\n\t\t\t FM10K_NOT_IMPLEMENTED);\n}\n\n/**\n * fm10k_update_mc_addr - Update device multicast address\n * @hw: pointer to the HW structure\n * @lport: logical port ID to update - unused\n * @mac: MAC address to add/remove from table\n * @vid: VLAN ID to add/remove from table\n * @add: Indicates if this is an add or remove operation\n *\n * This function is used to add or remove multicast MAC addresses\n **/\ns32 fm10k_update_mc_addr(struct fm10k_hw *hw, u16 lport,\n\t\t\t const u8 *mac, u16 vid, bool add)\n{\n\treturn fm10k_call_func(hw, hw->mac.ops.update_mc_addr,\n\t\t\t (hw, lport, mac, vid, add),\n\t\t\t FM10K_NOT_IMPLEMENTED);\n}\n\n/**\n * fm10k_adjust_systime - Adjust systime frequency\n * @hw: pointer to hardware structure\n * @ppb: adjustment rate in parts per billion\n *\n * This function is meant to update the frequency of the clock represented\n * by the SYSTIME register.\n **/\ns32 fm10k_adjust_systime(struct fm10k_hw *hw, s32 ppb)\n{\n\treturn fm10k_call_func(hw, hw->mac.ops.adjust_systime,\n\t\t\t (hw, ppb), FM10K_NOT_IMPLEMENTED);\n}\n" }, { "path": "drivers/net/fm10k/base/fm10k_api.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _FM10K_API_H_\n#define _FM10K_API_H_\n\n#include \"fm10k_pf.h\"\n#include \"fm10k_vf.h\"\n\ns32 fm10k_set_mac_type(struct fm10k_hw *hw);\ns32 fm10k_reset_hw(struct fm10k_hw *hw);\ns32 fm10k_init_hw(struct fm10k_hw *hw);\ns32 fm10k_stop_hw(struct fm10k_hw *hw);\ns32 fm10k_start_hw(struct fm10k_hw *hw);\ns32 fm10k_init_shared_code(struct fm10k_hw *hw);\ns32 fm10k_get_bus_info(struct fm10k_hw *hw);\nbool fm10k_is_slot_appropriate(struct fm10k_hw *hw);\ns32 fm10k_update_vlan(struct fm10k_hw *hw, u32 vid, u8 idx, bool set);\ns32 fm10k_read_mac_addr(struct fm10k_hw *hw);\nvoid fm10k_update_hw_stats(struct fm10k_hw *hw, struct fm10k_hw_stats *stats);\nvoid fm10k_rebind_hw_stats(struct fm10k_hw *hw, struct fm10k_hw_stats *stats);\ns32 fm10k_configure_dglort_map(struct fm10k_hw *hw,\n\t\t\t struct fm10k_dglort_cfg *dglort);\nvoid fm10k_set_dma_mask(struct fm10k_hw *hw, u64 dma_mask);\ns32 fm10k_get_fault(struct fm10k_hw *hw, int type, struct fm10k_fault *fault);\ns32 fm10k_update_uc_addr(struct fm10k_hw *hw, u16 lport,\n\t\t\t const u8 *mac, u16 vid, bool add, u8 flags);\ns32 fm10k_update_mc_addr(struct fm10k_hw *hw, u16 lport,\n\t\t\t const u8 *mac, u16 vid, bool add);\ns32 fm10k_adjust_systime(struct fm10k_hw *hw, s32 ppb);\n#endif /* _FM10K_API_H_ */\n" }, { "path": "drivers/net/fm10k/base/fm10k_common.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"fm10k_common.h\"\n\n/**\n * fm10k_get_bus_info_generic - Generic set PCI bus info\n * @hw: pointer to hardware structure\n *\n * Gets the PCI bus info (speed, width, type) then calls helper function to\n * store this data within the fm10k_hw structure.\n **/\nSTATIC s32 fm10k_get_bus_info_generic(struct fm10k_hw *hw)\n{\n\tu16 link_cap, link_status, device_cap, device_control;\n\n\tDEBUGFUNC(\"fm10k_get_bus_info_generic\");\n\n\t/* Get the maximum link width and speed from PCIe config space */\n\tlink_cap = FM10K_READ_PCI_WORD(hw, FM10K_PCIE_LINK_CAP);\n\n\tswitch (link_cap & FM10K_PCIE_LINK_WIDTH) {\n\tcase FM10K_PCIE_LINK_WIDTH_1:\n\t\thw->bus_caps.width = fm10k_bus_width_pcie_x1;\n\t\tbreak;\n\tcase FM10K_PCIE_LINK_WIDTH_2:\n\t\thw->bus_caps.width = fm10k_bus_width_pcie_x2;\n\t\tbreak;\n\tcase FM10K_PCIE_LINK_WIDTH_4:\n\t\thw->bus_caps.width = fm10k_bus_width_pcie_x4;\n\t\tbreak;\n\tcase FM10K_PCIE_LINK_WIDTH_8:\n\t\thw->bus_caps.width = fm10k_bus_width_pcie_x8;\n\t\tbreak;\n\tdefault:\n\t\thw->bus_caps.width = fm10k_bus_width_unknown;\n\t\tbreak;\n\t}\n\n\tswitch (link_cap & FM10K_PCIE_LINK_SPEED) {\n\tcase FM10K_PCIE_LINK_SPEED_2500:\n\t\thw->bus_caps.speed = fm10k_bus_speed_2500;\n\t\tbreak;\n\tcase FM10K_PCIE_LINK_SPEED_5000:\n\t\thw->bus_caps.speed = fm10k_bus_speed_5000;\n\t\tbreak;\n\tcase FM10K_PCIE_LINK_SPEED_8000:\n\t\thw->bus_caps.speed = fm10k_bus_speed_8000;\n\t\tbreak;\n\tdefault:\n\t\thw->bus_caps.speed = fm10k_bus_speed_unknown;\n\t\tbreak;\n\t}\n\n\t/* Get the PCIe maximum payload size for the PCIe function */\n\tdevice_cap = FM10K_READ_PCI_WORD(hw, FM10K_PCIE_DEV_CAP);\n\n\tswitch (device_cap & FM10K_PCIE_DEV_CAP_PAYLOAD) {\n\tcase FM10K_PCIE_DEV_CAP_PAYLOAD_128:\n\t\thw->bus_caps.payload = fm10k_bus_payload_128;\n\t\tbreak;\n\tcase FM10K_PCIE_DEV_CAP_PAYLOAD_256:\n\t\thw->bus_caps.payload = fm10k_bus_payload_256;\n\t\tbreak;\n\tcase FM10K_PCIE_DEV_CAP_PAYLOAD_512:\n\t\thw->bus_caps.payload = fm10k_bus_payload_512;\n\t\tbreak;\n\tdefault:\n\t\thw->bus_caps.payload = fm10k_bus_payload_unknown;\n\t\tbreak;\n\t}\n\n\t/* Get the negotiated link width and speed from PCIe config space */\n\tlink_status = FM10K_READ_PCI_WORD(hw, FM10K_PCIE_LINK_STATUS);\n\n\tswitch (link_status & FM10K_PCIE_LINK_WIDTH) {\n\tcase FM10K_PCIE_LINK_WIDTH_1:\n\t\thw->bus.width = fm10k_bus_width_pcie_x1;\n\t\tbreak;\n\tcase FM10K_PCIE_LINK_WIDTH_2:\n\t\thw->bus.width = fm10k_bus_width_pcie_x2;\n\t\tbreak;\n\tcase FM10K_PCIE_LINK_WIDTH_4:\n\t\thw->bus.width = fm10k_bus_width_pcie_x4;\n\t\tbreak;\n\tcase FM10K_PCIE_LINK_WIDTH_8:\n\t\thw->bus.width = fm10k_bus_width_pcie_x8;\n\t\tbreak;\n\tdefault:\n\t\thw->bus.width = fm10k_bus_width_unknown;\n\t\tbreak;\n\t}\n\n\tswitch (link_status & FM10K_PCIE_LINK_SPEED) {\n\tcase FM10K_PCIE_LINK_SPEED_2500:\n\t\thw->bus.speed = fm10k_bus_speed_2500;\n\t\tbreak;\n\tcase FM10K_PCIE_LINK_SPEED_5000:\n\t\thw->bus.speed = fm10k_bus_speed_5000;\n\t\tbreak;\n\tcase FM10K_PCIE_LINK_SPEED_8000:\n\t\thw->bus.speed = fm10k_bus_speed_8000;\n\t\tbreak;\n\tdefault:\n\t\thw->bus.speed = fm10k_bus_speed_unknown;\n\t\tbreak;\n\t}\n\n\t/* Get the negotiated PCIe maximum payload size for the PCIe function */\n\tdevice_control = FM10K_READ_PCI_WORD(hw, FM10K_PCIE_DEV_CTRL);\n\n\tswitch (device_control & FM10K_PCIE_DEV_CTRL_PAYLOAD) {\n\tcase FM10K_PCIE_DEV_CTRL_PAYLOAD_128:\n\t\thw->bus.payload = fm10k_bus_payload_128;\n\t\tbreak;\n\tcase FM10K_PCIE_DEV_CTRL_PAYLOAD_256:\n\t\thw->bus.payload = fm10k_bus_payload_256;\n\t\tbreak;\n\tcase FM10K_PCIE_DEV_CTRL_PAYLOAD_512:\n\t\thw->bus.payload = fm10k_bus_payload_512;\n\t\tbreak;\n\tdefault:\n\t\thw->bus.payload = fm10k_bus_payload_unknown;\n\t\tbreak;\n\t}\n\n\treturn FM10K_SUCCESS;\n}\n\nu16 fm10k_get_pcie_msix_count_generic(struct fm10k_hw *hw)\n{\n\tu16 msix_count;\n\n\tDEBUGFUNC(\"fm10k_get_pcie_msix_count_generic\");\n\n\t/* read in value from MSI-X capability register */\n\tmsix_count = FM10K_READ_PCI_WORD(hw, FM10K_PCI_MSIX_MSG_CTRL);\n\tmsix_count &= FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK;\n\n\t/* MSI-X count is zero-based in HW */\n\tmsix_count++;\n\n\tif (msix_count > FM10K_MAX_MSIX_VECTORS)\n\t\tmsix_count = FM10K_MAX_MSIX_VECTORS;\n\n\treturn msix_count;\n}\n\n/**\n * fm10k_init_ops_generic - Inits function ptrs\n * @hw: pointer to the hardware structure\n *\n * Initialize the function pointers.\n **/\ns32 fm10k_init_ops_generic(struct fm10k_hw *hw)\n{\n\tstruct fm10k_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"fm10k_init_ops_generic\");\n\n\t/* MAC */\n\tmac->ops.get_bus_info = &fm10k_get_bus_info_generic;\n\n\t/* initialize GLORT state to avoid any false hits */\n\tmac->dglort_map = FM10K_DGLORTMAP_NONE;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_start_hw_generic - Prepare hardware for Tx/Rx\n * @hw: pointer to hardware structure\n *\n * This function sets the Tx ready flag to indicate that the Tx path has\n * been initialized.\n **/\ns32 fm10k_start_hw_generic(struct fm10k_hw *hw)\n{\n\tDEBUGFUNC(\"fm10k_start_hw_generic\");\n\n\t/* set flag indicating we are beginning Tx */\n\thw->mac.tx_ready = true;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_disable_queues_generic - Stop Tx/Rx queues\n * @hw: pointer to hardware structure\n * @q_cnt: number of queues to be disabled\n *\n **/\ns32 fm10k_disable_queues_generic(struct fm10k_hw *hw, u16 q_cnt)\n{\n\tu32 reg;\n\tu16 i, time;\n\n\tDEBUGFUNC(\"fm10k_disable_queues_generic\");\n\n\t/* clear tx_ready to prevent any false hits for reset */\n\thw->mac.tx_ready = false;\n\n\t/* clear the enable bit for all rings */\n\tfor (i = 0; i < q_cnt; i++) {\n\t\treg = FM10K_READ_REG(hw, FM10K_TXDCTL(i));\n\t\tFM10K_WRITE_REG(hw, FM10K_TXDCTL(i),\n\t\t\t\treg & ~FM10K_TXDCTL_ENABLE);\n\t\treg = FM10K_READ_REG(hw, FM10K_RXQCTL(i));\n\t\tFM10K_WRITE_REG(hw, FM10K_RXQCTL(i),\n\t\t\t\treg & ~FM10K_RXQCTL_ENABLE);\n\t}\n\n\tFM10K_WRITE_FLUSH(hw);\n\tusec_delay(1);\n\n\t/* loop through all queues to verify that they are all disabled */\n\tfor (i = 0, time = FM10K_QUEUE_DISABLE_TIMEOUT; time;) {\n\t\t/* if we are at end of rings all rings are disabled */\n\t\tif (i == q_cnt)\n\t\t\treturn FM10K_SUCCESS;\n\n\t\t/* if queue enables cleared, then move to next ring pair */\n\t\treg = FM10K_READ_REG(hw, FM10K_TXDCTL(i));\n\t\tif (!~reg || !(reg & FM10K_TXDCTL_ENABLE)) {\n\t\t\treg = FM10K_READ_REG(hw, FM10K_RXQCTL(i));\n\t\t\tif (!~reg || !(reg & FM10K_RXQCTL_ENABLE)) {\n\t\t\t\ti++;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\n\t\t/* decrement time and wait 1 usec */\n\t\ttime--;\n\t\tif (time)\n\t\t\tusec_delay(1);\n\t}\n\n\treturn FM10K_ERR_REQUESTS_PENDING;\n}\n\n/**\n * fm10k_stop_hw_generic - Stop Tx/Rx units\n * @hw: pointer to hardware structure\n *\n **/\ns32 fm10k_stop_hw_generic(struct fm10k_hw *hw)\n{\n\tDEBUGFUNC(\"fm10k_stop_hw_generic\");\n\n\treturn fm10k_disable_queues_generic(hw, hw->mac.max_queues);\n}\n\n/**\n * fm10k_read_hw_stats_32b - Reads value of 32-bit registers\n * @hw: pointer to the hardware structure\n * @addr: address of register containing a 32-bit value\n *\n * Function reads the content of the register and returns the delta\n * between the base and the current value.\n * **/\nu32 fm10k_read_hw_stats_32b(struct fm10k_hw *hw, u32 addr,\n\t\t\t struct fm10k_hw_stat *stat)\n{\n\tu32 delta = FM10K_READ_REG(hw, addr) - stat->base_l;\n\n\tDEBUGFUNC(\"fm10k_read_hw_stats_32b\");\n\n\tif (FM10K_REMOVED(hw->hw_addr))\n\t\tstat->base_h = 0;\n\n\treturn delta;\n}\n\n/**\n * fm10k_read_hw_stats_48b - Reads value of 48-bit registers\n * @hw: pointer to the hardware structure\n * @addr: address of register containing the lower 32-bit value\n *\n * Function reads the content of 2 registers, combined to represent a 48-bit\n * statistical value. Extra processing is required to handle overflowing.\n * Finally, a delta value is returned representing the difference between the\n * values stored in registers and values stored in the statistic counters.\n * **/\nSTATIC u64 fm10k_read_hw_stats_48b(struct fm10k_hw *hw, u32 addr,\n\t\t\t\t struct fm10k_hw_stat *stat)\n{\n\tu32 count_l;\n\tu32 count_h;\n\tu32 count_tmp;\n\tu64 delta;\n\n\tDEBUGFUNC(\"fm10k_read_hw_stats_48b\");\n\n\tcount_h = FM10K_READ_REG(hw, addr + 1);\n\n\t/* Check for overflow */\n\tdo {\n\t\tcount_tmp = count_h;\n\t\tcount_l = FM10K_READ_REG(hw, addr);\n\t\tcount_h = FM10K_READ_REG(hw, addr + 1);\n\t} while (count_h != count_tmp);\n\n\tdelta = ((u64)(count_h - stat->base_h) << 32) + count_l;\n\tdelta -= stat->base_l;\n\n\treturn delta & FM10K_48_BIT_MASK;\n}\n\n/**\n * fm10k_update_hw_base_48b - Updates 48-bit statistic base value\n * @stat: pointer to the hardware statistic structure\n * @delta: value to be updated into the hardware statistic structure\n *\n * Function receives a value and determines if an update is required based on\n * a delta calculation. Only the base value will be updated.\n **/\nSTATIC void fm10k_update_hw_base_48b(struct fm10k_hw_stat *stat, u64 delta)\n{\n\tDEBUGFUNC(\"fm10k_update_hw_base_48b\");\n\n\tif (!delta)\n\t\treturn;\n\n\t/* update lower 32 bits */\n\tdelta += stat->base_l;\n\tstat->base_l = (u32)delta;\n\n\t/* update upper 32 bits */\n\tstat->base_h += (u32)(delta >> 32);\n}\n\n/**\n * fm10k_update_hw_stats_tx_q - Updates TX queue statistics counters\n * @hw: pointer to the hardware structure\n * @q: pointer to the ring of hardware statistics queue\n * @idx: index pointing to the start of the ring iteration\n *\n * Function updates the TX queue statistics counters that are related to the\n * hardware.\n **/\nSTATIC void fm10k_update_hw_stats_tx_q(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_hw_stats_q *q,\n\t\t\t\t u32 idx)\n{\n\tu32 id_tx, id_tx_prev, tx_packets;\n\tu64 tx_bytes = 0;\n\n\tDEBUGFUNC(\"fm10k_update_hw_stats_tx_q\");\n\n\t/* Retrieve TX Owner Data */\n\tid_tx = FM10K_READ_REG(hw, FM10K_TXQCTL(idx));\n\n\t/* Process TX Ring */\n\tdo {\n\t\ttx_packets = fm10k_read_hw_stats_32b(hw, FM10K_QPTC(idx),\n\t\t\t\t\t\t &q->tx_packets);\n\n\t\tif (tx_packets)\n\t\t\ttx_bytes = fm10k_read_hw_stats_48b(hw,\n\t\t\t\t\t\t\t FM10K_QBTC_L(idx),\n\t\t\t\t\t\t\t &q->tx_bytes);\n\n\t\t/* Re-Check Owner Data */\n\t\tid_tx_prev = id_tx;\n\t\tid_tx = FM10K_READ_REG(hw, FM10K_TXQCTL(idx));\n\t} while ((id_tx ^ id_tx_prev) & FM10K_TXQCTL_ID_MASK);\n\n\t/* drop non-ID bits and set VALID ID bit */\n\tid_tx &= FM10K_TXQCTL_ID_MASK;\n\tid_tx |= FM10K_STAT_VALID;\n\n\t/* update packet counts */\n\tif (q->tx_stats_idx == id_tx) {\n\t\tq->tx_packets.count += tx_packets;\n\t\tq->tx_bytes.count += tx_bytes;\n\t}\n\n\t/* update bases and record ID */\n\tfm10k_update_hw_base_32b(&q->tx_packets, tx_packets);\n\tfm10k_update_hw_base_48b(&q->tx_bytes, tx_bytes);\n\n\tq->tx_stats_idx = id_tx;\n}\n\n/**\n * fm10k_update_hw_stats_rx_q - Updates RX queue statistics counters\n * @hw: pointer to the hardware structure\n * @q: pointer to the ring of hardware statistics queue\n * @idx: index pointing to the start of the ring iteration\n *\n * Function updates the RX queue statistics counters that are related to the\n * hardware.\n **/\nSTATIC void fm10k_update_hw_stats_rx_q(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_hw_stats_q *q,\n\t\t\t\t u32 idx)\n{\n\tu32 id_rx, id_rx_prev, rx_packets, rx_drops;\n\tu64 rx_bytes = 0;\n\n\tDEBUGFUNC(\"fm10k_update_hw_stats_rx_q\");\n\n\t/* Retrieve RX Owner Data */\n\tid_rx = FM10K_READ_REG(hw, FM10K_RXQCTL(idx));\n\n\t/* Process RX Ring */\n\tdo {\n\t\trx_drops = fm10k_read_hw_stats_32b(hw, FM10K_QPRDC(idx),\n\t\t\t\t\t\t &q->rx_drops);\n\n\t\trx_packets = fm10k_read_hw_stats_32b(hw, FM10K_QPRC(idx),\n\t\t\t\t\t\t &q->rx_packets);\n\n\t\tif (rx_packets)\n\t\t\trx_bytes = fm10k_read_hw_stats_48b(hw,\n\t\t\t\t\t\t\t FM10K_QBRC_L(idx),\n\t\t\t\t\t\t\t &q->rx_bytes);\n\n\t\t/* Re-Check Owner Data */\n\t\tid_rx_prev = id_rx;\n\t\tid_rx = FM10K_READ_REG(hw, FM10K_RXQCTL(idx));\n\t} while ((id_rx ^ id_rx_prev) & FM10K_RXQCTL_ID_MASK);\n\n\t/* drop non-ID bits and set VALID ID bit */\n\tid_rx &= FM10K_RXQCTL_ID_MASK;\n\tid_rx |= FM10K_STAT_VALID;\n\n\t/* update packet counts */\n\tif (q->rx_stats_idx == id_rx) {\n\t\tq->rx_drops.count += rx_drops;\n\t\tq->rx_packets.count += rx_packets;\n\t\tq->rx_bytes.count += rx_bytes;\n\t}\n\n\t/* update bases and record ID */\n\tfm10k_update_hw_base_32b(&q->rx_drops, rx_drops);\n\tfm10k_update_hw_base_32b(&q->rx_packets, rx_packets);\n\tfm10k_update_hw_base_48b(&q->rx_bytes, rx_bytes);\n\n\tq->rx_stats_idx = id_rx;\n}\n\n/**\n * fm10k_update_hw_stats_q - Updates queue statistics counters\n * @hw: pointer to the hardware structure\n * @q: pointer to the ring of hardware statistics queue\n * @idx: index pointing to the start of the ring iteration\n * @count: number of queues to iterate over\n *\n * Function updates the queue statistics counters that are related to the\n * hardware.\n **/\nvoid fm10k_update_hw_stats_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q,\n\t\t\t u32 idx, u32 count)\n{\n\tu32 i;\n\n\tDEBUGFUNC(\"fm10k_update_hw_stats_q\");\n\n\tfor (i = 0; i < count; i++, idx++, q++) {\n\t\tfm10k_update_hw_stats_tx_q(hw, q, idx);\n\t\tfm10k_update_hw_stats_rx_q(hw, q, idx);\n\t}\n}\n\n/**\n * fm10k_unbind_hw_stats_q - Unbind the queue counters from their queues\n * @hw: pointer to the hardware structure\n * @q: pointer to the ring of hardware statistics queue\n * @idx: index pointing to the start of the ring iteration\n * @count: number of queues to iterate over\n *\n * Function invalidates the index values for the queues so any updates that\n * may have happened are ignored and the base for the queue stats is reset.\n **/\nvoid fm10k_unbind_hw_stats_q(struct fm10k_hw_stats_q *q, u32 idx, u32 count)\n{\n\tu32 i;\n\n\tfor (i = 0; i < count; i++, idx++, q++) {\n\t\tq->rx_stats_idx = 0;\n\t\tq->tx_stats_idx = 0;\n\t}\n}\n\n/**\n * fm10k_get_host_state_generic - Returns the state of the host\n * @hw: pointer to hardware structure\n * @host_ready: pointer to boolean value that will record host state\n *\n * This function will check the health of the mailbox and Tx queue 0\n * in order to determine if we should report that the link is up or not.\n **/\ns32 fm10k_get_host_state_generic(struct fm10k_hw *hw, bool *host_ready)\n{\n\tstruct fm10k_mbx_info *mbx = &hw->mbx;\n\tstruct fm10k_mac_info *mac = &hw->mac;\n\ts32 ret_val = FM10K_SUCCESS;\n\tu32 txdctl = FM10K_READ_REG(hw, FM10K_TXDCTL(0));\n\n\tDEBUGFUNC(\"fm10k_get_host_state_generic\");\n\n\t/* process upstream mailbox in case interrupts were disabled */\n\tmbx->ops.process(hw, mbx);\n\n\t/* If Tx is no longer enabled link should come down */\n\tif (!(~txdctl) || !(txdctl & FM10K_TXDCTL_ENABLE))\n\t\tmac->get_host_state = true;\n\n\t/* exit if not checking for link, or link cannot be changed */\n\tif (!mac->get_host_state || !(~txdctl))\n\t\tgoto out;\n\n\t/* if we somehow dropped the Tx enable we should reset */\n\tif (hw->mac.tx_ready && !(txdctl & FM10K_TXDCTL_ENABLE)) {\n\t\tret_val = FM10K_ERR_RESET_REQUESTED;\n\t\tgoto out;\n\t}\n\n\t/* if Mailbox timed out we should request reset */\n\tif (!mbx->timeout) {\n\t\tret_val = FM10K_ERR_RESET_REQUESTED;\n\t\tgoto out;\n\t}\n\n\t/* verify Mailbox is still valid */\n\tif (!mbx->ops.tx_ready(mbx, FM10K_VFMBX_MSG_MTU))\n\t\tgoto out;\n\n\t/* interface cannot receive traffic without logical ports */\n\tif (mac->dglort_map == FM10K_DGLORTMAP_NONE)\n\t\tgoto out;\n\n\t/* if we passed all the tests above then the switch is ready and we no\n\t * longer need to check for link\n\t */\n\tmac->get_host_state = false;\n\nout:\n\t*host_ready = !mac->get_host_state;\n\treturn ret_val;\n}\n" }, { "path": "drivers/net/fm10k/base/fm10k_common.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _FM10K_COMMON_H_\n#define _FM10K_COMMON_H_\n\n#include \"fm10k_type.h\"\n\nu16 fm10k_get_pcie_msix_count_generic(struct fm10k_hw *hw);\ns32 fm10k_init_ops_generic(struct fm10k_hw *hw);\ns32 fm10k_disable_queues_generic(struct fm10k_hw *hw, u16 q_cnt);\ns32 fm10k_start_hw_generic(struct fm10k_hw *hw);\ns32 fm10k_stop_hw_generic(struct fm10k_hw *hw);\nu32 fm10k_read_hw_stats_32b(struct fm10k_hw *hw, u32 addr,\n\t\t\t struct fm10k_hw_stat *stat);\n#define fm10k_update_hw_base_32b(stat, delta) ((stat)->base_l += (delta))\nvoid fm10k_update_hw_stats_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q,\n\t\t\t u32 idx, u32 count);\n#define fm10k_unbind_hw_stats_32b(s) ((s)->base_h = 0)\nvoid fm10k_unbind_hw_stats_q(struct fm10k_hw_stats_q *q, u32 idx, u32 count);\ns32 fm10k_get_host_state_generic(struct fm10k_hw *hw, bool *host_ready);\n#endif /* _FM10K_COMMON_H_ */\n" }, { "path": "drivers/net/fm10k/base/fm10k_mbx.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"fm10k_common.h\"\n\n/**\n * fm10k_fifo_init - Initialize a message FIFO\n * @fifo: pointer to FIFO\n * @buffer: pointer to memory to be used to store FIFO\n * @size: maximum message size to store in FIFO, must be 2^n - 1\n **/\nSTATIC void fm10k_fifo_init(struct fm10k_mbx_fifo *fifo, u32 *buffer, u16 size)\n{\n\tfifo->buffer = buffer;\n\tfifo->size = size;\n\tfifo->head = 0;\n\tfifo->tail = 0;\n}\n\n/**\n * fm10k_fifo_used - Retrieve used space in FIFO\n * @fifo: pointer to FIFO\n *\n * This function returns the number of DWORDs used in the FIFO\n **/\nSTATIC u16 fm10k_fifo_used(struct fm10k_mbx_fifo *fifo)\n{\n\treturn fifo->tail - fifo->head;\n}\n\n/**\n * fm10k_fifo_unused - Retrieve unused space in FIFO\n * @fifo: pointer to FIFO\n *\n * This function returns the number of unused DWORDs in the FIFO\n **/\nSTATIC u16 fm10k_fifo_unused(struct fm10k_mbx_fifo *fifo)\n{\n\treturn fifo->size + fifo->head - fifo->tail;\n}\n\n/**\n * fm10k_fifo_empty - Test to verify if fifo is empty\n * @fifo: pointer to FIFO\n *\n * This function returns true if the FIFO is empty, else false\n **/\nSTATIC bool fm10k_fifo_empty(struct fm10k_mbx_fifo *fifo)\n{\n\treturn fifo->head == fifo->tail;\n}\n\n/**\n * fm10k_fifo_head_offset - returns indices of head with given offset\n * @fifo: pointer to FIFO\n * @offset: offset to add to head\n *\n * This function returns the indices into the fifo based on head + offset\n **/\nSTATIC u16 fm10k_fifo_head_offset(struct fm10k_mbx_fifo *fifo, u16 offset)\n{\n\treturn (fifo->head + offset) & (fifo->size - 1);\n}\n\n/**\n * fm10k_fifo_tail_offset - returns indices of tail with given offset\n * @fifo: pointer to FIFO\n * @offset: offset to add to tail\n *\n * This function returns the indices into the fifo based on tail + offset\n **/\nSTATIC u16 fm10k_fifo_tail_offset(struct fm10k_mbx_fifo *fifo, u16 offset)\n{\n\treturn (fifo->tail + offset) & (fifo->size - 1);\n}\n\n/**\n * fm10k_fifo_head_len - Retrieve length of first message in FIFO\n * @fifo: pointer to FIFO\n *\n * This function returns the size of the first message in the FIFO\n **/\nSTATIC u16 fm10k_fifo_head_len(struct fm10k_mbx_fifo *fifo)\n{\n\tu32 *head = fifo->buffer + fm10k_fifo_head_offset(fifo, 0);\n\n\t/* verify there is at least 1 DWORD in the fifo so *head is valid */\n\tif (fm10k_fifo_empty(fifo))\n\t\treturn 0;\n\n\t/* retieve the message length */\n\treturn FM10K_TLV_DWORD_LEN(*head);\n}\n\n/**\n * fm10k_fifo_head_drop - Drop the first message in FIFO\n * @fifo: pointer to FIFO\n *\n * This function returns the size of the message dropped from the FIFO\n **/\nSTATIC u16 fm10k_fifo_head_drop(struct fm10k_mbx_fifo *fifo)\n{\n\tu16 len = fm10k_fifo_head_len(fifo);\n\n\t/* update head so it is at the start of next frame */\n\tfifo->head += len;\n\n\treturn len;\n}\n\n/**\n * fm10k_mbx_index_len - Convert a head/tail index into a length value\n * @mbx: pointer to mailbox\n * @head: head index\n * @tail: head index\n *\n * This function takes the head and tail index and determines the length\n * of the data indicated by this pair.\n **/\nSTATIC u16 fm10k_mbx_index_len(struct fm10k_mbx_info *mbx, u16 head, u16 tail)\n{\n\tu16 len = tail - head;\n\n\t/* we wrapped so subtract 2, one for index 0, one for all 1s index */\n\tif (len > tail)\n\t\tlen -= 2;\n\n\treturn len & ((mbx->mbmem_len << 1) - 1);\n}\n\n/**\n * fm10k_mbx_tail_add - Determine new tail value with added offset\n * @mbx: pointer to mailbox\n * @offset: length to add to head offset\n *\n * This function takes the local tail index and recomputes it for\n * a given length added as an offset.\n **/\nSTATIC u16 fm10k_mbx_tail_add(struct fm10k_mbx_info *mbx, u16 offset)\n{\n\tu16 tail = (mbx->tail + offset + 1) & ((mbx->mbmem_len << 1) - 1);\n\n\t/* add/sub 1 because we cannot have offset 0 or all 1s */\n\treturn (tail > mbx->tail) ? --tail : ++tail;\n}\n\n/**\n * fm10k_mbx_tail_sub - Determine new tail value with subtracted offset\n * @mbx: pointer to mailbox\n * @offset: length to add to head offset\n *\n * This function takes the local tail index and recomputes it for\n * a given length added as an offset.\n **/\nSTATIC u16 fm10k_mbx_tail_sub(struct fm10k_mbx_info *mbx, u16 offset)\n{\n\tu16 tail = (mbx->tail - offset - 1) & ((mbx->mbmem_len << 1) - 1);\n\n\t/* sub/add 1 because we cannot have offset 0 or all 1s */\n\treturn (tail < mbx->tail) ? ++tail : --tail;\n}\n\n/**\n * fm10k_mbx_head_add - Determine new head value with added offset\n * @mbx: pointer to mailbox\n * @offset: length to add to head offset\n *\n * This function takes the local head index and recomputes it for\n * a given length added as an offset.\n **/\nSTATIC u16 fm10k_mbx_head_add(struct fm10k_mbx_info *mbx, u16 offset)\n{\n\tu16 head = (mbx->head + offset + 1) & ((mbx->mbmem_len << 1) - 1);\n\n\t/* add/sub 1 because we cannot have offset 0 or all 1s */\n\treturn (head > mbx->head) ? --head : ++head;\n}\n\n/**\n * fm10k_mbx_head_sub - Determine new head value with subtracted offset\n * @mbx: pointer to mailbox\n * @offset: length to add to head offset\n *\n * This function takes the local head index and recomputes it for\n * a given length added as an offset.\n **/\nSTATIC u16 fm10k_mbx_head_sub(struct fm10k_mbx_info *mbx, u16 offset)\n{\n\tu16 head = (mbx->head - offset - 1) & ((mbx->mbmem_len << 1) - 1);\n\n\t/* sub/add 1 because we cannot have offset 0 or all 1s */\n\treturn (head < mbx->head) ? ++head : --head;\n}\n\n/**\n * fm10k_mbx_pushed_tail_len - Retrieve the length of message being pushed\n * @mbx: pointer to mailbox\n *\n * This function will return the length of the message currently being\n * pushed onto the tail of the Rx queue.\n **/\nSTATIC u16 fm10k_mbx_pushed_tail_len(struct fm10k_mbx_info *mbx)\n{\n\tu32 *tail = mbx->rx.buffer + fm10k_fifo_tail_offset(&mbx->rx, 0);\n\n\t/* pushed tail is only valid if pushed is set */\n\tif (!mbx->pushed)\n\t\treturn 0;\n\n\treturn FM10K_TLV_DWORD_LEN(*tail);\n}\n\n/**\n * fm10k_fifo_write_copy - pulls data off of msg and places it in fifo\n * @fifo: pointer to FIFO\n * @msg: message array to populate\n * @tail_offset: additional offset to add to tail pointer\n * @len: length of FIFO to copy into message header\n *\n * This function will take a message and copy it into a section of the\n * FIFO. In order to get something into a location other than just\n * the tail you can use tail_offset to adjust the pointer.\n **/\nSTATIC void fm10k_fifo_write_copy(struct fm10k_mbx_fifo *fifo,\n\t\t\t\t const u32 *msg, u16 tail_offset, u16 len)\n{\n\tu16 end = fm10k_fifo_tail_offset(fifo, tail_offset);\n\tu32 *tail = fifo->buffer + end;\n\n\t/* track when we should cross the end of the FIFO */\n\tend = fifo->size - end;\n\n\t/* copy end of message before start of message */\n\tif (end < len)\n\t\tmemcpy(fifo->buffer, msg + end, (len - end) << 2);\n\telse\n\t\tend = len;\n\n\t/* Copy remaining message into Tx FIFO */\n\tmemcpy(tail, msg, end << 2);\n}\n\n/**\n * fm10k_fifo_enqueue - Enqueues the message to the tail of the FIFO\n * @fifo: pointer to FIFO\n * @msg: message array to read\n *\n * This function enqueues a message up to the size specified by the length\n * contained in the first DWORD of the message and will place at the tail\n * of the FIFO. It will return 0 on success, or a negative value on error.\n **/\nSTATIC s32 fm10k_fifo_enqueue(struct fm10k_mbx_fifo *fifo, const u32 *msg)\n{\n\tu16 len = FM10K_TLV_DWORD_LEN(*msg);\n\n\tDEBUGFUNC(\"fm10k_fifo_enqueue\");\n\n\t/* verify parameters */\n\tif (len > fifo->size)\n\t\treturn FM10K_MBX_ERR_SIZE;\n\n\t/* verify there is room for the message */\n\tif (len > fm10k_fifo_unused(fifo))\n\t\treturn FM10K_MBX_ERR_NO_SPACE;\n\n\t/* Copy message into FIFO */\n\tfm10k_fifo_write_copy(fifo, msg, 0, len);\n\n\t/* memory barrier to guarantee FIFO is written before tail update */\n\tFM10K_WMB();\n\n\t/* Update Tx FIFO tail */\n\tfifo->tail += len;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_mbx_validate_msg_size - Validate incoming message based on size\n * @mbx: pointer to mailbox\n * @len: length of data pushed onto buffer\n *\n * This function analyzes the frame and will return a non-zero value when\n * the start of a message larger than the mailbox is detected.\n **/\nSTATIC u16 fm10k_mbx_validate_msg_size(struct fm10k_mbx_info *mbx, u16 len)\n{\n\tstruct fm10k_mbx_fifo *fifo = &mbx->rx;\n\tu16 total_len = 0, msg_len;\n\tu32 *msg;\n\n\tDEBUGFUNC(\"fm10k_mbx_validate_msg\");\n\n\t/* length should include previous amounts pushed */\n\tlen += mbx->pushed;\n\n\t/* offset in message is based off of current message size */\n\tdo {\n\t\tmsg = fifo->buffer + fm10k_fifo_tail_offset(fifo, total_len);\n\t\tmsg_len = FM10K_TLV_DWORD_LEN(*msg);\n\t\ttotal_len += msg_len;\n\t} while (total_len < len);\n\n\t/* message extends out of pushed section, but fits in FIFO */\n\tif ((len < total_len) && (msg_len <= mbx->rx.size))\n\t\treturn 0;\n\n\t/* return length of invalid section */\n\treturn (len < total_len) ? len : (len - total_len);\n}\n\n/**\n * fm10k_mbx_write_copy - pulls data off of Tx FIFO and places it in mbmem\n * @mbx: pointer to mailbox\n *\n * This function will take a section of the Rx FIFO and copy it into the\n\t\tmbx->tail--;\n * mailbox memory. The offset in mbmem is based on the lower bits of the\n * tail and len determines the length to copy.\n **/\nSTATIC void fm10k_mbx_write_copy(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tstruct fm10k_mbx_fifo *fifo = &mbx->tx;\n\tu32 mbmem = mbx->mbmem_reg;\n\tu32 *head = fifo->buffer;\n\tu16 end, len, tail, mask;\n\n\tDEBUGFUNC(\"fm10k_mbx_write_copy\");\n\n\tif (!mbx->tail_len)\n\t\treturn;\n\n\t/* determine data length and mbmem tail index */\n\tmask = mbx->mbmem_len - 1;\n\tlen = mbx->tail_len;\n\ttail = fm10k_mbx_tail_sub(mbx, len);\n\tif (tail > mask)\n\t\ttail++;\n\n\t/* determine offset in the ring */\n\tend = fm10k_fifo_head_offset(fifo, mbx->pulled);\n\thead += end;\n\n\t/* memory barrier to guarantee data is ready to be read */\n\tFM10K_RMB();\n\n\t/* Copy message from Tx FIFO */\n\tfor (end = fifo->size - end; len; head = fifo->buffer) {\n\t\tdo {\n\t\t\t/* adjust tail to match offset for FIFO */\n\t\t\ttail &= mask;\n\t\t\tif (!tail)\n\t\t\t\ttail++;\n\n\t\t\t/* write message to hardware FIFO */\n\t\t\tFM10K_WRITE_MBX(hw, mbmem + tail++, *(head++));\n\t\t} while (--len && --end);\n\t}\n}\n\n/**\n * fm10k_mbx_pull_head - Pulls data off of head of Tx FIFO\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n * @head: acknowledgement number last received\n *\n * This function will push the tail index forward based on the remote\n * head index. It will then pull up to mbmem_len DWORDs off of the\n * head of the FIFO and will place it in the MBMEM registers\n * associated with the mailbox.\n **/\nSTATIC void fm10k_mbx_pull_head(struct fm10k_hw *hw,\n\t\t\t\tstruct fm10k_mbx_info *mbx, u16 head)\n{\n\tu16 mbmem_len, len, ack = fm10k_mbx_index_len(mbx, head, mbx->tail);\n\tstruct fm10k_mbx_fifo *fifo = &mbx->tx;\n\n\t/* update number of bytes pulled and update bytes in transit */\n\tmbx->pulled += mbx->tail_len - ack;\n\n\t/* determine length of data to pull, reserve space for mbmem header */\n\tmbmem_len = mbx->mbmem_len - 1;\n\tlen = fm10k_fifo_used(fifo) - mbx->pulled;\n\tif (len > mbmem_len)\n\t\tlen = mbmem_len;\n\n\t/* update tail and record number of bytes in transit */\n\tmbx->tail = fm10k_mbx_tail_add(mbx, len - ack);\n\tmbx->tail_len = len;\n\n\t/* drop pulled messages from the FIFO */\n\tfor (len = fm10k_fifo_head_len(fifo);\n\t len && (mbx->pulled >= len);\n\t len = fm10k_fifo_head_len(fifo)) {\n\t\tmbx->pulled -= fm10k_fifo_head_drop(fifo);\n\t\tmbx->tx_messages++;\n\t\tmbx->tx_dwords += len;\n\t}\n\n\t/* Copy message out from the Tx FIFO */\n\tfm10k_mbx_write_copy(hw, mbx);\n}\n\n/**\n * fm10k_mbx_read_copy - pulls data off of mbmem and places it in Rx FIFO\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function will take a section of the mailbox memory and copy it\n * into the Rx FIFO. The offset is based on the lower bits of the\n * head and len determines the length to copy.\n **/\nSTATIC void fm10k_mbx_read_copy(struct fm10k_hw *hw,\n\t\t\t\tstruct fm10k_mbx_info *mbx)\n{\n\tstruct fm10k_mbx_fifo *fifo = &mbx->rx;\n\tu32 mbmem = mbx->mbmem_reg ^ mbx->mbmem_len;\n\tu32 *tail = fifo->buffer;\n\tu16 end, len, head;\n\n\tDEBUGFUNC(\"fm10k_mbx_read_copy\");\n\n\t/* determine data length and mbmem head index */\n\tlen = mbx->head_len;\n\thead = fm10k_mbx_head_sub(mbx, len);\n\tif (head >= mbx->mbmem_len)\n\t\thead++;\n\n\t/* determine offset in the ring */\n\tend = fm10k_fifo_tail_offset(fifo, mbx->pushed);\n\ttail += end;\n\n\t/* Copy message into Rx FIFO */\n\tfor (end = fifo->size - end; len; tail = fifo->buffer) {\n\t\tdo {\n\t\t\t/* adjust head to match offset for FIFO */\n\t\t\thead &= mbx->mbmem_len - 1;\n\t\t\tif (!head)\n\t\t\t\thead++;\n\n\t\t\t/* read message from hardware FIFO */\n\t\t\t*(tail++) = FM10K_READ_MBX(hw, mbmem + head++);\n\t\t} while (--len && --end);\n\t}\n\n\t/* memory barrier to guarantee FIFO is written before tail update */\n\tFM10K_WMB();\n}\n\n/**\n * fm10k_mbx_push_tail - Pushes up to 15 DWORDs on to tail of FIFO\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n * @tail: tail index of message\n *\n * This function will first validate the tail index and size for the\n * incoming message. It then updates the acknowledgment number and\n * copies the data into the FIFO. It will return the number of messages\n * dequeued on success and a negative value on error.\n **/\nSTATIC s32 fm10k_mbx_push_tail(struct fm10k_hw *hw,\n\t\t\t struct fm10k_mbx_info *mbx,\n\t\t\t u16 tail)\n{\n\tstruct fm10k_mbx_fifo *fifo = &mbx->rx;\n\tu16 len, seq = fm10k_mbx_index_len(mbx, mbx->head, tail);\n\n\tDEBUGFUNC(\"fm10k_mbx_push_tail\");\n\n\t/* determine length of data to push */\n\tlen = fm10k_fifo_unused(fifo) - mbx->pushed;\n\tif (len > seq)\n\t\tlen = seq;\n\n\t/* update head and record bytes received */\n\tmbx->head = fm10k_mbx_head_add(mbx, len);\n\tmbx->head_len = len;\n\n\t/* nothing to do if there is no data */\n\tif (!len)\n\t\treturn FM10K_SUCCESS;\n\n\t/* Copy msg into Rx FIFO */\n\tfm10k_mbx_read_copy(hw, mbx);\n\n\t/* determine if there are any invalid lengths in message */\n\tif (fm10k_mbx_validate_msg_size(mbx, len))\n\t\treturn FM10K_MBX_ERR_SIZE;\n\n\t/* Update pushed */\n\tmbx->pushed += len;\n\n\t/* flush any completed messages */\n\tfor (len = fm10k_mbx_pushed_tail_len(mbx);\n\t len && (mbx->pushed >= len);\n\t len = fm10k_mbx_pushed_tail_len(mbx)) {\n\t\tfifo->tail += len;\n\t\tmbx->pushed -= len;\n\t\tmbx->rx_messages++;\n\t\tmbx->rx_dwords += len;\n\t}\n\n\treturn FM10K_SUCCESS;\n}\n\n/* pre-generated data for generating the CRC based on the poly 0xAC9A. */\nstatic const u16 fm10k_crc_16b_table[256] = {\n\t0x0000, 0x7956, 0xF2AC, 0x8BFA, 0xBC6D, 0xC53B, 0x4EC1, 0x3797,\n\t0x21EF, 0x58B9, 0xD343, 0xAA15, 0x9D82, 0xE4D4, 0x6F2E, 0x1678,\n\t0x43DE, 0x3A88, 0xB172, 0xC824, 0xFFB3, 0x86E5, 0x0D1F, 0x7449,\n\t0x6231, 0x1B67, 0x909D, 0xE9CB, 0xDE5C, 0xA70A, 0x2CF0, 0x55A6,\n\t0x87BC, 0xFEEA, 0x7510, 0x0C46, 0x3BD1, 0x4287, 0xC97D, 0xB02B,\n\t0xA653, 0xDF05, 0x54FF, 0x2DA9, 0x1A3E, 0x6368, 0xE892, 0x91C4,\n\t0xC462, 0xBD34, 0x36CE, 0x4F98, 0x780F, 0x0159, 0x8AA3, 0xF3F5,\n\t0xE58D, 0x9CDB, 0x1721, 0x6E77, 0x59E0, 0x20B6, 0xAB4C, 0xD21A,\n\t0x564D, 0x2F1B, 0xA4E1, 0xDDB7, 0xEA20, 0x9376, 0x188C, 0x61DA,\n\t0x77A2, 0x0EF4, 0x850E, 0xFC58, 0xCBCF, 0xB299, 0x3963, 0x4035,\n\t0x1593, 0x6CC5, 0xE73F, 0x9E69, 0xA9FE, 0xD0A8, 0x5B52, 0x2204,\n\t0x347C, 0x4D2A, 0xC6D0, 0xBF86, 0x8811, 0xF147, 0x7ABD, 0x03EB,\n\t0xD1F1, 0xA8A7, 0x235D, 0x5A0B, 0x6D9C, 0x14CA, 0x9F30, 0xE666,\n\t0xF01E, 0x8948, 0x02B2, 0x7BE4, 0x4C73, 0x3525, 0xBEDF, 0xC789,\n\t0x922F, 0xEB79, 0x6083, 0x19D5, 0x2E42, 0x5714, 0xDCEE, 0xA5B8,\n\t0xB3C0, 0xCA96, 0x416C, 0x383A, 0x0FAD, 0x76FB, 0xFD01, 0x8457,\n\t0xAC9A, 0xD5CC, 0x5E36, 0x2760, 0x10F7, 0x69A1, 0xE25B, 0x9B0D,\n\t0x8D75, 0xF423, 0x7FD9, 0x068F, 0x3118, 0x484E, 0xC3B4, 0xBAE2,\n\t0xEF44, 0x9612, 0x1DE8, 0x64BE, 0x5329, 0x2A7F, 0xA185, 0xD8D3,\n\t0xCEAB, 0xB7FD, 0x3C07, 0x4551, 0x72C6, 0x0B90, 0x806A, 0xF93C,\n\t0x2B26, 0x5270, 0xD98A, 0xA0DC, 0x974B, 0xEE1D, 0x65E7, 0x1CB1,\n\t0x0AC9, 0x739F, 0xF865, 0x8133, 0xB6A4, 0xCFF2, 0x4408, 0x3D5E,\n\t0x68F8, 0x11AE, 0x9A54, 0xE302, 0xD495, 0xADC3, 0x2639, 0x5F6F,\n\t0x4917, 0x3041, 0xBBBB, 0xC2ED, 0xF57A, 0x8C2C, 0x07D6, 0x7E80,\n\t0xFAD7, 0x8381, 0x087B, 0x712D, 0x46BA, 0x3FEC, 0xB416, 0xCD40,\n\t0xDB38, 0xA26E, 0x2994, 0x50C2, 0x6755, 0x1E03, 0x95F9, 0xECAF,\n\t0xB909, 0xC05F, 0x4BA5, 0x32F3, 0x0564, 0x7C32, 0xF7C8, 0x8E9E,\n\t0x98E6, 0xE1B0, 0x6A4A, 0x131C, 0x248B, 0x5DDD, 0xD627, 0xAF71,\n\t0x7D6B, 0x043D, 0x8FC7, 0xF691, 0xC106, 0xB850, 0x33AA, 0x4AFC,\n\t0x5C84, 0x25D2, 0xAE28, 0xD77E, 0xE0E9, 0x99BF, 0x1245, 0x6B13,\n\t0x3EB5, 0x47E3, 0xCC19, 0xB54F, 0x82D8, 0xFB8E, 0x7074, 0x0922,\n\t0x1F5A, 0x660C, 0xEDF6, 0x94A0, 0xA337, 0xDA61, 0x519B, 0x28CD };\n\n/**\n * fm10k_crc_16b - Generate a 16 bit CRC for a region of 16 bit data\n * @data: pointer to data to process\n * @seed: seed value for CRC\n * @len: length measured in 16 bits words\n *\n * This function will generate a CRC based on the polynomial 0xAC9A and\n * whatever value is stored in the seed variable. Note that this\n * value inverts the local seed and the result in order to capture all\n * leading and trailing zeros.\n */\nSTATIC u16 fm10k_crc_16b(const u32 *data, u16 seed, u16 len)\n{\n\tu32 result = seed;\n\n\twhile (len--) {\n\t\tresult ^= *(data++);\n\t\tresult = (result >> 8) ^ fm10k_crc_16b_table[result & 0xFF];\n\t\tresult = (result >> 8) ^ fm10k_crc_16b_table[result & 0xFF];\n\n\t\tif (!(len--))\n\t\t\tbreak;\n\n\t\tresult = (result >> 8) ^ fm10k_crc_16b_table[result & 0xFF];\n\t\tresult = (result >> 8) ^ fm10k_crc_16b_table[result & 0xFF];\n\t}\n\n\treturn (u16)result;\n}\n\n/**\n * fm10k_fifo_crc - generate a CRC based off of FIFO data\n * @fifo: pointer to FIFO\n * @offset: offset point for start of FIFO\n * @len: number of DWORDS words to process\n * @seed: seed value for CRC\n *\n * This function generates a CRC for some region of the FIFO\n **/\nSTATIC u16 fm10k_fifo_crc(struct fm10k_mbx_fifo *fifo, u16 offset,\n\t\t\t u16 len, u16 seed)\n{\n\tu32 *data = fifo->buffer + offset;\n\n\t/* track when we should cross the end of the FIFO */\n\toffset = fifo->size - offset;\n\n\t/* if we are in 2 blocks process the end of the FIFO first */\n\tif (offset < len) {\n\t\tseed = fm10k_crc_16b(data, seed, offset * 2);\n\t\tdata = fifo->buffer;\n\t\tlen -= offset;\n\t}\n\n\t/* process any remaining bits */\n\treturn fm10k_crc_16b(data, seed, len * 2);\n}\n\n/**\n * fm10k_mbx_update_local_crc - Update the local CRC for outgoing data\n * @mbx: pointer to mailbox\n * @head: head index provided by remote mailbox\n *\n * This function will generate the CRC for all data from the end of the\n * last head update to the current one. It uses the result of the\n * previous CRC as the seed for this update. The result is stored in\n * mbx->local.\n **/\nSTATIC void fm10k_mbx_update_local_crc(struct fm10k_mbx_info *mbx, u16 head)\n{\n\tu16 len = mbx->tail_len - fm10k_mbx_index_len(mbx, head, mbx->tail);\n\n\t/* determine the offset for the start of the region to be pulled */\n\thead = fm10k_fifo_head_offset(&mbx->tx, mbx->pulled);\n\n\t/* update local CRC to include all of the pulled data */\n\tmbx->local = fm10k_fifo_crc(&mbx->tx, head, len, mbx->local);\n}\n\n/**\n * fm10k_mbx_verify_remote_crc - Verify the CRC is correct for current data\n * @mbx: pointer to mailbox\n *\n * This function will take all data that has been provided from the remote\n * end and generate a CRC for it. This is stored in mbx->remote. The\n * CRC for the header is then computed and if the result is non-zero this\n * is an error and we signal an error dropping all data and resetting the\n * connection.\n */\nSTATIC s32 fm10k_mbx_verify_remote_crc(struct fm10k_mbx_info *mbx)\n{\n\tstruct fm10k_mbx_fifo *fifo = &mbx->rx;\n\tu16 len = mbx->head_len;\n\tu16 offset = fm10k_fifo_tail_offset(fifo, mbx->pushed) - len;\n\tu16 crc;\n\n\t/* update the remote CRC if new data has been received */\n\tif (len)\n\t\tmbx->remote = fm10k_fifo_crc(fifo, offset, len, mbx->remote);\n\n\t/* process the full header as we have to validate the CRC */\n\tcrc = fm10k_crc_16b(&mbx->mbx_hdr, mbx->remote, 1);\n\n\t/* notify other end if we have a problem */\n\treturn crc ? FM10K_MBX_ERR_CRC : FM10K_SUCCESS;\n}\n\n/**\n * fm10k_mbx_rx_ready - Indicates that a message is ready in the Rx FIFO\n * @mbx: pointer to mailbox\n *\n * This function returns true if there is a message in the Rx FIFO to dequeue.\n **/\nSTATIC bool fm10k_mbx_rx_ready(struct fm10k_mbx_info *mbx)\n{\n\tu16 msg_size = fm10k_fifo_head_len(&mbx->rx);\n\n\treturn msg_size && (fm10k_fifo_used(&mbx->rx) >= msg_size);\n}\n\n/**\n * fm10k_mbx_tx_ready - Indicates that the mailbox is in state ready for Tx\n * @mbx: pointer to mailbox\n * @len: verify free space is >= this value\n *\n * This function returns true if the mailbox is in a state ready to transmit.\n **/\nSTATIC bool fm10k_mbx_tx_ready(struct fm10k_mbx_info *mbx, u16 len)\n{\n\tu16 fifo_unused = fm10k_fifo_unused(&mbx->tx);\n\n\treturn (mbx->state == FM10K_STATE_OPEN) && (fifo_unused >= len);\n}\n\n/**\n * fm10k_mbx_tx_complete - Indicates that the Tx FIFO has been emptied\n * @mbx: pointer to mailbox\n *\n * This function returns true if the Tx FIFO is empty.\n **/\nSTATIC bool fm10k_mbx_tx_complete(struct fm10k_mbx_info *mbx)\n{\n\treturn fm10k_fifo_empty(&mbx->tx);\n}\n\n/**\n * fm10k_mbx_deqeueue_rx - Dequeues the message from the head in the Rx FIFO\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function dequeues messages and hands them off to the tlv parser.\n * It will return the number of messages processed when called.\n **/\nSTATIC u16 fm10k_mbx_dequeue_rx(struct fm10k_hw *hw,\n\t\t\t\tstruct fm10k_mbx_info *mbx)\n{\n\tstruct fm10k_mbx_fifo *fifo = &mbx->rx;\n\ts32 err;\n\tu16 cnt;\n\n\t/* parse Rx messages out of the Rx FIFO to empty it */\n\tfor (cnt = 0; !fm10k_fifo_empty(fifo); cnt++) {\n\t\terr = fm10k_tlv_msg_parse(hw, fifo->buffer + fifo->head,\n\t\t\t\t\t mbx, mbx->msg_data);\n\t\tif (err < 0)\n\t\t\tmbx->rx_parse_err++;\n\n\t\tfm10k_fifo_head_drop(fifo);\n\t}\n\n\t/* shift remaining bytes back to start of FIFO */\n\tmemmove(fifo->buffer, fifo->buffer + fifo->tail, mbx->pushed << 2);\n\n\t/* shift head and tail based on the memory we moved */\n\tfifo->tail -= fifo->head;\n\tfifo->head = 0;\n\n\treturn cnt;\n}\n\n/**\n * fm10k_mbx_enqueue_tx - Enqueues the message to the tail of the Tx FIFO\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n * @msg: message array to read\n *\n * This function enqueues a message up to the size specified by the length\n * contained in the first DWORD of the message and will place at the tail\n * of the FIFO. It will return 0 on success, or a negative value on error.\n **/\nSTATIC s32 fm10k_mbx_enqueue_tx(struct fm10k_hw *hw,\n\t\t\t\tstruct fm10k_mbx_info *mbx, const u32 *msg)\n{\n\tu32 countdown = mbx->timeout;\n\ts32 err;\n\n\tswitch (mbx->state) {\n\tcase FM10K_STATE_CLOSED:\n\tcase FM10K_STATE_DISCONNECT:\n\t\treturn FM10K_MBX_ERR_NO_MBX;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* enqueue the message on the Tx FIFO */\n\terr = fm10k_fifo_enqueue(&mbx->tx, msg);\n\n\t/* if it failed give the FIFO a chance to drain */\n\twhile (err && countdown) {\n\t\tcountdown--;\n\t\tusec_delay(mbx->usec_delay);\n\t\tmbx->ops.process(hw, mbx);\n\t\terr = fm10k_fifo_enqueue(&mbx->tx, msg);\n\t}\n\n\t/* if we failed treat the error */\n\tif (err) {\n\t\tmbx->timeout = 0;\n\t\tmbx->tx_busy++;\n\t}\n\n\t/* begin processing message, ignore errors as this is just meant\n\t * to start the mailbox flow so we are not concerned if there\n\t * is a bad error, or the mailbox is already busy with a request\n\t */\n\tif (!mbx->tail_len)\n\t\tmbx->ops.process(hw, mbx);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_mbx_read - Copies the mbmem to local message buffer\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function copies the message from the mbmem to the message array\n **/\nSTATIC s32 fm10k_mbx_read(struct fm10k_hw *hw, struct fm10k_mbx_info *mbx)\n{\n\tDEBUGFUNC(\"fm10k_mbx_read\");\n\n\t/* only allow one reader in here at a time */\n\tif (mbx->mbx_hdr)\n\t\treturn FM10K_MBX_ERR_BUSY;\n\n\t/* read to capture initial interrupt bits */\n\tif (FM10K_READ_MBX(hw, mbx->mbx_reg) & FM10K_MBX_REQ_INTERRUPT)\n\t\tmbx->mbx_lock = FM10K_MBX_ACK;\n\n\t/* write back interrupt bits to clear */\n\tFM10K_WRITE_MBX(hw, mbx->mbx_reg,\n\t\t\tFM10K_MBX_REQ_INTERRUPT | FM10K_MBX_ACK_INTERRUPT);\n\n\t/* read remote header */\n\tmbx->mbx_hdr = FM10K_READ_MBX(hw, mbx->mbmem_reg ^ mbx->mbmem_len);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_mbx_write - Copies the local message buffer to mbmem\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function copies the message from the the message array to mbmem\n **/\nSTATIC void fm10k_mbx_write(struct fm10k_hw *hw, struct fm10k_mbx_info *mbx)\n{\n\tu32 mbmem = mbx->mbmem_reg;\n\n\tDEBUGFUNC(\"fm10k_mbx_write\");\n\n\t/* write new msg header to notify recipient of change */\n\tFM10K_WRITE_MBX(hw, mbmem, mbx->mbx_hdr);\n\n\t/* write mailbox to send interrupt */\n\tif (mbx->mbx_lock)\n\t\tFM10K_WRITE_MBX(hw, mbx->mbx_reg, mbx->mbx_lock);\n\n\t/* we no longer are using the header so free it */\n\tmbx->mbx_hdr = 0;\n\tmbx->mbx_lock = 0;\n}\n\n/**\n * fm10k_mbx_create_connect_hdr - Generate a connect mailbox header\n * @mbx: pointer to mailbox\n *\n * This function returns a connection mailbox header\n **/\nSTATIC void fm10k_mbx_create_connect_hdr(struct fm10k_mbx_info *mbx)\n{\n\tmbx->mbx_lock |= FM10K_MBX_REQ;\n\n\tmbx->mbx_hdr = FM10K_MSG_HDR_FIELD_SET(FM10K_MSG_CONNECT, TYPE) |\n\t\t FM10K_MSG_HDR_FIELD_SET(mbx->head, HEAD) |\n\t\t FM10K_MSG_HDR_FIELD_SET(mbx->rx.size - 1, CONNECT_SIZE);\n}\n\n/**\n * fm10k_mbx_create_data_hdr - Generate a data mailbox header\n * @mbx: pointer to mailbox\n *\n * This function returns a data mailbox header\n **/\nSTATIC void fm10k_mbx_create_data_hdr(struct fm10k_mbx_info *mbx)\n{\n\tu32 hdr = FM10K_MSG_HDR_FIELD_SET(FM10K_MSG_DATA, TYPE) |\n\t\t FM10K_MSG_HDR_FIELD_SET(mbx->tail, TAIL) |\n\t\t FM10K_MSG_HDR_FIELD_SET(mbx->head, HEAD);\n\tstruct fm10k_mbx_fifo *fifo = &mbx->tx;\n\tu16 crc;\n\n\tif (mbx->tail_len)\n\t\tmbx->mbx_lock |= FM10K_MBX_REQ;\n\n\t/* generate CRC for data in flight and header */\n\tcrc = fm10k_fifo_crc(fifo, fm10k_fifo_head_offset(fifo, mbx->pulled),\n\t\t\t mbx->tail_len, mbx->local);\n\tcrc = fm10k_crc_16b(&hdr, crc, 1);\n\n\t/* load header to memory to be written */\n\tmbx->mbx_hdr = hdr | FM10K_MSG_HDR_FIELD_SET(crc, CRC);\n}\n\n/**\n * fm10k_mbx_create_disconnect_hdr - Generate a disconnect mailbox header\n * @mbx: pointer to mailbox\n *\n * This function returns a disconnect mailbox header\n **/\nSTATIC void fm10k_mbx_create_disconnect_hdr(struct fm10k_mbx_info *mbx)\n{\n\tu32 hdr = FM10K_MSG_HDR_FIELD_SET(FM10K_MSG_DISCONNECT, TYPE) |\n\t\t FM10K_MSG_HDR_FIELD_SET(mbx->tail, TAIL) |\n\t\t FM10K_MSG_HDR_FIELD_SET(mbx->head, HEAD);\n\tu16 crc = fm10k_crc_16b(&hdr, mbx->local, 1);\n\n\tmbx->mbx_lock |= FM10K_MBX_ACK;\n\n\t/* load header to memory to be written */\n\tmbx->mbx_hdr = hdr | FM10K_MSG_HDR_FIELD_SET(crc, CRC);\n}\n\n/**\n * fm10k_mbx_create_error_msg - Generate a error message\n * @mbx: pointer to mailbox\n * @err: local error encountered\n *\n * This function will interpret the error provided by err, and based on\n * that it may shift the message by 1 DWORD and then place an error header\n * at the start of the message.\n **/\nSTATIC void fm10k_mbx_create_error_msg(struct fm10k_mbx_info *mbx, s32 err)\n{\n\t/* only generate an error message for these types */\n\tswitch (err) {\n\tcase FM10K_MBX_ERR_TAIL:\n\tcase FM10K_MBX_ERR_HEAD:\n\tcase FM10K_MBX_ERR_TYPE:\n\tcase FM10K_MBX_ERR_SIZE:\n\tcase FM10K_MBX_ERR_RSVD0:\n\tcase FM10K_MBX_ERR_CRC:\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\tmbx->mbx_lock |= FM10K_MBX_REQ;\n\n\tmbx->mbx_hdr = FM10K_MSG_HDR_FIELD_SET(FM10K_MSG_ERROR, TYPE) |\n\t\t FM10K_MSG_HDR_FIELD_SET(err, ERR_NO) |\n\t\t FM10K_MSG_HDR_FIELD_SET(mbx->head, HEAD);\n}\n\n/**\n * fm10k_mbx_validate_msg_hdr - Validate common fields in the message header\n * @mbx: pointer to mailbox\n * @msg: message array to read\n *\n * This function will parse up the fields in the mailbox header and return\n * an error if the header contains any of a number of invalid configurations\n * including unrecognized type, invalid route, or a malformed message.\n **/\nSTATIC s32 fm10k_mbx_validate_msg_hdr(struct fm10k_mbx_info *mbx)\n{\n\tu16 type, rsvd0, head, tail, size;\n\tconst u32 *hdr = &mbx->mbx_hdr;\n\n\tDEBUGFUNC(\"fm10k_mbx_validate_msg_hdr\");\n\n\ttype = FM10K_MSG_HDR_FIELD_GET(*hdr, TYPE);\n\trsvd0 = FM10K_MSG_HDR_FIELD_GET(*hdr, RSVD0);\n\ttail = FM10K_MSG_HDR_FIELD_GET(*hdr, TAIL);\n\thead = FM10K_MSG_HDR_FIELD_GET(*hdr, HEAD);\n\tsize = FM10K_MSG_HDR_FIELD_GET(*hdr, CONNECT_SIZE);\n\n\tif (rsvd0)\n\t\treturn FM10K_MBX_ERR_RSVD0;\n\n\tswitch (type) {\n\tcase FM10K_MSG_DISCONNECT:\n\t\t/* validate that all data has been received */\n\t\tif (tail != mbx->head)\n\t\t\treturn FM10K_MBX_ERR_TAIL;\n\n\t\t/* fall through */\n\tcase FM10K_MSG_DATA:\n\t\t/* validate that head is moving correctly */\n\t\tif (!head || (head == FM10K_MSG_HDR_MASK(HEAD)))\n\t\t\treturn FM10K_MBX_ERR_HEAD;\n\t\tif (fm10k_mbx_index_len(mbx, head, mbx->tail) > mbx->tail_len)\n\t\t\treturn FM10K_MBX_ERR_HEAD;\n\n\t\t/* validate that tail is moving correctly */\n\t\tif (!tail || (tail == FM10K_MSG_HDR_MASK(TAIL)))\n\t\t\treturn FM10K_MBX_ERR_TAIL;\n\t\tif (fm10k_mbx_index_len(mbx, mbx->head, tail) < mbx->mbmem_len)\n\t\t\tbreak;\n\n\t\treturn FM10K_MBX_ERR_TAIL;\n\tcase FM10K_MSG_CONNECT:\n\t\t/* validate size is in range and is power of 2 mask */\n\t\tif ((size < FM10K_VFMBX_MSG_MTU) || (size & (size + 1)))\n\t\t\treturn FM10K_MBX_ERR_SIZE;\n\n\t\t/* fall through */\n\tcase FM10K_MSG_ERROR:\n\t\tif (!head || (head == FM10K_MSG_HDR_MASK(HEAD)))\n\t\t\treturn FM10K_MBX_ERR_HEAD;\n\t\t/* neither create nor error include a tail offset */\n\t\tif (tail)\n\t\t\treturn FM10K_MBX_ERR_TAIL;\n\n\t\tbreak;\n\tdefault:\n\t\treturn FM10K_MBX_ERR_TYPE;\n\t}\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_mbx_create_reply - Generate reply based on state and remote head\n * @mbx: pointer to mailbox\n * @head: acknowledgement number\n *\n * This function will generate an outgoing message based on the current\n * mailbox state and the remote fifo head. It will return the length\n * of the outgoing message excluding header on success, and a negative value\n * on error.\n **/\nSTATIC s32 fm10k_mbx_create_reply(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_mbx_info *mbx, u16 head)\n{\n\tswitch (mbx->state) {\n\tcase FM10K_STATE_OPEN:\n\tcase FM10K_STATE_DISCONNECT:\n\t\t/* update our checksum for the outgoing data */\n\t\tfm10k_mbx_update_local_crc(mbx, head);\n\n\t\t/* as long as other end recognizes us keep sending data */\n\t\tfm10k_mbx_pull_head(hw, mbx, head);\n\n\t\t/* generate new header based on data */\n\t\tif (mbx->tail_len || (mbx->state == FM10K_STATE_OPEN))\n\t\t\tfm10k_mbx_create_data_hdr(mbx);\n\t\telse\n\t\t\tfm10k_mbx_create_disconnect_hdr(mbx);\n\t\tbreak;\n\tcase FM10K_STATE_CONNECT:\n\t\t/* send disconnect even if we aren't connected */\n\t\tfm10k_mbx_create_connect_hdr(mbx);\n\t\tbreak;\n\tcase FM10K_STATE_CLOSED:\n\t\t/* generate new header based on data */\n\t\tfm10k_mbx_create_disconnect_hdr(mbx);\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_mbx_reset_work- Reset internal pointers for any pending work\n * @mbx: pointer to mailbox\n *\n * This function will reset all internal pointers so any work in progress\n * is dropped. This call should occur every time we transition from the\n * open state to the connect state.\n **/\nSTATIC void fm10k_mbx_reset_work(struct fm10k_mbx_info *mbx)\n{\n\t/* reset our outgoing max size back to Rx limits */\n\tmbx->max_size = mbx->rx.size - 1;\n\n\t/* just do a quick resysnc to start of message */\n\tmbx->pushed = 0;\n\tmbx->pulled = 0;\n\tmbx->tail_len = 0;\n\tmbx->head_len = 0;\n\tmbx->rx.tail = 0;\n\tmbx->rx.head = 0;\n}\n\n/**\n * fm10k_mbx_update_max_size - Update the max_size and drop any large messages\n * @mbx: pointer to mailbox\n * @size: new value for max_size\n *\n * This function will update the max_size value and drop any outgoing messages\n * from the head of the Tx FIFO that are larger than max_size.\n **/\nSTATIC void fm10k_mbx_update_max_size(struct fm10k_mbx_info *mbx, u16 size)\n{\n\tu16 len;\n\n\tDEBUGFUNC(\"fm10k_mbx_update_max_size_hdr\");\n\n\tmbx->max_size = size;\n\n\t/* flush any oversized messages from the queue */\n\tfor (len = fm10k_fifo_head_len(&mbx->tx);\n\t len > size;\n\t len = fm10k_fifo_head_len(&mbx->tx)) {\n\t\tfm10k_fifo_head_drop(&mbx->tx);\n\t\tmbx->tx_dropped++;\n\t}\n}\n\n/**\n * fm10k_mbx_connect_reset - Reset following request for reset\n * @mbx: pointer to mailbox\n *\n * This function resets the mailbox to either a disconnected state\n * or a connect state depending on the current mailbox state\n **/\nSTATIC void fm10k_mbx_connect_reset(struct fm10k_mbx_info *mbx)\n{\n\t/* just do a quick resysnc to start of frame */\n\tfm10k_mbx_reset_work(mbx);\n\n\t/* reset CRC seeds */\n\tmbx->local = FM10K_MBX_CRC_SEED;\n\tmbx->remote = FM10K_MBX_CRC_SEED;\n\n\t/* we cannot exit connect until the size is good */\n\tif (mbx->state == FM10K_STATE_OPEN)\n\t\tmbx->state = FM10K_STATE_CONNECT;\n\telse\n\t\tmbx->state = FM10K_STATE_CLOSED;\n}\n\n/**\n * fm10k_mbx_process_connect - Process connect header\n * @mbx: pointer to mailbox\n * @msg: message array to process\n *\n * This function will read an incoming connect header and reply with the\n * appropriate message. It will return a value indicating the number of\n * data DWORDs on success, or will return a negative value on failure.\n **/\nSTATIC s32 fm10k_mbx_process_connect(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tconst enum fm10k_mbx_state state = mbx->state;\n\tconst u32 *hdr = &mbx->mbx_hdr;\n\tu16 size, head;\n\n\t/* we will need to pull all of the fields for verification */\n\tsize = FM10K_MSG_HDR_FIELD_GET(*hdr, CONNECT_SIZE);\n\thead = FM10K_MSG_HDR_FIELD_GET(*hdr, HEAD);\n\n\tswitch (state) {\n\tcase FM10K_STATE_DISCONNECT:\n\tcase FM10K_STATE_OPEN:\n\t\t/* reset any in-progress work */\n\t\tfm10k_mbx_connect_reset(mbx);\n\t\tbreak;\n\tcase FM10K_STATE_CONNECT:\n\t\t/* we cannot exit connect until the size is good */\n\t\tif (size > mbx->rx.size) {\n\t\t\tmbx->max_size = mbx->rx.size - 1;\n\t\t} else {\n\t\t\t/* record the remote system requesting connection */\n\t\t\tmbx->state = FM10K_STATE_OPEN;\n\n\t\t\tfm10k_mbx_update_max_size(mbx, size);\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* align our tail index to remote head index */\n\tmbx->tail = head;\n\n\treturn fm10k_mbx_create_reply(hw, mbx, head);\n}\n\n/**\n * fm10k_mbx_process_data - Process data header\n * @mbx: pointer to mailbox\n *\n * This function will read an incoming data header and reply with the\n * appropriate message. It will return a value indicating the number of\n * data DWORDs on success, or will return a negative value on failure.\n **/\nSTATIC s32 fm10k_mbx_process_data(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tconst u32 *hdr = &mbx->mbx_hdr;\n\tu16 head, tail;\n\ts32 err;\n\n\tDEBUGFUNC(\"fm10k_mbx_process_data\");\n\n\t/* we will need to pull all of the fields for verification */\n\thead = FM10K_MSG_HDR_FIELD_GET(*hdr, HEAD);\n\ttail = FM10K_MSG_HDR_FIELD_GET(*hdr, TAIL);\n\n\t/* if we are in connect just update our data and go */\n\tif (mbx->state == FM10K_STATE_CONNECT) {\n\t\tmbx->tail = head;\n\t\tmbx->state = FM10K_STATE_OPEN;\n\t}\n\n\t/* abort on message size errors */\n\terr = fm10k_mbx_push_tail(hw, mbx, tail);\n\tif (err < 0)\n\t\treturn err;\n\n\t/* verify the checksum on the incoming data */\n\terr = fm10k_mbx_verify_remote_crc(mbx);\n\tif (err)\n\t\treturn err;\n\n\t/* process messages if we have received any */\n\tfm10k_mbx_dequeue_rx(hw, mbx);\n\n\treturn fm10k_mbx_create_reply(hw, mbx, head);\n}\n\n/**\n * fm10k_mbx_process_disconnect - Process disconnect header\n * @mbx: pointer to mailbox\n *\n * This function will read an incoming disconnect header and reply with the\n * appropriate message. It will return a value indicating the number of\n * data DWORDs on success, or will return a negative value on failure.\n **/\nSTATIC s32 fm10k_mbx_process_disconnect(struct fm10k_hw *hw,\n\t\t\t\t\tstruct fm10k_mbx_info *mbx)\n{\n\tconst enum fm10k_mbx_state state = mbx->state;\n\tconst u32 *hdr = &mbx->mbx_hdr;\n\tu16 head;\n\ts32 err;\n\n\t/* we will need to pull the header field for verification */\n\thead = FM10K_MSG_HDR_FIELD_GET(*hdr, HEAD);\n\n\t/* We should not be receiving disconnect if Rx is incomplete */\n\tif (mbx->pushed)\n\t\treturn FM10K_MBX_ERR_TAIL;\n\n\t/* we have already verified mbx->head == tail so we know this is 0 */\n\tmbx->head_len = 0;\n\n\t/* verify the checksum on the incoming header is correct */\n\terr = fm10k_mbx_verify_remote_crc(mbx);\n\tif (err)\n\t\treturn err;\n\n\tswitch (state) {\n\tcase FM10K_STATE_DISCONNECT:\n\tcase FM10K_STATE_OPEN:\n\t\t/* state doesn't change if we still have work to do */\n\t\tif (!fm10k_mbx_tx_complete(mbx))\n\t\t\tbreak;\n\n\t\t/* verify the head indicates we completed all transmits */\n\t\tif (head != mbx->tail)\n\t\t\treturn FM10K_MBX_ERR_HEAD;\n\n\t\t/* reset any in-progress work */\n\t\tfm10k_mbx_connect_reset(mbx);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn fm10k_mbx_create_reply(hw, mbx, head);\n}\n\n/**\n * fm10k_mbx_process_error - Process error header\n * @mbx: pointer to mailbox\n *\n * This function will read an incoming error header and reply with the\n * appropriate message. It will return a value indicating the number of\n * data DWORDs on success, or will return a negative value on failure.\n **/\nSTATIC s32 fm10k_mbx_process_error(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tconst u32 *hdr = &mbx->mbx_hdr;\n\ts32 err_no;\n\tu16 head;\n\n\t/* we will need to pull all of the fields for verification */\n\thead = FM10K_MSG_HDR_FIELD_GET(*hdr, HEAD);\n\n\t/* we only have lower 10 bits of error number so add upper bits */\n\terr_no = FM10K_MSG_HDR_FIELD_GET(*hdr, ERR_NO);\n\terr_no |= ~FM10K_MSG_HDR_MASK(ERR_NO);\n\n\tswitch (mbx->state) {\n\tcase FM10K_STATE_OPEN:\n\tcase FM10K_STATE_DISCONNECT:\n\t\t/* flush any uncompleted work */\n\t\tfm10k_mbx_reset_work(mbx);\n\n\t\t/* reset CRC seeds */\n\t\tmbx->local = FM10K_MBX_CRC_SEED;\n\t\tmbx->remote = FM10K_MBX_CRC_SEED;\n\n\t\t/* reset tail index and size to prepare for reconnect */\n\t\tmbx->tail = head;\n\n\t\t/* if open then reset max_size and go back to connect */\n\t\tif (mbx->state == FM10K_STATE_OPEN) {\n\t\t\tmbx->state = FM10K_STATE_CONNECT;\n\t\t\tbreak;\n\t\t}\n\n\t\t/* send a connect message to get data flowing again */\n\t\tfm10k_mbx_create_connect_hdr(mbx);\n\t\treturn FM10K_SUCCESS;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn fm10k_mbx_create_reply(hw, mbx, mbx->tail);\n}\n\n/**\n * fm10k_mbx_process - Process mailbox interrupt\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function will process incoming mailbox events and generate mailbox\n * replies. It will return a value indicating the number of DWORDs\n * transmitted excluding header on success or a negative value on error.\n **/\nSTATIC s32 fm10k_mbx_process(struct fm10k_hw *hw,\n\t\t\t struct fm10k_mbx_info *mbx)\n{\n\ts32 err;\n\n\tDEBUGFUNC(\"fm10k_mbx_process\");\n\n\t/* we do not read mailbox if closed */\n\tif (mbx->state == FM10K_STATE_CLOSED)\n\t\treturn FM10K_SUCCESS;\n\n\t/* copy data from mailbox */\n\terr = fm10k_mbx_read(hw, mbx);\n\tif (err)\n\t\treturn err;\n\n\t/* validate type, source, and destination */\n\terr = fm10k_mbx_validate_msg_hdr(mbx);\n\tif (err < 0)\n\t\tgoto msg_err;\n\n\tswitch (FM10K_MSG_HDR_FIELD_GET(mbx->mbx_hdr, TYPE)) {\n\tcase FM10K_MSG_CONNECT:\n\t\terr = fm10k_mbx_process_connect(hw, mbx);\n\t\tbreak;\n\tcase FM10K_MSG_DATA:\n\t\terr = fm10k_mbx_process_data(hw, mbx);\n\t\tbreak;\n\tcase FM10K_MSG_DISCONNECT:\n\t\terr = fm10k_mbx_process_disconnect(hw, mbx);\n\t\tbreak;\n\tcase FM10K_MSG_ERROR:\n\t\terr = fm10k_mbx_process_error(hw, mbx);\n\t\tbreak;\n\tdefault:\n\t\terr = FM10K_MBX_ERR_TYPE;\n\t\tbreak;\n\t}\n\nmsg_err:\n\t/* notify partner of errors on our end */\n\tif (err < 0)\n\t\tfm10k_mbx_create_error_msg(mbx, err);\n\n\t/* copy data from mailbox */\n\tfm10k_mbx_write(hw, mbx);\n\n\treturn err;\n}\n\n/**\n * fm10k_mbx_disconnect - Shutdown mailbox connection\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function will shut down the mailbox. It places the mailbox first\n * in the disconnect state, it then allows up to a predefined timeout for\n * the mailbox to transition to close on its own. If this does not occur\n * then the mailbox will be forced into the closed state.\n *\n * Any mailbox transactions not completed before calling this function\n * are not guaranteed to complete and may be dropped.\n **/\nSTATIC void fm10k_mbx_disconnect(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tint timeout = mbx->timeout ? FM10K_MBX_DISCONNECT_TIMEOUT : 0;\n\n\tDEBUGFUNC(\"fm10k_mbx_disconnect\");\n\n\t/* Place mbx in ready to disconnect state */\n\tmbx->state = FM10K_STATE_DISCONNECT;\n\n\t/* trigger interrupt to start shutdown process */\n\tFM10K_WRITE_MBX(hw, mbx->mbx_reg, FM10K_MBX_REQ |\n\t\t\t\t\t FM10K_MBX_INTERRUPT_DISABLE);\n\tdo {\n\t\tusec_delay(FM10K_MBX_POLL_DELAY);\n\t\tmbx->ops.process(hw, mbx);\n\t\ttimeout -= FM10K_MBX_POLL_DELAY;\n\t} while ((timeout > 0) && (mbx->state != FM10K_STATE_CLOSED));\n\n\t/* in case we didn't close just force the mailbox into shutdown */\n\tfm10k_mbx_connect_reset(mbx);\n\tfm10k_mbx_update_max_size(mbx, 0);\n\n\tFM10K_WRITE_MBX(hw, mbx->mbmem_reg, 0);\n}\n\n/**\n * fm10k_mbx_connect - Start mailbox connection\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function will initiate a mailbox connection. It will populate the\n * mailbox with a broadcast connect message and then initialize the lock.\n * This is safe since the connect message is a single DWORD so the mailbox\n * transaction is guaranteed to be atomic.\n *\n * This function will return an error if the mailbox has not been initiated\n * or is currently in use.\n **/\nSTATIC s32 fm10k_mbx_connect(struct fm10k_hw *hw, struct fm10k_mbx_info *mbx)\n{\n\tDEBUGFUNC(\"fm10k_mbx_connect\");\n\n\t/* we cannot connect an uninitialized mailbox */\n\tif (!mbx->rx.buffer)\n\t\treturn FM10K_MBX_ERR_NO_SPACE;\n\n\t/* we cannot connect an already connected mailbox */\n\tif (mbx->state != FM10K_STATE_CLOSED)\n\t\treturn FM10K_MBX_ERR_BUSY;\n\n\t/* mailbox timeout can now become active */\n\tmbx->timeout = FM10K_MBX_INIT_TIMEOUT;\n\n\t/* Place mbx in ready to connect state */\n\tmbx->state = FM10K_STATE_CONNECT;\n\n\t/* initialize header of remote mailbox */\n\tfm10k_mbx_create_disconnect_hdr(mbx);\n\tFM10K_WRITE_MBX(hw, mbx->mbmem_reg ^ mbx->mbmem_len, mbx->mbx_hdr);\n\n\t/* enable interrupt and notify other party of new message */\n\tmbx->mbx_lock = FM10K_MBX_REQ_INTERRUPT | FM10K_MBX_ACK_INTERRUPT |\n\t\t\tFM10K_MBX_INTERRUPT_ENABLE;\n\n\t/* generate and load connect header into mailbox */\n\tfm10k_mbx_create_connect_hdr(mbx);\n\tfm10k_mbx_write(hw, mbx);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_mbx_validate_handlers - Validate layout of message parsing data\n * @msg_data: handlers for mailbox events\n *\n * This function validates the layout of the message parsing data. This\n * should be mostly static, but it is important to catch any errors that\n * are made when constructing the parsers.\n **/\nSTATIC s32 fm10k_mbx_validate_handlers(const struct fm10k_msg_data *msg_data)\n{\n\tconst struct fm10k_tlv_attr *attr;\n\tunsigned int id;\n\n\tDEBUGFUNC(\"fm10k_mbx_validate_handlers\");\n\n\t/* Allow NULL mailboxes that transmit but don't receive */\n\tif (!msg_data)\n\t\treturn FM10K_SUCCESS;\n\n\twhile (msg_data->id != FM10K_TLV_ERROR) {\n\t\t/* all messages should have a function handler */\n\t\tif (!msg_data->func)\n\t\t\treturn FM10K_ERR_PARAM;\n\n\t\t/* parser is optional */\n\t\tattr = msg_data->attr;\n\t\tif (attr) {\n\t\t\twhile (attr->id != FM10K_TLV_ERROR) {\n\t\t\t\tid = attr->id;\n\t\t\t\tattr++;\n\t\t\t\t/* ID should always be increasing */\n\t\t\t\tif (id >= attr->id)\n\t\t\t\t\treturn FM10K_ERR_PARAM;\n\t\t\t\t/* ID should fit in results array */\n\t\t\t\tif (id >= FM10K_TLV_RESULTS_MAX)\n\t\t\t\t\treturn FM10K_ERR_PARAM;\n\t\t\t}\n\n\t\t\t/* verify terminator is in the list */\n\t\t\tif (attr->id != FM10K_TLV_ERROR)\n\t\t\t\treturn FM10K_ERR_PARAM;\n\t\t}\n\n\t\tid = msg_data->id;\n\t\tmsg_data++;\n\t\t/* ID should always be increasing */\n\t\tif (id >= msg_data->id)\n\t\t\treturn FM10K_ERR_PARAM;\n\t}\n\n\t/* verify terminator is in the list */\n\tif ((msg_data->id != FM10K_TLV_ERROR) || !msg_data->func)\n\t\treturn FM10K_ERR_PARAM;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_mbx_register_handlers - Register a set of handler ops for mailbox\n * @mbx: pointer to mailbox\n * @msg_data: handlers for mailbox events\n *\n * This function associates a set of message handling ops with a mailbox.\n **/\nSTATIC s32 fm10k_mbx_register_handlers(struct fm10k_mbx_info *mbx,\n\t\t\t\t const struct fm10k_msg_data *msg_data)\n{\n\tDEBUGFUNC(\"fm10k_mbx_register_handlers\");\n\n\t/* validate layout of handlers before assigning them */\n\tif (fm10k_mbx_validate_handlers(msg_data))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* initialize the message handlers */\n\tmbx->msg_data = msg_data;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_pfvf_mbx_init - Initialize mailbox memory for PF/VF mailbox\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n * @msg_data: handlers for mailbox events\n * @id: ID reference for PF as it supports up to 64 PF/VF mailboxes\n *\n * This function initializes the mailbox for use. It will split the\n * buffer provided an use that th populate both the Tx and Rx FIFO by\n * evenly splitting it. In order to allow for easy masking of head/tail\n * the value reported in size must be a power of 2 and is reported in\n * DWORDs, not bytes. Any invalid values will cause the mailbox to return\n * error.\n **/\ns32 fm10k_pfvf_mbx_init(struct fm10k_hw *hw, struct fm10k_mbx_info *mbx,\n\t\t\tconst struct fm10k_msg_data *msg_data, u8 id)\n{\n\tDEBUGFUNC(\"fm10k_pfvf_mbx_init\");\n\n\t/* initialize registers */\n\tswitch (hw->mac.type) {\n\tcase fm10k_mac_vf:\n\t\tmbx->mbx_reg = FM10K_VFMBX;\n\t\tmbx->mbmem_reg = FM10K_VFMBMEM(FM10K_VFMBMEM_VF_XOR);\n\t\tbreak;\n\tcase fm10k_mac_pf:\n\t\t/* there are only 64 VF <-> PF mailboxes */\n\t\tif (id < 64) {\n\t\t\tmbx->mbx_reg = FM10K_MBX(id);\n\t\t\tmbx->mbmem_reg = FM10K_MBMEM_VF(id, 0);\n\t\t\tbreak;\n\t\t}\n\t\t/* fallthough */\n\tdefault:\n\t\treturn FM10K_MBX_ERR_NO_MBX;\n\t}\n\n\t/* start out in closed state */\n\tmbx->state = FM10K_STATE_CLOSED;\n\n\t/* validate layout of handlers before assigning them */\n\tif (fm10k_mbx_validate_handlers(msg_data))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* initialize the message handlers */\n\tmbx->msg_data = msg_data;\n\n\t/* start mailbox as timed out and let the reset_hw call\n\t * set the timeout value to begin communications\n\t */\n\tmbx->timeout = 0;\n\tmbx->usec_delay = FM10K_MBX_INIT_DELAY;\n\n\t/* initialize tail and head */\n\tmbx->tail = 1;\n\tmbx->head = 1;\n\n\t/* initialize CRC seeds */\n\tmbx->local = FM10K_MBX_CRC_SEED;\n\tmbx->remote = FM10K_MBX_CRC_SEED;\n\n\t/* Split buffer for use by Tx/Rx FIFOs */\n\tmbx->max_size = FM10K_MBX_MSG_MAX_SIZE;\n\tmbx->mbmem_len = FM10K_VFMBMEM_VF_XOR;\n\n\t/* initialize the FIFOs, sizes are in 4 byte increments */\n\tfm10k_fifo_init(&mbx->tx, mbx->buffer, FM10K_MBX_TX_BUFFER_SIZE);\n\tfm10k_fifo_init(&mbx->rx, &mbx->buffer[FM10K_MBX_TX_BUFFER_SIZE],\n\t\t\tFM10K_MBX_RX_BUFFER_SIZE);\n\n\t/* initialize function pointers */\n\tmbx->ops.connect = fm10k_mbx_connect;\n\tmbx->ops.disconnect = fm10k_mbx_disconnect;\n\tmbx->ops.rx_ready = fm10k_mbx_rx_ready;\n\tmbx->ops.tx_ready = fm10k_mbx_tx_ready;\n\tmbx->ops.tx_complete = fm10k_mbx_tx_complete;\n\tmbx->ops.enqueue_tx = fm10k_mbx_enqueue_tx;\n\tmbx->ops.process = fm10k_mbx_process;\n\tmbx->ops.register_handlers = fm10k_mbx_register_handlers;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_sm_mbx_create_data_hdr - Generate a mailbox header for local FIFO\n * @mbx: pointer to mailbox\n *\n * This function returns a connection mailbox header\n **/\nSTATIC void fm10k_sm_mbx_create_data_hdr(struct fm10k_mbx_info *mbx)\n{\n\tif (mbx->tail_len)\n\t\tmbx->mbx_lock |= FM10K_MBX_REQ;\n\n\tmbx->mbx_hdr = FM10K_MSG_HDR_FIELD_SET(mbx->tail, SM_TAIL) |\n\t\t FM10K_MSG_HDR_FIELD_SET(mbx->remote, SM_VER) |\n\t\t FM10K_MSG_HDR_FIELD_SET(mbx->head, SM_HEAD);\n}\n\n/**\n * fm10k_sm_mbx_create_connect_hdr - Generate a mailbox header for local FIFO\n * @mbx: pointer to mailbox\n * @err: error flags to report if any\n *\n * This function returns a connection mailbox header\n **/\nSTATIC void fm10k_sm_mbx_create_connect_hdr(struct fm10k_mbx_info *mbx, u8 err)\n{\n\tif (mbx->local)\n\t\tmbx->mbx_lock |= FM10K_MBX_REQ;\n\n\tmbx->mbx_hdr = FM10K_MSG_HDR_FIELD_SET(mbx->tail, SM_TAIL) |\n\t\t FM10K_MSG_HDR_FIELD_SET(mbx->remote, SM_VER) |\n\t\t FM10K_MSG_HDR_FIELD_SET(mbx->head, SM_HEAD) |\n\t\t FM10K_MSG_HDR_FIELD_SET(err, SM_ERR);\n}\n\n/**\n * fm10k_sm_mbx_connect_reset - Reset following request for reset\n * @mbx: pointer to mailbox\n *\n * This function resets the mailbox to a just connected state\n **/\nSTATIC void fm10k_sm_mbx_connect_reset(struct fm10k_mbx_info *mbx)\n{\n\t/* flush any uncompleted work */\n\tfm10k_mbx_reset_work(mbx);\n\n\t/* set local version to max and remote version to 0 */\n\tmbx->local = FM10K_SM_MBX_VERSION;\n\tmbx->remote = 0;\n\n\t/* initialize tail and head */\n\tmbx->tail = 1;\n\tmbx->head = 1;\n\n\t/* reset state back to connect */\n\tmbx->state = FM10K_STATE_CONNECT;\n}\n\n/**\n * fm10k_sm_mbx_connect - Start switch manager mailbox connection\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function will initiate a mailbox connection with the switch\n * manager. To do this it will first disconnect the mailbox, and then\n * reconnect it in order to complete a reset of the mailbox.\n *\n * This function will return an error if the mailbox has not been initiated\n * or is currently in use.\n **/\nSTATIC s32 fm10k_sm_mbx_connect(struct fm10k_hw *hw, struct fm10k_mbx_info *mbx)\n{\n\tDEBUGFUNC(\"fm10k_mbx_connect\");\n\n\t/* we cannot connect an uninitialized mailbox */\n\tif (!mbx->rx.buffer)\n\t\treturn FM10K_MBX_ERR_NO_SPACE;\n\n\t/* we cannot connect an already connected mailbox */\n\tif (mbx->state != FM10K_STATE_CLOSED)\n\t\treturn FM10K_MBX_ERR_BUSY;\n\n\t/* mailbox timeout can now become active */\n\tmbx->timeout = FM10K_MBX_INIT_TIMEOUT;\n\n\t/* Place mbx in ready to connect state */\n\tmbx->state = FM10K_STATE_CONNECT;\n\tmbx->max_size = FM10K_MBX_MSG_MAX_SIZE;\n\n\t/* reset interface back to connect */\n\tfm10k_sm_mbx_connect_reset(mbx);\n\n\t/* enable interrupt and notify other party of new message */\n\tmbx->mbx_lock = FM10K_MBX_REQ_INTERRUPT | FM10K_MBX_ACK_INTERRUPT |\n\t\t\tFM10K_MBX_INTERRUPT_ENABLE;\n\n\t/* generate and load connect header into mailbox */\n\tfm10k_sm_mbx_create_connect_hdr(mbx, 0);\n\tfm10k_mbx_write(hw, mbx);\n\n\t/* enable interrupt and notify other party of new message */\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_sm_mbx_disconnect - Shutdown mailbox connection\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function will shut down the mailbox. It places the mailbox first\n * in the disconnect state, it then allows up to a predefined timeout for\n * the mailbox to transition to close on its own. If this does not occur\n * then the mailbox will be forced into the closed state.\n *\n * Any mailbox transactions not completed before calling this function\n * are not guaranteed to complete and may be dropped.\n **/\nSTATIC void fm10k_sm_mbx_disconnect(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tint timeout = mbx->timeout ? FM10K_MBX_DISCONNECT_TIMEOUT : 0;\n\n\tDEBUGFUNC(\"fm10k_sm_mbx_disconnect\");\n\n\t/* Place mbx in ready to disconnect state */\n\tmbx->state = FM10K_STATE_DISCONNECT;\n\n\t/* trigger interrupt to start shutdown process */\n\tFM10K_WRITE_REG(hw, mbx->mbx_reg, FM10K_MBX_REQ |\n\t\t\t\t\t FM10K_MBX_INTERRUPT_DISABLE);\n\tdo {\n\t\tusec_delay(FM10K_MBX_POLL_DELAY);\n\t\tmbx->ops.process(hw, mbx);\n\t\ttimeout -= FM10K_MBX_POLL_DELAY;\n\t} while ((timeout > 0) && (mbx->state != FM10K_STATE_CLOSED));\n\n\t/* in case we didn't close just force the mailbox into shutdown */\n\tmbx->state = FM10K_STATE_CLOSED;\n\tmbx->remote = 0;\n\tfm10k_mbx_reset_work(mbx);\n\tfm10k_mbx_update_max_size(mbx, 0);\n\n\tFM10K_WRITE_REG(hw, mbx->mbmem_reg, 0);\n}\n\n/**\n * fm10k_mbx_validate_fifo_hdr - Validate fields in the remote FIFO header\n * @mbx: pointer to mailbox\n *\n * This function will parse up the fields in the mailbox header and return\n * an error if the header contains any of a number of invalid configurations\n * including unrecognized offsets or version numbers.\n **/\nSTATIC s32 fm10k_sm_mbx_validate_fifo_hdr(struct fm10k_mbx_info *mbx)\n{\n\tconst u32 *hdr = &mbx->mbx_hdr;\n\tu16 tail, head, ver;\n\n\tDEBUGFUNC(\"fm10k_mbx_validate_msg_hdr\");\n\n\ttail = FM10K_MSG_HDR_FIELD_GET(*hdr, SM_TAIL);\n\tver = FM10K_MSG_HDR_FIELD_GET(*hdr, SM_VER);\n\thead = FM10K_MSG_HDR_FIELD_GET(*hdr, SM_HEAD);\n\n\tswitch (ver) {\n\tcase 0:\n\t\tbreak;\n\tcase FM10K_SM_MBX_VERSION:\n\t\tif (!head || head > FM10K_SM_MBX_FIFO_LEN)\n\t\t\treturn FM10K_MBX_ERR_HEAD;\n\t\tif (!tail || tail > FM10K_SM_MBX_FIFO_LEN)\n\t\t\treturn FM10K_MBX_ERR_TAIL;\n\t\tif (mbx->tail < head)\n\t\t\thead += mbx->mbmem_len - 1;\n\t\tif (tail < mbx->head)\n\t\t\ttail += mbx->mbmem_len - 1;\n\t\tif (fm10k_mbx_index_len(mbx, head, mbx->tail) > mbx->tail_len)\n\t\t\treturn FM10K_MBX_ERR_HEAD;\n\t\tif (fm10k_mbx_index_len(mbx, mbx->head, tail) < mbx->mbmem_len)\n\t\t\tbreak;\n\t\treturn FM10K_MBX_ERR_TAIL;\n\tdefault:\n\t\treturn FM10K_MBX_ERR_SRC;\n\t}\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_sm_mbx_process_error - Process header with error flag set\n * @mbx: pointer to mailbox\n *\n * This function is meant to respond to a request where the error flag\n * is set. As a result we will terminate a connection if one is present\n * and fall back into the reset state with a connection header of version\n * 0 (RESET).\n **/\nSTATIC void fm10k_sm_mbx_process_error(struct fm10k_mbx_info *mbx)\n{\n\tconst enum fm10k_mbx_state state = mbx->state;\n\n\tswitch (state) {\n\tcase FM10K_STATE_DISCONNECT:\n\t\t/* if there is an error just disconnect */\n\t\tmbx->remote = 0;\n\t\tbreak;\n\tcase FM10K_STATE_OPEN:\n\t\t/* flush any uncompleted work */\n\t\tfm10k_sm_mbx_connect_reset(mbx);\n\t\tbreak;\n\tcase FM10K_STATE_CONNECT:\n\t\t/* try connnecting at lower version */\n\t\tif (mbx->remote) {\n\t\t\twhile (mbx->local > 1)\n\t\t\t\tmbx->local--;\n\t\t\tmbx->remote = 0;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tfm10k_sm_mbx_create_connect_hdr(mbx, 0);\n}\n\n/**\n * fm10k_sm_mbx_create_error_message - Process an error in FIFO hdr\n * @mbx: pointer to mailbox\n * @err: local error encountered\n *\n * This function will interpret the error provided by err, and based on\n * that it may set the error bit in the local message header\n **/\nSTATIC void fm10k_sm_mbx_create_error_msg(struct fm10k_mbx_info *mbx, s32 err)\n{\n\t/* only generate an error message for these types */\n\tswitch (err) {\n\tcase FM10K_MBX_ERR_TAIL:\n\tcase FM10K_MBX_ERR_HEAD:\n\tcase FM10K_MBX_ERR_SRC:\n\tcase FM10K_MBX_ERR_SIZE:\n\tcase FM10K_MBX_ERR_RSVD0:\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\t/* process it as though we received an error, and send error reply */\n\tfm10k_sm_mbx_process_error(mbx);\n\tfm10k_sm_mbx_create_connect_hdr(mbx, 1);\n}\n\n/**\n * fm10k_sm_mbx_receive - Take message from Rx mailbox FIFO and put it in Rx\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function will dequeue one message from the Rx switch manager mailbox\n * FIFO and place it in the Rx mailbox FIFO for processing by software.\n **/\nSTATIC s32 fm10k_sm_mbx_receive(struct fm10k_hw *hw,\n\t\t\t\tstruct fm10k_mbx_info *mbx,\n\t\t\t\tu16 tail)\n{\n\t/* reduce length by 1 to convert to a mask */\n\tu16 mbmem_len = mbx->mbmem_len - 1;\n\ts32 err;\n\n\tDEBUGFUNC(\"fm10k_sm_mbx_receive\");\n\n\t/* push tail in front of head */\n\tif (tail < mbx->head)\n\t\ttail += mbmem_len;\n\n\t/* copy data to the Rx FIFO */\n\terr = fm10k_mbx_push_tail(hw, mbx, tail);\n\tif (err < 0)\n\t\treturn err;\n\n\t/* process messages if we have received any */\n\tfm10k_mbx_dequeue_rx(hw, mbx);\n\n\t/* guarantee head aligns with the end of the last message */\n\tmbx->head = fm10k_mbx_head_sub(mbx, mbx->pushed);\n\tmbx->pushed = 0;\n\n\t/* clear any extra bits left over since index adds 1 extra bit */\n\tif (mbx->head > mbmem_len)\n\t\tmbx->head -= mbmem_len;\n\n\treturn err;\n}\n\n/**\n * fm10k_sm_mbx_transmit - Take message from Tx and put it in Tx mailbox FIFO\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function will dequeue one message from the Tx mailbox FIFO and place\n * it in the Tx switch manager mailbox FIFO for processing by hardware.\n **/\nSTATIC void fm10k_sm_mbx_transmit(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_mbx_info *mbx, u16 head)\n{\n\tstruct fm10k_mbx_fifo *fifo = &mbx->tx;\n\t/* reduce length by 1 to convert to a mask */\n\tu16 mbmem_len = mbx->mbmem_len - 1;\n\tu16 tail_len, len = 0;\n\tu32 *msg;\n\n\tDEBUGFUNC(\"fm10k_sm_mbx_transmit\");\n\n\t/* push head behind tail */\n\tif (mbx->tail < head)\n\t\thead += mbmem_len;\n\n\tfm10k_mbx_pull_head(hw, mbx, head);\n\n\t/* determine msg aligned offset for end of buffer */\n\tdo {\n\t\tmsg = fifo->buffer + fm10k_fifo_head_offset(fifo, len);\n\t\ttail_len = len;\n\t\tlen += FM10K_TLV_DWORD_LEN(*msg);\n\t} while ((len <= mbx->tail_len) && (len < mbmem_len));\n\n\t/* guarantee we stop on a message boundary */\n\tif (mbx->tail_len > tail_len) {\n\t\tmbx->tail = fm10k_mbx_tail_sub(mbx, mbx->tail_len - tail_len);\n\t\tmbx->tail_len = tail_len;\n\t}\n\n\t/* clear any extra bits left over since index adds 1 extra bit */\n\tif (mbx->tail > mbmem_len)\n\t\tmbx->tail -= mbmem_len;\n}\n\n/**\n * fm10k_sm_mbx_create_reply - Generate reply based on state and remote head\n * @mbx: pointer to mailbox\n * @head: acknowledgement number\n *\n * This function will generate an outgoing message based on the current\n * mailbox state and the remote fifo head. It will return the length\n * of the outgoing message excluding header on success, and a negative value\n * on error.\n **/\nSTATIC void fm10k_sm_mbx_create_reply(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_mbx_info *mbx, u16 head)\n{\n\tswitch (mbx->state) {\n\tcase FM10K_STATE_OPEN:\n\tcase FM10K_STATE_DISCONNECT:\n\t\t/* flush out Tx data */\n\t\tfm10k_sm_mbx_transmit(hw, mbx, head);\n\n\t\t/* generate new header based on data */\n\t\tif (mbx->tail_len || (mbx->state == FM10K_STATE_OPEN)) {\n\t\t\tfm10k_sm_mbx_create_data_hdr(mbx);\n\t\t} else {\n\t\t\tmbx->remote = 0;\n\t\t\tfm10k_sm_mbx_create_connect_hdr(mbx, 0);\n\t\t}\n\t\tbreak;\n\tcase FM10K_STATE_CONNECT:\n\tcase FM10K_STATE_CLOSED:\n\t\tfm10k_sm_mbx_create_connect_hdr(mbx, 0);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n/**\n * fm10k_sm_mbx_process_reset - Process header with version == 0 (RESET)\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function is meant to respond to a request where the version data\n * is set to 0. As such we will either terminate the connection or go\n * into the connect state in order to re-establish the connection. This\n * function can also be used to respond to an error as the connection\n * resetting would also be a means of dealing with errors.\n **/\nSTATIC void fm10k_sm_mbx_process_reset(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tconst enum fm10k_mbx_state state = mbx->state;\n\n\tswitch (state) {\n\tcase FM10K_STATE_DISCONNECT:\n\t\t/* drop remote connections and disconnect */\n\t\tmbx->state = FM10K_STATE_CLOSED;\n\t\tmbx->remote = 0;\n\t\tmbx->local = 0;\n\t\tbreak;\n\tcase FM10K_STATE_OPEN:\n\t\t/* flush any incomplete work */\n\t\tfm10k_sm_mbx_connect_reset(mbx);\n\t\tbreak;\n\tcase FM10K_STATE_CONNECT:\n\t\t/* Update remote value to match local value */\n\t\tmbx->remote = mbx->local;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tfm10k_sm_mbx_create_reply(hw, mbx, mbx->tail);\n}\n\n/**\n * fm10k_sm_mbx_process_version_1 - Process header with version == 1\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function is meant to process messages received when the remote\n * mailbox is active.\n **/\nSTATIC s32 fm10k_sm_mbx_process_version_1(struct fm10k_hw *hw,\n\t\t\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tconst u32 *hdr = &mbx->mbx_hdr;\n\tu16 head, tail;\n\ts32 len;\n\n\t/* pull all fields needed for verification */\n\ttail = FM10K_MSG_HDR_FIELD_GET(*hdr, SM_TAIL);\n\thead = FM10K_MSG_HDR_FIELD_GET(*hdr, SM_HEAD);\n\n\t/* if we are in connect and wanting version 1 then start up and go */\n\tif (mbx->state == FM10K_STATE_CONNECT) {\n\t\tif (!mbx->remote)\n\t\t\tgoto send_reply;\n\t\tif (mbx->remote != 1)\n\t\t\treturn FM10K_MBX_ERR_SRC;\n\n\t\tmbx->state = FM10K_STATE_OPEN;\n\t}\n\n\tdo {\n\t\t/* abort on message size errors */\n\t\tlen = fm10k_sm_mbx_receive(hw, mbx, tail);\n\t\tif (len < 0)\n\t\t\treturn len;\n\n\t\t/* continue until we have flushed the Rx FIFO */\n\t} while (len);\n\nsend_reply:\n\tfm10k_sm_mbx_create_reply(hw, mbx, head);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_sm_mbx_process - Process mailbox switch mailbox interrupt\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n *\n * This function will process incoming mailbox events and generate mailbox\n * replies. It will return a value indicating the number of DWORDs\n * transmitted excluding header on success or a negative value on error.\n **/\nSTATIC s32 fm10k_sm_mbx_process(struct fm10k_hw *hw,\n\t\t\t\tstruct fm10k_mbx_info *mbx)\n{\n\ts32 err;\n\n\tDEBUGFUNC(\"fm10k_sm_mbx_process\");\n\n\t/* we do not read mailbox if closed */\n\tif (mbx->state == FM10K_STATE_CLOSED)\n\t\treturn FM10K_SUCCESS;\n\n\t/* retrieve data from switch manager */\n\terr = fm10k_mbx_read(hw, mbx);\n\tif (err)\n\t\treturn err;\n\n\terr = fm10k_sm_mbx_validate_fifo_hdr(mbx);\n\tif (err < 0)\n\t\tgoto fifo_err;\n\n\tif (FM10K_MSG_HDR_FIELD_GET(mbx->mbx_hdr, SM_ERR)) {\n\t\tfm10k_sm_mbx_process_error(mbx);\n\t\tgoto fifo_err;\n\t}\n\n\tswitch (FM10K_MSG_HDR_FIELD_GET(mbx->mbx_hdr, SM_VER)) {\n\tcase 0:\n\t\tfm10k_sm_mbx_process_reset(hw, mbx);\n\t\tbreak;\n\tcase FM10K_SM_MBX_VERSION:\n\t\terr = fm10k_sm_mbx_process_version_1(hw, mbx);\n\t\tbreak;\n\t}\n\nfifo_err:\n\tif (err < 0)\n\t\tfm10k_sm_mbx_create_error_msg(mbx, err);\n\n\t/* report data to switch manager */\n\tfm10k_mbx_write(hw, mbx);\n\n\treturn err;\n}\n\n/**\n * fm10k_sm_mbx_init - Initialize mailbox memory for PF/SM mailbox\n * @hw: pointer to hardware structure\n * @mbx: pointer to mailbox\n * @msg_data: handlers for mailbox events\n *\n * This function for now is used to stub out the PF/SM mailbox\n **/\ns32 fm10k_sm_mbx_init(struct fm10k_hw *hw, struct fm10k_mbx_info *mbx,\n\t\t const struct fm10k_msg_data *msg_data)\n{\n\tDEBUGFUNC(\"fm10k_sm_mbx_init\");\n\tUNREFERENCED_1PARAMETER(hw);\n\n\tmbx->mbx_reg = FM10K_GMBX;\n\tmbx->mbmem_reg = FM10K_MBMEM_PF(0);\n\n\t/* start out in closed state */\n\tmbx->state = FM10K_STATE_CLOSED;\n\n\t/* validate layout of handlers before assigning them */\n\tif (fm10k_mbx_validate_handlers(msg_data))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* initialize the message handlers */\n\tmbx->msg_data = msg_data;\n\n\t/* start mailbox as timed out and let the reset_hw call\n\t * set the timeout value to begin communications\n\t */\n\tmbx->timeout = 0;\n\tmbx->usec_delay = FM10K_MBX_INIT_DELAY;\n\n\t/* Split buffer for use by Tx/Rx FIFOs */\n\tmbx->max_size = FM10K_MBX_MSG_MAX_SIZE;\n\tmbx->mbmem_len = FM10K_MBMEM_PF_XOR;\n\n\t/* initialize the FIFOs, sizes are in 4 byte increments */\n\tfm10k_fifo_init(&mbx->tx, mbx->buffer, FM10K_MBX_TX_BUFFER_SIZE);\n\tfm10k_fifo_init(&mbx->rx, &mbx->buffer[FM10K_MBX_TX_BUFFER_SIZE],\n\t\t\tFM10K_MBX_RX_BUFFER_SIZE);\n\n\t/* initialize function pointers */\n\tmbx->ops.connect = fm10k_sm_mbx_connect;\n\tmbx->ops.disconnect = fm10k_sm_mbx_disconnect;\n\tmbx->ops.rx_ready = fm10k_mbx_rx_ready;\n\tmbx->ops.tx_ready = fm10k_mbx_tx_ready;\n\tmbx->ops.tx_complete = fm10k_mbx_tx_complete;\n\tmbx->ops.enqueue_tx = fm10k_mbx_enqueue_tx;\n\tmbx->ops.process = fm10k_sm_mbx_process;\n\tmbx->ops.register_handlers = fm10k_mbx_register_handlers;\n\n\treturn FM10K_SUCCESS;\n}\n" }, { "path": "drivers/net/fm10k/base/fm10k_mbx.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _FM10K_MBX_H_\n#define _FM10K_MBX_H_\n\n/* forward declaration */\nstruct fm10k_mbx_info;\n\n#include \"fm10k_type.h\"\n#include \"fm10k_tlv.h\"\n\n/* PF Mailbox Registers */\n#define FM10K_MBMEM(_n)\t\t((_n) + 0x18000)\n#define FM10K_MBMEM_VF(_n, _m)\t(((_n) * 0x10) + (_m) + 0x18000)\n#define FM10K_MBMEM_SM(_n)\t((_n) + 0x18400)\n#define FM10K_MBMEM_PF(_n)\t((_n) + 0x18600)\n/* XOR provides means of switching from Tx to Rx FIFO */\n#define FM10K_MBMEM_PF_XOR\t(FM10K_MBMEM_SM(0) ^ FM10K_MBMEM_PF(0))\n#define FM10K_MBX(_n)\t\t((_n) + 0x18800)\n#define FM10K_MBX_OWNER\t\t\t\t0x00000001\n#define FM10K_MBX_REQ\t\t\t\t0x00000002\n#define FM10K_MBX_ACK\t\t\t\t0x00000004\n#define FM10K_MBX_REQ_INTERRUPT\t\t\t0x00000008\n#define FM10K_MBX_ACK_INTERRUPT\t\t\t0x00000010\n#define FM10K_MBX_INTERRUPT_ENABLE\t\t0x00000020\n#define FM10K_MBX_INTERRUPT_DISABLE\t\t0x00000040\n#define FM10K_MBICR(_n)\t\t((_n) + 0x18840)\n#define FM10K_GMBX\t\t0x18842\n\n/* VF Mailbox Registers */\n#define FM10K_VFMBX\t\t0x00010\n#define FM10K_VFMBMEM(_n)\t((_n) + 0x00020)\n#define FM10K_VFMBMEM_LEN\t16\n#define FM10K_VFMBMEM_VF_XOR\t(FM10K_VFMBMEM_LEN / 2)\n\n/* Delays/timeouts */\n#define FM10K_MBX_DISCONNECT_TIMEOUT\t\t500\n#define FM10K_MBX_POLL_DELAY\t\t\t19\n#define FM10K_MBX_INT_DELAY\t\t\t20\n\n#define FM10K_WRITE_MBX(hw, reg, value) FM10K_WRITE_REG(hw, reg, value)\n\n/* PF/VF Mailbox state machine\n *\n * +----------+\t connect()\t+----------+\n * | CLOSED | --------------> | CONNECT |\n * +----------+\t\t\t+----------+\n * ^\t\t\t\t ^\t |\n * | rcv:\t rcv:\t |\t | rcv:\n * | Connect\t Disconnect |\t | Connect\n * | Disconnect Error\t |\t | Data\n * |\t\t\t\t |\t |\n * |\t\t\t\t |\t V\n * +----------+ disconnect()\t+----------+\n * |DISCONNECT| <-------------- | OPEN |\n * +----------+\t\t\t+----------+\n *\n * The diagram above describes the PF/VF mailbox state machine. There\n * are four main states to this machine.\n * Closed: This state represents a mailbox that is in a standby state\n *\t with interrupts disabled. In this state the mailbox should not\n *\t read the mailbox or write any data. The only means of exiting\n *\t this state is for the system to make the connect() call for the\n *\t mailbox, it will then transition to the connect state.\n * Connect: In this state the mailbox is seeking a connection. It will\n *\t post a connect message with no specified destination and will\n *\t wait for a reply from the other side of the mailbox. This state\n *\t is exited when either a connect with the local mailbox as the\n *\t destination is received or when a data message is received with\n *\t a valid sequence number.\n * Open: In this state the mailbox is able to transfer data between the local\n * entity and the remote. It will fall back to connect in the event of\n * receiving either an error message, or a disconnect message. It will\n * transition to disconnect on a call to disconnect();\n * Disconnect: In this state the mailbox is attempting to gracefully terminate\n *\t the connection. It will do so at the first point where it knows\n *\t that the remote endpoint is either done sending, or when the\n *\t remote endpoint has fallen back into connect.\n */\nenum fm10k_mbx_state {\n\tFM10K_STATE_CLOSED,\n\tFM10K_STATE_CONNECT,\n\tFM10K_STATE_OPEN,\n\tFM10K_STATE_DISCONNECT,\n};\n\n/* PF/VF Mailbox header format\n * 3\t\t\t 2\t\t 1\t\t\t 0\n * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0\n * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n * | Size/Err_no/CRC | Rsvd0 | Head | Tail | Type |\n * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n *\n * The layout above describes the format for the header used in the PF/VF\n * mailbox. The header is broken out into the following fields:\n * Type: There are 4 supported message types\n *\t\t0x8: Data header - used to transport message data\n *\t\t0xC: Connect header - used to establish connection\n *\t\t0xD: Disconnect header - used to tear down a connection\n *\t\t0xE: Error header - used to address message exceptions\n * Tail: Tail index for local FIFO\n *\t\tTail index actually consists of two parts. The MSB of\n *\t\tthe head is a loop tracker, it is 0 on an even numbered\n *\t\tloop through the FIFO, and 1 on the odd numbered loops.\n *\t\tTo get the actual mailbox offset based on the tail it\n *\t\tis necessary to add bit 3 to bit 0 and clear bit 3. This\n *\t\tgives us a valid range of 0x1 - 0xE.\n * Head: Head index for remote FIFO\n *\t\tHead index follows the same format as the tail index.\n * Rsvd0: Reserved 0 portion of the mailbox header\n * CRC: Running CRC for all data since connect plus current message header\n * Size: Maximum message size - Applies only to connect headers\n *\t\tThe maximum message size is provided during connect to avoid\n *\t\tjamming the mailbox with messages that do not fit.\n * Err_no: Error number - Applies only to error headers\n *\t\tThe error number provides a indication of the type of error\n *\t\texperienced.\n */\n\n/* macros for retriving and setting header values */\n#define FM10K_MSG_HDR_MASK(name) \\\n\t((0x1u << FM10K_MSG_##name##_SIZE) - 1)\n#define FM10K_MSG_HDR_FIELD_SET(value, name) \\\n\t(((u32)(value) & FM10K_MSG_HDR_MASK(name)) << FM10K_MSG_##name##_SHIFT)\n#define FM10K_MSG_HDR_FIELD_GET(value, name) \\\n\t((u16)((value) >> FM10K_MSG_##name##_SHIFT) & FM10K_MSG_HDR_MASK(name))\n\n/* offsets shared between all headers */\n#define FM10K_MSG_TYPE_SHIFT\t\t\t0\n#define FM10K_MSG_TYPE_SIZE\t\t\t4\n#define FM10K_MSG_TAIL_SHIFT\t\t\t4\n#define FM10K_MSG_TAIL_SIZE\t\t\t4\n#define FM10K_MSG_HEAD_SHIFT\t\t\t8\n#define FM10K_MSG_HEAD_SIZE\t\t\t4\n#define FM10K_MSG_RSVD0_SHIFT\t\t\t12\n#define FM10K_MSG_RSVD0_SIZE\t\t\t4\n\n/* offsets for data/disconnect headers */\n#define FM10K_MSG_CRC_SHIFT\t\t\t16\n#define FM10K_MSG_CRC_SIZE\t\t\t16\n\n/* offsets for connect headers */\n#define FM10K_MSG_CONNECT_SIZE_SHIFT\t\t16\n#define FM10K_MSG_CONNECT_SIZE_SIZE\t\t16\n\n/* offsets for error headers */\n#define FM10K_MSG_ERR_NO_SHIFT\t\t\t16\n#define FM10K_MSG_ERR_NO_SIZE\t\t\t16\n\nenum fm10k_msg_type {\n\tFM10K_MSG_DATA\t\t\t= 0x8,\n\tFM10K_MSG_CONNECT\t\t= 0xC,\n\tFM10K_MSG_DISCONNECT\t\t= 0xD,\n\tFM10K_MSG_ERROR\t\t\t= 0xE,\n};\n\n/* HNI/SM Mailbox FIFO format\n * 3 2 1 0\n * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0\n * +-------+-----------------------+-------+-----------------------+\n * | Error | Remote Head |Version| Local Tail |\n * +-------+-----------------------+-------+-----------------------+\n * | |\n * . Local FIFO Data .\n * . .\n * +-------+-----------------------+-------+-----------------------+\n *\n * The layout above describes the format for the FIFOs used by the host\n * network interface and the switch manager to communicate messages back\n * and forth. Both the HNI and the switch maintain one such FIFO. The\n * layout in memory has the switch manager FIFO followed immediately by\n * the HNI FIFO. For this reason I am using just the pointer to the\n * HNI FIFO in the mailbox ops as the offset between the two is fixed.\n *\n * The header for the FIFO is broken out into the following fields:\n * Local Tail: Offset into FIFO region for next DWORD to write.\n * Version: Version info for mailbox, only values of 0/1 are supported.\n * Remote Head: Offset into remote FIFO to indicate how much we have read.\n * Error: Error indication, values TBD.\n */\n\n/* version number for switch manager mailboxes */\n#define FM10K_SM_MBX_VERSION\t\t1\n#define FM10K_SM_MBX_FIFO_LEN\t\t(FM10K_MBMEM_PF_XOR - 1)\n#define FM10K_SM_MBX_FIFO_HDR_LEN\t1\n\n/* offsets shared between all SM FIFO headers */\n#define FM10K_MSG_SM_TAIL_SHIFT\t\t\t0\n#define FM10K_MSG_SM_TAIL_SIZE\t\t\t12\n#define FM10K_MSG_SM_VER_SHIFT\t\t\t12\n#define FM10K_MSG_SM_VER_SIZE\t\t\t4\n#define FM10K_MSG_SM_HEAD_SHIFT\t\t\t16\n#define FM10K_MSG_SM_HEAD_SIZE\t\t\t12\n#define FM10K_MSG_SM_ERR_SHIFT\t\t\t28\n#define FM10K_MSG_SM_ERR_SIZE\t\t\t4\n\n/* All error messages returned by mailbox functions\n * The value -511 is 0xFE01 in hex. The idea is to order the errors\n * from 0xFE01 - 0xFEFF so error codes are easily visible in the mailbox\n * messages. This also helps to avoid error number collisions as Linux\n * doesn't appear to use error numbers 256 - 511.\n */\n#define FM10K_MBX_ERR(_n) ((_n) - 512)\n#define FM10K_MBX_ERR_NO_MBX\t\tFM10K_MBX_ERR(0x01)\n#define FM10K_MBX_ERR_NO_MSG\t\tFM10K_MBX_ERR(0x02)\n#define FM10K_MBX_ERR_NO_SPACE\t\tFM10K_MBX_ERR(0x03)\n#define FM10K_MBX_ERR_LOCK\t\tFM10K_MBX_ERR(0x04)\n#define FM10K_MBX_ERR_TAIL\t\tFM10K_MBX_ERR(0x05)\n#define FM10K_MBX_ERR_HEAD\t\tFM10K_MBX_ERR(0x06)\n#define FM10K_MBX_ERR_DST\t\tFM10K_MBX_ERR(0x07)\n#define FM10K_MBX_ERR_SRC\t\tFM10K_MBX_ERR(0x08)\n#define FM10K_MBX_ERR_TYPE\t\tFM10K_MBX_ERR(0x09)\n#define FM10K_MBX_ERR_LEN\t\tFM10K_MBX_ERR(0x0A)\n#define FM10K_MBX_ERR_SIZE\t\tFM10K_MBX_ERR(0x0B)\n#define FM10K_MBX_ERR_BUSY\t\tFM10K_MBX_ERR(0x0C)\n#define FM10K_MBX_ERR_VALUE\t\tFM10K_MBX_ERR(0x0D)\n#define FM10K_MBX_ERR_RSVD0\t\tFM10K_MBX_ERR(0x0E)\n#define FM10K_MBX_ERR_CRC\t\tFM10K_MBX_ERR(0x0F)\n\n#define FM10K_MBX_CRC_SEED\t\t0xFFFF\n\nstruct fm10k_mbx_ops {\n\ts32 (*connect)(struct fm10k_hw *, struct fm10k_mbx_info *);\n\tvoid (*disconnect)(struct fm10k_hw *, struct fm10k_mbx_info *);\n\tbool (*rx_ready)(struct fm10k_mbx_info *);\n\tbool (*tx_ready)(struct fm10k_mbx_info *, u16);\n\tbool (*tx_complete)(struct fm10k_mbx_info *);\n\ts32 (*enqueue_tx)(struct fm10k_hw *, struct fm10k_mbx_info *,\n\t\t\t const u32 *);\n\ts32 (*process)(struct fm10k_hw *, struct fm10k_mbx_info *);\n\ts32 (*register_handlers)(struct fm10k_mbx_info *,\n\t\t\t\t const struct fm10k_msg_data *);\n};\n\nstruct fm10k_mbx_fifo {\n\tu32 *buffer;\n\tu16 head;\n\tu16 tail;\n\tu16 size;\n};\n\n/* size of buffer to be stored in mailbox for FIFOs */\n#define FM10K_MBX_TX_BUFFER_SIZE\t512\n#define FM10K_MBX_RX_BUFFER_SIZE\t128\n#define FM10K_MBX_BUFFER_SIZE \\\n\t(FM10K_MBX_TX_BUFFER_SIZE + FM10K_MBX_RX_BUFFER_SIZE)\n\n/* minimum and maximum message size in dwords */\n#define FM10K_MBX_MSG_MAX_SIZE \\\n\t((FM10K_MBX_TX_BUFFER_SIZE - 1) & (FM10K_MBX_RX_BUFFER_SIZE - 1))\n#define FM10K_VFMBX_MSG_MTU\t((FM10K_VFMBMEM_LEN / 2) - 1)\n\n#define FM10K_MBX_INIT_TIMEOUT\t2000 /* number of retries on mailbox */\n#define FM10K_MBX_INIT_DELAY\t500 /* microseconds between retries */\n\nstruct fm10k_mbx_info {\n\t/* function pointers for mailbox operations */\n\tstruct fm10k_mbx_ops ops;\n\tconst struct fm10k_msg_data *msg_data;\n\n\t/* message FIFOs */\n\tstruct fm10k_mbx_fifo rx;\n\tstruct fm10k_mbx_fifo tx;\n\n\t/* delay for handling timeouts */\n\tu32 timeout;\n\tu32 usec_delay;\n\n\t/* mailbox state info */\n\tu32 mbx_reg, mbmem_reg, mbx_lock, mbx_hdr;\n\tu16 max_size, mbmem_len;\n\tu16 tail, tail_len, pulled;\n\tu16 head, head_len, pushed;\n\tu16 local, remote;\n\tenum fm10k_mbx_state state;\n\n\t/* result of last mailbox test */\n\ts32 test_result;\n\n\t/* statistics */\n\tu64 tx_busy;\n\tu64 tx_dropped;\n\tu64 tx_messages;\n\tu64 tx_dwords;\n\tu64 rx_messages;\n\tu64 rx_dwords;\n\tu64 rx_parse_err;\n\n\t/* Buffer to store messages */\n\tu32 buffer[FM10K_MBX_BUFFER_SIZE];\n};\n\ns32 fm10k_pfvf_mbx_init(struct fm10k_hw *, struct fm10k_mbx_info *,\n\t\t\tconst struct fm10k_msg_data *, u8);\ns32 fm10k_sm_mbx_init(struct fm10k_hw *, struct fm10k_mbx_info *,\n\t\t const struct fm10k_msg_data *);\n\n#endif /* _FM10K_MBX_H_ */\n" }, { "path": "drivers/net/fm10k/base/fm10k_osdep.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _FM10K_OSDEP_H_\n#define _FM10K_OSDEP_H_\n\n#include \n#include \n#include \n#include \n#include \n#include \"../fm10k_logs.h\"\n\n/* TODO: this does not look like it should be used... */\n#define ERROR_REPORT2(v1, v2, v3) do { } while (0)\n\n#define STATIC static\n#define DEBUGFUNC(F) DEBUGOUT(F \"\\n\");\n#define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)\n#define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)\n#define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)\n#define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)\n#define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)\n#define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)\n\n#define FALSE 0\n#define TRUE 1\n#ifndef false\n#define false FALSE\n#endif\n#ifndef true\n#define true TRUE\n#endif\n\ntypedef uint8_t u8;\ntypedef int8_t s8;\ntypedef uint16_t u16;\ntypedef int16_t s16;\ntypedef uint32_t u32;\ntypedef int32_t s32;\ntypedef int64_t s64;\ntypedef uint64_t u64;\ntypedef int bool;\n\n#ifndef __le16\n#define __le16 u16\n#define __le32 u32\n#define __le64 u64\n#endif\n#ifndef __be16\n#define __be16 u16\n#define __be32 u32\n#define __be64 u64\n#endif\n\n/* offsets are WORD offsets, not BYTE offsets */\n#define FM10K_WRITE_REG(hw, reg, val) \\\n\t((((volatile uint32_t *)(hw)->hw_addr)[(reg)]) = ((uint32_t)(val)))\n#define FM10K_READ_REG(hw, reg) \\\n\t(((volatile uint32_t *)(hw)->hw_addr)[(reg)])\n#define FM10K_WRITE_FLUSH(a) FM10K_READ_REG(a, FM10K_CTRL)\n\n#define FM10K_PCI_REG(reg) (*((volatile uint32_t *)(reg)))\n\n#define FM10K_PCI_REG_WRITE(reg, value) do { \\\n\tFM10K_PCI_REG((reg)) = (value); \\\n} while (0)\n\n/* not implemented */\n#define FM10K_READ_PCI_WORD(hw, reg) 0\n\n#define FM10K_WRITE_MBX(hw, reg, value) FM10K_WRITE_REG(hw, reg, value)\n#define FM10K_READ_MBX(hw, reg) FM10K_READ_REG(hw, reg)\n\n#define FM10K_LE16_TO_CPU rte_le_to_cpu_16\n#define FM10K_LE32_TO_CPU rte_le_to_cpu_32\n#define FM10K_CPU_TO_LE32 rte_cpu_to_le_32\n#define FM10K_CPU_TO_LE16 rte_cpu_to_le_16\n\n#define FM10K_RMB rte_rmb\n#define FM10K_WMB rte_wmb\n\n#define usec_delay rte_delay_us\n\n#define FM10K_REMOVED(hw_addr) (!(hw_addr))\n\n#ifndef FM10K_IS_ZERO_ETHER_ADDR\n/* make certain address is not 0 */\n#define FM10K_IS_ZERO_ETHER_ADDR(addr) \\\n(!((addr)[0] | (addr)[1] | (addr)[2] | (addr)[3] | (addr)[4] | (addr)[5]))\n#endif\n\n#ifndef FM10K_IS_MULTICAST_ETHER_ADDR\n#define FM10K_IS_MULTICAST_ETHER_ADDR(addr) ((addr)[0] & 0x1)\n#endif\n\n#ifndef FM10K_IS_VALID_ETHER_ADDR\n/* make certain address is not multicast or 0 */\n#define FM10K_IS_VALID_ETHER_ADDR(addr) \\\n(!FM10K_IS_MULTICAST_ETHER_ADDR(addr) && !FM10K_IS_ZERO_ETHER_ADDR(addr))\n#endif\n\n#ifndef do_div\n#define do_div(n, base) ({\\\n\t(n) = (n) / (base);\\\n})\n#endif /* do_div */\n\n/* DPDK can't access IOMEM directly */\n#ifndef FM10K_WRITE_SW_REG\n#define FM10K_WRITE_SW_REG(v1, v2, v3) do { } while (0)\n#endif\n\n#ifndef fm10k_read_reg\n#define fm10k_read_reg FM10K_READ_REG\n#endif\n\n#endif /* _FM10K_OSDEP_H_ */\n" }, { "path": "drivers/net/fm10k/base/fm10k_pf.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"fm10k_pf.h\"\n#include \"fm10k_vf.h\"\n\n/**\n * fm10k_reset_hw_pf - PF hardware reset\n * @hw: pointer to hardware structure\n *\n * This function should return the hardware to a state similar to the\n * one it is in after being powered on.\n **/\nSTATIC s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)\n{\n\ts32 err;\n\tu32 reg;\n\tu16 i;\n\n\tDEBUGFUNC(\"fm10k_reset_hw_pf\");\n\n\t/* Disable interrupts */\n\tFM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL));\n\n\t/* Lock ITR2 reg 0 into itself and disable interrupt moderation */\n\tFM10K_WRITE_REG(hw, FM10K_ITR2(0), 0);\n\tFM10K_WRITE_REG(hw, FM10K_INT_CTRL, 0);\n\n\t/* We assume here Tx and Rx queue 0 are owned by the PF */\n\n\t/* Shut off VF access to their queues forcing them to queue 0 */\n\tfor (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) {\n\t\tFM10K_WRITE_REG(hw, FM10K_TQMAP(i), 0);\n\t\tFM10K_WRITE_REG(hw, FM10K_RQMAP(i), 0);\n\t}\n\n\t/* shut down all rings */\n\terr = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES);\n\tif (err)\n\t\treturn err;\n\n\t/* Verify that DMA is no longer active */\n\treg = FM10K_READ_REG(hw, FM10K_DMA_CTRL);\n\tif (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE))\n\t\treturn FM10K_ERR_DMA_PENDING;\n\n\t/* verify the switch is ready for reset */\n\treg = FM10K_READ_REG(hw, FM10K_DMA_CTRL2);\n\tif (!(reg & FM10K_DMA_CTRL2_SWITCH_READY))\n\t\tgoto out;\n\n\t/* Inititate data path reset */\n\treg |= FM10K_DMA_CTRL_DATAPATH_RESET;\n\tFM10K_WRITE_REG(hw, FM10K_DMA_CTRL, reg);\n\n\t/* Flush write and allow 100us for reset to complete */\n\tFM10K_WRITE_FLUSH(hw);\n\tusec_delay(FM10K_RESET_TIMEOUT);\n\n\t/* Verify we made it out of reset */\n\treg = FM10K_READ_REG(hw, FM10K_IP);\n\tif (!(reg & FM10K_IP_NOTINRESET))\n\t\terr = FM10K_ERR_RESET_FAILED;\n\nout:\n\treturn err;\n}\n\n/**\n * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support\n * @hw: pointer to hardware structure\n *\n * Looks at the ARI hierarchy bit to determine whether ARI is supported or not.\n **/\nSTATIC bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw)\n{\n\tu16 sriov_ctrl = FM10K_READ_PCI_WORD(hw, FM10K_PCIE_SRIOV_CTRL);\n\n\tDEBUGFUNC(\"fm10k_is_ari_hierarchy_pf\");\n\n\treturn !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI);\n}\n\n/**\n * fm10k_init_hw_pf - PF hardware initialization\n * @hw: pointer to hardware structure\n *\n **/\nSTATIC s32 fm10k_init_hw_pf(struct fm10k_hw *hw)\n{\n\tu32 dma_ctrl, txqctl;\n\tu16 i;\n\n\tDEBUGFUNC(\"fm10k_init_hw_pf\");\n\n\t/* Establish default VSI as valid */\n\tFM10K_WRITE_REG(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0);\n\tFM10K_WRITE_REG(hw, FM10K_DGLORTMAP(fm10k_dglort_default),\n\t\t\tFM10K_DGLORTMAP_ANY);\n\n\t/* Invalidate all other GLORT entries */\n\tfor (i = 1; i < FM10K_DGLORT_COUNT; i++)\n\t\tFM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE);\n\n\t/* reset ITR2(0) to point to itself */\n\tFM10K_WRITE_REG(hw, FM10K_ITR2(0), 0);\n\n\t/* reset VF ITR2(0) to point to 0 avoid PF registers */\n\tFM10K_WRITE_REG(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0);\n\n\t/* loop through all PF ITR2 registers pointing them to the previous */\n\tfor (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++)\n\t\tFM10K_WRITE_REG(hw, FM10K_ITR2(i), i - 1);\n\n\t/* Enable interrupt moderator if not already enabled */\n\tFM10K_WRITE_REG(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);\n\n\t/* compute the default txqctl configuration */\n\ttxqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW |\n\t\t (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT);\n\n\tfor (i = 0; i < FM10K_MAX_QUEUES; i++) {\n\t\t/* configure rings for 256 Queue / 32 Descriptor cache mode */\n\t\tFM10K_WRITE_REG(hw, FM10K_TQDLOC(i),\n\t\t\t\t(i * FM10K_TQDLOC_BASE_32_DESC) |\n\t\t\t\tFM10K_TQDLOC_SIZE_32_DESC);\n\t\tFM10K_WRITE_REG(hw, FM10K_TXQCTL(i), txqctl);\n\n\t\t/* configure rings to provide TPH processing hints */\n\t\tFM10K_WRITE_REG(hw, FM10K_TPH_TXCTRL(i),\n\t\t\t\tFM10K_TPH_TXCTRL_DESC_TPHEN |\n\t\t\t\tFM10K_TPH_TXCTRL_DESC_RROEN |\n\t\t\t\tFM10K_TPH_TXCTRL_DESC_WROEN |\n\t\t\t\tFM10K_TPH_TXCTRL_DATA_RROEN);\n\t\tFM10K_WRITE_REG(hw, FM10K_TPH_RXCTRL(i),\n\t\t\t\tFM10K_TPH_RXCTRL_DESC_TPHEN |\n\t\t\t\tFM10K_TPH_RXCTRL_DESC_RROEN |\n\t\t\t\tFM10K_TPH_RXCTRL_DATA_WROEN |\n\t\t\t\tFM10K_TPH_RXCTRL_HDR_WROEN);\n\t}\n\n\t/* set max hold interval to align with 1.024 usec in all modes */\n\tswitch (hw->bus.speed) {\n\tcase fm10k_bus_speed_2500:\n\t\tdma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;\n\t\tbreak;\n\tcase fm10k_bus_speed_5000:\n\t\tdma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;\n\t\tbreak;\n\tcase fm10k_bus_speed_8000:\n\t\tdma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;\n\t\tbreak;\n\tdefault:\n\t\tdma_ctrl = 0;\n\t\tbreak;\n\t}\n\n\t/* Configure TSO flags */\n\tFM10K_WRITE_REG(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW);\n\tFM10K_WRITE_REG(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI);\n\n\t/* Enable DMA engine\n\t * Set Rx Descriptor size to 32\n\t * Set Minimum MSS to 64\n\t * Set Maximum number of Rx queues to 256 / 32 Descriptor\n\t */\n\tdma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE |\n\t\t FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 |\n\t\t FM10K_DMA_CTRL_32_DESC;\n\n\tFM10K_WRITE_REG(hw, FM10K_DMA_CTRL, dma_ctrl);\n\n\t/* record maximum queue count, we limit ourselves to 128 */\n\thw->mac.max_queues = FM10K_MAX_QUEUES_PF;\n\n\t/* We support either 64 VFs or 7 VFs depending on if we have ARI */\n\thw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_is_slot_appropriate_pf - Indicate appropriate slot for this SKU\n * @hw: pointer to hardware structure\n *\n * Looks at the PCIe bus info to confirm whether or not this slot can support\n * the necessary bandwidth for this device.\n **/\nSTATIC bool fm10k_is_slot_appropriate_pf(struct fm10k_hw *hw)\n{\n\tDEBUGFUNC(\"fm10k_is_slot_appropriate_pf\");\n\n\treturn (hw->bus.speed == hw->bus_caps.speed) &&\n\t (hw->bus.width == hw->bus_caps.width);\n}\n\n/**\n * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table\n * @hw: pointer to hardware structure\n * @vid: VLAN ID to add to table\n * @vsi: Index indicating VF ID or PF ID in table\n * @set: Indicates if this is a set or clear operation\n *\n * This function adds or removes the corresponding VLAN ID from the VLAN\n * filter table for the corresponding function. In addition to the\n * standard set/clear that supports one bit a multi-bit write is\n * supported to set 64 bits at a time.\n **/\nSTATIC s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)\n{\n\tu32 vlan_table, reg, mask, bit, len;\n\n\t/* verify the VSI index is valid */\n\tif (vsi > FM10K_VLAN_TABLE_VSI_MAX)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* VLAN multi-bit write:\n\t * The multi-bit write has several parts to it.\n\t * 3\t\t\t 2\t\t 1\t\t\t 0\n\t * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0\n\t * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n\t * | RSVD0 | Length |C|RSVD0| VLAN ID |\n\t * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n\t *\n\t * VLAN ID: Vlan Starting value\n\t * RSVD0: Reserved section, must be 0\n\t * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message)\n\t * Length: Number of times to repeat the bit being set\n\t */\n\tlen = vid >> 16;\n\tvid = (vid << 17) >> 17;\n\n\t/* verify the reserved 0 fields are 0 */\n\tif (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* Loop through the table updating all required VLANs */\n\tfor (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32;\n\t len < FM10K_VLAN_TABLE_VID_MAX;\n\t len -= 32 - bit, reg++, bit = 0) {\n\t\t/* record the initial state of the register */\n\t\tvlan_table = FM10K_READ_REG(hw, reg);\n\n\t\t/* truncate mask if we are at the start or end of the run */\n\t\tmask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit;\n\n\t\t/* make necessary modifications to the register */\n\t\tmask &= set ? ~vlan_table : vlan_table;\n\t\tif (mask)\n\t\t\tFM10K_WRITE_REG(hw, reg, vlan_table ^ mask);\n\t}\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_read_mac_addr_pf - Read device MAC address\n * @hw: pointer to the HW structure\n *\n * Reads the device MAC address from the SM_AREA and stores the value.\n **/\nSTATIC s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw)\n{\n\tu8 perm_addr[ETH_ALEN];\n\tu32 serial_num;\n\tint i;\n\n\tDEBUGFUNC(\"fm10k_read_mac_addr_pf\");\n\n\tserial_num = FM10K_READ_REG(hw, FM10K_SM_AREA(1));\n\n\t/* last byte should be all 1's */\n\tif ((~serial_num) << 24)\n\t\treturn FM10K_ERR_INVALID_MAC_ADDR;\n\n\tperm_addr[0] = (u8)(serial_num >> 24);\n\tperm_addr[1] = (u8)(serial_num >> 16);\n\tperm_addr[2] = (u8)(serial_num >> 8);\n\n\tserial_num = FM10K_READ_REG(hw, FM10K_SM_AREA(0));\n\n\t/* first byte should be all 1's */\n\tif ((~serial_num) >> 24)\n\t\treturn FM10K_ERR_INVALID_MAC_ADDR;\n\n\tperm_addr[3] = (u8)(serial_num >> 16);\n\tperm_addr[4] = (u8)(serial_num >> 8);\n\tperm_addr[5] = (u8)(serial_num);\n\n\tfor (i = 0; i < ETH_ALEN; i++) {\n\t\thw->mac.perm_addr[i] = perm_addr[i];\n\t\thw->mac.addr[i] = perm_addr[i];\n\t}\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_glort_valid_pf - Validate that the provided glort is valid\n * @hw: pointer to the HW structure\n * @glort: base glort to be validated\n *\n * This function will return an error if the provided glort is invalid\n **/\nbool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort)\n{\n\tglort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT;\n\n\treturn glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE);\n}\n\n/**\n * fm10k_update_xc_addr_pf - Update device addresses\n * @hw: pointer to the HW structure\n * @glort: base resource tag for this request\n * @mac: MAC address to add/remove from table\n * @vid: VLAN ID to add/remove from table\n * @add: Indicates if this is an add or remove operation\n * @flags: flags field to indicate add and secure\n *\n * This function generates a message to the Switch API requesting\n * that the given logical port add/remove the given L2 MAC/VLAN address.\n **/\nSTATIC s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort,\n\t\t\t\t const u8 *mac, u16 vid, bool add, u8 flags)\n{\n\tstruct fm10k_mbx_info *mbx = &hw->mbx;\n\tstruct fm10k_mac_update mac_update;\n\tu32 msg[5];\n\n\tDEBUGFUNC(\"fm10k_update_xc_addr_pf\");\n\n\t/* if glort or VLAN are not valid return error */\n\tif (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* record fields */\n\tmac_update.mac_lower = FM10K_CPU_TO_LE32(((u32)mac[2] << 24) |\n\t\t\t\t\t\t ((u32)mac[3] << 16) |\n\t\t\t\t\t\t ((u32)mac[4] << 8) |\n\t\t\t\t\t\t ((u32)mac[5]));\n\tmac_update.mac_upper = FM10K_CPU_TO_LE16(((u32)mac[0] << 8) |\n\t\t\t\t\t\t ((u32)mac[1]));\n\tmac_update.vlan = FM10K_CPU_TO_LE16(vid);\n\tmac_update.glort = FM10K_CPU_TO_LE16(glort);\n\tmac_update.action = add ? 0 : 1;\n\tmac_update.flags = flags;\n\n\t/* populate mac_update fields */\n\tfm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE);\n\tfm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE,\n\t\t\t\t &mac_update, sizeof(mac_update));\n\n\t/* load onto outgoing mailbox */\n\treturn mbx->ops.enqueue_tx(hw, mbx, msg);\n}\n\n/**\n * fm10k_update_uc_addr_pf - Update device unicast addresses\n * @hw: pointer to the HW structure\n * @glort: base resource tag for this request\n * @mac: MAC address to add/remove from table\n * @vid: VLAN ID to add/remove from table\n * @add: Indicates if this is an add or remove operation\n * @flags: flags field to indicate add and secure\n *\n * This function is used to add or remove unicast addresses for\n * the PF.\n **/\nSTATIC s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort,\n\t\t\t\t const u8 *mac, u16 vid, bool add, u8 flags)\n{\n\tDEBUGFUNC(\"fm10k_update_uc_addr_pf\");\n\n\t/* verify MAC address is valid */\n\tif (!FM10K_IS_VALID_ETHER_ADDR(mac))\n\t\treturn FM10K_ERR_PARAM;\n\n\treturn fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags);\n}\n\n/**\n * fm10k_update_mc_addr_pf - Update device multicast addresses\n * @hw: pointer to the HW structure\n * @glort: base resource tag for this request\n * @mac: MAC address to add/remove from table\n * @vid: VLAN ID to add/remove from table\n * @add: Indicates if this is an add or remove operation\n *\n * This function is used to add or remove multicast MAC addresses for\n * the PF.\n **/\nSTATIC s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort,\n\t\t\t\t const u8 *mac, u16 vid, bool add)\n{\n\tDEBUGFUNC(\"fm10k_update_mc_addr_pf\");\n\n\t/* verify multicast address is valid */\n\tif (!FM10K_IS_MULTICAST_ETHER_ADDR(mac))\n\t\treturn FM10K_ERR_PARAM;\n\n\treturn fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0);\n}\n\n/**\n * fm10k_update_xcast_mode_pf - Request update of multicast mode\n * @hw: pointer to hardware structure\n * @glort: base resource tag for this request\n * @mode: integer value indicating mode being requested\n *\n * This function will attempt to request a higher mode for the port\n * so that it can enable either multicast, multicast promiscuous, or\n * promiscuous mode of operation.\n **/\nSTATIC s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode)\n{\n\tstruct fm10k_mbx_info *mbx = &hw->mbx;\n\tu32 msg[3], xcast_mode;\n\n\tDEBUGFUNC(\"fm10k_update_xcast_mode_pf\");\n\n\tif (mode > FM10K_XCAST_MODE_NONE)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* if glort is not valid return error */\n\tif (!fm10k_glort_valid_pf(hw, glort))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* write xcast mode as a single u32 value,\n\t * lower 16 bits: glort\n\t * upper 16 bits: mode\n\t */\n\txcast_mode = ((u32)mode << 16) | glort;\n\n\t/* generate message requesting to change xcast mode */\n\tfm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES);\n\tfm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode);\n\n\t/* load onto outgoing mailbox */\n\treturn mbx->ops.enqueue_tx(hw, mbx, msg);\n}\n\n/**\n * fm10k_update_int_moderator_pf - Update interrupt moderator linked list\n * @hw: pointer to hardware structure\n *\n * This function walks through the MSI-X vector table to determine the\n * number of active interrupts and based on that information updates the\n * interrupt moderator linked list.\n **/\nSTATIC void fm10k_update_int_moderator_pf(struct fm10k_hw *hw)\n{\n\tu32 i;\n\n\t/* Disable interrupt moderator */\n\tFM10K_WRITE_REG(hw, FM10K_INT_CTRL, 0);\n\n\t/* loop through PF from last to first looking enabled vectors */\n\tfor (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) {\n\t\tif (!FM10K_READ_REG(hw, FM10K_MSIX_VECTOR_MASK(i)))\n\t\t\tbreak;\n\t}\n\n\t/* always reset VFITR2[0] to point to last enabled PF vector */\n\tFM10K_WRITE_REG(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i);\n\n\t/* reset ITR2[0] to point to last enabled PF vector */\n\tif (!hw->iov.num_vfs)\n\t\tFM10K_WRITE_REG(hw, FM10K_ITR2(0), i);\n\n\t/* Enable interrupt moderator */\n\tFM10K_WRITE_REG(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);\n}\n\n/**\n * fm10k_update_lport_state_pf - Notify the switch of a change in port state\n * @hw: pointer to the HW structure\n * @glort: base resource tag for this request\n * @count: number of logical ports being updated\n * @enable: boolean value indicating enable or disable\n *\n * This function is used to add/remove a logical port from the switch.\n **/\nSTATIC s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort,\n\t\t\t\t u16 count, bool enable)\n{\n\tstruct fm10k_mbx_info *mbx = &hw->mbx;\n\tu32 msg[3], lport_msg;\n\n\tDEBUGFUNC(\"fm10k_lport_state_pf\");\n\n\t/* do nothing if we are being asked to create or destroy 0 ports */\n\tif (!count)\n\t\treturn FM10K_SUCCESS;\n\n\t/* if glort is not valid return error */\n\tif (!fm10k_glort_valid_pf(hw, glort))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* construct the lport message from the 2 pieces of data we have */\n\tlport_msg = ((u32)count << 16) | glort;\n\n\t/* generate lport create/delete message */\n\tfm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE :\n\t\t\t\t\t FM10K_PF_MSG_ID_LPORT_DELETE);\n\tfm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg);\n\n\t/* load onto outgoing mailbox */\n\treturn mbx->ops.enqueue_tx(hw, mbx, msg);\n}\n\n/**\n * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues\n * @hw: pointer to hardware structure\n * @dglort: pointer to dglort configuration structure\n *\n * Reads the configuration structure contained in dglort_cfg and uses\n * that information to then populate a DGLORTMAP/DEC entry and the queues\n * to which it has been assigned.\n **/\nSTATIC s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw,\n\t\t\t\t\t struct fm10k_dglort_cfg *dglort)\n{\n\tu16 glort, queue_count, vsi_count, pc_count;\n\tu16 vsi, queue, pc, q_idx;\n\tu32 txqctl, dglortdec, dglortmap;\n\n\t/* verify the dglort pointer */\n\tif (!dglort)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* verify the dglort values */\n\tif ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) ||\n\t (dglort->vsi_l > 6) || (dglort->vsi_b > 64) ||\n\t (dglort->queue_l > 8) || (dglort->queue_b >= 256))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* determine count of VSIs and queues */\n\tqueue_count = 1 << (dglort->rss_l + dglort->pc_l);\n\tvsi_count = 1 << (dglort->vsi_l + dglort->queue_l);\n\tglort = dglort->glort;\n\tq_idx = dglort->queue_b;\n\n\t/* configure SGLORT for queues */\n\tfor (vsi = 0; vsi < vsi_count; vsi++, glort++) {\n\t\tfor (queue = 0; queue < queue_count; queue++, q_idx++) {\n\t\t\tif (q_idx >= FM10K_MAX_QUEUES)\n\t\t\t\tbreak;\n\n\t\t\tFM10K_WRITE_REG(hw, FM10K_TX_SGLORT(q_idx), glort);\n\t\t\tFM10K_WRITE_REG(hw, FM10K_RX_SGLORT(q_idx), glort);\n\t\t}\n\t}\n\n\t/* determine count of PCs and queues */\n\tqueue_count = 1 << (dglort->queue_l + dglort->rss_l + dglort->vsi_l);\n\tpc_count = 1 << dglort->pc_l;\n\n\t/* configure PC for Tx queues */\n\tfor (pc = 0; pc < pc_count; pc++) {\n\t\tq_idx = pc + dglort->queue_b;\n\t\tfor (queue = 0; queue < queue_count; queue++) {\n\t\t\tif (q_idx >= FM10K_MAX_QUEUES)\n\t\t\t\tbreak;\n\n\t\t\ttxqctl = FM10K_READ_REG(hw, FM10K_TXQCTL(q_idx));\n\t\t\ttxqctl &= ~FM10K_TXQCTL_PC_MASK;\n\t\t\ttxqctl |= pc << FM10K_TXQCTL_PC_SHIFT;\n\t\t\tFM10K_WRITE_REG(hw, FM10K_TXQCTL(q_idx), txqctl);\n\n\t\t\tq_idx += pc_count;\n\t\t}\n\t}\n\n\t/* configure DGLORTDEC */\n\tdglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) |\n\t\t ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) |\n\t\t ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) |\n\t\t ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) |\n\t\t ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) |\n\t\t ((u32)(dglort->queue_l));\n\tif (dglort->inner_rss)\n\t\tdglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE;\n\n\t/* configure DGLORTMAP */\n\tdglortmap = (dglort->idx == fm10k_dglort_default) ?\n\t\t\tFM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO;\n\tdglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l;\n\tdglortmap |= dglort->glort;\n\n\t/* write values to hardware */\n\tFM10K_WRITE_REG(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec);\n\tFM10K_WRITE_REG(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap);\n\n\treturn FM10K_SUCCESS;\n}\n\nu16 fm10k_queues_per_pool(struct fm10k_hw *hw)\n{\n\tu16 num_pools = hw->iov.num_pools;\n\n\treturn (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ?\n\t 8 : FM10K_MAX_QUEUES_POOL;\n}\n\nu16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx)\n{\n\tu16 num_vfs = hw->iov.num_vfs;\n\tu16 vf_q_idx = FM10K_MAX_QUEUES;\n\n\tvf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx);\n\n\treturn vf_q_idx;\n}\n\nSTATIC u16 fm10k_vectors_per_pool(struct fm10k_hw *hw)\n{\n\tu16 num_pools = hw->iov.num_pools;\n\n\treturn (num_pools > 32) ? 8 : (num_pools > 16) ? 16 :\n\t FM10K_MAX_VECTORS_POOL;\n}\n\nSTATIC u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx)\n{\n\tu16 vf_v_idx = FM10K_MAX_VECTORS_PF;\n\n\tvf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx;\n\n\treturn vf_v_idx;\n}\n\n/**\n * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization\n * @hw: pointer to the HW structure\n * @num_vfs: number of VFs to be allocated\n * @num_pools: number of virtualization pools to be allocated\n *\n * Allocates queues and traffic classes to virtualization entities to prepare\n * the PF for SR-IOV and VMDq\n **/\nSTATIC s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs,\n\t\t\t\t\t u16 num_pools)\n{\n\tu16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx;\n\tu32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT;\n\tint i, j;\n\n\t/* hardware only supports up to 64 pools */\n\tif (num_pools > 64)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* the number of VFs cannot exceed the number of pools */\n\tif ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* record number of virtualization entities */\n\thw->iov.num_vfs = num_vfs;\n\thw->iov.num_pools = num_pools;\n\n\t/* determine qmap offsets and counts */\n\tqmap_stride = (num_vfs > 8) ? 32 : 256;\n\tqpp = fm10k_queues_per_pool(hw);\n\tvpp = fm10k_vectors_per_pool(hw);\n\n\t/* calculate starting index for queues */\n\tvf_q_idx = fm10k_vf_queue_index(hw, 0);\n\tqmap_idx = 0;\n\n\t/* establish TCs with -1 credits and no quanta to prevent transmit */\n\tfor (i = 0; i < num_vfs; i++) {\n\t\tFM10K_WRITE_REG(hw, FM10K_TC_MAXCREDIT(i), 0);\n\t\tFM10K_WRITE_REG(hw, FM10K_TC_RATE(i), 0);\n\t\tFM10K_WRITE_REG(hw, FM10K_TC_CREDIT(i),\n\t\t\t\tFM10K_TC_CREDIT_CREDIT_MASK);\n\t}\n\n\t/* zero out all mbmem registers */\n\tfor (i = FM10K_VFMBMEM_LEN * num_vfs; i--;)\n\t\tFM10K_WRITE_REG(hw, FM10K_MBMEM(i), 0);\n\n\t/* clear event notification of VF FLR */\n\tFM10K_WRITE_REG(hw, FM10K_PFVFLREC(0), ~0);\n\tFM10K_WRITE_REG(hw, FM10K_PFVFLREC(1), ~0);\n\n\t/* loop through unallocated rings assigning them back to PF */\n\tfor (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) {\n\t\tFM10K_WRITE_REG(hw, FM10K_TXDCTL(i), 0);\n\t\tFM10K_WRITE_REG(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | vid);\n\t\tFM10K_WRITE_REG(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);\n\t}\n\n\t/* PF should have already updated VFITR2[0] */\n\n\t/* update all ITR registers to flow to VFITR2[0] */\n\tfor (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) {\n\t\tif (!(i & (vpp - 1)))\n\t\t\tFM10K_WRITE_REG(hw, FM10K_ITR2(i), i - vpp);\n\t\telse\n\t\t\tFM10K_WRITE_REG(hw, FM10K_ITR2(i), i - 1);\n\t}\n\n\t/* update PF ITR2[0] to reference the last vector */\n\tFM10K_WRITE_REG(hw, FM10K_ITR2(0),\n\t\t\tfm10k_vf_vector_index(hw, num_vfs - 1));\n\n\t/* loop through rings populating rings and TCs */\n\tfor (i = 0; i < num_vfs; i++) {\n\t\t/* record index for VF queue 0 for use in end of loop */\n\t\tvf_q_idx0 = vf_q_idx;\n\n\t\tfor (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) {\n\t\t\t/* assign VF and locked TC to queues */\n\t\t\tFM10K_WRITE_REG(hw, FM10K_TXDCTL(vf_q_idx), 0);\n\t\t\tFM10K_WRITE_REG(hw, FM10K_TXQCTL(vf_q_idx),\n\t\t\t\t\t(i << FM10K_TXQCTL_TC_SHIFT) | i |\n\t\t\t\t\tFM10K_TXQCTL_VF | vid);\n\t\t\tFM10K_WRITE_REG(hw, FM10K_RXDCTL(vf_q_idx),\n\t\t\t\t\tFM10K_RXDCTL_WRITE_BACK_MIN_DELAY |\n\t\t\t\t\tFM10K_RXDCTL_DROP_ON_EMPTY);\n\t\t\tFM10K_WRITE_REG(hw, FM10K_RXQCTL(vf_q_idx),\n\t\t\t\t\tFM10K_RXQCTL_VF |\n\t\t\t\t\t(i << FM10K_RXQCTL_VF_SHIFT));\n\n\t\t\t/* map queue pair to VF */\n\t\t\tFM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);\n\t\t\tFM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx), vf_q_idx);\n\t\t}\n\n\t\t/* repeat the first ring for all of the remaining VF rings */\n\t\tfor (; j < qmap_stride; j++, qmap_idx++) {\n\t\t\tFM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0);\n\t\t\tFM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0);\n\t\t}\n\t}\n\n\t/* loop through remaining indexes assigning all to queue 0 */\n\twhile (qmap_idx < FM10K_TQMAP_TABLE_SIZE) {\n\t\tFM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), 0);\n\t\tFM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx), 0);\n\t\tqmap_idx++;\n\t}\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_iov_configure_tc_pf - Configure the shaping group for VF\n * @hw: pointer to the HW structure\n * @vf_idx: index of VF receiving GLORT\n * @rate: Rate indicated in Mb/s\n *\n * Configured the TC for a given VF to allow only up to a given number\n * of Mb/s of outgoing Tx throughput.\n **/\nSTATIC s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate)\n{\n\t/* configure defaults */\n\tu32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3;\n\tu32 tc_rate = FM10K_TC_RATE_QUANTA_MASK;\n\n\t/* verify vf is in range */\n\tif (vf_idx >= hw->iov.num_vfs)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* set interval to align with 4.096 usec in all modes */\n\tswitch (hw->bus.speed) {\n\tcase fm10k_bus_speed_2500:\n\t\tinterval = FM10K_TC_RATE_INTERVAL_4US_GEN1;\n\t\tbreak;\n\tcase fm10k_bus_speed_5000:\n\t\tinterval = FM10K_TC_RATE_INTERVAL_4US_GEN2;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (rate) {\n\t\tif (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN)\n\t\t\treturn FM10K_ERR_PARAM;\n\n\t\t/* The quanta is measured in Bytes per 4.096 or 8.192 usec\n\t\t * The rate is provided in Mbits per second\n\t\t * To tralslate from rate to quanta we need to multiply the\n\t\t * rate by 8.192 usec and divide by 8 bits/byte. To avoid\n\t\t * dealing with floating point we can round the values up\n\t\t * to the nearest whole number ratio which gives us 128 / 125.\n\t\t */\n\t\ttc_rate = (rate * 128) / 125;\n\n\t\t/* try to keep the rate limiting accurate by increasing\n\t\t * the number of credits and interval for rates less than 4Gb/s\n\t\t */\n\t\tif (rate < 4000)\n\t\t\tinterval <<= 1;\n\t\telse\n\t\t\ttc_rate >>= 1;\n\t}\n\n\t/* update rate limiter with new values */\n\tFM10K_WRITE_REG(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval);\n\tFM10K_WRITE_REG(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);\n\tFM10K_WRITE_REG(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list\n * @hw: pointer to the HW structure\n * @vf_idx: index of VF receiving GLORT\n *\n * Update the interrupt moderator linked list to include any MSI-X\n * interrupts which the VF has enabled in the MSI-X vector table.\n **/\nSTATIC s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx)\n{\n\tu16 vf_v_idx, vf_v_limit, i;\n\n\t/* verify vf is in range */\n\tif (vf_idx >= hw->iov.num_vfs)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* determine vector offset and count */\n\tvf_v_idx = fm10k_vf_vector_index(hw, vf_idx);\n\tvf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);\n\n\t/* search for first vector that is not masked */\n\tfor (i = vf_v_limit - 1; i > vf_v_idx; i--) {\n\t\tif (!FM10K_READ_REG(hw, FM10K_MSIX_VECTOR_MASK(i)))\n\t\t\tbreak;\n\t}\n\n\t/* reset linked list so it now includes our active vectors */\n\tif (vf_idx == (hw->iov.num_vfs - 1))\n\t\tFM10K_WRITE_REG(hw, FM10K_ITR2(0), i);\n\telse\n\t\tFM10K_WRITE_REG(hw, FM10K_ITR2(vf_v_limit), i);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF\n * @hw: pointer to the HW structure\n * @vf_info: pointer to VF information structure\n *\n * Assign a MAC address and default VLAN to a VF and notify it of the update\n **/\nSTATIC s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,\n\t\t\t\t\t\tstruct fm10k_vf_info *vf_info)\n{\n\tu16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i;\n\tu32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0;\n\ts32 err = FM10K_SUCCESS;\n\tu16 vf_idx, vf_vid;\n\n\t/* verify vf is in range */\n\tif (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* determine qmap offsets and counts */\n\tqmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;\n\tqueues_per_pool = fm10k_queues_per_pool(hw);\n\n\t/* calculate starting index for queues */\n\tvf_idx = vf_info->vf_idx;\n\tvf_q_idx = fm10k_vf_queue_index(hw, vf_idx);\n\tqmap_idx = qmap_stride * vf_idx;\n\n\t/* MAP Tx queue back to 0 temporarily, and disable it */\n\tFM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), 0);\n\tFM10K_WRITE_REG(hw, FM10K_TXDCTL(vf_q_idx), 0);\n\n\t/* determine correct default VLAN ID */\n\tif (vf_info->pf_vid)\n\t\tvf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR;\n\telse\n\t\tvf_vid = vf_info->sw_vid;\n\n\t/* generate MAC_ADDR request */\n\tfm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);\n\tfm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC,\n\t\t\t\t vf_info->mac, vf_vid);\n\n\t/* load onto outgoing mailbox, ignore any errors on enqueue */\n\tif (vf_info->mbx.ops.enqueue_tx)\n\t\tvf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);\n\n\t/* verify ring has disabled before modifying base address registers */\n\ttxdctl = FM10K_READ_REG(hw, FM10K_TXDCTL(vf_q_idx));\n\tfor (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) {\n\t\t/* limit ourselves to a 1ms timeout */\n\t\tif (timeout == 10) {\n\t\t\terr = FM10K_ERR_DMA_PENDING;\n\t\t\tgoto err_out;\n\t\t}\n\n\t\tusec_delay(100);\n\t\ttxdctl = FM10K_READ_REG(hw, FM10K_TXDCTL(vf_q_idx));\n\t}\n\n\t/* Update base address registers to contain MAC address */\n\tif (FM10K_IS_VALID_ETHER_ADDR(vf_info->mac)) {\n\t\ttdbal = (((u32)vf_info->mac[3]) << 24) |\n\t\t\t(((u32)vf_info->mac[4]) << 16) |\n\t\t\t(((u32)vf_info->mac[5]) << 8);\n\n\t\ttdbah = (((u32)0xFF)\t << 24) |\n\t\t\t(((u32)vf_info->mac[0]) << 16) |\n\t\t\t(((u32)vf_info->mac[1]) << 8) |\n\t\t\t((u32)vf_info->mac[2]);\n\t}\n\n\t/* Record the base address into queue 0 */\n\tFM10K_WRITE_REG(hw, FM10K_TDBAL(vf_q_idx), tdbal);\n\tFM10K_WRITE_REG(hw, FM10K_TDBAH(vf_q_idx), tdbah);\n\nerr_out:\n\t/* configure Queue control register */\n\ttxqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) &\n\t\t FM10K_TXQCTL_VID_MASK;\n\ttxqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) |\n\t\t FM10K_TXQCTL_VF | vf_idx;\n\n\t/* assign VID */\n\tfor (i = 0; i < queues_per_pool; i++)\n\t\tFM10K_WRITE_REG(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl);\n\n\t/* restore the queue back to VF ownership */\n\tFM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);\n\treturn err;\n}\n\n/**\n * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF\n * @hw: pointer to the HW structure\n * @vf_info: pointer to VF information structure\n *\n * Reassign the interrupts and queues to a VF following an FLR\n **/\nSTATIC s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw,\n\t\t\t\t\tstruct fm10k_vf_info *vf_info)\n{\n\tu16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx;\n\tu32 tdbal = 0, tdbah = 0, txqctl, rxqctl;\n\tu16 vf_v_idx, vf_v_limit, vf_vid;\n\tu8 vf_idx = vf_info->vf_idx;\n\tint i;\n\n\t/* verify vf is in range */\n\tif (vf_idx >= hw->iov.num_vfs)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* clear event notification of VF FLR */\n\tFM10K_WRITE_REG(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32));\n\n\t/* force timeout and then disconnect the mailbox */\n\tvf_info->mbx.timeout = 0;\n\tif (vf_info->mbx.ops.disconnect)\n\t\tvf_info->mbx.ops.disconnect(hw, &vf_info->mbx);\n\n\t/* determine vector offset and count */\n\tvf_v_idx = fm10k_vf_vector_index(hw, vf_idx);\n\tvf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);\n\n\t/* determine qmap offsets and counts */\n\tqmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;\n\tqueues_per_pool = fm10k_queues_per_pool(hw);\n\tqmap_idx = qmap_stride * vf_idx;\n\n\t/* make all the queues inaccessible to the VF */\n\tfor (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) {\n\t\tFM10K_WRITE_REG(hw, FM10K_TQMAP(i), 0);\n\t\tFM10K_WRITE_REG(hw, FM10K_RQMAP(i), 0);\n\t}\n\n\t/* calculate starting index for queues */\n\tvf_q_idx = fm10k_vf_queue_index(hw, vf_idx);\n\n\t/* determine correct default VLAN ID */\n\tif (vf_info->pf_vid)\n\t\tvf_vid = vf_info->pf_vid;\n\telse\n\t\tvf_vid = vf_info->sw_vid;\n\n\t/* configure Queue control register */\n\ttxqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) |\n\t\t (vf_idx << FM10K_TXQCTL_TC_SHIFT) |\n\t\t FM10K_TXQCTL_VF | vf_idx;\n\trxqctl = FM10K_RXQCTL_VF | (vf_idx << FM10K_RXQCTL_VF_SHIFT);\n\n\t/* stop further DMA and reset queue ownership back to VF */\n\tfor (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) {\n\t\tFM10K_WRITE_REG(hw, FM10K_TXDCTL(i), 0);\n\t\tFM10K_WRITE_REG(hw, FM10K_TXQCTL(i), txqctl);\n\t\tFM10K_WRITE_REG(hw, FM10K_RXDCTL(i),\n\t\t\t\tFM10K_RXDCTL_WRITE_BACK_MIN_DELAY |\n\t\t\t\tFM10K_RXDCTL_DROP_ON_EMPTY);\n\t\tFM10K_WRITE_REG(hw, FM10K_RXQCTL(i), rxqctl);\n\t}\n\n\t/* reset TC with -1 credits and no quanta to prevent transmit */\n\tFM10K_WRITE_REG(hw, FM10K_TC_MAXCREDIT(vf_idx), 0);\n\tFM10K_WRITE_REG(hw, FM10K_TC_RATE(vf_idx), 0);\n\tFM10K_WRITE_REG(hw, FM10K_TC_CREDIT(vf_idx),\n\t\t\tFM10K_TC_CREDIT_CREDIT_MASK);\n\n\t/* update our first entry in the table based on previous VF */\n\tif (!vf_idx)\n\t\thw->mac.ops.update_int_moderator(hw);\n\telse\n\t\thw->iov.ops.assign_int_moderator(hw, vf_idx - 1);\n\n\t/* reset linked list so it now includes our active vectors */\n\tif (vf_idx == (hw->iov.num_vfs - 1))\n\t\tFM10K_WRITE_REG(hw, FM10K_ITR2(0), vf_v_idx);\n\telse\n\t\tFM10K_WRITE_REG(hw, FM10K_ITR2(vf_v_limit), vf_v_idx);\n\n\t/* link remaining vectors so that next points to previous */\n\tfor (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++)\n\t\tFM10K_WRITE_REG(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1);\n\n\t/* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */\n\tfor (i = FM10K_VFMBMEM_LEN; i--;)\n\t\tFM10K_WRITE_REG(hw, FM10K_MBMEM_VF(vf_idx, i), 0);\n\tfor (i = FM10K_VLAN_TABLE_SIZE; i--;)\n\t\tFM10K_WRITE_REG(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0);\n\tfor (i = FM10K_RETA_SIZE; i--;)\n\t\tFM10K_WRITE_REG(hw, FM10K_RETA(vf_info->vsi, i), 0);\n\tfor (i = FM10K_RSSRK_SIZE; i--;)\n\t\tFM10K_WRITE_REG(hw, FM10K_RSSRK(vf_info->vsi, i), 0);\n\tFM10K_WRITE_REG(hw, FM10K_MRQC(vf_info->vsi), 0);\n\n\t/* Update base address registers to contain MAC address */\n\tif (FM10K_IS_VALID_ETHER_ADDR(vf_info->mac)) {\n\t\ttdbal = (((u32)vf_info->mac[3]) << 24) |\n\t\t\t(((u32)vf_info->mac[4]) << 16) |\n\t\t\t(((u32)vf_info->mac[5]) << 8);\n\t\ttdbah = (((u32)0xFF)\t << 24) |\n\t\t\t(((u32)vf_info->mac[0]) << 16) |\n\t\t\t(((u32)vf_info->mac[1]) << 8) |\n\t\t\t((u32)vf_info->mac[2]);\n\t}\n\n\t/* map queue pairs back to VF from last to first */\n\tfor (i = queues_per_pool; i--;) {\n\t\tFM10K_WRITE_REG(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);\n\t\tFM10K_WRITE_REG(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);\n\t\tFM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);\n\t\tFM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);\n\t}\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF\n * @hw: pointer to hardware structure\n * @vf_info: pointer to VF information structure\n * @lport_idx: Logical port offset from the hardware glort\n * @flags: Set of capability flags to extend port beyond basic functionality\n *\n * This function allows enabling a VF port by assigning it a GLORT and\n * setting the flags so that it can enable an Rx mode.\n **/\nSTATIC s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_vf_info *vf_info,\n\t\t\t\t u16 lport_idx, u8 flags)\n{\n\tu16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE;\n\n\tDEBUGFUNC(\"fm10k_iov_set_lport_state_pf\");\n\n\t/* if glort is not valid return error */\n\tif (!fm10k_glort_valid_pf(hw, glort))\n\t\treturn FM10K_ERR_PARAM;\n\n\tvf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE;\n\tvf_info->glort = glort;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF\n * @hw: pointer to hardware structure\n * @vf_info: pointer to VF information structure\n *\n * This function disables a VF port by stripping it of a GLORT and\n * setting the flags so that it cannot enable any Rx mode.\n **/\nSTATIC void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_vf_info *vf_info)\n{\n\tu32 msg[1];\n\n\tDEBUGFUNC(\"fm10k_iov_reset_lport_state_pf\");\n\n\t/* need to disable the port if it is already enabled */\n\tif (FM10K_VF_FLAG_ENABLED(vf_info)) {\n\t\t/* notify switch that this port has been disabled */\n\t\tfm10k_update_lport_state_pf(hw, vf_info->glort, 1, false);\n\n\t\t/* generate port state response to notify VF it is not ready */\n\t\tfm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);\n\t\tvf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);\n\t}\n\n\t/* clear flags and glort if it exists */\n\tvf_info->vf_flags = 0;\n\tvf_info->glort = 0;\n}\n\n/**\n * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs\n * @hw: pointer to hardware structure\n * @q: stats for all queues of a VF\n * @vf_idx: index of VF\n *\n * This function collects queue stats for VFs.\n **/\nSTATIC void fm10k_iov_update_stats_pf(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_hw_stats_q *q,\n\t\t\t\t u16 vf_idx)\n{\n\tu32 idx, qpp;\n\n\t/* get stats for all of the queues */\n\tqpp = fm10k_queues_per_pool(hw);\n\tidx = fm10k_vf_queue_index(hw, vf_idx);\n\tfm10k_update_hw_stats_q(hw, q, idx, qpp);\n}\n\nSTATIC s32 fm10k_iov_report_timestamp_pf(struct fm10k_hw *hw,\n\t\t\t\t\t struct fm10k_vf_info *vf_info,\n\t\t\t\t\t u64 timestamp)\n{\n\tu32 msg[4];\n\n\t/* generate port state response to notify VF it is not ready */\n\tfm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_1588);\n\tfm10k_tlv_attr_put_u64(msg, FM10K_1588_MSG_TIMESTAMP, timestamp);\n\n\treturn vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);\n}\n\n/**\n * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF\n * @hw: Pointer to hardware structure\n * @results: Pointer array to message, results[0] is pointer to message\n * @mbx: Pointer to mailbox information structure\n *\n * This function is a default handler for MSI-X requests from the VF. The\n * assumption is that in this case it is acceptable to just directly\n * hand off the message from the VF to the underlying shared code.\n **/\ns32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results,\n\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tstruct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;\n\tu8 vf_idx = vf_info->vf_idx;\n\n\tUNREFERENCED_1PARAMETER(results);\n\tDEBUGFUNC(\"fm10k_iov_msg_msix_pf\");\n\n\treturn hw->iov.ops.assign_int_moderator(hw, vf_idx);\n}\n\n/**\n * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF\n * @hw: Pointer to hardware structure\n * @results: Pointer array to message, results[0] is pointer to message\n * @mbx: Pointer to mailbox information structure\n *\n * This function is a default handler for MAC/VLAN requests from the VF.\n * The assumption is that in this case it is acceptable to just directly\n * hand off the message from the VF to the underlying shared code.\n **/\ns32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results,\n\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tstruct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;\n\tint err = FM10K_SUCCESS;\n\tu8 mac[ETH_ALEN];\n\tu32 *result;\n\tu16 vlan;\n\tu32 vid;\n\n\tDEBUGFUNC(\"fm10k_iov_msg_mac_vlan_pf\");\n\n\t/* we shouldn't be updating rules on a disabled interface */\n\tif (!FM10K_VF_FLAG_ENABLED(vf_info))\n\t\terr = FM10K_ERR_PARAM;\n\n\tif (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) {\n\t\tresult = results[FM10K_MAC_VLAN_MSG_VLAN];\n\n\t\t/* record VLAN id requested */\n\t\terr = fm10k_tlv_attr_get_u32(result, &vid);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\t/* if VLAN ID is 0, set the default VLAN ID instead of 0 */\n\t\tif (!vid || (vid == FM10K_VLAN_CLEAR)) {\n\t\t\tif (vf_info->pf_vid)\n\t\t\t\tvid |= vf_info->pf_vid;\n\t\t\telse\n\t\t\t\tvid |= vf_info->sw_vid;\n\t\t} else if (vid != vf_info->pf_vid) {\n\t\t\treturn FM10K_ERR_PARAM;\n\t\t}\n\n\t\t/* update VSI info for VF in regards to VLAN table */\n\t\terr = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi,\n\t\t\t\t\t !(vid & FM10K_VLAN_CLEAR));\n\t}\n\n\tif (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) {\n\t\tresult = results[FM10K_MAC_VLAN_MSG_MAC];\n\n\t\t/* record unicast MAC address requested */\n\t\terr = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\t/* block attempts to set MAC for a locked device */\n\t\tif (FM10K_IS_VALID_ETHER_ADDR(vf_info->mac) &&\n\t\t memcmp(mac, vf_info->mac, ETH_ALEN))\n\t\t\treturn FM10K_ERR_PARAM;\n\n\t\t/* if VLAN ID is 0, set the default VLAN ID instead of 0 */\n\t\tif (!vlan || (vlan == FM10K_VLAN_CLEAR)) {\n\t\t\tif (vf_info->pf_vid)\n\t\t\t\tvlan |= vf_info->pf_vid;\n\t\t\telse\n\t\t\t\tvlan |= vf_info->sw_vid;\n\t\t} else if (vf_info->pf_vid) {\n\t\t\treturn FM10K_ERR_PARAM;\n\t\t}\n\n\t\t/* notify switch of request for new unicast address */\n\t\terr = hw->mac.ops.update_uc_addr(hw, vf_info->glort, mac, vlan,\n\t\t\t\t\t\t !(vlan & FM10K_VLAN_CLEAR), 0);\n\t}\n\n\tif (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) {\n\t\tresult = results[FM10K_MAC_VLAN_MSG_MULTICAST];\n\n\t\t/* record multicast MAC address requested */\n\t\terr = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);\n\t\tif (err)\n\t\t\treturn err;\n\n\t\t/* verify that the VF is allowed to request multicast */\n\t\tif (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED))\n\t\t\treturn FM10K_ERR_PARAM;\n\n\t\t/* if VLAN ID is 0, set the default VLAN ID instead of 0 */\n\t\tif (!vlan || (vlan == FM10K_VLAN_CLEAR)) {\n\t\t\tif (vf_info->pf_vid)\n\t\t\t\tvlan |= vf_info->pf_vid;\n\t\t\telse\n\t\t\t\tvlan |= vf_info->sw_vid;\n\t\t} else if (vf_info->pf_vid) {\n\t\t\treturn FM10K_ERR_PARAM;\n\t\t}\n\n\t\t/* notify switch of request for new multicast address */\n\t\terr = hw->mac.ops.update_mc_addr(hw, vf_info->glort, mac,\n\t\t\t\t\t\t !(vlan & FM10K_VLAN_CLEAR), 0);\n\t}\n\n\treturn err;\n}\n\n/**\n * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode\n * @vf_info: VF info structure containing capability flags\n * @mode: Requested xcast mode\n *\n * This function outputs the mode that most closely matches the requested\n * mode. If not modes match it will request we disable the port\n **/\nSTATIC u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info,\n\t\t\t\t\t u8 mode)\n{\n\tu8 vf_flags = vf_info->vf_flags;\n\n\t/* match up mode to capabilities as best as possible */\n\tswitch (mode) {\n\tcase FM10K_XCAST_MODE_PROMISC:\n\t\tif (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE)\n\t\t\treturn FM10K_XCAST_MODE_PROMISC;\n\t\t/* fallthough */\n\tcase FM10K_XCAST_MODE_ALLMULTI:\n\t\tif (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE)\n\t\t\treturn FM10K_XCAST_MODE_ALLMULTI;\n\t\t/* fallthough */\n\tcase FM10K_XCAST_MODE_MULTI:\n\t\tif (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE)\n\t\t\treturn FM10K_XCAST_MODE_MULTI;\n\t\t/* fallthough */\n\tcase FM10K_XCAST_MODE_NONE:\n\t\tif (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)\n\t\t\treturn FM10K_XCAST_MODE_NONE;\n\t\t/* fallthough */\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* disable interface as it should not be able to request any */\n\treturn FM10K_XCAST_MODE_DISABLE;\n}\n\n/**\n * fm10k_iov_msg_lport_state_pf - Message handler for port state requests\n * @hw: Pointer to hardware structure\n * @results: Pointer array to message, results[0] is pointer to message\n * @mbx: Pointer to mailbox information structure\n *\n * This function is a default handler for port state requests. The port\n * state requests for now are basic and consist of enabling or disabling\n * the port.\n **/\ns32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results,\n\t\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tstruct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;\n\tu32 *result;\n\ts32 err = FM10K_SUCCESS;\n\tu32 msg[2];\n\tu8 mode = 0;\n\n\tDEBUGFUNC(\"fm10k_iov_msg_lport_state_pf\");\n\n\t/* verify VF is allowed to enable even minimal mode */\n\tif (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE))\n\t\treturn FM10K_ERR_PARAM;\n\n\tif (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) {\n\t\tresult = results[FM10K_LPORT_STATE_MSG_XCAST_MODE];\n\n\t\t/* XCAST mode update requested */\n\t\terr = fm10k_tlv_attr_get_u8(result, &mode);\n\t\tif (err)\n\t\t\treturn FM10K_ERR_PARAM;\n\n\t\t/* prep for possible demotion depending on capabilities */\n\t\tmode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode);\n\n\t\t/* if mode is not currently enabled, enable it */\n\t\tif (!(FM10K_VF_FLAG_ENABLED(vf_info) & (1 << mode)))\n\t\t\tfm10k_update_xcast_mode_pf(hw, vf_info->glort, mode);\n\n\t\t/* swap mode back to a bit flag */\n\t\tmode = FM10K_VF_FLAG_SET_MODE(mode);\n\t} else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) {\n\t\t/* need to disable the port if it is already enabled */\n\t\tif (FM10K_VF_FLAG_ENABLED(vf_info))\n\t\t\terr = fm10k_update_lport_state_pf(hw, vf_info->glort,\n\t\t\t\t\t\t\t 1, false);\n\n\t\t/* when enabling the port we should reset the rate limiters */\n\t\thw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate);\n\n\t\t/* set mode for minimal functionality */\n\t\tmode = FM10K_VF_FLAG_SET_MODE_NONE;\n\n\t\t/* generate port state response to notify VF it is ready */\n\t\tfm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);\n\t\tfm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY);\n\t\tmbx->ops.enqueue_tx(hw, mbx, msg);\n\t}\n\n\t/* if enable state toggled note the update */\n\tif (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode))\n\t\terr = fm10k_update_lport_state_pf(hw, vf_info->glort, 1,\n\t\t\t\t\t\t !!mode);\n\n\t/* if state change succeeded, then update our stored state */\n\tmode |= FM10K_VF_FLAG_CAPABLE(vf_info);\n\tif (!err)\n\t\tvf_info->vf_flags = mode;\n\n\treturn err;\n}\n\nconst struct fm10k_msg_data fm10k_iov_msg_data_pf[] = {\n\tFM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),\n\tFM10K_VF_MSG_MSIX_HANDLER(fm10k_iov_msg_msix_pf),\n\tFM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_iov_msg_mac_vlan_pf),\n\tFM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_iov_msg_lport_state_pf),\n\tFM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),\n};\n\n/**\n * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF\n * @hw: pointer to hardware structure\n * @stats: pointer to the stats structure to update\n *\n * This function collects and aggregates global and per queue hardware\n * statistics.\n **/\nSTATIC void fm10k_update_hw_stats_pf(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_hw_stats *stats)\n{\n\tu32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop;\n\tu32 id, id_prev;\n\n\tDEBUGFUNC(\"fm10k_update_hw_stats_pf\");\n\n\t/* Use Tx queue 0 as a canary to detect a reset */\n\tid = FM10K_READ_REG(hw, FM10K_TXQCTL(0));\n\n\t/* Read Global Statistics */\n\tdo {\n\t\ttimeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT,\n\t\t\t\t\t\t &stats->timeout);\n\t\tur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur);\n\t\tca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca);\n\t\tum = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um);\n\t\txec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec);\n\t\tvlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP,\n\t\t\t\t\t\t &stats->vlan_drop);\n\t\tloopback_drop = fm10k_read_hw_stats_32b(hw,\n\t\t\t\t\t\t\tFM10K_STATS_LOOPBACK_DROP,\n\t\t\t\t\t\t\t&stats->loopback_drop);\n\t\tnodesc_drop = fm10k_read_hw_stats_32b(hw,\n\t\t\t\t\t\t FM10K_STATS_NODESC_DROP,\n\t\t\t\t\t\t &stats->nodesc_drop);\n\n\t\t/* if value has not changed then we have consistent data */\n\t\tid_prev = id;\n\t\tid = FM10K_READ_REG(hw, FM10K_TXQCTL(0));\n\t} while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK);\n\n\t/* drop non-ID bits and set VALID ID bit */\n\tid &= FM10K_TXQCTL_ID_MASK;\n\tid |= FM10K_STAT_VALID;\n\n\t/* Update Global Statistics */\n\tif (stats->stats_idx == id) {\n\t\tstats->timeout.count += timeout;\n\t\tstats->ur.count += ur;\n\t\tstats->ca.count += ca;\n\t\tstats->um.count += um;\n\t\tstats->xec.count += xec;\n\t\tstats->vlan_drop.count += vlan_drop;\n\t\tstats->loopback_drop.count += loopback_drop;\n\t\tstats->nodesc_drop.count += nodesc_drop;\n\t}\n\n\t/* Update bases and record current PF id */\n\tfm10k_update_hw_base_32b(&stats->timeout, timeout);\n\tfm10k_update_hw_base_32b(&stats->ur, ur);\n\tfm10k_update_hw_base_32b(&stats->ca, ca);\n\tfm10k_update_hw_base_32b(&stats->um, um);\n\tfm10k_update_hw_base_32b(&stats->xec, xec);\n\tfm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop);\n\tfm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop);\n\tfm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop);\n\tstats->stats_idx = id;\n\n\t/* Update Queue Statistics */\n\tfm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);\n}\n\n/**\n * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF\n * @hw: pointer to hardware structure\n * @stats: pointer to the stats structure to update\n *\n * This function resets the base for global and per queue hardware\n * statistics.\n **/\nSTATIC void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_hw_stats *stats)\n{\n\tDEBUGFUNC(\"fm10k_rebind_hw_stats_pf\");\n\n\t/* Unbind Global Statistics */\n\tfm10k_unbind_hw_stats_32b(&stats->timeout);\n\tfm10k_unbind_hw_stats_32b(&stats->ur);\n\tfm10k_unbind_hw_stats_32b(&stats->ca);\n\tfm10k_unbind_hw_stats_32b(&stats->um);\n\tfm10k_unbind_hw_stats_32b(&stats->xec);\n\tfm10k_unbind_hw_stats_32b(&stats->vlan_drop);\n\tfm10k_unbind_hw_stats_32b(&stats->loopback_drop);\n\tfm10k_unbind_hw_stats_32b(&stats->nodesc_drop);\n\n\t/* Unbind Queue Statistics */\n\tfm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);\n\n\t/* Reinitialize bases for all stats */\n\tfm10k_update_hw_stats_pf(hw, stats);\n}\n\n/**\n * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system\n * @hw: pointer to hardware structure\n * @dma_mask: 64 bit DMA mask required for platform\n *\n * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order\n * to limit the access to memory beyond what is physically in the system.\n **/\nSTATIC void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask)\n{\n\t/* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */\n\tu32 phyaddr = (u32)(dma_mask >> 32);\n\n\tDEBUGFUNC(\"fm10k_set_dma_mask_pf\");\n\n\tFM10K_WRITE_REG(hw, FM10K_PHYADDR, phyaddr);\n}\n\n/**\n * fm10k_get_fault_pf - Record a fault in one of the interface units\n * @hw: pointer to hardware structure\n * @type: pointer to fault type register offset\n * @fault: pointer to memory location to record the fault\n *\n * Record the fault register contents to the fault data structure and\n * clear the entry from the register.\n *\n * Returns ERR_PARAM if invalid register is specified or no error is present.\n **/\nSTATIC s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type,\n\t\t\t struct fm10k_fault *fault)\n{\n\tu32 func;\n\n\tDEBUGFUNC(\"fm10k_get_fault_pf\");\n\n\t/* verify the fault register is in range and is aligned */\n\tswitch (type) {\n\tcase FM10K_PCA_FAULT:\n\tcase FM10K_THI_FAULT:\n\tcase FM10K_FUM_FAULT:\n\t\tbreak;\n\tdefault:\n\t\treturn FM10K_ERR_PARAM;\n\t}\n\n\t/* only service faults that are valid */\n\tfunc = FM10K_READ_REG(hw, type + FM10K_FAULT_FUNC);\n\tif (!(func & FM10K_FAULT_FUNC_VALID))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* read remaining fields */\n\tfault->address = FM10K_READ_REG(hw, type + FM10K_FAULT_ADDR_HI);\n\tfault->address <<= 32;\n\tfault->address = FM10K_READ_REG(hw, type + FM10K_FAULT_ADDR_LO);\n\tfault->specinfo = FM10K_READ_REG(hw, type + FM10K_FAULT_SPECINFO);\n\n\t/* clear valid bit to allow for next error */\n\tFM10K_WRITE_REG(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID);\n\n\t/* Record which function triggered the error */\n\tif (func & FM10K_FAULT_FUNC_PF)\n\t\tfault->func = 0;\n\telse\n\t\tfault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >>\n\t\t\t\t FM10K_FAULT_FUNC_VF_SHIFT);\n\n\t/* record fault type */\n\tfault->type = func & FM10K_FAULT_FUNC_TYPE_MASK;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_request_lport_map_pf - Request LPORT map from the switch API\n * @hw: pointer to hardware structure\n *\n **/\nSTATIC s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw)\n{\n\tstruct fm10k_mbx_info *mbx = &hw->mbx;\n\tu32 msg[1];\n\n\tDEBUGFUNC(\"fm10k_request_lport_pf\");\n\n\t/* issue request asking for LPORT map */\n\tfm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP);\n\n\t/* load onto outgoing mailbox */\n\treturn mbx->ops.enqueue_tx(hw, mbx, msg);\n}\n\n/**\n * fm10k_get_host_state_pf - Returns the state of the switch and mailbox\n * @hw: pointer to hardware structure\n * @switch_ready: pointer to boolean value that will record switch state\n *\n * This funciton will check the DMA_CTRL2 register and mailbox in order\n * to determine if the switch is ready for the PF to begin requesting\n * addresses and mapping traffic to the local interface.\n **/\nSTATIC s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready)\n{\n\ts32 ret_val = FM10K_SUCCESS;\n\tu32 dma_ctrl2;\n\n\tDEBUGFUNC(\"fm10k_get_host_state_pf\");\n\n\t/* verify the switch is ready for interaction */\n\tdma_ctrl2 = FM10K_READ_REG(hw, FM10K_DMA_CTRL2);\n\tif (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY))\n\t\tgoto out;\n\n\t/* retrieve generic host state info */\n\tret_val = fm10k_get_host_state_generic(hw, switch_ready);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/* interface cannot receive traffic without logical ports */\n\tif (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE)\n\t\tret_val = fm10k_request_lport_map_pf(hw);\n\nout:\n\treturn ret_val;\n}\n\n/* This structure defines the attibutes to be parsed below */\nconst struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = {\n\tFM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP),\n\tFM10K_TLV_ATTR_LAST\n};\n\n/**\n * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM\n * @hw: Pointer to hardware structure\n * @results: pointer array containing parsed data\n * @mbx: Pointer to mailbox information structure\n *\n * This handler configures the lport mapping based on the reply from the\n * switch API.\n **/\ns32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results,\n\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tu16 glort, mask;\n\tu32 dglort_map;\n\ts32 err;\n\n\tUNREFERENCED_1PARAMETER(mbx);\n\tDEBUGFUNC(\"fm10k_msg_lport_map_pf\");\n\n\terr = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP],\n\t\t\t\t &dglort_map);\n\tif (err)\n\t\treturn err;\n\n\t/* extract values out of the header */\n\tglort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT);\n\tmask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK);\n\n\t/* verify mask is set and none of the masked bits in glort are set */\n\tif (!mask || (glort & ~mask))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* verify the mask is contiguous, and that it is 1's followed by 0's */\n\tif (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* record the glort, mask, and port count */\n\thw->mac.dglort_map = dglort_map;\n\n\treturn FM10K_SUCCESS;\n}\n\nconst struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = {\n\tFM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID),\n\tFM10K_TLV_ATTR_LAST\n};\n\n/**\n * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM\n * @hw: Pointer to hardware structure\n * @results: pointer array containing parsed data\n * @mbx: Pointer to mailbox information structure\n *\n * This handler configures the default VLAN for the PF\n **/\ns32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results,\n\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tu16 glort, pvid;\n\tu32 pvid_update;\n\ts32 err;\n\n\tUNREFERENCED_1PARAMETER(mbx);\n\tDEBUGFUNC(\"fm10k_msg_update_pvid_pf\");\n\n\terr = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],\n\t\t\t\t &pvid_update);\n\tif (err)\n\t\treturn err;\n\n\t/* extract values from the pvid update */\n\tglort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);\n\tpvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);\n\n\t/* if glort is not valid return error */\n\tif (!fm10k_glort_valid_pf(hw, glort))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* verify VID is valid */\n\tif (pvid >= FM10K_VLAN_TABLE_VID_MAX)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* record the port VLAN ID value */\n\thw->mac.default_vid = pvid;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_record_global_table_data - Move global table data to swapi table info\n * @from: pointer to source table data structure\n * @to: pointer to destination table info structure\n *\n * This function is will copy table_data to the table_info contained in\n * the hw struct.\n **/\nstatic void fm10k_record_global_table_data(struct fm10k_global_table_data *from,\n\t\t\t\t\t struct fm10k_swapi_table_info *to)\n{\n\t/* convert from le32 struct to CPU byte ordered values */\n\tto->used = FM10K_LE32_TO_CPU(from->used);\n\tto->avail = FM10K_LE32_TO_CPU(from->avail);\n}\n\nconst struct fm10k_tlv_attr fm10k_err_msg_attr[] = {\n\tFM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,\n\t\t\t\t sizeof(struct fm10k_swapi_error)),\n\tFM10K_TLV_ATTR_LAST\n};\n\n/**\n * fm10k_msg_err_pf - Message handler for error reply\n * @hw: Pointer to hardware structure\n * @results: pointer array containing parsed data\n * @mbx: Pointer to mailbox information structure\n *\n * This handler will capture the data for any error replies to previous\n * messages that the PF has sent.\n **/\ns32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results,\n\t\t struct fm10k_mbx_info *mbx)\n{\n\tstruct fm10k_swapi_error err_msg;\n\ts32 err;\n\n\tUNREFERENCED_1PARAMETER(mbx);\n\tDEBUGFUNC(\"fm10k_msg_err_pf\");\n\n\t/* extract structure from message */\n\terr = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR],\n\t\t\t\t\t &err_msg, sizeof(err_msg));\n\tif (err)\n\t\treturn err;\n\n\t/* record table status */\n\tfm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac);\n\tfm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop);\n\tfm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu);\n\n\t/* record SW API status value */\n\thw->swapi.status = FM10K_LE32_TO_CPU(err_msg.status);\n\n\treturn FM10K_SUCCESS;\n}\n\nconst struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = {\n\tFM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP,\n\t\t\t\t sizeof(struct fm10k_swapi_1588_timestamp)),\n\tFM10K_TLV_ATTR_LAST\n};\n\n/* currently there is no shared 1588 timestamp handler */\n\n/**\n * fm10k_request_tx_timestamp_mode_pf - Request a specific Tx timestamping mode\n * @hw: pointer to hardware structure\n * @glort: base resource tag for this request\n * @mode: integer value indicating the requested mode\n *\n * This function will attempt to request a specific timestamp mode for the\n * port so that it can receive Tx timestamp messages.\n **/\nSTATIC s32 fm10k_request_tx_timestamp_mode_pf(struct fm10k_hw *hw,\n\t\t\t\t\t u16 glort,\n\t\t\t\t\t u8 mode)\n{\n\tstruct fm10k_mbx_info *mbx = &hw->mbx;\n\tu32 msg[3], timestamp_mode;\n\n\tDEBUGFUNC(\"fm10k_request_timestamp_mode_pf\");\n\n\tif (mode > FM10K_TIMESTAMP_MODE_PEP_TO_ANY)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* if glort is not valid return error */\n\tif (!fm10k_glort_valid_pf(hw, glort))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* write timestamp mode as a single u32 value,\n\t * lower 16 bits: glort\n\t * upper 16 bits: mode\n\t */\n\ttimestamp_mode = ((u32)mode << 16) | glort;\n\n\t/* generate message requesting change to xcast mode */\n\tfm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_TX_TIMESTAMP_MODE);\n\tfm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_TIMESTAMP_MODE_REQ, timestamp_mode);\n\n\t/* load onto outgoing mailbox */\n\treturn mbx->ops.enqueue_tx(hw, mbx, msg);\n}\n\n/**\n * fm10k_adjust_systime_pf - Adjust systime frequency\n * @hw: pointer to hardware structure\n * @ppb: adjustment rate in parts per billion\n *\n * This function will adjust the SYSTIME_CFG register contained in BAR 4\n * if this function is supported for BAR 4 access. The adjustment amount\n * is based on the parts per billion value provided and adjusted to a\n * value based on parts per 2^48 clock cycles.\n *\n * If adjustment is not supported or the requested value is too large\n * we will return an error.\n **/\nSTATIC s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb)\n{\n\tu64 systime_adjust;\n\n\tDEBUGFUNC(\"fm10k_adjust_systime_vf\");\n\n\t/* if sw_addr is not set we don't have switch register access */\n\tif (!hw->sw_addr)\n\t\treturn ppb ? FM10K_ERR_PARAM : FM10K_SUCCESS;\n\n\t/* we must convert the value from parts per billion to parts per\n\t * 2^48 cycles. In addition I have opted to only use the 30 most\n\t * significant bits of the adjustment value as the 8 least\n\t * significant bits are located in another register and represent\n\t * a value significantly less than a part per billion, the result\n\t * of dropping the 8 least significant bits is that the adjustment\n\t * value is effectively multiplied by 2^8 when we write it.\n\t *\n\t * As a result of all this the math for this breaks down as follows:\n\t *\tppb / 10^9 == adjust * 2^8 / 2^48\n\t * If we solve this for adjust, and simplify it comes out as:\n\t *\tppb * 2^31 / 5^9 == adjust\n\t */\n\tsystime_adjust = (ppb < 0) ? -ppb : ppb;\n\tsystime_adjust <<= 31;\n\tdo_div(systime_adjust, 1953125);\n\n\t/* verify the requested adjustment value is in range */\n\tif (systime_adjust > FM10K_SW_SYSTIME_ADJUST_MASK)\n\t\treturn FM10K_ERR_PARAM;\n\n\tif (ppb < 0)\n\t\tsystime_adjust |= FM10K_SW_SYSTIME_ADJUST_DIR_NEGATIVE;\n\n\tFM10K_WRITE_SW_REG(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_read_systime_pf - Reads value of systime registers\n * @hw: pointer to the hardware structure\n *\n * Function reads the content of 2 registers, combined to represent a 64 bit\n * value measured in nanosecods. In order to guarantee the value is accurate\n * we check the 32 most significant bits both before and after reading the\n * 32 least significant bits to verify they didn't change as we were reading\n * the registers.\n **/\nstatic u64 fm10k_read_systime_pf(struct fm10k_hw *hw)\n{\n\tu32 systime_l, systime_h, systime_tmp;\n\n\tsystime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);\n\n\tdo {\n\t\tsystime_tmp = systime_h;\n\t\tsystime_l = fm10k_read_reg(hw, FM10K_SYSTIME);\n\t\tsystime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);\n\t} while (systime_tmp != systime_h);\n\n\treturn ((u64)systime_h << 32) | systime_l;\n}\n\nstatic const struct fm10k_msg_data fm10k_msg_data_pf[] = {\n\tFM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),\n\tFM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),\n\tFM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf),\n\tFM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),\n\tFM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),\n\tFM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),\n\tFM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),\n};\n\n/**\n * fm10k_init_ops_pf - Inits func ptrs and MAC type\n * @hw: pointer to hardware structure\n *\n * Initialize the function pointers and assign the MAC type for PF.\n * Does not touch the hardware.\n **/\ns32 fm10k_init_ops_pf(struct fm10k_hw *hw)\n{\n\tstruct fm10k_mac_info *mac = &hw->mac;\n\tstruct fm10k_iov_info *iov = &hw->iov;\n\n\tDEBUGFUNC(\"fm10k_init_ops_pf\");\n\n\tfm10k_init_ops_generic(hw);\n\n\tmac->ops.reset_hw = &fm10k_reset_hw_pf;\n\tmac->ops.init_hw = &fm10k_init_hw_pf;\n\tmac->ops.start_hw = &fm10k_start_hw_generic;\n\tmac->ops.stop_hw = &fm10k_stop_hw_generic;\n\tmac->ops.is_slot_appropriate = &fm10k_is_slot_appropriate_pf;\n\tmac->ops.update_vlan = &fm10k_update_vlan_pf;\n\tmac->ops.read_mac_addr = &fm10k_read_mac_addr_pf;\n\tmac->ops.update_uc_addr = &fm10k_update_uc_addr_pf;\n\tmac->ops.update_mc_addr = &fm10k_update_mc_addr_pf;\n\tmac->ops.update_xcast_mode = &fm10k_update_xcast_mode_pf;\n\tmac->ops.update_int_moderator = &fm10k_update_int_moderator_pf;\n\tmac->ops.update_lport_state = &fm10k_update_lport_state_pf;\n\tmac->ops.update_hw_stats = &fm10k_update_hw_stats_pf;\n\tmac->ops.rebind_hw_stats = &fm10k_rebind_hw_stats_pf;\n\tmac->ops.configure_dglort_map = &fm10k_configure_dglort_map_pf;\n\tmac->ops.set_dma_mask = &fm10k_set_dma_mask_pf;\n\tmac->ops.get_fault = &fm10k_get_fault_pf;\n\tmac->ops.get_host_state = &fm10k_get_host_state_pf;\n\tmac->ops.adjust_systime = &fm10k_adjust_systime_pf;\n\tmac->ops.read_systime = &fm10k_read_systime_pf;\n\tmac->ops.request_tx_timestamp_mode = &fm10k_request_tx_timestamp_mode_pf;\n\n\tmac->max_msix_vectors = fm10k_get_pcie_msix_count_generic(hw);\n\n\tiov->ops.assign_resources = &fm10k_iov_assign_resources_pf;\n\tiov->ops.configure_tc = &fm10k_iov_configure_tc_pf;\n\tiov->ops.assign_int_moderator = &fm10k_iov_assign_int_moderator_pf;\n\tiov->ops.assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf;\n\tiov->ops.reset_resources = &fm10k_iov_reset_resources_pf;\n\tiov->ops.set_lport = &fm10k_iov_set_lport_pf;\n\tiov->ops.reset_lport = &fm10k_iov_reset_lport_pf;\n\tiov->ops.update_stats = &fm10k_iov_update_stats_pf;\n\tiov->ops.report_timestamp = &fm10k_iov_report_timestamp_pf;\n\n\treturn fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf);\n}\n" }, { "path": "drivers/net/fm10k/base/fm10k_pf.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _FM10K_PF_H_\n#define _FM10K_PF_H_\n\n#include \"fm10k_type.h\"\n#include \"fm10k_common.h\"\n\nbool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort);\nu16 fm10k_queues_per_pool(struct fm10k_hw *hw);\nu16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx);\n\nenum fm10k_pf_tlv_msg_id_v1 {\n\tFM10K_PF_MSG_ID_TEST\t\t\t= 0x000, /* msg ID reserved */\n\tFM10K_PF_MSG_ID_XCAST_MODES\t\t= 0x001,\n\tFM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE\t= 0x002,\n\tFM10K_PF_MSG_ID_LPORT_MAP\t\t= 0x100,\n\tFM10K_PF_MSG_ID_LPORT_CREATE\t\t= 0x200,\n\tFM10K_PF_MSG_ID_LPORT_DELETE\t\t= 0x201,\n\tFM10K_PF_MSG_ID_CONFIG\t\t\t= 0x300,\n\tFM10K_PF_MSG_ID_UPDATE_PVID\t\t= 0x400,\n\tFM10K_PF_MSG_ID_CREATE_FLOW_TABLE\t= 0x501,\n\tFM10K_PF_MSG_ID_DELETE_FLOW_TABLE\t= 0x502,\n\tFM10K_PF_MSG_ID_UPDATE_FLOW\t\t= 0x503,\n\tFM10K_PF_MSG_ID_DELETE_FLOW\t\t= 0x504,\n\tFM10K_PF_MSG_ID_SET_FLOW_STATE\t\t= 0x505,\n\tFM10K_PF_MSG_ID_GET_1588_INFO\t\t= 0x506,\n\tFM10K_PF_MSG_ID_1588_TIMESTAMP\t\t= 0x701,\n\tFM10K_PF_MSG_ID_TX_TIMESTAMP_MODE\t= 0x702,\n};\n\nenum fm10k_pf_tlv_attr_id_v1 {\n\tFM10K_PF_ATTR_ID_ERR\t\t\t= 0x00,\n\tFM10K_PF_ATTR_ID_LPORT_MAP\t\t= 0x01,\n\tFM10K_PF_ATTR_ID_XCAST_MODE\t\t= 0x02,\n\tFM10K_PF_ATTR_ID_MAC_UPDATE\t\t= 0x03,\n\tFM10K_PF_ATTR_ID_VLAN_UPDATE\t\t= 0x04,\n\tFM10K_PF_ATTR_ID_CONFIG\t\t\t= 0x05,\n\tFM10K_PF_ATTR_ID_CREATE_FLOW_TABLE\t= 0x06,\n\tFM10K_PF_ATTR_ID_DELETE_FLOW_TABLE\t= 0x07,\n\tFM10K_PF_ATTR_ID_UPDATE_FLOW\t\t= 0x08,\n\tFM10K_PF_ATTR_ID_FLOW_STATE\t\t= 0x09,\n\tFM10K_PF_ATTR_ID_FLOW_HANDLE\t\t= 0x0A,\n\tFM10K_PF_ATTR_ID_DELETE_FLOW\t\t= 0x0B,\n\tFM10K_PF_ATTR_ID_PORT\t\t\t= 0x0C,\n\tFM10K_PF_ATTR_ID_UPDATE_PVID\t\t= 0x0D,\n\tFM10K_PF_ATTR_ID_1588_TIMESTAMP\t\t= 0x10,\n\tFM10K_PF_ATTR_ID_TIMESTAMP_MODE_REQ\t= 0x11,\n\tFM10K_PF_ATTR_ID_TIMESTAMP_MODE_RESP\t= 0x12,\n};\n\n#define FM10K_MSG_LPORT_MAP_GLORT_SHIFT\t0\n#define FM10K_MSG_LPORT_MAP_GLORT_SIZE\t16\n#define FM10K_MSG_LPORT_MAP_MASK_SHIFT\t16\n#define FM10K_MSG_LPORT_MAP_MASK_SIZE\t16\n\n#define FM10K_MSG_UPDATE_PVID_GLORT_SHIFT\t0\n#define FM10K_MSG_UPDATE_PVID_GLORT_SIZE\t16\n#define FM10K_MSG_UPDATE_PVID_PVID_SHIFT\t16\n#define FM10K_MSG_UPDATE_PVID_PVID_SIZE\t\t16\n\nstruct fm10k_mac_update {\n\t__le32\tmac_lower;\n\t__le16\tmac_upper;\n\t__le16\tvlan;\n\t__le16\tglort;\n\tu8\tflags;\n\tu8\taction;\n};\n\nstruct fm10k_global_table_data {\n\t__le32\tused;\n\t__le32\tavail;\n};\n\nstruct fm10k_swapi_error {\n\t__le32\t\t\t\tstatus;\n\tstruct fm10k_global_table_data\tmac;\n\tstruct fm10k_global_table_data\tnexthop;\n\tstruct fm10k_global_table_data\tffu;\n};\n\nstruct fm10k_swapi_1588_timestamp {\n\t__le64 egress;\n\t__le64 ingress;\n\t__le16 dglort;\n\t__le16 sglort;\n};\n\n#define FM10K_PF_MSG_LPORT_CREATE_HANDLER(func) \\\n\tFM10K_MSG_HANDLER(FM10K_PF_MSG_ID_LPORT_CREATE, NULL, func)\n#define FM10K_PF_MSG_LPORT_DELETE_HANDLER(func) \\\n\tFM10K_MSG_HANDLER(FM10K_PF_MSG_ID_LPORT_DELETE, NULL, func)\ns32 fm10k_msg_lport_map_pf(struct fm10k_hw *, u32 **, struct fm10k_mbx_info *);\nextern const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[];\n#define FM10K_PF_MSG_LPORT_MAP_HANDLER(func) \\\n\tFM10K_MSG_HANDLER(FM10K_PF_MSG_ID_LPORT_MAP, \\\n\t\t\t fm10k_lport_map_msg_attr, func)\ns32 fm10k_msg_update_pvid_pf(struct fm10k_hw *, u32 **,\n\t\t\t struct fm10k_mbx_info *);\nextern const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[];\n#define FM10K_PF_MSG_UPDATE_PVID_HANDLER(func) \\\n\tFM10K_MSG_HANDLER(FM10K_PF_MSG_ID_UPDATE_PVID, \\\n\t\t\t fm10k_update_pvid_msg_attr, func)\n\ns32 fm10k_msg_err_pf(struct fm10k_hw *, u32 **, struct fm10k_mbx_info *);\nextern const struct fm10k_tlv_attr fm10k_err_msg_attr[];\n#define FM10K_PF_MSG_ERR_HANDLER(msg, func) \\\n\tFM10K_MSG_HANDLER(FM10K_PF_MSG_ID_##msg, fm10k_err_msg_attr, func)\n\nextern const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[];\n#define FM10K_PF_MSG_1588_TIMESTAMP_HANDLER(func) \\\n\tFM10K_MSG_HANDLER(FM10K_PF_MSG_ID_1588_TIMESTAMP, \\\n\t\t\t fm10k_1588_timestamp_msg_attr, func)\n\ns32 fm10k_iov_msg_msix_pf(struct fm10k_hw *, u32 **, struct fm10k_mbx_info *);\ns32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *, u32 **,\n\t\t\t struct fm10k_mbx_info *);\ns32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *, u32 **,\n\t\t\t\t struct fm10k_mbx_info *);\nextern const struct fm10k_msg_data fm10k_iov_msg_data_pf[];\n\ns32 fm10k_init_ops_pf(struct fm10k_hw *hw);\n#endif /* _FM10K_PF_H */\n" }, { "path": "drivers/net/fm10k/base/fm10k_tlv.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"fm10k_tlv.h\"\n\n/**\n * fm10k_tlv_msg_init - Initialize message block for TLV data storage\n * @msg: Pointer to message block\n * @msg_id: Message ID indicating message type\n *\n * This function return success if provided with a valid message pointer\n **/\ns32 fm10k_tlv_msg_init(u32 *msg, u16 msg_id)\n{\n\tDEBUGFUNC(\"fm10k_tlv_msg_init\");\n\n\t/* verify pointer is not NULL */\n\tif (!msg)\n\t\treturn FM10K_ERR_PARAM;\n\n\t*msg = (FM10K_TLV_FLAGS_MSG << FM10K_TLV_FLAGS_SHIFT) | msg_id;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_attr_put_null_string - Place null terminated string on message\n * @msg: Pointer to message block\n * @attr_id: Attribute ID\n * @string: Pointer to string to be stored in attribute\n *\n * This function will reorder a string to be CPU endian and store it in\n * the attribute buffer. It will return success if provided with a valid\n * pointers.\n **/\ns32 fm10k_tlv_attr_put_null_string(u32 *msg, u16 attr_id,\n\t\t\t\t const unsigned char *string)\n{\n\tu32 attr_data = 0, len = 0;\n\tu32 *attr;\n\n\tDEBUGFUNC(\"fm10k_tlv_attr_put_null_string\");\n\n\t/* verify pointers are not NULL */\n\tif (!string || !msg)\n\t\treturn FM10K_ERR_PARAM;\n\n\tattr = &msg[FM10K_TLV_DWORD_LEN(*msg)];\n\n\t/* copy string into local variable and then write to msg */\n\tdo {\n\t\t/* write data to message */\n\t\tif (len && !(len % 4)) {\n\t\t\tattr[len / 4] = attr_data;\n\t\t\tattr_data = 0;\n\t\t}\n\n\t\t/* record character to offset location */\n\t\tattr_data |= (u32)(*string) << (8 * (len % 4));\n\t\tlen++;\n\n\t\t/* test for NULL and then increment */\n\t} while (*(string++));\n\n\t/* write last piece of data to message */\n\tattr[(len + 3) / 4] = attr_data;\n\n\t/* record attribute header, update message length */\n\tlen <<= FM10K_TLV_LEN_SHIFT;\n\tattr[0] = len | attr_id;\n\n\t/* add header length to length */\n\tlen += FM10K_TLV_HDR_LEN << FM10K_TLV_LEN_SHIFT;\n\t*msg += FM10K_TLV_LEN_ALIGN(len);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_attr_get_null_string - Get null terminated string from attribute\n * @attr: Pointer to attribute\n * @string: Pointer to location of destination string\n *\n * This function pulls the string back out of the attribute and will place\n * it in the array pointed by by string. It will return success if provided\n * with a valid pointers.\n **/\ns32 fm10k_tlv_attr_get_null_string(u32 *attr, unsigned char *string)\n{\n\tu32 len;\n\n\tDEBUGFUNC(\"fm10k_tlv_attr_get_null_string\");\n\n\t/* verify pointers are not NULL */\n\tif (!string || !attr)\n\t\treturn FM10K_ERR_PARAM;\n\n\tlen = *attr >> FM10K_TLV_LEN_SHIFT;\n\tattr++;\n\n\twhile (len--)\n\t\tstring[len] = (u8)(attr[len / 4] >> (8 * (len % 4)));\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_attr_put_mac_vlan - Store MAC/VLAN attribute in message\n * @msg: Pointer to message block\n * @attr_id: Attribute ID\n * @mac_addr: MAC address to be stored\n *\n * This function will reorder a MAC address to be CPU endian and store it\n * in the attribute buffer. It will return success if provided with a\n * valid pointers.\n **/\ns32 fm10k_tlv_attr_put_mac_vlan(u32 *msg, u16 attr_id,\n\t\t\t\tconst u8 *mac_addr, u16 vlan)\n{\n\tu32 len = ETH_ALEN << FM10K_TLV_LEN_SHIFT;\n\tu32 *attr;\n\n\tDEBUGFUNC(\"fm10k_tlv_attr_put_mac_vlan\");\n\n\t/* verify pointers are not NULL */\n\tif (!msg || !mac_addr)\n\t\treturn FM10K_ERR_PARAM;\n\n\tattr = &msg[FM10K_TLV_DWORD_LEN(*msg)];\n\n\t/* record attribute header, update message length */\n\tattr[0] = len | attr_id;\n\n\t/* copy value into local variable and then write to msg */\n\tattr[1] = FM10K_LE32_TO_CPU(*(const __le32 *)&mac_addr[0]);\n\tattr[2] = FM10K_LE16_TO_CPU(*(const __le16 *)&mac_addr[4]);\n\tattr[2] |= (u32)vlan << 16;\n\n\t/* add header length to length */\n\tlen += FM10K_TLV_HDR_LEN << FM10K_TLV_LEN_SHIFT;\n\t*msg += FM10K_TLV_LEN_ALIGN(len);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_attr_get_mac_vlan - Get MAC/VLAN stored in attribute\n * @attr: Pointer to attribute\n * @attr_id: Attribute ID\n * @mac_addr: location of buffer to store MAC address\n *\n * This function pulls the MAC address back out of the attribute and will\n * place it in the array pointed by by mac_addr. It will return success\n * if provided with a valid pointers.\n **/\ns32 fm10k_tlv_attr_get_mac_vlan(u32 *attr, u8 *mac_addr, u16 *vlan)\n{\n\tDEBUGFUNC(\"fm10k_tlv_attr_get_mac_vlan\");\n\n\t/* verify pointers are not NULL */\n\tif (!mac_addr || !attr)\n\t\treturn FM10K_ERR_PARAM;\n\n\t*(__le32 *)&mac_addr[0] = FM10K_CPU_TO_LE32(attr[1]);\n\t*(__le16 *)&mac_addr[4] = FM10K_CPU_TO_LE16((u16)(attr[2]));\n\t*vlan = (u16)(attr[2] >> 16);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_attr_put_bool - Add header indicating value \"true\"\n * @msg: Pointer to message block\n * @attr_id: Attribute ID\n *\n * This function will simply add an attribute header, the fact\n * that the header is here means the attribute value is true, else\n * it is false. The function will return success if provided with a\n * valid pointers.\n **/\ns32 fm10k_tlv_attr_put_bool(u32 *msg, u16 attr_id)\n{\n\tDEBUGFUNC(\"fm10k_tlv_attr_put_bool\");\n\n\t/* verify pointers are not NULL */\n\tif (!msg)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* record attribute header */\n\tmsg[FM10K_TLV_DWORD_LEN(*msg)] = attr_id;\n\n\t/* add header length to length */\n\t*msg += FM10K_TLV_HDR_LEN << FM10K_TLV_LEN_SHIFT;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_attr_put_value - Store integer value attribute in message\n * @msg: Pointer to message block\n * @attr_id: Attribute ID\n * @value: Value to be written\n * @len: Size of value\n *\n * This function will place an integer value of up to 8 bytes in size\n * in a message attribute. The function will return success provided\n * that msg is a valid pointer, and len is 1, 2, 4, or 8.\n **/\ns32 fm10k_tlv_attr_put_value(u32 *msg, u16 attr_id, s64 value, u32 len)\n{\n\tu32 *attr;\n\n\tDEBUGFUNC(\"fm10k_tlv_attr_put_value\");\n\n\t/* verify non-null msg and len is 1, 2, 4, or 8 */\n\tif (!msg || !len || len > 8 || (len & (len - 1)))\n\t\treturn FM10K_ERR_PARAM;\n\n\tattr = &msg[FM10K_TLV_DWORD_LEN(*msg)];\n\n\tif (len < 4) {\n\t\tattr[1] = (u32)value & ((0x1ul << (8 * len)) - 1);\n\t} else {\n\t\tattr[1] = (u32)value;\n\t\tif (len > 4)\n\t\t\tattr[2] = (u32)(value >> 32);\n\t}\n\n\t/* record attribute header, update message length */\n\tlen <<= FM10K_TLV_LEN_SHIFT;\n\tattr[0] = len | attr_id;\n\n\t/* add header length to length */\n\tlen += FM10K_TLV_HDR_LEN << FM10K_TLV_LEN_SHIFT;\n\t*msg += FM10K_TLV_LEN_ALIGN(len);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_attr_get_value - Get integer value stored in attribute\n * @attr: Pointer to attribute\n * @value: Pointer to destination buffer\n * @len: Size of value\n *\n * This function will place an integer value of up to 8 bytes in size\n * in the offset pointed to by value. The function will return success\n * provided that pointers are valid and the len value matches the\n * attribute length.\n **/\ns32 fm10k_tlv_attr_get_value(u32 *attr, void *value, u32 len)\n{\n\tDEBUGFUNC(\"fm10k_tlv_attr_get_value\");\n\n\t/* verify pointers are not NULL */\n\tif (!attr || !value)\n\t\treturn FM10K_ERR_PARAM;\n\n\tif ((*attr >> FM10K_TLV_LEN_SHIFT) != len)\n\t\treturn FM10K_ERR_PARAM;\n\n\tif (len == 8)\n\t\t*(u64 *)value = ((u64)attr[2] << 32) | attr[1];\n\telse if (len == 4)\n\t\t*(u32 *)value = attr[1];\n\telse if (len == 2)\n\t\t*(u16 *)value = (u16)attr[1];\n\telse\n\t\t*(u8 *)value = (u8)attr[1];\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_attr_put_le_struct - Store little endian structure in message\n * @msg: Pointer to message block\n * @attr_id: Attribute ID\n * @le_struct: Pointer to structure to be written\n * @len: Size of le_struct\n *\n * This function will place a little endian structure value in a message\n * attribute. The function will return success provided that all pointers\n * are valid and length is a non-zero multiple of 4.\n **/\ns32 fm10k_tlv_attr_put_le_struct(u32 *msg, u16 attr_id,\n\t\t\t\t const void *le_struct, u32 len)\n{\n\tconst __le32 *le32_ptr = (const __le32 *)le_struct;\n\tu32 *attr;\n\tu32 i;\n\n\tDEBUGFUNC(\"fm10k_tlv_attr_put_le_struct\");\n\n\t/* verify non-null msg and len is in 32 bit words */\n\tif (!msg || !len || (len % 4))\n\t\treturn FM10K_ERR_PARAM;\n\n\tattr = &msg[FM10K_TLV_DWORD_LEN(*msg)];\n\n\t/* copy le32 structure into host byte order at 32b boundaries */\n\tfor (i = 0; i < (len / 4); i++)\n\t\tattr[i + 1] = FM10K_LE32_TO_CPU(le32_ptr[i]);\n\n\t/* record attribute header, update message length */\n\tlen <<= FM10K_TLV_LEN_SHIFT;\n\tattr[0] = len | attr_id;\n\n\t/* add header length to length */\n\tlen += FM10K_TLV_HDR_LEN << FM10K_TLV_LEN_SHIFT;\n\t*msg += FM10K_TLV_LEN_ALIGN(len);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_attr_get_le_struct - Get little endian struct form attribute\n * @attr: Pointer to attribute\n * @le_struct: Pointer to structure to be written\n * @len: Size of structure\n *\n * This function will place a little endian structure in the buffer\n * pointed to by le_struct. The function will return success\n * provided that pointers are valid and the len value matches the\n * attribute length.\n **/\ns32 fm10k_tlv_attr_get_le_struct(u32 *attr, void *le_struct, u32 len)\n{\n\t__le32 *le32_ptr = (__le32 *)le_struct;\n\tu32 i;\n\n\tDEBUGFUNC(\"fm10k_tlv_attr_get_le_struct\");\n\n\t/* verify pointers are not NULL */\n\tif (!le_struct || !attr)\n\t\treturn FM10K_ERR_PARAM;\n\n\tif ((*attr >> FM10K_TLV_LEN_SHIFT) != len)\n\t\treturn FM10K_ERR_PARAM;\n\n\tattr++;\n\n\tfor (i = 0; len; i++, len -= 4)\n\t\tle32_ptr[i] = FM10K_CPU_TO_LE32(attr[i]);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_attr_nest_start - Start a set of nested attributes\n * @msg: Pointer to message block\n * @attr_id: Attribute ID\n *\n * This function will mark off a new nested region for encapsulating\n * a given set of attributes. The idea is if you wish to place a secondary\n * structure within the message this mechanism allows for that. The\n * function will return NULL on failure, and a pointer to the start\n * of the nested attributes on success.\n **/\nu32 *fm10k_tlv_attr_nest_start(u32 *msg, u16 attr_id)\n{\n\tu32 *attr;\n\n\tDEBUGFUNC(\"fm10k_tlv_attr_nest_start\");\n\n\t/* verify pointer is not NULL */\n\tif (!msg)\n\t\treturn NULL;\n\n\tattr = &msg[FM10K_TLV_DWORD_LEN(*msg)];\n\n\tattr[0] = attr_id;\n\n\t/* return pointer to nest header */\n\treturn attr;\n}\n\n/**\n * fm10k_tlv_attr_nest_start - Start a set of nested attributes\n * @msg: Pointer to message block\n *\n * This function closes off an existing set of nested attributes. The\n * message pointer should be pointing to the parent of the nest. So in\n * the case of a nest within the nest this would be the outer nest pointer.\n * This function will return success provided all pointers are valid.\n **/\ns32 fm10k_tlv_attr_nest_stop(u32 *msg)\n{\n\tu32 *attr;\n\tu32 len;\n\n\tDEBUGFUNC(\"fm10k_tlv_attr_nest_stop\");\n\n\t/* verify pointer is not NULL */\n\tif (!msg)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* locate the nested header and retrieve its length */\n\tattr = &msg[FM10K_TLV_DWORD_LEN(*msg)];\n\tlen = (attr[0] >> FM10K_TLV_LEN_SHIFT) << FM10K_TLV_LEN_SHIFT;\n\n\t/* only include nest if data was added to it */\n\tif (len) {\n\t\tlen += FM10K_TLV_HDR_LEN << FM10K_TLV_LEN_SHIFT;\n\t\t*msg += len;\n\t}\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_attr_validate - Validate attribute metadata\n * @attr: Pointer to attribute\n * @tlv_attr: Type and length info for attribute\n *\n * This function does some basic validation of the input TLV. It\n * verifies the length, and in the case of null terminated strings\n * it verifies that the last byte is null. The function will\n * return FM10K_ERR_PARAM if any attribute is malformed, otherwise\n * it returns 0.\n **/\nSTATIC s32 fm10k_tlv_attr_validate(u32 *attr,\n\t\t\t\t const struct fm10k_tlv_attr *tlv_attr)\n{\n\tu32 attr_id = *attr & FM10K_TLV_ID_MASK;\n\tu16 len = *attr >> FM10K_TLV_LEN_SHIFT;\n\n\tDEBUGFUNC(\"fm10k_tlv_attr_validate\");\n\n\t/* verify this is an attribute and not a message */\n\tif (*attr & (FM10K_TLV_FLAGS_MSG << FM10K_TLV_FLAGS_SHIFT))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* search through the list of attributes to find a matching ID */\n\twhile (tlv_attr->id < attr_id)\n\t\ttlv_attr++;\n\n\t/* if didn't find a match then we should exit */\n\tif (tlv_attr->id != attr_id)\n\t\treturn FM10K_NOT_IMPLEMENTED;\n\n\t/* move to start of attribute data */\n\tattr++;\n\n\tswitch (tlv_attr->type) {\n\tcase FM10K_TLV_NULL_STRING:\n\t\tif (!len ||\n\t\t (attr[(len - 1) / 4] & (0xFF << (8 * ((len - 1) % 4)))))\n\t\t\treturn FM10K_ERR_PARAM;\n\t\tif (len > tlv_attr->len)\n\t\t\treturn FM10K_ERR_PARAM;\n\t\tbreak;\n\tcase FM10K_TLV_MAC_ADDR:\n\t\tif (len != ETH_ALEN)\n\t\t\treturn FM10K_ERR_PARAM;\n\t\tbreak;\n\tcase FM10K_TLV_BOOL:\n\t\tif (len)\n\t\t\treturn FM10K_ERR_PARAM;\n\t\tbreak;\n\tcase FM10K_TLV_UNSIGNED:\n\tcase FM10K_TLV_SIGNED:\n\t\tif (len != tlv_attr->len)\n\t\t\treturn FM10K_ERR_PARAM;\n\t\tbreak;\n\tcase FM10K_TLV_LE_STRUCT:\n\t\t/* struct must be 4 byte aligned */\n\t\tif ((len % 4) || len != tlv_attr->len)\n\t\t\treturn FM10K_ERR_PARAM;\n\t\tbreak;\n\tcase FM10K_TLV_NESTED:\n\t\t/* nested attributes must be 4 byte aligned */\n\t\tif (len % 4)\n\t\t\treturn FM10K_ERR_PARAM;\n\t\tbreak;\n\tdefault:\n\t\t/* attribute id is mapped to bad value */\n\t\treturn FM10K_ERR_PARAM;\n\t}\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_attr_parse - Parses stream of attribute data\n * @attr: Pointer to attribute list\n * @results: Pointer array to store pointers to attributes\n * @tlv_attr: Type and length info for attributes\n *\n * This function validates a stream of attributes and parses them\n * up into an array of pointers stored in results. The function will\n * return FM10K_ERR_PARAM on any input or message error,\n * FM10K_NOT_IMPLEMENTED for any attribute that is outside of the array\n * and 0 on success.\n **/\ns32 fm10k_tlv_attr_parse(u32 *attr, u32 **results,\n\t\t\t const struct fm10k_tlv_attr *tlv_attr)\n{\n\tu32 i, attr_id, offset = 0;\n\ts32 err = 0;\n\tu16 len;\n\n\tDEBUGFUNC(\"fm10k_tlv_attr_parse\");\n\n\t/* verify pointers are not NULL */\n\tif (!attr || !results)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* initialize results to NULL */\n\tfor (i = 0; i < FM10K_TLV_RESULTS_MAX; i++)\n\t\tresults[i] = NULL;\n\n\t/* pull length from the message header */\n\tlen = *attr >> FM10K_TLV_LEN_SHIFT;\n\n\t/* no attributes to parse if there is no length */\n\tif (!len)\n\t\treturn FM10K_SUCCESS;\n\n\t/* no attributes to parse, just raw data, message becomes attribute */\n\tif (!tlv_attr) {\n\t\tresults[0] = attr;\n\t\treturn FM10K_SUCCESS;\n\t}\n\n\t/* move to start of attribute data */\n\tattr++;\n\n\t/* run through list parsing all attributes */\n\twhile (offset < len) {\n\t\tattr_id = *attr & FM10K_TLV_ID_MASK;\n\n\t\tif (attr_id < FM10K_TLV_RESULTS_MAX)\n\t\t\terr = fm10k_tlv_attr_validate(attr, tlv_attr);\n\t\telse\n\t\t\terr = FM10K_NOT_IMPLEMENTED;\n\n\t\tif (err < 0)\n\t\t\treturn err;\n\t\tif (!err)\n\t\t\tresults[attr_id] = attr;\n\n\t\t/* update offset */\n\t\toffset += FM10K_TLV_DWORD_LEN(*attr) * 4;\n\n\t\t/* move to next attribute */\n\t\tattr = &attr[FM10K_TLV_DWORD_LEN(*attr)];\n\t}\n\n\t/* we should find ourselves at the end of the list */\n\tif (offset != len)\n\t\treturn FM10K_ERR_PARAM;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_tlv_msg_parse - Parses message header and calls function handler\n * @hw: Pointer to hardware structure\n * @msg: Pointer to message\n * @mbx: Pointer to mailbox information structure\n * @func: Function array containing list of message handling functions\n *\n * This function should be the first function called upon receiving a\n * message. The handler will identify the message type and call the correct\n * handler for the given message. It will return the value from the function\n * call on a recognized message type, otherwise it will return\n * FM10K_NOT_IMPLEMENTED on an unrecognized type.\n **/\ns32 fm10k_tlv_msg_parse(struct fm10k_hw *hw, u32 *msg,\n\t\t\tstruct fm10k_mbx_info *mbx,\n\t\t\tconst struct fm10k_msg_data *data)\n{\n\tu32 *results[FM10K_TLV_RESULTS_MAX];\n\tu32 msg_id;\n\ts32 err;\n\n\tDEBUGFUNC(\"fm10k_tlv_msg_parse\");\n\n\t/* verify pointer is not NULL */\n\tif (!msg || !data)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* verify this is a message and not an attribute */\n\tif (!(*msg & (FM10K_TLV_FLAGS_MSG << FM10K_TLV_FLAGS_SHIFT)))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* grab message ID */\n\tmsg_id = *msg & FM10K_TLV_ID_MASK;\n\n\twhile (data->id < msg_id)\n\t\tdata++;\n\n\t/* if we didn't find it then pass it up as an error */\n\tif (data->id != msg_id) {\n\t\twhile (data->id != FM10K_TLV_ERROR)\n\t\t\tdata++;\n\t}\n\n\t/* parse the attributes into the results list */\n\terr = fm10k_tlv_attr_parse(msg, results, data->attr);\n\tif (err < 0)\n\t\treturn err;\n\n\treturn data->func(hw, results, mbx);\n}\n\n/**\n * fm10k_tlv_msg_error - Default handler for unrecognized TLV message IDs\n * @hw: Pointer to hardware structure\n * @results: Pointer array to message, results[0] is pointer to message\n * @mbx: Unused mailbox pointer\n *\n * This function is a default handler for unrecognized messages. At a\n * a minimum it just indicates that the message requested was\n * unimplemented.\n **/\ns32 fm10k_tlv_msg_error(struct fm10k_hw *hw, u32 **results,\n\t\t\tstruct fm10k_mbx_info *mbx)\n{\n\tUNREFERENCED_3PARAMETER(hw, results, mbx);\n\tDEBUGOUT1(\"Unknown message ID %u\\n\", **results & FM10K_TLV_ID_MASK);\n\treturn FM10K_NOT_IMPLEMENTED;\n}\n\nSTATIC const unsigned char test_str[] =\t\"fm10k\";\nSTATIC const unsigned char test_mac[ETH_ALEN] = { 0x12, 0x34, 0x56,\n\t\t\t\t\t\t 0x78, 0x9a, 0xbc };\nSTATIC const u16 test_vlan = 0x0FED;\nSTATIC const u64 test_u64 = 0xfedcba9876543210ull;\nSTATIC const u32 test_u32 = 0x87654321;\nSTATIC const u16 test_u16 = 0x8765;\nSTATIC const u8 test_u8 = 0x87;\nSTATIC const s64 test_s64 = -0x123456789abcdef0ll;\nSTATIC const s32 test_s32 = -0x1235678;\nSTATIC const s16 test_s16 = -0x1234;\nSTATIC const s8 test_s8 = -0x12;\nSTATIC const __le32 test_le[2] = { FM10K_CPU_TO_LE32(0x12345678),\n\t\t\t\t FM10K_CPU_TO_LE32(0x9abcdef0)};\n\n/* The message below is meant to be used as a test message to demonstrate\n * how to use the TLV interface and to test the types. Normally this code\n * be compiled out by stripping the code wrapped in FM10K_TLV_TEST_MSG\n */\nconst struct fm10k_tlv_attr fm10k_tlv_msg_test_attr[] = {\n\tFM10K_TLV_ATTR_NULL_STRING(FM10K_TEST_MSG_STRING, 80),\n\tFM10K_TLV_ATTR_MAC_ADDR(FM10K_TEST_MSG_MAC_ADDR),\n\tFM10K_TLV_ATTR_U8(FM10K_TEST_MSG_U8),\n\tFM10K_TLV_ATTR_U16(FM10K_TEST_MSG_U16),\n\tFM10K_TLV_ATTR_U32(FM10K_TEST_MSG_U32),\n\tFM10K_TLV_ATTR_U64(FM10K_TEST_MSG_U64),\n\tFM10K_TLV_ATTR_S8(FM10K_TEST_MSG_S8),\n\tFM10K_TLV_ATTR_S16(FM10K_TEST_MSG_S16),\n\tFM10K_TLV_ATTR_S32(FM10K_TEST_MSG_S32),\n\tFM10K_TLV_ATTR_S64(FM10K_TEST_MSG_S64),\n\tFM10K_TLV_ATTR_LE_STRUCT(FM10K_TEST_MSG_LE_STRUCT, 8),\n\tFM10K_TLV_ATTR_NESTED(FM10K_TEST_MSG_NESTED),\n\tFM10K_TLV_ATTR_S32(FM10K_TEST_MSG_RESULT),\n\tFM10K_TLV_ATTR_LAST\n};\n\n/**\n * fm10k_tlv_msg_test_generate_data - Stuff message with data\n * @msg: Pointer to message\n * @attr_flags: List of flags indicating what attributes to add\n *\n * This function is meant to load a message buffer with attribute data\n **/\nSTATIC void fm10k_tlv_msg_test_generate_data(u32 *msg, u32 attr_flags)\n{\n\tDEBUGFUNC(\"fm10k_tlv_msg_test_generate_data\");\n\n\tif (attr_flags & (1 << FM10K_TEST_MSG_STRING))\n\t\tfm10k_tlv_attr_put_null_string(msg, FM10K_TEST_MSG_STRING,\n\t\t\t\t\t test_str);\n\tif (attr_flags & (1 << FM10K_TEST_MSG_MAC_ADDR))\n\t\tfm10k_tlv_attr_put_mac_vlan(msg, FM10K_TEST_MSG_MAC_ADDR,\n\t\t\t\t\t test_mac, test_vlan);\n\tif (attr_flags & (1 << FM10K_TEST_MSG_U8))\n\t\tfm10k_tlv_attr_put_u8(msg, FM10K_TEST_MSG_U8, test_u8);\n\tif (attr_flags & (1 << FM10K_TEST_MSG_U16))\n\t\tfm10k_tlv_attr_put_u16(msg, FM10K_TEST_MSG_U16, test_u16);\n\tif (attr_flags & (1 << FM10K_TEST_MSG_U32))\n\t\tfm10k_tlv_attr_put_u32(msg, FM10K_TEST_MSG_U32, test_u32);\n\tif (attr_flags & (1 << FM10K_TEST_MSG_U64))\n\t\tfm10k_tlv_attr_put_u64(msg, FM10K_TEST_MSG_U64, test_u64);\n\tif (attr_flags & (1 << FM10K_TEST_MSG_S8))\n\t\tfm10k_tlv_attr_put_s8(msg, FM10K_TEST_MSG_S8, test_s8);\n\tif (attr_flags & (1 << FM10K_TEST_MSG_S16))\n\t\tfm10k_tlv_attr_put_s16(msg, FM10K_TEST_MSG_S16, test_s16);\n\tif (attr_flags & (1 << FM10K_TEST_MSG_S32))\n\t\tfm10k_tlv_attr_put_s32(msg, FM10K_TEST_MSG_S32, test_s32);\n\tif (attr_flags & (1 << FM10K_TEST_MSG_S64))\n\t\tfm10k_tlv_attr_put_s64(msg, FM10K_TEST_MSG_S64, test_s64);\n\tif (attr_flags & (1 << FM10K_TEST_MSG_LE_STRUCT))\n\t\tfm10k_tlv_attr_put_le_struct(msg, FM10K_TEST_MSG_LE_STRUCT,\n\t\t\t\t\t test_le, 8);\n}\n\n/**\n * fm10k_tlv_msg_test_create - Create a test message testing all attributes\n * @msg: Pointer to message\n * @attr_flags: List of flags indicating what attributes to add\n *\n * This function is meant to load a message buffer with all attribute types\n * including a nested attribute.\n **/\nvoid fm10k_tlv_msg_test_create(u32 *msg, u32 attr_flags)\n{\n\tu32 *nest = NULL;\n\n\tDEBUGFUNC(\"fm10k_tlv_msg_test_create\");\n\n\tfm10k_tlv_msg_init(msg, FM10K_TLV_MSG_ID_TEST);\n\n\tfm10k_tlv_msg_test_generate_data(msg, attr_flags);\n\n\t/* check for nested attributes */\n\tattr_flags >>= FM10K_TEST_MSG_NESTED;\n\n\tif (attr_flags) {\n\t\tnest = fm10k_tlv_attr_nest_start(msg, FM10K_TEST_MSG_NESTED);\n\n\t\tfm10k_tlv_msg_test_generate_data(nest, attr_flags);\n\n\t\tfm10k_tlv_attr_nest_stop(msg);\n\t}\n}\n\n/**\n * fm10k_tlv_msg_test - Validate all results on test message receive\n * @hw: Pointer to hardware structure\n * @results: Pointer array to attributes in the message\n * @mbx: Pointer to mailbox information structure\n *\n * This function does a check to verify all attributes match what the test\n * message placed in the message buffer. It is the default handler\n * for TLV test messages.\n **/\ns32 fm10k_tlv_msg_test(struct fm10k_hw *hw, u32 **results,\n\t\t struct fm10k_mbx_info *mbx)\n{\n\tu32 *nest_results[FM10K_TLV_RESULTS_MAX];\n\tunsigned char result_str[80];\n\tunsigned char result_mac[ETH_ALEN];\n\ts32 err = FM10K_SUCCESS;\n\t__le32 result_le[2];\n\tu16 result_vlan;\n\tu64 result_u64;\n\tu32 result_u32;\n\tu16 result_u16;\n\tu8 result_u8;\n\ts64 result_s64;\n\ts32 result_s32;\n\ts16 result_s16;\n\ts8 result_s8;\n\tu32 reply[3];\n\n\tDEBUGFUNC(\"fm10k_tlv_msg_test\");\n\n\t/* retrieve results of a previous test */\n\tif (!!results[FM10K_TEST_MSG_RESULT])\n\t\treturn fm10k_tlv_attr_get_s32(results[FM10K_TEST_MSG_RESULT],\n\t\t\t\t\t &mbx->test_result);\n\nparse_nested:\n\tif (!!results[FM10K_TEST_MSG_STRING]) {\n\t\terr = fm10k_tlv_attr_get_null_string(\n\t\t\t\t\tresults[FM10K_TEST_MSG_STRING],\n\t\t\t\t\tresult_str);\n\t\tif (!err && memcmp(test_str, result_str, sizeof(test_str)))\n\t\t\terr = FM10K_ERR_INVALID_VALUE;\n\t\tif (err)\n\t\t\tgoto report_result;\n\t}\n\tif (!!results[FM10K_TEST_MSG_MAC_ADDR]) {\n\t\terr = fm10k_tlv_attr_get_mac_vlan(\n\t\t\t\t\tresults[FM10K_TEST_MSG_MAC_ADDR],\n\t\t\t\t\tresult_mac, &result_vlan);\n\t\tif (!err && memcmp(test_mac, result_mac, ETH_ALEN))\n\t\t\terr = FM10K_ERR_INVALID_VALUE;\n\t\tif (!err && test_vlan != result_vlan)\n\t\t\terr = FM10K_ERR_INVALID_VALUE;\n\t\tif (err)\n\t\t\tgoto report_result;\n\t}\n\tif (!!results[FM10K_TEST_MSG_U8]) {\n\t\terr = fm10k_tlv_attr_get_u8(results[FM10K_TEST_MSG_U8],\n\t\t\t\t\t &result_u8);\n\t\tif (!err && test_u8 != result_u8)\n\t\t\terr = FM10K_ERR_INVALID_VALUE;\n\t\tif (err)\n\t\t\tgoto report_result;\n\t}\n\tif (!!results[FM10K_TEST_MSG_U16]) {\n\t\terr = fm10k_tlv_attr_get_u16(results[FM10K_TEST_MSG_U16],\n\t\t\t\t\t &result_u16);\n\t\tif (!err && test_u16 != result_u16)\n\t\t\terr = FM10K_ERR_INVALID_VALUE;\n\t\tif (err)\n\t\t\tgoto report_result;\n\t}\n\tif (!!results[FM10K_TEST_MSG_U32]) {\n\t\terr = fm10k_tlv_attr_get_u32(results[FM10K_TEST_MSG_U32],\n\t\t\t\t\t &result_u32);\n\t\tif (!err && test_u32 != result_u32)\n\t\t\terr = FM10K_ERR_INVALID_VALUE;\n\t\tif (err)\n\t\t\tgoto report_result;\n\t}\n\tif (!!results[FM10K_TEST_MSG_U64]) {\n\t\terr = fm10k_tlv_attr_get_u64(results[FM10K_TEST_MSG_U64],\n\t\t\t\t\t &result_u64);\n\t\tif (!err && test_u64 != result_u64)\n\t\t\terr = FM10K_ERR_INVALID_VALUE;\n\t\tif (err)\n\t\t\tgoto report_result;\n\t}\n\tif (!!results[FM10K_TEST_MSG_S8]) {\n\t\terr = fm10k_tlv_attr_get_s8(results[FM10K_TEST_MSG_S8],\n\t\t\t\t\t &result_s8);\n\t\tif (!err && test_s8 != result_s8)\n\t\t\terr = FM10K_ERR_INVALID_VALUE;\n\t\tif (err)\n\t\t\tgoto report_result;\n\t}\n\tif (!!results[FM10K_TEST_MSG_S16]) {\n\t\terr = fm10k_tlv_attr_get_s16(results[FM10K_TEST_MSG_S16],\n\t\t\t\t\t &result_s16);\n\t\tif (!err && test_s16 != result_s16)\n\t\t\terr = FM10K_ERR_INVALID_VALUE;\n\t\tif (err)\n\t\t\tgoto report_result;\n\t}\n\tif (!!results[FM10K_TEST_MSG_S32]) {\n\t\terr = fm10k_tlv_attr_get_s32(results[FM10K_TEST_MSG_S32],\n\t\t\t\t\t &result_s32);\n\t\tif (!err && test_s32 != result_s32)\n\t\t\terr = FM10K_ERR_INVALID_VALUE;\n\t\tif (err)\n\t\t\tgoto report_result;\n\t}\n\tif (!!results[FM10K_TEST_MSG_S64]) {\n\t\terr = fm10k_tlv_attr_get_s64(results[FM10K_TEST_MSG_S64],\n\t\t\t\t\t &result_s64);\n\t\tif (!err && test_s64 != result_s64)\n\t\t\terr = FM10K_ERR_INVALID_VALUE;\n\t\tif (err)\n\t\t\tgoto report_result;\n\t}\n\tif (!!results[FM10K_TEST_MSG_LE_STRUCT]) {\n\t\terr = fm10k_tlv_attr_get_le_struct(\n\t\t\t\t\tresults[FM10K_TEST_MSG_LE_STRUCT],\n\t\t\t\t\tresult_le,\n\t\t\t\t\tsizeof(result_le));\n\t\tif (!err && memcmp(test_le, result_le, sizeof(test_le)))\n\t\t\terr = FM10K_ERR_INVALID_VALUE;\n\t\tif (err)\n\t\t\tgoto report_result;\n\t}\n\n\tif (!!results[FM10K_TEST_MSG_NESTED]) {\n\t\t/* clear any pointers */\n\t\tmemset(nest_results, 0, sizeof(nest_results));\n\n\t\t/* parse the nested attributes into the nest results list */\n\t\terr = fm10k_tlv_attr_parse(results[FM10K_TEST_MSG_NESTED],\n\t\t\t\t\t nest_results,\n\t\t\t\t\t fm10k_tlv_msg_test_attr);\n\t\tif (err)\n\t\t\tgoto report_result;\n\n\t\t/* loop back through to the start */\n\t\tresults = nest_results;\n\t\tgoto parse_nested;\n\t}\n\nreport_result:\n\t/* generate reply with test result */\n\tfm10k_tlv_msg_init(reply, FM10K_TLV_MSG_ID_TEST);\n\tfm10k_tlv_attr_put_s32(reply, FM10K_TEST_MSG_RESULT, err);\n\n\t/* load onto outgoing mailbox */\n\treturn mbx->ops.enqueue_tx(hw, mbx, reply);\n}\n" }, { "path": "drivers/net/fm10k/base/fm10k_tlv.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _FM10K_TLV_H_\n#define _FM10K_TLV_H_\n\n/* forward declaration */\nstruct fm10k_msg_data;\n\n#include \"fm10k_type.h\"\n\n/* Message / Argument header format\n * 3\t\t\t 2\t\t 1\t\t\t 0\n * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0\n * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n * |\t Length\t | Flags |\t Type / ID\t\t |\n * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n *\n * The message header format described here is used for messages that are\n * passed between the PF and the VF. To allow for messages larger then\n * mailbox size we will provide a message with the above header and it\n * will be segmented and transported to the mailbox to the other side where\n * it is reassembled. It contains the following fields:\n * Len: Length of the message in bytes excluding the message header\n * Flags: TBD\n * Rule: These will be the message/argument types we pass\n */\n/* message data header */\n#define FM10K_TLV_ID_SHIFT\t\t0\n#define FM10K_TLV_ID_SIZE\t\t16\n#define FM10K_TLV_ID_MASK\t\t((1u << FM10K_TLV_ID_SIZE) - 1)\n#define FM10K_TLV_FLAGS_SHIFT\t\t16\n#define FM10K_TLV_FLAGS_MSG\t\t0x1\n#define FM10K_TLV_FLAGS_SIZE\t\t4\n#define FM10K_TLV_LEN_SHIFT\t\t20\n#define FM10K_TLV_LEN_SIZE\t\t12\n\n#define FM10K_TLV_HDR_LEN\t\t4ul\n#define FM10K_TLV_LEN_ALIGN_MASK \\\n\t((FM10K_TLV_HDR_LEN - 1) << FM10K_TLV_LEN_SHIFT)\n#define FM10K_TLV_LEN_ALIGN(tlv) \\\n\t(((tlv) + FM10K_TLV_LEN_ALIGN_MASK) & ~FM10K_TLV_LEN_ALIGN_MASK)\n#define FM10K_TLV_DWORD_LEN(tlv) \\\n\t((u16)((FM10K_TLV_LEN_ALIGN(tlv)) >> (FM10K_TLV_LEN_SHIFT + 2)) + 1)\n\n#define FM10K_TLV_RESULTS_MAX\t\t32\n\nenum fm10k_tlv_type {\n\tFM10K_TLV_NULL_STRING,\n\tFM10K_TLV_MAC_ADDR,\n\tFM10K_TLV_BOOL,\n\tFM10K_TLV_UNSIGNED,\n\tFM10K_TLV_SIGNED,\n\tFM10K_TLV_LE_STRUCT,\n\tFM10K_TLV_NESTED,\n\tFM10K_TLV_MAX_TYPE\n};\n\n#define FM10K_TLV_ERROR (~0u)\n\nstruct fm10k_tlv_attr {\n\tunsigned int\t\tid;\n\tenum fm10k_tlv_type\ttype;\n\tu16\t\t\tlen;\n};\n\n#define FM10K_TLV_ATTR_NULL_STRING(id, len) { id, FM10K_TLV_NULL_STRING, len }\n#define FM10K_TLV_ATTR_MAC_ADDR(id)\t { id, FM10K_TLV_MAC_ADDR, 6 }\n#define FM10K_TLV_ATTR_BOOL(id)\t\t { id, FM10K_TLV_BOOL, 0 }\n#define FM10K_TLV_ATTR_U8(id)\t\t { id, FM10K_TLV_UNSIGNED, 1 }\n#define FM10K_TLV_ATTR_U16(id)\t\t { id, FM10K_TLV_UNSIGNED, 2 }\n#define FM10K_TLV_ATTR_U32(id)\t\t { id, FM10K_TLV_UNSIGNED, 4 }\n#define FM10K_TLV_ATTR_U64(id)\t\t { id, FM10K_TLV_UNSIGNED, 8 }\n#define FM10K_TLV_ATTR_S8(id)\t\t { id, FM10K_TLV_SIGNED, 1 }\n#define FM10K_TLV_ATTR_S16(id)\t\t { id, FM10K_TLV_SIGNED, 2 }\n#define FM10K_TLV_ATTR_S32(id)\t\t { id, FM10K_TLV_SIGNED, 4 }\n#define FM10K_TLV_ATTR_S64(id)\t\t { id, FM10K_TLV_SIGNED, 8 }\n#define FM10K_TLV_ATTR_LE_STRUCT(id, len) { id, FM10K_TLV_LE_STRUCT, len }\n#define FM10K_TLV_ATTR_NESTED(id)\t { id, FM10K_TLV_NESTED }\n#define FM10K_TLV_ATTR_LAST\t\t { FM10K_TLV_ERROR }\n\nstruct fm10k_msg_data {\n\tunsigned int\t\t id;\n\tconst struct fm10k_tlv_attr *attr;\n\ts32\t\t\t (*func)(struct fm10k_hw *, u32 **,\n\t\t\t\t\t struct fm10k_mbx_info *);\n};\n\n#define FM10K_MSG_HANDLER(id, attr, func) { id, attr, func }\n\ns32 fm10k_tlv_msg_init(u32 *, u16);\ns32 fm10k_tlv_attr_put_null_string(u32 *, u16, const unsigned char *);\ns32 fm10k_tlv_attr_get_null_string(u32 *, unsigned char *);\ns32 fm10k_tlv_attr_put_mac_vlan(u32 *, u16, const u8 *, u16);\ns32 fm10k_tlv_attr_get_mac_vlan(u32 *, u8 *, u16 *);\ns32 fm10k_tlv_attr_put_bool(u32 *, u16);\ns32 fm10k_tlv_attr_put_value(u32 *, u16, s64, u32);\n#define fm10k_tlv_attr_put_u8(msg, attr_id, val) \\\n\t\tfm10k_tlv_attr_put_value(msg, attr_id, val, 1)\n#define fm10k_tlv_attr_put_u16(msg, attr_id, val) \\\n\t\tfm10k_tlv_attr_put_value(msg, attr_id, val, 2)\n#define fm10k_tlv_attr_put_u32(msg, attr_id, val) \\\n\t\tfm10k_tlv_attr_put_value(msg, attr_id, val, 4)\n#define fm10k_tlv_attr_put_u64(msg, attr_id, val) \\\n\t\tfm10k_tlv_attr_put_value(msg, attr_id, val, 8)\n#define fm10k_tlv_attr_put_s8(msg, attr_id, val) \\\n\t\tfm10k_tlv_attr_put_value(msg, attr_id, val, 1)\n#define fm10k_tlv_attr_put_s16(msg, attr_id, val) \\\n\t\tfm10k_tlv_attr_put_value(msg, attr_id, val, 2)\n#define fm10k_tlv_attr_put_s32(msg, attr_id, val) \\\n\t\tfm10k_tlv_attr_put_value(msg, attr_id, val, 4)\n#define fm10k_tlv_attr_put_s64(msg, attr_id, val) \\\n\t\tfm10k_tlv_attr_put_value(msg, attr_id, val, 8)\ns32 fm10k_tlv_attr_get_value(u32 *, void *, u32);\n#define fm10k_tlv_attr_get_u8(attr, ptr) \\\n\t\tfm10k_tlv_attr_get_value(attr, ptr, sizeof(u8))\n#define fm10k_tlv_attr_get_u16(attr, ptr) \\\n\t\tfm10k_tlv_attr_get_value(attr, ptr, sizeof(u16))\n#define fm10k_tlv_attr_get_u32(attr, ptr) \\\n\t\tfm10k_tlv_attr_get_value(attr, ptr, sizeof(u32))\n#define fm10k_tlv_attr_get_u64(attr, ptr) \\\n\t\tfm10k_tlv_attr_get_value(attr, ptr, sizeof(u64))\n#define fm10k_tlv_attr_get_s8(attr, ptr) \\\n\t\tfm10k_tlv_attr_get_value(attr, ptr, sizeof(s8))\n#define fm10k_tlv_attr_get_s16(attr, ptr) \\\n\t\tfm10k_tlv_attr_get_value(attr, ptr, sizeof(s16))\n#define fm10k_tlv_attr_get_s32(attr, ptr) \\\n\t\tfm10k_tlv_attr_get_value(attr, ptr, sizeof(s32))\n#define fm10k_tlv_attr_get_s64(attr, ptr) \\\n\t\tfm10k_tlv_attr_get_value(attr, ptr, sizeof(s64))\ns32 fm10k_tlv_attr_put_le_struct(u32 *, u16, const void *, u32);\ns32 fm10k_tlv_attr_get_le_struct(u32 *, void *, u32);\nu32 *fm10k_tlv_attr_nest_start(u32 *, u16);\ns32 fm10k_tlv_attr_nest_stop(u32 *);\ns32 fm10k_tlv_attr_parse(u32 *, u32 **, const struct fm10k_tlv_attr *);\ns32 fm10k_tlv_msg_parse(struct fm10k_hw *, u32 *, struct fm10k_mbx_info *,\n\t\t\tconst struct fm10k_msg_data *);\ns32 fm10k_tlv_msg_error(struct fm10k_hw *hw, u32 **results,\n\t\t\tstruct fm10k_mbx_info *);\n\n#define FM10K_TLV_MSG_ID_TEST\t0\n\nenum fm10k_tlv_test_attr_id {\n\tFM10K_TEST_MSG_UNSET,\n\tFM10K_TEST_MSG_STRING,\n\tFM10K_TEST_MSG_MAC_ADDR,\n\tFM10K_TEST_MSG_U8,\n\tFM10K_TEST_MSG_U16,\n\tFM10K_TEST_MSG_U32,\n\tFM10K_TEST_MSG_U64,\n\tFM10K_TEST_MSG_S8,\n\tFM10K_TEST_MSG_S16,\n\tFM10K_TEST_MSG_S32,\n\tFM10K_TEST_MSG_S64,\n\tFM10K_TEST_MSG_LE_STRUCT,\n\tFM10K_TEST_MSG_NESTED,\n\tFM10K_TEST_MSG_RESULT,\n\tFM10K_TEST_MSG_MAX\n};\n\nextern const struct fm10k_tlv_attr fm10k_tlv_msg_test_attr[];\nvoid fm10k_tlv_msg_test_create(u32 *, u32);\ns32 fm10k_tlv_msg_test(struct fm10k_hw *, u32 **, struct fm10k_mbx_info *);\n\n#define FM10K_TLV_MSG_TEST_HANDLER(func) \\\n\tFM10K_MSG_HANDLER(FM10K_TLV_MSG_ID_TEST, fm10k_tlv_msg_test_attr, func)\n#define FM10K_TLV_MSG_ERROR_HANDLER(func) \\\n\tFM10K_MSG_HANDLER(FM10K_TLV_ERROR, NULL, func)\n#endif /* _FM10K_MSG_H_ */\n" }, { "path": "drivers/net/fm10k/base/fm10k_type.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _FM10K_TYPE_H_\n#define _FM10K_TYPE_H_\n\n/* forward declaration */\nstruct fm10k_hw;\n\n#include \"fm10k_osdep.h\"\n#include \"fm10k_mbx.h\"\n\n#define FM10K_INTEL_VENDOR_ID\t\t0x8086\n#define FM10K_DEV_ID_PF\t\t\t0x15A4\n#define FM10K_DEV_ID_VF\t\t\t0x15A5\n\n#define FM10K_MAX_QUEUES\t\t256\n#define FM10K_MAX_QUEUES_PF\t\t128\n#define FM10K_MAX_QUEUES_POOL\t\t16\n\n#define FM10K_48_BIT_MASK\t\t0x0000FFFFFFFFFFFFull\n#define FM10K_STAT_VALID\t\t0x80000000\n\n/* PCI Bus Info */\n#define FM10K_PCIE_LINK_CAP\t\t0x7C\n#define FM10K_PCIE_LINK_STATUS\t\t0x82\n#define FM10K_PCIE_LINK_WIDTH\t\t0x3F0\n#define FM10K_PCIE_LINK_WIDTH_1\t\t0x10\n#define FM10K_PCIE_LINK_WIDTH_2\t\t0x20\n#define FM10K_PCIE_LINK_WIDTH_4\t\t0x40\n#define FM10K_PCIE_LINK_WIDTH_8\t\t0x80\n#define FM10K_PCIE_LINK_SPEED\t\t0xF\n#define FM10K_PCIE_LINK_SPEED_2500\t0x1\n#define FM10K_PCIE_LINK_SPEED_5000\t0x2\n#define FM10K_PCIE_LINK_SPEED_8000\t0x3\n\n/* PCIe payload size */\n#define FM10K_PCIE_DEV_CAP\t\t\t0x74\n#define FM10K_PCIE_DEV_CAP_PAYLOAD\t\t0x07\n#define FM10K_PCIE_DEV_CAP_PAYLOAD_128\t\t0x00\n#define FM10K_PCIE_DEV_CAP_PAYLOAD_256\t\t0x01\n#define FM10K_PCIE_DEV_CAP_PAYLOAD_512\t\t0x02\n#define FM10K_PCIE_DEV_CTRL\t\t\t0x78\n#define FM10K_PCIE_DEV_CTRL_PAYLOAD\t\t0xE0\n#define FM10K_PCIE_DEV_CTRL_PAYLOAD_128\t\t0x00\n#define FM10K_PCIE_DEV_CTRL_PAYLOAD_256\t\t0x20\n#define FM10K_PCIE_DEV_CTRL_PAYLOAD_512\t\t0x40\n\n/* PCIe MSI-X Capability info */\n#define FM10K_PCI_MSIX_MSG_CTRL\t\t\t0xB2\n#define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK\t0x7FF\n#define FM10K_MAX_MSIX_VECTORS\t\t\t256\n#define FM10K_MAX_VECTORS_PF\t\t\t256\n#define FM10K_MAX_VECTORS_POOL\t\t\t32\n\n/* PCIe SR-IOV Info */\n#define FM10K_PCIE_SRIOV_CTRL\t\t\t0x190\n#define FM10K_PCIE_SRIOV_CTRL_VFARI\t\t0x10\n\n#define FM10K_SUCCESS\t\t\t\t0\n#define FM10K_ERR_DEVICE_NOT_SUPPORTED\t\t-1\n#define FM10K_ERR_PARAM\t\t\t\t-2\n#define FM10K_ERR_NO_RESOURCES\t\t\t-3\n#define FM10K_ERR_REQUESTS_PENDING\t\t-4\n#define FM10K_ERR_RESET_REQUESTED\t\t-5\n#define FM10K_ERR_DMA_PENDING\t\t\t-6\n#define FM10K_ERR_RESET_FAILED\t\t\t-7\n#define FM10K_ERR_INVALID_MAC_ADDR\t\t-8\n#define FM10K_ERR_INVALID_VALUE\t\t\t-9\n#define FM10K_NOT_IMPLEMENTED\t\t\t0x7FFFFFFF\n\n#define UNREFERENCED_XPARAMETER\n#define UNREFERENCED_1PARAMETER(_p) (_p)\n#define UNREFERENCED_2PARAMETER(_p, _q)\t do { (_p); (_q); } while (0)\n#define UNREFERENCED_3PARAMETER(_p, _q, _r) do { (_p); (_q); (_r); } while (0)\n\n/* Start of PF registers */\n#define FM10K_CTRL\t\t0x0000\n#define FM10K_CTRL_BAR4_ALLOWED\t\t\t0x00000004\n\n#define FM10K_CTRL_EXT\t\t0x0001\n#define FM10K_CTRL_EXT_NS_DIS\t\t\t0x00000001\n#define FM10K_CTRL_EXT_RO_DIS\t\t\t0x00000002\n#define FM10K_CTRL_EXT_SWITCH_LOOPBACK\t\t0x00000004\n#define FM10K_EXVET\t\t0x0002\n#define FM10K_EXVET_ETHERTYPE_MASK\t\t0x000000FF\n#define FM10K_EXVET_TAG_SIZE_SHIFT\t\t16\n#define FM10K_EXVET_AFTER_VLAN\t\t\t0x00040000\n#define FM10K_GCR\t\t0x0003\n#define FM10K_FACTPS\t\t0x0004\n#define FM10K_GCR_EXT\t\t0x0005\n\n/* Interrupt control registers */\n#define FM10K_EICR\t\t0x0006\n#define FM10K_EICR_PCA_FAULT\t\t\t0x00000001\n#define FM10K_EICR_THI_FAULT\t\t\t0x00000004\n#define FM10K_EICR_FUM_FAULT\t\t\t0x00000020\n#define FM10K_EICR_FAULT_MASK\t\t\t0x0000003F\n#define FM10K_EICR_MAILBOX\t\t\t0x00000040\n#define FM10K_EICR_SWITCHREADY\t\t\t0x00000080\n#define FM10K_EICR_SWITCHNOTREADY\t\t0x00000100\n#define FM10K_EICR_SWITCHINTERRUPT\t\t0x00000200\n#define FM10K_EICR_SRAMERROR\t\t\t0x00000400\n#define FM10K_EICR_VFLR\t\t\t\t0x00000800\n#define FM10K_EICR_MAXHOLDTIME\t\t\t0x00001000\n#define FM10K_EIMR\t\t0x0007\n#define FM10K_EIMR_PCA_FAULT\t\t\t0x00000001\n#define FM10K_EIMR_THI_FAULT\t\t\t0x00000010\n#define FM10K_EIMR_FUM_FAULT\t\t\t0x00000400\n#define FM10K_EIMR_MAILBOX\t\t\t0x00001000\n#define FM10K_EIMR_SWITCHREADY\t\t\t0x00004000\n#define FM10K_EIMR_SWITCHNOTREADY\t\t0x00010000\n#define FM10K_EIMR_SWITCHINTERRUPT\t\t0x00040000\n#define FM10K_EIMR_SRAMERROR\t\t\t0x00100000\n#define FM10K_EIMR_VFLR\t\t\t\t0x00400000\n#define FM10K_EIMR_MAXHOLDTIME\t\t\t0x01000000\n#define FM10K_EIMR_ALL\t\t\t\t0x55555555\n#define FM10K_EIMR_DISABLE(NAME)\t\t((FM10K_EIMR_ ## NAME) << 0)\n#define FM10K_EIMR_ENABLE(NAME)\t\t\t((FM10K_EIMR_ ## NAME) << 1)\n#define FM10K_FAULT_ADDR_LO\t\t0x0\n#define FM10K_FAULT_ADDR_HI\t\t0x1\n#define FM10K_FAULT_SPECINFO\t\t0x2\n#define FM10K_FAULT_FUNC\t\t0x3\n#define FM10K_FAULT_SIZE\t\t0x4\n#define FM10K_FAULT_FUNC_VALID\t\t\t0x00008000\n#define FM10K_FAULT_FUNC_PF\t\t\t0x00004000\n#define FM10K_FAULT_FUNC_VF_MASK\t\t0x00003F00\n#define FM10K_FAULT_FUNC_VF_SHIFT\t\t8\n#define FM10K_FAULT_FUNC_TYPE_MASK\t\t0x000000FF\n\n#define FM10K_PCA_FAULT\t\t0x0008\n#define FM10K_THI_FAULT\t\t0x0010\n#define FM10K_FUM_FAULT\t\t0x001C\n\n/* Rx queue timeout indicator */\n#define FM10K_MAXHOLDQ(_n)\t((_n) + 0x0020)\n\n/* Switch Manager info */\n#define FM10K_SM_AREA(_n)\t((_n) + 0x0028)\n\n/* GLORT mapping registers */\n#define FM10K_DGLORTMAP(_n)\t((_n) + 0x0030)\n#define FM10K_DGLORT_COUNT\t\t\t8\n#define FM10K_DGLORTMAP_MASK_SHIFT\t\t16\n#define FM10K_DGLORTMAP_ANY\t\t\t0x00000000\n#define FM10K_DGLORTMAP_NONE\t\t\t0x0000FFFF\n#define FM10K_DGLORTMAP_ZERO\t\t\t0xFFFF0000\n#define FM10K_DGLORTDEC(_n)\t((_n) + 0x0038)\n#define FM10K_DGLORTDEC_VSILENGTH_SHIFT\t\t4\n#define FM10K_DGLORTDEC_VSIBASE_SHIFT\t\t7\n#define FM10K_DGLORTDEC_PCLENGTH_SHIFT\t\t14\n#define FM10K_DGLORTDEC_QBASE_SHIFT\t\t16\n#define FM10K_DGLORTDEC_RSSLENGTH_SHIFT\t\t24\n#define FM10K_DGLORTDEC_INNERRSS_ENABLE\t\t0x08000000\n#define FM10K_TUNNEL_CFG\t0x0040\n#define FM10K_TUNNEL_CFG_NVGRE_SHIFT\t\t16\n#define FM10K_TUNNEL_CFG_GENEVE\t0x0041\n#define FM10K_SWPRI_MAP(_n)\t((_n) + 0x0050)\n#define FM10K_SWPRI_MAX\t\t16\n#define FM10K_RSSRK(_n, _m)\t(((_n) * 0x10) + (_m) + 0x0800)\n#define FM10K_RSSRK_SIZE\t10\n#define FM10K_RSSRK_ENTRIES_PER_REG\t\t4\n#define FM10K_RETA(_n, _m)\t(((_n) * 0x20) + (_m) + 0x1000)\n#define FM10K_RETA_SIZE\t\t32\n#define FM10K_RETA_ENTRIES_PER_REG\t\t4\n#define FM10K_MAX_RSS_INDICES\t128\n\n/* Rate limiting registers */\n#define FM10K_TC_CREDIT(_n)\t((_n) + 0x2000)\n#define FM10K_TC_CREDIT_CREDIT_MASK\t\t0x001FFFFF\n#define FM10K_TC_MAXCREDIT(_n)\t((_n) + 0x2040)\n#define FM10K_TC_MAXCREDIT_64K\t\t\t0x00010000\n#define FM10K_TC_RATE(_n)\t((_n) + 0x2080)\n#define FM10K_TC_RATE_QUANTA_MASK\t\t0x0000FFFF\n#define FM10K_TC_RATE_INTERVAL_4US_GEN1\t\t0x00020000\n#define FM10K_TC_RATE_INTERVAL_4US_GEN2\t\t0x00040000\n#define FM10K_TC_RATE_INTERVAL_4US_GEN3\t\t0x00080000\n#define FM10K_TC_RATE_STATUS\t0x20C0\n#define FM10K_PAUSE\t\t0x20C2\n\n/* DMA control registers */\n#define FM10K_DMA_CTRL\t\t0x20C3\n#define FM10K_DMA_CTRL_TX_ENABLE\t\t0x00000001\n#define FM10K_DMA_CTRL_TX_HOST_PENDING\t\t0x00000002\n#define FM10K_DMA_CTRL_TX_DATA\t\t\t0x00000004\n#define FM10K_DMA_CTRL_TX_ACTIVE\t\t0x00000008\n#define FM10K_DMA_CTRL_RX_ENABLE\t\t0x00000010\n#define FM10K_DMA_CTRL_RX_HOST_PENDING\t\t0x00000020\n#define FM10K_DMA_CTRL_RX_DATA\t\t\t0x00000040\n#define FM10K_DMA_CTRL_RX_ACTIVE\t\t0x00000080\n#define FM10K_DMA_CTRL_RX_DESC_SIZE\t\t0x00000100\n#define FM10K_DMA_CTRL_MINMSS_SHIFT\t\t9\n#define FM10K_DMA_CTRL_MINMSS_64\t\t0x00008000\n#define FM10K_DMA_CTRL_MAX_HOLD_TIME_SHIFT\t23\n#define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3\t0x04800000\n#define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2\t0x04000000\n#define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1\t0x03800000\n#define FM10K_DMA_CTRL_DATAPATH_RESET\t\t0x20000000\n#define FM10K_DMA_CTRL_MAXNUMOFQ_MASK\t\t0xC0000000\n#define FM10K_DMA_CTRL_32_DESC\t\t\t0x00000000\n#define FM10K_DMA_CTRL_64_DESC\t\t\t0x40000000\n#define FM10K_DMA_CTRL_128_DESC\t\t\t0x80000000\n\n#define FM10K_DMA_CTRL2\t\t0x20C4\n#define FM10K_DMA_CTRL2_TX_FRAME_SPACING_SHIFT\t5\n#define FM10K_DMA_CTRL2_SWITCH_READY\t\t0x00002000\n#define FM10K_DMA_CTRL2_RX_DESC_READ_PRIO_SHIFT\t14\n#define FM10K_DMA_CTRL2_TX_DESC_READ_PRIO_SHIFT\t17\n#define FM10K_DMA_CTRL2_TX_DATA_READ_PRIO_SHIFT\t20\n\n/* TSO flags configuration\n * First packet contains all flags except for fin and psh\n * Middle packet contains only urg and ack\n * Last packet contains urg, ack, fin, and psh\n */\n#define FM10K_TSO_FLAGS_LOW\t\t0x00300FF6\n#define FM10K_TSO_FLAGS_HI\t\t0x00000039\n#define FM10K_DTXTCPFLGL\t0x20C5\n#define FM10K_DTXTCPFLGH\t0x20C6\n\n#define FM10K_TPH_CTRL\t\t0x20C7\n#define FM10K_TPH_CTRL_DISABLE_READ_HINT\t0x00000080\n#define FM10K_MRQC(_n)\t\t((_n) + 0x2100)\n#define FM10K_MRQC_TCP_IPV4\t\t\t0x00000001\n#define FM10K_MRQC_IPV4\t\t\t\t0x00000002\n#define FM10K_MRQC_IPV6\t\t\t\t0x00000010\n#define FM10K_MRQC_TCP_IPV6\t\t\t0x00000020\n#define FM10K_MRQC_UDP_IPV4\t\t\t0x00000040\n#define FM10K_MRQC_UDP_IPV6\t\t\t0x00000080\n\n#define FM10K_TQMAP(_n)\t\t((_n) + 0x2800)\n#define FM10K_TQMAP_TABLE_SIZE\t\t\t2048\n#define FM10K_RQMAP(_n)\t\t((_n) + 0x3000)\n#define FM10K_RQMAP_TABLE_SIZE\t\t\t2048\n\n/* Hardware Statistics */\n#define FM10K_STATS_TIMEOUT\t\t0x3800\n#define FM10K_STATS_UR\t\t\t0x3801\n#define FM10K_STATS_CA\t\t\t0x3802\n#define FM10K_STATS_UM\t\t\t0x3803\n#define FM10K_STATS_XEC\t\t\t0x3804\n#define FM10K_STATS_VLAN_DROP\t\t0x3805\n#define FM10K_STATS_LOOPBACK_DROP\t0x3806\n#define FM10K_STATS_NODESC_DROP\t\t0x3807\n\n/* Timesync registers */\n#define FM10K_RRTIME_CFG\t0x3808\n#define FM10K_RRTIME_LIMIT(_n)\t((_n) + 0x380C)\n#define FM10K_RRTIME_COUNT(_n)\t((_n) + 0x3810)\n#define FM10K_SYSTIME\t\t0x3814\n#define FM10K_SYSTIME0\t\t0x3816\n#define FM10K_SYSTIME_CFG\t0x3818\n#define FM10K_SYSTIME_CFG_STEP_MASK\t\t0x0000000F\n\n/* PCIe state registers */\n#define FM10K_PFVFBME(_n)\t((_n) + 0x381A)\n#define FM10K_PHYADDR\t\t0x381C\n\n/* Rx ring registers */\n#define FM10K_RDBAL(_n)\t\t((0x40 * (_n)) + 0x4000)\n#define FM10K_RDBAH(_n)\t\t((0x40 * (_n)) + 0x4001)\n#define FM10K_RDLEN(_n)\t\t((0x40 * (_n)) + 0x4002)\n#define FM10K_TPH_RXCTRL(_n)\t((0x40 * (_n)) + 0x4003)\n#define FM10K_TPH_RXCTRL_DESC_TPHEN\t\t0x00000020\n#define FM10K_TPH_RXCTRL_HDR_TPHEN\t\t0x00000040\n#define FM10K_TPH_RXCTRL_DATA_TPHEN\t\t0x00000080\n#define FM10K_TPH_RXCTRL_DESC_RROEN\t\t0x00000200\n#define FM10K_TPH_RXCTRL_DATA_WROEN\t\t0x00002000\n#define FM10K_TPH_RXCTRL_HDR_WROEN\t\t0x00008000\n#define FM10K_RDH(_n)\t\t((0x40 * (_n)) + 0x4004)\n#define FM10K_RDT(_n)\t\t((0x40 * (_n)) + 0x4005)\n#define FM10K_RXQCTL(_n)\t((0x40 * (_n)) + 0x4006)\n#define FM10K_RXQCTL_ENABLE\t\t\t0x00000001\n#define FM10K_RXQCTL_PF\t\t\t\t0x000000FC\n#define FM10K_RXQCTL_VF_SHIFT\t\t\t2\n#define FM10K_RXQCTL_VF\t\t\t\t0x00000100\n#define FM10K_RXQCTL_ID_MASK\t(FM10K_RXQCTL_PF | FM10K_RXQCTL_VF)\n#define FM10K_RXDCTL(_n)\t((0x40 * (_n)) + 0x4007)\n#define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY\t0x00000001\n#define FM10K_RXDCTL_WRITE_BACK_IMM\t\t0x00000100\n#define FM10K_RXDCTL_DROP_ON_EMPTY\t\t0x00000200\n#define FM10K_RXINT(_n)\t\t((0x40 * (_n)) + 0x4008)\n#define FM10K_RXINT_TIMER_SHIFT\t\t\t8\n#define FM10K_SRRCTL(_n)\t((0x40 * (_n)) + 0x4009)\n#define FM10K_SRRCTL_BSIZEPKT_SHIFT\t\t8 /* shift _right_ */\n#define FM10K_SRRCTL_BSIZEHDR_SHIFT\t\t2 /* shift _left_ */\n#define FM10K_SRRCTL_BSIZEHDR_MASK\t\t0x00003F00\n#define FM10K_SRRCTL_DESCTYPE_HDR_SPLIT\t\t0x00004000\n#define FM10K_SRRCTL_DESCTYPE_SIZE_SPLIT\t0x00008000\n#define FM10K_SRRCTL_PSRTYPE_INNER_TCPHDR\t0x00010000\n#define FM10K_SRRCTL_PSRTYPE_INNER_UDPHDR\t0x00020000\n#define FM10K_SRRCTL_PSRTYPE_INNER_IPV4HDR\t0x00040000\n#define FM10K_SRRCTL_PSRTYPE_INNER_IPV6HDR\t0x00080000\n#define FM10K_SRRCTL_PSRTYPE_INNER_L2HDR\t0x00100000\n#define FM10K_SRRCTL_PSRTYPE_ENCAPHDR\t\t0x00200000\n#define FM10K_SRRCTL_PSRTYPE_TCPHDR\t\t0x00400000\n#define FM10K_SRRCTL_PSRTYPE_UDPHDR\t\t0x00800000\n#define FM10K_SRRCTL_PSRTYPE_IPV4HDR\t\t0x01000000\n#define FM10K_SRRCTL_PSRTYPE_IPV6HDR\t\t0x02000000\n#define FM10K_SRRCTL_PSRTYPE_L2HDR\t\t0x04000000\n#define FM10K_SRRCTL_LOOPBACK_SUPPRESS\t\t0x40000000\n#define FM10K_SRRCTL_BUFFER_CHAINING_EN\t\t0x80000000\n\n/* Rx Statistics */\n#define FM10K_QPRC(_n)\t\t((0x40 * (_n)) + 0x400A)\n#define FM10K_QPRDC(_n)\t\t((0x40 * (_n)) + 0x400B)\n#define FM10K_QBRC_L(_n)\t((0x40 * (_n)) + 0x400C)\n#define FM10K_QBRC_H(_n)\t((0x40 * (_n)) + 0x400D)\n\n/* Rx GLORT register */\n#define FM10K_RX_SGLORT(_n)\t\t((0x40 * (_n)) + 0x400E)\n\n/* Tx ring registers */\n#define FM10K_TDBAL(_n)\t\t((0x40 * (_n)) + 0x8000)\n#define FM10K_TDBAH(_n)\t\t((0x40 * (_n)) + 0x8001)\n#define FM10K_TDLEN(_n)\t\t((0x40 * (_n)) + 0x8002)\n#define FM10K_TPH_TXCTRL(_n)\t((0x40 * (_n)) + 0x8003)\n#define FM10K_TPH_TXCTRL_DESC_TPHEN\t\t0x00000020\n#define FM10K_TPH_TXCTRL_DESC_RROEN\t\t0x00000200\n#define FM10K_TPH_TXCTRL_DESC_WROEN\t\t0x00000800\n#define FM10K_TPH_TXCTRL_DATA_RROEN\t\t0x00002000\n#define FM10K_TDH(_n)\t\t((0x40 * (_n)) + 0x8004)\n#define FM10K_TDT(_n)\t\t((0x40 * (_n)) + 0x8005)\n#define FM10K_TXDCTL(_n)\t((0x40 * (_n)) + 0x8006)\n#define FM10K_TXDCTL_ENABLE\t\t\t0x00004000\n#define FM10K_TXDCTL_MAX_TIME_SHIFT\t\t16\n#define FM10K_TXDCTL_PUSH_DESC\t\t\t0x10000000\n#define FM10K_TXQCTL(_n)\t((0x40 * (_n)) + 0x8007)\n#define FM10K_TXQCTL_PF\t\t\t\t0x0000003F\n#define FM10K_TXQCTL_VF\t\t\t\t0x00000040\n#define FM10K_TXQCTL_ID_MASK\t(FM10K_TXQCTL_PF | FM10K_TXQCTL_VF)\n#define FM10K_TXQCTL_PC_SHIFT\t\t\t7\n#define FM10K_TXQCTL_PC_MASK\t\t\t0x00000380\n#define FM10K_TXQCTL_TC_SHIFT\t\t\t10\n#define FM10K_TXQCTL_TC_MASK\t\t\t0x0000FC00\n#define FM10K_TXQCTL_VID_SHIFT\t\t\t16\n#define FM10K_TXQCTL_VID_MASK\t\t\t0x0FFF0000\n#define FM10K_TXQCTL_UNLIMITED_BW\t\t0x10000000\n#define FM10K_TXQCTL_PUSHMODEDIS\t\t0x20000000\n#define FM10K_TXINT(_n)\t\t((0x40 * (_n)) + 0x8008)\n#define FM10K_TXINT_TIMER_SHIFT\t\t\t8\n\n/* Tx Statistics */\n#define FM10K_QPTC(_n)\t\t((0x40 * (_n)) + 0x8009)\n#define FM10K_QBTC_L(_n)\t((0x40 * (_n)) + 0x800A)\n#define FM10K_QBTC_H(_n)\t((0x40 * (_n)) + 0x800B)\n\n/* Tx Push registers */\n#define FM10K_TQDLOC(_n)\t((0x40 * (_n)) + 0x800C)\n#define FM10K_TQDLOC_BASE_32_DESC\t\t0x08\n#define FM10K_TQDLOC_BASE_64_DESC\t\t0x10\n#define FM10K_TQDLOC_BASE_128_DESC\t\t0x20\n#define FM10K_TQDLOC_SIZE_32_DESC\t\t0x00050000\n#define FM10K_TQDLOC_SIZE_64_DESC\t\t0x00060000\n#define FM10K_TQDLOC_SIZE_128_DESC\t\t0x00070000\n#define FM10K_TQDLOC_SIZE_SHIFT\t\t\t16\n#define FM10K_TX_DCACHE(_n, _m)\t((0x400 * (_n)) + (0x4 * (_m)) + 0x40000)\n\n/* Tx GLORT registers */\n#define FM10K_TX_SGLORT(_n)\t((0x40 * (_n)) + 0x800D)\n#define FM10K_PFVTCTL(_n)\t((0x40 * (_n)) + 0x800E)\n#define FM10K_PFVTCTL_FTAG_DESC_ENABLE\t\t0x00000001\n\n/* Interrupt moderation and control registers */\n#define FM10K_PBACL(_n)\t\t((_n) + 0x10000)\n#define FM10K_INT_MAP(_n)\t((_n) + 0x10080)\n#define FM10K_INT_MAP_TIMER0\t\t\t0x00000000\n#define FM10K_INT_MAP_TIMER1\t\t\t0x00000100\n#define FM10K_INT_MAP_IMMEDIATE\t\t\t0x00000200\n#define FM10K_INT_MAP_DISABLE\t\t\t0x00000300\n#define FM10K_MSIX_VECTOR_ADDR_LO(_n)\t((0x4 * (_n)) + 0x11000)\n#define FM10K_MSIX_VECTOR_ADDR_HI(_n)\t((0x4 * (_n)) + 0x11001)\n#define FM10K_MSIX_VECTOR_DATA(_n)\t((0x4 * (_n)) + 0x11002)\n#define FM10K_MSIX_VECTOR_MASK(_n)\t((0x4 * (_n)) + 0x11003)\n#define FM10K_INT_CTRL\t\t0x12000\n#define FM10K_INT_CTRL_ENABLEMODERATOR\t\t0x00000400\n#define FM10K_ITR(_n)\t\t((_n) + 0x12400)\n#define FM10K_ITR_INTERVAL1_SHIFT\t\t12\n#define FM10K_ITR_TIMER0_EXPIRED\t\t0x01000000\n#define FM10K_ITR_TIMER1_EXPIRED\t\t0x02000000\n#define FM10K_ITR_PENDING0\t\t\t0x04000000\n#define FM10K_ITR_PENDING1\t\t\t0x08000000\n#define FM10K_ITR_PENDING2\t\t\t0x10000000\n#define FM10K_ITR_AUTOMASK\t\t\t0x20000000\n#define FM10K_ITR_MASK_SET\t\t\t0x40000000\n#define FM10K_ITR_MASK_CLEAR\t\t\t0x80000000\n#define FM10K_ITR2(_n)\t\t((0x2 * (_n)) + 0x12800)\n#define FM10K_ITR2_LP(_n)\t((0x2 * (_n)) + 0x12801)\n#define FM10K_ITR_REG_COUNT\t\t\t768\n#define FM10K_ITR_REG_COUNT_PF\t\t\t256\n\n/* Switch manager interrupt registers */\n#define FM10K_IP\t\t0x13000\n#define FM10K_IP_HOT_RESET\t\t\t0x00000001\n#define FM10K_IP_DEVICE_STATE_CHANGE\t\t0x00000002\n#define FM10K_IP_MAILBOX\t\t\t0x00000004\n#define FM10K_IP_VPD_REQUEST\t\t\t0x00000008\n#define FM10K_IP_SRAMERROR\t\t\t0x00000010\n#define FM10K_IP_PFLR\t\t\t\t0x00000020\n#define FM10K_IP_DATAPATHRESET\t\t\t0x00000040\n#define FM10K_IP_OUTOFRESET\t\t\t0x00000080\n#define FM10K_IP_NOTINRESET\t\t\t0x00000100\n#define FM10K_IP_TIMEOUT\t\t\t0x00000200\n#define FM10K_IP_VFLR\t\t\t\t0x00000400\n#define FM10K_IM\t\t0x13001\n#define FM10K_IB\t\t0x13002\n#define FM10K_SRAM_IP\t\t0x13003\n#define FM10K_SRAM_IM\t\t0x13004\n\n/* VLAN registers */\n#define FM10K_VLAN_TABLE(_n, _m)\t((0x80 * (_n)) + (_m) + 0x14000)\n#define FM10K_VLAN_TABLE_SIZE\t\t\t128\n\n/* VLAN specific message offsets */\n#define FM10K_VLAN_TABLE_VID_MAX\t\t4096\n#define FM10K_VLAN_TABLE_VSI_MAX\t\t64\n#define FM10K_VLAN_LENGTH_SHIFT\t\t\t16\n#define FM10K_VLAN_CLEAR\t\t\t(1 << 15)\n#define FM10K_VLAN_ALL \\\n\t((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT)\n\n/* VF FLR event notification registers */\n#define FM10K_PFVFLRE(_n)\t((0x1 * (_n)) + 0x18844)\n#define FM10K_PFVFLREC(_n)\t((0x1 * (_n)) + 0x18846)\n\n/* Defines for size of uncacheable and write-combining memories */\n#define FM10K_UC_ADDR_START\t0x000000\t/* start of standard regs */\n#define FM10K_WC_ADDR_START\t0x100000\t/* start of Tx Desc Cache */\n#define FM10K_DBI_ADDR_START\t0x200000\t/* start of debug registers */\n#define FM10K_UC_ADDR_SIZE\t(FM10K_WC_ADDR_START - FM10K_UC_ADDR_START)\n#define FM10K_WC_ADDR_SIZE\t(FM10K_DBI_ADDR_START - FM10K_WC_ADDR_START)\n\n/* Define timeouts for resets and disables */\n#define FM10K_QUEUE_DISABLE_TIMEOUT\t\t100\n#define FM10K_RESET_TIMEOUT\t\t\t150\n\n/* Maximum supported combined inner and outer header length for encapsulation */\n#define FM10K_TUNNEL_HEADER_LENGTH\t184\n\n/* VF registers */\n#define FM10K_VFCTRL\t\t0x00000\n#define FM10K_VFCTRL_RST\t\t\t0x00000008\n#define FM10K_VFINT_MAP\t\t0x00030\n#define FM10K_VFSYSTIME\t\t0x00040\n#define FM10K_VFITR(_n)\t\t((_n) + 0x00060)\n#define FM10K_VFPBACL(_n)\t((_n) + 0x00008)\n\n/* Registers contained in BAR 4 for Switch management */\n#define FM10K_SW_SYSTIME_CFG\t0x0224C\n#define FM10K_SW_SYSTIME_CFG_STEP_SHIFT\t\t4\n#define FM10K_SW_SYSTIME_CFG_ADJUST_MASK\t0xFF000000\n#define FM10K_SW_SYSTIME_ADJUST\t0x0224D\n#define FM10K_SW_SYSTIME_ADJUST_MASK\t\t0x3FFFFFFF\n#define FM10K_SW_SYSTIME_ADJUST_DIR_NEGATIVE\t0x80000000\n#define FM10K_SW_SYSTIME_PULSE(_n)\t((_n) + 0x02252)\n\n#ifndef ETH_ALEN\n#define ETH_ALEN\t6\n#endif /* ETH_ALEN */\n\n\n\n\nenum fm10k_int_source {\n\tfm10k_int_Mailbox\t= 0,\n\tfm10k_int_PCIeFault\t= 1,\n\tfm10k_int_SwitchUpDown\t= 2,\n\tfm10k_int_SwitchEvent\t= 3,\n\tfm10k_int_SRAM\t\t= 4,\n\tfm10k_int_VFLR\t\t= 5,\n\tfm10k_int_MaxHoldTime\t= 6,\n\tfm10k_int_sources_max_pf\n};\n\n/* PCIe bus speeds */\nenum fm10k_bus_speed {\n\tfm10k_bus_speed_unknown\t= 0,\n\tfm10k_bus_speed_2500\t= 2500,\n\tfm10k_bus_speed_5000\t= 5000,\n\tfm10k_bus_speed_8000\t= 8000,\n\tfm10k_bus_speed_reserved\n};\n\n/* PCIe bus widths */\nenum fm10k_bus_width {\n\tfm10k_bus_width_unknown\t= 0,\n\tfm10k_bus_width_pcie_x1\t= 1,\n\tfm10k_bus_width_pcie_x2\t= 2,\n\tfm10k_bus_width_pcie_x4\t= 4,\n\tfm10k_bus_width_pcie_x8\t= 8,\n\tfm10k_bus_width_reserved\n};\n\n/* PCIe payload sizes */\nenum fm10k_bus_payload {\n\tfm10k_bus_payload_unknown = 0,\n\tfm10k_bus_payload_128\t = 1,\n\tfm10k_bus_payload_256\t = 2,\n\tfm10k_bus_payload_512\t = 3,\n\tfm10k_bus_payload_reserved\n};\n\n/* Bus parameters */\nstruct fm10k_bus_info {\n\tenum fm10k_bus_speed speed;\n\tenum fm10k_bus_width width;\n\tenum fm10k_bus_payload payload;\n};\n\n/* Statistics related declarations */\nstruct fm10k_hw_stat {\n\tu64 count;\n\tu32 base_l;\n\tu32 base_h;\n};\n\nstruct fm10k_hw_stats_q {\n\tstruct fm10k_hw_stat tx_bytes;\n\tstruct fm10k_hw_stat tx_packets;\n#define tx_stats_idx\ttx_packets.base_h\n\tstruct fm10k_hw_stat rx_bytes;\n\tstruct fm10k_hw_stat rx_packets;\n#define rx_stats_idx\trx_packets.base_h\n\tstruct fm10k_hw_stat rx_drops;\n};\n\nstruct fm10k_hw_stats {\n\tstruct fm10k_hw_stat\ttimeout;\n#define stats_idx\ttimeout.base_h\n\tstruct fm10k_hw_stat\tur;\n\tstruct fm10k_hw_stat\tca;\n\tstruct fm10k_hw_stat\tum;\n\tstruct fm10k_hw_stat\txec;\n\tstruct fm10k_hw_stat\tvlan_drop;\n\tstruct fm10k_hw_stat\tloopback_drop;\n\tstruct fm10k_hw_stat\tnodesc_drop;\n\tstruct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF];\n};\n\n/* Establish DGLORT feature priority */\nenum fm10k_dglortdec_idx {\n\tfm10k_dglort_default\t= 0,\n\tfm10k_dglort_vf_rsvd0\t= 1,\n\tfm10k_dglort_vf_rss\t= 2,\n\tfm10k_dglort_pf_rsvd0\t= 3,\n\tfm10k_dglort_pf_queue\t= 4,\n\tfm10k_dglort_pf_vsi\t= 5,\n\tfm10k_dglort_pf_rsvd1\t= 6,\n\tfm10k_dglort_pf_rss\t= 7\n};\n\nstruct fm10k_dglort_cfg {\n\tu16 glort;\t/* GLORT base */\n\tu16 queue_b;\t/* Base value for queue */\n\tu8 vsi_b;\t/* Base value for VSI */\n\tu8 idx;\t/* index of DGLORTDEC entry */\n\tu8 rss_l;\t/* RSS indices */\n\tu8 pc_l;\t/* Priority Class indices */\n\tu8 vsi_l;\t/* Number of bits from GLORT used to determine VSI */\n\tu8 queue_l;\t/* Number of bits from GLORT used to determine queue */\n\tu8 shared_l;\t/* Ignored bits from GLORT resulting in shared VSI */\n\tu8 inner_rss;\t/* Boolean value if inner header is used for RSS */\n};\n\nenum fm10k_pca_fault {\n\tPCA_NO_FAULT,\n\tPCA_UNMAPPED_ADDR,\n\tPCA_BAD_QACCESS_PF,\n\tPCA_BAD_QACCESS_VF,\n\tPCA_MALICIOUS_REQ,\n\tPCA_POISONED_TLP,\n\tPCA_TLP_ABORT,\n\t__PCA_MAX\n};\n\nenum fm10k_thi_fault {\n\tTHI_NO_FAULT,\n\tTHI_MAL_DIS_Q_FAULT,\n\t__THI_MAX\n};\n\nenum fm10k_fum_fault {\n\tFUM_NO_FAULT,\n\tFUM_UNMAPPED_ADDR,\n\tFUM_POISONED_TLP,\n\tFUM_BAD_VF_QACCESS,\n\tFUM_ADD_DECODE_ERR,\n\tFUM_RO_ERROR,\n\tFUM_QPRC_CRC_ERROR,\n\tFUM_CSR_TIMEOUT,\n\tFUM_INVALID_TYPE,\n\tFUM_INVALID_LENGTH,\n\tFUM_INVALID_BE,\n\tFUM_INVALID_ALIGN,\n\t__FUM_MAX\n};\n\nstruct fm10k_fault {\n\tu64 address;\t/* Address at the time fault was detected */\n\tu32 specinfo;\t/* Extra info on this fault (fault dependent) */\n\tu8 type;\t/* Fault value dependent on subunit */\n\tu8 func;\t/* Function number of the fault */\n};\n\nstruct fm10k_mac_ops {\n\t/* basic bring-up and tear-down */\n\ts32 (*reset_hw)(struct fm10k_hw *);\n\ts32 (*init_hw)(struct fm10k_hw *);\n\ts32 (*start_hw)(struct fm10k_hw *);\n\ts32 (*stop_hw)(struct fm10k_hw *);\n\ts32 (*get_bus_info)(struct fm10k_hw *);\n\ts32 (*get_host_state)(struct fm10k_hw *, bool *);\n\tbool (*is_slot_appropriate)(struct fm10k_hw *);\n\ts32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool);\n\ts32 (*read_mac_addr)(struct fm10k_hw *);\n\ts32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *,\n\t\t\t u16, bool, u8);\n\ts32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool);\n\ts32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8);\n\tvoid (*update_int_moderator)(struct fm10k_hw *);\n\ts32 (*update_lport_state)(struct fm10k_hw *, u16, u16, bool);\n\tvoid (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);\n\tvoid (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);\n\ts32 (*configure_dglort_map)(struct fm10k_hw *,\n\t\t\t\t struct fm10k_dglort_cfg *);\n\tvoid (*set_dma_mask)(struct fm10k_hw *, u64);\n\ts32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *);\n\tvoid (*request_lport_map)(struct fm10k_hw *);\n\ts32 (*adjust_systime)(struct fm10k_hw *, s32 ppb);\n\tu64 (*read_systime)(struct fm10k_hw *);\n\ts32 (*request_tx_timestamp_mode)(struct fm10k_hw *, u16, u8);\n};\n\nenum fm10k_mac_type {\n\tfm10k_mac_unknown = 0,\n\tfm10k_mac_pf,\n\tfm10k_mac_vf,\n\tfm10k_num_macs\n};\n\nstruct fm10k_mac_info {\n\tstruct fm10k_mac_ops ops;\n\tenum fm10k_mac_type type;\n\tu8 addr[ETH_ALEN];\n\tu8 perm_addr[ETH_ALEN];\n\tu16 default_vid;\n\tu16 max_msix_vectors;\n\tu16 max_queues;\n\tbool vlan_override;\n\tbool get_host_state;\n\tbool tx_ready;\n\tu32 dglort_map;\n};\n\nstruct fm10k_swapi_table_info {\n\tu32 used;\n\tu32 avail;\n};\n\nstruct fm10k_swapi_info {\n\tu32 status;\n\tstruct fm10k_swapi_table_info mac;\n\tstruct fm10k_swapi_table_info nexthop;\n\tstruct fm10k_swapi_table_info ffu;\n};\n\nenum fm10k_xcast_modes {\n\tFM10K_XCAST_MODE_ALLMULTI\t= 0,\n\tFM10K_XCAST_MODE_MULTI\t\t= 1,\n\tFM10K_XCAST_MODE_PROMISC\t= 2,\n\tFM10K_XCAST_MODE_NONE\t\t= 3,\n\tFM10K_XCAST_MODE_DISABLE\t= 4\n};\n\nenum fm10k_timestamp_modes {\n\tFM10K_TIMESTAMP_MODE_NONE\t= 0,\n\tFM10K_TIMESTAMP_MODE_PEP_TO_PEP\t= 1,\n\tFM10K_TIMESTAMP_MODE_PEP_TO_ANY\t= 2,\n};\n\n#define FM10K_VF_TC_MAX\t\t100000\t/* 100,000 Mb/s aka 100Gb/s */\n#define FM10K_VF_TC_MIN\t\t1\t/* 1 Mb/s is the slowest rate */\n\nstruct fm10k_vf_info {\n\t/* mbx must be first field in struct unless all default IOV message\n\t * handlers are redone as the assumption is that vf_info starts\n\t * at the same offset as the mailbox\n\t */\n\tstruct fm10k_mbx_info\tmbx;\t\t/* PF side of VF mailbox */\n\tint\t\t\trate;\t\t/* Tx BW cap as defined by OS */\n\tu16\t\t\tglort;\t\t/* resource tag for this VF */\n\tu16\t\t\tsw_vid;\t\t/* Switch API assigned VLAN */\n\tu16\t\t\tpf_vid;\t\t/* PF assigned Default VLAN */\n\tu8\t\t\tmac[ETH_ALEN];\t/* PF Default MAC address */\n\tu8\t\t\tvsi;\t\t/* VSI identifier */\n\tu8\t\t\tvf_idx;\t\t/* which VF this is */\n\tu8\t\t\tvf_flags;\t/* flags indicating what modes\n\t\t\t\t\t\t * are supported for the port\n\t\t\t\t\t\t */\n};\n\n#define FM10K_VF_FLAG_ALLMULTI_CAPABLE\t((u8)1 << FM10K_XCAST_MODE_ALLMULTI)\n#define FM10K_VF_FLAG_MULTI_CAPABLE\t((u8)1 << FM10K_XCAST_MODE_MULTI)\n#define FM10K_VF_FLAG_PROMISC_CAPABLE\t((u8)1 << FM10K_XCAST_MODE_PROMISC)\n#define FM10K_VF_FLAG_NONE_CAPABLE\t((u8)1 << FM10K_XCAST_MODE_NONE)\n#define FM10K_VF_FLAG_CAPABLE(vf_info)\t((vf_info)->vf_flags & (u8)0xF)\n#define FM10K_VF_FLAG_ENABLED(vf_info)\t((vf_info)->vf_flags >> 4)\n#define FM10K_VF_FLAG_SET_MODE(mode)\t((u8)0x10 << (mode))\n#define FM10K_VF_FLAG_ENABLED_MODE_SHIFT\t4\n#define FM10K_VF_FLAG_SET_MODE_MASK\t((u8)0xF0)\n#define FM10K_VF_FLAG_SET_MODE_NONE \\\n\tFM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE)\n#define FM10K_VF_FLAG_MULTI_ENABLED \\\n\t(FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \\\n\t FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \\\n\t FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC))\n\nstruct fm10k_iov_ops {\n\t/* IOV related bring-up and tear-down */\n\ts32 (*assign_resources)(struct fm10k_hw *, u16, u16);\n\ts32 (*configure_tc)(struct fm10k_hw *, u16, int);\n\ts32 (*assign_int_moderator)(struct fm10k_hw *, u16);\n\ts32 (*assign_default_mac_vlan)(struct fm10k_hw *,\n\t\t\t\t struct fm10k_vf_info *);\n\ts32 (*reset_resources)(struct fm10k_hw *,\n\t\t\t struct fm10k_vf_info *);\n\ts32 (*set_lport)(struct fm10k_hw *, struct fm10k_vf_info *, u16, u8);\n\tvoid (*reset_lport)(struct fm10k_hw *, struct fm10k_vf_info *);\n\tvoid (*update_stats)(struct fm10k_hw *, struct fm10k_hw_stats_q *, u16);\n\ts32 (*report_timestamp)(struct fm10k_hw *, struct fm10k_vf_info *, u64);\n};\n\nstruct fm10k_iov_info {\n\tstruct fm10k_iov_ops ops;\n\tu16 total_vfs;\n\tu16 num_vfs;\n\tu16 num_pools;\n};\n\nstruct fm10k_hw {\n\tu32 *hw_addr;\n\tu32 *sw_addr;\n\tvoid *back;\n\tstruct fm10k_mac_info mac;\n\tstruct fm10k_bus_info bus;\n\tstruct fm10k_bus_info bus_caps;\n\tstruct fm10k_iov_info iov;\n\tstruct fm10k_mbx_info mbx;\n\tstruct fm10k_swapi_info swapi;\n\tu16 device_id;\n\tu16 vendor_id;\n\tu16 subsystem_device_id;\n\tu16 subsystem_vendor_id;\n\tu8 revision_id;\n};\n\n/* Number of Transmit and Receive Descriptors must be a multiple of 8 */\n#define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE\t8\n#define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE\t8\n\n/* Transmit Descriptor */\nstruct fm10k_tx_desc {\n\t__le64 buffer_addr;\t/* Address of the descriptor's data buffer */\n\t__le16 buflen;\t\t/* Length of data to be DMAed */\n\t__le16 vlan;\t\t/* VLAN_ID and VPRI to be inserted in FTAG */\n\t__le16 mss;\t\t/* MSS for segmentation offload */\n\tu8 hdrlen;\t\t/* Header size for segmentation offload */\n\tu8 flags;\t\t/* Status and offload request flags */\n};\n\n/* Transmit Descriptor Cache Structure */\nstruct fm10k_tx_desc_cache {\n\tstruct fm10k_tx_desc tx_desc[256];\n};\n\n#define FM10K_TXD_FLAG_INT\t0x01\n#define FM10K_TXD_FLAG_TIME\t0x02\n#define FM10K_TXD_FLAG_CSUM\t0x04\n#define FM10K_TXD_FLAG_CSUM2\t0x08\n#define FM10K_TXD_FLAG_FTAG\t0x10\n#define FM10K_TXD_FLAG_RS\t0x20\n#define FM10K_TXD_FLAG_LAST\t0x40\n#define FM10K_TXD_FLAG_DONE\t0x80\n\n#define FM10K_TXD_VLAN_PRI_SHIFT\t12\n\n/* These macros are meant to enable optimal placement of the RS and INT\n * bits. It will point us to the last descriptor in the cache for either the\n * start of the packet, or the end of the packet. If the index is actually\n * at the start of the FIFO it will point to the offset for the last index\n * in the FIFO to prevent an unnecessary write.\n */\n#define FM10K_TXD_WB_FIFO_SIZE\t4\n#define FM10K_TXD_WB_IDX(idx) \\\n\t(((idx) - 1) | (FM10K_TXD_WB_FIFO_SIZE - 1))\n\n/* Receive Descriptor - 32B */\nunion fm10k_rx_desc {\n\tstruct {\n\t\t__le64 pkt_addr; /* Packet buffer address */\n\t\t__le64 hdr_addr; /* Header buffer address */\n\t\t__le64 reserved; /* Empty space, RSS hash */\n\t\t__le64 timestamp;\n\t} q; /* Read, Writeback, 64b quad-words */\n\tstruct {\n\t\t__le32 data; /* RSS and header data */\n\t\t__le32 rss; /* RSS Hash */\n\t\t__le32 staterr;\n\t\t__le32 vlan_len;\n\t\t__le32 glort; /* sglort/dglort */\n\t} d; /* Writeback, 32b double-words */\n\tstruct {\n\t\t__le16 pkt_info; /* RSS, Pkt type */\n\t\t__le16 hdr_info; /* Splithdr, hdrlen, xC */\n\t\t__le16 rss_lower;\n\t\t__le16 rss_upper;\n\t\t__le16 status; /* status/error */\n\t\t__le16 csum_err; /* checksum or extended error value */\n\t\t__le16 length; /* Packet length */\n\t\t__le16 vlan; /* VLAN tag */\n\t\t__le16 dglort;\n\t\t__le16 sglort;\n\t} w; /* Writeback, 16b words */\n};\n\n#define FM10K_RXD_RSSTYPE_MASK\t\t0x000F\nenum fm10k_rdesc_rss_type {\n\tFM10K_RSSTYPE_NONE\t= 0x0,\n\tFM10K_RSSTYPE_IPV4_TCP\t= 0x1,\n\tFM10K_RSSTYPE_IPV4\t= 0x2,\n\tFM10K_RSSTYPE_IPV6_TCP\t= 0x3,\n\t/* Reserved 0x4 */\n\tFM10K_RSSTYPE_IPV6\t= 0x5,\n\t/* Reserved 0x6 */\n\tFM10K_RSSTYPE_IPV4_UDP\t= 0x7,\n\tFM10K_RSSTYPE_IPV6_UDP\t= 0x8\n\t/* Reserved 0x9 - 0xF */\n};\n\n#define FM10K_RXD_PKTTYPE_MASK\t\t0x03F0\n#define FM10K_RXD_PKTTYPE_MASK_L3\t0x0070\n#define FM10K_RXD_PKTTYPE_MASK_L4\t0x0380\n#define FM10K_RXD_PKTTYPE_SHIFT\t\t4\n#define FM10K_RXD_PKTTYPE_INNER_MASK_L3\t0x1C00\n#define FM10K_RXD_PKTTYPE_INNER_MASK_L4\t0xE000\n#define FM10K_RXD_PKTTYPE_INNER_SHIFT\t10\nenum fm10k_rdesc_pkt_type {\n\t/* L3 type */\n\tFM10K_PKTTYPE_OTHER\t= 0x00,\n\tFM10K_PKTTYPE_IPV4\t= 0x01,\n\tFM10K_PKTTYPE_IPV4_EX\t= 0x02,\n\tFM10K_PKTTYPE_IPV6\t= 0x03,\n\tFM10K_PKTTYPE_IPV6_EX\t= 0x04,\n\n\t/* L4 type */\n\tFM10K_PKTTYPE_TCP\t= 0x08,\n\tFM10K_PKTTYPE_UDP\t= 0x10,\n\tFM10K_PKTTYPE_GRE\t= 0x18,\n\tFM10K_PKTTYPE_VXLAN\t= 0x20,\n\tFM10K_PKTTYPE_NVGRE\t= 0x28,\n\tFM10K_PKTTYPE_GENEVE\t= 0x30\n};\n\n#define FM10K_RXD_HDR_INFO_XC_MASK\t0x0006\nenum fm10k_rxdesc_xc {\n\tFM10K_XC_UNICAST\t= 0x0,\n\tFM10K_XC_MULTICAST\t= 0x4,\n\tFM10K_XC_BROADCAST\t= 0x6\n};\n\n#define FM10K_RXD_HDR_INFO_LEN_SHIFT\t5\n#define FM10K_RXD_HDR_INFO_SPH\t\t0x8000\n\n#define FM10K_RXD_STATUS_DD\t\t0x0001 /* Descriptor done */\n#define FM10K_RXD_STATUS_EOP\t\t0x0002 /* End of packet */\n#define FM10K_RXD_STATUS_VEXT\t\t0x0004 /* A VLAN tag is present */\n#define FM10K_RXD_STATUS_IPCS\t\t0x0008 /* Indicates IPv4 csum */\n#define FM10K_RXD_STATUS_L4CS\t\t0x0010 /* Indicates an L4 csum */\n#define FM10K_RXD_STATUS_IPCS2\t\t0x0020 /* Inner header IPv4 csum */\n#define FM10K_RXD_STATUS_L4CS2\t\t0x0040 /* Inner header L4 csum */\n#define FM10K_RXD_STATUS_IPFRAG_MASK\t0x0180 /* Fragment mask */\n#define FM10K_RXD_STATUS_IPFRAG_CSUM\t0x0100 /* Fragment w/ CSUM field */\n#define FM10K_RXD_STATUS_VEXT2\t\t0x0200 /* A custom tag is present */\n#define FM10K_RXD_STATUS_HBO\t\t0x0400 /* header buffer overrun */\n#define FM10K_RXD_STATUS_L4E2\t\t0x0800 /* Inner header L4 csum err */\n#define FM10K_RXD_STATUS_IPE2\t\t0x1000 /* Inner header IPv4 csum err */\n#define FM10K_RXD_STATUS_RXE\t\t0x2000 /* Generic Rx error */\n#define FM10K_RXD_STATUS_L4E\t\t0x4000 /* L4 csum error */\n#define FM10K_RXD_STATUS_IPE\t\t0x8000 /* IPv4 csum error */\n\n#define FM10K_RXD_ERR_SWITCH_ERROR\t0x0001 /* Switch found bad packet */\n#define FM10K_RXD_ERR_NO_DESCRIPTOR\t0x0002 /* No descriptor available */\n#define FM10K_RXD_ERR_PP_ERROR\t\t0x0004 /* RAM error during processing */\n#define FM10K_RXD_ERR_SWITCH_READY\t0x0008 /* Link transition mid-packet */\n#define FM10K_RXD_ERR_TOO_BIG\t\t0x0010 /* Pkt too big for single buf */\n\n#define FM10K_RXD_VLAN_ID_MASK\t\t0x0FFF\n#define FM10K_RXD_VLAN_PRI_SHIFT\tFM10K_TXD_VLAN_PRI_SHIFT\n\nstruct fm10k_ftag {\n\t__be16 swpri_type_user;\n\t__be16 vlan;\n\t__be16 sglort;\n\t__be16 dglort;\n};\n\n#endif /* _FM10K_TYPE_H */\n" }, { "path": "drivers/net/fm10k/base/fm10k_vf.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"fm10k_vf.h\"\n\n/**\n * fm10k_stop_hw_vf - Stop Tx/Rx units\n * @hw: pointer to hardware structure\n *\n **/\nSTATIC s32 fm10k_stop_hw_vf(struct fm10k_hw *hw)\n{\n\tu8 *perm_addr = hw->mac.perm_addr;\n\tu32 bal = 0, bah = 0;\n\ts32 err;\n\tu16 i;\n\n\tDEBUGFUNC(\"fm10k_stop_hw_vf\");\n\n\t/* we need to disable the queues before taking further steps */\n\terr = fm10k_stop_hw_generic(hw);\n\tif (err)\n\t\treturn err;\n\n\t/* If permanent address is set then we need to restore it */\n\tif (FM10K_IS_VALID_ETHER_ADDR(perm_addr)) {\n\t\tbal = (((u32)perm_addr[3]) << 24) |\n\t\t (((u32)perm_addr[4]) << 16) |\n\t\t (((u32)perm_addr[5]) << 8);\n\t\tbah = (((u32)0xFF)\t << 24) |\n\t\t (((u32)perm_addr[0]) << 16) |\n\t\t (((u32)perm_addr[1]) << 8) |\n\t\t ((u32)perm_addr[2]);\n\t}\n\n\t/* The queues have already been disabled so we just need to\n\t * update their base address registers\n\t */\n\tfor (i = 0; i < hw->mac.max_queues; i++) {\n\t\tFM10K_WRITE_REG(hw, FM10K_TDBAL(i), bal);\n\t\tFM10K_WRITE_REG(hw, FM10K_TDBAH(i), bah);\n\t\tFM10K_WRITE_REG(hw, FM10K_RDBAL(i), bal);\n\t\tFM10K_WRITE_REG(hw, FM10K_RDBAH(i), bah);\n\t}\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_reset_hw_vf - VF hardware reset\n * @hw: pointer to hardware structure\n *\n * This function should return the hardware to a state similar to the\n * one it is in after just being initialized.\n **/\nSTATIC s32 fm10k_reset_hw_vf(struct fm10k_hw *hw)\n{\n\ts32 err;\n\n\tDEBUGFUNC(\"fm10k_reset_hw_vf\");\n\n\t/* shut down queues we own and reset DMA configuration */\n\terr = fm10k_stop_hw_vf(hw);\n\tif (err)\n\t\treturn err;\n\n\t/* Inititate VF reset */\n\tFM10K_WRITE_REG(hw, FM10K_VFCTRL, FM10K_VFCTRL_RST);\n\n\t/* Flush write and allow 100us for reset to complete */\n\tFM10K_WRITE_FLUSH(hw);\n\tusec_delay(FM10K_RESET_TIMEOUT);\n\n\t/* Clear reset bit and verify it was cleared */\n\tFM10K_WRITE_REG(hw, FM10K_VFCTRL, 0);\n\tif (FM10K_READ_REG(hw, FM10K_VFCTRL) & FM10K_VFCTRL_RST)\n\t\terr = FM10K_ERR_RESET_FAILED;\n\n\treturn err;\n}\n\n/**\n * fm10k_init_hw_vf - VF hardware initialization\n * @hw: pointer to hardware structure\n *\n **/\nSTATIC s32 fm10k_init_hw_vf(struct fm10k_hw *hw)\n{\n\tu32 tqdloc, tqdloc0 = ~FM10K_READ_REG(hw, FM10K_TQDLOC(0));\n\ts32 err;\n\tu16 i;\n\n\tDEBUGFUNC(\"fm10k_init_hw_vf\");\n\n\t/* assume we always have at least 1 queue */\n\tfor (i = 1; tqdloc0 && (i < FM10K_MAX_QUEUES_POOL); i++) {\n\t\t/* verify the Descriptor cache offsets are increasing */\n\t\ttqdloc = ~FM10K_READ_REG(hw, FM10K_TQDLOC(i));\n\t\tif (!tqdloc || (tqdloc == tqdloc0))\n\t\t\tbreak;\n\n\t\t/* check to verify the PF doesn't own any of our queues */\n\t\tif (!~FM10K_READ_REG(hw, FM10K_TXQCTL(i)) ||\n\t\t !~FM10K_READ_REG(hw, FM10K_RXQCTL(i)))\n\t\t\tbreak;\n\t}\n\n\t/* shut down queues we own and reset DMA configuration */\n\terr = fm10k_disable_queues_generic(hw, i);\n\tif (err)\n\t\treturn err;\n\n\t/* record maximum queue count */\n\thw->mac.max_queues = i;\n\n\t/* fetch default VLAN */\n\thw->mac.default_vid = (FM10K_READ_REG(hw, FM10K_TXQCTL(0)) &\n\t\t\t FM10K_TXQCTL_VID_MASK) >> FM10K_TXQCTL_VID_SHIFT;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_is_slot_appropriate_vf - Indicate appropriate slot for this SKU\n * @hw: pointer to hardware structure\n *\n * Looks at the PCIe bus info to confirm whether or not this slot can support\n * the necessary bandwidth for this device. Since the VF has no control over\n * the \"slot\" it is in, always indicate that the slot is appropriate.\n **/\nSTATIC bool fm10k_is_slot_appropriate_vf(struct fm10k_hw *hw)\n{\n\tUNREFERENCED_1PARAMETER(hw);\n\tDEBUGFUNC(\"fm10k_is_slot_appropriate_vf\");\n\n\treturn TRUE;\n}\n\n/* This structure defines the attibutes to be parsed below */\nconst struct fm10k_tlv_attr fm10k_mac_vlan_msg_attr[] = {\n\tFM10K_TLV_ATTR_U32(FM10K_MAC_VLAN_MSG_VLAN),\n\tFM10K_TLV_ATTR_BOOL(FM10K_MAC_VLAN_MSG_SET),\n\tFM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_MAC),\n\tFM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_DEFAULT_MAC),\n\tFM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_MULTICAST),\n\tFM10K_TLV_ATTR_LAST\n};\n\n/**\n * fm10k_update_vlan_vf - Update status of VLAN ID in VLAN filter table\n * @hw: pointer to hardware structure\n * @vid: VLAN ID to add to table\n * @vsi: Reserved, should always be 0\n * @set: Indicates if this is a set or clear operation\n *\n * This function adds or removes the corresponding VLAN ID from the VLAN\n * filter table for this VF.\n **/\nSTATIC s32 fm10k_update_vlan_vf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)\n{\n\tstruct fm10k_mbx_info *mbx = &hw->mbx;\n\tu32 msg[4];\n\n\t/* verify the index is not set */\n\tif (vsi)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* verify upper 4 bits of vid and length are 0 */\n\tif ((vid << 16 | vid) >> 28)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* encode set bit into the VLAN ID */\n\tif (!set)\n\t\tvid |= FM10K_VLAN_CLEAR;\n\n\t/* generate VLAN request */\n\tfm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);\n\tfm10k_tlv_attr_put_u32(msg, FM10K_MAC_VLAN_MSG_VLAN, vid);\n\n\t/* load onto outgoing mailbox */\n\treturn mbx->ops.enqueue_tx(hw, mbx, msg);\n}\n\n/**\n * fm10k_msg_mac_vlan_vf - Read device MAC address from mailbox message\n * @hw: pointer to the HW structure\n * @results: Attributes for message\n * @mbx: unused mailbox data\n *\n * This function should determine the MAC address for the VF\n **/\ns32 fm10k_msg_mac_vlan_vf(struct fm10k_hw *hw, u32 **results,\n\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tu8 perm_addr[ETH_ALEN];\n\tu16 vid;\n\ts32 err;\n\n\tUNREFERENCED_1PARAMETER(mbx);\n\tDEBUGFUNC(\"fm10k_msg_mac_vlan_vf\");\n\n\t/* record MAC address requested */\n\terr = fm10k_tlv_attr_get_mac_vlan(\n\t\t\t\t\tresults[FM10K_MAC_VLAN_MSG_DEFAULT_MAC],\n\t\t\t\t\tperm_addr, &vid);\n\tif (err)\n\t\treturn err;\n\n\tmemcpy(hw->mac.perm_addr, perm_addr, ETH_ALEN);\n\thw->mac.default_vid = vid & (FM10K_VLAN_TABLE_VID_MAX - 1);\n\thw->mac.vlan_override = !!(vid & FM10K_VLAN_CLEAR);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_read_mac_addr_vf - Read device MAC address\n * @hw: pointer to the HW structure\n *\n * This function should determine the MAC address for the VF\n **/\nSTATIC s32 fm10k_read_mac_addr_vf(struct fm10k_hw *hw)\n{\n\tu8 perm_addr[ETH_ALEN];\n\tu32 base_addr;\n\n\tDEBUGFUNC(\"fm10k_read_mac_addr_vf\");\n\n\tbase_addr = FM10K_READ_REG(hw, FM10K_TDBAL(0));\n\n\t/* last byte should be 0 */\n\tif (base_addr << 24)\n\t\treturn FM10K_ERR_INVALID_MAC_ADDR;\n\n\tperm_addr[3] = (u8)(base_addr >> 24);\n\tperm_addr[4] = (u8)(base_addr >> 16);\n\tperm_addr[5] = (u8)(base_addr >> 8);\n\n\tbase_addr = FM10K_READ_REG(hw, FM10K_TDBAH(0));\n\n\t/* first byte should be all 1's */\n\tif ((~base_addr) >> 24)\n\t\treturn FM10K_ERR_INVALID_MAC_ADDR;\n\n\tperm_addr[0] = (u8)(base_addr >> 16);\n\tperm_addr[1] = (u8)(base_addr >> 8);\n\tperm_addr[2] = (u8)(base_addr);\n\n\tmemcpy(hw->mac.perm_addr, perm_addr, ETH_ALEN);\n\tmemcpy(hw->mac.addr, perm_addr, ETH_ALEN);\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_update_uc_addr_vf - Update device unicast addresses\n * @hw: pointer to the HW structure\n * @glort: unused\n * @mac: MAC address to add/remove from table\n * @vid: VLAN ID to add/remove from table\n * @add: Indicates if this is an add or remove operation\n * @flags: flags field to indicate add and secure - unused\n *\n * This function is used to add or remove unicast MAC addresses for\n * the VF.\n **/\nSTATIC s32 fm10k_update_uc_addr_vf(struct fm10k_hw *hw, u16 glort,\n\t\t\t\t const u8 *mac, u16 vid, bool add, u8 flags)\n{\n\tstruct fm10k_mbx_info *mbx = &hw->mbx;\n\tu32 msg[7];\n\n\tDEBUGFUNC(\"fm10k_update_uc_addr_vf\");\n\n\tUNREFERENCED_2PARAMETER(glort, flags);\n\n\t/* verify VLAN ID is valid */\n\tif (vid >= FM10K_VLAN_TABLE_VID_MAX)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* verify MAC address is valid */\n\tif (!FM10K_IS_VALID_ETHER_ADDR(mac))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* verify we are not locked down on the MAC address */\n\tif (FM10K_IS_VALID_ETHER_ADDR(hw->mac.perm_addr) &&\n\t memcmp(hw->mac.perm_addr, mac, ETH_ALEN))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* add bit to notify us if this is a set or clear operation */\n\tif (!add)\n\t\tvid |= FM10K_VLAN_CLEAR;\n\n\t/* generate VLAN request */\n\tfm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);\n\tfm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_MAC, mac, vid);\n\n\t/* load onto outgoing mailbox */\n\treturn mbx->ops.enqueue_tx(hw, mbx, msg);\n}\n\n/**\n * fm10k_update_mc_addr_vf - Update device multicast addresses\n * @hw: pointer to the HW structure\n * @glort: unused\n * @mac: MAC address to add/remove from table\n * @vid: VLAN ID to add/remove from table\n * @add: Indicates if this is an add or remove operation\n *\n * This function is used to add or remove multicast MAC addresses for\n * the VF.\n **/\nSTATIC s32 fm10k_update_mc_addr_vf(struct fm10k_hw *hw, u16 glort,\n\t\t\t\t const u8 *mac, u16 vid, bool add)\n{\n\tstruct fm10k_mbx_info *mbx = &hw->mbx;\n\tu32 msg[7];\n\n\tDEBUGFUNC(\"fm10k_update_uc_addr_vf\");\n\n\tUNREFERENCED_1PARAMETER(glort);\n\n\t/* verify VLAN ID is valid */\n\tif (vid >= FM10K_VLAN_TABLE_VID_MAX)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* verify multicast address is valid */\n\tif (!FM10K_IS_MULTICAST_ETHER_ADDR(mac))\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* add bit to notify us if this is a set or clear operation */\n\tif (!add)\n\t\tvid |= FM10K_VLAN_CLEAR;\n\n\t/* generate VLAN request */\n\tfm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);\n\tfm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_MULTICAST,\n\t\t\t\t mac, vid);\n\n\t/* load onto outgoing mailbox */\n\treturn mbx->ops.enqueue_tx(hw, mbx, msg);\n}\n\n/**\n * fm10k_update_int_moderator_vf - Request update of interrupt moderator list\n * @hw: pointer to hardware structure\n *\n * This function will issue a request to the PF to rescan our MSI-X table\n * and to update the interrupt moderator linked list.\n **/\nSTATIC void fm10k_update_int_moderator_vf(struct fm10k_hw *hw)\n{\n\tstruct fm10k_mbx_info *mbx = &hw->mbx;\n\tu32 msg[1];\n\n\t/* generate MSI-X request */\n\tfm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MSIX);\n\n\t/* load onto outgoing mailbox */\n\tmbx->ops.enqueue_tx(hw, mbx, msg);\n}\n\n/* This structure defines the attibutes to be parsed below */\nconst struct fm10k_tlv_attr fm10k_lport_state_msg_attr[] = {\n\tFM10K_TLV_ATTR_BOOL(FM10K_LPORT_STATE_MSG_DISABLE),\n\tFM10K_TLV_ATTR_U8(FM10K_LPORT_STATE_MSG_XCAST_MODE),\n\tFM10K_TLV_ATTR_BOOL(FM10K_LPORT_STATE_MSG_READY),\n\tFM10K_TLV_ATTR_LAST\n};\n\n/**\n * fm10k_msg_lport_state_vf - Message handler for lport_state message from PF\n * @hw: Pointer to hardware structure\n * @results: pointer array containing parsed data\n * @mbx: Pointer to mailbox information structure\n *\n * This handler is meant to capture the indication from the PF that we\n * are ready to bring up the interface.\n **/\ns32 fm10k_msg_lport_state_vf(struct fm10k_hw *hw, u32 **results,\n\t\t\t struct fm10k_mbx_info *mbx)\n{\n\tUNREFERENCED_1PARAMETER(mbx);\n\tDEBUGFUNC(\"fm10k_msg_lport_state_vf\");\n\n\thw->mac.dglort_map = !results[FM10K_LPORT_STATE_MSG_READY] ?\n\t\t\t FM10K_DGLORTMAP_NONE : FM10K_DGLORTMAP_ZERO;\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_update_lport_state_vf - Update device state in lower device\n * @hw: pointer to the HW structure\n * @glort: unused\n * @count: number of logical ports to enable - unused (always 1)\n * @enable: boolean value indicating if this is an enable or disable request\n *\n * Notify the lower device of a state change. If the lower device is\n * enabled we can add filters, if it is disabled all filters for this\n * logical port are flushed.\n **/\nSTATIC s32 fm10k_update_lport_state_vf(struct fm10k_hw *hw, u16 glort,\n\t\t\t\t u16 count, bool enable)\n{\n\tstruct fm10k_mbx_info *mbx = &hw->mbx;\n\tu32 msg[2];\n\n\tUNREFERENCED_2PARAMETER(glort, count);\n\tDEBUGFUNC(\"fm10k_update_lport_state_vf\");\n\n\t/* reset glort mask 0 as we have to wait to be enabled */\n\thw->mac.dglort_map = FM10K_DGLORTMAP_NONE;\n\n\t/* generate port state request */\n\tfm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);\n\tif (!enable)\n\t\tfm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_DISABLE);\n\n\t/* load onto outgoing mailbox */\n\treturn mbx->ops.enqueue_tx(hw, mbx, msg);\n}\n\n/**\n * fm10k_update_xcast_mode_vf - Request update of multicast mode\n * @hw: pointer to hardware structure\n * @glort: unused\n * @mode: integer value indicating mode being requested\n *\n * This function will attempt to request a higher mode for the port\n * so that it can enable either multicast, multicast promiscuous, or\n * promiscuous mode of operation.\n **/\nSTATIC s32 fm10k_update_xcast_mode_vf(struct fm10k_hw *hw, u16 glort, u8 mode)\n{\n\tstruct fm10k_mbx_info *mbx = &hw->mbx;\n\tu32 msg[3];\n\n\tUNREFERENCED_1PARAMETER(glort);\n\tDEBUGFUNC(\"fm10k_update_xcast_mode_vf\");\n\n\tif (mode > FM10K_XCAST_MODE_NONE)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* generate message requesting to change xcast mode */\n\tfm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);\n\tfm10k_tlv_attr_put_u8(msg, FM10K_LPORT_STATE_MSG_XCAST_MODE, mode);\n\n\t/* load onto outgoing mailbox */\n\treturn mbx->ops.enqueue_tx(hw, mbx, msg);\n}\n\nconst struct fm10k_tlv_attr fm10k_1588_msg_attr[] = {\n\tFM10K_TLV_ATTR_U64(FM10K_1588_MSG_TIMESTAMP),\n\tFM10K_TLV_ATTR_LAST\n};\n\n/* currently there is no shared 1588 timestamp handler */\n\n/**\n * fm10k_update_hw_stats_vf - Updates hardware related statistics of VF\n * @hw: pointer to hardware structure\n * @stats: pointer to statistics structure\n *\n * This function collects and aggregates per queue hardware statistics.\n **/\nSTATIC void fm10k_update_hw_stats_vf(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_hw_stats *stats)\n{\n\tDEBUGFUNC(\"fm10k_update_hw_stats_vf\");\n\n\tfm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);\n}\n\n/**\n * fm10k_rebind_hw_stats_vf - Resets base for hardware statistics of VF\n * @hw: pointer to hardware structure\n * @stats: pointer to the stats structure to update\n *\n * This function resets the base for queue hardware statistics.\n **/\nSTATIC void fm10k_rebind_hw_stats_vf(struct fm10k_hw *hw,\n\t\t\t\t struct fm10k_hw_stats *stats)\n{\n\tDEBUGFUNC(\"fm10k_rebind_hw_stats_vf\");\n\n\t/* Unbind Queue Statistics */\n\tfm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);\n\n\t/* Reinitialize bases for all stats */\n\tfm10k_update_hw_stats_vf(hw, stats);\n}\n\n/**\n * fm10k_configure_dglort_map_vf - Configures GLORT entry and queues\n * @hw: pointer to hardware structure\n * @dglort: pointer to dglort configuration structure\n *\n * Reads the configuration structure contained in dglort_cfg and uses\n * that information to then populate a DGLORTMAP/DEC entry and the queues\n * to which it has been assigned.\n **/\nSTATIC s32 fm10k_configure_dglort_map_vf(struct fm10k_hw *hw,\n\t\t\t\t\t struct fm10k_dglort_cfg *dglort)\n{\n\tUNREFERENCED_1PARAMETER(hw);\n\tDEBUGFUNC(\"fm10k_configure_dglort_map_vf\");\n\n\t/* verify the dglort pointer */\n\tif (!dglort)\n\t\treturn FM10K_ERR_PARAM;\n\n\t/* stub for now until we determine correct message for this */\n\n\treturn FM10K_SUCCESS;\n}\n\n/**\n * fm10k_adjust_systime_vf - Adjust systime frequency\n * @hw: pointer to hardware structure\n * @ppb: adjustment rate in parts per billion\n *\n * This function takes an adjustment rate in parts per billion and will\n * verify that this value is 0 as the VF cannot support adjusting the\n * systime clock.\n *\n * If the ppb value is non-zero the return is ERR_PARAM else success\n **/\nSTATIC s32 fm10k_adjust_systime_vf(struct fm10k_hw *hw, s32 ppb)\n{\n\tUNREFERENCED_1PARAMETER(hw);\n\tDEBUGFUNC(\"fm10k_adjust_systime_vf\");\n\n\t/* The VF cannot adjust the clock frequency, however it should\n\t * already have a syntonic clock with whichever host interface is\n\t * running as the master for the host interface clock domain so\n\t * there should be not frequency adjustment necessary.\n\t */\n\treturn ppb ? FM10K_ERR_PARAM : FM10K_SUCCESS;\n}\n\n/**\n * fm10k_read_systime_vf - Reads value of systime registers\n * @hw: pointer to the hardware structure\n *\n * Function reads the content of 2 registers, combined to represent a 64 bit\n * value measured in nanoseconds. In order to guarantee the value is accurate\n * we check the 32 most significant bits both before and after reading the\n * 32 least significant bits to verify they didn't change as we were reading\n * the registers.\n **/\nstatic u64 fm10k_read_systime_vf(struct fm10k_hw *hw)\n{\n\tu32 systime_l, systime_h, systime_tmp;\n\n\tsystime_h = fm10k_read_reg(hw, FM10K_VFSYSTIME + 1);\n\n\tdo {\n\t\tsystime_tmp = systime_h;\n\t\tsystime_l = fm10k_read_reg(hw, FM10K_VFSYSTIME);\n\t\tsystime_h = fm10k_read_reg(hw, FM10K_VFSYSTIME + 1);\n\t} while (systime_tmp != systime_h);\n\n\treturn ((u64)systime_h << 32) | systime_l;\n}\n\nstatic const struct fm10k_msg_data fm10k_msg_data_vf[] = {\n\tFM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),\n\tFM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),\n\tFM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),\n\tFM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),\n};\n\n/**\n * fm10k_init_ops_vf - Inits func ptrs and MAC type\n * @hw: pointer to hardware structure\n *\n * Initialize the function pointers and assign the MAC type for VF.\n * Does not touch the hardware.\n **/\ns32 fm10k_init_ops_vf(struct fm10k_hw *hw)\n{\n\tstruct fm10k_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"fm10k_init_ops_vf\");\n\n\tfm10k_init_ops_generic(hw);\n\n\tmac->ops.reset_hw = &fm10k_reset_hw_vf;\n\tmac->ops.init_hw = &fm10k_init_hw_vf;\n\tmac->ops.start_hw = &fm10k_start_hw_generic;\n\tmac->ops.stop_hw = &fm10k_stop_hw_vf;\n\tmac->ops.is_slot_appropriate = &fm10k_is_slot_appropriate_vf;\n\tmac->ops.update_vlan = &fm10k_update_vlan_vf;\n\tmac->ops.read_mac_addr = &fm10k_read_mac_addr_vf;\n\tmac->ops.update_uc_addr = &fm10k_update_uc_addr_vf;\n\tmac->ops.update_mc_addr = &fm10k_update_mc_addr_vf;\n\tmac->ops.update_xcast_mode = &fm10k_update_xcast_mode_vf;\n\tmac->ops.update_int_moderator = &fm10k_update_int_moderator_vf;\n\tmac->ops.update_lport_state = &fm10k_update_lport_state_vf;\n\tmac->ops.update_hw_stats = &fm10k_update_hw_stats_vf;\n\tmac->ops.rebind_hw_stats = &fm10k_rebind_hw_stats_vf;\n\tmac->ops.configure_dglort_map = &fm10k_configure_dglort_map_vf;\n\tmac->ops.get_host_state = &fm10k_get_host_state_generic;\n\tmac->ops.adjust_systime = &fm10k_adjust_systime_vf;\n\tmac->ops.read_systime = &fm10k_read_systime_vf,\n\n\tmac->max_msix_vectors = fm10k_get_pcie_msix_count_generic(hw);\n\n\treturn fm10k_pfvf_mbx_init(hw, &hw->mbx, fm10k_msg_data_vf, 0);\n}\n" }, { "path": "drivers/net/fm10k/base/fm10k_vf.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _FM10K_VF_H_\n#define _FM10K_VF_H_\n\n#include \"fm10k_type.h\"\n#include \"fm10k_common.h\"\n\nenum fm10k_vf_tlv_msg_id {\n\tFM10K_VF_MSG_ID_TEST = 0,\t/* msg ID reserved for testing */\n\tFM10K_VF_MSG_ID_MSIX,\n\tFM10K_VF_MSG_ID_MAC_VLAN,\n\tFM10K_VF_MSG_ID_LPORT_STATE,\n\tFM10K_VF_MSG_ID_1588,\n\tFM10K_VF_MSG_ID_MAX,\n};\n\nenum fm10k_tlv_mac_vlan_attr_id {\n\tFM10K_MAC_VLAN_MSG_VLAN,\n\tFM10K_MAC_VLAN_MSG_SET,\n\tFM10K_MAC_VLAN_MSG_MAC,\n\tFM10K_MAC_VLAN_MSG_DEFAULT_MAC,\n\tFM10K_MAC_VLAN_MSG_MULTICAST,\n\tFM10K_MAC_VLAN_MSG_ID_MAX\n};\n\nenum fm10k_tlv_lport_state_attr_id {\n\tFM10K_LPORT_STATE_MSG_DISABLE,\n\tFM10K_LPORT_STATE_MSG_XCAST_MODE,\n\tFM10K_LPORT_STATE_MSG_READY,\n\tFM10K_LPORT_STATE_MSG_MAX\n};\n\nenum fm10k_tlv_1588_attr_id {\n\tFM10K_1588_MSG_TIMESTAMP,\n\tFM10K_1588_MSG_MAX\n};\n\n#define FM10K_VF_MSG_MSIX_HANDLER(func) \\\n\t FM10K_MSG_HANDLER(FM10K_VF_MSG_ID_MSIX, NULL, func)\n\ns32 fm10k_msg_mac_vlan_vf(struct fm10k_hw *, u32 **, struct fm10k_mbx_info *);\nextern const struct fm10k_tlv_attr fm10k_mac_vlan_msg_attr[];\n#define FM10K_VF_MSG_MAC_VLAN_HANDLER(func) \\\n\tFM10K_MSG_HANDLER(FM10K_VF_MSG_ID_MAC_VLAN, \\\n\t\t\t fm10k_mac_vlan_msg_attr, func)\n\ns32 fm10k_msg_lport_state_vf(struct fm10k_hw *, u32 **,\n\t\t\t struct fm10k_mbx_info *);\nextern const struct fm10k_tlv_attr fm10k_lport_state_msg_attr[];\n#define FM10K_VF_MSG_LPORT_STATE_HANDLER(func) \\\n\tFM10K_MSG_HANDLER(FM10K_VF_MSG_ID_LPORT_STATE, \\\n\t\t\t fm10k_lport_state_msg_attr, func)\n\nextern const struct fm10k_tlv_attr fm10k_1588_msg_attr[];\n#define FM10K_VF_MSG_1588_HANDLER(func) \\\n\tFM10K_MSG_HANDLER(FM10K_VF_MSG_ID_1588, fm10k_1588_msg_attr, func)\n\ns32 fm10k_init_ops_vf(struct fm10k_hw *hw);\n#endif /* _FM10K_VF_H */\n" }, { "path": "drivers/net/fm10k/fm10k.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _FM10K_H_\n#define _FM10K_H_\n\n#include \n#include \n#include \n#include \n#include \n#include \"fm10k_logs.h\"\n#include \"base/fm10k_type.h\"\n\n/* descriptor ring base addresses must be aligned to the following */\n#define FM10K_ALIGN_RX_DESC 128\n#define FM10K_ALIGN_TX_DESC 128\n\n/* The maximum packet size that FM10K supports */\n#define FM10K_MAX_PKT_SIZE (15 * 1024)\n\n/* Minimum size of RX buffer FM10K supported */\n#define FM10K_MIN_RX_BUF_SIZE 256\n\n/* The maximum of SRIOV VFs per port supported */\n#define FM10K_MAX_VF_NUM 64\n\n/* number of descriptors must be a multiple of the following */\n#define FM10K_MULT_RX_DESC FM10K_REQ_RX_DESCRIPTOR_MULTIPLE\n#define FM10K_MULT_TX_DESC FM10K_REQ_TX_DESCRIPTOR_MULTIPLE\n\n/* maximum size of descriptor rings */\n#define FM10K_MAX_RX_RING_SZ (512 * 1024)\n#define FM10K_MAX_TX_RING_SZ (512 * 1024)\n\n/* minimum and maximum number of descriptors in a ring */\n#define FM10K_MIN_RX_DESC 32\n#define FM10K_MIN_TX_DESC 32\n#define FM10K_MAX_RX_DESC (FM10K_MAX_RX_RING_SZ / sizeof(union fm10k_rx_desc))\n#define FM10K_MAX_TX_DESC (FM10K_MAX_TX_RING_SZ / sizeof(struct fm10k_tx_desc))\n\n/*\n * byte aligment for HW RX data buffer\n * Datasheet requires RX buffer addresses shall either be 512-byte aligned or\n * be 8-byte aligned but without crossing host memory pages (4KB alignment\n * boundaries). Satisfy first option.\n */\n#define FM10K_RX_DATABUF_ALIGN 512\n\n/*\n * threshold default, min, max, and divisor constraints\n * the configured values must satisfy the following:\n * MIN <= value <= MAX\n * DIV % value == 0\n */\n#define FM10K_RX_FREE_THRESH_DEFAULT(rxq) 32\n#define FM10K_RX_FREE_THRESH_MIN(rxq) 1\n#define FM10K_RX_FREE_THRESH_MAX(rxq) ((rxq)->nb_desc - 1)\n#define FM10K_RX_FREE_THRESH_DIV(rxq) ((rxq)->nb_desc)\n\n#define FM10K_TX_FREE_THRESH_DEFAULT(txq) 32\n#define FM10K_TX_FREE_THRESH_MIN(txq) 1\n#define FM10K_TX_FREE_THRESH_MAX(txq) ((txq)->nb_desc - 3)\n#define FM10K_TX_FREE_THRESH_DIV(txq) 0\n\n#define FM10K_DEFAULT_RX_PTHRESH 8\n#define FM10K_DEFAULT_RX_HTHRESH 8\n#define FM10K_DEFAULT_RX_WTHRESH 0\n\n#define FM10K_DEFAULT_TX_PTHRESH 32\n#define FM10K_DEFAULT_TX_HTHRESH 0\n#define FM10K_DEFAULT_TX_WTHRESH 0\n\n#define FM10K_TX_RS_THRESH_DEFAULT(txq) 32\n#define FM10K_TX_RS_THRESH_MIN(txq) 1\n#define FM10K_TX_RS_THRESH_MAX(txq) \\\n\tRTE_MIN(((txq)->nb_desc - 2), (txq)->free_thresh)\n#define FM10K_TX_RS_THRESH_DIV(txq) ((txq)->nb_desc)\n\n#define FM10K_VLAN_TAG_SIZE 4\n\n/* Maximum number of MAC addresses per PF/VF */\n#define FM10K_MAX_MACADDR_NUM 64\n\n#define FM10K_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))\n#define FM10K_VFTA_SIZE (4096 / FM10K_UINT32_BIT_SIZE)\n\n/* vlan_id is a 12 bit number.\n * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.\n * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.\n * The higher 7 bit val specifies VFTA array index.\n */\n#define FM10K_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))\n#define FM10K_VFTA_IDX(vlan_id) ((vlan_id) >> 5)\n\nstruct fm10k_macvlan_filter_info {\n\tuint16_t vlan_num; /* Total VLAN number */\n\tuint16_t mac_num; /* Total mac number */\n\tuint32_t vfta[FM10K_VFTA_SIZE]; /* VLAN bitmap */\n};\n\nstruct fm10k_dev_info {\n\tvolatile uint32_t enable;\n\tvolatile uint32_t glort;\n\t/* Protect the mailbox to avoid race condition */\n\trte_spinlock_t mbx_lock;\n\tstruct fm10k_macvlan_filter_info macvlan;\n};\n\n/*\n * Structure to store private data for each driver instance.\n */\nstruct fm10k_adapter {\n\tstruct fm10k_hw hw;\n\tstruct fm10k_hw_stats stats;\n\tstruct fm10k_dev_info info;\n};\n\n#define FM10K_DEV_PRIVATE_TO_HW(adapter) \\\n\t(&((struct fm10k_adapter *)adapter)->hw)\n\n#define FM10K_DEV_PRIVATE_TO_STATS(adapter) \\\n\t(&((struct fm10k_adapter *)adapter)->stats)\n\n#define FM10K_DEV_PRIVATE_TO_INFO(adapter) \\\n\t(&((struct fm10k_adapter *)adapter)->info)\n\n#define FM10K_DEV_PRIVATE_TO_MBXLOCK(adapter) \\\n\t(&(((struct fm10k_adapter *)adapter)->info.mbx_lock))\n\n#define FM10K_DEV_PRIVATE_TO_MACVLAN(adapter) \\\n\t\t(&(((struct fm10k_adapter *)adapter)->info.macvlan))\n\nstruct fm10k_rx_queue {\n\tstruct rte_mempool *mp;\n\tstruct rte_mbuf **sw_ring;\n\tvolatile union fm10k_rx_desc *hw_ring;\n\tstruct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */\n\tstruct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */\n\tuint64_t hw_ring_phys_addr;\n\tuint16_t next_dd;\n\tuint16_t next_alloc;\n\tuint16_t next_trigger;\n\tuint16_t alloc_thresh;\n\tvolatile uint32_t *tail_ptr;\n\tuint16_t nb_desc;\n\tuint16_t queue_id;\n\tuint8_t port_id;\n\tuint8_t drop_en;\n\tuint8_t rx_deferred_start; /**< don't start this queue in dev start. */\n};\n\n/*\n * a FIFO is used to track which descriptors have their RS bit set for Tx\n * queues which are configured to allow multiple descriptors per packet\n */\nstruct fifo {\n\tuint16_t *list;\n\tuint16_t *head;\n\tuint16_t *tail;\n\tuint16_t *endp;\n};\n\nstruct fm10k_tx_queue {\n\tstruct rte_mbuf **sw_ring;\n\tstruct fm10k_tx_desc *hw_ring;\n\tuint64_t hw_ring_phys_addr;\n\tstruct fifo rs_tracker;\n\tuint16_t last_free;\n\tuint16_t next_free;\n\tuint16_t nb_free;\n\tuint16_t nb_used;\n\tuint16_t free_thresh;\n\tuint16_t rs_thresh;\n\tvolatile uint32_t *tail_ptr;\n\tuint16_t nb_desc;\n\tuint8_t port_id;\n\tuint8_t tx_deferred_start; /** < don't start this queue in dev start. */\n\tuint16_t queue_id;\n};\n\n#define MBUF_DMA_ADDR(mb) \\\n\t((uint64_t) ((mb)->buf_physaddr + (mb)->data_off))\n\n/* enforce 512B alignment on default Rx DMA addresses */\n#define MBUF_DMA_ADDR_DEFAULT(mb) \\\n\t((uint64_t) RTE_ALIGN(((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM),\\\n\t\t\tFM10K_RX_DATABUF_ALIGN))\n\nstatic inline void fifo_reset(struct fifo *fifo, uint32_t len)\n{\n\tfifo->head = fifo->tail = fifo->list;\n\tfifo->endp = fifo->list + len;\n}\n\nstatic inline void fifo_insert(struct fifo *fifo, uint16_t val)\n{\n\t*fifo->head = val;\n\tif (++fifo->head == fifo->endp)\n\t\tfifo->head = fifo->list;\n}\n\n/* do not worry about list being empty since we only check it once we know\n * we have used enough descriptors to set the RS bit at least once */\nstatic inline uint16_t fifo_peek(struct fifo *fifo)\n{\n\treturn *fifo->tail;\n}\n\nstatic inline uint16_t fifo_remove(struct fifo *fifo)\n{\n\tuint16_t val;\n\tval = *fifo->tail;\n\tif (++fifo->tail == fifo->endp)\n\t\tfifo->tail = fifo->list;\n\treturn val;\n}\n\nstatic inline void\nfm10k_pktmbuf_reset(struct rte_mbuf *mb, uint8_t in_port)\n{\n\trte_mbuf_refcnt_set(mb, 1);\n\tmb->next = NULL;\n\tmb->nb_segs = 1;\n\n\t/* enforce 512B alignment on default Rx virtual addresses */\n\tmb->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb->buf_addr +\n\t\t\tRTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)\n\t\t\t- (char *)mb->buf_addr);\n\tmb->port = in_port;\n}\n\n/*\n * Verify Rx packet buffer alignment is valid.\n *\n * Hardware requires specific alignment for Rx packet buffers. At\n * least one of the following two conditions must be satisfied.\n * 1. Address is 512B aligned\n * 2. Address is 8B aligned and buffer does not cross 4K boundary.\n *\n * Return 1 if buffer alignment satisfies at least one condition,\n * otherwise return 0.\n *\n * Note: Alignment is checked by the driver when the Rx queue is reset. It\n * is assumed that if an entire descriptor ring can be filled with\n * buffers containing valid alignment, then all buffers in that mempool\n * have valid address alignment. It is the responsibility of the user\n * to ensure all buffers have valid alignment, as it is the user who\n * creates the mempool.\n * Note: It is assumed the buffer needs only to store a maximum size Ethernet\n * frame.\n */\nstatic inline int\nfm10k_addr_alignment_valid(struct rte_mbuf *mb)\n{\n\tuint64_t addr = MBUF_DMA_ADDR_DEFAULT(mb);\n\tuint64_t boundary1, boundary2;\n\n\t/* 512B aligned? */\n\tif (RTE_ALIGN(addr, FM10K_RX_DATABUF_ALIGN) == addr)\n\t\treturn 1;\n\n\t/* 8B aligned, and max Ethernet frame would not cross a 4KB boundary? */\n\tif (RTE_ALIGN(addr, 8) == addr) {\n\t\tboundary1 = RTE_ALIGN_FLOOR(addr, 4096);\n\t\tboundary2 = RTE_ALIGN_FLOOR(addr + ETHER_MAX_VLAN_FRAME_LEN,\n\t\t\t\t\t\t4096);\n\t\tif (boundary1 == boundary2)\n\t\t\treturn 1;\n\t}\n\n\tPMD_INIT_LOG(ERR, \"Error: Invalid buffer alignment!\");\n\n\treturn 0;\n}\n\n/* Rx and Tx prototypes */\nuint16_t fm10k_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\tuint16_t nb_pkts);\n\nuint16_t fm10k_recv_scattered_pkts(void *rx_queue,\n\t\tstruct rte_mbuf **rx_pkts, uint16_t nb_pkts);\n\nuint16_t fm10k_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\tuint16_t nb_pkts);\n#endif\n" }, { "path": "drivers/net/fm10k/fm10k_ethdev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"fm10k.h\"\n#include \"base/fm10k_api.h\"\n\n/* Default delay to acquire mailbox lock */\n#define FM10K_MBXLOCK_DELAY_US 20\n#define UINT64_LOWER_32BITS_MASK 0x00000000ffffffffULL\n\n/* Max try times to acquire switch status */\n#define MAX_QUERY_SWITCH_STATE_TIMES 10\n/* Wait interval to get switch status */\n#define WAIT_SWITCH_MSG_US 100000\n/* Number of chars per uint32 type */\n#define CHARS_PER_UINT32 (sizeof(uint32_t))\n#define BIT_MASK_PER_UINT32 ((1 << CHARS_PER_UINT32) - 1)\n\nstatic void fm10k_close_mbx_service(struct fm10k_hw *hw);\nstatic void fm10k_dev_promiscuous_enable(struct rte_eth_dev *dev);\nstatic void fm10k_dev_promiscuous_disable(struct rte_eth_dev *dev);\nstatic void fm10k_dev_allmulticast_enable(struct rte_eth_dev *dev);\nstatic void fm10k_dev_allmulticast_disable(struct rte_eth_dev *dev);\nstatic inline int fm10k_glort_valid(struct fm10k_hw *hw);\nstatic int\nfm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);\nstatic void\nfm10k_MAC_filter_set(struct rte_eth_dev *dev, const u8 *mac, bool add);\nstatic void\nfm10k_MACVLAN_remove_all(struct rte_eth_dev *dev);\nstatic void fm10k_tx_queue_release(void *queue);\nstatic void fm10k_rx_queue_release(void *queue);\n\nstatic void\nfm10k_mbx_initlock(struct fm10k_hw *hw)\n{\n\trte_spinlock_init(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));\n}\n\nstatic void\nfm10k_mbx_lock(struct fm10k_hw *hw)\n{\n\twhile (!rte_spinlock_trylock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back)))\n\t\trte_delay_us(FM10K_MBXLOCK_DELAY_US);\n}\n\nstatic void\nfm10k_mbx_unlock(struct fm10k_hw *hw)\n{\n\trte_spinlock_unlock(FM10K_DEV_PRIVATE_TO_MBXLOCK(hw->back));\n}\n\n/*\n * reset queue to initial state, allocate software buffers used when starting\n * device.\n * return 0 on success\n * return -ENOMEM if buffers cannot be allocated\n * return -EINVAL if buffers do not satisfy alignment condition\n */\nstatic inline int\nrx_queue_reset(struct fm10k_rx_queue *q)\n{\n\tuint64_t dma_addr;\n\tint i, diag;\n\tPMD_INIT_FUNC_TRACE();\n\n\tdiag = rte_mempool_get_bulk(q->mp, (void **)q->sw_ring, q->nb_desc);\n\tif (diag != 0)\n\t\treturn -ENOMEM;\n\n\tfor (i = 0; i < q->nb_desc; ++i) {\n\t\tfm10k_pktmbuf_reset(q->sw_ring[i], q->port_id);\n\t\tif (!fm10k_addr_alignment_valid(q->sw_ring[i])) {\n\t\t\trte_mempool_put_bulk(q->mp, (void **)q->sw_ring,\n\t\t\t\t\t\tq->nb_desc);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tdma_addr = MBUF_DMA_ADDR_DEFAULT(q->sw_ring[i]);\n\t\tq->hw_ring[i].q.pkt_addr = dma_addr;\n\t\tq->hw_ring[i].q.hdr_addr = dma_addr;\n\t}\n\n\tq->next_dd = 0;\n\tq->next_alloc = 0;\n\tq->next_trigger = q->alloc_thresh - 1;\n\tFM10K_PCI_REG_WRITE(q->tail_ptr, q->nb_desc - 1);\n\treturn 0;\n}\n\n/*\n * clean queue, descriptor rings, free software buffers used when stopping\n * device.\n */\nstatic inline void\nrx_queue_clean(struct fm10k_rx_queue *q)\n{\n\tunion fm10k_rx_desc zero = {.q = {0, 0, 0, 0} };\n\tuint32_t i;\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* zero descriptor rings */\n\tfor (i = 0; i < q->nb_desc; ++i)\n\t\tq->hw_ring[i] = zero;\n\n\t/* free software buffers */\n\tfor (i = 0; i < q->nb_desc; ++i) {\n\t\tif (q->sw_ring[i]) {\n\t\t\trte_pktmbuf_free_seg(q->sw_ring[i]);\n\t\t\tq->sw_ring[i] = NULL;\n\t\t}\n\t}\n}\n\n/*\n * free all queue memory used when releasing the queue (i.e. configure)\n */\nstatic inline void\nrx_queue_free(struct fm10k_rx_queue *q)\n{\n\tPMD_INIT_FUNC_TRACE();\n\tif (q) {\n\t\tPMD_INIT_LOG(DEBUG, \"Freeing rx queue %p\", q);\n\t\trx_queue_clean(q);\n\t\tif (q->sw_ring) {\n\t\t\trte_free(q->sw_ring);\n\t\t\tq->sw_ring = NULL;\n\t\t}\n\t\trte_free(q);\n\t\tq = NULL;\n\t}\n}\n\n/*\n * disable RX queue, wait unitl HW finished necessary flush operation\n */\nstatic inline int\nrx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)\n{\n\tuint32_t reg, i;\n\n\treg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));\n\tFM10K_WRITE_REG(hw, FM10K_RXQCTL(qnum),\n\t\t\treg & ~FM10K_RXQCTL_ENABLE);\n\n\t/* Wait 100us at most */\n\tfor (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {\n\t\trte_delay_us(1);\n\t\treg = FM10K_READ_REG(hw, FM10K_RXQCTL(qnum));\n\t\tif (!(reg & FM10K_RXQCTL_ENABLE))\n\t\t\tbreak;\n\t}\n\n\tif (i == FM10K_QUEUE_DISABLE_TIMEOUT)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * reset queue to initial state, allocate software buffers used when starting\n * device\n */\nstatic inline void\ntx_queue_reset(struct fm10k_tx_queue *q)\n{\n\tPMD_INIT_FUNC_TRACE();\n\tq->last_free = 0;\n\tq->next_free = 0;\n\tq->nb_used = 0;\n\tq->nb_free = q->nb_desc - 1;\n\tfifo_reset(&q->rs_tracker, (q->nb_desc + 1) / q->rs_thresh);\n\tFM10K_PCI_REG_WRITE(q->tail_ptr, 0);\n}\n\n/*\n * clean queue, descriptor rings, free software buffers used when stopping\n * device\n */\nstatic inline void\ntx_queue_clean(struct fm10k_tx_queue *q)\n{\n\tstruct fm10k_tx_desc zero = {0, 0, 0, 0, 0, 0};\n\tuint32_t i;\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* zero descriptor rings */\n\tfor (i = 0; i < q->nb_desc; ++i)\n\t\tq->hw_ring[i] = zero;\n\n\t/* free software buffers */\n\tfor (i = 0; i < q->nb_desc; ++i) {\n\t\tif (q->sw_ring[i]) {\n\t\t\trte_pktmbuf_free_seg(q->sw_ring[i]);\n\t\t\tq->sw_ring[i] = NULL;\n\t\t}\n\t}\n}\n\n/*\n * free all queue memory used when releasing the queue (i.e. configure)\n */\nstatic inline void\ntx_queue_free(struct fm10k_tx_queue *q)\n{\n\tPMD_INIT_FUNC_TRACE();\n\tif (q) {\n\t\tPMD_INIT_LOG(DEBUG, \"Freeing tx queue %p\", q);\n\t\ttx_queue_clean(q);\n\t\tif (q->rs_tracker.list) {\n\t\t\trte_free(q->rs_tracker.list);\n\t\t\tq->rs_tracker.list = NULL;\n\t\t}\n\t\tif (q->sw_ring) {\n\t\t\trte_free(q->sw_ring);\n\t\t\tq->sw_ring = NULL;\n\t\t}\n\t\trte_free(q);\n\t\tq = NULL;\n\t}\n}\n\n/*\n * disable TX queue, wait unitl HW finished necessary flush operation\n */\nstatic inline int\ntx_queue_disable(struct fm10k_hw *hw, uint16_t qnum)\n{\n\tuint32_t reg, i;\n\n\treg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));\n\tFM10K_WRITE_REG(hw, FM10K_TXDCTL(qnum),\n\t\t\treg & ~FM10K_TXDCTL_ENABLE);\n\n\t/* Wait 100us at most */\n\tfor (i = 0; i < FM10K_QUEUE_DISABLE_TIMEOUT; i++) {\n\t\trte_delay_us(1);\n\t\treg = FM10K_READ_REG(hw, FM10K_TXDCTL(qnum));\n\t\tif (!(reg & FM10K_TXDCTL_ENABLE))\n\t\t\tbreak;\n\t}\n\n\tif (i == FM10K_QUEUE_DISABLE_TIMEOUT)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic int\nfm10k_dev_configure(struct rte_eth_dev *dev)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (dev->data->dev_conf.rxmode.hw_strip_crc == 0)\n\t\tPMD_INIT_LOG(WARNING, \"fm10k always strip CRC\");\n\n\treturn 0;\n}\n\nstatic void\nfm10k_dev_mq_rx_configure(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct rte_eth_conf *dev_conf = &dev->data->dev_conf;\n\tuint32_t mrqc, *key, i, reta, j;\n\tuint64_t hf;\n\n#define RSS_KEY_SIZE 40\n\tstatic uint8_t rss_intel_key[RSS_KEY_SIZE] = {\n\t\t0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,\n\t\t0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,\n\t\t0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,\n\t\t0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,\n\t\t0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,\n\t};\n\n\tif (dev->data->nb_rx_queues == 1 ||\n\t dev_conf->rxmode.mq_mode != ETH_MQ_RX_RSS ||\n\t dev_conf->rx_adv_conf.rss_conf.rss_hf == 0)\n\t\treturn;\n\n\t/* random key is rss_intel_key (default) or user provided (rss_key) */\n\tif (dev_conf->rx_adv_conf.rss_conf.rss_key == NULL)\n\t\tkey = (uint32_t *)rss_intel_key;\n\telse\n\t\tkey = (uint32_t *)dev_conf->rx_adv_conf.rss_conf.rss_key;\n\n\t/* Now fill our hash function seeds, 4 bytes at a time */\n\tfor (i = 0; i < RSS_KEY_SIZE / sizeof(*key); ++i)\n\t\tFM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);\n\n\t/*\n\t * Fill in redirection table\n\t * The byte-swap is needed because NIC registers are in\n\t * little-endian order.\n\t */\n\treta = 0;\n\tfor (i = 0, j = 0; i < FM10K_MAX_RSS_INDICES; i++, j++) {\n\t\tif (j == dev->data->nb_rx_queues)\n\t\t\tj = 0;\n\t\treta = (reta << CHAR_BIT) | j;\n\t\tif ((i & 3) == 3)\n\t\t\tFM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2),\n\t\t\t\t\trte_bswap32(reta));\n\t}\n\n\t/*\n\t * Generate RSS hash based on packet types, TCP/UDP\n\t * port numbers and/or IPv4/v6 src and dst addresses\n\t */\n\thf = dev_conf->rx_adv_conf.rss_conf.rss_hf;\n\tmrqc = 0;\n\tmrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;\n\tmrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;\n\tmrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;\n\tmrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;\n\tmrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;\n\tmrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;\n\tmrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;\n\tmrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;\n\tmrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;\n\n\tif (mrqc == 0) {\n\t\tPMD_INIT_LOG(ERR, \"Specified RSS mode 0x%\"PRIx64\"is not\"\n\t\t\t\"supported\", hf);\n\t\treturn;\n\t}\n\n\tFM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);\n}\n\nstatic int\nfm10k_dev_tx_init(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint i, ret;\n\tstruct fm10k_tx_queue *txq;\n\tuint64_t base_addr;\n\tuint32_t size;\n\n\t/* Disable TXINT to avoid possible interrupt */\n\tfor (i = 0; i < hw->mac.max_queues; i++)\n\t\tFM10K_WRITE_REG(hw, FM10K_TXINT(i),\n\t\t\t\t3 << FM10K_TXINT_TIMER_SHIFT);\n\n\t/* Setup TX queue */\n\tfor (i = 0; i < dev->data->nb_tx_queues; ++i) {\n\t\ttxq = dev->data->tx_queues[i];\n\t\tbase_addr = txq->hw_ring_phys_addr;\n\t\tsize = txq->nb_desc * sizeof(struct fm10k_tx_desc);\n\n\t\t/* disable queue to avoid issues while updating state */\n\t\tret = tx_queue_disable(hw, i);\n\t\tif (ret) {\n\t\t\tPMD_INIT_LOG(ERR, \"failed to disable queue %d\", i);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* set location and size for descriptor ring */\n\t\tFM10K_WRITE_REG(hw, FM10K_TDBAL(i),\n\t\t\t\tbase_addr & UINT64_LOWER_32BITS_MASK);\n\t\tFM10K_WRITE_REG(hw, FM10K_TDBAH(i),\n\t\t\t\tbase_addr >> (CHAR_BIT * sizeof(uint32_t)));\n\t\tFM10K_WRITE_REG(hw, FM10K_TDLEN(i), size);\n\t}\n\treturn 0;\n}\n\nstatic int\nfm10k_dev_rx_init(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint i, ret;\n\tstruct fm10k_rx_queue *rxq;\n\tuint64_t base_addr;\n\tuint32_t size;\n\tuint32_t rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;\n\tuint16_t buf_size;\n\n\t/* Disable RXINT to avoid possible interrupt */\n\tfor (i = 0; i < hw->mac.max_queues; i++)\n\t\tFM10K_WRITE_REG(hw, FM10K_RXINT(i),\n\t\t\t\t3 << FM10K_RXINT_TIMER_SHIFT);\n\n\t/* Setup RX queues */\n\tfor (i = 0; i < dev->data->nb_rx_queues; ++i) {\n\t\trxq = dev->data->rx_queues[i];\n\t\tbase_addr = rxq->hw_ring_phys_addr;\n\t\tsize = rxq->nb_desc * sizeof(union fm10k_rx_desc);\n\n\t\t/* disable queue to avoid issues while updating state */\n\t\tret = rx_queue_disable(hw, i);\n\t\tif (ret) {\n\t\t\tPMD_INIT_LOG(ERR, \"failed to disable queue %d\", i);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Setup the Base and Length of the Rx Descriptor Ring */\n\t\tFM10K_WRITE_REG(hw, FM10K_RDBAL(i),\n\t\t\t\tbase_addr & UINT64_LOWER_32BITS_MASK);\n\t\tFM10K_WRITE_REG(hw, FM10K_RDBAH(i),\n\t\t\t\tbase_addr >> (CHAR_BIT * sizeof(uint32_t)));\n\t\tFM10K_WRITE_REG(hw, FM10K_RDLEN(i), size);\n\n\t\t/* Configure the Rx buffer size for one buff without split */\n\t\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -\n\t\t\tRTE_PKTMBUF_HEADROOM);\n\t\t/* As RX buffer is aligned to 512B within mbuf, some bytes are\n\t\t * reserved for this purpose, and the worst case could be 511B.\n\t\t * But SRR reg assumes all buffers have the same size. In order\n\t\t * to fill the gap, we'll have to consider the worst case and\n\t\t * assume 512B is reserved. If we don't do so, it's possible\n\t\t * for HW to overwrite data to next mbuf.\n\t\t */\n\t\tbuf_size -= FM10K_RX_DATABUF_ALIGN;\n\n\t\tFM10K_WRITE_REG(hw, FM10K_SRRCTL(i),\n\t\t\t\tbuf_size >> FM10K_SRRCTL_BSIZEPKT_SHIFT);\n\n\t\t/* It adds dual VLAN length for supporting dual VLAN */\n\t\tif ((dev->data->dev_conf.rxmode.max_rx_pkt_len +\n\t\t\t\t2 * FM10K_VLAN_TAG_SIZE) > buf_size ||\n\t\t\tdev->data->dev_conf.rxmode.enable_scatter) {\n\t\t\tuint32_t reg;\n\t\t\tdev->data->scattered_rx = 1;\n\t\t\tdev->rx_pkt_burst = fm10k_recv_scattered_pkts;\n\t\t\treg = FM10K_READ_REG(hw, FM10K_SRRCTL(i));\n\t\t\treg |= FM10K_SRRCTL_BUFFER_CHAINING_EN;\n\t\t\tFM10K_WRITE_REG(hw, FM10K_SRRCTL(i), reg);\n\t\t}\n\n\t\t/* Enable drop on empty, it's RO for VF */\n\t\tif (hw->mac.type == fm10k_mac_pf && rxq->drop_en)\n\t\t\trxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;\n\n\t\tFM10K_WRITE_REG(hw, FM10K_RXDCTL(i), rxdctl);\n\t\tFM10K_WRITE_FLUSH(hw);\n\t}\n\n\t/* Configure RSS if applicable */\n\tfm10k_dev_mq_rx_configure(dev);\n\treturn 0;\n}\n\nstatic int\nfm10k_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint err = -1;\n\tuint32_t reg;\n\tstruct fm10k_rx_queue *rxq;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rx_queue_id < dev->data->nb_rx_queues) {\n\t\trxq = dev->data->rx_queues[rx_queue_id];\n\t\terr = rx_queue_reset(rxq);\n\t\tif (err == -ENOMEM) {\n\t\t\tPMD_INIT_LOG(ERR, \"Failed to alloc memory : %d\", err);\n\t\t\treturn err;\n\t\t} else if (err == -EINVAL) {\n\t\t\tPMD_INIT_LOG(ERR, \"Invalid buffer address alignment :\"\n\t\t\t\t\" %d\", err);\n\t\t\treturn err;\n\t\t}\n\n\t\t/* Setup the HW Rx Head and Tail Descriptor Pointers\n\t\t * Note: this must be done AFTER the queue is enabled on real\n\t\t * hardware, but BEFORE the queue is enabled when using the\n\t\t * emulation platform. Do it in both places for now and remove\n\t\t * this comment and the following two register writes when the\n\t\t * emulation platform is no longer being used.\n\t\t */\n\t\tFM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);\n\t\tFM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);\n\n\t\t/* Set PF ownership flag for PF devices */\n\t\treg = FM10K_READ_REG(hw, FM10K_RXQCTL(rx_queue_id));\n\t\tif (hw->mac.type == fm10k_mac_pf)\n\t\t\treg |= FM10K_RXQCTL_PF;\n\t\treg |= FM10K_RXQCTL_ENABLE;\n\t\t/* enable RX queue */\n\t\tFM10K_WRITE_REG(hw, FM10K_RXQCTL(rx_queue_id), reg);\n\t\tFM10K_WRITE_FLUSH(hw);\n\n\t\t/* Setup the HW Rx Head and Tail Descriptor Pointers\n\t\t * Note: this must be done AFTER the queue is enabled\n\t\t */\n\t\tFM10K_WRITE_REG(hw, FM10K_RDH(rx_queue_id), 0);\n\t\tFM10K_WRITE_REG(hw, FM10K_RDT(rx_queue_id), rxq->nb_desc - 1);\n\t}\n\n\treturn err;\n}\n\nstatic int\nfm10k_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rx_queue_id < dev->data->nb_rx_queues) {\n\t\t/* Disable RX queue */\n\t\trx_queue_disable(hw, rx_queue_id);\n\n\t\t/* Free mbuf and clean HW ring */\n\t\trx_queue_clean(dev->data->rx_queues[rx_queue_id]);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nfm10k_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\t/** @todo - this should be defined in the shared code */\n#define FM10K_TXDCTL_WRITE_BACK_MIN_DELAY\t0x00010000\n\tuint32_t txdctl = FM10K_TXDCTL_WRITE_BACK_MIN_DELAY;\n\tint err = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (tx_queue_id < dev->data->nb_tx_queues) {\n\t\ttx_queue_reset(dev->data->tx_queues[tx_queue_id]);\n\n\t\t/* reset head and tail pointers */\n\t\tFM10K_WRITE_REG(hw, FM10K_TDH(tx_queue_id), 0);\n\t\tFM10K_WRITE_REG(hw, FM10K_TDT(tx_queue_id), 0);\n\n\t\t/* enable TX queue */\n\t\tFM10K_WRITE_REG(hw, FM10K_TXDCTL(tx_queue_id),\n\t\t\t\t\tFM10K_TXDCTL_ENABLE | txdctl);\n\t\tFM10K_WRITE_FLUSH(hw);\n\t} else\n\t\terr = -1;\n\n\treturn err;\n}\n\nstatic int\nfm10k_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (tx_queue_id < dev->data->nb_tx_queues) {\n\t\ttx_queue_disable(hw, tx_queue_id);\n\t\ttx_queue_clean(dev->data->tx_queues[tx_queue_id]);\n\t}\n\n\treturn 0;\n}\n\nstatic inline int fm10k_glort_valid(struct fm10k_hw *hw)\n{\n\treturn ((hw->mac.dglort_map & FM10K_DGLORTMAP_NONE)\n\t\t!= FM10K_DGLORTMAP_NONE);\n}\n\nstatic void\nfm10k_dev_promiscuous_enable(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint status;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* Return if it didn't acquire valid glort range */\n\tif (!fm10k_glort_valid(hw))\n\t\treturn;\n\n\tfm10k_mbx_lock(hw);\n\tstatus = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,\n\t\t\t\tFM10K_XCAST_MODE_PROMISC);\n\tfm10k_mbx_unlock(hw);\n\n\tif (status != FM10K_SUCCESS)\n\t\tPMD_INIT_LOG(ERR, \"Failed to enable promiscuous mode\");\n}\n\nstatic void\nfm10k_dev_promiscuous_disable(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint8_t mode;\n\tint status;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* Return if it didn't acquire valid glort range */\n\tif (!fm10k_glort_valid(hw))\n\t\treturn;\n\n\tif (dev->data->all_multicast == 1)\n\t\tmode = FM10K_XCAST_MODE_ALLMULTI;\n\telse\n\t\tmode = FM10K_XCAST_MODE_NONE;\n\n\tfm10k_mbx_lock(hw);\n\tstatus = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,\n\t\t\t\tmode);\n\tfm10k_mbx_unlock(hw);\n\n\tif (status != FM10K_SUCCESS)\n\t\tPMD_INIT_LOG(ERR, \"Failed to disable promiscuous mode\");\n}\n\nstatic void\nfm10k_dev_allmulticast_enable(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint status;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* Return if it didn't acquire valid glort range */\n\tif (!fm10k_glort_valid(hw))\n\t\treturn;\n\n\t/* If promiscuous mode is enabled, it doesn't make sense to enable\n\t * allmulticast and disable promiscuous since fm10k only can select\n\t * one of the modes.\n\t */\n\tif (dev->data->promiscuous) {\n\t\tPMD_INIT_LOG(INFO, \"Promiscuous mode is enabled, \"\\\n\t\t\t\"needn't enable allmulticast\");\n\t\treturn;\n\t}\n\n\tfm10k_mbx_lock(hw);\n\tstatus = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,\n\t\t\t\tFM10K_XCAST_MODE_ALLMULTI);\n\tfm10k_mbx_unlock(hw);\n\n\tif (status != FM10K_SUCCESS)\n\t\tPMD_INIT_LOG(ERR, \"Failed to enable allmulticast mode\");\n}\n\nstatic void\nfm10k_dev_allmulticast_disable(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint status;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* Return if it didn't acquire valid glort range */\n\tif (!fm10k_glort_valid(hw))\n\t\treturn;\n\n\tif (dev->data->promiscuous) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to disable allmulticast mode \"\\\n\t\t\t\"since promisc mode is enabled\");\n\t\treturn;\n\t}\n\n\tfm10k_mbx_lock(hw);\n\t/* Change mode to unicast mode */\n\tstatus = hw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,\n\t\t\t\tFM10K_XCAST_MODE_NONE);\n\tfm10k_mbx_unlock(hw);\n\n\tif (status != FM10K_SUCCESS)\n\t\tPMD_INIT_LOG(ERR, \"Failed to disable allmulticast mode\");\n}\n\n/* fls = find last set bit = 32 minus the number of leading zeros */\n#ifndef fls\n#define fls(x) (((x) == 0) ? 0 : (32 - __builtin_clz((x))))\n#endif\n#define BSIZEPKT_ROUNDUP ((1 << FM10K_SRRCTL_BSIZEPKT_SHIFT) - 1)\nstatic int\nfm10k_dev_start(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint i, diag;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* stop, init, then start the hw */\n\tdiag = fm10k_stop_hw(hw);\n\tif (diag != FM10K_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Hardware stop failed: %d\", diag);\n\t\treturn -EIO;\n\t}\n\n\tdiag = fm10k_init_hw(hw);\n\tif (diag != FM10K_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Hardware init failed: %d\", diag);\n\t\treturn -EIO;\n\t}\n\n\tdiag = fm10k_start_hw(hw);\n\tif (diag != FM10K_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Hardware start failed: %d\", diag);\n\t\treturn -EIO;\n\t}\n\n\tdiag = fm10k_dev_tx_init(dev);\n\tif (diag) {\n\t\tPMD_INIT_LOG(ERR, \"TX init failed: %d\", diag);\n\t\treturn diag;\n\t}\n\n\tdiag = fm10k_dev_rx_init(dev);\n\tif (diag) {\n\t\tPMD_INIT_LOG(ERR, \"RX init failed: %d\", diag);\n\t\treturn diag;\n\t}\n\n\tif (hw->mac.type == fm10k_mac_pf) {\n\t\t/* Establish only VSI 0 as valid */\n\t\tFM10K_WRITE_REG(hw, FM10K_DGLORTMAP(0), FM10K_DGLORTMAP_ANY);\n\n\t\t/* Configure RSS bits used in RETA table */\n\t\tFM10K_WRITE_REG(hw, FM10K_DGLORTDEC(0),\n\t\t\t\tfls(dev->data->nb_rx_queues - 1) <<\n\t\t\t\tFM10K_DGLORTDEC_RSSLENGTH_SHIFT);\n\n\t\t/* Invalidate all other GLORT entries */\n\t\tfor (i = 1; i < FM10K_DGLORT_COUNT; i++)\n\t\t\tFM10K_WRITE_REG(hw, FM10K_DGLORTMAP(i),\n\t\t\t\t\tFM10K_DGLORTMAP_NONE);\n\t}\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tstruct fm10k_rx_queue *rxq;\n\t\trxq = dev->data->rx_queues[i];\n\n\t\tif (rxq->rx_deferred_start)\n\t\t\tcontinue;\n\t\tdiag = fm10k_dev_rx_queue_start(dev, i);\n\t\tif (diag != 0) {\n\t\t\tint j;\n\t\t\tfor (j = 0; j < i; ++j)\n\t\t\t\trx_queue_clean(dev->data->rx_queues[j]);\n\t\t\treturn diag;\n\t\t}\n\t}\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tstruct fm10k_tx_queue *txq;\n\t\ttxq = dev->data->tx_queues[i];\n\n\t\tif (txq->tx_deferred_start)\n\t\t\tcontinue;\n\t\tdiag = fm10k_dev_tx_queue_start(dev, i);\n\t\tif (diag != 0) {\n\t\t\tint j;\n\t\t\tfor (j = 0; j < i; ++j)\n\t\t\t\ttx_queue_clean(dev->data->tx_queues[j]);\n\t\t\tfor (j = 0; j < dev->data->nb_rx_queues; ++j)\n\t\t\t\trx_queue_clean(dev->data->rx_queues[j]);\n\t\t\treturn diag;\n\t\t}\n\t}\n\n\t/* Update default vlan */\n\tif (hw->mac.default_vid && hw->mac.default_vid <= ETHER_MAX_VLAN_ID)\n\t\tfm10k_vlan_filter_set(dev, hw->mac.default_vid, true);\n\n\treturn 0;\n}\n\nstatic void\nfm10k_dev_stop(struct rte_eth_dev *dev)\n{\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (dev->data->tx_queues)\n\t\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n\t\t\tfm10k_dev_tx_queue_stop(dev, i);\n\n\tif (dev->data->rx_queues)\n\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n\t\t\tfm10k_dev_rx_queue_stop(dev, i);\n}\n\nstatic void\nfm10k_dev_queue_release(struct rte_eth_dev *dev)\n{\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (dev->data->tx_queues) {\n\t\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n\t\t\tfm10k_tx_queue_release(dev->data->tx_queues[i]);\n\t}\n\n\tif (dev->data->rx_queues) {\n\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n\t\t\tfm10k_rx_queue_release(dev->data->rx_queues[i]);\n\t}\n}\n\nstatic void\nfm10k_dev_close(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tfm10k_MACVLAN_remove_all(dev);\n\n\t/* Stop mailbox service first */\n\tfm10k_close_mbx_service(hw);\n\tfm10k_dev_stop(dev);\n\tfm10k_dev_queue_release(dev);\n\tfm10k_stop_hw(hw);\n}\n\nstatic int\nfm10k_link_update(struct rte_eth_dev *dev,\n\t__rte_unused int wait_to_complete)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* The host-interface link is always up. The speed is ~50Gbps per Gen3\n\t * x8 PCIe interface. For now, we leave the speed undefined since there\n\t * is no 50Gbps Ethernet. */\n\tdev->data->dev_link.link_speed = 0;\n\tdev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;\n\tdev->data->dev_link.link_status = 1;\n\n\treturn 0;\n}\n\nstatic void\nfm10k_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tuint64_t ipackets, opackets, ibytes, obytes;\n\tstruct fm10k_hw *hw =\n\t\tFM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct fm10k_hw_stats *hw_stats =\n\t\tFM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tfm10k_update_hw_stats(hw, hw_stats);\n\n\tipackets = opackets = ibytes = obytes = 0;\n\tfor (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&\n\t\t(i < hw->mac.max_queues); ++i) {\n\t\tstats->q_ipackets[i] = hw_stats->q[i].rx_packets.count;\n\t\tstats->q_opackets[i] = hw_stats->q[i].tx_packets.count;\n\t\tstats->q_ibytes[i] = hw_stats->q[i].rx_bytes.count;\n\t\tstats->q_obytes[i] = hw_stats->q[i].tx_bytes.count;\n\t\tipackets += stats->q_ipackets[i];\n\t\topackets += stats->q_opackets[i];\n\t\tibytes += stats->q_ibytes[i];\n\t\tobytes += stats->q_obytes[i];\n\t}\n\tstats->ipackets = ipackets;\n\tstats->opackets = opackets;\n\tstats->ibytes = ibytes;\n\tstats->obytes = obytes;\n}\n\nstatic void\nfm10k_stats_reset(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct fm10k_hw_stats *hw_stats =\n\t\tFM10K_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tmemset(hw_stats, 0, sizeof(*hw_stats));\n\tfm10k_rebind_hw_stats(hw, hw_stats);\n}\n\nstatic void\nfm10k_dev_infos_get(struct rte_eth_dev *dev,\n\tstruct rte_eth_dev_info *dev_info)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tdev_info->min_rx_bufsize = FM10K_MIN_RX_BUF_SIZE;\n\tdev_info->max_rx_pktlen = FM10K_MAX_PKT_SIZE;\n\tdev_info->max_rx_queues = hw->mac.max_queues;\n\tdev_info->max_tx_queues = hw->mac.max_queues;\n\tdev_info->max_mac_addrs = FM10K_MAX_MACADDR_NUM;\n\tdev_info->max_hash_mac_addrs = 0;\n\tdev_info->max_vfs = dev->pci_dev->max_vfs;\n\tdev_info->max_vmdq_pools = ETH_64_POOLS;\n\tdev_info->rx_offload_capa =\n\t\tDEV_RX_OFFLOAD_VLAN_STRIP |\n\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n\t\tDEV_RX_OFFLOAD_TCP_CKSUM;\n\tdev_info->tx_offload_capa =\n\t\tDEV_TX_OFFLOAD_VLAN_INSERT |\n\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n\t\tDEV_TX_OFFLOAD_TCP_CKSUM;\n\n\tdev_info->hash_key_size = FM10K_RSSRK_SIZE * sizeof(uint32_t);\n\tdev_info->reta_size = FM10K_MAX_RSS_INDICES;\n\n\tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n\t\t.rx_thresh = {\n\t\t\t.pthresh = FM10K_DEFAULT_RX_PTHRESH,\n\t\t\t.hthresh = FM10K_DEFAULT_RX_HTHRESH,\n\t\t\t.wthresh = FM10K_DEFAULT_RX_WTHRESH,\n\t\t},\n\t\t.rx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(0),\n\t\t.rx_drop_en = 0,\n\t};\n\n\tdev_info->default_txconf = (struct rte_eth_txconf) {\n\t\t.tx_thresh = {\n\t\t\t.pthresh = FM10K_DEFAULT_TX_PTHRESH,\n\t\t\t.hthresh = FM10K_DEFAULT_TX_HTHRESH,\n\t\t\t.wthresh = FM10K_DEFAULT_TX_WTHRESH,\n\t\t},\n\t\t.tx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(0),\n\t\t.tx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(0),\n\t\t.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |\n\t\t\t\tETH_TXQ_FLAGS_NOOFFLOADS,\n\t};\n\n}\n\nstatic int\nfm10k_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n{\n\ts32 result;\n\tuint16_t mac_num = 0;\n\tuint32_t vid_idx, vid_bit, mac_index;\n\tstruct fm10k_hw *hw;\n\tstruct fm10k_macvlan_filter_info *macvlan;\n\tstruct rte_eth_dev_data *data = dev->data;\n\n\thw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tmacvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);\n\n\tif (vlan_id > ETH_VLAN_ID_MAX) {\n\t\tPMD_INIT_LOG(ERR, \"Invalid vlan_id: must be < 4096\");\n\t\treturn (-EINVAL);\n\t}\n\n\tvid_idx = FM10K_VFTA_IDX(vlan_id);\n\tvid_bit = FM10K_VFTA_BIT(vlan_id);\n\t/* this VLAN ID is already in the VLAN filter table, return SUCCESS */\n\tif (on && (macvlan->vfta[vid_idx] & vid_bit))\n\t\treturn 0;\n\t/* this VLAN ID is NOT in the VLAN filter table, cannot remove */\n\tif (!on && !(macvlan->vfta[vid_idx] & vid_bit)) {\n\t\tPMD_INIT_LOG(ERR, \"Invalid vlan_id: not existing \"\n\t\t\t\"in the VLAN filter table\");\n\t\treturn (-EINVAL);\n\t}\n\n\tfm10k_mbx_lock(hw);\n\tresult = fm10k_update_vlan(hw, vlan_id, 0, on);\n\tfm10k_mbx_unlock(hw);\n\tif (result != FM10K_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"VLAN update failed: %d\", result);\n\t\treturn (-EIO);\n\t}\n\n\tfor (mac_index = 0; (mac_index < FM10K_MAX_MACADDR_NUM) &&\n\t\t\t(result == FM10K_SUCCESS); mac_index++) {\n\t\tif (is_zero_ether_addr(&data->mac_addrs[mac_index]))\n\t\t\tcontinue;\n\t\tif (mac_num > macvlan->mac_num - 1) {\n\t\t\tPMD_INIT_LOG(ERR, \"MAC address number \"\n\t\t\t\t\t\"not match\");\n\t\t\tbreak;\n\t\t}\n\t\tfm10k_mbx_lock(hw);\n\t\tresult = fm10k_update_uc_addr(hw, hw->mac.dglort_map,\n\t\t\tdata->mac_addrs[mac_index].addr_bytes,\n\t\t\tvlan_id, on, 0);\n\t\tfm10k_mbx_unlock(hw);\n\t\tmac_num++;\n\t}\n\tif (result != FM10K_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"MAC address update failed: %d\", result);\n\t\treturn (-EIO);\n\t}\n\n\tif (on) {\n\t\tmacvlan->vlan_num++;\n\t\tmacvlan->vfta[vid_idx] |= vid_bit;\n\t} else {\n\t\tmacvlan->vlan_num--;\n\t\tmacvlan->vfta[vid_idx] &= ~vid_bit;\n\t}\n\treturn 0;\n}\n\nstatic void\nfm10k_vlan_offload_set(__rte_unused struct rte_eth_dev *dev, int mask)\n{\n\tif (mask & ETH_VLAN_STRIP_MASK) {\n\t\tif (!dev->data->dev_conf.rxmode.hw_vlan_strip)\n\t\t\tPMD_INIT_LOG(ERR, \"VLAN stripping is \"\n\t\t\t\t\t\"always on in fm10k\");\n\t}\n\n\tif (mask & ETH_VLAN_EXTEND_MASK) {\n\t\tif (dev->data->dev_conf.rxmode.hw_vlan_extend)\n\t\t\tPMD_INIT_LOG(ERR, \"VLAN QinQ is not \"\n\t\t\t\t\t\"supported in fm10k\");\n\t}\n\n\tif (mask & ETH_VLAN_FILTER_MASK) {\n\t\tif (!dev->data->dev_conf.rxmode.hw_vlan_filter)\n\t\t\tPMD_INIT_LOG(ERR, \"VLAN filter is always on in fm10k\");\n\t}\n}\n\n/* Add/Remove a MAC address, and update filters */\nstatic void\nfm10k_MAC_filter_set(struct rte_eth_dev *dev, const u8 *mac, bool add)\n{\n\tuint32_t i, j, k;\n\tstruct fm10k_hw *hw;\n\tstruct fm10k_macvlan_filter_info *macvlan;\n\n\thw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tmacvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);\n\n\ti = 0;\n\tfor (j = 0; j < FM10K_VFTA_SIZE; j++) {\n\t\tif (macvlan->vfta[j]) {\n\t\t\tfor (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {\n\t\t\t\tif (macvlan->vfta[j] & (1 << k)) {\n\t\t\t\t\tif (i + 1 > macvlan->vlan_num) {\n\t\t\t\t\t\tPMD_INIT_LOG(ERR, \"vlan number \"\n\t\t\t\t\t\t\t\t\"not match\");\n\t\t\t\t\t\treturn;\n\t\t\t\t\t}\n\t\t\t\t\tfm10k_mbx_lock(hw);\n\t\t\t\t\tfm10k_update_uc_addr(hw,\n\t\t\t\t\t\thw->mac.dglort_map, mac,\n\t\t\t\t\t\tj * FM10K_UINT32_BIT_SIZE + k,\n\t\t\t\t\t\tadd, 0);\n\t\t\t\t\tfm10k_mbx_unlock(hw);\n\t\t\t\t\ti++;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tif (add)\n\t\tmacvlan->mac_num++;\n\telse\n\t\tmacvlan->mac_num--;\n}\n\n/* Add a MAC address, and update filters */\nstatic void\nfm10k_macaddr_add(struct rte_eth_dev *dev,\n\t\t struct ether_addr *mac_addr,\n\t\t __rte_unused uint32_t index,\n\t\t __rte_unused uint32_t pool)\n{\n\tfm10k_MAC_filter_set(dev, mac_addr->addr_bytes, TRUE);\n}\n\n/* Remove a MAC address, and update filters */\nstatic void\nfm10k_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)\n{\n\tstruct rte_eth_dev_data *data = dev->data;\n\n\tif (index < FM10K_MAX_MACADDR_NUM)\n\t\tfm10k_MAC_filter_set(dev, data->mac_addrs[index].addr_bytes,\n\t\t\t\tFALSE);\n}\n\n/* Remove all VLAN and MAC address table entries */\nstatic void\nfm10k_MACVLAN_remove_all(struct rte_eth_dev *dev)\n{\n\tuint32_t j, k;\n\tstruct fm10k_macvlan_filter_info *macvlan;\n\n\tmacvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);\n\tfor (j = 0; j < FM10K_VFTA_SIZE; j++) {\n\t\tif (macvlan->vfta[j]) {\n\t\t\tfor (k = 0; k < FM10K_UINT32_BIT_SIZE; k++) {\n\t\t\t\tif (macvlan->vfta[j] & (1 << k))\n\t\t\t\t\tfm10k_vlan_filter_set(dev,\n\t\t\t\t\t\tj * FM10K_UINT32_BIT_SIZE + k, false);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic inline int\ncheck_nb_desc(uint16_t min, uint16_t max, uint16_t mult, uint16_t request)\n{\n\tif ((request < min) || (request > max) || ((request % mult) != 0))\n\t\treturn -1;\n\telse\n\t\treturn 0;\n}\n\n/*\n * Create a memzone for hardware descriptor rings. Malloc cannot be used since\n * the physical address is required. If the memzone is already created, then\n * this function returns a pointer to the existing memzone.\n */\nstatic inline const struct rte_memzone *\nallocate_hw_ring(const char *driver_name, const char *ring_name,\n\tuint8_t port_id, uint16_t queue_id, int socket_id,\n\tuint32_t size, uint32_t align)\n{\n\tchar name[RTE_MEMZONE_NAMESIZE];\n\tconst struct rte_memzone *mz;\n\n\tsnprintf(name, sizeof(name), \"%s_%s_%d_%d_%d\",\n\t\t driver_name, ring_name, port_id, queue_id, socket_id);\n\n\t/* return the memzone if it already exists */\n\tmz = rte_memzone_lookup(name);\n\tif (mz)\n\t\treturn mz;\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n\treturn rte_memzone_reserve_bounded(name, size, socket_id, 0, align,\n\t\t\t\t\t RTE_PGSIZE_2M);\n#else\n\treturn rte_memzone_reserve_aligned(name, size, socket_id, 0, align);\n#endif\n}\n\nstatic inline int\ncheck_thresh(uint16_t min, uint16_t max, uint16_t div, uint16_t request)\n{\n\tif ((request < min) || (request > max) || ((div % request) != 0))\n\t\treturn -1;\n\telse\n\t\treturn 0;\n}\n\nstatic inline int\nhandle_rxconf(struct fm10k_rx_queue *q, const struct rte_eth_rxconf *conf)\n{\n\tuint16_t rx_free_thresh;\n\n\tif (conf->rx_free_thresh == 0)\n\t\trx_free_thresh = FM10K_RX_FREE_THRESH_DEFAULT(q);\n\telse\n\t\trx_free_thresh = conf->rx_free_thresh;\n\n\t/* make sure the requested threshold satisfies the constraints */\n\tif (check_thresh(FM10K_RX_FREE_THRESH_MIN(q),\n\t\t\tFM10K_RX_FREE_THRESH_MAX(q),\n\t\t\tFM10K_RX_FREE_THRESH_DIV(q),\n\t\t\trx_free_thresh)) {\n\t\tPMD_INIT_LOG(ERR, \"rx_free_thresh (%u) must be \"\n\t\t\t\"less than or equal to %u, \"\n\t\t\t\"greater than or equal to %u, \"\n\t\t\t\"and a divisor of %u\",\n\t\t\trx_free_thresh, FM10K_RX_FREE_THRESH_MAX(q),\n\t\t\tFM10K_RX_FREE_THRESH_MIN(q),\n\t\t\tFM10K_RX_FREE_THRESH_DIV(q));\n\t\treturn (-EINVAL);\n\t}\n\n\tq->alloc_thresh = rx_free_thresh;\n\tq->drop_en = conf->rx_drop_en;\n\tq->rx_deferred_start = conf->rx_deferred_start;\n\n\treturn 0;\n}\n\n/*\n * Hardware requires specific alignment for Rx packet buffers. At\n * least one of the following two conditions must be satisfied.\n * 1. Address is 512B aligned\n * 2. Address is 8B aligned and buffer does not cross 4K boundary.\n *\n * As such, the driver may need to adjust the DMA address within the\n * buffer by up to 512B.\n *\n * return 1 if the element size is valid, otherwise return 0.\n */\nstatic int\nmempool_element_size_valid(struct rte_mempool *mp)\n{\n\tuint32_t min_size;\n\n\t/* elt_size includes mbuf header and headroom */\n\tmin_size = mp->elt_size - sizeof(struct rte_mbuf) -\n\t\t\tRTE_PKTMBUF_HEADROOM;\n\n\t/* account for up to 512B of alignment */\n\tmin_size -= FM10K_RX_DATABUF_ALIGN;\n\n\t/* sanity check for overflow */\n\tif (min_size > mp->elt_size)\n\t\treturn 0;\n\n\t/* size is valid */\n\treturn 1;\n}\n\nstatic int\nfm10k_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,\n\tuint16_t nb_desc, unsigned int socket_id,\n\tconst struct rte_eth_rxconf *conf, struct rte_mempool *mp)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct fm10k_rx_queue *q;\n\tconst struct rte_memzone *mz;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* make sure the mempool element size can account for alignment. */\n\tif (!mempool_element_size_valid(mp)) {\n\t\tPMD_INIT_LOG(ERR, \"Error : Mempool element size is too small\");\n\t\treturn (-EINVAL);\n\t}\n\n\t/* make sure a valid number of descriptors have been requested */\n\tif (check_nb_desc(FM10K_MIN_RX_DESC, FM10K_MAX_RX_DESC,\n\t\t\t\tFM10K_MULT_RX_DESC, nb_desc)) {\n\t\tPMD_INIT_LOG(ERR, \"Number of Rx descriptors (%u) must be \"\n\t\t\t\"less than or equal to %\"PRIu32\", \"\n\t\t\t\"greater than or equal to %u, \"\n\t\t\t\"and a multiple of %u\",\n\t\t\tnb_desc, (uint32_t)FM10K_MAX_RX_DESC, FM10K_MIN_RX_DESC,\n\t\t\tFM10K_MULT_RX_DESC);\n\t\treturn (-EINVAL);\n\t}\n\n\t/*\n\t * if this queue existed already, free the associated memory. The\n\t * queue cannot be reused in case we need to allocate memory on\n\t * different socket than was previously used.\n\t */\n\tif (dev->data->rx_queues[queue_id] != NULL) {\n\t\trx_queue_free(dev->data->rx_queues[queue_id]);\n\t\tdev->data->rx_queues[queue_id] = NULL;\n\t}\n\n\t/* allocate memory for the queue structure */\n\tq = rte_zmalloc_socket(\"fm10k\", sizeof(*q), RTE_CACHE_LINE_SIZE,\n\t\t\t\tsocket_id);\n\tif (q == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Cannot allocate queue structure\");\n\t\treturn (-ENOMEM);\n\t}\n\n\t/* setup queue */\n\tq->mp = mp;\n\tq->nb_desc = nb_desc;\n\tq->port_id = dev->data->port_id;\n\tq->queue_id = queue_id;\n\tq->tail_ptr = (volatile uint32_t *)\n\t\t&((uint32_t *)hw->hw_addr)[FM10K_RDT(queue_id)];\n\tif (handle_rxconf(q, conf))\n\t\treturn (-EINVAL);\n\n\t/* allocate memory for the software ring */\n\tq->sw_ring = rte_zmalloc_socket(\"fm10k sw ring\",\n\t\t\t\t\tnb_desc * sizeof(struct rte_mbuf *),\n\t\t\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (q->sw_ring == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Cannot allocate software ring\");\n\t\trte_free(q);\n\t\treturn (-ENOMEM);\n\t}\n\n\t/*\n\t * allocate memory for the hardware descriptor ring. A memzone large\n\t * enough to hold the maximum ring size is requested to allow for\n\t * resizing in later calls to the queue setup function.\n\t */\n\tmz = allocate_hw_ring(dev->driver->pci_drv.name, \"rx_ring\",\n\t\t\t\tdev->data->port_id, queue_id, socket_id,\n\t\t\t\tFM10K_MAX_RX_RING_SZ, FM10K_ALIGN_RX_DESC);\n\tif (mz == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Cannot allocate hardware ring\");\n\t\trte_free(q->sw_ring);\n\t\trte_free(q);\n\t\treturn (-ENOMEM);\n\t}\n\tq->hw_ring = mz->addr;\n#ifdef RTE_LIBRTE_XEN_DOM0\n\tq->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);\n#else\n\tq->hw_ring_phys_addr = mz->phys_addr;\n#endif\n\n\tdev->data->rx_queues[queue_id] = q;\n\treturn 0;\n}\n\nstatic void\nfm10k_rx_queue_release(void *queue)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\trx_queue_free(queue);\n}\n\nstatic inline int\nhandle_txconf(struct fm10k_tx_queue *q, const struct rte_eth_txconf *conf)\n{\n\tuint16_t tx_free_thresh;\n\tuint16_t tx_rs_thresh;\n\n\t/* constraint MACROs require that tx_free_thresh is configured\n\t * before tx_rs_thresh */\n\tif (conf->tx_free_thresh == 0)\n\t\ttx_free_thresh = FM10K_TX_FREE_THRESH_DEFAULT(q);\n\telse\n\t\ttx_free_thresh = conf->tx_free_thresh;\n\n\t/* make sure the requested threshold satisfies the constraints */\n\tif (check_thresh(FM10K_TX_FREE_THRESH_MIN(q),\n\t\t\tFM10K_TX_FREE_THRESH_MAX(q),\n\t\t\tFM10K_TX_FREE_THRESH_DIV(q),\n\t\t\ttx_free_thresh)) {\n\t\tPMD_INIT_LOG(ERR, \"tx_free_thresh (%u) must be \"\n\t\t\t\"less than or equal to %u, \"\n\t\t\t\"greater than or equal to %u, \"\n\t\t\t\"and a divisor of %u\",\n\t\t\ttx_free_thresh, FM10K_TX_FREE_THRESH_MAX(q),\n\t\t\tFM10K_TX_FREE_THRESH_MIN(q),\n\t\t\tFM10K_TX_FREE_THRESH_DIV(q));\n\t\treturn (-EINVAL);\n\t}\n\n\tq->free_thresh = tx_free_thresh;\n\n\tif (conf->tx_rs_thresh == 0)\n\t\ttx_rs_thresh = FM10K_TX_RS_THRESH_DEFAULT(q);\n\telse\n\t\ttx_rs_thresh = conf->tx_rs_thresh;\n\n\tq->tx_deferred_start = conf->tx_deferred_start;\n\n\t/* make sure the requested threshold satisfies the constraints */\n\tif (check_thresh(FM10K_TX_RS_THRESH_MIN(q),\n\t\t\tFM10K_TX_RS_THRESH_MAX(q),\n\t\t\tFM10K_TX_RS_THRESH_DIV(q),\n\t\t\ttx_rs_thresh)) {\n\t\tPMD_INIT_LOG(ERR, \"tx_rs_thresh (%u) must be \"\n\t\t\t\"less than or equal to %u, \"\n\t\t\t\"greater than or equal to %u, \"\n\t\t\t\"and a divisor of %u\",\n\t\t\ttx_rs_thresh, FM10K_TX_RS_THRESH_MAX(q),\n\t\t\tFM10K_TX_RS_THRESH_MIN(q),\n\t\t\tFM10K_TX_RS_THRESH_DIV(q));\n\t\treturn (-EINVAL);\n\t}\n\n\tq->rs_thresh = tx_rs_thresh;\n\n\treturn 0;\n}\n\nstatic int\nfm10k_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_id,\n\tuint16_t nb_desc, unsigned int socket_id,\n\tconst struct rte_eth_txconf *conf)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct fm10k_tx_queue *q;\n\tconst struct rte_memzone *mz;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* make sure a valid number of descriptors have been requested */\n\tif (check_nb_desc(FM10K_MIN_TX_DESC, FM10K_MAX_TX_DESC,\n\t\t\t\tFM10K_MULT_TX_DESC, nb_desc)) {\n\t\tPMD_INIT_LOG(ERR, \"Number of Tx descriptors (%u) must be \"\n\t\t\t\"less than or equal to %\"PRIu32\", \"\n\t\t\t\"greater than or equal to %u, \"\n\t\t\t\"and a multiple of %u\",\n\t\t\tnb_desc, (uint32_t)FM10K_MAX_TX_DESC, FM10K_MIN_TX_DESC,\n\t\t\tFM10K_MULT_TX_DESC);\n\t\treturn (-EINVAL);\n\t}\n\n\t/*\n\t * if this queue existed already, free the associated memory. The\n\t * queue cannot be reused in case we need to allocate memory on\n\t * different socket than was previously used.\n\t */\n\tif (dev->data->tx_queues[queue_id] != NULL) {\n\t\ttx_queue_free(dev->data->tx_queues[queue_id]);\n\t\tdev->data->tx_queues[queue_id] = NULL;\n\t}\n\n\t/* allocate memory for the queue structure */\n\tq = rte_zmalloc_socket(\"fm10k\", sizeof(*q), RTE_CACHE_LINE_SIZE,\n\t\t\t\tsocket_id);\n\tif (q == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Cannot allocate queue structure\");\n\t\treturn (-ENOMEM);\n\t}\n\n\t/* setup queue */\n\tq->nb_desc = nb_desc;\n\tq->port_id = dev->data->port_id;\n\tq->queue_id = queue_id;\n\tq->tail_ptr = (volatile uint32_t *)\n\t\t&((uint32_t *)hw->hw_addr)[FM10K_TDT(queue_id)];\n\tif (handle_txconf(q, conf))\n\t\treturn (-EINVAL);\n\n\t/* allocate memory for the software ring */\n\tq->sw_ring = rte_zmalloc_socket(\"fm10k sw ring\",\n\t\t\t\t\tnb_desc * sizeof(struct rte_mbuf *),\n\t\t\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (q->sw_ring == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Cannot allocate software ring\");\n\t\trte_free(q);\n\t\treturn (-ENOMEM);\n\t}\n\n\t/*\n\t * allocate memory for the hardware descriptor ring. A memzone large\n\t * enough to hold the maximum ring size is requested to allow for\n\t * resizing in later calls to the queue setup function.\n\t */\n\tmz = allocate_hw_ring(dev->driver->pci_drv.name, \"tx_ring\",\n\t\t\t\tdev->data->port_id, queue_id, socket_id,\n\t\t\t\tFM10K_MAX_TX_RING_SZ, FM10K_ALIGN_TX_DESC);\n\tif (mz == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Cannot allocate hardware ring\");\n\t\trte_free(q->sw_ring);\n\t\trte_free(q);\n\t\treturn (-ENOMEM);\n\t}\n\tq->hw_ring = mz->addr;\n#ifdef RTE_LIBRTE_XEN_DOM0\n\tq->hw_ring_phys_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);\n#else\n\tq->hw_ring_phys_addr = mz->phys_addr;\n#endif\n\n\t/*\n\t * allocate memory for the RS bit tracker. Enough slots to hold the\n\t * descriptor index for each RS bit needing to be set are required.\n\t */\n\tq->rs_tracker.list = rte_zmalloc_socket(\"fm10k rs tracker\",\n\t\t\t\t((nb_desc + 1) / q->rs_thresh) *\n\t\t\t\tsizeof(uint16_t),\n\t\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (q->rs_tracker.list == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Cannot allocate RS bit tracker\");\n\t\trte_free(q->sw_ring);\n\t\trte_free(q);\n\t\treturn (-ENOMEM);\n\t}\n\n\tdev->data->tx_queues[queue_id] = q;\n\treturn 0;\n}\n\nstatic void\nfm10k_tx_queue_release(void *queue)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\ttx_queue_free(queue);\n}\n\nstatic int\nfm10k_reta_update(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\tuint16_t reta_size)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint16_t i, j, idx, shift;\n\tuint8_t mask;\n\tuint32_t reta;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (reta_size > FM10K_MAX_RSS_INDICES) {\n\t\tPMD_INIT_LOG(ERR, \"The size of hash lookup table configured \"\n\t\t\t\"(%d) doesn't match the number hardware can supported \"\n\t\t\t\"(%d)\", reta_size, FM10K_MAX_RSS_INDICES);\n\t\treturn -EINVAL;\n\t}\n\n\t/*\n\t * Update Redirection Table RETA[n], n=0..31. The redirection table has\n\t * 128-entries in 32 registers\n\t */\n\tfor (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {\n\t\tidx = i / RTE_RETA_GROUP_SIZE;\n\t\tshift = i % RTE_RETA_GROUP_SIZE;\n\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n\t\t\t\tBIT_MASK_PER_UINT32);\n\t\tif (mask == 0)\n\t\t\tcontinue;\n\n\t\treta = 0;\n\t\tif (mask != BIT_MASK_PER_UINT32)\n\t\t\treta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));\n\n\t\tfor (j = 0; j < CHARS_PER_UINT32; j++) {\n\t\t\tif (mask & (0x1 << j)) {\n\t\t\t\tif (mask != 0xF)\n\t\t\t\t\treta &= ~(UINT8_MAX << CHAR_BIT * j);\n\t\t\t\treta |= reta_conf[idx].reta[shift + j] <<\n\t\t\t\t\t\t(CHAR_BIT * j);\n\t\t\t}\n\t\t}\n\t\tFM10K_WRITE_REG(hw, FM10K_RETA(0, i >> 2), reta);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nfm10k_reta_query(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\tuint16_t reta_size)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint16_t i, j, idx, shift;\n\tuint8_t mask;\n\tuint32_t reta;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (reta_size < FM10K_MAX_RSS_INDICES) {\n\t\tPMD_INIT_LOG(ERR, \"The size of hash lookup table configured \"\n\t\t\t\"(%d) doesn't match the number hardware can supported \"\n\t\t\t\"(%d)\", reta_size, FM10K_MAX_RSS_INDICES);\n\t\treturn -EINVAL;\n\t}\n\n\t/*\n\t * Read Redirection Table RETA[n], n=0..31. The redirection table has\n\t * 128-entries in 32 registers\n\t */\n\tfor (i = 0; i < FM10K_MAX_RSS_INDICES; i += CHARS_PER_UINT32) {\n\t\tidx = i / RTE_RETA_GROUP_SIZE;\n\t\tshift = i % RTE_RETA_GROUP_SIZE;\n\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n\t\t\t\tBIT_MASK_PER_UINT32);\n\t\tif (mask == 0)\n\t\t\tcontinue;\n\n\t\treta = FM10K_READ_REG(hw, FM10K_RETA(0, i >> 2));\n\t\tfor (j = 0; j < CHARS_PER_UINT32; j++) {\n\t\t\tif (mask & (0x1 << j))\n\t\t\t\treta_conf[idx].reta[shift + j] = ((reta >>\n\t\t\t\t\tCHAR_BIT * j) & UINT8_MAX);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\nfm10k_rss_hash_update(struct rte_eth_dev *dev,\n\tstruct rte_eth_rss_conf *rss_conf)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t *key = (uint32_t *)rss_conf->rss_key;\n\tuint32_t mrqc;\n\tuint64_t hf = rss_conf->rss_hf;\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *\n\t\tFM10K_RSSRK_ENTRIES_PER_REG)\n\t\treturn -EINVAL;\n\n\tif (hf == 0)\n\t\treturn -EINVAL;\n\n\tmrqc = 0;\n\tmrqc |= (hf & ETH_RSS_IPV4) ? FM10K_MRQC_IPV4 : 0;\n\tmrqc |= (hf & ETH_RSS_IPV6) ? FM10K_MRQC_IPV6 : 0;\n\tmrqc |= (hf & ETH_RSS_IPV6_EX) ? FM10K_MRQC_IPV6 : 0;\n\tmrqc |= (hf & ETH_RSS_NONFRAG_IPV4_TCP) ? FM10K_MRQC_TCP_IPV4 : 0;\n\tmrqc |= (hf & ETH_RSS_NONFRAG_IPV6_TCP) ? FM10K_MRQC_TCP_IPV6 : 0;\n\tmrqc |= (hf & ETH_RSS_IPV6_TCP_EX) ? FM10K_MRQC_TCP_IPV6 : 0;\n\tmrqc |= (hf & ETH_RSS_NONFRAG_IPV4_UDP) ? FM10K_MRQC_UDP_IPV4 : 0;\n\tmrqc |= (hf & ETH_RSS_NONFRAG_IPV6_UDP) ? FM10K_MRQC_UDP_IPV6 : 0;\n\tmrqc |= (hf & ETH_RSS_IPV6_UDP_EX) ? FM10K_MRQC_UDP_IPV6 : 0;\n\n\t/* If the mapping doesn't fit any supported, return */\n\tif (mrqc == 0)\n\t\treturn -EINVAL;\n\n\tif (key != NULL)\n\t\tfor (i = 0; i < FM10K_RSSRK_SIZE; ++i)\n\t\t\tFM10K_WRITE_REG(hw, FM10K_RSSRK(0, i), key[i]);\n\n\tFM10K_WRITE_REG(hw, FM10K_MRQC(0), mrqc);\n\n\treturn 0;\n}\n\nstatic int\nfm10k_rss_hash_conf_get(struct rte_eth_dev *dev,\n\tstruct rte_eth_rss_conf *rss_conf)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t *key = (uint32_t *)rss_conf->rss_key;\n\tuint32_t mrqc;\n\tuint64_t hf;\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rss_conf->rss_key_len < FM10K_RSSRK_SIZE *\n\t\t\t\tFM10K_RSSRK_ENTRIES_PER_REG)\n\t\treturn -EINVAL;\n\n\tif (key != NULL)\n\t\tfor (i = 0; i < FM10K_RSSRK_SIZE; ++i)\n\t\t\tkey[i] = FM10K_READ_REG(hw, FM10K_RSSRK(0, i));\n\n\tmrqc = FM10K_READ_REG(hw, FM10K_MRQC(0));\n\thf = 0;\n\thf |= (mrqc & FM10K_MRQC_IPV4) ? ETH_RSS_IPV4 : 0;\n\thf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6 : 0;\n\thf |= (mrqc & FM10K_MRQC_IPV6) ? ETH_RSS_IPV6_EX : 0;\n\thf |= (mrqc & FM10K_MRQC_TCP_IPV4) ? ETH_RSS_NONFRAG_IPV4_TCP : 0;\n\thf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_NONFRAG_IPV6_TCP : 0;\n\thf |= (mrqc & FM10K_MRQC_TCP_IPV6) ? ETH_RSS_IPV6_TCP_EX : 0;\n\thf |= (mrqc & FM10K_MRQC_UDP_IPV4) ? ETH_RSS_NONFRAG_IPV4_UDP : 0;\n\thf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_NONFRAG_IPV6_UDP : 0;\n\thf |= (mrqc & FM10K_MRQC_UDP_IPV6) ? ETH_RSS_IPV6_UDP_EX : 0;\n\n\trss_conf->rss_hf = hf;\n\n\treturn 0;\n}\n\nstatic void\nfm10k_dev_enable_intr_pf(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t int_map = FM10K_INT_MAP_IMMEDIATE;\n\n\t/* Bind all local non-queue interrupt to vector 0 */\n\tint_map |= 0;\n\n\tFM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_Mailbox), int_map);\n\tFM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_PCIeFault), int_map);\n\tFM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_SwitchUpDown), int_map);\n\tFM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_SwitchEvent), int_map);\n\tFM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_SRAM), int_map);\n\tFM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_VFLR), int_map);\n\n\t/* Enable misc causes */\n\tFM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |\n\t\t\t\tFM10K_EIMR_ENABLE(THI_FAULT) |\n\t\t\t\tFM10K_EIMR_ENABLE(FUM_FAULT) |\n\t\t\t\tFM10K_EIMR_ENABLE(MAILBOX) |\n\t\t\t\tFM10K_EIMR_ENABLE(SWITCHREADY) |\n\t\t\t\tFM10K_EIMR_ENABLE(SWITCHNOTREADY) |\n\t\t\t\tFM10K_EIMR_ENABLE(SRAMERROR) |\n\t\t\t\tFM10K_EIMR_ENABLE(VFLR));\n\n\t/* Enable ITR 0 */\n\tFM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |\n\t\t\t\t\tFM10K_ITR_MASK_CLEAR);\n\tFM10K_WRITE_FLUSH(hw);\n}\n\nstatic void\nfm10k_dev_disable_intr_pf(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t int_map = FM10K_INT_MAP_DISABLE;\n\n\tint_map |= 0;\n\n\tFM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_Mailbox), int_map);\n\tFM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_PCIeFault), int_map);\n\tFM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_SwitchUpDown), int_map);\n\tFM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_SwitchEvent), int_map);\n\tFM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_SRAM), int_map);\n\tFM10K_WRITE_REG(hw, FM10K_INT_MAP(fm10k_int_VFLR), int_map);\n\n\t/* Disable misc causes */\n\tFM10K_WRITE_REG(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(PCA_FAULT) |\n\t\t\t\tFM10K_EIMR_DISABLE(THI_FAULT) |\n\t\t\t\tFM10K_EIMR_DISABLE(FUM_FAULT) |\n\t\t\t\tFM10K_EIMR_DISABLE(MAILBOX) |\n\t\t\t\tFM10K_EIMR_DISABLE(SWITCHREADY) |\n\t\t\t\tFM10K_EIMR_DISABLE(SWITCHNOTREADY) |\n\t\t\t\tFM10K_EIMR_DISABLE(SRAMERROR) |\n\t\t\t\tFM10K_EIMR_DISABLE(VFLR));\n\n\t/* Disable ITR 0 */\n\tFM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_MASK_SET);\n\tFM10K_WRITE_FLUSH(hw);\n}\n\nstatic void\nfm10k_dev_enable_intr_vf(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t int_map = FM10K_INT_MAP_IMMEDIATE;\n\n\t/* Bind all local non-queue interrupt to vector 0 */\n\tint_map |= 0;\n\n\t/* Only INT 0 available, other 15 are reserved. */\n\tFM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);\n\n\t/* Enable ITR 0 */\n\tFM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |\n\t\t\t\t\tFM10K_ITR_MASK_CLEAR);\n\tFM10K_WRITE_FLUSH(hw);\n}\n\nstatic void\nfm10k_dev_disable_intr_vf(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t int_map = FM10K_INT_MAP_DISABLE;\n\n\tint_map |= 0;\n\n\t/* Only INT 0 available, other 15 are reserved. */\n\tFM10K_WRITE_REG(hw, FM10K_VFINT_MAP, int_map);\n\n\t/* Disable ITR 0 */\n\tFM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_MASK_SET);\n\tFM10K_WRITE_FLUSH(hw);\n}\n\nstatic int\nfm10k_dev_handle_fault(struct fm10k_hw *hw, uint32_t eicr)\n{\n\tstruct fm10k_fault fault;\n\tint err;\n\tconst char *estr = \"Unknown error\";\n\n\t/* Process PCA fault */\n\tif (eicr & FM10K_EICR_PCA_FAULT) {\n\t\terr = fm10k_get_fault(hw, FM10K_PCA_FAULT, &fault);\n\t\tif (err)\n\t\t\tgoto error;\n\t\tswitch (fault.type) {\n\t\tcase PCA_NO_FAULT:\n\t\t\testr = \"PCA_NO_FAULT\"; break;\n\t\tcase PCA_UNMAPPED_ADDR:\n\t\t\testr = \"PCA_UNMAPPED_ADDR\"; break;\n\t\tcase PCA_BAD_QACCESS_PF:\n\t\t\testr = \"PCA_BAD_QACCESS_PF\"; break;\n\t\tcase PCA_BAD_QACCESS_VF:\n\t\t\testr = \"PCA_BAD_QACCESS_VF\"; break;\n\t\tcase PCA_MALICIOUS_REQ:\n\t\t\testr = \"PCA_MALICIOUS_REQ\"; break;\n\t\tcase PCA_POISONED_TLP:\n\t\t\testr = \"PCA_POISONED_TLP\"; break;\n\t\tcase PCA_TLP_ABORT:\n\t\t\testr = \"PCA_TLP_ABORT\"; break;\n\t\tdefault:\n\t\t\tgoto error;\n\t\t}\n\t\tPMD_INIT_LOG(ERR, \"%s: %s(%d) Addr:0x%\"PRIx64\" Spec: 0x%x\",\n\t\t\testr, fault.func ? \"VF\" : \"PF\", fault.func,\n\t\t\tfault.address, fault.specinfo);\n\t}\n\n\t/* Process THI fault */\n\tif (eicr & FM10K_EICR_THI_FAULT) {\n\t\terr = fm10k_get_fault(hw, FM10K_THI_FAULT, &fault);\n\t\tif (err)\n\t\t\tgoto error;\n\t\tswitch (fault.type) {\n\t\tcase THI_NO_FAULT:\n\t\t\testr = \"THI_NO_FAULT\"; break;\n\t\tcase THI_MAL_DIS_Q_FAULT:\n\t\t\testr = \"THI_MAL_DIS_Q_FAULT\"; break;\n\t\tdefault:\n\t\t\tgoto error;\n\t\t}\n\t\tPMD_INIT_LOG(ERR, \"%s: %s(%d) Addr:0x%\"PRIx64\" Spec: 0x%x\",\n\t\t\testr, fault.func ? \"VF\" : \"PF\", fault.func,\n\t\t\tfault.address, fault.specinfo);\n\t}\n\n\t/* Process FUM fault */\n\tif (eicr & FM10K_EICR_FUM_FAULT) {\n\t\terr = fm10k_get_fault(hw, FM10K_FUM_FAULT, &fault);\n\t\tif (err)\n\t\t\tgoto error;\n\t\tswitch (fault.type) {\n\t\tcase FUM_NO_FAULT:\n\t\t\testr = \"FUM_NO_FAULT\"; break;\n\t\tcase FUM_UNMAPPED_ADDR:\n\t\t\testr = \"FUM_UNMAPPED_ADDR\"; break;\n\t\tcase FUM_POISONED_TLP:\n\t\t\testr = \"FUM_POISONED_TLP\"; break;\n\t\tcase FUM_BAD_VF_QACCESS:\n\t\t\testr = \"FUM_BAD_VF_QACCESS\"; break;\n\t\tcase FUM_ADD_DECODE_ERR:\n\t\t\testr = \"FUM_ADD_DECODE_ERR\"; break;\n\t\tcase FUM_RO_ERROR:\n\t\t\testr = \"FUM_RO_ERROR\"; break;\n\t\tcase FUM_QPRC_CRC_ERROR:\n\t\t\testr = \"FUM_QPRC_CRC_ERROR\"; break;\n\t\tcase FUM_CSR_TIMEOUT:\n\t\t\testr = \"FUM_CSR_TIMEOUT\"; break;\n\t\tcase FUM_INVALID_TYPE:\n\t\t\testr = \"FUM_INVALID_TYPE\"; break;\n\t\tcase FUM_INVALID_LENGTH:\n\t\t\testr = \"FUM_INVALID_LENGTH\"; break;\n\t\tcase FUM_INVALID_BE:\n\t\t\testr = \"FUM_INVALID_BE\"; break;\n\t\tcase FUM_INVALID_ALIGN:\n\t\t\testr = \"FUM_INVALID_ALIGN\"; break;\n\t\tdefault:\n\t\t\tgoto error;\n\t\t}\n\t\tPMD_INIT_LOG(ERR, \"%s: %s(%d) Addr:0x%\"PRIx64\" Spec: 0x%x\",\n\t\t\testr, fault.func ? \"VF\" : \"PF\", fault.func,\n\t\t\tfault.address, fault.specinfo);\n\t}\n\n\treturn 0;\nerror:\n\tPMD_INIT_LOG(ERR, \"Failed to handle fault event.\");\n\treturn err;\n}\n\n/**\n * PF interrupt handler triggered by NIC for handling specific interrupt.\n *\n * @param handle\n * Pointer to interrupt handle.\n * @param param\n * The address of parameter (struct rte_eth_dev *) regsitered before.\n *\n * @return\n * void\n */\nstatic void\nfm10k_dev_interrupt_handler_pf(\n\t\t\t__rte_unused struct rte_intr_handle *handle,\n\t\t\tvoid *param)\n{\n\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t cause, status;\n\n\tif (hw->mac.type != fm10k_mac_pf)\n\t\treturn;\n\n\tcause = FM10K_READ_REG(hw, FM10K_EICR);\n\n\t/* Handle PCI fault cases */\n\tif (cause & FM10K_EICR_FAULT_MASK) {\n\t\tPMD_INIT_LOG(ERR, \"INT: find fault!\");\n\t\tfm10k_dev_handle_fault(hw, cause);\n\t}\n\n\t/* Handle switch up/down */\n\tif (cause & FM10K_EICR_SWITCHNOTREADY)\n\t\tPMD_INIT_LOG(ERR, \"INT: Switch is not ready\");\n\n\tif (cause & FM10K_EICR_SWITCHREADY)\n\t\tPMD_INIT_LOG(INFO, \"INT: Switch is ready\");\n\n\t/* Handle mailbox message */\n\tfm10k_mbx_lock(hw);\n\thw->mbx.ops.process(hw, &hw->mbx);\n\tfm10k_mbx_unlock(hw);\n\n\t/* Handle SRAM error */\n\tif (cause & FM10K_EICR_SRAMERROR) {\n\t\tPMD_INIT_LOG(ERR, \"INT: SRAM error on PEP\");\n\n\t\tstatus = FM10K_READ_REG(hw, FM10K_SRAM_IP);\n\t\t/* Write to clear pending bits */\n\t\tFM10K_WRITE_REG(hw, FM10K_SRAM_IP, status);\n\n\t\t/* Todo: print out error message after shared code updates */\n\t}\n\n\t/* Clear these 3 events if having any */\n\tcause &= FM10K_EICR_SWITCHNOTREADY | FM10K_EICR_MAILBOX |\n\t\t FM10K_EICR_SWITCHREADY;\n\tif (cause)\n\t\tFM10K_WRITE_REG(hw, FM10K_EICR, cause);\n\n\t/* Re-enable interrupt from device side */\n\tFM10K_WRITE_REG(hw, FM10K_ITR(0), FM10K_ITR_AUTOMASK |\n\t\t\t\t\tFM10K_ITR_MASK_CLEAR);\n\t/* Re-enable interrupt from host side */\n\trte_intr_enable(&(dev->pci_dev->intr_handle));\n}\n\n/**\n * VF interrupt handler triggered by NIC for handling specific interrupt.\n *\n * @param handle\n * Pointer to interrupt handle.\n * @param param\n * The address of parameter (struct rte_eth_dev *) regsitered before.\n *\n * @return\n * void\n */\nstatic void\nfm10k_dev_interrupt_handler_vf(\n\t\t\t__rte_unused struct rte_intr_handle *handle,\n\t\t\tvoid *param)\n{\n\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (hw->mac.type != fm10k_mac_vf)\n\t\treturn;\n\n\t/* Handle mailbox message if lock is acquired */\n\tfm10k_mbx_lock(hw);\n\thw->mbx.ops.process(hw, &hw->mbx);\n\tfm10k_mbx_unlock(hw);\n\n\t/* Re-enable interrupt from device side */\n\tFM10K_WRITE_REG(hw, FM10K_VFITR(0), FM10K_ITR_AUTOMASK |\n\t\t\t\t\tFM10K_ITR_MASK_CLEAR);\n\t/* Re-enable interrupt from host side */\n\trte_intr_enable(&(dev->pci_dev->intr_handle));\n}\n\n/* Mailbox message handler in VF */\nstatic const struct fm10k_msg_data fm10k_msgdata_vf[] = {\n\tFM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),\n\tFM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),\n\tFM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),\n\tFM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),\n};\n\n/* Mailbox message handler in PF */\nstatic const struct fm10k_msg_data fm10k_msgdata_pf[] = {\n\tFM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),\n\tFM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),\n\tFM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf),\n\tFM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),\n\tFM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),\n\tFM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),\n\tFM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),\n};\n\nstatic int\nfm10k_setup_mbx_service(struct fm10k_hw *hw)\n{\n\tint err;\n\n\t/* Initialize mailbox lock */\n\tfm10k_mbx_initlock(hw);\n\n\t/* Replace default message handler with new ones */\n\tif (hw->mac.type == fm10k_mac_pf)\n\t\terr = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_pf);\n\telse\n\t\terr = hw->mbx.ops.register_handlers(&hw->mbx, fm10k_msgdata_vf);\n\n\tif (err) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to register mailbox handler.err:%d\",\n\t\t\t\terr);\n\t\treturn err;\n\t}\n\t/* Connect to SM for PF device or PF for VF device */\n\treturn hw->mbx.ops.connect(hw, &hw->mbx);\n}\n\nstatic void\nfm10k_close_mbx_service(struct fm10k_hw *hw)\n{\n\t/* Disconnect from SM for PF device or PF for VF device */\n\thw->mbx.ops.disconnect(hw, &hw->mbx);\n}\n\nstatic const struct eth_dev_ops fm10k_eth_dev_ops = {\n\t.dev_configure\t\t= fm10k_dev_configure,\n\t.dev_start\t\t= fm10k_dev_start,\n\t.dev_stop\t\t= fm10k_dev_stop,\n\t.dev_close\t\t= fm10k_dev_close,\n\t.promiscuous_enable = fm10k_dev_promiscuous_enable,\n\t.promiscuous_disable = fm10k_dev_promiscuous_disable,\n\t.allmulticast_enable = fm10k_dev_allmulticast_enable,\n\t.allmulticast_disable = fm10k_dev_allmulticast_disable,\n\t.stats_get\t\t= fm10k_stats_get,\n\t.stats_reset\t\t= fm10k_stats_reset,\n\t.link_update\t\t= fm10k_link_update,\n\t.dev_infos_get\t\t= fm10k_dev_infos_get,\n\t.vlan_filter_set\t= fm10k_vlan_filter_set,\n\t.vlan_offload_set\t= fm10k_vlan_offload_set,\n\t.mac_addr_add\t\t= fm10k_macaddr_add,\n\t.mac_addr_remove\t= fm10k_macaddr_remove,\n\t.rx_queue_start\t\t= fm10k_dev_rx_queue_start,\n\t.rx_queue_stop\t\t= fm10k_dev_rx_queue_stop,\n\t.tx_queue_start\t\t= fm10k_dev_tx_queue_start,\n\t.tx_queue_stop\t\t= fm10k_dev_tx_queue_stop,\n\t.rx_queue_setup\t\t= fm10k_rx_queue_setup,\n\t.rx_queue_release\t= fm10k_rx_queue_release,\n\t.tx_queue_setup\t\t= fm10k_tx_queue_setup,\n\t.tx_queue_release\t= fm10k_tx_queue_release,\n\t.reta_update\t\t= fm10k_reta_update,\n\t.reta_query\t\t= fm10k_reta_query,\n\t.rss_hash_update\t= fm10k_rss_hash_update,\n\t.rss_hash_conf_get\t= fm10k_rss_hash_conf_get,\n};\n\nstatic int\neth_fm10k_dev_init(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint diag;\n\tstruct fm10k_macvlan_filter_info *macvlan;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tdev->dev_ops = &fm10k_eth_dev_ops;\n\tdev->rx_pkt_burst = &fm10k_recv_pkts;\n\tdev->tx_pkt_burst = &fm10k_xmit_pkts;\n\n\tif (dev->data->scattered_rx)\n\t\tdev->rx_pkt_burst = &fm10k_recv_scattered_pkts;\n\n\t/* only initialize in the primary process */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn 0;\n\n\tmacvlan = FM10K_DEV_PRIVATE_TO_MACVLAN(dev->data->dev_private);\n\tmemset(macvlan, 0, sizeof(*macvlan));\n\t/* Vendor and Device ID need to be set before init of shared code */\n\tmemset(hw, 0, sizeof(*hw));\n\thw->device_id = dev->pci_dev->id.device_id;\n\thw->vendor_id = dev->pci_dev->id.vendor_id;\n\thw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;\n\thw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;\n\thw->revision_id = 0;\n\thw->hw_addr = (void *)dev->pci_dev->mem_resource[0].addr;\n\tif (hw->hw_addr == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Bad mem resource.\"\n\t\t\t\" Try to blacklist unused devices.\");\n\t\treturn -EIO;\n\t}\n\n\t/* Store fm10k_adapter pointer */\n\thw->back = dev->data->dev_private;\n\n\t/* Initialize the shared code */\n\tdiag = fm10k_init_shared_code(hw);\n\tif (diag != FM10K_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Shared code init failed: %d\", diag);\n\t\treturn -EIO;\n\t}\n\n\t/*\n\t * Inialize bus info. Normally we would call fm10k_get_bus_info(), but\n\t * there is no way to get link status without reading BAR4. Until this\n\t * works, assume we have maximum bandwidth.\n\t * @todo - fix bus info\n\t */\n\thw->bus_caps.speed = fm10k_bus_speed_8000;\n\thw->bus_caps.width = fm10k_bus_width_pcie_x8;\n\thw->bus_caps.payload = fm10k_bus_payload_512;\n\thw->bus.speed = fm10k_bus_speed_8000;\n\thw->bus.width = fm10k_bus_width_pcie_x8;\n\thw->bus.payload = fm10k_bus_payload_256;\n\n\t/* Initialize the hw */\n\tdiag = fm10k_init_hw(hw);\n\tif (diag != FM10K_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Hardware init failed: %d\", diag);\n\t\treturn -EIO;\n\t}\n\n\t/* Initialize MAC address(es) */\n\tdev->data->mac_addrs = rte_zmalloc(\"fm10k\",\n\t\t\tETHER_ADDR_LEN * FM10K_MAX_MACADDR_NUM, 0);\n\tif (dev->data->mac_addrs == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Cannot allocate memory for MAC addresses\");\n\t\treturn -ENOMEM;\n\t}\n\n\tdiag = fm10k_read_mac_addr(hw);\n\n\tether_addr_copy((const struct ether_addr *)hw->mac.addr,\n\t\t\t&dev->data->mac_addrs[0]);\n\n\tif (diag != FM10K_SUCCESS ||\n\t\t!is_valid_assigned_ether_addr(dev->data->mac_addrs)) {\n\n\t\t/* Generate a random addr */\n\t\teth_random_addr(hw->mac.addr);\n\t\tmemcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);\n\t\tether_addr_copy((const struct ether_addr *)hw->mac.addr,\n\t\t&dev->data->mac_addrs[0]);\n\t}\n\n\t/* Reset the hw statistics */\n\tfm10k_stats_reset(dev);\n\n\t/* Reset the hw */\n\tdiag = fm10k_reset_hw(hw);\n\tif (diag != FM10K_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Hardware reset failed: %d\", diag);\n\t\treturn -EIO;\n\t}\n\n\t/* Setup mailbox service */\n\tdiag = fm10k_setup_mbx_service(hw);\n\tif (diag != FM10K_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to setup mailbox: %d\", diag);\n\t\treturn -EIO;\n\t}\n\n\t/*PF/VF has different interrupt handling mechanism */\n\tif (hw->mac.type == fm10k_mac_pf) {\n\t\t/* register callback func to eal lib */\n\t\trte_intr_callback_register(&(dev->pci_dev->intr_handle),\n\t\t\tfm10k_dev_interrupt_handler_pf, (void *)dev);\n\n\t\t/* enable MISC interrupt */\n\t\tfm10k_dev_enable_intr_pf(dev);\n\t} else { /* VF */\n\t\trte_intr_callback_register(&(dev->pci_dev->intr_handle),\n\t\t\tfm10k_dev_interrupt_handler_vf, (void *)dev);\n\n\t\tfm10k_dev_enable_intr_vf(dev);\n\t}\n\n\t/* Enable uio intr after callback registered */\n\trte_intr_enable(&(dev->pci_dev->intr_handle));\n\n\thw->mac.ops.update_int_moderator(hw);\n\n\t/* Make sure Switch Manager is ready before going forward. */\n\tif (hw->mac.type == fm10k_mac_pf) {\n\t\tint switch_ready = 0;\n\t\tint i;\n\n\t\tfor (i = 0; i < MAX_QUERY_SWITCH_STATE_TIMES; i++) {\n\t\t\tfm10k_mbx_lock(hw);\n\t\t\thw->mac.ops.get_host_state(hw, &switch_ready);\n\t\t\tfm10k_mbx_unlock(hw);\n\t\t\tif (switch_ready)\n\t\t\t\tbreak;\n\t\t\t/* Delay some time to acquire async LPORT_MAP info. */\n\t\t\trte_delay_us(WAIT_SWITCH_MSG_US);\n\t\t}\n\n\t\tif (switch_ready == 0) {\n\t\t\tPMD_INIT_LOG(ERR, \"switch is not ready\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/*\n\t * Below function will trigger operations on mailbox, acquire lock to\n\t * avoid race condition from interrupt handler. Operations on mailbox\n\t * FIFO will trigger interrupt to PF/SM, in which interrupt handler\n\t * will handle and generate an interrupt to our side. Then, FIFO in\n\t * mailbox will be touched.\n\t */\n\tfm10k_mbx_lock(hw);\n\t/* Enable port first */\n\thw->mac.ops.update_lport_state(hw, hw->mac.dglort_map, 1, 1);\n\n\t/* Set unicast mode by default. App can change to other mode in other\n\t * API func.\n\t */\n\thw->mac.ops.update_xcast_mode(hw, hw->mac.dglort_map,\n\t\t\t\t\tFM10K_XCAST_MODE_NONE);\n\n\tfm10k_mbx_unlock(hw);\n\n\t/* Add default mac address */\n\tfm10k_MAC_filter_set(dev, hw->mac.addr, true);\n\n\treturn 0;\n}\n\nstatic int\neth_fm10k_dev_uninit(struct rte_eth_dev *dev)\n{\n\tstruct fm10k_hw *hw = FM10K_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* only uninitialize in the primary process */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn 0;\n\n\t/* safe to close dev here */\n\tfm10k_dev_close(dev);\n\n\tdev->dev_ops = NULL;\n\tdev->rx_pkt_burst = NULL;\n\tdev->tx_pkt_burst = NULL;\n\n\t/* disable uio/vfio intr */\n\trte_intr_disable(&(dev->pci_dev->intr_handle));\n\n\t/*PF/VF has different interrupt handling mechanism */\n\tif (hw->mac.type == fm10k_mac_pf) {\n\t\t/* disable interrupt */\n\t\tfm10k_dev_disable_intr_pf(dev);\n\n\t\t/* unregister callback func to eal lib */\n\t\trte_intr_callback_unregister(&(dev->pci_dev->intr_handle),\n\t\t\tfm10k_dev_interrupt_handler_pf, (void *)dev);\n\t} else {\n\t\t/* disable interrupt */\n\t\tfm10k_dev_disable_intr_vf(dev);\n\n\t\trte_intr_callback_unregister(&(dev->pci_dev->intr_handle),\n\t\t\tfm10k_dev_interrupt_handler_vf, (void *)dev);\n\t}\n\n\t/* free mac memory */\n\tif (dev->data->mac_addrs) {\n\t\trte_free(dev->data->mac_addrs);\n\t\tdev->data->mac_addrs = NULL;\n\t}\n\n\tmemset(hw, 0, sizeof(*hw));\n\n\treturn 0;\n}\n\n/*\n * The set of PCI devices this driver supports. This driver will enable both PF\n * and SRIOV-VF devices.\n */\nstatic const struct rte_pci_id pci_id_fm10k_map[] = {\n#define RTE_PCI_DEV_ID_DECL_FM10K(vend, dev) { RTE_PCI_DEVICE(vend, dev) },\n#define RTE_PCI_DEV_ID_DECL_FM10KVF(vend, dev) { RTE_PCI_DEVICE(vend, dev) },\n#include \"rte_pci_dev_ids.h\"\n\t{ .vendor_id = 0, /* sentinel */ },\n};\n\nstatic struct eth_driver rte_pmd_fm10k = {\n\t.pci_drv = {\n\t\t.name = \"rte_pmd_fm10k\",\n\t\t.id_table = pci_id_fm10k_map,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,\n\t},\n\t.eth_dev_init = eth_fm10k_dev_init,\n\t.eth_dev_uninit = eth_fm10k_dev_uninit,\n\t.dev_private_size = sizeof(struct fm10k_adapter),\n};\n\n/*\n * Driver initialization routine.\n * Invoked once at EAL init time.\n * Register itself as the [Poll Mode] Driver of PCI FM10K devices.\n */\nstatic int\nrte_pmd_fm10k_init(__rte_unused const char *name,\n\t__rte_unused const char *params)\n{\n\tPMD_INIT_FUNC_TRACE();\n\trte_eth_driver_register(&rte_pmd_fm10k);\n\treturn 0;\n}\n\nstatic struct rte_driver rte_fm10k_driver = {\n\t.type = PMD_PDEV,\n\t.init = rte_pmd_fm10k_init,\n};\n\nPMD_REGISTER_DRIVER(rte_fm10k_driver);\n" }, { "path": "drivers/net/fm10k/fm10k_logs.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _FM10K_LOGS_H_\n#define _FM10K_LOGS_H_\n\n#include \n\n#define PMD_INIT_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ##args)\n\n#ifdef RTE_LIBRTE_FM10K_DEBUG_INIT\n#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, \" >>\")\n#else\n#define PMD_INIT_FUNC_TRACE() do { } while (0)\n#endif\n\n#ifdef RTE_LIBRTE_FM10K_DEBUG_RX\n#define PMD_RX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_RX_LOG(level, fmt, args...) do { } while (0)\n#endif\n\n#ifdef RTE_LIBRTE_FM10K_DEBUG_TX\n#define PMD_TX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_TX_LOG(level, fmt, args...) do { } while (0)\n#endif\n\n#ifdef RTE_LIBRTE_FM10K_DEBUG_TX_FREE\n#define PMD_TX_FREE_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_TX_FREE_LOG(level, fmt, args...) do { } while (0)\n#endif\n\n#ifdef RTE_LIBRTE_FM10K_DEBUG_DRIVER\n#define PMD_DRV_LOG_RAW(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt, __func__, ## args)\n#else\n#define PMD_DRV_LOG_RAW(level, fmt, args...) do { } while (0)\n#endif\n\n#define PMD_DRV_LOG(level, fmt, args...) \\\n\tPMD_DRV_LOG_RAW(level, fmt \"\\n\", ## args)\n\n#endif /* _FM10K_LOGS_H_ */\n" }, { "path": "drivers/net/fm10k/fm10k_rxtx.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \"fm10k.h\"\n#include \"base/fm10k_type.h\"\n\n#ifdef RTE_PMD_PACKET_PREFETCH\n#define rte_packet_prefetch(p) rte_prefetch1(p)\n#else\n#define rte_packet_prefetch(p) do {} while (0)\n#endif\n\n#ifdef RTE_LIBRTE_FM10K_DEBUG_RX\nstatic inline void dump_rxd(union fm10k_rx_desc *rxd)\n{\n\tPMD_RX_LOG(DEBUG, \"+----------------|----------------+\");\n\tPMD_RX_LOG(DEBUG, \"| GLORT | PKT HDR & TYPE |\");\n\tPMD_RX_LOG(DEBUG, \"| 0x%08x | 0x%08x |\", rxd->d.glort,\n\t\t\trxd->d.data);\n\tPMD_RX_LOG(DEBUG, \"+----------------|----------------+\");\n\tPMD_RX_LOG(DEBUG, \"| VLAN & LEN | STATUS |\");\n\tPMD_RX_LOG(DEBUG, \"| 0x%08x | 0x%08x |\", rxd->d.vlan_len,\n\t\t\trxd->d.staterr);\n\tPMD_RX_LOG(DEBUG, \"+----------------|----------------+\");\n\tPMD_RX_LOG(DEBUG, \"| RESERVED | RSS_HASH |\");\n\tPMD_RX_LOG(DEBUG, \"| 0x%08x | 0x%08x |\", 0, rxd->d.rss);\n\tPMD_RX_LOG(DEBUG, \"+----------------|----------------+\");\n\tPMD_RX_LOG(DEBUG, \"| TIME TAG |\");\n\tPMD_RX_LOG(DEBUG, \"| 0x%016\"PRIx64\" |\", rxd->q.timestamp);\n\tPMD_RX_LOG(DEBUG, \"+----------------|----------------+\");\n}\n#endif\n\nstatic inline void\nrx_desc_to_ol_flags(struct rte_mbuf *m, const union fm10k_rx_desc *d)\n{\n#ifdef RTE_NEXT_ABI\n\tstatic const uint32_t\n\t\tptype_table[FM10K_RXD_PKTTYPE_MASK >> FM10K_RXD_PKTTYPE_SHIFT]\n\t\t\t__rte_cache_aligned = {\n\t\t[FM10K_PKTTYPE_OTHER] = RTE_PTYPE_L2_ETHER,\n\t\t[FM10K_PKTTYPE_IPV4] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4,\n\t\t[FM10K_PKTTYPE_IPV4_EX] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4_EXT,\n\t\t[FM10K_PKTTYPE_IPV6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6,\n\t\t[FM10K_PKTTYPE_IPV6_EX] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6_EXT,\n\t\t[FM10K_PKTTYPE_IPV4 | FM10K_PKTTYPE_TCP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,\n\t\t[FM10K_PKTTYPE_IPV6 | FM10K_PKTTYPE_TCP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,\n\t\t[FM10K_PKTTYPE_IPV4 | FM10K_PKTTYPE_UDP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,\n\t\t[FM10K_PKTTYPE_IPV6 | FM10K_PKTTYPE_UDP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,\n\t};\n\n\tm->packet_type = ptype_table[(d->w.pkt_info & FM10K_RXD_PKTTYPE_MASK)\n\t\t\t\t\t\t>> FM10K_RXD_PKTTYPE_SHIFT];\n#else /* RTE_NEXT_ABI */\n\tuint16_t ptype;\n\tstatic const uint16_t pt_lut[] = { 0,\n\t\tPKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT,\n\t\tPKT_RX_IPV6_HDR, PKT_RX_IPV6_HDR_EXT,\n\t\t0, 0, 0\n\t};\n#endif /* RTE_NEXT_ABI */\n\n\tif (d->w.pkt_info & FM10K_RXD_RSSTYPE_MASK)\n\t\tm->ol_flags |= PKT_RX_RSS_HASH;\n\n\tif (unlikely((d->d.staterr &\n\t\t(FM10K_RXD_STATUS_IPCS | FM10K_RXD_STATUS_IPE)) ==\n\t\t(FM10K_RXD_STATUS_IPCS | FM10K_RXD_STATUS_IPE)))\n\t\tm->ol_flags |= PKT_RX_IP_CKSUM_BAD;\n\n\tif (unlikely((d->d.staterr &\n\t\t(FM10K_RXD_STATUS_L4CS | FM10K_RXD_STATUS_L4E)) ==\n\t\t(FM10K_RXD_STATUS_L4CS | FM10K_RXD_STATUS_L4E)))\n\t\tm->ol_flags |= PKT_RX_L4_CKSUM_BAD;\n\n\tif (d->d.staterr & FM10K_RXD_STATUS_VEXT)\n\t\tm->ol_flags |= PKT_RX_VLAN_PKT;\n\n\tif (unlikely(d->d.staterr & FM10K_RXD_STATUS_HBO))\n\t\tm->ol_flags |= PKT_RX_HBUF_OVERFLOW;\n\n\tif (unlikely(d->d.staterr & FM10K_RXD_STATUS_RXE))\n\t\tm->ol_flags |= PKT_RX_RECIP_ERR;\n\n#ifndef RTE_NEXT_ABI\n\tptype = (d->d.data & FM10K_RXD_PKTTYPE_MASK_L3) >>\n\t\t\t\t\t\tFM10K_RXD_PKTTYPE_SHIFT;\n\tm->ol_flags |= pt_lut[(uint8_t)ptype];\n#endif\n}\n\nuint16_t\nfm10k_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\tuint16_t nb_pkts)\n{\n\tstruct rte_mbuf *mbuf;\n\tunion fm10k_rx_desc desc;\n\tstruct fm10k_rx_queue *q = rx_queue;\n\tuint16_t count = 0;\n\tint alloc = 0;\n\tuint16_t next_dd;\n\tint ret;\n\n\tnext_dd = q->next_dd;\n\n\tnb_pkts = RTE_MIN(nb_pkts, q->alloc_thresh);\n\tfor (count = 0; count < nb_pkts; ++count) {\n\t\tmbuf = q->sw_ring[next_dd];\n\t\tdesc = q->hw_ring[next_dd];\n\t\tif (!(desc.d.staterr & FM10K_RXD_STATUS_DD))\n\t\t\tbreak;\n#ifdef RTE_LIBRTE_FM10K_DEBUG_RX\n\t\tdump_rxd(&desc);\n#endif\n\t\trte_pktmbuf_pkt_len(mbuf) = desc.w.length;\n\t\trte_pktmbuf_data_len(mbuf) = desc.w.length;\n\n\t\tmbuf->ol_flags = 0;\n#ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE\n\t\trx_desc_to_ol_flags(mbuf, &desc);\n#endif\n\n\t\tmbuf->hash.rss = desc.d.rss;\n\n\t\trx_pkts[count] = mbuf;\n\t\tif (++next_dd == q->nb_desc) {\n\t\t\tnext_dd = 0;\n\t\t\talloc = 1;\n\t\t}\n\n\t\t/* Prefetch next mbuf while processing current one. */\n\t\trte_prefetch0(q->sw_ring[next_dd]);\n\n\t\t/*\n\t\t * When next RX descriptor is on a cache-line boundary,\n\t\t * prefetch the next 4 RX descriptors and the next 8 pointers\n\t\t * to mbufs.\n\t\t */\n\t\tif ((next_dd & 0x3) == 0) {\n\t\t\trte_prefetch0(&q->hw_ring[next_dd]);\n\t\t\trte_prefetch0(&q->sw_ring[next_dd]);\n\t\t}\n\t}\n\n\tq->next_dd = next_dd;\n\n\tif ((q->next_dd > q->next_trigger) || (alloc == 1)) {\n\t\tret = rte_mempool_get_bulk(q->mp,\n\t\t\t\t\t(void **)&q->sw_ring[q->next_alloc],\n\t\t\t\t\tq->alloc_thresh);\n\n\t\tif (unlikely(ret != 0)) {\n\t\t\tuint8_t port = q->port_id;\n\t\t\tPMD_RX_LOG(ERR, \"Failed to alloc mbuf\");\n\t\t\t/*\n\t\t\t * Need to restore next_dd if we cannot allocate new\n\t\t\t * buffers to replenish the old ones.\n\t\t\t */\n\t\t\tq->next_dd = (q->next_dd + q->nb_desc - count) %\n\t\t\t\t\t\t\t\tq->nb_desc;\n\t\t\trte_eth_devices[port].data->rx_mbuf_alloc_failed++;\n\t\t\treturn 0;\n\t\t}\n\n\t\tfor (; q->next_alloc <= q->next_trigger; ++q->next_alloc) {\n\t\t\tmbuf = q->sw_ring[q->next_alloc];\n\n\t\t\t/* setup static mbuf fields */\n\t\t\tfm10k_pktmbuf_reset(mbuf, q->port_id);\n\n\t\t\t/* write descriptor */\n\t\t\tdesc.q.pkt_addr = MBUF_DMA_ADDR_DEFAULT(mbuf);\n\t\t\tdesc.q.hdr_addr = MBUF_DMA_ADDR_DEFAULT(mbuf);\n\t\t\tq->hw_ring[q->next_alloc] = desc;\n\t\t}\n\t\tFM10K_PCI_REG_WRITE(q->tail_ptr, q->next_trigger);\n\t\tq->next_trigger += q->alloc_thresh;\n\t\tif (q->next_trigger >= q->nb_desc) {\n\t\t\tq->next_trigger = q->alloc_thresh - 1;\n\t\t\tq->next_alloc = 0;\n\t\t}\n\t}\n\n\treturn count;\n}\n\nuint16_t\nfm10k_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\t\t\tuint16_t nb_pkts)\n{\n\tstruct rte_mbuf *mbuf;\n\tunion fm10k_rx_desc desc;\n\tstruct fm10k_rx_queue *q = rx_queue;\n\tuint16_t count = 0;\n\tuint16_t nb_rcv, nb_seg;\n\tint alloc = 0;\n\tuint16_t next_dd;\n\tstruct rte_mbuf *first_seg = q->pkt_first_seg;\n\tstruct rte_mbuf *last_seg = q->pkt_last_seg;\n\tint ret;\n\n\tnext_dd = q->next_dd;\n\tnb_rcv = 0;\n\n\tnb_seg = RTE_MIN(nb_pkts, q->alloc_thresh);\n\tfor (count = 0; count < nb_seg; count++) {\n\t\tmbuf = q->sw_ring[next_dd];\n\t\tdesc = q->hw_ring[next_dd];\n\t\tif (!(desc.d.staterr & FM10K_RXD_STATUS_DD))\n\t\t\tbreak;\n#ifdef RTE_LIBRTE_FM10K_DEBUG_RX\n\t\tdump_rxd(&desc);\n#endif\n\n\t\tif (++next_dd == q->nb_desc) {\n\t\t\tnext_dd = 0;\n\t\t\talloc = 1;\n\t\t}\n\n\t\t/* Prefetch next mbuf while processing current one. */\n\t\trte_prefetch0(q->sw_ring[next_dd]);\n\n\t\t/*\n\t\t * When next RX descriptor is on a cache-line boundary,\n\t\t * prefetch the next 4 RX descriptors and the next 8 pointers\n\t\t * to mbufs.\n\t\t */\n\t\tif ((next_dd & 0x3) == 0) {\n\t\t\trte_prefetch0(&q->hw_ring[next_dd]);\n\t\t\trte_prefetch0(&q->sw_ring[next_dd]);\n\t\t}\n\n\t\t/* Fill data length */\n\t\trte_pktmbuf_data_len(mbuf) = desc.w.length;\n\n\t\t/*\n\t\t * If this is the first buffer of the received packet,\n\t\t * set the pointer to the first mbuf of the packet and\n\t\t * initialize its context.\n\t\t * Otherwise, update the total length and the number of segments\n\t\t * of the current scattered packet, and update the pointer to\n\t\t * the last mbuf of the current packet.\n\t\t */\n\t\tif (!first_seg) {\n\t\t\tfirst_seg = mbuf;\n\t\t\tfirst_seg->pkt_len = desc.w.length;\n\t\t} else {\n\t\t\tfirst_seg->pkt_len =\n\t\t\t\t\t(uint16_t)(first_seg->pkt_len +\n\t\t\t\t\trte_pktmbuf_data_len(mbuf));\n\t\t\tfirst_seg->nb_segs++;\n\t\t\tlast_seg->next = mbuf;\n\t\t}\n\n\t\t/*\n\t\t * If this is not the last buffer of the received packet,\n\t\t * update the pointer to the last mbuf of the current scattered\n\t\t * packet and continue to parse the RX ring.\n\t\t */\n\t\tif (!(desc.d.staterr & FM10K_RXD_STATUS_EOP)) {\n\t\t\tlast_seg = mbuf;\n\t\t\tcontinue;\n\t\t}\n\n\t\tfirst_seg->ol_flags = 0;\n#ifdef RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE\n\t\trx_desc_to_ol_flags(first_seg, &desc);\n#endif\n\t\tfirst_seg->hash.rss = desc.d.rss;\n\n\t\t/* Prefetch data of first segment, if configured to do so. */\n\t\trte_packet_prefetch((char *)first_seg->buf_addr +\n\t\t\tfirst_seg->data_off);\n\n\t\t/*\n\t\t * Store the mbuf address into the next entry of the array\n\t\t * of returned packets.\n\t\t */\n\t\trx_pkts[nb_rcv++] = first_seg;\n\n\t\t/*\n\t\t * Setup receipt context for a new packet.\n\t\t */\n\t\tfirst_seg = NULL;\n\t}\n\n\tq->next_dd = next_dd;\n\n\tif ((q->next_dd > q->next_trigger) || (alloc == 1)) {\n\t\tret = rte_mempool_get_bulk(q->mp,\n\t\t\t\t\t(void **)&q->sw_ring[q->next_alloc],\n\t\t\t\t\tq->alloc_thresh);\n\n\t\tif (unlikely(ret != 0)) {\n\t\t\tuint8_t port = q->port_id;\n\t\t\tPMD_RX_LOG(ERR, \"Failed to alloc mbuf\");\n\t\t\t/*\n\t\t\t * Need to restore next_dd if we cannot allocate new\n\t\t\t * buffers to replenish the old ones.\n\t\t\t */\n\t\t\tq->next_dd = (q->next_dd + q->nb_desc - count) %\n\t\t\t\t\t\t\t\tq->nb_desc;\n\t\t\trte_eth_devices[port].data->rx_mbuf_alloc_failed++;\n\t\t\treturn 0;\n\t\t}\n\n\t\tfor (; q->next_alloc <= q->next_trigger; ++q->next_alloc) {\n\t\t\tmbuf = q->sw_ring[q->next_alloc];\n\n\t\t\t/* setup static mbuf fields */\n\t\t\tfm10k_pktmbuf_reset(mbuf, q->port_id);\n\n\t\t\t/* write descriptor */\n\t\t\tdesc.q.pkt_addr = MBUF_DMA_ADDR_DEFAULT(mbuf);\n\t\t\tdesc.q.hdr_addr = MBUF_DMA_ADDR_DEFAULT(mbuf);\n\t\t\tq->hw_ring[q->next_alloc] = desc;\n\t\t}\n\t\tFM10K_PCI_REG_WRITE(q->tail_ptr, q->next_trigger);\n\t\tq->next_trigger += q->alloc_thresh;\n\t\tif (q->next_trigger >= q->nb_desc) {\n\t\t\tq->next_trigger = q->alloc_thresh - 1;\n\t\t\tq->next_alloc = 0;\n\t\t}\n\t}\n\n\tq->pkt_first_seg = first_seg;\n\tq->pkt_last_seg = last_seg;\n\n\treturn nb_rcv;\n}\n\nstatic inline void tx_free_descriptors(struct fm10k_tx_queue *q)\n{\n\tuint16_t next_rs, count = 0;\n\n\tnext_rs = fifo_peek(&q->rs_tracker);\n\tif (!(q->hw_ring[next_rs].flags & FM10K_TXD_FLAG_DONE))\n\t\treturn;\n\n\t/* the DONE flag is set on this descriptor so remove the ID\n\t * from the RS bit tracker and free the buffers */\n\tfifo_remove(&q->rs_tracker);\n\n\t/* wrap around? if so, free buffers from last_free up to but NOT\n\t * including nb_desc */\n\tif (q->last_free > next_rs) {\n\t\tcount = q->nb_desc - q->last_free;\n\t\twhile (q->last_free < q->nb_desc) {\n\t\t\trte_pktmbuf_free_seg(q->sw_ring[q->last_free]);\n\t\t\tq->sw_ring[q->last_free] = NULL;\n\t\t\t++q->last_free;\n\t\t}\n\t\tq->last_free = 0;\n\t}\n\n\t/* adjust free descriptor count before the next loop */\n\tq->nb_free += count + (next_rs + 1 - q->last_free);\n\n\t/* free buffers from last_free, up to and including next_rs */\n\twhile (q->last_free <= next_rs) {\n\t\trte_pktmbuf_free_seg(q->sw_ring[q->last_free]);\n\t\tq->sw_ring[q->last_free] = NULL;\n\t\t++q->last_free;\n\t}\n\n\tif (q->last_free == q->nb_desc)\n\t\tq->last_free = 0;\n}\n\nstatic inline void tx_xmit_pkt(struct fm10k_tx_queue *q, struct rte_mbuf *mb)\n{\n\tuint16_t last_id;\n\tuint8_t flags;\n\n\t/* always set the LAST flag on the last descriptor used to\n\t * transmit the packet */\n\tflags = FM10K_TXD_FLAG_LAST;\n\tlast_id = q->next_free + mb->nb_segs - 1;\n\tif (last_id >= q->nb_desc)\n\t\tlast_id = last_id - q->nb_desc;\n\n\t/* but only set the RS flag on the last descriptor if rs_thresh\n\t * descriptors will be used since the RS flag was last set */\n\tif ((q->nb_used + mb->nb_segs) >= q->rs_thresh) {\n\t\tflags |= FM10K_TXD_FLAG_RS;\n\t\tfifo_insert(&q->rs_tracker, last_id);\n\t\tq->nb_used = 0;\n\t} else {\n\t\tq->nb_used = q->nb_used + mb->nb_segs;\n\t}\n\n\tq->nb_free -= mb->nb_segs;\n\n\tq->hw_ring[q->next_free].flags = 0;\n\t/* set checksum flags on first descriptor of packet. SCTP checksum\n\t * offload is not supported, but we do not explicitly check for this\n\t * case in favor of greatly simplified processing. */\n\tif (mb->ol_flags & (PKT_TX_IP_CKSUM | PKT_TX_L4_MASK))\n\t\tq->hw_ring[q->next_free].flags |= FM10K_TXD_FLAG_CSUM;\n\n\t/* set vlan if requested */\n\tif (mb->ol_flags & PKT_TX_VLAN_PKT)\n\t\tq->hw_ring[q->next_free].vlan = mb->vlan_tci;\n\n\tq->sw_ring[q->next_free] = mb;\n\tq->hw_ring[q->next_free].buffer_addr =\n\t\t\trte_cpu_to_le_64(MBUF_DMA_ADDR(mb));\n\tq->hw_ring[q->next_free].buflen =\n\t\t\trte_cpu_to_le_16(rte_pktmbuf_data_len(mb));\n\tif (++q->next_free == q->nb_desc)\n\t\tq->next_free = 0;\n\n\t/* fill up the rings */\n\tfor (mb = mb->next; mb != NULL; mb = mb->next) {\n\t\tq->sw_ring[q->next_free] = mb;\n\t\tq->hw_ring[q->next_free].buffer_addr =\n\t\t\t\trte_cpu_to_le_64(MBUF_DMA_ADDR(mb));\n\t\tq->hw_ring[q->next_free].buflen =\n\t\t\t\trte_cpu_to_le_16(rte_pktmbuf_data_len(mb));\n\t\tq->hw_ring[q->next_free].flags = 0;\n\t\tif (++q->next_free == q->nb_desc)\n\t\t\tq->next_free = 0;\n\t}\n\n\tq->hw_ring[last_id].flags = flags;\n}\n\nuint16_t\nfm10k_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\tuint16_t nb_pkts)\n{\n\tstruct fm10k_tx_queue *q = tx_queue;\n\tstruct rte_mbuf *mb;\n\tuint16_t count;\n\n\tfor (count = 0; count < nb_pkts; ++count) {\n\t\tmb = tx_pkts[count];\n\n\t\t/* running low on descriptors? try to free some... */\n\t\tif (q->nb_free < q->free_thresh)\n\t\t\ttx_free_descriptors(q);\n\n\t\t/* make sure there are enough free descriptors to transmit the\n\t\t * entire packet before doing anything */\n\t\tif (q->nb_free < mb->nb_segs)\n\t\t\tbreak;\n\n\t\t/* sanity check to make sure the mbuf is valid */\n\t\tif ((mb->nb_segs == 0) ||\n\t\t ((mb->nb_segs > 1) && (mb->next == NULL)))\n\t\t\tbreak;\n\n\t\t/* process the packet */\n\t\ttx_xmit_pkt(q, mb);\n\t}\n\n\t/* update the tail pointer if any packets were processed */\n\tif (likely(count > 0))\n\t\tFM10K_PCI_REG_WRITE(q->tail_ptr, q->next_free);\n\n\treturn count;\n}\n" }, { "path": "drivers/net/i40e/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_i40e.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS) -DPF_DRIVER -DVF_DRIVER -DINTEGRATED_VF\n\nEXPORT_MAP := rte_pmd_i40e_version.map\n\nLIBABIVER := 1\n\n#\n# Add extra flags for base driver files (also known as shared code)\n# to disable warnings\n#\nifeq ($(CC), icc)\nCFLAGS_BASE_DRIVER = -wd593 -wd188\nelse ifeq ($(CC), clang)\nCFLAGS_BASE_DRIVER += -Wno-sign-compare\nCFLAGS_BASE_DRIVER += -Wno-unused-value\nCFLAGS_BASE_DRIVER += -Wno-unused-parameter\nCFLAGS_BASE_DRIVER += -Wno-strict-aliasing\nCFLAGS_BASE_DRIVER += -Wno-format\nCFLAGS_BASE_DRIVER += -Wno-missing-field-initializers\nCFLAGS_BASE_DRIVER += -Wno-pointer-to-int-cast\nCFLAGS_BASE_DRIVER += -Wno-format-nonliteral\nCFLAGS_BASE_DRIVER += -Wno-unused-variable\nelse\nCFLAGS_BASE_DRIVER = -Wno-sign-compare\nCFLAGS_BASE_DRIVER += -Wno-unused-value\nCFLAGS_BASE_DRIVER += -Wno-unused-parameter\nCFLAGS_BASE_DRIVER += -Wno-strict-aliasing\nCFLAGS_BASE_DRIVER += -Wno-format\nCFLAGS_BASE_DRIVER += -Wno-missing-field-initializers\nCFLAGS_BASE_DRIVER += -Wno-pointer-to-int-cast\nCFLAGS_BASE_DRIVER += -Wno-format-nonliteral\nCFLAGS_BASE_DRIVER += -Wno-format-security\nCFLAGS_BASE_DRIVER += -Wno-unused-variable\n\nifeq ($(shell test $(GCC_VERSION) -ge 44 && echo 1), 1)\nCFLAGS_BASE_DRIVER += -Wno-unused-but-set-variable\nendif\n\nCFLAGS_i40e_lan_hmc.o += -Wno-error\nendif\nOBJS_BASE_DRIVER=$(patsubst %.c,%.o,$(notdir $(wildcard $(SRCDIR)/base/*.c)))\n$(foreach obj, $(OBJS_BASE_DRIVER), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER)))\n\nVPATH += $(SRCDIR)/base\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_adminq.c\nSRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_common.c\nSRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_diag.c\nSRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_hmc.c\nSRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_lan_hmc.c\nSRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_nvm.c\nSRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_dcb.c\n\nSRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_ethdev.c\nSRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_rxtx.c\nSRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_ethdev_vf.c\nSRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_pf.c\nSRCS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e_fdir.c\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += lib/librte_eal lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += lib/librte_mempool lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += lib/librte_net\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/i40e/base/i40e_adminq.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"i40e_status.h\"\n#include \"i40e_type.h\"\n#include \"i40e_register.h\"\n#include \"i40e_adminq.h\"\n#include \"i40e_prototype.h\"\n\n#ifdef PF_DRIVER\n/**\n * i40e_is_nvm_update_op - return true if this is an NVM update operation\n * @desc: API request descriptor\n **/\nSTATIC INLINE bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)\n{\n\treturn (desc->opcode == CPU_TO_LE16(i40e_aqc_opc_nvm_erase) ||\n\t\tdesc->opcode == CPU_TO_LE16(i40e_aqc_opc_nvm_update));\n}\n\n#endif /* PF_DRIVER */\n/**\n * i40e_adminq_init_regs - Initialize AdminQ registers\n * @hw: pointer to the hardware structure\n *\n * This assumes the alloc_asq and alloc_arq functions have already been called\n **/\nSTATIC void i40e_adminq_init_regs(struct i40e_hw *hw)\n{\n\t/* set head and tail registers in our local struct */\n\tif (i40e_is_vf(hw)) {\n\t\thw->aq.asq.tail = I40E_VF_ATQT1;\n\t\thw->aq.asq.head = I40E_VF_ATQH1;\n\t\thw->aq.asq.len = I40E_VF_ATQLEN1;\n\t\thw->aq.asq.bal = I40E_VF_ATQBAL1;\n\t\thw->aq.asq.bah = I40E_VF_ATQBAH1;\n\t\thw->aq.arq.tail = I40E_VF_ARQT1;\n\t\thw->aq.arq.head = I40E_VF_ARQH1;\n\t\thw->aq.arq.len = I40E_VF_ARQLEN1;\n\t\thw->aq.arq.bal = I40E_VF_ARQBAL1;\n\t\thw->aq.arq.bah = I40E_VF_ARQBAH1;\n\t} else {\n\t\thw->aq.asq.tail = I40E_PF_ATQT;\n\t\thw->aq.asq.head = I40E_PF_ATQH;\n\t\thw->aq.asq.len = I40E_PF_ATQLEN;\n\t\thw->aq.asq.bal = I40E_PF_ATQBAL;\n\t\thw->aq.asq.bah = I40E_PF_ATQBAH;\n\t\thw->aq.arq.tail = I40E_PF_ARQT;\n\t\thw->aq.arq.head = I40E_PF_ARQH;\n\t\thw->aq.arq.len = I40E_PF_ARQLEN;\n\t\thw->aq.arq.bal = I40E_PF_ARQBAL;\n\t\thw->aq.arq.bah = I40E_PF_ARQBAH;\n\t}\n}\n\n/**\n * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings\n * @hw: pointer to the hardware structure\n **/\nenum i40e_status_code i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code;\n\n\tret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,\n\t\t\t\t\t i40e_mem_atq_ring,\n\t\t\t\t\t (hw->aq.num_asq_entries *\n\t\t\t\t\t sizeof(struct i40e_aq_desc)),\n\t\t\t\t\t I40E_ADMINQ_DESC_ALIGNMENT);\n\tif (ret_code)\n\t\treturn ret_code;\n\n\tret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf,\n\t\t\t\t\t (hw->aq.num_asq_entries *\n\t\t\t\t\t sizeof(struct i40e_asq_cmd_details)));\n\tif (ret_code) {\n\t\ti40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);\n\t\treturn ret_code;\n\t}\n\n\treturn ret_code;\n}\n\n/**\n * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings\n * @hw: pointer to the hardware structure\n **/\nenum i40e_status_code i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code;\n\n\tret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,\n\t\t\t\t\t i40e_mem_arq_ring,\n\t\t\t\t\t (hw->aq.num_arq_entries *\n\t\t\t\t\t sizeof(struct i40e_aq_desc)),\n\t\t\t\t\t I40E_ADMINQ_DESC_ALIGNMENT);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_free_adminq_asq - Free Admin Queue send rings\n * @hw: pointer to the hardware structure\n *\n * This assumes the posted send buffers have already been cleaned\n * and de-allocated\n **/\nvoid i40e_free_adminq_asq(struct i40e_hw *hw)\n{\n\ti40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);\n}\n\n/**\n * i40e_free_adminq_arq - Free Admin Queue receive rings\n * @hw: pointer to the hardware structure\n *\n * This assumes the posted receive buffers have already been cleaned\n * and de-allocated\n **/\nvoid i40e_free_adminq_arq(struct i40e_hw *hw)\n{\n\ti40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);\n}\n\n/**\n * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue\n * @hw: pointer to the hardware structure\n **/\nSTATIC enum i40e_status_code i40e_alloc_arq_bufs(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code;\n\tstruct i40e_aq_desc *desc;\n\tstruct i40e_dma_mem *bi;\n\tint i;\n\n\t/* We'll be allocating the buffer info memory first, then we can\n\t * allocate the mapped buffers for the event processing\n\t */\n\n\t/* buffer_info structures do not need alignment */\n\tret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,\n\t\t(hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));\n\tif (ret_code)\n\t\tgoto alloc_arq_bufs;\n\thw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;\n\n\t/* allocate the mapped buffers */\n\tfor (i = 0; i < hw->aq.num_arq_entries; i++) {\n\t\tbi = &hw->aq.arq.r.arq_bi[i];\n\t\tret_code = i40e_allocate_dma_mem(hw, bi,\n\t\t\t\t\t\t i40e_mem_arq_buf,\n\t\t\t\t\t\t hw->aq.arq_buf_size,\n\t\t\t\t\t\t I40E_ADMINQ_DESC_ALIGNMENT);\n\t\tif (ret_code)\n\t\t\tgoto unwind_alloc_arq_bufs;\n\n\t\t/* now configure the descriptors for use */\n\t\tdesc = I40E_ADMINQ_DESC(hw->aq.arq, i);\n\n\t\tdesc->flags = CPU_TO_LE16(I40E_AQ_FLAG_BUF);\n\t\tif (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)\n\t\t\tdesc->flags |= CPU_TO_LE16(I40E_AQ_FLAG_LB);\n\t\tdesc->opcode = 0;\n\t\t/* This is in accordance with Admin queue design, there is no\n\t\t * register for buffer size configuration\n\t\t */\n\t\tdesc->datalen = CPU_TO_LE16((u16)bi->size);\n\t\tdesc->retval = 0;\n\t\tdesc->cookie_high = 0;\n\t\tdesc->cookie_low = 0;\n\t\tdesc->params.external.addr_high =\n\t\t\tCPU_TO_LE32(I40E_HI_DWORD(bi->pa));\n\t\tdesc->params.external.addr_low =\n\t\t\tCPU_TO_LE32(I40E_LO_DWORD(bi->pa));\n\t\tdesc->params.external.param0 = 0;\n\t\tdesc->params.external.param1 = 0;\n\t}\n\nalloc_arq_bufs:\n\treturn ret_code;\n\nunwind_alloc_arq_bufs:\n\t/* don't try to free the one that failed... */\n\ti--;\n\tfor (; i >= 0; i--)\n\t\ti40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);\n\ti40e_free_virt_mem(hw, &hw->aq.arq.dma_head);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue\n * @hw: pointer to the hardware structure\n **/\nSTATIC enum i40e_status_code i40e_alloc_asq_bufs(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code;\n\tstruct i40e_dma_mem *bi;\n\tint i;\n\n\t/* No mapped memory needed yet, just the buffer info structures */\n\tret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head,\n\t\t(hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem)));\n\tif (ret_code)\n\t\tgoto alloc_asq_bufs;\n\thw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va;\n\n\t/* allocate the mapped buffers */\n\tfor (i = 0; i < hw->aq.num_asq_entries; i++) {\n\t\tbi = &hw->aq.asq.r.asq_bi[i];\n\t\tret_code = i40e_allocate_dma_mem(hw, bi,\n\t\t\t\t\t\t i40e_mem_asq_buf,\n\t\t\t\t\t\t hw->aq.asq_buf_size,\n\t\t\t\t\t\t I40E_ADMINQ_DESC_ALIGNMENT);\n\t\tif (ret_code)\n\t\t\tgoto unwind_alloc_asq_bufs;\n\t}\nalloc_asq_bufs:\n\treturn ret_code;\n\nunwind_alloc_asq_bufs:\n\t/* don't try to free the one that failed... */\n\ti--;\n\tfor (; i >= 0; i--)\n\t\ti40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);\n\ti40e_free_virt_mem(hw, &hw->aq.asq.dma_head);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_free_arq_bufs - Free receive queue buffer info elements\n * @hw: pointer to the hardware structure\n **/\nSTATIC void i40e_free_arq_bufs(struct i40e_hw *hw)\n{\n\tint i;\n\n\t/* free descriptors */\n\tfor (i = 0; i < hw->aq.num_arq_entries; i++)\n\t\ti40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);\n\n\t/* free the descriptor memory */\n\ti40e_free_dma_mem(hw, &hw->aq.arq.desc_buf);\n\n\t/* free the dma header */\n\ti40e_free_virt_mem(hw, &hw->aq.arq.dma_head);\n}\n\n/**\n * i40e_free_asq_bufs - Free send queue buffer info elements\n * @hw: pointer to the hardware structure\n **/\nSTATIC void i40e_free_asq_bufs(struct i40e_hw *hw)\n{\n\tint i;\n\n\t/* only unmap if the address is non-NULL */\n\tfor (i = 0; i < hw->aq.num_asq_entries; i++)\n\t\tif (hw->aq.asq.r.asq_bi[i].pa)\n\t\t\ti40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);\n\n\t/* free the buffer info list */\n\ti40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf);\n\n\t/* free the descriptor memory */\n\ti40e_free_dma_mem(hw, &hw->aq.asq.desc_buf);\n\n\t/* free the dma header */\n\ti40e_free_virt_mem(hw, &hw->aq.asq.dma_head);\n}\n\n/**\n * i40e_config_asq_regs - configure ASQ registers\n * @hw: pointer to the hardware structure\n *\n * Configure base address and length registers for the transmit queue\n **/\nSTATIC enum i40e_status_code i40e_config_asq_regs(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tu32 reg = 0;\n\n\t/* Clear Head and Tail */\n\twr32(hw, hw->aq.asq.head, 0);\n\twr32(hw, hw->aq.asq.tail, 0);\n\n\t/* set starting point */\n\twr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |\n\t\t\t\t I40E_PF_ATQLEN_ATQENABLE_MASK));\n\twr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa));\n\twr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa));\n\n\t/* Check one register to verify that config was applied */\n\treg = rd32(hw, hw->aq.asq.bal);\n\tif (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa))\n\t\tret_code = I40E_ERR_ADMIN_QUEUE_ERROR;\n\n\treturn ret_code;\n}\n\n/**\n * i40e_config_arq_regs - ARQ register configuration\n * @hw: pointer to the hardware structure\n *\n * Configure base address and length registers for the receive (event queue)\n **/\nSTATIC enum i40e_status_code i40e_config_arq_regs(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tu32 reg = 0;\n\n\t/* Clear Head and Tail */\n\twr32(hw, hw->aq.arq.head, 0);\n\twr32(hw, hw->aq.arq.tail, 0);\n\n\t/* set starting point */\n\twr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |\n\t\t\t\t I40E_PF_ARQLEN_ARQENABLE_MASK));\n\twr32(hw, hw->aq.arq.bal, I40E_LO_DWORD(hw->aq.arq.desc_buf.pa));\n\twr32(hw, hw->aq.arq.bah, I40E_HI_DWORD(hw->aq.arq.desc_buf.pa));\n\n\t/* Update tail in the HW to post pre-allocated buffers */\n\twr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);\n\n\t/* Check one register to verify that config was applied */\n\treg = rd32(hw, hw->aq.arq.bal);\n\tif (reg != I40E_LO_DWORD(hw->aq.arq.desc_buf.pa))\n\t\tret_code = I40E_ERR_ADMIN_QUEUE_ERROR;\n\n\treturn ret_code;\n}\n\n/**\n * i40e_init_asq - main initialization routine for ASQ\n * @hw: pointer to the hardware structure\n *\n * This is the main initialization routine for the Admin Send Queue\n * Prior to calling this function, drivers *MUST* set the following fields\n * in the hw->aq structure:\n * - hw->aq.num_asq_entries\n * - hw->aq.arq_buf_size\n *\n * Do *NOT* hold the lock when calling this as the memory allocation routines\n * called are not going to be atomic context safe\n **/\nenum i40e_status_code i40e_init_asq(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\n\tif (hw->aq.asq.count > 0) {\n\t\t/* queue already initialized */\n\t\tret_code = I40E_ERR_NOT_READY;\n\t\tgoto init_adminq_exit;\n\t}\n\n\t/* verify input for valid configuration */\n\tif ((hw->aq.num_asq_entries == 0) ||\n\t (hw->aq.asq_buf_size == 0)) {\n\t\tret_code = I40E_ERR_CONFIG;\n\t\tgoto init_adminq_exit;\n\t}\n\n\thw->aq.asq.next_to_use = 0;\n\thw->aq.asq.next_to_clean = 0;\n\thw->aq.asq.count = hw->aq.num_asq_entries;\n\n\t/* allocate the ring memory */\n\tret_code = i40e_alloc_adminq_asq_ring(hw);\n\tif (ret_code != I40E_SUCCESS)\n\t\tgoto init_adminq_exit;\n\n\t/* allocate buffers in the rings */\n\tret_code = i40e_alloc_asq_bufs(hw);\n\tif (ret_code != I40E_SUCCESS)\n\t\tgoto init_adminq_free_rings;\n\n\t/* initialize base registers */\n\tret_code = i40e_config_asq_regs(hw);\n\tif (ret_code != I40E_SUCCESS)\n\t\tgoto init_adminq_free_rings;\n\n\t/* success! */\n\tgoto init_adminq_exit;\n\ninit_adminq_free_rings:\n\ti40e_free_adminq_asq(hw);\n\ninit_adminq_exit:\n\treturn ret_code;\n}\n\n/**\n * i40e_init_arq - initialize ARQ\n * @hw: pointer to the hardware structure\n *\n * The main initialization routine for the Admin Receive (Event) Queue.\n * Prior to calling this function, drivers *MUST* set the following fields\n * in the hw->aq structure:\n * - hw->aq.num_asq_entries\n * - hw->aq.arq_buf_size\n *\n * Do *NOT* hold the lock when calling this as the memory allocation routines\n * called are not going to be atomic context safe\n **/\nenum i40e_status_code i40e_init_arq(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\n\tif (hw->aq.arq.count > 0) {\n\t\t/* queue already initialized */\n\t\tret_code = I40E_ERR_NOT_READY;\n\t\tgoto init_adminq_exit;\n\t}\n\n\t/* verify input for valid configuration */\n\tif ((hw->aq.num_arq_entries == 0) ||\n\t (hw->aq.arq_buf_size == 0)) {\n\t\tret_code = I40E_ERR_CONFIG;\n\t\tgoto init_adminq_exit;\n\t}\n\n\thw->aq.arq.next_to_use = 0;\n\thw->aq.arq.next_to_clean = 0;\n\thw->aq.arq.count = hw->aq.num_arq_entries;\n\n\t/* allocate the ring memory */\n\tret_code = i40e_alloc_adminq_arq_ring(hw);\n\tif (ret_code != I40E_SUCCESS)\n\t\tgoto init_adminq_exit;\n\n\t/* allocate buffers in the rings */\n\tret_code = i40e_alloc_arq_bufs(hw);\n\tif (ret_code != I40E_SUCCESS)\n\t\tgoto init_adminq_free_rings;\n\n\t/* initialize base registers */\n\tret_code = i40e_config_arq_regs(hw);\n\tif (ret_code != I40E_SUCCESS)\n\t\tgoto init_adminq_free_rings;\n\n\t/* success! */\n\tgoto init_adminq_exit;\n\ninit_adminq_free_rings:\n\ti40e_free_adminq_arq(hw);\n\ninit_adminq_exit:\n\treturn ret_code;\n}\n\n/**\n * i40e_shutdown_asq - shutdown the ASQ\n * @hw: pointer to the hardware structure\n *\n * The main shutdown routine for the Admin Send Queue\n **/\nenum i40e_status_code i40e_shutdown_asq(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\n\tif (hw->aq.asq.count == 0)\n\t\treturn I40E_ERR_NOT_READY;\n\n\t/* Stop firmware AdminQ processing */\n\twr32(hw, hw->aq.asq.head, 0);\n\twr32(hw, hw->aq.asq.tail, 0);\n\twr32(hw, hw->aq.asq.len, 0);\n\twr32(hw, hw->aq.asq.bal, 0);\n\twr32(hw, hw->aq.asq.bah, 0);\n\n\t/* make sure spinlock is available */\n\ti40e_acquire_spinlock(&hw->aq.asq_spinlock);\n\n\thw->aq.asq.count = 0; /* to indicate uninitialized queue */\n\n\t/* free ring buffers */\n\ti40e_free_asq_bufs(hw);\n\n\ti40e_release_spinlock(&hw->aq.asq_spinlock);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_shutdown_arq - shutdown ARQ\n * @hw: pointer to the hardware structure\n *\n * The main shutdown routine for the Admin Receive Queue\n **/\nenum i40e_status_code i40e_shutdown_arq(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\n\tif (hw->aq.arq.count == 0)\n\t\treturn I40E_ERR_NOT_READY;\n\n\t/* Stop firmware AdminQ processing */\n\twr32(hw, hw->aq.arq.head, 0);\n\twr32(hw, hw->aq.arq.tail, 0);\n\twr32(hw, hw->aq.arq.len, 0);\n\twr32(hw, hw->aq.arq.bal, 0);\n\twr32(hw, hw->aq.arq.bah, 0);\n\n\t/* make sure spinlock is available */\n\ti40e_acquire_spinlock(&hw->aq.arq_spinlock);\n\n\thw->aq.arq.count = 0; /* to indicate uninitialized queue */\n\n\t/* free ring buffers */\n\ti40e_free_arq_bufs(hw);\n\n\ti40e_release_spinlock(&hw->aq.arq_spinlock);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_init_adminq - main initialization routine for Admin Queue\n * @hw: pointer to the hardware structure\n *\n * Prior to calling this function, drivers *MUST* set the following fields\n * in the hw->aq structure:\n * - hw->aq.num_asq_entries\n * - hw->aq.num_arq_entries\n * - hw->aq.arq_buf_size\n * - hw->aq.asq_buf_size\n **/\nenum i40e_status_code i40e_init_adminq(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code;\n#ifdef PF_DRIVER\n\tu16 eetrack_lo, eetrack_hi;\n\tint retry = 0;\n#endif\n\t/* verify input for valid configuration */\n\tif ((hw->aq.num_arq_entries == 0) ||\n\t (hw->aq.num_asq_entries == 0) ||\n\t (hw->aq.arq_buf_size == 0) ||\n\t (hw->aq.asq_buf_size == 0)) {\n\t\tret_code = I40E_ERR_CONFIG;\n\t\tgoto init_adminq_exit;\n\t}\n\n\t/* initialize spin locks */\n\ti40e_init_spinlock(&hw->aq.asq_spinlock);\n\ti40e_init_spinlock(&hw->aq.arq_spinlock);\n\n\t/* Set up register offsets */\n\ti40e_adminq_init_regs(hw);\n\n\t/* setup ASQ command write back timeout */\n\thw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT;\n\n\t/* allocate the ASQ */\n\tret_code = i40e_init_asq(hw);\n\tif (ret_code != I40E_SUCCESS)\n\t\tgoto init_adminq_destroy_spinlocks;\n\n\t/* allocate the ARQ */\n\tret_code = i40e_init_arq(hw);\n\tif (ret_code != I40E_SUCCESS)\n\t\tgoto init_adminq_free_asq;\n\n#ifdef PF_DRIVER\n#ifdef INTEGRATED_VF\n\t/* VF has no need of firmware */\n\tif (i40e_is_vf(hw))\n\t\tgoto init_adminq_exit;\n#endif\n\t/* There are some cases where the firmware may not be quite ready\n\t * for AdminQ operations, so we retry the AdminQ setup a few times\n\t * if we see timeouts in this first AQ call.\n\t */\n\tdo {\n\t\tret_code = i40e_aq_get_firmware_version(hw,\n\t\t\t\t\t\t\t&hw->aq.fw_maj_ver,\n\t\t\t\t\t\t\t&hw->aq.fw_min_ver,\n\t\t\t\t\t\t\t&hw->aq.fw_build,\n\t\t\t\t\t\t\t&hw->aq.api_maj_ver,\n\t\t\t\t\t\t\t&hw->aq.api_min_ver,\n\t\t\t\t\t\t\tNULL);\n\t\tif (ret_code != I40E_ERR_ADMIN_QUEUE_TIMEOUT)\n\t\t\tbreak;\n\t\tretry++;\n\t\ti40e_msec_delay(100);\n\t\ti40e_resume_aq(hw);\n\t} while (retry < 10);\n\tif (ret_code != I40E_SUCCESS)\n\t\tgoto init_adminq_free_arq;\n\n\t/* get the NVM version info */\n\ti40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION,\n\t\t\t &hw->nvm.version);\n\ti40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);\n\ti40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);\n\thw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;\n\n\tif (hw->aq.api_maj_ver > I40E_FW_API_VERSION_MAJOR) {\n\t\tret_code = I40E_ERR_FIRMWARE_API_VERSION;\n\t\tgoto init_adminq_free_arq;\n\t}\n\n\t/* pre-emptive resource lock release */\n\ti40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);\n\thw->aq.nvm_release_on_done = false;\n\thw->nvmupd_state = I40E_NVMUPD_STATE_INIT;\n\n\tret_code = i40e_aq_set_hmc_resource_profile(hw,\n\t\t\t\t\t\t I40E_HMC_PROFILE_DEFAULT,\n\t\t\t\t\t\t 0,\n\t\t\t\t\t\t NULL);\n#endif /* PF_DRIVER */\n\tret_code = I40E_SUCCESS;\n\n\t/* success! */\n\tgoto init_adminq_exit;\n\n#ifdef PF_DRIVER\ninit_adminq_free_arq:\n\ti40e_shutdown_arq(hw);\n#endif\ninit_adminq_free_asq:\n\ti40e_shutdown_asq(hw);\ninit_adminq_destroy_spinlocks:\n\ti40e_destroy_spinlock(&hw->aq.asq_spinlock);\n\ti40e_destroy_spinlock(&hw->aq.arq_spinlock);\n\ninit_adminq_exit:\n\treturn ret_code;\n}\n\n/**\n * i40e_shutdown_adminq - shutdown routine for the Admin Queue\n * @hw: pointer to the hardware structure\n **/\nenum i40e_status_code i40e_shutdown_adminq(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\n\tif (i40e_check_asq_alive(hw))\n\t\ti40e_aq_queue_shutdown(hw, true);\n\n\ti40e_shutdown_asq(hw);\n\ti40e_shutdown_arq(hw);\n\n\t/* destroy the spinlocks */\n\ti40e_destroy_spinlock(&hw->aq.asq_spinlock);\n\ti40e_destroy_spinlock(&hw->aq.arq_spinlock);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_clean_asq - cleans Admin send queue\n * @hw: pointer to the hardware structure\n *\n * returns the number of free desc\n **/\nu16 i40e_clean_asq(struct i40e_hw *hw)\n{\n\tstruct i40e_adminq_ring *asq = &(hw->aq.asq);\n\tstruct i40e_asq_cmd_details *details;\n\tu16 ntc = asq->next_to_clean;\n\tstruct i40e_aq_desc desc_cb;\n\tstruct i40e_aq_desc *desc;\n\n\tdesc = I40E_ADMINQ_DESC(*asq, ntc);\n\tdetails = I40E_ADMINQ_DETAILS(*asq, ntc);\n\twhile (rd32(hw, hw->aq.asq.head) != ntc) {\n\t\ti40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,\n\t\t\t \"%s: ntc %d head %d.\\n\", __FUNCTION__, ntc,\n\t\t\t rd32(hw, hw->aq.asq.head));\n\n\t\tif (details->callback) {\n\t\t\tI40E_ADMINQ_CALLBACK cb_func =\n\t\t\t\t\t(I40E_ADMINQ_CALLBACK)details->callback;\n\t\t\ti40e_memcpy(&desc_cb, desc,\n\t\t\t sizeof(struct i40e_aq_desc), I40E_DMA_TO_DMA);\n\t\t\tcb_func(hw, &desc_cb);\n\t\t}\n\t\ti40e_memset(desc, 0, sizeof(*desc), I40E_DMA_MEM);\n\t\ti40e_memset(details, 0, sizeof(*details), I40E_NONDMA_MEM);\n\t\tntc++;\n\t\tif (ntc == asq->count)\n\t\t\tntc = 0;\n\t\tdesc = I40E_ADMINQ_DESC(*asq, ntc);\n\t\tdetails = I40E_ADMINQ_DETAILS(*asq, ntc);\n\t}\n\n\tasq->next_to_clean = ntc;\n\n\treturn I40E_DESC_UNUSED(asq);\n}\n\n/**\n * i40e_asq_done - check if FW has processed the Admin Send Queue\n * @hw: pointer to the hw struct\n *\n * Returns true if the firmware has processed all descriptors on the\n * admin send queue. Returns false if there are still requests pending.\n **/\nbool i40e_asq_done(struct i40e_hw *hw)\n{\n\t/* AQ designers suggest use of head for better\n\t * timing reliability than DD bit\n\t */\n\treturn rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;\n\n}\n\n/**\n * i40e_asq_send_command - send command to Admin Queue\n * @hw: pointer to the hw struct\n * @desc: prefilled descriptor describing the command (non DMA mem)\n * @buff: buffer to use for indirect commands\n * @buff_size: size of buffer for indirect commands\n * @cmd_details: pointer to command details structure\n *\n * This is the main send command driver routine for the Admin Queue send\n * queue. It runs the queue, cleans the queue, etc\n **/\nenum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_aq_desc *desc,\n\t\t\t\tvoid *buff, /* can be NULL */\n\t\t\t\tu16 buff_size,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tenum i40e_status_code status = I40E_SUCCESS;\n\tstruct i40e_dma_mem *dma_buff = NULL;\n\tstruct i40e_asq_cmd_details *details;\n\tstruct i40e_aq_desc *desc_on_ring;\n\tbool cmd_completed = false;\n\tu16 retval = 0;\n\tu32 val = 0;\n\n\tval = rd32(hw, hw->aq.asq.head);\n\tif (val >= hw->aq.num_asq_entries) {\n\t\ti40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,\n\t\t\t \"AQTX: head overrun at %d\\n\", val);\n\t\tstatus = I40E_ERR_QUEUE_EMPTY;\n\t\tgoto asq_send_command_exit;\n\t}\n\n\tif (hw->aq.asq.count == 0) {\n\t\ti40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,\n\t\t\t \"AQTX: Admin queue not initialized.\\n\");\n\t\tstatus = I40E_ERR_QUEUE_EMPTY;\n\t\tgoto asq_send_command_exit;\n\t}\n\n\tdetails = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);\n\tif (cmd_details) {\n\t\ti40e_memcpy(details,\n\t\t\t cmd_details,\n\t\t\t sizeof(struct i40e_asq_cmd_details),\n\t\t\t I40E_NONDMA_TO_NONDMA);\n\n\t\t/* If the cmd_details are defined copy the cookie. The\n\t\t * CPU_TO_LE32 is not needed here because the data is ignored\n\t\t * by the FW, only used by the driver\n\t\t */\n\t\tif (details->cookie) {\n\t\t\tdesc->cookie_high =\n\t\t\t\tCPU_TO_LE32(I40E_HI_DWORD(details->cookie));\n\t\t\tdesc->cookie_low =\n\t\t\t\tCPU_TO_LE32(I40E_LO_DWORD(details->cookie));\n\t\t}\n\t} else {\n\t\ti40e_memset(details, 0,\n\t\t\t sizeof(struct i40e_asq_cmd_details),\n\t\t\t I40E_NONDMA_MEM);\n\t}\n\n\t/* clear requested flags and then set additional flags if defined */\n\tdesc->flags &= ~CPU_TO_LE16(details->flags_dis);\n\tdesc->flags |= CPU_TO_LE16(details->flags_ena);\n\n\ti40e_acquire_spinlock(&hw->aq.asq_spinlock);\n\n\tif (buff_size > hw->aq.asq_buf_size) {\n\t\ti40e_debug(hw,\n\t\t\t I40E_DEBUG_AQ_MESSAGE,\n\t\t\t \"AQTX: Invalid buffer size: %d.\\n\",\n\t\t\t buff_size);\n\t\tstatus = I40E_ERR_INVALID_SIZE;\n\t\tgoto asq_send_command_error;\n\t}\n\n\tif (details->postpone && !details->async) {\n\t\ti40e_debug(hw,\n\t\t\t I40E_DEBUG_AQ_MESSAGE,\n\t\t\t \"AQTX: Async flag not set along with postpone flag\");\n\t\tstatus = I40E_ERR_PARAM;\n\t\tgoto asq_send_command_error;\n\t}\n\n\t/* call clean and check queue available function to reclaim the\n\t * descriptors that were processed by FW, the function returns the\n\t * number of desc available\n\t */\n\t/* the clean function called here could be called in a separate thread\n\t * in case of asynchronous completions\n\t */\n\tif (i40e_clean_asq(hw) == 0) {\n\t\ti40e_debug(hw,\n\t\t\t I40E_DEBUG_AQ_MESSAGE,\n\t\t\t \"AQTX: Error queue is full.\\n\");\n\t\tstatus = I40E_ERR_ADMIN_QUEUE_FULL;\n\t\tgoto asq_send_command_error;\n\t}\n\n\t/* initialize the temp desc pointer with the right desc */\n\tdesc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);\n\n\t/* if the desc is available copy the temp desc to the right place */\n\ti40e_memcpy(desc_on_ring, desc, sizeof(struct i40e_aq_desc),\n\t\t I40E_NONDMA_TO_DMA);\n\n\t/* if buff is not NULL assume indirect command */\n\tif (buff != NULL) {\n\t\tdma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);\n\t\t/* copy the user buff into the respective DMA buff */\n\t\ti40e_memcpy(dma_buff->va, buff, buff_size,\n\t\t\t I40E_NONDMA_TO_DMA);\n\t\tdesc_on_ring->datalen = CPU_TO_LE16(buff_size);\n\n\t\t/* Update the address values in the desc with the pa value\n\t\t * for respective buffer\n\t\t */\n\t\tdesc_on_ring->params.external.addr_high =\n\t\t\t\tCPU_TO_LE32(I40E_HI_DWORD(dma_buff->pa));\n\t\tdesc_on_ring->params.external.addr_low =\n\t\t\t\tCPU_TO_LE32(I40E_LO_DWORD(dma_buff->pa));\n\t}\n\n\t/* bump the tail */\n\ti40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, \"AQTX: desc and buffer:\\n\");\n\ti40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,\n\t\t buff, buff_size);\n\t(hw->aq.asq.next_to_use)++;\n\tif (hw->aq.asq.next_to_use == hw->aq.asq.count)\n\t\thw->aq.asq.next_to_use = 0;\n\tif (!details->postpone)\n\t\twr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);\n\n\t/* if cmd_details are not defined or async flag is not set,\n\t * we need to wait for desc write back\n\t */\n\tif (!details->async && !details->postpone) {\n\t\tu32 total_delay = 0;\n\n\t\tdo {\n\t\t\t/* AQ designers suggest use of head for better\n\t\t\t * timing reliability than DD bit\n\t\t\t */\n\t\t\tif (i40e_asq_done(hw))\n\t\t\t\tbreak;\n\t\t\t/* ugh! delay while spin_lock */\n\t\t\ti40e_msec_delay(1);\n\t\t\ttotal_delay++;\n\t\t} while (total_delay < hw->aq.asq_cmd_timeout);\n\t}\n\n\t/* if ready, copy the desc back to temp */\n\tif (i40e_asq_done(hw)) {\n\t\ti40e_memcpy(desc, desc_on_ring, sizeof(struct i40e_aq_desc),\n\t\t\t I40E_DMA_TO_NONDMA);\n\t\tif (buff != NULL)\n\t\t\ti40e_memcpy(buff, dma_buff->va, buff_size,\n\t\t\t\t I40E_DMA_TO_NONDMA);\n\t\tretval = LE16_TO_CPU(desc->retval);\n\t\tif (retval != 0) {\n\t\t\ti40e_debug(hw,\n\t\t\t\t I40E_DEBUG_AQ_MESSAGE,\n\t\t\t\t \"AQTX: Command completed with error 0x%X.\\n\",\n\t\t\t\t retval);\n\n\t\t\t/* strip off FW internal code */\n\t\t\tretval &= 0xff;\n\t\t}\n\t\tcmd_completed = true;\n\t\tif ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)\n\t\t\tstatus = I40E_SUCCESS;\n\t\telse\n\t\t\tstatus = I40E_ERR_ADMIN_QUEUE_ERROR;\n\t\thw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;\n\t}\n\n\ti40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,\n\t\t \"AQTX: desc and buffer writeback:\\n\");\n\ti40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);\n\n\t/* update the error if time out occurred */\n\tif ((!cmd_completed) &&\n\t (!details->async && !details->postpone)) {\n\t\ti40e_debug(hw,\n\t\t\t I40E_DEBUG_AQ_MESSAGE,\n\t\t\t \"AQTX: Writeback timeout.\\n\");\n\t\tstatus = I40E_ERR_ADMIN_QUEUE_TIMEOUT;\n\t}\n\nasq_send_command_error:\n\ti40e_release_spinlock(&hw->aq.asq_spinlock);\nasq_send_command_exit:\n\treturn status;\n}\n\n/**\n * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function\n * @desc: pointer to the temp descriptor (non DMA mem)\n * @opcode: the opcode can be used to decide which flags to turn off or on\n *\n * Fill the desc with default values\n **/\nvoid i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,\n\t\t\t\t u16 opcode)\n{\n\t/* zero out the desc */\n\ti40e_memset((void *)desc, 0, sizeof(struct i40e_aq_desc),\n\t\t I40E_NONDMA_MEM);\n\tdesc->opcode = CPU_TO_LE16(opcode);\n\tdesc->flags = CPU_TO_LE16(I40E_AQ_FLAG_SI);\n}\n\n/**\n * i40e_clean_arq_element\n * @hw: pointer to the hw struct\n * @e: event info from the receive descriptor, includes any buffers\n * @pending: number of events that could be left to process\n *\n * This function cleans one Admin Receive Queue element and returns\n * the contents through e. It can also return how many events are\n * left to process through 'pending'\n **/\nenum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_arq_event_info *e,\n\t\t\t\t\t u16 *pending)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tu16 ntc = hw->aq.arq.next_to_clean;\n\tstruct i40e_aq_desc *desc;\n\tstruct i40e_dma_mem *bi;\n\tu16 desc_idx;\n\tu16 datalen;\n\tu16 flags;\n\tu16 ntu;\n\n\t/* take the lock before we start messing with the ring */\n\ti40e_acquire_spinlock(&hw->aq.arq_spinlock);\n\n\t/* set next_to_use to head */\n\tntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);\n\tif (ntu == ntc) {\n\t\t/* nothing to do - shouldn't need to update ring's values */\n\t\tret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;\n\t\tgoto clean_arq_element_out;\n\t}\n\n\t/* now clean the next descriptor */\n\tdesc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);\n\tdesc_idx = ntc;\n\n\tflags = LE16_TO_CPU(desc->flags);\n\tif (flags & I40E_AQ_FLAG_ERR) {\n\t\tret_code = I40E_ERR_ADMIN_QUEUE_ERROR;\n\t\thw->aq.arq_last_status =\n\t\t\t(enum i40e_admin_queue_err)LE16_TO_CPU(desc->retval);\n\t\ti40e_debug(hw,\n\t\t\t I40E_DEBUG_AQ_MESSAGE,\n\t\t\t \"AQRX: Event received with error 0x%X.\\n\",\n\t\t\t hw->aq.arq_last_status);\n\t}\n\n\ti40e_memcpy(&e->desc, desc, sizeof(struct i40e_aq_desc),\n\t\t I40E_DMA_TO_NONDMA);\n\tdatalen = LE16_TO_CPU(desc->datalen);\n\te->msg_len = min(datalen, e->buf_len);\n\tif (e->msg_buf != NULL && (e->msg_len != 0))\n\t\ti40e_memcpy(e->msg_buf,\n\t\t\t hw->aq.arq.r.arq_bi[desc_idx].va,\n\t\t\t e->msg_len, I40E_DMA_TO_NONDMA);\n\n\ti40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, \"AQRX: desc and buffer:\\n\");\n\ti40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,\n\t\t hw->aq.arq_buf_size);\n\n\t/* Restore the original datalen and buffer address in the desc,\n\t * FW updates datalen to indicate the event message\n\t * size\n\t */\n\tbi = &hw->aq.arq.r.arq_bi[ntc];\n\ti40e_memset((void *)desc, 0, sizeof(struct i40e_aq_desc), I40E_DMA_MEM);\n\n\tdesc->flags = CPU_TO_LE16(I40E_AQ_FLAG_BUF);\n\tif (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)\n\t\tdesc->flags |= CPU_TO_LE16(I40E_AQ_FLAG_LB);\n\tdesc->datalen = CPU_TO_LE16((u16)bi->size);\n\tdesc->params.external.addr_high = CPU_TO_LE32(I40E_HI_DWORD(bi->pa));\n\tdesc->params.external.addr_low = CPU_TO_LE32(I40E_LO_DWORD(bi->pa));\n\n\t/* set tail = the last cleaned desc index. */\n\twr32(hw, hw->aq.arq.tail, ntc);\n\t/* ntc is updated to tail + 1 */\n\tntc++;\n\tif (ntc == hw->aq.num_arq_entries)\n\t\tntc = 0;\n\thw->aq.arq.next_to_clean = ntc;\n\thw->aq.arq.next_to_use = ntu;\n\nclean_arq_element_out:\n\t/* Set pending if needed, unlock and return */\n\tif (pending != NULL)\n\t\t*pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);\n\ti40e_release_spinlock(&hw->aq.arq_spinlock);\n\n#ifdef PF_DRIVER\n\tif (i40e_is_nvm_update_op(&e->desc)) {\n\t\tif (hw->aq.nvm_release_on_done) {\n\t\t\ti40e_release_nvm(hw);\n\t\t\thw->aq.nvm_release_on_done = false;\n\t\t}\n\t}\n\n#endif\n\treturn ret_code;\n}\n\nvoid i40e_resume_aq(struct i40e_hw *hw)\n{\n\t/* Registers are reset after PF reset */\n\thw->aq.asq.next_to_use = 0;\n\thw->aq.asq.next_to_clean = 0;\n\n#if (I40E_VF_ATQLEN_ATQENABLE_MASK != I40E_PF_ATQLEN_ATQENABLE_MASK)\n#error I40E_VF_ATQLEN_ATQENABLE_MASK != I40E_PF_ATQLEN_ATQENABLE_MASK\n#endif\n\ti40e_config_asq_regs(hw);\n\n\thw->aq.arq.next_to_use = 0;\n\thw->aq.arq.next_to_clean = 0;\n\n\ti40e_config_arq_regs(hw);\n}\n" }, { "path": "drivers/net/i40e/base/i40e_adminq.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _I40E_ADMINQ_H_\n#define _I40E_ADMINQ_H_\n\n#include \"i40e_osdep.h\"\n#include \"i40e_status.h\"\n#include \"i40e_adminq_cmd.h\"\n\n#define I40E_ADMINQ_DESC(R, i) \\\n\t(&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))\n\n#define I40E_ADMINQ_DESC_ALIGNMENT 4096\n\nstruct i40e_adminq_ring {\n\tstruct i40e_virt_mem dma_head;\t/* space for dma structures */\n\tstruct i40e_dma_mem desc_buf;\t/* descriptor ring memory */\n\tstruct i40e_virt_mem cmd_buf;\t/* command buffer memory */\n\n\tunion {\n\t\tstruct i40e_dma_mem *asq_bi;\n\t\tstruct i40e_dma_mem *arq_bi;\n\t} r;\n\n\tu16 count;\t\t/* Number of descriptors */\n\tu16 rx_buf_len;\t\t/* Admin Receive Queue buffer length */\n\n\t/* used for interrupt processing */\n\tu16 next_to_use;\n\tu16 next_to_clean;\n\n\t/* used for queue tracking */\n\tu32 head;\n\tu32 tail;\n\tu32 len;\n\tu32 bah;\n\tu32 bal;\n};\n\n/* ASQ transaction details */\nstruct i40e_asq_cmd_details {\n\tvoid *callback; /* cast from type I40E_ADMINQ_CALLBACK */\n\tu64 cookie;\n\tu16 flags_ena;\n\tu16 flags_dis;\n\tbool async;\n\tbool postpone;\n};\n\n#define I40E_ADMINQ_DETAILS(R, i) \\\n\t(&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))\n\n/* ARQ event information */\nstruct i40e_arq_event_info {\n\tstruct i40e_aq_desc desc;\n\tu16 msg_len;\n\tu16 buf_len;\n\tu8 *msg_buf;\n};\n\n/* Admin Queue information */\nstruct i40e_adminq_info {\n\tstruct i40e_adminq_ring arq; /* receive queue */\n\tstruct i40e_adminq_ring asq; /* send queue */\n\tu32 asq_cmd_timeout; /* send queue cmd write back timeout*/\n\tu16 num_arq_entries; /* receive queue depth */\n\tu16 num_asq_entries; /* send queue depth */\n\tu16 arq_buf_size; /* receive queue buffer size */\n\tu16 asq_buf_size; /* send queue buffer size */\n\tu16 fw_maj_ver; /* firmware major version */\n\tu16 fw_min_ver; /* firmware minor version */\n\tu32 fw_build; /* firmware build number */\n\tu16 api_maj_ver; /* api major version */\n\tu16 api_min_ver; /* api minor version */\n\tbool nvm_release_on_done;\n\n\tstruct i40e_spinlock asq_spinlock; /* Send queue spinlock */\n\tstruct i40e_spinlock arq_spinlock; /* Receive queue spinlock */\n\n\t/* last status values on send and receive queues */\n\tenum i40e_admin_queue_err asq_last_status;\n\tenum i40e_admin_queue_err arq_last_status;\n};\n\n/**\n * i40e_aq_rc_to_posix - convert errors to user-land codes\n * aq_rc: AdminQ error code to convert\n **/\nSTATIC inline int i40e_aq_rc_to_posix(int aq_ret, u16 aq_rc)\n{\n\tint aq_to_posix[] = {\n\t\t0, /* I40E_AQ_RC_OK */\n\t\t-EPERM, /* I40E_AQ_RC_EPERM */\n\t\t-ENOENT, /* I40E_AQ_RC_ENOENT */\n\t\t-ESRCH, /* I40E_AQ_RC_ESRCH */\n\t\t-EINTR, /* I40E_AQ_RC_EINTR */\n\t\t-EIO, /* I40E_AQ_RC_EIO */\n\t\t-ENXIO, /* I40E_AQ_RC_ENXIO */\n\t\t-E2BIG, /* I40E_AQ_RC_E2BIG */\n\t\t-EAGAIN, /* I40E_AQ_RC_EAGAIN */\n\t\t-ENOMEM, /* I40E_AQ_RC_ENOMEM */\n\t\t-EACCES, /* I40E_AQ_RC_EACCES */\n\t\t-EFAULT, /* I40E_AQ_RC_EFAULT */\n\t\t-EBUSY, /* I40E_AQ_RC_EBUSY */\n\t\t-EEXIST, /* I40E_AQ_RC_EEXIST */\n\t\t-EINVAL, /* I40E_AQ_RC_EINVAL */\n\t\t-ENOTTY, /* I40E_AQ_RC_ENOTTY */\n\t\t-ENOSPC, /* I40E_AQ_RC_ENOSPC */\n\t\t-ENOSYS, /* I40E_AQ_RC_ENOSYS */\n\t\t-ERANGE, /* I40E_AQ_RC_ERANGE */\n\t\t-EPIPE, /* I40E_AQ_RC_EFLUSHED */\n\t\t-ESPIPE, /* I40E_AQ_RC_BAD_ADDR */\n\t\t-EROFS, /* I40E_AQ_RC_EMODE */\n\t\t-EFBIG, /* I40E_AQ_RC_EFBIG */\n\t};\n\n\t/* aq_rc is invalid if AQ timed out */\n\tif (aq_ret == I40E_ERR_ADMIN_QUEUE_TIMEOUT)\n\t\treturn -EAGAIN;\n\n\tif (aq_rc >= (sizeof(aq_to_posix) / sizeof((aq_to_posix)[0])))\n\t\treturn -ERANGE;\n\treturn aq_to_posix[aq_rc];\n}\n\n/* general information */\n#define I40E_AQ_LARGE_BUF\t\t512\n#define I40E_ASQ_CMD_TIMEOUT\t\t250 /* msecs */\n\nvoid i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,\n\t\t\t\t u16 opcode);\n\n#endif /* _I40E_ADMINQ_H_ */\n" }, { "path": "drivers/net/i40e/base/i40e_adminq_cmd.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _I40E_ADMINQ_CMD_H_\n#define _I40E_ADMINQ_CMD_H_\n\n/* This header file defines the i40e Admin Queue commands and is shared between\n * i40e Firmware and Software.\n *\n * This file needs to comply with the Linux Kernel coding style.\n */\n\n#define I40E_FW_API_VERSION_MAJOR\t0x0001\n#define I40E_FW_API_VERSION_MINOR\t0x0002\n\nstruct i40e_aq_desc {\n\t__le16 flags;\n\t__le16 opcode;\n\t__le16 datalen;\n\t__le16 retval;\n\t__le32 cookie_high;\n\t__le32 cookie_low;\n\tunion {\n\t\tstruct {\n\t\t\t__le32 param0;\n\t\t\t__le32 param1;\n\t\t\t__le32 param2;\n\t\t\t__le32 param3;\n\t\t} internal;\n\t\tstruct {\n\t\t\t__le32 param0;\n\t\t\t__le32 param1;\n\t\t\t__le32 addr_high;\n\t\t\t__le32 addr_low;\n\t\t} external;\n\t\tu8 raw[16];\n\t} params;\n};\n\n/* Flags sub-structure\n * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |\n * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |\n */\n\n/* command flags and offsets*/\n#define I40E_AQ_FLAG_DD_SHIFT\t0\n#define I40E_AQ_FLAG_CMP_SHIFT\t1\n#define I40E_AQ_FLAG_ERR_SHIFT\t2\n#define I40E_AQ_FLAG_VFE_SHIFT\t3\n#define I40E_AQ_FLAG_LB_SHIFT\t9\n#define I40E_AQ_FLAG_RD_SHIFT\t10\n#define I40E_AQ_FLAG_VFC_SHIFT\t11\n#define I40E_AQ_FLAG_BUF_SHIFT\t12\n#define I40E_AQ_FLAG_SI_SHIFT\t13\n#define I40E_AQ_FLAG_EI_SHIFT\t14\n#define I40E_AQ_FLAG_FE_SHIFT\t15\n\n#define I40E_AQ_FLAG_DD\t\t(1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */\n#define I40E_AQ_FLAG_CMP\t(1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */\n#define I40E_AQ_FLAG_ERR\t(1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */\n#define I40E_AQ_FLAG_VFE\t(1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */\n#define I40E_AQ_FLAG_LB\t\t(1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */\n#define I40E_AQ_FLAG_RD\t\t(1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */\n#define I40E_AQ_FLAG_VFC\t(1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */\n#define I40E_AQ_FLAG_BUF\t(1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */\n#define I40E_AQ_FLAG_SI\t\t(1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */\n#define I40E_AQ_FLAG_EI\t\t(1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */\n#define I40E_AQ_FLAG_FE\t\t(1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */\n\n/* error codes */\nenum i40e_admin_queue_err {\n\tI40E_AQ_RC_OK\t\t= 0, /* success */\n\tI40E_AQ_RC_EPERM\t= 1, /* Operation not permitted */\n\tI40E_AQ_RC_ENOENT\t= 2, /* No such element */\n\tI40E_AQ_RC_ESRCH\t= 3, /* Bad opcode */\n\tI40E_AQ_RC_EINTR\t= 4, /* operation interrupted */\n\tI40E_AQ_RC_EIO\t\t= 5, /* I/O error */\n\tI40E_AQ_RC_ENXIO\t= 6, /* No such resource */\n\tI40E_AQ_RC_E2BIG\t= 7, /* Arg too long */\n\tI40E_AQ_RC_EAGAIN\t= 8, /* Try again */\n\tI40E_AQ_RC_ENOMEM\t= 9, /* Out of memory */\n\tI40E_AQ_RC_EACCES\t= 10, /* Permission denied */\n\tI40E_AQ_RC_EFAULT\t= 11, /* Bad address */\n\tI40E_AQ_RC_EBUSY\t= 12, /* Device or resource busy */\n\tI40E_AQ_RC_EEXIST\t= 13, /* object already exists */\n\tI40E_AQ_RC_EINVAL\t= 14, /* Invalid argument */\n\tI40E_AQ_RC_ENOTTY\t= 15, /* Not a typewriter */\n\tI40E_AQ_RC_ENOSPC\t= 16, /* No space left or alloc failure */\n\tI40E_AQ_RC_ENOSYS\t= 17, /* Function not implemented */\n\tI40E_AQ_RC_ERANGE\t= 18, /* Parameter out of range */\n\tI40E_AQ_RC_EFLUSHED\t= 19, /* Cmd flushed due to prev cmd error */\n\tI40E_AQ_RC_BAD_ADDR\t= 20, /* Descriptor contains a bad pointer */\n\tI40E_AQ_RC_EMODE\t= 21, /* Op not allowed in current dev mode */\n\tI40E_AQ_RC_EFBIG\t= 22, /* File too large */\n};\n\n/* Admin Queue command opcodes */\nenum i40e_admin_queue_opc {\n\t/* aq commands */\n\ti40e_aqc_opc_get_version\t= 0x0001,\n\ti40e_aqc_opc_driver_version\t= 0x0002,\n\ti40e_aqc_opc_queue_shutdown\t= 0x0003,\n\ti40e_aqc_opc_set_pf_context\t= 0x0004,\n\n\t/* resource ownership */\n\ti40e_aqc_opc_request_resource\t= 0x0008,\n\ti40e_aqc_opc_release_resource\t= 0x0009,\n\n\ti40e_aqc_opc_list_func_capabilities\t= 0x000A,\n\ti40e_aqc_opc_list_dev_capabilities\t= 0x000B,\n\n\ti40e_aqc_opc_set_cppm_configuration\t= 0x0103,\n\ti40e_aqc_opc_set_arp_proxy_entry\t= 0x0104,\n\ti40e_aqc_opc_set_ns_proxy_entry\t\t= 0x0105,\n\n\t/* LAA */\n\ti40e_aqc_opc_mng_laa\t\t= 0x0106, /* AQ obsolete */\n\ti40e_aqc_opc_mac_address_read\t= 0x0107,\n\ti40e_aqc_opc_mac_address_write\t= 0x0108,\n\n\t/* PXE */\n\ti40e_aqc_opc_clear_pxe_mode\t= 0x0110,\n\n\t/* internal switch commands */\n\ti40e_aqc_opc_get_switch_config\t\t= 0x0200,\n\ti40e_aqc_opc_add_statistics\t\t= 0x0201,\n\ti40e_aqc_opc_remove_statistics\t\t= 0x0202,\n\ti40e_aqc_opc_set_port_parameters\t= 0x0203,\n\ti40e_aqc_opc_get_switch_resource_alloc\t= 0x0204,\n\n\ti40e_aqc_opc_add_vsi\t\t\t= 0x0210,\n\ti40e_aqc_opc_update_vsi_parameters\t= 0x0211,\n\ti40e_aqc_opc_get_vsi_parameters\t\t= 0x0212,\n\n\ti40e_aqc_opc_add_pv\t\t\t= 0x0220,\n\ti40e_aqc_opc_update_pv_parameters\t= 0x0221,\n\ti40e_aqc_opc_get_pv_parameters\t\t= 0x0222,\n\n\ti40e_aqc_opc_add_veb\t\t\t= 0x0230,\n\ti40e_aqc_opc_update_veb_parameters\t= 0x0231,\n\ti40e_aqc_opc_get_veb_parameters\t\t= 0x0232,\n\n\ti40e_aqc_opc_delete_element\t\t= 0x0243,\n\n\ti40e_aqc_opc_add_macvlan\t\t= 0x0250,\n\ti40e_aqc_opc_remove_macvlan\t\t= 0x0251,\n\ti40e_aqc_opc_add_vlan\t\t\t= 0x0252,\n\ti40e_aqc_opc_remove_vlan\t\t= 0x0253,\n\ti40e_aqc_opc_set_vsi_promiscuous_modes\t= 0x0254,\n\ti40e_aqc_opc_add_tag\t\t\t= 0x0255,\n\ti40e_aqc_opc_remove_tag\t\t\t= 0x0256,\n\ti40e_aqc_opc_add_multicast_etag\t\t= 0x0257,\n\ti40e_aqc_opc_remove_multicast_etag\t= 0x0258,\n\ti40e_aqc_opc_update_tag\t\t\t= 0x0259,\n\ti40e_aqc_opc_add_control_packet_filter\t= 0x025A,\n\ti40e_aqc_opc_remove_control_packet_filter\t= 0x025B,\n\ti40e_aqc_opc_add_cloud_filters\t\t= 0x025C,\n\ti40e_aqc_opc_remove_cloud_filters\t= 0x025D,\n\n\ti40e_aqc_opc_add_mirror_rule\t= 0x0260,\n\ti40e_aqc_opc_delete_mirror_rule\t= 0x0261,\n\n\t/* DCB commands */\n\ti40e_aqc_opc_dcb_ignore_pfc\t= 0x0301,\n\ti40e_aqc_opc_dcb_updated\t= 0x0302,\n\n\t/* TX scheduler */\n\ti40e_aqc_opc_configure_vsi_bw_limit\t\t= 0x0400,\n\ti40e_aqc_opc_configure_vsi_ets_sla_bw_limit\t= 0x0406,\n\ti40e_aqc_opc_configure_vsi_tc_bw\t\t= 0x0407,\n\ti40e_aqc_opc_query_vsi_bw_config\t\t= 0x0408,\n\ti40e_aqc_opc_query_vsi_ets_sla_config\t\t= 0x040A,\n\ti40e_aqc_opc_configure_switching_comp_bw_limit\t= 0x0410,\n\n\ti40e_aqc_opc_enable_switching_comp_ets\t\t\t= 0x0413,\n\ti40e_aqc_opc_modify_switching_comp_ets\t\t\t= 0x0414,\n\ti40e_aqc_opc_disable_switching_comp_ets\t\t\t= 0x0415,\n\ti40e_aqc_opc_configure_switching_comp_ets_bw_limit\t= 0x0416,\n\ti40e_aqc_opc_configure_switching_comp_bw_config\t\t= 0x0417,\n\ti40e_aqc_opc_query_switching_comp_ets_config\t\t= 0x0418,\n\ti40e_aqc_opc_query_port_ets_config\t\t\t= 0x0419,\n\ti40e_aqc_opc_query_switching_comp_bw_config\t\t= 0x041A,\n\ti40e_aqc_opc_suspend_port_tx\t\t\t\t= 0x041B,\n\ti40e_aqc_opc_resume_port_tx\t\t\t\t= 0x041C,\n\ti40e_aqc_opc_configure_partition_bw\t\t\t= 0x041D,\n\n\t/* hmc */\n\ti40e_aqc_opc_query_hmc_resource_profile\t= 0x0500,\n\ti40e_aqc_opc_set_hmc_resource_profile\t= 0x0501,\n\n\t/* phy commands*/\n\ti40e_aqc_opc_get_phy_abilities\t\t= 0x0600,\n\ti40e_aqc_opc_set_phy_config\t\t= 0x0601,\n\ti40e_aqc_opc_set_mac_config\t\t= 0x0603,\n\ti40e_aqc_opc_set_link_restart_an\t= 0x0605,\n\ti40e_aqc_opc_get_link_status\t\t= 0x0607,\n\ti40e_aqc_opc_set_phy_int_mask\t\t= 0x0613,\n\ti40e_aqc_opc_get_local_advt_reg\t\t= 0x0614,\n\ti40e_aqc_opc_set_local_advt_reg\t\t= 0x0615,\n\ti40e_aqc_opc_get_partner_advt\t\t= 0x0616,\n\ti40e_aqc_opc_set_lb_modes\t\t= 0x0618,\n\ti40e_aqc_opc_get_phy_wol_caps\t\t= 0x0621,\n\ti40e_aqc_opc_set_phy_debug\t\t= 0x0622,\n\ti40e_aqc_opc_upload_ext_phy_fm\t\t= 0x0625,\n\n\t/* NVM commands */\n\ti40e_aqc_opc_nvm_read\t\t\t= 0x0701,\n\ti40e_aqc_opc_nvm_erase\t\t\t= 0x0702,\n\ti40e_aqc_opc_nvm_update\t\t\t= 0x0703,\n\ti40e_aqc_opc_nvm_config_read\t\t= 0x0704,\n\ti40e_aqc_opc_nvm_config_write\t\t= 0x0705,\n\n\t/* virtualization commands */\n\ti40e_aqc_opc_send_msg_to_pf\t\t= 0x0801,\n\ti40e_aqc_opc_send_msg_to_vf\t\t= 0x0802,\n\ti40e_aqc_opc_send_msg_to_peer\t\t= 0x0803,\n\n\t/* alternate structure */\n\ti40e_aqc_opc_alternate_write\t\t= 0x0900,\n\ti40e_aqc_opc_alternate_write_indirect\t= 0x0901,\n\ti40e_aqc_opc_alternate_read\t\t= 0x0902,\n\ti40e_aqc_opc_alternate_read_indirect\t= 0x0903,\n\ti40e_aqc_opc_alternate_write_done\t= 0x0904,\n\ti40e_aqc_opc_alternate_set_mode\t\t= 0x0905,\n\ti40e_aqc_opc_alternate_clear_port\t= 0x0906,\n\n\t/* LLDP commands */\n\ti40e_aqc_opc_lldp_get_mib\t= 0x0A00,\n\ti40e_aqc_opc_lldp_update_mib\t= 0x0A01,\n\ti40e_aqc_opc_lldp_add_tlv\t= 0x0A02,\n\ti40e_aqc_opc_lldp_update_tlv\t= 0x0A03,\n\ti40e_aqc_opc_lldp_delete_tlv\t= 0x0A04,\n\ti40e_aqc_opc_lldp_stop\t\t= 0x0A05,\n\ti40e_aqc_opc_lldp_start\t\t= 0x0A06,\n\ti40e_aqc_opc_get_cee_dcb_cfg\t= 0x0A07,\n\ti40e_aqc_opc_lldp_set_local_mib\t= 0x0A08,\n\ti40e_aqc_opc_lldp_stop_start_spec_agent\t= 0x0A09,\n\n\t/* Tunnel commands */\n\ti40e_aqc_opc_add_udp_tunnel\t= 0x0B00,\n\ti40e_aqc_opc_del_udp_tunnel\t= 0x0B01,\n\ti40e_aqc_opc_tunnel_key_structure\t= 0x0B10,\n\n\t/* Async Events */\n\ti40e_aqc_opc_event_lan_overflow\t\t= 0x1001,\n\n\t/* OEM commands */\n\ti40e_aqc_opc_oem_parameter_change\t= 0xFE00,\n\ti40e_aqc_opc_oem_device_status_change\t= 0xFE01,\n\ti40e_aqc_opc_oem_ocsd_initialize\t= 0xFE02,\n\ti40e_aqc_opc_oem_ocbb_initialize\t= 0xFE03,\n\n\t/* debug commands */\n\ti40e_aqc_opc_debug_get_deviceid\t\t= 0xFF00,\n\ti40e_aqc_opc_debug_set_mode\t\t= 0xFF01,\n\ti40e_aqc_opc_debug_read_reg\t\t= 0xFF03,\n\ti40e_aqc_opc_debug_write_reg\t\t= 0xFF04,\n\ti40e_aqc_opc_debug_modify_reg\t\t= 0xFF07,\n\ti40e_aqc_opc_debug_dump_internals\t= 0xFF08,\n};\n\n/* command structures and indirect data structures */\n\n/* Structure naming conventions:\n * - no suffix for direct command descriptor structures\n * - _data for indirect sent data\n * - _resp for indirect return data (data which is both will use _data)\n * - _completion for direct return data\n * - _element_ for repeated elements (may also be _data or _resp)\n *\n * Command structures are expected to overlay the params.raw member of the basic\n * descriptor, and as such cannot exceed 16 bytes in length.\n */\n\n/* This macro is used to generate a compilation error if a structure\n * is not exactly the correct length. It gives a divide by zero error if the\n * structure is not of the correct size, otherwise it creates an enum that is\n * never used.\n */\n#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \\\n\t{ i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }\n\n/* This macro is used extensively to ensure that command structures are 16\n * bytes in length as they have to map to the raw array of that size.\n */\n#define I40E_CHECK_CMD_LENGTH(X)\tI40E_CHECK_STRUCT_LEN(16, X)\n\n/* internal (0x00XX) commands */\n\n/* Get version (direct 0x0001) */\nstruct i40e_aqc_get_version {\n\t__le32 rom_ver;\n\t__le32 fw_build;\n\t__le16 fw_major;\n\t__le16 fw_minor;\n\t__le16 api_major;\n\t__le16 api_minor;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);\n\n/* Send driver version (indirect 0x0002) */\nstruct i40e_aqc_driver_version {\n\tu8\tdriver_major_ver;\n\tu8\tdriver_minor_ver;\n\tu8\tdriver_build_ver;\n\tu8\tdriver_subbuild_ver;\n\tu8\treserved[4];\n\t__le32\taddress_high;\n\t__le32\taddress_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);\n\n/* Queue Shutdown (direct 0x0003) */\nstruct i40e_aqc_queue_shutdown {\n\t__le32\tdriver_unloading;\n#define I40E_AQ_DRIVER_UNLOADING\t0x1\n\tu8\treserved[12];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);\n\n/* Set PF context (0x0004, direct) */\nstruct i40e_aqc_set_pf_context {\n\tu8\tpf_id;\n\tu8\treserved[15];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);\n\n/* Request resource ownership (direct 0x0008)\n * Release resource ownership (direct 0x0009)\n */\n#define I40E_AQ_RESOURCE_NVM\t\t\t1\n#define I40E_AQ_RESOURCE_SDP\t\t\t2\n#define I40E_AQ_RESOURCE_ACCESS_READ\t\t1\n#define I40E_AQ_RESOURCE_ACCESS_WRITE\t\t2\n#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT\t3000\n#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT\t180000\n\nstruct i40e_aqc_request_resource {\n\t__le16\tresource_id;\n\t__le16\taccess_type;\n\t__le32\ttimeout;\n\t__le32\tresource_number;\n\tu8\treserved[4];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);\n\n/* Get function capabilities (indirect 0x000A)\n * Get device capabilities (indirect 0x000B)\n */\nstruct i40e_aqc_list_capabilites {\n\tu8 command_flags;\n#define I40E_AQ_LIST_CAP_PF_INDEX_EN\t1\n\tu8 pf_index;\n\tu8 reserved[2];\n\t__le32 count;\n\t__le32 addr_high;\n\t__le32 addr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);\n\nstruct i40e_aqc_list_capabilities_element_resp {\n\t__le16\tid;\n\tu8\tmajor_rev;\n\tu8\tminor_rev;\n\t__le32\tnumber;\n\t__le32\tlogical_id;\n\t__le32\tphys_id;\n\tu8\treserved[16];\n};\n\n/* list of caps */\n\n#define I40E_AQ_CAP_ID_SWITCH_MODE\t0x0001\n#define I40E_AQ_CAP_ID_MNG_MODE\t\t0x0002\n#define I40E_AQ_CAP_ID_NPAR_ACTIVE\t0x0003\n#define I40E_AQ_CAP_ID_OS2BMC_CAP\t0x0004\n#define I40E_AQ_CAP_ID_FUNCTIONS_VALID\t0x0005\n#define I40E_AQ_CAP_ID_ALTERNATE_RAM\t0x0006\n#define I40E_AQ_CAP_ID_SRIOV\t\t0x0012\n#define I40E_AQ_CAP_ID_VF\t\t0x0013\n#define I40E_AQ_CAP_ID_VMDQ\t\t0x0014\n#define I40E_AQ_CAP_ID_8021QBG\t\t0x0015\n#define I40E_AQ_CAP_ID_8021QBR\t\t0x0016\n#define I40E_AQ_CAP_ID_VSI\t\t0x0017\n#define I40E_AQ_CAP_ID_DCB\t\t0x0018\n#define I40E_AQ_CAP_ID_FCOE\t\t0x0021\n#define I40E_AQ_CAP_ID_ISCSI\t\t0x0022\n#define I40E_AQ_CAP_ID_RSS\t\t0x0040\n#define I40E_AQ_CAP_ID_RXQ\t\t0x0041\n#define I40E_AQ_CAP_ID_TXQ\t\t0x0042\n#define I40E_AQ_CAP_ID_MSIX\t\t0x0043\n#define I40E_AQ_CAP_ID_VF_MSIX\t\t0x0044\n#define I40E_AQ_CAP_ID_FLOW_DIRECTOR\t0x0045\n#define I40E_AQ_CAP_ID_1588\t\t0x0046\n#define I40E_AQ_CAP_ID_IWARP\t\t0x0051\n#define I40E_AQ_CAP_ID_LED\t\t0x0061\n#define I40E_AQ_CAP_ID_SDP\t\t0x0062\n#define I40E_AQ_CAP_ID_MDIO\t\t0x0063\n#define I40E_AQ_CAP_ID_FLEX10\t\t0x00F1\n#define I40E_AQ_CAP_ID_CEM\t\t0x00F2\n\n/* Set CPPM Configuration (direct 0x0103) */\nstruct i40e_aqc_cppm_configuration {\n\t__le16\tcommand_flags;\n#define I40E_AQ_CPPM_EN_LTRC\t0x0800\n#define I40E_AQ_CPPM_EN_DMCTH\t0x1000\n#define I40E_AQ_CPPM_EN_DMCTLX\t0x2000\n#define I40E_AQ_CPPM_EN_HPTC\t0x4000\n#define I40E_AQ_CPPM_EN_DMARC\t0x8000\n\t__le16\tttlx;\n\t__le32\tdmacr;\n\t__le16\tdmcth;\n\tu8\thptc;\n\tu8\treserved;\n\t__le32\tpfltrc;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);\n\n/* Set ARP Proxy command / response (indirect 0x0104) */\nstruct i40e_aqc_arp_proxy_data {\n\t__le16\tcommand_flags;\n#define I40E_AQ_ARP_INIT_IPV4\t0x0008\n#define I40E_AQ_ARP_UNSUP_CTL\t0x0010\n#define I40E_AQ_ARP_ENA\t\t0x0020\n#define I40E_AQ_ARP_ADD_IPV4\t0x0040\n#define I40E_AQ_ARP_DEL_IPV4\t0x0080\n\t__le16\ttable_id;\n\t__le32\tpfpm_proxyfc;\n\t__le32\tip_addr;\n\tu8\tmac_addr[6];\n\tu8\treserved[2];\n};\n\nI40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);\n\n/* Set NS Proxy Table Entry Command (indirect 0x0105) */\nstruct i40e_aqc_ns_proxy_data {\n\t__le16\ttable_idx_mac_addr_0;\n\t__le16\ttable_idx_mac_addr_1;\n\t__le16\ttable_idx_ipv6_0;\n\t__le16\ttable_idx_ipv6_1;\n\t__le16\tcontrol;\n#define I40E_AQ_NS_PROXY_ADD_0\t\t0x0100\n#define I40E_AQ_NS_PROXY_DEL_0\t\t0x0200\n#define I40E_AQ_NS_PROXY_ADD_1\t\t0x0400\n#define I40E_AQ_NS_PROXY_DEL_1\t\t0x0800\n#define I40E_AQ_NS_PROXY_ADD_IPV6_0\t0x1000\n#define I40E_AQ_NS_PROXY_DEL_IPV6_0\t0x2000\n#define I40E_AQ_NS_PROXY_ADD_IPV6_1\t0x4000\n#define I40E_AQ_NS_PROXY_DEL_IPV6_1\t0x8000\n#define I40E_AQ_NS_PROXY_COMMAND_SEQ\t0x0001\n#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL\t0x0002\n#define I40E_AQ_NS_PROXY_INIT_MAC_TBL\t0x0004\n\tu8\tmac_addr_0[6];\n\tu8\tmac_addr_1[6];\n\tu8\tlocal_mac_addr[6];\n\tu8\tipv6_addr_0[16]; /* Warning! spec specifies BE byte order */\n\tu8\tipv6_addr_1[16];\n};\n\nI40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);\n\n/* Manage LAA Command (0x0106) - obsolete */\nstruct i40e_aqc_mng_laa {\n\t__le16\tcommand_flags;\n#define I40E_AQ_LAA_FLAG_WR\t0x8000\n\tu8\treserved[2];\n\t__le32\tsal;\n\t__le16\tsah;\n\tu8\treserved2[6];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);\n\n/* Manage MAC Address Read Command (indirect 0x0107) */\nstruct i40e_aqc_mac_address_read {\n\t__le16\tcommand_flags;\n#define I40E_AQC_LAN_ADDR_VALID\t\t0x10\n#define I40E_AQC_SAN_ADDR_VALID\t\t0x20\n#define I40E_AQC_PORT_ADDR_VALID\t0x40\n#define I40E_AQC_WOL_ADDR_VALID\t\t0x80\n#define I40E_AQC_ADDR_VALID_MASK\t0xf0\n\tu8\treserved[6];\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);\n\nstruct i40e_aqc_mac_address_read_data {\n\tu8 pf_lan_mac[6];\n\tu8 pf_san_mac[6];\n\tu8 port_mac[6];\n\tu8 pf_wol_mac[6];\n};\n\nI40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);\n\n/* Manage MAC Address Write Command (0x0108) */\nstruct i40e_aqc_mac_address_write {\n\t__le16\tcommand_flags;\n#define I40E_AQC_WRITE_TYPE_LAA_ONLY\t0x0000\n#define I40E_AQC_WRITE_TYPE_LAA_WOL\t0x4000\n#define I40E_AQC_WRITE_TYPE_PORT\t0x8000\n#define I40E_AQC_WRITE_TYPE_MASK\t0xc000\n\t__le16\tmac_sah;\n\t__le32\tmac_sal;\n\tu8\treserved[8];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);\n\n/* PXE commands (0x011x) */\n\n/* Clear PXE Command and response (direct 0x0110) */\nstruct i40e_aqc_clear_pxe {\n\tu8\trx_cnt;\n\tu8\treserved[15];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);\n\n/* Switch configuration commands (0x02xx) */\n\n/* Used by many indirect commands that only pass an seid and a buffer in the\n * command\n */\nstruct i40e_aqc_switch_seid {\n\t__le16\tseid;\n\tu8\treserved[6];\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);\n\n/* Get Switch Configuration command (indirect 0x0200)\n * uses i40e_aqc_switch_seid for the descriptor\n */\nstruct i40e_aqc_get_switch_config_header_resp {\n\t__le16\tnum_reported;\n\t__le16\tnum_total;\n\tu8\treserved[12];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);\n\nstruct i40e_aqc_switch_config_element_resp {\n\tu8\telement_type;\n#define I40E_AQ_SW_ELEM_TYPE_MAC\t1\n#define I40E_AQ_SW_ELEM_TYPE_PF\t\t2\n#define I40E_AQ_SW_ELEM_TYPE_VF\t\t3\n#define I40E_AQ_SW_ELEM_TYPE_EMP\t4\n#define I40E_AQ_SW_ELEM_TYPE_BMC\t5\n#define I40E_AQ_SW_ELEM_TYPE_PV\t\t16\n#define I40E_AQ_SW_ELEM_TYPE_VEB\t17\n#define I40E_AQ_SW_ELEM_TYPE_PA\t\t18\n#define I40E_AQ_SW_ELEM_TYPE_VSI\t19\n\tu8\trevision;\n#define I40E_AQ_SW_ELEM_REV_1\t\t1\n\t__le16\tseid;\n\t__le16\tuplink_seid;\n\t__le16\tdownlink_seid;\n\tu8\treserved[3];\n\tu8\tconnection_type;\n#define I40E_AQ_CONN_TYPE_REGULAR\t0x1\n#define I40E_AQ_CONN_TYPE_DEFAULT\t0x2\n#define I40E_AQ_CONN_TYPE_CASCADED\t0x3\n\t__le16\tscheduler_id;\n\t__le16\telement_info;\n};\n\nI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);\n\n/* Get Switch Configuration (indirect 0x0200)\n * an array of elements are returned in the response buffer\n * the first in the array is the header, remainder are elements\n */\nstruct i40e_aqc_get_switch_config_resp {\n\tstruct i40e_aqc_get_switch_config_header_resp\theader;\n\tstruct i40e_aqc_switch_config_element_resp\telement[1];\n};\n\nI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);\n\n/* Add Statistics (direct 0x0201)\n * Remove Statistics (direct 0x0202)\n */\nstruct i40e_aqc_add_remove_statistics {\n\t__le16\tseid;\n\t__le16\tvlan;\n\t__le16\tstat_index;\n\tu8\treserved[10];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);\n\n/* Set Port Parameters command (direct 0x0203) */\nstruct i40e_aqc_set_port_parameters {\n\t__le16\tcommand_flags;\n#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS\t1\n#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS\t2 /* must set! */\n#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA\t4\n\t__le16\tbad_frame_vsi;\n\t__le16\tdefault_seid; /* reserved for command */\n\tu8\treserved[10];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);\n\n/* Get Switch Resource Allocation (indirect 0x0204) */\nstruct i40e_aqc_get_switch_resource_alloc {\n\tu8\tnum_entries; /* reserved for command */\n\tu8\treserved[7];\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);\n\n/* expect an array of these structs in the response buffer */\nstruct i40e_aqc_switch_resource_alloc_element_resp {\n\tu8\tresource_type;\n#define I40E_AQ_RESOURCE_TYPE_VEB\t\t0x0\n#define I40E_AQ_RESOURCE_TYPE_VSI\t\t0x1\n#define I40E_AQ_RESOURCE_TYPE_MACADDR\t\t0x2\n#define I40E_AQ_RESOURCE_TYPE_STAG\t\t0x3\n#define I40E_AQ_RESOURCE_TYPE_ETAG\t\t0x4\n#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH\t0x5\n#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH\t0x6\n#define I40E_AQ_RESOURCE_TYPE_VLAN\t\t0x7\n#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY\t0x8\n#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY\t0x9\n#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL\t0xA\n#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE\t0xB\n#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS\t0xC\n#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS\t0xD\n#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS\t0xF\n#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS\t0x10\n#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS\t0x11\n#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS\t\t0x12\n#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS\t0x13\n\tu8\treserved1;\n\t__le16\tguaranteed;\n\t__le16\ttotal;\n\t__le16\tused;\n\t__le16\ttotal_unalloced;\n\tu8\treserved2[6];\n};\n\nI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);\n\n/* Add VSI (indirect 0x0210)\n * this indirect command uses struct i40e_aqc_vsi_properties_data\n * as the indirect buffer (128 bytes)\n *\n * Update VSI (indirect 0x211)\n * uses the same data structure as Add VSI\n *\n * Get VSI (indirect 0x0212)\n * uses the same completion and data structure as Add VSI\n */\nstruct i40e_aqc_add_get_update_vsi {\n\t__le16\tuplink_seid;\n\tu8\tconnection_type;\n#define I40E_AQ_VSI_CONN_TYPE_NORMAL\t0x1\n#define I40E_AQ_VSI_CONN_TYPE_DEFAULT\t0x2\n#define I40E_AQ_VSI_CONN_TYPE_CASCADED\t0x3\n\tu8\treserved1;\n\tu8\tvf_id;\n\tu8\treserved2;\n\t__le16\tvsi_flags;\n#define I40E_AQ_VSI_TYPE_SHIFT\t\t0x0\n#define I40E_AQ_VSI_TYPE_MASK\t\t(0x3 << I40E_AQ_VSI_TYPE_SHIFT)\n#define I40E_AQ_VSI_TYPE_VF\t\t0x0\n#define I40E_AQ_VSI_TYPE_VMDQ2\t\t0x1\n#define I40E_AQ_VSI_TYPE_PF\t\t0x2\n#define I40E_AQ_VSI_TYPE_EMP_MNG\t0x3\n#define I40E_AQ_VSI_FLAG_CASCADED_PV\t0x4\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);\n\nstruct i40e_aqc_add_get_update_vsi_completion {\n\t__le16 seid;\n\t__le16 vsi_number;\n\t__le16 vsi_used;\n\t__le16 vsi_free;\n\t__le32 addr_high;\n\t__le32 addr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);\n\nstruct i40e_aqc_vsi_properties_data {\n\t/* first 96 byte are written by SW */\n\t__le16\tvalid_sections;\n#define I40E_AQ_VSI_PROP_SWITCH_VALID\t\t0x0001\n#define I40E_AQ_VSI_PROP_SECURITY_VALID\t\t0x0002\n#define I40E_AQ_VSI_PROP_VLAN_VALID\t\t0x0004\n#define I40E_AQ_VSI_PROP_CAS_PV_VALID\t\t0x0008\n#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID\t0x0010\n#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID\t0x0020\n#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID\t0x0040\n#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID\t0x0080\n#define I40E_AQ_VSI_PROP_OUTER_UP_VALID\t\t0x0100\n#define I40E_AQ_VSI_PROP_SCHED_VALID\t\t0x0200\n\t/* switch section */\n\t__le16\tswitch_id; /* 12bit id combined with flags below */\n#define I40E_AQ_VSI_SW_ID_SHIFT\t\t0x0000\n#define I40E_AQ_VSI_SW_ID_MASK\t\t(0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)\n#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG\t0x1000\n#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB\t0x2000\n#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB\t0x4000\n\tu8\tsw_reserved[2];\n\t/* security section */\n\tu8\tsec_flags;\n#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD\t0x01\n#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK\t0x02\n#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK\t0x04\n\tu8\tsec_reserved;\n\t/* VLAN section */\n\t__le16\tpvid; /* VLANS include priority bits */\n\t__le16\tfcoe_pvid;\n\tu8\tport_vlan_flags;\n#define I40E_AQ_VSI_PVLAN_MODE_SHIFT\t0x00\n#define I40E_AQ_VSI_PVLAN_MODE_MASK\t(0x03 << \\\n\t\t\t\t\t I40E_AQ_VSI_PVLAN_MODE_SHIFT)\n#define I40E_AQ_VSI_PVLAN_MODE_TAGGED\t0x01\n#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED\t0x02\n#define I40E_AQ_VSI_PVLAN_MODE_ALL\t0x03\n#define I40E_AQ_VSI_PVLAN_INSERT_PVID\t0x04\n#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT\t0x03\n#define I40E_AQ_VSI_PVLAN_EMOD_MASK\t(0x3 << \\\n\t\t\t\t\t I40E_AQ_VSI_PVLAN_EMOD_SHIFT)\n#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH\t0x0\n#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP\t0x08\n#define I40E_AQ_VSI_PVLAN_EMOD_STR\t0x10\n#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING\t0x18\n\tu8\tpvlan_reserved[3];\n\t/* ingress egress up sections */\n\t__le32\tingress_table; /* bitmap, 3 bits per up */\n#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT\t0\n#define I40E_AQ_VSI_UP_TABLE_UP0_MASK\t(0x7 << \\\n\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)\n#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT\t3\n#define I40E_AQ_VSI_UP_TABLE_UP1_MASK\t(0x7 << \\\n\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)\n#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT\t6\n#define I40E_AQ_VSI_UP_TABLE_UP2_MASK\t(0x7 << \\\n\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)\n#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT\t9\n#define I40E_AQ_VSI_UP_TABLE_UP3_MASK\t(0x7 << \\\n\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)\n#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT\t12\n#define I40E_AQ_VSI_UP_TABLE_UP4_MASK\t(0x7 << \\\n\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)\n#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT\t15\n#define I40E_AQ_VSI_UP_TABLE_UP5_MASK\t(0x7 << \\\n\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)\n#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT\t18\n#define I40E_AQ_VSI_UP_TABLE_UP6_MASK\t(0x7 << \\\n\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)\n#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT\t21\n#define I40E_AQ_VSI_UP_TABLE_UP7_MASK\t(0x7 << \\\n\t\t\t\t\t I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)\n\t__le32\tegress_table; /* same defines as for ingress table */\n\t/* cascaded PV section */\n\t__le16\tcas_pv_tag;\n\tu8\tcas_pv_flags;\n#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT\t\t0x00\n#define I40E_AQ_VSI_CAS_PV_TAGX_MASK\t\t(0x03 << \\\n\t\t\t\t\t\t I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)\n#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE\t\t0x00\n#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE\t\t0x01\n#define I40E_AQ_VSI_CAS_PV_TAGX_COPY\t\t0x02\n#define I40E_AQ_VSI_CAS_PV_INSERT_TAG\t\t0x10\n#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE\t\t0x20\n#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG\t0x40\n\tu8\tcas_pv_reserved;\n\t/* queue mapping section */\n\t__le16\tmapping_flags;\n#define I40E_AQ_VSI_QUE_MAP_CONTIG\t0x0\n#define I40E_AQ_VSI_QUE_MAP_NONCONTIG\t0x1\n\t__le16\tqueue_mapping[16];\n#define I40E_AQ_VSI_QUEUE_SHIFT\t\t0x0\n#define I40E_AQ_VSI_QUEUE_MASK\t\t(0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)\n\t__le16\ttc_mapping[8];\n#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT\t0\n#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK\t(0x1FF << \\\n\t\t\t\t\t I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)\n#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT\t9\n#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK\t(0x7 << \\\n\t\t\t\t\t I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)\n\t/* queueing option section */\n\tu8\tqueueing_opt_flags;\n#define I40E_AQ_VSI_QUE_OPT_TCP_ENA\t0x10\n#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA\t0x20\n\tu8\tqueueing_opt_reserved[3];\n\t/* scheduler section */\n\tu8\tup_enable_bits;\n\tu8\tsched_reserved;\n\t/* outer up section */\n\t__le32\touter_up_table; /* same structure and defines as ingress table */\n\tu8\tcmd_reserved[8];\n\t/* last 32 bytes are written by FW */\n\t__le16\tqs_handle[8];\n#define I40E_AQ_VSI_QS_HANDLE_INVALID\t0xFFFF\n\t__le16\tstat_counter_idx;\n\t__le16\tsched_id;\n\tu8\tresp_reserved[12];\n};\n\nI40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);\n\n/* Add Port Virtualizer (direct 0x0220)\n * also used for update PV (direct 0x0221) but only flags are used\n * (IS_CTRL_PORT only works on add PV)\n */\nstruct i40e_aqc_add_update_pv {\n\t__le16\tcommand_flags;\n#define I40E_AQC_PV_FLAG_PV_TYPE\t\t0x1\n#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN\t0x2\n#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN\t0x4\n#define I40E_AQC_PV_FLAG_IS_CTRL_PORT\t\t0x8\n\t__le16\tuplink_seid;\n\t__le16\tconnected_seid;\n\tu8\treserved[10];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);\n\nstruct i40e_aqc_add_update_pv_completion {\n\t/* reserved for update; for add also encodes error if rc == ENOSPC */\n\t__le16\tpv_seid;\n#define I40E_AQC_PV_ERR_FLAG_NO_PV\t0x1\n#define I40E_AQC_PV_ERR_FLAG_NO_SCHED\t0x2\n#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER\t0x4\n#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY\t0x8\n\tu8\treserved[14];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);\n\n/* Get PV Params (direct 0x0222)\n * uses i40e_aqc_switch_seid for the descriptor\n */\n\nstruct i40e_aqc_get_pv_params_completion {\n\t__le16\tseid;\n\t__le16\tdefault_stag;\n\t__le16\tpv_flags; /* same flags as add_pv */\n#define I40E_AQC_GET_PV_PV_TYPE\t\t\t0x1\n#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG\t0x2\n#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG\t0x4\n\tu8\treserved[8];\n\t__le16\tdefault_port_seid;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);\n\n/* Add VEB (direct 0x0230) */\nstruct i40e_aqc_add_veb {\n\t__le16\tuplink_seid;\n\t__le16\tdownlink_seid;\n\t__le16\tveb_flags;\n#define I40E_AQC_ADD_VEB_FLOATING\t\t0x1\n#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT\t1\n#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK\t\t(0x3 << \\\n\t\t\t\t\tI40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)\n#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT\t0x2\n#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA\t\t0x4\n#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER\t0x8\n\tu8\tenable_tcs;\n\tu8\treserved[9];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);\n\nstruct i40e_aqc_add_veb_completion {\n\tu8\treserved[6];\n\t__le16\tswitch_seid;\n\t/* also encodes error if rc == ENOSPC; codes are the same as add_pv */\n\t__le16\tveb_seid;\n#define I40E_AQC_VEB_ERR_FLAG_NO_VEB\t\t0x1\n#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED\t\t0x2\n#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER\t0x4\n#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY\t\t0x8\n\t__le16\tstatistic_index;\n\t__le16\tvebs_used;\n\t__le16\tvebs_free;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);\n\n/* Get VEB Parameters (direct 0x0232)\n * uses i40e_aqc_switch_seid for the descriptor\n */\nstruct i40e_aqc_get_veb_parameters_completion {\n\t__le16\tseid;\n\t__le16\tswitch_id;\n\t__le16\tveb_flags; /* only the first/last flags from 0x0230 is valid */\n\t__le16\tstatistic_index;\n\t__le16\tvebs_used;\n\t__le16\tvebs_free;\n\tu8\treserved[4];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);\n\n/* Delete Element (direct 0x0243)\n * uses the generic i40e_aqc_switch_seid\n */\n\n/* Add MAC-VLAN (indirect 0x0250) */\n\n/* used for the command for most vlan commands */\nstruct i40e_aqc_macvlan {\n\t__le16\tnum_addresses;\n\t__le16\tseid[3];\n#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT\t0\n#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK\t(0x3FF << \\\n\t\t\t\t\tI40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)\n#define I40E_AQC_MACVLAN_CMD_SEID_VALID\t\t0x8000\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);\n\n/* indirect data for command and response */\nstruct i40e_aqc_add_macvlan_element_data {\n\tu8\tmac_addr[6];\n\t__le16\tvlan_tag;\n\t__le16\tflags;\n#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH\t0x0001\n#define I40E_AQC_MACVLAN_ADD_HASH_MATCH\t\t0x0002\n#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN\t0x0004\n#define I40E_AQC_MACVLAN_ADD_TO_QUEUE\t\t0x0008\n\t__le16\tqueue_number;\n#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT\t0\n#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK\t\t(0x7FF << \\\n\t\t\t\t\tI40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)\n\t/* response section */\n\tu8\tmatch_method;\n#define I40E_AQC_MM_PERFECT_MATCH\t0x01\n#define I40E_AQC_MM_HASH_MATCH\t\t0x02\n#define I40E_AQC_MM_ERR_NO_RES\t\t0xFF\n\tu8\treserved1[3];\n};\n\nstruct i40e_aqc_add_remove_macvlan_completion {\n\t__le16 perfect_mac_used;\n\t__le16 perfect_mac_free;\n\t__le16 unicast_hash_free;\n\t__le16 multicast_hash_free;\n\t__le32 addr_high;\n\t__le32 addr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);\n\n/* Remove MAC-VLAN (indirect 0x0251)\n * uses i40e_aqc_macvlan for the descriptor\n * data points to an array of num_addresses of elements\n */\n\nstruct i40e_aqc_remove_macvlan_element_data {\n\tu8\tmac_addr[6];\n\t__le16\tvlan_tag;\n\tu8\tflags;\n#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH\t0x01\n#define I40E_AQC_MACVLAN_DEL_HASH_MATCH\t\t0x02\n#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN\t0x08\n#define I40E_AQC_MACVLAN_DEL_ALL_VSIS\t\t0x10\n\tu8\treserved[3];\n\t/* reply section */\n\tu8\terror_code;\n#define I40E_AQC_REMOVE_MACVLAN_SUCCESS\t\t0x0\n#define I40E_AQC_REMOVE_MACVLAN_FAIL\t\t0xFF\n\tu8\treply_reserved[3];\n};\n\n/* Add VLAN (indirect 0x0252)\n * Remove VLAN (indirect 0x0253)\n * use the generic i40e_aqc_macvlan for the command\n */\nstruct i40e_aqc_add_remove_vlan_element_data {\n\t__le16\tvlan_tag;\n\tu8\tvlan_flags;\n/* flags for add VLAN */\n#define I40E_AQC_ADD_VLAN_LOCAL\t\t\t0x1\n#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT\t\t1\n#define I40E_AQC_ADD_PVLAN_TYPE_MASK\t(0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)\n#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR\t\t0x0\n#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY\t\t0x2\n#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY\t0x4\n#define I40E_AQC_VLAN_PTYPE_SHIFT\t\t3\n#define I40E_AQC_VLAN_PTYPE_MASK\t(0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)\n#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI\t\t0x0\n#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI\t\t0x8\n#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI\t0x10\n#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI\t0x18\n/* flags for remove VLAN */\n#define I40E_AQC_REMOVE_VLAN_ALL\t0x1\n\tu8\treserved;\n\tu8\tresult;\n/* flags for add VLAN */\n#define I40E_AQC_ADD_VLAN_SUCCESS\t0x0\n#define I40E_AQC_ADD_VLAN_FAIL_REQUEST\t0xFE\n#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE\t0xFF\n/* flags for remove VLAN */\n#define I40E_AQC_REMOVE_VLAN_SUCCESS\t0x0\n#define I40E_AQC_REMOVE_VLAN_FAIL\t0xFF\n\tu8\treserved1[3];\n};\n\nstruct i40e_aqc_add_remove_vlan_completion {\n\tu8\treserved[4];\n\t__le16\tvlans_used;\n\t__le16\tvlans_free;\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\n/* Set VSI Promiscuous Modes (direct 0x0254) */\nstruct i40e_aqc_set_vsi_promiscuous_modes {\n\t__le16\tpromiscuous_flags;\n\t__le16\tvalid_flags;\n/* flags used for both fields above */\n#define I40E_AQC_SET_VSI_PROMISC_UNICAST\t0x01\n#define I40E_AQC_SET_VSI_PROMISC_MULTICAST\t0x02\n#define I40E_AQC_SET_VSI_PROMISC_BROADCAST\t0x04\n#define I40E_AQC_SET_VSI_DEFAULT\t\t0x08\n#define I40E_AQC_SET_VSI_PROMISC_VLAN\t\t0x10\n\t__le16\tseid;\n#define I40E_AQC_VSI_PROM_CMD_SEID_MASK\t\t0x3FF\n\t__le16\tvlan_tag;\n#define I40E_AQC_SET_VSI_VLAN_VALID\t\t0x8000\n\tu8\treserved[8];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);\n\n/* Add S/E-tag command (direct 0x0255)\n * Uses generic i40e_aqc_add_remove_tag_completion for completion\n */\nstruct i40e_aqc_add_tag {\n\t__le16\tflags;\n#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE\t\t0x0001\n\t__le16\tseid;\n#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT\t0\n#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK\t(0x3FF << \\\n\t\t\t\t\tI40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)\n\t__le16\ttag;\n\t__le16\tqueue_number;\n\tu8\treserved[8];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);\n\nstruct i40e_aqc_add_remove_tag_completion {\n\tu8\treserved[12];\n\t__le16\ttags_used;\n\t__le16\ttags_free;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);\n\n/* Remove S/E-tag command (direct 0x0256)\n * Uses generic i40e_aqc_add_remove_tag_completion for completion\n */\nstruct i40e_aqc_remove_tag {\n\t__le16\tseid;\n#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT\t0\n#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK\t(0x3FF << \\\n\t\t\t\t\tI40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)\n\t__le16\ttag;\n\tu8\treserved[12];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);\n\n/* Add multicast E-Tag (direct 0x0257)\n * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields\n * and no external data\n */\nstruct i40e_aqc_add_remove_mcast_etag {\n\t__le16\tpv_seid;\n\t__le16\tetag;\n\tu8\tnum_unicast_etags;\n\tu8\treserved[3];\n\t__le32\taddr_high; /* address of array of 2-byte s-tags */\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);\n\nstruct i40e_aqc_add_remove_mcast_etag_completion {\n\tu8\treserved[4];\n\t__le16\tmcast_etags_used;\n\t__le16\tmcast_etags_free;\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);\n\n/* Update S/E-Tag (direct 0x0259) */\nstruct i40e_aqc_update_tag {\n\t__le16\tseid;\n#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT\t0\n#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK\t(0x3FF << \\\n\t\t\t\t\tI40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)\n\t__le16\told_tag;\n\t__le16\tnew_tag;\n\tu8\treserved[10];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);\n\nstruct i40e_aqc_update_tag_completion {\n\tu8\treserved[12];\n\t__le16\ttags_used;\n\t__le16\ttags_free;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);\n\n/* Add Control Packet filter (direct 0x025A)\n * Remove Control Packet filter (direct 0x025B)\n * uses the i40e_aqc_add_oveb_cloud,\n * and the generic direct completion structure\n */\nstruct i40e_aqc_add_remove_control_packet_filter {\n\tu8\tmac[6];\n\t__le16\tetype;\n\t__le16\tflags;\n#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC\t0x0001\n#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP\t\t0x0002\n#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE\t0x0004\n#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX\t\t0x0008\n#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX\t\t0x0000\n\t__le16\tseid;\n#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT\t0\n#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK\t(0x3FF << \\\n\t\t\t\tI40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)\n\t__le16\tqueue;\n\tu8\treserved[2];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);\n\nstruct i40e_aqc_add_remove_control_packet_filter_completion {\n\t__le16\tmac_etype_used;\n\t__le16\tetype_used;\n\t__le16\tmac_etype_free;\n\t__le16\tetype_free;\n\tu8\treserved[8];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);\n\n/* Add Cloud filters (indirect 0x025C)\n * Remove Cloud filters (indirect 0x025D)\n * uses the i40e_aqc_add_remove_cloud_filters,\n * and the generic indirect completion structure\n */\nstruct i40e_aqc_add_remove_cloud_filters {\n\tu8\tnum_filters;\n\tu8\treserved;\n\t__le16\tseid;\n#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT\t0\n#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK\t(0x3FF << \\\n\t\t\t\t\tI40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)\n\tu8\treserved2[4];\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);\n\nstruct i40e_aqc_add_remove_cloud_filters_element_data {\n\tu8\touter_mac[6];\n\tu8\tinner_mac[6];\n\t__le16\tinner_vlan;\n\tunion {\n\t\tstruct {\n\t\t\tu8 reserved[12];\n\t\t\tu8 data[4];\n\t\t} v4;\n\t\tstruct {\n\t\t\tu8 data[16];\n\t\t} v6;\n\t} ipaddr;\n\t__le16\tflags;\n#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT\t\t\t0\n#define I40E_AQC_ADD_CLOUD_FILTER_MASK\t(0x3F << \\\n\t\t\t\t\tI40E_AQC_ADD_CLOUD_FILTER_SHIFT)\n/* 0x0000 reserved */\n#define I40E_AQC_ADD_CLOUD_FILTER_OIP\t\t\t0x0001\n/* 0x0002 reserved */\n#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN\t\t0x0003\n#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID\t0x0004\n/* 0x0005 reserved */\n#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID\t\t0x0006\n/* 0x0007 reserved */\n/* 0x0008 reserved */\n#define I40E_AQC_ADD_CLOUD_FILTER_OMAC\t\t\t0x0009\n#define I40E_AQC_ADD_CLOUD_FILTER_IMAC\t\t\t0x000A\n#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC\t0x000B\n#define I40E_AQC_ADD_CLOUD_FILTER_IIP\t\t\t0x000C\n\n#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE\t\t0x0080\n#define I40E_AQC_ADD_CLOUD_VNK_SHIFT\t\t\t6\n#define I40E_AQC_ADD_CLOUD_VNK_MASK\t\t\t0x00C0\n#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4\t\t\t0\n#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6\t\t\t0x0100\n\n#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT\t\t9\n#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK\t\t0x1E00\n#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN\t\t0\n#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC\t\t1\n#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE\t\t\t2\n#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP\t\t\t3\n\n\t__le32\ttenant_id;\n\tu8\treserved[4];\n\t__le16\tqueue_number;\n#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT\t\t0\n#define I40E_AQC_ADD_CLOUD_QUEUE_MASK\t\t(0x7FF << \\\n\t\t\t\t\t\t I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)\n\tu8\treserved2[14];\n\t/* response section */\n\tu8\tallocation_result;\n#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS\t0x0\n#define I40E_AQC_ADD_CLOUD_FILTER_FAIL\t\t0xFF\n\tu8\tresponse_reserved[7];\n};\n\nstruct i40e_aqc_remove_cloud_filters_completion {\n\t__le16 perfect_ovlan_used;\n\t__le16 perfect_ovlan_free;\n\t__le16 vlan_used;\n\t__le16 vlan_free;\n\t__le32 addr_high;\n\t__le32 addr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);\n\n/* Add Mirror Rule (indirect or direct 0x0260)\n * Delete Mirror Rule (indirect or direct 0x0261)\n * note: some rule types (4,5) do not use an external buffer.\n * take care to set the flags correctly.\n */\nstruct i40e_aqc_add_delete_mirror_rule {\n\t__le16 seid;\n\t__le16 rule_type;\n#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT\t\t0\n#define I40E_AQC_MIRROR_RULE_TYPE_MASK\t\t(0x7 << \\\n\t\t\t\t\t\tI40E_AQC_MIRROR_RULE_TYPE_SHIFT)\n#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS\t1\n#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS\t2\n#define I40E_AQC_MIRROR_RULE_TYPE_VLAN\t\t3\n#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS\t4\n#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS\t5\n\t__le16 num_entries;\n\t__le16 destination; /* VSI for add, rule id for delete */\n\t__le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */\n\t__le32 addr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);\n\nstruct i40e_aqc_add_delete_mirror_rule_completion {\n\tu8\treserved[2];\n\t__le16\trule_id; /* only used on add */\n\t__le16\tmirror_rules_used;\n\t__le16\tmirror_rules_free;\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);\n\n/* DCB 0x03xx*/\n\n/* PFC Ignore (direct 0x0301)\n * the command and response use the same descriptor structure\n */\nstruct i40e_aqc_pfc_ignore {\n\tu8\ttc_bitmap;\n\tu8\tcommand_flags; /* unused on response */\n#define I40E_AQC_PFC_IGNORE_SET\t\t0x80\n#define I40E_AQC_PFC_IGNORE_CLEAR\t0x0\n\tu8\treserved[14];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);\n\n/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure\n * with no parameters\n */\n\n/* TX scheduler 0x04xx */\n\n/* Almost all the indirect commands use\n * this generic struct to pass the SEID in param0\n */\nstruct i40e_aqc_tx_sched_ind {\n\t__le16\tvsi_seid;\n\tu8\treserved[6];\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);\n\n/* Several commands respond with a set of queue set handles */\nstruct i40e_aqc_qs_handles_resp {\n\t__le16 qs_handles[8];\n};\n\n/* Configure VSI BW limits (direct 0x0400) */\nstruct i40e_aqc_configure_vsi_bw_limit {\n\t__le16\tvsi_seid;\n\tu8\treserved[2];\n\t__le16\tcredit;\n\tu8\treserved1[2];\n\tu8\tmax_credit; /* 0-3, limit = 2^max */\n\tu8\treserved2[7];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);\n\n/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)\n * responds with i40e_aqc_qs_handles_resp\n */\nstruct i40e_aqc_configure_vsi_ets_sla_bw_data {\n\tu8\ttc_valid_bits;\n\tu8\treserved[15];\n\t__le16\ttc_bw_credits[8]; /* FW writesback QS handles here */\n\n\t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n\t__le16\ttc_bw_max[2];\n\tu8\treserved1[28];\n};\n\nI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);\n\n/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)\n * responds with i40e_aqc_qs_handles_resp\n */\nstruct i40e_aqc_configure_vsi_tc_bw_data {\n\tu8\ttc_valid_bits;\n\tu8\treserved[3];\n\tu8\ttc_bw_credits[8];\n\tu8\treserved1[4];\n\t__le16\tqs_handles[8];\n};\n\nI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);\n\n/* Query vsi bw configuration (indirect 0x0408) */\nstruct i40e_aqc_query_vsi_bw_config_resp {\n\tu8\ttc_valid_bits;\n\tu8\ttc_suspended_bits;\n\tu8\treserved[14];\n\t__le16\tqs_handles[8];\n\tu8\treserved1[4];\n\t__le16\tport_bw_limit;\n\tu8\treserved2[2];\n\tu8\tmax_bw; /* 0-3, limit = 2^max */\n\tu8\treserved3[23];\n};\n\nI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);\n\n/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */\nstruct i40e_aqc_query_vsi_ets_sla_config_resp {\n\tu8\ttc_valid_bits;\n\tu8\treserved[3];\n\tu8\tshare_credits[8];\n\t__le16\tcredits[8];\n\n\t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n\t__le16\ttc_bw_max[2];\n};\n\nI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);\n\n/* Configure Switching Component Bandwidth Limit (direct 0x0410) */\nstruct i40e_aqc_configure_switching_comp_bw_limit {\n\t__le16\tseid;\n\tu8\treserved[2];\n\t__le16\tcredit;\n\tu8\treserved1[2];\n\tu8\tmax_bw; /* 0-3, limit = 2^max */\n\tu8\treserved2[7];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);\n\n/* Enable Physical Port ETS (indirect 0x0413)\n * Modify Physical Port ETS (indirect 0x0414)\n * Disable Physical Port ETS (indirect 0x0415)\n */\nstruct i40e_aqc_configure_switching_comp_ets_data {\n\tu8\treserved[4];\n\tu8\ttc_valid_bits;\n\tu8\tseepage;\n#define I40E_AQ_ETS_SEEPAGE_EN_MASK\t0x1\n\tu8\ttc_strict_priority_flags;\n\tu8\treserved1[17];\n\tu8\ttc_bw_share_credits[8];\n\tu8\treserved2[96];\n};\n\nI40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);\n\n/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */\nstruct i40e_aqc_configure_switching_comp_ets_bw_limit_data {\n\tu8\ttc_valid_bits;\n\tu8\treserved[15];\n\t__le16\ttc_bw_credit[8];\n\n\t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n\t__le16\ttc_bw_max[2];\n\tu8\treserved1[28];\n};\n\nI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data);\n\n/* Configure Switching Component Bandwidth Allocation per Tc\n * (indirect 0x0417)\n */\nstruct i40e_aqc_configure_switching_comp_bw_config_data {\n\tu8\ttc_valid_bits;\n\tu8\treserved[2];\n\tu8\tabsolute_credits; /* bool */\n\tu8\ttc_bw_share_credits[8];\n\tu8\treserved1[20];\n};\n\nI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);\n\n/* Query Switching Component Configuration (indirect 0x0418) */\nstruct i40e_aqc_query_switching_comp_ets_config_resp {\n\tu8\ttc_valid_bits;\n\tu8\treserved[35];\n\t__le16\tport_bw_limit;\n\tu8\treserved1[2];\n\tu8\ttc_bw_max; /* 0-3, limit = 2^max */\n\tu8\treserved2[23];\n};\n\nI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);\n\n/* Query PhysicalPort ETS Configuration (indirect 0x0419) */\nstruct i40e_aqc_query_port_ets_config_resp {\n\tu8\treserved[4];\n\tu8\ttc_valid_bits;\n\tu8\treserved1;\n\tu8\ttc_strict_priority_bits;\n\tu8\treserved2;\n\tu8\ttc_bw_share_credits[8];\n\t__le16\ttc_bw_limits[8];\n\n\t/* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */\n\t__le16\ttc_bw_max[2];\n\tu8\treserved3[32];\n};\n\nI40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);\n\n/* Query Switching Component Bandwidth Allocation per Traffic Type\n * (indirect 0x041A)\n */\nstruct i40e_aqc_query_switching_comp_bw_config_resp {\n\tu8\ttc_valid_bits;\n\tu8\treserved[2];\n\tu8\tabsolute_credits_enable; /* bool */\n\tu8\ttc_bw_share_credits[8];\n\t__le16\ttc_bw_limits[8];\n\n\t/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */\n\t__le16\ttc_bw_max[2];\n};\n\nI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);\n\n/* Suspend/resume port TX traffic\n * (direct 0x041B and 0x041C) uses the generic SEID struct\n */\n\n/* Configure partition BW\n * (indirect 0x041D)\n */\nstruct i40e_aqc_configure_partition_bw_data {\n\t__le16\tpf_valid_bits;\n\tu8\tmin_bw[16]; /* guaranteed bandwidth */\n\tu8\tmax_bw[16]; /* bandwidth limit */\n};\n\nI40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);\n\n/* Get and set the active HMC resource profile and status.\n * (direct 0x0500) and (direct 0x0501)\n */\nstruct i40e_aq_get_set_hmc_resource_profile {\n\tu8\tpm_profile;\n\tu8\tpe_vf_enabled;\n\tu8\treserved[14];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);\n\nenum i40e_aq_hmc_profile {\n\t/* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */\n\tI40E_HMC_PROFILE_DEFAULT\t= 1,\n\tI40E_HMC_PROFILE_FAVOR_VF\t= 2,\n\tI40E_HMC_PROFILE_EQUAL\t\t= 3,\n};\n\n#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK\t0xF\n#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK\t0x3F\n\n/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */\n\n/* set in param0 for get phy abilities to report qualified modules */\n#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES\t0x0001\n#define I40E_AQ_PHY_REPORT_INITIAL_VALUES\t0x0002\n\nenum i40e_aq_phy_type {\n\tI40E_PHY_TYPE_SGMII\t\t\t= 0x0,\n\tI40E_PHY_TYPE_1000BASE_KX\t\t= 0x1,\n\tI40E_PHY_TYPE_10GBASE_KX4\t\t= 0x2,\n\tI40E_PHY_TYPE_10GBASE_KR\t\t= 0x3,\n\tI40E_PHY_TYPE_40GBASE_KR4\t\t= 0x4,\n\tI40E_PHY_TYPE_XAUI\t\t\t= 0x5,\n\tI40E_PHY_TYPE_XFI\t\t\t= 0x6,\n\tI40E_PHY_TYPE_SFI\t\t\t= 0x7,\n\tI40E_PHY_TYPE_XLAUI\t\t\t= 0x8,\n\tI40E_PHY_TYPE_XLPPI\t\t\t= 0x9,\n\tI40E_PHY_TYPE_40GBASE_CR4_CU\t\t= 0xA,\n\tI40E_PHY_TYPE_10GBASE_CR1_CU\t\t= 0xB,\n\tI40E_PHY_TYPE_10GBASE_AOC\t\t= 0xC,\n\tI40E_PHY_TYPE_40GBASE_AOC\t\t= 0xD,\n\tI40E_PHY_TYPE_100BASE_TX\t\t= 0x11,\n\tI40E_PHY_TYPE_1000BASE_T\t\t= 0x12,\n\tI40E_PHY_TYPE_10GBASE_T\t\t\t= 0x13,\n\tI40E_PHY_TYPE_10GBASE_SR\t\t= 0x14,\n\tI40E_PHY_TYPE_10GBASE_LR\t\t= 0x15,\n\tI40E_PHY_TYPE_10GBASE_SFPP_CU\t\t= 0x16,\n\tI40E_PHY_TYPE_10GBASE_CR1\t\t= 0x17,\n\tI40E_PHY_TYPE_40GBASE_CR4\t\t= 0x18,\n\tI40E_PHY_TYPE_40GBASE_SR4\t\t= 0x19,\n\tI40E_PHY_TYPE_40GBASE_LR4\t\t= 0x1A,\n\tI40E_PHY_TYPE_1000BASE_SX\t\t= 0x1B,\n\tI40E_PHY_TYPE_1000BASE_LX\t\t= 0x1C,\n\tI40E_PHY_TYPE_1000BASE_T_OPTICAL\t= 0x1D,\n\tI40E_PHY_TYPE_20GBASE_KR2\t\t= 0x1E,\n\tI40E_PHY_TYPE_MAX\n};\n\n#define I40E_LINK_SPEED_100MB_SHIFT\t0x1\n#define I40E_LINK_SPEED_1000MB_SHIFT\t0x2\n#define I40E_LINK_SPEED_10GB_SHIFT\t0x3\n#define I40E_LINK_SPEED_40GB_SHIFT\t0x4\n#define I40E_LINK_SPEED_20GB_SHIFT\t0x5\n\nenum i40e_aq_link_speed {\n\tI40E_LINK_SPEED_UNKNOWN\t= 0,\n\tI40E_LINK_SPEED_100MB\t= (1 << I40E_LINK_SPEED_100MB_SHIFT),\n\tI40E_LINK_SPEED_1GB\t= (1 << I40E_LINK_SPEED_1000MB_SHIFT),\n\tI40E_LINK_SPEED_10GB\t= (1 << I40E_LINK_SPEED_10GB_SHIFT),\n\tI40E_LINK_SPEED_40GB\t= (1 << I40E_LINK_SPEED_40GB_SHIFT),\n\tI40E_LINK_SPEED_20GB\t= (1 << I40E_LINK_SPEED_20GB_SHIFT)\n};\n\nstruct i40e_aqc_module_desc {\n\tu8 oui[3];\n\tu8 reserved1;\n\tu8 part_number[16];\n\tu8 revision[4];\n\tu8 reserved2[8];\n};\n\nI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);\n\nstruct i40e_aq_get_phy_abilities_resp {\n\t__le32\tphy_type; /* bitmap using the above enum for offsets */\n\tu8\tlink_speed; /* bitmap using the above enum bit patterns */\n\tu8\tabilities;\n#define I40E_AQ_PHY_FLAG_PAUSE_TX\t0x01\n#define I40E_AQ_PHY_FLAG_PAUSE_RX\t0x02\n#define I40E_AQ_PHY_FLAG_LOW_POWER\t0x04\n#define I40E_AQ_PHY_LINK_ENABLED\t0x08\n#define I40E_AQ_PHY_AN_ENABLED\t\t0x10\n#define I40E_AQ_PHY_FLAG_MODULE_QUAL\t0x20\n\t__le16\teee_capability;\n#define I40E_AQ_EEE_100BASE_TX\t\t0x0002\n#define I40E_AQ_EEE_1000BASE_T\t\t0x0004\n#define I40E_AQ_EEE_10GBASE_T\t\t0x0008\n#define I40E_AQ_EEE_1000BASE_KX\t\t0x0010\n#define I40E_AQ_EEE_10GBASE_KX4\t\t0x0020\n#define I40E_AQ_EEE_10GBASE_KR\t\t0x0040\n\t__le32\teeer_val;\n\tu8\td3_lpan;\n#define I40E_AQ_SET_PHY_D3_LPAN_ENA\t0x01\n\tu8\treserved[3];\n\tu8\tphy_id[4];\n\tu8\tmodule_type[3];\n\tu8\tqualified_module_count;\n#define I40E_AQ_PHY_MAX_QMS\t\t16\n\tstruct i40e_aqc_module_desc\tqualified_module[I40E_AQ_PHY_MAX_QMS];\n};\n\nI40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);\n\n/* Set PHY Config (direct 0x0601) */\nstruct i40e_aq_set_phy_config { /* same bits as above in all */\n\t__le32\tphy_type;\n\tu8\tlink_speed;\n\tu8\tabilities;\n/* bits 0-2 use the values from get_phy_abilities_resp */\n#define I40E_AQ_PHY_ENABLE_LINK\t\t0x08\n#define I40E_AQ_PHY_ENABLE_AN\t\t0x10\n#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK\t0x20\n\t__le16\teee_capability;\n\t__le32\teeer;\n\tu8\tlow_power_ctrl;\n\tu8\treserved[3];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);\n\n/* Set MAC Config command data structure (direct 0x0603) */\nstruct i40e_aq_set_mac_config {\n\t__le16\tmax_frame_size;\n\tu8\tparams;\n#define I40E_AQ_SET_MAC_CONFIG_CRC_EN\t\t0x04\n#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK\t0x78\n#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT\t3\n#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE\t0x0\n#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX\t0xF\n#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX\t0x9\n#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX\t0x8\n#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX\t0x7\n#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX\t0x6\n#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX\t0x5\n#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX\t0x4\n#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX\t0x3\n#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX\t0x2\n#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX\t0x1\n\tu8\ttx_timer_priority; /* bitmap */\n\t__le16\ttx_timer_value;\n\t__le16\tfc_refresh_threshold;\n\tu8\treserved[8];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);\n\n/* Restart Auto-Negotiation (direct 0x605) */\nstruct i40e_aqc_set_link_restart_an {\n\tu8\tcommand;\n#define I40E_AQ_PHY_RESTART_AN\t0x02\n#define I40E_AQ_PHY_LINK_ENABLE\t0x04\n\tu8\treserved[15];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);\n\n/* Get Link Status cmd & response data structure (direct 0x0607) */\nstruct i40e_aqc_get_link_status {\n\t__le16\tcommand_flags; /* only field set on command */\n#define I40E_AQ_LSE_MASK\t\t0x3\n#define I40E_AQ_LSE_NOP\t\t\t0x0\n#define I40E_AQ_LSE_DISABLE\t\t0x2\n#define I40E_AQ_LSE_ENABLE\t\t0x3\n/* only response uses this flag */\n#define I40E_AQ_LSE_IS_ENABLED\t\t0x1\n\tu8\tphy_type; /* i40e_aq_phy_type */\n\tu8\tlink_speed; /* i40e_aq_link_speed */\n\tu8\tlink_info;\n#define I40E_AQ_LINK_UP\t\t\t0x01\n#define I40E_AQ_LINK_FAULT\t\t0x02\n#define I40E_AQ_LINK_FAULT_TX\t\t0x04\n#define I40E_AQ_LINK_FAULT_RX\t\t0x08\n#define I40E_AQ_LINK_FAULT_REMOTE\t0x10\n#define I40E_AQ_MEDIA_AVAILABLE\t\t0x40\n#define I40E_AQ_SIGNAL_DETECT\t\t0x80\n\tu8\tan_info;\n#define I40E_AQ_AN_COMPLETED\t\t0x01\n#define I40E_AQ_LP_AN_ABILITY\t\t0x02\n#define I40E_AQ_PD_FAULT\t\t0x04\n#define I40E_AQ_FEC_EN\t\t\t0x08\n#define I40E_AQ_PHY_LOW_POWER\t\t0x10\n#define I40E_AQ_LINK_PAUSE_TX\t\t0x20\n#define I40E_AQ_LINK_PAUSE_RX\t\t0x40\n#define I40E_AQ_QUALIFIED_MODULE\t0x80\n\tu8\text_info;\n#define I40E_AQ_LINK_PHY_TEMP_ALARM\t0x01\n#define I40E_AQ_LINK_XCESSIVE_ERRORS\t0x02\n#define I40E_AQ_LINK_TX_SHIFT\t\t0x02\n#define I40E_AQ_LINK_TX_MASK\t\t(0x03 << I40E_AQ_LINK_TX_SHIFT)\n#define I40E_AQ_LINK_TX_ACTIVE\t\t0x00\n#define I40E_AQ_LINK_TX_DRAINED\t\t0x01\n#define I40E_AQ_LINK_TX_FLUSHED\t\t0x03\n#define I40E_AQ_LINK_FORCED_40G\t\t0x10\n\tu8\tloopback; /* use defines from i40e_aqc_set_lb_mode */\n\t__le16\tmax_frame_size;\n\tu8\tconfig;\n#define I40E_AQ_CONFIG_CRC_ENA\t\t0x04\n#define I40E_AQ_CONFIG_PACING_MASK\t0x78\n\tu8\treserved[5];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);\n\n/* Set event mask command (direct 0x613) */\nstruct i40e_aqc_set_phy_int_mask {\n\tu8\treserved[8];\n\t__le16\tevent_mask;\n#define I40E_AQ_EVENT_LINK_UPDOWN\t0x0002\n#define I40E_AQ_EVENT_MEDIA_NA\t\t0x0004\n#define I40E_AQ_EVENT_LINK_FAULT\t0x0008\n#define I40E_AQ_EVENT_PHY_TEMP_ALARM\t0x0010\n#define I40E_AQ_EVENT_EXCESSIVE_ERRORS\t0x0020\n#define I40E_AQ_EVENT_SIGNAL_DETECT\t0x0040\n#define I40E_AQ_EVENT_AN_COMPLETED\t0x0080\n#define I40E_AQ_EVENT_MODULE_QUAL_FAIL\t0x0100\n#define I40E_AQ_EVENT_PORT_TX_SUSPENDED\t0x0200\n\tu8\treserved1[6];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);\n\n/* Get Local AN advt register (direct 0x0614)\n * Set Local AN advt register (direct 0x0615)\n * Get Link Partner AN advt register (direct 0x0616)\n */\nstruct i40e_aqc_an_advt_reg {\n\t__le32\tlocal_an_reg0;\n\t__le16\tlocal_an_reg1;\n\tu8\treserved[10];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);\n\n/* Set Loopback mode (0x0618) */\nstruct i40e_aqc_set_lb_mode {\n\t__le16\tlb_mode;\n#define I40E_AQ_LB_PHY_LOCAL\t0x01\n#define I40E_AQ_LB_PHY_REMOTE\t0x02\n#define I40E_AQ_LB_MAC_LOCAL\t0x04\n\tu8\treserved[14];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);\n\n/* Set PHY Debug command (0x0622) */\nstruct i40e_aqc_set_phy_debug {\n\tu8\tcommand_flags;\n#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL\t0x02\n#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT\t2\n#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK\t(0x03 << \\\n\t\t\t\t\tI40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)\n#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE\t0x00\n#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD\t0x01\n#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT\t0x02\n#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW\t0x10\n\tu8\treserved[15];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);\n\nenum i40e_aq_phy_reg_type {\n\tI40E_AQC_PHY_REG_INTERNAL\t= 0x1,\n\tI40E_AQC_PHY_REG_EXERNAL_BASET\t= 0x2,\n\tI40E_AQC_PHY_REG_EXERNAL_MODULE\t= 0x3\n};\n\n/* NVM Read command (indirect 0x0701)\n * NVM Erase commands (direct 0x0702)\n * NVM Update commands (indirect 0x0703)\n */\nstruct i40e_aqc_nvm_update {\n\tu8\tcommand_flags;\n#define I40E_AQ_NVM_LAST_CMD\t0x01\n#define I40E_AQ_NVM_FLASH_ONLY\t0x80\n\tu8\tmodule_pointer;\n\t__le16\tlength;\n\t__le32\toffset;\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);\n\n/* NVM Config Read (indirect 0x0704) */\nstruct i40e_aqc_nvm_config_read {\n\t__le16\tcmd_flags;\n#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK\t1\n#define I40E_AQ_ANVM_READ_SINGLE_FEATURE\t\t0\n#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES\t\t1\n\t__le16\telement_count;\n\t__le16\telement_id; /* Feature/field ID */\n\t__le16\telement_id_msw;\t/* MSWord of field ID */\n\t__le32\taddress_high;\n\t__le32\taddress_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);\n\n/* NVM Config Write (indirect 0x0705) */\nstruct i40e_aqc_nvm_config_write {\n\t__le16\tcmd_flags;\n\t__le16\telement_count;\n\tu8\treserved[4];\n\t__le32\taddress_high;\n\t__le32\taddress_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);\n\n/* Used for 0x0704 as well as for 0x0705 commands */\n#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT\t\t1\n#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK\t\t(1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)\n#define I40E_AQ_ANVM_FEATURE\t\t\t\t0\n#define I40E_AQ_ANVM_IMMEDIATE_FIELD\t\t\t(1 << FEATURE_OR_IMMEDIATE_SHIFT)\nstruct i40e_aqc_nvm_config_data_feature {\n\t__le16 feature_id;\n#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY\t\t0x01\n#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP\t\t0x08\n#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR\t\t0x10\n\t__le16 feature_options;\n\t__le16 feature_selection;\n};\n\nI40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);\n\nstruct i40e_aqc_nvm_config_data_immediate_field {\n\t__le32 field_id;\n\t__le32 field_value;\n\t__le16 field_options;\n\t__le16 reserved;\n};\n\nI40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);\n\n/* Send to PF command (indirect 0x0801) id is only used by PF\n * Send to VF command (indirect 0x0802) id is only used by PF\n * Send to Peer PF command (indirect 0x0803)\n */\nstruct i40e_aqc_pf_vf_message {\n\t__le32\tid;\n\tu8\treserved[4];\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);\n\n/* Alternate structure */\n\n/* Direct write (direct 0x0900)\n * Direct read (direct 0x0902)\n */\nstruct i40e_aqc_alternate_write {\n\t__le32 address0;\n\t__le32 data0;\n\t__le32 address1;\n\t__le32 data1;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);\n\n/* Indirect write (indirect 0x0901)\n * Indirect read (indirect 0x0903)\n */\n\nstruct i40e_aqc_alternate_ind_write {\n\t__le32 address;\n\t__le32 length;\n\t__le32 addr_high;\n\t__le32 addr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);\n\n/* Done alternate write (direct 0x0904)\n * uses i40e_aq_desc\n */\nstruct i40e_aqc_alternate_write_done {\n\t__le16\tcmd_flags;\n#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK\t1\n#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY\t0\n#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI\t1\n#define I40E_AQ_ALTERNATE_RESET_NEEDED\t\t2\n\tu8\treserved[14];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);\n\n/* Set OEM mode (direct 0x0905) */\nstruct i40e_aqc_alternate_set_mode {\n\t__le32\tmode;\n#define I40E_AQ_ALTERNATE_MODE_NONE\t0\n#define I40E_AQ_ALTERNATE_MODE_OEM\t1\n\tu8\treserved[12];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);\n\n/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */\n\n/* async events 0x10xx */\n\n/* Lan Queue Overflow Event (direct, 0x1001) */\nstruct i40e_aqc_lan_overflow {\n\t__le32\tprtdcb_rupto;\n\t__le32\totx_ctl;\n\tu8\treserved[8];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);\n\n/* Get LLDP MIB (indirect 0x0A00) */\nstruct i40e_aqc_lldp_get_mib {\n\tu8\ttype;\n\tu8\treserved1;\n#define I40E_AQ_LLDP_MIB_TYPE_MASK\t\t0x3\n#define I40E_AQ_LLDP_MIB_LOCAL\t\t\t0x0\n#define I40E_AQ_LLDP_MIB_REMOTE\t\t\t0x1\n#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE\t0x2\n#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK\t\t0xC\n#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT\t\t0x2\n#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE\t0x0\n#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR\t0x1\n#define I40E_AQ_LLDP_TX_SHIFT\t\t\t0x4\n#define I40E_AQ_LLDP_TX_MASK\t\t\t(0x03 << I40E_AQ_LLDP_TX_SHIFT)\n/* TX pause flags use I40E_AQ_LINK_TX_* above */\n\t__le16\tlocal_len;\n\t__le16\tremote_len;\n\tu8\treserved2[2];\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);\n\n/* Configure LLDP MIB Change Event (direct 0x0A01)\n * also used for the event (with type in the command field)\n */\nstruct i40e_aqc_lldp_update_mib {\n\tu8\tcommand;\n#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE\t0x0\n#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE\t0x1\n\tu8\treserved[7];\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);\n\n/* Add LLDP TLV (indirect 0x0A02)\n * Delete LLDP TLV (indirect 0x0A04)\n */\nstruct i40e_aqc_lldp_add_tlv {\n\tu8\ttype; /* only nearest bridge and non-TPMR from 0x0A00 */\n\tu8\treserved1[1];\n\t__le16\tlen;\n\tu8\treserved2[4];\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);\n\n/* Update LLDP TLV (indirect 0x0A03) */\nstruct i40e_aqc_lldp_update_tlv {\n\tu8\ttype; /* only nearest bridge and non-TPMR from 0x0A00 */\n\tu8\treserved;\n\t__le16\told_len;\n\t__le16\tnew_offset;\n\t__le16\tnew_len;\n\t__le32\taddr_high;\n\t__le32\taddr_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);\n\n/* Stop LLDP (direct 0x0A05) */\nstruct i40e_aqc_lldp_stop {\n\tu8\tcommand;\n#define I40E_AQ_LLDP_AGENT_STOP\t\t0x0\n#define I40E_AQ_LLDP_AGENT_SHUTDOWN\t0x1\n\tu8\treserved[15];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);\n\n/* Start LLDP (direct 0x0A06) */\n\nstruct i40e_aqc_lldp_start {\n\tu8\tcommand;\n#define I40E_AQ_LLDP_AGENT_START\t0x1\n\tu8\treserved[15];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);\n\n/* Get CEE DCBX Oper Config (0x0A07)\n * uses the generic descriptor struct\n * returns below as indirect response\n */\n\n#define I40E_AQC_CEE_APP_FCOE_SHIFT\t0x0\n#define I40E_AQC_CEE_APP_FCOE_MASK\t(0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)\n#define I40E_AQC_CEE_APP_ISCSI_SHIFT\t0x3\n#define I40E_AQC_CEE_APP_ISCSI_MASK\t(0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)\n#define I40E_AQC_CEE_APP_FIP_SHIFT\t0x8\n#define I40E_AQC_CEE_APP_FIP_MASK\t(0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)\n#define I40E_AQC_CEE_PG_STATUS_SHIFT\t0x0\n#define I40E_AQC_CEE_PG_STATUS_MASK\t(0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)\n#define I40E_AQC_CEE_PFC_STATUS_SHIFT\t0x3\n#define I40E_AQC_CEE_PFC_STATUS_MASK\t(0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)\n#define I40E_AQC_CEE_APP_STATUS_SHIFT\t0x8\n#define I40E_AQC_CEE_APP_STATUS_MASK\t(0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)\nstruct i40e_aqc_get_cee_dcb_cfg_v1_resp {\n\tu8\treserved1;\n\tu8\toper_num_tc;\n\tu8\toper_prio_tc[4];\n\tu8\treserved2;\n\tu8\toper_tc_bw[8];\n\tu8\toper_pfc_en;\n\tu8\treserved3;\n\t__le16\toper_app_prio;\n\tu8\treserved4;\n\t__le16\ttlv_status;\n};\n\nI40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);\n\nstruct i40e_aqc_get_cee_dcb_cfg_resp {\n\tu8\toper_num_tc;\n\tu8\toper_prio_tc[4];\n\tu8\toper_tc_bw[8];\n\tu8\toper_pfc_en;\n\t__le16\toper_app_prio;\n\t__le32\ttlv_status;\n\tu8\treserved[12];\n};\n\nI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);\n\n/*\tSet Local LLDP MIB (indirect 0x0A08)\n *\tUsed to replace the local MIB of a given LLDP agent. e.g. DCBx\n */\nstruct i40e_aqc_lldp_set_local_mib {\n#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT\t0\n#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK\t\t(1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)\n\tu8\ttype;\n\tu8\treserved0;\n\t__le16\tlength;\n\tu8\treserved1[4];\n\t__le32\taddress_high;\n\t__le32\taddress_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);\n\n/*\tStop/Start LLDP Agent (direct 0x0A09)\n *\tUsed for stopping/starting specific LLDP agent. e.g. DCBx\n */\nstruct i40e_aqc_lldp_stop_start_specific_agent {\n#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT\t0\n#define I40E_AQC_START_SPECIFIC_AGENT_MASK\t(1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)\n\tu8\tcommand;\n\tu8\treserved[15];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);\n\n/* Add Udp Tunnel command and completion (direct 0x0B00) */\nstruct i40e_aqc_add_udp_tunnel {\n\t__le16\tudp_port;\n\tu8\treserved0[3];\n\tu8\tprotocol_type;\n#define I40E_AQC_TUNNEL_TYPE_VXLAN\t0x00\n#define I40E_AQC_TUNNEL_TYPE_NGE\t0x01\n#define I40E_AQC_TUNNEL_TYPE_TEREDO\t0x10\n\tu8\treserved1[10];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);\n\nstruct i40e_aqc_add_udp_tunnel_completion {\n\t__le16 udp_port;\n\tu8\tfilter_entry_index;\n\tu8\tmultiple_pfs;\n#define I40E_AQC_SINGLE_PF\t\t0x0\n#define I40E_AQC_MULTIPLE_PFS\t\t0x1\n\tu8\ttotal_filters;\n\tu8\treserved[11];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);\n\n/* remove UDP Tunnel command (0x0B01) */\nstruct i40e_aqc_remove_udp_tunnel {\n\tu8\treserved[2];\n\tu8\tindex; /* 0 to 15 */\n\tu8\treserved2[13];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);\n\nstruct i40e_aqc_del_udp_tunnel_completion {\n\t__le16\tudp_port;\n\tu8\tindex; /* 0 to 15 */\n\tu8\tmultiple_pfs;\n\tu8\ttotal_filters_used;\n\tu8\treserved1[11];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);\n\n/* tunnel key structure 0x0B10 */\n\nstruct i40e_aqc_tunnel_key_structure {\n\tu8\tkey1_off;\n\tu8\tkey2_off;\n\tu8\tkey1_len; /* 0 to 15 */\n\tu8\tkey2_len; /* 0 to 15 */\n\tu8\tflags;\n#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE\t0x01\n/* response flags */\n#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS\t0x01\n#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED\t0x02\n#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN\t0x03\n\tu8\tnetwork_key_index;\n#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN\t\t0x0\n#define I40E_AQC_NETWORK_KEY_INDEX_NGE\t\t\t0x1\n#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP\t0x2\n#define I40E_AQC_NETWORK_KEY_INDEX_GRE\t\t\t0x3\n\tu8\treserved[10];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);\n\n/* OEM mode commands (direct 0xFE0x) */\nstruct i40e_aqc_oem_param_change {\n\t__le32\tparam_type;\n#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL\t0\n#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL\t1\n#define I40E_AQ_OEM_PARAM_MAC\t\t2\n\t__le32\tparam_value1;\n\t__le16\tparam_value2;\n\tu8\treserved[6];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);\n\nstruct i40e_aqc_oem_state_change {\n\t__le32\tstate;\n#define I40E_AQ_OEM_STATE_LINK_DOWN\t0x0\n#define I40E_AQ_OEM_STATE_LINK_UP\t0x1\n\tu8\treserved[12];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);\n\n/* Initialize OCSD (0xFE02, direct) */\nstruct i40e_aqc_opc_oem_ocsd_initialize {\n\tu8 type_status;\n\tu8 reserved1[3];\n\t__le32 ocsd_memory_block_addr_high;\n\t__le32 ocsd_memory_block_addr_low;\n\t__le32 requested_update_interval;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);\n\n/* Initialize OCBB (0xFE03, direct) */\nstruct i40e_aqc_opc_oem_ocbb_initialize {\n\tu8 type_status;\n\tu8 reserved1[3];\n\t__le32 ocbb_memory_block_addr_high;\n\t__le32 ocbb_memory_block_addr_low;\n\tu8 reserved2[4];\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);\n\n/* debug commands */\n\n/* get device id (0xFF00) uses the generic structure */\n\n/* set test more (0xFF01, internal) */\n\nstruct i40e_acq_set_test_mode {\n\tu8\tmode;\n#define I40E_AQ_TEST_PARTIAL\t0\n#define I40E_AQ_TEST_FULL\t1\n#define I40E_AQ_TEST_NVM\t2\n\tu8\treserved[3];\n\tu8\tcommand;\n#define I40E_AQ_TEST_OPEN\t0\n#define I40E_AQ_TEST_CLOSE\t1\n#define I40E_AQ_TEST_INC\t2\n\tu8\treserved2[3];\n\t__le32\taddress_high;\n\t__le32\taddress_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);\n\n/* Debug Read Register command (0xFF03)\n * Debug Write Register command (0xFF04)\n */\nstruct i40e_aqc_debug_reg_read_write {\n\t__le32 reserved;\n\t__le32 address;\n\t__le32 value_high;\n\t__le32 value_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);\n\n/* Scatter/gather Reg Read (indirect 0xFF05)\n * Scatter/gather Reg Write (indirect 0xFF06)\n */\n\n/* i40e_aq_desc is used for the command */\nstruct i40e_aqc_debug_reg_sg_element_data {\n\t__le32 address;\n\t__le32 value;\n};\n\n/* Debug Modify register (direct 0xFF07) */\nstruct i40e_aqc_debug_modify_reg {\n\t__le32 address;\n\t__le32 value;\n\t__le32 clear_mask;\n\t__le32 set_mask;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);\n\n/* dump internal data (0xFF08, indirect) */\n\n#define I40E_AQ_CLUSTER_ID_AUX\t\t0\n#define I40E_AQ_CLUSTER_ID_SWITCH_FLU\t1\n#define I40E_AQ_CLUSTER_ID_TXSCHED\t2\n#define I40E_AQ_CLUSTER_ID_HMC\t\t3\n#define I40E_AQ_CLUSTER_ID_MAC0\t\t4\n#define I40E_AQ_CLUSTER_ID_MAC1\t\t5\n#define I40E_AQ_CLUSTER_ID_MAC2\t\t6\n#define I40E_AQ_CLUSTER_ID_MAC3\t\t7\n#define I40E_AQ_CLUSTER_ID_DCB\t\t8\n#define I40E_AQ_CLUSTER_ID_EMP_MEM\t9\n#define I40E_AQ_CLUSTER_ID_PKT_BUF\t10\n#define I40E_AQ_CLUSTER_ID_ALTRAM\t11\n\nstruct i40e_aqc_debug_dump_internals {\n\tu8\tcluster_id;\n\tu8\ttable_id;\n\t__le16\tdata_size;\n\t__le32\tidx;\n\t__le32\taddress_high;\n\t__le32\taddress_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);\n\nstruct i40e_aqc_debug_modify_internals {\n\tu8\tcluster_id;\n\tu8\tcluster_specific_params[7];\n\t__le32\taddress_high;\n\t__le32\taddress_low;\n};\n\nI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);\n\n#endif\n" }, { "path": "drivers/net/i40e/base/i40e_alloc.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _I40E_ALLOC_H_\n#define _I40E_ALLOC_H_\n\nstruct i40e_hw;\n\n/* Memory allocation types */\nenum i40e_memory_type {\n\ti40e_mem_arq_buf = 0,\t\t/* ARQ indirect command buffer */\n\ti40e_mem_asq_buf = 1,\n\ti40e_mem_atq_buf = 2,\t\t/* ATQ indirect command buffer */\n\ti40e_mem_arq_ring = 3,\t\t/* ARQ descriptor ring */\n\ti40e_mem_atq_ring = 4,\t\t/* ATQ descriptor ring */\n\ti40e_mem_pd = 5,\t\t/* Page Descriptor */\n\ti40e_mem_bp = 6,\t\t/* Backing Page - 4KB */\n\ti40e_mem_bp_jumbo = 7,\t\t/* Backing Page - > 4KB */\n\ti40e_mem_reserved\n};\n\n/* prototype for functions used for dynamic memory allocation */\nenum i40e_status_code i40e_allocate_dma_mem(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_dma_mem *mem,\n\t\t\t\t\t enum i40e_memory_type type,\n\t\t\t\t\t u64 size, u32 alignment);\nenum i40e_status_code i40e_free_dma_mem(struct i40e_hw *hw,\n\t\t\t\t\tstruct i40e_dma_mem *mem);\nenum i40e_status_code i40e_allocate_virt_mem(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_virt_mem *mem,\n\t\t\t\t\t u32 size);\nenum i40e_status_code i40e_free_virt_mem(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_virt_mem *mem);\n\n#endif /* _I40E_ALLOC_H_ */\n" }, { "path": "drivers/net/i40e/base/i40e_common.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"i40e_type.h\"\n#include \"i40e_adminq.h\"\n#include \"i40e_prototype.h\"\n#include \"i40e_virtchnl.h\"\n\n\n/**\n * i40e_set_mac_type - Sets MAC type\n * @hw: pointer to the HW structure\n *\n * This function sets the mac type of the adapter based on the\n * vendor ID and device ID stored in the hw structure.\n **/\n#if defined(INTEGRATED_VF) || defined(VF_DRIVER)\nenum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)\n#else\nSTATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)\n#endif\n{\n\tenum i40e_status_code status = I40E_SUCCESS;\n\n\tDEBUGFUNC(\"i40e_set_mac_type\\n\");\n\n\tif (hw->vendor_id == I40E_INTEL_VENDOR_ID) {\n\t\tswitch (hw->device_id) {\n\t\tcase I40E_DEV_ID_SFP_XL710:\n\t\tcase I40E_DEV_ID_QEMU:\n\t\tcase I40E_DEV_ID_KX_A:\n\t\tcase I40E_DEV_ID_KX_B:\n\t\tcase I40E_DEV_ID_KX_C:\n\t\tcase I40E_DEV_ID_QSFP_A:\n\t\tcase I40E_DEV_ID_QSFP_B:\n\t\tcase I40E_DEV_ID_QSFP_C:\n\t\tcase I40E_DEV_ID_10G_BASE_T:\n\t\t\thw->mac.type = I40E_MAC_XL710;\n\t\t\tbreak;\n\t\tcase I40E_DEV_ID_VF:\n\t\tcase I40E_DEV_ID_VF_HV:\n\t\t\thw->mac.type = I40E_MAC_VF;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\thw->mac.type = I40E_MAC_GENERIC;\n\t\t\tbreak;\n\t\t}\n\t} else {\n\t\tstatus = I40E_ERR_DEVICE_NOT_SUPPORTED;\n\t}\n\n\tDEBUGOUT2(\"i40e_set_mac_type found mac: %d, returns: %d\\n\",\n\t\t hw->mac.type, status);\n\treturn status;\n}\n\n/**\n * i40e_debug_aq\n * @hw: debug mask related to admin queue\n * @mask: debug mask\n * @desc: pointer to admin queue descriptor\n * @buffer: pointer to command buffer\n * @buf_len: max length of buffer\n *\n * Dumps debug log about adminq command with descriptor contents.\n **/\nvoid i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,\n\t\t void *buffer, u16 buf_len)\n{\n\tstruct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;\n\tu16 len = LE16_TO_CPU(aq_desc->datalen);\n\tu8 *buf = (u8 *)buffer;\n\tu16 i = 0;\n\n\tif ((!(mask & hw->debug_mask)) || (desc == NULL))\n\t\treturn;\n\n\ti40e_debug(hw, mask,\n\t\t \"AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\\n\",\n\t\t LE16_TO_CPU(aq_desc->opcode),\n\t\t LE16_TO_CPU(aq_desc->flags),\n\t\t LE16_TO_CPU(aq_desc->datalen),\n\t\t LE16_TO_CPU(aq_desc->retval));\n\ti40e_debug(hw, mask, \"\\tcookie (h,l) 0x%08X 0x%08X\\n\",\n\t\t LE32_TO_CPU(aq_desc->cookie_high),\n\t\t LE32_TO_CPU(aq_desc->cookie_low));\n\ti40e_debug(hw, mask, \"\\tparam (0,1) 0x%08X 0x%08X\\n\",\n\t\t LE32_TO_CPU(aq_desc->params.internal.param0),\n\t\t LE32_TO_CPU(aq_desc->params.internal.param1));\n\ti40e_debug(hw, mask, \"\\taddr (h,l) 0x%08X 0x%08X\\n\",\n\t\t LE32_TO_CPU(aq_desc->params.external.addr_high),\n\t\t LE32_TO_CPU(aq_desc->params.external.addr_low));\n\n\tif ((buffer != NULL) && (aq_desc->datalen != 0)) {\n\t\ti40e_debug(hw, mask, \"AQ CMD Buffer:\\n\");\n\t\tif (buf_len < len)\n\t\t\tlen = buf_len;\n\t\t/* write the full 16-byte chunks */\n\t\tfor (i = 0; i < (len - 16); i += 16)\n\t\t\ti40e_debug(hw, mask,\n\t\t\t\t \"\\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\\n\",\n\t\t\t\t i, buf[i], buf[i+1], buf[i+2], buf[i+3],\n\t\t\t\t buf[i+4], buf[i+5], buf[i+6], buf[i+7],\n\t\t\t\t buf[i+8], buf[i+9], buf[i+10], buf[i+11],\n\t\t\t\t buf[i+12], buf[i+13], buf[i+14], buf[i+15]);\n\t\t/* write whatever's left over without overrunning the buffer */\n\t\tif (i < len) {\n\t\t\tchar d_buf[80];\n\t\t\tint j = 0;\n\n\t\t\tmemset(d_buf, 0, sizeof(d_buf));\n\t\t\tj += sprintf(d_buf, \"\\t0x%04X \", i);\n\t\t\twhile (i < len)\n\t\t\t\tj += sprintf(&d_buf[j], \" %02X\", buf[i++]);\n\t\t\ti40e_debug(hw, mask, \"%s\\n\", d_buf);\n\t\t}\n\t}\n}\n\n/**\n * i40e_check_asq_alive\n * @hw: pointer to the hw struct\n *\n * Returns true if Queue is enabled else false.\n **/\nbool i40e_check_asq_alive(struct i40e_hw *hw)\n{\n\tif (hw->aq.asq.len)\n\t\treturn !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);\n\telse\n\t\treturn false;\n}\n\n/**\n * i40e_aq_queue_shutdown\n * @hw: pointer to the hw struct\n * @unloading: is the driver unloading itself\n *\n * Tell the Firmware that we're shutting down the AdminQ and whether\n * or not the driver is unloading as well.\n **/\nenum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,\n\t\t\t\t\t bool unloading)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_queue_shutdown *cmd =\n\t\t(struct i40e_aqc_queue_shutdown *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_queue_shutdown);\n\n\tif (unloading)\n\t\tcmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);\n\n\treturn status;\n}\n\n/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the\n * hardware to a bit-field that can be used by SW to more easily determine the\n * packet type.\n *\n * Macros are used to shorten the table lines and make this table human\n * readable.\n *\n * We store the PTYPE in the top byte of the bit field - this is just so that\n * we can check that the table doesn't have a row missing, as the index into\n * the table should be the PTYPE.\n *\n * Typical work flow:\n *\n * IF NOT i40e_ptype_lookup[ptype].known\n * THEN\n * Packet is unknown\n * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP\n * Use the rest of the fields to look at the tunnels, inner protocols, etc\n * ELSE\n * Use the enum i40e_rx_l2_ptype to decode the packet type\n * ENDIF\n */\n\n/* macro to make the table lines short */\n#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\\\n\t{\tPTYPE, \\\n\t\t1, \\\n\t\tI40E_RX_PTYPE_OUTER_##OUTER_IP, \\\n\t\tI40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \\\n\t\tI40E_RX_PTYPE_##OUTER_FRAG, \\\n\t\tI40E_RX_PTYPE_TUNNEL_##T, \\\n\t\tI40E_RX_PTYPE_TUNNEL_END_##TE, \\\n\t\tI40E_RX_PTYPE_##TEF, \\\n\t\tI40E_RX_PTYPE_INNER_PROT_##I, \\\n\t\tI40E_RX_PTYPE_PAYLOAD_LAYER_##PL }\n\n#define I40E_PTT_UNUSED_ENTRY(PTYPE) \\\n\t\t{ PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }\n\n/* shorter macros makes the table fit but are terse */\n#define I40E_RX_PTYPE_NOF\t\tI40E_RX_PTYPE_NOT_FRAG\n#define I40E_RX_PTYPE_FRG\t\tI40E_RX_PTYPE_FRAG\n#define I40E_RX_PTYPE_INNER_PROT_TS\tI40E_RX_PTYPE_INNER_PROT_TIMESYNC\n\n/* Lookup table mapping the HW PTYPE to the bit field for decoding */\nstruct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {\n\t/* L2 Packet types */\n\tI40E_PTT_UNUSED_ENTRY(0),\n\tI40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),\n\tI40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),\n\tI40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),\n\tI40E_PTT_UNUSED_ENTRY(4),\n\tI40E_PTT_UNUSED_ENTRY(5),\n\tI40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),\n\tI40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),\n\tI40E_PTT_UNUSED_ENTRY(8),\n\tI40E_PTT_UNUSED_ENTRY(9),\n\tI40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),\n\tI40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),\n\tI40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),\n\n\t/* Non Tunneled IPv4 */\n\tI40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(25),\n\tI40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),\n\tI40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),\n\tI40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),\n\n\t/* IPv4 --> IPv4 */\n\tI40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),\n\tI40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),\n\tI40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(32),\n\tI40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),\n\tI40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),\n\tI40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),\n\n\t/* IPv4 --> IPv6 */\n\tI40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),\n\tI40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),\n\tI40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(39),\n\tI40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),\n\tI40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),\n\tI40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),\n\n\t/* IPv4 --> GRE/NAT */\n\tI40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),\n\n\t/* IPv4 --> GRE/NAT --> IPv4 */\n\tI40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),\n\tI40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),\n\tI40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(47),\n\tI40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),\n\tI40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),\n\tI40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),\n\n\t/* IPv4 --> GRE/NAT --> IPv6 */\n\tI40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),\n\tI40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),\n\tI40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(54),\n\tI40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),\n\tI40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),\n\tI40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),\n\n\t/* IPv4 --> GRE/NAT --> MAC */\n\tI40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),\n\n\t/* IPv4 --> GRE/NAT --> MAC --> IPv4 */\n\tI40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),\n\tI40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),\n\tI40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(62),\n\tI40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),\n\tI40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),\n\tI40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),\n\n\t/* IPv4 --> GRE/NAT -> MAC --> IPv6 */\n\tI40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),\n\tI40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),\n\tI40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(69),\n\tI40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),\n\tI40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),\n\tI40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),\n\n\t/* IPv4 --> GRE/NAT --> MAC/VLAN */\n\tI40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),\n\n\t/* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */\n\tI40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),\n\tI40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),\n\tI40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(77),\n\tI40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),\n\tI40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),\n\tI40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),\n\n\t/* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */\n\tI40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),\n\tI40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),\n\tI40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(84),\n\tI40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),\n\tI40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),\n\tI40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),\n\n\t/* Non Tunneled IPv6 */\n\tI40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),\n\tI40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),\n\tI40E_PTT_UNUSED_ENTRY(91),\n\tI40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),\n\tI40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),\n\tI40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),\n\n\t/* IPv6 --> IPv4 */\n\tI40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),\n\tI40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),\n\tI40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(98),\n\tI40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),\n\tI40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),\n\tI40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),\n\n\t/* IPv6 --> IPv6 */\n\tI40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),\n\tI40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),\n\tI40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(105),\n\tI40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),\n\tI40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),\n\tI40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),\n\n\t/* IPv6 --> GRE/NAT */\n\tI40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),\n\n\t/* IPv6 --> GRE/NAT -> IPv4 */\n\tI40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),\n\tI40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),\n\tI40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(113),\n\tI40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),\n\tI40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),\n\tI40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),\n\n\t/* IPv6 --> GRE/NAT -> IPv6 */\n\tI40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),\n\tI40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),\n\tI40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(120),\n\tI40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),\n\tI40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),\n\tI40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),\n\n\t/* IPv6 --> GRE/NAT -> MAC */\n\tI40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),\n\n\t/* IPv6 --> GRE/NAT -> MAC -> IPv4 */\n\tI40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),\n\tI40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),\n\tI40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(128),\n\tI40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),\n\tI40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),\n\tI40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),\n\n\t/* IPv6 --> GRE/NAT -> MAC -> IPv6 */\n\tI40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),\n\tI40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),\n\tI40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(135),\n\tI40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),\n\tI40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),\n\tI40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),\n\n\t/* IPv6 --> GRE/NAT -> MAC/VLAN */\n\tI40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),\n\n\t/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */\n\tI40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),\n\tI40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),\n\tI40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(143),\n\tI40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),\n\tI40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),\n\tI40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),\n\n\t/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */\n\tI40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),\n\tI40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),\n\tI40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),\n\tI40E_PTT_UNUSED_ENTRY(150),\n\tI40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),\n\tI40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),\n\tI40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),\n\n\t/* unused entries */\n\tI40E_PTT_UNUSED_ENTRY(154),\n\tI40E_PTT_UNUSED_ENTRY(155),\n\tI40E_PTT_UNUSED_ENTRY(156),\n\tI40E_PTT_UNUSED_ENTRY(157),\n\tI40E_PTT_UNUSED_ENTRY(158),\n\tI40E_PTT_UNUSED_ENTRY(159),\n\n\tI40E_PTT_UNUSED_ENTRY(160),\n\tI40E_PTT_UNUSED_ENTRY(161),\n\tI40E_PTT_UNUSED_ENTRY(162),\n\tI40E_PTT_UNUSED_ENTRY(163),\n\tI40E_PTT_UNUSED_ENTRY(164),\n\tI40E_PTT_UNUSED_ENTRY(165),\n\tI40E_PTT_UNUSED_ENTRY(166),\n\tI40E_PTT_UNUSED_ENTRY(167),\n\tI40E_PTT_UNUSED_ENTRY(168),\n\tI40E_PTT_UNUSED_ENTRY(169),\n\n\tI40E_PTT_UNUSED_ENTRY(170),\n\tI40E_PTT_UNUSED_ENTRY(171),\n\tI40E_PTT_UNUSED_ENTRY(172),\n\tI40E_PTT_UNUSED_ENTRY(173),\n\tI40E_PTT_UNUSED_ENTRY(174),\n\tI40E_PTT_UNUSED_ENTRY(175),\n\tI40E_PTT_UNUSED_ENTRY(176),\n\tI40E_PTT_UNUSED_ENTRY(177),\n\tI40E_PTT_UNUSED_ENTRY(178),\n\tI40E_PTT_UNUSED_ENTRY(179),\n\n\tI40E_PTT_UNUSED_ENTRY(180),\n\tI40E_PTT_UNUSED_ENTRY(181),\n\tI40E_PTT_UNUSED_ENTRY(182),\n\tI40E_PTT_UNUSED_ENTRY(183),\n\tI40E_PTT_UNUSED_ENTRY(184),\n\tI40E_PTT_UNUSED_ENTRY(185),\n\tI40E_PTT_UNUSED_ENTRY(186),\n\tI40E_PTT_UNUSED_ENTRY(187),\n\tI40E_PTT_UNUSED_ENTRY(188),\n\tI40E_PTT_UNUSED_ENTRY(189),\n\n\tI40E_PTT_UNUSED_ENTRY(190),\n\tI40E_PTT_UNUSED_ENTRY(191),\n\tI40E_PTT_UNUSED_ENTRY(192),\n\tI40E_PTT_UNUSED_ENTRY(193),\n\tI40E_PTT_UNUSED_ENTRY(194),\n\tI40E_PTT_UNUSED_ENTRY(195),\n\tI40E_PTT_UNUSED_ENTRY(196),\n\tI40E_PTT_UNUSED_ENTRY(197),\n\tI40E_PTT_UNUSED_ENTRY(198),\n\tI40E_PTT_UNUSED_ENTRY(199),\n\n\tI40E_PTT_UNUSED_ENTRY(200),\n\tI40E_PTT_UNUSED_ENTRY(201),\n\tI40E_PTT_UNUSED_ENTRY(202),\n\tI40E_PTT_UNUSED_ENTRY(203),\n\tI40E_PTT_UNUSED_ENTRY(204),\n\tI40E_PTT_UNUSED_ENTRY(205),\n\tI40E_PTT_UNUSED_ENTRY(206),\n\tI40E_PTT_UNUSED_ENTRY(207),\n\tI40E_PTT_UNUSED_ENTRY(208),\n\tI40E_PTT_UNUSED_ENTRY(209),\n\n\tI40E_PTT_UNUSED_ENTRY(210),\n\tI40E_PTT_UNUSED_ENTRY(211),\n\tI40E_PTT_UNUSED_ENTRY(212),\n\tI40E_PTT_UNUSED_ENTRY(213),\n\tI40E_PTT_UNUSED_ENTRY(214),\n\tI40E_PTT_UNUSED_ENTRY(215),\n\tI40E_PTT_UNUSED_ENTRY(216),\n\tI40E_PTT_UNUSED_ENTRY(217),\n\tI40E_PTT_UNUSED_ENTRY(218),\n\tI40E_PTT_UNUSED_ENTRY(219),\n\n\tI40E_PTT_UNUSED_ENTRY(220),\n\tI40E_PTT_UNUSED_ENTRY(221),\n\tI40E_PTT_UNUSED_ENTRY(222),\n\tI40E_PTT_UNUSED_ENTRY(223),\n\tI40E_PTT_UNUSED_ENTRY(224),\n\tI40E_PTT_UNUSED_ENTRY(225),\n\tI40E_PTT_UNUSED_ENTRY(226),\n\tI40E_PTT_UNUSED_ENTRY(227),\n\tI40E_PTT_UNUSED_ENTRY(228),\n\tI40E_PTT_UNUSED_ENTRY(229),\n\n\tI40E_PTT_UNUSED_ENTRY(230),\n\tI40E_PTT_UNUSED_ENTRY(231),\n\tI40E_PTT_UNUSED_ENTRY(232),\n\tI40E_PTT_UNUSED_ENTRY(233),\n\tI40E_PTT_UNUSED_ENTRY(234),\n\tI40E_PTT_UNUSED_ENTRY(235),\n\tI40E_PTT_UNUSED_ENTRY(236),\n\tI40E_PTT_UNUSED_ENTRY(237),\n\tI40E_PTT_UNUSED_ENTRY(238),\n\tI40E_PTT_UNUSED_ENTRY(239),\n\n\tI40E_PTT_UNUSED_ENTRY(240),\n\tI40E_PTT_UNUSED_ENTRY(241),\n\tI40E_PTT_UNUSED_ENTRY(242),\n\tI40E_PTT_UNUSED_ENTRY(243),\n\tI40E_PTT_UNUSED_ENTRY(244),\n\tI40E_PTT_UNUSED_ENTRY(245),\n\tI40E_PTT_UNUSED_ENTRY(246),\n\tI40E_PTT_UNUSED_ENTRY(247),\n\tI40E_PTT_UNUSED_ENTRY(248),\n\tI40E_PTT_UNUSED_ENTRY(249),\n\n\tI40E_PTT_UNUSED_ENTRY(250),\n\tI40E_PTT_UNUSED_ENTRY(251),\n\tI40E_PTT_UNUSED_ENTRY(252),\n\tI40E_PTT_UNUSED_ENTRY(253),\n\tI40E_PTT_UNUSED_ENTRY(254),\n\tI40E_PTT_UNUSED_ENTRY(255)\n};\n\n\n/**\n * i40e_validate_mac_addr - Validate unicast MAC address\n * @mac_addr: pointer to MAC address\n *\n * Tests a MAC address to ensure it is a valid Individual Address\n **/\nenum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)\n{\n\tenum i40e_status_code status = I40E_SUCCESS;\n\n\tDEBUGFUNC(\"i40e_validate_mac_addr\");\n\n\t/* Broadcast addresses ARE multicast addresses\n\t * Make sure it is not a multicast address\n\t * Reject the zero address\n\t */\n\tif (I40E_IS_MULTICAST(mac_addr) ||\n\t (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&\n\t mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))\n\t\tstatus = I40E_ERR_INVALID_MAC_ADDR;\n\n\treturn status;\n}\n#ifdef PF_DRIVER\n\n/**\n * i40e_init_shared_code - Initialize the shared code\n * @hw: pointer to hardware structure\n *\n * This assigns the MAC type and PHY code and inits the NVM.\n * Does not touch the hardware. This function must be called prior to any\n * other function in the shared code. The i40e_hw structure should be\n * memset to 0 prior to calling this function. The following fields in\n * hw structure should be filled in prior to calling this function:\n * hw_addr, back, device_id, vendor_id, subsystem_device_id,\n * subsystem_vendor_id, and revision_id\n **/\nenum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)\n{\n\tenum i40e_status_code status = I40E_SUCCESS;\n\tu32 port, ari, func_rid;\n\n\tDEBUGFUNC(\"i40e_init_shared_code\");\n\n\ti40e_set_mac_type(hw);\n\n\tswitch (hw->mac.type) {\n\tcase I40E_MAC_XL710:\n\t\tbreak;\n\tdefault:\n\t\treturn I40E_ERR_DEVICE_NOT_SUPPORTED;\n\t}\n\n\thw->phy.get_link_info = true;\n\n\t/* Determine port number and PF number*/\n\tport = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)\n\t\t\t\t\t >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;\n\thw->port = (u8)port;\n\tari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>\n\t\t\t\t\t\t I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;\n\tfunc_rid = rd32(hw, I40E_PF_FUNC_RID);\n\tif (ari)\n\t\thw->pf_id = (u8)(func_rid & 0xff);\n\telse\n\t\thw->pf_id = (u8)(func_rid & 0x7);\n\n\tstatus = i40e_init_nvm(hw);\n\treturn status;\n}\n\n/**\n * i40e_aq_mac_address_read - Retrieve the MAC addresses\n * @hw: pointer to the hw struct\n * @flags: a return indicator of what addresses were added to the addr store\n * @addrs: the requestor's mac addr store\n * @cmd_details: pointer to command details structure or NULL\n **/\nSTATIC enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,\n\t\t\t\t u16 *flags,\n\t\t\t\t struct i40e_aqc_mac_address_read_data *addrs,\n\t\t\t\t struct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_mac_address_read *cmd_data =\n\t\t(struct i40e_aqc_mac_address_read *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);\n\tdesc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);\n\n\tstatus = i40e_asq_send_command(hw, &desc, addrs,\n\t\t\t\t sizeof(*addrs), cmd_details);\n\t*flags = LE16_TO_CPU(cmd_data->command_flags);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_mac_address_write - Change the MAC addresses\n * @hw: pointer to the hw struct\n * @flags: indicates which MAC to be written\n * @mac_addr: address to write\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,\n\t\t\t\t u16 flags, u8 *mac_addr,\n\t\t\t\t struct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_mac_address_write *cmd_data =\n\t\t(struct i40e_aqc_mac_address_write *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_mac_address_write);\n\tcmd_data->command_flags = CPU_TO_LE16(flags);\n\tcmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);\n\tcmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |\n\t\t\t\t\t((u32)mac_addr[3] << 16) |\n\t\t\t\t\t((u32)mac_addr[4] << 8) |\n\t\t\t\t\tmac_addr[5]);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_get_mac_addr - get MAC address\n * @hw: pointer to the HW structure\n * @mac_addr: pointer to MAC address\n *\n * Reads the adapter's MAC address from register\n **/\nenum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)\n{\n\tstruct i40e_aqc_mac_address_read_data addrs;\n\tenum i40e_status_code status;\n\tu16 flags = 0;\n\n\tstatus = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);\n\n\tif (flags & I40E_AQC_LAN_ADDR_VALID)\n\t\tmemcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));\n\n\treturn status;\n}\n\n/**\n * i40e_get_port_mac_addr - get Port MAC address\n * @hw: pointer to the HW structure\n * @mac_addr: pointer to Port MAC address\n *\n * Reads the adapter's Port MAC address\n **/\nenum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)\n{\n\tstruct i40e_aqc_mac_address_read_data addrs;\n\tenum i40e_status_code status;\n\tu16 flags = 0;\n\n\tstatus = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);\n\tif (status)\n\t\treturn status;\n\n\tif (flags & I40E_AQC_PORT_ADDR_VALID)\n\t\tmemcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac));\n\telse\n\t\tstatus = I40E_ERR_INVALID_MAC_ADDR;\n\n\treturn status;\n}\n\n/**\n * i40e_pre_tx_queue_cfg - pre tx queue configure\n * @hw: pointer to the HW structure\n * @queue: target pf queue index\n * @enable: state change request\n *\n * Handles hw requirement to indicate intention to enable\n * or disable target queue.\n **/\nvoid i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)\n{\n\tu32 abs_queue_idx = hw->func_caps.base_queue + queue;\n\tu32 reg_block = 0;\n\tu32 reg_val;\n\n\tif (abs_queue_idx >= 128) {\n\t\treg_block = abs_queue_idx / 128;\n\t\tabs_queue_idx %= 128;\n\t}\n\n\treg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));\n\treg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;\n\treg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);\n\n\tif (enable)\n\t\treg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;\n\telse\n\t\treg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;\n\n\twr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);\n}\n\n/**\n * i40e_read_pba_string - Reads part number string from EEPROM\n * @hw: pointer to hardware structure\n * @pba_num: stores the part number string from the EEPROM\n * @pba_num_size: part number string buffer length\n *\n * Reads the part number string from the EEPROM.\n **/\nenum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,\n\t\t\t\t\t u32 pba_num_size)\n{\n\tenum i40e_status_code status = I40E_SUCCESS;\n\tu16 pba_word = 0;\n\tu16 pba_size = 0;\n\tu16 pba_ptr = 0;\n\tu16 i = 0;\n\n\tstatus = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);\n\tif ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {\n\t\tDEBUGOUT(\"Failed to read PBA flags or flag is invalid.\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);\n\tif (status != I40E_SUCCESS) {\n\t\tDEBUGOUT(\"Failed to read PBA Block pointer.\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = i40e_read_nvm_word(hw, pba_ptr, &pba_size);\n\tif (status != I40E_SUCCESS) {\n\t\tDEBUGOUT(\"Failed to read PBA Block size.\\n\");\n\t\treturn status;\n\t}\n\n\t/* Subtract one to get PBA word count (PBA Size word is included in\n\t * total size)\n\t */\n\tpba_size--;\n\tif (pba_num_size < (((u32)pba_size * 2) + 1)) {\n\t\tDEBUGOUT(\"Buffer to small for PBA data.\\n\");\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\tfor (i = 0; i < pba_size; i++) {\n\t\tstatus = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);\n\t\tif (status != I40E_SUCCESS) {\n\t\t\tDEBUGOUT1(\"Failed to read PBA Block word %d.\\n\", i);\n\t\t\treturn status;\n\t\t}\n\n\t\tpba_num[(i * 2)] = (pba_word >> 8) & 0xFF;\n\t\tpba_num[(i * 2) + 1] = pba_word & 0xFF;\n\t}\n\tpba_num[(pba_size * 2)] = '\\0';\n\n\treturn status;\n}\n\n/**\n * i40e_get_media_type - Gets media type\n * @hw: pointer to the hardware structure\n **/\nSTATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)\n{\n\tenum i40e_media_type media;\n\n\tswitch (hw->phy.link_info.phy_type) {\n\tcase I40E_PHY_TYPE_10GBASE_SR:\n\tcase I40E_PHY_TYPE_10GBASE_LR:\n\tcase I40E_PHY_TYPE_1000BASE_SX:\n\tcase I40E_PHY_TYPE_1000BASE_LX:\n\tcase I40E_PHY_TYPE_40GBASE_SR4:\n\tcase I40E_PHY_TYPE_40GBASE_LR4:\n\t\tmedia = I40E_MEDIA_TYPE_FIBER;\n\t\tbreak;\n\tcase I40E_PHY_TYPE_100BASE_TX:\n\tcase I40E_PHY_TYPE_1000BASE_T:\n\tcase I40E_PHY_TYPE_10GBASE_T:\n\t\tmedia = I40E_MEDIA_TYPE_BASET;\n\t\tbreak;\n\tcase I40E_PHY_TYPE_10GBASE_CR1_CU:\n\tcase I40E_PHY_TYPE_40GBASE_CR4_CU:\n\tcase I40E_PHY_TYPE_10GBASE_CR1:\n\tcase I40E_PHY_TYPE_40GBASE_CR4:\n\tcase I40E_PHY_TYPE_10GBASE_SFPP_CU:\n\tcase I40E_PHY_TYPE_40GBASE_AOC:\n\tcase I40E_PHY_TYPE_10GBASE_AOC:\n\t\tmedia = I40E_MEDIA_TYPE_DA;\n\t\tbreak;\n\tcase I40E_PHY_TYPE_1000BASE_KX:\n\tcase I40E_PHY_TYPE_10GBASE_KX4:\n\tcase I40E_PHY_TYPE_10GBASE_KR:\n\tcase I40E_PHY_TYPE_40GBASE_KR4:\n\t\tmedia = I40E_MEDIA_TYPE_BACKPLANE;\n\t\tbreak;\n\tcase I40E_PHY_TYPE_SGMII:\n\tcase I40E_PHY_TYPE_XAUI:\n\tcase I40E_PHY_TYPE_XFI:\n\tcase I40E_PHY_TYPE_XLAUI:\n\tcase I40E_PHY_TYPE_XLPPI:\n\tdefault:\n\t\tmedia = I40E_MEDIA_TYPE_UNKNOWN;\n\t\tbreak;\n\t}\n\n\treturn media;\n}\n\n#define I40E_PF_RESET_WAIT_COUNT\t110\n/**\n * i40e_pf_reset - Reset the PF\n * @hw: pointer to the hardware structure\n *\n * Assuming someone else has triggered a global reset,\n * assure the global reset is complete and then reset the PF\n **/\nenum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)\n{\n\tu32 cnt = 0;\n\tu32 cnt1 = 0;\n\tu32 reg = 0;\n\tu32 grst_del;\n\n\t/* Poll for Global Reset steady state in case of recent GRST.\n\t * The grst delay value is in 100ms units, and we'll wait a\n\t * couple counts longer to be sure we don't just miss the end.\n\t */\n\tgrst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &\n\t\t\tI40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>\n\t\t\tI40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;\n\tfor (cnt = 0; cnt < grst_del + 2; cnt++) {\n\t\treg = rd32(hw, I40E_GLGEN_RSTAT);\n\t\tif (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))\n\t\t\tbreak;\n\t\ti40e_msec_delay(100);\n\t}\n\tif (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {\n\t\tDEBUGOUT(\"Global reset polling failed to complete.\\n\");\n\t\treturn I40E_ERR_RESET_FAILED;\n\t}\n\n\t/* Now Wait for the FW to be ready */\n\tfor (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {\n\t\treg = rd32(hw, I40E_GLNVM_ULD);\n\t\treg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |\n\t\t\tI40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);\n\t\tif (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |\n\t\t\t I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {\n\t\t\tDEBUGOUT1(\"Core and Global modules ready %d\\n\", cnt1);\n\t\t\tbreak;\n\t\t}\n\t\ti40e_msec_delay(10);\n\t}\n\tif (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |\n\t\t I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {\n\t\tDEBUGOUT(\"wait for FW Reset complete timedout\\n\");\n\t\tDEBUGOUT1(\"I40E_GLNVM_ULD = 0x%x\\n\", reg);\n\t\treturn I40E_ERR_RESET_FAILED;\n\t}\n\n\t/* If there was a Global Reset in progress when we got here,\n\t * we don't need to do the PF Reset\n\t */\n\tif (!cnt) {\n\t\treg = rd32(hw, I40E_PFGEN_CTRL);\n\t\twr32(hw, I40E_PFGEN_CTRL,\n\t\t (reg | I40E_PFGEN_CTRL_PFSWR_MASK));\n\t\tfor (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {\n\t\t\treg = rd32(hw, I40E_PFGEN_CTRL);\n\t\t\tif (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))\n\t\t\t\tbreak;\n\t\t\ti40e_msec_delay(1);\n\t\t}\n\t\tif (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {\n\t\t\tDEBUGOUT(\"PF reset polling failed to complete.\\n\");\n\t\t\treturn I40E_ERR_RESET_FAILED;\n\t\t}\n\t}\n\n\ti40e_clear_pxe_mode(hw);\n\n\n\treturn I40E_SUCCESS;\n}\n\n/**\n * i40e_clear_hw - clear out any left over hw state\n * @hw: pointer to the hw struct\n *\n * Clear queues and interrupts, typically called at init time,\n * but after the capabilities have been found so we know how many\n * queues and msix vectors have been allocated.\n **/\nvoid i40e_clear_hw(struct i40e_hw *hw)\n{\n\tu32 num_queues, base_queue;\n\tu32 num_pf_int;\n\tu32 num_vf_int;\n\tu32 num_vfs;\n\tu32 i, j;\n\tu32 val;\n\tu32 eol = 0x7ff;\n\n\t/* get number of interrupts, queues, and vfs */\n\tval = rd32(hw, I40E_GLPCI_CNF2);\n\tnum_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>\n\t\t\tI40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;\n\tnum_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>\n\t\t\tI40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;\n\n\tval = rd32(hw, I40E_PFLAN_QALLOC);\n\tbase_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>\n\t\t\tI40E_PFLAN_QALLOC_FIRSTQ_SHIFT;\n\tj = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>\n\t\t\tI40E_PFLAN_QALLOC_LASTQ_SHIFT;\n\tif (val & I40E_PFLAN_QALLOC_VALID_MASK)\n\t\tnum_queues = (j - base_queue) + 1;\n\telse\n\t\tnum_queues = 0;\n\n\tval = rd32(hw, I40E_PF_VT_PFALLOC);\n\ti = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>\n\t\t\tI40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;\n\tj = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>\n\t\t\tI40E_PF_VT_PFALLOC_LASTVF_SHIFT;\n\tif (val & I40E_PF_VT_PFALLOC_VALID_MASK)\n\t\tnum_vfs = (j - i) + 1;\n\telse\n\t\tnum_vfs = 0;\n\n\t/* stop all the interrupts */\n\twr32(hw, I40E_PFINT_ICR0_ENA, 0);\n\tval = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;\n\tfor (i = 0; i < num_pf_int - 2; i++)\n\t\twr32(hw, I40E_PFINT_DYN_CTLN(i), val);\n\n\t/* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */\n\tval = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;\n\twr32(hw, I40E_PFINT_LNKLST0, val);\n\tfor (i = 0; i < num_pf_int - 2; i++)\n\t\twr32(hw, I40E_PFINT_LNKLSTN(i), val);\n\tval = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;\n\tfor (i = 0; i < num_vfs; i++)\n\t\twr32(hw, I40E_VPINT_LNKLST0(i), val);\n\tfor (i = 0; i < num_vf_int - 2; i++)\n\t\twr32(hw, I40E_VPINT_LNKLSTN(i), val);\n\n\t/* warn the HW of the coming Tx disables */\n\tfor (i = 0; i < num_queues; i++) {\n\t\tu32 abs_queue_idx = base_queue + i;\n\t\tu32 reg_block = 0;\n\n\t\tif (abs_queue_idx >= 128) {\n\t\t\treg_block = abs_queue_idx / 128;\n\t\t\tabs_queue_idx %= 128;\n\t\t}\n\n\t\tval = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));\n\t\tval &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;\n\t\tval |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);\n\t\tval |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;\n\n\t\twr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);\n\t}\n\ti40e_usec_delay(400);\n\n\t/* stop all the queues */\n\tfor (i = 0; i < num_queues; i++) {\n\t\twr32(hw, I40E_QINT_TQCTL(i), 0);\n\t\twr32(hw, I40E_QTX_ENA(i), 0);\n\t\twr32(hw, I40E_QINT_RQCTL(i), 0);\n\t\twr32(hw, I40E_QRX_ENA(i), 0);\n\t}\n\n\t/* short wait for all queue disables to settle */\n\ti40e_usec_delay(50);\n}\n\n/**\n * i40e_clear_pxe_mode - clear pxe operations mode\n * @hw: pointer to the hw struct\n *\n * Make sure all PXE mode settings are cleared, including things\n * like descriptor fetch/write-back mode.\n **/\nvoid i40e_clear_pxe_mode(struct i40e_hw *hw)\n{\n\tif (i40e_check_asq_alive(hw))\n\t\ti40e_aq_clear_pxe_mode(hw, NULL);\n}\n\n/**\n * i40e_led_is_mine - helper to find matching led\n * @hw: pointer to the hw struct\n * @idx: index into GPIO registers\n *\n * returns: 0 if no match, otherwise the value of the GPIO_CTL register\n */\nstatic u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)\n{\n\tu32 gpio_val = 0;\n\tu32 port;\n\n\tif (!hw->func_caps.led[idx])\n\t\treturn 0;\n\n\tgpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));\n\tport = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>\n\t\tI40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;\n\n\t/* if PRT_NUM_NA is 1 then this LED is not port specific, OR\n\t * if it is not our port then ignore\n\t */\n\tif ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||\n\t (port != hw->port))\n\t\treturn 0;\n\n\treturn gpio_val;\n}\n\n#define I40E_COMBINED_ACTIVITY 0xA\n#define I40E_FILTER_ACTIVITY 0xE\n#define I40E_LINK_ACTIVITY 0xC\n#define I40E_MAC_ACTIVITY 0xD\n#define I40E_LED0 22\n\n/**\n * i40e_led_get - return current on/off mode\n * @hw: pointer to the hw struct\n *\n * The value returned is the 'mode' field as defined in the\n * GPIO register definitions: 0x0 = off, 0xf = on, and other\n * values are variations of possible behaviors relating to\n * blink, link, and wire.\n **/\nu32 i40e_led_get(struct i40e_hw *hw)\n{\n\tu32 current_mode = 0;\n\tu32 mode = 0;\n\tint i;\n\n\t/* as per the documentation GPIO 22-29 are the LED\n\t * GPIO pins named LED0..LED7\n\t */\n\tfor (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {\n\t\tu32 gpio_val = i40e_led_is_mine(hw, i);\n\n\t\tif (!gpio_val)\n\t\t\tcontinue;\n\n\t\t/* ignore gpio LED src mode entries related to the activity LEDs */\n\t\tcurrent_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>\n\t\t\tI40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);\n\t\tswitch (current_mode) {\n\t\tcase I40E_COMBINED_ACTIVITY:\n\t\tcase I40E_FILTER_ACTIVITY:\n\t\tcase I40E_MAC_ACTIVITY:\n\t\t\tcontinue;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tmode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>\n\t\t\tI40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;\n\t\tbreak;\n\t}\n\n\treturn mode;\n}\n\n/**\n * i40e_led_set - set new on/off mode\n * @hw: pointer to the hw struct\n * @mode: 0=off, 0xf=on (else see manual for mode details)\n * @blink: true if the LED should blink when on, false if steady\n *\n * if this function is used to turn on the blink it should\n * be used to disable the blink when restoring the original state.\n **/\nvoid i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)\n{\n\tu32 current_mode = 0;\n\tint i;\n\n\tif (mode & 0xfffffff0)\n\t\tDEBUGOUT1(\"invalid mode passed in %X\\n\", mode);\n\n\t/* as per the documentation GPIO 22-29 are the LED\n\t * GPIO pins named LED0..LED7\n\t */\n\tfor (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {\n\t\tu32 gpio_val = i40e_led_is_mine(hw, i);\n\n\t\tif (!gpio_val)\n\t\t\tcontinue;\n\n\t\t/* ignore gpio LED src mode entries related to the activity LEDs */\n\t\tcurrent_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>\n\t\t\tI40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);\n\t\tswitch (current_mode) {\n\t\tcase I40E_COMBINED_ACTIVITY:\n\t\tcase I40E_FILTER_ACTIVITY:\n\t\tcase I40E_MAC_ACTIVITY:\n\t\t\tcontinue;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tgpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;\n\t\t/* this & is a bit of paranoia, but serves as a range check */\n\t\tgpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &\n\t\t\t I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);\n\n\t\tif (mode == I40E_LINK_ACTIVITY)\n\t\t\tblink = false;\n\n\t\tif (blink)\n\t\t\tgpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);\n\t\telse\n\t\t\tgpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);\n\n\t\twr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);\n\t\tbreak;\n\t}\n}\n\n/* Admin command wrappers */\n\n/**\n * i40e_aq_get_phy_capabilities\n * @hw: pointer to the hw struct\n * @abilities: structure for PHY capabilities to be filled\n * @qualified_modules: report Qualified Modules\n * @report_init: report init capabilities (active are default)\n * @cmd_details: pointer to command details structure or NULL\n *\n * Returns the various PHY abilities supported on the Port.\n **/\nenum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,\n\t\t\tbool qualified_modules, bool report_init,\n\t\t\tstruct i40e_aq_get_phy_abilities_resp *abilities,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tenum i40e_status_code status;\n\tu16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);\n\n\tif (!abilities)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_get_phy_abilities);\n\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);\n\tif (abilities_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tif (qualified_modules)\n\t\tdesc.params.external.param0 |=\n\t\t\tCPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);\n\n\tif (report_init)\n\t\tdesc.params.external.param0 |=\n\t\t\tCPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);\n\n\tstatus = i40e_asq_send_command(hw, &desc, abilities, abilities_size,\n\t\t\t\t cmd_details);\n\n\tif (hw->aq.asq_last_status == I40E_AQ_RC_EIO)\n\t\tstatus = I40E_ERR_UNKNOWN_PHY;\n\n\treturn status;\n}\n\n/**\n * i40e_aq_set_phy_config\n * @hw: pointer to the hw struct\n * @config: structure with PHY configuration to be set\n * @cmd_details: pointer to command details structure or NULL\n *\n * Set the various PHY configuration parameters\n * supported on the Port.One or more of the Set PHY config parameters may be\n * ignored in an MFP mode as the PF may not have the privilege to set some\n * of the PHY Config parameters. This status will be indicated by the\n * command response.\n **/\nenum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_aq_set_phy_config *config,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aq_set_phy_config *cmd =\n\t\t(struct i40e_aq_set_phy_config *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (!config)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_set_phy_config);\n\n\t*cmd = *config;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_set_fc\n * @hw: pointer to the hw struct\n *\n * Set the requested flow control mode using set_phy_config.\n **/\nenum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,\n\t\t\t\t bool atomic_restart)\n{\n\tenum i40e_fc_mode fc_mode = hw->fc.requested_mode;\n\tstruct i40e_aq_get_phy_abilities_resp abilities;\n\tstruct i40e_aq_set_phy_config config;\n\tenum i40e_status_code status;\n\tu8 pause_mask = 0x0;\n\n\t*aq_failures = 0x0;\n\n\tswitch (fc_mode) {\n\tcase I40E_FC_FULL:\n\t\tpause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;\n\t\tpause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;\n\t\tbreak;\n\tcase I40E_FC_RX_PAUSE:\n\t\tpause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;\n\t\tbreak;\n\tcase I40E_FC_TX_PAUSE:\n\t\tpause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Get the current phy config */\n\tstatus = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,\n\t\t\t\t\t NULL);\n\tif (status) {\n\t\t*aq_failures |= I40E_SET_FC_AQ_FAIL_GET;\n\t\treturn status;\n\t}\n\n\tmemset(&config, 0, sizeof(config));\n\t/* clear the old pause settings */\n\tconfig.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &\n\t\t\t ~(I40E_AQ_PHY_FLAG_PAUSE_RX);\n\t/* set the new abilities */\n\tconfig.abilities |= pause_mask;\n\t/* If the abilities have changed, then set the new config */\n\tif (config.abilities != abilities.abilities) {\n\t\t/* Auto restart link so settings take effect */\n\t\tif (atomic_restart)\n\t\t\tconfig.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;\n\t\t/* Copy over all the old settings */\n\t\tconfig.phy_type = abilities.phy_type;\n\t\tconfig.link_speed = abilities.link_speed;\n\t\tconfig.eee_capability = abilities.eee_capability;\n\t\tconfig.eeer = abilities.eeer_val;\n\t\tconfig.low_power_ctrl = abilities.d3_lpan;\n\t\tstatus = i40e_aq_set_phy_config(hw, &config, NULL);\n\n\t\tif (status)\n\t\t\t*aq_failures |= I40E_SET_FC_AQ_FAIL_SET;\n\t}\n\t/* Update the link info */\n\tstatus = i40e_aq_get_link_info(hw, true, NULL, NULL);\n\tif (status) {\n\t\t/* Wait a little bit (on 40G cards it sometimes takes a really\n\t\t * long time for link to come back from the atomic reset)\n\t\t * and try once more\n\t\t */\n\t\ti40e_msec_delay(1000);\n\t\tstatus = i40e_aq_get_link_info(hw, true, NULL, NULL);\n\t}\n\tif (status)\n\t\t*aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;\n\n\treturn status;\n}\n\n/**\n * i40e_aq_set_mac_config\n * @hw: pointer to the hw struct\n * @max_frame_size: Maximum Frame Size to be supported by the port\n * @crc_en: Tell HW to append a CRC to outgoing frames\n * @pacing: Pacing configurations\n * @cmd_details: pointer to command details structure or NULL\n *\n * Configure MAC settings for frame size, jumbo frame support and the\n * addition of a CRC by the hardware.\n **/\nenum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,\n\t\t\t\tu16 max_frame_size,\n\t\t\t\tbool crc_en, u16 pacing,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aq_set_mac_config *cmd =\n\t\t(struct i40e_aq_set_mac_config *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (max_frame_size == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_set_mac_config);\n\n\tcmd->max_frame_size = CPU_TO_LE16(max_frame_size);\n\tcmd->params = ((u8)pacing & 0x0F) << 3;\n\tif (crc_en)\n\t\tcmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_clear_pxe_mode\n * @hw: pointer to the hw struct\n * @cmd_details: pointer to command details structure or NULL\n *\n * Tell the firmware that the driver is taking over from PXE\n **/\nenum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tenum i40e_status_code status;\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_clear_pxe *cmd =\n\t\t(struct i40e_aqc_clear_pxe *)&desc.params.raw;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_clear_pxe_mode);\n\n\tcmd->rx_cnt = 0x2;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\twr32(hw, I40E_GLLAN_RCTL_0, 0x1);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_set_link_restart_an\n * @hw: pointer to the hw struct\n * @enable_link: if true: enable link, if false: disable link\n * @cmd_details: pointer to command details structure or NULL\n *\n * Sets up the link and restarts the Auto-Negotiation over the link.\n **/\nenum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,\n\t\tbool enable_link, struct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_set_link_restart_an *cmd =\n\t\t(struct i40e_aqc_set_link_restart_an *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_set_link_restart_an);\n\n\tcmd->command = I40E_AQ_PHY_RESTART_AN;\n\tif (enable_link)\n\t\tcmd->command |= I40E_AQ_PHY_LINK_ENABLE;\n\telse\n\t\tcmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_get_link_info\n * @hw: pointer to the hw struct\n * @enable_lse: enable/disable LinkStatusEvent reporting\n * @link: pointer to link status structure - optional\n * @cmd_details: pointer to command details structure or NULL\n *\n * Returns the link status of the adapter.\n **/\nenum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,\n\t\t\t\tbool enable_lse, struct i40e_link_status *link,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_get_link_status *resp =\n\t\t(struct i40e_aqc_get_link_status *)&desc.params.raw;\n\tstruct i40e_link_status *hw_link_info = &hw->phy.link_info;\n\tenum i40e_status_code status;\n\tbool tx_pause, rx_pause;\n\tu16 command_flags;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);\n\n\tif (enable_lse)\n\t\tcommand_flags = I40E_AQ_LSE_ENABLE;\n\telse\n\t\tcommand_flags = I40E_AQ_LSE_DISABLE;\n\tresp->command_flags = CPU_TO_LE16(command_flags);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (status != I40E_SUCCESS)\n\t\tgoto aq_get_link_info_exit;\n\n\t/* save off old link status information */\n\ti40e_memcpy(&hw->phy.link_info_old, hw_link_info,\n\t\t sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);\n\n\t/* update link status */\n\thw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;\n\thw->phy.media_type = i40e_get_media_type(hw);\n\thw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;\n\thw_link_info->link_info = resp->link_info;\n\thw_link_info->an_info = resp->an_info;\n\thw_link_info->ext_info = resp->ext_info;\n\thw_link_info->loopback = resp->loopback;\n\thw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);\n\thw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;\n\n\t/* update fc info */\n\ttx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);\n\trx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);\n\tif (tx_pause & rx_pause)\n\t\thw->fc.current_mode = I40E_FC_FULL;\n\telse if (tx_pause)\n\t\thw->fc.current_mode = I40E_FC_TX_PAUSE;\n\telse if (rx_pause)\n\t\thw->fc.current_mode = I40E_FC_RX_PAUSE;\n\telse\n\t\thw->fc.current_mode = I40E_FC_NONE;\n\n\tif (resp->config & I40E_AQ_CONFIG_CRC_ENA)\n\t\thw_link_info->crc_enable = true;\n\telse\n\t\thw_link_info->crc_enable = false;\n\n\tif (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_ENABLE))\n\t\thw_link_info->lse_enable = true;\n\telse\n\t\thw_link_info->lse_enable = false;\n\n\tif ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&\n\t hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)\n\t\thw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;\n\n\t/* save link status information */\n\tif (link)\n\t\ti40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),\n\t\t\t I40E_NONDMA_TO_NONDMA);\n\n\t/* flag cleared so helper functions don't call AQ again */\n\thw->phy.get_link_info = false;\n\naq_get_link_info_exit:\n\treturn status;\n}\n\n\n/**\n * i40e_aq_set_phy_int_mask\n * @hw: pointer to the hw struct\n * @mask: interrupt mask to be set\n * @cmd_details: pointer to command details structure or NULL\n *\n * Set link interrupt mask.\n **/\nenum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,\n\t\t\t\tu16 mask,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_set_phy_int_mask *cmd =\n\t\t(struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_set_phy_int_mask);\n\n\tcmd->event_mask = CPU_TO_LE16(mask);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_get_local_advt_reg\n * @hw: pointer to the hw struct\n * @advt_reg: local AN advertisement register value\n * @cmd_details: pointer to command details structure or NULL\n *\n * Get the Local AN advertisement register value.\n **/\nenum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,\n\t\t\t\tu64 *advt_reg,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_an_advt_reg *resp =\n\t\t(struct i40e_aqc_an_advt_reg *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_get_local_advt_reg);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (status != I40E_SUCCESS)\n\t\tgoto aq_get_local_advt_reg_exit;\n\n\t*advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;\n\t*advt_reg |= LE32_TO_CPU(resp->local_an_reg0);\n\naq_get_local_advt_reg_exit:\n\treturn status;\n}\n\n/**\n * i40e_aq_set_local_advt_reg\n * @hw: pointer to the hw struct\n * @advt_reg: local AN advertisement register value\n * @cmd_details: pointer to command details structure or NULL\n *\n * Get the Local AN advertisement register value.\n **/\nenum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,\n\t\t\t\tu64 advt_reg,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_an_advt_reg *cmd =\n\t\t(struct i40e_aqc_an_advt_reg *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_get_local_advt_reg);\n\n\tcmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));\n\tcmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_get_partner_advt\n * @hw: pointer to the hw struct\n * @advt_reg: AN partner advertisement register value\n * @cmd_details: pointer to command details structure or NULL\n *\n * Get the link partner AN advertisement register value.\n **/\nenum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,\n\t\t\t\tu64 *advt_reg,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_an_advt_reg *resp =\n\t\t(struct i40e_aqc_an_advt_reg *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_get_partner_advt);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (status != I40E_SUCCESS)\n\t\tgoto aq_get_partner_advt_exit;\n\n\t*advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;\n\t*advt_reg |= LE32_TO_CPU(resp->local_an_reg0);\n\naq_get_partner_advt_exit:\n\treturn status;\n}\n\n/**\n * i40e_aq_set_lb_modes\n * @hw: pointer to the hw struct\n * @lb_modes: loopback mode to be set\n * @cmd_details: pointer to command details structure or NULL\n *\n * Sets loopback modes.\n **/\nenum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw,\n\t\t\t\tu16 lb_modes,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_set_lb_mode *cmd =\n\t\t(struct i40e_aqc_set_lb_mode *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_set_lb_modes);\n\n\tcmd->lb_mode = CPU_TO_LE16(lb_modes);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_set_phy_debug\n * @hw: pointer to the hw struct\n * @cmd_flags: debug command flags\n * @cmd_details: pointer to command details structure or NULL\n *\n * Reset the external PHY.\n **/\nenum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_set_phy_debug *cmd =\n\t\t(struct i40e_aqc_set_phy_debug *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_set_phy_debug);\n\n\tcmd->command_flags = cmd_flags;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_add_vsi\n * @hw: pointer to the hw struct\n * @vsi_ctx: pointer to a vsi context struct\n * @cmd_details: pointer to command details structure or NULL\n *\n * Add a VSI context to the hardware.\n**/\nenum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_vsi_context *vsi_ctx,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_get_update_vsi *cmd =\n\t\t(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;\n\tstruct i40e_aqc_add_get_update_vsi_completion *resp =\n\t\t(struct i40e_aqc_add_get_update_vsi_completion *)\n\t\t&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_add_vsi);\n\n\tcmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);\n\tcmd->connection_type = vsi_ctx->connection_type;\n\tcmd->vf_id = vsi_ctx->vf_num;\n\tcmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);\n\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\n\tstatus = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,\n\t\t\t\t sizeof(vsi_ctx->info), cmd_details);\n\n\tif (status != I40E_SUCCESS)\n\t\tgoto aq_add_vsi_exit;\n\n\tvsi_ctx->seid = LE16_TO_CPU(resp->seid);\n\tvsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);\n\tvsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);\n\tvsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);\n\naq_add_vsi_exit:\n\treturn status;\n}\n\n/**\n * i40e_aq_set_default_vsi\n * @hw: pointer to the hw struct\n * @seid: vsi number\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,\n\t\t\t\tu16 seid,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_set_vsi_promiscuous_modes *cmd =\n\t\t(struct i40e_aqc_set_vsi_promiscuous_modes *)\n\t\t&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\ti40e_aqc_opc_set_vsi_promiscuous_modes);\n\n\tcmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);\n\tcmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);\n\tcmd->seid = CPU_TO_LE16(seid);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_set_vsi_unicast_promiscuous\n * @hw: pointer to the hw struct\n * @seid: vsi number\n * @set: set unicast promiscuous enable/disable\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,\n\t\t\t\tu16 seid, bool set,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_set_vsi_promiscuous_modes *cmd =\n\t\t(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;\n\tenum i40e_status_code status;\n\tu16 flags = 0;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\ti40e_aqc_opc_set_vsi_promiscuous_modes);\n\n\tif (set)\n\t\tflags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;\n\n\tcmd->promiscuous_flags = CPU_TO_LE16(flags);\n\n\tcmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);\n\n\tcmd->seid = CPU_TO_LE16(seid);\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_set_vsi_multicast_promiscuous\n * @hw: pointer to the hw struct\n * @seid: vsi number\n * @set: set multicast promiscuous enable/disable\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,\n\t\t\t\tu16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_set_vsi_promiscuous_modes *cmd =\n\t\t(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;\n\tenum i40e_status_code status;\n\tu16 flags = 0;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\ti40e_aqc_opc_set_vsi_promiscuous_modes);\n\n\tif (set)\n\t\tflags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;\n\n\tcmd->promiscuous_flags = CPU_TO_LE16(flags);\n\n\tcmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);\n\n\tcmd->seid = CPU_TO_LE16(seid);\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_set_vsi_broadcast\n * @hw: pointer to the hw struct\n * @seid: vsi number\n * @set_filter: true to set filter, false to clear filter\n * @cmd_details: pointer to command details structure or NULL\n *\n * Set or clear the broadcast promiscuous flag (filter) for a given VSI.\n **/\nenum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,\n\t\t\t\tu16 seid, bool set_filter,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_set_vsi_promiscuous_modes *cmd =\n\t\t(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\ti40e_aqc_opc_set_vsi_promiscuous_modes);\n\n\tif (set_filter)\n\t\tcmd->promiscuous_flags\n\t\t\t |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);\n\telse\n\t\tcmd->promiscuous_flags\n\t\t\t &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);\n\n\tcmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);\n\tcmd->seid = CPU_TO_LE16(seid);\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_get_vsi_params - get VSI configuration info\n * @hw: pointer to the hw struct\n * @vsi_ctx: pointer to a vsi context struct\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_vsi_context *vsi_ctx,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_get_update_vsi *cmd =\n\t\t(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;\n\tstruct i40e_aqc_add_get_update_vsi_completion *resp =\n\t\t(struct i40e_aqc_add_get_update_vsi_completion *)\n\t\t&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tUNREFERENCED_1PARAMETER(cmd_details);\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_get_vsi_parameters);\n\n\tcmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);\n\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);\n\n\tstatus = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,\n\t\t\t\t sizeof(vsi_ctx->info), NULL);\n\n\tif (status != I40E_SUCCESS)\n\t\tgoto aq_get_vsi_params_exit;\n\n\tvsi_ctx->seid = LE16_TO_CPU(resp->seid);\n\tvsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);\n\tvsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);\n\tvsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);\n\naq_get_vsi_params_exit:\n\treturn status;\n}\n\n/**\n * i40e_aq_update_vsi_params\n * @hw: pointer to the hw struct\n * @vsi_ctx: pointer to a vsi context struct\n * @cmd_details: pointer to command details structure or NULL\n *\n * Update a VSI context.\n **/\nenum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_vsi_context *vsi_ctx,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_get_update_vsi *cmd =\n\t\t(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_update_vsi_parameters);\n\tcmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);\n\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\n\tstatus = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,\n\t\t\t\t sizeof(vsi_ctx->info), cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_get_switch_config\n * @hw: pointer to the hardware structure\n * @buf: pointer to the result buffer\n * @buf_size: length of input buffer\n * @start_seid: seid to start for the report, 0 == beginning\n * @cmd_details: pointer to command details structure or NULL\n *\n * Fill the buf with switch configuration returned from AdminQ command\n **/\nenum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_aqc_get_switch_config_resp *buf,\n\t\t\t\tu16 buf_size, u16 *start_seid,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_switch_seid *scfg =\n\t\t(struct i40e_aqc_switch_seid *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_get_switch_config);\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);\n\tif (buf_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\tscfg->seid = CPU_TO_LE16(*start_seid);\n\n\tstatus = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);\n\t*start_seid = LE16_TO_CPU(scfg->seid);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_get_firmware_version\n * @hw: pointer to the hw struct\n * @fw_major_version: firmware major version\n * @fw_minor_version: firmware minor version\n * @fw_build: firmware build number\n * @api_major_version: major queue version\n * @api_minor_version: minor queue version\n * @cmd_details: pointer to command details structure or NULL\n *\n * Get the firmware version from the admin queue commands\n **/\nenum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,\n\t\t\t\tu16 *fw_major_version, u16 *fw_minor_version,\n\t\t\t\tu32 *fw_build,\n\t\t\t\tu16 *api_major_version, u16 *api_minor_version,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_get_version *resp =\n\t\t(struct i40e_aqc_get_version *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (status == I40E_SUCCESS) {\n\t\tif (fw_major_version != NULL)\n\t\t\t*fw_major_version = LE16_TO_CPU(resp->fw_major);\n\t\tif (fw_minor_version != NULL)\n\t\t\t*fw_minor_version = LE16_TO_CPU(resp->fw_minor);\n\t\tif (fw_build != NULL)\n\t\t\t*fw_build = LE32_TO_CPU(resp->fw_build);\n\t\tif (api_major_version != NULL)\n\t\t\t*api_major_version = LE16_TO_CPU(resp->api_major);\n\t\tif (api_minor_version != NULL)\n\t\t\t*api_minor_version = LE16_TO_CPU(resp->api_minor);\n\n\t\t/* A workaround to fix the API version in SW */\n\t\tif (api_major_version && api_minor_version &&\n\t\t fw_major_version && fw_minor_version &&\n\t\t ((*api_major_version == 1) && (*api_minor_version == 1)) &&\n\t\t (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||\n\t\t (*fw_major_version > 4)))\n\t\t\t*api_minor_version = 2;\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_send_driver_version\n * @hw: pointer to the hw struct\n * @dv: driver's major, minor version\n * @cmd_details: pointer to command details structure or NULL\n *\n * Send the driver version to the firmware\n **/\nenum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_driver_version *dv,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_driver_version *cmd =\n\t\t(struct i40e_aqc_driver_version *)&desc.params.raw;\n\tenum i40e_status_code status;\n\tu16 len;\n\n\tif (dv == NULL)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);\n\n\tdesc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);\n\tcmd->driver_major_ver = dv->major_version;\n\tcmd->driver_minor_ver = dv->minor_version;\n\tcmd->driver_build_ver = dv->build_version;\n\tcmd->driver_subbuild_ver = dv->subbuild_version;\n\n\tlen = 0;\n\twhile (len < sizeof(dv->driver_string) &&\n\t (dv->driver_string[len] < 0x80) &&\n\t dv->driver_string[len])\n\t\tlen++;\n\tstatus = i40e_asq_send_command(hw, &desc, dv->driver_string,\n\t\t\t\t len, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_get_link_status - get status of the HW network link\n * @hw: pointer to the hw struct\n *\n * Returns true if link is up, false if link is down.\n *\n * Side effect: LinkStatusEvent reporting becomes enabled\n **/\nbool i40e_get_link_status(struct i40e_hw *hw)\n{\n\tenum i40e_status_code status = I40E_SUCCESS;\n\tbool link_status = false;\n\n\tif (hw->phy.get_link_info) {\n\t\tstatus = i40e_aq_get_link_info(hw, true, NULL, NULL);\n\n\t\tif (status != I40E_SUCCESS)\n\t\t\tgoto i40e_get_link_status_exit;\n\t}\n\n\tlink_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;\n\ni40e_get_link_status_exit:\n\treturn link_status;\n}\n\n/**\n * i40e_get_link_speed\n * @hw: pointer to the hw struct\n *\n * Returns the link speed of the adapter.\n **/\nenum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)\n{\n\tenum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;\n\tenum i40e_status_code status = I40E_SUCCESS;\n\n\tif (hw->phy.get_link_info) {\n\t\tstatus = i40e_aq_get_link_info(hw, true, NULL, NULL);\n\n\t\tif (status != I40E_SUCCESS)\n\t\t\tgoto i40e_link_speed_exit;\n\t}\n\n\tspeed = hw->phy.link_info.link_speed;\n\ni40e_link_speed_exit:\n\treturn speed;\n}\n\n/**\n * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC\n * @hw: pointer to the hw struct\n * @uplink_seid: the MAC or other gizmo SEID\n * @downlink_seid: the VSI SEID\n * @enabled_tc: bitmap of TCs to be enabled\n * @default_port: true for default port VSI, false for control port\n * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support\n * @veb_seid: pointer to where to put the resulting VEB SEID\n * @cmd_details: pointer to command details structure or NULL\n *\n * This asks the FW to add a VEB between the uplink and downlink\n * elements. If the uplink SEID is 0, this will be a floating VEB.\n **/\nenum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,\n\t\t\t\tu16 downlink_seid, u8 enabled_tc,\n\t\t\t\tbool default_port, bool enable_l2_filtering,\n\t\t\t\tu16 *veb_seid,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_veb *cmd =\n\t\t(struct i40e_aqc_add_veb *)&desc.params.raw;\n\tstruct i40e_aqc_add_veb_completion *resp =\n\t\t(struct i40e_aqc_add_veb_completion *)&desc.params.raw;\n\tenum i40e_status_code status;\n\tu16 veb_flags = 0;\n\n\t/* SEIDs need to either both be set or both be 0 for floating VEB */\n\tif (!!uplink_seid != !!downlink_seid)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);\n\n\tcmd->uplink_seid = CPU_TO_LE16(uplink_seid);\n\tcmd->downlink_seid = CPU_TO_LE16(downlink_seid);\n\tcmd->enable_tcs = enabled_tc;\n\tif (!uplink_seid)\n\t\tveb_flags |= I40E_AQC_ADD_VEB_FLOATING;\n\tif (default_port)\n\t\tveb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;\n\telse\n\t\tveb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;\n\n\tif (enable_l2_filtering)\n\t\tveb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;\n\n\tcmd->veb_flags = CPU_TO_LE16(veb_flags);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (!status && veb_seid)\n\t\t*veb_seid = LE16_TO_CPU(resp->veb_seid);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_get_veb_parameters - Retrieve VEB parameters\n * @hw: pointer to the hw struct\n * @veb_seid: the SEID of the VEB to query\n * @switch_id: the uplink switch id\n * @floating: set to true if the VEB is floating\n * @statistic_index: index of the stats counter block for this VEB\n * @vebs_used: number of VEB's used by function\n * @vebs_free: total VEB's not reserved by any function\n * @cmd_details: pointer to command details structure or NULL\n *\n * This retrieves the parameters for a particular VEB, specified by\n * uplink_seid, and returns them to the caller.\n **/\nenum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,\n\t\t\t\tu16 veb_seid, u16 *switch_id,\n\t\t\t\tbool *floating, u16 *statistic_index,\n\t\t\t\tu16 *vebs_used, u16 *vebs_free,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_get_veb_parameters_completion *cmd_resp =\n\t\t(struct i40e_aqc_get_veb_parameters_completion *)\n\t\t&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (veb_seid == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_get_veb_parameters);\n\tcmd_resp->seid = CPU_TO_LE16(veb_seid);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\tif (status)\n\t\tgoto get_veb_exit;\n\n\tif (switch_id)\n\t\t*switch_id = LE16_TO_CPU(cmd_resp->switch_id);\n\tif (statistic_index)\n\t\t*statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);\n\tif (vebs_used)\n\t\t*vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);\n\tif (vebs_free)\n\t\t*vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);\n\tif (floating) {\n\t\tu16 flags = LE16_TO_CPU(cmd_resp->veb_flags);\n\t\tif (flags & I40E_AQC_ADD_VEB_FLOATING)\n\t\t\t*floating = true;\n\t\telse\n\t\t\t*floating = false;\n\t}\n\nget_veb_exit:\n\treturn status;\n}\n\n/**\n * i40e_aq_add_macvlan\n * @hw: pointer to the hw struct\n * @seid: VSI for the mac address\n * @mv_list: list of macvlans to be added\n * @count: length of the list\n * @cmd_details: pointer to command details structure or NULL\n *\n * Add MAC/VLAN addresses to the HW filtering\n **/\nenum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,\n\t\t\tstruct i40e_aqc_add_macvlan_element_data *mv_list,\n\t\t\tu16 count, struct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_macvlan *cmd =\n\t\t(struct i40e_aqc_macvlan *)&desc.params.raw;\n\tenum i40e_status_code status;\n\tu16 buf_size;\n\n\tif (count == 0 || !mv_list || !hw)\n\t\treturn I40E_ERR_PARAM;\n\n\tbuf_size = count * sizeof(*mv_list);\n\n\t/* prep the rest of the request */\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);\n\tcmd->num_addresses = CPU_TO_LE16(count);\n\tcmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);\n\tcmd->seid[1] = 0;\n\tcmd->seid[2] = 0;\n\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tif (buf_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tstatus = i40e_asq_send_command(hw, &desc, mv_list, buf_size,\n\t\t\t\t cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_remove_macvlan\n * @hw: pointer to the hw struct\n * @seid: VSI for the mac address\n * @mv_list: list of macvlans to be removed\n * @count: length of the list\n * @cmd_details: pointer to command details structure or NULL\n *\n * Remove MAC/VLAN addresses from the HW filtering\n **/\nenum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,\n\t\t\tstruct i40e_aqc_remove_macvlan_element_data *mv_list,\n\t\t\tu16 count, struct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_macvlan *cmd =\n\t\t(struct i40e_aqc_macvlan *)&desc.params.raw;\n\tenum i40e_status_code status;\n\tu16 buf_size;\n\n\tif (count == 0 || !mv_list || !hw)\n\t\treturn I40E_ERR_PARAM;\n\n\tbuf_size = count * sizeof(*mv_list);\n\n\t/* prep the rest of the request */\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);\n\tcmd->num_addresses = CPU_TO_LE16(count);\n\tcmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);\n\tcmd->seid[1] = 0;\n\tcmd->seid[2] = 0;\n\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tif (buf_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tstatus = i40e_asq_send_command(hw, &desc, mv_list, buf_size,\n\t\t\t\t cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_add_vlan - Add VLAN ids to the HW filtering\n * @hw: pointer to the hw struct\n * @seid: VSI for the vlan filters\n * @v_list: list of vlan filters to be added\n * @count: length of the list\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,\n\t\t\tstruct i40e_aqc_add_remove_vlan_element_data *v_list,\n\t\t\tu8 count, struct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_macvlan *cmd =\n\t\t(struct i40e_aqc_macvlan *)&desc.params.raw;\n\tenum i40e_status_code status;\n\tu16 buf_size;\n\n\tif (count == 0 || !v_list || !hw)\n\t\treturn I40E_ERR_PARAM;\n\n\tbuf_size = count * sizeof(*v_list);\n\n\t/* prep the rest of the request */\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);\n\tcmd->num_addresses = CPU_TO_LE16(count);\n\tcmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);\n\tcmd->seid[1] = 0;\n\tcmd->seid[2] = 0;\n\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tif (buf_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tstatus = i40e_asq_send_command(hw, &desc, v_list, buf_size,\n\t\t\t\t cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_remove_vlan - Remove VLANs from the HW filtering\n * @hw: pointer to the hw struct\n * @seid: VSI for the vlan filters\n * @v_list: list of macvlans to be removed\n * @count: length of the list\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,\n\t\t\tstruct i40e_aqc_add_remove_vlan_element_data *v_list,\n\t\t\tu8 count, struct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_macvlan *cmd =\n\t\t(struct i40e_aqc_macvlan *)&desc.params.raw;\n\tenum i40e_status_code status;\n\tu16 buf_size;\n\n\tif (count == 0 || !v_list || !hw)\n\t\treturn I40E_ERR_PARAM;\n\n\tbuf_size = count * sizeof(*v_list);\n\n\t/* prep the rest of the request */\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);\n\tcmd->num_addresses = CPU_TO_LE16(count);\n\tcmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);\n\tcmd->seid[1] = 0;\n\tcmd->seid[2] = 0;\n\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tif (buf_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tstatus = i40e_asq_send_command(hw, &desc, v_list, buf_size,\n\t\t\t\t cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_send_msg_to_vf\n * @hw: pointer to the hardware structure\n * @vfid: vf id to send msg\n * @v_opcode: opcodes for VF-PF communication\n * @v_retval: return error code\n * @msg: pointer to the msg buffer\n * @msglen: msg length\n * @cmd_details: pointer to command details\n *\n * send msg to vf\n **/\nenum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,\n\t\t\t\tu32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_pf_vf_message *cmd =\n\t\t(struct i40e_aqc_pf_vf_message *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);\n\tcmd->id = CPU_TO_LE32(vfid);\n\tdesc.cookie_high = CPU_TO_LE32(v_opcode);\n\tdesc.cookie_low = CPU_TO_LE32(v_retval);\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);\n\tif (msglen) {\n\t\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF |\n\t\t\t\t\t\tI40E_AQ_FLAG_RD));\n\t\tif (msglen > I40E_AQ_LARGE_BUF)\n\t\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\t\tdesc.datalen = CPU_TO_LE16(msglen);\n\t}\n\tstatus = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_debug_read_register\n * @hw: pointer to the hw struct\n * @reg_addr: register address\n * @reg_val: register value\n * @cmd_details: pointer to command details structure or NULL\n *\n * Read the register using the admin queue commands\n **/\nenum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,\n\t\t\t\tu32 reg_addr, u64 *reg_val,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_debug_reg_read_write *cmd_resp =\n\t\t(struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (reg_val == NULL)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);\n\n\tcmd_resp->address = CPU_TO_LE32(reg_addr);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (status == I40E_SUCCESS) {\n\t\t*reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) |\n\t\t\t (u64)LE32_TO_CPU(cmd_resp->value_low);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_debug_write_register\n * @hw: pointer to the hw struct\n * @reg_addr: register address\n * @reg_val: register value\n * @cmd_details: pointer to command details structure or NULL\n *\n * Write to a register using the admin queue commands\n **/\nenum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,\n\t\t\t\tu32 reg_addr, u64 reg_val,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_debug_reg_read_write *cmd =\n\t\t(struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);\n\n\tcmd->address = CPU_TO_LE32(reg_addr);\n\tcmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32));\n\tcmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF));\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_get_hmc_resource_profile\n * @hw: pointer to the hw struct\n * @profile: type of profile the HMC is to be set as\n * @pe_vf_enabled_count: the number of PE enabled VFs the system has\n * @cmd_details: pointer to command details structure or NULL\n *\n * query the HMC profile of the device.\n **/\nenum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,\n\t\t\t\tenum i40e_aq_hmc_profile *profile,\n\t\t\t\tu8 *pe_vf_enabled_count,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aq_get_set_hmc_resource_profile *resp =\n\t\t(struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\ti40e_aqc_opc_query_hmc_resource_profile);\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\t*profile = (enum i40e_aq_hmc_profile)(resp->pm_profile &\n\t\t I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK);\n\t*pe_vf_enabled_count = resp->pe_vf_enabled &\n\t\t\t I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK;\n\n\treturn status;\n}\n\n/**\n * i40e_aq_set_hmc_resource_profile\n * @hw: pointer to the hw struct\n * @profile: type of profile the HMC is to be set as\n * @pe_vf_enabled_count: the number of PE enabled VFs the system has\n * @cmd_details: pointer to command details structure or NULL\n *\n * set the HMC profile of the device.\n **/\nenum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,\n\t\t\t\tenum i40e_aq_hmc_profile profile,\n\t\t\t\tu8 pe_vf_enabled_count,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aq_get_set_hmc_resource_profile *cmd =\n\t\t(struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\ti40e_aqc_opc_set_hmc_resource_profile);\n\n\tcmd->pm_profile = (u8)profile;\n\tcmd->pe_vf_enabled = pe_vf_enabled_count;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_request_resource\n * @hw: pointer to the hw struct\n * @resource: resource id\n * @access: access type\n * @sdp_number: resource number\n * @timeout: the maximum time in ms that the driver may hold the resource\n * @cmd_details: pointer to command details structure or NULL\n *\n * requests common resource using the admin queue commands\n **/\nenum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,\n\t\t\t\tenum i40e_aq_resources_ids resource,\n\t\t\t\tenum i40e_aq_resource_access_type access,\n\t\t\t\tu8 sdp_number, u64 *timeout,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_request_resource *cmd_resp =\n\t\t(struct i40e_aqc_request_resource *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tDEBUGFUNC(\"i40e_aq_request_resource\");\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);\n\n\tcmd_resp->resource_id = CPU_TO_LE16(resource);\n\tcmd_resp->access_type = CPU_TO_LE16(access);\n\tcmd_resp->resource_number = CPU_TO_LE32(sdp_number);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\t/* The completion specifies the maximum time in ms that the driver\n\t * may hold the resource in the Timeout field.\n\t * If the resource is held by someone else, the command completes with\n\t * busy return value and the timeout field indicates the maximum time\n\t * the current owner of the resource has to free it.\n\t */\n\tif (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)\n\t\t*timeout = LE32_TO_CPU(cmd_resp->timeout);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_release_resource\n * @hw: pointer to the hw struct\n * @resource: resource id\n * @sdp_number: resource number\n * @cmd_details: pointer to command details structure or NULL\n *\n * release common resource using the admin queue commands\n **/\nenum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,\n\t\t\t\tenum i40e_aq_resources_ids resource,\n\t\t\t\tu8 sdp_number,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_request_resource *cmd =\n\t\t(struct i40e_aqc_request_resource *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tDEBUGFUNC(\"i40e_aq_release_resource\");\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);\n\n\tcmd->resource_id = CPU_TO_LE16(resource);\n\tcmd->resource_number = CPU_TO_LE32(sdp_number);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_read_nvm\n * @hw: pointer to the hw struct\n * @module_pointer: module pointer location in words from the NVM beginning\n * @offset: byte offset from the module beginning\n * @length: length of the section to be read (in bytes from the offset)\n * @data: command buffer (size [bytes] = length)\n * @last_command: tells if this is the last command in a series\n * @cmd_details: pointer to command details structure or NULL\n *\n * Read the NVM using the admin queue commands\n **/\nenum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,\n\t\t\t\tu32 offset, u16 length, void *data,\n\t\t\t\tbool last_command,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_nvm_update *cmd =\n\t\t(struct i40e_aqc_nvm_update *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tDEBUGFUNC(\"i40e_aq_read_nvm\");\n\n\t/* In offset the highest byte must be zeroed. */\n\tif (offset & 0xFF000000) {\n\t\tstatus = I40E_ERR_PARAM;\n\t\tgoto i40e_aq_read_nvm_exit;\n\t}\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);\n\n\t/* If this is the last command in a series, set the proper flag. */\n\tif (last_command)\n\t\tcmd->command_flags |= I40E_AQ_NVM_LAST_CMD;\n\tcmd->module_pointer = module_pointer;\n\tcmd->offset = CPU_TO_LE32(offset);\n\tcmd->length = CPU_TO_LE16(length);\n\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);\n\tif (length > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tstatus = i40e_asq_send_command(hw, &desc, data, length, cmd_details);\n\ni40e_aq_read_nvm_exit:\n\treturn status;\n}\n\n/**\n * i40e_aq_read_nvm_config - read an nvm config block\n * @hw: pointer to the hw struct\n * @cmd_flags: NVM access admin command bits\n * @field_id: field or feature id\n * @data: buffer for result\n * @buf_size: buffer size\n * @element_count: pointer to count of elements read by FW\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,\n\t\t\t\tu8 cmd_flags, u32 field_id, void *data,\n\t\t\t\tu16 buf_size, u16 *element_count,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_nvm_config_read *cmd =\n\t\t(struct i40e_aqc_nvm_config_read *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read);\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF));\n\tif (buf_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tcmd->cmd_flags = CPU_TO_LE16(cmd_flags);\n\tcmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id));\n\tif (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK)\n\t\tcmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16));\n\telse\n\t\tcmd->element_id_msw = 0;\n\n\tstatus = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);\n\n\tif (!status && element_count)\n\t\t*element_count = LE16_TO_CPU(cmd->element_count);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_write_nvm_config - write an nvm config block\n * @hw: pointer to the hw struct\n * @cmd_flags: NVM access admin command bits\n * @data: buffer for result\n * @buf_size: buffer size\n * @element_count: count of elements to be written\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,\n\t\t\t\tu8 cmd_flags, void *data, u16 buf_size,\n\t\t\t\tu16 element_count,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_nvm_config_write *cmd =\n\t\t(struct i40e_aqc_nvm_config_write *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write);\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tif (buf_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tcmd->element_count = CPU_TO_LE16(element_count);\n\tcmd->cmd_flags = CPU_TO_LE16(cmd_flags);\n\tstatus = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_erase_nvm\n * @hw: pointer to the hw struct\n * @module_pointer: module pointer location in words from the NVM beginning\n * @offset: offset in the module (expressed in 4 KB from module's beginning)\n * @length: length of the section to be erased (expressed in 4 KB)\n * @last_command: tells if this is the last command in a series\n * @cmd_details: pointer to command details structure or NULL\n *\n * Erase the NVM sector using the admin queue commands\n **/\nenum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,\n\t\t\t\tu32 offset, u16 length, bool last_command,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_nvm_update *cmd =\n\t\t(struct i40e_aqc_nvm_update *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tDEBUGFUNC(\"i40e_aq_erase_nvm\");\n\n\t/* In offset the highest byte must be zeroed. */\n\tif (offset & 0xFF000000) {\n\t\tstatus = I40E_ERR_PARAM;\n\t\tgoto i40e_aq_erase_nvm_exit;\n\t}\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);\n\n\t/* If this is the last command in a series, set the proper flag. */\n\tif (last_command)\n\t\tcmd->command_flags |= I40E_AQ_NVM_LAST_CMD;\n\tcmd->module_pointer = module_pointer;\n\tcmd->offset = CPU_TO_LE32(offset);\n\tcmd->length = CPU_TO_LE16(length);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\ni40e_aq_erase_nvm_exit:\n\treturn status;\n}\n\n#define I40E_DEV_FUNC_CAP_SWITCH_MODE\t0x01\n#define I40E_DEV_FUNC_CAP_MGMT_MODE\t0x02\n#define I40E_DEV_FUNC_CAP_NPAR\t\t0x03\n#define I40E_DEV_FUNC_CAP_OS2BMC\t0x04\n#define I40E_DEV_FUNC_CAP_VALID_FUNC\t0x05\n#define I40E_DEV_FUNC_CAP_SRIOV_1_1\t0x12\n#define I40E_DEV_FUNC_CAP_VF\t\t0x13\n#define I40E_DEV_FUNC_CAP_VMDQ\t\t0x14\n#define I40E_DEV_FUNC_CAP_802_1_QBG\t0x15\n#define I40E_DEV_FUNC_CAP_802_1_QBH\t0x16\n#define I40E_DEV_FUNC_CAP_VSI\t\t0x17\n#define I40E_DEV_FUNC_CAP_DCB\t\t0x18\n#define I40E_DEV_FUNC_CAP_FCOE\t\t0x21\n#define I40E_DEV_FUNC_CAP_ISCSI\t\t0x22\n#define I40E_DEV_FUNC_CAP_RSS\t\t0x40\n#define I40E_DEV_FUNC_CAP_RX_QUEUES\t0x41\n#define I40E_DEV_FUNC_CAP_TX_QUEUES\t0x42\n#define I40E_DEV_FUNC_CAP_MSIX\t\t0x43\n#define I40E_DEV_FUNC_CAP_MSIX_VF\t0x44\n#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR\t0x45\n#define I40E_DEV_FUNC_CAP_IEEE_1588\t0x46\n#define I40E_DEV_FUNC_CAP_MFP_MODE_1\t0xF1\n#define I40E_DEV_FUNC_CAP_CEM\t\t0xF2\n#define I40E_DEV_FUNC_CAP_IWARP\t\t0x51\n#define I40E_DEV_FUNC_CAP_LED\t\t0x61\n#define I40E_DEV_FUNC_CAP_SDP\t\t0x62\n#define I40E_DEV_FUNC_CAP_MDIO\t\t0x63\n\n/**\n * i40e_parse_discover_capabilities\n * @hw: pointer to the hw struct\n * @buff: pointer to a buffer containing device/function capability records\n * @cap_count: number of capability records in the list\n * @list_type_opc: type of capabilities list to parse\n *\n * Parse the device/function capabilities list.\n **/\nSTATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,\n\t\t\t\t u32 cap_count,\n\t\t\t\t enum i40e_admin_queue_opc list_type_opc)\n{\n\tstruct i40e_aqc_list_capabilities_element_resp *cap;\n\tu32 valid_functions, num_functions;\n\tu32 number, logical_id, phys_id;\n\tstruct i40e_hw_capabilities *p;\n\tu32 i = 0;\n\tu16 id;\n\n\tcap = (struct i40e_aqc_list_capabilities_element_resp *) buff;\n\n\tif (list_type_opc == i40e_aqc_opc_list_dev_capabilities)\n\t\tp = (struct i40e_hw_capabilities *)&hw->dev_caps;\n\telse if (list_type_opc == i40e_aqc_opc_list_func_capabilities)\n\t\tp = (struct i40e_hw_capabilities *)&hw->func_caps;\n\telse\n\t\treturn;\n\n\tfor (i = 0; i < cap_count; i++, cap++) {\n\t\tid = LE16_TO_CPU(cap->id);\n\t\tnumber = LE32_TO_CPU(cap->number);\n\t\tlogical_id = LE32_TO_CPU(cap->logical_id);\n\t\tphys_id = LE32_TO_CPU(cap->phys_id);\n\n\t\tswitch (id) {\n\t\tcase I40E_DEV_FUNC_CAP_SWITCH_MODE:\n\t\t\tp->switch_mode = number;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_MGMT_MODE:\n\t\t\tp->management_mode = number;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_NPAR:\n\t\t\tp->npar_enable = number;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_OS2BMC:\n\t\t\tp->os2bmc = number;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_VALID_FUNC:\n\t\t\tp->valid_functions = number;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_SRIOV_1_1:\n\t\t\tif (number == 1)\n\t\t\t\tp->sr_iov_1_1 = true;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_VF:\n\t\t\tp->num_vfs = number;\n\t\t\tp->vf_base_id = logical_id;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_VMDQ:\n\t\t\tif (number == 1)\n\t\t\t\tp->vmdq = true;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_802_1_QBG:\n\t\t\tif (number == 1)\n\t\t\t\tp->evb_802_1_qbg = true;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_802_1_QBH:\n\t\t\tif (number == 1)\n\t\t\t\tp->evb_802_1_qbh = true;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_VSI:\n\t\t\tp->num_vsis = number;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_DCB:\n\t\t\tif (number == 1) {\n\t\t\t\tp->dcb = true;\n\t\t\t\tp->enabled_tcmap = logical_id;\n\t\t\t\tp->maxtc = phys_id;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_FCOE:\n\t\t\tif (number == 1)\n\t\t\t\tp->fcoe = true;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_ISCSI:\n\t\t\tif (number == 1)\n\t\t\t\tp->iscsi = true;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_RSS:\n\t\t\tp->rss = true;\n\t\t\tp->rss_table_size = number;\n\t\t\tp->rss_table_entry_width = logical_id;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_RX_QUEUES:\n\t\t\tp->num_rx_qp = number;\n\t\t\tp->base_queue = phys_id;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_TX_QUEUES:\n\t\t\tp->num_tx_qp = number;\n\t\t\tp->base_queue = phys_id;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_MSIX:\n\t\t\tp->num_msix_vectors = number;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_MSIX_VF:\n\t\t\tp->num_msix_vectors_vf = number;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_MFP_MODE_1:\n\t\t\tif (number == 1)\n\t\t\t\tp->mfp_mode_1 = true;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_CEM:\n\t\t\tif (number == 1)\n\t\t\t\tp->mgmt_cem = true;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_IWARP:\n\t\t\tif (number == 1)\n\t\t\t\tp->iwarp = true;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_LED:\n\t\t\tif (phys_id < I40E_HW_CAP_MAX_GPIO)\n\t\t\t\tp->led[phys_id] = true;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_SDP:\n\t\t\tif (phys_id < I40E_HW_CAP_MAX_GPIO)\n\t\t\t\tp->sdp[phys_id] = true;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_MDIO:\n\t\t\tif (number == 1) {\n\t\t\t\tp->mdio_port_num = phys_id;\n\t\t\t\tp->mdio_port_mode = logical_id;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_IEEE_1588:\n\t\t\tif (number == 1)\n\t\t\t\tp->ieee_1588 = true;\n\t\t\tbreak;\n\t\tcase I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:\n\t\t\tp->fd = true;\n\t\t\tp->fd_filters_guaranteed = number;\n\t\t\tp->fd_filters_best_effort = logical_id;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n#ifdef I40E_FCOE_ENA\n\t/* Software override ensuring FCoE is disabled if npar or mfp\n\t * mode because it is not supported in these modes.\n\t */\n\tif (p->npar_enable || p->mfp_mode_1)\n\t\tp->fcoe = false;\n#else\n\t/* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */\n\tp->fcoe = false;\n#endif\n\n\t/* count the enabled ports (aka the \"not disabled\" ports) */\n\thw->num_ports = 0;\n\tfor (i = 0; i < 4; i++) {\n\t\tu32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);\n\t\tu64 port_cfg = 0;\n\n\t\t/* use AQ read to get the physical register offset instead\n\t\t * of the port relative offset\n\t\t */\n\t\ti40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);\n\t\tif (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))\n\t\t\thw->num_ports++;\n\t}\n\n\tvalid_functions = p->valid_functions;\n\tnum_functions = 0;\n\twhile (valid_functions) {\n\t\tif (valid_functions & 1)\n\t\t\tnum_functions++;\n\t\tvalid_functions >>= 1;\n\t}\n\n\t/* partition id is 1-based, and functions are evenly spread\n\t * across the ports as partitions\n\t */\n\thw->partition_id = (hw->pf_id / hw->num_ports) + 1;\n\thw->num_partitions = num_functions / hw->num_ports;\n\n\t/* additional HW specific goodies that might\n\t * someday be HW version specific\n\t */\n\tp->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;\n}\n\n/**\n * i40e_aq_discover_capabilities\n * @hw: pointer to the hw struct\n * @buff: a virtual buffer to hold the capabilities\n * @buff_size: Size of the virtual buffer\n * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM\n * @list_type_opc: capabilities type to discover - pass in the command opcode\n * @cmd_details: pointer to command details structure or NULL\n *\n * Get the device capabilities descriptions from the firmware\n **/\nenum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,\n\t\t\t\tvoid *buff, u16 buff_size, u16 *data_size,\n\t\t\t\tenum i40e_admin_queue_opc list_type_opc,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aqc_list_capabilites *cmd;\n\tstruct i40e_aq_desc desc;\n\tenum i40e_status_code status = I40E_SUCCESS;\n\n\tcmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;\n\n\tif (list_type_opc != i40e_aqc_opc_list_func_capabilities &&\n\t\tlist_type_opc != i40e_aqc_opc_list_dev_capabilities) {\n\t\tstatus = I40E_ERR_PARAM;\n\t\tgoto exit;\n\t}\n\n\ti40e_fill_default_direct_cmd_desc(&desc, list_type_opc);\n\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);\n\tif (buff_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tstatus = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);\n\t*data_size = LE16_TO_CPU(desc.datalen);\n\n\tif (status)\n\t\tgoto exit;\n\n\ti40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count),\n\t\t\t\t\t list_type_opc);\n\nexit:\n\treturn status;\n}\n\n/**\n * i40e_aq_update_nvm\n * @hw: pointer to the hw struct\n * @module_pointer: module pointer location in words from the NVM beginning\n * @offset: byte offset from the module beginning\n * @length: length of the section to be written (in bytes from the offset)\n * @data: command buffer (size [bytes] = length)\n * @last_command: tells if this is the last command in a series\n * @cmd_details: pointer to command details structure or NULL\n *\n * Update the NVM using the admin queue commands\n **/\nenum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,\n\t\t\t\tu32 offset, u16 length, void *data,\n\t\t\t\tbool last_command,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_nvm_update *cmd =\n\t\t(struct i40e_aqc_nvm_update *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tDEBUGFUNC(\"i40e_aq_update_nvm\");\n\n\t/* In offset the highest byte must be zeroed. */\n\tif (offset & 0xFF000000) {\n\t\tstatus = I40E_ERR_PARAM;\n\t\tgoto i40e_aq_update_nvm_exit;\n\t}\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);\n\n\t/* If this is the last command in a series, set the proper flag. */\n\tif (last_command)\n\t\tcmd->command_flags |= I40E_AQ_NVM_LAST_CMD;\n\tcmd->module_pointer = module_pointer;\n\tcmd->offset = CPU_TO_LE32(offset);\n\tcmd->length = CPU_TO_LE16(length);\n\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tif (length > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tstatus = i40e_asq_send_command(hw, &desc, data, length, cmd_details);\n\ni40e_aq_update_nvm_exit:\n\treturn status;\n}\n\n/**\n * i40e_aq_get_lldp_mib\n * @hw: pointer to the hw struct\n * @bridge_type: type of bridge requested\n * @mib_type: Local, Remote or both Local and Remote MIBs\n * @buff: pointer to a user supplied buffer to store the MIB block\n * @buff_size: size of the buffer (in bytes)\n * @local_len : length of the returned Local LLDP MIB\n * @remote_len: length of the returned Remote LLDP MIB\n * @cmd_details: pointer to command details structure or NULL\n *\n * Requests the complete LLDP MIB (entire packet).\n **/\nenum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,\n\t\t\t\tu8 mib_type, void *buff, u16 buff_size,\n\t\t\t\tu16 *local_len, u16 *remote_len,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_lldp_get_mib *cmd =\n\t\t(struct i40e_aqc_lldp_get_mib *)&desc.params.raw;\n\tstruct i40e_aqc_lldp_get_mib *resp =\n\t\t(struct i40e_aqc_lldp_get_mib *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (buff_size == 0 || !buff)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);\n\t/* Indirect Command */\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);\n\n\tcmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;\n\tcmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &\n\t\t I40E_AQ_LLDP_BRIDGE_TYPE_MASK);\n\n\tdesc.datalen = CPU_TO_LE16(buff_size);\n\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);\n\tif (buff_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tstatus = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);\n\tif (!status) {\n\t\tif (local_len != NULL)\n\t\t\t*local_len = LE16_TO_CPU(resp->local_len);\n\t\tif (remote_len != NULL)\n\t\t\t*remote_len = LE16_TO_CPU(resp->remote_len);\n\t}\n\n\treturn status;\n}\n\n /**\n * i40e_aq_set_lldp_mib - Set the LLDP MIB\n * @hw: pointer to the hw struct\n * @mib_type: Local, Remote or both Local and Remote MIBs\n * @buff: pointer to a user supplied buffer to store the MIB block\n * @buff_size: size of the buffer (in bytes)\n * @cmd_details: pointer to command details structure or NULL\n *\n * Set the LLDP MIB.\n **/\nenum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,\n\t\t\t\tu8 mib_type, void *buff, u16 buff_size,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_lldp_set_local_mib *cmd =\n\t\t(struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (buff_size == 0 || !buff)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\ti40e_aqc_opc_lldp_set_local_mib);\n\t/* Indirect Command */\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tif (buff_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\tdesc.datalen = CPU_TO_LE16(buff_size);\n\n\tcmd->type = mib_type;\n\tcmd->length = CPU_TO_LE16(buff_size);\n\tcmd->address_high = CPU_TO_LE32(I40E_HI_WORD((u64)buff));\n\tcmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buff));\n\n\tstatus = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);\n\treturn status;\n}\n\n/**\n * i40e_aq_cfg_lldp_mib_change_event\n * @hw: pointer to the hw struct\n * @enable_update: Enable or Disable event posting\n * @cmd_details: pointer to command details structure or NULL\n *\n * Enable or Disable posting of an event on ARQ when LLDP MIB\n * associated with the interface changes\n **/\nenum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,\n\t\t\t\tbool enable_update,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_lldp_update_mib *cmd =\n\t\t(struct i40e_aqc_lldp_update_mib *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);\n\n\tif (!enable_update)\n\t\tcmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_add_lldp_tlv\n * @hw: pointer to the hw struct\n * @bridge_type: type of bridge\n * @buff: buffer with TLV to add\n * @buff_size: length of the buffer\n * @tlv_len: length of the TLV to be added\n * @mib_len: length of the LLDP MIB returned in response\n * @cmd_details: pointer to command details structure or NULL\n *\n * Add the specified TLV to LLDP Local MIB for the given bridge type,\n * it is responsibility of the caller to make sure that the TLV is not\n * already present in the LLDPDU.\n * In return firmware will write the complete LLDP MIB with the newly\n * added TLV in the response buffer.\n **/\nenum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,\n\t\t\t\tvoid *buff, u16 buff_size, u16 tlv_len,\n\t\t\t\tu16 *mib_len,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_lldp_add_tlv *cmd =\n\t\t(struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (buff_size == 0 || !buff || tlv_len == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv);\n\n\t/* Indirect Command */\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tif (buff_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\tdesc.datalen = CPU_TO_LE16(buff_size);\n\n\tcmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &\n\t\t I40E_AQ_LLDP_BRIDGE_TYPE_MASK);\n\tcmd->len = CPU_TO_LE16(tlv_len);\n\n\tstatus = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);\n\tif (!status) {\n\t\tif (mib_len != NULL)\n\t\t\t*mib_len = LE16_TO_CPU(desc.datalen);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_update_lldp_tlv\n * @hw: pointer to the hw struct\n * @bridge_type: type of bridge\n * @buff: buffer with TLV to update\n * @buff_size: size of the buffer holding original and updated TLVs\n * @old_len: Length of the Original TLV\n * @new_len: Length of the Updated TLV\n * @offset: offset of the updated TLV in the buff\n * @mib_len: length of the returned LLDP MIB\n * @cmd_details: pointer to command details structure or NULL\n *\n * Update the specified TLV to the LLDP Local MIB for the given bridge type.\n * Firmware will place the complete LLDP MIB in response buffer with the\n * updated TLV.\n **/\nenum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,\n\t\t\t\tu8 bridge_type, void *buff, u16 buff_size,\n\t\t\t\tu16 old_len, u16 new_len, u16 offset,\n\t\t\t\tu16 *mib_len,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_lldp_update_tlv *cmd =\n\t\t(struct i40e_aqc_lldp_update_tlv *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (buff_size == 0 || !buff || offset == 0 ||\n\t old_len == 0 || new_len == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv);\n\n\t/* Indirect Command */\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tif (buff_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\tdesc.datalen = CPU_TO_LE16(buff_size);\n\n\tcmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &\n\t\t I40E_AQ_LLDP_BRIDGE_TYPE_MASK);\n\tcmd->old_len = CPU_TO_LE16(old_len);\n\tcmd->new_offset = CPU_TO_LE16(offset);\n\tcmd->new_len = CPU_TO_LE16(new_len);\n\n\tstatus = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);\n\tif (!status) {\n\t\tif (mib_len != NULL)\n\t\t\t*mib_len = LE16_TO_CPU(desc.datalen);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_delete_lldp_tlv\n * @hw: pointer to the hw struct\n * @bridge_type: type of bridge\n * @buff: pointer to a user supplied buffer that has the TLV\n * @buff_size: length of the buffer\n * @tlv_len: length of the TLV to be deleted\n * @mib_len: length of the returned LLDP MIB\n * @cmd_details: pointer to command details structure or NULL\n *\n * Delete the specified TLV from LLDP Local MIB for the given bridge type.\n * The firmware places the entire LLDP MIB in the response buffer.\n **/\nenum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,\n\t\t\t\tu8 bridge_type, void *buff, u16 buff_size,\n\t\t\t\tu16 tlv_len, u16 *mib_len,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_lldp_add_tlv *cmd =\n\t\t(struct i40e_aqc_lldp_add_tlv *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (buff_size == 0 || !buff)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv);\n\n\t/* Indirect Command */\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tif (buff_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\tdesc.datalen = CPU_TO_LE16(buff_size);\n\tcmd->len = CPU_TO_LE16(tlv_len);\n\tcmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &\n\t\t I40E_AQ_LLDP_BRIDGE_TYPE_MASK);\n\n\tstatus = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);\n\tif (!status) {\n\t\tif (mib_len != NULL)\n\t\t\t*mib_len = LE16_TO_CPU(desc.datalen);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_stop_lldp\n * @hw: pointer to the hw struct\n * @shutdown_agent: True if LLDP Agent needs to be Shutdown\n * @cmd_details: pointer to command details structure or NULL\n *\n * Stop or Shutdown the embedded LLDP Agent\n **/\nenum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_lldp_stop *cmd =\n\t\t(struct i40e_aqc_lldp_stop *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);\n\n\tif (shutdown_agent)\n\t\tcmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_start_lldp\n * @hw: pointer to the hw struct\n * @cmd_details: pointer to command details structure or NULL\n *\n * Start the embedded LLDP Agent on all ports.\n **/\nenum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_lldp_start *cmd =\n\t\t(struct i40e_aqc_lldp_start *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);\n\n\tcmd->command = I40E_AQ_LLDP_AGENT_START;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_get_cee_dcb_config\n * @hw: pointer to the hw struct\n * @buff: response buffer that stores CEE operational configuration\n * @buff_size: size of the buffer passed\n * @cmd_details: pointer to command details structure or NULL\n *\n * Get CEE DCBX mode operational configuration from firmware\n **/\nenum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,\n\t\t\t\tvoid *buff, u16 buff_size,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tenum i40e_status_code status;\n\n\tif (buff_size == 0 || !buff)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);\n\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);\n\tstatus = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,\n\t\t\t\t cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW\n * @hw: pointer to the hw struct\n * @start_agent: True if DCBx Agent needs to be Started\n *\t\t\t\tFalse if DCBx Agent needs to be Stopped\n * @cmd_details: pointer to command details structure or NULL\n *\n * Start/Stop the embedded dcbx Agent\n **/\nenum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,\n\t\t\t\tbool start_agent,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_lldp_stop_start_specific_agent *cmd =\n\t\t(struct i40e_aqc_lldp_stop_start_specific_agent *)\n\t\t\t\t&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\ti40e_aqc_opc_lldp_stop_start_spec_agent);\n\n\tif (start_agent)\n\t\tcmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_add_udp_tunnel\n * @hw: pointer to the hw struct\n * @udp_port: the UDP port to add\n * @header_len: length of the tunneling header length in DWords\n * @protocol_index: protocol index type\n * @filter_index: pointer to filter index\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,\n\t\t\t\tu16 udp_port, u8 protocol_index,\n\t\t\t\tu8 *filter_index,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_udp_tunnel *cmd =\n\t\t(struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;\n\tstruct i40e_aqc_del_udp_tunnel_completion *resp =\n\t\t(struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);\n\n\tcmd->udp_port = CPU_TO_LE16(udp_port);\n\tcmd->protocol_type = protocol_index;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (!status && filter_index)\n\t\t*filter_index = resp->index;\n\n\treturn status;\n}\n\n/**\n * i40e_aq_del_udp_tunnel\n * @hw: pointer to the hw struct\n * @index: filter index\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_remove_udp_tunnel *cmd =\n\t\t(struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);\n\n\tcmd->index = index;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_get_switch_resource_alloc (0x0204)\n * @hw: pointer to the hw struct\n * @num_entries: pointer to u8 to store the number of resource entries returned\n * @buf: pointer to a user supplied buffer. This buffer must be large enough\n * to store the resource information for all resource types. Each\n * resource type is a i40e_aqc_switch_resource_alloc_data structure.\n * @count: size, in bytes, of the buffer provided\n * @cmd_details: pointer to command details structure or NULL\n *\n * Query the resources allocated to a function.\n **/\nenum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,\n\t\t\tu8 *num_entries,\n\t\t\tstruct i40e_aqc_switch_resource_alloc_element_resp *buf,\n\t\t\tu16 count,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_get_switch_resource_alloc *cmd_resp =\n\t\t(struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw;\n\tenum i40e_status_code status;\n\tu16 length = count * sizeof(*buf);\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\ti40e_aqc_opc_get_switch_resource_alloc);\n\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);\n\tif (length > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tstatus = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);\n\n\tif (!status && num_entries)\n\t\t*num_entries = cmd_resp->num_entries;\n\n\treturn status;\n}\n\n/**\n * i40e_aq_delete_element - Delete switch element\n * @hw: pointer to the hw struct\n * @seid: the SEID to delete from the switch\n * @cmd_details: pointer to command details structure or NULL\n *\n * This deletes a switch element from the switch.\n **/\nenum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_switch_seid *cmd =\n\t\t(struct i40e_aqc_switch_seid *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (seid == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);\n\n\tcmd->seid = CPU_TO_LE16(seid);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40_aq_add_pvirt - Instantiate a Port Virtualizer on a port\n * @hw: pointer to the hw struct\n * @flags: component flags\n * @mac_seid: uplink seid (MAC SEID)\n * @vsi_seid: connected vsi seid\n * @ret_seid: seid of create pv component\n *\n * This instantiates an i40e port virtualizer with specified flags.\n * Depending on specified flags the port virtualizer can act as a\n * 802.1Qbr port virtualizer or a 802.1Qbg S-component.\n */\nenum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,\n\t\t\t\t u16 mac_seid, u16 vsi_seid,\n\t\t\t\t u16 *ret_seid)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_update_pv *cmd =\n\t\t(struct i40e_aqc_add_update_pv *)&desc.params.raw;\n\tstruct i40e_aqc_add_update_pv_completion *resp =\n\t\t(struct i40e_aqc_add_update_pv_completion *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (vsi_seid == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv);\n\tcmd->command_flags = CPU_TO_LE16(flags);\n\tcmd->uplink_seid = CPU_TO_LE16(mac_seid);\n\tcmd->connected_seid = CPU_TO_LE16(vsi_seid);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);\n\tif (!status && ret_seid)\n\t\t*ret_seid = LE16_TO_CPU(resp->pv_seid);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_add_tag - Add an S/E-tag\n * @hw: pointer to the hw struct\n * @direct_to_queue: should s-tag direct flow to a specific queue\n * @vsi_seid: VSI SEID to use this tag\n * @tag: value of the tag\n * @queue_num: queue number, only valid is direct_to_queue is true\n * @tags_used: return value, number of tags in use by this PF\n * @tags_free: return value, number of unallocated tags\n * @cmd_details: pointer to command details structure or NULL\n *\n * This associates an S- or E-tag to a VSI in the switch complex. It returns\n * the number of tags allocated by the PF, and the number of unallocated\n * tags available.\n **/\nenum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,\n\t\t\t\tu16 vsi_seid, u16 tag, u16 queue_num,\n\t\t\t\tu16 *tags_used, u16 *tags_free,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_tag *cmd =\n\t\t(struct i40e_aqc_add_tag *)&desc.params.raw;\n\tstruct i40e_aqc_add_remove_tag_completion *resp =\n\t\t(struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (vsi_seid == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag);\n\n\tcmd->seid = CPU_TO_LE16(vsi_seid);\n\tcmd->tag = CPU_TO_LE16(tag);\n\tif (direct_to_queue) {\n\t\tcmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE);\n\t\tcmd->queue_number = CPU_TO_LE16(queue_num);\n\t}\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (!status) {\n\t\tif (tags_used != NULL)\n\t\t\t*tags_used = LE16_TO_CPU(resp->tags_used);\n\t\tif (tags_free != NULL)\n\t\t\t*tags_free = LE16_TO_CPU(resp->tags_free);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_remove_tag - Remove an S- or E-tag\n * @hw: pointer to the hw struct\n * @vsi_seid: VSI SEID this tag is associated with\n * @tag: value of the S-tag to delete\n * @tags_used: return value, number of tags in use by this PF\n * @tags_free: return value, number of unallocated tags\n * @cmd_details: pointer to command details structure or NULL\n *\n * This deletes an S- or E-tag from a VSI in the switch complex. It returns\n * the number of tags allocated by the PF, and the number of unallocated\n * tags available.\n **/\nenum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,\n\t\t\t\tu16 tag, u16 *tags_used, u16 *tags_free,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_remove_tag *cmd =\n\t\t(struct i40e_aqc_remove_tag *)&desc.params.raw;\n\tstruct i40e_aqc_add_remove_tag_completion *resp =\n\t\t(struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (vsi_seid == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag);\n\n\tcmd->seid = CPU_TO_LE16(vsi_seid);\n\tcmd->tag = CPU_TO_LE16(tag);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (!status) {\n\t\tif (tags_used != NULL)\n\t\t\t*tags_used = LE16_TO_CPU(resp->tags_used);\n\t\tif (tags_free != NULL)\n\t\t\t*tags_free = LE16_TO_CPU(resp->tags_free);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_add_mcast_etag - Add a multicast E-tag\n * @hw: pointer to the hw struct\n * @pv_seid: Port Virtualizer of this SEID to associate E-tag with\n * @etag: value of E-tag to add\n * @num_tags_in_buf: number of unicast E-tags in indirect buffer\n * @buf: address of indirect buffer\n * @tags_used: return value, number of E-tags in use by this port\n * @tags_free: return value, number of unallocated M-tags\n * @cmd_details: pointer to command details structure or NULL\n *\n * This associates a multicast E-tag to a port virtualizer. It will return\n * the number of tags allocated by the PF, and the number of unallocated\n * tags available.\n *\n * The indirect buffer pointed to by buf is a list of 2-byte E-tags,\n * num_tags_in_buf long.\n **/\nenum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid,\n\t\t\t\tu16 etag, u8 num_tags_in_buf, void *buf,\n\t\t\t\tu16 *tags_used, u16 *tags_free,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_remove_mcast_etag *cmd =\n\t\t(struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;\n\tstruct i40e_aqc_add_remove_mcast_etag_completion *resp =\n\t (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;\n\tenum i40e_status_code status;\n\tu16 length = sizeof(u16) * num_tags_in_buf;\n\n\tif ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0))\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_add_multicast_etag);\n\n\tcmd->pv_seid = CPU_TO_LE16(pv_seid);\n\tcmd->etag = CPU_TO_LE16(etag);\n\tcmd->num_unicast_etags = num_tags_in_buf;\n\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tif (length > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tstatus = i40e_asq_send_command(hw, &desc, buf, length, cmd_details);\n\n\tif (!status) {\n\t\tif (tags_used != NULL)\n\t\t\t*tags_used = LE16_TO_CPU(resp->mcast_etags_used);\n\t\tif (tags_free != NULL)\n\t\t\t*tags_free = LE16_TO_CPU(resp->mcast_etags_free);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_remove_mcast_etag - Remove a multicast E-tag\n * @hw: pointer to the hw struct\n * @pv_seid: Port Virtualizer SEID this M-tag is associated with\n * @etag: value of the E-tag to remove\n * @tags_used: return value, number of tags in use by this port\n * @tags_free: return value, number of unallocated tags\n * @cmd_details: pointer to command details structure or NULL\n *\n * This deletes an E-tag from the port virtualizer. It will return\n * the number of tags allocated by the port, and the number of unallocated\n * tags available.\n **/\nenum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid,\n\t\t\t\tu16 etag, u16 *tags_used, u16 *tags_free,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_remove_mcast_etag *cmd =\n\t\t(struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw;\n\tstruct i40e_aqc_add_remove_mcast_etag_completion *resp =\n\t (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\n\tif (pv_seid == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_remove_multicast_etag);\n\n\tcmd->pv_seid = CPU_TO_LE16(pv_seid);\n\tcmd->etag = CPU_TO_LE16(etag);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (!status) {\n\t\tif (tags_used != NULL)\n\t\t\t*tags_used = LE16_TO_CPU(resp->mcast_etags_used);\n\t\tif (tags_free != NULL)\n\t\t\t*tags_free = LE16_TO_CPU(resp->mcast_etags_free);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_update_tag - Update an S/E-tag\n * @hw: pointer to the hw struct\n * @vsi_seid: VSI SEID using this S-tag\n * @old_tag: old tag value\n * @new_tag: new tag value\n * @tags_used: return value, number of tags in use by this PF\n * @tags_free: return value, number of unallocated tags\n * @cmd_details: pointer to command details structure or NULL\n *\n * This updates the value of the tag currently attached to this VSI\n * in the switch complex. It will return the number of tags allocated\n * by the PF, and the number of unallocated tags available.\n **/\nenum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,\n\t\t\t\tu16 old_tag, u16 new_tag, u16 *tags_used,\n\t\t\t\tu16 *tags_free,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_update_tag *cmd =\n\t\t(struct i40e_aqc_update_tag *)&desc.params.raw;\n\tstruct i40e_aqc_update_tag_completion *resp =\n\t\t(struct i40e_aqc_update_tag_completion *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (vsi_seid == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag);\n\n\tcmd->seid = CPU_TO_LE16(vsi_seid);\n\tcmd->old_tag = CPU_TO_LE16(old_tag);\n\tcmd->new_tag = CPU_TO_LE16(new_tag);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (!status) {\n\t\tif (tags_used != NULL)\n\t\t\t*tags_used = LE16_TO_CPU(resp->tags_used);\n\t\tif (tags_free != NULL)\n\t\t\t*tags_free = LE16_TO_CPU(resp->tags_free);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs\n * @hw: pointer to the hw struct\n * @tcmap: TC map for request/release any ignore PFC condition\n * @request: request or release ignore PFC condition\n * @tcmap_ret: return TCs for which PFC is currently ignored\n * @cmd_details: pointer to command details structure or NULL\n *\n * This sends out request/release to ignore PFC condition for a TC.\n * It will return the TCs for which PFC is currently ignored.\n **/\nenum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap,\n\t\t\t\tbool request, u8 *tcmap_ret,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_pfc_ignore *cmd_resp =\n\t\t(struct i40e_aqc_pfc_ignore *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc);\n\n\tif (request)\n\t\tcmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET;\n\n\tcmd_resp->tc_bitmap = tcmap;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (!status) {\n\t\tif (tcmap_ret != NULL)\n\t\t\t*tcmap_ret = cmd_resp->tc_bitmap;\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_dcb_updated - DCB Updated Command\n * @hw: pointer to the hw struct\n * @cmd_details: pointer to command details structure or NULL\n *\n * When LLDP is handled in PF this command is used by the PF\n * to notify EMP that a DCB setting is modified.\n * When LLDP is handled in EMP this command is used by the PF\n * to notify EMP whenever one of the following parameters get\n * modified:\n * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA\n * - PCIRTT in PRTDCB_GENC.PCIRTT\n * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME.\n * EMP will return when the shared RPB settings have been\n * recomputed and modified. The retval field in the descriptor\n * will be set to 0 when RPB is modified.\n **/\nenum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch.\n * @hw: pointer to the hw struct\n * @seid: defines the SEID of the switch for which the stats are requested\n * @vlan_id: the VLAN ID for which the statistics are requested\n * @stat_index: index of the statistics counters block assigned to this VLAN\n * @cmd_details: pointer to command details structure or NULL\n *\n * XL710 supports 128 smonVlanStats counters.This command is used to\n * allocate a set of smonVlanStats counters to a specific VLAN in a specific\n * switch.\n **/\nenum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,\n\t\t\t\tu16 vlan_id, u16 *stat_index,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_remove_statistics *cmd_resp =\n\t\t(struct i40e_aqc_add_remove_statistics *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif ((seid == 0) || (stat_index == NULL))\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics);\n\n\tcmd_resp->seid = CPU_TO_LE16(seid);\n\tcmd_resp->vlan = CPU_TO_LE16(vlan_id);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (!status && stat_index)\n\t\t*stat_index = LE16_TO_CPU(cmd_resp->stat_index);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch.\n * @hw: pointer to the hw struct\n * @seid: defines the SEID of the switch for which the stats are requested\n * @vlan_id: the VLAN ID for which the statistics are requested\n * @stat_index: index of the statistics counters block assigned to this VLAN\n * @cmd_details: pointer to command details structure or NULL\n *\n * XL710 supports 128 smonVlanStats counters.This command is used to\n * deallocate a set of smonVlanStats counters to a specific VLAN in a specific\n * switch.\n **/\nenum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,\n\t\t\t\tu16 vlan_id, u16 stat_index,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_remove_statistics *cmd =\n\t\t(struct i40e_aqc_add_remove_statistics *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (seid == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_remove_statistics);\n\n\tcmd->seid = CPU_TO_LE16(seid);\n\tcmd->vlan = CPU_TO_LE16(vlan_id);\n\tcmd->stat_index = CPU_TO_LE16(stat_index);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_set_port_parameters - set physical port parameters.\n * @hw: pointer to the hw struct\n * @bad_frame_vsi: defines the VSI to which bad frames are forwarded\n * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI\n * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded\n * @double_vlan: if set double VLAN is enabled\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,\n\t\t\t\tu16 bad_frame_vsi, bool save_bad_pac,\n\t\t\t\tbool pad_short_pac, bool double_vlan,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aqc_set_port_parameters *cmd;\n\tenum i40e_status_code status;\n\tstruct i40e_aq_desc desc;\n\tu16 command_flags = 0;\n\n\tcmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_set_port_parameters);\n\n\tcmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi);\n\tif (save_bad_pac)\n\t\tcommand_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS;\n\tif (pad_short_pac)\n\t\tcommand_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS;\n\tif (double_vlan)\n\t\tcommand_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA;\n\tcmd->command_flags = CPU_TO_LE16(command_flags);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler\n * @hw: pointer to the hw struct\n * @seid: seid for the physical port/switching component/vsi\n * @buff: Indirect buffer to hold data parameters and response\n * @buff_size: Indirect buffer size\n * @opcode: Tx scheduler AQ command opcode\n * @cmd_details: pointer to command details structure or NULL\n *\n * Generic command handler for Tx scheduler AQ commands\n **/\nstatic enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,\n\t\t\t\tvoid *buff, u16 buff_size,\n\t\t\t\t enum i40e_admin_queue_opc opcode,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_tx_sched_ind *cmd =\n\t\t(struct i40e_aqc_tx_sched_ind *)&desc.params.raw;\n\tenum i40e_status_code status;\n\tbool cmd_param_flag = false;\n\n\tswitch (opcode) {\n\tcase i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:\n\tcase i40e_aqc_opc_configure_vsi_tc_bw:\n\tcase i40e_aqc_opc_enable_switching_comp_ets:\n\tcase i40e_aqc_opc_modify_switching_comp_ets:\n\tcase i40e_aqc_opc_disable_switching_comp_ets:\n\tcase i40e_aqc_opc_configure_switching_comp_ets_bw_limit:\n\tcase i40e_aqc_opc_configure_switching_comp_bw_config:\n\t\tcmd_param_flag = true;\n\t\tbreak;\n\tcase i40e_aqc_opc_query_vsi_bw_config:\n\tcase i40e_aqc_opc_query_vsi_ets_sla_config:\n\tcase i40e_aqc_opc_query_switching_comp_ets_config:\n\tcase i40e_aqc_opc_query_port_ets_config:\n\tcase i40e_aqc_opc_query_switching_comp_bw_config:\n\t\tcmd_param_flag = false;\n\t\tbreak;\n\tdefault:\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\ti40e_fill_default_direct_cmd_desc(&desc, opcode);\n\n\t/* Indirect command */\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);\n\tif (cmd_param_flag)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);\n\tif (buff_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tdesc.datalen = CPU_TO_LE16(buff_size);\n\n\tcmd->vsi_seid = CPU_TO_LE16(seid);\n\n\tstatus = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit\n * @hw: pointer to the hw struct\n * @seid: VSI seid\n * @credit: BW limit credits (0 = disabled)\n * @max_credit: Max BW limit credits\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,\n\t\t\t\tu16 seid, u16 credit, u8 max_credit,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_configure_vsi_bw_limit *cmd =\n\t\t(struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_configure_vsi_bw_limit);\n\n\tcmd->vsi_seid = CPU_TO_LE16(seid);\n\tcmd->credit = CPU_TO_LE16(credit);\n\tcmd->max_credit = max_credit;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit\n * @hw: pointer to the hw struct\n * @seid: switching component seid\n * @credit: BW limit credits (0 = disabled)\n * @max_bw: Max BW limit credits\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,\n\t\t\t\tu16 seid, u16 credit, u8 max_bw,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_configure_switching_comp_bw_limit *cmd =\n\t (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\ti40e_aqc_opc_configure_switching_comp_bw_limit);\n\n\tcmd->seid = CPU_TO_LE16(seid);\n\tcmd->credit = CPU_TO_LE16(credit);\n\tcmd->max_bw = max_bw;\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC\n * @hw: pointer to the hw struct\n * @seid: VSI seid\n * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,\n\t\t\tu16 seid,\n\t\t\tstruct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\treturn i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),\n\t\t\t\t i40e_aqc_opc_configure_vsi_ets_sla_bw_limit,\n\t\t\t\t cmd_details);\n}\n\n/**\n * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC\n * @hw: pointer to the hw struct\n * @seid: VSI seid\n * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,\n\t\t\tu16 seid,\n\t\t\tstruct i40e_aqc_configure_vsi_tc_bw_data *bw_data,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\treturn i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),\n\t\t\t\t i40e_aqc_opc_configure_vsi_tc_bw,\n\t\t\t\t cmd_details);\n}\n\n/**\n * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC\n * @hw: pointer to the hw struct\n * @seid: seid of the switching component\n * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(\n\tstruct i40e_hw *hw, u16 seid,\n\tstruct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,\n\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\treturn i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),\n\t\t\t i40e_aqc_opc_configure_switching_comp_ets_bw_limit,\n\t\t\t cmd_details);\n}\n\n/**\n * i40e_aq_query_vsi_bw_config - Query VSI BW configuration\n * @hw: pointer to the hw struct\n * @seid: seid of the VSI\n * @bw_data: Buffer to hold VSI BW configuration\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,\n\t\t\tu16 seid,\n\t\t\tstruct i40e_aqc_query_vsi_bw_config_resp *bw_data,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\treturn i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),\n\t\t\t\t i40e_aqc_opc_query_vsi_bw_config,\n\t\t\t\t cmd_details);\n}\n\n/**\n * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC\n * @hw: pointer to the hw struct\n * @seid: seid of the VSI\n * @bw_data: Buffer to hold VSI BW configuration per TC\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,\n\t\t\tu16 seid,\n\t\t\tstruct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\treturn i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),\n\t\t\t\t i40e_aqc_opc_query_vsi_ets_sla_config,\n\t\t\t\t cmd_details);\n}\n\n/**\n * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC\n * @hw: pointer to the hw struct\n * @seid: seid of the switching component\n * @bw_data: Buffer to hold switching component's per TC BW config\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,\n\t\tu16 seid,\n\t\tstruct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,\n\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\treturn i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),\n\t\t\t\t i40e_aqc_opc_query_switching_comp_ets_config,\n\t\t\t\t cmd_details);\n}\n\n/**\n * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration\n * @hw: pointer to the hw struct\n * @seid: seid of the VSI or switching component connected to Physical Port\n * @bw_data: Buffer to hold current ETS configuration for the Physical Port\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,\n\t\t\tu16 seid,\n\t\t\tstruct i40e_aqc_query_port_ets_config_resp *bw_data,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\treturn i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),\n\t\t\t\t i40e_aqc_opc_query_port_ets_config,\n\t\t\t\t cmd_details);\n}\n\n/**\n * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration\n * @hw: pointer to the hw struct\n * @seid: seid of the switching component\n * @bw_data: Buffer to hold switching component's BW configuration\n * @cmd_details: pointer to command details structure or NULL\n **/\nenum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,\n\t\tu16 seid,\n\t\tstruct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,\n\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\treturn i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),\n\t\t\t\t i40e_aqc_opc_query_switching_comp_bw_config,\n\t\t\t\t cmd_details);\n}\n\n/**\n * i40e_validate_filter_settings\n * @hw: pointer to the hardware structure\n * @settings: Filter control settings\n *\n * Check and validate the filter control settings passed.\n * The function checks for the valid filter/context sizes being\n * passed for FCoE and PE.\n *\n * Returns I40E_SUCCESS if the values passed are valid and within\n * range else returns an error.\n **/\nSTATIC enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_filter_control_settings *settings)\n{\n\tu32 fcoe_cntx_size, fcoe_filt_size;\n\tu32 pe_cntx_size, pe_filt_size;\n\tu32 fcoe_fmax;\n\n\tu32 val;\n\n\t/* Validate FCoE settings passed */\n\tswitch (settings->fcoe_filt_num) {\n\tcase I40E_HASH_FILTER_SIZE_1K:\n\tcase I40E_HASH_FILTER_SIZE_2K:\n\tcase I40E_HASH_FILTER_SIZE_4K:\n\tcase I40E_HASH_FILTER_SIZE_8K:\n\tcase I40E_HASH_FILTER_SIZE_16K:\n\tcase I40E_HASH_FILTER_SIZE_32K:\n\t\tfcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;\n\t\tfcoe_filt_size <<= (u32)settings->fcoe_filt_num;\n\t\tbreak;\n\tdefault:\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\tswitch (settings->fcoe_cntx_num) {\n\tcase I40E_DMA_CNTX_SIZE_512:\n\tcase I40E_DMA_CNTX_SIZE_1K:\n\tcase I40E_DMA_CNTX_SIZE_2K:\n\tcase I40E_DMA_CNTX_SIZE_4K:\n\t\tfcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;\n\t\tfcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;\n\t\tbreak;\n\tdefault:\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\t/* Validate PE settings passed */\n\tswitch (settings->pe_filt_num) {\n\tcase I40E_HASH_FILTER_SIZE_1K:\n\tcase I40E_HASH_FILTER_SIZE_2K:\n\tcase I40E_HASH_FILTER_SIZE_4K:\n\tcase I40E_HASH_FILTER_SIZE_8K:\n\tcase I40E_HASH_FILTER_SIZE_16K:\n\tcase I40E_HASH_FILTER_SIZE_32K:\n\tcase I40E_HASH_FILTER_SIZE_64K:\n\tcase I40E_HASH_FILTER_SIZE_128K:\n\tcase I40E_HASH_FILTER_SIZE_256K:\n\tcase I40E_HASH_FILTER_SIZE_512K:\n\tcase I40E_HASH_FILTER_SIZE_1M:\n\t\tpe_filt_size = I40E_HASH_FILTER_BASE_SIZE;\n\t\tpe_filt_size <<= (u32)settings->pe_filt_num;\n\t\tbreak;\n\tdefault:\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\tswitch (settings->pe_cntx_num) {\n\tcase I40E_DMA_CNTX_SIZE_512:\n\tcase I40E_DMA_CNTX_SIZE_1K:\n\tcase I40E_DMA_CNTX_SIZE_2K:\n\tcase I40E_DMA_CNTX_SIZE_4K:\n\tcase I40E_DMA_CNTX_SIZE_8K:\n\tcase I40E_DMA_CNTX_SIZE_16K:\n\tcase I40E_DMA_CNTX_SIZE_32K:\n\tcase I40E_DMA_CNTX_SIZE_64K:\n\tcase I40E_DMA_CNTX_SIZE_128K:\n\tcase I40E_DMA_CNTX_SIZE_256K:\n\t\tpe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;\n\t\tpe_cntx_size <<= (u32)settings->pe_cntx_num;\n\t\tbreak;\n\tdefault:\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\t/* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */\n\tval = rd32(hw, I40E_GLHMC_FCOEFMAX);\n\tfcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)\n\t\t >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;\n\tif (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)\n\t\treturn I40E_ERR_INVALID_SIZE;\n\n\treturn I40E_SUCCESS;\n}\n\n/**\n * i40e_set_filter_control\n * @hw: pointer to the hardware structure\n * @settings: Filter control settings\n *\n * Set the Queue Filters for PE/FCoE and enable filters required\n * for a single PF. It is expected that these settings are programmed\n * at the driver initialization time.\n **/\nenum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_filter_control_settings *settings)\n{\n\tenum i40e_status_code ret = I40E_SUCCESS;\n\tu32 hash_lut_size = 0;\n\tu32 val;\n\n\tif (!settings)\n\t\treturn I40E_ERR_PARAM;\n\n\t/* Validate the input settings */\n\tret = i40e_validate_filter_settings(hw, settings);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Read the PF Queue Filter control register */\n\tval = rd32(hw, I40E_PFQF_CTL_0);\n\n\t/* Program required PE hash buckets for the PF */\n\tval &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;\n\tval |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &\n\t\tI40E_PFQF_CTL_0_PEHSIZE_MASK;\n\t/* Program required PE contexts for the PF */\n\tval &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;\n\tval |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &\n\t\tI40E_PFQF_CTL_0_PEDSIZE_MASK;\n\n\t/* Program required FCoE hash buckets for the PF */\n\tval &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;\n\tval |= ((u32)settings->fcoe_filt_num <<\n\t\t\tI40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &\n\t\tI40E_PFQF_CTL_0_PFFCHSIZE_MASK;\n\t/* Program required FCoE DDP contexts for the PF */\n\tval &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;\n\tval |= ((u32)settings->fcoe_cntx_num <<\n\t\t\tI40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &\n\t\tI40E_PFQF_CTL_0_PFFCDSIZE_MASK;\n\n\t/* Program Hash LUT size for the PF */\n\tval &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;\n\tif (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)\n\t\thash_lut_size = 1;\n\tval |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &\n\t\tI40E_PFQF_CTL_0_HASHLUTSIZE_MASK;\n\n\t/* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */\n\tif (settings->enable_fdir)\n\t\tval |= I40E_PFQF_CTL_0_FD_ENA_MASK;\n\tif (settings->enable_ethtype)\n\t\tval |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;\n\tif (settings->enable_macvlan)\n\t\tval |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;\n\n\twr32(hw, I40E_PFQF_CTL_0, val);\n\n\treturn I40E_SUCCESS;\n}\n\n/**\n * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter\n * @hw: pointer to the hw struct\n * @mac_addr: MAC address to use in the filter\n * @ethtype: Ethertype to use in the filter\n * @flags: Flags that needs to be applied to the filter\n * @vsi_seid: seid of the control VSI\n * @queue: VSI queue number to send the packet to\n * @is_add: Add control packet filter if True else remove\n * @stats: Structure to hold information on control filter counts\n * @cmd_details: pointer to command details structure or NULL\n *\n * This command will Add or Remove control packet filter for a control VSI.\n * In return it will update the total number of perfect filter count in\n * the stats member.\n **/\nenum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,\n\t\t\t\tu8 *mac_addr, u16 ethtype, u16 flags,\n\t\t\t\tu16 vsi_seid, u16 queue, bool is_add,\n\t\t\t\tstruct i40e_control_filter_stats *stats,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_remove_control_packet_filter *cmd =\n\t\t(struct i40e_aqc_add_remove_control_packet_filter *)\n\t\t&desc.params.raw;\n\tstruct i40e_aqc_add_remove_control_packet_filter_completion *resp =\n\t\t(struct i40e_aqc_add_remove_control_packet_filter_completion *)\n\t\t&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (vsi_seid == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\tif (is_add) {\n\t\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\ti40e_aqc_opc_add_control_packet_filter);\n\t\tcmd->queue = CPU_TO_LE16(queue);\n\t} else {\n\t\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\ti40e_aqc_opc_remove_control_packet_filter);\n\t}\n\n\tif (mac_addr)\n\t\ti40e_memcpy(cmd->mac, mac_addr, I40E_ETH_LENGTH_OF_ADDRESS,\n\t\t\t I40E_NONDMA_TO_NONDMA);\n\n\tcmd->etype = CPU_TO_LE16(ethtype);\n\tcmd->flags = CPU_TO_LE16(flags);\n\tcmd->seid = CPU_TO_LE16(vsi_seid);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\tif (!status && stats) {\n\t\tstats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used);\n\t\tstats->etype_used = LE16_TO_CPU(resp->etype_used);\n\t\tstats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free);\n\t\tstats->etype_free = LE16_TO_CPU(resp->etype_free);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_add_cloud_filters\n * @hw: pointer to the hardware structure\n * @seid: VSI seid to add cloud filters from\n * @filters: Buffer which contains the filters to be added\n * @filter_count: number of filters contained in the buffer\n *\n * Set the cloud filters for a given VSI. The contents of the\n * i40e_aqc_add_remove_cloud_filters_element_data are filled\n * in by the caller of the function.\n *\n **/\nenum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,\n\tu16 seid,\n\tstruct i40e_aqc_add_remove_cloud_filters_element_data *filters,\n\tu8 filter_count)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_remove_cloud_filters *cmd =\n\t(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;\n\tu16 buff_len;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_add_cloud_filters);\n\n\tbuff_len = filter_count * sizeof(*filters);\n\tdesc.datalen = CPU_TO_LE16(buff_len);\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tcmd->num_filters = filter_count;\n\tcmd->seid = CPU_TO_LE16(seid);\n\n\tstatus = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_remove_cloud_filters\n * @hw: pointer to the hardware structure\n * @seid: VSI seid to remove cloud filters from\n * @filters: Buffer which contains the filters to be removed\n * @filter_count: number of filters contained in the buffer\n *\n * Remove the cloud filters for a given VSI. The contents of the\n * i40e_aqc_add_remove_cloud_filters_element_data are filled\n * in by the caller of the function.\n *\n **/\nenum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,\n\t\tu16 seid,\n\t\tstruct i40e_aqc_add_remove_cloud_filters_element_data *filters,\n\t\tu8 filter_count)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_remove_cloud_filters *cmd =\n\t(struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;\n\tenum i40e_status_code status;\n\tu16 buff_len;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_remove_cloud_filters);\n\n\tbuff_len = filter_count * sizeof(*filters);\n\tdesc.datalen = CPU_TO_LE16(buff_len);\n\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tcmd->num_filters = filter_count;\n\tcmd->seid = CPU_TO_LE16(seid);\n\n\tstatus = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_alternate_write\n * @hw: pointer to the hardware structure\n * @reg_addr0: address of first dword to be read\n * @reg_val0: value to be written under 'reg_addr0'\n * @reg_addr1: address of second dword to be read\n * @reg_val1: value to be written under 'reg_addr1'\n *\n * Write one or two dwords to alternate structure. Fields are indicated\n * by 'reg_addr0' and 'reg_addr1' register numbers.\n *\n **/\nenum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,\n\t\t\t\tu32 reg_addr0, u32 reg_val0,\n\t\t\t\tu32 reg_addr1, u32 reg_val1)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_alternate_write *cmd_resp =\n\t\t(struct i40e_aqc_alternate_write *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write);\n\tcmd_resp->address0 = CPU_TO_LE32(reg_addr0);\n\tcmd_resp->address1 = CPU_TO_LE32(reg_addr1);\n\tcmd_resp->data0 = CPU_TO_LE32(reg_val0);\n\tcmd_resp->data1 = CPU_TO_LE32(reg_val1);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_alternate_write_indirect\n * @hw: pointer to the hardware structure\n * @addr: address of a first register to be modified\n * @dw_count: number of alternate structure fields to write\n * @buffer: pointer to the command buffer\n *\n * Write 'dw_count' dwords from 'buffer' to alternate structure\n * starting at 'addr'.\n *\n **/\nenum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,\n\t\t\t\tu32 addr, u32 dw_count, void *buffer)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_alternate_ind_write *cmd_resp =\n\t\t(struct i40e_aqc_alternate_ind_write *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (buffer == NULL)\n\t\treturn I40E_ERR_PARAM;\n\n\t/* Indirect command */\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_alternate_write_indirect);\n\n\tdesc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);\n\tdesc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);\n\tif (dw_count > (I40E_AQ_LARGE_BUF/4))\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tcmd_resp->address = CPU_TO_LE32(addr);\n\tcmd_resp->length = CPU_TO_LE32(dw_count);\n\tcmd_resp->addr_high = CPU_TO_LE32(I40E_HI_WORD((u64)buffer));\n\tcmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));\n\n\tstatus = i40e_asq_send_command(hw, &desc, buffer,\n\t\t\t\t I40E_LO_DWORD(4*dw_count), NULL);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_alternate_read\n * @hw: pointer to the hardware structure\n * @reg_addr0: address of first dword to be read\n * @reg_val0: pointer for data read from 'reg_addr0'\n * @reg_addr1: address of second dword to be read\n * @reg_val1: pointer for data read from 'reg_addr1'\n *\n * Read one or two dwords from alternate structure. Fields are indicated\n * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer\n * is not passed then only register at 'reg_addr0' is read.\n *\n **/\nenum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,\n\t\t\t\tu32 reg_addr0, u32 *reg_val0,\n\t\t\t\tu32 reg_addr1, u32 *reg_val1)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_alternate_write *cmd_resp =\n\t\t(struct i40e_aqc_alternate_write *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (reg_val0 == NULL)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);\n\tcmd_resp->address0 = CPU_TO_LE32(reg_addr0);\n\tcmd_resp->address1 = CPU_TO_LE32(reg_addr1);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);\n\n\tif (status == I40E_SUCCESS) {\n\t\t*reg_val0 = LE32_TO_CPU(cmd_resp->data0);\n\n\t\tif (reg_val1 != NULL)\n\t\t\t*reg_val1 = LE32_TO_CPU(cmd_resp->data1);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_aq_alternate_read_indirect\n * @hw: pointer to the hardware structure\n * @addr: address of the alternate structure field\n * @dw_count: number of alternate structure fields to read\n * @buffer: pointer to the command buffer\n *\n * Read 'dw_count' dwords from alternate structure starting at 'addr' and\n * place them in 'buffer'. The buffer should be allocated by caller.\n *\n **/\nenum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,\n\t\t\t\tu32 addr, u32 dw_count, void *buffer)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_alternate_ind_write *cmd_resp =\n\t\t(struct i40e_aqc_alternate_ind_write *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (buffer == NULL)\n\t\treturn I40E_ERR_PARAM;\n\n\t/* Indirect command */\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\ti40e_aqc_opc_alternate_read_indirect);\n\n\tdesc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD);\n\tdesc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);\n\tif (dw_count > (I40E_AQ_LARGE_BUF/4))\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tcmd_resp->address = CPU_TO_LE32(addr);\n\tcmd_resp->length = CPU_TO_LE32(dw_count);\n\tcmd_resp->addr_high = CPU_TO_LE32(I40E_HI_DWORD((u64)buffer));\n\tcmd_resp->addr_low = CPU_TO_LE32(I40E_LO_DWORD((u64)buffer));\n\n\tstatus = i40e_asq_send_command(hw, &desc, buffer,\n\t\t\t\t I40E_LO_DWORD(4*dw_count), NULL);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_alternate_clear\n * @hw: pointer to the HW structure.\n *\n * Clear the alternate structures of the port from which the function\n * is called.\n *\n **/\nenum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw)\n{\n\tstruct i40e_aq_desc desc;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_alternate_clear_port);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_alternate_write_done\n * @hw: pointer to the HW structure.\n * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS\n * @reset_needed: indicates the SW should trigger GLOBAL reset\n *\n * Indicates to the FW that alternate structures have been changed.\n *\n **/\nenum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,\n\t\tu8 bios_mode, bool *reset_needed)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_alternate_write_done *cmd =\n\t\t(struct i40e_aqc_alternate_write_done *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\tif (reset_needed == NULL)\n\t\treturn I40E_ERR_PARAM;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_alternate_write_done);\n\n\tcmd->cmd_flags = CPU_TO_LE16(bios_mode);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);\n\tif (!status && reset_needed)\n\t\t*reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) &\n\t\t\t\t I40E_AQ_ALTERNATE_RESET_NEEDED) != 0);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_set_oem_mode\n * @hw: pointer to the HW structure.\n * @oem_mode: the OEM mode to be used\n *\n * Sets the device to a specific operating mode. Currently the only supported\n * mode is no_clp, which causes FW to refrain from using Alternate RAM.\n *\n **/\nenum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,\n\t\tu8 oem_mode)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_alternate_write_done *cmd =\n\t\t(struct i40e_aqc_alternate_write_done *)&desc.params.raw;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_alternate_set_mode);\n\n\tcmd->cmd_flags = CPU_TO_LE16(oem_mode);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_resume_port_tx\n * @hw: pointer to the hardware structure\n * @cmd_details: pointer to command details structure or NULL\n *\n * Resume port's Tx traffic\n **/\nenum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);\n\n\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n\n\treturn status;\n}\n\n/**\n * i40e_set_pci_config_data - store PCI bus info\n * @hw: pointer to hardware structure\n * @link_status: the link status word from PCI config space\n *\n * Stores the PCI bus info (speed, width, type) within the i40e_hw structure\n **/\nvoid i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)\n{\n\thw->bus.type = i40e_bus_type_pci_express;\n\n\tswitch (link_status & I40E_PCI_LINK_WIDTH) {\n\tcase I40E_PCI_LINK_WIDTH_1:\n\t\thw->bus.width = i40e_bus_width_pcie_x1;\n\t\tbreak;\n\tcase I40E_PCI_LINK_WIDTH_2:\n\t\thw->bus.width = i40e_bus_width_pcie_x2;\n\t\tbreak;\n\tcase I40E_PCI_LINK_WIDTH_4:\n\t\thw->bus.width = i40e_bus_width_pcie_x4;\n\t\tbreak;\n\tcase I40E_PCI_LINK_WIDTH_8:\n\t\thw->bus.width = i40e_bus_width_pcie_x8;\n\t\tbreak;\n\tdefault:\n\t\thw->bus.width = i40e_bus_width_unknown;\n\t\tbreak;\n\t}\n\n\tswitch (link_status & I40E_PCI_LINK_SPEED) {\n\tcase I40E_PCI_LINK_SPEED_2500:\n\t\thw->bus.speed = i40e_bus_speed_2500;\n\t\tbreak;\n\tcase I40E_PCI_LINK_SPEED_5000:\n\t\thw->bus.speed = i40e_bus_speed_5000;\n\t\tbreak;\n\tcase I40E_PCI_LINK_SPEED_8000:\n\t\thw->bus.speed = i40e_bus_speed_8000;\n\t\tbreak;\n\tdefault:\n\t\thw->bus.speed = i40e_bus_speed_unknown;\n\t\tbreak;\n\t}\n}\n\n/**\n * i40e_read_bw_from_alt_ram\n * @hw: pointer to the hardware structure\n * @max_bw: pointer for max_bw read\n * @min_bw: pointer for min_bw read\n * @min_valid: pointer for bool that is true if min_bw is a valid value\n * @max_valid: pointer for bool that is true if max_bw is a valid value\n *\n * Read bw from the alternate ram for the given pf\n **/\nenum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,\n\t\t\t\t\tu32 *max_bw, u32 *min_bw,\n\t\t\t\t\tbool *min_valid, bool *max_valid)\n{\n\tenum i40e_status_code status;\n\tu32 max_bw_addr, min_bw_addr;\n\n\t/* Calculate the address of the min/max bw registers */\n\tmax_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +\n\t\tI40E_ALT_STRUCT_MAX_BW_OFFSET +\n\t\t(I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);\n\tmin_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +\n\t\tI40E_ALT_STRUCT_MIN_BW_OFFSET +\n\t\t(I40E_ALT_STRUCT_DWORDS_PER_PF*hw->pf_id);\n\n\t/* Read the bandwidths from alt ram */\n\tstatus = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,\n\t\t\t\t\tmin_bw_addr, min_bw);\n\n\tif (*min_bw & I40E_ALT_BW_VALID_MASK)\n\t\t*min_valid = true;\n\telse\n\t\t*min_valid = false;\n\n\tif (*max_bw & I40E_ALT_BW_VALID_MASK)\n\t\t*max_valid = true;\n\telse\n\t\t*max_valid = false;\n\n\treturn status;\n}\n\n/**\n * i40e_aq_configure_partition_bw\n * @hw: pointer to the hardware structure\n * @bw_data: Buffer holding valid pfs and bw limits\n * @cmd_details: pointer to command details\n *\n * Configure partitions guaranteed/max bw\n **/\nenum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,\n\t\t\tstruct i40e_aqc_configure_partition_bw_data *bw_data,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tenum i40e_status_code status;\n\tstruct i40e_aq_desc desc;\n\tu16 bwd_size = sizeof(*bw_data);\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\ti40e_aqc_opc_configure_partition_bw);\n\n\t/* Indirect command */\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);\n\n\tif (bwd_size > I40E_AQ_LARGE_BUF)\n\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\n\tdesc.datalen = CPU_TO_LE16(bwd_size);\n\n\tstatus = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details);\n\n\treturn status;\n}\n#endif /* PF_DRIVER */\n#ifdef VF_DRIVER\n\n/**\n * i40e_aq_send_msg_to_pf\n * @hw: pointer to the hardware structure\n * @v_opcode: opcodes for VF-PF communication\n * @v_retval: return error code\n * @msg: pointer to the msg buffer\n * @msglen: msg length\n * @cmd_details: pointer to command details\n *\n * Send message to PF driver using admin queue. By default, this message\n * is sent asynchronously, i.e. i40e_asq_send_command() does not wait for\n * completion before returning.\n **/\nenum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,\n\t\t\t\tenum i40e_virtchnl_ops v_opcode,\n\t\t\t\tenum i40e_status_code v_retval,\n\t\t\t\tu8 *msg, u16 msglen,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_asq_cmd_details details;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);\n\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI);\n\tdesc.cookie_high = CPU_TO_LE32(v_opcode);\n\tdesc.cookie_low = CPU_TO_LE32(v_retval);\n\tif (msglen) {\n\t\tdesc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF\n\t\t\t\t\t\t| I40E_AQ_FLAG_RD));\n\t\tif (msglen > I40E_AQ_LARGE_BUF)\n\t\t\tdesc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);\n\t\tdesc.datalen = CPU_TO_LE16(msglen);\n\t}\n\tif (!cmd_details) {\n\t\ti40e_memset(&details, 0, sizeof(details), I40E_NONDMA_MEM);\n\t\tdetails.async = true;\n\t\tcmd_details = &details;\n\t}\n\tstatus = i40e_asq_send_command(hw, (struct i40e_aq_desc *)&desc, msg,\n\t\t\t\t msglen, cmd_details);\n\treturn status;\n}\n\n/**\n * i40e_vf_parse_hw_config\n * @hw: pointer to the hardware structure\n * @msg: pointer to the virtual channel VF resource structure\n *\n * Given a VF resource message from the PF, populate the hw struct\n * with appropriate information.\n **/\nvoid i40e_vf_parse_hw_config(struct i40e_hw *hw,\n\t\t\t struct i40e_virtchnl_vf_resource *msg)\n{\n\tstruct i40e_virtchnl_vsi_resource *vsi_res;\n\tint i;\n\n\tvsi_res = &msg->vsi_res[0];\n\n\thw->dev_caps.num_vsis = msg->num_vsis;\n\thw->dev_caps.num_rx_qp = msg->num_queue_pairs;\n\thw->dev_caps.num_tx_qp = msg->num_queue_pairs;\n\thw->dev_caps.num_msix_vectors_vf = msg->max_vectors;\n\thw->dev_caps.dcb = msg->vf_offload_flags &\n\t\t\t I40E_VIRTCHNL_VF_OFFLOAD_L2;\n\thw->dev_caps.fcoe = (msg->vf_offload_flags &\n\t\t\t I40E_VIRTCHNL_VF_OFFLOAD_FCOE) ? 1 : 0;\n\thw->dev_caps.iwarp = (msg->vf_offload_flags &\n\t\t\t I40E_VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;\n\tfor (i = 0; i < msg->num_vsis; i++) {\n\t\tif (vsi_res->vsi_type == I40E_VSI_SRIOV) {\n\t\t\ti40e_memcpy(hw->mac.perm_addr,\n\t\t\t\t vsi_res->default_mac_addr,\n\t\t\t\t I40E_ETH_LENGTH_OF_ADDRESS,\n\t\t\t\t I40E_NONDMA_TO_NONDMA);\n\t\t\ti40e_memcpy(hw->mac.addr, vsi_res->default_mac_addr,\n\t\t\t\t I40E_ETH_LENGTH_OF_ADDRESS,\n\t\t\t\t I40E_NONDMA_TO_NONDMA);\n\t\t}\n\t\tvsi_res++;\n\t}\n}\n\n/**\n * i40e_vf_reset\n * @hw: pointer to the hardware structure\n *\n * Send a VF_RESET message to the PF. Does not wait for response from PF\n * as none will be forthcoming. Immediately after calling this function,\n * the admin queue should be shut down and (optionally) reinitialized.\n **/\nenum i40e_status_code i40e_vf_reset(struct i40e_hw *hw)\n{\n\treturn i40e_aq_send_msg_to_pf(hw, I40E_VIRTCHNL_OP_RESET_VF,\n\t\t\t\t I40E_SUCCESS, NULL, 0, NULL);\n}\n#endif /* VF_DRIVER */\n" }, { "path": "drivers/net/i40e/base/i40e_dcb.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"i40e_adminq.h\"\n#include \"i40e_prototype.h\"\n#include \"i40e_dcb.h\"\n\n/**\n * i40e_get_dcbx_status\n * @hw: pointer to the hw struct\n * @status: Embedded DCBX Engine Status\n *\n * Get the DCBX status from the Firmware\n **/\nenum i40e_status_code i40e_get_dcbx_status(struct i40e_hw *hw, u16 *status)\n{\n\tu32 reg;\n\n\tif (!status)\n\t\treturn I40E_ERR_PARAM;\n\n\treg = rd32(hw, I40E_PRTDCB_GENS);\n\t*status = (u16)((reg & I40E_PRTDCB_GENS_DCBX_STATUS_MASK) >>\n\t\t\tI40E_PRTDCB_GENS_DCBX_STATUS_SHIFT);\n\n\treturn I40E_SUCCESS;\n}\n\n/**\n * i40e_parse_ieee_etscfg_tlv\n * @tlv: IEEE 802.1Qaz ETS CFG TLV\n * @dcbcfg: Local store to update ETS CFG data\n *\n * Parses IEEE 802.1Qaz ETS CFG TLV\n **/\nstatic void i40e_parse_ieee_etscfg_tlv(struct i40e_lldp_org_tlv *tlv,\n\t\t\t\t struct i40e_dcbx_config *dcbcfg)\n{\n\tstruct i40e_dcb_ets_config *etscfg;\n\tu8 *buf = tlv->tlvinfo;\n\tu16 offset = 0;\n\tu8 priority;\n\tint i;\n\n\t/* First Octet post subtype\n\t * --------------------------\n\t * |will-|CBS | Re- | Max |\n\t * |ing | |served| TCs |\n\t * --------------------------\n\t * |1bit | 1bit|3 bits|3bits|\n\t */\n\tetscfg = &dcbcfg->etscfg;\n\tetscfg->willing = (u8)((buf[offset] & I40E_IEEE_ETS_WILLING_MASK) >>\n\t\t\t I40E_IEEE_ETS_WILLING_SHIFT);\n\tetscfg->cbs = (u8)((buf[offset] & I40E_IEEE_ETS_CBS_MASK) >>\n\t\t\t I40E_IEEE_ETS_CBS_SHIFT);\n\tetscfg->maxtcs = (u8)((buf[offset] & I40E_IEEE_ETS_MAXTC_MASK) >>\n\t\t\t I40E_IEEE_ETS_MAXTC_SHIFT);\n\n\t/* Move offset to Priority Assignment Table */\n\toffset++;\n\n\t/* Priority Assignment Table (4 octets)\n\t * Octets:| 1 | 2 | 3 | 4 |\n\t * -----------------------------------------\n\t * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|\n\t * -----------------------------------------\n\t * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0|\n\t * -----------------------------------------\n\t */\n\tfor (i = 0; i < 4; i++) {\n\t\tpriority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_1_MASK) >>\n\t\t\t\tI40E_IEEE_ETS_PRIO_1_SHIFT);\n\t\tetscfg->prioritytable[i * 2] = priority;\n\t\tpriority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_0_MASK) >>\n\t\t\t\tI40E_IEEE_ETS_PRIO_0_SHIFT);\n\t\tetscfg->prioritytable[i * 2 + 1] = priority;\n\t\toffset++;\n\t}\n\n\t/* TC Bandwidth Table (8 octets)\n\t * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |\n\t * ---------------------------------\n\t * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|\n\t * ---------------------------------\n\t */\n\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)\n\t\tetscfg->tcbwtable[i] = buf[offset++];\n\n\t/* TSA Assignment Table (8 octets)\n\t * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |\n\t * ---------------------------------\n\t * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|\n\t * ---------------------------------\n\t */\n\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)\n\t\tetscfg->tsatable[i] = buf[offset++];\n}\n\n/**\n * i40e_parse_ieee_etsrec_tlv\n * @tlv: IEEE 802.1Qaz ETS REC TLV\n * @dcbcfg: Local store to update ETS REC data\n *\n * Parses IEEE 802.1Qaz ETS REC TLV\n **/\nstatic void i40e_parse_ieee_etsrec_tlv(struct i40e_lldp_org_tlv *tlv,\n\t\t\t\t struct i40e_dcbx_config *dcbcfg)\n{\n\tu8 *buf = tlv->tlvinfo;\n\tu16 offset = 0;\n\tu8 priority;\n\tint i;\n\n\t/* Move offset to priority table */\n\toffset++;\n\n\t/* Priority Assignment Table (4 octets)\n\t * Octets:| 1 | 2 | 3 | 4 |\n\t * -----------------------------------------\n\t * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|\n\t * -----------------------------------------\n\t * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0|\n\t * -----------------------------------------\n\t */\n\tfor (i = 0; i < 4; i++) {\n\t\tpriority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_1_MASK) >>\n\t\t\t\tI40E_IEEE_ETS_PRIO_1_SHIFT);\n\t\tdcbcfg->etsrec.prioritytable[i*2] = priority;\n\t\tpriority = (u8)((buf[offset] & I40E_IEEE_ETS_PRIO_0_MASK) >>\n\t\t\t\tI40E_IEEE_ETS_PRIO_0_SHIFT);\n\t\tdcbcfg->etsrec.prioritytable[i*2 + 1] = priority;\n\t\toffset++;\n\t}\n\n\t/* TC Bandwidth Table (8 octets)\n\t * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |\n\t * ---------------------------------\n\t * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|\n\t * ---------------------------------\n\t */\n\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)\n\t\tdcbcfg->etsrec.tcbwtable[i] = buf[offset++];\n\n\t/* TSA Assignment Table (8 octets)\n\t * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |\n\t * ---------------------------------\n\t * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7|\n\t * ---------------------------------\n\t */\n\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)\n\t\tdcbcfg->etsrec.tsatable[i] = buf[offset++];\n}\n\n/**\n * i40e_parse_ieee_pfccfg_tlv\n * @tlv: IEEE 802.1Qaz PFC CFG TLV\n * @dcbcfg: Local store to update PFC CFG data\n *\n * Parses IEEE 802.1Qaz PFC CFG TLV\n **/\nstatic void i40e_parse_ieee_pfccfg_tlv(struct i40e_lldp_org_tlv *tlv,\n\t\t\t\t struct i40e_dcbx_config *dcbcfg)\n{\n\tu8 *buf = tlv->tlvinfo;\n\n\t/* ----------------------------------------\n\t * |will-|MBC | Re- | PFC | PFC Enable |\n\t * |ing | |served| cap | |\n\t * -----------------------------------------\n\t * |1bit | 1bit|2 bits|4bits| 1 octet |\n\t */\n\tdcbcfg->pfc.willing = (u8)((buf[0] & I40E_IEEE_PFC_WILLING_MASK) >>\n\t\t\t\t I40E_IEEE_PFC_WILLING_SHIFT);\n\tdcbcfg->pfc.mbc = (u8)((buf[0] & I40E_IEEE_PFC_MBC_MASK) >>\n\t\t\t I40E_IEEE_PFC_MBC_SHIFT);\n\tdcbcfg->pfc.pfccap = (u8)((buf[0] & I40E_IEEE_PFC_CAP_MASK) >>\n\t\t\t\t I40E_IEEE_PFC_CAP_SHIFT);\n\tdcbcfg->pfc.pfcenable = buf[1];\n}\n\n/**\n * i40e_parse_ieee_app_tlv\n * @tlv: IEEE 802.1Qaz APP TLV\n * @dcbcfg: Local store to update APP PRIO data\n *\n * Parses IEEE 802.1Qaz APP PRIO TLV\n **/\nstatic void i40e_parse_ieee_app_tlv(struct i40e_lldp_org_tlv *tlv,\n\t\t\t\t struct i40e_dcbx_config *dcbcfg)\n{\n\tu16 typelength;\n\tu16 offset = 0;\n\tu16 length;\n\tint i = 0;\n\tu8 *buf;\n\n\ttypelength = I40E_NTOHS(tlv->typelength);\n\tlength = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>\n\t\t I40E_LLDP_TLV_LEN_SHIFT);\n\tbuf = tlv->tlvinfo;\n\n\t/* The App priority table starts 5 octets after TLV header */\n\tlength -= (sizeof(tlv->ouisubtype) + 1);\n\n\t/* Move offset to App Priority Table */\n\toffset++;\n\n\t/* Application Priority Table (3 octets)\n\t * Octets:| 1 | 2 | 3 |\n\t * -----------------------------------------\n\t * |Priority|Rsrvd| Sel | Protocol ID |\n\t * -----------------------------------------\n\t * Bits:|23 21|20 19|18 16|15 0|\n\t * -----------------------------------------\n\t */\n\twhile (offset < length) {\n\t\tdcbcfg->app[i].priority = (u8)((buf[offset] &\n\t\t\t\t\t\tI40E_IEEE_APP_PRIO_MASK) >>\n\t\t\t\t\t I40E_IEEE_APP_PRIO_SHIFT);\n\t\tdcbcfg->app[i].selector = (u8)((buf[offset] &\n\t\t\t\t\t\tI40E_IEEE_APP_SEL_MASK) >>\n\t\t\t\t\t I40E_IEEE_APP_SEL_SHIFT);\n\t\tdcbcfg->app[i].protocolid = (buf[offset + 1] << 0x8) |\n\t\t\t\t\t buf[offset + 2];\n\t\t/* Move to next app */\n\t\toffset += 3;\n\t\ti++;\n\t\tif (i >= I40E_DCBX_MAX_APPS)\n\t\t\tbreak;\n\t}\n\n\tdcbcfg->numapps = i;\n}\n\n/**\n * i40e_parse_ieee_etsrec_tlv\n * @tlv: IEEE 802.1Qaz TLV\n * @dcbcfg: Local store to update ETS REC data\n *\n * Get the TLV subtype and send it to parsing function\n * based on the subtype value\n **/\nstatic void i40e_parse_ieee_tlv(struct i40e_lldp_org_tlv *tlv,\n\t\t\t\tstruct i40e_dcbx_config *dcbcfg)\n{\n\tu32 ouisubtype;\n\tu8 subtype;\n\n\touisubtype = I40E_NTOHL(tlv->ouisubtype);\n\tsubtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >>\n\t\t I40E_LLDP_TLV_SUBTYPE_SHIFT);\n\tswitch (subtype) {\n\tcase I40E_IEEE_SUBTYPE_ETS_CFG:\n\t\ti40e_parse_ieee_etscfg_tlv(tlv, dcbcfg);\n\t\tbreak;\n\tcase I40E_IEEE_SUBTYPE_ETS_REC:\n\t\ti40e_parse_ieee_etsrec_tlv(tlv, dcbcfg);\n\t\tbreak;\n\tcase I40E_IEEE_SUBTYPE_PFC_CFG:\n\t\ti40e_parse_ieee_pfccfg_tlv(tlv, dcbcfg);\n\t\tbreak;\n\tcase I40E_IEEE_SUBTYPE_APP_PRI:\n\t\ti40e_parse_ieee_app_tlv(tlv, dcbcfg);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n/**\n * i40e_parse_org_tlv\n * @tlv: Organization specific TLV\n * @dcbcfg: Local store to update ETS REC data\n *\n * Currently only IEEE 802.1Qaz TLV is supported, all others\n * will be returned\n **/\nstatic void i40e_parse_org_tlv(struct i40e_lldp_org_tlv *tlv,\n\t\t\t struct i40e_dcbx_config *dcbcfg)\n{\n\tu32 ouisubtype;\n\tu32 oui;\n\n\touisubtype = I40E_NTOHL(tlv->ouisubtype);\n\toui = (u32)((ouisubtype & I40E_LLDP_TLV_OUI_MASK) >>\n\t\t I40E_LLDP_TLV_OUI_SHIFT);\n\tswitch (oui) {\n\tcase I40E_IEEE_8021QAZ_OUI:\n\t\ti40e_parse_ieee_tlv(tlv, dcbcfg);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n/**\n * i40e_lldp_to_dcb_config\n * @lldpmib: LLDPDU to be parsed\n * @dcbcfg: store for LLDPDU data\n *\n * Parse DCB configuration from the LLDPDU\n **/\nenum i40e_status_code i40e_lldp_to_dcb_config(u8 *lldpmib,\n\t\t\t\t struct i40e_dcbx_config *dcbcfg)\n{\n\tenum i40e_status_code ret = I40E_SUCCESS;\n\tstruct i40e_lldp_org_tlv *tlv;\n\tu16 type;\n\tu16 length;\n\tu16 typelength;\n\tu16 offset = 0;\n\n\tif (!lldpmib || !dcbcfg)\n\t\treturn I40E_ERR_PARAM;\n\n\t/* set to the start of LLDPDU */\n\tlldpmib += I40E_LLDP_MIB_HLEN;\n\ttlv = (struct i40e_lldp_org_tlv *)lldpmib;\n\twhile (1) {\n\t\ttypelength = I40E_NTOHS(tlv->typelength);\n\t\ttype = (u16)((typelength & I40E_LLDP_TLV_TYPE_MASK) >>\n\t\t\t I40E_LLDP_TLV_TYPE_SHIFT);\n\t\tlength = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>\n\t\t\t I40E_LLDP_TLV_LEN_SHIFT);\n\t\toffset += sizeof(typelength) + length;\n\n\t\t/* END TLV or beyond LLDPDU size */\n\t\tif ((type == I40E_TLV_TYPE_END) || (offset > I40E_LLDPDU_SIZE))\n\t\t\tbreak;\n\n\t\tswitch (type) {\n\t\tcase I40E_TLV_TYPE_ORG:\n\t\t\ti40e_parse_org_tlv(tlv, dcbcfg);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Move to next TLV */\n\t\ttlv = (struct i40e_lldp_org_tlv *)((char *)tlv +\n\t\t\t\t\t\t sizeof(tlv->typelength) +\n\t\t\t\t\t\t length);\n\t}\n\n\treturn ret;\n}\n\n/**\n * i40e_aq_get_dcb_config\n * @hw: pointer to the hw struct\n * @mib_type: mib type for the query\n * @bridgetype: bridge type for the query (remote)\n * @dcbcfg: store for LLDPDU data\n *\n * Query DCB configuration from the Firmware\n **/\nenum i40e_status_code i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,\n\t\t\t\t u8 bridgetype,\n\t\t\t\t struct i40e_dcbx_config *dcbcfg)\n{\n\tenum i40e_status_code ret = I40E_SUCCESS;\n\tstruct i40e_virt_mem mem;\n\tu8 *lldpmib;\n\n\t/* Allocate the LLDPDU */\n\tret = i40e_allocate_virt_mem(hw, &mem, I40E_LLDPDU_SIZE);\n\tif (ret)\n\t\treturn ret;\n\n\tlldpmib = (u8 *)mem.va;\n\tret = i40e_aq_get_lldp_mib(hw, bridgetype, mib_type,\n\t\t\t\t (void *)lldpmib, I40E_LLDPDU_SIZE,\n\t\t\t\t NULL, NULL, NULL);\n\tif (ret)\n\t\tgoto free_mem;\n\n\t/* Parse LLDP MIB to get dcb configuration */\n\tret = i40e_lldp_to_dcb_config(lldpmib, dcbcfg);\n\nfree_mem:\n\ti40e_free_virt_mem(hw, &mem);\n\treturn ret;\n}\n\n/**\n * i40e_cee_to_dcb_v1_config\n * @cee_cfg: pointer to CEE v1 response configuration struct\n * @dcbcfg: DCB configuration struct\n *\n * Convert CEE v1 configuration from firmware to DCB configuration\n **/\nstatic void i40e_cee_to_dcb_v1_config(\n\t\t\tstruct i40e_aqc_get_cee_dcb_cfg_v1_resp *cee_cfg,\n\t\t\tstruct i40e_dcbx_config *dcbcfg)\n{\n\tu16 status, tlv_status = LE16_TO_CPU(cee_cfg->tlv_status);\n\tu16 app_prio = LE16_TO_CPU(cee_cfg->oper_app_prio);\n\tu8 i, tc, err, sync, oper;\n\n\t/* CEE PG data to ETS config */\n\tdcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc;\n\n\t/* Note that the FW creates the oper_prio_tc nibbles reversed\n\t * from those in the CEE Priority Group sub-TLV.\n\t */\n\tfor (i = 0; i < 4; i++) {\n\t\ttc = (u8)((cee_cfg->oper_prio_tc[i] &\n\t\t\t I40E_CEE_PGID_PRIO_0_MASK) >>\n\t\t\t I40E_CEE_PGID_PRIO_0_SHIFT);\n\t\tdcbcfg->etscfg.prioritytable[i*2] = tc;\n\t\ttc = (u8)((cee_cfg->oper_prio_tc[i] &\n\t\t\t I40E_CEE_PGID_PRIO_1_MASK) >>\n\t\t\t I40E_CEE_PGID_PRIO_1_SHIFT);\n\t\tdcbcfg->etscfg.prioritytable[i*2 + 1] = tc;\n\t}\n\n\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)\n\t\tdcbcfg->etscfg.tcbwtable[i] = cee_cfg->oper_tc_bw[i];\n\n\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n\t\tif (dcbcfg->etscfg.prioritytable[i] == I40E_CEE_PGID_STRICT) {\n\t\t\t/* Map it to next empty TC */\n\t\t\tdcbcfg->etscfg.prioritytable[i] =\n\t\t\t\t\t\tcee_cfg->oper_num_tc - 1;\n\t\t\tdcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_STRICT;\n\t\t} else {\n\t\t\tdcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;\n\t\t}\n\t}\n\n\t/* CEE PFC data to ETS config */\n\tdcbcfg->pfc.pfcenable = cee_cfg->oper_pfc_en;\n\tdcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;\n\n\tstatus = (tlv_status & I40E_AQC_CEE_APP_STATUS_MASK) >>\n\t\t I40E_AQC_CEE_APP_STATUS_SHIFT;\n\terr = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;\n\tsync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;\n\toper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;\n\t/* Add APPs if Error is False and Oper/Sync is True */\n\tif (!err) {\n\t\t/* CEE operating configuration supports FCoE/iSCSI/FIP only */\n\t\tdcbcfg->numapps = I40E_CEE_OPER_MAX_APPS;\n\n\t\t/* FCoE APP */\n\t\tdcbcfg->app[0].priority =\n\t\t\t(app_prio & I40E_AQC_CEE_APP_FCOE_MASK) >>\n\t\t\t I40E_AQC_CEE_APP_FCOE_SHIFT;\n\t\tdcbcfg->app[0].selector = I40E_APP_SEL_ETHTYPE;\n\t\tdcbcfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;\n\n\t\t/* iSCSI APP */\n\t\tdcbcfg->app[1].priority =\n\t\t\t(app_prio & I40E_AQC_CEE_APP_ISCSI_MASK) >>\n\t\t\t I40E_AQC_CEE_APP_ISCSI_SHIFT;\n\t\tdcbcfg->app[1].selector = I40E_APP_SEL_TCPIP;\n\t\tdcbcfg->app[1].protocolid = I40E_APP_PROTOID_ISCSI;\n\n\t\t/* FIP APP */\n\t\tdcbcfg->app[2].priority =\n\t\t\t(app_prio & I40E_AQC_CEE_APP_FIP_MASK) >>\n\t\t\t I40E_AQC_CEE_APP_FIP_SHIFT;\n\t\tdcbcfg->app[2].selector = I40E_APP_SEL_ETHTYPE;\n\t\tdcbcfg->app[2].protocolid = I40E_APP_PROTOID_FIP;\n\t}\n}\n\n/**\n * i40e_cee_to_dcb_config\n * @cee_cfg: pointer to CEE configuration struct\n * @dcbcfg: DCB configuration struct\n *\n * Convert CEE configuration from firmware to DCB configuration\n **/\nstatic void i40e_cee_to_dcb_config(\n\t\t\t\tstruct i40e_aqc_get_cee_dcb_cfg_resp *cee_cfg,\n\t\t\t\tstruct i40e_dcbx_config *dcbcfg)\n{\n\tu32 status, tlv_status = LE32_TO_CPU(cee_cfg->tlv_status);\n\tu16 app_prio = LE16_TO_CPU(cee_cfg->oper_app_prio);\n\tu8 i, tc, err, sync, oper;\n\n\t/* CEE PG data to ETS config */\n\tdcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc;\n\n\tfor (i = 0; i < 4; i++) {\n\t\ttc = (u8)((cee_cfg->oper_prio_tc[i] &\n\t\t\t I40E_CEE_PGID_PRIO_1_MASK) >>\n\t\t\t I40E_CEE_PGID_PRIO_1_SHIFT);\n\t\tdcbcfg->etscfg.prioritytable[i*2] = tc;\n\t\ttc = (u8)((cee_cfg->oper_prio_tc[i] &\n\t\t\t I40E_CEE_PGID_PRIO_0_MASK) >>\n\t\t\t I40E_CEE_PGID_PRIO_0_SHIFT);\n\t\tdcbcfg->etscfg.prioritytable[i*2 + 1] = tc;\n\t}\n\n\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)\n\t\tdcbcfg->etscfg.tcbwtable[i] = cee_cfg->oper_tc_bw[i];\n\n\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n\t\tif (dcbcfg->etscfg.prioritytable[i] == I40E_CEE_PGID_STRICT) {\n\t\t\t/* Map it to next empty TC */\n\t\t\tdcbcfg->etscfg.prioritytable[i] =\n\t\t\t\t\t\tcee_cfg->oper_num_tc - 1;\n\t\t\tdcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_STRICT;\n\t\t} else {\n\t\t\tdcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;\n\t\t}\n\t}\n\n\t/* CEE PFC data to ETS config */\n\tdcbcfg->pfc.pfcenable = cee_cfg->oper_pfc_en;\n\tdcbcfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;\n\n\tstatus = (tlv_status & I40E_AQC_CEE_APP_STATUS_MASK) >>\n\t\t I40E_AQC_CEE_APP_STATUS_SHIFT;\n\terr = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;\n\tsync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;\n\toper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;\n\t/* Add APPs if Error is False and Oper/Sync is True */\n\tif (!err && sync && oper) {\n\t\t/* CEE operating configuration supports FCoE/iSCSI/FIP only */\n\t\tdcbcfg->numapps = I40E_CEE_OPER_MAX_APPS;\n\n\t\t/* FCoE APP */\n\t\tdcbcfg->app[0].priority =\n\t\t\t(app_prio & I40E_AQC_CEE_APP_FCOE_MASK) >>\n\t\t\t I40E_AQC_CEE_APP_FCOE_SHIFT;\n\t\tdcbcfg->app[0].selector = I40E_APP_SEL_ETHTYPE;\n\t\tdcbcfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;\n\n\t\t/* iSCSI APP */\n\t\tdcbcfg->app[1].priority =\n\t\t\t(app_prio & I40E_AQC_CEE_APP_ISCSI_MASK) >>\n\t\t\t I40E_AQC_CEE_APP_ISCSI_SHIFT;\n\t\tdcbcfg->app[1].selector = I40E_APP_SEL_TCPIP;\n\t\tdcbcfg->app[1].protocolid = I40E_APP_PROTOID_ISCSI;\n\n\t\t/* FIP APP */\n\t\tdcbcfg->app[2].priority =\n\t\t\t(app_prio & I40E_AQC_CEE_APP_FIP_MASK) >>\n\t\t\t I40E_AQC_CEE_APP_FIP_SHIFT;\n\t\tdcbcfg->app[2].selector = I40E_APP_SEL_ETHTYPE;\n\t\tdcbcfg->app[2].protocolid = I40E_APP_PROTOID_FIP;\n\t}\n}\n\n/**\n * i40e_get_dcb_config\n * @hw: pointer to the hw struct\n *\n * Get DCB configuration from the Firmware\n **/\nenum i40e_status_code i40e_get_dcb_config(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret = I40E_SUCCESS;\n\tstruct i40e_aqc_get_cee_dcb_cfg_resp cee_cfg;\n\tstruct i40e_aqc_get_cee_dcb_cfg_v1_resp cee_v1_cfg;\n\n\t/* If Firmware version < v4.33 IEEE only */\n\tif (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) ||\n\t (hw->aq.fw_maj_ver < 4))\n\t\tgoto ieee;\n\n\t/* If Firmware version == v4.33 use old CEE struct */\n\tif ((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver == 33)) {\n\t\tret = i40e_aq_get_cee_dcb_config(hw, &cee_v1_cfg,\n\t\t\t\t\t\t sizeof(cee_v1_cfg), NULL);\n\t\tif (ret == I40E_SUCCESS) {\n\t\t\t/* CEE mode */\n\t\t\thw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_CEE;\n\t\t\ti40e_cee_to_dcb_v1_config(&cee_v1_cfg,\n\t\t\t\t\t\t &hw->local_dcbx_config);\n\t\t}\n\t} else {\n\t\tret = i40e_aq_get_cee_dcb_config(hw, &cee_cfg,\n\t\t\t\t\t\t sizeof(cee_cfg), NULL);\n\t\tif (ret == I40E_SUCCESS) {\n\t\t\t/* CEE mode */\n\t\t\thw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_CEE;\n\t\t\ti40e_cee_to_dcb_config(&cee_cfg,\n\t\t\t\t\t &hw->local_dcbx_config);\n\t\t}\n\t}\n\n\t/* CEE mode not enabled try querying IEEE data */\n\tif (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)\n\t\tgoto ieee;\n\telse\n\t\tgoto out;\n\nieee:\n\t/* IEEE mode */\n\thw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;\n\t/* Get Local DCB Config */\n\tret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,\n\t\t\t\t &hw->local_dcbx_config);\n\tif (ret)\n\t\tgoto out;\n\n\t/* Get Remote DCB Config */\n\tret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,\n\t\t\t I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,\n\t\t\t &hw->remote_dcbx_config);\n\t/* Don't treat ENOENT as an error for Remote MIBs */\n\tif (hw->aq.asq_last_status == I40E_AQ_RC_ENOENT)\n\t\tret = I40E_SUCCESS;\n\nout:\n\treturn ret;\n}\n\n/**\n * i40e_init_dcb\n * @hw: pointer to the hw struct\n *\n * Update DCB configuration from the Firmware\n **/\nenum i40e_status_code i40e_init_dcb(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret = I40E_SUCCESS;\n\tstruct i40e_lldp_variables lldp_cfg;\n\tu8 adminstatus = 0;\n\n\tif (!hw->func_caps.dcb)\n\t\treturn ret;\n\n\t/* Read LLDP NVM area */\n\tret = i40e_read_lldp_cfg(hw, &lldp_cfg);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Get the LLDP AdminStatus for the current port */\n\tadminstatus = lldp_cfg.adminstatus >> (hw->port * 4);\n\tadminstatus &= 0xF;\n\n\t/* LLDP agent disabled */\n\tif (!adminstatus) {\n\t\thw->dcbx_status = I40E_DCBX_STATUS_DISABLED;\n\t\treturn ret;\n\t}\n\n\t/* Get DCBX status */\n\tret = i40e_get_dcbx_status(hw, &hw->dcbx_status);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Check the DCBX Status */\n\tswitch (hw->dcbx_status) {\n\tcase I40E_DCBX_STATUS_DONE:\n\tcase I40E_DCBX_STATUS_IN_PROGRESS:\n\t\t/* Get current DCBX configuration */\n\t\tret = i40e_get_dcb_config(hw);\n\t\tif (ret)\n\t\t\treturn ret;\n\t\tbreak;\n\tcase I40E_DCBX_STATUS_DISABLED:\n\t\treturn ret;\n\tcase I40E_DCBX_STATUS_NOT_STARTED:\n\tcase I40E_DCBX_STATUS_MULTIPLE_PEERS:\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Configure the LLDP MIB change event */\n\tret = i40e_aq_cfg_lldp_mib_change_event(hw, true, NULL);\n\tif (ret)\n\t\treturn ret;\n\n\treturn ret;\n}\n\n\n\n/**\n * i40e_read_lldp_cfg - read LLDP Configuration data from NVM\n * @hw: pointer to the HW structure\n * @lldp_cfg: pointer to hold lldp configuration variables\n *\n * Reads the LLDP configuration data from NVM\n **/\nenum i40e_status_code i40e_read_lldp_cfg(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_lldp_variables *lldp_cfg)\n{\n\tenum i40e_status_code ret = I40E_SUCCESS;\n\tu32 offset = (2 * I40E_NVM_LLDP_CFG_PTR);\n\n\tif (!lldp_cfg)\n\t\treturn I40E_ERR_PARAM;\n\n\tret = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);\n\tif (ret != I40E_SUCCESS)\n\t\tgoto err_lldp_cfg;\n\n\tret = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, offset,\n\t\t\t sizeof(struct i40e_lldp_variables),\n\t\t\t (u8 *)lldp_cfg,\n\t\t\t true, NULL);\n\ti40e_release_nvm(hw);\n\nerr_lldp_cfg:\n\treturn ret;\n}\n" }, { "path": "drivers/net/i40e/base/i40e_dcb.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _I40E_DCB_H_\n#define _I40E_DCB_H_\n\n#include \"i40e_type.h\"\n\n#define I40E_DCBX_OFFLOAD_DISABLED\t0\n#define I40E_DCBX_OFFLOAD_ENABLED\t1\n\n#define I40E_DCBX_STATUS_NOT_STARTED\t0\n#define I40E_DCBX_STATUS_IN_PROGRESS\t1\n#define I40E_DCBX_STATUS_DONE\t\t2\n#define I40E_DCBX_STATUS_MULTIPLE_PEERS\t3\n#define I40E_DCBX_STATUS_DISABLED\t7\n\n#define I40E_TLV_TYPE_END\t\t0\n#define I40E_TLV_TYPE_ORG\t\t127\n\n#define I40E_IEEE_8021QAZ_OUI\t\t0x0080C2\n#define I40E_IEEE_SUBTYPE_ETS_CFG\t9\n#define I40E_IEEE_SUBTYPE_ETS_REC\t10\n#define I40E_IEEE_SUBTYPE_PFC_CFG\t11\n#define I40E_IEEE_SUBTYPE_APP_PRI\t12\n\n#define I40E_LLDP_ADMINSTATUS_DISABLED\t\t0\n#define I40E_LLDP_ADMINSTATUS_ENABLED_RX\t1\n#define I40E_LLDP_ADMINSTATUS_ENABLED_TX\t2\n#define I40E_LLDP_ADMINSTATUS_ENABLED_RXTX\t3\n\n/* Defines for LLDP TLV header */\n#define I40E_LLDP_MIB_HLEN\t\t14\n#define I40E_LLDP_TLV_LEN_SHIFT\t\t0\n#define I40E_LLDP_TLV_LEN_MASK\t\t(0x01FF << I40E_LLDP_TLV_LEN_SHIFT)\n#define I40E_LLDP_TLV_TYPE_SHIFT\t9\n#define I40E_LLDP_TLV_TYPE_MASK\t\t(0x7F << I40E_LLDP_TLV_TYPE_SHIFT)\n#define I40E_LLDP_TLV_SUBTYPE_SHIFT\t0\n#define I40E_LLDP_TLV_SUBTYPE_MASK\t(0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT)\n#define I40E_LLDP_TLV_OUI_SHIFT\t\t8\n#define I40E_LLDP_TLV_OUI_MASK\t\t(0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT)\n\n/* Defines for IEEE ETS TLV */\n#define I40E_IEEE_ETS_MAXTC_SHIFT\t0\n#define I40E_IEEE_ETS_MAXTC_MASK\t(0x7 << I40E_IEEE_ETS_MAXTC_SHIFT)\n#define I40E_IEEE_ETS_CBS_SHIFT\t\t6\n#define I40E_IEEE_ETS_CBS_MASK\t\t(0x1 << I40E_IEEE_ETS_CBS_SHIFT)\n#define I40E_IEEE_ETS_WILLING_SHIFT\t7\n#define I40E_IEEE_ETS_WILLING_MASK\t(0x1 << I40E_IEEE_ETS_WILLING_SHIFT)\n#define I40E_IEEE_ETS_PRIO_0_SHIFT\t0\n#define I40E_IEEE_ETS_PRIO_0_MASK\t(0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)\n#define I40E_IEEE_ETS_PRIO_1_SHIFT\t4\n#define I40E_IEEE_ETS_PRIO_1_MASK\t(0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT)\n#define I40E_CEE_PGID_PRIO_0_SHIFT\t0\n#define I40E_CEE_PGID_PRIO_0_MASK\t(0xF << I40E_CEE_PGID_PRIO_0_SHIFT)\n#define I40E_CEE_PGID_PRIO_1_SHIFT\t4\n#define I40E_CEE_PGID_PRIO_1_MASK\t(0xF << I40E_CEE_PGID_PRIO_1_SHIFT)\n#define I40E_CEE_PGID_STRICT\t\t15\n\n/* Defines for IEEE TSA types */\n#define I40E_IEEE_TSA_STRICT\t\t0\n#define I40E_IEEE_TSA_CBS\t\t1\n#define I40E_IEEE_TSA_ETS\t\t2\n#define I40E_IEEE_TSA_VENDOR\t\t255\n\n/* Defines for IEEE PFC TLV */\n#define I40E_IEEE_PFC_CAP_SHIFT\t\t0\n#define I40E_IEEE_PFC_CAP_MASK\t\t(0xF << I40E_IEEE_PFC_CAP_SHIFT)\n#define I40E_IEEE_PFC_MBC_SHIFT\t\t6\n#define I40E_IEEE_PFC_MBC_MASK\t\t(0x1 << I40E_IEEE_PFC_MBC_SHIFT)\n#define I40E_IEEE_PFC_WILLING_SHIFT\t7\n#define I40E_IEEE_PFC_WILLING_MASK\t(0x1 << I40E_IEEE_PFC_WILLING_SHIFT)\n\n/* Defines for IEEE APP TLV */\n#define I40E_IEEE_APP_SEL_SHIFT\t\t0\n#define I40E_IEEE_APP_SEL_MASK\t\t(0x7 << I40E_IEEE_APP_SEL_SHIFT)\n#define I40E_IEEE_APP_PRIO_SHIFT\t5\n#define I40E_IEEE_APP_PRIO_MASK\t\t(0x7 << I40E_IEEE_APP_PRIO_SHIFT)\n\n/* TLV definitions for preparing MIB */\n#define I40E_TLV_ID_CHASSIS_ID\t\t0\n#define I40E_TLV_ID_PORT_ID\t\t1\n#define I40E_TLV_ID_TIME_TO_LIVE\t2\n#define I40E_IEEE_TLV_ID_ETS_CFG\t3\n#define I40E_IEEE_TLV_ID_ETS_REC\t4\n#define I40E_IEEE_TLV_ID_PFC_CFG\t5\n#define I40E_IEEE_TLV_ID_APP_PRI\t6\n#define I40E_TLV_ID_END_OF_LLDPPDU\t7\n#define I40E_TLV_ID_START\t\tI40E_IEEE_TLV_ID_ETS_CFG\n\n#define I40E_IEEE_ETS_TLV_LENGTH\t25\n#define I40E_IEEE_PFC_TLV_LENGTH\t6\n#define I40E_IEEE_APP_TLV_LENGTH\t11\n\n#pragma pack(1)\n\n/* IEEE 802.1AB LLDP TLV structure */\nstruct i40e_lldp_generic_tlv {\n\t__be16 typelength;\n\tu8 tlvinfo[1];\n};\n\n/* IEEE 802.1AB LLDP Organization specific TLV */\nstruct i40e_lldp_org_tlv {\n\t__be16 typelength;\n\t__be32 ouisubtype;\n\tu8 tlvinfo[1];\n};\n#pragma pack()\n\n/*\n * TODO: The below structures related LLDP/DCBX variables\n * and statistics are defined but need to find how to get\n * the required information from the Firmware to use them\n */\n\n/* IEEE 802.1AB LLDP Agent Statistics */\nstruct i40e_lldp_stats {\n\tu64 remtablelastchangetime;\n\tu64 remtableinserts;\n\tu64 remtabledeletes;\n\tu64 remtabledrops;\n\tu64 remtableageouts;\n\tu64 txframestotal;\n\tu64 rxframesdiscarded;\n\tu64 rxportframeerrors;\n\tu64 rxportframestotal;\n\tu64 rxporttlvsdiscardedtotal;\n\tu64 rxporttlvsunrecognizedtotal;\n\tu64 remtoomanyneighbors;\n};\n\n/* IEEE 802.1Qaz DCBX variables */\nstruct i40e_dcbx_variables {\n\tu32 defmaxtrafficclasses;\n\tu32 defprioritytcmapping;\n\tu32 deftcbandwidth;\n\tu32 deftsaassignment;\n};\n\nenum i40e_status_code i40e_get_dcbx_status(struct i40e_hw *hw,\n\t\t\t\t\t u16 *status);\nenum i40e_status_code i40e_lldp_to_dcb_config(u8 *lldpmib,\n\t\t\t\t\t struct i40e_dcbx_config *dcbcfg);\nenum i40e_status_code i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,\n\t\t\t\t\t u8 bridgetype,\n\t\t\t\t\t struct i40e_dcbx_config *dcbcfg);\nenum i40e_status_code i40e_get_dcb_config(struct i40e_hw *hw);\nenum i40e_status_code i40e_init_dcb(struct i40e_hw *hw);\n\n#endif /* _I40E_DCB_H_ */\n" }, { "path": "drivers/net/i40e/base/i40e_diag.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"i40e_diag.h\"\n#include \"i40e_prototype.h\"\n\n/**\n * i40e_diag_set_loopback\n * @hw: pointer to the hw struct\n * @mode: loopback mode\n *\n * Set chosen loopback mode\n **/\nenum i40e_status_code i40e_diag_set_loopback(struct i40e_hw *hw,\n\t\t\t\t\t enum i40e_lb_mode mode)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\n\tif (i40e_aq_set_lb_modes(hw, mode, NULL))\n\t\tret_code = I40E_ERR_DIAG_TEST_FAILED;\n\n\treturn ret_code;\n}\n\n/**\n * i40e_diag_reg_pattern_test\n * @hw: pointer to the hw struct\n * @reg: reg to be tested\n * @mask: bits to be touched\n **/\nstatic enum i40e_status_code i40e_diag_reg_pattern_test(struct i40e_hw *hw,\n\t\t\t\t\t\t\tu32 reg, u32 mask)\n{\n\tconst u32 patterns[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};\n\tu32 pat, val, orig_val;\n\tint i;\n\n\torig_val = rd32(hw, reg);\n\tfor (i = 0; i < ARRAY_SIZE(patterns); i++) {\n\t\tpat = patterns[i];\n\t\twr32(hw, reg, (pat & mask));\n\t\tval = rd32(hw, reg);\n\t\tif ((val & mask) != (pat & mask)) {\n\t\t\treturn I40E_ERR_DIAG_TEST_FAILED;\n\t\t}\n\t}\n\n\twr32(hw, reg, orig_val);\n\tval = rd32(hw, reg);\n\tif (val != orig_val) {\n\t\treturn I40E_ERR_DIAG_TEST_FAILED;\n\t}\n\n\treturn I40E_SUCCESS;\n}\n\nstruct i40e_diag_reg_test_info i40e_reg_list[] = {\n\t/* offset mask elements stride */\n\t{I40E_QTX_CTL(0), 0x0000FFBF, 1, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},\n\t{I40E_PFINT_ITR0(0), 0x00000FFF, 3, I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},\n\t{I40E_PFINT_ITRN(0, 0), 0x00000FFF, 1, I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},\n\t{I40E_PFINT_ITRN(1, 0), 0x00000FFF, 1, I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},\n\t{I40E_PFINT_ITRN(2, 0), 0x00000FFF, 1, I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},\n\t{I40E_PFINT_STAT_CTL0, 0x0000000C, 1, 0},\n\t{I40E_PFINT_LNKLST0, 0x00001FFF, 1, 0},\n\t{I40E_PFINT_LNKLSTN(0), 0x000007FF, 1, I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},\n\t{I40E_QINT_TQCTL(0), 0x000000FF, 1, I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},\n\t{I40E_QINT_RQCTL(0), 0x000000FF, 1, I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},\n\t{I40E_PFINT_ICR0_ENA, 0xF7F20000, 1, 0},\n\t{ 0 }\n};\n\n/**\n * i40e_diag_reg_test\n * @hw: pointer to the hw struct\n *\n * Perform registers diagnostic test\n **/\nenum i40e_status_code i40e_diag_reg_test(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tu32 reg, mask;\n\tu32 i, j;\n\n\tfor (i = 0; i40e_reg_list[i].offset != 0 &&\n\t\t\t\t\t ret_code == I40E_SUCCESS; i++) {\n\n\t\t/* set actual reg range for dynamically allocated resources */\n\t\tif (i40e_reg_list[i].offset == I40E_QTX_CTL(0) &&\n\t\t hw->func_caps.num_tx_qp != 0)\n\t\t\ti40e_reg_list[i].elements = hw->func_caps.num_tx_qp;\n\t\tif ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) ||\n\t\t i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) ||\n\t\t i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) ||\n\t\t i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) ||\n\t\t i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) &&\n\t\t hw->func_caps.num_msix_vectors != 0)\n\t\t\ti40e_reg_list[i].elements =\n\t\t\t\thw->func_caps.num_msix_vectors - 1;\n\n\t\t/* test register access */\n\t\tmask = i40e_reg_list[i].mask;\n\t\tfor (j = 0; j < i40e_reg_list[i].elements &&\n\t\t\t ret_code == I40E_SUCCESS; j++) {\n\t\t\treg = i40e_reg_list[i].offset\n\t\t\t\t+ (j * i40e_reg_list[i].stride);\n\t\t\tret_code = i40e_diag_reg_pattern_test(hw, reg, mask);\n\t\t}\n\t}\n\n\treturn ret_code;\n}\n\n/**\n * i40e_diag_eeprom_test\n * @hw: pointer to the hw struct\n *\n * Perform EEPROM diagnostic test\n **/\nenum i40e_status_code i40e_diag_eeprom_test(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code;\n\tu16 reg_val;\n\n\t/* read NVM control word and if NVM valid, validate EEPROM checksum*/\n\tret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, ®_val);\n\tif ((ret_code == I40E_SUCCESS) &&\n\t ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==\n\t (0x01 << I40E_SR_CONTROL_WORD_1_SHIFT))) {\n\t\tret_code = i40e_validate_nvm_checksum(hw, NULL);\n\t} else {\n\t\tret_code = I40E_ERR_DIAG_TEST_FAILED;\n\t}\n\n\treturn ret_code;\n}\n\n/**\n * i40e_diag_fw_alive_test\n * @hw: pointer to the hw struct\n *\n * Perform FW alive diagnostic test\n **/\nenum i40e_status_code i40e_diag_fw_alive_test(struct i40e_hw *hw)\n{\n\tUNREFERENCED_1PARAMETER(hw);\n\treturn I40E_SUCCESS;\n}\n" }, { "path": "drivers/net/i40e/base/i40e_diag.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _I40E_DIAG_H_\n#define _I40E_DIAG_H_\n\n#include \"i40e_type.h\"\n\nenum i40e_lb_mode {\n\tI40E_LB_MODE_NONE = 0x0,\n\tI40E_LB_MODE_PHY_LOCAL = I40E_AQ_LB_PHY_LOCAL,\n\tI40E_LB_MODE_PHY_REMOTE = I40E_AQ_LB_PHY_REMOTE,\n\tI40E_LB_MODE_MAC_LOCAL = I40E_AQ_LB_MAC_LOCAL,\n};\n\nstruct i40e_diag_reg_test_info {\n\tu32 offset;\t/* the base register */\n\tu32 mask;\t/* bits that can be tested */\n\tu32 elements;\t/* number of elements if array */\n\tu32 stride;\t/* bytes between each element */\n};\n\nextern struct i40e_diag_reg_test_info i40e_reg_list[];\n\nenum i40e_status_code i40e_diag_set_loopback(struct i40e_hw *hw,\n\t\t\t\t\t enum i40e_lb_mode mode);\nenum i40e_status_code i40e_diag_fw_alive_test(struct i40e_hw *hw);\nenum i40e_status_code i40e_diag_reg_test(struct i40e_hw *hw);\nenum i40e_status_code i40e_diag_eeprom_test(struct i40e_hw *hw);\n\n#endif /* _I40E_DIAG_H_ */\n" }, { "path": "drivers/net/i40e/base/i40e_hmc.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"i40e_osdep.h\"\n#include \"i40e_register.h\"\n#include \"i40e_status.h\"\n#include \"i40e_alloc.h\"\n#include \"i40e_hmc.h\"\n#include \"i40e_type.h\"\n\n/**\n * i40e_add_sd_table_entry - Adds a segment descriptor to the table\n * @hw: pointer to our hw struct\n * @hmc_info: pointer to the HMC configuration information struct\n * @sd_index: segment descriptor index to manipulate\n * @type: what type of segment descriptor we're manipulating\n * @direct_mode_sz: size to alloc in direct mode\n **/\nenum i40e_status_code i40e_add_sd_table_entry(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 sd_index,\n\t\t\t\t\t enum i40e_sd_entry_type type,\n\t\t\t\t\t u64 direct_mode_sz)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tstruct i40e_hmc_sd_entry *sd_entry;\n\tenum i40e_memory_type mem_type;\n\tbool dma_mem_alloc_done = false;\n\tstruct i40e_dma_mem mem;\n\tu64 alloc_len;\n\n\tif (NULL == hmc_info->sd_table.sd_entry) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_add_sd_table_entry: bad sd_entry\\n\");\n\t\tgoto exit;\n\t}\n\n\tif (sd_index >= hmc_info->sd_table.sd_cnt) {\n\t\tret_code = I40E_ERR_INVALID_SD_INDEX;\n\t\tDEBUGOUT(\"i40e_add_sd_table_entry: bad sd_index\\n\");\n\t\tgoto exit;\n\t}\n\n\tsd_entry = &hmc_info->sd_table.sd_entry[sd_index];\n\tif (!sd_entry->valid) {\n\t\tif (I40E_SD_TYPE_PAGED == type) {\n\t\t\tmem_type = i40e_mem_pd;\n\t\t\talloc_len = I40E_HMC_PAGED_BP_SIZE;\n\t\t} else {\n\t\t\tmem_type = i40e_mem_bp_jumbo;\n\t\t\talloc_len = direct_mode_sz;\n\t\t}\n\n\t\t/* allocate a 4K pd page or 2M backing page */\n\t\tret_code = i40e_allocate_dma_mem(hw, &mem, mem_type, alloc_len,\n\t\t\t\t\t\t I40E_HMC_PD_BP_BUF_ALIGNMENT);\n\t\tif (ret_code)\n\t\t\tgoto exit;\n\t\tdma_mem_alloc_done = true;\n\t\tif (I40E_SD_TYPE_PAGED == type) {\n\t\t\tret_code = i40e_allocate_virt_mem(hw,\n\t\t\t\t\t&sd_entry->u.pd_table.pd_entry_virt_mem,\n\t\t\t\t\tsizeof(struct i40e_hmc_pd_entry) * 512);\n\t\t\tif (ret_code)\n\t\t\t\tgoto exit;\n\t\t\tsd_entry->u.pd_table.pd_entry =\n\t\t\t\t(struct i40e_hmc_pd_entry *)\n\t\t\t\tsd_entry->u.pd_table.pd_entry_virt_mem.va;\n\t\t\ti40e_memcpy(&sd_entry->u.pd_table.pd_page_addr,\n\t\t\t\t &mem, sizeof(struct i40e_dma_mem),\n\t\t\t\t I40E_NONDMA_TO_NONDMA);\n\t\t} else {\n\t\t\ti40e_memcpy(&sd_entry->u.bp.addr,\n\t\t\t\t &mem, sizeof(struct i40e_dma_mem),\n\t\t\t\t I40E_NONDMA_TO_NONDMA);\n\t\t\tsd_entry->u.bp.sd_pd_index = sd_index;\n\t\t}\n\t\t/* initialize the sd entry */\n\t\thmc_info->sd_table.sd_entry[sd_index].entry_type = type;\n\n\t\t/* increment the ref count */\n\t\tI40E_INC_SD_REFCNT(&hmc_info->sd_table);\n\t}\n\t/* Increment backing page reference count */\n\tif (I40E_SD_TYPE_DIRECT == sd_entry->entry_type)\n\t\tI40E_INC_BP_REFCNT(&sd_entry->u.bp);\nexit:\n\tif (I40E_SUCCESS != ret_code)\n\t\tif (dma_mem_alloc_done)\n\t\t\ti40e_free_dma_mem(hw, &mem);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_add_pd_table_entry - Adds page descriptor to the specified table\n * @hw: pointer to our HW structure\n * @hmc_info: pointer to the HMC configuration information structure\n * @pd_index: which page descriptor index to manipulate\n *\n * This function:\n *\t1. Initializes the pd entry\n *\t2. Adds pd_entry in the pd_table\n *\t3. Mark the entry valid in i40e_hmc_pd_entry structure\n *\t4. Initializes the pd_entry's ref count to 1\n * assumptions:\n *\t1. The memory for pd should be pinned down, physically contiguous and\n *\t aligned on 4K boundary and zeroed memory.\n *\t2. It should be 4K in size.\n **/\nenum i40e_status_code i40e_add_pd_table_entry(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 pd_index)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tstruct i40e_hmc_pd_table *pd_table;\n\tstruct i40e_hmc_pd_entry *pd_entry;\n\tstruct i40e_dma_mem mem;\n\tu32 sd_idx, rel_pd_idx;\n\tu64 *pd_addr;\n\tu64 page_desc;\n\n\tif (pd_index / I40E_HMC_PD_CNT_IN_SD >= hmc_info->sd_table.sd_cnt) {\n\t\tret_code = I40E_ERR_INVALID_PAGE_DESC_INDEX;\n\t\tDEBUGOUT(\"i40e_add_pd_table_entry: bad pd_index\\n\");\n\t\tgoto exit;\n\t}\n\n\t/* find corresponding sd */\n\tsd_idx = (pd_index / I40E_HMC_PD_CNT_IN_SD);\n\tif (I40E_SD_TYPE_PAGED !=\n\t hmc_info->sd_table.sd_entry[sd_idx].entry_type)\n\t\tgoto exit;\n\n\trel_pd_idx = (pd_index % I40E_HMC_PD_CNT_IN_SD);\n\tpd_table = &hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;\n\tpd_entry = &pd_table->pd_entry[rel_pd_idx];\n\tif (!pd_entry->valid) {\n\t\t/* allocate a 4K backing page */\n\t\tret_code = i40e_allocate_dma_mem(hw, &mem, i40e_mem_bp,\n\t\t\t\t\t\t I40E_HMC_PAGED_BP_SIZE,\n\t\t\t\t\t\t I40E_HMC_PD_BP_BUF_ALIGNMENT);\n\t\tif (ret_code)\n\t\t\tgoto exit;\n\n\t\ti40e_memcpy(&pd_entry->bp.addr, &mem,\n\t\t\t sizeof(struct i40e_dma_mem), I40E_NONDMA_TO_NONDMA);\n\t\tpd_entry->bp.sd_pd_index = pd_index;\n\t\tpd_entry->bp.entry_type = I40E_SD_TYPE_PAGED;\n\t\t/* Set page address and valid bit */\n\t\tpage_desc = mem.pa | 0x1;\n\n\t\tpd_addr = (u64 *)pd_table->pd_page_addr.va;\n\t\tpd_addr += rel_pd_idx;\n\n\t\t/* Add the backing page physical address in the pd entry */\n\t\ti40e_memcpy(pd_addr, &page_desc, sizeof(u64),\n\t\t\t I40E_NONDMA_TO_DMA);\n\n\t\tpd_entry->sd_index = sd_idx;\n\t\tpd_entry->valid = true;\n\t\tI40E_INC_PD_REFCNT(pd_table);\n\t}\n\tI40E_INC_BP_REFCNT(&pd_entry->bp);\nexit:\n\treturn ret_code;\n}\n\n/**\n * i40e_remove_pd_bp - remove a backing page from a page descriptor\n * @hw: pointer to our HW structure\n * @hmc_info: pointer to the HMC configuration information structure\n * @idx: the page index\n * @is_pf: distinguishes a VF from a PF\n *\n * This function:\n *\t1. Marks the entry in pd tabe (for paged address mode) or in sd table\n *\t (for direct address mode) invalid.\n *\t2. Write to register PMPDINV to invalidate the backing page in FV cache\n *\t3. Decrement the ref count for the pd _entry\n * assumptions:\n *\t1. Caller can deallocate the memory used by backing storage after this\n *\t function returns.\n **/\nenum i40e_status_code i40e_remove_pd_bp(struct i40e_hw *hw,\n\t\t\t\t\tstruct i40e_hmc_info *hmc_info,\n\t\t\t\t\tu32 idx)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tstruct i40e_hmc_pd_entry *pd_entry;\n\tstruct i40e_hmc_pd_table *pd_table;\n\tstruct i40e_hmc_sd_entry *sd_entry;\n\tu32 sd_idx, rel_pd_idx;\n\tu64 *pd_addr;\n\n\t/* calculate index */\n\tsd_idx = idx / I40E_HMC_PD_CNT_IN_SD;\n\trel_pd_idx = idx % I40E_HMC_PD_CNT_IN_SD;\n\tif (sd_idx >= hmc_info->sd_table.sd_cnt) {\n\t\tret_code = I40E_ERR_INVALID_PAGE_DESC_INDEX;\n\t\tDEBUGOUT(\"i40e_remove_pd_bp: bad idx\\n\");\n\t\tgoto exit;\n\t}\n\tsd_entry = &hmc_info->sd_table.sd_entry[sd_idx];\n\tif (I40E_SD_TYPE_PAGED != sd_entry->entry_type) {\n\t\tret_code = I40E_ERR_INVALID_SD_TYPE;\n\t\tDEBUGOUT(\"i40e_remove_pd_bp: wrong sd_entry type\\n\");\n\t\tgoto exit;\n\t}\n\t/* get the entry and decrease its ref counter */\n\tpd_table = &hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;\n\tpd_entry = &pd_table->pd_entry[rel_pd_idx];\n\tI40E_DEC_BP_REFCNT(&pd_entry->bp);\n\tif (pd_entry->bp.ref_cnt)\n\t\tgoto exit;\n\n\t/* mark the entry invalid */\n\tpd_entry->valid = false;\n\tI40E_DEC_PD_REFCNT(pd_table);\n\tpd_addr = (u64 *)pd_table->pd_page_addr.va;\n\tpd_addr += rel_pd_idx;\n\ti40e_memset(pd_addr, 0, sizeof(u64), I40E_DMA_MEM);\n\tI40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, idx);\n\n\t/* free memory here */\n\tret_code = i40e_free_dma_mem(hw, &(pd_entry->bp.addr));\n\tif (I40E_SUCCESS != ret_code)\n\t\tgoto exit;\n\tif (!pd_table->ref_cnt)\n\t\ti40e_free_virt_mem(hw, &pd_table->pd_entry_virt_mem);\nexit:\n\treturn ret_code;\n}\n\n/**\n * i40e_prep_remove_sd_bp - Prepares to remove a backing page from a sd entry\n * @hmc_info: pointer to the HMC configuration information structure\n * @idx: the page index\n **/\nenum i40e_status_code i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 idx)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tstruct i40e_hmc_sd_entry *sd_entry;\n\n\t/* get the entry and decrease its ref counter */\n\tsd_entry = &hmc_info->sd_table.sd_entry[idx];\n\tI40E_DEC_BP_REFCNT(&sd_entry->u.bp);\n\tif (sd_entry->u.bp.ref_cnt) {\n\t\tret_code = I40E_ERR_NOT_READY;\n\t\tgoto exit;\n\t}\n\tI40E_DEC_SD_REFCNT(&hmc_info->sd_table);\n\n\t/* mark the entry invalid */\n\tsd_entry->valid = false;\nexit:\n\treturn ret_code;\n}\n\n/**\n * i40e_remove_sd_bp_new - Removes a backing page from a segment descriptor\n * @hw: pointer to our hw struct\n * @hmc_info: pointer to the HMC configuration information structure\n * @idx: the page index\n * @is_pf: used to distinguish between VF and PF\n **/\nenum i40e_status_code i40e_remove_sd_bp_new(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 idx, bool is_pf)\n{\n\tstruct i40e_hmc_sd_entry *sd_entry;\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\n\t/* get the entry and decrease its ref counter */\n\tsd_entry = &hmc_info->sd_table.sd_entry[idx];\n\tif (is_pf) {\n\t\tI40E_CLEAR_PF_SD_ENTRY(hw, idx, I40E_SD_TYPE_DIRECT);\n\t} else {\n\t\tret_code = I40E_NOT_SUPPORTED;\n\t\tgoto exit;\n\t}\n\tret_code = i40e_free_dma_mem(hw, &(sd_entry->u.bp.addr));\n\tif (I40E_SUCCESS != ret_code)\n\t\tgoto exit;\nexit:\n\treturn ret_code;\n}\n\n/**\n * i40e_prep_remove_pd_page - Prepares to remove a PD page from sd entry.\n * @hmc_info: pointer to the HMC configuration information structure\n * @idx: segment descriptor index to find the relevant page descriptor\n **/\nenum i40e_status_code i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 idx)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tstruct i40e_hmc_sd_entry *sd_entry;\n\n\tsd_entry = &hmc_info->sd_table.sd_entry[idx];\n\n\tif (sd_entry->u.pd_table.ref_cnt) {\n\t\tret_code = I40E_ERR_NOT_READY;\n\t\tgoto exit;\n\t}\n\n\t/* mark the entry invalid */\n\tsd_entry->valid = false;\n\n\tI40E_DEC_SD_REFCNT(&hmc_info->sd_table);\nexit:\n\treturn ret_code;\n}\n\n/**\n * i40e_remove_pd_page_new - Removes a PD page from sd entry.\n * @hw: pointer to our hw struct\n * @hmc_info: pointer to the HMC configuration information structure\n * @idx: segment descriptor index to find the relevant page descriptor\n * @is_pf: used to distinguish between VF and PF\n **/\nenum i40e_status_code i40e_remove_pd_page_new(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 idx, bool is_pf)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tstruct i40e_hmc_sd_entry *sd_entry;\n\n\tsd_entry = &hmc_info->sd_table.sd_entry[idx];\n\tif (is_pf) {\n\t\tI40E_CLEAR_PF_SD_ENTRY(hw, idx, I40E_SD_TYPE_PAGED);\n\t} else {\n\t\tret_code = I40E_NOT_SUPPORTED;\n\t\tgoto exit;\n\t}\n\t/* free memory here */\n\tret_code = i40e_free_dma_mem(hw, &(sd_entry->u.pd_table.pd_page_addr));\n\tif (I40E_SUCCESS != ret_code)\n\t\tgoto exit;\nexit:\n\treturn ret_code;\n}\n" }, { "path": "drivers/net/i40e/base/i40e_hmc.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _I40E_HMC_H_\n#define _I40E_HMC_H_\n\n#define I40E_HMC_MAX_BP_COUNT 512\n\n/* forward-declare the HW struct for the compiler */\nstruct i40e_hw;\n\n#define I40E_HMC_INFO_SIGNATURE\t\t0x484D5347 /* HMSG */\n#define I40E_HMC_PD_CNT_IN_SD\t\t512\n#define I40E_HMC_DIRECT_BP_SIZE\t\t0x200000 /* 2M */\n#define I40E_HMC_PAGED_BP_SIZE\t\t4096\n#define I40E_HMC_PD_BP_BUF_ALIGNMENT\t4096\n#define I40E_FIRST_VF_FPM_ID\t\t16\n\nstruct i40e_hmc_obj_info {\n\tu64 base;\t/* base addr in FPM */\n\tu32 max_cnt;\t/* max count available for this hmc func */\n\tu32 cnt;\t/* count of objects driver actually wants to create */\n\tu64 size;\t/* size in bytes of one object */\n};\n\nenum i40e_sd_entry_type {\n\tI40E_SD_TYPE_INVALID = 0,\n\tI40E_SD_TYPE_PAGED = 1,\n\tI40E_SD_TYPE_DIRECT = 2\n};\n\nstruct i40e_hmc_bp {\n\tenum i40e_sd_entry_type entry_type;\n\tstruct i40e_dma_mem addr; /* populate to be used by hw */\n\tu32 sd_pd_index;\n\tu32 ref_cnt;\n};\n\nstruct i40e_hmc_pd_entry {\n\tstruct i40e_hmc_bp bp;\n\tu32 sd_index;\n\tbool valid;\n};\n\nstruct i40e_hmc_pd_table {\n\tstruct i40e_dma_mem pd_page_addr; /* populate to be used by hw */\n\tstruct i40e_hmc_pd_entry *pd_entry; /* [512] for sw book keeping */\n\tstruct i40e_virt_mem pd_entry_virt_mem; /* virt mem for pd_entry */\n\n\tu32 ref_cnt;\n\tu32 sd_index;\n};\n\nstruct i40e_hmc_sd_entry {\n\tenum i40e_sd_entry_type entry_type;\n\tbool valid;\n\n\tunion {\n\t\tstruct i40e_hmc_pd_table pd_table;\n\t\tstruct i40e_hmc_bp bp;\n\t} u;\n};\n\nstruct i40e_hmc_sd_table {\n\tstruct i40e_virt_mem addr; /* used to track sd_entry allocations */\n\tu32 sd_cnt;\n\tu32 ref_cnt;\n\tstruct i40e_hmc_sd_entry *sd_entry; /* (sd_cnt*512) entries max */\n};\n\nstruct i40e_hmc_info {\n\tu32 signature;\n\t/* equals to pci func num for PF and dynamically allocated for VFs */\n\tu8 hmc_fn_id;\n\tu16 first_sd_index; /* index of the first available SD */\n\n\t/* hmc objects */\n\tstruct i40e_hmc_obj_info *hmc_obj;\n\tstruct i40e_virt_mem hmc_obj_virt_mem;\n\tstruct i40e_hmc_sd_table sd_table;\n};\n\n#define I40E_INC_SD_REFCNT(sd_table)\t((sd_table)->ref_cnt++)\n#define I40E_INC_PD_REFCNT(pd_table)\t((pd_table)->ref_cnt++)\n#define I40E_INC_BP_REFCNT(bp)\t\t((bp)->ref_cnt++)\n\n#define I40E_DEC_SD_REFCNT(sd_table)\t((sd_table)->ref_cnt--)\n#define I40E_DEC_PD_REFCNT(pd_table)\t((pd_table)->ref_cnt--)\n#define I40E_DEC_BP_REFCNT(bp)\t\t((bp)->ref_cnt--)\n\n/**\n * I40E_SET_PF_SD_ENTRY - marks the sd entry as valid in the hardware\n * @hw: pointer to our hw struct\n * @pa: pointer to physical address\n * @sd_index: segment descriptor index\n * @type: if sd entry is direct or paged\n **/\n#define I40E_SET_PF_SD_ENTRY(hw, pa, sd_index, type)\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tu32 val1, val2, val3;\t\t\t\t\t\t\\\n\tval1 = (u32)(I40E_HI_DWORD(pa));\t\t\t\t\\\n\tval2 = (u32)(pa) | (I40E_HMC_MAX_BP_COUNT <<\t\t\t\\\n\t\t I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) |\t\t\\\n\t\t((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) <<\t\t\\\n\t\tI40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) |\t\t\t\\\n\t\t(1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT);\t\t\\\n\tval3 = (sd_index) | (1u << I40E_PFHMC_SDCMD_PMSDWR_SHIFT);\t\\\n\twr32((hw), I40E_PFHMC_SDDATAHIGH, val1);\t\t\t\\\n\twr32((hw), I40E_PFHMC_SDDATALOW, val2);\t\t\t\t\\\n\twr32((hw), I40E_PFHMC_SDCMD, val3);\t\t\t\t\\\n}\n\n/**\n * I40E_CLEAR_PF_SD_ENTRY - marks the sd entry as invalid in the hardware\n * @hw: pointer to our hw struct\n * @sd_index: segment descriptor index\n * @type: if sd entry is direct or paged\n **/\n#define I40E_CLEAR_PF_SD_ENTRY(hw, sd_index, type)\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tu32 val2, val3;\t\t\t\t\t\t\t\\\n\tval2 = (I40E_HMC_MAX_BP_COUNT <<\t\t\t\t\\\n\t\tI40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) |\t\t\\\n\t\t((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) <<\t\t\\\n\t\tI40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT);\t\t\t\\\n\tval3 = (sd_index) | (1u << I40E_PFHMC_SDCMD_PMSDWR_SHIFT);\t\\\n\twr32((hw), I40E_PFHMC_SDDATAHIGH, 0);\t\t\t\t\\\n\twr32((hw), I40E_PFHMC_SDDATALOW, val2);\t\t\t\t\\\n\twr32((hw), I40E_PFHMC_SDCMD, val3);\t\t\t\t\\\n}\n\n/**\n * I40E_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware\n * @hw: pointer to our hw struct\n * @sd_idx: segment descriptor index\n * @pd_idx: page descriptor index\n **/\n#define I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx)\t\t\t\\\n\twr32((hw), I40E_PFHMC_PDINV,\t\t\t\t\t\\\n\t (((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) |\t\t\\\n\t ((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)))\n\n/**\n * I40E_FIND_SD_INDEX_LIMIT - finds segment descriptor index limit\n * @hmc_info: pointer to the HMC configuration information structure\n * @type: type of HMC resources we're searching\n * @index: starting index for the object\n * @cnt: number of objects we're trying to create\n * @sd_idx: pointer to return index of the segment descriptor in question\n * @sd_limit: pointer to return the maximum number of segment descriptors\n *\n * This function calculates the segment descriptor index and index limit\n * for the resource defined by i40e_hmc_rsrc_type.\n **/\n#define I40E_FIND_SD_INDEX_LIMIT(hmc_info, type, index, cnt, sd_idx, sd_limit)\\\n{\t\t\t\t\t\t\t\t\t\\\n\tu64 fpm_addr, fpm_limit;\t\t\t\t\t\\\n\tfpm_addr = (hmc_info)->hmc_obj[(type)].base +\t\t\t\\\n\t\t (hmc_info)->hmc_obj[(type)].size * (index);\t\t\\\n\tfpm_limit = fpm_addr + (hmc_info)->hmc_obj[(type)].size * (cnt);\\\n\t*(sd_idx) = (u32)(fpm_addr / I40E_HMC_DIRECT_BP_SIZE);\t\t\\\n\t*(sd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_DIRECT_BP_SIZE);\t\\\n\t/* add one more to the limit to correct our range */\t\t\\\n\t*(sd_limit) += 1;\t\t\t\t\t\t\\\n}\n\n/**\n * I40E_FIND_PD_INDEX_LIMIT - finds page descriptor index limit\n * @hmc_info: pointer to the HMC configuration information struct\n * @type: HMC resource type we're examining\n * @idx: starting index for the object\n * @cnt: number of objects we're trying to create\n * @pd_index: pointer to return page descriptor index\n * @pd_limit: pointer to return page descriptor index limit\n *\n * Calculates the page descriptor index and index limit for the resource\n * defined by i40e_hmc_rsrc_type.\n **/\n#define I40E_FIND_PD_INDEX_LIMIT(hmc_info, type, idx, cnt, pd_index, pd_limit)\\\n{\t\t\t\t\t\t\t\t\t\\\n\tu64 fpm_adr, fpm_limit;\t\t\t\t\t\t\\\n\tfpm_adr = (hmc_info)->hmc_obj[(type)].base +\t\t\t\\\n\t\t (hmc_info)->hmc_obj[(type)].size * (idx);\t\t\\\n\tfpm_limit = fpm_adr + (hmc_info)->hmc_obj[(type)].size * (cnt);\t\\\n\t*(pd_index) = (u32)(fpm_adr / I40E_HMC_PAGED_BP_SIZE);\t\t\\\n\t*(pd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_PAGED_BP_SIZE);\t\\\n\t/* add one more to the limit to correct our range */\t\t\\\n\t*(pd_limit) += 1;\t\t\t\t\t\t\\\n}\nenum i40e_status_code i40e_add_sd_table_entry(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 sd_index,\n\t\t\t\t\t enum i40e_sd_entry_type type,\n\t\t\t\t\t u64 direct_mode_sz);\n\nenum i40e_status_code i40e_add_pd_table_entry(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 pd_index);\nenum i40e_status_code i40e_remove_pd_bp(struct i40e_hw *hw,\n\t\t\t\t\tstruct i40e_hmc_info *hmc_info,\n\t\t\t\t\tu32 idx);\nenum i40e_status_code i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 idx);\nenum i40e_status_code i40e_remove_sd_bp_new(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 idx, bool is_pf);\nenum i40e_status_code i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 idx);\nenum i40e_status_code i40e_remove_pd_page_new(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 idx, bool is_pf);\n\n#endif /* _I40E_HMC_H_ */\n" }, { "path": "drivers/net/i40e/base/i40e_lan_hmc.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"i40e_osdep.h\"\n#include \"i40e_register.h\"\n#include \"i40e_type.h\"\n#include \"i40e_hmc.h\"\n#include \"i40e_lan_hmc.h\"\n#include \"i40e_prototype.h\"\n\n/* lan specific interface functions */\n\n/**\n * i40e_align_l2obj_base - aligns base object pointer to 512 bytes\n * @offset: base address offset needing alignment\n *\n * Aligns the layer 2 function private memory so it's 512-byte aligned.\n **/\nSTATIC u64 i40e_align_l2obj_base(u64 offset)\n{\n\tu64 aligned_offset = offset;\n\n\tif ((offset % I40E_HMC_L2OBJ_BASE_ALIGNMENT) > 0)\n\t\taligned_offset += (I40E_HMC_L2OBJ_BASE_ALIGNMENT -\n\t\t\t\t (offset % I40E_HMC_L2OBJ_BASE_ALIGNMENT));\n\n\treturn aligned_offset;\n}\n\n/**\n * i40e_calculate_l2fpm_size - calculates layer 2 FPM memory size\n * @txq_num: number of Tx queues needing backing context\n * @rxq_num: number of Rx queues needing backing context\n * @fcoe_cntx_num: amount of FCoE statefull contexts needing backing context\n * @fcoe_filt_num: number of FCoE filters needing backing context\n *\n * Calculates the maximum amount of memory for the function required, based\n * on the number of resources it must provide context for.\n **/\nu64 i40e_calculate_l2fpm_size(u32 txq_num, u32 rxq_num,\n\t\t\t u32 fcoe_cntx_num, u32 fcoe_filt_num)\n{\n\tu64 fpm_size = 0;\n\n\tfpm_size = txq_num * I40E_HMC_OBJ_SIZE_TXQ;\n\tfpm_size = i40e_align_l2obj_base(fpm_size);\n\n\tfpm_size += (rxq_num * I40E_HMC_OBJ_SIZE_RXQ);\n\tfpm_size = i40e_align_l2obj_base(fpm_size);\n\n\tfpm_size += (fcoe_cntx_num * I40E_HMC_OBJ_SIZE_FCOE_CNTX);\n\tfpm_size = i40e_align_l2obj_base(fpm_size);\n\n\tfpm_size += (fcoe_filt_num * I40E_HMC_OBJ_SIZE_FCOE_FILT);\n\tfpm_size = i40e_align_l2obj_base(fpm_size);\n\n\treturn fpm_size;\n}\n\n/**\n * i40e_init_lan_hmc - initialize i40e_hmc_info struct\n * @hw: pointer to the HW structure\n * @txq_num: number of Tx queues needing backing context\n * @rxq_num: number of Rx queues needing backing context\n * @fcoe_cntx_num: amount of FCoE statefull contexts needing backing context\n * @fcoe_filt_num: number of FCoE filters needing backing context\n *\n * This function will be called once per physical function initialization.\n * It will fill out the i40e_hmc_obj_info structure for LAN objects based on\n * the driver's provided input, as well as information from the HMC itself\n * loaded from NVRAM.\n *\n * Assumptions:\n * - HMC Resource Profile has been selected before calling this function.\n **/\nenum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,\n\t\t\t\t\tu32 rxq_num, u32 fcoe_cntx_num,\n\t\t\t\t\tu32 fcoe_filt_num)\n{\n\tstruct i40e_hmc_obj_info *obj, *full_obj;\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tu64 l2fpm_size;\n\tu32 size_exp;\n\n\thw->hmc.signature = I40E_HMC_INFO_SIGNATURE;\n\thw->hmc.hmc_fn_id = hw->pf_id;\n\n\t/* allocate memory for hmc_obj */\n\tret_code = i40e_allocate_virt_mem(hw, &hw->hmc.hmc_obj_virt_mem,\n\t\t\tsizeof(struct i40e_hmc_obj_info) * I40E_HMC_LAN_MAX);\n\tif (ret_code)\n\t\tgoto init_lan_hmc_out;\n\thw->hmc.hmc_obj = (struct i40e_hmc_obj_info *)\n\t\t\t hw->hmc.hmc_obj_virt_mem.va;\n\n\t/* The full object will be used to create the LAN HMC SD */\n\tfull_obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_FULL];\n\tfull_obj->max_cnt = 0;\n\tfull_obj->cnt = 0;\n\tfull_obj->base = 0;\n\tfull_obj->size = 0;\n\n\t/* Tx queue context information */\n\tobj = &hw->hmc.hmc_obj[I40E_HMC_LAN_TX];\n\tobj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX);\n\tobj->cnt = txq_num;\n\tobj->base = 0;\n\tsize_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ);\n\tobj->size = (u64)1 << size_exp;\n\n\t/* validate values requested by driver don't exceed HMC capacity */\n\tif (txq_num > obj->max_cnt) {\n\t\tret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;\n\t\tDEBUGOUT3(\"i40e_init_lan_hmc: Tx context: asks for 0x%x but max allowed is 0x%x, returns error %d\\n\",\n\t\t\t txq_num, obj->max_cnt, ret_code);\n\t\tgoto init_lan_hmc_out;\n\t}\n\n\t/* aggregate values into the full LAN object for later */\n\tfull_obj->max_cnt += obj->max_cnt;\n\tfull_obj->cnt += obj->cnt;\n\n\t/* Rx queue context information */\n\tobj = &hw->hmc.hmc_obj[I40E_HMC_LAN_RX];\n\tobj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX);\n\tobj->cnt = rxq_num;\n\tobj->base = hw->hmc.hmc_obj[I40E_HMC_LAN_TX].base +\n\t\t (hw->hmc.hmc_obj[I40E_HMC_LAN_TX].cnt *\n\t\t hw->hmc.hmc_obj[I40E_HMC_LAN_TX].size);\n\tobj->base = i40e_align_l2obj_base(obj->base);\n\tsize_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ);\n\tobj->size = (u64)1 << size_exp;\n\n\t/* validate values requested by driver don't exceed HMC capacity */\n\tif (rxq_num > obj->max_cnt) {\n\t\tret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;\n\t\tDEBUGOUT3(\"i40e_init_lan_hmc: Rx context: asks for 0x%x but max allowed is 0x%x, returns error %d\\n\",\n\t\t\t rxq_num, obj->max_cnt, ret_code);\n\t\tgoto init_lan_hmc_out;\n\t}\n\n\t/* aggregate values into the full LAN object for later */\n\tfull_obj->max_cnt += obj->max_cnt;\n\tfull_obj->cnt += obj->cnt;\n\n\t/* FCoE context information */\n\tobj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX];\n\tobj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX);\n\tobj->cnt = fcoe_cntx_num;\n\tobj->base = hw->hmc.hmc_obj[I40E_HMC_LAN_RX].base +\n\t\t (hw->hmc.hmc_obj[I40E_HMC_LAN_RX].cnt *\n\t\t hw->hmc.hmc_obj[I40E_HMC_LAN_RX].size);\n\tobj->base = i40e_align_l2obj_base(obj->base);\n\tsize_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ);\n\tobj->size = (u64)1 << size_exp;\n\n\t/* validate values requested by driver don't exceed HMC capacity */\n\tif (fcoe_cntx_num > obj->max_cnt) {\n\t\tret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;\n\t\tDEBUGOUT3(\"i40e_init_lan_hmc: FCoE context: asks for 0x%x but max allowed is 0x%x, returns error %d\\n\",\n\t\t\t fcoe_cntx_num, obj->max_cnt, ret_code);\n\t\tgoto init_lan_hmc_out;\n\t}\n\n\t/* aggregate values into the full LAN object for later */\n\tfull_obj->max_cnt += obj->max_cnt;\n\tfull_obj->cnt += obj->cnt;\n\n\t/* FCoE filter information */\n\tobj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_FILT];\n\tobj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX);\n\tobj->cnt = fcoe_filt_num;\n\tobj->base = hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].base +\n\t\t (hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].cnt *\n\t\t hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].size);\n\tobj->base = i40e_align_l2obj_base(obj->base);\n\tsize_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ);\n\tobj->size = (u64)1 << size_exp;\n\n\t/* validate values requested by driver don't exceed HMC capacity */\n\tif (fcoe_filt_num > obj->max_cnt) {\n\t\tret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;\n\t\tDEBUGOUT3(\"i40e_init_lan_hmc: FCoE filter: asks for 0x%x but max allowed is 0x%x, returns error %d\\n\",\n\t\t\t fcoe_filt_num, obj->max_cnt, ret_code);\n\t\tgoto init_lan_hmc_out;\n\t}\n\n\t/* aggregate values into the full LAN object for later */\n\tfull_obj->max_cnt += obj->max_cnt;\n\tfull_obj->cnt += obj->cnt;\n\n\thw->hmc.first_sd_index = 0;\n\thw->hmc.sd_table.ref_cnt = 0;\n\tl2fpm_size = i40e_calculate_l2fpm_size(txq_num, rxq_num, fcoe_cntx_num,\n\t\t\t\t\t fcoe_filt_num);\n\tif (NULL == hw->hmc.sd_table.sd_entry) {\n\t\thw->hmc.sd_table.sd_cnt = (u32)\n\t\t\t\t (l2fpm_size + I40E_HMC_DIRECT_BP_SIZE - 1) /\n\t\t\t\t I40E_HMC_DIRECT_BP_SIZE;\n\n\t\t/* allocate the sd_entry members in the sd_table */\n\t\tret_code = i40e_allocate_virt_mem(hw, &hw->hmc.sd_table.addr,\n\t\t\t\t\t (sizeof(struct i40e_hmc_sd_entry) *\n\t\t\t\t\t hw->hmc.sd_table.sd_cnt));\n\t\tif (ret_code)\n\t\t\tgoto init_lan_hmc_out;\n\t\thw->hmc.sd_table.sd_entry =\n\t\t\t(struct i40e_hmc_sd_entry *)hw->hmc.sd_table.addr.va;\n\t}\n\t/* store in the LAN full object for later */\n\tfull_obj->size = l2fpm_size;\n\ninit_lan_hmc_out:\n\treturn ret_code;\n}\n\n/**\n * i40e_remove_pd_page - Remove a page from the page descriptor table\n * @hw: pointer to the HW structure\n * @hmc_info: pointer to the HMC configuration information structure\n * @idx: segment descriptor index to find the relevant page descriptor\n *\n * This function:\n *\t1. Marks the entry in pd table (for paged address mode) invalid\n *\t2. write to register PMPDINV to invalidate the backing page in FV cache\n *\t3. Decrement the ref count for pd_entry\n * assumptions:\n *\t1. caller can deallocate the memory used by pd after this function\n *\t returns.\n **/\nSTATIC enum i40e_status_code i40e_remove_pd_page(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t\t u32 idx)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\n\tif (i40e_prep_remove_pd_page(hmc_info, idx) == I40E_SUCCESS)\n\t\tret_code = i40e_remove_pd_page_new(hw, hmc_info, idx, true);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_remove_sd_bp - remove a backing page from a segment descriptor\n * @hw: pointer to our HW structure\n * @hmc_info: pointer to the HMC configuration information structure\n * @idx: the page index\n *\n * This function:\n *\t1. Marks the entry in sd table (for direct address mode) invalid\n *\t2. write to register PMSDCMD, PMSDDATALOW(PMSDDATALOW.PMSDVALID set\n *\t to 0) and PMSDDATAHIGH to invalidate the sd page\n *\t3. Decrement the ref count for the sd_entry\n * assumptions:\n *\t1. caller can deallocate the memory used by backing storage after this\n *\t function returns.\n **/\nSTATIC enum i40e_status_code i40e_remove_sd_bp(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_hmc_info *hmc_info,\n\t\t\t\t\t u32 idx)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\n\tif (i40e_prep_remove_sd_bp(hmc_info, idx) == I40E_SUCCESS)\n\t\tret_code = i40e_remove_sd_bp_new(hw, hmc_info, idx, true);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_create_lan_hmc_object - allocate backing store for hmc objects\n * @hw: pointer to the HW structure\n * @info: pointer to i40e_hmc_create_obj_info struct\n *\n * This will allocate memory for PDs and backing pages and populate\n * the sd and pd entries.\n **/\nenum i40e_status_code i40e_create_lan_hmc_object(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_hmc_lan_create_obj_info *info)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tstruct i40e_hmc_sd_entry *sd_entry;\n\tu32 pd_idx1 = 0, pd_lmt1 = 0;\n\tu32 pd_idx = 0, pd_lmt = 0;\n\tbool pd_error = false;\n\tu32 sd_idx, sd_lmt;\n\tu64 sd_size;\n\tu32 i, j;\n\n\tif (NULL == info) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_create_lan_hmc_object: bad info ptr\\n\");\n\t\tgoto exit;\n\t}\n\tif (NULL == info->hmc_info) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_create_lan_hmc_object: bad hmc_info ptr\\n\");\n\t\tgoto exit;\n\t}\n\tif (I40E_HMC_INFO_SIGNATURE != info->hmc_info->signature) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_create_lan_hmc_object: bad signature\\n\");\n\t\tgoto exit;\n\t}\n\n\tif (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) {\n\t\tret_code = I40E_ERR_INVALID_HMC_OBJ_INDEX;\n\t\tDEBUGOUT1(\"i40e_create_lan_hmc_object: returns error %d\\n\",\n\t\t\t ret_code);\n\t\tgoto exit;\n\t}\n\tif ((info->start_idx + info->count) >\n\t info->hmc_info->hmc_obj[info->rsrc_type].cnt) {\n\t\tret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;\n\t\tDEBUGOUT1(\"i40e_create_lan_hmc_object: returns error %d\\n\",\n\t\t\t ret_code);\n\t\tgoto exit;\n\t}\n\n\t/* find sd index and limit */\n\tI40E_FIND_SD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,\n\t\t\t\t info->start_idx, info->count,\n\t\t\t\t &sd_idx, &sd_lmt);\n\tif (sd_idx >= info->hmc_info->sd_table.sd_cnt ||\n\t sd_lmt > info->hmc_info->sd_table.sd_cnt) {\n\t\t\tret_code = I40E_ERR_INVALID_SD_INDEX;\n\t\t\tgoto exit;\n\t}\n\t/* find pd index */\n\tI40E_FIND_PD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,\n\t\t\t\t info->start_idx, info->count, &pd_idx,\n\t\t\t\t &pd_lmt);\n\n\t/* This is to cover for cases where you may not want to have an SD with\n\t * the full 2M memory but something smaller. By not filling out any\n\t * size, the function will default the SD size to be 2M.\n\t */\n\tif (info->direct_mode_sz == 0)\n\t\tsd_size = I40E_HMC_DIRECT_BP_SIZE;\n\telse\n\t\tsd_size = info->direct_mode_sz;\n\n\t/* check if all the sds are valid. If not, allocate a page and\n\t * initialize it.\n\t */\n\tfor (j = sd_idx; j < sd_lmt; j++) {\n\t\t/* update the sd table entry */\n\t\tret_code = i40e_add_sd_table_entry(hw, info->hmc_info, j,\n\t\t\t\t\t\t info->entry_type,\n\t\t\t\t\t\t sd_size);\n\t\tif (I40E_SUCCESS != ret_code)\n\t\t\tgoto exit_sd_error;\n\t\tsd_entry = &info->hmc_info->sd_table.sd_entry[j];\n\t\tif (I40E_SD_TYPE_PAGED == sd_entry->entry_type) {\n\t\t\t/* check if all the pds in this sd are valid. If not,\n\t\t\t * allocate a page and initialize it.\n\t\t\t */\n\n\t\t\t/* find pd_idx and pd_lmt in this sd */\n\t\t\tpd_idx1 = max(pd_idx, (j * I40E_HMC_MAX_BP_COUNT));\n\t\t\tpd_lmt1 = min(pd_lmt,\n\t\t\t\t ((j + 1) * I40E_HMC_MAX_BP_COUNT));\n\t\t\tfor (i = pd_idx1; i < pd_lmt1; i++) {\n\t\t\t\t/* update the pd table entry */\n\t\t\t\tret_code = i40e_add_pd_table_entry(hw,\n\t\t\t\t\t\t\t\tinfo->hmc_info,\n\t\t\t\t\t\t\t\ti);\n\t\t\t\tif (I40E_SUCCESS != ret_code) {\n\t\t\t\t\tpd_error = true;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (pd_error) {\n\t\t\t\t/* remove the backing pages from pd_idx1 to i */\n\t\t\t\twhile (i && (i > pd_idx1)) {\n\t\t\t\t\ti40e_remove_pd_bp(hw, info->hmc_info,\n\t\t\t\t\t\t\t (i - 1));\n\t\t\t\t\ti--;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tif (!sd_entry->valid) {\n\t\t\tsd_entry->valid = true;\n\t\t\tswitch (sd_entry->entry_type) {\n\t\t\tcase I40E_SD_TYPE_PAGED:\n\t\t\t\tI40E_SET_PF_SD_ENTRY(hw,\n\t\t\t\t\tsd_entry->u.pd_table.pd_page_addr.pa,\n\t\t\t\t\tj, sd_entry->entry_type);\n\t\t\t\tbreak;\n\t\t\tcase I40E_SD_TYPE_DIRECT:\n\t\t\t\tI40E_SET_PF_SD_ENTRY(hw, sd_entry->u.bp.addr.pa,\n\t\t\t\t\t\t j, sd_entry->entry_type);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tret_code = I40E_ERR_INVALID_SD_TYPE;\n\t\t\t\tgoto exit;\n\t\t\t}\n\t\t}\n\t}\n\tgoto exit;\n\nexit_sd_error:\n\t/* cleanup for sd entries from j to sd_idx */\n\twhile (j && (j > sd_idx)) {\n\t\tsd_entry = &info->hmc_info->sd_table.sd_entry[j - 1];\n\t\tswitch (sd_entry->entry_type) {\n\t\tcase I40E_SD_TYPE_PAGED:\n\t\t\tpd_idx1 = max(pd_idx,\n\t\t\t\t ((j - 1) * I40E_HMC_MAX_BP_COUNT));\n\t\t\tpd_lmt1 = min(pd_lmt, (j * I40E_HMC_MAX_BP_COUNT));\n\t\t\tfor (i = pd_idx1; i < pd_lmt1; i++) {\n\t\t\t\ti40e_remove_pd_bp(hw, info->hmc_info, i);\n\t\t\t}\n\t\t\ti40e_remove_pd_page(hw, info->hmc_info, (j - 1));\n\t\t\tbreak;\n\t\tcase I40E_SD_TYPE_DIRECT:\n\t\t\ti40e_remove_sd_bp(hw, info->hmc_info, (j - 1));\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tret_code = I40E_ERR_INVALID_SD_TYPE;\n\t\t\tbreak;\n\t\t}\n\t\tj--;\n\t}\nexit:\n\treturn ret_code;\n}\n\n/**\n * i40e_configure_lan_hmc - prepare the HMC backing store\n * @hw: pointer to the hw structure\n * @model: the model for the layout of the SD/PD tables\n *\n * - This function will be called once per physical function initialization.\n * - This function will be called after i40e_init_lan_hmc() and before\n * any LAN/FCoE HMC objects can be created.\n **/\nenum i40e_status_code i40e_configure_lan_hmc(struct i40e_hw *hw,\n\t\t\t\t\t enum i40e_hmc_model model)\n{\n\tstruct i40e_hmc_lan_create_obj_info info;\n\tu8 hmc_fn_id = hw->hmc.hmc_fn_id;\n\tstruct i40e_hmc_obj_info *obj;\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\n\t/* Initialize part of the create object info struct */\n\tinfo.hmc_info = &hw->hmc;\n\tinfo.rsrc_type = I40E_HMC_LAN_FULL;\n\tinfo.start_idx = 0;\n\tinfo.direct_mode_sz = hw->hmc.hmc_obj[I40E_HMC_LAN_FULL].size;\n\n\t/* Build the SD entry for the LAN objects */\n\tswitch (model) {\n\tcase I40E_HMC_MODEL_DIRECT_PREFERRED:\n\tcase I40E_HMC_MODEL_DIRECT_ONLY:\n\t\tinfo.entry_type = I40E_SD_TYPE_DIRECT;\n\t\t/* Make one big object, a single SD */\n\t\tinfo.count = 1;\n\t\tret_code = i40e_create_lan_hmc_object(hw, &info);\n\t\tif ((ret_code != I40E_SUCCESS) && (model == I40E_HMC_MODEL_DIRECT_PREFERRED))\n\t\t\tgoto try_type_paged;\n\t\telse if (ret_code != I40E_SUCCESS)\n\t\t\tgoto configure_lan_hmc_out;\n\t\t/* else clause falls through the break */\n\t\tbreak;\n\tcase I40E_HMC_MODEL_PAGED_ONLY:\ntry_type_paged:\n\t\tinfo.entry_type = I40E_SD_TYPE_PAGED;\n\t\t/* Make one big object in the PD table */\n\t\tinfo.count = 1;\n\t\tret_code = i40e_create_lan_hmc_object(hw, &info);\n\t\tif (ret_code != I40E_SUCCESS)\n\t\t\tgoto configure_lan_hmc_out;\n\t\tbreak;\n\tdefault:\n\t\t/* unsupported type */\n\t\tret_code = I40E_ERR_INVALID_SD_TYPE;\n\t\tDEBUGOUT1(\"i40e_configure_lan_hmc: Unknown SD type: %d\\n\",\n\t\t\t ret_code);\n\t\tgoto configure_lan_hmc_out;\n\t}\n\n\t/* Configure and program the FPM registers so objects can be created */\n\n\t/* Tx contexts */\n\tobj = &hw->hmc.hmc_obj[I40E_HMC_LAN_TX];\n\twr32(hw, I40E_GLHMC_LANTXBASE(hmc_fn_id),\n\t (u32)((obj->base & I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK) / 512));\n\twr32(hw, I40E_GLHMC_LANTXCNT(hmc_fn_id), obj->cnt);\n\n\t/* Rx contexts */\n\tobj = &hw->hmc.hmc_obj[I40E_HMC_LAN_RX];\n\twr32(hw, I40E_GLHMC_LANRXBASE(hmc_fn_id),\n\t (u32)((obj->base & I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK) / 512));\n\twr32(hw, I40E_GLHMC_LANRXCNT(hmc_fn_id), obj->cnt);\n\n\t/* FCoE contexts */\n\tobj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX];\n\twr32(hw, I40E_GLHMC_FCOEDDPBASE(hmc_fn_id),\n\t (u32)((obj->base & I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK) / 512));\n\twr32(hw, I40E_GLHMC_FCOEDDPCNT(hmc_fn_id), obj->cnt);\n\n\t/* FCoE filters */\n\tobj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_FILT];\n\twr32(hw, I40E_GLHMC_FCOEFBASE(hmc_fn_id),\n\t (u32)((obj->base & I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK) / 512));\n\twr32(hw, I40E_GLHMC_FCOEFCNT(hmc_fn_id), obj->cnt);\n\nconfigure_lan_hmc_out:\n\treturn ret_code;\n}\n\n/**\n * i40e_delete_hmc_object - remove hmc objects\n * @hw: pointer to the HW structure\n * @info: pointer to i40e_hmc_delete_obj_info struct\n *\n * This will de-populate the SDs and PDs. It frees\n * the memory for PDS and backing storage. After this function is returned,\n * caller should deallocate memory allocated previously for\n * book-keeping information about PDs and backing storage.\n **/\nenum i40e_status_code i40e_delete_lan_hmc_object(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_hmc_lan_delete_obj_info *info)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tstruct i40e_hmc_pd_table *pd_table;\n\tu32 pd_idx, pd_lmt, rel_pd_idx;\n\tu32 sd_idx, sd_lmt;\n\tu32 i, j;\n\n\tif (NULL == info) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_delete_hmc_object: bad info ptr\\n\");\n\t\tgoto exit;\n\t}\n\tif (NULL == info->hmc_info) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_delete_hmc_object: bad info->hmc_info ptr\\n\");\n\t\tgoto exit;\n\t}\n\tif (I40E_HMC_INFO_SIGNATURE != info->hmc_info->signature) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_delete_hmc_object: bad hmc_info->signature\\n\");\n\t\tgoto exit;\n\t}\n\n\tif (NULL == info->hmc_info->sd_table.sd_entry) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_delete_hmc_object: bad sd_entry\\n\");\n\t\tgoto exit;\n\t}\n\n\tif (NULL == info->hmc_info->hmc_obj) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_delete_hmc_object: bad hmc_info->hmc_obj\\n\");\n\t\tgoto exit;\n\t}\n\tif (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) {\n\t\tret_code = I40E_ERR_INVALID_HMC_OBJ_INDEX;\n\t\tDEBUGOUT1(\"i40e_delete_hmc_object: returns error %d\\n\",\n\t\t\t ret_code);\n\t\tgoto exit;\n\t}\n\n\tif ((info->start_idx + info->count) >\n\t info->hmc_info->hmc_obj[info->rsrc_type].cnt) {\n\t\tret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;\n\t\tDEBUGOUT1(\"i40e_delete_hmc_object: returns error %d\\n\",\n\t\t\t ret_code);\n\t\tgoto exit;\n\t}\n\n\tI40E_FIND_PD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,\n\t\t\t\t info->start_idx, info->count, &pd_idx,\n\t\t\t\t &pd_lmt);\n\n\tfor (j = pd_idx; j < pd_lmt; j++) {\n\t\tsd_idx = j / I40E_HMC_PD_CNT_IN_SD;\n\n\t\tif (I40E_SD_TYPE_PAGED !=\n\t\t info->hmc_info->sd_table.sd_entry[sd_idx].entry_type)\n\t\t\tcontinue;\n\n\t\trel_pd_idx = j % I40E_HMC_PD_CNT_IN_SD;\n\n\t\tpd_table =\n\t\t\t&info->hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;\n\t\tif (pd_table->pd_entry[rel_pd_idx].valid) {\n\t\t\tret_code = i40e_remove_pd_bp(hw, info->hmc_info, j);\n\t\t\tif (I40E_SUCCESS != ret_code)\n\t\t\t\tgoto exit;\n\t\t}\n\t}\n\n\t/* find sd index and limit */\n\tI40E_FIND_SD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,\n\t\t\t\t info->start_idx, info->count,\n\t\t\t\t &sd_idx, &sd_lmt);\n\tif (sd_idx >= info->hmc_info->sd_table.sd_cnt ||\n\t sd_lmt > info->hmc_info->sd_table.sd_cnt) {\n\t\tret_code = I40E_ERR_INVALID_SD_INDEX;\n\t\tgoto exit;\n\t}\n\n\tfor (i = sd_idx; i < sd_lmt; i++) {\n\t\tif (!info->hmc_info->sd_table.sd_entry[i].valid)\n\t\t\tcontinue;\n\t\tswitch (info->hmc_info->sd_table.sd_entry[i].entry_type) {\n\t\tcase I40E_SD_TYPE_DIRECT:\n\t\t\tret_code = i40e_remove_sd_bp(hw, info->hmc_info, i);\n\t\t\tif (I40E_SUCCESS != ret_code)\n\t\t\t\tgoto exit;\n\t\t\tbreak;\n\t\tcase I40E_SD_TYPE_PAGED:\n\t\t\tret_code = i40e_remove_pd_page(hw, info->hmc_info, i);\n\t\t\tif (I40E_SUCCESS != ret_code)\n\t\t\t\tgoto exit;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\nexit:\n\treturn ret_code;\n}\n\n/**\n * i40e_shutdown_lan_hmc - Remove HMC backing store, free allocated memory\n * @hw: pointer to the hw structure\n *\n * This must be called by drivers as they are shutting down and being\n * removed from the OS.\n **/\nenum i40e_status_code i40e_shutdown_lan_hmc(struct i40e_hw *hw)\n{\n\tstruct i40e_hmc_lan_delete_obj_info info;\n\tenum i40e_status_code ret_code;\n\n\tinfo.hmc_info = &hw->hmc;\n\tinfo.rsrc_type = I40E_HMC_LAN_FULL;\n\tinfo.start_idx = 0;\n\tinfo.count = 1;\n\n\t/* delete the object */\n\tret_code = i40e_delete_lan_hmc_object(hw, &info);\n\n\t/* free the SD table entry for LAN */\n\ti40e_free_virt_mem(hw, &hw->hmc.sd_table.addr);\n\thw->hmc.sd_table.sd_cnt = 0;\n\thw->hmc.sd_table.sd_entry = NULL;\n\n\t/* free memory used for hmc_obj */\n\ti40e_free_virt_mem(hw, &hw->hmc.hmc_obj_virt_mem);\n\thw->hmc.hmc_obj = NULL;\n\n\treturn ret_code;\n}\n\n#define I40E_HMC_STORE(_struct, _ele)\t\t\\\n\toffsetof(struct _struct, _ele),\t\t\\\n\tFIELD_SIZEOF(struct _struct, _ele)\n\nstruct i40e_context_ele {\n\tu16 offset;\n\tu16 size_of;\n\tu16 width;\n\tu16 lsb;\n};\n\n/* LAN Tx Queue Context */\nstatic struct i40e_context_ele i40e_hmc_txq_ce_info[] = {\n\t\t\t\t\t /* Field Width LSB */\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, head), 13, 0 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, new_context), 1, 30 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, base), 57, 32 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, fc_ena), 1, 89 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, timesync_ena), 1, 90 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, fd_ena), 1, 91 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, alt_vlan_ena), 1, 92 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, cpuid), 8, 96 },\n/* line 1 */\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, thead_wb), 13, 0 + 128 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, head_wb_ena), 1, 32 + 128 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, qlen), 13, 33 + 128 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, tphrdesc_ena), 1, 46 + 128 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, tphrpacket_ena), 1, 47 + 128 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, tphwdesc_ena), 1, 48 + 128 },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, head_wb_addr), 64, 64 + 128 },\n/* line 7 */\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, crc), 32, 0 + (7 * 128) },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, rdylist), 10, 84 + (7 * 128) },\n\t{I40E_HMC_STORE(i40e_hmc_obj_txq, rdylist_act), 1, 94 + (7 * 128) },\n\t{ 0 }\n};\n\n/* LAN Rx Queue Context */\nstatic struct i40e_context_ele i40e_hmc_rxq_ce_info[] = {\n\t\t\t\t\t /* Field Width LSB */\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, head), 13,\t0 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, cpuid), 8,\t13 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, base), 57,\t32 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, qlen), 13,\t89 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, dbuff), 7,\t102 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, hbuff), 5,\t109 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, dtype), 2,\t114 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, dsize), 1,\t116 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, crcstrip), 1,\t117 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, fc_ena), 1,\t118 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, l2tsel), 1,\t119 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, hsplit_0), 4,\t120 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, hsplit_1), 2,\t124 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, showiv), 1,\t127 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, rxmax), 14,\t174 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, tphrdesc_ena), 1,\t193 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, tphwdesc_ena), 1,\t194 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, tphdata_ena), 1,\t195 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, tphhead_ena), 1,\t196 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, lrxqthresh), 3,\t198 },\n\t{ I40E_HMC_STORE(i40e_hmc_obj_rxq, prefena), 1,\t201 },\n\t{ 0 }\n};\n\n/**\n * i40e_write_byte - replace HMC context byte\n * @hmc_bits: pointer to the HMC memory\n * @ce_info: a description of the struct to be read from\n * @src: the struct to be read from\n **/\nstatic void i40e_write_byte(u8 *hmc_bits,\n\t\t\t struct i40e_context_ele *ce_info,\n\t\t\t u8 *src)\n{\n\tu8 src_byte, dest_byte, mask;\n\tu8 *from, *dest;\n\tu16 shift_width;\n\n\t/* copy from the next struct field */\n\tfrom = src + ce_info->offset;\n\n\t/* prepare the bits and mask */\n\tshift_width = ce_info->lsb % 8;\n\tmask = ((u8)1 << ce_info->width) - 1;\n\n\tsrc_byte = *from;\n\tsrc_byte &= mask;\n\n\t/* shift to correct alignment */\n\tmask <<= shift_width;\n\tsrc_byte <<= shift_width;\n\n\t/* get the current bits from the target bit string */\n\tdest = hmc_bits + (ce_info->lsb / 8);\n\n\ti40e_memcpy(&dest_byte, dest, sizeof(dest_byte), I40E_DMA_TO_NONDMA);\n\n\tdest_byte &= ~mask;\t/* get the bits not changing */\n\tdest_byte |= src_byte;\t/* add in the new bits */\n\n\t/* put it all back */\n\ti40e_memcpy(dest, &dest_byte, sizeof(dest_byte), I40E_NONDMA_TO_DMA);\n}\n\n/**\n * i40e_write_word - replace HMC context word\n * @hmc_bits: pointer to the HMC memory\n * @ce_info: a description of the struct to be read from\n * @src: the struct to be read from\n **/\nstatic void i40e_write_word(u8 *hmc_bits,\n\t\t\t struct i40e_context_ele *ce_info,\n\t\t\t u8 *src)\n{\n\tu16 src_word, mask;\n\tu8 *from, *dest;\n\tu16 shift_width;\n\t__le16 dest_word;\n\n\t/* copy from the next struct field */\n\tfrom = src + ce_info->offset;\n\n\t/* prepare the bits and mask */\n\tshift_width = ce_info->lsb % 8;\n\tmask = ((u16)1 << ce_info->width) - 1;\n\n\t/* don't swizzle the bits until after the mask because the mask bits\n\t * will be in a different bit position on big endian machines\n\t */\n\tsrc_word = *(u16 *)from;\n\tsrc_word &= mask;\n\n\t/* shift to correct alignment */\n\tmask <<= shift_width;\n\tsrc_word <<= shift_width;\n\n\t/* get the current bits from the target bit string */\n\tdest = hmc_bits + (ce_info->lsb / 8);\n\n\ti40e_memcpy(&dest_word, dest, sizeof(dest_word), I40E_DMA_TO_NONDMA);\n\n\tdest_word &= ~(CPU_TO_LE16(mask));\t/* get the bits not changing */\n\tdest_word |= CPU_TO_LE16(src_word);\t/* add in the new bits */\n\n\t/* put it all back */\n\ti40e_memcpy(dest, &dest_word, sizeof(dest_word), I40E_NONDMA_TO_DMA);\n}\n\n/**\n * i40e_write_dword - replace HMC context dword\n * @hmc_bits: pointer to the HMC memory\n * @ce_info: a description of the struct to be read from\n * @src: the struct to be read from\n **/\nstatic void i40e_write_dword(u8 *hmc_bits,\n\t\t\t struct i40e_context_ele *ce_info,\n\t\t\t u8 *src)\n{\n\tu32 src_dword, mask;\n\tu8 *from, *dest;\n\tu16 shift_width;\n\t__le32 dest_dword;\n\n\t/* copy from the next struct field */\n\tfrom = src + ce_info->offset;\n\n\t/* prepare the bits and mask */\n\tshift_width = ce_info->lsb % 8;\n\n\t/* if the field width is exactly 32 on an x86 machine, then the shift\n\t * operation will not work because the SHL instructions count is masked\n\t * to 5 bits so the shift will do nothing\n\t */\n\tif (ce_info->width < 32)\n\t\tmask = ((u32)1 << ce_info->width) - 1;\n\telse\n\t\tmask = ~(u32)0;\n\n\t/* don't swizzle the bits until after the mask because the mask bits\n\t * will be in a different bit position on big endian machines\n\t */\n\tsrc_dword = *(u32 *)from;\n\tsrc_dword &= mask;\n\n\t/* shift to correct alignment */\n\tmask <<= shift_width;\n\tsrc_dword <<= shift_width;\n\n\t/* get the current bits from the target bit string */\n\tdest = hmc_bits + (ce_info->lsb / 8);\n\n\ti40e_memcpy(&dest_dword, dest, sizeof(dest_dword), I40E_DMA_TO_NONDMA);\n\n\tdest_dword &= ~(CPU_TO_LE32(mask));\t/* get the bits not changing */\n\tdest_dword |= CPU_TO_LE32(src_dword);\t/* add in the new bits */\n\n\t/* put it all back */\n\ti40e_memcpy(dest, &dest_dword, sizeof(dest_dword), I40E_NONDMA_TO_DMA);\n}\n\n/**\n * i40e_write_qword - replace HMC context qword\n * @hmc_bits: pointer to the HMC memory\n * @ce_info: a description of the struct to be read from\n * @src: the struct to be read from\n **/\nstatic void i40e_write_qword(u8 *hmc_bits,\n\t\t\t struct i40e_context_ele *ce_info,\n\t\t\t u8 *src)\n{\n\tu64 src_qword, mask;\n\tu8 *from, *dest;\n\tu16 shift_width;\n\t__le64 dest_qword;\n\n\t/* copy from the next struct field */\n\tfrom = src + ce_info->offset;\n\n\t/* prepare the bits and mask */\n\tshift_width = ce_info->lsb % 8;\n\n\t/* if the field width is exactly 64 on an x86 machine, then the shift\n\t * operation will not work because the SHL instructions count is masked\n\t * to 6 bits so the shift will do nothing\n\t */\n\tif (ce_info->width < 64)\n\t\tmask = ((u64)1 << ce_info->width) - 1;\n\telse\n\t\tmask = ~(u64)0;\n\n\t/* don't swizzle the bits until after the mask because the mask bits\n\t * will be in a different bit position on big endian machines\n\t */\n\tsrc_qword = *(u64 *)from;\n\tsrc_qword &= mask;\n\n\t/* shift to correct alignment */\n\tmask <<= shift_width;\n\tsrc_qword <<= shift_width;\n\n\t/* get the current bits from the target bit string */\n\tdest = hmc_bits + (ce_info->lsb / 8);\n\n\ti40e_memcpy(&dest_qword, dest, sizeof(dest_qword), I40E_DMA_TO_NONDMA);\n\n\tdest_qword &= ~(CPU_TO_LE64(mask));\t/* get the bits not changing */\n\tdest_qword |= CPU_TO_LE64(src_qword);\t/* add in the new bits */\n\n\t/* put it all back */\n\ti40e_memcpy(dest, &dest_qword, sizeof(dest_qword), I40E_NONDMA_TO_DMA);\n}\n\n/**\n * i40e_read_byte - read HMC context byte into struct\n * @hmc_bits: pointer to the HMC memory\n * @ce_info: a description of the struct to be filled\n * @dest: the struct to be filled\n **/\nstatic void i40e_read_byte(u8 *hmc_bits,\n\t\t\t struct i40e_context_ele *ce_info,\n\t\t\t u8 *dest)\n{\n\tu8 dest_byte, mask;\n\tu8 *src, *target;\n\tu16 shift_width;\n\n\t/* prepare the bits and mask */\n\tshift_width = ce_info->lsb % 8;\n\tmask = ((u8)1 << ce_info->width) - 1;\n\n\t/* shift to correct alignment */\n\tmask <<= shift_width;\n\n\t/* get the current bits from the src bit string */\n\tsrc = hmc_bits + (ce_info->lsb / 8);\n\n\ti40e_memcpy(&dest_byte, src, sizeof(dest_byte), I40E_DMA_TO_NONDMA);\n\n\tdest_byte &= ~(mask);\n\n\tdest_byte >>= shift_width;\n\n\t/* get the address from the struct field */\n\ttarget = dest + ce_info->offset;\n\n\t/* put it back in the struct */\n\ti40e_memcpy(target, &dest_byte, sizeof(dest_byte), I40E_NONDMA_TO_DMA);\n}\n\n/**\n * i40e_read_word - read HMC context word into struct\n * @hmc_bits: pointer to the HMC memory\n * @ce_info: a description of the struct to be filled\n * @dest: the struct to be filled\n **/\nstatic void i40e_read_word(u8 *hmc_bits,\n\t\t\t struct i40e_context_ele *ce_info,\n\t\t\t u8 *dest)\n{\n\tu16 dest_word, mask;\n\tu8 *src, *target;\n\tu16 shift_width;\n\t__le16 src_word;\n\n\t/* prepare the bits and mask */\n\tshift_width = ce_info->lsb % 8;\n\tmask = ((u16)1 << ce_info->width) - 1;\n\n\t/* shift to correct alignment */\n\tmask <<= shift_width;\n\n\t/* get the current bits from the src bit string */\n\tsrc = hmc_bits + (ce_info->lsb / 8);\n\n\ti40e_memcpy(&src_word, src, sizeof(src_word), I40E_DMA_TO_NONDMA);\n\n\t/* the data in the memory is stored as little endian so mask it\n\t * correctly\n\t */\n\tsrc_word &= ~(CPU_TO_LE16(mask));\n\n\t/* get the data back into host order before shifting */\n\tdest_word = LE16_TO_CPU(src_word);\n\n\tdest_word >>= shift_width;\n\n\t/* get the address from the struct field */\n\ttarget = dest + ce_info->offset;\n\n\t/* put it back in the struct */\n\ti40e_memcpy(target, &dest_word, sizeof(dest_word), I40E_NONDMA_TO_DMA);\n}\n\n/**\n * i40e_read_dword - read HMC context dword into struct\n * @hmc_bits: pointer to the HMC memory\n * @ce_info: a description of the struct to be filled\n * @dest: the struct to be filled\n **/\nstatic void i40e_read_dword(u8 *hmc_bits,\n\t\t\t struct i40e_context_ele *ce_info,\n\t\t\t u8 *dest)\n{\n\tu32 dest_dword, mask;\n\tu8 *src, *target;\n\tu16 shift_width;\n\t__le32 src_dword;\n\n\t/* prepare the bits and mask */\n\tshift_width = ce_info->lsb % 8;\n\n\t/* if the field width is exactly 32 on an x86 machine, then the shift\n\t * operation will not work because the SHL instructions count is masked\n\t * to 5 bits so the shift will do nothing\n\t */\n\tif (ce_info->width < 32)\n\t\tmask = ((u32)1 << ce_info->width) - 1;\n\telse\n\t\tmask = ~(u32)0;\n\n\t/* shift to correct alignment */\n\tmask <<= shift_width;\n\n\t/* get the current bits from the src bit string */\n\tsrc = hmc_bits + (ce_info->lsb / 8);\n\n\ti40e_memcpy(&src_dword, src, sizeof(src_dword), I40E_DMA_TO_NONDMA);\n\n\t/* the data in the memory is stored as little endian so mask it\n\t * correctly\n\t */\n\tsrc_dword &= ~(CPU_TO_LE32(mask));\n\n\t/* get the data back into host order before shifting */\n\tdest_dword = LE32_TO_CPU(src_dword);\n\n\tdest_dword >>= shift_width;\n\n\t/* get the address from the struct field */\n\ttarget = dest + ce_info->offset;\n\n\t/* put it back in the struct */\n\ti40e_memcpy(target, &dest_dword, sizeof(dest_dword),\n\t\t I40E_NONDMA_TO_DMA);\n}\n\n/**\n * i40e_read_qword - read HMC context qword into struct\n * @hmc_bits: pointer to the HMC memory\n * @ce_info: a description of the struct to be filled\n * @dest: the struct to be filled\n **/\nstatic void i40e_read_qword(u8 *hmc_bits,\n\t\t\t struct i40e_context_ele *ce_info,\n\t\t\t u8 *dest)\n{\n\tu64 dest_qword, mask;\n\tu8 *src, *target;\n\tu16 shift_width;\n\t__le64 src_qword;\n\n\t/* prepare the bits and mask */\n\tshift_width = ce_info->lsb % 8;\n\n\t/* if the field width is exactly 64 on an x86 machine, then the shift\n\t * operation will not work because the SHL instructions count is masked\n\t * to 6 bits so the shift will do nothing\n\t */\n\tif (ce_info->width < 64)\n\t\tmask = ((u64)1 << ce_info->width) - 1;\n\telse\n\t\tmask = ~(u64)0;\n\n\t/* shift to correct alignment */\n\tmask <<= shift_width;\n\n\t/* get the current bits from the src bit string */\n\tsrc = hmc_bits + (ce_info->lsb / 8);\n\n\ti40e_memcpy(&src_qword, src, sizeof(src_qword), I40E_DMA_TO_NONDMA);\n\n\t/* the data in the memory is stored as little endian so mask it\n\t * correctly\n\t */\n\tsrc_qword &= ~(CPU_TO_LE64(mask));\n\n\t/* get the data back into host order before shifting */\n\tdest_qword = LE64_TO_CPU(src_qword);\n\n\tdest_qword >>= shift_width;\n\n\t/* get the address from the struct field */\n\ttarget = dest + ce_info->offset;\n\n\t/* put it back in the struct */\n\ti40e_memcpy(target, &dest_qword, sizeof(dest_qword),\n\t\t I40E_NONDMA_TO_DMA);\n}\n\n/**\n * i40e_get_hmc_context - extract HMC context bits\n * @context_bytes: pointer to the context bit array\n * @ce_info: a description of the struct to be filled\n * @dest: the struct to be filled\n **/\nstatic enum i40e_status_code i40e_get_hmc_context(u8 *context_bytes,\n\t\t\t\t\tstruct i40e_context_ele *ce_info,\n\t\t\t\t\tu8 *dest)\n{\n\tint f;\n\n\tfor (f = 0; ce_info[f].width != 0; f++) {\n\t\tswitch (ce_info[f].size_of) {\n\t\tcase 1:\n\t\t\ti40e_read_byte(context_bytes, &ce_info[f], dest);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\ti40e_read_word(context_bytes, &ce_info[f], dest);\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\ti40e_read_dword(context_bytes, &ce_info[f], dest);\n\t\t\tbreak;\n\t\tcase 8:\n\t\t\ti40e_read_qword(context_bytes, &ce_info[f], dest);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* nothing to do, just keep going */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn I40E_SUCCESS;\n}\n\n/**\n * i40e_clear_hmc_context - zero out the HMC context bits\n * @hw: the hardware struct\n * @context_bytes: pointer to the context bit array (DMA memory)\n * @hmc_type: the type of HMC resource\n **/\nstatic enum i40e_status_code i40e_clear_hmc_context(struct i40e_hw *hw,\n\t\t\t\t\tu8 *context_bytes,\n\t\t\t\t\tenum i40e_hmc_lan_rsrc_type hmc_type)\n{\n\t/* clean the bit array */\n\ti40e_memset(context_bytes, 0, (u32)hw->hmc.hmc_obj[hmc_type].size,\n\t\t I40E_DMA_MEM);\n\n\treturn I40E_SUCCESS;\n}\n\n/**\n * i40e_set_hmc_context - replace HMC context bits\n * @context_bytes: pointer to the context bit array\n * @ce_info: a description of the struct to be filled\n * @dest: the struct to be filled\n **/\nstatic enum i40e_status_code i40e_set_hmc_context(u8 *context_bytes,\n\t\t\t\t\tstruct i40e_context_ele *ce_info,\n\t\t\t\t\tu8 *dest)\n{\n\tint f;\n\n\tfor (f = 0; ce_info[f].width != 0; f++) {\n\n\t\t/* we have to deal with each element of the HMC using the\n\t\t * correct size so that we are correct regardless of the\n\t\t * endianness of the machine\n\t\t */\n\t\tswitch (ce_info[f].size_of) {\n\t\tcase 1:\n\t\t\ti40e_write_byte(context_bytes, &ce_info[f], dest);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\ti40e_write_word(context_bytes, &ce_info[f], dest);\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\ti40e_write_dword(context_bytes, &ce_info[f], dest);\n\t\t\tbreak;\n\t\tcase 8:\n\t\t\ti40e_write_qword(context_bytes, &ce_info[f], dest);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn I40E_SUCCESS;\n}\n\n/**\n * i40e_hmc_get_object_va - retrieves an object's virtual address\n * @hw: pointer to the hw structure\n * @object_base: pointer to u64 to get the va\n * @rsrc_type: the hmc resource type\n * @obj_idx: hmc object index\n *\n * This function retrieves the object's virtual address from the object\n * base pointer. This function is used for LAN Queue contexts.\n **/\nSTATIC\nenum i40e_status_code i40e_hmc_get_object_va(struct i40e_hw *hw,\n\t\t\t\t\tu8 **object_base,\n\t\t\t\t\tenum i40e_hmc_lan_rsrc_type rsrc_type,\n\t\t\t\t\tu32 obj_idx)\n{\n\tu32 obj_offset_in_sd, obj_offset_in_pd;\n\tstruct i40e_hmc_info *hmc_info = &hw->hmc;\n\tstruct i40e_hmc_sd_entry *sd_entry;\n\tstruct i40e_hmc_pd_entry *pd_entry;\n\tu32 pd_idx, pd_lmt, rel_pd_idx;\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tu64 obj_offset_in_fpm;\n\tu32 sd_idx, sd_lmt;\n\n\tif (NULL == hmc_info) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_hmc_get_object_va: bad hmc_info ptr\\n\");\n\t\tgoto exit;\n\t}\n\tif (NULL == hmc_info->hmc_obj) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_hmc_get_object_va: bad hmc_info->hmc_obj ptr\\n\");\n\t\tgoto exit;\n\t}\n\tif (NULL == object_base) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_hmc_get_object_va: bad object_base ptr\\n\");\n\t\tgoto exit;\n\t}\n\tif (I40E_HMC_INFO_SIGNATURE != hmc_info->signature) {\n\t\tret_code = I40E_ERR_BAD_PTR;\n\t\tDEBUGOUT(\"i40e_hmc_get_object_va: bad hmc_info->signature\\n\");\n\t\tgoto exit;\n\t}\n\tif (obj_idx >= hmc_info->hmc_obj[rsrc_type].cnt) {\n\t\tDEBUGOUT1(\"i40e_hmc_get_object_va: returns error %d\\n\",\n\t\t\t ret_code);\n\t\tret_code = I40E_ERR_INVALID_HMC_OBJ_INDEX;\n\t\tgoto exit;\n\t}\n\t/* find sd index and limit */\n\tI40E_FIND_SD_INDEX_LIMIT(hmc_info, rsrc_type, obj_idx, 1,\n\t\t\t\t &sd_idx, &sd_lmt);\n\n\tsd_entry = &hmc_info->sd_table.sd_entry[sd_idx];\n\tobj_offset_in_fpm = hmc_info->hmc_obj[rsrc_type].base +\n\t\t\t hmc_info->hmc_obj[rsrc_type].size * obj_idx;\n\n\tif (I40E_SD_TYPE_PAGED == sd_entry->entry_type) {\n\t\tI40E_FIND_PD_INDEX_LIMIT(hmc_info, rsrc_type, obj_idx, 1,\n\t\t\t\t\t &pd_idx, &pd_lmt);\n\t\trel_pd_idx = pd_idx % I40E_HMC_PD_CNT_IN_SD;\n\t\tpd_entry = &sd_entry->u.pd_table.pd_entry[rel_pd_idx];\n\t\tobj_offset_in_pd = (u32)(obj_offset_in_fpm %\n\t\t\t\t\t I40E_HMC_PAGED_BP_SIZE);\n\t\t*object_base = (u8 *)pd_entry->bp.addr.va + obj_offset_in_pd;\n\t} else {\n\t\tobj_offset_in_sd = (u32)(obj_offset_in_fpm %\n\t\t\t\t\t I40E_HMC_DIRECT_BP_SIZE);\n\t\t*object_base = (u8 *)sd_entry->u.bp.addr.va + obj_offset_in_sd;\n\t}\nexit:\n\treturn ret_code;\n}\n\n/**\n * i40e_get_lan_tx_queue_context - return the HMC context for the queue\n * @hw: the hardware struct\n * @queue: the queue we care about\n * @s: the struct to be filled\n **/\nenum i40e_status_code i40e_get_lan_tx_queue_context(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 queue,\n\t\t\t\t\t\t struct i40e_hmc_obj_txq *s)\n{\n\tenum i40e_status_code err;\n\tu8 *context_bytes;\n\n\terr = i40e_hmc_get_object_va(hw, &context_bytes, I40E_HMC_LAN_TX, queue);\n\tif (err < 0)\n\t\treturn err;\n\n\treturn i40e_get_hmc_context(context_bytes,\n\t\t\t\t i40e_hmc_txq_ce_info, (u8 *)s);\n}\n\n/**\n * i40e_clear_lan_tx_queue_context - clear the HMC context for the queue\n * @hw: the hardware struct\n * @queue: the queue we care about\n **/\nenum i40e_status_code i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 queue)\n{\n\tenum i40e_status_code err;\n\tu8 *context_bytes;\n\n\terr = i40e_hmc_get_object_va(hw, &context_bytes, I40E_HMC_LAN_TX, queue);\n\tif (err < 0)\n\t\treturn err;\n\n\treturn i40e_clear_hmc_context(hw, context_bytes, I40E_HMC_LAN_TX);\n}\n\n/**\n * i40e_set_lan_tx_queue_context - set the HMC context for the queue\n * @hw: the hardware struct\n * @queue: the queue we care about\n * @s: the struct to be filled\n **/\nenum i40e_status_code i40e_set_lan_tx_queue_context(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 queue,\n\t\t\t\t\t\t struct i40e_hmc_obj_txq *s)\n{\n\tenum i40e_status_code err;\n\tu8 *context_bytes;\n\n\terr = i40e_hmc_get_object_va(hw, &context_bytes, I40E_HMC_LAN_TX, queue);\n\tif (err < 0)\n\t\treturn err;\n\n\treturn i40e_set_hmc_context(context_bytes,\n\t\t\t\t i40e_hmc_txq_ce_info, (u8 *)s);\n}\n\n/**\n * i40e_get_lan_rx_queue_context - return the HMC context for the queue\n * @hw: the hardware struct\n * @queue: the queue we care about\n * @s: the struct to be filled\n **/\nenum i40e_status_code i40e_get_lan_rx_queue_context(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 queue,\n\t\t\t\t\t\t struct i40e_hmc_obj_rxq *s)\n{\n\tenum i40e_status_code err;\n\tu8 *context_bytes;\n\n\terr = i40e_hmc_get_object_va(hw, &context_bytes, I40E_HMC_LAN_RX, queue);\n\tif (err < 0)\n\t\treturn err;\n\n\treturn i40e_get_hmc_context(context_bytes,\n\t\t\t\t i40e_hmc_rxq_ce_info, (u8 *)s);\n}\n\n/**\n * i40e_clear_lan_rx_queue_context - clear the HMC context for the queue\n * @hw: the hardware struct\n * @queue: the queue we care about\n **/\nenum i40e_status_code i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 queue)\n{\n\tenum i40e_status_code err;\n\tu8 *context_bytes;\n\n\terr = i40e_hmc_get_object_va(hw, &context_bytes, I40E_HMC_LAN_RX, queue);\n\tif (err < 0)\n\t\treturn err;\n\n\treturn i40e_clear_hmc_context(hw, context_bytes, I40E_HMC_LAN_RX);\n}\n\n/**\n * i40e_set_lan_rx_queue_context - set the HMC context for the queue\n * @hw: the hardware struct\n * @queue: the queue we care about\n * @s: the struct to be filled\n **/\nenum i40e_status_code i40e_set_lan_rx_queue_context(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 queue,\n\t\t\t\t\t\t struct i40e_hmc_obj_rxq *s)\n{\n\tenum i40e_status_code err;\n\tu8 *context_bytes;\n\n\terr = i40e_hmc_get_object_va(hw, &context_bytes, I40E_HMC_LAN_RX, queue);\n\tif (err < 0)\n\t\treturn err;\n\n\treturn i40e_set_hmc_context(context_bytes,\n\t\t\t\t i40e_hmc_rxq_ce_info, (u8 *)s);\n}\n" }, { "path": "drivers/net/i40e/base/i40e_lan_hmc.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _I40E_LAN_HMC_H_\n#define _I40E_LAN_HMC_H_\n\n/* forward-declare the HW struct for the compiler */\nstruct i40e_hw;\n\n/* HMC element context information */\n\n/* Rx queue context data\n *\n * The sizes of the variables may be larger than needed due to crossing byte\n * boundaries. If we do not have the width of the variable set to the correct\n * size then we could end up shifting bits off the top of the variable when the\n * variable is at the top of a byte and crosses over into the next byte.\n */\nstruct i40e_hmc_obj_rxq {\n\tu16 head;\n\tu16 cpuid; /* bigger than needed, see above for reason */\n\tu64 base;\n\tu16 qlen;\n#define I40E_RXQ_CTX_DBUFF_SHIFT 7\n\tu16 dbuff; /* bigger than needed, see above for reason */\n#define I40E_RXQ_CTX_HBUFF_SHIFT 6\n\tu16 hbuff; /* bigger than needed, see above for reason */\n\tu8 dtype;\n\tu8 dsize;\n\tu8 crcstrip;\n\tu8 fc_ena;\n\tu8 l2tsel;\n\tu8 hsplit_0;\n\tu8 hsplit_1;\n\tu8 showiv;\n\tu32 rxmax; /* bigger than needed, see above for reason */\n\tu8 tphrdesc_ena;\n\tu8 tphwdesc_ena;\n\tu8 tphdata_ena;\n\tu8 tphhead_ena;\n\tu16 lrxqthresh; /* bigger than needed, see above for reason */\n\tu8 prefena;\t/* NOTE: normally must be set to 1 at init */\n};\n\n/* Tx queue context data\n*\n* The sizes of the variables may be larger than needed due to crossing byte\n* boundaries. If we do not have the width of the variable set to the correct\n* size then we could end up shifting bits off the top of the variable when the\n* variable is at the top of a byte and crosses over into the next byte.\n*/\nstruct i40e_hmc_obj_txq {\n\tu16 head;\n\tu8 new_context;\n\tu64 base;\n\tu8 fc_ena;\n\tu8 timesync_ena;\n\tu8 fd_ena;\n\tu8 alt_vlan_ena;\n\tu16 thead_wb;\n\tu8 cpuid;\n\tu8 head_wb_ena;\n\tu16 qlen;\n\tu8 tphrdesc_ena;\n\tu8 tphrpacket_ena;\n\tu8 tphwdesc_ena;\n\tu64 head_wb_addr;\n\tu32 crc;\n\tu16 rdylist;\n\tu8 rdylist_act;\n};\n\n/* for hsplit_0 field of Rx HMC context */\nenum i40e_hmc_obj_rx_hsplit_0 {\n\tI40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0,\n\tI40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1,\n\tI40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2,\n\tI40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,\n\tI40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8,\n};\n\n/* fcoe_cntx and fcoe_filt are for debugging purpose only */\nstruct i40e_hmc_obj_fcoe_cntx {\n\tu32 rsv[32];\n};\n\nstruct i40e_hmc_obj_fcoe_filt {\n\tu32 rsv[8];\n};\n\n/* Context sizes for LAN objects */\nenum i40e_hmc_lan_object_size {\n\tI40E_HMC_LAN_OBJ_SZ_8 = 0x3,\n\tI40E_HMC_LAN_OBJ_SZ_16 = 0x4,\n\tI40E_HMC_LAN_OBJ_SZ_32 = 0x5,\n\tI40E_HMC_LAN_OBJ_SZ_64 = 0x6,\n\tI40E_HMC_LAN_OBJ_SZ_128 = 0x7,\n\tI40E_HMC_LAN_OBJ_SZ_256 = 0x8,\n\tI40E_HMC_LAN_OBJ_SZ_512 = 0x9,\n};\n\n#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512\n#define I40E_HMC_OBJ_SIZE_TXQ 128\n#define I40E_HMC_OBJ_SIZE_RXQ 32\n#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 64\n#define I40E_HMC_OBJ_SIZE_FCOE_FILT 64\n\nenum i40e_hmc_lan_rsrc_type {\n\tI40E_HMC_LAN_FULL = 0,\n\tI40E_HMC_LAN_TX = 1,\n\tI40E_HMC_LAN_RX = 2,\n\tI40E_HMC_FCOE_CTX = 3,\n\tI40E_HMC_FCOE_FILT = 4,\n\tI40E_HMC_LAN_MAX = 5\n};\n\nenum i40e_hmc_model {\n\tI40E_HMC_MODEL_DIRECT_PREFERRED = 0,\n\tI40E_HMC_MODEL_DIRECT_ONLY = 1,\n\tI40E_HMC_MODEL_PAGED_ONLY = 2,\n\tI40E_HMC_MODEL_UNKNOWN,\n};\n\nstruct i40e_hmc_lan_create_obj_info {\n\tstruct i40e_hmc_info *hmc_info;\n\tu32 rsrc_type;\n\tu32 start_idx;\n\tu32 count;\n\tenum i40e_sd_entry_type entry_type;\n\tu64 direct_mode_sz;\n};\n\nstruct i40e_hmc_lan_delete_obj_info {\n\tstruct i40e_hmc_info *hmc_info;\n\tu32 rsrc_type;\n\tu32 start_idx;\n\tu32 count;\n};\n\nenum i40e_status_code i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,\n\t\t\t\t\tu32 rxq_num, u32 fcoe_cntx_num,\n\t\t\t\t\tu32 fcoe_filt_num);\nenum i40e_status_code i40e_configure_lan_hmc(struct i40e_hw *hw,\n\t\t\t\t\t enum i40e_hmc_model model);\nenum i40e_status_code i40e_shutdown_lan_hmc(struct i40e_hw *hw);\n\nu64 i40e_calculate_l2fpm_size(u32 txq_num, u32 rxq_num,\n\t\t\t u32 fcoe_cntx_num, u32 fcoe_filt_num);\nenum i40e_status_code i40e_get_lan_tx_queue_context(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 queue,\n\t\t\t\t\t\t struct i40e_hmc_obj_txq *s);\nenum i40e_status_code i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 queue);\nenum i40e_status_code i40e_set_lan_tx_queue_context(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 queue,\n\t\t\t\t\t\t struct i40e_hmc_obj_txq *s);\nenum i40e_status_code i40e_get_lan_rx_queue_context(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 queue,\n\t\t\t\t\t\t struct i40e_hmc_obj_rxq *s);\nenum i40e_status_code i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 queue);\nenum i40e_status_code i40e_set_lan_rx_queue_context(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 queue,\n\t\t\t\t\t\t struct i40e_hmc_obj_rxq *s);\nenum i40e_status_code i40e_create_lan_hmc_object(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_hmc_lan_create_obj_info *info);\nenum i40e_status_code i40e_delete_lan_hmc_object(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_hmc_lan_delete_obj_info *info);\n\n#endif /* _I40E_LAN_HMC_H_ */\n" }, { "path": "drivers/net/i40e/base/i40e_nvm.c", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"i40e_prototype.h\"\n\nenum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,\n\t\t\t\t\t u16 *data);\nenum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,\n\t\t\t\t\t u16 *data);\nenum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,\n\t\t\t\t\t\t u16 *words, u16 *data);\nenum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,\n\t\t\t\t\t u16 *words, u16 *data);\nenum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,\n\t\t\t\t u32 offset, u16 words, void *data,\n\t\t\t\t bool last_command);\n\n/**\n * i40e_init_nvm_ops - Initialize NVM function pointers\n * @hw: pointer to the HW structure\n *\n * Setup the function pointers and the NVM info structure. Should be called\n * once per NVM initialization, e.g. inside the i40e_init_shared_code().\n * Please notice that the NVM term is used here (& in all methods covered\n * in this file) as an equivalent of the FLASH part mapped into the SR.\n * We are accessing FLASH always thru the Shadow RAM.\n **/\nenum i40e_status_code i40e_init_nvm(struct i40e_hw *hw)\n{\n\tstruct i40e_nvm_info *nvm = &hw->nvm;\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tu32 fla, gens;\n\tu8 sr_size;\n\n\tDEBUGFUNC(\"i40e_init_nvm\");\n\n\t/* The SR size is stored regardless of the nvm programming mode\n\t * as the blank mode may be used in the factory line.\n\t */\n\tgens = rd32(hw, I40E_GLNVM_GENS);\n\tsr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>\n\t\t\t I40E_GLNVM_GENS_SR_SIZE_SHIFT);\n\t/* Switching to words (sr_size contains power of 2KB) */\n\tnvm->sr_size = (1 << sr_size) * I40E_SR_WORDS_IN_1KB;\n\n\t/* Check if we are in the normal or blank NVM programming mode */\n\tfla = rd32(hw, I40E_GLNVM_FLA);\n\tif (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */\n\t\t/* Max NVM timeout */\n\t\tnvm->timeout = I40E_MAX_NVM_TIMEOUT;\n\t\tnvm->blank_nvm_mode = false;\n\t} else { /* Blank programming mode */\n\t\tnvm->blank_nvm_mode = true;\n\t\tret_code = I40E_ERR_NVM_BLANK_MODE;\n\t\ti40e_debug(hw, I40E_DEBUG_NVM, \"NVM init error: unsupported blank mode.\\n\");\n\t}\n\n\treturn ret_code;\n}\n\n/**\n * i40e_acquire_nvm - Generic request for acquiring the NVM ownership\n * @hw: pointer to the HW structure\n * @access: NVM access type (read or write)\n *\n * This function will request NVM ownership for reading\n * via the proper Admin Command.\n **/\nenum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,\n\t\t\t\t enum i40e_aq_resource_access_type access)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tu64 gtime, timeout;\n\tu64 time_left = 0;\n\n\tDEBUGFUNC(\"i40e_acquire_nvm\");\n\n\tif (hw->nvm.blank_nvm_mode)\n\t\tgoto i40e_i40e_acquire_nvm_exit;\n\n\tret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,\n\t\t\t\t\t 0, &time_left, NULL);\n\t/* Reading the Global Device Timer */\n\tgtime = rd32(hw, I40E_GLVFGEN_TIMER);\n\n\t/* Store the timeout */\n\thw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;\n\n\tif (ret_code)\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\\n\",\n\t\t\t access, time_left, ret_code, hw->aq.asq_last_status);\n\n\tif (ret_code && time_left) {\n\t\t/* Poll until the current NVM owner timeouts */\n\t\ttimeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;\n\t\twhile ((gtime < timeout) && time_left) {\n\t\t\ti40e_msec_delay(10);\n\t\t\tgtime = rd32(hw, I40E_GLVFGEN_TIMER);\n\t\t\tret_code = i40e_aq_request_resource(hw,\n\t\t\t\t\t\t\tI40E_NVM_RESOURCE_ID,\n\t\t\t\t\t\t\taccess, 0, &time_left,\n\t\t\t\t\t\t\tNULL);\n\t\t\tif (ret_code == I40E_SUCCESS) {\n\t\t\t\thw->nvm.hw_semaphore_timeout =\n\t\t\t\t\t I40E_MS_TO_GTIME(time_left) + gtime;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (ret_code != I40E_SUCCESS) {\n\t\t\thw->nvm.hw_semaphore_timeout = 0;\n\t\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t\t \"NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\\n\",\n\t\t\t\t time_left, ret_code, hw->aq.asq_last_status);\n\t\t}\n\t}\n\ni40e_i40e_acquire_nvm_exit:\n\treturn ret_code;\n}\n\n/**\n * i40e_release_nvm - Generic request for releasing the NVM ownership\n * @hw: pointer to the HW structure\n *\n * This function will release NVM resource via the proper Admin Command.\n **/\nvoid i40e_release_nvm(struct i40e_hw *hw)\n{\n\tDEBUGFUNC(\"i40e_release_nvm\");\n\n\tif (!hw->nvm.blank_nvm_mode)\n\t\ti40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);\n}\n\n/**\n * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit\n * @hw: pointer to the HW structure\n *\n * Polls the SRCTL Shadow RAM register done bit.\n **/\nstatic enum i40e_status_code i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code = I40E_ERR_TIMEOUT;\n\tu32 srctl, wait_cnt;\n\n\tDEBUGFUNC(\"i40e_poll_sr_srctl_done_bit\");\n\n\t/* Poll the I40E_GLNVM_SRCTL until the done bit is set */\n\tfor (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {\n\t\tsrctl = rd32(hw, I40E_GLNVM_SRCTL);\n\t\tif (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {\n\t\t\tret_code = I40E_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\ti40e_usec_delay(5);\n\t}\n\tif (ret_code == I40E_ERR_TIMEOUT)\n\t\ti40e_debug(hw, I40E_DEBUG_NVM, \"Done bit in GLNVM_SRCTL not set\");\n\treturn ret_code;\n}\n\n/**\n * i40e_read_nvm_word - Reads Shadow RAM\n * @hw: pointer to the HW structure\n * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n * @data: word read from the Shadow RAM\n *\n * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.\n **/\nenum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,\n\t\t\t\t\t u16 *data)\n{\n\treturn i40e_read_nvm_word_srctl(hw, offset, data);\n}\n\n/**\n * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register\n * @hw: pointer to the HW structure\n * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n * @data: word read from the Shadow RAM\n *\n * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.\n **/\nenum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,\n\t\t\t\t\t u16 *data)\n{\n\tenum i40e_status_code ret_code = I40E_ERR_TIMEOUT;\n\tu32 sr_reg;\n\n\tDEBUGFUNC(\"i40e_read_nvm_word_srctl\");\n\n\tif (offset >= hw->nvm.sr_size) {\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"NVM read error: Offset %d beyond Shadow RAM limit %d\\n\",\n\t\t\t offset, hw->nvm.sr_size);\n\t\tret_code = I40E_ERR_PARAM;\n\t\tgoto read_nvm_exit;\n\t}\n\n\t/* Poll the done bit first */\n\tret_code = i40e_poll_sr_srctl_done_bit(hw);\n\tif (ret_code == I40E_SUCCESS) {\n\t\t/* Write the address and start reading */\n\t\tsr_reg = (u32)(offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |\n\t\t\t (1 << I40E_GLNVM_SRCTL_START_SHIFT);\n\t\twr32(hw, I40E_GLNVM_SRCTL, sr_reg);\n\n\t\t/* Poll I40E_GLNVM_SRCTL until the done bit is set */\n\t\tret_code = i40e_poll_sr_srctl_done_bit(hw);\n\t\tif (ret_code == I40E_SUCCESS) {\n\t\t\tsr_reg = rd32(hw, I40E_GLNVM_SRDATA);\n\t\t\t*data = (u16)((sr_reg &\n\t\t\t\t I40E_GLNVM_SRDATA_RDDATA_MASK)\n\t\t\t\t >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);\n\t\t}\n\t}\n\tif (ret_code != I40E_SUCCESS)\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"NVM read error: Couldn't access Shadow RAM address: 0x%x\\n\",\n\t\t\t offset);\n\nread_nvm_exit:\n\treturn ret_code;\n}\n\n/**\n * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ\n * @hw: pointer to the HW structure\n * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n * @data: word read from the Shadow RAM\n *\n * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.\n **/\nenum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,\n\t\t\t\t\t u16 *data)\n{\n\tenum i40e_status_code ret_code = I40E_ERR_TIMEOUT;\n\n\tDEBUGFUNC(\"i40e_read_nvm_word_aq\");\n\n\tret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);\n\t*data = LE16_TO_CPU(*(__le16 *)data);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_read_nvm_buffer - Reads Shadow RAM buffer\n * @hw: pointer to the HW structure\n * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).\n * @words: (in) number of words to read; (out) number of words actually read\n * @data: words read from the Shadow RAM\n *\n * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()\n * method. The buffer read is preceded by the NVM ownership take\n * and followed by the release.\n **/\nenum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,\n\t\t\t\t\t u16 *words, u16 *data)\n{\n\treturn i40e_read_nvm_buffer_srctl(hw, offset, words, data);\n}\n\n/**\n * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register\n * @hw: pointer to the HW structure\n * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).\n * @words: (in) number of words to read; (out) number of words actually read\n * @data: words read from the Shadow RAM\n *\n * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()\n * method. The buffer read is preceded by the NVM ownership take\n * and followed by the release.\n **/\nenum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,\n\t\t\t\t\t\t u16 *words, u16 *data)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tu16 index, word;\n\n\tDEBUGFUNC(\"i40e_read_nvm_buffer_srctl\");\n\n\t/* Loop thru the selected region */\n\tfor (word = 0; word < *words; word++) {\n\t\tindex = offset + word;\n\t\tret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);\n\t\tif (ret_code != I40E_SUCCESS)\n\t\t\tbreak;\n\t}\n\n\t/* Update the number of words read from the Shadow RAM */\n\t*words = word;\n\n\treturn ret_code;\n}\n\n/**\n * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ\n * @hw: pointer to the HW structure\n * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).\n * @words: (in) number of words to read; (out) number of words actually read\n * @data: words read from the Shadow RAM\n *\n * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()\n * method. The buffer read is preceded by the NVM ownership take\n * and followed by the release.\n **/\nenum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,\n\t\t\t\t\t u16 *words, u16 *data)\n{\n\tenum i40e_status_code ret_code;\n\tu16 read_size = *words;\n\tbool last_cmd = false;\n\tu16 words_read = 0;\n\tu16 i = 0;\n\n\tDEBUGFUNC(\"i40e_read_nvm_buffer_aq\");\n\n\tdo {\n\t\t/* Calculate number of bytes we should read in this step.\n\t\t * FVL AQ do not allow to read more than one page at a time or\n\t\t * to cross page boundaries.\n\t\t */\n\t\tif (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)\n\t\t\tread_size = min(*words,\n\t\t\t\t\t(u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -\n\t\t\t\t (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));\n\t\telse\n\t\t\tread_size = min((*words - words_read),\n\t\t\t\t\tI40E_SR_SECTOR_SIZE_IN_WORDS);\n\n\t\t/* Check if this is last command, if so set proper flag */\n\t\tif ((words_read + read_size) >= *words)\n\t\t\tlast_cmd = true;\n\n\t\tret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,\n\t\t\t\t\t data + words_read, last_cmd);\n\t\tif (ret_code != I40E_SUCCESS)\n\t\t\tgoto read_nvm_buffer_aq_exit;\n\n\t\t/* Increment counter for words already read and move offset to\n\t\t * new read location\n\t\t */\n\t\twords_read += read_size;\n\t\toffset += read_size;\n\t} while (words_read < *words);\n\n\tfor (i = 0; i < *words; i++)\n\t\tdata[i] = LE16_TO_CPU(((__le16 *)data)[i]);\n\nread_nvm_buffer_aq_exit:\n\t*words = words_read;\n\treturn ret_code;\n}\n\n/**\n * i40e_read_nvm_aq - Read Shadow RAM.\n * @hw: pointer to the HW structure.\n * @module_pointer: module pointer location in words from the NVM beginning\n * @offset: offset in words from module start\n * @words: number of words to write\n * @data: buffer with words to write to the Shadow RAM\n * @last_command: tells the AdminQ that this is the last command\n *\n * Writes a 16 bit words buffer to the Shadow RAM using the admin command.\n **/\nenum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,\n\t\t\t\t u32 offset, u16 words, void *data,\n\t\t\t\t bool last_command)\n{\n\tenum i40e_status_code ret_code = I40E_ERR_NVM;\n\n\tDEBUGFUNC(\"i40e_read_nvm_aq\");\n\n\t/* Here we are checking the SR limit only for the flat memory model.\n\t * We cannot do it for the module-based model, as we did not acquire\n\t * the NVM resource yet (we cannot get the module pointer value).\n\t * Firmware will check the module-based model.\n\t */\n\tif ((offset + words) > hw->nvm.sr_size)\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"NVM write error: offset %d beyond Shadow RAM limit %d\\n\",\n\t\t\t (offset + words), hw->nvm.sr_size);\n\telse if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)\n\t\t/* We can write only up to 4KB (one sector), in one AQ write */\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"NVM write fail error: tried to write %d words, limit is %d.\\n\",\n\t\t\t words, I40E_SR_SECTOR_SIZE_IN_WORDS);\n\telse if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)\n\t\t != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))\n\t\t/* A single write cannot spread over two sectors */\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\\n\",\n\t\t\t offset, words);\n\telse\n\t\tret_code = i40e_aq_read_nvm(hw, module_pointer,\n\t\t\t\t\t 2 * offset, /*bytes*/\n\t\t\t\t\t 2 * words, /*bytes*/\n\t\t\t\t\t data, last_command, NULL);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_write_nvm_aq - Writes Shadow RAM.\n * @hw: pointer to the HW structure.\n * @module_pointer: module pointer location in words from the NVM beginning\n * @offset: offset in words from module start\n * @words: number of words to write\n * @data: buffer with words to write to the Shadow RAM\n * @last_command: tells the AdminQ that this is the last command\n *\n * Writes a 16 bit words buffer to the Shadow RAM using the admin command.\n **/\nenum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,\n\t\t\t\t\tu32 offset, u16 words, void *data,\n\t\t\t\t\tbool last_command)\n{\n\tenum i40e_status_code ret_code = I40E_ERR_NVM;\n\n\tDEBUGFUNC(\"i40e_write_nvm_aq\");\n\n\t/* Here we are checking the SR limit only for the flat memory model.\n\t * We cannot do it for the module-based model, as we did not acquire\n\t * the NVM resource yet (we cannot get the module pointer value).\n\t * Firmware will check the module-based model.\n\t */\n\tif ((offset + words) > hw->nvm.sr_size)\n\t\tDEBUGOUT(\"NVM write error: offset beyond Shadow RAM limit.\\n\");\n\telse if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)\n\t\t/* We can write only up to 4KB (one sector), in one AQ write */\n\t\tDEBUGOUT(\"NVM write fail error: cannot write more than 4KB in a single write.\\n\");\n\telse if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)\n\t\t != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))\n\t\t/* A single write cannot spread over two sectors */\n\t\tDEBUGOUT(\"NVM write error: cannot spread over two sectors in a single write.\\n\");\n\telse\n\t\tret_code = i40e_aq_update_nvm(hw, module_pointer,\n\t\t\t\t\t 2 * offset, /*bytes*/\n\t\t\t\t\t 2 * words, /*bytes*/\n\t\t\t\t\t data, last_command, NULL);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_write_nvm_word - Writes Shadow RAM word\n * @hw: pointer to the HW structure\n * @offset: offset of the Shadow RAM word to write\n * @data: word to write to the Shadow RAM\n *\n * Writes a 16 bit word to the SR using the i40e_write_nvm_aq() method.\n * NVM ownership have to be acquired and released (on ARQ completion event\n * reception) by caller. To commit SR to NVM update checksum function\n * should be called.\n **/\nenum i40e_status_code i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,\n\t\t\t\t\t void *data)\n{\n\tDEBUGFUNC(\"i40e_write_nvm_word\");\n\n\t*((__le16 *)data) = CPU_TO_LE16(*((u16 *)data));\n\n\t/* Value 0x00 below means that we treat SR as a flat mem */\n\treturn i40e_write_nvm_aq(hw, 0x00, offset, 1, data, false);\n}\n\n/**\n * i40e_write_nvm_buffer - Writes Shadow RAM buffer\n * @hw: pointer to the HW structure\n * @module_pointer: module pointer location in words from the NVM beginning\n * @offset: offset of the Shadow RAM buffer to write\n * @words: number of words to write\n * @data: words to write to the Shadow RAM\n *\n * Writes a 16 bit words buffer to the Shadow RAM using the admin command.\n * NVM ownership must be acquired before calling this function and released\n * on ARQ completion event reception by caller. To commit SR to NVM update\n * checksum function should be called.\n **/\nenum i40e_status_code i40e_write_nvm_buffer(struct i40e_hw *hw,\n\t\t\t\t\t u8 module_pointer, u32 offset,\n\t\t\t\t\t u16 words, void *data)\n{\n\t__le16 *le_word_ptr = (__le16 *)data;\n\tu16 *word_ptr = (u16 *)data;\n\tu32 i = 0;\n\n\tDEBUGFUNC(\"i40e_write_nvm_buffer\");\n\n\tfor (i = 0; i < words; i++)\n\t\tle_word_ptr[i] = CPU_TO_LE16(word_ptr[i]);\n\n\t/* Here we will only write one buffer as the size of the modules\n\t * mirrored in the Shadow RAM is always less than 4K.\n\t */\n\treturn i40e_write_nvm_aq(hw, module_pointer, offset, words,\n\t\t\t\t data, false);\n}\n\n/**\n * i40e_calc_nvm_checksum - Calculates and returns the checksum\n * @hw: pointer to hardware structure\n * @checksum: pointer to the checksum\n *\n * This function calculates SW Checksum that covers the whole 64kB shadow RAM\n * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD\n * is customer specific and unknown. Therefore, this function skips all maximum\n * possible size of VPD (1kB).\n **/\nenum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tstruct i40e_virt_mem vmem;\n\tu16 pcie_alt_module = 0;\n\tu16 checksum_local = 0;\n\tu16 vpd_module = 0;\n\tu16 *data;\n\tu16 i = 0;\n\n\tDEBUGFUNC(\"i40e_calc_nvm_checksum\");\n\n\tret_code = i40e_allocate_virt_mem(hw, &vmem,\n\t\t\t\t I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));\n\tif (ret_code)\n\t\tgoto i40e_calc_nvm_checksum_exit;\n\tdata = (u16 *)vmem.va;\n\n\t/* read pointer to VPD area */\n\tret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);\n\tif (ret_code != I40E_SUCCESS) {\n\t\tret_code = I40E_ERR_NVM_CHECKSUM;\n\t\tgoto i40e_calc_nvm_checksum_exit;\n\t}\n\n\t/* read pointer to PCIe Alt Auto-load module */\n\tret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,\n\t\t\t\t &pcie_alt_module);\n\tif (ret_code != I40E_SUCCESS) {\n\t\tret_code = I40E_ERR_NVM_CHECKSUM;\n\t\tgoto i40e_calc_nvm_checksum_exit;\n\t}\n\n\t/* Calculate SW checksum that covers the whole 64kB shadow RAM\n\t * except the VPD and PCIe ALT Auto-load modules\n\t */\n\tfor (i = 0; i < hw->nvm.sr_size; i++) {\n\t\t/* Read SR page */\n\t\tif ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {\n\t\t\tu16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;\n\t\t\tret_code = i40e_read_nvm_buffer(hw, i, &words, data);\n\t\t\tif (ret_code != I40E_SUCCESS) {\n\t\t\t\tret_code = I40E_ERR_NVM_CHECKSUM;\n\t\t\t\tgoto i40e_calc_nvm_checksum_exit;\n\t\t\t}\n\t\t}\n\n\t\t/* Skip Checksum word */\n\t\tif (i == I40E_SR_SW_CHECKSUM_WORD)\n\t\t\tcontinue;\n\t\t/* Skip VPD module (convert byte size to word count) */\n\t\tif ((i >= (u32)vpd_module) &&\n\t\t (i < ((u32)vpd_module +\n\t\t (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {\n\t\t\tcontinue;\n\t\t}\n\t\t/* Skip PCIe ALT module (convert byte size to word count) */\n\t\tif ((i >= (u32)pcie_alt_module) &&\n\t\t (i < ((u32)pcie_alt_module +\n\t\t (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tchecksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];\n\t}\n\n\t*checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;\n\ni40e_calc_nvm_checksum_exit:\n\ti40e_free_virt_mem(hw, &vmem);\n\treturn ret_code;\n}\n\n/**\n * i40e_update_nvm_checksum - Updates the NVM checksum\n * @hw: pointer to hardware structure\n *\n * NVM ownership must be acquired before calling this function and released\n * on ARQ completion event reception by caller.\n * This function will commit SR to NVM.\n **/\nenum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tu16 checksum;\n\n\tDEBUGFUNC(\"i40e_update_nvm_checksum\");\n\n\tret_code = i40e_calc_nvm_checksum(hw, &checksum);\n\tif (ret_code == I40E_SUCCESS)\n\t\tret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,\n\t\t\t\t\t 1, &checksum, true);\n\n\treturn ret_code;\n}\n\n/**\n * i40e_validate_nvm_checksum - Validate EEPROM checksum\n * @hw: pointer to hardware structure\n * @checksum: calculated checksum\n *\n * Performs checksum calculation and validates the NVM SW checksum. If the\n * caller does not need checksum, the value can be NULL.\n **/\nenum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 *checksum)\n{\n\tenum i40e_status_code ret_code = I40E_SUCCESS;\n\tu16 checksum_sr = 0;\n\tu16 checksum_local = 0;\n\n\tDEBUGFUNC(\"i40e_validate_nvm_checksum\");\n\n\tret_code = i40e_calc_nvm_checksum(hw, &checksum_local);\n\tif (ret_code != I40E_SUCCESS)\n\t\tgoto i40e_validate_nvm_checksum_exit;\n\n\t/* Do not use i40e_read_nvm_word() because we do not want to take\n\t * the synchronization semaphores twice here.\n\t */\n\ti40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);\n\n\t/* Verify read checksum from EEPROM is the same as\n\t * calculated checksum\n\t */\n\tif (checksum_local != checksum_sr)\n\t\tret_code = I40E_ERR_NVM_CHECKSUM;\n\n\t/* If the user cares, return the calculated checksum */\n\tif (checksum)\n\t\t*checksum = checksum_local;\n\ni40e_validate_nvm_checksum_exit:\n\treturn ret_code;\n}\n\nSTATIC enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t u8 *bytes, int *perrno);\nSTATIC enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t u8 *bytes, int *perrno);\nSTATIC enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t u8 *bytes, int *perrno);\nSTATIC enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t int *perrno);\nSTATIC enum i40e_status_code i40e_nvmupd_nvm_erase(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t int *perrno);\nSTATIC enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t u8 *bytes, int *perrno);\nSTATIC enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t u8 *bytes, int *perrno);\nSTATIC inline u8 i40e_nvmupd_get_module(u32 val)\n{\n\treturn (u8)(val & I40E_NVM_MOD_PNT_MASK);\n}\nSTATIC inline u8 i40e_nvmupd_get_transaction(u32 val)\n{\n\treturn (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);\n}\n\nSTATIC const char *i40e_nvm_update_state_str[] = {\n\t\"I40E_NVMUPD_INVALID\",\n\t\"I40E_NVMUPD_READ_CON\",\n\t\"I40E_NVMUPD_READ_SNT\",\n\t\"I40E_NVMUPD_READ_LCB\",\n\t\"I40E_NVMUPD_READ_SA\",\n\t\"I40E_NVMUPD_WRITE_ERA\",\n\t\"I40E_NVMUPD_WRITE_CON\",\n\t\"I40E_NVMUPD_WRITE_SNT\",\n\t\"I40E_NVMUPD_WRITE_LCB\",\n\t\"I40E_NVMUPD_WRITE_SA\",\n\t\"I40E_NVMUPD_CSUM_CON\",\n\t\"I40E_NVMUPD_CSUM_SA\",\n\t\"I40E_NVMUPD_CSUM_LCB\",\n};\n\n/**\n * i40e_nvmupd_command - Process an NVM update command\n * @hw: pointer to hardware structure\n * @cmd: pointer to nvm update command\n * @bytes: pointer to the data buffer\n * @perrno: pointer to return error code\n *\n * Dispatches command depending on what update state is current\n **/\nenum i40e_status_code i40e_nvmupd_command(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t u8 *bytes, int *perrno)\n{\n\tenum i40e_status_code status;\n\n\tDEBUGFUNC(\"i40e_nvmupd_command\");\n\n\t/* assume success */\n\t*perrno = 0;\n\n\tswitch (hw->nvmupd_state) {\n\tcase I40E_NVMUPD_STATE_INIT:\n\t\tstatus = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);\n\t\tbreak;\n\n\tcase I40E_NVMUPD_STATE_READING:\n\t\tstatus = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);\n\t\tbreak;\n\n\tcase I40E_NVMUPD_STATE_WRITING:\n\t\tstatus = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);\n\t\tbreak;\n\n\tdefault:\n\t\t/* invalid state, should never happen */\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"NVMUPD: no such state %d\\n\", hw->nvmupd_state);\n\t\tstatus = I40E_NOT_SUPPORTED;\n\t\t*perrno = -ESRCH;\n\t\tbreak;\n\t}\n\treturn status;\n}\n\n/**\n * i40e_nvmupd_state_init - Handle NVM update state Init\n * @hw: pointer to hardware structure\n * @cmd: pointer to nvm update command buffer\n * @bytes: pointer to the data buffer\n * @perrno: pointer to return error code\n *\n * Process legitimate commands of the Init state and conditionally set next\n * state. Reject all other commands.\n **/\nSTATIC enum i40e_status_code i40e_nvmupd_state_init(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t u8 *bytes, int *perrno)\n{\n\tenum i40e_status_code status = I40E_SUCCESS;\n\tenum i40e_nvmupd_cmd upd_cmd;\n\n\tDEBUGFUNC(\"i40e_nvmupd_state_init\");\n\n\tupd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);\n\n\tswitch (upd_cmd) {\n\tcase I40E_NVMUPD_READ_SA:\n\t\tstatus = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);\n\t\tif (status) {\n\t\t\t*perrno = i40e_aq_rc_to_posix(status,\n\t\t\t\t\t\t hw->aq.asq_last_status);\n\t\t} else {\n\t\t\tstatus = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);\n\t\t\ti40e_release_nvm(hw);\n\t\t}\n\t\tbreak;\n\n\tcase I40E_NVMUPD_READ_SNT:\n\t\tstatus = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);\n\t\tif (status) {\n\t\t\t*perrno = i40e_aq_rc_to_posix(status,\n\t\t\t\t\t\t hw->aq.asq_last_status);\n\t\t} else {\n\t\t\tstatus = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);\n\t\t\tif (status)\n\t\t\t\ti40e_release_nvm(hw);\n\t\t\telse\n\t\t\t\thw->nvmupd_state = I40E_NVMUPD_STATE_READING;\n\t\t}\n\t\tbreak;\n\n\tcase I40E_NVMUPD_WRITE_ERA:\n\t\tstatus = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);\n\t\tif (status) {\n\t\t\t*perrno = i40e_aq_rc_to_posix(status,\n\t\t\t\t\t\t hw->aq.asq_last_status);\n\t\t} else {\n\t\t\tstatus = i40e_nvmupd_nvm_erase(hw, cmd, perrno);\n\t\t\tif (status)\n\t\t\t\ti40e_release_nvm(hw);\n\t\t\telse\n\t\t\t\thw->aq.nvm_release_on_done = true;\n\t\t}\n\t\tbreak;\n\n\tcase I40E_NVMUPD_WRITE_SA:\n\t\tstatus = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);\n\t\tif (status) {\n\t\t\t*perrno = i40e_aq_rc_to_posix(status,\n\t\t\t\t\t\t hw->aq.asq_last_status);\n\t\t} else {\n\t\t\tstatus = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);\n\t\t\tif (status)\n\t\t\t\ti40e_release_nvm(hw);\n\t\t\telse\n\t\t\t\thw->aq.nvm_release_on_done = true;\n\t\t}\n\t\tbreak;\n\n\tcase I40E_NVMUPD_WRITE_SNT:\n\t\tstatus = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);\n\t\tif (status) {\n\t\t\t*perrno = i40e_aq_rc_to_posix(status,\n\t\t\t\t\t\t hw->aq.asq_last_status);\n\t\t} else {\n\t\t\tstatus = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);\n\t\t\tif (status)\n\t\t\t\ti40e_release_nvm(hw);\n\t\t\telse\n\t\t\t\thw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;\n\t\t}\n\t\tbreak;\n\n\tcase I40E_NVMUPD_CSUM_SA:\n\t\tstatus = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);\n\t\tif (status) {\n\t\t\t*perrno = i40e_aq_rc_to_posix(status,\n\t\t\t\t\t\t hw->aq.asq_last_status);\n\t\t} else {\n\t\t\tstatus = i40e_update_nvm_checksum(hw);\n\t\t\tif (status) {\n\t\t\t\t*perrno = hw->aq.asq_last_status ?\n\t\t\t\t i40e_aq_rc_to_posix(status,\n\t\t\t\t\t\t hw->aq.asq_last_status) :\n\t\t\t\t -EIO;\n\t\t\t\ti40e_release_nvm(hw);\n\t\t\t} else {\n\t\t\t\thw->aq.nvm_release_on_done = true;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"NVMUPD: bad cmd %s in init state\\n\",\n\t\t\t i40e_nvm_update_state_str[upd_cmd]);\n\t\tstatus = I40E_ERR_NVM;\n\t\t*perrno = -ESRCH;\n\t\tbreak;\n\t}\n\treturn status;\n}\n\n/**\n * i40e_nvmupd_state_reading - Handle NVM update state Reading\n * @hw: pointer to hardware structure\n * @cmd: pointer to nvm update command buffer\n * @bytes: pointer to the data buffer\n * @perrno: pointer to return error code\n *\n * NVM ownership is already held. Process legitimate commands and set any\n * change in state; reject all other commands.\n **/\nSTATIC enum i40e_status_code i40e_nvmupd_state_reading(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t u8 *bytes, int *perrno)\n{\n\tenum i40e_status_code status;\n\tenum i40e_nvmupd_cmd upd_cmd;\n\n\tDEBUGFUNC(\"i40e_nvmupd_state_reading\");\n\n\tupd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);\n\n\tswitch (upd_cmd) {\n\tcase I40E_NVMUPD_READ_SA:\n\tcase I40E_NVMUPD_READ_CON:\n\t\tstatus = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);\n\t\tbreak;\n\n\tcase I40E_NVMUPD_READ_LCB:\n\t\tstatus = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);\n\t\ti40e_release_nvm(hw);\n\t\thw->nvmupd_state = I40E_NVMUPD_STATE_INIT;\n\t\tbreak;\n\n\tdefault:\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"NVMUPD: bad cmd %s in reading state.\\n\",\n\t\t\t i40e_nvm_update_state_str[upd_cmd]);\n\t\tstatus = I40E_NOT_SUPPORTED;\n\t\t*perrno = -ESRCH;\n\t\tbreak;\n\t}\n\treturn status;\n}\n\n/**\n * i40e_nvmupd_state_writing - Handle NVM update state Writing\n * @hw: pointer to hardware structure\n * @cmd: pointer to nvm update command buffer\n * @bytes: pointer to the data buffer\n * @perrno: pointer to return error code\n *\n * NVM ownership is already held. Process legitimate commands and set any\n * change in state; reject all other commands\n **/\nSTATIC enum i40e_status_code i40e_nvmupd_state_writing(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t u8 *bytes, int *perrno)\n{\n\tenum i40e_status_code status;\n\tenum i40e_nvmupd_cmd upd_cmd;\n\tbool retry_attempt = false;\n\n\tDEBUGFUNC(\"i40e_nvmupd_state_writing\");\n\n\tupd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);\n\nretry:\n\tswitch (upd_cmd) {\n\tcase I40E_NVMUPD_WRITE_CON:\n\t\tstatus = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);\n\t\tbreak;\n\n\tcase I40E_NVMUPD_WRITE_LCB:\n\t\tstatus = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);\n\t\tif (!status)\n\t\t\thw->aq.nvm_release_on_done = true;\n\t\thw->nvmupd_state = I40E_NVMUPD_STATE_INIT;\n\t\tbreak;\n\n\tcase I40E_NVMUPD_CSUM_CON:\n\t\tstatus = i40e_update_nvm_checksum(hw);\n\t\tif (status) {\n\t\t\t*perrno = hw->aq.asq_last_status ?\n\t\t\t\t i40e_aq_rc_to_posix(status,\n\t\t\t\t\t\t hw->aq.asq_last_status) :\n\t\t\t\t -EIO;\n\t\t\thw->nvmupd_state = I40E_NVMUPD_STATE_INIT;\n\t\t}\n\t\tbreak;\n\n\tcase I40E_NVMUPD_CSUM_LCB:\n\t\tstatus = i40e_update_nvm_checksum(hw);\n\t\tif (status)\n\t\t\t*perrno = hw->aq.asq_last_status ?\n\t\t\t\t i40e_aq_rc_to_posix(status,\n\t\t\t\t\t\t hw->aq.asq_last_status) :\n\t\t\t\t -EIO;\n\t\telse\n\t\t\thw->aq.nvm_release_on_done = true;\n\t\thw->nvmupd_state = I40E_NVMUPD_STATE_INIT;\n\t\tbreak;\n\n\tdefault:\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"NVMUPD: bad cmd %s in writing state.\\n\",\n\t\t\t i40e_nvm_update_state_str[upd_cmd]);\n\t\tstatus = I40E_NOT_SUPPORTED;\n\t\t*perrno = -ESRCH;\n\t\tbreak;\n\t}\n\n\t/* In some circumstances, a multi-write transaction takes longer\n\t * than the default 3 minute timeout on the write semaphore. If\n\t * the write failed with an EBUSY status, this is likely the problem,\n\t * so here we try to reacquire the semaphore then retry the write.\n\t * We only do one retry, then give up.\n\t */\n\tif (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&\n\t !retry_attempt) {\n\t\tenum i40e_status_code old_status = status;\n\t\tu32 old_asq_status = hw->aq.asq_last_status;\n\t\tu32 gtime;\n\n\t\tgtime = rd32(hw, I40E_GLVFGEN_TIMER);\n\t\tif (gtime >= hw->nvm.hw_semaphore_timeout) {\n\t\t\ti40e_debug(hw, I40E_DEBUG_ALL,\n\t\t\t\t \"NVMUPD: write semaphore expired (%d >= %lld), retrying\\n\",\n\t\t\t\t gtime, hw->nvm.hw_semaphore_timeout);\n\t\t\ti40e_release_nvm(hw);\n\t\t\tstatus = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);\n\t\t\tif (status) {\n\t\t\t\ti40e_debug(hw, I40E_DEBUG_ALL,\n\t\t\t\t\t \"NVMUPD: write semaphore reacquire failed aq_err = %d\\n\",\n\t\t\t\t\t hw->aq.asq_last_status);\n\t\t\t\tstatus = old_status;\n\t\t\t\thw->aq.asq_last_status = old_asq_status;\n\t\t\t} else {\n\t\t\t\tretry_attempt = true;\n\t\t\t\tgoto retry;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_nvmupd_validate_command - Validate given command\n * @hw: pointer to hardware structure\n * @cmd: pointer to nvm update command buffer\n * @perrno: pointer to return error code\n *\n * Return one of the valid command types or I40E_NVMUPD_INVALID\n **/\nSTATIC enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t int *perrno)\n{\n\tenum i40e_nvmupd_cmd upd_cmd;\n\tu8 transaction, module;\n\n\tDEBUGFUNC(\"i40e_nvmupd_validate_command\\n\");\n\n\t/* anything that doesn't match a recognized case is an error */\n\tupd_cmd = I40E_NVMUPD_INVALID;\n\n\ttransaction = i40e_nvmupd_get_transaction(cmd->config);\n\tmodule = i40e_nvmupd_get_module(cmd->config);\n\n\t/* limits on data size */\n\tif ((cmd->data_size < 1) ||\n\t (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"i40e_nvmupd_validate_command data_size %d\\n\",\n\t\t\t cmd->data_size);\n\t\t*perrno = -EFAULT;\n\t\treturn I40E_NVMUPD_INVALID;\n\t}\n\n\tswitch (cmd->command) {\n\tcase I40E_NVM_READ:\n\t\tswitch (transaction) {\n\t\tcase I40E_NVM_CON:\n\t\t\tupd_cmd = I40E_NVMUPD_READ_CON;\n\t\t\tbreak;\n\t\tcase I40E_NVM_SNT:\n\t\t\tupd_cmd = I40E_NVMUPD_READ_SNT;\n\t\t\tbreak;\n\t\tcase I40E_NVM_LCB:\n\t\t\tupd_cmd = I40E_NVMUPD_READ_LCB;\n\t\t\tbreak;\n\t\tcase I40E_NVM_SA:\n\t\t\tupd_cmd = I40E_NVMUPD_READ_SA;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\n\tcase I40E_NVM_WRITE:\n\t\tswitch (transaction) {\n\t\tcase I40E_NVM_CON:\n\t\t\tupd_cmd = I40E_NVMUPD_WRITE_CON;\n\t\t\tbreak;\n\t\tcase I40E_NVM_SNT:\n\t\t\tupd_cmd = I40E_NVMUPD_WRITE_SNT;\n\t\t\tbreak;\n\t\tcase I40E_NVM_LCB:\n\t\t\tupd_cmd = I40E_NVMUPD_WRITE_LCB;\n\t\t\tbreak;\n\t\tcase I40E_NVM_SA:\n\t\t\tupd_cmd = I40E_NVMUPD_WRITE_SA;\n\t\t\tbreak;\n\t\tcase I40E_NVM_ERA:\n\t\t\tupd_cmd = I40E_NVMUPD_WRITE_ERA;\n\t\t\tbreak;\n\t\tcase I40E_NVM_CSUM:\n\t\t\tupd_cmd = I40E_NVMUPD_CSUM_CON;\n\t\t\tbreak;\n\t\tcase (I40E_NVM_CSUM|I40E_NVM_SA):\n\t\t\tupd_cmd = I40E_NVMUPD_CSUM_SA;\n\t\t\tbreak;\n\t\tcase (I40E_NVM_CSUM|I40E_NVM_LCB):\n\t\t\tupd_cmd = I40E_NVMUPD_CSUM_LCB;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\t}\n\ti40e_debug(hw, I40E_DEBUG_NVM, \"%s state %d nvm_release_on_hold %d\\n\",\n\t\t i40e_nvm_update_state_str[upd_cmd],\n\t\t hw->nvmupd_state,\n\t\t hw->aq.nvm_release_on_done);\n\n\tif (upd_cmd == I40E_NVMUPD_INVALID) {\n\t\t*perrno = -EFAULT;\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"i40e_nvmupd_validate_command returns %d perrno %d\\n\",\n\t\t\t upd_cmd, *perrno);\n\t}\n\treturn upd_cmd;\n}\n\n/**\n * i40e_nvmupd_nvm_read - Read NVM\n * @hw: pointer to hardware structure\n * @cmd: pointer to nvm update command buffer\n * @bytes: pointer to the data buffer\n * @perrno: pointer to return error code\n *\n * cmd structure contains identifiers and data buffer\n **/\nSTATIC enum i40e_status_code i40e_nvmupd_nvm_read(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t u8 *bytes, int *perrno)\n{\n\tenum i40e_status_code status;\n\tu8 module, transaction;\n\tbool last;\n\n\ttransaction = i40e_nvmupd_get_transaction(cmd->config);\n\tmodule = i40e_nvmupd_get_module(cmd->config);\n\tlast = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);\n\n\tstatus = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,\n\t\t\t\t bytes, last, NULL);\n\tif (status) {\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\\n\",\n\t\t\t module, cmd->offset, cmd->data_size);\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"i40e_nvmupd_nvm_read status %d aq %d\\n\",\n\t\t\t status, hw->aq.asq_last_status);\n\t\t*perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_nvmupd_nvm_erase - Erase an NVM module\n * @hw: pointer to hardware structure\n * @cmd: pointer to nvm update command buffer\n * @perrno: pointer to return error code\n *\n * module, offset, data_size and data are in cmd structure\n **/\nSTATIC enum i40e_status_code i40e_nvmupd_nvm_erase(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t int *perrno)\n{\n\tenum i40e_status_code status = I40E_SUCCESS;\n\tu8 module, transaction;\n\tbool last;\n\n\ttransaction = i40e_nvmupd_get_transaction(cmd->config);\n\tmodule = i40e_nvmupd_get_module(cmd->config);\n\tlast = (transaction & I40E_NVM_LCB);\n\tstatus = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,\n\t\t\t\t last, NULL);\n\tif (status) {\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\\n\",\n\t\t\t module, cmd->offset, cmd->data_size);\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"i40e_nvmupd_nvm_erase status %d aq %d\\n\",\n\t\t\t status, hw->aq.asq_last_status);\n\t\t*perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);\n\t}\n\n\treturn status;\n}\n\n/**\n * i40e_nvmupd_nvm_write - Write NVM\n * @hw: pointer to hardware structure\n * @cmd: pointer to nvm update command buffer\n * @bytes: pointer to the data buffer\n * @perrno: pointer to return error code\n *\n * module, offset, data_size and data are in cmd structure\n **/\nSTATIC enum i40e_status_code i40e_nvmupd_nvm_write(struct i40e_hw *hw,\n\t\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t\t u8 *bytes, int *perrno)\n{\n\tenum i40e_status_code status = I40E_SUCCESS;\n\tu8 module, transaction;\n\tbool last;\n\n\ttransaction = i40e_nvmupd_get_transaction(cmd->config);\n\tmodule = i40e_nvmupd_get_module(cmd->config);\n\tlast = (transaction & I40E_NVM_LCB);\n\n\tstatus = i40e_aq_update_nvm(hw, module, cmd->offset,\n\t\t\t\t (u16)cmd->data_size, bytes, last, NULL);\n\tif (status) {\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\\n\",\n\t\t\t module, cmd->offset, cmd->data_size);\n\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n\t\t\t \"i40e_nvmupd_nvm_write status %d aq %d\\n\",\n\t\t\t status, hw->aq.asq_last_status);\n\t\t*perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);\n\t}\n\n\treturn status;\n}\n" }, { "path": "drivers/net/i40e/base/i40e_osdep.h", "content": "/******************************************************************************\n\n Copyright (c) 2001-2015, Intel Corporation\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n******************************************************************************/\n\n#ifndef _I40E_OSDEP_H_\n#define _I40E_OSDEP_H_\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"../i40e_logs.h\"\n\n#define INLINE inline\n#define STATIC static\n\ntypedef uint8_t u8;\ntypedef int8_t s8;\ntypedef uint16_t u16;\ntypedef uint32_t u32;\ntypedef int32_t s32;\ntypedef uint64_t u64;\ntypedef int bool;\n\ntypedef enum i40e_status_code i40e_status;\n#define __iomem\n#define hw_dbg(hw, S, A...) do {} while (0)\n#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))\n#define lower_32_bits(n) ((u32)(n))\n#define low_16_bits(x) ((x) & 0xFFFF)\n#define high_16_bits(x) (((x) & 0xFFFF0000) >> 16)\n\n#ifndef ETH_ADDR_LEN\n#define ETH_ADDR_LEN 6\n#endif\n\n#ifndef __le16\n#define __le16 uint16_t\n#endif\n#ifndef __le32\n#define __le32 uint32_t\n#endif\n#ifndef __le64\n#define __le64 uint64_t\n#endif\n#ifndef __be16\n#define __be16 uint16_t\n#endif\n#ifndef __be32\n#define __be32 uint32_t\n#endif\n#ifndef __be64\n#define __be64 uint64_t\n#endif\n\n#define FALSE 0\n#define TRUE 1\n#define false 0\n#define true 1\n\n#define min(a,b) RTE_MIN(a,b)\n#define max(a,b) RTE_MAX(a,b)\n\n#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))\n#define ASSERT(x) if(!(x)) rte_panic(\"IXGBE: x\")\n\n#define DEBUGOUT(S) PMD_DRV_LOG_RAW(DEBUG, S)\n#define DEBUGOUT1(S, A...) PMD_DRV_LOG_RAW(DEBUG, S, ##A)\n\n#define DEBUGFUNC(F) DEBUGOUT(F \"\\n\")\n#define DEBUGOUT2 DEBUGOUT1\n#define DEBUGOUT3 DEBUGOUT2\n#define DEBUGOUT6 DEBUGOUT3\n#define DEBUGOUT7 DEBUGOUT6\n\n#define i40e_debug(h, m, s, ...) \\\ndo { \\\n\tif (((m) & (h)->debug_mask)) \\\n\t\tPMD_DRV_LOG_RAW(DEBUG, \"i40e %02x.%x \" s, \\\n\t\t\t(h)->bus.device, (h)->bus.func, \\\n\t\t\t\t\t##__VA_ARGS__); \\\n} while (0)\n\n#define I40E_PCI_REG(reg) (*((volatile uint32_t *)(reg)))\n#define I40E_PCI_REG_ADDR(a, reg) \\\n\t((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))\nstatic inline uint32_t i40e_read_addr(volatile void *addr)\n{\n\treturn rte_le_to_cpu_32(I40E_PCI_REG(addr));\n}\n#define I40E_PCI_REG_WRITE(reg, value) \\\n\tdo { I40E_PCI_REG((reg)) = rte_cpu_to_le_32(value); } while (0)\n\n#define I40E_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_GLGEN_STAT)\n#define I40EVF_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_VFGEN_RSTAT)\n\n#define I40E_READ_REG(hw, reg) i40e_read_addr(I40E_PCI_REG_ADDR((hw), (reg)))\n#define I40E_WRITE_REG(hw, reg, value) \\\n\tI40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((hw), (reg)), (value))\n\n#define rd32(a, reg) i40e_read_addr(I40E_PCI_REG_ADDR((a), (reg)))\n#define wr32(a, reg, value) \\\n\tI40E_PCI_REG_WRITE(I40E_PCI_REG_ADDR((a), (reg)), (value))\n#define flush(a) i40e_read_addr(I40E_PCI_REG_ADDR((a), (I40E_GLGEN_STAT)))\n\n#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof(arr[0]))\n\n/* memory allocation tracking */\nstruct i40e_dma_mem {\n\tvoid *va;\n\tu64 pa;\n\tu32 size;\n\tu64 id;\n} __attribute__((packed));\n\n#define i40e_allocate_dma_mem(h, m, unused, s, a) \\\n\t\t\ti40e_allocate_dma_mem_d(h, m, s, a)\n#define i40e_free_dma_mem(h, m) i40e_free_dma_mem_d(h, m)\n\nstruct i40e_virt_mem {\n\tvoid *va;\n\tu32 size;\n} __attribute__((packed));\n\n#define i40e_allocate_virt_mem(h, m, s) i40e_allocate_virt_mem_d(h, m, s)\n#define i40e_free_virt_mem(h, m) i40e_free_virt_mem_d(h, m)\n\n#define CPU_TO_LE16(o) rte_cpu_to_le_16(o)\n#define CPU_TO_LE32(s) rte_cpu_to_le_32(s)\n#define CPU_TO_LE64(h) rte_cpu_to_le_64(h)\n#define LE16_TO_CPU(a) rte_le_to_cpu_16(a)\n#define LE32_TO_CPU(c) rte_le_to_cpu_32(c)\n#define LE64_TO_CPU(k) rte_le_to_cpu_64(k)\n\n/* SW spinlock */\nstruct i40e_spinlock {\n\trte_spinlock_t spinlock;\n};\n\n#define i40e_init_spinlock(_sp) i40e_init_spinlock_d(_sp)\n#define i40e_acquire_spinlock(_sp) i40e_acquire_spinlock_d(_sp)\n#define i40e_release_spinlock(_sp) i40e_release_spinlock_d(_sp)\n#define i40e_destroy_spinlock(_sp) i40e_destroy_spinlock_d(_sp)\n\n#define I40E_NTOHS(a) rte_be_to_cpu_16(a)\n#define I40E_NTOHL(a) rte_be_to_cpu_32(a)\n#define I40E_HTONS(a) rte_cpu_to_be_16(a)\n#define I40E_HTONL(a) rte_cpu_to_be_32(a)\n\n#define i40e_memset(a, b, c, d) memset((a), (b), (c))\n#define i40e_memcpy(a, b, c, d) rte_memcpy((a), (b), (c))\n\n#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))\n#define DELAY(x) rte_delay_us(x)\n#define i40e_usec_delay(x) rte_delay_us(x)\n#define i40e_msec_delay(x) rte_delay_us(1000*(x))\n#define udelay(x) DELAY(x)\n#define msleep(x) DELAY(1000*(x))\n#define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))\n\n#endif /* _I40E_OSDEP_H_ */\n" }, { "path": "drivers/net/i40e/base/i40e_prototype.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _I40E_PROTOTYPE_H_\n#define _I40E_PROTOTYPE_H_\n\n#include \"i40e_type.h\"\n#include \"i40e_alloc.h\"\n#include \"i40e_virtchnl.h\"\n\n/* Prototypes for shared code functions that are not in\n * the standard function pointer structures. These are\n * mostly because they are needed even before the init\n * has happened and will assist in the early SW and FW\n * setup.\n */\n\n/* adminq functions */\nenum i40e_status_code i40e_init_adminq(struct i40e_hw *hw);\nenum i40e_status_code i40e_shutdown_adminq(struct i40e_hw *hw);\nenum i40e_status_code i40e_init_asq(struct i40e_hw *hw);\nenum i40e_status_code i40e_init_arq(struct i40e_hw *hw);\nenum i40e_status_code i40e_alloc_adminq_asq_ring(struct i40e_hw *hw);\nenum i40e_status_code i40e_alloc_adminq_arq_ring(struct i40e_hw *hw);\nenum i40e_status_code i40e_shutdown_asq(struct i40e_hw *hw);\nenum i40e_status_code i40e_shutdown_arq(struct i40e_hw *hw);\nu16 i40e_clean_asq(struct i40e_hw *hw);\nvoid i40e_free_adminq_asq(struct i40e_hw *hw);\nvoid i40e_free_adminq_arq(struct i40e_hw *hw);\nenum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr);\nvoid i40e_adminq_init_ring_data(struct i40e_hw *hw);\nenum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_arq_event_info *e,\n\t\t\t\t\t u16 *events_pending);\nenum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_aq_desc *desc,\n\t\t\t\tvoid *buff, /* can be NULL */\n\t\t\t\tu16 buff_size,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nbool i40e_asq_done(struct i40e_hw *hw);\n\n/* debug function for adminq */\nvoid i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask,\n\t\t void *desc, void *buffer, u16 buf_len);\n\nvoid i40e_idle_aq(struct i40e_hw *hw);\nvoid i40e_resume_aq(struct i40e_hw *hw);\nbool i40e_check_asq_alive(struct i40e_hw *hw);\nenum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);\n\n#ifdef PF_DRIVER\n\nu32 i40e_led_get(struct i40e_hw *hw);\nvoid i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink);\n\n/* admin send queue commands */\n\nenum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,\n\t\t\t\tu16 *fw_major_version, u16 *fw_minor_version,\n\t\t\t\tu32 *fw_build,\n\t\t\t\tu16 *api_major_version, u16 *api_minor_version,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,\n\t\t\t\tu32 reg_addr, u64 reg_val,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,\n\t\t\t\tu32 reg_addr, u64 *reg_val,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,\n\t\t\tbool qualified_modules, bool report_init,\n\t\t\tstruct i40e_aq_get_phy_abilities_resp *abilities,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_aq_set_phy_config *config,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,\n\t\t\t\t bool atomic_reset);\nenum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, u16 mask,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,\n\t\t\t\tu16 max_frame_size, bool crc_en, u16 pacing,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,\n\t\t\t\tu64 *advt_reg,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,\n\t\t\t\tu64 *advt_reg,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, u16 lb_modes,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,\n\t\tbool enable_link, struct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,\n\t\t\t\tbool enable_lse, struct i40e_link_status *link,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,\n\t\t\t\tu64 advt_reg,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_driver_version *dv,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_vsi_context *vsi_ctx,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,\n\t\t\t\tu16 vsi_id, bool set_filter,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,\n\t\tu16 vsi_id, bool set, struct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,\n\t\tu16 vsi_id, bool set, struct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_vsi_context *vsi_ctx,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_vsi_context *vsi_ctx,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,\n\t\t\t\tu16 downlink_seid, u8 enabled_tc,\n\t\t\t\tbool default_port, bool enable_l2_filtering,\n\t\t\t\tu16 *pveb_seid,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,\n\t\t\t\tu16 veb_seid, u16 *switch_id, bool *floating,\n\t\t\t\tu16 *statistic_index, u16 *vebs_used,\n\t\t\t\tu16 *vebs_free,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 vsi_id,\n\t\t\tstruct i40e_aqc_add_macvlan_element_data *mv_list,\n\t\t\tu16 count, struct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 vsi_id,\n\t\t\tstruct i40e_aqc_remove_macvlan_element_data *mv_list,\n\t\t\tu16 count, struct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 vsi_id,\n\t\t\tstruct i40e_aqc_add_remove_vlan_element_data *v_list,\n\t\t\tu8 count, struct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 vsi_id,\n\t\t\tstruct i40e_aqc_add_remove_vlan_element_data *v_list,\n\t\t\tu8 count, struct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,\n\t\t\t\tu32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_aqc_get_switch_config_resp *buf,\n\t\t\t\tu16 buf_size, u16 *start_seid,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,\n\t\t\t\tenum i40e_aq_resources_ids resource,\n\t\t\t\tenum i40e_aq_resource_access_type access,\n\t\t\t\tu8 sdp_number, u64 *timeout,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,\n\t\t\t\tenum i40e_aq_resources_ids resource,\n\t\t\t\tu8 sdp_number,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,\n\t\t\t\tu32 offset, u16 length, void *data,\n\t\t\t\tbool last_command,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,\n\t\t\t\tu32 offset, u16 length, bool last_command,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,\n\t\t\t\tu8 cmd_flags, u32 field_id, void *data,\n\t\t\t\tu16 buf_size, u16 *element_count,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,\n\t\t\t\tu8 cmd_flags, void *data, u16 buf_size,\n\t\t\t\tu16 element_count,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,\n\t\t\t\tvoid *buff, u16 buff_size, u16 *data_size,\n\t\t\t\tenum i40e_admin_queue_opc list_type_opc,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,\n\t\t\t\tu32 offset, u16 length, void *data,\n\t\t\t\tbool last_command,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,\n\t\t\t\tu8 mib_type, void *buff, u16 buff_size,\n\t\t\t\tu16 *local_len, u16 *remote_len,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,\n\t\t\t\tu8 mib_type, void *buff, u16 buff_size,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,\n\t\t\t\tbool enable_update,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,\n\t\t\t\tvoid *buff, u16 buff_size, u16 tlv_len,\n\t\t\t\tu16 *mib_len,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,\n\t\t\t\tu8 bridge_type, void *buff, u16 buff_size,\n\t\t\t\tu16 old_len, u16 new_len, u16 offset,\n\t\t\t\tu16 *mib_len,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,\n\t\t\t\tu8 bridge_type, void *buff, u16 buff_size,\n\t\t\t\tu16 tlv_len, u16 *mib_len,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,\n\t\t\t\tvoid *buff, u16 buff_size,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,\n\t\t\t\tbool start_agent,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,\n\t\t\t\tu16 udp_port, u8 protocol_index,\n\t\t\t\tu8 *filter_index,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,\n\t\t\tu8 *num_entries,\n\t\t\tstruct i40e_aqc_switch_resource_alloc_element_resp *buf,\n\t\t\tu16 count,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,\n\t\t\t\t u16 mac_seid, u16 vsi_seid,\n\t\t\t\t u16 *ret_seid);\nenum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,\n\t\t\t\tu16 vsi_seid, u16 tag, u16 queue_num,\n\t\t\t\tu16 *tags_used, u16 *tags_free,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,\n\t\t\t\tu16 tag, u16 *tags_used, u16 *tags_free,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pe_seid,\n\t\t\t\tu16 etag, u8 num_tags_in_buf, void *buf,\n\t\t\t\tu16 *tags_used, u16 *tags_free,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pe_seid,\n\t\t\t\tu16 etag, u16 *tags_used, u16 *tags_free,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,\n\t\t\t\tu16 old_tag, u16 new_tag, u16 *tags_used,\n\t\t\t\tu16 *tags_free,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,\n\t\t\t\tu16 vlan_id, u16 *stat_index,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,\n\t\t\t\tu16 vlan_id, u16 stat_index,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,\n\t\t\t\tu16 bad_frame_vsi, bool save_bad_pac,\n\t\t\t\tbool pad_short_pac, bool double_vlan,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,\n\t\t\t\t u16 flags, u8 *mac_addr,\n\t\t\t\t struct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,\n\t\t\t\tu16 seid, u16 credit, u8 max_credit,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw,\n\t\t\t\tu8 tcmap, bool request, u8 *tcmap_ret,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_get_hmc_resource_profile(struct i40e_hw *hw,\n\t\t\t\tenum i40e_aq_hmc_profile *profile,\n\t\t\t\tu8 *pe_vf_enabled_count,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(\n\tstruct i40e_hw *hw, u16 seid,\n\tstruct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,\n\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,\n\t\t\tu16 seid,\n\t\t\tstruct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,\n\t\t\t\tenum i40e_aq_hmc_profile profile,\n\t\t\t\tu8 pe_vf_enabled_count,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,\n\t\t\t\tu16 seid, u16 credit, u8 max_bw,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, u16 seid,\n\t\t\tstruct i40e_aqc_configure_vsi_tc_bw_data *bw_data,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,\n\t\t\tu16 seid,\n\t\t\tstruct i40e_aqc_query_vsi_bw_config_resp *bw_data,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,\n\t\t\tu16 seid,\n\t\t\tstruct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,\n\t\tu16 seid,\n\t\tstruct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,\n\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,\n\t\tu16 seid,\n\t\tstruct i40e_aqc_query_port_ets_config_resp *bw_data,\n\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,\n\t\tu16 seid,\n\t\tstruct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,\n\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_read_lldp_cfg(struct i40e_hw *hw,\n\t\t\t\t\tstruct i40e_lldp_variables *lldp_cfg);\nenum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,\n\t\tu16 vsi,\n\t\tstruct i40e_aqc_add_remove_cloud_filters_element_data *filters,\n\t\tu8 filter_count);\n\nenum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,\n\t\tu16 vsi,\n\t\tstruct i40e_aqc_add_remove_cloud_filters_element_data *filters,\n\t\tu8 filter_count);\n\nenum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,\n\t\t\t\tu32 reg_addr0, u32 *reg_val0,\n\t\t\t\tu32 reg_addr1, u32 *reg_val1);\nenum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,\n\t\t\t\tu32 addr, u32 dw_count, void *buffer);\nenum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,\n\t\t\t\tu32 reg_addr0, u32 reg_val0,\n\t\t\t\tu32 reg_addr1, u32 reg_val1);\nenum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,\n\t\t\t\tu32 addr, u32 dw_count, void *buffer);\nenum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw);\nenum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,\n\t\t\t\tu8 bios_mode, bool *reset_needed);\nenum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,\n\t\t\t\tu8 oem_mode);\n\n/* i40e_common */\nenum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw);\nenum i40e_status_code i40e_pf_reset(struct i40e_hw *hw);\nvoid i40e_clear_hw(struct i40e_hw *hw);\nvoid i40e_clear_pxe_mode(struct i40e_hw *hw);\nbool i40e_get_link_status(struct i40e_hw *hw);\nenum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr);\nenum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,\n\t\tu32 *max_bw, u32 *min_bw, bool *min_valid, bool *max_valid);\nenum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,\n\t\t\tstruct i40e_aqc_configure_partition_bw_data *bw_data,\n\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr);\nenum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,\n\t\t\t\t\t u32 pba_num_size);\nvoid i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable);\nenum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw);\n/* prototype for functions used for NVM access */\nenum i40e_status_code i40e_init_nvm(struct i40e_hw *hw);\nenum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,\n\t\t\t\t enum i40e_aq_resource_access_type access);\nvoid i40e_release_nvm(struct i40e_hw *hw);\nenum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,\n\t\t\t\t\t u16 *data);\nenum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,\n\t\t\t\t\t u16 *words, u16 *data);\nenum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module,\n\t\t\t\t\tu32 offset, u16 words, void *data,\n\t\t\t\t\tbool last_command);\nenum i40e_status_code i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,\n\t\t\t\t\t void *data);\nenum i40e_status_code i40e_write_nvm_buffer(struct i40e_hw *hw, u8 module,\n\t\t\t\t\t u32 offset, u16 words, void *data);\nenum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum);\nenum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw);\nenum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,\n\t\t\t\t\t\t u16 *checksum);\nenum i40e_status_code i40e_nvmupd_command(struct i40e_hw *hw,\n\t\t\t\t\t struct i40e_nvm_access *cmd,\n\t\t\t\t\t u8 *bytes, int *);\nvoid i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status);\n#endif /* PF_DRIVER */\n\n#if defined(I40E_QV) || defined(VF_DRIVER)\nenum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw);\n\n#endif\nextern struct i40e_rx_ptype_decoded i40e_ptype_lookup[];\n\nSTATIC INLINE struct i40e_rx_ptype_decoded decode_rx_desc_ptype(u8 ptype)\n{\n\treturn i40e_ptype_lookup[ptype];\n}\n\n/* prototype for functions used for SW spinlocks */\nvoid i40e_init_spinlock(struct i40e_spinlock *sp);\nvoid i40e_acquire_spinlock(struct i40e_spinlock *sp);\nvoid i40e_release_spinlock(struct i40e_spinlock *sp);\nvoid i40e_destroy_spinlock(struct i40e_spinlock *sp);\n\n/* i40e_common for VF drivers*/\nvoid i40e_vf_parse_hw_config(struct i40e_hw *hw,\n\t\t\t struct i40e_virtchnl_vf_resource *msg);\nenum i40e_status_code i40e_vf_reset(struct i40e_hw *hw);\nenum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,\n\t\t\t\tenum i40e_virtchnl_ops v_opcode,\n\t\t\t\tenum i40e_status_code v_retval,\n\t\t\t\tu8 *msg, u16 msglen,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\nenum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,\n\t\t\t\tstruct i40e_filter_control_settings *settings);\nenum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,\n\t\t\t\tu8 *mac_addr, u16 ethtype, u16 flags,\n\t\t\t\tu16 vsi_seid, u16 queue, bool is_add,\n\t\t\t\tstruct i40e_control_filter_stats *stats,\n\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n#endif /* _I40E_PROTOTYPE_H_ */\n" }, { "path": "drivers/net/i40e/base/i40e_register.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _I40E_REGISTER_H_\n#define _I40E_REGISTER_H_\n\n\n#define I40E_GL_ARQBAH 0x000801C0 /* Reset: EMPR */\n#define I40E_GL_ARQBAH_ARQBAH_SHIFT 0\n#define I40E_GL_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAH_ARQBAH_SHIFT)\n#define I40E_GL_ARQBAL 0x000800C0 /* Reset: EMPR */\n#define I40E_GL_ARQBAL_ARQBAL_SHIFT 0\n#define I40E_GL_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAL_ARQBAL_SHIFT)\n#define I40E_GL_ARQH 0x000803C0 /* Reset: EMPR */\n#define I40E_GL_ARQH_ARQH_SHIFT 0\n#define I40E_GL_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_GL_ARQH_ARQH_SHIFT)\n#define I40E_GL_ARQT 0x000804C0 /* Reset: EMPR */\n#define I40E_GL_ARQT_ARQT_SHIFT 0\n#define I40E_GL_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_GL_ARQT_ARQT_SHIFT)\n#define I40E_GL_ATQBAH 0x00080140 /* Reset: EMPR */\n#define I40E_GL_ATQBAH_ATQBAH_SHIFT 0\n#define I40E_GL_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAH_ATQBAH_SHIFT)\n#define I40E_GL_ATQBAL 0x00080040 /* Reset: EMPR */\n#define I40E_GL_ATQBAL_ATQBAL_SHIFT 0\n#define I40E_GL_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAL_ATQBAL_SHIFT)\n#define I40E_GL_ATQH 0x00080340 /* Reset: EMPR */\n#define I40E_GL_ATQH_ATQH_SHIFT 0\n#define I40E_GL_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_GL_ATQH_ATQH_SHIFT)\n#define I40E_GL_ATQLEN 0x00080240 /* Reset: EMPR */\n#define I40E_GL_ATQLEN_ATQLEN_SHIFT 0\n#define I40E_GL_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_GL_ATQLEN_ATQLEN_SHIFT)\n#define I40E_GL_ATQLEN_ATQVFE_SHIFT 28\n#define I40E_GL_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQVFE_SHIFT)\n#define I40E_GL_ATQLEN_ATQOVFL_SHIFT 29\n#define I40E_GL_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQOVFL_SHIFT)\n#define I40E_GL_ATQLEN_ATQCRIT_SHIFT 30\n#define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT)\n#define I40E_GL_ATQLEN_ATQENABLE_SHIFT 31\n#define I40E_GL_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQENABLE_SHIFT)\n#define I40E_GL_ATQT 0x00080440 /* Reset: EMPR */\n#define I40E_GL_ATQT_ATQT_SHIFT 0\n#define I40E_GL_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_GL_ATQT_ATQT_SHIFT)\n#define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */\n#define I40E_PF_ARQBAH_ARQBAH_SHIFT 0\n#define I40E_PF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAH_ARQBAH_SHIFT)\n#define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */\n#define I40E_PF_ARQBAL_ARQBAL_SHIFT 0\n#define I40E_PF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAL_ARQBAL_SHIFT)\n#define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */\n#define I40E_PF_ARQH_ARQH_SHIFT 0\n#define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT)\n#define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */\n#define I40E_PF_ARQLEN_ARQLEN_SHIFT 0\n#define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT)\n#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28\n#define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT)\n#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29\n#define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT)\n#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30\n#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)\n#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31\n#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT)\n#define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */\n#define I40E_PF_ARQT_ARQT_SHIFT 0\n#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT)\n#define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */\n#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0\n#define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT)\n#define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */\n#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0\n#define I40E_PF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAL_ATQBAL_SHIFT)\n#define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */\n#define I40E_PF_ATQH_ATQH_SHIFT 0\n#define I40E_PF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_PF_ATQH_ATQH_SHIFT)\n#define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */\n#define I40E_PF_ATQLEN_ATQLEN_SHIFT 0\n#define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT)\n#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28\n#define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT)\n#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29\n#define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT)\n#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30\n#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)\n#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31\n#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQENABLE_SHIFT)\n#define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */\n#define I40E_PF_ATQT_ATQT_SHIFT 0\n#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT)\n#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */\n#define I40E_VF_ARQBAH_MAX_INDEX 127\n#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0\n#define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT)\n#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */\n#define I40E_VF_ARQBAL_MAX_INDEX 127\n#define I40E_VF_ARQBAL_ARQBAL_SHIFT 0\n#define I40E_VF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL_ARQBAL_SHIFT)\n#define I40E_VF_ARQH(_VF) (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */\n#define I40E_VF_ARQH_MAX_INDEX 127\n#define I40E_VF_ARQH_ARQH_SHIFT 0\n#define I40E_VF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH_ARQH_SHIFT)\n#define I40E_VF_ARQLEN(_VF) (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */\n#define I40E_VF_ARQLEN_MAX_INDEX 127\n#define I40E_VF_ARQLEN_ARQLEN_SHIFT 0\n#define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT)\n#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28\n#define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT)\n#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29\n#define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT)\n#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30\n#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT)\n#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31\n#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT)\n#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */\n#define I40E_VF_ARQT_MAX_INDEX 127\n#define I40E_VF_ARQT_ARQT_SHIFT 0\n#define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT)\n#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */\n#define I40E_VF_ATQBAH_MAX_INDEX 127\n#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0\n#define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT)\n#define I40E_VF_ATQBAL(_VF) (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */\n#define I40E_VF_ATQBAL_MAX_INDEX 127\n#define I40E_VF_ATQBAL_ATQBAL_SHIFT 0\n#define I40E_VF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL_ATQBAL_SHIFT)\n#define I40E_VF_ATQH(_VF) (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */\n#define I40E_VF_ATQH_MAX_INDEX 127\n#define I40E_VF_ATQH_ATQH_SHIFT 0\n#define I40E_VF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH_ATQH_SHIFT)\n#define I40E_VF_ATQLEN(_VF) (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */\n#define I40E_VF_ATQLEN_MAX_INDEX 127\n#define I40E_VF_ATQLEN_ATQLEN_SHIFT 0\n#define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT)\n#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28\n#define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT)\n#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29\n#define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT)\n#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30\n#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT)\n#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31\n#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT)\n#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */\n#define I40E_VF_ATQT_MAX_INDEX 127\n#define I40E_VF_ATQT_ATQT_SHIFT 0\n#define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT)\n#define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */\n#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0\n#define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT)\n#define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */\n#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT 0\n#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT)\n#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT 4\n#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT)\n#define I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT 8\n#define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT)\n#define I40E_PFCM_LAN_ERRINFO 0x0010C000 /* Reset: PFR */\n#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT 0\n#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT)\n#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT 4\n#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT)\n#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT 8\n#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT)\n#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT 16\n#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT)\n#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24\n#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT)\n#define I40E_PFCM_LANCTXCTL 0x0010C300 /* Reset: CORER */\n#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT 0\n#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT)\n#define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT 12\n#define I40E_PFCM_LANCTXCTL_SUB_LINE_MASK I40E_MASK(0x7, I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT)\n#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT 15\n#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT)\n#define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT 17\n#define I40E_PFCM_LANCTXCTL_OP_CODE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT)\n#define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_PFCM_LANCTXDATA_MAX_INDEX 3\n#define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0\n#define I40E_PFCM_LANCTXDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFCM_LANCTXDATA_DATA_SHIFT)\n#define I40E_PFCM_LANCTXSTAT 0x0010C380 /* Reset: CORER */\n#define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0\n#define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT)\n#define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1\n#define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT)\n#define I40E_VFCM_PE_ERRDATA1(_VF) (0x00138800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */\n#define I40E_VFCM_PE_ERRDATA1_MAX_INDEX 127\n#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT 0\n#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT)\n#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT 4\n#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT)\n#define I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT 8\n#define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT)\n#define I40E_VFCM_PE_ERRINFO1(_VF) (0x00138400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */\n#define I40E_VFCM_PE_ERRINFO1_MAX_INDEX 127\n#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT 0\n#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT)\n#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT 4\n#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT)\n#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8\n#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT)\n#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16\n#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT)\n#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24\n#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT)\n#define I40E_GLDCB_GENC 0x00083044 /* Reset: CORER */\n#define I40E_GLDCB_GENC_PCIRTT_SHIFT 0\n#define I40E_GLDCB_GENC_PCIRTT_MASK I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT)\n#define I40E_GLDCB_RUPTI 0x00122618 /* Reset: CORER */\n#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0\n#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT)\n#define I40E_PRTDCB_FCCFG 0x001E4640 /* Reset: GLOBR */\n#define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3\n#define I40E_PRTDCB_FCCFG_TFCE_MASK I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT)\n#define I40E_PRTDCB_FCRTV 0x001E4600 /* Reset: GLOBR */\n#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT 0\n#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT)\n#define I40E_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: GLOBR */\n#define I40E_PRTDCB_FCTTVN_MAX_INDEX 3\n#define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT 0\n#define I40E_PRTDCB_FCTTVN_TTV_2N_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT)\n#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16\n#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT)\n#define I40E_PRTDCB_GENC 0x00083000 /* Reset: CORER */\n#define I40E_PRTDCB_GENC_RESERVED_1_SHIFT 0\n#define I40E_PRTDCB_GENC_RESERVED_1_MASK I40E_MASK(0x3, I40E_PRTDCB_GENC_RESERVED_1_SHIFT)\n#define I40E_PRTDCB_GENC_NUMTC_SHIFT 2\n#define I40E_PRTDCB_GENC_NUMTC_MASK I40E_MASK(0xF, I40E_PRTDCB_GENC_NUMTC_SHIFT)\n#define I40E_PRTDCB_GENC_FCOEUP_SHIFT 6\n#define I40E_PRTDCB_GENC_FCOEUP_MASK I40E_MASK(0x7, I40E_PRTDCB_GENC_FCOEUP_SHIFT)\n#define I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT 9\n#define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK I40E_MASK(0x1, I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT)\n#define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16\n#define I40E_PRTDCB_GENC_PFCLDA_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT)\n#define I40E_PRTDCB_GENS 0x00083020 /* Reset: CORER */\n#define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0\n#define I40E_PRTDCB_GENS_DCBX_STATUS_MASK I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT)\n#define I40E_PRTDCB_MFLCN 0x001E2400 /* Reset: GLOBR */\n#define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0\n#define I40E_PRTDCB_MFLCN_PMCF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_PMCF_SHIFT)\n#define I40E_PRTDCB_MFLCN_DPF_SHIFT 1\n#define I40E_PRTDCB_MFLCN_DPF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_DPF_SHIFT)\n#define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2\n#define I40E_PRTDCB_MFLCN_RPFCM_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RPFCM_SHIFT)\n#define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3\n#define I40E_PRTDCB_MFLCN_RFCE_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RFCE_SHIFT)\n#define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4\n#define I40E_PRTDCB_MFLCN_RPFCE_MASK I40E_MASK(0xFF, I40E_PRTDCB_MFLCN_RPFCE_SHIFT)\n#define I40E_PRTDCB_RETSC 0x001223E0 /* Reset: CORER */\n#define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0\n#define I40E_PRTDCB_RETSC_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_ETS_MODE_SHIFT)\n#define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1\n#define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT)\n#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2\n#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK I40E_MASK(0xF, I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT)\n#define I40E_PRTDCB_RETSC_LLTC_SHIFT 8\n#define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT)\n#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */\n#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7\n#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0\n#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT)\n#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30\n#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)\n#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31\n#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)\n#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */\n#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0\n#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)\n#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8\n#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT)\n#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16\n#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT)\n#define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */\n#define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0\n#define I40E_PRTDCB_RUP_NOVLANUP_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP_NOVLANUP_SHIFT)\n#define I40E_PRTDCB_RUP2TC 0x001C09A0 /* Reset: CORER */\n#define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0\n#define I40E_PRTDCB_RUP2TC_UP0TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP0TC_SHIFT)\n#define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3\n#define I40E_PRTDCB_RUP2TC_UP1TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP1TC_SHIFT)\n#define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6\n#define I40E_PRTDCB_RUP2TC_UP2TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP2TC_SHIFT)\n#define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9\n#define I40E_PRTDCB_RUP2TC_UP3TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP3TC_SHIFT)\n#define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12\n#define I40E_PRTDCB_RUP2TC_UP4TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT)\n#define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15\n#define I40E_PRTDCB_RUP2TC_UP5TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT)\n#define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18\n#define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT)\n#define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21\n#define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)\n#define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */\n#define I40E_PRTDCB_RUPTQ_MAX_INDEX 7\n#define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0\n#define I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT)\n#define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */\n#define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0\n#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT)\n#define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */\n#define I40E_PRTDCB_TCMSTC_MAX_INDEX 7\n#define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0\n#define I40E_PRTDCB_TCMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT)\n#define I40E_PRTDCB_TCPMC 0x000A21A0 /* Reset: CORER */\n#define I40E_PRTDCB_TCPMC_CPM_SHIFT 0\n#define I40E_PRTDCB_TCPMC_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_CPM_SHIFT)\n#define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13\n#define I40E_PRTDCB_TCPMC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_LLTC_SHIFT)\n#define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30\n#define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT)\n#define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */\n#define I40E_PRTDCB_TCWSTC_MAX_INDEX 7\n#define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0\n#define I40E_PRTDCB_TCWSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSTC_MSTC_SHIFT)\n#define I40E_PRTDCB_TDPMC 0x000A0180 /* Reset: CORER */\n#define I40E_PRTDCB_TDPMC_DPM_SHIFT 0\n#define I40E_PRTDCB_TDPMC_DPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_TDPMC_DPM_SHIFT)\n#define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30\n#define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT)\n#define I40E_PRTDCB_TETSC_TCB 0x000AE060 /* Reset: CORER */\n#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0\n#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT)\n#define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8\n#define I40E_PRTDCB_TETSC_TCB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT)\n#define I40E_PRTDCB_TETSC_TPB 0x00098060 /* Reset: CORER */\n#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0\n#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT)\n#define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8\n#define I40E_PRTDCB_TETSC_TPB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT)\n#define I40E_PRTDCB_TFCS 0x001E4560 /* Reset: GLOBR */\n#define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0\n#define I40E_PRTDCB_TFCS_TXOFF_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF_SHIFT)\n#define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8\n#define I40E_PRTDCB_TFCS_TXOFF0_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF0_SHIFT)\n#define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9\n#define I40E_PRTDCB_TFCS_TXOFF1_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF1_SHIFT)\n#define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10\n#define I40E_PRTDCB_TFCS_TXOFF2_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF2_SHIFT)\n#define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11\n#define I40E_PRTDCB_TFCS_TXOFF3_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF3_SHIFT)\n#define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12\n#define I40E_PRTDCB_TFCS_TXOFF4_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF4_SHIFT)\n#define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13\n#define I40E_PRTDCB_TFCS_TXOFF5_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF5_SHIFT)\n#define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14\n#define I40E_PRTDCB_TFCS_TXOFF6_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF6_SHIFT)\n#define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15\n#define I40E_PRTDCB_TFCS_TXOFF7_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF7_SHIFT)\n#define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */\n#define I40E_PRTDCB_TPFCTS_MAX_INDEX 7\n#define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0\n#define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT)\n#define I40E_GLFCOE_RCTL 0x00269B94 /* Reset: CORER */\n#define I40E_GLFCOE_RCTL_FCOEVER_SHIFT 0\n#define I40E_GLFCOE_RCTL_FCOEVER_MASK I40E_MASK(0xF, I40E_GLFCOE_RCTL_FCOEVER_SHIFT)\n#define I40E_GLFCOE_RCTL_SAVBAD_SHIFT 4\n#define I40E_GLFCOE_RCTL_SAVBAD_MASK I40E_MASK(0x1, I40E_GLFCOE_RCTL_SAVBAD_SHIFT)\n#define I40E_GLFCOE_RCTL_ICRC_SHIFT 5\n#define I40E_GLFCOE_RCTL_ICRC_MASK I40E_MASK(0x1, I40E_GLFCOE_RCTL_ICRC_SHIFT)\n#define I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT 16\n#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT)\n#define I40E_GL_FWSTS 0x00083048 /* Reset: POR */\n#define I40E_GL_FWSTS_FWS0B_SHIFT 0\n#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT)\n#define I40E_GL_FWSTS_FWRI_SHIFT 9\n#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT)\n#define I40E_GL_FWSTS_FWS1B_SHIFT 16\n#define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT)\n#define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */\n#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0\n#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT)\n#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4\n#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT)\n#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8\n#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT)\n#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12\n#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT)\n#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT 16\n#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT)\n#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT 20\n#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT)\n#define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */\n#define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29\n#define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0\n#define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)\n#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3\n#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)\n#define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4\n#define I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)\n#define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5\n#define I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)\n#define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6\n#define I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)\n#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7\n#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)\n#define I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT 10\n#define I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT)\n#define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11\n#define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT)\n#define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12\n#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)\n#define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT 17\n#define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT)\n#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19\n#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)\n#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20\n#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)\n#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT 26\n#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK I40E_MASK(0xF, I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT)\n#define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */\n#define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0\n#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT)\n#define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5\n#define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)\n#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6\n#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)\n#define I40E_GLGEN_GPIO_STAT 0x0008817C /* Reset: POR */\n#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT 0\n#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT)\n#define I40E_GLGEN_GPIO_TRANSIT 0x00088180 /* Reset: POR */\n#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT 0\n#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT)\n#define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */\n#define I40E_GLGEN_I2CCMD_MAX_INDEX 3\n#define I40E_GLGEN_I2CCMD_DATA_SHIFT 0\n#define I40E_GLGEN_I2CCMD_DATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_I2CCMD_DATA_SHIFT)\n#define I40E_GLGEN_I2CCMD_REGADD_SHIFT 16\n#define I40E_GLGEN_I2CCMD_REGADD_MASK I40E_MASK(0xFF, I40E_GLGEN_I2CCMD_REGADD_SHIFT)\n#define I40E_GLGEN_I2CCMD_PHYADD_SHIFT 24\n#define I40E_GLGEN_I2CCMD_PHYADD_MASK I40E_MASK(0x7, I40E_GLGEN_I2CCMD_PHYADD_SHIFT)\n#define I40E_GLGEN_I2CCMD_OP_SHIFT 27\n#define I40E_GLGEN_I2CCMD_OP_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_OP_SHIFT)\n#define I40E_GLGEN_I2CCMD_RESET_SHIFT 28\n#define I40E_GLGEN_I2CCMD_RESET_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_RESET_SHIFT)\n#define I40E_GLGEN_I2CCMD_R_SHIFT 29\n#define I40E_GLGEN_I2CCMD_R_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_R_SHIFT)\n#define I40E_GLGEN_I2CCMD_E_SHIFT 31\n#define I40E_GLGEN_I2CCMD_E_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_E_SHIFT)\n#define I40E_GLGEN_I2CPARAMS(_i) (0x000881AC + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */\n#define I40E_GLGEN_I2CPARAMS_MAX_INDEX 3\n#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT 0\n#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK I40E_MASK(0x1F, I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT)\n#define I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT 5\n#define I40E_GLGEN_I2CPARAMS_READ_TIME_MASK I40E_MASK(0x7, I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT)\n#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT 8\n#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT)\n#define I40E_GLGEN_I2CPARAMS_CLK_SHIFT 9\n#define I40E_GLGEN_I2CPARAMS_CLK_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_SHIFT)\n#define I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT 10\n#define I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT)\n#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT 11\n#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT)\n#define I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT 12\n#define I40E_GLGEN_I2CPARAMS_DATA_IN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT)\n#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT 13\n#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT)\n#define I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT 14\n#define I40E_GLGEN_I2CPARAMS_CLK_IN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT)\n#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT 15\n#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT)\n#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT 31\n#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT)\n#define I40E_GLGEN_LED_CTL 0x00088178 /* Reset: POR */\n#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT 0\n#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT)\n#define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */\n#define I40E_GLGEN_MDIO_CTRL_MAX_INDEX 3\n#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0\n#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK I40E_MASK(0x1FFFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT)\n#define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17\n#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT)\n#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18\n#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x7FF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)\n#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT 29\n#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK I40E_MASK(0x7, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT)\n#define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */\n#define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3\n#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0\n#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT)\n#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1\n#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT)\n#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5\n#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT)\n#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT 10\n#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT)\n#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT 15\n#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT)\n#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT 20\n#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT)\n#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT 25\n#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT)\n#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT 31\n#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT)\n#define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */\n#define I40E_GLGEN_MSCA_MAX_INDEX 3\n#define I40E_GLGEN_MSCA_MDIADD_SHIFT 0\n#define I40E_GLGEN_MSCA_MDIADD_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSCA_MDIADD_SHIFT)\n#define I40E_GLGEN_MSCA_DEVADD_SHIFT 16\n#define I40E_GLGEN_MSCA_DEVADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_DEVADD_SHIFT)\n#define I40E_GLGEN_MSCA_PHYADD_SHIFT 21\n#define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT)\n#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26\n#define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT)\n#define I40E_GLGEN_MSCA_STCODE_SHIFT 28\n#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT)\n#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30\n#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)\n#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31\n#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)\n#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */\n#define I40E_GLGEN_MSRWD_MAX_INDEX 3\n#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0\n#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT)\n#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16\n#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)\n#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */\n#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0\n#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)\n#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16\n#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)\n#define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */\n#define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0\n#define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT)\n#define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2\n#define I40E_GLGEN_RSTAT_RESET_TYPE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT)\n#define I40E_GLGEN_RSTAT_CORERCNT_SHIFT 4\n#define I40E_GLGEN_RSTAT_CORERCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_CORERCNT_SHIFT)\n#define I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT 6\n#define I40E_GLGEN_RSTAT_GLOBRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT)\n#define I40E_GLGEN_RSTAT_EMPRCNT_SHIFT 8\n#define I40E_GLGEN_RSTAT_EMPRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_EMPRCNT_SHIFT)\n#define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10\n#define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT)\n#define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */\n#define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0\n#define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)\n#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8\n#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT)\n#define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */\n#define I40E_GLGEN_RTRIG_CORER_SHIFT 0\n#define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT)\n#define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1\n#define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT)\n#define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2\n#define I40E_GLGEN_RTRIG_EMPFWR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_EMPFWR_SHIFT)\n#define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */\n#define I40E_GLGEN_STAT_HWRSVD0_SHIFT 0\n#define I40E_GLGEN_STAT_HWRSVD0_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD0_SHIFT)\n#define I40E_GLGEN_STAT_DCBEN_SHIFT 2\n#define I40E_GLGEN_STAT_DCBEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_DCBEN_SHIFT)\n#define I40E_GLGEN_STAT_VTEN_SHIFT 3\n#define I40E_GLGEN_STAT_VTEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_VTEN_SHIFT)\n#define I40E_GLGEN_STAT_FCOEN_SHIFT 4\n#define I40E_GLGEN_STAT_FCOEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_FCOEN_SHIFT)\n#define I40E_GLGEN_STAT_EVBEN_SHIFT 5\n#define I40E_GLGEN_STAT_EVBEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_EVBEN_SHIFT)\n#define I40E_GLGEN_STAT_HWRSVD1_SHIFT 6\n#define I40E_GLGEN_STAT_HWRSVD1_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD1_SHIFT)\n#define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLGEN_VFLRSTAT_MAX_INDEX 3\n#define I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT 0\n#define I40E_GLGEN_VFLRSTAT_VFLRE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT)\n#define I40E_GLVFGEN_TIMER 0x000881BC /* Reset: CORER */\n#define I40E_GLVFGEN_TIMER_GTIME_SHIFT 0\n#define I40E_GLVFGEN_TIMER_GTIME_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVFGEN_TIMER_GTIME_SHIFT)\n#define I40E_PFGEN_CTRL 0x00092400 /* Reset: PFR */\n#define I40E_PFGEN_CTRL_PFSWR_SHIFT 0\n#define I40E_PFGEN_CTRL_PFSWR_MASK I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT)\n#define I40E_PFGEN_DRUN 0x00092500 /* Reset: CORER */\n#define I40E_PFGEN_DRUN_DRVUNLD_SHIFT 0\n#define I40E_PFGEN_DRUN_DRVUNLD_MASK I40E_MASK(0x1, I40E_PFGEN_DRUN_DRVUNLD_SHIFT)\n#define I40E_PFGEN_PORTNUM 0x001C0480 /* Reset: CORER */\n#define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0\n#define I40E_PFGEN_PORTNUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT)\n#define I40E_PFGEN_STATE 0x00088000 /* Reset: CORER */\n#define I40E_PFGEN_STATE_RESERVED_0_SHIFT 0\n#define I40E_PFGEN_STATE_RESERVED_0_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_RESERVED_0_SHIFT)\n#define I40E_PFGEN_STATE_PFFCEN_SHIFT 1\n#define I40E_PFGEN_STATE_PFFCEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFFCEN_SHIFT)\n#define I40E_PFGEN_STATE_PFLINKEN_SHIFT 2\n#define I40E_PFGEN_STATE_PFLINKEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFLINKEN_SHIFT)\n#define I40E_PFGEN_STATE_PFSCEN_SHIFT 3\n#define I40E_PFGEN_STATE_PFSCEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFSCEN_SHIFT)\n#define I40E_PRTGEN_CNF 0x000B8120 /* Reset: POR */\n#define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0\n#define I40E_PRTGEN_CNF_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT)\n#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT 1\n#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT)\n#define I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT 2\n#define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT)\n#define I40E_PRTGEN_CNF2 0x000B8160 /* Reset: POR */\n#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT 0\n#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT)\n#define I40E_PRTGEN_STATUS 0x000B8100 /* Reset: POR */\n#define I40E_PRTGEN_STATUS_PORT_VALID_SHIFT 0\n#define I40E_PRTGEN_STATUS_PORT_VALID_MASK I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_VALID_SHIFT)\n#define I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT 1\n#define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT)\n#define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */\n#define I40E_VFGEN_RSTAT1_MAX_INDEX 127\n#define I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT 0\n#define I40E_VFGEN_RSTAT1_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT)\n#define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_VPGEN_VFRSTAT_MAX_INDEX 127\n#define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0\n#define I40E_VPGEN_VFRSTAT_VFRD_MASK I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT)\n#define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_VPGEN_VFRTRIG_MAX_INDEX 127\n#define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0\n#define I40E_VPGEN_VFRTRIG_VFSWR_MASK I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT)\n#define I40E_VSIGEN_RSTAT(_VSI) (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_VSIGEN_RSTAT_MAX_INDEX 383\n#define I40E_VSIGEN_RSTAT_VMRD_SHIFT 0\n#define I40E_VSIGEN_RSTAT_VMRD_MASK I40E_MASK(0x1, I40E_VSIGEN_RSTAT_VMRD_SHIFT)\n#define I40E_VSIGEN_RTRIG(_VSI) (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_VSIGEN_RTRIG_MAX_INDEX 383\n#define I40E_VSIGEN_RTRIG_VMSWR_SHIFT 0\n#define I40E_VSIGEN_RTRIG_VMSWR_MASK I40E_MASK(0x1, I40E_VSIGEN_RTRIG_VMSWR_SHIFT)\n#define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_FCOEDDPBASE_MAX_INDEX 15\n#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0\n#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT)\n#define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_FCOEDDPCNT_MAX_INDEX 15\n#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT 0\n#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK I40E_MASK(0xFFFFF, I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT)\n#define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 /* Reset: CORER */\n#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT 0\n#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT)\n#define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_FCOEFBASE_MAX_INDEX 15\n#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0\n#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT)\n#define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_FCOEFCNT_MAX_INDEX 15\n#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT 0\n#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT)\n#define I40E_GLHMC_FCOEFMAX 0x000C20D0 /* Reset: CORER */\n#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0\n#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT)\n#define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 /* Reset: CORER */\n#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT 0\n#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT)\n#define I40E_GLHMC_FCOEMAX 0x000C2014 /* Reset: CORER */\n#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT 0\n#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK I40E_MASK(0x1FFF, I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT)\n#define I40E_GLHMC_FSIAVBASE(_i) (0x000C5600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_FSIAVBASE_MAX_INDEX 15\n#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT 0\n#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT)\n#define I40E_GLHMC_FSIAVCNT(_i) (0x000C5700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_FSIAVCNT_MAX_INDEX 15\n#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT 0\n#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT)\n#define I40E_GLHMC_FSIAVCNT_RSVD_SHIFT 29\n#define I40E_GLHMC_FSIAVCNT_RSVD_MASK I40E_MASK(0x7, I40E_GLHMC_FSIAVCNT_RSVD_SHIFT)\n#define I40E_GLHMC_FSIAVMAX 0x000C2068 /* Reset: CORER */\n#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT 0\n#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT)\n#define I40E_GLHMC_FSIAVOBJSZ 0x000C2064 /* Reset: CORER */\n#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT 0\n#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT)\n#define I40E_GLHMC_FSIMCBASE(_i) (0x000C6000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_FSIMCBASE_MAX_INDEX 15\n#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT 0\n#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT)\n#define I40E_GLHMC_FSIMCCNT(_i) (0x000C6100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_FSIMCCNT_MAX_INDEX 15\n#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT 0\n#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT)\n#define I40E_GLHMC_FSIMCMAX 0x000C2060 /* Reset: CORER */\n#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT 0\n#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK I40E_MASK(0x3FFF, I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT)\n#define I40E_GLHMC_FSIMCOBJSZ 0x000C205c /* Reset: CORER */\n#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT 0\n#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT)\n#define I40E_GLHMC_LANQMAX 0x000C2008 /* Reset: CORER */\n#define I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT 0\n#define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT)\n#define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_LANRXBASE_MAX_INDEX 15\n#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0\n#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT)\n#define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_LANRXCNT_MAX_INDEX 15\n#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT 0\n#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT)\n#define I40E_GLHMC_LANRXOBJSZ 0x000C200c /* Reset: CORER */\n#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT 0\n#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT)\n#define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_LANTXBASE_MAX_INDEX 15\n#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0\n#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT)\n#define I40E_GLHMC_LANTXBASE_RSVD_SHIFT 24\n#define I40E_GLHMC_LANTXBASE_RSVD_MASK I40E_MASK(0xFF, I40E_GLHMC_LANTXBASE_RSVD_SHIFT)\n#define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_LANTXCNT_MAX_INDEX 15\n#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT 0\n#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT)\n#define I40E_GLHMC_LANTXOBJSZ 0x000C2004 /* Reset: CORER */\n#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT 0\n#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT)\n#define I40E_GLHMC_PFASSIGN(_i) (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_PFASSIGN_MAX_INDEX 15\n#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT 0\n#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK I40E_MASK(0xF, I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT)\n#define I40E_GLHMC_SDPART(_i) (0x000C0800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLHMC_SDPART_MAX_INDEX 15\n#define I40E_GLHMC_SDPART_PMSDBASE_SHIFT 0\n#define I40E_GLHMC_SDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_SDPART_PMSDBASE_SHIFT)\n#define I40E_GLHMC_SDPART_PMSDSIZE_SHIFT 16\n#define I40E_GLHMC_SDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_SDPART_PMSDSIZE_SHIFT)\n#define I40E_PFHMC_ERRORDATA 0x000C0500 /* Reset: PFR */\n#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT 0\n#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK I40E_MASK(0x3FFFFFFF, I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT)\n#define I40E_PFHMC_ERRORINFO 0x000C0400 /* Reset: PFR */\n#define I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT 0\n#define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT)\n#define I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT 7\n#define I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT)\n#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT 8\n#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK I40E_MASK(0xF, I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT)\n#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT 16\n#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT)\n#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT 31\n#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT)\n#define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */\n#define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0\n#define I40E_PFHMC_PDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_PDINV_PMSDIDX_SHIFT)\n#define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16\n#define I40E_PFHMC_PDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_PFHMC_PDINV_PMPDIDX_SHIFT)\n#define I40E_PFHMC_SDCMD 0x000C0000 /* Reset: PFR */\n#define I40E_PFHMC_SDCMD_PMSDIDX_SHIFT 0\n#define I40E_PFHMC_SDCMD_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_SDCMD_PMSDIDX_SHIFT)\n#define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31\n#define I40E_PFHMC_SDCMD_PMSDWR_MASK I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDWR_SHIFT)\n#define I40E_PFHMC_SDDATAHIGH 0x000C0200 /* Reset: PFR */\n#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT 0\n#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT)\n#define I40E_PFHMC_SDDATALOW 0x000C0100 /* Reset: PFR */\n#define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0\n#define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)\n#define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1\n#define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT)\n#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2\n#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK I40E_MASK(0x3FF, I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT)\n#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT 12\n#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK I40E_MASK(0xFFFFF, I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT)\n#define I40E_GL_GP_FUSE(_i) (0x0009400C + ((_i) * 4)) /* _i=0...28 */ /* Reset: POR */\n#define I40E_GL_GP_FUSE_MAX_INDEX 28\n#define I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT 0\n#define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT)\n#define I40E_GL_UFUSE 0x00094008 /* Reset: POR */\n#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT 1\n#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK I40E_MASK(0x1, I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT)\n#define I40E_GL_UFUSE_NIC_ID_SHIFT 2\n#define I40E_GL_UFUSE_NIC_ID_MASK I40E_MASK(0x1, I40E_GL_UFUSE_NIC_ID_SHIFT)\n#define I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT 10\n#define I40E_GL_UFUSE_ULT_LOCKOUT_MASK I40E_MASK(0x1, I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT)\n#define I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT 11\n#define I40E_GL_UFUSE_CLS_LOCKOUT_MASK I40E_MASK(0x1, I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT)\n#define I40E_EMPINT_GPIO_ENA 0x00088188 /* Reset: POR */\n#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT 0\n#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT 1\n#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT 2\n#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT 3\n#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT 4\n#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT 5\n#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT 6\n#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT 7\n#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT 8\n#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT 9\n#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT 10\n#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT 11\n#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT 12\n#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT 13\n#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT 14\n#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT 15\n#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT 16\n#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT 17\n#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT 18\n#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT 19\n#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT 20\n#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT 21\n#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT 22\n#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT 23\n#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT 24\n#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT 25\n#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT 26\n#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT 27\n#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT 28\n#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT)\n#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT 29\n#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT)\n#define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 /* Reset: CORER */\n#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT 0\n#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT)\n#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4\n#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT)\n#define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */\n#define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0\n#define I40E_PFINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT)\n#define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11\n#define I40E_PFINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_AEQCTL_ITR_INDX_SHIFT)\n#define I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT 13\n#define I40E_PFINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT)\n#define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30\n#define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT)\n#define I40E_PFINT_AEQCTL_INTEVENT_SHIFT 31\n#define I40E_PFINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_INTEVENT_SHIFT)\n#define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */\n#define I40E_PFINT_CEQCTL_MAX_INDEX 511\n#define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0\n#define I40E_PFINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT)\n#define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11\n#define I40E_PFINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_ITR_INDX_SHIFT)\n#define I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT 13\n#define I40E_PFINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT)\n#define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16\n#define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT)\n#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27\n#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT)\n#define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30\n#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT)\n#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31\n#define I40E_PFINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT)\n#define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */\n#define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0\n#define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT)\n#define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1\n#define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT)\n#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2\n#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT)\n#define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3\n#define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)\n#define I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT 5\n#define I40E_PFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT)\n#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24\n#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)\n#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25\n#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)\n#define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31\n#define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT)\n#define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */\n#define I40E_PFINT_DYN_CTLN_MAX_INDEX 511\n#define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0\n#define I40E_PFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT)\n#define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1\n#define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT)\n#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2\n#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT)\n#define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3\n#define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)\n#define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5\n#define I40E_PFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT)\n#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24\n#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)\n#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25\n#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)\n#define I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT 31\n#define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT)\n#define I40E_PFINT_GPIO_ENA 0x00088080 /* Reset: CORER */\n#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT 0\n#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT 1\n#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT 2\n#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT 3\n#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT 4\n#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT 5\n#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT 6\n#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT 7\n#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT 8\n#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT 9\n#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT 10\n#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT 11\n#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT 12\n#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT 13\n#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT 14\n#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT 15\n#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT 16\n#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT 17\n#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT 18\n#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT 19\n#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT 20\n#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT 21\n#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT 22\n#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT 23\n#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT 24\n#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT 25\n#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT 26\n#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT 27\n#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT 28\n#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT)\n#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT 29\n#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT)\n#define I40E_PFINT_ICR0 0x00038780 /* Reset: CORER */\n#define I40E_PFINT_ICR0_INTEVENT_SHIFT 0\n#define I40E_PFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT)\n#define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1\n#define I40E_PFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_0_SHIFT)\n#define I40E_PFINT_ICR0_QUEUE_1_SHIFT 2\n#define I40E_PFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_1_SHIFT)\n#define I40E_PFINT_ICR0_QUEUE_2_SHIFT 3\n#define I40E_PFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_2_SHIFT)\n#define I40E_PFINT_ICR0_QUEUE_3_SHIFT 4\n#define I40E_PFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_3_SHIFT)\n#define I40E_PFINT_ICR0_QUEUE_4_SHIFT 5\n#define I40E_PFINT_ICR0_QUEUE_4_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_4_SHIFT)\n#define I40E_PFINT_ICR0_QUEUE_5_SHIFT 6\n#define I40E_PFINT_ICR0_QUEUE_5_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_5_SHIFT)\n#define I40E_PFINT_ICR0_QUEUE_6_SHIFT 7\n#define I40E_PFINT_ICR0_QUEUE_6_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_6_SHIFT)\n#define I40E_PFINT_ICR0_QUEUE_7_SHIFT 8\n#define I40E_PFINT_ICR0_QUEUE_7_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_7_SHIFT)\n#define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16\n#define I40E_PFINT_ICR0_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ECC_ERR_SHIFT)\n#define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19\n#define I40E_PFINT_ICR0_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_MAL_DETECT_SHIFT)\n#define I40E_PFINT_ICR0_GRST_SHIFT 20\n#define I40E_PFINT_ICR0_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GRST_SHIFT)\n#define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21\n#define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT)\n#define I40E_PFINT_ICR0_GPIO_SHIFT 22\n#define I40E_PFINT_ICR0_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GPIO_SHIFT)\n#define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23\n#define I40E_PFINT_ICR0_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_TIMESYNC_SHIFT)\n#define I40E_PFINT_ICR0_STORM_DETECT_SHIFT 24\n#define I40E_PFINT_ICR0_STORM_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_STORM_DETECT_SHIFT)\n#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25\n#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT)\n#define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26\n#define I40E_PFINT_ICR0_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_HMC_ERR_SHIFT)\n#define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28\n#define I40E_PFINT_ICR0_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PE_CRITERR_SHIFT)\n#define I40E_PFINT_ICR0_VFLR_SHIFT 29\n#define I40E_PFINT_ICR0_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_VFLR_SHIFT)\n#define I40E_PFINT_ICR0_ADMINQ_SHIFT 30\n#define I40E_PFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ADMINQ_SHIFT)\n#define I40E_PFINT_ICR0_SWINT_SHIFT 31\n#define I40E_PFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_SWINT_SHIFT)\n#define I40E_PFINT_ICR0_ENA 0x00038800 /* Reset: CORER */\n#define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16\n#define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT)\n#define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19\n#define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT)\n#define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20\n#define I40E_PFINT_ICR0_ENA_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GRST_SHIFT)\n#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21\n#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT)\n#define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22\n#define I40E_PFINT_ICR0_ENA_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GPIO_SHIFT)\n#define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23\n#define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT)\n#define I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT 24\n#define I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT)\n#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25\n#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)\n#define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26\n#define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT)\n#define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28\n#define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT)\n#define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29\n#define I40E_PFINT_ICR0_ENA_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_VFLR_SHIFT)\n#define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30\n#define I40E_PFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT)\n#define I40E_PFINT_ICR0_ENA_RSVD_SHIFT 31\n#define I40E_PFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_RSVD_SHIFT)\n#define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */\n#define I40E_PFINT_ITR0_MAX_INDEX 2\n#define I40E_PFINT_ITR0_INTERVAL_SHIFT 0\n#define I40E_PFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITR0_INTERVAL_SHIFT)\n#define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */\n#define I40E_PFINT_ITRN_MAX_INDEX 2\n#define I40E_PFINT_ITRN_INTERVAL_SHIFT 0\n#define I40E_PFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITRN_INTERVAL_SHIFT)\n#define I40E_PFINT_LNKLST0 0x00038500 /* Reset: PFR */\n#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0\n#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT)\n#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11\n#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT)\n#define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */\n#define I40E_PFINT_LNKLSTN_MAX_INDEX 511\n#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0\n#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT)\n#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11\n#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)\n#define I40E_PFINT_RATE0 0x00038580 /* Reset: PFR */\n#define I40E_PFINT_RATE0_INTERVAL_SHIFT 0\n#define I40E_PFINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATE0_INTERVAL_SHIFT)\n#define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6\n#define I40E_PFINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATE0_INTRL_ENA_SHIFT)\n#define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */\n#define I40E_PFINT_RATEN_MAX_INDEX 511\n#define I40E_PFINT_RATEN_INTERVAL_SHIFT 0\n#define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT)\n#define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6\n#define I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT)\n#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */\n#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2\n#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)\n#define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */\n#define I40E_QINT_RQCTL_MAX_INDEX 1535\n#define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0\n#define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT)\n#define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11\n#define I40E_QINT_RQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT)\n#define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13\n#define I40E_QINT_RQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_RQCTL_MSIX0_INDX_SHIFT)\n#define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16\n#define I40E_QINT_RQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)\n#define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27\n#define I40E_QINT_RQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)\n#define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30\n#define I40E_QINT_RQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT)\n#define I40E_QINT_RQCTL_INTEVENT_SHIFT 31\n#define I40E_QINT_RQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT)\n#define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */\n#define I40E_QINT_TQCTL_MAX_INDEX 1535\n#define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0\n#define I40E_QINT_TQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT)\n#define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11\n#define I40E_QINT_TQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_ITR_INDX_SHIFT)\n#define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13\n#define I40E_QINT_TQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_TQCTL_MSIX0_INDX_SHIFT)\n#define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16\n#define I40E_QINT_TQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)\n#define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27\n#define I40E_QINT_TQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)\n#define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30\n#define I40E_QINT_TQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT)\n#define I40E_QINT_TQCTL_INTEVENT_SHIFT 31\n#define I40E_QINT_TQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT)\n#define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */\n#define I40E_VFINT_DYN_CTL0_MAX_INDEX 127\n#define I40E_VFINT_DYN_CTL0_INTENA_SHIFT 0\n#define I40E_VFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_SHIFT)\n#define I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT 1\n#define I40E_VFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT)\n#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2\n#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT)\n#define I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT 3\n#define I40E_VFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)\n#define I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT 5\n#define I40E_VFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT)\n#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24\n#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)\n#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25\n#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)\n#define I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT 31\n#define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT)\n#define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */\n#define I40E_VFINT_DYN_CTLN_MAX_INDEX 511\n#define I40E_VFINT_DYN_CTLN_INTENA_SHIFT 0\n#define I40E_VFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_SHIFT)\n#define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1\n#define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT)\n#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2\n#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT)\n#define I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT 3\n#define I40E_VFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT)\n#define I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT 5\n#define I40E_VFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT)\n#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24\n#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)\n#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25\n#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)\n#define I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT 31\n#define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT)\n#define I40E_VFINT_ICR0(_VF) (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_VFINT_ICR0_MAX_INDEX 127\n#define I40E_VFINT_ICR0_INTEVENT_SHIFT 0\n#define I40E_VFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_INTEVENT_SHIFT)\n#define I40E_VFINT_ICR0_QUEUE_0_SHIFT 1\n#define I40E_VFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_0_SHIFT)\n#define I40E_VFINT_ICR0_QUEUE_1_SHIFT 2\n#define I40E_VFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_1_SHIFT)\n#define I40E_VFINT_ICR0_QUEUE_2_SHIFT 3\n#define I40E_VFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_2_SHIFT)\n#define I40E_VFINT_ICR0_QUEUE_3_SHIFT 4\n#define I40E_VFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_3_SHIFT)\n#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25\n#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT)\n#define I40E_VFINT_ICR0_ADMINQ_SHIFT 30\n#define I40E_VFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ADMINQ_SHIFT)\n#define I40E_VFINT_ICR0_SWINT_SHIFT 31\n#define I40E_VFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_SWINT_SHIFT)\n#define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_VFINT_ICR0_ENA_MAX_INDEX 127\n#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25\n#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)\n#define I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT 30\n#define I40E_VFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT)\n#define I40E_VFINT_ICR0_ENA_RSVD_SHIFT 31\n#define I40E_VFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_RSVD_SHIFT)\n#define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ /* Reset: VFR */\n#define I40E_VFINT_ITR0_MAX_INDEX 2\n#define I40E_VFINT_ITR0_INTERVAL_SHIFT 0\n#define I40E_VFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR0_INTERVAL_SHIFT)\n#define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */ /* Reset: VFR */\n#define I40E_VFINT_ITRN_MAX_INDEX 2\n#define I40E_VFINT_ITRN_INTERVAL_SHIFT 0\n#define I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT)\n#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_VFINT_STAT_CTL0_MAX_INDEX 127\n#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2\n#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)\n#define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_VPINT_AEQCTL_MAX_INDEX 127\n#define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0\n#define I40E_VPINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT)\n#define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11\n#define I40E_VPINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_AEQCTL_ITR_INDX_SHIFT)\n#define I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT 13\n#define I40E_VPINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT)\n#define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30\n#define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT)\n#define I40E_VPINT_AEQCTL_INTEVENT_SHIFT 31\n#define I40E_VPINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_INTEVENT_SHIFT)\n#define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */\n#define I40E_VPINT_CEQCTL_MAX_INDEX 511\n#define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0\n#define I40E_VPINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT)\n#define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11\n#define I40E_VPINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_ITR_INDX_SHIFT)\n#define I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT 13\n#define I40E_VPINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT)\n#define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16\n#define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT)\n#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27\n#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT)\n#define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30\n#define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT)\n#define I40E_VPINT_CEQCTL_INTEVENT_SHIFT 31\n#define I40E_VPINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_INTEVENT_SHIFT)\n#define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */\n#define I40E_VPINT_LNKLST0_MAX_INDEX 127\n#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0\n#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT)\n#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11\n#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)\n#define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */\n#define I40E_VPINT_LNKLSTN_MAX_INDEX 511\n#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0\n#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT)\n#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11\n#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)\n#define I40E_VPINT_RATE0(_VF) (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */\n#define I40E_VPINT_RATE0_MAX_INDEX 127\n#define I40E_VPINT_RATE0_INTERVAL_SHIFT 0\n#define I40E_VPINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATE0_INTERVAL_SHIFT)\n#define I40E_VPINT_RATE0_INTRL_ENA_SHIFT 6\n#define I40E_VPINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_VPINT_RATE0_INTRL_ENA_SHIFT)\n#define I40E_VPINT_RATEN(_INTVF) (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */\n#define I40E_VPINT_RATEN_MAX_INDEX 511\n#define I40E_VPINT_RATEN_INTERVAL_SHIFT 0\n#define I40E_VPINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATEN_INTERVAL_SHIFT)\n#define I40E_VPINT_RATEN_INTRL_ENA_SHIFT 6\n#define I40E_VPINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_VPINT_RATEN_INTRL_ENA_SHIFT)\n#define I40E_GL_RDPU_CNTRL 0x00051060 /* Reset: CORER */\n#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT 0\n#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK I40E_MASK(0x1, I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT)\n#define I40E_GL_RDPU_CNTRL_ECO_SHIFT 1\n#define I40E_GL_RDPU_CNTRL_ECO_MASK I40E_MASK(0x7FFFFFFF, I40E_GL_RDPU_CNTRL_ECO_SHIFT)\n#define I40E_GLLAN_RCTL_0 0x0012A500 /* Reset: CORER */\n#define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0\n#define I40E_GLLAN_RCTL_0_PXE_MODE_MASK I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT)\n#define I40E_GLLAN_TSOMSK_F 0x000442D8 /* Reset: CORER */\n#define I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT 0\n#define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT)\n#define I40E_GLLAN_TSOMSK_L 0x000442E0 /* Reset: CORER */\n#define I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT 0\n#define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT)\n#define I40E_GLLAN_TSOMSK_M 0x000442DC /* Reset: CORER */\n#define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0\n#define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT)\n#define I40E_GLLAN_TXPRE_QDIS(_i) (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */\n#define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX 11\n#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0\n#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT)\n#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT 16\n#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT)\n#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30\n#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)\n#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31\n#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)\n#define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */\n#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0\n#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)\n#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16\n#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)\n#define I40E_PFLAN_QALLOC_VALID_SHIFT 31\n#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT)\n#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */\n#define I40E_QRX_ENA_MAX_INDEX 1535\n#define I40E_QRX_ENA_QENA_REQ_SHIFT 0\n#define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT)\n#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1\n#define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT)\n#define I40E_QRX_ENA_QENA_STAT_SHIFT 2\n#define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT)\n#define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */\n#define I40E_QRX_TAIL_MAX_INDEX 1535\n#define I40E_QRX_TAIL_TAIL_SHIFT 0\n#define I40E_QRX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL_TAIL_SHIFT)\n#define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */\n#define I40E_QTX_CTL_MAX_INDEX 1535\n#define I40E_QTX_CTL_PFVF_Q_SHIFT 0\n#define I40E_QTX_CTL_PFVF_Q_MASK I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT)\n#define I40E_QTX_CTL_PF_INDX_SHIFT 2\n#define I40E_QTX_CTL_PF_INDX_MASK I40E_MASK(0xF, I40E_QTX_CTL_PF_INDX_SHIFT)\n#define I40E_QTX_CTL_VFVM_INDX_SHIFT 7\n#define I40E_QTX_CTL_VFVM_INDX_MASK I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT)\n#define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */\n#define I40E_QTX_ENA_MAX_INDEX 1535\n#define I40E_QTX_ENA_QENA_REQ_SHIFT 0\n#define I40E_QTX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT)\n#define I40E_QTX_ENA_FAST_QDIS_SHIFT 1\n#define I40E_QTX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QTX_ENA_FAST_QDIS_SHIFT)\n#define I40E_QTX_ENA_QENA_STAT_SHIFT 2\n#define I40E_QTX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT)\n#define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */\n#define I40E_QTX_HEAD_MAX_INDEX 1535\n#define I40E_QTX_HEAD_HEAD_SHIFT 0\n#define I40E_QTX_HEAD_HEAD_MASK I40E_MASK(0x1FFF, I40E_QTX_HEAD_HEAD_SHIFT)\n#define I40E_QTX_HEAD_RS_PENDING_SHIFT 16\n#define I40E_QTX_HEAD_RS_PENDING_MASK I40E_MASK(0x1, I40E_QTX_HEAD_RS_PENDING_SHIFT)\n#define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */\n#define I40E_QTX_TAIL_MAX_INDEX 1535\n#define I40E_QTX_TAIL_TAIL_SHIFT 0\n#define I40E_QTX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL_TAIL_SHIFT)\n#define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */\n#define I40E_VPLAN_MAPENA_MAX_INDEX 127\n#define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0\n#define I40E_VPLAN_MAPENA_TXRX_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT)\n#define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */\n#define I40E_VPLAN_QTABLE_MAX_INDEX 15\n#define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0\n#define I40E_VPLAN_QTABLE_QINDEX_MASK I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT)\n#define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */\n#define I40E_VSILAN_QBASE_MAX_INDEX 383\n#define I40E_VSILAN_QBASE_VSIBASE_SHIFT 0\n#define I40E_VSILAN_QBASE_VSIBASE_MASK I40E_MASK(0x7FF, I40E_VSILAN_QBASE_VSIBASE_SHIFT)\n#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11\n#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT)\n#define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */\n#define I40E_VSILAN_QTABLE_MAX_INDEX 7\n#define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0\n#define I40E_VSILAN_QTABLE_QINDEX_0_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_0_SHIFT)\n#define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16\n#define I40E_VSILAN_QTABLE_QINDEX_1_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_1_SHIFT)\n#define I40E_PRTGL_SAH 0x001E2140 /* Reset: GLOBR */\n#define I40E_PRTGL_SAH_FC_SAH_SHIFT 0\n#define I40E_PRTGL_SAH_FC_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT)\n#define I40E_PRTGL_SAH_MFS_SHIFT 16\n#define I40E_PRTGL_SAH_MFS_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_MFS_SHIFT)\n#define I40E_PRTGL_SAL 0x001E2120 /* Reset: GLOBR */\n#define I40E_PRTGL_SAL_FC_SAL_SHIFT 0\n#define I40E_PRTGL_SAL_FC_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E30E0 /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E3360 /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3110 /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3120 /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3140 /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E3150 /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0 /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E3370 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8\n#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8\n#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E34B0 /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT)\n#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E34C0 /* Reset: GLOBR */\n#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT 0\n#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A 0x0008C480 /* Reset: GLOBR */\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT 0\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT 2\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT 4\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT 6\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT 8\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT 10\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT 12\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT 14\n#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B 0x0008C484 /* Reset: GLOBR */\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT 0\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT 2\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT 4\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT 6\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT 8\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT 10\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT 12\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT)\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14\n#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT)\n#define I40E_GL_FWRESETCNT 0x00083100 /* Reset: POR */\n#define I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT 0\n#define I40E_GL_FWRESETCNT_FWRESETCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT)\n#define I40E_GL_MNG_FWSM 0x000B6134 /* Reset: POR */\n#define I40E_GL_MNG_FWSM_FW_MODES_SHIFT 0\n#define I40E_GL_MNG_FWSM_FW_MODES_MASK I40E_MASK(0x3, I40E_GL_MNG_FWSM_FW_MODES_SHIFT)\n#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT 10\n#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT)\n#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT 11\n#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK I40E_MASK(0xF, I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT)\n#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT 15\n#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT)\n#define I40E_GL_MNG_FWSM_RESET_CNT_SHIFT 16\n#define I40E_GL_MNG_FWSM_RESET_CNT_MASK I40E_MASK(0x7, I40E_GL_MNG_FWSM_RESET_CNT_SHIFT)\n#define I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT 19\n#define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK I40E_MASK(0x3F, I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT)\n#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT 26\n#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT)\n#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT 27\n#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT)\n#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT 28\n#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT)\n#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT 29\n#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT)\n#define I40E_GL_MNG_HWARB_CTRL 0x000B6130 /* Reset: POR */\n#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT 0\n#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK I40E_MASK(0x1, I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT)\n#define I40E_PRT_MNG_FTFT_DATA(_i) (0x000852A0 + ((_i) * 32)) /* _i=0...31 */ /* Reset: POR */\n#define I40E_PRT_MNG_FTFT_DATA_MAX_INDEX 31\n#define I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT 0\n#define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT)\n#define I40E_PRT_MNG_FTFT_LENGTH 0x00085260 /* Reset: POR */\n#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT 0\n#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT)\n#define I40E_PRT_MNG_FTFT_MASK(_i) (0x00085160 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */\n#define I40E_PRT_MNG_FTFT_MASK_MAX_INDEX 7\n#define I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT 0\n#define I40E_PRT_MNG_FTFT_MASK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT)\n#define I40E_PRT_MNG_MANC 0x00256A20 /* Reset: POR */\n#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT 0\n#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT)\n#define I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT 1\n#define I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT)\n#define I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT 17\n#define I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT)\n#define I40E_PRT_MNG_MANC_RCV_ALL_SHIFT 19\n#define I40E_PRT_MNG_MANC_RCV_ALL_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_ALL_SHIFT)\n#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT 25\n#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT)\n#define I40E_PRT_MNG_MANC_NET_TYPE_SHIFT 26\n#define I40E_PRT_MNG_MANC_NET_TYPE_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_NET_TYPE_SHIFT)\n#define I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT 28\n#define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT)\n#define I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT 29\n#define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT)\n#define I40E_PRT_MNG_MAVTV(_i) (0x00255900 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */\n#define I40E_PRT_MNG_MAVTV_MAX_INDEX 7\n#define I40E_PRT_MNG_MAVTV_VID_SHIFT 0\n#define I40E_PRT_MNG_MAVTV_VID_MASK I40E_MASK(0xFFF, I40E_PRT_MNG_MAVTV_VID_SHIFT)\n#define I40E_PRT_MNG_MDEF(_i) (0x00255D00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */\n#define I40E_PRT_MNG_MDEF_MAX_INDEX 7\n#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT 0\n#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT)\n#define I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT 4\n#define I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT)\n#define I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT 5\n#define I40E_PRT_MNG_MDEF_VLAN_AND_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT)\n#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT 13\n#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT)\n#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT 17\n#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT)\n#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT 21\n#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT 25\n#define I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT 26\n#define I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT)\n#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT 27\n#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT 28\n#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT 29\n#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT 30\n#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT 31\n#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_EXT(_i) (0x00255F00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */\n#define I40E_PRT_MNG_MDEF_EXT_MAX_INDEX 7\n#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT 0\n#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT)\n#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT 4\n#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT 8\n#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT 24\n#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT)\n#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT 25\n#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT 26\n#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT 27\n#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT 28\n#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT)\n#define I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT 29\n#define I40E_PRT_MNG_MDEF_EXT_MLD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT)\n#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT 30\n#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT)\n#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT 31\n#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT)\n#define I40E_PRT_MNG_MDEFVSI(_i) (0x00256580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */\n#define I40E_PRT_MNG_MDEFVSI_MAX_INDEX 3\n#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT 0\n#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT)\n#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16\n#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT)\n#define I40E_PRT_MNG_METF(_i) (0x00256780 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */\n#define I40E_PRT_MNG_METF_MAX_INDEX 3\n#define I40E_PRT_MNG_METF_ETYPE_SHIFT 0\n#define I40E_PRT_MNG_METF_ETYPE_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_METF_ETYPE_SHIFT)\n#define I40E_PRT_MNG_METF_POLARITY_SHIFT 30\n#define I40E_PRT_MNG_METF_POLARITY_MASK I40E_MASK(0x1, I40E_PRT_MNG_METF_POLARITY_SHIFT)\n#define I40E_PRT_MNG_MFUTP(_i) (0x00254E00 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */\n#define I40E_PRT_MNG_MFUTP_MAX_INDEX 15\n#define I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT 0\n#define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT)\n#define I40E_PRT_MNG_MFUTP_UDP_SHIFT 16\n#define I40E_PRT_MNG_MFUTP_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_UDP_SHIFT)\n#define I40E_PRT_MNG_MFUTP_TCP_SHIFT 17\n#define I40E_PRT_MNG_MFUTP_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_TCP_SHIFT)\n#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT 18\n#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT)\n#define I40E_PRT_MNG_MIPAF4(_i) (0x00256280 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */\n#define I40E_PRT_MNG_MIPAF4_MAX_INDEX 3\n#define I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT 0\n#define I40E_PRT_MNG_MIPAF4_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT)\n#define I40E_PRT_MNG_MIPAF6(_i) (0x00254200 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */\n#define I40E_PRT_MNG_MIPAF6_MAX_INDEX 15\n#define I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT 0\n#define I40E_PRT_MNG_MIPAF6_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT)\n#define I40E_PRT_MNG_MMAH(_i) (0x00256380 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */\n#define I40E_PRT_MNG_MMAH_MAX_INDEX 3\n#define I40E_PRT_MNG_MMAH_MMAH_SHIFT 0\n#define I40E_PRT_MNG_MMAH_MMAH_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MMAH_MMAH_SHIFT)\n#define I40E_PRT_MNG_MMAL(_i) (0x00256480 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */\n#define I40E_PRT_MNG_MMAL_MAX_INDEX 3\n#define I40E_PRT_MNG_MMAL_MMAL_SHIFT 0\n#define I40E_PRT_MNG_MMAL_MMAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MMAL_MMAL_SHIFT)\n#define I40E_PRT_MNG_MNGONLY 0x00256A60 /* Reset: POR */\n#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT 0\n#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT)\n#define I40E_PRT_MNG_MSFM 0x00256AA0 /* Reset: POR */\n#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT 0\n#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT)\n#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT 1\n#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT)\n#define I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT 2\n#define I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT)\n#define I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT 3\n#define I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT)\n#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT 4\n#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT)\n#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT 5\n#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT)\n#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT 6\n#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT)\n#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT 7\n#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT)\n#define I40E_MSIX_PBA(_i) (0x00001000 + ((_i) * 4)) /* _i=0...5 */ /* Reset: FLR */\n#define I40E_MSIX_PBA_MAX_INDEX 5\n#define I40E_MSIX_PBA_PENBIT_SHIFT 0\n#define I40E_MSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_PBA_PENBIT_SHIFT)\n#define I40E_MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */\n#define I40E_MSIX_TADD_MAX_INDEX 128\n#define I40E_MSIX_TADD_MSIXTADD10_SHIFT 0\n#define I40E_MSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_MSIX_TADD_MSIXTADD10_SHIFT)\n#define I40E_MSIX_TADD_MSIXTADD_SHIFT 2\n#define I40E_MSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_MSIX_TADD_MSIXTADD_SHIFT)\n#define I40E_MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */\n#define I40E_MSIX_TMSG_MAX_INDEX 128\n#define I40E_MSIX_TMSG_MSIXTMSG_SHIFT 0\n#define I40E_MSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TMSG_MSIXTMSG_SHIFT)\n#define I40E_MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */\n#define I40E_MSIX_TUADD_MAX_INDEX 128\n#define I40E_MSIX_TUADD_MSIXTUADD_SHIFT 0\n#define I40E_MSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TUADD_MSIXTUADD_SHIFT)\n#define I40E_MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */\n#define I40E_MSIX_TVCTRL_MAX_INDEX 128\n#define I40E_MSIX_TVCTRL_MASK_SHIFT 0\n#define I40E_MSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_MSIX_TVCTRL_MASK_SHIFT)\n#define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */\n#define I40E_VFMSIX_PBA1_MAX_INDEX 19\n#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0\n#define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT)\n#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */\n#define I40E_VFMSIX_TADD1_MAX_INDEX 639\n#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0\n#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT)\n#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2\n#define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT)\n#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */\n#define I40E_VFMSIX_TMSG1_MAX_INDEX 639\n#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0\n#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT)\n#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */\n#define I40E_VFMSIX_TUADD1_MAX_INDEX 639\n#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0\n#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT)\n#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */\n#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639\n#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0\n#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT)\n#define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */\n#define I40E_GLNVM_FLA_FL_SCK_SHIFT 0\n#define I40E_GLNVM_FLA_FL_SCK_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SCK_SHIFT)\n#define I40E_GLNVM_FLA_FL_CE_SHIFT 1\n#define I40E_GLNVM_FLA_FL_CE_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_CE_SHIFT)\n#define I40E_GLNVM_FLA_FL_SI_SHIFT 2\n#define I40E_GLNVM_FLA_FL_SI_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SI_SHIFT)\n#define I40E_GLNVM_FLA_FL_SO_SHIFT 3\n#define I40E_GLNVM_FLA_FL_SO_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SO_SHIFT)\n#define I40E_GLNVM_FLA_FL_REQ_SHIFT 4\n#define I40E_GLNVM_FLA_FL_REQ_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_REQ_SHIFT)\n#define I40E_GLNVM_FLA_FL_GNT_SHIFT 5\n#define I40E_GLNVM_FLA_FL_GNT_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_GNT_SHIFT)\n#define I40E_GLNVM_FLA_LOCKED_SHIFT 6\n#define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT)\n#define I40E_GLNVM_FLA_FL_SADDR_SHIFT 18\n#define I40E_GLNVM_FLA_FL_SADDR_MASK I40E_MASK(0x7FF, I40E_GLNVM_FLA_FL_SADDR_SHIFT)\n#define I40E_GLNVM_FLA_FL_BUSY_SHIFT 30\n#define I40E_GLNVM_FLA_FL_BUSY_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_BUSY_SHIFT)\n#define I40E_GLNVM_FLA_FL_DER_SHIFT 31\n#define I40E_GLNVM_FLA_FL_DER_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_DER_SHIFT)\n#define I40E_GLNVM_FLASHID 0x000B6104 /* Reset: POR */\n#define I40E_GLNVM_FLASHID_FLASHID_SHIFT 0\n#define I40E_GLNVM_FLASHID_FLASHID_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_FLASHID_FLASHID_SHIFT)\n#define I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT 31\n#define I40E_GLNVM_FLASHID_FLEEP_PERF_MASK I40E_MASK(0x1, I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT)\n#define I40E_GLNVM_GENS 0x000B6100 /* Reset: POR */\n#define I40E_GLNVM_GENS_NVM_PRES_SHIFT 0\n#define I40E_GLNVM_GENS_NVM_PRES_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_NVM_PRES_SHIFT)\n#define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5\n#define I40E_GLNVM_GENS_SR_SIZE_MASK I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT)\n#define I40E_GLNVM_GENS_BANK1VAL_SHIFT 8\n#define I40E_GLNVM_GENS_BANK1VAL_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_BANK1VAL_SHIFT)\n#define I40E_GLNVM_GENS_ALT_PRST_SHIFT 23\n#define I40E_GLNVM_GENS_ALT_PRST_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_ALT_PRST_SHIFT)\n#define I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT 25\n#define I40E_GLNVM_GENS_FL_AUTO_RD_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT)\n#define I40E_GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset: POR */\n#define I40E_GLNVM_PROTCSR_MAX_INDEX 59\n#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT 0\n#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT)\n#define I40E_GLNVM_SRCTL 0x000B6110 /* Reset: POR */\n#define I40E_GLNVM_SRCTL_SRBUSY_SHIFT 0\n#define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT)\n#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14\n#define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT)\n#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29\n#define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT)\n#define I40E_GLNVM_SRCTL_START_SHIFT 30\n#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT)\n#define I40E_GLNVM_SRCTL_DONE_SHIFT 31\n#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT)\n#define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */\n#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0\n#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)\n#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16\n#define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT)\n#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */\n#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0\n#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT)\n#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT 1\n#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT)\n#define I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT 2\n#define I40E_GLNVM_ULD_CONF_LCB_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT)\n#define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3\n#define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT)\n#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4\n#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT)\n#define I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT 5\n#define I40E_GLNVM_ULD_CONF_POR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT)\n#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT 6\n#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT)\n#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT 7\n#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT)\n#define I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT 8\n#define I40E_GLNVM_ULD_CONF_EMP_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT)\n#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT 9\n#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT)\n#define I40E_GLPCI_BYTCTH 0x0009C484 /* Reset: PCIR */\n#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT 0\n#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT)\n#define I40E_GLPCI_BYTCTL 0x0009C488 /* Reset: PCIR */\n#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT 0\n#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT)\n#define I40E_GLPCI_CAPCTRL 0x000BE4A4 /* Reset: PCIR */\n#define I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT 0\n#define I40E_GLPCI_CAPCTRL_VPD_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT)\n#define I40E_GLPCI_CAPSUP 0x000BE4A8 /* Reset: PCIR */\n#define I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT 0\n#define I40E_GLPCI_CAPSUP_PCIE_VER_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT)\n#define I40E_GLPCI_CAPSUP_LTR_EN_SHIFT 2\n#define I40E_GLPCI_CAPSUP_LTR_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LTR_EN_SHIFT)\n#define I40E_GLPCI_CAPSUP_TPH_EN_SHIFT 3\n#define I40E_GLPCI_CAPSUP_TPH_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_TPH_EN_SHIFT)\n#define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4\n#define I40E_GLPCI_CAPSUP_ARI_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT)\n#define I40E_GLPCI_CAPSUP_IOV_EN_SHIFT 5\n#define I40E_GLPCI_CAPSUP_IOV_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IOV_EN_SHIFT)\n#define I40E_GLPCI_CAPSUP_ACS_EN_SHIFT 6\n#define I40E_GLPCI_CAPSUP_ACS_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ACS_EN_SHIFT)\n#define I40E_GLPCI_CAPSUP_SEC_EN_SHIFT 7\n#define I40E_GLPCI_CAPSUP_SEC_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_SEC_EN_SHIFT)\n#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT 16\n#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT)\n#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT 17\n#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT)\n#define I40E_GLPCI_CAPSUP_IDO_EN_SHIFT 18\n#define I40E_GLPCI_CAPSUP_IDO_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IDO_EN_SHIFT)\n#define I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT 19\n#define I40E_GLPCI_CAPSUP_MSI_MASK_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT)\n#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT 20\n#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT)\n#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT 30\n#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT)\n#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT 31\n#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT)\n#define I40E_GLPCI_CNF 0x000BE4C0 /* Reset: POR */\n#define I40E_GLPCI_CNF_FLEX10_SHIFT 1\n#define I40E_GLPCI_CNF_FLEX10_MASK I40E_MASK(0x1, I40E_GLPCI_CNF_FLEX10_SHIFT)\n#define I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT 2\n#define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT)\n#define I40E_GLPCI_CNF2 0x000BE494 /* Reset: PCIR */\n#define I40E_GLPCI_CNF2_RO_DIS_SHIFT 0\n#define I40E_GLPCI_CNF2_RO_DIS_MASK I40E_MASK(0x1, I40E_GLPCI_CNF2_RO_DIS_SHIFT)\n#define I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT 1\n#define I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK I40E_MASK(0x1, I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT)\n#define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2\n#define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT)\n#define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13\n#define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT)\n#define I40E_GLPCI_DREVID 0x0009C480 /* Reset: PCIR */\n#define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0\n#define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT)\n#define I40E_GLPCI_GSCL_1 0x0009C48C /* Reset: PCIR */\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT 0\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT)\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT 1\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT)\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT 2\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT)\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT 3\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT)\n#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT 4\n#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT)\n#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT 5\n#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT)\n#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT 6\n#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT)\n#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT 7\n#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT)\n#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT 8\n#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT)\n#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT 9\n#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT)\n#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT 14\n#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT)\n#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT 15\n#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT)\n#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT 28\n#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT)\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT 29\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT)\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT 30\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT)\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT 31\n#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT)\n#define I40E_GLPCI_GSCL_2 0x0009C490 /* Reset: PCIR */\n#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT 0\n#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT)\n#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT 8\n#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT)\n#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT 16\n#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT)\n#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT 24\n#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT)\n#define I40E_GLPCI_GSCL_5_8(_i) (0x0009C494 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */\n#define I40E_GLPCI_GSCL_5_8_MAX_INDEX 3\n#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0\n#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT)\n#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT 16\n#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT)\n#define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */\n#define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3\n#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0\n#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT)\n#define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */\n#define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0\n#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT)\n#define I40E_GLPCI_LBARCTRL_BAR32_SHIFT 1\n#define I40E_GLPCI_LBARCTRL_BAR32_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_BAR32_SHIFT)\n#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3\n#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT)\n#define I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT 4\n#define I40E_GLPCI_LBARCTRL_RSVD_4_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT)\n#define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6\n#define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT)\n#define I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT 10\n#define I40E_GLPCI_LBARCTRL_RSVD_10_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT)\n#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT 11\n#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT)\n#define I40E_GLPCI_LINKCAP 0x000BE4AC /* Reset: PCIR */\n#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT 0\n#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK I40E_MASK(0x3F, I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT)\n#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT 6\n#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK I40E_MASK(0x7, I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT)\n#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT 9\n#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK I40E_MASK(0xF, I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT)\n#define I40E_GLPCI_PCIERR 0x000BE4FC /* Reset: PCIR */\n#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0\n#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT)\n#define I40E_GLPCI_PKTCT 0x0009C4BC /* Reset: PCIR */\n#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0\n#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT)\n#define I40E_GLPCI_PM_MUX_NPQ 0x0009C4F4 /* Reset: PCIR */\n#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0\n#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT)\n#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT 16\n#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT)\n#define I40E_GLPCI_PM_MUX_PFB 0x0009C4F0 /* Reset: PCIR */\n#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT 0\n#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT)\n#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16\n#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT)\n#define I40E_GLPCI_PMSUP 0x000BE4B0 /* Reset: PCIR */\n#define I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT 0\n#define I40E_GLPCI_PMSUP_ASPM_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT)\n#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT 2\n#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT)\n#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT 5\n#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT)\n#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT 8\n#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT)\n#define I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT 11\n#define I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT)\n#define I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT 14\n#define I40E_GLPCI_PMSUP_SLOT_CLK_MASK I40E_MASK(0x1, I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT)\n#define I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT 15\n#define I40E_GLPCI_PMSUP_OBFF_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT)\n#define I40E_GLPCI_PQ_MAX_USED_SPC 0x0009C4EC /* Reset: PCIR */\n#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT 0\n#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT)\n#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT 8\n#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT)\n#define I40E_GLPCI_PWRDATA 0x000BE490 /* Reset: PCIR */\n#define I40E_GLPCI_PWRDATA_D0_POWER_SHIFT 0\n#define I40E_GLPCI_PWRDATA_D0_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D0_POWER_SHIFT)\n#define I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT 8\n#define I40E_GLPCI_PWRDATA_COMM_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT)\n#define I40E_GLPCI_PWRDATA_D3_POWER_SHIFT 16\n#define I40E_GLPCI_PWRDATA_D3_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D3_POWER_SHIFT)\n#define I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT 24\n#define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK I40E_MASK(0x3, I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT)\n#define I40E_GLPCI_REVID 0x000BE4B4 /* Reset: PCIR */\n#define I40E_GLPCI_REVID_NVM_REVID_SHIFT 0\n#define I40E_GLPCI_REVID_NVM_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_REVID_NVM_REVID_SHIFT)\n#define I40E_GLPCI_SERH 0x000BE49C /* Reset: PCIR */\n#define I40E_GLPCI_SERH_SER_NUM_H_SHIFT 0\n#define I40E_GLPCI_SERH_SER_NUM_H_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SERH_SER_NUM_H_SHIFT)\n#define I40E_GLPCI_SERL 0x000BE498 /* Reset: PCIR */\n#define I40E_GLPCI_SERL_SER_NUM_L_SHIFT 0\n#define I40E_GLPCI_SERL_SER_NUM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SERL_SER_NUM_L_SHIFT)\n#define I40E_GLPCI_SPARE_BITS_0 0x0009C4F8 /* Reset: PCIR */\n#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0\n#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT)\n#define I40E_GLPCI_SPARE_BITS_1 0x0009C4FC /* Reset: PCIR */\n#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT 0\n#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT)\n#define I40E_GLPCI_SUBVENID 0x000BE48C /* Reset: PCIR */\n#define I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT 0\n#define I40E_GLPCI_SUBVENID_SUB_VEN_ID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT)\n#define I40E_GLPCI_UPADD 0x000BE4F8 /* Reset: PCIR */\n#define I40E_GLPCI_UPADD_ADDRESS_SHIFT 1\n#define I40E_GLPCI_UPADD_ADDRESS_MASK I40E_MASK(0x7FFFFFFF, I40E_GLPCI_UPADD_ADDRESS_SHIFT)\n#define I40E_GLPCI_VENDORID 0x000BE518 /* Reset: PCIR */\n#define I40E_GLPCI_VENDORID_VENDORID_SHIFT 0\n#define I40E_GLPCI_VENDORID_VENDORID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_VENDORID_VENDORID_SHIFT)\n#define I40E_GLPCI_VFSUP 0x000BE4B8 /* Reset: PCIR */\n#define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0\n#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT)\n#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1\n#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT)\n#define I40E_GLTPH_CTRL 0x000BE480 /* Reset: PCIR */\n#define I40E_GLTPH_CTRL_DESC_PH_SHIFT 9\n#define I40E_GLTPH_CTRL_DESC_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DESC_PH_SHIFT)\n#define I40E_GLTPH_CTRL_DATA_PH_SHIFT 11\n#define I40E_GLTPH_CTRL_DATA_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DATA_PH_SHIFT)\n#define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */\n#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0\n#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT)\n#define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT 3\n#define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK I40E_MASK(0x1F, I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT)\n#define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT 8\n#define I40E_PF_FUNC_RID_BUS_NUMBER_MASK I40E_MASK(0xFF, I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT)\n#define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */\n#define I40E_PF_PCI_CIAA_ADDRESS_SHIFT 0\n#define I40E_PF_PCI_CIAA_ADDRESS_MASK I40E_MASK(0xFFF, I40E_PF_PCI_CIAA_ADDRESS_SHIFT)\n#define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12\n#define I40E_PF_PCI_CIAA_VF_NUM_MASK I40E_MASK(0x7F, I40E_PF_PCI_CIAA_VF_NUM_SHIFT)\n#define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */\n#define I40E_PF_PCI_CIAD_DATA_SHIFT 0\n#define I40E_PF_PCI_CIAD_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_PCI_CIAD_DATA_SHIFT)\n#define I40E_PFPCI_CLASS 0x000BE400 /* Reset: PCIR */\n#define I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT 0\n#define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT)\n#define I40E_PFPCI_CLASS_RESERVED_1_SHIFT 1\n#define I40E_PFPCI_CLASS_RESERVED_1_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_RESERVED_1_SHIFT)\n#define I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT 2\n#define I40E_PFPCI_CLASS_PF_IS_LAN_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT)\n#define I40E_PFPCI_CNF 0x000BE000 /* Reset: PCIR */\n#define I40E_PFPCI_CNF_MSI_EN_SHIFT 2\n#define I40E_PFPCI_CNF_MSI_EN_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_MSI_EN_SHIFT)\n#define I40E_PFPCI_CNF_EXROM_DIS_SHIFT 3\n#define I40E_PFPCI_CNF_EXROM_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_EXROM_DIS_SHIFT)\n#define I40E_PFPCI_CNF_IO_BAR_SHIFT 4\n#define I40E_PFPCI_CNF_IO_BAR_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_IO_BAR_SHIFT)\n#define I40E_PFPCI_CNF_INT_PIN_SHIFT 5\n#define I40E_PFPCI_CNF_INT_PIN_MASK I40E_MASK(0x3, I40E_PFPCI_CNF_INT_PIN_SHIFT)\n#define I40E_PFPCI_DEVID 0x000BE080 /* Reset: PCIR */\n#define I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT 0\n#define I40E_PFPCI_DEVID_PF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT)\n#define I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT 16\n#define I40E_PFPCI_DEVID_VF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT)\n#define I40E_PFPCI_FACTPS 0x0009C180 /* Reset: FLR */\n#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0\n#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK I40E_MASK(0x3, I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT)\n#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT 3\n#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK I40E_MASK(0x1, I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT)\n#define I40E_PFPCI_FUNC 0x000BE200 /* Reset: POR */\n#define I40E_PFPCI_FUNC_FUNC_DIS_SHIFT 0\n#define I40E_PFPCI_FUNC_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_FUNC_DIS_SHIFT)\n#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT 1\n#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT)\n#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT 2\n#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT)\n#define I40E_PFPCI_FUNC2 0x000BE180 /* Reset: PCIR */\n#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT 0\n#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT)\n#define I40E_PFPCI_ICAUSE 0x0009C200 /* Reset: PFR */\n#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT 0\n#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT)\n#define I40E_PFPCI_IENA 0x0009C280 /* Reset: PFR */\n#define I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT 0\n#define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT)\n#define I40E_PFPCI_PF_FLUSH_DONE 0x0009C800 /* Reset: PCIR */\n#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT 0\n#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT)\n#define I40E_PFPCI_PM 0x000BE300 /* Reset: POR */\n#define I40E_PFPCI_PM_PME_EN_SHIFT 0\n#define I40E_PFPCI_PM_PME_EN_MASK I40E_MASK(0x1, I40E_PFPCI_PM_PME_EN_SHIFT)\n#define I40E_PFPCI_STATUS1 0x000BE280 /* Reset: POR */\n#define I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT 0\n#define I40E_PFPCI_STATUS1_FUNC_VALID_MASK I40E_MASK(0x1, I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT)\n#define I40E_PFPCI_SUBSYSID 0x000BE100 /* Reset: PCIR */\n#define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT 0\n#define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT)\n#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT 16\n#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT)\n#define I40E_PFPCI_VF_FLUSH_DONE 0x0000E400 /* Reset: PCIR */\n#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0\n#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT)\n#define I40E_PFPCI_VF_FLUSH_DONE1(_VF) (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: PCIR */\n#define I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX 127\n#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT 0\n#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT)\n#define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880 /* Reset: PCIR */\n#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0\n#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT)\n#define I40E_PFPCI_VMINDEX 0x0009C300 /* Reset: PCIR */\n#define I40E_PFPCI_VMINDEX_VMINDEX_SHIFT 0\n#define I40E_PFPCI_VMINDEX_VMINDEX_MASK I40E_MASK(0x1FF, I40E_PFPCI_VMINDEX_VMINDEX_SHIFT)\n#define I40E_PFPCI_VMPEND 0x0009C380 /* Reset: PCIR */\n#define I40E_PFPCI_VMPEND_PENDING_SHIFT 0\n#define I40E_PFPCI_VMPEND_PENDING_MASK I40E_MASK(0x1, I40E_PFPCI_VMPEND_PENDING_SHIFT)\n#define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */\n#define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT 29\n#define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT)\n#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30\n#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT)\n#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31\n#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT)\n#define I40E_PRTPM_EEEC 0x001E4380 /* Reset: GLOBR */\n#define I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT 16\n#define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT)\n#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT 24\n#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK I40E_MASK(0x3, I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT)\n#define I40E_PRTPM_EEEC_TEEE_DLY_SHIFT 26\n#define I40E_PRTPM_EEEC_TEEE_DLY_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TEEE_DLY_SHIFT)\n#define I40E_PRTPM_EEEFWD 0x001E4400 /* Reset: GLOBR */\n#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT 31\n#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK I40E_MASK(0x1, I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT)\n#define I40E_PRTPM_EEER 0x001E4360 /* Reset: GLOBR */\n#define I40E_PRTPM_EEER_TW_SYSTEM_SHIFT 0\n#define I40E_PRTPM_EEER_TW_SYSTEM_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEER_TW_SYSTEM_SHIFT)\n#define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16\n#define I40E_PRTPM_EEER_TX_LPI_EN_MASK I40E_MASK(0x1, I40E_PRTPM_EEER_TX_LPI_EN_SHIFT)\n#define I40E_PRTPM_EEETXC 0x001E43E0 /* Reset: GLOBR */\n#define I40E_PRTPM_EEETXC_TW_PHY_SHIFT 0\n#define I40E_PRTPM_EEETXC_TW_PHY_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEETXC_TW_PHY_SHIFT)\n#define I40E_PRTPM_GC 0x000B8140 /* Reset: POR */\n#define I40E_PRTPM_GC_EMP_LINK_ON_SHIFT 0\n#define I40E_PRTPM_GC_EMP_LINK_ON_MASK I40E_MASK(0x1, I40E_PRTPM_GC_EMP_LINK_ON_SHIFT)\n#define I40E_PRTPM_GC_MNG_VETO_SHIFT 1\n#define I40E_PRTPM_GC_MNG_VETO_MASK I40E_MASK(0x1, I40E_PRTPM_GC_MNG_VETO_SHIFT)\n#define I40E_PRTPM_GC_RATD_SHIFT 2\n#define I40E_PRTPM_GC_RATD_MASK I40E_MASK(0x1, I40E_PRTPM_GC_RATD_SHIFT)\n#define I40E_PRTPM_GC_LCDMP_SHIFT 3\n#define I40E_PRTPM_GC_LCDMP_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LCDMP_SHIFT)\n#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31\n#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT)\n#define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */\n#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0\n#define I40E_PRTPM_RLPIC_ERLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT)\n#define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */\n#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0\n#define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)\n#define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */\n#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0\n#define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT)\n#define I40E_GLRPB_GHW 0x000AC830 /* Reset: CORER */\n#define I40E_GLRPB_GHW_GHW_SHIFT 0\n#define I40E_GLRPB_GHW_GHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT)\n#define I40E_GLRPB_GLW 0x000AC834 /* Reset: CORER */\n#define I40E_GLRPB_GLW_GLW_SHIFT 0\n#define I40E_GLRPB_GLW_GLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GLW_GLW_SHIFT)\n#define I40E_GLRPB_PHW 0x000AC844 /* Reset: CORER */\n#define I40E_GLRPB_PHW_PHW_SHIFT 0\n#define I40E_GLRPB_PHW_PHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PHW_PHW_SHIFT)\n#define I40E_GLRPB_PLW 0x000AC848 /* Reset: CORER */\n#define I40E_GLRPB_PLW_PLW_SHIFT 0\n#define I40E_GLRPB_PLW_PLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PLW_PLW_SHIFT)\n#define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */\n#define I40E_PRTRPB_DHW_MAX_INDEX 7\n#define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0\n#define I40E_PRTRPB_DHW_DHW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DHW_DHW_TCN_SHIFT)\n#define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */\n#define I40E_PRTRPB_DLW_MAX_INDEX 7\n#define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0\n#define I40E_PRTRPB_DLW_DLW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DLW_DLW_TCN_SHIFT)\n#define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */\n#define I40E_PRTRPB_DPS_MAX_INDEX 7\n#define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0\n#define I40E_PRTRPB_DPS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DPS_DPS_TCN_SHIFT)\n#define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */\n#define I40E_PRTRPB_SHT_MAX_INDEX 7\n#define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0\n#define I40E_PRTRPB_SHT_SHT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHT_SHT_TCN_SHIFT)\n#define I40E_PRTRPB_SHW 0x000AC580 /* Reset: CORER */\n#define I40E_PRTRPB_SHW_SHW_SHIFT 0\n#define I40E_PRTRPB_SHW_SHW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHW_SHW_SHIFT)\n#define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */\n#define I40E_PRTRPB_SLT_MAX_INDEX 7\n#define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0\n#define I40E_PRTRPB_SLT_SLT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLT_SLT_TCN_SHIFT)\n#define I40E_PRTRPB_SLW 0x000AC6A0 /* Reset: CORER */\n#define I40E_PRTRPB_SLW_SLW_SHIFT 0\n#define I40E_PRTRPB_SLW_SLW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLW_SLW_SHIFT)\n#define I40E_PRTRPB_SPS 0x000AC7C0 /* Reset: CORER */\n#define I40E_PRTRPB_SPS_SPS_SHIFT 0\n#define I40E_PRTRPB_SPS_SPS_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SPS_SPS_SHIFT)\n#define I40E_GLQF_CTL 0x00269BA4 /* Reset: CORER */\n#define I40E_GLQF_CTL_HTOEP_SHIFT 1\n#define I40E_GLQF_CTL_HTOEP_MASK I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_SHIFT)\n#define I40E_GLQF_CTL_HTOEP_FCOE_SHIFT 2\n#define I40E_GLQF_CTL_HTOEP_FCOE_MASK I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_FCOE_SHIFT)\n#define I40E_GLQF_CTL_PCNT_ALLOC_SHIFT 3\n#define I40E_GLQF_CTL_PCNT_ALLOC_MASK I40E_MASK(0x7, I40E_GLQF_CTL_PCNT_ALLOC_SHIFT)\n#define I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT 6\n#define I40E_GLQF_CTL_FD_AUTO_PCTYPE_MASK I40E_MASK(0x1, I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT)\n#define I40E_GLQF_CTL_RSVD_SHIFT 7\n#define I40E_GLQF_CTL_RSVD_MASK I40E_MASK(0x1, I40E_GLQF_CTL_RSVD_SHIFT)\n#define I40E_GLQF_CTL_MAXPEBLEN_SHIFT 8\n#define I40E_GLQF_CTL_MAXPEBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXPEBLEN_SHIFT)\n#define I40E_GLQF_CTL_MAXFCBLEN_SHIFT 11\n#define I40E_GLQF_CTL_MAXFCBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFCBLEN_SHIFT)\n#define I40E_GLQF_CTL_MAXFDBLEN_SHIFT 14\n#define I40E_GLQF_CTL_MAXFDBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFDBLEN_SHIFT)\n#define I40E_GLQF_CTL_FDBEST_SHIFT 17\n#define I40E_GLQF_CTL_FDBEST_MASK I40E_MASK(0xFF, I40E_GLQF_CTL_FDBEST_SHIFT)\n#define I40E_GLQF_CTL_PROGPRIO_SHIFT 25\n#define I40E_GLQF_CTL_PROGPRIO_MASK I40E_MASK(0x1, I40E_GLQF_CTL_PROGPRIO_SHIFT)\n#define I40E_GLQF_CTL_INVALPRIO_SHIFT 26\n#define I40E_GLQF_CTL_INVALPRIO_MASK I40E_MASK(0x1, I40E_GLQF_CTL_INVALPRIO_SHIFT)\n#define I40E_GLQF_CTL_IGNORE_IP_SHIFT 27\n#define I40E_GLQF_CTL_IGNORE_IP_MASK I40E_MASK(0x1, I40E_GLQF_CTL_IGNORE_IP_SHIFT)\n#define I40E_GLQF_FDCNT_0 0x00269BAC /* Reset: CORER */\n#define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0\n#define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT)\n#define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13\n#define I40E_GLQF_FDCNT_0_BESTCNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT)\n#define I40E_GLQF_HKEY(_i) (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */\n#define I40E_GLQF_HKEY_MAX_INDEX 12\n#define I40E_GLQF_HKEY_KEY_0_SHIFT 0\n#define I40E_GLQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_0_SHIFT)\n#define I40E_GLQF_HKEY_KEY_1_SHIFT 8\n#define I40E_GLQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_1_SHIFT)\n#define I40E_GLQF_HKEY_KEY_2_SHIFT 16\n#define I40E_GLQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_2_SHIFT)\n#define I40E_GLQF_HKEY_KEY_3_SHIFT 24\n#define I40E_GLQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_3_SHIFT)\n#define I40E_GLQF_HSYM(_i) (0x00269D00 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */\n#define I40E_GLQF_HSYM_MAX_INDEX 63\n#define I40E_GLQF_HSYM_SYMH_ENA_SHIFT 0\n#define I40E_GLQF_HSYM_SYMH_ENA_MASK I40E_MASK(0x1, I40E_GLQF_HSYM_SYMH_ENA_SHIFT)\n#define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */\n#define I40E_GLQF_PCNT_MAX_INDEX 511\n#define I40E_GLQF_PCNT_PCNT_SHIFT 0\n#define I40E_GLQF_PCNT_PCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_PCNT_PCNT_SHIFT)\n#define I40E_GLQF_SWAP(_i, _j) (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */\n#define I40E_GLQF_SWAP_MAX_INDEX 1\n#define I40E_GLQF_SWAP_OFF0_SRC0_SHIFT 0\n#define I40E_GLQF_SWAP_OFF0_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC0_SHIFT)\n#define I40E_GLQF_SWAP_OFF0_SRC1_SHIFT 6\n#define I40E_GLQF_SWAP_OFF0_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC1_SHIFT)\n#define I40E_GLQF_SWAP_FLEN0_SHIFT 12\n#define I40E_GLQF_SWAP_FLEN0_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN0_SHIFT)\n#define I40E_GLQF_SWAP_OFF1_SRC0_SHIFT 16\n#define I40E_GLQF_SWAP_OFF1_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC0_SHIFT)\n#define I40E_GLQF_SWAP_OFF1_SRC1_SHIFT 22\n#define I40E_GLQF_SWAP_OFF1_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC1_SHIFT)\n#define I40E_GLQF_SWAP_FLEN1_SHIFT 28\n#define I40E_GLQF_SWAP_FLEN1_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN1_SHIFT)\n#define I40E_PFQF_CTL_0 0x001C0AC0 /* Reset: CORER */\n#define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0\n#define I40E_PFQF_CTL_0_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT)\n#define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5\n#define I40E_PFQF_CTL_0_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEDSIZE_SHIFT)\n#define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10\n#define I40E_PFQF_CTL_0_PFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT)\n#define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14\n#define I40E_PFQF_CTL_0_PFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT)\n#define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16\n#define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT)\n#define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17\n#define I40E_PFQF_CTL_0_FD_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_FD_ENA_SHIFT)\n#define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18\n#define I40E_PFQF_CTL_0_ETYPE_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT)\n#define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19\n#define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT)\n#define I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT 20\n#define I40E_PFQF_CTL_0_VFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT)\n#define I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT 24\n#define I40E_PFQF_CTL_0_VFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT)\n#define I40E_PFQF_CTL_1 0x00245D80 /* Reset: CORER */\n#define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0\n#define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT)\n#define I40E_PFQF_FDALLOC 0x00246280 /* Reset: CORER */\n#define I40E_PFQF_FDALLOC_FDALLOC_SHIFT 0\n#define I40E_PFQF_FDALLOC_FDALLOC_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDALLOC_SHIFT)\n#define I40E_PFQF_FDALLOC_FDBEST_SHIFT 8\n#define I40E_PFQF_FDALLOC_FDBEST_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDBEST_SHIFT)\n#define I40E_PFQF_FDSTAT 0x00246380 /* Reset: CORER */\n#define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0\n#define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT)\n#define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16\n#define I40E_PFQF_FDSTAT_BEST_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT)\n#define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */\n#define I40E_PFQF_HENA_MAX_INDEX 1\n#define I40E_PFQF_HENA_PTYPE_ENA_SHIFT 0\n#define I40E_PFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFQF_HENA_PTYPE_ENA_SHIFT)\n#define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */\n#define I40E_PFQF_HKEY_MAX_INDEX 12\n#define I40E_PFQF_HKEY_KEY_0_SHIFT 0\n#define I40E_PFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_0_SHIFT)\n#define I40E_PFQF_HKEY_KEY_1_SHIFT 8\n#define I40E_PFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_1_SHIFT)\n#define I40E_PFQF_HKEY_KEY_2_SHIFT 16\n#define I40E_PFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_2_SHIFT)\n#define I40E_PFQF_HKEY_KEY_3_SHIFT 24\n#define I40E_PFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_3_SHIFT)\n#define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_PFQF_HLUT_MAX_INDEX 127\n#define I40E_PFQF_HLUT_LUT0_SHIFT 0\n#define I40E_PFQF_HLUT_LUT0_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT0_SHIFT)\n#define I40E_PFQF_HLUT_LUT1_SHIFT 8\n#define I40E_PFQF_HLUT_LUT1_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT1_SHIFT)\n#define I40E_PFQF_HLUT_LUT2_SHIFT 16\n#define I40E_PFQF_HLUT_LUT2_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT2_SHIFT)\n#define I40E_PFQF_HLUT_LUT3_SHIFT 24\n#define I40E_PFQF_HLUT_LUT3_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT3_SHIFT)\n#define I40E_PRTQF_CTL_0 0x00256E60 /* Reset: CORER */\n#define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0\n#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK I40E_MASK(0x1, I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT)\n#define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */ /* Reset: CORER */\n#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63\n#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0\n#define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT)\n#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */\n#define I40E_PRTQF_FD_MSK_MAX_INDEX 63\n#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0\n#define I40E_PRTQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRTQF_FD_MSK_MASK_SHIFT)\n#define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16\n#define I40E_PRTQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_PRTQF_FD_MSK_OFFSET_SHIFT)\n#define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */\n#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8\n#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0\n#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)\n#define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5\n#define I40E_PRTQF_FLX_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)\n#define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10\n#define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)\n#define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */\n#define I40E_VFQF_HENA1_MAX_INDEX 1\n#define I40E_VFQF_HENA1_PTYPE_ENA_SHIFT 0\n#define I40E_VFQF_HENA1_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA1_PTYPE_ENA_SHIFT)\n#define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */\n#define I40E_VFQF_HKEY1_MAX_INDEX 12\n#define I40E_VFQF_HKEY1_KEY_0_SHIFT 0\n#define I40E_VFQF_HKEY1_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_0_SHIFT)\n#define I40E_VFQF_HKEY1_KEY_1_SHIFT 8\n#define I40E_VFQF_HKEY1_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_1_SHIFT)\n#define I40E_VFQF_HKEY1_KEY_2_SHIFT 16\n#define I40E_VFQF_HKEY1_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_2_SHIFT)\n#define I40E_VFQF_HKEY1_KEY_3_SHIFT 24\n#define I40E_VFQF_HKEY1_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_3_SHIFT)\n#define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */\n#define I40E_VFQF_HLUT1_MAX_INDEX 15\n#define I40E_VFQF_HLUT1_LUT0_SHIFT 0\n#define I40E_VFQF_HLUT1_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT0_SHIFT)\n#define I40E_VFQF_HLUT1_LUT1_SHIFT 8\n#define I40E_VFQF_HLUT1_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT1_SHIFT)\n#define I40E_VFQF_HLUT1_LUT2_SHIFT 16\n#define I40E_VFQF_HLUT1_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT2_SHIFT)\n#define I40E_VFQF_HLUT1_LUT3_SHIFT 24\n#define I40E_VFQF_HLUT1_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT3_SHIFT)\n#define I40E_VFQF_HREGION1(_i, _VF) (0x0022E000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...7, _VF=0...127 */ /* Reset: CORER */\n#define I40E_VFQF_HREGION1_MAX_INDEX 7\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT 0\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT)\n#define I40E_VFQF_HREGION1_REGION_0_SHIFT 1\n#define I40E_VFQF_HREGION1_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_0_SHIFT)\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT 4\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT)\n#define I40E_VFQF_HREGION1_REGION_1_SHIFT 5\n#define I40E_VFQF_HREGION1_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_1_SHIFT)\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT 8\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT)\n#define I40E_VFQF_HREGION1_REGION_2_SHIFT 9\n#define I40E_VFQF_HREGION1_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_2_SHIFT)\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT 12\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT)\n#define I40E_VFQF_HREGION1_REGION_3_SHIFT 13\n#define I40E_VFQF_HREGION1_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_3_SHIFT)\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT 16\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT)\n#define I40E_VFQF_HREGION1_REGION_4_SHIFT 17\n#define I40E_VFQF_HREGION1_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_4_SHIFT)\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT 20\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT)\n#define I40E_VFQF_HREGION1_REGION_5_SHIFT 21\n#define I40E_VFQF_HREGION1_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_5_SHIFT)\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT 24\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT)\n#define I40E_VFQF_HREGION1_REGION_6_SHIFT 25\n#define I40E_VFQF_HREGION1_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_6_SHIFT)\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT 28\n#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT)\n#define I40E_VFQF_HREGION1_REGION_7_SHIFT 29\n#define I40E_VFQF_HREGION1_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_7_SHIFT)\n#define I40E_VPQF_CTL(_VF) (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */\n#define I40E_VPQF_CTL_MAX_INDEX 127\n#define I40E_VPQF_CTL_PEHSIZE_SHIFT 0\n#define I40E_VPQF_CTL_PEHSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEHSIZE_SHIFT)\n#define I40E_VPQF_CTL_PEDSIZE_SHIFT 5\n#define I40E_VPQF_CTL_PEDSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEDSIZE_SHIFT)\n#define I40E_VPQF_CTL_FCHSIZE_SHIFT 10\n#define I40E_VPQF_CTL_FCHSIZE_MASK I40E_MASK(0xF, I40E_VPQF_CTL_FCHSIZE_SHIFT)\n#define I40E_VPQF_CTL_FCDSIZE_SHIFT 14\n#define I40E_VPQF_CTL_FCDSIZE_MASK I40E_MASK(0x3, I40E_VPQF_CTL_FCDSIZE_SHIFT)\n#define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */\n#define I40E_VSIQF_CTL_MAX_INDEX 383\n#define I40E_VSIQF_CTL_FCOE_ENA_SHIFT 0\n#define I40E_VSIQF_CTL_FCOE_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_FCOE_ENA_SHIFT)\n#define I40E_VSIQF_CTL_PETCP_ENA_SHIFT 1\n#define I40E_VSIQF_CTL_PETCP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PETCP_ENA_SHIFT)\n#define I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT 2\n#define I40E_VSIQF_CTL_PEUUDP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT)\n#define I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT 3\n#define I40E_VSIQF_CTL_PEMUDP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT)\n#define I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT 4\n#define I40E_VSIQF_CTL_PEUFRAG_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT)\n#define I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT 5\n#define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT)\n#define I40E_VSIQF_TCREGION(_i, _VSI) (0x00206000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...3, _VSI=0...383 */ /* Reset: PFR */\n#define I40E_VSIQF_TCREGION_MAX_INDEX 3\n#define I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT 0\n#define I40E_VSIQF_TCREGION_TC_OFFSET_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT)\n#define I40E_VSIQF_TCREGION_TC_SIZE_SHIFT 9\n#define I40E_VSIQF_TCREGION_TC_SIZE_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE_SHIFT)\n#define I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT 16\n#define I40E_VSIQF_TCREGION_TC_OFFSET2_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT)\n#define I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT 25\n#define I40E_VSIQF_TCREGION_TC_SIZE2_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT)\n#define I40E_GL_FCOECRC(_i) (0x00314d80 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOECRC_MAX_INDEX 143\n#define I40E_GL_FCOECRC_FCOECRC_SHIFT 0\n#define I40E_GL_FCOECRC_FCOECRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOECRC_FCOECRC_SHIFT)\n#define I40E_GL_FCOEDDPC(_i) (0x00314480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOEDDPC_MAX_INDEX 143\n#define I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT 0\n#define I40E_GL_FCOEDDPC_FCOEDDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT)\n#define I40E_GL_FCOEDIFEC(_i) (0x00318480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOEDIFEC_MAX_INDEX 143\n#define I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT 0\n#define I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT)\n#define I40E_GL_FCOEDIFTCL(_i) (0x00354000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOEDIFTCL_MAX_INDEX 143\n#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT 0\n#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT)\n#define I40E_GL_FCOEDIXEC(_i) (0x0034c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOEDIXEC_MAX_INDEX 143\n#define I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT 0\n#define I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT)\n#define I40E_GL_FCOEDIXVC(_i) (0x00350000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOEDIXVC_MAX_INDEX 143\n#define I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT 0\n#define I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT)\n#define I40E_GL_FCOEDWRCH(_i) (0x00320004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOEDWRCH_MAX_INDEX 143\n#define I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT 0\n#define I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT)\n#define I40E_GL_FCOEDWRCL(_i) (0x00320000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOEDWRCL_MAX_INDEX 143\n#define I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT 0\n#define I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT)\n#define I40E_GL_FCOEDWTCH(_i) (0x00348084 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOEDWTCH_MAX_INDEX 143\n#define I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT 0\n#define I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT)\n#define I40E_GL_FCOEDWTCL(_i) (0x00348080 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOEDWTCL_MAX_INDEX 143\n#define I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT 0\n#define I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT)\n#define I40E_GL_FCOELAST(_i) (0x00314000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOELAST_MAX_INDEX 143\n#define I40E_GL_FCOELAST_FCOELAST_SHIFT 0\n#define I40E_GL_FCOELAST_FCOELAST_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOELAST_FCOELAST_SHIFT)\n#define I40E_GL_FCOEPRC(_i) (0x00315200 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOEPRC_MAX_INDEX 143\n#define I40E_GL_FCOEPRC_FCOEPRC_SHIFT 0\n#define I40E_GL_FCOEPRC_FCOEPRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPRC_FCOEPRC_SHIFT)\n#define I40E_GL_FCOEPTC(_i) (0x00344C00 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOEPTC_MAX_INDEX 143\n#define I40E_GL_FCOEPTC_FCOEPTC_SHIFT 0\n#define I40E_GL_FCOEPTC_FCOEPTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPTC_FCOEPTC_SHIFT)\n#define I40E_GL_FCOERPDC(_i) (0x00324000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_FCOERPDC_MAX_INDEX 143\n#define I40E_GL_FCOERPDC_FCOERPDC_SHIFT 0\n#define I40E_GL_FCOERPDC_FCOERPDC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOERPDC_FCOERPDC_SHIFT)\n#define I40E_GL_RXERR1_L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_RXERR1_L_MAX_INDEX 143\n#define I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT 0\n#define I40E_GL_RXERR1_L_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT)\n#define I40E_GL_RXERR2_L(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */\n#define I40E_GL_RXERR2_L_MAX_INDEX 143\n#define I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT 0\n#define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT)\n#define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_BPRCH_MAX_INDEX 3\n#define I40E_GLPRT_BPRCH_BPRCH_SHIFT 0\n#define I40E_GLPRT_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_BPRCH_SHIFT)\n#define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_BPRCL_MAX_INDEX 3\n#define I40E_GLPRT_BPRCL_BPRCL_SHIFT 0\n#define I40E_GLPRT_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_BPRCL_SHIFT)\n#define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_BPTCH_MAX_INDEX 3\n#define I40E_GLPRT_BPTCH_BPTCH_SHIFT 0\n#define I40E_GLPRT_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_BPTCH_SHIFT)\n#define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_BPTCL_MAX_INDEX 3\n#define I40E_GLPRT_BPTCL_BPTCL_SHIFT 0\n#define I40E_GLPRT_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_BPTCL_SHIFT)\n#define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_CRCERRS_MAX_INDEX 3\n#define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0\n#define I40E_GLPRT_CRCERRS_CRCERRS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_CRCERRS_CRCERRS_SHIFT)\n#define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_GORCH_MAX_INDEX 3\n#define I40E_GLPRT_GORCH_GORCH_SHIFT 0\n#define I40E_GLPRT_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GORCH_GORCH_SHIFT)\n#define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_GORCL_MAX_INDEX 3\n#define I40E_GLPRT_GORCL_GORCL_SHIFT 0\n#define I40E_GLPRT_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GORCL_GORCL_SHIFT)\n#define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_GOTCH_MAX_INDEX 3\n#define I40E_GLPRT_GOTCH_GOTCH_SHIFT 0\n#define I40E_GLPRT_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GOTCH_GOTCH_SHIFT)\n#define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_GOTCL_MAX_INDEX 3\n#define I40E_GLPRT_GOTCL_GOTCL_SHIFT 0\n#define I40E_GLPRT_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GOTCL_GOTCL_SHIFT)\n#define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_ILLERRC_MAX_INDEX 3\n#define I40E_GLPRT_ILLERRC_ILLERRC_SHIFT 0\n#define I40E_GLPRT_ILLERRC_ILLERRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ILLERRC_ILLERRC_SHIFT)\n#define I40E_GLPRT_LDPC(_i) (0x00300620 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_LDPC_MAX_INDEX 3\n#define I40E_GLPRT_LDPC_LDPC_SHIFT 0\n#define I40E_GLPRT_LDPC_LDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LDPC_LDPC_SHIFT)\n#define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_LXOFFRXC_MAX_INDEX 3\n#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT 0\n#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT)\n#define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_LXOFFTXC_MAX_INDEX 3\n#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT 0\n#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT)\n#define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_LXONRXC_MAX_INDEX 3\n#define I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT 0\n#define I40E_GLPRT_LXONRXC_LXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT)\n#define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_LXONTXC_MAX_INDEX 3\n#define I40E_GLPRT_LXONTXC_LXONTXC_SHIFT 0\n#define I40E_GLPRT_LXONTXC_LXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONTXC_LXONTXC_SHIFT)\n#define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_MLFC_MAX_INDEX 3\n#define I40E_GLPRT_MLFC_MLFC_SHIFT 0\n#define I40E_GLPRT_MLFC_MLFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MLFC_MLFC_SHIFT)\n#define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_MPRCH_MAX_INDEX 3\n#define I40E_GLPRT_MPRCH_MPRCH_SHIFT 0\n#define I40E_GLPRT_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPRCH_MPRCH_SHIFT)\n#define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_MPRCL_MAX_INDEX 3\n#define I40E_GLPRT_MPRCL_MPRCL_SHIFT 0\n#define I40E_GLPRT_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPRCL_MPRCL_SHIFT)\n#define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_MPTCH_MAX_INDEX 3\n#define I40E_GLPRT_MPTCH_MPTCH_SHIFT 0\n#define I40E_GLPRT_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPTCH_MPTCH_SHIFT)\n#define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_MPTCL_MAX_INDEX 3\n#define I40E_GLPRT_MPTCL_MPTCL_SHIFT 0\n#define I40E_GLPRT_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPTCL_MPTCL_SHIFT)\n#define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_MRFC_MAX_INDEX 3\n#define I40E_GLPRT_MRFC_MRFC_SHIFT 0\n#define I40E_GLPRT_MRFC_MRFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MRFC_MRFC_SHIFT)\n#define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC1023H_MAX_INDEX 3\n#define I40E_GLPRT_PRC1023H_PRC1023H_SHIFT 0\n#define I40E_GLPRT_PRC1023H_PRC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1023H_PRC1023H_SHIFT)\n#define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC1023L_MAX_INDEX 3\n#define I40E_GLPRT_PRC1023L_PRC1023L_SHIFT 0\n#define I40E_GLPRT_PRC1023L_PRC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1023L_PRC1023L_SHIFT)\n#define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC127H_MAX_INDEX 3\n#define I40E_GLPRT_PRC127H_PRC127H_SHIFT 0\n#define I40E_GLPRT_PRC127H_PRC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC127H_PRC127H_SHIFT)\n#define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC127L_MAX_INDEX 3\n#define I40E_GLPRT_PRC127L_PRC127L_SHIFT 0\n#define I40E_GLPRT_PRC127L_PRC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC127L_PRC127L_SHIFT)\n#define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC1522H_MAX_INDEX 3\n#define I40E_GLPRT_PRC1522H_PRC1522H_SHIFT 0\n#define I40E_GLPRT_PRC1522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1522H_PRC1522H_SHIFT)\n#define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC1522L_MAX_INDEX 3\n#define I40E_GLPRT_PRC1522L_PRC1522L_SHIFT 0\n#define I40E_GLPRT_PRC1522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1522L_PRC1522L_SHIFT)\n#define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC255H_MAX_INDEX 3\n#define I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT 0\n#define I40E_GLPRT_PRC255H_PRTPRC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT)\n#define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC255L_MAX_INDEX 3\n#define I40E_GLPRT_PRC255L_PRC255L_SHIFT 0\n#define I40E_GLPRT_PRC255L_PRC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC255L_PRC255L_SHIFT)\n#define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC511H_MAX_INDEX 3\n#define I40E_GLPRT_PRC511H_PRC511H_SHIFT 0\n#define I40E_GLPRT_PRC511H_PRC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC511H_PRC511H_SHIFT)\n#define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC511L_MAX_INDEX 3\n#define I40E_GLPRT_PRC511L_PRC511L_SHIFT 0\n#define I40E_GLPRT_PRC511L_PRC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC511L_PRC511L_SHIFT)\n#define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC64H_MAX_INDEX 3\n#define I40E_GLPRT_PRC64H_PRC64H_SHIFT 0\n#define I40E_GLPRT_PRC64H_PRC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC64H_PRC64H_SHIFT)\n#define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC64L_MAX_INDEX 3\n#define I40E_GLPRT_PRC64L_PRC64L_SHIFT 0\n#define I40E_GLPRT_PRC64L_PRC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC64L_PRC64L_SHIFT)\n#define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC9522H_MAX_INDEX 3\n#define I40E_GLPRT_PRC9522H_PRC1522H_SHIFT 0\n#define I40E_GLPRT_PRC9522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC9522H_PRC1522H_SHIFT)\n#define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PRC9522L_MAX_INDEX 3\n#define I40E_GLPRT_PRC9522L_PRC1522L_SHIFT 0\n#define I40E_GLPRT_PRC9522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC9522L_PRC1522L_SHIFT)\n#define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC1023H_MAX_INDEX 3\n#define I40E_GLPRT_PTC1023H_PTC1023H_SHIFT 0\n#define I40E_GLPRT_PTC1023H_PTC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1023H_PTC1023H_SHIFT)\n#define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC1023L_MAX_INDEX 3\n#define I40E_GLPRT_PTC1023L_PTC1023L_SHIFT 0\n#define I40E_GLPRT_PTC1023L_PTC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1023L_PTC1023L_SHIFT)\n#define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC127H_MAX_INDEX 3\n#define I40E_GLPRT_PTC127H_PTC127H_SHIFT 0\n#define I40E_GLPRT_PTC127H_PTC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC127H_PTC127H_SHIFT)\n#define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC127L_MAX_INDEX 3\n#define I40E_GLPRT_PTC127L_PTC127L_SHIFT 0\n#define I40E_GLPRT_PTC127L_PTC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC127L_PTC127L_SHIFT)\n#define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC1522H_MAX_INDEX 3\n#define I40E_GLPRT_PTC1522H_PTC1522H_SHIFT 0\n#define I40E_GLPRT_PTC1522H_PTC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1522H_PTC1522H_SHIFT)\n#define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC1522L_MAX_INDEX 3\n#define I40E_GLPRT_PTC1522L_PTC1522L_SHIFT 0\n#define I40E_GLPRT_PTC1522L_PTC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1522L_PTC1522L_SHIFT)\n#define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC255H_MAX_INDEX 3\n#define I40E_GLPRT_PTC255H_PTC255H_SHIFT 0\n#define I40E_GLPRT_PTC255H_PTC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC255H_PTC255H_SHIFT)\n#define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC255L_MAX_INDEX 3\n#define I40E_GLPRT_PTC255L_PTC255L_SHIFT 0\n#define I40E_GLPRT_PTC255L_PTC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC255L_PTC255L_SHIFT)\n#define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC511H_MAX_INDEX 3\n#define I40E_GLPRT_PTC511H_PTC511H_SHIFT 0\n#define I40E_GLPRT_PTC511H_PTC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC511H_PTC511H_SHIFT)\n#define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC511L_MAX_INDEX 3\n#define I40E_GLPRT_PTC511L_PTC511L_SHIFT 0\n#define I40E_GLPRT_PTC511L_PTC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC511L_PTC511L_SHIFT)\n#define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC64H_MAX_INDEX 3\n#define I40E_GLPRT_PTC64H_PTC64H_SHIFT 0\n#define I40E_GLPRT_PTC64H_PTC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC64H_PTC64H_SHIFT)\n#define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC64L_MAX_INDEX 3\n#define I40E_GLPRT_PTC64L_PTC64L_SHIFT 0\n#define I40E_GLPRT_PTC64L_PTC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC64L_PTC64L_SHIFT)\n#define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC9522H_MAX_INDEX 3\n#define I40E_GLPRT_PTC9522H_PTC9522H_SHIFT 0\n#define I40E_GLPRT_PTC9522H_PTC9522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC9522H_PTC9522H_SHIFT)\n#define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_PTC9522L_MAX_INDEX 3\n#define I40E_GLPRT_PTC9522L_PTC9522L_SHIFT 0\n#define I40E_GLPRT_PTC9522L_PTC9522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC9522L_PTC9522L_SHIFT)\n#define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */\n#define I40E_GLPRT_PXOFFRXC_MAX_INDEX 3\n#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT 0\n#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT)\n#define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */\n#define I40E_GLPRT_PXOFFTXC_MAX_INDEX 3\n#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT 0\n#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT)\n#define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */\n#define I40E_GLPRT_PXONRXC_MAX_INDEX 3\n#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT 0\n#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT)\n#define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */\n#define I40E_GLPRT_PXONTXC_MAX_INDEX 3\n#define I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT 0\n#define I40E_GLPRT_PXONTXC_PRPXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT)\n#define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_RDPC_MAX_INDEX 3\n#define I40E_GLPRT_RDPC_RDPC_SHIFT 0\n#define I40E_GLPRT_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RDPC_RDPC_SHIFT)\n#define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_RFC_MAX_INDEX 3\n#define I40E_GLPRT_RFC_RFC_SHIFT 0\n#define I40E_GLPRT_RFC_RFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RFC_RFC_SHIFT)\n#define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_RJC_MAX_INDEX 3\n#define I40E_GLPRT_RJC_RJC_SHIFT 0\n#define I40E_GLPRT_RJC_RJC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RJC_RJC_SHIFT)\n#define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_RLEC_MAX_INDEX 3\n#define I40E_GLPRT_RLEC_RLEC_SHIFT 0\n#define I40E_GLPRT_RLEC_RLEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RLEC_RLEC_SHIFT)\n#define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_ROC_MAX_INDEX 3\n#define I40E_GLPRT_ROC_ROC_SHIFT 0\n#define I40E_GLPRT_ROC_ROC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ROC_ROC_SHIFT)\n#define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_RUC_MAX_INDEX 3\n#define I40E_GLPRT_RUC_RUC_SHIFT 0\n#define I40E_GLPRT_RUC_RUC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUC_RUC_SHIFT)\n#define I40E_GLPRT_RUPP(_i) (0x00300660 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_RUPP_MAX_INDEX 3\n#define I40E_GLPRT_RUPP_RUPP_SHIFT 0\n#define I40E_GLPRT_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUPP_RUPP_SHIFT)\n#define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */\n#define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX 3\n#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0\n#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT)\n#define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_TDOLD_MAX_INDEX 3\n#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0\n#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT)\n#define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_UPRCH_MAX_INDEX 3\n#define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0\n#define I40E_GLPRT_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPRCH_UPRCH_SHIFT)\n#define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_UPRCL_MAX_INDEX 3\n#define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0\n#define I40E_GLPRT_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPRCL_UPRCL_SHIFT)\n#define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_UPTCH_MAX_INDEX 3\n#define I40E_GLPRT_UPTCH_UPTCH_SHIFT 0\n#define I40E_GLPRT_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPTCH_UPTCH_SHIFT)\n#define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_GLPRT_UPTCL_MAX_INDEX 3\n#define I40E_GLPRT_UPTCL_VUPTCH_SHIFT 0\n#define I40E_GLPRT_UPTCL_VUPTCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPTCL_VUPTCH_SHIFT)\n#define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_BPRCH_MAX_INDEX 15\n#define I40E_GLSW_BPRCH_BPRCH_SHIFT 0\n#define I40E_GLSW_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPRCH_BPRCH_SHIFT)\n#define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_BPRCL_MAX_INDEX 15\n#define I40E_GLSW_BPRCL_BPRCL_SHIFT 0\n#define I40E_GLSW_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPRCL_BPRCL_SHIFT)\n#define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_BPTCH_MAX_INDEX 15\n#define I40E_GLSW_BPTCH_BPTCH_SHIFT 0\n#define I40E_GLSW_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPTCH_BPTCH_SHIFT)\n#define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_BPTCL_MAX_INDEX 15\n#define I40E_GLSW_BPTCL_BPTCL_SHIFT 0\n#define I40E_GLSW_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPTCL_BPTCL_SHIFT)\n#define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_GORCH_MAX_INDEX 15\n#define I40E_GLSW_GORCH_GORCH_SHIFT 0\n#define I40E_GLSW_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GORCH_GORCH_SHIFT)\n#define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_GORCL_MAX_INDEX 15\n#define I40E_GLSW_GORCL_GORCL_SHIFT 0\n#define I40E_GLSW_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GORCL_GORCL_SHIFT)\n#define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_GOTCH_MAX_INDEX 15\n#define I40E_GLSW_GOTCH_GOTCH_SHIFT 0\n#define I40E_GLSW_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GOTCH_GOTCH_SHIFT)\n#define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_GOTCL_MAX_INDEX 15\n#define I40E_GLSW_GOTCL_GOTCL_SHIFT 0\n#define I40E_GLSW_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GOTCL_GOTCL_SHIFT)\n#define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_MPRCH_MAX_INDEX 15\n#define I40E_GLSW_MPRCH_MPRCH_SHIFT 0\n#define I40E_GLSW_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPRCH_MPRCH_SHIFT)\n#define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_MPRCL_MAX_INDEX 15\n#define I40E_GLSW_MPRCL_MPRCL_SHIFT 0\n#define I40E_GLSW_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPRCL_MPRCL_SHIFT)\n#define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_MPTCH_MAX_INDEX 15\n#define I40E_GLSW_MPTCH_MPTCH_SHIFT 0\n#define I40E_GLSW_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPTCH_MPTCH_SHIFT)\n#define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_MPTCL_MAX_INDEX 15\n#define I40E_GLSW_MPTCL_MPTCL_SHIFT 0\n#define I40E_GLSW_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPTCL_MPTCL_SHIFT)\n#define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_RUPP_MAX_INDEX 15\n#define I40E_GLSW_RUPP_RUPP_SHIFT 0\n#define I40E_GLSW_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_RUPP_RUPP_SHIFT)\n#define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_TDPC_MAX_INDEX 15\n#define I40E_GLSW_TDPC_TDPC_SHIFT 0\n#define I40E_GLSW_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_TDPC_TDPC_SHIFT)\n#define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_UPRCH_MAX_INDEX 15\n#define I40E_GLSW_UPRCH_UPRCH_SHIFT 0\n#define I40E_GLSW_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPRCH_UPRCH_SHIFT)\n#define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_UPRCL_MAX_INDEX 15\n#define I40E_GLSW_UPRCL_UPRCL_SHIFT 0\n#define I40E_GLSW_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPRCL_UPRCL_SHIFT)\n#define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_UPTCH_MAX_INDEX 15\n#define I40E_GLSW_UPTCH_UPTCH_SHIFT 0\n#define I40E_GLSW_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPTCH_UPTCH_SHIFT)\n#define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_GLSW_UPTCL_MAX_INDEX 15\n#define I40E_GLSW_UPTCL_UPTCL_SHIFT 0\n#define I40E_GLSW_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPTCL_UPTCL_SHIFT)\n#define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_BPRCH_MAX_INDEX 383\n#define I40E_GLV_BPRCH_BPRCH_SHIFT 0\n#define I40E_GLV_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPRCH_BPRCH_SHIFT)\n#define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_BPRCL_MAX_INDEX 383\n#define I40E_GLV_BPRCL_BPRCL_SHIFT 0\n#define I40E_GLV_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPRCL_BPRCL_SHIFT)\n#define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_BPTCH_MAX_INDEX 383\n#define I40E_GLV_BPTCH_BPTCH_SHIFT 0\n#define I40E_GLV_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPTCH_BPTCH_SHIFT)\n#define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_BPTCL_MAX_INDEX 383\n#define I40E_GLV_BPTCL_BPTCL_SHIFT 0\n#define I40E_GLV_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPTCL_BPTCL_SHIFT)\n#define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_GORCH_MAX_INDEX 383\n#define I40E_GLV_GORCH_GORCH_SHIFT 0\n#define I40E_GLV_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GORCH_GORCH_SHIFT)\n#define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_GORCL_MAX_INDEX 383\n#define I40E_GLV_GORCL_GORCL_SHIFT 0\n#define I40E_GLV_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GORCL_GORCL_SHIFT)\n#define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_GOTCH_MAX_INDEX 383\n#define I40E_GLV_GOTCH_GOTCH_SHIFT 0\n#define I40E_GLV_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GOTCH_GOTCH_SHIFT)\n#define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_GOTCL_MAX_INDEX 383\n#define I40E_GLV_GOTCL_GOTCL_SHIFT 0\n#define I40E_GLV_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GOTCL_GOTCL_SHIFT)\n#define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_MPRCH_MAX_INDEX 383\n#define I40E_GLV_MPRCH_MPRCH_SHIFT 0\n#define I40E_GLV_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPRCH_MPRCH_SHIFT)\n#define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_MPRCL_MAX_INDEX 383\n#define I40E_GLV_MPRCL_MPRCL_SHIFT 0\n#define I40E_GLV_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPRCL_MPRCL_SHIFT)\n#define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_MPTCH_MAX_INDEX 383\n#define I40E_GLV_MPTCH_MPTCH_SHIFT 0\n#define I40E_GLV_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPTCH_MPTCH_SHIFT)\n#define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_MPTCL_MAX_INDEX 383\n#define I40E_GLV_MPTCL_MPTCL_SHIFT 0\n#define I40E_GLV_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPTCL_MPTCL_SHIFT)\n#define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_RDPC_MAX_INDEX 383\n#define I40E_GLV_RDPC_RDPC_SHIFT 0\n#define I40E_GLV_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RDPC_RDPC_SHIFT)\n#define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_RUPP_MAX_INDEX 383\n#define I40E_GLV_RUPP_RUPP_SHIFT 0\n#define I40E_GLV_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RUPP_RUPP_SHIFT)\n#define I40E_GLV_TEPC(_VSI) (0x00344000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_TEPC_MAX_INDEX 383\n#define I40E_GLV_TEPC_TEPC_SHIFT 0\n#define I40E_GLV_TEPC_TEPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_TEPC_TEPC_SHIFT)\n#define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_UPRCH_MAX_INDEX 383\n#define I40E_GLV_UPRCH_UPRCH_SHIFT 0\n#define I40E_GLV_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPRCH_UPRCH_SHIFT)\n#define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_UPRCL_MAX_INDEX 383\n#define I40E_GLV_UPRCL_UPRCL_SHIFT 0\n#define I40E_GLV_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPRCL_UPRCL_SHIFT)\n#define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_UPTCH_MAX_INDEX 383\n#define I40E_GLV_UPTCH_GLVUPTCH_SHIFT 0\n#define I40E_GLV_UPTCH_GLVUPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPTCH_GLVUPTCH_SHIFT)\n#define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */\n#define I40E_GLV_UPTCL_MAX_INDEX 383\n#define I40E_GLV_UPTCL_UPTCL_SHIFT 0\n#define I40E_GLV_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPTCL_UPTCL_SHIFT)\n#define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */\n#define I40E_GLVEBTC_RBCH_MAX_INDEX 7\n#define I40E_GLVEBTC_RBCH_TCBCH_SHIFT 0\n#define I40E_GLVEBTC_RBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RBCH_TCBCH_SHIFT)\n#define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */\n#define I40E_GLVEBTC_RBCL_MAX_INDEX 7\n#define I40E_GLVEBTC_RBCL_TCBCL_SHIFT 0\n#define I40E_GLVEBTC_RBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RBCL_TCBCL_SHIFT)\n#define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */\n#define I40E_GLVEBTC_RPCH_MAX_INDEX 7\n#define I40E_GLVEBTC_RPCH_TCPCH_SHIFT 0\n#define I40E_GLVEBTC_RPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RPCH_TCPCH_SHIFT)\n#define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */\n#define I40E_GLVEBTC_RPCL_MAX_INDEX 7\n#define I40E_GLVEBTC_RPCL_TCPCL_SHIFT 0\n#define I40E_GLVEBTC_RPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RPCL_TCPCL_SHIFT)\n#define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */\n#define I40E_GLVEBTC_TBCH_MAX_INDEX 7\n#define I40E_GLVEBTC_TBCH_TCBCH_SHIFT 0\n#define I40E_GLVEBTC_TBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TBCH_TCBCH_SHIFT)\n#define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */\n#define I40E_GLVEBTC_TBCL_MAX_INDEX 7\n#define I40E_GLVEBTC_TBCL_TCBCL_SHIFT 0\n#define I40E_GLVEBTC_TBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TBCL_TCBCL_SHIFT)\n#define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */\n#define I40E_GLVEBTC_TPCH_MAX_INDEX 7\n#define I40E_GLVEBTC_TPCH_TCPCH_SHIFT 0\n#define I40E_GLVEBTC_TPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TPCH_TCPCH_SHIFT)\n#define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */\n#define I40E_GLVEBTC_TPCL_MAX_INDEX 7\n#define I40E_GLVEBTC_TPCL_TCPCL_SHIFT 0\n#define I40E_GLVEBTC_TPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TPCL_TCPCL_SHIFT)\n#define I40E_GLVEBVL_BPCH(_i) (0x00374804 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_GLVEBVL_BPCH_MAX_INDEX 127\n#define I40E_GLVEBVL_BPCH_VLBPCH_SHIFT 0\n#define I40E_GLVEBVL_BPCH_VLBPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_BPCH_VLBPCH_SHIFT)\n#define I40E_GLVEBVL_BPCL(_i) (0x00374800 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_GLVEBVL_BPCL_MAX_INDEX 127\n#define I40E_GLVEBVL_BPCL_VLBPCL_SHIFT 0\n#define I40E_GLVEBVL_BPCL_VLBPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_BPCL_VLBPCL_SHIFT)\n#define I40E_GLVEBVL_GORCH(_i) (0x00360004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_GLVEBVL_GORCH_MAX_INDEX 127\n#define I40E_GLVEBVL_GORCH_VLBCH_SHIFT 0\n#define I40E_GLVEBVL_GORCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GORCH_VLBCH_SHIFT)\n#define I40E_GLVEBVL_GORCL(_i) (0x00360000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_GLVEBVL_GORCL_MAX_INDEX 127\n#define I40E_GLVEBVL_GORCL_VLBCL_SHIFT 0\n#define I40E_GLVEBVL_GORCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GORCL_VLBCL_SHIFT)\n#define I40E_GLVEBVL_GOTCH(_i) (0x00330004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_GLVEBVL_GOTCH_MAX_INDEX 127\n#define I40E_GLVEBVL_GOTCH_VLBCH_SHIFT 0\n#define I40E_GLVEBVL_GOTCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GOTCH_VLBCH_SHIFT)\n#define I40E_GLVEBVL_GOTCL(_i) (0x00330000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_GLVEBVL_GOTCL_MAX_INDEX 127\n#define I40E_GLVEBVL_GOTCL_VLBCL_SHIFT 0\n#define I40E_GLVEBVL_GOTCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GOTCL_VLBCL_SHIFT)\n#define I40E_GLVEBVL_MPCH(_i) (0x00374404 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_GLVEBVL_MPCH_MAX_INDEX 127\n#define I40E_GLVEBVL_MPCH_VLMPCH_SHIFT 0\n#define I40E_GLVEBVL_MPCH_VLMPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_MPCH_VLMPCH_SHIFT)\n#define I40E_GLVEBVL_MPCL(_i) (0x00374400 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_GLVEBVL_MPCL_MAX_INDEX 127\n#define I40E_GLVEBVL_MPCL_VLMPCL_SHIFT 0\n#define I40E_GLVEBVL_MPCL_VLMPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_MPCL_VLMPCL_SHIFT)\n#define I40E_GLVEBVL_UPCH(_i) (0x00374004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_GLVEBVL_UPCH_MAX_INDEX 127\n#define I40E_GLVEBVL_UPCH_VLUPCH_SHIFT 0\n#define I40E_GLVEBVL_UPCH_VLUPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_UPCH_VLUPCH_SHIFT)\n#define I40E_GLVEBVL_UPCL(_i) (0x00374000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_GLVEBVL_UPCL_MAX_INDEX 127\n#define I40E_GLVEBVL_UPCL_VLUPCL_SHIFT 0\n#define I40E_GLVEBVL_UPCL_VLUPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_UPCL_VLUPCL_SHIFT)\n#define I40E_GL_MTG_FLU_MSK_H 0x00269F4C /* Reset: CORER */\n#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT 0\n#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK I40E_MASK(0xFFFF, I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT)\n#define I40E_GL_SWR_DEF_ACT(_i) (0x00270200 + ((_i) * 4)) /* _i=0...35 */ /* Reset: CORER */\n#define I40E_GL_SWR_DEF_ACT_MAX_INDEX 35\n#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT 0\n#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT)\n#define I40E_GL_SWR_DEF_ACT_EN(_i) (0x0026CFB8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */\n#define I40E_GL_SWR_DEF_ACT_EN_MAX_INDEX 1\n#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT 0\n#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT)\n#define I40E_PRTTSYN_ADJ 0x001E4280 /* Reset: GLOBR */\n#define I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT 0\n#define I40E_PRTTSYN_ADJ_TSYNADJ_MASK I40E_MASK(0x7FFFFFFF, I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT)\n#define I40E_PRTTSYN_ADJ_SIGN_SHIFT 31\n#define I40E_PRTTSYN_ADJ_SIGN_MASK I40E_MASK(0x1, I40E_PRTTSYN_ADJ_SIGN_SHIFT)\n#define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */\n#define I40E_PRTTSYN_AUX_0_MAX_INDEX 1\n#define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0\n#define I40E_PRTTSYN_AUX_0_OUT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)\n#define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1\n#define I40E_PRTTSYN_AUX_0_OUTMOD_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)\n#define I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT 3\n#define I40E_PRTTSYN_AUX_0_OUTLVL_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT)\n#define I40E_PRTTSYN_AUX_0_PULSEW_SHIFT 8\n#define I40E_PRTTSYN_AUX_0_PULSEW_MASK I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT)\n#define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16\n#define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT)\n#define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */\n#define I40E_PRTTSYN_AUX_1_MAX_INDEX 1\n#define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0\n#define I40E_PRTTSYN_AUX_1_INSTNT_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)\n#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT 1\n#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT)\n#define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */\n#define I40E_PRTTSYN_CLKO_MAX_INDEX 1\n#define I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT 0\n#define I40E_PRTTSYN_CLKO_TSYNCLKO_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT)\n#define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */\n#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT 0\n#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT)\n#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1\n#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT)\n#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2\n#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT)\n#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT 3\n#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT)\n#define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8\n#define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT)\n#define I40E_PRTTSYN_CTL0_TSYNACT_SHIFT 12\n#define I40E_PRTTSYN_CTL0_TSYNACT_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL0_TSYNACT_SHIFT)\n#define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31\n#define I40E_PRTTSYN_CTL0_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT)\n#define I40E_PRTTSYN_CTL1 0x00085020 /* Reset: CORER */\n#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0\n#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT)\n#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT 8\n#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT)\n#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16\n#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT)\n#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT 20\n#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT)\n#define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24\n#define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)\n#define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26\n#define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT)\n#define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31\n#define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT)\n#define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */\n#define I40E_PRTTSYN_EVNT_H_MAX_INDEX 1\n#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT 0\n#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT)\n#define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */\n#define I40E_PRTTSYN_EVNT_L_MAX_INDEX 1\n#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT 0\n#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT)\n#define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */\n#define I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT 0\n#define I40E_PRTTSYN_INC_H_TSYNINC_H_MASK I40E_MASK(0x3F, I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT)\n#define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */\n#define I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT 0\n#define I40E_PRTTSYN_INC_L_TSYNINC_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT)\n#define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_PRTTSYN_RXTIME_H_MAX_INDEX 3\n#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT 0\n#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT)\n#define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */\n#define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3\n#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT 0\n#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT)\n#define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */\n#define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0\n#define I40E_PRTTSYN_STAT_0_EVENT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT0_SHIFT)\n#define I40E_PRTTSYN_STAT_0_EVENT1_SHIFT 1\n#define I40E_PRTTSYN_STAT_0_EVENT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT1_SHIFT)\n#define I40E_PRTTSYN_STAT_0_TGT0_SHIFT 2\n#define I40E_PRTTSYN_STAT_0_TGT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT0_SHIFT)\n#define I40E_PRTTSYN_STAT_0_TGT1_SHIFT 3\n#define I40E_PRTTSYN_STAT_0_TGT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT1_SHIFT)\n#define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4\n#define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT)\n#define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */\n#define I40E_PRTTSYN_STAT_1_RXT0_SHIFT 0\n#define I40E_PRTTSYN_STAT_1_RXT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT0_SHIFT)\n#define I40E_PRTTSYN_STAT_1_RXT1_SHIFT 1\n#define I40E_PRTTSYN_STAT_1_RXT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT1_SHIFT)\n#define I40E_PRTTSYN_STAT_1_RXT2_SHIFT 2\n#define I40E_PRTTSYN_STAT_1_RXT2_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT2_SHIFT)\n#define I40E_PRTTSYN_STAT_1_RXT3_SHIFT 3\n#define I40E_PRTTSYN_STAT_1_RXT3_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT3_SHIFT)\n#define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */\n#define I40E_PRTTSYN_TGT_H_MAX_INDEX 1\n#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT 0\n#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT)\n#define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */\n#define I40E_PRTTSYN_TGT_L_MAX_INDEX 1\n#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT 0\n#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT)\n#define I40E_PRTTSYN_TIME_H 0x001E4120 /* Reset: GLOBR */\n#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT 0\n#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT)\n#define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */\n#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0\n#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT)\n#define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */\n#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0\n#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT)\n#define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */\n#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0\n#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT)\n#define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */\n#define I40E_GL_MDET_RX_FUNCTION_SHIFT 0\n#define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT)\n#define I40E_GL_MDET_RX_EVENT_SHIFT 8\n#define I40E_GL_MDET_RX_EVENT_MASK I40E_MASK(0x1FF, I40E_GL_MDET_RX_EVENT_SHIFT)\n#define I40E_GL_MDET_RX_QUEUE_SHIFT 17\n#define I40E_GL_MDET_RX_QUEUE_MASK I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT)\n#define I40E_GL_MDET_RX_VALID_SHIFT 31\n#define I40E_GL_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_RX_VALID_SHIFT)\n#define I40E_GL_MDET_TX 0x000E6480 /* Reset: CORER */\n#define I40E_GL_MDET_TX_QUEUE_SHIFT 0\n#define I40E_GL_MDET_TX_QUEUE_MASK I40E_MASK(0xFFF, I40E_GL_MDET_TX_QUEUE_SHIFT)\n#define I40E_GL_MDET_TX_VF_NUM_SHIFT 12\n#define I40E_GL_MDET_TX_VF_NUM_MASK I40E_MASK(0x1FF, I40E_GL_MDET_TX_VF_NUM_SHIFT)\n#define I40E_GL_MDET_TX_PF_NUM_SHIFT 21\n#define I40E_GL_MDET_TX_PF_NUM_MASK I40E_MASK(0xF, I40E_GL_MDET_TX_PF_NUM_SHIFT)\n#define I40E_GL_MDET_TX_EVENT_SHIFT 25\n#define I40E_GL_MDET_TX_EVENT_MASK I40E_MASK(0x1F, I40E_GL_MDET_TX_EVENT_SHIFT)\n#define I40E_GL_MDET_TX_VALID_SHIFT 31\n#define I40E_GL_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_TX_VALID_SHIFT)\n#define I40E_PF_MDET_RX 0x0012A400 /* Reset: CORER */\n#define I40E_PF_MDET_RX_VALID_SHIFT 0\n#define I40E_PF_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_RX_VALID_SHIFT)\n#define I40E_PF_MDET_TX 0x000E6400 /* Reset: CORER */\n#define I40E_PF_MDET_TX_VALID_SHIFT 0\n#define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT)\n#define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */\n#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0\n#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT)\n#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8\n#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT)\n#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31\n#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1, I40E_PF_VT_PFALLOC_VALID_SHIFT)\n#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_VP_MDET_RX_MAX_INDEX 127\n#define I40E_VP_MDET_RX_VALID_SHIFT 0\n#define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT)\n#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */\n#define I40E_VP_MDET_TX_MAX_INDEX 127\n#define I40E_VP_MDET_TX_VALID_SHIFT 0\n#define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT)\n#define I40E_GLPM_WUMC 0x0006C800 /* Reset: POR */\n#define I40E_GLPM_WUMC_NOTCO_SHIFT 0\n#define I40E_GLPM_WUMC_NOTCO_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_NOTCO_SHIFT)\n#define I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT 1\n#define I40E_GLPM_WUMC_SRST_PIN_VAL_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT)\n#define I40E_GLPM_WUMC_ROL_MODE_SHIFT 2\n#define I40E_GLPM_WUMC_ROL_MODE_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_ROL_MODE_SHIFT)\n#define I40E_GLPM_WUMC_RESERVED_4_SHIFT 3\n#define I40E_GLPM_WUMC_RESERVED_4_MASK I40E_MASK(0x1FFF, I40E_GLPM_WUMC_RESERVED_4_SHIFT)\n#define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT 16\n#define I40E_GLPM_WUMC_MNG_WU_PF_MASK I40E_MASK(0xFFFF, I40E_GLPM_WUMC_MNG_WU_PF_SHIFT)\n#define I40E_PFPM_APM 0x000B8080 /* Reset: POR */\n#define I40E_PFPM_APM_APME_SHIFT 0\n#define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT)\n#define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ /* Reset: POR */\n#define I40E_PFPM_FHFT_LENGTH_MAX_INDEX 7\n#define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0\n#define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT)\n#define I40E_PFPM_WUC 0x0006B200 /* Reset: POR */\n#define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5\n#define I40E_PFPM_WUC_EN_APM_D0_MASK I40E_MASK(0x1, I40E_PFPM_WUC_EN_APM_D0_SHIFT)\n#define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */\n#define I40E_PFPM_WUFC_LNKC_SHIFT 0\n#define I40E_PFPM_WUFC_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_LNKC_SHIFT)\n#define I40E_PFPM_WUFC_MAG_SHIFT 1\n#define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT)\n#define I40E_PFPM_WUFC_MNG_SHIFT 3\n#define I40E_PFPM_WUFC_MNG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MNG_SHIFT)\n#define I40E_PFPM_WUFC_FLX0_ACT_SHIFT 4\n#define I40E_PFPM_WUFC_FLX0_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX0_ACT_SHIFT)\n#define I40E_PFPM_WUFC_FLX1_ACT_SHIFT 5\n#define I40E_PFPM_WUFC_FLX1_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX1_ACT_SHIFT)\n#define I40E_PFPM_WUFC_FLX2_ACT_SHIFT 6\n#define I40E_PFPM_WUFC_FLX2_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX2_ACT_SHIFT)\n#define I40E_PFPM_WUFC_FLX3_ACT_SHIFT 7\n#define I40E_PFPM_WUFC_FLX3_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX3_ACT_SHIFT)\n#define I40E_PFPM_WUFC_FLX4_ACT_SHIFT 8\n#define I40E_PFPM_WUFC_FLX4_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX4_ACT_SHIFT)\n#define I40E_PFPM_WUFC_FLX5_ACT_SHIFT 9\n#define I40E_PFPM_WUFC_FLX5_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX5_ACT_SHIFT)\n#define I40E_PFPM_WUFC_FLX6_ACT_SHIFT 10\n#define I40E_PFPM_WUFC_FLX6_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX6_ACT_SHIFT)\n#define I40E_PFPM_WUFC_FLX7_ACT_SHIFT 11\n#define I40E_PFPM_WUFC_FLX7_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_ACT_SHIFT)\n#define I40E_PFPM_WUFC_FLX0_SHIFT 16\n#define I40E_PFPM_WUFC_FLX0_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX0_SHIFT)\n#define I40E_PFPM_WUFC_FLX1_SHIFT 17\n#define I40E_PFPM_WUFC_FLX1_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX1_SHIFT)\n#define I40E_PFPM_WUFC_FLX2_SHIFT 18\n#define I40E_PFPM_WUFC_FLX2_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX2_SHIFT)\n#define I40E_PFPM_WUFC_FLX3_SHIFT 19\n#define I40E_PFPM_WUFC_FLX3_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX3_SHIFT)\n#define I40E_PFPM_WUFC_FLX4_SHIFT 20\n#define I40E_PFPM_WUFC_FLX4_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX4_SHIFT)\n#define I40E_PFPM_WUFC_FLX5_SHIFT 21\n#define I40E_PFPM_WUFC_FLX5_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX5_SHIFT)\n#define I40E_PFPM_WUFC_FLX6_SHIFT 22\n#define I40E_PFPM_WUFC_FLX6_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX6_SHIFT)\n#define I40E_PFPM_WUFC_FLX7_SHIFT 23\n#define I40E_PFPM_WUFC_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_SHIFT)\n#define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31\n#define I40E_PFPM_WUFC_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FW_RST_WK_SHIFT)\n#define I40E_PFPM_WUS 0x0006B600 /* Reset: POR */\n#define I40E_PFPM_WUS_LNKC_SHIFT 0\n#define I40E_PFPM_WUS_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUS_LNKC_SHIFT)\n#define I40E_PFPM_WUS_MAG_SHIFT 1\n#define I40E_PFPM_WUS_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUS_MAG_SHIFT)\n#define I40E_PFPM_WUS_PME_STATUS_SHIFT 2\n#define I40E_PFPM_WUS_PME_STATUS_MASK I40E_MASK(0x1, I40E_PFPM_WUS_PME_STATUS_SHIFT)\n#define I40E_PFPM_WUS_MNG_SHIFT 3\n#define I40E_PFPM_WUS_MNG_MASK I40E_MASK(0x1, I40E_PFPM_WUS_MNG_SHIFT)\n#define I40E_PFPM_WUS_FLX0_SHIFT 16\n#define I40E_PFPM_WUS_FLX0_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX0_SHIFT)\n#define I40E_PFPM_WUS_FLX1_SHIFT 17\n#define I40E_PFPM_WUS_FLX1_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX1_SHIFT)\n#define I40E_PFPM_WUS_FLX2_SHIFT 18\n#define I40E_PFPM_WUS_FLX2_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX2_SHIFT)\n#define I40E_PFPM_WUS_FLX3_SHIFT 19\n#define I40E_PFPM_WUS_FLX3_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX3_SHIFT)\n#define I40E_PFPM_WUS_FLX4_SHIFT 20\n#define I40E_PFPM_WUS_FLX4_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX4_SHIFT)\n#define I40E_PFPM_WUS_FLX5_SHIFT 21\n#define I40E_PFPM_WUS_FLX5_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX5_SHIFT)\n#define I40E_PFPM_WUS_FLX6_SHIFT 22\n#define I40E_PFPM_WUS_FLX6_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX6_SHIFT)\n#define I40E_PFPM_WUS_FLX7_SHIFT 23\n#define I40E_PFPM_WUS_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX7_SHIFT)\n#define I40E_PFPM_WUS_FW_RST_WK_SHIFT 31\n#define I40E_PFPM_WUS_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FW_RST_WK_SHIFT)\n#define I40E_PRTPM_FHFHR 0x0006C000 /* Reset: POR */\n#define I40E_PRTPM_FHFHR_UNICAST_SHIFT 0\n#define I40E_PRTPM_FHFHR_UNICAST_MASK I40E_MASK(0x1, I40E_PRTPM_FHFHR_UNICAST_SHIFT)\n#define I40E_PRTPM_FHFHR_MULTICAST_SHIFT 1\n#define I40E_PRTPM_FHFHR_MULTICAST_MASK I40E_MASK(0x1, I40E_PRTPM_FHFHR_MULTICAST_SHIFT)\n#define I40E_PRTPM_SAH(_i) (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */\n#define I40E_PRTPM_SAH_MAX_INDEX 3\n#define I40E_PRTPM_SAH_PFPM_SAH_SHIFT 0\n#define I40E_PRTPM_SAH_PFPM_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTPM_SAH_PFPM_SAH_SHIFT)\n#define I40E_PRTPM_SAH_PF_NUM_SHIFT 26\n#define I40E_PRTPM_SAH_PF_NUM_MASK I40E_MASK(0xF, I40E_PRTPM_SAH_PF_NUM_SHIFT)\n#define I40E_PRTPM_SAH_MC_MAG_EN_SHIFT 30\n#define I40E_PRTPM_SAH_MC_MAG_EN_MASK I40E_MASK(0x1, I40E_PRTPM_SAH_MC_MAG_EN_SHIFT)\n#define I40E_PRTPM_SAH_AV_SHIFT 31\n#define I40E_PRTPM_SAH_AV_MASK I40E_MASK(0x1, I40E_PRTPM_SAH_AV_SHIFT)\n#define I40E_PRTPM_SAL(_i) (0x001E4440 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */\n#define I40E_PRTPM_SAL_MAX_INDEX 3\n#define I40E_PRTPM_SAL_PFPM_SAL_SHIFT 0\n#define I40E_PRTPM_SAL_PFPM_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_SAL_PFPM_SAL_SHIFT)\n#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */\n#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0\n#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT)\n#define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */\n#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0\n#define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT)\n#define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */\n#define I40E_VF_ARQH1_ARQH_SHIFT 0\n#define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT)\n#define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */\n#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0\n#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT)\n#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28\n#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT)\n#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29\n#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT)\n#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30\n#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)\n#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31\n#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)\n#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */\n#define I40E_VF_ARQT1_ARQT_SHIFT 0\n#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)\n#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */\n#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0\n#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT)\n#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */\n#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0\n#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT)\n#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */\n#define I40E_VF_ATQH1_ATQH_SHIFT 0\n#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT)\n#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */\n#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0\n#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT)\n#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28\n#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT)\n#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29\n#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT)\n#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30\n#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)\n#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31\n#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)\n#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */\n#define I40E_VF_ATQT1_ATQT_SHIFT 0\n#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)\n#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */\n#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0\n#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)\n#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */\n#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0\n#define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT)\n#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1\n#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT)\n#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2\n#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT)\n#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3\n#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT)\n#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5\n#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT)\n#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24\n#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)\n#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25\n#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)\n#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31\n#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT)\n#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */\n#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15\n#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0\n#define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT)\n#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1\n#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT)\n#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2\n#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)\n#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3\n#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)\n#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5\n#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT)\n#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24\n#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)\n#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25\n#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)\n#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31\n#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT)\n#define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */\n#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25\n#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)\n#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30\n#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT)\n#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31\n#define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT)\n#define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */\n#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0\n#define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT)\n#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1\n#define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT)\n#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2\n#define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT)\n#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3\n#define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT)\n#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4\n#define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT)\n#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25\n#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT)\n#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30\n#define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT)\n#define I40E_VFINT_ICR01_SWINT_SHIFT 31\n#define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT)\n#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */\n#define I40E_VFINT_ITR01_MAX_INDEX 2\n#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0\n#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT)\n#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */\n#define I40E_VFINT_ITRN1_MAX_INDEX 2\n#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0\n#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT)\n#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */\n#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2\n#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)\n#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_QRX_TAIL1_MAX_INDEX 15\n#define I40E_QRX_TAIL1_TAIL_SHIFT 0\n#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT)\n#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */\n#define I40E_QTX_TAIL1_MAX_INDEX 15\n#define I40E_QTX_TAIL1_TAIL_SHIFT 0\n#define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT)\n#define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */\n#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0\n#define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT)\n#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */\n#define I40E_VFMSIX_TADD_MAX_INDEX 16\n#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0\n#define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT)\n#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2\n#define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT)\n#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */\n#define I40E_VFMSIX_TMSG_MAX_INDEX 16\n#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0\n#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT)\n#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */\n#define I40E_VFMSIX_TUADD_MAX_INDEX 16\n#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0\n#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT)\n#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */\n#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16\n#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0\n#define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT)\n#define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */\n#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0\n#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT)\n#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4\n#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT)\n#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8\n#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT)\n#define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */\n#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0\n#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT)\n#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4\n#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT)\n#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8\n#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)\n#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16\n#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)\n#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24\n#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)\n#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */\n#define I40E_VFQF_HENA_MAX_INDEX 1\n#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0\n#define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT)\n#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */\n#define I40E_VFQF_HKEY_MAX_INDEX 12\n#define I40E_VFQF_HKEY_KEY_0_SHIFT 0\n#define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT)\n#define I40E_VFQF_HKEY_KEY_1_SHIFT 8\n#define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT)\n#define I40E_VFQF_HKEY_KEY_2_SHIFT 16\n#define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT)\n#define I40E_VFQF_HKEY_KEY_3_SHIFT 24\n#define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT)\n#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */\n#define I40E_VFQF_HLUT_MAX_INDEX 15\n#define I40E_VFQF_HLUT_LUT0_SHIFT 0\n#define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT)\n#define I40E_VFQF_HLUT_LUT1_SHIFT 8\n#define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT)\n#define I40E_VFQF_HLUT_LUT2_SHIFT 16\n#define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT)\n#define I40E_VFQF_HLUT_LUT3_SHIFT 24\n#define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT)\n#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */\n#define I40E_VFQF_HREGION_MAX_INDEX 7\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT)\n#define I40E_VFQF_HREGION_REGION_0_SHIFT 1\n#define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT)\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT)\n#define I40E_VFQF_HREGION_REGION_1_SHIFT 5\n#define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT)\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT)\n#define I40E_VFQF_HREGION_REGION_2_SHIFT 9\n#define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT)\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT)\n#define I40E_VFQF_HREGION_REGION_3_SHIFT 13\n#define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT)\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT)\n#define I40E_VFQF_HREGION_REGION_4_SHIFT 17\n#define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT)\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT)\n#define I40E_VFQF_HREGION_REGION_5_SHIFT 21\n#define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT)\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT)\n#define I40E_VFQF_HREGION_REGION_6_SHIFT 25\n#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT)\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28\n#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)\n#define I40E_VFQF_HREGION_REGION_7_SHIFT 29\n#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)\n#endif /* _I40E_REGISTER_H_ */\n" }, { "path": "drivers/net/i40e/base/i40e_status.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _I40E_STATUS_H_\n#define _I40E_STATUS_H_\n\n/* Error Codes */\nenum i40e_status_code {\n\tI40E_SUCCESS\t\t\t\t= 0,\n\tI40E_ERR_NVM\t\t\t\t= -1,\n\tI40E_ERR_NVM_CHECKSUM\t\t\t= -2,\n\tI40E_ERR_PHY\t\t\t\t= -3,\n\tI40E_ERR_CONFIG\t\t\t\t= -4,\n\tI40E_ERR_PARAM\t\t\t\t= -5,\n\tI40E_ERR_MAC_TYPE\t\t\t= -6,\n\tI40E_ERR_UNKNOWN_PHY\t\t\t= -7,\n\tI40E_ERR_LINK_SETUP\t\t\t= -8,\n\tI40E_ERR_ADAPTER_STOPPED\t\t= -9,\n\tI40E_ERR_INVALID_MAC_ADDR\t\t= -10,\n\tI40E_ERR_DEVICE_NOT_SUPPORTED\t\t= -11,\n\tI40E_ERR_MASTER_REQUESTS_PENDING\t= -12,\n\tI40E_ERR_INVALID_LINK_SETTINGS\t\t= -13,\n\tI40E_ERR_AUTONEG_NOT_COMPLETE\t\t= -14,\n\tI40E_ERR_RESET_FAILED\t\t\t= -15,\n\tI40E_ERR_SWFW_SYNC\t\t\t= -16,\n\tI40E_ERR_NO_AVAILABLE_VSI\t\t= -17,\n\tI40E_ERR_NO_MEMORY\t\t\t= -18,\n\tI40E_ERR_BAD_PTR\t\t\t= -19,\n\tI40E_ERR_RING_FULL\t\t\t= -20,\n\tI40E_ERR_INVALID_PD_ID\t\t\t= -21,\n\tI40E_ERR_INVALID_QP_ID\t\t\t= -22,\n\tI40E_ERR_INVALID_CQ_ID\t\t\t= -23,\n\tI40E_ERR_INVALID_CEQ_ID\t\t\t= -24,\n\tI40E_ERR_INVALID_AEQ_ID\t\t\t= -25,\n\tI40E_ERR_INVALID_SIZE\t\t\t= -26,\n\tI40E_ERR_INVALID_ARP_INDEX\t\t= -27,\n\tI40E_ERR_INVALID_FPM_FUNC_ID\t\t= -28,\n\tI40E_ERR_QP_INVALID_MSG_SIZE\t\t= -29,\n\tI40E_ERR_QP_TOOMANY_WRS_POSTED\t\t= -30,\n\tI40E_ERR_INVALID_FRAG_COUNT\t\t= -31,\n\tI40E_ERR_QUEUE_EMPTY\t\t\t= -32,\n\tI40E_ERR_INVALID_ALIGNMENT\t\t= -33,\n\tI40E_ERR_FLUSHED_QUEUE\t\t\t= -34,\n\tI40E_ERR_INVALID_PUSH_PAGE_INDEX\t= -35,\n\tI40E_ERR_INVALID_IMM_DATA_SIZE\t\t= -36,\n\tI40E_ERR_TIMEOUT\t\t\t= -37,\n\tI40E_ERR_OPCODE_MISMATCH\t\t= -38,\n\tI40E_ERR_CQP_COMPL_ERROR\t\t= -39,\n\tI40E_ERR_INVALID_VF_ID\t\t\t= -40,\n\tI40E_ERR_INVALID_HMCFN_ID\t\t= -41,\n\tI40E_ERR_BACKING_PAGE_ERROR\t\t= -42,\n\tI40E_ERR_NO_PBLCHUNKS_AVAILABLE\t\t= -43,\n\tI40E_ERR_INVALID_PBLE_INDEX\t\t= -44,\n\tI40E_ERR_INVALID_SD_INDEX\t\t= -45,\n\tI40E_ERR_INVALID_PAGE_DESC_INDEX\t= -46,\n\tI40E_ERR_INVALID_SD_TYPE\t\t= -47,\n\tI40E_ERR_MEMCPY_FAILED\t\t\t= -48,\n\tI40E_ERR_INVALID_HMC_OBJ_INDEX\t\t= -49,\n\tI40E_ERR_INVALID_HMC_OBJ_COUNT\t\t= -50,\n\tI40E_ERR_INVALID_SRQ_ARM_LIMIT\t\t= -51,\n\tI40E_ERR_SRQ_ENABLED\t\t\t= -52,\n\tI40E_ERR_ADMIN_QUEUE_ERROR\t\t= -53,\n\tI40E_ERR_ADMIN_QUEUE_TIMEOUT\t\t= -54,\n\tI40E_ERR_BUF_TOO_SHORT\t\t\t= -55,\n\tI40E_ERR_ADMIN_QUEUE_FULL\t\t= -56,\n\tI40E_ERR_ADMIN_QUEUE_NO_WORK\t\t= -57,\n\tI40E_ERR_BAD_IWARP_CQE\t\t\t= -58,\n\tI40E_ERR_NVM_BLANK_MODE\t\t\t= -59,\n\tI40E_ERR_NOT_IMPLEMENTED\t\t= -60,\n\tI40E_ERR_PE_DOORBELL_NOT_ENABLED\t= -61,\n\tI40E_ERR_DIAG_TEST_FAILED\t\t= -62,\n\tI40E_ERR_NOT_READY\t\t\t= -63,\n\tI40E_NOT_SUPPORTED\t\t\t= -64,\n\tI40E_ERR_FIRMWARE_API_VERSION\t\t= -65,\n};\n\n#endif /* _I40E_STATUS_H_ */\n" }, { "path": "drivers/net/i40e/base/i40e_type.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _I40E_TYPE_H_\n#define _I40E_TYPE_H_\n\n#include \"i40e_status.h\"\n#include \"i40e_osdep.h\"\n#include \"i40e_register.h\"\n#include \"i40e_adminq.h\"\n#include \"i40e_hmc.h\"\n#include \"i40e_lan_hmc.h\"\n\n#define UNREFERENCED_XPARAMETER\n#define UNREFERENCED_1PARAMETER(_p) (_p);\n#define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);\n#define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);\n#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);\n#define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);\n\n/* Vendor ID */\n#define I40E_INTEL_VENDOR_ID\t\t0x8086\n\n/* Device IDs */\n#define I40E_DEV_ID_SFP_XL710\t\t0x1572\n#define I40E_DEV_ID_QEMU\t\t0x1574\n#define I40E_DEV_ID_KX_A\t\t0x157F\n#define I40E_DEV_ID_KX_B\t\t0x1580\n#define I40E_DEV_ID_KX_C\t\t0x1581\n#define I40E_DEV_ID_QSFP_A\t\t0x1583\n#define I40E_DEV_ID_QSFP_B\t\t0x1584\n#define I40E_DEV_ID_QSFP_C\t\t0x1585\n#define I40E_DEV_ID_10G_BASE_T\t\t0x1586\n#define I40E_DEV_ID_VF\t\t\t0x154C\n#define I40E_DEV_ID_VF_HV\t\t0x1571\n\n#define i40e_is_40G_device(d)\t\t((d) == I40E_DEV_ID_QSFP_A || \\\n\t\t\t\t\t (d) == I40E_DEV_ID_QSFP_B || \\\n\t\t\t\t\t (d) == I40E_DEV_ID_QSFP_C)\n\n#ifndef I40E_MASK\n/* I40E_MASK is a macro used on 32 bit registers */\n#define I40E_MASK(mask, shift) (mask << shift)\n#endif\n\n#define I40E_MAX_PF\t\t\t16\n#define I40E_MAX_PF_VSI\t\t\t64\n#define I40E_MAX_PF_QP\t\t\t128\n#define I40E_MAX_VSI_QP\t\t\t16\n#define I40E_MAX_VF_VSI\t\t\t3\n#define I40E_MAX_CHAINED_RX_BUFFERS\t5\n#define I40E_MAX_PF_UDP_OFFLOAD_PORTS\t16\n\n/* something less than 1 minute */\n#define I40E_HEARTBEAT_TIMEOUT\t\t(HZ * 50)\n\n/* Max default timeout in ms, */\n#define I40E_MAX_NVM_TIMEOUT\t\t18000\n\n/* Check whether address is multicast. */\n#define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))\n\n/* Check whether an address is broadcast. */\n#define I40E_IS_BROADCAST(address)\t\\\n\t((((u8 *)(address))[0] == ((u8)0xff)) && \\\n\t(((u8 *)(address))[1] == ((u8)0xff)))\n\n/* Switch from ms to the 1usec global time (this is the GTIME resolution) */\n#define I40E_MS_TO_GTIME(time)\t\t((time) * 1000)\n\n/* forward declaration */\nstruct i40e_hw;\ntypedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);\n\n#define I40E_ETH_LENGTH_OF_ADDRESS\t6\n/* Data type manipulation macros. */\n#define I40E_HI_DWORD(x)\t((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))\n#define I40E_LO_DWORD(x)\t((u32)((x) & 0xFFFFFFFF))\n\n#define I40E_HI_WORD(x)\t\t((u16)(((x) >> 16) & 0xFFFF))\n#define I40E_LO_WORD(x)\t\t((u16)((x) & 0xFFFF))\n\n#define I40E_HI_BYTE(x)\t\t((u8)(((x) >> 8) & 0xFF))\n#define I40E_LO_BYTE(x)\t\t((u8)((x) & 0xFF))\n\n/* Number of Transmit Descriptors must be a multiple of 8. */\n#define I40E_REQ_TX_DESCRIPTOR_MULTIPLE\t8\n/* Number of Receive Descriptors must be a multiple of 32 if\n * the number of descriptors is greater than 32.\n */\n#define I40E_REQ_RX_DESCRIPTOR_MULTIPLE\t32\n\n#define I40E_DESC_UNUSED(R)\t\\\n\t((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \\\n\t(R)->next_to_clean - (R)->next_to_use - 1)\n\n/* bitfields for Tx queue mapping in QTX_CTL */\n#define I40E_QTX_CTL_VF_QUEUE\t0x0\n#define I40E_QTX_CTL_VM_QUEUE\t0x1\n#define I40E_QTX_CTL_PF_QUEUE\t0x2\n\n/* debug masks - set these bits in hw->debug_mask to control output */\nenum i40e_debug_mask {\n\tI40E_DEBUG_INIT\t\t\t= 0x00000001,\n\tI40E_DEBUG_RELEASE\t\t= 0x00000002,\n\n\tI40E_DEBUG_LINK\t\t\t= 0x00000010,\n\tI40E_DEBUG_PHY\t\t\t= 0x00000020,\n\tI40E_DEBUG_HMC\t\t\t= 0x00000040,\n\tI40E_DEBUG_NVM\t\t\t= 0x00000080,\n\tI40E_DEBUG_LAN\t\t\t= 0x00000100,\n\tI40E_DEBUG_FLOW\t\t\t= 0x00000200,\n\tI40E_DEBUG_DCB\t\t\t= 0x00000400,\n\tI40E_DEBUG_DIAG\t\t\t= 0x00000800,\n\tI40E_DEBUG_FD\t\t\t= 0x00001000,\n\n\tI40E_DEBUG_AQ_MESSAGE\t\t= 0x01000000,\n\tI40E_DEBUG_AQ_DESCRIPTOR\t= 0x02000000,\n\tI40E_DEBUG_AQ_DESC_BUFFER\t= 0x04000000,\n\tI40E_DEBUG_AQ_COMMAND\t\t= 0x06000000,\n\tI40E_DEBUG_AQ\t\t\t= 0x0F000000,\n\n\tI40E_DEBUG_USER\t\t\t= 0xF0000000,\n\n\tI40E_DEBUG_ALL\t\t\t= 0xFFFFFFFF\n};\n\n/* PCI Bus Info */\n#define I40E_PCI_LINK_STATUS\t\t0xB2\n#define I40E_PCI_LINK_WIDTH\t\t0x3F0\n#define I40E_PCI_LINK_WIDTH_1\t\t0x10\n#define I40E_PCI_LINK_WIDTH_2\t\t0x20\n#define I40E_PCI_LINK_WIDTH_4\t\t0x40\n#define I40E_PCI_LINK_WIDTH_8\t\t0x80\n#define I40E_PCI_LINK_SPEED\t\t0xF\n#define I40E_PCI_LINK_SPEED_2500\t0x1\n#define I40E_PCI_LINK_SPEED_5000\t0x2\n#define I40E_PCI_LINK_SPEED_8000\t0x3\n\n/* Memory types */\nenum i40e_memset_type {\n\tI40E_NONDMA_MEM = 0,\n\tI40E_DMA_MEM\n};\n\n/* Memcpy types */\nenum i40e_memcpy_type {\n\tI40E_NONDMA_TO_NONDMA = 0,\n\tI40E_NONDMA_TO_DMA,\n\tI40E_DMA_TO_DMA,\n\tI40E_DMA_TO_NONDMA\n};\n\n/* These are structs for managing the hardware information and the operations.\n * The structures of function pointers are filled out at init time when we\n * know for sure exactly which hardware we're working with. This gives us the\n * flexibility of using the same main driver code but adapting to slightly\n * different hardware needs as new parts are developed. For this architecture,\n * the Firmware and AdminQ are intended to insulate the driver from most of the\n * future changes, but these structures will also do part of the job.\n */\nenum i40e_mac_type {\n\tI40E_MAC_UNKNOWN = 0,\n\tI40E_MAC_X710,\n\tI40E_MAC_XL710,\n\tI40E_MAC_VF,\n\tI40E_MAC_GENERIC,\n};\n\nenum i40e_media_type {\n\tI40E_MEDIA_TYPE_UNKNOWN = 0,\n\tI40E_MEDIA_TYPE_FIBER,\n\tI40E_MEDIA_TYPE_BASET,\n\tI40E_MEDIA_TYPE_BACKPLANE,\n\tI40E_MEDIA_TYPE_CX4,\n\tI40E_MEDIA_TYPE_DA,\n\tI40E_MEDIA_TYPE_VIRTUAL\n};\n\nenum i40e_fc_mode {\n\tI40E_FC_NONE = 0,\n\tI40E_FC_RX_PAUSE,\n\tI40E_FC_TX_PAUSE,\n\tI40E_FC_FULL,\n\tI40E_FC_PFC,\n\tI40E_FC_DEFAULT\n};\n\nenum i40e_set_fc_aq_failures {\n\tI40E_SET_FC_AQ_FAIL_NONE = 0,\n\tI40E_SET_FC_AQ_FAIL_GET = 1,\n\tI40E_SET_FC_AQ_FAIL_SET = 2,\n\tI40E_SET_FC_AQ_FAIL_UPDATE = 4,\n\tI40E_SET_FC_AQ_FAIL_SET_UPDATE = 6\n};\n\nenum i40e_vsi_type {\n\tI40E_VSI_MAIN = 0,\n\tI40E_VSI_VMDQ1,\n\tI40E_VSI_VMDQ2,\n\tI40E_VSI_CTRL,\n\tI40E_VSI_FCOE,\n\tI40E_VSI_MIRROR,\n\tI40E_VSI_SRIOV,\n\tI40E_VSI_FDIR,\n\tI40E_VSI_TYPE_UNKNOWN\n};\n\nenum i40e_queue_type {\n\tI40E_QUEUE_TYPE_RX = 0,\n\tI40E_QUEUE_TYPE_TX,\n\tI40E_QUEUE_TYPE_PE_CEQ,\n\tI40E_QUEUE_TYPE_UNKNOWN\n};\n\nstruct i40e_link_status {\n\tenum i40e_aq_phy_type phy_type;\n\tenum i40e_aq_link_speed link_speed;\n\tu8 link_info;\n\tu8 an_info;\n\tu8 ext_info;\n\tu8 loopback;\n\t/* is Link Status Event notification to SW enabled */\n\tbool lse_enable;\n\tu16 max_frame_size;\n\tbool crc_enable;\n\tu8 pacing;\n\tu8 requested_speeds;\n};\n\nstruct i40e_phy_info {\n\tstruct i40e_link_status link_info;\n\tstruct i40e_link_status link_info_old;\n\tu32 autoneg_advertised;\n\tu32 phy_id;\n\tu32 module_type;\n\tbool get_link_info;\n\tenum i40e_media_type media_type;\n};\n\n#define I40E_HW_CAP_MAX_GPIO\t\t\t30\n#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO\t\t0\n#define I40E_HW_CAP_MDIO_PORT_MODE_I2C\t\t1\n\n/* Capabilities of a PF or a VF or the whole device */\nstruct i40e_hw_capabilities {\n\tu32 switch_mode;\n#define I40E_NVM_IMAGE_TYPE_EVB\t\t0x0\n#define I40E_NVM_IMAGE_TYPE_CLOUD\t0x2\n#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD\t0x3\n\n\tu32 management_mode;\n\tu32 npar_enable;\n\tu32 os2bmc;\n\tu32 valid_functions;\n\tbool sr_iov_1_1;\n\tbool vmdq;\n\tbool evb_802_1_qbg; /* Edge Virtual Bridging */\n\tbool evb_802_1_qbh; /* Bridge Port Extension */\n\tbool dcb;\n\tbool fcoe;\n\tbool iscsi; /* Indicates iSCSI enabled */\n\tbool mfp_mode_1;\n\tbool mgmt_cem;\n\tbool ieee_1588;\n\tbool iwarp;\n\tbool fd;\n\tu32 fd_filters_guaranteed;\n\tu32 fd_filters_best_effort;\n\tbool rss;\n\tu32 rss_table_size;\n\tu32 rss_table_entry_width;\n\tbool led[I40E_HW_CAP_MAX_GPIO];\n\tbool sdp[I40E_HW_CAP_MAX_GPIO];\n\tu32 nvm_image_type;\n\tu32 num_flow_director_filters;\n\tu32 num_vfs;\n\tu32 vf_base_id;\n\tu32 num_vsis;\n\tu32 num_rx_qp;\n\tu32 num_tx_qp;\n\tu32 base_queue;\n\tu32 num_msix_vectors;\n\tu32 num_msix_vectors_vf;\n\tu32 led_pin_num;\n\tu32 sdp_pin_num;\n\tu32 mdio_port_num;\n\tu32 mdio_port_mode;\n\tu8 rx_buf_chain_len;\n\tu32 enabled_tcmap;\n\tu32 maxtc;\n};\n\nstruct i40e_mac_info {\n\tenum i40e_mac_type type;\n\tu8 addr[I40E_ETH_LENGTH_OF_ADDRESS];\n\tu8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];\n\tu8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];\n\tu8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS];\n\tu16 max_fcoeq;\n};\n\nenum i40e_aq_resources_ids {\n\tI40E_NVM_RESOURCE_ID = 1\n};\n\nenum i40e_aq_resource_access_type {\n\tI40E_RESOURCE_READ = 1,\n\tI40E_RESOURCE_WRITE\n};\n\nstruct i40e_nvm_info {\n\tu64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */\n\tu32 timeout; /* [ms] */\n\tu16 sr_size; /* Shadow RAM size in words */\n\tbool blank_nvm_mode; /* is NVM empty (no FW present)*/\n\tu16 version; /* NVM package version */\n\tu32 eetrack; /* NVM data version */\n};\n\n/* definitions used in NVM update support */\n\nenum i40e_nvmupd_cmd {\n\tI40E_NVMUPD_INVALID,\n\tI40E_NVMUPD_READ_CON,\n\tI40E_NVMUPD_READ_SNT,\n\tI40E_NVMUPD_READ_LCB,\n\tI40E_NVMUPD_READ_SA,\n\tI40E_NVMUPD_WRITE_ERA,\n\tI40E_NVMUPD_WRITE_CON,\n\tI40E_NVMUPD_WRITE_SNT,\n\tI40E_NVMUPD_WRITE_LCB,\n\tI40E_NVMUPD_WRITE_SA,\n\tI40E_NVMUPD_CSUM_CON,\n\tI40E_NVMUPD_CSUM_SA,\n\tI40E_NVMUPD_CSUM_LCB,\n};\n\nenum i40e_nvmupd_state {\n\tI40E_NVMUPD_STATE_INIT,\n\tI40E_NVMUPD_STATE_READING,\n\tI40E_NVMUPD_STATE_WRITING\n};\n\n/* nvm_access definition and its masks/shifts need to be accessible to\n * application, core driver, and shared code. Where is the right file?\n */\n#define I40E_NVM_READ\t0xB\n#define I40E_NVM_WRITE\t0xC\n\n#define I40E_NVM_MOD_PNT_MASK 0xFF\n\n#define I40E_NVM_TRANS_SHIFT\t8\n#define I40E_NVM_TRANS_MASK\t(0xf << I40E_NVM_TRANS_SHIFT)\n#define I40E_NVM_CON\t\t0x0\n#define I40E_NVM_SNT\t\t0x1\n#define I40E_NVM_LCB\t\t0x2\n#define I40E_NVM_SA\t\t(I40E_NVM_SNT | I40E_NVM_LCB)\n#define I40E_NVM_ERA\t\t0x4\n#define I40E_NVM_CSUM\t\t0x8\n\n#define I40E_NVM_ADAPT_SHIFT\t16\n#define I40E_NVM_ADAPT_MASK\t(0xffffULL << I40E_NVM_ADAPT_SHIFT)\n\n#define I40E_NVMUPD_MAX_DATA\t4096\n#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */\n\nstruct i40e_nvm_access {\n\tu32 command;\n\tu32 config;\n\tu32 offset;\t/* in bytes */\n\tu32 data_size;\t/* in bytes */\n\tu8 data[1];\n};\n\n/* PCI bus types */\nenum i40e_bus_type {\n\ti40e_bus_type_unknown = 0,\n\ti40e_bus_type_pci,\n\ti40e_bus_type_pcix,\n\ti40e_bus_type_pci_express,\n\ti40e_bus_type_reserved\n};\n\n/* PCI bus speeds */\nenum i40e_bus_speed {\n\ti40e_bus_speed_unknown\t= 0,\n\ti40e_bus_speed_33\t= 33,\n\ti40e_bus_speed_66\t= 66,\n\ti40e_bus_speed_100\t= 100,\n\ti40e_bus_speed_120\t= 120,\n\ti40e_bus_speed_133\t= 133,\n\ti40e_bus_speed_2500\t= 2500,\n\ti40e_bus_speed_5000\t= 5000,\n\ti40e_bus_speed_8000\t= 8000,\n\ti40e_bus_speed_reserved\n};\n\n/* PCI bus widths */\nenum i40e_bus_width {\n\ti40e_bus_width_unknown\t= 0,\n\ti40e_bus_width_pcie_x1\t= 1,\n\ti40e_bus_width_pcie_x2\t= 2,\n\ti40e_bus_width_pcie_x4\t= 4,\n\ti40e_bus_width_pcie_x8\t= 8,\n\ti40e_bus_width_32\t= 32,\n\ti40e_bus_width_64\t= 64,\n\ti40e_bus_width_reserved\n};\n\n/* Bus parameters */\nstruct i40e_bus_info {\n\tenum i40e_bus_speed speed;\n\tenum i40e_bus_width width;\n\tenum i40e_bus_type type;\n\n\tu16 func;\n\tu16 device;\n\tu16 lan_id;\n};\n\n/* Flow control (FC) parameters */\nstruct i40e_fc_info {\n\tenum i40e_fc_mode current_mode; /* FC mode in effect */\n\tenum i40e_fc_mode requested_mode; /* FC mode requested by caller */\n};\n\n#define I40E_MAX_TRAFFIC_CLASS\t\t8\n#define I40E_MAX_USER_PRIORITY\t\t8\n#define I40E_DCBX_MAX_APPS\t\t32\n#define I40E_LLDPDU_SIZE\t\t1500\n#define I40E_TLV_STATUS_OPER\t\t0x1\n#define I40E_TLV_STATUS_SYNC\t\t0x2\n#define I40E_TLV_STATUS_ERR\t\t0x4\n#define I40E_CEE_OPER_MAX_APPS\t\t3\n#define I40E_APP_PROTOID_FCOE\t\t0x8906\n#define I40E_APP_PROTOID_ISCSI\t\t0x0cbc\n#define I40E_APP_PROTOID_FIP\t\t0x8914\n#define I40E_APP_SEL_ETHTYPE\t\t0x1\n#define I40E_APP_SEL_TCPIP\t\t0x2\n\n/* CEE or IEEE 802.1Qaz ETS Configuration data */\nstruct i40e_dcb_ets_config {\n\tu8 willing;\n\tu8 cbs;\n\tu8 maxtcs;\n\tu8 prioritytable[I40E_MAX_TRAFFIC_CLASS];\n\tu8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];\n\tu8 tsatable[I40E_MAX_TRAFFIC_CLASS];\n};\n\n/* CEE or IEEE 802.1Qaz PFC Configuration data */\nstruct i40e_dcb_pfc_config {\n\tu8 willing;\n\tu8 mbc;\n\tu8 pfccap;\n\tu8 pfcenable;\n};\n\n/* CEE or IEEE 802.1Qaz Application Priority data */\nstruct i40e_dcb_app_priority_table {\n\tu8 priority;\n\tu8 selector;\n\tu16 protocolid;\n};\n\nstruct i40e_dcbx_config {\n\tu8 dcbx_mode;\n#define I40E_DCBX_MODE_CEE\t0x1\n#define I40E_DCBX_MODE_IEEE\t0x2\n\tu32 numapps;\n\tstruct i40e_dcb_ets_config etscfg;\n\tstruct i40e_dcb_ets_config etsrec;\n\tstruct i40e_dcb_pfc_config pfc;\n\tstruct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];\n};\n\n/* Port hardware description */\nstruct i40e_hw {\n\tu8 *hw_addr;\n\tvoid *back;\n\n\t/* subsystem structs */\n\tstruct i40e_phy_info phy;\n\tstruct i40e_mac_info mac;\n\tstruct i40e_bus_info bus;\n\tstruct i40e_nvm_info nvm;\n\tstruct i40e_fc_info fc;\n\n\t/* pci info */\n\tu16 device_id;\n\tu16 vendor_id;\n\tu16 subsystem_device_id;\n\tu16 subsystem_vendor_id;\n\tu8 revision_id;\n\tu8 port;\n\tbool adapter_stopped;\n\n\t/* capabilities for entire device and PCI func */\n\tstruct i40e_hw_capabilities dev_caps;\n\tstruct i40e_hw_capabilities func_caps;\n\n\t/* Flow Director shared filter space */\n\tu16 fdir_shared_filter_count;\n\n\t/* device profile info */\n\tu8 pf_id;\n\tu16 main_vsi_seid;\n\n\t/* for multi-function MACs */\n\tu16 partition_id;\n\tu16 num_partitions;\n\tu16 num_ports;\n\n\t/* Closest numa node to the device */\n\tu16 numa_node;\n\n\t/* Admin Queue info */\n\tstruct i40e_adminq_info aq;\n\n\t/* state of nvm update process */\n\tenum i40e_nvmupd_state nvmupd_state;\n\n\t/* HMC info */\n\tstruct i40e_hmc_info hmc; /* HMC info struct */\n\n\t/* LLDP/DCBX Status */\n\tu16 dcbx_status;\n\n\t/* DCBX info */\n\tstruct i40e_dcbx_config local_dcbx_config;\n\tstruct i40e_dcbx_config remote_dcbx_config;\n\n\t/* debug mask */\n\tu32 debug_mask;\n};\n\nstatic inline bool i40e_is_vf(struct i40e_hw *hw)\n{\n\treturn hw->mac.type == I40E_MAC_VF;\n}\n\nstruct i40e_driver_version {\n\tu8 major_version;\n\tu8 minor_version;\n\tu8 build_version;\n\tu8 subbuild_version;\n\tu8 driver_string[32];\n};\n\n/* RX Descriptors */\nunion i40e_16byte_rx_desc {\n\tstruct {\n\t\t__le64 pkt_addr; /* Packet buffer address */\n\t\t__le64 hdr_addr; /* Header buffer address */\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__le16 mirroring_status;\n\t\t\t\t\t__le16 fcoe_ctx_id;\n\t\t\t\t} mirr_fcoe;\n\t\t\t\t__le16 l2tag1;\n\t\t\t} lo_dword;\n\t\t\tunion {\n\t\t\t\t__le32 rss; /* RSS Hash */\n\t\t\t\t__le32 fd_id; /* Flow director filter id */\n\t\t\t\t__le32 fcoe_param; /* FCoE DDP Context id */\n\t\t\t} hi_dword;\n\t\t} qword0;\n\t\tstruct {\n\t\t\t/* ext status/error/pktype/length */\n\t\t\t__le64 status_error_len;\n\t\t} qword1;\n\t} wb; /* writeback */\n};\n\nunion i40e_32byte_rx_desc {\n\tstruct {\n\t\t__le64 pkt_addr; /* Packet buffer address */\n\t\t__le64 hdr_addr; /* Header buffer address */\n\t\t\t/* bit 0 of hdr_buffer_addr is DD bit */\n\t\t__le64 rsvd1;\n\t\t__le64 rsvd2;\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\tstruct {\n\t\t\t\tunion {\n\t\t\t\t\t__le16 mirroring_status;\n\t\t\t\t\t__le16 fcoe_ctx_id;\n\t\t\t\t} mirr_fcoe;\n\t\t\t\t__le16 l2tag1;\n\t\t\t} lo_dword;\n\t\t\tunion {\n\t\t\t\t__le32 rss; /* RSS Hash */\n\t\t\t\t__le32 fcoe_param; /* FCoE DDP Context id */\n\t\t\t\t/* Flow director filter id in case of\n\t\t\t\t * Programming status desc WB\n\t\t\t\t */\n\t\t\t\t__le32 fd_id;\n\t\t\t} hi_dword;\n\t\t} qword0;\n\t\tstruct {\n\t\t\t/* status/error/pktype/length */\n\t\t\t__le64 status_error_len;\n\t\t} qword1;\n\t\tstruct {\n\t\t\t__le16 ext_status; /* extended status */\n\t\t\t__le16 rsvd;\n\t\t\t__le16 l2tag2_1;\n\t\t\t__le16 l2tag2_2;\n\t\t} qword2;\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\t__le32 flex_bytes_lo;\n\t\t\t\t__le32 pe_status;\n\t\t\t} lo_dword;\n\t\t\tunion {\n\t\t\t\t__le32 flex_bytes_hi;\n\t\t\t\t__le32 fd_id;\n\t\t\t} hi_dword;\n\t\t} qword3;\n\t} wb; /* writeback */\n};\n\n#define I40E_RXD_QW0_MIRROR_STATUS_SHIFT\t8\n#define I40E_RXD_QW0_MIRROR_STATUS_MASK\t(0x3FUL << \\\n\t\t\t\t\t I40E_RXD_QW0_MIRROR_STATUS_SHIFT)\n#define I40E_RXD_QW0_FCOEINDX_SHIFT\t0\n#define I40E_RXD_QW0_FCOEINDX_MASK\t(0xFFFUL << \\\n\t\t\t\t\t I40E_RXD_QW0_FCOEINDX_SHIFT)\n\nenum i40e_rx_desc_status_bits {\n\t/* Note: These are predefined bit offsets */\n\tI40E_RX_DESC_STATUS_DD_SHIFT\t\t= 0,\n\tI40E_RX_DESC_STATUS_EOF_SHIFT\t\t= 1,\n\tI40E_RX_DESC_STATUS_L2TAG1P_SHIFT\t= 2,\n\tI40E_RX_DESC_STATUS_L3L4P_SHIFT\t\t= 3,\n\tI40E_RX_DESC_STATUS_CRCP_SHIFT\t\t= 4,\n\tI40E_RX_DESC_STATUS_TSYNINDX_SHIFT\t= 5, /* 2 BITS */\n\tI40E_RX_DESC_STATUS_TSYNVALID_SHIFT\t= 7,\n\tI40E_RX_DESC_STATUS_RESERVED1_SHIFT\t= 8,\n\n\tI40E_RX_DESC_STATUS_UMBCAST_SHIFT\t= 9, /* 2 BITS */\n\tI40E_RX_DESC_STATUS_FLM_SHIFT\t\t= 11,\n\tI40E_RX_DESC_STATUS_FLTSTAT_SHIFT\t= 12, /* 2 BITS */\n\tI40E_RX_DESC_STATUS_LPBK_SHIFT\t\t= 14,\n\tI40E_RX_DESC_STATUS_IPV6EXADD_SHIFT\t= 15,\n\tI40E_RX_DESC_STATUS_RESERVED2_SHIFT\t= 16, /* 2 BITS */\n\tI40E_RX_DESC_STATUS_UDP_0_SHIFT\t\t= 18,\n\tI40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */\n};\n\n#define I40E_RXD_QW1_STATUS_SHIFT\t0\n#define I40E_RXD_QW1_STATUS_MASK\t(((1 << I40E_RX_DESC_STATUS_LAST) - 1) << \\\n\t\t\t\t\t I40E_RXD_QW1_STATUS_SHIFT)\n\n#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT\n#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK\t(0x3UL << \\\n\t\t\t\t\t I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)\n\n#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT\n#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK\t(0x1UL << \\\n\t\t\t\t\t I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)\n\n#define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT\tI40E_RX_DESC_STATUS_UMBCAST\n#define I40E_RXD_QW1_STATUS_UMBCAST_MASK\t(0x3UL << \\\n\t\t\t\t\t I40E_RXD_QW1_STATUS_UMBCAST_SHIFT)\n\nenum i40e_rx_desc_fltstat_values {\n\tI40E_RX_DESC_FLTSTAT_NO_DATA\t= 0,\n\tI40E_RX_DESC_FLTSTAT_RSV_FD_ID\t= 1, /* 16byte desc? FD_ID : RSV */\n\tI40E_RX_DESC_FLTSTAT_RSV\t= 2,\n\tI40E_RX_DESC_FLTSTAT_RSS_HASH\t= 3,\n};\n\n#define I40E_RXD_PACKET_TYPE_UNICAST\t0\n#define I40E_RXD_PACKET_TYPE_MULTICAST\t1\n#define I40E_RXD_PACKET_TYPE_BROADCAST\t2\n#define I40E_RXD_PACKET_TYPE_MIRRORED\t3\n\n#define I40E_RXD_QW1_ERROR_SHIFT\t19\n#define I40E_RXD_QW1_ERROR_MASK\t\t(0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)\n\nenum i40e_rx_desc_error_bits {\n\t/* Note: These are predefined bit offsets */\n\tI40E_RX_DESC_ERROR_RXE_SHIFT\t\t= 0,\n\tI40E_RX_DESC_ERROR_RECIPE_SHIFT\t\t= 1,\n\tI40E_RX_DESC_ERROR_HBO_SHIFT\t\t= 2,\n\tI40E_RX_DESC_ERROR_L3L4E_SHIFT\t\t= 3, /* 3 BITS */\n\tI40E_RX_DESC_ERROR_IPE_SHIFT\t\t= 3,\n\tI40E_RX_DESC_ERROR_L4E_SHIFT\t\t= 4,\n\tI40E_RX_DESC_ERROR_EIPE_SHIFT\t\t= 5,\n\tI40E_RX_DESC_ERROR_OVERSIZE_SHIFT\t= 6,\n\tI40E_RX_DESC_ERROR_PPRS_SHIFT\t\t= 7\n};\n\nenum i40e_rx_desc_error_l3l4e_fcoe_masks {\n\tI40E_RX_DESC_ERROR_L3L4E_NONE\t\t= 0,\n\tI40E_RX_DESC_ERROR_L3L4E_PROT\t\t= 1,\n\tI40E_RX_DESC_ERROR_L3L4E_FC\t\t= 2,\n\tI40E_RX_DESC_ERROR_L3L4E_DMAC_ERR\t= 3,\n\tI40E_RX_DESC_ERROR_L3L4E_DMAC_WARN\t= 4\n};\n\n#define I40E_RXD_QW1_PTYPE_SHIFT\t30\n#define I40E_RXD_QW1_PTYPE_MASK\t\t(0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)\n\n/* Packet type non-ip values */\nenum i40e_rx_l2_ptype {\n\tI40E_RX_PTYPE_L2_RESERVED\t\t\t= 0,\n\tI40E_RX_PTYPE_L2_MAC_PAY2\t\t\t= 1,\n\tI40E_RX_PTYPE_L2_TIMESYNC_PAY2\t\t\t= 2,\n\tI40E_RX_PTYPE_L2_FIP_PAY2\t\t\t= 3,\n\tI40E_RX_PTYPE_L2_OUI_PAY2\t\t\t= 4,\n\tI40E_RX_PTYPE_L2_MACCNTRL_PAY2\t\t\t= 5,\n\tI40E_RX_PTYPE_L2_LLDP_PAY2\t\t\t= 6,\n\tI40E_RX_PTYPE_L2_ECP_PAY2\t\t\t= 7,\n\tI40E_RX_PTYPE_L2_EVB_PAY2\t\t\t= 8,\n\tI40E_RX_PTYPE_L2_QCN_PAY2\t\t\t= 9,\n\tI40E_RX_PTYPE_L2_EAPOL_PAY2\t\t\t= 10,\n\tI40E_RX_PTYPE_L2_ARP\t\t\t\t= 11,\n\tI40E_RX_PTYPE_L2_FCOE_PAY3\t\t\t= 12,\n\tI40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3\t\t= 13,\n\tI40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3\t\t= 14,\n\tI40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3\t\t= 15,\n\tI40E_RX_PTYPE_L2_FCOE_FCOTHER_PA\t\t= 16,\n\tI40E_RX_PTYPE_L2_FCOE_VFT_PAY3\t\t\t= 17,\n\tI40E_RX_PTYPE_L2_FCOE_VFT_FCDATA\t\t= 18,\n\tI40E_RX_PTYPE_L2_FCOE_VFT_FCRDY\t\t\t= 19,\n\tI40E_RX_PTYPE_L2_FCOE_VFT_FCRSP\t\t\t= 20,\n\tI40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER\t\t= 21,\n\tI40E_RX_PTYPE_GRENAT4_MAC_PAY3\t\t\t= 58,\n\tI40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4\t= 87,\n\tI40E_RX_PTYPE_GRENAT6_MAC_PAY3\t\t\t= 124,\n\tI40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4\t= 153\n};\n\nstruct i40e_rx_ptype_decoded {\n\tu32 ptype:8;\n\tu32 known:1;\n\tu32 outer_ip:1;\n\tu32 outer_ip_ver:1;\n\tu32 outer_frag:1;\n\tu32 tunnel_type:3;\n\tu32 tunnel_end_prot:2;\n\tu32 tunnel_end_frag:1;\n\tu32 inner_prot:4;\n\tu32 payload_layer:3;\n};\n\nenum i40e_rx_ptype_outer_ip {\n\tI40E_RX_PTYPE_OUTER_L2\t= 0,\n\tI40E_RX_PTYPE_OUTER_IP\t= 1\n};\n\nenum i40e_rx_ptype_outer_ip_ver {\n\tI40E_RX_PTYPE_OUTER_NONE\t= 0,\n\tI40E_RX_PTYPE_OUTER_IPV4\t= 0,\n\tI40E_RX_PTYPE_OUTER_IPV6\t= 1\n};\n\nenum i40e_rx_ptype_outer_fragmented {\n\tI40E_RX_PTYPE_NOT_FRAG\t= 0,\n\tI40E_RX_PTYPE_FRAG\t= 1\n};\n\nenum i40e_rx_ptype_tunnel_type {\n\tI40E_RX_PTYPE_TUNNEL_NONE\t\t= 0,\n\tI40E_RX_PTYPE_TUNNEL_IP_IP\t\t= 1,\n\tI40E_RX_PTYPE_TUNNEL_IP_GRENAT\t\t= 2,\n\tI40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC\t= 3,\n\tI40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN\t= 4,\n};\n\nenum i40e_rx_ptype_tunnel_end_prot {\n\tI40E_RX_PTYPE_TUNNEL_END_NONE\t= 0,\n\tI40E_RX_PTYPE_TUNNEL_END_IPV4\t= 1,\n\tI40E_RX_PTYPE_TUNNEL_END_IPV6\t= 2,\n};\n\nenum i40e_rx_ptype_inner_prot {\n\tI40E_RX_PTYPE_INNER_PROT_NONE\t\t= 0,\n\tI40E_RX_PTYPE_INNER_PROT_UDP\t\t= 1,\n\tI40E_RX_PTYPE_INNER_PROT_TCP\t\t= 2,\n\tI40E_RX_PTYPE_INNER_PROT_SCTP\t\t= 3,\n\tI40E_RX_PTYPE_INNER_PROT_ICMP\t\t= 4,\n\tI40E_RX_PTYPE_INNER_PROT_TIMESYNC\t= 5\n};\n\nenum i40e_rx_ptype_payload_layer {\n\tI40E_RX_PTYPE_PAYLOAD_LAYER_NONE\t= 0,\n\tI40E_RX_PTYPE_PAYLOAD_LAYER_PAY2\t= 1,\n\tI40E_RX_PTYPE_PAYLOAD_LAYER_PAY3\t= 2,\n\tI40E_RX_PTYPE_PAYLOAD_LAYER_PAY4\t= 3,\n};\n\n#define I40E_RX_PTYPE_BIT_MASK\t\t0x0FFFFFFF\n#define I40E_RX_PTYPE_SHIFT\t\t56\n\n#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT\t38\n#define I40E_RXD_QW1_LENGTH_PBUF_MASK\t(0x3FFFULL << \\\n\t\t\t\t\t I40E_RXD_QW1_LENGTH_PBUF_SHIFT)\n\n#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT\t52\n#define I40E_RXD_QW1_LENGTH_HBUF_MASK\t(0x7FFULL << \\\n\t\t\t\t\t I40E_RXD_QW1_LENGTH_HBUF_SHIFT)\n\n#define I40E_RXD_QW1_LENGTH_SPH_SHIFT\t63\n#define I40E_RXD_QW1_LENGTH_SPH_MASK\t(0x1ULL << \\\n\t\t\t\t\t I40E_RXD_QW1_LENGTH_SPH_SHIFT)\n\n#define I40E_RXD_QW1_NEXTP_SHIFT\t38\n#define I40E_RXD_QW1_NEXTP_MASK\t\t(0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT)\n\n#define I40E_RXD_QW2_EXT_STATUS_SHIFT\t0\n#define I40E_RXD_QW2_EXT_STATUS_MASK\t(0xFFFFFUL << \\\n\t\t\t\t\t I40E_RXD_QW2_EXT_STATUS_SHIFT)\n\nenum i40e_rx_desc_ext_status_bits {\n\t/* Note: These are predefined bit offsets */\n\tI40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT\t= 0,\n\tI40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT\t= 1,\n\tI40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT\t= 2, /* 2 BITS */\n\tI40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT\t= 4, /* 2 BITS */\n\tI40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT\t= 9,\n\tI40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT\t= 10,\n\tI40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT\t= 11,\n};\n\n#define I40E_RXD_QW2_L2TAG2_SHIFT\t0\n#define I40E_RXD_QW2_L2TAG2_MASK\t(0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT)\n\n#define I40E_RXD_QW2_L2TAG3_SHIFT\t16\n#define I40E_RXD_QW2_L2TAG3_MASK\t(0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT)\n\nenum i40e_rx_desc_pe_status_bits {\n\t/* Note: These are predefined bit offsets */\n\tI40E_RX_DESC_PE_STATUS_QPID_SHIFT\t= 0, /* 18 BITS */\n\tI40E_RX_DESC_PE_STATUS_L4PORT_SHIFT\t= 0, /* 16 BITS */\n\tI40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT\t= 16, /* 8 BITS */\n\tI40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT\t= 24,\n\tI40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT\t= 25,\n\tI40E_RX_DESC_PE_STATUS_PORTV_SHIFT\t= 26,\n\tI40E_RX_DESC_PE_STATUS_URG_SHIFT\t= 27,\n\tI40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT\t= 28,\n\tI40E_RX_DESC_PE_STATUS_IPOPT_SHIFT\t= 29\n};\n\n#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT\t\t38\n#define I40E_RX_PROG_STATUS_DESC_LENGTH\t\t\t0x2000000\n\n#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT\t2\n#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK\t(0x7UL << \\\n\t\t\t\tI40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)\n\n#define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT\t0\n#define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK\t(0x7FFFUL << \\\n\t\t\t\tI40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)\n\n#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT\t19\n#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK\t\t(0x3FUL << \\\n\t\t\t\tI40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)\n\nenum i40e_rx_prog_status_desc_status_bits {\n\t/* Note: These are predefined bit offsets */\n\tI40E_RX_PROG_STATUS_DESC_DD_SHIFT\t= 0,\n\tI40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT\t= 2 /* 3 BITS */\n};\n\nenum i40e_rx_prog_status_desc_prog_id_masks {\n\tI40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS\t= 1,\n\tI40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS\t= 2,\n\tI40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS\t= 4,\n};\n\nenum i40e_rx_prog_status_desc_error_bits {\n\t/* Note: These are predefined bit offsets */\n\tI40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT\t= 0,\n\tI40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT\t= 1,\n\tI40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT\t= 2,\n\tI40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT\t= 3\n};\n\n#define I40E_TWO_BIT_MASK\t0x3\n#define I40E_THREE_BIT_MASK\t0x7\n#define I40E_FOUR_BIT_MASK\t0xF\n#define I40E_EIGHTEEN_BIT_MASK\t0x3FFFF\n\n/* TX Descriptor */\nstruct i40e_tx_desc {\n\t__le64 buffer_addr; /* Address of descriptor's data buf */\n\t__le64 cmd_type_offset_bsz;\n};\n\n#define I40E_TXD_QW1_DTYPE_SHIFT\t0\n#define I40E_TXD_QW1_DTYPE_MASK\t\t(0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)\n\nenum i40e_tx_desc_dtype_value {\n\tI40E_TX_DESC_DTYPE_DATA\t\t= 0x0,\n\tI40E_TX_DESC_DTYPE_NOP\t\t= 0x1, /* same as Context desc */\n\tI40E_TX_DESC_DTYPE_CONTEXT\t= 0x1,\n\tI40E_TX_DESC_DTYPE_FCOE_CTX\t= 0x2,\n\tI40E_TX_DESC_DTYPE_FILTER_PROG\t= 0x8,\n\tI40E_TX_DESC_DTYPE_DDP_CTX\t= 0x9,\n\tI40E_TX_DESC_DTYPE_FLEX_DATA\t= 0xB,\n\tI40E_TX_DESC_DTYPE_FLEX_CTX_1\t= 0xC,\n\tI40E_TX_DESC_DTYPE_FLEX_CTX_2\t= 0xD,\n\tI40E_TX_DESC_DTYPE_DESC_DONE\t= 0xF\n};\n\n#define I40E_TXD_QW1_CMD_SHIFT\t4\n#define I40E_TXD_QW1_CMD_MASK\t(0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)\n\nenum i40e_tx_desc_cmd_bits {\n\tI40E_TX_DESC_CMD_EOP\t\t\t= 0x0001,\n\tI40E_TX_DESC_CMD_RS\t\t\t= 0x0002,\n\tI40E_TX_DESC_CMD_ICRC\t\t\t= 0x0004,\n\tI40E_TX_DESC_CMD_IL2TAG1\t\t= 0x0008,\n\tI40E_TX_DESC_CMD_DUMMY\t\t\t= 0x0010,\n\tI40E_TX_DESC_CMD_IIPT_NONIP\t\t= 0x0000, /* 2 BITS */\n\tI40E_TX_DESC_CMD_IIPT_IPV6\t\t= 0x0020, /* 2 BITS */\n\tI40E_TX_DESC_CMD_IIPT_IPV4\t\t= 0x0040, /* 2 BITS */\n\tI40E_TX_DESC_CMD_IIPT_IPV4_CSUM\t\t= 0x0060, /* 2 BITS */\n\tI40E_TX_DESC_CMD_FCOET\t\t\t= 0x0080,\n\tI40E_TX_DESC_CMD_L4T_EOFT_UNK\t\t= 0x0000, /* 2 BITS */\n\tI40E_TX_DESC_CMD_L4T_EOFT_TCP\t\t= 0x0100, /* 2 BITS */\n\tI40E_TX_DESC_CMD_L4T_EOFT_SCTP\t\t= 0x0200, /* 2 BITS */\n\tI40E_TX_DESC_CMD_L4T_EOFT_UDP\t\t= 0x0300, /* 2 BITS */\n\tI40E_TX_DESC_CMD_L4T_EOFT_EOF_N\t\t= 0x0000, /* 2 BITS */\n\tI40E_TX_DESC_CMD_L4T_EOFT_EOF_T\t\t= 0x0100, /* 2 BITS */\n\tI40E_TX_DESC_CMD_L4T_EOFT_EOF_NI\t= 0x0200, /* 2 BITS */\n\tI40E_TX_DESC_CMD_L4T_EOFT_EOF_A\t\t= 0x0300, /* 2 BITS */\n};\n\n#define I40E_TXD_QW1_OFFSET_SHIFT\t16\n#define I40E_TXD_QW1_OFFSET_MASK\t(0x3FFFFULL << \\\n\t\t\t\t\t I40E_TXD_QW1_OFFSET_SHIFT)\n\nenum i40e_tx_desc_length_fields {\n\t/* Note: These are predefined bit offsets */\n\tI40E_TX_DESC_LENGTH_MACLEN_SHIFT\t= 0, /* 7 BITS */\n\tI40E_TX_DESC_LENGTH_IPLEN_SHIFT\t\t= 7, /* 7 BITS */\n\tI40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT\t= 14 /* 4 BITS */\n};\n\n#define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT)\n#define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT)\n#define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)\n#define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)\n\n#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT\t34\n#define I40E_TXD_QW1_TX_BUF_SZ_MASK\t(0x3FFFULL << \\\n\t\t\t\t\t I40E_TXD_QW1_TX_BUF_SZ_SHIFT)\n\n#define I40E_TXD_QW1_L2TAG1_SHIFT\t48\n#define I40E_TXD_QW1_L2TAG1_MASK\t(0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)\n\n/* Context descriptors */\nstruct i40e_tx_context_desc {\n\t__le32 tunneling_params;\n\t__le16 l2tag2;\n\t__le16 rsvd;\n\t__le64 type_cmd_tso_mss;\n};\n\n#define I40E_TXD_CTX_QW1_DTYPE_SHIFT\t0\n#define I40E_TXD_CTX_QW1_DTYPE_MASK\t(0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)\n\n#define I40E_TXD_CTX_QW1_CMD_SHIFT\t4\n#define I40E_TXD_CTX_QW1_CMD_MASK\t(0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)\n\nenum i40e_tx_ctx_desc_cmd_bits {\n\tI40E_TX_CTX_DESC_TSO\t\t= 0x01,\n\tI40E_TX_CTX_DESC_TSYN\t\t= 0x02,\n\tI40E_TX_CTX_DESC_IL2TAG2\t= 0x04,\n\tI40E_TX_CTX_DESC_IL2TAG2_IL2H\t= 0x08,\n\tI40E_TX_CTX_DESC_SWTCH_NOTAG\t= 0x00,\n\tI40E_TX_CTX_DESC_SWTCH_UPLINK\t= 0x10,\n\tI40E_TX_CTX_DESC_SWTCH_LOCAL\t= 0x20,\n\tI40E_TX_CTX_DESC_SWTCH_VSI\t= 0x30,\n\tI40E_TX_CTX_DESC_SWPE\t\t= 0x40\n};\n\n#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT\t30\n#define I40E_TXD_CTX_QW1_TSO_LEN_MASK\t(0x3FFFFULL << \\\n\t\t\t\t\t I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)\n\n#define I40E_TXD_CTX_QW1_MSS_SHIFT\t50\n#define I40E_TXD_CTX_QW1_MSS_MASK\t(0x3FFFULL << \\\n\t\t\t\t\t I40E_TXD_CTX_QW1_MSS_SHIFT)\n\n#define I40E_TXD_CTX_QW1_VSI_SHIFT\t50\n#define I40E_TXD_CTX_QW1_VSI_MASK\t(0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)\n\n#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT\t0\n#define I40E_TXD_CTX_QW0_EXT_IP_MASK\t(0x3ULL << \\\n\t\t\t\t\t I40E_TXD_CTX_QW0_EXT_IP_SHIFT)\n\nenum i40e_tx_ctx_desc_eipt_offload {\n\tI40E_TX_CTX_EXT_IP_NONE\t\t= 0x0,\n\tI40E_TX_CTX_EXT_IP_IPV6\t\t= 0x1,\n\tI40E_TX_CTX_EXT_IP_IPV4_NO_CSUM\t= 0x2,\n\tI40E_TX_CTX_EXT_IP_IPV4\t\t= 0x3\n};\n\n#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT\t2\n#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK\t(0x3FULL << \\\n\t\t\t\t\t I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)\n\n#define I40E_TXD_CTX_QW0_NATT_SHIFT\t9\n#define I40E_TXD_CTX_QW0_NATT_MASK\t(0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)\n\n#define I40E_TXD_CTX_UDP_TUNNELING\t(0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)\n#define I40E_TXD_CTX_GRE_TUNNELING\t(0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)\n\n#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT\t11\n#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK\t(0x1ULL << \\\n\t\t\t\t\t I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)\n\n#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST\tI40E_TXD_CTX_QW0_EIP_NOINC_MASK\n\n#define I40E_TXD_CTX_QW0_NATLEN_SHIFT\t12\n#define I40E_TXD_CTX_QW0_NATLEN_MASK\t(0X7FULL << \\\n\t\t\t\t\t I40E_TXD_CTX_QW0_NATLEN_SHIFT)\n\n#define I40E_TXD_CTX_QW0_DECTTL_SHIFT\t19\n#define I40E_TXD_CTX_QW0_DECTTL_MASK\t(0xFULL << \\\n\t\t\t\t\t I40E_TXD_CTX_QW0_DECTTL_SHIFT)\n\nstruct i40e_nop_desc {\n\t__le64 rsvd;\n\t__le64 dtype_cmd;\n};\n\n#define I40E_TXD_NOP_QW1_DTYPE_SHIFT\t0\n#define I40E_TXD_NOP_QW1_DTYPE_MASK\t(0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT)\n\n#define I40E_TXD_NOP_QW1_CMD_SHIFT\t4\n#define I40E_TXD_NOP_QW1_CMD_MASK\t(0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT)\n\nenum i40e_tx_nop_desc_cmd_bits {\n\t/* Note: These are predefined bit offsets */\n\tI40E_TX_NOP_DESC_EOP_SHIFT\t= 0,\n\tI40E_TX_NOP_DESC_RS_SHIFT\t= 1,\n\tI40E_TX_NOP_DESC_RSV_SHIFT\t= 2 /* 5 bits */\n};\n\nstruct i40e_filter_program_desc {\n\t__le32 qindex_flex_ptype_vsi;\n\t__le32 rsvd;\n\t__le32 dtype_cmd_cntindex;\n\t__le32 fd_id;\n};\n#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT\t0\n#define I40E_TXD_FLTR_QW0_QINDEX_MASK\t(0x7FFUL << \\\n\t\t\t\t\t I40E_TXD_FLTR_QW0_QINDEX_SHIFT)\n#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT\t11\n#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK\t(0x7UL << \\\n\t\t\t\t\t I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)\n#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT\t17\n#define I40E_TXD_FLTR_QW0_PCTYPE_MASK\t(0x3FUL << \\\n\t\t\t\t\t I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)\n\n/* Packet Classifier Types for filters */\nenum i40e_filter_pctype {\n\t/* Note: Values 0-30 are reserved for future use */\n\tI40E_FILTER_PCTYPE_NONF_IPV4_UDP\t\t= 31,\n\t/* Note: Value 32 is reserved for future use */\n\tI40E_FILTER_PCTYPE_NONF_IPV4_TCP\t\t= 33,\n\tI40E_FILTER_PCTYPE_NONF_IPV4_SCTP\t\t= 34,\n\tI40E_FILTER_PCTYPE_NONF_IPV4_OTHER\t\t= 35,\n\tI40E_FILTER_PCTYPE_FRAG_IPV4\t\t\t= 36,\n\t/* Note: Values 37-40 are reserved for future use */\n\tI40E_FILTER_PCTYPE_NONF_IPV6_UDP\t\t= 41,\n\tI40E_FILTER_PCTYPE_NONF_IPV6_TCP\t\t= 43,\n\tI40E_FILTER_PCTYPE_NONF_IPV6_SCTP\t\t= 44,\n\tI40E_FILTER_PCTYPE_NONF_IPV6_OTHER\t\t= 45,\n\tI40E_FILTER_PCTYPE_FRAG_IPV6\t\t\t= 46,\n\t/* Note: Value 47 is reserved for future use */\n\tI40E_FILTER_PCTYPE_FCOE_OX\t\t\t= 48,\n\tI40E_FILTER_PCTYPE_FCOE_RX\t\t\t= 49,\n\tI40E_FILTER_PCTYPE_FCOE_OTHER\t\t\t= 50,\n\t/* Note: Values 51-62 are reserved for future use */\n\tI40E_FILTER_PCTYPE_L2_PAYLOAD\t\t\t= 63,\n};\n\nenum i40e_filter_program_desc_dest {\n\tI40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET\t\t= 0x0,\n\tI40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX\t= 0x1,\n\tI40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER\t= 0x2,\n};\n\nenum i40e_filter_program_desc_fd_status {\n\tI40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE\t\t\t= 0x0,\n\tI40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID\t\t= 0x1,\n\tI40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES\t= 0x2,\n\tI40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES\t\t= 0x3,\n};\n\n#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT\t23\n#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK\t(0x1FFUL << \\\n\t\t\t\t\t I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)\n\n#define I40E_TXD_FLTR_QW1_DTYPE_SHIFT\t0\n#define I40E_TXD_FLTR_QW1_DTYPE_MASK\t(0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT)\n\n#define I40E_TXD_FLTR_QW1_CMD_SHIFT\t4\n#define I40E_TXD_FLTR_QW1_CMD_MASK\t(0xFFFFULL << \\\n\t\t\t\t\t I40E_TXD_FLTR_QW1_CMD_SHIFT)\n\n#define I40E_TXD_FLTR_QW1_PCMD_SHIFT\t(0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)\n#define I40E_TXD_FLTR_QW1_PCMD_MASK\t(0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)\n\nenum i40e_filter_program_desc_pcmd {\n\tI40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE\t= 0x1,\n\tI40E_FILTER_PROGRAM_DESC_PCMD_REMOVE\t\t= 0x2,\n};\n\n#define I40E_TXD_FLTR_QW1_DEST_SHIFT\t(0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)\n#define I40E_TXD_FLTR_QW1_DEST_MASK\t(0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)\n\n#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT\t(0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)\n#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK\t(0x1ULL << \\\n\t\t\t\t\t I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)\n\n#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT\t(0x9ULL + \\\n\t\t\t\t\t\t I40E_TXD_FLTR_QW1_CMD_SHIFT)\n#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \\\n\t\t\t\t\t I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)\n\n#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20\n#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK\t(0x1FFUL << \\\n\t\t\t\t\t I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)\n\nenum i40e_filter_type {\n\tI40E_FLOW_DIRECTOR_FLTR = 0,\n\tI40E_PE_QUAD_HASH_FLTR = 1,\n\tI40E_ETHERTYPE_FLTR,\n\tI40E_FCOE_CTX_FLTR,\n\tI40E_MAC_VLAN_FLTR,\n\tI40E_HASH_FLTR\n};\n\nstruct i40e_vsi_context {\n\tu16 seid;\n\tu16 uplink_seid;\n\tu16 vsi_number;\n\tu16 vsis_allocated;\n\tu16 vsis_unallocated;\n\tu16 flags;\n\tu8 pf_num;\n\tu8 vf_num;\n\tu8 connection_type;\n\tstruct i40e_aqc_vsi_properties_data info;\n};\n\nstruct i40e_veb_context {\n\tu16 seid;\n\tu16 uplink_seid;\n\tu16 veb_number;\n\tu16 vebs_allocated;\n\tu16 vebs_unallocated;\n\tu16 flags;\n\tstruct i40e_aqc_get_veb_parameters_completion info;\n};\n\n/* Statistics collected by each port, VSI, VEB, and S-channel */\nstruct i40e_eth_stats {\n\tu64 rx_bytes;\t\t\t/* gorc */\n\tu64 rx_unicast;\t\t\t/* uprc */\n\tu64 rx_multicast;\t\t/* mprc */\n\tu64 rx_broadcast;\t\t/* bprc */\n\tu64 rx_discards;\t\t/* rdpc */\n\tu64 rx_unknown_protocol;\t/* rupp */\n\tu64 tx_bytes;\t\t\t/* gotc */\n\tu64 tx_unicast;\t\t\t/* uptc */\n\tu64 tx_multicast;\t\t/* mptc */\n\tu64 tx_broadcast;\t\t/* bptc */\n\tu64 tx_discards;\t\t/* tdpc */\n\tu64 tx_errors;\t\t\t/* tepc */\n};\n\n/* Statistics collected per VEB per TC */\nstruct i40e_veb_tc_stats {\n\tu64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];\n\tu64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];\n\tu64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];\n\tu64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];\n};\n\n/* Statistics collected by the MAC */\nstruct i40e_hw_port_stats {\n\t/* eth stats collected by the port */\n\tstruct i40e_eth_stats eth;\n\n\t/* additional port specific stats */\n\tu64 tx_dropped_link_down;\t/* tdold */\n\tu64 crc_errors;\t\t\t/* crcerrs */\n\tu64 illegal_bytes;\t\t/* illerrc */\n\tu64 error_bytes;\t\t/* errbc */\n\tu64 mac_local_faults;\t\t/* mlfc */\n\tu64 mac_remote_faults;\t\t/* mrfc */\n\tu64 rx_length_errors;\t\t/* rlec */\n\tu64 link_xon_rx;\t\t/* lxonrxc */\n\tu64 link_xoff_rx;\t\t/* lxoffrxc */\n\tu64 priority_xon_rx[8];\t\t/* pxonrxc[8] */\n\tu64 priority_xoff_rx[8];\t/* pxoffrxc[8] */\n\tu64 link_xon_tx;\t\t/* lxontxc */\n\tu64 link_xoff_tx;\t\t/* lxofftxc */\n\tu64 priority_xon_tx[8];\t\t/* pxontxc[8] */\n\tu64 priority_xoff_tx[8];\t/* pxofftxc[8] */\n\tu64 priority_xon_2_xoff[8];\t/* pxon2offc[8] */\n\tu64 rx_size_64;\t\t\t/* prc64 */\n\tu64 rx_size_127;\t\t/* prc127 */\n\tu64 rx_size_255;\t\t/* prc255 */\n\tu64 rx_size_511;\t\t/* prc511 */\n\tu64 rx_size_1023;\t\t/* prc1023 */\n\tu64 rx_size_1522;\t\t/* prc1522 */\n\tu64 rx_size_big;\t\t/* prc9522 */\n\tu64 rx_undersize;\t\t/* ruc */\n\tu64 rx_fragments;\t\t/* rfc */\n\tu64 rx_oversize;\t\t/* roc */\n\tu64 rx_jabber;\t\t\t/* rjc */\n\tu64 tx_size_64;\t\t\t/* ptc64 */\n\tu64 tx_size_127;\t\t/* ptc127 */\n\tu64 tx_size_255;\t\t/* ptc255 */\n\tu64 tx_size_511;\t\t/* ptc511 */\n\tu64 tx_size_1023;\t\t/* ptc1023 */\n\tu64 tx_size_1522;\t\t/* ptc1522 */\n\tu64 tx_size_big;\t\t/* ptc9522 */\n\tu64 mac_short_packet_dropped;\t/* mspdc */\n\tu64 checksum_error;\t\t/* xec */\n\t/* flow director stats */\n\tu64 fd_atr_match;\n\tu64 fd_sb_match;\n\t/* EEE LPI */\n\tu32 tx_lpi_status;\n\tu32 rx_lpi_status;\n\tu64 tx_lpi_count;\t\t/* etlpic */\n\tu64 rx_lpi_count;\t\t/* erlpic */\n};\n\n/* Checksum and Shadow RAM pointers */\n#define I40E_SR_NVM_CONTROL_WORD\t\t0x00\n#define I40E_SR_PCIE_ANALOG_CONFIG_PTR\t\t0x03\n#define I40E_SR_PHY_ANALOG_CONFIG_PTR\t\t0x04\n#define I40E_SR_OPTION_ROM_PTR\t\t\t0x05\n#define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR\t0x06\n#define I40E_SR_AUTO_GENERATED_POINTERS_PTR\t0x07\n#define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR\t\t0x08\n#define I40E_SR_EMP_GLOBAL_MODULE_PTR\t\t0x09\n#define I40E_SR_RO_PCIE_LCB_PTR\t\t\t0x0A\n#define I40E_SR_EMP_IMAGE_PTR\t\t\t0x0B\n#define I40E_SR_PE_IMAGE_PTR\t\t\t0x0C\n#define I40E_SR_CSR_PROTECTED_LIST_PTR\t\t0x0D\n#define I40E_SR_MNG_CONFIG_PTR\t\t\t0x0E\n#define I40E_SR_EMP_MODULE_PTR\t\t\t0x0F\n#define I40E_SR_PBA_FLAGS\t\t\t0x15\n#define I40E_SR_PBA_BLOCK_PTR\t\t\t0x16\n#define I40E_SR_BOOT_CONFIG_PTR\t\t\t0x17\n#define I40E_SR_NVM_DEV_STARTER_VERSION\t\t0x18\n#define I40E_SR_NVM_WAKE_ON_LAN\t\t\t0x19\n#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR\t0x27\n#define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR\t0x28\n#define I40E_SR_NVM_MAP_VERSION\t\t\t0x29\n#define I40E_SR_NVM_IMAGE_VERSION\t\t0x2A\n#define I40E_SR_NVM_STRUCTURE_VERSION\t\t0x2B\n#define I40E_SR_NVM_EETRACK_LO\t\t\t0x2D\n#define I40E_SR_NVM_EETRACK_HI\t\t\t0x2E\n#define I40E_SR_VPD_PTR\t\t\t\t0x2F\n#define I40E_SR_PXE_SETUP_PTR\t\t\t0x30\n#define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR\t0x31\n#define I40E_SR_NVM_ORIGINAL_EETRACK_LO\t\t0x34\n#define I40E_SR_NVM_ORIGINAL_EETRACK_HI\t\t0x35\n#define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR\t0x37\n#define I40E_SR_POR_REGS_AUTO_LOAD_PTR\t\t0x38\n#define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR\t\t0x3A\n#define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR\t0x3B\n#define I40E_SR_CORER_REGS_AUTO_LOAD_PTR\t0x3C\n#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR\t\t0x3E\n#define I40E_SR_SW_CHECKSUM_WORD\t\t0x3F\n#define I40E_SR_1ST_FREE_PROVISION_AREA_PTR\t0x40\n#define I40E_SR_4TH_FREE_PROVISION_AREA_PTR\t0x42\n#define I40E_SR_3RD_FREE_PROVISION_AREA_PTR\t0x44\n#define I40E_SR_2ND_FREE_PROVISION_AREA_PTR\t0x46\n#define I40E_SR_EMP_SR_SETTINGS_PTR\t\t0x48\n#define I40E_SR_FEATURE_CONFIGURATION_PTR\t0x49\n#define I40E_SR_CONFIGURATION_METADATA_PTR\t0x4D\n#define I40E_SR_IMMEDIATE_VALUES_PTR\t\t0x4E\n\n/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */\n#define I40E_SR_VPD_MODULE_MAX_SIZE\t\t1024\n#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE\t1024\n#define I40E_SR_CONTROL_WORD_1_SHIFT\t\t0x06\n#define I40E_SR_CONTROL_WORD_1_MASK\t(0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)\n\n/* Shadow RAM related */\n#define I40E_SR_SECTOR_SIZE_IN_WORDS\t0x800\n#define I40E_SR_BUF_ALIGNMENT\t\t4096\n#define I40E_SR_WORDS_IN_1KB\t\t512\n/* Checksum should be calculated such that after adding all the words,\n * including the checksum word itself, the sum should be 0xBABA.\n */\n#define I40E_SR_SW_CHECKSUM_BASE\t0xBABA\n\n#define I40E_SRRD_SRCTL_ATTEMPTS\t100000\n\nenum i40e_switch_element_types {\n\tI40E_SWITCH_ELEMENT_TYPE_MAC\t= 1,\n\tI40E_SWITCH_ELEMENT_TYPE_PF\t= 2,\n\tI40E_SWITCH_ELEMENT_TYPE_VF\t= 3,\n\tI40E_SWITCH_ELEMENT_TYPE_EMP\t= 4,\n\tI40E_SWITCH_ELEMENT_TYPE_BMC\t= 6,\n\tI40E_SWITCH_ELEMENT_TYPE_PE\t= 16,\n\tI40E_SWITCH_ELEMENT_TYPE_VEB\t= 17,\n\tI40E_SWITCH_ELEMENT_TYPE_PA\t= 18,\n\tI40E_SWITCH_ELEMENT_TYPE_VSI\t= 19,\n};\n\n/* Supported EtherType filters */\nenum i40e_ether_type_index {\n\tI40E_ETHER_TYPE_1588\t\t= 0,\n\tI40E_ETHER_TYPE_FIP\t\t= 1,\n\tI40E_ETHER_TYPE_OUI_EXTENDED\t= 2,\n\tI40E_ETHER_TYPE_MAC_CONTROL\t= 3,\n\tI40E_ETHER_TYPE_LLDP\t\t= 4,\n\tI40E_ETHER_TYPE_EVB_PROTOCOL1\t= 5,\n\tI40E_ETHER_TYPE_EVB_PROTOCOL2\t= 6,\n\tI40E_ETHER_TYPE_QCN_CNM\t\t= 7,\n\tI40E_ETHER_TYPE_8021X\t\t= 8,\n\tI40E_ETHER_TYPE_ARP\t\t= 9,\n\tI40E_ETHER_TYPE_RSV1\t\t= 10,\n\tI40E_ETHER_TYPE_RSV2\t\t= 11,\n};\n\n/* Filter context base size is 1K */\n#define I40E_HASH_FILTER_BASE_SIZE\t1024\n/* Supported Hash filter values */\nenum i40e_hash_filter_size {\n\tI40E_HASH_FILTER_SIZE_1K\t= 0,\n\tI40E_HASH_FILTER_SIZE_2K\t= 1,\n\tI40E_HASH_FILTER_SIZE_4K\t= 2,\n\tI40E_HASH_FILTER_SIZE_8K\t= 3,\n\tI40E_HASH_FILTER_SIZE_16K\t= 4,\n\tI40E_HASH_FILTER_SIZE_32K\t= 5,\n\tI40E_HASH_FILTER_SIZE_64K\t= 6,\n\tI40E_HASH_FILTER_SIZE_128K\t= 7,\n\tI40E_HASH_FILTER_SIZE_256K\t= 8,\n\tI40E_HASH_FILTER_SIZE_512K\t= 9,\n\tI40E_HASH_FILTER_SIZE_1M\t= 10,\n};\n\n/* DMA context base size is 0.5K */\n#define I40E_DMA_CNTX_BASE_SIZE\t\t512\n/* Supported DMA context values */\nenum i40e_dma_cntx_size {\n\tI40E_DMA_CNTX_SIZE_512\t\t= 0,\n\tI40E_DMA_CNTX_SIZE_1K\t\t= 1,\n\tI40E_DMA_CNTX_SIZE_2K\t\t= 2,\n\tI40E_DMA_CNTX_SIZE_4K\t\t= 3,\n\tI40E_DMA_CNTX_SIZE_8K\t\t= 4,\n\tI40E_DMA_CNTX_SIZE_16K\t\t= 5,\n\tI40E_DMA_CNTX_SIZE_32K\t\t= 6,\n\tI40E_DMA_CNTX_SIZE_64K\t\t= 7,\n\tI40E_DMA_CNTX_SIZE_128K\t\t= 8,\n\tI40E_DMA_CNTX_SIZE_256K\t\t= 9,\n};\n\n/* Supported Hash look up table (LUT) sizes */\nenum i40e_hash_lut_size {\n\tI40E_HASH_LUT_SIZE_128\t\t= 0,\n\tI40E_HASH_LUT_SIZE_512\t\t= 1,\n};\n\n/* Structure to hold a per PF filter control settings */\nstruct i40e_filter_control_settings {\n\t/* number of PE Quad Hash filter buckets */\n\tenum i40e_hash_filter_size pe_filt_num;\n\t/* number of PE Quad Hash contexts */\n\tenum i40e_dma_cntx_size pe_cntx_num;\n\t/* number of FCoE filter buckets */\n\tenum i40e_hash_filter_size fcoe_filt_num;\n\t/* number of FCoE DDP contexts */\n\tenum i40e_dma_cntx_size fcoe_cntx_num;\n\t/* size of the Hash LUT */\n\tenum i40e_hash_lut_size\thash_lut_size;\n\t/* enable FDIR filters for PF and its VFs */\n\tbool enable_fdir;\n\t/* enable Ethertype filters for PF and its VFs */\n\tbool enable_ethtype;\n\t/* enable MAC/VLAN filters for PF and its VFs */\n\tbool enable_macvlan;\n};\n\n/* Structure to hold device level control filter counts */\nstruct i40e_control_filter_stats {\n\tu16 mac_etype_used; /* Used perfect match MAC/EtherType filters */\n\tu16 etype_used; /* Used perfect EtherType filters */\n\tu16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */\n\tu16 etype_free; /* Un-used perfect EtherType filters */\n};\n\nenum i40e_reset_type {\n\tI40E_RESET_POR\t\t= 0,\n\tI40E_RESET_CORER\t= 1,\n\tI40E_RESET_GLOBR\t= 2,\n\tI40E_RESET_EMPR\t\t= 3,\n};\n\n/* IEEE 802.1AB LLDP Agent Variables from NVM */\n#define I40E_NVM_LLDP_CFG_PTR\t\t0xD\nstruct i40e_lldp_variables {\n\tu16 length;\n\tu16 adminstatus;\n\tu16 msgfasttx;\n\tu16 msgtxinterval;\n\tu16 txparams;\n\tu16 timers;\n\tu16 crc8;\n};\n\n/* Offsets into Alternate Ram */\n#define I40E_ALT_STRUCT_FIRST_PF_OFFSET\t\t0 /* in dwords */\n#define I40E_ALT_STRUCT_DWORDS_PER_PF\t\t64 /* in dwords */\n#define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET\t0xD /* in dwords */\n#define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET\t0xC /* in dwords */\n#define I40E_ALT_STRUCT_MIN_BW_OFFSET\t\t0xE /* in dwords */\n#define I40E_ALT_STRUCT_MAX_BW_OFFSET\t\t0xF /* in dwords */\n\n/* Alternate Ram Bandwidth Masks */\n#define I40E_ALT_BW_VALUE_MASK\t\t0xFF\n#define I40E_ALT_BW_RELATIVE_MASK\t0x40000000\n#define I40E_ALT_BW_VALID_MASK\t\t0x80000000\n\n/* RSS Hash Table Size */\n#define I40E_PFQF_CTL_0_HASHLUTSIZE_512\t0x00010000\n#endif /* _I40E_TYPE_H_ */\n" }, { "path": "drivers/net/i40e/base/i40e_virtchnl.h", "content": "/*******************************************************************************\n\nCopyright (c) 2013 - 2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _I40E_VIRTCHNL_H_\n#define _I40E_VIRTCHNL_H_\n\n#include \"i40e_type.h\"\n\n/* Description:\n * This header file describes the VF-PF communication protocol used\n * by the various i40e drivers.\n *\n * Admin queue buffer usage:\n * desc->opcode is always i40e_aqc_opc_send_msg_to_pf\n * flags, retval, datalen, and data addr are all used normally.\n * Firmware copies the cookie fields when sending messages between the PF and\n * VF, but uses all other fields internally. Due to this limitation, we\n * must send all messages as \"indirect\", i.e. using an external buffer.\n *\n * All the vsi indexes are relative to the VF. Each VF can have maximum of\n * three VSIs. All the queue indexes are relative to the VSI. Each VF can\n * have a maximum of sixteen queues for all of its VSIs.\n *\n * The PF is required to return a status code in v_retval for all messages\n * except RESET_VF, which does not require any response. The return value is of\n * i40e_status_code type, defined in the i40e_type.h.\n *\n * In general, VF driver initialization should roughly follow the order of these\n * opcodes. The VF driver must first validate the API version of the PF driver,\n * then request a reset, then get resources, then configure queues and\n * interrupts. After these operations are complete, the VF driver may start\n * its queues, optionally add MAC and VLAN filters, and process traffic.\n */\n\n/* Opcodes for VF-PF communication. These are placed in the v_opcode field\n * of the virtchnl_msg structure.\n */\nenum i40e_virtchnl_ops {\n/* The PF sends status change events to VFs using\n * the I40E_VIRTCHNL_OP_EVENT opcode.\n * VFs send requests to the PF using the other ops.\n */\n\tI40E_VIRTCHNL_OP_UNKNOWN = 0,\n\tI40E_VIRTCHNL_OP_VERSION = 1, /* must ALWAYS be 1 */\n\tI40E_VIRTCHNL_OP_RESET_VF = 2,\n\tI40E_VIRTCHNL_OP_GET_VF_RESOURCES = 3,\n\tI40E_VIRTCHNL_OP_CONFIG_TX_QUEUE = 4,\n\tI40E_VIRTCHNL_OP_CONFIG_RX_QUEUE = 5,\n\tI40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES = 6,\n\tI40E_VIRTCHNL_OP_CONFIG_IRQ_MAP = 7,\n\tI40E_VIRTCHNL_OP_ENABLE_QUEUES = 8,\n\tI40E_VIRTCHNL_OP_DISABLE_QUEUES = 9,\n\tI40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS = 10,\n\tI40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS = 11,\n\tI40E_VIRTCHNL_OP_ADD_VLAN = 12,\n\tI40E_VIRTCHNL_OP_DEL_VLAN = 13,\n\tI40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE = 14,\n\tI40E_VIRTCHNL_OP_GET_STATS = 15,\n\tI40E_VIRTCHNL_OP_FCOE = 16,\n\tI40E_VIRTCHNL_OP_EVENT = 17,\n\tI40E_VIRTCHNL_OP_CONFIG_RSS = 18,\n};\n\n/* Virtual channel message descriptor. This overlays the admin queue\n * descriptor. All other data is passed in external buffers.\n */\n\nstruct i40e_virtchnl_msg {\n\tu8 pad[8];\t\t\t /* AQ flags/opcode/len/retval fields */\n\tenum i40e_virtchnl_ops v_opcode; /* avoid confusion with desc->opcode */\n\tenum i40e_status_code v_retval; /* ditto for desc->retval */\n\tu32 vfid;\t\t\t /* used by PF when sending to VF */\n};\n\n/* Message descriptions and data structures.*/\n\n/* I40E_VIRTCHNL_OP_VERSION\n * VF posts its version number to the PF. PF responds with its version number\n * in the same format, along with a return code.\n * Reply from PF has its major/minor versions also in param0 and param1.\n * If there is a major version mismatch, then the VF cannot operate.\n * If there is a minor version mismatch, then the VF can operate but should\n * add a warning to the system log.\n *\n * This enum element MUST always be specified as == 1, regardless of other\n * changes in the API. The PF must always respond to this message without\n * error regardless of version mismatch.\n */\n#define I40E_VIRTCHNL_VERSION_MAJOR\t\t1\n#define I40E_VIRTCHNL_VERSION_MINOR\t\t0\nstruct i40e_virtchnl_version_info {\n\tu32 major;\n\tu32 minor;\n};\n\n/* I40E_VIRTCHNL_OP_RESET_VF\n * VF sends this request to PF with no parameters\n * PF does NOT respond! VF driver must delay then poll VFGEN_RSTAT register\n * until reset completion is indicated. The admin queue must be reinitialized\n * after this operation.\n *\n * When reset is complete, PF must ensure that all queues in all VSIs associated\n * with the VF are stopped, all queue configurations in the HMC are set to 0,\n * and all MAC and VLAN filters (except the default MAC address) on all VSIs\n * are cleared.\n */\n\n/* I40E_VIRTCHNL_OP_GET_VF_RESOURCES\n * VF sends this request to PF with no parameters\n * PF responds with an indirect message containing\n * i40e_virtchnl_vf_resource and one or more\n * i40e_virtchnl_vsi_resource structures.\n */\n\nstruct i40e_virtchnl_vsi_resource {\n\tu16 vsi_id;\n\tu16 num_queue_pairs;\n\tenum i40e_vsi_type vsi_type;\n\tu16 qset_handle;\n\tu8 default_mac_addr[I40E_ETH_LENGTH_OF_ADDRESS];\n};\n/* VF offload flags */\n#define I40E_VIRTCHNL_VF_OFFLOAD_L2\t0x00000001\n#define I40E_VIRTCHNL_VF_OFFLOAD_IWARP\t0x00000002\n#define I40E_VIRTCHNL_VF_OFFLOAD_FCOE\t0x00000004\n#define I40E_VIRTCHNL_VF_OFFLOAD_VLAN\t0x00010000\n\nstruct i40e_virtchnl_vf_resource {\n\tu16 num_vsis;\n\tu16 num_queue_pairs;\n\tu16 max_vectors;\n\tu16 max_mtu;\n\n\tu32 vf_offload_flags;\n\tu32 max_fcoe_contexts;\n\tu32 max_fcoe_filters;\n\n\tstruct i40e_virtchnl_vsi_resource vsi_res[1];\n};\n\n/* I40E_VIRTCHNL_OP_CONFIG_TX_QUEUE\n * VF sends this message to set up parameters for one TX queue.\n * External data buffer contains one instance of i40e_virtchnl_txq_info.\n * PF configures requested queue and returns a status code.\n */\n\n/* Tx queue config info */\nstruct i40e_virtchnl_txq_info {\n\tu16 vsi_id;\n\tu16 queue_id;\n\tu16 ring_len;\t\t/* number of descriptors, multiple of 8 */\n\tu16 headwb_enabled;\n\tu64 dma_ring_addr;\n\tu64 dma_headwb_addr;\n};\n\n/* I40E_VIRTCHNL_OP_CONFIG_RX_QUEUE\n * VF sends this message to set up parameters for one RX queue.\n * External data buffer contains one instance of i40e_virtchnl_rxq_info.\n * PF configures requested queue and returns a status code.\n */\n\n/* Rx queue config info */\nstruct i40e_virtchnl_rxq_info {\n\tu16 vsi_id;\n\tu16 queue_id;\n\tu32 ring_len;\t\t/* number of descriptors, multiple of 32 */\n\tu16 hdr_size;\n\tu16 splithdr_enabled;\n\tu32 databuffer_size;\n\tu32 max_pkt_size;\n\tu64 dma_ring_addr;\n\tenum i40e_hmc_obj_rx_hsplit_0 rx_split_pos;\n};\n\n/* I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n * VF sends this message to set parameters for all active TX and RX queues\n * associated with the specified VSI.\n * PF configures queues and returns status.\n * If the number of queues specified is greater than the number of queues\n * associated with the VSI, an error is returned and no queues are configured.\n */\nstruct i40e_virtchnl_queue_pair_info {\n\t/* NOTE: vsi_id and queue_id should be identical for both queues. */\n\tstruct i40e_virtchnl_txq_info txq;\n\tstruct i40e_virtchnl_rxq_info rxq;\n};\n\nstruct i40e_virtchnl_vsi_queue_config_info {\n\tu16 vsi_id;\n\tu16 num_queue_pairs;\n\tstruct i40e_virtchnl_queue_pair_info qpair[1];\n};\n\n/* I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP\n * VF uses this message to map vectors to queues.\n * The rxq_map and txq_map fields are bitmaps used to indicate which queues\n * are to be associated with the specified vector.\n * The \"other\" causes are always mapped to vector 0.\n * PF configures interrupt mapping and returns status.\n */\nstruct i40e_virtchnl_vector_map {\n\tu16 vsi_id;\n\tu16 vector_id;\n\tu16 rxq_map;\n\tu16 txq_map;\n\tu16 rxitr_idx;\n\tu16 txitr_idx;\n};\n\nstruct i40e_virtchnl_irq_map_info {\n\tu16 num_vectors;\n\tstruct i40e_virtchnl_vector_map vecmap[1];\n};\n\n/* I40E_VIRTCHNL_OP_ENABLE_QUEUES\n * I40E_VIRTCHNL_OP_DISABLE_QUEUES\n * VF sends these message to enable or disable TX/RX queue pairs.\n * The queues fields are bitmaps indicating which queues to act upon.\n * (Currently, we only support 16 queues per VF, but we make the field\n * u32 to allow for expansion.)\n * PF performs requested action and returns status.\n */\nstruct i40e_virtchnl_queue_select {\n\tu16 vsi_id;\n\tu16 pad;\n\tu32 rx_queues;\n\tu32 tx_queues;\n};\n\n/* I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS\n * VF sends this message in order to add one or more unicast or multicast\n * address filters for the specified VSI.\n * PF adds the filters and returns status.\n */\n\n/* I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS\n * VF sends this message in order to remove one or more unicast or multicast\n * filters for the specified VSI.\n * PF removes the filters and returns status.\n */\n\nstruct i40e_virtchnl_ether_addr {\n\tu8 addr[I40E_ETH_LENGTH_OF_ADDRESS];\n\tu8 pad[2];\n};\n\nstruct i40e_virtchnl_ether_addr_list {\n\tu16 vsi_id;\n\tu16 num_elements;\n\tstruct i40e_virtchnl_ether_addr list[1];\n};\n\n/* I40E_VIRTCHNL_OP_ADD_VLAN\n * VF sends this message to add one or more VLAN tag filters for receives.\n * PF adds the filters and returns status.\n * If a port VLAN is configured by the PF, this operation will return an\n * error to the VF.\n */\n\n/* I40E_VIRTCHNL_OP_DEL_VLAN\n * VF sends this message to remove one or more VLAN tag filters for receives.\n * PF removes the filters and returns status.\n * If a port VLAN is configured by the PF, this operation will return an\n * error to the VF.\n */\n\nstruct i40e_virtchnl_vlan_filter_list {\n\tu16 vsi_id;\n\tu16 num_elements;\n\tu16 vlan_id[1];\n};\n\n/* I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE\n * VF sends VSI id and flags.\n * PF returns status code in retval.\n * Note: we assume that broadcast accept mode is always enabled.\n */\nstruct i40e_virtchnl_promisc_info {\n\tu16 vsi_id;\n\tu16 flags;\n};\n\n#define I40E_FLAG_VF_UNICAST_PROMISC\t0x00000001\n#define I40E_FLAG_VF_MULTICAST_PROMISC\t0x00000002\n\n/* I40E_VIRTCHNL_OP_GET_STATS\n * VF sends this message to request stats for the selected VSI. VF uses\n * the i40e_virtchnl_queue_select struct to specify the VSI. The queue_id\n * field is ignored by the PF.\n *\n * PF replies with struct i40e_eth_stats in an external buffer.\n */\n\n/* I40E_VIRTCHNL_OP_EVENT\n * PF sends this message to inform the VF driver of events that may affect it.\n * No direct response is expected from the VF, though it may generate other\n * messages in response to this one.\n */\nenum i40e_virtchnl_event_codes {\n\tI40E_VIRTCHNL_EVENT_UNKNOWN = 0,\n\tI40E_VIRTCHNL_EVENT_LINK_CHANGE,\n\tI40E_VIRTCHNL_EVENT_RESET_IMPENDING,\n\tI40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE,\n};\n#define I40E_PF_EVENT_SEVERITY_INFO\t\t0\n#define I40E_PF_EVENT_SEVERITY_ATTENTION\t1\n#define I40E_PF_EVENT_SEVERITY_ACTION_REQUIRED\t2\n#define I40E_PF_EVENT_SEVERITY_CERTAIN_DOOM\t255\n\nstruct i40e_virtchnl_pf_event {\n\tenum i40e_virtchnl_event_codes event;\n\tunion {\n\t\tstruct {\n\t\t\tenum i40e_aq_link_speed link_speed;\n\t\t\tbool link_status;\n\t\t} link_event;\n\t} event_data;\n\n\tint severity;\n};\n\n/* VF reset states - these are written into the RSTAT register:\n * I40E_VFGEN_RSTAT1 on the PF\n * I40E_VFGEN_RSTAT on the VF\n * When the PF initiates a reset, it writes 0\n * When the reset is complete, it writes 1\n * When the PF detects that the VF has recovered, it writes 2\n * VF checks this register periodically to determine if a reset has occurred,\n * then polls it to know when the reset is complete.\n * If either the PF or VF reads the register while the hardware\n * is in a reset state, it will return DEADBEEF, which, when masked\n * will result in 3.\n */\nenum i40e_vfr_states {\n\tI40E_VFR_INPROGRESS = 0,\n\tI40E_VFR_COMPLETED,\n\tI40E_VFR_VFACTIVE,\n\tI40E_VFR_UNKNOWN,\n};\n\n#endif /* _I40E_VIRTCHNL_H_ */\n" }, { "path": "drivers/net/i40e/i40e_ethdev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"i40e_logs.h\"\n#include \"base/i40e_prototype.h\"\n#include \"base/i40e_adminq_cmd.h\"\n#include \"base/i40e_type.h\"\n#include \"base/i40e_register.h\"\n#include \"i40e_ethdev.h\"\n#include \"i40e_rxtx.h\"\n#include \"i40e_pf.h\"\n\n/* Maximun number of MAC addresses */\n#define I40E_NUM_MACADDR_MAX 64\n#define I40E_CLEAR_PXE_WAIT_MS 200\n\n/* Maximun number of capability elements */\n#define I40E_MAX_CAP_ELE_NUM 128\n\n/* Wait count and inteval */\n#define I40E_CHK_Q_ENA_COUNT 1000\n#define I40E_CHK_Q_ENA_INTERVAL_US 1000\n\n/* Maximun number of VSI */\n#define I40E_MAX_NUM_VSIS (384UL)\n\n/* Default queue interrupt throttling time in microseconds */\n#define I40E_ITR_INDEX_DEFAULT 0\n#define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */\n#define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */\n\n#define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */\n\n/* Mask of PF interrupt causes */\n#define I40E_PFINT_ICR0_ENA_MASK ( \\\n\t\tI40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \\\n\t\tI40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \\\n\t\tI40E_PFINT_ICR0_ENA_GRST_MASK | \\\n\t\tI40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \\\n\t\tI40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \\\n\t\tI40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \\\n\t\tI40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \\\n\t\tI40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \\\n\t\tI40E_PFINT_ICR0_ENA_VFLR_MASK | \\\n\t\tI40E_PFINT_ICR0_ENA_ADMINQ_MASK)\n\n#define I40E_FLOW_TYPES ( \\\n\t(1UL << RTE_ETH_FLOW_FRAG_IPV4) | \\\n\t(1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \\\n\t(1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \\\n\t(1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \\\n\t(1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \\\n\t(1UL << RTE_ETH_FLOW_FRAG_IPV6) | \\\n\t(1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \\\n\t(1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \\\n\t(1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \\\n\t(1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \\\n\t(1UL << RTE_ETH_FLOW_L2_PAYLOAD))\n\n#define I40E_PTP_40GB_INCVAL 0x0199999999ULL\n#define I40E_PTP_10GB_INCVAL 0x0333333333ULL\n#define I40E_PTP_1GB_INCVAL 0x2000000000ULL\n#define I40E_PRTTSYN_TSYNENA 0x80000000\n#define I40E_PRTTSYN_TSYNTYPE 0x0e000000\n\nstatic int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);\nstatic int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);\nstatic int i40e_dev_configure(struct rte_eth_dev *dev);\nstatic int i40e_dev_start(struct rte_eth_dev *dev);\nstatic void i40e_dev_stop(struct rte_eth_dev *dev);\nstatic void i40e_dev_close(struct rte_eth_dev *dev);\nstatic void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);\nstatic void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);\nstatic void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);\nstatic void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);\nstatic int i40e_dev_set_link_up(struct rte_eth_dev *dev);\nstatic int i40e_dev_set_link_down(struct rte_eth_dev *dev);\nstatic void i40e_dev_stats_get(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_stats *stats);\nstatic void i40e_dev_stats_reset(struct rte_eth_dev *dev);\nstatic int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,\n\t\t\t\t\t uint16_t queue_id,\n\t\t\t\t\t uint8_t stat_idx,\n\t\t\t\t\t uint8_t is_rx);\nstatic void i40e_dev_info_get(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_dev_info *dev_info);\nstatic int i40e_vlan_filter_set(struct rte_eth_dev *dev,\n\t\t\t\tuint16_t vlan_id,\n\t\t\t\tint on);\nstatic void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);\nstatic void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);\nstatic void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t queue,\n\t\t\t\t int on);\nstatic int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);\nstatic int i40e_dev_led_on(struct rte_eth_dev *dev);\nstatic int i40e_dev_led_off(struct rte_eth_dev *dev);\nstatic int i40e_flow_ctrl_set(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_fc_conf *fc_conf);\nstatic int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_pfc_conf *pfc_conf);\nstatic void i40e_macaddr_add(struct rte_eth_dev *dev,\n\t\t\t struct ether_addr *mac_addr,\n\t\t\t uint32_t index,\n\t\t\t uint32_t pool);\nstatic void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);\nstatic int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t\t uint16_t reta_size);\nstatic int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t\t uint16_t reta_size);\n\nstatic int i40e_get_cap(struct i40e_hw *hw);\nstatic int i40e_pf_parameter_init(struct rte_eth_dev *dev);\nstatic int i40e_pf_setup(struct i40e_pf *pf);\nstatic int i40e_dev_rxtx_init(struct i40e_pf *pf);\nstatic int i40e_vmdq_setup(struct rte_eth_dev *dev);\nstatic void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,\n\t\tbool offset_loaded, uint64_t *offset, uint64_t *stat);\nstatic void i40e_stat_update_48(struct i40e_hw *hw,\n\t\t\t uint32_t hireg,\n\t\t\t uint32_t loreg,\n\t\t\t bool offset_loaded,\n\t\t\t uint64_t *offset,\n\t\t\t uint64_t *stat);\nstatic void i40e_pf_config_irq0(struct i40e_hw *hw);\nstatic void i40e_dev_interrupt_handler(\n\t\t__rte_unused struct rte_intr_handle *handle, void *param);\nstatic int i40e_res_pool_init(struct i40e_res_pool_info *pool,\n\t\t\t\tuint32_t base, uint32_t num);\nstatic void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);\nstatic int i40e_res_pool_free(struct i40e_res_pool_info *pool,\n\t\t\tuint32_t base);\nstatic int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,\n\t\t\tuint16_t num);\nstatic int i40e_dev_init_vlan(struct rte_eth_dev *dev);\nstatic int i40e_veb_release(struct i40e_veb *veb);\nstatic struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,\n\t\t\t\t\t\tstruct i40e_vsi *vsi);\nstatic int i40e_pf_config_mq_rx(struct i40e_pf *pf);\nstatic int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);\nstatic inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,\n\t\t\t\t\t struct i40e_macvlan_filter *mv_f,\n\t\t\t\t\t int num,\n\t\t\t\t\t struct ether_addr *addr);\nstatic inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,\n\t\t\t\t\t struct i40e_macvlan_filter *mv_f,\n\t\t\t\t\t int num,\n\t\t\t\t\t uint16_t vlan);\nstatic int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);\nstatic int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_rss_conf *rss_conf);\nstatic int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_rss_conf *rss_conf);\nstatic int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_udp_tunnel *udp_tunnel);\nstatic int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_udp_tunnel *udp_tunnel);\nstatic int i40e_ethertype_filter_set(struct i40e_pf *pf,\n\t\t\tstruct rte_eth_ethertype_filter *filter,\n\t\t\tbool add);\nstatic int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,\n\t\t\t\tenum rte_filter_op filter_op,\n\t\t\t\tvoid *arg);\nstatic int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n\t\t\t\tenum rte_filter_type filter_type,\n\t\t\t\tenum rte_filter_op filter_op,\n\t\t\t\tvoid *arg);\nstatic void i40e_configure_registers(struct i40e_hw *hw);\nstatic void i40e_hw_init(struct i40e_hw *hw);\nstatic int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);\nstatic int i40e_mirror_rule_set(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_mirror_conf *mirror_conf,\n\t\t\tuint8_t sw_id, uint8_t on);\nstatic int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);\n\nstatic int i40e_timesync_enable(struct rte_eth_dev *dev);\nstatic int i40e_timesync_disable(struct rte_eth_dev *dev);\nstatic int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n\t\t\t\t\t struct timespec *timestamp,\n\t\t\t\t\t uint32_t flags);\nstatic int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n\t\t\t\t\t struct timespec *timestamp);\n\nstatic const struct rte_pci_id pci_id_i40e_map[] = {\n#define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \"rte_pci_dev_ids.h\"\n{ .vendor_id = 0, /* sentinel */ },\n};\n\nstatic const struct eth_dev_ops i40e_eth_dev_ops = {\n\t.dev_configure = i40e_dev_configure,\n\t.dev_start = i40e_dev_start,\n\t.dev_stop = i40e_dev_stop,\n\t.dev_close = i40e_dev_close,\n\t.promiscuous_enable = i40e_dev_promiscuous_enable,\n\t.promiscuous_disable = i40e_dev_promiscuous_disable,\n\t.allmulticast_enable = i40e_dev_allmulticast_enable,\n\t.allmulticast_disable = i40e_dev_allmulticast_disable,\n\t.dev_set_link_up = i40e_dev_set_link_up,\n\t.dev_set_link_down = i40e_dev_set_link_down,\n\t.link_update = i40e_dev_link_update,\n\t.stats_get = i40e_dev_stats_get,\n\t.stats_reset = i40e_dev_stats_reset,\n\t.queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,\n\t.dev_infos_get = i40e_dev_info_get,\n\t.vlan_filter_set = i40e_vlan_filter_set,\n\t.vlan_tpid_set = i40e_vlan_tpid_set,\n\t.vlan_offload_set = i40e_vlan_offload_set,\n\t.vlan_strip_queue_set = i40e_vlan_strip_queue_set,\n\t.vlan_pvid_set = i40e_vlan_pvid_set,\n\t.rx_queue_start = i40e_dev_rx_queue_start,\n\t.rx_queue_stop = i40e_dev_rx_queue_stop,\n\t.tx_queue_start = i40e_dev_tx_queue_start,\n\t.tx_queue_stop = i40e_dev_tx_queue_stop,\n\t.rx_queue_setup = i40e_dev_rx_queue_setup,\n\t.rx_queue_release = i40e_dev_rx_queue_release,\n\t.rx_queue_count = i40e_dev_rx_queue_count,\n\t.rx_descriptor_done = i40e_dev_rx_descriptor_done,\n\t.tx_queue_setup = i40e_dev_tx_queue_setup,\n\t.tx_queue_release = i40e_dev_tx_queue_release,\n\t.dev_led_on = i40e_dev_led_on,\n\t.dev_led_off = i40e_dev_led_off,\n\t.flow_ctrl_set = i40e_flow_ctrl_set,\n\t.priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,\n\t.mac_addr_add = i40e_macaddr_add,\n\t.mac_addr_remove = i40e_macaddr_remove,\n\t.reta_update = i40e_dev_rss_reta_update,\n\t.reta_query = i40e_dev_rss_reta_query,\n\t.rss_hash_update = i40e_dev_rss_hash_update,\n\t.rss_hash_conf_get = i40e_dev_rss_hash_conf_get,\n\t.udp_tunnel_add = i40e_dev_udp_tunnel_add,\n\t.udp_tunnel_del = i40e_dev_udp_tunnel_del,\n\t.filter_ctrl = i40e_dev_filter_ctrl,\n\t.mirror_rule_set = i40e_mirror_rule_set,\n\t.mirror_rule_reset = i40e_mirror_rule_reset,\n\t.timesync_enable = i40e_timesync_enable,\n\t.timesync_disable = i40e_timesync_disable,\n\t.timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,\n\t.timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,\n};\n\nstatic struct eth_driver rte_i40e_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_i40e_pmd\",\n\t\t.id_table = pci_id_i40e_map,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |\n\t\t\tRTE_PCI_DRV_DETACHABLE,\n\t},\n\t.eth_dev_init = eth_i40e_dev_init,\n\t.eth_dev_uninit = eth_i40e_dev_uninit,\n\t.dev_private_size = sizeof(struct i40e_adapter),\n};\n\nstatic inline int\nrte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = link;\n\tstruct rte_eth_link *src = &(dev->data->dev_link);\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic inline int\nrte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = &(dev->data->dev_link);\n\tstruct rte_eth_link *src = link;\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * Driver initialization routine.\n * Invoked once at EAL init time.\n * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.\n */\nstatic int\nrte_i40e_pmd_init(const char *name __rte_unused,\n\t\t const char *params __rte_unused)\n{\n\tPMD_INIT_FUNC_TRACE();\n\trte_eth_driver_register(&rte_i40e_pmd);\n\n\treturn 0;\n}\n\nstatic struct rte_driver rte_i40e_driver = {\n\t.type = PMD_PDEV,\n\t.init = rte_i40e_pmd_init,\n};\n\nPMD_REGISTER_DRIVER(rte_i40e_driver);\n\n/*\n * Initialize registers for flexible payload, which should be set by NVM.\n * This should be removed from code once it is fixed in NVM.\n */\n#ifndef I40E_GLQF_ORT\n#define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))\n#endif\n#ifndef I40E_GLQF_PIT\n#define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))\n#endif\n\nstatic inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)\n{\n\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);\n\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);\n\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);\n\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);\n\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);\n\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);\n\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);\n\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);\n\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);\n\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);\n\n\t/* GLQF_PIT Registers */\n\tI40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);\n\tI40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);\n}\n\nstatic int\neth_i40e_dev_init(struct rte_eth_dev *dev)\n{\n\tstruct rte_pci_device *pci_dev;\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_vsi *vsi;\n\tint ret;\n\tuint32_t len;\n\tuint8_t aq_fail = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tdev->dev_ops = &i40e_eth_dev_ops;\n\tdev->rx_pkt_burst = i40e_recv_pkts;\n\tdev->tx_pkt_burst = i40e_xmit_pkts;\n\n\t/* for secondary processes, we don't initialise any further as primary\n\t * has already done this work. Only check we don't need a different\n\t * RX function */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY){\n\t\tif (dev->data->scattered_rx)\n\t\t\tdev->rx_pkt_burst = i40e_recv_scattered_pkts;\n\t\treturn 0;\n\t}\n\tpci_dev = dev->pci_dev;\n\tpf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n\tpf->adapter->eth_dev = dev;\n\tpf->dev_data = dev->data;\n\n\thw->back = I40E_PF_TO_ADAPTER(pf);\n\thw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);\n\tif (!hw->hw_addr) {\n\t\tPMD_INIT_LOG(ERR, \"Hardware is not available, \"\n\t\t\t \"as address is NULL\");\n\t\treturn -ENODEV;\n\t}\n\n\thw->vendor_id = pci_dev->id.vendor_id;\n\thw->device_id = pci_dev->id.device_id;\n\thw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;\n\thw->subsystem_device_id = pci_dev->id.subsystem_device_id;\n\thw->bus.device = pci_dev->addr.devid;\n\thw->bus.func = pci_dev->addr.function;\n\thw->adapter_stopped = 0;\n\n\t/* Make sure all is clean before doing PF reset */\n\ti40e_clear_hw(hw);\n\n\t/* Initialize the hardware */\n\ti40e_hw_init(hw);\n\n\t/* Reset here to make sure all is clean for each PF */\n\tret = i40e_pf_reset(hw);\n\tif (ret) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to reset pf: %d\", ret);\n\t\treturn ret;\n\t}\n\n\t/* Initialize the shared code (base driver) */\n\tret = i40e_init_shared_code(hw);\n\tif (ret) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to init shared code (base driver): %d\", ret);\n\t\treturn ret;\n\t}\n\n\t/*\n\t * To work around the NVM issue,initialize registers\n\t * for flexible payload by software.\n\t * It should be removed once issues are fixed in NVM.\n\t */\n\ti40e_flex_payload_reg_init(hw);\n\n\t/* Initialize the parameters for adminq */\n\ti40e_init_adminq_parameter(hw);\n\tret = i40e_init_adminq(hw);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to init adminq: %d\", ret);\n\t\treturn -EIO;\n\t}\n\tPMD_INIT_LOG(INFO, \"FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x\",\n\t\t hw->aq.fw_maj_ver, hw->aq.fw_min_ver,\n\t\t hw->aq.api_maj_ver, hw->aq.api_min_ver,\n\t\t ((hw->nvm.version >> 12) & 0xf),\n\t\t ((hw->nvm.version >> 4) & 0xff),\n\t\t (hw->nvm.version & 0xf), hw->nvm.eetrack);\n\n\t/* Disable LLDP */\n\tret = i40e_aq_stop_lldp(hw, true, NULL);\n\tif (ret != I40E_SUCCESS) /* Its failure can be ignored */\n\t\tPMD_INIT_LOG(INFO, \"Failed to stop lldp\");\n\n\t/* Clear PXE mode */\n\ti40e_clear_pxe_mode(hw);\n\n\t/*\n\t * On X710, performance number is far from the expectation on recent\n\t * firmware versions. The fix for this issue may not be integrated in\n\t * the following firmware version. So the workaround in software driver\n\t * is needed. It needs to modify the initial values of 3 internal only\n\t * registers. Note that the workaround can be removed when it is fixed\n\t * in firmware in the future.\n\t */\n\ti40e_configure_registers(hw);\n\n\t/* Get hw capabilities */\n\tret = i40e_get_cap(hw);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to get capabilities: %d\", ret);\n\t\tgoto err_get_capabilities;\n\t}\n\n\t/* Initialize parameters for PF */\n\tret = i40e_pf_parameter_init(dev);\n\tif (ret != 0) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to do parameter init: %d\", ret);\n\t\tgoto err_parameter_init;\n\t}\n\n\t/* Initialize the queue management */\n\tret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);\n\tif (ret < 0) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to init queue pool\");\n\t\tgoto err_qp_pool_init;\n\t}\n\tret = i40e_res_pool_init(&pf->msix_pool, 1,\n\t\t\t\thw->func_caps.num_msix_vectors - 1);\n\tif (ret < 0) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to init MSIX pool\");\n\t\tgoto err_msix_pool_init;\n\t}\n\n\t/* Initialize lan hmc */\n\tret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,\n\t\t\t\thw->func_caps.num_rx_qp, 0, 0);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to init lan hmc: %d\", ret);\n\t\tgoto err_init_lan_hmc;\n\t}\n\n\t/* Configure lan hmc */\n\tret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to configure lan hmc: %d\", ret);\n\t\tgoto err_configure_lan_hmc;\n\t}\n\n\t/* Get and check the mac address */\n\ti40e_get_mac_addr(hw, hw->mac.addr);\n\tif (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"mac address is not valid\");\n\t\tret = -EIO;\n\t\tgoto err_get_mac_addr;\n\t}\n\t/* Copy the permanent MAC address */\n\tether_addr_copy((struct ether_addr *) hw->mac.addr,\n\t\t\t(struct ether_addr *) hw->mac.perm_addr);\n\n\t/* Disable flow control */\n\thw->fc.requested_mode = I40E_FC_NONE;\n\ti40e_set_fc(hw, &aq_fail, TRUE);\n\n\t/* PF setup, which includes VSI setup */\n\tret = i40e_pf_setup(pf);\n\tif (ret) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to setup pf switch: %d\", ret);\n\t\tgoto err_setup_pf_switch;\n\t}\n\n\tvsi = pf->main_vsi;\n\n\t/* Disable double vlan by default */\n\ti40e_vsi_config_double_vlan(vsi, FALSE);\n\n\tif (!vsi->max_macaddrs)\n\t\tlen = ETHER_ADDR_LEN;\n\telse\n\t\tlen = ETHER_ADDR_LEN * vsi->max_macaddrs;\n\n\t/* Should be after VSI initialized */\n\tdev->data->mac_addrs = rte_zmalloc(\"i40e\", len, 0);\n\tif (!dev->data->mac_addrs) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to allocated memory \"\n\t\t\t\t\t\"for storing mac address\");\n\t\tgoto err_mac_alloc;\n\t}\n\tether_addr_copy((struct ether_addr *)hw->mac.perm_addr,\n\t\t\t\t\t&dev->data->mac_addrs[0]);\n\n\t/* initialize pf host driver to setup SRIOV resource if applicable */\n\ti40e_pf_host_init(dev);\n\n\t/* register callback func to eal lib */\n\trte_intr_callback_register(&(pci_dev->intr_handle),\n\t\ti40e_dev_interrupt_handler, (void *)dev);\n\n\t/* configure and enable device interrupt */\n\ti40e_pf_config_irq0(hw);\n\ti40e_pf_enable_irq0(hw);\n\n\t/* enable uio intr after callback register */\n\trte_intr_enable(&(pci_dev->intr_handle));\n\n\t/* initialize mirror rule list */\n\tTAILQ_INIT(&pf->mirror_list);\n\n\treturn 0;\n\nerr_mac_alloc:\n\ti40e_vsi_release(pf->main_vsi);\nerr_setup_pf_switch:\nerr_get_mac_addr:\nerr_configure_lan_hmc:\n\t(void)i40e_shutdown_lan_hmc(hw);\nerr_init_lan_hmc:\n\ti40e_res_pool_destroy(&pf->msix_pool);\nerr_msix_pool_init:\n\ti40e_res_pool_destroy(&pf->qp_pool);\nerr_qp_pool_init:\nerr_parameter_init:\nerr_get_capabilities:\n\t(void)i40e_shutdown_adminq(hw);\n\n\treturn ret;\n}\n\nstatic int\neth_i40e_dev_uninit(struct rte_eth_dev *dev)\n{\n\tstruct rte_pci_device *pci_dev;\n\tstruct i40e_hw *hw;\n\tstruct i40e_filter_control_settings settings;\n\tint ret;\n\tuint8_t aq_fail = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn 0;\n\n\thw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tpci_dev = dev->pci_dev;\n\n\tif (hw->adapter_stopped == 0)\n\t\ti40e_dev_close(dev);\n\n\tdev->dev_ops = NULL;\n\tdev->rx_pkt_burst = NULL;\n\tdev->tx_pkt_burst = NULL;\n\n\t/* Disable LLDP */\n\tret = i40e_aq_stop_lldp(hw, true, NULL);\n\tif (ret != I40E_SUCCESS) /* Its failure can be ignored */\n\t\tPMD_INIT_LOG(INFO, \"Failed to stop lldp\");\n\n\t/* Clear PXE mode */\n\ti40e_clear_pxe_mode(hw);\n\n\t/* Unconfigure filter control */\n\tmemset(&settings, 0, sizeof(settings));\n\tret = i40e_set_filter_control(hw, &settings);\n\tif (ret)\n\t\tPMD_INIT_LOG(WARNING, \"setup_pf_filter_control failed: %d\",\n\t\t\t\t\tret);\n\n\t/* Disable flow control */\n\thw->fc.requested_mode = I40E_FC_NONE;\n\ti40e_set_fc(hw, &aq_fail, TRUE);\n\n\t/* uninitialize pf host driver */\n\ti40e_pf_host_uninit(dev);\n\n\trte_free(dev->data->mac_addrs);\n\tdev->data->mac_addrs = NULL;\n\n\t/* disable uio intr before callback unregister */\n\trte_intr_disable(&(pci_dev->intr_handle));\n\n\t/* register callback func to eal lib */\n\trte_intr_callback_unregister(&(pci_dev->intr_handle),\n\t\ti40e_dev_interrupt_handler, (void *)dev);\n\n\treturn 0;\n}\n\nstatic int\ni40e_dev_configure(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tenum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;\n\tint ret;\n\n\tif (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {\n\t\tret = i40e_fdir_setup(pf);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to setup flow director.\");\n\t\t\treturn -ENOTSUP;\n\t\t}\n\t\tret = i40e_fdir_configure(dev);\n\t\tif (ret < 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"failed to configure fdir.\");\n\t\t\tgoto err;\n\t\t}\n\t} else\n\t\ti40e_fdir_teardown(pf);\n\n\tret = i40e_dev_init_vlan(dev);\n\tif (ret < 0)\n\t\tgoto err;\n\n\t/* VMDQ setup.\n\t * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and\n\t * RSS setting have different requirements.\n\t * General PMD driver call sequence are NIC init, configure,\n\t * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it\n\t * will try to lookup the VSI that specific queue belongs to if VMDQ\n\t * applicable. So, VMDQ setting has to be done before\n\t * rx/tx_queue_setup(). This function is good to place vmdq_setup.\n\t * For RSS setting, it will try to calculate actual configured RX queue\n\t * number, which will be available after rx_queue_setup(). dev_start()\n\t * function is good to place RSS setup.\n\t */\n\tif (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {\n\t\tret = i40e_vmdq_setup(dev);\n\t\tif (ret)\n\t\t\tgoto err;\n\t}\n\treturn 0;\nerr:\n\ti40e_fdir_teardown(pf);\n\treturn ret;\n}\n\nvoid\ni40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)\n{\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\tuint16_t msix_vect = vsi->msix_intr;\n\tuint16_t i;\n\n\tfor (i = 0; i < vsi->nb_qps; i++) {\n\t\tI40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);\n\t\tI40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);\n\t\trte_wmb();\n\t}\n\n\tif (vsi->type != I40E_VSI_SRIOV) {\n\t\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);\n\t\tI40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,\n\t\t\t\tmsix_vect - 1), 0);\n\t} else {\n\t\tuint32_t reg;\n\t\treg = (hw->func_caps.num_msix_vectors_vf - 1) *\n\t\t\tvsi->user_param + (msix_vect - 1);\n\n\t\tI40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);\n\t}\n\tI40E_WRITE_FLUSH(hw);\n}\n\nstatic inline uint16_t\ni40e_calc_itr_interval(int16_t interval)\n{\n\tif (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)\n\t\tinterval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;\n\n\t/* Convert to hardware count, as writing each 1 represents 2 us */\n\treturn (interval/2);\n}\n\nvoid\ni40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)\n{\n\tuint32_t val;\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\tuint16_t msix_vect = vsi->msix_intr;\n\tint i;\n\n\tfor (i = 0; i < vsi->nb_qps; i++)\n\t\tI40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);\n\n\t/* Bind all RX queues to allocated MSIX interrupt */\n\tfor (i = 0; i < vsi->nb_qps; i++) {\n\t\tval = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |\n\t\t\tI40E_QINT_RQCTL_ITR_INDX_MASK |\n\t\t\t((vsi->base_queue + i + 1) <<\n\t\t\tI40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |\n\t\t\t(0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |\n\t\t\tI40E_QINT_RQCTL_CAUSE_ENA_MASK;\n\n\t\tif (i == vsi->nb_qps - 1)\n\t\t\tval |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;\n\t\tI40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);\n\t}\n\n\t/* Write first RX queue to Link list register as the head element */\n\tif (vsi->type != I40E_VSI_SRIOV) {\n\t\tuint16_t interval =\n\t\t\ti40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);\n\n\t\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),\n\t\t\t\t\t\t(vsi->base_queue <<\n\t\t\t\tI40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |\n\t\t\t(0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));\n\n\t\tI40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,\n\t\t\t\t\t\tmsix_vect - 1), interval);\n\n#ifndef I40E_GLINT_CTL\n#define I40E_GLINT_CTL 0x0003F800\n#define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4\n#endif\n\t\t/* Disable auto-mask on enabling of all none-zero interrupt */\n\t\tI40E_WRITE_REG(hw, I40E_GLINT_CTL,\n\t\t\tI40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);\n\t} else {\n\t\tuint32_t reg;\n\n\t\t/* num_msix_vectors_vf needs to minus irq0 */\n\t\treg = (hw->func_caps.num_msix_vectors_vf - 1) *\n\t\t\tvsi->user_param + (msix_vect - 1);\n\n\t\tI40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<\n\t\t\t\t\tI40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |\n\t\t\t\t(0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));\n\t}\n\n\tI40E_WRITE_FLUSH(hw);\n}\n\nstatic void\ni40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)\n{\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\tuint16_t interval = i40e_calc_itr_interval(\\\n\t\t\tRTE_LIBRTE_I40E_ITR_INTERVAL);\n\n\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),\n\t\t\t\t\tI40E_PFINT_DYN_CTLN_INTENA_MASK |\n\t\t\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n\t\t\t\t(0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n\t\t\t(interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));\n}\n\nstatic void\ni40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)\n{\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\n\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);\n}\n\nstatic inline uint8_t\ni40e_parse_link_speed(uint16_t eth_link_speed)\n{\n\tuint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;\n\n\tswitch (eth_link_speed) {\n\tcase ETH_LINK_SPEED_40G:\n\t\tlink_speed = I40E_LINK_SPEED_40GB;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_20G:\n\t\tlink_speed = I40E_LINK_SPEED_20GB;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_10G:\n\t\tlink_speed = I40E_LINK_SPEED_10GB;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_1000:\n\t\tlink_speed = I40E_LINK_SPEED_1GB;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_100:\n\t\tlink_speed = I40E_LINK_SPEED_100MB;\n\t\tbreak;\n\t}\n\n\treturn link_speed;\n}\n\nstatic int\ni40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)\n{\n\tenum i40e_status_code status;\n\tstruct i40e_aq_get_phy_abilities_resp phy_ab;\n\tstruct i40e_aq_set_phy_config phy_conf;\n\tconst uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |\n\t\t\tI40E_AQ_PHY_FLAG_PAUSE_RX |\n\t\t\tI40E_AQ_PHY_FLAG_LOW_POWER;\n\tconst uint8_t advt = I40E_LINK_SPEED_40GB |\n\t\t\tI40E_LINK_SPEED_10GB |\n\t\t\tI40E_LINK_SPEED_1GB |\n\t\t\tI40E_LINK_SPEED_100MB;\n\tint ret = -ENOTSUP;\n\n\t/* Skip it on 40G interfaces, as a workaround for the link issue */\n\tif (i40e_is_40G_device(hw->device_id))\n\t\treturn I40E_SUCCESS;\n\n\tstatus = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,\n\t\t\t\t\t NULL);\n\tif (status)\n\t\treturn ret;\n\n\tmemset(&phy_conf, 0, sizeof(phy_conf));\n\n\t/* bits 0-2 use the values from get_phy_abilities_resp */\n\tabilities &= ~mask;\n\tabilities |= phy_ab.abilities & mask;\n\n\t/* update ablities and speed */\n\tif (abilities & I40E_AQ_PHY_AN_ENABLED)\n\t\tphy_conf.link_speed = advt;\n\telse\n\t\tphy_conf.link_speed = force_speed;\n\n\tphy_conf.abilities = abilities;\n\n\t/* use get_phy_abilities_resp value for the rest */\n\tphy_conf.phy_type = phy_ab.phy_type;\n\tphy_conf.eee_capability = phy_ab.eee_capability;\n\tphy_conf.eeer = phy_ab.eeer_val;\n\tphy_conf.low_power_ctrl = phy_ab.d3_lpan;\n\n\tPMD_DRV_LOG(DEBUG, \"\\tCurrent: abilities %x, link_speed %x\",\n\t\t phy_ab.abilities, phy_ab.link_speed);\n\tPMD_DRV_LOG(DEBUG, \"\\tConfig: abilities %x, link_speed %x\",\n\t\t phy_conf.abilities, phy_conf.link_speed);\n\n\tstatus = i40e_aq_set_phy_config(hw, &phy_conf, NULL);\n\tif (status)\n\t\treturn ret;\n\n\treturn I40E_SUCCESS;\n}\n\nstatic int\ni40e_apply_link_speed(struct rte_eth_dev *dev)\n{\n\tuint8_t speed;\n\tuint8_t abilities = 0;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct rte_eth_conf *conf = &dev->data->dev_conf;\n\n\tspeed = i40e_parse_link_speed(conf->link_speed);\n\tabilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;\n\tif (conf->link_speed == ETH_LINK_SPEED_AUTONEG)\n\t\tabilities |= I40E_AQ_PHY_AN_ENABLED;\n\telse\n\t\tabilities |= I40E_AQ_PHY_LINK_ENABLED;\n\n\treturn i40e_phy_conf_link(hw, abilities, speed);\n}\n\nstatic int\ni40e_dev_start(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_vsi *main_vsi = pf->main_vsi;\n\tint ret, i;\n\n\thw->adapter_stopped = 0;\n\n\tif ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&\n\t\t(dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {\n\t\tPMD_INIT_LOG(ERR, \"Invalid link_duplex (%hu) for port %hhu\",\n\t\t\t dev->data->dev_conf.link_duplex,\n\t\t\t dev->data->port_id);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Initialize VSI */\n\tret = i40e_dev_rxtx_init(pf);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to init rx/tx queues\");\n\t\tgoto err_up;\n\t}\n\n\t/* Map queues with MSIX interrupt */\n\ti40e_vsi_queues_bind_intr(main_vsi);\n\ti40e_vsi_enable_queues_intr(main_vsi);\n\n\t/* Map VMDQ VSI queues with MSIX interrupt */\n\tfor (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {\n\t\ti40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);\n\t\ti40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);\n\t}\n\n\t/* enable FDIR MSIX interrupt */\n\tif (pf->fdir.fdir_vsi) {\n\t\ti40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);\n\t\ti40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);\n\t}\n\n\t/* Enable all queues which have been configured */\n\tret = i40e_dev_switch_queues(pf, TRUE);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to enable VSI\");\n\t\tgoto err_up;\n\t}\n\n\t/* Enable receiving broadcast packets */\n\tret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);\n\tif (ret != I40E_SUCCESS)\n\t\tPMD_DRV_LOG(INFO, \"fail to set vsi broadcast\");\n\n\tfor (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {\n\t\tret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,\n\t\t\t\t\t\ttrue, NULL);\n\t\tif (ret != I40E_SUCCESS)\n\t\t\tPMD_DRV_LOG(INFO, \"fail to set vsi broadcast\");\n\t}\n\n\t/* Apply link configure */\n\tret = i40e_apply_link_speed(dev);\n\tif (I40E_SUCCESS != ret) {\n\t\tPMD_DRV_LOG(ERR, \"Fail to apply link setting\");\n\t\tgoto err_up;\n\t}\n\n\treturn I40E_SUCCESS;\n\nerr_up:\n\ti40e_dev_switch_queues(pf, FALSE);\n\ti40e_dev_clear_queues(dev);\n\n\treturn ret;\n}\n\nstatic void\ni40e_dev_stop(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_vsi *main_vsi = pf->main_vsi;\n\tstruct i40e_mirror_rule *p_mirror;\n\tint i;\n\n\t/* Disable all queues */\n\ti40e_dev_switch_queues(pf, FALSE);\n\n\t/* un-map queues with interrupt registers */\n\ti40e_vsi_disable_queues_intr(main_vsi);\n\ti40e_vsi_queues_unbind_intr(main_vsi);\n\n\tfor (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {\n\t\ti40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);\n\t\ti40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);\n\t}\n\n\tif (pf->fdir.fdir_vsi) {\n\t\ti40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);\n\t\ti40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);\n\t}\n\t/* Clear all queues and release memory */\n\ti40e_dev_clear_queues(dev);\n\n\t/* Set link down */\n\ti40e_dev_set_link_down(dev);\n\n\t/* Remove all mirror rules */\n\twhile ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {\n\t\tTAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);\n\t\trte_free(p_mirror);\n\t}\n\tpf->nb_mirror_rule = 0;\n\n}\n\nstatic void\ni40e_dev_close(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t reg;\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\ti40e_dev_stop(dev);\n\thw->adapter_stopped = 1;\n\ti40e_dev_free_queues(dev);\n\n\t/* Disable interrupt */\n\ti40e_pf_disable_irq0(hw);\n\trte_intr_disable(&(dev->pci_dev->intr_handle));\n\n\t/* shutdown and destroy the HMC */\n\ti40e_shutdown_lan_hmc(hw);\n\n\t/* release all the existing VSIs and VEBs */\n\ti40e_fdir_teardown(pf);\n\ti40e_vsi_release(pf->main_vsi);\n\n\tfor (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {\n\t\ti40e_vsi_release(pf->vmdq[i].vsi);\n\t\tpf->vmdq[i].vsi = NULL;\n\t}\n\n\trte_free(pf->vmdq);\n\tpf->vmdq = NULL;\n\n\t/* shutdown the adminq */\n\ti40e_aq_queue_shutdown(hw, true);\n\ti40e_shutdown_adminq(hw);\n\n\ti40e_res_pool_destroy(&pf->qp_pool);\n\ti40e_res_pool_destroy(&pf->msix_pool);\n\n\t/* force a PF reset to clean anything leftover */\n\treg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);\n\tI40E_WRITE_REG(hw, I40E_PFGEN_CTRL,\n\t\t\t(reg | I40E_PFGEN_CTRL_PFSWR_MASK));\n\tI40E_WRITE_FLUSH(hw);\n}\n\nstatic void\ni40e_dev_promiscuous_enable(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_vsi *vsi = pf->main_vsi;\n\tint status;\n\n\tstatus = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,\n\t\t\t\t\t\t\ttrue, NULL);\n\tif (status != I40E_SUCCESS)\n\t\tPMD_DRV_LOG(ERR, \"Failed to enable unicast promiscuous\");\n\n\tstatus = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,\n\t\t\t\t\t\t\tTRUE, NULL);\n\tif (status != I40E_SUCCESS)\n\t\tPMD_DRV_LOG(ERR, \"Failed to enable multicast promiscuous\");\n\n}\n\nstatic void\ni40e_dev_promiscuous_disable(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_vsi *vsi = pf->main_vsi;\n\tint status;\n\n\tstatus = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,\n\t\t\t\t\t\t\tfalse, NULL);\n\tif (status != I40E_SUCCESS)\n\t\tPMD_DRV_LOG(ERR, \"Failed to disable unicast promiscuous\");\n\n\tstatus = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,\n\t\t\t\t\t\t\tfalse, NULL);\n\tif (status != I40E_SUCCESS)\n\t\tPMD_DRV_LOG(ERR, \"Failed to disable multicast promiscuous\");\n}\n\nstatic void\ni40e_dev_allmulticast_enable(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_vsi *vsi = pf->main_vsi;\n\tint ret;\n\n\tret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);\n\tif (ret != I40E_SUCCESS)\n\t\tPMD_DRV_LOG(ERR, \"Failed to enable multicast promiscuous\");\n}\n\nstatic void\ni40e_dev_allmulticast_disable(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_vsi *vsi = pf->main_vsi;\n\tint ret;\n\n\tif (dev->data->promiscuous == 1)\n\t\treturn; /* must remain in all_multicast mode */\n\n\tret = i40e_aq_set_vsi_multicast_promiscuous(hw,\n\t\t\t\tvsi->seid, FALSE, NULL);\n\tif (ret != I40E_SUCCESS)\n\t\tPMD_DRV_LOG(ERR, \"Failed to disable multicast promiscuous\");\n}\n\n/*\n * Set device link up.\n */\nstatic int\ni40e_dev_set_link_up(struct rte_eth_dev *dev)\n{\n\t/* re-apply link speed setting */\n\treturn i40e_apply_link_speed(dev);\n}\n\n/*\n * Set device link down.\n */\nstatic int\ni40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)\n{\n\tuint8_t speed = I40E_LINK_SPEED_UNKNOWN;\n\tuint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\treturn i40e_phy_conf_link(hw, abilities, speed);\n}\n\nint\ni40e_dev_link_update(struct rte_eth_dev *dev,\n\t\t int wait_to_complete)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_link_status link_status;\n\tstruct rte_eth_link link, old;\n\tint status;\n\tunsigned rep_cnt = MAX_REPEAT_TIME;\n\n\tmemset(&link, 0, sizeof(link));\n\tmemset(&old, 0, sizeof(old));\n\tmemset(&link_status, 0, sizeof(link_status));\n\trte_i40e_dev_atomic_read_link_status(dev, &old);\n\n\tdo {\n\t\t/* Get link status information from hardware */\n\t\tstatus = i40e_aq_get_link_info(hw, false, &link_status, NULL);\n\t\tif (status != I40E_SUCCESS) {\n\t\t\tlink.link_speed = ETH_LINK_SPEED_100;\n\t\t\tlink.link_duplex = ETH_LINK_FULL_DUPLEX;\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to get link info\");\n\t\t\tgoto out;\n\t\t}\n\n\t\tlink.link_status = link_status.link_info & I40E_AQ_LINK_UP;\n\t\tif (!wait_to_complete)\n\t\t\tbreak;\n\n\t\trte_delay_ms(CHECK_INTERVAL);\n\t} while (!link.link_status && rep_cnt--);\n\n\tif (!link.link_status)\n\t\tgoto out;\n\n\t/* i40e uses full duplex only */\n\tlink.link_duplex = ETH_LINK_FULL_DUPLEX;\n\n\t/* Parse the link status */\n\tswitch (link_status.link_speed) {\n\tcase I40E_LINK_SPEED_100MB:\n\t\tlink.link_speed = ETH_LINK_SPEED_100;\n\t\tbreak;\n\tcase I40E_LINK_SPEED_1GB:\n\t\tlink.link_speed = ETH_LINK_SPEED_1000;\n\t\tbreak;\n\tcase I40E_LINK_SPEED_10GB:\n\t\tlink.link_speed = ETH_LINK_SPEED_10G;\n\t\tbreak;\n\tcase I40E_LINK_SPEED_20GB:\n\t\tlink.link_speed = ETH_LINK_SPEED_20G;\n\t\tbreak;\n\tcase I40E_LINK_SPEED_40GB:\n\t\tlink.link_speed = ETH_LINK_SPEED_40G;\n\t\tbreak;\n\tdefault:\n\t\tlink.link_speed = ETH_LINK_SPEED_100;\n\t\tbreak;\n\t}\n\nout:\n\trte_i40e_dev_atomic_write_link_status(dev, &link);\n\tif (link.link_status == old.link_status)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/* Get all the statistics of a VSI */\nvoid\ni40e_update_vsi_stats(struct i40e_vsi *vsi)\n{\n\tstruct i40e_eth_stats *oes = &vsi->eth_stats_offset;\n\tstruct i40e_eth_stats *nes = &vsi->eth_stats;\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\tint idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);\n\n\ti40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),\n\t\t\t vsi->offset_loaded, &oes->rx_bytes,\n\t\t\t &nes->rx_bytes);\n\ti40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),\n\t\t\t vsi->offset_loaded, &oes->rx_unicast,\n\t\t\t &nes->rx_unicast);\n\ti40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),\n\t\t\t vsi->offset_loaded, &oes->rx_multicast,\n\t\t\t &nes->rx_multicast);\n\ti40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),\n\t\t\t vsi->offset_loaded, &oes->rx_broadcast,\n\t\t\t &nes->rx_broadcast);\n\ti40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,\n\t\t\t &oes->rx_discards, &nes->rx_discards);\n\t/* GLV_REPC not supported */\n\t/* GLV_RMPC not supported */\n\ti40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,\n\t\t\t &oes->rx_unknown_protocol,\n\t\t\t &nes->rx_unknown_protocol);\n\ti40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),\n\t\t\t vsi->offset_loaded, &oes->tx_bytes,\n\t\t\t &nes->tx_bytes);\n\ti40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),\n\t\t\t vsi->offset_loaded, &oes->tx_unicast,\n\t\t\t &nes->tx_unicast);\n\ti40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),\n\t\t\t vsi->offset_loaded, &oes->tx_multicast,\n\t\t\t &nes->tx_multicast);\n\ti40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),\n\t\t\t vsi->offset_loaded, &oes->tx_broadcast,\n\t\t\t &nes->tx_broadcast);\n\t/* GLV_TDPC not supported */\n\ti40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,\n\t\t\t &oes->tx_errors, &nes->tx_errors);\n\tvsi->offset_loaded = true;\n\n\tPMD_DRV_LOG(DEBUG, \"***************** VSI[%u] stats start *******************\",\n\t\t vsi->vsi_id);\n\tPMD_DRV_LOG(DEBUG, \"rx_bytes: %\"PRIu64\"\", nes->rx_bytes);\n\tPMD_DRV_LOG(DEBUG, \"rx_unicast: %\"PRIu64\"\", nes->rx_unicast);\n\tPMD_DRV_LOG(DEBUG, \"rx_multicast: %\"PRIu64\"\", nes->rx_multicast);\n\tPMD_DRV_LOG(DEBUG, \"rx_broadcast: %\"PRIu64\"\", nes->rx_broadcast);\n\tPMD_DRV_LOG(DEBUG, \"rx_discards: %\"PRIu64\"\", nes->rx_discards);\n\tPMD_DRV_LOG(DEBUG, \"rx_unknown_protocol: %\"PRIu64\"\",\n\t\t nes->rx_unknown_protocol);\n\tPMD_DRV_LOG(DEBUG, \"tx_bytes: %\"PRIu64\"\", nes->tx_bytes);\n\tPMD_DRV_LOG(DEBUG, \"tx_unicast: %\"PRIu64\"\", nes->tx_unicast);\n\tPMD_DRV_LOG(DEBUG, \"tx_multicast: %\"PRIu64\"\", nes->tx_multicast);\n\tPMD_DRV_LOG(DEBUG, \"tx_broadcast: %\"PRIu64\"\", nes->tx_broadcast);\n\tPMD_DRV_LOG(DEBUG, \"tx_discards: %\"PRIu64\"\", nes->tx_discards);\n\tPMD_DRV_LOG(DEBUG, \"tx_errors: %\"PRIu64\"\", nes->tx_errors);\n\tPMD_DRV_LOG(DEBUG, \"***************** VSI[%u] stats end *******************\",\n\t\t vsi->vsi_id);\n}\n\n/* Get all statistics of a port */\nstatic void\ni40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tuint32_t i;\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_hw_port_stats *ns = &pf->stats; /* new stats */\n\tstruct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */\n\n\t/* Get statistics of struct i40e_eth_stats */\n\ti40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),\n\t\t\t I40E_GLPRT_GORCL(hw->port),\n\t\t\t pf->offset_loaded, &os->eth.rx_bytes,\n\t\t\t &ns->eth.rx_bytes);\n\ti40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),\n\t\t\t I40E_GLPRT_UPRCL(hw->port),\n\t\t\t pf->offset_loaded, &os->eth.rx_unicast,\n\t\t\t &ns->eth.rx_unicast);\n\ti40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),\n\t\t\t I40E_GLPRT_MPRCL(hw->port),\n\t\t\t pf->offset_loaded, &os->eth.rx_multicast,\n\t\t\t &ns->eth.rx_multicast);\n\ti40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),\n\t\t\t I40E_GLPRT_BPRCL(hw->port),\n\t\t\t pf->offset_loaded, &os->eth.rx_broadcast,\n\t\t\t &ns->eth.rx_broadcast);\n\ti40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),\n\t\t\t pf->offset_loaded, &os->eth.rx_discards,\n\t\t\t &ns->eth.rx_discards);\n\t/* GLPRT_REPC not supported */\n\t/* GLPRT_RMPC not supported */\n\ti40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),\n\t\t\t pf->offset_loaded,\n\t\t\t &os->eth.rx_unknown_protocol,\n\t\t\t &ns->eth.rx_unknown_protocol);\n\ti40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),\n\t\t\t I40E_GLPRT_GOTCL(hw->port),\n\t\t\t pf->offset_loaded, &os->eth.tx_bytes,\n\t\t\t &ns->eth.tx_bytes);\n\ti40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),\n\t\t\t I40E_GLPRT_UPTCL(hw->port),\n\t\t\t pf->offset_loaded, &os->eth.tx_unicast,\n\t\t\t &ns->eth.tx_unicast);\n\ti40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),\n\t\t\t I40E_GLPRT_MPTCL(hw->port),\n\t\t\t pf->offset_loaded, &os->eth.tx_multicast,\n\t\t\t &ns->eth.tx_multicast);\n\ti40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),\n\t\t\t I40E_GLPRT_BPTCL(hw->port),\n\t\t\t pf->offset_loaded, &os->eth.tx_broadcast,\n\t\t\t &ns->eth.tx_broadcast);\n\t/* GLPRT_TEPC not supported */\n\n\t/* additional port specific stats */\n\ti40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),\n\t\t\t pf->offset_loaded, &os->tx_dropped_link_down,\n\t\t\t &ns->tx_dropped_link_down);\n\ti40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),\n\t\t\t pf->offset_loaded, &os->crc_errors,\n\t\t\t &ns->crc_errors);\n\ti40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),\n\t\t\t pf->offset_loaded, &os->illegal_bytes,\n\t\t\t &ns->illegal_bytes);\n\t/* GLPRT_ERRBC not supported */\n\ti40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),\n\t\t\t pf->offset_loaded, &os->mac_local_faults,\n\t\t\t &ns->mac_local_faults);\n\ti40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),\n\t\t\t pf->offset_loaded, &os->mac_remote_faults,\n\t\t\t &ns->mac_remote_faults);\n\ti40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),\n\t\t\t pf->offset_loaded, &os->rx_length_errors,\n\t\t\t &ns->rx_length_errors);\n\ti40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),\n\t\t\t pf->offset_loaded, &os->link_xon_rx,\n\t\t\t &ns->link_xon_rx);\n\ti40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),\n\t\t\t pf->offset_loaded, &os->link_xoff_rx,\n\t\t\t &ns->link_xoff_rx);\n\tfor (i = 0; i < 8; i++) {\n\t\ti40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),\n\t\t\t\t pf->offset_loaded,\n\t\t\t\t &os->priority_xon_rx[i],\n\t\t\t\t &ns->priority_xon_rx[i]);\n\t\ti40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),\n\t\t\t\t pf->offset_loaded,\n\t\t\t\t &os->priority_xoff_rx[i],\n\t\t\t\t &ns->priority_xoff_rx[i]);\n\t}\n\ti40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),\n\t\t\t pf->offset_loaded, &os->link_xon_tx,\n\t\t\t &ns->link_xon_tx);\n\ti40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),\n\t\t\t pf->offset_loaded, &os->link_xoff_tx,\n\t\t\t &ns->link_xoff_tx);\n\tfor (i = 0; i < 8; i++) {\n\t\ti40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),\n\t\t\t\t pf->offset_loaded,\n\t\t\t\t &os->priority_xon_tx[i],\n\t\t\t\t &ns->priority_xon_tx[i]);\n\t\ti40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),\n\t\t\t\t pf->offset_loaded,\n\t\t\t\t &os->priority_xoff_tx[i],\n\t\t\t\t &ns->priority_xoff_tx[i]);\n\t\ti40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),\n\t\t\t\t pf->offset_loaded,\n\t\t\t\t &os->priority_xon_2_xoff[i],\n\t\t\t\t &ns->priority_xon_2_xoff[i]);\n\t}\n\ti40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),\n\t\t\t I40E_GLPRT_PRC64L(hw->port),\n\t\t\t pf->offset_loaded, &os->rx_size_64,\n\t\t\t &ns->rx_size_64);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),\n\t\t\t I40E_GLPRT_PRC127L(hw->port),\n\t\t\t pf->offset_loaded, &os->rx_size_127,\n\t\t\t &ns->rx_size_127);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),\n\t\t\t I40E_GLPRT_PRC255L(hw->port),\n\t\t\t pf->offset_loaded, &os->rx_size_255,\n\t\t\t &ns->rx_size_255);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),\n\t\t\t I40E_GLPRT_PRC511L(hw->port),\n\t\t\t pf->offset_loaded, &os->rx_size_511,\n\t\t\t &ns->rx_size_511);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),\n\t\t\t I40E_GLPRT_PRC1023L(hw->port),\n\t\t\t pf->offset_loaded, &os->rx_size_1023,\n\t\t\t &ns->rx_size_1023);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),\n\t\t\t I40E_GLPRT_PRC1522L(hw->port),\n\t\t\t pf->offset_loaded, &os->rx_size_1522,\n\t\t\t &ns->rx_size_1522);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),\n\t\t\t I40E_GLPRT_PRC9522L(hw->port),\n\t\t\t pf->offset_loaded, &os->rx_size_big,\n\t\t\t &ns->rx_size_big);\n\ti40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),\n\t\t\t pf->offset_loaded, &os->rx_undersize,\n\t\t\t &ns->rx_undersize);\n\ti40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),\n\t\t\t pf->offset_loaded, &os->rx_fragments,\n\t\t\t &ns->rx_fragments);\n\ti40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),\n\t\t\t pf->offset_loaded, &os->rx_oversize,\n\t\t\t &ns->rx_oversize);\n\ti40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),\n\t\t\t pf->offset_loaded, &os->rx_jabber,\n\t\t\t &ns->rx_jabber);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),\n\t\t\t I40E_GLPRT_PTC64L(hw->port),\n\t\t\t pf->offset_loaded, &os->tx_size_64,\n\t\t\t &ns->tx_size_64);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),\n\t\t\t I40E_GLPRT_PTC127L(hw->port),\n\t\t\t pf->offset_loaded, &os->tx_size_127,\n\t\t\t &ns->tx_size_127);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),\n\t\t\t I40E_GLPRT_PTC255L(hw->port),\n\t\t\t pf->offset_loaded, &os->tx_size_255,\n\t\t\t &ns->tx_size_255);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),\n\t\t\t I40E_GLPRT_PTC511L(hw->port),\n\t\t\t pf->offset_loaded, &os->tx_size_511,\n\t\t\t &ns->tx_size_511);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),\n\t\t\t I40E_GLPRT_PTC1023L(hw->port),\n\t\t\t pf->offset_loaded, &os->tx_size_1023,\n\t\t\t &ns->tx_size_1023);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),\n\t\t\t I40E_GLPRT_PTC1522L(hw->port),\n\t\t\t pf->offset_loaded, &os->tx_size_1522,\n\t\t\t &ns->tx_size_1522);\n\ti40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),\n\t\t\t I40E_GLPRT_PTC9522L(hw->port),\n\t\t\t pf->offset_loaded, &os->tx_size_big,\n\t\t\t &ns->tx_size_big);\n\ti40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),\n\t\t\t pf->offset_loaded,\n\t\t\t &os->fd_sb_match, &ns->fd_sb_match);\n\t/* GLPRT_MSPDC not supported */\n\t/* GLPRT_XEC not supported */\n\n\tpf->offset_loaded = true;\n\n\tif (pf->main_vsi)\n\t\ti40e_update_vsi_stats(pf->main_vsi);\n\n\tstats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +\n\t\t\t\t\t\tns->eth.rx_broadcast;\n\tstats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +\n\t\t\t\t\t\tns->eth.tx_broadcast;\n\tstats->ibytes = ns->eth.rx_bytes;\n\tstats->obytes = ns->eth.tx_bytes;\n\tstats->oerrors = ns->eth.tx_errors;\n\tstats->imcasts = ns->eth.rx_multicast;\n\tstats->fdirmatch = ns->fd_sb_match;\n\n\t/* Rx Errors */\n\tstats->ibadcrc = ns->crc_errors;\n\tstats->ibadlen = ns->rx_length_errors + ns->rx_undersize +\n\t\t\tns->rx_oversize + ns->rx_fragments + ns->rx_jabber;\n\tstats->imissed = ns->eth.rx_discards;\n\tstats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;\n\n\tPMD_DRV_LOG(DEBUG, \"***************** PF stats start *******************\");\n\tPMD_DRV_LOG(DEBUG, \"rx_bytes: %\"PRIu64\"\", ns->eth.rx_bytes);\n\tPMD_DRV_LOG(DEBUG, \"rx_unicast: %\"PRIu64\"\", ns->eth.rx_unicast);\n\tPMD_DRV_LOG(DEBUG, \"rx_multicast: %\"PRIu64\"\", ns->eth.rx_multicast);\n\tPMD_DRV_LOG(DEBUG, \"rx_broadcast: %\"PRIu64\"\", ns->eth.rx_broadcast);\n\tPMD_DRV_LOG(DEBUG, \"rx_discards: %\"PRIu64\"\", ns->eth.rx_discards);\n\tPMD_DRV_LOG(DEBUG, \"rx_unknown_protocol: %\"PRIu64\"\",\n\t\t ns->eth.rx_unknown_protocol);\n\tPMD_DRV_LOG(DEBUG, \"tx_bytes: %\"PRIu64\"\", ns->eth.tx_bytes);\n\tPMD_DRV_LOG(DEBUG, \"tx_unicast: %\"PRIu64\"\", ns->eth.tx_unicast);\n\tPMD_DRV_LOG(DEBUG, \"tx_multicast: %\"PRIu64\"\", ns->eth.tx_multicast);\n\tPMD_DRV_LOG(DEBUG, \"tx_broadcast: %\"PRIu64\"\", ns->eth.tx_broadcast);\n\tPMD_DRV_LOG(DEBUG, \"tx_discards: %\"PRIu64\"\", ns->eth.tx_discards);\n\tPMD_DRV_LOG(DEBUG, \"tx_errors: %\"PRIu64\"\", ns->eth.tx_errors);\n\n\tPMD_DRV_LOG(DEBUG, \"tx_dropped_link_down: %\"PRIu64\"\",\n\t\t ns->tx_dropped_link_down);\n\tPMD_DRV_LOG(DEBUG, \"crc_errors: %\"PRIu64\"\", ns->crc_errors);\n\tPMD_DRV_LOG(DEBUG, \"illegal_bytes: %\"PRIu64\"\",\n\t\t ns->illegal_bytes);\n\tPMD_DRV_LOG(DEBUG, \"error_bytes: %\"PRIu64\"\", ns->error_bytes);\n\tPMD_DRV_LOG(DEBUG, \"mac_local_faults: %\"PRIu64\"\",\n\t\t ns->mac_local_faults);\n\tPMD_DRV_LOG(DEBUG, \"mac_remote_faults: %\"PRIu64\"\",\n\t\t ns->mac_remote_faults);\n\tPMD_DRV_LOG(DEBUG, \"rx_length_errors: %\"PRIu64\"\",\n\t\t ns->rx_length_errors);\n\tPMD_DRV_LOG(DEBUG, \"link_xon_rx: %\"PRIu64\"\", ns->link_xon_rx);\n\tPMD_DRV_LOG(DEBUG, \"link_xoff_rx: %\"PRIu64\"\", ns->link_xoff_rx);\n\tfor (i = 0; i < 8; i++) {\n\t\tPMD_DRV_LOG(DEBUG, \"priority_xon_rx[%d]: %\"PRIu64\"\",\n\t\t\t\ti, ns->priority_xon_rx[i]);\n\t\tPMD_DRV_LOG(DEBUG, \"priority_xoff_rx[%d]: %\"PRIu64\"\",\n\t\t\t\ti, ns->priority_xoff_rx[i]);\n\t}\n\tPMD_DRV_LOG(DEBUG, \"link_xon_tx: %\"PRIu64\"\", ns->link_xon_tx);\n\tPMD_DRV_LOG(DEBUG, \"link_xoff_tx: %\"PRIu64\"\", ns->link_xoff_tx);\n\tfor (i = 0; i < 8; i++) {\n\t\tPMD_DRV_LOG(DEBUG, \"priority_xon_tx[%d]: %\"PRIu64\"\",\n\t\t\t\ti, ns->priority_xon_tx[i]);\n\t\tPMD_DRV_LOG(DEBUG, \"priority_xoff_tx[%d]: %\"PRIu64\"\",\n\t\t\t\ti, ns->priority_xoff_tx[i]);\n\t\tPMD_DRV_LOG(DEBUG, \"priority_xon_2_xoff[%d]: %\"PRIu64\"\",\n\t\t\t\ti, ns->priority_xon_2_xoff[i]);\n\t}\n\tPMD_DRV_LOG(DEBUG, \"rx_size_64: %\"PRIu64\"\", ns->rx_size_64);\n\tPMD_DRV_LOG(DEBUG, \"rx_size_127: %\"PRIu64\"\", ns->rx_size_127);\n\tPMD_DRV_LOG(DEBUG, \"rx_size_255: %\"PRIu64\"\", ns->rx_size_255);\n\tPMD_DRV_LOG(DEBUG, \"rx_size_511: %\"PRIu64\"\", ns->rx_size_511);\n\tPMD_DRV_LOG(DEBUG, \"rx_size_1023: %\"PRIu64\"\", ns->rx_size_1023);\n\tPMD_DRV_LOG(DEBUG, \"rx_size_1522: %\"PRIu64\"\", ns->rx_size_1522);\n\tPMD_DRV_LOG(DEBUG, \"rx_size_big: %\"PRIu64\"\", ns->rx_size_big);\n\tPMD_DRV_LOG(DEBUG, \"rx_undersize: %\"PRIu64\"\", ns->rx_undersize);\n\tPMD_DRV_LOG(DEBUG, \"rx_fragments: %\"PRIu64\"\", ns->rx_fragments);\n\tPMD_DRV_LOG(DEBUG, \"rx_oversize: %\"PRIu64\"\", ns->rx_oversize);\n\tPMD_DRV_LOG(DEBUG, \"rx_jabber: %\"PRIu64\"\", ns->rx_jabber);\n\tPMD_DRV_LOG(DEBUG, \"tx_size_64: %\"PRIu64\"\", ns->tx_size_64);\n\tPMD_DRV_LOG(DEBUG, \"tx_size_127: %\"PRIu64\"\", ns->tx_size_127);\n\tPMD_DRV_LOG(DEBUG, \"tx_size_255: %\"PRIu64\"\", ns->tx_size_255);\n\tPMD_DRV_LOG(DEBUG, \"tx_size_511: %\"PRIu64\"\", ns->tx_size_511);\n\tPMD_DRV_LOG(DEBUG, \"tx_size_1023: %\"PRIu64\"\", ns->tx_size_1023);\n\tPMD_DRV_LOG(DEBUG, \"tx_size_1522: %\"PRIu64\"\", ns->tx_size_1522);\n\tPMD_DRV_LOG(DEBUG, \"tx_size_big: %\"PRIu64\"\", ns->tx_size_big);\n\tPMD_DRV_LOG(DEBUG, \"mac_short_packet_dropped: %\"PRIu64\"\",\n\t\t\tns->mac_short_packet_dropped);\n\tPMD_DRV_LOG(DEBUG, \"checksum_error: %\"PRIu64\"\",\n\t\t ns->checksum_error);\n\tPMD_DRV_LOG(DEBUG, \"fdir_match: %\"PRIu64\"\", ns->fd_sb_match);\n\tPMD_DRV_LOG(DEBUG, \"***************** PF stats end ********************\");\n}\n\n/* Reset the statistics */\nstatic void\ni40e_dev_stats_reset(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\n\t/* It results in reloading the start point of each counter */\n\tpf->offset_loaded = false;\n}\n\nstatic int\ni40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,\n\t\t\t\t __rte_unused uint16_t queue_id,\n\t\t\t\t __rte_unused uint8_t stat_idx,\n\t\t\t\t __rte_unused uint8_t is_rx)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\treturn -ENOSYS;\n}\n\nstatic void\ni40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_vsi *vsi = pf->main_vsi;\n\n\tdev_info->max_rx_queues = vsi->nb_qps;\n\tdev_info->max_tx_queues = vsi->nb_qps;\n\tdev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;\n\tdev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;\n\tdev_info->max_mac_addrs = vsi->max_macaddrs;\n\tdev_info->max_vfs = dev->pci_dev->max_vfs;\n\tdev_info->rx_offload_capa =\n\t\tDEV_RX_OFFLOAD_VLAN_STRIP |\n\t\tDEV_RX_OFFLOAD_QINQ_STRIP |\n\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n\t\tDEV_RX_OFFLOAD_TCP_CKSUM;\n\tdev_info->tx_offload_capa =\n\t\tDEV_TX_OFFLOAD_VLAN_INSERT |\n\t\tDEV_TX_OFFLOAD_QINQ_INSERT |\n\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n\t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n\t\tDEV_TX_OFFLOAD_SCTP_CKSUM |\n\t\tDEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |\n\t\tDEV_TX_OFFLOAD_TCP_TSO;\n\tdev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *\n\t\t\t\t\t\tsizeof(uint32_t);\n\tdev_info->reta_size = pf->hash_lut_size;\n\tdev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;\n\n\tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n\t\t.rx_thresh = {\n\t\t\t.pthresh = I40E_DEFAULT_RX_PTHRESH,\n\t\t\t.hthresh = I40E_DEFAULT_RX_HTHRESH,\n\t\t\t.wthresh = I40E_DEFAULT_RX_WTHRESH,\n\t\t},\n\t\t.rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,\n\t\t.rx_drop_en = 0,\n\t};\n\n\tdev_info->default_txconf = (struct rte_eth_txconf) {\n\t\t.tx_thresh = {\n\t\t\t.pthresh = I40E_DEFAULT_TX_PTHRESH,\n\t\t\t.hthresh = I40E_DEFAULT_TX_HTHRESH,\n\t\t\t.wthresh = I40E_DEFAULT_TX_WTHRESH,\n\t\t},\n\t\t.tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,\n\t\t.tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,\n\t\t.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |\n\t\t\t\tETH_TXQ_FLAGS_NOOFFLOADS,\n\t};\n\n\tif (pf->flags & I40E_FLAG_VMDQ) {\n\t\tdev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;\n\t\tdev_info->vmdq_queue_base = dev_info->max_rx_queues;\n\t\tdev_info->vmdq_queue_num = pf->vmdq_nb_qps *\n\t\t\t\t\t\tpf->max_nb_vmdq_vsi;\n\t\tdev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;\n\t\tdev_info->max_rx_queues += dev_info->vmdq_queue_num;\n\t\tdev_info->max_tx_queues += dev_info->vmdq_queue_num;\n\t}\n}\n\nstatic int\ni40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_vsi *vsi = pf->main_vsi;\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (on)\n\t\treturn i40e_vsi_add_vlan(vsi, vlan_id);\n\telse\n\t\treturn i40e_vsi_delete_vlan(vsi, vlan_id);\n}\n\nstatic void\ni40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,\n\t\t __rte_unused uint16_t tpid)\n{\n\tPMD_INIT_FUNC_TRACE();\n}\n\nstatic void\ni40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_vsi *vsi = pf->main_vsi;\n\n\tif (mask & ETH_VLAN_STRIP_MASK) {\n\t\t/* Enable or disable VLAN stripping */\n\t\tif (dev->data->dev_conf.rxmode.hw_vlan_strip)\n\t\t\ti40e_vsi_config_vlan_stripping(vsi, TRUE);\n\t\telse\n\t\t\ti40e_vsi_config_vlan_stripping(vsi, FALSE);\n\t}\n\n\tif (mask & ETH_VLAN_EXTEND_MASK) {\n\t\tif (dev->data->dev_conf.rxmode.hw_vlan_extend)\n\t\t\ti40e_vsi_config_double_vlan(vsi, TRUE);\n\t\telse\n\t\t\ti40e_vsi_config_double_vlan(vsi, FALSE);\n\t}\n}\n\nstatic void\ni40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,\n\t\t\t __rte_unused uint16_t queue,\n\t\t\t __rte_unused int on)\n{\n\tPMD_INIT_FUNC_TRACE();\n}\n\nstatic int\ni40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_vsi *vsi = pf->main_vsi;\n\tstruct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);\n\tstruct i40e_vsi_vlan_pvid_info info;\n\n\tmemset(&info, 0, sizeof(info));\n\tinfo.on = on;\n\tif (info.on)\n\t\tinfo.config.pvid = pvid;\n\telse {\n\t\tinfo.config.reject.tagged =\n\t\t\t\tdata->dev_conf.txmode.hw_vlan_reject_tagged;\n\t\tinfo.config.reject.untagged =\n\t\t\t\tdata->dev_conf.txmode.hw_vlan_reject_untagged;\n\t}\n\n\treturn i40e_vsi_vlan_pvid_set(vsi, &info);\n}\n\nstatic int\ni40e_dev_led_on(struct rte_eth_dev *dev)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t mode = i40e_led_get(hw);\n\n\tif (mode == 0)\n\t\ti40e_led_set(hw, 0xf, true); /* 0xf means led always true */\n\n\treturn 0;\n}\n\nstatic int\ni40e_dev_led_off(struct rte_eth_dev *dev)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t mode = i40e_led_get(hw);\n\n\tif (mode != 0)\n\t\ti40e_led_set(hw, 0, false);\n\n\treturn 0;\n}\n\nstatic int\ni40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,\n\t\t __rte_unused struct rte_eth_fc_conf *fc_conf)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\treturn -ENOSYS;\n}\n\nstatic int\ni40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,\n\t\t\t __rte_unused struct rte_eth_pfc_conf *pfc_conf)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\treturn -ENOSYS;\n}\n\n/* Add a MAC address, and update filters */\nstatic void\ni40e_macaddr_add(struct rte_eth_dev *dev,\n\t\t struct ether_addr *mac_addr,\n\t\t __rte_unused uint32_t index,\n\t\t uint32_t pool)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_mac_filter_info mac_filter;\n\tstruct i40e_vsi *vsi;\n\tint ret;\n\n\t/* If VMDQ not enabled or configured, return */\n\tif (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {\n\t\tPMD_DRV_LOG(ERR, \"VMDQ not %s, can't set mac to pool %u\",\n\t\t\tpf->flags | I40E_FLAG_VMDQ ? \"configured\" : \"enabled\",\n\t\t\tpool);\n\t\treturn;\n\t}\n\n\tif (pool > pf->nb_cfg_vmdq_vsi) {\n\t\tPMD_DRV_LOG(ERR, \"Pool number %u invalid. Max pool is %u\",\n\t\t\t\tpool, pf->nb_cfg_vmdq_vsi);\n\t\treturn;\n\t}\n\n\t(void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);\n\tmac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;\n\n\tif (pool == 0)\n\t\tvsi = pf->main_vsi;\n\telse\n\t\tvsi = pf->vmdq[pool - 1].vsi;\n\n\tret = i40e_vsi_add_mac(vsi, &mac_filter);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to add MACVLAN filter\");\n\t\treturn;\n\t}\n}\n\n/* Remove a MAC address, and update filters */\nstatic void\ni40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_vsi *vsi;\n\tstruct rte_eth_dev_data *data = dev->data;\n\tstruct ether_addr *macaddr;\n\tint ret;\n\tuint32_t i;\n\tuint64_t pool_sel;\n\n\tmacaddr = &(data->mac_addrs[index]);\n\n\tpool_sel = dev->data->mac_pool_sel[index];\n\n\tfor (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {\n\t\tif (pool_sel & (1ULL << i)) {\n\t\t\tif (i == 0)\n\t\t\t\tvsi = pf->main_vsi;\n\t\t\telse {\n\t\t\t\t/* No VMDQ pool enabled or configured */\n\t\t\t\tif (!(pf->flags | I40E_FLAG_VMDQ) ||\n\t\t\t\t\t(i > pf->nb_cfg_vmdq_vsi)) {\n\t\t\t\t\tPMD_DRV_LOG(ERR, \"No VMDQ pool enabled\"\n\t\t\t\t\t\t\t\"/configured\");\n\t\t\t\t\treturn;\n\t\t\t\t}\n\t\t\t\tvsi = pf->vmdq[i - 1].vsi;\n\t\t\t}\n\t\t\tret = i40e_vsi_delete_mac(vsi, macaddr);\n\n\t\t\tif (ret) {\n\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to remove MACVLAN filter\");\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\t}\n}\n\n/* Set perfect match or hash match of MAC and VLAN for a VF */\nstatic int\ni40e_vf_mac_filter_set(struct i40e_pf *pf,\n\t\t struct rte_eth_mac_filter *filter,\n\t\t bool add)\n{\n\tstruct i40e_hw *hw;\n\tstruct i40e_mac_filter_info mac_filter;\n\tstruct ether_addr old_mac;\n\tstruct ether_addr *new_mac;\n\tstruct i40e_pf_vf *vf = NULL;\n\tuint16_t vf_id;\n\tint ret;\n\n\tif (pf == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid PF argument.\");\n\t\treturn -EINVAL;\n\t}\n\thw = I40E_PF_TO_HW(pf);\n\n\tif (filter == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid mac filter argument.\");\n\t\treturn -EINVAL;\n\t}\n\n\tnew_mac = &filter->mac_addr;\n\n\tif (is_zero_ether_addr(new_mac)) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid ethernet address.\");\n\t\treturn -EINVAL;\n\t}\n\n\tvf_id = filter->dst_id;\n\n\tif (vf_id > pf->vf_num - 1 || !pf->vfs) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid argument.\");\n\t\treturn -EINVAL;\n\t}\n\tvf = &pf->vfs[vf_id];\n\n\tif (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {\n\t\tPMD_DRV_LOG(INFO, \"Ignore adding permanent MAC address.\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (add) {\n\t\t(void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);\n\t\t(void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,\n\t\t\t\tETHER_ADDR_LEN);\n\t\t(void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,\n\t\t\t\t ETHER_ADDR_LEN);\n\n\t\tmac_filter.filter_type = filter->filter_type;\n\t\tret = i40e_vsi_add_mac(vf->vsi, &mac_filter);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to add MAC filter.\");\n\t\t\treturn -1;\n\t\t}\n\t\tether_addr_copy(new_mac, &pf->dev_addr);\n\t} else {\n\t\t(void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,\n\t\t\t\tETHER_ADDR_LEN);\n\t\tret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to delete MAC filter.\");\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Clear device address as it has been removed */\n\t\tif (is_same_ether_addr(&(pf->dev_addr), new_mac))\n\t\t\tmemset(&pf->dev_addr, 0, sizeof(struct ether_addr));\n\t}\n\n\treturn 0;\n}\n\n/* MAC filter handle */\nstatic int\ni40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,\n\t\tvoid *arg)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct rte_eth_mac_filter *filter;\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tint ret = I40E_NOT_SUPPORTED;\n\n\tfilter = (struct rte_eth_mac_filter *)(arg);\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_NOP:\n\t\tret = I40E_SUCCESS;\n\t\tbreak;\n\tcase RTE_ETH_FILTER_ADD:\n\t\ti40e_pf_disable_irq0(hw);\n\t\tif (filter->is_vf)\n\t\t\tret = i40e_vf_mac_filter_set(pf, filter, 1);\n\t\ti40e_pf_enable_irq0(hw);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_DELETE:\n\t\ti40e_pf_disable_irq0(hw);\n\t\tif (filter->is_vf)\n\t\t\tret = i40e_vf_mac_filter_set(pf, filter, 0);\n\t\ti40e_pf_enable_irq0(hw);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unknown operation %u\", filter_op);\n\t\tret = I40E_ERR_PARAM;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int\ni40e_dev_rss_reta_update(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t uint16_t reta_size)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t lut, l;\n\tuint16_t i, j, lut_size = pf->hash_lut_size;\n\tuint16_t idx, shift;\n\tuint8_t mask;\n\n\tif (reta_size != lut_size ||\n\t\treta_size > ETH_RSS_RETA_SIZE_512) {\n\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n\t\t\t\"(%d) doesn't match the number hardware can supported \"\n\t\t\t\t\t\"(%d)\\n\", reta_size, lut_size);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {\n\t\tidx = i / RTE_RETA_GROUP_SIZE;\n\t\tshift = i % RTE_RETA_GROUP_SIZE;\n\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n\t\t\t\t\t\tI40E_4_BIT_MASK);\n\t\tif (!mask)\n\t\t\tcontinue;\n\t\tif (mask == I40E_4_BIT_MASK)\n\t\t\tl = 0;\n\t\telse\n\t\t\tl = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));\n\t\tfor (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {\n\t\t\tif (mask & (0x1 << j))\n\t\t\t\tlut |= reta_conf[idx].reta[shift + j] <<\n\t\t\t\t\t\t\t(CHAR_BIT * j);\n\t\t\telse\n\t\t\t\tlut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));\n\t\t}\n\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40e_dev_rss_reta_query(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\tuint16_t reta_size)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t lut;\n\tuint16_t i, j, lut_size = pf->hash_lut_size;\n\tuint16_t idx, shift;\n\tuint8_t mask;\n\n\tif (reta_size != lut_size ||\n\t\treta_size > ETH_RSS_RETA_SIZE_512) {\n\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n\t\t\t\"(%d) doesn't match the number hardware can supported \"\n\t\t\t\t\t\"(%d)\\n\", reta_size, lut_size);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {\n\t\tidx = i / RTE_RETA_GROUP_SIZE;\n\t\tshift = i % RTE_RETA_GROUP_SIZE;\n\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n\t\t\t\t\t\tI40E_4_BIT_MASK);\n\t\tif (!mask)\n\t\t\tcontinue;\n\n\t\tlut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));\n\t\tfor (j = 0; j < I40E_4_BIT_WIDTH; j++) {\n\t\t\tif (mask & (0x1 << j))\n\t\t\t\treta_conf[idx].reta[shift + j] = ((lut >>\n\t\t\t\t\t(CHAR_BIT * j)) & I40E_8_BIT_MASK);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/**\n * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)\n * @hw: pointer to the HW structure\n * @mem: pointer to mem struct to fill out\n * @size: size of memory requested\n * @alignment: what to align the allocation to\n **/\nenum i40e_status_code\ni40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,\n\t\t\tstruct i40e_dma_mem *mem,\n\t\t\tu64 size,\n\t\t\tu32 alignment)\n{\n\tstatic uint64_t id = 0;\n\tconst struct rte_memzone *mz = NULL;\n\tchar z_name[RTE_MEMZONE_NAMESIZE];\n\n\tif (!mem)\n\t\treturn I40E_ERR_PARAM;\n\n\tid++;\n\tsnprintf(z_name, sizeof(z_name), \"i40e_dma_%\"PRIu64, id);\n#ifdef RTE_LIBRTE_XEN_DOM0\n\tmz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,\n\t\t\t\t\t\t\tRTE_PGSIZE_2M);\n#else\n\tmz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);\n#endif\n\tif (!mz)\n\t\treturn I40E_ERR_NO_MEMORY;\n\n\tmem->id = id;\n\tmem->size = size;\n\tmem->va = mz->addr;\n#ifdef RTE_LIBRTE_XEN_DOM0\n\tmem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);\n#else\n\tmem->pa = mz->phys_addr;\n#endif\n\n\treturn I40E_SUCCESS;\n}\n\n/**\n * i40e_free_dma_mem_d - specific memory free for shared code (base driver)\n * @hw: pointer to the HW structure\n * @mem: ptr to mem struct to free\n **/\nenum i40e_status_code\ni40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,\n\t\t struct i40e_dma_mem *mem)\n{\n\tif (!mem || !mem->va)\n\t\treturn I40E_ERR_PARAM;\n\n\tmem->va = NULL;\n\tmem->pa = (u64)0;\n\n\treturn I40E_SUCCESS;\n}\n\n/**\n * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)\n * @hw: pointer to the HW structure\n * @mem: pointer to mem struct to fill out\n * @size: size of memory requested\n **/\nenum i40e_status_code\ni40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,\n\t\t\t struct i40e_virt_mem *mem,\n\t\t\t u32 size)\n{\n\tif (!mem)\n\t\treturn I40E_ERR_PARAM;\n\n\tmem->size = size;\n\tmem->va = rte_zmalloc(\"i40e\", size, 0);\n\n\tif (mem->va)\n\t\treturn I40E_SUCCESS;\n\telse\n\t\treturn I40E_ERR_NO_MEMORY;\n}\n\n/**\n * i40e_free_virt_mem_d - specific memory free for shared code (base driver)\n * @hw: pointer to the HW structure\n * @mem: pointer to mem struct to free\n **/\nenum i40e_status_code\ni40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,\n\t\t struct i40e_virt_mem *mem)\n{\n\tif (!mem)\n\t\treturn I40E_ERR_PARAM;\n\n\trte_free(mem->va);\n\tmem->va = NULL;\n\n\treturn I40E_SUCCESS;\n}\n\nvoid\ni40e_init_spinlock_d(struct i40e_spinlock *sp)\n{\n\trte_spinlock_init(&sp->spinlock);\n}\n\nvoid\ni40e_acquire_spinlock_d(struct i40e_spinlock *sp)\n{\n\trte_spinlock_lock(&sp->spinlock);\n}\n\nvoid\ni40e_release_spinlock_d(struct i40e_spinlock *sp)\n{\n\trte_spinlock_unlock(&sp->spinlock);\n}\n\nvoid\ni40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)\n{\n\treturn;\n}\n\n/**\n * Get the hardware capabilities, which will be parsed\n * and saved into struct i40e_hw.\n */\nstatic int\ni40e_get_cap(struct i40e_hw *hw)\n{\n\tstruct i40e_aqc_list_capabilities_element_resp *buf;\n\tuint16_t len, size = 0;\n\tint ret;\n\n\t/* Calculate a huge enough buff for saving response data temporarily */\n\tlen = sizeof(struct i40e_aqc_list_capabilities_element_resp) *\n\t\t\t\t\t\tI40E_MAX_CAP_ELE_NUM;\n\tbuf = rte_zmalloc(\"i40e\", len, 0);\n\tif (!buf) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\n\t/* Get, parse the capabilities and save it to hw */\n\tret = i40e_aq_discover_capabilities(hw, buf, len, &size,\n\t\t\ti40e_aqc_opc_list_func_capabilities, NULL);\n\tif (ret != I40E_SUCCESS)\n\t\tPMD_DRV_LOG(ERR, \"Failed to discover capabilities\");\n\n\t/* Free the temporary buffer after being used */\n\trte_free(buf);\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_parameter_init(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tuint16_t sum_queues = 0, sum_vsis, left_queues;\n\n\t/* First check if FW support SRIOV */\n\tif (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {\n\t\tPMD_INIT_LOG(ERR, \"HW configuration doesn't support SRIOV\");\n\t\treturn -EINVAL;\n\t}\n\n\tpf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;\n\tpf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);\n\tPMD_INIT_LOG(INFO, \"Max supported VSIs:%u\", pf->max_num_vsi);\n\t/* Allocate queues for pf */\n\tif (hw->func_caps.rss) {\n\t\tpf->flags |= I40E_FLAG_RSS;\n\t\tpf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,\n\t\t\t(uint32_t)(1 << hw->func_caps.rss_table_entry_width));\n\t\tpf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);\n\t} else\n\t\tpf->lan_nb_qps = 1;\n\tsum_queues = pf->lan_nb_qps;\n\t/* Default VSI is not counted in */\n\tsum_vsis = 0;\n\tPMD_INIT_LOG(INFO, \"PF queue pairs:%u\", pf->lan_nb_qps);\n\n\tif (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {\n\t\tpf->flags |= I40E_FLAG_SRIOV;\n\t\tpf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;\n\t\tif (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {\n\t\t\tPMD_INIT_LOG(ERR, \"Config VF number %u, \"\n\t\t\t\t \"max supported %u.\",\n\t\t\t\t dev->pci_dev->max_vfs,\n\t\t\t\t hw->func_caps.num_vfs);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tif (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {\n\t\t\tPMD_INIT_LOG(ERR, \"FVL VF queue %u, \"\n\t\t\t\t \"max support %u queues.\",\n\t\t\t\t pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tpf->vf_num = dev->pci_dev->max_vfs;\n\t\tsum_queues += pf->vf_nb_qps * pf->vf_num;\n\t\tsum_vsis += pf->vf_num;\n\t\tPMD_INIT_LOG(INFO, \"Max VF num:%u each has queue pairs:%u\",\n\t\t\t pf->vf_num, pf->vf_nb_qps);\n\t} else\n\t\tpf->vf_num = 0;\n\n\tif (hw->func_caps.vmdq) {\n\t\tpf->flags |= I40E_FLAG_VMDQ;\n\t\tpf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;\n\t\tpf->max_nb_vmdq_vsi = 1;\n\t\t/*\n\t\t * If VMDQ available, assume a single VSI can be created. Will adjust\n\t\t * later.\n\t\t */\n\t\tsum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;\n\t\tsum_vsis += pf->max_nb_vmdq_vsi;\n\t} else {\n\t\tpf->vmdq_nb_qps = 0;\n\t\tpf->max_nb_vmdq_vsi = 0;\n\t}\n\tpf->nb_cfg_vmdq_vsi = 0;\n\n\tif (hw->func_caps.fd) {\n\t\tpf->flags |= I40E_FLAG_FDIR;\n\t\tpf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;\n\t\t/**\n\t\t * Each flow director consumes one VSI and one queue,\n\t\t * but can't calculate out predictably here.\n\t\t */\n\t}\n\n\tif (sum_vsis > pf->max_num_vsi ||\n\t\tsum_queues > hw->func_caps.num_rx_qp) {\n\t\tPMD_INIT_LOG(ERR, \"VSI/QUEUE setting can't be satisfied\");\n\t\tPMD_INIT_LOG(ERR, \"Max VSIs: %u, asked:%u\",\n\t\t\t pf->max_num_vsi, sum_vsis);\n\t\tPMD_INIT_LOG(ERR, \"Total queue pairs:%u, asked:%u\",\n\t\t\t hw->func_caps.num_rx_qp, sum_queues);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Adjust VMDQ setting to support as many VMs as possible */\n\tif (pf->flags & I40E_FLAG_VMDQ) {\n\t\tleft_queues = hw->func_caps.num_rx_qp - sum_queues;\n\n\t\tpf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,\n\t\t\t\t\tpf->max_num_vsi - sum_vsis);\n\n\t\t/* Limit the max VMDQ number that rte_ether that can support */\n\t\tpf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,\n\t\t\t\t\tETH_64_POOLS - 1);\n\n\t\tPMD_INIT_LOG(INFO, \"Max VMDQ VSI num:%u\",\n\t\t\t\tpf->max_nb_vmdq_vsi);\n\t\tPMD_INIT_LOG(INFO, \"VMDQ queue pairs:%u\", pf->vmdq_nb_qps);\n\t}\n\n\t/* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr\n\t * cause */\n\tif (sum_vsis > hw->func_caps.num_msix_vectors - 1) {\n\t\tPMD_INIT_LOG(ERR, \"Too many VSIs(%u), MSIX intr(%u) not enough\",\n\t\t\t sum_vsis, hw->func_caps.num_msix_vectors);\n\t\treturn -EINVAL;\n\t}\n\treturn I40E_SUCCESS;\n}\n\nstatic int\ni40e_pf_get_switch_config(struct i40e_pf *pf)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tstruct i40e_aqc_get_switch_config_resp *switch_config;\n\tstruct i40e_aqc_switch_config_element_resp *element;\n\tuint16_t start_seid = 0, num_reported;\n\tint ret;\n\n\tswitch_config = (struct i40e_aqc_get_switch_config_resp *)\\\n\t\t\trte_zmalloc(\"i40e\", I40E_AQ_LARGE_BUF, 0);\n\tif (!switch_config) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to allocated memory\");\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Get the switch configurations */\n\tret = i40e_aq_get_switch_config(hw, switch_config,\n\t\tI40E_AQ_LARGE_BUF, &start_seid, NULL);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to get switch configurations\");\n\t\tgoto fail;\n\t}\n\tnum_reported = rte_le_to_cpu_16(switch_config->header.num_reported);\n\tif (num_reported != 1) { /* The number should be 1 */\n\t\tPMD_DRV_LOG(ERR, \"Wrong number of switch config reported\");\n\t\tgoto fail;\n\t}\n\n\t/* Parse the switch configuration elements */\n\telement = &(switch_config->element[0]);\n\tif (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {\n\t\tpf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);\n\t\tpf->main_vsi_seid = rte_le_to_cpu_16(element->seid);\n\t} else\n\t\tPMD_DRV_LOG(INFO, \"Unknown element type\");\n\nfail:\n\trte_free(switch_config);\n\n\treturn ret;\n}\n\nstatic int\ni40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,\n\t\t\tuint32_t num)\n{\n\tstruct pool_entry *entry;\n\n\tif (pool == NULL || num == 0)\n\t\treturn -EINVAL;\n\n\tentry = rte_zmalloc(\"i40e\", sizeof(*entry), 0);\n\tif (entry == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for resource pool\");\n\t\treturn -ENOMEM;\n\t}\n\n\t/* queue heap initialize */\n\tpool->num_free = num;\n\tpool->num_alloc = 0;\n\tpool->base = base;\n\tLIST_INIT(&pool->alloc_list);\n\tLIST_INIT(&pool->free_list);\n\n\t/* Initialize element */\n\tentry->base = 0;\n\tentry->len = num;\n\n\tLIST_INSERT_HEAD(&pool->free_list, entry, next);\n\treturn 0;\n}\n\nstatic void\ni40e_res_pool_destroy(struct i40e_res_pool_info *pool)\n{\n\tstruct pool_entry *entry;\n\n\tif (pool == NULL)\n\t\treturn;\n\n\tLIST_FOREACH(entry, &pool->alloc_list, next) {\n\t\tLIST_REMOVE(entry, next);\n\t\trte_free(entry);\n\t}\n\n\tLIST_FOREACH(entry, &pool->free_list, next) {\n\t\tLIST_REMOVE(entry, next);\n\t\trte_free(entry);\n\t}\n\n\tpool->num_free = 0;\n\tpool->num_alloc = 0;\n\tpool->base = 0;\n\tLIST_INIT(&pool->alloc_list);\n\tLIST_INIT(&pool->free_list);\n}\n\nstatic int\ni40e_res_pool_free(struct i40e_res_pool_info *pool,\n\t\t uint32_t base)\n{\n\tstruct pool_entry *entry, *next, *prev, *valid_entry = NULL;\n\tuint32_t pool_offset;\n\tint insert;\n\n\tif (pool == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid parameter\");\n\t\treturn -EINVAL;\n\t}\n\n\tpool_offset = base - pool->base;\n\t/* Lookup in alloc list */\n\tLIST_FOREACH(entry, &pool->alloc_list, next) {\n\t\tif (entry->base == pool_offset) {\n\t\t\tvalid_entry = entry;\n\t\t\tLIST_REMOVE(entry, next);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Not find, return */\n\tif (valid_entry == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to find entry\");\n\t\treturn -EINVAL;\n\t}\n\n\t/**\n\t * Found it, move it to free list and try to merge.\n\t * In order to make merge easier, always sort it by qbase.\n\t * Find adjacent prev and last entries.\n\t */\n\tprev = next = NULL;\n\tLIST_FOREACH(entry, &pool->free_list, next) {\n\t\tif (entry->base > valid_entry->base) {\n\t\t\tnext = entry;\n\t\t\tbreak;\n\t\t}\n\t\tprev = entry;\n\t}\n\n\tinsert = 0;\n\t/* Try to merge with next one*/\n\tif (next != NULL) {\n\t\t/* Merge with next one */\n\t\tif (valid_entry->base + valid_entry->len == next->base) {\n\t\t\tnext->base = valid_entry->base;\n\t\t\tnext->len += valid_entry->len;\n\t\t\trte_free(valid_entry);\n\t\t\tvalid_entry = next;\n\t\t\tinsert = 1;\n\t\t}\n\t}\n\n\tif (prev != NULL) {\n\t\t/* Merge with previous one */\n\t\tif (prev->base + prev->len == valid_entry->base) {\n\t\t\tprev->len += valid_entry->len;\n\t\t\t/* If it merge with next one, remove next node */\n\t\t\tif (insert == 1) {\n\t\t\t\tLIST_REMOVE(valid_entry, next);\n\t\t\t\trte_free(valid_entry);\n\t\t\t} else {\n\t\t\t\trte_free(valid_entry);\n\t\t\t\tinsert = 1;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Not find any entry to merge, insert */\n\tif (insert == 0) {\n\t\tif (prev != NULL)\n\t\t\tLIST_INSERT_AFTER(prev, valid_entry, next);\n\t\telse if (next != NULL)\n\t\t\tLIST_INSERT_BEFORE(next, valid_entry, next);\n\t\telse /* It's empty list, insert to head */\n\t\t\tLIST_INSERT_HEAD(&pool->free_list, valid_entry, next);\n\t}\n\n\tpool->num_free += valid_entry->len;\n\tpool->num_alloc -= valid_entry->len;\n\n\treturn 0;\n}\n\nstatic int\ni40e_res_pool_alloc(struct i40e_res_pool_info *pool,\n\t\t uint16_t num)\n{\n\tstruct pool_entry *entry, *valid_entry;\n\n\tif (pool == NULL || num == 0) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid parameter\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (pool->num_free < num) {\n\t\tPMD_DRV_LOG(ERR, \"No resource. ask:%u, available:%u\",\n\t\t\t num, pool->num_free);\n\t\treturn -ENOMEM;\n\t}\n\n\tvalid_entry = NULL;\n\t/* Lookup in free list and find most fit one */\n\tLIST_FOREACH(entry, &pool->free_list, next) {\n\t\tif (entry->len >= num) {\n\t\t\t/* Find best one */\n\t\t\tif (entry->len == num) {\n\t\t\t\tvalid_entry = entry;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (valid_entry == NULL || valid_entry->len > entry->len)\n\t\t\t\tvalid_entry = entry;\n\t\t}\n\t}\n\n\t/* Not find one to satisfy the request, return */\n\tif (valid_entry == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"No valid entry found\");\n\t\treturn -ENOMEM;\n\t}\n\t/**\n\t * The entry have equal queue number as requested,\n\t * remove it from alloc_list.\n\t */\n\tif (valid_entry->len == num) {\n\t\tLIST_REMOVE(valid_entry, next);\n\t} else {\n\t\t/**\n\t\t * The entry have more numbers than requested,\n\t\t * create a new entry for alloc_list and minus its\n\t\t * queue base and number in free_list.\n\t\t */\n\t\tentry = rte_zmalloc(\"res_pool\", sizeof(*entry), 0);\n\t\tif (entry == NULL) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for \"\n\t\t\t\t \"resource pool\");\n\t\t\treturn -ENOMEM;\n\t\t}\n\t\tentry->base = valid_entry->base;\n\t\tentry->len = num;\n\t\tvalid_entry->base += num;\n\t\tvalid_entry->len -= num;\n\t\tvalid_entry = entry;\n\t}\n\n\t/* Insert it into alloc list, not sorted */\n\tLIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);\n\n\tpool->num_free -= valid_entry->len;\n\tpool->num_alloc += valid_entry->len;\n\n\treturn (valid_entry->base + pool->base);\n}\n\n/**\n * bitmap_is_subset - Check whether src2 is subset of src1\n **/\nstatic inline int\nbitmap_is_subset(uint8_t src1, uint8_t src2)\n{\n\treturn !((src1 ^ src2) & src2);\n}\n\nstatic int\nvalidate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)\n{\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\n\t/* If DCB is not supported, only default TC is supported */\n\tif (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {\n\t\tPMD_DRV_LOG(ERR, \"DCB is not enabled, only TC0 is supported\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {\n\t\tPMD_DRV_LOG(ERR, \"Enabled TC map 0x%x not applicable to \"\n\t\t\t \"HW support 0x%x\", hw->func_caps.enabled_tcmap,\n\t\t\t enabled_tcmap);\n\t\treturn -EINVAL;\n\t}\n\treturn I40E_SUCCESS;\n}\n\nint\ni40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,\n\t\t\t\tstruct i40e_vsi_vlan_pvid_info *info)\n{\n\tstruct i40e_hw *hw;\n\tstruct i40e_vsi_context ctxt;\n\tuint8_t vlan_flags = 0;\n\tint ret;\n\n\tif (vsi == NULL || info == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"invalid parameters\");\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\tif (info->on) {\n\t\tvsi->info.pvid = info->config.pvid;\n\t\t/**\n\t\t * If insert pvid is enabled, only tagged pkts are\n\t\t * allowed to be sent out.\n\t\t */\n\t\tvlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |\n\t\t\t\tI40E_AQ_VSI_PVLAN_MODE_TAGGED;\n\t} else {\n\t\tvsi->info.pvid = 0;\n\t\tif (info->config.reject.tagged == 0)\n\t\t\tvlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;\n\n\t\tif (info->config.reject.untagged == 0)\n\t\t\tvlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;\n\t}\n\tvsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |\n\t\t\t\t\tI40E_AQ_VSI_PVLAN_MODE_MASK);\n\tvsi->info.port_vlan_flags |= vlan_flags;\n\tvsi->info.valid_sections =\n\t\trte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);\n\tmemset(&ctxt, 0, sizeof(ctxt));\n\t(void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));\n\tctxt.seid = vsi->seid;\n\n\thw = I40E_VSI_TO_HW(vsi);\n\tret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);\n\tif (ret != I40E_SUCCESS)\n\t\tPMD_DRV_LOG(ERR, \"Failed to update VSI params\");\n\n\treturn ret;\n}\n\nstatic int\ni40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)\n{\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\tint i, ret;\n\tstruct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;\n\n\tret = validate_tcmap_parameter(vsi, enabled_tcmap);\n\tif (ret != I40E_SUCCESS)\n\t\treturn ret;\n\n\tif (!vsi->seid) {\n\t\tPMD_DRV_LOG(ERR, \"seid not valid\");\n\t\treturn -EINVAL;\n\t}\n\n\tmemset(&tc_bw_data, 0, sizeof(tc_bw_data));\n\ttc_bw_data.tc_valid_bits = enabled_tcmap;\n\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)\n\t\ttc_bw_data.tc_bw_credits[i] =\n\t\t\t(enabled_tcmap & (1 << i)) ? 1 : 0;\n\n\tret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to configure TC BW\");\n\t\treturn ret;\n\t}\n\n\t(void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,\n\t\t\t\t\tsizeof(vsi->info.qs_handle));\n\treturn I40E_SUCCESS;\n}\n\nstatic int\ni40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,\n\t\t\t\t struct i40e_aqc_vsi_properties_data *info,\n\t\t\t\t uint8_t enabled_tcmap)\n{\n\tint ret, total_tc = 0, i;\n\tuint16_t qpnum_per_tc, bsf, qp_idx;\n\n\tret = validate_tcmap_parameter(vsi, enabled_tcmap);\n\tif (ret != I40E_SUCCESS)\n\t\treturn ret;\n\n\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)\n\t\tif (enabled_tcmap & (1 << i))\n\t\t\ttotal_tc++;\n\tvsi->enabled_tc = enabled_tcmap;\n\n\t/* Number of queues per enabled TC */\n\tqpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);\n\tqpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);\n\tbsf = rte_bsf32(qpnum_per_tc);\n\n\t/* Adjust the queue number to actual queues that can be applied */\n\tvsi->nb_qps = qpnum_per_tc * total_tc;\n\n\t/**\n\t * Configure TC and queue mapping parameters, for enabled TC,\n\t * allocate qpnum_per_tc queues to this traffic. For disabled TC,\n\t * default queue will serve it.\n\t */\n\tqp_idx = 0;\n\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n\t\tif (vsi->enabled_tc & (1 << i)) {\n\t\t\tinfo->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<\n\t\t\t\t\tI40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |\n\t\t\t\t(bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));\n\t\t\tqp_idx += qpnum_per_tc;\n\t\t} else\n\t\t\tinfo->tc_mapping[i] = 0;\n\t}\n\n\t/* Associate queue number with VSI */\n\tif (vsi->type == I40E_VSI_SRIOV) {\n\t\tinfo->mapping_flags |=\n\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);\n\t\tfor (i = 0; i < vsi->nb_qps; i++)\n\t\t\tinfo->queue_mapping[i] =\n\t\t\t\trte_cpu_to_le_16(vsi->base_queue + i);\n\t} else {\n\t\tinfo->mapping_flags |=\n\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);\n\t\tinfo->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);\n\t}\n\tinfo->valid_sections |=\n\t\trte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);\n\n\treturn I40E_SUCCESS;\n}\n\nstatic int\ni40e_veb_release(struct i40e_veb *veb)\n{\n\tstruct i40e_vsi *vsi;\n\tstruct i40e_hw *hw;\n\n\tif (veb == NULL || veb->associate_vsi == NULL)\n\t\treturn -EINVAL;\n\n\tif (!TAILQ_EMPTY(&veb->head)) {\n\t\tPMD_DRV_LOG(ERR, \"VEB still has VSI attached, can't remove\");\n\t\treturn -EACCES;\n\t}\n\n\tvsi = veb->associate_vsi;\n\thw = I40E_VSI_TO_HW(vsi);\n\n\tvsi->uplink_seid = veb->uplink_seid;\n\ti40e_aq_delete_element(hw, veb->seid, NULL);\n\trte_free(veb);\n\tvsi->veb = NULL;\n\treturn I40E_SUCCESS;\n}\n\n/* Setup a veb */\nstatic struct i40e_veb *\ni40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)\n{\n\tstruct i40e_veb *veb;\n\tint ret;\n\tstruct i40e_hw *hw;\n\n\tif (NULL == pf || vsi == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"veb setup failed, \"\n\t\t\t \"associated VSI shouldn't null\");\n\t\treturn NULL;\n\t}\n\thw = I40E_PF_TO_HW(pf);\n\n\tveb = rte_zmalloc(\"i40e_veb\", sizeof(struct i40e_veb), 0);\n\tif (!veb) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for veb\");\n\t\tgoto fail;\n\t}\n\n\tveb->associate_vsi = vsi;\n\tTAILQ_INIT(&veb->head);\n\tveb->uplink_seid = vsi->uplink_seid;\n\n\tret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,\n\t\tI40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);\n\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Add veb failed, aq_err: %d\",\n\t\t\t hw->aq.asq_last_status);\n\t\tgoto fail;\n\t}\n\n\t/* get statistics index */\n\tret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,\n\t\t\t\t&veb->stats_idx, NULL, NULL, NULL);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Get veb statics index failed, aq_err: %d\",\n\t\t\t hw->aq.asq_last_status);\n\t\tgoto fail;\n\t}\n\n\t/* Get VEB bandwidth, to be implemented */\n\t/* Now associated vsi binding to the VEB, set uplink to this VEB */\n\tvsi->uplink_seid = veb->seid;\n\n\treturn veb;\nfail:\n\trte_free(veb);\n\treturn NULL;\n}\n\nint\ni40e_vsi_release(struct i40e_vsi *vsi)\n{\n\tstruct i40e_pf *pf;\n\tstruct i40e_hw *hw;\n\tstruct i40e_vsi_list *vsi_list;\n\tint ret;\n\tstruct i40e_mac_filter *f;\n\n\tif (!vsi)\n\t\treturn I40E_SUCCESS;\n\n\tpf = I40E_VSI_TO_PF(vsi);\n\thw = I40E_VSI_TO_HW(vsi);\n\n\t/* VSI has child to attach, release child first */\n\tif (vsi->veb) {\n\t\tTAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {\n\t\t\tif (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)\n\t\t\t\treturn -1;\n\t\t\tTAILQ_REMOVE(&vsi->veb->head, vsi_list, list);\n\t\t}\n\t\ti40e_veb_release(vsi->veb);\n\t}\n\n\t/* Remove all macvlan filters of the VSI */\n\ti40e_vsi_remove_all_macvlan_filter(vsi);\n\tTAILQ_FOREACH(f, &vsi->mac_list, next)\n\t\trte_free(f);\n\n\tif (vsi->type != I40E_VSI_MAIN) {\n\t\t/* Remove vsi from parent's sibling list */\n\t\tif (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {\n\t\t\tPMD_DRV_LOG(ERR, \"VSI's parent VSI is NULL\");\n\t\t\treturn I40E_ERR_PARAM;\n\t\t}\n\t\tTAILQ_REMOVE(&vsi->parent_vsi->veb->head,\n\t\t\t\t&vsi->sib_vsi_list, list);\n\n\t\t/* Remove all switch element of the VSI */\n\t\tret = i40e_aq_delete_element(hw, vsi->seid, NULL);\n\t\tif (ret != I40E_SUCCESS)\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to delete element\");\n\t}\n\ti40e_res_pool_free(&pf->qp_pool, vsi->base_queue);\n\n\tif (vsi->type != I40E_VSI_SRIOV)\n\t\ti40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);\n\trte_free(vsi);\n\n\treturn I40E_SUCCESS;\n}\n\nstatic int\ni40e_update_default_filter_setting(struct i40e_vsi *vsi)\n{\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\tstruct i40e_aqc_remove_macvlan_element_data def_filter;\n\tstruct i40e_mac_filter_info filter;\n\tint ret;\n\n\tif (vsi->type != I40E_VSI_MAIN)\n\t\treturn I40E_ERR_CONFIG;\n\tmemset(&def_filter, 0, sizeof(def_filter));\n\t(void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,\n\t\t\t\t\tETH_ADDR_LEN);\n\tdef_filter.vlan_tag = 0;\n\tdef_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |\n\t\t\t\tI40E_AQC_MACVLAN_DEL_IGNORE_VLAN;\n\tret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);\n\tif (ret != I40E_SUCCESS) {\n\t\tstruct i40e_mac_filter *f;\n\t\tstruct ether_addr *mac;\n\n\t\tPMD_DRV_LOG(WARNING, \"Cannot remove the default \"\n\t\t\t \"macvlan filter\");\n\t\t/* It needs to add the permanent mac into mac list */\n\t\tf = rte_zmalloc(\"macv_filter\", sizeof(*f), 0);\n\t\tif (f == NULL) {\n\t\t\tPMD_DRV_LOG(ERR, \"failed to allocate memory\");\n\t\t\treturn I40E_ERR_NO_MEMORY;\n\t\t}\n\t\tmac = &f->mac_info.mac_addr;\n\t\t(void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,\n\t\t\t\tETH_ADDR_LEN);\n\t\tf->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;\n\t\tTAILQ_INSERT_TAIL(&vsi->mac_list, f, next);\n\t\tvsi->mac_num++;\n\n\t\treturn ret;\n\t}\n\t(void)rte_memcpy(&filter.mac_addr,\n\t\t(struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);\n\tfilter.filter_type = RTE_MACVLAN_PERFECT_MATCH;\n\treturn i40e_vsi_add_mac(vsi, &filter);\n}\n\nstatic int\ni40e_vsi_dump_bw_config(struct i40e_vsi *vsi)\n{\n\tstruct i40e_aqc_query_vsi_bw_config_resp bw_config;\n\tstruct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;\n\tstruct i40e_hw *hw = &vsi->adapter->hw;\n\ti40e_status ret;\n\tint i;\n\n\tmemset(&bw_config, 0, sizeof(bw_config));\n\tret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"VSI failed to get bandwidth configuration %u\",\n\t\t\t hw->aq.asq_last_status);\n\t\treturn ret;\n\t}\n\n\tmemset(&ets_sla_config, 0, sizeof(ets_sla_config));\n\tret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,\n\t\t\t\t\t&ets_sla_config, NULL);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"VSI failed to get TC bandwdith \"\n\t\t\t \"configuration %u\", hw->aq.asq_last_status);\n\t\treturn ret;\n\t}\n\n\t/* Not store the info yet, just print out */\n\tPMD_DRV_LOG(INFO, \"VSI bw limit:%u\", bw_config.port_bw_limit);\n\tPMD_DRV_LOG(INFO, \"VSI max_bw:%u\", bw_config.max_bw);\n\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n\t\tPMD_DRV_LOG(INFO, \"\\tVSI TC%u:share credits %u\", i,\n\t\t\t ets_sla_config.share_credits[i]);\n\t\tPMD_DRV_LOG(INFO, \"\\tVSI TC%u:credits %u\", i,\n\t\t\t rte_le_to_cpu_16(ets_sla_config.credits[i]));\n\t\tPMD_DRV_LOG(INFO, \"\\tVSI TC%u: max credits: %u\", i,\n\t\t\t rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>\n\t\t\t (i * 4));\n\t}\n\n\treturn 0;\n}\n\n/* Setup a VSI */\nstruct i40e_vsi *\ni40e_vsi_setup(struct i40e_pf *pf,\n\t enum i40e_vsi_type type,\n\t struct i40e_vsi *uplink_vsi,\n\t uint16_t user_param)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tstruct i40e_vsi *vsi;\n\tstruct i40e_mac_filter_info filter;\n\tint ret;\n\tstruct i40e_vsi_context ctxt;\n\tstruct ether_addr broadcast =\n\t\t{.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};\n\n\tif (type != I40E_VSI_MAIN && uplink_vsi == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"VSI setup failed, \"\n\t\t\t \"VSI link shouldn't be NULL\");\n\t\treturn NULL;\n\t}\n\n\tif (type == I40E_VSI_MAIN && uplink_vsi != NULL) {\n\t\tPMD_DRV_LOG(ERR, \"VSI setup failed, MAIN VSI \"\n\t\t\t \"uplink VSI should be NULL\");\n\t\treturn NULL;\n\t}\n\n\t/* If uplink vsi didn't setup VEB, create one first */\n\tif (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {\n\t\tuplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);\n\n\t\tif (NULL == uplink_vsi->veb) {\n\t\t\tPMD_DRV_LOG(ERR, \"VEB setup failed\");\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\tvsi = rte_zmalloc(\"i40e_vsi\", sizeof(struct i40e_vsi), 0);\n\tif (!vsi) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for vsi\");\n\t\treturn NULL;\n\t}\n\tTAILQ_INIT(&vsi->mac_list);\n\tvsi->type = type;\n\tvsi->adapter = I40E_PF_TO_ADAPTER(pf);\n\tvsi->max_macaddrs = I40E_NUM_MACADDR_MAX;\n\tvsi->parent_vsi = uplink_vsi;\n\tvsi->user_param = user_param;\n\t/* Allocate queues */\n\tswitch (vsi->type) {\n\tcase I40E_VSI_MAIN :\n\t\tvsi->nb_qps = pf->lan_nb_qps;\n\t\tbreak;\n\tcase I40E_VSI_SRIOV :\n\t\tvsi->nb_qps = pf->vf_nb_qps;\n\t\tbreak;\n\tcase I40E_VSI_VMDQ2:\n\t\tvsi->nb_qps = pf->vmdq_nb_qps;\n\t\tbreak;\n\tcase I40E_VSI_FDIR:\n\t\tvsi->nb_qps = pf->fdir_nb_qps;\n\t\tbreak;\n\tdefault:\n\t\tgoto fail_mem;\n\t}\n\t/*\n\t * The filter status descriptor is reported in rx queue 0,\n\t * while the tx queue for fdir filter programming has no\n\t * such constraints, can be non-zero queues.\n\t * To simplify it, choose FDIR vsi use queue 0 pair.\n\t * To make sure it will use queue 0 pair, queue allocation\n\t * need be done before this function is called\n\t */\n\tif (type != I40E_VSI_FDIR) {\n\t\tret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);\n\t\t\tif (ret < 0) {\n\t\t\t\tPMD_DRV_LOG(ERR, \"VSI %d allocate queue failed %d\",\n\t\t\t\t\t\tvsi->seid, ret);\n\t\t\t\tgoto fail_mem;\n\t\t\t}\n\t\t\tvsi->base_queue = ret;\n\t} else\n\t\tvsi->base_queue = I40E_FDIR_QUEUE_ID;\n\n\t/* VF has MSIX interrupt in VF range, don't allocate here */\n\tif (type != I40E_VSI_SRIOV) {\n\t\tret = i40e_res_pool_alloc(&pf->msix_pool, 1);\n\t\tif (ret < 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"VSI %d get heap failed %d\", vsi->seid, ret);\n\t\t\tgoto fail_queue_alloc;\n\t\t}\n\t\tvsi->msix_intr = ret;\n\t} else\n\t\tvsi->msix_intr = 0;\n\t/* Add VSI */\n\tif (type == I40E_VSI_MAIN) {\n\t\t/* For main VSI, no need to add since it's default one */\n\t\tvsi->uplink_seid = pf->mac_seid;\n\t\tvsi->seid = pf->main_vsi_seid;\n\t\t/* Bind queues with specific MSIX interrupt */\n\t\t/**\n\t\t * Needs 2 interrupt at least, one for misc cause which will\n\t\t * enabled from OS side, Another for queues binding the\n\t\t * interrupt from device side only.\n\t\t */\n\n\t\t/* Get default VSI parameters from hardware */\n\t\tmemset(&ctxt, 0, sizeof(ctxt));\n\t\tctxt.seid = vsi->seid;\n\t\tctxt.pf_num = hw->pf_id;\n\t\tctxt.uplink_seid = vsi->uplink_seid;\n\t\tctxt.vf_num = 0;\n\t\tret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to get VSI params\");\n\t\t\tgoto fail_msix_alloc;\n\t\t}\n\t\t(void)rte_memcpy(&vsi->info, &ctxt.info,\n\t\t\tsizeof(struct i40e_aqc_vsi_properties_data));\n\t\tvsi->vsi_id = ctxt.vsi_number;\n\t\tvsi->info.valid_sections = 0;\n\n\t\t/* Configure tc, enabled TC0 only */\n\t\tif (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=\n\t\t\tI40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to update TC bandwidth\");\n\t\t\tgoto fail_msix_alloc;\n\t\t}\n\n\t\t/* TC, queue mapping */\n\t\tmemset(&ctxt, 0, sizeof(ctxt));\n\t\tvsi->info.valid_sections |=\n\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);\n\t\tvsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |\n\t\t\t\t\tI40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;\n\t\t(void)rte_memcpy(&ctxt.info, &vsi->info,\n\t\t\tsizeof(struct i40e_aqc_vsi_properties_data));\n\t\tret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,\n\t\t\t\t\t\tI40E_DEFAULT_TCMAP);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to configure \"\n\t\t\t\t \"TC queue mapping\");\n\t\t\tgoto fail_msix_alloc;\n\t\t}\n\t\tctxt.seid = vsi->seid;\n\t\tctxt.pf_num = hw->pf_id;\n\t\tctxt.uplink_seid = vsi->uplink_seid;\n\t\tctxt.vf_num = 0;\n\n\t\t/* Update VSI parameters */\n\t\tret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to update VSI params\");\n\t\t\tgoto fail_msix_alloc;\n\t\t}\n\n\t\t(void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,\n\t\t\t\t\t\tsizeof(vsi->info.tc_mapping));\n\t\t(void)rte_memcpy(&vsi->info.queue_mapping,\n\t\t\t\t&ctxt.info.queue_mapping,\n\t\t\tsizeof(vsi->info.queue_mapping));\n\t\tvsi->info.mapping_flags = ctxt.info.mapping_flags;\n\t\tvsi->info.valid_sections = 0;\n\n\t\t(void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,\n\t\t\t\tETH_ADDR_LEN);\n\n\t\t/**\n\t\t * Updating default filter settings are necessary to prevent\n\t\t * reception of tagged packets.\n\t\t * Some old firmware configurations load a default macvlan\n\t\t * filter which accepts both tagged and untagged packets.\n\t\t * The updating is to use a normal filter instead if needed.\n\t\t * For NVM 4.2.2 or after, the updating is not needed anymore.\n\t\t * The firmware with correct configurations load the default\n\t\t * macvlan filter which is expected and cannot be removed.\n\t\t */\n\t\ti40e_update_default_filter_setting(vsi);\n\t\ti40e_config_qinq(hw, vsi);\n\t} else if (type == I40E_VSI_SRIOV) {\n\t\tmemset(&ctxt, 0, sizeof(ctxt));\n\t\t/**\n\t\t * For other VSI, the uplink_seid equals to uplink VSI's\n\t\t * uplink_seid since they share same VEB\n\t\t */\n\t\tvsi->uplink_seid = uplink_vsi->uplink_seid;\n\t\tctxt.pf_num = hw->pf_id;\n\t\tctxt.vf_num = hw->func_caps.vf_base_id + user_param;\n\t\tctxt.uplink_seid = vsi->uplink_seid;\n\t\tctxt.connection_type = 0x1;\n\t\tctxt.flags = I40E_AQ_VSI_TYPE_VF;\n\n\t\t/**\n\t\t * Do not configure switch ID to enable VEB switch by\n\t\t * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,\n\t\t * if the source mac address of packet sent from VF is not\n\t\t * listed in the VEB's mac table, the VEB will switch the\n\t\t * packet back to the VF. Need to enable it when HW issue\n\t\t * is fixed.\n\t\t */\n\n\t\t/* Configure port/vlan */\n\t\tctxt.info.valid_sections |=\n\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);\n\t\tctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;\n\t\tret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,\n\t\t\t\t\t\tI40E_DEFAULT_TCMAP);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to configure \"\n\t\t\t\t \"TC queue mapping\");\n\t\t\tgoto fail_msix_alloc;\n\t\t}\n\t\tctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;\n\t\tctxt.info.valid_sections |=\n\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);\n\t\t/**\n\t\t * Since VSI is not created yet, only configure parameter,\n\t\t * will add vsi below.\n\t\t */\n\n\t\ti40e_config_qinq(hw, vsi);\n\t} else if (type == I40E_VSI_VMDQ2) {\n\t\tmemset(&ctxt, 0, sizeof(ctxt));\n\t\t/*\n\t\t * For other VSI, the uplink_seid equals to uplink VSI's\n\t\t * uplink_seid since they share same VEB\n\t\t */\n\t\tvsi->uplink_seid = uplink_vsi->uplink_seid;\n\t\tctxt.pf_num = hw->pf_id;\n\t\tctxt.vf_num = 0;\n\t\tctxt.uplink_seid = vsi->uplink_seid;\n\t\tctxt.connection_type = 0x1;\n\t\tctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;\n\n\t\tctxt.info.valid_sections |=\n\t\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);\n\t\t/* user_param carries flag to enable loop back */\n\t\tif (user_param) {\n\t\t\tctxt.info.switch_id =\n\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);\n\t\t\tctxt.info.switch_id |=\n\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);\n\t\t}\n\n\t\t/* Configure port/vlan */\n\t\tctxt.info.valid_sections |=\n\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);\n\t\tctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;\n\t\tret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,\n\t\t\t\t\t\tI40E_DEFAULT_TCMAP);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to configure \"\n\t\t\t\t\t\"TC queue mapping\");\n\t\t\tgoto fail_msix_alloc;\n\t\t}\n\t\tctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;\n\t\tctxt.info.valid_sections |=\n\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);\n\t} else if (type == I40E_VSI_FDIR) {\n\t\tmemset(&ctxt, 0, sizeof(ctxt));\n\t\tvsi->uplink_seid = uplink_vsi->uplink_seid;\n\t\tctxt.pf_num = hw->pf_id;\n\t\tctxt.vf_num = 0;\n\t\tctxt.uplink_seid = vsi->uplink_seid;\n\t\tctxt.connection_type = 0x1; /* regular data port */\n\t\tctxt.flags = I40E_AQ_VSI_TYPE_PF;\n\t\tret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,\n\t\t\t\t\t\tI40E_DEFAULT_TCMAP);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to configure \"\n\t\t\t\t\t\"TC queue mapping.\");\n\t\t\tgoto fail_msix_alloc;\n\t\t}\n\t\tctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;\n\t\tctxt.info.valid_sections |=\n\t\t\trte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);\n\t} else {\n\t\tPMD_DRV_LOG(ERR, \"VSI: Not support other type VSI yet\");\n\t\tgoto fail_msix_alloc;\n\t}\n\n\tif (vsi->type != I40E_VSI_MAIN) {\n\t\tret = i40e_aq_add_vsi(hw, &ctxt, NULL);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"add vsi failed, aq_err=%d\",\n\t\t\t\t hw->aq.asq_last_status);\n\t\t\tgoto fail_msix_alloc;\n\t\t}\n\t\tmemcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));\n\t\tvsi->info.valid_sections = 0;\n\t\tvsi->seid = ctxt.seid;\n\t\tvsi->vsi_id = ctxt.vsi_number;\n\t\tvsi->sib_vsi_list.vsi = vsi;\n\t\tTAILQ_INSERT_TAIL(&uplink_vsi->veb->head,\n\t\t\t\t&vsi->sib_vsi_list, list);\n\t}\n\n\t/* MAC/VLAN configuration */\n\t(void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);\n\tfilter.filter_type = RTE_MACVLAN_PERFECT_MATCH;\n\n\tret = i40e_vsi_add_mac(vsi, &filter);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to add MACVLAN filter\");\n\t\tgoto fail_msix_alloc;\n\t}\n\n\t/* Get VSI BW information */\n\ti40e_vsi_dump_bw_config(vsi);\n\treturn vsi;\nfail_msix_alloc:\n\ti40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);\nfail_queue_alloc:\n\ti40e_res_pool_free(&pf->qp_pool,vsi->base_queue);\nfail_mem:\n\trte_free(vsi);\n\treturn NULL;\n}\n\n/* Configure vlan stripping on or off */\nint\ni40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)\n{\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\tstruct i40e_vsi_context ctxt;\n\tuint8_t vlan_flags;\n\tint ret = I40E_SUCCESS;\n\n\t/* Check if it has been already on or off */\n\tif (vsi->info.valid_sections &\n\t\trte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {\n\t\tif (on) {\n\t\t\tif ((vsi->info.port_vlan_flags &\n\t\t\t\tI40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)\n\t\t\t\treturn 0; /* already on */\n\t\t} else {\n\t\t\tif ((vsi->info.port_vlan_flags &\n\t\t\t\tI40E_AQ_VSI_PVLAN_EMOD_MASK) ==\n\t\t\t\tI40E_AQ_VSI_PVLAN_EMOD_MASK)\n\t\t\t\treturn 0; /* already off */\n\t\t}\n\t}\n\n\tif (on)\n\t\tvlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;\n\telse\n\t\tvlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;\n\tvsi->info.valid_sections =\n\t\trte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);\n\tvsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);\n\tvsi->info.port_vlan_flags |= vlan_flags;\n\tctxt.seid = vsi->seid;\n\t(void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));\n\tret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);\n\tif (ret)\n\t\tPMD_DRV_LOG(INFO, \"Update VSI failed to %s vlan stripping\",\n\t\t\t on ? \"enable\" : \"disable\");\n\n\treturn ret;\n}\n\nstatic int\ni40e_dev_init_vlan(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_dev_data *data = dev->data;\n\tint ret;\n\n\t/* Apply vlan offload setting */\n\ti40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);\n\n\t/* Apply double-vlan setting, not implemented yet */\n\n\t/* Apply pvid setting */\n\tret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,\n\t\t\t\tdata->dev_conf.txmode.hw_vlan_insert_pvid);\n\tif (ret)\n\t\tPMD_DRV_LOG(INFO, \"Failed to update VSI params\");\n\n\treturn ret;\n}\n\nstatic int\ni40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)\n{\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\n\treturn i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);\n}\n\nstatic int\ni40e_update_flow_control(struct i40e_hw *hw)\n{\n#define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)\n\tstruct i40e_link_status link_status;\n\tuint32_t rxfc = 0, txfc = 0, reg;\n\tuint8_t an_info;\n\tint ret;\n\n\tmemset(&link_status, 0, sizeof(link_status));\n\tret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to get link status information\");\n\t\tgoto write_reg; /* Disable flow control */\n\t}\n\n\tan_info = hw->phy.link_info.an_info;\n\tif (!(an_info & I40E_AQ_AN_COMPLETED)) {\n\t\tPMD_DRV_LOG(INFO, \"Link auto negotiation not completed\");\n\t\tret = I40E_ERR_NOT_READY;\n\t\tgoto write_reg; /* Disable flow control */\n\t}\n\t/**\n\t * If link auto negotiation is enabled, flow control needs to\n\t * be configured according to it\n\t */\n\tswitch (an_info & I40E_LINK_PAUSE_RXTX) {\n\tcase I40E_LINK_PAUSE_RXTX:\n\t\trxfc = 1;\n\t\ttxfc = 1;\n\t\thw->fc.current_mode = I40E_FC_FULL;\n\t\tbreak;\n\tcase I40E_AQ_LINK_PAUSE_RX:\n\t\trxfc = 1;\n\t\thw->fc.current_mode = I40E_FC_RX_PAUSE;\n\t\tbreak;\n\tcase I40E_AQ_LINK_PAUSE_TX:\n\t\ttxfc = 1;\n\t\thw->fc.current_mode = I40E_FC_TX_PAUSE;\n\t\tbreak;\n\tdefault:\n\t\thw->fc.current_mode = I40E_FC_NONE;\n\t\tbreak;\n\t}\n\nwrite_reg:\n\tI40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,\n\t\ttxfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);\n\treg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);\n\treg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;\n\treg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;\n\tI40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);\n\n\treturn ret;\n}\n\n/* PF setup */\nstatic int\ni40e_pf_setup(struct i40e_pf *pf)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tstruct i40e_filter_control_settings settings;\n\tstruct i40e_vsi *vsi;\n\tint ret;\n\n\t/* Clear all stats counters */\n\tpf->offset_loaded = FALSE;\n\tmemset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));\n\tmemset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));\n\n\tret = i40e_pf_get_switch_config(pf);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Could not get switch config, err %d\", ret);\n\t\treturn ret;\n\t}\n\tif (pf->flags & I40E_FLAG_FDIR) {\n\t\t/* make queue allocated first, let FDIR use queue pair 0*/\n\t\tret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);\n\t\tif (ret != I40E_FDIR_QUEUE_ID) {\n\t\t\tPMD_DRV_LOG(ERR, \"queue allocation fails for FDIR :\"\n\t\t\t\t \" ret =%d\", ret);\n\t\t\tpf->flags &= ~I40E_FLAG_FDIR;\n\t\t}\n\t}\n\t/* main VSI setup */\n\tvsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);\n\tif (!vsi) {\n\t\tPMD_DRV_LOG(ERR, \"Setup of main vsi failed\");\n\t\treturn I40E_ERR_NOT_READY;\n\t}\n\tpf->main_vsi = vsi;\n\n\t/* Configure filter control */\n\tmemset(&settings, 0, sizeof(settings));\n\tif (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)\n\t\tsettings.hash_lut_size = I40E_HASH_LUT_SIZE_128;\n\telse if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)\n\t\tsettings.hash_lut_size = I40E_HASH_LUT_SIZE_512;\n\telse {\n\t\tPMD_DRV_LOG(ERR, \"Hash lookup table size (%u) not supported\\n\",\n\t\t\t\t\t\thw->func_caps.rss_table_size);\n\t\treturn I40E_ERR_PARAM;\n\t}\n\tPMD_DRV_LOG(INFO, \"Hardware capability of hash lookup table \"\n\t\t\t\"size: %u\\n\", hw->func_caps.rss_table_size);\n\tpf->hash_lut_size = hw->func_caps.rss_table_size;\n\n\t/* Enable ethtype and macvlan filters */\n\tsettings.enable_ethtype = TRUE;\n\tsettings.enable_macvlan = TRUE;\n\tret = i40e_set_filter_control(hw, &settings);\n\tif (ret)\n\t\tPMD_INIT_LOG(WARNING, \"setup_pf_filter_control failed: %d\",\n\t\t\t\t\t\t\t\tret);\n\n\t/* Update flow control according to the auto negotiation */\n\ti40e_update_flow_control(hw);\n\n\treturn I40E_SUCCESS;\n}\n\nint\ni40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)\n{\n\tuint32_t reg;\n\tuint16_t j;\n\n\t/**\n\t * Set or clear TX Queue Disable flags,\n\t * which is required by hardware.\n\t */\n\ti40e_pre_tx_queue_cfg(hw, q_idx, on);\n\trte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);\n\n\t/* Wait until the request is finished */\n\tfor (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {\n\t\trte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);\n\t\treg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));\n\t\tif (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^\n\t\t\t((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)\n\t\t\t\t\t\t\t& 0x1))) {\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (on) {\n\t\tif (reg & I40E_QTX_ENA_QENA_STAT_MASK)\n\t\t\treturn I40E_SUCCESS; /* already on, skip next steps */\n\n\t\tI40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);\n\t\treg |= I40E_QTX_ENA_QENA_REQ_MASK;\n\t} else {\n\t\tif (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))\n\t\t\treturn I40E_SUCCESS; /* already off, skip next steps */\n\t\treg &= ~I40E_QTX_ENA_QENA_REQ_MASK;\n\t}\n\t/* Write the register */\n\tI40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);\n\t/* Check the result */\n\tfor (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {\n\t\trte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);\n\t\treg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));\n\t\tif (on) {\n\t\t\tif ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&\n\t\t\t\t(reg & I40E_QTX_ENA_QENA_STAT_MASK))\n\t\t\t\tbreak;\n\t\t} else {\n\t\t\tif (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&\n\t\t\t\t!(reg & I40E_QTX_ENA_QENA_STAT_MASK))\n\t\t\t\tbreak;\n\t\t}\n\t}\n\t/* Check if it is timeout */\n\tif (j >= I40E_CHK_Q_ENA_COUNT) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to %s tx queue[%u]\",\n\t\t\t (on ? \"enable\" : \"disable\"), q_idx);\n\t\treturn I40E_ERR_TIMEOUT;\n\t}\n\n\treturn I40E_SUCCESS;\n}\n\n/* Swith on or off the tx queues */\nstatic int\ni40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)\n{\n\tstruct rte_eth_dev_data *dev_data = pf->dev_data;\n\tstruct i40e_tx_queue *txq;\n\tstruct rte_eth_dev *dev = pf->adapter->eth_dev;\n\tuint16_t i;\n\tint ret;\n\n\tfor (i = 0; i < dev_data->nb_tx_queues; i++) {\n\t\ttxq = dev_data->tx_queues[i];\n\t\t/* Don't operate the queue if not configured or\n\t\t * if starting only per queue */\n\t\tif (!txq || !txq->q_set || (on && txq->tx_deferred_start))\n\t\t\tcontinue;\n\t\tif (on)\n\t\t\tret = i40e_dev_tx_queue_start(dev, i);\n\t\telse\n\t\t\tret = i40e_dev_tx_queue_stop(dev, i);\n\t\tif ( ret != I40E_SUCCESS)\n\t\t\treturn ret;\n\t}\n\n\treturn I40E_SUCCESS;\n}\n\nint\ni40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)\n{\n\tuint32_t reg;\n\tuint16_t j;\n\n\t/* Wait until the request is finished */\n\tfor (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {\n\t\trte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);\n\t\treg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));\n\t\tif (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^\n\t\t\t((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))\n\t\t\tbreak;\n\t}\n\n\tif (on) {\n\t\tif (reg & I40E_QRX_ENA_QENA_STAT_MASK)\n\t\t\treturn I40E_SUCCESS; /* Already on, skip next steps */\n\t\treg |= I40E_QRX_ENA_QENA_REQ_MASK;\n\t} else {\n\t\tif (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))\n\t\t\treturn I40E_SUCCESS; /* Already off, skip next steps */\n\t\treg &= ~I40E_QRX_ENA_QENA_REQ_MASK;\n\t}\n\n\t/* Write the register */\n\tI40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);\n\t/* Check the result */\n\tfor (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {\n\t\trte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);\n\t\treg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));\n\t\tif (on) {\n\t\t\tif ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&\n\t\t\t\t(reg & I40E_QRX_ENA_QENA_STAT_MASK))\n\t\t\t\tbreak;\n\t\t} else {\n\t\t\tif (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&\n\t\t\t\t!(reg & I40E_QRX_ENA_QENA_STAT_MASK))\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Check if it is timeout */\n\tif (j >= I40E_CHK_Q_ENA_COUNT) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to %s rx queue[%u]\",\n\t\t\t (on ? \"enable\" : \"disable\"), q_idx);\n\t\treturn I40E_ERR_TIMEOUT;\n\t}\n\n\treturn I40E_SUCCESS;\n}\n/* Switch on or off the rx queues */\nstatic int\ni40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)\n{\n\tstruct rte_eth_dev_data *dev_data = pf->dev_data;\n\tstruct i40e_rx_queue *rxq;\n\tstruct rte_eth_dev *dev = pf->adapter->eth_dev;\n\tuint16_t i;\n\tint ret;\n\n\tfor (i = 0; i < dev_data->nb_rx_queues; i++) {\n\t\trxq = dev_data->rx_queues[i];\n\t\t/* Don't operate the queue if not configured or\n\t\t * if starting only per queue */\n\t\tif (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))\n\t\t\tcontinue;\n\t\tif (on)\n\t\t\tret = i40e_dev_rx_queue_start(dev, i);\n\t\telse\n\t\t\tret = i40e_dev_rx_queue_stop(dev, i);\n\t\tif (ret != I40E_SUCCESS)\n\t\t\treturn ret;\n\t}\n\n\treturn I40E_SUCCESS;\n}\n\n/* Switch on or off all the rx/tx queues */\nint\ni40e_dev_switch_queues(struct i40e_pf *pf, bool on)\n{\n\tint ret;\n\n\tif (on) {\n\t\t/* enable rx queues before enabling tx queues */\n\t\tret = i40e_dev_switch_rx_queues(pf, on);\n\t\tif (ret) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch rx queues\");\n\t\t\treturn ret;\n\t\t}\n\t\tret = i40e_dev_switch_tx_queues(pf, on);\n\t} else {\n\t\t/* Stop tx queues before stopping rx queues */\n\t\tret = i40e_dev_switch_tx_queues(pf, on);\n\t\tif (ret) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch tx queues\");\n\t\t\treturn ret;\n\t\t}\n\t\tret = i40e_dev_switch_rx_queues(pf, on);\n\t}\n\n\treturn ret;\n}\n\n/* Initialize VSI for TX */\nstatic int\ni40e_dev_tx_init(struct i40e_pf *pf)\n{\n\tstruct rte_eth_dev_data *data = pf->dev_data;\n\tuint16_t i;\n\tuint32_t ret = I40E_SUCCESS;\n\tstruct i40e_tx_queue *txq;\n\n\tfor (i = 0; i < data->nb_tx_queues; i++) {\n\t\ttxq = data->tx_queues[i];\n\t\tif (!txq || !txq->q_set)\n\t\t\tcontinue;\n\t\tret = i40e_tx_queue_init(txq);\n\t\tif (ret != I40E_SUCCESS)\n\t\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n/* Initialize VSI for RX */\nstatic int\ni40e_dev_rx_init(struct i40e_pf *pf)\n{\n\tstruct rte_eth_dev_data *data = pf->dev_data;\n\tint ret = I40E_SUCCESS;\n\tuint16_t i;\n\tstruct i40e_rx_queue *rxq;\n\n\ti40e_pf_config_mq_rx(pf);\n\tfor (i = 0; i < data->nb_rx_queues; i++) {\n\t\trxq = data->rx_queues[i];\n\t\tif (!rxq || !rxq->q_set)\n\t\t\tcontinue;\n\n\t\tret = i40e_rx_queue_init(rxq);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to do RX queue \"\n\t\t\t\t \"initialization\");\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn ret;\n}\n\nstatic int\ni40e_dev_rxtx_init(struct i40e_pf *pf)\n{\n\tint err;\n\n\terr = i40e_dev_tx_init(pf);\n\tif (err) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to do TX initialization\");\n\t\treturn err;\n\t}\n\terr = i40e_dev_rx_init(pf);\n\tif (err) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to do RX initialization\");\n\t\treturn err;\n\t}\n\n\treturn err;\n}\n\nstatic int\ni40e_vmdq_setup(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_conf *conf = &dev->data->dev_conf;\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tint i, err, conf_vsis, j, loop;\n\tstruct i40e_vsi *vsi;\n\tstruct i40e_vmdq_info *vmdq_info;\n\tstruct rte_eth_vmdq_rx_conf *vmdq_conf;\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\n\t/*\n\t * Disable interrupt to avoid message from VF. Furthermore, it will\n\t * avoid race condition in VSI creation/destroy.\n\t */\n\ti40e_pf_disable_irq0(hw);\n\n\tif ((pf->flags & I40E_FLAG_VMDQ) == 0) {\n\t\tPMD_INIT_LOG(ERR, \"FW doesn't support VMDQ\");\n\t\treturn -ENOTSUP;\n\t}\n\n\tconf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;\n\tif (conf_vsis > pf->max_nb_vmdq_vsi) {\n\t\tPMD_INIT_LOG(ERR, \"VMDQ config: %u, max support:%u\",\n\t\t\tconf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,\n\t\t\tpf->max_nb_vmdq_vsi);\n\t\treturn -ENOTSUP;\n\t}\n\n\tif (pf->vmdq != NULL) {\n\t\tPMD_INIT_LOG(INFO, \"VMDQ already configured\");\n\t\treturn 0;\n\t}\n\n\tpf->vmdq = rte_zmalloc(\"vmdq_info_struct\",\n\t\t\t\tsizeof(*vmdq_info) * conf_vsis, 0);\n\n\tif (pf->vmdq == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to allocate memory\");\n\t\treturn -ENOMEM;\n\t}\n\n\tvmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;\n\n\t/* Create VMDQ VSI */\n\tfor (i = 0; i < conf_vsis; i++) {\n\t\tvsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,\n\t\t\t\tvmdq_conf->enable_loop_back);\n\t\tif (vsi == NULL) {\n\t\t\tPMD_INIT_LOG(ERR, \"Failed to create VMDQ VSI\");\n\t\t\terr = -1;\n\t\t\tgoto err_vsi_setup;\n\t\t}\n\t\tvmdq_info = &pf->vmdq[i];\n\t\tvmdq_info->pf = pf;\n\t\tvmdq_info->vsi = vsi;\n\t}\n\tpf->nb_cfg_vmdq_vsi = conf_vsis;\n\n\t/* Configure Vlan */\n\tloop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;\n\tfor (i = 0; i < vmdq_conf->nb_pool_maps; i++) {\n\t\tfor (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {\n\t\t\tif (vmdq_conf->pool_map[i].pools & (1UL << j)) {\n\t\t\t\tPMD_INIT_LOG(INFO, \"Add vlan %u to vmdq pool %u\",\n\t\t\t\t\tvmdq_conf->pool_map[i].vlan_id, j);\n\n\t\t\t\terr = i40e_vsi_add_vlan(pf->vmdq[j].vsi,\n\t\t\t\t\t\tvmdq_conf->pool_map[i].vlan_id);\n\t\t\t\tif (err) {\n\t\t\t\t\tPMD_INIT_LOG(ERR, \"Failed to add vlan\");\n\t\t\t\t\terr = -1;\n\t\t\t\t\tgoto err_vsi_setup;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\ti40e_pf_enable_irq0(hw);\n\n\treturn 0;\n\nerr_vsi_setup:\n\tfor (i = 0; i < conf_vsis; i++)\n\t\tif (pf->vmdq[i].vsi == NULL)\n\t\t\tbreak;\n\t\telse\n\t\t\ti40e_vsi_release(pf->vmdq[i].vsi);\n\n\trte_free(pf->vmdq);\n\tpf->vmdq = NULL;\n\ti40e_pf_enable_irq0(hw);\n\treturn err;\n}\n\nstatic void\ni40e_stat_update_32(struct i40e_hw *hw,\n\t\t uint32_t reg,\n\t\t bool offset_loaded,\n\t\t uint64_t *offset,\n\t\t uint64_t *stat)\n{\n\tuint64_t new_data;\n\n\tnew_data = (uint64_t)I40E_READ_REG(hw, reg);\n\tif (!offset_loaded)\n\t\t*offset = new_data;\n\n\tif (new_data >= *offset)\n\t\t*stat = (uint64_t)(new_data - *offset);\n\telse\n\t\t*stat = (uint64_t)((new_data +\n\t\t\t((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);\n}\n\nstatic void\ni40e_stat_update_48(struct i40e_hw *hw,\n\t\t uint32_t hireg,\n\t\t uint32_t loreg,\n\t\t bool offset_loaded,\n\t\t uint64_t *offset,\n\t\t uint64_t *stat)\n{\n\tuint64_t new_data;\n\n\tnew_data = (uint64_t)I40E_READ_REG(hw, loreg);\n\tnew_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &\n\t\t\tI40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;\n\n\tif (!offset_loaded)\n\t\t*offset = new_data;\n\n\tif (new_data >= *offset)\n\t\t*stat = new_data - *offset;\n\telse\n\t\t*stat = (uint64_t)((new_data +\n\t\t\t((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);\n\n\t*stat &= I40E_48_BIT_MASK;\n}\n\n/* Disable IRQ0 */\nvoid\ni40e_pf_disable_irq0(struct i40e_hw *hw)\n{\n\t/* Disable all interrupt types */\n\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);\n\tI40E_WRITE_FLUSH(hw);\n}\n\n/* Enable IRQ0 */\nvoid\ni40e_pf_enable_irq0(struct i40e_hw *hw)\n{\n\tI40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,\n\t\tI40E_PFINT_DYN_CTL0_INTENA_MASK |\n\t\tI40E_PFINT_DYN_CTL0_CLEARPBA_MASK |\n\t\tI40E_PFINT_DYN_CTL0_ITR_INDX_MASK);\n\tI40E_WRITE_FLUSH(hw);\n}\n\nstatic void\ni40e_pf_config_irq0(struct i40e_hw *hw)\n{\n\t/* read pending request and disable first */\n\ti40e_pf_disable_irq0(hw);\n\tI40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);\n\tI40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,\n\t\tI40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);\n\n\t/* Link no queues with irq0 */\n\tI40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,\n\t\tI40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);\n}\n\nstatic void\ni40e_dev_handle_vfr_event(struct rte_eth_dev *dev)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tint i;\n\tuint16_t abs_vf_id;\n\tuint32_t index, offset, val;\n\n\tif (!pf->vfs)\n\t\treturn;\n\t/**\n\t * Try to find which VF trigger a reset, use absolute VF id to access\n\t * since the reg is global register.\n\t */\n\tfor (i = 0; i < pf->vf_num; i++) {\n\t\tabs_vf_id = hw->func_caps.vf_base_id + i;\n\t\tindex = abs_vf_id / I40E_UINT32_BIT_SIZE;\n\t\toffset = abs_vf_id % I40E_UINT32_BIT_SIZE;\n\t\tval = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));\n\t\t/* VFR event occured */\n\t\tif (val & (0x1 << offset)) {\n\t\t\tint ret;\n\n\t\t\t/* Clear the event first */\n\t\t\tI40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),\n\t\t\t\t\t\t\t(0x1 << offset));\n\t\t\tPMD_DRV_LOG(INFO, \"VF %u reset occured\", abs_vf_id);\n\t\t\t/**\n\t\t\t * Only notify a VF reset event occured,\n\t\t\t * don't trigger another SW reset\n\t\t\t */\n\t\t\tret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);\n\t\t\tif (ret != I40E_SUCCESS)\n\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to do VF reset\");\n\t\t}\n\t}\n}\n\nstatic void\ni40e_dev_handle_aq_msg(struct rte_eth_dev *dev)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_arq_event_info info;\n\tuint16_t pending, opcode;\n\tint ret;\n\n\tinfo.buf_len = I40E_AQ_BUF_SZ;\n\tinfo.msg_buf = rte_zmalloc(\"msg_buffer\", info.buf_len, 0);\n\tif (!info.msg_buf) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to allocate mem\");\n\t\treturn;\n\t}\n\n\tpending = 1;\n\twhile (pending) {\n\t\tret = i40e_clean_arq_element(hw, &info, &pending);\n\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(INFO, \"Failed to read msg from AdminQ, \"\n\t\t\t\t \"aq_err: %u\", hw->aq.asq_last_status);\n\t\t\tbreak;\n\t\t}\n\t\topcode = rte_le_to_cpu_16(info.desc.opcode);\n\n\t\tswitch (opcode) {\n\t\tcase i40e_aqc_opc_send_msg_to_pf:\n\t\t\t/* Refer to i40e_aq_send_msg_to_pf() for argument layout*/\n\t\t\ti40e_pf_host_handle_vf_msg(dev,\n\t\t\t\t\trte_le_to_cpu_16(info.desc.retval),\n\t\t\t\t\trte_le_to_cpu_32(info.desc.cookie_high),\n\t\t\t\t\trte_le_to_cpu_32(info.desc.cookie_low),\n\t\t\t\t\tinfo.msg_buf,\n\t\t\t\t\tinfo.msg_len);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(ERR, \"Request %u is not supported yet\",\n\t\t\t\t opcode);\n\t\t\tbreak;\n\t\t}\n\t}\n\trte_free(info.msg_buf);\n}\n\n/*\n * Interrupt handler is registered as the alarm callback for handling LSC\n * interrupt in a definite of time, in order to wait the NIC into a stable\n * state. Currently it waits 1 sec in i40e for the link up interrupt, and\n * no need for link down interrupt.\n */\nstatic void\ni40e_dev_interrupt_delayed_handler(void *param)\n{\n\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t icr0;\n\n\t/* read interrupt causes again */\n\ticr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);\n\n#ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER\n\tif (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)\n\t\tPMD_DRV_LOG(ERR, \"ICR0: unrecoverable ECC error\\n\");\n\tif (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)\n\t\tPMD_DRV_LOG(ERR, \"ICR0: malicious programming detected\\n\");\n\tif (icr0 & I40E_PFINT_ICR0_GRST_MASK)\n\t\tPMD_DRV_LOG(INFO, \"ICR0: global reset requested\\n\");\n\tif (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)\n\t\tPMD_DRV_LOG(INFO, \"ICR0: PCI exception\\n activated\\n\");\n\tif (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)\n\t\tPMD_DRV_LOG(INFO, \"ICR0: a change in the storm control \"\n\t\t\t\t\t\t\t\t\"state\\n\");\n\tif (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)\n\t\tPMD_DRV_LOG(ERR, \"ICR0: HMC error\\n\");\n\tif (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)\n\t\tPMD_DRV_LOG(ERR, \"ICR0: protocol engine critical error\\n\");\n#endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */\n\n\tif (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {\n\t\tPMD_DRV_LOG(INFO, \"INT:VF reset detected\\n\");\n\t\ti40e_dev_handle_vfr_event(dev);\n\t}\n\tif (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {\n\t\tPMD_DRV_LOG(INFO, \"INT:ADMINQ event\\n\");\n\t\ti40e_dev_handle_aq_msg(dev);\n\t}\n\n\t/* handle the link up interrupt in an alarm callback */\n\ti40e_dev_link_update(dev, 0);\n\t_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);\n\n\ti40e_pf_enable_irq0(hw);\n\trte_intr_enable(&(dev->pci_dev->intr_handle));\n}\n\n/**\n * Interrupt handler triggered by NIC for handling\n * specific interrupt.\n *\n * @param handle\n * Pointer to interrupt handle.\n * @param param\n * The address of parameter (struct rte_eth_dev *) regsitered before.\n *\n * @return\n * void\n */\nstatic void\ni40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,\n\t\t\t void *param)\n{\n\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t icr0;\n\n\t/* Disable interrupt */\n\ti40e_pf_disable_irq0(hw);\n\n\t/* read out interrupt causes */\n\ticr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);\n\n\t/* No interrupt event indicated */\n\tif (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {\n\t\tPMD_DRV_LOG(INFO, \"No interrupt event\");\n\t\tgoto done;\n\t}\n#ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER\n\tif (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)\n\t\tPMD_DRV_LOG(ERR, \"ICR0: unrecoverable ECC error\");\n\tif (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)\n\t\tPMD_DRV_LOG(ERR, \"ICR0: malicious programming detected\");\n\tif (icr0 & I40E_PFINT_ICR0_GRST_MASK)\n\t\tPMD_DRV_LOG(INFO, \"ICR0: global reset requested\");\n\tif (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)\n\t\tPMD_DRV_LOG(INFO, \"ICR0: PCI exception activated\");\n\tif (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)\n\t\tPMD_DRV_LOG(INFO, \"ICR0: a change in the storm control state\");\n\tif (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)\n\t\tPMD_DRV_LOG(ERR, \"ICR0: HMC error\");\n\tif (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)\n\t\tPMD_DRV_LOG(ERR, \"ICR0: protocol engine critical error\");\n#endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */\n\n\tif (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {\n\t\tPMD_DRV_LOG(INFO, \"ICR0: VF reset detected\");\n\t\ti40e_dev_handle_vfr_event(dev);\n\t}\n\tif (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {\n\t\tPMD_DRV_LOG(INFO, \"ICR0: adminq event\");\n\t\ti40e_dev_handle_aq_msg(dev);\n\t}\n\n\t/* Link Status Change interrupt */\n\tif (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {\n#define I40E_US_PER_SECOND 1000000\n\t\tstruct rte_eth_link link;\n\n\t\tPMD_DRV_LOG(INFO, \"ICR0: link status changed\\n\");\n\t\tmemset(&link, 0, sizeof(link));\n\t\trte_i40e_dev_atomic_read_link_status(dev, &link);\n\t\ti40e_dev_link_update(dev, 0);\n\n\t\t/*\n\t\t * For link up interrupt, it needs to wait 1 second to let the\n\t\t * hardware be a stable state. Otherwise several consecutive\n\t\t * interrupts can be observed.\n\t\t * For link down interrupt, no need to wait.\n\t\t */\n\t\tif (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,\n\t\t\ti40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)\n\t\t\treturn;\n\t\telse\n\t\t\t_rte_eth_dev_callback_process(dev,\n\t\t\t\tRTE_ETH_EVENT_INTR_LSC);\n\t}\n\ndone:\n\t/* Enable interrupt */\n\ti40e_pf_enable_irq0(hw);\n\trte_intr_enable(&(dev->pci_dev->intr_handle));\n}\n\nstatic int\ni40e_add_macvlan_filters(struct i40e_vsi *vsi,\n\t\t\t struct i40e_macvlan_filter *filter,\n\t\t\t int total)\n{\n\tint ele_num, ele_buff_size;\n\tint num, actual_num, i;\n\tuint16_t flags;\n\tint ret = I40E_SUCCESS;\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\tstruct i40e_aqc_add_macvlan_element_data *req_list;\n\n\tif (filter == NULL || total == 0)\n\t\treturn I40E_ERR_PARAM;\n\tele_num = hw->aq.asq_buf_size / sizeof(*req_list);\n\tele_buff_size = hw->aq.asq_buf_size;\n\n\treq_list = rte_zmalloc(\"macvlan_add\", ele_buff_size, 0);\n\tif (req_list == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"Fail to allocate memory\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\n\tnum = 0;\n\tdo {\n\t\tactual_num = (num + ele_num > total) ? (total - num) : ele_num;\n\t\tmemset(req_list, 0, ele_buff_size);\n\n\t\tfor (i = 0; i < actual_num; i++) {\n\t\t\t(void)rte_memcpy(req_list[i].mac_addr,\n\t\t\t\t&filter[num + i].macaddr, ETH_ADDR_LEN);\n\t\t\treq_list[i].vlan_tag =\n\t\t\t\trte_cpu_to_le_16(filter[num + i].vlan_id);\n\n\t\t\tswitch (filter[num + i].filter_type) {\n\t\t\tcase RTE_MAC_PERFECT_MATCH:\n\t\t\t\tflags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |\n\t\t\t\t\tI40E_AQC_MACVLAN_ADD_IGNORE_VLAN;\n\t\t\t\tbreak;\n\t\t\tcase RTE_MACVLAN_PERFECT_MATCH:\n\t\t\t\tflags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;\n\t\t\t\tbreak;\n\t\t\tcase RTE_MAC_HASH_MATCH:\n\t\t\t\tflags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |\n\t\t\t\t\tI40E_AQC_MACVLAN_ADD_IGNORE_VLAN;\n\t\t\t\tbreak;\n\t\t\tcase RTE_MACVLAN_HASH_MATCH:\n\t\t\t\tflags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tPMD_DRV_LOG(ERR, \"Invalid MAC match type\\n\");\n\t\t\t\tret = I40E_ERR_PARAM;\n\t\t\t\tgoto DONE;\n\t\t\t}\n\n\t\t\treq_list[i].queue_number = 0;\n\n\t\t\treq_list[i].flags = rte_cpu_to_le_16(flags);\n\t\t}\n\n\t\tret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,\n\t\t\t\t\t\tactual_num, NULL);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to add macvlan filter\");\n\t\t\tgoto DONE;\n\t\t}\n\t\tnum += actual_num;\n\t} while (num < total);\n\nDONE:\n\trte_free(req_list);\n\treturn ret;\n}\n\nstatic int\ni40e_remove_macvlan_filters(struct i40e_vsi *vsi,\n\t\t\t struct i40e_macvlan_filter *filter,\n\t\t\t int total)\n{\n\tint ele_num, ele_buff_size;\n\tint num, actual_num, i;\n\tuint16_t flags;\n\tint ret = I40E_SUCCESS;\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\tstruct i40e_aqc_remove_macvlan_element_data *req_list;\n\n\tif (filter == NULL || total == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\tele_num = hw->aq.asq_buf_size / sizeof(*req_list);\n\tele_buff_size = hw->aq.asq_buf_size;\n\n\treq_list = rte_zmalloc(\"macvlan_remove\", ele_buff_size, 0);\n\tif (req_list == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"Fail to allocate memory\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\n\tnum = 0;\n\tdo {\n\t\tactual_num = (num + ele_num > total) ? (total - num) : ele_num;\n\t\tmemset(req_list, 0, ele_buff_size);\n\n\t\tfor (i = 0; i < actual_num; i++) {\n\t\t\t(void)rte_memcpy(req_list[i].mac_addr,\n\t\t\t\t&filter[num + i].macaddr, ETH_ADDR_LEN);\n\t\t\treq_list[i].vlan_tag =\n\t\t\t\trte_cpu_to_le_16(filter[num + i].vlan_id);\n\n\t\t\tswitch (filter[num + i].filter_type) {\n\t\t\tcase RTE_MAC_PERFECT_MATCH:\n\t\t\t\tflags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |\n\t\t\t\t\tI40E_AQC_MACVLAN_DEL_IGNORE_VLAN;\n\t\t\t\tbreak;\n\t\t\tcase RTE_MACVLAN_PERFECT_MATCH:\n\t\t\t\tflags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;\n\t\t\t\tbreak;\n\t\t\tcase RTE_MAC_HASH_MATCH:\n\t\t\t\tflags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |\n\t\t\t\t\tI40E_AQC_MACVLAN_DEL_IGNORE_VLAN;\n\t\t\t\tbreak;\n\t\t\tcase RTE_MACVLAN_HASH_MATCH:\n\t\t\t\tflags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tPMD_DRV_LOG(ERR, \"Invalid MAC filter type\\n\");\n\t\t\t\tret = I40E_ERR_PARAM;\n\t\t\t\tgoto DONE;\n\t\t\t}\n\t\t\treq_list[i].flags = rte_cpu_to_le_16(flags);\n\t\t}\n\n\t\tret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,\n\t\t\t\t\t\tactual_num, NULL);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to remove macvlan filter\");\n\t\t\tgoto DONE;\n\t\t}\n\t\tnum += actual_num;\n\t} while (num < total);\n\nDONE:\n\trte_free(req_list);\n\treturn ret;\n}\n\n/* Find out specific MAC filter */\nstatic struct i40e_mac_filter *\ni40e_find_mac_filter(struct i40e_vsi *vsi,\n\t\t\t struct ether_addr *macaddr)\n{\n\tstruct i40e_mac_filter *f;\n\n\tTAILQ_FOREACH(f, &vsi->mac_list, next) {\n\t\tif (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))\n\t\t\treturn f;\n\t}\n\n\treturn NULL;\n}\n\nstatic bool\ni40e_find_vlan_filter(struct i40e_vsi *vsi,\n\t\t\t uint16_t vlan_id)\n{\n\tuint32_t vid_idx, vid_bit;\n\n\tif (vlan_id > ETH_VLAN_ID_MAX)\n\t\treturn 0;\n\n\tvid_idx = I40E_VFTA_IDX(vlan_id);\n\tvid_bit = I40E_VFTA_BIT(vlan_id);\n\n\tif (vsi->vfta[vid_idx] & vid_bit)\n\t\treturn 1;\n\telse\n\t\treturn 0;\n}\n\nstatic void\ni40e_set_vlan_filter(struct i40e_vsi *vsi,\n\t\t\t uint16_t vlan_id, bool on)\n{\n\tuint32_t vid_idx, vid_bit;\n\n\tif (vlan_id > ETH_VLAN_ID_MAX)\n\t\treturn;\n\n\tvid_idx = I40E_VFTA_IDX(vlan_id);\n\tvid_bit = I40E_VFTA_BIT(vlan_id);\n\n\tif (on)\n\t\tvsi->vfta[vid_idx] |= vid_bit;\n\telse\n\t\tvsi->vfta[vid_idx] &= ~vid_bit;\n}\n\n/**\n * Find all vlan options for specific mac addr,\n * return with actual vlan found.\n */\nstatic inline int\ni40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,\n\t\t\t struct i40e_macvlan_filter *mv_f,\n\t\t\t int num, struct ether_addr *addr)\n{\n\tint i;\n\tuint32_t j, k;\n\n\t/**\n\t * Not to use i40e_find_vlan_filter to decrease the loop time,\n\t * although the code looks complex.\n\t */\n\tif (num < vsi->vlan_num)\n\t\treturn I40E_ERR_PARAM;\n\n\ti = 0;\n\tfor (j = 0; j < I40E_VFTA_SIZE; j++) {\n\t\tif (vsi->vfta[j]) {\n\t\t\tfor (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {\n\t\t\t\tif (vsi->vfta[j] & (1 << k)) {\n\t\t\t\t\tif (i > num - 1) {\n\t\t\t\t\t\tPMD_DRV_LOG(ERR, \"vlan number \"\n\t\t\t\t\t\t\t \"not match\");\n\t\t\t\t\t\treturn I40E_ERR_PARAM;\n\t\t\t\t\t}\n\t\t\t\t\t(void)rte_memcpy(&mv_f[i].macaddr,\n\t\t\t\t\t\t\taddr, ETH_ADDR_LEN);\n\t\t\t\t\tmv_f[i].vlan_id =\n\t\t\t\t\t\tj * I40E_UINT32_BIT_SIZE + k;\n\t\t\t\t\ti++;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\treturn I40E_SUCCESS;\n}\n\nstatic inline int\ni40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,\n\t\t\t struct i40e_macvlan_filter *mv_f,\n\t\t\t int num,\n\t\t\t uint16_t vlan)\n{\n\tint i = 0;\n\tstruct i40e_mac_filter *f;\n\n\tif (num < vsi->mac_num)\n\t\treturn I40E_ERR_PARAM;\n\n\tTAILQ_FOREACH(f, &vsi->mac_list, next) {\n\t\tif (i > num - 1) {\n\t\t\tPMD_DRV_LOG(ERR, \"buffer number not match\");\n\t\t\treturn I40E_ERR_PARAM;\n\t\t}\n\t\t(void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,\n\t\t\t\tETH_ADDR_LEN);\n\t\tmv_f[i].vlan_id = vlan;\n\t\tmv_f[i].filter_type = f->mac_info.filter_type;\n\t\ti++;\n\t}\n\n\treturn I40E_SUCCESS;\n}\n\nstatic int\ni40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)\n{\n\tint i, num;\n\tstruct i40e_mac_filter *f;\n\tstruct i40e_macvlan_filter *mv_f;\n\tint ret = I40E_SUCCESS;\n\n\tif (vsi == NULL || vsi->mac_num == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\t/* Case that no vlan is set */\n\tif (vsi->vlan_num == 0)\n\t\tnum = vsi->mac_num;\n\telse\n\t\tnum = vsi->mac_num * vsi->vlan_num;\n\n\tmv_f = rte_zmalloc(\"macvlan_data\", num * sizeof(*mv_f), 0);\n\tif (mv_f == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"failed to allocate memory\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\n\ti = 0;\n\tif (vsi->vlan_num == 0) {\n\t\tTAILQ_FOREACH(f, &vsi->mac_list, next) {\n\t\t\t(void)rte_memcpy(&mv_f[i].macaddr,\n\t\t\t\t&f->mac_info.mac_addr, ETH_ADDR_LEN);\n\t\t\tmv_f[i].vlan_id = 0;\n\t\t\ti++;\n\t\t}\n\t} else {\n\t\tTAILQ_FOREACH(f, &vsi->mac_list, next) {\n\t\t\tret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],\n\t\t\t\t\tvsi->vlan_num, &f->mac_info.mac_addr);\n\t\t\tif (ret != I40E_SUCCESS)\n\t\t\t\tgoto DONE;\n\t\t\ti += vsi->vlan_num;\n\t\t}\n\t}\n\n\tret = i40e_remove_macvlan_filters(vsi, mv_f, num);\nDONE:\n\trte_free(mv_f);\n\n\treturn ret;\n}\n\nint\ni40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)\n{\n\tstruct i40e_macvlan_filter *mv_f;\n\tint mac_num;\n\tint ret = I40E_SUCCESS;\n\n\tif (!vsi || vlan > ETHER_MAX_VLAN_ID)\n\t\treturn I40E_ERR_PARAM;\n\n\t/* If it's already set, just return */\n\tif (i40e_find_vlan_filter(vsi,vlan))\n\t\treturn I40E_SUCCESS;\n\n\tmac_num = vsi->mac_num;\n\n\tif (mac_num == 0) {\n\t\tPMD_DRV_LOG(ERR, \"Error! VSI doesn't have a mac addr\");\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\tmv_f = rte_zmalloc(\"macvlan_data\", mac_num * sizeof(*mv_f), 0);\n\n\tif (mv_f == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"failed to allocate memory\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\n\tret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);\n\n\tif (ret != I40E_SUCCESS)\n\t\tgoto DONE;\n\n\tret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);\n\n\tif (ret != I40E_SUCCESS)\n\t\tgoto DONE;\n\n\ti40e_set_vlan_filter(vsi, vlan, 1);\n\n\tvsi->vlan_num++;\n\tret = I40E_SUCCESS;\nDONE:\n\trte_free(mv_f);\n\treturn ret;\n}\n\nint\ni40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)\n{\n\tstruct i40e_macvlan_filter *mv_f;\n\tint mac_num;\n\tint ret = I40E_SUCCESS;\n\n\t/**\n\t * Vlan 0 is the generic filter for untagged packets\n\t * and can't be removed.\n\t */\n\tif (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)\n\t\treturn I40E_ERR_PARAM;\n\n\t/* If can't find it, just return */\n\tif (!i40e_find_vlan_filter(vsi, vlan))\n\t\treturn I40E_ERR_PARAM;\n\n\tmac_num = vsi->mac_num;\n\n\tif (mac_num == 0) {\n\t\tPMD_DRV_LOG(ERR, \"Error! VSI doesn't have a mac addr\");\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\tmv_f = rte_zmalloc(\"macvlan_data\", mac_num * sizeof(*mv_f), 0);\n\n\tif (mv_f == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"failed to allocate memory\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\n\tret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);\n\n\tif (ret != I40E_SUCCESS)\n\t\tgoto DONE;\n\n\tret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);\n\n\tif (ret != I40E_SUCCESS)\n\t\tgoto DONE;\n\n\t/* This is last vlan to remove, replace all mac filter with vlan 0 */\n\tif (vsi->vlan_num == 1) {\n\t\tret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);\n\t\tif (ret != I40E_SUCCESS)\n\t\t\tgoto DONE;\n\n\t\tret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);\n\t\tif (ret != I40E_SUCCESS)\n\t\t\tgoto DONE;\n\t}\n\n\ti40e_set_vlan_filter(vsi, vlan, 0);\n\n\tvsi->vlan_num--;\n\tret = I40E_SUCCESS;\nDONE:\n\trte_free(mv_f);\n\treturn ret;\n}\n\nint\ni40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)\n{\n\tstruct i40e_mac_filter *f;\n\tstruct i40e_macvlan_filter *mv_f;\n\tint i, vlan_num = 0;\n\tint ret = I40E_SUCCESS;\n\n\t/* If it's add and we've config it, return */\n\tf = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);\n\tif (f != NULL)\n\t\treturn I40E_SUCCESS;\n\tif ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||\n\t\t(mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {\n\n\t\t/**\n\t\t * If vlan_num is 0, that's the first time to add mac,\n\t\t * set mask for vlan_id 0.\n\t\t */\n\t\tif (vsi->vlan_num == 0) {\n\t\t\ti40e_set_vlan_filter(vsi, 0, 1);\n\t\t\tvsi->vlan_num = 1;\n\t\t}\n\t\tvlan_num = vsi->vlan_num;\n\t} else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||\n\t\t\t(mac_filter->filter_type == RTE_MAC_HASH_MATCH))\n\t\tvlan_num = 1;\n\n\tmv_f = rte_zmalloc(\"macvlan_data\", vlan_num * sizeof(*mv_f), 0);\n\tif (mv_f == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"failed to allocate memory\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\n\tfor (i = 0; i < vlan_num; i++) {\n\t\tmv_f[i].filter_type = mac_filter->filter_type;\n\t\t(void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,\n\t\t\t\tETH_ADDR_LEN);\n\t}\n\n\tif (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||\n\t\tmac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {\n\t\tret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,\n\t\t\t\t\t&mac_filter->mac_addr);\n\t\tif (ret != I40E_SUCCESS)\n\t\t\tgoto DONE;\n\t}\n\n\tret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);\n\tif (ret != I40E_SUCCESS)\n\t\tgoto DONE;\n\n\t/* Add the mac addr into mac list */\n\tf = rte_zmalloc(\"macv_filter\", sizeof(*f), 0);\n\tif (f == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"failed to allocate memory\");\n\t\tret = I40E_ERR_NO_MEMORY;\n\t\tgoto DONE;\n\t}\n\t(void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,\n\t\t\tETH_ADDR_LEN);\n\tf->mac_info.filter_type = mac_filter->filter_type;\n\tTAILQ_INSERT_TAIL(&vsi->mac_list, f, next);\n\tvsi->mac_num++;\n\n\tret = I40E_SUCCESS;\nDONE:\n\trte_free(mv_f);\n\n\treturn ret;\n}\n\nint\ni40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)\n{\n\tstruct i40e_mac_filter *f;\n\tstruct i40e_macvlan_filter *mv_f;\n\tint i, vlan_num;\n\tenum rte_mac_filter_type filter_type;\n\tint ret = I40E_SUCCESS;\n\n\t/* Can't find it, return an error */\n\tf = i40e_find_mac_filter(vsi, addr);\n\tif (f == NULL)\n\t\treturn I40E_ERR_PARAM;\n\n\tvlan_num = vsi->vlan_num;\n\tfilter_type = f->mac_info.filter_type;\n\tif (filter_type == RTE_MACVLAN_PERFECT_MATCH ||\n\t\tfilter_type == RTE_MACVLAN_HASH_MATCH) {\n\t\tif (vlan_num == 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"VLAN number shouldn't be 0\\n\");\n\t\t\treturn I40E_ERR_PARAM;\n\t\t}\n\t} else if (filter_type == RTE_MAC_PERFECT_MATCH ||\n\t\t\tfilter_type == RTE_MAC_HASH_MATCH)\n\t\tvlan_num = 1;\n\n\tmv_f = rte_zmalloc(\"macvlan_data\", vlan_num * sizeof(*mv_f), 0);\n\tif (mv_f == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"failed to allocate memory\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\n\tfor (i = 0; i < vlan_num; i++) {\n\t\tmv_f[i].filter_type = filter_type;\n\t\t(void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,\n\t\t\t\tETH_ADDR_LEN);\n\t}\n\tif (filter_type == RTE_MACVLAN_PERFECT_MATCH ||\n\t\t\tfilter_type == RTE_MACVLAN_HASH_MATCH) {\n\t\tret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);\n\t\tif (ret != I40E_SUCCESS)\n\t\t\tgoto DONE;\n\t}\n\n\tret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);\n\tif (ret != I40E_SUCCESS)\n\t\tgoto DONE;\n\n\t/* Remove the mac addr into mac list */\n\tTAILQ_REMOVE(&vsi->mac_list, f, next);\n\trte_free(f);\n\tvsi->mac_num--;\n\n\tret = I40E_SUCCESS;\nDONE:\n\trte_free(mv_f);\n\treturn ret;\n}\n\n/* Configure hash enable flags for RSS */\nuint64_t\ni40e_config_hena(uint64_t flags)\n{\n\tuint64_t hena = 0;\n\n\tif (!flags)\n\t\treturn hena;\n\n\tif (flags & ETH_RSS_FRAG_IPV4)\n\t\thena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;\n\tif (flags & ETH_RSS_NONFRAG_IPV4_TCP)\n\t\thena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;\n\tif (flags & ETH_RSS_NONFRAG_IPV4_UDP)\n\t\thena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;\n\tif (flags & ETH_RSS_NONFRAG_IPV4_SCTP)\n\t\thena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;\n\tif (flags & ETH_RSS_NONFRAG_IPV4_OTHER)\n\t\thena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;\n\tif (flags & ETH_RSS_FRAG_IPV6)\n\t\thena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;\n\tif (flags & ETH_RSS_NONFRAG_IPV6_TCP)\n\t\thena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;\n\tif (flags & ETH_RSS_NONFRAG_IPV6_UDP)\n\t\thena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;\n\tif (flags & ETH_RSS_NONFRAG_IPV6_SCTP)\n\t\thena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;\n\tif (flags & ETH_RSS_NONFRAG_IPV6_OTHER)\n\t\thena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;\n\tif (flags & ETH_RSS_L2_PAYLOAD)\n\t\thena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;\n\n\treturn hena;\n}\n\n/* Parse the hash enable flags */\nuint64_t\ni40e_parse_hena(uint64_t flags)\n{\n\tuint64_t rss_hf = 0;\n\n\tif (!flags)\n\t\treturn rss_hf;\n\tif (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))\n\t\trss_hf |= ETH_RSS_FRAG_IPV4;\n\tif (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;\n\tif (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;\n\tif (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;\n\tif (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;\n\tif (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))\n\t\trss_hf |= ETH_RSS_FRAG_IPV6;\n\tif (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;\n\tif (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;\n\tif (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;\n\tif (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;\n\tif (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))\n\t\trss_hf |= ETH_RSS_L2_PAYLOAD;\n\n\treturn rss_hf;\n}\n\n/* Disable RSS */\nstatic void\ni40e_pf_disable_rss(struct i40e_pf *pf)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tuint64_t hena;\n\n\thena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));\n\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;\n\thena &= ~I40E_RSS_HENA_ALL;\n\tI40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);\n\tI40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));\n\tI40E_WRITE_FLUSH(hw);\n}\n\nstatic int\ni40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)\n{\n\tuint32_t *hash_key;\n\tuint8_t hash_key_len;\n\tuint64_t rss_hf;\n\tuint16_t i;\n\tuint64_t hena;\n\n\thash_key = (uint32_t *)(rss_conf->rss_key);\n\thash_key_len = rss_conf->rss_key_len;\n\tif (hash_key != NULL && hash_key_len >=\n\t\t(I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {\n\t\t/* Fill in RSS hash key */\n\t\tfor (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)\n\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);\n\t}\n\n\trss_hf = rss_conf->rss_hf;\n\thena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));\n\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;\n\thena &= ~I40E_RSS_HENA_ALL;\n\thena |= i40e_config_hena(rss_hf);\n\tI40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);\n\tI40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));\n\tI40E_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\nstatic int\ni40e_dev_rss_hash_update(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_conf *rss_conf)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;\n\tuint64_t hena;\n\n\thena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));\n\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;\n\tif (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */\n\t\tif (rss_hf != 0) /* Enable RSS */\n\t\t\treturn -EINVAL;\n\t\treturn 0; /* Nothing to do */\n\t}\n\t/* RSS enabled */\n\tif (rss_hf == 0) /* Disable RSS */\n\t\treturn -EINVAL;\n\n\treturn i40e_hw_rss_hash_set(hw, rss_conf);\n}\n\nstatic int\ni40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_conf *rss_conf)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);\n\tuint64_t hena;\n\tuint16_t i;\n\n\tif (hash_key != NULL) {\n\t\tfor (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)\n\t\t\thash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));\n\t\trss_conf->rss_key_len = i * sizeof(uint32_t);\n\t}\n\thena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));\n\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;\n\trss_conf->rss_hf = i40e_parse_hena(hena);\n\n\treturn 0;\n}\n\nstatic int\ni40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)\n{\n\tswitch (filter_type) {\n\tcase RTE_TUNNEL_FILTER_IMAC_IVLAN:\n\t\t*flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;\n\t\tbreak;\n\tcase RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:\n\t\t*flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;\n\t\tbreak;\n\tcase RTE_TUNNEL_FILTER_IMAC_TENID:\n\t\t*flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;\n\t\tbreak;\n\tcase RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:\n\t\t*flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;\n\t\tbreak;\n\tcase ETH_TUNNEL_FILTER_IMAC:\n\t\t*flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid tunnel filter type\");\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40e_dev_tunnel_filter_set(struct i40e_pf *pf,\n\t\t\tstruct rte_eth_tunnel_filter_conf *tunnel_filter,\n\t\t\tuint8_t add)\n{\n\tuint16_t ip_type;\n\tuint8_t tun_type = 0;\n\tint val, ret = 0;\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tstruct i40e_vsi *vsi = pf->main_vsi;\n\tstruct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;\n\tstruct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;\n\n\tcld_filter = rte_zmalloc(\"tunnel_filter\",\n\t\tsizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),\n\t\t0);\n\n\tif (NULL == cld_filter) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to alloc memory.\");\n\t\treturn -EINVAL;\n\t}\n\tpfilter = cld_filter;\n\n\t(void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,\n\t\t\tsizeof(struct ether_addr));\n\t(void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,\n\t\t\tsizeof(struct ether_addr));\n\n\tpfilter->inner_vlan = tunnel_filter->inner_vlan;\n\tif (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {\n\t\tip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;\n\t\t(void)rte_memcpy(&pfilter->ipaddr.v4.data,\n\t\t\t\t&tunnel_filter->ip_addr,\n\t\t\t\tsizeof(pfilter->ipaddr.v4.data));\n\t} else {\n\t\tip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;\n\t\t(void)rte_memcpy(&pfilter->ipaddr.v6.data,\n\t\t\t\t&tunnel_filter->ip_addr,\n\t\t\t\tsizeof(pfilter->ipaddr.v6.data));\n\t}\n\n\t/* check tunneled type */\n\tswitch (tunnel_filter->tunnel_type) {\n\tcase RTE_TUNNEL_TYPE_VXLAN:\n\t\ttun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;\n\t\tbreak;\n\tcase RTE_TUNNEL_TYPE_NVGRE:\n\t\ttun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;\n\t\tbreak;\n\tdefault:\n\t\t/* Other tunnel types is not supported. */\n\t\tPMD_DRV_LOG(ERR, \"tunnel type is not supported.\");\n\t\trte_free(cld_filter);\n\t\treturn -EINVAL;\n\t}\n\n\tval = i40e_dev_get_filter_type(tunnel_filter->filter_type,\n\t\t\t\t\t\t&pfilter->flags);\n\tif (val < 0) {\n\t\trte_free(cld_filter);\n\t\treturn -EINVAL;\n\t}\n\n\tpfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |\n\t\t(tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);\n\tpfilter->tenant_id = tunnel_filter->tenant_id;\n\tpfilter->queue_number = tunnel_filter->queue_id;\n\n\tif (add)\n\t\tret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);\n\telse\n\t\tret = i40e_aq_remove_cloud_filters(hw, vsi->seid,\n\t\t\t\t\t\tcld_filter, 1);\n\n\trte_free(cld_filter);\n\treturn ret;\n}\n\nstatic int\ni40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)\n{\n\tuint8_t i;\n\n\tfor (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {\n\t\tif (pf->vxlan_ports[i] == port)\n\t\t\treturn i;\n\t}\n\n\treturn -1;\n}\n\nstatic int\ni40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)\n{\n\tint idx, ret;\n\tuint8_t filter_idx;\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\n\tidx = i40e_get_vxlan_port_idx(pf, port);\n\n\t/* Check if port already exists */\n\tif (idx >= 0) {\n\t\tPMD_DRV_LOG(ERR, \"Port %d already offloaded\", port);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Now check if there is space to add the new port */\n\tidx = i40e_get_vxlan_port_idx(pf, 0);\n\tif (idx < 0) {\n\t\tPMD_DRV_LOG(ERR, \"Maximum number of UDP ports reached,\"\n\t\t\t\"not adding port %d\", port);\n\t\treturn -ENOSPC;\n\t}\n\n\tret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,\n\t\t\t\t\t&filter_idx, NULL);\n\tif (ret < 0) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to add VXLAN UDP port %d\", port);\n\t\treturn -1;\n\t}\n\n\tPMD_DRV_LOG(INFO, \"Added port %d with AQ command with index %d\",\n\t\t\t port, filter_idx);\n\n\t/* New port: add it and mark its index in the bitmap */\n\tpf->vxlan_ports[idx] = port;\n\tpf->vxlan_bitmap |= (1 << idx);\n\n\tif (!(pf->flags & I40E_FLAG_VXLAN))\n\t\tpf->flags |= I40E_FLAG_VXLAN;\n\n\treturn 0;\n}\n\nstatic int\ni40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)\n{\n\tint idx;\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\n\tif (!(pf->flags & I40E_FLAG_VXLAN)) {\n\t\tPMD_DRV_LOG(ERR, \"VXLAN UDP port was not configured.\");\n\t\treturn -EINVAL;\n\t}\n\n\tidx = i40e_get_vxlan_port_idx(pf, port);\n\n\tif (idx < 0) {\n\t\tPMD_DRV_LOG(ERR, \"Port %d doesn't exist\", port);\n\t\treturn -EINVAL;\n\t}\n\n\tif (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to delete VXLAN UDP port %d\", port);\n\t\treturn -1;\n\t}\n\n\tPMD_DRV_LOG(INFO, \"Deleted port %d with AQ command with index %d\",\n\t\t\tport, idx);\n\n\tpf->vxlan_ports[idx] = 0;\n\tpf->vxlan_bitmap &= ~(1 << idx);\n\n\tif (!pf->vxlan_bitmap)\n\t\tpf->flags &= ~I40E_FLAG_VXLAN;\n\n\treturn 0;\n}\n\n/* Add UDP tunneling port */\nstatic int\ni40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_udp_tunnel *udp_tunnel)\n{\n\tint ret = 0;\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\n\tif (udp_tunnel == NULL)\n\t\treturn -EINVAL;\n\n\tswitch (udp_tunnel->prot_type) {\n\tcase RTE_TUNNEL_TYPE_VXLAN:\n\t\tret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);\n\t\tbreak;\n\n\tcase RTE_TUNNEL_TYPE_GENEVE:\n\tcase RTE_TUNNEL_TYPE_TEREDO:\n\t\tPMD_DRV_LOG(ERR, \"Tunnel type is not supported now.\");\n\t\tret = -1;\n\t\tbreak;\n\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Invalid tunnel type\");\n\t\tret = -1;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n/* Remove UDP tunneling port */\nstatic int\ni40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_udp_tunnel *udp_tunnel)\n{\n\tint ret = 0;\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\n\tif (udp_tunnel == NULL)\n\t\treturn -EINVAL;\n\n\tswitch (udp_tunnel->prot_type) {\n\tcase RTE_TUNNEL_TYPE_VXLAN:\n\t\tret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);\n\t\tbreak;\n\tcase RTE_TUNNEL_TYPE_GENEVE:\n\tcase RTE_TUNNEL_TYPE_TEREDO:\n\t\tPMD_DRV_LOG(ERR, \"Tunnel type is not supported now.\");\n\t\tret = -1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Invalid tunnel type\");\n\t\tret = -1;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n/* Calculate the maximum number of contiguous PF queues that are configured */\nstatic int\ni40e_pf_calc_configured_queues_num(struct i40e_pf *pf)\n{\n\tstruct rte_eth_dev_data *data = pf->dev_data;\n\tint i, num;\n\tstruct i40e_rx_queue *rxq;\n\n\tnum = 0;\n\tfor (i = 0; i < pf->lan_nb_qps; i++) {\n\t\trxq = data->rx_queues[i];\n\t\tif (rxq && rxq->q_set)\n\t\t\tnum++;\n\t\telse\n\t\t\tbreak;\n\t}\n\n\treturn num;\n}\n\n/* Configure RSS */\nstatic int\ni40e_pf_config_rss(struct i40e_pf *pf)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tstruct rte_eth_rss_conf rss_conf;\n\tuint32_t i, lut = 0;\n\tuint16_t j, num;\n\n\t/*\n\t * If both VMDQ and RSS enabled, not all of PF queues are configured.\n\t * It's necessary to calulate the actual PF queues that are configured.\n\t */\n\tif (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {\n\t\tnum = i40e_pf_calc_configured_queues_num(pf);\n\t\tnum = i40e_align_floor(num);\n\t} else\n\t\tnum = i40e_align_floor(pf->dev_data->nb_rx_queues);\n\n\tPMD_INIT_LOG(INFO, \"Max of contiguous %u PF queues are configured\",\n\t\t\tnum);\n\n\tif (num == 0) {\n\t\tPMD_INIT_LOG(ERR, \"No PF queues are configured to enable RSS\");\n\t\treturn -ENOTSUP;\n\t}\n\n\tfor (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {\n\t\tif (j == num)\n\t\t\tj = 0;\n\t\tlut = (lut << 8) | (j & ((0x1 <<\n\t\t\thw->func_caps.rss_table_entry_width) - 1));\n\t\tif ((i & 3) == 3)\n\t\t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n\t}\n\n\trss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;\n\tif ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {\n\t\ti40e_pf_disable_rss(pf);\n\t\treturn 0;\n\t}\n\tif (rss_conf.rss_key == NULL || rss_conf.rss_key_len <\n\t\t(I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {\n\t\t/* Random default keys */\n\t\tstatic uint32_t rss_key_default[] = {0x6b793944,\n\t\t\t0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,\n\t\t\t0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,\n\t\t\t0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};\n\n\t\trss_conf.rss_key = (uint8_t *)rss_key_default;\n\t\trss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *\n\t\t\t\t\t\t\tsizeof(uint32_t);\n\t}\n\n\treturn i40e_hw_rss_hash_set(hw, &rss_conf);\n}\n\nstatic int\ni40e_tunnel_filter_param_check(struct i40e_pf *pf,\n\t\t\tstruct rte_eth_tunnel_filter_conf *filter)\n{\n\tif (pf == NULL || filter == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid parameter\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (filter->queue_id >= pf->dev_data->nb_rx_queues) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid queue ID\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (filter->inner_vlan > ETHER_MAX_VLAN_ID) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid inner VLAN ID\");\n\t\treturn -EINVAL;\n\t}\n\n\tif ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&\n\t\t(is_zero_ether_addr(filter->outer_mac))) {\n\t\tPMD_DRV_LOG(ERR, \"Cannot add NULL outer MAC address\");\n\t\treturn -EINVAL;\n\t}\n\n\tif ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&\n\t\t(is_zero_ether_addr(filter->inner_mac))) {\n\t\tPMD_DRV_LOG(ERR, \"Cannot add NULL inner MAC address\");\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,\n\t\t\tvoid *arg)\n{\n\tstruct rte_eth_tunnel_filter_conf *filter;\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tint ret = I40E_SUCCESS;\n\n\tfilter = (struct rte_eth_tunnel_filter_conf *)(arg);\n\n\tif (i40e_tunnel_filter_param_check(pf, filter) < 0)\n\t\treturn I40E_ERR_PARAM;\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_NOP:\n\t\tif (!(pf->flags & I40E_FLAG_VXLAN))\n\t\t\tret = I40E_NOT_SUPPORTED;\n\tcase RTE_ETH_FILTER_ADD:\n\t\tret = i40e_dev_tunnel_filter_set(pf, filter, 1);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_DELETE:\n\t\tret = i40e_dev_tunnel_filter_set(pf, filter, 0);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unknown operation %u\", filter_op);\n\t\tret = I40E_ERR_PARAM;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_config_mq_rx(struct i40e_pf *pf)\n{\n\tint ret = 0;\n\tenum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;\n\n\tif (mq_mode & ETH_MQ_RX_DCB_FLAG) {\n\t\tPMD_INIT_LOG(ERR, \"i40e doesn't support DCB yet\");\n\t\treturn -ENOTSUP;\n\t}\n\n\t/* RSS setup */\n\tif (mq_mode & ETH_MQ_RX_RSS_FLAG)\n\t\tret = i40e_pf_config_rss(pf);\n\telse\n\t\ti40e_pf_disable_rss(pf);\n\n\treturn ret;\n}\n\n/* Get the symmetric hash enable configurations per port */\nstatic void\ni40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)\n{\n\tuint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);\n\n\t*enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;\n}\n\n/* Set the symmetric hash enable configurations per port */\nstatic void\ni40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)\n{\n\tuint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);\n\n\tif (enable > 0) {\n\t\tif (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {\n\t\t\tPMD_DRV_LOG(INFO, \"Symmetric hash has already \"\n\t\t\t\t\t\t\t\"been enabled\");\n\t\t\treturn;\n\t\t}\n\t\treg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;\n\t} else {\n\t\tif (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {\n\t\t\tPMD_DRV_LOG(INFO, \"Symmetric hash has already \"\n\t\t\t\t\t\t\t\"been disabled\");\n\t\t\treturn;\n\t\t}\n\t\treg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;\n\t}\n\tI40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);\n\tI40E_WRITE_FLUSH(hw);\n}\n\n/*\n * Get global configurations of hash function type and symmetric hash enable\n * per flow type (pctype). Note that global configuration means it affects all\n * the ports on the same NIC.\n */\nstatic int\ni40e_get_hash_filter_global_config(struct i40e_hw *hw,\n\t\t\t\t struct rte_eth_hash_global_conf *g_cfg)\n{\n\tuint32_t reg, mask = I40E_FLOW_TYPES;\n\tuint16_t i;\n\tenum i40e_filter_pctype pctype;\n\n\tmemset(g_cfg, 0, sizeof(*g_cfg));\n\treg = I40E_READ_REG(hw, I40E_GLQF_CTL);\n\tif (reg & I40E_GLQF_CTL_HTOEP_MASK)\n\t\tg_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;\n\telse\n\t\tg_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;\n\tPMD_DRV_LOG(DEBUG, \"Hash function is %s\",\n\t\t(reg & I40E_GLQF_CTL_HTOEP_MASK) ? \"Toeplitz\" : \"Simple XOR\");\n\n\tfor (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {\n\t\tif (!(mask & (1UL << i)))\n\t\t\tcontinue;\n\t\tmask &= ~(1UL << i);\n\t\t/* Bit set indicats the coresponding flow type is supported */\n\t\tg_cfg->valid_bit_mask[0] |= (1UL << i);\n\t\tpctype = i40e_flowtype_to_pctype(i);\n\t\treg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));\n\t\tif (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)\n\t\t\tg_cfg->sym_hash_enable_mask[0] |= (1UL << i);\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)\n{\n\tuint32_t i;\n\tuint32_t mask0, i40e_mask = I40E_FLOW_TYPES;\n\n\tif (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&\n\t\tg_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&\n\t\tg_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {\n\t\tPMD_DRV_LOG(ERR, \"Unsupported hash function type %d\",\n\t\t\t\t\t\tg_cfg->hash_func);\n\t\treturn -EINVAL;\n\t}\n\n\t/*\n\t * As i40e supports less than 32 flow types, only first 32 bits need to\n\t * be checked.\n\t */\n\tmask0 = g_cfg->valid_bit_mask[0];\n\tfor (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {\n\t\tif (i == 0) {\n\t\t\t/* Check if any unsupported flow type configured */\n\t\t\tif ((mask0 | i40e_mask) ^ i40e_mask)\n\t\t\t\tgoto mask_err;\n\t\t} else {\n\t\t\tif (g_cfg->valid_bit_mask[i])\n\t\t\t\tgoto mask_err;\n\t\t}\n\t}\n\n\treturn 0;\n\nmask_err:\n\tPMD_DRV_LOG(ERR, \"i40e unsupported flow type bit(s) configured\");\n\n\treturn -EINVAL;\n}\n\n/*\n * Set global configurations of hash function type and symmetric hash enable\n * per flow type (pctype). Note any modifying global configuration will affect\n * all the ports on the same NIC.\n */\nstatic int\ni40e_set_hash_filter_global_config(struct i40e_hw *hw,\n\t\t\t\t struct rte_eth_hash_global_conf *g_cfg)\n{\n\tint ret;\n\tuint16_t i;\n\tuint32_t reg;\n\tuint32_t mask0 = g_cfg->valid_bit_mask[0];\n\tenum i40e_filter_pctype pctype;\n\n\t/* Check the input parameters */\n\tret = i40e_hash_global_config_check(g_cfg);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tfor (i = 0; mask0 && i < UINT32_BIT; i++) {\n\t\tif (!(mask0 & (1UL << i)))\n\t\t\tcontinue;\n\t\tmask0 &= ~(1UL << i);\n\t\tpctype = i40e_flowtype_to_pctype(i);\n\t\treg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?\n\t\t\t\tI40E_GLQF_HSYM_SYMH_ENA_MASK : 0;\n\t\tI40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);\n\t}\n\n\treg = I40E_READ_REG(hw, I40E_GLQF_CTL);\n\tif (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {\n\t\t/* Toeplitz */\n\t\tif (reg & I40E_GLQF_CTL_HTOEP_MASK) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Hash function already set to \"\n\t\t\t\t\t\t\t\t\"Toeplitz\");\n\t\t\tgoto out;\n\t\t}\n\t\treg |= I40E_GLQF_CTL_HTOEP_MASK;\n\t} else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {\n\t\t/* Simple XOR */\n\t\tif (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {\n\t\t\tPMD_DRV_LOG(DEBUG, \"Hash function already set to \"\n\t\t\t\t\t\t\t\"Simple XOR\");\n\t\t\tgoto out;\n\t\t}\n\t\treg &= ~I40E_GLQF_CTL_HTOEP_MASK;\n\t} else\n\t\t/* Use the default, and keep it as it is */\n\t\tgoto out;\n\n\tI40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);\n\nout:\n\tI40E_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\nstatic int\ni40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)\n{\n\tint ret = 0;\n\n\tif (!hw || !info) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\");\n\t\treturn -EFAULT;\n\t}\n\n\tswitch (info->info_type) {\n\tcase RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:\n\t\ti40e_get_symmetric_hash_enable_per_port(hw,\n\t\t\t\t\t&(info->info.enable));\n\t\tbreak;\n\tcase RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:\n\t\tret = i40e_get_hash_filter_global_config(hw,\n\t\t\t\t&(info->info.global_conf));\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Hash filter info type (%d) not supported\",\n\t\t\t\t\t\t\tinfo->info_type);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int\ni40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)\n{\n\tint ret = 0;\n\n\tif (!hw || !info) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid pointer\");\n\t\treturn -EFAULT;\n\t}\n\n\tswitch (info->info_type) {\n\tcase RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:\n\t\ti40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);\n\t\tbreak;\n\tcase RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:\n\t\tret = i40e_set_hash_filter_global_config(hw,\n\t\t\t\t&(info->info.global_conf));\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Hash filter info type (%d) not supported\",\n\t\t\t\t\t\t\tinfo->info_type);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n/* Operations for hash function */\nstatic int\ni40e_hash_filter_ctrl(struct rte_eth_dev *dev,\n\t\t enum rte_filter_op filter_op,\n\t\t void *arg)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint ret = 0;\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_NOP:\n\t\tbreak;\n\tcase RTE_ETH_FILTER_GET:\n\t\tret = i40e_hash_filter_get(hw,\n\t\t\t(struct rte_eth_hash_filter_info *)arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_SET:\n\t\tret = i40e_hash_filter_set(hw,\n\t\t\t(struct rte_eth_hash_filter_info *)arg);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(WARNING, \"Filter operation (%d) not supported\",\n\t\t\t\t\t\t\t\tfilter_op);\n\t\tret = -ENOTSUP;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n/*\n * Configure ethertype filter, which can director packet by filtering\n * with mac address and ether_type or only ether_type\n */\nstatic int\ni40e_ethertype_filter_set(struct i40e_pf *pf,\n\t\t\tstruct rte_eth_ethertype_filter *filter,\n\t\t\tbool add)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tstruct i40e_control_filter_stats stats;\n\tuint16_t flags = 0;\n\tint ret;\n\n\tif (filter->queue >= pf->dev_data->nb_rx_queues) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid queue ID\");\n\t\treturn -EINVAL;\n\t}\n\tif (filter->ether_type == ETHER_TYPE_IPv4 ||\n\t\tfilter->ether_type == ETHER_TYPE_IPv6) {\n\t\tPMD_DRV_LOG(ERR, \"unsupported ether_type(0x%04x) in\"\n\t\t\t\" control packet filter.\", filter->ether_type);\n\t\treturn -EINVAL;\n\t}\n\tif (filter->ether_type == ETHER_TYPE_VLAN)\n\t\tPMD_DRV_LOG(WARNING, \"filter vlan ether_type in first tag is\"\n\t\t\t\" not supported.\");\n\n\tif (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))\n\t\tflags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;\n\tif (filter->flags & RTE_ETHTYPE_FLAGS_DROP)\n\t\tflags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;\n\tflags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;\n\n\tmemset(&stats, 0, sizeof(stats));\n\tret = i40e_aq_add_rem_control_packet_filter(hw,\n\t\t\tfilter->mac_addr.addr_bytes,\n\t\t\tfilter->ether_type, flags,\n\t\t\tpf->main_vsi->seid,\n\t\t\tfilter->queue, add, &stats, NULL);\n\n\tPMD_DRV_LOG(INFO, \"add/rem control packet filter, return %d,\"\n\t\t\t \" mac_etype_used = %u, etype_used = %u,\"\n\t\t\t \" mac_etype_free = %u, etype_free = %u\\n\",\n\t\t\t ret, stats.mac_etype_used, stats.etype_used,\n\t\t\t stats.mac_etype_free, stats.etype_free);\n\tif (ret < 0)\n\t\treturn -ENOSYS;\n\treturn 0;\n}\n\n/*\n * Handle operations for ethertype filter.\n */\nstatic int\ni40e_ethertype_filter_handle(struct rte_eth_dev *dev,\n\t\t\t\tenum rte_filter_op filter_op,\n\t\t\t\tvoid *arg)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tint ret = 0;\n\n\tif (filter_op == RTE_ETH_FILTER_NOP)\n\t\treturn ret;\n\n\tif (arg == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"arg shouldn't be NULL for operation %u\",\n\t\t\t filter_op);\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_ADD:\n\t\tret = i40e_ethertype_filter_set(pf,\n\t\t\t(struct rte_eth_ethertype_filter *)arg,\n\t\t\tTRUE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_DELETE:\n\t\tret = i40e_ethertype_filter_set(pf,\n\t\t\t(struct rte_eth_ethertype_filter *)arg,\n\t\t\tFALSE);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unsupported operation %u\\n\", filter_op);\n\t\tret = -ENOSYS;\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\nstatic int\ni40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n\t\t enum rte_filter_type filter_type,\n\t\t enum rte_filter_op filter_op,\n\t\t void *arg)\n{\n\tint ret = 0;\n\n\tif (dev == NULL)\n\t\treturn -EINVAL;\n\n\tswitch (filter_type) {\n\tcase RTE_ETH_FILTER_HASH:\n\t\tret = i40e_hash_filter_ctrl(dev, filter_op, arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_MACVLAN:\n\t\tret = i40e_mac_filter_handle(dev, filter_op, arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_ETHERTYPE:\n\t\tret = i40e_ethertype_filter_handle(dev, filter_op, arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_TUNNEL:\n\t\tret = i40e_tunnel_filter_handle(dev, filter_op, arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_FDIR:\n\t\tret = i40e_fdir_ctrl_func(dev, filter_op, arg);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(WARNING, \"Filter type (%d) not supported\",\n\t\t\t\t\t\t\tfilter_type);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n/*\n * As some registers wouldn't be reset unless a global hardware reset,\n * hardware initialization is needed to put those registers into an\n * expected initial state.\n */\nstatic void\ni40e_hw_init(struct i40e_hw *hw)\n{\n\t/* clear the PF Queue Filter control register */\n\tI40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);\n\n\t/* Disable symmetric hash per port */\n\ti40e_set_symmetric_hash_enable_per_port(hw, 0);\n}\n\nenum i40e_filter_pctype\ni40e_flowtype_to_pctype(uint16_t flow_type)\n{\n\tstatic const enum i40e_filter_pctype pctype_table[] = {\n\t\t[RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =\n\t\t\tI40E_FILTER_PCTYPE_NONF_IPV4_UDP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =\n\t\t\tI40E_FILTER_PCTYPE_NONF_IPV4_TCP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =\n\t\t\tI40E_FILTER_PCTYPE_NONF_IPV4_SCTP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =\n\t\t\tI40E_FILTER_PCTYPE_NONF_IPV4_OTHER,\n\t\t[RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =\n\t\t\tI40E_FILTER_PCTYPE_NONF_IPV6_UDP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =\n\t\t\tI40E_FILTER_PCTYPE_NONF_IPV6_TCP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =\n\t\t\tI40E_FILTER_PCTYPE_NONF_IPV6_SCTP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =\n\t\t\tI40E_FILTER_PCTYPE_NONF_IPV6_OTHER,\n\t\t[RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,\n\t};\n\n\treturn pctype_table[flow_type];\n}\n\nuint16_t\ni40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)\n{\n\tstatic const uint16_t flowtype_table[] = {\n\t\t[I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,\n\t\t[I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =\n\t\t\tRTE_ETH_FLOW_NONFRAG_IPV4_UDP,\n\t\t[I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =\n\t\t\tRTE_ETH_FLOW_NONFRAG_IPV4_TCP,\n\t\t[I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =\n\t\t\tRTE_ETH_FLOW_NONFRAG_IPV4_SCTP,\n\t\t[I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =\n\t\t\tRTE_ETH_FLOW_NONFRAG_IPV4_OTHER,\n\t\t[I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,\n\t\t[I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =\n\t\t\tRTE_ETH_FLOW_NONFRAG_IPV6_UDP,\n\t\t[I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =\n\t\t\tRTE_ETH_FLOW_NONFRAG_IPV6_TCP,\n\t\t[I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =\n\t\t\tRTE_ETH_FLOW_NONFRAG_IPV6_SCTP,\n\t\t[I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =\n\t\t\tRTE_ETH_FLOW_NONFRAG_IPV6_OTHER,\n\t\t[I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,\n\t};\n\n\treturn flowtype_table[pctype];\n}\n\n/*\n * On X710, performance number is far from the expectation on recent firmware\n * versions; on XL710, performance number is also far from the expectation on\n * recent firmware versions, if promiscuous mode is disabled, or promiscuous\n * mode is enabled and port MAC address is equal to the packet destination MAC\n * address. The fix for this issue may not be integrated in the following\n * firmware version. So the workaround in software driver is needed. It needs\n * to modify the initial values of 3 internal only registers for both X710 and\n * XL710. Note that the values for X710 or XL710 could be different, and the\n * workaround can be removed when it is fixed in firmware in the future.\n */\n\n/* For both X710 and XL710 */\n#define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200\n#define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00\n\n#define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200\n#define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08\n\n/* For X710 */\n#define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303\n/* For XL710 */\n#define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606\n#define I40E_GL_SWR_PM_UP_THR 0x269FBC\n\nstatic void\ni40e_configure_registers(struct i40e_hw *hw)\n{\n\tstatic struct {\n\t\tuint32_t addr;\n\t\tuint64_t val;\n\t} reg_table[] = {\n\t\t{I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},\n\t\t{I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},\n\t\t{I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */\n\t};\n\tuint64_t reg;\n\tuint32_t i;\n\tint ret;\n\n\tfor (i = 0; i < RTE_DIM(reg_table); i++) {\n\t\tif (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {\n\t\t\tif (i40e_is_40G_device(hw->device_id)) /* For XL710 */\n\t\t\t\treg_table[i].val =\n\t\t\t\t\tI40E_GL_SWR_PM_UP_THR_SF_VALUE;\n\t\t\telse /* For X710 */\n\t\t\t\treg_table[i].val =\n\t\t\t\t\tI40E_GL_SWR_PM_UP_THR_EF_VALUE;\n\t\t}\n\n\t\tret = i40e_aq_debug_read_register(hw, reg_table[i].addr,\n\t\t\t\t\t\t\t®, NULL);\n\t\tif (ret < 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to read from 0x%\"PRIx32,\n\t\t\t\t\t\t\treg_table[i].addr);\n\t\t\tbreak;\n\t\t}\n\t\tPMD_DRV_LOG(DEBUG, \"Read from 0x%\"PRIx32\": 0x%\"PRIx64,\n\t\t\t\t\t\treg_table[i].addr, reg);\n\t\tif (reg == reg_table[i].val)\n\t\t\tcontinue;\n\n\t\tret = i40e_aq_debug_write_register(hw, reg_table[i].addr,\n\t\t\t\t\t\treg_table[i].val, NULL);\n\t\tif (ret < 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to write 0x%\"PRIx64\" to the \"\n\t\t\t\t\"address of 0x%\"PRIx32, reg_table[i].val,\n\t\t\t\t\t\t\treg_table[i].addr);\n\t\t\tbreak;\n\t\t}\n\t\tPMD_DRV_LOG(DEBUG, \"Write 0x%\"PRIx64\" to the address of \"\n\t\t\t\"0x%\"PRIx32, reg_table[i].val, reg_table[i].addr);\n\t}\n}\n\n#define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))\n#define I40E_VSI_TSR_QINQ_CONFIG 0xc030\n#define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))\n#define I40E_VSI_L2TAGSTXVALID_QINQ 0xab\nstatic int\ni40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)\n{\n\tuint32_t reg;\n\tint ret;\n\n\tif (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {\n\t\tPMD_DRV_LOG(ERR, \"VSI ID exceeds the maximum\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* Configure for double VLAN RX stripping */\n\treg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));\n\tif ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {\n\t\treg |= I40E_VSI_TSR_QINQ_CONFIG;\n\t\tret = i40e_aq_debug_write_register(hw,\n\t\t\t\t\t\t I40E_VSI_TSR(vsi->vsi_id),\n\t\t\t\t\t\t reg, NULL);\n\t\tif (ret < 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to update VSI_TSR[%d]\",\n\t\t\t\t vsi->vsi_id);\n\t\t\treturn I40E_ERR_CONFIG;\n\t\t}\n\t}\n\n\t/* Configure for double VLAN TX insertion */\n\treg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));\n\tif ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {\n\t\treg = I40E_VSI_L2TAGSTXVALID_QINQ;\n\t\tret = i40e_aq_debug_write_register(hw,\n\t\t\t\t\t\t I40E_VSI_L2TAGSTXVALID(\n\t\t\t\t\t\t vsi->vsi_id), reg, NULL);\n\t\tif (ret < 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to update \"\n\t\t\t\t\"VSI_L2TAGSTXVALID[%d]\", vsi->vsi_id);\n\t\t\treturn I40E_ERR_CONFIG;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/**\n * i40e_aq_add_mirror_rule\n * @hw: pointer to the hardware structure\n * @seid: VEB seid to add mirror rule to\n * @dst_id: destination vsi seid\n * @entries: Buffer which contains the entities to be mirrored\n * @count: number of entities contained in the buffer\n * @rule_id:the rule_id of the rule to be added\n *\n * Add a mirror rule for a given veb.\n *\n **/\nstatic enum i40e_status_code\ni40e_aq_add_mirror_rule(struct i40e_hw *hw,\n\t\t\tuint16_t seid, uint16_t dst_id,\n\t\t\tuint16_t rule_type, uint16_t *entries,\n\t\t\tuint16_t count, uint16_t *rule_id)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_delete_mirror_rule cmd;\n\tstruct i40e_aqc_add_delete_mirror_rule_completion *resp =\n\t\t(struct i40e_aqc_add_delete_mirror_rule_completion *)\n\t\t&desc.params.raw;\n\tuint16_t buff_len;\n\tenum i40e_status_code status;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_add_mirror_rule);\n\tmemset(&cmd, 0, sizeof(cmd));\n\n\tbuff_len = sizeof(uint16_t) * count;\n\tdesc.datalen = rte_cpu_to_le_16(buff_len);\n\tif (buff_len > 0)\n\t\tdesc.flags |= rte_cpu_to_le_16(\n\t\t\t(uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));\n\tcmd.rule_type = rte_cpu_to_le_16(rule_type <<\n\t\t\t\tI40E_AQC_MIRROR_RULE_TYPE_SHIFT);\n\tcmd.num_entries = rte_cpu_to_le_16(count);\n\tcmd.seid = rte_cpu_to_le_16(seid);\n\tcmd.destination = rte_cpu_to_le_16(dst_id);\n\n\trte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));\n\tstatus = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);\n\tPMD_DRV_LOG(INFO, \"i40e_aq_add_mirror_rule, aq_status %d,\"\n\t\t\t \"rule_id = %u\"\n\t\t\t \" mirror_rules_used = %u, mirror_rules_free = %u,\",\n\t\t\t hw->aq.asq_last_status, resp->rule_id,\n\t\t\t resp->mirror_rules_used, resp->mirror_rules_free);\n\t*rule_id = rte_le_to_cpu_16(resp->rule_id);\n\n\treturn status;\n}\n\n/**\n * i40e_aq_del_mirror_rule\n * @hw: pointer to the hardware structure\n * @seid: VEB seid to add mirror rule to\n * @entries: Buffer which contains the entities to be mirrored\n * @count: number of entities contained in the buffer\n * @rule_id:the rule_id of the rule to be delete\n *\n * Delete a mirror rule for a given veb.\n *\n **/\nstatic enum i40e_status_code\ni40e_aq_del_mirror_rule(struct i40e_hw *hw,\n\t\tuint16_t seid, uint16_t rule_type, uint16_t *entries,\n\t\tuint16_t count, uint16_t rule_id)\n{\n\tstruct i40e_aq_desc desc;\n\tstruct i40e_aqc_add_delete_mirror_rule cmd;\n\tuint16_t buff_len = 0;\n\tenum i40e_status_code status;\n\tvoid *buff = NULL;\n\n\ti40e_fill_default_direct_cmd_desc(&desc,\n\t\t\t\t\t i40e_aqc_opc_delete_mirror_rule);\n\tmemset(&cmd, 0, sizeof(cmd));\n\tif (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {\n\t\tdesc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |\n\t\t\t\t\t\t\t I40E_AQ_FLAG_RD));\n\t\tcmd.num_entries = count;\n\t\tbuff_len = sizeof(uint16_t) * count;\n\t\tdesc.datalen = rte_cpu_to_le_16(buff_len);\n\t\tbuff = (void *)entries;\n\t} else\n\t\t/* rule id is filled in destination field for deleting mirror rule */\n\t\tcmd.destination = rte_cpu_to_le_16(rule_id);\n\n\tcmd.rule_type = rte_cpu_to_le_16(rule_type <<\n\t\t\t\tI40E_AQC_MIRROR_RULE_TYPE_SHIFT);\n\tcmd.seid = rte_cpu_to_le_16(seid);\n\n\trte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));\n\tstatus = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);\n\n\treturn status;\n}\n\n/**\n * i40e_mirror_rule_set\n * @dev: pointer to the hardware structure\n * @mirror_conf: mirror rule info\n * @sw_id: mirror rule's sw_id\n * @on: enable/disable\n *\n * set a mirror rule.\n *\n **/\nstatic int\ni40e_mirror_rule_set(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_mirror_conf *mirror_conf,\n\t\t\tuint8_t sw_id, uint8_t on)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_mirror_rule *it, *mirr_rule = NULL;\n\tstruct i40e_mirror_rule *parent = NULL;\n\tuint16_t seid, dst_seid, rule_id;\n\tuint16_t i, j = 0;\n\tint ret;\n\n\tPMD_DRV_LOG(DEBUG, \"i40e_mirror_rule_set: sw_id = %d.\", sw_id);\n\n\tif (pf->main_vsi->veb == NULL || pf->vfs == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"mirror rule can not be configured\"\n\t\t\t\" without veb or vfs.\");\n\t\treturn -ENOSYS;\n\t}\n\tif (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {\n\t\tPMD_DRV_LOG(ERR, \"mirror table is full.\");\n\t\treturn -ENOSPC;\n\t}\n\tif (mirror_conf->dst_pool > pf->vf_num) {\n\t\tPMD_DRV_LOG(ERR, \"invalid destination pool %u.\",\n\t\t\t\t mirror_conf->dst_pool);\n\t\treturn -EINVAL;\n\t}\n\n\tseid = pf->main_vsi->veb->seid;\n\n\tTAILQ_FOREACH(it, &pf->mirror_list, rules) {\n\t\tif (sw_id <= it->index) {\n\t\t\tmirr_rule = it;\n\t\t\tbreak;\n\t\t}\n\t\tparent = it;\n\t}\n\tif (mirr_rule && sw_id == mirr_rule->index) {\n\t\tif (on) {\n\t\t\tPMD_DRV_LOG(ERR, \"mirror rule exists.\");\n\t\t\treturn -EEXIST;\n\t\t} else {\n\t\t\tret = i40e_aq_del_mirror_rule(hw, seid,\n\t\t\t\t\tmirr_rule->rule_type,\n\t\t\t\t\tmirr_rule->entries,\n\t\t\t\t\tmirr_rule->num_entries, mirr_rule->id);\n\t\t\tif (ret < 0) {\n\t\t\t\tPMD_DRV_LOG(ERR, \"failed to remove mirror rule:\"\n\t\t\t\t\t\t \" ret = %d, aq_err = %d.\",\n\t\t\t\t\t\t ret, hw->aq.asq_last_status);\n\t\t\t\treturn -ENOSYS;\n\t\t\t}\n\t\t\tTAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);\n\t\t\trte_free(mirr_rule);\n\t\t\tpf->nb_mirror_rule--;\n\t\t\treturn 0;\n\t\t}\n\t} else if (!on) {\n\t\tPMD_DRV_LOG(ERR, \"mirror rule doesn't exist.\");\n\t\treturn -ENOENT;\n\t}\n\n\tmirr_rule = rte_zmalloc(\"i40e_mirror_rule\",\n\t\t\t\tsizeof(struct i40e_mirror_rule) , 0);\n\tif (!mirr_rule) {\n\t\tPMD_DRV_LOG(ERR, \"failed to allocate memory\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\tswitch (mirror_conf->rule_type) {\n\tcase ETH_MIRROR_VLAN:\n\t\tfor (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {\n\t\t\tif (mirror_conf->vlan.vlan_mask & (1ULL << i)) {\n\t\t\t\tmirr_rule->entries[j] =\n\t\t\t\t\tmirror_conf->vlan.vlan_id[i];\n\t\t\t\tj++;\n\t\t\t}\n\t\t}\n\t\tif (j == 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"vlan is not specified.\");\n\t\t\trte_free(mirr_rule);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tmirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;\n\t\tbreak;\n\tcase ETH_MIRROR_VIRTUAL_POOL_UP:\n\tcase ETH_MIRROR_VIRTUAL_POOL_DOWN:\n\t\t/* check if the specified pool bit is out of range */\n\t\tif (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {\n\t\t\tPMD_DRV_LOG(ERR, \"pool mask is out of range.\");\n\t\t\trte_free(mirr_rule);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tfor (i = 0, j = 0; i < pf->vf_num; i++) {\n\t\t\tif (mirror_conf->pool_mask & (1ULL << i)) {\n\t\t\t\tmirr_rule->entries[j] = pf->vfs[i].vsi->seid;\n\t\t\t\tj++;\n\t\t\t}\n\t\t}\n\t\tif (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {\n\t\t\t/* add pf vsi to entries */\n\t\t\tmirr_rule->entries[j] = pf->main_vsi_seid;\n\t\t\tj++;\n\t\t}\n\t\tif (j == 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"pool is not specified.\");\n\t\t\trte_free(mirr_rule);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\t/* egress and ingress in aq commands means from switch but not port */\n\t\tmirr_rule->rule_type =\n\t\t\t(mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?\n\t\t\tI40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :\n\t\t\tI40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;\n\t\tbreak;\n\tcase ETH_MIRROR_UPLINK_PORT:\n\t\t/* egress and ingress in aq commands means from switch but not port*/\n\t\tmirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;\n\t\tbreak;\n\tcase ETH_MIRROR_DOWNLINK_PORT:\n\t\tmirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unsupported mirror type %d.\",\n\t\t\tmirror_conf->rule_type);\n\t\trte_free(mirr_rule);\n\t\treturn -EINVAL;\n\t}\n\n\t/* If the dst_pool is equal to vf_num, consider it as PF */\n\tif (mirror_conf->dst_pool == pf->vf_num)\n\t\tdst_seid = pf->main_vsi_seid;\n\telse\n\t\tdst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;\n\n\tret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,\n\t\t\t\t mirr_rule->rule_type, mirr_rule->entries,\n\t\t\t\t j, &rule_id);\n\tif (ret < 0) {\n\t\tPMD_DRV_LOG(ERR, \"failed to add mirror rule:\"\n\t\t\t\t \" ret = %d, aq_err = %d.\",\n\t\t\t\t ret, hw->aq.asq_last_status);\n\t\trte_free(mirr_rule);\n\t\treturn -ENOSYS;\n\t}\n\n\tmirr_rule->index = sw_id;\n\tmirr_rule->num_entries = j;\n\tmirr_rule->id = rule_id;\n\tmirr_rule->dst_vsi_seid = dst_seid;\n\n\tif (parent)\n\t\tTAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);\n\telse\n\t\tTAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);\n\n\tpf->nb_mirror_rule++;\n\treturn 0;\n}\n\n/**\n * i40e_mirror_rule_reset\n * @dev: pointer to the device\n * @sw_id: mirror rule's sw_id\n *\n * reset a mirror rule.\n *\n **/\nstatic int\ni40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_mirror_rule *it, *mirr_rule = NULL;\n\tuint16_t seid;\n\tint ret;\n\n\tPMD_DRV_LOG(DEBUG, \"i40e_mirror_rule_reset: sw_id = %d.\", sw_id);\n\n\tseid = pf->main_vsi->veb->seid;\n\n\tTAILQ_FOREACH(it, &pf->mirror_list, rules) {\n\t\tif (sw_id == it->index) {\n\t\t\tmirr_rule = it;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (mirr_rule) {\n\t\tret = i40e_aq_del_mirror_rule(hw, seid,\n\t\t\t\tmirr_rule->rule_type,\n\t\t\t\tmirr_rule->entries,\n\t\t\t\tmirr_rule->num_entries, mirr_rule->id);\n\t\tif (ret < 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"failed to remove mirror rule:\"\n\t\t\t\t\t \" status = %d, aq_err = %d.\",\n\t\t\t\t\t ret, hw->aq.asq_last_status);\n\t\t\treturn -ENOSYS;\n\t\t}\n\t\tTAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);\n\t\trte_free(mirr_rule);\n\t\tpf->nb_mirror_rule--;\n\t} else {\n\t\tPMD_DRV_LOG(ERR, \"mirror rule doesn't exist.\");\n\t\treturn -ENOENT;\n\t}\n\treturn 0;\n}\n\nstatic int\ni40e_timesync_enable(struct rte_eth_dev *dev)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct rte_eth_link *link = &dev->data->dev_link;\n\tuint32_t tsync_ctl_l;\n\tuint32_t tsync_ctl_h;\n\tuint32_t tsync_inc_l;\n\tuint32_t tsync_inc_h;\n\n\tswitch (link->link_speed) {\n\tcase ETH_LINK_SPEED_40G:\n\t\ttsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;\n\t\ttsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_10G:\n\t\ttsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;\n\t\ttsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_1000:\n\t\ttsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;\n\t\ttsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;\n\t\tbreak;\n\tdefault:\n\t\ttsync_inc_l = 0x0;\n\t\ttsync_inc_h = 0x0;\n\t}\n\n\t/* Clear timesync registers. */\n\tI40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);\n\tI40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);\n\tI40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));\n\tI40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));\n\tI40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));\n\tI40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));\n\tI40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);\n\n\t/* Set the timesync increment value. */\n\tI40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);\n\tI40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);\n\n\t/* Enable timestamping of PTP packets. */\n\ttsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);\n\ttsync_ctl_l |= I40E_PRTTSYN_TSYNENA;\n\n\ttsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);\n\ttsync_ctl_h |= I40E_PRTTSYN_TSYNENA;\n\ttsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;\n\n\tI40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);\n\tI40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);\n\n\treturn 0;\n}\n\nstatic int\ni40e_timesync_disable(struct rte_eth_dev *dev)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t tsync_ctl_l;\n\tuint32_t tsync_ctl_h;\n\n\t/* Disable timestamping of transmitted PTP packets. */\n\ttsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);\n\ttsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;\n\n\ttsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);\n\ttsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;\n\n\tI40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);\n\tI40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);\n\n\t/* Set the timesync increment value. */\n\tI40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);\n\tI40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);\n\n\treturn 0;\n}\n\nstatic int\ni40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n\t\t\t\tstruct timespec *timestamp, uint32_t flags)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t sync_status;\n\tuint32_t rx_stmpl;\n\tuint32_t rx_stmph;\n\tuint32_t index = flags & 0x03;\n\n\tsync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);\n\tif ((sync_status & (1 << index)) == 0)\n\t\treturn -EINVAL;\n\n\trx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));\n\trx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));\n\n\ttimestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);\n\ttimestamp->tv_nsec = 0;\n\n\treturn 0;\n}\n\nstatic int\ni40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n\t\t\t\tstruct timespec *timestamp)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t sync_status;\n\tuint32_t tx_stmpl;\n\tuint32_t tx_stmph;\n\n\tsync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);\n\tif ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)\n\t\treturn -EINVAL;\n\n\ttx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);\n\ttx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);\n\n\ttimestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);\n\ttimestamp->tv_nsec = 0;\n\n\treturn 0;\n}\n" }, { "path": "drivers/net/i40e/i40e_ethdev.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _I40E_ETHDEV_H_\n#define _I40E_ETHDEV_H_\n\n#include \n\n#define I40E_VLAN_TAG_SIZE 4\n\n#define I40E_AQ_LEN 32\n#define I40E_AQ_BUF_SZ 4096\n/* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */\n#define I40E_MAX_Q_PER_TC 64\n#define I40E_NUM_DESC_DEFAULT 512\n#define I40E_NUM_DESC_ALIGN 32\n#define I40E_BUF_SIZE_MIN 1024\n#define I40E_FRAME_SIZE_MAX 9728\n#define I40E_QUEUE_BASE_ADDR_UNIT 128\n/* number of VSIs and queue default setting */\n#define I40E_MAX_QP_NUM_PER_VF 16\n#define I40E_DEFAULT_QP_NUM_FDIR 1\n#define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))\n#define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)\n/*\n * vlan_id is a 12 bit number.\n * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.\n * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.\n * The higher 7 bit val specifies VFTA array index.\n */\n#define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))\n#define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)\n\n/* Default TC traffic in case DCB is not enabled */\n#define I40E_DEFAULT_TCMAP 0x1\n#define I40E_FDIR_QUEUE_ID 0\n\n/* Always assign pool 0 to main VSI, VMDQ will start from 1 */\n#define I40E_VMDQ_POOL_BASE 1\n\n#define I40E_DEFAULT_RX_FREE_THRESH 32\n#define I40E_DEFAULT_RX_PTHRESH 8\n#define I40E_DEFAULT_RX_HTHRESH 8\n#define I40E_DEFAULT_RX_WTHRESH 0\n\n#define I40E_DEFAULT_TX_FREE_THRESH 32\n#define I40E_DEFAULT_TX_PTHRESH 32\n#define I40E_DEFAULT_TX_HTHRESH 0\n#define I40E_DEFAULT_TX_WTHRESH 0\n#define I40E_DEFAULT_TX_RSBIT_THRESH 32\n\n/* Bit shift and mask */\n#define I40E_4_BIT_WIDTH (CHAR_BIT / 2)\n#define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)\n#define I40E_8_BIT_WIDTH CHAR_BIT\n#define I40E_8_BIT_MASK UINT8_MAX\n#define I40E_16_BIT_WIDTH (CHAR_BIT * 2)\n#define I40E_16_BIT_MASK UINT16_MAX\n#define I40E_32_BIT_WIDTH (CHAR_BIT * 4)\n#define I40E_32_BIT_MASK UINT32_MAX\n#define I40E_48_BIT_WIDTH (CHAR_BIT * 6)\n#define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)\n\n/* index flex payload per layer */\nenum i40e_flxpld_layer_idx {\n\tI40E_FLXPLD_L2_IDX = 0,\n\tI40E_FLXPLD_L3_IDX = 1,\n\tI40E_FLXPLD_L4_IDX = 2,\n\tI40E_MAX_FLXPLD_LAYER = 3,\n};\n#define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */\n#define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */\n#define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */\n#define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */\n\n/* i40e flags */\n#define I40E_FLAG_RSS (1ULL << 0)\n#define I40E_FLAG_DCB (1ULL << 1)\n#define I40E_FLAG_VMDQ (1ULL << 2)\n#define I40E_FLAG_SRIOV (1ULL << 3)\n#define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)\n#define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)\n#define I40E_FLAG_FDIR (1ULL << 6)\n#define I40E_FLAG_VXLAN (1ULL << 7)\n#define I40E_FLAG_ALL (I40E_FLAG_RSS | \\\n\t\t I40E_FLAG_DCB | \\\n\t\t I40E_FLAG_VMDQ | \\\n\t\t I40E_FLAG_SRIOV | \\\n\t\t I40E_FLAG_HEADER_SPLIT_DISABLED | \\\n\t\t I40E_FLAG_HEADER_SPLIT_ENABLED | \\\n\t\t I40E_FLAG_FDIR | \\\n\t\t I40E_FLAG_VXLAN)\n\n#define I40E_RSS_OFFLOAD_ALL ( \\\n\tETH_RSS_FRAG_IPV4 | \\\n\tETH_RSS_NONFRAG_IPV4_TCP | \\\n\tETH_RSS_NONFRAG_IPV4_UDP | \\\n\tETH_RSS_NONFRAG_IPV4_SCTP | \\\n\tETH_RSS_NONFRAG_IPV4_OTHER | \\\n\tETH_RSS_FRAG_IPV6 | \\\n\tETH_RSS_NONFRAG_IPV6_TCP | \\\n\tETH_RSS_NONFRAG_IPV6_UDP | \\\n\tETH_RSS_NONFRAG_IPV6_SCTP | \\\n\tETH_RSS_NONFRAG_IPV6_OTHER | \\\n\tETH_RSS_L2_PAYLOAD)\n\n/* All bits of RSS hash enable */\n#define I40E_RSS_HENA_ALL ( \\\n\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \\\n\t(1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))\n\nstruct i40e_adapter;\n\n/**\n * MAC filter structure\n */\nstruct i40e_mac_filter_info {\n\tenum rte_mac_filter_type filter_type;\n\tstruct ether_addr mac_addr;\n};\n\nTAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);\n\n/* MAC filter list structure */\nstruct i40e_mac_filter {\n\tTAILQ_ENTRY(i40e_mac_filter) next;\n\tstruct i40e_mac_filter_info mac_info;\n};\n\nTAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);\n\nstruct i40e_vsi;\n\n/* VSI list structure */\nstruct i40e_vsi_list {\n\tTAILQ_ENTRY(i40e_vsi_list) list;\n\tstruct i40e_vsi *vsi;\n};\n\nstruct i40e_rx_queue;\nstruct i40e_tx_queue;\n\n/* Structure that defines a VEB */\nstruct i40e_veb {\n\tstruct i40e_vsi_list_head head;\n\tstruct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */\n\tuint16_t seid; /* The seid of VEB itself */\n\tuint16_t uplink_seid; /* The uplink seid of this VEB */\n\tuint16_t stats_idx;\n\tstruct i40e_eth_stats stats;\n};\n\n/* i40e MACVLAN filter structure */\nstruct i40e_macvlan_filter {\n\tstruct ether_addr macaddr;\n\tenum rte_mac_filter_type filter_type;\n\tuint16_t vlan_id;\n};\n\n/*\n * Structure that defines a VSI, associated with a adapter.\n */\nstruct i40e_vsi {\n\tstruct i40e_adapter *adapter; /* Backreference to associated adapter */\n\tstruct i40e_aqc_vsi_properties_data info; /* VSI properties */\n\n\tstruct i40e_eth_stats eth_stats_offset;\n\tstruct i40e_eth_stats eth_stats;\n\t/*\n\t * When drivers loaded, only a default main VSI exists. In case new VSI\n\t * needs to add, HW needs to know the layout that VSIs are organized.\n\t * Besides that, VSI isan element and can't switch packets, which needs\n\t * to add new component VEB to perform switching. So, a new VSI needs\n\t * to specify the the uplink VSI (Parent VSI) before created. The\n\t * uplink VSI will check whether it had a VEB to switch packets. If no,\n\t * it will try to create one. Then, uplink VSI will move the new VSI\n\t * into its' sib_vsi_list to manage all the downlink VSI.\n\t * sib_vsi_list: the VSI list that shared the same uplink VSI.\n\t * parent_vsi : the uplink VSI. It's NULL for main VSI.\n\t * veb : the VEB associates with the VSI.\n\t */\n\tstruct i40e_vsi_list sib_vsi_list; /* sibling vsi list */\n\tstruct i40e_vsi *parent_vsi;\n\tstruct i40e_veb *veb; /* Associated veb, could be null */\n\tbool offset_loaded;\n\tenum i40e_vsi_type type; /* VSI types */\n\tuint16_t vlan_num; /* Total VLAN number */\n\tuint16_t mac_num; /* Total mac number */\n\tuint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */\n\tstruct i40e_mac_filter_list mac_list; /* macvlan filter list */\n\t/* specific VSI-defined parameters, SRIOV stored the vf_id */\n\tuint32_t user_param;\n\tuint16_t seid; /* The seid of VSI itself */\n\tuint16_t uplink_seid; /* The uplink seid of this VSI */\n\tuint16_t nb_qps; /* Number of queue pairs VSI can occupy */\n\tuint16_t max_macaddrs; /* Maximum number of MAC addresses */\n\tuint16_t base_queue; /* The first queue index of this VSI */\n\t/*\n\t * The offset to visit VSI related register, assigned by HW when\n\t * creating VSI\n\t */\n\tuint16_t vsi_id;\n\tuint16_t msix_intr; /* The MSIX interrupt binds to VSI */\n\tuint8_t enabled_tc; /* The traffic class enabled */\n};\n\nstruct pool_entry {\n\tLIST_ENTRY(pool_entry) next;\n\tuint16_t base;\n\tuint16_t len;\n};\n\nLIST_HEAD(res_list, pool_entry);\n\nstruct i40e_res_pool_info {\n\tuint32_t base; /* Resource start index */\n\tuint32_t num_alloc; /* Allocated resource number */\n\tuint32_t num_free; /* Total available resource number */\n\tstruct res_list alloc_list; /* Allocated resource list */\n\tstruct res_list free_list; /* Available resource list */\n};\n\nenum I40E_VF_STATE {\n\tI40E_VF_INACTIVE = 0,\n\tI40E_VF_INRESET,\n\tI40E_VF_ININIT,\n\tI40E_VF_ACTIVE,\n};\n\n/*\n * Structure to store private data for PF host.\n */\nstruct i40e_pf_vf {\n\tstruct i40e_pf *pf;\n\tstruct i40e_vsi *vsi;\n\tenum I40E_VF_STATE state; /* The number of queue pairs availiable */\n\tuint16_t vf_idx; /* VF index in pf->vfs */\n\tuint16_t lan_nb_qps; /* Actual queues allocated */\n\tuint16_t reset_cnt; /* Total vf reset times */\n};\n\n/*\n * Structure to store private data for VMDQ instance\n */\nstruct i40e_vmdq_info {\n\tstruct i40e_pf *pf;\n\tstruct i40e_vsi *vsi;\n};\n\n/*\n * Structure to store flex pit for flow diretor.\n */\nstruct i40e_fdir_flex_pit {\n\tuint8_t src_offset; /* offset in words from the beginning of payload */\n\tuint8_t size; /* size in words */\n\tuint8_t dst_offset; /* offset in words of flexible payload */\n};\n\nstruct i40e_fdir_flex_mask {\n\tuint8_t word_mask; /**< Bit i enables word i of flexible payload */\n\tstruct {\n\t\tuint8_t offset;\n\t\tuint16_t mask;\n\t} bitmask[I40E_FDIR_BITMASK_NUM_WORD];\n};\n\n#define I40E_FILTER_PCTYPE_MAX 64\n/*\n * A structure used to define fields of a FDIR related info.\n */\nstruct i40e_fdir_info {\n\tstruct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */\n\tuint16_t match_counter_index; /* Statistic counter index used for fdir*/\n\tstruct i40e_tx_queue *txq;\n\tstruct i40e_rx_queue *rxq;\n\tvoid *prg_pkt; /* memory for fdir program packet */\n\tuint64_t dma_addr; /* physic address of packet memory*/\n\t/*\n\t * the rule how bytes stream is extracted as flexible payload\n\t * for each payload layer, the setting can up to three elements\n\t */\n\tstruct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];\n\tstruct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];\n};\n\n#define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64\n#define I40E_MAX_MIRROR_RULES 64\n/*\n * Mirror rule structure\n */\nstruct i40e_mirror_rule {\n\tTAILQ_ENTRY(i40e_mirror_rule) rules;\n\tuint8_t rule_type;\n\tuint16_t index; /* the sw index of mirror rule */\n\tuint16_t id; /* the rule id assigned by firmware */\n\tuint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */\n\tuint16_t num_entries;\n\t/* the info stores depend on the rule type.\n\t If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.\n\t If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.\n\t */\n\tuint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];\n};\n\nTAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);\n\n/*\n * Structure to store private data specific for PF instance.\n */\nstruct i40e_pf {\n\tstruct i40e_adapter *adapter; /* The adapter this PF associate to */\n\tstruct i40e_vsi *main_vsi; /* pointer to main VSI structure */\n\tuint16_t mac_seid; /* The seid of the MAC of this PF */\n\tuint16_t main_vsi_seid; /* The seid of the main VSI */\n\tuint16_t max_num_vsi;\n\tstruct i40e_res_pool_info qp_pool; /*Queue pair pool */\n\tstruct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */\n\n\tstruct i40e_hw_port_stats stats_offset;\n\tstruct i40e_hw_port_stats stats;\n\tbool offset_loaded;\n\n\tstruct rte_eth_dev_data *dev_data; /* Pointer to the device data */\n\tstruct ether_addr dev_addr; /* PF device mac address */\n\tuint64_t flags; /* PF featuer flags */\n\t/* All kinds of queue pair setting for different VSIs */\n\tstruct i40e_pf_vf *vfs;\n\tuint16_t vf_num;\n\t/* Each of below queue pairs should be power of 2 since it's the\n\t precondition after TC configuration applied */\n\tuint16_t lan_nb_qps; /* The number of queue pairs of LAN */\n\tuint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */\n\tuint16_t vf_nb_qps; /* The number of queue pairs of VF */\n\tuint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */\n\tuint16_t hash_lut_size; /* The size of hash lookup table */\n\t/* store VXLAN UDP ports */\n\tuint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];\n\tuint16_t vxlan_bitmap; /* Vxlan bit mask */\n\n\t/* VMDQ related info */\n\tuint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */\n\tuint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */\n\tstruct i40e_vmdq_info *vmdq;\n\n\tstruct i40e_fdir_info fdir; /* flow director info */\n\tstruct i40e_mirror_rule_list mirror_list;\n\tuint16_t nb_mirror_rule; /* The number of mirror rules */\n};\n\nenum pending_msg {\n\tPFMSG_LINK_CHANGE = 0x1,\n\tPFMSG_RESET_IMPENDING = 0x2,\n\tPFMSG_DRIVER_CLOSE = 0x4,\n};\n\nstruct i40e_vsi_vlan_pvid_info {\n\tuint16_t on; /* Enable or disable pvid */\n\tunion {\n\t\tuint16_t pvid; /* Valid in case 'on' is set to set pvid */\n\t\tstruct {\n\t\t/* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,\n\t\t * while 'untagged' will reject untagged packets.\n\t\t */\n\t\t\tuint8_t tagged;\n\t\t\tuint8_t untagged;\n\t\t} reject;\n\t} config;\n};\n\nstruct i40e_vf_rx_queues {\n\tuint64_t rx_dma_addr;\n\tuint32_t rx_ring_len;\n\tuint32_t buff_size;\n};\n\nstruct i40e_vf_tx_queues {\n\tuint64_t tx_dma_addr;\n\tuint32_t tx_ring_len;\n};\n\n/*\n * Structure to store private data specific for VF instance.\n */\nstruct i40e_vf {\n\tstruct i40e_adapter *adapter; /* The adapter this VF associate to */\n\tstruct rte_eth_dev_data *dev_data; /* Pointer to the device data */\n\tuint16_t num_queue_pairs;\n\tuint16_t max_pkt_len; /* Maximum packet length */\n\tbool promisc_unicast_enabled;\n\tbool promisc_multicast_enabled;\n\n\tuint32_t version_major; /* Major version number */\n\tuint32_t version_minor; /* Minor version number */\n\tuint16_t promisc_flags; /* Promiscuous setting */\n\tuint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */\n\n\t/* Event from pf */\n\tbool dev_closed;\n\tbool link_up;\n\tbool vf_reset;\n\tvolatile uint32_t pend_cmd; /* pending command not finished yet */\n\tu16 pend_msg; /* flags indicates events from pf not handled yet */\n\n\t/* VSI info */\n\tstruct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */\n\tstruct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */\n\tstruct i40e_vsi vsi;\n};\n\n/*\n * Structure to store private data for each PF/VF instance.\n */\nstruct i40e_adapter {\n\t/* Common for both PF and VF */\n\tstruct i40e_hw hw;\n\tstruct rte_eth_dev *eth_dev;\n\n\t/* Specific for PF or VF */\n\tunion {\n\t\tstruct i40e_pf pf;\n\t\tstruct i40e_vf vf;\n\t};\n};\n\nint i40e_dev_switch_queues(struct i40e_pf *pf, bool on);\nint i40e_vsi_release(struct i40e_vsi *vsi);\nstruct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,\n\t\t\t\tenum i40e_vsi_type type,\n\t\t\t\tstruct i40e_vsi *uplink_vsi,\n\t\t\t\tuint16_t user_param);\nint i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);\nint i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);\nint i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);\nint i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);\nint i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);\nint i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);\nvoid i40e_update_vsi_stats(struct i40e_vsi *vsi);\nvoid i40e_pf_disable_irq0(struct i40e_hw *hw);\nvoid i40e_pf_enable_irq0(struct i40e_hw *hw);\nint i40e_dev_link_update(struct rte_eth_dev *dev,\n\t\t\t __rte_unused int wait_to_complete);\nvoid i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);\nvoid i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);\nint i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,\n\t\t\t struct i40e_vsi_vlan_pvid_info *info);\nint i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);\nuint64_t i40e_config_hena(uint64_t flags);\nuint64_t i40e_parse_hena(uint64_t flags);\nenum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);\nenum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);\nint i40e_fdir_setup(struct i40e_pf *pf);\nconst struct rte_memzone *i40e_memzone_reserve(const char *name,\n\t\t\t\t\tuint32_t len,\n\t\t\t\t\tint socket_id);\nint i40e_fdir_configure(struct rte_eth_dev *dev);\nvoid i40e_fdir_teardown(struct i40e_pf *pf);\nenum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);\nuint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);\nint i40e_fdir_ctrl_func(struct rte_eth_dev *dev,\n\t\t\t enum rte_filter_op filter_op,\n\t\t\t void *arg);\n\n/* I40E_DEV_PRIVATE_TO */\n#define I40E_DEV_PRIVATE_TO_PF(adapter) \\\n\t(&((struct i40e_adapter *)adapter)->pf)\n#define I40E_DEV_PRIVATE_TO_HW(adapter) \\\n\t(&((struct i40e_adapter *)adapter)->hw)\n#define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \\\n\t((struct i40e_adapter *)adapter)\n\n/* I40EVF_DEV_PRIVATE_TO */\n#define I40EVF_DEV_PRIVATE_TO_VF(adapter) \\\n\t(&((struct i40e_adapter *)adapter)->vf)\n\nstatic inline struct i40e_vsi *\ni40e_get_vsi_from_adapter(struct i40e_adapter *adapter)\n{\n\tstruct i40e_hw *hw;\n\n if (!adapter)\n return NULL;\n\n\thw = I40E_DEV_PRIVATE_TO_HW(adapter);\n\tif (hw->mac.type == I40E_MAC_VF) {\n\t\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);\n\t\treturn &vf->vsi;\n\t} else {\n\t\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);\n\t\treturn pf->main_vsi;\n\t}\n}\n#define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \\\n\ti40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)\n\n/* I40E_VSI_TO */\n#define I40E_VSI_TO_HW(vsi) \\\n\t(&(((struct i40e_vsi *)vsi)->adapter->hw))\n#define I40E_VSI_TO_PF(vsi) \\\n\t(&(((struct i40e_vsi *)vsi)->adapter->pf))\n#define I40E_VSI_TO_DEV_DATA(vsi) \\\n\t(((struct i40e_vsi *)vsi)->adapter->pf.dev_data)\n#define I40E_VSI_TO_ETH_DEV(vsi) \\\n\t(((struct i40e_vsi *)vsi)->adapter->eth_dev)\n\n/* I40E_PF_TO */\n#define I40E_PF_TO_HW(pf) \\\n\t(&(((struct i40e_pf *)pf)->adapter->hw))\n#define I40E_PF_TO_ADAPTER(pf) \\\n\t((struct i40e_adapter *)pf->adapter)\n\n/* I40E_VF_TO */\n#define I40E_VF_TO_HW(vf) \\\n\t(&(((struct i40e_vf *)vf)->adapter->hw))\n\nstatic inline void\ni40e_init_adminq_parameter(struct i40e_hw *hw)\n{\n\thw->aq.num_arq_entries = I40E_AQ_LEN;\n\thw->aq.num_asq_entries = I40E_AQ_LEN;\n\thw->aq.arq_buf_size = I40E_AQ_BUF_SZ;\n\thw->aq.asq_buf_size = I40E_AQ_BUF_SZ;\n}\n\nstatic inline int\ni40e_align_floor(int n)\n{\n\tif (n == 0)\n\t\treturn 0;\n\treturn 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));\n}\n\n#define I40E_VALID_FLOW(flow_type) \\\n\t((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \\\n\t(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \\\n\t(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \\\n\t(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \\\n\t(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \\\n\t(flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \\\n\t(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \\\n\t(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \\\n\t(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \\\n\t(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \\\n\t(flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)\n\n#define I40E_VALID_PCTYPE(pctype) \\\n\t((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \\\n\t(pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \\\n\t(pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \\\n\t(pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \\\n\t(pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \\\n\t(pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \\\n\t(pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \\\n\t(pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \\\n\t(pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \\\n\t(pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \\\n\t(pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)\n\n#endif /* _I40E_ETHDEV_H_ */\n" }, { "path": "drivers/net/i40e/i40e_ethdev_vf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"i40e_logs.h\"\n#include \"base/i40e_prototype.h\"\n#include \"base/i40e_adminq_cmd.h\"\n#include \"base/i40e_type.h\"\n\n#include \"i40e_rxtx.h\"\n#include \"i40e_ethdev.h\"\n#include \"i40e_pf.h\"\n#define I40EVF_VSI_DEFAULT_MSIX_INTR 1\n\n/* busy wait delay in msec */\n#define I40EVF_BUSY_WAIT_DELAY 10\n#define I40EVF_BUSY_WAIT_COUNT 50\n#define MAX_RESET_WAIT_CNT 20\n\nstruct i40evf_arq_msg_info {\n\tenum i40e_virtchnl_ops ops;\n\tenum i40e_status_code result;\n\tuint16_t buf_len;\n\tuint16_t msg_len;\n\tuint8_t *msg;\n};\n\nstruct vf_cmd_info {\n\tenum i40e_virtchnl_ops ops;\n\tuint8_t *in_args;\n\tuint32_t in_args_size;\n\tuint8_t *out_buffer;\n\t/* Input & output type. pass in buffer size and pass out\n\t * actual return result\n\t */\n\tuint32_t out_size;\n};\n\nenum i40evf_aq_result {\n\tI40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */\n\tI40EVF_MSG_NON, /* Read nothing from admin queue */\n\tI40EVF_MSG_SYS, /* Read system msg from admin queue */\n\tI40EVF_MSG_CMD, /* Read async command result */\n};\n\n/* A share buffer to store the command result from PF driver */\nstatic uint8_t cmd_result_buffer[I40E_AQ_BUF_SZ];\n\nstatic int i40evf_dev_configure(struct rte_eth_dev *dev);\nstatic int i40evf_dev_start(struct rte_eth_dev *dev);\nstatic void i40evf_dev_stop(struct rte_eth_dev *dev);\nstatic void i40evf_dev_info_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_dev_info *dev_info);\nstatic int i40evf_dev_link_update(struct rte_eth_dev *dev,\n\t\t\t\t __rte_unused int wait_to_complete);\nstatic void i40evf_dev_stats_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_stats *stats);\nstatic int i40evf_vlan_filter_set(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t vlan_id, int on);\nstatic void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);\nstatic int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,\n\t\t\t\tint on);\nstatic void i40evf_dev_close(struct rte_eth_dev *dev);\nstatic void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);\nstatic void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);\nstatic void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);\nstatic void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);\nstatic int i40evf_get_link_status(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_link *link);\nstatic int i40evf_init_vlan(struct rte_eth_dev *dev);\nstatic int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t rx_queue_id);\nstatic int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t rx_queue_id);\nstatic int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t tx_queue_id);\nstatic int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t tx_queue_id);\nstatic int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\tuint16_t reta_size);\nstatic int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\tuint16_t reta_size);\nstatic int i40evf_config_rss(struct i40e_vf *vf);\nstatic int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_rss_conf *rss_conf);\nstatic int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n\t\t\t\t\tstruct rte_eth_rss_conf *rss_conf);\n\n/* Default hash key buffer for RSS */\nstatic uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];\n\nstatic const struct eth_dev_ops i40evf_eth_dev_ops = {\n\t.dev_configure = i40evf_dev_configure,\n\t.dev_start = i40evf_dev_start,\n\t.dev_stop = i40evf_dev_stop,\n\t.promiscuous_enable = i40evf_dev_promiscuous_enable,\n\t.promiscuous_disable = i40evf_dev_promiscuous_disable,\n\t.allmulticast_enable = i40evf_dev_allmulticast_enable,\n\t.allmulticast_disable = i40evf_dev_allmulticast_disable,\n\t.link_update = i40evf_dev_link_update,\n\t.stats_get = i40evf_dev_stats_get,\n\t.dev_close = i40evf_dev_close,\n\t.dev_infos_get = i40evf_dev_info_get,\n\t.vlan_filter_set = i40evf_vlan_filter_set,\n\t.vlan_offload_set = i40evf_vlan_offload_set,\n\t.vlan_pvid_set = i40evf_vlan_pvid_set,\n\t.rx_queue_start = i40evf_dev_rx_queue_start,\n\t.rx_queue_stop = i40evf_dev_rx_queue_stop,\n\t.tx_queue_start = i40evf_dev_tx_queue_start,\n\t.tx_queue_stop = i40evf_dev_tx_queue_stop,\n\t.rx_queue_setup = i40e_dev_rx_queue_setup,\n\t.rx_queue_release = i40e_dev_rx_queue_release,\n\t.tx_queue_setup = i40e_dev_tx_queue_setup,\n\t.tx_queue_release = i40e_dev_tx_queue_release,\n\t.reta_update = i40evf_dev_rss_reta_update,\n\t.reta_query = i40evf_dev_rss_reta_query,\n\t.rss_hash_update = i40evf_dev_rss_hash_update,\n\t.rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,\n};\n\nstatic int\ni40evf_set_mac_type(struct i40e_hw *hw)\n{\n\tint status = I40E_ERR_DEVICE_NOT_SUPPORTED;\n\n\tif (hw->vendor_id == I40E_INTEL_VENDOR_ID) {\n\t\tswitch (hw->device_id) {\n\t\tcase I40E_DEV_ID_VF:\n\t\tcase I40E_DEV_ID_VF_HV:\n\t\t\thw->mac.type = I40E_MAC_VF;\n\t\t\tstatus = I40E_SUCCESS;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t;\n\t\t}\n\t}\n\n\treturn status;\n}\n\n/*\n * Parse admin queue message.\n *\n * return value:\n * < 0: meet error\n * 0: read sys msg\n * > 0: read cmd result\n */\nstatic enum i40evf_aq_result\ni40evf_parse_pfmsg(struct i40e_vf *vf,\n\t\t struct i40e_arq_event_info *event,\n\t\t struct i40evf_arq_msg_info *data)\n{\n\tenum i40e_virtchnl_ops opcode = (enum i40e_virtchnl_ops)\\\n\t\t\trte_le_to_cpu_32(event->desc.cookie_high);\n\tenum i40e_status_code retval = (enum i40e_status_code)\\\n\t\t\trte_le_to_cpu_32(event->desc.cookie_low);\n\tenum i40evf_aq_result ret = I40EVF_MSG_CMD;\n\n\t/* pf sys event */\n\tif (opcode == I40E_VIRTCHNL_OP_EVENT) {\n\t\tstruct i40e_virtchnl_pf_event *vpe =\n\t\t\t(struct i40e_virtchnl_pf_event *)event->msg_buf;\n\n\t\t/* Initialize ret to sys event */\n\t\tret = I40EVF_MSG_SYS;\n\t\tswitch (vpe->event) {\n\t\tcase I40E_VIRTCHNL_EVENT_LINK_CHANGE:\n\t\t\tvf->link_up =\n\t\t\t\tvpe->event_data.link_event.link_status;\n\t\t\tvf->pend_msg |= PFMSG_LINK_CHANGE;\n\t\t\tPMD_DRV_LOG(INFO, \"Link status update:%s\",\n\t\t\t\t vf->link_up ? \"up\" : \"down\");\n\t\t\tbreak;\n\t\tcase I40E_VIRTCHNL_EVENT_RESET_IMPENDING:\n\t\t\tvf->vf_reset = true;\n\t\t\tvf->pend_msg |= PFMSG_RESET_IMPENDING;\n\t\t\tPMD_DRV_LOG(INFO, \"vf is reseting\");\n\t\t\tbreak;\n\t\tcase I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:\n\t\t\tvf->dev_closed = true;\n\t\t\tvf->pend_msg |= PFMSG_DRIVER_CLOSE;\n\t\t\tPMD_DRV_LOG(INFO, \"PF driver closed\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tPMD_DRV_LOG(ERR, \"%s: Unknown event %d from pf\",\n\t\t\t\t __func__, vpe->event);\n\t\t}\n\t} else {\n\t\t/* async reply msg on command issued by vf previously */\n\t\tret = I40EVF_MSG_CMD;\n\t\t/* Actual data length read from PF */\n\t\tdata->msg_len = event->msg_len;\n\t}\n\t/* fill the ops and result to notify VF */\n\tdata->result = retval;\n\tdata->ops = opcode;\n\n\treturn ret;\n}\n\n/*\n * Read data in admin queue to get msg from pf driver\n */\nstatic enum i40evf_aq_result\ni40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tstruct i40e_arq_event_info event;\n\tint ret;\n\tenum i40evf_aq_result result = I40EVF_MSG_NON;\n\n\tevent.buf_len = data->buf_len;\n\tevent.msg_buf = data->msg;\n\tret = i40e_clean_arq_element(hw, &event, NULL);\n\t/* Can't read any msg from adminQ */\n\tif (ret) {\n\t\tif (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)\n\t\t\tresult = I40EVF_MSG_NON;\n\t\telse\n\t\t\tresult = I40EVF_MSG_ERR;\n\t\treturn result;\n\t}\n\n\t/* Parse the event */\n\tresult = i40evf_parse_pfmsg(vf, &event, data);\n\n\treturn result;\n}\n\n/*\n * Polling read until command result return from pf driver or meet error.\n */\nstatic int\ni40evf_wait_cmd_done(struct rte_eth_dev *dev,\n\t\t struct i40evf_arq_msg_info *data)\n{\n\tint i = 0;\n\tenum i40evf_aq_result ret;\n\n#define MAX_TRY_TIMES 20\n#define ASQ_DELAY_MS 100\n\tdo {\n\t\t/* Delay some time first */\n\t\trte_delay_ms(ASQ_DELAY_MS);\n\t\tret = i40evf_read_pfmsg(dev, data);\n\t\tif (ret == I40EVF_MSG_CMD)\n\t\t\treturn 0;\n\t\telse if (ret == I40EVF_MSG_ERR)\n\t\t\treturn -1;\n\n\t\t/* If don't read msg or read sys event, continue */\n\t} while(i++ < MAX_TRY_TIMES);\n\n\treturn -1;\n}\n\n/**\n * clear current command. Only call in case execute\n * _atomic_set_cmd successfully.\n */\nstatic inline void\n_clear_cmd(struct i40e_vf *vf)\n{\n\trte_wmb();\n\tvf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;\n}\n\n/*\n * Check there is pending cmd in execution. If none, set new command.\n */\nstatic inline int\n_atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)\n{\n\tint ret = rte_atomic32_cmpset(&vf->pend_cmd,\n\t\t\tI40E_VIRTCHNL_OP_UNKNOWN, ops);\n\n\tif (!ret)\n\t\tPMD_DRV_LOG(ERR, \"There is incomplete cmd %d\", vf->pend_cmd);\n\n\treturn !ret;\n}\n\nstatic int\ni40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tint err = -1;\n\tstruct i40evf_arq_msg_info info;\n\n\tif (_atomic_set_cmd(vf, args->ops))\n\t\treturn -1;\n\n\tinfo.msg = args->out_buffer;\n\tinfo.buf_len = args->out_size;\n\tinfo.ops = I40E_VIRTCHNL_OP_UNKNOWN;\n\tinfo.result = I40E_SUCCESS;\n\n\terr = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,\n\t\t args->in_args, args->in_args_size, NULL);\n\tif (err) {\n\t\tPMD_DRV_LOG(ERR, \"fail to send cmd %d\", args->ops);\n\t\t_clear_cmd(vf);\n\t\treturn err;\n\t}\n\n\terr = i40evf_wait_cmd_done(dev, &info);\n\t/* read message and it's expected one */\n\tif (!err && args->ops == info.ops)\n\t\t_clear_cmd(vf);\n\telse if (err) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to read message from AdminQ\");\n\t\t_clear_cmd(vf);\n\t}\n\telse if (args->ops != info.ops)\n\t\tPMD_DRV_LOG(ERR, \"command mismatch, expect %u, get %u\",\n\t\t\t args->ops, info.ops);\n\n\treturn (err | info.result);\n}\n\n/*\n * Check API version with sync wait until version read or fail from admin queue\n */\nstatic int\ni40evf_check_api_version(struct rte_eth_dev *dev)\n{\n\tstruct i40e_virtchnl_version_info version, *pver;\n\tint err;\n\tstruct vf_cmd_info args;\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\n\tversion.major = I40E_VIRTCHNL_VERSION_MAJOR;\n\tversion.minor = I40E_VIRTCHNL_VERSION_MINOR;\n\n\targs.ops = I40E_VIRTCHNL_OP_VERSION;\n\targs.in_args = (uint8_t *)&version;\n\targs.in_args_size = sizeof(version);\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\tif (err) {\n\t\tPMD_INIT_LOG(ERR, \"fail to execute command OP_VERSION\");\n\t\treturn err;\n\t}\n\n\tpver = (struct i40e_virtchnl_version_info *)args.out_buffer;\n\tvf->version_major = pver->major;\n\tvf->version_minor = pver->minor;\n\tif (vf->version_major == I40E_DPDK_VERSION_MAJOR)\n\t\tPMD_DRV_LOG(INFO, \"Peer is DPDK PF host\");\n\telse if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&\n\t\t(vf->version_minor == I40E_VIRTCHNL_VERSION_MINOR))\n\t\tPMD_DRV_LOG(INFO, \"Peer is Linux PF host\");\n\telse {\n\t\tPMD_INIT_LOG(ERR, \"PF/VF API version mismatch:(%u.%u)-(%u.%u)\",\n\t\t\t\t\tvf->version_major, vf->version_minor,\n\t\t\t\t\t\tI40E_VIRTCHNL_VERSION_MAJOR,\n\t\t\t\t\t\tI40E_VIRTCHNL_VERSION_MINOR);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40evf_get_vf_resource(struct rte_eth_dev *dev)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tint err;\n\tstruct vf_cmd_info args;\n\tuint32_t len;\n\n\targs.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;\n\targs.in_args = NULL;\n\targs.in_args_size = 0;\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\n\tif (err) {\n\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_GET_VF_RESOURCE\");\n\t\treturn err;\n\t}\n\n\tlen = sizeof(struct i40e_virtchnl_vf_resource) +\n\t\tI40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);\n\n\t(void)rte_memcpy(vf->vf_res, args.out_buffer,\n\t\t\tRTE_MIN(args.out_size, len));\n\ti40e_vf_parse_hw_config(hw, vf->vf_res);\n\n\treturn 0;\n}\n\nstatic int\ni40evf_config_promisc(struct rte_eth_dev *dev,\n\t\t bool enable_unicast,\n\t\t bool enable_multicast)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tint err;\n\tstruct vf_cmd_info args;\n\tstruct i40e_virtchnl_promisc_info promisc;\n\n\tpromisc.flags = 0;\n\tpromisc.vsi_id = vf->vsi_res->vsi_id;\n\n\tif (enable_unicast)\n\t\tpromisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;\n\n\tif (enable_multicast)\n\t\tpromisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;\n\n\targs.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;\n\targs.in_args = (uint8_t *)&promisc;\n\targs.in_args_size = sizeof(promisc);\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\n\tif (err)\n\t\tPMD_DRV_LOG(ERR, \"fail to execute command \"\n\t\t\t \"CONFIG_PROMISCUOUS_MODE\");\n\treturn err;\n}\n\n/* Configure vlan and double vlan offload. Use flag to specify which part to configure */\nstatic int\ni40evf_config_vlan_offload(struct rte_eth_dev *dev,\n\t\t\t\tbool enable_vlan_strip)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tint err;\n\tstruct vf_cmd_info args;\n\tstruct i40e_virtchnl_vlan_offload_info offload;\n\n\toffload.vsi_id = vf->vsi_res->vsi_id;\n\toffload.enable_vlan_strip = enable_vlan_strip;\n\n\targs.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;\n\targs.in_args = (uint8_t *)&offload;\n\targs.in_args_size = sizeof(offload);\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\tif (err)\n\t\tPMD_DRV_LOG(ERR, \"fail to execute command CFG_VLAN_OFFLOAD\");\n\n\treturn err;\n}\n\nstatic int\ni40evf_config_vlan_pvid(struct rte_eth_dev *dev,\n\t\t\t\tstruct i40e_vsi_vlan_pvid_info *info)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tint err;\n\tstruct vf_cmd_info args;\n\tstruct i40e_virtchnl_pvid_info tpid_info;\n\n\tif (dev == NULL || info == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"invalid parameters\");\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\tmemset(&tpid_info, 0, sizeof(tpid_info));\n\ttpid_info.vsi_id = vf->vsi_res->vsi_id;\n\t(void)rte_memcpy(&tpid_info.info, info, sizeof(*info));\n\n\targs.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;\n\targs.in_args = (uint8_t *)&tpid_info;\n\targs.in_args_size = sizeof(tpid_info);\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\tif (err)\n\t\tPMD_DRV_LOG(ERR, \"fail to execute command CFG_VLAN_PVID\");\n\n\treturn err;\n}\n\nstatic void\ni40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,\n\t\t\t\t uint16_t vsi_id,\n\t\t\t\t uint16_t queue_id,\n\t\t\t\t uint16_t nb_txq,\n\t\t\t\t struct i40e_tx_queue *txq)\n{\n\ttxq_info->vsi_id = vsi_id;\n\ttxq_info->queue_id = queue_id;\n\tif (queue_id < nb_txq) {\n\t\ttxq_info->ring_len = txq->nb_tx_desc;\n\t\ttxq_info->dma_ring_addr = txq->tx_ring_phys_addr;\n\t}\n}\n\nstatic void\ni40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,\n\t\t\t\t uint16_t vsi_id,\n\t\t\t\t uint16_t queue_id,\n\t\t\t\t uint16_t nb_rxq,\n\t\t\t\t uint32_t max_pkt_size,\n\t\t\t\t struct i40e_rx_queue *rxq)\n{\n\trxq_info->vsi_id = vsi_id;\n\trxq_info->queue_id = queue_id;\n\trxq_info->max_pkt_size = max_pkt_size;\n\tif (queue_id < nb_rxq) {\n\t\trxq_info->ring_len = rxq->nb_rx_desc;\n\t\trxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;\n\t\trxq_info->databuffer_size =\n\t\t\t(rte_pktmbuf_data_room_size(rxq->mp) -\n\t\t\t\tRTE_PKTMBUF_HEADROOM);\n\t}\n}\n\n/* It configures VSI queues to co-work with Linux PF host */\nstatic int\ni40evf_configure_vsi_queues(struct rte_eth_dev *dev)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tstruct i40e_rx_queue **rxq =\n\t\t(struct i40e_rx_queue **)dev->data->rx_queues;\n\tstruct i40e_tx_queue **txq =\n\t\t(struct i40e_tx_queue **)dev->data->tx_queues;\n\tstruct i40e_virtchnl_vsi_queue_config_info *vc_vqci;\n\tstruct i40e_virtchnl_queue_pair_info *vc_qpi;\n\tstruct vf_cmd_info args;\n\tuint16_t i, nb_qp = vf->num_queue_pairs;\n\tconst uint32_t size =\n\t\tI40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);\n\tuint8_t buff[size];\n\tint ret;\n\n\tmemset(buff, 0, sizeof(buff));\n\tvc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;\n\tvc_vqci->vsi_id = vf->vsi_res->vsi_id;\n\tvc_vqci->num_queue_pairs = nb_qp;\n\n\tfor (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {\n\t\ti40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,\n\t\t\tvc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);\n\t\ti40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,\n\t\t\tvc_vqci->vsi_id, i, dev->data->nb_rx_queues,\n\t\t\t\t\tvf->max_pkt_len, rxq[i]);\n\t}\n\tmemset(&args, 0, sizeof(args));\n\targs.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;\n\targs.in_args = (uint8_t *)vc_vqci;\n\targs.in_args_size = size;\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\tret = i40evf_execute_vf_cmd(dev, &args);\n\tif (ret)\n\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of \"\n\t\t\t\"I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\\n\");\n\n\treturn ret;\n}\n\n/* It configures VSI queues to co-work with DPDK PF host */\nstatic int\ni40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tstruct i40e_rx_queue **rxq =\n\t\t(struct i40e_rx_queue **)dev->data->rx_queues;\n\tstruct i40e_tx_queue **txq =\n\t\t(struct i40e_tx_queue **)dev->data->tx_queues;\n\tstruct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;\n\tstruct i40e_virtchnl_queue_pair_ext_info *vc_qpei;\n\tstruct vf_cmd_info args;\n\tuint16_t i, nb_qp = vf->num_queue_pairs;\n\tconst uint32_t size =\n\t\tI40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);\n\tuint8_t buff[size];\n\tint ret;\n\n\tmemset(buff, 0, sizeof(buff));\n\tvc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;\n\tvc_vqcei->vsi_id = vf->vsi_res->vsi_id;\n\tvc_vqcei->num_queue_pairs = nb_qp;\n\tvc_qpei = vc_vqcei->qpair;\n\tfor (i = 0; i < nb_qp; i++, vc_qpei++) {\n\t\ti40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,\n\t\t\tvc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);\n\t\ti40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,\n\t\t\tvc_vqcei->vsi_id, i, dev->data->nb_rx_queues,\n\t\t\t\t\tvf->max_pkt_len, rxq[i]);\n\t\tif (i < dev->data->nb_rx_queues)\n\t\t\t/*\n\t\t\t * It adds extra info for configuring VSI queues, which\n\t\t\t * is needed to enable the configurable crc stripping\n\t\t\t * in VF.\n\t\t\t */\n\t\t\tvc_qpei->rxq_ext.crcstrip =\n\t\t\t\tdev->data->dev_conf.rxmode.hw_strip_crc;\n\t}\n\tmemset(&args, 0, sizeof(args));\n\targs.ops =\n\t\t(enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;\n\targs.in_args = (uint8_t *)vc_vqcei;\n\targs.in_args_size = size;\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\tret = i40evf_execute_vf_cmd(dev, &args);\n\tif (ret)\n\t\tPMD_DRV_LOG(ERR, \"Failed to execute command of \"\n\t\t\t\"I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\\n\");\n\n\treturn ret;\n}\n\nstatic int\ni40evf_configure_queues(struct rte_eth_dev *dev)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\n\tif (vf->version_major == I40E_DPDK_VERSION_MAJOR)\n\t\t/* To support DPDK PF host */\n\t\treturn i40evf_configure_vsi_queues_ext(dev);\n\telse\n\t\t/* To support Linux PF host */\n\t\treturn i40evf_configure_vsi_queues(dev);\n}\n\nstatic int\ni40evf_config_irq_map(struct rte_eth_dev *dev)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tstruct vf_cmd_info args;\n\tuint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \\\n\t\tsizeof(struct i40e_virtchnl_vector_map)];\n\tstruct i40e_virtchnl_irq_map_info *map_info;\n\tint i, err;\n\tmap_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;\n\tmap_info->num_vectors = 1;\n\tmap_info->vecmap[0].rxitr_idx = RTE_LIBRTE_I40E_ITR_INTERVAL / 2;\n\tmap_info->vecmap[0].txitr_idx = RTE_LIBRTE_I40E_ITR_INTERVAL / 2;\n\tmap_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;\n\t/* Alway use default dynamic MSIX interrupt */\n\tmap_info->vecmap[0].vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;\n\t/* Don't map any tx queue */\n\tmap_info->vecmap[0].txq_map = 0;\n\tmap_info->vecmap[0].rxq_map = 0;\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n\t\tmap_info->vecmap[0].rxq_map |= 1 << i;\n\n\targs.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;\n\targs.in_args = (u8 *)cmd_buffer;\n\targs.in_args_size = sizeof(cmd_buffer);\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\tif (err)\n\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_ENABLE_QUEUES\");\n\n\treturn err;\n}\n\nstatic int\ni40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,\n\t\t\t\tbool on)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tstruct i40e_virtchnl_queue_select queue_select;\n\tint err;\n\tstruct vf_cmd_info args;\n\tmemset(&queue_select, 0, sizeof(queue_select));\n\tqueue_select.vsi_id = vf->vsi_res->vsi_id;\n\n\tif (isrx)\n\t\tqueue_select.rx_queues |= 1 << qid;\n\telse\n\t\tqueue_select.tx_queues |= 1 << qid;\n\n\tif (on)\n\t\targs.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;\n\telse\n\t\targs.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;\n\targs.in_args = (u8 *)&queue_select;\n\targs.in_args_size = sizeof(queue_select);\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\tif (err)\n\t\tPMD_DRV_LOG(ERR, \"fail to switch %s %u %s\",\n\t\t\t isrx ? \"RX\" : \"TX\", qid, on ? \"on\" : \"off\");\n\n\treturn err;\n}\n\nstatic int\ni40evf_start_queues(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_dev_data *dev_data = dev->data;\n\tint i;\n\tstruct i40e_rx_queue *rxq;\n\tstruct i40e_tx_queue *txq;\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\trxq = dev_data->rx_queues[i];\n\t\tif (rxq->rx_deferred_start)\n\t\t\tcontinue;\n\t\tif (i40evf_dev_rx_queue_start(dev, i) != 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"Fail to start queue %u\", i);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\ttxq = dev_data->tx_queues[i];\n\t\tif (txq->tx_deferred_start)\n\t\t\tcontinue;\n\t\tif (i40evf_dev_tx_queue_start(dev, i) != 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"Fail to start queue %u\", i);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40evf_stop_queues(struct rte_eth_dev *dev)\n{\n\tint i;\n\n\t/* Stop TX queues first */\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tif (i40evf_dev_tx_queue_stop(dev, i) != 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"Fail to stop queue %u\", i);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* Then stop RX queues */\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tif (i40evf_dev_rx_queue_stop(dev, i) != 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"Fail to stop queue %u\", i);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40evf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)\n{\n\tstruct i40e_virtchnl_ether_addr_list *list;\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tuint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \\\n\t\t\tsizeof(struct i40e_virtchnl_ether_addr)];\n\tint err;\n\tstruct vf_cmd_info args;\n\n\tif (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid mac:%x:%x:%x:%x:%x:%x\",\n\t\t\t addr->addr_bytes[0], addr->addr_bytes[1],\n\t\t\t addr->addr_bytes[2], addr->addr_bytes[3],\n\t\t\t addr->addr_bytes[4], addr->addr_bytes[5]);\n\t\treturn -1;\n\t}\n\n\tlist = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;\n\tlist->vsi_id = vf->vsi_res->vsi_id;\n\tlist->num_elements = 1;\n\t(void)rte_memcpy(list->list[0].addr, addr->addr_bytes,\n\t\t\t\t\tsizeof(addr->addr_bytes));\n\n\targs.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;\n\targs.in_args = cmd_buffer;\n\targs.in_args_size = sizeof(cmd_buffer);\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\tif (err)\n\t\tPMD_DRV_LOG(ERR, \"fail to execute command \"\n\t\t\t \"OP_ADD_ETHER_ADDRESS\");\n\n\treturn err;\n}\n\nstatic int\ni40evf_del_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)\n{\n\tstruct i40e_virtchnl_ether_addr_list *list;\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tuint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \\\n\t\t\tsizeof(struct i40e_virtchnl_ether_addr)];\n\tint err;\n\tstruct vf_cmd_info args;\n\n\tif (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid mac:%x-%x-%x-%x-%x-%x\",\n\t\t\t addr->addr_bytes[0], addr->addr_bytes[1],\n\t\t\t addr->addr_bytes[2], addr->addr_bytes[3],\n\t\t\t addr->addr_bytes[4], addr->addr_bytes[5]);\n\t\treturn -1;\n\t}\n\n\tlist = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;\n\tlist->vsi_id = vf->vsi_res->vsi_id;\n\tlist->num_elements = 1;\n\t(void)rte_memcpy(list->list[0].addr, addr->addr_bytes,\n\t\t\tsizeof(addr->addr_bytes));\n\n\targs.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;\n\targs.in_args = cmd_buffer;\n\targs.in_args_size = sizeof(cmd_buffer);\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\tif (err)\n\t\tPMD_DRV_LOG(ERR, \"fail to execute command \"\n\t\t\t \"OP_DEL_ETHER_ADDRESS\");\n\n\treturn err;\n}\n\nstatic int\ni40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tstruct i40e_virtchnl_queue_select q_stats;\n\tstruct i40e_eth_stats *pstats;\n\tint err;\n\tstruct vf_cmd_info args;\n\n\tmemset(&q_stats, 0, sizeof(q_stats));\n\tq_stats.vsi_id = vf->vsi_res->vsi_id;\n\targs.ops = I40E_VIRTCHNL_OP_GET_STATS;\n\targs.in_args = (u8 *)&q_stats;\n\targs.in_args_size = sizeof(q_stats);\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\tif (err) {\n\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_GET_STATS\");\n\t\treturn err;\n\t}\n\tpstats = (struct i40e_eth_stats *)args.out_buffer;\n\tstats->ipackets = pstats->rx_unicast + pstats->rx_multicast +\n\t\t\t\t\t\tpstats->rx_broadcast;\n\tstats->opackets = pstats->tx_broadcast + pstats->tx_multicast +\n\t\t\t\t\t\tpstats->tx_unicast;\n\tstats->ierrors = pstats->rx_discards;\n\tstats->oerrors = pstats->tx_errors + pstats->tx_discards;\n\tstats->ibytes = pstats->rx_bytes;\n\tstats->obytes = pstats->tx_bytes;\n\n\treturn 0;\n}\n\nstatic int\ni40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tstruct i40e_virtchnl_vlan_filter_list *vlan_list;\n\tuint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +\n\t\t\t\t\t\t\tsizeof(uint16_t)];\n\tint err;\n\tstruct vf_cmd_info args;\n\n\tvlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;\n\tvlan_list->vsi_id = vf->vsi_res->vsi_id;\n\tvlan_list->num_elements = 1;\n\tvlan_list->vlan_id[0] = vlanid;\n\n\targs.ops = I40E_VIRTCHNL_OP_ADD_VLAN;\n\targs.in_args = (u8 *)&cmd_buffer;\n\targs.in_args_size = sizeof(cmd_buffer);\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\tif (err)\n\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_ADD_VLAN\");\n\n\treturn err;\n}\n\nstatic int\ni40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tstruct i40e_virtchnl_vlan_filter_list *vlan_list;\n\tuint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +\n\t\t\t\t\t\t\tsizeof(uint16_t)];\n\tint err;\n\tstruct vf_cmd_info args;\n\n\tvlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;\n\tvlan_list->vsi_id = vf->vsi_res->vsi_id;\n\tvlan_list->num_elements = 1;\n\tvlan_list->vlan_id[0] = vlanid;\n\n\targs.ops = I40E_VIRTCHNL_OP_DEL_VLAN;\n\targs.in_args = (u8 *)&cmd_buffer;\n\targs.in_args_size = sizeof(cmd_buffer);\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\tif (err)\n\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_DEL_VLAN\");\n\n\treturn err;\n}\n\nstatic int\ni40evf_get_link_status(struct rte_eth_dev *dev, struct rte_eth_link *link)\n{\n\tint err;\n\tstruct vf_cmd_info args;\n\tstruct rte_eth_link *new_link;\n\n\targs.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_GET_LINK_STAT;\n\targs.in_args = NULL;\n\targs.in_args_size = 0;\n\targs.out_buffer = cmd_result_buffer;\n\targs.out_size = I40E_AQ_BUF_SZ;\n\terr = i40evf_execute_vf_cmd(dev, &args);\n\tif (err) {\n\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_GET_LINK_STAT\");\n\t\treturn err;\n\t}\n\n\tnew_link = (struct rte_eth_link *)args.out_buffer;\n\t(void)rte_memcpy(link, new_link, sizeof(*link));\n\n\treturn 0;\n}\n\nstatic const struct rte_pci_id pci_id_i40evf_map[] = {\n#define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \"rte_pci_dev_ids.h\"\n{ .vendor_id = 0, /* sentinel */ },\n};\n\nstatic inline int\ni40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = &(dev->data->dev_link);\n\tstruct rte_eth_link *src = link;\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic int\ni40evf_reset_vf(struct i40e_hw *hw)\n{\n\tint i, reset;\n\n\tif (i40e_vf_reset(hw) != I40E_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Reset VF NIC failed\");\n\t\treturn -1;\n\t}\n\t/**\n\t * After issuing vf reset command to pf, pf won't necessarily\n\t * reset vf, it depends on what state it exactly is. If it's not\n\t * initialized yet, it won't have vf reset since it's in a certain\n\t * state. If not, it will try to reset. Even vf is reset, pf will\n\t * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set\n\t * it to ACTIVE. In this duration, vf may not catch the moment that\n\t * COMPLETE is set. So, for vf, we'll try to wait a long time.\n\t */\n\trte_delay_ms(200);\n\n\tfor (i = 0; i < MAX_RESET_WAIT_CNT; i++) {\n\t\treset = rd32(hw, I40E_VFGEN_RSTAT) &\n\t\t\tI40E_VFGEN_RSTAT_VFR_STATE_MASK;\n\t\treset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;\n\t\tif (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)\n\t\t\tbreak;\n\t\telse\n\t\t\trte_delay_ms(50);\n\t}\n\n\tif (i >= MAX_RESET_WAIT_CNT) {\n\t\tPMD_INIT_LOG(ERR, \"Reset VF NIC failed\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40evf_init_vf(struct rte_eth_dev *dev)\n{\n\tint i, err, bufsz;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\n\tvf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n\tvf->dev_data = dev->data;\n\terr = i40evf_set_mac_type(hw);\n\tif (err) {\n\t\tPMD_INIT_LOG(ERR, \"set_mac_type failed: %d\", err);\n\t\tgoto err;\n\t}\n\n\ti40e_init_adminq_parameter(hw);\n\terr = i40e_init_adminq(hw);\n\tif (err) {\n\t\tPMD_INIT_LOG(ERR, \"init_adminq failed: %d\", err);\n\t\tgoto err;\n\t}\n\n\n\t/* Reset VF and wait until it's complete */\n\tif (i40evf_reset_vf(hw)) {\n\t\tPMD_INIT_LOG(ERR, \"reset NIC failed\");\n\t\tgoto err_aq;\n\t}\n\n\t/* VF reset, shutdown admin queue and initialize again */\n\tif (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"i40e_shutdown_adminq failed\");\n\t\treturn -1;\n\t}\n\n\ti40e_init_adminq_parameter(hw);\n\tif (i40e_init_adminq(hw) != I40E_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"init_adminq failed\");\n\t\treturn -1;\n\t}\n\tif (i40evf_check_api_version(dev) != 0) {\n\t\tPMD_INIT_LOG(ERR, \"check_api version failed\");\n\t\tgoto err_aq;\n\t}\n\tbufsz = sizeof(struct i40e_virtchnl_vf_resource) +\n\t\t(I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));\n\tvf->vf_res = rte_zmalloc(\"vf_res\", bufsz, 0);\n\tif (!vf->vf_res) {\n\t\tPMD_INIT_LOG(ERR, \"unable to allocate vf_res memory\");\n\t\t\tgoto err_aq;\n\t}\n\n\tif (i40evf_get_vf_resource(dev) != 0) {\n\t\tPMD_INIT_LOG(ERR, \"i40evf_get_vf_config failed\");\n\t\tgoto err_alloc;\n\t}\n\n\t/* got VF config message back from PF, now we can parse it */\n\tfor (i = 0; i < vf->vf_res->num_vsis; i++) {\n\t\tif (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)\n\t\t\tvf->vsi_res = &vf->vf_res->vsi_res[i];\n\t}\n\n\tif (!vf->vsi_res) {\n\t\tPMD_INIT_LOG(ERR, \"no LAN VSI found\");\n\t\tgoto err_alloc;\n\t}\n\n\tvf->vsi.vsi_id = vf->vsi_res->vsi_id;\n\tvf->vsi.type = vf->vsi_res->vsi_type;\n\tvf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;\n\n\t/* check mac addr, if it's not valid, genrate one */\n\tif (I40E_SUCCESS != i40e_validate_mac_addr(\\\n\t\t\tvf->vsi_res->default_mac_addr))\n\t\teth_random_addr(vf->vsi_res->default_mac_addr);\n\n\tether_addr_copy((struct ether_addr *)vf->vsi_res->default_mac_addr,\n\t\t\t\t\t(struct ether_addr *)hw->mac.addr);\n\n\treturn 0;\n\nerr_alloc:\n\trte_free(vf->vf_res);\nerr_aq:\n\ti40e_shutdown_adminq(hw); /* ignore error */\nerr:\n\treturn -1;\n}\n\nstatic int\ni40evf_uninit_vf(struct rte_eth_dev *dev)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (hw->adapter_stopped == 0)\n\t\ti40evf_dev_close(dev);\n\trte_free(vf->vf_res);\n\tvf->vf_res = NULL;\n\n\treturn 0;\n}\n\nstatic int\ni40evf_dev_init(struct rte_eth_dev *eth_dev)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(\\\n\t\t\teth_dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* assign ops func pointer */\n\teth_dev->dev_ops = &i40evf_eth_dev_ops;\n\teth_dev->rx_pkt_burst = &i40e_recv_pkts;\n\teth_dev->tx_pkt_burst = &i40e_xmit_pkts;\n\n\t/*\n\t * For secondary processes, we don't initialise any further as primary\n\t * has already done this work.\n\t */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY){\n\t\tif (eth_dev->data->scattered_rx)\n\t\t\teth_dev->rx_pkt_burst = i40e_recv_scattered_pkts;\n\t\treturn 0;\n\t}\n\n\thw->vendor_id = eth_dev->pci_dev->id.vendor_id;\n\thw->device_id = eth_dev->pci_dev->id.device_id;\n\thw->subsystem_vendor_id = eth_dev->pci_dev->id.subsystem_vendor_id;\n\thw->subsystem_device_id = eth_dev->pci_dev->id.subsystem_device_id;\n\thw->bus.device = eth_dev->pci_dev->addr.devid;\n\thw->bus.func = eth_dev->pci_dev->addr.function;\n\thw->hw_addr = (void *)eth_dev->pci_dev->mem_resource[0].addr;\n\thw->adapter_stopped = 0;\n\n\tif(i40evf_init_vf(eth_dev) != 0) {\n\t\tPMD_INIT_LOG(ERR, \"Init vf failed\");\n\t\treturn -1;\n\t}\n\n\t/* copy mac addr */\n\teth_dev->data->mac_addrs = rte_zmalloc(\"i40evf_mac\",\n\t\t\t\t\tETHER_ADDR_LEN, 0);\n\tif (eth_dev->data->mac_addrs == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to allocate %d bytes needed to \"\n\t\t\t\t\"store MAC addresses\", ETHER_ADDR_LEN);\n\t\treturn -ENOMEM;\n\t}\n\tether_addr_copy((struct ether_addr *)hw->mac.addr,\n\t\t(struct ether_addr *)eth_dev->data->mac_addrs);\n\n\treturn 0;\n}\n\nstatic int\ni40evf_dev_uninit(struct rte_eth_dev *eth_dev)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn -EPERM;\n\n\teth_dev->dev_ops = NULL;\n\teth_dev->rx_pkt_burst = NULL;\n\teth_dev->tx_pkt_burst = NULL;\n\n\tif (i40evf_uninit_vf(eth_dev) != 0) {\n\t\tPMD_INIT_LOG(ERR, \"i40evf_uninit_vf failed\");\n\t\treturn -1;\n\t}\n\n\trte_free(eth_dev->data->mac_addrs);\n\teth_dev->data->mac_addrs = NULL;\n\n\treturn 0;\n}\n/*\n * virtual function driver struct\n */\nstatic struct eth_driver rte_i40evf_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_i40evf_pmd\",\n\t\t.id_table = pci_id_i40evf_map,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,\n\t},\n\t.eth_dev_init = i40evf_dev_init,\n\t.eth_dev_uninit = i40evf_dev_uninit,\n\t.dev_private_size = sizeof(struct i40e_adapter),\n};\n\n/*\n * VF Driver initialization routine.\n * Invoked one at EAL init time.\n * Register itself as the [Virtual Poll Mode] Driver of PCI Fortville devices.\n */\nstatic int\nrte_i40evf_pmd_init(const char *name __rte_unused,\n\t\t const char *params __rte_unused)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\trte_eth_driver_register(&rte_i40evf_pmd);\n\n\treturn 0;\n}\n\nstatic struct rte_driver rte_i40evf_driver = {\n\t.type = PMD_PDEV,\n\t.init = rte_i40evf_pmd_init,\n};\n\nPMD_REGISTER_DRIVER(rte_i40evf_driver);\n\nstatic int\ni40evf_dev_configure(struct rte_eth_dev *dev)\n{\n\treturn i40evf_init_vlan(dev);\n}\n\nstatic int\ni40evf_init_vlan(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_dev_data *data = dev->data;\n\tint ret;\n\n\t/* Apply vlan offload setting */\n\ti40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);\n\n\t/* Apply pvid setting */\n\tret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,\n\t\t\t\tdata->dev_conf.txmode.hw_vlan_insert_pvid);\n\treturn ret;\n}\n\nstatic void\ni40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)\n{\n\tbool enable_vlan_strip = 0;\n\tstruct rte_eth_conf *dev_conf = &dev->data->dev_conf;\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\n\t/* Linux pf host doesn't support vlan offload yet */\n\tif (vf->version_major == I40E_DPDK_VERSION_MAJOR) {\n\t\t/* Vlan stripping setting */\n\t\tif (mask & ETH_VLAN_STRIP_MASK) {\n\t\t\t/* Enable or disable VLAN stripping */\n\t\t\tif (dev_conf->rxmode.hw_vlan_strip)\n\t\t\t\tenable_vlan_strip = 1;\n\t\t\telse\n\t\t\t\tenable_vlan_strip = 0;\n\n\t\t\ti40evf_config_vlan_offload(dev, enable_vlan_strip);\n\t\t}\n\t}\n}\n\nstatic int\ni40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)\n{\n\tstruct rte_eth_conf *dev_conf = &dev->data->dev_conf;\n\tstruct i40e_vsi_vlan_pvid_info info;\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\n\tmemset(&info, 0, sizeof(info));\n\tinfo.on = on;\n\n\t/* Linux pf host don't support vlan offload yet */\n\tif (vf->version_major == I40E_DPDK_VERSION_MAJOR) {\n\t\tif (info.on)\n\t\t\tinfo.config.pvid = pvid;\n\t\telse {\n\t\t\tinfo.config.reject.tagged =\n\t\t\t\tdev_conf->txmode.hw_vlan_reject_tagged;\n\t\t\tinfo.config.reject.untagged =\n\t\t\t\tdev_conf->txmode.hw_vlan_reject_untagged;\n\t\t}\n\t\treturn i40evf_config_vlan_pvid(dev, &info);\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n{\n\tstruct i40e_rx_queue *rxq;\n\tint err = 0;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rx_queue_id < dev->data->nb_rx_queues) {\n\t\trxq = dev->data->rx_queues[rx_queue_id];\n\n\t\terr = i40e_alloc_rx_queue_mbufs(rxq);\n\t\tif (err) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX queue mbuf\");\n\t\t\treturn err;\n\t\t}\n\n\t\trte_wmb();\n\n\t\t/* Init the RX tail register. */\n\t\tI40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);\n\t\tI40EVF_WRITE_FLUSH(hw);\n\n\t\t/* Ready to switch the queue on */\n\t\terr = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);\n\n\t\tif (err)\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch RX queue %u on\",\n\t\t\t\t rx_queue_id);\n\t}\n\n\treturn err;\n}\n\nstatic int\ni40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n{\n\tstruct i40e_rx_queue *rxq;\n\tint err;\n\n\tif (rx_queue_id < dev->data->nb_rx_queues) {\n\t\trxq = dev->data->rx_queues[rx_queue_id];\n\n\t\terr = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);\n\n\t\tif (err) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch RX queue %u off\",\n\t\t\t\t rx_queue_id);\n\t\t\treturn err;\n\t\t}\n\n\t\ti40e_rx_queue_release_mbufs(rxq);\n\t\ti40e_reset_rx_queue(rxq);\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n{\n\tint err = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (tx_queue_id < dev->data->nb_tx_queues) {\n\n\t\t/* Ready to switch the queue on */\n\t\terr = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);\n\n\t\tif (err)\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch TX queue %u on\",\n\t\t\t\t tx_queue_id);\n\t}\n\n\treturn err;\n}\n\nstatic int\ni40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n{\n\tstruct i40e_tx_queue *txq;\n\tint err;\n\n\tif (tx_queue_id < dev->data->nb_tx_queues) {\n\t\ttxq = dev->data->tx_queues[tx_queue_id];\n\n\t\terr = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);\n\n\t\tif (err) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch TX queue %u off\",\n\t\t\t\t tx_queue_id);\n\t\t\treturn err;\n\t\t}\n\n\t\ti40e_tx_queue_release_mbufs(txq);\n\t\ti40e_reset_tx_queue(txq);\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n{\n\tint ret;\n\n\tif (on)\n\t\tret = i40evf_add_vlan(dev, vlan_id);\n\telse\n\t\tret = i40evf_del_vlan(dev,vlan_id);\n\n\treturn ret;\n}\n\nstatic int\ni40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct rte_eth_dev_data *dev_data = dev->data;\n\tstruct rte_pktmbuf_pool_private *mbp_priv;\n\tuint16_t buf_size, len;\n\n\trxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);\n\tI40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);\n\tI40EVF_WRITE_FLUSH(hw);\n\n\t/* Calculate the maximum packet length allowed */\n\tmbp_priv = rte_mempool_get_priv(rxq->mp);\n\tbuf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -\n\t\t\t\t\tRTE_PKTMBUF_HEADROOM);\n\trxq->hs_mode = i40e_header_split_none;\n\trxq->rx_hdr_len = 0;\n\trxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));\n\tlen = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;\n\trxq->max_pkt_len = RTE_MIN(len,\n\t\tdev_data->dev_conf.rxmode.max_rx_pkt_len);\n\n\t/**\n\t * Check if the jumbo frame and maximum packet length are set correctly\n\t */\n\tif (dev_data->dev_conf.rxmode.jumbo_frame == 1) {\n\t\tif (rxq->max_pkt_len <= ETHER_MAX_LEN ||\n\t\t rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {\n\t\t\tPMD_DRV_LOG(ERR, \"maximum packet length must be \"\n\t\t\t\t\"larger than %u and smaller than %u, as jumbo \"\n\t\t\t\t\"frame is enabled\", (uint32_t)ETHER_MAX_LEN,\n\t\t\t\t\t(uint32_t)I40E_FRAME_SIZE_MAX);\n\t\t\treturn I40E_ERR_CONFIG;\n\t\t}\n\t} else {\n\t\tif (rxq->max_pkt_len < ETHER_MIN_LEN ||\n\t\t rxq->max_pkt_len > ETHER_MAX_LEN) {\n\t\t\tPMD_DRV_LOG(ERR, \"maximum packet length must be \"\n\t\t\t\t\"larger than %u and smaller than %u, as jumbo \"\n\t\t\t\t\"frame is disabled\", (uint32_t)ETHER_MIN_LEN,\n\t\t\t\t\t\t(uint32_t)ETHER_MAX_LEN);\n\t\t\treturn I40E_ERR_CONFIG;\n\t\t}\n\t}\n\n\tif (dev_data->dev_conf.rxmode.enable_scatter ||\n\t (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {\n\t\tdev_data->scattered_rx = 1;\n\t\tdev->rx_pkt_burst = i40e_recv_scattered_pkts;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40evf_rx_init(struct rte_eth_dev *dev)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tuint16_t i;\n\tstruct i40e_rx_queue **rxq =\n\t\t(struct i40e_rx_queue **)dev->data->rx_queues;\n\n\ti40evf_config_rss(vf);\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tif (!rxq[i] || !rxq[i]->q_set)\n\t\t\tcontinue;\n\t\tif (i40evf_rxq_init(dev, rxq[i]) < 0)\n\t\t\treturn -EFAULT;\n\t}\n\n\treturn 0;\n}\n\nstatic void\ni40evf_tx_init(struct rte_eth_dev *dev)\n{\n\tuint16_t i;\n\tstruct i40e_tx_queue **txq =\n\t\t(struct i40e_tx_queue **)dev->data->tx_queues;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n\t\ttxq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);\n}\n\nstatic inline void\ni40evf_enable_queues_intr(struct i40e_hw *hw)\n{\n\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),\n\t\t\tI40E_VFINT_DYN_CTLN1_INTENA_MASK |\n\t\t\tI40E_VFINT_DYN_CTLN_CLEARPBA_MASK);\n}\n\nstatic inline void\ni40evf_disable_queues_intr(struct i40e_hw *hw)\n{\n\tI40E_WRITE_REG(hw, I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),\n\t\t\t0);\n}\n\nstatic int\ni40evf_dev_start(struct rte_eth_dev *dev)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ether_addr mac_addr;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\thw->adapter_stopped = 0;\n\n\tvf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;\n\tvf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,\n\t\t\t\t\tdev->data->nb_tx_queues);\n\n\tif (i40evf_rx_init(dev) != 0){\n\t\tPMD_DRV_LOG(ERR, \"failed to do RX init\");\n\t\treturn -1;\n\t}\n\n\ti40evf_tx_init(dev);\n\n\tif (i40evf_configure_queues(dev) != 0) {\n\t\tPMD_DRV_LOG(ERR, \"configure queues failed\");\n\t\tgoto err_queue;\n\t}\n\tif (i40evf_config_irq_map(dev)) {\n\t\tPMD_DRV_LOG(ERR, \"config_irq_map failed\");\n\t\tgoto err_queue;\n\t}\n\n\t/* Set mac addr */\n\t(void)rte_memcpy(mac_addr.addr_bytes, hw->mac.addr,\n\t\t\t\tsizeof(mac_addr.addr_bytes));\n\tif (i40evf_add_mac_addr(dev, &mac_addr)) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to add mac addr\");\n\t\tgoto err_queue;\n\t}\n\n\tif (i40evf_start_queues(dev) != 0) {\n\t\tPMD_DRV_LOG(ERR, \"enable queues failed\");\n\t\tgoto err_mac;\n\t}\n\n\ti40evf_enable_queues_intr(hw);\n\treturn 0;\n\nerr_mac:\n\ti40evf_del_mac_addr(dev, &mac_addr);\nerr_queue:\n\treturn -1;\n}\n\nstatic void\ni40evf_dev_stop(struct rte_eth_dev *dev)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\ti40evf_disable_queues_intr(hw);\n\ti40evf_stop_queues(dev);\n\ti40e_dev_clear_queues(dev);\n}\n\nstatic int\ni40evf_dev_link_update(struct rte_eth_dev *dev,\n\t\t __rte_unused int wait_to_complete)\n{\n\tstruct rte_eth_link new_link;\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\t/*\n\t * DPDK pf host provide interfacet to acquire link status\n\t * while Linux driver does not\n\t */\n\tif (vf->version_major == I40E_DPDK_VERSION_MAJOR)\n\t\ti40evf_get_link_status(dev, &new_link);\n\telse {\n\t\t/* Always assume it's up, for Linux driver PF host */\n\t\tnew_link.link_duplex = ETH_LINK_AUTONEG_DUPLEX;\n\t\tnew_link.link_speed = ETH_LINK_SPEED_10000;\n\t\tnew_link.link_status = 1;\n\t}\n\ti40evf_dev_atomic_write_link_status(dev, &new_link);\n\n\treturn 0;\n}\n\nstatic void\ni40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tint ret;\n\n\t/* If enabled, just return */\n\tif (vf->promisc_unicast_enabled)\n\t\treturn;\n\n\tret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);\n\tif (ret == 0)\n\t\tvf->promisc_unicast_enabled = TRUE;\n}\n\nstatic void\ni40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tint ret;\n\n\t/* If disabled, just return */\n\tif (!vf->promisc_unicast_enabled)\n\t\treturn;\n\n\tret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);\n\tif (ret == 0)\n\t\tvf->promisc_unicast_enabled = FALSE;\n}\n\nstatic void\ni40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tint ret;\n\n\t/* If enabled, just return */\n\tif (vf->promisc_multicast_enabled)\n\t\treturn;\n\n\tret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);\n\tif (ret == 0)\n\t\tvf->promisc_multicast_enabled = TRUE;\n}\n\nstatic void\ni40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\tint ret;\n\n\t/* If enabled, just return */\n\tif (!vf->promisc_multicast_enabled)\n\t\treturn;\n\n\tret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);\n\tif (ret == 0)\n\t\tvf->promisc_multicast_enabled = FALSE;\n}\n\nstatic void\ni40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n{\n\tstruct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\n\tmemset(dev_info, 0, sizeof(*dev_info));\n\tdev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;\n\tdev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;\n\tdev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;\n\tdev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;\n\tdev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);\n\tdev_info->reta_size = ETH_RSS_RETA_SIZE_64;\n\tdev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;\n\tdev_info->rx_offload_capa =\n\t\tDEV_RX_OFFLOAD_VLAN_STRIP |\n\t\tDEV_RX_OFFLOAD_QINQ_STRIP |\n\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n\t\tDEV_RX_OFFLOAD_TCP_CKSUM;\n\tdev_info->tx_offload_capa =\n\t\tDEV_TX_OFFLOAD_VLAN_INSERT |\n\t\tDEV_TX_OFFLOAD_QINQ_INSERT |\n\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n\t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n\t\tDEV_TX_OFFLOAD_SCTP_CKSUM;\n\n\tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n\t\t.rx_thresh = {\n\t\t\t.pthresh = I40E_DEFAULT_RX_PTHRESH,\n\t\t\t.hthresh = I40E_DEFAULT_RX_HTHRESH,\n\t\t\t.wthresh = I40E_DEFAULT_RX_WTHRESH,\n\t\t},\n\t\t.rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,\n\t\t.rx_drop_en = 0,\n\t};\n\n\tdev_info->default_txconf = (struct rte_eth_txconf) {\n\t\t.tx_thresh = {\n\t\t\t.pthresh = I40E_DEFAULT_TX_PTHRESH,\n\t\t\t.hthresh = I40E_DEFAULT_TX_HTHRESH,\n\t\t\t.wthresh = I40E_DEFAULT_TX_WTHRESH,\n\t\t},\n\t\t.tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,\n\t\t.tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,\n\t\t.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |\n\t\t\t\tETH_TXQ_FLAGS_NOOFFLOADS,\n\t};\n}\n\nstatic void\ni40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tif (i40evf_get_statics(dev, stats))\n\t\tPMD_DRV_LOG(ERR, \"Get statics failed\");\n}\n\nstatic void\ni40evf_dev_close(struct rte_eth_dev *dev)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\ti40evf_dev_stop(dev);\n\thw->adapter_stopped = 1;\n\ti40e_dev_free_queues(dev);\n\ti40evf_reset_vf(hw);\n\ti40e_shutdown_adminq(hw);\n}\n\nstatic int\ni40evf_dev_rss_reta_update(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t uint16_t reta_size)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t lut, l;\n\tuint16_t i, j;\n\tuint16_t idx, shift;\n\tuint8_t mask;\n\n\tif (reta_size != ETH_RSS_RETA_SIZE_64) {\n\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n\t\t\t\"(%d) doesn't match the number of hardware can \"\n\t\t\t\"support (%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_64);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {\n\t\tidx = i / RTE_RETA_GROUP_SIZE;\n\t\tshift = i % RTE_RETA_GROUP_SIZE;\n\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n\t\t\t\t\t\tI40E_4_BIT_MASK);\n\t\tif (!mask)\n\t\t\tcontinue;\n\t\tif (mask == I40E_4_BIT_MASK)\n\t\t\tl = 0;\n\t\telse\n\t\t\tl = I40E_READ_REG(hw, I40E_VFQF_HLUT(i >> 2));\n\n\t\tfor (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {\n\t\t\tif (mask & (0x1 << j))\n\t\t\t\tlut |= reta_conf[idx].reta[shift + j] <<\n\t\t\t\t\t\t\t(CHAR_BIT * j);\n\t\t\telse\n\t\t\t\tlut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));\n\t\t}\n\t\tI40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40evf_dev_rss_reta_query(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t uint16_t reta_size)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t lut;\n\tuint16_t i, j;\n\tuint16_t idx, shift;\n\tuint8_t mask;\n\n\tif (reta_size != ETH_RSS_RETA_SIZE_64) {\n\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n\t\t\t\"(%d) doesn't match the number of hardware can \"\n\t\t\t\"support (%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_64);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {\n\t\tidx = i / RTE_RETA_GROUP_SIZE;\n\t\tshift = i % RTE_RETA_GROUP_SIZE;\n\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n\t\t\t\t\t\tI40E_4_BIT_MASK);\n\t\tif (!mask)\n\t\t\tcontinue;\n\n\t\tlut = I40E_READ_REG(hw, I40E_VFQF_HLUT(i >> 2));\n\t\tfor (j = 0; j < I40E_4_BIT_WIDTH; j++) {\n\t\t\tif (mask & (0x1 << j))\n\t\t\t\treta_conf[idx].reta[shift + j] =\n\t\t\t\t\t((lut >> (CHAR_BIT * j)) &\n\t\t\t\t\t\tI40E_8_BIT_MASK);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\ni40evf_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)\n{\n\tuint32_t *hash_key;\n\tuint8_t hash_key_len;\n\tuint64_t rss_hf, hena;\n\n\thash_key = (uint32_t *)(rss_conf->rss_key);\n\thash_key_len = rss_conf->rss_key_len;\n\tif (hash_key != NULL && hash_key_len >=\n\t\t(I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {\n\t\tuint16_t i;\n\n\t\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n\t\t\tI40E_WRITE_REG(hw, I40E_VFQF_HKEY(i), hash_key[i]);\n\t}\n\n\trss_hf = rss_conf->rss_hf;\n\thena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));\n\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;\n\thena &= ~I40E_RSS_HENA_ALL;\n\thena |= i40e_config_hena(rss_hf);\n\tI40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena);\n\tI40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));\n\tI40EVF_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\nstatic void\ni40evf_disable_rss(struct i40e_vf *vf)\n{\n\tstruct i40e_hw *hw = I40E_VF_TO_HW(vf);\n\tuint64_t hena;\n\n\thena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));\n\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;\n\thena &= ~I40E_RSS_HENA_ALL;\n\tI40E_WRITE_REG(hw, I40E_VFQF_HENA(0), (uint32_t)hena);\n\tI40E_WRITE_REG(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));\n\tI40EVF_WRITE_FLUSH(hw);\n}\n\nstatic int\ni40evf_config_rss(struct i40e_vf *vf)\n{\n\tstruct i40e_hw *hw = I40E_VF_TO_HW(vf);\n\tstruct rte_eth_rss_conf rss_conf;\n\tuint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;\n\tuint16_t num;\n\n\tif (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {\n\t\ti40evf_disable_rss(vf);\n\t\tPMD_DRV_LOG(DEBUG, \"RSS not configured\\n\");\n\t\treturn 0;\n\t}\n\n\tnum = i40e_align_floor(vf->dev_data->nb_rx_queues);\n\t/* Fill out the look up table */\n\tfor (i = 0, j = 0; i < nb_q; i++, j++) {\n\t\tif (j >= num)\n\t\t\tj = 0;\n\t\tlut = (lut << 8) | j;\n\t\tif ((i & 3) == 3)\n\t\t\tI40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);\n\t}\n\n\trss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;\n\tif ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {\n\t\ti40evf_disable_rss(vf);\n\t\tPMD_DRV_LOG(DEBUG, \"No hash flag is set\\n\");\n\t\treturn 0;\n\t}\n\n\tif (rss_conf.rss_key == NULL || rss_conf.rss_key_len < nb_q) {\n\t\t/* Calculate the default hash key */\n\t\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n\t\t\trss_key_default[i] = (uint32_t)rte_rand();\n\t\trss_conf.rss_key = (uint8_t *)rss_key_default;\n\t\trss_conf.rss_key_len = nb_q;\n\t}\n\n\treturn i40evf_hw_rss_hash_set(hw, &rss_conf);\n}\n\nstatic int\ni40evf_dev_rss_hash_update(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_conf *rss_conf)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;\n\tuint64_t hena;\n\n\thena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));\n\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;\n\tif (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */\n\t\tif (rss_hf != 0) /* Enable RSS */\n\t\t\treturn -EINVAL;\n\t\treturn 0;\n\t}\n\n\t/* RSS enabled */\n\tif (rss_hf == 0) /* Disable RSS */\n\t\treturn -EINVAL;\n\n\treturn i40evf_hw_rss_hash_set(hw, rss_conf);\n}\n\nstatic int\ni40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_conf *rss_conf)\n{\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);\n\tuint64_t hena;\n\tuint16_t i;\n\n\tif (hash_key) {\n\t\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n\t\t\thash_key[i] = I40E_READ_REG(hw, I40E_VFQF_HKEY(i));\n\t\trss_conf->rss_key_len = i * sizeof(uint32_t);\n\t}\n\thena = (uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(0));\n\thena |= ((uint64_t)I40E_READ_REG(hw, I40E_VFQF_HENA(1))) << 32;\n\trss_conf->rss_hf = i40e_parse_hena(hena);\n\n\treturn 0;\n}\n" }, { "path": "drivers/net/i40e/i40e_fdir.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"i40e_logs.h\"\n#include \"base/i40e_type.h\"\n#include \"i40e_ethdev.h\"\n#include \"i40e_rxtx.h\"\n\n#define I40E_FDIR_MZ_NAME \"FDIR_MEMZONE\"\n#ifndef IPV6_ADDR_LEN\n#define IPV6_ADDR_LEN 16\n#endif\n\n#define I40E_FDIR_PKT_LEN 512\n#define I40E_FDIR_IP_DEFAULT_LEN 420\n#define I40E_FDIR_IP_DEFAULT_TTL 0x40\n#define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45\n#define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50\n#define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60300000\n#define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF\n#define I40E_FDIR_IPv6_PAYLOAD_LEN 380\n#define I40E_FDIR_UDP_DEFAULT_LEN 400\n\n/* Wait count and interval for fdir filter programming */\n#define I40E_FDIR_WAIT_COUNT 10\n#define I40E_FDIR_WAIT_INTERVAL_US 1000\n\n/* Wait count and interval for fdir filter flush */\n#define I40E_FDIR_FLUSH_RETRY 50\n#define I40E_FDIR_FLUSH_INTERVAL_MS 5\n\n#define I40E_COUNTER_PF 2\n/* Statistic counter index for one pf */\n#define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)\n#define I40E_MAX_FLX_SOURCE_OFF 480\n#define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50\n\n#define NONUSE_FLX_PIT_DEST_OFF 63\n#define NONUSE_FLX_PIT_FSIZE 1\n#define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \\\n\t(((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \\\n\t\tI40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \\\n\t(((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \\\n\t\t\tI40E_PRTQF_FLX_PIT_FSIZE_MASK) | \\\n\t((((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR) << \\\n\t\t\tI40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \\\n\t\t\tI40E_PRTQF_FLX_PIT_DEST_OFF_MASK))\n\n#define I40E_FDIR_FLOWS ( \\\n\t(1 << RTE_ETH_FLOW_FRAG_IPV4) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \\\n\t(1 << RTE_ETH_FLOW_FRAG_IPV6) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \\\n\t(1 << RTE_ETH_FLOW_L2_PAYLOAD))\n\n#define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))\n\nstatic int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq);\nstatic int i40e_check_fdir_flex_conf(\n\tconst struct rte_eth_fdir_flex_conf *conf);\nstatic void i40e_set_flx_pld_cfg(struct i40e_pf *pf,\n\t\t\t const struct rte_eth_flex_payload_cfg *cfg);\nstatic void i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,\n\t\tenum i40e_filter_pctype pctype,\n\t\tconst struct rte_eth_fdir_flex_mask *mask_cfg);\nstatic int i40e_fdir_construct_pkt(struct i40e_pf *pf,\n\t\t\t\t const struct rte_eth_fdir_input *fdir_input,\n\t\t\t\t unsigned char *raw_pkt);\nstatic int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,\n\t\t\t const struct rte_eth_fdir_filter *filter,\n\t\t\t bool add);\nstatic int i40e_fdir_filter_programming(struct i40e_pf *pf,\n\t\t\tenum i40e_filter_pctype pctype,\n\t\t\tconst struct rte_eth_fdir_filter *filter,\n\t\t\tbool add);\nstatic int i40e_fdir_flush(struct rte_eth_dev *dev);\nstatic void i40e_fdir_info_get(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_fdir_info *fdir);\nstatic void i40e_fdir_stats_get(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_fdir_stats *stat);\n\nstatic int\ni40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)\n{\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);\n\tstruct i40e_hmc_obj_rxq rx_ctx;\n\tint err = I40E_SUCCESS;\n\n\tmemset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));\n\t/* Init the RX queue in hardware */\n\trx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;\n\trx_ctx.hbuff = 0;\n\trx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;\n\trx_ctx.qlen = rxq->nb_rx_desc;\n#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n\trx_ctx.dsize = 1;\n#endif\n\trx_ctx.dtype = i40e_header_split_none;\n\trx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;\n\trx_ctx.rxmax = ETHER_MAX_LEN;\n\trx_ctx.tphrdesc_ena = 1;\n\trx_ctx.tphwdesc_ena = 1;\n\trx_ctx.tphdata_ena = 1;\n\trx_ctx.tphhead_ena = 1;\n\trx_ctx.lrxqthresh = 2;\n\trx_ctx.crcstrip = 0;\n\trx_ctx.l2tsel = 1;\n\trx_ctx.showiv = 1;\n\trx_ctx.prefena = 1;\n\n\terr = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);\n\tif (err != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to clear FDIR RX queue context.\");\n\t\treturn err;\n\t}\n\terr = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);\n\tif (err != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to set FDIR RX queue context.\");\n\t\treturn err;\n\t}\n\trxq->qrx_tail = hw->hw_addr +\n\t\tI40E_QRX_TAIL(rxq->vsi->base_queue);\n\n\trte_wmb();\n\t/* Init the RX tail regieter. */\n\tI40E_PCI_REG_WRITE(rxq->qrx_tail, 0);\n\tI40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);\n\n\treturn err;\n}\n\n/*\n * i40e_fdir_setup - reserve and initialize the Flow Director resources\n * @pf: board private structure\n */\nint\ni40e_fdir_setup(struct i40e_pf *pf)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tstruct i40e_vsi *vsi;\n\tint err = I40E_SUCCESS;\n\tchar z_name[RTE_MEMZONE_NAMESIZE];\n\tconst struct rte_memzone *mz = NULL;\n\tstruct rte_eth_dev *eth_dev = pf->adapter->eth_dev;\n\n\tif ((pf->flags & I40E_FLAG_FDIR) == 0) {\n\t\tPMD_INIT_LOG(ERR, \"HW doesn't support FDIR\");\n\t\treturn I40E_NOT_SUPPORTED;\n\t}\n\n\tPMD_DRV_LOG(INFO, \"FDIR HW Capabilities: num_filters_guaranteed = %u,\"\n\t\t\t\" num_filters_best_effort = %u.\",\n\t\t\thw->func_caps.fd_filters_guaranteed,\n\t\t\thw->func_caps.fd_filters_best_effort);\n\n\tvsi = pf->fdir.fdir_vsi;\n\tif (vsi) {\n\t\tPMD_DRV_LOG(INFO, \"FDIR initialization has been done.\");\n\t\treturn I40E_SUCCESS;\n\t}\n\t/* make new FDIR VSI */\n\tvsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);\n\tif (!vsi) {\n\t\tPMD_DRV_LOG(ERR, \"Couldn't create FDIR VSI.\");\n\t\treturn I40E_ERR_NO_AVAILABLE_VSI;\n\t}\n\tpf->fdir.fdir_vsi = vsi;\n\n\t/*Fdir tx queue setup*/\n\terr = i40e_fdir_setup_tx_resources(pf);\n\tif (err) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to setup FDIR TX resources.\");\n\t\tgoto fail_setup_tx;\n\t}\n\n\t/*Fdir rx queue setup*/\n\terr = i40e_fdir_setup_rx_resources(pf);\n\tif (err) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to setup FDIR RX resources.\");\n\t\tgoto fail_setup_rx;\n\t}\n\n\terr = i40e_tx_queue_init(pf->fdir.txq);\n\tif (err) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to do FDIR TX initialization.\");\n\t\tgoto fail_mem;\n\t}\n\n\t/* need switch on before dev start*/\n\terr = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);\n\tif (err) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to do fdir TX switch on.\");\n\t\tgoto fail_mem;\n\t}\n\n\t/* Init the rx queue in hardware */\n\terr = i40e_fdir_rx_queue_init(pf->fdir.rxq);\n\tif (err) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to do FDIR RX initialization.\");\n\t\tgoto fail_mem;\n\t}\n\n\t/* switch on rx queue */\n\terr = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);\n\tif (err) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to do FDIR RX switch on.\");\n\t\tgoto fail_mem;\n\t}\n\n\t/* reserve memory for the fdir programming packet */\n\tsnprintf(z_name, sizeof(z_name), \"%s_%s_%d\",\n\t\t\teth_dev->driver->pci_drv.name,\n\t\t\tI40E_FDIR_MZ_NAME,\n\t\t\teth_dev->data->port_id);\n\tmz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);\n\tif (!mz) {\n\t\tPMD_DRV_LOG(ERR, \"Cannot init memzone for \"\n\t\t\t\t \"flow director program packet.\");\n\t\terr = I40E_ERR_NO_MEMORY;\n\t\tgoto fail_mem;\n\t}\n\tpf->fdir.prg_pkt = mz->addr;\n#ifdef RTE_LIBRTE_XEN_DOM0\n\tpf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);\n#else\n\tpf->fdir.dma_addr = (uint64_t)mz->phys_addr;\n#endif\n\tpf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);\n\tPMD_DRV_LOG(INFO, \"FDIR setup successfully, with programming queue %u.\",\n\t\t vsi->base_queue);\n\treturn I40E_SUCCESS;\n\nfail_mem:\n\ti40e_dev_rx_queue_release(pf->fdir.rxq);\n\tpf->fdir.rxq = NULL;\nfail_setup_rx:\n\ti40e_dev_tx_queue_release(pf->fdir.txq);\n\tpf->fdir.txq = NULL;\nfail_setup_tx:\n\ti40e_vsi_release(vsi);\n\tpf->fdir.fdir_vsi = NULL;\n\treturn err;\n}\n\n/*\n * i40e_fdir_teardown - release the Flow Director resources\n * @pf: board private structure\n */\nvoid\ni40e_fdir_teardown(struct i40e_pf *pf)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tstruct i40e_vsi *vsi;\n\n\tvsi = pf->fdir.fdir_vsi;\n\tif (!vsi)\n\t\treturn;\n\ti40e_switch_tx_queue(hw, vsi->base_queue, FALSE);\n\ti40e_switch_rx_queue(hw, vsi->base_queue, FALSE);\n\ti40e_dev_rx_queue_release(pf->fdir.rxq);\n\tpf->fdir.rxq = NULL;\n\ti40e_dev_tx_queue_release(pf->fdir.txq);\n\tpf->fdir.txq = NULL;\n\ti40e_vsi_release(vsi);\n\tpf->fdir.fdir_vsi = NULL;\n}\n\n/* check whether the flow director table in empty */\nstatic inline int\ni40e_fdir_empty(struct i40e_hw *hw)\n{\n\tuint32_t guarant_cnt, best_cnt;\n\n\tguarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &\n\t\t\t\t I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>\n\t\t\t\t I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);\n\tbest_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &\n\t\t\t I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>\n\t\t\t I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);\n\tif (best_cnt + guarant_cnt > 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * Initialize the configuration about bytes stream extracted as flexible payload\n * and mask setting\n */\nstatic inline void\ni40e_init_flx_pld(struct i40e_pf *pf)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tuint8_t pctype;\n\tint i, index;\n\n\t/*\n\t * Define the bytes stream extracted as flexible payload in\n\t * field vector. By default, select 8 words from the beginning\n\t * of payload as flexible payload.\n\t */\n\tfor (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {\n\t\tindex = i * I40E_MAX_FLXPLD_FIED;\n\t\tpf->fdir.flex_set[index].src_offset = 0;\n\t\tpf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;\n\t\tpf->fdir.flex_set[index].dst_offset = 0;\n\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);\n\t\tI40E_WRITE_REG(hw,\n\t\t\tI40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/\n\t\tI40E_WRITE_REG(hw,\n\t\t\tI40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/\n\t}\n\n\t/* initialize the masks */\n\tfor (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;\n\t pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {\n\t\tif (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)pctype))\n\t\t\tcontinue;\n\t\tpf->fdir.flex_mask[pctype].word_mask = 0;\n\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);\n\t\tfor (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {\n\t\t\tpf->fdir.flex_mask[pctype].bitmask[i].offset = 0;\n\t\t\tpf->fdir.flex_mask[pctype].bitmask[i].mask = 0;\n\t\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);\n\t\t}\n\t}\n}\n\n#define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))\n\n#define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \\\n\tif ((flex_pit2).src_offset < \\\n\t\t(flex_pit1).src_offset + (flex_pit1).size) { \\\n\t\tPMD_DRV_LOG(ERR, \"src_offset should be not\" \\\n\t\t\t\" less than than previous offset\" \\\n\t\t\t\" + previous FSIZE.\"); \\\n\t\treturn -EINVAL; \\\n\t} \\\n} while (0)\n\n/*\n * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,\n * and the flex_pit will be sorted by it's src_offset value\n */\nstatic inline uint16_t\ni40e_srcoff_to_flx_pit(const uint16_t *src_offset,\n\t\t\tstruct i40e_fdir_flex_pit *flex_pit)\n{\n\tuint16_t src_tmp, size, num = 0;\n\tuint16_t i, k, j = 0;\n\n\twhile (j < I40E_FDIR_MAX_FLEX_LEN) {\n\t\tsize = 1;\n\t\tfor (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {\n\t\t\tif (src_offset[j + 1] == src_offset[j] + 1)\n\t\t\t\tsize++;\n\t\t\telse\n\t\t\t\tbreak;\n\t\t}\n\t\tsrc_tmp = src_offset[j] + 1 - size;\n\t\t/* the flex_pit need to be sort by src_offset */\n\t\tfor (i = 0; i < num; i++) {\n\t\t\tif (src_tmp < flex_pit[i].src_offset)\n\t\t\t\tbreak;\n\t\t}\n\t\t/* if insert required, move backward */\n\t\tfor (k = num; k > i; k--)\n\t\t\tflex_pit[k] = flex_pit[k - 1];\n\t\t/* insert */\n\t\tflex_pit[i].dst_offset = j + 1 - size;\n\t\tflex_pit[i].src_offset = src_tmp;\n\t\tflex_pit[i].size = size;\n\t\tj++;\n\t\tnum++;\n\t}\n\treturn num;\n}\n\n/* i40e_check_fdir_flex_payload -check flex payload configuration arguments */\nstatic inline int\ni40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)\n{\n\tstruct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];\n\tuint16_t num, i;\n\n\tfor (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {\n\t\tif (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {\n\t\t\tPMD_DRV_LOG(ERR, \"exceeds maxmial payload limit.\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\tmemset(flex_pit, 0, sizeof(flex_pit));\n\tnum = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);\n\tif (num > I40E_MAX_FLXPLD_FIED) {\n\t\tPMD_DRV_LOG(ERR, \"exceeds maxmial number of flex fields.\");\n\t\treturn -EINVAL;\n\t}\n\tfor (i = 0; i < num; i++) {\n\t\tif (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||\n\t\t\tflex_pit[i].src_offset & 0x01) {\n\t\t\tPMD_DRV_LOG(ERR, \"flexpayload should be measured\"\n\t\t\t\t\" in word\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tif (i != num - 1)\n\t\t\tI40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);\n\t}\n\treturn 0;\n}\n\n/*\n * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration\n * arguments are valid\n */\nstatic int\ni40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)\n{\n\tconst struct rte_eth_flex_payload_cfg *flex_cfg;\n\tconst struct rte_eth_fdir_flex_mask *flex_mask;\n\tuint16_t mask_tmp;\n\tuint8_t nb_bitmask;\n\tuint16_t i, j;\n\tint ret = 0;\n\n\tif (conf == NULL) {\n\t\tPMD_DRV_LOG(INFO, \"NULL pointer.\");\n\t\treturn -EINVAL;\n\t}\n\t/* check flexible payload setting configuration */\n\tif (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {\n\t\tPMD_DRV_LOG(ERR, \"invalid number of payload setting.\");\n\t\treturn -EINVAL;\n\t}\n\tfor (i = 0; i < conf->nb_payloads; i++) {\n\t\tflex_cfg = &conf->flex_set[i];\n\t\tif (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {\n\t\t\tPMD_DRV_LOG(ERR, \"invalid payload type.\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tret = i40e_check_fdir_flex_payload(flex_cfg);\n\t\tif (ret < 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"invalid flex payload arguments.\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\t/* check flex mask setting configuration */\n\tif (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {\n\t\tPMD_DRV_LOG(ERR, \"invalid number of flex masks.\");\n\t\treturn -EINVAL;\n\t}\n\tfor (i = 0; i < conf->nb_flexmasks; i++) {\n\t\tflex_mask = &conf->flex_mask[i];\n\t\tif (!I40E_VALID_FLOW(flex_mask->flow_type)) {\n\t\t\tPMD_DRV_LOG(WARNING, \"invalid flow type.\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tnb_bitmask = 0;\n\t\tfor (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {\n\t\t\tmask_tmp = I40E_WORD(flex_mask->mask[j],\n\t\t\t\t\t flex_mask->mask[j + 1]);\n\t\t\tif (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {\n\t\t\t\tnb_bitmask++;\n\t\t\t\tif (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {\n\t\t\t\t\tPMD_DRV_LOG(ERR, \" exceed maximal\"\n\t\t\t\t\t\t\" number of bitmasks.\");\n\t\t\t\t\treturn -EINVAL;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\n/*\n * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload\n * @pf: board private structure\n * @cfg: the rule how bytes stream is extracted as flexible payload\n */\nstatic void\ni40e_set_flx_pld_cfg(struct i40e_pf *pf,\n\t\t\t const struct rte_eth_flex_payload_cfg *cfg)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tstruct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];\n\tuint32_t flx_pit;\n\tuint16_t num, min_next_off; /* in words */\n\tuint8_t field_idx = 0;\n\tuint8_t layer_idx = 0;\n\tuint16_t i;\n\n\tif (cfg->type == RTE_ETH_L2_PAYLOAD)\n\t\tlayer_idx = I40E_FLXPLD_L2_IDX;\n\telse if (cfg->type == RTE_ETH_L3_PAYLOAD)\n\t\tlayer_idx = I40E_FLXPLD_L3_IDX;\n\telse if (cfg->type == RTE_ETH_L4_PAYLOAD)\n\t\tlayer_idx = I40E_FLXPLD_L4_IDX;\n\n\tmemset(flex_pit, 0, sizeof(flex_pit));\n\tnum = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);\n\n\tfor (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {\n\t\tfield_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;\n\t\t/* record the info in fdir structure */\n\t\tpf->fdir.flex_set[field_idx].src_offset =\n\t\t\tflex_pit[i].src_offset / sizeof(uint16_t);\n\t\tpf->fdir.flex_set[field_idx].size =\n\t\t\tflex_pit[i].size / sizeof(uint16_t);\n\t\tpf->fdir.flex_set[field_idx].dst_offset =\n\t\t\tflex_pit[i].dst_offset / sizeof(uint16_t);\n\t\tflx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,\n\t\t\t\tpf->fdir.flex_set[field_idx].size,\n\t\t\t\tpf->fdir.flex_set[field_idx].dst_offset);\n\n\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);\n\t}\n\tmin_next_off = pf->fdir.flex_set[field_idx].src_offset +\n\t\t\t\tpf->fdir.flex_set[field_idx].size;\n\n\tfor (; i < I40E_MAX_FLXPLD_FIED; i++) {\n\t\t/* set the non-used register obeying register's constrain */\n\t\tflx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,\n\t\t\t NONUSE_FLX_PIT_DEST_OFF);\n\t\tI40E_WRITE_REG(hw,\n\t\t\tI40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),\n\t\t\tflx_pit);\n\t\tmin_next_off++;\n\t}\n}\n\n/*\n * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload\n * @pf: board private structure\n * @pctype: packet classify type\n * @flex_masks: mask for flexible payload\n */\nstatic void\ni40e_set_flex_mask_on_pctype(struct i40e_pf *pf,\n\t\tenum i40e_filter_pctype pctype,\n\t\tconst struct rte_eth_fdir_flex_mask *mask_cfg)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tstruct i40e_fdir_flex_mask *flex_mask;\n\tuint32_t flxinset, fd_mask;\n\tuint16_t mask_tmp;\n\tuint8_t i, nb_bitmask = 0;\n\n\tflex_mask = &pf->fdir.flex_mask[pctype];\n\tmemset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));\n\tfor (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {\n\t\tmask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);\n\t\tif (mask_tmp != 0x0) {\n\t\t\tflex_mask->word_mask |=\n\t\t\t\tI40E_FLEX_WORD_MASK(i / sizeof(uint16_t));\n\t\t\tif (mask_tmp != UINT16_MAX) {\n\t\t\t\t/* set bit mask */\n\t\t\t\tflex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;\n\t\t\t\tflex_mask->bitmask[nb_bitmask].offset =\n\t\t\t\t\ti / sizeof(uint16_t);\n\t\t\t\tnb_bitmask++;\n\t\t\t}\n\t\t}\n\t}\n\t/* write mask to hw */\n\tflxinset = (flex_mask->word_mask <<\n\t\tI40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &\n\t\tI40E_PRTQF_FD_FLXINSET_INSET_MASK;\n\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);\n\n\tfor (i = 0; i < nb_bitmask; i++) {\n\t\tfd_mask = (flex_mask->bitmask[i].mask <<\n\t\t\tI40E_PRTQF_FD_MSK_MASK_SHIFT) &\n\t\t\tI40E_PRTQF_FD_MSK_MASK_MASK;\n\t\tfd_mask |= ((flex_mask->bitmask[i].offset +\n\t\t\tI40E_FLX_OFFSET_IN_FIELD_VECTOR) <<\n\t\t\tI40E_PRTQF_FD_MSK_OFFSET_SHIFT) &\n\t\t\tI40E_PRTQF_FD_MSK_OFFSET_MASK;\n\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);\n\t}\n}\n\n/*\n * Configure flow director related setting\n */\nint\ni40e_fdir_configure(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct rte_eth_fdir_flex_conf *conf;\n\tenum i40e_filter_pctype pctype;\n\tuint32_t val;\n\tuint8_t i;\n\tint ret = 0;\n\n\t/*\n\t* configuration need to be done before\n\t* flow director filters are added\n\t* If filters exist, flush them.\n\t*/\n\tif (i40e_fdir_empty(hw) < 0) {\n\t\tret = i40e_fdir_flush(dev);\n\t\tif (ret) {\n\t\t\tPMD_DRV_LOG(ERR, \"failed to flush fdir table.\");\n\t\t\treturn ret;\n\t\t}\n\t}\n\n\t/* enable FDIR filter */\n\tval = I40E_READ_REG(hw, I40E_PFQF_CTL_0);\n\tval |= I40E_PFQF_CTL_0_FD_ENA_MASK;\n\tI40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);\n\n\ti40e_init_flx_pld(pf); /* set flex config to default value */\n\n\tconf = &dev->data->dev_conf.fdir_conf.flex_conf;\n\tret = i40e_check_fdir_flex_conf(conf);\n\tif (ret < 0) {\n\t\tPMD_DRV_LOG(ERR, \" invalid configuration arguments.\");\n\t\treturn -EINVAL;\n\t}\n\t/* configure flex payload */\n\tfor (i = 0; i < conf->nb_payloads; i++)\n\t\ti40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);\n\t/* configure flex mask*/\n\tfor (i = 0; i < conf->nb_flexmasks; i++) {\n\t\tpctype = i40e_flowtype_to_pctype(conf->flex_mask[i].flow_type);\n\t\ti40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);\n\t}\n\n\treturn ret;\n}\n\nstatic inline void\ni40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,\n\t\t\t unsigned char *raw_pkt)\n{\n\tstruct ether_hdr *ether = (struct ether_hdr *)raw_pkt;\n\tstruct ipv4_hdr *ip;\n\tstruct ipv6_hdr *ip6;\n\tstatic const uint8_t next_proto[] = {\n\t\t[RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,\n\t\t[RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,\n\t\t[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,\n\t};\n\n\tswitch (fdir_input->flow_type) {\n\tcase RTE_ETH_FLOW_L2_PAYLOAD:\n\t\tether->ether_type = fdir_input->flow.l2_flow.ether_type;\n\t\tbreak;\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_TCP:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_UDP:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:\n\tcase RTE_ETH_FLOW_FRAG_IPV4:\n\t\tip = (struct ipv4_hdr *)(raw_pkt + sizeof(struct ether_hdr));\n\n\t\tether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);\n\t\tip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;\n\t\t/* set len to by default */\n\t\tip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);\n\t\tip->time_to_live = I40E_FDIR_IP_DEFAULT_TTL;\n\t\t/*\n\t\t * The source and destination fields in the transmitted packet\n\t\t * need to be presented in a reversed order with respect\n\t\t * to the expected received packets.\n\t\t */\n\t\tip->src_addr = fdir_input->flow.ip4_flow.dst_ip;\n\t\tip->dst_addr = fdir_input->flow.ip4_flow.src_ip;\n\t\tip->next_proto_id = next_proto[fdir_input->flow_type];\n\t\tbreak;\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_TCP:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_UDP:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:\n\tcase RTE_ETH_FLOW_FRAG_IPV6:\n\t\tip6 = (struct ipv6_hdr *)(raw_pkt + sizeof(struct ether_hdr));\n\n\t\tether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);\n\t\tip6->vtc_flow =\n\t\t\trte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW);\n\t\tip6->payload_len =\n\t\t\trte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);\n\t\tip6->hop_limits = I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;\n\n\t\t/*\n\t\t * The source and destination fields in the transmitted packet\n\t\t * need to be presented in a reversed order with respect\n\t\t * to the expected received packets.\n\t\t */\n\t\trte_memcpy(&(ip6->src_addr),\n\t\t\t &(fdir_input->flow.ipv6_flow.dst_ip),\n\t\t\t IPV6_ADDR_LEN);\n\t\trte_memcpy(&(ip6->dst_addr),\n\t\t\t &(fdir_input->flow.ipv6_flow.src_ip),\n\t\t\t IPV6_ADDR_LEN);\n\t\tip6->proto = next_proto[fdir_input->flow_type];\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unknown flow type %u.\",\n\t\t\t fdir_input->flow_type);\n\t\tbreak;\n\t}\n}\n\n\n/*\n * i40e_fdir_construct_pkt - construct packet based on fields in input\n * @pf: board private structure\n * @fdir_input: input set of the flow director entry\n * @raw_pkt: a packet to be constructed\n */\nstatic int\ni40e_fdir_construct_pkt(struct i40e_pf *pf,\n\t\t\t const struct rte_eth_fdir_input *fdir_input,\n\t\t\t unsigned char *raw_pkt)\n{\n\tunsigned char *payload, *ptr;\n\tstruct udp_hdr *udp;\n\tstruct tcp_hdr *tcp;\n\tstruct sctp_hdr *sctp;\n\tuint8_t size, dst = 0;\n\tuint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/\n\n\t/* fill the ethernet and IP head */\n\ti40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt);\n\n\t/* fill the L4 head */\n\tswitch (fdir_input->flow_type) {\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_UDP:\n\t\tudp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +\n\t\t\t\tsizeof(struct ipv4_hdr));\n\t\tpayload = (unsigned char *)udp + sizeof(struct udp_hdr);\n\t\t/*\n\t\t * The source and destination fields in the transmitted packet\n\t\t * need to be presented in a reversed order with respect\n\t\t * to the expected received packets.\n\t\t */\n\t\tudp->src_port = fdir_input->flow.udp4_flow.dst_port;\n\t\tudp->dst_port = fdir_input->flow.udp4_flow.src_port;\n\t\tudp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);\n\t\tbreak;\n\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_TCP:\n\t\ttcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +\n\t\t\t\t\t sizeof(struct ipv4_hdr));\n\t\tpayload = (unsigned char *)tcp + sizeof(struct tcp_hdr);\n\t\t/*\n\t\t * The source and destination fields in the transmitted packet\n\t\t * need to be presented in a reversed order with respect\n\t\t * to the expected received packets.\n\t\t */\n\t\ttcp->src_port = fdir_input->flow.tcp4_flow.dst_port;\n\t\ttcp->dst_port = fdir_input->flow.tcp4_flow.src_port;\n\t\ttcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;\n\t\tbreak;\n\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:\n\t\tsctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +\n\t\t\t\t\t sizeof(struct ipv4_hdr));\n\t\tpayload = (unsigned char *)sctp + sizeof(struct sctp_hdr);\n#ifdef RTE_NEXT_ABI\n\t\t/*\n\t\t * The source and destination fields in the transmitted packet\n\t\t * need to be presented in a reversed order with respect\n\t\t * to the expected received packets.\n\t\t */\n\t\tsctp->src_port = fdir_input->flow.sctp4_flow.dst_port;\n\t\tsctp->dst_port = fdir_input->flow.sctp4_flow.src_port;\n#endif\n\t\tsctp->tag = fdir_input->flow.sctp4_flow.verify_tag;\n\t\tbreak;\n\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:\n\tcase RTE_ETH_FLOW_FRAG_IPV4:\n\t\tpayload = raw_pkt + sizeof(struct ether_hdr) +\n\t\t\t sizeof(struct ipv4_hdr);\n\t\tset_idx = I40E_FLXPLD_L3_IDX;\n\t\tbreak;\n\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_UDP:\n\t\tudp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +\n\t\t\t\t\t sizeof(struct ipv6_hdr));\n\t\tpayload = (unsigned char *)udp + sizeof(struct udp_hdr);\n\t\t/*\n\t\t * The source and destination fields in the transmitted packet\n\t\t * need to be presented in a reversed order with respect\n\t\t * to the expected received packets.\n\t\t */\n\t\tudp->src_port = fdir_input->flow.udp6_flow.dst_port;\n\t\tudp->dst_port = fdir_input->flow.udp6_flow.src_port;\n\t\tudp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);\n\t\tbreak;\n\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_TCP:\n\t\ttcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +\n\t\t\t\t\t sizeof(struct ipv6_hdr));\n\t\tpayload = (unsigned char *)tcp + sizeof(struct tcp_hdr);\n\t\t/*\n\t\t * The source and destination fields in the transmitted packet\n\t\t * need to be presented in a reversed order with respect\n\t\t * to the expected received packets.\n\t\t */\n\t\ttcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;\n\t\ttcp->src_port = fdir_input->flow.udp6_flow.dst_port;\n\t\ttcp->dst_port = fdir_input->flow.udp6_flow.src_port;\n\t\tbreak;\n\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:\n\t\tsctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +\n\t\t\t\t\t sizeof(struct ipv6_hdr));\n\t\tpayload = (unsigned char *)sctp + sizeof(struct sctp_hdr);\n#ifdef RTE_NEXT_ABI\n\t\t/*\n\t\t * The source and destination fields in the transmitted packet\n\t\t * need to be presented in a reversed order with respect\n\t\t * to the expected received packets.\n\t\t */\n\t\tsctp->src_port = fdir_input->flow.sctp6_flow.dst_port;\n\t\tsctp->dst_port = fdir_input->flow.sctp6_flow.src_port;\n#endif\n\t\tsctp->tag = fdir_input->flow.sctp6_flow.verify_tag;\n\t\tbreak;\n\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:\n\tcase RTE_ETH_FLOW_FRAG_IPV6:\n\t\tpayload = raw_pkt + sizeof(struct ether_hdr) +\n\t\t\t sizeof(struct ipv6_hdr);\n\t\tset_idx = I40E_FLXPLD_L3_IDX;\n\t\tbreak;\n\tcase RTE_ETH_FLOW_L2_PAYLOAD:\n\t\tpayload = raw_pkt + sizeof(struct ether_hdr);\n\t\t/*\n\t\t * ARP packet is a special case on which the payload\n\t\t * starts after the whole ARP header\n\t\t */\n\t\tif (fdir_input->flow.l2_flow.ether_type ==\n\t\t\t\trte_cpu_to_be_16(ETHER_TYPE_ARP))\n\t\t\tpayload += sizeof(struct arp_hdr);\n\t\tset_idx = I40E_FLXPLD_L2_IDX;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unknown flow type %u.\", fdir_input->flow_type);\n\t\treturn -EINVAL;\n\t}\n\n\t/* fill the flexbytes to payload */\n\tfor (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {\n\t\tpit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;\n\t\tsize = pf->fdir.flex_set[pit_idx].size;\n\t\tif (size == 0)\n\t\t\tcontinue;\n\t\tdst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);\n\t\tptr = payload +\n\t\t\tpf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);\n\t\t(void)rte_memcpy(ptr,\n\t\t\t\t &fdir_input->flow_ext.flexbytes[dst],\n\t\t\t\t size * sizeof(uint16_t));\n\t}\n\n\treturn 0;\n}\n\n/* Construct the tx flags */\nstatic inline uint64_t\ni40e_build_ctob(uint32_t td_cmd,\n\t\tuint32_t td_offset,\n\t\tunsigned int size,\n\t\tuint32_t td_tag)\n{\n\treturn rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |\n\t\t\t((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |\n\t\t\t((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |\n\t\t\t((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |\n\t\t\t((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));\n}\n\n/*\n * check the programming status descriptor in rx queue.\n * done after Programming Flow Director is programmed on\n * tx queue\n */\nstatic inline int\ni40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)\n{\n\tvolatile union i40e_rx_desc *rxdp;\n\tuint64_t qword1;\n\tuint32_t rx_status;\n\tuint32_t len, id;\n\tuint32_t error;\n\tint ret = 0;\n\n\trxdp = &rxq->rx_ring[rxq->rx_tail];\n\tqword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);\n\trx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)\n\t\t\t>> I40E_RXD_QW1_STATUS_SHIFT;\n\n\tif (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {\n\t\tlen = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;\n\t\tid = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>\n\t\t\t I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;\n\n\t\tif (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&\n\t\t id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {\n\t\t\terror = (qword1 &\n\t\t\t\tI40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>\n\t\t\t\tI40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;\n\t\t\tif (error == (0x1 <<\n\t\t\t\tI40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {\n\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to add FDIR filter\"\n\t\t\t\t\t \" (FD_ID %u): programming status\"\n\t\t\t\t\t \" reported.\",\n\t\t\t\t\t rxdp->wb.qword0.hi_dword.fd_id);\n\t\t\t\tret = -1;\n\t\t\t} else if (error == (0x1 <<\n\t\t\t\tI40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {\n\t\t\t\tPMD_DRV_LOG(ERR, \"Failed to delete FDIR filter\"\n\t\t\t\t\t \" (FD_ID %u): programming status\"\n\t\t\t\t\t \" reported.\",\n\t\t\t\t\t rxdp->wb.qword0.hi_dword.fd_id);\n\t\t\t\tret = -1;\n\t\t\t} else\n\t\t\t\tPMD_DRV_LOG(ERR, \"invalid programming status\"\n\t\t\t\t\t \" reported, error = %u.\", error);\n\t\t} else\n\t\t\tPMD_DRV_LOG(ERR, \"unknown programming status\"\n\t\t\t\t \" reported, len = %d, id = %u.\", len, id);\n\t\trxdp->wb.qword1.status_error_len = 0;\n\t\trxq->rx_tail++;\n\t\tif (unlikely(rxq->rx_tail == rxq->nb_rx_desc))\n\t\t\trxq->rx_tail = 0;\n\t}\n\treturn ret;\n}\n\n/*\n * i40e_add_del_fdir_filter - add or remove a flow director filter.\n * @pf: board private structure\n * @filter: fdir filter entry\n * @add: 0 - delete, 1 - add\n */\nstatic int\ni40e_add_del_fdir_filter(struct rte_eth_dev *dev,\n\t\t\t const struct rte_eth_fdir_filter *filter,\n\t\t\t bool add)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tunsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;\n\tenum i40e_filter_pctype pctype;\n\tint ret = 0;\n\n\tif (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {\n\t\tPMD_DRV_LOG(ERR, \"FDIR is not enabled, please\"\n\t\t\t\" check the mode in fdir_conf.\");\n\t\treturn -ENOTSUP;\n\t}\n\n\tif (!I40E_VALID_FLOW(filter->input.flow_type)) {\n\t\tPMD_DRV_LOG(ERR, \"invalid flow_type input.\");\n\t\treturn -EINVAL;\n\t}\n\tif (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid queue ID\");\n\t\treturn -EINVAL;\n\t}\n\n\tmemset(pkt, 0, I40E_FDIR_PKT_LEN);\n\n\tret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);\n\tif (ret < 0) {\n\t\tPMD_DRV_LOG(ERR, \"construct packet for fdir fails.\");\n\t\treturn ret;\n\t}\n\tpctype = i40e_flowtype_to_pctype(filter->input.flow_type);\n\tret = i40e_fdir_filter_programming(pf, pctype, filter, add);\n\tif (ret < 0) {\n\t\tPMD_DRV_LOG(ERR, \"fdir programming fails for PCTYPE(%u).\",\n\t\t\t pctype);\n\t\treturn ret;\n\t}\n\treturn ret;\n}\n\n/*\n * i40e_fdir_filter_programming - Program a flow director filter rule.\n * Is done by Flow Director Programming Descriptor followed by packet\n * structure that contains the filter fields need to match.\n * @pf: board private structure\n * @pctype: pctype\n * @filter: fdir filter entry\n * @add: 0 - delelet, 1 - add\n */\nstatic int\ni40e_fdir_filter_programming(struct i40e_pf *pf,\n\t\t\tenum i40e_filter_pctype pctype,\n\t\t\tconst struct rte_eth_fdir_filter *filter,\n\t\t\tbool add)\n{\n\tstruct i40e_tx_queue *txq = pf->fdir.txq;\n\tstruct i40e_rx_queue *rxq = pf->fdir.rxq;\n\tconst struct rte_eth_fdir_action *fdir_action = &filter->action;\n\tvolatile struct i40e_tx_desc *txdp;\n\tvolatile struct i40e_filter_program_desc *fdirdp;\n\tuint32_t td_cmd;\n\tuint16_t i;\n\tuint8_t dest;\n\n\tPMD_DRV_LOG(INFO, \"filling filter programming descriptor.\");\n\tfdirdp = (volatile struct i40e_filter_program_desc *)\n\t\t\t(&(txq->tx_ring[txq->tx_tail]));\n\n\tfdirdp->qindex_flex_ptype_vsi =\n\t\t\trte_cpu_to_le_32((fdir_action->rx_queue <<\n\t\t\t\t\t I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &\n\t\t\t\t\t I40E_TXD_FLTR_QW0_QINDEX_MASK);\n\n\tfdirdp->qindex_flex_ptype_vsi |=\n\t\t\trte_cpu_to_le_32((fdir_action->flex_off <<\n\t\t\t\t\t I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &\n\t\t\t\t\t I40E_TXD_FLTR_QW0_FLEXOFF_MASK);\n\n\tfdirdp->qindex_flex_ptype_vsi |=\n\t\t\trte_cpu_to_le_32((pctype <<\n\t\t\t\t\t I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &\n\t\t\t\t\t I40E_TXD_FLTR_QW0_PCTYPE_MASK);\n\n\t/* Use LAN VSI Id by default */\n\tfdirdp->qindex_flex_ptype_vsi |=\n\t\trte_cpu_to_le_32((pf->main_vsi->vsi_id <<\n\t\t\t\t I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &\n\t\t\t\t I40E_TXD_FLTR_QW0_DEST_VSI_MASK);\n\n\tfdirdp->dtype_cmd_cntindex =\n\t\t\trte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);\n\n\tif (add)\n\t\tfdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(\n\t\t\t\tI40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<\n\t\t\t\tI40E_TXD_FLTR_QW1_PCMD_SHIFT);\n\telse\n\t\tfdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(\n\t\t\t\tI40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<\n\t\t\t\tI40E_TXD_FLTR_QW1_PCMD_SHIFT);\n\n\tif (fdir_action->behavior == RTE_ETH_FDIR_REJECT)\n\t\tdest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;\n\telse\n\t\tdest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;\n\tfdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<\n\t\t\t\tI40E_TXD_FLTR_QW1_DEST_SHIFT) &\n\t\t\t\tI40E_TXD_FLTR_QW1_DEST_MASK);\n\n\tfdirdp->dtype_cmd_cntindex |=\n\t\trte_cpu_to_le_32((fdir_action->report_status<<\n\t\t\t\tI40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &\n\t\t\t\tI40E_TXD_FLTR_QW1_FD_STATUS_MASK);\n\n\tfdirdp->dtype_cmd_cntindex |=\n\t\t\trte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);\n\tfdirdp->dtype_cmd_cntindex |=\n\t\t\trte_cpu_to_le_32((pf->fdir.match_counter_index <<\n\t\t\tI40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &\n\t\t\tI40E_TXD_FLTR_QW1_CNTINDEX_MASK);\n\n\tfdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);\n\n\tPMD_DRV_LOG(INFO, \"filling transmit descriptor.\");\n\ttxdp = &(txq->tx_ring[txq->tx_tail + 1]);\n\ttxdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);\n\ttd_cmd = I40E_TX_DESC_CMD_EOP |\n\t\t I40E_TX_DESC_CMD_RS |\n\t\t I40E_TX_DESC_CMD_DUMMY;\n\n\ttxdp->cmd_type_offset_bsz =\n\t\ti40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);\n\n\ttxq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */\n\tif (txq->tx_tail >= txq->nb_tx_desc)\n\t\ttxq->tx_tail = 0;\n\t/* Update the tx tail register */\n\trte_wmb();\n\tI40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);\n\n\tfor (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {\n\t\trte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);\n\t\tif ((txdp->cmd_type_offset_bsz &\n\t\t\t\trte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==\n\t\t\t\trte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))\n\t\t\tbreak;\n\t}\n\tif (i >= I40E_FDIR_WAIT_COUNT) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to program FDIR filter:\"\n\t\t\t \" time out to get DD on tx queue.\");\n\t\treturn -ETIMEDOUT;\n\t}\n\t/* totally delay 10 ms to check programming status*/\n\trte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);\n\tif (i40e_check_fdir_programming_status(rxq) < 0) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to program FDIR filter:\"\n\t\t\t \" programming status reported.\");\n\t\treturn -ENOSYS;\n\t}\n\n\treturn 0;\n}\n\n/*\n * i40e_fdir_flush - clear all filters of Flow Director table\n * @pf: board private structure\n */\nstatic int\ni40e_fdir_flush(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tuint32_t reg;\n\tuint16_t guarant_cnt, best_cnt;\n\tuint16_t i;\n\n\tI40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);\n\tI40E_WRITE_FLUSH(hw);\n\n\tfor (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {\n\t\trte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);\n\t\treg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);\n\t\tif (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))\n\t\t\tbreak;\n\t}\n\tif (i >= I40E_FDIR_FLUSH_RETRY) {\n\t\tPMD_DRV_LOG(ERR, \"FD table did not flush, may need more time.\");\n\t\treturn -ETIMEDOUT;\n\t}\n\tguarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &\n\t\t\t\tI40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>\n\t\t\t\tI40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);\n\tbest_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &\n\t\t\t\tI40E_PFQF_FDSTAT_BEST_CNT_MASK) >>\n\t\t\t\tI40E_PFQF_FDSTAT_BEST_CNT_SHIFT);\n\tif (guarant_cnt != 0 || best_cnt != 0) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to flush FD table.\");\n\t\treturn -ENOSYS;\n\t} else\n\t\tPMD_DRV_LOG(INFO, \"FD table Flush success.\");\n\treturn 0;\n}\n\nstatic inline void\ni40e_fdir_info_get_flex_set(struct i40e_pf *pf,\n\t\t\tstruct rte_eth_flex_payload_cfg *flex_set,\n\t\t\tuint16_t *num)\n{\n\tstruct i40e_fdir_flex_pit *flex_pit;\n\tstruct rte_eth_flex_payload_cfg *ptr = flex_set;\n\tuint16_t src, dst, size, j, k;\n\tuint8_t i, layer_idx;\n\n\tfor (layer_idx = I40E_FLXPLD_L2_IDX;\n\t layer_idx <= I40E_FLXPLD_L4_IDX;\n\t layer_idx++) {\n\t\tif (layer_idx == I40E_FLXPLD_L2_IDX)\n\t\t\tptr->type = RTE_ETH_L2_PAYLOAD;\n\t\telse if (layer_idx == I40E_FLXPLD_L3_IDX)\n\t\t\tptr->type = RTE_ETH_L3_PAYLOAD;\n\t\telse if (layer_idx == I40E_FLXPLD_L4_IDX)\n\t\t\tptr->type = RTE_ETH_L4_PAYLOAD;\n\n\t\tfor (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {\n\t\t\tflex_pit = &pf->fdir.flex_set[layer_idx *\n\t\t\t\tI40E_MAX_FLXPLD_FIED + i];\n\t\t\tif (flex_pit->size == 0)\n\t\t\t\tcontinue;\n\t\t\tsrc = flex_pit->src_offset * sizeof(uint16_t);\n\t\t\tdst = flex_pit->dst_offset * sizeof(uint16_t);\n\t\t\tsize = flex_pit->size * sizeof(uint16_t);\n\t\t\tfor (j = src, k = dst; j < src + size; j++, k++)\n\t\t\t\tptr->src_offset[k] = j;\n\t\t}\n\t\t(*num)++;\n\t\tptr++;\n\t}\n}\n\nstatic inline void\ni40e_fdir_info_get_flex_mask(struct i40e_pf *pf,\n\t\t\tstruct rte_eth_fdir_flex_mask *flex_mask,\n\t\t\tuint16_t *num)\n{\n\tstruct i40e_fdir_flex_mask *mask;\n\tstruct rte_eth_fdir_flex_mask *ptr = flex_mask;\n\tuint16_t flow_type;\n\tuint8_t i, j;\n\tuint16_t off_bytes, mask_tmp;\n\n\tfor (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;\n\t i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;\n\t i++) {\n\t\tmask = &pf->fdir.flex_mask[i];\n\t\tif (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))\n\t\t\tcontinue;\n\t\tflow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);\n\t\tfor (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {\n\t\t\tif (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {\n\t\t\t\tptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;\n\t\t\t\tptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;\n\t\t\t} else {\n\t\t\t\tptr->mask[j * sizeof(uint16_t)] = 0x0;\n\t\t\t\tptr->mask[j * sizeof(uint16_t) + 1] = 0x0;\n\t\t\t}\n\t\t}\n\t\tfor (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {\n\t\t\toff_bytes = mask->bitmask[j].offset * sizeof(uint16_t);\n\t\t\tmask_tmp = ~mask->bitmask[j].mask;\n\t\t\tptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);\n\t\t\tptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);\n\t\t}\n\t\tptr->flow_type = flow_type;\n\t\tptr++;\n\t\t(*num)++;\n\t}\n}\n\n/*\n * i40e_fdir_info_get - get information of Flow Director\n * @pf: ethernet device to get info from\n * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with\n * the flow director information.\n */\nstatic void\ni40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tuint16_t num_flex_set = 0;\n\tuint16_t num_flex_mask = 0;\n\n\tif (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)\n\t\tfdir->mode = RTE_FDIR_MODE_PERFECT;\n\telse\n\t\tfdir->mode = RTE_FDIR_MODE_NONE;\n\n\tfdir->guarant_spc =\n\t\t(uint32_t)hw->func_caps.fd_filters_guaranteed;\n\tfdir->best_spc =\n\t\t(uint32_t)hw->func_caps.fd_filters_best_effort;\n\tfdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;\n\tfdir->flow_types_mask[0] = I40E_FDIR_FLOWS;\n\tfdir->flex_payload_unit = sizeof(uint16_t);\n\tfdir->flex_bitmask_unit = sizeof(uint16_t);\n\tfdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;\n\tfdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;\n\tfdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;\n\n\ti40e_fdir_info_get_flex_set(pf,\n\t\t\t\tfdir->flex_conf.flex_set,\n\t\t\t\t&num_flex_set);\n\ti40e_fdir_info_get_flex_mask(pf,\n\t\t\t\tfdir->flex_conf.flex_mask,\n\t\t\t\t&num_flex_mask);\n\n\tfdir->flex_conf.nb_payloads = num_flex_set;\n\tfdir->flex_conf.nb_flexmasks = num_flex_mask;\n}\n\n/*\n * i40e_fdir_stat_get - get statistics of Flow Director\n * @pf: ethernet device to get info from\n * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with\n * the flow director statistics.\n */\nstatic void\ni40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tuint32_t fdstat;\n\n\tfdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);\n\tstat->guarant_cnt =\n\t\t(uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>\n\t\t\t I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);\n\tstat->best_cnt =\n\t\t(uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>\n\t\t\t I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);\n}\n\n/*\n * i40e_fdir_ctrl_func - deal with all operations on flow director.\n * @pf: board private structure\n * @filter_op:operation will be taken.\n * @arg: a pointer to specific structure corresponding to the filter_op\n */\nint\ni40e_fdir_ctrl_func(struct rte_eth_dev *dev,\n\t\t enum rte_filter_op filter_op,\n\t\t void *arg)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tint ret = 0;\n\n\tif ((pf->flags & I40E_FLAG_FDIR) == 0)\n\t\treturn -ENOTSUP;\n\n\tif (filter_op == RTE_ETH_FILTER_NOP)\n\t\treturn 0;\n\n\tif (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)\n\t\treturn -EINVAL;\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_ADD:\n\t\tret = i40e_add_del_fdir_filter(dev,\n\t\t\t(struct rte_eth_fdir_filter *)arg,\n\t\t\tTRUE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_DELETE:\n\t\tret = i40e_add_del_fdir_filter(dev,\n\t\t\t(struct rte_eth_fdir_filter *)arg,\n\t\t\tFALSE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_FLUSH:\n\t\tret = i40e_fdir_flush(dev);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_INFO:\n\t\ti40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_STATS:\n\t\ti40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unknown operation %u.\", filter_op);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\treturn ret;\n}\n" }, { "path": "drivers/net/i40e/i40e_logs.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _I40E_LOGS_H_\n#define _I40E_LOGS_H_\n\n#define PMD_INIT_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ##args)\n\n#ifdef RTE_LIBRTE_I40E_DEBUG_INIT\n#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, \" >>\")\n#else\n#define PMD_INIT_FUNC_TRACE() do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_I40E_DEBUG_RX\n#define PMD_RX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_RX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_I40E_DEBUG_TX\n#define PMD_TX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_TX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE\n#define PMD_TX_FREE_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_TX_FREE_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER\n#define PMD_DRV_LOG_RAW(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt, __func__, ## args)\n#else\n#define PMD_DRV_LOG_RAW(level, fmt, args...) do { } while (0)\n#endif\n\n#define PMD_DRV_LOG(level, fmt, args...) \\\n\tPMD_DRV_LOG_RAW(level, fmt \"\\n\", ## args)\n\n#endif /* _I40E_LOGS_H_ */\n" }, { "path": "drivers/net/i40e/i40e_pf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"i40e_logs.h\"\n#include \"base/i40e_prototype.h\"\n#include \"base/i40e_adminq_cmd.h\"\n#include \"base/i40e_type.h\"\n#include \"i40e_ethdev.h\"\n#include \"i40e_rxtx.h\"\n#include \"i40e_pf.h\"\n\n#define I40E_CFG_CRCSTRIP_DEFAULT 1\n\nstatic int\ni40e_pf_host_switch_queues(struct i40e_pf_vf *vf,\n\t\t\t struct i40e_virtchnl_queue_select *qsel,\n\t\t\t bool on);\n\n/**\n * Bind PF queues with VSI and VF.\n **/\nstatic int\ni40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)\n{\n\tint i;\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);\n\tuint16_t vsi_id = vf->vsi->vsi_id;\n\tuint16_t vf_id = vf->vf_idx;\n\tuint16_t nb_qps = vf->vsi->nb_qps;\n\tuint16_t qbase = vf->vsi->base_queue;\n\tuint16_t q1, q2;\n\tuint32_t val;\n\n\t/*\n\t * VF should use scatter range queues. So, it needn't\n\t * to set QBASE in this register.\n\t */\n\tI40E_WRITE_REG(hw, I40E_VSILAN_QBASE(vsi_id),\n\t I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);\n\n\t/* Set to enable VFLAN_QTABLE[] registers valid */\n\tI40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id),\n\t\tI40E_VPLAN_MAPENA_TXRX_ENA_MASK);\n\n\t/* map PF queues to VF */\n\tfor (i = 0; i < nb_qps; i++) {\n\t\tval = ((qbase + i) & I40E_VPLAN_QTABLE_QINDEX_MASK);\n\t\tI40E_WRITE_REG(hw, I40E_VPLAN_QTABLE(i, vf_id), val);\n\t}\n\n\t/* map PF queues to VSI */\n\tfor (i = 0; i < I40E_MAX_QP_NUM_PER_VF / 2; i++) {\n\t\tif (2 * i > nb_qps - 1)\n\t\t\tq1 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;\n\t\telse\n\t\t\tq1 = qbase + 2 * i;\n\n\t\tif (2 * i + 1 > nb_qps - 1)\n\t\t\tq2 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;\n\t\telse\n\t\t\tq2 = qbase + 2 * i + 1;\n\n\t\tval = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1;\n\t\tI40E_WRITE_REG(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);\n\t}\n\tI40E_WRITE_FLUSH(hw);\n\n\treturn I40E_SUCCESS;\n}\n\n\n/**\n * Proceed VF reset operation.\n */\nint\ni40e_pf_host_vf_reset(struct i40e_pf_vf *vf, bool do_hw_reset)\n{\n\tuint32_t val, i;\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);\n\tuint16_t vf_id, abs_vf_id, vf_msix_num;\n\tint ret;\n\tstruct i40e_virtchnl_queue_select qsel;\n\n\tif (vf == NULL)\n\t\treturn -EINVAL;\n\n\tvf_id = vf->vf_idx;\n\tabs_vf_id = vf_id + hw->func_caps.vf_base_id;\n\n\t/* Notify VF that we are in VFR progress */\n\tI40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), I40E_PF_VFR_INPROGRESS);\n\n\t/*\n\t * If require a SW VF reset, a VFLR interrupt will be generated,\n\t * this function will be called again. To avoid it,\n\t * disable interrupt first.\n\t */\n\tif (do_hw_reset) {\n\t\tvf->state = I40E_VF_INRESET;\n\t\tval = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));\n\t\tval |= I40E_VPGEN_VFRTRIG_VFSWR_MASK;\n\t\tI40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);\n\t\tI40E_WRITE_FLUSH(hw);\n\t}\n\n#define VFRESET_MAX_WAIT_CNT 100\n\t/* Wait until VF reset is done */\n\tfor (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {\n\t\trte_delay_us(10);\n\t\tval = I40E_READ_REG(hw, I40E_VPGEN_VFRSTAT(vf_id));\n\t\tif (val & I40E_VPGEN_VFRSTAT_VFRD_MASK)\n\t\t\tbreak;\n\t}\n\n\tif (i >= VFRESET_MAX_WAIT_CNT) {\n\t\tPMD_DRV_LOG(ERR, \"VF reset timeout\");\n\t\treturn -ETIMEDOUT;\n\t}\n\n\t/* This is not first time to do reset, do cleanup job first */\n\tif (vf->vsi) {\n\t\t/* Disable queues */\n\t\tmemset(&qsel, 0, sizeof(qsel));\n\t\tfor (i = 0; i < vf->vsi->nb_qps; i++)\n\t\t\tqsel.rx_queues |= 1 << i;\n\t\tqsel.tx_queues = qsel.rx_queues;\n\t\tret = i40e_pf_host_switch_queues(vf, &qsel, false);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Disable VF queues failed\");\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\t/* Disable VF interrupt setting */\n\t\tvf_msix_num = hw->func_caps.num_msix_vectors_vf;\n\t\tfor (i = 0; i < vf_msix_num; i++) {\n\t\t\tif (!i)\n\t\t\t\tval = I40E_VFINT_DYN_CTL0(vf_id);\n\t\t\telse\n\t\t\t\tval = I40E_VFINT_DYN_CTLN(((vf_msix_num - 1) *\n\t\t\t\t\t\t\t(vf_id)) + (i - 1));\n\t\t\tI40E_WRITE_REG(hw, val, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);\n\t\t}\n\t\tI40E_WRITE_FLUSH(hw);\n\n\t\t/* remove VSI */\n\t\tret = i40e_vsi_release(vf->vsi);\n\t\tif (ret != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Release VSI failed\");\n\t\t\treturn -EFAULT;\n\t\t}\n\t}\n\n#define I40E_VF_PCI_ADDR 0xAA\n#define I40E_VF_PEND_MASK 0x20\n\t/* Check the pending transactions of this VF */\n\t/* Use absolute VF id, refer to datasheet for details */\n\tI40E_WRITE_REG(hw, I40E_PF_PCI_CIAA, I40E_VF_PCI_ADDR |\n\t\t(abs_vf_id << I40E_PF_PCI_CIAA_VF_NUM_SHIFT));\n\tfor (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {\n\t\trte_delay_us(1);\n\t\tval = I40E_READ_REG(hw, I40E_PF_PCI_CIAD);\n\t\tif ((val & I40E_VF_PEND_MASK) == 0)\n\t\t\tbreak;\n\t}\n\n\tif (i >= VFRESET_MAX_WAIT_CNT) {\n\t\tPMD_DRV_LOG(ERR, \"Wait VF PCI transaction end timeout\");\n\t\treturn -ETIMEDOUT;\n\t}\n\n\t/* Reset done, Set COMPLETE flag and clear reset bit */\n\tI40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), I40E_PF_VFR_COMPLETED);\n\tval = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));\n\tval &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK;\n\tI40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);\n\tvf->reset_cnt++;\n\tI40E_WRITE_FLUSH(hw);\n\n\t/* Allocate resource again */\n\tvf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,\n\t\t\tvf->pf->main_vsi, vf->vf_idx);\n\tif (vf->vsi == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"Add vsi failed\");\n\t\treturn -EFAULT;\n\t}\n\n\tret = i40e_pf_vf_queues_mapping(vf);\n\tif (ret != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"queue mapping error\");\n\t\ti40e_vsi_release(vf->vsi);\n\t\treturn -EFAULT;\n\t}\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf,\n\t\t\t uint32_t opcode,\n\t\t\t uint32_t retval,\n\t\t\t uint8_t *msg,\n\t\t\t uint16_t msglen)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);\n\tuint16_t abs_vf_id = hw->func_caps.vf_base_id + vf->vf_idx;\n\tint ret;\n\n\tret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, opcode, retval,\n\t\t\t\t\t\tmsg, msglen, NULL);\n\tif (ret) {\n\t\tPMD_INIT_LOG(ERR, \"Fail to send message to VF, err %u\",\n\t\t\t hw->aq.asq_last_status);\n\t}\n\n\treturn ret;\n}\n\nstatic void\ni40e_pf_host_process_cmd_version(struct i40e_pf_vf *vf)\n{\n\tstruct i40e_virtchnl_version_info info;\n\n\tinfo.major = I40E_DPDK_VERSION_MAJOR;\n\tinfo.minor = I40E_DPDK_VERSION_MINOR;\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_VERSION,\n\t\tI40E_SUCCESS, (uint8_t *)&info, sizeof(info));\n}\n\nstatic int\ni40e_pf_host_process_cmd_reset_vf(struct i40e_pf_vf *vf)\n{\n\ti40e_pf_host_vf_reset(vf, 1);\n\n\t/* No feedback will be sent to VF for VFLR */\n\treturn I40E_SUCCESS;\n}\n\nstatic int\ni40e_pf_host_process_cmd_get_vf_resource(struct i40e_pf_vf *vf)\n{\n\tstruct i40e_virtchnl_vf_resource *vf_res = NULL;\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);\n\tuint32_t len = 0;\n\tint ret = I40E_SUCCESS;\n\n\t/* only have 1 VSI by default */\n\tlen = sizeof(struct i40e_virtchnl_vf_resource) +\n\t\t\t\tI40E_DEFAULT_VF_VSI_NUM *\n\t\tsizeof(struct i40e_virtchnl_vsi_resource);\n\n\tvf_res = rte_zmalloc(\"i40e_vf_res\", len, 0);\n\tif (vf_res == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"failed to allocate mem\");\n\t\tret = I40E_ERR_NO_MEMORY;\n\t\tvf_res = NULL;\n\t\tlen = 0;\n\t\tgoto send_msg;\n\t}\n\n\tvf_res->vf_offload_flags = I40E_VIRTCHNL_VF_OFFLOAD_L2 |\n\t\t\t\tI40E_VIRTCHNL_VF_OFFLOAD_VLAN;\n\tvf_res->max_vectors = hw->func_caps.num_msix_vectors_vf;\n\tvf_res->num_queue_pairs = vf->vsi->nb_qps;\n\tvf_res->num_vsis = I40E_DEFAULT_VF_VSI_NUM;\n\n\t/* Change below setting if PF host can support more VSIs for VF */\n\tvf_res->vsi_res[0].vsi_type = I40E_VSI_SRIOV;\n\t/* As assume Vf only has single VSI now, always return 0 */\n\tvf_res->vsi_res[0].vsi_id = 0;\n\tvf_res->vsi_res[0].num_queue_pairs = vf->vsi->nb_qps;\n\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES,\n\t\t\t\t\tret, (uint8_t *)vf_res, len);\n\trte_free(vf_res);\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_hmc_config_rxq(struct i40e_hw *hw,\n\t\t\t struct i40e_pf_vf *vf,\n\t\t\t struct i40e_virtchnl_rxq_info *rxq,\n\t\t\t uint8_t crcstrip)\n{\n\tint err = I40E_SUCCESS;\n\tstruct i40e_hmc_obj_rxq rx_ctx;\n\tuint16_t abs_queue_id = vf->vsi->base_queue + rxq->queue_id;\n\n\t/* Clear the context structure first */\n\tmemset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));\n\trx_ctx.dbuff = rxq->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT;\n\trx_ctx.hbuff = rxq->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT;\n\trx_ctx.base = rxq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;\n\trx_ctx.qlen = rxq->ring_len;\n#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n\trx_ctx.dsize = 1;\n#endif\n\n\tif (rxq->splithdr_enabled) {\n\t\trx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;\n\t\trx_ctx.dtype = i40e_header_split_enabled;\n\t} else {\n\t\trx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;\n\t\trx_ctx.dtype = i40e_header_split_none;\n\t}\n\trx_ctx.rxmax = rxq->max_pkt_size;\n\trx_ctx.tphrdesc_ena = 1;\n\trx_ctx.tphwdesc_ena = 1;\n\trx_ctx.tphdata_ena = 1;\n\trx_ctx.tphhead_ena = 1;\n\trx_ctx.lrxqthresh = 2;\n\trx_ctx.crcstrip = crcstrip;\n\trx_ctx.l2tsel = 1;\n\trx_ctx.prefena = 1;\n\n\terr = i40e_clear_lan_rx_queue_context(hw, abs_queue_id);\n\tif (err != I40E_SUCCESS)\n\t\treturn err;\n\terr = i40e_set_lan_rx_queue_context(hw, abs_queue_id, &rx_ctx);\n\n\treturn err;\n}\n\nstatic int\ni40e_pf_host_hmc_config_txq(struct i40e_hw *hw,\n\t\t\t struct i40e_pf_vf *vf,\n\t\t\t struct i40e_virtchnl_txq_info *txq)\n{\n\tint err = I40E_SUCCESS;\n\tstruct i40e_hmc_obj_txq tx_ctx;\n\tuint32_t qtx_ctl;\n\tuint16_t abs_queue_id = vf->vsi->base_queue + txq->queue_id;\n\n\n\t/* clear the context structure first */\n\tmemset(&tx_ctx, 0, sizeof(tx_ctx));\n\ttx_ctx.new_context = 1;\n\ttx_ctx.base = txq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;\n\ttx_ctx.qlen = txq->ring_len;\n\ttx_ctx.rdylist = rte_le_to_cpu_16(vf->vsi->info.qs_handle[0]);\n\terr = i40e_clear_lan_tx_queue_context(hw, abs_queue_id);\n\tif (err != I40E_SUCCESS)\n\t\treturn err;\n\n\terr = i40e_set_lan_tx_queue_context(hw, abs_queue_id, &tx_ctx);\n\tif (err != I40E_SUCCESS)\n\t\treturn err;\n\n\t/* bind queue with VF function, since TX/QX will appear in pair,\n\t * so only has QTX_CTL to set.\n\t */\n\tqtx_ctl = (I40E_QTX_CTL_VF_QUEUE << I40E_QTX_CTL_PFVF_Q_SHIFT) |\n\t\t\t\t((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &\n\t\t\t\tI40E_QTX_CTL_PF_INDX_MASK) |\n\t\t\t\t(((vf->vf_idx + hw->func_caps.vf_base_id) <<\n\t\t\t\tI40E_QTX_CTL_VFVM_INDX_SHIFT) &\n\t\t\t\tI40E_QTX_CTL_VFVM_INDX_MASK);\n\tI40E_WRITE_REG(hw, I40E_QTX_CTL(abs_queue_id), qtx_ctl);\n\tI40E_WRITE_FLUSH(hw);\n\n\treturn I40E_SUCCESS;\n}\n\nstatic int\ni40e_pf_host_process_cmd_config_vsi_queues(struct i40e_pf_vf *vf,\n\t\t\t\t\t uint8_t *msg,\n\t\t\t\t\t uint16_t msglen)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);\n\tstruct i40e_vsi *vsi = vf->vsi;\n\tstruct i40e_virtchnl_vsi_queue_config_info *vc_vqci =\n\t\t(struct i40e_virtchnl_vsi_queue_config_info *)msg;\n\tstruct i40e_virtchnl_queue_pair_info *vc_qpi;\n\tint i, ret = I40E_SUCCESS;\n\n\tif (!msg || vc_vqci->num_queue_pairs > vsi->nb_qps ||\n\t\tvc_vqci->num_queue_pairs > I40E_MAX_VSI_QP ||\n\t\tmsglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci,\n\t\t\t\t\tvc_vqci->num_queue_pairs)) {\n\t\tPMD_DRV_LOG(ERR, \"vsi_queue_config_info argument wrong\\n\");\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\n\tvc_qpi = vc_vqci->qpair;\n\tfor (i = 0; i < vc_vqci->num_queue_pairs; i++) {\n\t\tif (vc_qpi[i].rxq.queue_id > vsi->nb_qps - 1 ||\n\t\t\tvc_qpi[i].txq.queue_id > vsi->nb_qps - 1) {\n\t\t\tret = I40E_ERR_PARAM;\n\t\t\tgoto send_msg;\n\t\t}\n\n\t\t/*\n\t\t * Apply VF RX queue setting to HMC.\n\t\t * If the opcode is I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,\n\t\t * then the extra information of\n\t\t * 'struct i40e_virtchnl_queue_pair_extra_info' is needed,\n\t\t * otherwise set the last parameter to NULL.\n\t\t */\n\t\tif (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpi[i].rxq,\n\t\t\tI40E_CFG_CRCSTRIP_DEFAULT) != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Configure RX queue HMC failed\");\n\t\t\tret = I40E_ERR_PARAM;\n\t\t\tgoto send_msg;\n\t\t}\n\n\t\t/* Apply VF TX queue setting to HMC */\n\t\tif (i40e_pf_host_hmc_config_txq(hw, vf,\n\t\t\t&vc_qpi[i].txq) != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Configure TX queue HMC failed\");\n\t\t\tret = I40E_ERR_PARAM;\n\t\t\tgoto send_msg;\n\t\t}\n\t}\n\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES,\n\t\t\t\t\t\t\tret, NULL, 0);\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_process_cmd_config_vsi_queues_ext(struct i40e_pf_vf *vf,\n\t\t\t\t\t uint8_t *msg,\n\t\t\t\t\t uint16_t msglen)\n{\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);\n\tstruct i40e_vsi *vsi = vf->vsi;\n\tstruct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei =\n\t\t(struct i40e_virtchnl_vsi_queue_config_ext_info *)msg;\n\tstruct i40e_virtchnl_queue_pair_ext_info *vc_qpei;\n\tint i, ret = I40E_SUCCESS;\n\n\tif (!msg || vc_vqcei->num_queue_pairs > vsi->nb_qps ||\n\t\tvc_vqcei->num_queue_pairs > I40E_MAX_VSI_QP ||\n\t\tmsglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei,\n\t\t\t\t\tvc_vqcei->num_queue_pairs)) {\n\t\tPMD_DRV_LOG(ERR, \"vsi_queue_config_ext_info argument wrong\\n\");\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\n\tvc_qpei = vc_vqcei->qpair;\n\tfor (i = 0; i < vc_vqcei->num_queue_pairs; i++) {\n\t\tif (vc_qpei[i].rxq.queue_id > vsi->nb_qps - 1 ||\n\t\t\tvc_qpei[i].txq.queue_id > vsi->nb_qps - 1) {\n\t\t\tret = I40E_ERR_PARAM;\n\t\t\tgoto send_msg;\n\t\t}\n\t\t/*\n\t\t * Apply VF RX queue setting to HMC.\n\t\t * If the opcode is I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,\n\t\t * then the extra information of\n\t\t * 'struct i40e_virtchnl_queue_pair_ext_info' is needed,\n\t\t * otherwise set the last parameter to NULL.\n\t\t */\n\t\tif (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpei[i].rxq,\n\t\t\tvc_qpei[i].rxq_ext.crcstrip) != I40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Configure RX queue HMC failed\");\n\t\t\tret = I40E_ERR_PARAM;\n\t\t\tgoto send_msg;\n\t\t}\n\n\t\t/* Apply VF TX queue setting to HMC */\n\t\tif (i40e_pf_host_hmc_config_txq(hw, vf, &vc_qpei[i].txq) !=\n\t\t\t\t\t\t\tI40E_SUCCESS) {\n\t\t\tPMD_DRV_LOG(ERR, \"Configure TX queue HMC failed\");\n\t\t\tret = I40E_ERR_PARAM;\n\t\t\tgoto send_msg;\n\t\t}\n\t}\n\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,\n\t\t\t\t\t\t\t\tret, NULL, 0);\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf *vf,\n\t\t\t\t\tuint8_t *msg, uint16_t msglen)\n{\n\tint ret = I40E_SUCCESS;\n\tstruct i40e_virtchnl_irq_map_info *irqmap =\n\t (struct i40e_virtchnl_irq_map_info *)msg;\n\n\tif (msg == NULL || msglen < sizeof(struct i40e_virtchnl_irq_map_info)) {\n\t\tPMD_DRV_LOG(ERR, \"buffer too short\");\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\n\t/* Assume VF only have 1 vector to bind all queues */\n\tif (irqmap->num_vectors != 1) {\n\t\tPMD_DRV_LOG(ERR, \"DKDK host only support 1 vector\");\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\n\tif (irqmap->vecmap[0].vector_id == 0) {\n\t\tPMD_DRV_LOG(ERR, \"DPDK host don't support use IRQ0\");\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\t/* This MSIX intr store the intr in VF range */\n\tvf->vsi->msix_intr = irqmap->vecmap[0].vector_id;\n\n\t/* Don't care how the TX/RX queue mapping with this vector.\n\t * Link all VF RX queues together. Only did mapping work.\n\t * VF can disable/enable the intr by itself.\n\t */\n\ti40e_vsi_queues_bind_intr(vf->vsi);\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP,\n\t\t\t\t\t\t\tret, NULL, 0);\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_switch_queues(struct i40e_pf_vf *vf,\n\t\t\t struct i40e_virtchnl_queue_select *qsel,\n\t\t\t bool on)\n{\n\tint ret = I40E_SUCCESS;\n\tint i;\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);\n\tuint16_t baseq = vf->vsi->base_queue;\n\n\tif (qsel->rx_queues + qsel->tx_queues == 0)\n\t\treturn I40E_ERR_PARAM;\n\n\t/* always enable RX first and disable last */\n\t/* Enable RX if it's enable */\n\tif (on) {\n\t\tfor (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)\n\t\t\tif (qsel->rx_queues & (1 << i)) {\n\t\t\t\tret = i40e_switch_rx_queue(hw, baseq + i, on);\n\t\t\t\tif (ret != I40E_SUCCESS)\n\t\t\t\t\treturn ret;\n\t\t\t}\n\t}\n\n\t/* Enable/Disable TX */\n\tfor (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)\n\t\tif (qsel->tx_queues & (1 << i)) {\n\t\t\tret = i40e_switch_tx_queue(hw, baseq + i, on);\n\t\t\tif (ret != I40E_SUCCESS)\n\t\t\t\treturn ret;\n\t\t}\n\n\t/* disable RX last if it's disable */\n\tif (!on) {\n\t\t/* disable RX */\n\t\tfor (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)\n\t\t\tif (qsel->rx_queues & (1 << i)) {\n\t\t\t\tret = i40e_switch_rx_queue(hw, baseq + i, on);\n\t\t\t\tif (ret != I40E_SUCCESS)\n\t\t\t\t\treturn ret;\n\t\t\t}\n\t}\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_process_cmd_enable_queues(struct i40e_pf_vf *vf,\n\t\t\t\t uint8_t *msg,\n\t\t\t\t uint16_t msglen)\n{\n\tint ret = I40E_SUCCESS;\n\tstruct i40e_virtchnl_queue_select *q_sel =\n\t\t(struct i40e_virtchnl_queue_select *)msg;\n\n\tif (msg == NULL || msglen != sizeof(*q_sel)) {\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\tret = i40e_pf_host_switch_queues(vf, q_sel, true);\n\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES,\n\t\t\t\t\t\t\tret, NULL, 0);\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_process_cmd_disable_queues(struct i40e_pf_vf *vf,\n\t\t\t\t\tuint8_t *msg,\n\t\t\t\t\tuint16_t msglen)\n{\n\tint ret = I40E_SUCCESS;\n\tstruct i40e_virtchnl_queue_select *q_sel =\n\t\t(struct i40e_virtchnl_queue_select *)msg;\n\n\tif (msg == NULL || msglen != sizeof(*q_sel)) {\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\tret = i40e_pf_host_switch_queues(vf, q_sel, false);\n\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES,\n\t\t\t\t\t\t\tret, NULL, 0);\n\n\treturn ret;\n}\n\n\nstatic int\ni40e_pf_host_process_cmd_add_ether_address(struct i40e_pf_vf *vf,\n\t\t\t\t\t uint8_t *msg,\n\t\t\t\t\t uint16_t msglen)\n{\n\tint ret = I40E_SUCCESS;\n\tstruct i40e_virtchnl_ether_addr_list *addr_list =\n\t\t\t(struct i40e_virtchnl_ether_addr_list *)msg;\n\tstruct i40e_mac_filter_info filter;\n\tint i;\n\tstruct ether_addr *mac;\n\n\tmemset(&filter, 0 , sizeof(struct i40e_mac_filter_info));\n\n\tif (msg == NULL || msglen <= sizeof(*addr_list)) {\n\t\tPMD_DRV_LOG(ERR, \"add_ether_address argument too short\");\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\n\tfor (i = 0; i < addr_list->num_elements; i++) {\n\t\tmac = (struct ether_addr *)(addr_list->list[i].addr);\n\t\t(void)rte_memcpy(&filter.mac_addr, mac, ETHER_ADDR_LEN);\n\t\tfilter.filter_type = RTE_MACVLAN_PERFECT_MATCH;\n\t\tif(!is_valid_assigned_ether_addr(mac) ||\n\t\t\ti40e_vsi_add_mac(vf->vsi, &filter)) {\n\t\t\tret = I40E_ERR_INVALID_MAC_ADDR;\n\t\t\tgoto send_msg;\n\t\t}\n\t}\n\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS,\n\t\t\t\t\t\t\tret, NULL, 0);\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_process_cmd_del_ether_address(struct i40e_pf_vf *vf,\n\t\t\t\t\t uint8_t *msg,\n\t\t\t\t\t uint16_t msglen)\n{\n\tint ret = I40E_SUCCESS;\n\tstruct i40e_virtchnl_ether_addr_list *addr_list =\n\t\t(struct i40e_virtchnl_ether_addr_list *)msg;\n\tint i;\n\tstruct ether_addr *mac;\n\n\tif (msg == NULL || msglen <= sizeof(*addr_list)) {\n\t\tPMD_DRV_LOG(ERR, \"delete_ether_address argument too short\");\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\n\tfor (i = 0; i < addr_list->num_elements; i++) {\n\t\tmac = (struct ether_addr *)(addr_list->list[i].addr);\n\t\tif(!is_valid_assigned_ether_addr(mac) ||\n\t\t\ti40e_vsi_delete_mac(vf->vsi, mac)) {\n\t\t\tret = I40E_ERR_INVALID_MAC_ADDR;\n\t\t\tgoto send_msg;\n\t\t}\n\t}\n\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS,\n\t\t\t\t\t\t\tret, NULL, 0);\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_process_cmd_add_vlan(struct i40e_pf_vf *vf,\n\t\t\t\tuint8_t *msg, uint16_t msglen)\n{\n\tint ret = I40E_SUCCESS;\n\tstruct i40e_virtchnl_vlan_filter_list *vlan_filter_list =\n\t\t(struct i40e_virtchnl_vlan_filter_list *)msg;\n\tint i;\n\tuint16_t *vid;\n\n\tif (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {\n\t\tPMD_DRV_LOG(ERR, \"add_vlan argument too short\");\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\n\tvid = vlan_filter_list->vlan_id;\n\n\tfor (i = 0; i < vlan_filter_list->num_elements; i++) {\n\t\tret = i40e_vsi_add_vlan(vf->vsi, vid[i]);\n\t\tif(ret != I40E_SUCCESS)\n\t\t\tgoto send_msg;\n\t}\n\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ADD_VLAN,\n\t\t\t\t\t\tret, NULL, 0);\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_process_cmd_del_vlan(struct i40e_pf_vf *vf,\n\t\t\t\t uint8_t *msg,\n\t\t\t\t uint16_t msglen)\n{\n\tint ret = I40E_SUCCESS;\n\tstruct i40e_virtchnl_vlan_filter_list *vlan_filter_list =\n\t\t\t(struct i40e_virtchnl_vlan_filter_list *)msg;\n\tint i;\n\tuint16_t *vid;\n\n\tif (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {\n\t\tPMD_DRV_LOG(ERR, \"delete_vlan argument too short\");\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\n\tvid = vlan_filter_list->vlan_id;\n\tfor (i = 0; i < vlan_filter_list->num_elements; i++) {\n\t\tret = i40e_vsi_delete_vlan(vf->vsi, vid[i]);\n\t\tif(ret != I40E_SUCCESS)\n\t\t\tgoto send_msg;\n\t}\n\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DEL_VLAN,\n\t\t\t\t\t\tret, NULL, 0);\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_process_cmd_config_promisc_mode(\n\t\t\t\t\tstruct i40e_pf_vf *vf,\n\t\t\t\t\tuint8_t *msg,\n\t\t\t\t\tuint16_t msglen)\n{\n\tint ret = I40E_SUCCESS;\n\tstruct i40e_virtchnl_promisc_info *promisc =\n\t\t\t\t(struct i40e_virtchnl_promisc_info *)msg;\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);\n\tbool unicast = FALSE, multicast = FALSE;\n\n\tif (msg == NULL || msglen != sizeof(*promisc)) {\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\n\tif (promisc->flags & I40E_FLAG_VF_UNICAST_PROMISC)\n\t\tunicast = TRUE;\n\tret = i40e_aq_set_vsi_unicast_promiscuous(hw,\n\t\t\tvf->vsi->seid, unicast, NULL);\n\tif (ret != I40E_SUCCESS)\n\t\tgoto send_msg;\n\n\tif (promisc->flags & I40E_FLAG_VF_MULTICAST_PROMISC)\n\t\tmulticast = TRUE;\n\tret = i40e_aq_set_vsi_multicast_promiscuous(hw, vf->vsi->seid,\n\t\t\t\t\t\tmulticast, NULL);\n\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf,\n\t\tI40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, ret, NULL, 0);\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_process_cmd_get_stats(struct i40e_pf_vf *vf)\n{\n\ti40e_update_vsi_stats(vf->vsi);\n\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_STATS,\n\t\tI40E_SUCCESS, (uint8_t *)&vf->vsi->eth_stats,\n\t\t\t\tsizeof(vf->vsi->eth_stats));\n\n\treturn I40E_SUCCESS;\n}\n\nstatic void\ni40e_pf_host_process_cmd_get_link_status(struct i40e_pf_vf *vf)\n{\n\tstruct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vf->pf->main_vsi);\n\n\t/* Update link status first to acquire latest link change */\n\ti40e_dev_link_update(dev, 1);\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_LINK_STAT,\n\t\tI40E_SUCCESS, (uint8_t *)&dev->data->dev_link,\n\t\t\t\tsizeof(struct rte_eth_link));\n}\n\nstatic int\ni40e_pf_host_process_cmd_cfg_vlan_offload(\n\t\t\t\t\tstruct i40e_pf_vf *vf,\n\t\t\t\t\tuint8_t *msg,\n\t\t\t\t\tuint16_t msglen)\n{\n\tint ret = I40E_SUCCESS;\n\tstruct i40e_virtchnl_vlan_offload_info *offload =\n\t\t\t(struct i40e_virtchnl_vlan_offload_info *)msg;\n\n\tif (msg == NULL || msglen != sizeof(*offload)) {\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\n\tret = i40e_vsi_config_vlan_stripping(vf->vsi,\n\t\t\t\t\t\t!!offload->enable_vlan_strip);\n\tif (ret != 0)\n\t\tPMD_DRV_LOG(ERR, \"Failed to configure vlan stripping\");\n\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD,\n\t\t\t\t\tret, NULL, 0);\n\n\treturn ret;\n}\n\nstatic int\ni40e_pf_host_process_cmd_cfg_pvid(struct i40e_pf_vf *vf,\n\t\t\t\t\tuint8_t *msg,\n\t\t\t\t\tuint16_t msglen)\n{\n\tint ret = I40E_SUCCESS;\n\tstruct i40e_virtchnl_pvid_info *tpid_info =\n\t\t\t(struct i40e_virtchnl_pvid_info *)msg;\n\n\tif (msg == NULL || msglen != sizeof(*tpid_info)) {\n\t\tret = I40E_ERR_PARAM;\n\t\tgoto send_msg;\n\t}\n\n\tret = i40e_vsi_vlan_pvid_set(vf->vsi, &tpid_info->info);\n\nsend_msg:\n\ti40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CFG_VLAN_PVID,\n\t\t\t\t\tret, NULL, 0);\n\n\treturn ret;\n}\n\nvoid\ni40e_pf_host_handle_vf_msg(struct rte_eth_dev *dev,\n\t\t\t uint16_t abs_vf_id, uint32_t opcode,\n\t\t\t __rte_unused uint32_t retval,\n\t\t\t uint8_t *msg,\n\t\t\t uint16_t msglen)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_pf_vf *vf;\n\t/* AdminQ will pass absolute VF id, transfer to internal vf id */\n\tuint16_t vf_id = abs_vf_id - hw->func_caps.vf_base_id;\n\n\tif (!dev || vf_id > pf->vf_num - 1 || !pf->vfs) {\n\t\tPMD_DRV_LOG(ERR, \"invalid argument\");\n\t\treturn;\n\t}\n\n\tvf = &pf->vfs[vf_id];\n\tif (!vf->vsi) {\n\t\tPMD_DRV_LOG(ERR, \"NO VSI associated with VF found\");\n\t\ti40e_pf_host_send_msg_to_vf(vf, opcode,\n\t\t\tI40E_ERR_NO_AVAILABLE_VSI, NULL, 0);\n\t\treturn;\n\t}\n\n\tswitch (opcode) {\n\tcase I40E_VIRTCHNL_OP_VERSION :\n\t\tPMD_DRV_LOG(INFO, \"OP_VERSION received\");\n\t\ti40e_pf_host_process_cmd_version(vf);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_RESET_VF :\n\t\tPMD_DRV_LOG(INFO, \"OP_RESET_VF received\");\n\t\ti40e_pf_host_process_cmd_reset_vf(vf);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_GET_VF_RESOURCES:\n\t\tPMD_DRV_LOG(INFO, \"OP_GET_VF_RESOURCES received\");\n\t\ti40e_pf_host_process_cmd_get_vf_resource(vf);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES:\n\t\tPMD_DRV_LOG(INFO, \"OP_CONFIG_VSI_QUEUES received\");\n\t\ti40e_pf_host_process_cmd_config_vsi_queues(vf, msg, msglen);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT:\n\t\tPMD_DRV_LOG(INFO, \"OP_CONFIG_VSI_QUEUES_EXT received\");\n\t\ti40e_pf_host_process_cmd_config_vsi_queues_ext(vf, msg,\n\t\t\t\t\t\t\t\tmsglen);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP:\n\t\tPMD_DRV_LOG(INFO, \"OP_CONFIG_IRQ_MAP received\");\n\t\ti40e_pf_host_process_cmd_config_irq_map(vf, msg, msglen);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_ENABLE_QUEUES:\n\t\tPMD_DRV_LOG(INFO, \"OP_ENABLE_QUEUES received\");\n\t\ti40e_pf_host_process_cmd_enable_queues(vf, msg, msglen);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_DISABLE_QUEUES:\n\t\tPMD_DRV_LOG(INFO, \"OP_DISABLE_QUEUE received\");\n\t\ti40e_pf_host_process_cmd_disable_queues(vf, msg, msglen);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS:\n\t\tPMD_DRV_LOG(INFO, \"OP_ADD_ETHER_ADDRESS received\");\n\t\ti40e_pf_host_process_cmd_add_ether_address(vf, msg, msglen);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS:\n\t\tPMD_DRV_LOG(INFO, \"OP_DEL_ETHER_ADDRESS received\");\n\t\ti40e_pf_host_process_cmd_del_ether_address(vf, msg, msglen);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_ADD_VLAN:\n\t\tPMD_DRV_LOG(INFO, \"OP_ADD_VLAN received\");\n\t\ti40e_pf_host_process_cmd_add_vlan(vf, msg, msglen);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_DEL_VLAN:\n\t\tPMD_DRV_LOG(INFO, \"OP_DEL_VLAN received\");\n\t\ti40e_pf_host_process_cmd_del_vlan(vf, msg, msglen);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:\n\t\tPMD_DRV_LOG(INFO, \"OP_CONFIG_PROMISCUOUS_MODE received\");\n\t\ti40e_pf_host_process_cmd_config_promisc_mode(vf, msg, msglen);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_GET_STATS:\n\t\tPMD_DRV_LOG(INFO, \"OP_GET_STATS received\");\n\t\ti40e_pf_host_process_cmd_get_stats(vf);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_GET_LINK_STAT:\n\t\tPMD_DRV_LOG(INFO, \"OP_GET_LINK_STAT received\");\n\t\ti40e_pf_host_process_cmd_get_link_status(vf);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD:\n\t\tPMD_DRV_LOG(INFO, \"OP_CFG_VLAN_OFFLOAD received\");\n\t\ti40e_pf_host_process_cmd_cfg_vlan_offload(vf, msg, msglen);\n\t\tbreak;\n\tcase I40E_VIRTCHNL_OP_CFG_VLAN_PVID:\n\t\tPMD_DRV_LOG(INFO, \"OP_CFG_VLAN_PVID received\");\n\t\ti40e_pf_host_process_cmd_cfg_pvid(vf, msg, msglen);\n\t\tbreak;\n\t /* Don't add command supported below, which will\n\t * return an error code.\n\t */\n\tcase I40E_VIRTCHNL_OP_FCOE:\n\t\tPMD_DRV_LOG(ERR, \"OP_FCOE received, not supported\");\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"%u received, not supported\", opcode);\n\t\ti40e_pf_host_send_msg_to_vf(vf, opcode, I40E_ERR_PARAM,\n\t\t\t\t\t\t\t\tNULL, 0);\n\t\tbreak;\n\t}\n}\n\nint\ni40e_pf_host_init(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tint ret, i;\n\tuint32_t val;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/**\n\t * return if SRIOV not enabled, VF number not configured or\n\t * no queue assigned.\n\t */\n\tif(!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 || pf->vf_nb_qps == 0)\n\t\treturn I40E_SUCCESS;\n\n\t/* Allocate memory to store VF structure */\n\tpf->vfs = rte_zmalloc(\"i40e_pf_vf\",sizeof(*pf->vfs) * pf->vf_num, 0);\n\tif(pf->vfs == NULL)\n\t\treturn -ENOMEM;\n\n\t/* Disable irq0 for VFR event */\n\ti40e_pf_disable_irq0(hw);\n\n\t/* Disable VF link status interrupt */\n\tval = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);\n\tval &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;\n\tI40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);\n\tI40E_WRITE_FLUSH(hw);\n\n\tfor (i = 0; i < pf->vf_num; i++) {\n\t\tpf->vfs[i].pf = pf;\n\t\tpf->vfs[i].state = I40E_VF_INACTIVE;\n\t\tpf->vfs[i].vf_idx = i;\n\t\tret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);\n\t\tif (ret != I40E_SUCCESS)\n\t\t\tgoto fail;\n\t}\n\n\t/* restore irq0 */\n\ti40e_pf_enable_irq0(hw);\n\n\treturn I40E_SUCCESS;\n\nfail:\n\trte_free(pf->vfs);\n\ti40e_pf_enable_irq0(hw);\n\n\treturn ret;\n}\n\nint\ni40e_pf_host_uninit(struct rte_eth_dev *dev)\n{\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n\tuint32_t val;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/**\n\t * return if SRIOV not enabled, VF number not configured or\n\t * no queue assigned.\n\t */\n\tif ((!hw->func_caps.sr_iov_1_1) ||\n\t\t(pf->vf_num == 0) ||\n\t\t(pf->vf_nb_qps == 0))\n\t\treturn I40E_SUCCESS;\n\n\t/* free memory to store VF structure */\n\trte_free(pf->vfs);\n\tpf->vfs = NULL;\n\n\t/* Disable irq0 for VFR event */\n\ti40e_pf_disable_irq0(hw);\n\n\t/* Disable VF link status interrupt */\n\tval = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);\n\tval &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;\n\tI40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);\n\tI40E_WRITE_FLUSH(hw);\n\n\treturn I40E_SUCCESS;\n}\n" }, { "path": "drivers/net/i40e/i40e_pf.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _I40E_PF_H_\n#define _I40E_PF_H_\n\n/* VERSION info to exchange between VF and PF host. In case VF works with\n * ND kernel driver, it reads I40E_VIRTCHNL_VERSION_MAJOR/MINOR. In\n * case works with DPDK host, it reads version below. Then VF realize who it\n * is talking to and use proper language to communicate.\n * */\n#define I40E_DPDK_SIGNATURE ('D' << 24 | 'P' << 16 | 'D' << 8 | 'K')\n#define I40E_DPDK_VERSION_MAJOR I40E_DPDK_SIGNATURE\n#define I40E_DPDK_VERSION_MINOR 0\n\n/* Default setting on number of VSIs that VF can contain */\n#define I40E_DEFAULT_VF_VSI_NUM 1\n\n#define I40E_DPDK_OFFSET 0x100\n\nenum i40e_pf_vfr_state {\n\tI40E_PF_VFR_INPROGRESS = 0,\n\tI40E_PF_VFR_COMPLETED = 1,\n};\n\n/* DPDK pf driver specific command to VF */\nenum i40e_virtchnl_ops_dpdk {\n\t/*\n\t * Keep some gap between Linux PF commands and\n\t * DPDK PF extended commands.\n\t */\n\tI40E_VIRTCHNL_OP_GET_LINK_STAT = I40E_VIRTCHNL_OP_VERSION +\n\t\t\t\t\t\tI40E_DPDK_OFFSET,\n\tI40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD,\n\tI40E_VIRTCHNL_OP_CFG_VLAN_PVID,\n\tI40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,\n};\n\n/* A structure to support extended info of a receive queue. */\nstruct i40e_virtchnl_rxq_ext_info {\n\tuint8_t crcstrip;\n};\n\n/*\n * A structure to support extended info of queue pairs, an additional field\n * is added, comparing to original 'struct i40e_virtchnl_queue_pair_info'.\n */\nstruct i40e_virtchnl_queue_pair_ext_info {\n\t/* vsi_id and queue_id should be identical for both rx and tx queues.*/\n\tstruct i40e_virtchnl_txq_info txq;\n\tstruct i40e_virtchnl_rxq_info rxq;\n\tstruct i40e_virtchnl_rxq_ext_info rxq_ext;\n};\n\n/*\n * A structure to support extended info of VSI queue pairs,\n * 'struct i40e_virtchnl_queue_pair_ext_info' is used, see its original\n * of 'struct i40e_virtchnl_queue_pair_info'.\n */\nstruct i40e_virtchnl_vsi_queue_config_ext_info {\n\tuint16_t vsi_id;\n\tuint16_t num_queue_pairs;\n\tstruct i40e_virtchnl_queue_pair_ext_info qpair[0];\n};\n\nstruct i40e_virtchnl_vlan_offload_info {\n\tuint16_t vsi_id;\n\tuint8_t enable_vlan_strip;\n\tuint8_t reserved;\n};\n\n/*\n * Macro to calculate the memory size for configuring VSI queues\n * via virtual channel.\n */\n#define I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(x, n) \\\n\t(sizeof(*(x)) + sizeof((x)->qpair[0]) * (n))\n\n/*\n * I40E_VIRTCHNL_OP_CFG_VLAN_PVID\n * VF sends this message to enable/disable pvid. If it's\n * enable op, needs to specify the pvid. PF returns status\n * code in retval.\n */\nstruct i40e_virtchnl_pvid_info {\n\tuint16_t vsi_id;\n\tstruct i40e_vsi_vlan_pvid_info info;\n};\n\nint i40e_pf_host_vf_reset(struct i40e_pf_vf *vf, bool do_hw_reset);\nvoid i40e_pf_host_handle_vf_msg(struct rte_eth_dev *dev,\n\t\t\t\tuint16_t abs_vf_id, uint32_t opcode,\n\t\t\t\t__rte_unused uint32_t retval,\n\t\t\t\tuint8_t *msg, uint16_t msglen);\nint i40e_pf_host_init(struct rte_eth_dev *dev);\nint i40e_pf_host_uninit(struct rte_eth_dev *dev);\n\n#endif /* _I40E_PF_H_ */\n" }, { "path": "drivers/net/i40e/i40e_rxtx.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"i40e_logs.h\"\n#include \"base/i40e_prototype.h\"\n#include \"base/i40e_type.h\"\n#include \"i40e_ethdev.h\"\n#include \"i40e_rxtx.h\"\n\n#define I40E_MIN_RING_DESC 64\n#define I40E_MAX_RING_DESC 4096\n#define I40E_ALIGN 128\n#define DEFAULT_TX_RS_THRESH 32\n#define DEFAULT_TX_FREE_THRESH 32\n#define I40E_MAX_PKT_TYPE 256\n\n#define I40E_TX_MAX_BURST 32\n\n#define I40E_DMA_MEM_ALIGN 4096\n\n#define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \\\n\t\t\t\t\tETH_TXQ_FLAGS_NOOFFLOADS)\n\n#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)\n\n#define I40E_TX_CKSUM_OFFLOAD_MASK (\t\t \\\n\t\tPKT_TX_IP_CKSUM |\t\t \\\n\t\tPKT_TX_L4_MASK |\t\t \\\n\t\tPKT_TX_OUTER_IP_CKSUM)\n\n#define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \\\n\t(uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)\n\n#define RTE_MBUF_DATA_DMA_ADDR(mb) \\\n\t((uint64_t)((mb)->buf_physaddr + (mb)->data_off))\n\nstatic const struct rte_memzone *\ni40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,\n\t\t\t const char *ring_name,\n\t\t\t uint16_t queue_id,\n\t\t\t uint32_t ring_size,\n\t\t\t int socket_id);\nstatic uint16_t i40e_xmit_pkts_simple(void *tx_queue,\n\t\t\t\t struct rte_mbuf **tx_pkts,\n\t\t\t\t uint16_t nb_pkts);\n\nstatic inline void\ni40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)\n{\n\tif (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &\n\t\t(1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {\n\t\tmb->ol_flags |= PKT_RX_VLAN_PKT;\n\t\tmb->vlan_tci =\n\t\t\trte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);\n\t\tPMD_RX_LOG(DEBUG, \"Descriptor l2tag1: %u\",\n\t\t\t rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));\n\t} else {\n\t\tmb->vlan_tci = 0;\n\t}\n#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n\tif (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &\n\t\t(1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {\n\t\tmb->ol_flags |= PKT_RX_QINQ_PKT;\n\t\tmb->vlan_tci_outer = mb->vlan_tci;\n\t\tmb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);\n\t\tPMD_RX_LOG(DEBUG, \"Descriptor l2tag2_1: %u, l2tag2_2: %u\",\n\t\t\t rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),\n\t\t\t rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));\n\t} else {\n\t\tmb->vlan_tci_outer = 0;\n\t}\n#endif\n\tPMD_RX_LOG(DEBUG, \"Mbuf vlan_tci: %u, vlan_tci_outer: %u\",\n\t\t mb->vlan_tci, mb->vlan_tci_outer);\n}\n\n/* Translate the rx descriptor status to pkt flags */\nstatic inline uint64_t\ni40e_rxd_status_to_pkt_flags(uint64_t qword)\n{\n\tuint64_t flags;\n\n\t/* Check if RSS_HASH */\n\tflags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &\n\t\t\t\t\tI40E_RX_DESC_FLTSTAT_RSS_HASH) ==\n\t\t\tI40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;\n\n\t/* Check if FDIR Match */\n\tflags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?\n\t\t\t\t\t\t\tPKT_RX_FDIR : 0);\n\n\treturn flags;\n}\n\nstatic inline uint64_t\ni40e_rxd_error_to_pkt_flags(uint64_t qword)\n{\n\tuint64_t flags = 0;\n\tuint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);\n\n#define I40E_RX_ERR_BITS 0x3f\n\tif (likely((error_bits & I40E_RX_ERR_BITS) == 0))\n\t\treturn flags;\n\t/* If RXE bit set, all other status bits are meaningless */\n\tif (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {\n\t\tflags |= PKT_RX_MAC_ERR;\n\t\treturn flags;\n\t}\n\n\t/* If RECIPE bit set, all other status indications should be ignored */\n\tif (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {\n\t\tflags |= PKT_RX_RECIP_ERR;\n\t\treturn flags;\n\t}\n\tif (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))\n\t\tflags |= PKT_RX_HBUF_OVERFLOW;\n\tif (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))\n\t\tflags |= PKT_RX_IP_CKSUM_BAD;\n\tif (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))\n\t\tflags |= PKT_RX_L4_CKSUM_BAD;\n\tif (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))\n\t\tflags |= PKT_RX_EIP_CKSUM_BAD;\n\tif (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))\n\t\tflags |= PKT_RX_OVERSIZE;\n\n\treturn flags;\n}\n\n/* Function to check and set the ieee1588 timesync index and get the\n * appropriate flags.\n */\n#ifdef RTE_LIBRTE_IEEE1588\nstatic inline uint64_t\ni40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)\n{\n\tuint64_t pkt_flags = 0;\n\tuint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK\n\t\t\t\t | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))\n\t\t\t\t >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;\n\n#ifdef RTE_NEXT_ABI\n\tif ((mb->packet_type & RTE_PTYPE_L2_MASK)\n\t\t\t== RTE_PTYPE_L2_ETHER_TIMESYNC)\n\t\tpkt_flags = PKT_RX_IEEE1588_PTP;\n#endif\n\tif (tsyn & 0x04) {\n\t\tpkt_flags |= PKT_RX_IEEE1588_TMST;\n\t\tmb->timesync = tsyn & 0x03;\n\t}\n\n\treturn pkt_flags;\n}\n#endif\n\n#ifdef RTE_NEXT_ABI\n/* For each value it means, datasheet of hardware can tell more details */\nstatic inline uint32_t\ni40e_rxd_pkt_type_mapping(uint8_t ptype)\n{\n\tstatic const uint32_t ptype_table[UINT8_MAX] __rte_cache_aligned = {\n\t\t/* L2 types */\n\t\t/* [0] reserved */\n\t\t[1] = RTE_PTYPE_L2_ETHER,\n\t\t[2] = RTE_PTYPE_L2_ETHER_TIMESYNC,\n\t\t/* [3] - [5] reserved */\n\t\t[6] = RTE_PTYPE_L2_ETHER_LLDP,\n\t\t/* [7] - [10] reserved */\n\t\t[11] = RTE_PTYPE_L2_ETHER_ARP,\n\t\t/* [12] - [21] reserved */\n\n\t\t/* Non tunneled IPv4 */\n\t\t[22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_L4_FRAG,\n\t\t[23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_L4_NONFRAG,\n\t\t[24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_L4_UDP,\n\t\t/* [25] reserved */\n\t\t[26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_L4_TCP,\n\t\t[27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_L4_SCTP,\n\t\t[28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_L4_ICMP,\n\n\t\t/* IPv4 --> IPv4 */\n\t\t[29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [32] reserved */\n\t\t[33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv4 --> IPv6 */\n\t\t[36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [39] reserved */\n\t\t[40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv4 --> GRE/Teredo/VXLAN */\n\t\t[43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT,\n\n\t\t/* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */\n\t\t[44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [47] reserved */\n\t\t[48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */\n\t\t[51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [54] reserved */\n\t\t[55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv4 --> GRE/Teredo/VXLAN --> MAC */\n\t\t[58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,\n\n\t\t/* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */\n\t\t[59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [62] reserved */\n\t\t[63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */\n\t\t[66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [69] reserved */\n\t\t[70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */\n\t\t[73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN,\n\n\t\t/* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */\n\t\t[74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [77] reserved */\n\t\t[78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */\n\t\t[81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [84] reserved */\n\t\t[85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* Non tunneled IPv6 */\n\t\t[88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_L4_FRAG,\n\t\t[89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_L4_NONFRAG,\n\t\t[90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_L4_UDP,\n\t\t/* [91] reserved */\n\t\t[92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_L4_TCP,\n\t\t[93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_L4_SCTP,\n\t\t[94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_L4_ICMP,\n\n\t\t/* IPv6 --> IPv4 */\n\t\t[95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [98] reserved */\n\t\t[99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv6 --> IPv6 */\n\t\t[102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [105] reserved */\n\t\t[106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv6 --> GRE/Teredo/VXLAN */\n\t\t[109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT,\n\n\t\t/* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */\n\t\t[110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [113] reserved */\n\t\t[114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */\n\t\t[117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [120] reserved */\n\t\t[121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv6 --> GRE/Teredo/VXLAN --> MAC */\n\t\t[124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,\n\n\t\t/* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */\n\t\t[125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [128] reserved */\n\t\t[129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */\n\t\t[132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [135] reserved */\n\t\t[136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */\n\t\t[139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN,\n\n\t\t/* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */\n\t\t[140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [143] reserved */\n\t\t[144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */\n\t\t[147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_FRAG,\n\t\t[148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_NONFRAG,\n\t\t[149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_UDP,\n\t\t/* [150] reserved */\n\t\t[151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_TCP,\n\t\t[152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_SCTP,\n\t\t[153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_TUNNEL_GRENAT |\n\t\t\tRTE_PTYPE_INNER_L2_ETHER_VLAN |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n\t\t\tRTE_PTYPE_INNER_L4_ICMP,\n\n\t\t/* All others reserved */\n\t};\n\n\treturn ptype_table[ptype];\n}\n#else /* RTE_NEXT_ABI */\n/* Translate pkt types to pkt flags */\nstatic inline uint64_t\ni40e_rxd_ptype_to_pkt_flags(uint64_t qword)\n{\n\tuint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>\n\t\t\t\t\tI40E_RXD_QW1_PTYPE_SHIFT);\n\tstatic const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {\n\t\t0, /* PTYPE 0 */\n\t\t0, /* PTYPE 1 */\n\t\tPKT_RX_IEEE1588_PTP, /* PTYPE 2 */\n\t\t0, /* PTYPE 3 */\n\t\t0, /* PTYPE 4 */\n\t\t0, /* PTYPE 5 */\n\t\t0, /* PTYPE 6 */\n\t\t0, /* PTYPE 7 */\n\t\t0, /* PTYPE 8 */\n\t\t0, /* PTYPE 9 */\n\t\t0, /* PTYPE 10 */\n\t\t0, /* PTYPE 11 */\n\t\t0, /* PTYPE 12 */\n\t\t0, /* PTYPE 13 */\n\t\t0, /* PTYPE 14 */\n\t\t0, /* PTYPE 15 */\n\t\t0, /* PTYPE 16 */\n\t\t0, /* PTYPE 17 */\n\t\t0, /* PTYPE 18 */\n\t\t0, /* PTYPE 19 */\n\t\t0, /* PTYPE 20 */\n\t\t0, /* PTYPE 21 */\n\t\tPKT_RX_IPV4_HDR, /* PTYPE 22 */\n\t\tPKT_RX_IPV4_HDR, /* PTYPE 23 */\n\t\tPKT_RX_IPV4_HDR, /* PTYPE 24 */\n\t\t0, /* PTYPE 25 */\n\t\tPKT_RX_IPV4_HDR, /* PTYPE 26 */\n\t\tPKT_RX_IPV4_HDR, /* PTYPE 27 */\n\t\tPKT_RX_IPV4_HDR, /* PTYPE 28 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */\n\t\t0, /* PTYPE 32 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */\n\t\t0, /* PTYPE 39 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */\n\t\t0, /* PTYPE 47 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */\n\t\t0, /* PTYPE 54 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */\n\t\t0, /* PTYPE 62 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */\n\t\t0, /* PTYPE 69 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */\n\t\t0, /* PTYPE 77 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */\n\t\t0, /* PTYPE 84 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */\n\t\tPKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */\n\t\tPKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */\n\t\tPKT_RX_IPV6_HDR, /* PTYPE 88 */\n\t\tPKT_RX_IPV6_HDR, /* PTYPE 89 */\n\t\tPKT_RX_IPV6_HDR, /* PTYPE 90 */\n\t\t0, /* PTYPE 91 */\n\t\tPKT_RX_IPV6_HDR, /* PTYPE 92 */\n\t\tPKT_RX_IPV6_HDR, /* PTYPE 93 */\n\t\tPKT_RX_IPV6_HDR, /* PTYPE 94 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */\n\t\t0, /* PTYPE 98 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */\n\t\t0, /* PTYPE 105 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */\n\t\t0, /* PTYPE 113 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */\n\t\t0, /* PTYPE 120 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */\n\t\t0, /* PTYPE 128 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */\n\t\t0, /* PTYPE 135 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */\n\t\t0, /* PTYPE 143 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */\n\t\t0, /* PTYPE 150 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */\n\t\tPKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */\n\t\tPKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */\n\t\t0, /* PTYPE 154 */\n\t\t0, /* PTYPE 155 */\n\t\t0, /* PTYPE 156 */\n\t\t0, /* PTYPE 157 */\n\t\t0, /* PTYPE 158 */\n\t\t0, /* PTYPE 159 */\n\t\t0, /* PTYPE 160 */\n\t\t0, /* PTYPE 161 */\n\t\t0, /* PTYPE 162 */\n\t\t0, /* PTYPE 163 */\n\t\t0, /* PTYPE 164 */\n\t\t0, /* PTYPE 165 */\n\t\t0, /* PTYPE 166 */\n\t\t0, /* PTYPE 167 */\n\t\t0, /* PTYPE 168 */\n\t\t0, /* PTYPE 169 */\n\t\t0, /* PTYPE 170 */\n\t\t0, /* PTYPE 171 */\n\t\t0, /* PTYPE 172 */\n\t\t0, /* PTYPE 173 */\n\t\t0, /* PTYPE 174 */\n\t\t0, /* PTYPE 175 */\n\t\t0, /* PTYPE 176 */\n\t\t0, /* PTYPE 177 */\n\t\t0, /* PTYPE 178 */\n\t\t0, /* PTYPE 179 */\n\t\t0, /* PTYPE 180 */\n\t\t0, /* PTYPE 181 */\n\t\t0, /* PTYPE 182 */\n\t\t0, /* PTYPE 183 */\n\t\t0, /* PTYPE 184 */\n\t\t0, /* PTYPE 185 */\n\t\t0, /* PTYPE 186 */\n\t\t0, /* PTYPE 187 */\n\t\t0, /* PTYPE 188 */\n\t\t0, /* PTYPE 189 */\n\t\t0, /* PTYPE 190 */\n\t\t0, /* PTYPE 191 */\n\t\t0, /* PTYPE 192 */\n\t\t0, /* PTYPE 193 */\n\t\t0, /* PTYPE 194 */\n\t\t0, /* PTYPE 195 */\n\t\t0, /* PTYPE 196 */\n\t\t0, /* PTYPE 197 */\n\t\t0, /* PTYPE 198 */\n\t\t0, /* PTYPE 199 */\n\t\t0, /* PTYPE 200 */\n\t\t0, /* PTYPE 201 */\n\t\t0, /* PTYPE 202 */\n\t\t0, /* PTYPE 203 */\n\t\t0, /* PTYPE 204 */\n\t\t0, /* PTYPE 205 */\n\t\t0, /* PTYPE 206 */\n\t\t0, /* PTYPE 207 */\n\t\t0, /* PTYPE 208 */\n\t\t0, /* PTYPE 209 */\n\t\t0, /* PTYPE 210 */\n\t\t0, /* PTYPE 211 */\n\t\t0, /* PTYPE 212 */\n\t\t0, /* PTYPE 213 */\n\t\t0, /* PTYPE 214 */\n\t\t0, /* PTYPE 215 */\n\t\t0, /* PTYPE 216 */\n\t\t0, /* PTYPE 217 */\n\t\t0, /* PTYPE 218 */\n\t\t0, /* PTYPE 219 */\n\t\t0, /* PTYPE 220 */\n\t\t0, /* PTYPE 221 */\n\t\t0, /* PTYPE 222 */\n\t\t0, /* PTYPE 223 */\n\t\t0, /* PTYPE 224 */\n\t\t0, /* PTYPE 225 */\n\t\t0, /* PTYPE 226 */\n\t\t0, /* PTYPE 227 */\n\t\t0, /* PTYPE 228 */\n\t\t0, /* PTYPE 229 */\n\t\t0, /* PTYPE 230 */\n\t\t0, /* PTYPE 231 */\n\t\t0, /* PTYPE 232 */\n\t\t0, /* PTYPE 233 */\n\t\t0, /* PTYPE 234 */\n\t\t0, /* PTYPE 235 */\n\t\t0, /* PTYPE 236 */\n\t\t0, /* PTYPE 237 */\n\t\t0, /* PTYPE 238 */\n\t\t0, /* PTYPE 239 */\n\t\t0, /* PTYPE 240 */\n\t\t0, /* PTYPE 241 */\n\t\t0, /* PTYPE 242 */\n\t\t0, /* PTYPE 243 */\n\t\t0, /* PTYPE 244 */\n\t\t0, /* PTYPE 245 */\n\t\t0, /* PTYPE 246 */\n\t\t0, /* PTYPE 247 */\n\t\t0, /* PTYPE 248 */\n\t\t0, /* PTYPE 249 */\n\t\t0, /* PTYPE 250 */\n\t\t0, /* PTYPE 251 */\n\t\t0, /* PTYPE 252 */\n\t\t0, /* PTYPE 253 */\n\t\t0, /* PTYPE 254 */\n\t\t0, /* PTYPE 255 */\n\t};\n\n\treturn ip_ptype_map[ptype];\n}\n#endif /* RTE_NEXT_ABI */\n\n#define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03\n#define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01\n#define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02\n#define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03\n#define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01\n\nstatic inline uint64_t\ni40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)\n{\n\tuint64_t flags = 0;\n#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n\tuint16_t flexbh, flexbl;\n\n\tflexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>\n\t\tI40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &\n\t\tI40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;\n\tflexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>\n\t\tI40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &\n\t\tI40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;\n\n\n\tif (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {\n\t\tmb->hash.fdir.hi =\n\t\t\trte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);\n\t\tflags |= PKT_RX_FDIR_ID;\n\t} else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {\n\t\tmb->hash.fdir.hi =\n\t\t\trte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);\n\t\tflags |= PKT_RX_FDIR_FLX;\n\t}\n\tif (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {\n\t\tmb->hash.fdir.lo =\n\t\t\trte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);\n\t\tflags |= PKT_RX_FDIR_FLX;\n\t}\n#else\n\tmb->hash.fdir.hi =\n\t\trte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);\n\tflags |= PKT_RX_FDIR_ID;\n#endif\n\treturn flags;\n}\nstatic inline void\ni40e_txd_enable_checksum(uint64_t ol_flags,\n\t\t\tuint32_t *td_cmd,\n\t\t\tuint32_t *td_offset,\n\t\t\tunion i40e_tx_offload tx_offload,\n\t\t\tuint32_t *cd_tunneling)\n{\n\t/* UDP tunneling packet TX checksum offload */\n\tif (ol_flags & PKT_TX_OUTER_IP_CKSUM) {\n\n\t\t*td_offset |= (tx_offload.outer_l2_len >> 1)\n\t\t\t\t<< I40E_TX_DESC_LENGTH_MACLEN_SHIFT;\n\n\t\tif (ol_flags & PKT_TX_OUTER_IP_CKSUM)\n\t\t\t*cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;\n\t\telse if (ol_flags & PKT_TX_OUTER_IPV4)\n\t\t\t*cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;\n\t\telse if (ol_flags & PKT_TX_OUTER_IPV6)\n\t\t\t*cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;\n\n\t\t/* Now set the ctx descriptor fields */\n\t\t*cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<\n\t\t\t\tI40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |\n\t\t\t\t(tx_offload.l2_len >> 1) <<\n\t\t\t\tI40E_TXD_CTX_QW0_NATLEN_SHIFT;\n\n\t} else\n\t\t*td_offset |= (tx_offload.l2_len >> 1)\n\t\t\t<< I40E_TX_DESC_LENGTH_MACLEN_SHIFT;\n\n\t/* Enable L3 checksum offloads */\n\tif (ol_flags & PKT_TX_IP_CKSUM) {\n\t\t*td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;\n\t\t*td_offset |= (tx_offload.l3_len >> 2)\n\t\t\t\t<< I40E_TX_DESC_LENGTH_IPLEN_SHIFT;\n\t} else if (ol_flags & PKT_TX_IPV4) {\n\t\t*td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;\n\t\t*td_offset |= (tx_offload.l3_len >> 2)\n\t\t\t\t<< I40E_TX_DESC_LENGTH_IPLEN_SHIFT;\n\t} else if (ol_flags & PKT_TX_IPV6) {\n\t\t*td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;\n\t\t*td_offset |= (tx_offload.l3_len >> 2)\n\t\t\t\t<< I40E_TX_DESC_LENGTH_IPLEN_SHIFT;\n\t}\n\n\tif (ol_flags & PKT_TX_TCP_SEG) {\n\t\t*td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;\n\t\t*td_offset |= (tx_offload.l4_len >> 2)\n\t\t\t<< I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n\t\treturn;\n\t}\n\n\t/* Enable L4 checksum offloads */\n\tswitch (ol_flags & PKT_TX_L4_MASK) {\n\tcase PKT_TX_TCP_CKSUM:\n\t\t*td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;\n\t\t*td_offset |= (sizeof(struct tcp_hdr) >> 2) <<\n\t\t\t\tI40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n\t\tbreak;\n\tcase PKT_TX_SCTP_CKSUM:\n\t\t*td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;\n\t\t*td_offset |= (sizeof(struct sctp_hdr) >> 2) <<\n\t\t\t\tI40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n\t\tbreak;\n\tcase PKT_TX_UDP_CKSUM:\n\t\t*td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;\n\t\t*td_offset |= (sizeof(struct udp_hdr) >> 2) <<\n\t\t\t\tI40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nstatic inline struct rte_mbuf *\nrte_rxmbuf_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\n\tm = __rte_mbuf_raw_alloc(mp);\n\t__rte_mbuf_sanity_check_raw(m, 0);\n\n\treturn m;\n}\n\n/* Construct the tx flags */\nstatic inline uint64_t\ni40e_build_ctob(uint32_t td_cmd,\n\t\tuint32_t td_offset,\n\t\tunsigned int size,\n\t\tuint32_t td_tag)\n{\n\treturn rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |\n\t\t\t((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |\n\t\t\t((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |\n\t\t\t((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |\n\t\t\t((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));\n}\n\nstatic inline int\ni40e_xmit_cleanup(struct i40e_tx_queue *txq)\n{\n\tstruct i40e_tx_entry *sw_ring = txq->sw_ring;\n\tvolatile struct i40e_tx_desc *txd = txq->tx_ring;\n\tuint16_t last_desc_cleaned = txq->last_desc_cleaned;\n\tuint16_t nb_tx_desc = txq->nb_tx_desc;\n\tuint16_t desc_to_clean_to;\n\tuint16_t nb_tx_to_clean;\n\n\tdesc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);\n\tif (desc_to_clean_to >= nb_tx_desc)\n\t\tdesc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);\n\n\tdesc_to_clean_to = sw_ring[desc_to_clean_to].last_id;\n\tif ((txd[desc_to_clean_to].cmd_type_offset_bsz &\n\t\t\trte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=\n\t\t\trte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {\n\t\tPMD_TX_FREE_LOG(DEBUG, \"TX descriptor %4u is not done \"\n\t\t\t\"(port=%d queue=%d)\", desc_to_clean_to,\n\t\t\t\ttxq->port_id, txq->queue_id);\n\t\treturn -1;\n\t}\n\n\tif (last_desc_cleaned > desc_to_clean_to)\n\t\tnb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +\n\t\t\t\t\t\t\tdesc_to_clean_to);\n\telse\n\t\tnb_tx_to_clean = (uint16_t)(desc_to_clean_to -\n\t\t\t\t\tlast_desc_cleaned);\n\n\ttxd[desc_to_clean_to].cmd_type_offset_bsz = 0;\n\n\ttxq->last_desc_cleaned = desc_to_clean_to;\n\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);\n\n\treturn 0;\n}\n\nstatic inline int\n#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC\ncheck_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)\n#else\ncheck_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)\n#endif\n{\n\tint ret = 0;\n\n#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC\n\tif (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {\n\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions: \"\n\t\t\t \"rxq->rx_free_thresh=%d, \"\n\t\t\t \"RTE_PMD_I40E_RX_MAX_BURST=%d\",\n\t\t\t rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);\n\t\tret = -EINVAL;\n\t} else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {\n\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions: \"\n\t\t\t \"rxq->rx_free_thresh=%d, \"\n\t\t\t \"rxq->nb_rx_desc=%d\",\n\t\t\t rxq->rx_free_thresh, rxq->nb_rx_desc);\n\t\tret = -EINVAL;\n\t} else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {\n\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions: \"\n\t\t\t \"rxq->nb_rx_desc=%d, \"\n\t\t\t \"rxq->rx_free_thresh=%d\",\n\t\t\t rxq->nb_rx_desc, rxq->rx_free_thresh);\n\t\tret = -EINVAL;\n\t} else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -\n\t\t\t\tRTE_PMD_I40E_RX_MAX_BURST))) {\n\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions: \"\n\t\t\t \"rxq->nb_rx_desc=%d, \"\n\t\t\t \"I40E_MAX_RING_DESC=%d, \"\n\t\t\t \"RTE_PMD_I40E_RX_MAX_BURST=%d\",\n\t\t\t rxq->nb_rx_desc, I40E_MAX_RING_DESC,\n\t\t\t RTE_PMD_I40E_RX_MAX_BURST);\n\t\tret = -EINVAL;\n\t}\n#else\n\tret = -EINVAL;\n#endif\n\n\treturn ret;\n}\n\n#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC\n#define I40E_LOOK_AHEAD 8\n#if (I40E_LOOK_AHEAD != 8)\n#error \"PMD I40E: I40E_LOOK_AHEAD must be 8\\n\"\n#endif\nstatic inline int\ni40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)\n{\n\tvolatile union i40e_rx_desc *rxdp;\n\tstruct i40e_rx_entry *rxep;\n\tstruct rte_mbuf *mb;\n\tuint16_t pkt_len;\n\tuint64_t qword1;\n\tuint32_t rx_status;\n\tint32_t s[I40E_LOOK_AHEAD], nb_dd;\n\tint32_t i, j, nb_rx = 0;\n\tuint64_t pkt_flags;\n\n\trxdp = &rxq->rx_ring[rxq->rx_tail];\n\trxep = &rxq->sw_ring[rxq->rx_tail];\n\n\tqword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);\n\trx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>\n\t\t\t\tI40E_RXD_QW1_STATUS_SHIFT;\n\n\t/* Make sure there is at least 1 packet to receive */\n\tif (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))\n\t\treturn 0;\n\n\t/**\n\t * Scan LOOK_AHEAD descriptors at a time to determine which\n\t * descriptors reference packets that are ready to be received.\n\t */\n\tfor (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,\n\t\t\trxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {\n\t\t/* Read desc statuses backwards to avoid race condition */\n\t\tfor (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {\n\t\t\tqword1 = rte_le_to_cpu_64(\\\n\t\t\t\trxdp[j].wb.qword1.status_error_len);\n\t\t\ts[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>\n\t\t\t\t\tI40E_RXD_QW1_STATUS_SHIFT;\n\t\t}\n\n\t\t/* Compute how many status bits were set */\n\t\tfor (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)\n\t\t\tnb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);\n\n\t\tnb_rx += nb_dd;\n\n\t\t/* Translate descriptor info to mbuf parameters */\n\t\tfor (j = 0; j < nb_dd; j++) {\n\t\t\tmb = rxep[j].mbuf;\n\t\t\tqword1 = rte_le_to_cpu_64(\\\n\t\t\t\trxdp[j].wb.qword1.status_error_len);\n\t\t\tpkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>\n\t\t\t\tI40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;\n\t\t\tmb->data_len = pkt_len;\n\t\t\tmb->pkt_len = pkt_len;\n\t\t\tmb->ol_flags = 0;\n\t\t\ti40e_rxd_to_vlan_tci(mb, &rxdp[j]);\n\t\t\tpkt_flags = i40e_rxd_status_to_pkt_flags(qword1);\n\t\t\tpkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);\n#ifdef RTE_NEXT_ABI\n\t\t\tmb->packet_type =\n\t\t\t\ti40e_rxd_pkt_type_mapping((uint8_t)((qword1 &\n\t\t\t\t\t\tI40E_RXD_QW1_PTYPE_MASK) >>\n\t\t\t\t\t\tI40E_RXD_QW1_PTYPE_SHIFT));\n#else\n\t\t\tpkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);\n\n\t\t\tmb->packet_type = (uint16_t)((qword1 &\n\t\t\t\t\tI40E_RXD_QW1_PTYPE_MASK) >>\n\t\t\t\t\tI40E_RXD_QW1_PTYPE_SHIFT);\n#endif /* RTE_NEXT_ABI */\n\t\t\tif (pkt_flags & PKT_RX_RSS_HASH)\n\t\t\t\tmb->hash.rss = rte_le_to_cpu_32(\\\n\t\t\t\t\trxdp[j].wb.qword0.hi_dword.rss);\n\t\t\tif (pkt_flags & PKT_RX_FDIR)\n\t\t\t\tpkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);\n\n#ifdef RTE_LIBRTE_IEEE1588\n\t\t\tpkt_flags |= i40e_get_iee15888_flags(mb, qword1);\n#endif\n\t\t\tmb->ol_flags |= pkt_flags;\n\n\t\t}\n\n\t\tfor (j = 0; j < I40E_LOOK_AHEAD; j++)\n\t\t\trxq->rx_stage[i + j] = rxep[j].mbuf;\n\n\t\tif (nb_dd != I40E_LOOK_AHEAD)\n\t\t\tbreak;\n\t}\n\n\t/* Clear software ring entries */\n\tfor (i = 0; i < nb_rx; i++)\n\t\trxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;\n\n\treturn nb_rx;\n}\n\nstatic inline uint16_t\ni40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,\n\t\t\tstruct rte_mbuf **rx_pkts,\n\t\t\tuint16_t nb_pkts)\n{\n\tuint16_t i;\n\tstruct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];\n\n\tnb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);\n\n\tfor (i = 0; i < nb_pkts; i++)\n\t\trx_pkts[i] = stage[i];\n\n\trxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);\n\trxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);\n\n\treturn nb_pkts;\n}\n\nstatic inline int\ni40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)\n{\n\tvolatile union i40e_rx_desc *rxdp;\n\tstruct i40e_rx_entry *rxep;\n\tstruct rte_mbuf *mb;\n\tuint16_t alloc_idx, i;\n\tuint64_t dma_addr;\n\tint diag;\n\n\t/* Allocate buffers in bulk */\n\talloc_idx = (uint16_t)(rxq->rx_free_trigger -\n\t\t\t\t(rxq->rx_free_thresh - 1));\n\trxep = &(rxq->sw_ring[alloc_idx]);\n\tdiag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,\n\t\t\t\t\trxq->rx_free_thresh);\n\tif (unlikely(diag != 0)) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to get mbufs in bulk\");\n\t\treturn -ENOMEM;\n\t}\n\n\trxdp = &rxq->rx_ring[alloc_idx];\n\tfor (i = 0; i < rxq->rx_free_thresh; i++) {\n\t\tif (likely(i < (rxq->rx_free_thresh - 1)))\n\t\t\t/* Prefetch next mbuf */\n\t\t\trte_prefetch0(rxep[i + 1].mbuf);\n\n\t\tmb = rxep[i].mbuf;\n\t\trte_mbuf_refcnt_set(mb, 1);\n\t\tmb->next = NULL;\n\t\tmb->data_off = RTE_PKTMBUF_HEADROOM;\n\t\tmb->nb_segs = 1;\n\t\tmb->port = rxq->port_id;\n\t\tdma_addr = rte_cpu_to_le_64(\\\n\t\t\tRTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));\n\t\trxdp[i].read.hdr_addr = 0;\n\t\trxdp[i].read.pkt_addr = dma_addr;\n\t}\n\n\t/* Update rx tail regsiter */\n\trte_wmb();\n\tI40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);\n\n\trxq->rx_free_trigger =\n\t\t(uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);\n\tif (rxq->rx_free_trigger >= rxq->nb_rx_desc)\n\t\trxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);\n\n\treturn 0;\n}\n\nstatic inline uint16_t\nrx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n{\n\tstruct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;\n\tuint16_t nb_rx = 0;\n\n\tif (!nb_pkts)\n\t\treturn 0;\n\n\tif (rxq->rx_nb_avail)\n\t\treturn i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);\n\n\tnb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);\n\trxq->rx_next_avail = 0;\n\trxq->rx_nb_avail = nb_rx;\n\trxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);\n\n\tif (rxq->rx_tail > rxq->rx_free_trigger) {\n\t\tif (i40e_rx_alloc_bufs(rxq) != 0) {\n\t\t\tuint16_t i, j;\n\n\t\t\tPMD_RX_LOG(DEBUG, \"Rx mbuf alloc failed for \"\n\t\t\t\t \"port_id=%u, queue_id=%u\",\n\t\t\t\t rxq->port_id, rxq->queue_id);\n\t\t\trxq->rx_nb_avail = 0;\n\t\t\trxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);\n\t\t\tfor (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)\n\t\t\t\trxq->sw_ring[j].mbuf = rxq->rx_stage[i];\n\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\tif (rxq->rx_tail >= rxq->nb_rx_desc)\n\t\trxq->rx_tail = 0;\n\n\tif (rxq->rx_nb_avail)\n\t\treturn i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);\n\n\treturn 0;\n}\n\nstatic uint16_t\ni40e_recv_pkts_bulk_alloc(void *rx_queue,\n\t\t\t struct rte_mbuf **rx_pkts,\n\t\t\t uint16_t nb_pkts)\n{\n\tuint16_t nb_rx = 0, n, count;\n\n\tif (unlikely(nb_pkts == 0))\n\t\treturn 0;\n\n\tif (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))\n\t\treturn rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);\n\n\twhile (nb_pkts) {\n\t\tn = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);\n\t\tcount = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);\n\t\tnb_rx = (uint16_t)(nb_rx + count);\n\t\tnb_pkts = (uint16_t)(nb_pkts - count);\n\t\tif (count < n)\n\t\t\tbreak;\n\t}\n\n\treturn nb_rx;\n}\n#endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */\n\nuint16_t\ni40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n{\n\tstruct i40e_rx_queue *rxq;\n\tvolatile union i40e_rx_desc *rx_ring;\n\tvolatile union i40e_rx_desc *rxdp;\n\tunion i40e_rx_desc rxd;\n\tstruct i40e_rx_entry *sw_ring;\n\tstruct i40e_rx_entry *rxe;\n\tstruct rte_mbuf *rxm;\n\tstruct rte_mbuf *nmb;\n\tuint16_t nb_rx;\n\tuint32_t rx_status;\n\tuint64_t qword1;\n\tuint16_t rx_packet_len;\n\tuint16_t rx_id, nb_hold;\n\tuint64_t dma_addr;\n\tuint64_t pkt_flags;\n\n\tnb_rx = 0;\n\tnb_hold = 0;\n\trxq = rx_queue;\n\trx_id = rxq->rx_tail;\n\trx_ring = rxq->rx_ring;\n\tsw_ring = rxq->sw_ring;\n\n\twhile (nb_rx < nb_pkts) {\n\t\trxdp = &rx_ring[rx_id];\n\t\tqword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);\n\t\trx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)\n\t\t\t\t>> I40E_RXD_QW1_STATUS_SHIFT;\n\n\t\t/* Check the DD bit first */\n\t\tif (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))\n\t\t\tbreak;\n\n\t\tnmb = rte_rxmbuf_alloc(rxq->mp);\n\t\tif (unlikely(!nmb))\n\t\t\tbreak;\n\t\trxd = *rxdp;\n\n\t\tnb_hold++;\n\t\trxe = &sw_ring[rx_id];\n\t\trx_id++;\n\t\tif (unlikely(rx_id == rxq->nb_rx_desc))\n\t\t\trx_id = 0;\n\n\t\t/* Prefetch next mbuf */\n\t\trte_prefetch0(sw_ring[rx_id].mbuf);\n\n\t\t/**\n\t\t * When next RX descriptor is on a cache line boundary,\n\t\t * prefetch the next 4 RX descriptors and next 8 pointers\n\t\t * to mbufs.\n\t\t */\n\t\tif ((rx_id & 0x3) == 0) {\n\t\t\trte_prefetch0(&rx_ring[rx_id]);\n\t\t\trte_prefetch0(&sw_ring[rx_id]);\n\t\t}\n\t\trxm = rxe->mbuf;\n\t\trxe->mbuf = nmb;\n\t\tdma_addr =\n\t\t\trte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));\n\t\trxdp->read.hdr_addr = 0;\n\t\trxdp->read.pkt_addr = dma_addr;\n\n\t\trx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>\n\t\t\t\tI40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;\n\n\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n\t\trte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));\n\t\trxm->nb_segs = 1;\n\t\trxm->next = NULL;\n\t\trxm->pkt_len = rx_packet_len;\n\t\trxm->data_len = rx_packet_len;\n\t\trxm->port = rxq->port_id;\n\t\trxm->ol_flags = 0;\n\t\ti40e_rxd_to_vlan_tci(rxm, &rxd);\n\t\tpkt_flags = i40e_rxd_status_to_pkt_flags(qword1);\n\t\tpkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);\n#ifdef RTE_NEXT_ABI\n\t\trxm->packet_type =\n\t\t\ti40e_rxd_pkt_type_mapping((uint8_t)((qword1 &\n\t\t\tI40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));\n#else\n\t\tpkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);\n\t\trxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>\n\t\t\t\tI40E_RXD_QW1_PTYPE_SHIFT);\n#endif /* RTE_NEXT_ABI */\n\t\tif (pkt_flags & PKT_RX_RSS_HASH)\n\t\t\trxm->hash.rss =\n\t\t\t\trte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);\n\t\tif (pkt_flags & PKT_RX_FDIR)\n\t\t\tpkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);\n\n#ifdef RTE_LIBRTE_IEEE1588\n\t\tpkt_flags |= i40e_get_iee15888_flags(rxm, qword1);\n#endif\n\t\trxm->ol_flags |= pkt_flags;\n\n\t\trx_pkts[nb_rx++] = rxm;\n\t}\n\trxq->rx_tail = rx_id;\n\n\t/**\n\t * If the number of free RX descriptors is greater than the RX free\n\t * threshold of the queue, advance the receive tail register of queue.\n\t * Update that register with the value of the last processed RX\n\t * descriptor minus 1.\n\t */\n\tnb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);\n\tif (nb_hold > rxq->rx_free_thresh) {\n\t\trx_id = (uint16_t) ((rx_id == 0) ?\n\t\t\t(rxq->nb_rx_desc - 1) : (rx_id - 1));\n\t\tI40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);\n\t\tnb_hold = 0;\n\t}\n\trxq->nb_rx_hold = nb_hold;\n\n\treturn nb_rx;\n}\n\nuint16_t\ni40e_recv_scattered_pkts(void *rx_queue,\n\t\t\t struct rte_mbuf **rx_pkts,\n\t\t\t uint16_t nb_pkts)\n{\n\tstruct i40e_rx_queue *rxq = rx_queue;\n\tvolatile union i40e_rx_desc *rx_ring = rxq->rx_ring;\n\tvolatile union i40e_rx_desc *rxdp;\n\tunion i40e_rx_desc rxd;\n\tstruct i40e_rx_entry *sw_ring = rxq->sw_ring;\n\tstruct i40e_rx_entry *rxe;\n\tstruct rte_mbuf *first_seg = rxq->pkt_first_seg;\n\tstruct rte_mbuf *last_seg = rxq->pkt_last_seg;\n\tstruct rte_mbuf *nmb, *rxm;\n\tuint16_t rx_id = rxq->rx_tail;\n\tuint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;\n\tuint32_t rx_status;\n\tuint64_t qword1;\n\tuint64_t dma_addr;\n\tuint64_t pkt_flags;\n\n\twhile (nb_rx < nb_pkts) {\n\t\trxdp = &rx_ring[rx_id];\n\t\tqword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);\n\t\trx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>\n\t\t\t\t\tI40E_RXD_QW1_STATUS_SHIFT;\n\n\t\t/* Check the DD bit */\n\t\tif (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))\n\t\t\tbreak;\n\n\t\tnmb = rte_rxmbuf_alloc(rxq->mp);\n\t\tif (unlikely(!nmb))\n\t\t\tbreak;\n\t\trxd = *rxdp;\n\t\tnb_hold++;\n\t\trxe = &sw_ring[rx_id];\n\t\trx_id++;\n\t\tif (rx_id == rxq->nb_rx_desc)\n\t\t\trx_id = 0;\n\n\t\t/* Prefetch next mbuf */\n\t\trte_prefetch0(sw_ring[rx_id].mbuf);\n\n\t\t/**\n\t\t * When next RX descriptor is on a cache line boundary,\n\t\t * prefetch the next 4 RX descriptors and next 8 pointers\n\t\t * to mbufs.\n\t\t */\n\t\tif ((rx_id & 0x3) == 0) {\n\t\t\trte_prefetch0(&rx_ring[rx_id]);\n\t\t\trte_prefetch0(&sw_ring[rx_id]);\n\t\t}\n\n\t\trxm = rxe->mbuf;\n\t\trxe->mbuf = nmb;\n\t\tdma_addr =\n\t\t\trte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));\n\n\t\t/* Set data buffer address and data length of the mbuf */\n\t\trxdp->read.hdr_addr = 0;\n\t\trxdp->read.pkt_addr = dma_addr;\n\t\trx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>\n\t\t\t\t\tI40E_RXD_QW1_LENGTH_PBUF_SHIFT;\n\t\trxm->data_len = rx_packet_len;\n\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n\n\t\t/**\n\t\t * If this is the first buffer of the received packet, set the\n\t\t * pointer to the first mbuf of the packet and initialize its\n\t\t * context. Otherwise, update the total length and the number\n\t\t * of segments of the current scattered packet, and update the\n\t\t * pointer to the last mbuf of the current packet.\n\t\t */\n\t\tif (!first_seg) {\n\t\t\tfirst_seg = rxm;\n\t\t\tfirst_seg->nb_segs = 1;\n\t\t\tfirst_seg->pkt_len = rx_packet_len;\n\t\t} else {\n\t\t\tfirst_seg->pkt_len =\n\t\t\t\t(uint16_t)(first_seg->pkt_len +\n\t\t\t\t\t\trx_packet_len);\n\t\t\tfirst_seg->nb_segs++;\n\t\t\tlast_seg->next = rxm;\n\t\t}\n\n\t\t/**\n\t\t * If this is not the last buffer of the received packet,\n\t\t * update the pointer to the last mbuf of the current scattered\n\t\t * packet and continue to parse the RX ring.\n\t\t */\n\t\tif (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {\n\t\t\tlast_seg = rxm;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/**\n\t\t * This is the last buffer of the received packet. If the CRC\n\t\t * is not stripped by the hardware:\n\t\t * - Subtract the CRC length from the total packet length.\n\t\t * - If the last buffer only contains the whole CRC or a part\n\t\t * of it, free the mbuf associated to the last buffer. If part\n\t\t * of the CRC is also contained in the previous mbuf, subtract\n\t\t * the length of that CRC part from the data length of the\n\t\t * previous mbuf.\n\t\t */\n\t\trxm->next = NULL;\n\t\tif (unlikely(rxq->crc_len > 0)) {\n\t\t\tfirst_seg->pkt_len -= ETHER_CRC_LEN;\n\t\t\tif (rx_packet_len <= ETHER_CRC_LEN) {\n\t\t\t\trte_pktmbuf_free_seg(rxm);\n\t\t\t\tfirst_seg->nb_segs--;\n\t\t\t\tlast_seg->data_len =\n\t\t\t\t\t(uint16_t)(last_seg->data_len -\n\t\t\t\t\t(ETHER_CRC_LEN - rx_packet_len));\n\t\t\t\tlast_seg->next = NULL;\n\t\t\t} else\n\t\t\t\trxm->data_len = (uint16_t)(rx_packet_len -\n\t\t\t\t\t\t\t\tETHER_CRC_LEN);\n\t\t}\n\n\t\tfirst_seg->port = rxq->port_id;\n\t\tfirst_seg->ol_flags = 0;\n\t\ti40e_rxd_to_vlan_tci(first_seg, &rxd);\n\t\tpkt_flags = i40e_rxd_status_to_pkt_flags(qword1);\n\t\tpkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);\n#ifdef RTE_NEXT_ABI\n\t\tfirst_seg->packet_type =\n\t\t\ti40e_rxd_pkt_type_mapping((uint8_t)((qword1 &\n\t\t\tI40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));\n#else\n\t\tpkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);\n\t\tfirst_seg->packet_type = (uint16_t)((qword1 &\n\t\t\t\t\tI40E_RXD_QW1_PTYPE_MASK) >>\n\t\t\t\t\tI40E_RXD_QW1_PTYPE_SHIFT);\n#endif /* RTE_NEXT_ABI */\n\t\tif (pkt_flags & PKT_RX_RSS_HASH)\n\t\t\trxm->hash.rss =\n\t\t\t\trte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);\n\t\tif (pkt_flags & PKT_RX_FDIR)\n\t\t\tpkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);\n\n#ifdef RTE_LIBRTE_IEEE1588\n\t\tpkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);\n#endif\n\t\tfirst_seg->ol_flags |= pkt_flags;\n\n\t\t/* Prefetch data of first segment, if configured to do so. */\n\t\trte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,\n\t\t\tfirst_seg->data_off));\n\t\trx_pkts[nb_rx++] = first_seg;\n\t\tfirst_seg = NULL;\n\t}\n\n\t/* Record index of the next RX descriptor to probe. */\n\trxq->rx_tail = rx_id;\n\trxq->pkt_first_seg = first_seg;\n\trxq->pkt_last_seg = last_seg;\n\n\t/**\n\t * If the number of free RX descriptors is greater than the RX free\n\t * threshold of the queue, advance the Receive Descriptor Tail (RDT)\n\t * register. Update the RDT with the value of the last processed RX\n\t * descriptor minus 1, to guarantee that the RDT register is never\n\t * equal to the RDH register, which creates a \"full\" ring situtation\n\t * from the hardware point of view.\n\t */\n\tnb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);\n\tif (nb_hold > rxq->rx_free_thresh) {\n\t\trx_id = (uint16_t)(rx_id == 0 ?\n\t\t\t(rxq->nb_rx_desc - 1) : (rx_id - 1));\n\t\tI40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);\n\t\tnb_hold = 0;\n\t}\n\trxq->nb_rx_hold = nb_hold;\n\n\treturn nb_rx;\n}\n\n/* Check if the context descriptor is needed for TX offloading */\nstatic inline uint16_t\ni40e_calc_context_desc(uint64_t flags)\n{\n\tstatic uint64_t mask = PKT_TX_OUTER_IP_CKSUM |\n\t\tPKT_TX_TCP_SEG |\n\t\tPKT_TX_QINQ_PKT;\n\n#ifdef RTE_LIBRTE_IEEE1588\n\tmask |= PKT_TX_IEEE1588_TMST;\n#endif\n\n\treturn ((flags & mask) ? 1 : 0);\n}\n\n/* set i40e TSO context descriptor */\nstatic inline uint64_t\ni40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)\n{\n\tuint64_t ctx_desc = 0;\n\tuint32_t cd_cmd, hdr_len, cd_tso_len;\n\n\tif (!tx_offload.l4_len) {\n\t\tPMD_DRV_LOG(DEBUG, \"L4 length set to 0\");\n\t\treturn ctx_desc;\n\t}\n\n\t/**\n\t * in case of tunneling packet, the outer_l2_len and\n\t * outer_l3_len must be 0.\n\t */\n\thdr_len = tx_offload.outer_l2_len +\n\t\ttx_offload.outer_l3_len +\n\t\ttx_offload.l2_len +\n\t\ttx_offload.l3_len +\n\t\ttx_offload.l4_len;\n\n\tcd_cmd = I40E_TX_CTX_DESC_TSO;\n\tcd_tso_len = mbuf->pkt_len - hdr_len;\n\tctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |\n\t\t((uint64_t)cd_tso_len <<\n\t\t I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |\n\t\t((uint64_t)mbuf->tso_segsz <<\n\t\t I40E_TXD_CTX_QW1_MSS_SHIFT);\n\n\treturn ctx_desc;\n}\n\nuint16_t\ni40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n{\n\tstruct i40e_tx_queue *txq;\n\tstruct i40e_tx_entry *sw_ring;\n\tstruct i40e_tx_entry *txe, *txn;\n\tvolatile struct i40e_tx_desc *txd;\n\tvolatile struct i40e_tx_desc *txr;\n\tstruct rte_mbuf *tx_pkt;\n\tstruct rte_mbuf *m_seg;\n\tuint32_t cd_tunneling_params;\n\tuint16_t tx_id;\n\tuint16_t nb_tx;\n\tuint32_t td_cmd;\n\tuint32_t td_offset;\n\tuint32_t tx_flags;\n\tuint32_t td_tag;\n\tuint64_t ol_flags;\n\tuint16_t nb_used;\n\tuint16_t nb_ctx;\n\tuint16_t tx_last;\n\tuint16_t slen;\n\tuint64_t buf_dma_addr;\n\tunion i40e_tx_offload tx_offload = {0};\n\n\ttxq = tx_queue;\n\tsw_ring = txq->sw_ring;\n\ttxr = txq->tx_ring;\n\ttx_id = txq->tx_tail;\n\ttxe = &sw_ring[tx_id];\n\n\t/* Check if the descriptor ring needs to be cleaned. */\n\tif (txq->nb_tx_free < txq->tx_free_thresh)\n\t\ti40e_xmit_cleanup(txq);\n\n\tfor (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {\n\t\ttd_cmd = 0;\n\t\ttd_tag = 0;\n\t\ttd_offset = 0;\n\t\ttx_flags = 0;\n\n\t\ttx_pkt = *tx_pkts++;\n\t\tRTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);\n\n\t\tol_flags = tx_pkt->ol_flags;\n\t\ttx_offload.l2_len = tx_pkt->l2_len;\n\t\ttx_offload.l3_len = tx_pkt->l3_len;\n\t\ttx_offload.outer_l2_len = tx_pkt->outer_l2_len;\n\t\ttx_offload.outer_l3_len = tx_pkt->outer_l3_len;\n\t\ttx_offload.l4_len = tx_pkt->l4_len;\n\t\ttx_offload.tso_segsz = tx_pkt->tso_segsz;\n\n\t\t/* Calculate the number of context descriptors needed. */\n\t\tnb_ctx = i40e_calc_context_desc(ol_flags);\n\n\t\t/**\n\t\t * The number of descriptors that must be allocated for\n\t\t * a packet equals to the number of the segments of that\n\t\t * packet plus 1 context descriptor if needed.\n\t\t */\n\t\tnb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);\n\t\ttx_last = (uint16_t)(tx_id + nb_used - 1);\n\n\t\t/* Circular ring */\n\t\tif (tx_last >= txq->nb_tx_desc)\n\t\t\ttx_last = (uint16_t)(tx_last - txq->nb_tx_desc);\n\n\t\tif (nb_used > txq->nb_tx_free) {\n\t\t\tif (i40e_xmit_cleanup(txq) != 0) {\n\t\t\t\tif (nb_tx == 0)\n\t\t\t\t\treturn 0;\n\t\t\t\tgoto end_of_tx;\n\t\t\t}\n\t\t\tif (unlikely(nb_used > txq->tx_rs_thresh)) {\n\t\t\t\twhile (nb_used > txq->nb_tx_free) {\n\t\t\t\t\tif (i40e_xmit_cleanup(txq) != 0) {\n\t\t\t\t\t\tif (nb_tx == 0)\n\t\t\t\t\t\t\treturn 0;\n\t\t\t\t\t\tgoto end_of_tx;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* Descriptor based VLAN insertion */\n\t\tif (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {\n\t\t\ttx_flags |= tx_pkt->vlan_tci <<\n\t\t\t\tI40E_TX_FLAG_L2TAG1_SHIFT;\n\t\t\ttx_flags |= I40E_TX_FLAG_INSERT_VLAN;\n\t\t\ttd_cmd |= I40E_TX_DESC_CMD_IL2TAG1;\n\t\t\ttd_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>\n\t\t\t\t\t\tI40E_TX_FLAG_L2TAG1_SHIFT;\n\t\t}\n\n\t\t/* Always enable CRC offload insertion */\n\t\ttd_cmd |= I40E_TX_DESC_CMD_ICRC;\n\n\t\t/* Enable checksum offloading */\n\t\tcd_tunneling_params = 0;\n\t\tif (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {\n\t\t\ti40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,\n\t\t\t\ttx_offload, &cd_tunneling_params);\n\t\t}\n\n\t\tif (nb_ctx) {\n\t\t\t/* Setup TX context descriptor if required */\n\t\t\tvolatile struct i40e_tx_context_desc *ctx_txd =\n\t\t\t\t(volatile struct i40e_tx_context_desc *)\\\n\t\t\t\t\t\t\t&txr[tx_id];\n\t\t\tuint16_t cd_l2tag2 = 0;\n\t\t\tuint64_t cd_type_cmd_tso_mss =\n\t\t\t\tI40E_TX_DESC_DTYPE_CONTEXT;\n\n\t\t\ttxn = &sw_ring[txe->next_id];\n\t\t\tRTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);\n\t\t\tif (txe->mbuf != NULL) {\n\t\t\t\trte_pktmbuf_free_seg(txe->mbuf);\n\t\t\t\ttxe->mbuf = NULL;\n\t\t\t}\n\n\t\t\t/* TSO enabled means no timestamp */\n\t\t\tif (ol_flags & PKT_TX_TCP_SEG)\n\t\t\t\tcd_type_cmd_tso_mss |=\n\t\t\t\t\ti40e_set_tso_ctx(tx_pkt, tx_offload);\n\t\t\telse {\n#ifdef RTE_LIBRTE_IEEE1588\n\t\t\t\tif (ol_flags & PKT_TX_IEEE1588_TMST)\n\t\t\t\t\tcd_type_cmd_tso_mss |=\n\t\t\t\t\t\t((uint64_t)I40E_TX_CTX_DESC_TSYN <<\n\t\t\t\t\t\t I40E_TXD_CTX_QW1_CMD_SHIFT);\n#endif\n\t\t\t}\n\n\t\t\tctx_txd->tunneling_params =\n\t\t\t\trte_cpu_to_le_32(cd_tunneling_params);\n\t\t\tif (ol_flags & PKT_TX_QINQ_PKT) {\n\t\t\t\tcd_l2tag2 = tx_pkt->vlan_tci_outer;\n\t\t\t\tcd_type_cmd_tso_mss |=\n\t\t\t\t\t((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<\n\t\t\t\t\t\tI40E_TXD_CTX_QW1_CMD_SHIFT);\n\t\t\t}\n\t\t\tctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);\n\t\t\tctx_txd->type_cmd_tso_mss =\n\t\t\t\trte_cpu_to_le_64(cd_type_cmd_tso_mss);\n\n\t\t\tPMD_TX_LOG(DEBUG, \"mbuf: %p, TCD[%u]:\\n\"\n\t\t\t\t\"tunneling_params: %#x;\\n\"\n\t\t\t\t\"l2tag2: %#hx;\\n\"\n\t\t\t\t\"rsvd: %#hx;\\n\"\n\t\t\t\t\"type_cmd_tso_mss: %#\"PRIx64\";\\n\",\n\t\t\t\ttx_pkt, tx_id,\n\t\t\t\tctx_txd->tunneling_params,\n\t\t\t\tctx_txd->l2tag2,\n\t\t\t\tctx_txd->rsvd,\n\t\t\t\tctx_txd->type_cmd_tso_mss);\n\n\t\t\ttxe->last_id = tx_last;\n\t\t\ttx_id = txe->next_id;\n\t\t\ttxe = txn;\n\t\t}\n\n\t\tm_seg = tx_pkt;\n\t\tdo {\n\t\t\ttxd = &txr[tx_id];\n\t\t\ttxn = &sw_ring[txe->next_id];\n\n\t\t\tif (txe->mbuf)\n\t\t\t\trte_pktmbuf_free_seg(txe->mbuf);\n\t\t\ttxe->mbuf = m_seg;\n\n\t\t\t/* Setup TX Descriptor */\n\t\t\tslen = m_seg->data_len;\n\t\t\tbuf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);\n\n\t\t\tPMD_TX_LOG(DEBUG, \"mbuf: %p, TDD[%u]:\\n\"\n\t\t\t\t\"buf_dma_addr: %#\"PRIx64\";\\n\"\n\t\t\t\t\"td_cmd: %#x;\\n\"\n\t\t\t\t\"td_offset: %#x;\\n\"\n\t\t\t\t\"td_len: %u;\\n\"\n\t\t\t\t\"td_tag: %#x;\\n\",\n\t\t\t\ttx_pkt, tx_id, buf_dma_addr,\n\t\t\t\ttd_cmd, td_offset, slen, td_tag);\n\n\t\t\ttxd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);\n\t\t\ttxd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,\n\t\t\t\t\t\ttd_offset, slen, td_tag);\n\t\t\ttxe->last_id = tx_last;\n\t\t\ttx_id = txe->next_id;\n\t\t\ttxe = txn;\n\t\t\tm_seg = m_seg->next;\n\t\t} while (m_seg != NULL);\n\n\t\t/* The last packet data descriptor needs End Of Packet (EOP) */\n\t\ttd_cmd |= I40E_TX_DESC_CMD_EOP;\n\t\ttxq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);\n\t\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);\n\n\t\tif (txq->nb_tx_used >= txq->tx_rs_thresh) {\n\t\t\tPMD_TX_FREE_LOG(DEBUG,\n\t\t\t\t\t\"Setting RS bit on TXD id=\"\n\t\t\t\t\t\"%4u (port=%d queue=%d)\",\n\t\t\t\t\ttx_last, txq->port_id, txq->queue_id);\n\n\t\t\ttd_cmd |= I40E_TX_DESC_CMD_RS;\n\n\t\t\t/* Update txq RS bit counters */\n\t\t\ttxq->nb_tx_used = 0;\n\t\t}\n\n\t\ttxd->cmd_type_offset_bsz |=\n\t\t\trte_cpu_to_le_64(((uint64_t)td_cmd) <<\n\t\t\t\t\tI40E_TXD_QW1_CMD_SHIFT);\n\t}\n\nend_of_tx:\n\trte_wmb();\n\n\tPMD_TX_LOG(DEBUG, \"port_id=%u queue_id=%u tx_tail=%u nb_tx=%u\",\n\t\t (unsigned) txq->port_id, (unsigned) txq->queue_id,\n\t\t (unsigned) tx_id, (unsigned) nb_tx);\n\n\tI40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);\n\ttxq->tx_tail = tx_id;\n\n\treturn nb_tx;\n}\n\nstatic inline int __attribute__((always_inline))\ni40e_tx_free_bufs(struct i40e_tx_queue *txq)\n{\n\tstruct i40e_tx_entry *txep;\n\tuint16_t i;\n\n\tif ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &\n\t\t\trte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=\n\t\t\trte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))\n\t\treturn 0;\n\n\ttxep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);\n\n\tfor (i = 0; i < txq->tx_rs_thresh; i++)\n\t\trte_prefetch0((txep + i)->mbuf);\n\n\tif (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {\n\t\tfor (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {\n\t\t\trte_mempool_put(txep->mbuf->pool, txep->mbuf);\n\t\t\ttxep->mbuf = NULL;\n\t\t}\n\t} else {\n\t\tfor (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {\n\t\t\trte_pktmbuf_free_seg(txep->mbuf);\n\t\t\ttxep->mbuf = NULL;\n\t\t}\n\t}\n\n\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);\n\ttxq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);\n\tif (txq->tx_next_dd >= txq->nb_tx_desc)\n\t\ttxq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);\n\n\treturn txq->tx_rs_thresh;\n}\n\n#define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\\\n\t\t I40E_TX_DESC_CMD_EOP)\n\n/* Populate 4 descriptors with data from 4 mbufs */\nstatic inline void\ntx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)\n{\n\tuint64_t dma_addr;\n\tuint32_t i;\n\n\tfor (i = 0; i < 4; i++, txdp++, pkts++) {\n\t\tdma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);\n\t\ttxdp->buffer_addr = rte_cpu_to_le_64(dma_addr);\n\t\ttxdp->cmd_type_offset_bsz =\n\t\t\ti40e_build_ctob((uint32_t)I40E_TD_CMD, 0,\n\t\t\t\t\t(*pkts)->data_len, 0);\n\t}\n}\n\n/* Populate 1 descriptor with data from 1 mbuf */\nstatic inline void\ntx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)\n{\n\tuint64_t dma_addr;\n\n\tdma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);\n\ttxdp->buffer_addr = rte_cpu_to_le_64(dma_addr);\n\ttxdp->cmd_type_offset_bsz =\n\t\ti40e_build_ctob((uint32_t)I40E_TD_CMD, 0,\n\t\t\t\t(*pkts)->data_len, 0);\n}\n\n/* Fill hardware descriptor ring with mbuf data */\nstatic inline void\ni40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,\n\t\t struct rte_mbuf **pkts,\n\t\t uint16_t nb_pkts)\n{\n\tvolatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);\n\tstruct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);\n\tconst int N_PER_LOOP = 4;\n\tconst int N_PER_LOOP_MASK = N_PER_LOOP - 1;\n\tint mainpart, leftover;\n\tint i, j;\n\n\tmainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));\n\tleftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));\n\tfor (i = 0; i < mainpart; i += N_PER_LOOP) {\n\t\tfor (j = 0; j < N_PER_LOOP; ++j) {\n\t\t\t(txep + i + j)->mbuf = *(pkts + i + j);\n\t\t}\n\t\ttx4(txdp + i, pkts + i);\n\t}\n\tif (unlikely(leftover > 0)) {\n\t\tfor (i = 0; i < leftover; ++i) {\n\t\t\t(txep + mainpart + i)->mbuf = *(pkts + mainpart + i);\n\t\t\ttx1(txdp + mainpart + i, pkts + mainpart + i);\n\t\t}\n\t}\n}\n\nstatic inline uint16_t\ntx_xmit_pkts(struct i40e_tx_queue *txq,\n\t struct rte_mbuf **tx_pkts,\n\t uint16_t nb_pkts)\n{\n\tvolatile struct i40e_tx_desc *txr = txq->tx_ring;\n\tuint16_t n = 0;\n\n\t/**\n\t * Begin scanning the H/W ring for done descriptors when the number\n\t * of available descriptors drops below tx_free_thresh. For each done\n\t * descriptor, free the associated buffer.\n\t */\n\tif (txq->nb_tx_free < txq->tx_free_thresh)\n\t\ti40e_tx_free_bufs(txq);\n\n\t/* Use available descriptor only */\n\tnb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);\n\tif (unlikely(!nb_pkts))\n\t\treturn 0;\n\n\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);\n\tif ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {\n\t\tn = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);\n\t\ti40e_tx_fill_hw_ring(txq, tx_pkts, n);\n\t\ttxr[txq->tx_next_rs].cmd_type_offset_bsz |=\n\t\t\trte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<\n\t\t\t\t\t\tI40E_TXD_QW1_CMD_SHIFT);\n\t\ttxq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);\n\t\ttxq->tx_tail = 0;\n\t}\n\n\t/* Fill hardware descriptor ring with mbuf data */\n\ti40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));\n\ttxq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));\n\n\t/* Determin if RS bit needs to be set */\n\tif (txq->tx_tail > txq->tx_next_rs) {\n\t\ttxr[txq->tx_next_rs].cmd_type_offset_bsz |=\n\t\t\trte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<\n\t\t\t\t\t\tI40E_TXD_QW1_CMD_SHIFT);\n\t\ttxq->tx_next_rs =\n\t\t\t(uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);\n\t\tif (txq->tx_next_rs >= txq->nb_tx_desc)\n\t\t\ttxq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);\n\t}\n\n\tif (txq->tx_tail >= txq->nb_tx_desc)\n\t\ttxq->tx_tail = 0;\n\n\t/* Update the tx tail register */\n\trte_wmb();\n\tI40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);\n\n\treturn nb_pkts;\n}\n\nstatic uint16_t\ni40e_xmit_pkts_simple(void *tx_queue,\n\t\t struct rte_mbuf **tx_pkts,\n\t\t uint16_t nb_pkts)\n{\n\tuint16_t nb_tx = 0;\n\n\tif (likely(nb_pkts <= I40E_TX_MAX_BURST))\n\t\treturn tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,\n\t\t\t\t\t\ttx_pkts, nb_pkts);\n\n\twhile (nb_pkts) {\n\t\tuint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,\n\t\t\t\t\t\tI40E_TX_MAX_BURST);\n\n\t\tret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,\n\t\t\t\t\t\t&tx_pkts[nb_tx], num);\n\t\tnb_tx = (uint16_t)(nb_tx + ret);\n\t\tnb_pkts = (uint16_t)(nb_pkts - ret);\n\t\tif (ret < num)\n\t\t\tbreak;\n\t}\n\n\treturn nb_tx;\n}\n\n/*\n * Find the VSI the queue belongs to. 'queue_idx' is the queue index\n * application used, which assume having sequential ones. But from driver's\n * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64\n * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application\n * running on host, q1-64 and q97-128 can be used, total 96 queues. They can\n * use queue_idx from 0 to 95 to access queues, while real queue would be\n * different. This function will do a queue mapping to find VSI the queue\n * belongs to.\n */\nstatic struct i40e_vsi*\ni40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)\n{\n\t/* the queue in MAIN VSI range */\n\tif (queue_idx < pf->main_vsi->nb_qps)\n\t\treturn pf->main_vsi;\n\n\tqueue_idx -= pf->main_vsi->nb_qps;\n\n\t/* queue_idx is greater than VMDQ VSIs range */\n\tif (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {\n\t\tPMD_INIT_LOG(ERR, \"queue_idx out of range. VMDQ configured?\");\n\t\treturn NULL;\n\t}\n\n\treturn pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;\n}\n\nstatic uint16_t\ni40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)\n{\n\t/* the queue in MAIN VSI range */\n\tif (queue_idx < pf->main_vsi->nb_qps)\n\t\treturn queue_idx;\n\n\t/* It's VMDQ queues */\n\tqueue_idx -= pf->main_vsi->nb_qps;\n\n\tif (pf->nb_cfg_vmdq_vsi)\n\t\treturn queue_idx % pf->vmdq_nb_qps;\n\telse {\n\t\tPMD_INIT_LOG(ERR, \"Fail to get queue offset\");\n\t\treturn (uint16_t)(-1);\n\t}\n}\n\nint\ni40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n{\n\tstruct i40e_rx_queue *rxq;\n\tint err = -1;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rx_queue_id < dev->data->nb_rx_queues) {\n\t\trxq = dev->data->rx_queues[rx_queue_id];\n\n\t\terr = i40e_alloc_rx_queue_mbufs(rxq);\n\t\tif (err) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate RX queue mbuf\");\n\t\t\treturn err;\n\t\t}\n\n\t\trte_wmb();\n\n\t\t/* Init the RX tail regieter. */\n\t\tI40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);\n\n\t\terr = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);\n\n\t\tif (err) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch RX queue %u on\",\n\t\t\t\t rx_queue_id);\n\n\t\t\ti40e_rx_queue_release_mbufs(rxq);\n\t\t\ti40e_reset_rx_queue(rxq);\n\t\t}\n\t}\n\n\treturn err;\n}\n\nint\ni40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n{\n\tstruct i40e_rx_queue *rxq;\n\tint err;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (rx_queue_id < dev->data->nb_rx_queues) {\n\t\trxq = dev->data->rx_queues[rx_queue_id];\n\n\t\t/*\n\t\t* rx_queue_id is queue id aplication refers to, while\n\t\t* rxq->reg_idx is the real queue index.\n\t\t*/\n\t\terr = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);\n\n\t\tif (err) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch RX queue %u off\",\n\t\t\t\t rx_queue_id);\n\t\t\treturn err;\n\t\t}\n\t\ti40e_rx_queue_release_mbufs(rxq);\n\t\ti40e_reset_rx_queue(rxq);\n\t}\n\n\treturn 0;\n}\n\nint\ni40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n{\n\tint err = -1;\n\tstruct i40e_tx_queue *txq;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (tx_queue_id < dev->data->nb_tx_queues) {\n\t\ttxq = dev->data->tx_queues[tx_queue_id];\n\n\t\t/*\n\t\t* tx_queue_id is queue id aplication refers to, while\n\t\t* rxq->reg_idx is the real queue index.\n\t\t*/\n\t\terr = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);\n\t\tif (err)\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch TX queue %u on\",\n\t\t\t\t tx_queue_id);\n\t}\n\n\treturn err;\n}\n\nint\ni40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n{\n\tstruct i40e_tx_queue *txq;\n\tint err;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (tx_queue_id < dev->data->nb_tx_queues) {\n\t\ttxq = dev->data->tx_queues[tx_queue_id];\n\n\t\t/*\n\t\t* tx_queue_id is queue id aplication refers to, while\n\t\t* txq->reg_idx is the real queue index.\n\t\t*/\n\t\terr = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);\n\n\t\tif (err) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to switch TX queue %u of\",\n\t\t\t\t tx_queue_id);\n\t\t\treturn err;\n\t\t}\n\n\t\ti40e_tx_queue_release_mbufs(txq);\n\t\ti40e_reset_tx_queue(txq);\n\t}\n\n\treturn 0;\n}\n\nint\ni40e_dev_rx_queue_setup(struct rte_eth_dev *dev,\n\t\t\tuint16_t queue_idx,\n\t\t\tuint16_t nb_desc,\n\t\t\tunsigned int socket_id,\n\t\t\tconst struct rte_eth_rxconf *rx_conf,\n\t\t\tstruct rte_mempool *mp)\n{\n\tstruct i40e_vsi *vsi;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_rx_queue *rxq;\n\tconst struct rte_memzone *rz;\n\tuint32_t ring_size;\n\tuint16_t len;\n\tint use_def_burst_func = 1;\n\n\tif (hw->mac.type == I40E_MAC_VF) {\n\t\tstruct i40e_vf *vf =\n\t\t\tI40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\t\tvsi = &vf->vsi;\n\t} else\n\t\tvsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);\n\n\tif (vsi == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"VSI not available or queue \"\n\t\t\t \"index exceeds the maximum\");\n\t\treturn I40E_ERR_PARAM;\n\t}\n\tif (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||\n\t\t\t\t\t(nb_desc > I40E_MAX_RING_DESC) ||\n\t\t\t\t\t(nb_desc < I40E_MIN_RING_DESC)) {\n\t\tPMD_DRV_LOG(ERR, \"Number (%u) of receive descriptors is \"\n\t\t\t \"invalid\", nb_desc);\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\t/* Free memory if needed */\n\tif (dev->data->rx_queues[queue_idx]) {\n\t\ti40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);\n\t\tdev->data->rx_queues[queue_idx] = NULL;\n\t}\n\n\t/* Allocate the rx queue data structure */\n\trxq = rte_zmalloc_socket(\"i40e rx queue\",\n\t\t\t\t sizeof(struct i40e_rx_queue),\n\t\t\t\t RTE_CACHE_LINE_SIZE,\n\t\t\t\t socket_id);\n\tif (!rxq) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for \"\n\t\t\t \"rx queue data structure\");\n\t\treturn (-ENOMEM);\n\t}\n\trxq->mp = mp;\n\trxq->nb_rx_desc = nb_desc;\n\trxq->rx_free_thresh = rx_conf->rx_free_thresh;\n\trxq->queue_id = queue_idx;\n\tif (hw->mac.type == I40E_MAC_VF)\n\t\trxq->reg_idx = queue_idx;\n\telse /* PF device */\n\t\trxq->reg_idx = vsi->base_queue +\n\t\t\ti40e_get_queue_offset_by_qindex(pf, queue_idx);\n\n\trxq->port_id = dev->data->port_id;\n\trxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?\n\t\t\t\t\t\t\t0 : ETHER_CRC_LEN);\n\trxq->drop_en = rx_conf->rx_drop_en;\n\trxq->vsi = vsi;\n\trxq->rx_deferred_start = rx_conf->rx_deferred_start;\n\n\t/* Allocate the maximun number of RX ring hardware descriptor. */\n\tring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;\n\tring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);\n\trz = i40e_ring_dma_zone_reserve(dev,\n\t\t\t\t\t\"rx_ring\",\n\t\t\t\t\tqueue_idx,\n\t\t\t\t\tring_size,\n\t\t\t\t\tsocket_id);\n\tif (!rz) {\n\t\ti40e_dev_rx_queue_release(rxq);\n\t\tPMD_DRV_LOG(ERR, \"Failed to reserve DMA memory for RX\");\n\t\treturn (-ENOMEM);\n\t}\n\n\t/* Zero all the descriptors in the ring. */\n\tmemset(rz->addr, 0, ring_size);\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n\trxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);\n#else\n\trxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;\n#endif\n\n\trxq->rx_ring = (union i40e_rx_desc *)rz->addr;\n\n#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC\n\tlen = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);\n#else\n\tlen = nb_desc;\n#endif\n\n\t/* Allocate the software ring. */\n\trxq->sw_ring =\n\t\trte_zmalloc_socket(\"i40e rx sw ring\",\n\t\t\t\t sizeof(struct i40e_rx_entry) * len,\n\t\t\t\t RTE_CACHE_LINE_SIZE,\n\t\t\t\t socket_id);\n\tif (!rxq->sw_ring) {\n\t\ti40e_dev_rx_queue_release(rxq);\n\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for SW ring\");\n\t\treturn (-ENOMEM);\n\t}\n\n\ti40e_reset_rx_queue(rxq);\n\trxq->q_set = TRUE;\n\tdev->data->rx_queues[queue_idx] = rxq;\n\n\tuse_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);\n\n\tif (!use_def_burst_func && !dev->data->scattered_rx) {\n#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC\n\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions are \"\n\t\t\t \"satisfied. Rx Burst Bulk Alloc function will be \"\n\t\t\t \"used on port=%d, queue=%d.\",\n\t\t\t rxq->port_id, rxq->queue_id);\n\t\tdev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;\n#endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */\n\t} else {\n\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions are \"\n\t\t\t \"not satisfied, Scattered Rx is requested, \"\n\t\t\t \"or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is \"\n\t\t\t \"not enabled on port=%d, queue=%d.\",\n\t\t\t rxq->port_id, rxq->queue_id);\n\t}\n\n\treturn 0;\n}\n\nvoid\ni40e_dev_rx_queue_release(void *rxq)\n{\n\tstruct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;\n\n\tif (!q) {\n\t\tPMD_DRV_LOG(DEBUG, \"Pointer to rxq is NULL\");\n\t\treturn;\n\t}\n\n\ti40e_rx_queue_release_mbufs(q);\n\trte_free(q->sw_ring);\n\trte_free(q);\n}\n\nuint32_t\ni40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n{\n#define I40E_RXQ_SCAN_INTERVAL 4\n\tvolatile union i40e_rx_desc *rxdp;\n\tstruct i40e_rx_queue *rxq;\n\tuint16_t desc = 0;\n\n\tif (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid RX queue id %u\", rx_queue_id);\n\t\treturn 0;\n\t}\n\n\trxq = dev->data->rx_queues[rx_queue_id];\n\trxdp = &(rxq->rx_ring[rxq->rx_tail]);\n\twhile ((desc < rxq->nb_rx_desc) &&\n\t\t((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &\n\t\tI40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &\n\t\t\t\t(1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {\n\t\t/**\n\t\t * Check the DD bit of a rx descriptor of each 4 in a group,\n\t\t * to avoid checking too frequently and downgrading performance\n\t\t * too much.\n\t\t */\n\t\tdesc += I40E_RXQ_SCAN_INTERVAL;\n\t\trxdp += I40E_RXQ_SCAN_INTERVAL;\n\t\tif (rxq->rx_tail + desc >= rxq->nb_rx_desc)\n\t\t\trxdp = &(rxq->rx_ring[rxq->rx_tail +\n\t\t\t\t\tdesc - rxq->nb_rx_desc]);\n\t}\n\n\treturn desc;\n}\n\nint\ni40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)\n{\n\tvolatile union i40e_rx_desc *rxdp;\n\tstruct i40e_rx_queue *rxq = rx_queue;\n\tuint16_t desc;\n\tint ret;\n\n\tif (unlikely(offset >= rxq->nb_rx_desc)) {\n\t\tPMD_DRV_LOG(ERR, \"Invalid RX queue id %u\", offset);\n\t\treturn 0;\n\t}\n\n\tdesc = rxq->rx_tail + offset;\n\tif (desc >= rxq->nb_rx_desc)\n\t\tdesc -= rxq->nb_rx_desc;\n\n\trxdp = &(rxq->rx_ring[desc]);\n\n\tret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &\n\t\tI40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &\n\t\t\t\t(1 << I40E_RX_DESC_STATUS_DD_SHIFT));\n\n\treturn ret;\n}\n\nint\ni40e_dev_tx_queue_setup(struct rte_eth_dev *dev,\n\t\t\tuint16_t queue_idx,\n\t\t\tuint16_t nb_desc,\n\t\t\tunsigned int socket_id,\n\t\t\tconst struct rte_eth_txconf *tx_conf)\n{\n\tstruct i40e_vsi *vsi;\n\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n\tstruct i40e_tx_queue *txq;\n\tconst struct rte_memzone *tz;\n\tuint32_t ring_size;\n\tuint16_t tx_rs_thresh, tx_free_thresh;\n\n\tif (hw->mac.type == I40E_MAC_VF) {\n\t\tstruct i40e_vf *vf =\n\t\t\tI40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);\n\t\tvsi = &vf->vsi;\n\t} else\n\t\tvsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);\n\n\tif (vsi == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"VSI is NULL, or queue index (%u) \"\n\t\t\t \"exceeds the maximum\", queue_idx);\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\tif (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||\n\t\t\t\t\t(nb_desc > I40E_MAX_RING_DESC) ||\n\t\t\t\t\t(nb_desc < I40E_MIN_RING_DESC)) {\n\t\tPMD_DRV_LOG(ERR, \"Number (%u) of transmit descriptors is \"\n\t\t\t \"invalid\", nb_desc);\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\t/**\n\t * The following two parameters control the setting of the RS bit on\n\t * transmit descriptors. TX descriptors will have their RS bit set\n\t * after txq->tx_rs_thresh descriptors have been used. The TX\n\t * descriptor ring will be cleaned after txq->tx_free_thresh\n\t * descriptors are used or if the number of descriptors required to\n\t * transmit a packet is greater than the number of free TX descriptors.\n\t *\n\t * The following constraints must be satisfied:\n\t * - tx_rs_thresh must be greater than 0.\n\t * - tx_rs_thresh must be less than the size of the ring minus 2.\n\t * - tx_rs_thresh must be less than or equal to tx_free_thresh.\n\t * - tx_rs_thresh must be a divisor of the ring size.\n\t * - tx_free_thresh must be greater than 0.\n\t * - tx_free_thresh must be less than the size of the ring minus 3.\n\t *\n\t * One descriptor in the TX ring is used as a sentinel to avoid a H/W\n\t * race condition, hence the maximum threshold constraints. When set\n\t * to zero use default values.\n\t */\n\ttx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?\n\t\ttx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);\n\ttx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?\n\t\ttx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);\n\tif (tx_rs_thresh >= (nb_desc - 2)) {\n\t\tPMD_INIT_LOG(ERR, \"tx_rs_thresh must be less than the \"\n\t\t\t \"number of TX descriptors minus 2. \"\n\t\t\t \"(tx_rs_thresh=%u port=%d queue=%d)\",\n\t\t\t (unsigned int)tx_rs_thresh,\n\t\t\t (int)dev->data->port_id,\n\t\t\t (int)queue_idx);\n\t\treturn I40E_ERR_PARAM;\n\t}\n\tif (tx_free_thresh >= (nb_desc - 3)) {\n\t\tPMD_INIT_LOG(ERR, \"tx_rs_thresh must be less than the \"\n\t\t\t \"tx_free_thresh must be less than the \"\n\t\t\t \"number of TX descriptors minus 3. \"\n\t\t\t \"(tx_free_thresh=%u port=%d queue=%d)\",\n\t\t\t (unsigned int)tx_free_thresh,\n\t\t\t (int)dev->data->port_id,\n\t\t\t (int)queue_idx);\n\t\treturn I40E_ERR_PARAM;\n\t}\n\tif (tx_rs_thresh > tx_free_thresh) {\n\t\tPMD_INIT_LOG(ERR, \"tx_rs_thresh must be less than or \"\n\t\t\t \"equal to tx_free_thresh. (tx_free_thresh=%u\"\n\t\t\t \" tx_rs_thresh=%u port=%d queue=%d)\",\n\t\t\t (unsigned int)tx_free_thresh,\n\t\t\t (unsigned int)tx_rs_thresh,\n\t\t\t (int)dev->data->port_id,\n\t\t\t (int)queue_idx);\n\t\treturn I40E_ERR_PARAM;\n\t}\n\tif ((nb_desc % tx_rs_thresh) != 0) {\n\t\tPMD_INIT_LOG(ERR, \"tx_rs_thresh must be a divisor of the \"\n\t\t\t \"number of TX descriptors. (tx_rs_thresh=%u\"\n\t\t\t \" port=%d queue=%d)\",\n\t\t\t (unsigned int)tx_rs_thresh,\n\t\t\t (int)dev->data->port_id,\n\t\t\t (int)queue_idx);\n\t\treturn I40E_ERR_PARAM;\n\t}\n\tif ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {\n\t\tPMD_INIT_LOG(ERR, \"TX WTHRESH must be set to 0 if \"\n\t\t\t \"tx_rs_thresh is greater than 1. \"\n\t\t\t \"(tx_rs_thresh=%u port=%d queue=%d)\",\n\t\t\t (unsigned int)tx_rs_thresh,\n\t\t\t (int)dev->data->port_id,\n\t\t\t (int)queue_idx);\n\t\treturn I40E_ERR_PARAM;\n\t}\n\n\t/* Free memory if needed. */\n\tif (dev->data->tx_queues[queue_idx]) {\n\t\ti40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);\n\t\tdev->data->tx_queues[queue_idx] = NULL;\n\t}\n\n\t/* Allocate the TX queue data structure. */\n\ttxq = rte_zmalloc_socket(\"i40e tx queue\",\n\t\t\t\t sizeof(struct i40e_tx_queue),\n\t\t\t\t RTE_CACHE_LINE_SIZE,\n\t\t\t\t socket_id);\n\tif (!txq) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for \"\n\t\t\t \"tx queue structure\");\n\t\treturn (-ENOMEM);\n\t}\n\n\t/* Allocate TX hardware ring descriptors. */\n\tring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;\n\tring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);\n\ttz = i40e_ring_dma_zone_reserve(dev,\n\t\t\t\t\t\"tx_ring\",\n\t\t\t\t\tqueue_idx,\n\t\t\t\t\tring_size,\n\t\t\t\t\tsocket_id);\n\tif (!tz) {\n\t\ti40e_dev_tx_queue_release(txq);\n\t\tPMD_DRV_LOG(ERR, \"Failed to reserve DMA memory for TX\");\n\t\treturn (-ENOMEM);\n\t}\n\n\ttxq->nb_tx_desc = nb_desc;\n\ttxq->tx_rs_thresh = tx_rs_thresh;\n\ttxq->tx_free_thresh = tx_free_thresh;\n\ttxq->pthresh = tx_conf->tx_thresh.pthresh;\n\ttxq->hthresh = tx_conf->tx_thresh.hthresh;\n\ttxq->wthresh = tx_conf->tx_thresh.wthresh;\n\ttxq->queue_id = queue_idx;\n\tif (hw->mac.type == I40E_MAC_VF)\n\t\ttxq->reg_idx = queue_idx;\n\telse /* PF device */\n\t\ttxq->reg_idx = vsi->base_queue +\n\t\t\ti40e_get_queue_offset_by_qindex(pf, queue_idx);\n\n\ttxq->port_id = dev->data->port_id;\n\ttxq->txq_flags = tx_conf->txq_flags;\n\ttxq->vsi = vsi;\n\ttxq->tx_deferred_start = tx_conf->tx_deferred_start;\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n\ttxq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);\n#else\n\ttxq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;\n#endif\n\ttxq->tx_ring = (struct i40e_tx_desc *)tz->addr;\n\n\t/* Allocate software ring */\n\ttxq->sw_ring =\n\t\trte_zmalloc_socket(\"i40e tx sw ring\",\n\t\t\t\t sizeof(struct i40e_tx_entry) * nb_desc,\n\t\t\t\t RTE_CACHE_LINE_SIZE,\n\t\t\t\t socket_id);\n\tif (!txq->sw_ring) {\n\t\ti40e_dev_tx_queue_release(txq);\n\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for SW TX ring\");\n\t\treturn (-ENOMEM);\n\t}\n\n\ti40e_reset_tx_queue(txq);\n\ttxq->q_set = TRUE;\n\tdev->data->tx_queues[queue_idx] = txq;\n\n\t/* Use a simple TX queue without offloads or multi segs if possible */\n\tif (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&\n\t\t\t\t(txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {\n\t\tPMD_INIT_LOG(INFO, \"Using simple tx path\");\n\t\tdev->tx_pkt_burst = i40e_xmit_pkts_simple;\n\t} else {\n\t\tPMD_INIT_LOG(INFO, \"Using full-featured tx path\");\n\t\tdev->tx_pkt_burst = i40e_xmit_pkts;\n\t}\n\n\treturn 0;\n}\n\nvoid\ni40e_dev_tx_queue_release(void *txq)\n{\n\tstruct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;\n\n\tif (!q) {\n\t\tPMD_DRV_LOG(DEBUG, \"Pointer to TX queue is NULL\");\n\t\treturn;\n\t}\n\n\ti40e_tx_queue_release_mbufs(q);\n\trte_free(q->sw_ring);\n\trte_free(q);\n}\n\nstatic const struct rte_memzone *\ni40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,\n\t\t\t const char *ring_name,\n\t\t\t uint16_t queue_id,\n\t\t\t uint32_t ring_size,\n\t\t\t int socket_id)\n{\n\tchar z_name[RTE_MEMZONE_NAMESIZE];\n\tconst struct rte_memzone *mz;\n\n\tsnprintf(z_name, sizeof(z_name), \"%s_%s_%d_%d\",\n\t\t\tdev->driver->pci_drv.name, ring_name,\n\t\t\t\tdev->data->port_id, queue_id);\n\tmz = rte_memzone_lookup(z_name);\n\tif (mz)\n\t\treturn mz;\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n\treturn rte_memzone_reserve_bounded(z_name, ring_size,\n\t\tsocket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);\n#else\n\treturn rte_memzone_reserve_aligned(z_name, ring_size,\n\t\t\t\tsocket_id, 0, I40E_ALIGN);\n#endif\n}\n\nconst struct rte_memzone *\ni40e_memzone_reserve(const char *name, uint32_t len, int socket_id)\n{\n\tconst struct rte_memzone *mz = NULL;\n\n\tmz = rte_memzone_lookup(name);\n\tif (mz)\n\t\treturn mz;\n#ifdef RTE_LIBRTE_XEN_DOM0\n\tmz = rte_memzone_reserve_bounded(name, len,\n\t\tsocket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);\n#else\n\tmz = rte_memzone_reserve_aligned(name, len,\n\t\t\t\tsocket_id, 0, I40E_ALIGN);\n#endif\n\treturn mz;\n}\n\nvoid\ni40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)\n{\n\tuint16_t i;\n\n\tif (!rxq || !rxq->sw_ring) {\n\t\tPMD_DRV_LOG(DEBUG, \"Pointer to rxq or sw_ring is NULL\");\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n\t\tif (rxq->sw_ring[i].mbuf) {\n\t\t\trte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);\n\t\t\trxq->sw_ring[i].mbuf = NULL;\n\t\t}\n\t}\n#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC\n\tif (rxq->rx_nb_avail == 0)\n\t\treturn;\n\tfor (i = 0; i < rxq->rx_nb_avail; i++) {\n\t\tstruct rte_mbuf *mbuf;\n\n\t\tmbuf = rxq->rx_stage[rxq->rx_next_avail + i];\n\t\trte_pktmbuf_free_seg(mbuf);\n\t}\n\trxq->rx_nb_avail = 0;\n#endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */\n}\n\nvoid\ni40e_reset_rx_queue(struct i40e_rx_queue *rxq)\n{\n\tunsigned i;\n\tuint16_t len;\n\n\tif (!rxq) {\n\t\tPMD_DRV_LOG(DEBUG, \"Pointer to rxq is NULL\");\n\t\treturn;\n\t}\n\n#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC\n\tif (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)\n\t\tlen = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);\n\telse\n#endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */\n\t\tlen = rxq->nb_rx_desc;\n\n\tfor (i = 0; i < len * sizeof(union i40e_rx_desc); i++)\n\t\t((volatile char *)rxq->rx_ring)[i] = 0;\n\n#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC\n\tmemset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));\n\tfor (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)\n\t\trxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;\n\n\trxq->rx_nb_avail = 0;\n\trxq->rx_next_avail = 0;\n\trxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);\n#endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */\n\trxq->rx_tail = 0;\n\trxq->nb_rx_hold = 0;\n\trxq->pkt_first_seg = NULL;\n\trxq->pkt_last_seg = NULL;\n}\n\nvoid\ni40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)\n{\n\tuint16_t i;\n\n\tif (!txq || !txq->sw_ring) {\n\t\tPMD_DRV_LOG(DEBUG, \"Pointer to rxq or sw_ring is NULL\");\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n\t\tif (txq->sw_ring[i].mbuf) {\n\t\t\trte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);\n\t\t\ttxq->sw_ring[i].mbuf = NULL;\n\t\t}\n\t}\n}\n\nvoid\ni40e_reset_tx_queue(struct i40e_tx_queue *txq)\n{\n\tstruct i40e_tx_entry *txe;\n\tuint16_t i, prev, size;\n\n\tif (!txq) {\n\t\tPMD_DRV_LOG(DEBUG, \"Pointer to txq is NULL\");\n\t\treturn;\n\t}\n\n\ttxe = txq->sw_ring;\n\tsize = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;\n\tfor (i = 0; i < size; i++)\n\t\t((volatile char *)txq->tx_ring)[i] = 0;\n\n\tprev = (uint16_t)(txq->nb_tx_desc - 1);\n\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n\t\tvolatile struct i40e_tx_desc *txd = &txq->tx_ring[i];\n\n\t\ttxd->cmd_type_offset_bsz =\n\t\t\trte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);\n\t\ttxe[i].mbuf = NULL;\n\t\ttxe[i].last_id = i;\n\t\ttxe[prev].next_id = i;\n\t\tprev = i;\n\t}\n\n\ttxq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);\n\ttxq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);\n\n\ttxq->tx_tail = 0;\n\ttxq->nb_tx_used = 0;\n\n\ttxq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);\n\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);\n}\n\n/* Init the TX queue in hardware */\nint\ni40e_tx_queue_init(struct i40e_tx_queue *txq)\n{\n\tenum i40e_status_code err = I40E_SUCCESS;\n\tstruct i40e_vsi *vsi = txq->vsi;\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(vsi);\n\tuint16_t pf_q = txq->reg_idx;\n\tstruct i40e_hmc_obj_txq tx_ctx;\n\tuint32_t qtx_ctl;\n\n\t/* clear the context structure first */\n\tmemset(&tx_ctx, 0, sizeof(tx_ctx));\n\ttx_ctx.new_context = 1;\n\ttx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;\n\ttx_ctx.qlen = txq->nb_tx_desc;\n\n#ifdef RTE_LIBRTE_IEEE1588\n\ttx_ctx.timesync_ena = 1;\n#endif\n\ttx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);\n\tif (vsi->type == I40E_VSI_FDIR)\n\t\ttx_ctx.fd_ena = TRUE;\n\n\terr = i40e_clear_lan_tx_queue_context(hw, pf_q);\n\tif (err != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failure of clean lan tx queue context\");\n\t\treturn err;\n\t}\n\n\terr = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);\n\tif (err != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failure of set lan tx queue context\");\n\t\treturn err;\n\t}\n\n\t/* Now associate this queue with this PCI function */\n\tqtx_ctl = I40E_QTX_CTL_PF_QUEUE;\n\tqtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &\n\t\t\t\t\tI40E_QTX_CTL_PF_INDX_MASK);\n\tI40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);\n\tI40E_WRITE_FLUSH(hw);\n\n\ttxq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);\n\n\treturn err;\n}\n\nint\ni40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)\n{\n\tstruct i40e_rx_entry *rxe = rxq->sw_ring;\n\tuint64_t dma_addr;\n\tuint16_t i;\n\n\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n\t\tvolatile union i40e_rx_desc *rxd;\n\t\tstruct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);\n\n\t\tif (unlikely(!mbuf)) {\n\t\t\tPMD_DRV_LOG(ERR, \"Failed to allocate mbuf for RX\");\n\t\t\treturn -ENOMEM;\n\t\t}\n\n\t\trte_mbuf_refcnt_set(mbuf, 1);\n\t\tmbuf->next = NULL;\n\t\tmbuf->data_off = RTE_PKTMBUF_HEADROOM;\n\t\tmbuf->nb_segs = 1;\n\t\tmbuf->port = rxq->port_id;\n\n\t\tdma_addr =\n\t\t\trte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));\n\n\t\trxd = &rxq->rx_ring[i];\n\t\trxd->read.pkt_addr = dma_addr;\n\t\trxd->read.hdr_addr = 0;\n#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n\t\trxd->read.rsvd1 = 0;\n\t\trxd->read.rsvd2 = 0;\n#endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */\n\n\t\trxe[i].mbuf = mbuf;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Calculate the buffer length, and check the jumbo frame\n * and maximum packet length.\n */\nstatic int\ni40e_rx_queue_config(struct i40e_rx_queue *rxq)\n{\n\tstruct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);\n\tstruct rte_eth_dev_data *data = pf->dev_data;\n\tuint16_t buf_size, len;\n\n\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -\n\t\tRTE_PKTMBUF_HEADROOM);\n\n\tswitch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |\n\t\t\tI40E_FLAG_HEADER_SPLIT_ENABLED)) {\n\tcase I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */\n\t\trxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,\n\t\t\t\t(1 << I40E_RXQ_CTX_HBUFF_SHIFT));\n\t\trxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,\n\t\t\t\t(1 << I40E_RXQ_CTX_DBUFF_SHIFT));\n\t\trxq->hs_mode = i40e_header_split_enabled;\n\t\tbreak;\n\tcase I40E_FLAG_HEADER_SPLIT_DISABLED:\n\tdefault:\n\t\trxq->rx_hdr_len = 0;\n\t\trxq->rx_buf_len = RTE_ALIGN(buf_size,\n\t\t\t(1 << I40E_RXQ_CTX_DBUFF_SHIFT));\n\t\trxq->hs_mode = i40e_header_split_none;\n\t\tbreak;\n\t}\n\n\tlen = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;\n\trxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);\n\tif (data->dev_conf.rxmode.jumbo_frame == 1) {\n\t\tif (rxq->max_pkt_len <= ETHER_MAX_LEN ||\n\t\t\trxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {\n\t\t\tPMD_DRV_LOG(ERR, \"maximum packet length must \"\n\t\t\t\t \"be larger than %u and smaller than %u,\"\n\t\t\t\t \"as jumbo frame is enabled\",\n\t\t\t\t (uint32_t)ETHER_MAX_LEN,\n\t\t\t\t (uint32_t)I40E_FRAME_SIZE_MAX);\n\t\t\treturn I40E_ERR_CONFIG;\n\t\t}\n\t} else {\n\t\tif (rxq->max_pkt_len < ETHER_MIN_LEN ||\n\t\t\trxq->max_pkt_len > ETHER_MAX_LEN) {\n\t\t\tPMD_DRV_LOG(ERR, \"maximum packet length must be \"\n\t\t\t\t \"larger than %u and smaller than %u, \"\n\t\t\t\t \"as jumbo frame is disabled\",\n\t\t\t\t (uint32_t)ETHER_MIN_LEN,\n\t\t\t\t (uint32_t)ETHER_MAX_LEN);\n\t\t\treturn I40E_ERR_CONFIG;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/* Init the RX queue in hardware */\nint\ni40e_rx_queue_init(struct i40e_rx_queue *rxq)\n{\n\tint err = I40E_SUCCESS;\n\tstruct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);\n\tstruct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);\n\tstruct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);\n\tuint16_t pf_q = rxq->reg_idx;\n\tuint16_t buf_size;\n\tstruct i40e_hmc_obj_rxq rx_ctx;\n\n\terr = i40e_rx_queue_config(rxq);\n\tif (err < 0) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to config RX queue\");\n\t\treturn err;\n\t}\n\n\t/* Clear the context structure first */\n\tmemset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));\n\trx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;\n\trx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;\n\n\trx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;\n\trx_ctx.qlen = rxq->nb_rx_desc;\n#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n\trx_ctx.dsize = 1;\n#endif\n\trx_ctx.dtype = rxq->hs_mode;\n\tif (rxq->hs_mode)\n\t\trx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;\n\telse\n\t\trx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;\n\trx_ctx.rxmax = rxq->max_pkt_len + I40E_VLAN_TAG_SIZE;\n\trx_ctx.tphrdesc_ena = 1;\n\trx_ctx.tphwdesc_ena = 1;\n\trx_ctx.tphdata_ena = 1;\n\trx_ctx.tphhead_ena = 1;\n\trx_ctx.lrxqthresh = 2;\n\trx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;\n\trx_ctx.l2tsel = 1;\n\trx_ctx.showiv = 1;\n\trx_ctx.prefena = 1;\n\n\terr = i40e_clear_lan_rx_queue_context(hw, pf_q);\n\tif (err != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to clear LAN RX queue context\");\n\t\treturn err;\n\t}\n\terr = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);\n\tif (err != I40E_SUCCESS) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to set LAN RX queue context\");\n\t\treturn err;\n\t}\n\n\trxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);\n\n\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -\n\t\tRTE_PKTMBUF_HEADROOM);\n\n\t/* Check if scattered RX needs to be used. */\n\tif ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {\n\t\tdev_data->scattered_rx = 1;\n\t\tdev->rx_pkt_burst = i40e_recv_scattered_pkts;\n\t}\n\n\t/* Init the RX tail regieter. */\n\tI40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);\n\n\treturn 0;\n}\n\nvoid\ni40e_dev_clear_queues(struct rte_eth_dev *dev)\n{\n\tuint16_t i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\ti40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);\n\t\ti40e_reset_tx_queue(dev->data->tx_queues[i]);\n\t}\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\ti40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);\n\t\ti40e_reset_rx_queue(dev->data->rx_queues[i]);\n\t}\n}\n\nvoid\ni40e_dev_free_queues(struct rte_eth_dev *dev)\n{\n\tuint16_t i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\ti40e_dev_rx_queue_release(dev->data->rx_queues[i]);\n\t\tdev->data->rx_queues[i] = NULL;\n\t}\n\tdev->data->nb_rx_queues = 0;\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\ti40e_dev_tx_queue_release(dev->data->tx_queues[i]);\n\t\tdev->data->tx_queues[i] = NULL;\n\t}\n\tdev->data->nb_tx_queues = 0;\n}\n\n#define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC\n#define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC\n\nenum i40e_status_code\ni40e_fdir_setup_tx_resources(struct i40e_pf *pf)\n{\n\tstruct i40e_tx_queue *txq;\n\tconst struct rte_memzone *tz = NULL;\n\tuint32_t ring_size;\n\tstruct rte_eth_dev *dev = pf->adapter->eth_dev;\n\n\tif (!pf) {\n\t\tPMD_DRV_LOG(ERR, \"PF is not available\");\n\t\treturn I40E_ERR_BAD_PTR;\n\t}\n\n\t/* Allocate the TX queue data structure. */\n\ttxq = rte_zmalloc_socket(\"i40e fdir tx queue\",\n\t\t\t\t sizeof(struct i40e_tx_queue),\n\t\t\t\t RTE_CACHE_LINE_SIZE,\n\t\t\t\t SOCKET_ID_ANY);\n\tif (!txq) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for \"\n\t\t\t\t\t\"tx queue structure.\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\n\t/* Allocate TX hardware ring descriptors. */\n\tring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;\n\tring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);\n\n\ttz = i40e_ring_dma_zone_reserve(dev,\n\t\t\t\t\t\"fdir_tx_ring\",\n\t\t\t\t\tI40E_FDIR_QUEUE_ID,\n\t\t\t\t\tring_size,\n\t\t\t\t\tSOCKET_ID_ANY);\n\tif (!tz) {\n\t\ti40e_dev_tx_queue_release(txq);\n\t\tPMD_DRV_LOG(ERR, \"Failed to reserve DMA memory for TX.\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\n\ttxq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;\n\ttxq->queue_id = I40E_FDIR_QUEUE_ID;\n\ttxq->reg_idx = pf->fdir.fdir_vsi->base_queue;\n\ttxq->vsi = pf->fdir.fdir_vsi;\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n\ttxq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);\n#else\n\ttxq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;\n#endif\n\ttxq->tx_ring = (struct i40e_tx_desc *)tz->addr;\n\t/*\n\t * don't need to allocate software ring and reset for the fdir\n\t * program queue just set the queue has been configured.\n\t */\n\ttxq->q_set = TRUE;\n\tpf->fdir.txq = txq;\n\n\treturn I40E_SUCCESS;\n}\n\nenum i40e_status_code\ni40e_fdir_setup_rx_resources(struct i40e_pf *pf)\n{\n\tstruct i40e_rx_queue *rxq;\n\tconst struct rte_memzone *rz = NULL;\n\tuint32_t ring_size;\n\tstruct rte_eth_dev *dev = pf->adapter->eth_dev;\n\n\tif (!pf) {\n\t\tPMD_DRV_LOG(ERR, \"PF is not available\");\n\t\treturn I40E_ERR_BAD_PTR;\n\t}\n\n\t/* Allocate the RX queue data structure. */\n\trxq = rte_zmalloc_socket(\"i40e fdir rx queue\",\n\t\t\t\t sizeof(struct i40e_rx_queue),\n\t\t\t\t RTE_CACHE_LINE_SIZE,\n\t\t\t\t SOCKET_ID_ANY);\n\tif (!rxq) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to allocate memory for \"\n\t\t\t\t\t\"rx queue structure.\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\n\t/* Allocate RX hardware ring descriptors. */\n\tring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;\n\tring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);\n\n\trz = i40e_ring_dma_zone_reserve(dev,\n\t\t\t\t\t\"fdir_rx_ring\",\n\t\t\t\t\tI40E_FDIR_QUEUE_ID,\n\t\t\t\t\tring_size,\n\t\t\t\t\tSOCKET_ID_ANY);\n\tif (!rz) {\n\t\ti40e_dev_rx_queue_release(rxq);\n\t\tPMD_DRV_LOG(ERR, \"Failed to reserve DMA memory for RX.\");\n\t\treturn I40E_ERR_NO_MEMORY;\n\t}\n\n\trxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;\n\trxq->queue_id = I40E_FDIR_QUEUE_ID;\n\trxq->reg_idx = pf->fdir.fdir_vsi->base_queue;\n\trxq->vsi = pf->fdir.fdir_vsi;\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n\trxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);\n#else\n\trxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;\n#endif\n\trxq->rx_ring = (union i40e_rx_desc *)rz->addr;\n\n\t/*\n\t * Don't need to allocate software ring and reset for the fdir\n\t * rx queue, just set the queue has been configured.\n\t */\n\trxq->q_set = TRUE;\n\tpf->fdir.rxq = rxq;\n\n\treturn I40E_SUCCESS;\n}\n" }, { "path": "drivers/net/i40e/i40e_rxtx.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _I40E_RXTX_H_\n#define _I40E_RXTX_H_\n\n/**\n * 32 bits tx flags, high 16 bits for L2TAG1 (VLAN),\n * low 16 bits for others.\n */\n#define I40E_TX_FLAG_L2TAG1_SHIFT 16\n#define I40E_TX_FLAG_L2TAG1_MASK 0xffff0000\n#define I40E_TX_FLAG_CSUM ((uint32_t)(1 << 0))\n#define I40E_TX_FLAG_INSERT_VLAN ((uint32_t)(1 << 1))\n#define I40E_TX_FLAG_TSYN ((uint32_t)(1 << 2))\n\n#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC\n#define RTE_PMD_I40E_RX_MAX_BURST 32\n#endif\n\n#define I40E_RXBUF_SZ_1024 1024\n#define I40E_RXBUF_SZ_2048 2048\n\nenum i40e_header_split_mode {\n\ti40e_header_split_none = 0,\n\ti40e_header_split_enabled = 1,\n\ti40e_header_split_always = 2,\n\ti40e_header_split_reserved\n};\n\n#define I40E_HEADER_SPLIT_NONE ((uint8_t)0)\n#define I40E_HEADER_SPLIT_L2 ((uint8_t)(1 << 0))\n#define I40E_HEADER_SPLIT_IP ((uint8_t)(1 << 1))\n#define I40E_HEADER_SPLIT_UDP_TCP ((uint8_t)(1 << 2))\n#define I40E_HEADER_SPLIT_SCTP ((uint8_t)(1 << 3))\n#define I40E_HEADER_SPLIT_ALL (I40E_HEADER_SPLIT_L2 | \\\n\t\t\t I40E_HEADER_SPLIT_IP | \\\n\t\t\t I40E_HEADER_SPLIT_UDP_TCP | \\\n\t\t\t I40E_HEADER_SPLIT_SCTP)\n\n/* HW desc structure, both 16-byte and 32-byte types are supported */\n#ifdef RTE_LIBRTE_I40E_16BYTE_RX_DESC\n#define i40e_rx_desc i40e_16byte_rx_desc\n#else\n#define i40e_rx_desc i40e_32byte_rx_desc\n#endif\n\nstruct i40e_rx_entry {\n\tstruct rte_mbuf *mbuf;\n};\n\n/*\n * Structure associated with each RX queue.\n */\nstruct i40e_rx_queue {\n\tstruct rte_mempool *mp; /**< mbuf pool to populate RX ring */\n\tvolatile union i40e_rx_desc *rx_ring;/**< RX ring virtual address */\n\tuint64_t rx_ring_phys_addr; /**< RX ring DMA address */\n\tstruct i40e_rx_entry *sw_ring; /**< address of RX soft ring */\n\tuint16_t nb_rx_desc; /**< number of RX descriptors */\n\tuint16_t rx_free_thresh; /**< max free RX desc to hold */\n\tuint16_t rx_tail; /**< current value of tail */\n\tuint16_t nb_rx_hold; /**< number of held free RX desc */\n\tstruct rte_mbuf *pkt_first_seg; /**< first segment of current packet */\n\tstruct rte_mbuf *pkt_last_seg; /**< last segment of current packet */\n#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC\n\tuint16_t rx_nb_avail; /**< number of staged packets ready */\n\tuint16_t rx_next_avail; /**< index of next staged packets */\n\tuint16_t rx_free_trigger; /**< triggers rx buffer allocation */\n\tstruct rte_mbuf fake_mbuf; /**< dummy mbuf */\n\tstruct rte_mbuf *rx_stage[RTE_PMD_I40E_RX_MAX_BURST * 2];\n#endif\n\tuint8_t port_id; /**< device port ID */\n\tuint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise */\n\tuint16_t queue_id; /**< RX queue index */\n\tuint16_t reg_idx; /**< RX queue register index */\n\tuint8_t drop_en; /**< if not 0, set register bit */\n\tvolatile uint8_t *qrx_tail; /**< register address of tail */\n\tstruct i40e_vsi *vsi; /**< the VSI this queue belongs to */\n\tuint16_t rx_buf_len; /* The packet buffer size */\n\tuint16_t rx_hdr_len; /* The header buffer size */\n\tuint16_t max_pkt_len; /* Maximum packet length */\n\tuint8_t hs_mode; /* Header Split mode */\n\tbool q_set; /**< indicate if rx queue has been configured */\n\tbool rx_deferred_start; /**< don't start this queue in dev start */\n};\n\nstruct i40e_tx_entry {\n\tstruct rte_mbuf *mbuf;\n\tuint16_t next_id;\n\tuint16_t last_id;\n};\n\n/*\n * Structure associated with each TX queue.\n */\nstruct i40e_tx_queue {\n\tuint16_t nb_tx_desc; /**< number of TX descriptors */\n\tuint64_t tx_ring_phys_addr; /**< TX ring DMA address */\n\tvolatile struct i40e_tx_desc *tx_ring; /**< TX ring virtual address */\n\tstruct i40e_tx_entry *sw_ring; /**< virtual address of SW ring */\n\tuint16_t tx_tail; /**< current value of tail register */\n\tvolatile uint8_t *qtx_tail; /**< register address of tail */\n\tuint16_t nb_tx_used; /**< number of TX desc used since RS bit set */\n\t/**< index to last TX descriptor to have been cleaned */\n\tuint16_t last_desc_cleaned;\n\t/**< Total number of TX descriptors ready to be allocated. */\n\tuint16_t nb_tx_free;\n\t/**< Start freeing TX buffers if there are less free descriptors than\n\t this value. */\n\tuint16_t tx_free_thresh;\n\t/** Number of TX descriptors to use before RS bit is set. */\n\tuint16_t tx_rs_thresh;\n\tuint8_t pthresh; /**< Prefetch threshold register. */\n\tuint8_t hthresh; /**< Host threshold register. */\n\tuint8_t wthresh; /**< Write-back threshold reg. */\n\tuint8_t port_id; /**< Device port identifier. */\n\tuint16_t queue_id; /**< TX queue index. */\n\tuint16_t reg_idx;\n\tuint32_t txq_flags;\n\tstruct i40e_vsi *vsi; /**< the VSI this queue belongs to */\n\tuint16_t tx_next_dd;\n\tuint16_t tx_next_rs;\n\tbool q_set; /**< indicate if tx queue has been configured */\n\tbool tx_deferred_start; /**< don't start this queue in dev start */\n};\n\n/** Offload features */\nunion i40e_tx_offload {\n\tuint64_t data;\n\tstruct {\n\t\tuint64_t l2_len:7; /**< L2 (MAC) Header Length. */\n\t\tuint64_t l3_len:9; /**< L3 (IP) Header Length. */\n\t\tuint64_t l4_len:8; /**< L4 Header Length. */\n\t\tuint64_t tso_segsz:16; /**< TCP TSO segment size */\n\t\tuint64_t outer_l2_len:8; /**< outer L2 Header Length */\n\t\tuint64_t outer_l3_len:16; /**< outer L3 Header Length */\n\t};\n};\n\nint i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);\nint i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);\nint i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);\nint i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);\nint i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,\n\t\t\t uint16_t queue_idx,\n\t\t\t uint16_t nb_desc,\n\t\t\t unsigned int socket_id,\n\t\t\t const struct rte_eth_rxconf *rx_conf,\n\t\t\t struct rte_mempool *mp);\nint i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,\n\t\t\t uint16_t queue_idx,\n\t\t\t uint16_t nb_desc,\n\t\t\t unsigned int socket_id,\n\t\t\t const struct rte_eth_txconf *tx_conf);\nvoid i40e_dev_rx_queue_release(void *rxq);\nvoid i40e_dev_tx_queue_release(void *txq);\nuint16_t i40e_recv_pkts(void *rx_queue,\n\t\t\tstruct rte_mbuf **rx_pkts,\n\t\t\tuint16_t nb_pkts);\nuint16_t i40e_recv_scattered_pkts(void *rx_queue,\n\t\t\t\t struct rte_mbuf **rx_pkts,\n\t\t\t\t uint16_t nb_pkts);\nuint16_t i40e_xmit_pkts(void *tx_queue,\n\t\t\tstruct rte_mbuf **tx_pkts,\n\t\t\tuint16_t nb_pkts);\nint i40e_tx_queue_init(struct i40e_tx_queue *txq);\nint i40e_rx_queue_init(struct i40e_rx_queue *rxq);\nvoid i40e_free_tx_resources(struct i40e_tx_queue *txq);\nvoid i40e_free_rx_resources(struct i40e_rx_queue *rxq);\nvoid i40e_dev_clear_queues(struct rte_eth_dev *dev);\nvoid i40e_dev_free_queues(struct rte_eth_dev *dev);\nvoid i40e_reset_rx_queue(struct i40e_rx_queue *rxq);\nvoid i40e_reset_tx_queue(struct i40e_tx_queue *txq);\nvoid i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq);\nint i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq);\nvoid i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq);\n\nuint32_t i40e_dev_rx_queue_count(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t rx_queue_id);\nint i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);\n\n#endif /* _I40E_RXTX_H_ */\n" }, { "path": "drivers/net/ixgbe/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_ixgbe.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_pmd_ixgbe_version.map\n\nLIBABIVER := 1\n\nifeq ($(CC), icc)\n#\n# CFLAGS for icc\n#\nCFLAGS_BASE_DRIVER = -wd174 -wd593 -wd869 -wd981 -wd2259\n\nelse ifeq ($(CC), clang)\n#\n# CFLAGS for clang\n#\nCFLAGS_BASE_DRIVER = -Wno-unused-parameter -Wno-unused-value\nCFLAGS_BASE_DRIVER += -Wno-strict-aliasing -Wno-format-extra-args\n\nelse\n#\n# CFLAGS for gcc\n#\nifeq ($(shell test $(GCC_VERSION) -ge 44 && echo 1), 1)\nCFLAGS += -Wno-deprecated\nCFLAGS_ixgbe_common.o += -Wno-unused-but-set-variable\nCFLAGS_ixgbe_x550.o += -Wno-unused-but-set-variable\nendif\nCFLAGS_BASE_DRIVER = -Wno-unused-parameter -Wno-unused-value\nCFLAGS_BASE_DRIVER += -Wno-strict-aliasing -Wno-format-extra-args\n\nifeq ($(shell test $(GCC_VERSION) -ge 46 && echo 1), 1)\nCFLAGS_ixgbe_x550.o += -Wno-maybe-uninitialized\nendif\n\nifeq ($(shell test $(GCC_VERSION) -ge 50 && echo 1), 1)\nCFLAGS_ixgbe_common.o += -Wno-logical-not-parentheses\nendif\n\nendif\n\n#\n# Add extra flags for base driver files (also known as shared code)\n# to disable warnings in them\n#\nBASE_DRIVER_OBJS=$(patsubst %.c,%.o,$(notdir $(wildcard $(SRCDIR)/base/*.c)))\n$(foreach obj, $(BASE_DRIVER_OBJS), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER)))\n\nVPATH += $(SRCDIR)/base\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_common.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_82598.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_82599.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_x540.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_x550.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_phy.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_api.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_vf.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_dcb.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_dcb_82599.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_dcb_82598.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_mbx.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_rxtx.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_ethdev.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_fdir.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_pf.c\nSRCS-$(CONFIG_RTE_IXGBE_INC_VECTOR) += ixgbe_rxtx_vec.c\n\nifeq ($(CONFIG_RTE_NIC_BYPASS),y)\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_bypass.c\nSRCS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe_82599_bypass.c\nendif\n\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += lib/librte_eal lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += lib/librte_mempool lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += lib/librte_net\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/ixgbe/base/README", "content": "..\n BSD LICENSE\n \n Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n All rights reserved.\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n \n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n \n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIntel® IXGBE driver\n===================\n\nThis directory contains source code of FreeBSD ixgbe driver of version\ncid-10g-shared-code.2015.06.05 released by ND. The sub-directory of base/\ncontains the original source package.\nThis driver is valid for the product(s) listed below\n\n* Intel® 10 Gigabit AF DA Dual Port Server Adapter\n* Intel® 10 Gigabit AT Server Adapter\n* Intel® 10 Gigabit AT2 Server Adapter\n* Intel® 10 Gigabit CX4 Dual Port Server Adapter\n* Intel® 10 Gigabit XF LR Server Adapter\n* Intel® 10 Gigabit XF SR Dual Port Server Adapter\n* Intel® 10 Gigabit XF SR Server Adapter\n* Intel® 82598 10 Gigabit Ethernet Controller\n* Intel® 82599 10 Gigabit Ethernet Controller\n* Intel® Ethernet Controller X540-AT2\n* Intel® Ethernet Server Adapter X520 Series\n* Intel® Ethernet Server Adapter X520-T2\n* Intel® Ethernet Controller X550-BT2\n\nUpdating the driver\n===================\n\nNOTE: The source code in this directory should not be modified apart from\nthe following file(s):\n\n ixgbe_osdep.h\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_82598.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"ixgbe_type.h\"\n#include \"ixgbe_82598.h\"\n#include \"ixgbe_api.h\"\n#include \"ixgbe_common.h\"\n#include \"ixgbe_phy.h\"\n\n#define IXGBE_82598_MAX_TX_QUEUES 32\n#define IXGBE_82598_MAX_RX_QUEUES 64\n#define IXGBE_82598_RAR_ENTRIES 16\n#define IXGBE_82598_MC_TBL_SIZE 128\n#define IXGBE_82598_VFT_TBL_SIZE 128\n#define IXGBE_82598_RX_PB_SIZE 512\n\nSTATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t\t bool *autoneg);\nSTATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);\nSTATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t bool autoneg_wait_to_complete);\nSTATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed, bool *link_up,\n\t\t\t\t bool link_up_wait_to_complete);\nSTATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg_wait_to_complete);\nSTATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t\t bool autoneg_wait_to_complete);\nSTATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);\nSTATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);\nSTATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);\nSTATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,\n\t\t\t\t u32 headroom, int strategy);\nSTATIC s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\tu8 *sff8472_data);\n/**\n * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout\n * @hw: pointer to the HW structure\n *\n * The defaults for 82598 should be in the range of 50us to 50ms,\n * however the hardware default for these parts is 500us to 1ms which is less\n * than the 10ms recommended by the pci-e spec. To address this we need to\n * increase the value to either 10ms to 250ms for capability version 1 config,\n * or 16ms to 55ms for version 2.\n **/\nvoid ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)\n{\n\tu32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);\n\tu16 pcie_devctl2;\n\n\t/* only take action if timeout value is defaulted to 0 */\n\tif (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)\n\t\tgoto out;\n\n\t/*\n\t * if capababilities version is type 1 we can write the\n\t * timeout of 10ms to 250ms through the GCR register\n\t */\n\tif (!(gcr & IXGBE_GCR_CAP_VER2)) {\n\t\tgcr |= IXGBE_GCR_CMPL_TMOUT_10ms;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * for version 2 capabilities we need to write the config space\n\t * directly in order to set the completion timeout value for\n\t * 16ms to 55ms\n\t */\n\tpcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);\n\tpcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;\n\tIXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);\nout:\n\t/* disable completion timeout resend */\n\tgcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;\n\tIXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);\n}\n\n/**\n * ixgbe_init_ops_82598 - Inits func ptrs and MAC type\n * @hw: pointer to hardware structure\n *\n * Initialize the function pointers and assign the MAC type for 82598.\n * Does not touch the hardware.\n **/\ns32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"ixgbe_init_ops_82598\");\n\n\tret_val = ixgbe_init_phy_ops_generic(hw);\n\tret_val = ixgbe_init_ops_generic(hw);\n\n\t/* PHY */\n\tphy->ops.init = ixgbe_init_phy_ops_82598;\n\n\t/* MAC */\n\tmac->ops.start_hw = ixgbe_start_hw_82598;\n\tmac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_82598;\n\tmac->ops.reset_hw = ixgbe_reset_hw_82598;\n\tmac->ops.get_media_type = ixgbe_get_media_type_82598;\n\tmac->ops.get_supported_physical_layer =\n\t\t\t\tixgbe_get_supported_physical_layer_82598;\n\tmac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82598;\n\tmac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82598;\n\tmac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie_82598;\n\tmac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82598;\n\n\t/* RAR, Multicast, VLAN */\n\tmac->ops.set_vmdq = ixgbe_set_vmdq_82598;\n\tmac->ops.clear_vmdq = ixgbe_clear_vmdq_82598;\n\tmac->ops.set_vfta = ixgbe_set_vfta_82598;\n\tmac->ops.set_vlvf = NULL;\n\tmac->ops.clear_vfta = ixgbe_clear_vfta_82598;\n\n\t/* Flow Control */\n\tmac->ops.fc_enable = ixgbe_fc_enable_82598;\n\n\tmac->mcft_size\t\t= IXGBE_82598_MC_TBL_SIZE;\n\tmac->vft_size\t\t= IXGBE_82598_VFT_TBL_SIZE;\n\tmac->num_rar_entries\t= IXGBE_82598_RAR_ENTRIES;\n\tmac->rx_pb_size\t\t= IXGBE_82598_RX_PB_SIZE;\n\tmac->max_rx_queues\t= IXGBE_82598_MAX_RX_QUEUES;\n\tmac->max_tx_queues\t= IXGBE_82598_MAX_TX_QUEUES;\n\tmac->max_msix_vectors\t= ixgbe_get_pcie_msix_count_generic(hw);\n\n\t/* SFP+ Module */\n\tphy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598;\n\tphy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_82598;\n\n\t/* Link */\n\tmac->ops.check_link = ixgbe_check_mac_link_82598;\n\tmac->ops.setup_link = ixgbe_setup_mac_link_82598;\n\tmac->ops.flap_tx_laser = NULL;\n\tmac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82598;\n\tmac->ops.setup_rxpba = ixgbe_set_rxpba_82598;\n\n\t/* Manageability interface */\n\tmac->ops.set_fw_drv_ver = NULL;\n\n\tmac->ops.get_rtrup2tc = NULL;\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_init_phy_ops_82598 - PHY/SFP specific init\n * @hw: pointer to hardware structure\n *\n * Initialize any function pointers that were not able to be\n * set during init_shared_code because the PHY/SFP type was\n * not known. Perform the SFP init if necessary.\n *\n **/\ns32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\ts32 ret_val = IXGBE_SUCCESS;\n\tu16 list_offset, data_offset;\n\n\tDEBUGFUNC(\"ixgbe_init_phy_ops_82598\");\n\n\t/* Identify the PHY */\n\tphy->ops.identify(hw);\n\n\t/* Overwrite the link function pointers if copper PHY */\n\tif (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {\n\t\tmac->ops.setup_link = ixgbe_setup_copper_link_82598;\n\t\tmac->ops.get_link_capabilities =\n\t\t\t\tixgbe_get_copper_link_capabilities_generic;\n\t}\n\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_tn:\n\t\tphy->ops.setup_link = ixgbe_setup_phy_link_tnx;\n\t\tphy->ops.check_link = ixgbe_check_phy_link_tnx;\n\t\tphy->ops.get_firmware_version =\n\t\t\t\t\tixgbe_get_phy_firmware_version_tnx;\n\t\tbreak;\n\tcase ixgbe_phy_nl:\n\t\tphy->ops.reset = ixgbe_reset_phy_nl;\n\n\t\t/* Call SFP+ identify routine to get the SFP+ module type */\n\t\tret_val = phy->ops.identify_sfp(hw);\n\t\tif (ret_val != IXGBE_SUCCESS)\n\t\t\tgoto out;\n\t\telse if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {\n\t\t\tret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/* Check to see if SFP+ module is supported */\n\t\tret_val = ixgbe_get_sfp_init_sequence_offsets(hw,\n\t\t\t\t\t\t\t &list_offset,\n\t\t\t\t\t\t\t &data_offset);\n\t\tif (ret_val != IXGBE_SUCCESS) {\n\t\t\tret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\t\tgoto out;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx\n * @hw: pointer to hardware structure\n *\n * Starts the hardware using the generic start_hw function.\n * Disables relaxed ordering Then set pcie completion timeout\n *\n **/\ns32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)\n{\n\tu32 regval;\n\tu32 i;\n\ts32 ret_val = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_start_hw_82598\");\n\n\tret_val = ixgbe_start_hw_generic(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Disable relaxed ordering */\n\tfor (i = 0; ((i < hw->mac.max_tx_queues) &&\n\t (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {\n\t\tregval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));\n\t\tregval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);\n\t}\n\n\tfor (i = 0; ((i < hw->mac.max_rx_queues) &&\n\t (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {\n\t\tregval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));\n\t\tregval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |\n\t\t\t IXGBE_DCA_RXCTRL_HEAD_WRO_EN);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);\n\t}\n\n\t/* set the completion timeout for interface */\n\tixgbe_set_pcie_completion_timeout(hw);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_get_link_capabilities_82598 - Determines link capabilities\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @autoneg: boolean auto-negotiation value\n *\n * Determines the link capabilities by reading the AUTOC register.\n **/\nSTATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t\t bool *autoneg)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu32 autoc = 0;\n\n\tDEBUGFUNC(\"ixgbe_get_link_capabilities_82598\");\n\n\t/*\n\t * Determine link capabilities based on the stored value of AUTOC,\n\t * which represents EEPROM defaults. If AUTOC value has not been\n\t * stored, use the current register value.\n\t */\n\tif (hw->mac.orig_link_settings_stored)\n\t\tautoc = hw->mac.orig_autoc;\n\telse\n\t\tautoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\n\tswitch (autoc & IXGBE_AUTOC_LMS_MASK) {\n\tcase IXGBE_AUTOC_LMS_1G_LINK_NO_AN:\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*autoneg = false;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_10G_LINK_NO_AN:\n\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\t\t*autoneg = false;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_1G_AN:\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*autoneg = true;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_KX4_AN:\n\tcase IXGBE_AUTOC_LMS_KX4_AN_1G_AN:\n\t\t*speed = IXGBE_LINK_SPEED_UNKNOWN;\n\t\tif (autoc & IXGBE_AUTOC_KX4_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (autoc & IXGBE_AUTOC_KX_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*autoneg = true;\n\t\tbreak;\n\n\tdefault:\n\t\tstatus = IXGBE_ERR_LINK_SETUP;\n\t\tbreak;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_media_type_82598 - Determines media type\n * @hw: pointer to hardware structure\n *\n * Returns the media type (fiber, copper, backplane)\n **/\nSTATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)\n{\n\tenum ixgbe_media_type media_type;\n\n\tDEBUGFUNC(\"ixgbe_get_media_type_82598\");\n\n\t/* Detect if there is a copper PHY attached. */\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_cu_unknown:\n\tcase ixgbe_phy_tn:\n\t\tmedia_type = ixgbe_media_type_copper;\n\t\tgoto out;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Media type for I82598 is based on device ID */\n\tswitch (hw->device_id) {\n\tcase IXGBE_DEV_ID_82598:\n\tcase IXGBE_DEV_ID_82598_BX:\n\t\t/* Default device ID is mezzanine card KX/KX4 */\n\t\tmedia_type = ixgbe_media_type_backplane;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82598AF_DUAL_PORT:\n\tcase IXGBE_DEV_ID_82598AF_SINGLE_PORT:\n\tcase IXGBE_DEV_ID_82598_DA_DUAL_PORT:\n\tcase IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:\n\tcase IXGBE_DEV_ID_82598EB_XF_LR:\n\tcase IXGBE_DEV_ID_82598EB_SFP_LOM:\n\t\tmedia_type = ixgbe_media_type_fiber;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82598EB_CX4:\n\tcase IXGBE_DEV_ID_82598_CX4_DUAL_PORT:\n\t\tmedia_type = ixgbe_media_type_cx4;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82598AT:\n\tcase IXGBE_DEV_ID_82598AT2:\n\t\tmedia_type = ixgbe_media_type_copper;\n\t\tbreak;\n\tdefault:\n\t\tmedia_type = ixgbe_media_type_unknown;\n\t\tbreak;\n\t}\nout:\n\treturn media_type;\n}\n\n/**\n * ixgbe_fc_enable_82598 - Enable flow control\n * @hw: pointer to hardware structure\n *\n * Enable flow control according to the current settings.\n **/\ns32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = IXGBE_SUCCESS;\n\tu32 fctrl_reg;\n\tu32 rmcs_reg;\n\tu32 reg;\n\tu32 fcrtl, fcrth;\n\tu32 link_speed = 0;\n\tint i;\n\tbool link_up;\n\n\tDEBUGFUNC(\"ixgbe_fc_enable_82598\");\n\n\t/* Validate the water mark configuration */\n\tif (!hw->fc.pause_time) {\n\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\tgoto out;\n\t}\n\n\t/* Low water mark of zero causes XOFF floods */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tif ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&\n\t\t hw->fc.high_water[i]) {\n\t\t\tif (!hw->fc.low_water[i] ||\n\t\t\t hw->fc.low_water[i] >= hw->fc.high_water[i]) {\n\t\t\t\tDEBUGOUT(\"Invalid water mark configuration\\n\");\n\t\t\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\t}\n\n\t/*\n\t * On 82598 having Rx FC on causes resets while doing 1G\n\t * so if it's on turn it off once we know link_speed. For\n\t * more details see 82598 Specification update.\n\t */\n\thw->mac.ops.check_link(hw, &link_speed, &link_up, false);\n\tif (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {\n\t\tswitch (hw->fc.requested_mode) {\n\t\tcase ixgbe_fc_full:\n\t\t\thw->fc.requested_mode = ixgbe_fc_tx_pause;\n\t\t\tbreak;\n\t\tcase ixgbe_fc_rx_pause:\n\t\t\thw->fc.requested_mode = ixgbe_fc_none;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* no change */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Negotiate the fc mode to use */\n\tixgbe_fc_autoneg(hw);\n\n\t/* Disable any previous flow control settings */\n\tfctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\tfctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);\n\n\trmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);\n\trmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);\n\n\t/*\n\t * The possible values of fc.current_mode are:\n\t * 0: Flow control is completely disabled\n\t * 1: Rx flow control is enabled (we can receive pause frames,\n\t * but not send pause frames).\n\t * 2: Tx flow control is enabled (we can send pause frames but\n\t * we do not support receiving pause frames).\n\t * 3: Both Rx and Tx flow control (symmetric) are enabled.\n\t * other: Invalid.\n\t */\n\tswitch (hw->fc.current_mode) {\n\tcase ixgbe_fc_none:\n\t\t/*\n\t\t * Flow control is disabled by software override or autoneg.\n\t\t * The code below will actually disable it in the HW.\n\t\t */\n\t\tbreak;\n\tcase ixgbe_fc_rx_pause:\n\t\t/*\n\t\t * Rx Flow control is enabled and Tx Flow control is\n\t\t * disabled by software override. Since there really\n\t\t * isn't a way to advertise that we are capable of RX\n\t\t * Pause ONLY, we will advertise that we support both\n\t\t * symmetric and asymmetric Rx PAUSE. Later, we will\n\t\t * disable the adapter's ability to send PAUSE frames.\n\t\t */\n\t\tfctrl_reg |= IXGBE_FCTRL_RFCE;\n\t\tbreak;\n\tcase ixgbe_fc_tx_pause:\n\t\t/*\n\t\t * Tx Flow control is enabled, and Rx Flow control is\n\t\t * disabled by software override.\n\t\t */\n\t\trmcs_reg |= IXGBE_RMCS_TFCE_802_3X;\n\t\tbreak;\n\tcase ixgbe_fc_full:\n\t\t/* Flow control (both Rx and Tx) is enabled by SW override. */\n\t\tfctrl_reg |= IXGBE_FCTRL_RFCE;\n\t\trmcs_reg |= IXGBE_RMCS_TFCE_802_3X;\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\"Flow control param set incorrectly\\n\");\n\t\tret_val = IXGBE_ERR_CONFIG;\n\t\tgoto out;\n\t\tbreak;\n\t}\n\n\t/* Set 802.3x based flow control settings. */\n\tfctrl_reg |= IXGBE_FCTRL_DPF;\n\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);\n\tIXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);\n\n\t/* Set up and enable Rx high/low water mark thresholds, enable XON. */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tif ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&\n\t\t hw->fc.high_water[i]) {\n\t\t\tfcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;\n\t\t\tfcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);\n\t\t} else {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);\n\t\t}\n\n\t}\n\n\t/* Configure pause time (2 TCs per register) */\n\treg = hw->fc.pause_time * 0x00010001;\n\tfor (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);\n\n\t/* Configure flow control refresh threshold value */\n\tIXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_start_mac_link_82598 - Configures MAC link settings\n * @hw: pointer to hardware structure\n *\n * Configures link settings based on values in the ixgbe_hw struct.\n * Restarts the link. Performs autonegotiation if needed.\n **/\nSTATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t bool autoneg_wait_to_complete)\n{\n\tu32 autoc_reg;\n\tu32 links_reg;\n\tu32 i;\n\ts32 status = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_start_mac_link_82598\");\n\n\t/* Restart link */\n\tautoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tautoc_reg |= IXGBE_AUTOC_AN_RESTART;\n\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);\n\n\t/* Only poll for autoneg to complete if specified to do so */\n\tif (autoneg_wait_to_complete) {\n\t\tif ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==\n\t\t IXGBE_AUTOC_LMS_KX4_AN ||\n\t\t (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==\n\t\t IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {\n\t\t\tlinks_reg = 0; /* Just in case Autoneg time = 0 */\n\t\t\tfor (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {\n\t\t\t\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\t\t\t\tif (links_reg & IXGBE_LINKS_KX_AN_COMP)\n\t\t\t\t\tbreak;\n\t\t\t\tmsec_delay(100);\n\t\t\t}\n\t\t\tif (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {\n\t\t\t\tstatus = IXGBE_ERR_AUTONEG_NOT_COMPLETE;\n\t\t\t\tDEBUGOUT(\"Autonegotiation did not complete.\\n\");\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Add delay to filter out noises during initial link setup */\n\tmsec_delay(50);\n\n\treturn status;\n}\n\n/**\n * ixgbe_validate_link_ready - Function looks for phy link\n * @hw: pointer to hardware structure\n *\n * Function indicates success when phy link is available. If phy is not ready\n * within 5 seconds of MAC indicating link, the function returns error.\n **/\nSTATIC s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)\n{\n\tu32 timeout;\n\tu16 an_reg;\n\n\tif (hw->device_id != IXGBE_DEV_ID_82598AT2)\n\t\treturn IXGBE_SUCCESS;\n\n\tfor (timeout = 0;\n\t timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);\n\n\t\tif ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&\n\t\t (an_reg & IXGBE_MII_AUTONEG_LINK_UP))\n\t\t\tbreak;\n\n\t\tmsec_delay(100);\n\t}\n\n\tif (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {\n\t\tDEBUGOUT(\"Link was indicated but link is down\\n\");\n\t\treturn IXGBE_ERR_LINK_SETUP;\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_check_mac_link_82598 - Get link/speed status\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @link_up: true is link is up, false otherwise\n * @link_up_wait_to_complete: bool used to wait for link up or not\n *\n * Reads the links register to determine if link is up and the current speed\n **/\nSTATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed, bool *link_up,\n\t\t\t\t bool link_up_wait_to_complete)\n{\n\tu32 links_reg;\n\tu32 i;\n\tu16 link_reg, adapt_comp_reg;\n\n\tDEBUGFUNC(\"ixgbe_check_mac_link_82598\");\n\n\t/*\n\t * SERDES PHY requires us to read link status from undocumented\n\t * register 0xC79F. Bit 0 set indicates link is up/ready; clear\n\t * indicates link down. OxC00C is read to check that the XAUI lanes\n\t * are active. Bit 0 clear indicates active; set indicates inactive.\n\t */\n\tif (hw->phy.type == ixgbe_phy_nl) {\n\t\thw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);\n\t\thw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);\n\t\thw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,\n\t\t\t\t &adapt_comp_reg);\n\t\tif (link_up_wait_to_complete) {\n\t\t\tfor (i = 0; i < hw->mac.max_link_up_time; i++) {\n\t\t\t\tif ((link_reg & 1) &&\n\t\t\t\t ((adapt_comp_reg & 1) == 0)) {\n\t\t\t\t\t*link_up = true;\n\t\t\t\t\tbreak;\n\t\t\t\t} else {\n\t\t\t\t\t*link_up = false;\n\t\t\t\t}\n\t\t\t\tmsec_delay(100);\n\t\t\t\thw->phy.ops.read_reg(hw, 0xC79F,\n\t\t\t\t\t\t IXGBE_TWINAX_DEV,\n\t\t\t\t\t\t &link_reg);\n\t\t\t\thw->phy.ops.read_reg(hw, 0xC00C,\n\t\t\t\t\t\t IXGBE_TWINAX_DEV,\n\t\t\t\t\t\t &adapt_comp_reg);\n\t\t\t}\n\t\t} else {\n\t\t\tif ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))\n\t\t\t\t*link_up = true;\n\t\t\telse\n\t\t\t\t*link_up = false;\n\t\t}\n\n\t\tif (*link_up == false)\n\t\t\tgoto out;\n\t}\n\n\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\tif (link_up_wait_to_complete) {\n\t\tfor (i = 0; i < hw->mac.max_link_up_time; i++) {\n\t\t\tif (links_reg & IXGBE_LINKS_UP) {\n\t\t\t\t*link_up = true;\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\t*link_up = false;\n\t\t\t}\n\t\t\tmsec_delay(100);\n\t\t\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\t\t}\n\t} else {\n\t\tif (links_reg & IXGBE_LINKS_UP)\n\t\t\t*link_up = true;\n\t\telse\n\t\t\t*link_up = false;\n\t}\n\n\tif (links_reg & IXGBE_LINKS_SPEED)\n\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\telse\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\n\tif ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&\n\t (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))\n\t\t*link_up = false;\n\nout:\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_setup_mac_link_82598 - Set MAC link speed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Set the link speed in the AUTOC register and restarts link.\n **/\nSTATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg_wait_to_complete)\n{\n\tbool autoneg = false;\n\ts32 status = IXGBE_SUCCESS;\n\tixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;\n\tu32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tu32 autoc = curr_autoc;\n\tu32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;\n\n\tDEBUGFUNC(\"ixgbe_setup_mac_link_82598\");\n\n\t/* Check to see if speed passed in is supported. */\n\tixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);\n\tspeed &= link_capabilities;\n\n\tif (speed == IXGBE_LINK_SPEED_UNKNOWN)\n\t\tstatus = IXGBE_ERR_LINK_SETUP;\n\n\t/* Set KX4/KX support according to speed requested */\n\telse if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||\n\t\t link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {\n\t\tautoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;\n\t\tif (speed & IXGBE_LINK_SPEED_10GB_FULL)\n\t\t\tautoc |= IXGBE_AUTOC_KX4_SUPP;\n\t\tif (speed & IXGBE_LINK_SPEED_1GB_FULL)\n\t\t\tautoc |= IXGBE_AUTOC_KX_SUPP;\n\t\tif (autoc != curr_autoc)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);\n\t}\n\n\tif (status == IXGBE_SUCCESS) {\n\t\t/*\n\t\t * Setup and restart the link based on the new values in\n\t\t * ixgbe_hw This will write the AUTOC register based on the new\n\t\t * stored values\n\t\t */\n\t\tstatus = ixgbe_start_mac_link_82598(hw,\n\t\t\t\t\t\t autoneg_wait_to_complete);\n\t}\n\n\treturn status;\n}\n\n\n/**\n * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg_wait_to_complete: true if waiting is needed to complete\n *\n * Sets the link speed in the AUTOC register in the MAC and restarts link.\n **/\nSTATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t\t bool autoneg_wait_to_complete)\n{\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_setup_copper_link_82598\");\n\n\t/* Setup the PHY according to input speed */\n\tstatus = hw->phy.ops.setup_link_speed(hw, speed,\n\t\t\t\t\t autoneg_wait_to_complete);\n\t/* Set up MAC */\n\tixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);\n\n\treturn status;\n}\n\n/**\n * ixgbe_reset_hw_82598 - Performs hardware reset\n * @hw: pointer to hardware structure\n *\n * Resets the hardware by resetting the transmit and receive units, masks and\n * clears all interrupts, performing a PHY reset, and performing a link (MAC)\n * reset.\n **/\nSTATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_SUCCESS;\n\ts32 phy_status = IXGBE_SUCCESS;\n\tu32 ctrl;\n\tu32 gheccr;\n\tu32 i;\n\tu32 autoc;\n\tu8 analog_val;\n\n\tDEBUGFUNC(\"ixgbe_reset_hw_82598\");\n\n\t/* Call adapter stop to disable tx/rx and clear interrupts */\n\tstatus = hw->mac.ops.stop_adapter(hw);\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto reset_hw_out;\n\n\t/*\n\t * Power up the Atlas Tx lanes if they are currently powered down.\n\t * Atlas Tx lanes are powered down for MAC loopback tests, but\n\t * they are not automatically restored on reset.\n\t */\n\thw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);\n\tif (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {\n\t\t/* Enable Tx Atlas so packets can be transmitted again */\n\t\thw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,\n\t\t\t\t\t &analog_val);\n\t\tanalog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;\n\t\thw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,\n\t\t\t\t\t analog_val);\n\n\t\thw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,\n\t\t\t\t\t &analog_val);\n\t\tanalog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;\n\t\thw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,\n\t\t\t\t\t analog_val);\n\n\t\thw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,\n\t\t\t\t\t &analog_val);\n\t\tanalog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;\n\t\thw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,\n\t\t\t\t\t analog_val);\n\n\t\thw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,\n\t\t\t\t\t &analog_val);\n\t\tanalog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;\n\t\thw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,\n\t\t\t\t\t analog_val);\n\t}\n\n\t/* Reset PHY */\n\tif (hw->phy.reset_disable == false) {\n\t\t/* PHY ops must be identified and initialized prior to reset */\n\n\t\t/* Init PHY and function pointers, perform SFP setup */\n\t\tphy_status = hw->phy.ops.init(hw);\n\t\tif (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)\n\t\t\tgoto reset_hw_out;\n\t\tif (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)\n\t\t\tgoto mac_reset_top;\n\n\t\thw->phy.ops.reset(hw);\n\t}\n\nmac_reset_top:\n\t/*\n\t * Issue global reset to the MAC. This needs to be a SW reset.\n\t * If link reset is used, it might reset the MAC when mng is using it\n\t */\n\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Poll for reset bit to self-clear indicating reset is complete */\n\tfor (i = 0; i < 10; i++) {\n\t\tusec_delay(1);\n\t\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);\n\t\tif (!(ctrl & IXGBE_CTRL_RST))\n\t\t\tbreak;\n\t}\n\tif (ctrl & IXGBE_CTRL_RST) {\n\t\tstatus = IXGBE_ERR_RESET_FAILED;\n\t\tDEBUGOUT(\"Reset polling failed to complete.\\n\");\n\t}\n\n\tmsec_delay(50);\n\n\t/*\n\t * Double resets are required for recovery from certain error\n\t * conditions. Between resets, it is necessary to stall to allow time\n\t * for any pending HW events to complete.\n\t */\n\tif (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {\n\t\thw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;\n\t\tgoto mac_reset_top;\n\t}\n\n\tgheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);\n\tgheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));\n\tIXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);\n\n\t/*\n\t * Store the original AUTOC value if it has not been\n\t * stored off yet. Otherwise restore the stored original\n\t * AUTOC value since the reset operation sets back to deaults.\n\t */\n\tautoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tif (hw->mac.orig_link_settings_stored == false) {\n\t\thw->mac.orig_autoc = autoc;\n\t\thw->mac.orig_link_settings_stored = true;\n\t} else if (autoc != hw->mac.orig_autoc) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);\n\t}\n\n\t/* Store the permanent mac address */\n\thw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);\n\n\t/*\n\t * Store MAC address from RAR0, clear receive address registers, and\n\t * clear the multicast table\n\t */\n\thw->mac.ops.init_rx_addrs(hw);\n\nreset_hw_out:\n\tif (phy_status != IXGBE_SUCCESS)\n\t\tstatus = phy_status;\n\n\treturn status;\n}\n\n/**\n * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address\n * @hw: pointer to hardware struct\n * @rar: receive address register index to associate with a VMDq index\n * @vmdq: VMDq set index\n **/\ns32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n{\n\tu32 rar_high;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\tDEBUGFUNC(\"ixgbe_set_vmdq_82598\");\n\n\t/* Make sure we are using a valid rar index range */\n\tif (rar >= rar_entries) {\n\t\tDEBUGOUT1(\"RAR index %d is out of range.\\n\", rar);\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));\n\trar_high &= ~IXGBE_RAH_VIND_MASK;\n\trar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);\n\tIXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address\n * @hw: pointer to hardware struct\n * @rar: receive address register index to associate with a VMDq index\n * @vmdq: VMDq clear index (not used in 82598, but elsewhere)\n **/\nSTATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n{\n\tu32 rar_high;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\tUNREFERENCED_1PARAMETER(vmdq);\n\n\t/* Make sure we are using a valid rar index range */\n\tif (rar >= rar_entries) {\n\t\tDEBUGOUT1(\"RAR index %d is out of range.\\n\", rar);\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));\n\tif (rar_high & IXGBE_RAH_VIND_MASK) {\n\t\trar_high &= ~IXGBE_RAH_VIND_MASK;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_set_vfta_82598 - Set VLAN filter table\n * @hw: pointer to hardware structure\n * @vlan: VLAN id to write to VLAN filter\n * @vind: VMDq output index that maps queue to VLAN id in VFTA\n * @vlan_on: boolean flag to turn on/off VLAN in VFTA\n *\n * Turn on/off specified VLAN in the VLAN filter table.\n **/\ns32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n\t\t\t bool vlan_on)\n{\n\tu32 regindex;\n\tu32 bitindex;\n\tu32 bits;\n\tu32 vftabyte;\n\n\tDEBUGFUNC(\"ixgbe_set_vfta_82598\");\n\n\tif (vlan > 4095)\n\t\treturn IXGBE_ERR_PARAM;\n\n\t/* Determine 32-bit word position in array */\n\tregindex = (vlan >> 5) & 0x7F; /* upper seven bits */\n\n\t/* Determine the location of the (VMD) queue index */\n\tvftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */\n\tbitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */\n\n\t/* Set the nibble for VMD queue index */\n\tbits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));\n\tbits &= (~(0x0F << bitindex));\n\tbits |= (vind << bitindex);\n\tIXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);\n\n\t/* Determine the location of the bit for this VLAN id */\n\tbitindex = vlan & 0x1F; /* lower five bits */\n\n\tbits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));\n\tif (vlan_on)\n\t\t/* Turn on this VLAN id */\n\t\tbits |= (1 << bitindex);\n\telse\n\t\t/* Turn off this VLAN id */\n\t\tbits &= ~(1 << bitindex);\n\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_clear_vfta_82598 - Clear VLAN filter table\n * @hw: pointer to hardware structure\n *\n * Clears the VLAN filer table, and the VMDq index associated with the filter\n **/\nSTATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)\n{\n\tu32 offset;\n\tu32 vlanbyte;\n\n\tDEBUGFUNC(\"ixgbe_clear_vfta_82598\");\n\n\tfor (offset = 0; offset < hw->mac.vft_size; offset++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);\n\n\tfor (vlanbyte = 0; vlanbyte < 4; vlanbyte++)\n\t\tfor (offset = 0; offset < hw->mac.vft_size; offset++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),\n\t\t\t\t\t0);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register\n * @hw: pointer to hardware structure\n * @reg: analog register to read\n * @val: read value\n *\n * Performs read operation to Atlas analog register specified.\n **/\ns32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)\n{\n\tu32 atlas_ctl;\n\n\tDEBUGFUNC(\"ixgbe_read_analog_reg8_82598\");\n\n\tIXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,\n\t\t\tIXGBE_ATLASCTL_WRITE_CMD | (reg << 8));\n\tIXGBE_WRITE_FLUSH(hw);\n\tusec_delay(10);\n\tatlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);\n\t*val = (u8)atlas_ctl;\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register\n * @hw: pointer to hardware structure\n * @reg: atlas register to write\n * @val: value to write\n *\n * Performs write operation to Atlas analog register specified.\n **/\ns32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)\n{\n\tu32 atlas_ctl;\n\n\tDEBUGFUNC(\"ixgbe_write_analog_reg8_82598\");\n\n\tatlas_ctl = (reg << 8) | val;\n\tIXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);\n\tIXGBE_WRITE_FLUSH(hw);\n\tusec_delay(10);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.\n * @hw: pointer to hardware structure\n * @dev_addr: address to read from\n * @byte_offset: byte offset to read from dev_addr\n * @eeprom_data: value read\n *\n * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.\n **/\nSTATIC s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,\n\t\t\t\t u8 byte_offset, u8 *eeprom_data)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu16 sfp_addr = 0;\n\tu16 sfp_data = 0;\n\tu16 sfp_stat = 0;\n\tu16 gssr;\n\tu32 i;\n\n\tDEBUGFUNC(\"ixgbe_read_i2c_phy_82598\");\n\n\tif (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)\n\t\tgssr = IXGBE_GSSR_PHY1_SM;\n\telse\n\t\tgssr = IXGBE_GSSR_PHY0_SM;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)\n\t\treturn IXGBE_ERR_SWFW_SYNC;\n\n\tif (hw->phy.type == ixgbe_phy_nl) {\n\t\t/*\n\t\t * NetLogic phy SDA/SCL registers are at addresses 0xC30A to\n\t\t * 0xC30D. These registers are used to talk to the SFP+\n\t\t * module's EEPROM through the SDA/SCL (I2C) interface.\n\t\t */\n\t\tsfp_addr = (dev_addr << 8) + byte_offset;\n\t\tsfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);\n\t\thw->phy.ops.write_reg_mdi(hw,\n\t\t\t\t\t IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,\n\t\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t\t sfp_addr);\n\n\t\t/* Poll status */\n\t\tfor (i = 0; i < 100; i++) {\n\t\t\thw->phy.ops.read_reg_mdi(hw,\n\t\t\t\t\t\tIXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,\n\t\t\t\t\t\tIXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t\t\t&sfp_stat);\n\t\t\tsfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;\n\t\t\tif (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)\n\t\t\t\tbreak;\n\t\t\tmsec_delay(10);\n\t\t}\n\n\t\tif (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {\n\t\t\tDEBUGOUT(\"EEPROM read did not pass.\\n\");\n\t\t\tstatus = IXGBE_ERR_SFP_NOT_PRESENT;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/* Read data */\n\t\thw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,\n\t\t\t\t\tIXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);\n\n\t\t*eeprom_data = (u8)(sfp_data >> 8);\n\t} else {\n\t\tstatus = IXGBE_ERR_PHY;\n\t}\n\nout:\n\thw->mac.ops.release_swfw_sync(hw, gssr);\n\treturn status;\n}\n\n/**\n * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.\n * @hw: pointer to hardware structure\n * @byte_offset: EEPROM byte offset to read\n * @eeprom_data: value read\n *\n * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\tu8 *eeprom_data)\n{\n\treturn ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,\n\t\t\t\t\tbyte_offset, eeprom_data);\n}\n\n/**\n * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset at address 0xA2\n * @eeprom_data: value read\n *\n * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C\n **/\nSTATIC s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\tu8 *sff8472_data)\n{\n\treturn ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,\n\t\t\t\t\tbyte_offset, sff8472_data);\n}\n\n/**\n * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type\n * @hw: pointer to hardware structure\n *\n * Determines physical layer capabilities of the current configuration.\n **/\nu32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)\n{\n\tu32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n\tu32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tu32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;\n\tu32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;\n\tu16 ext_ability = 0;\n\n\tDEBUGFUNC(\"ixgbe_get_supported_physical_layer_82598\");\n\n\thw->phy.ops.identify(hw);\n\n\t/* Copper PHY must be checked before AUTOC LMS to determine correct\n\t * physical layer because 10GBase-T PHYs use LMS = KX4/KX */\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_tn:\n\tcase ixgbe_phy_cu_unknown:\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,\n\t\tIXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);\n\t\tif (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;\n\t\tif (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;\n\t\tif (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;\n\t\tgoto out;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tswitch (autoc & IXGBE_AUTOC_LMS_MASK) {\n\tcase IXGBE_AUTOC_LMS_1G_AN:\n\tcase IXGBE_AUTOC_LMS_1G_LINK_NO_AN:\n\t\tif (pma_pmd_1g == IXGBE_AUTOC_1G_KX)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;\n\t\telse\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;\n\t\tbreak;\n\tcase IXGBE_AUTOC_LMS_10G_LINK_NO_AN:\n\t\tif (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;\n\t\telse if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;\n\t\telse /* XAUI */\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n\t\tbreak;\n\tcase IXGBE_AUTOC_LMS_KX4_AN:\n\tcase IXGBE_AUTOC_LMS_KX4_AN_1G_AN:\n\t\tif (autoc & IXGBE_AUTOC_KX_SUPP)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;\n\t\tif (autoc & IXGBE_AUTOC_KX4_SUPP)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (hw->phy.type == ixgbe_phy_nl) {\n\t\thw->phy.ops.identify_sfp(hw);\n\n\t\tswitch (hw->phy.sfp_type) {\n\t\tcase ixgbe_sfp_type_da_cu:\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;\n\t\t\tbreak;\n\t\tcase ixgbe_sfp_type_sr:\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;\n\t\t\tbreak;\n\t\tcase ixgbe_sfp_type_lr:\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tswitch (hw->device_id) {\n\tcase IXGBE_DEV_ID_82598_DA_DUAL_PORT:\n\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82598AF_DUAL_PORT:\n\tcase IXGBE_DEV_ID_82598AF_SINGLE_PORT:\n\tcase IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:\n\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82598EB_XF_LR:\n\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\nout:\n\treturn physical_layer;\n}\n\n/**\n * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple\n * port devices.\n * @hw: pointer to the HW structure\n *\n * Calls common function and corrects issue with some single port devices\n * that enable LAN1 but not LAN0.\n **/\nvoid ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_bus_info *bus = &hw->bus;\n\tu16 pci_gen = 0;\n\tu16 pci_ctrl2 = 0;\n\n\tDEBUGFUNC(\"ixgbe_set_lan_id_multi_port_pcie_82598\");\n\n\tixgbe_set_lan_id_multi_port_pcie(hw);\n\n\t/* check if LAN0 is disabled */\n\thw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);\n\tif ((pci_gen != 0) && (pci_gen != 0xFFFF)) {\n\n\t\thw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);\n\n\t\t/* if LAN0 is completely disabled force function to 0 */\n\t\tif ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&\n\t\t !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&\n\t\t !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {\n\n\t\t\tbus->func = 0;\n\t\t}\n\t}\n}\n\n/**\n * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering\n * @hw: pointer to hardware structure\n *\n **/\nvoid ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)\n{\n\tu32 regval;\n\tu32 i;\n\n\tDEBUGFUNC(\"ixgbe_enable_relaxed_ordering_82598\");\n\n\t/* Enable relaxed ordering */\n\tfor (i = 0; ((i < hw->mac.max_tx_queues) &&\n\t (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {\n\t\tregval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));\n\t\tregval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);\n\t}\n\n\tfor (i = 0; ((i < hw->mac.max_rx_queues) &&\n\t (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {\n\t\tregval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));\n\t\tregval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |\n\t\t\t IXGBE_DCA_RXCTRL_HEAD_WRO_EN;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);\n\t}\n\n}\n\n/**\n * ixgbe_set_rxpba_82598 - Initialize RX packet buffer\n * @hw: pointer to hardware structure\n * @num_pb: number of packet buffers to allocate\n * @headroom: reserve n KB of headroom\n * @strategy: packet buffer allocation strategy\n **/\nSTATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,\n\t\t\t\t u32 headroom, int strategy)\n{\n\tu32 rxpktsize = IXGBE_RXPBSIZE_64KB;\n\tu8 i = 0;\n\tUNREFERENCED_1PARAMETER(headroom);\n\n\tif (!num_pb)\n\t\treturn;\n\n\t/* Setup Rx packet buffer sizes */\n\tswitch (strategy) {\n\tcase PBA_STRATEGY_WEIGHTED:\n\t\t/* Setup the first four at 80KB */\n\t\trxpktsize = IXGBE_RXPBSIZE_80KB;\n\t\tfor (; i < 4; i++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);\n\t\t/* Setup the last four at 48KB...don't re-init i */\n\t\trxpktsize = IXGBE_RXPBSIZE_48KB;\n\t\t/* Fall Through */\n\tcase PBA_STRATEGY_EQUAL:\n\tdefault:\n\t\t/* Divide the remaining Rx packet buffer evenly among the TCs */\n\t\tfor (; i < IXGBE_MAX_PACKET_BUFFERS; i++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);\n\t\tbreak;\n\t}\n\n\t/* Setup Tx packet buffer sizes */\n\tfor (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);\n}\n\n/**\n * ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit\n * @hw: pointer to hardware structure\n * @regval: register value to write to RXCTRL\n *\n * Enables the Rx DMA unit\n **/\ns32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval)\n{\n\tDEBUGFUNC(\"ixgbe_enable_rx_dma_82598\");\n\n\tIXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);\n\n\treturn IXGBE_SUCCESS;\n}\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_82598.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _IXGBE_82598_H_\n#define _IXGBE_82598_H_\n\nu32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);\ns32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw);\ns32 ixgbe_start_hw_82598(struct ixgbe_hw *hw);\nvoid ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw);\ns32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);\ns32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on);\ns32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);\ns32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);\ns32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\tu8 *eeprom_data);\nu32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);\ns32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);\nvoid ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);\nvoid ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);\ns32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval);\n#endif /* _IXGBE_82598_H_ */\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_82599.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"ixgbe_type.h\"\n#include \"ixgbe_82599.h\"\n#include \"ixgbe_api.h\"\n#include \"ixgbe_common.h\"\n#include \"ixgbe_phy.h\"\n\n#define IXGBE_82599_MAX_TX_QUEUES 128\n#define IXGBE_82599_MAX_RX_QUEUES 128\n#define IXGBE_82599_RAR_ENTRIES 128\n#define IXGBE_82599_MC_TBL_SIZE 128\n#define IXGBE_82599_VFT_TBL_SIZE 128\n#define IXGBE_82599_RX_PB_SIZE\t 512\n\nSTATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t\t bool autoneg_wait_to_complete);\nSTATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);\nSTATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,\n\t\t\t\t u16 offset, u16 *data);\nSTATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data);\nSTATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\tu8 dev_addr, u8 *data);\nSTATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\tu8 dev_addr, u8 data);\n\nvoid ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"ixgbe_init_mac_link_ops_82599\");\n\n\t/*\n\t * enable the laser control functions for SFP+ fiber\n\t * and MNG not enabled\n\t */\n\tif ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&\n\t !ixgbe_mng_enabled(hw)) {\n\t\tmac->ops.disable_tx_laser =\n\t\t\t\t ixgbe_disable_tx_laser_multispeed_fiber;\n\t\tmac->ops.enable_tx_laser =\n\t\t\t\t\tixgbe_enable_tx_laser_multispeed_fiber;\n\t\tmac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber;\n\n\t} else {\n\t\tmac->ops.disable_tx_laser = NULL;\n\t\tmac->ops.enable_tx_laser = NULL;\n\t\tmac->ops.flap_tx_laser = NULL;\n\t}\n\n\tif (hw->phy.multispeed_fiber) {\n\t\t/* Set up dual speed SFP+ support */\n\t\tmac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;\n\t\tmac->ops.setup_mac_link = ixgbe_setup_mac_link_82599;\n\t\tmac->ops.set_rate_select_speed =\n\t\t\t\t\t ixgbe_set_hard_rate_select_speed;\n\t} else {\n\t\tif ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&\n\t\t (hw->phy.smart_speed == ixgbe_smart_speed_auto ||\n\t\t hw->phy.smart_speed == ixgbe_smart_speed_on) &&\n\t\t !ixgbe_verify_lesm_fw_enabled_82599(hw)) {\n\t\t\tmac->ops.setup_link = ixgbe_setup_mac_link_smartspeed;\n\t\t} else {\n\t\t\tmac->ops.setup_link = ixgbe_setup_mac_link_82599;\n\t\t}\n\t}\n}\n\n/**\n * ixgbe_init_phy_ops_82599 - PHY/SFP specific init\n * @hw: pointer to hardware structure\n *\n * Initialize any function pointers that were not able to be\n * set during init_shared_code because the PHY/SFP type was\n * not known. Perform the SFP init if necessary.\n *\n **/\ns32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\ts32 ret_val = IXGBE_SUCCESS;\n\tu32 esdp;\n\n\tDEBUGFUNC(\"ixgbe_init_phy_ops_82599\");\n\n\tif (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {\n\t\t/* Store flag indicating I2C bus access control unit. */\n\t\thw->phy.qsfp_shared_i2c_bus = TRUE;\n\n\t\t/* Initialize access to QSFP+ I2C bus */\n\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\tesdp |= IXGBE_ESDP_SDP0_DIR;\n\t\tesdp &= ~IXGBE_ESDP_SDP1_DIR;\n\t\tesdp &= ~IXGBE_ESDP_SDP0;\n\t\tesdp &= ~IXGBE_ESDP_SDP0_NATIVE;\n\t\tesdp &= ~IXGBE_ESDP_SDP1_NATIVE;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\n\t\tphy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599;\n\t\tphy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599;\n\t}\n\t/* Identify the PHY or SFP module */\n\tret_val = phy->ops.identify(hw);\n\tif (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)\n\t\tgoto init_phy_ops_out;\n\n\t/* Setup function pointers based on detected SFP module and speeds */\n\tixgbe_init_mac_link_ops_82599(hw);\n\tif (hw->phy.sfp_type != ixgbe_sfp_type_unknown)\n\t\thw->phy.ops.reset = NULL;\n\n\t/* If copper media, overwrite with copper function pointers */\n\tif (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {\n\t\tmac->ops.setup_link = ixgbe_setup_copper_link_82599;\n\t\tmac->ops.get_link_capabilities =\n\t\t\t\t ixgbe_get_copper_link_capabilities_generic;\n\t}\n\n\t/* Set necessary function pointers based on PHY type */\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_tn:\n\t\tphy->ops.setup_link = ixgbe_setup_phy_link_tnx;\n\t\tphy->ops.check_link = ixgbe_check_phy_link_tnx;\n\t\tphy->ops.get_firmware_version =\n\t\t\t ixgbe_get_phy_firmware_version_tnx;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\ninit_phy_ops_out:\n\treturn ret_val;\n}\n\ns32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = IXGBE_SUCCESS;\n\tu16 list_offset, data_offset, data_value;\n\n\tDEBUGFUNC(\"ixgbe_setup_sfp_modules_82599\");\n\n\tif (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {\n\t\tixgbe_init_mac_link_ops_82599(hw);\n\n\t\thw->phy.ops.reset = NULL;\n\n\t\tret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,\n\t\t\t\t\t\t\t &data_offset);\n\t\tif (ret_val != IXGBE_SUCCESS)\n\t\t\tgoto setup_sfp_out;\n\n\t\t/* PHY config will finish before releasing the semaphore */\n\t\tret_val = hw->mac.ops.acquire_swfw_sync(hw,\n\t\t\t\t\t\t\tIXGBE_GSSR_MAC_CSR_SM);\n\t\tif (ret_val != IXGBE_SUCCESS) {\n\t\t\tret_val = IXGBE_ERR_SWFW_SYNC;\n\t\t\tgoto setup_sfp_out;\n\t\t}\n\n\t\tif (hw->eeprom.ops.read(hw, ++data_offset, &data_value))\n\t\t\tgoto setup_sfp_err;\n\t\twhile (data_value != 0xffff) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);\n\t\t\tIXGBE_WRITE_FLUSH(hw);\n\t\t\tif (hw->eeprom.ops.read(hw, ++data_offset, &data_value))\n\t\t\t\tgoto setup_sfp_err;\n\t\t}\n\n\t\t/* Release the semaphore */\n\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);\n\t\t/* Delay obtaining semaphore again to allow FW access\n\t\t * prot_autoc_write uses the semaphore too.\n\t\t */\n\t\tmsec_delay(hw->eeprom.semaphore_delay);\n\n\t\t/* Restart DSP and set SFI mode */\n\t\tret_val = hw->mac.ops.prot_autoc_write(hw,\n\t\t\thw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,\n\t\t\tfalse);\n\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"sfp module setup not complete\\n\");\n\t\t\tret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;\n\t\t\tgoto setup_sfp_out;\n\t\t}\n\n\t}\n\nsetup_sfp_out:\n\treturn ret_val;\n\nsetup_sfp_err:\n\t/* Release the semaphore */\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);\n\t/* Delay obtaining semaphore again to allow FW access */\n\tmsec_delay(hw->eeprom.semaphore_delay);\n\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t \"eeprom read at offset %d failed\", data_offset);\n\treturn IXGBE_ERR_PHY;\n}\n\n/**\n * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read\n * @hw: pointer to hardware structure\n * @locked: Return the if we locked for this read.\n * @reg_val: Value we read from AUTOC\n *\n * For this part (82599) we need to wrap read-modify-writes with a possible\n * FW/SW lock. It is assumed this lock will be freed with the next\n * prot_autoc_write_82599().\n */\ns32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)\n{\n\ts32 ret_val;\n\n\t*locked = false;\n\t /* If LESM is on then we need to hold the SW/FW semaphore. */\n\tif (ixgbe_verify_lesm_fw_enabled_82599(hw)) {\n\t\tret_val = hw->mac.ops.acquire_swfw_sync(hw,\n\t\t\t\t\tIXGBE_GSSR_MAC_CSR_SM);\n\t\tif (ret_val != IXGBE_SUCCESS)\n\t\t\treturn IXGBE_ERR_SWFW_SYNC;\n\n\t\t*locked = true;\n\t}\n\n\t*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write\n * @hw: pointer to hardware structure\n * @reg_val: value to write to AUTOC\n * @locked: bool to indicate whether the SW/FW lock was already taken by\n * previous proc_autoc_read_82599.\n *\n * This part (82599) may need to hold the SW/FW lock around all writes to\n * AUTOC. Likewise after a write we need to do a pipeline reset.\n */\ns32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)\n{\n\ts32 ret_val = IXGBE_SUCCESS;\n\n\t/* Blocked by MNG FW so bail */\n\tif (ixgbe_check_reset_blocked(hw))\n\t\tgoto out;\n\n\t/* We only need to get the lock if:\n\t * - We didn't do it already (in the read part of a read-modify-write)\n\t * - LESM is enabled.\n\t */\n\tif (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {\n\t\tret_val = hw->mac.ops.acquire_swfw_sync(hw,\n\t\t\t\t\tIXGBE_GSSR_MAC_CSR_SM);\n\t\tif (ret_val != IXGBE_SUCCESS)\n\t\t\treturn IXGBE_ERR_SWFW_SYNC;\n\n\t\tlocked = true;\n\t}\n\n\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);\n\tret_val = ixgbe_reset_pipeline_82599(hw);\n\nout:\n\t/* Free the SW/FW semaphore as we either grabbed it here or\n\t * already had it when this function was called.\n\t */\n\tif (locked)\n\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_init_ops_82599 - Inits func ptrs and MAC type\n * @hw: pointer to hardware structure\n *\n * Initialize the function pointers and assign the MAC type for 82599.\n * Does not touch the hardware.\n **/\n\ns32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"ixgbe_init_ops_82599\");\n\n\tixgbe_init_phy_ops_generic(hw);\n\tret_val = ixgbe_init_ops_generic(hw);\n\n\t/* PHY */\n\tphy->ops.identify = ixgbe_identify_phy_82599;\n\tphy->ops.init = ixgbe_init_phy_ops_82599;\n\n\t/* MAC */\n\tmac->ops.reset_hw = ixgbe_reset_hw_82599;\n\tmac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;\n\tmac->ops.get_media_type = ixgbe_get_media_type_82599;\n\tmac->ops.get_supported_physical_layer =\n\t\t\t\t ixgbe_get_supported_physical_layer_82599;\n\tmac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;\n\tmac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;\n\tmac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599;\n\tmac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599;\n\tmac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599;\n\tmac->ops.start_hw = ixgbe_start_hw_82599;\n\tmac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;\n\tmac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;\n\tmac->ops.get_device_caps = ixgbe_get_device_caps_generic;\n\tmac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;\n\tmac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;\n\tmac->ops.prot_autoc_read = prot_autoc_read_82599;\n\tmac->ops.prot_autoc_write = prot_autoc_write_82599;\n\n\t/* RAR, Multicast, VLAN */\n\tmac->ops.set_vmdq = ixgbe_set_vmdq_generic;\n\tmac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;\n\tmac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;\n\tmac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;\n\tmac->rar_highwater = 1;\n\tmac->ops.set_vfta = ixgbe_set_vfta_generic;\n\tmac->ops.set_vlvf = ixgbe_set_vlvf_generic;\n\tmac->ops.clear_vfta = ixgbe_clear_vfta_generic;\n\tmac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;\n\tmac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599;\n\tmac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;\n\tmac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;\n\n\t/* Link */\n\tmac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599;\n\tmac->ops.check_link = ixgbe_check_mac_link_generic;\n\tmac->ops.setup_rxpba = ixgbe_set_rxpba_generic;\n\tixgbe_init_mac_link_ops_82599(hw);\n\n\tmac->mcft_size\t\t= IXGBE_82599_MC_TBL_SIZE;\n\tmac->vft_size\t\t= IXGBE_82599_VFT_TBL_SIZE;\n\tmac->num_rar_entries\t= IXGBE_82599_RAR_ENTRIES;\n\tmac->rx_pb_size\t\t= IXGBE_82599_RX_PB_SIZE;\n\tmac->max_rx_queues\t= IXGBE_82599_MAX_RX_QUEUES;\n\tmac->max_tx_queues\t= IXGBE_82599_MAX_TX_QUEUES;\n\tmac->max_msix_vectors\t= ixgbe_get_pcie_msix_count_generic(hw);\n\n\tmac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &\n\t\t\t\t IXGBE_FWSM_MODE_MASK) ? true : false;\n\n\thw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;\n\n\t/* EEPROM */\n\teeprom->ops.read = ixgbe_read_eeprom_82599;\n\teeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599;\n\n\t/* Manageability interface */\n\tmac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;\n\n\tmac->ops.get_thermal_sensor_data =\n\t\t\t\t\t ixgbe_get_thermal_sensor_data_generic;\n\tmac->ops.init_thermal_sensor_thresh =\n\t\t\t\t ixgbe_init_thermal_sensor_thresh_generic;\n\n\tmac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_get_link_capabilities_82599 - Determines link capabilities\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @autoneg: true when autoneg or autotry is enabled\n *\n * Determines the link capabilities by reading the AUTOC register.\n **/\ns32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t bool *autoneg)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu32 autoc = 0;\n\n\tDEBUGFUNC(\"ixgbe_get_link_capabilities_82599\");\n\n\n\t/* Check if 1G SFP module. */\n\tif (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||\n\t hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||\n\t hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||\n\t hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||\n\t hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||\n\t hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*autoneg = true;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * Determine link capabilities based on the stored value of AUTOC,\n\t * which represents EEPROM defaults. If AUTOC value has not\n\t * been stored, use the current register values.\n\t */\n\tif (hw->mac.orig_link_settings_stored)\n\t\tautoc = hw->mac.orig_autoc;\n\telse\n\t\tautoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\n\tswitch (autoc & IXGBE_AUTOC_LMS_MASK) {\n\tcase IXGBE_AUTOC_LMS_1G_LINK_NO_AN:\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*autoneg = false;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_10G_LINK_NO_AN:\n\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\t\t*autoneg = false;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_1G_AN:\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*autoneg = true;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_10G_SERIAL:\n\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\t\t*autoneg = false;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_KX4_KX_KR:\n\tcase IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:\n\t\t*speed = IXGBE_LINK_SPEED_UNKNOWN;\n\t\tif (autoc & IXGBE_AUTOC_KR_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (autoc & IXGBE_AUTOC_KX4_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (autoc & IXGBE_AUTOC_KX_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*autoneg = true;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:\n\t\t*speed = IXGBE_LINK_SPEED_100_FULL;\n\t\tif (autoc & IXGBE_AUTOC_KR_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (autoc & IXGBE_AUTOC_KX4_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (autoc & IXGBE_AUTOC_KX_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*autoneg = true;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_SGMII_1G_100M:\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;\n\t\t*autoneg = false;\n\t\tbreak;\n\n\tdefault:\n\t\tstatus = IXGBE_ERR_LINK_SETUP;\n\t\tgoto out;\n\t\tbreak;\n\t}\n\n\tif (hw->phy.multispeed_fiber) {\n\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL |\n\t\t\t IXGBE_LINK_SPEED_1GB_FULL;\n\n\t\t/* QSFP must not enable full auto-negotiation\n\t\t * Limited autoneg is enabled at 1G\n\t\t */\n\t\tif (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)\n\t\t\t*autoneg = false;\n\t\telse\n\t\t\t*autoneg = true;\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_get_media_type_82599 - Get media type\n * @hw: pointer to hardware structure\n *\n * Returns the media type (fiber, copper, backplane)\n **/\nenum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)\n{\n\tenum ixgbe_media_type media_type;\n\n\tDEBUGFUNC(\"ixgbe_get_media_type_82599\");\n\n\t/* Detect if there is a copper PHY attached. */\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_cu_unknown:\n\tcase ixgbe_phy_tn:\n\t\tmedia_type = ixgbe_media_type_copper;\n\t\tgoto out;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tswitch (hw->device_id) {\n\tcase IXGBE_DEV_ID_82599_KX4:\n\tcase IXGBE_DEV_ID_82599_KX4_MEZZ:\n\tcase IXGBE_DEV_ID_82599_COMBO_BACKPLANE:\n\tcase IXGBE_DEV_ID_82599_KR:\n\tcase IXGBE_DEV_ID_82599_BACKPLANE_FCOE:\n\tcase IXGBE_DEV_ID_82599_XAUI_LOM:\n\t\t/* Default device ID is mezzanine card KX/KX4 */\n\t\tmedia_type = ixgbe_media_type_backplane;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_SFP:\n\tcase IXGBE_DEV_ID_82599_SFP_FCOE:\n\tcase IXGBE_DEV_ID_82599_SFP_EM:\n\tcase IXGBE_DEV_ID_82599_SFP_SF2:\n\tcase IXGBE_DEV_ID_82599_SFP_SF_QP:\n\tcase IXGBE_DEV_ID_82599EN_SFP:\n\t\tmedia_type = ixgbe_media_type_fiber;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_CX4:\n\t\tmedia_type = ixgbe_media_type_cx4;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_T3_LOM:\n\t\tmedia_type = ixgbe_media_type_copper;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_LS:\n\t\tmedia_type = ixgbe_media_type_fiber_lco;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_QSFP_SF_QP:\n\t\tmedia_type = ixgbe_media_type_fiber_qsfp;\n\t\tbreak;\n\tdefault:\n\t\tmedia_type = ixgbe_media_type_unknown;\n\t\tbreak;\n\t}\nout:\n\treturn media_type;\n}\n\n/**\n * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3\n * @hw: pointer to hardware structure\n *\n * Disables link during D3 power down sequence.\n *\n **/\nvoid ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)\n{\n\tu32 autoc2_reg;\n\tu16 ee_ctrl_2 = 0;\n\n\tDEBUGFUNC(\"ixgbe_stop_mac_link_on_d3_82599\");\n\tixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);\n\n\tif (!ixgbe_mng_present(hw) && !hw->wol_enabled &&\n\t ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {\n\t\tautoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);\n\t\tautoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);\n\t}\n}\n\n/**\n * ixgbe_start_mac_link_82599 - Setup MAC link settings\n * @hw: pointer to hardware structure\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Configures link settings based on values in the ixgbe_hw struct.\n * Restarts the link. Performs autonegotiation if needed.\n **/\ns32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,\n\t\t\t bool autoneg_wait_to_complete)\n{\n\tu32 autoc_reg;\n\tu32 links_reg;\n\tu32 i;\n\ts32 status = IXGBE_SUCCESS;\n\tbool got_lock = false;\n\n\tDEBUGFUNC(\"ixgbe_start_mac_link_82599\");\n\n\n\t/* reset_pipeline requires us to hold this lock as it writes to\n\t * AUTOC.\n\t */\n\tif (ixgbe_verify_lesm_fw_enabled_82599(hw)) {\n\t\tstatus = hw->mac.ops.acquire_swfw_sync(hw,\n\t\t\t\t\t\t IXGBE_GSSR_MAC_CSR_SM);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto out;\n\n\t\tgot_lock = true;\n\t}\n\n\t/* Restart link */\n\tixgbe_reset_pipeline_82599(hw);\n\n\tif (got_lock)\n\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);\n\n\t/* Only poll for autoneg to complete if specified to do so */\n\tif (autoneg_wait_to_complete) {\n\t\tautoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\t\tif ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==\n\t\t IXGBE_AUTOC_LMS_KX4_KX_KR ||\n\t\t (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==\n\t\t IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||\n\t\t (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==\n\t\t IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {\n\t\t\tlinks_reg = 0; /* Just in case Autoneg time = 0 */\n\t\t\tfor (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {\n\t\t\t\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\t\t\t\tif (links_reg & IXGBE_LINKS_KX_AN_COMP)\n\t\t\t\t\tbreak;\n\t\t\t\tmsec_delay(100);\n\t\t\t}\n\t\t\tif (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {\n\t\t\t\tstatus = IXGBE_ERR_AUTONEG_NOT_COMPLETE;\n\t\t\t\tDEBUGOUT(\"Autoneg did not complete.\\n\");\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Add delay to filter out noises during initial link setup */\n\tmsec_delay(50);\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser\n * @hw: pointer to hardware structure\n *\n * The base drivers may require better control over SFP+ module\n * PHY states. This includes selectively shutting down the Tx\n * laser on the PHY, effectively halting physical link.\n **/\nvoid ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n{\n\tu32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\n\t/* Blocked by MNG FW so bail */\n\tif (ixgbe_check_reset_blocked(hw))\n\t\treturn;\n\n\t/* Disable Tx laser; allow 100us to go dark per spec */\n\tesdp_reg |= IXGBE_ESDP_SDP3;\n\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\tusec_delay(100);\n}\n\n/**\n * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser\n * @hw: pointer to hardware structure\n *\n * The base drivers may require better control over SFP+ module\n * PHY states. This includes selectively turning on the Tx\n * laser on the PHY, effectively starting physical link.\n **/\nvoid ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n{\n\tu32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\n\t/* Enable Tx laser; allow 100ms to light up */\n\tesdp_reg &= ~IXGBE_ESDP_SDP3;\n\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\tmsec_delay(100);\n}\n\n/**\n * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser\n * @hw: pointer to hardware structure\n *\n * When the driver changes the link speeds that it can support,\n * it sets autotry_restart to true to indicate that we need to\n * initiate a new autotry session with the link partner. To do\n * so, we set the speed then disable and re-enable the Tx laser, to\n * alert the link partner that it also needs to restart autotry on its\n * end. This is consistent with true clause 37 autoneg, which also\n * involves a loss of signal.\n **/\nvoid ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n{\n\tDEBUGFUNC(\"ixgbe_flap_tx_laser_multispeed_fiber\");\n\n\t/* Blocked by MNG FW so bail */\n\tif (ixgbe_check_reset_blocked(hw))\n\t\treturn;\n\n\tif (hw->mac.autotry_restart) {\n\t\tixgbe_disable_tx_laser_multispeed_fiber(hw);\n\t\tixgbe_enable_tx_laser_multispeed_fiber(hw);\n\t\thw->mac.autotry_restart = false;\n\t}\n}\n\n/**\n * ixgbe_set_hard_rate_select_speed - Set module link speed\n * @hw: pointer to hardware structure\n * @speed: link speed to set\n *\n * Set module link speed via RS0/RS1 rate select pins.\n */\nvoid ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,\n\t\t\t\t\tixgbe_link_speed speed)\n{\n\tu32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\n\tswitch (speed) {\n\tcase IXGBE_LINK_SPEED_10GB_FULL:\n\t\tesdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);\n\t\tbreak;\n\tcase IXGBE_LINK_SPEED_1GB_FULL:\n\t\tesdp_reg &= ~IXGBE_ESDP_SDP5;\n\t\tesdp_reg |= IXGBE_ESDP_SDP5_DIR;\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\"Invalid fixed module speed\\n\");\n\t\treturn;\n\t}\n\n\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/**\n * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Implements the Intel SmartSpeed algorithm.\n **/\ns32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg_wait_to_complete)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;\n\ts32 i, j;\n\tbool link_up = false;\n\tu32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\n\tDEBUGFUNC(\"ixgbe_setup_mac_link_smartspeed\");\n\n\t /* Set autoneg_advertised value based on input link speed */\n\thw->phy.autoneg_advertised = 0;\n\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_100_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;\n\n\t/*\n\t * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the\n\t * autoneg advertisement if link is unable to be established at the\n\t * highest negotiated rate. This can sometimes happen due to integrity\n\t * issues with the physical media connection.\n\t */\n\n\t/* First, try to get link with full advertisement */\n\thw->phy.smart_speed_active = false;\n\tfor (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {\n\t\tstatus = ixgbe_setup_mac_link_82599(hw, speed,\n\t\t\t\t\t\t autoneg_wait_to_complete);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto out;\n\n\t\t/*\n\t\t * Wait for the controller to acquire link. Per IEEE 802.3ap,\n\t\t * Section 73.10.2, we may have to wait up to 500ms if KR is\n\t\t * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per\n\t\t * Table 9 in the AN MAS.\n\t\t */\n\t\tfor (i = 0; i < 5; i++) {\n\t\t\tmsec_delay(100);\n\n\t\t\t/* If we have link, just jump out */\n\t\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up,\n\t\t\t\t\t\t false);\n\t\t\tif (status != IXGBE_SUCCESS)\n\t\t\t\tgoto out;\n\n\t\t\tif (link_up)\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\n\t/*\n\t * We didn't get link. If we advertised KR plus one of KX4/KX\n\t * (or BX4/BX), then disable KR and try again.\n\t */\n\tif (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||\n\t ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))\n\t\tgoto out;\n\n\t/* Turn SmartSpeed on to disable KR support */\n\thw->phy.smart_speed_active = true;\n\tstatus = ixgbe_setup_mac_link_82599(hw, speed,\n\t\t\t\t\t autoneg_wait_to_complete);\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\t/*\n\t * Wait for the controller to acquire link. 600ms will allow for\n\t * the AN link_fail_inhibit_timer as well for multiple cycles of\n\t * parallel detect, both 10g and 1g. This allows for the maximum\n\t * connect attempts as defined in the AN MAS table 73-7.\n\t */\n\tfor (i = 0; i < 6; i++) {\n\t\tmsec_delay(100);\n\n\t\t/* If we have link, just jump out */\n\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up, false);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto out;\n\n\t\tif (link_up)\n\t\t\tgoto out;\n\t}\n\n\t/* We didn't get link. Turn SmartSpeed back off. */\n\thw->phy.smart_speed_active = false;\n\tstatus = ixgbe_setup_mac_link_82599(hw, speed,\n\t\t\t\t\t autoneg_wait_to_complete);\n\nout:\n\tif (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))\n\t\tDEBUGOUT(\"Smartspeed has downgraded the link speed \"\n\t\t\"from the maximum advertised\\n\");\n\treturn status;\n}\n\n/**\n * ixgbe_setup_mac_link_82599 - Set MAC link speed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Set the link speed in the AUTOC register and restarts link.\n **/\ns32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,\n\t\t\t ixgbe_link_speed speed,\n\t\t\t bool autoneg_wait_to_complete)\n{\n\tbool autoneg = false;\n\ts32 status = IXGBE_SUCCESS;\n\tu32 pma_pmd_1g, link_mode;\n\tu32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */\n\tu32 orig_autoc = 0; /* holds the cached value of AUTOC register */\n\tu32 autoc = current_autoc; /* Temporary variable used for comparison purposes */\n\tu32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);\n\tu32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;\n\tu32 links_reg;\n\tu32 i;\n\tixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;\n\n\tDEBUGFUNC(\"ixgbe_setup_mac_link_82599\");\n\n\t/* Check to see if speed passed in is supported. */\n\tstatus = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);\n\tif (status)\n\t\tgoto out;\n\n\tspeed &= link_capabilities;\n\n\tif (speed == IXGBE_LINK_SPEED_UNKNOWN) {\n\t\tstatus = IXGBE_ERR_LINK_SETUP;\n\t\tgoto out;\n\t}\n\n\t/* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/\n\tif (hw->mac.orig_link_settings_stored)\n\t\torig_autoc = hw->mac.orig_autoc;\n\telse\n\t\torig_autoc = autoc;\n\n\tlink_mode = autoc & IXGBE_AUTOC_LMS_MASK;\n\tpma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;\n\n\tif (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||\n\t link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||\n\t link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {\n\t\t/* Set KX4/KX/KR support according to speed requested */\n\t\tautoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);\n\t\tif (speed & IXGBE_LINK_SPEED_10GB_FULL) {\n\t\t\tif (orig_autoc & IXGBE_AUTOC_KX4_SUPP)\n\t\t\t\tautoc |= IXGBE_AUTOC_KX4_SUPP;\n\t\t\tif ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&\n\t\t\t (hw->phy.smart_speed_active == false))\n\t\t\t\tautoc |= IXGBE_AUTOC_KR_SUPP;\n\t\t}\n\t\tif (speed & IXGBE_LINK_SPEED_1GB_FULL)\n\t\t\tautoc |= IXGBE_AUTOC_KX_SUPP;\n\t} else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&\n\t\t (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||\n\t\t link_mode == IXGBE_AUTOC_LMS_1G_AN)) {\n\t\t/* Switch from 1G SFI to 10G SFI if requested */\n\t\tif ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&\n\t\t (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {\n\t\t\tautoc &= ~IXGBE_AUTOC_LMS_MASK;\n\t\t\tautoc |= IXGBE_AUTOC_LMS_10G_SERIAL;\n\t\t}\n\t} else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&\n\t\t (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {\n\t\t/* Switch from 10G SFI to 1G SFI if requested */\n\t\tif ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&\n\t\t (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {\n\t\t\tautoc &= ~IXGBE_AUTOC_LMS_MASK;\n\t\t\tif (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)\n\t\t\t\tautoc |= IXGBE_AUTOC_LMS_1G_AN;\n\t\t\telse\n\t\t\t\tautoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;\n\t\t}\n\t}\n\n\tif (autoc != current_autoc) {\n\t\t/* Restart link */\n\t\tstatus = hw->mac.ops.prot_autoc_write(hw, autoc, false);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto out;\n\n\t\t/* Only poll for autoneg to complete if specified to do so */\n\t\tif (autoneg_wait_to_complete) {\n\t\t\tif (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||\n\t\t\t link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||\n\t\t\t link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {\n\t\t\t\tlinks_reg = 0; /*Just in case Autoneg time=0*/\n\t\t\t\tfor (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {\n\t\t\t\t\tlinks_reg =\n\t\t\t\t\t IXGBE_READ_REG(hw, IXGBE_LINKS);\n\t\t\t\t\tif (links_reg & IXGBE_LINKS_KX_AN_COMP)\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tmsec_delay(100);\n\t\t\t\t}\n\t\t\t\tif (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {\n\t\t\t\t\tstatus =\n\t\t\t\t\t\tIXGBE_ERR_AUTONEG_NOT_COMPLETE;\n\t\t\t\t\tDEBUGOUT(\"Autoneg did not complete.\\n\");\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* Add delay to filter out noises during initial link setup */\n\t\tmsec_delay(50);\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg_wait_to_complete: true if waiting is needed to complete\n *\n * Restarts link on PHY and MAC based on settings passed in.\n **/\nSTATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t\t bool autoneg_wait_to_complete)\n{\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_setup_copper_link_82599\");\n\n\t/* Setup the PHY according to input speed */\n\tstatus = hw->phy.ops.setup_link_speed(hw, speed,\n\t\t\t\t\t autoneg_wait_to_complete);\n\t/* Set up MAC */\n\tixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);\n\n\treturn status;\n}\n\n/**\n * ixgbe_reset_hw_82599 - Perform hardware reset\n * @hw: pointer to hardware structure\n *\n * Resets the hardware by resetting the transmit and receive units, masks\n * and clears all interrupts, perform a PHY reset, and perform a link (MAC)\n * reset.\n **/\ns32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)\n{\n\tixgbe_link_speed link_speed;\n\ts32 status;\n\tu32 ctrl = 0;\n\tu32 i, autoc, autoc2;\n\tu32 curr_lms;\n\tbool link_up = false;\n\n\tDEBUGFUNC(\"ixgbe_reset_hw_82599\");\n\n\t/* Call adapter stop to disable tx/rx and clear interrupts */\n\tstatus = hw->mac.ops.stop_adapter(hw);\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto reset_hw_out;\n\n\t/* flush pending Tx transactions */\n\tixgbe_clear_tx_pending(hw);\n\n\t/* PHY ops must be identified and initialized prior to reset */\n\n\t/* Identify PHY and related function pointers */\n\tstatus = hw->phy.ops.init(hw);\n\n\tif (status == IXGBE_ERR_SFP_NOT_SUPPORTED)\n\t\tgoto reset_hw_out;\n\n\t/* Setup SFP module if there is one present. */\n\tif (hw->phy.sfp_setup_needed) {\n\t\tstatus = hw->mac.ops.setup_sfp(hw);\n\t\thw->phy.sfp_setup_needed = false;\n\t}\n\n\tif (status == IXGBE_ERR_SFP_NOT_SUPPORTED)\n\t\tgoto reset_hw_out;\n\n\t/* Reset PHY */\n\tif (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)\n\t\thw->phy.ops.reset(hw);\n\n\t/* remember AUTOC from before we reset */\n\tcurr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;\n\nmac_reset_top:\n\t/*\n\t * Issue global reset to the MAC. Needs to be SW reset if link is up.\n\t * If link reset is used when link is up, it might reset the PHY when\n\t * mng is using it. If link is down or the flag to force full link\n\t * reset is set, then perform link reset.\n\t */\n\tctrl = IXGBE_CTRL_LNK_RST;\n\tif (!hw->force_full_reset) {\n\t\thw->mac.ops.check_link(hw, &link_speed, &link_up, false);\n\t\tif (link_up)\n\t\t\tctrl = IXGBE_CTRL_RST;\n\t}\n\n\tctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Poll for reset bit to self-clear meaning reset is complete */\n\tfor (i = 0; i < 10; i++) {\n\t\tusec_delay(1);\n\t\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);\n\t\tif (!(ctrl & IXGBE_CTRL_RST_MASK))\n\t\t\tbreak;\n\t}\n\n\tif (ctrl & IXGBE_CTRL_RST_MASK) {\n\t\tstatus = IXGBE_ERR_RESET_FAILED;\n\t\tDEBUGOUT(\"Reset polling failed to complete.\\n\");\n\t}\n\n\tmsec_delay(50);\n\n\t/*\n\t * Double resets are required for recovery from certain error\n\t * conditions. Between resets, it is necessary to stall to\n\t * allow time for any pending HW events to complete.\n\t */\n\tif (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {\n\t\thw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;\n\t\tgoto mac_reset_top;\n\t}\n\n\t/*\n\t * Store the original AUTOC/AUTOC2 values if they have not been\n\t * stored off yet. Otherwise restore the stored original\n\t * values since the reset operation sets back to defaults.\n\t */\n\tautoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tautoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);\n\n\t/* Enable link if disabled in NVM */\n\tif (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {\n\t\tautoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t}\n\n\tif (hw->mac.orig_link_settings_stored == false) {\n\t\thw->mac.orig_autoc = autoc;\n\t\thw->mac.orig_autoc2 = autoc2;\n\t\thw->mac.orig_link_settings_stored = true;\n\t} else {\n\n\t\t/* If MNG FW is running on a multi-speed device that\n\t\t * doesn't autoneg with out driver support we need to\n\t\t * leave LMS in the state it was before we MAC reset.\n\t\t * Likewise if we support WoL we don't want change the\n\t\t * LMS state.\n\t\t */\n\t\tif ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||\n\t\t hw->wol_enabled)\n\t\t\thw->mac.orig_autoc =\n\t\t\t\t(hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |\n\t\t\t\tcurr_lms;\n\n\t\tif (autoc != hw->mac.orig_autoc) {\n\t\t\tstatus = hw->mac.ops.prot_autoc_write(hw,\n\t\t\t\t\t\t\thw->mac.orig_autoc,\n\t\t\t\t\t\t\tfalse);\n\t\t\tif (status != IXGBE_SUCCESS)\n\t\t\t\tgoto reset_hw_out;\n\t\t}\n\n\t\tif ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=\n\t\t (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {\n\t\t\tautoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;\n\t\t\tautoc2 |= (hw->mac.orig_autoc2 &\n\t\t\t\t IXGBE_AUTOC2_UPPER_MASK);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);\n\t\t}\n\t}\n\n\t/* Store the permanent mac address */\n\thw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);\n\n\t/*\n\t * Store MAC address from RAR0, clear receive address registers, and\n\t * clear the multicast table. Also reset num_rar_entries to 128,\n\t * since we modify this value when programming the SAN MAC address.\n\t */\n\thw->mac.num_rar_entries = 128;\n\thw->mac.ops.init_rx_addrs(hw);\n\n\t/* Store the permanent SAN mac address */\n\thw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);\n\n\t/* Add the SAN MAC address to the RAR only if it's a valid address */\n\tif (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {\n\t\thw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,\n\t\t\t\t hw->mac.san_addr, 0, IXGBE_RAH_AV);\n\n\t\t/* Save the SAN MAC RAR index */\n\t\thw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;\n\n\t\t/* Reserve the last RAR for the SAN MAC address */\n\t\thw->mac.num_rar_entries--;\n\t}\n\n\t/* Store the alternative WWNN/WWPN prefix */\n\thw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,\n\t\t\t\t &hw->mac.wwpn_prefix);\n\nreset_hw_out:\n\treturn status;\n}\n\n/**\n * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete\n * @hw: pointer to hardware structure\n * @fdircmd: current value of FDIRCMD register\n */\nSTATIC s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd)\n{\n\tint i;\n\n\tfor (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {\n\t\t*fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);\n\t\tif (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))\n\t\t\treturn IXGBE_SUCCESS;\n\t\tusec_delay(10);\n\t}\n\n\treturn IXGBE_ERR_FDIR_CMD_INCOMPLETE;\n}\n\n/**\n * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)\n{\n\ts32 err;\n\tint i;\n\tu32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);\n\tu32 fdircmd;\n\tfdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;\n\n\tDEBUGFUNC(\"ixgbe_reinit_fdir_tables_82599\");\n\n\t/*\n\t * Before starting reinitialization process,\n\t * FDIRCMD.CMD must be zero.\n\t */\n\terr = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);\n\tif (err) {\n\t\tDEBUGOUT(\"Flow Director previous command did not complete, aborting table re-initialization.\\n\");\n\t\treturn err;\n\t}\n\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);\n\tIXGBE_WRITE_FLUSH(hw);\n\t/*\n\t * 82599 adapters flow director init flow cannot be restarted,\n\t * Workaround 82599 silicon errata by performing the following steps\n\t * before re-writing the FDIRCTRL control register with the same value.\n\t * - write 1 to bit 8 of FDIRCMD register &\n\t * - write 0 to bit 8 of FDIRCMD register\n\t */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,\n\t\t\t(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |\n\t\t\t IXGBE_FDIRCMD_CLEARHT));\n\tIXGBE_WRITE_FLUSH(hw);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,\n\t\t\t(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &\n\t\t\t ~IXGBE_FDIRCMD_CLEARHT));\n\tIXGBE_WRITE_FLUSH(hw);\n\t/*\n\t * Clear FDIR Hash register to clear any leftover hashes\n\t * waiting to be programmed.\n\t */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Poll init-done after we write FDIRCTRL register */\n\tfor (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {\n\t\tif (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &\n\t\t\t\t IXGBE_FDIRCTRL_INIT_DONE)\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t}\n\tif (i >= IXGBE_FDIR_INIT_DONE_POLL) {\n\t\tDEBUGOUT(\"Flow Director Signature poll time exceeded!\\n\");\n\t\treturn IXGBE_ERR_FDIR_REINIT_FAILED;\n\t}\n\n\t/* Clear FDIR statistics registers (read to clear) */\n\tIXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);\n\tIXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);\n\tIXGBE_READ_REG(hw, IXGBE_FDIRMATCH);\n\tIXGBE_READ_REG(hw, IXGBE_FDIRMISS);\n\tIXGBE_READ_REG(hw, IXGBE_FDIRLEN);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers\n * @hw: pointer to hardware structure\n * @fdirctrl: value to write to flow director control register\n **/\nSTATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)\n{\n\tint i;\n\n\tDEBUGFUNC(\"ixgbe_fdir_enable_82599\");\n\n\t/* Prime the keys for hashing */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);\n\n\t/*\n\t * Poll init-done after we write the register. Estimated times:\n\t * 10G: PBALLOC = 11b, timing is 60us\n\t * 1G: PBALLOC = 11b, timing is 600us\n\t * 100M: PBALLOC = 11b, timing is 6ms\n\t *\n\t * Multiple these timings by 4 if under full Rx load\n\t *\n\t * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for\n\t * 1 msec per poll time. If we're at line rate and drop to 100M, then\n\t * this might not finish in our poll time, but we can live with that\n\t * for now.\n\t */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);\n\tIXGBE_WRITE_FLUSH(hw);\n\tfor (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {\n\t\tif (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &\n\t\t\t\t IXGBE_FDIRCTRL_INIT_DONE)\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t}\n\n\tif (i >= IXGBE_FDIR_INIT_DONE_POLL)\n\t\tDEBUGOUT(\"Flow Director poll time exceeded!\\n\");\n}\n\n/**\n * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters\n * @hw: pointer to hardware structure\n * @fdirctrl: value to write to flow director control register, initially\n *\t contains just the value of the Rx packet buffer allocation\n **/\ns32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)\n{\n\tDEBUGFUNC(\"ixgbe_init_fdir_signature_82599\");\n\n\t/*\n\t * Continue setup of fdirctrl register bits:\n\t * Move the flexible bytes to use the ethertype - shift 6 words\n\t * Set the maximum length per hash bucket to 0xA filters\n\t * Send interrupt when 64 filters are left\n\t */\n\tfdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |\n\t\t (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |\n\t\t (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);\n\n\t/* write hashes and fdirctrl register, poll for completion */\n\tixgbe_fdir_enable_82599(hw, fdirctrl);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters\n * @hw: pointer to hardware structure\n * @fdirctrl: value to write to flow director control register, initially\n *\t contains just the value of the Rx packet buffer allocation\n * @cloud_mode: true - cloud mode, false - other mode\n **/\ns32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,\n\t\t\tbool cloud_mode)\n{\n\tDEBUGFUNC(\"ixgbe_init_fdir_perfect_82599\");\n\n\t/*\n\t * Continue setup of fdirctrl register bits:\n\t * Turn perfect match filtering on\n\t * Report hash in RSS field of Rx wb descriptor\n\t * Initialize the drop queue\n\t * Move the flexible bytes to use the ethertype - shift 6 words\n\t * Set the maximum length per hash bucket to 0xA filters\n\t * Send interrupt when 64 (0x4 * 16) filters are left\n\t */\n\tfdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |\n\t\t IXGBE_FDIRCTRL_REPORT_STATUS |\n\t\t (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |\n\t\t (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |\n\t\t (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |\n\t\t (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);\n\n\tif (cloud_mode)\n\t\tfdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<\n\t\t\t\t\tIXGBE_FDIRCTRL_FILTERMODE_SHIFT);\n\n\t/* write hashes and fdirctrl register, poll for completion */\n\tixgbe_fdir_enable_82599(hw, fdirctrl);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/*\n * These defines allow us to quickly generate all of the necessary instructions\n * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION\n * for values 0 through 15\n */\n#define IXGBE_ATR_COMMON_HASH_KEY \\\n\t\t(IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)\n#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \\\ndo { \\\n\tu32 n = (_n); \\\n\tif (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \\\n\t\tcommon_hash ^= lo_hash_dword >> n; \\\n\telse if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \\\n\t\tbucket_hash ^= lo_hash_dword >> n; \\\n\telse if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \\\n\t\tsig_hash ^= lo_hash_dword << (16 - n); \\\n\tif (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \\\n\t\tcommon_hash ^= hi_hash_dword >> n; \\\n\telse if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \\\n\t\tbucket_hash ^= hi_hash_dword >> n; \\\n\telse if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \\\n\t\tsig_hash ^= hi_hash_dword << (16 - n); \\\n} while (0)\n\n/**\n * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash\n * @stream: input bitstream to compute the hash on\n *\n * This function is almost identical to the function above but contains\n * several optimizations such as unwinding all of the loops, letting the\n * compiler work out all of the conditional ifs since the keys are static\n * defines, and computing two keys at once since the hashed dword stream\n * will be the same for both keys.\n **/\nu32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,\n\t\t\t\t union ixgbe_atr_hash_dword common)\n{\n\tu32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;\n\tu32 sig_hash = 0, bucket_hash = 0, common_hash = 0;\n\n\t/* record the flow_vm_vlan bits as they are a key part to the hash */\n\tflow_vm_vlan = IXGBE_NTOHL(input.dword);\n\n\t/* generate common hash dword */\n\thi_hash_dword = IXGBE_NTOHL(common.dword);\n\n\t/* low dword is word swapped version of common */\n\tlo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);\n\n\t/* apply flow ID/VM pool/VLAN ID bits to hash words */\n\thi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);\n\n\t/* Process bits 0 and 16 */\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(0);\n\n\t/*\n\t * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to\n\t * delay this because bit 0 of the stream should not be processed\n\t * so we do not add the VLAN until after bit 0 was processed\n\t */\n\tlo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);\n\n\t/* Process remaining 30 bit of the key */\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(1);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(2);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(3);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(4);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(5);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(6);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(7);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(8);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(9);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(10);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(11);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(12);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(13);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(14);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(15);\n\n\t/* combine common_hash result with signature and bucket hashes */\n\tbucket_hash ^= common_hash;\n\tbucket_hash &= IXGBE_ATR_HASH_MASK;\n\n\tsig_hash ^= common_hash << 16;\n\tsig_hash &= IXGBE_ATR_HASH_MASK << 16;\n\n\t/* return completed signature hash */\n\treturn sig_hash ^ bucket_hash;\n}\n\n/**\n * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter\n * @hw: pointer to hardware structure\n * @input: unique input dword\n * @common: compressed common input dword\n * @queue: queue index to direct traffic to\n *\n * Note that the tunnel bit in input must not be set when the hardware\n * tunneling support does not exist.\n **/\ns32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t union ixgbe_atr_hash_dword input,\n\t\t\t\t\t union ixgbe_atr_hash_dword common,\n\t\t\t\t\t u8 queue)\n{\n\tu64 fdirhashcmd;\n\tu8 flow_type;\n\tbool tunnel;\n\tu32 fdircmd;\n\ts32 err;\n\n\tDEBUGFUNC(\"ixgbe_fdir_add_signature_filter_82599\");\n\n\t/*\n\t * Get the flow_type in order to program FDIRCMD properly\n\t * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6\n\t * fifth is FDIRCMD.TUNNEL_FILTER\n\t */\n\ttunnel = !!(input.formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK);\n\tflow_type = input.formatted.flow_type &\n\t\t (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1);\n\tswitch (flow_type) {\n\tcase IXGBE_ATR_FLOW_TYPE_TCPV4:\n\tcase IXGBE_ATR_FLOW_TYPE_UDPV4:\n\tcase IXGBE_ATR_FLOW_TYPE_SCTPV4:\n\tcase IXGBE_ATR_FLOW_TYPE_TCPV6:\n\tcase IXGBE_ATR_FLOW_TYPE_UDPV6:\n\tcase IXGBE_ATR_FLOW_TYPE_SCTPV6:\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\" Error on flow type input\\n\");\n\t\treturn IXGBE_ERR_CONFIG;\n\t}\n\n\t/* configure FDIRCMD register */\n\tfdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |\n\t\t IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;\n\tfdircmd |= (u32)flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;\n\tfdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;\n\tif (tunnel)\n\t\tfdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;\n\n\t/*\n\t * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits\n\t * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.\n\t */\n\tfdirhashcmd = (u64)fdircmd << 32;\n\tfdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);\n\tIXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);\n\n\terr = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);\n\tif (err) {\n\t\tDEBUGOUT(\"Flow Director command did not complete!\\n\");\n\t\treturn err;\n\t}\n\n\tDEBUGOUT2(\"Tx Queue=%x hash=%x\\n\", queue, (u32)fdirhashcmd);\n\n\treturn IXGBE_SUCCESS;\n}\n\n#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \\\ndo { \\\n\tu32 n = (_n); \\\n\tif (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \\\n\t\tbucket_hash ^= lo_hash_dword >> n; \\\n\tif (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \\\n\t\tbucket_hash ^= hi_hash_dword >> n; \\\n} while (0)\n\n/**\n * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash\n * @atr_input: input bitstream to compute the hash on\n * @input_mask: mask for the input bitstream\n *\n * This function serves two main purposes. First it applies the input_mask\n * to the atr_input resulting in a cleaned up atr_input data stream.\n * Secondly it computes the hash and stores it in the bkt_hash field at\n * the end of the input byte stream. This way it will be available for\n * future use without needing to recompute the hash.\n **/\nvoid ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,\n\t\t\t\t\t union ixgbe_atr_input *input_mask)\n{\n\n\tu32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;\n\tu32 bucket_hash = 0;\n\tu32 hi_dword = 0;\n\tu32 i = 0;\n\n\t/* Apply masks to input data */\n\tfor (i = 0; i < 14; i++)\n\t\tinput->dword_stream[i] &= input_mask->dword_stream[i];\n\n\t/* record the flow_vm_vlan bits as they are a key part to the hash */\n\tflow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);\n\n\t/* generate common hash dword */\n\tfor (i = 1; i <= 13; i++)\n\t\thi_dword ^= input->dword_stream[i];\n\thi_hash_dword = IXGBE_NTOHL(hi_dword);\n\n\t/* low dword is word swapped version of common */\n\tlo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);\n\n\t/* apply flow ID/VM pool/VLAN ID bits to hash words */\n\thi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);\n\n\t/* Process bits 0 and 16 */\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(0);\n\n\t/*\n\t * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to\n\t * delay this because bit 0 of the stream should not be processed\n\t * so we do not add the VLAN until after bit 0 was processed\n\t */\n\tlo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);\n\n\t/* Process remaining 30 bit of the key */\n\tfor (i = 1; i <= 15; i++)\n\t\tIXGBE_COMPUTE_BKT_HASH_ITERATION(i);\n\n\t/*\n\t * Limit hash to 13 bits since max bucket count is 8K.\n\t * Store result at the end of the input stream.\n\t */\n\tinput->formatted.bkt_hash = bucket_hash & 0x1FFF;\n}\n\n/**\n * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks\n * @input_mask: mask to be bit swapped\n *\n * The source and destination port masks for flow director are bit swapped\n * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to\n * generate a correctly swapped value we need to bit swap the mask and that\n * is what is accomplished by this function.\n **/\nSTATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)\n{\n\tu32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);\n\tmask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;\n\tmask |= IXGBE_NTOHS(input_mask->formatted.src_port);\n\tmask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);\n\tmask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);\n\tmask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);\n\treturn ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);\n}\n\n/*\n * These two macros are meant to address the fact that we have registers\n * that are either all or in part big-endian. As a result on big-endian\n * systems we will end up byte swapping the value to little-endian before\n * it is byte swapped again and written to the hardware in the original\n * big-endian format.\n */\n#define IXGBE_STORE_AS_BE32(_value) \\\n\t(((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \\\n\t (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))\n\n#define IXGBE_WRITE_REG_BE32(a, reg, value) \\\n\tIXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))\n\n#define IXGBE_STORE_AS_BE16(_value) \\\n\tIXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))\n\ns32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,\n\t\t\t\t union ixgbe_atr_input *input_mask, bool cloud_mode)\n{\n\t/* mask IPv6 since it is currently not supported */\n\tu32 fdirm = IXGBE_FDIRM_DIPv6;\n\tu32 fdirtcpm;\n\tu32 fdirip6m;\n\tDEBUGFUNC(\"ixgbe_fdir_set_atr_input_mask_82599\");\n\n\t/*\n\t * Program the relevant mask registers. If src/dst_port or src/dst_addr\n\t * are zero, then assume a full mask for that field. Also assume that\n\t * a VLAN of 0 is unspecified, so mask that out as well. L4type\n\t * cannot be masked out in this implementation.\n\t *\n\t * This also assumes IPv4 only. IPv6 masking isn't supported at this\n\t * point in time.\n\t */\n\n\t/* verify bucket hash is cleared on hash generation */\n\tif (input_mask->formatted.bkt_hash)\n\t\tDEBUGOUT(\" bucket hash should always be 0 in mask\\n\");\n\n\t/* Program FDIRM and verify partial masks */\n\tswitch (input_mask->formatted.vm_pool & 0x7F) {\n\tcase 0x0:\n\t\tfdirm |= IXGBE_FDIRM_POOL;\n\tcase 0x7F:\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\" Error on vm pool mask\\n\");\n\t\treturn IXGBE_ERR_CONFIG;\n\t}\n\n\tswitch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {\n\tcase 0x0:\n\t\tfdirm |= IXGBE_FDIRM_L4P;\n\t\tif (input_mask->formatted.dst_port ||\n\t\t input_mask->formatted.src_port) {\n\t\t\tDEBUGOUT(\" Error on src/dst port mask\\n\");\n\t\t\treturn IXGBE_ERR_CONFIG;\n\t\t}\n\tcase IXGBE_ATR_L4TYPE_MASK:\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\" Error on flow type mask\\n\");\n\t\treturn IXGBE_ERR_CONFIG;\n\t}\n\n\tswitch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {\n\tcase 0x0000:\n\t\t/* mask VLAN ID, fall through to mask VLAN priority */\n\t\tfdirm |= IXGBE_FDIRM_VLANID;\n\tcase 0x0FFF:\n\t\t/* mask VLAN priority */\n\t\tfdirm |= IXGBE_FDIRM_VLANP;\n\t\tbreak;\n\tcase 0xE000:\n\t\t/* mask VLAN ID only, fall through */\n\t\tfdirm |= IXGBE_FDIRM_VLANID;\n\tcase 0xEFFF:\n\t\t/* no VLAN fields masked */\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\" Error on VLAN mask\\n\");\n\t\treturn IXGBE_ERR_CONFIG;\n\t}\n\n\tswitch (input_mask->formatted.flex_bytes & 0xFFFF) {\n\tcase 0x0000:\n\t\t/* Mask Flex Bytes, fall through */\n\t\tfdirm |= IXGBE_FDIRM_FLEX;\n\tcase 0xFFFF:\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\" Error on flexible byte mask\\n\");\n\t\treturn IXGBE_ERR_CONFIG;\n\t}\n\n\tif (cloud_mode) {\n\t\tfdirm |= IXGBE_FDIRM_L3P;\n\t\tfdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);\n\t\tfdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;\n\n\t\tswitch (input_mask->formatted.inner_mac[0] & 0xFF) {\n\t\tcase 0x00:\n\t\t\t/* Mask inner MAC, fall through */\n\t\t\tfdirip6m |= IXGBE_FDIRIP6M_INNER_MAC;\n\t\tcase 0xFF:\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tDEBUGOUT(\" Error on inner_mac byte mask\\n\");\n\t\t\treturn IXGBE_ERR_CONFIG;\n\t\t}\n\n\t\tswitch (input_mask->formatted.tni_vni & 0xFFFFFFFF) {\n\t\tcase 0x0:\n\t\t\t/* Mask vxlan id */\n\t\t\tfdirip6m |= IXGBE_FDIRIP6M_TNI_VNI;\n\t\t\tbreak;\n\t\tcase 0x00FFFFFF:\n\t\t\tfdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24;\n\t\t\tbreak;\n\t\tcase 0xFFFFFFFF:\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tDEBUGOUT(\" Error on TNI/VNI byte mask\\n\");\n\t\t\treturn IXGBE_ERR_CONFIG;\n\t\t}\n\n\t\tswitch (input_mask->formatted.tunnel_type & 0xFFFF) {\n\t\tcase 0x0:\n\t\t\t/* Mask turnnel type, fall through */\n\t\t\tfdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;\n\t\tcase 0xFFFF:\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tDEBUGOUT(\" Error on tunnel type byte mask\\n\");\n\t\t\treturn IXGBE_ERR_CONFIG;\n\t\t}\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);\n\n\t\t/* Set all bits in FDIRTCPM, FDIRUDPM, FDIRSIP4M and\n\t\t * FDIRDIP4M in cloud mode to allow L3/L3 packets to\n\t\t * tunnel.\n\t\t */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);\n\t}\n\n\t/* Now mask VM pool and destination IPv6 - bits 5 and 2 */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);\n\n\tif (!cloud_mode) {\n\t\t/* store the TCP/UDP port masks, bit reversed from port\n\t\t * layout */\n\t\tfdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);\n\n\t\t/* write both the same so that UDP and TCP use the same mask */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);\n\t\t/* also use it for SCTP */\n\t\tswitch (hw->mac.type) {\n\t\tcase ixgbe_mac_X550:\n\t\tcase ixgbe_mac_X550EM_x:\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\t/* store source and destination IP masks (big-enian) */\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,\n\t\t\t\t ~input_mask->formatted.src_ip[0]);\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,\n\t\t\t\t ~input_mask->formatted.dst_ip[0]);\n\t}\n\treturn IXGBE_SUCCESS;\n}\n\ns32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t union ixgbe_atr_input *input,\n\t\t\t\t\t u16 soft_id, u8 queue, bool cloud_mode)\n{\n\tu32 fdirport, fdirvlan, fdirhash, fdircmd;\n\tu32 addr_low, addr_high;\n\tu32 cloud_type = 0;\n\ts32 err;\n\n\tDEBUGFUNC(\"ixgbe_fdir_write_perfect_filter_82599\");\n\tif (!cloud_mode) {\n\t\t/* currently IPv6 is not supported, must be programmed with 0 */\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),\n\t\t\t\t input->formatted.src_ip[0]);\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),\n\t\t\t\t input->formatted.src_ip[1]);\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),\n\t\t\t\t input->formatted.src_ip[2]);\n\n\t\t/* record the source address (big-endian) */\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA,\n\t\t\tinput->formatted.src_ip[0]);\n\n\t\t/* record the first 32 bits of the destination address\n\t\t * (big-endian) */\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA,\n\t\t\tinput->formatted.dst_ip[0]);\n\n\t\t/* record source and destination port (little-endian)*/\n\t\tfdirport = IXGBE_NTOHS(input->formatted.dst_port);\n\t\tfdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;\n\t\tfdirport |= IXGBE_NTOHS(input->formatted.src_port);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);\n\t}\n\n\t/* record VLAN (little-endian) and flex_bytes(big-endian) */\n\tfdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);\n\tfdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;\n\tfdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);\n\n\tif (cloud_mode) {\n\t\tif (input->formatted.tunnel_type != 0)\n\t\t\tcloud_type = 0x80000000;\n\n\t\taddr_low = ((u32)input->formatted.inner_mac[0] |\n\t\t\t\t((u32)input->formatted.inner_mac[1] << 8) |\n\t\t\t\t((u32)input->formatted.inner_mac[2] << 16) |\n\t\t\t\t((u32)input->formatted.inner_mac[3] << 24));\n\t\taddr_high = ((u32)input->formatted.inner_mac[4] |\n\t\t\t\t((u32)input->formatted.inner_mac[5] << 8));\n\t\tcloud_type |= addr_high;\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);\n\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);\n\t}\n\n\t/* configure FDIRHASH register */\n\tfdirhash = input->formatted.bkt_hash;\n\tfdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);\n\n\t/*\n\t * flush all previous writes to make certain registers are\n\t * programmed prior to issuing the command\n\t */\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* configure FDIRCMD register */\n\tfdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |\n\t\t IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;\n\tif (queue == IXGBE_FDIR_DROP_QUEUE)\n\t\tfdircmd |= IXGBE_FDIRCMD_DROP;\n\tif (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)\n\t\tfdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;\n\tfdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;\n\tfdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;\n\tfdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);\n\terr = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);\n\tif (err) {\n\t\tDEBUGOUT(\"Flow Director command did not complete!\\n\");\n\t\treturn err;\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\ns32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t union ixgbe_atr_input *input,\n\t\t\t\t\t u16 soft_id)\n{\n\tu32 fdirhash;\n\tu32 fdircmd;\n\ts32 err;\n\n\t/* configure FDIRHASH register */\n\tfdirhash = input->formatted.bkt_hash;\n\tfdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);\n\n\t/* flush hash to HW */\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Query if filter is present */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);\n\n\terr = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);\n\tif (err) {\n\t\tDEBUGOUT(\"Flow Director command did not complete!\\n\");\n\t\treturn err;\n\t}\n\n\t/* if filter exists in hardware then remove it */\n\tif (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,\n\t\t\t\tIXGBE_FDIRCMD_CMD_REMOVE_FLOW);\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter\n * @hw: pointer to hardware structure\n * @input: input bitstream\n * @input_mask: mask for the input bitstream\n * @soft_id: software index for the filters\n * @queue: queue index to direct traffic to\n *\n * Note that the caller to this function must lock before calling, since the\n * hardware writes must be protected from one another.\n **/\ns32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\tunion ixgbe_atr_input *input,\n\t\t\t\t\tunion ixgbe_atr_input *input_mask,\n\t\t\t\t\tu16 soft_id, u8 queue, bool cloud_mode)\n{\n\ts32 err = IXGBE_ERR_CONFIG;\n\n\tDEBUGFUNC(\"ixgbe_fdir_add_perfect_filter_82599\");\n\n\t/*\n\t * Check flow_type formatting, and bail out before we touch the hardware\n\t * if there's a configuration issue\n\t */\n\tswitch (input->formatted.flow_type) {\n\tcase IXGBE_ATR_FLOW_TYPE_IPV4:\n\tcase IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:\n\t\tinput_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;\n\t\tif (input->formatted.dst_port || input->formatted.src_port) {\n\t\t\tDEBUGOUT(\" Error on src/dst port\\n\");\n\t\t\treturn IXGBE_ERR_CONFIG;\n\t\t}\n\t\tbreak;\n\tcase IXGBE_ATR_FLOW_TYPE_SCTPV4:\n\tcase IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:\n\t\tif (input->formatted.dst_port || input->formatted.src_port) {\n\t\t\tDEBUGOUT(\" Error on src/dst port\\n\");\n\t\t\treturn IXGBE_ERR_CONFIG;\n\t\t}\n\tcase IXGBE_ATR_FLOW_TYPE_TCPV4:\n\tcase IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:\n\tcase IXGBE_ATR_FLOW_TYPE_UDPV4:\n\tcase IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:\n\t\tinput_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |\n\t\t\t\t\t\t IXGBE_ATR_L4TYPE_MASK;\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\" Error on flow type input\\n\");\n\t\treturn err;\n\t}\n\n\t/* program input mask into the HW */\n\terr = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);\n\tif (err)\n\t\treturn err;\n\n\t/* apply mask and compute/store hash */\n\tixgbe_atr_compute_perfect_hash_82599(input, input_mask);\n\n\t/* program filters to filter memory */\n\treturn ixgbe_fdir_write_perfect_filter_82599(hw, input,\n\t\t\t\t\t\t soft_id, queue, cloud_mode);\n}\n\n/**\n * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register\n * @hw: pointer to hardware structure\n * @reg: analog register to read\n * @val: read value\n *\n * Performs read operation to Omer analog register specified.\n **/\ns32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)\n{\n\tu32 core_ctl;\n\n\tDEBUGFUNC(\"ixgbe_read_analog_reg8_82599\");\n\n\tIXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |\n\t\t\t(reg << 8));\n\tIXGBE_WRITE_FLUSH(hw);\n\tusec_delay(10);\n\tcore_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);\n\t*val = (u8)core_ctl;\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register\n * @hw: pointer to hardware structure\n * @reg: atlas register to write\n * @val: value to write\n *\n * Performs write operation to Omer analog register specified.\n **/\ns32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)\n{\n\tu32 core_ctl;\n\n\tDEBUGFUNC(\"ixgbe_write_analog_reg8_82599\");\n\n\tcore_ctl = (reg << 8) | val;\n\tIXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);\n\tIXGBE_WRITE_FLUSH(hw);\n\tusec_delay(10);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx\n * @hw: pointer to hardware structure\n *\n * Starts the hardware using the generic start_hw function\n * and the generation start_hw function.\n * Then performs revision-specific operations, if any.\n **/\ns32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_start_hw_82599\");\n\n\tret_val = ixgbe_start_hw_generic(hw);\n\tif (ret_val != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\tret_val = ixgbe_start_hw_gen2(hw);\n\tif (ret_val != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\t/* We need to run link autotry after the driver loads */\n\thw->mac.autotry_restart = true;\n\n\tif (ret_val == IXGBE_SUCCESS)\n\t\tret_val = ixgbe_verify_fw_version_82599(hw);\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_identify_phy_82599 - Get physical layer module\n * @hw: pointer to hardware structure\n *\n * Determines the physical layer module found on the current adapter.\n * If PHY already detected, maintains current PHY type in hw struct,\n * otherwise executes the PHY detection routine.\n **/\ns32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_identify_phy_82599\");\n\n\t/* Detect PHY if not unknown - returns success if already detected. */\n\tstatus = ixgbe_identify_phy_generic(hw);\n\tif (status != IXGBE_SUCCESS) {\n\t\t/* 82599 10GBASE-T requires an external PHY */\n\t\tif (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)\n\t\t\treturn status;\n\t\telse\n\t\t\tstatus = ixgbe_identify_module_generic(hw);\n\t}\n\n\t/* Set PHY type none if no PHY detected */\n\tif (hw->phy.type == ixgbe_phy_unknown) {\n\t\thw->phy.type = ixgbe_phy_none;\n\t\treturn IXGBE_SUCCESS;\n\t}\n\n\t/* Return error if SFP module has been detected but is not supported */\n\tif (hw->phy.type == ixgbe_phy_sfp_unsupported)\n\t\treturn IXGBE_ERR_SFP_NOT_SUPPORTED;\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type\n * @hw: pointer to hardware structure\n *\n * Determines physical layer capabilities of the current configuration.\n **/\nu32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)\n{\n\tu32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n\tu32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tu32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);\n\tu32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;\n\tu32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;\n\tu32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;\n\tu16 ext_ability = 0;\n\n\tDEBUGFUNC(\"ixgbe_get_support_physical_layer_82599\");\n\n\thw->phy.ops.identify(hw);\n\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_tn:\n\tcase ixgbe_phy_cu_unknown:\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,\n\t\tIXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);\n\t\tif (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;\n\t\tif (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;\n\t\tif (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;\n\t\tgoto out;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tswitch (autoc & IXGBE_AUTOC_LMS_MASK) {\n\tcase IXGBE_AUTOC_LMS_1G_AN:\n\tcase IXGBE_AUTOC_LMS_1G_LINK_NO_AN:\n\t\tif (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |\n\t\t\t IXGBE_PHYSICAL_LAYER_1000BASE_BX;\n\t\t\tgoto out;\n\t\t} else\n\t\t\t/* SFI mode so read SFP module */\n\t\t\tgoto sfp_check;\n\t\tbreak;\n\tcase IXGBE_AUTOC_LMS_10G_LINK_NO_AN:\n\t\tif (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;\n\t\telse if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;\n\t\telse if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;\n\t\tgoto out;\n\t\tbreak;\n\tcase IXGBE_AUTOC_LMS_10G_SERIAL:\n\t\tif (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;\n\t\t\tgoto out;\n\t\t} else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)\n\t\t\tgoto sfp_check;\n\t\tbreak;\n\tcase IXGBE_AUTOC_LMS_KX4_KX_KR:\n\tcase IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:\n\t\tif (autoc & IXGBE_AUTOC_KX_SUPP)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;\n\t\tif (autoc & IXGBE_AUTOC_KX4_SUPP)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;\n\t\tif (autoc & IXGBE_AUTOC_KR_SUPP)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;\n\t\tgoto out;\n\t\tbreak;\n\tdefault:\n\t\tgoto out;\n\t\tbreak;\n\t}\n\nsfp_check:\n\t/* SFP check must be done last since DA modules are sometimes used to\n\t * test KR mode - we need to id KR mode correctly before SFP module.\n\t * Call identify_sfp because the pluggable module may have changed */\n\tphysical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);\nout:\n\treturn physical_layer;\n}\n\n/**\n * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599\n * @hw: pointer to hardware structure\n * @regval: register value to write to RXCTRL\n *\n * Enables the Rx DMA unit for 82599\n **/\ns32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)\n{\n\n\tDEBUGFUNC(\"ixgbe_enable_rx_dma_82599\");\n\n\t/*\n\t * Workaround for 82599 silicon errata when enabling the Rx datapath.\n\t * If traffic is incoming before we enable the Rx unit, it could hang\n\t * the Rx DMA unit. Therefore, make sure the security engine is\n\t * completely disabled prior to enabling the Rx unit.\n\t */\n\n\thw->mac.ops.disable_sec_rx_path(hw);\n\n\tif (regval & IXGBE_RXCTRL_RXEN)\n\t\tixgbe_enable_rx(hw);\n\telse\n\t\tixgbe_disable_rx(hw);\n\n\thw->mac.ops.enable_sec_rx_path(hw);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_verify_fw_version_82599 - verify FW version for 82599\n * @hw: pointer to hardware structure\n *\n * Verifies that installed the firmware version is 0.6 or higher\n * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.\n *\n * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or\n * if the FW version is not supported.\n **/\nSTATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_EEPROM_VERSION;\n\tu16 fw_offset, fw_ptp_cfg_offset;\n\tu16 fw_version;\n\n\tDEBUGFUNC(\"ixgbe_verify_fw_version_82599\");\n\n\t/* firmware check is only necessary for SFI devices */\n\tif (hw->phy.media_type != ixgbe_media_type_fiber) {\n\t\tstatus = IXGBE_SUCCESS;\n\t\tgoto fw_version_out;\n\t}\n\n\t/* get the offset to the Firmware Module block */\n\tif (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {\n\t\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t\t \"eeprom read at offset %d failed\", IXGBE_FW_PTR);\n\t\treturn IXGBE_ERR_EEPROM_VERSION;\n\t}\n\n\tif ((fw_offset == 0) || (fw_offset == 0xFFFF))\n\t\tgoto fw_version_out;\n\n\t/* get the offset to the Pass Through Patch Configuration block */\n\tif (hw->eeprom.ops.read(hw, (fw_offset +\n\t\t\t\t IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),\n\t\t\t\t &fw_ptp_cfg_offset)) {\n\t\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t\t \"eeprom read at offset %d failed\",\n\t\t\t fw_offset +\n\t\t\t IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);\n\t\treturn IXGBE_ERR_EEPROM_VERSION;\n\t}\n\n\tif ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))\n\t\tgoto fw_version_out;\n\n\t/* get the firmware version */\n\tif (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +\n\t\t\t IXGBE_FW_PATCH_VERSION_4), &fw_version)) {\n\t\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t\t \"eeprom read at offset %d failed\",\n\t\t\t fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);\n\t\treturn IXGBE_ERR_EEPROM_VERSION;\n\t}\n\n\tif (fw_version > 0x5)\n\t\tstatus = IXGBE_SUCCESS;\n\nfw_version_out:\n\treturn status;\n}\n\n/**\n * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.\n * @hw: pointer to hardware structure\n *\n * Returns true if the LESM FW module is present and enabled. Otherwise\n * returns false. Smart Speed must be disabled if LESM FW module is enabled.\n **/\nbool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)\n{\n\tbool lesm_enabled = false;\n\tu16 fw_offset, fw_lesm_param_offset, fw_lesm_state;\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_verify_lesm_fw_enabled_82599\");\n\n\t/* get the offset to the Firmware Module block */\n\tstatus = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);\n\n\tif ((status != IXGBE_SUCCESS) ||\n\t (fw_offset == 0) || (fw_offset == 0xFFFF))\n\t\tgoto out;\n\n\t/* get the offset to the LESM Parameters block */\n\tstatus = hw->eeprom.ops.read(hw, (fw_offset +\n\t\t\t\t IXGBE_FW_LESM_PARAMETERS_PTR),\n\t\t\t\t &fw_lesm_param_offset);\n\n\tif ((status != IXGBE_SUCCESS) ||\n\t (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))\n\t\tgoto out;\n\n\t/* get the LESM state word */\n\tstatus = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +\n\t\t\t\t IXGBE_FW_LESM_STATE_1),\n\t\t\t\t &fw_lesm_state);\n\n\tif ((status == IXGBE_SUCCESS) &&\n\t (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))\n\t\tlesm_enabled = true;\n\nout:\n\treturn lesm_enabled;\n}\n\n/**\n * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using\n * fastest available method\n *\n * @hw: pointer to hardware structure\n * @offset: offset of word in EEPROM to read\n * @words: number of words\n * @data: word(s) read from the EEPROM\n *\n * Retrieves 16 bit word(s) read from EEPROM\n **/\nSTATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data)\n{\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\ts32 ret_val = IXGBE_ERR_CONFIG;\n\n\tDEBUGFUNC(\"ixgbe_read_eeprom_buffer_82599\");\n\n\t/*\n\t * If EEPROM is detected and can be addressed using 14 bits,\n\t * use EERD otherwise use bit bang\n\t */\n\tif ((eeprom->type == ixgbe_eeprom_spi) &&\n\t (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))\n\t\tret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,\n\t\t\t\t\t\t\t data);\n\telse\n\t\tret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,\n\t\t\t\t\t\t\t\t words,\n\t\t\t\t\t\t\t\t data);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_read_eeprom_82599 - Read EEPROM word using\n * fastest available method\n *\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM\n **/\nSTATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,\n\t\t\t\t u16 offset, u16 *data)\n{\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\ts32 ret_val = IXGBE_ERR_CONFIG;\n\n\tDEBUGFUNC(\"ixgbe_read_eeprom_82599\");\n\n\t/*\n\t * If EEPROM is detected and can be addressed using 14 bits,\n\t * use EERD otherwise use bit bang\n\t */\n\tif ((eeprom->type == ixgbe_eeprom_spi) &&\n\t (offset <= IXGBE_EERD_MAX_ADDR))\n\t\tret_val = ixgbe_read_eerd_generic(hw, offset, data);\n\telse\n\t\tret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_reset_pipeline_82599 - perform pipeline reset\n *\n * @hw: pointer to hardware structure\n *\n * Reset pipeline by asserting Restart_AN together with LMS change to ensure\n * full pipeline reset. This function assumes the SW/FW lock is held.\n **/\ns32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)\n{\n\ts32 ret_val;\n\tu32 anlp1_reg = 0;\n\tu32 i, autoc_reg, autoc2_reg;\n\n\t/* Enable link if disabled in NVM */\n\tautoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);\n\tif (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {\n\t\tautoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t}\n\n\tautoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tautoc_reg |= IXGBE_AUTOC_AN_RESTART;\n\t/* Write AUTOC register with toggled LMS[2] bit and Restart_AN */\n\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC,\n\t\t\tautoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));\n\t/* Wait for AN to leave state 0 */\n\tfor (i = 0; i < 10; i++) {\n\t\tmsec_delay(4);\n\t\tanlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);\n\t\tif (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)\n\t\t\tbreak;\n\t}\n\n\tif (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {\n\t\tDEBUGOUT(\"auto negotiation not completed\\n\");\n\t\tret_val = IXGBE_ERR_RESET_FAILED;\n\t\tgoto reset_pipeline_out;\n\t}\n\n\tret_val = IXGBE_SUCCESS;\n\nreset_pipeline_out:\n\t/* Write AUTOC register with original LMS field and Restart_AN */\n\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to read\n * @data: value read\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface at\n * a specified device address.\n **/\nSTATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\tu8 dev_addr, u8 *data)\n{\n\tu32 esdp;\n\ts32 status;\n\ts32 timeout = 200;\n\n\tDEBUGFUNC(\"ixgbe_read_i2c_byte_82599\");\n\n\tif (hw->phy.qsfp_shared_i2c_bus == TRUE) {\n\t\t/* Acquire I2C bus ownership. */\n\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\tesdp |= IXGBE_ESDP_SDP0;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\n\t\twhile (timeout) {\n\t\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\t\tif (esdp & IXGBE_ESDP_SDP1)\n\t\t\t\tbreak;\n\n\t\t\tmsec_delay(5);\n\t\t\ttimeout--;\n\t\t}\n\n\t\tif (!timeout) {\n\t\t\tDEBUGOUT(\"Driver can't access resource,\"\n\t\t\t\t \" acquiring I2C bus timeout.\\n\");\n\t\t\tstatus = IXGBE_ERR_I2C;\n\t\t\tgoto release_i2c_access;\n\t\t}\n\t}\n\n\tstatus = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);\n\nrelease_i2c_access:\n\n\tif (hw->phy.qsfp_shared_i2c_bus == TRUE) {\n\t\t/* Release I2C bus ownership. */\n\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\tesdp &= ~IXGBE_ESDP_SDP0;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @data: value to write\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface at\n * a specified device address.\n **/\nSTATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data)\n{\n\tu32 esdp;\n\ts32 status;\n\ts32 timeout = 200;\n\n\tDEBUGFUNC(\"ixgbe_write_i2c_byte_82599\");\n\n\tif (hw->phy.qsfp_shared_i2c_bus == TRUE) {\n\t\t/* Acquire I2C bus ownership. */\n\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\tesdp |= IXGBE_ESDP_SDP0;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\n\t\twhile (timeout) {\n\t\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\t\tif (esdp & IXGBE_ESDP_SDP1)\n\t\t\t\tbreak;\n\n\t\t\tmsec_delay(5);\n\t\t\ttimeout--;\n\t\t}\n\n\t\tif (!timeout) {\n\t\t\tDEBUGOUT(\"Driver can't access resource,\"\n\t\t\t\t \" acquiring I2C bus timeout.\\n\");\n\t\t\tstatus = IXGBE_ERR_I2C;\n\t\t\tgoto release_i2c_access;\n\t\t}\n\t}\n\n\tstatus = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);\n\nrelease_i2c_access:\n\n\tif (hw->phy.qsfp_shared_i2c_bus == TRUE) {\n\t\t/* Release I2C bus ownership. */\n\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\tesdp &= ~IXGBE_ESDP_SDP0;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t}\n\n\treturn status;\n}\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_82599.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _IXGBE_82599_H_\n#define _IXGBE_82599_H_\n\ns32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed, bool *autoneg);\nenum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);\nvoid ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);\nvoid ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);\nvoid ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);\nvoid ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw,\n\t\t\t\t\tixgbe_link_speed speed);\ns32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,\n\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw);\nvoid ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw);\ns32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);\ns32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);\ns32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);\ns32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);\ns32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);\ns32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);\nu32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);\ns32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);\ns32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val);\ns32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 reg_val, bool locked);\n#endif /* _IXGBE_82599_H_ */\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_api.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"ixgbe_api.h\"\n#include \"ixgbe_common.h\"\n\n#define IXGBE_EMPTY_PARAM\n\nstatic const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = {\n\tIXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM)\n};\n\nstatic const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {\n\tIXGBE_MVALS_INIT(_X540)\n};\n\nstatic const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {\n\tIXGBE_MVALS_INIT(_X550)\n};\n\nstatic const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {\n\tIXGBE_MVALS_INIT(_X550EM_x)\n};\n\n/**\n * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg\n * @hw: pointer to hardware structure\n * @map: pointer to u8 arr for returning map\n *\n * Read the rtrup2tc HW register and resolve its content into map\n **/\nvoid ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map)\n{\n\tif (hw->mac.ops.get_rtrup2tc)\n\t\thw->mac.ops.get_rtrup2tc(hw, map);\n}\n\n/**\n * ixgbe_init_shared_code - Initialize the shared code\n * @hw: pointer to hardware structure\n *\n * This will assign function pointers and assign the MAC type and PHY code.\n * Does not touch the hardware. This function must be called prior to any\n * other function in the shared code. The ixgbe_hw structure should be\n * memset to 0 prior to calling this function. The following fields in\n * hw structure should be filled in prior to calling this function:\n * hw_addr, back, device_id, vendor_id, subsystem_device_id,\n * subsystem_vendor_id, and revision_id\n **/\ns32 ixgbe_init_shared_code(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_init_shared_code\");\n\n\t/*\n\t * Set the mac type\n\t */\n\tixgbe_set_mac_type(hw);\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tstatus = ixgbe_init_ops_82598(hw);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\t\tstatus = ixgbe_init_ops_82599(hw);\n\t\tbreak;\n\tcase ixgbe_mac_X540:\n\t\tstatus = ixgbe_init_ops_X540(hw);\n\t\tbreak;\n\tcase ixgbe_mac_X550:\n\t\tstatus = ixgbe_init_ops_X550(hw);\n\t\tbreak;\n\tcase ixgbe_mac_X550EM_x:\n\t\tstatus = ixgbe_init_ops_X550EM(hw);\n\t\tbreak;\n\tcase ixgbe_mac_82599_vf:\n\tcase ixgbe_mac_X540_vf:\n\tcase ixgbe_mac_X550_vf:\n\tcase ixgbe_mac_X550EM_x_vf:\n\t\tstatus = ixgbe_init_ops_vf(hw);\n\t\tbreak;\n\tdefault:\n\t\tstatus = IXGBE_ERR_DEVICE_NOT_SUPPORTED;\n\t\tbreak;\n\t}\n\thw->mac.max_link_up_time = IXGBE_LINK_UP_TIME;\n\n\treturn status;\n}\n\n/**\n * ixgbe_set_mac_type - Sets MAC type\n * @hw: pointer to the HW structure\n *\n * This function sets the mac type of the adapter based on the\n * vendor ID and device ID stored in the hw structure.\n **/\ns32 ixgbe_set_mac_type(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_set_mac_type\\n\");\n\n\tif (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) {\n\t\tERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,\n\t\t\t \"Unsupported vendor id: %x\", hw->vendor_id);\n\t\treturn IXGBE_ERR_DEVICE_NOT_SUPPORTED;\n\t}\n\n\thw->mvals = ixgbe_mvals_base;\n\n\tswitch (hw->device_id) {\n\tcase IXGBE_DEV_ID_82598:\n\tcase IXGBE_DEV_ID_82598_BX:\n\tcase IXGBE_DEV_ID_82598AF_SINGLE_PORT:\n\tcase IXGBE_DEV_ID_82598AF_DUAL_PORT:\n\tcase IXGBE_DEV_ID_82598AT:\n\tcase IXGBE_DEV_ID_82598AT2:\n\tcase IXGBE_DEV_ID_82598EB_CX4:\n\tcase IXGBE_DEV_ID_82598_CX4_DUAL_PORT:\n\tcase IXGBE_DEV_ID_82598_DA_DUAL_PORT:\n\tcase IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:\n\tcase IXGBE_DEV_ID_82598EB_XF_LR:\n\tcase IXGBE_DEV_ID_82598EB_SFP_LOM:\n\t\thw->mac.type = ixgbe_mac_82598EB;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_KX4:\n\tcase IXGBE_DEV_ID_82599_KX4_MEZZ:\n\tcase IXGBE_DEV_ID_82599_XAUI_LOM:\n\tcase IXGBE_DEV_ID_82599_COMBO_BACKPLANE:\n\tcase IXGBE_DEV_ID_82599_KR:\n\tcase IXGBE_DEV_ID_82599_SFP:\n\tcase IXGBE_DEV_ID_82599_BACKPLANE_FCOE:\n\tcase IXGBE_DEV_ID_82599_SFP_FCOE:\n\tcase IXGBE_DEV_ID_82599_SFP_EM:\n\tcase IXGBE_DEV_ID_82599_SFP_SF2:\n\tcase IXGBE_DEV_ID_82599_SFP_SF_QP:\n\tcase IXGBE_DEV_ID_82599_QSFP_SF_QP:\n\tcase IXGBE_DEV_ID_82599EN_SFP:\n\tcase IXGBE_DEV_ID_82599_CX4:\n\tcase IXGBE_DEV_ID_82599_LS:\n\tcase IXGBE_DEV_ID_82599_T3_LOM:\n\t\thw->mac.type = ixgbe_mac_82599EB;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_VF:\n\tcase IXGBE_DEV_ID_82599_VF_HV:\n\t\thw->mac.type = ixgbe_mac_82599_vf;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X540_VF:\n\tcase IXGBE_DEV_ID_X540_VF_HV:\n\t\thw->mac.type = ixgbe_mac_X540_vf;\n\t\thw->mvals = ixgbe_mvals_X540;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X540T:\n\tcase IXGBE_DEV_ID_X540T1:\n\t\thw->mac.type = ixgbe_mac_X540;\n\t\thw->mvals = ixgbe_mvals_X540;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X550T:\n\t\thw->mac.type = ixgbe_mac_X550;\n\t\thw->mvals = ixgbe_mvals_X550;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X550EM_X_KX4:\n\tcase IXGBE_DEV_ID_X550EM_X_KR:\n\tcase IXGBE_DEV_ID_X550EM_X_10G_T:\n\tcase IXGBE_DEV_ID_X550EM_X_1G_T:\n\tcase IXGBE_DEV_ID_X550EM_X_SFP:\n\t\thw->mac.type = ixgbe_mac_X550EM_x;\n\t\thw->mvals = ixgbe_mvals_X550EM_x;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X550_VF:\n\tcase IXGBE_DEV_ID_X550_VF_HV:\n\t\thw->mac.type = ixgbe_mac_X550_vf;\n\t\thw->mvals = ixgbe_mvals_X550;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X550EM_X_VF:\n\tcase IXGBE_DEV_ID_X550EM_X_VF_HV:\n\t\thw->mac.type = ixgbe_mac_X550EM_x_vf;\n\t\thw->mvals = ixgbe_mvals_X550EM_x;\n\t\tbreak;\n\tdefault:\n\t\tret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;\n\t\tERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,\n\t\t\t \"Unsupported device id: %x\",\n\t\t\t hw->device_id);\n\t\tbreak;\n\t}\n\n\tDEBUGOUT2(\"ixgbe_set_mac_type found mac: %d, returns: %d\\n\",\n\t\t hw->mac.type, ret_val);\n\treturn ret_val;\n}\n\n/**\n * ixgbe_init_hw - Initialize the hardware\n * @hw: pointer to hardware structure\n *\n * Initialize the hardware by resetting and then starting the hardware\n **/\ns32 ixgbe_init_hw(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_reset_hw - Performs a hardware reset\n * @hw: pointer to hardware structure\n *\n * Resets the hardware by resetting the transmit and receive units, masks and\n * clears all interrupts, performs a PHY reset, and performs a MAC reset\n **/\ns32 ixgbe_reset_hw(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_start_hw - Prepares hardware for Rx/Tx\n * @hw: pointer to hardware structure\n *\n * Starts the hardware by filling the bus info structure and media type,\n * clears all on chip counters, initializes receive address registers,\n * multicast table, VLAN filter table, calls routine to setup link and\n * flow control settings, and leaves transmit and receive units disabled\n * and uninitialized.\n **/\ns32 ixgbe_start_hw(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,\n * which is disabled by default in ixgbe_start_hw();\n *\n * @hw: pointer to hardware structure\n *\n * Enable relaxed ordering;\n **/\nvoid ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw)\n{\n\tif (hw->mac.ops.enable_relaxed_ordering)\n\t\thw->mac.ops.enable_relaxed_ordering(hw);\n}\n\n/**\n * ixgbe_clear_hw_cntrs - Clear hardware counters\n * @hw: pointer to hardware structure\n *\n * Clears all hardware statistics counters by reading them from the hardware\n * Statistics counters are clear on read.\n **/\ns32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_media_type - Get media type\n * @hw: pointer to hardware structure\n *\n * Returns the media type (fiber, copper, backplane)\n **/\nenum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),\n\t\t\t ixgbe_media_type_unknown);\n}\n\n/**\n * ixgbe_get_mac_addr - Get MAC address\n * @hw: pointer to hardware structure\n * @mac_addr: Adapter MAC address\n *\n * Reads the adapter's MAC address from the first Receive Address Register\n * (RAR0) A reset of the adapter must have been performed prior to calling\n * this function in order for the MAC address to have been loaded from the\n * EEPROM into RAR0\n **/\ns32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,\n\t\t\t (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_san_mac_addr - Get SAN MAC address\n * @hw: pointer to hardware structure\n * @san_mac_addr: SAN MAC address\n *\n * Reads the SAN MAC address from the EEPROM, if it's available. This is\n * per-port, so set_lan_id() must be called before reading the addresses.\n **/\ns32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr,\n\t\t\t (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_san_mac_addr - Write a SAN MAC address\n * @hw: pointer to hardware structure\n * @san_mac_addr: SAN MAC address\n *\n * Writes A SAN MAC address to the EEPROM.\n **/\ns32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr,\n\t\t\t (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_device_caps - Get additional device capabilities\n * @hw: pointer to hardware structure\n * @device_caps: the EEPROM word for device capabilities\n *\n * Reads the extra device capabilities from the EEPROM\n **/\ns32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_device_caps,\n\t\t\t (hw, device_caps), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM\n * @hw: pointer to hardware structure\n * @wwnn_prefix: the alternative WWNN prefix\n * @wwpn_prefix: the alternative WWPN prefix\n *\n * This function will read the EEPROM from the alternative SAN MAC address\n * block to check the support for the alternative WWNN/WWPN prefix support.\n **/\ns32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n\t\t\t u16 *wwpn_prefix)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,\n\t\t\t (hw, wwnn_prefix, wwpn_prefix),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM\n * @hw: pointer to hardware structure\n * @bs: the fcoe boot status\n *\n * This function will read the FCOE boot status from the iSCSI FCOE block\n **/\ns32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status,\n\t\t\t (hw, bs),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_bus_info - Set PCI bus info\n * @hw: pointer to hardware structure\n *\n * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure\n **/\ns32 ixgbe_get_bus_info(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_num_of_tx_queues - Get Tx queues\n * @hw: pointer to hardware structure\n *\n * Returns the number of transmit queues for the given adapter.\n **/\nu32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)\n{\n\treturn hw->mac.max_tx_queues;\n}\n\n/**\n * ixgbe_get_num_of_rx_queues - Get Rx queues\n * @hw: pointer to hardware structure\n *\n * Returns the number of receive queues for the given adapter.\n **/\nu32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)\n{\n\treturn hw->mac.max_rx_queues;\n}\n\n/**\n * ixgbe_stop_adapter - Disable Rx/Tx units\n * @hw: pointer to hardware structure\n *\n * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,\n * disables transmit and receive units. The adapter_stopped flag is used by\n * the shared code and drivers to determine if the adapter is in a stopped\n * state and should not touch the hardware.\n **/\ns32 ixgbe_stop_adapter(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_pba_string - Reads part number string from EEPROM\n * @hw: pointer to hardware structure\n * @pba_num: stores the part number string from the EEPROM\n * @pba_num_size: part number string buffer length\n *\n * Reads the part number string from the EEPROM.\n **/\ns32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)\n{\n\treturn ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);\n}\n\n/**\n * ixgbe_read_pba_num - Reads part number from EEPROM\n * @hw: pointer to hardware structure\n * @pba_num: stores the part number from the EEPROM\n *\n * Reads the part number from the EEPROM.\n **/\ns32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)\n{\n\treturn ixgbe_read_pba_num_generic(hw, pba_num);\n}\n\n/**\n * ixgbe_identify_phy - Get PHY type\n * @hw: pointer to hardware structure\n *\n * Determines the physical layer module found on the current adapter.\n **/\ns32 ixgbe_identify_phy(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_SUCCESS;\n\n\tif (hw->phy.type == ixgbe_phy_unknown) {\n\t\tstatus = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),\n\t\t\t\t\t IXGBE_NOT_IMPLEMENTED);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_reset_phy - Perform a PHY reset\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_reset_phy(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_SUCCESS;\n\n\tif (hw->phy.type == ixgbe_phy_unknown) {\n\t\tif (ixgbe_identify_phy(hw) != IXGBE_SUCCESS)\n\t\t\tstatus = IXGBE_ERR_PHY;\n\t}\n\n\tif (status == IXGBE_SUCCESS) {\n\t\tstatus = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),\n\t\t\t\t\t IXGBE_NOT_IMPLEMENTED);\n\t}\n\treturn status;\n}\n\n/**\n * ixgbe_get_phy_firmware_version -\n * @hw: pointer to hardware structure\n * @firmware_version: pointer to firmware version\n **/\ns32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)\n{\n\ts32 status = IXGBE_SUCCESS;\n\n\tstatus = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,\n\t\t\t\t (hw, firmware_version),\n\t\t\t\t IXGBE_NOT_IMPLEMENTED);\n\treturn status;\n}\n\n/**\n * ixgbe_read_phy_reg - Read PHY register\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit address of PHY register to read\n * @phy_data: Pointer to read data from PHY register\n *\n * Reads a value from a specified PHY register\n **/\ns32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n\t\t u16 *phy_data)\n{\n\tif (hw->phy.id == 0)\n\t\tixgbe_identify_phy(hw);\n\n\treturn ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,\n\t\t\t device_type, phy_data), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_phy_reg - Write PHY register\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit PHY register to write\n * @phy_data: Data to write to the PHY register\n *\n * Writes a value to specified PHY register\n **/\ns32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n\t\t\tu16 phy_data)\n{\n\tif (hw->phy.id == 0)\n\t\tixgbe_identify_phy(hw);\n\n\treturn ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,\n\t\t\t device_type, phy_data), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_setup_phy_link - Restart PHY autoneg\n * @hw: pointer to hardware structure\n *\n * Restart autonegotiation and PHY and waits for completion.\n **/\ns32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_setup_internal_phy - Configure integrated PHY\n * @hw: pointer to hardware structure\n *\n * Reconfigure the integrated PHY in order to enable talk to the external PHY.\n * Returns success if not implemented, since nothing needs to be done in this\n * case.\n */\ns32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw),\n\t\t\t IXGBE_SUCCESS);\n}\n\n/**\n * ixgbe_check_phy_link - Determine link and speed status\n * @hw: pointer to hardware structure\n *\n * Reads a PHY register to determine if link is up and the current speed for\n * the PHY.\n **/\ns32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t bool *link_up)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,\n\t\t\t link_up), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_setup_phy_link_speed - Set auto advertise\n * @hw: pointer to hardware structure\n * @speed: new link speed\n *\n * Sets the auto advertised capabilities\n **/\ns32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t\t bool autoneg_wait_to_complete)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,\n\t\t\t autoneg_wait_to_complete),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_phy_power - Control the phy power state\n * @hw: pointer to hardware structure\n * @on: true for on, false for off\n */\ns32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_check_link - Get link and speed status\n * @hw: pointer to hardware structure\n *\n * Reads the links register to determine if link is up and the current speed\n **/\ns32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t bool *link_up, bool link_up_wait_to_complete)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,\n\t\t\t link_up, link_up_wait_to_complete),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_disable_tx_laser - Disable Tx laser\n * @hw: pointer to hardware structure\n *\n * If the driver needs to disable the laser on SFI optics.\n **/\nvoid ixgbe_disable_tx_laser(struct ixgbe_hw *hw)\n{\n\tif (hw->mac.ops.disable_tx_laser)\n\t\thw->mac.ops.disable_tx_laser(hw);\n}\n\n/**\n * ixgbe_enable_tx_laser - Enable Tx laser\n * @hw: pointer to hardware structure\n *\n * If the driver needs to enable the laser on SFI optics.\n **/\nvoid ixgbe_enable_tx_laser(struct ixgbe_hw *hw)\n{\n\tif (hw->mac.ops.enable_tx_laser)\n\t\thw->mac.ops.enable_tx_laser(hw);\n}\n\n/**\n * ixgbe_flap_tx_laser - flap Tx laser to start autotry process\n * @hw: pointer to hardware structure\n *\n * When the driver changes the link speeds that it can support then\n * flap the tx laser to alert the link partner to start autotry\n * process on its end.\n **/\nvoid ixgbe_flap_tx_laser(struct ixgbe_hw *hw)\n{\n\tif (hw->mac.ops.flap_tx_laser)\n\t\thw->mac.ops.flap_tx_laser(hw);\n}\n\n/**\n * ixgbe_setup_link - Set link speed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n *\n * Configures link settings. Restarts the link.\n * Performs autonegotiation if needed.\n **/\ns32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t bool autoneg_wait_to_complete)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,\n\t\t\t autoneg_wait_to_complete),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_setup_mac_link - Set link speed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n *\n * Configures link settings. Restarts the link.\n * Performs autonegotiation if needed.\n **/\ns32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t\t bool autoneg_wait_to_complete)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed,\n\t\t\t autoneg_wait_to_complete),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_link_capabilities - Returns link capabilities\n * @hw: pointer to hardware structure\n *\n * Determines the link capabilities of the current configuration.\n **/\ns32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t\tbool *autoneg)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,\n\t\t\t speed, autoneg), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_led_on - Turn on LEDs\n * @hw: pointer to hardware structure\n * @index: led number to turn on\n *\n * Turns on the software controllable LEDs.\n **/\ns32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_led_off - Turn off LEDs\n * @hw: pointer to hardware structure\n * @index: led number to turn off\n *\n * Turns off the software controllable LEDs.\n **/\ns32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_blink_led_start - Blink LEDs\n * @hw: pointer to hardware structure\n * @index: led number to blink\n *\n * Blink LED based on index.\n **/\ns32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_blink_led_stop - Stop blinking LEDs\n * @hw: pointer to hardware structure\n *\n * Stop blinking LED based on index.\n **/\ns32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_init_eeprom_params - Initialize EEPROM parameters\n * @hw: pointer to hardware structure\n *\n * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n * ixgbe_hw struct in order to set up EEPROM access.\n **/\ns32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n\n/**\n * ixgbe_write_eeprom - Write word to EEPROM\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be written to\n * @data: 16 bit word to be written to the EEPROM\n *\n * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not\n * called after this function, the EEPROM will most likely contain an\n * invalid checksum.\n **/\ns32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be written to\n * @data: 16 bit word(s) to be written to the EEPROM\n * @words: number of words\n *\n * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not\n * called after this function, the EEPROM will most likely contain an\n * invalid checksum.\n **/\ns32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,\n\t\t\t u16 *data)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.write_buffer,\n\t\t\t (hw, offset, words, data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_eeprom - Read word from EEPROM\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be read\n * @data: read 16 bit value from EEPROM\n *\n * Reads 16 bit value from EEPROM\n **/\ns32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be read\n * @data: read 16 bit word(s) from EEPROM\n * @words: number of words\n *\n * Reads 16 bit word(s) from EEPROM\n **/\ns32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,\n\t\t\t u16 words, u16 *data)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.read_buffer,\n\t\t\t (hw, offset, words, data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum\n * @hw: pointer to hardware structure\n * @checksum_val: calculated checksum\n *\n * Performs checksum calculation and validates the EEPROM checksum\n **/\ns32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,\n\t\t\t (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_insert_mac_addr - Find a RAR for this mac address\n * @hw: pointer to hardware structure\n * @addr: Address to put into receive address register\n * @vmdq: VMDq pool to assign\n *\n * Puts an ethernet address into a receive address register, or\n * finds the rar that it is aleady in; adds to the pool list\n **/\ns32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr,\n\t\t\t (hw, addr, vmdq),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_rar - Set Rx address register\n * @hw: pointer to hardware structure\n * @index: Receive address register to write\n * @addr: Address to put into receive address register\n * @vmdq: VMDq \"set\"\n * @enable_addr: set flag that address is active\n *\n * Puts an ethernet address into a receive address register.\n **/\ns32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n\t\t u32 enable_addr)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,\n\t\t\t enable_addr), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_clear_rar - Clear Rx address register\n * @hw: pointer to hardware structure\n * @index: Receive address register to write\n *\n * Puts an ethernet address into a receive address register.\n **/\ns32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_vmdq - Associate a VMDq index with a receive address\n * @hw: pointer to hardware structure\n * @rar: receive address register index to associate with VMDq index\n * @vmdq: VMDq set or pool index\n **/\ns32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n\n}\n\n/**\n * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address\n * @hw: pointer to hardware structure\n * @vmdq: VMDq default pool index\n **/\ns32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,\n\t\t\t (hw, vmdq), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address\n * @hw: pointer to hardware structure\n * @rar: receive address register index to disassociate with VMDq index\n * @vmdq: VMDq set or pool index\n **/\ns32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_init_rx_addrs - Initializes receive address filters.\n * @hw: pointer to hardware structure\n *\n * Places the MAC address in receive address register 0 and clears the rest\n * of the receive address registers. Clears the multicast table. Assumes\n * the receiver is in reset when the routine is called.\n **/\ns32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_num_rx_addrs - Returns the number of RAR entries.\n * @hw: pointer to hardware structure\n **/\nu32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)\n{\n\treturn hw->mac.num_rar_entries;\n}\n\n/**\n * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses\n * @hw: pointer to hardware structure\n * @addr_list: the list of new multicast addresses\n * @addr_count: number of addresses\n * @func: iterator function to walk the multicast address list\n *\n * The given list replaces any existing list. Clears the secondary addrs from\n * receive address registers. Uses unused receive address registers for the\n * first secondary addresses, and falls back to promiscuous mode as needed.\n **/\ns32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,\n\t\t\t u32 addr_count, ixgbe_mc_addr_itr func)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,\n\t\t\t addr_list, addr_count, func),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses\n * @hw: pointer to hardware structure\n * @mc_addr_list: the list of new multicast addresses\n * @mc_addr_count: number of addresses\n * @func: iterator function to walk the multicast address list\n *\n * The given list replaces any existing list. Clears the MC addrs from receive\n * address registers and the multicast table. Uses unused receive address\n * registers for the first multicast addresses, and hashes the rest into the\n * multicast table.\n **/\ns32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,\n\t\t\t u32 mc_addr_count, ixgbe_mc_addr_itr func,\n\t\t\t bool clear)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,\n\t\t\t mc_addr_list, mc_addr_count, func, clear),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_enable_mc - Enable multicast address in RAR\n * @hw: pointer to hardware structure\n *\n * Enables multicast address in RAR and the use of the multicast hash table.\n **/\ns32 ixgbe_enable_mc(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_disable_mc - Disable multicast address in RAR\n * @hw: pointer to hardware structure\n *\n * Disables multicast address in RAR and the use of the multicast hash table.\n **/\ns32 ixgbe_disable_mc(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_clear_vfta - Clear VLAN filter table\n * @hw: pointer to hardware structure\n *\n * Clears the VLAN filer table, and the VMDq index associated with the filter\n **/\ns32 ixgbe_clear_vfta(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_vfta - Set VLAN filter table\n * @hw: pointer to hardware structure\n * @vlan: VLAN id to write to VLAN filter\n * @vind: VMDq output index that maps queue to VLAN id in VFTA\n * @vlan_on: boolean flag to turn on/off VLAN in VFTA\n *\n * Turn on/off specified VLAN in the VLAN filter table.\n **/\ns32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,\n\t\t\t vlan_on), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_vlvf - Set VLAN Pool Filter\n * @hw: pointer to hardware structure\n * @vlan: VLAN id to write to VLAN filter\n * @vind: VMDq output index that maps queue to VLAN id in VFVFB\n * @vlan_on: boolean flag to turn on/off VLAN in VFVF\n * @vfta_changed: pointer to boolean flag which indicates whether VFTA\n * should be changed\n *\n * Turn on/off specified bit in VLVF table.\n **/\ns32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,\n\t\t bool *vfta_changed)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,\n\t\t\t vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_fc_enable - Enable flow control\n * @hw: pointer to hardware structure\n *\n * Configures the flow control settings based on SW configuration.\n **/\ns32 ixgbe_fc_enable(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_setup_fc - Set up flow control\n * @hw: pointer to hardware structure\n *\n * Called at init time to set up flow control.\n **/\ns32 ixgbe_setup_fc(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw),\n\t\tIXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_fw_drv_ver - Try to send the driver version number FW\n * @hw: pointer to hardware structure\n * @maj: driver major number to be sent to firmware\n * @min: driver minor number to be sent to firmware\n * @build: driver build number to be sent to firmware\n * @ver: driver version number to be sent to firmware\n **/\ns32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n\t\t\t u8 ver)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,\n\t\t\t build, ver), IXGBE_NOT_IMPLEMENTED);\n}\n\n\n/**\n * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data\n * @hw: pointer to hardware structure\n *\n * Updates the temperatures in mac.thermal_sensor_data\n **/\ns32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw),\n\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds\n * @hw: pointer to hardware structure\n *\n * Inits the thermal sensor thresholds according to the NVM map\n **/\ns32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw),\n\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_dmac_config - Configure DMA Coalescing registers.\n * @hw: pointer to hardware structure\n *\n * Configure DMA coalescing. If enabling dmac, dmac is activated.\n * When disabling dmac, dmac enable dmac bit is cleared.\n **/\ns32 ixgbe_dmac_config(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw),\n\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers.\n * @hw: pointer to hardware structure\n *\n * Disables dmac, updates per TC settings, and then enable dmac.\n **/\ns32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw),\n\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers.\n * @hw: pointer to hardware structure\n *\n * Configure DMA coalescing threshold per TC and set high priority bit for\n * FCOE TC. The dmac enable bit must be cleared before configuring.\n **/\ns32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw),\n\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_setup_eee - Enable/disable EEE support\n * @hw: pointer to the HW structure\n * @enable_eee: boolean flag to enable EEE\n *\n * Enable/disable EEE based on enable_ee flag.\n * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C\n * are modified.\n *\n **/\ns32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee),\n\t\t\tIXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_source_address_pruning - Enable/Disable source address pruning\n * @hw: pointer to hardware structure\n * @enbale: enable or disable source address pruning\n * @pool: Rx pool - Rx pool to toggle source address pruning\n **/\nvoid ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,\n\t\t\t\t unsigned int pool)\n{\n\tif (hw->mac.ops.set_source_address_pruning)\n\t\thw->mac.ops.set_source_address_pruning(hw, enable, pool);\n}\n\n/**\n * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing\n * @hw: pointer to hardware structure\n * @enable: enable or disable switch for Ethertype anti-spoofing\n * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing\n *\n **/\nvoid ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)\n{\n\tif (hw->mac.ops.set_ethertype_anti_spoofing)\n\t\thw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf);\n}\n\n/**\n * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit address of PHY register to read\n * @device_type: type of device you want to communicate with\n * @phy_data: Pointer to read data from PHY register\n *\n * Reads a value from a specified PHY register\n **/\ns32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t u32 device_type, u32 *phy_data)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr,\n\t\t\t device_type, phy_data), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit PHY register to write\n * @device_type: type of device you want to communicate with\n * @phy_data: Data to write to the PHY register\n *\n * Writes a value to specified PHY register\n **/\ns32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t u32 device_type, u32 phy_data)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr,\n\t\t\t device_type, phy_data), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_disable_mdd - Disable malicious driver detection\n * @hw: pointer to hardware structure\n *\n **/\nvoid ixgbe_disable_mdd(struct ixgbe_hw *hw)\n{\n\tif (hw->mac.ops.disable_mdd)\n\t\thw->mac.ops.disable_mdd(hw);\n}\n\n/**\n * ixgbe_enable_mdd - Enable malicious driver detection\n * @hw: pointer to hardware structure\n *\n **/\nvoid ixgbe_enable_mdd(struct ixgbe_hw *hw)\n{\n\tif (hw->mac.ops.enable_mdd)\n\t\thw->mac.ops.enable_mdd(hw);\n}\n\n/**\n * ixgbe_mdd_event - Handle malicious driver detection event\n * @hw: pointer to hardware structure\n * @vf_bitmap: vf bitmap of malicious vfs\n *\n **/\nvoid ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap)\n{\n\tif (hw->mac.ops.mdd_event)\n\t\thw->mac.ops.mdd_event(hw, vf_bitmap);\n}\n\n/**\n * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver\n * detection event\n * @hw: pointer to hardware structure\n * @vf: vf index\n *\n **/\nvoid ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf)\n{\n\tif (hw->mac.ops.restore_mdd_vf)\n\t\thw->mac.ops.restore_mdd_vf(hw, vf);\n}\n\n/**\n * ixgbe_enter_lplu - Transition to low power states\n * @hw: pointer to hardware structure\n *\n * Configures Low Power Link Up on transition to low power states\n * (from D0 to non-D0).\n **/\ns32 ixgbe_enter_lplu(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw),\n\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_handle_lasi - Handle external Base T PHY interrupt\n * @hw: pointer to hardware structure\n *\n * Handle external Base T PHY interrupt. If high temperature\n * failure alarm then return error, else if link status change\n * then setup internal/external PHY link\n *\n * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature\n * failure alarm, else return PHY access status.\n */\ns32 ixgbe_handle_lasi(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw),\n\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_analog_reg8 - Reads 8 bit analog register\n * @hw: pointer to hardware structure\n * @reg: analog register to read\n * @val: read value\n *\n * Performs write operation to analog register specified.\n **/\ns32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,\n\t\t\t val), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_analog_reg8 - Writes 8 bit analog register\n * @hw: pointer to hardware structure\n * @reg: analog register to write\n * @val: value to write\n *\n * Performs write operation to Atlas analog register specified.\n **/\ns32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,\n\t\t\t val), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.\n * @hw: pointer to hardware structure\n *\n * Initializes the Unicast Table Arrays to zero on device load. This\n * is part of the Rx init addr execution path.\n **/\ns32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to read\n * @dev_addr: I2C bus address to read from\n * @data: value read\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,\n\t\t\tu8 *data)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,\n\t\t\t dev_addr, data), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to read\n * @dev_addr: I2C bus address to read from\n * @data: value read\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 *data)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked,\n\t\t\t (hw, byte_offset, dev_addr, data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_i2c_combined - Perform I2C read combined operation\n * @hw: pointer to the hardware structure\n * @addr: I2C bus address to read from\n * @reg: I2C device register to read from\n * @val: pointer to location to receive read value\n *\n * Returns an error code on error.\n */\ns32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined, (hw, addr,\n\t\t\t reg, val), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation\n * @hw: pointer to the hardware structure\n * @addr: I2C bus address to read from\n * @reg: I2C device register to read from\n * @val: pointer to location to receive read value\n *\n * Returns an error code on error.\n **/\ns32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,\n\t\t\t\t u16 *val)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.read_i2c_combined_unlocked,\n\t\t\t (hw, addr, reg, val),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_i2c_byte - Writes 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @dev_addr: I2C bus address to write to\n * @data: value to write\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface\n * at a specified device address.\n **/\ns32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,\n\t\t\t u8 data)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,\n\t\t\t dev_addr, data), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @dev_addr: I2C bus address to write to\n * @data: value to write\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface\n * at a specified device address.\n **/\ns32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked,\n\t\t\t (hw, byte_offset, dev_addr, data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_i2c_combined - Perform I2C write combined operation\n * @hw: pointer to the hardware structure\n * @addr: I2C bus address to write to\n * @reg: I2C device register to write to\n * @val: value to write\n *\n * Returns an error code on error.\n */\ns32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined, (hw, addr,\n\t\t\t reg, val), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation\n * @hw: pointer to the hardware structure\n * @addr: I2C bus address to write to\n * @reg: I2C device register to write to\n * @val: value to write\n *\n * Returns an error code on error.\n **/\ns32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,\n\t\t\t\t u16 val)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.write_i2c_combined_unlocked,\n\t\t\t (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface\n * @hw: pointer to hardware structure\n * @byte_offset: EEPROM byte offset to write\n * @eeprom_data: value to write\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,\n\t\t\t u8 byte_offset, u8 eeprom_data)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,\n\t\t\t (hw, byte_offset, eeprom_data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface\n * @hw: pointer to hardware structure\n * @byte_offset: EEPROM byte offset to read\n * @eeprom_data: value read\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,\n\t\t\t (hw, byte_offset, eeprom_data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_supported_physical_layer - Returns physical layer type\n * @hw: pointer to hardware structure\n *\n * Determines physical layer capabilities of the current configuration.\n **/\nu32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,\n\t\t\t (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);\n}\n\n/**\n * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics\n * @hw: pointer to hardware structure\n * @regval: bitfield to write to the Rx DMA register\n *\n * Enables the Rx DMA unit of the device.\n **/\ns32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,\n\t\t\t (hw, regval), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_disable_sec_rx_path - Stops the receive data path\n * @hw: pointer to hardware structure\n *\n * Stops the receive data path.\n **/\ns32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path,\n\t\t\t\t(hw), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_enable_sec_rx_path - Enables the receive data path\n * @hw: pointer to hardware structure\n *\n * Enables the receive data path.\n **/\ns32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,\n\t\t\t\t(hw), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to acquire\n *\n * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified\n * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\ns32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,\n\t\t\t (hw, mask), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_release_swfw_semaphore - Release SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to release\n *\n * Releases the SWFW semaphore through SW_FW_SYNC register for the specified\n * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\nvoid ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)\n{\n\tif (hw->mac.ops.release_swfw_sync)\n\t\thw->mac.ops.release_swfw_sync(hw, mask);\n}\n\n\nvoid ixgbe_disable_rx(struct ixgbe_hw *hw)\n{\n\tif (hw->mac.ops.disable_rx)\n\t\thw->mac.ops.disable_rx(hw);\n}\n\nvoid ixgbe_enable_rx(struct ixgbe_hw *hw)\n{\n\tif (hw->mac.ops.enable_rx)\n\t\thw->mac.ops.enable_rx(hw);\n}\n\n/**\n * ixgbe_set_rate_select_speed - Set module link speed\n * @hw: pointer to hardware structure\n * @speed: link speed to set\n *\n * Set module link speed via the rate select.\n */\nvoid ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)\n{\n\tif (hw->mac.ops.set_rate_select_speed)\n\t\thw->mac.ops.set_rate_select_speed(hw, speed);\n}\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_api.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _IXGBE_API_H_\n#define _IXGBE_API_H_\n\n#include \"ixgbe_type.h\"\n\nvoid ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map);\n\ns32 ixgbe_init_shared_code(struct ixgbe_hw *hw);\n\nextern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);\nextern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);\nextern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);\nextern s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw);\nextern s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw);\nextern s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw);\n\ns32 ixgbe_set_mac_type(struct ixgbe_hw *hw);\ns32 ixgbe_init_hw(struct ixgbe_hw *hw);\ns32 ixgbe_reset_hw(struct ixgbe_hw *hw);\ns32 ixgbe_start_hw(struct ixgbe_hw *hw);\nvoid ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw);\ns32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);\nenum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw);\ns32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);\ns32 ixgbe_get_bus_info(struct ixgbe_hw *hw);\nu32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);\nu32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);\ns32 ixgbe_stop_adapter(struct ixgbe_hw *hw);\ns32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num);\ns32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);\n\ns32 ixgbe_identify_phy(struct ixgbe_hw *hw);\ns32 ixgbe_reset_phy(struct ixgbe_hw *hw);\ns32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n\t\t u16 *phy_data);\ns32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n\t\t\tu16 phy_data);\n\ns32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);\ns32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw);\ns32 ixgbe_check_phy_link(struct ixgbe_hw *hw,\n\t\t\t ixgbe_link_speed *speed,\n\t\t\t bool *link_up);\ns32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,\n\t\t\t ixgbe_link_speed speed,\n\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_set_phy_power(struct ixgbe_hw *, bool on);\nvoid ixgbe_disable_tx_laser(struct ixgbe_hw *hw);\nvoid ixgbe_enable_tx_laser(struct ixgbe_hw *hw);\nvoid ixgbe_flap_tx_laser(struct ixgbe_hw *hw);\ns32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t bool *link_up, bool link_up_wait_to_complete);\ns32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t\tbool *autoneg);\ns32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);\n\ns32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);\ns32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);\ns32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,\n\t\t\t u16 words, u16 *data);\ns32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);\ns32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,\n\t\t\t u16 words, u16 *data);\n\ns32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);\ns32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);\n\ns32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);\ns32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n\t\t u32 enable_addr);\ns32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);\ns32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);\ns32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);\ns32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);\nu32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);\ns32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,\n\t\t\t u32 addr_count, ixgbe_mc_addr_itr func);\ns32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,\n\t\t\t u32 mc_addr_count, ixgbe_mc_addr_itr func,\n\t\t\t bool clear);\nvoid ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);\ns32 ixgbe_enable_mc(struct ixgbe_hw *hw);\ns32 ixgbe_disable_mc(struct ixgbe_hw *hw);\ns32 ixgbe_clear_vfta(struct ixgbe_hw *hw);\ns32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,\n\t\t u32 vind, bool vlan_on);\ns32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n\t\t bool vlan_on, bool *vfta_changed);\ns32 ixgbe_fc_enable(struct ixgbe_hw *hw);\ns32 ixgbe_setup_fc(struct ixgbe_hw *hw);\ns32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n\t\t\t u8 ver);\ns32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw);\ns32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw);\nvoid ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);\ns32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,\n\t\t\t\t u16 *firmware_version);\ns32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);\ns32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);\ns32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);\ns32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data);\nu32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);\ns32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);\ns32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw);\ns32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);\ns32 ixgbe_mng_fw_enabled(struct ixgbe_hw *hw);\ns32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);\ns32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);\ns32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,\n\t\t\t\t\tbool cloud_mode);\ns32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t union ixgbe_atr_hash_dword input,\n\t\t\t\t\t union ixgbe_atr_hash_dword common,\n\t\t\t\t\t u8 queue);\ns32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,\n\t\t\t\t union ixgbe_atr_input *input_mask, bool cloud_mode);\ns32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t union ixgbe_atr_input *input,\n\t\t\t\t\t u16 soft_id, u8 queue, bool cloud_mode);\ns32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t union ixgbe_atr_input *input,\n\t\t\t\t\t u16 soft_id);\ns32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\tunion ixgbe_atr_input *input,\n\t\t\t\t\tunion ixgbe_atr_input *mask,\n\t\t\t\t\tu16 soft_id,\n\t\t\t\t\tu8 queue,\n\t\t\t\t\tbool cloud_mode);\nvoid ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,\n\t\t\t\t\t union ixgbe_atr_input *mask);\nu32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,\n\t\t\t\t union ixgbe_atr_hash_dword common);\nbool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);\ns32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,\n\t\t\tu8 *data);\ns32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 *data);\ns32 ixgbe_read_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);\ns32 ixgbe_read_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,\n\t\t\t\t u16 *val);\ns32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,\n\t\t\t u8 data);\ns32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data);\ns32 ixgbe_write_i2c_combined(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);\ns32 ixgbe_write_i2c_combined_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg,\n\t\t\t\t u16 val);\ns32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);\ns32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);\ns32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);\ns32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);\ns32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);\nvoid ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);\ns32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n\t\t\t u16 *wwpn_prefix);\ns32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);\ns32 ixgbe_dmac_config(struct ixgbe_hw *hw);\ns32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw);\ns32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw);\ns32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee);\nvoid ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,\n\t\t\t\t unsigned int vf);\nvoid ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable,\n\t\t\t\t int vf);\ns32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\tu32 device_type, u32 *phy_data);\ns32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\tu32 device_type, u32 phy_data);\nvoid ixgbe_disable_mdd(struct ixgbe_hw *hw);\nvoid ixgbe_enable_mdd(struct ixgbe_hw *hw);\nvoid ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap);\nvoid ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf);\ns32 ixgbe_enter_lplu(struct ixgbe_hw *hw);\ns32 ixgbe_handle_lasi(struct ixgbe_hw *hw);\nvoid ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed);\nvoid ixgbe_disable_rx(struct ixgbe_hw *hw);\nvoid ixgbe_enable_rx(struct ixgbe_hw *hw);\n\n#endif /* _IXGBE_API_H_ */\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_common.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"ixgbe_common.h\"\n#include \"ixgbe_phy.h\"\n#include \"ixgbe_dcb.h\"\n#include \"ixgbe_dcb_82599.h\"\n#include \"ixgbe_api.h\"\n\nSTATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);\nSTATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);\nSTATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);\nSTATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);\nSTATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);\nSTATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,\n\t\t\t\t\tu16 count);\nSTATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);\nSTATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);\nSTATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);\nSTATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);\n\nSTATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);\nSTATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *san_mac_offset);\nSTATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data);\nSTATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data);\nSTATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t\t u16 offset);\n\n/**\n * ixgbe_init_ops_generic - Inits function ptrs\n * @hw: pointer to the hardware structure\n *\n * Initialize the function pointers.\n **/\ns32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tu32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\tDEBUGFUNC(\"ixgbe_init_ops_generic\");\n\n\t/* EEPROM */\n\teeprom->ops.init_params = ixgbe_init_eeprom_params_generic;\n\t/* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */\n\tif (eec & IXGBE_EEC_PRES) {\n\t\teeprom->ops.read = ixgbe_read_eerd_generic;\n\t\teeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;\n\t} else {\n\t\teeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;\n\t\teeprom->ops.read_buffer =\n\t\t\t\t ixgbe_read_eeprom_buffer_bit_bang_generic;\n\t}\n\teeprom->ops.write = ixgbe_write_eeprom_generic;\n\teeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;\n\teeprom->ops.validate_checksum =\n\t\t\t\t ixgbe_validate_eeprom_checksum_generic;\n\teeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;\n\teeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;\n\n\t/* MAC */\n\tmac->ops.init_hw = ixgbe_init_hw_generic;\n\tmac->ops.reset_hw = NULL;\n\tmac->ops.start_hw = ixgbe_start_hw_generic;\n\tmac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;\n\tmac->ops.get_media_type = NULL;\n\tmac->ops.get_supported_physical_layer = NULL;\n\tmac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;\n\tmac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;\n\tmac->ops.stop_adapter = ixgbe_stop_adapter_generic;\n\tmac->ops.get_bus_info = ixgbe_get_bus_info_generic;\n\tmac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;\n\tmac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;\n\tmac->ops.release_swfw_sync = ixgbe_release_swfw_sync;\n\tmac->ops.prot_autoc_read = prot_autoc_read_generic;\n\tmac->ops.prot_autoc_write = prot_autoc_write_generic;\n\n\t/* LEDs */\n\tmac->ops.led_on = ixgbe_led_on_generic;\n\tmac->ops.led_off = ixgbe_led_off_generic;\n\tmac->ops.blink_led_start = ixgbe_blink_led_start_generic;\n\tmac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;\n\n\t/* RAR, Multicast, VLAN */\n\tmac->ops.set_rar = ixgbe_set_rar_generic;\n\tmac->ops.clear_rar = ixgbe_clear_rar_generic;\n\tmac->ops.insert_mac_addr = NULL;\n\tmac->ops.set_vmdq = NULL;\n\tmac->ops.clear_vmdq = NULL;\n\tmac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;\n\tmac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;\n\tmac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;\n\tmac->ops.enable_mc = ixgbe_enable_mc_generic;\n\tmac->ops.disable_mc = ixgbe_disable_mc_generic;\n\tmac->ops.clear_vfta = NULL;\n\tmac->ops.set_vfta = NULL;\n\tmac->ops.set_vlvf = NULL;\n\tmac->ops.init_uta_tables = NULL;\n\tmac->ops.enable_rx = ixgbe_enable_rx_generic;\n\tmac->ops.disable_rx = ixgbe_disable_rx_generic;\n\n\t/* Flow Control */\n\tmac->ops.fc_enable = ixgbe_fc_enable_generic;\n\tmac->ops.setup_fc = ixgbe_setup_fc_generic;\n\n\t/* Link */\n\tmac->ops.get_link_capabilities = NULL;\n\tmac->ops.setup_link = NULL;\n\tmac->ops.check_link = NULL;\n\tmac->ops.dmac_config = NULL;\n\tmac->ops.dmac_update_tcs = NULL;\n\tmac->ops.dmac_config_tcs = NULL;\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation\n * of flow control\n * @hw: pointer to hardware structure\n *\n * This function returns true if the device supports flow control\n * autonegotiation, and false if it does not.\n *\n **/\nbool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)\n{\n\tbool supported = false;\n\tixgbe_link_speed speed;\n\tbool link_up;\n\n\tDEBUGFUNC(\"ixgbe_device_supports_autoneg_fc\");\n\n\tswitch (hw->phy.media_type) {\n\tcase ixgbe_media_type_fiber_qsfp:\n\tcase ixgbe_media_type_fiber:\n\t\thw->mac.ops.check_link(hw, &speed, &link_up, false);\n\t\t/* if link is down, assume supported */\n\t\tif (link_up)\n\t\t\tsupported = speed == IXGBE_LINK_SPEED_1GB_FULL ?\n\t\t\t\ttrue : false;\n\t\telse\n\t\t\tsupported = true;\n\t\tbreak;\n\tcase ixgbe_media_type_backplane:\n\t\tsupported = true;\n\t\tbreak;\n\tcase ixgbe_media_type_copper:\n\t\t/* only some copper devices support flow control autoneg */\n\t\tswitch (hw->device_id) {\n\t\tcase IXGBE_DEV_ID_82599_T3_LOM:\n\t\tcase IXGBE_DEV_ID_X540T:\n\t\tcase IXGBE_DEV_ID_X540T1:\n\t\tcase IXGBE_DEV_ID_X550T:\n\t\tcase IXGBE_DEV_ID_X550EM_X_10G_T:\n\t\t\tsupported = true;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tsupported = false;\n\t\t}\n\tdefault:\n\t\tbreak;\n\t}\n\n\tERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,\n\t\t \"Device %x does not support flow control autoneg\",\n\t\t hw->device_id);\n\treturn supported;\n}\n\n/**\n * ixgbe_setup_fc_generic - Set up flow control\n * @hw: pointer to hardware structure\n *\n * Called at init time to set up flow control.\n **/\ns32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = IXGBE_SUCCESS;\n\tu32 reg = 0, reg_bp = 0;\n\tu16 reg_cu = 0;\n\tbool locked = false;\n\n\tDEBUGFUNC(\"ixgbe_setup_fc_generic\");\n\n\t/* Validate the requested mode */\n\tif (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {\n\t\tERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,\n\t\t\t \"ixgbe_fc_rx_pause not valid in strict IEEE mode\\n\");\n\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * 10gig parts do not have a word in the EEPROM to determine the\n\t * default flow control setting, so we explicitly set it to full.\n\t */\n\tif (hw->fc.requested_mode == ixgbe_fc_default)\n\t\thw->fc.requested_mode = ixgbe_fc_full;\n\n\t/*\n\t * Set up the 1G and 10G flow control advertisement registers so the\n\t * HW will be able to do fc autoneg once the cable is plugged in. If\n\t * we link at 10G, the 1G advertisement is harmless and vice versa.\n\t */\n\tswitch (hw->phy.media_type) {\n\tcase ixgbe_media_type_backplane:\n\t\t/* some MAC's need RMW protection on AUTOC */\n\t\tret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);\n\t\tif (ret_val != IXGBE_SUCCESS)\n\t\t\tgoto out;\n\n\t\t/* only backplane uses autoc so fall though */\n\tcase ixgbe_media_type_fiber_qsfp:\n\tcase ixgbe_media_type_fiber:\n\t\treg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);\n\n\t\tbreak;\n\tcase ixgbe_media_type_copper:\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/*\n\t * The possible values of fc.requested_mode are:\n\t * 0: Flow control is completely disabled\n\t * 1: Rx flow control is enabled (we can receive pause frames,\n\t * but not send pause frames).\n\t * 2: Tx flow control is enabled (we can send pause frames but\n\t * we do not support receiving pause frames).\n\t * 3: Both Rx and Tx flow control (symmetric) are enabled.\n\t * other: Invalid.\n\t */\n\tswitch (hw->fc.requested_mode) {\n\tcase ixgbe_fc_none:\n\t\t/* Flow control completely disabled by software override. */\n\t\treg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);\n\t\tif (hw->phy.media_type == ixgbe_media_type_backplane)\n\t\t\treg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |\n\t\t\t\t IXGBE_AUTOC_ASM_PAUSE);\n\t\telse if (hw->phy.media_type == ixgbe_media_type_copper)\n\t\t\treg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);\n\t\tbreak;\n\tcase ixgbe_fc_tx_pause:\n\t\t/*\n\t\t * Tx Flow control is enabled, and Rx Flow control is\n\t\t * disabled by software override.\n\t\t */\n\t\treg |= IXGBE_PCS1GANA_ASM_PAUSE;\n\t\treg &= ~IXGBE_PCS1GANA_SYM_PAUSE;\n\t\tif (hw->phy.media_type == ixgbe_media_type_backplane) {\n\t\t\treg_bp |= IXGBE_AUTOC_ASM_PAUSE;\n\t\t\treg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;\n\t\t} else if (hw->phy.media_type == ixgbe_media_type_copper) {\n\t\t\treg_cu |= IXGBE_TAF_ASM_PAUSE;\n\t\t\treg_cu &= ~IXGBE_TAF_SYM_PAUSE;\n\t\t}\n\t\tbreak;\n\tcase ixgbe_fc_rx_pause:\n\t\t/*\n\t\t * Rx Flow control is enabled and Tx Flow control is\n\t\t * disabled by software override. Since there really\n\t\t * isn't a way to advertise that we are capable of RX\n\t\t * Pause ONLY, we will advertise that we support both\n\t\t * symmetric and asymmetric Rx PAUSE, as such we fall\n\t\t * through to the fc_full statement. Later, we will\n\t\t * disable the adapter's ability to send PAUSE frames.\n\t\t */\n\tcase ixgbe_fc_full:\n\t\t/* Flow control (both Rx and Tx) is enabled by SW override. */\n\t\treg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;\n\t\tif (hw->phy.media_type == ixgbe_media_type_backplane)\n\t\t\treg_bp |= IXGBE_AUTOC_SYM_PAUSE |\n\t\t\t\t IXGBE_AUTOC_ASM_PAUSE;\n\t\telse if (hw->phy.media_type == ixgbe_media_type_copper)\n\t\t\treg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;\n\t\tbreak;\n\tdefault:\n\t\tERROR_REPORT1(IXGBE_ERROR_ARGUMENT,\n\t\t\t \"Flow control param set incorrectly\\n\");\n\t\tret_val = IXGBE_ERR_CONFIG;\n\t\tgoto out;\n\t\tbreak;\n\t}\n\n\tif (hw->mac.type < ixgbe_mac_X540) {\n\t\t/*\n\t\t * Enable auto-negotiation between the MAC & PHY;\n\t\t * the MAC will advertise clause 37 flow control.\n\t\t */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);\n\t\treg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);\n\n\t\t/* Disable AN timeout */\n\t\tif (hw->fc.strict_ieee)\n\t\t\treg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);\n\t\tDEBUGOUT1(\"Set up FC; PCS1GLCTL = 0x%08X\\n\", reg);\n\t}\n\n\t/*\n\t * AUTOC restart handles negotiation of 1G and 10G on backplane\n\t * and copper. There is no need to set the PCS1GCTL register.\n\t *\n\t */\n\tif (hw->phy.media_type == ixgbe_media_type_backplane) {\n\t\treg_bp |= IXGBE_AUTOC_AN_RESTART;\n\t\tret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&\n\t\t (ixgbe_device_supports_autoneg_fc(hw))) {\n\t\thw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);\n\t}\n\n\tDEBUGOUT1(\"Set up FC; PCS1GLCTL = 0x%08X\\n\", reg);\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx\n * @hw: pointer to hardware structure\n *\n * Starts the hardware by filling the bus info structure and media type, clears\n * all on chip counters, initializes receive address registers, multicast\n * table, VLAN filter table, calls routine to set up link and flow control\n * settings, and leaves transmit and receive units disabled and uninitialized\n **/\ns32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)\n{\n\ts32 ret_val;\n\tu32 ctrl_ext;\n\n\tDEBUGFUNC(\"ixgbe_start_hw_generic\");\n\n\t/* Set the media type */\n\thw->phy.media_type = hw->mac.ops.get_media_type(hw);\n\n\t/* PHY ops initialization must be done in reset_hw() */\n\n\t/* Clear the VLAN filter table */\n\thw->mac.ops.clear_vfta(hw);\n\n\t/* Clear statistics registers */\n\thw->mac.ops.clear_hw_cntrs(hw);\n\n\t/* Set No Snoop Disable */\n\tctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);\n\tctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Setup flow control */\n\tret_val = ixgbe_setup_fc(hw);\n\tif (ret_val != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\t/* Clear adapter stopped flag */\n\thw->adapter_stopped = false;\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_start_hw_gen2 - Init sequence for common device family\n * @hw: pointer to hw structure\n *\n * Performs the init sequence common to the second generation\n * of 10 GbE devices.\n * Devices in the second generation:\n * 82599\n * X540\n **/\ns32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)\n{\n\tu32 i;\n\tu32 regval;\n\n\t/* Clear the rate limiters */\n\tfor (i = 0; i < hw->mac.max_tx_queues; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);\n\t}\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Disable relaxed ordering */\n\tfor (i = 0; i < hw->mac.max_tx_queues; i++) {\n\t\tregval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));\n\t\tregval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);\n\t}\n\n\tfor (i = 0; i < hw->mac.max_rx_queues; i++) {\n\t\tregval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));\n\t\tregval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |\n\t\t\t IXGBE_DCA_RXCTRL_HEAD_WRO_EN);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_init_hw_generic - Generic hardware initialization\n * @hw: pointer to hardware structure\n *\n * Initialize the hardware by resetting the hardware, filling the bus info\n * structure and media type, clears all on chip counters, initializes receive\n * address registers, multicast table, VLAN filter table, calls routine to set\n * up link and flow control settings, and leaves transmit and receive units\n * disabled and uninitialized\n **/\ns32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_init_hw_generic\");\n\n\t/* Reset the hardware */\n\tstatus = hw->mac.ops.reset_hw(hw);\n\n\tif (status == IXGBE_SUCCESS) {\n\t\t/* Start the HW */\n\t\tstatus = hw->mac.ops.start_hw(hw);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters\n * @hw: pointer to hardware structure\n *\n * Clears all hardware statistics counters by reading them from the hardware\n * Statistics counters are clear on read.\n **/\ns32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)\n{\n\tu16 i = 0;\n\n\tDEBUGFUNC(\"ixgbe_clear_hw_cntrs_generic\");\n\n\tIXGBE_READ_REG(hw, IXGBE_CRCERRS);\n\tIXGBE_READ_REG(hw, IXGBE_ILLERRC);\n\tIXGBE_READ_REG(hw, IXGBE_ERRBC);\n\tIXGBE_READ_REG(hw, IXGBE_MSPDC);\n\tfor (i = 0; i < 8; i++)\n\t\tIXGBE_READ_REG(hw, IXGBE_MPC(i));\n\n\tIXGBE_READ_REG(hw, IXGBE_MLFC);\n\tIXGBE_READ_REG(hw, IXGBE_MRFC);\n\tIXGBE_READ_REG(hw, IXGBE_RLEC);\n\tIXGBE_READ_REG(hw, IXGBE_LXONTXC);\n\tIXGBE_READ_REG(hw, IXGBE_LXOFFTXC);\n\tif (hw->mac.type >= ixgbe_mac_82599EB) {\n\t\tIXGBE_READ_REG(hw, IXGBE_LXONRXCNT);\n\t\tIXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);\n\t} else {\n\t\tIXGBE_READ_REG(hw, IXGBE_LXONRXC);\n\t\tIXGBE_READ_REG(hw, IXGBE_LXOFFRXC);\n\t}\n\n\tfor (i = 0; i < 8; i++) {\n\t\tIXGBE_READ_REG(hw, IXGBE_PXONTXC(i));\n\t\tIXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));\n\t\tif (hw->mac.type >= ixgbe_mac_82599EB) {\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));\n\t\t} else {\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PXONRXC(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));\n\t\t}\n\t}\n\tif (hw->mac.type >= ixgbe_mac_82599EB)\n\t\tfor (i = 0; i < 8; i++)\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));\n\tIXGBE_READ_REG(hw, IXGBE_PRC64);\n\tIXGBE_READ_REG(hw, IXGBE_PRC127);\n\tIXGBE_READ_REG(hw, IXGBE_PRC255);\n\tIXGBE_READ_REG(hw, IXGBE_PRC511);\n\tIXGBE_READ_REG(hw, IXGBE_PRC1023);\n\tIXGBE_READ_REG(hw, IXGBE_PRC1522);\n\tIXGBE_READ_REG(hw, IXGBE_GPRC);\n\tIXGBE_READ_REG(hw, IXGBE_BPRC);\n\tIXGBE_READ_REG(hw, IXGBE_MPRC);\n\tIXGBE_READ_REG(hw, IXGBE_GPTC);\n\tIXGBE_READ_REG(hw, IXGBE_GORCL);\n\tIXGBE_READ_REG(hw, IXGBE_GORCH);\n\tIXGBE_READ_REG(hw, IXGBE_GOTCL);\n\tIXGBE_READ_REG(hw, IXGBE_GOTCH);\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\tfor (i = 0; i < 8; i++)\n\t\t\tIXGBE_READ_REG(hw, IXGBE_RNBC(i));\n\tIXGBE_READ_REG(hw, IXGBE_RUC);\n\tIXGBE_READ_REG(hw, IXGBE_RFC);\n\tIXGBE_READ_REG(hw, IXGBE_ROC);\n\tIXGBE_READ_REG(hw, IXGBE_RJC);\n\tIXGBE_READ_REG(hw, IXGBE_MNGPRC);\n\tIXGBE_READ_REG(hw, IXGBE_MNGPDC);\n\tIXGBE_READ_REG(hw, IXGBE_MNGPTC);\n\tIXGBE_READ_REG(hw, IXGBE_TORL);\n\tIXGBE_READ_REG(hw, IXGBE_TORH);\n\tIXGBE_READ_REG(hw, IXGBE_TPR);\n\tIXGBE_READ_REG(hw, IXGBE_TPT);\n\tIXGBE_READ_REG(hw, IXGBE_PTC64);\n\tIXGBE_READ_REG(hw, IXGBE_PTC127);\n\tIXGBE_READ_REG(hw, IXGBE_PTC255);\n\tIXGBE_READ_REG(hw, IXGBE_PTC511);\n\tIXGBE_READ_REG(hw, IXGBE_PTC1023);\n\tIXGBE_READ_REG(hw, IXGBE_PTC1522);\n\tIXGBE_READ_REG(hw, IXGBE_MPTC);\n\tIXGBE_READ_REG(hw, IXGBE_BPTC);\n\tfor (i = 0; i < 16; i++) {\n\t\tIXGBE_READ_REG(hw, IXGBE_QPRC(i));\n\t\tIXGBE_READ_REG(hw, IXGBE_QPTC(i));\n\t\tif (hw->mac.type >= ixgbe_mac_82599EB) {\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBRC_L(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBRC_H(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBTC_L(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBTC_H(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QPRDC(i));\n\t\t} else {\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBRC(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBTC(i));\n\t\t}\n\t}\n\n\tif (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {\n\t\tif (hw->phy.id == 0)\n\t\t\tixgbe_identify_phy(hw);\n\t\thw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,\n\t\t\t\t IXGBE_MDIO_PCS_DEV_TYPE, &i);\n\t\thw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,\n\t\t\t\t IXGBE_MDIO_PCS_DEV_TYPE, &i);\n\t\thw->phy.ops.read_reg(hw, IXGBE_LDPCECL,\n\t\t\t\t IXGBE_MDIO_PCS_DEV_TYPE, &i);\n\t\thw->phy.ops.read_reg(hw, IXGBE_LDPCECH,\n\t\t\t\t IXGBE_MDIO_PCS_DEV_TYPE, &i);\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_read_pba_string_generic - Reads part number string from EEPROM\n * @hw: pointer to hardware structure\n * @pba_num: stores the part number string from the EEPROM\n * @pba_num_size: part number string buffer length\n *\n * Reads the part number string from the EEPROM.\n **/\ns32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,\n\t\t\t\t u32 pba_num_size)\n{\n\ts32 ret_val;\n\tu16 data;\n\tu16 pba_ptr;\n\tu16 offset;\n\tu16 length;\n\n\tDEBUGFUNC(\"ixgbe_read_pba_string_generic\");\n\n\tif (pba_num == NULL) {\n\t\tDEBUGOUT(\"PBA string buffer was null\\n\");\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\tret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\t/*\n\t * if data is not ptr guard the PBA must be in legacy format which\n\t * means pba_ptr is actually our second data word for the PBA number\n\t * and we can decode it into an ascii string\n\t */\n\tif (data != IXGBE_PBANUM_PTR_GUARD) {\n\t\tDEBUGOUT(\"NVM PBA number is not stored as string\\n\");\n\n\t\t/* we will need 11 characters to store the PBA */\n\t\tif (pba_num_size < 11) {\n\t\t\tDEBUGOUT(\"PBA string buffer too small\\n\");\n\t\t\treturn IXGBE_ERR_NO_SPACE;\n\t\t}\n\n\t\t/* extract hex string from data and pba_ptr */\n\t\tpba_num[0] = (data >> 12) & 0xF;\n\t\tpba_num[1] = (data >> 8) & 0xF;\n\t\tpba_num[2] = (data >> 4) & 0xF;\n\t\tpba_num[3] = data & 0xF;\n\t\tpba_num[4] = (pba_ptr >> 12) & 0xF;\n\t\tpba_num[5] = (pba_ptr >> 8) & 0xF;\n\t\tpba_num[6] = '-';\n\t\tpba_num[7] = 0;\n\t\tpba_num[8] = (pba_ptr >> 4) & 0xF;\n\t\tpba_num[9] = pba_ptr & 0xF;\n\n\t\t/* put a null character on the end of our string */\n\t\tpba_num[10] = '\\0';\n\n\t\t/* switch all the data but the '-' to hex char */\n\t\tfor (offset = 0; offset < 10; offset++) {\n\t\t\tif (pba_num[offset] < 0xA)\n\t\t\t\tpba_num[offset] += '0';\n\t\t\telse if (pba_num[offset] < 0x10)\n\t\t\t\tpba_num[offset] += 'A' - 0xA;\n\t\t}\n\n\t\treturn IXGBE_SUCCESS;\n\t}\n\n\tret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif (length == 0xFFFF || length == 0) {\n\t\tDEBUGOUT(\"NVM PBA number section invalid length\\n\");\n\t\treturn IXGBE_ERR_PBA_SECTION;\n\t}\n\n\t/* check if pba_num buffer is big enough */\n\tif (pba_num_size < (((u32)length * 2) - 1)) {\n\t\tDEBUGOUT(\"PBA string buffer too small\\n\");\n\t\treturn IXGBE_ERR_NO_SPACE;\n\t}\n\n\t/* trim pba length from start of string */\n\tpba_ptr++;\n\tlength--;\n\n\tfor (offset = 0; offset < length; offset++) {\n\t\tret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t\tpba_num[offset * 2] = (u8)(data >> 8);\n\t\tpba_num[(offset * 2) + 1] = (u8)(data & 0xFF);\n\t}\n\tpba_num[offset * 2] = '\\0';\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_read_pba_num_generic - Reads part number from EEPROM\n * @hw: pointer to hardware structure\n * @pba_num: stores the part number from the EEPROM\n *\n * Reads the part number from the EEPROM.\n **/\ns32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)\n{\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"ixgbe_read_pba_num_generic\");\n\n\tret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t} else if (data == IXGBE_PBANUM_PTR_GUARD) {\n\t\tDEBUGOUT(\"NVM Not supported\\n\");\n\t\treturn IXGBE_NOT_IMPLEMENTED;\n\t}\n\t*pba_num = (u32)(data << 16);\n\n\tret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\t*pba_num |= data;\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_read_pba_raw\n * @hw: pointer to the HW structure\n * @eeprom_buf: optional pointer to EEPROM image\n * @eeprom_buf_size: size of EEPROM image in words\n * @max_pba_block_size: PBA block size limit\n * @pba: pointer to output PBA structure\n *\n * Reads PBA from EEPROM image when eeprom_buf is not NULL.\n * Reads PBA from physical EEPROM device when eeprom_buf is NULL.\n *\n **/\ns32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,\n\t\t u32 eeprom_buf_size, u16 max_pba_block_size,\n\t\t struct ixgbe_pba *pba)\n{\n\ts32 ret_val;\n\tu16 pba_block_size;\n\n\tif (pba == NULL)\n\t\treturn IXGBE_ERR_PARAM;\n\n\tif (eeprom_buf == NULL) {\n\t\tret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,\n\t\t\t\t\t\t &pba->word[0]);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\tif (eeprom_buf_size > IXGBE_PBANUM1_PTR) {\n\t\t\tpba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];\n\t\t\tpba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];\n\t\t} else {\n\t\t\treturn IXGBE_ERR_PARAM;\n\t\t}\n\t}\n\n\tif (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {\n\t\tif (pba->pba_block == NULL)\n\t\t\treturn IXGBE_ERR_PARAM;\n\n\t\tret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,\n\t\t\t\t\t\t eeprom_buf_size,\n\t\t\t\t\t\t &pba_block_size);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (pba_block_size > max_pba_block_size)\n\t\t\treturn IXGBE_ERR_PARAM;\n\n\t\tif (eeprom_buf == NULL) {\n\t\t\tret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],\n\t\t\t\t\t\t\t pba_block_size,\n\t\t\t\t\t\t\t pba->pba_block);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t} else {\n\t\t\tif (eeprom_buf_size > (u32)(pba->word[1] +\n\t\t\t\t\t pba_block_size)) {\n\t\t\t\tmemcpy(pba->pba_block,\n\t\t\t\t &eeprom_buf[pba->word[1]],\n\t\t\t\t pba_block_size * sizeof(u16));\n\t\t\t} else {\n\t\t\t\treturn IXGBE_ERR_PARAM;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_write_pba_raw\n * @hw: pointer to the HW structure\n * @eeprom_buf: optional pointer to EEPROM image\n * @eeprom_buf_size: size of EEPROM image in words\n * @pba: pointer to PBA structure\n *\n * Writes PBA to EEPROM image when eeprom_buf is not NULL.\n * Writes PBA to physical EEPROM device when eeprom_buf is NULL.\n *\n **/\ns32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,\n\t\t\tu32 eeprom_buf_size, struct ixgbe_pba *pba)\n{\n\ts32 ret_val;\n\n\tif (pba == NULL)\n\t\treturn IXGBE_ERR_PARAM;\n\n\tif (eeprom_buf == NULL) {\n\t\tret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,\n\t\t\t\t\t\t &pba->word[0]);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\tif (eeprom_buf_size > IXGBE_PBANUM1_PTR) {\n\t\t\teeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];\n\t\t\teeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];\n\t\t} else {\n\t\t\treturn IXGBE_ERR_PARAM;\n\t\t}\n\t}\n\n\tif (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {\n\t\tif (pba->pba_block == NULL)\n\t\t\treturn IXGBE_ERR_PARAM;\n\n\t\tif (eeprom_buf == NULL) {\n\t\t\tret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],\n\t\t\t\t\t\t\t pba->pba_block[0],\n\t\t\t\t\t\t\t pba->pba_block);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t} else {\n\t\t\tif (eeprom_buf_size > (u32)(pba->word[1] +\n\t\t\t\t\t pba->pba_block[0])) {\n\t\t\t\tmemcpy(&eeprom_buf[pba->word[1]],\n\t\t\t\t pba->pba_block,\n\t\t\t\t pba->pba_block[0] * sizeof(u16));\n\t\t\t} else {\n\t\t\t\treturn IXGBE_ERR_PARAM;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_get_pba_block_size\n * @hw: pointer to the HW structure\n * @eeprom_buf: optional pointer to EEPROM image\n * @eeprom_buf_size: size of EEPROM image in words\n * @pba_data_size: pointer to output variable\n *\n * Returns the size of the PBA block in words. Function operates on EEPROM\n * image if the eeprom_buf pointer is not NULL otherwise it accesses physical\n * EEPROM device.\n *\n **/\ns32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,\n\t\t\t u32 eeprom_buf_size, u16 *pba_block_size)\n{\n\ts32 ret_val;\n\tu16 pba_word[2];\n\tu16 length;\n\n\tDEBUGFUNC(\"ixgbe_get_pba_block_size\");\n\n\tif (eeprom_buf == NULL) {\n\t\tret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,\n\t\t\t\t\t\t &pba_word[0]);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\tif (eeprom_buf_size > IXGBE_PBANUM1_PTR) {\n\t\t\tpba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];\n\t\t\tpba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];\n\t\t} else {\n\t\t\treturn IXGBE_ERR_PARAM;\n\t\t}\n\t}\n\n\tif (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {\n\t\tif (eeprom_buf == NULL) {\n\t\t\tret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,\n\t\t\t\t\t\t &length);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t} else {\n\t\t\tif (eeprom_buf_size > pba_word[1])\n\t\t\t\tlength = eeprom_buf[pba_word[1] + 0];\n\t\t\telse\n\t\t\t\treturn IXGBE_ERR_PARAM;\n\t\t}\n\n\t\tif (length == 0xFFFF || length == 0)\n\t\t\treturn IXGBE_ERR_PBA_SECTION;\n\t} else {\n\t\t/* PBA number in legacy format, there is no PBA Block. */\n\t\tlength = 0;\n\t}\n\n\tif (pba_block_size != NULL)\n\t\t*pba_block_size = length;\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_get_mac_addr_generic - Generic get MAC address\n * @hw: pointer to hardware structure\n * @mac_addr: Adapter MAC address\n *\n * Reads the adapter's MAC address from first Receive Address Register (RAR0)\n * A reset of the adapter must be performed prior to calling this function\n * in order for the MAC address to have been loaded from the EEPROM into RAR0\n **/\ns32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)\n{\n\tu32 rar_high;\n\tu32 rar_low;\n\tu16 i;\n\n\tDEBUGFUNC(\"ixgbe_get_mac_addr_generic\");\n\n\trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));\n\trar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));\n\n\tfor (i = 0; i < 4; i++)\n\t\tmac_addr[i] = (u8)(rar_low >> (i*8));\n\n\tfor (i = 0; i < 2; i++)\n\t\tmac_addr[i+4] = (u8)(rar_high >> (i*8));\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_set_pci_config_data_generic - Generic store PCI bus info\n * @hw: pointer to hardware structure\n * @link_status: the link status returned by the PCI config space\n *\n * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure\n **/\nvoid ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\n\tif (hw->bus.type == ixgbe_bus_type_unknown)\n\t\thw->bus.type = ixgbe_bus_type_pci_express;\n\n\tswitch (link_status & IXGBE_PCI_LINK_WIDTH) {\n\tcase IXGBE_PCI_LINK_WIDTH_1:\n\t\thw->bus.width = ixgbe_bus_width_pcie_x1;\n\t\tbreak;\n\tcase IXGBE_PCI_LINK_WIDTH_2:\n\t\thw->bus.width = ixgbe_bus_width_pcie_x2;\n\t\tbreak;\n\tcase IXGBE_PCI_LINK_WIDTH_4:\n\t\thw->bus.width = ixgbe_bus_width_pcie_x4;\n\t\tbreak;\n\tcase IXGBE_PCI_LINK_WIDTH_8:\n\t\thw->bus.width = ixgbe_bus_width_pcie_x8;\n\t\tbreak;\n\tdefault:\n\t\thw->bus.width = ixgbe_bus_width_unknown;\n\t\tbreak;\n\t}\n\n\tswitch (link_status & IXGBE_PCI_LINK_SPEED) {\n\tcase IXGBE_PCI_LINK_SPEED_2500:\n\t\thw->bus.speed = ixgbe_bus_speed_2500;\n\t\tbreak;\n\tcase IXGBE_PCI_LINK_SPEED_5000:\n\t\thw->bus.speed = ixgbe_bus_speed_5000;\n\t\tbreak;\n\tcase IXGBE_PCI_LINK_SPEED_8000:\n\t\thw->bus.speed = ixgbe_bus_speed_8000;\n\t\tbreak;\n\tdefault:\n\t\thw->bus.speed = ixgbe_bus_speed_unknown;\n\t\tbreak;\n\t}\n\n\tmac->ops.set_lan_id(hw);\n}\n\n/**\n * ixgbe_get_bus_info_generic - Generic set PCI bus info\n * @hw: pointer to hardware structure\n *\n * Gets the PCI bus info (speed, width, type) then calls helper function to\n * store this data within the ixgbe_hw structure.\n **/\ns32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)\n{\n\tu16 link_status;\n\n\tDEBUGFUNC(\"ixgbe_get_bus_info_generic\");\n\n\t/* Get the negotiated link width and speed from PCI config space */\n\tlink_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);\n\n\tixgbe_set_pci_config_data_generic(hw, link_status);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices\n * @hw: pointer to the HW structure\n *\n * Determines the LAN function id by reading memory-mapped registers\n * and swaps the port value if requested.\n **/\nvoid ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_bus_info *bus = &hw->bus;\n\tu32 reg;\n\n\tDEBUGFUNC(\"ixgbe_set_lan_id_multi_port_pcie\");\n\n\treg = IXGBE_READ_REG(hw, IXGBE_STATUS);\n\tbus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;\n\tbus->lan_id = bus->func;\n\n\t/* check for a port swap */\n\treg = IXGBE_READ_REG(hw, IXGBE_FACTPS);\n\tif (reg & IXGBE_FACTPS_LFS)\n\t\tbus->func ^= 0x1;\n}\n\n/**\n * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units\n * @hw: pointer to hardware structure\n *\n * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,\n * disables transmit and receive units. The adapter_stopped flag is used by\n * the shared code and drivers to determine if the adapter is in a stopped\n * state and should not touch the hardware.\n **/\ns32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)\n{\n\tu32 reg_val;\n\tu16 i;\n\n\tDEBUGFUNC(\"ixgbe_stop_adapter_generic\");\n\n\t/*\n\t * Set the adapter_stopped flag so other driver functions stop touching\n\t * the hardware\n\t */\n\thw->adapter_stopped = true;\n\n\t/* Disable the receive unit */\n\tixgbe_disable_rx(hw);\n\n\t/* Clear interrupt mask to stop interrupts from being generated */\n\tIXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);\n\n\t/* Clear any pending interrupts, flush previous writes */\n\tIXGBE_READ_REG(hw, IXGBE_EICR);\n\n\t/* Disable the transmit unit. Each queue must be disabled. */\n\tfor (i = 0; i < hw->mac.max_tx_queues; i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);\n\n\t/* Disable the receive unit by stopping each queue */\n\tfor (i = 0; i < hw->mac.max_rx_queues; i++) {\n\t\treg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));\n\t\treg_val &= ~IXGBE_RXDCTL_ENABLE;\n\t\treg_val |= IXGBE_RXDCTL_SWFLSH;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);\n\t}\n\n\t/* flush all queues disables */\n\tIXGBE_WRITE_FLUSH(hw);\n\tmsec_delay(2);\n\n\t/*\n\t * Prevent the PCI-E bus from hanging by disabling PCI-E master\n\t * access and verify no pending requests\n\t */\n\treturn ixgbe_disable_pcie_master(hw);\n}\n\n/**\n * ixgbe_led_on_generic - Turns on the software controllable LEDs.\n * @hw: pointer to hardware structure\n * @index: led number to turn on\n **/\ns32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)\n{\n\tu32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\n\tDEBUGFUNC(\"ixgbe_led_on_generic\");\n\n\t/* To turn on the LED, set mode to ON. */\n\tled_reg &= ~IXGBE_LED_MODE_MASK(index);\n\tled_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_led_off_generic - Turns off the software controllable LEDs.\n * @hw: pointer to hardware structure\n * @index: led number to turn off\n **/\ns32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)\n{\n\tu32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\n\tDEBUGFUNC(\"ixgbe_led_off_generic\");\n\n\t/* To turn off the LED, set mode to OFF. */\n\tled_reg &= ~IXGBE_LED_MODE_MASK(index);\n\tled_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_init_eeprom_params_generic - Initialize EEPROM params\n * @hw: pointer to hardware structure\n *\n * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n * ixgbe_hw struct in order to set up EEPROM access.\n **/\ns32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\tu32 eec;\n\tu16 eeprom_size;\n\n\tDEBUGFUNC(\"ixgbe_init_eeprom_params_generic\");\n\n\tif (eeprom->type == ixgbe_eeprom_uninitialized) {\n\t\teeprom->type = ixgbe_eeprom_none;\n\t\t/* Set default semaphore delay to 10ms which is a well\n\t\t * tested value */\n\t\teeprom->semaphore_delay = 10;\n\t\t/* Clear EEPROM page size, it will be initialized as needed */\n\t\teeprom->word_page_size = 0;\n\n\t\t/*\n\t\t * Check for EEPROM present first.\n\t\t * If not present leave as none\n\t\t */\n\t\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\t\tif (eec & IXGBE_EEC_PRES) {\n\t\t\teeprom->type = ixgbe_eeprom_spi;\n\n\t\t\t/*\n\t\t\t * SPI EEPROM is assumed here. This code would need to\n\t\t\t * change if a future EEPROM is not SPI.\n\t\t\t */\n\t\t\teeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>\n\t\t\t\t\t IXGBE_EEC_SIZE_SHIFT);\n\t\t\teeprom->word_size = 1 << (eeprom_size +\n\t\t\t\t\t IXGBE_EEPROM_WORD_SIZE_SHIFT);\n\t\t}\n\n\t\tif (eec & IXGBE_EEC_ADDR_SIZE)\n\t\t\teeprom->address_bits = 16;\n\t\telse\n\t\t\teeprom->address_bits = 8;\n\t\tDEBUGOUT3(\"Eeprom params: type = %d, size = %d, address bits: \"\n\t\t\t \"%d\\n\", eeprom->type, eeprom->word_size,\n\t\t\t eeprom->address_bits);\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to write\n * @words: number of word(s)\n * @data: 16 bit word(s) to write to EEPROM\n *\n * Reads 16 bit word(s) from EEPROM through bit-bang method\n **/\ns32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu16 i, count;\n\n\tDEBUGFUNC(\"ixgbe_write_eeprom_buffer_bit_bang_generic\");\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (words == 0) {\n\t\tstatus = IXGBE_ERR_INVALID_ARGUMENT;\n\t\tgoto out;\n\t}\n\n\tif (offset + words > hw->eeprom.word_size) {\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * The EEPROM page size cannot be queried from the chip. We do lazy\n\t * initialization. It is worth to do that when we write large buffer.\n\t */\n\tif ((hw->eeprom.word_page_size == 0) &&\n\t (words > IXGBE_EEPROM_PAGE_SIZE_MAX))\n\t\tixgbe_detect_eeprom_page_size_generic(hw, offset);\n\n\t/*\n\t * We cannot hold synchronization semaphores for too long\n\t * to avoid other entity starvation. However it is more efficient\n\t * to read in bursts than synchronizing access for each word.\n\t */\n\tfor (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {\n\t\tcount = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?\n\t\t\tIXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);\n\t\tstatus = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,\n\t\t\t\t\t\t\t count, &data[i]);\n\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tbreak;\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be written to\n * @words: number of word(s)\n * @data: 16 bit word(s) to be written to the EEPROM\n *\n * If ixgbe_eeprom_update_checksum is not called after this function, the\n * EEPROM will most likely contain an invalid checksum.\n **/\nSTATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data)\n{\n\ts32 status;\n\tu16 word;\n\tu16 page_size;\n\tu16 i;\n\tu8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;\n\n\tDEBUGFUNC(\"ixgbe_write_eeprom_buffer_bit_bang\");\n\n\t/* Prepare the EEPROM for writing */\n\tstatus = ixgbe_acquire_eeprom(hw);\n\n\tif (status == IXGBE_SUCCESS) {\n\t\tif (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {\n\t\t\tixgbe_release_eeprom(hw);\n\t\t\tstatus = IXGBE_ERR_EEPROM;\n\t\t}\n\t}\n\n\tif (status == IXGBE_SUCCESS) {\n\t\tfor (i = 0; i < words; i++) {\n\t\t\tixgbe_standby_eeprom(hw);\n\n\t\t\t/* Send the WRITE ENABLE command (8 bit opcode ) */\n\t\t\tixgbe_shift_out_eeprom_bits(hw,\n\t\t\t\t\t\t IXGBE_EEPROM_WREN_OPCODE_SPI,\n\t\t\t\t\t\t IXGBE_EEPROM_OPCODE_BITS);\n\n\t\t\tixgbe_standby_eeprom(hw);\n\n\t\t\t/*\n\t\t\t * Some SPI eeproms use the 8th address bit embedded\n\t\t\t * in the opcode\n\t\t\t */\n\t\t\tif ((hw->eeprom.address_bits == 8) &&\n\t\t\t ((offset + i) >= 128))\n\t\t\t\twrite_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;\n\n\t\t\t/* Send the Write command (8-bit opcode + addr) */\n\t\t\tixgbe_shift_out_eeprom_bits(hw, write_opcode,\n\t\t\t\t\t\t IXGBE_EEPROM_OPCODE_BITS);\n\t\t\tixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),\n\t\t\t\t\t\t hw->eeprom.address_bits);\n\n\t\t\tpage_size = hw->eeprom.word_page_size;\n\n\t\t\t/* Send the data in burst via SPI*/\n\t\t\tdo {\n\t\t\t\tword = data[i];\n\t\t\t\tword = (word >> 8) | (word << 8);\n\t\t\t\tixgbe_shift_out_eeprom_bits(hw, word, 16);\n\n\t\t\t\tif (page_size == 0)\n\t\t\t\t\tbreak;\n\n\t\t\t\t/* do not wrap around page */\n\t\t\t\tif (((offset + i) & (page_size - 1)) ==\n\t\t\t\t (page_size - 1))\n\t\t\t\t\tbreak;\n\t\t\t} while (++i < words);\n\n\t\t\tixgbe_standby_eeprom(hw);\n\t\t\tmsec_delay(10);\n\t\t}\n\t\t/* Done with writing - release the EEPROM */\n\t\tixgbe_release_eeprom(hw);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be written to\n * @data: 16 bit word to be written to the EEPROM\n *\n * If ixgbe_eeprom_update_checksum is not called after this function, the\n * EEPROM will most likely contain an invalid checksum.\n **/\ns32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)\n{\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_write_eeprom_generic\");\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (offset >= hw->eeprom.word_size) {\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t\tgoto out;\n\t}\n\n\tstatus = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be read\n * @data: read 16 bit words(s) from EEPROM\n * @words: number of word(s)\n *\n * Reads 16 bit word(s) from EEPROM through bit-bang method\n **/\ns32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu16 i, count;\n\n\tDEBUGFUNC(\"ixgbe_read_eeprom_buffer_bit_bang_generic\");\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (words == 0) {\n\t\tstatus = IXGBE_ERR_INVALID_ARGUMENT;\n\t\tgoto out;\n\t}\n\n\tif (offset + words > hw->eeprom.word_size) {\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * We cannot hold synchronization semaphores for too long\n\t * to avoid other entity starvation. However it is more efficient\n\t * to read in bursts than synchronizing access for each word.\n\t */\n\tfor (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {\n\t\tcount = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?\n\t\t\tIXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);\n\n\t\tstatus = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,\n\t\t\t\t\t\t\t count, &data[i]);\n\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tbreak;\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be read\n * @words: number of word(s)\n * @data: read 16 bit word(s) from EEPROM\n *\n * Reads 16 bit word(s) from EEPROM through bit-bang method\n **/\nSTATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data)\n{\n\ts32 status;\n\tu16 word_in;\n\tu8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;\n\tu16 i;\n\n\tDEBUGFUNC(\"ixgbe_read_eeprom_buffer_bit_bang\");\n\n\t/* Prepare the EEPROM for reading */\n\tstatus = ixgbe_acquire_eeprom(hw);\n\n\tif (status == IXGBE_SUCCESS) {\n\t\tif (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {\n\t\t\tixgbe_release_eeprom(hw);\n\t\t\tstatus = IXGBE_ERR_EEPROM;\n\t\t}\n\t}\n\n\tif (status == IXGBE_SUCCESS) {\n\t\tfor (i = 0; i < words; i++) {\n\t\t\tixgbe_standby_eeprom(hw);\n\t\t\t/*\n\t\t\t * Some SPI eeproms use the 8th address bit embedded\n\t\t\t * in the opcode\n\t\t\t */\n\t\t\tif ((hw->eeprom.address_bits == 8) &&\n\t\t\t ((offset + i) >= 128))\n\t\t\t\tread_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;\n\n\t\t\t/* Send the READ command (opcode + addr) */\n\t\t\tixgbe_shift_out_eeprom_bits(hw, read_opcode,\n\t\t\t\t\t\t IXGBE_EEPROM_OPCODE_BITS);\n\t\t\tixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),\n\t\t\t\t\t\t hw->eeprom.address_bits);\n\n\t\t\t/* Read the data. */\n\t\t\tword_in = ixgbe_shift_in_eeprom_bits(hw, 16);\n\t\t\tdata[i] = (word_in >> 8) | (word_in << 8);\n\t\t}\n\n\t\t/* End this read operation */\n\t\tixgbe_release_eeprom(hw);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be read\n * @data: read 16 bit value from EEPROM\n *\n * Reads 16 bit value from EEPROM through bit-bang method\n **/\ns32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 *data)\n{\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_read_eeprom_bit_bang_generic\");\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (offset >= hw->eeprom.word_size) {\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t\tgoto out;\n\t}\n\n\tstatus = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @words: number of word(s)\n * @data: 16 bit word(s) from the EEPROM\n *\n * Reads a 16 bit word(s) from the EEPROM using the EERD register.\n **/\ns32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data)\n{\n\tu32 eerd;\n\ts32 status = IXGBE_SUCCESS;\n\tu32 i;\n\n\tDEBUGFUNC(\"ixgbe_read_eerd_buffer_generic\");\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (words == 0) {\n\t\tstatus = IXGBE_ERR_INVALID_ARGUMENT;\n\t\tERROR_REPORT1(IXGBE_ERROR_ARGUMENT, \"Invalid EEPROM words\");\n\t\tgoto out;\n\t}\n\n\tif (offset >= hw->eeprom.word_size) {\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t\tERROR_REPORT1(IXGBE_ERROR_ARGUMENT, \"Invalid EEPROM offset\");\n\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < words; i++) {\n\t\teerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |\n\t\t IXGBE_EEPROM_RW_REG_START;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);\n\t\tstatus = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);\n\n\t\tif (status == IXGBE_SUCCESS) {\n\t\t\tdata[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>\n\t\t\t\t IXGBE_EEPROM_RW_REG_DATA);\n\t\t} else {\n\t\t\tDEBUGOUT(\"Eeprom read timed out\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be used as a scratch pad\n *\n * Discover EEPROM page size by writing marching data at given offset.\n * This function is called only when we are writing a new large buffer\n * at given offset so the data would be overwritten anyway.\n **/\nSTATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t\t u16 offset)\n{\n\tu16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];\n\ts32 status = IXGBE_SUCCESS;\n\tu16 i;\n\n\tDEBUGFUNC(\"ixgbe_detect_eeprom_page_size_generic\");\n\n\tfor (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)\n\t\tdata[i] = i;\n\n\thw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;\n\tstatus = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,\n\t\t\t\t\t IXGBE_EEPROM_PAGE_SIZE_MAX, data);\n\thw->eeprom.word_page_size = 0;\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\tstatus = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\t/*\n\t * When writing in burst more than the actual page size\n\t * EEPROM address wraps around current page.\n\t */\n\thw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];\n\n\tDEBUGOUT1(\"Detected EEPROM page size = %d words.\",\n\t\t hw->eeprom.word_page_size);\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_read_eerd_generic - Read EEPROM word using EERD\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM using the EERD register.\n **/\ns32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)\n{\n\treturn ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);\n}\n\n/**\n * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to write\n * @words: number of word(s)\n * @data: word(s) write to the EEPROM\n *\n * Write a 16 bit word(s) to the EEPROM using the EEWR register.\n **/\ns32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data)\n{\n\tu32 eewr;\n\ts32 status = IXGBE_SUCCESS;\n\tu16 i;\n\n\tDEBUGFUNC(\"ixgbe_write_eewr_generic\");\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (words == 0) {\n\t\tstatus = IXGBE_ERR_INVALID_ARGUMENT;\n\t\tERROR_REPORT1(IXGBE_ERROR_ARGUMENT, \"Invalid EEPROM words\");\n\t\tgoto out;\n\t}\n\n\tif (offset >= hw->eeprom.word_size) {\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t\tERROR_REPORT1(IXGBE_ERROR_ARGUMENT, \"Invalid EEPROM offset\");\n\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < words; i++) {\n\t\teewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |\n\t\t\t(data[i] << IXGBE_EEPROM_RW_REG_DATA) |\n\t\t\tIXGBE_EEPROM_RW_REG_START;\n\n\t\tstatus = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);\n\t\tif (status != IXGBE_SUCCESS) {\n\t\t\tDEBUGOUT(\"Eeprom write EEWR timed out\\n\");\n\t\t\tgoto out;\n\t\t}\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);\n\n\t\tstatus = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);\n\t\tif (status != IXGBE_SUCCESS) {\n\t\t\tDEBUGOUT(\"Eeprom write EEWR timed out\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_write_eewr_generic - Write EEPROM word using EEWR\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to write\n * @data: word write to the EEPROM\n *\n * Write a 16 bit word to the EEPROM using the EEWR register.\n **/\ns32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)\n{\n\treturn ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);\n}\n\n/**\n * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status\n * @hw: pointer to hardware structure\n * @ee_reg: EEPROM flag for polling\n *\n * Polls the status bit (bit 1) of the EERD or EEWR to determine when the\n * read or write is done respectively.\n **/\ns32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)\n{\n\tu32 i;\n\tu32 reg;\n\ts32 status = IXGBE_ERR_EEPROM;\n\n\tDEBUGFUNC(\"ixgbe_poll_eerd_eewr_done\");\n\n\tfor (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {\n\t\tif (ee_reg == IXGBE_NVM_POLL_READ)\n\t\t\treg = IXGBE_READ_REG(hw, IXGBE_EERD);\n\t\telse\n\t\t\treg = IXGBE_READ_REG(hw, IXGBE_EEWR);\n\n\t\tif (reg & IXGBE_EEPROM_RW_REG_DONE) {\n\t\t\tstatus = IXGBE_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\tusec_delay(5);\n\t}\n\n\tif (i == IXGBE_EERD_EEWR_ATTEMPTS)\n\t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n\t\t\t \"EEPROM read/write done polling timed out\");\n\n\treturn status;\n}\n\n/**\n * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang\n * @hw: pointer to hardware structure\n *\n * Prepares EEPROM for access using bit-bang method. This function should\n * be called before issuing a command to the EEPROM.\n **/\nSTATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu32 eec;\n\tu32 i;\n\n\tDEBUGFUNC(\"ixgbe_acquire_eeprom\");\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)\n\t != IXGBE_SUCCESS)\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\n\tif (status == IXGBE_SUCCESS) {\n\t\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\t\t/* Request EEPROM Access */\n\t\teec |= IXGBE_EEC_REQ;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\n\t\tfor (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {\n\t\t\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\t\t\tif (eec & IXGBE_EEC_GNT)\n\t\t\t\tbreak;\n\t\t\tusec_delay(5);\n\t\t}\n\n\t\t/* Release if grant not acquired */\n\t\tif (!(eec & IXGBE_EEC_GNT)) {\n\t\t\teec &= ~IXGBE_EEC_REQ;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\t\t\tDEBUGOUT(\"Could not acquire EEPROM grant\\n\");\n\n\t\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\t\t\tstatus = IXGBE_ERR_EEPROM;\n\t\t}\n\n\t\t/* Setup EEPROM for Read/Write */\n\t\tif (status == IXGBE_SUCCESS) {\n\t\t\t/* Clear CS and SK */\n\t\t\teec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\t\t\tIXGBE_WRITE_FLUSH(hw);\n\t\t\tusec_delay(1);\n\t\t}\n\t}\n\treturn status;\n}\n\n/**\n * ixgbe_get_eeprom_semaphore - Get hardware semaphore\n * @hw: pointer to hardware structure\n *\n * Sets the hardware semaphores so EEPROM access can occur for bit-bang method\n **/\nSTATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_EEPROM;\n\tu32 timeout = 2000;\n\tu32 i;\n\tu32 swsm;\n\n\tDEBUGFUNC(\"ixgbe_get_eeprom_semaphore\");\n\n\n\t/* Get SMBI software semaphore between device drivers first */\n\tfor (i = 0; i < timeout; i++) {\n\t\t/*\n\t\t * If the SMBI bit is 0 when we read it, then the bit will be\n\t\t * set and we have the semaphore\n\t\t */\n\t\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\t\tif (!(swsm & IXGBE_SWSM_SMBI)) {\n\t\t\tstatus = IXGBE_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\tusec_delay(50);\n\t}\n\n\tif (i == timeout) {\n\t\tDEBUGOUT(\"Driver can't access the Eeprom - SMBI Semaphore \"\n\t\t\t \"not granted.\\n\");\n\t\t/*\n\t\t * this release is particularly important because our attempts\n\t\t * above to get the semaphore may have succeeded, and if there\n\t\t * was a timeout, we should unconditionally clear the semaphore\n\t\t * bits to free the driver to make progress\n\t\t */\n\t\tixgbe_release_eeprom_semaphore(hw);\n\n\t\tusec_delay(50);\n\t\t/*\n\t\t * one last try\n\t\t * If the SMBI bit is 0 when we read it, then the bit will be\n\t\t * set and we have the semaphore\n\t\t */\n\t\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\t\tif (!(swsm & IXGBE_SWSM_SMBI))\n\t\t\tstatus = IXGBE_SUCCESS;\n\t}\n\n\t/* Now get the semaphore between SW/FW through the SWESMBI bit */\n\tif (status == IXGBE_SUCCESS) {\n\t\tfor (i = 0; i < timeout; i++) {\n\t\t\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\n\t\t\t/* Set the SW EEPROM semaphore bit to request access */\n\t\t\tswsm |= IXGBE_SWSM_SWESMBI;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);\n\n\t\t\t/*\n\t\t\t * If we set the bit successfully then we got the\n\t\t\t * semaphore.\n\t\t\t */\n\t\t\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\t\t\tif (swsm & IXGBE_SWSM_SWESMBI)\n\t\t\t\tbreak;\n\n\t\t\tusec_delay(50);\n\t\t}\n\n\t\t/*\n\t\t * Release semaphores and return error if SW EEPROM semaphore\n\t\t * was not granted because we don't have access to the EEPROM\n\t\t */\n\t\tif (i >= timeout) {\n\t\t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n\t\t\t \"SWESMBI Software EEPROM semaphore not granted.\\n\");\n\t\t\tixgbe_release_eeprom_semaphore(hw);\n\t\t\tstatus = IXGBE_ERR_EEPROM;\n\t\t}\n\t} else {\n\t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n\t\t\t \"Software semaphore SMBI between device drivers \"\n\t\t\t \"not granted.\\n\");\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_release_eeprom_semaphore - Release hardware semaphore\n * @hw: pointer to hardware structure\n *\n * This function clears hardware semaphore bits.\n **/\nSTATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)\n{\n\tu32 swsm;\n\n\tDEBUGFUNC(\"ixgbe_release_eeprom_semaphore\");\n\n\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\n\t/* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */\n\tswsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);\n\tIXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/**\n * ixgbe_ready_eeprom - Polls for EEPROM ready\n * @hw: pointer to hardware structure\n **/\nSTATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu16 i;\n\tu8 spi_stat_reg;\n\n\tDEBUGFUNC(\"ixgbe_ready_eeprom\");\n\n\t/*\n\t * Read \"Status Register\" repeatedly until the LSB is cleared. The\n\t * EEPROM will signal that the command has been completed by clearing\n\t * bit 0 of the internal status register. If it's not cleared within\n\t * 5 milliseconds, then error out.\n\t */\n\tfor (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {\n\t\tixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,\n\t\t\t\t\t IXGBE_EEPROM_OPCODE_BITS);\n\t\tspi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);\n\t\tif (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))\n\t\t\tbreak;\n\n\t\tusec_delay(5);\n\t\tixgbe_standby_eeprom(hw);\n\t};\n\n\t/*\n\t * On some parts, SPI write time could vary from 0-20mSec on 3.3V\n\t * devices (and only 0-5mSec on 5V devices)\n\t */\n\tif (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {\n\t\tDEBUGOUT(\"SPI EEPROM Status error\\n\");\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_standby_eeprom - Returns EEPROM to a \"standby\" state\n * @hw: pointer to hardware structure\n **/\nSTATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)\n{\n\tu32 eec;\n\n\tDEBUGFUNC(\"ixgbe_standby_eeprom\");\n\n\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\t/* Toggle CS to flush commands */\n\teec |= IXGBE_EEC_CS;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\tIXGBE_WRITE_FLUSH(hw);\n\tusec_delay(1);\n\teec &= ~IXGBE_EEC_CS;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\tIXGBE_WRITE_FLUSH(hw);\n\tusec_delay(1);\n}\n\n/**\n * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.\n * @hw: pointer to hardware structure\n * @data: data to send to the EEPROM\n * @count: number of bits to shift out\n **/\nSTATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,\n\t\t\t\t\tu16 count)\n{\n\tu32 eec;\n\tu32 mask;\n\tu32 i;\n\n\tDEBUGFUNC(\"ixgbe_shift_out_eeprom_bits\");\n\n\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\t/*\n\t * Mask is used to shift \"count\" bits of \"data\" out to the EEPROM\n\t * one bit at a time. Determine the starting bit based on count\n\t */\n\tmask = 0x01 << (count - 1);\n\n\tfor (i = 0; i < count; i++) {\n\t\t/*\n\t\t * A \"1\" is shifted out to the EEPROM by setting bit \"DI\" to a\n\t\t * \"1\", and then raising and then lowering the clock (the SK\n\t\t * bit controls the clock input to the EEPROM). A \"0\" is\n\t\t * shifted out to the EEPROM by setting \"DI\" to \"0\" and then\n\t\t * raising and then lowering the clock.\n\t\t */\n\t\tif (data & mask)\n\t\t\teec |= IXGBE_EEC_DI;\n\t\telse\n\t\t\teec &= ~IXGBE_EEC_DI;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\n\t\tusec_delay(1);\n\n\t\tixgbe_raise_eeprom_clk(hw, &eec);\n\t\tixgbe_lower_eeprom_clk(hw, &eec);\n\n\t\t/*\n\t\t * Shift mask to signify next bit of data to shift in to the\n\t\t * EEPROM\n\t\t */\n\t\tmask = mask >> 1;\n\t};\n\n\t/* We leave the \"DI\" bit set to \"0\" when we leave this routine. */\n\teec &= ~IXGBE_EEC_DI;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/**\n * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM\n * @hw: pointer to hardware structure\n **/\nSTATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)\n{\n\tu32 eec;\n\tu32 i;\n\tu16 data = 0;\n\n\tDEBUGFUNC(\"ixgbe_shift_in_eeprom_bits\");\n\n\t/*\n\t * In order to read a register from the EEPROM, we need to shift\n\t * 'count' bits in from the EEPROM. Bits are \"shifted in\" by raising\n\t * the clock input to the EEPROM (setting the SK bit), and then reading\n\t * the value of the \"DO\" bit. During this \"shifting in\" process the\n\t * \"DI\" bit should always be clear.\n\t */\n\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\teec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);\n\n\tfor (i = 0; i < count; i++) {\n\t\tdata = data << 1;\n\t\tixgbe_raise_eeprom_clk(hw, &eec);\n\n\t\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\t\teec &= ~(IXGBE_EEC_DI);\n\t\tif (eec & IXGBE_EEC_DO)\n\t\t\tdata |= 1;\n\n\t\tixgbe_lower_eeprom_clk(hw, &eec);\n\t}\n\n\treturn data;\n}\n\n/**\n * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.\n * @hw: pointer to hardware structure\n * @eec: EEC register's current value\n **/\nSTATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)\n{\n\tDEBUGFUNC(\"ixgbe_raise_eeprom_clk\");\n\n\t/*\n\t * Raise the clock input to the EEPROM\n\t * (setting the SK bit), then delay\n\t */\n\t*eec = *eec | IXGBE_EEC_SK;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);\n\tIXGBE_WRITE_FLUSH(hw);\n\tusec_delay(1);\n}\n\n/**\n * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.\n * @hw: pointer to hardware structure\n * @eecd: EECD's current value\n **/\nSTATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)\n{\n\tDEBUGFUNC(\"ixgbe_lower_eeprom_clk\");\n\n\t/*\n\t * Lower the clock input to the EEPROM (clearing the SK bit), then\n\t * delay\n\t */\n\t*eec = *eec & ~IXGBE_EEC_SK;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);\n\tIXGBE_WRITE_FLUSH(hw);\n\tusec_delay(1);\n}\n\n/**\n * ixgbe_release_eeprom - Release EEPROM, release semaphores\n * @hw: pointer to hardware structure\n **/\nSTATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)\n{\n\tu32 eec;\n\n\tDEBUGFUNC(\"ixgbe_release_eeprom\");\n\n\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\teec |= IXGBE_EEC_CS; /* Pull CS high */\n\teec &= ~IXGBE_EEC_SK; /* Lower SCK */\n\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\tusec_delay(1);\n\n\t/* Stop requesting EEPROM access */\n\teec &= ~IXGBE_EEC_REQ;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\n\t/* Delay before attempt to obtain semaphore again to allow FW access */\n\tmsec_delay(hw->eeprom.semaphore_delay);\n}\n\n/**\n * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum\n * @hw: pointer to hardware structure\n *\n * Returns a negative error code on error, or the 16-bit checksum\n **/\ns32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)\n{\n\tu16 i;\n\tu16 j;\n\tu16 checksum = 0;\n\tu16 length = 0;\n\tu16 pointer = 0;\n\tu16 word = 0;\n\n\tDEBUGFUNC(\"ixgbe_calc_eeprom_checksum_generic\");\n\n\t/* Include 0x0-0x3F in the checksum */\n\tfor (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {\n\t\tif (hw->eeprom.ops.read(hw, i, &word)) {\n\t\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\t\treturn IXGBE_ERR_EEPROM;\n\t\t}\n\t\tchecksum += word;\n\t}\n\n\t/* Include all data from pointers except for the fw pointer */\n\tfor (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {\n\t\tif (hw->eeprom.ops.read(hw, i, &pointer)) {\n\t\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\t\treturn IXGBE_ERR_EEPROM;\n\t\t}\n\n\t\t/* If the pointer seems invalid */\n\t\tif (pointer == 0xFFFF || pointer == 0)\n\t\t\tcontinue;\n\n\t\tif (hw->eeprom.ops.read(hw, pointer, &length)) {\n\t\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\t\treturn IXGBE_ERR_EEPROM;\n\t\t}\n\n\t\tif (length == 0xFFFF || length == 0)\n\t\t\tcontinue;\n\n\t\tfor (j = pointer + 1; j <= pointer + length; j++) {\n\t\t\tif (hw->eeprom.ops.read(hw, j, &word)) {\n\t\t\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\t\t\treturn IXGBE_ERR_EEPROM;\n\t\t\t}\n\t\t\tchecksum += word;\n\t\t}\n\t}\n\n\tchecksum = (u16)IXGBE_EEPROM_SUM - checksum;\n\n\treturn (s32)checksum;\n}\n\n/**\n * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum\n * @hw: pointer to hardware structure\n * @checksum_val: calculated checksum\n *\n * Performs checksum calculation and validates the EEPROM checksum. If the\n * caller does not need checksum_val, the value can be NULL.\n **/\ns32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *checksum_val)\n{\n\ts32 status;\n\tu16 checksum;\n\tu16 read_checksum = 0;\n\n\tDEBUGFUNC(\"ixgbe_validate_eeprom_checksum_generic\");\n\n\t/* Read the first word from the EEPROM. If this times out or fails, do\n\t * not continue or we could be in for a very long wait while every\n\t * EEPROM read fails\n\t */\n\tstatus = hw->eeprom.ops.read(hw, 0, &checksum);\n\tif (status) {\n\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = hw->eeprom.ops.calc_checksum(hw);\n\tif (status < 0)\n\t\treturn status;\n\n\tchecksum = (u16)(status & 0xffff);\n\n\tstatus = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);\n\tif (status) {\n\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\treturn status;\n\t}\n\n\t/* Verify read checksum from EEPROM is the same as\n\t * calculated checksum\n\t */\n\tif (read_checksum != checksum)\n\t\tstatus = IXGBE_ERR_EEPROM_CHECKSUM;\n\n\t/* If the user cares, return the calculated checksum */\n\tif (checksum_val)\n\t\t*checksum_val = checksum;\n\n\treturn status;\n}\n\n/**\n * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\tu16 checksum;\n\n\tDEBUGFUNC(\"ixgbe_update_eeprom_checksum_generic\");\n\n\t/* Read the first word from the EEPROM. If this times out or fails, do\n\t * not continue or we could be in for a very long wait while every\n\t * EEPROM read fails\n\t */\n\tstatus = hw->eeprom.ops.read(hw, 0, &checksum);\n\tif (status) {\n\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = hw->eeprom.ops.calc_checksum(hw);\n\tif (status < 0)\n\t\treturn status;\n\n\tchecksum = (u16)(status & 0xffff);\n\n\tstatus = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);\n\n\treturn status;\n}\n\n/**\n * ixgbe_validate_mac_addr - Validate MAC address\n * @mac_addr: pointer to MAC address.\n *\n * Tests a MAC address to ensure it is a valid Individual Address\n **/\ns32 ixgbe_validate_mac_addr(u8 *mac_addr)\n{\n\ts32 status = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_validate_mac_addr\");\n\n\t/* Make sure it is not a multicast address */\n\tif (IXGBE_IS_MULTICAST(mac_addr)) {\n\t\tDEBUGOUT(\"MAC address is multicast\\n\");\n\t\tstatus = IXGBE_ERR_INVALID_MAC_ADDR;\n\t/* Not a broadcast address */\n\t} else if (IXGBE_IS_BROADCAST(mac_addr)) {\n\t\tDEBUGOUT(\"MAC address is broadcast\\n\");\n\t\tstatus = IXGBE_ERR_INVALID_MAC_ADDR;\n\t/* Reject the zero address */\n\t} else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&\n\t\t mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {\n\t\tDEBUGOUT(\"MAC address is all zeros\\n\");\n\t\tstatus = IXGBE_ERR_INVALID_MAC_ADDR;\n\t}\n\treturn status;\n}\n\n/**\n * ixgbe_set_rar_generic - Set Rx address register\n * @hw: pointer to hardware structure\n * @index: Receive address register to write\n * @addr: Address to put into receive address register\n * @vmdq: VMDq \"set\" or \"pool\" index\n * @enable_addr: set flag that address is active\n *\n * Puts an ethernet address into a receive address register.\n **/\ns32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n\t\t\t u32 enable_addr)\n{\n\tu32 rar_low, rar_high;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\tDEBUGFUNC(\"ixgbe_set_rar_generic\");\n\n\t/* Make sure we are using a valid rar index range */\n\tif (index >= rar_entries) {\n\t\tERROR_REPORT2(IXGBE_ERROR_ARGUMENT,\n\t\t\t \"RAR index %d is out of range.\\n\", index);\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\t/* setup VMDq pool selection before this RAR gets enabled */\n\thw->mac.ops.set_vmdq(hw, index, vmdq);\n\n\t/*\n\t * HW expects these in little endian so we reverse the byte\n\t * order from network order (big endian) to little endian\n\t */\n\trar_low = ((u32)addr[0] |\n\t\t ((u32)addr[1] << 8) |\n\t\t ((u32)addr[2] << 16) |\n\t\t ((u32)addr[3] << 24));\n\t/*\n\t * Some parts put the VMDq setting in the extra RAH bits,\n\t * so save everything except the lower 16 bits that hold part\n\t * of the address and the address valid bit.\n\t */\n\trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));\n\trar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);\n\trar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));\n\n\tif (enable_addr != 0)\n\t\trar_high |= IXGBE_RAH_AV;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);\n\tIXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_clear_rar_generic - Remove Rx address register\n * @hw: pointer to hardware structure\n * @index: Receive address register to write\n *\n * Clears an ethernet address from a receive address register.\n **/\ns32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)\n{\n\tu32 rar_high;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\tDEBUGFUNC(\"ixgbe_clear_rar_generic\");\n\n\t/* Make sure we are using a valid rar index range */\n\tif (index >= rar_entries) {\n\t\tERROR_REPORT2(IXGBE_ERROR_ARGUMENT,\n\t\t\t \"RAR index %d is out of range.\\n\", index);\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\t/*\n\t * Some parts put the VMDq setting in the extra RAH bits,\n\t * so save everything except the lower 16 bits that hold part\n\t * of the address and the address valid bit.\n\t */\n\trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));\n\trar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);\n\tIXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);\n\n\t/* clear VMDq pool/queue selection for this RAR */\n\thw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_init_rx_addrs_generic - Initializes receive address filters.\n * @hw: pointer to hardware structure\n *\n * Places the MAC address in receive address register 0 and clears the rest\n * of the receive address registers. Clears the multicast table. Assumes\n * the receiver is in reset when the routine is called.\n **/\ns32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)\n{\n\tu32 i;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\tDEBUGFUNC(\"ixgbe_init_rx_addrs_generic\");\n\n\t/*\n\t * If the current mac address is valid, assume it is a software override\n\t * to the permanent address.\n\t * Otherwise, use the permanent address from the eeprom.\n\t */\n\tif (ixgbe_validate_mac_addr(hw->mac.addr) ==\n\t IXGBE_ERR_INVALID_MAC_ADDR) {\n\t\t/* Get the MAC address from the RAR0 for later reference */\n\t\thw->mac.ops.get_mac_addr(hw, hw->mac.addr);\n\n\t\tDEBUGOUT3(\" Keeping Current RAR0 Addr =%.2X %.2X %.2X \",\n\t\t\t hw->mac.addr[0], hw->mac.addr[1],\n\t\t\t hw->mac.addr[2]);\n\t\tDEBUGOUT3(\"%.2X %.2X %.2X\\n\", hw->mac.addr[3],\n\t\t\t hw->mac.addr[4], hw->mac.addr[5]);\n\t} else {\n\t\t/* Setup the receive address. */\n\t\tDEBUGOUT(\"Overriding MAC Address in RAR[0]\\n\");\n\t\tDEBUGOUT3(\" New MAC Addr =%.2X %.2X %.2X \",\n\t\t\t hw->mac.addr[0], hw->mac.addr[1],\n\t\t\t hw->mac.addr[2]);\n\t\tDEBUGOUT3(\"%.2X %.2X %.2X\\n\", hw->mac.addr[3],\n\t\t\t hw->mac.addr[4], hw->mac.addr[5]);\n\n\t\thw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);\n\n\t\t/* clear VMDq pool/queue selection for RAR 0 */\n\t\thw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);\n\t}\n\thw->addr_ctrl.overflow_promisc = 0;\n\n\thw->addr_ctrl.rar_used_count = 1;\n\n\t/* Zero out the other receive addresses. */\n\tDEBUGOUT1(\"Clearing RAR[1-%d]\\n\", rar_entries - 1);\n\tfor (i = 1; i < rar_entries; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);\n\t}\n\n\t/* Clear the MTA */\n\thw->addr_ctrl.mta_in_use = 0;\n\tIXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);\n\n\tDEBUGOUT(\" Clearing MTA\\n\");\n\tfor (i = 0; i < hw->mac.mcft_size; i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);\n\n\tixgbe_init_uta_tables(hw);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_add_uc_addr - Adds a secondary unicast address.\n * @hw: pointer to hardware structure\n * @addr: new address\n *\n * Adds it to unused receive address register or goes into promiscuous mode.\n **/\nvoid ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)\n{\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\tu32 rar;\n\n\tDEBUGFUNC(\"ixgbe_add_uc_addr\");\n\n\tDEBUGOUT6(\" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\\n\",\n\t\t addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);\n\n\t/*\n\t * Place this address in the RAR if there is room,\n\t * else put the controller into promiscuous mode\n\t */\n\tif (hw->addr_ctrl.rar_used_count < rar_entries) {\n\t\trar = hw->addr_ctrl.rar_used_count;\n\t\thw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);\n\t\tDEBUGOUT1(\"Added a secondary address to RAR[%d]\\n\", rar);\n\t\thw->addr_ctrl.rar_used_count++;\n\t} else {\n\t\thw->addr_ctrl.overflow_promisc++;\n\t}\n\n\tDEBUGOUT(\"ixgbe_add_uc_addr Complete\\n\");\n}\n\n/**\n * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses\n * @hw: pointer to hardware structure\n * @addr_list: the list of new addresses\n * @addr_count: number of addresses\n * @next: iterator function to walk the address list\n *\n * The given list replaces any existing list. Clears the secondary addrs from\n * receive address registers. Uses unused receive address registers for the\n * first secondary addresses, and falls back to promiscuous mode as needed.\n *\n * Drivers using secondary unicast addresses must set user_set_promisc when\n * manually putting the device into promiscuous mode.\n **/\ns32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,\n\t\t\t\t u32 addr_count, ixgbe_mc_addr_itr next)\n{\n\tu8 *addr;\n\tu32 i;\n\tu32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;\n\tu32 uc_addr_in_use;\n\tu32 fctrl;\n\tu32 vmdq;\n\n\tDEBUGFUNC(\"ixgbe_update_uc_addr_list_generic\");\n\n\t/*\n\t * Clear accounting of old secondary address list,\n\t * don't count RAR[0]\n\t */\n\tuc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;\n\thw->addr_ctrl.rar_used_count -= uc_addr_in_use;\n\thw->addr_ctrl.overflow_promisc = 0;\n\n\t/* Zero out the other receive addresses */\n\tDEBUGOUT1(\"Clearing RAR[1-%d]\\n\", uc_addr_in_use+1);\n\tfor (i = 0; i < uc_addr_in_use; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);\n\t}\n\n\t/* Add the new addresses */\n\tfor (i = 0; i < addr_count; i++) {\n\t\tDEBUGOUT(\" Adding the secondary addresses:\\n\");\n\t\taddr = next(hw, &addr_list, &vmdq);\n\t\tixgbe_add_uc_addr(hw, addr, vmdq);\n\t}\n\n\tif (hw->addr_ctrl.overflow_promisc) {\n\t\t/* enable promisc if not already in overflow or set by user */\n\t\tif (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {\n\t\t\tDEBUGOUT(\" Entering address overflow promisc mode\\n\");\n\t\t\tfctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\t\t\tfctrl |= IXGBE_FCTRL_UPE;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);\n\t\t}\n\t} else {\n\t\t/* only disable if set by overflow, not by user */\n\t\tif (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {\n\t\t\tDEBUGOUT(\" Leaving address overflow promisc mode\\n\");\n\t\t\tfctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\t\t\tfctrl &= ~IXGBE_FCTRL_UPE;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);\n\t\t}\n\t}\n\n\tDEBUGOUT(\"ixgbe_update_uc_addr_list_generic Complete\\n\");\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_mta_vector - Determines bit-vector in multicast table to set\n * @hw: pointer to hardware structure\n * @mc_addr: the multicast address\n *\n * Extracts the 12 bits, from a multicast address, to determine which\n * bit-vector to set in the multicast table. The hardware uses 12 bits, from\n * incoming rx multicast addresses, to determine the bit-vector to check in\n * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set\n * by the MO field of the MCSTCTRL. The MO field is set during initialization\n * to mc_filter_type.\n **/\nSTATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)\n{\n\tu32 vector = 0;\n\n\tDEBUGFUNC(\"ixgbe_mta_vector\");\n\n\tswitch (hw->mac.mc_filter_type) {\n\tcase 0: /* use bits [47:36] of the address */\n\t\tvector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));\n\t\tbreak;\n\tcase 1: /* use bits [46:35] of the address */\n\t\tvector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));\n\t\tbreak;\n\tcase 2: /* use bits [45:34] of the address */\n\t\tvector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));\n\t\tbreak;\n\tcase 3: /* use bits [43:32] of the address */\n\t\tvector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));\n\t\tbreak;\n\tdefault: /* Invalid mc_filter_type */\n\t\tDEBUGOUT(\"MC filter type param set incorrectly\\n\");\n\t\tASSERT(0);\n\t\tbreak;\n\t}\n\n\t/* vector can only be 12-bits or boundary will be exceeded */\n\tvector &= 0xFFF;\n\treturn vector;\n}\n\n/**\n * ixgbe_set_mta - Set bit-vector in multicast table\n * @hw: pointer to hardware structure\n * @hash_value: Multicast address hash value\n *\n * Sets the bit-vector in the multicast table.\n **/\nvoid ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)\n{\n\tu32 vector;\n\tu32 vector_bit;\n\tu32 vector_reg;\n\n\tDEBUGFUNC(\"ixgbe_set_mta\");\n\n\thw->addr_ctrl.mta_in_use++;\n\n\tvector = ixgbe_mta_vector(hw, mc_addr);\n\tDEBUGOUT1(\" bit-vector = 0x%03X\\n\", vector);\n\n\t/*\n\t * The MTA is a register array of 128 32-bit registers. It is treated\n\t * like an array of 4096 bits. We want to set bit\n\t * BitArray[vector_value]. So we figure out what register the bit is\n\t * in, read it, OR in the new bit, then write back the new value. The\n\t * register is determined by the upper 7 bits of the vector value and\n\t * the bit within that register are determined by the lower 5 bits of\n\t * the value.\n\t */\n\tvector_reg = (vector >> 5) & 0x7F;\n\tvector_bit = vector & 0x1F;\n\thw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);\n}\n\n/**\n * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses\n * @hw: pointer to hardware structure\n * @mc_addr_list: the list of new multicast addresses\n * @mc_addr_count: number of addresses\n * @next: iterator function to walk the multicast address list\n * @clear: flag, when set clears the table beforehand\n *\n * When the clear flag is set, the given list replaces any existing list.\n * Hashes the given addresses into the multicast table.\n **/\ns32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,\n\t\t\t\t u32 mc_addr_count, ixgbe_mc_addr_itr next,\n\t\t\t\t bool clear)\n{\n\tu32 i;\n\tu32 vmdq;\n\n\tDEBUGFUNC(\"ixgbe_update_mc_addr_list_generic\");\n\n\t/*\n\t * Set the new number of MC addresses that we are being requested to\n\t * use.\n\t */\n\thw->addr_ctrl.num_mc_addrs = mc_addr_count;\n\thw->addr_ctrl.mta_in_use = 0;\n\n\t/* Clear mta_shadow */\n\tif (clear) {\n\t\tDEBUGOUT(\" Clearing MTA\\n\");\n\t\tmemset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));\n\t}\n\n\t/* Update mta_shadow */\n\tfor (i = 0; i < mc_addr_count; i++) {\n\t\tDEBUGOUT(\" Adding the multicast addresses:\\n\");\n\t\tixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));\n\t}\n\n\t/* Enable mta */\n\tfor (i = 0; i < hw->mac.mcft_size; i++)\n\t\tIXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,\n\t\t\t\t hw->mac.mta_shadow[i]);\n\n\tif (hw->addr_ctrl.mta_in_use > 0)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,\n\t\t\t\tIXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);\n\n\tDEBUGOUT(\"ixgbe_update_mc_addr_list_generic Complete\\n\");\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_enable_mc_generic - Enable multicast address in RAR\n * @hw: pointer to hardware structure\n *\n * Enables multicast address in RAR and the use of the multicast hash table.\n **/\ns32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_addr_filter_info *a = &hw->addr_ctrl;\n\n\tDEBUGFUNC(\"ixgbe_enable_mc_generic\");\n\n\tif (a->mta_in_use > 0)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |\n\t\t\t\thw->mac.mc_filter_type);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_disable_mc_generic - Disable multicast address in RAR\n * @hw: pointer to hardware structure\n *\n * Disables multicast address in RAR and the use of the multicast hash table.\n **/\ns32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_addr_filter_info *a = &hw->addr_ctrl;\n\n\tDEBUGFUNC(\"ixgbe_disable_mc_generic\");\n\n\tif (a->mta_in_use > 0)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_fc_enable_generic - Enable flow control\n * @hw: pointer to hardware structure\n *\n * Enable flow control according to the current settings.\n **/\ns32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = IXGBE_SUCCESS;\n\tu32 mflcn_reg, fccfg_reg;\n\tu32 reg;\n\tu32 fcrtl, fcrth;\n\tint i;\n\n\tDEBUGFUNC(\"ixgbe_fc_enable_generic\");\n\n\t/* Validate the water mark configuration */\n\tif (!hw->fc.pause_time) {\n\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\tgoto out;\n\t}\n\n\t/* Low water mark of zero causes XOFF floods */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tif ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&\n\t\t hw->fc.high_water[i]) {\n\t\t\tif (!hw->fc.low_water[i] ||\n\t\t\t hw->fc.low_water[i] >= hw->fc.high_water[i]) {\n\t\t\t\tDEBUGOUT(\"Invalid water mark configuration\\n\");\n\t\t\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Negotiate the fc mode to use */\n\tixgbe_fc_autoneg(hw);\n\n\t/* Disable any previous flow control settings */\n\tmflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);\n\tmflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);\n\n\tfccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);\n\tfccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);\n\n\t/*\n\t * The possible values of fc.current_mode are:\n\t * 0: Flow control is completely disabled\n\t * 1: Rx flow control is enabled (we can receive pause frames,\n\t * but not send pause frames).\n\t * 2: Tx flow control is enabled (we can send pause frames but\n\t * we do not support receiving pause frames).\n\t * 3: Both Rx and Tx flow control (symmetric) are enabled.\n\t * other: Invalid.\n\t */\n\tswitch (hw->fc.current_mode) {\n\tcase ixgbe_fc_none:\n\t\t/*\n\t\t * Flow control is disabled by software override or autoneg.\n\t\t * The code below will actually disable it in the HW.\n\t\t */\n\t\tbreak;\n\tcase ixgbe_fc_rx_pause:\n\t\t/*\n\t\t * Rx Flow control is enabled and Tx Flow control is\n\t\t * disabled by software override. Since there really\n\t\t * isn't a way to advertise that we are capable of RX\n\t\t * Pause ONLY, we will advertise that we support both\n\t\t * symmetric and asymmetric Rx PAUSE. Later, we will\n\t\t * disable the adapter's ability to send PAUSE frames.\n\t\t */\n\t\tmflcn_reg |= IXGBE_MFLCN_RFCE;\n\t\tbreak;\n\tcase ixgbe_fc_tx_pause:\n\t\t/*\n\t\t * Tx Flow control is enabled, and Rx Flow control is\n\t\t * disabled by software override.\n\t\t */\n\t\tfccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;\n\t\tbreak;\n\tcase ixgbe_fc_full:\n\t\t/* Flow control (both Rx and Tx) is enabled by SW override. */\n\t\tmflcn_reg |= IXGBE_MFLCN_RFCE;\n\t\tfccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;\n\t\tbreak;\n\tdefault:\n\t\tERROR_REPORT1(IXGBE_ERROR_ARGUMENT,\n\t\t\t \"Flow control param set incorrectly\\n\");\n\t\tret_val = IXGBE_ERR_CONFIG;\n\t\tgoto out;\n\t\tbreak;\n\t}\n\n\t/* Set 802.3x based flow control settings. */\n\tmflcn_reg |= IXGBE_MFLCN_DPF;\n\tIXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);\n\tIXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);\n\n\n\t/* Set up and enable Rx high/low water mark thresholds, enable XON. */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tif ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&\n\t\t hw->fc.high_water[i]) {\n\t\t\tfcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);\n\t\t\tfcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;\n\t\t} else {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);\n\t\t\t/*\n\t\t\t * In order to prevent Tx hangs when the internal Tx\n\t\t\t * switch is enabled we must set the high water mark\n\t\t\t * to the Rx packet buffer size - 24KB. This allows\n\t\t\t * the Tx switch to function even under heavy Rx\n\t\t\t * workloads.\n\t\t\t */\n\t\t\tfcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;\n\t\t}\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);\n\t}\n\n\t/* Configure pause time (2 TCs per register) */\n\treg = hw->fc.pause_time * 0x00010001;\n\tfor (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);\n\n\t/* Configure flow control refresh threshold value */\n\tIXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_negotiate_fc - Negotiate flow control\n * @hw: pointer to hardware structure\n * @adv_reg: flow control advertised settings\n * @lp_reg: link partner's flow control settings\n * @adv_sym: symmetric pause bit in advertisement\n * @adv_asm: asymmetric pause bit in advertisement\n * @lp_sym: symmetric pause bit in link partner advertisement\n * @lp_asm: asymmetric pause bit in link partner advertisement\n *\n * Find the intersection between advertised settings and link partner's\n * advertised settings\n **/\nSTATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,\n\t\t\t u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)\n{\n\tif ((!(adv_reg)) || (!(lp_reg))) {\n\t\tERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,\n\t\t\t \"Local or link partner's advertised flow control \"\n\t\t\t \"settings are NULL. Local: %x, link partner: %x\\n\",\n\t\t\t adv_reg, lp_reg);\n\t\treturn IXGBE_ERR_FC_NOT_NEGOTIATED;\n\t}\n\n\tif ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {\n\t\t/*\n\t\t * Now we need to check if the user selected Rx ONLY\n\t\t * of pause frames. In this case, we had to advertise\n\t\t * FULL flow control because we could not advertise RX\n\t\t * ONLY. Hence, we must now check to see if we need to\n\t\t * turn OFF the TRANSMISSION of PAUSE frames.\n\t\t */\n\t\tif (hw->fc.requested_mode == ixgbe_fc_full) {\n\t\t\thw->fc.current_mode = ixgbe_fc_full;\n\t\t\tDEBUGOUT(\"Flow Control = FULL.\\n\");\n\t\t} else {\n\t\t\thw->fc.current_mode = ixgbe_fc_rx_pause;\n\t\t\tDEBUGOUT(\"Flow Control=RX PAUSE frames only\\n\");\n\t\t}\n\t} else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&\n\t\t (lp_reg & lp_sym) && (lp_reg & lp_asm)) {\n\t\thw->fc.current_mode = ixgbe_fc_tx_pause;\n\t\tDEBUGOUT(\"Flow Control = TX PAUSE frames only.\\n\");\n\t} else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&\n\t\t !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {\n\t\thw->fc.current_mode = ixgbe_fc_rx_pause;\n\t\tDEBUGOUT(\"Flow Control = RX PAUSE frames only.\\n\");\n\t} else {\n\t\thw->fc.current_mode = ixgbe_fc_none;\n\t\tDEBUGOUT(\"Flow Control = NONE.\\n\");\n\t}\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber\n * @hw: pointer to hardware structure\n *\n * Enable flow control according on 1 gig fiber.\n **/\nSTATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)\n{\n\tu32 pcs_anadv_reg, pcs_lpab_reg, linkstat;\n\ts32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;\n\n\t/*\n\t * On multispeed fiber at 1g, bail out if\n\t * - link is up but AN did not complete, or if\n\t * - link is up and AN completed but timed out\n\t */\n\n\tlinkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);\n\tif ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||\n\t (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {\n\t\tDEBUGOUT(\"Auto-Negotiation did not complete or timed out\\n\");\n\t\tgoto out;\n\t}\n\n\tpcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);\n\tpcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);\n\n\tret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,\n\t\t\t\t pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,\n\t\t\t\t IXGBE_PCS1GANA_ASM_PAUSE,\n\t\t\t\t IXGBE_PCS1GANA_SYM_PAUSE,\n\t\t\t\t IXGBE_PCS1GANA_ASM_PAUSE);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37\n * @hw: pointer to hardware structure\n *\n * Enable flow control according to IEEE clause 37.\n **/\nSTATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)\n{\n\tu32 links2, anlp1_reg, autoc_reg, links;\n\ts32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;\n\n\t/*\n\t * On backplane, bail out if\n\t * - backplane autoneg was not completed, or if\n\t * - we are 82599 and link partner is not AN enabled\n\t */\n\tlinks = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\tif ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {\n\t\tDEBUGOUT(\"Auto-Negotiation did not complete\\n\");\n\t\tgoto out;\n\t}\n\n\tif (hw->mac.type == ixgbe_mac_82599EB) {\n\t\tlinks2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);\n\t\tif ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {\n\t\t\tDEBUGOUT(\"Link partner is not AN enabled\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\t/*\n\t * Read the 10g AN autoc and LP ability registers and resolve\n\t * local flow control settings accordingly\n\t */\n\tautoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tanlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);\n\n\tret_val = ixgbe_negotiate_fc(hw, autoc_reg,\n\t\tanlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,\n\t\tIXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37\n * @hw: pointer to hardware structure\n *\n * Enable flow control according to IEEE clause 37.\n **/\nSTATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)\n{\n\tu16 technology_ability_reg = 0;\n\tu16 lp_technology_ability_reg = 0;\n\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t &technology_ability_reg);\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t &lp_technology_ability_reg);\n\n\treturn ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,\n\t\t\t\t (u32)lp_technology_ability_reg,\n\t\t\t\t IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,\n\t\t\t\t IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);\n}\n\n/**\n * ixgbe_fc_autoneg - Configure flow control\n * @hw: pointer to hardware structure\n *\n * Compares our advertised flow control capabilities to those advertised by\n * our link partner, and determines the proper flow control mode to use.\n **/\nvoid ixgbe_fc_autoneg(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;\n\tixgbe_link_speed speed;\n\tbool link_up;\n\n\tDEBUGFUNC(\"ixgbe_fc_autoneg\");\n\n\t/*\n\t * AN should have completed when the cable was plugged in.\n\t * Look for reasons to bail out. Bail out if:\n\t * - FC autoneg is disabled, or if\n\t * - link is not up.\n\t */\n\tif (hw->fc.disable_fc_autoneg) {\n\t\tERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,\n\t\t\t \"Flow control autoneg is disabled\");\n\t\tgoto out;\n\t}\n\n\thw->mac.ops.check_link(hw, &speed, &link_up, false);\n\tif (!link_up) {\n\t\tERROR_REPORT1(IXGBE_ERROR_SOFTWARE, \"The link is down\");\n\t\tgoto out;\n\t}\n\n\tswitch (hw->phy.media_type) {\n\t/* Autoneg flow control on fiber adapters */\n\tcase ixgbe_media_type_fiber_qsfp:\n\tcase ixgbe_media_type_fiber:\n\t\tif (speed == IXGBE_LINK_SPEED_1GB_FULL)\n\t\t\tret_val = ixgbe_fc_autoneg_fiber(hw);\n\t\tbreak;\n\n\t/* Autoneg flow control on backplane adapters */\n\tcase ixgbe_media_type_backplane:\n\t\tret_val = ixgbe_fc_autoneg_backplane(hw);\n\t\tbreak;\n\n\t/* Autoneg flow control on copper adapters */\n\tcase ixgbe_media_type_copper:\n\t\tif (ixgbe_device_supports_autoneg_fc(hw))\n\t\t\tret_val = ixgbe_fc_autoneg_copper(hw);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\nout:\n\tif (ret_val == IXGBE_SUCCESS) {\n\t\thw->fc.fc_was_autonegged = true;\n\t} else {\n\t\thw->fc.fc_was_autonegged = false;\n\t\thw->fc.current_mode = hw->fc.requested_mode;\n\t}\n}\n\n/*\n * ixgbe_pcie_timeout_poll - Return number of times to poll for completion\n * @hw: pointer to hardware structure\n *\n * System-wide timeout range is encoded in PCIe Device Control2 register.\n *\n * Add 10% to specified maximum and return the number of times to poll for\n * completion timeout, in units of 100 microsec. Never return less than\n * 800 = 80 millisec.\n */\nSTATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)\n{\n\ts16 devctl2;\n\tu32 pollcnt;\n\n\tdevctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);\n\tdevctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;\n\n\tswitch (devctl2) {\n\tcase IXGBE_PCIDEVCTRL2_65_130ms:\n\t\tpollcnt = 1300;\t\t/* 130 millisec */\n\t\tbreak;\n\tcase IXGBE_PCIDEVCTRL2_260_520ms:\n\t\tpollcnt = 5200;\t\t/* 520 millisec */\n\t\tbreak;\n\tcase IXGBE_PCIDEVCTRL2_1_2s:\n\t\tpollcnt = 20000;\t/* 2 sec */\n\t\tbreak;\n\tcase IXGBE_PCIDEVCTRL2_4_8s:\n\t\tpollcnt = 80000;\t/* 8 sec */\n\t\tbreak;\n\tcase IXGBE_PCIDEVCTRL2_17_34s:\n\t\tpollcnt = 34000;\t/* 34 sec */\n\t\tbreak;\n\tcase IXGBE_PCIDEVCTRL2_50_100us:\t/* 100 microsecs */\n\tcase IXGBE_PCIDEVCTRL2_1_2ms:\t\t/* 2 millisecs */\n\tcase IXGBE_PCIDEVCTRL2_16_32ms:\t\t/* 32 millisec */\n\tcase IXGBE_PCIDEVCTRL2_16_32ms_def:\t/* 32 millisec default */\n\tdefault:\n\t\tpollcnt = 800;\t\t/* 80 millisec minimum */\n\t\tbreak;\n\t}\n\n\t/* add 10% to spec maximum */\n\treturn (pollcnt * 11) / 10;\n}\n\n/**\n * ixgbe_disable_pcie_master - Disable PCI-express master access\n * @hw: pointer to hardware structure\n *\n * Disables PCI-Express master access and verifies there are no pending\n * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable\n * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS\n * is returned signifying master requests disabled.\n **/\ns32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu32 i, poll;\n\tu16 value;\n\n\tDEBUGFUNC(\"ixgbe_disable_pcie_master\");\n\n\t/* Always set this bit to ensure any future transactions are blocked */\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);\n\n\t/* Exit if master requests are blocked */\n\tif (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||\n\t IXGBE_REMOVED(hw->hw_addr))\n\t\tgoto out;\n\n\t/* Poll for master request bit to clear */\n\tfor (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {\n\t\tusec_delay(100);\n\t\tif (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))\n\t\t\tgoto out;\n\t}\n\n\t/*\n\t * Two consecutive resets are required via CTRL.RST per datasheet\n\t * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine\n\t * of this need. The first reset prevents new master requests from\n\t * being issued by our device. We then must wait 1usec or more for any\n\t * remaining completions from the PCIe bus to trickle in, and then reset\n\t * again to clear out any effects they may have had on our device.\n\t */\n\tDEBUGOUT(\"GIO Master Disable bit didn't clear - requesting resets\\n\");\n\thw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;\n\n\tif (hw->mac.type >= ixgbe_mac_X550)\n\t\tgoto out;\n\n\t/*\n\t * Before proceeding, make sure that the PCIe block does not have\n\t * transactions pending.\n\t */\n\tpoll = ixgbe_pcie_timeout_poll(hw);\n\tfor (i = 0; i < poll; i++) {\n\t\tusec_delay(100);\n\t\tvalue = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);\n\t\tif (IXGBE_REMOVED(hw->hw_addr))\n\t\t\tgoto out;\n\t\tif (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))\n\t\t\tgoto out;\n\t}\n\n\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n\t\t \"PCIe transaction pending bit also did not clear.\\n\");\n\tstatus = IXGBE_ERR_MASTER_REQUESTS_PENDING;\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to acquire\n *\n * Acquires the SWFW semaphore through the GSSR register for the specified\n * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\ns32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)\n{\n\tu32 gssr = 0;\n\tu32 swmask = mask;\n\tu32 fwmask = mask << 5;\n\tu32 timeout = 200;\n\tu32 i;\n\n\tDEBUGFUNC(\"ixgbe_acquire_swfw_sync\");\n\n\tfor (i = 0; i < timeout; i++) {\n\t\t/*\n\t\t * SW NVM semaphore bit is used for access to all\n\t\t * SW_FW_SYNC bits (not just NVM)\n\t\t */\n\t\tif (ixgbe_get_eeprom_semaphore(hw))\n\t\t\treturn IXGBE_ERR_SWFW_SYNC;\n\n\t\tgssr = IXGBE_READ_REG(hw, IXGBE_GSSR);\n\t\tif (!(gssr & (fwmask | swmask))) {\n\t\t\tgssr |= swmask;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);\n\t\t\tixgbe_release_eeprom_semaphore(hw);\n\t\t\treturn IXGBE_SUCCESS;\n\t\t} else {\n\t\t\t/* Resource is currently in use by FW or SW */\n\t\t\tixgbe_release_eeprom_semaphore(hw);\n\t\t\tmsec_delay(5);\n\t\t}\n\t}\n\n\t/* If time expired clear the bits holding the lock and retry */\n\tif (gssr & (fwmask | swmask))\n\t\tixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));\n\n\tmsec_delay(5);\n\treturn IXGBE_ERR_SWFW_SYNC;\n}\n\n/**\n * ixgbe_release_swfw_sync - Release SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to release\n *\n * Releases the SWFW semaphore through the GSSR register for the specified\n * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\nvoid ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)\n{\n\tu32 gssr;\n\tu32 swmask = mask;\n\n\tDEBUGFUNC(\"ixgbe_release_swfw_sync\");\n\n\tixgbe_get_eeprom_semaphore(hw);\n\n\tgssr = IXGBE_READ_REG(hw, IXGBE_GSSR);\n\tgssr &= ~swmask;\n\tIXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);\n\n\tixgbe_release_eeprom_semaphore(hw);\n}\n\n/**\n * ixgbe_disable_sec_rx_path_generic - Stops the receive data path\n * @hw: pointer to hardware structure\n *\n * Stops the receive data path and waits for the HW to internally empty\n * the Rx security block\n **/\ns32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)\n{\n#define IXGBE_MAX_SECRX_POLL 40\n\n\tint i;\n\tint secrxreg;\n\n\tDEBUGFUNC(\"ixgbe_disable_sec_rx_path_generic\");\n\n\n\tsecrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);\n\tsecrxreg |= IXGBE_SECRXCTRL_RX_DIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);\n\tfor (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {\n\t\tsecrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);\n\t\tif (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)\n\t\t\tbreak;\n\t\telse\n\t\t\t/* Use interrupt-safe sleep just in case */\n\t\t\tusec_delay(1000);\n\t}\n\n\t/* For informational purposes only */\n\tif (i >= IXGBE_MAX_SECRX_POLL)\n\t\tDEBUGOUT(\"Rx unit being enabled before security \"\n\t\t\t \"path fully disabled. Continuing with init.\\n\");\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read\n * @hw: pointer to hardware structure\n * @reg_val: Value we read from AUTOC\n *\n * The default case requires no protection so just to the register read.\n */\ns32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)\n{\n\t*locked = false;\n\t*reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write\n * @hw: pointer to hardware structure\n * @reg_val: value to write to AUTOC\n * @locked: bool to indicate whether the SW/FW lock was already taken by\n * previous read.\n *\n * The default case requires no protection so just to the register write.\n */\ns32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)\n{\n\tUNREFERENCED_1PARAMETER(locked);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_enable_sec_rx_path_generic - Enables the receive data path\n * @hw: pointer to hardware structure\n *\n * Enables the receive data path.\n **/\ns32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)\n{\n\tint secrxreg;\n\n\tDEBUGFUNC(\"ixgbe_enable_sec_rx_path_generic\");\n\n\tsecrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);\n\tsecrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit\n * @hw: pointer to hardware structure\n * @regval: register value to write to RXCTRL\n *\n * Enables the Rx DMA unit\n **/\ns32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)\n{\n\tDEBUGFUNC(\"ixgbe_enable_rx_dma_generic\");\n\n\tif (regval & IXGBE_RXCTRL_RXEN)\n\t\tixgbe_enable_rx(hw);\n\telse\n\t\tixgbe_disable_rx(hw);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_blink_led_start_generic - Blink LED based on index.\n * @hw: pointer to hardware structure\n * @index: led number to blink\n **/\ns32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)\n{\n\tixgbe_link_speed speed = 0;\n\tbool link_up = 0;\n\tu32 autoc_reg = 0;\n\tu32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\ts32 ret_val = IXGBE_SUCCESS;\n\tbool locked = false;\n\n\tDEBUGFUNC(\"ixgbe_blink_led_start_generic\");\n\n\t/*\n\t * Link must be up to auto-blink the LEDs;\n\t * Force it if link is down.\n\t */\n\thw->mac.ops.check_link(hw, &speed, &link_up, false);\n\n\tif (!link_up) {\n\t\tret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);\n\t\tif (ret_val != IXGBE_SUCCESS)\n\t\t\tgoto out;\n\n\t\tautoc_reg |= IXGBE_AUTOC_AN_RESTART;\n\t\tautoc_reg |= IXGBE_AUTOC_FLU;\n\n\t\tret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);\n\t\tif (ret_val != IXGBE_SUCCESS)\n\t\t\tgoto out;\n\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t\tmsec_delay(10);\n\t}\n\n\tled_reg &= ~IXGBE_LED_MODE_MASK(index);\n\tled_reg |= IXGBE_LED_BLINK(index);\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.\n * @hw: pointer to hardware structure\n * @index: led number to stop blinking\n **/\ns32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)\n{\n\tu32 autoc_reg = 0;\n\tu32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\ts32 ret_val = IXGBE_SUCCESS;\n\tbool locked = false;\n\n\tDEBUGFUNC(\"ixgbe_blink_led_stop_generic\");\n\n\tret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);\n\tif (ret_val != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\tautoc_reg &= ~IXGBE_AUTOC_FLU;\n\tautoc_reg |= IXGBE_AUTOC_AN_RESTART;\n\n\tret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);\n\tif (ret_val != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\tled_reg &= ~IXGBE_LED_MODE_MASK(index);\n\tled_reg &= ~IXGBE_LED_BLINK(index);\n\tled_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM\n * @hw: pointer to hardware structure\n * @san_mac_offset: SAN MAC address offset\n *\n * This function will read the EEPROM location for the SAN MAC address\n * pointer, and returns the value at that location. This is used in both\n * get and set mac_addr routines.\n **/\nSTATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *san_mac_offset)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"ixgbe_get_san_mac_addr_offset\");\n\n\t/*\n\t * First read the EEPROM pointer to see if the MAC addresses are\n\t * available.\n\t */\n\tret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,\n\t\t\t\t san_mac_offset);\n\tif (ret_val) {\n\t\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t\t \"eeprom at offset %d failed\",\n\t\t\t IXGBE_SAN_MAC_ADDR_PTR);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM\n * @hw: pointer to hardware structure\n * @san_mac_addr: SAN MAC address\n *\n * Reads the SAN MAC address from the EEPROM, if it's available. This is\n * per-port, so set_lan_id() must be called before reading the addresses.\n * set_lan_id() is called by identify_sfp(), but this cannot be relied\n * upon for non-SFP connections, so we must call it here.\n **/\ns32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)\n{\n\tu16 san_mac_data, san_mac_offset;\n\tu8 i;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"ixgbe_get_san_mac_addr_generic\");\n\n\t/*\n\t * First read the EEPROM pointer to see if the MAC addresses are\n\t * available. If they're not, no point in calling set_lan_id() here.\n\t */\n\tret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);\n\tif (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)\n\t\tgoto san_mac_addr_out;\n\n\t/* make sure we know which port we need to program */\n\thw->mac.ops.set_lan_id(hw);\n\t/* apply the port offset to the address offset */\n\t(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :\n\t\t\t (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);\n\tfor (i = 0; i < 3; i++) {\n\t\tret_val = hw->eeprom.ops.read(hw, san_mac_offset,\n\t\t\t\t\t &san_mac_data);\n\t\tif (ret_val) {\n\t\t\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t\t\t \"eeprom read at offset %d failed\",\n\t\t\t\t san_mac_offset);\n\t\t\tgoto san_mac_addr_out;\n\t\t}\n\t\tsan_mac_addr[i * 2] = (u8)(san_mac_data);\n\t\tsan_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);\n\t\tsan_mac_offset++;\n\t}\n\treturn IXGBE_SUCCESS;\n\nsan_mac_addr_out:\n\t/*\n\t * No addresses available in this EEPROM. It's not an\n\t * error though, so just wipe the local address and return.\n\t */\n\tfor (i = 0; i < 6; i++)\n\t\tsan_mac_addr[i] = 0xFF;\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM\n * @hw: pointer to hardware structure\n * @san_mac_addr: SAN MAC address\n *\n * Write a SAN MAC address to the EEPROM.\n **/\ns32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)\n{\n\ts32 ret_val;\n\tu16 san_mac_data, san_mac_offset;\n\tu8 i;\n\n\tDEBUGFUNC(\"ixgbe_set_san_mac_addr_generic\");\n\n\t/* Look for SAN mac address pointer. If not defined, return */\n\tret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);\n\tif (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)\n\t\treturn IXGBE_ERR_NO_SAN_ADDR_PTR;\n\n\t/* Make sure we know which port we need to write */\n\thw->mac.ops.set_lan_id(hw);\n\t/* Apply the port offset to the address offset */\n\t(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :\n\t\t\t (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);\n\n\tfor (i = 0; i < 3; i++) {\n\t\tsan_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);\n\t\tsan_mac_data |= (u16)(san_mac_addr[i * 2]);\n\t\thw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);\n\t\tsan_mac_offset++;\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count\n * @hw: pointer to hardware structure\n *\n * Read PCIe configuration space, and get the MSI-X vector count from\n * the capabilities table.\n **/\nu16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)\n{\n\tu16 msix_count = 1;\n\tu16 max_msix_count;\n\tu16 pcie_offset;\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tpcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;\n\t\tmax_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tpcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;\n\t\tmax_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;\n\t\tbreak;\n\tdefault:\n\t\treturn msix_count;\n\t}\n\n\tDEBUGFUNC(\"ixgbe_get_pcie_msix_count_generic\");\n\tmsix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);\n\tif (IXGBE_REMOVED(hw->hw_addr))\n\t\tmsix_count = 0;\n\tmsix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;\n\n\t/* MSI-X count is zero-based in HW */\n\tmsix_count++;\n\n\tif (msix_count > max_msix_count)\n\t\tmsix_count = max_msix_count;\n\n\treturn msix_count;\n}\n\n/**\n * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address\n * @hw: pointer to hardware structure\n * @addr: Address to put into receive address register\n * @vmdq: VMDq pool to assign\n *\n * Puts an ethernet address into a receive address register, or\n * finds the rar that it is aleady in; adds to the pool list\n **/\ns32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)\n{\n\tstatic const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;\n\tu32 first_empty_rar = NO_EMPTY_RAR_FOUND;\n\tu32 rar;\n\tu32 rar_low, rar_high;\n\tu32 addr_low, addr_high;\n\n\tDEBUGFUNC(\"ixgbe_insert_mac_addr_generic\");\n\n\t/* swap bytes for HW little endian */\n\taddr_low = addr[0] | (addr[1] << 8)\n\t\t\t | (addr[2] << 16)\n\t\t\t | (addr[3] << 24);\n\taddr_high = addr[4] | (addr[5] << 8);\n\n\t/*\n\t * Either find the mac_id in rar or find the first empty space.\n\t * rar_highwater points to just after the highest currently used\n\t * rar in order to shorten the search. It grows when we add a new\n\t * rar to the top.\n\t */\n\tfor (rar = 0; rar < hw->mac.rar_highwater; rar++) {\n\t\trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));\n\n\t\tif (((IXGBE_RAH_AV & rar_high) == 0)\n\t\t && first_empty_rar == NO_EMPTY_RAR_FOUND) {\n\t\t\tfirst_empty_rar = rar;\n\t\t} else if ((rar_high & 0xFFFF) == addr_high) {\n\t\t\trar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));\n\t\t\tif (rar_low == addr_low)\n\t\t\t\tbreak; /* found it already in the rars */\n\t\t}\n\t}\n\n\tif (rar < hw->mac.rar_highwater) {\n\t\t/* already there so just add to the pool bits */\n\t\tixgbe_set_vmdq(hw, rar, vmdq);\n\t} else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {\n\t\t/* stick it into first empty RAR slot we found */\n\t\trar = first_empty_rar;\n\t\tixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);\n\t} else if (rar == hw->mac.rar_highwater) {\n\t\t/* add it to the top of the list and inc the highwater mark */\n\t\tixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);\n\t\thw->mac.rar_highwater++;\n\t} else if (rar >= hw->mac.num_rar_entries) {\n\t\treturn IXGBE_ERR_INVALID_MAC_ADDR;\n\t}\n\n\t/*\n\t * If we found rar[0], make sure the default pool bit (we use pool 0)\n\t * remains cleared to be sure default pool packets will get delivered\n\t */\n\tif (rar == 0)\n\t\tixgbe_clear_vmdq(hw, rar, 0);\n\n\treturn rar;\n}\n\n/**\n * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address\n * @hw: pointer to hardware struct\n * @rar: receive address register index to disassociate\n * @vmdq: VMDq pool index to remove from the rar\n **/\ns32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n{\n\tu32 mpsar_lo, mpsar_hi;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\tDEBUGFUNC(\"ixgbe_clear_vmdq_generic\");\n\n\t/* Make sure we are using a valid rar index range */\n\tif (rar >= rar_entries) {\n\t\tERROR_REPORT2(IXGBE_ERROR_ARGUMENT,\n\t\t\t \"RAR index %d is out of range.\\n\", rar);\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\tmpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));\n\tmpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));\n\n\tif (IXGBE_REMOVED(hw->hw_addr))\n\t\tgoto done;\n\n\tif (!mpsar_lo && !mpsar_hi)\n\t\tgoto done;\n\n\tif (vmdq == IXGBE_CLEAR_VMDQ_ALL) {\n\t\tif (mpsar_lo) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);\n\t\t\tmpsar_lo = 0;\n\t\t}\n\t\tif (mpsar_hi) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);\n\t\t\tmpsar_hi = 0;\n\t\t}\n\t} else if (vmdq < 32) {\n\t\tmpsar_lo &= ~(1 << vmdq);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);\n\t} else {\n\t\tmpsar_hi &= ~(1 << (vmdq - 32));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);\n\t}\n\n\t/* was that the last pool using this rar? */\n\tif (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)\n\t\thw->mac.ops.clear_rar(hw, rar);\ndone:\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address\n * @hw: pointer to hardware struct\n * @rar: receive address register index to associate with a VMDq index\n * @vmdq: VMDq pool index\n **/\ns32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n{\n\tu32 mpsar;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\tDEBUGFUNC(\"ixgbe_set_vmdq_generic\");\n\n\t/* Make sure we are using a valid rar index range */\n\tif (rar >= rar_entries) {\n\t\tERROR_REPORT2(IXGBE_ERROR_ARGUMENT,\n\t\t\t \"RAR index %d is out of range.\\n\", rar);\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\tif (vmdq < 32) {\n\t\tmpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));\n\t\tmpsar |= 1 << vmdq;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);\n\t} else {\n\t\tmpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));\n\t\tmpsar |= 1 << (vmdq - 32);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);\n\t}\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * This function should only be involved in the IOV mode.\n * In IOV mode, Default pool is next pool after the number of\n * VFs advertized and not 0.\n * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]\n *\n * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address\n * @hw: pointer to hardware struct\n * @vmdq: VMDq pool index\n **/\ns32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)\n{\n\tu32 rar = hw->mac.san_mac_rar_index;\n\n\tDEBUGFUNC(\"ixgbe_set_vmdq_san_mac\");\n\n\tif (vmdq < 32) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);\n\t} else {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)\n{\n\tint i;\n\n\tDEBUGFUNC(\"ixgbe_init_uta_tables_generic\");\n\tDEBUGOUT(\" Clearing UTA\\n\");\n\n\tfor (i = 0; i < 128; i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot\n * @hw: pointer to hardware structure\n * @vlan: VLAN id to write to VLAN filter\n *\n * return the VLVF index where this VLAN id should be placed\n *\n **/\ns32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)\n{\n\tu32 bits = 0;\n\tu32 first_empty_slot = 0;\n\ts32 regindex;\n\n\t/* short cut the special case */\n\tif (vlan == 0)\n\t\treturn 0;\n\n\t/*\n\t * Search for the vlan id in the VLVF entries. Save off the first empty\n\t * slot found along the way\n\t */\n\tfor (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {\n\t\tbits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));\n\t\tif (!bits && !(first_empty_slot))\n\t\t\tfirst_empty_slot = regindex;\n\t\telse if ((bits & 0x0FFF) == vlan)\n\t\t\tbreak;\n\t}\n\n\t/*\n\t * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan\n\t * in the VLVF. Else use the first empty VLVF register for this\n\t * vlan id.\n\t */\n\tif (regindex >= IXGBE_VLVF_ENTRIES) {\n\t\tif (first_empty_slot)\n\t\t\tregindex = first_empty_slot;\n\t\telse {\n\t\t\tERROR_REPORT1(IXGBE_ERROR_SOFTWARE,\n\t\t\t\t \"No space in VLVF.\\n\");\n\t\t\tregindex = IXGBE_ERR_NO_SPACE;\n\t\t}\n\t}\n\n\treturn regindex;\n}\n\n/**\n * ixgbe_set_vfta_generic - Set VLAN filter table\n * @hw: pointer to hardware structure\n * @vlan: VLAN id to write to VLAN filter\n * @vind: VMDq output index that maps queue to VLAN id in VFVFB\n * @vlan_on: boolean flag to turn on/off VLAN in VFVF\n *\n * Turn on/off specified VLAN in the VLAN filter table.\n **/\ns32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n\t\t\t bool vlan_on)\n{\n\ts32 regindex;\n\tu32 bitindex;\n\tu32 vfta;\n\tu32 targetbit;\n\ts32 ret_val = IXGBE_SUCCESS;\n\tbool vfta_changed = false;\n\n\tDEBUGFUNC(\"ixgbe_set_vfta_generic\");\n\n\tif (vlan > 4095)\n\t\treturn IXGBE_ERR_PARAM;\n\n\t/*\n\t * this is a 2 part operation - first the VFTA, then the\n\t * VLVF and VLVFB if VT Mode is set\n\t * We don't write the VFTA until we know the VLVF part succeeded.\n\t */\n\n\t/* Part 1\n\t * The VFTA is a bitstring made up of 128 32-bit registers\n\t * that enable the particular VLAN id, much like the MTA:\n\t * bits[11-5]: which register\n\t * bits[4-0]: which bit in the register\n\t */\n\tregindex = (vlan >> 5) & 0x7F;\n\tbitindex = vlan & 0x1F;\n\ttargetbit = (1 << bitindex);\n\tvfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));\n\n\tif (vlan_on) {\n\t\tif (!(vfta & targetbit)) {\n\t\t\tvfta |= targetbit;\n\t\t\tvfta_changed = true;\n\t\t}\n\t} else {\n\t\tif ((vfta & targetbit)) {\n\t\t\tvfta &= ~targetbit;\n\t\t\tvfta_changed = true;\n\t\t}\n\t}\n\n\t/* Part 2\n\t * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF\n\t */\n\tret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,\n\t\t\t\t\t &vfta_changed);\n\tif (ret_val != IXGBE_SUCCESS)\n\t\treturn ret_val;\n\n\tif (vfta_changed)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_set_vlvf_generic - Set VLAN Pool Filter\n * @hw: pointer to hardware structure\n * @vlan: VLAN id to write to VLAN filter\n * @vind: VMDq output index that maps queue to VLAN id in VFVFB\n * @vlan_on: boolean flag to turn on/off VLAN in VFVF\n * @vfta_changed: pointer to boolean flag which indicates whether VFTA\n * should be changed\n *\n * Turn on/off specified bit in VLVF table.\n **/\ns32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n\t\t\t bool vlan_on, bool *vfta_changed)\n{\n\tu32 vt;\n\n\tDEBUGFUNC(\"ixgbe_set_vlvf_generic\");\n\n\tif (vlan > 4095)\n\t\treturn IXGBE_ERR_PARAM;\n\n\t/* If VT Mode is set\n\t * Either vlan_on\n\t * make sure the vlan is in VLVF\n\t * set the vind bit in the matching VLVFB\n\t * Or !vlan_on\n\t * clear the pool bit and possibly the vind\n\t */\n\tvt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);\n\tif (vt & IXGBE_VT_CTL_VT_ENABLE) {\n\t\ts32 vlvf_index;\n\t\tu32 bits;\n\n\t\tvlvf_index = ixgbe_find_vlvf_slot(hw, vlan);\n\t\tif (vlvf_index < 0)\n\t\t\treturn vlvf_index;\n\n\t\tif (vlan_on) {\n\t\t\t/* set the pool bit */\n\t\t\tif (vind < 32) {\n\t\t\t\tbits = IXGBE_READ_REG(hw,\n\t\t\t\t\t\tIXGBE_VLVFB(vlvf_index * 2));\n\t\t\t\tbits |= (1 << vind);\n\t\t\t\tIXGBE_WRITE_REG(hw,\n\t\t\t\t\t\tIXGBE_VLVFB(vlvf_index * 2),\n\t\t\t\t\t\tbits);\n\t\t\t} else {\n\t\t\t\tbits = IXGBE_READ_REG(hw,\n\t\t\t\t\tIXGBE_VLVFB((vlvf_index * 2) + 1));\n\t\t\t\tbits |= (1 << (vind - 32));\n\t\t\t\tIXGBE_WRITE_REG(hw,\n\t\t\t\t\tIXGBE_VLVFB((vlvf_index * 2) + 1),\n\t\t\t\t\tbits);\n\t\t\t}\n\t\t} else {\n\t\t\t/* clear the pool bit */\n\t\t\tif (vind < 32) {\n\t\t\t\tbits = IXGBE_READ_REG(hw,\n\t\t\t\t\t\tIXGBE_VLVFB(vlvf_index * 2));\n\t\t\t\tbits &= ~(1 << vind);\n\t\t\t\tIXGBE_WRITE_REG(hw,\n\t\t\t\t\t\tIXGBE_VLVFB(vlvf_index * 2),\n\t\t\t\t\t\tbits);\n\t\t\t\tbits |= IXGBE_READ_REG(hw,\n\t\t\t\t\tIXGBE_VLVFB((vlvf_index * 2) + 1));\n\t\t\t} else {\n\t\t\t\tbits = IXGBE_READ_REG(hw,\n\t\t\t\t\tIXGBE_VLVFB((vlvf_index * 2) + 1));\n\t\t\t\tbits &= ~(1 << (vind - 32));\n\t\t\t\tIXGBE_WRITE_REG(hw,\n\t\t\t\t\tIXGBE_VLVFB((vlvf_index * 2) + 1),\n\t\t\t\t\tbits);\n\t\t\t\tbits |= IXGBE_READ_REG(hw,\n\t\t\t\t\t\tIXGBE_VLVFB(vlvf_index * 2));\n\t\t\t}\n\t\t}\n\n\t\t/*\n\t\t * If there are still bits set in the VLVFB registers\n\t\t * for the VLAN ID indicated we need to see if the\n\t\t * caller is requesting that we clear the VFTA entry bit.\n\t\t * If the caller has requested that we clear the VFTA\n\t\t * entry bit but there are still pools/VFs using this VLAN\n\t\t * ID entry then ignore the request. We're not worried\n\t\t * about the case where we're turning the VFTA VLAN ID\n\t\t * entry bit on, only when requested to turn it off as\n\t\t * there may be multiple pools and/or VFs using the\n\t\t * VLAN ID entry. In that case we cannot clear the\n\t\t * VFTA bit until all pools/VFs using that VLAN ID have also\n\t\t * been cleared. This will be indicated by \"bits\" being\n\t\t * zero.\n\t\t */\n\t\tif (bits) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),\n\t\t\t\t\t(IXGBE_VLVF_VIEN | vlan));\n\t\t\tif ((!vlan_on) && (vfta_changed != NULL)) {\n\t\t\t\t/* someone wants to clear the vfta entry\n\t\t\t\t * but some pools/VFs are still using it.\n\t\t\t\t * Ignore it. */\n\t\t\t\t*vfta_changed = false;\n\t\t\t}\n\t\t} else\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_clear_vfta_generic - Clear VLAN filter table\n * @hw: pointer to hardware structure\n *\n * Clears the VLAN filer table, and the VMDq index associated with the filter\n **/\ns32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)\n{\n\tu32 offset;\n\n\tDEBUGFUNC(\"ixgbe_clear_vfta_generic\");\n\n\tfor (offset = 0; offset < hw->mac.vft_size; offset++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);\n\n\tfor (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_check_mac_link_generic - Determine link and speed status\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @link_up: true when link is up\n * @link_up_wait_to_complete: bool used to wait for link up or not\n *\n * Reads the links register to determine if link is up and the current speed\n **/\ns32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t\t bool *link_up, bool link_up_wait_to_complete)\n{\n\tu32 links_reg, links_orig;\n\tu32 i;\n\n\tDEBUGFUNC(\"ixgbe_check_mac_link_generic\");\n\n\t/* clear the old state */\n\tlinks_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\n\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\n\tif (links_orig != links_reg) {\n\t\tDEBUGOUT2(\"LINKS changed from %08X to %08X\\n\",\n\t\t\t links_orig, links_reg);\n\t}\n\n\tif (link_up_wait_to_complete) {\n\t\tfor (i = 0; i < hw->mac.max_link_up_time; i++) {\n\t\t\tif (links_reg & IXGBE_LINKS_UP) {\n\t\t\t\t*link_up = true;\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\t*link_up = false;\n\t\t\t}\n\t\t\tmsec_delay(100);\n\t\t\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\t\t}\n\t} else {\n\t\tif (links_reg & IXGBE_LINKS_UP)\n\t\t\t*link_up = true;\n\t\telse\n\t\t\t*link_up = false;\n\t}\n\n\tswitch (links_reg & IXGBE_LINKS_SPEED_82599) {\n\tcase IXGBE_LINKS_SPEED_10G_82599:\n\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (hw->mac.type >= ixgbe_mac_X550) {\n\t\t\tif (links_reg & IXGBE_LINKS_SPEED_NON_STD)\n\t\t\t\t*speed = IXGBE_LINK_SPEED_2_5GB_FULL;\n\t\t}\n\t\tbreak;\n\tcase IXGBE_LINKS_SPEED_1G_82599:\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\tbreak;\n\tcase IXGBE_LINKS_SPEED_100_82599:\n\t\t*speed = IXGBE_LINK_SPEED_100_FULL;\n\t\tif (hw->mac.type >= ixgbe_mac_X550) {\n\t\t\tif (links_reg & IXGBE_LINKS_SPEED_NON_STD)\n\t\t\t\t*speed = IXGBE_LINK_SPEED_5GB_FULL;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\t*speed = IXGBE_LINK_SPEED_UNKNOWN;\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from\n * the EEPROM\n * @hw: pointer to hardware structure\n * @wwnn_prefix: the alternative WWNN prefix\n * @wwpn_prefix: the alternative WWPN prefix\n *\n * This function will read the EEPROM from the alternative SAN MAC address\n * block to check the support for the alternative WWNN/WWPN prefix support.\n **/\ns32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n\t\t\t\t u16 *wwpn_prefix)\n{\n\tu16 offset, caps;\n\tu16 alt_san_mac_blk_offset;\n\n\tDEBUGFUNC(\"ixgbe_get_wwn_prefix_generic\");\n\n\t/* clear output first */\n\t*wwnn_prefix = 0xFFFF;\n\t*wwpn_prefix = 0xFFFF;\n\n\t/* check if alternative SAN MAC is supported */\n\toffset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;\n\tif (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))\n\t\tgoto wwn_prefix_err;\n\n\tif ((alt_san_mac_blk_offset == 0) ||\n\t (alt_san_mac_blk_offset == 0xFFFF))\n\t\tgoto wwn_prefix_out;\n\n\t/* check capability in alternative san mac address block */\n\toffset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;\n\tif (hw->eeprom.ops.read(hw, offset, &caps))\n\t\tgoto wwn_prefix_err;\n\tif (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))\n\t\tgoto wwn_prefix_out;\n\n\t/* get the corresponding prefix for WWNN/WWPN */\n\toffset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;\n\tif (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {\n\t\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t\t \"eeprom read at offset %d failed\", offset);\n\t}\n\n\toffset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;\n\tif (hw->eeprom.ops.read(hw, offset, wwpn_prefix))\n\t\tgoto wwn_prefix_err;\n\nwwn_prefix_out:\n\treturn IXGBE_SUCCESS;\n\nwwn_prefix_err:\n\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t \"eeprom read at offset %d failed\", offset);\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM\n * @hw: pointer to hardware structure\n * @bs: the fcoe boot status\n *\n * This function will read the FCOE boot status from the iSCSI FCOE block\n **/\ns32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)\n{\n\tu16 offset, caps, flags;\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_get_fcoe_boot_status_generic\");\n\n\t/* clear output first */\n\t*bs = ixgbe_fcoe_bootstatus_unavailable;\n\n\t/* check if FCOE IBA block is present */\n\toffset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;\n\tstatus = hw->eeprom.ops.read(hw, offset, &caps);\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\tif (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))\n\t\tgoto out;\n\n\t/* check if iSCSI FCOE block is populated */\n\tstatus = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\tif ((offset == 0) || (offset == 0xFFFF))\n\t\tgoto out;\n\n\t/* read fcoe flags in iSCSI FCOE block */\n\toffset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;\n\tstatus = hw->eeprom.ops.read(hw, offset, &flags);\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\tif (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)\n\t\t*bs = ixgbe_fcoe_bootstatus_enabled;\n\telse\n\t\t*bs = ixgbe_fcoe_bootstatus_disabled;\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing\n * @hw: pointer to hardware structure\n * @enable: enable or disable switch for anti-spoofing\n * @pf: Physical Function pool - do not enable anti-spoofing for the PF\n *\n **/\nvoid ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)\n{\n\tint j;\n\tint pf_target_reg = pf >> 3;\n\tint pf_target_shift = pf % 8;\n\tu32 pfvfspoof = 0;\n\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\treturn;\n\n\tif (enable)\n\t\tpfvfspoof = IXGBE_SPOOF_MACAS_MASK;\n\n\t/*\n\t * PFVFSPOOF register array is size 8 with 8 bits assigned to\n\t * MAC anti-spoof enables in each register array element.\n\t */\n\tfor (j = 0; j < pf_target_reg; j++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);\n\n\t/*\n\t * The PF should be allowed to spoof so that it can support\n\t * emulation mode NICs. Do not set the bits assigned to the PF\n\t */\n\tpfvfspoof &= (1 << pf_target_shift) - 1;\n\tIXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);\n\n\t/*\n\t * Remaining pools belong to the PF so they do not need to have\n\t * anti-spoofing enabled.\n\t */\n\tfor (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);\n}\n\n/**\n * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing\n * @hw: pointer to hardware structure\n * @enable: enable or disable switch for VLAN anti-spoofing\n * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing\n *\n **/\nvoid ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)\n{\n\tint vf_target_reg = vf >> 3;\n\tint vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;\n\tu32 pfvfspoof;\n\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\treturn;\n\n\tpfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));\n\tif (enable)\n\t\tpfvfspoof |= (1 << vf_target_shift);\n\telse\n\t\tpfvfspoof &= ~(1 << vf_target_shift);\n\tIXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);\n}\n\n/**\n * ixgbe_get_device_caps_generic - Get additional device capabilities\n * @hw: pointer to hardware structure\n * @device_caps: the EEPROM word with the extra device capabilities\n *\n * This function will read the EEPROM location for the device capabilities,\n * and return the word through device_caps.\n **/\ns32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)\n{\n\tDEBUGFUNC(\"ixgbe_get_device_caps_generic\");\n\n\thw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering\n * @hw: pointer to hardware structure\n *\n **/\nvoid ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)\n{\n\tu32 regval;\n\tu32 i;\n\n\tDEBUGFUNC(\"ixgbe_enable_relaxed_ordering_gen2\");\n\n\t/* Enable relaxed ordering */\n\tfor (i = 0; i < hw->mac.max_tx_queues; i++) {\n\t\tregval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));\n\t\tregval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);\n\t}\n\n\tfor (i = 0; i < hw->mac.max_rx_queues; i++) {\n\t\tregval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));\n\t\tregval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |\n\t\t\t IXGBE_DCA_RXCTRL_HEAD_WRO_EN;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);\n\t}\n\n}\n\n/**\n * ixgbe_calculate_checksum - Calculate checksum for buffer\n * @buffer: pointer to EEPROM\n * @length: size of EEPROM to calculate a checksum for\n * Calculates the checksum for some buffer on a specified length. The\n * checksum calculated is returned.\n **/\nu8 ixgbe_calculate_checksum(u8 *buffer, u32 length)\n{\n\tu32 i;\n\tu8 sum = 0;\n\n\tDEBUGFUNC(\"ixgbe_calculate_checksum\");\n\n\tif (!buffer)\n\t\treturn 0;\n\n\tfor (i = 0; i < length; i++)\n\t\tsum += buffer[i];\n\n\treturn (u8) (0 - sum);\n}\n\n/**\n * ixgbe_host_interface_command - Issue command to manageability block\n * @hw: pointer to the HW structure\n * @buffer: contains the command to write and where the return status will\n * be placed\n * @length: length of buffer, must be multiple of 4 bytes\n * @timeout: time in ms to wait for command completion\n * @return_data: read and return data from the buffer (true) or not (false)\n * Needed because FW structures are big endian and decoding of\n * these fields can be 8 bit or 16 bit based on command. Decoding\n * is not easily understood without making a table of commands.\n * So we will leave this up to the caller to read back the data\n * in these cases.\n *\n * Communicates with the manageability block. On success return IXGBE_SUCCESS\n * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.\n **/\ns32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,\n\t\t\t\t u32 length, u32 timeout, bool return_data)\n{\n\tu32 hicr, i, bi, fwsts;\n\tu32 hdr_size = sizeof(struct ixgbe_hic_hdr);\n\tu16 buf_len;\n\tu16 dword_len;\n\n\tDEBUGFUNC(\"ixgbe_host_interface_command\");\n\n\tif (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {\n\t\tDEBUGOUT1(\"Buffer length failure buffersize=%d.\\n\", length);\n\t\treturn IXGBE_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\t/* Set bit 9 of FWSTS clearing FW reset indication */\n\tfwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);\n\tIXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);\n\n\t/* Check that the host interface is enabled. */\n\thicr = IXGBE_READ_REG(hw, IXGBE_HICR);\n\tif ((hicr & IXGBE_HICR_EN) == 0) {\n\t\tDEBUGOUT(\"IXGBE_HOST_EN bit disabled.\\n\");\n\t\treturn IXGBE_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\t/* Calculate length in DWORDs. We must be DWORD aligned */\n\tif ((length % (sizeof(u32))) != 0) {\n\t\tDEBUGOUT(\"Buffer length failure, not aligned to dword\");\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\tdword_len = length >> 2;\n\n\t/* The device driver writes the relevant command block\n\t * into the ram area.\n\t */\n\tfor (i = 0; i < dword_len; i++)\n\t\tIXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,\n\t\t\t\t i, IXGBE_CPU_TO_LE32(buffer[i]));\n\n\t/* Setting this bit tells the ARC that a new command is pending. */\n\tIXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);\n\n\tfor (i = 0; i < timeout; i++) {\n\t\thicr = IXGBE_READ_REG(hw, IXGBE_HICR);\n\t\tif (!(hicr & IXGBE_HICR_C))\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t}\n\n\t/* Check command completion */\n\tif ((timeout != 0 && i == timeout) ||\n\t !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {\n\t\tERROR_REPORT1(IXGBE_ERROR_CAUTION,\n\t\t\t \"Command has failed with no status valid.\\n\");\n\t\treturn IXGBE_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\tif (!return_data)\n\t\treturn 0;\n\n\t/* Calculate length in DWORDs */\n\tdword_len = hdr_size >> 2;\n\n\t/* first pull in the header so we know the buffer length */\n\tfor (bi = 0; bi < dword_len; bi++) {\n\t\tbuffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);\n\t\tIXGBE_LE32_TO_CPUS(&buffer[bi]);\n\t}\n\n\t/* If there is any thing in data position pull it in */\n\tbuf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;\n\tif (buf_len == 0)\n\t\treturn 0;\n\n\tif (length < buf_len + hdr_size) {\n\t\tDEBUGOUT(\"Buffer not large enough for reply message.\\n\");\n\t\treturn IXGBE_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\t/* Calculate length in DWORDs, add 3 for odd lengths */\n\tdword_len = (buf_len + 3) >> 2;\n\n\t/* Pull in the rest of the buffer (bi is where we left off) */\n\tfor (; bi <= dword_len; bi++) {\n\t\tbuffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);\n\t\tIXGBE_LE32_TO_CPUS(&buffer[bi]);\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware\n * @hw: pointer to the HW structure\n * @maj: driver version major number\n * @min: driver version minor number\n * @build: driver version build number\n * @sub: driver version sub build number\n *\n * Sends driver version number to firmware through the manageability\n * block. On success return IXGBE_SUCCESS\n * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring\n * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n **/\ns32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,\n\t\t\t\t u8 build, u8 sub)\n{\n\tstruct ixgbe_hic_drv_info fw_cmd;\n\tint i;\n\ts32 ret_val = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_set_fw_drv_ver_generic\");\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)\n\t != IXGBE_SUCCESS) {\n\t\tret_val = IXGBE_ERR_SWFW_SYNC;\n\t\tgoto out;\n\t}\n\n\tfw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;\n\tfw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;\n\tfw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;\n\tfw_cmd.port_num = (u8)hw->bus.func;\n\tfw_cmd.ver_maj = maj;\n\tfw_cmd.ver_min = min;\n\tfw_cmd.ver_build = build;\n\tfw_cmd.ver_sub = sub;\n\tfw_cmd.hdr.checksum = 0;\n\tfw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,\n\t\t\t\t(FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));\n\tfw_cmd.pad = 0;\n\tfw_cmd.pad2 = 0;\n\n\tfor (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {\n\t\tret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,\n\t\t\t\t\t\t sizeof(fw_cmd),\n\t\t\t\t\t\t IXGBE_HI_COMMAND_TIMEOUT,\n\t\t\t\t\t\t true);\n\t\tif (ret_val != IXGBE_SUCCESS)\n\t\t\tcontinue;\n\n\t\tif (fw_cmd.hdr.cmd_or_resp.ret_status ==\n\t\t FW_CEM_RESP_STATUS_SUCCESS)\n\t\t\tret_val = IXGBE_SUCCESS;\n\t\telse\n\t\t\tret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;\n\n\t\tbreak;\n\t}\n\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_set_rxpba_generic - Initialize Rx packet buffer\n * @hw: pointer to hardware structure\n * @num_pb: number of packet buffers to allocate\n * @headroom: reserve n KB of headroom\n * @strategy: packet buffer allocation strategy\n **/\nvoid ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,\n\t\t\t int strategy)\n{\n\tu32 pbsize = hw->mac.rx_pb_size;\n\tint i = 0;\n\tu32 rxpktsize, txpktsize, txpbthresh;\n\n\t/* Reserve headroom */\n\tpbsize -= headroom;\n\n\tif (!num_pb)\n\t\tnum_pb = 1;\n\n\t/* Divide remaining packet buffer space amongst the number of packet\n\t * buffers requested using supplied strategy.\n\t */\n\tswitch (strategy) {\n\tcase PBA_STRATEGY_WEIGHTED:\n\t\t/* ixgbe_dcb_pba_80_48 strategy weight first half of packet\n\t\t * buffer with 5/8 of the packet buffer space.\n\t\t */\n\t\trxpktsize = (pbsize * 5) / (num_pb * 4);\n\t\tpbsize -= rxpktsize * (num_pb / 2);\n\t\trxpktsize <<= IXGBE_RXPBSIZE_SHIFT;\n\t\tfor (; i < (num_pb / 2); i++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);\n\t\t/* Fall through to configure remaining packet buffers */\n\tcase PBA_STRATEGY_EQUAL:\n\t\trxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;\n\t\tfor (; i < num_pb; i++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Only support an equally distributed Tx packet buffer strategy. */\n\ttxpktsize = IXGBE_TXPBSIZE_MAX / num_pb;\n\ttxpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;\n\tfor (i = 0; i < num_pb; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);\n\t}\n\n\t/* Clear unused TCs, if any, to zero buffer size*/\n\tfor (; i < IXGBE_MAX_PB; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);\n\t}\n}\n\n/**\n * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo\n * @hw: pointer to the hardware structure\n *\n * The 82599 and x540 MACs can experience issues if TX work is still pending\n * when a reset occurs. This function prevents this by flushing the PCIe\n * buffers on the system.\n **/\nvoid ixgbe_clear_tx_pending(struct ixgbe_hw *hw)\n{\n\tu32 gcr_ext, hlreg0, i, poll;\n\tu16 value;\n\n\t/*\n\t * If double reset is not requested then all transactions should\n\t * already be clear and as such there is no work to do\n\t */\n\tif (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))\n\t\treturn;\n\n\t/*\n\t * Set loopback enable to prevent any transmits from being sent\n\t * should the link come up. This assumes that the RXCTRL.RXEN bit\n\t * has already been cleared.\n\t */\n\thlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);\n\tIXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);\n\n\t/* Wait for a last completion before clearing buffers */\n\tIXGBE_WRITE_FLUSH(hw);\n\tmsec_delay(3);\n\n\t/*\n\t * Before proceeding, make sure that the PCIe block does not have\n\t * transactions pending.\n\t */\n\tpoll = ixgbe_pcie_timeout_poll(hw);\n\tfor (i = 0; i < poll; i++) {\n\t\tusec_delay(100);\n\t\tvalue = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);\n\t\tif (IXGBE_REMOVED(hw->hw_addr))\n\t\t\tgoto out;\n\t\tif (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))\n\t\t\tgoto out;\n\t}\n\nout:\n\t/* initiate cleaning flow for buffers in the PCIe transaction layer */\n\tgcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);\n\tIXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,\n\t\t\tgcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);\n\n\t/* Flush all writes and allow 20usec for all transactions to clear */\n\tIXGBE_WRITE_FLUSH(hw);\n\tusec_delay(20);\n\n\t/* restore previous register values */\n\tIXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);\n\tIXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);\n}\n\nSTATIC const u8 ixgbe_emc_temp_data[4] = {\n\tIXGBE_EMC_INTERNAL_DATA,\n\tIXGBE_EMC_DIODE1_DATA,\n\tIXGBE_EMC_DIODE2_DATA,\n\tIXGBE_EMC_DIODE3_DATA\n};\nSTATIC const u8 ixgbe_emc_therm_limit[4] = {\n\tIXGBE_EMC_INTERNAL_THERM_LIMIT,\n\tIXGBE_EMC_DIODE1_THERM_LIMIT,\n\tIXGBE_EMC_DIODE2_THERM_LIMIT,\n\tIXGBE_EMC_DIODE3_THERM_LIMIT\n};\n\n/**\n * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data\n * @hw: pointer to hardware structure\n * @data: pointer to the thermal sensor data structure\n *\n * Returns the thermal sensor data structure\n **/\ns32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu16 ets_offset;\n\tu16 ets_cfg;\n\tu16 ets_sensor;\n\tu8 num_sensors;\n\tu8 sensor_index;\n\tu8 sensor_location;\n\tu8 i;\n\tstruct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;\n\n\tDEBUGFUNC(\"ixgbe_get_thermal_sensor_data_generic\");\n\n\t/* Only support thermal sensors attached to 82599 physical port 0 */\n\tif ((hw->mac.type != ixgbe_mac_82599EB) ||\n\t (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {\n\t\tstatus = IXGBE_NOT_IMPLEMENTED;\n\t\tgoto out;\n\t}\n\n\tstatus = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);\n\tif (status)\n\t\tgoto out;\n\n\tif ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {\n\t\tstatus = IXGBE_NOT_IMPLEMENTED;\n\t\tgoto out;\n\t}\n\n\tstatus = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);\n\tif (status)\n\t\tgoto out;\n\n\tif (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)\n\t\t!= IXGBE_ETS_TYPE_EMC) {\n\t\tstatus = IXGBE_NOT_IMPLEMENTED;\n\t\tgoto out;\n\t}\n\n\tnum_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);\n\tif (num_sensors > IXGBE_MAX_SENSORS)\n\t\tnum_sensors = IXGBE_MAX_SENSORS;\n\n\tfor (i = 0; i < num_sensors; i++) {\n\t\tstatus = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),\n\t\t\t\t\t &ets_sensor);\n\t\tif (status)\n\t\t\tgoto out;\n\n\t\tsensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>\n\t\t\t\tIXGBE_ETS_DATA_INDEX_SHIFT);\n\t\tsensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>\n\t\t\t\t IXGBE_ETS_DATA_LOC_SHIFT);\n\n\t\tif (sensor_location != 0) {\n\t\t\tstatus = hw->phy.ops.read_i2c_byte(hw,\n\t\t\t\t\tixgbe_emc_temp_data[sensor_index],\n\t\t\t\t\tIXGBE_I2C_THERMAL_SENSOR_ADDR,\n\t\t\t\t\t&data->sensor[i].temp);\n\t\t\tif (status)\n\t\t\t\tgoto out;\n\t\t}\n\t}\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds\n * @hw: pointer to hardware structure\n *\n * Inits the thermal sensor thresholds according to the NVM map\n * and save off the threshold and location values into mac.thermal_sensor_data\n **/\ns32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu16 offset;\n\tu16 ets_offset;\n\tu16 ets_cfg;\n\tu16 ets_sensor;\n\tu8 low_thresh_delta;\n\tu8 num_sensors;\n\tu8 sensor_index;\n\tu8 sensor_location;\n\tu8 therm_limit;\n\tu8 i;\n\tstruct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;\n\n\tDEBUGFUNC(\"ixgbe_init_thermal_sensor_thresh_generic\");\n\n\tmemset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));\n\n\t/* Only support thermal sensors attached to 82599 physical port 0 */\n\tif ((hw->mac.type != ixgbe_mac_82599EB) ||\n\t (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))\n\t\treturn IXGBE_NOT_IMPLEMENTED;\n\n\toffset = IXGBE_ETS_CFG;\n\tif (hw->eeprom.ops.read(hw, offset, &ets_offset))\n\t\tgoto eeprom_err;\n\tif ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))\n\t\treturn IXGBE_NOT_IMPLEMENTED;\n\n\toffset = ets_offset;\n\tif (hw->eeprom.ops.read(hw, offset, &ets_cfg))\n\t\tgoto eeprom_err;\n\tif (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)\n\t\t!= IXGBE_ETS_TYPE_EMC)\n\t\treturn IXGBE_NOT_IMPLEMENTED;\n\n\tlow_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>\n\t\t\t IXGBE_ETS_LTHRES_DELTA_SHIFT);\n\tnum_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);\n\n\tfor (i = 0; i < num_sensors; i++) {\n\t\toffset = ets_offset + 1 + i;\n\t\tif (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {\n\t\t\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t\t\t \"eeprom read at offset %d failed\",\n\t\t\t\t offset);\n\t\t\tcontinue;\n\t\t}\n\t\tsensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>\n\t\t\t\tIXGBE_ETS_DATA_INDEX_SHIFT);\n\t\tsensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>\n\t\t\t\t IXGBE_ETS_DATA_LOC_SHIFT);\n\t\ttherm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;\n\n\t\thw->phy.ops.write_i2c_byte(hw,\n\t\t\tixgbe_emc_therm_limit[sensor_index],\n\t\t\tIXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);\n\n\t\tif ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {\n\t\t\tdata->sensor[i].location = sensor_location;\n\t\t\tdata->sensor[i].caution_thresh = therm_limit;\n\t\t\tdata->sensor[i].max_op_thresh = therm_limit -\n\t\t\t\t\t\t\tlow_thresh_delta;\n\t\t}\n\t}\n\treturn status;\n\neeprom_err:\n\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t \"eeprom read at offset %d failed\", offset);\n\treturn IXGBE_NOT_IMPLEMENTED;\n}\n\n\n/**\n * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg\n * @hw: pointer to hardware structure\n * @map: pointer to u8 arr for returning map\n *\n * Read the rtrup2tc HW register and resolve its content into map\n **/\nvoid ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)\n{\n\tu32 reg, i;\n\n\treg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);\n\tfor (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)\n\t\tmap[i] = IXGBE_RTRUP2TC_UP_MASK &\n\t\t\t(reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));\n\treturn;\n}\n\nvoid ixgbe_disable_rx_generic(struct ixgbe_hw *hw)\n{\n\tu32 pfdtxgswc;\n\tu32 rxctrl;\n\n\trxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n\tif (rxctrl & IXGBE_RXCTRL_RXEN) {\n\t\tif (hw->mac.type != ixgbe_mac_82598EB) {\n\t\t\tpfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);\n\t\t\tif (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {\n\t\t\t\tpfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;\n\t\t\t\tIXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);\n\t\t\t\thw->mac.set_lben = true;\n\t\t\t} else {\n\t\t\t\thw->mac.set_lben = false;\n\t\t\t}\n\t\t}\n\t\trxctrl &= ~IXGBE_RXCTRL_RXEN;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);\n\t}\n}\n\nvoid ixgbe_enable_rx_generic(struct ixgbe_hw *hw)\n{\n\tu32 pfdtxgswc;\n\tu32 rxctrl;\n\n\trxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n\tIXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));\n\n\tif (hw->mac.type != ixgbe_mac_82598EB) {\n\t\tif (hw->mac.set_lben) {\n\t\t\tpfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);\n\t\t\tpfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);\n\t\t\thw->mac.set_lben = false;\n\t\t}\n\t}\n}\n\n/**\n * ixgbe_mng_present - returns true when management capability is present\n * @hw: pointer to hardware structure\n */\nbool ixgbe_mng_present(struct ixgbe_hw *hw)\n{\n\tu32 fwsm;\n\n\tif (hw->mac.type < ixgbe_mac_82599EB)\n\t\treturn false;\n\n\tfwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);\n\tfwsm &= IXGBE_FWSM_MODE_MASK;\n\treturn fwsm == IXGBE_FWSM_FW_MODE_PT;\n}\n\n/**\n * ixgbe_mng_enabled - Is the manageability engine enabled?\n * @hw: pointer to hardware structure\n *\n * Returns true if the manageability engine is enabled.\n **/\nbool ixgbe_mng_enabled(struct ixgbe_hw *hw)\n{\n\tu32 fwsm, manc, factps;\n\n\tfwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);\n\tif ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)\n\t\treturn false;\n\n\tmanc = IXGBE_READ_REG(hw, IXGBE_MANC);\n\tif (!(manc & IXGBE_MANC_RCV_TCO_EN))\n\t\treturn false;\n\n\tif (hw->mac.type <= ixgbe_mac_X540) {\n\t\tfactps = IXGBE_READ_REG(hw, IXGBE_FACTPS);\n\t\tif (factps & IXGBE_FACTPS_MNGCG)\n\t\t\treturn false;\n\t}\n\n\treturn true;\n}\n\n/**\n * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Set the link speed in the MAC and/or PHY register and restarts link.\n **/\ns32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t\t bool autoneg_wait_to_complete)\n{\n\tixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;\n\tixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;\n\ts32 status = IXGBE_SUCCESS;\n\tu32 speedcnt = 0;\n\tu32 i = 0;\n\tbool autoneg, link_up = false;\n\n\tDEBUGFUNC(\"ixgbe_setup_mac_link_multispeed_fiber\");\n\n\t/* Mask off requested but non-supported speeds */\n\tstatus = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tspeed &= link_speed;\n\n\t/* Try each speed one by one, highest priority first. We do this in\n\t * software because 10Gb fiber doesn't support speed autonegotiation.\n\t */\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL) {\n\t\tspeedcnt++;\n\t\thighest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;\n\n\t\t/* If we already have link at this speed, just jump out */\n\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up, false);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\tif ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)\n\t\t\tgoto out;\n\n\t\t/* Set the module link speed */\n\t\tswitch (hw->phy.media_type) {\n\t\tcase ixgbe_media_type_fiber:\n\t\t\tixgbe_set_rate_select_speed(hw,\n\t\t\t\t\t\t IXGBE_LINK_SPEED_10GB_FULL);\n\t\t\tbreak;\n\t\tcase ixgbe_media_type_fiber_qsfp:\n\t\t\t/* QSFP module automatically detects MAC link speed */\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tDEBUGOUT(\"Unexpected media type.\\n\");\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Allow module to change analog characteristics (1G->10G) */\n\t\tmsec_delay(40);\n\n\t\tstatus = ixgbe_setup_mac_link(hw,\n\t\t\t\t\t IXGBE_LINK_SPEED_10GB_FULL,\n\t\t\t\t\t autoneg_wait_to_complete);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\t/* Flap the Tx laser if it has not already been done */\n\t\tixgbe_flap_tx_laser(hw);\n\n\t\t/* Wait for the controller to acquire link. Per IEEE 802.3ap,\n\t\t * Section 73.10.2, we may have to wait up to 500ms if KR is\n\t\t * attempted. 82599 uses the same timing for 10g SFI.\n\t\t */\n\t\tfor (i = 0; i < 5; i++) {\n\t\t\t/* Wait for the link partner to also set speed */\n\t\t\tmsec_delay(100);\n\n\t\t\t/* If we have link, just jump out */\n\t\t\tstatus = ixgbe_check_link(hw, &link_speed,\n\t\t\t\t\t\t &link_up, false);\n\t\t\tif (status != IXGBE_SUCCESS)\n\t\t\t\treturn status;\n\n\t\t\tif (link_up)\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL) {\n\t\tspeedcnt++;\n\t\tif (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)\n\t\t\thighest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;\n\n\t\t/* If we already have link at this speed, just jump out */\n\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up, false);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\tif ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)\n\t\t\tgoto out;\n\n\t\t/* Set the module link speed */\n\t\tswitch (hw->phy.media_type) {\n\t\tcase ixgbe_media_type_fiber:\n\t\t\tixgbe_set_rate_select_speed(hw,\n\t\t\t\t\t\t IXGBE_LINK_SPEED_1GB_FULL);\n\t\t\tbreak;\n\t\tcase ixgbe_media_type_fiber_qsfp:\n\t\t\t/* QSFP module automatically detects link speed */\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tDEBUGOUT(\"Unexpected media type.\\n\");\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Allow module to change analog characteristics (10G->1G) */\n\t\tmsec_delay(40);\n\n\t\tstatus = ixgbe_setup_mac_link(hw,\n\t\t\t\t\t IXGBE_LINK_SPEED_1GB_FULL,\n\t\t\t\t\t autoneg_wait_to_complete);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\t/* Flap the Tx laser if it has not already been done */\n\t\tixgbe_flap_tx_laser(hw);\n\n\t\t/* Wait for the link partner to also set speed */\n\t\tmsec_delay(100);\n\n\t\t/* If we have link, just jump out */\n\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up, false);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\tif (link_up)\n\t\t\tgoto out;\n\t}\n\n\t/* We didn't get link. Configure back to the highest speed we tried,\n\t * (if there was more than one). We call ourselves back with just the\n\t * single highest speed that the user requested.\n\t */\n\tif (speedcnt > 1)\n\t\tstatus = ixgbe_setup_mac_link_multispeed_fiber(hw,\n\t\t\t\t\t\t highest_link_speed,\n\t\t\t\t\t\t autoneg_wait_to_complete);\n\nout:\n\t/* Set autoneg_advertised value based on input link speed */\n\thw->phy.autoneg_advertised = 0;\n\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;\n\n\treturn status;\n}\n\n/**\n * ixgbe_set_soft_rate_select_speed - Set module link speed\n * @hw: pointer to hardware structure\n * @speed: link speed to set\n *\n * Set module link speed via the soft rate select.\n */\nvoid ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,\n\t\t\t\t\tixgbe_link_speed speed)\n{\n\ts32 status;\n\tu8 rs, eeprom_data;\n\n\tswitch (speed) {\n\tcase IXGBE_LINK_SPEED_10GB_FULL:\n\t\t/* one bit mask same as setting on */\n\t\trs = IXGBE_SFF_SOFT_RS_SELECT_10G;\n\t\tbreak;\n\tcase IXGBE_LINK_SPEED_1GB_FULL:\n\t\trs = IXGBE_SFF_SOFT_RS_SELECT_1G;\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\"Invalid fixed module speed\\n\");\n\t\treturn;\n\t}\n\n\t/* Set RS0 */\n\tstatus = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR2,\n\t\t\t\t\t &eeprom_data);\n\tif (status) {\n\t\tDEBUGOUT(\"Failed to read Rx Rate Select RS0\\n\");\n\t\tgoto out;\n\t}\n\n\teeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;\n\n\tstatus = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR2,\n\t\t\t\t\t eeprom_data);\n\tif (status) {\n\t\tDEBUGOUT(\"Failed to write Rx Rate Select RS0\\n\");\n\t\tgoto out;\n\t}\n\n\t/* Set RS1 */\n\tstatus = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR2,\n\t\t\t\t\t &eeprom_data);\n\tif (status) {\n\t\tDEBUGOUT(\"Failed to read Rx Rate Select RS1\\n\");\n\t\tgoto out;\n\t}\n\n\teeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;\n\n\tstatus = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR2,\n\t\t\t\t\t eeprom_data);\n\tif (status) {\n\t\tDEBUGOUT(\"Failed to write Rx Rate Select RS1\\n\");\n\t\tgoto out;\n\t}\nout:\n\treturn;\n}\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_common.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _IXGBE_COMMON_H_\n#define _IXGBE_COMMON_H_\n\n#include \"ixgbe_type.h\"\n#define IXGBE_WRITE_REG64(hw, reg, value) \\\n\tdo { \\\n\t\tIXGBE_WRITE_REG(hw, reg, (u32) value); \\\n\t\tIXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \\\n\t} while (0)\n#define IXGBE_REMOVED(a) (0)\nstruct ixgbe_pba {\n\tu16 word[2];\n\tu16 *pba_block;\n};\n\nvoid ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map);\n\nu16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);\ns32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);\ns32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);\ns32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);\ns32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);\ns32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);\ns32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);\ns32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,\n\t\t\t\t u32 pba_num_size);\ns32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,\n\t\t u32 eeprom_buf_size, u16 max_pba_block_size,\n\t\t struct ixgbe_pba *pba);\ns32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,\n\t\t\tu32 eeprom_buf_size, struct ixgbe_pba *pba);\ns32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,\n\t\t\t u32 eeprom_buf_size, u16 *pba_block_size);\ns32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);\ns32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);\nvoid ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status);\nvoid ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);\ns32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);\n\ns32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);\n\ns32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);\ns32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);\ns32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data);\ns32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);\ns32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data);\ns32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);\ns32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data);\ns32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 *data);\ns32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data);\ns32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);\ns32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *checksum_val);\ns32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);\ns32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);\n\ns32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n\t\t\t u32 enable_addr);\ns32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);\ns32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,\n\t\t\t\t u32 mc_addr_count,\n\t\t\t\t ixgbe_mc_addr_itr func, bool clear);\ns32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,\n\t\t\t\t u32 addr_count, ixgbe_mc_addr_itr func);\ns32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);\ns32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);\ns32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);\ns32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw);\ns32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw);\n\ns32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);\nbool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);\nvoid ixgbe_fc_autoneg(struct ixgbe_hw *hw);\ns32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw);\n\ns32 ixgbe_validate_mac_addr(u8 *mac_addr);\ns32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask);\nvoid ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask);\ns32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);\n\ns32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);\ns32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);\n\ns32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);\n\ns32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);\ns32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);\n\ns32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);\ns32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);\ns32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);\ns32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);\ns32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);\ns32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,\n\t\t\t u32 vind, bool vlan_on);\ns32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n\t\t\t bool vlan_on, bool *vfta_changed);\ns32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);\ns32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan);\n\ns32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,\n\t\t\t ixgbe_link_speed *speed,\n\t\t\t bool *link_up, bool link_up_wait_to_complete);\n\ns32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n\t\t\t\t u16 *wwpn_prefix);\n\ns32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs);\nvoid ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf);\nvoid ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);\ns32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);\nvoid ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,\n\t\t\t int strategy);\nvoid ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw);\ns32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,\n\t\t\t\t u8 build, u8 ver);\nu8 ixgbe_calculate_checksum(u8 *buffer, u32 length);\ns32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,\n\t\t\t\t u32 length, u32 timeout, bool return_data);\n\nvoid ixgbe_clear_tx_pending(struct ixgbe_hw *hw);\n\nextern s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);\nextern void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);\nbool ixgbe_mng_present(struct ixgbe_hw *hw);\nbool ixgbe_mng_enabled(struct ixgbe_hw *hw);\n\n#define IXGBE_I2C_THERMAL_SENSOR_ADDR\t0xF8\n#define IXGBE_EMC_INTERNAL_DATA\t\t0x00\n#define IXGBE_EMC_INTERNAL_THERM_LIMIT\t0x20\n#define IXGBE_EMC_DIODE1_DATA\t\t0x01\n#define IXGBE_EMC_DIODE1_THERM_LIMIT\t0x19\n#define IXGBE_EMC_DIODE2_DATA\t\t0x23\n#define IXGBE_EMC_DIODE2_THERM_LIMIT\t0x1A\n#define IXGBE_EMC_DIODE3_DATA\t\t0x2A\n#define IXGBE_EMC_DIODE3_THERM_LIMIT\t0x30\n\ns32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);\ns32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);\nvoid ixgbe_disable_rx_generic(struct ixgbe_hw *hw);\nvoid ixgbe_enable_rx_generic(struct ixgbe_hw *hw);\ns32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t\t bool autoneg_wait_to_complete);\nvoid ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed);\n#endif /* IXGBE_COMMON */\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_dcb.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n\n#include \"ixgbe_type.h\"\n#include \"ixgbe_dcb.h\"\n#include \"ixgbe_dcb_82598.h\"\n#include \"ixgbe_dcb_82599.h\"\n\n/**\n * ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class\n * credits from the configured bandwidth percentages. Credits\n * are the smallest unit programmable into the underlying\n * hardware. The IEEE 802.1Qaz specification do not use bandwidth\n * groups so this is much simplified from the CEE case.\n */\ns32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max,\n\t\t\t\t int max_frame_size)\n{\n\tint min_percent = 100;\n\tint min_credit, multiplier;\n\tint i;\n\n\tmin_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /\n\t\t\tIXGBE_DCB_CREDIT_QUANTUM;\n\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tif (bw[i] < min_percent && bw[i])\n\t\t\tmin_percent = bw[i];\n\t}\n\n\tmultiplier = (min_credit / min_percent) + 1;\n\n\t/* Find out the hw credits for each TC */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tint val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL);\n\n\t\tif (val < min_credit)\n\t\t\tval = min_credit;\n\t\trefill[i] = (u16)val;\n\n\t\tmax[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit;\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits\n * @ixgbe_dcb_config: Struct containing DCB settings.\n * @direction: Configuring either Tx or Rx.\n *\n * This function calculates the credits allocated to each traffic class.\n * It should be called only after the rules are checked by\n * ixgbe_dcb_check_config_cee().\n */\ns32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw,\n\t\t\t\t struct ixgbe_dcb_config *dcb_config,\n\t\t\t\t u32 max_frame_size, u8 direction)\n{\n\tstruct ixgbe_dcb_tc_path *p;\n\tu32 min_multiplier\t= 0;\n\tu16 min_percent\t\t= 100;\n\ts32 ret_val =\t\tIXGBE_SUCCESS;\n\t/* Initialization values default for Tx settings */\n\tu32 min_credit\t\t= 0;\n\tu32 credit_refill\t= 0;\n\tu32 credit_max\t\t= 0;\n\tu16 link_percentage\t= 0;\n\tu8 bw_percent\t\t= 0;\n\tu8 i;\n\n\tif (dcb_config == NULL) {\n\t\tret_val = IXGBE_ERR_CONFIG;\n\t\tgoto out;\n\t}\n\n\tmin_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /\n\t\t IXGBE_DCB_CREDIT_QUANTUM;\n\n\t/* Find smallest link percentage */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tp = &dcb_config->tc_config[i].path[direction];\n\t\tbw_percent = dcb_config->bw_percentage[direction][p->bwg_id];\n\t\tlink_percentage = p->bwg_percent;\n\n\t\tlink_percentage = (link_percentage * bw_percent) / 100;\n\n\t\tif (link_percentage && link_percentage < min_percent)\n\t\t\tmin_percent = link_percentage;\n\t}\n\n\t/*\n\t * The ratio between traffic classes will control the bandwidth\n\t * percentages seen on the wire. To calculate this ratio we use\n\t * a multiplier. It is required that the refill credits must be\n\t * larger than the max frame size so here we find the smallest\n\t * multiplier that will allow all bandwidth percentages to be\n\t * greater than the max frame size.\n\t */\n\tmin_multiplier = (min_credit / min_percent) + 1;\n\n\t/* Find out the link percentage for each TC first */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tp = &dcb_config->tc_config[i].path[direction];\n\t\tbw_percent = dcb_config->bw_percentage[direction][p->bwg_id];\n\n\t\tlink_percentage = p->bwg_percent;\n\t\t/* Must be careful of integer division for very small nums */\n\t\tlink_percentage = (link_percentage * bw_percent) / 100;\n\t\tif (p->bwg_percent > 0 && link_percentage == 0)\n\t\t\tlink_percentage = 1;\n\n\t\t/* Save link_percentage for reference */\n\t\tp->link_percent = (u8)link_percentage;\n\n\t\t/* Calculate credit refill ratio using multiplier */\n\t\tcredit_refill = min(link_percentage * min_multiplier,\n\t\t\t\t (u32)IXGBE_DCB_MAX_CREDIT_REFILL);\n\t\tp->data_credits_refill = (u16)credit_refill;\n\n\t\t/* Calculate maximum credit for the TC */\n\t\tcredit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100;\n\n\t\t/*\n\t\t * Adjustment based on rule checking, if the percentage\n\t\t * of a TC is too small, the maximum credit may not be\n\t\t * enough to send out a jumbo frame in data plane arbitration.\n\t\t */\n\t\tif (credit_max && (credit_max < min_credit))\n\t\t\tcredit_max = min_credit;\n\n\t\tif (direction == IXGBE_DCB_TX_CONFIG) {\n\t\t\t/*\n\t\t\t * Adjustment based on rule checking, if the\n\t\t\t * percentage of a TC is too small, the maximum\n\t\t\t * credit may not be enough to send out a TSO\n\t\t\t * packet in descriptor plane arbitration.\n\t\t\t */\n\t\t\tif (credit_max && (credit_max <\n\t\t\t IXGBE_DCB_MIN_TSO_CREDIT)\n\t\t\t && (hw->mac.type == ixgbe_mac_82598EB))\n\t\t\t\tcredit_max = IXGBE_DCB_MIN_TSO_CREDIT;\n\n\t\t\tdcb_config->tc_config[i].desc_credits_max =\n\t\t\t\t\t\t\t\t(u16)credit_max;\n\t\t}\n\n\t\tp->data_credits_max = (u16)credit_max;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info\n * @cfg: dcb configuration to unpack into hardware consumable fields\n * @map: user priority to traffic class map\n * @pfc_up: u8 to store user priority PFC bitmask\n *\n * This unpacks the dcb configuration PFC info which is stored per\n * traffic class into a 8bit user priority bitmask that can be\n * consumed by hardware routines. The priority to tc map must be\n * updated before calling this routine to use current up-to maps.\n */\nvoid ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up)\n{\n\tstruct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];\n\tint up;\n\n\t/*\n\t * If the TC for this user priority has PFC enabled then set the\n\t * matching bit in 'pfc_up' to reflect that PFC is enabled.\n\t */\n\tfor (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) {\n\t\tif (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled)\n\t\t\t*pfc_up |= 1 << up;\n\t}\n}\n\nvoid ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction,\n\t\t\t u16 *refill)\n{\n\tstruct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];\n\tint tc;\n\n\tfor (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)\n\t\trefill[tc] = tc_config[tc].path[direction].data_credits_refill;\n}\n\nvoid ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max)\n{\n\tstruct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];\n\tint tc;\n\n\tfor (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)\n\t\tmax[tc] = tc_config[tc].desc_credits_max;\n}\n\nvoid ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction,\n\t\t\t u8 *bwgid)\n{\n\tstruct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];\n\tint tc;\n\n\tfor (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)\n\t\tbwgid[tc] = tc_config[tc].path[direction].bwg_id;\n}\n\nvoid ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction,\n\t\t\t u8 *tsa)\n{\n\tstruct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];\n\tint tc;\n\n\tfor (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)\n\t\ttsa[tc] = tc_config[tc].path[direction].tsa;\n}\n\nu8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)\n{\n\tstruct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];\n\tu8 prio_mask = 1 << up;\n\tu8 tc = cfg->num_tcs.pg_tcs;\n\n\t/* If tc is 0 then DCB is likely not enabled or supported */\n\tif (!tc)\n\t\tgoto out;\n\n\t/*\n\t * Test from maximum TC to 1 and report the first match we find. If\n\t * we find no match we can assume that the TC is 0 since the TC must\n\t * be set for all user priorities\n\t */\n\tfor (tc--; tc; tc--) {\n\t\tif (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)\n\t\t\tbreak;\n\t}\nout:\n\treturn tc;\n}\n\nvoid ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction,\n\t\t\t u8 *map)\n{\n\tu8 up;\n\n\tfor (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++)\n\t\tmap[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up);\n}\n\n/**\n * ixgbe_dcb_config - Struct containing DCB settings.\n * @dcb_config: Pointer to DCB config structure\n *\n * This function checks DCB rules for DCB settings.\n * The following rules are checked:\n * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%.\n * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth\n * Group must total 100.\n * 3. A Traffic Class should not be set to both Link Strict Priority\n * and Group Strict Priority.\n * 4. Link strict Bandwidth Groups can only have link strict traffic classes\n * with zero bandwidth.\n */\ns32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config)\n{\n\tstruct ixgbe_dcb_tc_path *p;\n\ts32 ret_val = IXGBE_SUCCESS;\n\tu8 i, j, bw = 0, bw_id;\n\tu8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP];\n\tbool link_strict[2][IXGBE_DCB_MAX_BW_GROUP];\n\n\tmemset(bw_sum, 0, sizeof(bw_sum));\n\tmemset(link_strict, 0, sizeof(link_strict));\n\n\t/* First Tx, then Rx */\n\tfor (i = 0; i < 2; i++) {\n\t\t/* Check each traffic class for rule violation */\n\t\tfor (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {\n\t\t\tp = &dcb_config->tc_config[j].path[i];\n\n\t\t\tbw = p->bwg_percent;\n\t\t\tbw_id = p->bwg_id;\n\n\t\t\tif (bw_id >= IXGBE_DCB_MAX_BW_GROUP) {\n\t\t\t\tret_val = IXGBE_ERR_CONFIG;\n\t\t\t\tgoto err_config;\n\t\t\t}\n\t\t\tif (p->tsa == ixgbe_dcb_tsa_strict) {\n\t\t\t\tlink_strict[i][bw_id] = true;\n\t\t\t\t/* Link strict should have zero bandwidth */\n\t\t\t\tif (bw) {\n\t\t\t\t\tret_val = IXGBE_ERR_CONFIG;\n\t\t\t\t\tgoto err_config;\n\t\t\t\t}\n\t\t\t} else if (!bw) {\n\t\t\t\t/*\n\t\t\t\t * Traffic classes without link strict\n\t\t\t\t * should have non-zero bandwidth.\n\t\t\t\t */\n\t\t\t\tret_val = IXGBE_ERR_CONFIG;\n\t\t\t\tgoto err_config;\n\t\t\t}\n\t\t\tbw_sum[i][bw_id] += bw;\n\t\t}\n\n\t\tbw = 0;\n\n\t\t/* Check each bandwidth group for rule violation */\n\t\tfor (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) {\n\t\t\tbw += dcb_config->bw_percentage[i][j];\n\t\t\t/*\n\t\t\t * Sum of bandwidth percentages of all traffic classes\n\t\t\t * within a Bandwidth Group must total 100 except for\n\t\t\t * link strict group (zero bandwidth).\n\t\t\t */\n\t\t\tif (link_strict[i][j]) {\n\t\t\t\tif (bw_sum[i][j]) {\n\t\t\t\t\t/*\n\t\t\t\t\t * Link strict group should have zero\n\t\t\t\t\t * bandwidth.\n\t\t\t\t\t */\n\t\t\t\t\tret_val = IXGBE_ERR_CONFIG;\n\t\t\t\t\tgoto err_config;\n\t\t\t\t}\n\t\t\t} else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT &&\n\t\t\t\t bw_sum[i][j] != 0) {\n\t\t\t\tret_val = IXGBE_ERR_CONFIG;\n\t\t\t\tgoto err_config;\n\t\t\t}\n\t\t}\n\n\t\tif (bw != IXGBE_DCB_BW_PERCENT) {\n\t\t\tret_val = IXGBE_ERR_CONFIG;\n\t\t\tgoto err_config;\n\t\t}\n\t}\n\nerr_config:\n\tDEBUGOUT2(\"DCB error code %d while checking %s settings.\\n\",\n\t\t ret_val, (i == IXGBE_DCB_TX_CONFIG) ? \"Tx\" : \"Rx\");\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_dcb_get_tc_stats - Returns status of each traffic class\n * @hw: pointer to hardware structure\n * @stats: pointer to statistics structure\n * @tc_count: Number of elements in bwg_array.\n *\n * This function returns the status data for each of the Traffic Classes in use.\n */\ns32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,\n\t\t\t u8 tc_count)\n{\n\ts32 ret = IXGBE_NOT_IMPLEMENTED;\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\n/**\n * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class\n * @hw: pointer to hardware structure\n * @stats: pointer to statistics structure\n * @tc_count: Number of elements in bwg_array.\n *\n * This function returns the CBFC status data for each of the Traffic Classes.\n */\ns32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,\n\t\t\t u8 tc_count)\n{\n\ts32 ret = IXGBE_NOT_IMPLEMENTED;\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\n/**\n * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure Rx Data Arbiter and credits for each traffic class.\n */\ns32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw,\n\t\t\t\tstruct ixgbe_dcb_config *dcb_config)\n{\n\ts32 ret = IXGBE_NOT_IMPLEMENTED;\n\tu8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS]\t= { 0 };\n\tu8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS]\t= { 0 };\n\tu8 map[IXGBE_DCB_MAX_USER_PRIORITY]\t= { 0 };\n\tu16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS]\t= { 0 };\n\tu16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS]\t= { 0 };\n\n\tixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);\n\tixgbe_dcb_unpack_max_cee(dcb_config, max);\n\tixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);\n\tixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);\n\tixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid,\n\t\t\t\t\t\t\ttsa, map);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\n/**\n * ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure Tx Descriptor Arbiter and credits for each traffic class.\n */\ns32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw,\n\t\t\t\t struct ixgbe_dcb_config *dcb_config)\n{\n\ts32 ret = IXGBE_NOT_IMPLEMENTED;\n\tu8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\tu8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\tu16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\tu16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\n\tixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);\n\tixgbe_dcb_unpack_max_cee(dcb_config, max);\n\tixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);\n\tixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,\n\t\t\t\t\t\t\t bwgid, tsa);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,\n\t\t\t\t\t\t\t bwgid, tsa);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\n/**\n * ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure Tx Data Arbiter and credits for each traffic class.\n */\ns32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw,\n\t\t\t\t struct ixgbe_dcb_config *dcb_config)\n{\n\ts32 ret = IXGBE_NOT_IMPLEMENTED;\n\tu8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\tu8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\tu8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };\n\tu16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\tu16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\n\tixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);\n\tixgbe_dcb_unpack_max_cee(dcb_config, max);\n\tixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);\n\tixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);\n\tixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,\n\t\t\t\t\t\t\t bwgid, tsa);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,\n\t\t\t\t\t\t\t bwgid, tsa,\n\t\t\t\t\t\t\t map);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\n/**\n * ixgbe_dcb_config_pfc_cee - Config priority flow control\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure Priority Flow Control for each traffic class.\n */\ns32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw,\n\t\t\t struct ixgbe_dcb_config *dcb_config)\n{\n\ts32 ret = IXGBE_NOT_IMPLEMENTED;\n\tu8 pfc_en;\n\tu8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };\n\n\tixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);\n\tixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\n/**\n * ixgbe_dcb_config_tc_stats - Config traffic class statistics\n * @hw: pointer to hardware structure\n *\n * Configure queue statistics registers, all queues belonging to same traffic\n * class uses a single set of queue statistics counters.\n */\ns32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)\n{\n\ts32 ret = IXGBE_NOT_IMPLEMENTED;\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tret = ixgbe_dcb_config_tc_stats_82598(hw);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tret = ixgbe_dcb_config_tc_stats_82599(hw, NULL);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\n/**\n * ixgbe_dcb_hw_config_cee - Config and enable DCB\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure dcb settings and enable dcb mode.\n */\ns32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw,\n\t\t\tstruct ixgbe_dcb_config *dcb_config)\n{\n\ts32 ret = IXGBE_NOT_IMPLEMENTED;\n\tu8 pfc_en;\n\tu8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\tu8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\tu8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };\n\tu16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\tu16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\n\t/* Unpack CEE standard containers */\n\tixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);\n\tixgbe_dcb_unpack_max_cee(dcb_config, max);\n\tixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);\n\tixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);\n\tixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed,\n\t\t\t\t\t\trefill, max, bwgid, tsa);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tixgbe_dcb_config_82599(hw, dcb_config);\n\t\tret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed,\n\t\t\t\t\t\trefill, max, bwgid,\n\t\t\t\t\t\ttsa, map);\n\n\t\tixgbe_dcb_config_tc_stats_82599(hw, dcb_config);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (!ret && dcb_config->pfc_mode_enable) {\n\t\tixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);\n\t\tret = ixgbe_dcb_config_pfc(hw, pfc_en, map);\n\t}\n\n\treturn ret;\n}\n\n/* Helper routines to abstract HW specifics from DCB netlink ops */\ns32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)\n{\n\tint ret = IXGBE_ERR_PARAM;\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\ns32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,\n\t\t\t u8 *bwg_id, u8 *tsa, u8 *map)\n{\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);\n\t\tixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,\n\t\t\t\t\t\t tsa);\n\t\tixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,\n\t\t\t\t\t\t tsa);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,\n\t\t\t\t\t\t tsa, map);\n\t\tixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,\n\t\t\t\t\t\t tsa);\n\t\tixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,\n\t\t\t\t\t\t tsa, map);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn 0;\n}\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_dcb.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _IXGBE_DCB_H_\n#define _IXGBE_DCB_H_\n\n#include \"ixgbe_type.h\"\n\n/* DCB defines */\n/* DCB credit calculation defines */\n#define IXGBE_DCB_CREDIT_QUANTUM\t64\n#define IXGBE_DCB_MAX_CREDIT_REFILL\t200 /* 200 * 64B = 12800B */\n#define IXGBE_DCB_MAX_TSO_SIZE\t\t(32 * 1024) /* Max TSO pkt size in DCB*/\n#define IXGBE_DCB_MAX_CREDIT\t\t(2 * IXGBE_DCB_MAX_CREDIT_REFILL)\n\n/* 513 for 32KB TSO packet */\n#define IXGBE_DCB_MIN_TSO_CREDIT\t\\\n\t((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1)\n\n/* DCB configuration defines */\n#define IXGBE_DCB_MAX_USER_PRIORITY\t8\n#define IXGBE_DCB_MAX_BW_GROUP\t\t8\n#define IXGBE_DCB_BW_PERCENT\t\t100\n\n#define IXGBE_DCB_TX_CONFIG\t\t0\n#define IXGBE_DCB_RX_CONFIG\t\t1\n\n/* DCB capability defines */\n#define IXGBE_DCB_PG_SUPPORT\t0x00000001\n#define IXGBE_DCB_PFC_SUPPORT\t0x00000002\n#define IXGBE_DCB_BCN_SUPPORT\t0x00000004\n#define IXGBE_DCB_UP2TC_SUPPORT\t0x00000008\n#define IXGBE_DCB_GSP_SUPPORT\t0x00000010\n\nstruct ixgbe_dcb_support {\n\tu32 capabilities; /* DCB capabilities */\n\n\t/* Each bit represents a number of TCs configurable in the hw.\n\t * If 8 traffic classes can be configured, the value is 0x80. */\n\tu8 traffic_classes;\n\tu8 pfc_traffic_classes;\n};\n\nenum ixgbe_dcb_tsa {\n\tixgbe_dcb_tsa_ets = 0,\n\tixgbe_dcb_tsa_group_strict_cee,\n\tixgbe_dcb_tsa_strict\n};\n\n/* Traffic class bandwidth allocation per direction */\nstruct ixgbe_dcb_tc_path {\n\tu8 bwg_id; /* Bandwidth Group (BWG) ID */\n\tu8 bwg_percent; /* % of BWG's bandwidth */\n\tu8 link_percent; /* % of link bandwidth */\n\tu8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */\n\tu16 data_credits_refill; /* Credit refill amount in 64B granularity */\n\tu16 data_credits_max; /* Max credits for a configured packet buffer\n\t\t\t * in 64B granularity.*/\n\tenum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */\n};\n\nenum ixgbe_dcb_pfc {\n\tixgbe_dcb_pfc_disabled = 0,\n\tixgbe_dcb_pfc_enabled,\n\tixgbe_dcb_pfc_enabled_txonly,\n\tixgbe_dcb_pfc_enabled_rxonly\n};\n\n/* Traffic class configuration */\nstruct ixgbe_dcb_tc_config {\n\tstruct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */\n\tenum ixgbe_dcb_pfc pfc; /* Class based flow control setting */\n\n\tu16 desc_credits_max; /* For Tx Descriptor arbitration */\n\tu8 tc; /* Traffic class (TC) */\n};\n\nenum ixgbe_dcb_pba {\n\t/* PBA[0-7] each use 64KB FIFO */\n\tixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL,\n\t/* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */\n\tixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED\n};\n\nstruct ixgbe_dcb_num_tcs {\n\tu8 pg_tcs;\n\tu8 pfc_tcs;\n};\n\nstruct ixgbe_dcb_config {\n\tstruct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\tstruct ixgbe_dcb_support support;\n\tstruct ixgbe_dcb_num_tcs num_tcs;\n\tu8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */\n\tbool pfc_mode_enable;\n\tbool round_robin_enable;\n\n\tenum ixgbe_dcb_pba rx_pba_cfg;\n\n\tu32 dcb_cfg_version; /* Not used...OS-specific? */\n\tu32 link_speed; /* For bandwidth allocation validation purpose */\n\tbool vt_mode;\n};\n\n/* DCB driver APIs */\n\n/* DCB rule checking */\ns32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *);\n\n/* DCB credits calculation */\ns32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int);\ns32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *,\n\t\t\t\t struct ixgbe_dcb_config *, u32, u8);\n\n/* DCB PFC */\ns32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *);\ns32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);\n\n/* DCB stats */\ns32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);\ns32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);\ns32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);\n\n/* DCB config arbiters */\ns32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *,\n\t\t\t\t\t struct ixgbe_dcb_config *);\ns32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *,\n\t\t\t\t\t struct ixgbe_dcb_config *);\ns32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *,\n\t\t\t\t struct ixgbe_dcb_config *);\n\n/* DCB unpack routines */\nvoid ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *);\nvoid ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *);\nvoid ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *);\nvoid ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *);\nvoid ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *);\nvoid ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *);\nu8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8);\n\n/* DCB initialization */\ns32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *);\ns32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);\n#endif /* _IXGBE_DCB_H_ */\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_dcb_82598.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n\n#include \"ixgbe_type.h\"\n#include \"ixgbe_dcb.h\"\n#include \"ixgbe_dcb_82598.h\"\n\n/**\n * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class\n * @hw: pointer to hardware structure\n * @stats: pointer to statistics structure\n * @tc_count: Number of elements in bwg_array.\n *\n * This function returns the status data for each of the Traffic Classes in use.\n */\ns32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,\n\t\t\t\t struct ixgbe_hw_stats *stats,\n\t\t\t\t u8 tc_count)\n{\n\tint tc;\n\n\tDEBUGFUNC(\"dcb_get_tc_stats\");\n\n\tif (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)\n\t\treturn IXGBE_ERR_PARAM;\n\n\t/* Statistics pertaining to each traffic class */\n\tfor (tc = 0; tc < tc_count; tc++) {\n\t\t/* Transmitted Packets */\n\t\tstats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));\n\t\t/* Transmitted Bytes */\n\t\tstats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));\n\t\t/* Received Packets */\n\t\tstats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));\n\t\t/* Received Bytes */\n\t\tstats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));\n\n#if 0\n\t\t/* Can we get rid of these?? Consequently, getting rid\n\t\t * of the tc_stats structure.\n\t\t */\n\t\ttc_stats_array[up]->in_overflow_discards = 0;\n\t\ttc_stats_array[up]->out_overflow_discards = 0;\n#endif\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data\n * @hw: pointer to hardware structure\n * @stats: pointer to statistics structure\n * @tc_count: Number of elements in bwg_array.\n *\n * This function returns the CBFC status data for each of the Traffic Classes.\n */\ns32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,\n\t\t\t\t struct ixgbe_hw_stats *stats,\n\t\t\t\t u8 tc_count)\n{\n\tint tc;\n\n\tDEBUGFUNC(\"dcb_get_pfc_stats\");\n\n\tif (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)\n\t\treturn IXGBE_ERR_PARAM;\n\n\tfor (tc = 0; tc < tc_count; tc++) {\n\t\t/* Priority XOFF Transmitted */\n\t\tstats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));\n\t\t/* Priority XOFF Received */\n\t\tstats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc));\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure Rx Data Arbiter and credits for each traffic class.\n */\ns32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,\n\t\t\t\t u16 *max, u8 *tsa)\n{\n\tu32 reg = 0;\n\tu32 credit_refill = 0;\n\tu32 credit_max = 0;\n\tu8 i = 0;\n\n\treg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;\n\tIXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);\n\n\treg = IXGBE_READ_REG(hw, IXGBE_RMCS);\n\t/* Enable Arbiter */\n\treg &= ~IXGBE_RMCS_ARBDIS;\n\t/* Enable Receive Recycle within the BWG */\n\treg |= IXGBE_RMCS_RRM;\n\t/* Enable Deficit Fixed Priority arbitration*/\n\treg |= IXGBE_RMCS_DFP;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);\n\n\t/* Configure traffic class credits and priority */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tcredit_refill = refill[i];\n\t\tcredit_max = max[i];\n\n\t\treg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);\n\n\t\tif (tsa[i] == ixgbe_dcb_tsa_strict)\n\t\t\treg |= IXGBE_RT2CR_LSP;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);\n\t}\n\n\treg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);\n\treg |= IXGBE_RDRXCTL_RDMTS_1_2;\n\treg |= IXGBE_RDRXCTL_MPBEN;\n\treg |= IXGBE_RDRXCTL_MCEN;\n\tIXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);\n\n\treg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n\t/* Make sure there is enough descriptors before arbitration */\n\treg &= ~IXGBE_RXCTRL_DMBYPS;\n\tIXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure Tx Descriptor Arbiter and credits for each traffic class.\n */\ns32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *refill, u16 *max, u8 *bwg_id,\n\t\t\t\t\t u8 *tsa)\n{\n\tu32 reg, max_credits;\n\tu8 i;\n\n\treg = IXGBE_READ_REG(hw, IXGBE_DPMCS);\n\n\t/* Enable arbiter */\n\treg &= ~IXGBE_DPMCS_ARBDIS;\n\treg |= IXGBE_DPMCS_TSOEF;\n\n\t/* Configure Max TSO packet size 34KB including payload and headers */\n\treg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);\n\n\t/* Configure traffic class credits and priority */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tmax_credits = max[i];\n\t\treg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;\n\t\treg |= refill[i];\n\t\treg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;\n\n\t\tif (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)\n\t\t\treg |= IXGBE_TDTQ2TCCR_GSP;\n\n\t\tif (tsa[i] == ixgbe_dcb_tsa_strict)\n\t\t\treg |= IXGBE_TDTQ2TCCR_LSP;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure Tx Data Arbiter and credits for each traffic class.\n */\ns32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *refill, u16 *max, u8 *bwg_id,\n\t\t\t\t\t u8 *tsa)\n{\n\tu32 reg;\n\tu8 i;\n\n\treg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);\n\t/* Enable Data Plane Arbiter */\n\treg &= ~IXGBE_PDPMCS_ARBDIS;\n\t/* Enable DFP and Transmit Recycle Mode */\n\treg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);\n\n\t/* Configure traffic class credits and priority */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\treg = refill[i];\n\t\treg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;\n\t\treg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;\n\n\t\tif (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)\n\t\t\treg |= IXGBE_TDPT2TCCR_GSP;\n\n\t\tif (tsa[i] == ixgbe_dcb_tsa_strict)\n\t\t\treg |= IXGBE_TDPT2TCCR_LSP;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);\n\t}\n\n\t/* Enable Tx packet buffer division */\n\treg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);\n\treg |= IXGBE_DTXCTL_ENDBUBD;\n\tIXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_config_pfc_82598 - Config priority flow control\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure Priority Flow Control for each traffic class.\n */\ns32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)\n{\n\tu32 fcrtl, reg;\n\tu8 i;\n\n\t/* Enable Transmit Priority Flow Control */\n\treg = IXGBE_READ_REG(hw, IXGBE_RMCS);\n\treg &= ~IXGBE_RMCS_TFCE_802_3X;\n\treg |= IXGBE_RMCS_TFCE_PRIORITY;\n\tIXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);\n\n\t/* Enable Receive Priority Flow Control */\n\treg = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\treg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);\n\n\tif (pfc_en)\n\t\treg |= IXGBE_FCTRL_RPFCE;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);\n\n\t/* Configure PFC Tx thresholds per TC */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tif (!(pfc_en & (1 << i))) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);\n\t\t\tcontinue;\n\t\t}\n\n\t\tfcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;\n\t\treg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);\n\t}\n\n\t/* Configure pause time */\n\treg = hw->fc.pause_time | (hw->fc.pause_time << 16);\n\tfor (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);\n\n\t/* Configure flow control refresh threshold value */\n\tIXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics\n * @hw: pointer to hardware structure\n *\n * Configure queue statistics registers, all queues belonging to same traffic\n * class uses a single set of queue statistics counters.\n */\ns32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)\n{\n\tu32 reg = 0;\n\tu8 i = 0;\n\tu8 j = 0;\n\n\t/* Receive Queues stats setting - 8 queues per statistics reg */\n\tfor (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {\n\t\treg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));\n\t\treg |= ((0x1010101) * j);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);\n\t\treg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));\n\t\treg |= ((0x1010101) * j);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);\n\t}\n\t/* Transmit Queues stats setting - 4 queues per statistics reg*/\n\tfor (i = 0; i < 8; i++) {\n\t\treg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));\n\t\treg |= ((0x1010101) * i);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_hw_config_82598 - Config and enable DCB\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure dcb settings and enable dcb mode.\n */\ns32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed,\n\t\t\t u16 *refill, u16 *max, u8 *bwg_id,\n\t\t\t u8 *tsa)\n{\n\tUNREFERENCED_1PARAMETER(link_speed);\n\n\tixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);\n\tixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,\n\t\t\t\t\t tsa);\n\tixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,\n\t\t\t\t\t tsa);\n\tixgbe_dcb_config_tc_stats_82598(hw);\n\n\n\treturn IXGBE_SUCCESS;\n}\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_dcb_82598.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _IXGBE_DCB_82598_H_\n#define _IXGBE_DCB_82598_H_\n\n/* DCB register definitions */\n\n#define IXGBE_DPMCS_MTSOS_SHIFT\t16\n#define IXGBE_DPMCS_TDPAC\t0x00000001 /* 0 Round Robin,\n\t\t\t\t\t * 1 DFP - Deficit Fixed Priority */\n#define IXGBE_DPMCS_TRM\t\t0x00000010 /* Transmit Recycle Mode */\n#define IXGBE_DPMCS_ARBDIS\t0x00000040 /* DCB arbiter disable */\n#define IXGBE_DPMCS_TSOEF\t0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */\n\n#define IXGBE_RUPPBMR_MQA\t0x80000000 /* Enable UP to queue mapping */\n\n#define IXGBE_RT2CR_MCL_SHIFT\t12 /* Offset to Max Credit Limit setting */\n#define IXGBE_RT2CR_LSP\t\t0x80000000 /* LSP enable bit */\n\n#define IXGBE_RDRXCTL_MPBEN\t0x00000010 /* DMA config for multiple packet\n\t\t\t\t\t * buffers enable */\n#define IXGBE_RDRXCTL_MCEN\t0x00000040 /* DMA config for multiple cores\n\t\t\t\t\t * (RSS) enable */\n\n#define IXGBE_TDTQ2TCCR_MCL_SHIFT\t12\n#define IXGBE_TDTQ2TCCR_BWG_SHIFT\t9\n#define IXGBE_TDTQ2TCCR_GSP\t0x40000000\n#define IXGBE_TDTQ2TCCR_LSP\t0x80000000\n\n#define IXGBE_TDPT2TCCR_MCL_SHIFT\t12\n#define IXGBE_TDPT2TCCR_BWG_SHIFT\t9\n#define IXGBE_TDPT2TCCR_GSP\t0x40000000\n#define IXGBE_TDPT2TCCR_LSP\t0x80000000\n\n#define IXGBE_PDPMCS_TPPAC\t0x00000020 /* 0 Round Robin,\n\t\t\t\t\t * 1 DFP - Deficit Fixed Priority */\n#define IXGBE_PDPMCS_ARBDIS\t0x00000040 /* Arbiter disable */\n#define IXGBE_PDPMCS_TRM\t0x00000100 /* Transmit Recycle Mode enable */\n\n#define IXGBE_DTXCTL_ENDBUBD\t0x00000004 /* Enable DBU buffer division */\n\n#define IXGBE_TXPBSIZE_40KB\t0x0000A000 /* 40KB Packet Buffer */\n#define IXGBE_RXPBSIZE_48KB\t0x0000C000 /* 48KB Packet Buffer */\n#define IXGBE_RXPBSIZE_64KB\t0x00010000 /* 64KB Packet Buffer */\n#define IXGBE_RXPBSIZE_80KB\t0x00014000 /* 80KB Packet Buffer */\n\n/* DCB driver APIs */\n\n/* DCB PFC */\ns32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8);\n\n/* DCB stats */\ns32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *);\ns32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *,\n\t\t\t\t struct ixgbe_hw_stats *, u8);\ns32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *,\n\t\t\t\t struct ixgbe_hw_stats *, u8);\n\n/* DCB config arbiters */\ns32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *,\n\t\t\t\t\t u8 *, u8 *);\ns32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *,\n\t\t\t\t\t u8 *, u8 *);\ns32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, u8 *);\n\n/* DCB initialization */\ns32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, u8 *);\n#endif /* _IXGBE_DCB_82958_H_ */\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_dcb_82599.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n\n#include \"ixgbe_type.h\"\n#include \"ixgbe_dcb.h\"\n#include \"ixgbe_dcb_82599.h\"\n\n/**\n * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class\n * @hw: pointer to hardware structure\n * @stats: pointer to statistics structure\n * @tc_count: Number of elements in bwg_array.\n *\n * This function returns the status data for each of the Traffic Classes in use.\n */\ns32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *hw,\n\t\t\t\t struct ixgbe_hw_stats *stats,\n\t\t\t\t u8 tc_count)\n{\n\tint tc;\n\n\tDEBUGFUNC(\"dcb_get_tc_stats\");\n\n\tif (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)\n\t\treturn IXGBE_ERR_PARAM;\n\n\t/* Statistics pertaining to each traffic class */\n\tfor (tc = 0; tc < tc_count; tc++) {\n\t\t/* Transmitted Packets */\n\t\tstats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));\n\t\t/* Transmitted Bytes (read low first to prevent missed carry) */\n\t\tstats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc));\n\t\tstats->qbtc[tc] +=\n\t\t\t(((u64)(IXGBE_READ_REG(hw, IXGBE_QBTC_H(tc)))) << 32);\n\t\t/* Received Packets */\n\t\tstats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));\n\t\t/* Received Bytes (read low first to prevent missed carry) */\n\t\tstats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc));\n\t\tstats->qbrc[tc] +=\n\t\t\t(((u64)(IXGBE_READ_REG(hw, IXGBE_QBRC_H(tc)))) << 32);\n\n\t\t/* Received Dropped Packet */\n\t\tstats->qprdc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRDC(tc));\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_get_pfc_stats_82599 - Return CBFC status data\n * @hw: pointer to hardware structure\n * @stats: pointer to statistics structure\n * @tc_count: Number of elements in bwg_array.\n *\n * This function returns the CBFC status data for each of the Traffic Classes.\n */\ns32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *hw,\n\t\t\t\t struct ixgbe_hw_stats *stats,\n\t\t\t\t u8 tc_count)\n{\n\tint tc;\n\n\tDEBUGFUNC(\"dcb_get_pfc_stats\");\n\n\tif (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)\n\t\treturn IXGBE_ERR_PARAM;\n\n\tfor (tc = 0; tc < tc_count; tc++) {\n\t\t/* Priority XOFF Transmitted */\n\t\tstats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));\n\t\t/* Priority XOFF Received */\n\t\tstats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(tc));\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure Rx Packet Arbiter and credits for each traffic class.\n */\ns32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,\n\t\t\t\t u16 *max, u8 *bwg_id, u8 *tsa,\n\t\t\t\t u8 *map)\n{\n\tu32 reg = 0;\n\tu32 credit_refill = 0;\n\tu32 credit_max = 0;\n\tu8 i = 0;\n\n\t/*\n\t * Disable the arbiter before changing parameters\n\t * (always enable recycle mode; WSP)\n\t */\n\treg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);\n\n\t/*\n\t * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding\n\t * bits sets for the UPs that needs to be mappped to that TC.\n\t * e.g if priorities 6 and 7 are to be mapped to a TC then the\n\t * up_to_tc_bitmap value for that TC will be 11000000 in binary.\n\t */\n\treg = 0;\n\tfor (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)\n\t\treg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));\n\n\tIXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);\n\n\t/* Configure traffic class credits and priority */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tcredit_refill = refill[i];\n\t\tcredit_max = max[i];\n\t\treg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);\n\n\t\treg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;\n\n\t\tif (tsa[i] == ixgbe_dcb_tsa_strict)\n\t\t\treg |= IXGBE_RTRPT4C_LSP;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);\n\t}\n\n\t/*\n\t * Configure Rx packet plane (recycle mode; WSP) and\n\t * enable arbiter\n\t */\n\treg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;\n\tIXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure Tx Descriptor Arbiter and credits for each traffic class.\n */\ns32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,\n\t\t\t\t\t u16 *max, u8 *bwg_id, u8 *tsa)\n{\n\tu32 reg, max_credits;\n\tu8 i;\n\n\t/* Clear the per-Tx queue credits; we use per-TC instead */\n\tfor (i = 0; i < 128; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);\n\t}\n\n\t/* Configure traffic class credits and priority */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tmax_credits = max[i];\n\t\treg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;\n\t\treg |= refill[i];\n\t\treg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;\n\n\t\tif (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)\n\t\t\treg |= IXGBE_RTTDT2C_GSP;\n\n\t\tif (tsa[i] == ixgbe_dcb_tsa_strict)\n\t\t\treg |= IXGBE_RTTDT2C_LSP;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);\n\t}\n\n\t/*\n\t * Configure Tx descriptor plane (recycle mode; WSP) and\n\t * enable arbiter\n\t */\n\treg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;\n\tIXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure Tx Packet Arbiter and credits for each traffic class.\n */\ns32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw, u16 *refill,\n\t\t\t\t\t u16 *max, u8 *bwg_id, u8 *tsa,\n\t\t\t\t\t u8 *map)\n{\n\tu32 reg;\n\tu8 i;\n\n\t/*\n\t * Disable the arbiter before changing parameters\n\t * (always enable recycle mode; SP; arb delay)\n\t */\n\treg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |\n\t (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |\n\t IXGBE_RTTPCS_ARBDIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);\n\n\t/*\n\t * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding\n\t * bits sets for the UPs that needs to be mappped to that TC.\n\t * e.g if priorities 6 and 7 are to be mapped to a TC then the\n\t * up_to_tc_bitmap value for that TC will be 11000000 in binary.\n\t */\n\treg = 0;\n\tfor (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)\n\t\treg |= (map[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));\n\n\tIXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);\n\n\t/* Configure traffic class credits and priority */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\treg = refill[i];\n\t\treg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;\n\t\treg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;\n\n\t\tif (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)\n\t\t\treg |= IXGBE_RTTPT2C_GSP;\n\n\t\tif (tsa[i] == ixgbe_dcb_tsa_strict)\n\t\t\treg |= IXGBE_RTTPT2C_LSP;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);\n\t}\n\n\t/*\n\t * Configure Tx packet plane (recycle mode; SP; arb delay) and\n\t * enable arbiter\n\t */\n\treg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |\n\t (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);\n\tIXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_config_pfc_82599 - Configure priority flow control\n * @hw: pointer to hardware structure\n * @pfc_en: enabled pfc bitmask\n * @map: priority to tc assignments indexed by priority\n *\n * Configure Priority Flow Control (PFC) for each traffic class.\n */\ns32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)\n{\n\tu32 i, j, fcrtl, reg;\n\tu8 max_tc = 0;\n\n\t/* Enable Transmit Priority Flow Control */\n\tIXGBE_WRITE_REG(hw, IXGBE_FCCFG, IXGBE_FCCFG_TFCE_PRIORITY);\n\n\t/* Enable Receive Priority Flow Control */\n\treg = IXGBE_READ_REG(hw, IXGBE_MFLCN);\n\treg |= IXGBE_MFLCN_DPF;\n\n\t/*\n\t * X540 supports per TC Rx priority flow control. So\n\t * clear all TCs and only enable those that should be\n\t * enabled.\n\t */\n\treg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);\n\n\tif (hw->mac.type >= ixgbe_mac_X540)\n\t\treg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;\n\n\tif (pfc_en)\n\t\treg |= IXGBE_MFLCN_RPFCE;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);\n\n\tfor (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) {\n\t\tif (map[i] > max_tc)\n\t\t\tmax_tc = map[i];\n\t}\n\n\n\t/* Configure PFC Tx thresholds per TC */\n\tfor (i = 0; i <= max_tc; i++) {\n\t\tint enabled = 0;\n\n\t\tfor (j = 0; j < IXGBE_DCB_MAX_USER_PRIORITY; j++) {\n\t\t\tif ((map[j] == i) && (pfc_en & (1 << j))) {\n\t\t\t\tenabled = 1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (enabled) {\n\t\t\treg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;\n\t\t\tfcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);\n\t\t} else {\n\t\t\t/*\n\t\t\t * In order to prevent Tx hangs when the internal Tx\n\t\t\t * switch is enabled we must set the high water mark\n\t\t\t * to the Rx packet buffer size - 24KB. This allows\n\t\t\t * the Tx switch to function even under heavy Rx\n\t\t\t * workloads.\n\t\t\t */\n\t\t\treg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);\n\t\t}\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);\n\t}\n\n\tfor (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), 0);\n\t}\n\n\t/* Configure pause time (2 TCs per register) */\n\treg = hw->fc.pause_time | (hw->fc.pause_time << 16);\n\tfor (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);\n\n\t/* Configure flow control refresh threshold value */\n\tIXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics\n * @hw: pointer to hardware structure\n *\n * Configure queue statistics registers, all queues belonging to same traffic\n * class uses a single set of queue statistics counters.\n */\ns32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw,\n\t\t\t\t struct ixgbe_dcb_config *dcb_config)\n{\n\tu32 reg = 0;\n\tu8 i = 0;\n\tu8 tc_count = 8;\n\tbool vt_mode = false;\n\n\tif (dcb_config != NULL) {\n\t\ttc_count = dcb_config->num_tcs.pg_tcs;\n\t\tvt_mode = dcb_config->vt_mode;\n\t}\n\n\tif (!((tc_count == 8 && vt_mode == false) || tc_count == 4))\n\t\treturn IXGBE_ERR_PARAM;\n\n\tif (tc_count == 8 && vt_mode == false) {\n\t\t/*\n\t\t * Receive Queues stats setting\n\t\t * 32 RQSMR registers, each configuring 4 queues.\n\t\t *\n\t\t * Set all 16 queues of each TC to the same stat\n\t\t * with TC 'n' going to stat 'n'.\n\t\t */\n\t\tfor (i = 0; i < 32; i++) {\n\t\t\treg = 0x01010101 * (i / 4);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);\n\t\t}\n\t\t/*\n\t\t * Transmit Queues stats setting\n\t\t * 32 TQSM registers, each controlling 4 queues.\n\t\t *\n\t\t * Set all queues of each TC to the same stat\n\t\t * with TC 'n' going to stat 'n'.\n\t\t * Tx queues are allocated non-uniformly to TCs:\n\t\t * 32, 32, 16, 16, 8, 8, 8, 8.\n\t\t */\n\t\tfor (i = 0; i < 32; i++) {\n\t\t\tif (i < 8)\n\t\t\t\treg = 0x00000000;\n\t\t\telse if (i < 16)\n\t\t\t\treg = 0x01010101;\n\t\t\telse if (i < 20)\n\t\t\t\treg = 0x02020202;\n\t\t\telse if (i < 24)\n\t\t\t\treg = 0x03030303;\n\t\t\telse if (i < 26)\n\t\t\t\treg = 0x04040404;\n\t\t\telse if (i < 28)\n\t\t\t\treg = 0x05050505;\n\t\t\telse if (i < 30)\n\t\t\t\treg = 0x06060606;\n\t\t\telse\n\t\t\t\treg = 0x07070707;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);\n\t\t}\n\t} else if (tc_count == 4 && vt_mode == false) {\n\t\t/*\n\t\t * Receive Queues stats setting\n\t\t * 32 RQSMR registers, each configuring 4 queues.\n\t\t *\n\t\t * Set all 16 queues of each TC to the same stat\n\t\t * with TC 'n' going to stat 'n'.\n\t\t */\n\t\tfor (i = 0; i < 32; i++) {\n\t\t\tif (i % 8 > 3)\n\t\t\t\t/* In 4 TC mode, odd 16-queue ranges are\n\t\t\t\t * not used.\n\t\t\t\t*/\n\t\t\t\tcontinue;\n\t\t\treg = 0x01010101 * (i / 8);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);\n\t\t}\n\t\t/*\n\t\t * Transmit Queues stats setting\n\t\t * 32 TQSM registers, each controlling 4 queues.\n\t\t *\n\t\t * Set all queues of each TC to the same stat\n\t\t * with TC 'n' going to stat 'n'.\n\t\t * Tx queues are allocated non-uniformly to TCs:\n\t\t * 64, 32, 16, 16.\n\t\t */\n\t\tfor (i = 0; i < 32; i++) {\n\t\t\tif (i < 16)\n\t\t\t\treg = 0x00000000;\n\t\t\telse if (i < 24)\n\t\t\t\treg = 0x01010101;\n\t\t\telse if (i < 28)\n\t\t\t\treg = 0x02020202;\n\t\t\telse\n\t\t\t\treg = 0x03030303;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);\n\t\t}\n\t} else if (tc_count == 4 && vt_mode == true) {\n\t\t/*\n\t\t * Receive Queues stats setting\n\t\t * 32 RQSMR registers, each configuring 4 queues.\n\t\t *\n\t\t * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each\n\t\t * pool. Set all 32 queues of each TC across pools to the same\n\t\t * stat with TC 'n' going to stat 'n'.\n\t\t */\n\t\tfor (i = 0; i < 32; i++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0x03020100);\n\t\t/*\n\t\t * Transmit Queues stats setting\n\t\t * 32 TQSM registers, each controlling 4 queues.\n\t\t *\n\t\t * Queue Indexing in 32 VF with DCB mode maps 4 TC's to each\n\t\t * pool. Set all 32 queues of each TC across pools to the same\n\t\t * stat with TC 'n' going to stat 'n'.\n\t\t */\n\t\tfor (i = 0; i < 32; i++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0x03020100);\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_config_82599 - Configure general DCB parameters\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure general DCB parameters.\n */\ns32 ixgbe_dcb_config_82599(struct ixgbe_hw *hw,\n\t\t\t struct ixgbe_dcb_config *dcb_config)\n{\n\tu32 reg;\n\tu32 q;\n\n\t/* Disable the Tx desc arbiter so that MTQC can be changed */\n\treg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);\n\treg |= IXGBE_RTTDCS_ARBDIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);\n\n\treg = IXGBE_READ_REG(hw, IXGBE_MRQC);\n\tif (dcb_config->num_tcs.pg_tcs == 8) {\n\t\t/* Enable DCB for Rx with 8 TCs */\n\t\tswitch (reg & IXGBE_MRQC_MRQE_MASK) {\n\t\tcase 0:\n\t\tcase IXGBE_MRQC_RT4TCEN:\n\t\t\t/* RSS disabled cases */\n\t\t\treg = (reg & ~IXGBE_MRQC_MRQE_MASK) |\n\t\t\t IXGBE_MRQC_RT8TCEN;\n\t\t\tbreak;\n\t\tcase IXGBE_MRQC_RSSEN:\n\t\tcase IXGBE_MRQC_RTRSS4TCEN:\n\t\t\t/* RSS enabled cases */\n\t\t\treg = (reg & ~IXGBE_MRQC_MRQE_MASK) |\n\t\t\t IXGBE_MRQC_RTRSS8TCEN;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/*\n\t\t\t * Unsupported value, assume stale data,\n\t\t\t * overwrite no RSS\n\t\t\t */\n\t\t\tASSERT(0);\n\t\t\treg = (reg & ~IXGBE_MRQC_MRQE_MASK) |\n\t\t\t IXGBE_MRQC_RT8TCEN;\n\t\t}\n\t}\n\tif (dcb_config->num_tcs.pg_tcs == 4) {\n\t\t/* We support both VT-on and VT-off with 4 TCs. */\n\t\tif (dcb_config->vt_mode)\n\t\t\treg = (reg & ~IXGBE_MRQC_MRQE_MASK) |\n\t\t\t IXGBE_MRQC_VMDQRT4TCEN;\n\t\telse\n\t\t\treg = (reg & ~IXGBE_MRQC_MRQE_MASK) |\n\t\t\t IXGBE_MRQC_RTRSS4TCEN;\n\t}\n\tIXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);\n\n\t/* Enable DCB for Tx with 8 TCs */\n\tif (dcb_config->num_tcs.pg_tcs == 8)\n\t\treg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;\n\telse {\n\t\t/* We support both VT-on and VT-off with 4 TCs. */\n\t\treg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;\n\t\tif (dcb_config->vt_mode)\n\t\t\treg |= IXGBE_MTQC_VT_ENA;\n\t}\n\tIXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);\n\n\t/* Disable drop for all queues */\n\tfor (q = 0; q < 128; q++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_QDE,\n\t\t\t\t(IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));\n\n\t/* Enable the Tx desc arbiter */\n\treg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);\n\treg &= ~IXGBE_RTTDCS_ARBDIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);\n\n\t/* Enable Security TX Buffer IFG for DCB */\n\treg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);\n\treg |= IXGBE_SECTX_DCB;\n\tIXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dcb_hw_config_82599 - Configure and enable DCB\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n *\n * Configure dcb settings and enable dcb mode.\n */\ns32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, int link_speed,\n\t\t\t u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa,\n\t\t\t u8 *map)\n{\n\tUNREFERENCED_1PARAMETER(link_speed);\n\n\tixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id, tsa,\n\t\t\t\t\t map);\n\tixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,\n\t\t\t\t\t tsa);\n\tixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,\n\t\t\t\t\t tsa, map);\n\n\treturn IXGBE_SUCCESS;\n}\n\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_dcb_82599.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _IXGBE_DCB_82599_H_\n#define _IXGBE_DCB_82599_H_\n\n/* DCB register definitions */\n#define IXGBE_RTTDCS_TDPAC\t0x00000001 /* 0 Round Robin,\n\t\t\t\t\t * 1 WSP - Weighted Strict Priority\n\t\t\t\t\t */\n#define IXGBE_RTTDCS_VMPAC\t0x00000002 /* 0 Round Robin,\n\t\t\t\t\t * 1 WRR - Weighted Round Robin\n\t\t\t\t\t */\n#define IXGBE_RTTDCS_TDRM\t0x00000010 /* Transmit Recycle Mode */\n#define IXGBE_RTTDCS_BDPM\t0x00400000 /* Bypass Data Pipe - must clear! */\n#define IXGBE_RTTDCS_BPBFSM\t0x00800000 /* Bypass PB Free Space - must\n\t\t\t\t\t * clear!\n\t\t\t\t\t */\n#define IXGBE_RTTDCS_SPEED_CHG\t0x80000000 /* Link speed change */\n\n/* Receive UP2TC mapping */\n#define IXGBE_RTRUP2TC_UP_SHIFT\t3\n#define IXGBE_RTRUP2TC_UP_MASK\t7\n/* Transmit UP2TC mapping */\n#define IXGBE_RTTUP2TC_UP_SHIFT\t3\n\n#define IXGBE_RTRPT4C_MCL_SHIFT\t12 /* Offset to Max Credit Limit setting */\n#define IXGBE_RTRPT4C_BWG_SHIFT\t9 /* Offset to BWG index */\n#define IXGBE_RTRPT4C_GSP\t0x40000000 /* GSP enable bit */\n#define IXGBE_RTRPT4C_LSP\t0x80000000 /* LSP enable bit */\n\n#define IXGBE_RDRXCTL_MPBEN\t0x00000010 /* DMA config for multiple packet\n\t\t\t\t\t * buffers enable\n\t\t\t\t\t */\n#define IXGBE_RDRXCTL_MCEN\t0x00000040 /* DMA config for multiple cores\n\t\t\t\t\t * (RSS) enable\n\t\t\t\t\t */\n\n/* RTRPCS Bit Masks */\n#define IXGBE_RTRPCS_RRM\t0x00000002 /* Receive Recycle Mode enable */\n/* Receive Arbitration Control: 0 Round Robin, 1 DFP */\n#define IXGBE_RTRPCS_RAC\t0x00000004\n#define IXGBE_RTRPCS_ARBDIS\t0x00000040 /* Arbitration disable bit */\n\n/* RTTDT2C Bit Masks */\n#define IXGBE_RTTDT2C_MCL_SHIFT\t12\n#define IXGBE_RTTDT2C_BWG_SHIFT\t9\n#define IXGBE_RTTDT2C_GSP\t0x40000000\n#define IXGBE_RTTDT2C_LSP\t0x80000000\n\n#define IXGBE_RTTPT2C_MCL_SHIFT\t12\n#define IXGBE_RTTPT2C_BWG_SHIFT\t9\n#define IXGBE_RTTPT2C_GSP\t0x40000000\n#define IXGBE_RTTPT2C_LSP\t0x80000000\n\n/* RTTPCS Bit Masks */\n#define IXGBE_RTTPCS_TPPAC\t0x00000020 /* 0 Round Robin,\n\t\t\t\t\t * 1 SP - Strict Priority\n\t\t\t\t\t */\n#define IXGBE_RTTPCS_ARBDIS\t0x00000040 /* Arbiter disable */\n#define IXGBE_RTTPCS_TPRM\t0x00000100 /* Transmit Recycle Mode enable */\n#define IXGBE_RTTPCS_ARBD_SHIFT\t22\n#define IXGBE_RTTPCS_ARBD_DCB\t0x4 /* Arbitration delay in DCB mode */\n\n#define IXGBE_TXPBTHRESH_DCB\t0xA /* THRESH value for DCB mode */\n\n/* SECTXMINIFG DCB */\n#define IXGBE_SECTX_DCB\t\t0x00001F00 /* DCB TX Buffer SEC IFG */\n\n/* BCN register definitions */\n#define IXGBE_RTTBCNRC_RF_INT_SHIFT\t14\n#define IXGBE_RTTBCNRC_RS_ENA\t\t0x80000000\n\n#define IXGBE_RTTBCNCR_MNG_CMTGI\t0x00000001\n#define IXGBE_RTTBCNCR_MGN_BCNA_MODE\t0x00000002\n#define IXGBE_RTTBCNCR_RSV7_11_SHIFT\t5\n#define IXGBE_RTTBCNCR_G\t\t0x00000400\n#define IXGBE_RTTBCNCR_I\t\t0x00000800\n#define IXGBE_RTTBCNCR_H\t\t0x00001000\n#define IXGBE_RTTBCNCR_VER_SHIFT\t14\n#define IXGBE_RTTBCNCR_CMT_ETH_SHIFT\t16\n\n#define IXGBE_RTTBCNACL_SMAC_L_SHIFT\t16\n\n#define IXGBE_RTTBCNTG_BCNA_MODE\t0x80000000\n\n#define IXGBE_RTTBCNRTT_TS_SHIFT\t3\n#define IXGBE_RTTBCNRTT_TXQ_IDX_SHIFT\t16\n\n#define IXGBE_RTTBCNRD_BCN_CLEAR_ALL\t0x00000002\n#define IXGBE_RTTBCNRD_DRIFT_FAC_SHIFT\t2\n#define IXGBE_RTTBCNRD_DRIFT_INT_SHIFT\t16\n#define IXGBE_RTTBCNRD_DRIFT_ENA\t0x80000000\n\n\n/* DCB driver APIs */\n\n/* DCB PFC */\ns32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *, u8, u8 *);\n\n/* DCB stats */\ns32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *,\n\t\t\t\t struct ixgbe_dcb_config *);\ns32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *,\n\t\t\t\t struct ixgbe_hw_stats *, u8);\ns32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *,\n\t\t\t\t struct ixgbe_hw_stats *, u8);\n\n/* DCB config arbiters */\ns32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *,\n\t\t\t\t\t u8 *, u8 *);\ns32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *,\n\t\t\t\t\t u8 *, u8 *, u8 *);\ns32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, u8 *,\n\t\t\t\t u8 *, u8 *);\n\n/* DCB initialization */\ns32 ixgbe_dcb_config_82599(struct ixgbe_hw *,\n\t\t\t struct ixgbe_dcb_config *);\n\ns32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *, int, u16 *, u16 *, u8 *,\n\t\t\t u8 *, u8 *);\n#endif /* _IXGBE_DCB_82959_H_ */\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_mbx.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"ixgbe_type.h\"\n#include \"ixgbe_mbx.h\"\n\n/**\n * ixgbe_read_mbx - Reads a message from the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to read\n *\n * returns SUCCESS if it successfully read message from buffer\n **/\ns32 ixgbe_read_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tDEBUGFUNC(\"ixgbe_read_mbx\");\n\n\t/* limit read to size of mailbox */\n\tif (size > mbx->size)\n\t\tsize = mbx->size;\n\n\tif (mbx->ops.read)\n\t\tret_val = mbx->ops.read(hw, msg, size, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_write_mbx - Write a message to the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully copied message into the buffer\n **/\ns32 ixgbe_write_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_write_mbx\");\n\n\tif (size > mbx->size) {\n\t\tret_val = IXGBE_ERR_MBX;\n\t\tERROR_REPORT2(IXGBE_ERROR_ARGUMENT,\n\t\t\t \"Invalid mailbox message size %d\", size);\n\t} else if (mbx->ops.write)\n\t\tret_val = mbx->ops.write(hw, msg, size, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_check_for_msg - checks to see if someone sent us mail\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the Status bit was found or else ERR_MBX\n **/\ns32 ixgbe_check_for_msg(struct ixgbe_hw *hw, u16 mbx_id)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tDEBUGFUNC(\"ixgbe_check_for_msg\");\n\n\tif (mbx->ops.check_for_msg)\n\t\tret_val = mbx->ops.check_for_msg(hw, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_check_for_ack - checks to see if someone sent us ACK\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the Status bit was found or else ERR_MBX\n **/\ns32 ixgbe_check_for_ack(struct ixgbe_hw *hw, u16 mbx_id)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tDEBUGFUNC(\"ixgbe_check_for_ack\");\n\n\tif (mbx->ops.check_for_ack)\n\t\tret_val = mbx->ops.check_for_ack(hw, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_check_for_rst - checks to see if other side has reset\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the Status bit was found or else ERR_MBX\n **/\ns32 ixgbe_check_for_rst(struct ixgbe_hw *hw, u16 mbx_id)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tDEBUGFUNC(\"ixgbe_check_for_rst\");\n\n\tif (mbx->ops.check_for_rst)\n\t\tret_val = mbx->ops.check_for_rst(hw, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_poll_for_msg - Wait for message notification\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully received a message notification\n **/\nSTATIC s32 ixgbe_poll_for_msg(struct ixgbe_hw *hw, u16 mbx_id)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\tint countdown = mbx->timeout;\n\n\tDEBUGFUNC(\"ixgbe_poll_for_msg\");\n\n\tif (!countdown || !mbx->ops.check_for_msg)\n\t\tgoto out;\n\n\twhile (countdown && mbx->ops.check_for_msg(hw, mbx_id)) {\n\t\tcountdown--;\n\t\tif (!countdown)\n\t\t\tbreak;\n\t\tusec_delay(mbx->usec_delay);\n\t}\n\n\tif (countdown == 0)\n\t\tERROR_REPORT2(IXGBE_ERROR_POLLING,\n\t\t\t \"Polling for VF%d mailbox message timedout\", mbx_id);\n\nout:\n\treturn countdown ? IXGBE_SUCCESS : IXGBE_ERR_MBX;\n}\n\n/**\n * ixgbe_poll_for_ack - Wait for message acknowledgement\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully received a message acknowledgement\n **/\nSTATIC s32 ixgbe_poll_for_ack(struct ixgbe_hw *hw, u16 mbx_id)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\tint countdown = mbx->timeout;\n\n\tDEBUGFUNC(\"ixgbe_poll_for_ack\");\n\n\tif (!countdown || !mbx->ops.check_for_ack)\n\t\tgoto out;\n\n\twhile (countdown && mbx->ops.check_for_ack(hw, mbx_id)) {\n\t\tcountdown--;\n\t\tif (!countdown)\n\t\t\tbreak;\n\t\tusec_delay(mbx->usec_delay);\n\t}\n\n\tif (countdown == 0)\n\t\tERROR_REPORT2(IXGBE_ERROR_POLLING,\n\t\t\t \"Polling for VF%d mailbox ack timedout\", mbx_id);\n\nout:\n\treturn countdown ? IXGBE_SUCCESS : IXGBE_ERR_MBX;\n}\n\n/**\n * ixgbe_read_posted_mbx - Wait for message notification and receive message\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully received a message notification and\n * copied it into the receive buffer.\n **/\ns32 ixgbe_read_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tDEBUGFUNC(\"ixgbe_read_posted_mbx\");\n\n\tif (!mbx->ops.read)\n\t\tgoto out;\n\n\tret_val = ixgbe_poll_for_msg(hw, mbx_id);\n\n\t/* if ack received read message, otherwise we timed out */\n\tif (!ret_val)\n\t\tret_val = mbx->ops.read(hw, msg, size, mbx_id);\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_write_posted_mbx - Write a message to the mailbox, wait for ack\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully copied message into the buffer and\n * received an ack to that message within delay * timeout period\n **/\ns32 ixgbe_write_posted_mbx(struct ixgbe_hw *hw, u32 *msg, u16 size,\n\t\t\t u16 mbx_id)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tDEBUGFUNC(\"ixgbe_write_posted_mbx\");\n\n\t/* exit if either we can't write or there isn't a defined timeout */\n\tif (!mbx->ops.write || !mbx->timeout)\n\t\tgoto out;\n\n\t/* send msg */\n\tret_val = mbx->ops.write(hw, msg, size, mbx_id);\n\n\t/* if msg sent wait until we receive an ack */\n\tif (!ret_val)\n\t\tret_val = ixgbe_poll_for_ack(hw, mbx_id);\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_init_mbx_ops_generic - Initialize MB function pointers\n * @hw: pointer to the HW structure\n *\n * Setups up the mailbox read and write message function pointers\n **/\nvoid ixgbe_init_mbx_ops_generic(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\n\tmbx->ops.read_posted = ixgbe_read_posted_mbx;\n\tmbx->ops.write_posted = ixgbe_write_posted_mbx;\n}\n\n/**\n * ixgbe_read_v2p_mailbox - read v2p mailbox\n * @hw: pointer to the HW structure\n *\n * This function is used to read the v2p mailbox without losing the read to\n * clear status bits.\n **/\nSTATIC u32 ixgbe_read_v2p_mailbox(struct ixgbe_hw *hw)\n{\n\tu32 v2p_mailbox = IXGBE_READ_REG(hw, IXGBE_VFMAILBOX);\n\n\tv2p_mailbox |= hw->mbx.v2p_mailbox;\n\thw->mbx.v2p_mailbox |= v2p_mailbox & IXGBE_VFMAILBOX_R2C_BITS;\n\n\treturn v2p_mailbox;\n}\n\n/**\n * ixgbe_check_for_bit_vf - Determine if a status bit was set\n * @hw: pointer to the HW structure\n * @mask: bitmask for bits to be tested and cleared\n *\n * This function is used to check for the read to clear bits within\n * the V2P mailbox.\n **/\nSTATIC s32 ixgbe_check_for_bit_vf(struct ixgbe_hw *hw, u32 mask)\n{\n\tu32 v2p_mailbox = ixgbe_read_v2p_mailbox(hw);\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tif (v2p_mailbox & mask)\n\t\tret_val = IXGBE_SUCCESS;\n\n\thw->mbx.v2p_mailbox &= ~mask;\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_check_for_msg_vf - checks to see if the PF has sent mail\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the PF has set the Status bit or else ERR_MBX\n **/\nSTATIC s32 ixgbe_check_for_msg_vf(struct ixgbe_hw *hw, u16 mbx_id)\n{\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tUNREFERENCED_1PARAMETER(mbx_id);\n\tDEBUGFUNC(\"ixgbe_check_for_msg_vf\");\n\n\tif (!ixgbe_check_for_bit_vf(hw, IXGBE_VFMAILBOX_PFSTS)) {\n\t\tret_val = IXGBE_SUCCESS;\n\t\thw->mbx.stats.reqs++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_check_for_ack_vf - checks to see if the PF has ACK'd\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the PF has set the ACK bit or else ERR_MBX\n **/\nSTATIC s32 ixgbe_check_for_ack_vf(struct ixgbe_hw *hw, u16 mbx_id)\n{\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tUNREFERENCED_1PARAMETER(mbx_id);\n\tDEBUGFUNC(\"ixgbe_check_for_ack_vf\");\n\n\tif (!ixgbe_check_for_bit_vf(hw, IXGBE_VFMAILBOX_PFACK)) {\n\t\tret_val = IXGBE_SUCCESS;\n\t\thw->mbx.stats.acks++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_check_for_rst_vf - checks to see if the PF has reset\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns true if the PF has set the reset done bit or else false\n **/\nSTATIC s32 ixgbe_check_for_rst_vf(struct ixgbe_hw *hw, u16 mbx_id)\n{\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tUNREFERENCED_1PARAMETER(mbx_id);\n\tDEBUGFUNC(\"ixgbe_check_for_rst_vf\");\n\n\tif (!ixgbe_check_for_bit_vf(hw, (IXGBE_VFMAILBOX_RSTD |\n\t IXGBE_VFMAILBOX_RSTI))) {\n\t\tret_val = IXGBE_SUCCESS;\n\t\thw->mbx.stats.rsts++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_obtain_mbx_lock_vf - obtain mailbox lock\n * @hw: pointer to the HW structure\n *\n * return SUCCESS if we obtained the mailbox lock\n **/\nSTATIC s32 ixgbe_obtain_mbx_lock_vf(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tDEBUGFUNC(\"ixgbe_obtain_mbx_lock_vf\");\n\n\t/* Take ownership of the buffer */\n\tIXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_VFU);\n\n\t/* reserve mailbox for vf use */\n\tif (ixgbe_read_v2p_mailbox(hw) & IXGBE_VFMAILBOX_VFU)\n\t\tret_val = IXGBE_SUCCESS;\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_write_mbx_vf - Write a message to the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully copied message into the buffer\n **/\nSTATIC s32 ixgbe_write_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,\n\t\t\t u16 mbx_id)\n{\n\ts32 ret_val;\n\tu16 i;\n\n\tUNREFERENCED_1PARAMETER(mbx_id);\n\n\tDEBUGFUNC(\"ixgbe_write_mbx_vf\");\n\n\t/* lock the mailbox to prevent pf/vf race condition */\n\tret_val = ixgbe_obtain_mbx_lock_vf(hw);\n\tif (ret_val)\n\t\tgoto out_no_write;\n\n\t/* flush msg and acks as we are overwriting the message buffer */\n\tixgbe_check_for_msg_vf(hw, 0);\n\tixgbe_check_for_ack_vf(hw, 0);\n\n\t/* copy the caller specified message to the mailbox memory buffer */\n\tfor (i = 0; i < size; i++)\n\t\tIXGBE_WRITE_REG_ARRAY(hw, IXGBE_VFMBMEM, i, msg[i]);\n\n\t/*\n\t * Complete the remaining mailbox data registers with zero to reset\n\t * the data sent in a previous exchange (in either side) with the PF,\n\t * including exchanges performed by another Guest OS to which that VF\n\t * was previously assigned.\n\t */\n\twhile (i < hw->mbx.size) {\n\t\tIXGBE_WRITE_REG_ARRAY(hw, IXGBE_VFMBMEM, i, 0);\n\t\ti++;\n\t}\n\n\t/* update stats */\n\thw->mbx.stats.msgs_tx++;\n\n\t/* Drop VFU and interrupt the PF to tell it a message has been sent */\n\tIXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_REQ);\n\nout_no_write:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_read_mbx_vf - Reads a message from the inbox intended for vf\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to read\n *\n * returns SUCCESS if it successfully read message from buffer\n **/\nSTATIC s32 ixgbe_read_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,\n\t\t\t u16 mbx_id)\n{\n\ts32 ret_val = IXGBE_SUCCESS;\n\tu16 i;\n\n\tDEBUGFUNC(\"ixgbe_read_mbx_vf\");\n\tUNREFERENCED_1PARAMETER(mbx_id);\n\n\t/* lock the mailbox to prevent pf/vf race condition */\n\tret_val = ixgbe_obtain_mbx_lock_vf(hw);\n\tif (ret_val)\n\t\tgoto out_no_read;\n\n\t/* copy the message from the mailbox memory buffer */\n\tfor (i = 0; i < size; i++)\n\t\tmsg[i] = IXGBE_READ_REG_ARRAY(hw, IXGBE_VFMBMEM, i);\n\n\t/* Acknowledge receipt and release mailbox, then we're done */\n\tIXGBE_WRITE_REG(hw, IXGBE_VFMAILBOX, IXGBE_VFMAILBOX_ACK);\n\n\t/* update stats */\n\thw->mbx.stats.msgs_rx++;\n\nout_no_read:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_init_mbx_params_vf - set initial values for vf mailbox\n * @hw: pointer to the HW structure\n *\n * Initializes the hw->mbx struct to correct values for vf mailbox\n */\nvoid ixgbe_init_mbx_params_vf(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\n\t/* start mailbox as timed out and let the reset_hw call set the timeout\n\t * value to begin communications */\n\tmbx->timeout = 0;\n\tmbx->usec_delay = IXGBE_VF_MBX_INIT_DELAY;\n\n\tmbx->size = IXGBE_VFMAILBOX_SIZE;\n\n\tmbx->ops.read = ixgbe_read_mbx_vf;\n\tmbx->ops.write = ixgbe_write_mbx_vf;\n\tmbx->ops.read_posted = ixgbe_read_posted_mbx;\n\tmbx->ops.write_posted = ixgbe_write_posted_mbx;\n\tmbx->ops.check_for_msg = ixgbe_check_for_msg_vf;\n\tmbx->ops.check_for_ack = ixgbe_check_for_ack_vf;\n\tmbx->ops.check_for_rst = ixgbe_check_for_rst_vf;\n\n\tmbx->stats.msgs_tx = 0;\n\tmbx->stats.msgs_rx = 0;\n\tmbx->stats.reqs = 0;\n\tmbx->stats.acks = 0;\n\tmbx->stats.rsts = 0;\n}\n\nSTATIC s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index)\n{\n\tu32 mbvficr = IXGBE_READ_REG(hw, IXGBE_MBVFICR(index));\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tif (mbvficr & mask) {\n\t\tret_val = IXGBE_SUCCESS;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MBVFICR(index), mask);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_check_for_msg_pf - checks to see if the VF has sent mail\n * @hw: pointer to the HW structure\n * @vf_number: the VF index\n *\n * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n **/\nSTATIC s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number)\n{\n\ts32 ret_val = IXGBE_ERR_MBX;\n\ts32 index = IXGBE_MBVFICR_INDEX(vf_number);\n\tu32 vf_bit = vf_number % 16;\n\n\tDEBUGFUNC(\"ixgbe_check_for_msg_pf\");\n\n\tif (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFREQ_VF1 << vf_bit,\n\t\t\t\t index)) {\n\t\tret_val = IXGBE_SUCCESS;\n\t\thw->mbx.stats.reqs++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_check_for_ack_pf - checks to see if the VF has ACKed\n * @hw: pointer to the HW structure\n * @vf_number: the VF index\n *\n * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n **/\nSTATIC s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number)\n{\n\ts32 ret_val = IXGBE_ERR_MBX;\n\ts32 index = IXGBE_MBVFICR_INDEX(vf_number);\n\tu32 vf_bit = vf_number % 16;\n\n\tDEBUGFUNC(\"ixgbe_check_for_ack_pf\");\n\n\tif (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFACK_VF1 << vf_bit,\n\t\t\t\t index)) {\n\t\tret_val = IXGBE_SUCCESS;\n\t\thw->mbx.stats.acks++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_check_for_rst_pf - checks to see if the VF has reset\n * @hw: pointer to the HW structure\n * @vf_number: the VF index\n *\n * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n **/\nSTATIC s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number)\n{\n\tu32 reg_offset = (vf_number < 32) ? 0 : 1;\n\tu32 vf_shift = vf_number % 32;\n\tu32 vflre = 0;\n\ts32 ret_val = IXGBE_ERR_MBX;\n\n\tDEBUGFUNC(\"ixgbe_check_for_rst_pf\");\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82599EB:\n\t\tvflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));\n\t\tbreak;\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\tcase ixgbe_mac_X540:\n\t\tvflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (vflre & (1 << vf_shift)) {\n\t\tret_val = IXGBE_SUCCESS;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift));\n\t\thw->mbx.stats.rsts++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_obtain_mbx_lock_pf - obtain mailbox lock\n * @hw: pointer to the HW structure\n * @vf_number: the VF index\n *\n * return SUCCESS if we obtained the mailbox lock\n **/\nSTATIC s32 ixgbe_obtain_mbx_lock_pf(struct ixgbe_hw *hw, u16 vf_number)\n{\n\ts32 ret_val = IXGBE_ERR_MBX;\n\tu32 p2v_mailbox;\n\n\tDEBUGFUNC(\"ixgbe_obtain_mbx_lock_pf\");\n\n\t/* Take ownership of the buffer */\n\tIXGBE_WRITE_REG(hw, IXGBE_PFMAILBOX(vf_number), IXGBE_PFMAILBOX_PFU);\n\n\t/* reserve mailbox for vf use */\n\tp2v_mailbox = IXGBE_READ_REG(hw, IXGBE_PFMAILBOX(vf_number));\n\tif (p2v_mailbox & IXGBE_PFMAILBOX_PFU)\n\t\tret_val = IXGBE_SUCCESS;\n\telse\n\t\tERROR_REPORT2(IXGBE_ERROR_POLLING,\n\t\t\t \"Failed to obtain mailbox lock for VF%d\", vf_number);\n\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_write_mbx_pf - Places a message in the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @vf_number: the VF index\n *\n * returns SUCCESS if it successfully copied message into the buffer\n **/\nSTATIC s32 ixgbe_write_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size,\n\t\t\t u16 vf_number)\n{\n\ts32 ret_val;\n\tu16 i;\n\n\tDEBUGFUNC(\"ixgbe_write_mbx_pf\");\n\n\t/* lock the mailbox to prevent pf/vf race condition */\n\tret_val = ixgbe_obtain_mbx_lock_pf(hw, vf_number);\n\tif (ret_val)\n\t\tgoto out_no_write;\n\n\t/* flush msg and acks as we are overwriting the message buffer */\n\tixgbe_check_for_msg_pf(hw, vf_number);\n\tixgbe_check_for_ack_pf(hw, vf_number);\n\n\t/* copy the caller specified message to the mailbox memory buffer */\n\tfor (i = 0; i < size; i++)\n\t\tIXGBE_WRITE_REG_ARRAY(hw, IXGBE_PFMBMEM(vf_number), i, msg[i]);\n\n\t/*\n\t * Complete the remaining mailbox data registers with zero to reset\n\t * the data sent in a previous exchange (in either side) with the VF,\n\t * including exchanges performed by another Guest OS to which that VF\n\t * was previously assigned.\n\t */\n\twhile (i < hw->mbx.size) {\n\t\tIXGBE_WRITE_REG_ARRAY(hw, IXGBE_PFMBMEM(vf_number), i, 0);\n\t\ti++;\n\t}\n\n\t/* Interrupt VF to tell it a message has been sent and release buffer*/\n\tIXGBE_WRITE_REG(hw, IXGBE_PFMAILBOX(vf_number), IXGBE_PFMAILBOX_STS);\n\n\t/* update stats */\n\thw->mbx.stats.msgs_tx++;\n\nout_no_write:\n\treturn ret_val;\n\n}\n\n/**\n * ixgbe_read_mbx_pf - Read a message from the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @vf_number: the VF index\n *\n * This function copies a message from the mailbox buffer to the caller's\n * memory buffer. The presumption is that the caller knows that there was\n * a message due to a VF request so no polling for message is needed.\n **/\nSTATIC s32 ixgbe_read_mbx_pf(struct ixgbe_hw *hw, u32 *msg, u16 size,\n\t\t\t u16 vf_number)\n{\n\ts32 ret_val;\n\tu16 i;\n\n\tDEBUGFUNC(\"ixgbe_read_mbx_pf\");\n\n\t/* lock the mailbox to prevent pf/vf race condition */\n\tret_val = ixgbe_obtain_mbx_lock_pf(hw, vf_number);\n\tif (ret_val)\n\t\tgoto out_no_read;\n\n\t/* copy the message to the mailbox memory buffer */\n\tfor (i = 0; i < size; i++)\n\t\tmsg[i] = IXGBE_READ_REG_ARRAY(hw, IXGBE_PFMBMEM(vf_number), i);\n\n\t/* Acknowledge the message and release buffer */\n\tIXGBE_WRITE_REG(hw, IXGBE_PFMAILBOX(vf_number), IXGBE_PFMAILBOX_ACK);\n\n\t/* update stats */\n\thw->mbx.stats.msgs_rx++;\n\nout_no_read:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_init_mbx_params_pf - set initial values for pf mailbox\n * @hw: pointer to the HW structure\n *\n * Initializes the hw->mbx struct to correct values for pf mailbox\n */\nvoid ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\n\tif (hw->mac.type != ixgbe_mac_82599EB &&\n\t hw->mac.type != ixgbe_mac_X550 &&\n\t hw->mac.type != ixgbe_mac_X550EM_x &&\n\t hw->mac.type != ixgbe_mac_X540)\n\t\treturn;\n\n\tmbx->timeout = 0;\n\tmbx->usec_delay = 0;\n\n\tmbx->size = IXGBE_VFMAILBOX_SIZE;\n\n\tmbx->ops.read = ixgbe_read_mbx_pf;\n\tmbx->ops.write = ixgbe_write_mbx_pf;\n\tmbx->ops.read_posted = ixgbe_read_posted_mbx;\n\tmbx->ops.write_posted = ixgbe_write_posted_mbx;\n\tmbx->ops.check_for_msg = ixgbe_check_for_msg_pf;\n\tmbx->ops.check_for_ack = ixgbe_check_for_ack_pf;\n\tmbx->ops.check_for_rst = ixgbe_check_for_rst_pf;\n\n\tmbx->stats.msgs_tx = 0;\n\tmbx->stats.msgs_rx = 0;\n\tmbx->stats.reqs = 0;\n\tmbx->stats.acks = 0;\n\tmbx->stats.rsts = 0;\n}\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_mbx.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _IXGBE_MBX_H_\n#define _IXGBE_MBX_H_\n\n#include \"ixgbe_type.h\"\n\n#define IXGBE_VFMAILBOX_SIZE\t16 /* 16 32 bit words - 64 bytes */\n#define IXGBE_ERR_MBX\t\t-100\n\n#define IXGBE_VFMAILBOX\t\t0x002FC\n#define IXGBE_VFMBMEM\t\t0x00200\n\n/* Define mailbox register bits */\n#define IXGBE_VFMAILBOX_REQ\t0x00000001 /* Request for PF Ready bit */\n#define IXGBE_VFMAILBOX_ACK\t0x00000002 /* Ack PF message received */\n#define IXGBE_VFMAILBOX_VFU\t0x00000004 /* VF owns the mailbox buffer */\n#define IXGBE_VFMAILBOX_PFU\t0x00000008 /* PF owns the mailbox buffer */\n#define IXGBE_VFMAILBOX_PFSTS\t0x00000010 /* PF wrote a message in the MB */\n#define IXGBE_VFMAILBOX_PFACK\t0x00000020 /* PF ack the previous VF msg */\n#define IXGBE_VFMAILBOX_RSTI\t0x00000040 /* PF has reset indication */\n#define IXGBE_VFMAILBOX_RSTD\t0x00000080 /* PF has indicated reset done */\n#define IXGBE_VFMAILBOX_R2C_BITS\t0x000000B0 /* All read to clear bits */\n\n#define IXGBE_PFMAILBOX_STS\t0x00000001 /* Initiate message send to VF */\n#define IXGBE_PFMAILBOX_ACK\t0x00000002 /* Ack message recv'd from VF */\n#define IXGBE_PFMAILBOX_VFU\t0x00000004 /* VF owns the mailbox buffer */\n#define IXGBE_PFMAILBOX_PFU\t0x00000008 /* PF owns the mailbox buffer */\n#define IXGBE_PFMAILBOX_RVFU\t0x00000010 /* Reset VFU - used when VF stuck */\n\n#define IXGBE_MBVFICR_VFREQ_MASK\t0x0000FFFF /* bits for VF messages */\n#define IXGBE_MBVFICR_VFREQ_VF1\t\t0x00000001 /* bit for VF 1 message */\n#define IXGBE_MBVFICR_VFACK_MASK\t0xFFFF0000 /* bits for VF acks */\n#define IXGBE_MBVFICR_VFACK_VF1\t\t0x00010000 /* bit for VF 1 ack */\n\n\n/* If it's a IXGBE_VF_* msg then it originates in the VF and is sent to the\n * PF. The reverse is true if it is IXGBE_PF_*.\n * Message ACK's are the value or'd with 0xF0000000\n */\n#define IXGBE_VT_MSGTYPE_ACK\t0x80000000 /* Messages below or'd with\n\t\t\t\t\t * this are the ACK */\n#define IXGBE_VT_MSGTYPE_NACK\t0x40000000 /* Messages below or'd with\n\t\t\t\t\t * this are the NACK */\n#define IXGBE_VT_MSGTYPE_CTS\t0x20000000 /* Indicates that VF is still\n\t\t\t\t\t * clear to send requests */\n#define IXGBE_VT_MSGINFO_SHIFT\t16\n/* bits 23:16 are used for extra info for certain messages */\n#define IXGBE_VT_MSGINFO_MASK\t(0xFF << IXGBE_VT_MSGINFO_SHIFT)\n\n/* definitions to support mailbox API version negotiation */\n\n/*\n * each element denotes a version of the API; existing numbers may not\n * change; any additions must go at the end\n */\nenum ixgbe_pfvf_api_rev {\n\tixgbe_mbox_api_10,\t/* API version 1.0, linux/freebsd VF driver */\n\tixgbe_mbox_api_20,\t/* API version 2.0, solaris Phase1 VF driver */\n\tixgbe_mbox_api_11,\t/* API version 1.1, linux/freebsd VF driver */\n\t/* This value should always be last */\n\tixgbe_mbox_api_unknown,\t/* indicates that API version is not known */\n};\n\n/* mailbox API, legacy requests */\n#define IXGBE_VF_RESET\t\t0x01 /* VF requests reset */\n#define IXGBE_VF_SET_MAC_ADDR\t0x02 /* VF requests PF to set MAC addr */\n#define IXGBE_VF_SET_MULTICAST\t0x03 /* VF requests PF to set MC addr */\n#define IXGBE_VF_SET_VLAN\t0x04 /* VF requests PF to set VLAN */\n\n/* mailbox API, version 1.0 VF requests */\n#define IXGBE_VF_SET_LPE\t0x05 /* VF requests PF to set VMOLR.LPE */\n#define IXGBE_VF_SET_MACVLAN\t0x06 /* VF requests PF for unicast filter */\n#define IXGBE_VF_API_NEGOTIATE\t0x08 /* negotiate API version */\n\n/* mailbox API, version 1.1 VF requests */\n#define IXGBE_VF_GET_QUEUES\t0x09 /* get queue configuration */\n\n/* GET_QUEUES return data indices within the mailbox */\n#define IXGBE_VF_TX_QUEUES\t1\t/* number of Tx queues supported */\n#define IXGBE_VF_RX_QUEUES\t2\t/* number of Rx queues supported */\n#define IXGBE_VF_TRANS_VLAN\t3\t/* Indication of port vlan */\n#define IXGBE_VF_DEF_QUEUE\t4\t/* Default queue offset */\n\n/* length of permanent address message returned from PF */\n#define IXGBE_VF_PERMADDR_MSG_LEN\t4\n/* word in permanent address message with the current multicast type */\n#define IXGBE_VF_MC_TYPE_WORD\t\t3\n\n#define IXGBE_PF_CONTROL_MSG\t\t0x0100 /* PF control message */\n\n/* mailbox API, version 2.0 VF requests */\n#define IXGBE_VF_API_NEGOTIATE\t\t0x08 /* negotiate API version */\n#define IXGBE_VF_GET_QUEUES\t\t0x09 /* get queue configuration */\n#define IXGBE_VF_ENABLE_MACADDR\t\t0x0A /* enable MAC address */\n#define IXGBE_VF_DISABLE_MACADDR\t0x0B /* disable MAC address */\n#define IXGBE_VF_GET_MACADDRS\t\t0x0C /* get all configured MAC addrs */\n#define IXGBE_VF_SET_MCAST_PROMISC\t0x0D /* enable multicast promiscuous */\n#define IXGBE_VF_GET_MTU\t\t0x0E /* get bounds on MTU */\n#define IXGBE_VF_SET_MTU\t\t0x0F /* set a specific MTU */\n\n/* mailbox API, version 2.0 PF requests */\n#define IXGBE_PF_TRANSPARENT_VLAN\t0x0101 /* enable transparent vlan */\n\n#define IXGBE_VF_MBX_INIT_TIMEOUT\t2000 /* number of retries on mailbox */\n#define IXGBE_VF_MBX_INIT_DELAY\t\t500 /* microseconds between retries */\n\ns32 ixgbe_read_mbx(struct ixgbe_hw *, u32 *, u16, u16);\ns32 ixgbe_write_mbx(struct ixgbe_hw *, u32 *, u16, u16);\ns32 ixgbe_read_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);\ns32 ixgbe_write_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);\ns32 ixgbe_check_for_msg(struct ixgbe_hw *, u16);\ns32 ixgbe_check_for_ack(struct ixgbe_hw *, u16);\ns32 ixgbe_check_for_rst(struct ixgbe_hw *, u16);\nvoid ixgbe_init_mbx_ops_generic(struct ixgbe_hw *hw);\nvoid ixgbe_init_mbx_params_vf(struct ixgbe_hw *);\nvoid ixgbe_init_mbx_params_pf(struct ixgbe_hw *);\n\n#endif /* _IXGBE_MBX_H_ */\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_osdep.h", "content": "/******************************************************************************\n\n Copyright (c) 2001-2015, Intel Corporation\n All rights reserved.\n \n Redistribution and use in source and binary forms, with or without \n modification, are permitted provided that the following conditions are met:\n \n 1. Redistributions of source code must retain the above copyright notice, \n this list of conditions and the following disclaimer.\n \n 2. Redistributions in binary form must reproduce the above copyright \n notice, this list of conditions and the following disclaimer in the \n documentation and/or other materials provided with the distribution.\n \n 3. Neither the name of the Intel Corporation nor the names of its \n contributors may be used to endorse or promote products derived from \n this software without specific prior written permission.\n \n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE \n IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE \n ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE \n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR \n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF \n SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS \n INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN \n CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n POSSIBILITY OF SUCH DAMAGE.\n\n******************************************************************************/\n/*$FreeBSD$*/\n\n#ifndef _IXGBE_OS_H_\n#define _IXGBE_OS_H_\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"../ixgbe_logs.h\"\n#include \"../ixgbe_bypass_defines.h\"\n\n#define ASSERT(x) if(!(x)) rte_panic(\"IXGBE: x\")\n\n#define DELAY(x) rte_delay_us(x)\n#define usec_delay(x) DELAY(x)\n#define msec_delay(x) DELAY(1000*(x))\n\n#define DEBUGFUNC(F) DEBUGOUT(F \"\\n\");\n#define DEBUGOUT(S, args...) PMD_DRV_LOG_RAW(DEBUG, S, ##args)\n#define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)\n#define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)\n#define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)\n#define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)\n#define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)\n\n#define ERROR_REPORT1(e, S, args...) DEBUGOUT(S, ##args)\n#define ERROR_REPORT2(e, S, args...) DEBUGOUT(S, ##args)\n#define ERROR_REPORT3(e, S, args...) DEBUGOUT(S, ##args)\n\n#define FALSE 0\n#define TRUE 1\n\n#define false 0\n#define true 1\n#define min(a,b)\tRTE_MIN(a,b) \n\n#define EWARN(hw, S, args...) DEBUGOUT1(S, ##args)\n\n/* Bunch of defines for shared code bogosity */\n#define UNREFERENCED_PARAMETER(_p) \n#define UNREFERENCED_1PARAMETER(_p) \n#define UNREFERENCED_2PARAMETER(_p, _q)\n#define UNREFERENCED_3PARAMETER(_p, _q, _r) \n#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) \n\n/* Shared code error reporting */\nenum {\n\tIXGBE_ERROR_SOFTWARE,\n\tIXGBE_ERROR_POLLING,\n\tIXGBE_ERROR_INVALID_STATE,\n\tIXGBE_ERROR_UNSUPPORTED,\n\tIXGBE_ERROR_ARGUMENT,\n\tIXGBE_ERROR_CAUTION,\n};\n\n#define STATIC static\n#define IXGBE_NTOHL(_i)\trte_be_to_cpu_32(_i)\n#define IXGBE_NTOHS(_i)\trte_be_to_cpu_16(_i)\n#define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i)\n#define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)\n#define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i)\n#define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i)\n\ntypedef uint8_t\t\tu8;\ntypedef int8_t\t\ts8;\ntypedef uint16_t\tu16;\ntypedef int16_t\t\ts16;\ntypedef uint32_t\tu32;\ntypedef int32_t\t\ts32;\ntypedef uint64_t\tu64;\ntypedef int\t\tbool;\n\n#define mb()\trte_mb()\n#define wmb()\trte_wmb()\n#define rmb()\trte_rmb()\n\n#define IOMEM\n\n#define prefetch(x) rte_prefetch0(x)\n\n#define IXGBE_PCI_REG(reg) (*((volatile uint32_t *)(reg)))\n\nstatic inline uint32_t ixgbe_read_addr(volatile void* addr)\n{\n\treturn rte_le_to_cpu_32(IXGBE_PCI_REG(addr));\n}\n\n#define IXGBE_PCI_REG_WRITE(reg, value) do { \\\n\tIXGBE_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \\\n} while(0)\n\n#define IXGBE_PCI_REG_ADDR(hw, reg) \\\n\t((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))\n\n#define IXGBE_PCI_REG_ARRAY_ADDR(hw, reg, index) \\\n\tIXGBE_PCI_REG_ADDR((hw), (reg) + ((index) << 2))\n\n/* Not implemented !! */\n#define IXGBE_READ_PCIE_WORD(hw, reg) 0\t\n#define IXGBE_WRITE_PCIE_WORD(hw, reg, value) do { } while(0)\n\n#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)\n\n#define IXGBE_READ_REG(hw, reg) \\\n\tixgbe_read_addr(IXGBE_PCI_REG_ADDR((hw), (reg)))\n\n#define IXGBE_WRITE_REG(hw, reg, value) \\\n\tIXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ADDR((hw), (reg)), (value))\n\n#define IXGBE_READ_REG_ARRAY(hw, reg, index) \\\n\tIXGBE_PCI_REG(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))\n\n#define IXGBE_WRITE_REG_ARRAY(hw, reg, index, value) \\\n\tIXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))\n\n#endif /* _IXGBE_OS_H_ */\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_phy.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"ixgbe_api.h\"\n#include \"ixgbe_common.h\"\n#include \"ixgbe_phy.h\"\n\nSTATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);\nSTATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);\nSTATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);\nSTATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);\nSTATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);\nSTATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);\nSTATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);\nSTATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);\nSTATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);\nSTATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);\nSTATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);\nSTATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\t u8 *sff8472_data);\n\n/**\n * ixgbe_out_i2c_byte_ack - Send I2C byte with ack\n * @hw: pointer to the hardware structure\n * @byte: byte to send\n *\n * Returns an error code on error.\n */\nSTATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)\n{\n\ts32 status;\n\n\tstatus = ixgbe_clock_out_i2c_byte(hw, byte);\n\tif (status)\n\t\treturn status;\n\treturn ixgbe_get_i2c_ack(hw);\n}\n\n/**\n * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack\n * @hw: pointer to the hardware structure\n * @byte: pointer to a u8 to receive the byte\n *\n * Returns an error code on error.\n */\nSTATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)\n{\n\ts32 status;\n\n\tstatus = ixgbe_clock_in_i2c_byte(hw, byte);\n\tif (status)\n\t\treturn status;\n\t/* ACK */\n\treturn ixgbe_clock_out_i2c_bit(hw, false);\n}\n\n/**\n * ixgbe_ones_comp_byte_add - Perform one's complement addition\n * @add1 - addend 1\n * @add2 - addend 2\n *\n * Returns one's complement 8-bit sum.\n */\nSTATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)\n{\n\tu16 sum = add1 + add2;\n\n\tsum = (sum & 0xFF) + (sum >> 8);\n\treturn sum & 0xFF;\n}\n\n/**\n * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation\n * @hw: pointer to the hardware structure\n * @addr: I2C bus address to read from\n * @reg: I2C device register to read from\n * @val: pointer to location to receive read value\n * @lock: true if to take and release semaphore\n *\n * Returns an error code on error.\n */\nSTATIC s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,\n\t\t\t\t\t u16 reg, u16 *val, bool lock)\n{\n\tu32 swfw_mask = hw->phy.phy_semaphore_mask;\n\tint max_retry = 10;\n\tint retry = 0;\n\tu8 csum_byte;\n\tu8 high_bits;\n\tu8 low_bits;\n\tu8 reg_high;\n\tu8 csum;\n\n\tif (hw->mac.type >= ixgbe_mac_X550)\n\t\tmax_retry = 3;\n\treg_high = ((reg >> 7) & 0xFE) | 1;\t/* Indicate read combined */\n\tcsum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);\n\tcsum = ~csum;\n\tdo {\n\t\tif (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))\n\t\t\treturn IXGBE_ERR_SWFW_SYNC;\n\t\tixgbe_i2c_start(hw);\n\t\t/* Device Address and write indication */\n\t\tif (ixgbe_out_i2c_byte_ack(hw, addr))\n\t\t\tgoto fail;\n\t\t/* Write bits 14:8 */\n\t\tif (ixgbe_out_i2c_byte_ack(hw, reg_high))\n\t\t\tgoto fail;\n\t\t/* Write bits 7:0 */\n\t\tif (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))\n\t\t\tgoto fail;\n\t\t/* Write csum */\n\t\tif (ixgbe_out_i2c_byte_ack(hw, csum))\n\t\t\tgoto fail;\n\t\t/* Re-start condition */\n\t\tixgbe_i2c_start(hw);\n\t\t/* Device Address and read indication */\n\t\tif (ixgbe_out_i2c_byte_ack(hw, addr | 1))\n\t\t\tgoto fail;\n\t\t/* Get upper bits */\n\t\tif (ixgbe_in_i2c_byte_ack(hw, &high_bits))\n\t\t\tgoto fail;\n\t\t/* Get low bits */\n\t\tif (ixgbe_in_i2c_byte_ack(hw, &low_bits))\n\t\t\tgoto fail;\n\t\t/* Get csum */\n\t\tif (ixgbe_clock_in_i2c_byte(hw, &csum_byte))\n\t\t\tgoto fail;\n\t\t/* NACK */\n\t\tif (ixgbe_clock_out_i2c_bit(hw, false))\n\t\t\tgoto fail;\n\t\tixgbe_i2c_stop(hw);\n\t\tif (lock)\n\t\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\t\t*val = (high_bits << 8) | low_bits;\n\t\treturn 0;\n\nfail:\n\t\tixgbe_i2c_bus_clear(hw);\n\t\tif (lock)\n\t\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\t\tretry++;\n\t\tif (retry < max_retry)\n\t\t\tDEBUGOUT(\"I2C byte read combined error - Retrying.\\n\");\n\t\telse\n\t\t\tDEBUGOUT(\"I2C byte read combined error.\\n\");\n\t} while (retry < max_retry);\n\n\treturn IXGBE_ERR_I2C;\n}\n\n/**\n * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation\n * @hw: pointer to the hardware structure\n * @addr: I2C bus address to read from\n * @reg: I2C device register to read from\n * @val: pointer to location to receive read value\n *\n * Returns an error code on error.\n **/\nSTATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,\n\t\t\t\t\t u16 reg, u16 *val)\n{\n\treturn ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);\n}\n\n/**\n * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation\n * @hw: pointer to the hardware structure\n * @addr: I2C bus address to read from\n * @reg: I2C device register to read from\n * @val: pointer to location to receive read value\n *\n * Returns an error code on error.\n **/\nSTATIC s32\nixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,\n\t\t\t\t\t u16 reg, u16 *val)\n{\n\treturn ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);\n}\n\n/**\n * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation\n * @hw: pointer to the hardware structure\n * @addr: I2C bus address to write to\n * @reg: I2C device register to write to\n * @val: value to write\n * @lock: true if to take and release semaphore\n *\n * Returns an error code on error.\n */\nSTATIC s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,\n\t\t\t\t\t\tu16 reg, u16 val, bool lock)\n{\n\tu32 swfw_mask = hw->phy.phy_semaphore_mask;\n\tint max_retry = 1;\n\tint retry = 0;\n\tu8 reg_high;\n\tu8 csum;\n\n\treg_high = (reg >> 7) & 0xFE;\t/* Indicate write combined */\n\tcsum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);\n\tcsum = ixgbe_ones_comp_byte_add(csum, val >> 8);\n\tcsum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);\n\tcsum = ~csum;\n\tdo {\n\t\tif (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))\n\t\t\treturn IXGBE_ERR_SWFW_SYNC;\n\t\tixgbe_i2c_start(hw);\n\t\t/* Device Address and write indication */\n\t\tif (ixgbe_out_i2c_byte_ack(hw, addr))\n\t\t\tgoto fail;\n\t\t/* Write bits 14:8 */\n\t\tif (ixgbe_out_i2c_byte_ack(hw, reg_high))\n\t\t\tgoto fail;\n\t\t/* Write bits 7:0 */\n\t\tif (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))\n\t\t\tgoto fail;\n\t\t/* Write data 15:8 */\n\t\tif (ixgbe_out_i2c_byte_ack(hw, val >> 8))\n\t\t\tgoto fail;\n\t\t/* Write data 7:0 */\n\t\tif (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))\n\t\t\tgoto fail;\n\t\t/* Write csum */\n\t\tif (ixgbe_out_i2c_byte_ack(hw, csum))\n\t\t\tgoto fail;\n\t\tixgbe_i2c_stop(hw);\n\t\tif (lock)\n\t\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\t\treturn 0;\n\nfail:\n\t\tixgbe_i2c_bus_clear(hw);\n\t\tif (lock)\n\t\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\t\tretry++;\n\t\tif (retry < max_retry)\n\t\t\tDEBUGOUT(\"I2C byte write combined error - Retrying.\\n\");\n\t\telse\n\t\t\tDEBUGOUT(\"I2C byte write combined error.\\n\");\n\t} while (retry < max_retry);\n\n\treturn IXGBE_ERR_I2C;\n}\n\n/**\n * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation\n * @hw: pointer to the hardware structure\n * @addr: I2C bus address to write to\n * @reg: I2C device register to write to\n * @val: value to write\n *\n * Returns an error code on error.\n **/\nSTATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t u8 addr, u16 reg, u16 val)\n{\n\treturn ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);\n}\n\n/**\n * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation\n * @hw: pointer to the hardware structure\n * @addr: I2C bus address to write to\n * @reg: I2C device register to write to\n * @val: value to write\n *\n * Returns an error code on error.\n **/\nSTATIC s32\nixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,\n\t\t\t\t\t u8 addr, u16 reg, u16 val)\n{\n\treturn ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);\n}\n\n/**\n * ixgbe_init_phy_ops_generic - Inits PHY function ptrs\n * @hw: pointer to the hardware structure\n *\n * Initialize the function pointers.\n **/\ns32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\n\tDEBUGFUNC(\"ixgbe_init_phy_ops_generic\");\n\n\t/* PHY */\n\tphy->ops.identify = ixgbe_identify_phy_generic;\n\tphy->ops.reset = ixgbe_reset_phy_generic;\n\tphy->ops.read_reg = ixgbe_read_phy_reg_generic;\n\tphy->ops.write_reg = ixgbe_write_phy_reg_generic;\n\tphy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;\n\tphy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;\n\tphy->ops.setup_link = ixgbe_setup_phy_link_generic;\n\tphy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;\n\tphy->ops.check_link = NULL;\n\tphy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;\n\tphy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;\n\tphy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;\n\tphy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;\n\tphy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;\n\tphy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;\n\tphy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;\n\tphy->ops.identify_sfp = ixgbe_identify_module_generic;\n\tphy->sfp_type = ixgbe_sfp_type_unknown;\n\tphy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;\n\tphy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;\n\tphy->ops.read_i2c_combined_unlocked =\n\t\t\t\tixgbe_read_i2c_combined_generic_unlocked;\n\tphy->ops.write_i2c_combined_unlocked =\n\t\t\t\tixgbe_write_i2c_combined_generic_unlocked;\n\tphy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;\n\tphy->ops.write_i2c_byte_unlocked =\n\t\t\t\tixgbe_write_i2c_byte_generic_unlocked;\n\tphy->ops.check_overtemp = ixgbe_tn_check_overtemp;\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_identify_phy_generic - Get physical layer module\n * @hw: pointer to hardware structure\n *\n * Determines the physical layer module found on the current adapter.\n **/\ns32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_PHY_ADDR_INVALID;\n\tu32 phy_addr;\n\tu16 ext_ability = 0;\n\n\tDEBUGFUNC(\"ixgbe_identify_phy_generic\");\n\n\tif (!hw->phy.phy_semaphore_mask) {\n\t\tif (hw->bus.lan_id)\n\t\t\thw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;\n\t\telse\n\t\t\thw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;\n\t}\n\n\tif (hw->phy.type == ixgbe_phy_unknown) {\n\t\tfor (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {\n\t\t\tif (ixgbe_validate_phy_addr(hw, phy_addr)) {\n\t\t\t\thw->phy.addr = phy_addr;\n\t\t\t\tixgbe_get_phy_id(hw);\n\t\t\t\thw->phy.type =\n\t\t\t\t\tixgbe_get_phy_type_from_id(hw->phy.id);\n\n\t\t\t\tif (hw->phy.type == ixgbe_phy_unknown) {\n\t\t\t\t\thw->phy.ops.read_reg(hw,\n\t\t\t\t\t\t IXGBE_MDIO_PHY_EXT_ABILITY,\n\t\t\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t\t\t &ext_ability);\n\t\t\t\t\tif (ext_ability &\n\t\t\t\t\t (IXGBE_MDIO_PHY_10GBASET_ABILITY |\n\t\t\t\t\t IXGBE_MDIO_PHY_1000BASET_ABILITY))\n\t\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\t\t ixgbe_phy_cu_unknown;\n\t\t\t\t\telse\n\t\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\t\t ixgbe_phy_generic;\n\t\t\t\t}\n\n\t\t\t\tstatus = IXGBE_SUCCESS;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/* Certain media types do not have a phy so an address will not\n\t\t * be found and the code will take this path. Caller has to\n\t\t * decide if it is an error or not.\n\t\t */\n\t\tif (status != IXGBE_SUCCESS) {\n\t\t\thw->phy.addr = 0;\n\t\t}\n\t} else {\n\t\tstatus = IXGBE_SUCCESS;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_check_reset_blocked - check status of MNG FW veto bit\n * @hw: pointer to the hardware structure\n *\n * This function checks the MMNGC.MNG_VETO bit to see if there are\n * any constraints on link from manageability. For MAC's that don't\n * have this bit just return faluse since the link can not be blocked\n * via this method.\n **/\ns32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)\n{\n\tu32 mmngc;\n\n\tDEBUGFUNC(\"ixgbe_check_reset_blocked\");\n\n\t/* If we don't have this bit, it can't be blocking */\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\treturn false;\n\n\tmmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);\n\tif (mmngc & IXGBE_MMNGC_MNG_VETO) {\n\t\tERROR_REPORT1(IXGBE_ERROR_SOFTWARE,\n\t\t\t \"MNG_VETO bit detected.\\n\");\n\t\treturn true;\n\t}\n\n\treturn false;\n}\n\n/**\n * ixgbe_validate_phy_addr - Determines phy address is valid\n * @hw: pointer to hardware structure\n *\n **/\nbool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)\n{\n\tu16 phy_id = 0;\n\tbool valid = false;\n\n\tDEBUGFUNC(\"ixgbe_validate_phy_addr\");\n\n\thw->phy.addr = phy_addr;\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,\n\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);\n\n\tif (phy_id != 0xFFFF && phy_id != 0x0)\n\t\tvalid = true;\n\n\treturn valid;\n}\n\n/**\n * ixgbe_get_phy_id - Get the phy type\n * @hw: pointer to hardware structure\n *\n **/\ns32 ixgbe_get_phy_id(struct ixgbe_hw *hw)\n{\n\tu32 status;\n\tu16 phy_id_high = 0;\n\tu16 phy_id_low = 0;\n\n\tDEBUGFUNC(\"ixgbe_get_phy_id\");\n\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,\n\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t &phy_id_high);\n\n\tif (status == IXGBE_SUCCESS) {\n\t\thw->phy.id = (u32)(phy_id_high << 16);\n\t\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,\n\t\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t\t &phy_id_low);\n\t\thw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);\n\t\thw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);\n\t}\n\treturn status;\n}\n\n/**\n * ixgbe_get_phy_type_from_id - Get the phy type\n * @hw: pointer to hardware structure\n *\n **/\nenum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)\n{\n\tenum ixgbe_phy_type phy_type;\n\n\tDEBUGFUNC(\"ixgbe_get_phy_type_from_id\");\n\n\tswitch (phy_id) {\n\tcase TN1010_PHY_ID:\n\t\tphy_type = ixgbe_phy_tn;\n\t\tbreak;\n\tcase X550_PHY_ID1:\n\tcase X550_PHY_ID2:\n\tcase X550_PHY_ID3:\n\tcase X540_PHY_ID:\n\t\tphy_type = ixgbe_phy_aq;\n\t\tbreak;\n\tcase QT2022_PHY_ID:\n\t\tphy_type = ixgbe_phy_qt;\n\t\tbreak;\n\tcase ATH_PHY_ID:\n\t\tphy_type = ixgbe_phy_nl;\n\t\tbreak;\n\tcase X557_PHY_ID:\n\t\tphy_type = ixgbe_phy_x550em_ext_t;\n\t\tbreak;\n\tdefault:\n\t\tphy_type = ixgbe_phy_unknown;\n\t\tbreak;\n\t}\n\n\tDEBUGOUT1(\"phy type found is %d\\n\", phy_type);\n\treturn phy_type;\n}\n\n/**\n * ixgbe_reset_phy_generic - Performs a PHY reset\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)\n{\n\tu32 i;\n\tu16 ctrl = 0;\n\ts32 status = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_reset_phy_generic\");\n\n\tif (hw->phy.type == ixgbe_phy_unknown)\n\t\tstatus = ixgbe_identify_phy_generic(hw);\n\n\tif (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)\n\t\tgoto out;\n\n\t/* Don't reset PHY if it's shut down due to overtemp. */\n\tif (!hw->phy.reset_if_overtemp &&\n\t (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))\n\t\tgoto out;\n\n\t/* Blocked by MNG FW so bail */\n\tif (ixgbe_check_reset_blocked(hw))\n\t\tgoto out;\n\n\t/*\n\t * Perform soft PHY reset to the PHY_XS.\n\t * This will cause a soft reset to the PHY\n\t */\n\thw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,\n\t\t\t IXGBE_MDIO_PHY_XS_DEV_TYPE,\n\t\t\t IXGBE_MDIO_PHY_XS_RESET);\n\n\t/*\n\t * Poll for reset bit to self-clear indicating reset is complete.\n\t * Some PHYs could take up to 3 seconds to complete and need about\n\t * 1.7 usec delay after the reset is complete.\n\t */\n\tfor (i = 0; i < 30; i++) {\n\t\tmsec_delay(100);\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,\n\t\t\t\t IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);\n\t\tif (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {\n\t\t\tusec_delay(2);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (ctrl & IXGBE_MDIO_PHY_XS_RESET) {\n\t\tstatus = IXGBE_ERR_RESET_FAILED;\n\t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n\t\t\t \"PHY reset polling failed to complete.\\n\");\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without\n * the SWFW lock\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit address of PHY register to read\n * @phy_data: Pointer to read data from PHY register\n **/\ns32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n\t\t u16 *phy_data)\n{\n\tu32 i, data, command;\n\n\t/* Setup and write the address cycle command */\n\tcommand = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |\n\t\t (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |\n\t\t (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |\n\t\t (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));\n\n\tIXGBE_WRITE_REG(hw, IXGBE_MSCA, command);\n\n\t/*\n\t * Check every 10 usec to see if the address cycle completed.\n\t * The MDI Command bit will clear when the operation is\n\t * complete\n\t */\n\tfor (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {\n\t\tusec_delay(10);\n\n\t\tcommand = IXGBE_READ_REG(hw, IXGBE_MSCA);\n\t\tif ((command & IXGBE_MSCA_MDI_COMMAND) == 0)\n\t\t\t\tbreak;\n\t}\n\n\n\tif ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {\n\t\tERROR_REPORT1(IXGBE_ERROR_POLLING, \"PHY address command did not complete.\\n\");\n\t\treturn IXGBE_ERR_PHY;\n\t}\n\n\t/*\n\t * Address cycle complete, setup and write the read\n\t * command\n\t */\n\tcommand = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |\n\t\t (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |\n\t\t (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |\n\t\t (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));\n\n\tIXGBE_WRITE_REG(hw, IXGBE_MSCA, command);\n\n\t/*\n\t * Check every 10 usec to see if the address cycle\n\t * completed. The MDI Command bit will clear when the\n\t * operation is complete\n\t */\n\tfor (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {\n\t\tusec_delay(10);\n\n\t\tcommand = IXGBE_READ_REG(hw, IXGBE_MSCA);\n\t\tif ((command & IXGBE_MSCA_MDI_COMMAND) == 0)\n\t\t\tbreak;\n\t}\n\n\tif ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {\n\t\tERROR_REPORT1(IXGBE_ERROR_POLLING, \"PHY read command didn't complete\\n\");\n\t\treturn IXGBE_ERR_PHY;\n\t}\n\n\t/*\n\t * Read operation is complete. Get the data\n\t * from MSRWD\n\t */\n\tdata = IXGBE_READ_REG(hw, IXGBE_MSRWD);\n\tdata >>= IXGBE_MSRWD_READ_DATA_SHIFT;\n\t*phy_data = (u16)(data);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register\n * using the SWFW lock - this function is needed in most cases\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit address of PHY register to read\n * @phy_data: Pointer to read data from PHY register\n **/\ns32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t u32 device_type, u16 *phy_data)\n{\n\ts32 status;\n\tu32 gssr = hw->phy.phy_semaphore_mask;\n\n\tDEBUGFUNC(\"ixgbe_read_phy_reg_generic\");\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {\n\t\tstatus = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,\n\t\t\t\t\t\tphy_data);\n\t\thw->mac.ops.release_swfw_sync(hw, gssr);\n\t} else {\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register\n * without SWFW lock\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit PHY register to write\n * @device_type: 5 bit device type\n * @phy_data: Data to write to the PHY register\n **/\ns32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t\tu32 device_type, u16 phy_data)\n{\n\tu32 i, command;\n\n\t/* Put the data in the MDI single read and write data register*/\n\tIXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);\n\n\t/* Setup and write the address cycle command */\n\tcommand = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |\n\t\t (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |\n\t\t (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |\n\t\t (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));\n\n\tIXGBE_WRITE_REG(hw, IXGBE_MSCA, command);\n\n\t/*\n\t * Check every 10 usec to see if the address cycle completed.\n\t * The MDI Command bit will clear when the operation is\n\t * complete\n\t */\n\tfor (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {\n\t\tusec_delay(10);\n\n\t\tcommand = IXGBE_READ_REG(hw, IXGBE_MSCA);\n\t\tif ((command & IXGBE_MSCA_MDI_COMMAND) == 0)\n\t\t\tbreak;\n\t}\n\n\tif ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {\n\t\tERROR_REPORT1(IXGBE_ERROR_POLLING, \"PHY address cmd didn't complete\\n\");\n\t\treturn IXGBE_ERR_PHY;\n\t}\n\n\t/*\n\t * Address cycle complete, setup and write the write\n\t * command\n\t */\n\tcommand = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |\n\t\t (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |\n\t\t (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |\n\t\t (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));\n\n\tIXGBE_WRITE_REG(hw, IXGBE_MSCA, command);\n\n\t/*\n\t * Check every 10 usec to see if the address cycle\n\t * completed. The MDI Command bit will clear when the\n\t * operation is complete\n\t */\n\tfor (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {\n\t\tusec_delay(10);\n\n\t\tcommand = IXGBE_READ_REG(hw, IXGBE_MSCA);\n\t\tif ((command & IXGBE_MSCA_MDI_COMMAND) == 0)\n\t\t\tbreak;\n\t}\n\n\tif ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {\n\t\tERROR_REPORT1(IXGBE_ERROR_POLLING, \"PHY write cmd didn't complete\\n\");\n\t\treturn IXGBE_ERR_PHY;\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register\n * using SWFW lock- this function is needed in most cases\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit PHY register to write\n * @device_type: 5 bit device type\n * @phy_data: Data to write to the PHY register\n **/\ns32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t\tu32 device_type, u16 phy_data)\n{\n\ts32 status;\n\tu32 gssr = hw->phy.phy_semaphore_mask;\n\n\tDEBUGFUNC(\"ixgbe_write_phy_reg_generic\");\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {\n\t\tstatus = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,\n\t\t\t\t\t\t phy_data);\n\t\thw->mac.ops.release_swfw_sync(hw, gssr);\n\t} else {\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_setup_phy_link_generic - Set and restart auto-neg\n * @hw: pointer to hardware structure\n *\n * Restart auto-negotiation and PHY and waits for completion.\n **/\ns32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu16 autoneg_reg = IXGBE_MII_AUTONEG_REG;\n\tbool autoneg = false;\n\tixgbe_link_speed speed;\n\n\tDEBUGFUNC(\"ixgbe_setup_phy_link_generic\");\n\n\tixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);\n\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL) {\n\t\t/* Set or unset auto-negotiation 10G advertisement */\n\t\thw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;\n\t\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)\n\t\t\tautoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;\n\n\t\thw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t autoneg_reg);\n\t}\n\n\tif (hw->mac.type == ixgbe_mac_X550) {\n\t\tif (speed & IXGBE_LINK_SPEED_5GB_FULL) {\n\t\t\t/* Set or unset auto-negotiation 5G advertisement */\n\t\t\thw->phy.ops.read_reg(hw,\n\t\t\t\tIXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,\n\t\t\t\tIXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t&autoneg_reg);\n\n\t\t\tautoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;\n\t\t\tif (hw->phy.autoneg_advertised &\n\t\t\t IXGBE_LINK_SPEED_5GB_FULL)\n\t\t\t\tautoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;\n\n\t\t\thw->phy.ops.write_reg(hw,\n\t\t\t\tIXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,\n\t\t\t\tIXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\tautoneg_reg);\n\t\t}\n\n\t\tif (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {\n\t\t\t/* Set or unset auto-negotiation 2.5G advertisement */\n\t\t\thw->phy.ops.read_reg(hw,\n\t\t\t\tIXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,\n\t\t\t\tIXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t&autoneg_reg);\n\n\t\t\tautoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;\n\t\t\tif (hw->phy.autoneg_advertised &\n\t\t\t IXGBE_LINK_SPEED_2_5GB_FULL)\n\t\t\t\tautoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;\n\n\t\t\thw->phy.ops.write_reg(hw,\n\t\t\t\tIXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,\n\t\t\t\tIXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\tautoneg_reg);\n\t\t}\n\t}\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL) {\n\t\t/* Set or unset auto-negotiation 1G advertisement */\n\t\thw->phy.ops.read_reg(hw,\n\t\t\t\t IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;\n\t\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)\n\t\t\tautoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;\n\n\t\thw->phy.ops.write_reg(hw,\n\t\t\t\t IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t autoneg_reg);\n\t}\n\n\tif (speed & IXGBE_LINK_SPEED_100_FULL) {\n\t\t/* Set or unset auto-negotiation 100M advertisement */\n\t\thw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |\n\t\t\t\t IXGBE_MII_100BASE_T_ADVERTISE_HALF);\n\t\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)\n\t\t\tautoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;\n\n\t\thw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t autoneg_reg);\n\t}\n\n\t/* Blocked by MNG FW so don't reset PHY */\n\tif (ixgbe_check_reset_blocked(hw))\n\t\treturn status;\n\n\t/* Restart PHY auto-negotiation. */\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);\n\n\tautoneg_reg |= IXGBE_MII_RESTART;\n\n\thw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);\n\n\treturn status;\n}\n\n/**\n * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities\n * @hw: pointer to hardware structure\n * @speed: new link speed\n **/\ns32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg_wait_to_complete)\n{\n\tUNREFERENCED_1PARAMETER(autoneg_wait_to_complete);\n\n\tDEBUGFUNC(\"ixgbe_setup_phy_link_speed_generic\");\n\n\t/*\n\t * Clear autoneg_advertised and set new values based on input link\n\t * speed.\n\t */\n\thw->phy.autoneg_advertised = 0;\n\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_5GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_2_5GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_100_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;\n\n\t/* Setup link based on the new speed settings */\n\thw->phy.ops.setup_link(hw);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @autoneg: boolean auto-negotiation value\n *\n * Determines the supported link capabilities by reading the PHY auto\n * negotiation register.\n **/\ns32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t\t bool *autoneg)\n{\n\ts32 status;\n\tu16 speed_ability;\n\n\tDEBUGFUNC(\"ixgbe_get_copper_link_capabilities_generic\");\n\n\t*speed = 0;\n\t*autoneg = true;\n\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,\n\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t &speed_ability);\n\n\tif (status == IXGBE_SUCCESS) {\n\t\tif (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)\n\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)\n\t\t\t*speed |= IXGBE_LINK_SPEED_1GB_FULL;\n\t\tif (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)\n\t\t\t*speed |= IXGBE_LINK_SPEED_100_FULL;\n\t}\n\n\t/* Internal PHY does not support 100 Mbps */\n\tif (hw->mac.type == ixgbe_mac_X550EM_x)\n\t\t*speed &= ~IXGBE_LINK_SPEED_100_FULL;\n\n\tif (hw->mac.type == ixgbe_mac_X550) {\n\t\t*speed |= IXGBE_LINK_SPEED_2_5GB_FULL;\n\t\t*speed |= IXGBE_LINK_SPEED_5GB_FULL;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_check_phy_link_tnx - Determine link and speed status\n * @hw: pointer to hardware structure\n *\n * Reads the VS1 register to determine if link is up and the current speed for\n * the PHY.\n **/\ns32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t bool *link_up)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu32 time_out;\n\tu32 max_time_out = 10;\n\tu16 phy_link = 0;\n\tu16 phy_speed = 0;\n\tu16 phy_data = 0;\n\n\tDEBUGFUNC(\"ixgbe_check_phy_link_tnx\");\n\n\t/* Initialize speed and link to default case */\n\t*link_up = false;\n\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\n\t/*\n\t * Check current speed and link status of the PHY register.\n\t * This is a vendor specific register and may have to\n\t * be changed for other copper PHYs.\n\t */\n\tfor (time_out = 0; time_out < max_time_out; time_out++) {\n\t\tusec_delay(10);\n\t\tstatus = hw->phy.ops.read_reg(hw,\n\t\t\t\t\tIXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,\n\t\t\t\t\tIXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t\t&phy_data);\n\t\tphy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;\n\t\tphy_speed = phy_data &\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;\n\t\tif (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {\n\t\t\t*link_up = true;\n\t\t\tif (phy_speed ==\n\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)\n\t\t\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn status;\n}\n\n/**\n *\tixgbe_setup_phy_link_tnx - Set and restart auto-neg\n *\t@hw: pointer to hardware structure\n *\n *\tRestart auto-negotiation and PHY and waits for completion.\n **/\ns32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu16 autoneg_reg = IXGBE_MII_AUTONEG_REG;\n\tbool autoneg = false;\n\tixgbe_link_speed speed;\n\n\tDEBUGFUNC(\"ixgbe_setup_phy_link_tnx\");\n\n\tixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);\n\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL) {\n\t\t/* Set or unset auto-negotiation 10G advertisement */\n\t\thw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;\n\t\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)\n\t\t\tautoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;\n\n\t\thw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t autoneg_reg);\n\t}\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL) {\n\t\t/* Set or unset auto-negotiation 1G advertisement */\n\t\thw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;\n\t\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)\n\t\t\tautoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;\n\n\t\thw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t autoneg_reg);\n\t}\n\n\tif (speed & IXGBE_LINK_SPEED_100_FULL) {\n\t\t/* Set or unset auto-negotiation 100M advertisement */\n\t\thw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;\n\t\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)\n\t\t\tautoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;\n\n\t\thw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t autoneg_reg);\n\t}\n\n\t/* Blocked by MNG FW so don't reset PHY */\n\tif (ixgbe_check_reset_blocked(hw))\n\t\treturn status;\n\n\t/* Restart PHY auto-negotiation. */\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);\n\n\tautoneg_reg |= IXGBE_MII_RESTART;\n\n\thw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version\n * @hw: pointer to hardware structure\n * @firmware_version: pointer to the PHY Firmware Version\n **/\ns32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,\n\t\t\t\t u16 *firmware_version)\n{\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_get_phy_firmware_version_tnx\");\n\n\tstatus = hw->phy.ops.read_reg(hw, TNX_FW_REV,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t firmware_version);\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version\n * @hw: pointer to hardware structure\n * @firmware_version: pointer to the PHY Firmware Version\n **/\ns32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *firmware_version)\n{\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_get_phy_firmware_version_generic\");\n\n\tstatus = hw->phy.ops.read_reg(hw, AQ_FW_REV,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t firmware_version);\n\n\treturn status;\n}\n\n/**\n * ixgbe_reset_phy_nl - Performs a PHY reset\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)\n{\n\tu16 phy_offset, control, eword, edata, block_crc;\n\tbool end_data = false;\n\tu16 list_offset, data_offset;\n\tu16 phy_data = 0;\n\ts32 ret_val = IXGBE_SUCCESS;\n\tu32 i;\n\n\tDEBUGFUNC(\"ixgbe_reset_phy_nl\");\n\n\t/* Blocked by MNG FW so bail */\n\tif (ixgbe_check_reset_blocked(hw))\n\t\tgoto out;\n\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,\n\t\t\t IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);\n\n\t/* reset the PHY and poll for completion */\n\thw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,\n\t\t\t IXGBE_MDIO_PHY_XS_DEV_TYPE,\n\t\t\t (phy_data | IXGBE_MDIO_PHY_XS_RESET));\n\n\tfor (i = 0; i < 100; i++) {\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,\n\t\t\t\t IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);\n\t\tif ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)\n\t\t\tbreak;\n\t\tmsec_delay(10);\n\t}\n\n\tif ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {\n\t\tDEBUGOUT(\"PHY reset did not complete.\\n\");\n\t\tret_val = IXGBE_ERR_PHY;\n\t\tgoto out;\n\t}\n\n\t/* Get init offsets */\n\tret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,\n\t\t\t\t\t\t &data_offset);\n\tif (ret_val != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\tret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);\n\tdata_offset++;\n\twhile (!end_data) {\n\t\t/*\n\t\t * Read control word from PHY init contents offset\n\t\t */\n\t\tret_val = hw->eeprom.ops.read(hw, data_offset, &eword);\n\t\tif (ret_val)\n\t\t\tgoto err_eeprom;\n\t\tcontrol = (eword & IXGBE_CONTROL_MASK_NL) >>\n\t\t\t IXGBE_CONTROL_SHIFT_NL;\n\t\tedata = eword & IXGBE_DATA_MASK_NL;\n\t\tswitch (control) {\n\t\tcase IXGBE_DELAY_NL:\n\t\t\tdata_offset++;\n\t\t\tDEBUGOUT1(\"DELAY: %d MS\\n\", edata);\n\t\t\tmsec_delay(edata);\n\t\t\tbreak;\n\t\tcase IXGBE_DATA_NL:\n\t\t\tDEBUGOUT(\"DATA:\\n\");\n\t\t\tdata_offset++;\n\t\t\tret_val = hw->eeprom.ops.read(hw, data_offset,\n\t\t\t\t\t\t &phy_offset);\n\t\t\tif (ret_val)\n\t\t\t\tgoto err_eeprom;\n\t\t\tdata_offset++;\n\t\t\tfor (i = 0; i < edata; i++) {\n\t\t\t\tret_val = hw->eeprom.ops.read(hw, data_offset,\n\t\t\t\t\t\t\t &eword);\n\t\t\t\tif (ret_val)\n\t\t\t\t\tgoto err_eeprom;\n\t\t\t\thw->phy.ops.write_reg(hw, phy_offset,\n\t\t\t\t\t\t IXGBE_TWINAX_DEV, eword);\n\t\t\t\tDEBUGOUT2(\"Wrote %4.4x to %4.4x\\n\", eword,\n\t\t\t\t\t phy_offset);\n\t\t\t\tdata_offset++;\n\t\t\t\tphy_offset++;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase IXGBE_CONTROL_NL:\n\t\t\tdata_offset++;\n\t\t\tDEBUGOUT(\"CONTROL:\\n\");\n\t\t\tif (edata == IXGBE_CONTROL_EOL_NL) {\n\t\t\t\tDEBUGOUT(\"EOL\\n\");\n\t\t\t\tend_data = true;\n\t\t\t} else if (edata == IXGBE_CONTROL_SOL_NL) {\n\t\t\t\tDEBUGOUT(\"SOL\\n\");\n\t\t\t} else {\n\t\t\t\tDEBUGOUT(\"Bad control value\\n\");\n\t\t\t\tret_val = IXGBE_ERR_PHY;\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tDEBUGOUT(\"Bad control type\\n\");\n\t\t\tret_val = IXGBE_ERR_PHY;\n\t\t\tgoto out;\n\t\t}\n\t}\n\nout:\n\treturn ret_val;\n\nerr_eeprom:\n\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t \"eeprom read at offset %d failed\", data_offset);\n\treturn IXGBE_ERR_PHY;\n}\n\n/**\n * ixgbe_identify_module_generic - Identifies module type\n * @hw: pointer to hardware structure\n *\n * Determines HW type and calls appropriate function.\n **/\ns32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_SFP_NOT_PRESENT;\n\n\tDEBUGFUNC(\"ixgbe_identify_module_generic\");\n\n\tswitch (hw->mac.ops.get_media_type(hw)) {\n\tcase ixgbe_media_type_fiber:\n\t\tstatus = ixgbe_identify_sfp_module_generic(hw);\n\t\tbreak;\n\n\tcase ixgbe_media_type_fiber_qsfp:\n\t\tstatus = ixgbe_identify_qsfp_module_generic(hw);\n\t\tbreak;\n\n\tdefault:\n\t\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n\t\tstatus = IXGBE_ERR_SFP_NOT_PRESENT;\n\t\tbreak;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_identify_sfp_module_generic - Identifies SFP modules\n * @hw: pointer to hardware structure\n *\n * Searches for and identifies the SFP module and assigns appropriate PHY type.\n **/\ns32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_PHY_ADDR_INVALID;\n\tu32 vendor_oui = 0;\n\tenum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;\n\tu8 identifier = 0;\n\tu8 comp_codes_1g = 0;\n\tu8 comp_codes_10g = 0;\n\tu8 oui_bytes[3] = {0, 0, 0};\n\tu8 cable_tech = 0;\n\tu8 cable_spec = 0;\n\tu16 enforce_sfp = 0;\n\n\tDEBUGFUNC(\"ixgbe_identify_sfp_module_generic\");\n\n\tif (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {\n\t\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n\t\tstatus = IXGBE_ERR_SFP_NOT_PRESENT;\n\t\tgoto out;\n\t}\n\n\t/* LAN ID is needed for I2C access */\n\thw->mac.ops.set_lan_id(hw);\n\n\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t IXGBE_SFF_IDENTIFIER,\n\t\t\t\t\t &identifier);\n\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto err_read_i2c_eeprom;\n\n\tif (identifier != IXGBE_SFF_IDENTIFIER_SFP) {\n\t\thw->phy.type = ixgbe_phy_sfp_unsupported;\n\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t} else {\n\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t\t IXGBE_SFF_1GBE_COMP_CODES,\n\t\t\t\t\t\t &comp_codes_1g);\n\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto err_read_i2c_eeprom;\n\n\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t\t IXGBE_SFF_10GBE_COMP_CODES,\n\t\t\t\t\t\t &comp_codes_10g);\n\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto err_read_i2c_eeprom;\n\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t\t IXGBE_SFF_CABLE_TECHNOLOGY,\n\t\t\t\t\t\t &cable_tech);\n\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto err_read_i2c_eeprom;\n\n\t\t /* ID Module\n\t\t * =========\n\t\t * 0 SFP_DA_CU\n\t\t * 1 SFP_SR\n\t\t * 2 SFP_LR\n\t\t * 3 SFP_DA_CORE0 - 82599-specific\n\t\t * 4 SFP_DA_CORE1 - 82599-specific\n\t\t * 5 SFP_SR/LR_CORE0 - 82599-specific\n\t\t * 6 SFP_SR/LR_CORE1 - 82599-specific\n\t\t * 7 SFP_act_lmt_DA_CORE0 - 82599-specific\n\t\t * 8 SFP_act_lmt_DA_CORE1 - 82599-specific\n\t\t * 9 SFP_1g_cu_CORE0 - 82599-specific\n\t\t * 10 SFP_1g_cu_CORE1 - 82599-specific\n\t\t * 11 SFP_1g_sx_CORE0 - 82599-specific\n\t\t * 12 SFP_1g_sx_CORE1 - 82599-specific\n\t\t */\n\t\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\t\tif (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)\n\t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_da_cu;\n\t\t\telse if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)\n\t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_sr;\n\t\t\telse if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)\n\t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_lr;\n\t\t\telse\n\t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_unknown;\n\t\t} else {\n\t\t\tif (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {\n\t\t\t\tif (hw->bus.lan_id == 0)\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\t ixgbe_sfp_type_da_cu_core0;\n\t\t\t\telse\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\t ixgbe_sfp_type_da_cu_core1;\n\t\t\t} else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {\n\t\t\t\thw->phy.ops.read_i2c_eeprom(\n\t\t\t\t\t\thw, IXGBE_SFF_CABLE_SPEC_COMP,\n\t\t\t\t\t\t&cable_spec);\n\t\t\t\tif (cable_spec &\n\t\t\t\t IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {\n\t\t\t\t\tif (hw->bus.lan_id == 0)\n\t\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_da_act_lmt_core0;\n\t\t\t\t\telse\n\t\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_da_act_lmt_core1;\n\t\t\t\t} else {\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\t\tixgbe_sfp_type_unknown;\n\t\t\t\t}\n\t\t\t} else if (comp_codes_10g &\n\t\t\t\t (IXGBE_SFF_10GBASESR_CAPABLE |\n\t\t\t\t IXGBE_SFF_10GBASELR_CAPABLE)) {\n\t\t\t\tif (hw->bus.lan_id == 0)\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\t ixgbe_sfp_type_srlr_core0;\n\t\t\t\telse\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\t ixgbe_sfp_type_srlr_core1;\n\t\t\t} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {\n\t\t\t\tif (hw->bus.lan_id == 0)\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_1g_cu_core0;\n\t\t\t\telse\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_1g_cu_core1;\n\t\t\t} else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {\n\t\t\t\tif (hw->bus.lan_id == 0)\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_1g_sx_core0;\n\t\t\t\telse\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_1g_sx_core1;\n\t\t\t} else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {\n\t\t\t\tif (hw->bus.lan_id == 0)\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_1g_lx_core0;\n\t\t\t\telse\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_1g_lx_core1;\n\t\t\t} else {\n\t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_unknown;\n\t\t\t}\n\t\t}\n\n\t\tif (hw->phy.sfp_type != stored_sfp_type)\n\t\t\thw->phy.sfp_setup_needed = true;\n\n\t\t/* Determine if the SFP+ PHY is dual speed or not. */\n\t\thw->phy.multispeed_fiber = false;\n\t\tif (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&\n\t\t (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||\n\t\t ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&\n\t\t (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))\n\t\t\thw->phy.multispeed_fiber = true;\n\n\t\t/* Determine PHY vendor */\n\t\tif (hw->phy.type != ixgbe_phy_nl) {\n\t\t\thw->phy.id = identifier;\n\t\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t\t IXGBE_SFF_VENDOR_OUI_BYTE0,\n\t\t\t\t\t\t &oui_bytes[0]);\n\n\t\t\tif (status != IXGBE_SUCCESS)\n\t\t\t\tgoto err_read_i2c_eeprom;\n\n\t\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t\t IXGBE_SFF_VENDOR_OUI_BYTE1,\n\t\t\t\t\t\t &oui_bytes[1]);\n\n\t\t\tif (status != IXGBE_SUCCESS)\n\t\t\t\tgoto err_read_i2c_eeprom;\n\n\t\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t\t IXGBE_SFF_VENDOR_OUI_BYTE2,\n\t\t\t\t\t\t &oui_bytes[2]);\n\n\t\t\tif (status != IXGBE_SUCCESS)\n\t\t\t\tgoto err_read_i2c_eeprom;\n\n\t\t\tvendor_oui =\n\t\t\t ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |\n\t\t\t (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |\n\t\t\t (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));\n\n\t\t\tswitch (vendor_oui) {\n\t\t\tcase IXGBE_SFF_VENDOR_OUI_TYCO:\n\t\t\t\tif (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)\n\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\t ixgbe_phy_sfp_passive_tyco;\n\t\t\t\tbreak;\n\t\t\tcase IXGBE_SFF_VENDOR_OUI_FTL:\n\t\t\t\tif (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)\n\t\t\t\t\thw->phy.type = ixgbe_phy_sfp_ftl_active;\n\t\t\t\telse\n\t\t\t\t\thw->phy.type = ixgbe_phy_sfp_ftl;\n\t\t\t\tbreak;\n\t\t\tcase IXGBE_SFF_VENDOR_OUI_AVAGO:\n\t\t\t\thw->phy.type = ixgbe_phy_sfp_avago;\n\t\t\t\tbreak;\n\t\t\tcase IXGBE_SFF_VENDOR_OUI_INTEL:\n\t\t\t\thw->phy.type = ixgbe_phy_sfp_intel;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tif (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)\n\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\t ixgbe_phy_sfp_passive_unknown;\n\t\t\t\telse if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)\n\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\tixgbe_phy_sfp_active_unknown;\n\t\t\t\telse\n\t\t\t\t\thw->phy.type = ixgbe_phy_sfp_unknown;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/* Allow any DA cable vendor */\n\t\tif (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |\n\t\t IXGBE_SFF_DA_ACTIVE_CABLE)) {\n\t\t\tstatus = IXGBE_SUCCESS;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/* Verify supported 1G SFP modules */\n\t\tif (comp_codes_10g == 0 &&\n\t\t !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {\n\t\t\thw->phy.type = ixgbe_phy_sfp_unsupported;\n\t\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/* Anything else 82598-based is supported */\n\t\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\t\tstatus = IXGBE_SUCCESS;\n\t\t\tgoto out;\n\t\t}\n\n\t\tixgbe_get_device_caps(hw, &enforce_sfp);\n\t\tif (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&\n\t\t !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {\n\t\t\t/* Make sure we're a supported PHY type */\n\t\t\tif (hw->phy.type == ixgbe_phy_sfp_intel) {\n\t\t\t\tstatus = IXGBE_SUCCESS;\n\t\t\t} else {\n\t\t\t\tif (hw->allow_unsupported_sfp == true) {\n\t\t\t\t\tEWARN(hw, \"WARNING: Intel (R) Network \"\n\t\t\t\t\t \"Connections are quality tested \"\n\t\t\t\t\t \"using Intel (R) Ethernet Optics.\"\n\t\t\t\t\t \" Using untested modules is not \"\n\t\t\t\t\t \"supported and may cause unstable\"\n\t\t\t\t\t \" operation or damage to the \"\n\t\t\t\t\t \"module or the adapter. Intel \"\n\t\t\t\t\t \"Corporation is not responsible \"\n\t\t\t\t\t \"for any harm caused by using \"\n\t\t\t\t\t \"untested modules.\\n\", status);\n\t\t\t\t\tstatus = IXGBE_SUCCESS;\n\t\t\t\t} else {\n\t\t\t\t\tDEBUGOUT(\"SFP+ module not supported\\n\");\n\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\tixgbe_phy_sfp_unsupported;\n\t\t\t\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tstatus = IXGBE_SUCCESS;\n\t\t}\n\t}\n\nout:\n\treturn status;\n\nerr_read_i2c_eeprom:\n\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n\tif (hw->phy.type != ixgbe_phy_nl) {\n\t\thw->phy.id = 0;\n\t\thw->phy.type = ixgbe_phy_unknown;\n\t}\n\treturn IXGBE_ERR_SFP_NOT_PRESENT;\n}\n\n/**\n * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type\n * @hw: pointer to hardware structure\n *\n * Determines physical layer capabilities of the current SFP.\n */\ns32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)\n{\n\tu32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n\tu8 comp_codes_10g = 0;\n\tu8 comp_codes_1g = 0;\n\n\tDEBUGFUNC(\"ixgbe_get_supported_phy_sfp_layer_generic\");\n\n\thw->phy.ops.identify_sfp(hw);\n\tif (hw->phy.sfp_type == ixgbe_sfp_type_not_present)\n\t\treturn physical_layer;\n\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_sfp_passive_tyco:\n\tcase ixgbe_phy_sfp_passive_unknown:\n\tcase ixgbe_phy_qsfp_passive_unknown:\n\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;\n\t\tbreak;\n\tcase ixgbe_phy_sfp_ftl_active:\n\tcase ixgbe_phy_sfp_active_unknown:\n\tcase ixgbe_phy_qsfp_active_unknown:\n\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;\n\t\tbreak;\n\tcase ixgbe_phy_sfp_avago:\n\tcase ixgbe_phy_sfp_ftl:\n\tcase ixgbe_phy_sfp_intel:\n\tcase ixgbe_phy_sfp_unknown:\n\t\thw->phy.ops.read_i2c_eeprom(hw,\n\t\t IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);\n\t\thw->phy.ops.read_i2c_eeprom(hw,\n\t\t IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);\n\t\tif (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;\n\t\telse if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;\n\t\telse if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;\n\t\telse if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;\n\t\tbreak;\n\tcase ixgbe_phy_qsfp_intel:\n\tcase ixgbe_phy_qsfp_unknown:\n\t\thw->phy.ops.read_i2c_eeprom(hw,\n\t\t IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);\n\t\tif (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;\n\t\telse if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn physical_layer;\n}\n\n/**\n * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules\n * @hw: pointer to hardware structure\n *\n * Searches for and identifies the QSFP module and assigns appropriate PHY type\n **/\ns32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_PHY_ADDR_INVALID;\n\tu32 vendor_oui = 0;\n\tenum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;\n\tu8 identifier = 0;\n\tu8 comp_codes_1g = 0;\n\tu8 comp_codes_10g = 0;\n\tu8 oui_bytes[3] = {0, 0, 0};\n\tu16 enforce_sfp = 0;\n\tu8 connector = 0;\n\tu8 cable_length = 0;\n\tu8 device_tech = 0;\n\tbool active_cable = false;\n\n\tDEBUGFUNC(\"ixgbe_identify_qsfp_module_generic\");\n\n\tif (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {\n\t\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n\t\tstatus = IXGBE_ERR_SFP_NOT_PRESENT;\n\t\tgoto out;\n\t}\n\n\t/* LAN ID is needed for I2C access */\n\thw->mac.ops.set_lan_id(hw);\n\n\tstatus = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,\n\t\t\t\t\t &identifier);\n\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto err_read_i2c_eeprom;\n\n\tif (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {\n\t\thw->phy.type = ixgbe_phy_sfp_unsupported;\n\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\tgoto out;\n\t}\n\n\thw->phy.id = identifier;\n\n\tstatus = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,\n\t\t\t\t\t &comp_codes_10g);\n\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto err_read_i2c_eeprom;\n\n\tstatus = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,\n\t\t\t\t\t &comp_codes_1g);\n\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto err_read_i2c_eeprom;\n\n\tif (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {\n\t\thw->phy.type = ixgbe_phy_qsfp_passive_unknown;\n\t\tif (hw->bus.lan_id == 0)\n\t\t\thw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;\n\t\telse\n\t\t\thw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;\n\t} else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |\n\t\t\t\t IXGBE_SFF_10GBASELR_CAPABLE)) {\n\t\tif (hw->bus.lan_id == 0)\n\t\t\thw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;\n\t\telse\n\t\t\thw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;\n\t} else {\n\t\tif (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)\n\t\t\tactive_cable = true;\n\n\t\tif (!active_cable) {\n\t\t\t/* check for active DA cables that pre-date\n\t\t\t * SFF-8436 v3.6 */\n\t\t\thw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\tIXGBE_SFF_QSFP_CONNECTOR,\n\t\t\t\t\t&connector);\n\n\t\t\thw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\tIXGBE_SFF_QSFP_CABLE_LENGTH,\n\t\t\t\t\t&cable_length);\n\n\t\t\thw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\tIXGBE_SFF_QSFP_DEVICE_TECH,\n\t\t\t\t\t&device_tech);\n\n\t\t\tif ((connector ==\n\t\t\t\t IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&\n\t\t\t (cable_length > 0) &&\n\t\t\t ((device_tech >> 4) ==\n\t\t\t\t IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))\n\t\t\t\tactive_cable = true;\n\t\t}\n\n\t\tif (active_cable) {\n\t\t\thw->phy.type = ixgbe_phy_qsfp_active_unknown;\n\t\t\tif (hw->bus.lan_id == 0)\n\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_da_act_lmt_core0;\n\t\t\telse\n\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_da_act_lmt_core1;\n\t\t} else {\n\t\t\t/* unsupported module type */\n\t\t\thw->phy.type = ixgbe_phy_sfp_unsupported;\n\t\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\tif (hw->phy.sfp_type != stored_sfp_type)\n\t\thw->phy.sfp_setup_needed = true;\n\n\t/* Determine if the QSFP+ PHY is dual speed or not. */\n\thw->phy.multispeed_fiber = false;\n\tif (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&\n\t (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||\n\t ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&\n\t (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))\n\t\thw->phy.multispeed_fiber = true;\n\n\t/* Determine PHY vendor for optical modules */\n\tif (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |\n\t\t\t IXGBE_SFF_10GBASELR_CAPABLE)) {\n\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,\n\t\t\t\t\t &oui_bytes[0]);\n\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto err_read_i2c_eeprom;\n\n\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,\n\t\t\t\t\t &oui_bytes[1]);\n\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto err_read_i2c_eeprom;\n\n\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,\n\t\t\t\t\t &oui_bytes[2]);\n\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto err_read_i2c_eeprom;\n\n\t\tvendor_oui =\n\t\t ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |\n\t\t (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |\n\t\t (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));\n\n\t\tif (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)\n\t\t\thw->phy.type = ixgbe_phy_qsfp_intel;\n\t\telse\n\t\t\thw->phy.type = ixgbe_phy_qsfp_unknown;\n\n\t\tixgbe_get_device_caps(hw, &enforce_sfp);\n\t\tif (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {\n\t\t\t/* Make sure we're a supported PHY type */\n\t\t\tif (hw->phy.type == ixgbe_phy_qsfp_intel) {\n\t\t\t\tstatus = IXGBE_SUCCESS;\n\t\t\t} else {\n\t\t\t\tif (hw->allow_unsupported_sfp == true) {\n\t\t\t\t\tEWARN(hw, \"WARNING: Intel (R) Network \"\n\t\t\t\t\t \"Connections are quality tested \"\n\t\t\t\t\t \"using Intel (R) Ethernet Optics.\"\n\t\t\t\t\t \" Using untested modules is not \"\n\t\t\t\t\t \"supported and may cause unstable\"\n\t\t\t\t\t \" operation or damage to the \"\n\t\t\t\t\t \"module or the adapter. Intel \"\n\t\t\t\t\t \"Corporation is not responsible \"\n\t\t\t\t\t \"for any harm caused by using \"\n\t\t\t\t\t \"untested modules.\\n\", status);\n\t\t\t\t\tstatus = IXGBE_SUCCESS;\n\t\t\t\t} else {\n\t\t\t\t\tDEBUGOUT(\"QSFP module not supported\\n\");\n\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\tixgbe_phy_sfp_unsupported;\n\t\t\t\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tstatus = IXGBE_SUCCESS;\n\t\t}\n\t}\n\nout:\n\treturn status;\n\nerr_read_i2c_eeprom:\n\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n\thw->phy.id = 0;\n\thw->phy.type = ixgbe_phy_unknown;\n\n\treturn IXGBE_ERR_SFP_NOT_PRESENT;\n}\n\n\n/**\n * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence\n * @hw: pointer to hardware structure\n * @list_offset: offset to the SFP ID list\n * @data_offset: offset to the SFP data block\n *\n * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if\n * so it returns the offsets to the phy init sequence block.\n **/\ns32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,\n\t\t\t\t\tu16 *list_offset,\n\t\t\t\t\tu16 *data_offset)\n{\n\tu16 sfp_id;\n\tu16 sfp_type = hw->phy.sfp_type;\n\n\tDEBUGFUNC(\"ixgbe_get_sfp_init_sequence_offsets\");\n\n\tif (hw->phy.sfp_type == ixgbe_sfp_type_unknown)\n\t\treturn IXGBE_ERR_SFP_NOT_SUPPORTED;\n\n\tif (hw->phy.sfp_type == ixgbe_sfp_type_not_present)\n\t\treturn IXGBE_ERR_SFP_NOT_PRESENT;\n\n\tif ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&\n\t (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))\n\t\treturn IXGBE_ERR_SFP_NOT_SUPPORTED;\n\n\t/*\n\t * Limiting active cables and 1G Phys must be initialized as\n\t * SR modules\n\t */\n\tif (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||\n\t sfp_type == ixgbe_sfp_type_1g_lx_core0 ||\n\t sfp_type == ixgbe_sfp_type_1g_cu_core0 ||\n\t sfp_type == ixgbe_sfp_type_1g_sx_core0)\n\t\tsfp_type = ixgbe_sfp_type_srlr_core0;\n\telse if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||\n\t\t sfp_type == ixgbe_sfp_type_1g_lx_core1 ||\n\t\t sfp_type == ixgbe_sfp_type_1g_cu_core1 ||\n\t\t sfp_type == ixgbe_sfp_type_1g_sx_core1)\n\t\tsfp_type = ixgbe_sfp_type_srlr_core1;\n\n\t/* Read offset to PHY init contents */\n\tif (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {\n\t\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t\t \"eeprom read at offset %d failed\",\n\t\t\t IXGBE_PHY_INIT_OFFSET_NL);\n\t\treturn IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;\n\t}\n\n\tif ((!*list_offset) || (*list_offset == 0xFFFF))\n\t\treturn IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;\n\n\t/* Shift offset to first ID word */\n\t(*list_offset)++;\n\n\t/*\n\t * Find the matching SFP ID in the EEPROM\n\t * and program the init sequence\n\t */\n\tif (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))\n\t\tgoto err_phy;\n\n\twhile (sfp_id != IXGBE_PHY_INIT_END_NL) {\n\t\tif (sfp_id == sfp_type) {\n\t\t\t(*list_offset)++;\n\t\t\tif (hw->eeprom.ops.read(hw, *list_offset, data_offset))\n\t\t\t\tgoto err_phy;\n\t\t\tif ((!*data_offset) || (*data_offset == 0xFFFF)) {\n\t\t\t\tDEBUGOUT(\"SFP+ module not supported\\n\");\n\t\t\t\treturn IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\t\t} else {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else {\n\t\t\t(*list_offset) += 2;\n\t\t\tif (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))\n\t\t\t\tgoto err_phy;\n\t\t}\n\t}\n\n\tif (sfp_id == IXGBE_PHY_INIT_END_NL) {\n\t\tDEBUGOUT(\"No matching SFP+ module found\\n\");\n\t\treturn IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t}\n\n\treturn IXGBE_SUCCESS;\n\nerr_phy:\n\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t \"eeprom read at offset %d failed\", *list_offset);\n\treturn IXGBE_ERR_PHY;\n}\n\n/**\n * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface\n * @hw: pointer to hardware structure\n * @byte_offset: EEPROM byte offset to read\n * @eeprom_data: value read\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 *eeprom_data)\n{\n\tDEBUGFUNC(\"ixgbe_read_i2c_eeprom_generic\");\n\n\treturn hw->phy.ops.read_i2c_byte(hw, byte_offset,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR,\n\t\t\t\t\t eeprom_data);\n}\n\n/**\n * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset at address 0xA2\n * @eeprom_data: value read\n *\n * Performs byte read operation to SFP module's SFF-8472 data over I2C\n **/\nSTATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\t u8 *sff8472_data)\n{\n\treturn hw->phy.ops.read_i2c_byte(hw, byte_offset,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR2,\n\t\t\t\t\t sff8472_data);\n}\n\n/**\n * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface\n * @hw: pointer to hardware structure\n * @byte_offset: EEPROM byte offset to write\n * @eeprom_data: value to write\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 eeprom_data)\n{\n\tDEBUGFUNC(\"ixgbe_write_i2c_eeprom_generic\");\n\n\treturn hw->phy.ops.write_i2c_byte(hw, byte_offset,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR,\n\t\t\t\t\t eeprom_data);\n}\n\n/**\n * ixgbe_is_sfp_probe - Returns true if SFP is being detected\n * @hw: pointer to hardware structure\n * @offset: eeprom offset to be read\n * @addr: I2C address to be read\n */\nSTATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)\n{\n\tif (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&\n\t offset == IXGBE_SFF_IDENTIFIER &&\n\t hw->phy.sfp_type == ixgbe_sfp_type_not_present)\n\t\treturn true;\n\treturn false;\n}\n\n/**\n * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to read\n * @data: value read\n * @lock: true if to take and release semaphore\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface at\n * a specified device address.\n **/\nSTATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\t u8 dev_addr, u8 *data, bool lock)\n{\n\ts32 status;\n\tu32 max_retry = 10;\n\tu32 retry = 0;\n\tu32 swfw_mask = hw->phy.phy_semaphore_mask;\n\tbool nack = 1;\n\t*data = 0;\n\n\tDEBUGFUNC(\"ixgbe_read_i2c_byte_generic\");\n\n\tif (hw->mac.type >= ixgbe_mac_X550)\n\t\tmax_retry = 3;\n\tif (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))\n\t\tmax_retry = IXGBE_SFP_DETECT_RETRIES;\n\n\tdo {\n\t\tif (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))\n\t\t\treturn IXGBE_ERR_SWFW_SYNC;\n\n\t\tixgbe_i2c_start(hw);\n\n\t\t/* Device Address and write indication */\n\t\tstatus = ixgbe_clock_out_i2c_byte(hw, dev_addr);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_get_i2c_ack(hw);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_clock_out_i2c_byte(hw, byte_offset);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_get_i2c_ack(hw);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tixgbe_i2c_start(hw);\n\n\t\t/* Device Address and read indication */\n\t\tstatus = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_get_i2c_ack(hw);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_clock_in_i2c_byte(hw, data);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_clock_out_i2c_bit(hw, nack);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tixgbe_i2c_stop(hw);\n\t\tif (lock)\n\t\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\t\treturn IXGBE_SUCCESS;\n\nfail:\n\t\tixgbe_i2c_bus_clear(hw);\n\t\tif (lock) {\n\t\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\t\t\tmsec_delay(100);\n\t\t}\n\t\tretry++;\n\t\tif (retry < max_retry)\n\t\t\tDEBUGOUT(\"I2C byte read error - Retrying.\\n\");\n\t\telse\n\t\t\tDEBUGOUT(\"I2C byte read error.\\n\");\n\n\t} while (retry < max_retry);\n\n\treturn status;\n}\n\n/**\n * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to read\n * @data: value read\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface at\n * a specified device address.\n **/\ns32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\tu8 dev_addr, u8 *data)\n{\n\treturn ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,\n\t\t\t\t\t data, true);\n}\n\n/**\n * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to read\n * @data: value read\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface at\n * a specified device address.\n **/\ns32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\t u8 dev_addr, u8 *data)\n{\n\treturn ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,\n\t\t\t\t\t data, false);\n}\n\n/**\n * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @data: value to write\n * @lock: true if to take and release semaphore\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface at\n * a specified device address.\n **/\nSTATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\t u8 dev_addr, u8 data, bool lock)\n{\n\ts32 status;\n\tu32 max_retry = 1;\n\tu32 retry = 0;\n\tu32 swfw_mask = hw->phy.phy_semaphore_mask;\n\n\tDEBUGFUNC(\"ixgbe_write_i2c_byte_generic\");\n\n\tif (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=\n\t IXGBE_SUCCESS)\n\t\treturn IXGBE_ERR_SWFW_SYNC;\n\n\tdo {\n\t\tixgbe_i2c_start(hw);\n\n\t\tstatus = ixgbe_clock_out_i2c_byte(hw, dev_addr);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_get_i2c_ack(hw);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_clock_out_i2c_byte(hw, byte_offset);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_get_i2c_ack(hw);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_clock_out_i2c_byte(hw, data);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_get_i2c_ack(hw);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tixgbe_i2c_stop(hw);\n\t\tif (lock)\n\t\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\t\treturn IXGBE_SUCCESS;\n\nfail:\n\t\tixgbe_i2c_bus_clear(hw);\n\t\tretry++;\n\t\tif (retry < max_retry)\n\t\t\tDEBUGOUT(\"I2C byte write error - Retrying.\\n\");\n\t\telse\n\t\t\tDEBUGOUT(\"I2C byte write error.\\n\");\n\t} while (retry < max_retry);\n\n\tif (lock)\n\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\n\treturn status;\n}\n\n/**\n * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @data: value to write\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface at\n * a specified device address.\n **/\ns32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data)\n{\n\treturn ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,\n\t\t\t\t\t\tdata, true);\n}\n\n/**\n * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @data: value to write\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface at\n * a specified device address.\n **/\ns32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\t u8 dev_addr, u8 data)\n{\n\treturn ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,\n\t\t\t\t\t\tdata, false);\n}\n\n/**\n * ixgbe_i2c_start - Sets I2C start condition\n * @hw: pointer to hardware structure\n *\n * Sets I2C start condition (High -> Low on SDA while SCL is High)\n * Set bit-bang mode on X550 hardware.\n **/\nSTATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)\n{\n\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n\n\tDEBUGFUNC(\"ixgbe_i2c_start\");\n\n\ti2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);\n\n\t/* Start condition must begin with data and clock high */\n\tixgbe_set_i2c_data(hw, &i2cctl, 1);\n\tixgbe_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Setup time for start condition (4.7us) */\n\tusec_delay(IXGBE_I2C_T_SU_STA);\n\n\tixgbe_set_i2c_data(hw, &i2cctl, 0);\n\n\t/* Hold time for start condition (4us) */\n\tusec_delay(IXGBE_I2C_T_HD_STA);\n\n\tixgbe_lower_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum low period of clock is 4.7 us */\n\tusec_delay(IXGBE_I2C_T_LOW);\n\n}\n\n/**\n * ixgbe_i2c_stop - Sets I2C stop condition\n * @hw: pointer to hardware structure\n *\n * Sets I2C stop condition (Low -> High on SDA while SCL is High)\n * Disables bit-bang mode and negates data output enable on X550\n * hardware.\n **/\nSTATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)\n{\n\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n\tu32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);\n\tu32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);\n\tu32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);\n\n\tDEBUGFUNC(\"ixgbe_i2c_stop\");\n\n\t/* Stop condition must begin with data low and clock high */\n\tixgbe_set_i2c_data(hw, &i2cctl, 0);\n\tixgbe_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Setup time for stop condition (4us) */\n\tusec_delay(IXGBE_I2C_T_SU_STO);\n\n\tixgbe_set_i2c_data(hw, &i2cctl, 1);\n\n\t/* bus free time between stop and start (4.7us)*/\n\tusec_delay(IXGBE_I2C_T_BUF);\n\n\tif (bb_en_bit || data_oe_bit || clk_oe_bit) {\n\t\ti2cctl &= ~bb_en_bit;\n\t\ti2cctl |= data_oe_bit | clk_oe_bit;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t}\n}\n\n/**\n * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C\n * @hw: pointer to hardware structure\n * @data: data byte to clock in\n *\n * Clocks in one byte data via I2C data/clock\n **/\nSTATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)\n{\n\ts32 i;\n\tbool bit = 0;\n\n\tDEBUGFUNC(\"ixgbe_clock_in_i2c_byte\");\n\n\t*data = 0;\n\tfor (i = 7; i >= 0; i--) {\n\t\tixgbe_clock_in_i2c_bit(hw, &bit);\n\t\t*data |= bit << i;\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C\n * @hw: pointer to hardware structure\n * @data: data byte clocked out\n *\n * Clocks out one byte data via I2C data/clock\n **/\nSTATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)\n{\n\ts32 status = IXGBE_SUCCESS;\n\ts32 i;\n\tu32 i2cctl;\n\tbool bit;\n\n\tDEBUGFUNC(\"ixgbe_clock_out_i2c_byte\");\n\n\tfor (i = 7; i >= 0; i--) {\n\t\tbit = (data >> i) & 0x1;\n\t\tstatus = ixgbe_clock_out_i2c_bit(hw, bit);\n\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\tbreak;\n\t}\n\n\t/* Release SDA line (set high) */\n\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n\ti2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);\n\ti2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);\n\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_i2c_ack - Polls for I2C ACK\n * @hw: pointer to hardware structure\n *\n * Clocks in/out one bit via I2C data/clock\n **/\nSTATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)\n{\n\tu32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);\n\ts32 status = IXGBE_SUCCESS;\n\tu32 i = 0;\n\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n\tu32 timeout = 10;\n\tbool ack = 1;\n\n\tDEBUGFUNC(\"ixgbe_get_i2c_ack\");\n\n\tif (data_oe_bit) {\n\t\ti2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);\n\t\ti2cctl |= data_oe_bit;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t}\n\tixgbe_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum high period of clock is 4us */\n\tusec_delay(IXGBE_I2C_T_HIGH);\n\n\t/* Poll for ACK. Note that ACK in I2C spec is\n\t * transition from 1 to 0 */\n\tfor (i = 0; i < timeout; i++) {\n\t\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n\t\tack = ixgbe_get_i2c_data(hw, &i2cctl);\n\n\t\tusec_delay(1);\n\t\tif (!ack)\n\t\t\tbreak;\n\t}\n\n\tif (ack) {\n\t\tDEBUGOUT(\"I2C ack was not received.\\n\");\n\t\tstatus = IXGBE_ERR_I2C;\n\t}\n\n\tixgbe_lower_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum low period of clock is 4.7 us */\n\tusec_delay(IXGBE_I2C_T_LOW);\n\n\treturn status;\n}\n\n/**\n * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock\n * @hw: pointer to hardware structure\n * @data: read data value\n *\n * Clocks in one bit via I2C data/clock\n **/\nSTATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)\n{\n\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n\tu32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);\n\n\tDEBUGFUNC(\"ixgbe_clock_in_i2c_bit\");\n\n\tif (data_oe_bit) {\n\t\ti2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);\n\t\ti2cctl |= data_oe_bit;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t}\n\tixgbe_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum high period of clock is 4us */\n\tusec_delay(IXGBE_I2C_T_HIGH);\n\n\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n\t*data = ixgbe_get_i2c_data(hw, &i2cctl);\n\n\tixgbe_lower_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum low period of clock is 4.7 us */\n\tusec_delay(IXGBE_I2C_T_LOW);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock\n * @hw: pointer to hardware structure\n * @data: data value to write\n *\n * Clocks out one bit via I2C data/clock\n **/\nSTATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)\n{\n\ts32 status;\n\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n\n\tDEBUGFUNC(\"ixgbe_clock_out_i2c_bit\");\n\n\tstatus = ixgbe_set_i2c_data(hw, &i2cctl, data);\n\tif (status == IXGBE_SUCCESS) {\n\t\tixgbe_raise_i2c_clk(hw, &i2cctl);\n\n\t\t/* Minimum high period of clock is 4us */\n\t\tusec_delay(IXGBE_I2C_T_HIGH);\n\n\t\tixgbe_lower_i2c_clk(hw, &i2cctl);\n\n\t\t/* Minimum low period of clock is 4.7 us.\n\t\t * This also takes care of the data hold time.\n\t\t */\n\t\tusec_delay(IXGBE_I2C_T_LOW);\n\t} else {\n\t\tstatus = IXGBE_ERR_I2C;\n\t\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t\t \"I2C data was not set to %X\\n\", data);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_raise_i2c_clk - Raises the I2C SCL clock\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Raises the I2C clock line '0'->'1'\n * Negates the I2C clock output enable on X550 hardware.\n **/\nSTATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)\n{\n\tu32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);\n\tu32 i = 0;\n\tu32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;\n\tu32 i2cctl_r = 0;\n\n\tDEBUGFUNC(\"ixgbe_raise_i2c_clk\");\n\n\tif (clk_oe_bit) {\n\t\t*i2cctl |= clk_oe_bit;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);\n\t}\n\n\tfor (i = 0; i < timeout; i++) {\n\t\t*i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t\t/* SCL rise time (1000ns) */\n\t\tusec_delay(IXGBE_I2C_T_RISE);\n\n\t\ti2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n\t\tif (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))\n\t\t\tbreak;\n\t}\n}\n\n/**\n * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Lowers the I2C clock line '1'->'0'\n * Asserts the I2C clock output enable on X550 hardware.\n **/\nSTATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)\n{\n\tDEBUGFUNC(\"ixgbe_lower_i2c_clk\");\n\n\t*i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));\n\t*i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* SCL fall time (300ns) */\n\tusec_delay(IXGBE_I2C_T_FALL);\n}\n\n/**\n * ixgbe_set_i2c_data - Sets the I2C data bit\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n * @data: I2C data value (0 or 1) to set\n *\n * Sets the I2C data bit\n * Asserts the I2C data output enable on X550 hardware.\n **/\nSTATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)\n{\n\tu32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);\n\ts32 status = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_set_i2c_data\");\n\n\tif (data)\n\t\t*i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);\n\telse\n\t\t*i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));\n\t*i2cctl &= ~data_oe_bit;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */\n\tusec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);\n\n\tif (!data)\t/* Can't verify data in this case */\n\t\treturn IXGBE_SUCCESS;\n\tif (data_oe_bit) {\n\t\t*i2cctl |= data_oe_bit;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t}\n\n\t/* Verify data was set correctly */\n\t*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n\tif (data != ixgbe_get_i2c_data(hw, i2cctl)) {\n\t\tstatus = IXGBE_ERR_I2C;\n\t\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n\t\t\t \"Error - I2C data was not set to %X.\\n\",\n\t\t\t data);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_i2c_data - Reads the I2C SDA data bit\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Returns the I2C data bit value\n * Negates the I2C data output enable on X550 hardware.\n **/\nSTATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)\n{\n\tu32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);\n\tbool data;\n\n\tDEBUGFUNC(\"ixgbe_get_i2c_data\");\n\n\tif (data_oe_bit) {\n\t\t*i2cctl |= data_oe_bit;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t\tusec_delay(IXGBE_I2C_T_FALL);\n\t}\n\n\tif (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))\n\t\tdata = 1;\n\telse\n\t\tdata = 0;\n\n\treturn data;\n}\n\n/**\n * ixgbe_i2c_bus_clear - Clears the I2C bus\n * @hw: pointer to hardware structure\n *\n * Clears the I2C bus by sending nine clock pulses.\n * Used when data line is stuck low.\n **/\nvoid ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)\n{\n\tu32 i2cctl;\n\tu32 i;\n\n\tDEBUGFUNC(\"ixgbe_i2c_bus_clear\");\n\n\tixgbe_i2c_start(hw);\n\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n\n\tixgbe_set_i2c_data(hw, &i2cctl, 1);\n\n\tfor (i = 0; i < 9; i++) {\n\t\tixgbe_raise_i2c_clk(hw, &i2cctl);\n\n\t\t/* Min high period of clock is 4us */\n\t\tusec_delay(IXGBE_I2C_T_HIGH);\n\n\t\tixgbe_lower_i2c_clk(hw, &i2cctl);\n\n\t\t/* Min low period of clock is 4.7us*/\n\t\tusec_delay(IXGBE_I2C_T_LOW);\n\t}\n\n\tixgbe_i2c_start(hw);\n\n\t/* Put the i2c bus back to default state */\n\tixgbe_i2c_stop(hw);\n}\n\n/**\n * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.\n * @hw: pointer to hardware structure\n *\n * Checks if the LASI temp alarm status was triggered due to overtemp\n **/\ns32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu16 phy_data = 0;\n\n\tDEBUGFUNC(\"ixgbe_tn_check_overtemp\");\n\n\tif (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)\n\t\tgoto out;\n\n\t/* Check that the LASI temp alarm status was triggered */\n\thw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,\n\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);\n\n\tif (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))\n\t\tgoto out;\n\n\tstatus = IXGBE_ERR_OVERTEMP;\n\tERROR_REPORT1(IXGBE_ERROR_CAUTION, \"Device over temperature\");\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_set_copper_phy_power - Control power for copper phy\n * @hw: pointer to hardware structure\n * @on: true for on, false for off\n */\ns32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)\n{\n\tu32 status;\n\tu16 reg;\n\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t ®);\n\tif (status)\n\t\treturn status;\n\n\tif (on) {\n\t\treg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;\n\t} else {\n\t\tif (ixgbe_check_reset_blocked(hw))\n\t\t\treturn 0;\n\t\treg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;\n\t}\n\n\tstatus = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t reg);\n\treturn status;\n}\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_phy.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _IXGBE_PHY_H_\n#define _IXGBE_PHY_H_\n\n#include \"ixgbe_type.h\"\n#define IXGBE_I2C_EEPROM_DEV_ADDR\t0xA0\n#define IXGBE_I2C_EEPROM_DEV_ADDR2\t0xA2\n#define IXGBE_I2C_EEPROM_BANK_LEN\t0xFF\n\n/* EEPROM byte offsets */\n#define IXGBE_SFF_IDENTIFIER\t\t0x0\n#define IXGBE_SFF_IDENTIFIER_SFP\t0x3\n#define IXGBE_SFF_VENDOR_OUI_BYTE0\t0x25\n#define IXGBE_SFF_VENDOR_OUI_BYTE1\t0x26\n#define IXGBE_SFF_VENDOR_OUI_BYTE2\t0x27\n#define IXGBE_SFF_1GBE_COMP_CODES\t0x6\n#define IXGBE_SFF_10GBE_COMP_CODES\t0x3\n#define IXGBE_SFF_CABLE_TECHNOLOGY\t0x8\n#define IXGBE_SFF_CABLE_SPEC_COMP\t0x3C\n#define IXGBE_SFF_SFF_8472_SWAP\t\t0x5C\n#define IXGBE_SFF_SFF_8472_COMP\t\t0x5E\n#define IXGBE_SFF_SFF_8472_OSCB\t\t0x6E\n#define IXGBE_SFF_SFF_8472_ESCB\t\t0x76\n#define IXGBE_SFF_IDENTIFIER_QSFP_PLUS\t0xD\n#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0\t0xA5\n#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1\t0xA6\n#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2\t0xA7\n#define IXGBE_SFF_QSFP_CONNECTOR\t0x82\n#define IXGBE_SFF_QSFP_10GBE_COMP\t0x83\n#define IXGBE_SFF_QSFP_1GBE_COMP\t0x86\n#define IXGBE_SFF_QSFP_CABLE_LENGTH\t0x92\n#define IXGBE_SFF_QSFP_DEVICE_TECH\t0x93\n\n/* Bitmasks */\n#define IXGBE_SFF_DA_PASSIVE_CABLE\t0x4\n#define IXGBE_SFF_DA_ACTIVE_CABLE\t0x8\n#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING\t0x4\n#define IXGBE_SFF_1GBASESX_CAPABLE\t0x1\n#define IXGBE_SFF_1GBASELX_CAPABLE\t0x2\n#define IXGBE_SFF_1GBASET_CAPABLE\t0x8\n#define IXGBE_SFF_10GBASESR_CAPABLE\t0x10\n#define IXGBE_SFF_10GBASELR_CAPABLE\t0x20\n#define IXGBE_SFF_SOFT_RS_SELECT_MASK\t0x8\n#define IXGBE_SFF_SOFT_RS_SELECT_10G\t0x8\n#define IXGBE_SFF_SOFT_RS_SELECT_1G\t0x0\n#define IXGBE_SFF_ADDRESSING_MODE\t0x4\n#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE\t0x1\n#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE\t0x8\n#define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE\t0x23\n#define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL\t0x0\n#define IXGBE_I2C_EEPROM_READ_MASK\t0x100\n#define IXGBE_I2C_EEPROM_STATUS_MASK\t0x3\n#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION\t0x0\n#define IXGBE_I2C_EEPROM_STATUS_PASS\t0x1\n#define IXGBE_I2C_EEPROM_STATUS_FAIL\t0x2\n#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS\t0x3\n\n#define IXGBE_CS4227\t\t\t0xBE\t/* CS4227 address */\n#define IXGBE_CS4227_GLOBAL_ID_LSB\t0\n#define IXGBE_CS4227_SCRATCH\t\t2\n#define IXGBE_CS4227_GLOBAL_ID_VALUE\t0x03E5\n#define IXGBE_CS4227_SCRATCH_VALUE\t0x5aa5\n#define IXGBE_CS4227_RETRIES\t\t5\n#define IXGBE_CS4227_LINE_SPARE22_MSB\t0x12AD\t/* Reg to program speed */\n#define IXGBE_CS4227_LINE_SPARE24_LSB\t0x12B0\t/* Reg to program EDC */\n#define IXGBE_CS4227_HOST_SPARE22_MSB\t0x1AAD\t/* Reg to program speed */\n#define IXGBE_CS4227_HOST_SPARE24_LSB\t0x1AB0\t/* Reg to program EDC */\n#define IXGBE_CS4227_SPEED_1G\t\t0x8000\n#define IXGBE_CS4227_SPEED_10G\t\t0\n#define IXGBE_CS4227_EDC_MODE_CX1\t0x0002\n#define IXGBE_CS4227_EDC_MODE_SR\t0x0004\n#define IXGBE_CS4227_RESET_HOLD\t\t500\t/* microseconds */\n#define IXGBE_CS4227_RESET_DELAY\t500\t/* milliseconds */\n#define IXGBE_CS4227_CHECK_DELAY\t30\t/* milliseconds */\n#define IXGBE_PE\t\t\t0xE0\t/* Port expander address */\n#define IXGBE_PE_OUTPUT\t\t\t1\t/* Output register offset */\n#define IXGBE_PE_CONFIG\t\t\t3\t/* Config register offset */\n#define IXGBE_PE_BIT1\t\t\t(1 << 1)\n\n/* Flow control defines */\n#define IXGBE_TAF_SYM_PAUSE\t\t0x400\n#define IXGBE_TAF_ASM_PAUSE\t\t0x800\n\n/* Bit-shift macros */\n#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT\t24\n#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT\t16\n#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT\t8\n\n/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */\n#define IXGBE_SFF_VENDOR_OUI_TYCO\t0x00407600\n#define IXGBE_SFF_VENDOR_OUI_FTL\t0x00906500\n#define IXGBE_SFF_VENDOR_OUI_AVAGO\t0x00176A00\n#define IXGBE_SFF_VENDOR_OUI_INTEL\t0x001B2100\n\n/* I2C SDA and SCL timing parameters for standard mode */\n#define IXGBE_I2C_T_HD_STA\t4\n#define IXGBE_I2C_T_LOW\t\t5\n#define IXGBE_I2C_T_HIGH\t4\n#define IXGBE_I2C_T_SU_STA\t5\n#define IXGBE_I2C_T_HD_DATA\t5\n#define IXGBE_I2C_T_SU_DATA\t1\n#define IXGBE_I2C_T_RISE\t1\n#define IXGBE_I2C_T_FALL\t1\n#define IXGBE_I2C_T_SU_STO\t4\n#define IXGBE_I2C_T_BUF\t\t5\n\n#ifndef IXGBE_SFP_DETECT_RETRIES\n#define IXGBE_SFP_DETECT_RETRIES\t10\n\n#endif /* IXGBE_SFP_DETECT_RETRIES */\n#define IXGBE_TN_LASI_STATUS_REG\t0x9005\n#define IXGBE_TN_LASI_STATUS_TEMP_ALARM\t0x0008\n\n/* SFP+ SFF-8472 Compliance */\n#define IXGBE_SFF_SFF_8472_UNSUP\t0x00\n\n#ident \"$Id: ixgbe_phy.h,v 1.56 2013/09/05 23:59:49 jtkirshe Exp $\"\n\ns32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);\nbool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);\nenum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);\ns32 ixgbe_get_phy_id(struct ixgbe_hw *hw);\ns32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);\ns32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);\ns32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n\t\t\t u16 *phy_data);\ns32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n\t\t\t u16 phy_data);\ns32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t u32 device_type, u16 *phy_data);\ns32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t\tu32 device_type, u16 phy_data);\ns32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);\ns32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t\t bool *autoneg);\ns32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw);\n\n/* PHY specific */\ns32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,\n\t\t\t ixgbe_link_speed *speed,\n\t\t\t bool *link_up);\ns32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);\ns32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,\n\t\t\t\t u16 *firmware_version);\ns32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *firmware_version);\n\ns32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);\ns32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);\ns32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);\ns32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);\ns32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw);\ns32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);\ns32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,\n\t\t\t\t\tu16 *list_offset,\n\t\t\t\t\tu16 *data_offset);\ns32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);\ns32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\tu8 dev_addr, u8 *data);\ns32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\t u8 dev_addr, u8 *data);\ns32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data);\ns32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\t u8 dev_addr, u8 data);\ns32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 *eeprom_data);\ns32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 eeprom_data);\nvoid ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);\n#endif /* _IXGBE_PHY_H_ */\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_type.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _IXGBE_TYPE_H_\n#define _IXGBE_TYPE_H_\n\n/*\n * The following is a brief description of the error categories used by the\n * ERROR_REPORT* macros.\n *\n * - IXGBE_ERROR_INVALID_STATE\n * This category is for errors which represent a serious failure state that is\n * unexpected, and could be potentially harmful to device operation. It should\n * not be used for errors relating to issues that can be worked around or\n * ignored.\n *\n * - IXGBE_ERROR_POLLING\n * This category is for errors related to polling/timeout issues and should be\n * used in any case where the timeout occured, or a failure to obtain a lock, or\n * failure to receive data within the time limit.\n *\n * - IXGBE_ERROR_CAUTION\n * This category should be used for reporting issues that may be the cause of\n * other errors, such as temperature warnings. It should indicate an event which\n * could be serious, but hasn't necessarily caused problems yet.\n *\n * - IXGBE_ERROR_SOFTWARE\n * This category is intended for errors due to software state preventing\n * something. The category is not intended for errors due to bad arguments, or\n * due to unsupported features. It should be used when a state occurs which\n * prevents action but is not a serious issue.\n *\n * - IXGBE_ERROR_ARGUMENT\n * This category is for when a bad or invalid argument is passed. It should be\n * used whenever a function is called and error checking has detected the\n * argument is wrong or incorrect.\n *\n * - IXGBE_ERROR_UNSUPPORTED\n * This category is for errors which are due to unsupported circumstances or\n * configuration issues. It should not be used when the issue is due to an\n * invalid argument, but for when something has occurred that is unsupported\n * (Ex: Flow control autonegotiation or an unsupported SFP+ module.)\n */\n\n#include \"ixgbe_osdep.h\"\n\n/* Override this by setting IOMEM in your ixgbe_osdep.h header */\n\n/* Vendor ID */\n#define IXGBE_INTEL_VENDOR_ID\t\t\t0x8086\n\n/* Device IDs */\n#define IXGBE_DEV_ID_82598\t\t\t0x10B6\n#define IXGBE_DEV_ID_82598_BX\t\t\t0x1508\n#define IXGBE_DEV_ID_82598AF_DUAL_PORT\t\t0x10C6\n#define IXGBE_DEV_ID_82598AF_SINGLE_PORT\t0x10C7\n#define IXGBE_DEV_ID_82598AT\t\t\t0x10C8\n#define IXGBE_DEV_ID_82598AT2\t\t\t0x150B\n#define IXGBE_DEV_ID_82598EB_SFP_LOM\t\t0x10DB\n#define IXGBE_DEV_ID_82598EB_CX4\t\t0x10DD\n#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT\t0x10EC\n#define IXGBE_DEV_ID_82598_DA_DUAL_PORT\t\t0x10F1\n#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM\t0x10E1\n#define IXGBE_DEV_ID_82598EB_XF_LR\t\t0x10F4\n#define IXGBE_DEV_ID_82599_KX4\t\t\t0x10F7\n#define IXGBE_DEV_ID_82599_KX4_MEZZ\t\t0x1514\n#define IXGBE_DEV_ID_82599_KR\t\t\t0x1517\n#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE\t0x10F8\n#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ\t0x000C\n#define IXGBE_DEV_ID_82599_CX4\t\t\t0x10F9\n#define IXGBE_DEV_ID_82599_SFP\t\t\t0x10FB\n#define IXGBE_SUBDEV_ID_82599_SFP\t\t0x11A9\n#define IXGBE_SUBDEV_ID_82599_SFP_WOL0\t\t0x1071\n#define IXGBE_SUBDEV_ID_82599_RNDC\t\t0x1F72\n#define IXGBE_SUBDEV_ID_82599_560FLR\t\t0x17D0\n#define IXGBE_SUBDEV_ID_82599_ECNA_DP\t\t0x0470\n#define IXGBE_SUBDEV_ID_82599_SP_560FLR\t\t0x211B\n#define IXGBE_SUBDEV_ID_82599_LOM_SFP\t\t0x8976\n#define IXGBE_SUBDEV_ID_82599_LOM_SNAP6\t\t0x2159\n#define IXGBE_SUBDEV_ID_82599_SFP_1OCP\t\t0x000D\n#define IXGBE_SUBDEV_ID_82599_SFP_2OCP\t\t0x0008\n#define IXGBE_SUBDEV_ID_82599_SFP_LOM\t\t0x06EE\n#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE\t0x152A\n#define IXGBE_DEV_ID_82599_SFP_FCOE\t\t0x1529\n#define IXGBE_DEV_ID_82599_SFP_EM\t\t0x1507\n#define IXGBE_DEV_ID_82599_SFP_SF2\t\t0x154D\n#define IXGBE_DEV_ID_82599_SFP_SF_QP\t\t0x154A\n#define IXGBE_DEV_ID_82599_QSFP_SF_QP\t\t0x1558\n#define IXGBE_DEV_ID_82599EN_SFP\t\t0x1557\n#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1\t0x0001\n#define IXGBE_DEV_ID_82599_XAUI_LOM\t\t0x10FC\n#define IXGBE_DEV_ID_82599_T3_LOM\t\t0x151C\n#define IXGBE_DEV_ID_82599_VF\t\t\t0x10ED\n#define IXGBE_DEV_ID_82599_VF_HV\t\t0x152E\n#define IXGBE_DEV_ID_82599_LS\t\t\t0x154F\n#define IXGBE_DEV_ID_X540T\t\t\t0x1528\n#define IXGBE_DEV_ID_X540_VF\t\t\t0x1515\n#define IXGBE_DEV_ID_X540_VF_HV\t\t\t0x1530\n#define IXGBE_DEV_ID_X540T1\t\t\t0x1560\n#define IXGBE_DEV_ID_X550T\t\t\t0x1563\n#define IXGBE_DEV_ID_X550EM_X_KX4\t\t0x15AA\n#define IXGBE_DEV_ID_X550EM_X_KR\t\t0x15AB\n#define IXGBE_DEV_ID_X550EM_X_SFP\t\t0x15AC\n#define IXGBE_DEV_ID_X550EM_X_10G_T\t\t0x15AD\n#define IXGBE_DEV_ID_X550EM_X_1G_T\t\t0x15AE\n#define IXGBE_DEV_ID_X550_VF_HV\t\t\t0x1564\n#define IXGBE_DEV_ID_X550_VF\t\t\t0x1565\n#define IXGBE_DEV_ID_X550EM_X_VF\t\t0x15A8\n#define IXGBE_DEV_ID_X550EM_X_VF_HV\t\t0x15A9\n\n#define IXGBE_CAT(r, m) IXGBE_##r##m\n\n#define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)])\n\n/* General Registers */\n#define IXGBE_CTRL\t\t0x00000\n#define IXGBE_STATUS\t\t0x00008\n#define IXGBE_CTRL_EXT\t\t0x00018\n#define IXGBE_ESDP\t\t0x00020\n#define IXGBE_EODSDP\t\t0x00028\n#define IXGBE_I2CCTL_82599\t0x00028\n#define IXGBE_I2CCTL\t\tIXGBE_I2CCTL_82599\n#define IXGBE_I2CCTL_X540\tIXGBE_I2CCTL_82599\n#define IXGBE_I2CCTL_X550\t0x15F5C\n#define IXGBE_I2CCTL_X550EM_x\tIXGBE_I2CCTL_X550\n#define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL)\n#define IXGBE_PHY_GPIO\t\t0x00028\n#define IXGBE_MAC_GPIO\t\t0x00030\n#define IXGBE_PHYINT_STATUS0\t0x00100\n#define IXGBE_PHYINT_STATUS1\t0x00104\n#define IXGBE_PHYINT_STATUS2\t0x00108\n#define IXGBE_LEDCTL\t\t0x00200\n#define IXGBE_FRTIMER\t\t0x00048\n#define IXGBE_TCPTIMER\t\t0x0004C\n#define IXGBE_CORESPARE\t\t0x00600\n#define IXGBE_EXVET\t\t0x05078\n\n/* NVM Registers */\n#define IXGBE_EEC\t\t0x10010\n#define IXGBE_EEC_X540\t\tIXGBE_EEC\n#define IXGBE_EEC_X550\t\tIXGBE_EEC\n#define IXGBE_EEC_X550EM_x\tIXGBE_EEC\n#define IXGBE_EEC_BY_MAC(_hw)\tIXGBE_EEC\n\n#define IXGBE_EERD\t\t0x10014\n#define IXGBE_EEWR\t\t0x10018\n\n#define IXGBE_FLA\t\t0x1001C\n#define IXGBE_FLA_X540\t\tIXGBE_FLA\n#define IXGBE_FLA_X550\t\tIXGBE_FLA\n#define IXGBE_FLA_X550EM_x\tIXGBE_FLA\n#define IXGBE_FLA_BY_MAC(_hw)\tIXGBE_FLA\n\n#define IXGBE_EEMNGCTL\t0x10110\n#define IXGBE_EEMNGDATA\t0x10114\n#define IXGBE_FLMNGCTL\t0x10118\n#define IXGBE_FLMNGDATA\t0x1011C\n#define IXGBE_FLMNGCNT\t0x10120\n#define IXGBE_FLOP\t0x1013C\n\n#define IXGBE_GRC\t\t0x10200\n#define IXGBE_GRC_X540\t\tIXGBE_GRC\n#define IXGBE_GRC_X550\t\tIXGBE_GRC\n#define IXGBE_GRC_X550EM_x\tIXGBE_GRC\n#define IXGBE_GRC_BY_MAC(_hw)\tIXGBE_GRC\n\n#define IXGBE_SRAMREL\t\t0x10210\n#define IXGBE_SRAMREL_X540\tIXGBE_SRAMREL\n#define IXGBE_SRAMREL_X550\tIXGBE_SRAMREL\n#define IXGBE_SRAMREL_X550EM_x\tIXGBE_SRAMREL\n#define IXGBE_SRAMREL_BY_MAC(_hw)\tIXGBE_SRAMREL\n\n#define IXGBE_PHYDBG\t0x10218\n\n/* General Receive Control */\n#define IXGBE_GRC_MNG\t0x00000001 /* Manageability Enable */\n#define IXGBE_GRC_APME\t0x00000002 /* APM enabled in EEPROM */\n\n#define IXGBE_VPDDIAG0\t0x10204\n#define IXGBE_VPDDIAG1\t0x10208\n\n/* I2CCTL Bit Masks */\n#define IXGBE_I2C_CLK_IN\t\t0x00000001\n#define IXGBE_I2C_CLK_IN_X540\t\tIXGBE_I2C_CLK_IN\n#define IXGBE_I2C_CLK_IN_X550\t\t0x00004000\n#define IXGBE_I2C_CLK_IN_X550EM_x\tIXGBE_I2C_CLK_IN_X550\n#define IXGBE_I2C_CLK_IN_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), I2C_CLK_IN)\n\n#define IXGBE_I2C_CLK_OUT\t\t0x00000002\n#define IXGBE_I2C_CLK_OUT_X540\t\tIXGBE_I2C_CLK_OUT\n#define IXGBE_I2C_CLK_OUT_X550\t\t0x00000200\n#define IXGBE_I2C_CLK_OUT_X550EM_x\tIXGBE_I2C_CLK_OUT_X550\n#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), I2C_CLK_OUT)\n\n#define IXGBE_I2C_DATA_IN\t\t0x00000004\n#define IXGBE_I2C_DATA_IN_X540\t\tIXGBE_I2C_DATA_IN\n#define IXGBE_I2C_DATA_IN_X550\t\t0x00001000\n#define IXGBE_I2C_DATA_IN_X550EM_x\tIXGBE_I2C_DATA_IN_X550\n#define IXGBE_I2C_DATA_IN_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), I2C_DATA_IN)\n\n#define IXGBE_I2C_DATA_OUT\t\t0x00000008\n#define IXGBE_I2C_DATA_OUT_X540\t\tIXGBE_I2C_DATA_OUT\n#define IXGBE_I2C_DATA_OUT_X550\t\t0x00000400\n#define IXGBE_I2C_DATA_OUT_X550EM_x\tIXGBE_I2C_DATA_OUT_X550\n#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), I2C_DATA_OUT)\n\n#define IXGBE_I2C_DATA_OE_N_EN\t\t0\n#define IXGBE_I2C_DATA_OE_N_EN_X540\tIXGBE_I2C_DATA_OE_N_EN\n#define IXGBE_I2C_DATA_OE_N_EN_X550\t0x00000800\n#define IXGBE_I2C_DATA_OE_N_EN_X550EM_x\tIXGBE_I2C_DATA_OE_N_EN_X550\n#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)\n\n#define IXGBE_I2C_BB_EN\t\t\t0\n#define IXGBE_I2C_BB_EN_X540\t\tIXGBE_I2C_BB_EN\n#define IXGBE_I2C_BB_EN_X550\t\t0x00000100\n#define IXGBE_I2C_BB_EN_X550EM_x\tIXGBE_I2C_BB_EN_X550\n\n#define IXGBE_I2C_BB_EN_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), I2C_BB_EN)\n\n#define IXGBE_I2C_CLK_OE_N_EN\t\t0\n#define IXGBE_I2C_CLK_OE_N_EN_X540\tIXGBE_I2C_CLK_OE_N_EN\n#define IXGBE_I2C_CLK_OE_N_EN_X550\t0x00002000\n#define IXGBE_I2C_CLK_OE_N_EN_X550EM_x\tIXGBE_I2C_CLK_OE_N_EN_X550\n#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)\n#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT\t500\n\n#define IXGBE_I2C_THERMAL_SENSOR_ADDR\t0xF8\n#define IXGBE_EMC_INTERNAL_DATA\t\t0x00\n#define IXGBE_EMC_INTERNAL_THERM_LIMIT\t0x20\n#define IXGBE_EMC_DIODE1_DATA\t\t0x01\n#define IXGBE_EMC_DIODE1_THERM_LIMIT\t0x19\n#define IXGBE_EMC_DIODE2_DATA\t\t0x23\n#define IXGBE_EMC_DIODE2_THERM_LIMIT\t0x1A\n\n#define IXGBE_MAX_SENSORS\t\t3\n\nstruct ixgbe_thermal_diode_data {\n\tu8 location;\n\tu8 temp;\n\tu8 caution_thresh;\n\tu8 max_op_thresh;\n};\n\nstruct ixgbe_thermal_sensor_data {\n\tstruct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];\n};\n\n/* Interrupt Registers */\n#define IXGBE_EICR\t\t0x00800\n#define IXGBE_EICS\t\t0x00808\n#define IXGBE_EIMS\t\t0x00880\n#define IXGBE_EIMC\t\t0x00888\n#define IXGBE_EIAC\t\t0x00810\n#define IXGBE_EIAM\t\t0x00890\n#define IXGBE_EICS_EX(_i)\t(0x00A90 + (_i) * 4)\n#define IXGBE_EIMS_EX(_i)\t(0x00AA0 + (_i) * 4)\n#define IXGBE_EIMC_EX(_i)\t(0x00AB0 + (_i) * 4)\n#define IXGBE_EIAM_EX(_i)\t(0x00AD0 + (_i) * 4)\n/* 82599 EITR is only 12 bits, with the lower 3 always zero */\n/*\n * 82598 EITR is 16 bits but set the limits based on the max\n * supported by all ixgbe hardware\n */\n#define IXGBE_MAX_INT_RATE\t488281\n#define IXGBE_MIN_INT_RATE\t956\n#define IXGBE_MAX_EITR\t\t0x00000FF8\n#define IXGBE_MIN_EITR\t\t8\n#define IXGBE_EITR(_i)\t\t(((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \\\n\t\t\t\t (0x012300 + (((_i) - 24) * 4)))\n#define IXGBE_EITR_ITR_INT_MASK\t0x00000FF8\n#define IXGBE_EITR_LLI_MOD\t0x00008000\n#define IXGBE_EITR_CNT_WDIS\t0x80000000\n#define IXGBE_IVAR(_i)\t\t(0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */\n#define IXGBE_IVAR_MISC\t\t0x00A00 /* misc MSI-X interrupt causes */\n#define IXGBE_EITRSEL\t\t0x00894\n#define IXGBE_MSIXT\t\t0x00000 /* MSI-X Table. 0x0000 - 0x01C */\n#define IXGBE_MSIXPBA\t\t0x02000 /* MSI-X Pending bit array */\n#define IXGBE_PBACL(_i)\t(((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))\n#define IXGBE_GPIE\t\t0x00898\n\n/* Flow Control Registers */\n#define IXGBE_FCADBUL\t\t0x03210\n#define IXGBE_FCADBUH\t\t0x03214\n#define IXGBE_FCAMACL\t\t0x04328\n#define IXGBE_FCAMACH\t\t0x0432C\n#define IXGBE_FCRTH_82599(_i)\t(0x03260 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_FCRTL_82599(_i)\t(0x03220 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_PFCTOP\t\t0x03008\n#define IXGBE_FCTTV(_i)\t\t(0x03200 + ((_i) * 4)) /* 4 of these (0-3) */\n#define IXGBE_FCRTL(_i)\t\t(0x03220 + ((_i) * 8)) /* 8 of these (0-7) */\n#define IXGBE_FCRTH(_i)\t\t(0x03260 + ((_i) * 8)) /* 8 of these (0-7) */\n#define IXGBE_FCRTV\t\t0x032A0\n#define IXGBE_FCCFG\t\t0x03D00\n#define IXGBE_TFCS\t\t0x0CE00\n\n/* Receive DMA Registers */\n#define IXGBE_RDBAL(_i)\t(((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \\\n\t\t\t (0x0D000 + (((_i) - 64) * 0x40)))\n#define IXGBE_RDBAH(_i)\t(((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \\\n\t\t\t (0x0D004 + (((_i) - 64) * 0x40)))\n#define IXGBE_RDLEN(_i)\t(((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \\\n\t\t\t (0x0D008 + (((_i) - 64) * 0x40)))\n#define IXGBE_RDH(_i)\t(((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \\\n\t\t\t (0x0D010 + (((_i) - 64) * 0x40)))\n#define IXGBE_RDT(_i)\t(((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \\\n\t\t\t (0x0D018 + (((_i) - 64) * 0x40)))\n#define IXGBE_RXDCTL(_i)\t(((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \\\n\t\t\t\t (0x0D028 + (((_i) - 64) * 0x40)))\n#define IXGBE_RSCCTL(_i)\t(((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \\\n\t\t\t\t (0x0D02C + (((_i) - 64) * 0x40)))\n#define IXGBE_RSCDBU\t0x03028\n#define IXGBE_RDDCC\t0x02F20\n#define IXGBE_RXMEMWRAP\t0x03190\n#define IXGBE_STARCTRL\t0x03024\n/*\n * Split and Replication Receive Control Registers\n * 00-15 : 0x02100 + n*4\n * 16-64 : 0x01014 + n*0x40\n * 64-127: 0x0D014 + (n-64)*0x40\n */\n#define IXGBE_SRRCTL(_i)\t(((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \\\n\t\t\t\t (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \\\n\t\t\t\t (0x0D014 + (((_i) - 64) * 0x40))))\n/*\n * Rx DCA Control Register:\n * 00-15 : 0x02200 + n*4\n * 16-64 : 0x0100C + n*0x40\n * 64-127: 0x0D00C + (n-64)*0x40\n */\n#define IXGBE_DCA_RXCTRL(_i)\t(((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \\\n\t\t\t\t (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \\\n\t\t\t\t (0x0D00C + (((_i) - 64) * 0x40))))\n#define IXGBE_RDRXCTL\t\t0x02F00\n/* 8 of these 0x03C00 - 0x03C1C */\n#define IXGBE_RXPBSIZE(_i)\t(0x03C00 + ((_i) * 4))\n#define IXGBE_RXCTRL\t\t0x03000\n#define IXGBE_DROPEN\t\t0x03D04\n#define IXGBE_RXPBSIZE_SHIFT\t10\n#define IXGBE_RXPBSIZE_MASK\t0x000FFC00\n\n/* Receive Registers */\n#define IXGBE_RXCSUM\t\t0x05000\n#define IXGBE_RFCTL\t\t0x05008\n#define IXGBE_DRECCCTL\t\t0x02F08\n#define IXGBE_DRECCCTL_DISABLE\t0\n#define IXGBE_DRECCCTL2\t\t0x02F8C\n\n/* Multicast Table Array - 128 entries */\n#define IXGBE_MTA(_i)\t\t(0x05200 + ((_i) * 4))\n#define IXGBE_RAL(_i)\t\t(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \\\n\t\t\t\t (0x0A200 + ((_i) * 8)))\n#define IXGBE_RAH(_i)\t\t(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \\\n\t\t\t\t (0x0A204 + ((_i) * 8)))\n#define IXGBE_MPSAR_LO(_i)\t(0x0A600 + ((_i) * 8))\n#define IXGBE_MPSAR_HI(_i)\t(0x0A604 + ((_i) * 8))\n/* Packet split receive type */\n#define IXGBE_PSRTYPE(_i)\t(((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \\\n\t\t\t\t (0x0EA00 + ((_i) * 4)))\n/* array of 4096 1-bit vlan filters */\n#define IXGBE_VFTA(_i)\t\t(0x0A000 + ((_i) * 4))\n/*array of 4096 4-bit vlan vmdq indices */\n#define IXGBE_VFTAVIND(_j, _i)\t(0x0A200 + ((_j) * 0x200) + ((_i) * 4))\n#define IXGBE_FCTRL\t\t0x05080\n#define IXGBE_VLNCTRL\t\t0x05088\n#define IXGBE_MCSTCTRL\t\t0x05090\n#define IXGBE_MRQC\t\t0x05818\n#define IXGBE_SAQF(_i)\t(0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */\n#define IXGBE_DAQF(_i)\t(0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */\n#define IXGBE_SDPQF(_i)\t(0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */\n#define IXGBE_FTQF(_i)\t(0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */\n#define IXGBE_ETQF(_i)\t(0x05128 + ((_i) * 4)) /* EType Queue Filter */\n#define IXGBE_ETQS(_i)\t(0x0EC00 + ((_i) * 4)) /* EType Queue Select */\n#define IXGBE_SYNQF\t0x0EC30 /* SYN Packet Queue Filter */\n#define IXGBE_RQTC\t0x0EC70\n#define IXGBE_MTQC\t0x08120\n#define IXGBE_VLVF(_i)\t(0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */\n#define IXGBE_VLVFB(_i)\t(0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */\n#define IXGBE_VMVIR(_i)\t(0x08000 + ((_i) * 4)) /* 64 of these (0-63) */\n#define IXGBE_PFFLPL\t\t0x050B0\n#define IXGBE_PFFLPH\t\t0x050B4\n#define IXGBE_VT_CTL\t\t0x051B0\n#define IXGBE_PFMAILBOX(_i)\t(0x04B00 + (4 * (_i))) /* 64 total */\n/* 64 Mailboxes, 16 DW each */\n#define IXGBE_PFMBMEM(_i)\t(0x13000 + (64 * (_i)))\n#define IXGBE_PFMBICR(_i)\t(0x00710 + (4 * (_i))) /* 4 total */\n#define IXGBE_PFMBIMR(_i)\t(0x00720 + (4 * (_i))) /* 4 total */\n#define IXGBE_VFRE(_i)\t\t(0x051E0 + ((_i) * 4))\n#define IXGBE_VFTE(_i)\t\t(0x08110 + ((_i) * 4))\n#define IXGBE_VMECM(_i)\t\t(0x08790 + ((_i) * 4))\n#define IXGBE_QDE\t\t0x2F04\n#define IXGBE_VMTXSW(_i)\t(0x05180 + ((_i) * 4)) /* 2 total */\n#define IXGBE_VMOLR(_i)\t\t(0x0F000 + ((_i) * 4)) /* 64 total */\n#define IXGBE_UTA(_i)\t\t(0x0F400 + ((_i) * 4))\n#define IXGBE_MRCTL(_i)\t\t(0x0F600 + ((_i) * 4))\n#define IXGBE_VMRVLAN(_i)\t(0x0F610 + ((_i) * 4))\n#define IXGBE_VMRVM(_i)\t\t(0x0F630 + ((_i) * 4))\n#define IXGBE_LVMMC_RX\t\t0x2FA8\n#define IXGBE_LVMMC_TX\t\t0x8108\n#define IXGBE_LMVM_RX\t\t0x2FA4\n#define IXGBE_LMVM_TX\t\t0x8124\n#define IXGBE_WQBR_RX(_i)\t(0x2FB0 + ((_i) * 4)) /* 4 total */\n#define IXGBE_WQBR_TX(_i)\t(0x8130 + ((_i) * 4)) /* 4 total */\n#define IXGBE_L34T_IMIR(_i)\t(0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/\n#define IXGBE_RXFECCERR0\t0x051B8\n#define IXGBE_LLITHRESH\t\t0x0EC90\n#define IXGBE_IMIR(_i)\t\t(0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_IMIREXT(_i)\t(0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_IMIRVP\t\t0x05AC0\n#define IXGBE_VMD_CTL\t\t0x0581C\n#define IXGBE_RETA(_i)\t\t(0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */\n#define IXGBE_ERETA(_i)\t\t(0x0EE80 + ((_i) * 4)) /* 96 of these (0-95) */\n#define IXGBE_RSSRK(_i)\t\t(0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */\n\n/* Registers for setting up RSS on X550 with SRIOV\n * _p - pool number (0..63)\n * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)\n */\n#define IXGBE_PFVFMRQC(_p)\t(0x03400 + ((_p) * 4))\n#define IXGBE_PFVFRSSRK(_i, _p)\t(0x018000 + ((_i) * 4) + ((_p) * 0x40))\n#define IXGBE_PFVFRETA(_i, _p)\t(0x019000 + ((_i) * 4) + ((_p) * 0x40))\n\n/* Flow Director registers */\n#define IXGBE_FDIRCTRL\t0x0EE00\n#define IXGBE_FDIRHKEY\t0x0EE68\n#define IXGBE_FDIRSKEY\t0x0EE6C\n#define IXGBE_FDIRDIP4M\t0x0EE3C\n#define IXGBE_FDIRSIP4M\t0x0EE40\n#define IXGBE_FDIRTCPM\t0x0EE44\n#define IXGBE_FDIRUDPM\t0x0EE48\n#define IXGBE_FDIRSCTPM\t0x0EE78\n#define IXGBE_FDIRIP6M\t0x0EE74\n#define IXGBE_FDIRM\t0x0EE70\n\n/* Flow Director Stats registers */\n#define IXGBE_FDIRFREE\t0x0EE38\n#define IXGBE_FDIRLEN\t0x0EE4C\n#define IXGBE_FDIRUSTAT\t0x0EE50\n#define IXGBE_FDIRFSTAT\t0x0EE54\n#define IXGBE_FDIRMATCH\t0x0EE58\n#define IXGBE_FDIRMISS\t0x0EE5C\n\n/* Flow Director Programming registers */\n#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */\n#define IXGBE_FDIRIPSA\t0x0EE18\n#define IXGBE_FDIRIPDA\t0x0EE1C\n#define IXGBE_FDIRPORT\t0x0EE20\n#define IXGBE_FDIRVLAN\t0x0EE24\n#define IXGBE_FDIRHASH\t0x0EE28\n#define IXGBE_FDIRCMD\t0x0EE2C\n\n/* Transmit DMA registers */\n#define IXGBE_TDBAL(_i)\t\t(0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/\n#define IXGBE_TDBAH(_i)\t\t(0x06004 + ((_i) * 0x40))\n#define IXGBE_TDLEN(_i)\t\t(0x06008 + ((_i) * 0x40))\n#define IXGBE_TDH(_i)\t\t(0x06010 + ((_i) * 0x40))\n#define IXGBE_TDT(_i)\t\t(0x06018 + ((_i) * 0x40))\n#define IXGBE_TXDCTL(_i)\t(0x06028 + ((_i) * 0x40))\n#define IXGBE_TDWBAL(_i)\t(0x06038 + ((_i) * 0x40))\n#define IXGBE_TDWBAH(_i)\t(0x0603C + ((_i) * 0x40))\n#define IXGBE_DTXCTL\t\t0x07E00\n\n#define IXGBE_DMATXCTL\t\t0x04A80\n#define IXGBE_PFVFSPOOF(_i)\t(0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */\n#define IXGBE_PFDTXGSWC\t\t0x08220\n#define IXGBE_DTXMXSZRQ\t\t0x08100\n#define IXGBE_DTXTCPFLGL\t0x04A88\n#define IXGBE_DTXTCPFLGH\t0x04A8C\n#define IXGBE_LBDRPEN\t\t0x0CA00\n#define IXGBE_TXPBTHRESH(_i)\t(0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */\n\n#define IXGBE_DMATXCTL_TE\t0x1 /* Transmit Enable */\n#define IXGBE_DMATXCTL_NS\t0x2 /* No Snoop LSO hdr buffer */\n#define IXGBE_DMATXCTL_GDV\t0x8 /* Global Double VLAN */\n#define IXGBE_DMATXCTL_MDP_EN\t0x20 /* Bit 5 */\n#define IXGBE_DMATXCTL_MBINTEN\t0x40 /* Bit 6 */\n#define IXGBE_DMATXCTL_VT_SHIFT\t16 /* VLAN EtherType */\n\n#define IXGBE_PFDTXGSWC_VT_LBEN\t0x1 /* Local L2 VT switch enable */\n\n/* Anti-spoofing defines */\n#define IXGBE_SPOOF_MACAS_MASK\t\t0xFF\n#define IXGBE_SPOOF_VLANAS_MASK\t\t0xFF00\n#define IXGBE_SPOOF_VLANAS_SHIFT\t8\n#define IXGBE_SPOOF_ETHERTYPEAS\t\t0xFF000000\n#define IXGBE_SPOOF_ETHERTYPEAS_SHIFT\t16\n#define IXGBE_PFVFSPOOF_REG_COUNT\t8\n/* 16 of these (0-15) */\n#define IXGBE_DCA_TXCTRL(_i)\t\t(0x07200 + ((_i) * 4))\n/* Tx DCA Control register : 128 of these (0-127) */\n#define IXGBE_DCA_TXCTRL_82599(_i)\t(0x0600C + ((_i) * 0x40))\n#define IXGBE_TIPG\t\t\t0x0CB00\n#define IXGBE_TXPBSIZE(_i)\t\t(0x0CC00 + ((_i) * 4)) /* 8 of these */\n#define IXGBE_MNGTXMAP\t\t\t0x0CD10\n#define IXGBE_TIPG_FIBER_DEFAULT\t3\n#define IXGBE_TXPBSIZE_SHIFT\t\t10\n\n/* Wake up registers */\n#define IXGBE_WUC\t0x05800\n#define IXGBE_WUFC\t0x05808\n#define IXGBE_WUS\t0x05810\n#define IXGBE_IPAV\t0x05838\n#define IXGBE_IP4AT\t0x05840 /* IPv4 table 0x5840-0x5858 */\n#define IXGBE_IP6AT\t0x05880 /* IPv6 table 0x5880-0x588F */\n\n#define IXGBE_WUPL\t0x05900\n#define IXGBE_WUPM\t0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */\n#define IXGBE_PROXYS\t0x05F60 /* Proxying Status Register */\n#define IXGBE_PROXYFC\t0x05F64 /* Proxying Filter Control Register */\n#define IXGBE_VXLANCTRL\t0x0000507C /* Rx filter VXLAN UDPPORT Register */\n\n#define IXGBE_FHFT(_n)\t(0x09000 + ((_n) * 0x100)) /* Flex host filter table */\n/* Ext Flexible Host Filter Table */\n#define IXGBE_FHFT_EXT(_n)\t(0x09800 + ((_n) * 0x100))\n#define IXGBE_FHFT_EXT_X550(_n)\t(0x09600 + ((_n) * 0x100))\n\n/* Four Flexible Filters are supported */\n#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX\t\t4\n\n/* Six Flexible Filters are supported */\n#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6\t6\n/* Eight Flexible Filters are supported */\n#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8\t8\n#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX\t2\n\n/* Each Flexible Filter is at most 128 (0x80) bytes in length */\n#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX\t\t128\n#define IXGBE_FHFT_LENGTH_OFFSET\t\t0xFC /* Length byte in FHFT */\n#define IXGBE_FHFT_LENGTH_MASK\t\t\t0x0FF /* Length in lower byte */\n\n/* Definitions for power management and wakeup registers */\n/* Wake Up Control */\n#define IXGBE_WUC_PME_EN\t0x00000002 /* PME Enable */\n#define IXGBE_WUC_PME_STATUS\t0x00000004 /* PME Status */\n#define IXGBE_WUC_WKEN\t\t0x00000010 /* Enable PE_WAKE_N pin assertion */\n\n/* Wake Up Filter Control */\n#define IXGBE_WUFC_LNKC\t0x00000001 /* Link Status Change Wakeup Enable */\n#define IXGBE_WUFC_MAG\t0x00000002 /* Magic Packet Wakeup Enable */\n#define IXGBE_WUFC_EX\t0x00000004 /* Directed Exact Wakeup Enable */\n#define IXGBE_WUFC_MC\t0x00000008 /* Directed Multicast Wakeup Enable */\n#define IXGBE_WUFC_BC\t0x00000010 /* Broadcast Wakeup Enable */\n#define IXGBE_WUFC_ARP\t0x00000020 /* ARP Request Packet Wakeup Enable */\n#define IXGBE_WUFC_IPV4\t0x00000040 /* Directed IPv4 Packet Wakeup Enable */\n#define IXGBE_WUFC_IPV6\t0x00000080 /* Directed IPv6 Packet Wakeup Enable */\n#define IXGBE_WUFC_MNG\t0x00000100 /* Directed Mgmt Packet Wakeup Enable */\n\n#define IXGBE_WUFC_IGNORE_TCO\t0x00008000 /* Ignore WakeOn TCO packets */\n#define IXGBE_WUFC_FLX0\t0x00010000 /* Flexible Filter 0 Enable */\n#define IXGBE_WUFC_FLX1\t0x00020000 /* Flexible Filter 1 Enable */\n#define IXGBE_WUFC_FLX2\t0x00040000 /* Flexible Filter 2 Enable */\n#define IXGBE_WUFC_FLX3\t0x00080000 /* Flexible Filter 3 Enable */\n#define IXGBE_WUFC_FLX4\t0x00100000 /* Flexible Filter 4 Enable */\n#define IXGBE_WUFC_FLX5\t0x00200000 /* Flexible Filter 5 Enable */\n#define IXGBE_WUFC_FLX_FILTERS\t\t0x000F0000 /* Mask for 4 flex filters */\n#define IXGBE_WUFC_FLX_FILTERS_6\t0x003F0000 /* Mask for 6 flex filters */\n#define IXGBE_WUFC_FLX_FILTERS_8\t0x00FF0000 /* Mask for 8 flex filters */\n#define IXGBE_WUFC_FW_RST_WK\t0x80000000 /* Ena wake on FW reset assertion */\n/* Mask for Ext. flex filters */\n#define IXGBE_WUFC_EXT_FLX_FILTERS\t0x00300000\n#define IXGBE_WUFC_ALL_FILTERS\t\t0x000F00FF /* Mask all 4 flex filters */\n#define IXGBE_WUFC_ALL_FILTERS_6\t0x003F00FF /* Mask all 6 flex filters */\n#define IXGBE_WUFC_ALL_FILTERS_8\t0x00FF00FF /* Mask all 8 flex filters */\n#define IXGBE_WUFC_FLX_OFFSET\t16 /* Offset to the Flexible Filters bits */\n\n/* Wake Up Status */\n#define IXGBE_WUS_LNKC\t\tIXGBE_WUFC_LNKC\n#define IXGBE_WUS_MAG\t\tIXGBE_WUFC_MAG\n#define IXGBE_WUS_EX\t\tIXGBE_WUFC_EX\n#define IXGBE_WUS_MC\t\tIXGBE_WUFC_MC\n#define IXGBE_WUS_BC\t\tIXGBE_WUFC_BC\n#define IXGBE_WUS_ARP\t\tIXGBE_WUFC_ARP\n#define IXGBE_WUS_IPV4\t\tIXGBE_WUFC_IPV4\n#define IXGBE_WUS_IPV6\t\tIXGBE_WUFC_IPV6\n#define IXGBE_WUS_MNG\t\tIXGBE_WUFC_MNG\n#define IXGBE_WUS_FLX0\t\tIXGBE_WUFC_FLX0\n#define IXGBE_WUS_FLX1\t\tIXGBE_WUFC_FLX1\n#define IXGBE_WUS_FLX2\t\tIXGBE_WUFC_FLX2\n#define IXGBE_WUS_FLX3\t\tIXGBE_WUFC_FLX3\n#define IXGBE_WUS_FLX4\t\tIXGBE_WUFC_FLX4\n#define IXGBE_WUS_FLX5\t\tIXGBE_WUFC_FLX5\n#define IXGBE_WUS_FLX_FILTERS\tIXGBE_WUFC_FLX_FILTERS\n#define IXGBE_WUS_FW_RST_WK\tIXGBE_WUFC_FW_RST_WK\n/* Proxy Status */\n#define IXGBE_PROXYS_EX\t\t0x00000004 /* Exact packet received */\n#define IXGBE_PROXYS_ARP_DIR\t0x00000020 /* ARP w/filter match received */\n#define IXGBE_PROXYS_NS\t\t0x00000200 /* IPV6 NS received */\n#define IXGBE_PROXYS_NS_DIR\t0x00000400 /* IPV6 NS w/DA match received */\n#define IXGBE_PROXYS_ARP\t0x00000800 /* ARP request packet received */\n#define IXGBE_PROXYS_MLD\t0x00001000 /* IPv6 MLD packet received */\n\n/* Proxying Filter Control */\n#define IXGBE_PROXYFC_ENABLE\t0x00000001 /* Port Proxying Enable */\n#define IXGBE_PROXYFC_EX\t0x00000004 /* Directed Exact Proxy Enable */\n#define IXGBE_PROXYFC_ARP_DIR\t0x00000020 /* Directed ARP Proxy Enable */\n#define IXGBE_PROXYFC_NS\t0x00000200 /* IPv6 Neighbor Solicitation */\n#define IXGBE_PROXYFC_ARP\t0x00000800 /* ARP Request Proxy Enable */\n#define IXGBE_PROXYFC_MLD\t0x00000800 /* IPv6 MLD Proxy Enable */\n#define IXGBE_PROXYFC_NO_TCO\t0x00008000 /* Ignore TCO packets */\n\n#define IXGBE_WUPL_LENGTH_MASK\t0xFFFF\n\n/* DCB registers */\n#define IXGBE_DCB_MAX_TRAFFIC_CLASS\t8\n#define IXGBE_RMCS\t\t0x03D00\n#define IXGBE_DPMCS\t\t0x07F40\n#define IXGBE_PDPMCS\t\t0x0CD00\n#define IXGBE_RUPPBMR\t\t0x050A0\n#define IXGBE_RT2CR(_i)\t\t(0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_RT2SR(_i)\t\t(0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_TDTQ2TCCR(_i)\t(0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */\n#define IXGBE_TDTQ2TCSR(_i)\t(0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */\n#define IXGBE_TDPT2TCCR(_i)\t(0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_TDPT2TCSR(_i)\t(0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */\n\n/* Power Management */\n/* DMA Coalescing configuration */\nstruct ixgbe_dmac_config {\n\tu16\twatchdog_timer; /* usec units */\n\tbool\tfcoe_en;\n\tu32\tlink_speed;\n\tu8\tfcoe_tc;\n\tu8\tnum_tcs;\n};\n\n/*\n * DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed.\n * DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 ==\n * 87500 bytes [85KB]\n */\n#define IXGBE_DMACRXT_10G\t\t0x55\n#define IXGBE_DMACRXT_1G\t\t0x09\n#define IXGBE_DMACRXT_100M\t\t0x01\n\n/* DMA Coalescing registers */\n#define IXGBE_DMCMNGTH\t\t\t0x15F20 /* Management Threshold */\n#define IXGBE_DMACR\t\t\t0x02400 /* Control register */\n#define IXGBE_DMCTH(_i)\t\t\t(0x03300 + ((_i) * 4)) /* 8 of these */\n#define IXGBE_DMCTLX\t\t\t0x02404 /* Time to Lx request */\n/* DMA Coalescing register fields */\n#define IXGBE_DMCMNGTH_DMCMNGTH_MASK\t0x000FFFF0 /* Mng Threshold mask */\n#define IXGBE_DMCMNGTH_DMCMNGTH_SHIFT\t4 /* Management Threshold shift */\n#define IXGBE_DMACR_DMACWT_MASK\t\t0x0000FFFF /* Watchdog Timer mask */\n#define IXGBE_DMACR_HIGH_PRI_TC_MASK\t0x00FF0000\n#define IXGBE_DMACR_HIGH_PRI_TC_SHIFT\t16\n#define IXGBE_DMACR_EN_MNG_IND\t\t0x10000000 /* Enable Mng Indications */\n#define IXGBE_DMACR_LX_COAL_IND\t\t0x40000000 /* Lx Coalescing indicate */\n#define IXGBE_DMACR_DMAC_EN\t\t0x80000000 /* DMA Coalescing Enable */\n#define IXGBE_DMCTH_DMACRXT_MASK\t0x000001FF /* Receive Threshold mask */\n#define IXGBE_DMCTLX_TTLX_MASK\t\t0x00000FFF /* Time to Lx request mask */\n\n/* EEE registers */\n#define IXGBE_EEER\t\t\t0x043A0 /* EEE register */\n#define IXGBE_EEE_STAT\t\t\t0x04398 /* EEE Status */\n#define IXGBE_EEE_SU\t\t\t0x04380 /* EEE Set up */\n#define IXGBE_EEE_SU_TEEE_DLY_SHIFT\t26\n#define IXGBE_TLPIC\t\t\t0x041F4 /* EEE Tx LPI count */\n#define IXGBE_RLPIC\t\t\t0x041F8 /* EEE Rx LPI count */\n\n/* EEE register fields */\n#define IXGBE_EEER_TX_LPI_EN\t\t0x00010000 /* Enable EEE LPI TX path */\n#define IXGBE_EEER_RX_LPI_EN\t\t0x00020000 /* Enable EEE LPI RX path */\n#define IXGBE_EEE_STAT_NEG\t\t0x20000000 /* EEE support neg on link */\n#define IXGBE_EEE_RX_LPI_STATUS\t\t0x40000000 /* RX Link in LPI status */\n#define IXGBE_EEE_TX_LPI_STATUS\t\t0x80000000 /* TX Link in LPI status */\n\n\n\n/* Security Control Registers */\n#define IXGBE_SECTXCTRL\t\t0x08800\n#define IXGBE_SECTXSTAT\t\t0x08804\n#define IXGBE_SECTXBUFFAF\t0x08808\n#define IXGBE_SECTXMINIFG\t0x08810\n#define IXGBE_SECRXCTRL\t\t0x08D00\n#define IXGBE_SECRXSTAT\t\t0x08D04\n\n/* Security Bit Fields and Masks */\n#define IXGBE_SECTXCTRL_SECTX_DIS\t0x00000001\n#define IXGBE_SECTXCTRL_TX_DIS\t\t0x00000002\n#define IXGBE_SECTXCTRL_STORE_FORWARD\t0x00000004\n\n#define IXGBE_SECTXSTAT_SECTX_RDY\t0x00000001\n#define IXGBE_SECTXSTAT_ECC_TXERR\t0x00000002\n\n#define IXGBE_SECRXCTRL_SECRX_DIS\t0x00000001\n#define IXGBE_SECRXCTRL_RX_DIS\t\t0x00000002\n\n#define IXGBE_SECRXSTAT_SECRX_RDY\t0x00000001\n#define IXGBE_SECRXSTAT_ECC_RXERR\t0x00000002\n\n/* LinkSec (MacSec) Registers */\n#define IXGBE_LSECTXCAP\t\t0x08A00\n#define IXGBE_LSECRXCAP\t\t0x08F00\n#define IXGBE_LSECTXCTRL\t0x08A04\n#define IXGBE_LSECTXSCL\t\t0x08A08 /* SCI Low */\n#define IXGBE_LSECTXSCH\t\t0x08A0C /* SCI High */\n#define IXGBE_LSECTXSA\t\t0x08A10\n#define IXGBE_LSECTXPN0\t\t0x08A14\n#define IXGBE_LSECTXPN1\t\t0x08A18\n#define IXGBE_LSECTXKEY0(_n)\t(0x08A1C + (4 * (_n))) /* 4 of these (0-3) */\n#define IXGBE_LSECTXKEY1(_n)\t(0x08A2C + (4 * (_n))) /* 4 of these (0-3) */\n#define IXGBE_LSECRXCTRL\t0x08F04\n#define IXGBE_LSECRXSCL\t\t0x08F08\n#define IXGBE_LSECRXSCH\t\t0x08F0C\n#define IXGBE_LSECRXSA(_i)\t(0x08F10 + (4 * (_i))) /* 2 of these (0-1) */\n#define IXGBE_LSECRXPN(_i)\t(0x08F18 + (4 * (_i))) /* 2 of these (0-1) */\n#define IXGBE_LSECRXKEY(_n, _m)\t(0x08F20 + ((0x10 * (_n)) + (4 * (_m))))\n#define IXGBE_LSECTXUT\t\t0x08A3C /* OutPktsUntagged */\n#define IXGBE_LSECTXPKTE\t0x08A40 /* OutPktsEncrypted */\n#define IXGBE_LSECTXPKTP\t0x08A44 /* OutPktsProtected */\n#define IXGBE_LSECTXOCTE\t0x08A48 /* OutOctetsEncrypted */\n#define IXGBE_LSECTXOCTP\t0x08A4C /* OutOctetsProtected */\n#define IXGBE_LSECRXUT\t\t0x08F40 /* InPktsUntagged/InPktsNoTag */\n#define IXGBE_LSECRXOCTD\t0x08F44 /* InOctetsDecrypted */\n#define IXGBE_LSECRXOCTV\t0x08F48 /* InOctetsValidated */\n#define IXGBE_LSECRXBAD\t\t0x08F4C /* InPktsBadTag */\n#define IXGBE_LSECRXNOSCI\t0x08F50 /* InPktsNoSci */\n#define IXGBE_LSECRXUNSCI\t0x08F54 /* InPktsUnknownSci */\n#define IXGBE_LSECRXUNCH\t0x08F58 /* InPktsUnchecked */\n#define IXGBE_LSECRXDELAY\t0x08F5C /* InPktsDelayed */\n#define IXGBE_LSECRXLATE\t0x08F60 /* InPktsLate */\n#define IXGBE_LSECRXOK(_n)\t(0x08F64 + (0x04 * (_n))) /* InPktsOk */\n#define IXGBE_LSECRXINV(_n)\t(0x08F6C + (0x04 * (_n))) /* InPktsInvalid */\n#define IXGBE_LSECRXNV(_n)\t(0x08F74 + (0x04 * (_n))) /* InPktsNotValid */\n#define IXGBE_LSECRXUNSA\t0x08F7C /* InPktsUnusedSa */\n#define IXGBE_LSECRXNUSA\t0x08F80 /* InPktsNotUsingSa */\n\n/* LinkSec (MacSec) Bit Fields and Masks */\n#define IXGBE_LSECTXCAP_SUM_MASK\t0x00FF0000\n#define IXGBE_LSECTXCAP_SUM_SHIFT\t16\n#define IXGBE_LSECRXCAP_SUM_MASK\t0x00FF0000\n#define IXGBE_LSECRXCAP_SUM_SHIFT\t16\n\n#define IXGBE_LSECTXCTRL_EN_MASK\t0x00000003\n#define IXGBE_LSECTXCTRL_DISABLE\t0x0\n#define IXGBE_LSECTXCTRL_AUTH\t\t0x1\n#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT\t0x2\n#define IXGBE_LSECTXCTRL_AISCI\t\t0x00000020\n#define IXGBE_LSECTXCTRL_PNTHRSH_MASK\t0xFFFFFF00\n#define IXGBE_LSECTXCTRL_RSV_MASK\t0x000000D8\n\n#define IXGBE_LSECRXCTRL_EN_MASK\t0x0000000C\n#define IXGBE_LSECRXCTRL_EN_SHIFT\t2\n#define IXGBE_LSECRXCTRL_DISABLE\t0x0\n#define IXGBE_LSECRXCTRL_CHECK\t\t0x1\n#define IXGBE_LSECRXCTRL_STRICT\t\t0x2\n#define IXGBE_LSECRXCTRL_DROP\t\t0x3\n#define IXGBE_LSECRXCTRL_PLSH\t\t0x00000040\n#define IXGBE_LSECRXCTRL_RP\t\t0x00000080\n#define IXGBE_LSECRXCTRL_RSV_MASK\t0xFFFFFF33\n\n/* IpSec Registers */\n#define IXGBE_IPSTXIDX\t\t0x08900\n#define IXGBE_IPSTXSALT\t\t0x08904\n#define IXGBE_IPSTXKEY(_i)\t(0x08908 + (4 * (_i))) /* 4 of these (0-3) */\n#define IXGBE_IPSRXIDX\t\t0x08E00\n#define IXGBE_IPSRXIPADDR(_i)\t(0x08E04 + (4 * (_i))) /* 4 of these (0-3) */\n#define IXGBE_IPSRXSPI\t\t0x08E14\n#define IXGBE_IPSRXIPIDX\t0x08E18\n#define IXGBE_IPSRXKEY(_i)\t(0x08E1C + (4 * (_i))) /* 4 of these (0-3) */\n#define IXGBE_IPSRXSALT\t\t0x08E2C\n#define IXGBE_IPSRXMOD\t\t0x08E30\n\n#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE\t0x4\n\n/* DCB registers */\n#define IXGBE_RTRPCS\t\t0x02430\n#define IXGBE_RTTDCS\t\t0x04900\n#define IXGBE_RTTDCS_ARBDIS\t0x00000040 /* DCB arbiter disable */\n#define IXGBE_RTTPCS\t\t0x0CD00\n#define IXGBE_RTRUP2TC\t\t0x03020\n#define IXGBE_RTTUP2TC\t\t0x0C800\n#define IXGBE_RTRPT4C(_i)\t(0x02140 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_TXLLQ(_i)\t\t(0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */\n#define IXGBE_RTRPT4S(_i)\t(0x02160 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_RTTDT2C(_i)\t(0x04910 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_RTTDT2S(_i)\t(0x04930 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_RTTPT2C(_i)\t(0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_RTTPT2S(_i)\t(0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_RTTDQSEL\t\t0x04904\n#define IXGBE_RTTDT1C\t\t0x04908\n#define IXGBE_RTTDT1S\t\t0x0490C\n#define IXGBE_RTTDTECC\t\t0x04990\n#define IXGBE_RTTDTECC_NO_BCN\t0x00000100\n\n#define IXGBE_RTTBCNRC\t\t\t0x04984\n#define IXGBE_RTTBCNRC_RS_ENA\t\t0x80000000\n#define IXGBE_RTTBCNRC_RF_DEC_MASK\t0x00003FFF\n#define IXGBE_RTTBCNRC_RF_INT_SHIFT\t14\n#define IXGBE_RTTBCNRC_RF_INT_MASK \\\n\t(IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)\n#define IXGBE_RTTBCNRM\t0x04980\n\n/* BCN (for DCB) Registers */\n#define IXGBE_RTTBCNRS\t0x04988\n#define IXGBE_RTTBCNCR\t0x08B00\n#define IXGBE_RTTBCNACH\t0x08B04\n#define IXGBE_RTTBCNACL\t0x08B08\n#define IXGBE_RTTBCNTG\t0x04A90\n#define IXGBE_RTTBCNIDX\t0x08B0C\n#define IXGBE_RTTBCNCP\t0x08B10\n#define IXGBE_RTFRTIMER\t0x08B14\n#define IXGBE_RTTBCNRTT\t0x05150\n#define IXGBE_RTTBCNRD\t0x0498C\n\n\n/* FCoE DMA Context Registers */\n/* FCoE Direct DMA Context */\n#define IXGBE_FCDDC(_i, _j)\t(0x20000 + ((_i) * 0x4) + ((_j) * 0x10))\n#define IXGBE_FCPTRL\t\t0x02410 /* FC User Desc. PTR Low */\n#define IXGBE_FCPTRH\t\t0x02414 /* FC USer Desc. PTR High */\n#define IXGBE_FCBUFF\t\t0x02418 /* FC Buffer Control */\n#define IXGBE_FCDMARW\t\t0x02420 /* FC Receive DMA RW */\n#define IXGBE_FCBUFF_VALID\t(1 << 0) /* DMA Context Valid */\n#define IXGBE_FCBUFF_BUFFSIZE\t(3 << 3) /* User Buffer Size */\n#define IXGBE_FCBUFF_WRCONTX\t(1 << 7) /* 0: Initiator, 1: Target */\n#define IXGBE_FCBUFF_BUFFCNT\t0x0000ff00 /* Number of User Buffers */\n#define IXGBE_FCBUFF_OFFSET\t0xffff0000 /* User Buffer Offset */\n#define IXGBE_FCBUFF_BUFFSIZE_SHIFT\t3\n#define IXGBE_FCBUFF_BUFFCNT_SHIFT\t8\n#define IXGBE_FCBUFF_OFFSET_SHIFT\t16\n#define IXGBE_FCDMARW_WE\t\t(1 << 14) /* Write enable */\n#define IXGBE_FCDMARW_RE\t\t(1 << 15) /* Read enable */\n#define IXGBE_FCDMARW_FCOESEL\t\t0x000001ff /* FC X_ID: 11 bits */\n#define IXGBE_FCDMARW_LASTSIZE\t\t0xffff0000 /* Last User Buffer Size */\n#define IXGBE_FCDMARW_LASTSIZE_SHIFT\t16\n/* FCoE SOF/EOF */\n#define IXGBE_TEOFF\t\t0x04A94 /* Tx FC EOF */\n#define IXGBE_TSOFF\t\t0x04A98 /* Tx FC SOF */\n#define IXGBE_REOFF\t\t0x05158 /* Rx FC EOF */\n#define IXGBE_RSOFF\t\t0x051F8 /* Rx FC SOF */\n/* FCoE Filter Context Registers */\n#define IXGBE_FCD_ID\t\t0x05114 /* FCoE D_ID */\n#define IXGBE_FCSMAC\t\t0x0510C /* FCoE Source MAC */\n#define IXGBE_FCFLTRW_SMAC_HIGH_SHIFT\t16\n/* FCoE Direct Filter Context */\n#define IXGBE_FCDFC(_i, _j)\t(0x28000 + ((_i) * 0x4) + ((_j) * 0x10))\n#define IXGBE_FCDFCD(_i)\t(0x30000 + ((_i) * 0x4))\n#define IXGBE_FCFLT\t\t0x05108 /* FC FLT Context */\n#define IXGBE_FCFLTRW\t\t0x05110 /* FC Filter RW Control */\n#define IXGBE_FCPARAM\t\t0x051d8 /* FC Offset Parameter */\n#define IXGBE_FCFLT_VALID\t(1 << 0) /* Filter Context Valid */\n#define IXGBE_FCFLT_FIRST\t(1 << 1) /* Filter First */\n#define IXGBE_FCFLT_SEQID\t0x00ff0000 /* Sequence ID */\n#define IXGBE_FCFLT_SEQCNT\t0xff000000 /* Sequence Count */\n#define IXGBE_FCFLTRW_RVALDT\t(1 << 13) /* Fast Re-Validation */\n#define IXGBE_FCFLTRW_WE\t(1 << 14) /* Write Enable */\n#define IXGBE_FCFLTRW_RE\t(1 << 15) /* Read Enable */\n/* FCoE Receive Control */\n#define IXGBE_FCRXCTRL\t\t0x05100 /* FC Receive Control */\n#define IXGBE_FCRXCTRL_FCOELLI\t(1 << 0) /* Low latency interrupt */\n#define IXGBE_FCRXCTRL_SAVBAD\t(1 << 1) /* Save Bad Frames */\n#define IXGBE_FCRXCTRL_FRSTRDH\t(1 << 2) /* EN 1st Read Header */\n#define IXGBE_FCRXCTRL_LASTSEQH\t(1 << 3) /* EN Last Header in Seq */\n#define IXGBE_FCRXCTRL_ALLH\t(1 << 4) /* EN All Headers */\n#define IXGBE_FCRXCTRL_FRSTSEQH\t(1 << 5) /* EN 1st Seq. Header */\n#define IXGBE_FCRXCTRL_ICRC\t(1 << 6) /* Ignore Bad FC CRC */\n#define IXGBE_FCRXCTRL_FCCRCBO\t(1 << 7) /* FC CRC Byte Ordering */\n#define IXGBE_FCRXCTRL_FCOEVER\t0x00000f00 /* FCoE Version: 4 bits */\n#define IXGBE_FCRXCTRL_FCOEVER_SHIFT\t8\n/* FCoE Redirection */\n#define IXGBE_FCRECTL\t\t0x0ED00 /* FC Redirection Control */\n#define IXGBE_FCRETA0\t\t0x0ED10 /* FC Redirection Table 0 */\n#define IXGBE_FCRETA(_i)\t(IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */\n#define IXGBE_FCRECTL_ENA\t0x1 /* FCoE Redir Table Enable */\n#define IXGBE_FCRETASEL_ENA\t0x2 /* FCoE FCRETASEL bit */\n#define IXGBE_FCRETA_SIZE\t8 /* Max entries in FCRETA */\n#define IXGBE_FCRETA_ENTRY_MASK\t0x0000007f /* 7 bits for the queue index */\n#define IXGBE_FCRETA_SIZE_X550\t32 /* Max entries in FCRETA */\n/* Higher 7 bits for the queue index */\n#define IXGBE_FCRETA_ENTRY_HIGH_MASK\t0x007F0000\n#define IXGBE_FCRETA_ENTRY_HIGH_SHIFT\t16\n\n/* Stats registers */\n#define IXGBE_CRCERRS\t0x04000\n#define IXGBE_ILLERRC\t0x04004\n#define IXGBE_ERRBC\t0x04008\n#define IXGBE_MSPDC\t0x04010\n#define IXGBE_MPC(_i)\t(0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/\n#define IXGBE_MLFC\t0x04034\n#define IXGBE_MRFC\t0x04038\n#define IXGBE_RLEC\t0x04040\n#define IXGBE_LXONTXC\t0x03F60\n#define IXGBE_LXONRXC\t0x0CF60\n#define IXGBE_LXOFFTXC\t0x03F68\n#define IXGBE_LXOFFRXC\t0x0CF68\n#define IXGBE_LXONRXCNT\t\t0x041A4\n#define IXGBE_LXOFFRXCNT\t0x041A8\n#define IXGBE_PXONRXCNT(_i)\t(0x04140 + ((_i) * 4)) /* 8 of these */\n#define IXGBE_PXOFFRXCNT(_i)\t(0x04160 + ((_i) * 4)) /* 8 of these */\n#define IXGBE_PXON2OFFCNT(_i)\t(0x03240 + ((_i) * 4)) /* 8 of these */\n#define IXGBE_PXONTXC(_i)\t(0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/\n#define IXGBE_PXONRXC(_i)\t(0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/\n#define IXGBE_PXOFFTXC(_i)\t(0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/\n#define IXGBE_PXOFFRXC(_i)\t(0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/\n#define IXGBE_PRC64\t\t0x0405C\n#define IXGBE_PRC127\t\t0x04060\n#define IXGBE_PRC255\t\t0x04064\n#define IXGBE_PRC511\t\t0x04068\n#define IXGBE_PRC1023\t\t0x0406C\n#define IXGBE_PRC1522\t\t0x04070\n#define IXGBE_GPRC\t\t0x04074\n#define IXGBE_BPRC\t\t0x04078\n#define IXGBE_MPRC\t\t0x0407C\n#define IXGBE_GPTC\t\t0x04080\n#define IXGBE_GORCL\t\t0x04088\n#define IXGBE_GORCH\t\t0x0408C\n#define IXGBE_GOTCL\t\t0x04090\n#define IXGBE_GOTCH\t\t0x04094\n#define IXGBE_RNBC(_i)\t\t(0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/\n#define IXGBE_RUC\t\t0x040A4\n#define IXGBE_RFC\t\t0x040A8\n#define IXGBE_ROC\t\t0x040AC\n#define IXGBE_RJC\t\t0x040B0\n#define IXGBE_MNGPRC\t\t0x040B4\n#define IXGBE_MNGPDC\t\t0x040B8\n#define IXGBE_MNGPTC\t\t0x0CF90\n#define IXGBE_TORL\t\t0x040C0\n#define IXGBE_TORH\t\t0x040C4\n#define IXGBE_TPR\t\t0x040D0\n#define IXGBE_TPT\t\t0x040D4\n#define IXGBE_PTC64\t\t0x040D8\n#define IXGBE_PTC127\t\t0x040DC\n#define IXGBE_PTC255\t\t0x040E0\n#define IXGBE_PTC511\t\t0x040E4\n#define IXGBE_PTC1023\t\t0x040E8\n#define IXGBE_PTC1522\t\t0x040EC\n#define IXGBE_MPTC\t\t0x040F0\n#define IXGBE_BPTC\t\t0x040F4\n#define IXGBE_XEC\t\t0x04120\n#define IXGBE_SSVPC\t\t0x08780\n\n#define IXGBE_RQSMR(_i)\t(0x02300 + ((_i) * 4))\n#define IXGBE_TQSMR(_i)\t(((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \\\n\t\t\t (0x08600 + ((_i) * 4)))\n#define IXGBE_TQSM(_i)\t(0x08600 + ((_i) * 4))\n\n#define IXGBE_QPRC(_i)\t(0x01030 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QPTC(_i)\t(0x06030 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QBRC(_i)\t(0x01034 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QBTC(_i)\t(0x06034 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QBRC_L(_i)\t(0x01034 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QBRC_H(_i)\t(0x01038 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QPRDC(_i)\t\t(0x01430 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QBTC_L(_i)\t(0x08700 + ((_i) * 0x8)) /* 16 of these */\n#define IXGBE_QBTC_H(_i)\t(0x08704 + ((_i) * 0x8)) /* 16 of these */\n#define IXGBE_FCCRC\t\t0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */\n#define IXGBE_FCOERPDC\t\t0x0241C /* FCoE Rx Packets Dropped Count */\n#define IXGBE_FCLAST\t\t0x02424 /* FCoE Last Error Count */\n#define IXGBE_FCOEPRC\t\t0x02428 /* Number of FCoE Packets Received */\n#define IXGBE_FCOEDWRC\t\t0x0242C /* Number of FCoE DWords Received */\n#define IXGBE_FCOEPTC\t\t0x08784 /* Number of FCoE Packets Transmitted */\n#define IXGBE_FCOEDWTC\t\t0x08788 /* Number of FCoE DWords Transmitted */\n#define IXGBE_FCCRC_CNT_MASK\t0x0000FFFF /* CRC_CNT: bit 0 - 15 */\n#define IXGBE_FCLAST_CNT_MASK\t0x0000FFFF /* Last_CNT: bit 0 - 15 */\n#define IXGBE_O2BGPTC\t\t0x041C4\n#define IXGBE_O2BSPC\t\t0x087B0\n#define IXGBE_B2OSPC\t\t0x041C0\n#define IXGBE_B2OGPRC\t\t0x02F90\n#define IXGBE_BUPRC\t\t0x04180\n#define IXGBE_BMPRC\t\t0x04184\n#define IXGBE_BBPRC\t\t0x04188\n#define IXGBE_BUPTC\t\t0x0418C\n#define IXGBE_BMPTC\t\t0x04190\n#define IXGBE_BBPTC\t\t0x04194\n#define IXGBE_BCRCERRS\t\t0x04198\n#define IXGBE_BXONRXC\t\t0x0419C\n#define IXGBE_BXOFFRXC\t\t0x041E0\n#define IXGBE_BXONTXC\t\t0x041E4\n#define IXGBE_BXOFFTXC\t\t0x041E8\n\n/* Management */\n#define IXGBE_MAVTV(_i)\t\t(0x05010 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_MFUTP(_i)\t\t(0x05030 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_MANC\t\t0x05820\n#define IXGBE_MFVAL\t\t0x05824\n#define IXGBE_MANC2H\t\t0x05860\n#define IXGBE_MDEF(_i)\t\t(0x05890 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_MIPAF\t\t0x058B0\n#define IXGBE_MMAL(_i)\t\t(0x05910 + ((_i) * 8)) /* 4 of these (0-3) */\n#define IXGBE_MMAH(_i)\t\t(0x05914 + ((_i) * 8)) /* 4 of these (0-3) */\n#define IXGBE_FTFT\t\t0x09400 /* 0x9400-0x97FC */\n#define IXGBE_METF(_i)\t\t(0x05190 + ((_i) * 4)) /* 4 of these (0-3) */\n#define IXGBE_MDEF_EXT(_i)\t(0x05160 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_LSWFW\t\t0x15014\n#define IXGBE_BMCIP(_i)\t\t(0x05050 + ((_i) * 4)) /* 0x5050-0x505C */\n#define IXGBE_BMCIPVAL\t\t0x05060\n#define IXGBE_BMCIP_IPADDR_TYPE\t0x00000001\n#define IXGBE_BMCIP_IPADDR_VALID\t0x00000002\n\n/* Management Bit Fields and Masks */\n#define IXGBE_MANC_MPROXYE\t0x40000000 /* Management Proxy Enable */\n#define IXGBE_MANC_RCV_TCO_EN\t0x00020000 /* Rcv TCO packet enable */\n#define IXGBE_MANC_EN_BMC2OS\t0x10000000 /* Ena BMC2OS and OS2BMC traffic */\n#define IXGBE_MANC_EN_BMC2OS_SHIFT\t28\n\n/* Firmware Semaphore Register */\n#define IXGBE_FWSM_MODE_MASK\t0xE\n#define IXGBE_FWSM_TS_ENABLED\t0x1\n#define IXGBE_FWSM_FW_MODE_PT\t0x4\n\n/* ARC Subsystem registers */\n#define IXGBE_HICR\t\t0x15F00\n#define IXGBE_FWSTS\t\t0x15F0C\n#define IXGBE_HSMC0R\t\t0x15F04\n#define IXGBE_HSMC1R\t\t0x15F08\n#define IXGBE_SWSR\t\t0x15F10\n#define IXGBE_HFDR\t\t0x15FE8\n#define IXGBE_FLEX_MNG\t\t0x15800 /* 0x15800 - 0x15EFC */\n\n#define IXGBE_HICR_EN\t\t0x01 /* Enable bit - RO */\n/* Driver sets this bit when done to put command in RAM */\n#define IXGBE_HICR_C\t\t0x02\n#define IXGBE_HICR_SV\t\t0x04 /* Status Validity */\n#define IXGBE_HICR_FW_RESET_ENABLE\t0x40\n#define IXGBE_HICR_FW_RESET\t0x80\n\n/* PCI-E registers */\n#define IXGBE_GCR\t\t0x11000\n#define IXGBE_GTV\t\t0x11004\n#define IXGBE_FUNCTAG\t\t0x11008\n#define IXGBE_GLT\t\t0x1100C\n#define IXGBE_PCIEPIPEADR\t0x11004\n#define IXGBE_PCIEPIPEDAT\t0x11008\n#define IXGBE_GSCL_1\t\t0x11010\n#define IXGBE_GSCL_2\t\t0x11014\n#define IXGBE_GSCL_3\t\t0x11018\n#define IXGBE_GSCL_4\t\t0x1101C\n#define IXGBE_GSCN_0\t\t0x11020\n#define IXGBE_GSCN_1\t\t0x11024\n#define IXGBE_GSCN_2\t\t0x11028\n#define IXGBE_GSCN_3\t\t0x1102C\n#define IXGBE_FACTPS\t\t0x10150\n#define IXGBE_FACTPS_X540\tIXGBE_FACTPS\n#define IXGBE_FACTPS_X550\tIXGBE_FACTPS\n#define IXGBE_FACTPS_X550EM_x\tIXGBE_FACTPS\n#define IXGBE_FACTPS_BY_MAC(_hw)\tIXGBE_FACTPS\n\n#define IXGBE_PCIEANACTL\t0x11040\n#define IXGBE_SWSM\t\t0x10140\n#define IXGBE_SWSM_X540\t\tIXGBE_SWSM\n#define IXGBE_SWSM_X550\t\tIXGBE_SWSM\n#define IXGBE_SWSM_X550EM_x\tIXGBE_SWSM\n#define IXGBE_SWSM_BY_MAC(_hw)\tIXGBE_SWSM\n\n#define IXGBE_FWSM\t\t0x10148\n#define IXGBE_FWSM_X540\t\tIXGBE_FWSM\n#define IXGBE_FWSM_X550\t\tIXGBE_FWSM\n#define IXGBE_FWSM_X550EM_x\tIXGBE_FWSM\n#define IXGBE_FWSM_BY_MAC(_hw)\tIXGBE_FWSM\n\n#define IXGBE_SWFW_SYNC\t\tIXGBE_GSSR\n#define IXGBE_SWFW_SYNC_X540\tIXGBE_SWFW_SYNC\n#define IXGBE_SWFW_SYNC_X550\tIXGBE_SWFW_SYNC\n#define IXGBE_SWFW_SYNC_X550EM_x\tIXGBE_SWFW_SYNC\n#define IXGBE_SWFW_SYNC_BY_MAC(_hw)\tIXGBE_SWFW_SYNC\n\n#define IXGBE_GSSR\t\t0x10160\n#define IXGBE_MREVID\t\t0x11064\n#define IXGBE_DCA_ID\t\t0x11070\n#define IXGBE_DCA_CTRL\t\t0x11074\n\n/* PCI-E registers 82599-Specific */\n#define IXGBE_GCR_EXT\t\t0x11050\n#define IXGBE_GSCL_5_82599\t0x11030\n#define IXGBE_GSCL_6_82599\t0x11034\n#define IXGBE_GSCL_7_82599\t0x11038\n#define IXGBE_GSCL_8_82599\t0x1103C\n#define IXGBE_PHYADR_82599\t0x11040\n#define IXGBE_PHYDAT_82599\t0x11044\n#define IXGBE_PHYCTL_82599\t0x11048\n#define IXGBE_PBACLR_82599\t0x11068\n#define IXGBE_CIAA\t\t0x11088\n#define IXGBE_CIAD\t\t0x1108C\n#define IXGBE_CIAA_82599\tIXGBE_CIAA\n#define IXGBE_CIAD_82599\tIXGBE_CIAD\n#define IXGBE_CIAA_X540\t\tIXGBE_CIAA\n#define IXGBE_CIAD_X540\t\tIXGBE_CIAD\n#define IXGBE_CIAA_X550\t\t0x11508\n#define IXGBE_CIAD_X550\t\t0x11510\n#define IXGBE_CIAA_X550EM_x\tIXGBE_CIAA_X550\n#define IXGBE_CIAD_X550EM_x\tIXGBE_CIAD_X550\n#define IXGBE_CIAA_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), CIAA)\n#define IXGBE_CIAD_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), CIAD)\n#define IXGBE_PICAUSE\t\t0x110B0\n#define IXGBE_PIENA\t\t0x110B8\n#define IXGBE_CDQ_MBR_82599\t0x110B4\n#define IXGBE_PCIESPARE\t\t0x110BC\n#define IXGBE_MISC_REG_82599\t0x110F0\n#define IXGBE_ECC_CTRL_0_82599\t0x11100\n#define IXGBE_ECC_CTRL_1_82599\t0x11104\n#define IXGBE_ECC_STATUS_82599\t0x110E0\n#define IXGBE_BAR_CTRL_82599\t0x110F4\n\n/* PCI Express Control */\n#define IXGBE_GCR_CMPL_TMOUT_MASK\t0x0000F000\n#define IXGBE_GCR_CMPL_TMOUT_10ms\t0x00001000\n#define IXGBE_GCR_CMPL_TMOUT_RESEND\t0x00010000\n#define IXGBE_GCR_CAP_VER2\t\t0x00040000\n\n#define IXGBE_GCR_EXT_MSIX_EN\t\t0x80000000\n#define IXGBE_GCR_EXT_BUFFERS_CLEAR\t0x40000000\n#define IXGBE_GCR_EXT_VT_MODE_16\t0x00000001\n#define IXGBE_GCR_EXT_VT_MODE_32\t0x00000002\n#define IXGBE_GCR_EXT_VT_MODE_64\t0x00000003\n#define IXGBE_GCR_EXT_SRIOV\t\t(IXGBE_GCR_EXT_MSIX_EN | \\\n\t\t\t\t\t IXGBE_GCR_EXT_VT_MODE_64)\n#define IXGBE_GCR_EXT_VT_MODE_MASK\t0x00000003\n/* Time Sync Registers */\n#define IXGBE_TSYNCRXCTL\t0x05188 /* Rx Time Sync Control register - RW */\n#define IXGBE_TSYNCTXCTL\t0x08C00 /* Tx Time Sync Control register - RW */\n#define IXGBE_RXSTMPL\t0x051E8 /* Rx timestamp Low - RO */\n#define IXGBE_RXSTMPH\t0x051A4 /* Rx timestamp High - RO */\n#define IXGBE_RXSATRL\t0x051A0 /* Rx timestamp attribute low - RO */\n#define IXGBE_RXSATRH\t0x051A8 /* Rx timestamp attribute high - RO */\n#define IXGBE_RXMTRL\t0x05120 /* RX message type register low - RW */\n#define IXGBE_TXSTMPL\t0x08C04 /* Tx timestamp value Low - RO */\n#define IXGBE_TXSTMPH\t0x08C08 /* Tx timestamp value High - RO */\n#define IXGBE_SYSTIML\t0x08C0C /* System time register Low - RO */\n#define IXGBE_SYSTIMH\t0x08C10 /* System time register High - RO */\n#define IXGBE_SYSTIMR\t0x08C58 /* System time register Residue - RO */\n#define IXGBE_TIMINCA\t0x08C14 /* Increment attributes register - RW */\n#define IXGBE_TIMADJL\t0x08C18 /* Time Adjustment Offset register Low - RW */\n#define IXGBE_TIMADJH\t0x08C1C /* Time Adjustment Offset register High - RW */\n#define IXGBE_TSAUXC\t0x08C20 /* TimeSync Auxiliary Control register - RW */\n#define IXGBE_TRGTTIML0\t0x08C24 /* Target Time Register 0 Low - RW */\n#define IXGBE_TRGTTIMH0\t0x08C28 /* Target Time Register 0 High - RW */\n#define IXGBE_TRGTTIML1\t0x08C2C /* Target Time Register 1 Low - RW */\n#define IXGBE_TRGTTIMH1\t0x08C30 /* Target Time Register 1 High - RW */\n#define IXGBE_CLKTIML\t0x08C34 /* Clock Out Time Register Low - RW */\n#define IXGBE_CLKTIMH\t0x08C38 /* Clock Out Time Register High - RW */\n#define IXGBE_FREQOUT0\t0x08C34 /* Frequency Out 0 Control register - RW */\n#define IXGBE_FREQOUT1\t0x08C38 /* Frequency Out 1 Control register - RW */\n#define IXGBE_AUXSTMPL0\t0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */\n#define IXGBE_AUXSTMPH0\t0x08C40 /* Auxiliary Time Stamp 0 register High - RO */\n#define IXGBE_AUXSTMPL1\t0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */\n#define IXGBE_AUXSTMPH1\t0x08C48 /* Auxiliary Time Stamp 1 register High - RO */\n#define IXGBE_TSIM\t0x08C68 /* TimeSync Interrupt Mask Register - RW */\n#define IXGBE_TSICR\t0x08C60 /* TimeSync Interrupt Cause Register - WO */\n#define IXGBE_TSSDP\t0x0003C /* TimeSync SDP Configuration Register - RW */\n\n/* Diagnostic Registers */\n#define IXGBE_RDSTATCTL\t\t0x02C20\n#define IXGBE_RDSTAT(_i)\t(0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */\n#define IXGBE_RDHMPN\t\t0x02F08\n#define IXGBE_RIC_DW(_i)\t(0x02F10 + ((_i) * 4))\n#define IXGBE_RDPROBE\t\t0x02F20\n#define IXGBE_RDMAM\t\t0x02F30\n#define IXGBE_RDMAD\t\t0x02F34\n#define IXGBE_TDHMPN\t\t0x07F08\n#define IXGBE_TDHMPN2\t\t0x082FC\n#define IXGBE_TXDESCIC\t\t0x082CC\n#define IXGBE_TIC_DW(_i)\t(0x07F10 + ((_i) * 4))\n#define IXGBE_TIC_DW2(_i)\t(0x082B0 + ((_i) * 4))\n#define IXGBE_TDPROBE\t\t0x07F20\n#define IXGBE_TXBUFCTRL\t\t0x0C600\n#define IXGBE_TXBUFDATA0\t0x0C610\n#define IXGBE_TXBUFDATA1\t0x0C614\n#define IXGBE_TXBUFDATA2\t0x0C618\n#define IXGBE_TXBUFDATA3\t0x0C61C\n#define IXGBE_RXBUFCTRL\t\t0x03600\n#define IXGBE_RXBUFDATA0\t0x03610\n#define IXGBE_RXBUFDATA1\t0x03614\n#define IXGBE_RXBUFDATA2\t0x03618\n#define IXGBE_RXBUFDATA3\t0x0361C\n#define IXGBE_PCIE_DIAG(_i)\t(0x11090 + ((_i) * 4)) /* 8 of these */\n#define IXGBE_RFVAL\t\t0x050A4\n#define IXGBE_MDFTC1\t\t0x042B8\n#define IXGBE_MDFTC2\t\t0x042C0\n#define IXGBE_MDFTFIFO1\t\t0x042C4\n#define IXGBE_MDFTFIFO2\t\t0x042C8\n#define IXGBE_MDFTS\t\t0x042CC\n#define IXGBE_RXDATAWRPTR(_i)\t(0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/\n#define IXGBE_RXDESCWRPTR(_i)\t(0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/\n#define IXGBE_RXDATARDPTR(_i)\t(0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/\n#define IXGBE_RXDESCRDPTR(_i)\t(0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/\n#define IXGBE_TXDATAWRPTR(_i)\t(0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/\n#define IXGBE_TXDESCWRPTR(_i)\t(0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/\n#define IXGBE_TXDATARDPTR(_i)\t(0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/\n#define IXGBE_TXDESCRDPTR(_i)\t(0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/\n#define IXGBE_PCIEECCCTL\t0x1106C\n#define IXGBE_RXWRPTR(_i)\t(0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/\n#define IXGBE_RXUSED(_i)\t(0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/\n#define IXGBE_RXRDPTR(_i)\t(0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/\n#define IXGBE_RXRDWRPTR(_i)\t(0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/\n#define IXGBE_TXWRPTR(_i)\t(0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/\n#define IXGBE_TXUSED(_i)\t(0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/\n#define IXGBE_TXRDPTR(_i)\t(0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/\n#define IXGBE_TXRDWRPTR(_i)\t(0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/\n#define IXGBE_PCIEECCCTL0\t0x11100\n#define IXGBE_PCIEECCCTL1\t0x11104\n#define IXGBE_RXDBUECC\t\t0x03F70\n#define IXGBE_TXDBUECC\t\t0x0CF70\n#define IXGBE_RXDBUEST\t\t0x03F74\n#define IXGBE_TXDBUEST\t\t0x0CF74\n#define IXGBE_PBTXECC\t\t0x0C300\n#define IXGBE_PBRXECC\t\t0x03300\n#define IXGBE_GHECCR\t\t0x110B0\n\n/* MAC Registers */\n#define IXGBE_PCS1GCFIG\t\t0x04200\n#define IXGBE_PCS1GLCTL\t\t0x04208\n#define IXGBE_PCS1GLSTA\t\t0x0420C\n#define IXGBE_PCS1GDBG0\t\t0x04210\n#define IXGBE_PCS1GDBG1\t\t0x04214\n#define IXGBE_PCS1GANA\t\t0x04218\n#define IXGBE_PCS1GANLP\t\t0x0421C\n#define IXGBE_PCS1GANNP\t\t0x04220\n#define IXGBE_PCS1GANLPNP\t0x04224\n#define IXGBE_HLREG0\t\t0x04240\n#define IXGBE_HLREG1\t\t0x04244\n#define IXGBE_PAP\t\t0x04248\n#define IXGBE_MACA\t\t0x0424C\n#define IXGBE_APAE\t\t0x04250\n#define IXGBE_ARD\t\t0x04254\n#define IXGBE_AIS\t\t0x04258\n#define IXGBE_MSCA\t\t0x0425C\n#define IXGBE_MSRWD\t\t0x04260\n#define IXGBE_MLADD\t\t0x04264\n#define IXGBE_MHADD\t\t0x04268\n#define IXGBE_MAXFRS\t\t0x04268\n#define IXGBE_TREG\t\t0x0426C\n#define IXGBE_PCSS1\t\t0x04288\n#define IXGBE_PCSS2\t\t0x0428C\n#define IXGBE_XPCSS\t\t0x04290\n#define IXGBE_MFLCN\t\t0x04294\n#define IXGBE_SERDESC\t\t0x04298\n#define IXGBE_MACS\t\t0x0429C\n#define IXGBE_AUTOC\t\t0x042A0\n#define IXGBE_LINKS\t\t0x042A4\n#define IXGBE_LINKS2\t\t0x04324\n#define IXGBE_AUTOC2\t\t0x042A8\n#define IXGBE_AUTOC3\t\t0x042AC\n#define IXGBE_ANLP1\t\t0x042B0\n#define IXGBE_ANLP2\t\t0x042B4\n#define IXGBE_MACC\t\t0x04330\n#define IXGBE_ATLASCTL\t\t0x04800\n#define IXGBE_MMNGC\t\t0x042D0\n#define IXGBE_ANLPNP1\t\t0x042D4\n#define IXGBE_ANLPNP2\t\t0x042D8\n#define IXGBE_KRPCSFC\t\t0x042E0\n#define IXGBE_KRPCSS\t\t0x042E4\n#define IXGBE_FECS1\t\t0x042E8\n#define IXGBE_FECS2\t\t0x042EC\n#define IXGBE_SMADARCTL\t\t0x14F10\n#define IXGBE_MPVC\t\t0x04318\n#define IXGBE_SGMIIC\t\t0x04314\n\n/* Statistics Registers */\n#define IXGBE_RXNFGPC\t\t0x041B0\n#define IXGBE_RXNFGBCL\t\t0x041B4\n#define IXGBE_RXNFGBCH\t\t0x041B8\n#define IXGBE_RXDGPC\t\t0x02F50\n#define IXGBE_RXDGBCL\t\t0x02F54\n#define IXGBE_RXDGBCH\t\t0x02F58\n#define IXGBE_RXDDGPC\t\t0x02F5C\n#define IXGBE_RXDDGBCL\t\t0x02F60\n#define IXGBE_RXDDGBCH\t\t0x02F64\n#define IXGBE_RXLPBKGPC\t\t0x02F68\n#define IXGBE_RXLPBKGBCL\t0x02F6C\n#define IXGBE_RXLPBKGBCH\t0x02F70\n#define IXGBE_RXDLPBKGPC\t0x02F74\n#define IXGBE_RXDLPBKGBCL\t0x02F78\n#define IXGBE_RXDLPBKGBCH\t0x02F7C\n#define IXGBE_TXDGPC\t\t0x087A0\n#define IXGBE_TXDGBCL\t\t0x087A4\n#define IXGBE_TXDGBCH\t\t0x087A8\n\n#define IXGBE_RXDSTATCTRL\t0x02F40\n\n/* Copper Pond 2 link timeout */\n#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50\n\n/* Omer CORECTL */\n#define IXGBE_CORECTL\t\t\t0x014F00\n/* BARCTRL */\n#define IXGBE_BARCTRL\t\t\t0x110F4\n#define IXGBE_BARCTRL_FLSIZE\t\t0x0700\n#define IXGBE_BARCTRL_FLSIZE_SHIFT\t8\n#define IXGBE_BARCTRL_CSRSIZE\t\t0x2000\n\n/* RSCCTL Bit Masks */\n#define IXGBE_RSCCTL_RSCEN\t0x01\n#define IXGBE_RSCCTL_MAXDESC_1\t0x00\n#define IXGBE_RSCCTL_MAXDESC_4\t0x04\n#define IXGBE_RSCCTL_MAXDESC_8\t0x08\n#define IXGBE_RSCCTL_MAXDESC_16\t0x0C\n#define IXGBE_RSCCTL_TS_DIS\t0x02\n\n/* RSCDBU Bit Masks */\n#define IXGBE_RSCDBU_RSCSMALDIS_MASK\t0x0000007F\n#define IXGBE_RSCDBU_RSCACKDIS\t\t0x00000080\n\n/* RDRXCTL Bit Masks */\n#define IXGBE_RDRXCTL_RDMTS_1_2\t\t0x00000000 /* Rx Desc Min THLD Size */\n#define IXGBE_RDRXCTL_CRCSTRIP\t\t0x00000002 /* CRC Strip */\n#define IXGBE_RDRXCTL_PSP\t\t0x00000004 /* Pad Small Packet */\n#define IXGBE_RDRXCTL_MVMEN\t\t0x00000020\n#define IXGBE_RDRXCTL_RSC_PUSH_DIS\t0x00000020\n#define IXGBE_RDRXCTL_DMAIDONE\t\t0x00000008 /* DMA init cycle done */\n#define IXGBE_RDRXCTL_RSC_PUSH\t\t0x00000080\n#define IXGBE_RDRXCTL_AGGDIS\t\t0x00010000 /* Aggregation disable */\n#define IXGBE_RDRXCTL_RSCFRSTSIZE\t0x003E0000 /* RSC First packet size */\n#define IXGBE_RDRXCTL_RSCLLIDIS\t\t0x00800000 /* Disable RSC compl on LLI*/\n#define IXGBE_RDRXCTL_RSCACKC\t\t0x02000000 /* must set 1 when RSC ena */\n#define IXGBE_RDRXCTL_FCOE_WRFIX\t0x04000000 /* must set 1 when RSC ena */\n#define IXGBE_RDRXCTL_MBINTEN\t\t0x10000000\n#define IXGBE_RDRXCTL_MDP_EN\t\t0x20000000\n\n/* RQTC Bit Masks and Shifts */\n#define IXGBE_RQTC_SHIFT_TC(_i)\t((_i) * 4)\n#define IXGBE_RQTC_TC0_MASK\t(0x7 << 0)\n#define IXGBE_RQTC_TC1_MASK\t(0x7 << 4)\n#define IXGBE_RQTC_TC2_MASK\t(0x7 << 8)\n#define IXGBE_RQTC_TC3_MASK\t(0x7 << 12)\n#define IXGBE_RQTC_TC4_MASK\t(0x7 << 16)\n#define IXGBE_RQTC_TC5_MASK\t(0x7 << 20)\n#define IXGBE_RQTC_TC6_MASK\t(0x7 << 24)\n#define IXGBE_RQTC_TC7_MASK\t(0x7 << 28)\n\n/* PSRTYPE.RQPL Bit masks and shift */\n#define IXGBE_PSRTYPE_RQPL_MASK\t\t0x7\n#define IXGBE_PSRTYPE_RQPL_SHIFT\t29\n\n/* CTRL Bit Masks */\n#define IXGBE_CTRL_GIO_DIS\t0x00000004 /* Global IO Master Disable bit */\n#define IXGBE_CTRL_LNK_RST\t0x00000008 /* Link Reset. Resets everything. */\n#define IXGBE_CTRL_RST\t\t0x04000000 /* Reset (SW) */\n#define IXGBE_CTRL_RST_MASK\t(IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)\n\n/* FACTPS */\n#define IXGBE_FACTPS_MNGCG\t0x20000000 /* Manageblility Clock Gated */\n#define IXGBE_FACTPS_LFS\t0x40000000 /* LAN Function Select */\n\n/* MHADD Bit Masks */\n#define IXGBE_MHADD_MFS_MASK\t0xFFFF0000\n#define IXGBE_MHADD_MFS_SHIFT\t16\n\n/* Extended Device Control */\n#define IXGBE_CTRL_EXT_PFRSTD\t0x00004000 /* Physical Function Reset Done */\n#define IXGBE_CTRL_EXT_NS_DIS\t0x00010000 /* No Snoop disable */\n#define IXGBE_CTRL_EXT_RO_DIS\t0x00020000 /* Relaxed Ordering disable */\n#define IXGBE_CTRL_EXT_DRV_LOAD\t0x10000000 /* Driver loaded bit for FW */\n\n/* Direct Cache Access (DCA) definitions */\n#define IXGBE_DCA_CTRL_DCA_ENABLE\t0x00000000 /* DCA Enable */\n#define IXGBE_DCA_CTRL_DCA_DISABLE\t0x00000001 /* DCA Disable */\n\n#define IXGBE_DCA_CTRL_DCA_MODE_CB1\t0x00 /* DCA Mode CB1 */\n#define IXGBE_DCA_CTRL_DCA_MODE_CB2\t0x02 /* DCA Mode CB2 */\n\n#define IXGBE_DCA_RXCTRL_CPUID_MASK\t0x0000001F /* Rx CPUID Mask */\n#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599\t0xFF000000 /* Rx CPUID Mask */\n#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599\t24 /* Rx CPUID Shift */\n#define IXGBE_DCA_RXCTRL_DESC_DCA_EN\t(1 << 5) /* Rx Desc enable */\n#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN\t(1 << 6) /* Rx Desc header ena */\n#define IXGBE_DCA_RXCTRL_DATA_DCA_EN\t(1 << 7) /* Rx Desc payload ena */\n#define IXGBE_DCA_RXCTRL_DESC_RRO_EN\t(1 << 9) /* Rx rd Desc Relax Order */\n#define IXGBE_DCA_RXCTRL_DATA_WRO_EN\t(1 << 13) /* Rx wr data Relax Order */\n#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN\t(1 << 15) /* Rx wr header RO */\n\n#define IXGBE_DCA_TXCTRL_CPUID_MASK\t0x0000001F /* Tx CPUID Mask */\n#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599\t0xFF000000 /* Tx CPUID Mask */\n#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599\t24 /* Tx CPUID Shift */\n#define IXGBE_DCA_TXCTRL_DESC_DCA_EN\t(1 << 5) /* DCA Tx Desc enable */\n#define IXGBE_DCA_TXCTRL_DESC_RRO_EN\t(1 << 9) /* Tx rd Desc Relax Order */\n#define IXGBE_DCA_TXCTRL_DESC_WRO_EN\t(1 << 11) /* Tx Desc writeback RO bit */\n#define IXGBE_DCA_TXCTRL_DATA_RRO_EN\t(1 << 13) /* Tx rd data Relax Order */\n#define IXGBE_DCA_MAX_QUEUES_82598\t16 /* DCA regs only on 16 queues */\n\n/* MSCA Bit Masks */\n#define IXGBE_MSCA_NP_ADDR_MASK\t\t0x0000FFFF /* MDI Addr (new prot) */\n#define IXGBE_MSCA_NP_ADDR_SHIFT\t0\n#define IXGBE_MSCA_DEV_TYPE_MASK\t0x001F0000 /* Dev Type (new prot) */\n#define IXGBE_MSCA_DEV_TYPE_SHIFT\t16 /* Register Address (old prot */\n#define IXGBE_MSCA_PHY_ADDR_MASK\t0x03E00000 /* PHY Address mask */\n#define IXGBE_MSCA_PHY_ADDR_SHIFT\t21 /* PHY Address shift*/\n#define IXGBE_MSCA_OP_CODE_MASK\t\t0x0C000000 /* OP CODE mask */\n#define IXGBE_MSCA_OP_CODE_SHIFT\t26 /* OP CODE shift */\n#define IXGBE_MSCA_ADDR_CYCLE\t\t0x00000000 /* OP CODE 00 (addr cycle) */\n#define IXGBE_MSCA_WRITE\t\t0x04000000 /* OP CODE 01 (wr) */\n#define IXGBE_MSCA_READ\t\t\t0x0C000000 /* OP CODE 11 (rd) */\n#define IXGBE_MSCA_READ_AUTOINC\t\t0x08000000 /* OP CODE 10 (rd auto inc)*/\n#define IXGBE_MSCA_ST_CODE_MASK\t\t0x30000000 /* ST Code mask */\n#define IXGBE_MSCA_ST_CODE_SHIFT\t28 /* ST Code shift */\n#define IXGBE_MSCA_NEW_PROTOCOL\t\t0x00000000 /* ST CODE 00 (new prot) */\n#define IXGBE_MSCA_OLD_PROTOCOL\t\t0x10000000 /* ST CODE 01 (old prot) */\n#define IXGBE_MSCA_MDI_COMMAND\t\t0x40000000 /* Initiate MDI command */\n#define IXGBE_MSCA_MDI_IN_PROG_EN\t0x80000000 /* MDI in progress ena */\n\n/* MSRWD bit masks */\n#define IXGBE_MSRWD_WRITE_DATA_MASK\t0x0000FFFF\n#define IXGBE_MSRWD_WRITE_DATA_SHIFT\t0\n#define IXGBE_MSRWD_READ_DATA_MASK\t0xFFFF0000\n#define IXGBE_MSRWD_READ_DATA_SHIFT\t16\n\n/* Atlas registers */\n#define IXGBE_ATLAS_PDN_LPBK\t\t0x24\n#define IXGBE_ATLAS_PDN_10G\t\t0xB\n#define IXGBE_ATLAS_PDN_1G\t\t0xC\n#define IXGBE_ATLAS_PDN_AN\t\t0xD\n\n/* Atlas bit masks */\n#define IXGBE_ATLASCTL_WRITE_CMD\t0x00010000\n#define IXGBE_ATLAS_PDN_TX_REG_EN\t0x10\n#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL\t0xF0\n#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL\t0xF0\n#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL\t0xF0\n\n/* Omer bit masks */\n#define IXGBE_CORECTL_WRITE_CMD\t\t0x00010000\n\n/* Device Type definitions for new protocol MDIO commands */\n#define IXGBE_MDIO_PMA_PMD_DEV_TYPE\t\t0x1\n#define IXGBE_MDIO_PCS_DEV_TYPE\t\t\t0x3\n#define IXGBE_MDIO_PHY_XS_DEV_TYPE\t\t0x4\n#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE\t\t0x7\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE\t0x1E /* Device 30 */\n#define IXGBE_TWINAX_DEV\t\t\t1\n\n#define IXGBE_MDIO_COMMAND_TIMEOUT\t100 /* PHY Timeout for 1 GB mode */\n\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL\t\t0x0 /* VS1 Ctrl Reg */\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS\t\t0x1 /* VS1 Status Reg */\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS\t0x0008 /* 1 = Link Up */\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS\t0x0010 /* 0-10G, 1-1G */\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED\t\t0x0018\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED\t\t0x0010\n\n#define IXGBE_MDIO_AUTO_NEG_CONTROL\t0x0 /* AUTO_NEG Control Reg */\n#define IXGBE_MDIO_AUTO_NEG_STATUS\t0x1 /* AUTO_NEG Status Reg */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT\t0xC800 /* AUTO_NEG Vendor Status Reg */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */\n#define IXGBE_MDIO_AUTO_NEG_VEN_LSC\t0x1 /* AUTO_NEG Vendor Tx LSC */\n#define IXGBE_MDIO_AUTO_NEG_ADVT\t0x10 /* AUTO_NEG Advt Reg */\n#define IXGBE_MDIO_AUTO_NEG_LP\t\t0x13 /* AUTO_NEG LP Status Reg */\n#define IXGBE_MDIO_AUTO_NEG_EEE_ADVT\t0x3C /* AUTO_NEG EEE Advt Reg */\n#define IXGBE_AUTO_NEG_10GBASE_EEE_ADVT\t0x8 /* AUTO NEG EEE 10GBaseT Advt */\n#define IXGBE_AUTO_NEG_1000BASE_EEE_ADVT 0x4 /* AUTO NEG EEE 1000BaseT Advt */\n#define IXGBE_AUTO_NEG_100BASE_EEE_ADVT\t0x2 /* AUTO NEG EEE 100BaseT Advt */\n#define IXGBE_MDIO_PHY_XS_CONTROL\t0x0 /* PHY_XS Control Reg */\n#define IXGBE_MDIO_PHY_XS_RESET\t\t0x8000 /* PHY_XS Reset */\n#define IXGBE_MDIO_PHY_ID_HIGH\t\t0x2 /* PHY ID High Reg*/\n#define IXGBE_MDIO_PHY_ID_LOW\t\t0x3 /* PHY ID Low Reg*/\n#define IXGBE_MDIO_PHY_SPEED_ABILITY\t0x4 /* Speed Ability Reg */\n#define IXGBE_MDIO_PHY_SPEED_10G\t0x0001 /* 10G capable */\n#define IXGBE_MDIO_PHY_SPEED_1G\t\t0x0010 /* 1G capable */\n#define IXGBE_MDIO_PHY_SPEED_100M\t0x0020 /* 100M capable */\n#define IXGBE_MDIO_PHY_EXT_ABILITY\t0xB /* Ext Ability Reg */\n#define IXGBE_MDIO_PHY_10GBASET_ABILITY\t\t0x0004 /* 10GBaseT capable */\n#define IXGBE_MDIO_PHY_1000BASET_ABILITY\t0x0020 /* 1000BaseT capable */\n#define IXGBE_MDIO_PHY_100BASETX_ABILITY\t0x0080 /* 100BaseTX capable */\n#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE\t0x0800 /* Set low power mode */\n#define IXGBE_AUTO_NEG_LP_STATUS\t0xE820 /* AUTO NEG Rx LP Status Reg */\n#define IXGBE_AUTO_NEG_LP_1000BASE_CAP\t0x8000 /* AUTO NEG Rx LP 1000BaseT Cap */\n#define IXGBE_AUTO_NEG_LP_10GBASE_CAP\t0x0800 /* AUTO NEG Rx LP 10GBaseT Cap */\n#define IXGBE_AUTO_NEG_10GBASET_STAT\t0x0021 /* AUTO NEG 10G BaseT Stat */\n\n#define IXGBE_MDIO_TX_VENDOR_ALARMS_3\t\t0xCC02 /* Vendor Alarms 3 Reg */\n#define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK\t0x3 /* PHY Reset Complete Mask */\n#define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */\n#define IXGBE_MDIO_POWER_UP_STALL\t\t0x8000 /* Power Up Stall */\n#define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK\t0xFF00 /* int std mask */\n#define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG\t0xFC00 /* chip std int flag */\n#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK\t0xFF01 /* int chip-wide mask */\n#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG\t0xFC01 /* int chip-wide mask */\n#define IXGBE_MDIO_GLOBAL_ALARM_1\t\t0xCC00 /* Global alarm 1 */\n#define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL\t0x4000 /* high temp failure */\n#define IXGBE_MDIO_GLOBAL_INT_MASK\t\t0xD400 /* Global int mask */\n#define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN\t0x1000 /* autoneg vendor alarm int enable */\n#define IXGBE_MDIO_GLOBAL_ALARM_1_INT\t\t0x4 /* int in Global alarm 1 */\n#define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN\t0x1 /* vendor alarm int enable */\n#define IXGBE_MDIO_GLOBAL_STD_ALM2_INT\t\t0x200 /* vendor alarm2 int mask */\n#define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN\t0x4000 /* int high temp enable */\n#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR\t0x0000 /* PMA/PMD Control Reg */\n#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR\t0xC30A /* PHY_XS SDA/SCL Addr Reg */\n#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA\t0xC30B /* PHY_XS SDA/SCL Data Reg */\n#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT\t0xC30C /* PHY_XS SDA/SCL Status Reg */\n#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */\n#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */\n#define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */\n#define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */\n\n#define IXGBE_PCRC8ECL\t\t0x0E810 /* PCR CRC-8 Error Count Lo */\n#define IXGBE_PCRC8ECH\t\t0x0E811 /* PCR CRC-8 Error Count Hi */\n#define IXGBE_PCRC8ECH_MASK\t0x1F\n#define IXGBE_LDPCECL\t\t0x0E820 /* PCR Uncorrected Error Count Lo */\n#define IXGBE_LDPCECH\t\t0x0E821 /* PCR Uncorrected Error Count Hi */\n\n/* MII clause 22/28 definitions */\n#define IXGBE_MDIO_PHY_LOW_POWER_MODE\t0x0800\n\n#define IXGBE_MDIO_XENPAK_LASI_STATUS\t\t0x9005 /* XENPAK LASI Status register*/\n#define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM\t0x1 /* Link Status Alarm change */\n\n#define IXGBE_MDIO_AUTO_NEG_LINK_STATUS\t\t0x4 /* Indicates if link is up */\n\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK\t0x7 /* Speed/Duplex Mask */\n#define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK\t\t0x6 /* Speed Mask */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF\t0x0 /* 10Mb/s Half Duplex */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL\t0x1 /* 10Mb/s Full Duplex */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF\t0x2 /* 100Mb/s Half Duplex */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL\t0x3 /* 100Mb/s Full Duplex */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF\t0x4 /* 1Gb/s Half Duplex */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL\t0x5 /* 1Gb/s Full Duplex */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF\t0x6 /* 10Gb/s Half Duplex */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL\t0x7 /* 10Gb/s Full Duplex */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB\t\t0x4 /* 1Gb/s */\n#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB\t\t0x6 /* 10Gb/s */\n\n#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG\t0x20 /* 10G Control Reg */\n#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */\n#define IXGBE_MII_AUTONEG_XNP_TX_REG\t\t0x17 /* 1G XNP Transmit */\n#define IXGBE_MII_AUTONEG_ADVERTISE_REG\t\t0x10 /* 100M Advertisement */\n#define IXGBE_MII_10GBASE_T_ADVERTISE\t\t0x1000 /* full duplex, bit:12*/\n#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX\t0x4000 /* full duplex, bit:14*/\n#define IXGBE_MII_1GBASE_T_ADVERTISE\t\t0x8000 /* full duplex, bit:15*/\n#define IXGBE_MII_2_5GBASE_T_ADVERTISE\t\t0x0400\n#define IXGBE_MII_5GBASE_T_ADVERTISE\t\t0x0800\n#define IXGBE_MII_100BASE_T_ADVERTISE\t\t0x0100 /* full duplex, bit:8 */\n#define IXGBE_MII_100BASE_T_ADVERTISE_HALF\t0x0080 /* half duplex, bit:7 */\n#define IXGBE_MII_RESTART\t\t\t0x200\n#define IXGBE_MII_AUTONEG_COMPLETE\t\t0x20\n#define IXGBE_MII_AUTONEG_LINK_UP\t\t0x04\n#define IXGBE_MII_AUTONEG_REG\t\t\t0x0\n\n#define IXGBE_PHY_REVISION_MASK\t\t0xFFFFFFF0\n#define IXGBE_MAX_PHY_ADDR\t\t32\n\n/* PHY IDs*/\n#define TN1010_PHY_ID\t0x00A19410\n#define TNX_FW_REV\t0xB\n#define X540_PHY_ID\t0x01540200\n#define X550_PHY_ID1\t0x01540220\n#define X550_PHY_ID2\t0x01540223\n#define X550_PHY_ID3\t0x01540221\n#define X557_PHY_ID\t0x01540240\n#define AQ_FW_REV\t0x20\n#define QT2022_PHY_ID\t0x0043A400\n#define ATH_PHY_ID\t0x03429050\n\n/* PHY Types */\n#define IXGBE_M88E1145_E_PHY_ID\t0x01410CD0\n\n/* Special PHY Init Routine */\n#define IXGBE_PHY_INIT_OFFSET_NL\t0x002B\n#define IXGBE_PHY_INIT_END_NL\t\t0xFFFF\n#define IXGBE_CONTROL_MASK_NL\t\t0xF000\n#define IXGBE_DATA_MASK_NL\t\t0x0FFF\n#define IXGBE_CONTROL_SHIFT_NL\t\t12\n#define IXGBE_DELAY_NL\t\t\t0\n#define IXGBE_DATA_NL\t\t\t1\n#define IXGBE_CONTROL_NL\t\t0x000F\n#define IXGBE_CONTROL_EOL_NL\t\t0x0FFF\n#define IXGBE_CONTROL_SOL_NL\t\t0x0000\n\n/* General purpose Interrupt Enable */\n#define IXGBE_SDP0_GPIEN\t0x00000001 /* SDP0 */\n#define IXGBE_SDP1_GPIEN\t0x00000002 /* SDP1 */\n#define IXGBE_SDP2_GPIEN\t0x00000004 /* SDP2 */\n#define IXGBE_SDP0_GPIEN_X540\t0x00000002 /* SDP0 on X540 and X550 */\n#define IXGBE_SDP1_GPIEN_X540\t0x00000004 /* SDP1 on X540 and X550 */\n#define IXGBE_SDP2_GPIEN_X540\t0x00000008 /* SDP2 on X540 and X550 */\n#define IXGBE_SDP0_GPIEN_X550\tIXGBE_SDP0_GPIEN_X540\n#define IXGBE_SDP1_GPIEN_X550\tIXGBE_SDP1_GPIEN_X540\n#define IXGBE_SDP2_GPIEN_X550\tIXGBE_SDP2_GPIEN_X540\n#define IXGBE_SDP0_GPIEN_X550EM_x\tIXGBE_SDP0_GPIEN_X540\n#define IXGBE_SDP1_GPIEN_X550EM_x\tIXGBE_SDP1_GPIEN_X540\n#define IXGBE_SDP2_GPIEN_X550EM_x\tIXGBE_SDP2_GPIEN_X540\n#define IXGBE_SDP0_GPIEN_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), SDP0_GPIEN)\n#define IXGBE_SDP1_GPIEN_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), SDP1_GPIEN)\n#define IXGBE_SDP2_GPIEN_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), SDP2_GPIEN)\n\n#define IXGBE_GPIE_MSIX_MODE\t0x00000010 /* MSI-X mode */\n#define IXGBE_GPIE_OCD\t\t0x00000020 /* Other Clear Disable */\n#define IXGBE_GPIE_EIMEN\t0x00000040 /* Immediate Interrupt Enable */\n#define IXGBE_GPIE_EIAME\t0x40000000\n#define IXGBE_GPIE_PBA_SUPPORT\t0x80000000\n#define IXGBE_GPIE_RSC_DELAY_SHIFT\t11\n#define IXGBE_GPIE_VTMODE_MASK\t0x0000C000 /* VT Mode Mask */\n#define IXGBE_GPIE_VTMODE_16\t0x00004000 /* 16 VFs 8 queues per VF */\n#define IXGBE_GPIE_VTMODE_32\t0x00008000 /* 32 VFs 4 queues per VF */\n#define IXGBE_GPIE_VTMODE_64\t0x0000C000 /* 64 VFs 2 queues per VF */\n\n/* Packet Buffer Initialization */\n#define IXGBE_MAX_PACKET_BUFFERS\t8\n\n#define IXGBE_TXPBSIZE_20KB\t0x00005000 /* 20KB Packet Buffer */\n#define IXGBE_TXPBSIZE_40KB\t0x0000A000 /* 40KB Packet Buffer */\n#define IXGBE_RXPBSIZE_48KB\t0x0000C000 /* 48KB Packet Buffer */\n#define IXGBE_RXPBSIZE_64KB\t0x00010000 /* 64KB Packet Buffer */\n#define IXGBE_RXPBSIZE_80KB\t0x00014000 /* 80KB Packet Buffer */\n#define IXGBE_RXPBSIZE_128KB\t0x00020000 /* 128KB Packet Buffer */\n#define IXGBE_RXPBSIZE_MAX\t0x00080000 /* 512KB Packet Buffer */\n#define IXGBE_TXPBSIZE_MAX\t0x00028000 /* 160KB Packet Buffer */\n\n#define IXGBE_TXPKT_SIZE_MAX\t0xA /* Max Tx Packet size */\n#define IXGBE_MAX_PB\t\t8\n\n/* Packet buffer allocation strategies */\nenum {\n\tPBA_STRATEGY_EQUAL\t= 0, /* Distribute PB space equally */\n#define PBA_STRATEGY_EQUAL\tPBA_STRATEGY_EQUAL\n\tPBA_STRATEGY_WEIGHTED\t= 1, /* Weight front half of TCs */\n#define PBA_STRATEGY_WEIGHTED\tPBA_STRATEGY_WEIGHTED\n};\n\n/* Transmit Flow Control status */\n#define IXGBE_TFCS_TXOFF\t0x00000001\n#define IXGBE_TFCS_TXOFF0\t0x00000100\n#define IXGBE_TFCS_TXOFF1\t0x00000200\n#define IXGBE_TFCS_TXOFF2\t0x00000400\n#define IXGBE_TFCS_TXOFF3\t0x00000800\n#define IXGBE_TFCS_TXOFF4\t0x00001000\n#define IXGBE_TFCS_TXOFF5\t0x00002000\n#define IXGBE_TFCS_TXOFF6\t0x00004000\n#define IXGBE_TFCS_TXOFF7\t0x00008000\n\n/* TCP Timer */\n#define IXGBE_TCPTIMER_KS\t\t0x00000100\n#define IXGBE_TCPTIMER_COUNT_ENABLE\t0x00000200\n#define IXGBE_TCPTIMER_COUNT_FINISH\t0x00000400\n#define IXGBE_TCPTIMER_LOOP\t\t0x00000800\n#define IXGBE_TCPTIMER_DURATION_MASK\t0x000000FF\n\n/* HLREG0 Bit Masks */\n#define IXGBE_HLREG0_TXCRCEN\t\t0x00000001 /* bit 0 */\n#define IXGBE_HLREG0_RXCRCSTRP\t\t0x00000002 /* bit 1 */\n#define IXGBE_HLREG0_JUMBOEN\t\t0x00000004 /* bit 2 */\n#define IXGBE_HLREG0_TXPADEN\t\t0x00000400 /* bit 10 */\n#define IXGBE_HLREG0_TXPAUSEEN\t\t0x00001000 /* bit 12 */\n#define IXGBE_HLREG0_RXPAUSEEN\t\t0x00004000 /* bit 14 */\n#define IXGBE_HLREG0_LPBK\t\t0x00008000 /* bit 15 */\n#define IXGBE_HLREG0_MDCSPD\t\t0x00010000 /* bit 16 */\n#define IXGBE_HLREG0_CONTMDC\t\t0x00020000 /* bit 17 */\n#define IXGBE_HLREG0_CTRLFLTR\t\t0x00040000 /* bit 18 */\n#define IXGBE_HLREG0_PREPEND\t\t0x00F00000 /* bits 20-23 */\n#define IXGBE_HLREG0_PRIPAUSEEN\t\t0x01000000 /* bit 24 */\n#define IXGBE_HLREG0_RXPAUSERECDA\t0x06000000 /* bits 25-26 */\n#define IXGBE_HLREG0_RXLNGTHERREN\t0x08000000 /* bit 27 */\n#define IXGBE_HLREG0_RXPADSTRIPEN\t0x10000000 /* bit 28 */\n\n/* VMD_CTL bitmasks */\n#define IXGBE_VMD_CTL_VMDQ_EN\t\t0x00000001\n#define IXGBE_VMD_CTL_VMDQ_FILTER\t0x00000002\n\n/* VT_CTL bitmasks */\n#define IXGBE_VT_CTL_DIS_DEFPL\t\t0x20000000 /* disable default pool */\n#define IXGBE_VT_CTL_REPLEN\t\t0x40000000 /* replication enabled */\n#define IXGBE_VT_CTL_VT_ENABLE\t\t0x00000001 /* Enable VT Mode */\n#define IXGBE_VT_CTL_POOL_SHIFT\t\t7\n#define IXGBE_VT_CTL_POOL_MASK\t\t(0x3F << IXGBE_VT_CTL_POOL_SHIFT)\n\n/* VMOLR bitmasks */\n#define IXGBE_VMOLR_AUPE\t0x01000000 /* accept untagged packets */\n#define IXGBE_VMOLR_ROMPE\t0x02000000 /* accept packets in MTA tbl */\n#define IXGBE_VMOLR_ROPE\t0x04000000 /* accept packets in UC tbl */\n#define IXGBE_VMOLR_BAM\t\t0x08000000 /* accept broadcast packets */\n#define IXGBE_VMOLR_MPE\t\t0x10000000 /* multicast promiscuous */\n\n/* VFRE bitmask */\n#define IXGBE_VFRE_ENABLE_ALL\t0xFFFFFFFF\n\n#define IXGBE_VF_INIT_TIMEOUT\t200 /* Number of retries to clear RSTI */\n\n/* RDHMPN and TDHMPN bitmasks */\n#define IXGBE_RDHMPN_RDICADDR\t\t0x007FF800\n#define IXGBE_RDHMPN_RDICRDREQ\t\t0x00800000\n#define IXGBE_RDHMPN_RDICADDR_SHIFT\t11\n#define IXGBE_TDHMPN_TDICADDR\t\t0x003FF800\n#define IXGBE_TDHMPN_TDICRDREQ\t\t0x00800000\n#define IXGBE_TDHMPN_TDICADDR_SHIFT\t11\n\n#define IXGBE_RDMAM_MEM_SEL_SHIFT\t\t13\n#define IXGBE_RDMAM_DWORD_SHIFT\t\t\t9\n#define IXGBE_RDMAM_DESC_COMP_FIFO\t\t1\n#define IXGBE_RDMAM_DFC_CMD_FIFO\t\t2\n#define IXGBE_RDMAM_RSC_HEADER_ADDR\t\t3\n#define IXGBE_RDMAM_TCN_STATUS_RAM\t\t4\n#define IXGBE_RDMAM_WB_COLL_FIFO\t\t5\n#define IXGBE_RDMAM_QSC_CNT_RAM\t\t\t6\n#define IXGBE_RDMAM_QSC_FCOE_RAM\t\t7\n#define IXGBE_RDMAM_QSC_QUEUE_CNT\t\t8\n#define IXGBE_RDMAM_QSC_QUEUE_RAM\t\t0xA\n#define IXGBE_RDMAM_QSC_RSC_RAM\t\t\t0xB\n#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE\t\t135\n#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT\t\t4\n#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE\t\t48\n#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT\t\t7\n#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE\t32\n#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT\t4\n#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE\t256\n#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT\t9\n#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE\t\t8\n#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT\t\t4\n#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE\t\t64\n#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT\t\t4\n#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE\t\t512\n#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT\t\t5\n#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE\t\t32\n#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT\t\t4\n#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE\t\t128\n#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT\t\t8\n#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE\t\t32\n#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT\t\t8\n\n#define IXGBE_TXDESCIC_READY\t0x80000000\n\n/* Receive Checksum Control */\n#define IXGBE_RXCSUM_IPPCSE\t0x00001000 /* IP payload checksum enable */\n#define IXGBE_RXCSUM_PCSD\t0x00002000 /* packet checksum disabled */\n\n/* FCRTL Bit Masks */\n#define IXGBE_FCRTL_XONE\t0x80000000 /* XON enable */\n#define IXGBE_FCRTH_FCEN\t0x80000000 /* Packet buffer fc enable */\n\n/* PAP bit masks*/\n#define IXGBE_PAP_TXPAUSECNT_MASK\t0x0000FFFF /* Pause counter mask */\n\n/* RMCS Bit Masks */\n#define IXGBE_RMCS_RRM\t\t\t0x00000002 /* Rx Recycle Mode enable */\n/* Receive Arbitration Control: 0 Round Robin, 1 DFP */\n#define IXGBE_RMCS_RAC\t\t\t0x00000004\n/* Deficit Fixed Prio ena */\n#define IXGBE_RMCS_DFP\t\t\tIXGBE_RMCS_RAC\n#define IXGBE_RMCS_TFCE_802_3X\t\t0x00000008 /* Tx Priority FC ena */\n#define IXGBE_RMCS_TFCE_PRIORITY\t0x00000010 /* Tx Priority FC ena */\n#define IXGBE_RMCS_ARBDIS\t\t0x00000040 /* Arbitration disable bit */\n\n/* FCCFG Bit Masks */\n#define IXGBE_FCCFG_TFCE_802_3X\t\t0x00000008 /* Tx link FC enable */\n#define IXGBE_FCCFG_TFCE_PRIORITY\t0x00000010 /* Tx priority FC enable */\n\n/* Interrupt register bitmasks */\n\n/* Extended Interrupt Cause Read */\n#define IXGBE_EICR_RTX_QUEUE\t0x0000FFFF /* RTx Queue Interrupt */\n#define IXGBE_EICR_FLOW_DIR\t0x00010000 /* FDir Exception */\n#define IXGBE_EICR_RX_MISS\t0x00020000 /* Packet Buffer Overrun */\n#define IXGBE_EICR_PCI\t\t0x00040000 /* PCI Exception */\n#define IXGBE_EICR_MAILBOX\t0x00080000 /* VF to PF Mailbox Interrupt */\n#define IXGBE_EICR_LSC\t\t0x00100000 /* Link Status Change */\n#define IXGBE_EICR_LINKSEC\t0x00200000 /* PN Threshold */\n#define IXGBE_EICR_MNG\t\t0x00400000 /* Manageability Event Interrupt */\n#define IXGBE_EICR_TS\t\t0x00800000 /* Thermal Sensor Event */\n#define IXGBE_EICR_TIMESYNC\t0x01000000 /* Timesync Event */\n#define IXGBE_EICR_GPI_SDP0\t0x01000000 /* Gen Purpose Interrupt on SDP0 */\n#define IXGBE_EICR_GPI_SDP1\t0x02000000 /* Gen Purpose Interrupt on SDP1 */\n#define IXGBE_EICR_GPI_SDP2\t0x04000000 /* Gen Purpose Interrupt on SDP2 */\n#define IXGBE_EICR_ECC\t\t0x10000000 /* ECC Error */\n#define IXGBE_EICR_GPI_SDP0_X540 0x02000000 /* Gen Purpose Interrupt on SDP0 */\n#define IXGBE_EICR_GPI_SDP1_X540 0x04000000 /* Gen Purpose Interrupt on SDP1 */\n#define IXGBE_EICR_GPI_SDP2_X540 0x08000000 /* Gen Purpose Interrupt on SDP2 */\n#define IXGBE_EICR_GPI_SDP0_X550\tIXGBE_EICR_GPI_SDP0_X540\n#define IXGBE_EICR_GPI_SDP1_X550\tIXGBE_EICR_GPI_SDP1_X540\n#define IXGBE_EICR_GPI_SDP2_X550\tIXGBE_EICR_GPI_SDP2_X540\n#define IXGBE_EICR_GPI_SDP0_X550EM_x\tIXGBE_EICR_GPI_SDP0_X540\n#define IXGBE_EICR_GPI_SDP1_X550EM_x\tIXGBE_EICR_GPI_SDP1_X540\n#define IXGBE_EICR_GPI_SDP2_X550EM_x\tIXGBE_EICR_GPI_SDP2_X540\n#define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), EICR_GPI_SDP0)\n#define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), EICR_GPI_SDP1)\n#define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), EICR_GPI_SDP2)\n\n#define IXGBE_EICR_PBUR\t\t0x10000000 /* Packet Buffer Handler Error */\n#define IXGBE_EICR_DHER\t\t0x20000000 /* Descriptor Handler Error */\n#define IXGBE_EICR_TCP_TIMER\t0x40000000 /* TCP Timer */\n#define IXGBE_EICR_OTHER\t0x80000000 /* Interrupt Cause Active */\n\n/* Extended Interrupt Cause Set */\n#define IXGBE_EICS_RTX_QUEUE\tIXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */\n#define IXGBE_EICS_FLOW_DIR\tIXGBE_EICR_FLOW_DIR /* FDir Exception */\n#define IXGBE_EICS_RX_MISS\tIXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */\n#define IXGBE_EICS_PCI\t\tIXGBE_EICR_PCI /* PCI Exception */\n#define IXGBE_EICS_MAILBOX\tIXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */\n#define IXGBE_EICS_LSC\t\tIXGBE_EICR_LSC /* Link Status Change */\n#define IXGBE_EICS_MNG\t\tIXGBE_EICR_MNG /* MNG Event Interrupt */\n#define IXGBE_EICS_TIMESYNC\tIXGBE_EICR_TIMESYNC /* Timesync Event */\n#define IXGBE_EICS_GPI_SDP0\tIXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */\n#define IXGBE_EICS_GPI_SDP1\tIXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */\n#define IXGBE_EICS_GPI_SDP2\tIXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */\n#define IXGBE_EICS_ECC\t\tIXGBE_EICR_ECC /* ECC Error */\n#define IXGBE_EICS_GPI_SDP0_BY_MAC(_hw)\tIXGBE_EICR_GPI_SDP0_BY_MAC(_hw)\n#define IXGBE_EICS_GPI_SDP1_BY_MAC(_hw)\tIXGBE_EICR_GPI_SDP1_BY_MAC(_hw)\n#define IXGBE_EICS_GPI_SDP2_BY_MAC(_hw)\tIXGBE_EICR_GPI_SDP2_BY_MAC(_hw)\n#define IXGBE_EICS_PBUR\t\tIXGBE_EICR_PBUR /* Pkt Buf Handler Err */\n#define IXGBE_EICS_DHER\t\tIXGBE_EICR_DHER /* Desc Handler Error */\n#define IXGBE_EICS_TCP_TIMER\tIXGBE_EICR_TCP_TIMER /* TCP Timer */\n#define IXGBE_EICS_OTHER\tIXGBE_EICR_OTHER /* INT Cause Active */\n\n/* Extended Interrupt Mask Set */\n#define IXGBE_EIMS_RTX_QUEUE\tIXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */\n#define IXGBE_EIMS_FLOW_DIR\tIXGBE_EICR_FLOW_DIR /* FDir Exception */\n#define IXGBE_EIMS_RX_MISS\tIXGBE_EICR_RX_MISS /* Packet Buffer Overrun */\n#define IXGBE_EIMS_PCI\t\tIXGBE_EICR_PCI /* PCI Exception */\n#define IXGBE_EIMS_MAILBOX\tIXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */\n#define IXGBE_EIMS_LSC\t\tIXGBE_EICR_LSC /* Link Status Change */\n#define IXGBE_EIMS_MNG\t\tIXGBE_EICR_MNG /* MNG Event Interrupt */\n#define IXGBE_EIMS_TS\t\tIXGBE_EICR_TS /* Thermal Sensor Event */\n#define IXGBE_EIMS_TIMESYNC\tIXGBE_EICR_TIMESYNC /* Timesync Event */\n#define IXGBE_EIMS_GPI_SDP0\tIXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */\n#define IXGBE_EIMS_GPI_SDP1\tIXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */\n#define IXGBE_EIMS_GPI_SDP2\tIXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */\n#define IXGBE_EIMS_ECC\t\tIXGBE_EICR_ECC /* ECC Error */\n#define IXGBE_EIMS_GPI_SDP0_BY_MAC(_hw)\tIXGBE_EICR_GPI_SDP0_BY_MAC(_hw)\n#define IXGBE_EIMS_GPI_SDP1_BY_MAC(_hw)\tIXGBE_EICR_GPI_SDP1_BY_MAC(_hw)\n#define IXGBE_EIMS_GPI_SDP2_BY_MAC(_hw)\tIXGBE_EICR_GPI_SDP2_BY_MAC(_hw)\n#define IXGBE_EIMS_PBUR\t\tIXGBE_EICR_PBUR /* Pkt Buf Handler Err */\n#define IXGBE_EIMS_DHER\t\tIXGBE_EICR_DHER /* Descr Handler Error */\n#define IXGBE_EIMS_TCP_TIMER\tIXGBE_EICR_TCP_TIMER /* TCP Timer */\n#define IXGBE_EIMS_OTHER\tIXGBE_EICR_OTHER /* INT Cause Active */\n\n/* Extended Interrupt Mask Clear */\n#define IXGBE_EIMC_RTX_QUEUE\tIXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */\n#define IXGBE_EIMC_FLOW_DIR\tIXGBE_EICR_FLOW_DIR /* FDir Exception */\n#define IXGBE_EIMC_RX_MISS\tIXGBE_EICR_RX_MISS /* Packet Buffer Overrun */\n#define IXGBE_EIMC_PCI\t\tIXGBE_EICR_PCI /* PCI Exception */\n#define IXGBE_EIMC_MAILBOX\tIXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */\n#define IXGBE_EIMC_LSC\t\tIXGBE_EICR_LSC /* Link Status Change */\n#define IXGBE_EIMC_MNG\t\tIXGBE_EICR_MNG /* MNG Event Interrupt */\n#define IXGBE_EIMC_TIMESYNC\tIXGBE_EICR_TIMESYNC /* Timesync Event */\n#define IXGBE_EIMC_GPI_SDP0\tIXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */\n#define IXGBE_EIMC_GPI_SDP1\tIXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */\n#define IXGBE_EIMC_GPI_SDP2\tIXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */\n#define IXGBE_EIMC_ECC\t\tIXGBE_EICR_ECC /* ECC Error */\n#define IXGBE_EIMC_GPI_SDP0_BY_MAC(_hw)\tIXGBE_EICR_GPI_SDP0_BY_MAC(_hw)\n#define IXGBE_EIMC_GPI_SDP1_BY_MAC(_hw)\tIXGBE_EICR_GPI_SDP1_BY_MAC(_hw)\n#define IXGBE_EIMC_GPI_SDP2_BY_MAC(_hw)\tIXGBE_EICR_GPI_SDP2_BY_MAC(_hw)\n#define IXGBE_EIMC_PBUR\t\tIXGBE_EICR_PBUR /* Pkt Buf Handler Err */\n#define IXGBE_EIMC_DHER\t\tIXGBE_EICR_DHER /* Desc Handler Err */\n#define IXGBE_EIMC_TCP_TIMER\tIXGBE_EICR_TCP_TIMER /* TCP Timer */\n#define IXGBE_EIMC_OTHER\tIXGBE_EICR_OTHER /* INT Cause Active */\n\n#define IXGBE_EIMS_ENABLE_MASK ( \\\n\t\t\t\tIXGBE_EIMS_RTX_QUEUE\t| \\\n\t\t\t\tIXGBE_EIMS_LSC\t\t| \\\n\t\t\t\tIXGBE_EIMS_TCP_TIMER\t| \\\n\t\t\t\tIXGBE_EIMS_OTHER)\n\n/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */\n#define IXGBE_IMIR_PORT_IM_EN\t0x00010000 /* TCP port enable */\n#define IXGBE_IMIR_PORT_BP\t0x00020000 /* TCP port check bypass */\n#define IXGBE_IMIREXT_SIZE_BP\t0x00001000 /* Packet size bypass */\n#define IXGBE_IMIREXT_CTRL_URG\t0x00002000 /* Check URG bit in header */\n#define IXGBE_IMIREXT_CTRL_ACK\t0x00004000 /* Check ACK bit in header */\n#define IXGBE_IMIREXT_CTRL_PSH\t0x00008000 /* Check PSH bit in header */\n#define IXGBE_IMIREXT_CTRL_RST\t0x00010000 /* Check RST bit in header */\n#define IXGBE_IMIREXT_CTRL_SYN\t0x00020000 /* Check SYN bit in header */\n#define IXGBE_IMIREXT_CTRL_FIN\t0x00040000 /* Check FIN bit in header */\n#define IXGBE_IMIREXT_CTRL_BP\t0x00080000 /* Bypass check of control bits */\n#define IXGBE_IMIR_SIZE_BP_82599\t0x00001000 /* Packet size bypass */\n#define IXGBE_IMIR_CTRL_URG_82599\t0x00002000 /* Check URG bit in header */\n#define IXGBE_IMIR_CTRL_ACK_82599\t0x00004000 /* Check ACK bit in header */\n#define IXGBE_IMIR_CTRL_PSH_82599\t0x00008000 /* Check PSH bit in header */\n#define IXGBE_IMIR_CTRL_RST_82599\t0x00010000 /* Check RST bit in header */\n#define IXGBE_IMIR_CTRL_SYN_82599\t0x00020000 /* Check SYN bit in header */\n#define IXGBE_IMIR_CTRL_FIN_82599\t0x00040000 /* Check FIN bit in header */\n#define IXGBE_IMIR_CTRL_BP_82599\t0x00080000 /* Bypass chk of ctrl bits */\n#define IXGBE_IMIR_LLI_EN_82599\t\t0x00100000 /* Enables low latency Int */\n#define IXGBE_IMIR_RX_QUEUE_MASK_82599\t0x0000007F /* Rx Queue Mask */\n#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599\t21 /* Rx Queue Shift */\n#define IXGBE_IMIRVP_PRIORITY_MASK\t0x00000007 /* VLAN priority mask */\n#define IXGBE_IMIRVP_PRIORITY_EN\t0x00000008 /* VLAN priority enable */\n\n#define IXGBE_MAX_FTQF_FILTERS\t\t128\n#define IXGBE_FTQF_PROTOCOL_MASK\t0x00000003\n#define IXGBE_FTQF_PROTOCOL_TCP\t\t0x00000000\n#define IXGBE_FTQF_PROTOCOL_UDP\t\t0x00000001\n#define IXGBE_FTQF_PROTOCOL_SCTP\t2\n#define IXGBE_FTQF_PRIORITY_MASK\t0x00000007\n#define IXGBE_FTQF_PRIORITY_SHIFT\t2\n#define IXGBE_FTQF_POOL_MASK\t\t0x0000003F\n#define IXGBE_FTQF_POOL_SHIFT\t\t8\n#define IXGBE_FTQF_5TUPLE_MASK_MASK\t0x0000001F\n#define IXGBE_FTQF_5TUPLE_MASK_SHIFT\t25\n#define IXGBE_FTQF_SOURCE_ADDR_MASK\t0x1E\n#define IXGBE_FTQF_DEST_ADDR_MASK\t0x1D\n#define IXGBE_FTQF_SOURCE_PORT_MASK\t0x1B\n#define IXGBE_FTQF_DEST_PORT_MASK\t0x17\n#define IXGBE_FTQF_PROTOCOL_COMP_MASK\t0x0F\n#define IXGBE_FTQF_POOL_MASK_EN\t\t0x40000000\n#define IXGBE_FTQF_QUEUE_ENABLE\t\t0x80000000\n\n/* Interrupt clear mask */\n#define IXGBE_IRQ_CLEAR_MASK\t0xFFFFFFFF\n\n/* Interrupt Vector Allocation Registers */\n#define IXGBE_IVAR_REG_NUM\t\t25\n#define IXGBE_IVAR_REG_NUM_82599\t64\n#define IXGBE_IVAR_TXRX_ENTRY\t\t96\n#define IXGBE_IVAR_RX_ENTRY\t\t64\n#define IXGBE_IVAR_RX_QUEUE(_i)\t\t(0 + (_i))\n#define IXGBE_IVAR_TX_QUEUE(_i)\t\t(64 + (_i))\n#define IXGBE_IVAR_TX_ENTRY\t\t32\n\n#define IXGBE_IVAR_TCP_TIMER_INDEX\t96 /* 0 based index */\n#define IXGBE_IVAR_OTHER_CAUSES_INDEX\t97 /* 0 based index */\n\n#define IXGBE_MSIX_VECTOR(_i)\t\t(0 + (_i))\n\n#define IXGBE_IVAR_ALLOC_VAL\t\t0x80 /* Interrupt Allocation valid */\n\n/* ETYPE Queue Filter/Select Bit Masks */\n#define IXGBE_MAX_ETQF_FILTERS\t\t8\n#define IXGBE_ETQF_FCOE\t\t\t0x08000000 /* bit 27 */\n#define IXGBE_ETQF_BCN\t\t\t0x10000000 /* bit 28 */\n#define IXGBE_ETQF_TX_ANTISPOOF\t\t0x20000000 /* bit 29 */\n#define IXGBE_ETQF_1588\t\t\t0x40000000 /* bit 30 */\n#define IXGBE_ETQF_FILTER_EN\t\t0x80000000 /* bit 31 */\n#define IXGBE_ETQF_POOL_ENABLE\t\t(1 << 26) /* bit 26 */\n#define IXGBE_ETQF_POOL_SHIFT\t\t20\n\n#define IXGBE_ETQS_RX_QUEUE\t\t0x007F0000 /* bits 22:16 */\n#define IXGBE_ETQS_RX_QUEUE_SHIFT\t16\n#define IXGBE_ETQS_LLI\t\t\t0x20000000 /* bit 29 */\n#define IXGBE_ETQS_QUEUE_EN\t\t0x80000000 /* bit 31 */\n\n/*\n * ETQF filter list: one static filter per filter consumer. This is\n *\t\t to avoid filter collisions later. Add new filters\n *\t\t here!!\n *\n * Current filters:\n *\tEAPOL 802.1x (0x888e): Filter 0\n *\tFCoE (0x8906):\t Filter 2\n *\t1588 (0x88f7):\t Filter 3\n *\tFIP (0x8914):\t Filter 4\n *\tLLDP (0x88CC):\t Filter 5\n *\tLACP (0x8809):\t Filter 6\n */\n#define IXGBE_ETQF_FILTER_EAPOL\t\t0\n#define IXGBE_ETQF_FILTER_FCOE\t\t2\n#define IXGBE_ETQF_FILTER_1588\t\t3\n#define IXGBE_ETQF_FILTER_FIP\t\t4\n#define IXGBE_ETQF_FILTER_LLDP\t\t5\n#define IXGBE_ETQF_FILTER_LACP\t\t6\n/* VLAN Control Bit Masks */\n#define IXGBE_VLNCTRL_VET\t\t0x0000FFFF /* bits 0-15 */\n#define IXGBE_VLNCTRL_CFI\t\t0x10000000 /* bit 28 */\n#define IXGBE_VLNCTRL_CFIEN\t\t0x20000000 /* bit 29 */\n#define IXGBE_VLNCTRL_VFE\t\t0x40000000 /* bit 30 */\n#define IXGBE_VLNCTRL_VME\t\t0x80000000 /* bit 31 */\n\n/* VLAN pool filtering masks */\n#define IXGBE_VLVF_VIEN\t\t\t0x80000000 /* filter is valid */\n#define IXGBE_VLVF_ENTRIES\t\t64\n#define IXGBE_VLVF_VLANID_MASK\t\t0x00000FFF\n/* Per VF Port VLAN insertion rules */\n#define IXGBE_VMVIR_VLANA_DEFAULT\t0x40000000 /* Always use default VLAN */\n#define IXGBE_VMVIR_VLANA_NEVER\t\t0x80000000 /* Never insert VLAN tag */\n\n#define IXGBE_ETHERNET_IEEE_VLAN_TYPE\t0x8100 /* 802.1q protocol */\n\n/* STATUS Bit Masks */\n#define IXGBE_STATUS_LAN_ID\t\t0x0000000C /* LAN ID */\n#define IXGBE_STATUS_LAN_ID_SHIFT\t2 /* LAN ID Shift*/\n#define IXGBE_STATUS_GIO\t\t0x00080000 /* GIO Master Ena Status */\n\n#define IXGBE_STATUS_LAN_ID_0\t0x00000000 /* LAN ID 0 */\n#define IXGBE_STATUS_LAN_ID_1\t0x00000004 /* LAN ID 1 */\n\n/* ESDP Bit Masks */\n#define IXGBE_ESDP_SDP0\t\t0x00000001 /* SDP0 Data Value */\n#define IXGBE_ESDP_SDP1\t\t0x00000002 /* SDP1 Data Value */\n#define IXGBE_ESDP_SDP2\t\t0x00000004 /* SDP2 Data Value */\n#define IXGBE_ESDP_SDP3\t\t0x00000008 /* SDP3 Data Value */\n#define IXGBE_ESDP_SDP4\t\t0x00000010 /* SDP4 Data Value */\n#define IXGBE_ESDP_SDP5\t\t0x00000020 /* SDP5 Data Value */\n#define IXGBE_ESDP_SDP6\t\t0x00000040 /* SDP6 Data Value */\n#define IXGBE_ESDP_SDP7\t\t0x00000080 /* SDP7 Data Value */\n#define IXGBE_ESDP_SDP0_DIR\t0x00000100 /* SDP0 IO direction */\n#define IXGBE_ESDP_SDP1_DIR\t0x00000200 /* SDP1 IO direction */\n#define IXGBE_ESDP_SDP2_DIR\t0x00000400 /* SDP1 IO direction */\n#define IXGBE_ESDP_SDP3_DIR\t0x00000800 /* SDP3 IO direction */\n#define IXGBE_ESDP_SDP4_DIR\t0x00001000 /* SDP4 IO direction */\n#define IXGBE_ESDP_SDP5_DIR\t0x00002000 /* SDP5 IO direction */\n#define IXGBE_ESDP_SDP6_DIR\t0x00004000 /* SDP6 IO direction */\n#define IXGBE_ESDP_SDP7_DIR\t0x00008000 /* SDP7 IO direction */\n#define IXGBE_ESDP_SDP0_NATIVE\t0x00010000 /* SDP0 IO mode */\n#define IXGBE_ESDP_SDP1_NATIVE\t0x00020000 /* SDP1 IO mode */\n\n\n/* LEDCTL Bit Masks */\n#define IXGBE_LED_IVRT_BASE\t\t0x00000040\n#define IXGBE_LED_BLINK_BASE\t\t0x00000080\n#define IXGBE_LED_MODE_MASK_BASE\t0x0000000F\n#define IXGBE_LED_OFFSET(_base, _i)\t(_base << (8 * (_i)))\n#define IXGBE_LED_MODE_SHIFT(_i)\t(8*(_i))\n#define IXGBE_LED_IVRT(_i)\tIXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)\n#define IXGBE_LED_BLINK(_i)\tIXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)\n#define IXGBE_LED_MODE_MASK(_i)\tIXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)\n#define IXGBE_X557_LED_MANUAL_SET_MASK\t(1 << 8)\n#define IXGBE_X557_MAX_LED_INDEX\t3\n#define IXGBE_X557_LED_PROVISIONING\t0xC430\n\n/* LED modes */\n#define IXGBE_LED_LINK_UP\t0x0\n#define IXGBE_LED_LINK_10G\t0x1\n#define IXGBE_LED_MAC\t\t0x2\n#define IXGBE_LED_FILTER\t0x3\n#define IXGBE_LED_LINK_ACTIVE\t0x4\n#define IXGBE_LED_LINK_1G\t0x5\n#define IXGBE_LED_ON\t\t0xE\n#define IXGBE_LED_OFF\t\t0xF\n\n/* AUTOC Bit Masks */\n#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000\n#define IXGBE_AUTOC_KX4_SUPP\t0x80000000\n#define IXGBE_AUTOC_KX_SUPP\t0x40000000\n#define IXGBE_AUTOC_PAUSE\t0x30000000\n#define IXGBE_AUTOC_ASM_PAUSE\t0x20000000\n#define IXGBE_AUTOC_SYM_PAUSE\t0x10000000\n#define IXGBE_AUTOC_RF\t\t0x08000000\n#define IXGBE_AUTOC_PD_TMR\t0x06000000\n#define IXGBE_AUTOC_AN_RX_LOOSE\t0x01000000\n#define IXGBE_AUTOC_AN_RX_DRIFT\t0x00800000\n#define IXGBE_AUTOC_AN_RX_ALIGN\t0x007C0000\n#define IXGBE_AUTOC_FECA\t0x00040000\n#define IXGBE_AUTOC_FECR\t0x00020000\n#define IXGBE_AUTOC_KR_SUPP\t0x00010000\n#define IXGBE_AUTOC_AN_RESTART\t0x00001000\n#define IXGBE_AUTOC_FLU\t\t0x00000001\n#define IXGBE_AUTOC_LMS_SHIFT\t13\n#define IXGBE_AUTOC_LMS_10G_SERIAL\t(0x3 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_KX4_KX_KR\t(0x4 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_SGMII_1G_100M\t(0x5 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN\t(0x6 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII\t(0x7 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_MASK\t\t(0x7 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN\t(0x0 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN\t(0x1 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_1G_AN\t\t(0x2 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_KX4_AN\t\t(0x4 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN\t(0x6 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_ATTACH_TYPE\t(0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)\n\n#define IXGBE_AUTOC_1G_PMA_PMD_MASK\t0x00000200\n#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT\t9\n#define IXGBE_AUTOC_10G_PMA_PMD_MASK\t0x00000180\n#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT\t7\n#define IXGBE_AUTOC_10G_XAUI\t(0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC_10G_KX4\t(0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC_10G_CX4\t(0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC_1G_BX\t(0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC_1G_KX\t(0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC_1G_SFI\t(0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC_1G_KX_BX\t(0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)\n\n#define IXGBE_AUTOC2_UPPER_MASK\t0xFFFF0000\n#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK\t0x00030000\n#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT\t16\n#define IXGBE_AUTOC2_10G_KR\t(0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC2_10G_XFI\t(0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC2_10G_SFI\t(0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK\t0x50000000\n#define IXGBE_AUTOC2_LINK_DISABLE_MASK\t\t0x70000000\n\n#define IXGBE_MACC_FLU\t\t0x00000001\n#define IXGBE_MACC_FSV_10G\t0x00030000\n#define IXGBE_MACC_FS\t\t0x00040000\n#define IXGBE_MAC_RX2TX_LPBK\t0x00000002\n\n/* Veto Bit definiton */\n#define IXGBE_MMNGC_MNG_VETO\t0x00000001\n\n/* LINKS Bit Masks */\n#define IXGBE_LINKS_KX_AN_COMP\t0x80000000\n#define IXGBE_LINKS_UP\t\t0x40000000\n#define IXGBE_LINKS_SPEED\t0x20000000\n#define IXGBE_LINKS_MODE\t0x18000000\n#define IXGBE_LINKS_RX_MODE\t0x06000000\n#define IXGBE_LINKS_TX_MODE\t0x01800000\n#define IXGBE_LINKS_XGXS_EN\t0x00400000\n#define IXGBE_LINKS_SGMII_EN\t0x02000000\n#define IXGBE_LINKS_PCS_1G_EN\t0x00200000\n#define IXGBE_LINKS_1G_AN_EN\t0x00100000\n#define IXGBE_LINKS_KX_AN_IDLE\t0x00080000\n#define IXGBE_LINKS_1G_SYNC\t0x00040000\n#define IXGBE_LINKS_10G_ALIGN\t0x00020000\n#define IXGBE_LINKS_10G_LANE_SYNC\t0x00017000\n#define IXGBE_LINKS_TL_FAULT\t\t0x00001000\n#define IXGBE_LINKS_SIGNAL\t\t0x00000F00\n\n#define IXGBE_LINKS_SPEED_NON_STD\t0x08000000\n#define IXGBE_LINKS_SPEED_82599\t\t0x30000000\n#define IXGBE_LINKS_SPEED_10G_82599\t0x30000000\n#define IXGBE_LINKS_SPEED_1G_82599\t0x20000000\n#define IXGBE_LINKS_SPEED_100_82599\t0x10000000\n#define IXGBE_LINK_UP_TIME\t\t90 /* 9.0 Seconds */\n#define IXGBE_AUTO_NEG_TIME\t\t45 /* 4.5 Seconds */\n\n#define IXGBE_LINKS2_AN_SUPPORTED\t0x00000040\n\n/* PCS1GLSTA Bit Masks */\n#define IXGBE_PCS1GLSTA_LINK_OK\t\t1\n#define IXGBE_PCS1GLSTA_SYNK_OK\t\t0x10\n#define IXGBE_PCS1GLSTA_AN_COMPLETE\t0x10000\n#define IXGBE_PCS1GLSTA_AN_PAGE_RX\t0x20000\n#define IXGBE_PCS1GLSTA_AN_TIMED_OUT\t0x40000\n#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT\t0x80000\n#define IXGBE_PCS1GLSTA_AN_ERROR_RWS\t0x100000\n\n#define IXGBE_PCS1GANA_SYM_PAUSE\t0x80\n#define IXGBE_PCS1GANA_ASM_PAUSE\t0x100\n\n/* PCS1GLCTL Bit Masks */\n#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */\n#define IXGBE_PCS1GLCTL_FLV_LINK_UP\t1\n#define IXGBE_PCS1GLCTL_FORCE_LINK\t0x20\n#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH\t0x40\n#define IXGBE_PCS1GLCTL_AN_ENABLE\t0x10000\n#define IXGBE_PCS1GLCTL_AN_RESTART\t0x20000\n\n/* ANLP1 Bit Masks */\n#define IXGBE_ANLP1_PAUSE\t\t0x0C00\n#define IXGBE_ANLP1_SYM_PAUSE\t\t0x0400\n#define IXGBE_ANLP1_ASM_PAUSE\t\t0x0800\n#define IXGBE_ANLP1_AN_STATE_MASK\t0x000f0000\n\n/* SW Semaphore Register bitmasks */\n#define IXGBE_SWSM_SMBI\t\t0x00000001 /* Driver Semaphore bit */\n#define IXGBE_SWSM_SWESMBI\t0x00000002 /* FW Semaphore bit */\n#define IXGBE_SWSM_WMNG\t\t0x00000004 /* Wake MNG Clock */\n#define IXGBE_SWFW_REGSMP\t0x80000000 /* Register Semaphore bit 31 */\n\n/* SW_FW_SYNC/GSSR definitions */\n#define IXGBE_GSSR_EEP_SM\t\t0x0001\n#define IXGBE_GSSR_PHY0_SM\t\t0x0002\n#define IXGBE_GSSR_PHY1_SM\t\t0x0004\n#define IXGBE_GSSR_MAC_CSR_SM\t\t0x0008\n#define IXGBE_GSSR_FLASH_SM\t\t0x0010\n#define IXGBE_GSSR_NVM_UPDATE_SM\t0x0200\n#define IXGBE_GSSR_SW_MNG_SM\t\t0x0400\n#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */\n#define IXGBE_GSSR_I2C_MASK\t0x1800\n#define IXGBE_GSSR_NVM_PHY_MASK\t0xF\n\n/* FW Status register bitmask */\n#define IXGBE_FWSTS_FWRI\t0x00000200 /* Firmware Reset Indication */\n\n/* EEC Register */\n#define IXGBE_EEC_SK\t\t0x00000001 /* EEPROM Clock */\n#define IXGBE_EEC_CS\t\t0x00000002 /* EEPROM Chip Select */\n#define IXGBE_EEC_DI\t\t0x00000004 /* EEPROM Data In */\n#define IXGBE_EEC_DO\t\t0x00000008 /* EEPROM Data Out */\n#define IXGBE_EEC_FWE_MASK\t0x00000030 /* FLASH Write Enable */\n#define IXGBE_EEC_FWE_DIS\t0x00000010 /* Disable FLASH writes */\n#define IXGBE_EEC_FWE_EN\t0x00000020 /* Enable FLASH writes */\n#define IXGBE_EEC_FWE_SHIFT\t4\n#define IXGBE_EEC_REQ\t\t0x00000040 /* EEPROM Access Request */\n#define IXGBE_EEC_GNT\t\t0x00000080 /* EEPROM Access Grant */\n#define IXGBE_EEC_PRES\t\t0x00000100 /* EEPROM Present */\n#define IXGBE_EEC_ARD\t\t0x00000200 /* EEPROM Auto Read Done */\n#define IXGBE_EEC_FLUP\t\t0x00800000 /* Flash update command */\n#define IXGBE_EEC_SEC1VAL\t0x02000000 /* Sector 1 Valid */\n#define IXGBE_EEC_FLUDONE\t0x04000000 /* Flash update done */\n/* EEPROM Addressing bits based on type (0-small, 1-large) */\n#define IXGBE_EEC_ADDR_SIZE\t0x00000400\n#define IXGBE_EEC_SIZE\t\t0x00007800 /* EEPROM Size */\n#define IXGBE_EERD_MAX_ADDR\t0x00003FFF /* EERD alows 14 bits for addr. */\n\n#define IXGBE_EEC_SIZE_SHIFT\t\t11\n#define IXGBE_EEPROM_WORD_SIZE_SHIFT\t6\n#define IXGBE_EEPROM_OPCODE_BITS\t8\n\n/* FLA Register */\n#define IXGBE_FLA_LOCKED\t0x00000040\n\n/* Part Number String Length */\n#define IXGBE_PBANUM_LENGTH\t11\n\n/* Checksum and EEPROM pointers */\n#define IXGBE_PBANUM_PTR_GUARD\t\t0xFAFA\n#define IXGBE_EEPROM_CHECKSUM\t\t0x3F\n#define IXGBE_EEPROM_SUM\t\t0xBABA\n#define IXGBE_PCIE_ANALOG_PTR\t\t0x03\n#define IXGBE_ATLAS0_CONFIG_PTR\t\t0x04\n#define IXGBE_PHY_PTR\t\t\t0x04\n#define IXGBE_ATLAS1_CONFIG_PTR\t\t0x05\n#define IXGBE_OPTION_ROM_PTR\t\t0x05\n#define IXGBE_PCIE_GENERAL_PTR\t\t0x06\n#define IXGBE_PCIE_CONFIG0_PTR\t\t0x07\n#define IXGBE_PCIE_CONFIG1_PTR\t\t0x08\n#define IXGBE_CORE0_PTR\t\t\t0x09\n#define IXGBE_CORE1_PTR\t\t\t0x0A\n#define IXGBE_MAC0_PTR\t\t\t0x0B\n#define IXGBE_MAC1_PTR\t\t\t0x0C\n#define IXGBE_CSR0_CONFIG_PTR\t\t0x0D\n#define IXGBE_CSR1_CONFIG_PTR\t\t0x0E\n#define IXGBE_PCIE_ANALOG_PTR_X550\t0x02\n#define IXGBE_SHADOW_RAM_SIZE_X550\t0x4000\n#define IXGBE_IXGBE_PCIE_GENERAL_SIZE\t0x24\n#define IXGBE_PCIE_CONFIG_SIZE\t\t0x08\n#define IXGBE_EEPROM_LAST_WORD\t\t0x41\n#define IXGBE_FW_PTR\t\t\t0x0F\n#define IXGBE_PBANUM0_PTR\t\t0x15\n#define IXGBE_PBANUM1_PTR\t\t0x16\n#define IXGBE_ALT_MAC_ADDR_PTR\t\t0x37\n#define IXGBE_FREE_SPACE_PTR\t\t0X3E\n\n/* External Thermal Sensor Config */\n#define IXGBE_ETS_CFG\t\t\t0x26\n#define IXGBE_ETS_LTHRES_DELTA_MASK\t0x07C0\n#define IXGBE_ETS_LTHRES_DELTA_SHIFT\t6\n#define IXGBE_ETS_TYPE_MASK\t\t0x0038\n#define IXGBE_ETS_TYPE_SHIFT\t\t3\n#define IXGBE_ETS_TYPE_EMC\t\t0x000\n#define IXGBE_ETS_NUM_SENSORS_MASK\t0x0007\n#define IXGBE_ETS_DATA_LOC_MASK\t\t0x3C00\n#define IXGBE_ETS_DATA_LOC_SHIFT\t10\n#define IXGBE_ETS_DATA_INDEX_MASK\t0x0300\n#define IXGBE_ETS_DATA_INDEX_SHIFT\t8\n#define IXGBE_ETS_DATA_HTHRESH_MASK\t0x00FF\n\n#define IXGBE_SAN_MAC_ADDR_PTR\t\t0x28\n#define IXGBE_DEVICE_CAPS\t\t0x2C\n#define IXGBE_SERIAL_NUMBER_MAC_ADDR\t0x11\n#define IXGBE_PCIE_MSIX_82599_CAPS\t0x72\n#define IXGBE_MAX_MSIX_VECTORS_82599\t0x40\n#define IXGBE_PCIE_MSIX_82598_CAPS\t0x62\n#define IXGBE_MAX_MSIX_VECTORS_82598\t0x13\n\n/* MSI-X capability fields masks */\n#define IXGBE_PCIE_MSIX_TBL_SZ_MASK\t0x7FF\n\n/* Legacy EEPROM word offsets */\n#define IXGBE_ISCSI_BOOT_CAPS\t\t0x0033\n#define IXGBE_ISCSI_SETUP_PORT_0\t0x0030\n#define IXGBE_ISCSI_SETUP_PORT_1\t0x0034\n\n/* EEPROM Commands - SPI */\n#define IXGBE_EEPROM_MAX_RETRY_SPI\t5000 /* Max wait 5ms for RDY signal */\n#define IXGBE_EEPROM_STATUS_RDY_SPI\t0x01\n#define IXGBE_EEPROM_READ_OPCODE_SPI\t0x03 /* EEPROM read opcode */\n#define IXGBE_EEPROM_WRITE_OPCODE_SPI\t0x02 /* EEPROM write opcode */\n#define IXGBE_EEPROM_A8_OPCODE_SPI\t0x08 /* opcode bit-3 = addr bit-8 */\n#define IXGBE_EEPROM_WREN_OPCODE_SPI\t0x06 /* EEPROM set Write Ena latch */\n/* EEPROM reset Write Enable latch */\n#define IXGBE_EEPROM_WRDI_OPCODE_SPI\t0x04\n#define IXGBE_EEPROM_RDSR_OPCODE_SPI\t0x05 /* EEPROM read Status reg */\n#define IXGBE_EEPROM_WRSR_OPCODE_SPI\t0x01 /* EEPROM write Status reg */\n#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI\t0x20 /* EEPROM ERASE 4KB */\n#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI\t0xD8 /* EEPROM ERASE 64KB */\n#define IXGBE_EEPROM_ERASE256_OPCODE_SPI\t0xDB /* EEPROM ERASE 256B */\n\n/* EEPROM Read Register */\n#define IXGBE_EEPROM_RW_REG_DATA\t16 /* data offset in EEPROM read reg */\n#define IXGBE_EEPROM_RW_REG_DONE\t2 /* Offset to READ done bit */\n#define IXGBE_EEPROM_RW_REG_START\t1 /* First bit to start operation */\n#define IXGBE_EEPROM_RW_ADDR_SHIFT\t2 /* Shift to the address bits */\n#define IXGBE_NVM_POLL_WRITE\t\t1 /* Flag for polling for wr complete */\n#define IXGBE_NVM_POLL_READ\t\t0 /* Flag for polling for rd complete */\n\n#define NVM_INIT_CTRL_3\t\t0x38\n#define NVM_INIT_CTRL_3_LPLU\t0x8\n#define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40\n#define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100\n\n#define IXGBE_ETH_LENGTH_OF_ADDRESS\t6\n\n#define IXGBE_EEPROM_PAGE_SIZE_MAX\t128\n#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT\t256 /* words rd in burst */\n#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT\t256 /* words wr in burst */\n#define IXGBE_EEPROM_CTRL_2\t\t1 /* EEPROM CTRL word 2 */\n#define IXGBE_EEPROM_CCD_BIT\t\t2\n\n#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS\n#define IXGBE_EEPROM_GRANT_ATTEMPTS\t1000 /* EEPROM attempts to gain grant */\n#endif\n\n/* Number of 5 microseconds we wait for EERD read and\n * EERW write to complete */\n#define IXGBE_EERD_EEWR_ATTEMPTS\t100000\n\n/* # attempts we wait for flush update to complete */\n#define IXGBE_FLUDONE_ATTEMPTS\t\t20000\n\n#define IXGBE_PCIE_CTRL2\t\t0x5 /* PCIe Control 2 Offset */\n#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE\t0x8 /* Dummy Function Enable */\n#define IXGBE_PCIE_CTRL2_LAN_DISABLE\t0x2 /* LAN PCI Disable */\n#define IXGBE_PCIE_CTRL2_DISABLE_SELECT\t0x1 /* LAN Disable Select */\n\n#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET\t\t0x0\n#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET\t\t0x3\n#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP\t\t0x1\n#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS\t\t0x2\n#define IXGBE_FW_LESM_PARAMETERS_PTR\t\t0x2\n#define IXGBE_FW_LESM_STATE_1\t\t\t0x1\n#define IXGBE_FW_LESM_STATE_ENABLED\t\t0x8000 /* LESM Enable bit */\n#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR\t0x4\n#define IXGBE_FW_PATCH_VERSION_4\t\t0x7\n#define IXGBE_FCOE_IBA_CAPS_BLK_PTR\t\t0x33 /* iSCSI/FCOE block */\n#define IXGBE_FCOE_IBA_CAPS_FCOE\t\t0x20 /* FCOE flags */\n#define IXGBE_ISCSI_FCOE_BLK_PTR\t\t0x17 /* iSCSI/FCOE block */\n#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET\t\t0x0 /* FCOE flags */\n#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE\t\t0x1 /* FCOE flags enable bit */\n#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR\t\t0x27 /* Alt. SAN MAC block */\n#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET\t0x0 /* Alt SAN MAC capability */\n#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET\t0x1 /* Alt SAN MAC 0 offset */\n#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET\t0x4 /* Alt SAN MAC 1 offset */\n#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET\t0x7 /* Alt WWNN prefix offset */\n#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET\t0x8 /* Alt WWPN prefix offset */\n#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC\t0x0 /* Alt SAN MAC exists */\n#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN\t0x1 /* Alt WWN base exists */\n\n/* FW header offset */\n#define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR\t0x4\n#define IXGBE_X540_FW_MODULE_MASK\t\t\t0x7FFF\n/* 4KB multiplier */\n#define IXGBE_X540_FW_MODULE_LENGTH\t\t\t0x1000\n/* version word 2 (month & day) */\n#define IXGBE_X540_FW_PATCH_VERSION_2\t\t0x5\n/* version word 3 (silicon compatibility & year) */\n#define IXGBE_X540_FW_PATCH_VERSION_3\t\t0x6\n/* version word 4 (major & minor numbers) */\n#define IXGBE_X540_FW_PATCH_VERSION_4\t\t0x7\n\n#define IXGBE_DEVICE_CAPS_WOL_PORT0_1\t0x4 /* WoL supported on ports 0 & 1 */\n#define IXGBE_DEVICE_CAPS_WOL_PORT0\t0x8 /* WoL supported on port 0 */\n#define IXGBE_DEVICE_CAPS_WOL_MASK\t0xC /* Mask for WoL capabilities */\n\n/* PCI Bus Info */\n#define IXGBE_PCI_DEVICE_STATUS\t\t0xAA\n#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING\t0x0020\n#define IXGBE_PCI_LINK_STATUS\t\t0xB2\n#define IXGBE_PCI_DEVICE_CONTROL2\t0xC8\n#define IXGBE_PCI_LINK_WIDTH\t\t0x3F0\n#define IXGBE_PCI_LINK_WIDTH_1\t\t0x10\n#define IXGBE_PCI_LINK_WIDTH_2\t\t0x20\n#define IXGBE_PCI_LINK_WIDTH_4\t\t0x40\n#define IXGBE_PCI_LINK_WIDTH_8\t\t0x80\n#define IXGBE_PCI_LINK_SPEED\t\t0xF\n#define IXGBE_PCI_LINK_SPEED_2500\t0x1\n#define IXGBE_PCI_LINK_SPEED_5000\t0x2\n#define IXGBE_PCI_LINK_SPEED_8000\t0x3\n#define IXGBE_PCI_HEADER_TYPE_REGISTER\t0x0E\n#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC\t0x80\n#define IXGBE_PCI_DEVICE_CONTROL2_16ms\t0x0005\n\n#define IXGBE_PCIDEVCTRL2_TIMEO_MASK\t0xf\n#define IXGBE_PCIDEVCTRL2_16_32ms_def\t0x0\n#define IXGBE_PCIDEVCTRL2_50_100us\t0x1\n#define IXGBE_PCIDEVCTRL2_1_2ms\t\t0x2\n#define IXGBE_PCIDEVCTRL2_16_32ms\t0x5\n#define IXGBE_PCIDEVCTRL2_65_130ms\t0x6\n#define IXGBE_PCIDEVCTRL2_260_520ms\t0x9\n#define IXGBE_PCIDEVCTRL2_1_2s\t\t0xa\n#define IXGBE_PCIDEVCTRL2_4_8s\t\t0xd\n#define IXGBE_PCIDEVCTRL2_17_34s\t0xe\n\n/* Number of 100 microseconds we wait for PCI Express master disable */\n#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT\t800\n\n/* Check whether address is multicast. This is little-endian specific check.*/\n#define IXGBE_IS_MULTICAST(Address) \\\n\t\t(bool)(((u8 *)(Address))[0] & ((u8)0x01))\n\n/* Check whether an address is broadcast. */\n#define IXGBE_IS_BROADCAST(Address) \\\n\t\t((((u8 *)(Address))[0] == ((u8)0xff)) && \\\n\t\t(((u8 *)(Address))[1] == ((u8)0xff)))\n\n/* RAH */\n#define IXGBE_RAH_VIND_MASK\t0x003C0000\n#define IXGBE_RAH_VIND_SHIFT\t18\n#define IXGBE_RAH_AV\t\t0x80000000\n#define IXGBE_CLEAR_VMDQ_ALL\t0xFFFFFFFF\n\n/* Header split receive */\n#define IXGBE_RFCTL_ISCSI_DIS\t\t0x00000001\n#define IXGBE_RFCTL_ISCSI_DWC_MASK\t0x0000003E\n#define IXGBE_RFCTL_ISCSI_DWC_SHIFT\t1\n#define IXGBE_RFCTL_RSC_DIS\t\t0x00000020\n#define IXGBE_RFCTL_NFSW_DIS\t\t0x00000040\n#define IXGBE_RFCTL_NFSR_DIS\t\t0x00000080\n#define IXGBE_RFCTL_NFS_VER_MASK\t0x00000300\n#define IXGBE_RFCTL_NFS_VER_SHIFT\t8\n#define IXGBE_RFCTL_NFS_VER_2\t\t0\n#define IXGBE_RFCTL_NFS_VER_3\t\t1\n#define IXGBE_RFCTL_NFS_VER_4\t\t2\n#define IXGBE_RFCTL_IPV6_DIS\t\t0x00000400\n#define IXGBE_RFCTL_IPV6_XSUM_DIS\t0x00000800\n#define IXGBE_RFCTL_IPFRSP_DIS\t\t0x00004000\n#define IXGBE_RFCTL_IPV6_EX_DIS\t\t0x00010000\n#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS\t0x00020000\n\n/* Transmit Config masks */\n#define IXGBE_TXDCTL_ENABLE\t\t0x02000000 /* Ena specific Tx Queue */\n#define IXGBE_TXDCTL_SWFLSH\t\t0x04000000 /* Tx Desc. wr-bk flushing */\n#define IXGBE_TXDCTL_WTHRESH_SHIFT\t16 /* shift to WTHRESH bits */\n/* Enable short packet padding to 64 bytes */\n#define IXGBE_TX_PAD_ENABLE\t\t0x00000400\n#define IXGBE_JUMBO_FRAME_ENABLE\t0x00000004 /* Allow jumbo frames */\n/* This allows for 16K packets + 4k for vlan */\n#define IXGBE_MAX_FRAME_SZ\t\t0x40040000\n\n#define IXGBE_TDWBAL_HEAD_WB_ENABLE\t0x1 /* Tx head write-back enable */\n#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE\t0x2 /* Tx seq# write-back enable */\n\n/* Receive Config masks */\n#define IXGBE_RXCTRL_RXEN\t\t0x00000001 /* Enable Receiver */\n#define IXGBE_RXCTRL_DMBYPS\t\t0x00000002 /* Desc Monitor Bypass */\n#define IXGBE_RXDCTL_ENABLE\t\t0x02000000 /* Ena specific Rx Queue */\n#define IXGBE_RXDCTL_SWFLSH\t\t0x04000000 /* Rx Desc wr-bk flushing */\n#define IXGBE_RXDCTL_RLPMLMASK\t\t0x00003FFF /* X540 supported only */\n#define IXGBE_RXDCTL_RLPML_EN\t\t0x00008000\n#define IXGBE_RXDCTL_VME\t\t0x40000000 /* VLAN mode enable */\n\n#define IXGBE_TSAUXC_EN_CLK\t\t0x00000004\n#define IXGBE_TSAUXC_SYNCLK\t\t0x00000008\n#define IXGBE_TSAUXC_SDP0_INT\t\t0x00000040\n#define IXGBE_TSAUXC_EN_TT0\t\t0x00000001\n#define IXGBE_TSAUXC_EN_TT1\t\t0x00000002\n#define IXGBE_TSAUXC_ST0\t\t0x00000010\n#define IXGBE_TSAUXC_DISABLE_SYSTIME\t0x80000000\n\n#define IXGBE_TSSDP_TS_SDP0_SEL_MASK\t0x000000C0\n#define IXGBE_TSSDP_TS_SDP0_CLK0\t0x00000080\n#define IXGBE_TSSDP_TS_SDP0_EN\t\t0x00000100\n\n#define IXGBE_TSYNCTXCTL_VALID\t\t0x00000001 /* Tx timestamp valid */\n#define IXGBE_TSYNCTXCTL_ENABLED\t0x00000010 /* Tx timestamping enabled */\n\n#define IXGBE_TSYNCRXCTL_VALID\t\t0x00000001 /* Rx timestamp valid */\n#define IXGBE_TSYNCRXCTL_TYPE_MASK\t0x0000000E /* Rx type mask */\n#define IXGBE_TSYNCRXCTL_TYPE_L2_V2\t0x00\n#define IXGBE_TSYNCRXCTL_TYPE_L4_V1\t0x02\n#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2\t0x04\n#define IXGBE_TSYNCRXCTL_TYPE_ALL\t0x08\n#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2\t0x0A\n#define IXGBE_TSYNCRXCTL_ENABLED\t0x00000010 /* Rx Timestamping enabled */\n#define IXGBE_TSYNCRXCTL_TSIP_UT_EN\t0x00800000 /* Rx Timestamp in Packet */\n#define IXGBE_TSYNCRXCTL_TSIP_UP_MASK\t0xFF000000 /* Rx Timestamp UP Mask */\n\n#define IXGBE_TSIM_SYS_WRAP\t\t0x00000001\n#define IXGBE_TSIM_TXTS\t\t\t0x00000002\n#define IXGBE_TSIM_TADJ\t\t\t0x00000080\n\n#define IXGBE_TSICR_SYS_WRAP\t\tIXGBE_TSIM_SYS_WRAP\n#define IXGBE_TSICR_TXTS\t\tIXGBE_TSIM_TXTS\n#define IXGBE_TSICR_TADJ\t\tIXGBE_TSIM_TADJ\n\n#define IXGBE_RXMTRL_V1_CTRLT_MASK\t0x000000FF\n#define IXGBE_RXMTRL_V1_SYNC_MSG\t0x00\n#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG\t0x01\n#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG\t0x02\n#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG\t0x03\n#define IXGBE_RXMTRL_V1_MGMT_MSG\t0x04\n\n#define IXGBE_RXMTRL_V2_MSGID_MASK\t0x0000FF00\n#define IXGBE_RXMTRL_V2_SYNC_MSG\t0x0000\n#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG\t0x0100\n#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG\t0x0200\n#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG\t0x0300\n#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG\t0x0800\n#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG\t0x0900\n#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00\n#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG\t0x0B00\n#define IXGBE_RXMTRL_V2_SIGNALLING_MSG\t0x0C00\n#define IXGBE_RXMTRL_V2_MGMT_MSG\t0x0D00\n\n#define IXGBE_FCTRL_SBP\t\t0x00000002 /* Store Bad Packet */\n#define IXGBE_FCTRL_MPE\t\t0x00000100 /* Multicast Promiscuous Ena*/\n#define IXGBE_FCTRL_UPE\t\t0x00000200 /* Unicast Promiscuous Ena */\n#define IXGBE_FCTRL_BAM\t\t0x00000400 /* Broadcast Accept Mode */\n#define IXGBE_FCTRL_PMCF\t0x00001000 /* Pass MAC Control Frames */\n#define IXGBE_FCTRL_DPF\t\t0x00002000 /* Discard Pause Frame */\n/* Receive Priority Flow Control Enable */\n#define IXGBE_FCTRL_RPFCE\t0x00004000\n#define IXGBE_FCTRL_RFCE\t0x00008000 /* Receive Flow Control Ena */\n#define IXGBE_MFLCN_PMCF\t0x00000001 /* Pass MAC Control Frames */\n#define IXGBE_MFLCN_DPF\t\t0x00000002 /* Discard Pause Frame */\n#define IXGBE_MFLCN_RPFCE\t0x00000004 /* Receive Priority FC Enable */\n#define IXGBE_MFLCN_RFCE\t0x00000008 /* Receive FC Enable */\n#define IXGBE_MFLCN_RPFCE_MASK\t0x00000FF4 /* Rx Priority FC bitmap mask */\n#define IXGBE_MFLCN_RPFCE_SHIFT\t4 /* Rx Priority FC bitmap shift */\n\n/* Multiple Receive Queue Control */\n#define IXGBE_MRQC_RSSEN\t0x00000001 /* RSS Enable */\n#define IXGBE_MRQC_MRQE_MASK\t0xF /* Bits 3:0 */\n#define IXGBE_MRQC_RT8TCEN\t0x00000002 /* 8 TC no RSS */\n#define IXGBE_MRQC_RT4TCEN\t0x00000003 /* 4 TC no RSS */\n#define IXGBE_MRQC_RTRSS8TCEN\t0x00000004 /* 8 TC w/ RSS */\n#define IXGBE_MRQC_RTRSS4TCEN\t0x00000005 /* 4 TC w/ RSS */\n#define IXGBE_MRQC_VMDQEN\t0x00000008 /* VMDq2 64 pools no RSS */\n#define IXGBE_MRQC_VMDQRSS32EN\t0x0000000A /* VMDq2 32 pools w/ RSS */\n#define IXGBE_MRQC_VMDQRSS64EN\t0x0000000B /* VMDq2 64 pools w/ RSS */\n#define IXGBE_MRQC_VMDQRT8TCEN\t0x0000000C /* VMDq2/RT 16 pool 8 TC */\n#define IXGBE_MRQC_VMDQRT4TCEN\t0x0000000D /* VMDq2/RT 32 pool 4 TC */\n#define IXGBE_MRQC_RSS_FIELD_MASK\t0xFFFF0000\n#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP\t0x00010000\n#define IXGBE_MRQC_RSS_FIELD_IPV4\t0x00020000\n#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000\n#define IXGBE_MRQC_RSS_FIELD_IPV6_EX\t0x00080000\n#define IXGBE_MRQC_RSS_FIELD_IPV6\t0x00100000\n#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP\t0x00200000\n#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP\t0x00400000\n#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP\t0x00800000\n#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000\n#define IXGBE_MRQC_MULTIPLE_RSS\t\t0x00002000\n#define IXGBE_MRQC_L3L4TXSWEN\t\t0x00008000\n\n/* Queue Drop Enable */\n#define IXGBE_QDE_ENABLE\t0x00000001\n#define IXGBE_QDE_HIDE_VLAN\t0x00000002\n#define IXGBE_QDE_IDX_MASK\t0x00007F00\n#define IXGBE_QDE_IDX_SHIFT\t8\n#define IXGBE_QDE_WRITE\t\t0x00010000\n#define IXGBE_QDE_READ\t\t0x00020000\n\n#define IXGBE_TXD_POPTS_IXSM\t0x01 /* Insert IP checksum */\n#define IXGBE_TXD_POPTS_TXSM\t0x02 /* Insert TCP/UDP checksum */\n#define IXGBE_TXD_CMD_EOP\t0x01000000 /* End of Packet */\n#define IXGBE_TXD_CMD_IFCS\t0x02000000 /* Insert FCS (Ethernet CRC) */\n#define IXGBE_TXD_CMD_IC\t0x04000000 /* Insert Checksum */\n#define IXGBE_TXD_CMD_RS\t0x08000000 /* Report Status */\n#define IXGBE_TXD_CMD_DEXT\t0x20000000 /* Desc extension (0 = legacy) */\n#define IXGBE_TXD_CMD_VLE\t0x40000000 /* Add VLAN tag */\n#define IXGBE_TXD_STAT_DD\t0x00000001 /* Descriptor Done */\n\n#define IXGBE_RXDADV_IPSEC_STATUS_SECP\t\t0x00020000\n#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000\n#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH\t0x10000000\n#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED\t0x18000000\n#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK\t0x18000000\n/* Multiple Transmit Queue Command Register */\n#define IXGBE_MTQC_RT_ENA\t0x1 /* DCB Enable */\n#define IXGBE_MTQC_VT_ENA\t0x2 /* VMDQ2 Enable */\n#define IXGBE_MTQC_64Q_1PB\t0x0 /* 64 queues 1 pack buffer */\n#define IXGBE_MTQC_32VF\t\t0x8 /* 4 TX Queues per pool w/32VF's */\n#define IXGBE_MTQC_64VF\t\t0x4 /* 2 TX Queues per pool w/64VF's */\n#define IXGBE_MTQC_4TC_4TQ\t0x8 /* 4 TC if RT_ENA and VT_ENA */\n#define IXGBE_MTQC_8TC_8TQ\t0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */\n\n/* Receive Descriptor bit definitions */\n#define IXGBE_RXD_STAT_DD\t0x01 /* Descriptor Done */\n#define IXGBE_RXD_STAT_EOP\t0x02 /* End of Packet */\n#define IXGBE_RXD_STAT_FLM\t0x04 /* FDir Match */\n#define IXGBE_RXD_STAT_VP\t0x08 /* IEEE VLAN Packet */\n#define IXGBE_RXDADV_NEXTP_MASK\t0x000FFFF0 /* Next Descriptor Index */\n#define IXGBE_RXDADV_NEXTP_SHIFT\t0x00000004\n#define IXGBE_RXD_STAT_UDPCS\t0x10 /* UDP xsum calculated */\n#define IXGBE_RXD_STAT_L4CS\t0x20 /* L4 xsum calculated */\n#define IXGBE_RXD_STAT_IPCS\t0x40 /* IP xsum calculated */\n#define IXGBE_RXD_STAT_PIF\t0x80 /* passed in-exact filter */\n#define IXGBE_RXD_STAT_CRCV\t0x100 /* Speculative CRC Valid */\n#define IXGBE_RXD_STAT_OUTERIPCS\t0x100 /* Cloud IP xsum calculated */\n#define IXGBE_RXD_STAT_VEXT\t0x200 /* 1st VLAN found */\n#define IXGBE_RXD_STAT_UDPV\t0x400 /* Valid UDP checksum */\n#define IXGBE_RXD_STAT_DYNINT\t0x800 /* Pkt caused INT via DYNINT */\n#define IXGBE_RXD_STAT_LLINT\t0x800 /* Pkt caused Low Latency Interrupt */\n#define IXGBE_RXD_STAT_TSIP\t0x08000 /* Time Stamp in packet buffer */\n#define IXGBE_RXD_STAT_TS\t0x10000 /* Time Stamp */\n#define IXGBE_RXD_STAT_SECP\t0x20000 /* Security Processing */\n#define IXGBE_RXD_STAT_LB\t0x40000 /* Loopback Status */\n#define IXGBE_RXD_STAT_ACK\t0x8000 /* ACK Packet indication */\n#define IXGBE_RXD_ERR_CE\t0x01 /* CRC Error */\n#define IXGBE_RXD_ERR_LE\t0x02 /* Length Error */\n#define IXGBE_RXD_ERR_PE\t0x08 /* Packet Error */\n#define IXGBE_RXD_ERR_OSE\t0x10 /* Oversize Error */\n#define IXGBE_RXD_ERR_USE\t0x20 /* Undersize Error */\n#define IXGBE_RXD_ERR_TCPE\t0x40 /* TCP/UDP Checksum Error */\n#define IXGBE_RXD_ERR_IPE\t0x80 /* IP Checksum Error */\n#define IXGBE_RXDADV_ERR_MASK\t\t0xfff00000 /* RDESC.ERRORS mask */\n#define IXGBE_RXDADV_ERR_SHIFT\t\t20 /* RDESC.ERRORS shift */\n#define IXGBE_RXDADV_ERR_OUTERIPER\t0x04000000 /* CRC IP Header error */\n#define IXGBE_RXDADV_ERR_RXE\t\t0x20000000 /* Any MAC Error */\n#define IXGBE_RXDADV_ERR_FCEOFE\t\t0x80000000 /* FCEOFe/IPE */\n#define IXGBE_RXDADV_ERR_FCERR\t\t0x00700000 /* FCERR/FDIRERR */\n#define IXGBE_RXDADV_ERR_FDIR_LEN\t0x00100000 /* FDIR Length error */\n#define IXGBE_RXDADV_ERR_FDIR_DROP\t0x00200000 /* FDIR Drop error */\n#define IXGBE_RXDADV_ERR_FDIR_COLL\t0x00400000 /* FDIR Collision error */\n#define IXGBE_RXDADV_ERR_HBO\t0x00800000 /*Header Buffer Overflow */\n#define IXGBE_RXDADV_ERR_CE\t0x01000000 /* CRC Error */\n#define IXGBE_RXDADV_ERR_LE\t0x02000000 /* Length Error */\n#define IXGBE_RXDADV_ERR_PE\t0x08000000 /* Packet Error */\n#define IXGBE_RXDADV_ERR_OSE\t0x10000000 /* Oversize Error */\n#define IXGBE_RXDADV_ERR_USE\t0x20000000 /* Undersize Error */\n#define IXGBE_RXDADV_ERR_TCPE\t0x40000000 /* TCP/UDP Checksum Error */\n#define IXGBE_RXDADV_ERR_IPE\t0x80000000 /* IP Checksum Error */\n#define IXGBE_RXD_VLAN_ID_MASK\t0x0FFF /* VLAN ID is in lower 12 bits */\n#define IXGBE_RXD_PRI_MASK\t0xE000 /* Priority is in upper 3 bits */\n#define IXGBE_RXD_PRI_SHIFT\t13\n#define IXGBE_RXD_CFI_MASK\t0x1000 /* CFI is bit 12 */\n#define IXGBE_RXD_CFI_SHIFT\t12\n\n#define IXGBE_RXDADV_STAT_DD\t\tIXGBE_RXD_STAT_DD /* Done */\n#define IXGBE_RXDADV_STAT_EOP\t\tIXGBE_RXD_STAT_EOP /* End of Packet */\n#define IXGBE_RXDADV_STAT_FLM\t\tIXGBE_RXD_STAT_FLM /* FDir Match */\n#define IXGBE_RXDADV_STAT_VP\t\tIXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */\n#define IXGBE_RXDADV_STAT_MASK\t\t0x000fffff /* Stat/NEXTP: bit 0-19 */\n#define IXGBE_RXDADV_STAT_FCEOFS\t0x00000040 /* FCoE EOF/SOF Stat */\n#define IXGBE_RXDADV_STAT_FCSTAT\t0x00000030 /* FCoE Pkt Stat */\n#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH\t0x00000000 /* 00: No Ctxt Match */\n#define IXGBE_RXDADV_STAT_FCSTAT_NODDP\t0x00000010 /* 01: Ctxt w/o DDP */\n#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP\t0x00000020 /* 10: Recv. FCP_RSP */\n#define IXGBE_RXDADV_STAT_FCSTAT_DDP\t0x00000030 /* 11: Ctxt w/ DDP */\n#define IXGBE_RXDADV_STAT_TS\t\t0x00010000 /* IEEE1588 Time Stamp */\n#define IXGBE_RXDADV_STAT_TSIP\t\t0x00008000 /* Time Stamp in packet buffer */\n\n/* PSRTYPE bit definitions */\n#define IXGBE_PSRTYPE_TCPHDR\t0x00000010\n#define IXGBE_PSRTYPE_UDPHDR\t0x00000020\n#define IXGBE_PSRTYPE_IPV4HDR\t0x00000100\n#define IXGBE_PSRTYPE_IPV6HDR\t0x00000200\n#define IXGBE_PSRTYPE_L2HDR\t0x00001000\n\n/* SRRCTL bit definitions */\n#define IXGBE_SRRCTL_BSIZEPKT_SHIFT\t10 /* so many KBs */\n#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT\t2 /* 64byte resolution (>> 6)\n\t\t\t\t\t * + at bit 8 offset (<< 8)\n\t\t\t\t\t * = (<< 2)\n\t\t\t\t\t */\n#define IXGBE_SRRCTL_RDMTS_SHIFT\t22\n#define IXGBE_SRRCTL_RDMTS_MASK\t\t0x01C00000\n#define IXGBE_SRRCTL_DROP_EN\t\t0x10000000\n#define IXGBE_SRRCTL_BSIZEPKT_MASK\t0x0000007F\n#define IXGBE_SRRCTL_BSIZEHDR_MASK\t0x00003F00\n#define IXGBE_SRRCTL_DESCTYPE_LEGACY\t0x00000000\n#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000\n#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT\t0x04000000\n#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000\n#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000\n#define IXGBE_SRRCTL_DESCTYPE_MASK\t0x0E000000\n\n#define IXGBE_RXDPS_HDRSTAT_HDRSP\t0x00008000\n#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK\t0x000003FF\n\n#define IXGBE_RXDADV_RSSTYPE_MASK\t0x0000000F\n#define IXGBE_RXDADV_PKTTYPE_MASK\t0x0000FFF0\n#define IXGBE_RXDADV_PKTTYPE_MASK_EX\t0x0001FFF0\n#define IXGBE_RXDADV_HDRBUFLEN_MASK\t0x00007FE0\n#define IXGBE_RXDADV_RSCCNT_MASK\t0x001E0000\n#define IXGBE_RXDADV_RSCCNT_SHIFT\t17\n#define IXGBE_RXDADV_HDRBUFLEN_SHIFT\t5\n#define IXGBE_RXDADV_SPLITHEADER_EN\t0x00001000\n#define IXGBE_RXDADV_SPH\t\t0x8000\n\n/* RSS Hash results */\n#define IXGBE_RXDADV_RSSTYPE_NONE\t0x00000000\n#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP\t0x00000001\n#define IXGBE_RXDADV_RSSTYPE_IPV4\t0x00000002\n#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP\t0x00000003\n#define IXGBE_RXDADV_RSSTYPE_IPV6_EX\t0x00000004\n#define IXGBE_RXDADV_RSSTYPE_IPV6\t0x00000005\n#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006\n#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP\t0x00000007\n#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP\t0x00000008\n#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009\n\n/* RSS Packet Types as indicated in the receive descriptor. */\n#define IXGBE_RXDADV_PKTTYPE_NONE\t0x00000000\n#define IXGBE_RXDADV_PKTTYPE_IPV4\t0x00000010 /* IPv4 hdr present */\n#define IXGBE_RXDADV_PKTTYPE_IPV4_EX\t0x00000020 /* IPv4 hdr + extensions */\n#define IXGBE_RXDADV_PKTTYPE_IPV6\t0x00000040 /* IPv6 hdr present */\n#define IXGBE_RXDADV_PKTTYPE_IPV6_EX\t0x00000080 /* IPv6 hdr + extensions */\n#define IXGBE_RXDADV_PKTTYPE_TCP\t0x00000100 /* TCP hdr present */\n#define IXGBE_RXDADV_PKTTYPE_UDP\t0x00000200 /* UDP hdr present */\n#define IXGBE_RXDADV_PKTTYPE_SCTP\t0x00000400 /* SCTP hdr present */\n#define IXGBE_RXDADV_PKTTYPE_NFS\t0x00000800 /* NFS hdr present */\n#define IXGBE_RXDADV_PKTTYPE_VXLAN\t0x00000800 /* VXLAN hdr present */\n#define IXGBE_RXDADV_PKTTYPE_TUNNEL\t0x00010000 /* Tunnel type */\n#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP\t0x00001000 /* IPSec ESP */\n#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH\t0x00002000 /* IPSec AH */\n#define IXGBE_RXDADV_PKTTYPE_LINKSEC\t0x00004000 /* LinkSec Encap */\n#define IXGBE_RXDADV_PKTTYPE_ETQF\t0x00008000 /* PKTTYPE is ETQF index */\n#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK\t0x00000070 /* ETQF has 8 indices */\n#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT\t4 /* Right-shift 4 bits */\n\n/* Security Processing bit Indication */\n#define IXGBE_RXDADV_LNKSEC_STATUS_SECP\t\t0x00020000\n#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH\t0x08000000\n#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR\t0x10000000\n#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK\t0x18000000\n#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG\t0x18000000\n\n/* Masks to determine if packets should be dropped due to frame errors */\n#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \\\n\t\t\t\tIXGBE_RXD_ERR_CE | \\\n\t\t\t\tIXGBE_RXD_ERR_LE | \\\n\t\t\t\tIXGBE_RXD_ERR_PE | \\\n\t\t\t\tIXGBE_RXD_ERR_OSE | \\\n\t\t\t\tIXGBE_RXD_ERR_USE)\n\n#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \\\n\t\t\t\tIXGBE_RXDADV_ERR_CE | \\\n\t\t\t\tIXGBE_RXDADV_ERR_LE | \\\n\t\t\t\tIXGBE_RXDADV_ERR_PE | \\\n\t\t\t\tIXGBE_RXDADV_ERR_OSE | \\\n\t\t\t\tIXGBE_RXDADV_ERR_USE)\n\n#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599\tIXGBE_RXDADV_ERR_RXE\n\n/* Multicast bit mask */\n#define IXGBE_MCSTCTRL_MFE\t0x4\n\n/* Number of Transmit and Receive Descriptors must be a multiple of 8 */\n#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE\t8\n#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE\t8\n#define IXGBE_REQ_TX_BUFFER_GRANULARITY\t\t1024\n\n/* Vlan-specific macros */\n#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK\t0x0FFF /* VLAN ID in lower 12 bits */\n#define IXGBE_RX_DESC_SPECIAL_PRI_MASK\t0xE000 /* Priority in upper 3 bits */\n#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT\t0x000D /* Priority in upper 3 of 16 */\n#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT\tIXGBE_RX_DESC_SPECIAL_PRI_SHIFT\n\n/* SR-IOV specific macros */\n#define IXGBE_MBVFICR_INDEX(vf_number)\t(vf_number >> 4)\n#define IXGBE_MBVFICR(_i)\t\t(0x00710 + ((_i) * 4))\n#define IXGBE_VFLRE(_i)\t\t\t(((_i & 1) ? 0x001C0 : 0x00600))\n#define IXGBE_VFLREC(_i)\t\t (0x00700 + ((_i) * 4))\n/* Translated register #defines */\n#define IXGBE_PVFCTRL(P)\t(0x00300 + (4 * (P)))\n#define IXGBE_PVFSTATUS(P)\t(0x00008 + (0 * (P)))\n#define IXGBE_PVFLINKS(P)\t(0x042A4 + (0 * (P)))\n#define IXGBE_PVFRTIMER(P)\t(0x00048 + (0 * (P)))\n#define IXGBE_PVFMAILBOX(P)\t(0x04C00 + (4 * (P)))\n#define IXGBE_PVFRXMEMWRAP(P)\t(0x03190 + (0 * (P)))\n#define IXGBE_PVTEICR(P)\t(0x00B00 + (4 * (P)))\n#define IXGBE_PVTEICS(P)\t(0x00C00 + (4 * (P)))\n#define IXGBE_PVTEIMS(P)\t(0x00D00 + (4 * (P)))\n#define IXGBE_PVTEIMC(P)\t(0x00E00 + (4 * (P)))\n#define IXGBE_PVTEIAC(P)\t(0x00F00 + (4 * (P)))\n#define IXGBE_PVTEIAM(P)\t(0x04D00 + (4 * (P)))\n#define IXGBE_PVTEITR(P)\t(((P) < 24) ? (0x00820 + ((P) * 4)) : \\\n\t\t\t\t (0x012300 + (((P) - 24) * 4)))\n#define IXGBE_PVTIVAR(P)\t(0x12500 + (4 * (P)))\n#define IXGBE_PVTIVAR_MISC(P)\t(0x04E00 + (4 * (P)))\n#define IXGBE_PVTRSCINT(P)\t(0x12000 + (4 * (P)))\n#define IXGBE_VFPBACL(P)\t(0x110C8 + (4 * (P)))\n#define IXGBE_PVFRDBAL(P)\t((P < 64) ? (0x01000 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D000 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFRDBAH(P)\t((P < 64) ? (0x01004 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D004 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFRDLEN(P)\t((P < 64) ? (0x01008 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D008 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFRDH(P)\t\t((P < 64) ? (0x01010 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D010 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFRDT(P)\t\t((P < 64) ? (0x01018 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D018 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFRXDCTL(P)\t((P < 64) ? (0x01028 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D028 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFSRRCTL(P)\t((P < 64) ? (0x01014 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D014 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFPSRTYPE(P)\t(0x0EA00 + (4 * (P)))\n#define IXGBE_PVFTDBAL(P)\t(0x06000 + (0x40 * (P)))\n#define IXGBE_PVFTDBAH(P)\t(0x06004 + (0x40 * (P)))\n#define IXGBE_PVFTTDLEN(P)\t(0x06008 + (0x40 * (P)))\n#define IXGBE_PVFTDH(P)\t\t(0x06010 + (0x40 * (P)))\n#define IXGBE_PVFTDT(P)\t\t(0x06018 + (0x40 * (P)))\n#define IXGBE_PVFTXDCTL(P)\t(0x06028 + (0x40 * (P)))\n#define IXGBE_PVFTDWBAL(P)\t(0x06038 + (0x40 * (P)))\n#define IXGBE_PVFTDWBAH(P)\t(0x0603C + (0x40 * (P)))\n#define IXGBE_PVFDCA_RXCTRL(P)\t(((P) < 64) ? (0x0100C + (0x40 * (P))) \\\n\t\t\t\t : (0x0D00C + (0x40 * ((P) - 64))))\n#define IXGBE_PVFDCA_TXCTRL(P)\t(0x0600C + (0x40 * (P)))\n#define IXGBE_PVFGPRC(x)\t(0x0101C + (0x40 * (x)))\n#define IXGBE_PVFGPTC(x)\t(0x08300 + (0x04 * (x)))\n#define IXGBE_PVFGORC_LSB(x)\t(0x01020 + (0x40 * (x)))\n#define IXGBE_PVFGORC_MSB(x)\t(0x0D020 + (0x40 * (x)))\n#define IXGBE_PVFGOTC_LSB(x)\t(0x08400 + (0x08 * (x)))\n#define IXGBE_PVFGOTC_MSB(x)\t(0x08404 + (0x08 * (x)))\n#define IXGBE_PVFMPRC(x)\t(0x0D01C + (0x40 * (x)))\n\n#define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \\\n\t\t(IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))\n#define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \\\n\t\t(IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))\n\n#define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \\\n\t\t(IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))\n#define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \\\n\t\t(IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))\n\n/* Little Endian defines */\n#ifndef __le16\n#define __le16 u16\n#endif\n#ifndef __le32\n#define __le32 u32\n#endif\n#ifndef __le64\n#define __le64 u64\n\n#endif\n#ifndef __be16\n/* Big Endian defines */\n#define __be16 u16\n#define __be32 u32\n#define __be64 u64\n\n#endif\nenum ixgbe_fdir_pballoc_type {\n\tIXGBE_FDIR_PBALLOC_NONE = 0,\n\tIXGBE_FDIR_PBALLOC_64K = 1,\n\tIXGBE_FDIR_PBALLOC_128K = 2,\n\tIXGBE_FDIR_PBALLOC_256K = 3,\n};\n\n/* Flow Director register values */\n#define IXGBE_FDIRCTRL_PBALLOC_64K\t\t0x00000001\n#define IXGBE_FDIRCTRL_PBALLOC_128K\t\t0x00000002\n#define IXGBE_FDIRCTRL_PBALLOC_256K\t\t0x00000003\n#define IXGBE_FDIRCTRL_INIT_DONE\t\t0x00000008\n#define IXGBE_FDIRCTRL_PERFECT_MATCH\t\t0x00000010\n#define IXGBE_FDIRCTRL_REPORT_STATUS\t\t0x00000020\n#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS\t0x00000080\n#define IXGBE_FDIRCTRL_DROP_Q_SHIFT\t\t8\n#define IXGBE_FDIRCTRL_FLEX_SHIFT\t\t16\n#define IXGBE_FDIRCTRL_FILTERMODE_SHIFT\t\t21\n#define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN\t0x0001 /* bit 23:21, 001b */\n#define IXGBE_FDIRCTRL_FILTERMODE_CLOUD\t\t0x0002 /* bit 23:21, 010b */\n#define IXGBE_FDIRCTRL_SEARCHLIM\t\t0x00800000\n#define IXGBE_FDIRCTRL_FILTERMODE_MASK\t\t0x00E00000\n#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT\t\t24\n#define IXGBE_FDIRCTRL_FULL_THRESH_MASK\t\t0xF0000000\n#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT\t28\n\n#define IXGBE_FDIRTCPM_DPORTM_SHIFT\t\t16\n#define IXGBE_FDIRUDPM_DPORTM_SHIFT\t\t16\n#define IXGBE_FDIRIP6M_DIPM_SHIFT\t\t16\n#define IXGBE_FDIRM_VLANID\t\t\t0x00000001\n#define IXGBE_FDIRM_VLANP\t\t\t0x00000002\n#define IXGBE_FDIRM_POOL\t\t\t0x00000004\n#define IXGBE_FDIRM_L4P\t\t\t\t0x00000008\n#define IXGBE_FDIRM_FLEX\t\t\t0x00000010\n#define IXGBE_FDIRM_DIPv6\t\t\t0x00000020\n#define IXGBE_FDIRM_L3P\t\t\t\t0x00000040\n\n#define IXGBE_FDIRIP6M_INNER_MAC\t0x03F0 /* bit 9:4 */\n#define IXGBE_FDIRIP6M_TUNNEL_TYPE\t0x0800 /* bit 11 */\n#define IXGBE_FDIRIP6M_TNI_VNI\t\t0xF000 /* bit 15:12 */\n#define IXGBE_FDIRIP6M_TNI_VNI_24\t0x1000 /* bit 12 */\n#define IXGBE_FDIRIP6M_ALWAYS_MASK\t0x040F /* bit 10, 3:0 */\n\n#define IXGBE_FDIRFREE_FREE_MASK\t\t0xFFFF\n#define IXGBE_FDIRFREE_FREE_SHIFT\t\t0\n#define IXGBE_FDIRFREE_COLL_MASK\t\t0x7FFF0000\n#define IXGBE_FDIRFREE_COLL_SHIFT\t\t16\n#define IXGBE_FDIRLEN_MAXLEN_MASK\t\t0x3F\n#define IXGBE_FDIRLEN_MAXLEN_SHIFT\t\t0\n#define IXGBE_FDIRLEN_MAXHASH_MASK\t\t0x7FFF0000\n#define IXGBE_FDIRLEN_MAXHASH_SHIFT\t\t16\n#define IXGBE_FDIRUSTAT_ADD_MASK\t\t0xFFFF\n#define IXGBE_FDIRUSTAT_ADD_SHIFT\t\t0\n#define IXGBE_FDIRUSTAT_REMOVE_MASK\t\t0xFFFF0000\n#define IXGBE_FDIRUSTAT_REMOVE_SHIFT\t\t16\n#define IXGBE_FDIRFSTAT_FADD_MASK\t\t0x00FF\n#define IXGBE_FDIRFSTAT_FADD_SHIFT\t\t0\n#define IXGBE_FDIRFSTAT_FREMOVE_MASK\t\t0xFF00\n#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT\t\t8\n#define IXGBE_FDIRPORT_DESTINATION_SHIFT\t16\n#define IXGBE_FDIRVLAN_FLEX_SHIFT\t\t16\n#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT\t15\n#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT\t16\n\n#define IXGBE_FDIRCMD_CMD_MASK\t\t\t0x00000003\n#define IXGBE_FDIRCMD_CMD_ADD_FLOW\t\t0x00000001\n#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW\t\t0x00000002\n#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT\t0x00000003\n#define IXGBE_FDIRCMD_FILTER_VALID\t\t0x00000004\n#define IXGBE_FDIRCMD_FILTER_UPDATE\t\t0x00000008\n#define IXGBE_FDIRCMD_IPv6DMATCH\t\t0x00000010\n#define IXGBE_FDIRCMD_L4TYPE_UDP\t\t0x00000020\n#define IXGBE_FDIRCMD_L4TYPE_TCP\t\t0x00000040\n#define IXGBE_FDIRCMD_L4TYPE_SCTP\t\t0x00000060\n#define IXGBE_FDIRCMD_IPV6\t\t\t0x00000080\n#define IXGBE_FDIRCMD_CLEARHT\t\t\t0x00000100\n#define IXGBE_FDIRCMD_DROP\t\t\t0x00000200\n#define IXGBE_FDIRCMD_INT\t\t\t0x00000400\n#define IXGBE_FDIRCMD_LAST\t\t\t0x00000800\n#define IXGBE_FDIRCMD_COLLISION\t\t\t0x00001000\n#define IXGBE_FDIRCMD_QUEUE_EN\t\t\t0x00008000\n#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT\t\t5\n#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT\t\t16\n#define IXGBE_FDIRCMD_TUNNEL_FILTER_SHIFT\t23\n#define IXGBE_FDIRCMD_VT_POOL_SHIFT\t\t24\n#define IXGBE_FDIR_INIT_DONE_POLL\t\t10\n#define IXGBE_FDIRCMD_CMD_POLL\t\t\t10\n#define IXGBE_FDIRCMD_TUNNEL_FILTER\t\t0x00800000\n#define IXGBE_FDIR_DROP_QUEUE\t\t\t127\n\n\n/* Manageablility Host Interface defines */\n#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH\t1792 /* Num of bytes in range */\n#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH\t448 /* Num of dwords in range */\n#define IXGBE_HI_COMMAND_TIMEOUT\t500 /* Process HI command limit */\n#define IXGBE_HI_FLASH_ERASE_TIMEOUT\t1000 /* Process Erase command limit */\n#define IXGBE_HI_FLASH_UPDATE_TIMEOUT\t5000 /* Process Update command limit */\n#define IXGBE_HI_FLASH_APPLY_TIMEOUT\t0 /* Process Apply command limit */\n#define IXGBE_HI_PHY_MGMT_REQ_TIMEOUT\t2000 /* Wait up to 2 seconds */\n\n/* CEM Support */\n#define FW_CEM_HDR_LEN\t\t\t0x4\n#define FW_CEM_CMD_DRIVER_INFO\t\t0xDD\n#define FW_CEM_CMD_DRIVER_INFO_LEN\t0x5\n#define FW_CEM_CMD_RESERVED\t\t0X0\n#define FW_CEM_UNUSED_VER\t\t0x0\n#define FW_CEM_MAX_RETRIES\t\t3\n#define FW_CEM_RESP_STATUS_SUCCESS\t0x1\n#define FW_READ_SHADOW_RAM_CMD\t\t0x31\n#define FW_READ_SHADOW_RAM_LEN\t\t0x6\n#define FW_WRITE_SHADOW_RAM_CMD\t\t0x33\n#define FW_WRITE_SHADOW_RAM_LEN\t\t0xA /* 8 plus 1 WORD to write */\n#define FW_SHADOW_RAM_DUMP_CMD\t\t0x36\n#define FW_SHADOW_RAM_DUMP_LEN\t\t0\n#define FW_DEFAULT_CHECKSUM\t\t0xFF /* checksum always 0xFF */\n#define FW_NVM_DATA_OFFSET\t\t3\n#define FW_MAX_READ_BUFFER_SIZE\t\t1024\n#define FW_DISABLE_RXEN_CMD\t\t0xDE\n#define FW_DISABLE_RXEN_LEN\t\t0x1\n#define FW_PHY_MGMT_REQ_CMD\t\t0x20\n/* Host Interface Command Structures */\n\nstruct ixgbe_hic_hdr {\n\tu8 cmd;\n\tu8 buf_len;\n\tunion {\n\t\tu8 cmd_resv;\n\t\tu8 ret_status;\n\t} cmd_or_resp;\n\tu8 checksum;\n};\n\nstruct ixgbe_hic_hdr2_req {\n\tu8 cmd;\n\tu8 buf_lenh;\n\tu8 buf_lenl;\n\tu8 checksum;\n};\n\nstruct ixgbe_hic_hdr2_rsp {\n\tu8 cmd;\n\tu8 buf_lenl;\n\tu8 buf_lenh_status;\t/* 7-5: high bits of buf_len, 4-0: status */\n\tu8 checksum;\n};\n\nunion ixgbe_hic_hdr2 {\n\tstruct ixgbe_hic_hdr2_req req;\n\tstruct ixgbe_hic_hdr2_rsp rsp;\n};\n\nstruct ixgbe_hic_drv_info {\n\tstruct ixgbe_hic_hdr hdr;\n\tu8 port_num;\n\tu8 ver_sub;\n\tu8 ver_build;\n\tu8 ver_min;\n\tu8 ver_maj;\n\tu8 pad; /* end spacing to ensure length is mult. of dword */\n\tu16 pad2; /* end spacing to ensure length is mult. of dword2 */\n};\n\n/* These need to be dword aligned */\nstruct ixgbe_hic_read_shadow_ram {\n\tunion ixgbe_hic_hdr2 hdr;\n\tu32 address;\n\tu16 length;\n\tu16 pad2;\n\tu16 data;\n\tu16 pad3;\n};\n\nstruct ixgbe_hic_write_shadow_ram {\n\tunion ixgbe_hic_hdr2 hdr;\n\tu32 address;\n\tu16 length;\n\tu16 pad2;\n\tu16 data;\n\tu16 pad3;\n};\n\nstruct ixgbe_hic_disable_rxen {\n\tstruct ixgbe_hic_hdr hdr;\n\tu8 port_number;\n\tu8 pad2;\n\tu16 pad3;\n};\n\n\n/* Transmit Descriptor - Legacy */\nstruct ixgbe_legacy_tx_desc {\n\tu64 buffer_addr; /* Address of the descriptor's data buffer */\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\t__le16 length; /* Data buffer length */\n\t\t\tu8 cso; /* Checksum offset */\n\t\t\tu8 cmd; /* Descriptor control */\n\t\t} flags;\n\t} lower;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status; /* Descriptor status */\n\t\t\tu8 css; /* Checksum start */\n\t\t\t__le16 vlan;\n\t\t} fields;\n\t} upper;\n};\n\n/* Transmit Descriptor - Advanced */\nunion ixgbe_adv_tx_desc {\n\tstruct {\n\t\t__le64 buffer_addr; /* Address of descriptor's data buf */\n\t\t__le32 cmd_type_len;\n\t\t__le32 olinfo_status;\n\t} read;\n\tstruct {\n\t\t__le64 rsvd; /* Reserved */\n\t\t__le32 nxtseq_seed;\n\t\t__le32 status;\n\t} wb;\n};\n\n/* Receive Descriptor - Legacy */\nstruct ixgbe_legacy_rx_desc {\n\t__le64 buffer_addr; /* Address of the descriptor's data buffer */\n\t__le16 length; /* Length of data DMAed into data buffer */\n\t__le16 csum; /* Packet checksum */\n\tu8 status; /* Descriptor status */\n\tu8 errors; /* Descriptor Errors */\n\t__le16 vlan;\n};\n\n/* Receive Descriptor - Advanced */\nunion ixgbe_adv_rx_desc {\n\tstruct {\n\t\t__le64 pkt_addr; /* Packet buffer address */\n\t\t__le64 hdr_addr; /* Header buffer address */\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\t__le32 data;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 pkt_info; /* RSS, Pkt type */\n\t\t\t\t\t__le16 hdr_info; /* Splithdr, hdrlen */\n\t\t\t\t} hs_rss;\n\t\t\t} lo_dword;\n\t\t\tunion {\n\t\t\t\t__le32 rss; /* RSS Hash */\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id; /* IP id */\n\t\t\t\t\t__le16 csum; /* Packet Checksum */\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error; /* ext status/error */\n\t\t\t__le16 length; /* Packet length */\n\t\t\t__le16 vlan; /* VLAN tag */\n\t\t} upper;\n\t} wb; /* writeback */\n};\n\n/* Context descriptors */\nstruct ixgbe_adv_tx_context_desc {\n\t__le32 vlan_macip_lens;\n\t__le32 seqnum_seed;\n\t__le32 type_tucmd_mlhl;\n\t__le32 mss_l4len_idx;\n};\n\n/* Adv Transmit Descriptor Config Masks */\n#define IXGBE_ADVTXD_DTALEN_MASK\t0x0000FFFF /* Data buf length(bytes) */\n#define IXGBE_ADVTXD_MAC_LINKSEC\t0x00040000 /* Insert LinkSec */\n#define IXGBE_ADVTXD_MAC_TSTAMP\t\t0x00080000 /* IEEE1588 time stamp */\n#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */\n#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK\t0x000001FF /* IPSec ESP length */\n#define IXGBE_ADVTXD_DTYP_MASK\t\t0x00F00000 /* DTYP mask */\n#define IXGBE_ADVTXD_DTYP_CTXT\t\t0x00200000 /* Adv Context Desc */\n#define IXGBE_ADVTXD_DTYP_DATA\t\t0x00300000 /* Adv Data Descriptor */\n#define IXGBE_ADVTXD_DCMD_EOP\t\tIXGBE_TXD_CMD_EOP /* End of Packet */\n#define IXGBE_ADVTXD_DCMD_IFCS\t\tIXGBE_TXD_CMD_IFCS /* Insert FCS */\n#define IXGBE_ADVTXD_DCMD_RS\t\tIXGBE_TXD_CMD_RS /* Report Status */\n#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI\t0x10000000 /* DDP hdr type or iSCSI */\n#define IXGBE_ADVTXD_DCMD_DEXT\t\tIXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */\n#define IXGBE_ADVTXD_DCMD_VLE\t\tIXGBE_TXD_CMD_VLE /* VLAN pkt enable */\n#define IXGBE_ADVTXD_DCMD_TSE\t\t0x80000000 /* TCP Seg enable */\n#define IXGBE_ADVTXD_STAT_DD\t\tIXGBE_TXD_STAT_DD /* Descriptor Done */\n#define IXGBE_ADVTXD_STAT_SN_CRC\t0x00000002 /* NXTSEQ/SEED pres in WB */\n#define IXGBE_ADVTXD_STAT_RSV\t\t0x0000000C /* STA Reserved */\n#define IXGBE_ADVTXD_IDX_SHIFT\t\t4 /* Adv desc Index shift */\n#define IXGBE_ADVTXD_CC\t\t\t0x00000080 /* Check Context */\n#define IXGBE_ADVTXD_POPTS_SHIFT\t8 /* Adv desc POPTS shift */\n#define IXGBE_ADVTXD_POPTS_IXSM\t\t(IXGBE_TXD_POPTS_IXSM << \\\n\t\t\t\t\t IXGBE_ADVTXD_POPTS_SHIFT)\n#define IXGBE_ADVTXD_POPTS_TXSM\t\t(IXGBE_TXD_POPTS_TXSM << \\\n\t\t\t\t\t IXGBE_ADVTXD_POPTS_SHIFT)\n#define IXGBE_ADVTXD_POPTS_ISCO_1ST\t0x00000000 /* 1st TSO of iSCSI PDU */\n#define IXGBE_ADVTXD_POPTS_ISCO_MDL\t0x00000800 /* Middle TSO of iSCSI PDU */\n#define IXGBE_ADVTXD_POPTS_ISCO_LAST\t0x00001000 /* Last TSO of iSCSI PDU */\n/* 1st&Last TSO-full iSCSI PDU */\n#define IXGBE_ADVTXD_POPTS_ISCO_FULL\t0x00001800\n#define IXGBE_ADVTXD_POPTS_RSV\t\t0x00002000 /* POPTS Reserved */\n#define IXGBE_ADVTXD_PAYLEN_SHIFT\t14 /* Adv desc PAYLEN shift */\n#define IXGBE_ADVTXD_MACLEN_SHIFT\t9 /* Adv ctxt desc mac len shift */\n#define IXGBE_ADVTXD_VLAN_SHIFT\t\t16 /* Adv ctxt vlan tag shift */\n#define IXGBE_ADVTXD_TUCMD_IPV4\t\t0x00000400 /* IP Packet Type: 1=IPv4 */\n#define IXGBE_ADVTXD_TUCMD_IPV6\t\t0x00000000 /* IP Packet Type: 0=IPv6 */\n#define IXGBE_ADVTXD_TUCMD_L4T_UDP\t0x00000000 /* L4 Packet TYPE of UDP */\n#define IXGBE_ADVTXD_TUCMD_L4T_TCP\t0x00000800 /* L4 Packet TYPE of TCP */\n#define IXGBE_ADVTXD_TUCMD_L4T_SCTP\t0x00001000 /* L4 Packet TYPE of SCTP */\n#define IXGBE_ADVTXD_TUCMD_MKRREQ\t0x00002000 /* req Markers and CRC */\n#define IXGBE_ADVTXD_POPTS_IPSEC\t0x00000400 /* IPSec offload request */\n#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */\n#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */\n#define IXGBE_ADVTXT_TUCMD_FCOE\t\t0x00008000 /* FCoE Frame Type */\n#define IXGBE_ADVTXD_FCOEF_EOF_MASK\t(0x3 << 10) /* FC EOF index */\n#define IXGBE_ADVTXD_FCOEF_SOF\t\t((1 << 2) << 10) /* FC SOF index */\n#define IXGBE_ADVTXD_FCOEF_PARINC\t((1 << 3) << 10) /* Rel_Off in F_CTL */\n#define IXGBE_ADVTXD_FCOEF_ORIE\t\t((1 << 4) << 10) /* Orientation End */\n#define IXGBE_ADVTXD_FCOEF_ORIS\t\t((1 << 5) << 10) /* Orientation Start */\n#define IXGBE_ADVTXD_FCOEF_EOF_N\t(0x0 << 10) /* 00: EOFn */\n#define IXGBE_ADVTXD_FCOEF_EOF_T\t(0x1 << 10) /* 01: EOFt */\n#define IXGBE_ADVTXD_FCOEF_EOF_NI\t(0x2 << 10) /* 10: EOFni */\n#define IXGBE_ADVTXD_FCOEF_EOF_A\t(0x3 << 10) /* 11: EOFa */\n#define IXGBE_ADVTXD_L4LEN_SHIFT\t8 /* Adv ctxt L4LEN shift */\n#define IXGBE_ADVTXD_MSS_SHIFT\t\t16 /* Adv ctxt MSS shift */\n\n#define IXGBE_ADVTXD_OUTER_IPLEN\t16 /* Adv ctxt OUTERIPLEN shift */\n#define IXGBE_ADVTXD_TUNNEL_LEN \t24 /* Adv ctxt TUNNELLEN shift */\n#define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT\t16 /* Adv Tx Desc Tunnel Type shift */\n#define IXGBE_ADVTXD_OUTERIPCS_SHIFT\t17 /* Adv Tx Desc OUTERIPCS Shift */\n#define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE\t1 /* Adv Tx Desc Tunnel Type NVGRE */\n\n/* Autonegotiation advertised speeds */\ntypedef u32 ixgbe_autoneg_advertised;\n/* Link speed */\ntypedef u32 ixgbe_link_speed;\n#define IXGBE_LINK_SPEED_UNKNOWN\t0\n#define IXGBE_LINK_SPEED_100_FULL\t0x0008\n#define IXGBE_LINK_SPEED_1GB_FULL\t0x0020\n#define IXGBE_LINK_SPEED_2_5GB_FULL\t0x0400\n#define IXGBE_LINK_SPEED_5GB_FULL\t0x0800\n#define IXGBE_LINK_SPEED_10GB_FULL\t0x0080\n#define IXGBE_LINK_SPEED_82598_AUTONEG\t(IXGBE_LINK_SPEED_1GB_FULL | \\\n\t\t\t\t\t IXGBE_LINK_SPEED_10GB_FULL)\n#define IXGBE_LINK_SPEED_82599_AUTONEG\t(IXGBE_LINK_SPEED_100_FULL | \\\n\t\t\t\t\t IXGBE_LINK_SPEED_1GB_FULL | \\\n\t\t\t\t\t IXGBE_LINK_SPEED_10GB_FULL)\n\n/* Physical layer type */\ntypedef u32 ixgbe_physical_layer;\n#define IXGBE_PHYSICAL_LAYER_UNKNOWN\t\t0\n#define IXGBE_PHYSICAL_LAYER_10GBASE_T\t\t0x0001\n#define IXGBE_PHYSICAL_LAYER_1000BASE_T\t\t0x0002\n#define IXGBE_PHYSICAL_LAYER_100BASE_TX\t\t0x0004\n#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU\t0x0008\n#define IXGBE_PHYSICAL_LAYER_10GBASE_LR\t\t0x0010\n#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM\t0x0020\n#define IXGBE_PHYSICAL_LAYER_10GBASE_SR\t\t0x0040\n#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4\t0x0080\n#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4\t0x0100\n#define IXGBE_PHYSICAL_LAYER_1000BASE_KX\t0x0200\n#define IXGBE_PHYSICAL_LAYER_1000BASE_BX\t0x0400\n#define IXGBE_PHYSICAL_LAYER_10GBASE_KR\t\t0x0800\n#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI\t0x1000\n#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA\t0x2000\n#define IXGBE_PHYSICAL_LAYER_1000BASE_SX\t0x4000\n\n/* Flow Control Data Sheet defined values\n * Calculation and defines taken from 802.1bb Annex O\n */\n\n/* BitTimes (BT) conversion */\n#define IXGBE_BT2KB(BT)\t\t((BT + (8 * 1024 - 1)) / (8 * 1024))\n#define IXGBE_B2BT(BT)\t\t(BT * 8)\n\n/* Calculate Delay to respond to PFC */\n#define IXGBE_PFC_D\t672\n\n/* Calculate Cable Delay */\n#define IXGBE_CABLE_DC\t5556 /* Delay Copper */\n#define IXGBE_CABLE_DO\t5000 /* Delay Optical */\n\n/* Calculate Interface Delay X540 */\n#define IXGBE_PHY_DC\t25600 /* Delay 10G BASET */\n#define IXGBE_MAC_DC\t8192 /* Delay Copper XAUI interface */\n#define IXGBE_XAUI_DC\t(2 * 2048) /* Delay Copper Phy */\n\n#define IXGBE_ID_X540\t(IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)\n\n/* Calculate Interface Delay 82598, 82599 */\n#define IXGBE_PHY_D\t12800\n#define IXGBE_MAC_D\t4096\n#define IXGBE_XAUI_D\t(2 * 1024)\n\n#define IXGBE_ID\t(IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)\n\n/* Calculate Delay incurred from higher layer */\n#define IXGBE_HD\t6144\n\n/* Calculate PCI Bus delay for low thresholds */\n#define IXGBE_PCI_DELAY\t10000\n\n/* Calculate X540 delay value in bit times */\n#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \\\n\t\t\t((36 * \\\n\t\t\t (IXGBE_B2BT(_max_frame_link) + \\\n\t\t\t IXGBE_PFC_D + \\\n\t\t\t (2 * IXGBE_CABLE_DC) + \\\n\t\t\t (2 * IXGBE_ID_X540) + \\\n\t\t\t IXGBE_HD) / 25 + 1) + \\\n\t\t\t 2 * IXGBE_B2BT(_max_frame_tc))\n\n/* Calculate 82599, 82598 delay value in bit times */\n#define IXGBE_DV(_max_frame_link, _max_frame_tc) \\\n\t\t\t((36 * \\\n\t\t\t (IXGBE_B2BT(_max_frame_link) + \\\n\t\t\t IXGBE_PFC_D + \\\n\t\t\t (2 * IXGBE_CABLE_DC) + \\\n\t\t\t (2 * IXGBE_ID) + \\\n\t\t\t IXGBE_HD) / 25 + 1) + \\\n\t\t\t 2 * IXGBE_B2BT(_max_frame_tc))\n\n/* Calculate low threshold delay values */\n#define IXGBE_LOW_DV_X540(_max_frame_tc) \\\n\t\t\t(2 * IXGBE_B2BT(_max_frame_tc) + \\\n\t\t\t(36 * IXGBE_PCI_DELAY / 25) + 1)\n#define IXGBE_LOW_DV(_max_frame_tc) \\\n\t\t\t(2 * IXGBE_LOW_DV_X540(_max_frame_tc))\n\n/* Software ATR hash keys */\n#define IXGBE_ATR_BUCKET_HASH_KEY\t0x3DAD14E2\n#define IXGBE_ATR_SIGNATURE_HASH_KEY\t0x174D3614\n\n/* Software ATR input stream values and masks */\n#define IXGBE_ATR_HASH_MASK\t\t0x7fff\n#define IXGBE_ATR_L4TYPE_MASK\t\t0x3\n#define IXGBE_ATR_L4TYPE_UDP\t\t0x1\n#define IXGBE_ATR_L4TYPE_TCP\t\t0x2\n#define IXGBE_ATR_L4TYPE_SCTP\t\t0x3\n#define IXGBE_ATR_L4TYPE_IPV6_MASK\t0x4\n#define IXGBE_ATR_L4TYPE_TUNNEL_MASK\t0x10\nenum ixgbe_atr_flow_type {\n\tIXGBE_ATR_FLOW_TYPE_IPV4\t= 0x0,\n\tIXGBE_ATR_FLOW_TYPE_UDPV4\t= 0x1,\n\tIXGBE_ATR_FLOW_TYPE_TCPV4\t= 0x2,\n\tIXGBE_ATR_FLOW_TYPE_SCTPV4\t= 0x3,\n\tIXGBE_ATR_FLOW_TYPE_IPV6\t= 0x4,\n\tIXGBE_ATR_FLOW_TYPE_UDPV6\t= 0x5,\n\tIXGBE_ATR_FLOW_TYPE_TCPV6\t= 0x6,\n\tIXGBE_ATR_FLOW_TYPE_SCTPV6\t= 0x7,\n\tIXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4\t= 0x10,\n\tIXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4\t= 0x11,\n\tIXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4\t= 0x12,\n\tIXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4\t= 0x13,\n\tIXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6\t= 0x14,\n\tIXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6\t= 0x15,\n\tIXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6\t= 0x16,\n\tIXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6\t= 0x17,\n};\n\n/* Flow Director ATR input struct. */\nunion ixgbe_atr_input {\n\t/*\n\t * Byte layout in order, all values with MSB first:\n\t *\n\t * vm_pool\t- 1 byte\n\t * flow_type\t- 1 byte\n\t * vlan_id\t- 2 bytes\n\t * src_ip\t- 16 bytes\n\t * inner_mac\t- 6 bytes\n\t * cloud_mode\t- 2 bytes\n\t * tni_vni\t- 4 bytes\n\t * dst_ip\t- 16 bytes\n\t * src_port\t- 2 bytes\n\t * dst_port\t- 2 bytes\n\t * flex_bytes\t- 2 bytes\n\t * bkt_hash\t- 2 bytes\n\t */\n\tstruct {\n\t\tu8 vm_pool;\n\t\tu8 flow_type;\n\t\t__be16 vlan_id;\n\t\t__be32 dst_ip[4];\n\t\t__be32 src_ip[4];\n\t\tu8 inner_mac[6];\n\t\t__be16 tunnel_type;\n\t\t__be32 tni_vni;\n\t\t__be16 src_port;\n\t\t__be16 dst_port;\n\t\t__be16 flex_bytes;\n\t\t__be16 bkt_hash;\n\t} formatted;\n\t__be32 dword_stream[14];\n};\n\n/* Flow Director compressed ATR hash input struct */\nunion ixgbe_atr_hash_dword {\n\tstruct {\n\t\tu8 vm_pool;\n\t\tu8 flow_type;\n\t\t__be16 vlan_id;\n\t} formatted;\n\t__be32 ip;\n\tstruct {\n\t\t__be16 src;\n\t\t__be16 dst;\n\t} port;\n\t__be16 flex_bytes;\n\t__be32 dword;\n};\n\n\n#define IXGBE_MVALS_INIT(m)\t\\\n\tIXGBE_CAT(EEC, m),\t\t\\\n\tIXGBE_CAT(FLA, m),\t\t\\\n\tIXGBE_CAT(GRC, m),\t\t\\\n\tIXGBE_CAT(SRAMREL, m),\t\t\\\n\tIXGBE_CAT(FACTPS, m),\t\t\\\n\tIXGBE_CAT(SWSM, m),\t\t\\\n\tIXGBE_CAT(SWFW_SYNC, m),\t\\\n\tIXGBE_CAT(FWSM, m),\t\t\\\n\tIXGBE_CAT(SDP0_GPIEN, m),\t\\\n\tIXGBE_CAT(SDP1_GPIEN, m),\t\\\n\tIXGBE_CAT(SDP2_GPIEN, m),\t\\\n\tIXGBE_CAT(EICR_GPI_SDP0, m),\t\\\n\tIXGBE_CAT(EICR_GPI_SDP1, m),\t\\\n\tIXGBE_CAT(EICR_GPI_SDP2, m),\t\\\n\tIXGBE_CAT(CIAA, m),\t\t\\\n\tIXGBE_CAT(CIAD, m),\t\t\\\n\tIXGBE_CAT(I2C_CLK_IN, m),\t\\\n\tIXGBE_CAT(I2C_CLK_OUT, m),\t\\\n\tIXGBE_CAT(I2C_DATA_IN, m),\t\\\n\tIXGBE_CAT(I2C_DATA_OUT, m),\t\\\n\tIXGBE_CAT(I2C_DATA_OE_N_EN, m),\t\\\n\tIXGBE_CAT(I2C_BB_EN, m),\t\\\n\tIXGBE_CAT(I2C_CLK_OE_N_EN, m),\t\\\n\tIXGBE_CAT(I2CCTL, m)\n\nenum ixgbe_mvals {\n\tIXGBE_MVALS_INIT(_IDX),\n\tIXGBE_MVALS_IDX_LIMIT\n};\n\n/*\n * Unavailable: The FCoE Boot Option ROM is not present in the flash.\n * Disabled: Present; boot order is not set for any targets on the port.\n * Enabled: Present; boot order is set for at least one target on the port.\n */\nenum ixgbe_fcoe_boot_status {\n\tixgbe_fcoe_bootstatus_disabled = 0,\n\tixgbe_fcoe_bootstatus_enabled = 1,\n\tixgbe_fcoe_bootstatus_unavailable = 0xFFFF\n};\n\nenum ixgbe_eeprom_type {\n\tixgbe_eeprom_uninitialized = 0,\n\tixgbe_eeprom_spi,\n\tixgbe_flash,\n\tixgbe_eeprom_none /* No NVM support */\n};\n\nenum ixgbe_mac_type {\n\tixgbe_mac_unknown = 0,\n\tixgbe_mac_82598EB,\n\tixgbe_mac_82599EB,\n\tixgbe_mac_82599_vf,\n\tixgbe_mac_X540,\n\tixgbe_mac_X540_vf,\n\tixgbe_mac_X550,\n\tixgbe_mac_X550EM_x,\n\tixgbe_mac_X550_vf,\n\tixgbe_mac_X550EM_x_vf,\n\tixgbe_num_macs\n};\n\nenum ixgbe_phy_type {\n\tixgbe_phy_unknown = 0,\n\tixgbe_phy_none,\n\tixgbe_phy_tn,\n\tixgbe_phy_aq,\n\tixgbe_phy_x550em_kr,\n\tixgbe_phy_x550em_kx4,\n\tixgbe_phy_x550em_ext_t,\n\tixgbe_phy_cu_unknown,\n\tixgbe_phy_qt,\n\tixgbe_phy_xaui,\n\tixgbe_phy_nl,\n\tixgbe_phy_sfp_passive_tyco,\n\tixgbe_phy_sfp_passive_unknown,\n\tixgbe_phy_sfp_active_unknown,\n\tixgbe_phy_sfp_avago,\n\tixgbe_phy_sfp_ftl,\n\tixgbe_phy_sfp_ftl_active,\n\tixgbe_phy_sfp_unknown,\n\tixgbe_phy_sfp_intel,\n\tixgbe_phy_qsfp_passive_unknown,\n\tixgbe_phy_qsfp_active_unknown,\n\tixgbe_phy_qsfp_intel,\n\tixgbe_phy_qsfp_unknown,\n\tixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/\n\tixgbe_phy_generic\n};\n\n/*\n * SFP+ module type IDs:\n *\n * ID\tModule Type\n * =============\n * 0\tSFP_DA_CU\n * 1\tSFP_SR\n * 2\tSFP_LR\n * 3\tSFP_DA_CU_CORE0 - 82599-specific\n * 4\tSFP_DA_CU_CORE1 - 82599-specific\n * 5\tSFP_SR/LR_CORE0 - 82599-specific\n * 6\tSFP_SR/LR_CORE1 - 82599-specific\n */\nenum ixgbe_sfp_type {\n\tixgbe_sfp_type_da_cu = 0,\n\tixgbe_sfp_type_sr = 1,\n\tixgbe_sfp_type_lr = 2,\n\tixgbe_sfp_type_da_cu_core0 = 3,\n\tixgbe_sfp_type_da_cu_core1 = 4,\n\tixgbe_sfp_type_srlr_core0 = 5,\n\tixgbe_sfp_type_srlr_core1 = 6,\n\tixgbe_sfp_type_da_act_lmt_core0 = 7,\n\tixgbe_sfp_type_da_act_lmt_core1 = 8,\n\tixgbe_sfp_type_1g_cu_core0 = 9,\n\tixgbe_sfp_type_1g_cu_core1 = 10,\n\tixgbe_sfp_type_1g_sx_core0 = 11,\n\tixgbe_sfp_type_1g_sx_core1 = 12,\n\tixgbe_sfp_type_1g_lx_core0 = 13,\n\tixgbe_sfp_type_1g_lx_core1 = 14,\n\tixgbe_sfp_type_not_present = 0xFFFE,\n\tixgbe_sfp_type_unknown = 0xFFFF\n};\n\nenum ixgbe_media_type {\n\tixgbe_media_type_unknown = 0,\n\tixgbe_media_type_fiber,\n\tixgbe_media_type_fiber_qsfp,\n\tixgbe_media_type_fiber_lco,\n\tixgbe_media_type_copper,\n\tixgbe_media_type_backplane,\n\tixgbe_media_type_cx4,\n\tixgbe_media_type_virtual\n};\n\n/* Flow Control Settings */\nenum ixgbe_fc_mode {\n\tixgbe_fc_none = 0,\n\tixgbe_fc_rx_pause,\n\tixgbe_fc_tx_pause,\n\tixgbe_fc_full,\n\tixgbe_fc_default\n};\n\n/* Smart Speed Settings */\n#define IXGBE_SMARTSPEED_MAX_RETRIES\t3\nenum ixgbe_smart_speed {\n\tixgbe_smart_speed_auto = 0,\n\tixgbe_smart_speed_on,\n\tixgbe_smart_speed_off\n};\n\n/* PCI bus types */\nenum ixgbe_bus_type {\n\tixgbe_bus_type_unknown = 0,\n\tixgbe_bus_type_pci,\n\tixgbe_bus_type_pcix,\n\tixgbe_bus_type_pci_express,\n\tixgbe_bus_type_internal,\n\tixgbe_bus_type_reserved\n};\n\n/* PCI bus speeds */\nenum ixgbe_bus_speed {\n\tixgbe_bus_speed_unknown\t= 0,\n\tixgbe_bus_speed_33\t= 33,\n\tixgbe_bus_speed_66\t= 66,\n\tixgbe_bus_speed_100\t= 100,\n\tixgbe_bus_speed_120\t= 120,\n\tixgbe_bus_speed_133\t= 133,\n\tixgbe_bus_speed_2500\t= 2500,\n\tixgbe_bus_speed_5000\t= 5000,\n\tixgbe_bus_speed_8000\t= 8000,\n\tixgbe_bus_speed_reserved\n};\n\n/* PCI bus widths */\nenum ixgbe_bus_width {\n\tixgbe_bus_width_unknown\t= 0,\n\tixgbe_bus_width_pcie_x1\t= 1,\n\tixgbe_bus_width_pcie_x2\t= 2,\n\tixgbe_bus_width_pcie_x4\t= 4,\n\tixgbe_bus_width_pcie_x8\t= 8,\n\tixgbe_bus_width_32\t= 32,\n\tixgbe_bus_width_64\t= 64,\n\tixgbe_bus_width_reserved\n};\n\nstruct ixgbe_addr_filter_info {\n\tu32 num_mc_addrs;\n\tu32 rar_used_count;\n\tu32 mta_in_use;\n\tu32 overflow_promisc;\n\tbool user_set_promisc;\n};\n\n/* Bus parameters */\nstruct ixgbe_bus_info {\n\tenum ixgbe_bus_speed speed;\n\tenum ixgbe_bus_width width;\n\tenum ixgbe_bus_type type;\n\n\tu16 func;\n\tu16 lan_id;\n};\n\n/* Flow control parameters */\nstruct ixgbe_fc_info {\n\tu32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */\n\tu32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */\n\tu16 pause_time; /* Flow Control Pause timer */\n\tbool send_xon; /* Flow control send XON */\n\tbool strict_ieee; /* Strict IEEE mode */\n\tbool disable_fc_autoneg; /* Do not autonegotiate FC */\n\tbool fc_was_autonegged; /* Is current_mode the result of autonegging? */\n\tenum ixgbe_fc_mode current_mode; /* FC mode in effect */\n\tenum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */\n};\n\n/* Statistics counters collected by the MAC */\nstruct ixgbe_hw_stats {\n\tu64 crcerrs;\n\tu64 illerrc;\n\tu64 errbc;\n\tu64 mspdc;\n\tu64 mpctotal;\n\tu64 mpc[8];\n\tu64 mlfc;\n\tu64 mrfc;\n\tu64 rlec;\n\tu64 lxontxc;\n\tu64 lxonrxc;\n\tu64 lxofftxc;\n\tu64 lxoffrxc;\n\tu64 pxontxc[8];\n\tu64 pxonrxc[8];\n\tu64 pxofftxc[8];\n\tu64 pxoffrxc[8];\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 rnbc[8];\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rjc;\n\tu64 mngprc;\n\tu64 mngpdc;\n\tu64 mngptc;\n\tu64 tor;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 xec;\n\tu64 qprc[16];\n\tu64 qptc[16];\n\tu64 qbrc[16];\n\tu64 qbtc[16];\n\tu64 qprdc[16];\n\tu64 pxon2offc[8];\n\tu64 fdirustat_add;\n\tu64 fdirustat_remove;\n\tu64 fdirfstat_fadd;\n\tu64 fdirfstat_fremove;\n\tu64 fdirmatch;\n\tu64 fdirmiss;\n\tu64 fccrc;\n\tu64 fclast;\n\tu64 fcoerpdc;\n\tu64 fcoeprc;\n\tu64 fcoeptc;\n\tu64 fcoedwrc;\n\tu64 fcoedwtc;\n\tu64 fcoe_noddp;\n\tu64 fcoe_noddp_ext_buff;\n\tu64 ldpcec;\n\tu64 pcrc8ec;\n\tu64 b2ospc;\n\tu64 b2ogprc;\n\tu64 o2bgptc;\n\tu64 o2bspc;\n};\n\n/* forward declaration */\nstruct ixgbe_hw;\n\n/* iterator type for walking multicast address lists */\ntypedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,\n\t\t\t\t u32 *vmdq);\n\n/* Function pointer table */\nstruct ixgbe_eeprom_operations {\n\ts32 (*init_params)(struct ixgbe_hw *);\n\ts32 (*read)(struct ixgbe_hw *, u16, u16 *);\n\ts32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);\n\ts32 (*write)(struct ixgbe_hw *, u16, u16);\n\ts32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);\n\ts32 (*validate_checksum)(struct ixgbe_hw *, u16 *);\n\ts32 (*update_checksum)(struct ixgbe_hw *);\n\ts32 (*calc_checksum)(struct ixgbe_hw *);\n};\n\nstruct ixgbe_mac_operations {\n\ts32 (*init_hw)(struct ixgbe_hw *);\n\ts32 (*reset_hw)(struct ixgbe_hw *);\n\ts32 (*start_hw)(struct ixgbe_hw *);\n\ts32 (*clear_hw_cntrs)(struct ixgbe_hw *);\n\tvoid (*enable_relaxed_ordering)(struct ixgbe_hw *);\n\tenum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);\n\tu32 (*get_supported_physical_layer)(struct ixgbe_hw *);\n\ts32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);\n\ts32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);\n\ts32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);\n\ts32 (*get_device_caps)(struct ixgbe_hw *, u16 *);\n\ts32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);\n\ts32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);\n\ts32 (*stop_adapter)(struct ixgbe_hw *);\n\ts32 (*get_bus_info)(struct ixgbe_hw *);\n\tvoid (*set_lan_id)(struct ixgbe_hw *);\n\ts32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);\n\ts32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);\n\ts32 (*setup_sfp)(struct ixgbe_hw *);\n\ts32 (*enable_rx_dma)(struct ixgbe_hw *, u32);\n\ts32 (*disable_sec_rx_path)(struct ixgbe_hw *);\n\ts32 (*enable_sec_rx_path)(struct ixgbe_hw *);\n\ts32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);\n\tvoid (*release_swfw_sync)(struct ixgbe_hw *, u32);\n\ts32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);\n\ts32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);\n\n\t/* Link */\n\tvoid (*disable_tx_laser)(struct ixgbe_hw *);\n\tvoid (*enable_tx_laser)(struct ixgbe_hw *);\n\tvoid (*flap_tx_laser)(struct ixgbe_hw *);\n\ts32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);\n\ts32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);\n\ts32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);\n\ts32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,\n\t\t\t\t bool *);\n\tvoid (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed);\n\n\t/* Packet Buffer manipulation */\n\tvoid (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);\n\n\t/* LED */\n\ts32 (*led_on)(struct ixgbe_hw *, u32);\n\ts32 (*led_off)(struct ixgbe_hw *, u32);\n\ts32 (*blink_led_start)(struct ixgbe_hw *, u32);\n\ts32 (*blink_led_stop)(struct ixgbe_hw *, u32);\n\n\t/* RAR, Multicast, VLAN */\n\ts32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);\n\ts32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);\n\ts32 (*clear_rar)(struct ixgbe_hw *, u32);\n\ts32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);\n\ts32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);\n\ts32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);\n\ts32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);\n\ts32 (*init_rx_addrs)(struct ixgbe_hw *);\n\ts32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,\n\t\t\t\t ixgbe_mc_addr_itr);\n\ts32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,\n\t\t\t\t ixgbe_mc_addr_itr, bool clear);\n\ts32 (*enable_mc)(struct ixgbe_hw *);\n\ts32 (*disable_mc)(struct ixgbe_hw *);\n\ts32 (*clear_vfta)(struct ixgbe_hw *);\n\ts32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);\n\ts32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *);\n\ts32 (*init_uta_tables)(struct ixgbe_hw *);\n\tvoid (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);\n\tvoid (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);\n\n\t/* Flow Control */\n\ts32 (*fc_enable)(struct ixgbe_hw *);\n\ts32 (*setup_fc)(struct ixgbe_hw *);\n\n\t/* Manageability interface */\n\ts32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);\n\ts32 (*get_thermal_sensor_data)(struct ixgbe_hw *);\n\ts32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);\n\tvoid (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map);\n\tvoid (*disable_rx)(struct ixgbe_hw *hw);\n\tvoid (*enable_rx)(struct ixgbe_hw *hw);\n\tvoid (*set_source_address_pruning)(struct ixgbe_hw *, bool,\n\t\t\t\t\t unsigned int);\n\tvoid (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);\n\ts32 (*dmac_update_tcs)(struct ixgbe_hw *hw);\n\ts32 (*dmac_config_tcs)(struct ixgbe_hw *hw);\n\ts32 (*dmac_config)(struct ixgbe_hw *hw);\n\ts32 (*setup_eee)(struct ixgbe_hw *hw, bool enable_eee);\n\ts32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *);\n\ts32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32);\n\tvoid (*disable_mdd)(struct ixgbe_hw *hw);\n\tvoid (*enable_mdd)(struct ixgbe_hw *hw);\n\tvoid (*mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap);\n\tvoid (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf);\n};\n\nstruct ixgbe_phy_operations {\n\ts32 (*identify)(struct ixgbe_hw *);\n\ts32 (*identify_sfp)(struct ixgbe_hw *);\n\ts32 (*init)(struct ixgbe_hw *);\n\ts32 (*reset)(struct ixgbe_hw *);\n\ts32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);\n\ts32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);\n\ts32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);\n\ts32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);\n\ts32 (*setup_link)(struct ixgbe_hw *);\n\ts32 (*setup_internal_link)(struct ixgbe_hw *);\n\ts32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);\n\ts32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);\n\ts32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);\n\ts32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);\n\ts32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);\n\ts32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);\n\ts32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);\n\ts32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);\n\tvoid (*i2c_bus_clear)(struct ixgbe_hw *);\n\ts32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);\n\ts32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);\n\ts32 (*check_overtemp)(struct ixgbe_hw *);\n\ts32 (*set_phy_power)(struct ixgbe_hw *, bool on);\n\ts32 (*enter_lplu)(struct ixgbe_hw *);\n\ts32 (*handle_lasi)(struct ixgbe_hw *hw);\n\ts32 (*read_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,\n\t\t\t\t\t u16 *value);\n\ts32 (*write_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,\n\t\t\t\t\t u16 value);\n\ts32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,\n\t\t\t\t u8 *value);\n\ts32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,\n\t\t\t\t u8 value);\n};\n\nstruct ixgbe_eeprom_info {\n\tstruct ixgbe_eeprom_operations ops;\n\tenum ixgbe_eeprom_type type;\n\tu32 semaphore_delay;\n\tu16 word_size;\n\tu16 address_bits;\n\tu16 word_page_size;\n\tu16 ctrl_word_3;\n};\n\n#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED\t0x01\nstruct ixgbe_mac_info {\n\tstruct ixgbe_mac_operations ops;\n\tenum ixgbe_mac_type type;\n\tu8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];\n\tu8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];\n\tu8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];\n\t/* prefix for World Wide Node Name (WWNN) */\n\tu16 wwnn_prefix;\n\t/* prefix for World Wide Port Name (WWPN) */\n\tu16 wwpn_prefix;\n#define IXGBE_MAX_MTA\t\t\t128\n\tu32 mta_shadow[IXGBE_MAX_MTA];\n\ts32 mc_filter_type;\n\tu32 mcft_size;\n\tu32 vft_size;\n\tu32 num_rar_entries;\n\tu32 rar_highwater;\n\tu32 rx_pb_size;\n\tu32 max_tx_queues;\n\tu32 max_rx_queues;\n\tu32 orig_autoc;\n\tu8 san_mac_rar_index;\n\tbool get_link_status;\n\tu32 orig_autoc2;\n\tu16 max_msix_vectors;\n\tbool arc_subsystem_valid;\n\tbool orig_link_settings_stored;\n\tbool autotry_restart;\n\tu8 flags;\n\tstruct ixgbe_thermal_sensor_data thermal_sensor_data;\n\tbool thermal_sensor_enabled;\n\tstruct ixgbe_dmac_config dmac_config;\n\tbool set_lben;\n\tu32 max_link_up_time;\n};\n\nstruct ixgbe_phy_info {\n\tstruct ixgbe_phy_operations ops;\n\tenum ixgbe_phy_type type;\n\tu32 addr;\n\tu32 id;\n\tenum ixgbe_sfp_type sfp_type;\n\tbool sfp_setup_needed;\n\tu32 revision;\n\tenum ixgbe_media_type media_type;\n\tu32 phy_semaphore_mask;\n\tbool reset_disable;\n\tixgbe_autoneg_advertised autoneg_advertised;\n\tenum ixgbe_smart_speed smart_speed;\n\tbool smart_speed_active;\n\tbool multispeed_fiber;\n\tbool reset_if_overtemp;\n\tbool qsfp_shared_i2c_bus;\n\tu32 nw_mng_if_sel;\n};\n\n#include \"ixgbe_mbx.h\"\n\nstruct ixgbe_mbx_operations {\n\tvoid (*init_params)(struct ixgbe_hw *hw);\n\ts32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);\n\ts32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);\n\ts32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);\n\ts32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);\n\ts32 (*check_for_msg)(struct ixgbe_hw *, u16);\n\ts32 (*check_for_ack)(struct ixgbe_hw *, u16);\n\ts32 (*check_for_rst)(struct ixgbe_hw *, u16);\n};\n\nstruct ixgbe_mbx_stats {\n\tu32 msgs_tx;\n\tu32 msgs_rx;\n\n\tu32 acks;\n\tu32 reqs;\n\tu32 rsts;\n};\n\nstruct ixgbe_mbx_info {\n\tstruct ixgbe_mbx_operations ops;\n\tstruct ixgbe_mbx_stats stats;\n\tu32 timeout;\n\tu32 usec_delay;\n\tu32 v2p_mailbox;\n\tu16 size;\n};\n\nstruct ixgbe_hw {\n\tu8 IOMEM *hw_addr;\n\tvoid *back;\n\tstruct ixgbe_mac_info mac;\n\tstruct ixgbe_addr_filter_info addr_ctrl;\n\tstruct ixgbe_fc_info fc;\n\tstruct ixgbe_phy_info phy;\n\tstruct ixgbe_eeprom_info eeprom;\n\tstruct ixgbe_bus_info bus;\n\tstruct ixgbe_mbx_info mbx;\n\tconst u32 *mvals;\n\tu16 device_id;\n\tu16 vendor_id;\n\tu16 subsystem_device_id;\n\tu16 subsystem_vendor_id;\n\tu8 revision_id;\n\tbool adapter_stopped;\n\tint api_version;\n\tbool force_full_reset;\n\tbool allow_unsupported_sfp;\n\tbool wol_enabled;\n};\n\n#define ixgbe_call_func(hw, func, params, error) \\\n\t\t(func != NULL) ? func params : error\n\n\n/* Error Codes */\n#define IXGBE_SUCCESS\t\t\t\t0\n#define IXGBE_ERR_EEPROM\t\t\t-1\n#define IXGBE_ERR_EEPROM_CHECKSUM\t\t-2\n#define IXGBE_ERR_PHY\t\t\t\t-3\n#define IXGBE_ERR_CONFIG\t\t\t-4\n#define IXGBE_ERR_PARAM\t\t\t\t-5\n#define IXGBE_ERR_MAC_TYPE\t\t\t-6\n#define IXGBE_ERR_UNKNOWN_PHY\t\t\t-7\n#define IXGBE_ERR_LINK_SETUP\t\t\t-8\n#define IXGBE_ERR_ADAPTER_STOPPED\t\t-9\n#define IXGBE_ERR_INVALID_MAC_ADDR\t\t-10\n#define IXGBE_ERR_DEVICE_NOT_SUPPORTED\t\t-11\n#define IXGBE_ERR_MASTER_REQUESTS_PENDING\t-12\n#define IXGBE_ERR_INVALID_LINK_SETTINGS\t\t-13\n#define IXGBE_ERR_AUTONEG_NOT_COMPLETE\t\t-14\n#define IXGBE_ERR_RESET_FAILED\t\t\t-15\n#define IXGBE_ERR_SWFW_SYNC\t\t\t-16\n#define IXGBE_ERR_PHY_ADDR_INVALID\t\t-17\n#define IXGBE_ERR_I2C\t\t\t\t-18\n#define IXGBE_ERR_SFP_NOT_SUPPORTED\t\t-19\n#define IXGBE_ERR_SFP_NOT_PRESENT\t\t-20\n#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT\t-21\n#define IXGBE_ERR_NO_SAN_ADDR_PTR\t\t-22\n#define IXGBE_ERR_FDIR_REINIT_FAILED\t\t-23\n#define IXGBE_ERR_EEPROM_VERSION\t\t-24\n#define IXGBE_ERR_NO_SPACE\t\t\t-25\n#define IXGBE_ERR_OVERTEMP\t\t\t-26\n#define IXGBE_ERR_FC_NOT_NEGOTIATED\t\t-27\n#define IXGBE_ERR_FC_NOT_SUPPORTED\t\t-28\n#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE\t-30\n#define IXGBE_ERR_PBA_SECTION\t\t\t-31\n#define IXGBE_ERR_INVALID_ARGUMENT\t\t-32\n#define IXGBE_ERR_HOST_INTERFACE_COMMAND\t-33\n#define IXGBE_ERR_OUT_OF_MEM\t\t\t-34\n#define IXGBE_ERR_FEATURE_NOT_SUPPORTED\t\t-36\n#define IXGBE_ERR_EEPROM_PROTECTED_REGION\t-37\n#define IXGBE_ERR_FDIR_CMD_INCOMPLETE\t\t-38\n\n#define IXGBE_NOT_IMPLEMENTED\t\t\t0x7FFFFFFF\n\n\n#define IXGBE_FUSES0_GROUP(_i)\t\t(0x11158 + ((_i) * 4))\n#define IXGBE_FUSES0_300MHZ\t\t(1 << 5)\n#define IXGBE_FUSES0_REV1\t\t(1 << 6)\n\n#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P)\t((P) ? 0x8010 : 0x4010)\n#define IXGBE_KRM_LINK_CTRL_1(P)\t((P) ? 0x820C : 0x420C)\n#define IXGBE_KRM_AN_CNTL_1(P)\t\t((P) ? 0x822C : 0x422C)\n#define IXGBE_KRM_DSP_TXFFE_STATE_4(P)\t((P) ? 0x8634 : 0x4634)\n#define IXGBE_KRM_DSP_TXFFE_STATE_5(P)\t((P) ? 0x8638 : 0x4638)\n#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P)\t((P) ? 0x8B00 : 0x4B00)\n#define IXGBE_KRM_PMD_DFX_BURNIN(P)\t((P) ? 0x8E00 : 0x4E00)\n#define IXGBE_KRM_TX_COEFF_CTRL_1(P)\t((P) ? 0x9520 : 0x5520)\n#define IXGBE_KRM_RX_ANA_CTL(P)\t\t((P) ? 0x9A00 : 0x5A00)\n\n#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B\t\t(1 << 9)\n#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS\t\t(1 << 11)\n\n#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK\t(0x7 << 8)\n#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G\t(2 << 8)\n#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G\t(4 << 8)\n#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ\t\t(1 << 14)\n#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC\t\t(1 << 15)\n#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX\t\t(1 << 16)\n#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR\t\t(1 << 18)\n#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX\t\t(1 << 24)\n#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR\t\t(1 << 26)\n#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE\t\t(1 << 29)\n#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART\t\t(1 << 31)\n\n#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE\t\t\t(1 << 28)\n#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE\t\t\t(1 << 29)\n\n#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN\t\t\t(1 << 6)\n#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN\t\t(1 << 15)\n#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN\t\t(1 << 16)\n\n#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL\t(1 << 4)\n#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS\t(1 << 2)\n\n#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK\t(0x3 << 16)\n\n#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN\t(1 << 1)\n#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN\t(1 << 2)\n#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN\t\t(1 << 3)\n#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN\t\t(1 << 31)\n\n#define IXGBE_KX4_LINK_CNTL_1\t\t\t\t0x4C\n#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX\t\t(1 << 16)\n#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4\t\t(1 << 17)\n#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX\t\t(1 << 24)\n#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX4\t\t(1 << 25)\n#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE\t\t(1 << 29)\n#define IXGBE_KX4_LINK_CNTL_1_TETH_FORCE_LINK_UP\t(1 << 30)\n#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART\t\t(1 << 31)\n\n#define IXGBE_SB_IOSF_INDIRECT_CTRL\t0x00011144\n#define IXGBE_SB_IOSF_INDIRECT_DATA\t0x00011148\n\n#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT\t\t0\n#define IXGBE_SB_IOSF_CTRL_ADDR_MASK\t\t0xFF\n#define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT\t18\n#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK\t\\\n\t\t\t\t(0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)\n#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT\t20\n#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK\t\\\n\t\t\t\t(0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)\n#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT\t28\n#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK\t0x7\n#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT\t\t31\n#define IXGBE_SB_IOSF_CTRL_BUSY\t\t(1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)\n#define IXGBE_SB_IOSF_TARGET_KR_PHY\t0\n#define IXGBE_SB_IOSF_TARGET_KX4_PHY\t1\n#define IXGBE_SB_IOSF_TARGET_KX4_PCS\t2\n\n#define IXGBE_NW_MNG_IF_SEL\t\t0x00011178\n#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24)\n\n#endif /* _IXGBE_TYPE_H_ */\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_vf.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n\n#include \"ixgbe_api.h\"\n#include \"ixgbe_type.h\"\n#include \"ixgbe_vf.h\"\n\n#ifndef IXGBE_VFWRITE_REG\n#define IXGBE_VFWRITE_REG IXGBE_WRITE_REG\n#endif\n#ifndef IXGBE_VFREAD_REG\n#define IXGBE_VFREAD_REG IXGBE_READ_REG\n#endif\n\n/**\n * ixgbe_init_ops_vf - Initialize the pointers for vf\n * @hw: pointer to hardware structure\n *\n * This will assign function pointers, adapter-specific functions can\n * override the assignment of generic function pointers by assigning\n * their own adapter-specific function pointers.\n * Does not touch the hardware.\n **/\ns32 ixgbe_init_ops_vf(struct ixgbe_hw *hw)\n{\n\t/* MAC */\n\thw->mac.ops.init_hw = ixgbe_init_hw_vf;\n\thw->mac.ops.reset_hw = ixgbe_reset_hw_vf;\n\thw->mac.ops.start_hw = ixgbe_start_hw_vf;\n\t/* Cannot clear stats on VF */\n\thw->mac.ops.clear_hw_cntrs = NULL;\n\thw->mac.ops.get_media_type = NULL;\n\thw->mac.ops.get_mac_addr = ixgbe_get_mac_addr_vf;\n\thw->mac.ops.stop_adapter = ixgbe_stop_adapter_vf;\n\thw->mac.ops.get_bus_info = NULL;\n\n\t/* Link */\n\thw->mac.ops.setup_link = ixgbe_setup_mac_link_vf;\n\thw->mac.ops.check_link = ixgbe_check_mac_link_vf;\n\thw->mac.ops.get_link_capabilities = NULL;\n\n\t/* RAR, Multicast, VLAN */\n\thw->mac.ops.set_rar = ixgbe_set_rar_vf;\n\thw->mac.ops.set_uc_addr = ixgbevf_set_uc_addr_vf;\n\thw->mac.ops.init_rx_addrs = NULL;\n\thw->mac.ops.update_mc_addr_list = ixgbe_update_mc_addr_list_vf;\n\thw->mac.ops.enable_mc = NULL;\n\thw->mac.ops.disable_mc = NULL;\n\thw->mac.ops.clear_vfta = NULL;\n\thw->mac.ops.set_vfta = ixgbe_set_vfta_vf;\n\n\thw->mac.max_tx_queues = 1;\n\thw->mac.max_rx_queues = 1;\n\n\thw->mbx.ops.init_params = ixgbe_init_mbx_params_vf;\n\n\treturn IXGBE_SUCCESS;\n}\n\n/* ixgbe_virt_clr_reg - Set register to default (power on) state.\n * @hw: pointer to hardware structure\n */\nstatic void ixgbe_virt_clr_reg(struct ixgbe_hw *hw)\n{\n\tint i;\n\tu32 vfsrrctl;\n\tu32 vfdca_rxctrl;\n\tu32 vfdca_txctrl;\n\n\t/* VRSRRCTL default values (BSIZEPACKET = 2048, BSIZEHEADER = 256) */\n\tvfsrrctl = 0x100 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;\n\tvfsrrctl |= 0x800 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;\n\n\t/* DCA_RXCTRL default value */\n\tvfdca_rxctrl = IXGBE_DCA_RXCTRL_DESC_RRO_EN |\n\t\t IXGBE_DCA_RXCTRL_DATA_WRO_EN |\n\t\t IXGBE_DCA_RXCTRL_HEAD_WRO_EN;\n\n\t/* DCA_TXCTRL default value */\n\tvfdca_txctrl = IXGBE_DCA_TXCTRL_DESC_RRO_EN |\n\t\t IXGBE_DCA_TXCTRL_DESC_WRO_EN |\n\t\t IXGBE_DCA_TXCTRL_DATA_RRO_EN;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);\n\n\tfor (i = 0; i < 7; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), vfsrrctl);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(i), vfdca_rxctrl);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i), vfdca_txctrl);\n\t}\n\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/**\n * ixgbe_start_hw_vf - Prepare hardware for Tx/Rx\n * @hw: pointer to hardware structure\n *\n * Starts the hardware by filling the bus info structure and media type, clears\n * all on chip counters, initializes receive address registers, multicast\n * table, VLAN filter table, calls routine to set up link and flow control\n * settings, and leaves transmit and receive units disabled and uninitialized\n **/\ns32 ixgbe_start_hw_vf(struct ixgbe_hw *hw)\n{\n\t/* Clear adapter stopped flag */\n\thw->adapter_stopped = false;\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_init_hw_vf - virtual function hardware initialization\n * @hw: pointer to hardware structure\n *\n * Initialize the hardware by resetting the hardware and then starting\n * the hardware\n **/\ns32 ixgbe_init_hw_vf(struct ixgbe_hw *hw)\n{\n\ts32 status = hw->mac.ops.start_hw(hw);\n\n\thw->mac.ops.get_mac_addr(hw, hw->mac.addr);\n\n\treturn status;\n}\n\n/**\n * ixgbe_reset_hw_vf - Performs hardware reset\n * @hw: pointer to hardware structure\n *\n * Resets the hardware by reseting the transmit and receive units, masks and\n * clears all interrupts.\n **/\ns32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\tu32 timeout = IXGBE_VF_INIT_TIMEOUT;\n\ts32 ret_val = IXGBE_ERR_INVALID_MAC_ADDR;\n\tu32 msgbuf[IXGBE_VF_PERMADDR_MSG_LEN];\n\tu8 *addr = (u8 *)(&msgbuf[1]);\n\n\tDEBUGFUNC(\"ixgbevf_reset_hw_vf\");\n\n\t/* Call adapter stop to disable tx/rx and clear interrupts */\n\thw->mac.ops.stop_adapter(hw);\n\n\t/* reset the api version */\n\thw->api_version = ixgbe_mbox_api_10;\n\n\tDEBUGOUT(\"Issuing a function level reset to MAC\\n\");\n\n\tIXGBE_VFWRITE_REG(hw, IXGBE_VFCTRL, IXGBE_CTRL_RST);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\tmsec_delay(50);\n\n\t/* we cannot reset while the RSTI / RSTD bits are asserted */\n\twhile (!mbx->ops.check_for_rst(hw, 0) && timeout) {\n\t\ttimeout--;\n\t\tusec_delay(5);\n\t}\n\n\tif (!timeout)\n\t\treturn IXGBE_ERR_RESET_FAILED;\n\n\t/* Reset VF registers to initial values */\n\tixgbe_virt_clr_reg(hw);\n\n\t/* mailbox timeout can now become active */\n\tmbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT;\n\n\tmsgbuf[0] = IXGBE_VF_RESET;\n\tmbx->ops.write_posted(hw, msgbuf, 1, 0);\n\n\tmsec_delay(10);\n\n\t/*\n\t * set our \"perm_addr\" based on info provided by PF\n\t * also set up the mc_filter_type which is piggy backed\n\t * on the mac address in word 3\n\t */\n\tret_val = mbx->ops.read_posted(hw, msgbuf,\n\t\t\tIXGBE_VF_PERMADDR_MSG_LEN, 0);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK) &&\n\t msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_NACK))\n\t\treturn IXGBE_ERR_INVALID_MAC_ADDR;\n\n\tmemcpy(hw->mac.perm_addr, addr, IXGBE_ETH_LENGTH_OF_ADDRESS);\n\thw->mac.mc_filter_type = msgbuf[IXGBE_VF_MC_TYPE_WORD];\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_stop_adapter_vf - Generic stop Tx/Rx units\n * @hw: pointer to hardware structure\n *\n * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,\n * disables transmit and receive units. The adapter_stopped flag is used by\n * the shared code and drivers to determine if the adapter is in a stopped\n * state and should not touch the hardware.\n **/\ns32 ixgbe_stop_adapter_vf(struct ixgbe_hw *hw)\n{\n\tu32 reg_val;\n\tu16 i;\n\n\t/*\n\t * Set the adapter_stopped flag so other driver functions stop touching\n\t * the hardware\n\t */\n\thw->adapter_stopped = true;\n\n\t/* Clear interrupt mask to stop from interrupts being generated */\n\tIXGBE_VFWRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);\n\n\t/* Clear any pending interrupts, flush previous writes */\n\tIXGBE_VFREAD_REG(hw, IXGBE_VTEICR);\n\n\t/* Disable the transmit unit. Each queue must be disabled. */\n\tfor (i = 0; i < hw->mac.max_tx_queues; i++)\n\t\tIXGBE_VFWRITE_REG(hw, IXGBE_VFTXDCTL(i), IXGBE_TXDCTL_SWFLSH);\n\n\t/* Disable the receive unit by stopping each queue */\n\tfor (i = 0; i < hw->mac.max_rx_queues; i++) {\n\t\treg_val = IXGBE_VFREAD_REG(hw, IXGBE_VFRXDCTL(i));\n\t\treg_val &= ~IXGBE_RXDCTL_ENABLE;\n\t\tIXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val);\n\t}\n\t/* Clear packet split and pool config */\n\tIXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0);\n\n\t/* flush all queues disables */\n\tIXGBE_WRITE_FLUSH(hw);\n\tmsec_delay(2);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_mta_vector - Determines bit-vector in multicast table to set\n * @hw: pointer to hardware structure\n * @mc_addr: the multicast address\n *\n * Extracts the 12 bits, from a multicast address, to determine which\n * bit-vector to set in the multicast table. The hardware uses 12 bits, from\n * incoming rx multicast addresses, to determine the bit-vector to check in\n * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set\n * by the MO field of the MCSTCTRL. The MO field is set during initialization\n * to mc_filter_type.\n **/\nSTATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)\n{\n\tu32 vector = 0;\n\n\tswitch (hw->mac.mc_filter_type) {\n\tcase 0: /* use bits [47:36] of the address */\n\t\tvector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));\n\t\tbreak;\n\tcase 1: /* use bits [46:35] of the address */\n\t\tvector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));\n\t\tbreak;\n\tcase 2: /* use bits [45:34] of the address */\n\t\tvector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));\n\t\tbreak;\n\tcase 3: /* use bits [43:32] of the address */\n\t\tvector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));\n\t\tbreak;\n\tdefault: /* Invalid mc_filter_type */\n\t\tDEBUGOUT(\"MC filter type param set incorrectly\\n\");\n\t\tASSERT(0);\n\t\tbreak;\n\t}\n\n\t/* vector can only be 12-bits or boundary will be exceeded */\n\tvector &= 0xFFF;\n\treturn vector;\n}\n\nSTATIC void ixgbevf_write_msg_read_ack(struct ixgbe_hw *hw,\n\t\t\t\t\tu32 *msg, u16 size)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\tu32 retmsg[IXGBE_VFMAILBOX_SIZE];\n\ts32 retval = mbx->ops.write_posted(hw, msg, size, 0);\n\n\tif (!retval)\n\t\tmbx->ops.read_posted(hw, retmsg, size, 0);\n}\n\n/**\n * ixgbe_set_rar_vf - set device MAC address\n * @hw: pointer to hardware structure\n * @index: Receive address register to write\n * @addr: Address to put into receive address register\n * @vmdq: VMDq \"set\" or \"pool\" index\n * @enable_addr: set flag that address is active\n **/\ns32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n\t\t u32 enable_addr)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\tu32 msgbuf[3];\n\tu8 *msg_addr = (u8 *)(&msgbuf[1]);\n\ts32 ret_val;\n\tUNREFERENCED_3PARAMETER(vmdq, enable_addr, index);\n\n\tmemset(msgbuf, 0, 12);\n\tmsgbuf[0] = IXGBE_VF_SET_MAC_ADDR;\n\tmemcpy(msg_addr, addr, 6);\n\tret_val = mbx->ops.write_posted(hw, msgbuf, 3, 0);\n\n\tif (!ret_val)\n\t\tret_val = mbx->ops.read_posted(hw, msgbuf, 3, 0);\n\n\tmsgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;\n\n\t/* if nacked the address was rejected, use \"perm_addr\" */\n\tif (!ret_val &&\n\t (msgbuf[0] == (IXGBE_VF_SET_MAC_ADDR | IXGBE_VT_MSGTYPE_NACK)))\n\t\tixgbe_get_mac_addr_vf(hw, hw->mac.addr);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_update_mc_addr_list_vf - Update Multicast addresses\n * @hw: pointer to the HW structure\n * @mc_addr_list: array of multicast addresses to program\n * @mc_addr_count: number of multicast addresses to program\n * @next: caller supplied function to return next address in list\n *\n * Updates the Multicast Table Array.\n **/\ns32 ixgbe_update_mc_addr_list_vf(struct ixgbe_hw *hw, u8 *mc_addr_list,\n\t\t\t\t u32 mc_addr_count, ixgbe_mc_addr_itr next,\n\t\t\t\t bool clear)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\tu32 msgbuf[IXGBE_VFMAILBOX_SIZE];\n\tu16 *vector_list = (u16 *)&msgbuf[1];\n\tu32 vector;\n\tu32 cnt, i;\n\tu32 vmdq;\n\n\tUNREFERENCED_1PARAMETER(clear);\n\n\tDEBUGFUNC(\"ixgbe_update_mc_addr_list_vf\");\n\n\t/* Each entry in the list uses 1 16 bit word. We have 30\n\t * 16 bit words available in our HW msg buffer (minus 1 for the\n\t * msg type). That's 30 hash values if we pack 'em right. If\n\t * there are more than 30 MC addresses to add then punt the\n\t * extras for now and then add code to handle more than 30 later.\n\t * It would be unusual for a server to request that many multi-cast\n\t * addresses except for in large enterprise network environments.\n\t */\n\n\tDEBUGOUT1(\"MC Addr Count = %d\\n\", mc_addr_count);\n\n\tcnt = (mc_addr_count > 30) ? 30 : mc_addr_count;\n\tmsgbuf[0] = IXGBE_VF_SET_MULTICAST;\n\tmsgbuf[0] |= cnt << IXGBE_VT_MSGINFO_SHIFT;\n\n\tfor (i = 0; i < cnt; i++) {\n\t\tvector = ixgbe_mta_vector(hw, next(hw, &mc_addr_list, &vmdq));\n\t\tDEBUGOUT1(\"Hash value = 0x%03X\\n\", vector);\n\t\tvector_list[i] = (u16)vector;\n\t}\n\n\treturn mbx->ops.write_posted(hw, msgbuf, IXGBE_VFMAILBOX_SIZE, 0);\n}\n\n/**\n * ixgbe_set_vfta_vf - Set/Unset vlan filter table address\n * @hw: pointer to the HW structure\n * @vlan: 12 bit VLAN ID\n * @vind: unused by VF drivers\n * @vlan_on: if true then set bit, else clear bit\n **/\ns32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\tu32 msgbuf[2];\n\ts32 ret_val;\n\tUNREFERENCED_1PARAMETER(vind);\n\n\tmsgbuf[0] = IXGBE_VF_SET_VLAN;\n\tmsgbuf[1] = vlan;\n\t/* Setting the 8 bit field MSG INFO to TRUE indicates \"add\" */\n\tmsgbuf[0] |= vlan_on << IXGBE_VT_MSGINFO_SHIFT;\n\n\tret_val = mbx->ops.write_posted(hw, msgbuf, 2, 0);\n\tif (!ret_val)\n\t\tret_val = mbx->ops.read_posted(hw, msgbuf, 1, 0);\n\n\tif (!ret_val && (msgbuf[0] & IXGBE_VT_MSGTYPE_ACK))\n\t\treturn IXGBE_SUCCESS;\n\n\treturn ret_val | (msgbuf[0] & IXGBE_VT_MSGTYPE_NACK);\n}\n\n/**\n * ixgbe_get_num_of_tx_queues_vf - Get number of TX queues\n * @hw: pointer to hardware structure\n *\n * Returns the number of transmit queues for the given adapter.\n **/\nu32 ixgbe_get_num_of_tx_queues_vf(struct ixgbe_hw *hw)\n{\n\tUNREFERENCED_1PARAMETER(hw);\n\treturn IXGBE_VF_MAX_TX_QUEUES;\n}\n\n/**\n * ixgbe_get_num_of_rx_queues_vf - Get number of RX queues\n * @hw: pointer to hardware structure\n *\n * Returns the number of receive queues for the given adapter.\n **/\nu32 ixgbe_get_num_of_rx_queues_vf(struct ixgbe_hw *hw)\n{\n\tUNREFERENCED_1PARAMETER(hw);\n\treturn IXGBE_VF_MAX_RX_QUEUES;\n}\n\n/**\n * ixgbe_get_mac_addr_vf - Read device MAC address\n * @hw: pointer to the HW structure\n **/\ns32 ixgbe_get_mac_addr_vf(struct ixgbe_hw *hw, u8 *mac_addr)\n{\n\tint i;\n\n\tfor (i = 0; i < IXGBE_ETH_LENGTH_OF_ADDRESS; i++)\n\t\tmac_addr[i] = hw->mac.perm_addr[i];\n\n\treturn IXGBE_SUCCESS;\n}\n\ns32 ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, u32 index, u8 *addr)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\tu32 msgbuf[3];\n\tu8 *msg_addr = (u8 *)(&msgbuf[1]);\n\ts32 ret_val;\n\n\tmemset(msgbuf, 0, sizeof(msgbuf));\n\t/*\n\t * If index is one then this is the start of a new list and needs\n\t * indication to the PF so it can do it's own list management.\n\t * If it is zero then that tells the PF to just clear all of\n\t * this VF's macvlans and there is no new list.\n\t */\n\tmsgbuf[0] |= index << IXGBE_VT_MSGINFO_SHIFT;\n\tmsgbuf[0] |= IXGBE_VF_SET_MACVLAN;\n\tif (addr)\n\t\tmemcpy(msg_addr, addr, 6);\n\tret_val = mbx->ops.write_posted(hw, msgbuf, 3, 0);\n\n\tif (!ret_val)\n\t\tret_val = mbx->ops.read_posted(hw, msgbuf, 3, 0);\n\n\tmsgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;\n\n\tif (!ret_val)\n\t\tif (msgbuf[0] == (IXGBE_VF_SET_MACVLAN | IXGBE_VT_MSGTYPE_NACK))\n\t\t\tret_val = IXGBE_ERR_OUT_OF_MEM;\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_setup_mac_link_vf - Setup MAC link settings\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg: true if autonegotiation enabled\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Set the link speed in the AUTOC register and restarts link.\n **/\ns32 ixgbe_setup_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t\t bool autoneg_wait_to_complete)\n{\n\tUNREFERENCED_3PARAMETER(hw, speed, autoneg_wait_to_complete);\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_check_mac_link_vf - Get link/speed status\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @link_up: true is link is up, false otherwise\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Reads the links register to determine if link is up and the current speed\n **/\ns32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t bool *link_up, bool autoneg_wait_to_complete)\n{\n\tstruct ixgbe_mbx_info *mbx = &hw->mbx;\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\ts32 ret_val = IXGBE_SUCCESS;\n\tu32 links_reg;\n\tu32 in_msg = 0;\n\tUNREFERENCED_1PARAMETER(autoneg_wait_to_complete);\n\n\t/* If we were hit with a reset drop the link */\n\tif (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)\n\t\tmac->get_link_status = true;\n\n\tif (!mac->get_link_status)\n\t\tgoto out;\n\n\t/* if link status is down no point in checking to see if pf is up */\n\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);\n\tif (!(links_reg & IXGBE_LINKS_UP))\n\t\tgoto out;\n\n\t/* for SFP+ modules and DA cables on 82599 it can take up to 500usecs\n\t * before the link status is correct\n\t */\n\tif (mac->type == ixgbe_mac_82599_vf) {\n\t\tint i;\n\n\t\tfor (i = 0; i < 5; i++) {\n\t\t\tusec_delay(100);\n\t\t\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);\n\n\t\t\tif (!(links_reg & IXGBE_LINKS_UP))\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\n\tswitch (links_reg & IXGBE_LINKS_SPEED_82599) {\n\tcase IXGBE_LINKS_SPEED_10G_82599:\n\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\t\tbreak;\n\tcase IXGBE_LINKS_SPEED_1G_82599:\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\tbreak;\n\tcase IXGBE_LINKS_SPEED_100_82599:\n\t\t*speed = IXGBE_LINK_SPEED_100_FULL;\n\t\tbreak;\n\t}\n\n\t/* if the read failed it could just be a mailbox collision, best wait\n\t * until we are called again and don't report an error\n\t */\n\tif (mbx->ops.read(hw, &in_msg, 1, 0))\n\t\tgoto out;\n\n\tif (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {\n\t\t/* msg is not CTS and is NACK we must have lost CTS status */\n\t\tif (in_msg & IXGBE_VT_MSGTYPE_NACK)\n\t\t\tret_val = -1;\n\t\tgoto out;\n\t}\n\n\t/* the pf is talking, if we timed out in the past we reinit */\n\tif (!mbx->timeout) {\n\t\tret_val = -1;\n\t\tgoto out;\n\t}\n\n\t/* if we passed all the tests above then the link is up and we no\n\t * longer need to check for link\n\t */\n\tmac->get_link_status = false;\n\nout:\n\t*link_up = !mac->get_link_status;\n\treturn ret_val;\n}\n\n/**\n * ixgbevf_rlpml_set_vf - Set the maximum receive packet length\n * @hw: pointer to the HW structure\n * @max_size: value to assign to max frame size\n **/\nvoid ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size)\n{\n\tu32 msgbuf[2];\n\n\tmsgbuf[0] = IXGBE_VF_SET_LPE;\n\tmsgbuf[1] = max_size;\n\tixgbevf_write_msg_read_ack(hw, msgbuf, 2);\n}\n\n/**\n * ixgbevf_negotiate_api_version - Negotiate supported API version\n * @hw: pointer to the HW structure\n * @api: integer containing requested API version\n **/\nint ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api)\n{\n\tint err;\n\tu32 msg[3];\n\n\t/* Negotiate the mailbox API version */\n\tmsg[0] = IXGBE_VF_API_NEGOTIATE;\n\tmsg[1] = api;\n\tmsg[2] = 0;\n\terr = hw->mbx.ops.write_posted(hw, msg, 3, 0);\n\n\tif (!err)\n\t\terr = hw->mbx.ops.read_posted(hw, msg, 3, 0);\n\n\tif (!err) {\n\t\tmsg[0] &= ~IXGBE_VT_MSGTYPE_CTS;\n\n\t\t/* Store value and return 0 on success */\n\t\tif (msg[0] == (IXGBE_VF_API_NEGOTIATE | IXGBE_VT_MSGTYPE_ACK)) {\n\t\t\thw->api_version = api;\n\t\t\treturn 0;\n\t\t}\n\n\t\terr = IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\treturn err;\n}\n\nint ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs,\n\t\t unsigned int *default_tc)\n{\n\tint err;\n\tu32 msg[5];\n\n\t/* do nothing if API doesn't support ixgbevf_get_queues */\n\tswitch (hw->api_version) {\n\tcase ixgbe_mbox_api_11:\n\t\tbreak;\n\tdefault:\n\t\treturn 0;\n\t}\n\n\t/* Fetch queue configuration from the PF */\n\tmsg[0] = IXGBE_VF_GET_QUEUES;\n\tmsg[1] = msg[2] = msg[3] = msg[4] = 0;\n\terr = hw->mbx.ops.write_posted(hw, msg, 5, 0);\n\n\tif (!err)\n\t\terr = hw->mbx.ops.read_posted(hw, msg, 5, 0);\n\n\tif (!err) {\n\t\tmsg[0] &= ~IXGBE_VT_MSGTYPE_CTS;\n\n\t\t/*\n\t\t * if we we didn't get an ACK there must have been\n\t\t * some sort of mailbox error so we should treat it\n\t\t * as such\n\t\t */\n\t\tif (msg[0] != (IXGBE_VF_GET_QUEUES | IXGBE_VT_MSGTYPE_ACK))\n\t\t\treturn IXGBE_ERR_MBX;\n\n\t\t/* record and validate values from message */\n\t\thw->mac.max_tx_queues = msg[IXGBE_VF_TX_QUEUES];\n\t\tif (hw->mac.max_tx_queues == 0 ||\n\t\t hw->mac.max_tx_queues > IXGBE_VF_MAX_TX_QUEUES)\n\t\t\thw->mac.max_tx_queues = IXGBE_VF_MAX_TX_QUEUES;\n\n\t\thw->mac.max_rx_queues = msg[IXGBE_VF_RX_QUEUES];\n\t\tif (hw->mac.max_rx_queues == 0 ||\n\t\t hw->mac.max_rx_queues > IXGBE_VF_MAX_RX_QUEUES)\n\t\t\thw->mac.max_rx_queues = IXGBE_VF_MAX_RX_QUEUES;\n\n\t\t*num_tcs = msg[IXGBE_VF_TRANS_VLAN];\n\t\t/* in case of unknown state assume we cannot tag frames */\n\t\tif (*num_tcs > hw->mac.max_rx_queues)\n\t\t\t*num_tcs = 1;\n\n\t\t*default_tc = msg[IXGBE_VF_DEF_QUEUE];\n\t\t/* default to queue 0 on out-of-bounds queue number */\n\t\tif (*default_tc >= hw->mac.max_tx_queues)\n\t\t\t*default_tc = 0;\n\t}\n\n\treturn err;\n}\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_vf.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef __IXGBE_VF_H__\n#define __IXGBE_VF_H__\n\n#define IXGBE_VF_IRQ_CLEAR_MASK\t7\n#define IXGBE_VF_MAX_TX_QUEUES\t8\n#define IXGBE_VF_MAX_RX_QUEUES\t8\n\n/* DCB define */\n#define IXGBE_VF_MAX_TRAFFIC_CLASS\t8\n\n#define IXGBE_VFCTRL\t\t0x00000\n#define IXGBE_VFSTATUS\t\t0x00008\n#define IXGBE_VFLINKS\t\t0x00010\n#define IXGBE_VFFRTIMER\t\t0x00048\n#define IXGBE_VFRXMEMWRAP\t0x03190\n#define IXGBE_VTEICR\t\t0x00100\n#define IXGBE_VTEICS\t\t0x00104\n#define IXGBE_VTEIMS\t\t0x00108\n#define IXGBE_VTEIMC\t\t0x0010C\n#define IXGBE_VTEIAC\t\t0x00110\n#define IXGBE_VTEIAM\t\t0x00114\n#define IXGBE_VTEITR(x)\t\t(0x00820 + (4 * (x)))\n#define IXGBE_VTIVAR(x)\t\t(0x00120 + (4 * (x)))\n#define IXGBE_VTIVAR_MISC\t0x00140\n#define IXGBE_VTRSCINT(x)\t(0x00180 + (4 * (x)))\n/* define IXGBE_VFPBACL still says TBD in EAS */\n#define IXGBE_VFRDBAL(x)\t(0x01000 + (0x40 * (x)))\n#define IXGBE_VFRDBAH(x)\t(0x01004 + (0x40 * (x)))\n#define IXGBE_VFRDLEN(x)\t(0x01008 + (0x40 * (x)))\n#define IXGBE_VFRDH(x)\t\t(0x01010 + (0x40 * (x)))\n#define IXGBE_VFRDT(x)\t\t(0x01018 + (0x40 * (x)))\n#define IXGBE_VFRXDCTL(x)\t(0x01028 + (0x40 * (x)))\n#define IXGBE_VFSRRCTL(x)\t(0x01014 + (0x40 * (x)))\n#define IXGBE_VFRSCCTL(x)\t(0x0102C + (0x40 * (x)))\n#define IXGBE_VFPSRTYPE\t\t0x00300\n#define IXGBE_VFTDBAL(x)\t(0x02000 + (0x40 * (x)))\n#define IXGBE_VFTDBAH(x)\t(0x02004 + (0x40 * (x)))\n#define IXGBE_VFTDLEN(x)\t(0x02008 + (0x40 * (x)))\n#define IXGBE_VFTDH(x)\t\t(0x02010 + (0x40 * (x)))\n#define IXGBE_VFTDT(x)\t\t(0x02018 + (0x40 * (x)))\n#define IXGBE_VFTXDCTL(x)\t(0x02028 + (0x40 * (x)))\n#define IXGBE_VFTDWBAL(x)\t(0x02038 + (0x40 * (x)))\n#define IXGBE_VFTDWBAH(x)\t(0x0203C + (0x40 * (x)))\n#define IXGBE_VFDCA_RXCTRL(x)\t(0x0100C + (0x40 * (x)))\n#define IXGBE_VFDCA_TXCTRL(x)\t(0x0200c + (0x40 * (x)))\n#define IXGBE_VFGPRC\t\t0x0101C\n#define IXGBE_VFGPTC\t\t0x0201C\n#define IXGBE_VFGORC_LSB\t0x01020\n#define IXGBE_VFGORC_MSB\t0x01024\n#define IXGBE_VFGOTC_LSB\t0x02020\n#define IXGBE_VFGOTC_MSB\t0x02024\n#define IXGBE_VFMPRC\t\t0x01034\n#define IXGBE_VFMRQC\t\t0x3000\n#define IXGBE_VFRSSRK(x)\t(0x3100 + ((x) * 4))\n#define IXGBE_VFRETA(x)\t(0x3200 + ((x) * 4))\n\n\nstruct ixgbevf_hw_stats {\n\tu64 base_vfgprc;\n\tu64 base_vfgptc;\n\tu64 base_vfgorc;\n\tu64 base_vfgotc;\n\tu64 base_vfmprc;\n\n\tu64 last_vfgprc;\n\tu64 last_vfgptc;\n\tu64 last_vfgorc;\n\tu64 last_vfgotc;\n\tu64 last_vfmprc;\n\n\tu64 vfgprc;\n\tu64 vfgptc;\n\tu64 vfgorc;\n\tu64 vfgotc;\n\tu64 vfmprc;\n\n\tu64 saved_reset_vfgprc;\n\tu64 saved_reset_vfgptc;\n\tu64 saved_reset_vfgorc;\n\tu64 saved_reset_vfgotc;\n\tu64 saved_reset_vfmprc;\n};\n\ns32 ixgbe_init_hw_vf(struct ixgbe_hw *hw);\ns32 ixgbe_start_hw_vf(struct ixgbe_hw *hw);\ns32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw);\ns32 ixgbe_stop_adapter_vf(struct ixgbe_hw *hw);\nu32 ixgbe_get_num_of_tx_queues_vf(struct ixgbe_hw *hw);\nu32 ixgbe_get_num_of_rx_queues_vf(struct ixgbe_hw *hw);\ns32 ixgbe_get_mac_addr_vf(struct ixgbe_hw *hw, u8 *mac_addr);\ns32 ixgbe_setup_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t bool *link_up, bool autoneg_wait_to_complete);\ns32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n\t\t u32 enable_addr);\ns32 ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, u32 index, u8 *addr);\ns32 ixgbe_update_mc_addr_list_vf(struct ixgbe_hw *hw, u8 *mc_addr_list,\n\t\t\t\t u32 mc_addr_count, ixgbe_mc_addr_itr,\n\t\t\t\t bool clear);\ns32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on);\nvoid ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size);\nint ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api);\nint ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs,\n\t\t unsigned int *default_tc);\n\n#endif /* __IXGBE_VF_H__ */\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_x540.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"ixgbe_x540.h\"\n#include \"ixgbe_type.h\"\n#include \"ixgbe_api.h\"\n#include \"ixgbe_common.h\"\n#include \"ixgbe_phy.h\"\n\n#define IXGBE_X540_MAX_TX_QUEUES\t128\n#define IXGBE_X540_MAX_RX_QUEUES\t128\n#define IXGBE_X540_RAR_ENTRIES\t\t128\n#define IXGBE_X540_MC_TBL_SIZE\t\t128\n#define IXGBE_X540_VFT_TBL_SIZE\t\t128\n#define IXGBE_X540_RX_PB_SIZE\t\t384\n\nSTATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);\nSTATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);\nSTATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);\n\n/**\n * ixgbe_init_ops_X540 - Inits func ptrs and MAC type\n * @hw: pointer to hardware structure\n *\n * Initialize the function pointers and assign the MAC type for X540.\n * Does not touch the hardware.\n **/\ns32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"ixgbe_init_ops_X540\");\n\n\tret_val = ixgbe_init_phy_ops_generic(hw);\n\tret_val = ixgbe_init_ops_generic(hw);\n\n\n\t/* EEPROM */\n\teeprom->ops.init_params = ixgbe_init_eeprom_params_X540;\n\teeprom->ops.read = ixgbe_read_eerd_X540;\n\teeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540;\n\teeprom->ops.write = ixgbe_write_eewr_X540;\n\teeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540;\n\teeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540;\n\teeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540;\n\teeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540;\n\n\t/* PHY */\n\tphy->ops.init = ixgbe_init_phy_ops_generic;\n\tphy->ops.reset = NULL;\n\tif (!ixgbe_mng_present(hw))\n\t\tphy->ops.set_phy_power = ixgbe_set_copper_phy_power;\n\n\t/* MAC */\n\tmac->ops.reset_hw = ixgbe_reset_hw_X540;\n\tmac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2;\n\tmac->ops.get_media_type = ixgbe_get_media_type_X540;\n\tmac->ops.get_supported_physical_layer =\n\t\t\t\t ixgbe_get_supported_physical_layer_X540;\n\tmac->ops.read_analog_reg8 = NULL;\n\tmac->ops.write_analog_reg8 = NULL;\n\tmac->ops.start_hw = ixgbe_start_hw_X540;\n\tmac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic;\n\tmac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic;\n\tmac->ops.get_device_caps = ixgbe_get_device_caps_generic;\n\tmac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic;\n\tmac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic;\n\tmac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540;\n\tmac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540;\n\tmac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic;\n\tmac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic;\n\n\t/* RAR, Multicast, VLAN */\n\tmac->ops.set_vmdq = ixgbe_set_vmdq_generic;\n\tmac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic;\n\tmac->ops.clear_vmdq = ixgbe_clear_vmdq_generic;\n\tmac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic;\n\tmac->rar_highwater = 1;\n\tmac->ops.set_vfta = ixgbe_set_vfta_generic;\n\tmac->ops.set_vlvf = ixgbe_set_vlvf_generic;\n\tmac->ops.clear_vfta = ixgbe_clear_vfta_generic;\n\tmac->ops.init_uta_tables = ixgbe_init_uta_tables_generic;\n\tmac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing;\n\tmac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing;\n\n\t/* Link */\n\tmac->ops.get_link_capabilities =\n\t\t\t\tixgbe_get_copper_link_capabilities_generic;\n\tmac->ops.setup_link = ixgbe_setup_mac_link_X540;\n\tmac->ops.setup_rxpba = ixgbe_set_rxpba_generic;\n\tmac->ops.check_link = ixgbe_check_mac_link_generic;\n\n\n\tmac->mcft_size\t\t= IXGBE_X540_MC_TBL_SIZE;\n\tmac->vft_size\t\t= IXGBE_X540_VFT_TBL_SIZE;\n\tmac->num_rar_entries\t= IXGBE_X540_RAR_ENTRIES;\n\tmac->rx_pb_size\t\t= IXGBE_X540_RX_PB_SIZE;\n\tmac->max_rx_queues\t= IXGBE_X540_MAX_RX_QUEUES;\n\tmac->max_tx_queues\t= IXGBE_X540_MAX_TX_QUEUES;\n\tmac->max_msix_vectors\t= ixgbe_get_pcie_msix_count_generic(hw);\n\n\t/*\n\t * FWSM register\n\t * ARC supported; valid only if manageability features are\n\t * enabled.\n\t */\n\tmac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &\n\t\t\t\t IXGBE_FWSM_MODE_MASK) ? true : false;\n\n\thw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;\n\n\t/* LEDs */\n\tmac->ops.blink_led_start = ixgbe_blink_led_start_X540;\n\tmac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;\n\n\t/* Manageability interface */\n\tmac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic;\n\n\tmac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_get_link_capabilities_X540 - Determines link capabilities\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @autoneg: true when autoneg or autotry is enabled\n *\n * Determines the link capabilities by reading the AUTOC register.\n **/\ns32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t bool *autoneg)\n{\n\tixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_get_media_type_X540 - Get media type\n * @hw: pointer to hardware structure\n *\n * Returns the media type (fiber, copper, backplane)\n **/\nenum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)\n{\n\tUNREFERENCED_1PARAMETER(hw);\n\treturn ixgbe_media_type_copper;\n}\n\n/**\n * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n **/\ns32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,\n\t\t\t ixgbe_link_speed speed,\n\t\t\t bool autoneg_wait_to_complete)\n{\n\tDEBUGFUNC(\"ixgbe_setup_mac_link_X540\");\n\treturn hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);\n}\n\n/**\n * ixgbe_reset_hw_X540 - Perform hardware reset\n * @hw: pointer to hardware structure\n *\n * Resets the hardware by resetting the transmit and receive units, masks\n * and clears all interrupts, and perform a reset.\n **/\ns32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\tu32 ctrl, i;\n\n\tDEBUGFUNC(\"ixgbe_reset_hw_X540\");\n\n\t/* Call adapter stop to disable tx/rx and clear interrupts */\n\tstatus = hw->mac.ops.stop_adapter(hw);\n\tif (status != IXGBE_SUCCESS)\n\t\tgoto reset_hw_out;\n\n\t/* flush pending Tx transactions */\n\tixgbe_clear_tx_pending(hw);\n\nmac_reset_top:\n\tctrl = IXGBE_CTRL_RST;\n\tctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Poll for reset bit to self-clear indicating reset is complete */\n\tfor (i = 0; i < 10; i++) {\n\t\tusec_delay(1);\n\t\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);\n\t\tif (!(ctrl & IXGBE_CTRL_RST_MASK))\n\t\t\tbreak;\n\t}\n\n\tif (ctrl & IXGBE_CTRL_RST_MASK) {\n\t\tstatus = IXGBE_ERR_RESET_FAILED;\n\t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n\t\t\t \"Reset polling failed to complete.\\n\");\n\t}\n\tmsec_delay(100);\n\n\t/*\n\t * Double resets are required for recovery from certain error\n\t * conditions. Between resets, it is necessary to stall to allow time\n\t * for any pending HW events to complete.\n\t */\n\tif (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {\n\t\thw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;\n\t\tgoto mac_reset_top;\n\t}\n\n\t/* Set the Rx packet buffer size. */\n\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);\n\n\t/* Store the permanent mac address */\n\thw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);\n\n\t/*\n\t * Store MAC address from RAR0, clear receive address registers, and\n\t * clear the multicast table. Also reset num_rar_entries to 128,\n\t * since we modify this value when programming the SAN MAC address.\n\t */\n\thw->mac.num_rar_entries = 128;\n\thw->mac.ops.init_rx_addrs(hw);\n\n\t/* Store the permanent SAN mac address */\n\thw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);\n\n\t/* Add the SAN MAC address to the RAR only if it's a valid address */\n\tif (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {\n\t\thw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,\n\t\t\t\t hw->mac.san_addr, 0, IXGBE_RAH_AV);\n\n\t\t/* Save the SAN MAC RAR index */\n\t\thw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;\n\n\t\t/* Reserve the last RAR for the SAN MAC address */\n\t\thw->mac.num_rar_entries--;\n\t}\n\n\t/* Store the alternative WWNN/WWPN prefix */\n\thw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,\n\t\t\t\t &hw->mac.wwpn_prefix);\n\nreset_hw_out:\n\treturn status;\n}\n\n/**\n * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx\n * @hw: pointer to hardware structure\n *\n * Starts the hardware using the generic start_hw function\n * and the generation start_hw function.\n * Then performs revision-specific operations, if any.\n **/\ns32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_start_hw_X540\");\n\n\tret_val = ixgbe_start_hw_generic(hw);\n\tif (ret_val != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\tret_val = ixgbe_start_hw_gen2(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type\n * @hw: pointer to hardware structure\n *\n * Determines physical layer capabilities of the current configuration.\n **/\nu32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)\n{\n\tu32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n\tu16 ext_ability = 0;\n\n\tDEBUGFUNC(\"ixgbe_get_supported_physical_layer_X540\");\n\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,\n\tIXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);\n\tif (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)\n\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;\n\tif (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)\n\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;\n\tif (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)\n\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;\n\n\treturn physical_layer;\n}\n\n/**\n * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params\n * @hw: pointer to hardware structure\n *\n * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n * ixgbe_hw struct in order to set up EEPROM access.\n **/\ns32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\tu32 eec;\n\tu16 eeprom_size;\n\n\tDEBUGFUNC(\"ixgbe_init_eeprom_params_X540\");\n\n\tif (eeprom->type == ixgbe_eeprom_uninitialized) {\n\t\teeprom->semaphore_delay = 10;\n\t\teeprom->type = ixgbe_flash;\n\n\t\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\t\teeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>\n\t\t\t\t IXGBE_EEC_SIZE_SHIFT);\n\t\teeprom->word_size = 1 << (eeprom_size +\n\t\t\t\t\t IXGBE_EEPROM_WORD_SIZE_SHIFT);\n\n\t\tDEBUGOUT2(\"Eeprom params: type = %d, size = %d\\n\",\n\t\t\t eeprom->type, eeprom->word_size);\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_read_eerd_X540- Read EEPROM word using EERD\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM using the EERD register.\n **/\ns32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)\n{\n\ts32 status = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_read_eerd_X540\");\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n\t IXGBE_SUCCESS) {\n\t\tstatus = ixgbe_read_eerd_generic(hw, offset, data);\n\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\t} else {\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @words: number of words\n * @data: word(s) read from the EEPROM\n *\n * Reads a 16 bit word(s) from the EEPROM using the EERD register.\n **/\ns32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,\n\t\t\t\tu16 offset, u16 words, u16 *data)\n{\n\ts32 status = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_read_eerd_buffer_X540\");\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n\t IXGBE_SUCCESS) {\n\t\tstatus = ixgbe_read_eerd_buffer_generic(hw, offset,\n\t\t\t\t\t\t\twords, data);\n\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\t} else {\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to write\n * @data: word write to the EEPROM\n *\n * Write a 16 bit word to the EEPROM using the EEWR register.\n **/\ns32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)\n{\n\ts32 status = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_write_eewr_X540\");\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n\t IXGBE_SUCCESS) {\n\t\tstatus = ixgbe_write_eewr_generic(hw, offset, data);\n\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\t} else {\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to write\n * @words: number of words\n * @data: word(s) write to the EEPROM\n *\n * Write a 16 bit word(s) to the EEPROM using the EEWR register.\n **/\ns32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,\n\t\t\t\t u16 offset, u16 words, u16 *data)\n{\n\ts32 status = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_write_eewr_buffer_X540\");\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n\t IXGBE_SUCCESS) {\n\t\tstatus = ixgbe_write_eewr_buffer_generic(hw, offset,\n\t\t\t\t\t\t\t words, data);\n\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\t} else {\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum\n *\n * This function does not use synchronization for EERD and EEWR. It can\n * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.\n *\n * @hw: pointer to hardware structure\n *\n * Returns a negative error code on error, or the 16-bit checksum\n **/\ns32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)\n{\n\tu16 i, j;\n\tu16 checksum = 0;\n\tu16 length = 0;\n\tu16 pointer = 0;\n\tu16 word = 0;\n\tu16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;\n\tu16 ptr_start = IXGBE_PCIE_ANALOG_PTR;\n\n\t/* Do not use hw->eeprom.ops.read because we do not want to take\n\t * the synchronization semaphores here. Instead use\n\t * ixgbe_read_eerd_generic\n\t */\n\n\tDEBUGFUNC(\"ixgbe_calc_eeprom_checksum_X540\");\n\n\t/* Include 0x0-0x3F in the checksum */\n\tfor (i = 0; i <= checksum_last_word; i++) {\n\t\tif (ixgbe_read_eerd_generic(hw, i, &word)) {\n\t\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\t\treturn IXGBE_ERR_EEPROM;\n\t\t}\n\t\tif (i != IXGBE_EEPROM_CHECKSUM)\n\t\t\tchecksum += word;\n\t}\n\n\t/* Include all data from pointers 0x3, 0x6-0xE. This excludes the\n\t * FW, PHY module, and PCIe Expansion/Option ROM pointers.\n\t */\n\tfor (i = ptr_start; i < IXGBE_FW_PTR; i++) {\n\t\tif (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)\n\t\t\tcontinue;\n\n\t\tif (ixgbe_read_eerd_generic(hw, i, &pointer)) {\n\t\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\t\treturn IXGBE_ERR_EEPROM;\n\t\t}\n\n\t\t/* Skip pointer section if the pointer is invalid. */\n\t\tif (pointer == 0xFFFF || pointer == 0 ||\n\t\t pointer >= hw->eeprom.word_size)\n\t\t\tcontinue;\n\n\t\tif (ixgbe_read_eerd_generic(hw, pointer, &length)) {\n\t\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\t\treturn IXGBE_ERR_EEPROM;\n\t\t}\n\n\t\t/* Skip pointer section if length is invalid. */\n\t\tif (length == 0xFFFF || length == 0 ||\n\t\t (pointer + length) >= hw->eeprom.word_size)\n\t\t\tcontinue;\n\n\t\tfor (j = pointer + 1; j <= pointer + length; j++) {\n\t\t\tif (ixgbe_read_eerd_generic(hw, j, &word)) {\n\t\t\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\t\t\treturn IXGBE_ERR_EEPROM;\n\t\t\t}\n\t\t\tchecksum += word;\n\t\t}\n\t}\n\n\tchecksum = (u16)IXGBE_EEPROM_SUM - checksum;\n\n\treturn (s32)checksum;\n}\n\n/**\n * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum\n * @hw: pointer to hardware structure\n * @checksum_val: calculated checksum\n *\n * Performs checksum calculation and validates the EEPROM checksum. If the\n * caller does not need checksum_val, the value can be NULL.\n **/\ns32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,\n\t\t\t\t\tu16 *checksum_val)\n{\n\ts32 status;\n\tu16 checksum;\n\tu16 read_checksum = 0;\n\n\tDEBUGFUNC(\"ixgbe_validate_eeprom_checksum_X540\");\n\n\t/* Read the first word from the EEPROM. If this times out or fails, do\n\t * not continue or we could be in for a very long wait while every\n\t * EEPROM read fails\n\t */\n\tstatus = hw->eeprom.ops.read(hw, 0, &checksum);\n\tif (status) {\n\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\treturn status;\n\t}\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))\n\t\treturn IXGBE_ERR_SWFW_SYNC;\n\n\tstatus = hw->eeprom.ops.calc_checksum(hw);\n\tif (status < 0)\n\t\tgoto out;\n\n\tchecksum = (u16)(status & 0xffff);\n\n\t/* Do not use hw->eeprom.ops.read because we do not want to take\n\t * the synchronization semaphores twice here.\n\t */\n\tstatus = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,\n\t\t\t\t\t &read_checksum);\n\tif (status)\n\t\tgoto out;\n\n\t/* Verify read checksum from EEPROM is the same as\n\t * calculated checksum\n\t */\n\tif (read_checksum != checksum) {\n\t\tERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,\n\t\t\t \"Invalid EEPROM checksum\");\n\t\tstatus = IXGBE_ERR_EEPROM_CHECKSUM;\n\t}\n\n\t/* If the user cares, return the calculated checksum */\n\tif (checksum_val)\n\t\t*checksum_val = checksum;\n\nout:\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\n\treturn status;\n}\n\n/**\n * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash\n * @hw: pointer to hardware structure\n *\n * After writing EEPROM to shadow RAM using EEWR register, software calculates\n * checksum and updates the EEPROM and instructs the hardware to update\n * the flash.\n **/\ns32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\tu16 checksum;\n\n\tDEBUGFUNC(\"ixgbe_update_eeprom_checksum_X540\");\n\n\t/* Read the first word from the EEPROM. If this times out or fails, do\n\t * not continue or we could be in for a very long wait while every\n\t * EEPROM read fails\n\t */\n\tstatus = hw->eeprom.ops.read(hw, 0, &checksum);\n\tif (status) {\n\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\treturn status;\n\t}\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))\n\t\treturn IXGBE_ERR_SWFW_SYNC;\n\n\tstatus = hw->eeprom.ops.calc_checksum(hw);\n\tif (status < 0)\n\t\tgoto out;\n\n\tchecksum = (u16)(status & 0xffff);\n\n\t/* Do not use hw->eeprom.ops.write because we do not want to\n\t * take the synchronization semaphores twice here.\n\t */\n\tstatus = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);\n\tif (status)\n\t\tgoto out;\n\n\tstatus = ixgbe_update_flash_X540(hw);\n\nout:\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\n\treturn status;\n}\n\n/**\n * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device\n * @hw: pointer to hardware structure\n *\n * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy\n * EEPROM from shadow RAM to the flash device.\n **/\ns32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)\n{\n\tu32 flup;\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_update_flash_X540\");\n\n\tstatus = ixgbe_poll_flash_update_done_X540(hw);\n\tif (status == IXGBE_ERR_EEPROM) {\n\t\tDEBUGOUT(\"Flash update time out\\n\");\n\t\tgoto out;\n\t}\n\n\tflup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, flup);\n\n\tstatus = ixgbe_poll_flash_update_done_X540(hw);\n\tif (status == IXGBE_SUCCESS)\n\t\tDEBUGOUT(\"Flash update complete\\n\");\n\telse\n\t\tDEBUGOUT(\"Flash update time out\\n\");\n\n\tif (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {\n\t\tflup = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\t\tif (flup & IXGBE_EEC_SEC1VAL) {\n\t\t\tflup |= IXGBE_EEC_FLUP;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_EEC, flup);\n\t\t}\n\n\t\tstatus = ixgbe_poll_flash_update_done_X540(hw);\n\t\tif (status == IXGBE_SUCCESS)\n\t\t\tDEBUGOUT(\"Flash update complete\\n\");\n\t\telse\n\t\t\tDEBUGOUT(\"Flash update time out\\n\");\n\t}\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_poll_flash_update_done_X540 - Poll flash update status\n * @hw: pointer to hardware structure\n *\n * Polls the FLUDONE (bit 26) of the EEC Register to determine when the\n * flash update is done.\n **/\nSTATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)\n{\n\tu32 i;\n\tu32 reg;\n\ts32 status = IXGBE_ERR_EEPROM;\n\n\tDEBUGFUNC(\"ixgbe_poll_flash_update_done_X540\");\n\n\tfor (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {\n\t\treg = IXGBE_READ_REG(hw, IXGBE_EEC);\n\t\tif (reg & IXGBE_EEC_FLUDONE) {\n\t\t\tstatus = IXGBE_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\tmsec_delay(5);\n\t}\n\n\tif (i == IXGBE_FLUDONE_ATTEMPTS)\n\t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n\t\t\t \"Flash update status polling timed out\");\n\n\treturn status;\n}\n\n/**\n * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to acquire\n *\n * Acquires the SWFW semaphore thought the SW_FW_SYNC register for\n * the specified function (CSR, PHY0, PHY1, NVM, Flash)\n **/\ns32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)\n{\n\tu32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;\n\tu32 fwmask = swmask << 5;\n\tu32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;\n\tu32 timeout = 200;\n\tu32 hwmask = 0;\n\tu32 swfw_sync;\n\tu32 i;\n\n\tDEBUGFUNC(\"ixgbe_acquire_swfw_sync_X540\");\n\n\tif (swmask & IXGBE_GSSR_EEP_SM)\n\t\thwmask |= IXGBE_GSSR_FLASH_SM;\n\n\t/* SW only mask doesn't have FW bit pair */\n\tif (mask & IXGBE_GSSR_SW_MNG_SM)\n\t\tswmask |= IXGBE_GSSR_SW_MNG_SM;\n\n\tswmask |= swi2c_mask;\n\tfwmask |= swi2c_mask << 2;\n\tfor (i = 0; i < timeout; i++) {\n\t\t/* SW NVM semaphore bit is used for access to all\n\t\t * SW_FW_SYNC bits (not just NVM)\n\t\t */\n\t\tif (ixgbe_get_swfw_sync_semaphore(hw))\n\t\t\treturn IXGBE_ERR_SWFW_SYNC;\n\n\t\tswfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\n\t\tif (!(swfw_sync & (fwmask | swmask | hwmask))) {\n\t\t\tswfw_sync |= swmask;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);\n\t\t\tixgbe_release_swfw_sync_semaphore(hw);\n\t\t\tmsec_delay(5);\n\t\t\treturn IXGBE_SUCCESS;\n\t\t}\n\t\t/* Firmware currently using resource (fwmask), hardware\n\t\t * currently using resource (hwmask), or other software\n\t\t * thread currently using resource (swmask)\n\t\t */\n\t\tixgbe_release_swfw_sync_semaphore(hw);\n\t\tmsec_delay(5);\n\t}\n\n\t/* Failed to get SW only semaphore */\n\tif (swmask == IXGBE_GSSR_SW_MNG_SM) {\n\t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n\t\t\t \"Failed to get SW only semaphore\");\n\t\treturn IXGBE_ERR_SWFW_SYNC;\n\t}\n\n\t/* If the resource is not released by the FW/HW the SW can assume that\n\t * the FW/HW malfunctions. In that case the SW should set the SW bit(s)\n\t * of the requested resource(s) while ignoring the corresponding FW/HW\n\t * bits in the SW_FW_SYNC register.\n\t */\n\tif (ixgbe_get_swfw_sync_semaphore(hw))\n\t\treturn IXGBE_ERR_SWFW_SYNC;\n\tswfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\n\tif (swfw_sync & (fwmask | hwmask)) {\n\t\tswfw_sync |= swmask;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);\n\t\tixgbe_release_swfw_sync_semaphore(hw);\n\t\tmsec_delay(5);\n\t\treturn IXGBE_SUCCESS;\n\t}\n\t/* If the resource is not released by other SW the SW can assume that\n\t * the other SW malfunctions. In that case the SW should clear all SW\n\t * flags that it does not own and then repeat the whole process once\n\t * again.\n\t */\n\tif (swfw_sync & swmask) {\n\t\tu32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |\n\t\t\t IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;\n\n\t\tif (swi2c_mask)\n\t\t\trmask |= IXGBE_GSSR_I2C_MASK;\n\t\tixgbe_release_swfw_sync_X540(hw, rmask);\n\t\tixgbe_release_swfw_sync_semaphore(hw);\n\t\treturn IXGBE_ERR_SWFW_SYNC;\n\t}\n\tixgbe_release_swfw_sync_semaphore(hw);\n\n\treturn IXGBE_ERR_SWFW_SYNC;\n}\n\n/**\n * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to release\n *\n * Releases the SWFW semaphore through the SW_FW_SYNC register\n * for the specified function (CSR, PHY0, PHY1, EVM, Flash)\n **/\nvoid ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)\n{\n\tu32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);\n\tu32 swfw_sync;\n\n\tDEBUGFUNC(\"ixgbe_release_swfw_sync_X540\");\n\n\tif (mask & IXGBE_GSSR_I2C_MASK)\n\t\tswmask |= mask & IXGBE_GSSR_I2C_MASK;\n\tixgbe_get_swfw_sync_semaphore(hw);\n\n\tswfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\n\tswfw_sync &= ~swmask;\n\tIXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);\n\n\tixgbe_release_swfw_sync_semaphore(hw);\n\tmsec_delay(5);\n}\n\n/**\n * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore\n * @hw: pointer to hardware structure\n *\n * Sets the hardware semaphores so SW/FW can gain control of shared resources\n **/\nSTATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_EEPROM;\n\tu32 timeout = 2000;\n\tu32 i;\n\tu32 swsm;\n\n\tDEBUGFUNC(\"ixgbe_get_swfw_sync_semaphore\");\n\n\t/* Get SMBI software semaphore between device drivers first */\n\tfor (i = 0; i < timeout; i++) {\n\t\t/*\n\t\t * If the SMBI bit is 0 when we read it, then the bit will be\n\t\t * set and we have the semaphore\n\t\t */\n\t\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\t\tif (!(swsm & IXGBE_SWSM_SMBI)) {\n\t\t\tstatus = IXGBE_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\tusec_delay(50);\n\t}\n\n\t/* Now get the semaphore between SW/FW through the REGSMP bit */\n\tif (status == IXGBE_SUCCESS) {\n\t\tfor (i = 0; i < timeout; i++) {\n\t\t\tswsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\n\t\t\tif (!(swsm & IXGBE_SWFW_REGSMP))\n\t\t\t\tbreak;\n\n\t\t\tusec_delay(50);\n\t\t}\n\n\t\t/*\n\t\t * Release semaphores and return error if SW NVM semaphore\n\t\t * was not granted because we don't have access to the EEPROM\n\t\t */\n\t\tif (i >= timeout) {\n\t\t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n\t\t\t\t\"REGSMP Software NVM semaphore not granted.\\n\");\n\t\t\tixgbe_release_swfw_sync_semaphore(hw);\n\t\t\tstatus = IXGBE_ERR_EEPROM;\n\t\t}\n\t} else {\n\t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n\t\t\t \"Software semaphore SMBI between device drivers \"\n\t\t\t \"not granted.\\n\");\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore\n * @hw: pointer to hardware structure\n *\n * This function clears hardware semaphore bits.\n **/\nSTATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)\n{\n\tu32 swsm;\n\n\tDEBUGFUNC(\"ixgbe_release_swfw_sync_semaphore\");\n\n\t/* Release both semaphores by writing 0 to the bits REGSMP and SMBI */\n\n\tswsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\n\tswsm &= ~IXGBE_SWFW_REGSMP;\n\tIXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);\n\n\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\tswsm &= ~IXGBE_SWSM_SMBI;\n\tIXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);\n\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/**\n * ixgbe_blink_led_start_X540 - Blink LED based on index.\n * @hw: pointer to hardware structure\n * @index: led number to blink\n *\n * Devices that implement the version 2 interface:\n * X540\n **/\ns32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)\n{\n\tu32 macc_reg;\n\tu32 ledctl_reg;\n\tixgbe_link_speed speed;\n\tbool link_up;\n\n\tDEBUGFUNC(\"ixgbe_blink_led_start_X540\");\n\n\t/*\n\t * Link should be up in order for the blink bit in the LED control\n\t * register to work. Force link and speed in the MAC if link is down.\n\t * This will be reversed when we stop the blinking.\n\t */\n\thw->mac.ops.check_link(hw, &speed, &link_up, false);\n\tif (link_up == false) {\n\t\tmacc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);\n\t\tmacc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);\n\t}\n\t/* Set the LED to LINK_UP + BLINK. */\n\tledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\tledctl_reg &= ~IXGBE_LED_MODE_MASK(index);\n\tledctl_reg |= IXGBE_LED_BLINK(index);\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.\n * @hw: pointer to hardware structure\n * @index: led number to stop blinking\n *\n * Devices that implement the version 2 interface:\n * X540\n **/\ns32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)\n{\n\tu32 macc_reg;\n\tu32 ledctl_reg;\n\n\tDEBUGFUNC(\"ixgbe_blink_led_stop_X540\");\n\n\t/* Restore the LED to its default value. */\n\tledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\tledctl_reg &= ~IXGBE_LED_MODE_MASK(index);\n\tledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);\n\tledctl_reg &= ~IXGBE_LED_BLINK(index);\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);\n\n\t/* Unforce link and speed in the MAC. */\n\tmacc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);\n\tmacc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);\n\tIXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn IXGBE_SUCCESS;\n}\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_x540.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _IXGBE_X540_H_\n#define _IXGBE_X540_H_\n\n#include \"ixgbe_type.h\"\n\ns32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed, bool *autoneg);\nenum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw);\ns32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t\t bool link_up_wait_to_complete);\ns32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw);\ns32 ixgbe_start_hw_X540(struct ixgbe_hw *hw);\nu32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw);\n\ns32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw);\ns32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data);\ns32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, u16 offset, u16 words,\n\t\t\t\tu16 *data);\ns32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data);\ns32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, u16 offset, u16 words,\n\t\t\t\t u16 *data);\ns32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw);\ns32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val);\ns32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);\ns32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);\n\ns32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask);\nvoid ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask);\n\ns32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index);\n#endif /* _IXGBE_X540_H_ */\n\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_x550.c", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#include \"ixgbe_x550.h\"\n#include \"ixgbe_x540.h\"\n#include \"ixgbe_type.h\"\n#include \"ixgbe_api.h\"\n#include \"ixgbe_common.h\"\n#include \"ixgbe_phy.h\"\n\nSTATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed);\n\n/**\n * ixgbe_init_ops_X550 - Inits func ptrs and MAC type\n * @hw: pointer to hardware structure\n *\n * Initialize the function pointers and assign the MAC type for X550.\n * Does not touch the hardware.\n **/\ns32 ixgbe_init_ops_X550(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"ixgbe_init_ops_X550\");\n\n\tret_val = ixgbe_init_ops_X540(hw);\n\tmac->ops.dmac_config = ixgbe_dmac_config_X550;\n\tmac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550;\n\tmac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550;\n\tmac->ops.setup_eee = ixgbe_setup_eee_X550;\n\tmac->ops.set_source_address_pruning =\n\t\t\tixgbe_set_source_address_pruning_X550;\n\tmac->ops.set_ethertype_anti_spoofing =\n\t\t\tixgbe_set_ethertype_anti_spoofing_X550;\n\n\tmac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic;\n\teeprom->ops.init_params = ixgbe_init_eeprom_params_X550;\n\teeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;\n\teeprom->ops.read = ixgbe_read_ee_hostif_X550;\n\teeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;\n\teeprom->ops.write = ixgbe_write_ee_hostif_X550;\n\teeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;\n\teeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;\n\teeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;\n\n\tmac->ops.disable_mdd = ixgbe_disable_mdd_X550;\n\tmac->ops.enable_mdd = ixgbe_enable_mdd_X550;\n\tmac->ops.mdd_event = ixgbe_mdd_event_X550;\n\tmac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550;\n\tmac->ops.disable_rx = ixgbe_disable_rx_x550;\n\tif (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {\n\t\thw->mac.ops.led_on = ixgbe_led_on_t_X550em;\n\t\thw->mac.ops.led_off = ixgbe_led_off_t_X550em;\n\t}\n\treturn ret_val;\n}\n\n/**\n * ixgbe_read_cs4227 - Read CS4227 register\n * @hw: pointer to hardware structure\n * @reg: register number to write\n * @value: pointer to receive value read\n *\n * Returns status code\n **/\nSTATIC s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)\n{\n\treturn ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);\n}\n\n/**\n * ixgbe_write_cs4227 - Write CS4227 register\n * @hw: pointer to hardware structure\n * @reg: register number to write\n * @value: value to write to register\n *\n * Returns status code\n **/\nSTATIC s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)\n{\n\treturn ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value);\n}\n\n/**\n * ixgbe_get_cs4227_status - Return CS4227 status\n * @hw: pointer to hardware structure\n *\n * Performs a diagnostic on the CS4227 chip. Returns an error if it is\n * not operating correctly.\n * This function assumes that the caller has acquired the proper semaphore.\n **/\nSTATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\tu16 value = 0;\n\tu16 reg_slice, reg_val;\n\tu8 retry;\n\n\t/* Check register reads. */\n\tfor (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) {\n\t\tstatus = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB,\n\t\t\t\t\t &value);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\t\tif (value == IXGBE_CS4227_GLOBAL_ID_VALUE)\n\t\t\tbreak;\n\t\tmsec_delay(IXGBE_CS4227_CHECK_DELAY);\n\t}\n\tif (value != IXGBE_CS4227_GLOBAL_ID_VALUE)\n\t\treturn IXGBE_ERR_PHY;\n\n\tstatus = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* If this is the first time after power-on, check the ucode.\n\t * Otherwise, this will disrupt link on all ports. Because we\n\t * can only do this the first time, we must check all ports,\n\t * not just our own.\n\t * While we are at it, set the LINE side to 10G SR, which is\n\t * what it needs to be regardless of the actual link.\n\t */\n\tif (value != IXGBE_CS4227_SCRATCH_VALUE) {\n\t\treg_slice = IXGBE_CS4227_LINE_SPARE22_MSB;\n\t\treg_val = IXGBE_CS4227_SPEED_10G;\n\t\tstatus = ixgbe_write_cs4227(hw, reg_slice, reg_val);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\treg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;\n\t\treg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;\n\t\tstatus = ixgbe_write_cs4227(hw, reg_slice, reg_val);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\treg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;\n\t\treg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;\n\t\tstatus = ixgbe_write_cs4227(hw, reg_slice, reg_val);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\treg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (1 << 12);\n\t\treg_val = IXGBE_CS4227_SPEED_10G;\n\t\tstatus = ixgbe_write_cs4227(hw, reg_slice, reg_val);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\treg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);\n\t\treg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;\n\t\tstatus = ixgbe_write_cs4227(hw, reg_slice, reg_val);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\treg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);\n\t\treg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;\n\t\tstatus = ixgbe_write_cs4227(hw, reg_slice, reg_val);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\tmsec_delay(10);\n\t}\n\n\t/* Verify that the ucode is operational on all ports. */\n\treg_slice = IXGBE_CS4227_LINE_SPARE24_LSB;\n\treg_val = 0xFFFF;\n\tstatus = ixgbe_read_cs4227(hw, reg_slice, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\tif (reg_val != 0)\n\t\treturn IXGBE_ERR_PHY;\n\n\treg_slice = IXGBE_CS4227_HOST_SPARE24_LSB;\n\treg_val = 0xFFFF;\n\tstatus = ixgbe_read_cs4227(hw, reg_slice, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\tif (reg_val != 0)\n\t\treturn IXGBE_ERR_PHY;\n\n\treg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12);\n\treg_val = 0xFFFF;\n\tstatus = ixgbe_read_cs4227(hw, reg_slice, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\tif (reg_val != 0)\n\t\treturn IXGBE_ERR_PHY;\n\n\treg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12);\n\treg_val = 0xFFFF;\n\tstatus = ixgbe_read_cs4227(hw, reg_slice, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\tif (reg_val != 0)\n\t\treturn IXGBE_ERR_PHY;\n\n\t/* Set scratch indicating that the diagnostic was successful. */\n\tstatus = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,\n\t\t\t\t IXGBE_CS4227_SCRATCH_VALUE);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\tstatus = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\tif (value != IXGBE_CS4227_SCRATCH_VALUE)\n\t\treturn IXGBE_ERR_PHY;\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_read_pe - Read register from port expander\n * @hw: pointer to hardware structure\n * @reg: register number to read\n * @value: pointer to receive read value\n *\n * Returns status code\n **/\nSTATIC s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)\n{\n\ts32 status;\n\n\tstatus = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);\n\tif (status != IXGBE_SUCCESS)\n\t\tERROR_REPORT2(IXGBE_ERROR_CAUTION,\n\t\t\t \"port expander access failed with %d\\n\", status);\n\treturn status;\n}\n\n/**\n * ixgbe_write_pe - Write register to port expander\n * @hw: pointer to hardware structure\n * @reg: register number to write\n * @value: value to write\n *\n * Returns status code\n **/\nSTATIC s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)\n{\n\ts32 status;\n\n\tstatus = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value);\n\tif (status != IXGBE_SUCCESS)\n\t\tERROR_REPORT2(IXGBE_ERROR_CAUTION,\n\t\t\t \"port expander access failed with %d\\n\", status);\n\treturn status;\n}\n\n/**\n * ixgbe_reset_cs4227 - Reset CS4227 using port expander\n * @hw: pointer to hardware structure\n *\n * Returns error code\n **/\nSTATIC s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\tu8 reg;\n\n\tstatus = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg |= IXGBE_PE_BIT1;\n\tstatus = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tstatus = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg &= ~IXGBE_PE_BIT1;\n\tstatus = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tstatus = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg &= ~IXGBE_PE_BIT1;\n\tstatus = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tusec_delay(IXGBE_CS4227_RESET_HOLD);\n\n\tstatus = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg |= IXGBE_PE_BIT1;\n\tstatus = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tmsec_delay(IXGBE_CS4227_RESET_DELAY);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_check_cs4227 - Check CS4227 and reset as needed\n * @hw: pointer to hardware structure\n **/\nSTATIC void ixgbe_check_cs4227(struct ixgbe_hw *hw)\n{\n\tu32 swfw_mask = hw->phy.phy_semaphore_mask;\n\ts32 status;\n\tu8 retry;\n\n\tfor (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {\n\t\tstatus = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);\n\t\tif (status != IXGBE_SUCCESS) {\n\t\t\tERROR_REPORT2(IXGBE_ERROR_CAUTION,\n\t\t\t\t \"semaphore failed with %d\\n\", status);\n\t\t\treturn;\n\t\t}\n\t\tstatus = ixgbe_get_cs4227_status(hw);\n\t\tif (status == IXGBE_SUCCESS) {\n\t\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\t\t\tmsec_delay(hw->eeprom.semaphore_delay);\n\t\t\treturn;\n\t\t}\n\t\tixgbe_reset_cs4227(hw);\n\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\t\tmsec_delay(hw->eeprom.semaphore_delay);\n\t}\n\tERROR_REPORT2(IXGBE_ERROR_CAUTION,\n\t\t \"Unable to initialize CS4227, err=%d\\n\", status);\n}\n\n/**\n * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control\n * @hw: pointer to hardware structure\n **/\nSTATIC void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)\n{\n\tu32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\n\tif (hw->bus.lan_id) {\n\t\tesdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);\n\t\tesdp |= IXGBE_ESDP_SDP1_DIR;\n\t}\n\tesdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);\n\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/**\n * ixgbe_identify_phy_x550em - Get PHY type based on device id\n * @hw: pointer to hardware structure\n *\n * Returns error code\n */\nSTATIC s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)\n{\n\tswitch (hw->device_id) {\n\tcase IXGBE_DEV_ID_X550EM_X_SFP:\n\t\t/* set up for CS4227 usage */\n\t\thw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;\n\t\tixgbe_setup_mux_ctl(hw);\n\t\tixgbe_check_cs4227(hw);\n\n\t\treturn ixgbe_identify_module_generic(hw);\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X550EM_X_KX4:\n\t\thw->phy.type = ixgbe_phy_x550em_kx4;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X550EM_X_KR:\n\t\thw->phy.type = ixgbe_phy_x550em_kr;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X550EM_X_1G_T:\n\tcase IXGBE_DEV_ID_X550EM_X_10G_T:\n\t\treturn ixgbe_identify_phy_generic(hw);\n\tdefault:\n\t\tbreak;\n\t}\n\treturn IXGBE_SUCCESS;\n}\n\nSTATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t\t u32 device_type, u16 *phy_data)\n{\n\tUNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data);\n\treturn IXGBE_NOT_IMPLEMENTED;\n}\n\nSTATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t\t u32 device_type, u16 phy_data)\n{\n\tUNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data);\n\treturn IXGBE_NOT_IMPLEMENTED;\n}\n\n/**\n* ixgbe_init_ops_X550EM - Inits func ptrs and MAC type\n* @hw: pointer to hardware structure\n*\n* Initialize the function pointers and for MAC type X550EM.\n* Does not touch the hardware.\n**/\ns32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"ixgbe_init_ops_X550EM\");\n\n\t/* Similar to X550 so start there. */\n\tret_val = ixgbe_init_ops_X550(hw);\n\n\t/* Since this function eventually calls\n\t * ixgbe_init_ops_540 by design, we are setting\n\t * the pointers to NULL explicitly here to overwrite\n\t * the values being set in the x540 function.\n\t */\n\t/* Thermal sensor not supported in x550EM */\n\tmac->ops.get_thermal_sensor_data = NULL;\n\tmac->ops.init_thermal_sensor_thresh = NULL;\n\tmac->thermal_sensor_enabled = false;\n\n\t/* FCOE not supported in x550EM */\n\tmac->ops.get_san_mac_addr = NULL;\n\tmac->ops.set_san_mac_addr = NULL;\n\tmac->ops.get_wwn_prefix = NULL;\n\tmac->ops.get_fcoe_boot_status = NULL;\n\n\t/* IPsec not supported in x550EM */\n\tmac->ops.disable_sec_rx_path = NULL;\n\tmac->ops.enable_sec_rx_path = NULL;\n\n\t/* AUTOC register is not present in x550EM. */\n\tmac->ops.prot_autoc_read = NULL;\n\tmac->ops.prot_autoc_write = NULL;\n\n\t/* X550EM bus type is internal*/\n\thw->bus.type = ixgbe_bus_type_internal;\n\tmac->ops.get_bus_info = ixgbe_get_bus_info_X550em;\n\n\tmac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550;\n\tmac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550;\n\tmac->ops.get_media_type = ixgbe_get_media_type_X550em;\n\tmac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em;\n\tmac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em;\n\tmac->ops.reset_hw = ixgbe_reset_hw_X550em;\n\tmac->ops.get_supported_physical_layer =\n\t\t\t\t ixgbe_get_supported_physical_layer_X550em;\n\n\tif (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)\n\t\tmac->ops.setup_fc = ixgbe_setup_fc_generic;\n\telse\n\t\tmac->ops.setup_fc = ixgbe_setup_fc_X550em;\n\n\tmac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em;\n\tmac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em;\n\n\tif (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR)\n\t\tmac->ops.setup_eee = NULL;\n\n\t/* PHY */\n\tphy->ops.init = ixgbe_init_phy_ops_X550em;\n\tphy->ops.identify = ixgbe_identify_phy_x550em;\n\tif (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)\n\t\tphy->ops.set_phy_power = NULL;\n\n\n\t/* EEPROM */\n\teeprom->ops.init_params = ixgbe_init_eeprom_params_X540;\n\teeprom->ops.read = ixgbe_read_ee_hostif_X550;\n\teeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550;\n\teeprom->ops.write = ixgbe_write_ee_hostif_X550;\n\teeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550;\n\teeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550;\n\teeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550;\n\teeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550;\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_dmac_config_X550\n * @hw: pointer to hardware structure\n *\n * Configure DMA coalescing. If enabling dmac, dmac is activated.\n * When disabling dmac, dmac enable dmac bit is cleared.\n **/\ns32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw)\n{\n\tu32 reg, high_pri_tc;\n\n\tDEBUGFUNC(\"ixgbe_dmac_config_X550\");\n\n\t/* Disable DMA coalescing before configuring */\n\treg = IXGBE_READ_REG(hw, IXGBE_DMACR);\n\treg &= ~IXGBE_DMACR_DMAC_EN;\n\tIXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);\n\n\t/* Disable DMA Coalescing if the watchdog timer is 0 */\n\tif (!hw->mac.dmac_config.watchdog_timer)\n\t\tgoto out;\n\n\tixgbe_dmac_config_tcs_X550(hw);\n\n\t/* Configure DMA Coalescing Control Register */\n\treg = IXGBE_READ_REG(hw, IXGBE_DMACR);\n\n\t/* Set the watchdog timer in units of 40.96 usec */\n\treg &= ~IXGBE_DMACR_DMACWT_MASK;\n\treg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096;\n\n\treg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK;\n\t/* If fcoe is enabled, set high priority traffic class */\n\tif (hw->mac.dmac_config.fcoe_en) {\n\t\thigh_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc;\n\t\treg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) &\n\t\t\tIXGBE_DMACR_HIGH_PRI_TC_MASK);\n\t}\n\treg |= IXGBE_DMACR_EN_MNG_IND;\n\n\t/* Enable DMA coalescing after configuration */\n\treg |= IXGBE_DMACR_DMAC_EN;\n\tIXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);\n\nout:\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dmac_config_tcs_X550\n * @hw: pointer to hardware structure\n *\n * Configure DMA coalescing threshold per TC. The dmac enable bit must\n * be cleared before configuring.\n **/\ns32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw)\n{\n\tu32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb;\n\n\tDEBUGFUNC(\"ixgbe_dmac_config_tcs_X550\");\n\n\t/* Configure DMA coalescing enabled */\n\tswitch (hw->mac.dmac_config.link_speed) {\n\tcase IXGBE_LINK_SPEED_100_FULL:\n\t\tpb_headroom = IXGBE_DMACRXT_100M;\n\t\tbreak;\n\tcase IXGBE_LINK_SPEED_1GB_FULL:\n\t\tpb_headroom = IXGBE_DMACRXT_1G;\n\t\tbreak;\n\tdefault:\n\t\tpb_headroom = IXGBE_DMACRXT_10G;\n\t\tbreak;\n\t}\n\n\tmaxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >>\n\t\t\t IXGBE_MHADD_MFS_SHIFT) / 1024);\n\n\t/* Set the per Rx packet buffer receive threshold */\n\tfor (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {\n\t\treg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc));\n\t\treg &= ~IXGBE_DMCTH_DMACRXT_MASK;\n\n\t\tif (tc < hw->mac.dmac_config.num_tcs) {\n\t\t\t/* Get Rx PB size */\n\t\t\trx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc));\n\t\t\trx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >>\n\t\t\t\tIXGBE_RXPBSIZE_SHIFT;\n\n\t\t\t/* Calculate receive buffer threshold in kilobytes */\n\t\t\tif (rx_pb_size > pb_headroom)\n\t\t\t\trx_pb_size = rx_pb_size - pb_headroom;\n\t\t\telse\n\t\t\t\trx_pb_size = 0;\n\n\t\t\t/* Minimum of MFS shall be set for DMCTH */\n\t\t\treg |= (rx_pb_size > maxframe_size_kb) ?\n\t\t\t\trx_pb_size : maxframe_size_kb;\n\t\t}\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg);\n\t}\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_dmac_update_tcs_X550\n * @hw: pointer to hardware structure\n *\n * Disables dmac, updates per TC settings, and then enables dmac.\n **/\ns32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw)\n{\n\tu32 reg;\n\n\tDEBUGFUNC(\"ixgbe_dmac_update_tcs_X550\");\n\n\t/* Disable DMA coalescing before configuring */\n\treg = IXGBE_READ_REG(hw, IXGBE_DMACR);\n\treg &= ~IXGBE_DMACR_DMAC_EN;\n\tIXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);\n\n\tixgbe_dmac_config_tcs_X550(hw);\n\n\t/* Enable DMA coalescing after configuration */\n\treg = IXGBE_READ_REG(hw, IXGBE_DMACR);\n\treg |= IXGBE_DMACR_DMAC_EN;\n\tIXGBE_WRITE_REG(hw, IXGBE_DMACR, reg);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params\n * @hw: pointer to hardware structure\n *\n * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n * ixgbe_hw struct in order to set up EEPROM access.\n **/\ns32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\tu32 eec;\n\tu16 eeprom_size;\n\n\tDEBUGFUNC(\"ixgbe_init_eeprom_params_X550\");\n\n\tif (eeprom->type == ixgbe_eeprom_uninitialized) {\n\t\teeprom->semaphore_delay = 10;\n\t\teeprom->type = ixgbe_flash;\n\n\t\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\t\teeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>\n\t\t\t\t IXGBE_EEC_SIZE_SHIFT);\n\t\teeprom->word_size = 1 << (eeprom_size +\n\t\t\t\t\t IXGBE_EEPROM_WORD_SIZE_SHIFT);\n\n\t\tDEBUGOUT2(\"Eeprom params: type = %d, size = %d\\n\",\n\t\t\t eeprom->type, eeprom->word_size);\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_setup_eee_X550 - Enable/disable EEE support\n * @hw: pointer to the HW structure\n * @enable_eee: boolean flag to enable EEE\n *\n * Enable/disable EEE based on enable_eee flag.\n * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C\n * are modified.\n *\n **/\ns32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee)\n{\n\tu32 eeer;\n\tu16 autoneg_eee_reg;\n\tu32 link_reg;\n\ts32 status;\n\tu32 fuse;\n\n\tDEBUGFUNC(\"ixgbe_setup_eee_X550\");\n\n\teeer = IXGBE_READ_REG(hw, IXGBE_EEER);\n\t/* Enable or disable EEE per flag */\n\tif (enable_eee) {\n\t\teeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);\n\n\t\tif (hw->device_id == IXGBE_DEV_ID_X550T) {\n\t\t\t/* Advertise EEE capability */\n\t\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,\n\t\t\t\tIXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);\n\n\t\t\tautoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |\n\t\t\t\tIXGBE_AUTO_NEG_1000BASE_EEE_ADVT |\n\t\t\t\tIXGBE_AUTO_NEG_100BASE_EEE_ADVT);\n\n\t\t\thw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,\n\t\t\t\tIXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);\n\t\t} else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {\n\t\t\t/* Not supported on first revision. */\n\t\t\tfuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));\n\t\t\tif (!(fuse & IXGBE_FUSES0_REV1))\n\t\t\t\treturn IXGBE_SUCCESS;\n\n\t\t\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);\n\t\t\tif (status != IXGBE_SUCCESS)\n\t\t\t\treturn status;\n\n\t\t\tlink_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |\n\t\t\t\t IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX;\n\n\t\t\t/* Don't advertise FEC capability when EEE enabled. */\n\t\t\tlink_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;\n\n\t\t\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);\n\t\t\tif (status != IXGBE_SUCCESS)\n\t\t\t\treturn status;\n\t\t}\n\t} else {\n\t\teeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN);\n\n\t\tif (hw->device_id == IXGBE_DEV_ID_X550T) {\n\t\t\t/* Disable advertised EEE capability */\n\t\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,\n\t\t\t\tIXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg);\n\n\t\t\tautoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT |\n\t\t\t\tIXGBE_AUTO_NEG_1000BASE_EEE_ADVT |\n\t\t\t\tIXGBE_AUTO_NEG_100BASE_EEE_ADVT);\n\n\t\t\thw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT,\n\t\t\t\tIXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg);\n\t\t} else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {\n\t\t\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg);\n\t\t\tif (status != IXGBE_SUCCESS)\n\t\t\t\treturn status;\n\n\t\t\tlink_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR |\n\t\t\t\tIXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX);\n\n\t\t\t/* Advertise FEC capability when EEE is disabled. */\n\t\t\tlink_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC;\n\n\t\t\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, link_reg);\n\t\t\tif (status != IXGBE_SUCCESS)\n\t\t\t\treturn status;\n\t\t}\n\t}\n\tIXGBE_WRITE_REG(hw, IXGBE_EEER, eeer);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning\n * @hw: pointer to hardware structure\n * @enable: enable or disable source address pruning\n * @pool: Rx pool to set source address pruning for\n **/\nvoid ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,\n\t\t\t\t\t unsigned int pool)\n{\n\tu64 pfflp;\n\n\t/* max rx pool is 63 */\n\tif (pool > 63)\n\t\treturn;\n\n\tpfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);\n\tpfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;\n\n\tif (enable)\n\t\tpfflp |= (1ULL << pool);\n\telse\n\t\tpfflp &= ~(1ULL << pool);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);\n\tIXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));\n}\n\n/**\n * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing\n * @hw: pointer to hardware structure\n * @enable: enable or disable switch for Ethertype anti-spoofing\n * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing\n *\n **/\nvoid ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,\n\t\tbool enable, int vf)\n{\n\tint vf_target_reg = vf >> 3;\n\tint vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;\n\tu32 pfvfspoof;\n\n\tDEBUGFUNC(\"ixgbe_set_ethertype_anti_spoofing_X550\");\n\n\tpfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));\n\tif (enable)\n\t\tpfvfspoof |= (1 << vf_target_shift);\n\telse\n\t\tpfvfspoof &= ~(1 << vf_target_shift);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);\n}\n\n/**\n * ixgbe_iosf_wait - Wait for IOSF command completion\n * @hw: pointer to hardware structure\n * @ctrl: pointer to location to receive final IOSF control value\n *\n * Returns failing status on timeout\n *\n * Note: ctrl can be NULL if the IOSF control register value is not needed\n **/\nSTATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)\n{\n\tu32 i, command = 0;\n\n\t/* Check every 10 usec to see if the address cycle completed.\n\t * The SB IOSF BUSY bit will clear when the operation is\n\t * complete\n\t */\n\tfor (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {\n\t\tcommand = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);\n\t\tif ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0)\n\t\t\tbreak;\n\t\tusec_delay(10);\n\t}\n\tif (ctrl)\n\t\t*ctrl = command;\n\tif (i == IXGBE_MDIO_COMMAND_TIMEOUT) {\n\t\tERROR_REPORT1(IXGBE_ERROR_POLLING, \"Wait timed out\\n\");\n\t\treturn IXGBE_ERR_PHY;\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF\n * device\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit PHY register to write\n * @device_type: 3 bit device type\n * @data: Data to write to the register\n **/\ns32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t u32 device_type, u32 data)\n{\n\tu32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;\n\tu32 command, error;\n\ts32 ret;\n\n\tret = ixgbe_acquire_swfw_semaphore(hw, gssr);\n\tif (ret != IXGBE_SUCCESS)\n\t\treturn ret;\n\n\tret = ixgbe_iosf_wait(hw, NULL);\n\tif (ret != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\tcommand = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |\n\t\t (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));\n\n\t/* Write IOSF control register */\n\tIXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);\n\n\t/* Write IOSF data register */\n\tIXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);\n\n\tret = ixgbe_iosf_wait(hw, &command);\n\n\tif ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {\n\t\terror = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>\n\t\t\t IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;\n\t\tERROR_REPORT2(IXGBE_ERROR_POLLING,\n\t\t\t \"Failed to write, error %x\\n\", error);\n\t\tret = IXGBE_ERR_PHY;\n\t}\n\nout:\n\tixgbe_release_swfw_semaphore(hw, gssr);\n\treturn ret;\n}\n\n/**\n * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF\n * device\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit PHY register to write\n * @device_type: 3 bit device type\n * @phy_data: Pointer to read data from the register\n **/\ns32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t u32 device_type, u32 *data)\n{\n\tu32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;\n\tu32 command, error;\n\ts32 ret;\n\n\tret = ixgbe_acquire_swfw_semaphore(hw, gssr);\n\tif (ret != IXGBE_SUCCESS)\n\t\treturn ret;\n\n\tret = ixgbe_iosf_wait(hw, NULL);\n\tif (ret != IXGBE_SUCCESS)\n\t\tgoto out;\n\n\tcommand = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |\n\t\t (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));\n\n\t/* Write IOSF control register */\n\tIXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);\n\n\tret = ixgbe_iosf_wait(hw, &command);\n\n\tif ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {\n\t\terror = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>\n\t\t\t IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;\n\t\tERROR_REPORT2(IXGBE_ERROR_POLLING,\n\t\t\t\t\"Failed to read, error %x\\n\", error);\n\t\tret = IXGBE_ERR_PHY;\n\t}\n\n\tif (ret == IXGBE_SUCCESS)\n\t\t*data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);\n\nout:\n\tixgbe_release_swfw_semaphore(hw, gssr);\n\treturn ret;\n}\n\n/**\n * ixgbe_disable_mdd_X550\n * @hw: pointer to hardware structure\n *\n * Disable malicious driver detection\n **/\nvoid ixgbe_disable_mdd_X550(struct ixgbe_hw *hw)\n{\n\tu32 reg;\n\n\tDEBUGFUNC(\"ixgbe_disable_mdd_X550\");\n\n\t/* Disable MDD for TX DMA and interrupt */\n\treg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);\n\treg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);\n\tIXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);\n\n\t/* Disable MDD for RX and interrupt */\n\treg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);\n\treg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);\n\tIXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);\n}\n\n/**\n * ixgbe_enable_mdd_X550\n * @hw: pointer to hardware structure\n *\n * Enable malicious driver detection\n **/\nvoid ixgbe_enable_mdd_X550(struct ixgbe_hw *hw)\n{\n\tu32 reg;\n\n\tDEBUGFUNC(\"ixgbe_enable_mdd_X550\");\n\n\t/* Enable MDD for TX DMA and interrupt */\n\treg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);\n\treg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN);\n\tIXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);\n\n\t/* Enable MDD for RX and interrupt */\n\treg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);\n\treg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN);\n\tIXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);\n}\n\n/**\n * ixgbe_restore_mdd_vf_X550\n * @hw: pointer to hardware structure\n * @vf: vf index\n *\n * Restore VF that was disabled during malicious driver detection event\n **/\nvoid ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf)\n{\n\tu32 idx, reg, num_qs, start_q, bitmask;\n\n\tDEBUGFUNC(\"ixgbe_restore_mdd_vf_X550\");\n\n\t/* Map VF to queues */\n\treg = IXGBE_READ_REG(hw, IXGBE_MRQC);\n\tswitch (reg & IXGBE_MRQC_MRQE_MASK) {\n\tcase IXGBE_MRQC_VMDQRT8TCEN:\n\t\tnum_qs = 8; /* 16 VFs / pools */\n\t\tbitmask = 0x000000FF;\n\t\tbreak;\n\tcase IXGBE_MRQC_VMDQRSS32EN:\n\tcase IXGBE_MRQC_VMDQRT4TCEN:\n\t\tnum_qs = 4; /* 32 VFs / pools */\n\t\tbitmask = 0x0000000F;\n\t\tbreak;\n\tdefault: /* 64 VFs / pools */\n\t\tnum_qs = 2;\n\t\tbitmask = 0x00000003;\n\t\tbreak;\n\t}\n\tstart_q = vf * num_qs;\n\n\t/* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */\n\tidx = start_q / 32;\n\treg = 0;\n\treg |= (bitmask << (start_q % 32));\n\tIXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg);\n\tIXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg);\n}\n\n/**\n * ixgbe_mdd_event_X550\n * @hw: pointer to hardware structure\n * @vf_bitmap: vf bitmap of malicious vfs\n *\n * Handle malicious driver detection event.\n **/\nvoid ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap)\n{\n\tu32 wqbr;\n\tu32 i, j, reg, q, shift, vf, idx;\n\n\tDEBUGFUNC(\"ixgbe_mdd_event_X550\");\n\n\t/* figure out pool size for mapping to vf's */\n\treg = IXGBE_READ_REG(hw, IXGBE_MRQC);\n\tswitch (reg & IXGBE_MRQC_MRQE_MASK) {\n\tcase IXGBE_MRQC_VMDQRT8TCEN:\n\t\tshift = 3; /* 16 VFs / pools */\n\t\tbreak;\n\tcase IXGBE_MRQC_VMDQRSS32EN:\n\tcase IXGBE_MRQC_VMDQRT4TCEN:\n\t\tshift = 2; /* 32 VFs / pools */\n\t\tbreak;\n\tdefault:\n\t\tshift = 1; /* 64 VFs / pools */\n\t\tbreak;\n\t}\n\n\t/* Read WQBR_TX and WQBR_RX and check for malicious queues */\n\tfor (i = 0; i < 4; i++) {\n\t\twqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i));\n\t\twqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i));\n\n\t\tif (!wqbr)\n\t\t\tcontinue;\n\n\t\t/* Get malicious queue */\n\t\tfor (j = 0; j < 32 && wqbr; j++) {\n\n\t\t\tif (!(wqbr & (1 << j)))\n\t\t\t\tcontinue;\n\n\t\t\t/* Get queue from bitmask */\n\t\t\tq = j + (i * 32);\n\n\t\t\t/* Map queue to vf */\n\t\t\tvf = (q >> shift);\n\n\t\t\t/* Set vf bit in vf_bitmap */\n\t\t\tidx = vf / 32;\n\t\t\tvf_bitmap[idx] |= (1 << (vf % 32));\n\t\t\twqbr &= ~(1 << j);\n\t\t}\n\t}\n}\n\n/**\n * ixgbe_get_media_type_X550em - Get media type\n * @hw: pointer to hardware structure\n *\n * Returns the media type (fiber, copper, backplane)\n */\nenum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)\n{\n\tenum ixgbe_media_type media_type;\n\n\tDEBUGFUNC(\"ixgbe_get_media_type_X550em\");\n\n\t/* Detect if there is a copper PHY attached. */\n\tswitch (hw->device_id) {\n\tcase IXGBE_DEV_ID_X550EM_X_KR:\n\tcase IXGBE_DEV_ID_X550EM_X_KX4:\n\t\tmedia_type = ixgbe_media_type_backplane;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X550EM_X_SFP:\n\t\tmedia_type = ixgbe_media_type_fiber;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X550EM_X_1G_T:\n\tcase IXGBE_DEV_ID_X550EM_X_10G_T:\n\t\tmedia_type = ixgbe_media_type_copper;\n\t\tbreak;\n\tdefault:\n\t\tmedia_type = ixgbe_media_type_unknown;\n\t\tbreak;\n\t}\n\treturn media_type;\n}\n\n/**\n * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported\n * @hw: pointer to hardware structure\n * @linear: true if SFP module is linear\n */\nSTATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)\n{\n\tDEBUGFUNC(\"ixgbe_supported_sfp_modules_X550em\");\n\n\tswitch (hw->phy.sfp_type) {\n\tcase ixgbe_sfp_type_not_present:\n\t\treturn IXGBE_ERR_SFP_NOT_PRESENT;\n\tcase ixgbe_sfp_type_da_cu_core0:\n\tcase ixgbe_sfp_type_da_cu_core1:\n\t\t*linear = true;\n\t\tbreak;\n\tcase ixgbe_sfp_type_srlr_core0:\n\tcase ixgbe_sfp_type_srlr_core1:\n\tcase ixgbe_sfp_type_da_act_lmt_core0:\n\tcase ixgbe_sfp_type_da_act_lmt_core1:\n\tcase ixgbe_sfp_type_1g_sx_core0:\n\tcase ixgbe_sfp_type_1g_sx_core1:\n\tcase ixgbe_sfp_type_1g_lx_core0:\n\tcase ixgbe_sfp_type_1g_lx_core1:\n\t\t*linear = false;\n\t\tbreak;\n\tcase ixgbe_sfp_type_unknown:\n\tcase ixgbe_sfp_type_1g_cu_core0:\n\tcase ixgbe_sfp_type_1g_cu_core1:\n\tdefault:\n\t\treturn IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_identify_sfp_module_X550em - Identifies SFP modules\n * @hw: pointer to hardware structure\n *\n * Searches for and identifies the SFP module and assigns appropriate PHY type.\n **/\ns32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\tbool linear;\n\n\tDEBUGFUNC(\"ixgbe_identify_sfp_module_X550em\");\n\n\tstatus = ixgbe_identify_module_generic(hw);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Check if SFP module is supported */\n\tstatus = ixgbe_supported_sfp_modules_X550em(hw, &linear);\n\n\treturn status;\n}\n\n/**\n * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops\n * @hw: pointer to hardware structure\n */\ns32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\tbool linear;\n\n\tDEBUGFUNC(\"ixgbe_setup_sfp_modules_X550em\");\n\n\t/* Check if SFP module is supported */\n\tstatus = ixgbe_supported_sfp_modules_X550em(hw, &linear);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tixgbe_init_mac_link_ops_X550em(hw);\n\thw->phy.ops.reset = NULL;\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_init_mac_link_ops_X550em - init mac link function pointers\n * @hw: pointer to hardware structure\n */\nvoid ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"ixgbe_init_mac_link_ops_X550em\");\n\n\t switch (hw->mac.ops.get_media_type(hw)) {\n\t case ixgbe_media_type_fiber:\n\t\t/* CS4227 does not support autoneg, so disable the laser control\n\t\t * functions for SFP+ fiber\n\t\t */\n\t\tmac->ops.disable_tx_laser = NULL;\n\t\tmac->ops.enable_tx_laser = NULL;\n\t\tmac->ops.flap_tx_laser = NULL;\n\t\tmac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;\n\t\tmac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em;\n\t\tmac->ops.set_rate_select_speed =\n\t\t\t\t\tixgbe_set_soft_rate_select_speed;\n\t\tbreak;\n\tcase ixgbe_media_type_copper:\n\t\tmac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;\n\t\tmac->ops.check_link = ixgbe_check_link_t_X550em;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t }\n}\n\n/**\n * ixgbe_get_link_capabilities_x550em - Determines link capabilities\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @autoneg: true when autoneg or autotry is enabled\n */\ns32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t bool *autoneg)\n{\n\tDEBUGFUNC(\"ixgbe_get_link_capabilities_X550em\");\n\n\t/* SFP */\n\tif (hw->phy.media_type == ixgbe_media_type_fiber) {\n\n\t\t/* CS4227 SFP must not enable auto-negotiation */\n\t\t*autoneg = false;\n\n\t\t/* Check if 1G SFP module. */\n\t\tif (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1\n\t\t || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {\n\t\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t\treturn IXGBE_SUCCESS;\n\t\t}\n\n\t\t/* Link capabilities are based on SFP */\n\t\tif (hw->phy.multispeed_fiber)\n\t\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL |\n\t\t\t\t IXGBE_LINK_SPEED_1GB_FULL;\n\t\telse\n\t\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\t} else {\n\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL |\n\t\t\t IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*autoneg = true;\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause\n * @hw: pointer to hardware structure\n * @lsc: pointer to boolean flag which indicates whether external Base T\n * PHY interrupt is lsc\n *\n * Determime if external Base T PHY interrupt cause is high temperature\n * failure alarm or link status change.\n *\n * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature\n * failure alarm, else return PHY access status.\n */\nSTATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)\n{\n\tu32 status;\n\tu16 reg;\n\n\t*lsc = false;\n\n\t/* Vendor alarm triggered */\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t ®);\n\n\tif (status != IXGBE_SUCCESS ||\n\t !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))\n\t\treturn status;\n\n\t/* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t ®);\n\n\tif (status != IXGBE_SUCCESS ||\n\t !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |\n\t IXGBE_MDIO_GLOBAL_ALARM_1_INT)))\n\t\treturn status;\n\n\t/* High temperature failure alarm triggered */\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t ®);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* If high temperature failure, then return over temp error and exit */\n\tif (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {\n\t\t/* power down the PHY in case the PHY FW didn't already */\n\t\tixgbe_set_copper_phy_power(hw, false);\n\t\treturn IXGBE_ERR_OVERTEMP;\n\t}\n\n\t/* Vendor alarm 2 triggered */\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);\n\n\tif (status != IXGBE_SUCCESS ||\n\t !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))\n\t\treturn status;\n\n\t/* link connect/disconnect event occurred */\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Indicate LSC */\n\tif (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)\n\t\t*lsc = true;\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts\n * @hw: pointer to hardware structure\n *\n * Enable link status change and temperature failure alarm for the external\n * Base T PHY\n *\n * Returns PHY access status\n */\nSTATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)\n{\n\tu32 status;\n\tu16 reg;\n\tbool lsc;\n\n\t/* Clear interrupt flags */\n\tstatus = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);\n\n\t/* Enable link status change alarm */\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\treg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;\n\n\tstatus = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Enables high temperature failure alarm */\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t ®);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\treg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN;\n\n\tstatus = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t reg);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t ®);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\treg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |\n\t\tIXGBE_MDIO_GLOBAL_ALARM_1_INT);\n\n\tstatus = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t reg);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Enable chip-wide vendor alarm */\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t ®);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\treg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;\n\n\tstatus = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t reg);\n\n\treturn status;\n}\n\n/**\n * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.\n * @hw: pointer to hardware structure\n * @speed: link speed\n *\n * Configures the integrated KR PHY.\n **/\nSTATIC s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed)\n{\n\ts32 status;\n\tu32 reg_val;\n\n\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\tIXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),\n\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n\tif (status)\n\t\treturn status;\n\n\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;\n\treg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |\n\t\t IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);\n\n\t/* Advertise 10G support. */\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL)\n\t\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;\n\n\t/* Advertise 1G support. */\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL)\n\t\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;\n\n\t/* Restart auto-negotiation. */\n\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;\n\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\tIXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),\n\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n\n\treturn status;\n}\n\n/**\n * ixgbe_init_phy_ops_X550em - PHY/SFP specific init\n * @hw: pointer to hardware structure\n *\n * Initialize any function pointers that were not able to be\n * set during init_shared_code because the PHY/SFP type was\n * not known. Perform the SFP init if necessary.\n */\ns32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\tixgbe_link_speed speed;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"ixgbe_init_phy_ops_X550em\");\n\n\thw->mac.ops.set_lan_id(hw);\n\n\tif (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {\n\t\tphy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;\n\t\tixgbe_setup_mux_ctl(hw);\n\n\t\t/* Save NW management interface connected on board. This is used\n\t\t * to determine internal PHY mode.\n\t\t */\n\t\tphy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);\n\n\t\t/* If internal PHY mode is KR, then initialize KR link */\n\t\tif (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {\n\t\t\tspeed = IXGBE_LINK_SPEED_10GB_FULL |\n\t\t\t\tIXGBE_LINK_SPEED_1GB_FULL;\n\t\t\tret_val = ixgbe_setup_kr_speed_x550em(hw, speed);\n\t\t}\n\n\t\tphy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em;\n\t}\n\n\t/* Identify the PHY or SFP module */\n\tret_val = phy->ops.identify(hw);\n\tif (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)\n\t\treturn ret_val;\n\n\t/* Setup function pointers based on detected hardware */\n\tixgbe_init_mac_link_ops_X550em(hw);\n\tif (phy->sfp_type != ixgbe_sfp_type_unknown)\n\t\tphy->ops.reset = NULL;\n\n\t/* Set functions pointers based on phy type */\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_x550em_kx4:\n\t\tphy->ops.setup_link = ixgbe_setup_kx4_x550em;\n\t\tphy->ops.read_reg = ixgbe_read_phy_reg_x550em;\n\t\tphy->ops.write_reg = ixgbe_write_phy_reg_x550em;\n\t\tbreak;\n\tcase ixgbe_phy_x550em_kr:\n\t\tphy->ops.setup_link = ixgbe_setup_kr_x550em;\n\t\tphy->ops.read_reg = ixgbe_read_phy_reg_x550em;\n\t\tphy->ops.write_reg = ixgbe_write_phy_reg_x550em;\n\t\tbreak;\n\tcase ixgbe_phy_x550em_ext_t:\n\t\t/* Save NW management interface connected on board. This is used\n\t\t * to determine internal PHY mode\n\t\t */\n\t\tphy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);\n\n\t\t/* If internal link mode is XFI, then setup iXFI internal link,\n\t\t * else setup KR now.\n\t\t */\n\t\tif (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {\n\t\t\tphy->ops.setup_internal_link =\n\t\t\t\t\t ixgbe_setup_internal_phy_t_x550em;\n\t\t} else {\n\t\t\tspeed = IXGBE_LINK_SPEED_10GB_FULL |\n\t\t\t\tIXGBE_LINK_SPEED_1GB_FULL;\n\t\t\tret_val = ixgbe_setup_kr_speed_x550em(hw, speed);\n\t\t}\n\n\t\t/* setup SW LPLU only for first revision */\n\t\tif (!(IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw,\n\t\t\t\t\t\t IXGBE_FUSES0_GROUP(0))))\n\t\t\tphy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;\n\n\t\tphy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;\n\t\tphy->ops.reset = ixgbe_reset_phy_t_X550em;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ret_val;\n}\n\n/**\n * ixgbe_reset_hw_X550em - Perform hardware reset\n * @hw: pointer to hardware structure\n *\n * Resets the hardware by resetting the transmit and receive units, masks\n * and clears all interrupts, perform a PHY reset, and perform a link (MAC)\n * reset.\n */\ns32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)\n{\n\tixgbe_link_speed link_speed;\n\ts32 status;\n\tu32 ctrl = 0;\n\tu32 i;\n\tu32 hlreg0;\n\tbool link_up = false;\n\n\tDEBUGFUNC(\"ixgbe_reset_hw_X550em\");\n\n\t/* Call adapter stop to disable Tx/Rx and clear interrupts */\n\tstatus = hw->mac.ops.stop_adapter(hw);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* flush pending Tx transactions */\n\tixgbe_clear_tx_pending(hw);\n\n\t/* PHY ops must be identified and initialized prior to reset */\n\n\t/* Identify PHY and related function pointers */\n\tstatus = hw->phy.ops.init(hw);\n\n\tif (status == IXGBE_ERR_SFP_NOT_SUPPORTED)\n\t\treturn status;\n\n\t/* start the external PHY */\n\tif (hw->phy.type == ixgbe_phy_x550em_ext_t) {\n\t\tstatus = ixgbe_init_ext_t_x550em(hw);\n\t\tif (status)\n\t\t\treturn status;\n\t}\n\n\t/* Setup SFP module if there is one present. */\n\tif (hw->phy.sfp_setup_needed) {\n\t\tstatus = hw->mac.ops.setup_sfp(hw);\n\t\thw->phy.sfp_setup_needed = false;\n\t}\n\n\tif (status == IXGBE_ERR_SFP_NOT_SUPPORTED)\n\t\treturn status;\n\n\t/* Reset PHY */\n\tif (!hw->phy.reset_disable && hw->phy.ops.reset)\n\t\thw->phy.ops.reset(hw);\n\nmac_reset_top:\n\t/* Issue global reset to the MAC. Needs to be SW reset if link is up.\n\t * If link reset is used when link is up, it might reset the PHY when\n\t * mng is using it. If link is down or the flag to force full link\n\t * reset is set, then perform link reset.\n\t */\n\tctrl = IXGBE_CTRL_LNK_RST;\n\tif (!hw->force_full_reset) {\n\t\thw->mac.ops.check_link(hw, &link_speed, &link_up, false);\n\t\tif (link_up)\n\t\t\tctrl = IXGBE_CTRL_RST;\n\t}\n\n\tctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Poll for reset bit to self-clear meaning reset is complete */\n\tfor (i = 0; i < 10; i++) {\n\t\tusec_delay(1);\n\t\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);\n\t\tif (!(ctrl & IXGBE_CTRL_RST_MASK))\n\t\t\tbreak;\n\t}\n\n\tif (ctrl & IXGBE_CTRL_RST_MASK) {\n\t\tstatus = IXGBE_ERR_RESET_FAILED;\n\t\tDEBUGOUT(\"Reset polling failed to complete.\\n\");\n\t}\n\n\tmsec_delay(50);\n\n\t/* Double resets are required for recovery from certain error\n\t * conditions. Between resets, it is necessary to stall to\n\t * allow time for any pending HW events to complete.\n\t */\n\tif (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {\n\t\thw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;\n\t\tgoto mac_reset_top;\n\t}\n\n\t/* Store the permanent mac address */\n\thw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);\n\n\t/* Store MAC address from RAR0, clear receive address registers, and\n\t * clear the multicast table. Also reset num_rar_entries to 128,\n\t * since we modify this value when programming the SAN MAC address.\n\t */\n\thw->mac.num_rar_entries = 128;\n\thw->mac.ops.init_rx_addrs(hw);\n\n\tif (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {\n\t\t/* Config MDIO clock speed. */\n\t\thlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);\n\t\thlreg0 &= ~IXGBE_HLREG0_MDCSPD;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);\n\t}\n\n\tif (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)\n\t\tixgbe_setup_mux_ctl(hw);\n\n\treturn status;\n}\n\n/**\n * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.\n * @hw: pointer to hardware structure\n */\ns32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)\n{\n\tu32 status;\n\tu16 reg;\n\n\tstatus = hw->phy.ops.read_reg(hw,\n\t\t\t\t IXGBE_MDIO_TX_VENDOR_ALARMS_3,\n\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t ®);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* If PHY FW reset completed bit is set then this is the first\n\t * SW instance after a power on so the PHY FW must be un-stalled.\n\t */\n\tif (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {\n\t\tstatus = hw->phy.ops.read_reg(hw,\n\t\t\t\t\tIXGBE_MDIO_GLOBAL_RES_PR_10,\n\t\t\t\t\tIXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t\t®);\n\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\treg &= ~IXGBE_MDIO_POWER_UP_STALL;\n\n\t\tstatus = hw->phy.ops.write_reg(hw,\n\t\t\t\t\tIXGBE_MDIO_GLOBAL_RES_PR_10,\n\t\t\t\t\tIXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t\treg);\n\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_setup_kr_x550em - Configure the KR PHY.\n * @hw: pointer to hardware structure\n *\n * Configures the integrated KR PHY.\n **/\ns32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);\n}\n\n/**\n * ixgbe_setup_kx4_x550em - Configure the KX4 PHY.\n * @hw: pointer to hardware structure\n *\n * Configures the integrated KX4 PHY.\n **/\ns32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\tu32 reg_val;\n\n\tstatus = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,\n\t\tIXGBE_SB_IOSF_TARGET_KX4_PCS, ®_val);\n\tif (status)\n\t\treturn status;\n\n\treg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |\n\t\t\tIXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);\n\n\treg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;\n\n\t/* Advertise 10G support. */\n\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)\n\t\treg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;\n\n\t/* Advertise 1G support. */\n\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)\n\t\treg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;\n\n\t/* Restart auto-negotiation. */\n\treg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;\n\tstatus = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1,\n\t\tIXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val);\n\n\treturn status;\n}\n\n/**\n * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP\n * @hw: pointer to hardware structure\n *\n * Configure the external PHY and the integrated KR PHY for SFP support.\n **/\ns32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg_wait_to_complete)\n{\n\ts32 ret_val;\n\tu16 reg_slice, reg_val;\n\tbool setup_linear = false;\n\tUNREFERENCED_1PARAMETER(autoneg_wait_to_complete);\n\n\t/* Check if SFP module is supported and linear */\n\tret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);\n\n\t/* If no SFP module present, then return success. Return success since\n\t * there is no reason to configure CS4227 and SFP not present error is\n\t * not excepted in the setup MAC link flow.\n\t */\n\tif (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)\n\t\treturn IXGBE_SUCCESS;\n\n\tif (ret_val != IXGBE_SUCCESS)\n\t\treturn ret_val;\n\n\t/* Configure CS4227 LINE side to 10G SR. */\n\treg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);\n\treg_val = IXGBE_CS4227_SPEED_10G;\n\tret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,\n\t\treg_val);\n\n\treg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);\n\treg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;\n\tret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,\n\t\treg_val);\n\n\t/* Configure CS4227 for HOST connection rate then type. */\n\treg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);\n\treg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ?\n\t\tIXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;\n\tret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,\n\t\t\t\t\t reg_val);\n\n\treg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);\n\tif (setup_linear)\n\t\treg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;\n\telse\n\t\treg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;\n\tret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice,\n\t\t\t\t\t reg_val);\n\n\t/* If internal link mode is XFI, then setup XFI internal link. */\n\tif (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))\n\t\tret_val = ixgbe_setup_ixfi_x550em(hw, &speed);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.\n * @hw: pointer to hardware structure\n * @speed: the link speed to force\n *\n * Configures the integrated KR PHY to use iXFI mode. Used to connect an\n * internal and external PHY at a specific speed, without autonegotiation.\n **/\nSTATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)\n{\n\ts32 status;\n\tu32 reg_val;\n\n\t/* Disable AN and force speed to 10G Serial. */\n\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),\n\t\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\treg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;\n\treg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;\n\n\t/* Select forced link speed for internal PHY. */\n\tswitch (*speed) {\n\tcase IXGBE_LINK_SPEED_10GB_FULL:\n\t\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;\n\t\tbreak;\n\tcase IXGBE_LINK_SPEED_1GB_FULL:\n\t\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;\n\t\tbreak;\n\tdefault:\n\t\t/* Other link speeds are not supported by internal KR PHY. */\n\t\treturn IXGBE_ERR_LINK_SETUP;\n\t}\n\n\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),\n\t\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Disable training protocol FSM. */\n\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\t\t\tIXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;\n\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\t\t\tIXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Disable Flex from training TXFFE. */\n\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\t\t\tIXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;\n\treg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;\n\treg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;\n\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\t\t\tIXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\t\t\tIXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;\n\treg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;\n\treg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;\n\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\t\t\tIXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Enable override for coefficients. */\n\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\t\t\tIXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;\n\treg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;\n\treg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;\n\treg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;\n\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\t\t\tIXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),\n\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Toggle port SW reset by AN reset. */\n\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),\n\t\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;\n\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\t\t\t\tIXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),\n\t\t\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n\n\treturn status;\n}\n\n/**\n * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status\n * @hw: address of hardware structure\n * @link_up: address of boolean to indicate link status\n *\n * Returns error code if unable to get link status.\n */\nSTATIC s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)\n{\n\tu32 ret;\n\tu16 autoneg_status;\n\n\t*link_up = false;\n\n\t/* read this twice back to back to indicate current status */\n\tret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_status);\n\tif (ret != IXGBE_SUCCESS)\n\t\treturn ret;\n\n\tret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_status);\n\tif (ret != IXGBE_SUCCESS)\n\t\treturn ret;\n\n\t*link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link\n * @hw: point to hardware structure\n *\n * Configures the link between the integrated KR PHY and the external X557 PHY\n * The driver will call this function when it gets a link status change\n * interrupt from the X557 PHY. This function configures the link speed\n * between the PHYs to match the link speed of the BASE-T link.\n *\n * A return of a non-zero value indicates an error, and the base driver should\n * not report link up.\n */\ns32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)\n{\n\tixgbe_link_speed force_speed;\n\tbool link_up;\n\tu32 status;\n\tu16 speed;\n\n\tif (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)\n\t\treturn IXGBE_ERR_CONFIG;\n\n\t/* If link is not up, then there is no setup necessary so return */\n\tstatus = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tif (!link_up)\n\t\treturn IXGBE_SUCCESS;\n\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &speed);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* If link is not still up, then no setup is necessary so return */\n\tstatus = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\tif (!link_up)\n\t\treturn IXGBE_SUCCESS;\n\n\t/* clear everything but the speed and duplex bits */\n\tspeed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;\n\n\tswitch (speed) {\n\tcase IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:\n\t\tforce_speed = IXGBE_LINK_SPEED_10GB_FULL;\n\t\tbreak;\n\tcase IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:\n\t\tforce_speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\tbreak;\n\tdefault:\n\t\t/* Internal PHY does not support anything else */\n\t\treturn IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t}\n\n\treturn ixgbe_setup_ixfi_x550em(hw, &force_speed);\n}\n\n/**\n * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback.\n * @hw: pointer to hardware structure\n *\n * Configures the integrated KR PHY to use internal loopback mode.\n **/\ns32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\tu32 reg_val;\n\n\t/* Disable AN and force speed to 10G Serial. */\n\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\tIXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),\n\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;\n\treg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;\n\treg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;\n\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\tIXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),\n\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Set near-end loopback clocks. */\n\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\tIXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),\n\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B;\n\treg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS;\n\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\tIXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id),\n\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Set loopback enable. */\n\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\tIXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),\n\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK;\n\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\tIXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id),\n\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Training bypass. */\n\tstatus = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\tIXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),\n\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\treg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS;\n\tstatus = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\tIXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),\n\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n\n\treturn status;\n}\n\n/**\n * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command\n * assuming that the semaphore is already obtained.\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM using the hostif.\n **/\ns32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 *data)\n{\n\ts32 status;\n\tstruct ixgbe_hic_read_shadow_ram buffer;\n\n\tDEBUGFUNC(\"ixgbe_read_ee_hostif_data_X550\");\n\tbuffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;\n\tbuffer.hdr.req.buf_lenh = 0;\n\tbuffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;\n\tbuffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;\n\n\t/* convert offset from words to bytes */\n\tbuffer.address = IXGBE_CPU_TO_BE32(offset * 2);\n\t/* one word */\n\tbuffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));\n\n\tstatus = ixgbe_host_interface_command(hw, (u32 *)&buffer,\n\t\t\t\t\t sizeof(buffer),\n\t\t\t\t\t IXGBE_HI_COMMAND_TIMEOUT, false);\n\n\tif (status)\n\t\treturn status;\n\n\t*data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,\n\t\t\t\t\t FW_NVM_DATA_OFFSET);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM using the hostif.\n **/\ns32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,\n\t\t\t u16 *data)\n{\n\ts32 status = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_read_ee_hostif_X550\");\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n\t IXGBE_SUCCESS) {\n\t\tstatus = ixgbe_read_ee_hostif_data_X550(hw, offset, data);\n\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\t} else {\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @words: number of words\n * @data: word(s) read from the EEPROM\n *\n * Reads a 16 bit word(s) from the EEPROM using the hostif.\n **/\ns32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,\n\t\t\t\t u16 offset, u16 words, u16 *data)\n{\n\tstruct ixgbe_hic_read_shadow_ram buffer;\n\tu32 current_word = 0;\n\tu16 words_to_read;\n\ts32 status;\n\tu32 i;\n\n\tDEBUGFUNC(\"ixgbe_read_ee_hostif_buffer_X550\");\n\n\t/* Take semaphore for the entire operation. */\n\tstatus = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\tif (status) {\n\t\tDEBUGOUT(\"EEPROM read buffer - semaphore failed\\n\");\n\t\treturn status;\n\t}\n\twhile (words) {\n\t\tif (words > FW_MAX_READ_BUFFER_SIZE / 2)\n\t\t\twords_to_read = FW_MAX_READ_BUFFER_SIZE / 2;\n\t\telse\n\t\t\twords_to_read = words;\n\n\t\tbuffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;\n\t\tbuffer.hdr.req.buf_lenh = 0;\n\t\tbuffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;\n\t\tbuffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;\n\n\t\t/* convert offset from words to bytes */\n\t\tbuffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2);\n\t\tbuffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2);\n\n\t\tstatus = ixgbe_host_interface_command(hw, (u32 *)&buffer,\n\t\t\t\t\t\t sizeof(buffer),\n\t\t\t\t\t\t IXGBE_HI_COMMAND_TIMEOUT,\n\t\t\t\t\t\t false);\n\n\t\tif (status) {\n\t\t\tDEBUGOUT(\"Host interface command failed\\n\");\n\t\t\tgoto out;\n\t\t}\n\n\t\tfor (i = 0; i < words_to_read; i++) {\n\t\t\tu32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +\n\t\t\t\t 2 * i;\n\t\t\tu32 value = IXGBE_READ_REG(hw, reg);\n\n\t\t\tdata[current_word] = (u16)(value & 0xffff);\n\t\t\tcurrent_word++;\n\t\t\ti++;\n\t\t\tif (i < words_to_read) {\n\t\t\t\tvalue >>= 16;\n\t\t\t\tdata[current_word] = (u16)(value & 0xffff);\n\t\t\t\tcurrent_word++;\n\t\t\t}\n\t\t}\n\t\twords -= words_to_read;\n\t}\n\nout:\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\treturn status;\n}\n\n/**\n * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to write\n * @data: word write to the EEPROM\n *\n * Write a 16 bit word to the EEPROM using the hostif.\n **/\ns32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 data)\n{\n\ts32 status;\n\tstruct ixgbe_hic_write_shadow_ram buffer;\n\n\tDEBUGFUNC(\"ixgbe_write_ee_hostif_data_X550\");\n\n\tbuffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;\n\tbuffer.hdr.req.buf_lenh = 0;\n\tbuffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;\n\tbuffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;\n\n\t /* one word */\n\tbuffer.length = IXGBE_CPU_TO_BE16(sizeof(u16));\n\tbuffer.data = data;\n\tbuffer.address = IXGBE_CPU_TO_BE32(offset * 2);\n\n\tstatus = ixgbe_host_interface_command(hw, (u32 *)&buffer,\n\t\t\t\t\t sizeof(buffer),\n\t\t\t\t\t IXGBE_HI_COMMAND_TIMEOUT, false);\n\n\treturn status;\n}\n\n/**\n * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to write\n * @data: word write to the EEPROM\n *\n * Write a 16 bit word to the EEPROM using the hostif.\n **/\ns32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,\n\t\t\t u16 data)\n{\n\ts32 status = IXGBE_SUCCESS;\n\n\tDEBUGFUNC(\"ixgbe_write_ee_hostif_X550\");\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n\t IXGBE_SUCCESS) {\n\t\tstatus = ixgbe_write_ee_hostif_data_X550(hw, offset, data);\n\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\t} else {\n\t\tDEBUGOUT(\"write ee hostif failed to get semaphore\");\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to write\n * @words: number of words\n * @data: word(s) write to the EEPROM\n *\n * Write a 16 bit word(s) to the EEPROM using the hostif.\n **/\ns32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,\n\t\t\t\t u16 offset, u16 words, u16 *data)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tu32 i = 0;\n\n\tDEBUGFUNC(\"ixgbe_write_ee_hostif_buffer_X550\");\n\n\t/* Take semaphore for the entire operation. */\n\tstatus = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\tif (status != IXGBE_SUCCESS) {\n\t\tDEBUGOUT(\"EEPROM write buffer - semaphore failed\\n\");\n\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < words; i++) {\n\t\tstatus = ixgbe_write_ee_hostif_data_X550(hw, offset + i,\n\t\t\t\t\t\t\t data[i]);\n\n\t\tif (status != IXGBE_SUCCESS) {\n\t\t\tDEBUGOUT(\"Eeprom buffered write failed\\n\");\n\t\t\tbreak;\n\t\t}\n\t}\n\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\nout:\n\n\treturn status;\n}\n\n/**\n * ixgbe_checksum_ptr_x550 - Checksum one pointer region\n * @hw: pointer to hardware structure\n * @ptr: pointer offset in eeprom\n * @size: size of section pointed by ptr, if 0 first word will be used as size\n * @csum: address of checksum to update\n *\n * Returns error status for any failure\n */\nSTATIC s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,\n\t\t\t\t u16 size, u16 *csum, u16 *buffer,\n\t\t\t\t u32 buffer_size)\n{\n\tu16 buf[256];\n\ts32 status;\n\tu16 length, bufsz, i, start;\n\tu16 *local_buffer;\n\n\tbufsz = sizeof(buf) / sizeof(buf[0]);\n\n\t/* Read a chunk at the pointer location */\n\tif (!buffer) {\n\t\tstatus = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);\n\t\tif (status) {\n\t\t\tDEBUGOUT(\"Failed to read EEPROM image\\n\");\n\t\t\treturn status;\n\t\t}\n\t\tlocal_buffer = buf;\n\t} else {\n\t\tif (buffer_size < ptr)\n\t\t\treturn IXGBE_ERR_PARAM;\n\t\tlocal_buffer = &buffer[ptr];\n\t}\n\n\tif (size) {\n\t\tstart = 0;\n\t\tlength = size;\n\t} else {\n\t\tstart = 1;\n\t\tlength = local_buffer[0];\n\n\t\t/* Skip pointer section if length is invalid. */\n\t\tif (length == 0xFFFF || length == 0 ||\n\t\t (ptr + length) >= hw->eeprom.word_size)\n\t\t\treturn IXGBE_SUCCESS;\n\t}\n\n\tif (buffer && ((u32)start + (u32)length > buffer_size))\n\t\treturn IXGBE_ERR_PARAM;\n\n\tfor (i = start; length; i++, length--) {\n\t\tif (i == bufsz && !buffer) {\n\t\t\tptr += bufsz;\n\t\t\ti = 0;\n\t\t\tif (length < bufsz)\n\t\t\t\tbufsz = length;\n\n\t\t\t/* Read a chunk at the pointer location */\n\t\t\tstatus = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,\n\t\t\t\t\t\t\t\t bufsz, buf);\n\t\t\tif (status) {\n\t\t\t\tDEBUGOUT(\"Failed to read EEPROM image\\n\");\n\t\t\t\treturn status;\n\t\t\t}\n\t\t}\n\t\t*csum += local_buffer[i];\n\t}\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_calc_checksum_X550 - Calculates and returns the checksum\n * @hw: pointer to hardware structure\n * @buffer: pointer to buffer containing calculated checksum\n * @buffer_size: size of buffer\n *\n * Returns a negative error code on error, or the 16-bit checksum\n **/\ns32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size)\n{\n\tu16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];\n\tu16 *local_buffer;\n\ts32 status;\n\tu16 checksum = 0;\n\tu16 pointer, i, size;\n\n\tDEBUGFUNC(\"ixgbe_calc_eeprom_checksum_X550\");\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (!buffer) {\n\t\t/* Read pointer area */\n\t\tstatus = ixgbe_read_ee_hostif_buffer_X550(hw, 0,\n\t\t\t\t\t\t IXGBE_EEPROM_LAST_WORD + 1,\n\t\t\t\t\t\t eeprom_ptrs);\n\t\tif (status) {\n\t\t\tDEBUGOUT(\"Failed to read EEPROM image\\n\");\n\t\t\treturn status;\n\t\t}\n\t\tlocal_buffer = eeprom_ptrs;\n\t} else {\n\t\tif (buffer_size < IXGBE_EEPROM_LAST_WORD)\n\t\t\treturn IXGBE_ERR_PARAM;\n\t\tlocal_buffer = buffer;\n\t}\n\n\t/*\n\t * For X550 hardware include 0x0-0x41 in the checksum, skip the\n\t * checksum word itself\n\t */\n\tfor (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)\n\t\tif (i != IXGBE_EEPROM_CHECKSUM)\n\t\t\tchecksum += local_buffer[i];\n\n\t/*\n\t * Include all data from pointers 0x3, 0x6-0xE. This excludes the\n\t * FW, PHY module, and PCIe Expansion/Option ROM pointers.\n\t */\n\tfor (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {\n\t\tif (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)\n\t\t\tcontinue;\n\n\t\tpointer = local_buffer[i];\n\n\t\t/* Skip pointer section if the pointer is invalid. */\n\t\tif (pointer == 0xFFFF || pointer == 0 ||\n\t\t pointer >= hw->eeprom.word_size)\n\t\t\tcontinue;\n\n\t\tswitch (i) {\n\t\tcase IXGBE_PCIE_GENERAL_PTR:\n\t\t\tsize = IXGBE_IXGBE_PCIE_GENERAL_SIZE;\n\t\t\tbreak;\n\t\tcase IXGBE_PCIE_CONFIG0_PTR:\n\t\tcase IXGBE_PCIE_CONFIG1_PTR:\n\t\t\tsize = IXGBE_PCIE_CONFIG_SIZE;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tsize = 0;\n\t\t\tbreak;\n\t\t}\n\n\t\tstatus = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,\n\t\t\t\t\t\tbuffer, buffer_size);\n\t\tif (status)\n\t\t\treturn status;\n\t}\n\n\tchecksum = (u16)IXGBE_EEPROM_SUM - checksum;\n\n\treturn (s32)checksum;\n}\n\n/**\n * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum\n * @hw: pointer to hardware structure\n *\n * Returns a negative error code on error, or the 16-bit checksum\n **/\ns32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_calc_checksum_X550(hw, NULL, 0);\n}\n\n/**\n * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum\n * @hw: pointer to hardware structure\n * @checksum_val: calculated checksum\n *\n * Performs checksum calculation and validates the EEPROM checksum. If the\n * caller does not need checksum_val, the value can be NULL.\n **/\ns32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val)\n{\n\ts32 status;\n\tu16 checksum;\n\tu16 read_checksum = 0;\n\n\tDEBUGFUNC(\"ixgbe_validate_eeprom_checksum_X550\");\n\n\t/* Read the first word from the EEPROM. If this times out or fails, do\n\t * not continue or we could be in for a very long wait while every\n\t * EEPROM read fails\n\t */\n\tstatus = hw->eeprom.ops.read(hw, 0, &checksum);\n\tif (status) {\n\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = hw->eeprom.ops.calc_checksum(hw);\n\tif (status < 0)\n\t\treturn status;\n\n\tchecksum = (u16)(status & 0xffff);\n\n\tstatus = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,\n\t\t\t\t\t &read_checksum);\n\tif (status)\n\t\treturn status;\n\n\t/* Verify read checksum from EEPROM is the same as\n\t * calculated checksum\n\t */\n\tif (read_checksum != checksum) {\n\t\tstatus = IXGBE_ERR_EEPROM_CHECKSUM;\n\t\tERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,\n\t\t\t \"Invalid EEPROM checksum\");\n\t}\n\n\t/* If the user cares, return the calculated checksum */\n\tif (checksum_val)\n\t\t*checksum_val = checksum;\n\n\treturn status;\n}\n\n/**\n * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash\n * @hw: pointer to hardware structure\n *\n * After writing EEPROM to shadow RAM using EEWR register, software calculates\n * checksum and updates the EEPROM and instructs the hardware to update\n * the flash.\n **/\ns32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\tu16 checksum = 0;\n\n\tDEBUGFUNC(\"ixgbe_update_eeprom_checksum_X550\");\n\n\t/* Read the first word from the EEPROM. If this times out or fails, do\n\t * not continue or we could be in for a very long wait while every\n\t * EEPROM read fails\n\t */\n\tstatus = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);\n\tif (status) {\n\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\treturn status;\n\t}\n\n\tstatus = ixgbe_calc_eeprom_checksum_X550(hw);\n\tif (status < 0)\n\t\treturn status;\n\n\tchecksum = (u16)(status & 0xffff);\n\n\tstatus = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,\n\t\t\t\t\t checksum);\n\tif (status)\n\t\treturn status;\n\n\tstatus = ixgbe_update_flash_X550(hw);\n\n\treturn status;\n}\n\n/**\n * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device\n * @hw: pointer to hardware structure\n *\n * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.\n **/\ns32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tunion ixgbe_hic_hdr2 buffer;\n\n\tDEBUGFUNC(\"ixgbe_update_flash_X550\");\n\n\tbuffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;\n\tbuffer.req.buf_lenh = 0;\n\tbuffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;\n\tbuffer.req.checksum = FW_DEFAULT_CHECKSUM;\n\n\tstatus = ixgbe_host_interface_command(hw, (u32 *)&buffer,\n\t\t\t\t\t sizeof(buffer),\n\t\t\t\t\t IXGBE_HI_COMMAND_TIMEOUT, false);\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type\n * @hw: pointer to hardware structure\n *\n * Determines physical layer capabilities of the current configuration.\n **/\nu32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw)\n{\n\tu32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n\tu16 ext_ability = 0;\n\n\tDEBUGFUNC(\"ixgbe_get_supported_physical_layer_X550em\");\n\n\thw->phy.ops.identify(hw);\n\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_x550em_kr:\n\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR |\n\t\t\t\t IXGBE_PHYSICAL_LAYER_1000BASE_KX;\n\t\tbreak;\n\tcase ixgbe_phy_x550em_kx4:\n\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |\n\t\t\t\t IXGBE_PHYSICAL_LAYER_1000BASE_KX;\n\t\tbreak;\n\tcase ixgbe_phy_x550em_ext_t:\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,\n\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t &ext_ability);\n\t\tif (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;\n\t\tif (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber)\n\t\tphysical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);\n\n\treturn physical_layer;\n}\n\n/**\n * ixgbe_get_bus_info_x550em - Set PCI bus info\n * @hw: pointer to hardware structure\n *\n * Sets bus link width and speed to unknown because X550em is\n * not a PCI device.\n **/\ns32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)\n{\n\n\tDEBUGFUNC(\"ixgbe_get_bus_info_x550em\");\n\n\thw->bus.width = ixgbe_bus_width_unknown;\n\thw->bus.speed = ixgbe_bus_speed_unknown;\n\n\thw->mac.ops.set_lan_id(hw);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_disable_rx_x550 - Disable RX unit\n *\n * Enables the Rx DMA unit for x550\n **/\nvoid ixgbe_disable_rx_x550(struct ixgbe_hw *hw)\n{\n\tu32 rxctrl, pfdtxgswc;\n\ts32 status;\n\tstruct ixgbe_hic_disable_rxen fw_cmd;\n\n\tDEBUGFUNC(\"ixgbe_enable_rx_dma_x550\");\n\n\trxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n\tif (rxctrl & IXGBE_RXCTRL_RXEN) {\n\t\tpfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);\n\t\tif (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {\n\t\t\tpfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);\n\t\t\thw->mac.set_lben = true;\n\t\t} else {\n\t\t\thw->mac.set_lben = false;\n\t\t}\n\n\t\tfw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;\n\t\tfw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;\n\t\tfw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;\n\t\tfw_cmd.port_number = (u8)hw->bus.lan_id;\n\n\t\tstatus = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,\n\t\t\t\t\tsizeof(struct ixgbe_hic_disable_rxen),\n\t\t\t\t\tIXGBE_HI_COMMAND_TIMEOUT, true);\n\n\t\t/* If we fail - disable RX using register write */\n\t\tif (status) {\n\t\t\trxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n\t\t\tif (rxctrl & IXGBE_RXCTRL_RXEN) {\n\t\t\t\trxctrl &= ~IXGBE_RXCTRL_RXEN;\n\t\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);\n\t\t\t}\n\t\t}\n\t}\n}\n\n/**\n * ixgbe_enter_lplu_x550em - Transition to low power states\n * @hw: pointer to hardware structure\n *\n * Configures Low Power Link Up on transition to low power states\n * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the\n * X557 PHY immediately prior to entering LPLU.\n **/\ns32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)\n{\n\tu16 an_10g_cntl_reg, autoneg_reg, speed;\n\ts32 status;\n\tixgbe_link_speed lcd_speed;\n\tu32 save_autoneg;\n\tbool link_up;\n\n\t/* SW LPLU not required on later HW revisions. */\n\tif (IXGBE_FUSES0_REV1 & IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)))\n\t\treturn IXGBE_SUCCESS;\n\n\t/* If blocked by MNG FW, then don't restart AN */\n\tif (ixgbe_check_reset_blocked(hw))\n\t\treturn IXGBE_SUCCESS;\n\n\tstatus = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tstatus = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* If link is down, LPLU disabled in NVM, WoL disabled, or manageability\n\t * disabled, then force link down by entering low power mode.\n\t */\n\tif (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||\n\t !(hw->wol_enabled || ixgbe_mng_present(hw)))\n\t\treturn ixgbe_set_copper_phy_power(hw, FALSE);\n\n\t/* Determine LCD */\n\tstatus = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* If no valid LCD link speed, then force link down and exit. */\n\tif (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)\n\t\treturn ixgbe_set_copper_phy_power(hw, FALSE);\n\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &speed);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* If no link now, speed is invalid so take link down */\n\tstatus = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn ixgbe_set_copper_phy_power(hw, false);\n\n\t/* clear everything but the speed bits */\n\tspeed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;\n\n\t/* If current speed is already LCD, then exit. */\n\tif (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&\n\t (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||\n\t ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&\n\t (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))\n\t\treturn status;\n\n\t/* Clear AN completed indication */\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t &an_10g_cntl_reg);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tstatus = hw->phy.ops.read_reg(hw,\n\t\t\t IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t &autoneg_reg);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tsave_autoneg = hw->phy.autoneg_advertised;\n\n\t/* Setup link at least common link speed */\n\tstatus = hw->mac.ops.setup_link(hw, lcd_speed, false);\n\n\t/* restore autoneg from before setting lplu speed */\n\thw->phy.autoneg_advertised = save_autoneg;\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_lcd_x550em - Determine lowest common denominator\n * @hw: pointer to hardware structure\n * @lcd_speed: pointer to lowest common link speed\n *\n * Determine lowest common link speed with link partner.\n **/\ns32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed)\n{\n\tu16 an_lp_status;\n\ts32 status;\n\tu16 word = hw->eeprom.ctrl_word_3;\n\n\t*lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;\n\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &an_lp_status);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* If link partner advertised 1G, return 1G */\n\tif (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {\n\t\t*lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\treturn status;\n\t}\n\n\t/* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */\n\tif ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||\n\t (word & NVM_INIT_CTRL_3_D10GMP_PORT0))\n\t\treturn status;\n\n\t/* Link partner not capable of lower speeds, return 10G */\n\t*lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;\n\treturn status;\n}\n\n/**\n * ixgbe_setup_fc_X550em - Set up flow control\n * @hw: pointer to hardware structure\n *\n * Called at init time to set up flow control.\n **/\ns32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = IXGBE_SUCCESS;\n\tu32 pause, asm_dir, reg_val;\n\n\tDEBUGFUNC(\"ixgbe_setup_fc_X550em\");\n\n\t/* Validate the requested mode */\n\tif (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {\n\t\tERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,\n\t\t\t\"ixgbe_fc_rx_pause not valid in strict IEEE mode\\n\");\n\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\tgoto out;\n\t}\n\n\t/* 10gig parts do not have a word in the EEPROM to determine the\n\t * default flow control setting, so we explicitly set it to full.\n\t */\n\tif (hw->fc.requested_mode == ixgbe_fc_default)\n\t\thw->fc.requested_mode = ixgbe_fc_full;\n\n\t/* Determine PAUSE and ASM_DIR bits. */\n\tswitch (hw->fc.requested_mode) {\n\tcase ixgbe_fc_none:\n\t\tpause = 0;\n\t\tasm_dir = 0;\n\t\tbreak;\n\tcase ixgbe_fc_tx_pause:\n\t\tpause = 0;\n\t\tasm_dir = 1;\n\t\tbreak;\n\tcase ixgbe_fc_rx_pause:\n\t\t/* Rx Flow control is enabled and Tx Flow control is\n\t\t * disabled by software override. Since there really\n\t\t * isn't a way to advertise that we are capable of RX\n\t\t * Pause ONLY, we will advertise that we support both\n\t\t * symmetric and asymmetric Rx PAUSE, as such we fall\n\t\t * through to the fc_full statement. Later, we will\n\t\t * disable the adapter's ability to send PAUSE frames.\n\t\t */\n\tcase ixgbe_fc_full:\n\t\tpause = 1;\n\t\tasm_dir = 1;\n\t\tbreak;\n\tdefault:\n\t\tERROR_REPORT1(IXGBE_ERROR_ARGUMENT,\n\t\t\t\"Flow control param set incorrectly\\n\");\n\t\tret_val = IXGBE_ERR_CONFIG;\n\t\tgoto out;\n\t}\n\n\tif (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) {\n\t\tret_val = ixgbe_read_iosf_sb_reg_x550(hw,\n\t\t\tIXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),\n\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);\n\t\tif (ret_val != IXGBE_SUCCESS)\n\t\t\tgoto out;\n\t\treg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |\n\t\t\tIXGBE_KRM_AN_CNTL_1_ASM_PAUSE);\n\t\tif (pause)\n\t\t\treg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;\n\t\tif (asm_dir)\n\t\t\treg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;\n\t\tret_val = ixgbe_write_iosf_sb_reg_x550(hw,\n\t\t\tIXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),\n\t\t\tIXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);\n\n\t\t/* This device does not fully support AN. */\n\t\thw->fc.disable_fc_autoneg = true;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_set_mux - Set mux for port 1 access with CS4227\n * @hw: pointer to hardware structure\n * @state: set mux if 1, clear if 0\n */\nSTATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)\n{\n\tu32 esdp;\n\n\tif (!hw->bus.lan_id)\n\t\treturn;\n\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\tif (state)\n\t\tesdp |= IXGBE_ESDP_SDP1;\n\telse\n\t\tesdp &= ~IXGBE_ESDP_SDP1;\n\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/**\n * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to acquire\n *\n * Acquires the SWFW semaphore and sets the I2C MUX\n **/\ns32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)\n{\n\ts32 status;\n\n\tDEBUGFUNC(\"ixgbe_acquire_swfw_sync_X550em\");\n\n\tstatus = ixgbe_acquire_swfw_sync_X540(hw, mask);\n\tif (status)\n\t\treturn status;\n\n\tif (mask & IXGBE_GSSR_I2C_MASK)\n\t\tixgbe_set_mux(hw, 1);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to release\n *\n * Releases the SWFW semaphore and sets the I2C MUX\n **/\nvoid ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)\n{\n\tDEBUGFUNC(\"ixgbe_release_swfw_sync_X550em\");\n\n\tif (mask & IXGBE_GSSR_I2C_MASK)\n\t\tixgbe_set_mux(hw, 0);\n\n\tixgbe_release_swfw_sync_X540(hw, mask);\n}\n\n/**\n * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt\n * @hw: pointer to hardware structure\n *\n * Handle external Base T PHY interrupt. If high temperature\n * failure alarm then return error, else if link status change\n * then setup internal/external PHY link\n *\n * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature\n * failure alarm, else return PHY access status.\n */\ns32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)\n{\n\tbool lsc;\n\tu32 status;\n\n\tstatus = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tif (lsc)\n\t\treturn ixgbe_setup_internal_phy(hw);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Setup internal/external PHY link speed based on link speed, then set\n * external PHY auto advertised link speed.\n *\n * Returns error status for any failure\n **/\ns32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg_wait_to_complete)\n{\n\ts32 status;\n\tixgbe_link_speed force_speed;\n\n\tDEBUGFUNC(\"ixgbe_setup_mac_link_t_X550em\");\n\n\t/* Setup internal/external PHY link speed to iXFI (10G), unless\n\t * only 1G is auto advertised then setup KX link.\n\t */\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL)\n\t\tforce_speed = IXGBE_LINK_SPEED_10GB_FULL;\n\telse\n\t\tforce_speed = IXGBE_LINK_SPEED_1GB_FULL;\n\n\t/* If internal link mode is XFI, then setup XFI internal link. */\n\tif (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {\n\t\tstatus = ixgbe_setup_ixfi_x550em(hw, &force_speed);\n\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\t}\n\n\treturn hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);\n}\n\n/**\n * ixgbe_check_link_t_X550em - Determine link and speed status\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @link_up: true when link is up\n * @link_up_wait_to_complete: bool used to wait for link up or not\n *\n * Check that both the MAC and X557 external PHY have link.\n **/\ns32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t bool *link_up, bool link_up_wait_to_complete)\n{\n\tu32 status;\n\tu16 autoneg_status;\n\n\tif (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)\n\t\treturn IXGBE_ERR_CONFIG;\n\n\tstatus = ixgbe_check_mac_link_generic(hw, speed, link_up,\n\t\t\t\t\t link_up_wait_to_complete);\n\n\t/* If check link fails or MAC link is not up, then return */\n\tif (status != IXGBE_SUCCESS || !(*link_up))\n\t\treturn status;\n\n\t/* MAC link is up, so check external PHY link.\n\t * Read this twice back to back to indicate current status.\n\t */\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_status);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_status);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* If external PHY link is not up, then indicate link not up */\n\tif (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))\n\t\t*link_up = false;\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\n\tstatus = ixgbe_reset_phy_generic(hw);\n\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\t/* Configure Link Status Alarm and Temperature Threshold interrupts */\n\treturn ixgbe_enable_lasi_ext_t_x550em(hw);\n}\n\n/**\n * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs.\n * @hw: pointer to hardware structure\n * @led_idx: led number to turn on\n **/\ns32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx)\n{\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"ixgbe_led_on_t_X550em\");\n\n\tif (led_idx >= IXGBE_X557_MAX_LED_INDEX)\n\t\treturn IXGBE_ERR_PARAM;\n\n\t/* To turn on the LED, set mode to ON. */\n\tixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,\n\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);\n\tphy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;\n\tixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,\n\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);\n\n\treturn IXGBE_SUCCESS;\n}\n\n/**\n * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs.\n * @hw: pointer to hardware structure\n * @led_idx: led number to turn off\n **/\ns32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx)\n{\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"ixgbe_led_off_t_X550em\");\n\n\tif (led_idx >= IXGBE_X557_MAX_LED_INDEX)\n\t\treturn IXGBE_ERR_PARAM;\n\n\t/* To turn on the LED, set mode to ON. */\n\tixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,\n\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);\n\tphy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;\n\tixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,\n\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);\n\n\treturn IXGBE_SUCCESS;\n}\n" }, { "path": "drivers/net/ixgbe/base/ixgbe_x550.h", "content": "/*******************************************************************************\n\nCopyright (c) 2001-2015, Intel Corporation\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n 1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n 2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n 3. Neither the name of the Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n\n***************************************************************************/\n\n#ifndef _IXGBE_X550_H_\n#define _IXGBE_X550_H_\n\n#include \"ixgbe_type.h\"\n\ns32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw);\ns32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw);\ns32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw);\n\ns32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw);\ns32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw);\ns32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw);\ns32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw);\ns32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size);\ns32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val);\ns32 ixgbe_update_flash_X550(struct ixgbe_hw *hw);\ns32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,\n\t\t\t\t u16 offset, u16 words, u16 *data);\ns32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,\n\t\t\t u16 data);\ns32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,\n\t\t\t\t u16 offset, u16 words, u16 *data);\ns32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset,\nu16\t\t\t\t*data);\ns32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 *data);\ns32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 data);\ns32 ixgbe_set_eee_X550(struct ixgbe_hw *hw, bool enable_eee);\ns32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee);\nvoid ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable,\n\t\t\t\t\t unsigned int pool);\nvoid ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,\n\t\t\t\t\t bool enable, int vf);\ns32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t\t u32 device_type, u32 data);\ns32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t\tu32 device_type, u32 *data);\nvoid ixgbe_disable_mdd_X550(struct ixgbe_hw *hw);\nvoid ixgbe_enable_mdd_X550(struct ixgbe_hw *hw);\nvoid ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap);\nvoid ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf);\nenum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw);\ns32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw);\ns32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed, bool *autoneg);\nvoid ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw);\ns32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw);\ns32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw);\ns32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw);\ns32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw);\ns32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw);\ns32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw);\ns32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw);\nu32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw);\nvoid ixgbe_disable_rx_x550(struct ixgbe_hw *hw);\ns32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed);\ns32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw);\ns32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask);\nvoid ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask);\ns32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw);\ns32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw);\ns32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t bool *link_up, bool link_up_wait_to_complete);\ns32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw);\ns32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw);\ns32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx);\ns32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx);\n#endif /* _IXGBE_X550_H_ */\n" }, { "path": "drivers/net/ixgbe/ixgbe_82599_bypass.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"base/ixgbe_type.h\"\n#include \"base/ixgbe_82599.h\"\n#include \"base/ixgbe_api.h\"\n#include \"base/ixgbe_common.h\"\n#include \"base/ixgbe_phy.h\"\n#include \"ixgbe_bypass_defines.h\"\n#include \"ixgbe_bypass.h\"\n\n/**\n * ixgbe_set_fiber_fixed_speed - Set module link speed for fixed fiber\n * @hw: pointer to hardware structure\n * @speed: link speed to set\n *\n * We set the module speed differently for fixed fiber. For other\n * multi-speed devices we don't have an error value so here if we\n * detect an error we just log it and exit.\n */\nstatic void\nixgbe_set_fiber_fixed_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)\n{\n\ts32 status;\n\tu8 rs, eeprom_data;\n\n\tswitch (speed) {\n\tcase IXGBE_LINK_SPEED_10GB_FULL:\n\t\t/* one bit mask same as setting on */\n\t\trs = IXGBE_SFF_SOFT_RS_SELECT_10G;\n\t\tbreak;\n\tcase IXGBE_LINK_SPEED_1GB_FULL:\n\t\trs = IXGBE_SFF_SOFT_RS_SELECT_1G;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"Invalid fixed module speed\");\n\t\treturn;\n\t}\n\n\t/* Set RS0 */\n\tstatus = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR2,\n\t\t\t\t\t &eeprom_data);\n\tif (status) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to read Rx Rate Select RS0\");\n\t\tgoto out;\n\t}\n\n\teeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;\n\n\tstatus = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR2,\n\t\t\t\t\t eeprom_data);\n\tif (status) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to write Rx Rate Select RS0\");\n\t\tgoto out;\n\t}\n\n\t/* Set RS1 */\n\tstatus = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR2,\n\t\t\t\t\t &eeprom_data);\n\tif (status) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to read Rx Rate Select RS1\");\n\t\tgoto out;\n\t}\n\n\teeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;\n\n\tstatus = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR2,\n\t\t\t\t\t eeprom_data);\n\tif (status) {\n\t\tPMD_DRV_LOG(ERR, \"Failed to write Rx Rate Select RS1\");\n\t\tgoto out;\n\t}\nout:\n\treturn;\n}\n\n/**\n * ixgbe_setup_mac_link_multispeed_fixed_fiber - Set MAC link speed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Set the link speed in the AUTOC register and restarts link.\n **/\nstatic s32\nixgbe_setup_mac_link_multispeed_fixed_fiber(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg_wait_to_complete)\n{\n\ts32 status = IXGBE_SUCCESS;\n\tixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;\n\tixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;\n\tu32 speedcnt = 0;\n\tu32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\tu32 i = 0;\n\tbool link_up = false;\n\tbool negotiation;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* Mask off requested but non-supported speeds */\n\tstatus = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);\n\tif (status != IXGBE_SUCCESS)\n\t\treturn status;\n\n\tspeed &= link_speed;\n\n\t/*\n\t * Try each speed one by one, highest priority first. We do this in\n\t * software because 10gb fiber doesn't support speed autonegotiation.\n\t */\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL) {\n\t\tspeedcnt++;\n\t\thighest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;\n\n\t\t/* If we already have link at this speed, just jump out */\n\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up, false);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\tif ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)\n\t\t\tgoto out;\n\t\t/* Set the module link speed */\n\t\tixgbe_set_fiber_fixed_speed(hw, IXGBE_LINK_SPEED_10GB_FULL);\n\n\t\t/* Set the module link speed */\n\t\tesdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\n\t\t/* Allow module to change analog characteristics (1G->10G) */\n\t\tmsec_delay(40);\n\n\t\tstatus = ixgbe_setup_mac_link_82599(hw,\n\t\t\t\t\t\t IXGBE_LINK_SPEED_10GB_FULL,\n\t\t\t\t\t\t autoneg_wait_to_complete);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\t/* Flap the tx laser if it has not already been done */\n\t\tixgbe_flap_tx_laser(hw);\n\n\t\t/*\n\t\t * Wait for the controller to acquire link. Per IEEE 802.3ap,\n\t\t * Section 73.10.2, we may have to wait up to 500ms if KR is\n\t\t * attempted. 82599 uses the same timing for 10g SFI.\n\t\t */\n\t\tfor (i = 0; i < 5; i++) {\n\t\t\t/* Wait for the link partner to also set speed */\n\t\t\tmsec_delay(100);\n\n\t\t\t/* If we have link, just jump out */\n\t\t\tstatus = ixgbe_check_link(hw, &link_speed,\n\t\t\t\t\t\t &link_up, false);\n\t\t\tif (status != IXGBE_SUCCESS)\n\t\t\t\treturn status;\n\n\t\t\tif (link_up)\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL) {\n\t\tspeedcnt++;\n\t\tif (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)\n\t\t\thighest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;\n\n\t\t/* If we already have link at this speed, just jump out */\n\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up, false);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\tif ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)\n\t\t\tgoto out;\n\n\t\t/* Set the module link speed */\n\t\tixgbe_set_fiber_fixed_speed(hw, IXGBE_LINK_SPEED_1GB_FULL);\n\n\t\t/* Allow module to change analog characteristics (10G->1G) */\n\t\tmsec_delay(40);\n\n\t\tstatus = ixgbe_setup_mac_link_82599(hw,\n\t\t\t\t\t\t IXGBE_LINK_SPEED_1GB_FULL,\n\t\t\t\t\t\t autoneg_wait_to_complete);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\t/* Flap the tx laser if it has not already been done */\n\t\tixgbe_flap_tx_laser(hw);\n\n\t\t/* Wait for the link partner to also set speed */\n\t\tmsec_delay(100);\n\n\t\t/* If we have link, just jump out */\n\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up, false);\n\t\tif (status != IXGBE_SUCCESS)\n\t\t\treturn status;\n\n\t\tif (link_up)\n\t\t\tgoto out;\n\t}\n\n\t/*\n\t * We didn't get link. Configure back to the highest speed we tried,\n\t * (if there was more than one). We call ourselves back with just the\n\t * single highest speed that the user requested.\n\t */\n\tif (speedcnt > 1)\n\t\tstatus = ixgbe_setup_mac_link_multispeed_fixed_fiber(hw,\n\t\t\thighest_link_speed, autoneg_wait_to_complete);\n\nout:\n\t/* Set autoneg_advertised value based on input link speed */\n\thw->phy.autoneg_advertised = 0;\n\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;\n\n\treturn status;\n}\n\nstatic enum ixgbe_media_type\nixgbe_bypass_get_media_type(struct ixgbe_hw *hw)\n{\n\tenum ixgbe_media_type media_type;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {\n\t\tmedia_type = ixgbe_media_type_fiber;\n\t} else {\n\t\tmedia_type = ixgbe_get_media_type_82599(hw);\n\t}\n\treturn (media_type);\n}\n\n/*\n * Wrapper around shared code (base driver) to support BYPASS nic.\n */\ns32\nixgbe_bypass_init_shared_code(struct ixgbe_hw *hw)\n{\n\ts32 ret_val;\n\n\tif (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {\n\t\thw->mac.type = ixgbe_mac_82599EB;\n\t}\n\n\tret_val = ixgbe_init_shared_code(hw);\n\tif (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {\n\t\thw->mac.ops.get_media_type = &ixgbe_bypass_get_media_type;\n\t\tixgbe_init_mac_link_ops_82599(hw);\n\t}\n\n\treturn ret_val;\n}\n\ns32\nixgbe_bypass_init_hw(struct ixgbe_hw *hw)\n{\n\tint rc;\n\n\tif ((rc = ixgbe_init_hw(hw)) == 0 &&\n\t\t\thw->device_id == IXGBE_DEV_ID_82599_BYPASS) {\n\n\t\thw->mac.ops.setup_link =\n\t\t\t&ixgbe_setup_mac_link_multispeed_fixed_fiber;\n\n\t\thw->mac.ops.get_media_type = &ixgbe_bypass_get_media_type;\n\n\t\thw->mac.ops.disable_tx_laser = NULL;\n hw->mac.ops.enable_tx_laser = NULL;\n hw->mac.ops.flap_tx_laser = NULL;\n\t}\n\n\treturn (rc);\n}\n" }, { "path": "drivers/net/ixgbe/ixgbe_bypass.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \"ixgbe_ethdev.h\"\n#include \"ixgbe_bypass_api.h\"\n\n#define\tBYPASS_STATUS_OFF_MASK\t3\n\n/* Macros to check for invlaid function pointers. */\n#define\tFUNC_PTR_OR_ERR_RET(func, retval) do { \\\n\tif ((func) == NULL) { \\\n\t\tPMD_DRV_LOG(ERR, \"%s:%d function not supported\", \\\n\t\t\t __func__, __LINE__); \\\n\t\treturn retval; \\\n\t} \\\n} while(0)\n\n#define\tFUNC_PTR_OR_RET(func) do { \\\n\tif ((func) == NULL) { \\\n\t\tPMD_DRV_LOG(ERR, \"%s:%d function not supported\", \\\n\t\t\t __func__, __LINE__); \\\n\t\treturn; \\\n\t} \\\n} while(0)\n\n\n/**\n * ixgbe_bypass_set_time - Set bypass FW time epoc.\n *\n * @hw: pointer to hardware structure\n *\n * This function with sync the FW date stamp with that of the\n * system clock.\n **/\nstatic void\nixgbe_bypass_set_time(struct ixgbe_adapter *adapter)\n{\n\tu32 mask, value;\n\tu32 sec;\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\n\tsec = 0;\n\n\t/*\n\t * Send the FW our current time and turn on time_valid and\n\t * timer_reset bits.\n\t */\n\tmask = BYPASS_CTL1_TIME_M |\n\t BYPASS_CTL1_VALID_M |\n\t BYPASS_CTL1_OFFTRST_M;\n\tvalue = (sec & BYPASS_CTL1_TIME_M) |\n\t BYPASS_CTL1_VALID |\n\t\tBYPASS_CTL1_OFFTRST;\n\n\tFUNC_PTR_OR_RET(adapter->bps.ops.bypass_set);\n\n\t/* Store FW reset time (in seconds from epoch). */\n\tadapter->bps.reset_tm = time(NULL);\n\n\t/* reset FW timer. */\n\tadapter->bps.ops.bypass_set(hw, BYPASS_PAGE_CTL1, mask, value);\n}\n\n/**\n * ixgbe_bypass_init - Make some environment changes for bypass\n *\n * @adapter: pointer to ixgbe_adapter structure for access to state bits\n *\n * This function collects all the modifications needed by the bypass\n * driver.\n **/\nvoid\nixgbe_bypass_init(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_adapter *adapter;\n\tstruct ixgbe_hw *hw;\n\n\tadapter = IXGBE_DEV_TO_ADPATER(dev);\n\thw = &adapter->hw;\n\n\t/* Only allow BYPASS ops on the first port */\n\tif (hw->device_id != IXGBE_DEV_ID_82599_BYPASS ||\n\t\t\thw->bus.func != 0) {\n\t\tPMD_DRV_LOG(ERR, \"bypass function is not supported on that device\");\n\t\treturn;\n\t}\n\n\t/* set bypass ops. */\n\tadapter->bps.ops.bypass_rw = &ixgbe_bypass_rw_generic;\n\tadapter->bps.ops.bypass_valid_rd = &ixgbe_bypass_valid_rd_generic;\n\tadapter->bps.ops.bypass_set = &ixgbe_bypass_set_generic;\n\tadapter->bps.ops.bypass_rd_eep = &ixgbe_bypass_rd_eep_generic;\n\n\t/* set the time for logging. */\n\tixgbe_bypass_set_time(adapter);\n\n\t/* Don't have the SDP to the laser */\n\thw->mac.ops.disable_tx_laser = NULL;\n\thw->mac.ops.enable_tx_laser = NULL;\n\thw->mac.ops.flap_tx_laser = NULL;\n}\n\ns32\nixgbe_bypass_state_show(struct rte_eth_dev *dev, u32 *state)\n{\n\tstruct ixgbe_hw *hw;\n\ts32 ret_val;\n\tu32 cmd;\n\tu32 by_ctl = 0;\n\tstruct ixgbe_adapter *adapter = IXGBE_DEV_TO_ADPATER(dev);\n\n\thw = &adapter->hw;\n\tFUNC_PTR_OR_ERR_RET(adapter->bps.ops.bypass_rw, -ENOTSUP);\n\n\tcmd = BYPASS_PAGE_CTL0;\n\tret_val = adapter->bps.ops.bypass_rw(hw, cmd, &by_ctl);\n\n\t/* Assume bypass_rw didn't error out, if it did state will\n\t * be ignored anyway.\n\t */\n\t*state = (by_ctl >> BYPASS_STATUS_OFF_SHIFT) & BYPASS_STATUS_OFF_MASK;\n\n\treturn (ret_val);\n}\n\n\ns32\nixgbe_bypass_state_store(struct rte_eth_dev *dev, u32 *new_state)\n{\n\tstruct ixgbe_adapter *adapter = IXGBE_DEV_TO_ADPATER(dev);\n\tstruct ixgbe_hw *hw;\n\ts32 ret_val;\n\n\thw = &adapter->hw;\n\tFUNC_PTR_OR_ERR_RET(adapter->bps.ops.bypass_set, -ENOTSUP);\n\n\t/* Set the new state */\n\tret_val = adapter->bps.ops.bypass_set(hw, BYPASS_PAGE_CTL0,\n\t\t\t\t\t BYPASS_MODE_OFF_M, *new_state);\n\tif (ret_val)\n\t\tgoto exit;\n\n\t/* Set AUTO back on so FW can receive events */\n\tret_val = adapter->bps.ops.bypass_set(hw, BYPASS_PAGE_CTL0,\n\t\t\t\t\t BYPASS_MODE_OFF_M, BYPASS_AUTO);\n\nexit:\n\treturn ret_val;\n\n}\n\ns32\nixgbe_bypass_event_show(struct rte_eth_dev *dev, u32 event,\n\t\t\t u32 *state)\n{\n\tstruct ixgbe_hw *hw;\n\ts32 ret_val;\n\tu32 shift;\n\tu32 cmd;\n\tu32 by_ctl = 0;\n\tstruct ixgbe_adapter *adapter = IXGBE_DEV_TO_ADPATER(dev);\n\n\thw = &adapter->hw;\n\tFUNC_PTR_OR_ERR_RET(adapter->bps.ops.bypass_rw, -ENOTSUP);\n\n\tcmd = BYPASS_PAGE_CTL0;\n\tret_val = adapter->bps.ops.bypass_rw(hw, cmd, &by_ctl);\n\n\t/* Assume bypass_rw didn't error out, if it did event will\n\t * be ignored anyway.\n\t */\n\tswitch (event) {\n\tcase BYPASS_EVENT_WDT_TO:\n\t\tshift = BYPASS_WDTIMEOUT_SHIFT;\n\t\tbreak;\n\tcase BYPASS_EVENT_MAIN_ON:\n\t\tshift = BYPASS_MAIN_ON_SHIFT;\n\t\tbreak;\n\tcase BYPASS_EVENT_MAIN_OFF:\n\t\tshift = BYPASS_MAIN_OFF_SHIFT;\n\t\tbreak;\n\tcase BYPASS_EVENT_AUX_ON:\n\t\tshift = BYPASS_AUX_ON_SHIFT;\n\t\tbreak;\n\tcase BYPASS_EVENT_AUX_OFF:\n\t\tshift = BYPASS_AUX_OFF_SHIFT;\n\t\tbreak;\n\tdefault:\n\t\treturn EINVAL;\n\t}\n\n\t*state = (by_ctl >> shift) & 0x3;\n\n\treturn ret_val;\n}\n\ns32\nixgbe_bypass_event_store(struct rte_eth_dev *dev, u32 event,\n\t\t\t u32 state)\n{\n\tstruct ixgbe_hw *hw;\n\tu32 status;\n\tu32 off;\n\ts32 ret_val;\n\tstruct ixgbe_adapter *adapter = IXGBE_DEV_TO_ADPATER(dev);\n\n\thw = &adapter->hw;\n\tFUNC_PTR_OR_ERR_RET(adapter->bps.ops.bypass_set, -ENOTSUP);\n\n\tswitch (event) {\n\tcase BYPASS_EVENT_WDT_TO:\n\t\toff = BYPASS_WDTIMEOUT_M;\n\t\tstatus = state << BYPASS_WDTIMEOUT_SHIFT;\n\t\tbreak;\n\tcase BYPASS_EVENT_MAIN_ON:\n\t\toff = BYPASS_MAIN_ON_M;\n\t\tstatus = state << BYPASS_MAIN_ON_SHIFT;\n\t\tbreak;\n\tcase BYPASS_EVENT_MAIN_OFF:\n\t\toff = BYPASS_MAIN_OFF_M;\n\t\tstatus = state << BYPASS_MAIN_OFF_SHIFT;\n\t\tbreak;\n\tcase BYPASS_EVENT_AUX_ON:\n\t\toff = BYPASS_AUX_ON_M;\n\t\tstatus = state << BYPASS_AUX_ON_SHIFT;\n\t\tbreak;\n\tcase BYPASS_EVENT_AUX_OFF:\n\t\toff = BYPASS_AUX_OFF_M;\n\t\tstatus = state << BYPASS_AUX_OFF_SHIFT;\n\t\tbreak;\n\tdefault:\n\t\treturn EINVAL;\n\t}\n\n\tret_val = adapter->bps.ops.bypass_set(hw, BYPASS_PAGE_CTL0,\n\t\toff, status);\n\n\treturn ret_val;\n}\n\ns32\nixgbe_bypass_wd_timeout_store(struct rte_eth_dev *dev, u32 timeout)\n{\n\tstruct ixgbe_hw *hw;\n u32 status;\n u32 mask;\n\ts32 ret_val;\n\tstruct ixgbe_adapter *adapter = IXGBE_DEV_TO_ADPATER(dev);\n\n\thw = &adapter->hw;\n\tFUNC_PTR_OR_ERR_RET(adapter->bps.ops.bypass_set, -ENOTSUP);\n\n\t/* disable the timer with timeout of zero */\n\tif (timeout == RTE_BYPASS_TMT_OFF) {\n\t\tstatus = 0x0; /* WDG enable off */\n\t\tmask = BYPASS_WDT_ENABLE_M;\n\t} else {\n\t\t/* set time out value */\n\t\tmask = BYPASS_WDT_VALUE_M;\n\n\t\t/* enable the timer */\n\t\tstatus = timeout << BYPASS_WDT_TIME_SHIFT;\n\t\tstatus |= 0x1 << BYPASS_WDT_ENABLE_SHIFT;\n\t\tmask |= BYPASS_WDT_ENABLE_M;\n\t}\n\n\tret_val = adapter->bps.ops.bypass_set(hw, BYPASS_PAGE_CTL0,\n\t\tmask, status);\n\n\treturn ret_val;\n}\n\ns32\nixgbe_bypass_ver_show(struct rte_eth_dev *dev, u32 *ver)\n{\n\tstruct ixgbe_hw *hw;\n\tu32 cmd;\n\tu32 status;\n\ts32 ret_val;\n\tstruct ixgbe_adapter *adapter = IXGBE_DEV_TO_ADPATER(dev);\n\n\thw = &adapter->hw;\n\tFUNC_PTR_OR_ERR_RET(adapter->bps.ops.bypass_rw, -ENOTSUP);\n\n\tcmd = BYPASS_PAGE_CTL2 | BYPASS_WE;\n\tcmd |= (BYPASS_EEPROM_VER_ADD << BYPASS_CTL2_OFFSET_SHIFT) &\n\t BYPASS_CTL2_OFFSET_M;\n\tret_val = adapter->bps.ops.bypass_rw(hw, cmd, &status);\n\tif (ret_val)\n\t\tgoto exit;\n\n\t/* wait for the write to stick */\n\tmsleep(100);\n\n\t/* Now read the results */\n\tcmd &= ~BYPASS_WE;\n\tret_val = adapter->bps.ops.bypass_rw(hw, cmd, &status);\n\tif (ret_val)\n\t\tgoto exit;\n\n\t*ver = status & BYPASS_CTL2_DATA_M; /* only one byte of date */\n\nexit:\n\treturn ret_val;\n}\n\ns32\nixgbe_bypass_wd_timeout_show(struct rte_eth_dev *dev, u32 *wd_timeout)\n{\n\tstruct ixgbe_hw *hw;\n\tu32 by_ctl = 0;\n\tu32 cmd;\n\tu32 wdg;\n\ts32 ret_val;\n\tstruct ixgbe_adapter *adapter = IXGBE_DEV_TO_ADPATER(dev);\n\n\thw = &adapter->hw;\n\tFUNC_PTR_OR_ERR_RET(adapter->bps.ops.bypass_rw, -ENOTSUP);\n\n\tcmd = BYPASS_PAGE_CTL0;\n\tret_val = adapter->bps.ops.bypass_rw(hw, cmd, &by_ctl);\n\n\twdg = by_ctl & BYPASS_WDT_ENABLE_M;\n\tif (!wdg)\n\t\t*wd_timeout = RTE_BYPASS_TMT_OFF;\n\telse\n\t\t*wd_timeout = (by_ctl >> BYPASS_WDT_TIME_SHIFT) &\n\t\t\tBYPASS_WDT_MASK;\n\n\treturn ret_val;\n}\n\ns32\nixgbe_bypass_wd_reset(struct rte_eth_dev *dev)\n{\n\tu32 cmd;\n\tu32 status;\n\tu32 sec;\n\tu32 count = 0;\n\ts32 ret_val;\n\tstruct ixgbe_hw *hw;\n\tstruct ixgbe_adapter *adapter = IXGBE_DEV_TO_ADPATER(dev);\n\n\thw = &adapter->hw;\n\n\tFUNC_PTR_OR_ERR_RET(adapter->bps.ops.bypass_rw, -ENOTSUP);\n\tFUNC_PTR_OR_ERR_RET(adapter->bps.ops.bypass_valid_rd, -ENOTSUP);\n\n\t/* Use the lower level bit-bang functions since we don't need\n\t * to read the register first to get it's current state as we\n\t * are setting every thing in this write.\n\t */\n\t/* Set up WD pet */\n\tcmd = BYPASS_PAGE_CTL1 | BYPASS_WE | BYPASS_CTL1_WDT_PET;\n\n\t/* Resync the FW time while writing to CTL1 anyway */\n\tadapter->bps.reset_tm = time(NULL);\n\tsec = 0;\n\n\tcmd |= (sec & BYPASS_CTL1_TIME_M) | BYPASS_CTL1_VALID;\n\n\t/* reset FW timer offset since we are resetting the clock */\n\tcmd |= BYPASS_CTL1_OFFTRST;\n\n\tret_val = adapter->bps.ops.bypass_rw(hw, cmd, &status);\n\n\t/* Read until it matches what we wrote, or we time out */\n\tdo {\n\t\tif (count++ > 10) {\n\t\t\tret_val = IXGBE_BYPASS_FW_WRITE_FAILURE;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (adapter->bps.ops.bypass_rw(hw, BYPASS_PAGE_CTL1, &status)) {\n\t\t\tret_val = IXGBE_ERR_INVALID_ARGUMENT;\n\t\t\tbreak;\n\t\t}\n\t} while (!adapter->bps.ops.bypass_valid_rd(cmd, status));\n\n\treturn ret_val;\n}\n" }, { "path": "drivers/net/ixgbe/ixgbe_bypass.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _IXGBE_BYPASS_H_\n#define _IXGBE_BYPASS_H_\n\n#ifdef RTE_NIC_BYPASS\n\nstruct ixgbe_bypass_mac_ops {\n\ts32 (*bypass_rw) (struct ixgbe_hw *hw, u32 cmd, u32 *status);\n\tbool (*bypass_valid_rd) (u32 in_reg, u32 out_reg);\n\ts32 (*bypass_set) (struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action);\n\ts32 (*bypass_rd_eep) (struct ixgbe_hw *hw, u32 addr, u8 *value);\n};\n\nstruct ixgbe_bypass_info {\n\tuint64_t reset_tm;\n\tstruct ixgbe_bypass_mac_ops ops;\n};\n\nstruct rte_eth_dev;\n\nvoid ixgbe_bypass_init(struct rte_eth_dev *dev);\ns32 ixgbe_bypass_state_show(struct rte_eth_dev *dev, u32 *state);\ns32 ixgbe_bypass_state_store(struct rte_eth_dev *dev, u32 *new_state);\ns32 ixgbe_bypass_event_show(struct rte_eth_dev *dev, u32 event, u32 *state);\ns32 ixgbe_bypass_event_store(struct rte_eth_dev *dev, u32 event, u32 state);\ns32 ixgbe_bypass_wd_timeout_store(struct rte_eth_dev *dev, u32 timeout);\ns32 ixgbe_bypass_ver_show(struct rte_eth_dev *dev, u32 *ver);\ns32 ixgbe_bypass_wd_timeout_show(struct rte_eth_dev *dev, u32 *wd_timeout);\ns32 ixgbe_bypass_wd_reset(struct rte_eth_dev *dev);\n\ns32 ixgbe_bypass_init_shared_code(struct ixgbe_hw *hw);\ns32 ixgbe_bypass_init_hw(struct ixgbe_hw *hw);\n\n#endif /* RTE_NIC_BYPASS */\n\n#endif /* _IXGBE_BYPASS_H_ */\n" }, { "path": "drivers/net/ixgbe/ixgbe_bypass_api.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _IXGBE_BYPASS_API_H_\n#define _IXGBE_BYPASS_API_H_\n\n#ifdef RTE_NIC_BYPASS\n\n#include \"ixgbe_bypass_defines.h\"\n/**\n * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW\n *\n * @hw: pointer to hardware structure\n * @cmd: Command we send to the FW\n * @status: The reply from the FW\n *\n * Bit-bangs the cmd to the by_pass FW status points to what is returned.\n **/\n#define IXGBE_BYPASS_BB_WAIT 1\nstatic s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status)\n{\n\tint i;\n\tu32 sck, sdi, sdo, dir_sck, dir_sdi, dir_sdo;\n\tu32 esdp;\n\n\tif (!status)\n\t\treturn IXGBE_ERR_PARAM;\n\n\t*status = 0;\n\n\t/* SDP vary by MAC type */\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82599EB:\n\t\tsck = IXGBE_ESDP_SDP7;\n\t\tsdi = IXGBE_ESDP_SDP0;\n\t\tsdo = IXGBE_ESDP_SDP6;\n\t\tdir_sck = IXGBE_ESDP_SDP7_DIR;\n\t\tdir_sdi = IXGBE_ESDP_SDP0_DIR;\n\t\tdir_sdo = IXGBE_ESDP_SDP6_DIR;\n\t\tbreak;\n\tcase ixgbe_mac_X540:\n\t\tsck = IXGBE_ESDP_SDP2;\n\t\tsdi = IXGBE_ESDP_SDP0;\n\t\tsdo = IXGBE_ESDP_SDP1;\n\t\tdir_sck = IXGBE_ESDP_SDP2_DIR;\n\t\tdir_sdi = IXGBE_ESDP_SDP0_DIR;\n\t\tdir_sdo = IXGBE_ESDP_SDP1_DIR;\n\t\tbreak;\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tsck = IXGBE_ESDP_SDP2;\n\t\tsdi = IXGBE_ESDP_SDP0;\n\t\tsdo = IXGBE_ESDP_SDP1;\n\t\tdir_sck = IXGBE_ESDP_SDP2_DIR;\n\t\tdir_sdi = IXGBE_ESDP_SDP0_DIR;\n\t\tdir_sdo = IXGBE_ESDP_SDP1_DIR;\n\t\tbreak;\n\tdefault:\n\t\treturn IXGBE_ERR_DEVICE_NOT_SUPPORTED;\n\t}\n\n\t/* Set SDP pins direction */\n\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\tesdp |= dir_sck;\t/* SCK as output */\n\tesdp |= dir_sdi;\t/* SDI as output */\n\tesdp &= ~dir_sdo;\t/* SDO as input */\n\tesdp |= sck;\n\tesdp |= sdi;\n\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\tIXGBE_WRITE_FLUSH(hw);\n // TODO:\n\tmsleep(IXGBE_BYPASS_BB_WAIT);\n\n\t/* Generate start condition */\n\tesdp &= ~sdi;\n\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\tIXGBE_WRITE_FLUSH(hw);\n\tmsleep(IXGBE_BYPASS_BB_WAIT);\n\n\tesdp &= ~sck;\n\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\tIXGBE_WRITE_FLUSH(hw);\n\tmsleep(IXGBE_BYPASS_BB_WAIT);\n\n\t/* Clock out the new control word and clock in the status */\n\tfor (i = 0; i < 32; i++) {\n\t\tif ((cmd >> (31 - i)) & 0x01) {\n\t\t\tesdp |= sdi;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\t} else {\n\t\t\tesdp &= ~sdi;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\t}\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t\tmsleep(IXGBE_BYPASS_BB_WAIT);\n\n\t\tesdp |= sck;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t\tmsleep(IXGBE_BYPASS_BB_WAIT);\n\n\t\tesdp &= ~sck;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t\tmsleep(IXGBE_BYPASS_BB_WAIT);\n\n\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\tif (esdp & sdo)\n\t\t\t*status = (*status << 1) | 0x01;\n\t\telse\n\t\t\t*status = (*status << 1) | 0x00;\n\t\tmsleep(IXGBE_BYPASS_BB_WAIT);\n\t}\n\n\t/* stop condition */\n\tesdp |= sck;\n\tesdp &= ~sdi;\n\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\tIXGBE_WRITE_FLUSH(hw);\n\tmsleep(IXGBE_BYPASS_BB_WAIT);\n\n\tesdp |= sdi;\n\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* set the page bits to match the cmd that the status it belongs to */\n\t*status = (*status & 0x3fffffff) | (cmd & 0xc0000000);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang.\n *\n * If we send a write we can't be sure it took until we can read back\n * that same register. It can be a problem as some of the feilds may\n * for valid reasons change between the time wrote the register and\n * we read it again to verify. So this function check everything we\n * can check and then assumes it worked.\n *\n * @u32 in_reg - The register cmd for the bit-bang read.\n * @u32 out_reg - The register returned from a bit-bang read.\n **/\nstatic bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg)\n{\n\tu32 mask;\n\n\t/* Page must match for all control pages */\n\tif ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M))\n\t\treturn false;\n\n\tswitch (in_reg & BYPASS_PAGE_M) {\n\tcase BYPASS_PAGE_CTL0:\n\t\t/* All the following can't change since the last write\n\t\t * - All the event actions\n\t\t * - The timeout value\n\t\t */\n\t\tmask = BYPASS_AUX_ON_M | BYPASS_MAIN_ON_M |\n\t\t BYPASS_MAIN_OFF_M | BYPASS_AUX_OFF_M |\n\t\t BYPASS_WDTIMEOUT_M |\n\t\t BYPASS_WDT_VALUE_M;\n\t\tif ((out_reg & mask) != (in_reg & mask))\n\t\t\treturn false;\n\n\t\t/* 0x0 is never a valid value for bypass status */\n\t\tif (!(out_reg & BYPASS_STATUS_OFF_M))\n\t\t\treturn false;\n\t\tbreak;\n\tcase BYPASS_PAGE_CTL1:\n\t\t/* All the following can't change since the last write\n\t\t * - time valid bit\n\t\t * - time we last sent\n\t\t */\n\t\tmask = BYPASS_CTL1_VALID_M | BYPASS_CTL1_TIME_M;\n\t\tif ((out_reg & mask) != (in_reg & mask))\n\t\t\treturn false;\n\t\tbreak;\n\tcase BYPASS_PAGE_CTL2:\n\t\t/* All we can check in this page is control number\n\t\t * which is already done above.\n\t\t */\n\t\tbreak;\n\t}\n\n\t/* We are as sure as we can be return true */\n\treturn true;\n}\n\n/**\n * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter.\n *\n * @hw: pointer to hardware structure\n * @cmd: The control word we are setting.\n * @event: The event we are setting in the FW. This also happens to\n *\t be the mask for the event we are setting (handy)\n * @action: The action we set the event to in the FW. This is in a\n *\t bit field that happens to be what we want to put in\n *\t the event spot (also handy)\n **/\nstatic s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event,\n\t\t\t u32 action)\n{\n\tu32 by_ctl = 0;\n\tu32 cmd, verify;\n\tu32 count = 0;\n\n\t/* Get current values */\n\tcmd = ctrl;\t/* just reading only need control number */\n\tif (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\n\t/* Set to new action */\n\tcmd = (by_ctl & ~event) | BYPASS_WE | action;\n\tif (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl))\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\n\t/* Page 0 force a FW eeprom write which is slow so verify */\n\tif ((cmd & BYPASS_PAGE_M) == BYPASS_PAGE_CTL0) {\n\t\tverify = BYPASS_PAGE_CTL0;\n\t\tdo {\n\t\t\tif (count++ > 5)\n\t\t\t\treturn IXGBE_BYPASS_FW_WRITE_FAILURE;\n\n\t\t\tif (ixgbe_bypass_rw_generic(hw, verify, &by_ctl))\n\t\t\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t\t} while (!ixgbe_bypass_valid_rd_generic(cmd, by_ctl));\n\t} else {\n\t\t/* We have give the FW time for the write to stick */\n\t\tmsleep(100);\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom address.\n *\n * @hw: pointer to hardware structure\n * @addr: The bypass eeprom address to read.\n * @value: The 8b of data at the address above.\n **/\nstatic s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)\n{\n\tu32 cmd;\n\tu32 status;\n\n\n\t/* send the request */\n\tcmd = BYPASS_PAGE_CTL2 | BYPASS_WE;\n\tcmd |= (addr << BYPASS_CTL2_OFFSET_SHIFT) & BYPASS_CTL2_OFFSET_M;\n\tif (ixgbe_bypass_rw_generic(hw, cmd, &status))\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\n\t/* We have give the FW time for the write to stick */\n\tmsleep(100);\n\n\t/* now read the results */\n\tcmd &= ~BYPASS_WE;\n\tif (ixgbe_bypass_rw_generic(hw, cmd, &status))\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\n\t*value = status & BYPASS_CTL2_DATA_M;\n\n\treturn 0;\n}\n\n#endif /* RTE_NIC_BYPASS */\n\n#endif /* _IXGBE_BYPASS_API_H_ */\n" }, { "path": "drivers/net/ixgbe/ixgbe_bypass_defines.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _IXGBE_BYPASS_DEFINES_H_\n#define _IXGBE_BYPASS_DEFINES_H_\n\n#ifdef RTE_NIC_BYPASS\n\n#define msleep(x) rte_delay_us(x*1000)\n#define usleep_range(min, max) rte_delay_us(min)\n\n#define BYPASS_PAGE_CTL0\t0x00000000\n#define BYPASS_PAGE_CTL1\t0x40000000\n#define BYPASS_PAGE_CTL2\t0x80000000\n#define BYPASS_PAGE_M\t\t0xc0000000\n#define BYPASS_WE\t\t0x20000000\n\n#define BYPASS_AUTO\t0x0\n#define BYPASS_NOP\t0x0\n#define BYPASS_NORM\t0x1\n#define BYPASS_BYPASS\t0x2\n#define BYPASS_ISOLATE\t0x3\n\n#define BYPASS_EVENT_MAIN_ON\t0x1\n#define BYPASS_EVENT_AUX_ON\t0x2\n#define BYPASS_EVENT_MAIN_OFF\t0x3\n#define BYPASS_EVENT_AUX_OFF\t0x4\n#define BYPASS_EVENT_WDT_TO\t0x5\n#define BYPASS_EVENT_USR\t0x6\n\n#define BYPASS_MODE_OFF_M\t0x00000003\n#define BYPASS_STATUS_OFF_M\t0x0000000c\n#define BYPASS_AUX_ON_M\t\t0x00000030\n#define BYPASS_MAIN_ON_M\t0x000000c0\n#define BYPASS_MAIN_OFF_M\t0x00000300\n#define BYPASS_AUX_OFF_M\t0x00000c00\n#define BYPASS_WDTIMEOUT_M\t0x00003000\n#define BYPASS_WDT_ENABLE_M\t0x00004000\n#define BYPASS_WDT_VALUE_M\t0x00070000\n\n#define BYPASS_MODE_OFF_SHIFT\t0\n#define BYPASS_STATUS_OFF_SHIFT\t2\n#define BYPASS_AUX_ON_SHIFT\t4\n#define BYPASS_MAIN_ON_SHIFT\t6\n#define BYPASS_MAIN_OFF_SHIFT\t8\n#define BYPASS_AUX_OFF_SHIFT\t10\n#define BYPASS_WDTIMEOUT_SHIFT\t12\n#define BYPASS_WDT_ENABLE_SHIFT\t14\n#define BYPASS_WDT_TIME_SHIFT\t16\n\n#define BYPASS_WDT_1\t0x0\n#define BYPASS_WDT_1_5\t0x1\n#define BYPASS_WDT_2\t0x2\n#define BYPASS_WDT_3\t0x3\n#define BYPASS_WDT_4\t0x4\n#define BYPASS_WDT_8\t0x5\n#define BYPASS_WDT_16\t0x6\n#define BYPASS_WDT_32\t0x7\n#define BYPASS_WDT_OFF\t0xffff\n\n#define BYPASS_WDT_MASK\t0x7\n\n#define BYPASS_CTL1_TIME_M\t0x01ffffff\n#define BYPASS_CTL1_VALID_M\t0x02000000\n#define BYPASS_CTL1_OFFTRST_M\t0x04000000\n#define BYPASS_CTL1_WDT_PET_M\t0x08000000\n\n#define BYPASS_CTL1_VALID\t0x02000000\n#define BYPASS_CTL1_OFFTRST\t0x04000000\n#define BYPASS_CTL1_WDT_PET\t0x08000000\n\n#define BYPASS_CTL2_DATA_M\t0x000000ff\n#define BYPASS_CTL2_OFFSET_M\t0x0000ff00\n#define BYPASS_CTL2_RW_M\t0x00010000\n#define BYPASS_CTL2_HEAD_M\t0x0ff00000\n\n#define BYPASS_CTL2_OFFSET_SHIFT\t8\n#define BYPASS_CTL2_HEAD_SHIFT\t\t20\n\n#define BYPASS_CTL2_RW\t\t0x00010000\n\nenum ixgbe_state_t {\n\t__IXGBE_TESTING,\n\t__IXGBE_RESETTING,\n\t__IXGBE_DOWN,\n\t__IXGBE_SERVICE_SCHED,\n\t__IXGBE_IN_SFP_INIT,\n\t__IXGBE_IN_BYPASS_LOW,\n\t__IXGBE_IN_BYPASS_HIGH,\n\t__IXGBE_IN_BYPASS_LOG,\n};\n\n#define BYPASS_MAX_LOGS\t\t43\n#define BYPASS_LOG_SIZE\t\t5\n#define BYPASS_LOG_LINE_SIZE\t37\n\n#define BYPASS_EEPROM_VER_ADD\t0x02\n\n#define BYPASS_LOG_TIME_M\t0x01ffffff\n#define BYPASS_LOG_TIME_VALID_M\t0x02000000\n#define BYPASS_LOG_HEAD_M\t0x04000000\n#define BYPASS_LOG_CLEAR_M\t0x08000000\n#define BYPASS_LOG_EVENT_M\t0xf0000000\n#define BYPASS_LOG_ACTION_M\t0x03\n\n#define BYPASS_LOG_EVENT_SHIFT\t28\n#define BYPASS_LOG_CLEAR_SHIFT\t24 /* bit offset */\n#define IXGBE_DEV_TO_ADPATER(dev) \\\n\t((struct ixgbe_adapter*)(dev->data->dev_private))\n\n/* extractions from ixgbe_phy.h */\n#define\tIXGBE_I2C_EEPROM_DEV_ADDR2\t0xA2\n\n#define IXGBE_SFF_SFF_8472_SWAP\t\t0x5C\n#define IXGBE_SFF_SFF_8472_COMP\t\t0x5E\n#define IXGBE_SFF_SFF_8472_OSCB\t\t0x6E\n#define IXGBE_SFF_SFF_8472_ESCB\t\t0x76\n\n#define IXGBE_SFF_SOFT_RS_SELECT_MASK\t0x8\n#define IXGBE_SFF_SOFT_RS_SELECT_10G\t0x8\n#define IXGBE_SFF_SOFT_RS_SELECT_1G\t0x0\n\n/* extractions from ixgbe_type.h */\n#define IXGBE_DEV_ID_82599_BYPASS\t0x155D\n\n#define IXGBE_BYPASS_FW_WRITE_FAILURE\t-35\n\n#endif /* RTE_NIC_BYPASS */\n\n#endif /* _IXGBE_BYPASS_DEFINES_H_ */\n" }, { "path": "drivers/net/ixgbe/ixgbe_ethdev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"ixgbe_logs.h\"\n#include \"base/ixgbe_api.h\"\n#include \"base/ixgbe_vf.h\"\n#include \"base/ixgbe_common.h\"\n#include \"ixgbe_ethdev.h\"\n#include \"ixgbe_bypass.h\"\n#include \"ixgbe_rxtx.h\"\n#include \"base/ixgbe_type.h\"\n#include \"base/ixgbe_phy.h\"\n#include \"ixgbe_regs.h\"\n\n/*\n * High threshold controlling when to start sending XOFF frames. Must be at\n * least 8 bytes less than receive packet buffer size. This value is in units\n * of 1024 bytes.\n */\n#define IXGBE_FC_HI 0x80\n\n/*\n * Low threshold controlling when to start sending XON frames. This value is\n * in units of 1024 bytes.\n */\n#define IXGBE_FC_LO 0x40\n\n/* Default minimum inter-interrupt interval for EITR configuration */\n#define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E\n\n/* Timer value included in XOFF frames. */\n#define IXGBE_FC_PAUSE 0x680\n\n#define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */\n#define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */\n#define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */\n\n#define IXGBE_MMW_SIZE_DEFAULT 0x4\n#define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14\n#define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */\n\n/*\n * Default values for RX/TX configuration\n */\n#define IXGBE_DEFAULT_RX_FREE_THRESH 32\n#define IXGBE_DEFAULT_RX_PTHRESH 8\n#define IXGBE_DEFAULT_RX_HTHRESH 8\n#define IXGBE_DEFAULT_RX_WTHRESH 0\n\n#define IXGBE_DEFAULT_TX_FREE_THRESH 32\n#define IXGBE_DEFAULT_TX_PTHRESH 32\n#define IXGBE_DEFAULT_TX_HTHRESH 0\n#define IXGBE_DEFAULT_TX_WTHRESH 0\n#define IXGBE_DEFAULT_TX_RSBIT_THRESH 32\n\n/* Bit shift and mask */\n#define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)\n#define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)\n#define IXGBE_8_BIT_WIDTH CHAR_BIT\n#define IXGBE_8_BIT_MASK UINT8_MAX\n\n#define IXGBEVF_PMD_NAME \"rte_ixgbevf_pmd\" /* PMD name */\n\n#define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))\n\n#define IXGBE_HKEY_MAX_INDEX 10\n\n/* Additional timesync values. */\n#define IXGBE_TIMINCA_16NS_SHIFT 24\n#define IXGBE_TIMINCA_INCVALUE 16000000\n#define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \\\n\t\t\t\t | IXGBE_TIMINCA_INCVALUE)\n\nstatic int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);\nstatic int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);\nstatic int ixgbe_dev_configure(struct rte_eth_dev *dev);\nstatic int ixgbe_dev_start(struct rte_eth_dev *dev);\nstatic void ixgbe_dev_stop(struct rte_eth_dev *dev);\nstatic int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);\nstatic int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);\nstatic void ixgbe_dev_close(struct rte_eth_dev *dev);\nstatic void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);\nstatic void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);\nstatic void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);\nstatic void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);\nstatic int ixgbe_dev_link_update(struct rte_eth_dev *dev,\n\t\t\t\tint wait_to_complete);\nstatic void ixgbe_dev_stats_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_stats *stats);\nstatic int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_xstats *xstats, unsigned n);\nstatic void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);\nstatic void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);\nstatic int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,\n\t\t\t\t\t uint16_t queue_id,\n\t\t\t\t\t uint8_t stat_idx,\n\t\t\t\t\t uint8_t is_rx);\nstatic void ixgbe_dev_info_get(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_dev_info *dev_info);\nstatic void ixgbevf_dev_info_get(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_dev_info *dev_info);\nstatic int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n\nstatic int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,\n\t\tuint16_t vlan_id, int on);\nstatic void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);\nstatic void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,\n\t\tuint16_t queue, bool on);\nstatic void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,\n\t\tint on);\nstatic void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);\nstatic void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);\nstatic void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);\nstatic void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);\nstatic void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);\n\nstatic int ixgbe_dev_led_on(struct rte_eth_dev *dev);\nstatic int ixgbe_dev_led_off(struct rte_eth_dev *dev);\nstatic int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_fc_conf *fc_conf);\nstatic int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_fc_conf *fc_conf);\nstatic int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_pfc_conf *pfc_conf);\nstatic int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\tuint16_t reta_size);\nstatic int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\tuint16_t reta_size);\nstatic void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);\nstatic int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);\n#ifdef RTE_NEXT_ABI\nstatic int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);\n#endif\nstatic int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);\nstatic int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);\nstatic void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,\n\t\tvoid *param);\nstatic void ixgbe_dev_interrupt_delayed_handler(void *param);\nstatic void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,\n\t\tuint32_t index, uint32_t pool);\nstatic void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);\nstatic void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,\n\t\t\t\t\t struct ether_addr *mac_addr);\nstatic void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);\n\n/* For Virtual Function support */\nstatic int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);\nstatic int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);\nstatic int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);\nstatic int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);\nstatic int ixgbevf_dev_configure(struct rte_eth_dev *dev);\nstatic int ixgbevf_dev_start(struct rte_eth_dev *dev);\nstatic void ixgbevf_dev_stop(struct rte_eth_dev *dev);\nstatic void ixgbevf_dev_close(struct rte_eth_dev *dev);\nstatic void ixgbevf_intr_disable(struct ixgbe_hw *hw);\nstatic void ixgbevf_intr_enable(struct ixgbe_hw *hw);\nstatic void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_stats *stats);\nstatic void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);\nstatic int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,\n\t\tuint16_t vlan_id, int on);\nstatic void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,\n\t\tuint16_t queue, int on);\nstatic void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);\nstatic void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);\nstatic void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,\n\t\t\t\t\t void *param);\n#ifdef RTE_NEXT_ABI\nstatic int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,\n\t\t\t\t\t uint16_t queue_id);\nstatic int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,\n\t\t\t\t\t uint16_t queue_id);\nstatic void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,\n\t\t\t\t uint8_t queue, uint8_t msix_vector);\n#endif\nstatic void ixgbevf_configure_msix(struct rte_eth_dev *dev);\n\n/* For Eth VMDQ APIs support */\nstatic int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct\n\t\tether_addr* mac_addr,uint8_t on);\nstatic int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);\nstatic int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,\n\t\tuint16_t rx_mask, uint8_t on);\nstatic int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);\nstatic int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);\nstatic int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,\n\t\tuint64_t pool_mask,uint8_t vlan_on);\nstatic int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_mirror_conf *mirror_conf,\n\t\tuint8_t rule_id, uint8_t on);\nstatic int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,\n\t\tuint8_t\trule_id);\n#ifdef RTE_NEXT_ABI\nstatic int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,\n\t\t\t\t\t uint16_t queue_id);\nstatic int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,\n\t\t\t\t\t uint16_t queue_id);\nstatic void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,\n\t\t\t uint8_t queue, uint8_t msix_vector);\n#endif\nstatic void ixgbe_configure_msix(struct rte_eth_dev *dev);\n\nstatic int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,\n\t\tuint16_t queue_idx, uint16_t tx_rate);\nstatic int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,\n\t\tuint16_t tx_rate, uint64_t q_msk);\n\nstatic void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,\n\t\t\t\t struct ether_addr *mac_addr,\n\t\t\t\t uint32_t index, uint32_t pool);\nstatic void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);\nstatic void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,\n\t\t\t\t\t struct ether_addr *mac_addr);\nstatic int ixgbe_syn_filter_set(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_syn_filter *filter,\n\t\t\tbool add);\nstatic int ixgbe_syn_filter_get(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_syn_filter *filter);\nstatic int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,\n\t\t\tenum rte_filter_op filter_op,\n\t\t\tvoid *arg);\nstatic int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct ixgbe_5tuple_filter *filter);\nstatic void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct ixgbe_5tuple_filter *filter);\nstatic int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *filter,\n\t\t\tbool add);\nstatic int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,\n\t\t\t\tenum rte_filter_op filter_op,\n\t\t\t\tvoid *arg);\nstatic int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *filter);\nstatic int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ethertype_filter *filter,\n\t\t\tbool add);\nstatic int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,\n\t\t\t\tenum rte_filter_op filter_op,\n\t\t\t\tvoid *arg);\nstatic int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ethertype_filter *filter);\nstatic int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,\n\t\t enum rte_filter_type filter_type,\n\t\t enum rte_filter_op filter_op,\n\t\t void *arg);\nstatic int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);\n\nstatic int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,\n\t\t\t\t struct ether_addr *mc_addr_set,\n\t\t\t\t uint32_t nb_mc_addr);\n\nstatic int ixgbe_get_reg_length(struct rte_eth_dev *dev);\nstatic int ixgbe_get_regs(struct rte_eth_dev *dev,\n\t\t\t struct rte_dev_reg_info *regs);\nstatic int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);\nstatic int ixgbe_get_eeprom(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_dev_eeprom_info *eeprom);\nstatic int ixgbe_set_eeprom(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_dev_eeprom_info *eeprom);\n\nstatic int ixgbevf_get_reg_length(struct rte_eth_dev *dev);\nstatic int ixgbevf_get_regs(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_dev_reg_info *regs);\n\nstatic int ixgbe_timesync_enable(struct rte_eth_dev *dev);\nstatic int ixgbe_timesync_disable(struct rte_eth_dev *dev);\nstatic int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n\t\t\t\t\t struct timespec *timestamp,\n\t\t\t\t\t uint32_t flags);\nstatic int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n\t\t\t\t\t struct timespec *timestamp);\n\n/*\n * Define VF Stats MACRO for Non \"cleared on read\" register\n */\n#define UPDATE_VF_STAT(reg, last, cur)\t \\\n{ \\\n\tuint32_t latest = IXGBE_READ_REG(hw, reg); \\\n\tcur += latest - last; \\\n\tlast = latest; \\\n}\n\n#define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \\\n{ \\\n\tu64 new_lsb = IXGBE_READ_REG(hw, lsb); \\\n\tu64 new_msb = IXGBE_READ_REG(hw, msb); \\\n\tu64 latest = ((new_msb << 32) | new_lsb); \\\n\tcur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \\\n\tlast = latest; \\\n}\n\n#define IXGBE_SET_HWSTRIP(h, q) do{\\\n\t\tuint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \\\n\t\tuint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \\\n\t\t(h)->bitmap[idx] |= 1 << bit;\\\n\t}while(0)\n\n#define IXGBE_CLEAR_HWSTRIP(h, q) do{\\\n\t\tuint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \\\n\t\tuint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \\\n\t\t(h)->bitmap[idx] &= ~(1 << bit);\\\n\t}while(0)\n\n#define IXGBE_GET_HWSTRIP(h, q, r) do{\\\n\t\tuint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \\\n\t\tuint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \\\n\t\t(r) = (h)->bitmap[idx] >> bit & 1;\\\n\t}while(0)\n\n/*\n * The set of PCI devices this driver supports\n */\nstatic const struct rte_pci_id pci_id_ixgbe_map[] = {\n\n#define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \"rte_pci_dev_ids.h\"\n\n{ .vendor_id = 0, /* sentinel */ },\n};\n\n\n/*\n * The set of PCI devices this driver supports (for 82599 VF)\n */\nstatic const struct rte_pci_id pci_id_ixgbevf_map[] = {\n\n#define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \"rte_pci_dev_ids.h\"\n{ .vendor_id = 0, /* sentinel */ },\n\n};\n\nstatic const struct eth_dev_ops ixgbe_eth_dev_ops = {\n\t.dev_configure = ixgbe_dev_configure,\n\t.dev_start = ixgbe_dev_start,\n\t.dev_stop = ixgbe_dev_stop,\n\t.dev_set_link_up = ixgbe_dev_set_link_up,\n\t.dev_set_link_down = ixgbe_dev_set_link_down,\n\t.dev_close = ixgbe_dev_close,\n\t.promiscuous_enable = ixgbe_dev_promiscuous_enable,\n\t.promiscuous_disable = ixgbe_dev_promiscuous_disable,\n\t.allmulticast_enable = ixgbe_dev_allmulticast_enable,\n\t.allmulticast_disable = ixgbe_dev_allmulticast_disable,\n\t.link_update = ixgbe_dev_link_update,\n\t.stats_get = ixgbe_dev_stats_get,\n\t.xstats_get = ixgbe_dev_xstats_get,\n\t.stats_reset = ixgbe_dev_stats_reset,\n\t.xstats_reset = ixgbe_dev_xstats_reset,\n\t.queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,\n\t.dev_infos_get = ixgbe_dev_info_get,\n\t.mtu_set = ixgbe_dev_mtu_set,\n\t.vlan_filter_set = ixgbe_vlan_filter_set,\n\t.vlan_tpid_set = ixgbe_vlan_tpid_set,\n\t.vlan_offload_set = ixgbe_vlan_offload_set,\n\t.vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,\n\t.rx_queue_start\t = ixgbe_dev_rx_queue_start,\n\t.rx_queue_stop = ixgbe_dev_rx_queue_stop,\n\t.tx_queue_start\t = ixgbe_dev_tx_queue_start,\n\t.tx_queue_stop = ixgbe_dev_tx_queue_stop,\n\t.rx_queue_setup = ixgbe_dev_rx_queue_setup,\n#ifdef RTE_NEXT_ABI\n\t.rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,\n\t.rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,\n#endif\n\t.rx_queue_release = ixgbe_dev_rx_queue_release,\n\t.rx_queue_count = ixgbe_dev_rx_queue_count,\n\t.rx_descriptor_done = ixgbe_dev_rx_descriptor_done,\n\t.tx_queue_setup = ixgbe_dev_tx_queue_setup,\n\t.tx_queue_release = ixgbe_dev_tx_queue_release,\n\t.dev_led_on = ixgbe_dev_led_on,\n\t.dev_led_off = ixgbe_dev_led_off,\n\t.flow_ctrl_get = ixgbe_flow_ctrl_get,\n\t.flow_ctrl_set = ixgbe_flow_ctrl_set,\n\t.priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,\n\t.mac_addr_add = ixgbe_add_rar,\n\t.mac_addr_remove = ixgbe_remove_rar,\n\t.mac_addr_set = ixgbe_set_default_mac_addr,\n\t.uc_hash_table_set = ixgbe_uc_hash_table_set,\n\t.uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,\n\t.mirror_rule_set = ixgbe_mirror_rule_set,\n\t.mirror_rule_reset = ixgbe_mirror_rule_reset,\n\t.set_vf_rx_mode = ixgbe_set_pool_rx_mode,\n\t.set_vf_rx = ixgbe_set_pool_rx,\n\t.set_vf_tx = ixgbe_set_pool_tx,\n\t.set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,\n\t.set_queue_rate_limit = ixgbe_set_queue_rate_limit,\n\t.set_vf_rate_limit = ixgbe_set_vf_rate_limit,\n\t.reta_update = ixgbe_dev_rss_reta_update,\n\t.reta_query = ixgbe_dev_rss_reta_query,\n#ifdef RTE_NIC_BYPASS\n\t.bypass_init = ixgbe_bypass_init,\n\t.bypass_state_set = ixgbe_bypass_state_store,\n\t.bypass_state_show = ixgbe_bypass_state_show,\n\t.bypass_event_set = ixgbe_bypass_event_store,\n\t.bypass_event_show = ixgbe_bypass_event_show,\n\t.bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,\n\t.bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,\n\t.bypass_ver_show = ixgbe_bypass_ver_show,\n\t.bypass_wd_reset = ixgbe_bypass_wd_reset,\n#endif /* RTE_NIC_BYPASS */\n\t.rss_hash_update = ixgbe_dev_rss_hash_update,\n\t.rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,\n\t.filter_ctrl = ixgbe_dev_filter_ctrl,\n\t.set_mc_addr_list = ixgbe_dev_set_mc_addr_list,\n\t.timesync_enable = ixgbe_timesync_enable,\n\t.timesync_disable = ixgbe_timesync_disable,\n\t.timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,\n\t.timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,\n\t.get_reg_length = ixgbe_get_reg_length,\n\t.get_reg = ixgbe_get_regs,\n\t.get_eeprom_length = ixgbe_get_eeprom_length,\n\t.get_eeprom = ixgbe_get_eeprom,\n\t.set_eeprom = ixgbe_set_eeprom,\n};\n\n/*\n * dev_ops for virtual function, bare necessities for basic vf\n * operation have been implemented\n */\nstatic const struct eth_dev_ops ixgbevf_eth_dev_ops = {\n\t.dev_configure = ixgbevf_dev_configure,\n\t.dev_start = ixgbevf_dev_start,\n\t.dev_stop = ixgbevf_dev_stop,\n\t.link_update = ixgbe_dev_link_update,\n\t.stats_get = ixgbevf_dev_stats_get,\n\t.stats_reset = ixgbevf_dev_stats_reset,\n\t.dev_close = ixgbevf_dev_close,\n\t.dev_infos_get = ixgbevf_dev_info_get,\n\t.mtu_set = ixgbevf_dev_set_mtu,\n\t.vlan_filter_set = ixgbevf_vlan_filter_set,\n\t.vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,\n\t.vlan_offload_set = ixgbevf_vlan_offload_set,\n\t.rx_queue_setup = ixgbe_dev_rx_queue_setup,\n\t.rx_queue_release = ixgbe_dev_rx_queue_release,\n\t.rx_descriptor_done = ixgbe_dev_rx_descriptor_done,\n\t.tx_queue_setup = ixgbe_dev_tx_queue_setup,\n\t.tx_queue_release = ixgbe_dev_tx_queue_release,\n#ifdef RTE_NEXT_ABI\n\t.rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,\n\t.rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,\n#endif\n\t.mac_addr_add = ixgbevf_add_mac_addr,\n\t.mac_addr_remove = ixgbevf_remove_mac_addr,\n\t.set_mc_addr_list = ixgbe_dev_set_mc_addr_list,\n\t.mac_addr_set = ixgbevf_set_default_mac_addr,\n\t.get_reg_length = ixgbevf_get_reg_length,\n\t.get_reg = ixgbevf_get_regs,\n};\n\n/* store statistics names and its offset in stats structure */\nstruct rte_ixgbe_xstats_name_off {\n\tchar name[RTE_ETH_XSTATS_NAME_SIZE];\n\tunsigned offset;\n};\n\nstatic const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {\n\t{\"rx_illegal_byte_err\", offsetof(struct ixgbe_hw_stats, errbc)},\n\t{\"rx_len_err\", offsetof(struct ixgbe_hw_stats, rlec)},\n\t{\"rx_undersize_count\", offsetof(struct ixgbe_hw_stats, ruc)},\n\t{\"rx_oversize_count\", offsetof(struct ixgbe_hw_stats, roc)},\n\t{\"rx_fragment_count\", offsetof(struct ixgbe_hw_stats, rfc)},\n\t{\"rx_jabber_count\", offsetof(struct ixgbe_hw_stats, rjc)},\n\t{\"l3_l4_xsum_error\", offsetof(struct ixgbe_hw_stats, xec)},\n\t{\"mac_local_fault\", offsetof(struct ixgbe_hw_stats, mlfc)},\n\t{\"mac_remote_fault\", offsetof(struct ixgbe_hw_stats, mrfc)},\n\t{\"mac_short_pkt_discard\", offsetof(struct ixgbe_hw_stats, mspdc)},\n\t{\"fccrc_error\", offsetof(struct ixgbe_hw_stats, fccrc)},\n\t{\"fcoe_drop\", offsetof(struct ixgbe_hw_stats, fcoerpdc)},\n\t{\"fc_last_error\", offsetof(struct ixgbe_hw_stats, fclast)},\n\t{\"rx_broadcast_packets\", offsetof(struct ixgbe_hw_stats, bprc)},\n\t{\"rx_phy_multicast_packets\", offsetof(struct ixgbe_hw_stats, mprc)},\n\t{\"mgmt_pkts_dropped\", offsetof(struct ixgbe_hw_stats, mngpdc)},\n\t{\"rx_crc_errors\", offsetof(struct ixgbe_hw_stats, crcerrs)},\n\t{\"fdir_match\", offsetof(struct ixgbe_hw_stats, fdirmatch)},\n\t{\"fdir_miss\", offsetof(struct ixgbe_hw_stats, fdirmiss)},\n\t{\"tx_flow_control_xon\", offsetof(struct ixgbe_hw_stats, lxontxc)},\n\t{\"rx_flow_control_xon\", offsetof(struct ixgbe_hw_stats, lxonrxc)},\n\t{\"tx_flow_control_xoff\", offsetof(struct ixgbe_hw_stats, lxofftxc)},\n\t{\"rx_flow_control_xoff\", offsetof(struct ixgbe_hw_stats, lxoffrxc)},\n};\n\n#define IXGBE_NB_XSTATS (sizeof(rte_ixgbe_stats_strings) /\t\\\n\t\tsizeof(rte_ixgbe_stats_strings[0]))\n\n/**\n * Atomically reads the link status information from global\n * structure rte_eth_dev.\n *\n * @param dev\n * - Pointer to the structure rte_eth_dev to read from.\n * - Pointer to the buffer to be saved with the link status.\n *\n * @return\n * - On success, zero.\n * - On failure, negative value.\n */\nstatic inline int\nrte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = link;\n\tstruct rte_eth_link *src = &(dev->data->dev_link);\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * Atomically writes the link status information into global\n * structure rte_eth_dev.\n *\n * @param dev\n * - Pointer to the structure rte_eth_dev to read from.\n * - Pointer to the buffer to be saved with the link status.\n *\n * @return\n * - On success, zero.\n * - On failure, negative value.\n */\nstatic inline int\nrte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = &(dev->data->dev_link);\n\tstruct rte_eth_link *src = link;\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.\n */\nstatic inline int\nixgbe_is_sfp(struct ixgbe_hw *hw)\n{\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_sfp_avago:\n\tcase ixgbe_phy_sfp_ftl:\n\tcase ixgbe_phy_sfp_intel:\n\tcase ixgbe_phy_sfp_unknown:\n\tcase ixgbe_phy_sfp_passive_tyco:\n\tcase ixgbe_phy_sfp_passive_unknown:\n\t\treturn 1;\n\tdefault:\n\t\treturn 0;\n\t}\n}\n\nstatic inline int32_t\nixgbe_pf_reset_hw(struct ixgbe_hw *hw)\n{\n\tuint32_t ctrl_ext;\n\tint32_t status;\n\n\tstatus = ixgbe_reset_hw(hw);\n\n\tctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);\n\t/* Set PF Reset Done bit so PF/VF Mail Ops can work */\n\tctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn status;\n}\n\nstatic inline void\nixgbe_enable_intr(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_interrupt *intr =\n\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/*\n * This function is based on ixgbe_disable_intr() in base/ixgbe.h.\n */\nstatic void\nixgbe_disable_intr(struct ixgbe_hw *hw)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);\n\t} else {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);\n\t}\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/*\n * This function resets queue statistics mapping registers.\n * From Niantic datasheet, Initialization of Statistics section:\n * \"...if software requires the queue counters, the RQSMR and TQSM registers\n * must be re-programmed following a device reset.\n */\nstatic void\nixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)\n{\n\tuint32_t i;\n\n\tfor(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);\n\t}\n}\n\n\nstatic int\nixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,\n\t\t\t\t uint16_t queue_id,\n\t\t\t\t uint8_t stat_idx,\n\t\t\t\t uint8_t is_rx)\n{\n#define QSM_REG_NB_BITS_PER_QMAP_FIELD 8\n#define NB_QMAP_FIELDS_PER_QSM_REG 4\n#define QMAP_FIELD_RESERVED_BITS_MASK 0x0f\n\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\tstruct ixgbe_stat_mapping_registers *stat_mappings =\n\t\tIXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);\n\tuint32_t qsmr_mask = 0;\n\tuint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;\n\tuint32_t q_map;\n\tuint8_t n, offset;\n\n\tif ((hw->mac.type != ixgbe_mac_82599EB) &&\n\t\t(hw->mac.type != ixgbe_mac_X540) &&\n\t\t(hw->mac.type != ixgbe_mac_X550) &&\n\t\t(hw->mac.type != ixgbe_mac_X550EM_x))\n\t\treturn -ENOSYS;\n\n\tPMD_INIT_LOG(DEBUG, \"Setting port %d, %s queue_id %d to stat index %d\",\n\t\t (int)(eth_dev->data->port_id), is_rx ? \"RX\" : \"TX\",\n\t\t queue_id, stat_idx);\n\n\tn = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);\n\tif (n >= IXGBE_NB_STAT_MAPPING_REGS) {\n\t\tPMD_INIT_LOG(ERR, \"Nb of stat mapping registers exceeded\");\n\t\treturn -EIO;\n\t}\n\toffset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);\n\n\t/* Now clear any previous stat_idx set */\n\tclearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);\n\tif (!is_rx)\n\t\tstat_mappings->tqsm[n] &= ~clearing_mask;\n\telse\n\t\tstat_mappings->rqsmr[n] &= ~clearing_mask;\n\n\tq_map = (uint32_t)stat_idx;\n\tq_map &= QMAP_FIELD_RESERVED_BITS_MASK;\n\tqsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);\n\tif (!is_rx)\n\t\tstat_mappings->tqsm[n] |= qsmr_mask;\n\telse\n\t\tstat_mappings->rqsmr[n] |= qsmr_mask;\n\n\tPMD_INIT_LOG(DEBUG, \"Set port %d, %s queue_id %d to stat index %d\",\n\t\t (int)(eth_dev->data->port_id), is_rx ? \"RX\" : \"TX\",\n\t\t queue_id, stat_idx);\n\tPMD_INIT_LOG(DEBUG, \"%s[%d] = 0x%08x\", is_rx ? \"RQSMR\" : \"TQSM\", n,\n\t\t is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);\n\n\t/* Now write the mapping in the appropriate register */\n\tif (is_rx) {\n\t\tPMD_INIT_LOG(DEBUG, \"Write 0x%x to RX IXGBE stat mapping reg:%d\",\n\t\t\t stat_mappings->rqsmr[n], n);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);\n\t}\n\telse {\n\t\tPMD_INIT_LOG(DEBUG, \"Write 0x%x to TX IXGBE stat mapping reg:%d\",\n\t\t\t stat_mappings->tqsm[n], n);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);\n\t}\n\treturn 0;\n}\n\nstatic void\nixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)\n{\n\tstruct ixgbe_stat_mapping_registers *stat_mappings =\n\t\tIXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint i;\n\n\t/* write whatever was in stat mapping table to the NIC */\n\tfor (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {\n\t\t/* rx */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);\n\n\t\t/* tx */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);\n\t}\n}\n\nstatic void\nixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)\n{\n\tuint8_t i;\n\tstruct ixgbe_dcb_tc_config *tc;\n\tuint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;\n\n\tdcb_config->num_tcs.pg_tcs = dcb_max_tc;\n\tdcb_config->num_tcs.pfc_tcs = dcb_max_tc;\n\tfor (i = 0; i < dcb_max_tc; i++) {\n\t\ttc = &dcb_config->tc_config[i];\n\t\ttc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;\n\t\ttc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =\n\t\t\t\t (uint8_t)(100/dcb_max_tc + (i & 1));\n\t\ttc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;\n\t\ttc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =\n\t\t\t\t (uint8_t)(100/dcb_max_tc + (i & 1));\n\t\ttc->pfc = ixgbe_dcb_pfc_disabled;\n\t}\n\n\t/* Initialize default user to priority mapping, UPx->TC0 */\n\ttc = &dcb_config->tc_config[0];\n\ttc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;\n\ttc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;\n\tfor (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {\n\t\tdcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;\n\t\tdcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;\n\t}\n\tdcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;\n\tdcb_config->pfc_mode_enable = false;\n\tdcb_config->vt_mode = true;\n\tdcb_config->round_robin_enable = false;\n\t/* support all DCB capabilities in 82599 */\n\tdcb_config->support.capabilities = 0xFF;\n\n\t/*we only support 4 Tcs for X540, X550 */\n\tif (hw->mac.type == ixgbe_mac_X540 ||\n\t\thw->mac.type == ixgbe_mac_X550 ||\n\t\thw->mac.type == ixgbe_mac_X550EM_x) {\n\t\tdcb_config->num_tcs.pg_tcs = 4;\n\t\tdcb_config->num_tcs.pfc_tcs = 4;\n\t}\n}\n\n/*\n * Ensure that all locks are released before first NVM or PHY access\n */\nstatic void\nixgbe_swfw_lock_reset(struct ixgbe_hw *hw)\n{\n\tuint16_t mask;\n\n\t/*\n\t * Phy lock should not fail in this early stage. If this is the case,\n\t * it is due to an improper exit of the application.\n\t * So force the release of the faulty lock. Release of common lock\n\t * is done automatically by swfw_sync function.\n\t */\n\tmask = IXGBE_GSSR_PHY0_SM << hw->bus.func;\n\tif (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {\n\t\tPMD_DRV_LOG(DEBUG, \"SWFW phy%d lock released\", hw->bus.func);\n\t}\n\tixgbe_release_swfw_semaphore(hw, mask);\n\n\t/*\n\t * These ones are more tricky since they are common to all ports; but\n\t * swfw_sync retries last long enough (1s) to be almost sure that if\n\t * lock can not be taken it is due to an improper lock of the\n\t * semaphore.\n\t */\n\tmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;\n\tif (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {\n\t\tPMD_DRV_LOG(DEBUG, \"SWFW common locks released\");\n\t}\n\tixgbe_release_swfw_semaphore(hw, mask);\n}\n\n/*\n * This function is based on code in ixgbe_attach() in base/ixgbe.c.\n * It returns 0 on success.\n */\nstatic int\neth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)\n{\n\tstruct rte_pci_device *pci_dev;\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\tstruct ixgbe_vfta * shadow_vfta =\n\t\tIXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);\n\tstruct ixgbe_hwstrip *hwstrip =\n\t\tIXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);\n\tstruct ixgbe_dcb_config *dcb_config =\n\t\tIXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);\n\tstruct ixgbe_filter_info *filter_info =\n\t\tIXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);\n\tuint32_t ctrl_ext;\n\tuint16_t csum;\n\tint diag, i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\teth_dev->dev_ops = &ixgbe_eth_dev_ops;\n\teth_dev->rx_pkt_burst = &ixgbe_recv_pkts;\n\teth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;\n\n\t/*\n\t * For secondary processes, we don't initialise any further as primary\n\t * has already done this work. Only check we don't need a different\n\t * RX and TX function.\n\t */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY){\n\t\tstruct ixgbe_tx_queue *txq;\n\t\t/* TX queue function in primary, set by last queue initialized\n\t\t * Tx queue may not initialized by primary process */\n\t\tif (eth_dev->data->tx_queues) {\n\t\t\ttxq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];\n\t\t\tixgbe_set_tx_function(eth_dev, txq);\n\t\t} else {\n\t\t\t/* Use default TX function if we get here */\n\t\t\tPMD_INIT_LOG(NOTICE, \"No TX queues configured yet. \"\n\t\t\t \"Using default TX function.\");\n\t\t}\n\n\t\tixgbe_set_rx_function(eth_dev);\n\n\t\treturn 0;\n\t}\n\tpci_dev = eth_dev->pci_dev;\n\n\t/* Vendor and Device ID need to be set before init of shared code */\n\thw->device_id = pci_dev->id.device_id;\n\thw->vendor_id = pci_dev->id.vendor_id;\n\thw->hw_addr = (void *)pci_dev->mem_resource[0].addr;\n\thw->allow_unsupported_sfp = 1;\n\n\t/* Initialize the shared code (base driver) */\n#ifdef RTE_NIC_BYPASS\n\tdiag = ixgbe_bypass_init_shared_code(hw);\n#else\n\tdiag = ixgbe_init_shared_code(hw);\n#endif /* RTE_NIC_BYPASS */\n\n\tif (diag != IXGBE_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Shared code init failed: %d\", diag);\n\t\treturn -EIO;\n\t}\n\n\t/* pick up the PCI bus settings for reporting later */\n\tixgbe_get_bus_info(hw);\n\n\t/* Unlock any pending hardware semaphore */\n\tixgbe_swfw_lock_reset(hw);\n\n\t/* Initialize DCB configuration*/\n\tmemset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));\n\tixgbe_dcb_init(hw,dcb_config);\n\t/* Get Hardware Flow Control setting */\n\thw->fc.requested_mode = ixgbe_fc_full;\n\thw->fc.current_mode = ixgbe_fc_full;\n\thw->fc.pause_time = IXGBE_FC_PAUSE;\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\thw->fc.low_water[i] = IXGBE_FC_LO;\n\t\thw->fc.high_water[i] = IXGBE_FC_HI;\n\t}\n\thw->fc.send_xon = 1;\n\n\t/* Make sure we have a good EEPROM before we read from it */\n\tdiag = ixgbe_validate_eeprom_checksum(hw, &csum);\n\tif (diag != IXGBE_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"The EEPROM checksum is not valid: %d\", diag);\n\t\treturn -EIO;\n\t}\n\n#ifdef RTE_NIC_BYPASS\n\tdiag = ixgbe_bypass_init_hw(hw);\n#else\n\tdiag = ixgbe_init_hw(hw);\n#endif /* RTE_NIC_BYPASS */\n\n\t/*\n\t * Devices with copper phys will fail to initialise if ixgbe_init_hw()\n\t * is called too soon after the kernel driver unbinding/binding occurs.\n\t * The failure occurs in ixgbe_identify_phy_generic() for all devices,\n\t * but for non-copper devies, ixgbe_identify_sfp_module_generic() is\n\t * also called. See ixgbe_identify_phy_82599(). The reason for the\n\t * failure is not known, and only occuts when virtualisation features\n\t * are disabled in the bios. A delay of 100ms was found to be enough by\n\t * trial-and-error, and is doubled to be safe.\n\t */\n\tif (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {\n\t\trte_delay_ms(200);\n\t\tdiag = ixgbe_init_hw(hw);\n\t}\n\n\tif (diag == IXGBE_ERR_EEPROM_VERSION) {\n\t\tPMD_INIT_LOG(ERR, \"This device is a pre-production adapter/\"\n\t\t \"LOM. Please be aware there may be issues associated \"\n\t\t \"with your hardware.\");\n\t\tPMD_INIT_LOG(ERR, \"If you are experiencing problems \"\n\t\t \"please contact your Intel or hardware representative \"\n\t\t \"who provided you with this hardware.\");\n\t} else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)\n\t\tPMD_INIT_LOG(ERR, \"Unsupported SFP+ Module\");\n\tif (diag) {\n\t\tPMD_INIT_LOG(ERR, \"Hardware Initialization Failure: %d\", diag);\n\t\treturn -EIO;\n\t}\n\n\t/* Reset the hw statistics */\n\tixgbe_dev_stats_reset(eth_dev);\n\n\t/* disable interrupt */\n\tixgbe_disable_intr(hw);\n\n\t/* reset mappings for queue statistics hw counters*/\n\tixgbe_reset_qstat_mappings(hw);\n\n\t/* Allocate memory for storing MAC addresses */\n\teth_dev->data->mac_addrs = rte_zmalloc(\"ixgbe\", ETHER_ADDR_LEN *\n\t\t\thw->mac.num_rar_entries, 0);\n\tif (eth_dev->data->mac_addrs == NULL) {\n\t\tPMD_INIT_LOG(ERR,\n\t\t\t\"Failed to allocate %u bytes needed to store \"\n\t\t\t\"MAC addresses\",\n\t\t\tETHER_ADDR_LEN * hw->mac.num_rar_entries);\n\t\treturn -ENOMEM;\n\t}\n\t/* Copy the permanent MAC address */\n\tether_addr_copy((struct ether_addr *) hw->mac.perm_addr,\n\t\t\tð_dev->data->mac_addrs[0]);\n\n\t/* Allocate memory for storing hash filter MAC addresses */\n\teth_dev->data->hash_mac_addrs = rte_zmalloc(\"ixgbe\", ETHER_ADDR_LEN *\n\t\t\tIXGBE_VMDQ_NUM_UC_MAC, 0);\n\tif (eth_dev->data->hash_mac_addrs == NULL) {\n\t\tPMD_INIT_LOG(ERR,\n\t\t\t\"Failed to allocate %d bytes needed to store MAC addresses\",\n\t\t\tETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);\n\t\treturn -ENOMEM;\n\t}\n\n\t/* initialize the vfta */\n\tmemset(shadow_vfta, 0, sizeof(*shadow_vfta));\n\n\t/* initialize the hw strip bitmap*/\n\tmemset(hwstrip, 0, sizeof(*hwstrip));\n\n\t/* initialize PF if max_vfs not zero */\n\tixgbe_pf_host_init(eth_dev);\n\n\tctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);\n\t/* let hardware know driver is loaded */\n\tctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;\n\t/* Set PF Reset Done bit so PF/VF Mail Ops can work */\n\tctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\tif (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)\n\t\tPMD_INIT_LOG(DEBUG, \"MAC: %d, PHY: %d, SFP+: %d\",\n\t\t\t (int) hw->mac.type, (int) hw->phy.type,\n\t\t\t (int) hw->phy.sfp_type);\n\telse\n\t\tPMD_INIT_LOG(DEBUG, \"MAC: %d, PHY: %d\",\n\t\t\t (int) hw->mac.type, (int) hw->phy.type);\n\n\tPMD_INIT_LOG(DEBUG, \"port %d vendorID=0x%x deviceID=0x%x\",\n\t\t\teth_dev->data->port_id, pci_dev->id.vendor_id,\n\t\t\tpci_dev->id.device_id);\n\n\t/* enable support intr */\n\tixgbe_enable_intr(eth_dev);\n\n\t/* initialize 5tuple filter list */\n\tTAILQ_INIT(&filter_info->fivetuple_list);\n\tmemset(filter_info->fivetuple_mask, 0,\n\t\tsizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);\n\n\treturn 0;\n}\n\nstatic int\neth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)\n{\n\tstruct rte_pci_device *pci_dev;\n\tstruct ixgbe_hw *hw;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn -EPERM;\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\tpci_dev = eth_dev->pci_dev;\n\n\tif (hw->adapter_stopped == 0)\n\t\tixgbe_dev_close(eth_dev);\n\n\teth_dev->dev_ops = NULL;\n\teth_dev->rx_pkt_burst = NULL;\n\teth_dev->tx_pkt_burst = NULL;\n\n\t/* Unlock any pending hardware semaphore */\n\tixgbe_swfw_lock_reset(hw);\n\n\t/* disable uio intr before callback unregister */\n\trte_intr_disable(&(pci_dev->intr_handle));\n\trte_intr_callback_unregister(&(pci_dev->intr_handle),\n\t\tixgbe_dev_interrupt_handler, (void *)eth_dev);\n\n\t/* uninitialize PF if max_vfs not zero */\n\tixgbe_pf_host_uninit(eth_dev);\n\n\trte_free(eth_dev->data->mac_addrs);\n\teth_dev->data->mac_addrs = NULL;\n\n\trte_free(eth_dev->data->hash_mac_addrs);\n\teth_dev->data->hash_mac_addrs = NULL;\n\n\treturn 0;\n}\n\n/*\n * Negotiate mailbox API version with the PF.\n * After reset API version is always set to the basic one (ixgbe_mbox_api_10).\n * Then we try to negotiate starting with the most recent one.\n * If all negotiation attempts fail, then we will proceed with\n * the default one (ixgbe_mbox_api_10).\n */\nstatic void\nixgbevf_negotiate_api(struct ixgbe_hw *hw)\n{\n\tint32_t i;\n\n\t/* start with highest supported, proceed down */\n\tstatic const enum ixgbe_pfvf_api_rev sup_ver[] = {\n\t\tixgbe_mbox_api_11,\n\t\tixgbe_mbox_api_10,\n\t};\n\n\tfor (i = 0;\n\t\t\ti != RTE_DIM(sup_ver) &&\n\t\t\tixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;\n\t\t\ti++)\n\t\t;\n}\n\nstatic void\ngenerate_random_mac_addr(struct ether_addr *mac_addr)\n{\n\tuint64_t random;\n\n\t/* Set Organizationally Unique Identifier (OUI) prefix. */\n\tmac_addr->addr_bytes[0] = 0x00;\n\tmac_addr->addr_bytes[1] = 0x09;\n\tmac_addr->addr_bytes[2] = 0xC0;\n\t/* Force indication of locally assigned MAC address. */\n\tmac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;\n\t/* Generate the last 3 bytes of the MAC address with a random number. */\n\trandom = rte_rand();\n\tmemcpy(&mac_addr->addr_bytes[3], &random, 3);\n}\n\n/*\n * Virtual Function device init\n */\nstatic int\neth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)\n{\n\tint diag;\n\tuint32_t tc, tcs;\n\tstruct rte_pci_device *pci_dev;\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\tstruct ixgbe_vfta * shadow_vfta =\n\t\tIXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);\n\tstruct ixgbe_hwstrip *hwstrip =\n\t\tIXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);\n\tstruct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\teth_dev->dev_ops = &ixgbevf_eth_dev_ops;\n\teth_dev->rx_pkt_burst = &ixgbe_recv_pkts;\n\teth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;\n\n\t/* for secondary processes, we don't initialise any further as primary\n\t * has already done this work. Only check we don't need a different\n\t * RX function */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY){\n\t\tif (eth_dev->data->scattered_rx)\n\t\t\teth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;\n\t\treturn 0;\n\t}\n\n\tpci_dev = eth_dev->pci_dev;\n\n\thw->device_id = pci_dev->id.device_id;\n\thw->vendor_id = pci_dev->id.vendor_id;\n\thw->hw_addr = (void *)pci_dev->mem_resource[0].addr;\n\n\t/* initialize the vfta */\n\tmemset(shadow_vfta, 0, sizeof(*shadow_vfta));\n\n\t/* initialize the hw strip bitmap*/\n\tmemset(hwstrip, 0, sizeof(*hwstrip));\n\n\t/* Initialize the shared code (base driver) */\n\tdiag = ixgbe_init_shared_code(hw);\n\tif (diag != IXGBE_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Shared code init failed for ixgbevf: %d\", diag);\n\t\treturn -EIO;\n\t}\n\n\t/* init_mailbox_params */\n\thw->mbx.ops.init_params(hw);\n\n\t/* Reset the hw statistics */\n\tixgbevf_dev_stats_reset(eth_dev);\n\n\t/* Disable the interrupts for VF */\n\tixgbevf_intr_disable(hw);\n\n\thw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */\n\tdiag = hw->mac.ops.reset_hw(hw);\n\n\t/*\n\t * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when\n\t * the underlying PF driver has not assigned a MAC address to the VF.\n\t * In this case, assign a random MAC address.\n\t */\n\tif ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {\n\t\tPMD_INIT_LOG(ERR, \"VF Initialization Failure: %d\", diag);\n\t\treturn (diag);\n\t}\n\n\t/* negotiate mailbox API version to use with the PF. */\n\tixgbevf_negotiate_api(hw);\n\n\t/* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */\n\tixgbevf_get_queues(hw, &tcs, &tc);\n\n\t/* Allocate memory for storing MAC addresses */\n\teth_dev->data->mac_addrs = rte_zmalloc(\"ixgbevf\", ETHER_ADDR_LEN *\n\t\t\thw->mac.num_rar_entries, 0);\n\tif (eth_dev->data->mac_addrs == NULL) {\n\t\tPMD_INIT_LOG(ERR,\n\t\t\t\"Failed to allocate %u bytes needed to store \"\n\t\t\t\"MAC addresses\",\n\t\t\tETHER_ADDR_LEN * hw->mac.num_rar_entries);\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Generate a random MAC address, if none was assigned by PF. */\n\tif (is_zero_ether_addr(perm_addr)) {\n\t\tgenerate_random_mac_addr(perm_addr);\n\t\tdiag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);\n\t\tif (diag) {\n\t\t\trte_free(eth_dev->data->mac_addrs);\n\t\t\teth_dev->data->mac_addrs = NULL;\n\t\t\treturn diag;\n\t\t}\n\t\tPMD_INIT_LOG(INFO, \"\\tVF MAC address not assigned by Host PF\");\n\t\tPMD_INIT_LOG(INFO, \"\\tAssign randomly generated MAC address \"\n\t\t\t \"%02x:%02x:%02x:%02x:%02x:%02x\",\n\t\t\t perm_addr->addr_bytes[0],\n\t\t\t perm_addr->addr_bytes[1],\n\t\t\t perm_addr->addr_bytes[2],\n\t\t\t perm_addr->addr_bytes[3],\n\t\t\t perm_addr->addr_bytes[4],\n\t\t\t perm_addr->addr_bytes[5]);\n\t}\n\n\t/* Copy the permanent MAC address */\n\tether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);\n\n\t/* reset the hardware with the new settings */\n\tdiag = hw->mac.ops.start_hw(hw);\n\tswitch (diag) {\n\t\tcase 0:\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tPMD_INIT_LOG(ERR, \"VF Initialization Failure: %d\", diag);\n\t\t\treturn (-EIO);\n\t}\n\n\tPMD_INIT_LOG(DEBUG, \"port %d vendorID=0x%x deviceID=0x%x mac.type=%s\",\n\t\t eth_dev->data->port_id, pci_dev->id.vendor_id,\n\t\t pci_dev->id.device_id, \"ixgbe_mac_82599_vf\");\n\n\treturn 0;\n}\n\n/* Virtual Function device uninit */\n\nstatic int\neth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)\n{\n\tstruct ixgbe_hw *hw;\n\tunsigned i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn -EPERM;\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\n\tif (hw->adapter_stopped == 0)\n\t\tixgbevf_dev_close(eth_dev);\n\n\teth_dev->dev_ops = NULL;\n\teth_dev->rx_pkt_burst = NULL;\n\teth_dev->tx_pkt_burst = NULL;\n\n\t/* Disable the interrupts for VF */\n\tixgbevf_intr_disable(hw);\n\n\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n\t\tixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);\n\t\teth_dev->data->rx_queues[i] = NULL;\n\t}\n\teth_dev->data->nb_rx_queues = 0;\n\n\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n\t\tixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);\n\t\teth_dev->data->tx_queues[i] = NULL;\n\t}\n\teth_dev->data->nb_tx_queues = 0;\n\n\trte_free(eth_dev->data->mac_addrs);\n\teth_dev->data->mac_addrs = NULL;\n\n\treturn 0;\n}\n\nstatic struct eth_driver rte_ixgbe_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_ixgbe_pmd\",\n\t\t.id_table = pci_id_ixgbe_map,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |\n\t\t\tRTE_PCI_DRV_DETACHABLE,\n\t},\n\t.eth_dev_init = eth_ixgbe_dev_init,\n\t.eth_dev_uninit = eth_ixgbe_dev_uninit,\n\t.dev_private_size = sizeof(struct ixgbe_adapter),\n};\n\n/*\n * virtual function driver struct\n */\nstatic struct eth_driver rte_ixgbevf_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_ixgbevf_pmd\",\n\t\t.id_table = pci_id_ixgbevf_map,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,\n\t},\n\t.eth_dev_init = eth_ixgbevf_dev_init,\n\t.eth_dev_uninit = eth_ixgbevf_dev_uninit,\n\t.dev_private_size = sizeof(struct ixgbe_adapter),\n};\n\n/*\n * Driver initialization routine.\n * Invoked once at EAL init time.\n * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.\n */\nstatic int\nrte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\trte_eth_driver_register(&rte_ixgbe_pmd);\n\treturn 0;\n}\n\n/*\n * VF Driver initialization routine.\n * Invoked one at EAL init time.\n * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.\n */\nstatic int\nrte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\trte_eth_driver_register(&rte_ixgbevf_pmd);\n\treturn (0);\n}\n\nstatic int\nixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vfta * shadow_vfta =\n\t\tIXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);\n\tuint32_t vfta;\n\tuint32_t vid_idx;\n\tuint32_t vid_bit;\n\n\tvid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);\n\tvid_bit = (uint32_t) (1 << (vlan_id & 0x1F));\n\tvfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));\n\tif (on)\n\t\tvfta |= vid_bit;\n\telse\n\t\tvfta &= ~vid_bit;\n\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);\n\n\t/* update local VFTA copy */\n\tshadow_vfta->vfta[vid_idx] = vfta;\n\n\treturn 0;\n}\n\nstatic void\nixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)\n{\n\tif (on)\n\t\tixgbe_vlan_hw_strip_enable(dev, queue);\n\telse\n\t\tixgbe_vlan_hw_strip_disable(dev, queue);\n}\n\nstatic void\nixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/* Only the high 16-bits is valid */\n\tIXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);\n}\n\nvoid\nixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t vlnctrl;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* Filter Table Disable */\n\tvlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n\tvlnctrl &= ~IXGBE_VLNCTRL_VFE;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);\n}\n\nvoid\nixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vfta * shadow_vfta =\n\t\tIXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);\n\tuint32_t vlnctrl;\n\tuint16_t i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* Filter Table Enable */\n\tvlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n\tvlnctrl &= ~IXGBE_VLNCTRL_CFIEN;\n\tvlnctrl |= IXGBE_VLNCTRL_VFE;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);\n\n\t/* write whatever is in local vfta copy */\n\tfor (i = 0; i < IXGBE_VFTA_SIZE; i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);\n}\n\nstatic void\nixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)\n{\n\tstruct ixgbe_hwstrip *hwstrip =\n\t\tIXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);\n\n\tif(queue >= IXGBE_MAX_RX_QUEUE_NUM)\n\t\treturn;\n\n\tif (on)\n\t\tIXGBE_SET_HWSTRIP(hwstrip, queue);\n\telse\n\t\tIXGBE_CLEAR_HWSTRIP(hwstrip, queue);\n}\n\nstatic void\nixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t ctrl;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\t/* No queue level support */\n\t\tPMD_INIT_LOG(NOTICE, \"82598EB not support queue level hw strip\");\n\t\treturn;\n\t}\n\telse {\n\t\t/* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */\n\t\tctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));\n\t\tctrl &= ~IXGBE_RXDCTL_VME;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);\n\t}\n\t/* record those setting for HW strip per queue */\n\tixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);\n}\n\nstatic void\nixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t ctrl;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\t/* No queue level supported */\n\t\tPMD_INIT_LOG(NOTICE, \"82598EB not support queue level hw strip\");\n\t\treturn;\n\t}\n\telse {\n\t\t/* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */\n\t\tctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));\n\t\tctrl |= IXGBE_RXDCTL_VME;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);\n\t}\n\t/* record those setting for HW strip per queue */\n\tixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);\n}\n\nvoid\nixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t ctrl;\n\tuint16_t i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\tctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n\t\tctrl &= ~IXGBE_VLNCTRL_VME;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);\n\t}\n\telse {\n\t\t/* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */\n\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\t\tctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));\n\t\t\tctrl &= ~IXGBE_RXDCTL_VME;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);\n\n\t\t\t/* record those setting for HW strip per queue */\n\t\t\tixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);\n\t\t}\n\t}\n}\n\nvoid\nixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t ctrl;\n\tuint16_t i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\tctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n\t\tctrl |= IXGBE_VLNCTRL_VME;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);\n\t}\n\telse {\n\t\t/* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */\n\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\t\tctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));\n\t\t\tctrl |= IXGBE_RXDCTL_VME;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);\n\n\t\t\t/* record those setting for HW strip per queue */\n\t\t\tixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);\n\t\t}\n\t}\n}\n\nstatic void\nixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t ctrl;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* DMATXCTRL: Geric Double VLAN Disable */\n\tctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);\n\tctrl &= ~IXGBE_DMATXCTL_GDV;\n\tIXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);\n\n\t/* CTRL_EXT: Global Double VLAN Disable */\n\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);\n\tctrl &= ~IXGBE_EXTENDED_VLAN;\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);\n\n}\n\nstatic void\nixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t ctrl;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* DMATXCTRL: Geric Double VLAN Enable */\n\tctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);\n\tctrl |= IXGBE_DMATXCTL_GDV;\n\tIXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);\n\n\t/* CTRL_EXT: Global Double VLAN Enable */\n\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);\n\tctrl |= IXGBE_EXTENDED_VLAN;\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);\n\n\t/*\n\t * VET EXT field in the EXVET register = 0x8100 by default\n\t * So no need to change. Same to VT field of DMATXCTL register\n\t */\n}\n\nstatic void\nixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)\n{\n\tif(mask & ETH_VLAN_STRIP_MASK){\n\t\tif (dev->data->dev_conf.rxmode.hw_vlan_strip)\n\t\t\tixgbe_vlan_hw_strip_enable_all(dev);\n\t\telse\n\t\t\tixgbe_vlan_hw_strip_disable_all(dev);\n\t}\n\n\tif(mask & ETH_VLAN_FILTER_MASK){\n\t\tif (dev->data->dev_conf.rxmode.hw_vlan_filter)\n\t\t\tixgbe_vlan_hw_filter_enable(dev);\n\t\telse\n\t\t\tixgbe_vlan_hw_filter_disable(dev);\n\t}\n\n\tif(mask & ETH_VLAN_EXTEND_MASK){\n\t\tif (dev->data->dev_conf.rxmode.hw_vlan_extend)\n\t\t\tixgbe_vlan_hw_extend_enable(dev);\n\t\telse\n\t\t\tixgbe_vlan_hw_extend_disable(dev);\n\t}\n}\n\nstatic void\nixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\t/* VLNCTRL: enable vlan filtering and allow all vlan tags through */\n\tuint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n\tvlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */\n\tIXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);\n}\n\nstatic int\nixgbe_dev_configure(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_interrupt *intr =\n\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\tstruct ixgbe_adapter *adapter =\n\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* set flag to update link status after init */\n\tintr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;\n\n\t/*\n\t * Initialize to TRUE. If any of Rx queues doesn't meet the bulk\n\t * allocation or vector Rx preconditions we will reset it.\n\t */\n\tadapter->rx_bulk_alloc_allowed = true;\n\tadapter->rx_vec_allowed = true;\n\n\treturn 0;\n}\n\n/*\n * Configure device link speed and setup link.\n * It returns 0 on success.\n */\nstatic int\nixgbe_dev_start(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);\n\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n#ifdef RTE_NEXT_ABI\n\tuint32_t intr_vector = 0;\n#endif\n\tint err, link_up = 0, negotiate = 0;\n\tuint32_t speed = 0;\n\tint mask = 0;\n\tint status;\n\tuint16_t vf, idx;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* IXGBE devices don't support half duplex */\n\tif ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&\n\t\t\t(dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {\n\t\tPMD_INIT_LOG(ERR, \"Invalid link_duplex (%hu) for port %hhu\",\n\t\t\t dev->data->dev_conf.link_duplex,\n\t\t\t dev->data->port_id);\n\t\treturn -EINVAL;\n\t}\n\n\t/* stop adapter */\n\thw->adapter_stopped = 0;\n\tixgbe_stop_adapter(hw);\n\n\t/* reinitialize adapter\n\t * this calls reset and start */\n\tstatus = ixgbe_pf_reset_hw(hw);\n\tif (status != 0)\n\t\treturn -1;\n\thw->mac.ops.start_hw(hw);\n\thw->mac.get_link_status = true;\n\n\t/* configure PF module if SRIOV enabled */\n\tixgbe_pf_host_configure(dev);\n\n#ifdef RTE_NEXT_ABI\n\t/* check and configure queue intr-vector mapping */\n\tif (dev->data->dev_conf.intr_conf.rxq != 0)\n\t\tintr_vector = dev->data->nb_rx_queues;\n\n\tif (rte_intr_efd_enable(intr_handle, intr_vector))\n\t\treturn -1;\n\n\tif (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {\n\t\tintr_handle->intr_vec =\n\t\t\trte_zmalloc(\"intr_vec\",\n\t\t\t\t dev->data->nb_rx_queues * sizeof(int),\n\t\t\t\t 0);\n\t\tif (intr_handle->intr_vec == NULL) {\n\t\t\tPMD_INIT_LOG(ERR, \"Failed to allocate %d rx_queues\"\n\t\t\t\t \" intr_vec\\n\", dev->data->nb_rx_queues);\n\t\t\treturn -ENOMEM;\n\t\t}\n\t}\n#endif\n\n\t/* confiugre msix for sleep until rx interrupt */\n\tixgbe_configure_msix(dev);\n\n\t/* initialize transmission unit */\n\tixgbe_dev_tx_init(dev);\n\n\t/* This can fail when allocating mbufs for descriptor rings */\n\terr = ixgbe_dev_rx_init(dev);\n\tif (err) {\n\t\tPMD_INIT_LOG(ERR, \"Unable to initialize RX hardware\");\n\t\tgoto error;\n\t}\n\n\terr = ixgbe_dev_rxtx_start(dev);\n\tif (err < 0) {\n\t\tPMD_INIT_LOG(ERR, \"Unable to start rxtx queues\");\n\t\tgoto error;\n\t}\n\n\t/* Skip link setup if loopback mode is enabled for 82599. */\n\tif (hw->mac.type == ixgbe_mac_82599EB &&\n\t\t\tdev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)\n\t\tgoto skip_link_setup;\n\n\tif (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {\n\t\terr = hw->mac.ops.setup_sfp(hw);\n\t\tif (err)\n\t\t\tgoto error;\n\t}\n\n\tif (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {\n\t\t/* Turn on the copper */\n\t\tixgbe_set_phy_power(hw, true);\n\t} else {\n\t\t/* Turn on the laser */\n\t\tixgbe_enable_tx_laser(hw);\n\t}\n\n\terr = ixgbe_check_link(hw, &speed, &link_up, 0);\n\tif (err)\n\t\tgoto error;\n\tdev->data->dev_link.link_status = link_up;\n\n\terr = ixgbe_get_link_capabilities(hw, &speed, &negotiate);\n\tif (err)\n\t\tgoto error;\n\n\tswitch(dev->data->dev_conf.link_speed) {\n\tcase ETH_LINK_SPEED_AUTONEG:\n\t\tspeed = (hw->mac.type != ixgbe_mac_82598EB) ?\n\t\t\t\tIXGBE_LINK_SPEED_82599_AUTONEG :\n\t\t\t\tIXGBE_LINK_SPEED_82598_AUTONEG;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_100:\n\t\t/*\n\t\t * Invalid for 82598 but error will be detected by\n\t\t * ixgbe_setup_link()\n\t\t */\n\t\tspeed = IXGBE_LINK_SPEED_100_FULL;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_1000:\n\t\tspeed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\tbreak;\n\tcase ETH_LINK_SPEED_10000:\n\t\tspeed = IXGBE_LINK_SPEED_10GB_FULL;\n\t\tbreak;\n\tdefault:\n\t\tPMD_INIT_LOG(ERR, \"Invalid link_speed (%hu) for port %hhu\",\n\t\t\t dev->data->dev_conf.link_speed,\n\t\t\t dev->data->port_id);\n\t\tgoto error;\n\t}\n\n\terr = ixgbe_setup_link(hw, speed, link_up);\n\tif (err)\n\t\tgoto error;\n\nskip_link_setup:\n\n\t/* check if lsc interrupt is enabled */\n\tif (dev->data->dev_conf.intr_conf.lsc != 0) {\n\t\tif (rte_intr_allow_others(intr_handle)) {\n\t\t\trte_intr_callback_register(intr_handle,\n\t\t\t\t\t\t ixgbe_dev_interrupt_handler,\n\t\t\t\t\t\t (void *)dev);\n\t\t\tixgbe_dev_lsc_interrupt_setup(dev);\n\t\t} else\n\t\t\tPMD_INIT_LOG(INFO, \"lsc won't enable because of\"\n\t\t\t\t \" no intr multiplex\\n\");\n\t}\n\n#ifdef RTE_NEXT_ABI\n\t/* check if rxq interrupt is enabled */\n\tif (dev->data->dev_conf.intr_conf.rxq != 0)\n\t\tixgbe_dev_rxq_interrupt_setup(dev);\n#endif\n\n\t/* enable uio/vfio intr/eventfd mapping */\n\trte_intr_enable(intr_handle);\n\n\t/* resume enabled intr since hw reset */\n\tixgbe_enable_intr(dev);\n\n\tmask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \\\n\t\tETH_VLAN_EXTEND_MASK;\n\tixgbe_vlan_offload_set(dev, mask);\n\n\tif (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {\n\t\t/* Enable vlan filtering for VMDq */\n\t\tixgbe_vmdq_vlan_hw_filter_enable(dev);\n\t}\n\n\t/* Configure DCB hw */\n\tixgbe_configure_dcb(dev);\n\n\tif (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {\n\t\terr = ixgbe_fdir_configure(dev);\n\t\tif (err)\n\t\t\tgoto error;\n\t}\n\n\t/* Restore vf rate limit */\n\tif (vfinfo != NULL) {\n\t\tfor (vf = 0; vf < dev->pci_dev->max_vfs; vf++)\n\t\t\tfor (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)\n\t\t\t\tif (vfinfo[vf].tx_rate[idx] != 0)\n\t\t\t\t\tixgbe_set_vf_rate_limit(dev, vf,\n\t\t\t\t\t\tvfinfo[vf].tx_rate[idx],\n\t\t\t\t\t\t1 << idx);\n\t}\n\n\tixgbe_restore_statistics_mapping(dev);\n\n\treturn (0);\n\nerror:\n\tPMD_INIT_LOG(ERR, \"failure in ixgbe_dev_start(): %d\", err);\n\tixgbe_dev_clear_queues(dev);\n\treturn -EIO;\n}\n\n/*\n * Stop device: disable rx and tx functions to allow for reconfiguring.\n */\nstatic void\nixgbe_dev_stop(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_link link;\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);\n\tstruct ixgbe_filter_info *filter_info =\n\t\tIXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tstruct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;\n\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n\tint vf;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* disable interrupts */\n\tixgbe_disable_intr(hw);\n\n\t/* disable intr eventfd mapping */\n\trte_intr_disable(intr_handle);\n\n\t/* reset the NIC */\n\tixgbe_pf_reset_hw(hw);\n\thw->adapter_stopped = 0;\n\n\t/* stop adapter */\n\tixgbe_stop_adapter(hw);\n\n\tfor (vf = 0; vfinfo != NULL &&\n\t\t vf < dev->pci_dev->max_vfs; vf++)\n\t\tvfinfo[vf].clear_to_send = false;\n\n\tif (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {\n\t\t/* Turn off the copper */\n\t\tixgbe_set_phy_power(hw, false);\n\t} else {\n\t\t/* Turn off the laser */\n\t\tixgbe_disable_tx_laser(hw);\n\t}\n\n\tixgbe_dev_clear_queues(dev);\n\n\t/* Clear stored conf */\n\tdev->data->scattered_rx = 0;\n\tdev->data->lro = 0;\n\n\t/* Clear recorded link status */\n\tmemset(&link, 0, sizeof(link));\n\trte_ixgbe_dev_atomic_write_link_status(dev, &link);\n\n\t/* Remove all ntuple filters of the device */\n\tfor (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);\n\t p_5tuple != NULL; p_5tuple = p_5tuple_next) {\n\t\tp_5tuple_next = TAILQ_NEXT(p_5tuple, entries);\n\t\tTAILQ_REMOVE(&filter_info->fivetuple_list,\n\t\t\t p_5tuple, entries);\n\t\trte_free(p_5tuple);\n\t}\n\tmemset(filter_info->fivetuple_mask, 0,\n\t\tsizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);\n\n#ifdef RTE_NEXT_ABI\n\t/* Clean datapath event and queue/vec mapping */\n\trte_intr_efd_disable(intr_handle);\n\tif (intr_handle->intr_vec != NULL) {\n\t\trte_free(intr_handle->intr_vec);\n\t\tintr_handle->intr_vec = NULL;\n\t}\n#endif\n}\n\n/*\n * Set device link up: enable tx.\n */\nstatic int\nixgbe_dev_set_link_up(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tif (hw->mac.type == ixgbe_mac_82599EB) {\n#ifdef RTE_NIC_BYPASS\n\t\tif (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {\n\t\t\t/* Not suported in bypass mode */\n\t\t\tPMD_INIT_LOG(ERR, \"Set link up is not supported \"\n\t\t\t\t \"by device id 0x%x\", hw->device_id);\n\t\t\treturn -ENOTSUP;\n\t\t}\n#endif\n\t}\n\n\tif (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {\n\t\t/* Turn on the copper */\n\t\tixgbe_set_phy_power(hw, true);\n\t} else {\n\t\t/* Turn on the laser */\n\t\tixgbe_enable_tx_laser(hw);\n\t}\n\n\treturn 0;\n}\n\n/*\n * Set device link down: disable tx.\n */\nstatic int\nixgbe_dev_set_link_down(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tif (hw->mac.type == ixgbe_mac_82599EB) {\n#ifdef RTE_NIC_BYPASS\n\t\tif (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {\n\t\t\t/* Not suported in bypass mode */\n\t\t\tPMD_INIT_LOG(ERR, \"Set link down is not supported \"\n\t\t\t\t \"by device id 0x%x\", hw->device_id);\n\t\t\treturn -ENOTSUP;\n\t\t}\n#endif\n\t}\n\n\tif (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {\n\t\t/* Turn off the copper */\n\t\tixgbe_set_phy_power(hw, false);\n\t} else {\n\t\t/* Turn off the laser */\n\t\tixgbe_disable_tx_laser(hw);\n\t}\n\n\treturn 0;\n}\n\n/*\n * Reest and stop device.\n */\nstatic void\nixgbe_dev_close(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tixgbe_pf_reset_hw(hw);\n\n\tixgbe_dev_stop(dev);\n\thw->adapter_stopped = 1;\n\n\tixgbe_dev_free_queues(dev);\n\n\tixgbe_disable_pcie_master(hw);\n\n\t/* reprogram the RAR[0] in case user changed it. */\n\tixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);\n}\n\nstatic void\nixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats\n\t\t\t\t\t\t *hw_stats, uint64_t *total_missed_rx,\n\t\t\t\t\t\t uint64_t *total_qbrc, uint64_t *total_qprc,\n\t\t\t\t\t\t uint64_t *total_qprdc)\n{\n\tuint32_t bprc, lxon, lxoff, total;\n\tunsigned i;\n\n\thw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);\n\thw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);\n\thw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);\n\thw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);\n\n\tfor (i = 0; i < 8; i++) {\n\t\tuint32_t mp;\n\t\tmp = IXGBE_READ_REG(hw, IXGBE_MPC(i));\n\t\t/* global total per queue */\n\t\thw_stats->mpc[i] += mp;\n\t\t/* Running comprehensive total for stats display */\n\t\t*total_missed_rx += hw_stats->mpc[i];\n\t\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\t\thw_stats->rnbc[i] +=\n\t\t\t IXGBE_READ_REG(hw, IXGBE_RNBC(i));\n\t\thw_stats->pxontxc[i] +=\n\t\t IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));\n\t\thw_stats->pxonrxc[i] +=\n\t\t IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));\n\t\thw_stats->pxofftxc[i] +=\n\t\t IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));\n\t\thw_stats->pxoffrxc[i] +=\n\t\t IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));\n\t\thw_stats->pxon2offc[i] +=\n\t\t IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));\n\t}\n\tfor (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {\n\t\thw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));\n\t\thw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));\n\t\thw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));\n\t\thw_stats->qbrc[i] +=\n\t\t ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);\n\t\thw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));\n\t\thw_stats->qbtc[i] +=\n\t\t ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);\n\t\t*total_qprdc += hw_stats->qprdc[i] +=\n\t\t\t\tIXGBE_READ_REG(hw, IXGBE_QPRDC(i));\n\n\t\t*total_qprc += hw_stats->qprc[i];\n\t\t*total_qbrc += hw_stats->qbrc[i];\n\t}\n\thw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);\n\thw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);\n\thw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);\n\n\t/* Note that gprc counts missed packets */\n\thw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);\n\n\tif (hw->mac.type != ixgbe_mac_82598EB) {\n\t\thw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);\n\t\thw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);\n\t\thw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);\n\t\thw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);\n\t\thw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);\n\t\thw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);\n\t\thw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);\n\t\thw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);\n\t} else {\n\t\thw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);\n\t\thw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);\n\t\t/* 82598 only has a counter in the high register */\n\t\thw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);\n\t\thw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);\n\t\thw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);\n\t}\n\n\t/*\n\t * Workaround: mprc hardware is incorrectly counting\n\t * broadcasts, so for now we subtract those.\n\t */\n\tbprc = IXGBE_READ_REG(hw, IXGBE_BPRC);\n\thw_stats->bprc += bprc;\n\thw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\thw_stats->mprc -= bprc;\n\n\thw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);\n\thw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);\n\thw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);\n\thw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);\n\thw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);\n\thw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);\n\n\tlxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);\n\thw_stats->lxontxc += lxon;\n\tlxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);\n\thw_stats->lxofftxc += lxoff;\n\ttotal = lxon + lxoff;\n\n\thw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);\n\thw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);\n\thw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);\n\thw_stats->gptc -= total;\n\thw_stats->mptc -= total;\n\thw_stats->ptc64 -= total;\n\thw_stats->gotc -= total * ETHER_MIN_LEN;\n\n\thw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);\n\thw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);\n\thw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);\n\thw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);\n\thw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);\n\thw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);\n\thw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);\n\thw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);\n\thw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);\n\thw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);\n\thw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);\n\thw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);\n\thw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);\n\thw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);\n\thw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);\n\thw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);\n\thw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);\n\thw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);\n\t/* Only read FCOE on 82599 */\n\tif (hw->mac.type != ixgbe_mac_82598EB) {\n\t\thw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);\n\t\thw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);\n\t\thw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);\n\t\thw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);\n\t\thw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);\n\t}\n\n\t/* Flow Director Stats registers */\n\thw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);\n\thw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);\n}\n\n/*\n * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c\n */\nstatic void\nixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tstruct ixgbe_hw *hw =\n\t\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_hw_stats *hw_stats =\n\t\t\tIXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\tuint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;\n\tunsigned i;\n\n\ttotal_missed_rx = 0;\n\ttotal_qbrc = 0;\n\ttotal_qprc = 0;\n\ttotal_qprdc = 0;\n\n\tixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,\n\t\t\t&total_qprc, &total_qprdc);\n\n\tif (stats == NULL)\n\t\treturn;\n\n\t/* Fill out the rte_eth_stats statistics structure */\n\tstats->ipackets = total_qprc;\n\tstats->ibytes = total_qbrc;\n\tstats->opackets = hw_stats->gptc;\n\tstats->obytes = hw_stats->gotc;\n\n\tfor (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {\n\t\tstats->q_ipackets[i] = hw_stats->qprc[i];\n\t\tstats->q_opackets[i] = hw_stats->qptc[i];\n\t\tstats->q_ibytes[i] = hw_stats->qbrc[i];\n\t\tstats->q_obytes[i] = hw_stats->qbtc[i];\n\t\tstats->q_errors[i] = hw_stats->qprdc[i];\n\t}\n\n\t/* Rx Errors */\n\tstats->ierrors = hw_stats->crcerrs +\n\t hw_stats->rlec +\n\t hw_stats->ruc +\n\t hw_stats->roc +\n\t total_missed_rx +\n\t hw_stats->illerrc +\n\t hw_stats->errbc +\n\t hw_stats->xec +\n\t hw_stats->mlfc +\n\t hw_stats->mrfc +\n\t hw_stats->rfc +\n\t hw_stats->rjc +\n\t hw_stats->fccrc +\n\t hw_stats->fclast;\n\n\t/* Tx Errors */\n\tstats->oerrors = 0;\n}\n\nstatic void\nixgbe_dev_stats_reset(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw_stats *stats =\n\t\t\tIXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\n\t/* HW registers are cleared on read */\n\tixgbe_dev_stats_get(dev, NULL);\n\n\t/* Reset software totals */\n\tmemset(stats, 0, sizeof(*stats));\n}\n\nstatic int\nixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,\n\t\t\t\t\t unsigned n)\n{\n\tstruct ixgbe_hw *hw =\n\t\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_hw_stats *hw_stats =\n\t\t\tIXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\tuint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;\n\tunsigned i, count = IXGBE_NB_XSTATS;\n\n\tif (n < count)\n\t\treturn count;\n\n\ttotal_missed_rx = 0;\n\ttotal_qbrc = 0;\n\ttotal_qprc = 0;\n\ttotal_qprdc = 0;\n\n\tixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,\n\t\t\t\t\t\t\t &total_qprc, &total_qprdc);\n\n\t/* If this is a reset xstats is NULL, and we have cleared the\n\t * registers by reading them.\n\t */\n\tif (!xstats)\n\t\treturn 0;\n\n\t/* Extended stats */\n\tfor (i = 0; i < IXGBE_NB_XSTATS; i++) {\n\t\tsnprintf(xstats[i].name, sizeof(xstats[i].name),\n\t\t\t\t\"%s\", rte_ixgbe_stats_strings[i].name);\n\t\txstats[i].value = *(uint64_t *)(((char *)hw_stats) +\n\t\t\t\t\t\t\trte_ixgbe_stats_strings[i].offset);\n\t}\n\n\treturn count;\n}\n\nstatic void\nixgbe_dev_xstats_reset(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw_stats *stats =\n\t\t\tIXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\n\t/* HW registers are cleared on read */\n\tixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);\n\n\t/* Reset software totals */\n\tmemset(stats, 0, sizeof(*stats));\n}\n\nstatic void\nixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)\n\t\t\t IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\n\t/* Good Rx packet, include VF loopback */\n\tUPDATE_VF_STAT(IXGBE_VFGPRC,\n\t hw_stats->last_vfgprc, hw_stats->vfgprc);\n\n\t/* Good Rx octets, include VF loopback */\n\tUPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,\n\t hw_stats->last_vfgorc, hw_stats->vfgorc);\n\n\t/* Good Tx packet, include VF loopback */\n\tUPDATE_VF_STAT(IXGBE_VFGPTC,\n\t hw_stats->last_vfgptc, hw_stats->vfgptc);\n\n\t/* Good Tx octets, include VF loopback */\n\tUPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,\n\t hw_stats->last_vfgotc, hw_stats->vfgotc);\n\n\t/* Rx Multicst Packet */\n\tUPDATE_VF_STAT(IXGBE_VFMPRC,\n\t hw_stats->last_vfmprc, hw_stats->vfmprc);\n\n\tif (stats == NULL)\n\t\treturn;\n\n\tstats->ipackets = hw_stats->vfgprc;\n\tstats->ibytes = hw_stats->vfgorc;\n\tstats->opackets = hw_stats->vfgptc;\n\tstats->obytes = hw_stats->vfgotc;\n\tstats->imcasts = hw_stats->vfmprc;\n\t/* stats->imcasts should be removed as imcasts is deprecated */\n}\n\nstatic void\nixgbevf_dev_stats_reset(struct rte_eth_dev *dev)\n{\n\tstruct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)\n\t\t\tIXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);\n\n\t/* Sync HW register to the last stats */\n\tixgbevf_dev_stats_get(dev, NULL);\n\n\t/* reset HW current stats*/\n\thw_stats->vfgprc = 0;\n\thw_stats->vfgorc = 0;\n\thw_stats->vfgptc = 0;\n\thw_stats->vfgotc = 0;\n\thw_stats->vfmprc = 0;\n\n}\n\nstatic void\nixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tdev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;\n\tdev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;\n\tdev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */\n\tdev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */\n\tdev_info->max_mac_addrs = hw->mac.num_rar_entries;\n\tdev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;\n\tdev_info->max_vfs = dev->pci_dev->max_vfs;\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\tdev_info->max_vmdq_pools = ETH_16_POOLS;\n\telse\n\t\tdev_info->max_vmdq_pools = ETH_64_POOLS;\n\tdev_info->vmdq_queue_num = dev_info->max_rx_queues;\n\tdev_info->rx_offload_capa =\n\t\tDEV_RX_OFFLOAD_VLAN_STRIP |\n\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n\t\tDEV_RX_OFFLOAD_TCP_CKSUM;\n\n\t/*\n\t * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV\n\t * mode.\n\t */\n\tif ((hw->mac.type == ixgbe_mac_82599EB ||\n\t hw->mac.type == ixgbe_mac_X540) &&\n\t !RTE_ETH_DEV_SRIOV(dev).active)\n\t\tdev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;\n\n\tdev_info->tx_offload_capa =\n\t\tDEV_TX_OFFLOAD_VLAN_INSERT |\n\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n\t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n\t\tDEV_TX_OFFLOAD_SCTP_CKSUM |\n\t\tDEV_TX_OFFLOAD_TCP_TSO;\n\n\tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n\t\t.rx_thresh = {\n\t\t\t.pthresh = IXGBE_DEFAULT_RX_PTHRESH,\n\t\t\t.hthresh = IXGBE_DEFAULT_RX_HTHRESH,\n\t\t\t.wthresh = IXGBE_DEFAULT_RX_WTHRESH,\n\t\t},\n\t\t.rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,\n\t\t.rx_drop_en = 0,\n\t};\n\n\tdev_info->default_txconf = (struct rte_eth_txconf) {\n\t\t.tx_thresh = {\n\t\t\t.pthresh = IXGBE_DEFAULT_TX_PTHRESH,\n\t\t\t.hthresh = IXGBE_DEFAULT_TX_HTHRESH,\n\t\t\t.wthresh = IXGBE_DEFAULT_TX_WTHRESH,\n\t\t},\n\t\t.tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,\n\t\t.tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,\n\t\t.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |\n\t\t\t\tETH_TXQ_FLAGS_NOOFFLOADS,\n\t};\n\n\t/*\n\t * According to 82599 and x540 specifications RS bit *must* be set on the\n\t * last descriptor of *every* packet. Therefore we will not allow the\n\t * tx_rs_thresh above 1 for all NICs newer than 82598.\n\t */\n\tif (hw->mac.type > ixgbe_mac_82598EB)\n\t\tdev_info->default_txconf.tx_rs_thresh = 1;\n\n\tdev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);\n\tdev_info->reta_size = ETH_RSS_RETA_SIZE_128;\n\tdev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;\n}\n\nstatic void\nixgbevf_dev_info_get(struct rte_eth_dev *dev,\n\t\t struct rte_eth_dev_info *dev_info)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tdev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;\n\tdev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;\n\tdev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */\n\tdev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */\n\tdev_info->max_mac_addrs = hw->mac.num_rar_entries;\n\tdev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;\n\tdev_info->max_vfs = dev->pci_dev->max_vfs;\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\tdev_info->max_vmdq_pools = ETH_16_POOLS;\n\telse\n\t\tdev_info->max_vmdq_pools = ETH_64_POOLS;\n\tdev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |\n\t\t\t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n\t\t\t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n\t\t\t\tDEV_RX_OFFLOAD_TCP_CKSUM;\n\tdev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |\n\t\t\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n\t\t\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n\t\t\t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n\t\t\t\tDEV_TX_OFFLOAD_SCTP_CKSUM;\n\n\tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n\t\t.rx_thresh = {\n\t\t\t.pthresh = IXGBE_DEFAULT_RX_PTHRESH,\n\t\t\t.hthresh = IXGBE_DEFAULT_RX_HTHRESH,\n\t\t\t.wthresh = IXGBE_DEFAULT_RX_WTHRESH,\n\t\t},\n\t\t.rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,\n\t\t.rx_drop_en = 0,\n\t};\n\n\tdev_info->default_txconf = (struct rte_eth_txconf) {\n\t\t.tx_thresh = {\n\t\t\t.pthresh = IXGBE_DEFAULT_TX_PTHRESH,\n\t\t\t.hthresh = IXGBE_DEFAULT_TX_HTHRESH,\n\t\t\t.wthresh = IXGBE_DEFAULT_TX_WTHRESH,\n\t\t},\n\t\t.tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,\n\t\t/*\n\t\t * According to 82599 and x540 specifications RS bit *must* be\n\t\t * set on the last descriptor of *every* packet. Therefore we\n\t\t * will not allow the tx_rs_thresh above 1 for all NICs newer\n\t\t * than 82598. Since VFs are available only on devices starting\n\t\t * from 82599, tx_rs_thresh should be set to 1 for ALL VF\n\t\t * devices.\n\t\t */\n\t\t.tx_rs_thresh = 1,\n\t\t.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |\n\t\t\t\tETH_TXQ_FLAGS_NOOFFLOADS,\n\t};\n}\n\n/* return 0 means link status changed, -1 means not changed */\nstatic int\nixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct rte_eth_link link, old;\n\tixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;\n\tint link_up;\n\tint diag;\n\n\tlink.link_status = 0;\n\tlink.link_speed = 0;\n\tlink.link_duplex = 0;\n\tmemset(&old, 0, sizeof(old));\n\trte_ixgbe_dev_atomic_read_link_status(dev, &old);\n\n\thw->mac.get_link_status = true;\n\n\t/* check if it needs to wait to complete, if lsc interrupt is enabled */\n\tif (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)\n\t\tdiag = ixgbe_check_link(hw, &link_speed, &link_up, 0);\n\telse\n\t\tdiag = ixgbe_check_link(hw, &link_speed, &link_up, 1);\n\n\tif (diag != 0) {\n\t\tlink.link_speed = ETH_LINK_SPEED_100;\n\t\tlink.link_duplex = ETH_LINK_HALF_DUPLEX;\n\t\trte_ixgbe_dev_atomic_write_link_status(dev, &link);\n\t\tif (link.link_status == old.link_status)\n\t\t\treturn -1;\n\t\treturn 0;\n\t}\n\n\tif (link_up == 0) {\n\t\trte_ixgbe_dev_atomic_write_link_status(dev, &link);\n\t\tif (link.link_status == old.link_status)\n\t\t\treturn -1;\n\t\treturn 0;\n\t}\n\tlink.link_status = 1;\n\tlink.link_duplex = ETH_LINK_FULL_DUPLEX;\n\n\tswitch (link_speed) {\n\tdefault:\n\tcase IXGBE_LINK_SPEED_UNKNOWN:\n\t\tlink.link_duplex = ETH_LINK_HALF_DUPLEX;\n\t\tlink.link_speed = ETH_LINK_SPEED_100;\n\t\tbreak;\n\n\tcase IXGBE_LINK_SPEED_100_FULL:\n\t\tlink.link_speed = ETH_LINK_SPEED_100;\n\t\tbreak;\n\n\tcase IXGBE_LINK_SPEED_1GB_FULL:\n\t\tlink.link_speed = ETH_LINK_SPEED_1000;\n\t\tbreak;\n\n\tcase IXGBE_LINK_SPEED_10GB_FULL:\n\t\tlink.link_speed = ETH_LINK_SPEED_10000;\n\t\tbreak;\n\t}\n\trte_ixgbe_dev_atomic_write_link_status(dev, &link);\n\n\tif (link.link_status == old.link_status)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic void\nixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t fctrl;\n\n\tfctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\tfctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);\n\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);\n}\n\nstatic void\nixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t fctrl;\n\n\tfctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\tfctrl &= (~IXGBE_FCTRL_UPE);\n\tif (dev->data->all_multicast == 1)\n\t\tfctrl |= IXGBE_FCTRL_MPE;\n\telse\n\t\tfctrl &= (~IXGBE_FCTRL_MPE);\n\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);\n}\n\nstatic void\nixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t fctrl;\n\n\tfctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\tfctrl |= IXGBE_FCTRL_MPE;\n\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);\n}\n\nstatic void\nixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t fctrl;\n\n\tif (dev->data->promiscuous == 1)\n\t\treturn; /* must remain in all_multicast mode */\n\n\tfctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\tfctrl &= (~IXGBE_FCTRL_MPE);\n\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);\n}\n\n/**\n * It clears the interrupt causes and enables the interrupt.\n * It will be called once only during nic initialized.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_interrupt *intr =\n\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\tixgbe_dev_link_status_print(dev);\n\tintr->mask |= IXGBE_EICR_LSC;\n\n\treturn 0;\n}\n\n/**\n * It clears the interrupt causes and enables the interrupt.\n * It will be called once only during nic initialized.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\n#ifdef RTE_NEXT_ABI\nstatic int\nixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_interrupt *intr =\n\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\tintr->mask |= IXGBE_EICR_RTX_QUEUE;\n\n\treturn 0;\n}\n#endif\n\n/*\n * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)\n{\n\tuint32_t eicr;\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_interrupt *intr =\n\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\t/* clear all cause mask */\n\tixgbe_disable_intr(hw);\n\n\t/* read-on-clear nic registers here */\n\teicr = IXGBE_READ_REG(hw, IXGBE_EICR);\n\tPMD_DRV_LOG(DEBUG, \"eicr %x\", eicr);\n\n\tintr->flags = 0;\n\n\t/* set flag for async link update */\n\tif (eicr & IXGBE_EICR_LSC)\n\t\tintr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;\n\n\tif (eicr & IXGBE_EICR_MAILBOX)\n\t\tintr->flags |= IXGBE_FLAG_MAILBOX;\n\n\treturn 0;\n}\n\nstatic int\nixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)\n{\n\tuint32_t eicr;\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_interrupt *intr =\n\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\t/* clear all cause mask */\n\tixgbevf_intr_disable(hw);\n\n\t/* read-on-clear nic registers here */\n\teicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);\n\tPMD_DRV_LOG(INFO, \"eicr %x\", eicr);\n\n\tintr->flags = 0;\n\n\t/* set flag for async link update */\n\tif (eicr & IXGBE_EICR_LSC)\n\t\tintr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;\n\n\treturn 0;\n}\n\n/**\n * It gets and then prints the link status.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic void\nixgbe_dev_link_status_print(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_link link;\n\n\tmemset(&link, 0, sizeof(link));\n\trte_ixgbe_dev_atomic_read_link_status(dev, &link);\n\tif (link.link_status) {\n\t\tPMD_INIT_LOG(INFO, \"Port %d: Link Up - speed %u Mbps - %s\",\n\t\t\t\t\t(int)(dev->data->port_id),\n\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\tlink.link_duplex == ETH_LINK_FULL_DUPLEX ?\n\t\t\t\t\t\"full-duplex\" : \"half-duplex\");\n\t} else {\n\t\tPMD_INIT_LOG(INFO, \" Port %d: Link Down\",\n\t\t\t\t(int)(dev->data->port_id));\n\t}\n\tPMD_INIT_LOG(DEBUG, \"PCI Address: %04d:%02d:%02d:%d\",\n\t\t\t\tdev->pci_dev->addr.domain,\n\t\t\t\tdev->pci_dev->addr.bus,\n\t\t\t\tdev->pci_dev->addr.devid,\n\t\t\t\tdev->pci_dev->addr.function);\n}\n\n/*\n * It executes link_update after knowing an interrupt occurred.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nixgbe_dev_interrupt_action(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_interrupt *intr =\n\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\tint64_t timeout;\n\tstruct rte_eth_link link;\n\tint intr_enable_delay = false;\n\n\tPMD_DRV_LOG(DEBUG, \"intr action type %d\", intr->flags);\n\n\tif (intr->flags & IXGBE_FLAG_MAILBOX) {\n\t\tixgbe_pf_mbx_process(dev);\n\t\tintr->flags &= ~IXGBE_FLAG_MAILBOX;\n\t}\n\n\tif (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {\n\t\t/* get the link status before link update, for predicting later */\n\t\tmemset(&link, 0, sizeof(link));\n\t\trte_ixgbe_dev_atomic_read_link_status(dev, &link);\n\n\t\tixgbe_dev_link_update(dev, 0);\n\n\t\t/* likely to up */\n\t\tif (!link.link_status)\n\t\t\t/* handle it 1 sec later, wait it being stable */\n\t\t\ttimeout = IXGBE_LINK_UP_CHECK_TIMEOUT;\n\t\t/* likely to down */\n\t\telse\n\t\t\t/* handle it 4 sec later, wait it being stable */\n\t\t\ttimeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;\n\n\t\tixgbe_dev_link_status_print(dev);\n\n\t\tintr_enable_delay = true;\n\t}\n\n\tif (intr_enable_delay) {\n\t\tif (rte_eal_alarm_set(timeout * 1000,\n\t\t\t\t ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)\n\t\t\tPMD_DRV_LOG(ERR, \"Error setting alarm\");\n\t} else {\n\t\tPMD_DRV_LOG(DEBUG, \"enable intr immediately\");\n\t\tixgbe_enable_intr(dev);\n\t\trte_intr_enable(&(dev->pci_dev->intr_handle));\n\t}\n\n\n\treturn 0;\n}\n\nstatic int\nixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_DRV_LOG(DEBUG, \"enable intr immediately\");\n\tixgbevf_intr_enable(hw);\n\trte_intr_enable(&dev->pci_dev->intr_handle);\n\treturn 0;\n}\n\n/**\n * Interrupt handler which shall be registered for alarm callback for delayed\n * handling specific interrupt to wait for the stable nic state. As the\n * NIC interrupt state is not stable for ixgbe after link is just down,\n * it needs to wait 4 seconds to get the stable status.\n *\n * @param handle\n * Pointer to interrupt handle.\n * @param param\n * The address of parameter (struct rte_eth_dev *) regsitered before.\n *\n * @return\n * void\n */\nstatic void\nixgbe_dev_interrupt_delayed_handler(void *param)\n{\n\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n\tstruct ixgbe_interrupt *intr =\n\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t eicr;\n\n\teicr = IXGBE_READ_REG(hw, IXGBE_EICR);\n\tif (eicr & IXGBE_EICR_MAILBOX)\n\t\tixgbe_pf_mbx_process(dev);\n\n\tif (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {\n\t\tixgbe_dev_link_update(dev, 0);\n\t\tintr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;\n\t\tixgbe_dev_link_status_print(dev);\n\t\t_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);\n\t}\n\n\tPMD_DRV_LOG(DEBUG, \"enable intr in delayed handler S[%08x]\", eicr);\n\tixgbe_enable_intr(dev);\n\trte_intr_enable(&(dev->pci_dev->intr_handle));\n}\n\n/**\n * Interrupt handler triggered by NIC for handling\n * specific interrupt.\n *\n * @param handle\n * Pointer to interrupt handle.\n * @param param\n * The address of parameter (struct rte_eth_dev *) regsitered before.\n *\n * @return\n * void\n */\nstatic void\nixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,\n\t\t\t void *param)\n{\n\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n\n\tixgbe_dev_interrupt_get_status(dev);\n\tixgbe_dev_interrupt_action(dev);\n}\n\nstatic void\nixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,\n\t\t\t void *param)\n{\n\tstruct rte_eth_dev *dev = (struct rte_eth_dev *)param;\n\n\tixgbevf_dev_interrupt_get_status(dev);\n\tixgbevf_dev_interrupt_action(dev);\n}\n\nstatic int\nixgbe_dev_led_on(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw;\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\treturn (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);\n}\n\nstatic int\nixgbe_dev_led_off(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw;\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\treturn (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);\n}\n\nstatic int\nixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n{\n\tstruct ixgbe_hw *hw;\n\tuint32_t mflcn_reg;\n\tuint32_t fccfg_reg;\n\tint rx_pause;\n\tint tx_pause;\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tfc_conf->pause_time = hw->fc.pause_time;\n\tfc_conf->high_water = hw->fc.high_water[0];\n\tfc_conf->low_water = hw->fc.low_water[0];\n\tfc_conf->send_xon = hw->fc.send_xon;\n\tfc_conf->autoneg = !hw->fc.disable_fc_autoneg;\n\n\t/*\n\t * Return rx_pause status according to actual setting of\n\t * MFLCN register.\n\t */\n\tmflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);\n\tif (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))\n\t\trx_pause = 1;\n\telse\n\t\trx_pause = 0;\n\n\t/*\n\t * Return tx_pause status according to actual setting of\n\t * FCCFG register.\n\t */\n\tfccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);\n\tif (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))\n\t\ttx_pause = 1;\n\telse\n\t\ttx_pause = 0;\n\n\tif (rx_pause && tx_pause)\n\t\tfc_conf->mode = RTE_FC_FULL;\n\telse if (rx_pause)\n\t\tfc_conf->mode = RTE_FC_RX_PAUSE;\n\telse if (tx_pause)\n\t\tfc_conf->mode = RTE_FC_TX_PAUSE;\n\telse\n\t\tfc_conf->mode = RTE_FC_NONE;\n\n\treturn 0;\n}\n\nstatic int\nixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n{\n\tstruct ixgbe_hw *hw;\n\tint err;\n\tuint32_t rx_buf_size;\n\tuint32_t max_high_water;\n\tuint32_t mflcn;\n\tenum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {\n\t\tixgbe_fc_none,\n\t\tixgbe_fc_rx_pause,\n\t\tixgbe_fc_tx_pause,\n\t\tixgbe_fc_full\n\t};\n\n\tPMD_INIT_FUNC_TRACE();\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\trx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));\n\tPMD_INIT_LOG(DEBUG, \"Rx packet buffer size = 0x%x\", rx_buf_size);\n\n\t/*\n\t * At least reserve one Ethernet frame for watermark\n\t * high_water/low_water in kilo bytes for ixgbe\n\t */\n\tmax_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;\n\tif ((fc_conf->high_water > max_high_water) ||\n\t\t(fc_conf->high_water < fc_conf->low_water)) {\n\t\tPMD_INIT_LOG(ERR, \"Invalid high/low water setup value in KB\");\n\t\tPMD_INIT_LOG(ERR, \"High_water must <= 0x%x\", max_high_water);\n\t\treturn (-EINVAL);\n\t}\n\n\thw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];\n\thw->fc.pause_time = fc_conf->pause_time;\n\thw->fc.high_water[0] = fc_conf->high_water;\n\thw->fc.low_water[0] = fc_conf->low_water;\n\thw->fc.send_xon = fc_conf->send_xon;\n\thw->fc.disable_fc_autoneg = !fc_conf->autoneg;\n\n\terr = ixgbe_fc_enable(hw);\n\n\t/* Not negotiated is not an error case */\n\tif ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {\n\n\t\t/* check if we want to forward MAC frames - driver doesn't have native\n\t\t * capability to do that, so we'll write the registers ourselves */\n\n\t\tmflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);\n\n\t\t/* set or clear MFLCN.PMCF bit depending on configuration */\n\t\tif (fc_conf->mac_ctrl_frame_fwd != 0)\n\t\t\tmflcn |= IXGBE_MFLCN_PMCF;\n\t\telse\n\t\t\tmflcn &= ~IXGBE_MFLCN_PMCF;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\n\t\treturn 0;\n\t}\n\n\tPMD_INIT_LOG(ERR, \"ixgbe_fc_enable = 0x%x\", err);\n\treturn -EIO;\n}\n\n/**\n * ixgbe_pfc_enable_generic - Enable flow control\n * @hw: pointer to hardware structure\n * @tc_num: traffic class number\n * Enable flow control according to the current settings.\n */\nstatic int\nixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)\n{\n\tint ret_val = 0;\n\tuint32_t mflcn_reg, fccfg_reg;\n\tuint32_t reg;\n\tuint32_t fcrtl, fcrth;\n\tuint8_t i;\n\tuint8_t nb_rx_en;\n\n\t/* Validate the water mark configuration */\n\tif (!hw->fc.pause_time) {\n\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\tgoto out;\n\t}\n\n\t/* Low water mark of zero causes XOFF floods */\n\tif (hw->fc.current_mode & ixgbe_fc_tx_pause) {\n\t\t /* High/Low water can not be 0 */\n\t\tif( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {\n\t\t\tPMD_INIT_LOG(ERR, \"Invalid water mark configuration\");\n\t\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\t\tgoto out;\n\t\t}\n\n\t\tif(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {\n\t\t\tPMD_INIT_LOG(ERR, \"Invalid water mark configuration\");\n\t\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\t\tgoto out;\n\t\t}\n\t}\n\t/* Negotiate the fc mode to use */\n\tixgbe_fc_autoneg(hw);\n\n\t/* Disable any previous flow control settings */\n\tmflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);\n\tmflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);\n\n\tfccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);\n\tfccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);\n\n\tswitch (hw->fc.current_mode) {\n\tcase ixgbe_fc_none:\n\t\t/*\n\t\t * If the count of enabled RX Priority Flow control >1,\n\t\t * and the TX pause can not be disabled\n\t\t */\n\t\tnb_rx_en = 0;\n\t\tfor (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\t\treg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));\n\t\t\tif (reg & IXGBE_FCRTH_FCEN)\n\t\t\t\tnb_rx_en++;\n\t\t}\n\t\tif (nb_rx_en > 1)\n\t\t\tfccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;\n\t\tbreak;\n\tcase ixgbe_fc_rx_pause:\n\t\t/*\n\t\t * Rx Flow control is enabled and Tx Flow control is\n\t\t * disabled by software override. Since there really\n\t\t * isn't a way to advertise that we are capable of RX\n\t\t * Pause ONLY, we will advertise that we support both\n\t\t * symmetric and asymmetric Rx PAUSE. Later, we will\n\t\t * disable the adapter's ability to send PAUSE frames.\n\t\t */\n\t\tmflcn_reg |= IXGBE_MFLCN_RPFCE;\n\t\t/*\n\t\t * If the count of enabled RX Priority Flow control >1,\n\t\t * and the TX pause can not be disabled\n\t\t */\n\t\tnb_rx_en = 0;\n\t\tfor (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\t\treg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));\n\t\t\tif (reg & IXGBE_FCRTH_FCEN)\n\t\t\t\tnb_rx_en++;\n\t\t}\n\t\tif (nb_rx_en > 1)\n\t\t\tfccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;\n\t\tbreak;\n\tcase ixgbe_fc_tx_pause:\n\t\t/*\n\t\t * Tx Flow control is enabled, and Rx Flow control is\n\t\t * disabled by software override.\n\t\t */\n\t\tfccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;\n\t\tbreak;\n\tcase ixgbe_fc_full:\n\t\t/* Flow control (both Rx and Tx) is enabled by SW override. */\n\t\tmflcn_reg |= IXGBE_MFLCN_RPFCE;\n\t\tfccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(DEBUG, \"Flow control param set incorrectly\");\n\t\tret_val = IXGBE_ERR_CONFIG;\n\t\tgoto out;\n\t\tbreak;\n\t}\n\n\t/* Set 802.3x based flow control settings. */\n\tmflcn_reg |= IXGBE_MFLCN_DPF;\n\tIXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);\n\tIXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);\n\n\t/* Set up and enable Rx high/low water mark thresholds, enable XON. */\n\tif ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&\n\t\thw->fc.high_water[tc_num]) {\n\t\tfcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);\n\t\tfcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;\n\t} else {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);\n\t\t/*\n\t\t * In order to prevent Tx hangs when the internal Tx\n\t\t * switch is enabled we must set the high water mark\n\t\t * to the maximum FCRTH value. This allows the Tx\n\t\t * switch to function even under heavy Rx workloads.\n\t\t */\n\t\tfcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;\n\t}\n\tIXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);\n\n\t/* Configure pause time (2 TCs per register) */\n\treg = hw->fc.pause_time * 0x00010001;\n\tfor (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);\n\n\t/* Configure flow control refresh threshold value */\n\tIXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);\n\nout:\n\treturn ret_val;\n}\n\nstatic int\nixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint32_t ret_val = IXGBE_NOT_IMPLEMENTED;\n\n\tif(hw->mac.type != ixgbe_mac_82598EB) {\n\t\tret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);\n\t}\n\treturn ret_val;\n}\n\nstatic int\nixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)\n{\n\tint err;\n\tuint32_t rx_buf_size;\n\tuint32_t max_high_water;\n\tuint8_t tc_num;\n\tuint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };\n\tstruct ixgbe_hw *hw =\n IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_dcb_config *dcb_config =\n IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);\n\n\tenum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {\n\t\tixgbe_fc_none,\n\t\tixgbe_fc_rx_pause,\n\t\tixgbe_fc_tx_pause,\n\t\tixgbe_fc_full\n\t};\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);\n\ttc_num = map[pfc_conf->priority];\n\trx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));\n\tPMD_INIT_LOG(DEBUG, \"Rx packet buffer size = 0x%x\", rx_buf_size);\n\t/*\n\t * At least reserve one Ethernet frame for watermark\n\t * high_water/low_water in kilo bytes for ixgbe\n\t */\n\tmax_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;\n\tif ((pfc_conf->fc.high_water > max_high_water) ||\n\t (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {\n\t\tPMD_INIT_LOG(ERR, \"Invalid high/low water setup value in KB\");\n\t\tPMD_INIT_LOG(ERR, \"High_water must <= 0x%x\", max_high_water);\n\t\treturn (-EINVAL);\n\t}\n\n\thw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];\n\thw->fc.pause_time = pfc_conf->fc.pause_time;\n\thw->fc.send_xon = pfc_conf->fc.send_xon;\n\thw->fc.low_water[tc_num] = pfc_conf->fc.low_water;\n\thw->fc.high_water[tc_num] = pfc_conf->fc.high_water;\n\n\terr = ixgbe_dcb_pfc_enable(dev,tc_num);\n\n\t/* Not negotiated is not an error case */\n\tif ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))\n\t\treturn 0;\n\n\tPMD_INIT_LOG(ERR, \"ixgbe_dcb_pfc_enable = 0x%x\", err);\n\treturn -EIO;\n}\n\nstatic int\nixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t uint16_t reta_size)\n{\n\tuint8_t i, j, mask;\n\tuint32_t reta, r;\n\tuint16_t idx, shift;\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n\t\t\t\"(%d) doesn't match the number hardware can supported \"\n\t\t\t\"(%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_128);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {\n\t\tidx = i / RTE_RETA_GROUP_SIZE;\n\t\tshift = i % RTE_RETA_GROUP_SIZE;\n\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n\t\t\t\t\t\tIXGBE_4_BIT_MASK);\n\t\tif (!mask)\n\t\t\tcontinue;\n\t\tif (mask == IXGBE_4_BIT_MASK)\n\t\t\tr = 0;\n\t\telse\n\t\t\tr = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));\n\t\tfor (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {\n\t\t\tif (mask & (0x1 << j))\n\t\t\t\treta |= reta_conf[idx].reta[shift + j] <<\n\t\t\t\t\t\t\t(CHAR_BIT * j);\n\t\t\telse\n\t\t\t\treta |= r & (IXGBE_8_BIT_MASK <<\n\t\t\t\t\t\t(CHAR_BIT * j));\n\t\t}\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t uint16_t reta_size)\n{\n\tuint8_t i, j, mask;\n\tuint32_t reta;\n\tuint16_t idx, shift;\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\tif (reta_size != ETH_RSS_RETA_SIZE_128) {\n\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n\t\t\t\"(%d) doesn't match the number hardware can supported \"\n\t\t\t\t\"(%d)\\n\", reta_size, ETH_RSS_RETA_SIZE_128);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {\n\t\tidx = i / RTE_RETA_GROUP_SIZE;\n\t\tshift = i % RTE_RETA_GROUP_SIZE;\n\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n\t\t\t\t\t\tIXGBE_4_BIT_MASK);\n\t\tif (!mask)\n\t\t\tcontinue;\n\n\t\treta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));\n\t\tfor (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {\n\t\t\tif (mask & (0x1 << j))\n\t\t\t\treta_conf[idx].reta[shift + j] =\n\t\t\t\t\t((reta >> (CHAR_BIT * j)) &\n\t\t\t\t\t\tIXGBE_8_BIT_MASK);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic void\nixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,\n\t\t\t\tuint32_t index, uint32_t pool)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t enable_addr = 1;\n\n\tixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);\n}\n\nstatic void\nixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tixgbe_clear_rar(hw, index);\n}\n\nstatic void\nixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)\n{\n\tixgbe_remove_rar(dev, 0);\n\n\tixgbe_add_rar(dev, addr, 0, 0);\n}\n\nstatic int\nixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)\n{\n\tuint32_t hlreg0;\n\tuint32_t maxfrs;\n\tstruct ixgbe_hw *hw;\n\tstruct rte_eth_dev_info dev_info;\n\tuint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;\n\n\tixgbe_dev_info_get(dev, &dev_info);\n\n\t/* check that mtu is within the allowed range */\n\tif ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))\n\t\treturn -EINVAL;\n\n\t/* refuse mtu that requires the support of scattered packets when this\n\t * feature has not been enabled before. */\n\tif (!dev->data->scattered_rx &&\n\t (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >\n\t dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))\n\t\treturn -EINVAL;\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\thlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);\n\n\t/* switch to jumbo mode if needed */\n\tif (frame_size > ETHER_MAX_LEN) {\n\t\tdev->data->dev_conf.rxmode.jumbo_frame = 1;\n\t\thlreg0 |= IXGBE_HLREG0_JUMBOEN;\n\t} else {\n\t\tdev->data->dev_conf.rxmode.jumbo_frame = 0;\n\t\thlreg0 &= ~IXGBE_HLREG0_JUMBOEN;\n\t}\n\tIXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);\n\n\t/* update max frame size */\n\tdev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;\n\n\tmaxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);\n\tmaxfrs &= 0x0000FFFF;\n\tmaxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);\n\tIXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);\n\n\treturn 0;\n}\n\n/*\n * Virtual Function operations\n */\nstatic void\nixgbevf_intr_disable(struct ixgbe_hw *hw)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* Clear interrupt mask to stop from interrupts being generated */\n\tIXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);\n\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\nstatic void\nixgbevf_intr_enable(struct ixgbe_hw *hw)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* VF enable interrupt autoclean */\n\tIXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);\n\tIXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);\n\tIXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);\n\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\nstatic int\nixgbevf_dev_configure(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_conf* conf = &dev->data->dev_conf;\n\tstruct ixgbe_adapter *adapter =\n\t\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n\n\tPMD_INIT_LOG(DEBUG, \"Configured Virtual Function port id: %d\",\n\t\t dev->data->port_id);\n\n\t/*\n\t * VF has no ability to enable/disable HW CRC\n\t * Keep the persistent behavior the same as Host PF\n\t */\n#ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC\n\tif (!conf->rxmode.hw_strip_crc) {\n\t\tPMD_INIT_LOG(NOTICE, \"VF can't disable HW CRC Strip\");\n\t\tconf->rxmode.hw_strip_crc = 1;\n\t}\n#else\n\tif (conf->rxmode.hw_strip_crc) {\n\t\tPMD_INIT_LOG(NOTICE, \"VF can't enable HW CRC Strip\");\n\t\tconf->rxmode.hw_strip_crc = 0;\n\t}\n#endif\n\n\t/*\n\t * Initialize to TRUE. If any of Rx queues doesn't meet the bulk\n\t * allocation or vector Rx preconditions we will reset it.\n\t */\n\tadapter->rx_bulk_alloc_allowed = true;\n\tadapter->rx_vec_allowed = true;\n\n\treturn 0;\n}\n\nstatic int\nixgbevf_dev_start(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n#ifdef RTE_NEXT_ABI\n\tuint32_t intr_vector = 0;\n#endif\n\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n\n\tint err, mask = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\thw->mac.ops.reset_hw(hw);\n\thw->mac.get_link_status = true;\n\n\t/* negotiate mailbox API version to use with the PF. */\n\tixgbevf_negotiate_api(hw);\n\n\tixgbevf_dev_tx_init(dev);\n\n\t/* This can fail when allocating mbufs for descriptor rings */\n\terr = ixgbevf_dev_rx_init(dev);\n\tif (err) {\n\t\tPMD_INIT_LOG(ERR, \"Unable to initialize RX hardware (%d)\", err);\n\t\tixgbe_dev_clear_queues(dev);\n\t\treturn err;\n\t}\n\n\t/* Set vfta */\n\tixgbevf_set_vfta_all(dev,1);\n\n\t/* Set HW strip */\n\tmask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \\\n\t\tETH_VLAN_EXTEND_MASK;\n\tixgbevf_vlan_offload_set(dev, mask);\n\n\tixgbevf_dev_rxtx_start(dev);\n\n#ifdef RTE_NEXT_ABI\n\t/* check and configure queue intr-vector mapping */\n\tif (dev->data->dev_conf.intr_conf.rxq != 0)\n\t\tintr_vector = dev->data->nb_rx_queues;\n\n\tif (rte_intr_efd_enable(intr_handle, intr_vector))\n\t\treturn -1;\n\n\tif (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {\n\t\tintr_handle->intr_vec =\n\t\t\trte_zmalloc(\"intr_vec\",\n\t\t\t\t dev->data->nb_rx_queues * sizeof(int), 0);\n\t\tif (intr_handle->intr_vec == NULL) {\n\t\t\tPMD_INIT_LOG(ERR, \"Failed to allocate %d rx_queues\"\n\t\t\t\t \" intr_vec\\n\", dev->data->nb_rx_queues);\n\t\t\treturn -ENOMEM;\n\t\t}\n\t}\n#endif\n\tixgbevf_configure_msix(dev);\n\n\tif (dev->data->dev_conf.intr_conf.lsc != 0) {\n\t\tif (rte_intr_allow_others(intr_handle))\n\t\t\trte_intr_callback_register(intr_handle,\n\t\t\t\t\tixgbevf_dev_interrupt_handler,\n\t\t\t\t\t(void *)dev);\n\t\telse\n\t\t\tPMD_INIT_LOG(INFO, \"lsc won't enable because of\"\n\t\t\t\t \" no intr multiplex\\n\");\n\t}\n\n\trte_intr_enable(intr_handle);\n\n\t/* Re-enable interrupt for VF */\n\tixgbevf_intr_enable(hw);\n\n\treturn 0;\n}\n\nstatic void\nixgbevf_dev_stop(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\thw->adapter_stopped = 1;\n\tixgbe_stop_adapter(hw);\n\n\t/*\n\t * Clear what we set, but we still keep shadow_vfta to\n\t * restore after device starts\n\t */\n\tixgbevf_set_vfta_all(dev,0);\n\n\t/* Clear stored conf */\n\tdev->data->scattered_rx = 0;\n\n\tixgbe_dev_clear_queues(dev);\n\n\t/* disable intr eventfd mapping */\n\trte_intr_disable(intr_handle);\n\n#ifdef RTE_NEXT_ABI\n\t/* Clean datapath event and queue/vec mapping */\n\trte_intr_efd_disable(intr_handle);\n\tif (intr_handle->intr_vec != NULL) {\n\t\trte_free(intr_handle->intr_vec);\n\t\tintr_handle->intr_vec = NULL;\n\t}\n#endif\n}\n\nstatic void\nixgbevf_dev_close(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n#ifdef RTE_NEXT_ABI\n\tstruct rte_pci_device *pci_dev;\n#endif\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tixgbe_reset_hw(hw);\n\n\tixgbevf_dev_stop(dev);\n\n\tixgbe_dev_free_queues(dev);\n\n\t/* reprogram the RAR[0] in case user changed it. */\n\tixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);\n\n#ifdef RTE_NEXT_ABI\n\tpci_dev = dev->pci_dev;\n\tif (pci_dev->intr_handle.intr_vec) {\n\t\trte_free(pci_dev->intr_handle.intr_vec);\n\t\tpci_dev->intr_handle.intr_vec = NULL;\n\t}\n#endif\n}\n\nstatic void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vfta * shadow_vfta =\n\t\tIXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);\n\tint i = 0, j = 0, vfta = 0, mask = 1;\n\n\tfor (i = 0; i < IXGBE_VFTA_SIZE; i++){\n\t\tvfta = shadow_vfta->vfta[i];\n\t\tif(vfta){\n\t\t\tmask = 1;\n\t\t\tfor (j = 0; j < 32; j++){\n\t\t\t\tif(vfta & mask)\n\t\t\t\t\tixgbe_set_vfta(hw, (i<<5)+j, 0, on);\n\t\t\t\tmask<<=1;\n\t\t\t}\n\t\t}\n\t}\n\n}\n\nstatic int\nixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vfta * shadow_vfta =\n\t\tIXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);\n\tuint32_t vid_idx = 0;\n\tuint32_t vid_bit = 0;\n\tint ret = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */\n\tret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);\n\tif(ret){\n\t\tPMD_INIT_LOG(ERR, \"Unable to set VF vlan\");\n\t\treturn ret;\n\t}\n\tvid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);\n\tvid_bit = (uint32_t) (1 << (vlan_id & 0x1F));\n\n\t/* Save what we set and retore it after device reset */\n\tif (on)\n\t\tshadow_vfta->vfta[vid_idx] |= vid_bit;\n\telse\n\t\tshadow_vfta->vfta[vid_idx] &= ~vid_bit;\n\n\treturn 0;\n}\n\nstatic void\nixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t ctrl;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif(queue >= hw->mac.max_rx_queues)\n\t\treturn;\n\n\tctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));\n\tif(on)\n\t\tctrl |= IXGBE_RXDCTL_VME;\n\telse\n\t\tctrl &= ~IXGBE_RXDCTL_VME;\n\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);\n\n\tixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);\n}\n\nstatic void\nixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint16_t i;\n\tint on = 0;\n\n\t/* VF function only support hw strip feature, others are not support */\n\tif(mask & ETH_VLAN_STRIP_MASK){\n\t\ton = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);\n\n\t\tfor(i=0; i < hw->mac.max_rx_queues; i++)\n\t\t\tixgbevf_vlan_strip_queue_set(dev,i,on);\n\t}\n}\n\nstatic int\nixgbe_vmdq_mode_check(struct ixgbe_hw *hw)\n{\n\tuint32_t reg_val;\n\n\t/* we only need to do this if VMDq is enabled */\n\treg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);\n\tif (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {\n\t\tPMD_INIT_LOG(ERR, \"VMDq must be enabled for this setting\");\n\t\treturn (-1);\n\t}\n\n\treturn 0;\n}\n\nstatic uint32_t\nixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)\n{\n\tuint32_t vector = 0;\n\tswitch (hw->mac.mc_filter_type) {\n\tcase 0: /* use bits [47:36] of the address */\n\t\tvector = ((uc_addr->addr_bytes[4] >> 4) |\n\t\t\t(((uint16_t)uc_addr->addr_bytes[5]) << 4));\n\t\tbreak;\n\tcase 1: /* use bits [46:35] of the address */\n\t\tvector = ((uc_addr->addr_bytes[4] >> 3) |\n\t\t\t(((uint16_t)uc_addr->addr_bytes[5]) << 5));\n\t\tbreak;\n\tcase 2: /* use bits [45:34] of the address */\n\t\tvector = ((uc_addr->addr_bytes[4] >> 2) |\n\t\t\t(((uint16_t)uc_addr->addr_bytes[5]) << 6));\n\t\tbreak;\n\tcase 3: /* use bits [43:32] of the address */\n\t\tvector = ((uc_addr->addr_bytes[4]) |\n\t\t\t(((uint16_t)uc_addr->addr_bytes[5]) << 8));\n\t\tbreak;\n\tdefault: /* Invalid mc_filter_type */\n\t\tbreak;\n\t}\n\n\t/* vector can only be 12-bits or boundary will be exceeded */\n\tvector &= 0xFFF;\n\treturn vector;\n}\n\nstatic int\nixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,\n\t\t\t uint8_t on)\n{\n\tuint32_t vector;\n\tuint32_t uta_idx;\n\tuint32_t reg_val;\n\tuint32_t uta_shift;\n\tuint32_t rc;\n\tconst uint32_t ixgbe_uta_idx_mask = 0x7F;\n\tconst uint32_t ixgbe_uta_bit_shift = 5;\n\tconst uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;\n\tconst uint32_t bit1 = 0x1;\n\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_uta_info *uta_info =\n\t\tIXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);\n\n\t/* The UTA table only exists on 82599 hardware and newer */\n\tif (hw->mac.type < ixgbe_mac_82599EB)\n\t\treturn (-ENOTSUP);\n\n\tvector = ixgbe_uta_vector(hw,mac_addr);\n\tuta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;\n\tuta_shift = vector & ixgbe_uta_bit_mask;\n\n\trc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);\n\tif(rc == on)\n\t\treturn 0;\n\n\treg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));\n\tif (on) {\n\t\tuta_info->uta_in_use++;\n\t\treg_val |= (bit1 << uta_shift);\n\t\tuta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);\n\t} else {\n\t\tuta_info->uta_in_use--;\n\t\treg_val &= ~(bit1 << uta_shift);\n\t\tuta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);\n\t}\n\n\tIXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);\n\n\tif (uta_info->uta_in_use > 0)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,\n\t\t\t\tIXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);\n\telse\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);\n\n\treturn 0;\n}\n\nstatic int\nixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)\n{\n\tint i;\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_uta_info *uta_info =\n\t\tIXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);\n\n\t/* The UTA table only exists on 82599 hardware and newer */\n\tif (hw->mac.type < ixgbe_mac_82599EB)\n\t\treturn (-ENOTSUP);\n\n\tif(on) {\n\t\tfor (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {\n\t\t\tuta_info->uta_shadow[i] = ~0;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);\n\t\t}\n\t} else {\n\t\tfor (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {\n\t\t\tuta_info->uta_shadow[i] = 0;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);\n\t\t}\n\t}\n\treturn 0;\n\n}\n\nuint32_t\nixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)\n{\n\tuint32_t new_val = orig_val;\n\n\tif (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)\n\t\tnew_val |= IXGBE_VMOLR_AUPE;\n\tif (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)\n\t\tnew_val |= IXGBE_VMOLR_ROMPE;\n\tif (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)\n\t\tnew_val |= IXGBE_VMOLR_ROPE;\n\tif (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)\n\t\tnew_val |= IXGBE_VMOLR_BAM;\n\tif (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)\n\t\tnew_val |= IXGBE_VMOLR_MPE;\n\n\treturn new_val;\n}\n\nstatic int\nixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,\n\t\t\t uint16_t rx_mask, uint8_t on)\n{\n\tint val = 0;\n\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));\n\n\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\tPMD_INIT_LOG(ERR, \"setting VF receive mode set should be done\"\n\t\t\t \" on 82599 hardware and newer\");\n\t\treturn (-ENOTSUP);\n\t}\n\tif (ixgbe_vmdq_mode_check(hw) < 0)\n\t\treturn (-ENOTSUP);\n\n\tval = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);\n\n\tif (on)\n\t\tvmolr |= val;\n\telse\n\t\tvmolr &= ~val;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);\n\n\treturn 0;\n}\n\nstatic int\nixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)\n{\n\tuint32_t reg,addr;\n\tuint32_t val;\n\tconst uint8_t bit1 = 0x1;\n\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (ixgbe_vmdq_mode_check(hw) < 0)\n\t\treturn (-ENOTSUP);\n\n\taddr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);\n\treg = IXGBE_READ_REG(hw, addr);\n\tval = bit1 << pool;\n\n\tif (on)\n\t\treg |= val;\n\telse\n\t\treg &= ~val;\n\n\tIXGBE_WRITE_REG(hw, addr,reg);\n\n\treturn 0;\n}\n\nstatic int\nixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)\n{\n\tuint32_t reg,addr;\n\tuint32_t val;\n\tconst uint8_t bit1 = 0x1;\n\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (ixgbe_vmdq_mode_check(hw) < 0)\n\t\treturn (-ENOTSUP);\n\n\taddr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);\n\treg = IXGBE_READ_REG(hw, addr);\n\tval = bit1 << pool;\n\n\tif (on)\n\t\treg |= val;\n\telse\n\t\treg &= ~val;\n\n\tIXGBE_WRITE_REG(hw, addr,reg);\n\n\treturn 0;\n}\n\nstatic int\nixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,\n\t\t\tuint64_t pool_mask, uint8_t vlan_on)\n{\n\tint ret = 0;\n\tuint16_t pool_idx;\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (ixgbe_vmdq_mode_check(hw) < 0)\n\t\treturn (-ENOTSUP);\n\tfor (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {\n\t\tif (pool_mask & ((uint64_t)(1ULL << pool_idx)))\n\t\t\tret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);\n\t\t\tif (ret < 0)\n\t\t\t\treturn ret;\n\t}\n\n\treturn ret;\n}\n\n#define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */\n#define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */\n#define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */\n#define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */\n#define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \\\n\t((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \\\n\tETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))\n\nstatic int\nixgbe_mirror_rule_set(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_mirror_conf *mirror_conf,\n\t\t\tuint8_t rule_id, uint8_t on)\n{\n\tuint32_t mr_ctl,vlvf;\n\tuint32_t mp_lsb = 0;\n\tuint32_t mv_msb = 0;\n\tuint32_t mv_lsb = 0;\n\tuint32_t mp_msb = 0;\n\tuint8_t i = 0;\n\tint reg_index = 0;\n\tuint64_t vlan_mask = 0;\n\n\tconst uint8_t pool_mask_offset = 32;\n\tconst uint8_t vlan_mask_offset = 32;\n\tconst uint8_t dst_pool_offset = 8;\n\tconst uint8_t rule_mr_offset = 4;\n\tconst uint8_t mirror_rule_mask= 0x0F;\n\n\tstruct ixgbe_mirror_info *mr_info =\n\t\t\t(IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint8_t mirror_type = 0;\n\n\tif (ixgbe_vmdq_mode_check(hw) < 0)\n\t\treturn -ENOTSUP;\n\n\tif (rule_id >= IXGBE_MAX_MIRROR_RULES)\n\t\treturn -EINVAL;\n\n\tif (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {\n\t\tPMD_DRV_LOG(ERR, \"unsupported mirror type 0x%x.\",\n\t\t\tmirror_conf->rule_type);\n\t\treturn -EINVAL;\n\t}\n\n\tif (mirror_conf->rule_type & ETH_MIRROR_VLAN) {\n\t\tmirror_type |= IXGBE_MRCTL_VLME;\n\t\t/* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */\n\t\tfor (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {\n\t\t\tif (mirror_conf->vlan.vlan_mask & (1ULL << i)) {\n\t\t\t\t/* search vlan id related pool vlan filter index */\n\t\t\t\treg_index = ixgbe_find_vlvf_slot(hw,\n\t\t\t\t\t\tmirror_conf->vlan.vlan_id[i]);\n\t\t\t\tif(reg_index < 0)\n\t\t\t\t\treturn -EINVAL;\n\t\t\t\tvlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));\n\t\t\t\tif ((vlvf & IXGBE_VLVF_VIEN) &&\n\t\t\t\t ((vlvf & IXGBE_VLVF_VLANID_MASK) ==\n\t\t\t\t mirror_conf->vlan.vlan_id[i]))\n\t\t\t\t\tvlan_mask |= (1ULL << reg_index);\n\t\t\t\telse\n\t\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t}\n\n\t\tif (on) {\n\t\t\tmv_lsb = vlan_mask & 0xFFFFFFFF;\n\t\t\tmv_msb = vlan_mask >> vlan_mask_offset;\n\n\t\t\tmr_info->mr_conf[rule_id].vlan.vlan_mask =\n\t\t\t\t\t\tmirror_conf->vlan.vlan_mask;\n\t\t\tfor(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {\n\t\t\t\tif(mirror_conf->vlan.vlan_mask & (1ULL << i))\n\t\t\t\t\tmr_info->mr_conf[rule_id].vlan.vlan_id[i] =\n\t\t\t\t\t\tmirror_conf->vlan.vlan_id[i];\n\t\t\t}\n\t\t} else {\n\t\t\tmv_lsb = 0;\n\t\t\tmv_msb = 0;\n\t\t\tmr_info->mr_conf[rule_id].vlan.vlan_mask = 0;\n\t\t\tfor(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)\n\t\t\t\tmr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;\n\t\t}\n\t}\n\n\t/*\n\t * if enable pool mirror, write related pool mask register,if disable\n\t * pool mirror, clear PFMRVM register\n\t */\n\tif (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {\n\t\tmirror_type |= IXGBE_MRCTL_VPME;\n\t\tif (on) {\n\t\t\tmp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;\n\t\t\tmp_msb = mirror_conf->pool_mask >> pool_mask_offset;\n\t\t\tmr_info->mr_conf[rule_id].pool_mask =\n\t\t\t\t\tmirror_conf->pool_mask;\n\n\t\t} else {\n\t\t\tmp_lsb = 0;\n\t\t\tmp_msb = 0;\n\t\t\tmr_info->mr_conf[rule_id].pool_mask = 0;\n\t\t}\n\t}\n\tif (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)\n\t\tmirror_type |= IXGBE_MRCTL_UPME;\n\tif (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)\n\t\tmirror_type |= IXGBE_MRCTL_DPME;\n\n\t/* read mirror control register and recalculate it */\n\tmr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));\n\n\tif (on) {\n\t\tmr_ctl |= mirror_type;\n\t\tmr_ctl &= mirror_rule_mask;\n\t\tmr_ctl |= mirror_conf->dst_pool << dst_pool_offset;\n\t} else\n\t\tmr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);\n\n\tmr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;\n\tmr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;\n\n\t/* write mirrror control register */\n\tIXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);\n\n\t/* write pool mirrror control register */\n\tif (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),\n\t\t\t\tmp_msb);\n\t}\n\t/* write VLAN mirrror control register */\n\tif (mirror_conf->rule_type == ETH_MIRROR_VLAN) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),\n\t\t\t\tmv_msb);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)\n{\n\tint mr_ctl = 0;\n\tuint32_t lsb_val = 0;\n\tuint32_t msb_val = 0;\n\tconst uint8_t rule_mr_offset = 4;\n\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_mirror_info *mr_info =\n\t\t(IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));\n\n\tif (ixgbe_vmdq_mode_check(hw) < 0)\n\t\treturn (-ENOTSUP);\n\n\tmemset(&mr_info->mr_conf[rule_id], 0,\n\t\tsizeof(struct rte_eth_mirror_conf));\n\n\t/* clear PFVMCTL register */\n\tIXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);\n\n\t/* clear pool mask register */\n\tIXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);\n\tIXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);\n\n\t/* clear vlan mask register */\n\tIXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);\n\tIXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);\n\n\treturn 0;\n}\n\n#ifdef RTE_NEXT_ABI\nstatic int\nixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n{\n\tuint32_t mask;\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tmask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);\n\tmask |= (1 << queue_id);\n\tIXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);\n\n\trte_intr_enable(&dev->pci_dev->intr_handle);\n\n\treturn 0;\n}\n\nstatic int\nixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)\n{\n\tuint32_t mask;\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tmask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);\n\tmask &= ~(1 << queue_id);\n\tIXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);\n\n\treturn 0;\n}\n\nstatic int\nixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)\n{\n\tuint32_t mask;\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_interrupt *intr =\n\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\tif (queue_id < 16) {\n\t\tixgbe_disable_intr(hw);\n\t\tintr->mask |= (1 << queue_id);\n\t\tixgbe_enable_intr(dev);\n\t} else if (queue_id < 32) {\n\t\tmask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));\n\t\tmask &= (1 << queue_id);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);\n\t} else if (queue_id < 64) {\n\t\tmask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));\n\t\tmask &= (1 << (queue_id - 32));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);\n\t}\n\trte_intr_enable(&dev->pci_dev->intr_handle);\n\n\treturn 0;\n}\n\nstatic int\nixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)\n{\n\tuint32_t mask;\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_interrupt *intr =\n\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\tif (queue_id < 16) {\n\t\tixgbe_disable_intr(hw);\n\t\tintr->mask &= ~(1 << queue_id);\n\t\tixgbe_enable_intr(dev);\n\t} else if (queue_id < 32) {\n\t\tmask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));\n\t\tmask &= ~(1 << queue_id);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);\n\t} else if (queue_id < 64) {\n\t\tmask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));\n\t\tmask &= ~(1 << (queue_id - 32));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);\n\t}\n\n\treturn 0;\n}\n\nstatic void\nixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,\n\t\t uint8_t queue, uint8_t msix_vector)\n{\n\tuint32_t tmp, idx;\n\n\tif (direction == -1) {\n\t\t/* other causes */\n\t\tmsix_vector |= IXGBE_IVAR_ALLOC_VAL;\n\t\ttmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);\n\t\ttmp &= ~0xFF;\n\t\ttmp |= msix_vector;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);\n\t} else {\n\t\t/* rx or tx cause */\n\t\tmsix_vector |= IXGBE_IVAR_ALLOC_VAL;\n\t\tidx = ((16 * (queue & 1)) + (8 * direction));\n\t\ttmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));\n\t\ttmp &= ~(0xFF << idx);\n\t\ttmp |= (msix_vector << idx);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);\n\t}\n}\n\n/**\n * set the IVAR registers, mapping interrupt causes to vectors\n * @param hw\n * pointer to ixgbe_hw struct\n * @direction\n * 0 for Rx, 1 for Tx, -1 for other causes\n * @queue\n * queue to map the corresponding interrupt to\n * @msix_vector\n * the vector to map to the corresponding queue\n */\nstatic void\nixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,\n\t\t uint8_t queue, uint8_t msix_vector)\n{\n\tuint32_t tmp, idx;\n\n\tmsix_vector |= IXGBE_IVAR_ALLOC_VAL;\n\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\tif (direction == -1)\n\t\t\tdirection = 0;\n\t\tidx = (((direction * 64) + queue) >> 2) & 0x1F;\n\t\ttmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));\n\t\ttmp &= ~(0xFF << (8 * (queue & 0x3)));\n\t\ttmp |= (msix_vector << (8 * (queue & 0x3)));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);\n\t} else if ((hw->mac.type == ixgbe_mac_82599EB) ||\n\t\t\t(hw->mac.type == ixgbe_mac_X540)) {\n\t\tif (direction == -1) {\n\t\t\t/* other causes */\n\t\t\tidx = ((queue & 1) * 8);\n\t\t\ttmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);\n\t\t\ttmp &= ~(0xFF << idx);\n\t\t\ttmp |= (msix_vector << idx);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);\n\t\t} else {\n\t\t\t/* rx or tx causes */\n\t\t\tidx = ((16 * (queue & 1)) + (8 * direction));\n\t\t\ttmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));\n\t\t\ttmp &= ~(0xFF << idx);\n\t\t\ttmp |= (msix_vector << idx);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);\n\t\t}\n\t}\n}\n#endif\n\nstatic void\nixgbevf_configure_msix(struct rte_eth_dev *dev)\n{\n\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n#ifdef RTE_NEXT_ABI\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t q_idx;\n\tuint32_t vector_idx = 0;\n#endif\n\n\t/* won't configure msix register if no mapping is done\n\t * between intr vector and event fd.\n\t */\n\tif (!rte_intr_dp_is_en(intr_handle))\n\t\treturn;\n\n#ifdef RTE_NEXT_ABI\n\t/* Configure all RX queues of VF */\n\tfor (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {\n\t\t/* Force all queue use vector 0,\n\t\t * as IXGBE_VF_MAXMSIVECOTR = 1\n\t\t */\n\t\tixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);\n\t\tintr_handle->intr_vec[q_idx] = vector_idx;\n\t}\n\n\t/* Configure VF Rx queue ivar */\n\tixgbevf_set_ivar_map(hw, -1, 1, vector_idx);\n#endif\n}\n\n/**\n * Sets up the hardware to properly generate MSI-X interrupts\n * @hw\n * board private structure\n */\nstatic void\nixgbe_configure_msix(struct rte_eth_dev *dev)\n{\n\tstruct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;\n#ifdef RTE_NEXT_ABI\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t queue_id, vec = 0;\n\tuint32_t mask;\n\tuint32_t gpie;\n#endif\n\n\t/* won't configure msix register if no mapping is done\n\t * between intr vector and event fd\n\t */\n\tif (!rte_intr_dp_is_en(intr_handle))\n\t\treturn;\n\n#ifdef RTE_NEXT_ABI\n\t/* setup GPIE for MSI-x mode */\n\tgpie = IXGBE_READ_REG(hw, IXGBE_GPIE);\n\tgpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |\n\t\tIXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;\n\t/* auto clearing and auto setting corresponding bits in EIMS\n\t * when MSI-X interrupt is triggered\n\t */\n\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);\n\t} else {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);\n\t}\n\tIXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);\n\n\t/* Populate the IVAR table and set the ITR values to the\n\t * corresponding register.\n\t */\n\tfor (queue_id = 0; queue_id < dev->data->nb_rx_queues;\n\t queue_id++) {\n\t\t/* by default, 1:1 mapping */\n\t\tixgbe_set_ivar_map(hw, 0, queue_id, vec);\n\t\tintr_handle->intr_vec[queue_id] = vec;\n\t\tif (vec < intr_handle->nb_efd - 1)\n\t\t\tvec++;\n\t}\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,\n\t\t\t\t intr_handle->max_intr - 1);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\t\tixgbe_set_ivar_map(hw, -1, 1, intr_handle->max_intr - 1);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\tIXGBE_WRITE_REG(hw, IXGBE_EITR(queue_id),\n\t\t\tIXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);\n\n\t/* set up to autoclear timer, and the vectors */\n\tmask = IXGBE_EIMS_ENABLE_MASK;\n\tmask &= ~(IXGBE_EIMS_OTHER |\n\t\t IXGBE_EIMS_MAILBOX |\n\t\t IXGBE_EIMS_LSC);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);\n#endif\n}\n\nstatic int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,\n\tuint16_t queue_idx, uint16_t tx_rate)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t rf_dec, rf_int;\n\tuint32_t bcnrc_val;\n\tuint16_t link_speed = dev->data->dev_link.link_speed;\n\n\tif (queue_idx >= hw->mac.max_tx_queues)\n\t\treturn -EINVAL;\n\n\tif (tx_rate != 0) {\n\t\t/* Calculate the rate factor values to set */\n\t\trf_int = (uint32_t)link_speed / (uint32_t)tx_rate;\n\t\trf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;\n\t\trf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;\n\n\t\tbcnrc_val = IXGBE_RTTBCNRC_RS_ENA;\n\t\tbcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &\n\t\t\t\tIXGBE_RTTBCNRC_RF_INT_MASK_M);\n\t\tbcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);\n\t} else {\n\t\tbcnrc_val = 0;\n\t}\n\n\t/*\n\t * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM\n\t * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise\n\t * set as 0x4.\n\t */\n\tif ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&\n\t\t(dev->data->dev_conf.rxmode.max_rx_pkt_len >=\n\t\t\t\tIXGBE_MAX_JUMBO_FRAME_SIZE))\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,\n\t\t\tIXGBE_MMW_SIZE_JUMBO_FRAME);\n\telse\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,\n\t\t\tIXGBE_MMW_SIZE_DEFAULT);\n\n\t/* Set RTTBCNRC of queue X */\n\tIXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);\n\tIXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\nstatic int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,\n\tuint16_t tx_rate, uint64_t q_msk)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));\n\tuint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;\n\tuint32_t queue_stride =\n\t\tIXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;\n\tuint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;\n\tuint32_t queue_end = queue_idx + nb_q_per_pool - 1;\n\tuint16_t total_rate = 0;\n\n\tif (queue_end >= hw->mac.max_tx_queues)\n\t\treturn -EINVAL;\n\n\tif (vfinfo != NULL) {\n\t\tfor (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {\n\t\t\tif (vf_idx == vf)\n\t\t\t\tcontinue;\n\t\t\tfor (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);\n\t\t\t\tidx++)\n\t\t\t\ttotal_rate += vfinfo[vf_idx].tx_rate[idx];\n\t\t}\n\t} else\n\t\treturn -EINVAL;\n\n\t/* Store tx_rate for this vf. */\n\tfor (idx = 0; idx < nb_q_per_pool; idx++) {\n\t\tif (((uint64_t)0x1 << idx) & q_msk) {\n\t\t\tif (vfinfo[vf].tx_rate[idx] != tx_rate)\n\t\t\t\tvfinfo[vf].tx_rate[idx] = tx_rate;\n\t\t\ttotal_rate += tx_rate;\n\t\t}\n\t}\n\n\tif (total_rate > dev->data->dev_link.link_speed) {\n\t\t/*\n\t\t * Reset stored TX rate of the VF if it causes exceed\n\t\t * link speed.\n\t\t */\n\t\tmemset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));\n\t\treturn -EINVAL;\n\t}\n\n\t/* Set RTTBCNRC of each queue/pool for vf X */\n\tfor (; queue_idx <= queue_end; queue_idx++) {\n\t\tif (0x1 & q_msk)\n\t\t\tixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);\n\t\tq_msk = q_msk >> 1;\n\t}\n\n\treturn 0;\n}\n\nstatic void\nixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,\n\t\t __attribute__((unused)) uint32_t index,\n\t\t __attribute__((unused)) uint32_t pool)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint diag;\n\n\t/*\n\t * On a 82599 VF, adding again the same MAC addr is not an idempotent\n\t * operation. Trap this case to avoid exhausting the [very limited]\n\t * set of PF resources used to store VF MAC addresses.\n\t */\n\tif (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)\n\t\treturn;\n\tdiag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);\n\tif (diag == 0)\n\t\treturn;\n\tPMD_DRV_LOG(ERR, \"Unable to add MAC address - diag=%d\", diag);\n}\n\nstatic void\nixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;\n\tstruct ether_addr *mac_addr;\n\tuint32_t i;\n\tint diag;\n\n\t/*\n\t * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does\n\t * not support the deletion of a given MAC address.\n\t * Instead, it imposes to delete all MAC addresses, then to add again\n\t * all MAC addresses with the exception of the one to be deleted.\n\t */\n\t(void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);\n\n\t/*\n\t * Add again all MAC addresses, with the exception of the deleted one\n\t * and of the permanent MAC address.\n\t */\n\tfor (i = 0, mac_addr = dev->data->mac_addrs;\n\t i < hw->mac.num_rar_entries; i++, mac_addr++) {\n\t\t/* Skip the deleted MAC address */\n\t\tif (i == index)\n\t\t\tcontinue;\n\t\t/* Skip NULL MAC addresses */\n\t\tif (is_zero_ether_addr(mac_addr))\n\t\t\tcontinue;\n\t\t/* Skip the permanent MAC address */\n\t\tif (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)\n\t\t\tcontinue;\n\t\tdiag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);\n\t\tif (diag != 0)\n\t\t\tPMD_DRV_LOG(ERR,\n\t\t\t\t \"Adding again MAC address \"\n\t\t\t\t \"%02x:%02x:%02x:%02x:%02x:%02x failed \"\n\t\t\t\t \"diag=%d\",\n\t\t\t\t mac_addr->addr_bytes[0],\n\t\t\t\t mac_addr->addr_bytes[1],\n\t\t\t\t mac_addr->addr_bytes[2],\n\t\t\t\t mac_addr->addr_bytes[3],\n\t\t\t\t mac_addr->addr_bytes[4],\n\t\t\t\t mac_addr->addr_bytes[5],\n\t\t\t\t diag);\n\t}\n}\n\nstatic void\nixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\thw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);\n}\n\n#define MAC_TYPE_FILTER_SUP(type) do {\\\n\tif ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\\\n\t\t(type) != ixgbe_mac_X550)\\\n\t\treturn -ENOTSUP;\\\n} while (0)\n\nstatic int\nixgbe_syn_filter_set(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_syn_filter *filter,\n\t\t\tbool add)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t synqf;\n\n\tif (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)\n\t\treturn -EINVAL;\n\n\tsynqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);\n\n\tif (add) {\n\t\tif (synqf & IXGBE_SYN_FILTER_ENABLE)\n\t\t\treturn -EINVAL;\n\t\tsynqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &\n\t\t\tIXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);\n\n\t\tif (filter->hig_pri)\n\t\t\tsynqf |= IXGBE_SYN_FILTER_SYNQFP;\n\t\telse\n\t\t\tsynqf &= ~IXGBE_SYN_FILTER_SYNQFP;\n\t} else {\n\t\tif (!(synqf & IXGBE_SYN_FILTER_ENABLE))\n\t\t\treturn -ENOENT;\n\t\tsynqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);\n\t}\n\tIXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);\n\tIXGBE_WRITE_FLUSH(hw);\n\treturn 0;\n}\n\nstatic int\nixgbe_syn_filter_get(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_syn_filter *filter)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);\n\n\tif (synqf & IXGBE_SYN_FILTER_ENABLE) {\n\t\tfilter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;\n\t\tfilter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);\n\t\treturn 0;\n\t}\n\treturn -ENOENT;\n}\n\nstatic int\nixgbe_syn_filter_handle(struct rte_eth_dev *dev,\n\t\t\tenum rte_filter_op filter_op,\n\t\t\tvoid *arg)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint ret;\n\n\tMAC_TYPE_FILTER_SUP(hw->mac.type);\n\n\tif (filter_op == RTE_ETH_FILTER_NOP)\n\t\treturn 0;\n\n\tif (arg == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"arg shouldn't be NULL for operation %u\",\n\t\t\t filter_op);\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_ADD:\n\t\tret = ixgbe_syn_filter_set(dev,\n\t\t\t\t(struct rte_eth_syn_filter *)arg,\n\t\t\t\tTRUE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_DELETE:\n\t\tret = ixgbe_syn_filter_set(dev,\n\t\t\t\t(struct rte_eth_syn_filter *)arg,\n\t\t\t\tFALSE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_GET:\n\t\tret = ixgbe_syn_filter_get(dev,\n\t\t\t\t(struct rte_eth_syn_filter *)arg);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unsupported operation %u\\n\", filter_op);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n\nstatic inline enum ixgbe_5tuple_protocol\nconvert_protocol_type(uint8_t protocol_value)\n{\n\tif (protocol_value == IPPROTO_TCP)\n\t\treturn IXGBE_FILTER_PROTOCOL_TCP;\n\telse if (protocol_value == IPPROTO_UDP)\n\t\treturn IXGBE_FILTER_PROTOCOL_UDP;\n\telse if (protocol_value == IPPROTO_SCTP)\n\t\treturn IXGBE_FILTER_PROTOCOL_SCTP;\n\telse\n\t\treturn IXGBE_FILTER_PROTOCOL_NONE;\n}\n\n/*\n * add a 5tuple filter\n *\n * @param\n * dev: Pointer to struct rte_eth_dev.\n * index: the index the filter allocates.\n * filter: ponter to the filter that will be added.\n * rx_queue: the queue id the filter assigned to.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nixgbe_add_5tuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct ixgbe_5tuple_filter *filter)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_filter_info *filter_info =\n\t\tIXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tint i, idx, shift;\n\tuint32_t ftqf, sdpqf;\n\tuint32_t l34timir = 0;\n\tuint8_t mask = 0xff;\n\n\t/*\n\t * look for an unused 5tuple filter index,\n\t * and insert the filter to list.\n\t */\n\tfor (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {\n\t\tidx = i / (sizeof(uint32_t) * NBBY);\n\t\tshift = i % (sizeof(uint32_t) * NBBY);\n\t\tif (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {\n\t\t\tfilter_info->fivetuple_mask[idx] |= 1 << shift;\n\t\t\tfilter->index = i;\n\t\t\tTAILQ_INSERT_TAIL(&filter_info->fivetuple_list,\n\t\t\t\t\t filter,\n\t\t\t\t\t entries);\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (i >= IXGBE_MAX_FTQF_FILTERS) {\n\t\tPMD_DRV_LOG(ERR, \"5tuple filters are full.\");\n\t\treturn -ENOSYS;\n\t}\n\n\tsdpqf = (uint32_t)(filter->filter_info.dst_port <<\n\t\t\t\tIXGBE_SDPQF_DSTPORT_SHIFT);\n\tsdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);\n\n\tftqf = (uint32_t)(filter->filter_info.proto &\n\t\tIXGBE_FTQF_PROTOCOL_MASK);\n\tftqf |= (uint32_t)((filter->filter_info.priority &\n\t\tIXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);\n\tif (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */\n\t\tmask &= IXGBE_FTQF_SOURCE_ADDR_MASK;\n\tif (filter->filter_info.dst_ip_mask == 0)\n\t\tmask &= IXGBE_FTQF_DEST_ADDR_MASK;\n\tif (filter->filter_info.src_port_mask == 0)\n\t\tmask &= IXGBE_FTQF_SOURCE_PORT_MASK;\n\tif (filter->filter_info.dst_port_mask == 0)\n\t\tmask &= IXGBE_FTQF_DEST_PORT_MASK;\n\tif (filter->filter_info.proto_mask == 0)\n\t\tmask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;\n\tftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;\n\tftqf |= IXGBE_FTQF_POOL_MASK_EN;\n\tftqf |= IXGBE_FTQF_QUEUE_ENABLE;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);\n\tIXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);\n\tIXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);\n\tIXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);\n\n\tl34timir |= IXGBE_L34T_IMIR_RESERVE;\n\tl34timir |= (uint32_t)(filter->queue <<\n\t\t\t\tIXGBE_L34T_IMIR_QUEUE_SHIFT);\n\tIXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);\n\treturn 0;\n}\n\n/*\n * remove a 5tuple filter\n *\n * @param\n * dev: Pointer to struct rte_eth_dev.\n * filter: the pointer of the filter will be removed.\n */\nstatic void\nixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct ixgbe_5tuple_filter *filter)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_filter_info *filter_info =\n\t\tIXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tuint16_t index = filter->index;\n\n\tfilter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=\n\t\t\t\t~(1 << (index % (sizeof(uint32_t) * NBBY)));\n\tTAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);\n\trte_free(filter);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);\n\tIXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);\n\tIXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);\n\tIXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);\n\tIXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);\n}\n\nstatic int\nixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)\n{\n\tstruct ixgbe_hw *hw;\n\tuint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))\n\t\treturn -EINVAL;\n\n\t/* refuse mtu that requires the support of scattered packets when this\n\t * feature has not been enabled before. */\n\tif (!dev->data->scattered_rx &&\n\t (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >\n\t dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))\n\t\treturn -EINVAL;\n\n\t/*\n\t * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU\n\t * request of the version 2.0 of the mailbox API.\n\t * For now, use the IXGBE_VF_SET_LPE request of the version 1.0\n\t * of the mailbox API.\n\t * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers\n\t * prior to 3.11.33 which contains the following change:\n\t * \"ixgbe: Enable jumbo frames support w/ SR-IOV\"\n\t */\n\tixgbevf_rlpml_set_vf(hw, max_frame);\n\n\t/* update max frame size */\n\tdev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;\n\treturn 0;\n}\n\n#define MAC_TYPE_FILTER_SUP_EXT(type) do {\\\n\tif ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\\\n\t\treturn -ENOTSUP;\\\n} while (0)\n\nstatic inline struct ixgbe_5tuple_filter *\nixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,\n\t\t\tstruct ixgbe_5tuple_filter_info *key)\n{\n\tstruct ixgbe_5tuple_filter *it;\n\n\tTAILQ_FOREACH(it, filter_list, entries) {\n\t\tif (memcmp(key, &it->filter_info,\n\t\t\tsizeof(struct ixgbe_5tuple_filter_info)) == 0) {\n\t\t\treturn it;\n\t\t}\n\t}\n\treturn NULL;\n}\n\n/* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/\nstatic inline int\nntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,\n\t\t\tstruct ixgbe_5tuple_filter_info *filter_info)\n{\n\tif (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||\n\t\tfilter->priority > IXGBE_5TUPLE_MAX_PRI ||\n\t\tfilter->priority < IXGBE_5TUPLE_MIN_PRI)\n\t\treturn -EINVAL;\n\n\tswitch (filter->dst_ip_mask) {\n\tcase UINT32_MAX:\n\t\tfilter_info->dst_ip_mask = 0;\n\t\tfilter_info->dst_ip = filter->dst_ip;\n\t\tbreak;\n\tcase 0:\n\t\tfilter_info->dst_ip_mask = 1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid dst_ip mask.\");\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter->src_ip_mask) {\n\tcase UINT32_MAX:\n\t\tfilter_info->src_ip_mask = 0;\n\t\tfilter_info->src_ip = filter->src_ip;\n\t\tbreak;\n\tcase 0:\n\t\tfilter_info->src_ip_mask = 1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid src_ip mask.\");\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter->dst_port_mask) {\n\tcase UINT16_MAX:\n\t\tfilter_info->dst_port_mask = 0;\n\t\tfilter_info->dst_port = filter->dst_port;\n\t\tbreak;\n\tcase 0:\n\t\tfilter_info->dst_port_mask = 1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid dst_port mask.\");\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter->src_port_mask) {\n\tcase UINT16_MAX:\n\t\tfilter_info->src_port_mask = 0;\n\t\tfilter_info->src_port = filter->src_port;\n\t\tbreak;\n\tcase 0:\n\t\tfilter_info->src_port_mask = 1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid src_port mask.\");\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter->proto_mask) {\n\tcase UINT8_MAX:\n\t\tfilter_info->proto_mask = 0;\n\t\tfilter_info->proto =\n\t\t\tconvert_protocol_type(filter->proto);\n\t\tbreak;\n\tcase 0:\n\t\tfilter_info->proto_mask = 1;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"invalid protocol mask.\");\n\t\treturn -EINVAL;\n\t}\n\n\tfilter_info->priority = (uint8_t)filter->priority;\n\treturn 0;\n}\n\n/*\n * add or delete a ntuple filter\n *\n * @param\n * dev: Pointer to struct rte_eth_dev.\n * ntuple_filter: Pointer to struct rte_eth_ntuple_filter\n * add: if true, add filter, if false, remove filter\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *ntuple_filter,\n\t\t\tbool add)\n{\n\tstruct ixgbe_filter_info *filter_info =\n\t\tIXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tstruct ixgbe_5tuple_filter_info filter_5tuple;\n\tstruct ixgbe_5tuple_filter *filter;\n\tint ret;\n\n\tif (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {\n\t\tPMD_DRV_LOG(ERR, \"only 5tuple is supported.\");\n\t\treturn -EINVAL;\n\t}\n\n\tmemset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));\n\tret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tfilter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,\n\t\t\t\t\t &filter_5tuple);\n\tif (filter != NULL && add) {\n\t\tPMD_DRV_LOG(ERR, \"filter exists.\");\n\t\treturn -EEXIST;\n\t}\n\tif (filter == NULL && !add) {\n\t\tPMD_DRV_LOG(ERR, \"filter doesn't exist.\");\n\t\treturn -ENOENT;\n\t}\n\n\tif (add) {\n\t\tfilter = rte_zmalloc(\"ixgbe_5tuple_filter\",\n\t\t\t\tsizeof(struct ixgbe_5tuple_filter), 0);\n\t\tif (filter == NULL)\n\t\t\treturn -ENOMEM;\n\t\t(void)rte_memcpy(&filter->filter_info,\n\t\t\t\t &filter_5tuple,\n\t\t\t\t sizeof(struct ixgbe_5tuple_filter_info));\n\t\tfilter->queue = ntuple_filter->queue;\n\t\tret = ixgbe_add_5tuple_filter(dev, filter);\n\t\tif (ret < 0) {\n\t\t\trte_free(filter);\n\t\t\treturn ret;\n\t\t}\n\t} else\n\t\tixgbe_remove_5tuple_filter(dev, filter);\n\n\treturn 0;\n}\n\n/*\n * get a ntuple filter\n *\n * @param\n * dev: Pointer to struct rte_eth_dev.\n * ntuple_filter: Pointer to struct rte_eth_ntuple_filter\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nixgbe_get_ntuple_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ntuple_filter *ntuple_filter)\n{\n\tstruct ixgbe_filter_info *filter_info =\n\t\tIXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tstruct ixgbe_5tuple_filter_info filter_5tuple;\n\tstruct ixgbe_5tuple_filter *filter;\n\tint ret;\n\n\tif (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {\n\t\tPMD_DRV_LOG(ERR, \"only 5tuple is supported.\");\n\t\treturn -EINVAL;\n\t}\n\n\tmemset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));\n\tret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tfilter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,\n\t\t\t\t\t &filter_5tuple);\n\tif (filter == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"filter doesn't exist.\");\n\t\treturn -ENOENT;\n\t}\n\tntuple_filter->queue = filter->queue;\n\treturn 0;\n}\n\n/*\n * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.\n * @dev: pointer to rte_eth_dev structure\n * @filter_op:operation will be taken.\n * @arg: a pointer to specific structure corresponding to the filter_op\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nstatic int\nixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,\n\t\t\t\tenum rte_filter_op filter_op,\n\t\t\t\tvoid *arg)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint ret;\n\n\tMAC_TYPE_FILTER_SUP_EXT(hw->mac.type);\n\n\tif (filter_op == RTE_ETH_FILTER_NOP)\n\t\treturn 0;\n\n\tif (arg == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"arg shouldn't be NULL for operation %u.\",\n\t\t\t filter_op);\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_ADD:\n\t\tret = ixgbe_add_del_ntuple_filter(dev,\n\t\t\t(struct rte_eth_ntuple_filter *)arg,\n\t\t\tTRUE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_DELETE:\n\t\tret = ixgbe_add_del_ntuple_filter(dev,\n\t\t\t(struct rte_eth_ntuple_filter *)arg,\n\t\t\tFALSE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_GET:\n\t\tret = ixgbe_get_ntuple_filter(dev,\n\t\t\t(struct rte_eth_ntuple_filter *)arg);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unsupported operation %u.\", filter_op);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\nstatic inline int\nixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,\n\t\t\tuint16_t ethertype)\n{\n\tint i;\n\n\tfor (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {\n\t\tif (filter_info->ethertype_filters[i] == ethertype &&\n\t\t (filter_info->ethertype_mask & (1 << i)))\n\t\t\treturn i;\n\t}\n\treturn -1;\n}\n\nstatic inline int\nixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,\n\t\t\tuint16_t ethertype)\n{\n\tint i;\n\n\tfor (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {\n\t\tif (!(filter_info->ethertype_mask & (1 << i))) {\n\t\t\tfilter_info->ethertype_mask |= 1 << i;\n\t\t\tfilter_info->ethertype_filters[i] = ethertype;\n\t\t\treturn i;\n\t\t}\n\t}\n\treturn -1;\n}\n\nstatic inline int\nixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,\n\t\t\tuint8_t idx)\n{\n\tif (idx >= IXGBE_MAX_ETQF_FILTERS)\n\t\treturn -1;\n\tfilter_info->ethertype_mask &= ~(1 << idx);\n\tfilter_info->ethertype_filters[idx] = 0;\n\treturn idx;\n}\n\nstatic int\nixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ethertype_filter *filter,\n\t\t\tbool add)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_filter_info *filter_info =\n\t\tIXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tuint32_t etqf = 0;\n\tuint32_t etqs = 0;\n\tint ret;\n\n\tif (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)\n\t\treturn -EINVAL;\n\n\tif (filter->ether_type == ETHER_TYPE_IPv4 ||\n\t\tfilter->ether_type == ETHER_TYPE_IPv6) {\n\t\tPMD_DRV_LOG(ERR, \"unsupported ether_type(0x%04x) in\"\n\t\t\t\" ethertype filter.\", filter->ether_type);\n\t\treturn -EINVAL;\n\t}\n\n\tif (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {\n\t\tPMD_DRV_LOG(ERR, \"mac compare is unsupported.\");\n\t\treturn -EINVAL;\n\t}\n\tif (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {\n\t\tPMD_DRV_LOG(ERR, \"drop option is unsupported.\");\n\t\treturn -EINVAL;\n\t}\n\n\tret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);\n\tif (ret >= 0 && add) {\n\t\tPMD_DRV_LOG(ERR, \"ethertype (0x%04x) filter exists.\",\n\t\t\t filter->ether_type);\n\t\treturn -EEXIST;\n\t}\n\tif (ret < 0 && !add) {\n\t\tPMD_DRV_LOG(ERR, \"ethertype (0x%04x) filter doesn't exist.\",\n\t\t\t filter->ether_type);\n\t\treturn -ENOENT;\n\t}\n\n\tif (add) {\n\t\tret = ixgbe_ethertype_filter_insert(filter_info,\n\t\t\tfilter->ether_type);\n\t\tif (ret < 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"ethertype filters are full.\");\n\t\t\treturn -ENOSYS;\n\t\t}\n\t\tetqf = IXGBE_ETQF_FILTER_EN;\n\t\tetqf |= (uint32_t)filter->ether_type;\n\t\tetqs |= (uint32_t)((filter->queue <<\n\t\t\t\t IXGBE_ETQS_RX_QUEUE_SHIFT) &\n\t\t\t\t IXGBE_ETQS_RX_QUEUE);\n\t\tetqs |= IXGBE_ETQS_QUEUE_EN;\n\t} else {\n\t\tret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);\n\t\tif (ret < 0)\n\t\t\treturn -ENOSYS;\n\t}\n\tIXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);\n\tIXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\nstatic int\nixgbe_get_ethertype_filter(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_ethertype_filter *filter)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_filter_info *filter_info =\n\t\tIXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);\n\tuint32_t etqf, etqs;\n\tint ret;\n\n\tret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);\n\tif (ret < 0) {\n\t\tPMD_DRV_LOG(ERR, \"ethertype (0x%04x) filter doesn't exist.\",\n\t\t\t filter->ether_type);\n\t\treturn -ENOENT;\n\t}\n\n\tetqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));\n\tif (etqf & IXGBE_ETQF_FILTER_EN) {\n\t\tetqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));\n\t\tfilter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;\n\t\tfilter->flags = 0;\n\t\tfilter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>\n\t\t\t IXGBE_ETQS_RX_QUEUE_SHIFT;\n\t\treturn 0;\n\t}\n\treturn -ENOENT;\n}\n\n/*\n * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.\n * @dev: pointer to rte_eth_dev structure\n * @filter_op:operation will be taken.\n * @arg: a pointer to specific structure corresponding to the filter_op\n */\nstatic int\nixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,\n\t\t\t\tenum rte_filter_op filter_op,\n\t\t\t\tvoid *arg)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint ret;\n\n\tMAC_TYPE_FILTER_SUP(hw->mac.type);\n\n\tif (filter_op == RTE_ETH_FILTER_NOP)\n\t\treturn 0;\n\n\tif (arg == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"arg shouldn't be NULL for operation %u.\",\n\t\t\t filter_op);\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_ADD:\n\t\tret = ixgbe_add_del_ethertype_filter(dev,\n\t\t\t(struct rte_eth_ethertype_filter *)arg,\n\t\t\tTRUE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_DELETE:\n\t\tret = ixgbe_add_del_ethertype_filter(dev,\n\t\t\t(struct rte_eth_ethertype_filter *)arg,\n\t\t\tFALSE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_GET:\n\t\tret = ixgbe_get_ethertype_filter(dev,\n\t\t\t(struct rte_eth_ethertype_filter *)arg);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unsupported operation %u.\", filter_op);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\treturn ret;\n}\n\nstatic int\nixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,\n\t\t enum rte_filter_type filter_type,\n\t\t enum rte_filter_op filter_op,\n\t\t void *arg)\n{\n\tint ret = -EINVAL;\n\n\tswitch (filter_type) {\n\tcase RTE_ETH_FILTER_NTUPLE:\n\t\tret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_ETHERTYPE:\n\t\tret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_SYN:\n\t\tret = ixgbe_syn_filter_handle(dev, filter_op, arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_FDIR:\n\t\tret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(WARNING, \"Filter type (%d) not supported\",\n\t\t\t\t\t\t\tfilter_type);\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic u8 *\nixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,\n\t\t\tu8 **mc_addr_ptr, u32 *vmdq)\n{\n\tu8 *mc_addr;\n\n\t*vmdq = 0;\n\tmc_addr = *mc_addr_ptr;\n\t*mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));\n\treturn mc_addr;\n}\n\nstatic int\nixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,\n\t\t\t struct ether_addr *mc_addr_set,\n\t\t\t uint32_t nb_mc_addr)\n{\n\tstruct ixgbe_hw *hw;\n\tu8 *mc_addr_list;\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tmc_addr_list = (u8 *)mc_addr_set;\n\treturn ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,\n\t\t\t\t\t ixgbe_dev_addr_list_itr, TRUE);\n}\n\nstatic int\nixgbe_timesync_enable(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t tsync_ctl;\n\tuint32_t tsauxc;\n\n\t/* Enable system time for platforms where it isn't on by default. */\n\ttsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);\n\ttsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;\n\tIXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);\n\n\t/* Start incrementing the register used to timestamp PTP packets. */\n\tIXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);\n\n\t/* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */\n\tIXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),\n\t\t\t(ETHER_TYPE_1588 |\n\t\t\t IXGBE_ETQF_FILTER_EN |\n\t\t\t IXGBE_ETQF_1588));\n\n\t/* Enable timestamping of received PTP packets. */\n\ttsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);\n\ttsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;\n\tIXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);\n\n\t/* Enable timestamping of transmitted PTP packets. */\n\ttsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);\n\ttsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;\n\tIXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);\n\n\treturn 0;\n}\n\nstatic int\nixgbe_timesync_disable(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t tsync_ctl;\n\n\t/* Disable timestamping of transmitted PTP packets. */\n\ttsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);\n\ttsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;\n\tIXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);\n\n\t/* Disable timestamping of received PTP packets. */\n\ttsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);\n\ttsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;\n\tIXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);\n\n\t/* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */\n\tIXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);\n\n\t/* Stop incrementating the System Time registers. */\n\tIXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);\n\n\treturn 0;\n}\n\nstatic int\nixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n\t\t\t\t struct timespec *timestamp,\n\t\t\t\t uint32_t flags __rte_unused)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t tsync_rxctl;\n\tuint32_t rx_stmpl;\n\tuint32_t rx_stmph;\n\n\ttsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);\n\tif ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)\n\t\treturn -EINVAL;\n\n\trx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);\n\trx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);\n\n\ttimestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);\n\ttimestamp->tv_nsec = 0;\n\n\treturn 0;\n}\n\nstatic int\nixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n\t\t\t\t struct timespec *timestamp)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t tsync_txctl;\n\tuint32_t tx_stmpl;\n\tuint32_t tx_stmph;\n\n\ttsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);\n\tif ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)\n\t\treturn -EINVAL;\n\n\ttx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);\n\ttx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);\n\n\ttimestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);\n\ttimestamp->tv_nsec = 0;\n\n\treturn 0;\n}\n\nstatic int\nixgbe_get_reg_length(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint count = 0;\n\tint g_ind = 0;\n\tconst struct reg_info *reg_group;\n\tconst struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?\n\t\t\t\t ixgbe_regs_mac_82598EB : ixgbe_regs_others;\n\n\twhile ((reg_group = reg_set[g_ind++]))\n\t\tcount += ixgbe_regs_group_count(reg_group);\n\n\treturn count;\n}\n\nstatic int\nixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)\n{\n\tint count = 0;\n\tint g_ind = 0;\n\tconst struct reg_info *reg_group;\n\n\twhile ((reg_group = ixgbevf_regs[g_ind++]))\n\t\tcount += ixgbe_regs_group_count(reg_group);\n\n\treturn count;\n}\n\nstatic int\nixgbe_get_regs(struct rte_eth_dev *dev,\n\t struct rte_dev_reg_info *regs)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t *data = regs->data;\n\tint g_ind = 0;\n\tint count = 0;\n\tconst struct reg_info *reg_group;\n\tconst struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?\n\t\t\t\t ixgbe_regs_mac_82598EB : ixgbe_regs_others;\n\n\t/* Support only full register dump */\n\tif ((regs->length == 0) ||\n\t (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {\n\t\tregs->version = hw->mac.type << 24 | hw->revision_id << 16 |\n\t\t\thw->device_id;\n\t\twhile ((reg_group = reg_set[g_ind++]))\n\t\t\tcount += ixgbe_read_regs_group(dev, &data[count],\n\t\t\t\treg_group);\n\t\treturn 0;\n\t}\n\n\treturn -ENOTSUP;\n}\n\nstatic int\nixgbevf_get_regs(struct rte_eth_dev *dev,\n\t\tstruct rte_dev_reg_info *regs)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t *data = regs->data;\n\tint g_ind = 0;\n\tint count = 0;\n\tconst struct reg_info *reg_group;\n\n\t/* Support only full register dump */\n\tif ((regs->length == 0) ||\n\t (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {\n\t\tregs->version = hw->mac.type << 24 | hw->revision_id << 16 |\n\t\t\thw->device_id;\n\t\twhile ((reg_group = ixgbevf_regs[g_ind++]))\n\t\t\tcount += ixgbe_read_regs_group(dev, &data[count],\n\t\t\t\t\t\t reg_group);\n\t\treturn 0;\n\t}\n\n\treturn -ENOTSUP;\n}\n\nstatic int\nixgbe_get_eeprom_length(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/* Return unit is byte count */\n\treturn hw->eeprom.word_size * 2;\n}\n\nstatic int\nixgbe_get_eeprom(struct rte_eth_dev *dev,\n\t\tstruct rte_dev_eeprom_info *in_eeprom)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\tuint16_t *data = in_eeprom->data;\n\tint first, length;\n\n\tfirst = in_eeprom->offset >> 1;\n\tlength = in_eeprom->length >> 1;\n\tif ((first >= hw->eeprom.word_size) ||\n\t ((first + length) >= hw->eeprom.word_size))\n\t\treturn -EINVAL;\n\n\tin_eeprom->magic = hw->vendor_id | (hw->device_id << 16);\n\n\treturn eeprom->ops.read_buffer(hw, first, length, data);\n}\n\nstatic int\nixgbe_set_eeprom(struct rte_eth_dev *dev,\n\t\tstruct rte_dev_eeprom_info *in_eeprom)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\tuint16_t *data = in_eeprom->data;\n\tint first, length;\n\n\tfirst = in_eeprom->offset >> 1;\n\tlength = in_eeprom->length >> 1;\n\tif ((first >= hw->eeprom.word_size) ||\n\t ((first + length) >= hw->eeprom.word_size))\n\t\treturn -EINVAL;\n\n\tin_eeprom->magic = hw->vendor_id | (hw->device_id << 16);\n\n\treturn eeprom->ops.write_buffer(hw, first, length, data);\n}\n\nstatic struct rte_driver rte_ixgbe_driver = {\n\t.type = PMD_PDEV,\n\t.init = rte_ixgbe_pmd_init,\n};\n\nstatic struct rte_driver rte_ixgbevf_driver = {\n\t.type = PMD_PDEV,\n\t.init = rte_ixgbevf_pmd_init,\n};\n\nPMD_REGISTER_DRIVER(rte_ixgbe_driver);\nPMD_REGISTER_DRIVER(rte_ixgbevf_driver);\n" }, { "path": "drivers/net/ixgbe/ixgbe_ethdev.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _IXGBE_ETHDEV_H_\n#define _IXGBE_ETHDEV_H_\n#include \"base/ixgbe_dcb.h\"\n#include \"base/ixgbe_dcb_82599.h\"\n#include \"base/ixgbe_dcb_82598.h\"\n#include \"ixgbe_bypass.h\"\n\n/* need update link, bit flag */\n#define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)\n#define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)\n\n/*\n * Defines that were not part of ixgbe_type.h as they are not used by the\n * FreeBSD driver.\n */\n#define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */\n#define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */\n#define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */\n#define IXGBE_RXDADV_ERR_CKSUM_BIT 30\n#define IXGBE_RXDADV_ERR_CKSUM_MSK 3\n#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */\n#define IXGBE_NB_STAT_MAPPING_REGS 32\n#define IXGBE_EXTENDED_VLAN\t (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */\n#define IXGBE_VFTA_SIZE 128\n#define IXGBE_VLAN_TAG_SIZE 4\n#define IXGBE_MAX_RX_QUEUE_NUM\t128\n#ifndef NBBY\n#define NBBY\t8\t/* number of bits in a byte */\n#endif\n#define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))\n\n/* EITR Inteval is in 2048ns uinits for 1G and 10G link */\n#define IXGBE_EITR_INTERVAL_UNIT_NS\t2048\n#define IXGBE_EITR_ITR_INT_SHIFT 3\n#define IXGBE_EITR_INTERVAL_US(us) \\\n\t(((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \\\n\t\tIXGBE_EITR_ITR_INT_MASK)\n\n\n/* Loopback operation modes */\n/* 82599 specific loopback operation types */\n#define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */\n#define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */\n\n#define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */\n\n#define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF\n#define IXGBE_RTTBCNRC_RF_INT_MASK_M \\\n\t(IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)\n\n#define IXGBE_MAX_QUEUE_NUM_PER_VF 8\n\n#define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */\n#define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */\n#define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */\n#define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */\n\n#define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */\n#define IXGBE_ETQF_SHIFT 16\n#define IXGBE_ETQF_UP_EN 0x00080000\n#define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */\n#define IXGBE_ETQF_MAX_PRI 7\n\n#define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */\n#define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */\n#define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */\n\n#define IXGBE_L34T_IMIR_SIZE_BP 0x00001000\n#define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */\n#define IXGBE_L34T_IMIR_LLI 0x00100000\n#define IXGBE_L34T_IMIR_QUEUE 0x0FE00000\n#define IXGBE_L34T_IMIR_QUEUE_SHIFT 21\n#define IXGBE_5TUPLE_MAX_PRI 7\n#define IXGBE_5TUPLE_MIN_PRI 1\n\n#define IXGBE_RSS_OFFLOAD_ALL ( \\\n\tETH_RSS_IPV4 | \\\n\tETH_RSS_NONFRAG_IPV4_TCP | \\\n\tETH_RSS_NONFRAG_IPV4_UDP | \\\n\tETH_RSS_IPV6 | \\\n\tETH_RSS_NONFRAG_IPV6_TCP | \\\n\tETH_RSS_NONFRAG_IPV6_UDP | \\\n\tETH_RSS_IPV6_EX | \\\n\tETH_RSS_IPV6_TCP_EX | \\\n\tETH_RSS_IPV6_UDP_EX)\n\n#define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */\n#define IXGBE_VF_MAXMSIVECTOR 1\n\n/*\n * Information about the fdir mode.\n */\n\nstruct ixgbe_hw_fdir_mask {\n\tuint16_t vlan_tci_mask;\n\tuint32_t src_ipv4_mask;\n\tuint32_t dst_ipv4_mask;\n\tuint16_t src_ipv6_mask;\n\tuint16_t dst_ipv6_mask;\n\tuint16_t src_port_mask;\n\tuint16_t dst_port_mask;\n\tuint16_t flex_bytes_mask;\n};\n\nstruct ixgbe_hw_fdir_info {\n\tstruct ixgbe_hw_fdir_mask mask;\n\tuint8_t flex_bytes_offset;\n\tuint16_t collision;\n\tuint16_t free;\n\tuint16_t maxhash;\n\tuint8_t maxlen;\n\tuint64_t add;\n\tuint64_t remove;\n\tuint64_t f_add;\n\tuint64_t f_remove;\n};\n\n/* structure for interrupt relative data */\nstruct ixgbe_interrupt {\n\tuint32_t flags;\n\tuint32_t mask;\n};\n\nstruct ixgbe_stat_mapping_registers {\n\tuint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];\n\tuint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];\n};\n\nstruct ixgbe_vfta {\n\tuint32_t vfta[IXGBE_VFTA_SIZE];\n};\n\nstruct ixgbe_hwstrip {\n\tuint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];\n};\n\n/*\n * VF data which used by PF host only\n */\n#define IXGBE_MAX_VF_MC_ENTRIES\t\t30\n#define IXGBE_MAX_MR_RULE_ENTRIES\t4 /* number of mirroring rules supported */\n#define IXGBE_MAX_UTA 128\n\nstruct ixgbe_uta_info {\n\tuint8_t uc_filter_type;\n\tuint16_t uta_in_use;\n\tuint32_t uta_shadow[IXGBE_MAX_UTA];\n};\n\n#define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */\n\nstruct ixgbe_mirror_info {\n\tstruct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];\n\t/**< store PF mirror rules configuration*/\n};\n\nstruct ixgbe_vf_info {\n\tuint8_t vf_mac_addresses[ETHER_ADDR_LEN];\n\tuint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];\n\tuint16_t num_vf_mc_hashes;\n\tuint16_t default_vf_vlan_id;\n\tuint16_t vlans_enabled;\n\tbool clear_to_send;\n\tuint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];\n\tuint16_t vlan_count;\n\tuint8_t spoofchk_enabled;\n\tuint8_t api_version;\n};\n\n/*\n * Possible l4type of 5tuple filters.\n */\nenum ixgbe_5tuple_protocol {\n\tIXGBE_FILTER_PROTOCOL_TCP = 0,\n\tIXGBE_FILTER_PROTOCOL_UDP,\n\tIXGBE_FILTER_PROTOCOL_SCTP,\n\tIXGBE_FILTER_PROTOCOL_NONE,\n};\n\nTAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);\n\nstruct ixgbe_5tuple_filter_info {\n\tuint32_t dst_ip;\n\tuint32_t src_ip;\n\tuint16_t dst_port;\n\tuint16_t src_port;\n\tenum ixgbe_5tuple_protocol proto; /* l4 protocol. */\n\tuint8_t priority; /* seven levels (001b-111b), 111b is highest,\n\t\t\t\t used when more than one filter matches. */\n\tuint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */\n\t\tsrc_ip_mask:1, /* if mask is 1b, do not compare src ip. */\n\t\tdst_port_mask:1, /* if mask is 1b, do not compare dst port. */\n\t\tsrc_port_mask:1, /* if mask is 1b, do not compare src port. */\n\t\tproto_mask:1; /* if mask is 1b, do not compare protocol. */\n};\n\n/* 5tuple filter structure */\nstruct ixgbe_5tuple_filter {\n\tTAILQ_ENTRY(ixgbe_5tuple_filter) entries;\n\tuint16_t index; /* the index of 5tuple filter */\n\tstruct ixgbe_5tuple_filter_info filter_info;\n\tuint16_t queue; /* rx queue assigned to */\n};\n\n#define IXGBE_5TUPLE_ARRAY_SIZE \\\n\t(RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \\\n\t (sizeof(uint32_t) * NBBY))\n\n/*\n * Structure to store filters' info.\n */\nstruct ixgbe_filter_info {\n\tuint8_t ethertype_mask; /* Bit mask for every used ethertype filter */\n\t/* store used ethertype filters*/\n\tuint16_t ethertype_filters[IXGBE_MAX_ETQF_FILTERS];\n\t/* Bit mask for every used 5tuple filter */\n\tuint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];\n\tstruct ixgbe_5tuple_filter_list fivetuple_list;\n};\n\n/*\n * Structure to store private data for each driver instance (for each port).\n */\nstruct ixgbe_adapter {\n\tstruct ixgbe_hw hw;\n\tstruct ixgbe_hw_stats stats;\n\tstruct ixgbe_hw_fdir_info fdir;\n\tstruct ixgbe_interrupt intr;\n\tstruct ixgbe_stat_mapping_registers stat_mappings;\n\tstruct ixgbe_vfta shadow_vfta;\n\tstruct ixgbe_hwstrip\t\thwstrip;\n\tstruct ixgbe_dcb_config dcb_config;\n\tstruct ixgbe_mirror_info mr_data;\n\tstruct ixgbe_vf_info *vfdata;\n\tstruct ixgbe_uta_info uta_info;\n#ifdef RTE_NIC_BYPASS\n\tstruct ixgbe_bypass_info bps;\n#endif /* RTE_NIC_BYPASS */\n\tstruct ixgbe_filter_info filter;\n\n\tbool rx_bulk_alloc_allowed;\n\tbool rx_vec_allowed;\n};\n\n#define IXGBE_DEV_PRIVATE_TO_HW(adapter)\\\n\t(&((struct ixgbe_adapter *)adapter)->hw)\n\n#define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \\\n\t(&((struct ixgbe_adapter *)adapter)->stats)\n\n#define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \\\n\t(&((struct ixgbe_adapter *)adapter)->intr)\n\n#define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \\\n\t(&((struct ixgbe_adapter *)adapter)->fdir)\n\n#define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \\\n\t(&((struct ixgbe_adapter *)adapter)->stat_mappings)\n\n#define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \\\n\t(&((struct ixgbe_adapter *)adapter)->shadow_vfta)\n\n#define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \\\n\t(&((struct ixgbe_adapter *)adapter)->hwstrip)\n\n#define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \\\n\t(&((struct ixgbe_adapter *)adapter)->dcb_config)\n\n#define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \\\n\t(&((struct ixgbe_adapter *)adapter)->vfdata)\n\n#define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \\\n\t(&((struct ixgbe_adapter *)adapter)->mr_data)\n\n#define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \\\n\t(&((struct ixgbe_adapter *)adapter)->uta_info)\n\n#define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \\\n\t(&((struct ixgbe_adapter *)adapter)->filter)\n\n/*\n * RX/TX function prototypes\n */\nvoid ixgbe_dev_clear_queues(struct rte_eth_dev *dev);\n\nvoid ixgbe_dev_free_queues(struct rte_eth_dev *dev);\n\nvoid ixgbe_dev_rx_queue_release(void *rxq);\n\nvoid ixgbe_dev_tx_queue_release(void *txq);\n\nint ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n\t\tuint16_t nb_rx_desc, unsigned int socket_id,\n\t\tconst struct rte_eth_rxconf *rx_conf,\n\t\tstruct rte_mempool *mb_pool);\n\nint ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n\t\tuint16_t nb_tx_desc, unsigned int socket_id,\n\t\tconst struct rte_eth_txconf *tx_conf);\n\nuint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,\n\t\tuint16_t rx_queue_id);\n\nint ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);\nint ixgbevf_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);\n\nint ixgbe_dev_rx_init(struct rte_eth_dev *dev);\n\nvoid ixgbe_dev_tx_init(struct rte_eth_dev *dev);\n\nint ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);\n\nint ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n\nint ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n\nint ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n\nint ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n\nint ixgbevf_dev_rx_init(struct rte_eth_dev *dev);\n\nvoid ixgbevf_dev_tx_init(struct rte_eth_dev *dev);\n\nvoid ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);\n\nuint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts);\n\nuint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,\n\t\tstruct rte_mbuf **rx_pkts, uint16_t nb_pkts);\nuint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,\n\t\tstruct rte_mbuf **rx_pkts, uint16_t nb_pkts);\n\nuint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t\tuint16_t nb_pkts);\n\nuint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t\tuint16_t nb_pkts);\n\nint ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_conf *rss_conf);\n\nint ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_rss_conf *rss_conf);\n\n/*\n * Flow director function prototypes\n */\nint ixgbe_fdir_configure(struct rte_eth_dev *dev);\n\nvoid ixgbe_configure_dcb(struct rte_eth_dev *dev);\n\n/*\n * misc function prototypes\n */\nvoid ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);\n\nvoid ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);\n\nvoid ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);\n\nvoid ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);\n\nvoid ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);\n\nvoid ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);\n\nvoid ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);\n\nint ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);\n\nuint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);\n\nint ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,\n\t\t\tenum rte_filter_op filter_op, void *arg);\n#endif /* _IXGBE_ETHDEV_H_ */\n" }, { "path": "drivers/net/ixgbe/ixgbe_fdir.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"ixgbe_logs.h\"\n#include \"base/ixgbe_api.h\"\n#include \"base/ixgbe_common.h\"\n#include \"ixgbe_ethdev.h\"\n\n/* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */\n#define FDIRCTRL_PBALLOC_MASK 0x03\n\n/* For calculating memory required for FDIR filters */\n#define PBALLOC_SIZE_SHIFT 15\n\n/* Number of bits used to mask bucket hash for different pballoc sizes */\n#define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */\n#define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */\n#define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */\n#define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */\n#define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */\n#define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */\n#define IXGBE_DEFAULT_FLEXBYTES_OFFSET 12 /* default flexbytes offset in bytes */\n#define IXGBE_FDIR_MAX_FLEX_LEN 2 /* len in bytes of flexbytes */\n#define IXGBE_MAX_FLX_SOURCE_OFF 62\n#define IXGBE_FDIRCTRL_FLEX_MASK (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)\n#define IXGBE_FDIRCMD_CMD_INTERVAL_US 10\n\n#define IXGBE_FDIR_FLOW_TYPES ( \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \\\n\t(1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))\n\n#define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \\\n\tuint8_t ipv6_addr[16]; \\\n\tuint8_t i; \\\n\trte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\\\n\t(ipv6m) = 0; \\\n\tfor (i = 0; i < sizeof(ipv6_addr); i++) { \\\n\t\tif (ipv6_addr[i] == UINT8_MAX) \\\n\t\t\t(ipv6m) |= 1 << i; \\\n\t\telse if (ipv6_addr[i] != 0) { \\\n\t\t\tPMD_DRV_LOG(ERR, \" invalid IPv6 address mask.\"); \\\n\t\t\treturn -EINVAL; \\\n\t\t} \\\n\t} \\\n} while (0)\n\n#define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \\\n\tuint8_t ipv6_addr[16]; \\\n\tuint8_t i; \\\n\tfor (i = 0; i < sizeof(ipv6_addr); i++) { \\\n\t\tif ((ipv6m) & (1 << i)) \\\n\t\t\tipv6_addr[i] = UINT8_MAX; \\\n\t\telse \\\n\t\t\tipv6_addr[i] = 0; \\\n\t} \\\n\trte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\\\n} while (0)\n\nstatic int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);\nstatic int fdir_set_input_mask_82599(struct rte_eth_dev *dev,\n\t\tconst struct rte_eth_fdir_masks *input_mask);\nstatic int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,\n\t\tconst struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl);\nstatic int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);\nstatic int ixgbe_fdir_filter_to_atr_input(\n\t\tconst struct rte_eth_fdir_filter *fdir_filter,\n\t\tunion ixgbe_atr_input *input);\nstatic uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,\n\t\t\t\t uint32_t key);\nstatic uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,\n\t\tenum rte_fdir_pballoc_type pballoc);\nstatic uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,\n\t\tenum rte_fdir_pballoc_type pballoc);\nstatic int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\tunion ixgbe_atr_input *input, uint8_t queue,\n\t\t\tuint32_t fdircmd, uint32_t fdirhash);\nstatic int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,\n\t\tunion ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,\n\t\tuint32_t fdirhash);\nstatic int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,\n\t\t\t const struct rte_eth_fdir_filter *fdir_filter,\n\t\t\t bool del,\n\t\t\t bool update);\nstatic int ixgbe_fdir_flush(struct rte_eth_dev *dev);\nstatic void ixgbe_fdir_info_get(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_fdir_info *fdir_info);\nstatic void ixgbe_fdir_stats_get(struct rte_eth_dev *dev,\n\t\t\tstruct rte_eth_fdir_stats *fdir_stats);\n\n/**\n * This function is based on ixgbe_fdir_enable_82599() in base/ixgbe_82599.c.\n * It adds extra configuration of fdirctrl that is common for all filter types.\n *\n * Initialize Flow Director control registers\n * @hw: pointer to hardware structure\n * @fdirctrl: value to write to flow director control register\n **/\nstatic int\nfdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)\n{\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* Prime the keys for hashing */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);\n\n\t/*\n\t * Continue setup of fdirctrl register bits:\n\t * Set the maximum length per hash bucket to 0xA filters\n\t * Send interrupt when 64 filters are left\n\t */\n\tfdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |\n\t\t (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);\n\n\t/*\n\t * Poll init-done after we write the register. Estimated times:\n\t * 10G: PBALLOC = 11b, timing is 60us\n\t * 1G: PBALLOC = 11b, timing is 600us\n\t * 100M: PBALLOC = 11b, timing is 6ms\n\t *\n\t * Multiple these timings by 4 if under full Rx load\n\t *\n\t * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for\n\t * 1 msec per poll time. If we're at line rate and drop to 100M, then\n\t * this might not finish in our poll time, but we can live with that\n\t * for now.\n\t */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);\n\tIXGBE_WRITE_FLUSH(hw);\n\tfor (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {\n\t\tif (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &\n\t\t IXGBE_FDIRCTRL_INIT_DONE)\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t}\n\n\tif (i >= IXGBE_FDIR_INIT_DONE_POLL) {\n\t\tPMD_INIT_LOG(ERR, \"Flow Director poll time exceeded \"\n\t\t\t\"during enabling!\");\n\t\treturn -ETIMEDOUT;\n\t}\n\treturn 0;\n}\n\n/*\n * Set appropriate bits in fdirctrl for: variable reporting levels, moving\n * flexbytes matching field, and drop queue (only for perfect matching mode).\n */\nstatic inline int\nconfigure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)\n{\n\t*fdirctrl = 0;\n\n\tswitch (conf->pballoc) {\n\tcase RTE_FDIR_PBALLOC_64K:\n\t\t/* 8k - 1 signature filters */\n\t\t*fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;\n\t\tbreak;\n\tcase RTE_FDIR_PBALLOC_128K:\n\t\t/* 16k - 1 signature filters */\n\t\t*fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;\n\t\tbreak;\n\tcase RTE_FDIR_PBALLOC_256K:\n\t\t/* 32k - 1 signature filters */\n\t\t*fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;\n\t\tbreak;\n\tdefault:\n\t\t/* bad value */\n\t\tPMD_INIT_LOG(ERR, \"Invalid fdir_conf->pballoc value\");\n\t\treturn -EINVAL;\n\t};\n\n\t/* status flags: write hash & swindex in the rx descriptor */\n\tswitch (conf->status) {\n\tcase RTE_FDIR_NO_REPORT_STATUS:\n\t\t/* do nothing, default mode */\n\t\tbreak;\n\tcase RTE_FDIR_REPORT_STATUS:\n\t\t/* report status when the packet matches a fdir rule */\n\t\t*fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;\n\t\tbreak;\n\tcase RTE_FDIR_REPORT_STATUS_ALWAYS:\n\t\t/* always report status */\n\t\t*fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;\n\t\tbreak;\n\tdefault:\n\t\t/* bad value */\n\t\tPMD_INIT_LOG(ERR, \"Invalid fdir_conf->status value\");\n\t\treturn -EINVAL;\n\t};\n\n\t*fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<\n\t\t IXGBE_FDIRCTRL_FLEX_SHIFT;\n\n\tif (conf->mode == RTE_FDIR_MODE_PERFECT) {\n\t\t*fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;\n\t\t*fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);\n\t}\n\n\treturn 0;\n}\n\n/**\n * Reverse the bits in FDIR registers that store 2 x 16 bit masks.\n *\n * @hi_dword: Bits 31:16 mask to be bit swapped.\n * @lo_dword: Bits 15:0 mask to be bit swapped.\n *\n * Flow director uses several registers to store 2 x 16 bit masks with the\n * bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the\n * mask affects the MS bit/byte of the target. This function reverses the\n * bits in these masks.\n * **/\nstatic inline uint32_t\nreverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)\n{\n\tuint32_t mask = hi_dword << 16;\n\tmask |= lo_dword;\n\tmask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);\n\tmask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);\n\tmask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);\n\treturn ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);\n}\n\n/*\n * This is based on ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,\n * but makes use of the rte_fdir_masks structure to see which bits to set.\n */\nstatic int\nfdir_set_input_mask_82599(struct rte_eth_dev *dev,\n\t\tconst struct rte_eth_fdir_masks *input_mask)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_hw_fdir_info *info =\n\t\t\tIXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);\n\t/*\n\t * mask VM pool and DIPv6 since there are currently not supported\n\t * mask FLEX byte, it will be set in flex_conf\n\t */\n\tuint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 | IXGBE_FDIRM_FLEX;\n\tuint32_t fdirtcpm; /* TCP source and destination port masks. */\n\tuint32_t fdiripv6m; /* IPv6 source and destination masks. */\n\tuint16_t dst_ipv6m = 0;\n\tuint16_t src_ipv6m = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/*\n\t * Program the relevant mask registers. If src/dst_port or src/dst_addr\n\t * are zero, then assume a full mask for that field. Also assume that\n\t * a VLAN of 0 is unspecified, so mask that out as well. L4type\n\t * cannot be masked out in this implementation.\n\t */\n\tif (input_mask->dst_port_mask == 0 && input_mask->src_port_mask == 0)\n\t\t/* use the L4 protocol mask for raw IPv4/IPv6 traffic */\n\t\tfdirm |= IXGBE_FDIRM_L4P;\n\n\tif (input_mask->vlan_tci_mask == 0x0FFF)\n\t\t/* mask VLAN Priority */\n\t\tfdirm |= IXGBE_FDIRM_VLANP;\n\telse if (input_mask->vlan_tci_mask == 0xE000)\n\t\t/* mask VLAN ID */\n\t\tfdirm |= IXGBE_FDIRM_VLANID;\n\telse if (input_mask->vlan_tci_mask == 0)\n\t\t/* mask VLAN ID and Priority */\n\t\tfdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;\n\telse if (input_mask->vlan_tci_mask != 0xEFFF) {\n\t\tPMD_INIT_LOG(ERR, \"invalid vlan_tci_mask\");\n\t\treturn -EINVAL;\n\t}\n\tinfo->mask.vlan_tci_mask = input_mask->vlan_tci_mask;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);\n\n\t/* store the TCP/UDP port masks, bit reversed from port layout */\n\tfdirtcpm = reverse_fdir_bitmasks(input_mask->dst_port_mask,\n\t\t\t\t\t input_mask->src_port_mask);\n\n\t/* write all the same so that UDP, TCP and SCTP use the same mask */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);\n\tinfo->mask.src_port_mask = input_mask->src_port_mask;\n\tinfo->mask.dst_port_mask = input_mask->dst_port_mask;\n\n\t/* Store source and destination IPv4 masks (big-endian) */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, ~(input_mask->ipv4_mask.src_ip));\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, ~(input_mask->ipv4_mask.dst_ip));\n\tinfo->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;\n\tinfo->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;\n\n\tif (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {\n\t\t/*\n\t\t * IPv6 mask is only meaningful in signature mode\n\t\t * Store source and destination IPv6 masks (bit reversed)\n\t\t */\n\t\tIPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);\n\t\tIPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);\n\t\tfdiripv6m = (dst_ipv6m << 16) | src_ipv6m;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);\n\t\tinfo->mask.src_ipv6_mask = src_ipv6m;\n\t\tinfo->mask.dst_ipv6_mask = dst_ipv6m;\n\t}\n\n\treturn IXGBE_SUCCESS;\n}\n\n/*\n * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration\n * arguments are valid\n */\nstatic int\nixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,\n\t\tconst struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_hw_fdir_info *info =\n\t\t\tIXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);\n\tconst struct rte_eth_flex_payload_cfg *flex_cfg;\n\tconst struct rte_eth_fdir_flex_mask *flex_mask;\n\tuint32_t fdirm;\n\tuint16_t flexbytes = 0;\n\tuint16_t i;\n\n\tfdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);\n\n\tif (conf == NULL) {\n\t\tPMD_DRV_LOG(ERR, \"NULL pointer.\");\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < conf->nb_payloads; i++) {\n\t\tflex_cfg = &conf->flex_set[i];\n\t\tif (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {\n\t\t\tPMD_DRV_LOG(ERR, \"unsupported payload type.\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tif (((flex_cfg->src_offset[0] & 0x1) == 0) &&\n\t\t (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&\n\t\t (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {\n\t\t\t*fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;\n\t\t\t*fdirctrl |=\n\t\t\t\t(flex_cfg->src_offset[0] / sizeof(uint16_t)) <<\n\t\t\t\t\tIXGBE_FDIRCTRL_FLEX_SHIFT;\n\t\t} else {\n\t\t\tPMD_DRV_LOG(ERR, \"invalid flexbytes arguments.\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\tfor (i = 0; i < conf->nb_flexmasks; i++) {\n\t\tflex_mask = &conf->flex_mask[i];\n\t\tif (flex_mask->flow_type != RTE_ETH_FLOW_UNKNOWN) {\n\t\t\tPMD_DRV_LOG(ERR, \"flexmask should be set globally.\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tflexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |\n\t\t\t\t\t((flex_mask->mask[1]) & 0xFF));\n\t\tif (flexbytes == UINT16_MAX)\n\t\t\tfdirm &= ~IXGBE_FDIRM_FLEX;\n\t\telse if (flexbytes != 0) {\n\t\t\t/* IXGBE_FDIRM_FLEX is set by default when set mask */\n\t\t\tPMD_DRV_LOG(ERR, \" invalid flexbytes mask arguments.\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);\n\tinfo->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;\n\tinfo->flex_bytes_offset = (uint8_t)((*fdirctrl &\n\t\t\t\t\t IXGBE_FDIRCTRL_FLEX_MASK) >>\n\t\t\t\t\t IXGBE_FDIRCTRL_FLEX_SHIFT);\n\treturn 0;\n}\n\nint\nixgbe_fdir_configure(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint err;\n\tuint32_t fdirctrl, pbsize;\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (hw->mac.type != ixgbe_mac_82599EB &&\n\t\thw->mac.type != ixgbe_mac_X540 &&\n\t\thw->mac.type != ixgbe_mac_X550 &&\n\t\thw->mac.type != ixgbe_mac_X550EM_x)\n\t\treturn -ENOSYS;\n\n\terr = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);\n\tif (err)\n\t\treturn err;\n\n\t/*\n\t * Before enabling Flow Director, the Rx Packet Buffer size\n\t * must be reduced. The new value is the current size minus\n\t * flow director memory usage size.\n\t */\n\tpbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));\n\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),\n\t (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));\n\n\t/*\n\t * The defaults in the HW for RX PB 1-7 are not zero and so should be\n\t * intialized to zero for non DCB mode otherwise actual total RX PB\n\t * would be bigger than programmed and filter space would run into\n\t * the PB 0 region.\n\t */\n\tfor (i = 1; i < 8; i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);\n\n\terr = fdir_set_input_mask_82599(dev, &dev->data->dev_conf.fdir_conf.mask);\n\tif (err < 0) {\n\t\tPMD_INIT_LOG(ERR, \" Error on setting FD mask\");\n\t\treturn err;\n\t}\n\terr = ixgbe_set_fdir_flex_conf(dev,\n\t\t&dev->data->dev_conf.fdir_conf.flex_conf, &fdirctrl);\n\tif (err < 0) {\n\t\tPMD_INIT_LOG(ERR, \" Error on setting FD flexible arguments.\");\n\t\treturn err;\n\t}\n\n\terr = fdir_enable_82599(hw, fdirctrl);\n\tif (err < 0) {\n\t\tPMD_INIT_LOG(ERR, \" Error on enabling FD.\");\n\t\treturn err;\n\t}\n\treturn 0;\n}\n\n/*\n * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used\n * by the IXGBE driver code.\n */\nstatic int\nixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,\n\t\tunion ixgbe_atr_input *input)\n{\n\tinput->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;\n\tinput->formatted.flex_bytes = (uint16_t)(\n\t\t(fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |\n\t\t(fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));\n\n\tswitch (fdir_filter->input.flow_type) {\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_UDP:\n\t\tinput->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;\n\t\tbreak;\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_TCP:\n\t\tinput->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;\n\t\tbreak;\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:\n\t\tinput->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;\n\t\tbreak;\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:\n\t\tinput->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;\n\t\tbreak;\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_UDP:\n\t\tinput->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;\n\t\tbreak;\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_TCP:\n\t\tinput->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;\n\t\tbreak;\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:\n\t\tinput->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;\n\t\tbreak;\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:\n\t\tinput->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \" Error on flow_type input\");\n\t\treturn -EINVAL;\n\t}\n\n\tswitch (fdir_filter->input.flow_type) {\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_UDP:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_TCP:\n\t\tinput->formatted.src_port =\n\t\t\tfdir_filter->input.flow.udp4_flow.src_port;\n\t\tinput->formatted.dst_port =\n\t\t\tfdir_filter->input.flow.udp4_flow.dst_port;\n\t/*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:\n\t\tinput->formatted.src_ip[0] =\n\t\t\tfdir_filter->input.flow.ip4_flow.src_ip;\n\t\tinput->formatted.dst_ip[0] =\n\t\t\tfdir_filter->input.flow.ip4_flow.dst_ip;\n\t\tbreak;\n\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_UDP:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_TCP:\n\t\tinput->formatted.src_port =\n\t\t\tfdir_filter->input.flow.udp6_flow.src_port;\n\t\tinput->formatted.dst_port =\n\t\t\tfdir_filter->input.flow.udp6_flow.dst_port;\n\t/*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:\n\tcase RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:\n\t\trte_memcpy(input->formatted.src_ip,\n\t\t\t fdir_filter->input.flow.ipv6_flow.src_ip,\n\t\t\t sizeof(input->formatted.src_ip));\n\t\trte_memcpy(input->formatted.dst_ip,\n\t\t\t fdir_filter->input.flow.ipv6_flow.dst_ip,\n\t\t\t sizeof(input->formatted.dst_ip));\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \" Error on flow_type input\");\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\n/*\n * The below function is taken from the FreeBSD IXGBE drivers release\n * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK\n * before returning, as the signature hash can use 16bits.\n *\n * The newer driver has optimised functions for calculating bucket and\n * signature hashes. However they don't support IPv6 type packets for signature\n * filters so are not used here.\n *\n * Note that the bkt_hash field in the ixgbe_atr_input structure is also never\n * set.\n *\n * Compute the hashes for SW ATR\n * @stream: input bitstream to compute the hash on\n * @key: 32-bit hash key\n **/\nstatic uint32_t\nixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,\n\t\t\t\t uint32_t key)\n{\n\t/*\n\t * The algorithm is as follows:\n\t * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350\n\t * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]\n\t * and A[n] x B[n] is bitwise AND between same length strings\n\t *\n\t * K[n] is 16 bits, defined as:\n\t * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]\n\t * for n modulo 32 < 15, K[n] =\n\t * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]\n\t *\n\t * S[n] is 16 bits, defined as:\n\t * for n >= 15, S[n] = S[n:n - 15]\n\t * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]\n\t *\n\t * To simplify for programming, the algorithm is implemented\n\t * in software this way:\n\t *\n\t * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]\n\t *\n\t * for (i = 0; i < 352; i+=32)\n\t * hi_hash_dword[31:0] ^= Stream[(i+31):i];\n\t *\n\t * lo_hash_dword[15:0] ^= Stream[15:0];\n\t * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];\n\t * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];\n\t *\n\t * hi_hash_dword[31:0] ^= Stream[351:320];\n\t *\n\t * if(key[0])\n\t * hash[15:0] ^= Stream[15:0];\n\t *\n\t * for (i = 0; i < 16; i++) {\n\t * if (key[i])\n\t * hash[15:0] ^= lo_hash_dword[(i+15):i];\n\t * if (key[i + 16])\n\t * hash[15:0] ^= hi_hash_dword[(i+15):i];\n\t * }\n\t *\n\t */\n\t__be32 common_hash_dword = 0;\n\tu32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;\n\tu32 hash_result = 0;\n\tu8 i;\n\n\t/* record the flow_vm_vlan bits as they are a key part to the hash */\n\tflow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);\n\n\t/* generate common hash dword */\n\tfor (i = 1; i <= 13; i++)\n\t\tcommon_hash_dword ^= atr_input->dword_stream[i];\n\n\thi_hash_dword = IXGBE_NTOHL(common_hash_dword);\n\n\t/* low dword is word swapped version of common */\n\tlo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);\n\n\t/* apply flow ID/VM pool/VLAN ID bits to hash words */\n\thi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);\n\n\t/* Process bits 0 and 16 */\n\tif (key & 0x0001) hash_result ^= lo_hash_dword;\n\tif (key & 0x00010000) hash_result ^= hi_hash_dword;\n\n\t/*\n\t * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to\n\t * delay this because bit 0 of the stream should not be processed\n\t * so we do not add the vlan until after bit 0 was processed\n\t */\n\tlo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);\n\n\n\t/* process the remaining 30 bits in the key 2 bits at a time */\n\tfor (i = 15; i; i-- ) {\n\t\tif (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;\n\t\tif (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;\n\t}\n\n\treturn hash_result;\n}\n\nstatic uint32_t\natr_compute_perfect_hash_82599(union ixgbe_atr_input *input,\n\t\tenum rte_fdir_pballoc_type pballoc)\n{\n\tif (pballoc == RTE_FDIR_PBALLOC_256K)\n\t\treturn ixgbe_atr_compute_hash_82599(input,\n\t\t\t\tIXGBE_ATR_BUCKET_HASH_KEY) &\n\t\t\t\tPERFECT_BUCKET_256KB_HASH_MASK;\n\telse if (pballoc == RTE_FDIR_PBALLOC_128K)\n\t\treturn ixgbe_atr_compute_hash_82599(input,\n\t\t\t\tIXGBE_ATR_BUCKET_HASH_KEY) &\n\t\t\t\tPERFECT_BUCKET_128KB_HASH_MASK;\n\telse\n\t\treturn ixgbe_atr_compute_hash_82599(input,\n\t\t\t\tIXGBE_ATR_BUCKET_HASH_KEY) &\n\t\t\t\tPERFECT_BUCKET_64KB_HASH_MASK;\n}\n\n/**\n * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete\n * @hw: pointer to hardware structure\n */\nstatic inline int\nixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)\n{\n\tint i;\n\n\tfor (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {\n\t\t*fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);\n\t\tif (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))\n\t\t\treturn 0;\n\t\trte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);\n\t}\n\n\treturn -ETIMEDOUT;\n}\n\n/*\n * Calculate the hash value needed for signature-match filters. In the FreeBSD\n * driver, this is done by the optimised function\n * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it\n * doesn't support calculating a hash for an IPv6 filter.\n */\nstatic uint32_t\natr_compute_sig_hash_82599(union ixgbe_atr_input *input,\n\t\tenum rte_fdir_pballoc_type pballoc)\n{\n\tuint32_t bucket_hash, sig_hash;\n\n\tif (pballoc == RTE_FDIR_PBALLOC_256K)\n\t\tbucket_hash = ixgbe_atr_compute_hash_82599(input,\n\t\t\t\tIXGBE_ATR_BUCKET_HASH_KEY) &\n\t\t\t\tSIG_BUCKET_256KB_HASH_MASK;\n\telse if (pballoc == RTE_FDIR_PBALLOC_128K)\n\t\tbucket_hash = ixgbe_atr_compute_hash_82599(input,\n\t\t\t\tIXGBE_ATR_BUCKET_HASH_KEY) &\n\t\t\t\tSIG_BUCKET_128KB_HASH_MASK;\n\telse\n\t\tbucket_hash = ixgbe_atr_compute_hash_82599(input,\n\t\t\t\tIXGBE_ATR_BUCKET_HASH_KEY) &\n\t\t\t\tSIG_BUCKET_64KB_HASH_MASK;\n\n\tsig_hash = ixgbe_atr_compute_hash_82599(input,\n\t\t\tIXGBE_ATR_SIGNATURE_HASH_KEY);\n\n\treturn (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;\n}\n\n/*\n * This is based on ixgbe_fdir_write_perfect_filter_82599() in\n * base/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register\n * added, and IPv6 support also added. The hash value is also pre-calculated\n * as the pballoc value is needed to do it.\n */\nstatic int\nfdir_write_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\tunion ixgbe_atr_input *input, uint8_t queue,\n\t\t\tuint32_t fdircmd, uint32_t fdirhash)\n{\n\tuint32_t fdirport, fdirvlan;\n\tint err = 0;\n\n\t/* record the IPv4 address (big-endian) */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);\n\n\t/* record source and destination port (little-endian)*/\n\tfdirport = IXGBE_NTOHS(input->formatted.dst_port);\n\tfdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;\n\tfdirport |= IXGBE_NTOHS(input->formatted.src_port);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);\n\n\t/* record vlan (little-endian) and flex_bytes(big-endian) */\n\tfdirvlan = input->formatted.flex_bytes;\n\tfdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;\n\tfdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);\n\n\t/* configure FDIRHASH register */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);\n\n\t/*\n\t * flush all previous writes to make certain registers are\n\t * programmed prior to issuing the command\n\t */\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* configure FDIRCMD register */\n\tfdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |\n\t\t IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;\n\tfdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;\n\tfdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;\n\tfdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);\n\n\tPMD_DRV_LOG(DEBUG, \"Rx Queue=%x hash=%x\", queue, fdirhash);\n\n\terr = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);\n\tif (err < 0)\n\t\tPMD_DRV_LOG(ERR, \"Timeout writing flow director filter.\");\n\n\treturn err;\n}\n\n/**\n * This function is based on ixgbe_atr_add_signature_filter_82599() in\n * base/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports\n * setting extra fields in the FDIRCMD register, and removes the code that was\n * verifying the flow_type field. According to the documentation, a flow type of\n * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to\n * work ok...\n *\n * Adds a signature hash filter\n * @hw: pointer to hardware structure\n * @input: unique input dword\n * @queue: queue index to direct traffic to\n * @fdircmd: any extra flags to set in fdircmd register\n * @fdirhash: pre-calculated hash value for the filter\n **/\nstatic int\nfdir_add_signature_filter_82599(struct ixgbe_hw *hw,\n\t\tunion ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,\n\t\tuint32_t fdirhash)\n{\n\tint err = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* configure FDIRCMD register */\n\tfdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |\n\t IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;\n\tfdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;\n\tfdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);\n\n\tPMD_DRV_LOG(DEBUG, \"Rx Queue=%x hash=%x\", queue, fdirhash);\n\n\terr = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);\n\tif (err < 0)\n\t\tPMD_DRV_LOG(ERR, \"Timeout writing flow director filter.\");\n\n\treturn err;\n}\n\n/*\n * This is based on ixgbe_fdir_erase_perfect_filter_82599() in\n * base/ixgbe_82599.c. It is modified to take in the hash as a parameter so\n * that it can be used for removing signature and perfect filters.\n */\nstatic int\nfdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)\n{\n\tuint32_t fdircmd = 0;\n\tint err = 0;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);\n\n\t/* flush hash to HW */\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Query if filter is present */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);\n\n\terr = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);\n\tif (err < 0) {\n\t\tPMD_INIT_LOG(ERR, \"Timeout querying for flow director filter.\");\n\t\treturn err;\n\t}\n\n\t/* if filter exists in hardware then remove it */\n\tif (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,\n\t\t\t\tIXGBE_FDIRCMD_CMD_REMOVE_FLOW);\n\t}\n\terr = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);\n\tif (err < 0)\n\t\tPMD_INIT_LOG(ERR, \"Timeout erasing flow director filter.\");\n\treturn err;\n\n}\n\n/*\n * ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.\n * @dev: pointer to the structure rte_eth_dev\n * @fdir_filter: fdir filter entry\n * @del: 1 - delete, 0 - add\n * @update: 1 - update\n */\nstatic int\nixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,\n\t\t\t const struct rte_eth_fdir_filter *fdir_filter,\n\t\t\t bool del,\n\t\t\t bool update)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t fdircmd_flags;\n\tuint32_t fdirhash;\n\tunion ixgbe_atr_input input;\n\tuint8_t queue;\n\tbool is_perfect = FALSE;\n\tint err;\n\tstruct ixgbe_hw_fdir_info *info =\n\t\t\tIXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);\n\n\tif (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_NONE)\n\t\treturn -ENOTSUP;\n\n\t/*\n\t * Sanity check for x550.\n\t * When adding a new filter with flow type set to IPv4-other,\n\t * the flow director mask should be configed before,\n\t * and the L4 protocol and ports are masked.\n\t */\n\tif ((!del) &&\n\t (hw->mac.type == ixgbe_mac_X550 ||\n\t hw->mac.type == ixgbe_mac_X550EM_x) &&\n\t (fdir_filter->input.flow_type ==\n\t RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) &&\n\t (info->mask.src_port_mask != 0 ||\n\t info->mask.dst_port_mask != 0)) {\n\t\tPMD_DRV_LOG(ERR, \"By this device,\"\n\t\t \" IPv4-other is not supported without\"\n\t\t \" L4 protocol and ports masked!\");\n\t\treturn -ENOTSUP;\n\t}\n\n\tif (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)\n\t\tis_perfect = TRUE;\n\n\tmemset(&input, 0, sizeof(input));\n\n\terr = ixgbe_fdir_filter_to_atr_input(fdir_filter, &input);\n\tif (err)\n\t\treturn err;\n\n\tif (is_perfect) {\n\t\tif (input.formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) {\n\t\t\tPMD_DRV_LOG(ERR, \"IPv6 is not supported in\"\n\t\t\t\t\t \" perfect mode!\");\n\t\t\treturn -ENOTSUP;\n\t\t}\n\t\tfdirhash = atr_compute_perfect_hash_82599(&input,\n\t\t\t\tdev->data->dev_conf.fdir_conf.pballoc);\n\t\tfdirhash |= fdir_filter->soft_id <<\n\t\t\t\tIXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;\n\t} else\n\t\tfdirhash = atr_compute_sig_hash_82599(&input,\n\t\t\t\tdev->data->dev_conf.fdir_conf.pballoc);\n\n\tif (del) {\n\t\terr = fdir_erase_filter_82599(hw, fdirhash);\n\t\tif (err < 0)\n\t\t\tPMD_DRV_LOG(ERR, \"Fail to delete FDIR filter!\");\n\t\telse\n\t\t\tPMD_DRV_LOG(DEBUG, \"Success to delete FDIR filter!\");\n\t\treturn err;\n\t}\n\t/* add or update an fdir filter*/\n\tfdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;\n\tif (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT) {\n\t\tif (is_perfect) {\n\t\t\tqueue = dev->data->dev_conf.fdir_conf.drop_queue;\n\t\t\tfdircmd_flags |= IXGBE_FDIRCMD_DROP;\n\t\t} else {\n\t\t\tPMD_DRV_LOG(ERR, \"Drop option is not supported in\"\n\t\t\t\t\" signature mode.\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t} else if (fdir_filter->action.rx_queue < IXGBE_MAX_RX_QUEUE_NUM)\n\t\tqueue = (uint8_t)fdir_filter->action.rx_queue;\n\telse\n\t\treturn -EINVAL;\n\n\tif (is_perfect) {\n\t\terr = fdir_write_perfect_filter_82599(hw, &input, queue,\n\t\t\t\tfdircmd_flags, fdirhash);\n\t} else {\n\t\terr = fdir_add_signature_filter_82599(hw, &input, queue,\n\t\t\t\tfdircmd_flags, fdirhash);\n\t}\n\tif (err < 0)\n\t\tPMD_DRV_LOG(ERR, \"Fail to add FDIR filter!\");\n\telse\n\t\tPMD_DRV_LOG(DEBUG, \"Success to add FDIR filter\");\n\n\treturn err;\n}\n\nstatic int\nixgbe_fdir_flush(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_hw_fdir_info *info =\n\t\t\tIXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);\n\tint ret;\n\n\tret = ixgbe_reinit_fdir_tables_82599(hw);\n\tif (ret < 0) {\n\t\tPMD_INIT_LOG(ERR, \"Failed to re-initialize FD table.\");\n\t\treturn ret;\n\t}\n\n\tinfo->f_add = 0;\n\tinfo->f_remove = 0;\n\tinfo->add = 0;\n\tinfo->remove = 0;\n\n\treturn ret;\n}\n\n#define FDIRENTRIES_NUM_SHIFT 10\nstatic void\nixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_hw_fdir_info *info =\n\t\t\tIXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);\n\tuint32_t fdirctrl, max_num;\n\tuint8_t offset;\n\n\tfdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);\n\toffset = ((fdirctrl & IXGBE_FDIRCTRL_FLEX_MASK) >>\n\t\t\tIXGBE_FDIRCTRL_FLEX_SHIFT) * sizeof(uint16_t);\n\n\tfdir_info->mode = dev->data->dev_conf.fdir_conf.mode;\n\tmax_num = (1 << (FDIRENTRIES_NUM_SHIFT +\n\t\t\t(fdirctrl & FDIRCTRL_PBALLOC_MASK)));\n\tif (fdir_info->mode == RTE_FDIR_MODE_PERFECT)\n\t\tfdir_info->guarant_spc = max_num;\n\telse if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE)\n\t\tfdir_info->guarant_spc = max_num * 4;\n\n\tfdir_info->mask.vlan_tci_mask = info->mask.vlan_tci_mask;\n\tfdir_info->mask.ipv4_mask.src_ip = info->mask.src_ipv4_mask;\n\tfdir_info->mask.ipv4_mask.dst_ip = info->mask.dst_ipv4_mask;\n\tIPV6_MASK_TO_ADDR(info->mask.src_ipv6_mask,\n\t\t\tfdir_info->mask.ipv6_mask.src_ip);\n\tIPV6_MASK_TO_ADDR(info->mask.dst_ipv6_mask,\n\t\t\tfdir_info->mask.ipv6_mask.dst_ip);\n\tfdir_info->mask.src_port_mask = info->mask.src_port_mask;\n\tfdir_info->mask.dst_port_mask = info->mask.dst_port_mask;\n\tfdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN;\n\tfdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;\n\tfdir_info->flex_payload_unit = sizeof(uint16_t);\n\tfdir_info->max_flex_payload_segment_num = 1;\n\tfdir_info->flex_payload_limit = 62;\n\tfdir_info->flex_conf.nb_payloads = 1;\n\tfdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD;\n\tfdir_info->flex_conf.flex_set[0].src_offset[0] = offset;\n\tfdir_info->flex_conf.flex_set[0].src_offset[1] = offset + 1;\n\tfdir_info->flex_conf.nb_flexmasks = 1;\n\tfdir_info->flex_conf.flex_mask[0].flow_type = RTE_ETH_FLOW_UNKNOWN;\n\tfdir_info->flex_conf.flex_mask[0].mask[0] =\n\t\t\t(uint8_t)(info->mask.flex_bytes_mask & 0x00FF);\n\tfdir_info->flex_conf.flex_mask[0].mask[1] =\n\t\t\t(uint8_t)((info->mask.flex_bytes_mask & 0xFF00) >> 8);\n}\n\nstatic void\nixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_stats)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_hw_fdir_info *info =\n\t\t\tIXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);\n\tuint32_t reg, max_num;\n\n\t/* Get the information from registers */\n\treg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);\n\tinfo->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>\n\t\t\t\t\tIXGBE_FDIRFREE_COLL_SHIFT);\n\tinfo->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>\n\t\t\t\t IXGBE_FDIRFREE_FREE_SHIFT);\n\n\treg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);\n\tinfo->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>\n\t\t\t\t IXGBE_FDIRLEN_MAXHASH_SHIFT);\n\tinfo->maxlen = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>\n\t\t\t\t IXGBE_FDIRLEN_MAXLEN_SHIFT);\n\n\treg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);\n\tinfo->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>\n\t\tIXGBE_FDIRUSTAT_REMOVE_SHIFT;\n\tinfo->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>\n\t\tIXGBE_FDIRUSTAT_ADD_SHIFT;\n\n\treg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;\n\tinfo->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>\n\t\tIXGBE_FDIRFSTAT_FREMOVE_SHIFT;\n\tinfo->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>\n\t\tIXGBE_FDIRFSTAT_FADD_SHIFT;\n\n\t/* Copy the new information in the fdir parameter */\n\tfdir_stats->collision = info->collision;\n\tfdir_stats->free = info->free;\n\tfdir_stats->maxhash = info->maxhash;\n\tfdir_stats->maxlen = info->maxlen;\n\tfdir_stats->remove = info->remove;\n\tfdir_stats->add = info->add;\n\tfdir_stats->f_remove = info->f_remove;\n\tfdir_stats->f_add = info->f_add;\n\n\treg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);\n\tmax_num = (1 << (FDIRENTRIES_NUM_SHIFT +\n\t\t\t(reg & FDIRCTRL_PBALLOC_MASK)));\n\tif (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)\n\t\t\tfdir_stats->guarant_cnt = max_num - fdir_stats->free;\n\telse if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE)\n\t\tfdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free;\n\n}\n\n/*\n * ixgbe_fdir_ctrl_func - deal with all operations on flow director.\n * @dev: pointer to the structure rte_eth_dev\n * @filter_op:operation will be taken\n * @arg: a pointer to specific structure corresponding to the filter_op\n */\nint\nixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,\n\t\t\tenum rte_filter_op filter_op, void *arg)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tint ret = 0;\n\n\tif (hw->mac.type != ixgbe_mac_82599EB &&\n\t\thw->mac.type != ixgbe_mac_X540 &&\n\t\thw->mac.type != ixgbe_mac_X550 &&\n\t\thw->mac.type != ixgbe_mac_X550EM_x)\n\t\treturn -ENOTSUP;\n\n\tif (filter_op == RTE_ETH_FILTER_NOP)\n\t\treturn 0;\n\n\tif (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)\n\t\treturn -EINVAL;\n\n\tswitch (filter_op) {\n\tcase RTE_ETH_FILTER_ADD:\n\t\tret = ixgbe_add_del_fdir_filter(dev,\n\t\t\t(struct rte_eth_fdir_filter *)arg, FALSE, FALSE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_UPDATE:\n\t\tret = ixgbe_add_del_fdir_filter(dev,\n\t\t\t(struct rte_eth_fdir_filter *)arg, FALSE, TRUE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_DELETE:\n\t\tret = ixgbe_add_del_fdir_filter(dev,\n\t\t\t(struct rte_eth_fdir_filter *)arg, TRUE, FALSE);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_FLUSH:\n\t\tret = ixgbe_fdir_flush(dev);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_INFO:\n\t\tixgbe_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);\n\t\tbreak;\n\tcase RTE_ETH_FILTER_STATS:\n\t\tixgbe_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(ERR, \"unknown operation %u\", filter_op);\n\t\tret = -EINVAL;\n\t\tbreak;\n\t}\n\treturn ret;\n}\n" }, { "path": "drivers/net/ixgbe/ixgbe_logs.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _IXGBE_LOGS_H_\n#define _IXGBE_LOGS_H_\n\n#define PMD_INIT_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ##args)\n\n#ifdef RTE_LIBRTE_IXGBE_DEBUG_INIT\n#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, \" >>\")\n#else\n#define PMD_INIT_FUNC_TRACE() do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_IXGBE_DEBUG_RX\n#define PMD_RX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_RX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_IXGBE_DEBUG_TX\n#define PMD_TX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_TX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE\n#define PMD_TX_FREE_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_TX_FREE_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_IXGBE_DEBUG_DRIVER\n#define PMD_DRV_LOG_RAW(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt, __func__, ## args)\n#else\n#define PMD_DRV_LOG_RAW(level, fmt, args...) do { } while (0)\n#endif\n\n#define PMD_DRV_LOG(level, fmt, args...) \\\n\tPMD_DRV_LOG_RAW(level, fmt \"\\n\", ## args)\n\n#endif /* _IXGBE_LOGS_H_ */\n" }, { "path": "drivers/net/ixgbe/ixgbe_pf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"base/ixgbe_common.h\"\n#include \"ixgbe_ethdev.h\"\n\n#define IXGBE_MAX_VFTA (128)\n#define IXGBE_VF_MSG_SIZE_DEFAULT 1\n#define IXGBE_VF_GET_QUEUE_MSG_SIZE 5\n\nstatic inline uint16_t\ndev_num_vf(struct rte_eth_dev *eth_dev)\n{\n\treturn eth_dev->pci_dev->max_vfs;\n}\n\nstatic inline\nint ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)\n{\n\tunsigned char vf_mac_addr[ETHER_ADDR_LEN];\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);\n\tuint16_t vfn;\n\n\tfor (vfn = 0; vfn < vf_num; vfn++) {\n\t\teth_random_addr(vf_mac_addr);\n\t\t/* keep the random address as default */\n\t\tmemcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,\n\t\t\t ETHER_ADDR_LEN);\n\t}\n\n\treturn 0;\n}\n\nstatic inline int\nixgbe_mb_intr_setup(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_interrupt *intr =\n\t\tIXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);\n\n\tintr->mask |= IXGBE_EICR_MAILBOX;\n\n\treturn 0;\n}\n\nvoid ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)\n{\n\tstruct ixgbe_vf_info **vfinfo =\n\t\tIXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);\n\tstruct ixgbe_mirror_info *mirror_info =\n IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);\n\tstruct ixgbe_uta_info *uta_info =\n IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\tuint16_t vf_num;\n\tuint8_t nb_queue;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tRTE_ETH_DEV_SRIOV(eth_dev).active = 0;\n\tif (0 == (vf_num = dev_num_vf(eth_dev)))\n\t\treturn;\n\n\t*vfinfo = rte_zmalloc(\"vf_info\", sizeof(struct ixgbe_vf_info) * vf_num, 0);\n\tif (*vfinfo == NULL)\n\t\trte_panic(\"Cannot allocate memory for private VF data\\n\");\n\n\tmemset(mirror_info,0,sizeof(struct ixgbe_mirror_info));\n\tmemset(uta_info,0,sizeof(struct ixgbe_uta_info));\n\thw->mac.mc_filter_type = 0;\n\n\tif (vf_num >= ETH_32_POOLS) {\n\t\tnb_queue = 2;\n\t\tRTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;\n\t} else if (vf_num >= ETH_16_POOLS) {\n\t\tnb_queue = 4;\n\t\tRTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;\n\t} else {\n\t\tnb_queue = 8;\n\t\tRTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;\n\t}\n\n\tRTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;\n\tRTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;\n\tRTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);\n\n\tixgbe_vf_perm_addr_gen(eth_dev, vf_num);\n\n\t/* init_mailbox_params */\n\thw->mbx.ops.init_params(hw);\n\n\t/* set mb interrupt mask */\n\tixgbe_mb_intr_setup(eth_dev);\n\n\treturn;\n}\n\nvoid ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)\n{\n\tstruct ixgbe_vf_info **vfinfo;\n\tuint16_t vf_num;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tvfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);\n\n\tRTE_ETH_DEV_SRIOV(eth_dev).active = 0;\n\tRTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0;\n\tRTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0;\n\tRTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0;\n\n\tvf_num = dev_num_vf(eth_dev);\n\tif (vf_num == 0)\n\t\treturn;\n\n\trte_free(*vfinfo);\n\t*vfinfo = NULL;\n}\n\nint ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)\n{\n\tuint32_t vtctl, fcrth;\n\tuint32_t vfre_slot, vfre_offset;\n\tuint16_t vf_num;\n\tconst uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */\n\tconst uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\tuint32_t gpie, gcr_ext;\n\tuint32_t vlanctrl;\n\tint i;\n\n\tif (0 == (vf_num = dev_num_vf(eth_dev)))\n\t\treturn -1;\n\n\t/* enable VMDq and set the default pool for PF */\n\tvtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);\n\tvtctl |= IXGBE_VMD_CTL_VMDQ_EN;\n\tvtctl &= ~IXGBE_VT_CTL_POOL_MASK;\n\tvtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx\n\t\t<< IXGBE_VT_CTL_POOL_SHIFT;\n\tvtctl |= IXGBE_VT_CTL_REPLEN;\n\tIXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);\n\n\tvfre_offset = vf_num & VFRE_MASK;\n\tvfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;\n\n\t/* Enable pools reserved to PF only */\n\tIXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0) << vfre_offset);\n\tIXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);\n\tIXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0) << vfre_offset);\n\tIXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);\n\n\t/* PFDMA Tx General Switch Control Enables VMDQ loopback */\n\tIXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);\n\n\t/* clear VMDq map to perment rar 0 */\n\thw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);\n\n\t/* clear VMDq map to scan rar 127 */\n\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);\n\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);\n\n\t/* set VMDq map to default PF pool */\n\thw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);\n\n\t/*\n\t * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode\n\t */\n\tgcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);\n\tgcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;\n\n\tgpie = IXGBE_READ_REG(hw, IXGBE_GPIE);\n\tgpie &= ~IXGBE_GPIE_VTMODE_MASK;\n\tgpie |= IXGBE_GPIE_MSIX_MODE;\n\n\tswitch (RTE_ETH_DEV_SRIOV(eth_dev).active) {\n\tcase ETH_64_POOLS:\n\t\tgcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;\n\t\tgpie |= IXGBE_GPIE_VTMODE_64;\n\t\tbreak;\n\tcase ETH_32_POOLS:\n\t\tgcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;\n\t\tgpie |= IXGBE_GPIE_VTMODE_32;\n\t\tbreak;\n\tcase ETH_16_POOLS:\n\t\tgcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;\n\t\tgpie |= IXGBE_GPIE_VTMODE_16;\n\t\tbreak;\n\t}\n\n\tIXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);\n IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);\n\n /*\n\t * enable vlan filtering and allow all vlan tags through\n\t */\n vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */\n IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);\n\n /* VFTA - enable all vlan filters */\n for (i = 0; i < IXGBE_MAX_VFTA; i++) {\n IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);\n }\n\n\t/* Enable MAC Anti-Spoofing */\n\thw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);\n\n\t/* set flow control threshold to max to avoid tx switch hang */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);\n\t\tfcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);\n\t}\n\n\treturn 0;\n}\n\nstatic void\nset_rx_mode(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_dev_data *dev_data =\n\t\t(struct rte_eth_dev_data*)dev->data->dev_private;\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tu32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;\n\tuint16_t vfn = dev_num_vf(dev);\n\n\t/* Check for Promiscuous and All Multicast modes */\n\tfctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\n\t/* set all bits that we expect to always be set */\n\tfctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */\n\tfctrl |= IXGBE_FCTRL_BAM;\n\n\t/* clear the bits we are changing the status of */\n\tfctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);\n\n\tif (dev_data->promiscuous) {\n\t\tfctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);\n\t\tvmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);\n\t} else {\n\t\tif (dev_data->all_multicast) {\n\t\t\tfctrl |= IXGBE_FCTRL_MPE;\n\t\t\tvmolr |= IXGBE_VMOLR_MPE;\n\t\t} else {\n\t\t\tvmolr |= IXGBE_VMOLR_ROMPE;\n\t\t}\n\t}\n\n\tif (hw->mac.type != ixgbe_mac_82598EB) {\n\t\tvmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &\n\t\t\t ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |\n\t\t\t IXGBE_VMOLR_ROPE);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);\n\t}\n\n\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);\n\n\tif (dev->data->dev_conf.rxmode.hw_vlan_strip)\n\t\tixgbe_vlan_hw_strip_enable_all(dev);\n\telse\n\t\tixgbe_vlan_hw_strip_disable_all(dev);\n}\n\nstatic inline void\nixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));\n\tint rar_entry = hw->mac.num_rar_entries - (vf + 1);\n\tuint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));\n\n\tvmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |\n\t\t\tIXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);\n\tIXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);\n\n\t/* reset multicast table array for vf */\n\tvfinfo[vf].num_vf_mc_hashes = 0;\n\n\t/* reset rx mode */\n\tset_rx_mode(dev);\n\n\thw->mac.ops.clear_rar(hw, rar_entry);\n}\n\nstatic inline void\nixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t reg;\n\tuint32_t reg_offset, vf_shift;\n\tconst uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */\n\tconst uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);\n\n\tvf_shift = vf & VFRE_MASK;\n\treg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;\n\n\t/* enable transmit and receive for vf */\n\treg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));\n\treg |= (reg | (1 << vf_shift));\n\tIXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);\n\n\treg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));\n\treg |= (reg | (1 << vf_shift));\n\tIXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);\n\n\t/* Enable counting of spoofed packets in the SSVPC register */\n\treg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));\n\treg |= (1 << vf_shift);\n\tIXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);\n\n\tixgbe_vf_reset_event(dev, vf);\n}\n\nstatic int\nixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));\n\tunsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;\n\tint rar_entry = hw->mac.num_rar_entries - (vf + 1);\n\tuint8_t *new_mac = (uint8_t *)(&msgbuf[1]);\n\n\tixgbe_vf_reset_msg(dev, vf);\n\n\thw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);\n\n\t/* reply to reset with ack and vf mac address */\n\tmsgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;\n\trte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);\n\t/*\n\t * Piggyback the multicast filter type so VF can compute the\n\t * correct vectors\n\t */\n\tmsgbuf[3] = hw->mac.mc_filter_type;\n\tixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);\n\n\treturn 0;\n}\n\nstatic int\nixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));\n\tint rar_entry = hw->mac.num_rar_entries - (vf + 1);\n\tuint8_t *new_mac = (uint8_t *)(&msgbuf[1]);\n\n\tif (is_valid_assigned_ether_addr((struct ether_addr*)new_mac)) {\n\t\trte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);\n\t\treturn hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);\n\t}\n\treturn -1;\n}\n\nstatic int\nixgbe_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));\n\tint nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>\n\t\tIXGBE_VT_MSGINFO_SHIFT;\n\tuint16_t *hash_list = (uint16_t *)&msgbuf[1];\n\tuint32_t mta_idx;\n\tuint32_t mta_shift;\n\tconst uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;\n\tconst uint32_t IXGBE_MTA_BIT_SHIFT = 5;\n\tconst uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;\n\tuint32_t reg_val;\n\tint i;\n\n\t/* only so many hash values supported */\n\tnb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);\n\n\t/* store the mc entries */\n\tvfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;\n\tfor (i = 0; i < nb_entries; i++) {\n\t\tvfinfo->vf_mc_hashes[i] = hash_list[i];\n\t}\n\n\tfor (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {\n\t\tmta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)\n\t\t\t\t& IXGBE_MTA_INDEX_MASK;\n\t\tmta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;\n\t\treg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));\n\t\treg_val |= (1 << mta_shift);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)\n{\n\tint add, vid;\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));\n\n\tadd = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)\n\t\t>> IXGBE_VT_MSGINFO_SHIFT;\n\tvid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);\n\n\tif (add)\n\t\tvfinfo[vf].vlan_count++;\n\telse if (vfinfo[vf].vlan_count)\n\t\tvfinfo[vf].vlan_count--;\n\treturn hw->mac.ops.set_vfta(hw, vid, vf, (bool)add);\n}\n\nstatic int\nixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t new_mtu = msgbuf[1];\n\tuint32_t max_frs;\n\tint max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;\n\n\t/* X540 and X550 support jumbo frames in IOV mode */\n\tif (hw->mac.type != ixgbe_mac_X540 &&\n\t\thw->mac.type != ixgbe_mac_X550 &&\n\t\thw->mac.type != ixgbe_mac_X550EM_x)\n\t\treturn -1;\n\n\tif ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))\n\t\treturn -1;\n\n\tmax_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &\n\t\t IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;\n\tif (max_frs < new_mtu) {\n\t\tmax_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)\n{\n\tuint32_t api_version = msgbuf[1];\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);\n\n\tswitch (api_version) {\n\tcase ixgbe_mbox_api_10:\n\tcase ixgbe_mbox_api_11:\n\t\tvfinfo[vf].api_version = (uint8_t)api_version;\n\t\treturn 0;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tRTE_LOG(ERR, PMD, \"Negotiate invalid api version %u from VF %d\\n\",\n\t\tapi_version, vf);\n\n\treturn -1;\n}\n\nstatic int\nixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)\n{\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);\n\tuint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;\n\n\t/* Verify if the PF supports the mbox APIs version or not */\n\tswitch (vfinfo[vf].api_version) {\n\tcase ixgbe_mbox_api_20:\n\tcase ixgbe_mbox_api_11:\n\t\tbreak;\n\tdefault:\n\t\treturn -1;\n\t}\n\n\t/* Notify VF of Rx and Tx queue number */\n\tmsgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;\n\tmsgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;\n\n\t/* Notify VF of default queue */\n\tmsgbuf[IXGBE_VF_DEF_QUEUE] = default_q;\n\n\t/*\n\t * FIX ME if it needs fill msgbuf[IXGBE_VF_TRANS_VLAN]\n\t * for VLAN strip or VMDQ_DCB or VMDQ_DCB_RSS\n\t */\n\n\treturn 0;\n}\n\nstatic int\nixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)\n{\n\tuint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;\n\tuint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;\n\tuint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];\n\tint32_t retval;\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);\n\n\tretval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);\n\tif (retval) {\n\t\tPMD_DRV_LOG(ERR, \"Error mbx recv msg from VF %d\", vf);\n\t\treturn retval;\n\t}\n\n\t/* do nothing with the message already been processed */\n\tif (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))\n\t\treturn retval;\n\n\t/* flush the ack before we write any messages back */\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* perform VF reset */\n\tif (msgbuf[0] == IXGBE_VF_RESET) {\n\t\tint ret = ixgbe_vf_reset(dev, vf, msgbuf);\n\t\tvfinfo[vf].clear_to_send = true;\n\t\treturn ret;\n\t}\n\n\t/* check & process VF to PF mailbox message */\n\tswitch ((msgbuf[0] & 0xFFFF)) {\n\tcase IXGBE_VF_SET_MAC_ADDR:\n\t\tretval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);\n\t\tbreak;\n\tcase IXGBE_VF_SET_MULTICAST:\n\t\tretval = ixgbe_vf_set_multicast(dev, vf, msgbuf);\n\t\tbreak;\n\tcase IXGBE_VF_SET_LPE:\n\t\tretval = ixgbe_set_vf_lpe(dev, vf, msgbuf);\n\t\tbreak;\n\tcase IXGBE_VF_SET_VLAN:\n\t\tretval = ixgbe_vf_set_vlan(dev, vf, msgbuf);\n\t\tbreak;\n\tcase IXGBE_VF_API_NEGOTIATE:\n\t\tretval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);\n\t\tbreak;\n\tcase IXGBE_VF_GET_QUEUES:\n\t\tretval = ixgbe_get_vf_queues(dev, vf, msgbuf);\n\t\tmsg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;\n\t\tbreak;\n\tdefault:\n\t\tPMD_DRV_LOG(DEBUG, \"Unhandled Msg %8.8x\", (unsigned)msgbuf[0]);\n\t\tretval = IXGBE_ERR_MBX;\n\t\tbreak;\n\t}\n\n\t/* response the VF according to the message process result */\n\tif (retval)\n\t\tmsgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;\n\telse\n\t\tmsgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;\n\n\tmsgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;\n\n\tixgbe_write_mbx(hw, msgbuf, msg_size, vf);\n\n\treturn retval;\n}\n\nstatic inline void\nixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)\n{\n\tuint32_t msg = IXGBE_VT_MSGTYPE_NACK;\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct ixgbe_vf_info *vfinfo =\n\t\t*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);\n\n\tif (!vfinfo[vf].clear_to_send)\n\t\tixgbe_write_mbx(hw, &msg, 1, vf);\n}\n\nvoid ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)\n{\n\tuint16_t vf;\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n\n\tfor (vf = 0; vf < dev_num_vf(eth_dev); vf++) {\n\t\t/* check & process vf function level reset */\n\t\tif (!ixgbe_check_for_rst(hw, vf))\n\t\t\tixgbe_vf_reset_event(eth_dev, vf);\n\n\t\t/* check & process vf mailbox messages */\n\t\tif (!ixgbe_check_for_msg(hw, vf))\n\t\t\tixgbe_rcv_msg_from_vf(eth_dev, vf);\n\n\t\t/* check & process acks from vf */\n\t\tif (!ixgbe_check_for_ack(hw, vf))\n\t\t\tixgbe_rcv_ack_from_vf(eth_dev, vf);\n\t}\n}\n" }, { "path": "drivers/net/ixgbe/ixgbe_regs.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef _IXGBE_REGS_H_\n#define _IXGBE_REGS_H_\n\n#include \"ixgbe_ethdev.h\"\n\nstruct ixgbe_hw;\nstruct reg_info {\n\tuint32_t base_addr;\n\tuint32_t count;\n\tuint32_t stride;\n\tconst char *name;\n} reg_info;\n\nstatic const struct reg_info ixgbe_regs_general[] = {\n\t{IXGBE_CTRL, 1, 1, \"IXGBE_CTRL\"},\n\t{IXGBE_STATUS, 1, 1, \"IXGBE_STATUS\"},\n\t{IXGBE_CTRL_EXT, 1, 1, \"IXGBE_CTRL_EXT\"},\n\t{IXGBE_ESDP, 1, 1, \"IXGBE_ESDP\"},\n\t{IXGBE_EODSDP, 1, 1, \"IXGBE_EODSDP\"},\n\t{IXGBE_LEDCTL, 1, 1, \"IXGBE_LEDCTL\"},\n\t{IXGBE_FRTIMER, 1, 1, \"IXGBE_FRTIMER\"},\n\t{IXGBE_TCPTIMER, 1, 1, \"IXGBE_TCPTIMER\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbevf_regs_general[] = {\n\t{IXGBE_CTRL, 1, 1, \"IXGBE_CTRL\"},\n\t{IXGBE_STATUS, 1, 1, \"IXGBE_STATUS\"},\n\t{IXGBE_VFLINKS, 1, 1, \"IXGBE_VFLINKS\"},\n\t{IXGBE_FRTIMER, 1, 1, \"IXGBE_FRTIMER\"},\n\t{IXGBE_VFMAILBOX, 1, 1, \"IXGBE_VFMAILBOX\"},\n\t{IXGBE_VFMBMEM, 16, 4, \"IXGBE_VFMBMEM\"},\n\t{IXGBE_VFRXMEMWRAP, 1, 1, \"IXGBE_VFRXMEMWRAP\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbe_regs_nvm[] = {\n\t{IXGBE_EEC, 1, 1, \"IXGBE_EEC\"},\n\t{IXGBE_EERD, 1, 1, \"IXGBE_EERD\"},\n\t{IXGBE_FLA, 1, 1, \"IXGBE_FLA\"},\n\t{IXGBE_EEMNGCTL, 1, 1, \"IXGBE_EEMNGCTL\"},\n\t{IXGBE_EEMNGDATA, 1, 1, \"IXGBE_EEMNGDATA\"},\n\t{IXGBE_FLMNGCTL, 1, 1, \"IXGBE_FLMNGCTL\"},\n\t{IXGBE_FLMNGDATA, 1, 1, \"IXGBE_FLMNGDATA\"},\n\t{IXGBE_FLMNGCNT, 1, 1, \"IXGBE_FLMNGCNT\"},\n\t{IXGBE_FLOP, 1, 1, \"IXGBE_FLOP\"},\n\t{IXGBE_GRC, 1, 1, \"IXGBE_GRC\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbe_regs_interrupt[] = {\n\t{IXGBE_EICS, 1, 1, \"IXGBE_EICS\"},\n\t{IXGBE_EIMS, 1, 1, \"IXGBE_EIMS\"},\n\t{IXGBE_EIMC, 1, 1, \"IXGBE_EIMC\"},\n\t{IXGBE_EIAC, 1, 1, \"IXGBE_EIAC\"},\n\t{IXGBE_EIAM, 1, 1, \"IXGBE_EIAM\"},\n\t{IXGBE_EITR(0), 24, 4, \"IXGBE_EITR\"},\n\t{IXGBE_IVAR(0), 24, 4, \"IXGBE_IVAR\"},\n\t{IXGBE_MSIXT, 1, 1, \"IXGBE_MSIXT\"},\n\t{IXGBE_MSIXPBA, 1, 1, \"IXGBE_MSIXPBA\"},\n\t{IXGBE_PBACL(0), 1, 4, \"IXGBE_PBACL\"},\n\t{IXGBE_GPIE, 1, 1, \"\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbevf_regs_interrupt[] = {\n\t{IXGBE_VTEICR, 1, 1, \"IXGBE_VTEICR\"},\n\t{IXGBE_VTEICS, 1, 1, \"IXGBE_VTEICS\"},\n\t{IXGBE_VTEIMS, 1, 1, \"IXGBE_VTEIMS\"},\n\t{IXGBE_VTEIMC, 1, 1, \"IXGBE_VTEIMC\"},\n\t{IXGBE_VTEIAM, 1, 1, \"IXGBE_VTEIAM\"},\n\t{IXGBE_VTEITR(0), 2, 4, \"IXGBE_VTEITR\"},\n\t{IXGBE_VTIVAR(0), 4, 4, \"IXGBE_VTIVAR\"},\n\t{IXGBE_VTIVAR_MISC, 1, 1, \"IXGBE_VTIVAR_MISC\"},\n\t{IXGBE_VTRSCINT(0), 2, 4, \"IXGBE_VTRSCINT\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbe_regs_fctl_mac_82598EB[] = {\n\t{IXGBE_PFCTOP, 1, 1, \"\"},\n\t{IXGBE_FCTTV(0), 4, 4, \"\"},\n\t{IXGBE_FCRTV, 1, 1, \"\"},\n\t{IXGBE_TFCS, 1, 1, \"\"},\n\t{IXGBE_FCRTL(0), 8, 8, \"IXGBE_FCRTL\"},\n\t{IXGBE_FCRTH(0), 8, 8, \"IXGBE_FCRTH\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbe_regs_fctl_others[] = {\n\t{IXGBE_PFCTOP, 1, 1, \"\"},\n\t{IXGBE_FCTTV(0), 4, 4, \"\"},\n\t{IXGBE_FCRTV, 1, 1, \"\"},\n\t{IXGBE_TFCS, 1, 1, \"\"},\n\t{IXGBE_FCRTL_82599(0), 8, 4, \"IXGBE_FCRTL\"},\n\t{IXGBE_FCRTH_82599(0), 8, 4, \"IXGBE_FCRTH\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbe_regs_rxdma[] = {\n\t{IXGBE_RDBAL(0), 64, 0x40, \"IXGBE_RDBAL\"},\n\t{IXGBE_RDBAH(0), 64, 0x40, \"IXGBE_RDBAH\"},\n\t{IXGBE_RDLEN(0), 64, 0x40, \"IXGBE_RDLEN\"},\n\t{IXGBE_RDH(0), 64, 0x40, \"IXGBE_RDH\"},\n\t{IXGBE_RDT(0), 64, 0x40, \"IXGBE_RDT\"},\n\t{IXGBE_RXDCTL(0), 64, 0x40, \"IXGBE_RXDCTL\"},\n\t{IXGBE_SRRCTL(0), 16, 0x4, \"IXGBE_SRRCTL\"},\n\t{IXGBE_DCA_RXCTRL(0), 16, 4, \"IXGBE_DCA_RXCTRL\"},\n\t{IXGBE_RDRXCTL, 1, 1, \"IXGBE_RDRXCTL\"},\n\t{IXGBE_RXPBSIZE(0), 8, 4, \"IXGBE_RXPBSIZE\"},\n\t{IXGBE_RXCTRL, 1, 1, \"IXGBE_RXCTRL\"},\n\t{IXGBE_DROPEN, 1, 1, \"IXGBE_DROPEN\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbevf_regs_rxdma[] = {\n\t{IXGBE_RDBAL(0), 8, 0x40, \"IXGBE_RDBAL\"},\n\t{IXGBE_RDBAH(0), 8, 0x40, \"IXGBE_RDBAH\"},\n\t{IXGBE_RDLEN(0), 8, 0x40, \"IXGBE_RDLEN\"},\n\t{IXGBE_RDH(0), 8, 0x40, \"IXGBE_RDH\"},\n\t{IXGBE_RDT(0), 8, 0x40, \"IXGBE_RDT\"},\n\t{IXGBE_RXDCTL(0), 8, 0x40, \"IXGBE_RXDCTL\"},\n\t{IXGBE_SRRCTL(0), 8, 0x40, \"IXGBE_SRRCTL\"},\n\t{IXGBE_VFPSRTYPE, 1, 1,\t\"IXGBE_VFPSRTYPE\"},\n\t{IXGBE_VFRSCCTL(0), 8, 0x40, \"IXGBE_VFRSCCTL\"},\n\t{IXGBE_PVFDCA_RXCTRL(0), 8, 0x40, \"IXGBE_PVFDCA_RXCTRL\"},\n\t{IXGBE_PVFDCA_TXCTRL(0), 8, 0x40, \"IXGBE_PVFDCA_TXCTRL\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbe_regs_rx[] = {\n\t{IXGBE_RXCSUM, 1, 1, \"IXGBE_RXCSUM\"},\n\t{IXGBE_RFCTL, 1, 1, \"IXGBE_RFCTL\"},\n\t{IXGBE_RAL(0), 16, 8, \"IXGBE_RAL\"},\n\t{IXGBE_RAH(0), 16, 8, \"IXGBE_RAH\"},\n\t{IXGBE_PSRTYPE(0), 1, 4, \"IXGBE_PSRTYPE\"},\n\t{IXGBE_FCTRL, 1, 1, \"IXGBE_FCTRL\"},\n\t{IXGBE_VLNCTRL, 1, 1, \"IXGBE_VLNCTRL\"},\n\t{IXGBE_MCSTCTRL, 1, 1, \"IXGBE_MCSTCTRL\"},\n\t{IXGBE_MRQC, 1, 1, \"IXGBE_MRQC\"},\n\t{IXGBE_VMD_CTL, 1, 1, \"IXGBE_VMD_CTL\"},\n\t{IXGBE_IMIR(0), 8, 4, \"IXGBE_IMIR\"},\n\t{IXGBE_IMIREXT(0), 8, 4, \"IXGBE_IMIREXT\"},\n\t{IXGBE_IMIRVP, 1, 1, \"IXGBE_IMIRVP\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic struct reg_info ixgbe_regs_tx[] = {\n\t{IXGBE_TDBAL(0), 32, 0x40, \"IXGBE_TDBAL\"},\n\t{IXGBE_TDBAH(0), 32, 0x40, \"IXGBE_TDBAH\"},\n\t{IXGBE_TDLEN(0), 32, 0x40, \"IXGBE_TDLEN\"},\n\t{IXGBE_TDH(0), 32, 0x40, \"IXGBE_TDH\"},\n\t{IXGBE_TDT(0), 32, 0x40, \"IXGBE_TDT\"},\n\t{IXGBE_TXDCTL(0), 32, 0x40, \"IXGBE_TXDCTL\"},\n\t{IXGBE_TDWBAL(0), 32, 0x40, \"IXGBE_TDWBAL\"},\n\t{IXGBE_TDWBAH(0), 32, 0x40, \"IXGBE_TDWBAH\"},\n\t{IXGBE_DTXCTL, 1, 1, \"IXGBE_DTXCTL\"},\n\t{IXGBE_DCA_TXCTRL(0), 16, 4, \"IXGBE_DCA_TXCTRL\"},\n\t{IXGBE_TXPBSIZE(0), 8, 4, \"IXGBE_TXPBSIZE\"},\n\t{IXGBE_MNGTXMAP, 1, 1, \"IXGBE_MNGTXMAP\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbevf_regs_tx[] = {\n\t{IXGBE_TDBAL(0), 4, 0x40, \"IXGBE_TDBAL\"},\n\t{IXGBE_TDBAH(0), 4, 0x40, \"IXGBE_TDBAH\"},\n\t{IXGBE_TDLEN(0), 4, 0x40, \"IXGBE_TDLEN\"},\n\t{IXGBE_TDH(0), 4, 0x40, \"IXGBE_TDH\"},\n\t{IXGBE_TDT(0), 4, 0x40, \"IXGBE_TDT\"},\n\t{IXGBE_TXDCTL(0), 4, 0x40, \"IXGBE_TXDCTL\"},\n\t{IXGBE_TDWBAL(0), 4, 0x40, \"IXGBE_TDWBAL\"},\n\t{IXGBE_TDWBAH(0), 4, 0x40, \"IXGBE_TDWBAH\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbe_regs_wakeup[] = {\n\t{IXGBE_WUC, 1, 1, \"IXGBE_WUC\"},\n\t{IXGBE_WUFC, 1, 1, \"IXGBE_WUFC\"},\n\t{IXGBE_WUS, 1, 1, \"IXGBE_WUS\"},\n\t{IXGBE_IPAV, 1, 1, \"IXGBE_IPAV\"},\n\t{IXGBE_IP4AT, 1, 1, \"IXGBE_IP4AT\"},\n\t{IXGBE_IP6AT, 1, 1, \"IXGBE_IP6AT\"},\n\t{IXGBE_WUPL, 1, 1, \"IXGBE_WUPL\"},\n\t{IXGBE_WUPM, 1, 1, \"IXGBE_WUPM\"},\n\t{IXGBE_FHFT(0), 1, 1, \"IXGBE_FHFT\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbe_regs_dcb[] = {\n\t{IXGBE_RMCS, 1, 1, \"IXGBE_RMCS\"},\n\t{IXGBE_DPMCS, 1, 1, \"IXGBE_DPMCS\"},\n\t{IXGBE_PDPMCS, 1, 1, \"IXGBE_PDPMCS\"},\n\t{IXGBE_RUPPBMR, 1, 1, \"IXGBE_RUPPBMR\"},\n\t{IXGBE_RT2CR(0), 8, 4, \"IXGBE_RT2CR\"},\n\t{IXGBE_RT2SR(0), 8, 4, \"IXGBE_RT2SR\"},\n\t{IXGBE_TDTQ2TCCR(0), 8, 0x40, \"IXGBE_TDTQ2TCCR\"},\n\t{IXGBE_TDTQ2TCSR(0), 8, 0x40, \"IXGBE_TDTQ2TCSR\"},\n\t{IXGBE_TDPT2TCCR(0), 8, 4, \"IXGBE_TDPT2TCCR\"},\n\t{IXGBE_TDPT2TCSR(0), 8, 4, \"IXGBE_TDPT2TCSR\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbe_regs_mac[] = {\n\t{IXGBE_PCS1GCFIG, 1, 1, \"IXGBE_PCS1GCFIG\"},\n\t{IXGBE_PCS1GLCTL, 1, 1, \"IXGBE_PCS1GLCTL\"},\n\t{IXGBE_PCS1GLSTA, 1, 1, \"IXGBE_PCS1GLSTA\"},\n\t{IXGBE_PCS1GDBG0, 1, 1, \"IXGBE_PCS1GDBG0\"},\n\t{IXGBE_PCS1GDBG1, 1, 1, \"IXGBE_PCS1GDBG1\"},\n\t{IXGBE_PCS1GANA, 1, 1, \"IXGBE_PCS1GANA\"},\n\t{IXGBE_PCS1GANLP, 1, 1, \"IXGBE_PCS1GANLP\"},\n\t{IXGBE_PCS1GANNP, 1, 1, \"IXGBE_PCS1GANNP\"},\n\t{IXGBE_PCS1GANLPNP, 1, 1, \"IXGBE_PCS1GANLPNP\"},\n\t{IXGBE_HLREG0, 1, 1, \"IXGBE_HLREG0\"},\n\t{IXGBE_HLREG1, 1, 1, \"IXGBE_HLREG1\"},\n\t{IXGBE_PAP, 1, 1, \"IXGBE_PAP\"},\n\t{IXGBE_MACA, 1, 1, \"IXGBE_MACA\"},\n\t{IXGBE_APAE, 1, 1, \"IXGBE_APAE\"},\n\t{IXGBE_ARD, 1, 1, \"IXGBE_ARD\"},\n\t{IXGBE_AIS, 1, 1, \"IXGBE_AIS\"},\n\t{IXGBE_MSCA, 1, 1, \"IXGBE_MSCA\"},\n\t{IXGBE_MSRWD, 1, 1, \"IXGBE_MSRWD\"},\n\t{IXGBE_MLADD, 1, 1, \"IXGBE_MLADD\"},\n\t{IXGBE_MHADD, 1, 1, \"IXGBE_MHADD\"},\n\t{IXGBE_TREG, 1, 1, \"IXGBE_TREG\"},\n\t{IXGBE_PCSS1, 1, 1, \"IXGBE_PCSS1\"},\n\t{IXGBE_PCSS2, 1, 1, \"IXGBE_PCSS2\"},\n\t{IXGBE_XPCSS, 1, 1, \"IXGBE_XPCSS\"},\n\t{IXGBE_SERDESC, 1, 1, \"IXGBE_SERDESC\"},\n\t{IXGBE_MACS, 1, 1, \"IXGBE_MACS\"},\n\t{IXGBE_AUTOC, 1, 1, \"IXGBE_AUTOC\"},\n\t{IXGBE_LINKS, 1, 1, \"IXGBE_LINKS\"},\n\t{IXGBE_AUTOC2, 1, 1, \"IXGBE_AUTOC2\"},\n\t{IXGBE_AUTOC3, 1, 1, \"IXGBE_AUTOC3\"},\n\t{IXGBE_ANLP1, 1, 1, \"IXGBE_ANLP1\"},\n\t{IXGBE_ANLP2, 1, 1, \"IXGBE_ANLP2\"},\n\t{IXGBE_ATLASCTL, 1, 1, \"IXGBE_ATLASCTL\"},\n\t{0, 0, 0, \"\"}\n};\n\nstatic const struct reg_info ixgbe_regs_diagnostic[] = {\n\t{IXGBE_RDSTATCTL, 1, 1, \"IXGBE_RDSTATCTL\"},\n\t{IXGBE_RDSTAT(0), 8, 4, \"IXGBE_RDSTAT\"},\n\t{IXGBE_RDHMPN, 1, 1, \"IXGBE_RDHMPN\"},\n\t{IXGBE_RIC_DW(0), 4, 4, \"IXGBE_RIC_DW\"},\n\t{IXGBE_RDPROBE, 1, 1, \"IXGBE_RDPROBE\"},\n\t{IXGBE_TDHMPN, 1, 1, \"IXGBE_TDHMPN\"},\n\t{IXGBE_TIC_DW(0), 4, 4, \"IXGBE_TIC_DW\"},\n\t{IXGBE_TDPROBE, 1, 1, \"IXGBE_TDPROBE\"},\n\t{IXGBE_TXBUFCTRL, 1, 1, \"IXGBE_TXBUFCTRL\"},\n\t{IXGBE_TXBUFDATA0, 1, 1, \"IXGBE_TXBUFDATA0\"},\n\t{IXGBE_TXBUFDATA1, 1, 1, \"IXGBE_TXBUFDATA1\"},\n\t{IXGBE_TXBUFDATA2, 1, 1, \"IXGBE_TXBUFDATA2\"},\n\t{IXGBE_TXBUFDATA3, 1, 1, \"IXGBE_TXBUFDATA3\"},\n\t{IXGBE_RXBUFCTRL, 1, 1, \"IXGBE_RXBUFCTRL\"},\n\t{IXGBE_RXBUFDATA0, 1, 1, \"IXGBE_RXBUFDATA0\"},\n\t{IXGBE_RXBUFDATA1, 1, 1, \"IXGBE_RXBUFDATA1\"},\n\t{IXGBE_RXBUFDATA2, 1, 1, \"IXGBE_RXBUFDATA2\"},\n\t{IXGBE_RXBUFDATA3, 1, 1, \"IXGBE_RXBUFDATA3\"},\n\t{IXGBE_PCIE_DIAG(0), 8, 4, \"\"},\n\t{IXGBE_RFVAL, 1, 1, \"IXGBE_RFVAL\"},\n\t{IXGBE_MDFTC1, 1, 1, \"IXGBE_MDFTC1\"},\n\t{IXGBE_MDFTC2, 1, 1, \"IXGBE_MDFTC2\"},\n\t{IXGBE_MDFTFIFO1, 1, 1, \"IXGBE_MDFTFIFO1\"},\n\t{IXGBE_MDFTFIFO2, 1, 1, \"IXGBE_MDFTFIFO2\"},\n\t{IXGBE_MDFTS, 1, 1, \"IXGBE_MDFTS\"},\n\t{IXGBE_PCIEECCCTL, 1, 1, \"IXGBE_PCIEECCCTL\"},\n\t{IXGBE_PBTXECC, 1, 1, \"IXGBE_PBTXECC\"},\n\t{IXGBE_PBRXECC, 1, 1, \"IXGBE_PBRXECC\"},\n\t{IXGBE_MFLCN, 1, 1, \"IXGBE_MFLCN\"},\n\t{0, 0, 0, \"\"},\n};\n\n/* PF registers */\nstatic const struct reg_info *ixgbe_regs_others[] = {\n\t\t\t\tixgbe_regs_general,\n\t\t\t\tixgbe_regs_nvm, ixgbe_regs_interrupt,\n\t\t\t\tixgbe_regs_fctl_others,\n\t\t\t\tixgbe_regs_rxdma,\n\t\t\t\tixgbe_regs_rx,\n\t\t\t\tixgbe_regs_tx,\n\t\t\t\tixgbe_regs_wakeup,\n\t\t\t\tixgbe_regs_dcb,\n\t\t\t\tixgbe_regs_mac,\n\t\t\t\tixgbe_regs_diagnostic,\n\t\t\t\tNULL};\n\nstatic const struct reg_info *ixgbe_regs_mac_82598EB[] = {\n\t\t\t\tixgbe_regs_general,\n\t\t\t\tixgbe_regs_nvm,\n\t\t\t\tixgbe_regs_interrupt,\n\t\t\t\tixgbe_regs_fctl_mac_82598EB,\n\t\t\t\tixgbe_regs_rxdma,\n\t\t\t\tixgbe_regs_rx,\n\t\t\t\tixgbe_regs_tx,\n\t\t\t\tixgbe_regs_wakeup,\n\t\t\t\tixgbe_regs_dcb,\n\t\t\t\tixgbe_regs_mac,\n\t\t\t\tixgbe_regs_diagnostic,\n\t\t\t\tNULL};\n\n/* VF registers */\nstatic const struct reg_info *ixgbevf_regs[] = {\n\t\t\t\tixgbevf_regs_general,\n\t\t\t\tixgbevf_regs_interrupt,\n\t\t\t\tixgbevf_regs_rxdma,\n\t\t\t\tixgbevf_regs_tx,\n\t\t\t\tNULL};\n\nstatic inline int\nixgbe_read_regs(struct ixgbe_hw *hw, const struct reg_info *reg,\n\tuint32_t *reg_buf)\n{\n\tunsigned int i;\n\n\tfor (i = 0; i < reg->count; i++)\n\t\treg_buf[i] = IXGBE_READ_REG(hw,\n\t\t\t\t\treg->base_addr + i * reg->stride);\n\treturn reg->count;\n};\n\nstatic inline int\nixgbe_regs_group_count(const struct reg_info *regs)\n{\n\tint count = 0;\n\tint i = 0;\n\n\twhile (regs[i].count)\n\t\tcount += regs[i++].count;\n\treturn count;\n};\n\nstatic inline int\nixgbe_read_regs_group(struct rte_eth_dev *dev, uint32_t *reg_buf,\n\t\t\t\t\t const struct reg_info *regs)\n{\n\tint count = 0;\n\tint i = 0;\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\twhile (regs[i].count)\n\t\tcount += ixgbe_read_regs(hw, ®s[i++], ®_buf[count]);\n\treturn count;\n};\n\n#endif /* _IXGBE_REGS_H_ */\n" }, { "path": "drivers/net/ixgbe/ixgbe_rxtx.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * Copyright 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"ixgbe_logs.h\"\n#include \"base/ixgbe_api.h\"\n#include \"base/ixgbe_vf.h\"\n#include \"ixgbe_ethdev.h\"\n#include \"base/ixgbe_dcb.h\"\n#include \"base/ixgbe_common.h\"\n#include \"ixgbe_rxtx.h\"\n\n/* Bit Mask to indicate what bits required for building TX context */\n#define IXGBE_TX_OFFLOAD_MASK (\t\t\t \\\n\t\tPKT_TX_VLAN_PKT |\t\t \\\n\t\tPKT_TX_IP_CKSUM |\t\t \\\n\t\tPKT_TX_L4_MASK |\t\t \\\n\t\tPKT_TX_TCP_SEG)\n\nstatic inline struct rte_mbuf *\nrte_rxmbuf_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\n\tm = __rte_mbuf_raw_alloc(mp);\n\t__rte_mbuf_sanity_check_raw(m, 0);\n\treturn (m);\n}\n\n\n#if 1\n#define RTE_PMD_USE_PREFETCH\n#endif\n\n#ifdef RTE_PMD_USE_PREFETCH\n/*\n * Prefetch a cache line into all cache levels.\n */\n#define rte_ixgbe_prefetch(p) rte_prefetch0(p)\n#else\n#define rte_ixgbe_prefetch(p) do {} while(0)\n#endif\n\n/*********************************************************************\n *\n * TX functions\n *\n **********************************************************************/\n\n/*\n * Check for descriptors with their DD bit set and free mbufs.\n * Return the total number of buffers freed.\n */\nstatic inline int __attribute__((always_inline))\nixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)\n{\n\tstruct ixgbe_tx_entry *txep;\n\tuint32_t status;\n\tint i;\n\n\t/* check DD bit on threshold descriptor */\n\tstatus = txq->tx_ring[txq->tx_next_dd].wb.status;\n\tif (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))\n\t\treturn 0;\n\n\t/*\n\t * first buffer to free from S/W ring is at index\n\t * tx_next_dd - (tx_rs_thresh-1)\n\t */\n\ttxep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);\n\n\t/* free buffers one at a time */\n\tif ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {\n\t\tfor (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {\n\t\t\ttxep->mbuf->next = NULL;\n\t\t\trte_mempool_put(txep->mbuf->pool, txep->mbuf);\n\t\t\ttxep->mbuf = NULL;\n\t\t}\n\t} else {\n\t\tfor (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {\n\t\t\trte_pktmbuf_free_seg(txep->mbuf);\n\t\t\ttxep->mbuf = NULL;\n\t\t}\n\t}\n\n\t/* buffers were freed, update counters */\n\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);\n\ttxq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);\n\tif (txq->tx_next_dd >= txq->nb_tx_desc)\n\t\ttxq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);\n\n\treturn txq->tx_rs_thresh;\n}\n\n/* Populate 4 descriptors with data from 4 mbufs */\nstatic inline void\ntx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)\n{\n\tuint64_t buf_dma_addr;\n\tuint32_t pkt_len;\n\tint i;\n\n\tfor (i = 0; i < 4; ++i, ++txdp, ++pkts) {\n\t\tbuf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);\n\t\tpkt_len = (*pkts)->data_len;\n\n\t\t/* write data to descriptor */\n\t\ttxdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);\n\n\t\ttxdp->read.cmd_type_len =\n\t\t\trte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);\n\n\t\ttxdp->read.olinfo_status =\n\t\t\trte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);\n\n\t\trte_prefetch0(&(*pkts)->pool);\n\t}\n}\n\n/* Populate 1 descriptor with data from 1 mbuf */\nstatic inline void\ntx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)\n{\n\tuint64_t buf_dma_addr;\n\tuint32_t pkt_len;\n\n\tbuf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);\n\tpkt_len = (*pkts)->data_len;\n\n\t/* write data to descriptor */\n\ttxdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);\n\ttxdp->read.cmd_type_len =\n\t\t\trte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);\n\ttxdp->read.olinfo_status =\n\t\t\trte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);\n\trte_prefetch0(&(*pkts)->pool);\n}\n\n/*\n * Fill H/W descriptor ring with mbuf data.\n * Copy mbuf pointers to the S/W ring.\n */\nstatic inline void\nixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,\n\t\t uint16_t nb_pkts)\n{\n\tvolatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);\n\tstruct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);\n\tconst int N_PER_LOOP = 4;\n\tconst int N_PER_LOOP_MASK = N_PER_LOOP-1;\n\tint mainpart, leftover;\n\tint i, j;\n\n\t/*\n\t * Process most of the packets in chunks of N pkts. Any\n\t * leftover packets will get processed one at a time.\n\t */\n\tmainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));\n\tleftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));\n\tfor (i = 0; i < mainpart; i += N_PER_LOOP) {\n\t\t/* Copy N mbuf pointers to the S/W ring */\n\t\tfor (j = 0; j < N_PER_LOOP; ++j) {\n\t\t\t(txep + i + j)->mbuf = *(pkts + i + j);\n\t\t}\n\t\ttx4(txdp + i, pkts + i);\n\t}\n\n\tif (unlikely(leftover > 0)) {\n\t\tfor (i = 0; i < leftover; ++i) {\n\t\t\t(txep + mainpart + i)->mbuf = *(pkts + mainpart + i);\n\t\t\ttx1(txdp + mainpart + i, pkts + mainpart + i);\n\t\t}\n\t}\n}\n\nstatic inline uint16_t\ntx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t uint16_t nb_pkts)\n{\n\tstruct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;\n\tvolatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;\n\tuint16_t n = 0;\n\n\t/*\n\t * Begin scanning the H/W ring for done descriptors when the\n\t * number of available descriptors drops below tx_free_thresh. For\n\t * each done descriptor, free the associated buffer.\n\t */\n\tif (txq->nb_tx_free < txq->tx_free_thresh)\n\t\tixgbe_tx_free_bufs(txq);\n\n\t/* Only use descriptors that are available */\n\tnb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);\n\tif (unlikely(nb_pkts == 0))\n\t\treturn 0;\n\n\t/* Use exactly nb_pkts descriptors */\n\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);\n\n\t/*\n\t * At this point, we know there are enough descriptors in the\n\t * ring to transmit all the packets. This assumes that each\n\t * mbuf contains a single segment, and that no new offloads\n\t * are expected, which would require a new context descriptor.\n\t */\n\n\t/*\n\t * See if we're going to wrap-around. If so, handle the top\n\t * of the descriptor ring first, then do the bottom. If not,\n\t * the processing looks just like the \"bottom\" part anyway...\n\t */\n\tif ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {\n\t\tn = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);\n\t\tixgbe_tx_fill_hw_ring(txq, tx_pkts, n);\n\n\t\t/*\n\t\t * We know that the last descriptor in the ring will need to\n\t\t * have its RS bit set because tx_rs_thresh has to be\n\t\t * a divisor of the ring size\n\t\t */\n\t\ttx_r[txq->tx_next_rs].read.cmd_type_len |=\n\t\t\trte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);\n\t\ttxq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);\n\n\t\ttxq->tx_tail = 0;\n\t}\n\n\t/* Fill H/W descriptor ring with mbuf data */\n\tixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));\n\ttxq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));\n\n\t/*\n\t * Determine if RS bit should be set\n\t * This is what we actually want:\n\t * if ((txq->tx_tail - 1) >= txq->tx_next_rs)\n\t * but instead of subtracting 1 and doing >=, we can just do\n\t * greater than without subtracting.\n\t */\n\tif (txq->tx_tail > txq->tx_next_rs) {\n\t\ttx_r[txq->tx_next_rs].read.cmd_type_len |=\n\t\t\trte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);\n\t\ttxq->tx_next_rs = (uint16_t)(txq->tx_next_rs +\n\t\t\t\t\t\ttxq->tx_rs_thresh);\n\t\tif (txq->tx_next_rs >= txq->nb_tx_desc)\n\t\t\ttxq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);\n\t}\n\n\t/*\n\t * Check for wrap-around. This would only happen if we used\n\t * up to the last descriptor in the ring, no more, no less.\n\t */\n\tif (txq->tx_tail >= txq->nb_tx_desc)\n\t\ttxq->tx_tail = 0;\n\n\t/* update tail pointer */\n\trte_wmb();\n\tIXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);\n\n\treturn nb_pkts;\n}\n\nuint16_t\nixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t\t uint16_t nb_pkts)\n{\n\tuint16_t nb_tx;\n\n\t/* Try to transmit at least chunks of TX_MAX_BURST pkts */\n\tif (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))\n\t\treturn tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);\n\n\t/* transmit more than the max burst, in chunks of TX_MAX_BURST */\n\tnb_tx = 0;\n\twhile (nb_pkts) {\n\t\tuint16_t ret, n;\n\t\tn = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);\n\t\tret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);\n\t\tnb_tx = (uint16_t)(nb_tx + ret);\n\t\tnb_pkts = (uint16_t)(nb_pkts - ret);\n\t\tif (ret < n)\n\t\t\tbreak;\n\t}\n\n\treturn nb_tx;\n}\n\nstatic inline void\nixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,\n\t\tvolatile struct ixgbe_adv_tx_context_desc *ctx_txd,\n\t\tuint64_t ol_flags, union ixgbe_tx_offload tx_offload)\n{\n\tuint32_t type_tucmd_mlhl;\n\tuint32_t mss_l4len_idx = 0;\n\tuint32_t ctx_idx;\n\tuint32_t vlan_macip_lens;\n\tunion ixgbe_tx_offload tx_offload_mask;\n\n\tctx_idx = txq->ctx_curr;\n\ttx_offload_mask.data = 0;\n\ttype_tucmd_mlhl = 0;\n\n\t/* Specify which HW CTX to upload. */\n\tmss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);\n\n\tif (ol_flags & PKT_TX_VLAN_PKT) {\n\t\ttx_offload_mask.vlan_tci |= ~0;\n\t}\n\n\t/* check if TCP segmentation required for this packet */\n\tif (ol_flags & PKT_TX_TCP_SEG) {\n\t\t/* implies IP cksum in IPv4 */\n\t\tif (ol_flags & PKT_TX_IP_CKSUM)\n\t\t\ttype_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |\n\t\t\t\tIXGBE_ADVTXD_TUCMD_L4T_TCP |\n\t\t\t\tIXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;\n\t\telse\n\t\t\ttype_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |\n\t\t\t\tIXGBE_ADVTXD_TUCMD_L4T_TCP |\n\t\t\t\tIXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;\n\n\t\ttx_offload_mask.l2_len |= ~0;\n\t\ttx_offload_mask.l3_len |= ~0;\n\t\ttx_offload_mask.l4_len |= ~0;\n\t\ttx_offload_mask.tso_segsz |= ~0;\n\t\tmss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;\n\t\tmss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;\n\t} else { /* no TSO, check if hardware checksum is needed */\n\t\tif (ol_flags & PKT_TX_IP_CKSUM) {\n\t\t\ttype_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;\n\t\t\ttx_offload_mask.l2_len |= ~0;\n\t\t\ttx_offload_mask.l3_len |= ~0;\n\t\t}\n\n\t\tswitch (ol_flags & PKT_TX_L4_MASK) {\n\t\tcase PKT_TX_UDP_CKSUM:\n\t\t\ttype_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |\n\t\t\t\tIXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;\n\t\t\tmss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;\n\t\t\ttx_offload_mask.l2_len |= ~0;\n\t\t\ttx_offload_mask.l3_len |= ~0;\n\t\t\tbreak;\n\t\tcase PKT_TX_TCP_CKSUM:\n\t\t\ttype_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |\n\t\t\t\tIXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;\n\t\t\tmss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;\n\t\t\ttx_offload_mask.l2_len |= ~0;\n\t\t\ttx_offload_mask.l3_len |= ~0;\n\t\t\ttx_offload_mask.l4_len |= ~0;\n\t\t\tbreak;\n\t\tcase PKT_TX_SCTP_CKSUM:\n\t\t\ttype_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |\n\t\t\t\tIXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;\n\t\t\tmss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;\n\t\t\ttx_offload_mask.l2_len |= ~0;\n\t\t\ttx_offload_mask.l3_len |= ~0;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\ttype_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |\n\t\t\t\tIXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\ttxq->ctx_cache[ctx_idx].flags = ol_flags;\n\ttxq->ctx_cache[ctx_idx].tx_offload.data =\n\t\ttx_offload_mask.data & tx_offload.data;\n\ttxq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;\n\n\tctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);\n\tvlan_macip_lens = tx_offload.l3_len;\n\tvlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);\n\tvlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);\n\tctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);\n\tctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);\n\tctx_txd->seqnum_seed = 0;\n}\n\n/*\n * Check which hardware context can be used. Use the existing match\n * or create a new context descriptor.\n */\nstatic inline uint32_t\nwhat_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,\n\t\tunion ixgbe_tx_offload tx_offload)\n{\n\t/* If match with the current used context */\n\tif (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&\n\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload.data ==\n\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {\n\t\t\treturn txq->ctx_curr;\n\t}\n\n\t/* What if match with the next context */\n\ttxq->ctx_curr ^= 1;\n\tif (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&\n\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload.data ==\n\t\t(txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {\n\t\t\treturn txq->ctx_curr;\n\t}\n\n\t/* Mismatch, use the previous context */\n\treturn (IXGBE_CTX_NUM);\n}\n\nstatic inline uint32_t\ntx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)\n{\n\tuint32_t tmp = 0;\n\tif ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)\n\t\ttmp |= IXGBE_ADVTXD_POPTS_TXSM;\n\tif (ol_flags & PKT_TX_IP_CKSUM)\n\t\ttmp |= IXGBE_ADVTXD_POPTS_IXSM;\n\tif (ol_flags & PKT_TX_TCP_SEG)\n\t\ttmp |= IXGBE_ADVTXD_POPTS_TXSM;\n\treturn tmp;\n}\n\nstatic inline uint32_t\ntx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)\n{\n\tuint32_t cmdtype = 0;\n\tif (ol_flags & PKT_TX_VLAN_PKT)\n\t\tcmdtype |= IXGBE_ADVTXD_DCMD_VLE;\n\tif (ol_flags & PKT_TX_TCP_SEG)\n\t\tcmdtype |= IXGBE_ADVTXD_DCMD_TSE;\n\treturn cmdtype;\n}\n\n/* Default RS bit threshold values */\n#ifndef DEFAULT_TX_RS_THRESH\n#define DEFAULT_TX_RS_THRESH 32\n#endif\n#ifndef DEFAULT_TX_FREE_THRESH\n#define DEFAULT_TX_FREE_THRESH 32\n#endif\n\n/* Reset transmit descriptors after they have been used */\nstatic inline int\nixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)\n{\n\tstruct ixgbe_tx_entry *sw_ring = txq->sw_ring;\n\tvolatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;\n\tuint16_t last_desc_cleaned = txq->last_desc_cleaned;\n\tuint16_t nb_tx_desc = txq->nb_tx_desc;\n\tuint16_t desc_to_clean_to;\n\tuint16_t nb_tx_to_clean;\n\tuint32_t status;\n\n\t/* Determine the last descriptor needing to be cleaned */\n\tdesc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);\n\tif (desc_to_clean_to >= nb_tx_desc)\n\t\tdesc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);\n\n\t/* Check to make sure the last descriptor to clean is done */\n\tdesc_to_clean_to = sw_ring[desc_to_clean_to].last_id;\n\tstatus = txr[desc_to_clean_to].wb.status;\n\tif (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD)))\n\t{\n\t\tPMD_TX_FREE_LOG(DEBUG,\n\t\t\t\t\"TX descriptor %4u is not done\"\n\t\t\t\t\"(port=%d queue=%d)\",\n\t\t\t\tdesc_to_clean_to,\n\t\t\t\ttxq->port_id, txq->queue_id);\n\t\t/* Failed to clean any descriptors, better luck next time */\n\t\treturn -(1);\n\t}\n\n\t/* Figure out how many descriptors will be cleaned */\n\tif (last_desc_cleaned > desc_to_clean_to)\n\t\tnb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +\n\t\t\t\t\t\t\tdesc_to_clean_to);\n\telse\n\t\tnb_tx_to_clean = (uint16_t)(desc_to_clean_to -\n\t\t\t\t\t\tlast_desc_cleaned);\n\n\tPMD_TX_FREE_LOG(DEBUG,\n\t\t\t\"Cleaning %4u TX descriptors: %4u to %4u \"\n\t\t\t\"(port=%d queue=%d)\",\n\t\t\tnb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,\n\t\t\ttxq->port_id, txq->queue_id);\n\n\t/*\n\t * The last descriptor to clean is done, so that means all the\n\t * descriptors from the last descriptor that was cleaned\n\t * up to the last descriptor with the RS bit set\n\t * are done. Only reset the threshold descriptor.\n\t */\n\ttxr[desc_to_clean_to].wb.status = 0;\n\n\t/* Update the txq to reflect the last descriptor that was cleaned */\n\ttxq->last_desc_cleaned = desc_to_clean_to;\n\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);\n\n\t/* No Error */\n\treturn (0);\n}\n\nuint16_t\nixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t\tuint16_t nb_pkts)\n{\n\tstruct ixgbe_tx_queue *txq;\n\tstruct ixgbe_tx_entry *sw_ring;\n\tstruct ixgbe_tx_entry *txe, *txn;\n\tvolatile union ixgbe_adv_tx_desc *txr;\n\tvolatile union ixgbe_adv_tx_desc *txd;\n\tstruct rte_mbuf *tx_pkt;\n\tstruct rte_mbuf *m_seg;\n\tuint64_t buf_dma_addr;\n\tuint32_t olinfo_status;\n\tuint32_t cmd_type_len;\n\tuint32_t pkt_len;\n\tuint16_t slen;\n\tuint64_t ol_flags;\n\tuint16_t tx_id;\n\tuint16_t tx_last;\n\tuint16_t nb_tx;\n\tuint16_t nb_used;\n\tuint64_t tx_ol_req;\n\tuint32_t ctx = 0;\n\tuint32_t new_ctx;\n\tunion ixgbe_tx_offload tx_offload = {0};\n\n\ttxq = tx_queue;\n\tsw_ring = txq->sw_ring;\n\ttxr = txq->tx_ring;\n\ttx_id = txq->tx_tail;\n\ttxe = &sw_ring[tx_id];\n\n\t/* Determine if the descriptor ring needs to be cleaned. */\n\tif (txq->nb_tx_free < txq->tx_free_thresh)\n\t\tixgbe_xmit_cleanup(txq);\n\n\trte_prefetch0(&txe->mbuf->pool);\n\n\t/* TX loop */\n\tfor (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {\n\t\tnew_ctx = 0;\n\t\ttx_pkt = *tx_pkts++;\n\t\tpkt_len = tx_pkt->pkt_len;\n\n\t\t/*\n\t\t * Determine how many (if any) context descriptors\n\t\t * are needed for offload functionality.\n\t\t */\n\t\tol_flags = tx_pkt->ol_flags;\n\n\t\t/* If hardware offload required */\n\t\ttx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;\n\t\tif (tx_ol_req) {\n\t\t\ttx_offload.l2_len = tx_pkt->l2_len;\n\t\t\ttx_offload.l3_len = tx_pkt->l3_len;\n\t\t\ttx_offload.l4_len = tx_pkt->l4_len;\n\t\t\ttx_offload.vlan_tci = tx_pkt->vlan_tci;\n\t\t\ttx_offload.tso_segsz = tx_pkt->tso_segsz;\n\n\t\t\t/* If new context need be built or reuse the exist ctx. */\n\t\t\tctx = what_advctx_update(txq, tx_ol_req,\n\t\t\t\ttx_offload);\n\t\t\t/* Only allocate context descriptor if required*/\n\t\t\tnew_ctx = (ctx == IXGBE_CTX_NUM);\n\t\t\tctx = txq->ctx_curr;\n\t\t}\n\n\t\t/*\n\t\t * Keep track of how many descriptors are used this loop\n\t\t * This will always be the number of segments + the number of\n\t\t * Context descriptors required to transmit the packet\n\t\t */\n\t\tnb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);\n\n\t\t/*\n\t\t * The number of descriptors that must be allocated for a\n\t\t * packet is the number of segments of that packet, plus 1\n\t\t * Context Descriptor for the hardware offload, if any.\n\t\t * Determine the last TX descriptor to allocate in the TX ring\n\t\t * for the packet, starting from the current position (tx_id)\n\t\t * in the ring.\n\t\t */\n\t\ttx_last = (uint16_t) (tx_id + nb_used - 1);\n\n\t\t/* Circular ring */\n\t\tif (tx_last >= txq->nb_tx_desc)\n\t\t\ttx_last = (uint16_t) (tx_last - txq->nb_tx_desc);\n\n\t\tPMD_TX_LOG(DEBUG, \"port_id=%u queue_id=%u pktlen=%u\"\n\t\t\t \" tx_first=%u tx_last=%u\",\n\t\t\t (unsigned) txq->port_id,\n\t\t\t (unsigned) txq->queue_id,\n\t\t\t (unsigned) pkt_len,\n\t\t\t (unsigned) tx_id,\n\t\t\t (unsigned) tx_last);\n\n\t\t/*\n\t\t * Make sure there are enough TX descriptors available to\n\t\t * transmit the entire packet.\n\t\t * nb_used better be less than or equal to txq->tx_rs_thresh\n\t\t */\n\t\tif (nb_used > txq->nb_tx_free) {\n\t\t\tPMD_TX_FREE_LOG(DEBUG,\n\t\t\t\t\t\"Not enough free TX descriptors \"\n\t\t\t\t\t\"nb_used=%4u nb_free=%4u \"\n\t\t\t\t\t\"(port=%d queue=%d)\",\n\t\t\t\t\tnb_used, txq->nb_tx_free,\n\t\t\t\t\ttxq->port_id, txq->queue_id);\n\n\t\t\tif (ixgbe_xmit_cleanup(txq) != 0) {\n\t\t\t\t/* Could not clean any descriptors */\n\t\t\t\tif (nb_tx == 0)\n\t\t\t\t\treturn (0);\n\t\t\t\tgoto end_of_tx;\n\t\t\t}\n\n\t\t\t/* nb_used better be <= txq->tx_rs_thresh */\n\t\t\tif (unlikely(nb_used > txq->tx_rs_thresh)) {\n\t\t\t\tPMD_TX_FREE_LOG(DEBUG,\n\t\t\t\t\t\"The number of descriptors needed to \"\n\t\t\t\t\t\"transmit the packet exceeds the \"\n\t\t\t\t\t\"RS bit threshold. This will impact \"\n\t\t\t\t\t\"performance.\"\n\t\t\t\t\t\"nb_used=%4u nb_free=%4u \"\n\t\t\t\t\t\"tx_rs_thresh=%4u. \"\n\t\t\t\t\t\"(port=%d queue=%d)\",\n\t\t\t\t\tnb_used, txq->nb_tx_free,\n\t\t\t\t\ttxq->tx_rs_thresh,\n\t\t\t\t\ttxq->port_id, txq->queue_id);\n\t\t\t\t/*\n\t\t\t\t * Loop here until there are enough TX\n\t\t\t\t * descriptors or until the ring cannot be\n\t\t\t\t * cleaned.\n\t\t\t\t */\n\t\t\t\twhile (nb_used > txq->nb_tx_free) {\n\t\t\t\t\tif (ixgbe_xmit_cleanup(txq) != 0) {\n\t\t\t\t\t\t/*\n\t\t\t\t\t\t * Could not clean any\n\t\t\t\t\t\t * descriptors\n\t\t\t\t\t\t */\n\t\t\t\t\t\tif (nb_tx == 0)\n\t\t\t\t\t\t\treturn (0);\n\t\t\t\t\t\tgoto end_of_tx;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/*\n\t\t * By now there are enough free TX descriptors to transmit\n\t\t * the packet.\n\t\t */\n\n\t\t/*\n\t\t * Set common flags of all TX Data Descriptors.\n\t\t *\n\t\t * The following bits must be set in all Data Descriptors:\n\t\t * - IXGBE_ADVTXD_DTYP_DATA\n\t\t * - IXGBE_ADVTXD_DCMD_DEXT\n\t\t *\n\t\t * The following bits must be set in the first Data Descriptor\n\t\t * and are ignored in the other ones:\n\t\t * - IXGBE_ADVTXD_DCMD_IFCS\n\t\t * - IXGBE_ADVTXD_MAC_1588\n\t\t * - IXGBE_ADVTXD_DCMD_VLE\n\t\t *\n\t\t * The following bits must only be set in the last Data\n\t\t * Descriptor:\n\t\t * - IXGBE_TXD_CMD_EOP\n\t\t *\n\t\t * The following bits can be set in any Data Descriptor, but\n\t\t * are only set in the last Data Descriptor:\n\t\t * - IXGBE_TXD_CMD_RS\n\t\t */\n\t\tcmd_type_len = IXGBE_ADVTXD_DTYP_DATA |\n\t\t\tIXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;\n\n#ifdef RTE_LIBRTE_IEEE1588\n\t\tif (ol_flags & PKT_TX_IEEE1588_TMST)\n\t\t\tcmd_type_len |= IXGBE_ADVTXD_MAC_1588;\n#endif\n\n\t\tolinfo_status = 0;\n\t\tif (tx_ol_req) {\n\n\t\t\tif (ol_flags & PKT_TX_TCP_SEG) {\n\t\t\t\t/* when TSO is on, paylen in descriptor is the\n\t\t\t\t * not the packet len but the tcp payload len */\n\t\t\t\tpkt_len -= (tx_offload.l2_len +\n\t\t\t\t\ttx_offload.l3_len + tx_offload.l4_len);\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Setup the TX Advanced Context Descriptor if required\n\t\t\t */\n\t\t\tif (new_ctx) {\n\t\t\t\tvolatile struct ixgbe_adv_tx_context_desc *\n\t\t\t\t ctx_txd;\n\n\t\t\t\tctx_txd = (volatile struct\n\t\t\t\t ixgbe_adv_tx_context_desc *)\n\t\t\t\t &txr[tx_id];\n\n\t\t\t\ttxn = &sw_ring[txe->next_id];\n\t\t\t\trte_prefetch0(&txn->mbuf->pool);\n\n\t\t\t\tif (txe->mbuf != NULL) {\n\t\t\t\t\trte_pktmbuf_free_seg(txe->mbuf);\n\t\t\t\t\ttxe->mbuf = NULL;\n\t\t\t\t}\n\n\t\t\t\tixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,\n\t\t\t\t\ttx_offload);\n\n\t\t\t\ttxe->last_id = tx_last;\n\t\t\t\ttx_id = txe->next_id;\n\t\t\t\ttxe = txn;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Setup the TX Advanced Data Descriptor,\n\t\t\t * This path will go through\n\t\t\t * whatever new/reuse the context descriptor\n\t\t\t */\n\t\t\tcmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);\n\t\t\tolinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);\n\t\t\tolinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;\n\t\t}\n\n\t\tolinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);\n\n\t\tm_seg = tx_pkt;\n\t\tdo {\n\t\t\ttxd = &txr[tx_id];\n\t\t\ttxn = &sw_ring[txe->next_id];\n\t\t\trte_prefetch0(&txn->mbuf->pool);\n\n\t\t\tif (txe->mbuf != NULL)\n\t\t\t\trte_pktmbuf_free_seg(txe->mbuf);\n\t\t\ttxe->mbuf = m_seg;\n\n\t\t\t/*\n\t\t\t * Set up Transmit Data Descriptor.\n\t\t\t */\n\t\t\tslen = m_seg->data_len;\n\t\t\tbuf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);\n\t\t\ttxd->read.buffer_addr =\n\t\t\t\trte_cpu_to_le_64(buf_dma_addr);\n\t\t\ttxd->read.cmd_type_len =\n\t\t\t\trte_cpu_to_le_32(cmd_type_len | slen);\n\t\t\ttxd->read.olinfo_status =\n\t\t\t\trte_cpu_to_le_32(olinfo_status);\n\t\t\ttxe->last_id = tx_last;\n\t\t\ttx_id = txe->next_id;\n\t\t\ttxe = txn;\n\t\t\tm_seg = m_seg->next;\n\t\t} while (m_seg != NULL);\n\n\t\t/*\n\t\t * The last packet data descriptor needs End Of Packet (EOP)\n\t\t */\n\t\tcmd_type_len |= IXGBE_TXD_CMD_EOP;\n\t\ttxq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);\n\t\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);\n\n\t\t/* Set RS bit only on threshold packets' last descriptor */\n\t\tif (txq->nb_tx_used >= txq->tx_rs_thresh) {\n\t\t\tPMD_TX_FREE_LOG(DEBUG,\n\t\t\t\t\t\"Setting RS bit on TXD id=\"\n\t\t\t\t\t\"%4u (port=%d queue=%d)\",\n\t\t\t\t\ttx_last, txq->port_id, txq->queue_id);\n\n\t\t\tcmd_type_len |= IXGBE_TXD_CMD_RS;\n\n\t\t\t/* Update txq RS bit counters */\n\t\t\ttxq->nb_tx_used = 0;\n\t\t}\n\t\ttxd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);\n\t}\nend_of_tx:\n\trte_wmb();\n\n\t/*\n\t * Set the Transmit Descriptor Tail (TDT)\n\t */\n\tPMD_TX_LOG(DEBUG, \"port_id=%u queue_id=%u tx_tail=%u nb_tx=%u\",\n\t\t (unsigned) txq->port_id, (unsigned) txq->queue_id,\n\t\t (unsigned) tx_id, (unsigned) nb_tx);\n\tIXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);\n\ttxq->tx_tail = tx_id;\n\n\treturn (nb_tx);\n}\n\n/*********************************************************************\n *\n * RX functions\n *\n **********************************************************************/\n#ifdef RTE_NEXT_ABI\n#define IXGBE_PACKET_TYPE_IPV4 0X01\n#define IXGBE_PACKET_TYPE_IPV4_TCP 0X11\n#define IXGBE_PACKET_TYPE_IPV4_UDP 0X21\n#define IXGBE_PACKET_TYPE_IPV4_SCTP 0X41\n#define IXGBE_PACKET_TYPE_IPV4_EXT 0X03\n#define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP 0X43\n#define IXGBE_PACKET_TYPE_IPV6 0X04\n#define IXGBE_PACKET_TYPE_IPV6_TCP 0X14\n#define IXGBE_PACKET_TYPE_IPV6_UDP 0X24\n#define IXGBE_PACKET_TYPE_IPV6_EXT 0X0C\n#define IXGBE_PACKET_TYPE_IPV6_EXT_TCP 0X1C\n#define IXGBE_PACKET_TYPE_IPV6_EXT_UDP 0X2C\n#define IXGBE_PACKET_TYPE_IPV4_IPV6 0X05\n#define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP 0X15\n#define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP 0X25\n#define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT 0X0D\n#define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D\n#define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D\n#define IXGBE_PACKET_TYPE_MAX 0X80\n#define IXGBE_PACKET_TYPE_MASK 0X7F\n#define IXGBE_PACKET_TYPE_SHIFT 0X04\nstatic inline uint32_t\nixgbe_rxd_pkt_info_to_pkt_type(uint16_t pkt_info)\n{\n\tstatic const uint32_t\n\t\tptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {\n\t\t[IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4,\n\t\t[IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4_EXT,\n\t\t[IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6,\n\t\t[IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6,\n\t\t[IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6_EXT,\n\t\t[IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT,\n\t\t[IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,\n\t\t[IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,\n\t\t[IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,\n\t\t[IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,\n\t\t[IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,\n\t\t[IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,\n\t\t[IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,\n\t\t[IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,\n\t\t[IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,\n\t\t[IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |\n\t\t\tRTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,\n\t\t[IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,\n\t\t[IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |\n\t\t\tRTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,\n\t};\n\tif (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))\n\t\treturn RTE_PTYPE_UNKNOWN;\n\n\tpkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) &\n\t\t\t\tIXGBE_PACKET_TYPE_MASK;\n\n\treturn ptype_table[pkt_info];\n}\n\nstatic inline uint64_t\nixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)\n{\n\tstatic uint64_t ip_rss_types_map[16] __rte_cache_aligned = {\n\t\t0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,\n\t\t0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,\n\t\tPKT_RX_RSS_HASH, 0, 0, 0,\n\t\t0, 0, 0, PKT_RX_FDIR,\n\t};\n#ifdef RTE_LIBRTE_IEEE1588\n\tstatic uint64_t ip_pkt_etqf_map[8] = {\n\t\t0, 0, 0, PKT_RX_IEEE1588_PTP,\n\t\t0, 0, 0, 0,\n\t};\n\n\tif (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))\n\t\treturn ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |\n\t\t\t\tip_rss_types_map[pkt_info & 0XF];\n\telse\n\t\treturn ip_rss_types_map[pkt_info & 0XF];\n#else\n\treturn ip_rss_types_map[pkt_info & 0XF];\n#endif\n}\n#else /* RTE_NEXT_ABI */\nstatic inline uint64_t\nrx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)\n{\n\tuint64_t pkt_flags;\n\n\tstatic const uint64_t ip_pkt_types_map[16] = {\n\t\t0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,\n\t\tPKT_RX_IPV6_HDR, 0, 0, 0,\n\t\tPKT_RX_IPV6_HDR_EXT, 0, 0, 0,\n\t\tPKT_RX_IPV6_HDR_EXT, 0, 0, 0,\n\t};\n\n\tstatic const uint64_t ip_rss_types_map[16] = {\n\t\t0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,\n\t\t0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,\n\t\tPKT_RX_RSS_HASH, 0, 0, 0,\n\t\t0, 0, 0, PKT_RX_FDIR,\n\t};\n\n#ifdef RTE_LIBRTE_IEEE1588\n\tstatic uint64_t ip_pkt_etqf_map[8] = {\n\t\t0, 0, 0, PKT_RX_IEEE1588_PTP,\n\t\t0, 0, 0, 0,\n\t};\n\n\tpkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?\n\t\t\tip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :\n\t\t\tip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];\n#else\n\tpkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :\n\t\t\tip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];\n\n#endif\n\treturn pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];\n}\n#endif /* RTE_NEXT_ABI */\n\nstatic inline uint64_t\nrx_desc_status_to_pkt_flags(uint32_t rx_status)\n{\n\tuint64_t pkt_flags;\n\n\t/*\n\t * Check if VLAN present only.\n\t * Do not check whether L3/L4 rx checksum done by NIC or not,\n\t * That can be found from rte_eth_rxmode.hw_ip_checksum flag\n\t */\n\tpkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;\n\n#ifdef RTE_LIBRTE_IEEE1588\n\tif (rx_status & IXGBE_RXD_STAT_TMST)\n\t\tpkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;\n#endif\n\treturn pkt_flags;\n}\n\nstatic inline uint64_t\nrx_desc_error_to_pkt_flags(uint32_t rx_status)\n{\n\t/*\n\t * Bit 31: IPE, IPv4 checksum error\n\t * Bit 30: L4I, L4I integrity error\n\t */\n\tstatic uint64_t error_to_pkt_flags_map[4] = {\n\t\t0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,\n\t\tPKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD\n\t};\n\treturn error_to_pkt_flags_map[(rx_status >>\n\t\tIXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];\n}\n\n/*\n * LOOK_AHEAD defines how many desc statuses to check beyond the\n * current descriptor.\n * It must be a pound define for optimal performance.\n * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring\n * function only works with LOOK_AHEAD=8.\n */\n#define LOOK_AHEAD 8\n#if (LOOK_AHEAD != 8)\n#error \"PMD IXGBE: LOOK_AHEAD must be 8\\n\"\n#endif\nstatic inline int\nixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)\n{\n\tvolatile union ixgbe_adv_rx_desc *rxdp;\n\tstruct ixgbe_rx_entry *rxep;\n\tstruct rte_mbuf *mb;\n\tuint16_t pkt_len;\n\tuint64_t pkt_flags;\n#ifdef RTE_NEXT_ABI\n\tint nb_dd;\n\tuint32_t s[LOOK_AHEAD];\n\tuint16_t pkt_info[LOOK_AHEAD];\n#else\n\tint s[LOOK_AHEAD], nb_dd;\n#endif /* RTE_NEXT_ABI */\n\tint i, j, nb_rx = 0;\n\tuint32_t status;\n\n\t/* get references to current descriptor and S/W ring entry */\n\trxdp = &rxq->rx_ring[rxq->rx_tail];\n\trxep = &rxq->sw_ring[rxq->rx_tail];\n\n\tstatus = rxdp->wb.upper.status_error;\n\t/* check to make sure there is at least 1 packet to receive */\n\tif (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))\n\t\treturn 0;\n\n\t/*\n\t * Scan LOOK_AHEAD descriptors at a time to determine which descriptors\n\t * reference packets that are ready to be received.\n\t */\n\tfor (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;\n\t i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)\n\t{\n\t\t/* Read desc statuses backwards to avoid race condition */\n\t\tfor (j = LOOK_AHEAD-1; j >= 0; --j)\n\t\t\ts[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);\n\n#ifdef RTE_NEXT_ABI\n\t\tfor (j = LOOK_AHEAD - 1; j >= 0; --j)\n\t\t\tpkt_info[j] = rxdp[j].wb.lower.lo_dword.\n\t\t\t\t\t\ths_rss.pkt_info;\n#endif /* RTE_NEXT_ABI */\n\n\t\t/* Compute how many status bits were set */\n\t\tnb_dd = 0;\n\t\tfor (j = 0; j < LOOK_AHEAD; ++j)\n\t\t\tnb_dd += s[j] & IXGBE_RXDADV_STAT_DD;\n\n\t\tnb_rx += nb_dd;\n\n\t\t/* Translate descriptor info to mbuf format */\n\t\tfor (j = 0; j < nb_dd; ++j) {\n\t\t\tmb = rxep[j].mbuf;\n\t\t\tpkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -\n\t\t\t\t rxq->crc_len;\n\t\t\tmb->data_len = pkt_len;\n\t\t\tmb->pkt_len = pkt_len;\n\t\t\tmb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);\n\n\t\t\t/* convert descriptor fields to rte mbuf flags */\n#ifdef RTE_NEXT_ABI\n\t\t\tpkt_flags = rx_desc_status_to_pkt_flags(s[j]);\n\t\t\tpkt_flags |= rx_desc_error_to_pkt_flags(s[j]);\n\t\t\tpkt_flags |=\n\t\t\t\tixgbe_rxd_pkt_info_to_pkt_flags(pkt_info[j]);\n\t\t\tmb->ol_flags = pkt_flags;\n\t\t\tmb->packet_type =\n\t\t\t\tixgbe_rxd_pkt_info_to_pkt_type(pkt_info[j]);\n#else /* RTE_NEXT_ABI */\n\t\t\tpkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(\n\t\t\t\t\trte_le_to_cpu_32(\n\t\t\t\t\trxdp[j].wb.lower.lo_dword.data));\n\t\t\t/* reuse status field from scan list */\n\t\t\tpkt_flags |= rx_desc_status_to_pkt_flags(s[j]);\n\t\t\tpkt_flags |= rx_desc_error_to_pkt_flags(s[j]);\n\t\t\tmb->ol_flags = pkt_flags;\n#endif /* RTE_NEXT_ABI */\n\n\t\t\tif (likely(pkt_flags & PKT_RX_RSS_HASH))\n\t\t\t\tmb->hash.rss = rte_le_to_cpu_32(\n\t\t\t\t rxdp[j].wb.lower.hi_dword.rss);\n\t\t\telse if (pkt_flags & PKT_RX_FDIR) {\n\t\t\t\tmb->hash.fdir.hash = rte_le_to_cpu_16(\n\t\t\t\t rxdp[j].wb.lower.hi_dword.csum_ip.csum) &\n\t\t\t\t IXGBE_ATR_HASH_MASK;\n\t\t\t\tmb->hash.fdir.id = rte_le_to_cpu_16(\n\t\t\t\t rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);\n\t\t\t}\n\t\t}\n\n\t\t/* Move mbuf pointers from the S/W ring to the stage */\n\t\tfor (j = 0; j < LOOK_AHEAD; ++j) {\n\t\t\trxq->rx_stage[i + j] = rxep[j].mbuf;\n\t\t}\n\n\t\t/* stop if all requested packets could not be received */\n\t\tif (nb_dd != LOOK_AHEAD)\n\t\t\tbreak;\n\t}\n\n\t/* clear software ring entries so we can cleanup correctly */\n\tfor (i = 0; i < nb_rx; ++i) {\n\t\trxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;\n\t}\n\n\n\treturn nb_rx;\n}\n\nstatic inline int\nixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)\n{\n\tvolatile union ixgbe_adv_rx_desc *rxdp;\n\tstruct ixgbe_rx_entry *rxep;\n\tstruct rte_mbuf *mb;\n\tuint16_t alloc_idx;\n\t__le64 dma_addr;\n\tint diag, i;\n\n\t/* allocate buffers in bulk directly into the S/W ring */\n\talloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);\n\trxep = &rxq->sw_ring[alloc_idx];\n\tdiag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,\n\t\t\t\t rxq->rx_free_thresh);\n\tif (unlikely(diag != 0))\n\t\treturn (-ENOMEM);\n\n\trxdp = &rxq->rx_ring[alloc_idx];\n\tfor (i = 0; i < rxq->rx_free_thresh; ++i) {\n\t\t/* populate the static rte mbuf fields */\n\t\tmb = rxep[i].mbuf;\n\t\tif (reset_mbuf) {\n\t\t\tmb->next = NULL;\n\t\t\tmb->nb_segs = 1;\n\t\t\tmb->port = rxq->port_id;\n\t\t}\n\n\t\trte_mbuf_refcnt_set(mb, 1);\n\t\tmb->data_off = RTE_PKTMBUF_HEADROOM;\n\n\t\t/* populate the descriptors */\n\t\tdma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));\n\t\trxdp[i].read.hdr_addr = 0;\n\t\trxdp[i].read.pkt_addr = dma_addr;\n\t}\n\n\t/* update state of internal queue structure */\n\trxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;\n\tif (rxq->rx_free_trigger >= rxq->nb_rx_desc)\n\t\trxq->rx_free_trigger = rxq->rx_free_thresh - 1;\n\n\t/* no errors */\n\treturn 0;\n}\n\nstatic inline uint16_t\nixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n\t\t\t uint16_t nb_pkts)\n{\n\tstruct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];\n\tint i;\n\n\t/* how many packets are ready to return? */\n\tnb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);\n\n\t/* copy mbuf pointers to the application's packet list */\n\tfor (i = 0; i < nb_pkts; ++i)\n\t\trx_pkts[i] = stage[i];\n\n\t/* update internal queue state */\n\trxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);\n\trxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);\n\n\treturn nb_pkts;\n}\n\nstatic inline uint16_t\nrx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t uint16_t nb_pkts)\n{\n\tstruct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;\n\tuint16_t nb_rx = 0;\n\n\t/* Any previously recv'd pkts will be returned from the Rx stage */\n\tif (rxq->rx_nb_avail)\n\t\treturn ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);\n\n\t/* Scan the H/W ring for packets to receive */\n\tnb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);\n\n\t/* update internal queue state */\n\trxq->rx_next_avail = 0;\n\trxq->rx_nb_avail = nb_rx;\n\trxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);\n\n\t/* if required, allocate new buffers to replenish descriptors */\n\tif (rxq->rx_tail > rxq->rx_free_trigger) {\n\t\tuint16_t cur_free_trigger = rxq->rx_free_trigger;\n\n\t\tif (ixgbe_rx_alloc_bufs(rxq, true) != 0) {\n\t\t\tint i, j;\n\t\t\tPMD_RX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u \"\n\t\t\t\t \"queue_id=%u\", (unsigned) rxq->port_id,\n\t\t\t\t (unsigned) rxq->queue_id);\n\n\t\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=\n\t\t\t\trxq->rx_free_thresh;\n\n\t\t\t/*\n\t\t\t * Need to rewind any previous receives if we cannot\n\t\t\t * allocate new buffers to replenish the old ones.\n\t\t\t */\n\t\t\trxq->rx_nb_avail = 0;\n\t\t\trxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);\n\t\t\tfor (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)\n\t\t\t\trxq->sw_ring[j].mbuf = rxq->rx_stage[i];\n\n\t\t\treturn 0;\n\t\t}\n\n\t\t/* update tail pointer */\n\t\trte_wmb();\n\t\tIXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, cur_free_trigger);\n\t}\n\n\tif (rxq->rx_tail >= rxq->nb_rx_desc)\n\t\trxq->rx_tail = 0;\n\n\t/* received any packets this loop? */\n\tif (rxq->rx_nb_avail)\n\t\treturn ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);\n\n\treturn 0;\n}\n\n/* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */\nstatic uint16_t\nixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\t\t uint16_t nb_pkts)\n{\n\tuint16_t nb_rx;\n\n\tif (unlikely(nb_pkts == 0))\n\t\treturn 0;\n\n\tif (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))\n\t\treturn rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);\n\n\t/* request is relatively large, chunk it up */\n\tnb_rx = 0;\n\twhile (nb_pkts) {\n\t\tuint16_t ret, n;\n\t\tn = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);\n\t\tret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);\n\t\tnb_rx = (uint16_t)(nb_rx + ret);\n\t\tnb_pkts = (uint16_t)(nb_pkts - ret);\n\t\tif (ret < n)\n\t\t\tbreak;\n\t}\n\n\treturn nb_rx;\n}\n\nuint16_t\nixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts)\n{\n\tstruct ixgbe_rx_queue *rxq;\n\tvolatile union ixgbe_adv_rx_desc *rx_ring;\n\tvolatile union ixgbe_adv_rx_desc *rxdp;\n\tstruct ixgbe_rx_entry *sw_ring;\n\tstruct ixgbe_rx_entry *rxe;\n\tstruct rte_mbuf *rxm;\n\tstruct rte_mbuf *nmb;\n\tunion ixgbe_adv_rx_desc rxd;\n\tuint64_t dma_addr;\n\tuint32_t staterr;\n#ifdef RTE_NEXT_ABI\n\tuint32_t pkt_info;\n#else\n\tuint32_t hlen_type_rss;\n#endif\n\tuint16_t pkt_len;\n\tuint16_t rx_id;\n\tuint16_t nb_rx;\n\tuint16_t nb_hold;\n\tuint64_t pkt_flags;\n\n\tnb_rx = 0;\n\tnb_hold = 0;\n\trxq = rx_queue;\n\trx_id = rxq->rx_tail;\n\trx_ring = rxq->rx_ring;\n\tsw_ring = rxq->sw_ring;\n\twhile (nb_rx < nb_pkts) {\n\t\t/*\n\t\t * The order of operations here is important as the DD status\n\t\t * bit must not be read after any other descriptor fields.\n\t\t * rx_ring and rxdp are pointing to volatile data so the order\n\t\t * of accesses cannot be reordered by the compiler. If they were\n\t\t * not volatile, they could be reordered which could lead to\n\t\t * using invalid descriptor fields when read from rxd.\n\t\t */\n\t\trxdp = &rx_ring[rx_id];\n\t\tstaterr = rxdp->wb.upper.status_error;\n\t\tif (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))\n\t\t\tbreak;\n\t\trxd = *rxdp;\n\n\t\t/*\n\t\t * End of packet.\n\t\t *\n\t\t * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet\n\t\t * is likely to be invalid and to be dropped by the various\n\t\t * validation checks performed by the network stack.\n\t\t *\n\t\t * Allocate a new mbuf to replenish the RX ring descriptor.\n\t\t * If the allocation fails:\n\t\t * - arrange for that RX descriptor to be the first one\n\t\t * being parsed the next time the receive function is\n\t\t * invoked [on the same queue].\n\t\t *\n\t\t * - Stop parsing the RX ring and return immediately.\n\t\t *\n\t\t * This policy do not drop the packet received in the RX\n\t\t * descriptor for which the allocation of a new mbuf failed.\n\t\t * Thus, it allows that packet to be later retrieved if\n\t\t * mbuf have been freed in the mean time.\n\t\t * As a side effect, holding RX descriptors instead of\n\t\t * systematically giving them back to the NIC may lead to\n\t\t * RX ring exhaustion situations.\n\t\t * However, the NIC can gracefully prevent such situations\n\t\t * to happen by sending specific \"back-pressure\" flow control\n\t\t * frames to its peer(s).\n\t\t */\n\t\tPMD_RX_LOG(DEBUG, \"port_id=%u queue_id=%u rx_id=%u \"\n\t\t\t \"ext_err_stat=0x%08x pkt_len=%u\",\n\t\t\t (unsigned) rxq->port_id, (unsigned) rxq->queue_id,\n\t\t\t (unsigned) rx_id, (unsigned) staterr,\n\t\t\t (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));\n\n\t\tnmb = rte_rxmbuf_alloc(rxq->mb_pool);\n\t\tif (nmb == NULL) {\n\t\t\tPMD_RX_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u \"\n\t\t\t\t \"queue_id=%u\", (unsigned) rxq->port_id,\n\t\t\t\t (unsigned) rxq->queue_id);\n\t\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;\n\t\t\tbreak;\n\t\t}\n\n\t\tnb_hold++;\n\t\trxe = &sw_ring[rx_id];\n\t\trx_id++;\n\t\tif (rx_id == rxq->nb_rx_desc)\n\t\t\trx_id = 0;\n\n\t\t/* Prefetch next mbuf while processing current one. */\n\t\trte_ixgbe_prefetch(sw_ring[rx_id].mbuf);\n\n\t\t/*\n\t\t * When next RX descriptor is on a cache-line boundary,\n\t\t * prefetch the next 4 RX descriptors and the next 8 pointers\n\t\t * to mbufs.\n\t\t */\n\t\tif ((rx_id & 0x3) == 0) {\n\t\t\trte_ixgbe_prefetch(&rx_ring[rx_id]);\n\t\t\trte_ixgbe_prefetch(&sw_ring[rx_id]);\n\t\t}\n\n\t\trxm = rxe->mbuf;\n\t\trxe->mbuf = nmb;\n\t\tdma_addr =\n\t\t\trte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));\n\t\trxdp->read.hdr_addr = 0;\n\t\trxdp->read.pkt_addr = dma_addr;\n\n\t\t/*\n\t\t * Initialize the returned mbuf.\n\t\t * 1) setup generic mbuf fields:\n\t\t * - number of segments,\n\t\t * - next segment,\n\t\t * - packet length,\n\t\t * - RX port identifier.\n\t\t * 2) integrate hardware offload data, if any:\n\t\t * - RSS flag & hash,\n\t\t * - IP checksum flag,\n\t\t * - VLAN TCI, if any,\n\t\t * - error flags.\n\t\t */\n\t\tpkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -\n\t\t\t\t rxq->crc_len);\n\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n\t\trte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);\n\t\trxm->nb_segs = 1;\n\t\trxm->next = NULL;\n\t\trxm->pkt_len = pkt_len;\n\t\trxm->data_len = pkt_len;\n\t\trxm->port = rxq->port_id;\n\n#ifdef RTE_NEXT_ABI\n\t\tpkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.hs_rss.\n\t\t\t\t\t\t\t\tpkt_info);\n\t\t/* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */\n\t\trxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);\n\n\t\tpkt_flags = rx_desc_status_to_pkt_flags(staterr);\n\t\tpkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);\n\t\tpkt_flags = pkt_flags |\n\t\t\tixgbe_rxd_pkt_info_to_pkt_flags(pkt_info);\n\t\trxm->ol_flags = pkt_flags;\n\t\trxm->packet_type = ixgbe_rxd_pkt_info_to_pkt_type(pkt_info);\n#else /* RTE_NEXT_ABI */\n\t\thlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);\n\t\t/* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */\n\t\trxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);\n\n\t\tpkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);\n\t\tpkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);\n\t\tpkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);\n\t\trxm->ol_flags = pkt_flags;\n#endif /* RTE_NEXT_ABI */\n\n\t\tif (likely(pkt_flags & PKT_RX_RSS_HASH))\n\t\t\trxm->hash.rss = rte_le_to_cpu_32(\n\t\t\t\t\t\trxd.wb.lower.hi_dword.rss);\n\t\telse if (pkt_flags & PKT_RX_FDIR) {\n\t\t\trxm->hash.fdir.hash = rte_le_to_cpu_16(\n\t\t\t\t\trxd.wb.lower.hi_dword.csum_ip.csum) &\n\t\t\t\t\tIXGBE_ATR_HASH_MASK;\n\t\t\trxm->hash.fdir.id = rte_le_to_cpu_16(\n\t\t\t\t\trxd.wb.lower.hi_dword.csum_ip.ip_id);\n\t\t}\n\t\t/*\n\t\t * Store the mbuf address into the next entry of the array\n\t\t * of returned packets.\n\t\t */\n\t\trx_pkts[nb_rx++] = rxm;\n\t}\n\trxq->rx_tail = rx_id;\n\n\t/*\n\t * If the number of free RX descriptors is greater than the RX free\n\t * threshold of the queue, advance the Receive Descriptor Tail (RDT)\n\t * register.\n\t * Update the RDT with the value of the last processed RX descriptor\n\t * minus 1, to guarantee that the RDT register is never equal to the\n\t * RDH register, which creates a \"full\" ring situtation from the\n\t * hardware point of view...\n\t */\n\tnb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);\n\tif (nb_hold > rxq->rx_free_thresh) {\n\t\tPMD_RX_LOG(DEBUG, \"port_id=%u queue_id=%u rx_tail=%u \"\n\t\t\t \"nb_hold=%u nb_rx=%u\",\n\t\t\t (unsigned) rxq->port_id, (unsigned) rxq->queue_id,\n\t\t\t (unsigned) rx_id, (unsigned) nb_hold,\n\t\t\t (unsigned) nb_rx);\n\t\trx_id = (uint16_t) ((rx_id == 0) ?\n\t\t\t\t (rxq->nb_rx_desc - 1) : (rx_id - 1));\n\t\tIXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);\n\t\tnb_hold = 0;\n\t}\n\trxq->nb_rx_hold = nb_hold;\n\treturn (nb_rx);\n}\n\n/**\n * Detect an RSC descriptor.\n */\nstatic inline uint32_t\nixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)\n{\n\treturn (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &\n\t\tIXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;\n}\n\n/**\n * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet\n *\n * Fill the following info in the HEAD buffer of the Rx cluster:\n * - RX port identifier\n * - hardware offload data, if any:\n * - RSS flag & hash\n * - IP checksum flag\n * - VLAN TCI, if any\n * - error flags\n * @head HEAD of the packet cluster\n * @desc HW descriptor to get data from\n * @port_id Port ID of the Rx queue\n */\nstatic inline void\nixgbe_fill_cluster_head_buf(\n\tstruct rte_mbuf *head,\n\tunion ixgbe_adv_rx_desc *desc,\n\tuint8_t port_id,\n\tuint32_t staterr)\n{\n#ifdef RTE_NEXT_ABI\n\tuint16_t pkt_info;\n\tuint64_t pkt_flags;\n\n\thead->port = port_id;\n\n\t/* The vlan_tci field is only valid when PKT_RX_VLAN_PKT is\n\t * set in the pkt_flags field.\n\t */\n\thead->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);\n\tpkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.hs_rss.pkt_info);\n\tpkt_flags = rx_desc_status_to_pkt_flags(staterr);\n\tpkt_flags |= rx_desc_error_to_pkt_flags(staterr);\n\tpkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info);\n\thead->ol_flags = pkt_flags;\n\thead->packet_type = ixgbe_rxd_pkt_info_to_pkt_type(pkt_info);\n#else /* RTE_NEXT_ABI */\n\tuint32_t hlen_type_rss;\n\tuint64_t pkt_flags;\n\n\thead->port = port_id;\n\n\t/*\n\t * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is\n\t * set in the pkt_flags field.\n\t */\n\thead->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);\n\thlen_type_rss = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);\n\tpkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);\n\tpkt_flags |= rx_desc_status_to_pkt_flags(staterr);\n\tpkt_flags |= rx_desc_error_to_pkt_flags(staterr);\n\thead->ol_flags = pkt_flags;\n#endif /* RTE_NEXT_ABI */\n\n\tif (likely(pkt_flags & PKT_RX_RSS_HASH))\n\t\thead->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);\n\telse if (pkt_flags & PKT_RX_FDIR) {\n\t\thead->hash.fdir.hash =\n\t\t\trte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)\n\t\t\t\t\t\t\t & IXGBE_ATR_HASH_MASK;\n\t\thead->hash.fdir.id =\n\t\t\trte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);\n\t}\n}\n\n/**\n * ixgbe_recv_pkts_lro - receive handler for and LRO case.\n *\n * @rx_queue Rx queue handle\n * @rx_pkts table of received packets\n * @nb_pkts size of rx_pkts table\n * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling\n *\n * Handles the Rx HW ring completions when RSC feature is configured. Uses an\n * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.\n *\n * We use the same logic as in Linux and in FreeBSD ixgbe drivers:\n * 1) When non-EOP RSC completion arrives:\n * a) Update the HEAD of the current RSC aggregation cluster with the new\n * segment's data length.\n * b) Set the \"next\" pointer of the current segment to point to the segment\n * at the NEXTP index.\n * c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry\n * in the sw_rsc_ring.\n * 2) When EOP arrives we just update the cluster's total length and offload\n * flags and deliver the cluster up to the upper layers. In our case - put it\n * in the rx_pkts table.\n *\n * Returns the number of received packets/clusters (according to the \"bulk\n * receive\" interface).\n */\nstatic inline uint16_t\nixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,\n\t\t bool bulk_alloc)\n{\n\tstruct ixgbe_rx_queue *rxq = rx_queue;\n\tvolatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;\n\tstruct ixgbe_rx_entry *sw_ring = rxq->sw_ring;\n\tstruct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;\n\tuint16_t rx_id = rxq->rx_tail;\n\tuint16_t nb_rx = 0;\n\tuint16_t nb_hold = rxq->nb_rx_hold;\n\tuint16_t prev_id = rxq->rx_tail;\n\n\twhile (nb_rx < nb_pkts) {\n\t\tbool eop;\n\t\tstruct ixgbe_rx_entry *rxe;\n\t\tstruct ixgbe_scattered_rx_entry *sc_entry;\n\t\tstruct ixgbe_scattered_rx_entry *next_sc_entry;\n\t\tstruct ixgbe_rx_entry *next_rxe;\n\t\tstruct rte_mbuf *first_seg;\n\t\tstruct rte_mbuf *rxm;\n\t\tstruct rte_mbuf *nmb;\n\t\tunion ixgbe_adv_rx_desc rxd;\n\t\tuint16_t data_len;\n\t\tuint16_t next_id;\n\t\tvolatile union ixgbe_adv_rx_desc *rxdp;\n\t\tuint32_t staterr;\n\nnext_desc:\n\t\t/*\n\t\t * The code in this whole file uses the volatile pointer to\n\t\t * ensure the read ordering of the status and the rest of the\n\t\t * descriptor fields (on the compiler level only!!!). This is so\n\t\t * UGLY - why not to just use the compiler barrier instead? DPDK\n\t\t * even has the rte_compiler_barrier() for that.\n\t\t *\n\t\t * But most importantly this is just wrong because this doesn't\n\t\t * ensure memory ordering in a general case at all. For\n\t\t * instance, DPDK is supposed to work on Power CPUs where\n\t\t * compiler barrier may just not be enough!\n\t\t *\n\t\t * I tried to write only this function properly to have a\n\t\t * starting point (as a part of an LRO/RSC series) but the\n\t\t * compiler cursed at me when I tried to cast away the\n\t\t * \"volatile\" from rx_ring (yes, it's volatile too!!!). So, I'm\n\t\t * keeping it the way it is for now.\n\t\t *\n\t\t * The code in this file is broken in so many other places and\n\t\t * will just not work on a big endian CPU anyway therefore the\n\t\t * lines below will have to be revisited together with the rest\n\t\t * of the ixgbe PMD.\n\t\t *\n\t\t * TODO:\n\t\t * - Get rid of \"volatile\" crap and let the compiler do its\n\t\t * job.\n\t\t * - Use the proper memory barrier (rte_rmb()) to ensure the\n\t\t * memory ordering below.\n\t\t */\n\t\trxdp = &rx_ring[rx_id];\n\t\tstaterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);\n\n\t\tif (!(staterr & IXGBE_RXDADV_STAT_DD))\n\t\t\tbreak;\n\n\t\trxd = *rxdp;\n\n\t\tPMD_RX_LOG(DEBUG, \"port_id=%u queue_id=%u rx_id=%u \"\n\t\t\t\t \"staterr=0x%x data_len=%u\",\n\t\t\t rxq->port_id, rxq->queue_id, rx_id, staterr,\n\t\t\t rte_le_to_cpu_16(rxd.wb.upper.length));\n\n\t\tif (!bulk_alloc) {\n\t\t\tnmb = rte_rxmbuf_alloc(rxq->mb_pool);\n\t\t\tif (nmb == NULL) {\n\t\t\t\tPMD_RX_LOG(DEBUG, \"RX mbuf alloc failed \"\n\t\t\t\t\t\t \"port_id=%u queue_id=%u\",\n\t\t\t\t\t rxq->port_id, rxq->queue_id);\n\n\t\t\t\trte_eth_devices[rxq->port_id].data->\n\t\t\t\t\t\t\trx_mbuf_alloc_failed++;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\telse if (nb_hold > rxq->rx_free_thresh) {\n\t\t\tuint16_t next_rdt = rxq->rx_free_trigger;\n\n\t\t\tif (!ixgbe_rx_alloc_bufs(rxq, false)) {\n\t\t\t\trte_wmb();\n\t\t\t\tIXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr,\n\t\t\t\t\t\t next_rdt);\n\t\t\t\tnb_hold -= rxq->rx_free_thresh;\n\t\t\t} else {\n\t\t\t\tPMD_RX_LOG(DEBUG, \"RX bulk alloc failed \"\n\t\t\t\t\t\t \"port_id=%u queue_id=%u\",\n\t\t\t\t\t rxq->port_id, rxq->queue_id);\n\n\t\t\t\trte_eth_devices[rxq->port_id].data->\n\t\t\t\t\t\t\trx_mbuf_alloc_failed++;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tnb_hold++;\n\t\trxe = &sw_ring[rx_id];\n\t\teop = staterr & IXGBE_RXDADV_STAT_EOP;\n\n\t\tnext_id = rx_id + 1;\n\t\tif (next_id == rxq->nb_rx_desc)\n\t\t\tnext_id = 0;\n\n\t\t/* Prefetch next mbuf while processing current one. */\n\t\trte_ixgbe_prefetch(sw_ring[next_id].mbuf);\n\n\t\t/*\n\t\t * When next RX descriptor is on a cache-line boundary,\n\t\t * prefetch the next 4 RX descriptors and the next 4 pointers\n\t\t * to mbufs.\n\t\t */\n\t\tif ((next_id & 0x3) == 0) {\n\t\t\trte_ixgbe_prefetch(&rx_ring[next_id]);\n\t\t\trte_ixgbe_prefetch(&sw_ring[next_id]);\n\t\t}\n\n\t\trxm = rxe->mbuf;\n\n\t\tif (!bulk_alloc) {\n\t\t\t__le64 dma =\n\t\t\t rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));\n\t\t\t/*\n\t\t\t * Update RX descriptor with the physical address of the\n\t\t\t * new data buffer of the new allocated mbuf.\n\t\t\t */\n\t\t\trxe->mbuf = nmb;\n\n\t\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n\t\t\trxdp->read.hdr_addr = 0;\n\t\t\trxdp->read.pkt_addr = dma;\n\t\t} else\n\t\t\trxe->mbuf = NULL;\n\n\t\t/*\n\t\t * Set data length & data buffer address of mbuf.\n\t\t */\n\t\tdata_len = rte_le_to_cpu_16(rxd.wb.upper.length);\n\t\trxm->data_len = data_len;\n\n\t\tif (!eop) {\n\t\t\tuint16_t nextp_id;\n\t\t\t/*\n\t\t\t * Get next descriptor index:\n\t\t\t * - For RSC it's in the NEXTP field.\n\t\t\t * - For a scattered packet - it's just a following\n\t\t\t * descriptor.\n\t\t\t */\n\t\t\tif (ixgbe_rsc_count(&rxd))\n\t\t\t\tnextp_id =\n\t\t\t\t\t(staterr & IXGBE_RXDADV_NEXTP_MASK) >>\n\t\t\t\t\t\t IXGBE_RXDADV_NEXTP_SHIFT;\n\t\t\telse\n\t\t\t\tnextp_id = next_id;\n\n\t\t\tnext_sc_entry = &sw_sc_ring[nextp_id];\n\t\t\tnext_rxe = &sw_ring[nextp_id];\n\t\t\trte_ixgbe_prefetch(next_rxe);\n\t\t}\n\n\t\tsc_entry = &sw_sc_ring[rx_id];\n\t\tfirst_seg = sc_entry->fbuf;\n\t\tsc_entry->fbuf = NULL;\n\n\t\t/*\n\t\t * If this is the first buffer of the received packet,\n\t\t * set the pointer to the first mbuf of the packet and\n\t\t * initialize its context.\n\t\t * Otherwise, update the total length and the number of segments\n\t\t * of the current scattered packet, and update the pointer to\n\t\t * the last mbuf of the current packet.\n\t\t */\n\t\tif (first_seg == NULL) {\n\t\t\tfirst_seg = rxm;\n\t\t\tfirst_seg->pkt_len = data_len;\n\t\t\tfirst_seg->nb_segs = 1;\n\t\t} else {\n\t\t\tfirst_seg->pkt_len += data_len;\n\t\t\tfirst_seg->nb_segs++;\n\t\t}\n\n\t\tprev_id = rx_id;\n\t\trx_id = next_id;\n\n\t\t/*\n\t\t * If this is not the last buffer of the received packet, update\n\t\t * the pointer to the first mbuf at the NEXTP entry in the\n\t\t * sw_sc_ring and continue to parse the RX ring.\n\t\t */\n\t\tif (!eop) {\n\t\t\trxm->next = next_rxe->mbuf;\n\t\t\tnext_sc_entry->fbuf = first_seg;\n\t\t\tgoto next_desc;\n\t\t}\n\n\t\t/*\n\t\t * This is the last buffer of the received packet - return\n\t\t * the current cluster to the user.\n\t\t */\n\t\trxm->next = NULL;\n\n\t\t/* Initialize the first mbuf of the returned packet */\n\t\tixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq->port_id,\n\t\t\t\t\t staterr);\n\n\t\t/*\n\t\t * Deal with the case, when HW CRC srip is disabled.\n\t\t * That can't happen when LRO is enabled, but still could\n\t\t * happen for scattered RX mode.\n\t\t */\n\t\tfirst_seg->pkt_len -= rxq->crc_len;\n\t\tif (unlikely(rxm->data_len <= rxq->crc_len)) {\n\t\t\tstruct rte_mbuf *lp;\n\n\t\t\tfor (lp = first_seg; lp->next != rxm; lp = lp->next)\n\t\t\t\t;\n\n\t\t\tfirst_seg->nb_segs--;\n\t\t\tlp->data_len -= rxq->crc_len - rxm->data_len;\n\t\t\tlp->next = NULL;\n\t\t\trte_pktmbuf_free_seg(rxm);\n\t\t} else\n\t\t\trxm->data_len -= rxq->crc_len;\n\n\t\t/* Prefetch data of first segment, if configured to do so. */\n\t\trte_packet_prefetch((char *)first_seg->buf_addr +\n\t\t\tfirst_seg->data_off);\n\n\t\t/*\n\t\t * Store the mbuf address into the next entry of the array\n\t\t * of returned packets.\n\t\t */\n\t\trx_pkts[nb_rx++] = first_seg;\n\t}\n\n\t/*\n\t * Record index of the next RX descriptor to probe.\n\t */\n\trxq->rx_tail = rx_id;\n\n\t/*\n\t * If the number of free RX descriptors is greater than the RX free\n\t * threshold of the queue, advance the Receive Descriptor Tail (RDT)\n\t * register.\n\t * Update the RDT with the value of the last processed RX descriptor\n\t * minus 1, to guarantee that the RDT register is never equal to the\n\t * RDH register, which creates a \"full\" ring situtation from the\n\t * hardware point of view...\n\t */\n\tif (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {\n\t\tPMD_RX_LOG(DEBUG, \"port_id=%u queue_id=%u rx_tail=%u \"\n\t\t\t \"nb_hold=%u nb_rx=%u\",\n\t\t\t rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);\n\n\t\trte_wmb();\n\t\tIXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, prev_id);\n\t\tnb_hold = 0;\n\t}\n\n\trxq->nb_rx_hold = nb_hold;\n\treturn nb_rx;\n}\n\nuint16_t\nixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\t\t\t uint16_t nb_pkts)\n{\n\treturn ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);\n}\n\nuint16_t\nixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\t\t uint16_t nb_pkts)\n{\n\treturn ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);\n}\n\n/*********************************************************************\n *\n * Queue management functions\n *\n **********************************************************************/\n\n/*\n * Rings setup and release.\n *\n * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be\n * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will\n * also optimize cache line size effect. H/W supports up to cache line size 128.\n */\n#define IXGBE_ALIGN 128\n\n/*\n * Maximum number of Ring Descriptors.\n *\n * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring\n * descriptors should meet the following condition:\n * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0\n */\n#define IXGBE_MIN_RING_DESC 32\n#define IXGBE_MAX_RING_DESC 4096\n\n/*\n * Create memzone for HW rings. malloc can't be used as the physical address is\n * needed. If the memzone is already created, then this function returns a ptr\n * to the old one.\n */\nstatic const struct rte_memzone * __attribute__((cold))\nring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,\n\t\t uint16_t queue_id, uint32_t ring_size, int socket_id)\n{\n\tchar z_name[RTE_MEMZONE_NAMESIZE];\n\tconst struct rte_memzone *mz;\n\n\tsnprintf(z_name, sizeof(z_name), \"%s_%s_%d_%d\",\n\t\t\tdev->driver->pci_drv.name, ring_name,\n\t\t\tdev->data->port_id, queue_id);\n\n\tmz = rte_memzone_lookup(z_name);\n\tif (mz)\n\t\treturn mz;\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n\treturn rte_memzone_reserve_bounded(z_name, ring_size,\n\t\tsocket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);\n#else\n\treturn rte_memzone_reserve_aligned(z_name, ring_size,\n\t\tsocket_id, 0, IXGBE_ALIGN);\n#endif\n}\n\nstatic void __attribute__((cold))\nixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)\n{\n\tunsigned i;\n\n\tif (txq->sw_ring != NULL) {\n\t\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n\t\t\tif (txq->sw_ring[i].mbuf != NULL) {\n\t\t\t\trte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);\n\t\t\t\ttxq->sw_ring[i].mbuf = NULL;\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void __attribute__((cold))\nixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)\n{\n\tif (txq != NULL &&\n\t txq->sw_ring != NULL)\n\t\trte_free(txq->sw_ring);\n}\n\nstatic void __attribute__((cold))\nixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)\n{\n\tif (txq != NULL && txq->ops != NULL) {\n\t\ttxq->ops->release_mbufs(txq);\n\t\ttxq->ops->free_swring(txq);\n\t\trte_free(txq);\n\t}\n}\n\nvoid __attribute__((cold))\nixgbe_dev_tx_queue_release(void *txq)\n{\n\tixgbe_tx_queue_release(txq);\n}\n\n/* (Re)set dynamic ixgbe_tx_queue fields to defaults */\nstatic void __attribute__((cold))\nixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)\n{\n\tstatic const union ixgbe_adv_tx_desc zeroed_desc = {{0}};\n\tstruct ixgbe_tx_entry *txe = txq->sw_ring;\n\tuint16_t prev, i;\n\n\t/* Zero out HW ring memory */\n\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n\t\ttxq->tx_ring[i] = zeroed_desc;\n\t}\n\n\t/* Initialize SW ring entries */\n\tprev = (uint16_t) (txq->nb_tx_desc - 1);\n\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n\t\tvolatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];\n\t\ttxd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);\n\t\ttxe[i].mbuf = NULL;\n\t\ttxe[i].last_id = i;\n\t\ttxe[prev].next_id = i;\n\t\tprev = i;\n\t}\n\n\ttxq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);\n\ttxq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);\n\n\ttxq->tx_tail = 0;\n\ttxq->nb_tx_used = 0;\n\t/*\n\t * Always allow 1 descriptor to be un-allocated to avoid\n\t * a H/W race condition\n\t */\n\ttxq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);\n\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);\n\ttxq->ctx_curr = 0;\n\tmemset((void*)&txq->ctx_cache, 0,\n\t\tIXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));\n}\n\nstatic const struct ixgbe_txq_ops def_txq_ops = {\n\t.release_mbufs = ixgbe_tx_queue_release_mbufs,\n\t.free_swring = ixgbe_tx_free_swring,\n\t.reset = ixgbe_reset_tx_queue,\n};\n\n/* Takes an ethdev and a queue and sets up the tx function to be used based on\n * the queue parameters. Used in tx_queue_setup by primary process and then\n * in dev_init by secondary process when attaching to an existing ethdev.\n */\nvoid __attribute__((cold))\nixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)\n{\n\t/* Use a simple Tx queue (no offloads, no multi segs) if possible */\n\tif (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)\n\t\t\t&& (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {\n\t\tPMD_INIT_LOG(DEBUG, \"Using simple tx code path\");\n#ifdef RTE_IXGBE_INC_VECTOR\n\t\tif (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&\n\t\t\t\t(rte_eal_process_type() != RTE_PROC_PRIMARY ||\n\t\t\t\t\tixgbe_txq_vec_setup(txq) == 0)) {\n\t\t\tPMD_INIT_LOG(DEBUG, \"Vector tx enabled.\");\n\t\t\tdev->tx_pkt_burst = ixgbe_xmit_pkts_vec;\n\t\t} else\n#endif\n\t\tdev->tx_pkt_burst = ixgbe_xmit_pkts_simple;\n\t} else {\n\t\tPMD_INIT_LOG(DEBUG, \"Using full-featured tx code path\");\n\t\tPMD_INIT_LOG(DEBUG,\n\t\t\t\t\" - txq_flags = %lx \" \"[IXGBE_SIMPLE_FLAGS=%lx]\",\n\t\t\t\t(unsigned long)txq->txq_flags,\n\t\t\t\t(unsigned long)IXGBE_SIMPLE_FLAGS);\n\t\tPMD_INIT_LOG(DEBUG,\n\t\t\t\t\" - tx_rs_thresh = %lu \" \"[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]\",\n\t\t\t\t(unsigned long)txq->tx_rs_thresh,\n\t\t\t\t(unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);\n\t\tdev->tx_pkt_burst = ixgbe_xmit_pkts;\n\t}\n}\n\nint __attribute__((cold))\nixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,\n\t\t\t uint16_t queue_idx,\n\t\t\t uint16_t nb_desc,\n\t\t\t unsigned int socket_id,\n\t\t\t const struct rte_eth_txconf *tx_conf)\n{\n\tconst struct rte_memzone *tz;\n\tstruct ixgbe_tx_queue *txq;\n\tstruct ixgbe_hw *hw;\n\tuint16_t tx_rs_thresh, tx_free_thresh;\n\tbool rs_deferring_allowed;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/*\n\t * According to 82599 and x540 specifications RS bit *must* be set on the\n\t * last descriptor of *every* packet. Therefore we will not allow the\n\t * tx_rs_thresh above 1 for all NICs newer than 82598.\n\t */\n\trs_deferring_allowed = (hw->mac.type <= ixgbe_mac_82598EB);\n\n\t/*\n\t * Validate number of transmit descriptors.\n\t * It must not exceed hardware maximum, and must be multiple\n\t * of IXGBE_ALIGN.\n\t */\n\tif (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||\n\t (nb_desc > IXGBE_MAX_RING_DESC) ||\n\t (nb_desc < IXGBE_MIN_RING_DESC)) {\n\t\treturn -EINVAL;\n\t}\n\n\t/*\n\t * The following two parameters control the setting of the RS bit on\n\t * transmit descriptors.\n\t * TX descriptors will have their RS bit set after txq->tx_rs_thresh\n\t * descriptors have been used.\n\t * The TX descriptor ring will be cleaned after txq->tx_free_thresh\n\t * descriptors are used or if the number of descriptors required\n\t * to transmit a packet is greater than the number of free TX\n\t * descriptors.\n\t * The following constraints must be satisfied:\n\t * tx_rs_thresh must be less than 2 for NICs for which RS deferring is\n\t * forbidden (all but 82598).\n\t * tx_rs_thresh must be greater than 0.\n\t * tx_rs_thresh must be less than the size of the ring minus 2.\n\t * tx_rs_thresh must be less than or equal to tx_free_thresh.\n\t * tx_rs_thresh must be a divisor of the ring size.\n\t * tx_free_thresh must be greater than 0.\n\t * tx_free_thresh must be less than the size of the ring minus 3.\n\t * One descriptor in the TX ring is used as a sentinel to avoid a\n\t * H/W race condition, hence the maximum threshold constraints.\n\t * When set to zero use default values.\n\t */\n\ttx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?\n\t\t\ttx_conf->tx_rs_thresh :\n\t\t\t(rs_deferring_allowed ? DEFAULT_TX_RS_THRESH : 1));\n\ttx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?\n\t\t\ttx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);\n\n\tif (!rs_deferring_allowed && tx_rs_thresh > 1) {\n\t\tPMD_INIT_LOG(ERR, \"tx_rs_thresh must be less than 2 since RS \"\n\t\t\t\t \"must be set for every packet for this HW. \"\n\t\t\t\t \"(tx_rs_thresh=%u port=%d queue=%d)\",\n\t\t\t (unsigned int)tx_rs_thresh,\n\t\t\t (int)dev->data->port_id, (int)queue_idx);\n\t\treturn -(EINVAL);\n\t}\n\n\tif (tx_rs_thresh >= (nb_desc - 2)) {\n\t\tPMD_INIT_LOG(ERR, \"tx_rs_thresh must be less than the number \"\n\t\t\t \"of TX descriptors minus 2. (tx_rs_thresh=%u \"\n\t\t\t \"port=%d queue=%d)\", (unsigned int)tx_rs_thresh,\n\t\t\t (int)dev->data->port_id, (int)queue_idx);\n\t\treturn -(EINVAL);\n\t}\n\tif (tx_free_thresh >= (nb_desc - 3)) {\n\t\tPMD_INIT_LOG(ERR, \"tx_rs_thresh must be less than the \"\n\t\t\t \"tx_free_thresh must be less than the number of \"\n\t\t\t \"TX descriptors minus 3. (tx_free_thresh=%u \"\n\t\t\t \"port=%d queue=%d)\",\n\t\t\t (unsigned int)tx_free_thresh,\n\t\t\t (int)dev->data->port_id, (int)queue_idx);\n\t\treturn -(EINVAL);\n\t}\n\tif (tx_rs_thresh > tx_free_thresh) {\n\t\tPMD_INIT_LOG(ERR, \"tx_rs_thresh must be less than or equal to \"\n\t\t\t \"tx_free_thresh. (tx_free_thresh=%u \"\n\t\t\t \"tx_rs_thresh=%u port=%d queue=%d)\",\n\t\t\t (unsigned int)tx_free_thresh,\n\t\t\t (unsigned int)tx_rs_thresh,\n\t\t\t (int)dev->data->port_id,\n\t\t\t (int)queue_idx);\n\t\treturn -(EINVAL);\n\t}\n\tif ((nb_desc % tx_rs_thresh) != 0) {\n\t\tPMD_INIT_LOG(ERR, \"tx_rs_thresh must be a divisor of the \"\n\t\t\t \"number of TX descriptors. (tx_rs_thresh=%u \"\n\t\t\t \"port=%d queue=%d)\", (unsigned int)tx_rs_thresh,\n\t\t\t (int)dev->data->port_id, (int)queue_idx);\n\t\treturn -(EINVAL);\n\t}\n\n\t/*\n\t * If rs_bit_thresh is greater than 1, then TX WTHRESH should be\n\t * set to 0. If WTHRESH is greater than zero, the RS bit is ignored\n\t * by the NIC and all descriptors are written back after the NIC\n\t * accumulates WTHRESH descriptors.\n\t */\n\tif ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {\n\t\tPMD_INIT_LOG(ERR, \"TX WTHRESH must be set to 0 if \"\n\t\t\t \"tx_rs_thresh is greater than 1. (tx_rs_thresh=%u \"\n\t\t\t \"port=%d queue=%d)\", (unsigned int)tx_rs_thresh,\n\t\t\t (int)dev->data->port_id, (int)queue_idx);\n\t\treturn -(EINVAL);\n\t}\n\n\t/* Free memory prior to re-allocation if needed... */\n\tif (dev->data->tx_queues[queue_idx] != NULL) {\n\t\tixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);\n\t\tdev->data->tx_queues[queue_idx] = NULL;\n\t}\n\n\t/* First allocate the tx queue data structure */\n\ttxq = rte_zmalloc_socket(\"ethdev TX queue\", sizeof(struct ixgbe_tx_queue),\n\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n\tif (txq == NULL)\n\t\treturn (-ENOMEM);\n\n\t/*\n\t * Allocate TX ring hardware descriptors. A memzone large enough to\n\t * handle the maximum ring size is allocated in order to allow for\n\t * resizing in later calls to the queue setup function.\n\t */\n\ttz = ring_dma_zone_reserve(dev, \"tx_ring\", queue_idx,\n\t\t\tsizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,\n\t\t\tsocket_id);\n\tif (tz == NULL) {\n\t\tixgbe_tx_queue_release(txq);\n\t\treturn (-ENOMEM);\n\t}\n\n\ttxq->nb_tx_desc = nb_desc;\n\ttxq->tx_rs_thresh = tx_rs_thresh;\n\ttxq->tx_free_thresh = tx_free_thresh;\n\ttxq->pthresh = tx_conf->tx_thresh.pthresh;\n\ttxq->hthresh = tx_conf->tx_thresh.hthresh;\n\ttxq->wthresh = tx_conf->tx_thresh.wthresh;\n\ttxq->queue_id = queue_idx;\n\ttxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?\n\t\tqueue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);\n\ttxq->port_id = dev->data->port_id;\n\ttxq->txq_flags = tx_conf->txq_flags;\n\ttxq->ops = &def_txq_ops;\n\ttxq->tx_deferred_start = tx_conf->tx_deferred_start;\n\n\t/*\n\t * Modification to set VFTDT for virtual function if vf is detected\n\t */\n\tif (hw->mac.type == ixgbe_mac_82599_vf ||\n\t hw->mac.type == ixgbe_mac_X540_vf ||\n\t hw->mac.type == ixgbe_mac_X550_vf ||\n\t hw->mac.type == ixgbe_mac_X550EM_x_vf)\n\t\ttxq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));\n\telse\n\t\ttxq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));\n#ifndef\tRTE_LIBRTE_XEN_DOM0\n\ttxq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;\n#else\n\ttxq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);\n#endif\n\ttxq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;\n\n\t/* Allocate software ring */\n\ttxq->sw_ring = rte_zmalloc_socket(\"txq->sw_ring\",\n\t\t\t\tsizeof(struct ixgbe_tx_entry) * nb_desc,\n\t\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (txq->sw_ring == NULL) {\n\t\tixgbe_tx_queue_release(txq);\n\t\treturn (-ENOMEM);\n\t}\n\tPMD_INIT_LOG(DEBUG, \"sw_ring=%p hw_ring=%p dma_addr=0x%\"PRIx64,\n\t\t txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);\n\n\t/* set up vector or scalar TX function as appropriate */\n\tixgbe_set_tx_function(dev, txq);\n\n\ttxq->ops->reset(txq);\n\n\tdev->data->tx_queues[queue_idx] = txq;\n\n\n\treturn (0);\n}\n\n/**\n * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster\n *\n * The \"next\" pointer of the last segment of (not-yet-completed) RSC clusters\n * in the sw_rsc_ring is not set to NULL but rather points to the next\n * mbuf of this RSC aggregation (that has not been completed yet and still\n * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we\n * will just free first \"nb_segs\" segments of the cluster explicitly by calling\n * an rte_pktmbuf_free_seg().\n *\n * @m scattered cluster head\n */\nstatic void __attribute__((cold))\nixgbe_free_sc_cluster(struct rte_mbuf *m)\n{\n\tuint8_t i, nb_segs = m->nb_segs;\n\tstruct rte_mbuf *next_seg;\n\n\tfor (i = 0; i < nb_segs; i++) {\n\t\tnext_seg = m->next;\n\t\trte_pktmbuf_free_seg(m);\n\t\tm = next_seg;\n\t}\n}\n\nstatic void __attribute__((cold))\nixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)\n{\n\tunsigned i;\n\n#ifdef RTE_IXGBE_INC_VECTOR\n\t/* SSE Vector driver has a different way of releasing mbufs. */\n\tif (rxq->rx_using_sse) {\n\t\tixgbe_rx_queue_release_mbufs_vec(rxq);\n\t\treturn;\n\t}\n#endif\n\n\tif (rxq->sw_ring != NULL) {\n\t\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n\t\t\tif (rxq->sw_ring[i].mbuf != NULL) {\n\t\t\t\trte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);\n\t\t\t\trxq->sw_ring[i].mbuf = NULL;\n\t\t\t}\n\t\t}\n\t\tif (rxq->rx_nb_avail) {\n\t\t\tfor (i = 0; i < rxq->rx_nb_avail; ++i) {\n\t\t\t\tstruct rte_mbuf *mb;\n\t\t\t\tmb = rxq->rx_stage[rxq->rx_next_avail + i];\n\t\t\t\trte_pktmbuf_free_seg(mb);\n\t\t\t}\n\t\t\trxq->rx_nb_avail = 0;\n\t\t}\n\t}\n\n\tif (rxq->sw_sc_ring)\n\t\tfor (i = 0; i < rxq->nb_rx_desc; i++)\n\t\t\tif (rxq->sw_sc_ring[i].fbuf) {\n\t\t\t\tixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);\n\t\t\t\trxq->sw_sc_ring[i].fbuf = NULL;\n\t\t\t}\n}\n\nstatic void __attribute__((cold))\nixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)\n{\n\tif (rxq != NULL) {\n\t\tixgbe_rx_queue_release_mbufs(rxq);\n\t\trte_free(rxq->sw_ring);\n\t\trte_free(rxq->sw_sc_ring);\n\t\trte_free(rxq);\n\t}\n}\n\nvoid __attribute__((cold))\nixgbe_dev_rx_queue_release(void *rxq)\n{\n\tixgbe_rx_queue_release(rxq);\n}\n\n/*\n * Check if Rx Burst Bulk Alloc function can be used.\n * Return\n * 0: the preconditions are satisfied and the bulk allocation function\n * can be used.\n * -EINVAL: the preconditions are NOT satisfied and the default Rx burst\n * function must be used.\n */\nstatic inline int __attribute__((cold))\ncheck_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)\n{\n\tint ret = 0;\n\n\t/*\n\t * Make sure the following pre-conditions are satisfied:\n\t * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST\n\t * rxq->rx_free_thresh < rxq->nb_rx_desc\n\t * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0\n\t * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)\n\t * Scattered packets are not supported. This should be checked\n\t * outside of this function.\n\t */\n\tif (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {\n\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions: \"\n\t\t\t \"rxq->rx_free_thresh=%d, \"\n\t\t\t \"RTE_PMD_IXGBE_RX_MAX_BURST=%d\",\n\t\t\t rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);\n\t\tret = -EINVAL;\n\t} else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {\n\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions: \"\n\t\t\t \"rxq->rx_free_thresh=%d, \"\n\t\t\t \"rxq->nb_rx_desc=%d\",\n\t\t\t rxq->rx_free_thresh, rxq->nb_rx_desc);\n\t\tret = -EINVAL;\n\t} else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {\n\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions: \"\n\t\t\t \"rxq->nb_rx_desc=%d, \"\n\t\t\t \"rxq->rx_free_thresh=%d\",\n\t\t\t rxq->nb_rx_desc, rxq->rx_free_thresh);\n\t\tret = -EINVAL;\n\t} else if (!(rxq->nb_rx_desc <\n\t (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {\n\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions: \"\n\t\t\t \"rxq->nb_rx_desc=%d, \"\n\t\t\t \"IXGBE_MAX_RING_DESC=%d, \"\n\t\t\t \"RTE_PMD_IXGBE_RX_MAX_BURST=%d\",\n\t\t\t rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,\n\t\t\t RTE_PMD_IXGBE_RX_MAX_BURST);\n\t\tret = -EINVAL;\n\t}\n\n\treturn ret;\n}\n\n/* Reset dynamic ixgbe_rx_queue fields back to defaults */\nstatic void __attribute__((cold))\nixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)\n{\n\tstatic const union ixgbe_adv_rx_desc zeroed_desc = {{0}};\n\tunsigned i;\n\tuint16_t len = rxq->nb_rx_desc;\n\n\t/*\n\t * By default, the Rx queue setup function allocates enough memory for\n\t * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires\n\t * extra memory at the end of the descriptor ring to be zero'd out. A\n\t * pre-condition for using the Rx burst bulk alloc function is that the\n\t * number of descriptors is less than or equal to\n\t * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the\n\t * constraints here to see if we need to zero out memory after the end\n\t * of the H/W descriptor ring.\n\t */\n\tif (adapter->rx_bulk_alloc_allowed)\n\t\t/* zero out extra memory */\n\t\tlen += RTE_PMD_IXGBE_RX_MAX_BURST;\n\n\t/*\n\t * Zero out HW ring memory. Zero out extra memory at the end of\n\t * the H/W ring so look-ahead logic in Rx Burst bulk alloc function\n\t * reads extra memory as zeros.\n\t */\n\tfor (i = 0; i < len; i++) {\n\t\trxq->rx_ring[i] = zeroed_desc;\n\t}\n\n\t/*\n\t * initialize extra software ring entries. Space for these extra\n\t * entries is always allocated\n\t */\n\tmemset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));\n\tfor (i = rxq->nb_rx_desc; i < len; ++i) {\n\t\trxq->sw_ring[i].mbuf = &rxq->fake_mbuf;\n\t}\n\n\trxq->rx_nb_avail = 0;\n\trxq->rx_next_avail = 0;\n\trxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);\n\trxq->rx_tail = 0;\n\trxq->nb_rx_hold = 0;\n\trxq->pkt_first_seg = NULL;\n\trxq->pkt_last_seg = NULL;\n\n#ifdef RTE_IXGBE_INC_VECTOR\n\trxq->rxrearm_start = 0;\n\trxq->rxrearm_nb = 0;\n#endif\n}\n\nint __attribute__((cold))\nixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,\n\t\t\t uint16_t queue_idx,\n\t\t\t uint16_t nb_desc,\n\t\t\t unsigned int socket_id,\n\t\t\t const struct rte_eth_rxconf *rx_conf,\n\t\t\t struct rte_mempool *mp)\n{\n\tconst struct rte_memzone *rz;\n\tstruct ixgbe_rx_queue *rxq;\n\tstruct ixgbe_hw *hw;\n\tuint16_t len;\n\tstruct ixgbe_adapter *adapter =\n\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/*\n\t * Validate number of receive descriptors.\n\t * It must not exceed hardware maximum, and must be multiple\n\t * of IXGBE_ALIGN.\n\t */\n\tif (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||\n\t (nb_desc > IXGBE_MAX_RING_DESC) ||\n\t (nb_desc < IXGBE_MIN_RING_DESC)) {\n\t\treturn (-EINVAL);\n\t}\n\n\t/* Free memory prior to re-allocation if needed... */\n\tif (dev->data->rx_queues[queue_idx] != NULL) {\n\t\tixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);\n\t\tdev->data->rx_queues[queue_idx] = NULL;\n\t}\n\n\t/* First allocate the rx queue data structure */\n\trxq = rte_zmalloc_socket(\"ethdev RX queue\", sizeof(struct ixgbe_rx_queue),\n\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n\tif (rxq == NULL)\n\t\treturn (-ENOMEM);\n\trxq->mb_pool = mp;\n\trxq->nb_rx_desc = nb_desc;\n\trxq->rx_free_thresh = rx_conf->rx_free_thresh;\n\trxq->queue_id = queue_idx;\n\trxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?\n\t\tqueue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);\n\trxq->port_id = dev->data->port_id;\n\trxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?\n\t\t\t\t\t\t\t0 : ETHER_CRC_LEN);\n\trxq->drop_en = rx_conf->rx_drop_en;\n\trxq->rx_deferred_start = rx_conf->rx_deferred_start;\n\n\t/*\n\t * Allocate RX ring hardware descriptors. A memzone large enough to\n\t * handle the maximum ring size is allocated in order to allow for\n\t * resizing in later calls to the queue setup function.\n\t */\n\trz = ring_dma_zone_reserve(dev, \"rx_ring\", queue_idx,\n\t\t\t\t RX_RING_SZ, socket_id);\n\tif (rz == NULL) {\n\t\tixgbe_rx_queue_release(rxq);\n\t\treturn (-ENOMEM);\n\t}\n\n\t/*\n\t * Zero init all the descriptors in the ring.\n\t */\n\tmemset (rz->addr, 0, RX_RING_SZ);\n\n\t/*\n\t * Modified to setup VFRDT for Virtual Function\n\t */\n\tif (hw->mac.type == ixgbe_mac_82599_vf ||\n\t hw->mac.type == ixgbe_mac_X540_vf ||\n\t hw->mac.type == ixgbe_mac_X550_vf ||\n\t hw->mac.type == ixgbe_mac_X550EM_x_vf) {\n\t\trxq->rdt_reg_addr =\n\t\t\tIXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));\n\t\trxq->rdh_reg_addr =\n\t\t\tIXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));\n\t}\n\telse {\n\t\trxq->rdt_reg_addr =\n\t\t\tIXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));\n\t\trxq->rdh_reg_addr =\n\t\t\tIXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));\n\t}\n#ifndef RTE_LIBRTE_XEN_DOM0\n\trxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;\n#else\n\trxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);\n#endif\n\trxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;\n\n\t/*\n\t * Certain constraints must be met in order to use the bulk buffer\n\t * allocation Rx burst function. If any of Rx queues doesn't meet them\n\t * the feature should be disabled for the whole port.\n\t */\n\tif (check_rx_burst_bulk_alloc_preconditions(rxq)) {\n\t\tPMD_INIT_LOG(DEBUG, \"queue[%d] doesn't meet Rx Bulk Alloc \"\n\t\t\t\t \"preconditions - canceling the feature for \"\n\t\t\t\t \"the whole port[%d]\",\n\t\t\t rxq->queue_id, rxq->port_id);\n\t\tadapter->rx_bulk_alloc_allowed = false;\n\t}\n\n\t/*\n\t * Allocate software ring. Allow for space at the end of the\n\t * S/W ring to make sure look-ahead logic in bulk alloc Rx burst\n\t * function does not access an invalid memory region.\n\t */\n\tlen = nb_desc;\n\tif (adapter->rx_bulk_alloc_allowed)\n\t\tlen += RTE_PMD_IXGBE_RX_MAX_BURST;\n\n\trxq->sw_ring = rte_zmalloc_socket(\"rxq->sw_ring\",\n\t\t\t\t\t sizeof(struct ixgbe_rx_entry) * len,\n\t\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n\tif (!rxq->sw_ring) {\n\t\tixgbe_rx_queue_release(rxq);\n\t\treturn (-ENOMEM);\n\t}\n\n\t/*\n\t * Always allocate even if it's not going to be needed in order to\n\t * simplify the code.\n\t *\n\t * This ring is used in LRO and Scattered Rx cases and Scattered Rx may\n\t * be requested in ixgbe_dev_rx_init(), which is called later from\n\t * dev_start() flow.\n\t */\n\trxq->sw_sc_ring =\n\t\trte_zmalloc_socket(\"rxq->sw_sc_ring\",\n\t\t\t\t sizeof(struct ixgbe_scattered_rx_entry) * len,\n\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n\tif (!rxq->sw_sc_ring) {\n\t\tixgbe_rx_queue_release(rxq);\n\t\treturn (-ENOMEM);\n\t}\n\n\tPMD_INIT_LOG(DEBUG, \"sw_ring=%p sw_sc_ring=%p hw_ring=%p \"\n\t\t\t \"dma_addr=0x%\"PRIx64,\n\t\t rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,\n\t\t rxq->rx_ring_phys_addr);\n\n\tif (!rte_is_power_of_2(nb_desc)) {\n\t\tPMD_INIT_LOG(DEBUG, \"queue[%d] doesn't meet Vector Rx \"\n\t\t\t\t \"preconditions - canceling the feature for \"\n\t\t\t\t \"the whole port[%d]\",\n\t\t\t rxq->queue_id, rxq->port_id);\n\t\tadapter->rx_vec_allowed = false;\n\t} else\n\t\tixgbe_rxq_vec_setup(rxq);\n\n\tdev->data->rx_queues[queue_idx] = rxq;\n\n\tixgbe_reset_rx_queue(adapter, rxq);\n\n\treturn 0;\n}\n\nuint32_t\nixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n{\n#define IXGBE_RXQ_SCAN_INTERVAL 4\n\tvolatile union ixgbe_adv_rx_desc *rxdp;\n\tstruct ixgbe_rx_queue *rxq;\n\tuint32_t desc = 0;\n\n\tif (rx_queue_id >= dev->data->nb_rx_queues) {\n\t\tPMD_RX_LOG(ERR, \"Invalid RX queue id=%d\", rx_queue_id);\n\t\treturn 0;\n\t}\n\n\trxq = dev->data->rx_queues[rx_queue_id];\n\trxdp = &(rxq->rx_ring[rxq->rx_tail]);\n\n\twhile ((desc < rxq->nb_rx_desc) &&\n\t\t(rxdp->wb.upper.status_error &\n\t\t\trte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {\n\t\tdesc += IXGBE_RXQ_SCAN_INTERVAL;\n\t\trxdp += IXGBE_RXQ_SCAN_INTERVAL;\n\t\tif (rxq->rx_tail + desc >= rxq->nb_rx_desc)\n\t\t\trxdp = &(rxq->rx_ring[rxq->rx_tail +\n\t\t\t\tdesc - rxq->nb_rx_desc]);\n\t}\n\n\treturn desc;\n}\n\nint\nixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)\n{\n\tvolatile union ixgbe_adv_rx_desc *rxdp;\n\tstruct ixgbe_rx_queue *rxq = rx_queue;\n\tuint32_t desc;\n\n\tif (unlikely(offset >= rxq->nb_rx_desc))\n\t\treturn 0;\n\tdesc = rxq->rx_tail + offset;\n\tif (desc >= rxq->nb_rx_desc)\n\t\tdesc -= rxq->nb_rx_desc;\n\n\trxdp = &rxq->rx_ring[desc];\n\treturn !!(rxdp->wb.upper.status_error &\n\t\t\trte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));\n}\n\nvoid __attribute__((cold))\nixgbe_dev_clear_queues(struct rte_eth_dev *dev)\n{\n\tunsigned i;\n\tstruct ixgbe_adapter *adapter =\n\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tstruct ixgbe_tx_queue *txq = dev->data->tx_queues[i];\n\t\tif (txq != NULL) {\n\t\t\ttxq->ops->release_mbufs(txq);\n\t\t\ttxq->ops->reset(txq);\n\t\t}\n\t}\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tstruct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];\n\t\tif (rxq != NULL) {\n\t\t\tixgbe_rx_queue_release_mbufs(rxq);\n\t\t\tixgbe_reset_rx_queue(adapter, rxq);\n\t\t}\n\t}\n}\n\nvoid\nixgbe_dev_free_queues(struct rte_eth_dev *dev)\n{\n\tunsigned i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);\n\t\tdev->data->rx_queues[i] = NULL;\n\t}\n\tdev->data->nb_rx_queues = 0;\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);\n\t\tdev->data->tx_queues[i] = NULL;\n\t}\n\tdev->data->nb_tx_queues = 0;\n}\n\n/*********************************************************************\n *\n * Device RX/TX init functions\n *\n **********************************************************************/\n\n/**\n * Receive Side Scaling (RSS)\n * See section 7.1.2.8 in the following document:\n * \"Intel 82599 10 GbE Controller Datasheet\" - Revision 2.1 October 2009\n *\n * Principles:\n * The source and destination IP addresses of the IP header and the source\n * and destination ports of TCP/UDP headers, if any, of received packets are\n * hashed against a configurable random key to compute a 32-bit RSS hash result.\n * The seven (7) LSBs of the 32-bit hash result are used as an index into a\n * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit\n * RSS output index which is used as the RX queue index where to store the\n * received packets.\n * The following output is supplied in the RX write-back descriptor:\n * - 32-bit result of the Microsoft RSS hash function,\n * - 4-bit RSS type field.\n */\n\n/*\n * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.\n * Used as the default key.\n */\nstatic uint8_t rss_intel_key[40] = {\n\t0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,\n\t0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,\n\t0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,\n\t0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,\n\t0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,\n};\n\nstatic void\nixgbe_rss_disable(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw;\n\tuint32_t mrqc;\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tmrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);\n\tmrqc &= ~IXGBE_MRQC_RSSEN;\n\tIXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);\n}\n\nstatic void\nixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)\n{\n\tuint8_t *hash_key;\n\tuint32_t mrqc;\n\tuint32_t rss_key;\n\tuint64_t rss_hf;\n\tuint16_t i;\n\n\thash_key = rss_conf->rss_key;\n\tif (hash_key != NULL) {\n\t\t/* Fill in RSS hash key */\n\t\tfor (i = 0; i < 10; i++) {\n\t\t\trss_key = hash_key[(i * 4)];\n\t\t\trss_key |= hash_key[(i * 4) + 1] << 8;\n\t\t\trss_key |= hash_key[(i * 4) + 2] << 16;\n\t\t\trss_key |= hash_key[(i * 4) + 3] << 24;\n\t\t\tIXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);\n\t\t}\n\t}\n\n\t/* Set configured hashing protocols in MRQC register */\n\trss_hf = rss_conf->rss_hf;\n\tmrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */\n\tif (rss_hf & ETH_RSS_IPV4)\n\t\tmrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;\n\tif (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)\n\t\tmrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;\n\tif (rss_hf & ETH_RSS_IPV6)\n\t\tmrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;\n\tif (rss_hf & ETH_RSS_IPV6_EX)\n\t\tmrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;\n\tif (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)\n\t\tmrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;\n\tif (rss_hf & ETH_RSS_IPV6_TCP_EX)\n\t\tmrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;\n\tif (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)\n\t\tmrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;\n\tif (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)\n\t\tmrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;\n\tif (rss_hf & ETH_RSS_IPV6_UDP_EX)\n\t\tmrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;\n\tIXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);\n}\n\nint\nixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_conf *rss_conf)\n{\n\tstruct ixgbe_hw *hw;\n\tuint32_t mrqc;\n\tuint64_t rss_hf;\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/*\n\t * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):\n\t * \"RSS enabling cannot be done dynamically while it must be\n\t * preceded by a software reset\"\n\t * Before changing anything, first check that the update RSS operation\n\t * does not attempt to disable RSS, if RSS was enabled at\n\t * initialization time, or does not attempt to enable RSS, if RSS was\n\t * disabled at initialization time.\n\t */\n\trss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;\n\tmrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);\n\tif (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */\n\t\tif (rss_hf != 0) /* Enable RSS */\n\t\t\treturn -(EINVAL);\n\t\treturn 0; /* Nothing to do */\n\t}\n\t/* RSS enabled */\n\tif (rss_hf == 0) /* Disable RSS */\n\t\treturn -(EINVAL);\n\tixgbe_hw_rss_hash_set(hw, rss_conf);\n\treturn 0;\n}\n\nint\nixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_conf *rss_conf)\n{\n\tstruct ixgbe_hw *hw;\n\tuint8_t *hash_key;\n\tuint32_t mrqc;\n\tuint32_t rss_key;\n\tuint64_t rss_hf;\n\tuint16_t i;\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\thash_key = rss_conf->rss_key;\n\tif (hash_key != NULL) {\n\t\t/* Return RSS hash key */\n\t\tfor (i = 0; i < 10; i++) {\n\t\t\trss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);\n\t\t\thash_key[(i * 4)] = rss_key & 0x000000FF;\n\t\t\thash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;\n\t\t\thash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;\n\t\t\thash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;\n\t\t}\n\t}\n\n\t/* Get RSS functions configured in MRQC register */\n\tmrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);\n\tif ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */\n\t\trss_conf->rss_hf = 0;\n\t\treturn 0;\n\t}\n\trss_hf = 0;\n\tif (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)\n\t\trss_hf |= ETH_RSS_IPV4;\n\tif (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;\n\tif (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)\n\t\trss_hf |= ETH_RSS_IPV6;\n\tif (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)\n\t\trss_hf |= ETH_RSS_IPV6_EX;\n\tif (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;\n\tif (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)\n\t\trss_hf |= ETH_RSS_IPV6_TCP_EX;\n\tif (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;\n\tif (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)\n\t\trss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;\n\tif (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)\n\t\trss_hf |= ETH_RSS_IPV6_UDP_EX;\n\trss_conf->rss_hf = rss_hf;\n\treturn 0;\n}\n\nstatic void\nixgbe_rss_configure(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_rss_conf rss_conf;\n\tstruct ixgbe_hw *hw;\n\tuint32_t reta;\n\tuint16_t i;\n\tuint16_t j;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/*\n\t * Fill in redirection table\n\t * The byte-swap is needed because NIC registers are in\n\t * little-endian order.\n\t */\n\treta = 0;\n\tfor (i = 0, j = 0; i < 128; i++, j++) {\n\t\tif (j == dev->data->nb_rx_queues)\n\t\t\tj = 0;\n\t\treta = (reta << 8) | j;\n\t\tif ((i & 3) == 3)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),\n\t\t\t\t\trte_bswap32(reta));\n\t}\n\n\t/*\n\t * Configure the RSS key and the RSS protocols used to compute\n\t * the RSS hash of input packets.\n\t */\n\trss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;\n\tif ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {\n\t\tixgbe_rss_disable(dev);\n\t\treturn;\n\t}\n\tif (rss_conf.rss_key == NULL)\n\t\trss_conf.rss_key = rss_intel_key; /* Default hash key */\n\tixgbe_hw_rss_hash_set(hw, &rss_conf);\n}\n\n#define NUM_VFTA_REGISTERS 128\n#define NIC_RX_BUFFER_SIZE 0x200\n\nstatic void\nixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_vmdq_dcb_conf *cfg;\n\tstruct ixgbe_hw *hw;\n\tenum rte_eth_nb_pools num_pools;\n\tuint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;\n\tuint16_t pbsize;\n\tuint8_t nb_tcs; /* number of traffic classes */\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tcfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;\n\tnum_pools = cfg->nb_queue_pools;\n\t/* Check we have a valid number of pools */\n\tif (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {\n\t\tixgbe_rss_disable(dev);\n\t\treturn;\n\t}\n\t/* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */\n\tnb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);\n\n\t/*\n\t * RXPBSIZE\n\t * split rx buffer up into sections, each for 1 traffic class\n\t */\n\tpbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);\n\tfor (i = 0 ; i < nb_tcs; i++) {\n\t\tuint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));\n\t\trxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));\n\t\t/* clear 10 bits. */\n\t\trxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);\n\t}\n\t/* zero alloc all unused TCs */\n\tfor (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {\n\t\tuint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));\n\t\trxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));\n\t\t/* clear 10 bits. */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);\n\t}\n\n\t/* MRQC: enable vmdq and dcb */\n\tmrqc = ((num_pools == ETH_16_POOLS) ? \\\n\t\tIXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );\n\tIXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);\n\n\t/* PFVTCTL: turn on virtualisation and set the default pool */\n\tvt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;\n\tif (cfg->enable_default_pool) {\n\t\tvt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);\n\t} else {\n\t\tvt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;\n\t}\n\n\tIXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);\n\n\t/* RTRUP2TC: mapping user priorities to traffic classes (TCs) */\n\tqueue_mapping = 0;\n\tfor (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)\n\t\t/*\n\t\t * mapping is done with 3 bits per priority,\n\t\t * so shift by i*3 each time\n\t\t */\n\t\tqueue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));\n\n\tIXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);\n\n\t/* RTRPCS: DCB related */\n\tIXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);\n\n\t/* VLNCTRL: enable vlan filtering and allow all vlan tags through */\n\tvlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n\tvlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */\n\tIXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);\n\n\t/* VFTA - enable all vlan filters */\n\tfor (i = 0; i < NUM_VFTA_REGISTERS; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);\n\t}\n\n\t/* VFRE: pool enabling for receive - 16 or 32 */\n\tIXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \\\n\t\t\tnum_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);\n\n\t/*\n\t * MPSAR - allow pools to read specific mac addresses\n\t * In this case, all pools should be able to read from mac addr 0\n\t */\n\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);\n\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);\n\n\t/* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */\n\tfor (i = 0; i < cfg->nb_pool_maps; i++) {\n\t\t/* set vlan id in VF register and set the valid bit */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \\\n\t\t\t\t(cfg->pool_map[i].vlan_id & 0xFFF)));\n\t\t/*\n\t\t * Put the allowed pools in VFB reg. As we only have 16 or 32\n\t\t * pools, we only need to use the first half of the register\n\t\t * i.e. bits 0-31\n\t\t */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);\n\t}\n}\n\n/**\n * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n */\nstatic void\nixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,\n struct ixgbe_dcb_config *dcb_config)\n{\n\tuint32_t reg;\n\tuint32_t q;\n\n\tPMD_INIT_FUNC_TRACE();\n\tif (hw->mac.type != ixgbe_mac_82598EB) {\n\t\t/* Disable the Tx desc arbiter so that MTQC can be changed */\n\t\treg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);\n\t\treg |= IXGBE_RTTDCS_ARBDIS;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);\n\n\t\t/* Enable DCB for Tx with 8 TCs */\n\t\tif (dcb_config->num_tcs.pg_tcs == 8) {\n\t\t\treg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;\n\t\t}\n\t\telse {\n\t\t\treg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;\n\t\t}\n\t\tif (dcb_config->vt_mode)\n\t reg |= IXGBE_MTQC_VT_ENA;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);\n\n\t\t/* Disable drop for all queues */\n\t\tfor (q = 0; q < 128; q++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_QDE,\n\t (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));\n\n\t\t/* Enable the Tx desc arbiter */\n\t\treg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);\n\t\treg &= ~IXGBE_RTTDCS_ARBDIS;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);\n\n\t\t/* Enable Security TX Buffer IFG for DCB */\n\t\treg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);\n\t\treg |= IXGBE_SECTX_DCB;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);\n\t}\n\treturn;\n}\n\n/**\n * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters\n * @dev: pointer to rte_eth_dev structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n */\nstatic void\nixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,\n\t\t\tstruct ixgbe_dcb_config *dcb_config)\n{\n\tstruct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =\n\t\t\t&dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;\n\tstruct ixgbe_hw *hw =\n\t\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tPMD_INIT_FUNC_TRACE();\n\tif (hw->mac.type != ixgbe_mac_82598EB)\n\t\t/*PF VF Transmit Enable*/\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTE(0),\n\t\t\tvmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);\n\n\t/*Configure general DCB TX parameters*/\n\tixgbe_dcb_tx_hw_config(hw,dcb_config);\n\treturn;\n}\n\nstatic void\nixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,\n struct ixgbe_dcb_config *dcb_config)\n{\n\tstruct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =\n\t\t\t&dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;\n\tstruct ixgbe_dcb_tc_config *tc;\n\tuint8_t i,j;\n\n\t/* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */\n\tif (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {\n\t\tdcb_config->num_tcs.pg_tcs = ETH_8_TCS;\n\t\tdcb_config->num_tcs.pfc_tcs = ETH_8_TCS;\n\t}\n\telse {\n\t\tdcb_config->num_tcs.pg_tcs = ETH_4_TCS;\n\t\tdcb_config->num_tcs.pfc_tcs = ETH_4_TCS;\n\t}\n\t/* User Priority to Traffic Class mapping */\n\tfor (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {\n\t\tj = vmdq_rx_conf->dcb_queue[i];\n\t\ttc = &dcb_config->tc_config[j];\n\t\ttc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =\n\t\t\t\t\t\t(uint8_t)(1 << j);\n\t}\n}\n\nstatic void\nixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,\n struct ixgbe_dcb_config *dcb_config)\n{\n\tstruct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =\n\t\t\t&dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;\n\tstruct ixgbe_dcb_tc_config *tc;\n\tuint8_t i,j;\n\n\t/* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */\n\tif (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {\n\t\tdcb_config->num_tcs.pg_tcs = ETH_8_TCS;\n\t\tdcb_config->num_tcs.pfc_tcs = ETH_8_TCS;\n\t}\n\telse {\n\t\tdcb_config->num_tcs.pg_tcs = ETH_4_TCS;\n\t\tdcb_config->num_tcs.pfc_tcs = ETH_4_TCS;\n\t}\n\n\t/* User Priority to Traffic Class mapping */\n\tfor (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {\n\t\tj = vmdq_tx_conf->dcb_queue[i];\n\t\ttc = &dcb_config->tc_config[j];\n\t\ttc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =\n\t\t\t\t\t\t(uint8_t)(1 << j);\n\t}\n\treturn;\n}\n\nstatic void\nixgbe_dcb_rx_config(struct rte_eth_dev *dev,\n\t\tstruct ixgbe_dcb_config *dcb_config)\n{\n\tstruct rte_eth_dcb_rx_conf *rx_conf =\n\t\t\t&dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;\n\tstruct ixgbe_dcb_tc_config *tc;\n\tuint8_t i,j;\n\n\tdcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;\n\tdcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;\n\n\t/* User Priority to Traffic Class mapping */\n\tfor (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {\n\t\tj = rx_conf->dcb_queue[i];\n\t\ttc = &dcb_config->tc_config[j];\n\t\ttc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =\n\t\t\t\t\t\t(uint8_t)(1 << j);\n\t}\n}\n\nstatic void\nixgbe_dcb_tx_config(struct rte_eth_dev *dev,\n\t\tstruct ixgbe_dcb_config *dcb_config)\n{\n\tstruct rte_eth_dcb_tx_conf *tx_conf =\n\t\t\t&dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;\n\tstruct ixgbe_dcb_tc_config *tc;\n\tuint8_t i,j;\n\n\tdcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;\n\tdcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;\n\n\t/* User Priority to Traffic Class mapping */\n\tfor (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {\n\t\tj = tx_conf->dcb_queue[i];\n\t\ttc = &dcb_config->tc_config[j];\n\t\ttc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =\n\t\t\t\t\t\t(uint8_t)(1 << j);\n\t}\n}\n\n/**\n * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters\n * @hw: pointer to hardware structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n */\nstatic void\nixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,\n struct ixgbe_dcb_config *dcb_config)\n{\n\tuint32_t reg;\n\tuint32_t vlanctrl;\n\tuint8_t i;\n\n\tPMD_INIT_FUNC_TRACE();\n\t/*\n\t * Disable the arbiter before changing parameters\n\t * (always enable recycle mode; WSP)\n\t */\n\treg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);\n\n\tif (hw->mac.type != ixgbe_mac_82598EB) {\n\t\treg = IXGBE_READ_REG(hw, IXGBE_MRQC);\n\t\tif (dcb_config->num_tcs.pg_tcs == 4) {\n\t\t\tif (dcb_config->vt_mode)\n\t\t\t\treg = (reg & ~IXGBE_MRQC_MRQE_MASK) |\n\t\t\t\t\tIXGBE_MRQC_VMDQRT4TCEN;\n\t\t\telse {\n\t\t\t\tIXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);\n\t\t\t\treg = (reg & ~IXGBE_MRQC_MRQE_MASK) |\n\t\t\t\t\tIXGBE_MRQC_RT4TCEN;\n\t\t\t}\n\t\t}\n\t\tif (dcb_config->num_tcs.pg_tcs == 8) {\n\t\t\tif (dcb_config->vt_mode)\n\t\t\t\treg = (reg & ~IXGBE_MRQC_MRQE_MASK) |\n\t\t\t\t\tIXGBE_MRQC_VMDQRT8TCEN;\n\t\t\telse {\n\t\t\t\tIXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);\n\t\t\t\treg = (reg & ~IXGBE_MRQC_MRQE_MASK) |\n\t\t\t\t\tIXGBE_MRQC_RT8TCEN;\n\t\t\t}\n\t\t}\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);\n\t}\n\n\t/* VLNCTRL: enable vlan filtering and allow all vlan tags through */\n\tvlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n\tvlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */\n\tIXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);\n\n\t/* VFTA - enable all vlan filters */\n\tfor (i = 0; i < NUM_VFTA_REGISTERS; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);\n\t}\n\n\t/*\n\t * Configure Rx packet plane (recycle mode; WSP) and\n\t * enable arbiter\n\t */\n\treg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;\n\tIXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);\n\n\treturn;\n}\n\nstatic void\nixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,\n\t\t\tuint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)\n{\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,\n\t\t\t\t\t\t tsa, map);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nstatic void\nixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,\n\t\t\t uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)\n{\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);\n\t\tixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_X550:\n\tcase ixgbe_mac_X550EM_x:\n\t\tixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);\n\t\tixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n#define DCB_RX_CONFIG 1\n#define DCB_TX_CONFIG 1\n#define DCB_TX_PB 1024\n/**\n * ixgbe_dcb_hw_configure - Enable DCB and configure\n * general DCB in VT mode and non-VT mode parameters\n * @dev: pointer to rte_eth_dev structure\n * @dcb_config: pointer to ixgbe_dcb_config structure\n */\nstatic int\nixgbe_dcb_hw_configure(struct rte_eth_dev *dev,\n\t\t\tstruct ixgbe_dcb_config *dcb_config)\n{\n\tint ret = 0;\n\tuint8_t i,pfc_en,nb_tcs;\n\tuint16_t pbsize;\n\tuint8_t config_dcb_rx = 0;\n\tuint8_t config_dcb_tx = 0;\n\tuint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};\n\tuint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};\n\tuint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};\n\tuint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};\n\tuint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};\n\tstruct ixgbe_dcb_tc_config *tc;\n\tuint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;\n\tstruct ixgbe_hw *hw =\n\t\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tswitch(dev->data->dev_conf.rxmode.mq_mode){\n\tcase ETH_MQ_RX_VMDQ_DCB:\n\t\tdcb_config->vt_mode = true;\n\t\tif (hw->mac.type != ixgbe_mac_82598EB) {\n\t\t\tconfig_dcb_rx = DCB_RX_CONFIG;\n\t\t\t/*\n\t\t\t *get dcb and VT rx configuration parameters\n\t\t\t *from rte_eth_conf\n\t\t\t */\n\t\t\tixgbe_vmdq_dcb_rx_config(dev,dcb_config);\n\t\t\t/*Configure general VMDQ and DCB RX parameters*/\n\t\t\tixgbe_vmdq_dcb_configure(dev);\n\t\t}\n\t\tbreak;\n\tcase ETH_MQ_RX_DCB:\n\t\tdcb_config->vt_mode = false;\n\t\tconfig_dcb_rx = DCB_RX_CONFIG;\n\t\t/* Get dcb TX configuration parameters from rte_eth_conf */\n\t\tixgbe_dcb_rx_config(dev,dcb_config);\n\t\t/*Configure general DCB RX parameters*/\n\t\tixgbe_dcb_rx_hw_config(hw, dcb_config);\n\t\tbreak;\n\tdefault:\n\t\tPMD_INIT_LOG(ERR, \"Incorrect DCB RX mode configuration\");\n\t\tbreak;\n\t}\n\tswitch (dev->data->dev_conf.txmode.mq_mode) {\n\tcase ETH_MQ_TX_VMDQ_DCB:\n\t\tdcb_config->vt_mode = true;\n\t\tconfig_dcb_tx = DCB_TX_CONFIG;\n\t\t/* get DCB and VT TX configuration parameters from rte_eth_conf */\n\t\tixgbe_dcb_vt_tx_config(dev,dcb_config);\n\t\t/*Configure general VMDQ and DCB TX parameters*/\n\t\tixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);\n\t\tbreak;\n\n\tcase ETH_MQ_TX_DCB:\n\t\tdcb_config->vt_mode = false;\n\t\tconfig_dcb_tx = DCB_TX_CONFIG;\n\t\t/*get DCB TX configuration parameters from rte_eth_conf*/\n\t\tixgbe_dcb_tx_config(dev,dcb_config);\n\t\t/*Configure general DCB TX parameters*/\n\t\tixgbe_dcb_tx_hw_config(hw, dcb_config);\n\t\tbreak;\n\tdefault:\n\t\tPMD_INIT_LOG(ERR, \"Incorrect DCB TX mode configuration\");\n\t\tbreak;\n\t}\n\n\tnb_tcs = dcb_config->num_tcs.pfc_tcs;\n\t/* Unpack map */\n\tixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);\n\tif(nb_tcs == ETH_4_TCS) {\n\t\t/* Avoid un-configured priority mapping to TC0 */\n\t\tuint8_t j = 4;\n\t\tuint8_t mask = 0xFF;\n\t\tfor (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)\n\t\t\tmask = (uint8_t)(mask & (~ (1 << map[i])));\n\t\tfor (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {\n\t\t\tif ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))\n\t\t\t\tmap[j++] = i;\n\t\t\tmask >>= 1;\n\t\t}\n\t\t/* Re-configure 4 TCs BW */\n\t\tfor (i = 0; i < nb_tcs; i++) {\n\t\t\ttc = &dcb_config->tc_config[i];\n\t\t\ttc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =\n\t\t\t\t\t\t(uint8_t)(100 / nb_tcs);\n\t\t\ttc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =\n\t\t\t\t\t\t(uint8_t)(100 / nb_tcs);\n\t\t}\n\t\tfor (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\t\ttc = &dcb_config->tc_config[i];\n\t\t\ttc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;\n\t\t\ttc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;\n\t\t}\n\t}\n\n\tif(config_dcb_rx) {\n\t\t/* Set RX buffer size */\n\t\tpbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);\n\t\tuint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;\n\t\tfor (i = 0 ; i < nb_tcs; i++) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);\n\t\t}\n\t\t/* zero alloc all unused TCs */\n\t\tfor (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);\n\t\t}\n\t}\n\tif(config_dcb_tx) {\n\t\t/* Only support an equally distributed Tx packet buffer strategy. */\n\t\tuint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;\n\t\tuint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;\n\t\tfor (i = 0; i < nb_tcs; i++) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);\n\t\t}\n\t\t/* Clear unused TCs, if any, to zero buffer size*/\n\t\tfor (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);\n\t\t}\n\t}\n\n\t/*Calculates traffic class credits*/\n\tixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,\n\t\t\t\tIXGBE_DCB_TX_CONFIG);\n\tixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,\n\t\t\t\tIXGBE_DCB_RX_CONFIG);\n\n\tif(config_dcb_rx) {\n\t\t/* Unpack CEE standard containers */\n\t\tixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);\n\t\tixgbe_dcb_unpack_max_cee(dcb_config, max);\n\t\tixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);\n\t\tixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);\n\t\t/* Configure PG(ETS) RX */\n\t\tixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);\n\t}\n\n\tif(config_dcb_tx) {\n\t\t/* Unpack CEE standard containers */\n\t\tixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);\n\t\tixgbe_dcb_unpack_max_cee(dcb_config, max);\n\t\tixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);\n\t\tixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);\n\t\t/* Configure PG(ETS) TX */\n\t\tixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);\n\t}\n\n\t/*Configure queue statistics registers*/\n\tixgbe_dcb_config_tc_stats_82599(hw, dcb_config);\n\n\t/* Check if the PFC is supported */\n\tif(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {\n\t\tpbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);\n\t\tfor (i = 0; i < nb_tcs; i++) {\n\t\t\t/*\n\t\t\t* If the TC count is 8,and the default high_water is 48,\n\t\t\t* the low_water is 16 as default.\n\t\t\t*/\n\t\t\thw->fc.high_water[i] = (pbsize * 3 ) / 4;\n\t\t\thw->fc.low_water[i] = pbsize / 4;\n\t\t\t/* Enable pfc for this TC */\n\t\t\ttc = &dcb_config->tc_config[i];\n\t\t\ttc->pfc = ixgbe_dcb_pfc_enabled;\n\t\t}\n\t\tixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);\n\t\tif(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)\n\t\t\tpfc_en &= 0x0F;\n\t\tret = ixgbe_dcb_config_pfc(hw, pfc_en, map);\n\t}\n\n\treturn ret;\n}\n\n/**\n * ixgbe_configure_dcb - Configure DCB Hardware\n * @dev: pointer to rte_eth_dev\n */\nvoid ixgbe_configure_dcb(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_dcb_config *dcb_cfg =\n\t\t\tIXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);\n\tstruct rte_eth_conf *dev_conf = &(dev->data->dev_conf);\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* check support mq_mode for DCB */\n\tif ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&\n\t (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))\n\t\treturn;\n\n\tif (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)\n\t\treturn;\n\n\t/** Configure DCB hardware **/\n\tixgbe_dcb_hw_configure(dev,dcb_cfg);\n\n\treturn;\n}\n\n/*\n * VMDq only support for 10 GbE NIC.\n */\nstatic void\nixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_vmdq_rx_conf *cfg;\n\tstruct ixgbe_hw *hw;\n\tenum rte_eth_nb_pools num_pools;\n\tuint32_t mrqc, vt_ctl, vlanctrl;\n\tuint32_t vmolr = 0;\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tcfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;\n\tnum_pools = cfg->nb_queue_pools;\n\n\tixgbe_rss_disable(dev);\n\n\t/* MRQC: enable vmdq */\n\tmrqc = IXGBE_MRQC_VMDQEN;\n\tIXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);\n\n\t/* PFVTCTL: turn on virtualisation and set the default pool */\n\tvt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;\n\tif (cfg->enable_default_pool)\n\t\tvt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);\n\telse\n\t\tvt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);\n\n\tfor (i = 0; i < (int)num_pools; i++) {\n\t\tvmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);\n\t}\n\n\t/* VLNCTRL: enable vlan filtering and allow all vlan tags through */\n\tvlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n\tvlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */\n\tIXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);\n\n\t/* VFTA - enable all vlan filters */\n\tfor (i = 0; i < NUM_VFTA_REGISTERS; i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);\n\n\t/* VFRE: pool enabling for receive - 64 */\n\tIXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);\n\tif (num_pools == ETH_64_POOLS)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);\n\n\t/*\n\t * MPSAR - allow pools to read specific mac addresses\n\t * In this case, all pools should be able to read from mac addr 0\n\t */\n\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);\n\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);\n\n\t/* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */\n\tfor (i = 0; i < cfg->nb_pool_maps; i++) {\n\t\t/* set vlan id in VF register and set the valid bit */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \\\n\t\t\t\t(cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));\n\t\t/*\n\t\t * Put the allowed pools in VFB reg. As we only have 16 or 64\n\t\t * pools, we only need to use the first half of the register\n\t\t * i.e. bits 0-31\n\t\t */\n\t\tif (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \\\n\t\t\t\t\t(cfg->pool_map[i].pools & UINT32_MAX));\n\t\telse\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \\\n\t\t\t\t\t((cfg->pool_map[i].pools >> 32) \\\n\t\t\t\t\t& UINT32_MAX));\n\n\t}\n\n\t/* PFDMA Tx General Switch Control Enables VMDQ loopback */\n\tif (cfg->enable_loop_back) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);\n\t\tfor (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);\n\t}\n\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/*\n * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters\n * @hw: pointer to hardware structure\n */\nstatic void\nixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)\n{\n\tuint32_t reg;\n\tuint32_t q;\n\n\tPMD_INIT_FUNC_TRACE();\n\t/*PF VF Transmit Enable*/\n\tIXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);\n\tIXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);\n\n\t/* Disable the Tx desc arbiter so that MTQC can be changed */\n\treg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);\n\treg |= IXGBE_RTTDCS_ARBDIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);\n\n\treg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;\n\tIXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);\n\n\t/* Disable drop for all queues */\n\tfor (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_QDE,\n\t (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));\n\n\t/* Enable the Tx desc arbiter */\n\treg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);\n\treg &= ~IXGBE_RTTDCS_ARBDIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);\n\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn;\n}\n\nstatic int __attribute__((cold))\nixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)\n{\n\tstruct ixgbe_rx_entry *rxe = rxq->sw_ring;\n\tuint64_t dma_addr;\n\tunsigned i;\n\n\t/* Initialize software ring entries */\n\tfor (i = 0; i < rxq->nb_rx_desc; i++) {\n\t\tvolatile union ixgbe_adv_rx_desc *rxd;\n\t\tstruct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);\n\t\tif (mbuf == NULL) {\n\t\t\tPMD_INIT_LOG(ERR, \"RX mbuf alloc failed queue_id=%u\",\n\t\t\t\t (unsigned) rxq->queue_id);\n\t\t\treturn (-ENOMEM);\n\t\t}\n\n\t\trte_mbuf_refcnt_set(mbuf, 1);\n\t\tmbuf->next = NULL;\n\t\tmbuf->data_off = RTE_PKTMBUF_HEADROOM;\n\t\tmbuf->nb_segs = 1;\n\t\tmbuf->port = rxq->port_id;\n\n\t\tdma_addr =\n\t\t\trte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));\n\t\trxd = &rxq->rx_ring[i];\n\t\trxd->read.hdr_addr = 0;\n\t\trxd->read.pkt_addr = dma_addr;\n\t\trxe[i].mbuf = mbuf;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nixgbe_config_vf_rss(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw;\n\tuint32_t mrqc;\n\n\tixgbe_rss_configure(dev);\n\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/* MRQC: enable VF RSS */\n\tmrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);\n\tmrqc &= ~IXGBE_MRQC_MRQE_MASK;\n\tswitch (RTE_ETH_DEV_SRIOV(dev).active) {\n\tcase ETH_64_POOLS:\n\t\tmrqc |= IXGBE_MRQC_VMDQRSS64EN;\n\t\tbreak;\n\n\tcase ETH_32_POOLS:\n\t\tmrqc |= IXGBE_MRQC_VMDQRSS32EN;\n\t\tbreak;\n\n\tdefault:\n\t\tPMD_INIT_LOG(ERR, \"Invalid pool number in IOV mode with VMDQ RSS\");\n\t\treturn -EINVAL;\n\t}\n\n\tIXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);\n\n\treturn 0;\n}\n\nstatic int\nixgbe_config_vf_default(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tswitch (RTE_ETH_DEV_SRIOV(dev).active) {\n\tcase ETH_64_POOLS:\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MRQC,\n\t\t\tIXGBE_MRQC_VMDQEN);\n\t\tbreak;\n\n\tcase ETH_32_POOLS:\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MRQC,\n\t\t\tIXGBE_MRQC_VMDQRT4TCEN);\n\t\tbreak;\n\n\tcase ETH_16_POOLS:\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MRQC,\n\t\t\tIXGBE_MRQC_VMDQRT8TCEN);\n\t\tbreak;\n\tdefault:\n\t\tPMD_INIT_LOG(ERR,\n\t\t\t\"invalid pool number in IOV mode\");\n\t\tbreak;\n\t}\n\treturn 0;\n}\n\nstatic int\nixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\treturn 0;\n\n\tif (RTE_ETH_DEV_SRIOV(dev).active == 0) {\n\t\t/*\n\t\t * SRIOV inactive scheme\n\t\t * any DCB/RSS w/o VMDq multi-queue setting\n\t\t */\n\t\tswitch (dev->data->dev_conf.rxmode.mq_mode) {\n\t\t\tcase ETH_MQ_RX_RSS:\n\t\t\t\tixgbe_rss_configure(dev);\n\t\t\t\tbreak;\n\n\t\t\tcase ETH_MQ_RX_VMDQ_DCB:\n\t\t\t\tixgbe_vmdq_dcb_configure(dev);\n\t\t\t\tbreak;\n\n\t\t\tcase ETH_MQ_RX_VMDQ_ONLY:\n\t\t\t\tixgbe_vmdq_rx_hw_configure(dev);\n\t\t\t\tbreak;\n\n\t\t\tcase ETH_MQ_RX_NONE:\n\t\t\t\t/* if mq_mode is none, disable rss mode.*/\n\t\t\tdefault: ixgbe_rss_disable(dev);\n\t\t}\n\t} else {\n\t\t/*\n\t\t * SRIOV active scheme\n\t\t * Support RSS together with VMDq & SRIOV\n\t\t */\n\t\tswitch (dev->data->dev_conf.rxmode.mq_mode) {\n\t\tcase ETH_MQ_RX_RSS:\n\t\tcase ETH_MQ_RX_VMDQ_RSS:\n\t\t\tixgbe_config_vf_rss(dev);\n\t\t\tbreak;\n\n\t\t/* FIXME if support DCB/RSS together with VMDq & SRIOV */\n\t\tcase ETH_MQ_RX_VMDQ_DCB:\n\t\tcase ETH_MQ_RX_VMDQ_DCB_RSS:\n\t\t\tPMD_INIT_LOG(ERR,\n\t\t\t\t\"Could not support DCB with VMDq & SRIOV\");\n\t\t\treturn -1;\n\t\tdefault:\n\t\t\tixgbe_config_vf_default(dev);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\nixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw =\n\t\tIXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tuint32_t mtqc;\n\tuint32_t rttdcs;\n\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\treturn 0;\n\n\t/* disable arbiter before setting MTQC */\n\trttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);\n\trttdcs |= IXGBE_RTTDCS_ARBDIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);\n\n\tif (RTE_ETH_DEV_SRIOV(dev).active == 0) {\n\t\t/*\n\t\t * SRIOV inactive scheme\n\t\t * any DCB w/o VMDq multi-queue setting\n\t\t */\n\t\tif (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)\n\t\t\tixgbe_vmdq_tx_hw_configure(hw);\n\t\telse {\n\t\t\tmtqc = IXGBE_MTQC_64Q_1PB;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);\n\t\t}\n\t} else {\n\t\tswitch (RTE_ETH_DEV_SRIOV(dev).active) {\n\n\t\t/*\n\t\t * SRIOV active scheme\n\t\t * FIXME if support DCB together with VMDq & SRIOV\n\t\t */\n\t\tcase ETH_64_POOLS:\n\t\t\tmtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;\n\t\t\tbreak;\n\t\tcase ETH_32_POOLS:\n\t\t\tmtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;\n\t\t\tbreak;\n\t\tcase ETH_16_POOLS:\n\t\t\tmtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |\n\t\t\t\tIXGBE_MTQC_8TC_8TQ;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tmtqc = IXGBE_MTQC_64Q_1PB;\n\t\t\tPMD_INIT_LOG(ERR, \"invalid pool number in IOV mode\");\n\t\t}\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);\n\t}\n\n\t/* re-enable arbiter */\n\trttdcs &= ~IXGBE_RTTDCS_ARBDIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF\n *\n * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the\n * spec rev. 3.0 chapter 8.2.3.8.13.\n *\n * @pool Memory pool of the Rx queue\n */\nstatic inline uint32_t\nixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)\n{\n\tstruct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);\n\n\t/* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */\n\tuint16_t maxdesc =\n\t\tIPV4_MAX_PKT_LEN /\n\t\t\t(mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);\n\n\tif (maxdesc >= 16)\n\t\treturn IXGBE_RSCCTL_MAXDESC_16;\n\telse if (maxdesc >= 8)\n\t\treturn IXGBE_RSCCTL_MAXDESC_8;\n\telse if (maxdesc >= 4)\n\t\treturn IXGBE_RSCCTL_MAXDESC_4;\n\telse\n\t\treturn IXGBE_RSCCTL_MAXDESC_1;\n}\n\n/**\n * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX\n * interrupt\n *\n * (Taken from FreeBSD tree)\n * (yes this is all very magic and confusing :)\n *\n * @dev port handle\n * @entry the register array entry\n * @vector the MSIX vector for this queue\n * @type RX/TX/MISC\n */\nstatic void\nixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)\n{\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tu32 ivar, index;\n\n\tvector |= IXGBE_IVAR_ALLOC_VAL;\n\n\tswitch (hw->mac.type) {\n\n\tcase ixgbe_mac_82598EB:\n\t\tif (type == -1)\n\t\t\tentry = IXGBE_IVAR_OTHER_CAUSES_INDEX;\n\t\telse\n\t\t\tentry += (type * 64);\n\t\tindex = (entry >> 2) & 0x1F;\n\t\tivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));\n\t\tivar &= ~(0xFF << (8 * (entry & 0x3)));\n\t\tivar |= (vector << (8 * (entry & 0x3)));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);\n\t\tbreak;\n\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\t\tif (type == -1) { /* MISC IVAR */\n\t\t\tindex = (entry & 1) * 8;\n\t\t\tivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);\n\t\t\tivar &= ~(0xFF << index);\n\t\t\tivar |= (vector << index);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);\n\t\t} else {\t/* RX/TX IVARS */\n\t\t\tindex = (16 * (entry & 1)) + (8 * type);\n\t\t\tivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));\n\t\t\tivar &= ~(0xFF << index);\n\t\t\tivar |= (vector << index);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);\n\t\t}\n\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n}\n\nvoid __attribute__((cold))\nixgbe_set_rx_function(struct rte_eth_dev *dev)\n{\n\tuint16_t i, rx_using_sse;\n\tstruct ixgbe_adapter *adapter =\n\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n\n\t/*\n\t * In order to allow Vector Rx there are a few configuration\n\t * conditions to be met and Rx Bulk Allocation should be allowed.\n\t */\n\tif (ixgbe_rx_vec_dev_conf_condition_check(dev) ||\n\t !adapter->rx_bulk_alloc_allowed) {\n\t\tPMD_INIT_LOG(DEBUG, \"Port[%d] doesn't meet Vector Rx \"\n\t\t\t\t \"preconditions or RTE_IXGBE_INC_VECTOR is \"\n\t\t\t\t \"not enabled\",\n\t\t\t dev->data->port_id);\n\n\t\tadapter->rx_vec_allowed = false;\n\t}\n\n\t/*\n\t * Initialize the appropriate LRO callback.\n\t *\n\t * If all queues satisfy the bulk allocation preconditions\n\t * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.\n\t * Otherwise use a single allocation version.\n\t */\n\tif (dev->data->lro) {\n\t\tif (adapter->rx_bulk_alloc_allowed) {\n\t\t\tPMD_INIT_LOG(DEBUG, \"LRO is requested. Using a bulk \"\n\t\t\t\t\t \"allocation version\");\n\t\t\tdev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;\n\t\t} else {\n\t\t\tPMD_INIT_LOG(DEBUG, \"LRO is requested. Using a single \"\n\t\t\t\t\t \"allocation version\");\n\t\t\tdev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;\n\t\t}\n\t} else if (dev->data->scattered_rx) {\n\t\t/*\n\t\t * Set the non-LRO scattered callback: there are Vector and\n\t\t * single allocation versions.\n\t\t */\n\t\tif (adapter->rx_vec_allowed) {\n\t\t\tPMD_INIT_LOG(DEBUG, \"Using Vector Scattered Rx \"\n\t\t\t\t\t \"callback (port=%d).\",\n\t\t\t\t dev->data->port_id);\n\n\t\t\tdev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;\n\t\t} else if (adapter->rx_bulk_alloc_allowed) {\n\t\t\tPMD_INIT_LOG(DEBUG, \"Using a Scattered with bulk \"\n\t\t\t\t\t \"allocation callback (port=%d).\",\n\t\t\t\t dev->data->port_id);\n\t\t\tdev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;\n\t\t} else {\n\t\t\tPMD_INIT_LOG(DEBUG, \"Using Regualr (non-vector, \"\n\t\t\t\t\t \"single allocation) \"\n\t\t\t\t\t \"Scattered Rx callback \"\n\t\t\t\t\t \"(port=%d).\",\n\t\t\t\t dev->data->port_id);\n\n\t\t\tdev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;\n\t\t}\n\t/*\n\t * Below we set \"simple\" callbacks according to port/queues parameters.\n\t * If parameters allow we are going to choose between the following\n\t * callbacks:\n\t * - Vector\n\t * - Bulk Allocation\n\t * - Single buffer allocation (the simplest one)\n\t */\n\t} else if (adapter->rx_vec_allowed) {\n\t\tPMD_INIT_LOG(DEBUG, \"Vector rx enabled, please make sure RX \"\n\t\t\t\t \"burst size no less than 32.\");\n\n\t\tdev->rx_pkt_burst = ixgbe_recv_pkts_vec;\n\t} else if (adapter->rx_bulk_alloc_allowed) {\n\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions are \"\n\t\t\t\t \"satisfied. Rx Burst Bulk Alloc function \"\n\t\t\t\t \"will be used on port=%d.\",\n\t\t\t dev->data->port_id);\n\n\t\tdev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;\n\t} else {\n\t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions are not \"\n\t\t\t\t \"satisfied, or Scattered Rx is requested \"\n\t\t\t\t \"(port=%d).\",\n\t\t\t dev->data->port_id);\n\n\t\tdev->rx_pkt_burst = ixgbe_recv_pkts;\n\t}\n\n\t/* Propagate information about RX function choice through all queues. */\n\n\trx_using_sse =\n\t\t(dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec ||\n\t\tdev->rx_pkt_burst == ixgbe_recv_pkts_vec);\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tstruct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];\n\t\trxq->rx_using_sse = rx_using_sse;\n\t}\n}\n\n/**\n * ixgbe_set_rsc - configure RSC related port HW registers\n *\n * Configures the port's RSC related registers according to the 4.6.7.2 chapter\n * of 82599 Spec (x540 configuration is virtually the same).\n *\n * @dev port handle\n *\n * Returns 0 in case of success or a non-zero error code\n */\nstatic int\nixgbe_set_rsc(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;\n\tstruct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\tstruct rte_eth_dev_info dev_info = { 0 };\n\tbool rsc_capable = false;\n\tuint16_t i;\n\tuint32_t rdrxctl;\n\n\t/* Sanity check */\n\tdev->dev_ops->dev_infos_get(dev, &dev_info);\n\tif (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)\n\t\trsc_capable = true;\n\n\tif (!rsc_capable && rx_conf->enable_lro) {\n\t\tPMD_INIT_LOG(CRIT, \"LRO is requested on HW that doesn't \"\n\t\t\t\t \"support it\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */\n\n\tif (!rx_conf->hw_strip_crc && rx_conf->enable_lro) {\n\t\t/*\n\t\t * According to chapter of 4.6.7.2.1 of the Spec Rev.\n\t\t * 3.0 RSC configuration requires HW CRC stripping being\n\t\t * enabled. If user requested both HW CRC stripping off\n\t\t * and RSC on - return an error.\n\t\t */\n\t\tPMD_INIT_LOG(CRIT, \"LRO can't be enabled when HW CRC \"\n\t\t\t\t \"is disabled\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* RFCTL configuration */\n\tif (rsc_capable) {\n\t\tuint32_t rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);\n\t\tif (rx_conf->enable_lro)\n\t\t\t/*\n\t\t\t * Since NFS packets coalescing is not supported - clear\n\t\t\t * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is\n\t\t\t * enabled.\n\t\t\t */\n\t\t\trfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |\n\t\t\t\t IXGBE_RFCTL_NFSR_DIS);\n\t\telse\n\t\t\trfctl |= IXGBE_RFCTL_RSC_DIS;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);\n\t}\n\n\t/* If LRO hasn't been requested - we are done here. */\n\tif (!rx_conf->enable_lro)\n\t\treturn 0;\n\n\t/* Set RDRXCTL.RSCACKC bit */\n\trdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);\n\trdrxctl |= IXGBE_RDRXCTL_RSCACKC;\n\tIXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);\n\n\t/* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tstruct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];\n\t\tuint32_t srrctl =\n\t\t\tIXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));\n\t\tuint32_t rscctl =\n\t\t\tIXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));\n\t\tuint32_t psrtype =\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));\n\t\tuint32_t eitr =\n\t\t\tIXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));\n\n\t\t/*\n\t\t * ixgbe PMD doesn't support header-split at the moment.\n\t\t *\n\t\t * Following the 4.6.7.2.1 chapter of the 82599/x540\n\t\t * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER\n\t\t * should be configured even if header split is not\n\t\t * enabled. We will configure it 128 bytes following the\n\t\t * recommendation in the spec.\n\t\t */\n\t\tsrrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;\n\t\tsrrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &\n\t\t\t\t\t IXGBE_SRRCTL_BSIZEHDR_MASK;\n\n\t\t/*\n\t\t * TODO: Consider setting the Receive Descriptor Minimum\n\t\t * Threshold Size for an RSC case. This is not an obviously\n\t\t * beneficiary option but the one worth considering...\n\t\t */\n\n\t\trscctl |= IXGBE_RSCCTL_RSCEN;\n\t\trscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);\n\t\tpsrtype |= IXGBE_PSRTYPE_TCPHDR;\n\n\t\t/*\n\t\t * RSC: Set ITR interval corresponding to 2K ints/s.\n\t\t *\n\t\t * Full-sized RSC aggregations for a 10Gb/s link will\n\t\t * arrive at about 20K aggregation/s rate.\n\t\t *\n\t\t * 2K inst/s rate will make only 10% of the\n\t\t * aggregations to be closed due to the interrupt timer\n\t\t * expiration for a streaming at wire-speed case.\n\t\t *\n\t\t * For a sparse streaming case this setting will yield\n\t\t * at most 500us latency for a single RSC aggregation.\n\t\t */\n\t\teitr &= ~IXGBE_EITR_ITR_INT_MASK;\n\t\teitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);\n\n\t\t/*\n\t\t * RSC requires the mapping of the queue to the\n\t\t * interrupt vector.\n\t\t */\n\t\tixgbe_set_ivar(dev, rxq->reg_idx, i, 0);\n\t}\n\n\tdev->data->lro = 1;\n\n\tPMD_INIT_LOG(DEBUG, \"enabling LRO mode\");\n\n\treturn 0;\n}\n\n/*\n * Initializes Receive Unit.\n */\nint __attribute__((cold))\nixgbe_dev_rx_init(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw;\n\tstruct ixgbe_rx_queue *rxq;\n\tuint64_t bus_addr;\n\tuint32_t rxctrl;\n\tuint32_t fctrl;\n\tuint32_t hlreg0;\n\tuint32_t maxfrs;\n\tuint32_t srrctl;\n\tuint32_t rdrxctl;\n\tuint32_t rxcsum;\n\tuint16_t buf_size;\n\tuint16_t i;\n\tstruct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;\n\tint rc;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/*\n\t * Make sure receives are disabled while setting\n\t * up the RX context (registers, descriptor rings, etc.).\n\t */\n\trxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n\tIXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);\n\n\t/* Enable receipt of broadcasted frames */\n\tfctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\tfctrl |= IXGBE_FCTRL_BAM;\n\tfctrl |= IXGBE_FCTRL_DPF;\n\tfctrl |= IXGBE_FCTRL_PMCF;\n\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);\n\n\t/*\n\t * Configure CRC stripping, if any.\n\t */\n\thlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);\n\tif (rx_conf->hw_strip_crc)\n\t\thlreg0 |= IXGBE_HLREG0_RXCRCSTRP;\n\telse\n\t\thlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;\n\n\t/*\n\t * Configure jumbo frame support, if any.\n\t */\n\tif (rx_conf->jumbo_frame == 1) {\n\t\thlreg0 |= IXGBE_HLREG0_JUMBOEN;\n\t\tmaxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);\n\t\tmaxfrs &= 0x0000FFFF;\n\t\tmaxfrs |= (rx_conf->max_rx_pkt_len << 16);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);\n\t} else\n\t\thlreg0 &= ~IXGBE_HLREG0_JUMBOEN;\n\n\t/*\n\t * If loopback mode is configured for 82599, set LPBK bit.\n\t */\n\tif (hw->mac.type == ixgbe_mac_82599EB &&\n\t\t\tdev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)\n\t\thlreg0 |= IXGBE_HLREG0_LPBK;\n\telse\n\t\thlreg0 &= ~IXGBE_HLREG0_LPBK;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);\n\n\t/* Setup RX queues */\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\trxq = dev->data->rx_queues[i];\n\n\t\t/*\n\t\t * Reset crc_len in case it was changed after queue setup by a\n\t\t * call to configure.\n\t\t */\n\t\trxq->crc_len = rx_conf->hw_strip_crc ? 0 : ETHER_CRC_LEN;\n\n\t\t/* Setup the Base and Length of the Rx Descriptor Rings */\n\t\tbus_addr = rxq->rx_ring_phys_addr;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),\n\t\t\t\t(uint32_t)(bus_addr & 0x00000000ffffffffULL));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),\n\t\t\t\t(uint32_t)(bus_addr >> 32));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),\n\t\t\t\trxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);\n\n\t\t/* Configure the SRRCTL register */\n#ifdef RTE_HEADER_SPLIT_ENABLE\n\t\t/*\n\t\t * Configure Header Split\n\t\t */\n\t\tif (rx_conf->header_split) {\n\t\t\tif (hw->mac.type == ixgbe_mac_82599EB) {\n\t\t\t\t/* Must setup the PSRTYPE register */\n\t\t\t\tuint32_t psrtype;\n\t\t\t\tpsrtype = IXGBE_PSRTYPE_TCPHDR |\n\t\t\t\t\tIXGBE_PSRTYPE_UDPHDR |\n\t\t\t\t\tIXGBE_PSRTYPE_IPV4HDR |\n\t\t\t\t\tIXGBE_PSRTYPE_IPV6HDR;\n\t\t\t\tIXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);\n\t\t\t}\n\t\t\tsrrctl = ((rx_conf->split_hdr_size <<\n\t\t\t\tIXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &\n\t\t\t\tIXGBE_SRRCTL_BSIZEHDR_MASK);\n\t\t\tsrrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;\n\t\t} else\n#endif\n\t\t\tsrrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;\n\n\t\t/* Set if packets are dropped when no descriptors available */\n\t\tif (rxq->drop_en)\n\t\t\tsrrctl |= IXGBE_SRRCTL_DROP_EN;\n\n\t\t/*\n\t\t * Configure the RX buffer size in the BSIZEPACKET field of\n\t\t * the SRRCTL register of the queue.\n\t\t * The value is in 1 KB resolution. Valid values can be from\n\t\t * 1 KB to 16 KB.\n\t\t */\n\t\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -\n\t\t\tRTE_PKTMBUF_HEADROOM);\n\t\tsrrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &\n\t\t\t IXGBE_SRRCTL_BSIZEPKT_MASK);\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);\n\n\t\tbuf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<\n\t\t\t\t IXGBE_SRRCTL_BSIZEPKT_SHIFT);\n\n\t\t/* It adds dual VLAN length for supporting dual VLAN */\n\t\tif (dev->data->dev_conf.rxmode.max_rx_pkt_len +\n\t\t\t\t\t 2 * IXGBE_VLAN_TAG_SIZE > buf_size)\n\t\t\tdev->data->scattered_rx = 1;\n\t}\n\n\tif (rx_conf->enable_scatter)\n\t\tdev->data->scattered_rx = 1;\n\n\t/*\n\t * Device configured with multiple RX queues.\n\t */\n\tixgbe_dev_mq_rx_configure(dev);\n\n\t/*\n\t * Setup the Checksum Register.\n\t * Disable Full-Packet Checksum which is mutually exclusive with RSS.\n\t * Enable IP/L4 checkum computation by hardware if requested to do so.\n\t */\n\trxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);\n\trxcsum |= IXGBE_RXCSUM_PCSD;\n\tif (rx_conf->hw_ip_checksum)\n\t\trxcsum |= IXGBE_RXCSUM_IPPCSE;\n\telse\n\t\trxcsum &= ~IXGBE_RXCSUM_IPPCSE;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);\n\n\tif (hw->mac.type == ixgbe_mac_82599EB ||\n\t hw->mac.type == ixgbe_mac_X540) {\n\t\trdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);\n\t\tif (rx_conf->hw_strip_crc)\n\t\t\trdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;\n\t\telse\n\t\t\trdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;\n\t\trdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);\n\t}\n\n\trc = ixgbe_set_rsc(dev);\n\tif (rc)\n\t\treturn rc;\n\n\tixgbe_set_rx_function(dev);\n\n\treturn 0;\n}\n\n/*\n * Initializes Transmit Unit.\n */\nvoid __attribute__((cold))\nixgbe_dev_tx_init(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw;\n\tstruct ixgbe_tx_queue *txq;\n\tuint64_t bus_addr;\n\tuint32_t hlreg0;\n\tuint32_t txctrl;\n\tuint16_t i;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/* Enable TX CRC (checksum offload requirement) and hw padding\n\t * (TSO requirement) */\n\thlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);\n\thlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);\n\tIXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);\n\n\t/* Setup the Base and Length of the Tx Descriptor Rings */\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\ttxq = dev->data->tx_queues[i];\n\n\t\tbus_addr = txq->tx_ring_phys_addr;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),\n\t\t\t\t(uint32_t)(bus_addr & 0x00000000ffffffffULL));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),\n\t\t\t\t(uint32_t)(bus_addr >> 32));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),\n\t\t\t\ttxq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));\n\t\t/* Setup the HW Tx Head and TX Tail descriptor pointers */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);\n\n\t\t/*\n\t\t * Disable Tx Head Writeback RO bit, since this hoses\n\t\t * bookkeeping if things aren't delivered in order.\n\t\t */\n\t\tswitch (hw->mac.type) {\n\t\t\tcase ixgbe_mac_82598EB:\n\t\t\t\ttxctrl = IXGBE_READ_REG(hw,\n\t\t\t\t\t\t\tIXGBE_DCA_TXCTRL(txq->reg_idx));\n\t\t\t\ttxctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;\n\t\t\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),\n\t\t\t\t\t\ttxctrl);\n\t\t\t\tbreak;\n\n\t\t\tcase ixgbe_mac_82599EB:\n\t\t\tcase ixgbe_mac_X540:\n\t\t\tcase ixgbe_mac_X550:\n\t\t\tcase ixgbe_mac_X550EM_x:\n\t\t\tdefault:\n\t\t\t\ttxctrl = IXGBE_READ_REG(hw,\n\t\t\t\t\t\tIXGBE_DCA_TXCTRL_82599(txq->reg_idx));\n\t\t\t\ttxctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;\n\t\t\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),\n\t\t\t\t\t\ttxctrl);\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Device configured with multiple TX queues. */\n\tixgbe_dev_mq_tx_configure(dev);\n}\n\n/*\n * Set up link for 82599 loopback mode Tx->Rx.\n */\nstatic inline void __attribute__((cold))\nixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (ixgbe_verify_lesm_fw_enabled_82599(hw)) {\n\t\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=\n\t\t\t\tIXGBE_SUCCESS) {\n\t\t\tPMD_INIT_LOG(ERR, \"Could not enable loopback mode\");\n\t\t\t/* ignore error */\n\t\t\treturn;\n\t\t}\n\t}\n\n\t/* Restart link */\n\tIXGBE_WRITE_REG(hw,\n\t\t\tIXGBE_AUTOC,\n\t\t\tIXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);\n\tixgbe_reset_pipeline_82599(hw);\n\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);\n\tmsec_delay(50);\n}\n\n\n/*\n * Start Transmit and Receive Units.\n */\nint __attribute__((cold))\nixgbe_dev_rxtx_start(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw;\n\tstruct ixgbe_tx_queue *txq;\n\tstruct ixgbe_rx_queue *rxq;\n\tuint32_t txdctl;\n\tuint32_t dmatxctl;\n\tuint32_t rxctrl;\n\tuint16_t i;\n\tint ret = 0;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\ttxq = dev->data->tx_queues[i];\n\t\t/* Setup Transmit Threshold Registers */\n\t\ttxdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));\n\t\ttxdctl |= txq->pthresh & 0x7F;\n\t\ttxdctl |= ((txq->hthresh & 0x7F) << 8);\n\t\ttxdctl |= ((txq->wthresh & 0x7F) << 16);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);\n\t}\n\n\tif (hw->mac.type != ixgbe_mac_82598EB) {\n\t\tdmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);\n\t\tdmatxctl |= IXGBE_DMATXCTL_TE;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);\n\t}\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\ttxq = dev->data->tx_queues[i];\n\t\tif (!txq->tx_deferred_start) {\n\t\t\tret = ixgbe_dev_tx_queue_start(dev, i);\n\t\t\tif (ret < 0)\n\t\t\t\treturn ret;\n\t\t}\n\t}\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\trxq = dev->data->rx_queues[i];\n\t\tif (!rxq->rx_deferred_start) {\n\t\t\tret = ixgbe_dev_rx_queue_start(dev, i);\n\t\t\tif (ret < 0)\n\t\t\t\treturn ret;\n\t\t}\n\t}\n\n\t/* Enable Receive engine */\n\trxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\trxctrl |= IXGBE_RXCTRL_DMBYPS;\n\trxctrl |= IXGBE_RXCTRL_RXEN;\n\thw->mac.ops.enable_rx_dma(hw, rxctrl);\n\n\t/* If loopback mode is enabled for 82599, set up the link accordingly */\n\tif (hw->mac.type == ixgbe_mac_82599EB &&\n\t\t\tdev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)\n\t\tixgbe_setup_loopback_link_82599(hw);\n\n\treturn 0;\n}\n\n/*\n * Start Receive Units for specified queue.\n */\nint __attribute__((cold))\nixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n{\n\tstruct ixgbe_hw *hw;\n\tstruct ixgbe_rx_queue *rxq;\n\tuint32_t rxdctl;\n\tint poll_ms;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (rx_queue_id < dev->data->nb_rx_queues) {\n\t\trxq = dev->data->rx_queues[rx_queue_id];\n\n\t\t/* Allocate buffers for descriptor rings */\n\t\tif (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {\n\t\t\tPMD_INIT_LOG(ERR, \"Could not alloc mbuf for queue:%d\",\n\t\t\t\t rx_queue_id);\n\t\t\treturn -1;\n\t\t}\n\t\trxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));\n\t\trxdctl |= IXGBE_RXDCTL_ENABLE;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);\n\n\t\t/* Wait until RX Enable ready */\n\t\tpoll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;\n\t\tdo {\n\t\t\trte_delay_ms(1);\n\t\t\trxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));\n\t\t} while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));\n\t\tif (!poll_ms)\n\t\t\tPMD_INIT_LOG(ERR, \"Could not enable Rx Queue %d\",\n\t\t\t\t rx_queue_id);\n\t\trte_wmb();\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);\n\t} else\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * Stop Receive Units for specified queue.\n */\nint __attribute__((cold))\nixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n{\n\tstruct ixgbe_hw *hw;\n\tstruct ixgbe_adapter *adapter =\n\t\t(struct ixgbe_adapter *)dev->data->dev_private;\n\tstruct ixgbe_rx_queue *rxq;\n\tuint32_t rxdctl;\n\tint poll_ms;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (rx_queue_id < dev->data->nb_rx_queues) {\n\t\trxq = dev->data->rx_queues[rx_queue_id];\n\n\t\trxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));\n\t\trxdctl &= ~IXGBE_RXDCTL_ENABLE;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);\n\n\t\t/* Wait until RX Enable ready */\n\t\tpoll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;\n\t\tdo {\n\t\t\trte_delay_ms(1);\n\t\t\trxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));\n\t\t} while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));\n\t\tif (!poll_ms)\n\t\t\tPMD_INIT_LOG(ERR, \"Could not disable Rx Queue %d\",\n\t\t\t\t rx_queue_id);\n\n\t\trte_delay_us(RTE_IXGBE_WAIT_100_US);\n\n\t\tixgbe_rx_queue_release_mbufs(rxq);\n\t\tixgbe_reset_rx_queue(adapter, rxq);\n\t} else\n\t\treturn -1;\n\n\treturn 0;\n}\n\n\n/*\n * Start Transmit Units for specified queue.\n */\nint __attribute__((cold))\nixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n{\n\tstruct ixgbe_hw *hw;\n\tstruct ixgbe_tx_queue *txq;\n\tuint32_t txdctl;\n\tint poll_ms;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (tx_queue_id < dev->data->nb_tx_queues) {\n\t\ttxq = dev->data->tx_queues[tx_queue_id];\n\t\ttxdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));\n\t\ttxdctl |= IXGBE_TXDCTL_ENABLE;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);\n\n\t\t/* Wait until TX Enable ready */\n\t\tif (hw->mac.type == ixgbe_mac_82599EB) {\n\t\t\tpoll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;\n\t\t\tdo {\n\t\t\t\trte_delay_ms(1);\n\t\t\t\ttxdctl = IXGBE_READ_REG(hw,\n\t\t\t\t\tIXGBE_TXDCTL(txq->reg_idx));\n\t\t\t} while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));\n\t\t\tif (!poll_ms)\n\t\t\t\tPMD_INIT_LOG(ERR, \"Could not enable \"\n\t\t\t\t\t \"Tx Queue %d\", tx_queue_id);\n\t\t}\n\t\trte_wmb();\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);\n\t} else\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * Stop Transmit Units for specified queue.\n */\nint __attribute__((cold))\nixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n{\n\tstruct ixgbe_hw *hw;\n\tstruct ixgbe_tx_queue *txq;\n\tuint32_t txdctl;\n\tuint32_t txtdh, txtdt;\n\tint poll_ms;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (tx_queue_id < dev->data->nb_tx_queues) {\n\t\ttxq = dev->data->tx_queues[tx_queue_id];\n\n\t\t/* Wait until TX queue is empty */\n\t\tif (hw->mac.type == ixgbe_mac_82599EB) {\n\t\t\tpoll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;\n\t\t\tdo {\n\t\t\t\trte_delay_us(RTE_IXGBE_WAIT_100_US);\n\t\t\t\ttxtdh = IXGBE_READ_REG(hw,\n\t\t\t\t\t\tIXGBE_TDH(txq->reg_idx));\n\t\t\t\ttxtdt = IXGBE_READ_REG(hw,\n\t\t\t\t\t\tIXGBE_TDT(txq->reg_idx));\n\t\t\t} while (--poll_ms && (txtdh != txtdt));\n\t\t\tif (!poll_ms)\n\t\t\t\tPMD_INIT_LOG(ERR, \"Tx Queue %d is not empty \"\n\t\t\t\t\t \"when stopping.\", tx_queue_id);\n\t\t}\n\n\t\ttxdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));\n\t\ttxdctl &= ~IXGBE_TXDCTL_ENABLE;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);\n\n\t\t/* Wait until TX Enable ready */\n\t\tif (hw->mac.type == ixgbe_mac_82599EB) {\n\t\t\tpoll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;\n\t\t\tdo {\n\t\t\t\trte_delay_ms(1);\n\t\t\t\ttxdctl = IXGBE_READ_REG(hw,\n\t\t\t\t\t\tIXGBE_TXDCTL(txq->reg_idx));\n\t\t\t} while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));\n\t\t\tif (!poll_ms)\n\t\t\t\tPMD_INIT_LOG(ERR, \"Could not disable \"\n\t\t\t\t\t \"Tx Queue %d\", tx_queue_id);\n\t\t}\n\n\t\tif (txq->ops != NULL) {\n\t\t\ttxq->ops->release_mbufs(txq);\n\t\t\ttxq->ops->reset(txq);\n\t\t}\n\t} else\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * [VF] Initializes Receive Unit.\n */\nint __attribute__((cold))\nixgbevf_dev_rx_init(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw;\n\tstruct ixgbe_rx_queue *rxq;\n\tuint64_t bus_addr;\n\tuint32_t srrctl, psrtype = 0;\n\tuint16_t buf_size;\n\tuint16_t i;\n\tint ret;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tif (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {\n\t\tPMD_INIT_LOG(ERR, \"The number of Rx queue invalid, \"\n\t\t\t\"it should be power of 2\");\n\t\treturn -1;\n\t}\n\n\tif (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {\n\t\tPMD_INIT_LOG(ERR, \"The number of Rx queue invalid, \"\n\t\t\t\"it should be equal to or less than %d\",\n\t\t\thw->mac.max_rx_queues);\n\t\treturn -1;\n\t}\n\n\t/*\n\t * When the VF driver issues a IXGBE_VF_RESET request, the PF driver\n\t * disables the VF receipt of packets if the PF MTU is > 1500.\n\t * This is done to deal with 82599 limitations that imposes\n\t * the PF and all VFs to share the same MTU.\n\t * Then, the PF driver enables again the VF receipt of packet when\n\t * the VF driver issues a IXGBE_VF_SET_LPE request.\n\t * In the meantime, the VF device cannot be used, even if the VF driver\n\t * and the Guest VM network stack are ready to accept packets with a\n\t * size up to the PF MTU.\n\t * As a work-around to this PF behaviour, force the call to\n\t * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,\n\t * VF packets received can work in all cases.\n\t */\n\tixgbevf_rlpml_set_vf(hw,\n\t\t(uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);\n\n\t/* Setup RX queues */\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\trxq = dev->data->rx_queues[i];\n\n\t\t/* Allocate buffers for descriptor rings */\n\t\tret = ixgbe_alloc_rx_queue_mbufs(rxq);\n\t\tif (ret)\n\t\t\treturn ret;\n\n\t\t/* Setup the Base and Length of the Rx Descriptor Rings */\n\t\tbus_addr = rxq->rx_ring_phys_addr;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),\n\t\t\t\t(uint32_t)(bus_addr & 0x00000000ffffffffULL));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),\n\t\t\t\t(uint32_t)(bus_addr >> 32));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),\n\t\t\t\trxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);\n\n\n\t\t/* Configure the SRRCTL register */\n#ifdef RTE_HEADER_SPLIT_ENABLE\n\t\t/*\n\t\t * Configure Header Split\n\t\t */\n\t\tif (dev->data->dev_conf.rxmode.header_split) {\n\t\t\tsrrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<\n\t\t\t\tIXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &\n\t\t\t\tIXGBE_SRRCTL_BSIZEHDR_MASK);\n\t\t\tsrrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;\n\t\t} else\n#endif\n\t\t\tsrrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;\n\n\t\t/* Set if packets are dropped when no descriptors available */\n\t\tif (rxq->drop_en)\n\t\t\tsrrctl |= IXGBE_SRRCTL_DROP_EN;\n\n\t\t/*\n\t\t * Configure the RX buffer size in the BSIZEPACKET field of\n\t\t * the SRRCTL register of the queue.\n\t\t * The value is in 1 KB resolution. Valid values can be from\n\t\t * 1 KB to 16 KB.\n\t\t */\n\t\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -\n\t\t\tRTE_PKTMBUF_HEADROOM);\n\t\tsrrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &\n\t\t\t IXGBE_SRRCTL_BSIZEPKT_MASK);\n\n\t\t/*\n\t\t * VF modification to write virtual function SRRCTL register\n\t\t */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);\n\n\t\tbuf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<\n\t\t\t\t IXGBE_SRRCTL_BSIZEPKT_SHIFT);\n\n\t\tif (dev->data->dev_conf.rxmode.enable_scatter ||\n\t\t /* It adds dual VLAN length for supporting dual VLAN */\n\t\t (dev->data->dev_conf.rxmode.max_rx_pkt_len +\n\t\t\t\t2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {\n\t\t\tif (!dev->data->scattered_rx)\n\t\t\t\tPMD_INIT_LOG(DEBUG, \"forcing scatter mode\");\n\t\t\tdev->data->scattered_rx = 1;\n\t\t}\n\t}\n\n#ifdef RTE_HEADER_SPLIT_ENABLE\n\tif (dev->data->dev_conf.rxmode.header_split)\n\t\t/* Must setup the PSRTYPE register */\n\t\tpsrtype = IXGBE_PSRTYPE_TCPHDR |\n\t\t\tIXGBE_PSRTYPE_UDPHDR |\n\t\t\tIXGBE_PSRTYPE_IPV4HDR |\n\t\t\tIXGBE_PSRTYPE_IPV6HDR;\n#endif\n\n\t/* Set RQPL for VF RSS according to max Rx queue */\n\tpsrtype |= (dev->data->nb_rx_queues >> 1) <<\n\t\tIXGBE_PSRTYPE_RQPL_SHIFT;\n\tIXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);\n\n\tixgbe_set_rx_function(dev);\n\n\treturn 0;\n}\n\n/*\n * [VF] Initializes Transmit Unit.\n */\nvoid __attribute__((cold))\nixgbevf_dev_tx_init(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw;\n\tstruct ixgbe_tx_queue *txq;\n\tuint64_t bus_addr;\n\tuint32_t txctrl;\n\tuint16_t i;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\t/* Setup the Base and Length of the Tx Descriptor Rings */\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\ttxq = dev->data->tx_queues[i];\n\t\tbus_addr = txq->tx_ring_phys_addr;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),\n\t\t\t\t(uint32_t)(bus_addr & 0x00000000ffffffffULL));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),\n\t\t\t\t(uint32_t)(bus_addr >> 32));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),\n\t\t\t\ttxq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));\n\t\t/* Setup the HW Tx Head and TX Tail descriptor pointers */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);\n\n\t\t/*\n\t\t * Disable Tx Head Writeback RO bit, since this hoses\n\t\t * bookkeeping if things aren't delivered in order.\n\t\t */\n\t\ttxctrl = IXGBE_READ_REG(hw,\n\t\t\t\tIXGBE_VFDCA_TXCTRL(i));\n\t\ttxctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),\n\t\t\t\ttxctrl);\n\t}\n}\n\n/*\n * [VF] Start Transmit and Receive Units.\n */\nvoid __attribute__((cold))\nixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)\n{\n\tstruct ixgbe_hw *hw;\n\tstruct ixgbe_tx_queue *txq;\n\tstruct ixgbe_rx_queue *rxq;\n\tuint32_t txdctl;\n\tuint32_t rxdctl;\n\tuint16_t i;\n\tint poll_ms;\n\n\tPMD_INIT_FUNC_TRACE();\n\thw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\ttxq = dev->data->tx_queues[i];\n\t\t/* Setup Transmit Threshold Registers */\n\t\ttxdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));\n\t\ttxdctl |= txq->pthresh & 0x7F;\n\t\ttxdctl |= ((txq->hthresh & 0x7F) << 8);\n\t\ttxdctl |= ((txq->wthresh & 0x7F) << 16);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);\n\t}\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\n\t\ttxdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));\n\t\ttxdctl |= IXGBE_TXDCTL_ENABLE;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);\n\n\t\tpoll_ms = 10;\n\t\t/* Wait until TX Enable ready */\n\t\tdo {\n\t\t\trte_delay_ms(1);\n\t\t\ttxdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));\n\t\t} while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));\n\t\tif (!poll_ms)\n\t\t\tPMD_INIT_LOG(ERR, \"Could not enable Tx Queue %d\", i);\n\t}\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\n\t\trxq = dev->data->rx_queues[i];\n\n\t\trxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));\n\t\trxdctl |= IXGBE_RXDCTL_ENABLE;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);\n\n\t\t/* Wait until RX Enable ready */\n\t\tpoll_ms = 10;\n\t\tdo {\n\t\t\trte_delay_ms(1);\n\t\t\trxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));\n\t\t} while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));\n\t\tif (!poll_ms)\n\t\t\tPMD_INIT_LOG(ERR, \"Could not enable Rx Queue %d\", i);\n\t\trte_wmb();\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);\n\n\t}\n}\n\n/* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */\nint __attribute__((weak))\nixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)\n{\n\treturn -1;\n}\n\nuint16_t __attribute__((weak))\nixgbe_recv_pkts_vec(\n\tvoid __rte_unused *rx_queue,\n\tstruct rte_mbuf __rte_unused **rx_pkts,\n\tuint16_t __rte_unused nb_pkts)\n{\n\treturn 0;\n}\n\nuint16_t __attribute__((weak))\nixgbe_recv_scattered_pkts_vec(\n\tvoid __rte_unused *rx_queue,\n\tstruct rte_mbuf __rte_unused **rx_pkts,\n\tuint16_t __rte_unused nb_pkts)\n{\n\treturn 0;\n}\n\nint __attribute__((weak))\nixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)\n{\n\treturn -1;\n}\n" }, { "path": "drivers/net/ixgbe/ixgbe_rxtx.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _IXGBE_RXTX_H_\n#define _IXGBE_RXTX_H_\n\n\n#define RTE_PMD_IXGBE_TX_MAX_BURST 32\n#define RTE_PMD_IXGBE_RX_MAX_BURST 32\n\n#define RTE_IXGBE_DESCS_PER_LOOP 4\n\n#define RTE_MBUF_DATA_DMA_ADDR(mb) \\\n\t(uint64_t) ((mb)->buf_physaddr + (mb)->data_off)\n\n#define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \\\n\t(uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)\n\n#ifdef RTE_IXGBE_INC_VECTOR\n#define RTE_IXGBE_VPMD_RX_BURST 32\n#define RTE_IXGBE_VPMD_TX_BURST 32\n#define RTE_IXGBE_RXQ_REARM_THRESH RTE_IXGBE_VPMD_RX_BURST\n#define RTE_IXGBE_TX_MAX_FREE_BUF_SZ 64\n#endif\n\n#define RX_RING_SZ ((IXGBE_MAX_RING_DESC + RTE_IXGBE_DESCS_PER_LOOP - 1) * \\\n\t\t sizeof(union ixgbe_adv_rx_desc))\n\n#ifdef RTE_PMD_PACKET_PREFETCH\n#define rte_packet_prefetch(p) rte_prefetch1(p)\n#else\n#define rte_packet_prefetch(p) do {} while(0)\n#endif\n\n#define RTE_IXGBE_REGISTER_POLL_WAIT_10_MS 10\n#define RTE_IXGBE_WAIT_100_US 100\n#define RTE_IXGBE_VMTXSW_REGISTER_COUNT 2\n\n/**\n * Structure associated with each descriptor of the RX ring of a RX queue.\n */\nstruct ixgbe_rx_entry {\n\tstruct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */\n};\n\nstruct ixgbe_scattered_rx_entry {\n\tstruct rte_mbuf *fbuf; /**< First segment of the fragmented packet. */\n};\n\n/**\n * Structure associated with each descriptor of the TX ring of a TX queue.\n */\nstruct ixgbe_tx_entry {\n\tstruct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */\n\tuint16_t next_id; /**< Index of next descriptor in ring. */\n\tuint16_t last_id; /**< Index of last scattered descriptor. */\n};\n\n/**\n * Structure associated with each descriptor of the TX ring of a TX queue.\n */\nstruct ixgbe_tx_entry_v {\n\tstruct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */\n};\n\n/**\n * Structure associated with each RX queue.\n */\nstruct ixgbe_rx_queue {\n\tstruct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */\n\tvolatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */\n\tuint64_t rx_ring_phys_addr; /**< RX ring DMA address. */\n\tvolatile uint32_t *rdt_reg_addr; /**< RDT register address. */\n\tvolatile uint32_t *rdh_reg_addr; /**< RDH register address. */\n\tstruct ixgbe_rx_entry *sw_ring; /**< address of RX software ring. */\n\tstruct ixgbe_scattered_rx_entry *sw_sc_ring; /**< address of scattered Rx software ring. */\n\tstruct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */\n\tstruct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */\n\tuint64_t mbuf_initializer; /**< value to init mbufs */\n\tuint16_t nb_rx_desc; /**< number of RX descriptors. */\n\tuint16_t rx_tail; /**< current value of RDT register. */\n\tuint16_t nb_rx_hold; /**< number of held free RX desc. */\n\tuint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */\n\tuint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */\n\tuint16_t rx_free_trigger; /**< triggers rx buffer allocation */\n\tuint16_t rx_using_sse;\n\t/**< indicates that vector RX is in use */\n#ifdef RTE_IXGBE_INC_VECTOR\n\tuint16_t rxrearm_nb; /**< number of remaining to be re-armed */\n\tuint16_t rxrearm_start; /**< the idx we start the re-arming from */\n#endif\n\tuint16_t rx_free_thresh; /**< max free RX desc to hold. */\n\tuint16_t queue_id; /**< RX queue index. */\n\tuint16_t reg_idx; /**< RX queue register index. */\n\tuint8_t port_id; /**< Device port identifier. */\n\tuint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */\n\tuint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */\n\tuint8_t rx_deferred_start; /**< not in global dev start. */\n\t/** need to alloc dummy mbuf, for wraparound when scanning hw ring */\n\tstruct rte_mbuf fake_mbuf;\n\t/** hold packets to return to application */\n\tstruct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];\n};\n\n/**\n * IXGBE CTX Constants\n */\nenum ixgbe_advctx_num {\n\tIXGBE_CTX_0 = 0, /**< CTX0 */\n\tIXGBE_CTX_1 = 1, /**< CTX1 */\n\tIXGBE_CTX_NUM = 2, /**< CTX NUMBER */\n};\n\n/** Offload features */\nunion ixgbe_tx_offload {\n\tuint64_t data;\n\tstruct {\n\t\tuint64_t l2_len:7; /**< L2 (MAC) Header Length. */\n\t\tuint64_t l3_len:9; /**< L3 (IP) Header Length. */\n\t\tuint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */\n\t\tuint64_t tso_segsz:16; /**< TCP TSO segment size */\n\t\tuint64_t vlan_tci:16;\n\t\t/**< VLAN Tag Control Identifier (CPU order). */\n\t};\n};\n\n/*\n * Compare mask for vlan_macip_len.data,\n * should be in sync with ixgbe_vlan_macip.f layout.\n * */\n#define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */\n#define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */\n#define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */\n/** MAC+IP length. */\n#define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)\n\n/**\n * Structure to check if new context need be built\n */\n\nstruct ixgbe_advctx_info {\n\tuint64_t flags; /**< ol_flags for context build. */\n\t/**< tx offload: vlan, tso, l2-l3-l4 lengths. */\n\tunion ixgbe_tx_offload tx_offload;\n\t/** compare mask for tx offload. */\n\tunion ixgbe_tx_offload tx_offload_mask;\n};\n\n/**\n * Structure associated with each TX queue.\n */\nstruct ixgbe_tx_queue {\n\t/** TX ring virtual address. */\n\tvolatile union ixgbe_adv_tx_desc *tx_ring;\n\tuint64_t tx_ring_phys_addr; /**< TX ring DMA address. */\n\tunion {\n\t\tstruct ixgbe_tx_entry *sw_ring; /**< address of SW ring for scalar PMD. */\n\t\tstruct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for vector PMD */\n\t};\n\tvolatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */\n\tuint16_t nb_tx_desc; /**< number of TX descriptors. */\n\tuint16_t tx_tail; /**< current value of TDT reg. */\n\t/**< Start freeing TX buffers if there are less free descriptors than\n\t this value. */\n\tuint16_t tx_free_thresh;\n\t/** Number of TX descriptors to use before RS bit is set. */\n\tuint16_t tx_rs_thresh;\n\t/** Number of TX descriptors used since RS bit was set. */\n\tuint16_t nb_tx_used;\n\t/** Index to last TX descriptor to have been cleaned. */\n\tuint16_t last_desc_cleaned;\n\t/** Total number of TX descriptors ready to be allocated. */\n\tuint16_t nb_tx_free;\n\tuint16_t tx_next_dd; /**< next desc to scan for DD bit */\n\tuint16_t tx_next_rs; /**< next desc to set RS bit */\n\tuint16_t queue_id; /**< TX queue index. */\n\tuint16_t reg_idx; /**< TX queue register index. */\n\tuint8_t port_id; /**< Device port identifier. */\n\tuint8_t pthresh; /**< Prefetch threshold register. */\n\tuint8_t hthresh; /**< Host threshold register. */\n\tuint8_t wthresh; /**< Write-back threshold reg. */\n\tuint32_t txq_flags; /**< Holds flags for this TXq */\n\tuint32_t ctx_curr; /**< Hardware context states. */\n\t/** Hardware context0 history. */\n\tstruct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];\n\tconst struct ixgbe_txq_ops *ops; /**< txq ops */\n\tuint8_t tx_deferred_start; /**< not in global dev start. */\n};\n\nstruct ixgbe_txq_ops {\n\tvoid (*release_mbufs)(struct ixgbe_tx_queue *txq);\n\tvoid (*free_swring)(struct ixgbe_tx_queue *txq);\n\tvoid (*reset)(struct ixgbe_tx_queue *txq);\n};\n\n/*\n * The \"simple\" TX queue functions require that the following\n * flags are set when the TX queue is configured:\n * - ETH_TXQ_FLAGS_NOMULTSEGS\n * - ETH_TXQ_FLAGS_NOVLANOFFL\n * - ETH_TXQ_FLAGS_NOXSUMSCTP\n * - ETH_TXQ_FLAGS_NOXSUMUDP\n * - ETH_TXQ_FLAGS_NOXSUMTCP\n * and that the RS bit threshold (tx_rs_thresh) is at least equal to\n * RTE_PMD_IXGBE_TX_MAX_BURST.\n */\n#define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \\\n\t\t\t ETH_TXQ_FLAGS_NOOFFLOADS)\n\n/*\n * Populate descriptors with the following info:\n * 1.) buffer_addr = phys_addr + headroom\n * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len\n * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT\n */\n\n/* Defines for Tx descriptor */\n#define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\\\n\t\t\t IXGBE_ADVTXD_DCMD_IFCS |\\\n\t\t\t IXGBE_ADVTXD_DCMD_DEXT |\\\n\t\t\t IXGBE_ADVTXD_DCMD_EOP)\n\n\n/* Takes an ethdev and a queue and sets up the tx function to be used based on\n * the queue parameters. Used in tx_queue_setup by primary process and then\n * in dev_init by secondary process when attaching to an existing ethdev.\n */\nvoid ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq);\n\n/**\n * Sets the rx_pkt_burst callback in the ixgbe rte_eth_dev instance.\n *\n * Sets the callback based on the device parameters:\n * - ixgbe_hw.rx_bulk_alloc_allowed\n * - rte_eth_dev_data.scattered_rx\n * - rte_eth_dev_data.lro\n * - conditions checked in ixgbe_rx_vec_condition_check()\n *\n * This means that the parameters above have to be configured prior to calling\n * to this function.\n *\n * @dev rte_eth_dev handle\n */\nvoid ixgbe_set_rx_function(struct rte_eth_dev *dev);\n\nuint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts);\nuint16_t ixgbe_recv_scattered_pkts_vec(void *rx_queue,\n\t\tstruct rte_mbuf **rx_pkts, uint16_t nb_pkts);\nint ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev);\nint ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq);\nvoid ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq);\n\n#ifdef RTE_IXGBE_INC_VECTOR\n\nuint16_t ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t\tuint16_t nb_pkts);\nint ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq);\n\n#endif /* RTE_IXGBE_INC_VECTOR */\n#endif /* _IXGBE_RXTX_H_ */\n" }, { "path": "drivers/net/ixgbe/ixgbe_rxtx_vec.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \"ixgbe_ethdev.h\"\n#include \"ixgbe_rxtx.h\"\n\n#include \n\n#ifndef __INTEL_COMPILER\n#pragma GCC diagnostic ignored \"-Wcast-qual\"\n#endif\n\nstatic inline void\nixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)\n{\n\tint i;\n\tuint16_t rx_id;\n\tvolatile union ixgbe_adv_rx_desc *rxdp;\n\tstruct ixgbe_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];\n\tstruct rte_mbuf *mb0, *mb1;\n\t__m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,\n\t\t\tRTE_PKTMBUF_HEADROOM);\n\t__m128i dma_addr0, dma_addr1;\n\n\tconst __m128i hba_msk = _mm_set_epi64x(0, UINT64_MAX);\n\n\trxdp = rxq->rx_ring + rxq->rxrearm_start;\n\n\t/* Pull 'n' more MBUFs into the software ring */\n\tif (rte_mempool_get_bulk(rxq->mb_pool,\n\t\t\t\t (void *)rxep,\n\t\t\t\t RTE_IXGBE_RXQ_REARM_THRESH) < 0) {\n\t\tif (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=\n\t\t rxq->nb_rx_desc) {\n\t\t\tdma_addr0 = _mm_setzero_si128();\n\t\t\tfor (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {\n\t\t\t\trxep[i].mbuf = &rxq->fake_mbuf;\n\t\t\t\t_mm_store_si128((__m128i *)&rxdp[i].read,\n\t\t\t\t\t\tdma_addr0);\n\t\t\t}\n\t\t}\n\t\trte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=\n\t\t\tRTE_IXGBE_RXQ_REARM_THRESH;\n\t\treturn;\n\t}\n\n\t/* Initialize the mbufs in vector, process 2 mbufs in one loop */\n\tfor (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {\n\t\t__m128i vaddr0, vaddr1;\n\t\tuintptr_t p0, p1;\n\n\t\tmb0 = rxep[0].mbuf;\n\t\tmb1 = rxep[1].mbuf;\n\n\t\t/*\n\t\t * Flush mbuf with pkt template.\n\t\t * Data to be rearmed is 6 bytes long.\n\t\t * Though, RX will overwrite ol_flags that are coming next\n\t\t * anyway. So overwrite whole 8 bytes with one load:\n\t\t * 6 bytes of rearm_data plus first 2 bytes of ol_flags.\n\t\t */\n\t\tp0 = (uintptr_t)&mb0->rearm_data;\n\t\t*(uint64_t *)p0 = rxq->mbuf_initializer;\n\t\tp1 = (uintptr_t)&mb1->rearm_data;\n\t\t*(uint64_t *)p1 = rxq->mbuf_initializer;\n\n\t\t/* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */\n\t\tvaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));\n\t\tvaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));\n\n\t\t/* convert pa to dma_addr hdr/data */\n\t\tdma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);\n\t\tdma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);\n\n\t\t/* add headroom to pa values */\n\t\tdma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);\n\t\tdma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);\n\n\t\t/* set Header Buffer Address to zero */\n\t\tdma_addr0 = _mm_and_si128(dma_addr0, hba_msk);\n\t\tdma_addr1 = _mm_and_si128(dma_addr1, hba_msk);\n\n\t\t/* flush desc with pa dma_addr */\n\t\t_mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);\n\t\t_mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);\n\t}\n\n\trxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;\n\tif (rxq->rxrearm_start >= rxq->nb_rx_desc)\n\t\trxq->rxrearm_start = 0;\n\n\trxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;\n\n\trx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?\n\t\t\t (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));\n\n\t/* Update the tail pointer on the NIC */\n\tIXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);\n}\n\n/* Handling the offload flags (olflags) field takes computation\n * time when receiving packets. Therefore we provide a flag to disable\n * the processing of the olflags field when they are not needed. This\n * gives improved performance, at the cost of losing the offload info\n * in the received packet\n */\n#ifdef RTE_IXGBE_RX_OLFLAGS_ENABLE\n\n#ifndef RTE_NEXT_ABI\n#define OLFLAGS_MASK\t((uint16_t)(PKT_RX_VLAN_PKT | PKT_RX_IPV4_HDR |\\\n\t\t\tPKT_RX_IPV4_HDR_EXT | PKT_RX_IPV6_HDR |\\\n\t\t\tPKT_RX_IPV6_HDR_EXT))\n#define PTYPE_SHIFT (1)\n#endif /* RTE_NEXT_ABI */\n\n#define VTAG_SHIFT (3)\n\nstatic inline void\ndesc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)\n{\n#ifdef RTE_NEXT_ABI\n\t__m128i ptype0, ptype1, vtag0, vtag1;\n\tunion {\n\t\tuint16_t e[4];\n\t\tuint64_t dword;\n\t} vol;\n\n\t/* pkt type + vlan olflags mask */\n\tconst __m128i pkttype_msk = _mm_set_epi16(\n\t\t\t0x0000, 0x0000, 0x0000, 0x0000,\n\t\t\tPKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT, PKT_RX_VLAN_PKT);\n\n\t/* mask everything except rss type */\n\tconst __m128i rsstype_msk = _mm_set_epi16(\n\t\t\t0x0000, 0x0000, 0x0000, 0x0000,\n\t\t\t0x000F, 0x000F, 0x000F, 0x000F);\n\n\t/* map rss type to rss hash flag */\n\tconst __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,\n\t\t\t0, 0, 0, PKT_RX_RSS_HASH,\n\t\t\tPKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,\n\t\t\tPKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);\n\n\tptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);\n\tptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);\n\tvtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);\n\tvtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);\n\n\tptype0 = _mm_unpacklo_epi32(ptype0, ptype1);\n\tptype0 = _mm_and_si128(ptype0, rsstype_msk);\n\tptype0 = _mm_shuffle_epi8(rss_flags, ptype0);\n\n\tvtag1 = _mm_unpacklo_epi32(vtag0, vtag1);\n\tvtag1 = _mm_srli_epi16(vtag1, VTAG_SHIFT);\n\tvtag1 = _mm_and_si128(vtag1, pkttype_msk);\n\n\tvtag1 = _mm_or_si128(ptype0, vtag1);\n\tvol.dword = _mm_cvtsi128_si64(vtag1);\n#else\n\t__m128i ptype0, ptype1, vtag0, vtag1;\n\tunion {\n\t\tuint16_t e[4];\n\t\tuint64_t dword;\n\t} vol;\n\n\t/* pkt type + vlan olflags mask */\n\tconst __m128i pkttype_msk = _mm_set_epi16(\n\t\t\t0x0000, 0x0000, 0x0000, 0x0000,\n\t\t\tOLFLAGS_MASK, OLFLAGS_MASK, OLFLAGS_MASK, OLFLAGS_MASK);\n\n\t/* mask everything except rss type */\n\tconst __m128i rsstype_msk = _mm_set_epi16(\n\t\t\t0x0000, 0x0000, 0x0000, 0x0000,\n\t\t\t0x000F, 0x000F, 0x000F, 0x000F);\n\n\t/* rss type to PKT_RX_RSS_HASH translation */\n\tconst __m128i rss_flags = _mm_set_epi8(PKT_RX_FDIR, 0, 0, 0,\n\t\t\t0, 0, 0, PKT_RX_RSS_HASH,\n\t\t\tPKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH, 0,\n\t\t\tPKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, 0);\n\n\tptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);\n\tptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);\n\tvtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);\n\tvtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);\n\n\tptype1 = _mm_unpacklo_epi32(ptype0, ptype1);\n\tvtag1 = _mm_unpacklo_epi32(vtag0, vtag1);\n\n\tptype0 = _mm_and_si128(ptype1, rsstype_msk);\n\tptype0 = _mm_shuffle_epi8(rss_flags, ptype0);\n\n\tptype1 = _mm_slli_epi16(ptype1, PTYPE_SHIFT);\n\tvtag1 = _mm_srli_epi16(vtag1, VTAG_SHIFT);\n\n\tptype1 = _mm_or_si128(ptype1, vtag1);\n\tptype1 = _mm_and_si128(ptype1, pkttype_msk);\n\n\tptype0 = _mm_or_si128(ptype0, ptype1);\n\n\tvol.dword = _mm_cvtsi128_si64(ptype0);\n#endif /* RTE_NEXT_ABI */\n\n\trx_pkts[0]->ol_flags = vol.e[0];\n\trx_pkts[1]->ol_flags = vol.e[1];\n\trx_pkts[2]->ol_flags = vol.e[2];\n\trx_pkts[3]->ol_flags = vol.e[3];\n}\n#else\n#define desc_to_olflags_v(desc, rx_pkts) do {} while (0)\n#endif\n\n/*\n * vPMD receive routine, now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)\n * in one loop\n *\n * Notice:\n * - nb_pkts < RTE_IXGBE_VPMD_RX_BURST, just return no packet\n * - nb_pkts > RTE_IXGBE_VPMD_RX_BURST, only scan RTE_IXGBE_VPMD_RX_BURST\n * numbers of DD bit\n * - don't support ol_flags for rss and csum err\n */\nstatic inline uint16_t\n_recv_raw_pkts_vec(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts, uint8_t *split_packet)\n{\n\tvolatile union ixgbe_adv_rx_desc *rxdp;\n\tstruct ixgbe_rx_entry *sw_ring;\n\tuint16_t nb_pkts_recd;\n\tint pos;\n\tuint64_t var;\n\t__m128i shuf_msk;\n#ifdef RTE_NEXT_ABI\n\t__m128i crc_adjust = _mm_set_epi16(\n\t\t\t\t0, 0, 0, /* ignore non-length fields */\n\t\t\t\t-rxq->crc_len, /* sub crc on data_len */\n\t\t\t\t0, /* ignore high-16bits of pkt_len */\n\t\t\t\t-rxq->crc_len, /* sub crc on pkt_len */\n\t\t\t\t0, 0 /* ignore pkt_type field */\n\t\t\t);\n\t__m128i dd_check, eop_check;\n\t__m128i desc_mask = _mm_set_epi32(0xFFFFFFFF, 0xFFFFFFFF,\n\t\t\t\t\t 0xFFFFFFFF, 0xFFFF07F0);\n#else\n\t__m128i crc_adjust = _mm_set_epi16(\n\t\t\t\t0, 0, 0, 0, /* ignore non-length fields */\n\t\t\t\t0, /* ignore high-16bits of pkt_len */\n\t\t\t\t-rxq->crc_len, /* sub crc on pkt_len */\n\t\t\t\t-rxq->crc_len, /* sub crc on data_len */\n\t\t\t\t0 /* ignore pkt_type field */\n\t\t\t);\n\t__m128i dd_check, eop_check;\n#endif /* RTE_NEXT_ABI */\n\n\tif (unlikely(nb_pkts < RTE_IXGBE_VPMD_RX_BURST))\n\t\treturn 0;\n\n\t/* Just the act of getting into the function from the application is\n\t * going to cost about 7 cycles */\n\trxdp = rxq->rx_ring + rxq->rx_tail;\n\n\t_mm_prefetch((const void *)rxdp, _MM_HINT_T0);\n\n\t/* See if we need to rearm the RX queue - gives the prefetch a bit\n\t * of time to act */\n\tif (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)\n\t\tixgbe_rxq_rearm(rxq);\n\n\t/* Before we start moving massive data around, check to see if\n\t * there is actually a packet available */\n\tif (!(rxdp->wb.upper.status_error &\n\t\t\t\trte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))\n\t\treturn 0;\n\n\t/* 4 packets DD mask */\n\tdd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);\n\n\t/* 4 packets EOP mask */\n\teop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);\n\n\t/* mask to shuffle from desc. to mbuf */\n#ifdef RTE_NEXT_ABI\n\tshuf_msk = _mm_set_epi8(\n\t\t7, 6, 5, 4, /* octet 4~7, 32bits rss */\n\t\t15, 14, /* octet 14~15, low 16 bits vlan_macip */\n\t\t13, 12, /* octet 12~13, 16 bits data_len */\n\t\t0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n\t\t13, 12, /* octet 12~13, low 16 bits pkt_len */\n\t\t0xFF, 0xFF, /* skip high 16 bits pkt_type */\n\t\t1, /* octet 1, 8 bits pkt_type field */\n\t\t0 /* octet 0, 4 bits offset 4 pkt_type field */\n\t\t);\n#else\n\tshuf_msk = _mm_set_epi8(\n\t\t7, 6, 5, 4, /* octet 4~7, 32bits rss */\n\t\t0xFF, 0xFF, /* skip high 16 bits vlan_macip, zero out */\n\t\t15, 14, /* octet 14~15, low 16 bits vlan_macip */\n\t\t0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n\t\t13, 12, /* octet 12~13, low 16 bits pkt_len */\n\t\t13, 12, /* octet 12~13, 16 bits data_len */\n\t\t0xFF, 0xFF /* skip pkt_type field */\n\t\t);\n#endif /* RTE_NEXT_ABI */\n\n\t/* Cache is empty -> need to scan the buffer rings, but first move\n\t * the next 'n' mbufs into the cache */\n\tsw_ring = &rxq->sw_ring[rxq->rx_tail];\n\n#ifdef RTE_NEXT_ABI\n\t/* A. load 4 packet in one loop\n\t * [A*. mask out 4 unused dirty field in desc]\n\t * B. copy 4 mbuf point from swring to rx_pkts\n\t * C. calc the number of DD bits among the 4 packets\n\t * [C*. extract the end-of-packet bit, if requested]\n\t * D. fill info. from desc to mbuf\n\t */\n#else\n\t/* A. load 4 packet in one loop\n\t * B. copy 4 mbuf point from swring to rx_pkts\n\t * C. calc the number of DD bits among the 4 packets\n\t * [C*. extract the end-of-packet bit, if requested]\n\t * D. fill info. from desc to mbuf\n\t */\n#endif /* RTE_NEXT_ABI */\n\tfor (pos = 0, nb_pkts_recd = 0; pos < RTE_IXGBE_VPMD_RX_BURST;\n\t\t\tpos += RTE_IXGBE_DESCS_PER_LOOP,\n\t\t\trxdp += RTE_IXGBE_DESCS_PER_LOOP) {\n#ifdef RTE_NEXT_ABI\n\t\t__m128i descs0[RTE_IXGBE_DESCS_PER_LOOP];\n#endif /* RTE_NEXT_ABI */\n\t\t__m128i descs[RTE_IXGBE_DESCS_PER_LOOP];\n\t\t__m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;\n\t\t__m128i zero, staterr, sterr_tmp1, sterr_tmp2;\n\t\t__m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */\n\n\t\tif (split_packet) {\n\t\t\trte_prefetch0(&rx_pkts[pos]->cacheline1);\n\t\t\trte_prefetch0(&rx_pkts[pos + 1]->cacheline1);\n\t\t\trte_prefetch0(&rx_pkts[pos + 2]->cacheline1);\n\t\t\trte_prefetch0(&rx_pkts[pos + 3]->cacheline1);\n\t\t}\n\n\t\t/* B.1 load 1 mbuf point */\n\t\tmbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);\n\n#ifdef RTE_NEXT_ABI\n\t\t/* Read desc statuses backwards to avoid race condition */\n\t\t/* A.1 load 4 pkts desc */\n\t\tdescs0[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));\n\n\t\t/* B.2 copy 2 mbuf point into rx_pkts */\n\t\t_mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);\n\n\t\t/* B.1 load 1 mbuf point */\n\t\tmbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);\n\n\t\tdescs0[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));\n\t\t/* B.1 load 2 mbuf point */\n\t\tdescs0[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));\n\t\tdescs0[0] = _mm_loadu_si128((__m128i *)(rxdp));\n\n\t\t/* B.2 copy 2 mbuf point into rx_pkts */\n\t\t_mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);\n\n\t\t/* A* mask out 0~3 bits RSS type */\n\t\tdescs[3] = _mm_and_si128(descs0[3], desc_mask);\n\t\tdescs[2] = _mm_and_si128(descs0[2], desc_mask);\n\n\t\t/* A* mask out 0~3 bits RSS type */\n\t\tdescs[1] = _mm_and_si128(descs0[1], desc_mask);\n\t\tdescs[0] = _mm_and_si128(descs0[0], desc_mask);\n#else\n\t\t/* Read desc statuses backwards to avoid race condition */\n\t\t/* A.1 load 4 pkts desc */\n\t\tdescs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));\n\n\t\t/* B.2 copy 2 mbuf point into rx_pkts */\n\t\t_mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);\n\n\t\t/* B.1 load 1 mbuf point */\n\t\tmbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);\n\n\t\tdescs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));\n\t\t/* B.1 load 2 mbuf point */\n\t\tdescs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));\n\t\tdescs[0] = _mm_loadu_si128((__m128i *)(rxdp));\n\n\t\t/* B.2 copy 2 mbuf point into rx_pkts */\n\t\t_mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);\n#endif /* RTE_NEXT_ABI */\n\n\t\t/* avoid compiler reorder optimization */\n\t\trte_compiler_barrier();\n\n\t\t/* D.1 pkt 3,4 convert format from desc to pktmbuf */\n\t\tpkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);\n\t\tpkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);\n\n\t\t/* C.1 4=>2 filter staterr info only */\n\t\tsterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);\n\t\t/* C.1 4=>2 filter staterr info only */\n\t\tsterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);\n\n#ifdef RTE_NEXT_ABI\n\t\t/* set ol_flags with vlan packet type */\n\t\tdesc_to_olflags_v(descs0, &rx_pkts[pos]);\n#else\n\t\t/* set ol_flags with packet type and vlan tag */\n\t\tdesc_to_olflags_v(descs, &rx_pkts[pos]);\n#endif /* RTE_NEXT_ABI */\n\n\t\t/* D.2 pkt 3,4 set in_port/nb_seg and remove crc */\n\t\tpkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);\n\t\tpkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);\n\n\t\t/* D.1 pkt 1,2 convert format from desc to pktmbuf */\n\t\tpkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);\n\t\tpkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);\n\n\t\t/* C.2 get 4 pkts staterr value */\n\t\tzero = _mm_xor_si128(dd_check, dd_check);\n\t\tstaterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);\n\n\t\t/* D.3 copy final 3,4 data to rx_pkts */\n\t\t_mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,\n\t\t\t\tpkt_mb4);\n\t\t_mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,\n\t\t\t\tpkt_mb3);\n\n\t\t/* D.2 pkt 1,2 set in_port/nb_seg and remove crc */\n\t\tpkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);\n\t\tpkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);\n\n\t\t/* C* extract and record EOP bit */\n\t\tif (split_packet) {\n\t\t\t__m128i eop_shuf_mask = _mm_set_epi8(\n\t\t\t\t\t0xFF, 0xFF, 0xFF, 0xFF,\n\t\t\t\t\t0xFF, 0xFF, 0xFF, 0xFF,\n\t\t\t\t\t0xFF, 0xFF, 0xFF, 0xFF,\n\t\t\t\t\t0x04, 0x0C, 0x00, 0x08\n\t\t\t\t\t);\n\n\t\t\t/* and with mask to extract bits, flipping 1-0 */\n\t\t\t__m128i eop_bits = _mm_andnot_si128(staterr, eop_check);\n\t\t\t/* the staterr values are not in order, as the count\n\t\t\t * count of dd bits doesn't care. However, for end of\n\t\t\t * packet tracking, we do care, so shuffle. This also\n\t\t\t * compresses the 32-bit values to 8-bit */\n\t\t\teop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);\n\t\t\t/* store the resulting 32-bit value */\n\t\t\t*(int *)split_packet = _mm_cvtsi128_si32(eop_bits);\n\t\t\tsplit_packet += RTE_IXGBE_DESCS_PER_LOOP;\n\n\t\t\t/* zero-out next pointers */\n\t\t\trx_pkts[pos]->next = NULL;\n\t\t\trx_pkts[pos + 1]->next = NULL;\n\t\t\trx_pkts[pos + 2]->next = NULL;\n\t\t\trx_pkts[pos + 3]->next = NULL;\n\t\t}\n\n\t\t/* C.3 calc available number of desc */\n\t\tstaterr = _mm_and_si128(staterr, dd_check);\n\t\tstaterr = _mm_packs_epi32(staterr, zero);\n\n\t\t/* D.3 copy final 1,2 data to rx_pkts */\n\t\t_mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,\n\t\t\t\tpkt_mb2);\n\t\t_mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,\n\t\t\t\tpkt_mb1);\n\n\t\t/* C.4 calc avaialbe number of desc */\n\t\tvar = __builtin_popcountll(_mm_cvtsi128_si64(staterr));\n\t\tnb_pkts_recd += var;\n\t\tif (likely(var != RTE_IXGBE_DESCS_PER_LOOP))\n\t\t\tbreak;\n\t}\n\n\t/* Update our internal tail pointer */\n\trxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);\n\trxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));\n\trxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);\n\n\treturn nb_pkts_recd;\n}\n\n/*\n * vPMD receive routine, now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)\n * in one loop\n *\n * Notice:\n * - nb_pkts < RTE_IXGBE_VPMD_RX_BURST, just return no packet\n * - nb_pkts > RTE_IXGBE_VPMD_RX_BURST, only scan RTE_IXGBE_VPMD_RX_BURST\n * numbers of DD bit\n * - don't support ol_flags for rss and csum err\n */\nuint16_t\nixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts)\n{\n\treturn _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);\n}\n\nstatic inline uint16_t\nreassemble_packets(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_bufs,\n\t\tuint16_t nb_bufs, uint8_t *split_flags)\n{\n\tstruct rte_mbuf *pkts[RTE_IXGBE_VPMD_RX_BURST]; /*finished pkts*/\n\tstruct rte_mbuf *start = rxq->pkt_first_seg;\n\tstruct rte_mbuf *end = rxq->pkt_last_seg;\n\tunsigned pkt_idx, buf_idx;\n\n\n\tfor (buf_idx = 0, pkt_idx = 0; buf_idx < nb_bufs; buf_idx++) {\n\t\tif (end != NULL) {\n\t\t\t/* processing a split packet */\n\t\t\tend->next = rx_bufs[buf_idx];\n\t\t\trx_bufs[buf_idx]->data_len += rxq->crc_len;\n\n\t\t\tstart->nb_segs++;\n\t\t\tstart->pkt_len += rx_bufs[buf_idx]->data_len;\n\t\t\tend = end->next;\n\n\t\t\tif (!split_flags[buf_idx]) {\n\t\t\t\t/* it's the last packet of the set */\n\t\t\t\tstart->hash = end->hash;\n\t\t\t\tstart->ol_flags = end->ol_flags;\n\t\t\t\t/* we need to strip crc for the whole packet */\n\t\t\t\tstart->pkt_len -= rxq->crc_len;\n\t\t\t\tif (end->data_len > rxq->crc_len)\n\t\t\t\t\tend->data_len -= rxq->crc_len;\n\t\t\t\telse {\n\t\t\t\t\t/* free up last mbuf */\n\t\t\t\t\tstruct rte_mbuf *secondlast = start;\n\n\t\t\t\t\tstart->nb_segs--;\n\t\t\t\t\twhile (secondlast->next != end)\n\t\t\t\t\t\tsecondlast = secondlast->next;\n\t\t\t\t\tsecondlast->data_len -= (rxq->crc_len -\n\t\t\t\t\t\t\tend->data_len);\n\t\t\t\t\tsecondlast->next = NULL;\n\t\t\t\t\trte_pktmbuf_free_seg(end);\n\t\t\t\t\tend = secondlast;\n\t\t\t\t}\n\t\t\t\tpkts[pkt_idx++] = start;\n\t\t\t\tstart = end = NULL;\n\t\t\t}\n\t\t} else {\n\t\t\t/* not processing a split packet */\n\t\t\tif (!split_flags[buf_idx]) {\n\t\t\t\t/* not a split packet, save and skip */\n\t\t\t\tpkts[pkt_idx++] = rx_bufs[buf_idx];\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tend = start = rx_bufs[buf_idx];\n\t\t\trx_bufs[buf_idx]->data_len += rxq->crc_len;\n\t\t\trx_bufs[buf_idx]->pkt_len += rxq->crc_len;\n\t\t}\n\t}\n\n\t/* save the partial packet for next time */\n\trxq->pkt_first_seg = start;\n\trxq->pkt_last_seg = end;\n\tmemcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));\n\treturn pkt_idx;\n}\n\n/*\n * vPMD receive routine that reassembles scattered packets\n *\n * Notice:\n * - don't support ol_flags for rss and csum err\n * - now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)\n */\nuint16_t\nixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts)\n{\n\tstruct ixgbe_rx_queue *rxq = rx_queue;\n\tuint8_t split_flags[RTE_IXGBE_VPMD_RX_BURST] = {0};\n\n\t/* get some new buffers */\n\tuint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,\n\t\t\tsplit_flags);\n\tif (nb_bufs == 0)\n\t\treturn 0;\n\n\t/* happy day case, full burst + no packets to be joined */\n\tconst uint64_t *split_fl64 = (uint64_t *)split_flags;\n\tif (rxq->pkt_first_seg == NULL &&\n\t\t\tsplit_fl64[0] == 0 && split_fl64[1] == 0 &&\n\t\t\tsplit_fl64[2] == 0 && split_fl64[3] == 0)\n\t\treturn nb_bufs;\n\n\t/* reassemble any packets that need reassembly*/\n\tunsigned i = 0;\n\tif (rxq->pkt_first_seg == NULL) {\n\t\t/* find the first split flag, and only reassemble then*/\n\t\twhile (i < nb_bufs && !split_flags[i])\n\t\t\ti++;\n\t\tif (i == nb_bufs)\n\t\t\treturn nb_bufs;\n\t}\n\treturn i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,\n\t\t&split_flags[i]);\n}\n\nstatic inline void\nvtx1(volatile union ixgbe_adv_tx_desc *txdp,\n\t\tstruct rte_mbuf *pkt, uint64_t flags)\n{\n\t__m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |\n\t\t\tflags | pkt->data_len,\n\t\t\tpkt->buf_physaddr + pkt->data_off);\n\t_mm_store_si128((__m128i *)&txdp->read, descriptor);\n}\n\nstatic inline void\nvtx(volatile union ixgbe_adv_tx_desc *txdp,\n\t\tstruct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)\n{\n\tint i;\n\tfor (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)\n\t\tvtx1(txdp, *pkt, flags);\n}\n\nstatic inline int __attribute__((always_inline))\nixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)\n{\n\tstruct ixgbe_tx_entry_v *txep;\n\tuint32_t status;\n\tuint32_t n;\n\tuint32_t i;\n\tint nb_free = 0;\n\tstruct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];\n\n\t/* check DD bit on threshold descriptor */\n\tstatus = txq->tx_ring[txq->tx_next_dd].wb.status;\n\tif (!(status & IXGBE_ADVTXD_STAT_DD))\n\t\treturn 0;\n\n\tn = txq->tx_rs_thresh;\n\n\t/*\n\t * first buffer to free from S/W ring is at index\n\t * tx_next_dd - (tx_rs_thresh-1)\n\t */\n\ttxep = &txq->sw_ring_v[txq->tx_next_dd - (n - 1)];\n\tm = __rte_pktmbuf_prefree_seg(txep[0].mbuf);\n\tif (likely(m != NULL)) {\n\t\tfree[0] = m;\n\t\tnb_free = 1;\n\t\tfor (i = 1; i < n; i++) {\n\t\t\tm = __rte_pktmbuf_prefree_seg(txep[i].mbuf);\n\t\t\tif (likely(m != NULL)) {\n\t\t\t\tif (likely(m->pool == free[0]->pool))\n\t\t\t\t\tfree[nb_free++] = m;\n\t\t\t\telse {\n\t\t\t\t\trte_mempool_put_bulk(free[0]->pool,\n\t\t\t\t\t\t\t(void *)free, nb_free);\n\t\t\t\t\tfree[0] = m;\n\t\t\t\t\tnb_free = 1;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\trte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);\n\t} else {\n\t\tfor (i = 1; i < n; i++) {\n\t\t\tm = __rte_pktmbuf_prefree_seg(txep[i].mbuf);\n\t\t\tif (m != NULL)\n\t\t\t\trte_mempool_put(m->pool, m);\n\t\t}\n\t}\n\n\t/* buffers were freed, update counters */\n\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);\n\ttxq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);\n\tif (txq->tx_next_dd >= txq->nb_tx_desc)\n\t\ttxq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);\n\n\treturn txq->tx_rs_thresh;\n}\n\nstatic inline void __attribute__((always_inline))\ntx_backlog_entry(struct ixgbe_tx_entry_v *txep,\n\t\t struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n{\n\tint i;\n\tfor (i = 0; i < (int)nb_pkts; ++i)\n\t\ttxep[i].mbuf = tx_pkts[i];\n}\n\nuint16_t\nixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t\t uint16_t nb_pkts)\n{\n\tstruct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;\n\tvolatile union ixgbe_adv_tx_desc *txdp;\n\tstruct ixgbe_tx_entry_v *txep;\n\tuint16_t n, nb_commit, tx_id;\n\tuint64_t flags = DCMD_DTYP_FLAGS;\n\tuint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;\n\tint i;\n\n\tif (unlikely(nb_pkts > RTE_IXGBE_VPMD_TX_BURST))\n\t\tnb_pkts = RTE_IXGBE_VPMD_TX_BURST;\n\n\tif (txq->nb_tx_free < txq->tx_free_thresh)\n\t\tixgbe_tx_free_bufs(txq);\n\n\tnb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);\n\tif (unlikely(nb_pkts == 0))\n\t\treturn 0;\n\n\ttx_id = txq->tx_tail;\n\ttxdp = &txq->tx_ring[tx_id];\n\ttxep = &txq->sw_ring_v[tx_id];\n\n\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);\n\n\tn = (uint16_t)(txq->nb_tx_desc - tx_id);\n\tif (nb_commit >= n) {\n\n\t\ttx_backlog_entry(txep, tx_pkts, n);\n\n\t\tfor (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)\n\t\t\tvtx1(txdp, *tx_pkts, flags);\n\n\t\tvtx1(txdp, *tx_pkts++, rs);\n\n\t\tnb_commit = (uint16_t)(nb_commit - n);\n\n\t\ttx_id = 0;\n\t\ttxq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);\n\n\t\t/* avoid reach the end of ring */\n\t\ttxdp = &(txq->tx_ring[tx_id]);\n\t\ttxep = &txq->sw_ring_v[tx_id];\n\t}\n\n\ttx_backlog_entry(txep, tx_pkts, nb_commit);\n\n\tvtx(txdp, tx_pkts, nb_commit, flags);\n\n\ttx_id = (uint16_t)(tx_id + nb_commit);\n\tif (tx_id > txq->tx_next_rs) {\n\t\ttxq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=\n\t\t\trte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);\n\t\ttxq->tx_next_rs = (uint16_t)(txq->tx_next_rs +\n\t\t\ttxq->tx_rs_thresh);\n\t}\n\n\ttxq->tx_tail = tx_id;\n\n\tIXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);\n\n\treturn nb_pkts;\n}\n\nstatic void __attribute__((cold))\nixgbe_tx_queue_release_mbufs_vec(struct ixgbe_tx_queue *txq)\n{\n\tunsigned i;\n\tstruct ixgbe_tx_entry_v *txe;\n\tconst uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);\n\n\tif (txq->sw_ring == NULL || txq->nb_tx_free == max_desc)\n\t\treturn;\n\n\t/* release the used mbufs in sw_ring */\n\tfor (i = txq->tx_next_dd - (txq->tx_rs_thresh - 1);\n\t i != txq->tx_tail;\n\t i = (i + 1) & max_desc) {\n\t\ttxe = &txq->sw_ring_v[i];\n\t\trte_pktmbuf_free_seg(txe->mbuf);\n\t}\n\ttxq->nb_tx_free = max_desc;\n\n\t/* reset tx_entry */\n\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n\t\ttxe = &txq->sw_ring_v[i];\n\t\ttxe->mbuf = NULL;\n\t}\n}\n\nvoid __attribute__((cold))\nixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq)\n{\n\tconst unsigned mask = rxq->nb_rx_desc - 1;\n\tunsigned i;\n\n\tif (rxq->sw_ring == NULL || rxq->rxrearm_nb >= rxq->nb_rx_desc)\n\t\treturn;\n\n\t/* free all mbufs that are valid in the ring */\n\tfor (i = rxq->rx_tail; i != rxq->rxrearm_start; i = (i + 1) & mask)\n\t\trte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);\n\trxq->rxrearm_nb = rxq->nb_rx_desc;\n\n\t/* set all entries to NULL */\n\tmemset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);\n}\n\nstatic void __attribute__((cold))\nixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)\n{\n\tif (txq == NULL)\n\t\treturn;\n\n\tif (txq->sw_ring != NULL) {\n\t\trte_free(txq->sw_ring_v - 1);\n\t\ttxq->sw_ring_v = NULL;\n\t}\n}\n\nstatic void __attribute__((cold))\nixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)\n{\n\tstatic const union ixgbe_adv_tx_desc zeroed_desc = {{0}};\n\tstruct ixgbe_tx_entry_v *txe = txq->sw_ring_v;\n\tuint16_t i;\n\n\t/* Zero out HW ring memory */\n\tfor (i = 0; i < txq->nb_tx_desc; i++)\n\t\ttxq->tx_ring[i] = zeroed_desc;\n\n\t/* Initialize SW ring entries */\n\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n\t\tvolatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];\n\t\ttxd->wb.status = IXGBE_TXD_STAT_DD;\n\t\ttxe[i].mbuf = NULL;\n\t}\n\n\ttxq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);\n\ttxq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);\n\n\ttxq->tx_tail = 0;\n\ttxq->nb_tx_used = 0;\n\t/*\n\t * Always allow 1 descriptor to be un-allocated to avoid\n\t * a H/W race condition\n\t */\n\ttxq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);\n\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);\n\ttxq->ctx_curr = 0;\n\tmemset((void *)&txq->ctx_cache, 0,\n\t\tIXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));\n}\n\nstatic const struct ixgbe_txq_ops vec_txq_ops = {\n\t.release_mbufs = ixgbe_tx_queue_release_mbufs_vec,\n\t.free_swring = ixgbe_tx_free_swring,\n\t.reset = ixgbe_reset_tx_queue,\n};\n\nint __attribute__((cold))\nixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq)\n{\n\tuintptr_t p;\n\tstruct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */\n\n\tmb_def.nb_segs = 1;\n\tmb_def.data_off = RTE_PKTMBUF_HEADROOM;\n\tmb_def.port = rxq->port_id;\n\trte_mbuf_refcnt_set(&mb_def, 1);\n\n\t/* prevent compiler reordering: rearm_data covers previous fields */\n\trte_compiler_barrier();\n\tp = (uintptr_t)&mb_def.rearm_data;\n\trxq->mbuf_initializer = *(uint64_t *)p;\n\treturn 0;\n}\n\nint __attribute__((cold))\nixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq)\n{\n\tif (txq->sw_ring_v == NULL)\n\t\treturn -1;\n\n\t/* leave the first one for overflow */\n\ttxq->sw_ring_v = txq->sw_ring_v + 1;\n\ttxq->ops = &vec_txq_ops;\n\n\treturn 0;\n}\n\nint __attribute__((cold))\nixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)\n{\n#ifndef RTE_LIBRTE_IEEE1588\n\tstruct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;\n\tstruct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;\n\n#ifndef RTE_IXGBE_RX_OLFLAGS_ENABLE\n\t/* whithout rx ol_flags, no VP flag report */\n\tif (rxmode->hw_vlan_strip != 0 ||\n\t rxmode->hw_vlan_extend != 0)\n\t\treturn -1;\n#endif\n\n\t/* no fdir support */\n\tif (fconf->mode != RTE_FDIR_MODE_NONE)\n\t\treturn -1;\n\n\t/*\n\t * - no csum error report support\n\t * - no header split support\n\t */\n\tif (rxmode->hw_ip_checksum == 1 ||\n\t rxmode->header_split == 1)\n\t\treturn -1;\n\n\treturn 0;\n#else\n\tRTE_SET_USED(dev);\n\treturn -1;\n#endif\n}\n" }, { "path": "drivers/net/mlx4/Makefile", "content": "# BSD LICENSE\n#\n# Copyright 2012-2015 6WIND S.A.\n# Copyright 2012 Mellanox.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifeq ($(CONFIG_RTE_BUILD_COMBINE_LIBS)$(CONFIG_RTE_BUILD_SHARED_LIB),yy)\nall:\n\t@echo 'MLX4: Not supported in a combined shared library'\n\t@false\nendif\n\n# Library name.\nLIB = librte_pmd_mlx4.a\n\n# Sources.\nSRCS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += mlx4.c\n\n# Dependencies.\nDEPDIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += lib/librte_eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += lib/librte_mempool\n\n# Basic CFLAGS.\nCFLAGS += -O3\nCFLAGS += -std=gnu99 -Wall -Wextra\nCFLAGS += -g\nCFLAGS += -I.\nCFLAGS += -D_XOPEN_SOURCE=600\nCFLAGS += $(WERROR_FLAGS)\nLDLIBS += -libverbs\n\n# A few warnings cannot be avoided in external headers.\nCFLAGS += -Wno-error=cast-qual\n\nEXPORT_MAP := rte_pmd_mlx4_version.map\nLIBABIVER := 1\n\n# DEBUG which is usually provided on the command-line may enable\n# CONFIG_RTE_LIBRTE_MLX4_DEBUG.\nifeq ($(DEBUG),1)\nCONFIG_RTE_LIBRTE_MLX4_DEBUG := y\nendif\n\n# User-defined CFLAGS.\nifeq ($(CONFIG_RTE_LIBRTE_MLX4_DEBUG),y)\nCFLAGS += -pedantic -UNDEBUG -DPEDANTIC\nelse\nCFLAGS += -DNDEBUG -UPEDANTIC\nendif\n\nifdef CONFIG_RTE_LIBRTE_MLX4_SGE_WR_N\nCFLAGS += -DMLX4_PMD_SGE_WR_N=$(CONFIG_RTE_LIBRTE_MLX4_SGE_WR_N)\nendif\n\nifdef CONFIG_RTE_LIBRTE_MLX4_MAX_INLINE\nCFLAGS += -DMLX4_PMD_MAX_INLINE=$(CONFIG_RTE_LIBRTE_MLX4_MAX_INLINE)\nendif\n\nifdef CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE\nCFLAGS += -DMLX4_PMD_TX_MP_CACHE=$(CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE)\nendif\n\nifdef CONFIG_RTE_LIBRTE_MLX4_SOFT_COUNTERS\nCFLAGS += -DMLX4_PMD_SOFT_COUNTERS=$(CONFIG_RTE_LIBRTE_MLX4_SOFT_COUNTERS)\nendif\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n\n# Generate and clean-up mlx4_autoconf.h.\n\nexport CC CFLAGS CPPFLAGS EXTRA_CFLAGS EXTRA_CPPFLAGS\nexport AUTO_CONFIG_CFLAGS = -Wno-error\n\nifndef V\nAUTOCONF_OUTPUT := >/dev/null\nendif\n\nmlx4_autoconf.h: $(RTE_SDK)/scripts/auto-config-h.sh\n\t$Q $(RM) -f -- '$@'\n\t$Q sh -- '$<' '$@' \\\n\t\tRSS_SUPPORT \\\n\t\tinfiniband/verbs.h \\\n\t\tenum IBV_EXP_DEVICE_UD_RSS $(AUTOCONF_OUTPUT)\n\t$Q sh -- '$<' '$@' \\\n\t\tINLINE_RECV \\\n\t\tinfiniband/verbs.h \\\n\t\tenum IBV_EXP_DEVICE_ATTR_INLINE_RECV_SZ $(AUTOCONF_OUTPUT)\n\t$Q sh -- '$<' '$@' \\\n\t\tHAVE_EXP_QUERY_DEVICE \\\n\t\tinfiniband/verbs.h \\\n\t\ttype 'struct ibv_exp_device_attr' $(AUTOCONF_OUTPUT)\n\t$Q sh -- '$<' '$@' \\\n\t\tHAVE_EXP_QP_BURST_CREATE_DISABLE_ETH_LOOPBACK \\\n\t\tinfiniband/verbs.h \\\n\t\tenum IBV_EXP_QP_BURST_CREATE_DISABLE_ETH_LOOPBACK \\\n\t\t$(AUTOCONF_OUTPUT)\n\nmlx4.o: mlx4_autoconf.h\n\nclean_mlx4: FORCE\n\t$Q rm -f -- mlx4_autoconf.h\n\nclean: clean_mlx4\n" }, { "path": "drivers/net/mlx4/mlx4.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright 2012-2015 6WIND S.A.\n * Copyright 2012 Mellanox.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Known limitations:\n * - RSS hash key and options cannot be modified.\n * - Hardware counters aren't implemented.\n */\n\n/* System headers. */\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/* Verbs header. */\n/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */\n#ifdef PEDANTIC\n#pragma GCC diagnostic ignored \"-pedantic\"\n#endif\n#include \n#ifdef PEDANTIC\n#pragma GCC diagnostic error \"-pedantic\"\n#endif\n\n/* DPDK headers don't like -pedantic. */\n#ifdef PEDANTIC\n#pragma GCC diagnostic ignored \"-pedantic\"\n#endif\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#ifdef PEDANTIC\n#pragma GCC diagnostic error \"-pedantic\"\n#endif\n\n/* Generated configuration header. */\n#include \"mlx4_autoconf.h\"\n\n/* PMD header. */\n#include \"mlx4.h\"\n\n/* Runtime logging through RTE_LOG() is enabled when not in debugging mode.\n * Intermediate LOG_*() macros add the required end-of-line characters. */\n#ifndef NDEBUG\n#define INFO(...) DEBUG(__VA_ARGS__)\n#define WARN(...) DEBUG(__VA_ARGS__)\n#define ERROR(...) DEBUG(__VA_ARGS__)\n#else\n#define LOG__(level, m, ...) \\\n\tRTE_LOG(level, PMD, MLX4_DRIVER_NAME \": \" m \"%c\", __VA_ARGS__)\n#define LOG_(level, ...) LOG__(level, __VA_ARGS__, '\\n')\n#define INFO(...) LOG_(INFO, __VA_ARGS__)\n#define WARN(...) LOG_(WARNING, __VA_ARGS__)\n#define ERROR(...) LOG_(ERR, __VA_ARGS__)\n#endif\n\n/* Convenience macros for accessing mbuf fields. */\n#define NEXT(m) ((m)->next)\n#define DATA_LEN(m) ((m)->data_len)\n#define PKT_LEN(m) ((m)->pkt_len)\n#define DATA_OFF(m) ((m)->data_off)\n#define SET_DATA_OFF(m, o) ((m)->data_off = (o))\n#define NB_SEGS(m) ((m)->nb_segs)\n#define PORT(m) ((m)->port)\n\n/* Work Request ID data type (64 bit). */\ntypedef union {\n\tstruct {\n\t\tuint32_t id;\n\t\tuint16_t offset;\n\t} data;\n\tuint64_t raw;\n} wr_id_t;\n\n#define WR_ID(o) (((wr_id_t *)&(o))->data)\n\n/* Compile-time check. */\nstatic inline void wr_id_t_check(void)\n{\n\twr_id_t check[1 + (2 * -!(sizeof(wr_id_t) == sizeof(uint64_t)))];\n\n\t(void)check;\n\t(void)wr_id_t_check;\n}\n\n/* Transpose flags. Useful to convert IBV to DPDK flags. */\n#define TRANSPOSE(val, from, to) \\\n\t(((from) >= (to)) ? \\\n\t (((val) & (from)) / ((from) / (to))) : \\\n\t (((val) & (from)) * ((to) / (from))))\n\nstruct mlx4_rxq_stats {\n\tunsigned int idx; /**< Mapping index. */\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\tuint64_t ipackets; /**< Total of successfully received packets. */\n\tuint64_t ibytes; /**< Total of successfully received bytes. */\n#endif\n\tuint64_t idropped; /**< Total of packets dropped when RX ring full. */\n\tuint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */\n};\n\nstruct mlx4_txq_stats {\n\tunsigned int idx; /**< Mapping index. */\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\tuint64_t opackets; /**< Total of successfully sent packets. */\n\tuint64_t obytes; /**< Total of successfully sent bytes. */\n#endif\n\tuint64_t odropped; /**< Total of packets not sent when TX ring full. */\n};\n\n/* RX element (scattered packets). */\nstruct rxq_elt_sp {\n\tstruct ibv_recv_wr wr; /* Work Request. */\n\tstruct ibv_sge sges[MLX4_PMD_SGE_WR_N]; /* Scatter/Gather Elements. */\n\tstruct rte_mbuf *bufs[MLX4_PMD_SGE_WR_N]; /* SGEs buffers. */\n};\n\n/* RX element. */\nstruct rxq_elt {\n\tstruct ibv_recv_wr wr; /* Work Request. */\n\tstruct ibv_sge sge; /* Scatter/Gather Element. */\n\t/* mbuf pointer is derived from WR_ID(wr.wr_id).offset. */\n};\n\n/* RX queue descriptor. */\nstruct rxq {\n\tstruct priv *priv; /* Back pointer to private data. */\n\tstruct rte_mempool *mp; /* Memory Pool for allocations. */\n\tstruct ibv_mr *mr; /* Memory Region (for mp). */\n\tstruct ibv_cq *cq; /* Completion Queue. */\n\tstruct ibv_qp *qp; /* Queue Pair. */\n\tstruct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */\n\tstruct ibv_exp_cq_family *if_cq; /* CQ interface. */\n\t/*\n\t * Each VLAN ID requires a separate flow steering rule.\n\t */\n\tBITFIELD_DECLARE(mac_configured, uint32_t, MLX4_MAX_MAC_ADDRESSES);\n\tstruct ibv_flow *mac_flow[MLX4_MAX_MAC_ADDRESSES][MLX4_MAX_VLAN_IDS];\n\tstruct ibv_flow *promisc_flow; /* Promiscuous flow. */\n\tstruct ibv_flow *allmulti_flow; /* Multicast flow. */\n\tunsigned int port_id; /* Port ID for incoming packets. */\n\tunsigned int elts_n; /* (*elts)[] length. */\n\tunsigned int elts_head; /* Current index in (*elts)[]. */\n\tunion {\n\t\tstruct rxq_elt_sp (*sp)[]; /* Scattered RX elements. */\n\t\tstruct rxq_elt (*no_sp)[]; /* RX elements. */\n\t} elts;\n\tunsigned int sp:1; /* Use scattered RX elements. */\n\tunsigned int csum:1; /* Enable checksum offloading. */\n\tunsigned int csum_l2tun:1; /* Same for L2 tunnels. */\n\tuint32_t mb_len; /* Length of a mp-issued mbuf. */\n\tstruct mlx4_rxq_stats stats; /* RX queue counters. */\n\tunsigned int socket; /* CPU socket ID for allocations. */\n\tstruct ibv_exp_res_domain *rd; /* Resource Domain. */\n};\n\n/* TX element. */\nstruct txq_elt {\n\tstruct rte_mbuf *buf;\n};\n\n/* Linear buffer type. It is used when transmitting buffers with too many\n * segments that do not fit the hardware queue (see max_send_sge).\n * Extra segments are copied (linearized) in such buffers, replacing the\n * last SGE during TX.\n * The size is arbitrary but large enough to hold a jumbo frame with\n * 8 segments considering mbuf.buf_len is about 2048 bytes. */\ntypedef uint8_t linear_t[16384];\n\n/* TX queue descriptor. */\nstruct txq {\n\tstruct priv *priv; /* Back pointer to private data. */\n\tstruct {\n\t\tstruct rte_mempool *mp; /* Cached Memory Pool. */\n\t\tstruct ibv_mr *mr; /* Memory Region (for mp). */\n\t\tuint32_t lkey; /* mr->lkey */\n\t} mp2mr[MLX4_PMD_TX_MP_CACHE]; /* MP to MR translation table. */\n\tstruct ibv_cq *cq; /* Completion Queue. */\n\tstruct ibv_qp *qp; /* Queue Pair. */\n\tstruct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */\n\tstruct ibv_exp_cq_family *if_cq; /* CQ interface. */\n#if MLX4_PMD_MAX_INLINE > 0\n\tuint32_t max_inline; /* Max inline send size <= MLX4_PMD_MAX_INLINE. */\n#endif\n\tunsigned int elts_n; /* (*elts)[] length. */\n\tstruct txq_elt (*elts)[]; /* TX elements. */\n\tunsigned int elts_head; /* Current index in (*elts)[]. */\n\tunsigned int elts_tail; /* First element awaiting completion. */\n\tunsigned int elts_comp; /* Number of completion requests. */\n\tunsigned int elts_comp_cd; /* Countdown for next completion request. */\n\tunsigned int elts_comp_cd_init; /* Initial value for countdown. */\n\tstruct mlx4_txq_stats stats; /* TX queue counters. */\n\tlinear_t (*elts_linear)[]; /* Linearized buffers. */\n\tstruct ibv_mr *mr_linear; /* Memory Region for linearized buffers. */\n\tunsigned int socket; /* CPU socket ID for allocations. */\n\tstruct ibv_exp_res_domain *rd; /* Resource Domain. */\n};\n\nstruct priv {\n\tstruct rte_eth_dev *dev; /* Ethernet device. */\n\tstruct ibv_context *ctx; /* Verbs context. */\n\tstruct ibv_device_attr device_attr; /* Device properties. */\n\tstruct ibv_pd *pd; /* Protection Domain. */\n\t/*\n\t * MAC addresses array and configuration bit-field.\n\t * An extra entry that cannot be modified by the DPDK is reserved\n\t * for broadcast frames (destination MAC address ff:ff:ff:ff:ff:ff).\n\t */\n\tstruct ether_addr mac[MLX4_MAX_MAC_ADDRESSES];\n\tBITFIELD_DECLARE(mac_configured, uint32_t, MLX4_MAX_MAC_ADDRESSES);\n\t/* VLAN filters. */\n\tstruct {\n\t\tunsigned int enabled:1; /* If enabled. */\n\t\tunsigned int id:12; /* VLAN ID (0-4095). */\n\t} vlan_filter[MLX4_MAX_VLAN_IDS]; /* VLAN filters table. */\n\t/* Device properties. */\n\tuint16_t mtu; /* Configured MTU. */\n\tuint8_t port; /* Physical port number. */\n\tunsigned int started:1; /* Device started, flows enabled. */\n\tunsigned int promisc:1; /* Device in promiscuous mode. */\n\tunsigned int allmulti:1; /* Device receives all multicast packets. */\n\tunsigned int hw_qpg:1; /* QP groups are supported. */\n\tunsigned int hw_tss:1; /* TSS is supported. */\n\tunsigned int hw_rss:1; /* RSS is supported. */\n\tunsigned int hw_csum:1; /* Checksum offload is supported. */\n\tunsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */\n\tunsigned int rss:1; /* RSS is enabled. */\n\tunsigned int vf:1; /* This is a VF device. */\n#ifdef INLINE_RECV\n\tunsigned int inl_recv_size; /* Inline recv size */\n#endif\n\tunsigned int max_rss_tbl_sz; /* Maximum number of RSS queues. */\n\t/* RX/TX queues. */\n\tstruct rxq rxq_parent; /* Parent queue when RSS is enabled. */\n\tunsigned int rxqs_n; /* RX queues array size. */\n\tunsigned int txqs_n; /* TX queues array size. */\n\tstruct rxq *(*rxqs)[]; /* RX queues. */\n\tstruct txq *(*txqs)[]; /* TX queues. */\n\trte_spinlock_t lock; /* Lock for control functions. */\n};\n\n/**\n * Lock private structure to protect it from concurrent access in the\n * control path.\n *\n * @param priv\n * Pointer to private structure.\n */\nstatic void\npriv_lock(struct priv *priv)\n{\n\trte_spinlock_lock(&priv->lock);\n}\n\n/**\n * Unlock private structure.\n *\n * @param priv\n * Pointer to private structure.\n */\nstatic void\npriv_unlock(struct priv *priv)\n{\n\trte_spinlock_unlock(&priv->lock);\n}\n\n/* Allocate a buffer on the stack and fill it with a printf format string. */\n#define MKSTR(name, ...) \\\n\tchar name[snprintf(NULL, 0, __VA_ARGS__) + 1]; \\\n\t\\\n\tsnprintf(name, sizeof(name), __VA_ARGS__)\n\n/**\n * Get interface name from private structure.\n *\n * @param[in] priv\n * Pointer to private structure.\n * @param[out] ifname\n * Interface name output buffer.\n *\n * @return\n * 0 on success, -1 on failure and errno is set.\n */\nstatic int\npriv_get_ifname(const struct priv *priv, char (*ifname)[IF_NAMESIZE])\n{\n\tDIR *dir;\n\tstruct dirent *dent;\n\tunsigned int dev_type = 0;\n\tunsigned int dev_port_prev = ~0u;\n\tchar match[IF_NAMESIZE] = \"\";\n\n\t{\n\t\tMKSTR(path, \"%s/device/net\", priv->ctx->device->ibdev_path);\n\n\t\tdir = opendir(path);\n\t\tif (dir == NULL)\n\t\t\treturn -1;\n\t}\n\twhile ((dent = readdir(dir)) != NULL) {\n\t\tchar *name = dent->d_name;\n\t\tFILE *file;\n\t\tunsigned int dev_port;\n\t\tint r;\n\n\t\tif ((name[0] == '.') &&\n\t\t ((name[1] == '\\0') ||\n\t\t ((name[1] == '.') && (name[2] == '\\0'))))\n\t\t\tcontinue;\n\n\t\tMKSTR(path, \"%s/device/net/%s/%s\",\n\t\t priv->ctx->device->ibdev_path, name,\n\t\t (dev_type ? \"dev_id\" : \"dev_port\"));\n\n\t\tfile = fopen(path, \"rb\");\n\t\tif (file == NULL) {\n\t\t\tif (errno != ENOENT)\n\t\t\t\tcontinue;\n\t\t\t/*\n\t\t\t * Switch to dev_id when dev_port does not exist as\n\t\t\t * is the case with Linux kernel versions < 3.15.\n\t\t\t */\ntry_dev_id:\n\t\t\tmatch[0] = '\\0';\n\t\t\tif (dev_type)\n\t\t\t\tbreak;\n\t\t\tdev_type = 1;\n\t\t\tdev_port_prev = ~0u;\n\t\t\trewinddir(dir);\n\t\t\tcontinue;\n\t\t}\n\t\tr = fscanf(file, (dev_type ? \"%x\" : \"%u\"), &dev_port);\n\t\tfclose(file);\n\t\tif (r != 1)\n\t\t\tcontinue;\n\t\t/*\n\t\t * Switch to dev_id when dev_port returns the same value for\n\t\t * all ports. May happen when using a MOFED release older than\n\t\t * 3.0 with a Linux kernel >= 3.15.\n\t\t */\n\t\tif (dev_port == dev_port_prev)\n\t\t\tgoto try_dev_id;\n\t\tdev_port_prev = dev_port;\n\t\tif (dev_port == (priv->port - 1u))\n\t\t\tsnprintf(match, sizeof(match), \"%s\", name);\n\t}\n\tclosedir(dir);\n\tif (match[0] == '\\0')\n\t\treturn -1;\n\tstrncpy(*ifname, match, sizeof(*ifname));\n\treturn 0;\n}\n\n/**\n * Read from sysfs entry.\n *\n * @param[in] priv\n * Pointer to private structure.\n * @param[in] entry\n * Entry name relative to sysfs path.\n * @param[out] buf\n * Data output buffer.\n * @param size\n * Buffer size.\n *\n * @return\n * 0 on success, -1 on failure and errno is set.\n */\nstatic int\npriv_sysfs_read(const struct priv *priv, const char *entry,\n\t\tchar *buf, size_t size)\n{\n\tchar ifname[IF_NAMESIZE];\n\tFILE *file;\n\tint ret;\n\tint err;\n\n\tif (priv_get_ifname(priv, &ifname))\n\t\treturn -1;\n\n\tMKSTR(path, \"%s/device/net/%s/%s\", priv->ctx->device->ibdev_path,\n\t ifname, entry);\n\n\tfile = fopen(path, \"rb\");\n\tif (file == NULL)\n\t\treturn -1;\n\tret = fread(buf, 1, size, file);\n\terr = errno;\n\tif (((size_t)ret < size) && (ferror(file)))\n\t\tret = -1;\n\telse\n\t\tret = size;\n\tfclose(file);\n\terrno = err;\n\treturn ret;\n}\n\n/**\n * Write to sysfs entry.\n *\n * @param[in] priv\n * Pointer to private structure.\n * @param[in] entry\n * Entry name relative to sysfs path.\n * @param[in] buf\n * Data buffer.\n * @param size\n * Buffer size.\n *\n * @return\n * 0 on success, -1 on failure and errno is set.\n */\nstatic int\npriv_sysfs_write(const struct priv *priv, const char *entry,\n\t\t char *buf, size_t size)\n{\n\tchar ifname[IF_NAMESIZE];\n\tFILE *file;\n\tint ret;\n\tint err;\n\n\tif (priv_get_ifname(priv, &ifname))\n\t\treturn -1;\n\n\tMKSTR(path, \"%s/device/net/%s/%s\", priv->ctx->device->ibdev_path,\n\t ifname, entry);\n\n\tfile = fopen(path, \"wb\");\n\tif (file == NULL)\n\t\treturn -1;\n\tret = fwrite(buf, 1, size, file);\n\terr = errno;\n\tif (((size_t)ret < size) || (ferror(file)))\n\t\tret = -1;\n\telse\n\t\tret = size;\n\tfclose(file);\n\terrno = err;\n\treturn ret;\n}\n\n/**\n * Get unsigned long sysfs property.\n *\n * @param priv\n * Pointer to private structure.\n * @param[in] name\n * Entry name relative to sysfs path.\n * @param[out] value\n * Value output buffer.\n *\n * @return\n * 0 on success, -1 on failure and errno is set.\n */\nstatic int\npriv_get_sysfs_ulong(struct priv *priv, const char *name, unsigned long *value)\n{\n\tint ret;\n\tunsigned long value_ret;\n\tchar value_str[32];\n\n\tret = priv_sysfs_read(priv, name, value_str, (sizeof(value_str) - 1));\n\tif (ret == -1) {\n\t\tDEBUG(\"cannot read %s value from sysfs: %s\",\n\t\t name, strerror(errno));\n\t\treturn -1;\n\t}\n\tvalue_str[ret] = '\\0';\n\terrno = 0;\n\tvalue_ret = strtoul(value_str, NULL, 0);\n\tif (errno) {\n\t\tDEBUG(\"invalid %s value `%s': %s\", name, value_str,\n\t\t strerror(errno));\n\t\treturn -1;\n\t}\n\t*value = value_ret;\n\treturn 0;\n}\n\n/**\n * Set unsigned long sysfs property.\n *\n * @param priv\n * Pointer to private structure.\n * @param[in] name\n * Entry name relative to sysfs path.\n * @param value\n * Value to set.\n *\n * @return\n * 0 on success, -1 on failure and errno is set.\n */\nstatic int\npriv_set_sysfs_ulong(struct priv *priv, const char *name, unsigned long value)\n{\n\tint ret;\n\tMKSTR(value_str, \"%lu\", value);\n\n\tret = priv_sysfs_write(priv, name, value_str, (sizeof(value_str) - 1));\n\tif (ret == -1) {\n\t\tDEBUG(\"cannot write %s `%s' (%lu) to sysfs: %s\",\n\t\t name, value_str, value, strerror(errno));\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/**\n * Perform ifreq ioctl() on associated Ethernet device.\n *\n * @param[in] priv\n * Pointer to private structure.\n * @param req\n * Request number to pass to ioctl().\n * @param[out] ifr\n * Interface request structure output buffer.\n *\n * @return\n * 0 on success, -1 on failure and errno is set.\n */\nstatic int\npriv_ifreq(const struct priv *priv, int req, struct ifreq *ifr)\n{\n\tint sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_IP);\n\tint ret = -1;\n\n\tif (sock == -1)\n\t\treturn ret;\n\tif (priv_get_ifname(priv, &ifr->ifr_name) == 0)\n\t\tret = ioctl(sock, req, ifr);\n\tclose(sock);\n\treturn ret;\n}\n\n/**\n * Get device MTU.\n *\n * @param priv\n * Pointer to private structure.\n * @param[out] mtu\n * MTU value output buffer.\n *\n * @return\n * 0 on success, -1 on failure and errno is set.\n */\nstatic int\npriv_get_mtu(struct priv *priv, uint16_t *mtu)\n{\n\tunsigned long ulong_mtu;\n\n\tif (priv_get_sysfs_ulong(priv, \"mtu\", &ulong_mtu) == -1)\n\t\treturn -1;\n\t*mtu = ulong_mtu;\n\treturn 0;\n}\n\n/**\n * Set device MTU.\n *\n * @param priv\n * Pointer to private structure.\n * @param mtu\n * MTU value to set.\n *\n * @return\n * 0 on success, -1 on failure and errno is set.\n */\nstatic int\npriv_set_mtu(struct priv *priv, uint16_t mtu)\n{\n\treturn priv_set_sysfs_ulong(priv, \"mtu\", mtu);\n}\n\n/**\n * Set device flags.\n *\n * @param priv\n * Pointer to private structure.\n * @param keep\n * Bitmask for flags that must remain untouched.\n * @param flags\n * Bitmask for flags to modify.\n *\n * @return\n * 0 on success, -1 on failure and errno is set.\n */\nstatic int\npriv_set_flags(struct priv *priv, unsigned int keep, unsigned int flags)\n{\n\tunsigned long tmp;\n\n\tif (priv_get_sysfs_ulong(priv, \"flags\", &tmp) == -1)\n\t\treturn -1;\n\ttmp &= keep;\n\ttmp |= flags;\n\treturn priv_set_sysfs_ulong(priv, \"flags\", tmp);\n}\n\n/* Device configuration. */\n\nstatic int\nrxq_setup(struct rte_eth_dev *dev, struct rxq *rxq, uint16_t desc,\n\t unsigned int socket, const struct rte_eth_rxconf *conf,\n\t struct rte_mempool *mp);\n\nstatic void\nrxq_cleanup(struct rxq *rxq);\n\n/**\n * Ethernet device configuration.\n *\n * Prepare the driver for a given number of TX and RX queues.\n * Allocate parent RSS queue when several RX queues are requested.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\ndev_configure(struct rte_eth_dev *dev)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tunsigned int rxqs_n = dev->data->nb_rx_queues;\n\tunsigned int txqs_n = dev->data->nb_tx_queues;\n\tunsigned int tmp;\n\tint ret;\n\n\tpriv->rxqs = (void *)dev->data->rx_queues;\n\tpriv->txqs = (void *)dev->data->tx_queues;\n\tif (txqs_n != priv->txqs_n) {\n\t\tINFO(\"%p: TX queues number update: %u -> %u\",\n\t\t (void *)dev, priv->txqs_n, txqs_n);\n\t\tpriv->txqs_n = txqs_n;\n\t}\n\tif (rxqs_n == priv->rxqs_n)\n\t\treturn 0;\n\tINFO(\"%p: RX queues number update: %u -> %u\",\n\t (void *)dev, priv->rxqs_n, rxqs_n);\n\t/* If RSS is enabled, disable it first. */\n\tif (priv->rss) {\n\t\tunsigned int i;\n\n\t\t/* Only if there are no remaining child RX queues. */\n\t\tfor (i = 0; (i != priv->rxqs_n); ++i)\n\t\t\tif ((*priv->rxqs)[i] != NULL)\n\t\t\t\treturn EINVAL;\n\t\trxq_cleanup(&priv->rxq_parent);\n\t\tpriv->rss = 0;\n\t\tpriv->rxqs_n = 0;\n\t}\n\tif (rxqs_n <= 1) {\n\t\t/* Nothing else to do. */\n\t\tpriv->rxqs_n = rxqs_n;\n\t\treturn 0;\n\t}\n\t/* Allocate a new RSS parent queue if supported by hardware. */\n\tif (!priv->hw_rss) {\n\t\tERROR(\"%p: only a single RX queue can be configured when\"\n\t\t \" hardware doesn't support RSS\",\n\t\t (void *)dev);\n\t\treturn EINVAL;\n\t}\n\t/* Fail if hardware doesn't support that many RSS queues. */\n\tif (rxqs_n >= priv->max_rss_tbl_sz) {\n\t\tERROR(\"%p: only %u RX queues can be configured for RSS\",\n\t\t (void *)dev, priv->max_rss_tbl_sz);\n\t\treturn EINVAL;\n\t}\n\tpriv->rss = 1;\n\ttmp = priv->rxqs_n;\n\tpriv->rxqs_n = rxqs_n;\n\tret = rxq_setup(dev, &priv->rxq_parent, 0, 0, NULL, NULL);\n\tif (!ret)\n\t\treturn 0;\n\t/* Failure, rollback. */\n\tpriv->rss = 0;\n\tpriv->rxqs_n = tmp;\n\tassert(ret > 0);\n\treturn ret;\n}\n\n/**\n * DPDK callback for Ethernet device configuration.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n *\n * @return\n * 0 on success, negative errno value on failure.\n */\nstatic int\nmlx4_dev_configure(struct rte_eth_dev *dev)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tint ret;\n\n\tpriv_lock(priv);\n\tret = dev_configure(dev);\n\tassert(ret >= 0);\n\tpriv_unlock(priv);\n\treturn -ret;\n}\n\n/* TX queues handling. */\n\n/**\n * Allocate TX queue elements.\n *\n * @param txq\n * Pointer to TX queue structure.\n * @param elts_n\n * Number of elements to allocate.\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\ntxq_alloc_elts(struct txq *txq, unsigned int elts_n)\n{\n\tunsigned int i;\n\tstruct txq_elt (*elts)[elts_n] =\n\t\trte_calloc_socket(\"TXQ\", 1, sizeof(*elts), 0, txq->socket);\n\tlinear_t (*elts_linear)[elts_n] =\n\t\trte_calloc_socket(\"TXQ\", 1, sizeof(*elts_linear), 0,\n\t\t\t\t txq->socket);\n\tstruct ibv_mr *mr_linear = NULL;\n\tint ret = 0;\n\n\tif ((elts == NULL) || (elts_linear == NULL)) {\n\t\tERROR(\"%p: can't allocate packets array\", (void *)txq);\n\t\tret = ENOMEM;\n\t\tgoto error;\n\t}\n\tmr_linear =\n\t\tibv_reg_mr(txq->priv->pd, elts_linear, sizeof(*elts_linear),\n\t\t\t (IBV_ACCESS_LOCAL_WRITE | IBV_ACCESS_REMOTE_WRITE));\n\tif (mr_linear == NULL) {\n\t\tERROR(\"%p: unable to configure MR, ibv_reg_mr() failed\",\n\t\t (void *)txq);\n\t\tret = EINVAL;\n\t\tgoto error;\n\t}\n\tfor (i = 0; (i != elts_n); ++i) {\n\t\tstruct txq_elt *elt = &(*elts)[i];\n\n\t\telt->buf = NULL;\n\t}\n\tDEBUG(\"%p: allocated and configured %u WRs\", (void *)txq, elts_n);\n\ttxq->elts_n = elts_n;\n\ttxq->elts = elts;\n\ttxq->elts_head = 0;\n\ttxq->elts_tail = 0;\n\ttxq->elts_comp = 0;\n\t/* Request send completion every MLX4_PMD_TX_PER_COMP_REQ packets or\n\t * at least 4 times per ring. */\n\ttxq->elts_comp_cd_init =\n\t\t((MLX4_PMD_TX_PER_COMP_REQ < (elts_n / 4)) ?\n\t\t MLX4_PMD_TX_PER_COMP_REQ : (elts_n / 4));\n\ttxq->elts_comp_cd = txq->elts_comp_cd_init;\n\ttxq->elts_linear = elts_linear;\n\ttxq->mr_linear = mr_linear;\n\tassert(ret == 0);\n\treturn 0;\nerror:\n\tif (mr_linear != NULL)\n\t\tclaim_zero(ibv_dereg_mr(mr_linear));\n\n\trte_free(elts_linear);\n\trte_free(elts);\n\n\tDEBUG(\"%p: failed, freed everything\", (void *)txq);\n\tassert(ret > 0);\n\treturn ret;\n}\n\n/**\n * Free TX queue elements.\n *\n * @param txq\n * Pointer to TX queue structure.\n */\nstatic void\ntxq_free_elts(struct txq *txq)\n{\n\tunsigned int i;\n\tunsigned int elts_n = txq->elts_n;\n\tstruct txq_elt (*elts)[elts_n] = txq->elts;\n\tlinear_t (*elts_linear)[elts_n] = txq->elts_linear;\n\tstruct ibv_mr *mr_linear = txq->mr_linear;\n\n\tDEBUG(\"%p: freeing WRs\", (void *)txq);\n\ttxq->elts_n = 0;\n\ttxq->elts = NULL;\n\ttxq->elts_linear = NULL;\n\ttxq->mr_linear = NULL;\n\tif (mr_linear != NULL)\n\t\tclaim_zero(ibv_dereg_mr(mr_linear));\n\n\trte_free(elts_linear);\n\tif (elts == NULL)\n\t\treturn;\n\tfor (i = 0; (i != elemof(*elts)); ++i) {\n\t\tstruct txq_elt *elt = &(*elts)[i];\n\n\t\tif (elt->buf == NULL)\n\t\t\tcontinue;\n\t\trte_pktmbuf_free(elt->buf);\n\t}\n\trte_free(elts);\n}\n\n\n/**\n * Clean up a TX queue.\n *\n * Destroy objects, free allocated memory and reset the structure for reuse.\n *\n * @param txq\n * Pointer to TX queue structure.\n */\nstatic void\ntxq_cleanup(struct txq *txq)\n{\n\tstruct ibv_exp_release_intf_params params;\n\tsize_t i;\n\n\tDEBUG(\"cleaning up %p\", (void *)txq);\n\ttxq_free_elts(txq);\n\tif (txq->if_qp != NULL) {\n\t\tassert(txq->priv != NULL);\n\t\tassert(txq->priv->ctx != NULL);\n\t\tassert(txq->qp != NULL);\n\t\tparams = (struct ibv_exp_release_intf_params){\n\t\t\t.comp_mask = 0,\n\t\t};\n\t\tclaim_zero(ibv_exp_release_intf(txq->priv->ctx,\n\t\t\t\t\t\ttxq->if_qp,\n\t\t\t\t\t\t¶ms));\n\t}\n\tif (txq->if_cq != NULL) {\n\t\tassert(txq->priv != NULL);\n\t\tassert(txq->priv->ctx != NULL);\n\t\tassert(txq->cq != NULL);\n\t\tparams = (struct ibv_exp_release_intf_params){\n\t\t\t.comp_mask = 0,\n\t\t};\n\t\tclaim_zero(ibv_exp_release_intf(txq->priv->ctx,\n\t\t\t\t\t\ttxq->if_cq,\n\t\t\t\t\t\t¶ms));\n\t}\n\tif (txq->qp != NULL)\n\t\tclaim_zero(ibv_destroy_qp(txq->qp));\n\tif (txq->cq != NULL)\n\t\tclaim_zero(ibv_destroy_cq(txq->cq));\n\tif (txq->rd != NULL) {\n\t\tstruct ibv_exp_destroy_res_domain_attr attr = {\n\t\t\t.comp_mask = 0,\n\t\t};\n\n\t\tassert(txq->priv != NULL);\n\t\tassert(txq->priv->ctx != NULL);\n\t\tclaim_zero(ibv_exp_destroy_res_domain(txq->priv->ctx,\n\t\t\t\t\t\t txq->rd,\n\t\t\t\t\t\t &attr));\n\t}\n\tfor (i = 0; (i != elemof(txq->mp2mr)); ++i) {\n\t\tif (txq->mp2mr[i].mp == NULL)\n\t\t\tbreak;\n\t\tassert(txq->mp2mr[i].mr != NULL);\n\t\tclaim_zero(ibv_dereg_mr(txq->mp2mr[i].mr));\n\t}\n\tmemset(txq, 0, sizeof(*txq));\n}\n\n/**\n * Manage TX completions.\n *\n * When sending a burst, mlx4_tx_burst() posts several WRs.\n * To improve performance, a completion event is only required once every\n * MLX4_PMD_TX_PER_COMP_REQ sends. Doing so discards completion information\n * for other WRs, but this information would not be used anyway.\n *\n * @param txq\n * Pointer to TX queue structure.\n *\n * @return\n * 0 on success, -1 on failure.\n */\nstatic int\ntxq_complete(struct txq *txq)\n{\n\tunsigned int elts_comp = txq->elts_comp;\n\tunsigned int elts_tail = txq->elts_tail;\n\tconst unsigned int elts_n = txq->elts_n;\n\tint wcs_n;\n\n\tif (unlikely(elts_comp == 0))\n\t\treturn 0;\n#ifdef DEBUG_SEND\n\tDEBUG(\"%p: processing %u work requests completions\",\n\t (void *)txq, elts_comp);\n#endif\n\twcs_n = txq->if_cq->poll_cnt(txq->cq, elts_comp);\n\tif (unlikely(wcs_n == 0))\n\t\treturn 0;\n\tif (unlikely(wcs_n < 0)) {\n\t\tDEBUG(\"%p: ibv_poll_cq() failed (wcs_n=%d)\",\n\t\t (void *)txq, wcs_n);\n\t\treturn -1;\n\t}\n\telts_comp -= wcs_n;\n\tassert(elts_comp <= txq->elts_comp);\n\t/*\n\t * Assume WC status is successful as nothing can be done about it\n\t * anyway.\n\t */\n\telts_tail += wcs_n * txq->elts_comp_cd_init;\n\tif (elts_tail >= elts_n)\n\t\telts_tail -= elts_n;\n\ttxq->elts_tail = elts_tail;\n\ttxq->elts_comp = elts_comp;\n\treturn 0;\n}\n\n/**\n * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].\n * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,\n * remove an entry first.\n *\n * @param txq\n * Pointer to TX queue structure.\n * @param[in] mp\n * Memory Pool for which a Memory Region lkey must be returned.\n *\n * @return\n * mr->lkey on success, (uint32_t)-1 on failure.\n */\nstatic uint32_t\ntxq_mp2mr(struct txq *txq, struct rte_mempool *mp)\n{\n\tunsigned int i;\n\tstruct ibv_mr *mr;\n\n\tfor (i = 0; (i != elemof(txq->mp2mr)); ++i) {\n\t\tif (unlikely(txq->mp2mr[i].mp == NULL)) {\n\t\t\t/* Unknown MP, add a new MR for it. */\n\t\t\tbreak;\n\t\t}\n\t\tif (txq->mp2mr[i].mp == mp) {\n\t\t\tassert(txq->mp2mr[i].lkey != (uint32_t)-1);\n\t\t\tassert(txq->mp2mr[i].mr->lkey == txq->mp2mr[i].lkey);\n\t\t\treturn txq->mp2mr[i].lkey;\n\t\t}\n\t}\n\t/* Add a new entry, register MR first. */\n\tDEBUG(\"%p: discovered new memory pool %p\", (void *)txq, (void *)mp);\n\tmr = ibv_reg_mr(txq->priv->pd,\n\t\t\t(void *)mp->elt_va_start,\n\t\t\t(mp->elt_va_end - mp->elt_va_start),\n\t\t\t(IBV_ACCESS_LOCAL_WRITE | IBV_ACCESS_REMOTE_WRITE));\n\tif (unlikely(mr == NULL)) {\n\t\tDEBUG(\"%p: unable to configure MR, ibv_reg_mr() failed.\",\n\t\t (void *)txq);\n\t\treturn (uint32_t)-1;\n\t}\n\tif (unlikely(i == elemof(txq->mp2mr))) {\n\t\t/* Table is full, remove oldest entry. */\n\t\tDEBUG(\"%p: MR <-> MP table full, dropping oldest entry.\",\n\t\t (void *)txq);\n\t\t--i;\n\t\tclaim_zero(ibv_dereg_mr(txq->mp2mr[i].mr));\n\t\tmemmove(&txq->mp2mr[0], &txq->mp2mr[1],\n\t\t\t(sizeof(txq->mp2mr) - sizeof(txq->mp2mr[0])));\n\t}\n\t/* Store the new entry. */\n\ttxq->mp2mr[i].mp = mp;\n\ttxq->mp2mr[i].mr = mr;\n\ttxq->mp2mr[i].lkey = mr->lkey;\n\tDEBUG(\"%p: new MR lkey for MP %p: 0x%08\" PRIu32,\n\t (void *)txq, (void *)mp, txq->mp2mr[i].lkey);\n\treturn txq->mp2mr[i].lkey;\n}\n\n#if MLX4_PMD_SGE_WR_N > 1\n\n/**\n * Copy scattered mbuf contents to a single linear buffer.\n *\n * @param[out] linear\n * Linear output buffer.\n * @param[in] buf\n * Scattered input buffer.\n *\n * @return\n * Number of bytes copied to the output buffer or 0 if not large enough.\n */\nstatic unsigned int\nlinearize_mbuf(linear_t *linear, struct rte_mbuf *buf)\n{\n\tunsigned int size = 0;\n\tunsigned int offset;\n\n\tdo {\n\t\tunsigned int len = DATA_LEN(buf);\n\n\t\toffset = size;\n\t\tsize += len;\n\t\tif (unlikely(size > sizeof(*linear)))\n\t\t\treturn 0;\n\t\tmemcpy(&(*linear)[offset],\n\t\t rte_pktmbuf_mtod(buf, uint8_t *),\n\t\t len);\n\t\tbuf = NEXT(buf);\n\t} while (buf != NULL);\n\treturn size;\n}\n\n/**\n * Handle scattered buffers for mlx4_tx_burst().\n *\n * @param txq\n * TX queue structure.\n * @param segs\n * Number of segments in buf.\n * @param elt\n * TX queue element to fill.\n * @param[in] buf\n * Buffer to process.\n * @param elts_head\n * Index of the linear buffer to use if necessary (normally txq->elts_head).\n * @param[out] sges\n * Array filled with SGEs on success.\n *\n * @return\n * A structure containing the processed packet size in bytes and the\n * number of SGEs. Both fields are set to (unsigned int)-1 in case of\n * failure.\n */\nstatic struct tx_burst_sg_ret {\n\tunsigned int length;\n\tunsigned int num;\n}\ntx_burst_sg(struct txq *txq, unsigned int segs, struct txq_elt *elt,\n\t struct rte_mbuf *buf, unsigned int elts_head,\n\t struct ibv_sge (*sges)[MLX4_PMD_SGE_WR_N])\n{\n\tunsigned int sent_size = 0;\n\tunsigned int j;\n\tint linearize = 0;\n\n\t/* When there are too many segments, extra segments are\n\t * linearized in the last SGE. */\n\tif (unlikely(segs > elemof(*sges))) {\n\t\tsegs = (elemof(*sges) - 1);\n\t\tlinearize = 1;\n\t}\n\t/* Update element. */\n\telt->buf = buf;\n\t/* Register segments as SGEs. */\n\tfor (j = 0; (j != segs); ++j) {\n\t\tstruct ibv_sge *sge = &(*sges)[j];\n\t\tuint32_t lkey;\n\n\t\t/* Retrieve Memory Region key for this memory pool. */\n\t\tlkey = txq_mp2mr(txq, buf->pool);\n\t\tif (unlikely(lkey == (uint32_t)-1)) {\n\t\t\t/* MR does not exist. */\n\t\t\tDEBUG(\"%p: unable to get MP <-> MR association\",\n\t\t\t (void *)txq);\n\t\t\t/* Clean up TX element. */\n\t\t\telt->buf = NULL;\n\t\t\tgoto stop;\n\t\t}\n\t\t/* Update SGE. */\n\t\tsge->addr = rte_pktmbuf_mtod(buf, uintptr_t);\n\t\tif (txq->priv->vf)\n\t\t\trte_prefetch0((volatile void *)\n\t\t\t\t (uintptr_t)sge->addr);\n\t\tsge->length = DATA_LEN(buf);\n\t\tsge->lkey = lkey;\n\t\tsent_size += sge->length;\n\t\tbuf = NEXT(buf);\n\t}\n\t/* If buf is not NULL here and is not going to be linearized,\n\t * nb_segs is not valid. */\n\tassert(j == segs);\n\tassert((buf == NULL) || (linearize));\n\t/* Linearize extra segments. */\n\tif (linearize) {\n\t\tstruct ibv_sge *sge = &(*sges)[segs];\n\t\tlinear_t *linear = &(*txq->elts_linear)[elts_head];\n\t\tunsigned int size = linearize_mbuf(linear, buf);\n\n\t\tassert(segs == (elemof(*sges) - 1));\n\t\tif (size == 0) {\n\t\t\t/* Invalid packet. */\n\t\t\tDEBUG(\"%p: packet too large to be linearized.\",\n\t\t\t (void *)txq);\n\t\t\t/* Clean up TX element. */\n\t\t\telt->buf = NULL;\n\t\t\tgoto stop;\n\t\t}\n\t\t/* If MLX4_PMD_SGE_WR_N is 1, free mbuf immediately. */\n\t\tif (elemof(*sges) == 1) {\n\t\t\tdo {\n\t\t\t\tstruct rte_mbuf *next = NEXT(buf);\n\n\t\t\t\trte_pktmbuf_free_seg(buf);\n\t\t\t\tbuf = next;\n\t\t\t} while (buf != NULL);\n\t\t\telt->buf = NULL;\n\t\t}\n\t\t/* Update SGE. */\n\t\tsge->addr = (uintptr_t)&(*linear)[0];\n\t\tsge->length = size;\n\t\tsge->lkey = txq->mr_linear->lkey;\n\t\tsent_size += size;\n\t}\n\treturn (struct tx_burst_sg_ret){\n\t\t.length = sent_size,\n\t\t.num = segs,\n\t};\nstop:\n\treturn (struct tx_burst_sg_ret){\n\t\t.length = -1,\n\t\t.num = -1,\n\t};\n}\n\n#endif /* MLX4_PMD_SGE_WR_N > 1 */\n\n/**\n * DPDK callback for TX.\n *\n * @param dpdk_txq\n * Generic pointer to TX queue structure.\n * @param[in] pkts\n * Packets to transmit.\n * @param pkts_n\n * Number of packets in array.\n *\n * @return\n * Number of packets successfully transmitted (<= pkts_n).\n */\nstatic uint16_t\nmlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n{\n\tstruct txq *txq = (struct txq *)dpdk_txq;\n\tunsigned int elts_head = txq->elts_head;\n\tconst unsigned int elts_tail = txq->elts_tail;\n\tconst unsigned int elts_n = txq->elts_n;\n\tunsigned int elts_comp_cd = txq->elts_comp_cd;\n\tunsigned int elts_comp = 0;\n\tunsigned int i;\n\tunsigned int max;\n\tint err;\n\n\tassert(elts_comp_cd != 0);\n\ttxq_complete(txq);\n\tmax = (elts_n - (elts_head - elts_tail));\n\tif (max > elts_n)\n\t\tmax -= elts_n;\n\tassert(max >= 1);\n\tassert(max <= elts_n);\n\t/* Always leave one free entry in the ring. */\n\t--max;\n\tif (max == 0)\n\t\treturn 0;\n\tif (max > pkts_n)\n\t\tmax = pkts_n;\n\tfor (i = 0; (i != max); ++i) {\n\t\tstruct rte_mbuf *buf = pkts[i];\n\t\tunsigned int elts_head_next =\n\t\t\t(((elts_head + 1) == elts_n) ? 0 : elts_head + 1);\n\t\tstruct txq_elt *elt_next = &(*txq->elts)[elts_head_next];\n\t\tstruct txq_elt *elt = &(*txq->elts)[elts_head];\n\t\tunsigned int segs = NB_SEGS(buf);\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t\tunsigned int sent_size = 0;\n#endif\n\t\tuint32_t send_flags = 0;\n\n\t\t/* Clean up old buffer. */\n\t\tif (likely(elt->buf != NULL)) {\n\t\t\tstruct rte_mbuf *tmp = elt->buf;\n\n\t\t\t/* Faster than rte_pktmbuf_free(). */\n\t\t\tdo {\n\t\t\t\tstruct rte_mbuf *next = NEXT(tmp);\n\n\t\t\t\trte_pktmbuf_free_seg(tmp);\n\t\t\t\ttmp = next;\n\t\t\t} while (tmp != NULL);\n\t\t}\n\t\t/* Request TX completion. */\n\t\tif (unlikely(--elts_comp_cd == 0)) {\n\t\t\telts_comp_cd = txq->elts_comp_cd_init;\n\t\t\t++elts_comp;\n\t\t\tsend_flags |= IBV_EXP_QP_BURST_SIGNALED;\n\t\t}\n\t\t/* Should we enable HW CKSUM offload */\n\t\tif (buf->ol_flags &\n\t\t (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {\n\t\t\tsend_flags |= IBV_EXP_QP_BURST_IP_CSUM;\n\t\t\t/* HW does not support checksum offloads at arbitrary\n\t\t\t * offsets but automatically recognizes the packet\n\t\t\t * type. For inner L3/L4 checksums, only VXLAN (UDP)\n\t\t\t * tunnels are currently supported. */\n#ifdef RTE_NEXT_ABI\n\t\t\tif (RTE_ETH_IS_TUNNEL_PKT(buf->packet_type))\n#else\n\t\t\t/* FIXME: since PKT_TX_UDP_TUNNEL_PKT has been removed,\n\t\t\t * the outer packet type is unknown. All we know is\n\t\t\t * that the L2 header is of unusual length (not\n\t\t\t * ETHER_HDR_LEN with or without 802.1Q header). */\n\t\t\tif ((buf->l2_len != ETHER_HDR_LEN) &&\n\t\t\t (buf->l2_len != (ETHER_HDR_LEN + 4)))\n#endif\n\t\t\t\tsend_flags |= IBV_EXP_QP_BURST_TUNNEL;\n\t\t}\n\t\tif (likely(segs == 1)) {\n\t\t\tuintptr_t addr;\n\t\t\tuint32_t length;\n\t\t\tuint32_t lkey;\n\n\t\t\t/* Retrieve buffer information. */\n\t\t\taddr = rte_pktmbuf_mtod(buf, uintptr_t);\n\t\t\tlength = DATA_LEN(buf);\n\t\t\t/* Retrieve Memory Region key for this memory pool. */\n\t\t\tlkey = txq_mp2mr(txq, buf->pool);\n\t\t\tif (unlikely(lkey == (uint32_t)-1)) {\n\t\t\t\t/* MR does not exist. */\n\t\t\t\tDEBUG(\"%p: unable to get MP <-> MR\"\n\t\t\t\t \" association\", (void *)txq);\n\t\t\t\t/* Clean up TX element. */\n\t\t\t\telt->buf = NULL;\n\t\t\t\tgoto stop;\n\t\t\t}\n\t\t\t/* Update element. */\n\t\t\telt->buf = buf;\n\t\t\tif (txq->priv->vf)\n\t\t\t\trte_prefetch0((volatile void *)\n\t\t\t\t\t (uintptr_t)addr);\n\t\t\tRTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);\n\t\t\t/* Put packet into send queue. */\n#if MLX4_PMD_MAX_INLINE > 0\n\t\t\tif (length <= txq->max_inline)\n\t\t\t\terr = txq->if_qp->send_pending_inline\n\t\t\t\t\t(txq->qp,\n\t\t\t\t\t (void *)addr,\n\t\t\t\t\t length,\n\t\t\t\t\t send_flags);\n\t\t\telse\n#endif\n\t\t\t\terr = txq->if_qp->send_pending\n\t\t\t\t\t(txq->qp,\n\t\t\t\t\t addr,\n\t\t\t\t\t length,\n\t\t\t\t\t lkey,\n\t\t\t\t\t send_flags);\n\t\t\tif (unlikely(err))\n\t\t\t\tgoto stop;\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t\t\tsent_size += length;\n#endif\n\t\t} else {\n#if MLX4_PMD_SGE_WR_N > 1\n\t\t\tstruct ibv_sge sges[MLX4_PMD_SGE_WR_N];\n\t\t\tstruct tx_burst_sg_ret ret;\n\n\t\t\tret = tx_burst_sg(txq, segs, elt, buf, elts_head,\n\t\t\t\t\t &sges);\n\t\t\tif (ret.length == (unsigned int)-1)\n\t\t\t\tgoto stop;\n\t\t\tRTE_MBUF_PREFETCH_TO_FREE(elt_next->buf);\n\t\t\t/* Put SG list into send queue. */\n\t\t\terr = txq->if_qp->send_pending_sg_list\n\t\t\t\t(txq->qp,\n\t\t\t\t sges,\n\t\t\t\t ret.num,\n\t\t\t\t send_flags);\n\t\t\tif (unlikely(err))\n\t\t\t\tgoto stop;\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t\t\tsent_size += ret.length;\n#endif\n#else /* MLX4_PMD_SGE_WR_N > 1 */\n\t\t\tDEBUG(\"%p: TX scattered buffers support not\"\n\t\t\t \" compiled in\", (void *)txq);\n\t\t\tgoto stop;\n#endif /* MLX4_PMD_SGE_WR_N > 1 */\n\t\t}\n\t\telts_head = elts_head_next;\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t\t/* Increment sent bytes counter. */\n\t\ttxq->stats.obytes += sent_size;\n#endif\n\t}\nstop:\n\t/* Take a shortcut if nothing must be sent. */\n\tif (unlikely(i == 0))\n\t\treturn 0;\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t/* Increment sent packets counter. */\n\ttxq->stats.opackets += i;\n#endif\n\t/* Ring QP doorbell. */\n\terr = txq->if_qp->send_flush(txq->qp);\n\tif (unlikely(err)) {\n\t\t/* A nonzero value is not supposed to be returned.\n\t\t * Nothing can be done about it. */\n\t\tDEBUG(\"%p: send_flush() failed with error %d\",\n\t\t (void *)txq, err);\n\t}\n\ttxq->elts_head = elts_head;\n\ttxq->elts_comp += elts_comp;\n\ttxq->elts_comp_cd = elts_comp_cd;\n\treturn i;\n}\n\n/**\n * Configure a TX queue.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param txq\n * Pointer to TX queue structure.\n * @param desc\n * Number of descriptors to configure in queue.\n * @param socket\n * NUMA socket on which memory must be allocated.\n * @param[in] conf\n * Thresholds parameters.\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\ntxq_setup(struct rte_eth_dev *dev, struct txq *txq, uint16_t desc,\n\t unsigned int socket, const struct rte_eth_txconf *conf)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tstruct txq tmpl = {\n\t\t.priv = priv,\n\t\t.socket = socket\n\t};\n\tunion {\n\t\tstruct ibv_exp_query_intf_params params;\n\t\tstruct ibv_exp_qp_init_attr init;\n\t\tstruct ibv_exp_res_domain_init_attr rd;\n\t\tstruct ibv_exp_cq_init_attr cq;\n\t\tstruct ibv_exp_qp_attr mod;\n\t} attr;\n\tenum ibv_exp_query_intf_status status;\n\tint ret = 0;\n\n\t(void)conf; /* Thresholds configuration (ignored). */\n\tif ((desc == 0) || (desc % MLX4_PMD_SGE_WR_N)) {\n\t\tERROR(\"%p: invalid number of TX descriptors (must be a\"\n\t\t \" multiple of %d)\", (void *)dev, MLX4_PMD_SGE_WR_N);\n\t\treturn EINVAL;\n\t}\n\tdesc /= MLX4_PMD_SGE_WR_N;\n\t/* MRs will be registered in mp2mr[] later. */\n\tattr.rd = (struct ibv_exp_res_domain_init_attr){\n\t\t.comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL |\n\t\t\t IBV_EXP_RES_DOMAIN_MSG_MODEL),\n\t\t.thread_model = IBV_EXP_THREAD_SINGLE,\n\t\t.msg_model = IBV_EXP_MSG_HIGH_BW,\n\t};\n\ttmpl.rd = ibv_exp_create_res_domain(priv->ctx, &attr.rd);\n\tif (tmpl.rd == NULL) {\n\t\tret = ENOMEM;\n\t\tERROR(\"%p: RD creation failure: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n\tattr.cq = (struct ibv_exp_cq_init_attr){\n\t\t.comp_mask = IBV_EXP_CQ_INIT_ATTR_RES_DOMAIN,\n\t\t.res_domain = tmpl.rd,\n\t};\n\ttmpl.cq = ibv_exp_create_cq(priv->ctx, desc, NULL, NULL, 0, &attr.cq);\n\tif (tmpl.cq == NULL) {\n\t\tret = ENOMEM;\n\t\tERROR(\"%p: CQ creation failure: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n\tDEBUG(\"priv->device_attr.max_qp_wr is %d\",\n\t priv->device_attr.max_qp_wr);\n\tDEBUG(\"priv->device_attr.max_sge is %d\",\n\t priv->device_attr.max_sge);\n\tattr.init = (struct ibv_exp_qp_init_attr){\n\t\t/* CQ to be associated with the send queue. */\n\t\t.send_cq = tmpl.cq,\n\t\t/* CQ to be associated with the receive queue. */\n\t\t.recv_cq = tmpl.cq,\n\t\t.cap = {\n\t\t\t/* Max number of outstanding WRs. */\n\t\t\t.max_send_wr = ((priv->device_attr.max_qp_wr < desc) ?\n\t\t\t\t\tpriv->device_attr.max_qp_wr :\n\t\t\t\t\tdesc),\n\t\t\t/* Max number of scatter/gather elements in a WR. */\n\t\t\t.max_send_sge = ((priv->device_attr.max_sge <\n\t\t\t\t\t MLX4_PMD_SGE_WR_N) ?\n\t\t\t\t\t priv->device_attr.max_sge :\n\t\t\t\t\t MLX4_PMD_SGE_WR_N),\n#if MLX4_PMD_MAX_INLINE > 0\n\t\t\t.max_inline_data = MLX4_PMD_MAX_INLINE,\n#endif\n\t\t},\n\t\t.qp_type = IBV_QPT_RAW_PACKET,\n\t\t/* Do *NOT* enable this, completions events are managed per\n\t\t * TX burst. */\n\t\t.sq_sig_all = 0,\n\t\t.pd = priv->pd,\n\t\t.res_domain = tmpl.rd,\n\t\t.comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |\n\t\t\t IBV_EXP_QP_INIT_ATTR_RES_DOMAIN),\n\t};\n\ttmpl.qp = ibv_exp_create_qp(priv->ctx, &attr.init);\n\tif (tmpl.qp == NULL) {\n\t\tret = (errno ? errno : EINVAL);\n\t\tERROR(\"%p: QP creation failure: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n#if MLX4_PMD_MAX_INLINE > 0\n\t/* ibv_create_qp() updates this value. */\n\ttmpl.max_inline = attr.init.cap.max_inline_data;\n#endif\n\tattr.mod = (struct ibv_exp_qp_attr){\n\t\t/* Move the QP to this state. */\n\t\t.qp_state = IBV_QPS_INIT,\n\t\t/* Primary port number. */\n\t\t.port_num = priv->port\n\t};\n\tret = ibv_exp_modify_qp(tmpl.qp, &attr.mod,\n\t\t\t\t(IBV_EXP_QP_STATE | IBV_EXP_QP_PORT));\n\tif (ret) {\n\t\tERROR(\"%p: QP state to IBV_QPS_INIT failed: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n\tret = txq_alloc_elts(&tmpl, desc);\n\tif (ret) {\n\t\tERROR(\"%p: TXQ allocation failed: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n\tattr.mod = (struct ibv_exp_qp_attr){\n\t\t.qp_state = IBV_QPS_RTR\n\t};\n\tret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);\n\tif (ret) {\n\t\tERROR(\"%p: QP state to IBV_QPS_RTR failed: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n\tattr.mod.qp_state = IBV_QPS_RTS;\n\tret = ibv_exp_modify_qp(tmpl.qp, &attr.mod, IBV_EXP_QP_STATE);\n\tif (ret) {\n\t\tERROR(\"%p: QP state to IBV_QPS_RTS failed: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n\tattr.params = (struct ibv_exp_query_intf_params){\n\t\t.intf_scope = IBV_EXP_INTF_GLOBAL,\n\t\t.intf = IBV_EXP_INTF_CQ,\n\t\t.obj = tmpl.cq,\n\t};\n\ttmpl.if_cq = ibv_exp_query_intf(priv->ctx, &attr.params, &status);\n\tif (tmpl.if_cq == NULL) {\n\t\tERROR(\"%p: CQ interface family query failed with status %d\",\n\t\t (void *)dev, status);\n\t\tgoto error;\n\t}\n\tattr.params = (struct ibv_exp_query_intf_params){\n\t\t.intf_scope = IBV_EXP_INTF_GLOBAL,\n\t\t.intf = IBV_EXP_INTF_QP_BURST,\n\t\t.obj = tmpl.qp,\n#ifdef HAVE_EXP_QP_BURST_CREATE_DISABLE_ETH_LOOPBACK\n\t\t/* MC loopback must be disabled when not using a VF. */\n\t\t.family_flags =\n\t\t\t(!priv->vf ?\n\t\t\t IBV_EXP_QP_BURST_CREATE_DISABLE_ETH_LOOPBACK :\n\t\t\t 0),\n#endif\n\t};\n\ttmpl.if_qp = ibv_exp_query_intf(priv->ctx, &attr.params, &status);\n\tif (tmpl.if_qp == NULL) {\n\t\tERROR(\"%p: QP interface family query failed with status %d\",\n\t\t (void *)dev, status);\n\t\tgoto error;\n\t}\n\t/* Clean up txq in case we're reinitializing it. */\n\tDEBUG(\"%p: cleaning-up old txq just in case\", (void *)txq);\n\ttxq_cleanup(txq);\n\t*txq = tmpl;\n\tDEBUG(\"%p: txq updated with %p\", (void *)txq, (void *)&tmpl);\n\tassert(ret == 0);\n\treturn 0;\nerror:\n\ttxq_cleanup(&tmpl);\n\tassert(ret > 0);\n\treturn ret;\n}\n\n/**\n * DPDK callback to configure a TX queue.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param idx\n * TX queue index.\n * @param desc\n * Number of descriptors to configure in queue.\n * @param socket\n * NUMA socket on which memory must be allocated.\n * @param[in] conf\n * Thresholds parameters.\n *\n * @return\n * 0 on success, negative errno value on failure.\n */\nstatic int\nmlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n\t\t unsigned int socket, const struct rte_eth_txconf *conf)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tstruct txq *txq = (*priv->txqs)[idx];\n\tint ret;\n\n\tpriv_lock(priv);\n\tDEBUG(\"%p: configuring queue %u for %u descriptors\",\n\t (void *)dev, idx, desc);\n\tif (idx >= priv->txqs_n) {\n\t\tERROR(\"%p: queue index out of range (%u >= %u)\",\n\t\t (void *)dev, idx, priv->txqs_n);\n\t\tpriv_unlock(priv);\n\t\treturn -EOVERFLOW;\n\t}\n\tif (txq != NULL) {\n\t\tDEBUG(\"%p: reusing already allocated queue index %u (%p)\",\n\t\t (void *)dev, idx, (void *)txq);\n\t\tif (priv->started) {\n\t\t\tpriv_unlock(priv);\n\t\t\treturn -EEXIST;\n\t\t}\n\t\t(*priv->txqs)[idx] = NULL;\n\t\ttxq_cleanup(txq);\n\t} else {\n\t\ttxq = rte_calloc_socket(\"TXQ\", 1, sizeof(*txq), 0, socket);\n\t\tif (txq == NULL) {\n\t\t\tERROR(\"%p: unable to allocate queue index %u\",\n\t\t\t (void *)dev, idx);\n\t\t\tpriv_unlock(priv);\n\t\t\treturn -ENOMEM;\n\t\t}\n\t}\n\tret = txq_setup(dev, txq, desc, socket, conf);\n\tif (ret)\n\t\trte_free(txq);\n\telse {\n\t\ttxq->stats.idx = idx;\n\t\tDEBUG(\"%p: adding TX queue %p to list\",\n\t\t (void *)dev, (void *)txq);\n\t\t(*priv->txqs)[idx] = txq;\n\t\t/* Update send callback. */\n\t\tdev->tx_pkt_burst = mlx4_tx_burst;\n\t}\n\tpriv_unlock(priv);\n\treturn -ret;\n}\n\n/**\n * DPDK callback to release a TX queue.\n *\n * @param dpdk_txq\n * Generic TX queue pointer.\n */\nstatic void\nmlx4_tx_queue_release(void *dpdk_txq)\n{\n\tstruct txq *txq = (struct txq *)dpdk_txq;\n\tstruct priv *priv;\n\tunsigned int i;\n\n\tif (txq == NULL)\n\t\treturn;\n\tpriv = txq->priv;\n\tpriv_lock(priv);\n\tfor (i = 0; (i != priv->txqs_n); ++i)\n\t\tif ((*priv->txqs)[i] == txq) {\n\t\t\tDEBUG(\"%p: removing TX queue %p from list\",\n\t\t\t (void *)priv->dev, (void *)txq);\n\t\t\t(*priv->txqs)[i] = NULL;\n\t\t\tbreak;\n\t\t}\n\ttxq_cleanup(txq);\n\trte_free(txq);\n\tpriv_unlock(priv);\n}\n\n/* RX queues handling. */\n\n/**\n * Allocate RX queue elements with scattered packets support.\n *\n * @param rxq\n * Pointer to RX queue structure.\n * @param elts_n\n * Number of elements to allocate.\n * @param[in] pool\n * If not NULL, fetch buffers from this array instead of allocating them\n * with rte_pktmbuf_alloc().\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\nrxq_alloc_elts_sp(struct rxq *rxq, unsigned int elts_n,\n\t\t struct rte_mbuf **pool)\n{\n\tunsigned int i;\n\tstruct rxq_elt_sp (*elts)[elts_n] =\n\t\trte_calloc_socket(\"RXQ elements\", 1, sizeof(*elts), 0,\n\t\t\t\t rxq->socket);\n\tint ret = 0;\n\n\tif (elts == NULL) {\n\t\tERROR(\"%p: can't allocate packets array\", (void *)rxq);\n\t\tret = ENOMEM;\n\t\tgoto error;\n\t}\n\t/* For each WR (packet). */\n\tfor (i = 0; (i != elts_n); ++i) {\n\t\tunsigned int j;\n\t\tstruct rxq_elt_sp *elt = &(*elts)[i];\n\t\tstruct ibv_recv_wr *wr = &elt->wr;\n\t\tstruct ibv_sge (*sges)[(elemof(elt->sges))] = &elt->sges;\n\n\t\t/* These two arrays must have the same size. */\n\t\tassert(elemof(elt->sges) == elemof(elt->bufs));\n\t\t/* Configure WR. */\n\t\twr->wr_id = i;\n\t\twr->next = &(*elts)[(i + 1)].wr;\n\t\twr->sg_list = &(*sges)[0];\n\t\twr->num_sge = elemof(*sges);\n\t\t/* For each SGE (segment). */\n\t\tfor (j = 0; (j != elemof(elt->bufs)); ++j) {\n\t\t\tstruct ibv_sge *sge = &(*sges)[j];\n\t\t\tstruct rte_mbuf *buf;\n\n\t\t\tif (pool != NULL) {\n\t\t\t\tbuf = *(pool++);\n\t\t\t\tassert(buf != NULL);\n\t\t\t\trte_pktmbuf_reset(buf);\n\t\t\t} else\n\t\t\t\tbuf = rte_pktmbuf_alloc(rxq->mp);\n\t\t\tif (buf == NULL) {\n\t\t\t\tassert(pool == NULL);\n\t\t\t\tERROR(\"%p: empty mbuf pool\", (void *)rxq);\n\t\t\t\tret = ENOMEM;\n\t\t\t\tgoto error;\n\t\t\t}\n\t\t\telt->bufs[j] = buf;\n\t\t\t/* Headroom is reserved by rte_pktmbuf_alloc(). */\n\t\t\tassert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);\n\t\t\t/* Buffer is supposed to be empty. */\n\t\t\tassert(rte_pktmbuf_data_len(buf) == 0);\n\t\t\tassert(rte_pktmbuf_pkt_len(buf) == 0);\n\t\t\t/* sge->addr must be able to store a pointer. */\n\t\t\tassert(sizeof(sge->addr) >= sizeof(uintptr_t));\n\t\t\tif (j == 0) {\n\t\t\t\t/* The first SGE keeps its headroom. */\n\t\t\t\tsge->addr = rte_pktmbuf_mtod(buf, uintptr_t);\n\t\t\t\tsge->length = (buf->buf_len -\n\t\t\t\t\t RTE_PKTMBUF_HEADROOM);\n\t\t\t} else {\n\t\t\t\t/* Subsequent SGEs lose theirs. */\n\t\t\t\tassert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);\n\t\t\t\tSET_DATA_OFF(buf, 0);\n\t\t\t\tsge->addr = (uintptr_t)buf->buf_addr;\n\t\t\t\tsge->length = buf->buf_len;\n\t\t\t}\n\t\t\tsge->lkey = rxq->mr->lkey;\n\t\t\t/* Redundant check for tailroom. */\n\t\t\tassert(sge->length == rte_pktmbuf_tailroom(buf));\n\t\t}\n\t}\n\t/* The last WR pointer must be NULL. */\n\t(*elts)[(i - 1)].wr.next = NULL;\n\tDEBUG(\"%p: allocated and configured %u WRs (%zu segments)\",\n\t (void *)rxq, elts_n, (elts_n * elemof((*elts)[0].sges)));\n\trxq->elts_n = elts_n;\n\trxq->elts_head = 0;\n\trxq->elts.sp = elts;\n\tassert(ret == 0);\n\treturn 0;\nerror:\n\tif (elts != NULL) {\n\t\tassert(pool == NULL);\n\t\tfor (i = 0; (i != elemof(*elts)); ++i) {\n\t\t\tunsigned int j;\n\t\t\tstruct rxq_elt_sp *elt = &(*elts)[i];\n\n\t\t\tfor (j = 0; (j != elemof(elt->bufs)); ++j) {\n\t\t\t\tstruct rte_mbuf *buf = elt->bufs[j];\n\n\t\t\t\tif (buf != NULL)\n\t\t\t\t\trte_pktmbuf_free_seg(buf);\n\t\t\t}\n\t\t}\n\t\trte_free(elts);\n\t}\n\tDEBUG(\"%p: failed, freed everything\", (void *)rxq);\n\tassert(ret > 0);\n\treturn ret;\n}\n\n/**\n * Free RX queue elements with scattered packets support.\n *\n * @param rxq\n * Pointer to RX queue structure.\n */\nstatic void\nrxq_free_elts_sp(struct rxq *rxq)\n{\n\tunsigned int i;\n\tunsigned int elts_n = rxq->elts_n;\n\tstruct rxq_elt_sp (*elts)[elts_n] = rxq->elts.sp;\n\n\tDEBUG(\"%p: freeing WRs\", (void *)rxq);\n\trxq->elts_n = 0;\n\trxq->elts.sp = NULL;\n\tif (elts == NULL)\n\t\treturn;\n\tfor (i = 0; (i != elemof(*elts)); ++i) {\n\t\tunsigned int j;\n\t\tstruct rxq_elt_sp *elt = &(*elts)[i];\n\n\t\tfor (j = 0; (j != elemof(elt->bufs)); ++j) {\n\t\t\tstruct rte_mbuf *buf = elt->bufs[j];\n\n\t\t\tif (buf != NULL)\n\t\t\t\trte_pktmbuf_free_seg(buf);\n\t\t}\n\t}\n\trte_free(elts);\n}\n\n/**\n * Allocate RX queue elements.\n *\n * @param rxq\n * Pointer to RX queue structure.\n * @param elts_n\n * Number of elements to allocate.\n * @param[in] pool\n * If not NULL, fetch buffers from this array instead of allocating them\n * with rte_pktmbuf_alloc().\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\nrxq_alloc_elts(struct rxq *rxq, unsigned int elts_n, struct rte_mbuf **pool)\n{\n\tunsigned int i;\n\tstruct rxq_elt (*elts)[elts_n] =\n\t\trte_calloc_socket(\"RXQ elements\", 1, sizeof(*elts), 0,\n\t\t\t\t rxq->socket);\n\tint ret = 0;\n\n\tif (elts == NULL) {\n\t\tERROR(\"%p: can't allocate packets array\", (void *)rxq);\n\t\tret = ENOMEM;\n\t\tgoto error;\n\t}\n\t/* For each WR (packet). */\n\tfor (i = 0; (i != elts_n); ++i) {\n\t\tstruct rxq_elt *elt = &(*elts)[i];\n\t\tstruct ibv_recv_wr *wr = &elt->wr;\n\t\tstruct ibv_sge *sge = &(*elts)[i].sge;\n\t\tstruct rte_mbuf *buf;\n\n\t\tif (pool != NULL) {\n\t\t\tbuf = *(pool++);\n\t\t\tassert(buf != NULL);\n\t\t\trte_pktmbuf_reset(buf);\n\t\t} else\n\t\t\tbuf = rte_pktmbuf_alloc(rxq->mp);\n\t\tif (buf == NULL) {\n\t\t\tassert(pool == NULL);\n\t\t\tERROR(\"%p: empty mbuf pool\", (void *)rxq);\n\t\t\tret = ENOMEM;\n\t\t\tgoto error;\n\t\t}\n\t\t/* Configure WR. Work request ID contains its own index in\n\t\t * the elts array and the offset between SGE buffer header and\n\t\t * its data. */\n\t\tWR_ID(wr->wr_id).id = i;\n\t\tWR_ID(wr->wr_id).offset =\n\t\t\t(((uintptr_t)buf->buf_addr + RTE_PKTMBUF_HEADROOM) -\n\t\t\t (uintptr_t)buf);\n\t\twr->next = &(*elts)[(i + 1)].wr;\n\t\twr->sg_list = sge;\n\t\twr->num_sge = 1;\n\t\t/* Headroom is reserved by rte_pktmbuf_alloc(). */\n\t\tassert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);\n\t\t/* Buffer is supposed to be empty. */\n\t\tassert(rte_pktmbuf_data_len(buf) == 0);\n\t\tassert(rte_pktmbuf_pkt_len(buf) == 0);\n\t\t/* sge->addr must be able to store a pointer. */\n\t\tassert(sizeof(sge->addr) >= sizeof(uintptr_t));\n\t\t/* SGE keeps its headroom. */\n\t\tsge->addr = (uintptr_t)\n\t\t\t((uint8_t *)buf->buf_addr + RTE_PKTMBUF_HEADROOM);\n\t\tsge->length = (buf->buf_len - RTE_PKTMBUF_HEADROOM);\n\t\tsge->lkey = rxq->mr->lkey;\n\t\t/* Redundant check for tailroom. */\n\t\tassert(sge->length == rte_pktmbuf_tailroom(buf));\n\t\t/* Make sure elts index and SGE mbuf pointer can be deduced\n\t\t * from WR ID. */\n\t\tif ((WR_ID(wr->wr_id).id != i) ||\n\t\t ((void *)((uintptr_t)sge->addr -\n\t\t\tWR_ID(wr->wr_id).offset) != buf)) {\n\t\t\tERROR(\"%p: cannot store index and offset in WR ID\",\n\t\t\t (void *)rxq);\n\t\t\tsge->addr = 0;\n\t\t\trte_pktmbuf_free(buf);\n\t\t\tret = EOVERFLOW;\n\t\t\tgoto error;\n\t\t}\n\t}\n\t/* The last WR pointer must be NULL. */\n\t(*elts)[(i - 1)].wr.next = NULL;\n\tDEBUG(\"%p: allocated and configured %u single-segment WRs\",\n\t (void *)rxq, elts_n);\n\trxq->elts_n = elts_n;\n\trxq->elts_head = 0;\n\trxq->elts.no_sp = elts;\n\tassert(ret == 0);\n\treturn 0;\nerror:\n\tif (elts != NULL) {\n\t\tassert(pool == NULL);\n\t\tfor (i = 0; (i != elemof(*elts)); ++i) {\n\t\t\tstruct rxq_elt *elt = &(*elts)[i];\n\t\t\tstruct rte_mbuf *buf;\n\n\t\t\tif (elt->sge.addr == 0)\n\t\t\t\tcontinue;\n\t\t\tassert(WR_ID(elt->wr.wr_id).id == i);\n\t\t\tbuf = (void *)((uintptr_t)elt->sge.addr -\n\t\t\t\tWR_ID(elt->wr.wr_id).offset);\n\t\t\trte_pktmbuf_free_seg(buf);\n\t\t}\n\t\trte_free(elts);\n\t}\n\tDEBUG(\"%p: failed, freed everything\", (void *)rxq);\n\tassert(ret > 0);\n\treturn ret;\n}\n\n/**\n * Free RX queue elements.\n *\n * @param rxq\n * Pointer to RX queue structure.\n */\nstatic void\nrxq_free_elts(struct rxq *rxq)\n{\n\tunsigned int i;\n\tunsigned int elts_n = rxq->elts_n;\n\tstruct rxq_elt (*elts)[elts_n] = rxq->elts.no_sp;\n\n\tDEBUG(\"%p: freeing WRs\", (void *)rxq);\n\trxq->elts_n = 0;\n\trxq->elts.no_sp = NULL;\n\tif (elts == NULL)\n\t\treturn;\n\tfor (i = 0; (i != elemof(*elts)); ++i) {\n\t\tstruct rxq_elt *elt = &(*elts)[i];\n\t\tstruct rte_mbuf *buf;\n\n\t\tif (elt->sge.addr == 0)\n\t\t\tcontinue;\n\t\tassert(WR_ID(elt->wr.wr_id).id == i);\n\t\tbuf = (void *)((uintptr_t)elt->sge.addr -\n\t\t\tWR_ID(elt->wr.wr_id).offset);\n\t\trte_pktmbuf_free_seg(buf);\n\t}\n\trte_free(elts);\n}\n\n/**\n * Delete flow steering rule.\n *\n * @param rxq\n * Pointer to RX queue structure.\n * @param mac_index\n * MAC address index.\n * @param vlan_index\n * VLAN index.\n */\nstatic void\nrxq_del_flow(struct rxq *rxq, unsigned int mac_index, unsigned int vlan_index)\n{\n#ifndef NDEBUG\n\tstruct priv *priv = rxq->priv;\n\tconst uint8_t (*mac)[ETHER_ADDR_LEN] =\n\t\t(const uint8_t (*)[ETHER_ADDR_LEN])\n\t\tpriv->mac[mac_index].addr_bytes;\n#endif\n\tassert(rxq->mac_flow[mac_index][vlan_index] != NULL);\n\tDEBUG(\"%p: removing MAC address %02x:%02x:%02x:%02x:%02x:%02x index %u\"\n\t \" (VLAN ID %\" PRIu16 \")\",\n\t (void *)rxq,\n\t (*mac)[0], (*mac)[1], (*mac)[2], (*mac)[3], (*mac)[4], (*mac)[5],\n\t mac_index, priv->vlan_filter[vlan_index].id);\n\tclaim_zero(ibv_destroy_flow(rxq->mac_flow[mac_index][vlan_index]));\n\trxq->mac_flow[mac_index][vlan_index] = NULL;\n}\n\n/**\n * Unregister a MAC address from a RX queue.\n *\n * @param rxq\n * Pointer to RX queue structure.\n * @param mac_index\n * MAC address index.\n */\nstatic void\nrxq_mac_addr_del(struct rxq *rxq, unsigned int mac_index)\n{\n\tstruct priv *priv = rxq->priv;\n\tunsigned int i;\n\tunsigned int vlans = 0;\n\n\tassert(mac_index < elemof(priv->mac));\n\tif (!BITFIELD_ISSET(rxq->mac_configured, mac_index))\n\t\treturn;\n\tfor (i = 0; (i != elemof(priv->vlan_filter)); ++i) {\n\t\tif (!priv->vlan_filter[i].enabled)\n\t\t\tcontinue;\n\t\trxq_del_flow(rxq, mac_index, i);\n\t\tvlans++;\n\t}\n\tif (!vlans) {\n\t\trxq_del_flow(rxq, mac_index, 0);\n\t}\n\tBITFIELD_RESET(rxq->mac_configured, mac_index);\n}\n\n/**\n * Unregister all MAC addresses from a RX queue.\n *\n * @param rxq\n * Pointer to RX queue structure.\n */\nstatic void\nrxq_mac_addrs_del(struct rxq *rxq)\n{\n\tstruct priv *priv = rxq->priv;\n\tunsigned int i;\n\n\tfor (i = 0; (i != elemof(priv->mac)); ++i)\n\t\trxq_mac_addr_del(rxq, i);\n}\n\nstatic int rxq_promiscuous_enable(struct rxq *);\nstatic void rxq_promiscuous_disable(struct rxq *);\n\n/**\n * Add single flow steering rule.\n *\n * @param rxq\n * Pointer to RX queue structure.\n * @param mac_index\n * MAC address index to register.\n * @param vlan_index\n * VLAN index. Use -1 for a flow without VLAN.\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\nrxq_add_flow(struct rxq *rxq, unsigned int mac_index, unsigned int vlan_index)\n{\n\tstruct ibv_flow *flow;\n\tstruct priv *priv = rxq->priv;\n\tconst uint8_t (*mac)[ETHER_ADDR_LEN] =\n\t\t\t(const uint8_t (*)[ETHER_ADDR_LEN])\n\t\t\tpriv->mac[mac_index].addr_bytes;\n\n\t/* Allocate flow specification on the stack. */\n\tstruct __attribute__((packed)) {\n\t\tstruct ibv_flow_attr attr;\n\t\tstruct ibv_flow_spec_eth spec;\n\t} data;\n\tstruct ibv_flow_attr *attr = &data.attr;\n\tstruct ibv_flow_spec_eth *spec = &data.spec;\n\n\tassert(mac_index < elemof(priv->mac));\n\tassert((vlan_index < elemof(priv->vlan_filter)) || (vlan_index == -1u));\n\t/*\n\t * No padding must be inserted by the compiler between attr and spec.\n\t * This layout is expected by libibverbs.\n\t */\n\tassert(((uint8_t *)attr + sizeof(*attr)) == (uint8_t *)spec);\n\t*attr = (struct ibv_flow_attr){\n\t\t.type = IBV_FLOW_ATTR_NORMAL,\n\t\t.num_of_specs = 1,\n\t\t.port = priv->port,\n\t\t.flags = 0\n\t};\n\t*spec = (struct ibv_flow_spec_eth){\n\t\t.type = IBV_FLOW_SPEC_ETH,\n\t\t.size = sizeof(*spec),\n\t\t.val = {\n\t\t\t.dst_mac = {\n\t\t\t\t(*mac)[0], (*mac)[1], (*mac)[2],\n\t\t\t\t(*mac)[3], (*mac)[4], (*mac)[5]\n\t\t\t},\n\t\t\t.vlan_tag = ((vlan_index != -1u) ?\n\t\t\t\t htons(priv->vlan_filter[vlan_index].id) :\n\t\t\t\t 0),\n\t\t},\n\t\t.mask = {\n\t\t\t.dst_mac = \"\\xff\\xff\\xff\\xff\\xff\\xff\",\n\t\t\t.vlan_tag = ((vlan_index != -1u) ? htons(0xfff) : 0),\n\t\t}\n\t};\n\tDEBUG(\"%p: adding MAC address %02x:%02x:%02x:%02x:%02x:%02x index %u\"\n\t \" (VLAN %s %\" PRIu16 \")\",\n\t (void *)rxq,\n\t (*mac)[0], (*mac)[1], (*mac)[2], (*mac)[3], (*mac)[4], (*mac)[5],\n\t mac_index,\n\t ((vlan_index != -1u) ? \"ID\" : \"index\"),\n\t ((vlan_index != -1u) ? priv->vlan_filter[vlan_index].id : -1u));\n\t/* Create related flow. */\n\terrno = 0;\n\tflow = ibv_create_flow(rxq->qp, attr);\n\tif (flow == NULL) {\n\t\t/* It's not clear whether errno is always set in this case. */\n\t\tERROR(\"%p: flow configuration failed, errno=%d: %s\",\n\t\t (void *)rxq, errno,\n\t\t (errno ? strerror(errno) : \"Unknown error\"));\n\t\tif (errno)\n\t\t\treturn errno;\n\t\treturn EINVAL;\n\t}\n\tif (vlan_index == -1u)\n\t\tvlan_index = 0;\n\tassert(rxq->mac_flow[mac_index][vlan_index] == NULL);\n\trxq->mac_flow[mac_index][vlan_index] = flow;\n\treturn 0;\n}\n\n/**\n * Register a MAC address in a RX queue.\n *\n * @param rxq\n * Pointer to RX queue structure.\n * @param mac_index\n * MAC address index to register.\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\nrxq_mac_addr_add(struct rxq *rxq, unsigned int mac_index)\n{\n\tstruct priv *priv = rxq->priv;\n\tunsigned int i;\n\tunsigned int vlans = 0;\n\tint ret;\n\n\tassert(mac_index < elemof(priv->mac));\n\tif (BITFIELD_ISSET(rxq->mac_configured, mac_index))\n\t\trxq_mac_addr_del(rxq, mac_index);\n\t/* Fill VLAN specifications. */\n\tfor (i = 0; (i != elemof(priv->vlan_filter)); ++i) {\n\t\tif (!priv->vlan_filter[i].enabled)\n\t\t\tcontinue;\n\t\t/* Create related flow. */\n\t\tret = rxq_add_flow(rxq, mac_index, i);\n\t\tif (!ret) {\n\t\t\tvlans++;\n\t\t\tcontinue;\n\t\t}\n\t\t/* Failure, rollback. */\n\t\twhile (i != 0)\n\t\t\tif (priv->vlan_filter[--i].enabled)\n\t\t\t\trxq_del_flow(rxq, mac_index, i);\n\t\tassert(ret > 0);\n\t\treturn ret;\n\t}\n\t/* In case there is no VLAN filter. */\n\tif (!vlans) {\n\t\tret = rxq_add_flow(rxq, mac_index, -1);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\tBITFIELD_SET(rxq->mac_configured, mac_index);\n\treturn 0;\n}\n\n/**\n * Register all MAC addresses in a RX queue.\n *\n * @param rxq\n * Pointer to RX queue structure.\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\nrxq_mac_addrs_add(struct rxq *rxq)\n{\n\tstruct priv *priv = rxq->priv;\n\tunsigned int i;\n\tint ret;\n\n\tfor (i = 0; (i != elemof(priv->mac)); ++i) {\n\t\tif (!BITFIELD_ISSET(priv->mac_configured, i))\n\t\t\tcontinue;\n\t\tret = rxq_mac_addr_add(rxq, i);\n\t\tif (!ret)\n\t\t\tcontinue;\n\t\t/* Failure, rollback. */\n\t\twhile (i != 0)\n\t\t\trxq_mac_addr_del(rxq, --i);\n\t\tassert(ret > 0);\n\t\treturn ret;\n\t}\n\treturn 0;\n}\n\n/**\n * Unregister a MAC address.\n *\n * In RSS mode, the MAC address is unregistered from the parent queue,\n * otherwise it is unregistered from each queue directly.\n *\n * @param priv\n * Pointer to private structure.\n * @param mac_index\n * MAC address index.\n */\nstatic void\npriv_mac_addr_del(struct priv *priv, unsigned int mac_index)\n{\n\tunsigned int i;\n\n\tassert(mac_index < elemof(priv->mac));\n\tif (!BITFIELD_ISSET(priv->mac_configured, mac_index))\n\t\treturn;\n\tif (priv->rss) {\n\t\trxq_mac_addr_del(&priv->rxq_parent, mac_index);\n\t\tgoto end;\n\t}\n\tfor (i = 0; (i != priv->dev->data->nb_rx_queues); ++i)\n\t\trxq_mac_addr_del((*priv->rxqs)[i], mac_index);\nend:\n\tBITFIELD_RESET(priv->mac_configured, mac_index);\n}\n\n/**\n * Register a MAC address.\n *\n * In RSS mode, the MAC address is registered in the parent queue,\n * otherwise it is registered in each queue directly.\n *\n * @param priv\n * Pointer to private structure.\n * @param mac_index\n * MAC address index to use.\n * @param mac\n * MAC address to register.\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\npriv_mac_addr_add(struct priv *priv, unsigned int mac_index,\n\t\t const uint8_t (*mac)[ETHER_ADDR_LEN])\n{\n\tunsigned int i;\n\tint ret;\n\n\tassert(mac_index < elemof(priv->mac));\n\t/* First, make sure this address isn't already configured. */\n\tfor (i = 0; (i != elemof(priv->mac)); ++i) {\n\t\t/* Skip this index, it's going to be reconfigured. */\n\t\tif (i == mac_index)\n\t\t\tcontinue;\n\t\tif (!BITFIELD_ISSET(priv->mac_configured, i))\n\t\t\tcontinue;\n\t\tif (memcmp(priv->mac[i].addr_bytes, *mac, sizeof(*mac)))\n\t\t\tcontinue;\n\t\t/* Address already configured elsewhere, return with error. */\n\t\treturn EADDRINUSE;\n\t}\n\tif (BITFIELD_ISSET(priv->mac_configured, mac_index))\n\t\tpriv_mac_addr_del(priv, mac_index);\n\tpriv->mac[mac_index] = (struct ether_addr){\n\t\t{\n\t\t\t(*mac)[0], (*mac)[1], (*mac)[2],\n\t\t\t(*mac)[3], (*mac)[4], (*mac)[5]\n\t\t}\n\t};\n\t/* If device isn't started, this is all we need to do. */\n\tif (!priv->started) {\n#ifndef NDEBUG\n\t\t/* Verify that all queues have this index disabled. */\n\t\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n\t\t\tif ((*priv->rxqs)[i] == NULL)\n\t\t\t\tcontinue;\n\t\t\tassert(!BITFIELD_ISSET\n\t\t\t ((*priv->rxqs)[i]->mac_configured, mac_index));\n\t\t}\n#endif\n\t\tgoto end;\n\t}\n\tif (priv->rss) {\n\t\tret = rxq_mac_addr_add(&priv->rxq_parent, mac_index);\n\t\tif (ret)\n\t\t\treturn ret;\n\t\tgoto end;\n\t}\n\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n\t\tif ((*priv->rxqs)[i] == NULL)\n\t\t\tcontinue;\n\t\tret = rxq_mac_addr_add((*priv->rxqs)[i], mac_index);\n\t\tif (!ret)\n\t\t\tcontinue;\n\t\t/* Failure, rollback. */\n\t\twhile (i != 0)\n\t\t\tif ((*priv->rxqs)[(--i)] != NULL)\n\t\t\t\trxq_mac_addr_del((*priv->rxqs)[i], mac_index);\n\t\treturn ret;\n\t}\nend:\n\tBITFIELD_SET(priv->mac_configured, mac_index);\n\treturn 0;\n}\n\n/**\n * Enable allmulti mode in a RX queue.\n *\n * @param rxq\n * Pointer to RX queue structure.\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\nrxq_allmulticast_enable(struct rxq *rxq)\n{\n\tstruct ibv_flow *flow;\n\tstruct ibv_flow_attr attr = {\n\t\t.type = IBV_FLOW_ATTR_MC_DEFAULT,\n\t\t.num_of_specs = 0,\n\t\t.port = rxq->priv->port,\n\t\t.flags = 0\n\t};\n\n\tDEBUG(\"%p: enabling allmulticast mode\", (void *)rxq);\n\tif (rxq->allmulti_flow != NULL)\n\t\treturn EBUSY;\n\terrno = 0;\n\tflow = ibv_create_flow(rxq->qp, &attr);\n\tif (flow == NULL) {\n\t\t/* It's not clear whether errno is always set in this case. */\n\t\tERROR(\"%p: flow configuration failed, errno=%d: %s\",\n\t\t (void *)rxq, errno,\n\t\t (errno ? strerror(errno) : \"Unknown error\"));\n\t\tif (errno)\n\t\t\treturn errno;\n\t\treturn EINVAL;\n\t}\n\trxq->allmulti_flow = flow;\n\tDEBUG(\"%p: allmulticast mode enabled\", (void *)rxq);\n\treturn 0;\n}\n\n/**\n * Disable allmulti mode in a RX queue.\n *\n * @param rxq\n * Pointer to RX queue structure.\n */\nstatic void\nrxq_allmulticast_disable(struct rxq *rxq)\n{\n\tDEBUG(\"%p: disabling allmulticast mode\", (void *)rxq);\n\tif (rxq->allmulti_flow == NULL)\n\t\treturn;\n\tclaim_zero(ibv_destroy_flow(rxq->allmulti_flow));\n\trxq->allmulti_flow = NULL;\n\tDEBUG(\"%p: allmulticast mode disabled\", (void *)rxq);\n}\n\n/**\n * Enable promiscuous mode in a RX queue.\n *\n * @param rxq\n * Pointer to RX queue structure.\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\nrxq_promiscuous_enable(struct rxq *rxq)\n{\n\tstruct ibv_flow *flow;\n\tstruct ibv_flow_attr attr = {\n\t\t.type = IBV_FLOW_ATTR_ALL_DEFAULT,\n\t\t.num_of_specs = 0,\n\t\t.port = rxq->priv->port,\n\t\t.flags = 0\n\t};\n\n\tif (rxq->priv->vf)\n\t\treturn 0;\n\tDEBUG(\"%p: enabling promiscuous mode\", (void *)rxq);\n\tif (rxq->promisc_flow != NULL)\n\t\treturn EBUSY;\n\terrno = 0;\n\tflow = ibv_create_flow(rxq->qp, &attr);\n\tif (flow == NULL) {\n\t\t/* It's not clear whether errno is always set in this case. */\n\t\tERROR(\"%p: flow configuration failed, errno=%d: %s\",\n\t\t (void *)rxq, errno,\n\t\t (errno ? strerror(errno) : \"Unknown error\"));\n\t\tif (errno)\n\t\t\treturn errno;\n\t\treturn EINVAL;\n\t}\n\trxq->promisc_flow = flow;\n\tDEBUG(\"%p: promiscuous mode enabled\", (void *)rxq);\n\treturn 0;\n}\n\n/**\n * Disable promiscuous mode in a RX queue.\n *\n * @param rxq\n * Pointer to RX queue structure.\n */\nstatic void\nrxq_promiscuous_disable(struct rxq *rxq)\n{\n\tif (rxq->priv->vf)\n\t\treturn;\n\tDEBUG(\"%p: disabling promiscuous mode\", (void *)rxq);\n\tif (rxq->promisc_flow == NULL)\n\t\treturn;\n\tclaim_zero(ibv_destroy_flow(rxq->promisc_flow));\n\trxq->promisc_flow = NULL;\n\tDEBUG(\"%p: promiscuous mode disabled\", (void *)rxq);\n}\n\n/**\n * Clean up a RX queue.\n *\n * Destroy objects, free allocated memory and reset the structure for reuse.\n *\n * @param rxq\n * Pointer to RX queue structure.\n */\nstatic void\nrxq_cleanup(struct rxq *rxq)\n{\n\tstruct ibv_exp_release_intf_params params;\n\n\tDEBUG(\"cleaning up %p\", (void *)rxq);\n\tif (rxq->sp)\n\t\trxq_free_elts_sp(rxq);\n\telse\n\t\trxq_free_elts(rxq);\n\tif (rxq->if_qp != NULL) {\n\t\tassert(rxq->priv != NULL);\n\t\tassert(rxq->priv->ctx != NULL);\n\t\tassert(rxq->qp != NULL);\n\t\tparams = (struct ibv_exp_release_intf_params){\n\t\t\t.comp_mask = 0,\n\t\t};\n\t\tclaim_zero(ibv_exp_release_intf(rxq->priv->ctx,\n\t\t\t\t\t\trxq->if_qp,\n\t\t\t\t\t\t¶ms));\n\t}\n\tif (rxq->if_cq != NULL) {\n\t\tassert(rxq->priv != NULL);\n\t\tassert(rxq->priv->ctx != NULL);\n\t\tassert(rxq->cq != NULL);\n\t\tparams = (struct ibv_exp_release_intf_params){\n\t\t\t.comp_mask = 0,\n\t\t};\n\t\tclaim_zero(ibv_exp_release_intf(rxq->priv->ctx,\n\t\t\t\t\t\trxq->if_cq,\n\t\t\t\t\t\t¶ms));\n\t}\n\tif (rxq->qp != NULL) {\n\t\trxq_promiscuous_disable(rxq);\n\t\trxq_allmulticast_disable(rxq);\n\t\trxq_mac_addrs_del(rxq);\n\t\tclaim_zero(ibv_destroy_qp(rxq->qp));\n\t}\n\tif (rxq->cq != NULL)\n\t\tclaim_zero(ibv_destroy_cq(rxq->cq));\n\tif (rxq->rd != NULL) {\n\t\tstruct ibv_exp_destroy_res_domain_attr attr = {\n\t\t\t.comp_mask = 0,\n\t\t};\n\n\t\tassert(rxq->priv != NULL);\n\t\tassert(rxq->priv->ctx != NULL);\n\t\tclaim_zero(ibv_exp_destroy_res_domain(rxq->priv->ctx,\n\t\t\t\t\t\t rxq->rd,\n\t\t\t\t\t\t &attr));\n\t}\n\tif (rxq->mr != NULL)\n\t\tclaim_zero(ibv_dereg_mr(rxq->mr));\n\tmemset(rxq, 0, sizeof(*rxq));\n}\n\n#ifdef RTE_NEXT_ABI\n/**\n * Translate RX completion flags to packet type.\n *\n * @param flags\n * RX completion flags returned by poll_length_flags().\n *\n * @return\n * Packet type for struct rte_mbuf.\n */\nstatic inline uint32_t\nrxq_cq_to_pkt_type(uint32_t flags)\n{\n\tuint32_t pkt_type;\n\n\tif (flags & IBV_EXP_CQ_RX_TUNNEL_PACKET)\n\t\tpkt_type =\n\t\t\tTRANSPOSE(flags,\n\t\t\t IBV_EXP_CQ_RX_OUTER_IPV4_PACKET, RTE_PTYPE_L3_IPV4) |\n\t\t\tTRANSPOSE(flags,\n\t\t\t IBV_EXP_CQ_RX_OUTER_IPV6_PACKET, RTE_PTYPE_L3_IPV6) |\n\t\t\tTRANSPOSE(flags,\n\t\t\t IBV_EXP_CQ_RX_IPV4_PACKET, RTE_PTYPE_INNER_L3_IPV4) |\n\t\t\tTRANSPOSE(flags,\n\t\t\t IBV_EXP_CQ_RX_IPV6_PACKET, RTE_PTYPE_INNER_L3_IPV6);\n\telse\n\t\tpkt_type =\n\t\t\tTRANSPOSE(flags,\n\t\t\t IBV_EXP_CQ_RX_IPV4_PACKET, RTE_PTYPE_L3_IPV4) |\n\t\t\tTRANSPOSE(flags,\n\t\t\t IBV_EXP_CQ_RX_IPV6_PACKET, RTE_PTYPE_L3_IPV6);\n\treturn pkt_type;\n}\n#endif /* RTE_NEXT_ABI */\n\n/**\n * Translate RX completion flags to offload flags.\n *\n * @param[in] rxq\n * Pointer to RX queue structure.\n * @param flags\n * RX completion flags returned by poll_length_flags().\n *\n * @return\n * Offload flags (ol_flags) for struct rte_mbuf.\n */\nstatic inline uint32_t\nrxq_cq_to_ol_flags(const struct rxq *rxq, uint32_t flags)\n{\n\tuint32_t ol_flags = 0;\n\n#ifndef RTE_NEXT_ABI\n\tol_flags =\n\t\tTRANSPOSE(flags, IBV_EXP_CQ_RX_IPV4_PACKET, PKT_RX_IPV4_HDR) |\n\t\tTRANSPOSE(flags, IBV_EXP_CQ_RX_IPV6_PACKET, PKT_RX_IPV6_HDR);\n#endif\n\tif (rxq->csum)\n\t\tol_flags |=\n\t\t\tTRANSPOSE(~flags,\n\t\t\t\t IBV_EXP_CQ_RX_IP_CSUM_OK,\n\t\t\t\t PKT_RX_IP_CKSUM_BAD) |\n\t\t\tTRANSPOSE(~flags,\n\t\t\t\t IBV_EXP_CQ_RX_TCP_UDP_CSUM_OK,\n\t\t\t\t PKT_RX_L4_CKSUM_BAD);\n\t/*\n\t * PKT_RX_IP_CKSUM_BAD and PKT_RX_L4_CKSUM_BAD are used in place\n\t * of PKT_RX_EIP_CKSUM_BAD because the latter is not functional\n\t * (its value is 0).\n\t */\n\tif ((flags & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))\n\t\tol_flags |=\n#ifndef RTE_NEXT_ABI\n\t\t\tTRANSPOSE(flags,\n\t\t\t\t IBV_EXP_CQ_RX_OUTER_IPV4_PACKET,\n\t\t\t\t PKT_RX_TUNNEL_IPV4_HDR) |\n\t\t\tTRANSPOSE(flags,\n\t\t\t\t IBV_EXP_CQ_RX_OUTER_IPV6_PACKET,\n\t\t\t\t PKT_RX_TUNNEL_IPV6_HDR) |\n#endif\n\t\t\tTRANSPOSE(~flags,\n\t\t\t\t IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK,\n\t\t\t\t PKT_RX_IP_CKSUM_BAD) |\n\t\t\tTRANSPOSE(~flags,\n\t\t\t\t IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK,\n\t\t\t\t PKT_RX_L4_CKSUM_BAD);\n\treturn ol_flags;\n}\n\nstatic uint16_t\nmlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);\n\n/**\n * DPDK callback for RX with scattered packets support.\n *\n * @param dpdk_rxq\n * Generic pointer to RX queue structure.\n * @param[out] pkts\n * Array to store received packets.\n * @param pkts_n\n * Maximum number of packets in array.\n *\n * @return\n * Number of packets successfully received (<= pkts_n).\n */\nstatic uint16_t\nmlx4_rx_burst_sp(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n{\n\tstruct rxq *rxq = (struct rxq *)dpdk_rxq;\n\tstruct rxq_elt_sp (*elts)[rxq->elts_n] = rxq->elts.sp;\n\tconst unsigned int elts_n = rxq->elts_n;\n\tunsigned int elts_head = rxq->elts_head;\n\tstruct ibv_recv_wr head;\n\tstruct ibv_recv_wr **next = &head.next;\n\tstruct ibv_recv_wr *bad_wr;\n\tunsigned int i;\n\tunsigned int pkts_ret = 0;\n\tint ret;\n\n\tif (unlikely(!rxq->sp))\n\t\treturn mlx4_rx_burst(dpdk_rxq, pkts, pkts_n);\n\tif (unlikely(elts == NULL)) /* See RTE_DEV_CMD_SET_MTU. */\n\t\treturn 0;\n\tfor (i = 0; (i != pkts_n); ++i) {\n\t\tstruct rxq_elt_sp *elt = &(*elts)[elts_head];\n\t\tstruct ibv_recv_wr *wr = &elt->wr;\n\t\tuint64_t wr_id = wr->wr_id;\n\t\tunsigned int len;\n\t\tunsigned int pkt_buf_len;\n\t\tstruct rte_mbuf *pkt_buf = NULL; /* Buffer returned in pkts. */\n\t\tstruct rte_mbuf **pkt_buf_next = &pkt_buf;\n\t\tunsigned int seg_headroom = RTE_PKTMBUF_HEADROOM;\n\t\tunsigned int j = 0;\n\t\tuint32_t flags;\n\n\t\t/* Sanity checks. */\n#ifdef NDEBUG\n\t\t(void)wr_id;\n#endif\n\t\tassert(wr_id < rxq->elts_n);\n\t\tassert(wr->sg_list == elt->sges);\n\t\tassert(wr->num_sge == elemof(elt->sges));\n\t\tassert(elts_head < rxq->elts_n);\n\t\tassert(rxq->elts_head < rxq->elts_n);\n\t\tret = rxq->if_cq->poll_length_flags(rxq->cq, NULL, NULL,\n\t\t\t\t\t\t &flags);\n\t\tif (unlikely(ret < 0)) {\n\t\t\tstruct ibv_wc wc;\n\t\t\tint wcs_n;\n\n\t\t\tDEBUG(\"rxq=%p, poll_length() failed (ret=%d)\",\n\t\t\t (void *)rxq, ret);\n\t\t\t/* ibv_poll_cq() must be used in case of failure. */\n\t\t\twcs_n = ibv_poll_cq(rxq->cq, 1, &wc);\n\t\t\tif (unlikely(wcs_n == 0))\n\t\t\t\tbreak;\n\t\t\tif (unlikely(wcs_n < 0)) {\n\t\t\t\tDEBUG(\"rxq=%p, ibv_poll_cq() failed (wcs_n=%d)\",\n\t\t\t\t (void *)rxq, wcs_n);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tassert(wcs_n == 1);\n\t\t\tif (unlikely(wc.status != IBV_WC_SUCCESS)) {\n\t\t\t\t/* Whatever, just repost the offending WR. */\n\t\t\t\tDEBUG(\"rxq=%p, wr_id=%\" PRIu64 \": bad work\"\n\t\t\t\t \" completion status (%d): %s\",\n\t\t\t\t (void *)rxq, wc.wr_id, wc.status,\n\t\t\t\t ibv_wc_status_str(wc.status));\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t\t\t\t/* Increment dropped packets counter. */\n\t\t\t\t++rxq->stats.idropped;\n#endif\n\t\t\t\t/* Link completed WRs together for repost. */\n\t\t\t\t*next = wr;\n\t\t\t\tnext = &wr->next;\n\t\t\t\tgoto repost;\n\t\t\t}\n\t\t\tret = wc.byte_len;\n\t\t}\n\t\tif (ret == 0)\n\t\t\tbreak;\n\t\tlen = ret;\n\t\tpkt_buf_len = len;\n\t\t/* Link completed WRs together for repost. */\n\t\t*next = wr;\n\t\tnext = &wr->next;\n\t\t/*\n\t\t * Replace spent segments with new ones, concatenate and\n\t\t * return them as pkt_buf.\n\t\t */\n\t\twhile (1) {\n\t\t\tstruct ibv_sge *sge = &elt->sges[j];\n\t\t\tstruct rte_mbuf *seg = elt->bufs[j];\n\t\t\tstruct rte_mbuf *rep;\n\t\t\tunsigned int seg_tailroom;\n\n\t\t\t/*\n\t\t\t * Fetch initial bytes of packet descriptor into a\n\t\t\t * cacheline while allocating rep.\n\t\t\t */\n\t\t\trte_prefetch0(seg);\n\t\t\trep = __rte_mbuf_raw_alloc(rxq->mp);\n\t\t\tif (unlikely(rep == NULL)) {\n\t\t\t\t/*\n\t\t\t\t * Unable to allocate a replacement mbuf,\n\t\t\t\t * repost WR.\n\t\t\t\t */\n\t\t\t\tDEBUG(\"rxq=%p, wr_id=%\" PRIu64 \":\"\n\t\t\t\t \" can't allocate a new mbuf\",\n\t\t\t\t (void *)rxq, wr_id);\n\t\t\t\tif (pkt_buf != NULL) {\n\t\t\t\t\t*pkt_buf_next = NULL;\n\t\t\t\t\trte_pktmbuf_free(pkt_buf);\n\t\t\t\t}\n\t\t\t\t/* Increase out of memory counters. */\n\t\t\t\t++rxq->stats.rx_nombuf;\n\t\t\t\t++rxq->priv->dev->data->rx_mbuf_alloc_failed;\n\t\t\t\tgoto repost;\n\t\t\t}\n#ifndef NDEBUG\n\t\t\t/* Poison user-modifiable fields in rep. */\n\t\t\tNEXT(rep) = (void *)((uintptr_t)-1);\n\t\t\tSET_DATA_OFF(rep, 0xdead);\n\t\t\tDATA_LEN(rep) = 0xd00d;\n\t\t\tPKT_LEN(rep) = 0xdeadd00d;\n\t\t\tNB_SEGS(rep) = 0x2a;\n\t\t\tPORT(rep) = 0x2a;\n\t\t\trep->ol_flags = -1;\n#endif\n\t\t\tassert(rep->buf_len == seg->buf_len);\n\t\t\tassert(rep->buf_len == rxq->mb_len);\n\t\t\t/* Reconfigure sge to use rep instead of seg. */\n\t\t\tassert(sge->lkey == rxq->mr->lkey);\n\t\t\tsge->addr = ((uintptr_t)rep->buf_addr + seg_headroom);\n\t\t\telt->bufs[j] = rep;\n\t\t\t++j;\n\t\t\t/* Update pkt_buf if it's the first segment, or link\n\t\t\t * seg to the previous one and update pkt_buf_next. */\n\t\t\t*pkt_buf_next = seg;\n\t\t\tpkt_buf_next = &NEXT(seg);\n\t\t\t/* Update seg information. */\n\t\t\tseg_tailroom = (seg->buf_len - seg_headroom);\n\t\t\tassert(sge->length == seg_tailroom);\n\t\t\tSET_DATA_OFF(seg, seg_headroom);\n\t\t\tif (likely(len <= seg_tailroom)) {\n\t\t\t\t/* Last segment. */\n\t\t\t\tDATA_LEN(seg) = len;\n\t\t\t\tPKT_LEN(seg) = len;\n\t\t\t\t/* Sanity check. */\n\t\t\t\tassert(rte_pktmbuf_headroom(seg) ==\n\t\t\t\t seg_headroom);\n\t\t\t\tassert(rte_pktmbuf_tailroom(seg) ==\n\t\t\t\t (seg_tailroom - len));\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tDATA_LEN(seg) = seg_tailroom;\n\t\t\tPKT_LEN(seg) = seg_tailroom;\n\t\t\t/* Sanity check. */\n\t\t\tassert(rte_pktmbuf_headroom(seg) == seg_headroom);\n\t\t\tassert(rte_pktmbuf_tailroom(seg) == 0);\n\t\t\t/* Fix len and clear headroom for next segments. */\n\t\t\tlen -= seg_tailroom;\n\t\t\tseg_headroom = 0;\n\t\t}\n\t\t/* Update head and tail segments. */\n\t\t*pkt_buf_next = NULL;\n\t\tassert(pkt_buf != NULL);\n\t\tassert(j != 0);\n\t\tNB_SEGS(pkt_buf) = j;\n\t\tPORT(pkt_buf) = rxq->port_id;\n\t\tPKT_LEN(pkt_buf) = pkt_buf_len;\n#ifdef RTE_NEXT_ABI\n\t\tpkt_buf->packet_type = rxq_cq_to_pkt_type(flags);\n#endif\n\t\tpkt_buf->ol_flags = rxq_cq_to_ol_flags(rxq, flags);\n\n\t\t/* Return packet. */\n\t\t*(pkts++) = pkt_buf;\n\t\t++pkts_ret;\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t\t/* Increase bytes counter. */\n\t\trxq->stats.ibytes += pkt_buf_len;\n#endif\nrepost:\n\t\tif (++elts_head >= elts_n)\n\t\t\telts_head = 0;\n\t\tcontinue;\n\t}\n\tif (unlikely(i == 0))\n\t\treturn 0;\n\t*next = NULL;\n\t/* Repost WRs. */\n#ifdef DEBUG_RECV\n\tDEBUG(\"%p: reposting %d WRs\", (void *)rxq, i);\n#endif\n\tret = ibv_post_recv(rxq->qp, head.next, &bad_wr);\n\tif (unlikely(ret)) {\n\t\t/* Inability to repost WRs is fatal. */\n\t\tDEBUG(\"%p: ibv_post_recv(): failed for WR %p: %s\",\n\t\t (void *)rxq->priv,\n\t\t (void *)bad_wr,\n\t\t strerror(ret));\n\t\tabort();\n\t}\n\trxq->elts_head = elts_head;\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t/* Increase packets counter. */\n\trxq->stats.ipackets += pkts_ret;\n#endif\n\treturn pkts_ret;\n}\n\n/**\n * DPDK callback for RX.\n *\n * The following function is the same as mlx4_rx_burst_sp(), except it doesn't\n * manage scattered packets. Improves performance when MRU is lower than the\n * size of the first segment.\n *\n * @param dpdk_rxq\n * Generic pointer to RX queue structure.\n * @param[out] pkts\n * Array to store received packets.\n * @param pkts_n\n * Maximum number of packets in array.\n *\n * @return\n * Number of packets successfully received (<= pkts_n).\n */\nstatic uint16_t\nmlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n{\n\tstruct rxq *rxq = (struct rxq *)dpdk_rxq;\n\tstruct rxq_elt (*elts)[rxq->elts_n] = rxq->elts.no_sp;\n\tconst unsigned int elts_n = rxq->elts_n;\n\tunsigned int elts_head = rxq->elts_head;\n\tstruct ibv_sge sges[pkts_n];\n\tunsigned int i;\n\tunsigned int pkts_ret = 0;\n\tint ret;\n\n\tif (unlikely(rxq->sp))\n\t\treturn mlx4_rx_burst_sp(dpdk_rxq, pkts, pkts_n);\n\tfor (i = 0; (i != pkts_n); ++i) {\n\t\tstruct rxq_elt *elt = &(*elts)[elts_head];\n\t\tstruct ibv_recv_wr *wr = &elt->wr;\n\t\tuint64_t wr_id = wr->wr_id;\n\t\tunsigned int len;\n\t\tstruct rte_mbuf *seg = (void *)((uintptr_t)elt->sge.addr -\n\t\t\tWR_ID(wr_id).offset);\n\t\tstruct rte_mbuf *rep;\n\t\tuint32_t flags;\n\n\t\t/* Sanity checks. */\n\t\tassert(WR_ID(wr_id).id < rxq->elts_n);\n\t\tassert(wr->sg_list == &elt->sge);\n\t\tassert(wr->num_sge == 1);\n\t\tassert(elts_head < rxq->elts_n);\n\t\tassert(rxq->elts_head < rxq->elts_n);\n\t\tret = rxq->if_cq->poll_length_flags(rxq->cq, NULL, NULL,\n\t\t\t\t\t\t &flags);\n\t\tif (unlikely(ret < 0)) {\n\t\t\tstruct ibv_wc wc;\n\t\t\tint wcs_n;\n\n\t\t\tDEBUG(\"rxq=%p, poll_length() failed (ret=%d)\",\n\t\t\t (void *)rxq, ret);\n\t\t\t/* ibv_poll_cq() must be used in case of failure. */\n\t\t\twcs_n = ibv_poll_cq(rxq->cq, 1, &wc);\n\t\t\tif (unlikely(wcs_n == 0))\n\t\t\t\tbreak;\n\t\t\tif (unlikely(wcs_n < 0)) {\n\t\t\t\tDEBUG(\"rxq=%p, ibv_poll_cq() failed (wcs_n=%d)\",\n\t\t\t\t (void *)rxq, wcs_n);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tassert(wcs_n == 1);\n\t\t\tif (unlikely(wc.status != IBV_WC_SUCCESS)) {\n\t\t\t\t/* Whatever, just repost the offending WR. */\n\t\t\t\tDEBUG(\"rxq=%p, wr_id=%\" PRIu64 \": bad work\"\n\t\t\t\t \" completion status (%d): %s\",\n\t\t\t\t (void *)rxq, wc.wr_id, wc.status,\n\t\t\t\t ibv_wc_status_str(wc.status));\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t\t\t\t/* Increment dropped packets counter. */\n\t\t\t\t++rxq->stats.idropped;\n#endif\n\t\t\t\t/* Add SGE to array for repost. */\n\t\t\t\tsges[i] = elt->sge;\n\t\t\t\tgoto repost;\n\t\t\t}\n\t\t\tret = wc.byte_len;\n\t\t}\n\t\tif (ret == 0)\n\t\t\tbreak;\n\t\tlen = ret;\n\t\t/*\n\t\t * Fetch initial bytes of packet descriptor into a\n\t\t * cacheline while allocating rep.\n\t\t */\n\t\trte_prefetch0(seg);\n\t\trep = __rte_mbuf_raw_alloc(rxq->mp);\n\t\tif (unlikely(rep == NULL)) {\n\t\t\t/*\n\t\t\t * Unable to allocate a replacement mbuf,\n\t\t\t * repost WR.\n\t\t\t */\n\t\t\tDEBUG(\"rxq=%p, wr_id=%\" PRIu32 \":\"\n\t\t\t \" can't allocate a new mbuf\",\n\t\t\t (void *)rxq, WR_ID(wr_id).id);\n\t\t\t/* Increase out of memory counters. */\n\t\t\t++rxq->stats.rx_nombuf;\n\t\t\t++rxq->priv->dev->data->rx_mbuf_alloc_failed;\n\t\t\tgoto repost;\n\t\t}\n\n\t\t/* Reconfigure sge to use rep instead of seg. */\n\t\telt->sge.addr = (uintptr_t)rep->buf_addr + RTE_PKTMBUF_HEADROOM;\n\t\tassert(elt->sge.lkey == rxq->mr->lkey);\n\t\tWR_ID(wr->wr_id).offset =\n\t\t\t(((uintptr_t)rep->buf_addr + RTE_PKTMBUF_HEADROOM) -\n\t\t\t (uintptr_t)rep);\n\t\tassert(WR_ID(wr->wr_id).id == WR_ID(wr_id).id);\n\n\t\t/* Add SGE to array for repost. */\n\t\tsges[i] = elt->sge;\n\n\t\t/* Update seg information. */\n\t\tSET_DATA_OFF(seg, RTE_PKTMBUF_HEADROOM);\n\t\tNB_SEGS(seg) = 1;\n\t\tPORT(seg) = rxq->port_id;\n\t\tNEXT(seg) = NULL;\n\t\tPKT_LEN(seg) = len;\n\t\tDATA_LEN(seg) = len;\n#ifdef RTE_NEXT_ABI\n\t\tseg->packet_type = rxq_cq_to_pkt_type(flags);\n#endif\n\t\tseg->ol_flags = rxq_cq_to_ol_flags(rxq, flags);\n\n\t\t/* Return packet. */\n\t\t*(pkts++) = seg;\n\t\t++pkts_ret;\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t\t/* Increase bytes counter. */\n\t\trxq->stats.ibytes += len;\n#endif\nrepost:\n\t\tif (++elts_head >= elts_n)\n\t\t\telts_head = 0;\n\t\tcontinue;\n\t}\n\tif (unlikely(i == 0))\n\t\treturn 0;\n\t/* Repost WRs. */\n#ifdef DEBUG_RECV\n\tDEBUG(\"%p: reposting %u WRs\", (void *)rxq, i);\n#endif\n\tret = rxq->if_qp->recv_burst(rxq->qp, sges, i);\n\tif (unlikely(ret)) {\n\t\t/* Inability to repost WRs is fatal. */\n\t\tDEBUG(\"%p: recv_burst(): failed (ret=%d)\",\n\t\t (void *)rxq->priv,\n\t\t ret);\n\t\tabort();\n\t}\n\trxq->elts_head = elts_head;\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t/* Increase packets counter. */\n\trxq->stats.ipackets += pkts_ret;\n#endif\n\treturn pkts_ret;\n}\n\n/**\n * Allocate a Queue Pair.\n * Optionally setup inline receive if supported.\n *\n * @param priv\n * Pointer to private structure.\n * @param cq\n * Completion queue to associate with QP.\n * @param desc\n * Number of descriptors in QP (hint only).\n *\n * @return\n * QP pointer or NULL in case of error.\n */\nstatic struct ibv_qp *\nrxq_setup_qp(struct priv *priv, struct ibv_cq *cq, uint16_t desc,\n\t struct ibv_exp_res_domain *rd)\n{\n\tstruct ibv_exp_qp_init_attr attr = {\n\t\t/* CQ to be associated with the send queue. */\n\t\t.send_cq = cq,\n\t\t/* CQ to be associated with the receive queue. */\n\t\t.recv_cq = cq,\n\t\t.cap = {\n\t\t\t/* Max number of outstanding WRs. */\n\t\t\t.max_recv_wr = ((priv->device_attr.max_qp_wr < desc) ?\n\t\t\t\t\tpriv->device_attr.max_qp_wr :\n\t\t\t\t\tdesc),\n\t\t\t/* Max number of scatter/gather elements in a WR. */\n\t\t\t.max_recv_sge = ((priv->device_attr.max_sge <\n\t\t\t\t\t MLX4_PMD_SGE_WR_N) ?\n\t\t\t\t\t priv->device_attr.max_sge :\n\t\t\t\t\t MLX4_PMD_SGE_WR_N),\n\t\t},\n\t\t.qp_type = IBV_QPT_RAW_PACKET,\n\t\t.comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |\n\t\t\t IBV_EXP_QP_INIT_ATTR_RES_DOMAIN),\n\t\t.pd = priv->pd,\n\t\t.res_domain = rd,\n\t};\n\n#ifdef INLINE_RECV\n\tattr.max_inl_recv = priv->inl_recv_size;\n\tattr.comp_mask |= IBV_EXP_QP_INIT_ATTR_INL_RECV;\n#endif\n\treturn ibv_exp_create_qp(priv->ctx, &attr);\n}\n\n#ifdef RSS_SUPPORT\n\n/**\n * Allocate a RSS Queue Pair.\n * Optionally setup inline receive if supported.\n *\n * @param priv\n * Pointer to private structure.\n * @param cq\n * Completion queue to associate with QP.\n * @param desc\n * Number of descriptors in QP (hint only).\n * @param parent\n * If nonzero, create a parent QP, otherwise a child.\n *\n * @return\n * QP pointer or NULL in case of error.\n */\nstatic struct ibv_qp *\nrxq_setup_qp_rss(struct priv *priv, struct ibv_cq *cq, uint16_t desc,\n\t\t int parent, struct ibv_exp_res_domain *rd)\n{\n\tstruct ibv_exp_qp_init_attr attr = {\n\t\t/* CQ to be associated with the send queue. */\n\t\t.send_cq = cq,\n\t\t/* CQ to be associated with the receive queue. */\n\t\t.recv_cq = cq,\n\t\t.cap = {\n\t\t\t/* Max number of outstanding WRs. */\n\t\t\t.max_recv_wr = ((priv->device_attr.max_qp_wr < desc) ?\n\t\t\t\t\tpriv->device_attr.max_qp_wr :\n\t\t\t\t\tdesc),\n\t\t\t/* Max number of scatter/gather elements in a WR. */\n\t\t\t.max_recv_sge = ((priv->device_attr.max_sge <\n\t\t\t\t\t MLX4_PMD_SGE_WR_N) ?\n\t\t\t\t\t priv->device_attr.max_sge :\n\t\t\t\t\t MLX4_PMD_SGE_WR_N),\n\t\t},\n\t\t.qp_type = IBV_QPT_RAW_PACKET,\n\t\t.comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |\n\t\t\t IBV_EXP_QP_INIT_ATTR_RES_DOMAIN |\n\t\t\t IBV_EXP_QP_INIT_ATTR_QPG),\n\t\t.pd = priv->pd,\n\t\t.res_domain = rd,\n\t};\n\n#ifdef INLINE_RECV\n\tattr.max_inl_recv = priv->inl_recv_size,\n\tattr.comp_mask |= IBV_EXP_QP_INIT_ATTR_INL_RECV;\n#endif\n\tif (parent) {\n\t\tattr.qpg.qpg_type = IBV_EXP_QPG_PARENT;\n\t\t/* TSS isn't necessary. */\n\t\tattr.qpg.parent_attrib.tss_child_count = 0;\n\t\tattr.qpg.parent_attrib.rss_child_count = priv->rxqs_n;\n\t\tDEBUG(\"initializing parent RSS queue\");\n\t} else {\n\t\tattr.qpg.qpg_type = IBV_EXP_QPG_CHILD_RX;\n\t\tattr.qpg.qpg_parent = priv->rxq_parent.qp;\n\t\tDEBUG(\"initializing child RSS queue\");\n\t}\n\treturn ibv_exp_create_qp(priv->ctx, &attr);\n}\n\n#endif /* RSS_SUPPORT */\n\n/**\n * Reconfigure a RX queue with new parameters.\n *\n * rxq_rehash() does not allocate mbufs, which, if not done from the right\n * thread (such as a control thread), may corrupt the pool.\n * In case of failure, the queue is left untouched.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param rxq\n * RX queue pointer.\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\nrxq_rehash(struct rte_eth_dev *dev, struct rxq *rxq)\n{\n\tstruct priv *priv = rxq->priv;\n\tstruct rxq tmpl = *rxq;\n\tunsigned int mbuf_n;\n\tunsigned int desc_n;\n\tstruct rte_mbuf **pool;\n\tunsigned int i, k;\n\tstruct ibv_exp_qp_attr mod;\n\tstruct ibv_recv_wr *bad_wr;\n\tint err;\n\tint parent = (rxq == &priv->rxq_parent);\n\n\tif (parent) {\n\t\tERROR(\"%p: cannot rehash parent queue %p\",\n\t\t (void *)dev, (void *)rxq);\n\t\treturn EINVAL;\n\t}\n\tDEBUG(\"%p: rehashing queue %p\", (void *)dev, (void *)rxq);\n\t/* Number of descriptors and mbufs currently allocated. */\n\tdesc_n = (tmpl.elts_n * (tmpl.sp ? MLX4_PMD_SGE_WR_N : 1));\n\tmbuf_n = desc_n;\n\t/* Toggle RX checksum offload if hardware supports it. */\n\tif (priv->hw_csum) {\n\t\ttmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;\n\t\trxq->csum = tmpl.csum;\n\t}\n\tif (priv->hw_csum_l2tun) {\n\t\ttmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum;\n\t\trxq->csum_l2tun = tmpl.csum_l2tun;\n\t}\n\t/* Enable scattered packets support for this queue if necessary. */\n\tif ((dev->data->dev_conf.rxmode.jumbo_frame) &&\n\t (dev->data->dev_conf.rxmode.max_rx_pkt_len >\n\t (tmpl.mb_len - RTE_PKTMBUF_HEADROOM))) {\n\t\ttmpl.sp = 1;\n\t\tdesc_n /= MLX4_PMD_SGE_WR_N;\n\t} else\n\t\ttmpl.sp = 0;\n\tDEBUG(\"%p: %s scattered packets support (%u WRs)\",\n\t (void *)dev, (tmpl.sp ? \"enabling\" : \"disabling\"), desc_n);\n\t/* If scatter mode is the same as before, nothing to do. */\n\tif (tmpl.sp == rxq->sp) {\n\t\tDEBUG(\"%p: nothing to do\", (void *)dev);\n\t\treturn 0;\n\t}\n\t/* Remove attached flows if RSS is disabled (no parent queue). */\n\tif (!priv->rss) {\n\t\trxq_allmulticast_disable(&tmpl);\n\t\trxq_promiscuous_disable(&tmpl);\n\t\trxq_mac_addrs_del(&tmpl);\n\t\t/* Update original queue in case of failure. */\n\t\trxq->allmulti_flow = tmpl.allmulti_flow;\n\t\trxq->promisc_flow = tmpl.promisc_flow;\n\t\tmemcpy(rxq->mac_configured, tmpl.mac_configured,\n\t\t sizeof(rxq->mac_configured));\n\t\tmemcpy(rxq->mac_flow, tmpl.mac_flow, sizeof(rxq->mac_flow));\n\t}\n\t/* From now on, any failure will render the queue unusable.\n\t * Reinitialize QP. */\n\tmod = (struct ibv_exp_qp_attr){ .qp_state = IBV_QPS_RESET };\n\terr = ibv_exp_modify_qp(tmpl.qp, &mod, IBV_EXP_QP_STATE);\n\tif (err) {\n\t\tERROR(\"%p: cannot reset QP: %s\", (void *)dev, strerror(err));\n\t\tassert(err > 0);\n\t\treturn err;\n\t}\n\terr = ibv_resize_cq(tmpl.cq, desc_n);\n\tif (err) {\n\t\tERROR(\"%p: cannot resize CQ: %s\", (void *)dev, strerror(err));\n\t\tassert(err > 0);\n\t\treturn err;\n\t}\n\tmod = (struct ibv_exp_qp_attr){\n\t\t/* Move the QP to this state. */\n\t\t.qp_state = IBV_QPS_INIT,\n\t\t/* Primary port number. */\n\t\t.port_num = priv->port\n\t};\n\terr = ibv_exp_modify_qp(tmpl.qp, &mod,\n\t\t\t\t(IBV_EXP_QP_STATE |\n#ifdef RSS_SUPPORT\n\t\t\t\t (parent ? IBV_EXP_QP_GROUP_RSS : 0) |\n#endif /* RSS_SUPPORT */\n\t\t\t\t IBV_EXP_QP_PORT));\n\tif (err) {\n\t\tERROR(\"%p: QP state to IBV_QPS_INIT failed: %s\",\n\t\t (void *)dev, strerror(err));\n\t\tassert(err > 0);\n\t\treturn err;\n\t};\n\t/* Reconfigure flows. Do not care for errors. */\n\tif (!priv->rss) {\n\t\trxq_mac_addrs_add(&tmpl);\n\t\tif (priv->promisc)\n\t\t\trxq_promiscuous_enable(&tmpl);\n\t\tif (priv->allmulti)\n\t\t\trxq_allmulticast_enable(&tmpl);\n\t\t/* Update original queue in case of failure. */\n\t\trxq->allmulti_flow = tmpl.allmulti_flow;\n\t\trxq->promisc_flow = tmpl.promisc_flow;\n\t\tmemcpy(rxq->mac_configured, tmpl.mac_configured,\n\t\t sizeof(rxq->mac_configured));\n\t\tmemcpy(rxq->mac_flow, tmpl.mac_flow, sizeof(rxq->mac_flow));\n\t}\n\t/* Allocate pool. */\n\tpool = rte_malloc(__func__, (mbuf_n * sizeof(*pool)), 0);\n\tif (pool == NULL) {\n\t\tERROR(\"%p: cannot allocate memory\", (void *)dev);\n\t\treturn ENOBUFS;\n\t}\n\t/* Snatch mbufs from original queue. */\n\tk = 0;\n\tif (rxq->sp) {\n\t\tstruct rxq_elt_sp (*elts)[rxq->elts_n] = rxq->elts.sp;\n\n\t\tfor (i = 0; (i != elemof(*elts)); ++i) {\n\t\t\tstruct rxq_elt_sp *elt = &(*elts)[i];\n\t\t\tunsigned int j;\n\n\t\t\tfor (j = 0; (j != elemof(elt->bufs)); ++j) {\n\t\t\t\tassert(elt->bufs[j] != NULL);\n\t\t\t\tpool[k++] = elt->bufs[j];\n\t\t\t}\n\t\t}\n\t} else {\n\t\tstruct rxq_elt (*elts)[rxq->elts_n] = rxq->elts.no_sp;\n\n\t\tfor (i = 0; (i != elemof(*elts)); ++i) {\n\t\t\tstruct rxq_elt *elt = &(*elts)[i];\n\t\t\tstruct rte_mbuf *buf = (void *)\n\t\t\t\t((uintptr_t)elt->sge.addr -\n\t\t\t\t WR_ID(elt->wr.wr_id).offset);\n\n\t\t\tassert(WR_ID(elt->wr.wr_id).id == i);\n\t\t\tpool[k++] = buf;\n\t\t}\n\t}\n\tassert(k == mbuf_n);\n\ttmpl.elts_n = 0;\n\ttmpl.elts.sp = NULL;\n\tassert((void *)&tmpl.elts.sp == (void *)&tmpl.elts.no_sp);\n\terr = ((tmpl.sp) ?\n\t rxq_alloc_elts_sp(&tmpl, desc_n, pool) :\n\t rxq_alloc_elts(&tmpl, desc_n, pool));\n\tif (err) {\n\t\tERROR(\"%p: cannot reallocate WRs, aborting\", (void *)dev);\n\t\trte_free(pool);\n\t\tassert(err > 0);\n\t\treturn err;\n\t}\n\tassert(tmpl.elts_n == desc_n);\n\tassert(tmpl.elts.sp != NULL);\n\trte_free(pool);\n\t/* Clean up original data. */\n\trxq->elts_n = 0;\n\trte_free(rxq->elts.sp);\n\trxq->elts.sp = NULL;\n\t/* Post WRs. */\n\terr = ibv_post_recv(tmpl.qp,\n\t\t\t (tmpl.sp ?\n\t\t\t &(*tmpl.elts.sp)[0].wr :\n\t\t\t &(*tmpl.elts.no_sp)[0].wr),\n\t\t\t &bad_wr);\n\tif (err) {\n\t\tERROR(\"%p: ibv_post_recv() failed for WR %p: %s\",\n\t\t (void *)dev,\n\t\t (void *)bad_wr,\n\t\t strerror(err));\n\t\tgoto skip_rtr;\n\t}\n\tmod = (struct ibv_exp_qp_attr){\n\t\t.qp_state = IBV_QPS_RTR\n\t};\n\terr = ibv_exp_modify_qp(tmpl.qp, &mod, IBV_EXP_QP_STATE);\n\tif (err)\n\t\tERROR(\"%p: QP state to IBV_QPS_RTR failed: %s\",\n\t\t (void *)dev, strerror(err));\nskip_rtr:\n\t*rxq = tmpl;\n\tassert(err >= 0);\n\treturn err;\n}\n\n/**\n * Configure a RX queue.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param rxq\n * Pointer to RX queue structure.\n * @param desc\n * Number of descriptors to configure in queue.\n * @param socket\n * NUMA socket on which memory must be allocated.\n * @param[in] conf\n * Thresholds parameters.\n * @param mp\n * Memory pool for buffer allocations.\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\nrxq_setup(struct rte_eth_dev *dev, struct rxq *rxq, uint16_t desc,\n\t unsigned int socket, const struct rte_eth_rxconf *conf,\n\t struct rte_mempool *mp)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tstruct rxq tmpl = {\n\t\t.priv = priv,\n\t\t.mp = mp,\n\t\t.socket = socket\n\t};\n\tstruct ibv_exp_qp_attr mod;\n\tunion {\n\t\tstruct ibv_exp_query_intf_params params;\n\t\tstruct ibv_exp_cq_init_attr cq;\n\t\tstruct ibv_exp_res_domain_init_attr rd;\n\t} attr;\n\tenum ibv_exp_query_intf_status status;\n\tstruct ibv_recv_wr *bad_wr;\n\tstruct rte_mbuf *buf;\n\tint ret = 0;\n\tint parent = (rxq == &priv->rxq_parent);\n\n\t(void)conf; /* Thresholds configuration (ignored). */\n\t/*\n\t * If this is a parent queue, hardware must support RSS and\n\t * RSS must be enabled.\n\t */\n\tassert((!parent) || ((priv->hw_rss) && (priv->rss)));\n\tif (parent) {\n\t\t/* Even if unused, ibv_create_cq() requires at least one\n\t\t * descriptor. */\n\t\tdesc = 1;\n\t\tgoto skip_mr;\n\t}\n\tif ((desc == 0) || (desc % MLX4_PMD_SGE_WR_N)) {\n\t\tERROR(\"%p: invalid number of RX descriptors (must be a\"\n\t\t \" multiple of %d)\", (void *)dev, MLX4_PMD_SGE_WR_N);\n\t\treturn EINVAL;\n\t}\n\t/* Get mbuf length. */\n\tbuf = rte_pktmbuf_alloc(mp);\n\tif (buf == NULL) {\n\t\tERROR(\"%p: unable to allocate mbuf\", (void *)dev);\n\t\treturn ENOMEM;\n\t}\n\ttmpl.mb_len = buf->buf_len;\n\tassert((rte_pktmbuf_headroom(buf) +\n\t\trte_pktmbuf_tailroom(buf)) == tmpl.mb_len);\n\tassert(rte_pktmbuf_headroom(buf) == RTE_PKTMBUF_HEADROOM);\n\trte_pktmbuf_free(buf);\n\t/* Toggle RX checksum offload if hardware supports it. */\n\tif (priv->hw_csum)\n\t\ttmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;\n\tif (priv->hw_csum_l2tun)\n\t\ttmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum;\n\t/* Enable scattered packets support for this queue if necessary. */\n\tif ((dev->data->dev_conf.rxmode.jumbo_frame) &&\n\t (dev->data->dev_conf.rxmode.max_rx_pkt_len >\n\t (tmpl.mb_len - RTE_PKTMBUF_HEADROOM))) {\n\t\ttmpl.sp = 1;\n\t\tdesc /= MLX4_PMD_SGE_WR_N;\n\t}\n\tDEBUG(\"%p: %s scattered packets support (%u WRs)\",\n\t (void *)dev, (tmpl.sp ? \"enabling\" : \"disabling\"), desc);\n\t/* Use the entire RX mempool as the memory region. */\n\ttmpl.mr = ibv_reg_mr(priv->pd,\n\t\t\t (void *)mp->elt_va_start,\n\t\t\t (mp->elt_va_end - mp->elt_va_start),\n\t\t\t (IBV_ACCESS_LOCAL_WRITE |\n\t\t\t IBV_ACCESS_REMOTE_WRITE));\n\tif (tmpl.mr == NULL) {\n\t\tret = EINVAL;\n\t\tERROR(\"%p: MR creation failure: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\nskip_mr:\n\tattr.rd = (struct ibv_exp_res_domain_init_attr){\n\t\t.comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL |\n\t\t\t IBV_EXP_RES_DOMAIN_MSG_MODEL),\n\t\t.thread_model = IBV_EXP_THREAD_SINGLE,\n\t\t.msg_model = IBV_EXP_MSG_HIGH_BW,\n\t};\n\ttmpl.rd = ibv_exp_create_res_domain(priv->ctx, &attr.rd);\n\tif (tmpl.rd == NULL) {\n\t\tret = ENOMEM;\n\t\tERROR(\"%p: RD creation failure: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n\tattr.cq = (struct ibv_exp_cq_init_attr){\n\t\t.comp_mask = IBV_EXP_CQ_INIT_ATTR_RES_DOMAIN,\n\t\t.res_domain = tmpl.rd,\n\t};\n\ttmpl.cq = ibv_exp_create_cq(priv->ctx, desc, NULL, NULL, 0, &attr.cq);\n\tif (tmpl.cq == NULL) {\n\t\tret = ENOMEM;\n\t\tERROR(\"%p: CQ creation failure: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n\tDEBUG(\"priv->device_attr.max_qp_wr is %d\",\n\t priv->device_attr.max_qp_wr);\n\tDEBUG(\"priv->device_attr.max_sge is %d\",\n\t priv->device_attr.max_sge);\n#ifdef RSS_SUPPORT\n\tif (priv->rss)\n\t\ttmpl.qp = rxq_setup_qp_rss(priv, tmpl.cq, desc, parent,\n\t\t\t\t\t tmpl.rd);\n\telse\n#endif /* RSS_SUPPORT */\n\t\ttmpl.qp = rxq_setup_qp(priv, tmpl.cq, desc, tmpl.rd);\n\tif (tmpl.qp == NULL) {\n\t\tret = (errno ? errno : EINVAL);\n\t\tERROR(\"%p: QP creation failure: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n\tmod = (struct ibv_exp_qp_attr){\n\t\t/* Move the QP to this state. */\n\t\t.qp_state = IBV_QPS_INIT,\n\t\t/* Primary port number. */\n\t\t.port_num = priv->port\n\t};\n\tret = ibv_exp_modify_qp(tmpl.qp, &mod,\n\t\t\t\t(IBV_EXP_QP_STATE |\n#ifdef RSS_SUPPORT\n\t\t\t\t (parent ? IBV_EXP_QP_GROUP_RSS : 0) |\n#endif /* RSS_SUPPORT */\n\t\t\t\t IBV_EXP_QP_PORT));\n\tif (ret) {\n\t\tERROR(\"%p: QP state to IBV_QPS_INIT failed: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n\tif ((parent) || (!priv->rss)) {\n\t\t/* Configure MAC and broadcast addresses. */\n\t\tret = rxq_mac_addrs_add(&tmpl);\n\t\tif (ret) {\n\t\t\tERROR(\"%p: QP flow attachment failed: %s\",\n\t\t\t (void *)dev, strerror(ret));\n\t\t\tgoto error;\n\t\t}\n\t}\n\t/* Allocate descriptors for RX queues, except for the RSS parent. */\n\tif (parent)\n\t\tgoto skip_alloc;\n\tif (tmpl.sp)\n\t\tret = rxq_alloc_elts_sp(&tmpl, desc, NULL);\n\telse\n\t\tret = rxq_alloc_elts(&tmpl, desc, NULL);\n\tif (ret) {\n\t\tERROR(\"%p: RXQ allocation failed: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n\tret = ibv_post_recv(tmpl.qp,\n\t\t\t (tmpl.sp ?\n\t\t\t &(*tmpl.elts.sp)[0].wr :\n\t\t\t &(*tmpl.elts.no_sp)[0].wr),\n\t\t\t &bad_wr);\n\tif (ret) {\n\t\tERROR(\"%p: ibv_post_recv() failed for WR %p: %s\",\n\t\t (void *)dev,\n\t\t (void *)bad_wr,\n\t\t strerror(ret));\n\t\tgoto error;\n\t}\nskip_alloc:\n\tmod = (struct ibv_exp_qp_attr){\n\t\t.qp_state = IBV_QPS_RTR\n\t};\n\tret = ibv_exp_modify_qp(tmpl.qp, &mod, IBV_EXP_QP_STATE);\n\tif (ret) {\n\t\tERROR(\"%p: QP state to IBV_QPS_RTR failed: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\tgoto error;\n\t}\n\t/* Save port ID. */\n\ttmpl.port_id = dev->data->port_id;\n\tDEBUG(\"%p: RTE port ID: %u\", (void *)rxq, tmpl.port_id);\n\tattr.params = (struct ibv_exp_query_intf_params){\n\t\t.intf_scope = IBV_EXP_INTF_GLOBAL,\n\t\t.intf = IBV_EXP_INTF_CQ,\n\t\t.obj = tmpl.cq,\n\t};\n\ttmpl.if_cq = ibv_exp_query_intf(priv->ctx, &attr.params, &status);\n\tif (tmpl.if_cq == NULL) {\n\t\tERROR(\"%p: CQ interface family query failed with status %d\",\n\t\t (void *)dev, status);\n\t\tgoto error;\n\t}\n\tattr.params = (struct ibv_exp_query_intf_params){\n\t\t.intf_scope = IBV_EXP_INTF_GLOBAL,\n\t\t.intf = IBV_EXP_INTF_QP_BURST,\n\t\t.obj = tmpl.qp,\n\t};\n\ttmpl.if_qp = ibv_exp_query_intf(priv->ctx, &attr.params, &status);\n\tif (tmpl.if_qp == NULL) {\n\t\tERROR(\"%p: QP interface family query failed with status %d\",\n\t\t (void *)dev, status);\n\t\tgoto error;\n\t}\n\t/* Clean up rxq in case we're reinitializing it. */\n\tDEBUG(\"%p: cleaning-up old rxq just in case\", (void *)rxq);\n\trxq_cleanup(rxq);\n\t*rxq = tmpl;\n\tDEBUG(\"%p: rxq updated with %p\", (void *)rxq, (void *)&tmpl);\n\tassert(ret == 0);\n\treturn 0;\nerror:\n\trxq_cleanup(&tmpl);\n\tassert(ret > 0);\n\treturn ret;\n}\n\n/**\n * DPDK callback to configure a RX queue.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param idx\n * RX queue index.\n * @param desc\n * Number of descriptors to configure in queue.\n * @param socket\n * NUMA socket on which memory must be allocated.\n * @param[in] conf\n * Thresholds parameters.\n * @param mp\n * Memory pool for buffer allocations.\n *\n * @return\n * 0 on success, negative errno value on failure.\n */\nstatic int\nmlx4_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n\t\t unsigned int socket, const struct rte_eth_rxconf *conf,\n\t\t struct rte_mempool *mp)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tstruct rxq *rxq = (*priv->rxqs)[idx];\n\tint ret;\n\n\tpriv_lock(priv);\n\tDEBUG(\"%p: configuring queue %u for %u descriptors\",\n\t (void *)dev, idx, desc);\n\tif (idx >= priv->rxqs_n) {\n\t\tERROR(\"%p: queue index out of range (%u >= %u)\",\n\t\t (void *)dev, idx, priv->rxqs_n);\n\t\tpriv_unlock(priv);\n\t\treturn -EOVERFLOW;\n\t}\n\tif (rxq != NULL) {\n\t\tDEBUG(\"%p: reusing already allocated queue index %u (%p)\",\n\t\t (void *)dev, idx, (void *)rxq);\n\t\tif (priv->started) {\n\t\t\tpriv_unlock(priv);\n\t\t\treturn -EEXIST;\n\t\t}\n\t\t(*priv->rxqs)[idx] = NULL;\n\t\trxq_cleanup(rxq);\n\t} else {\n\t\trxq = rte_calloc_socket(\"RXQ\", 1, sizeof(*rxq), 0, socket);\n\t\tif (rxq == NULL) {\n\t\t\tERROR(\"%p: unable to allocate queue index %u\",\n\t\t\t (void *)dev, idx);\n\t\t\tpriv_unlock(priv);\n\t\t\treturn -ENOMEM;\n\t\t}\n\t}\n\tret = rxq_setup(dev, rxq, desc, socket, conf, mp);\n\tif (ret)\n\t\trte_free(rxq);\n\telse {\n\t\trxq->stats.idx = idx;\n\t\tDEBUG(\"%p: adding RX queue %p to list\",\n\t\t (void *)dev, (void *)rxq);\n\t\t(*priv->rxqs)[idx] = rxq;\n\t\t/* Update receive callback. */\n\t\tif (rxq->sp)\n\t\t\tdev->rx_pkt_burst = mlx4_rx_burst_sp;\n\t\telse\n\t\t\tdev->rx_pkt_burst = mlx4_rx_burst;\n\t}\n\tpriv_unlock(priv);\n\treturn -ret;\n}\n\n/**\n * DPDK callback to release a RX queue.\n *\n * @param dpdk_rxq\n * Generic RX queue pointer.\n */\nstatic void\nmlx4_rx_queue_release(void *dpdk_rxq)\n{\n\tstruct rxq *rxq = (struct rxq *)dpdk_rxq;\n\tstruct priv *priv;\n\tunsigned int i;\n\n\tif (rxq == NULL)\n\t\treturn;\n\tpriv = rxq->priv;\n\tpriv_lock(priv);\n\tassert(rxq != &priv->rxq_parent);\n\tfor (i = 0; (i != priv->rxqs_n); ++i)\n\t\tif ((*priv->rxqs)[i] == rxq) {\n\t\t\tDEBUG(\"%p: removing RX queue %p from list\",\n\t\t\t (void *)priv->dev, (void *)rxq);\n\t\t\t(*priv->rxqs)[i] = NULL;\n\t\t\tbreak;\n\t\t}\n\trxq_cleanup(rxq);\n\trte_free(rxq);\n\tpriv_unlock(priv);\n}\n\n/**\n * DPDK callback to start the device.\n *\n * Simulate device start by attaching all configured flows.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n *\n * @return\n * 0 on success, negative errno value on failure.\n */\nstatic int\nmlx4_dev_start(struct rte_eth_dev *dev)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tunsigned int i = 0;\n\tunsigned int r;\n\tstruct rxq *rxq;\n\n\tpriv_lock(priv);\n\tif (priv->started) {\n\t\tpriv_unlock(priv);\n\t\treturn 0;\n\t}\n\tDEBUG(\"%p: attaching configured flows to all RX queues\", (void *)dev);\n\tpriv->started = 1;\n\tif (priv->rss) {\n\t\trxq = &priv->rxq_parent;\n\t\tr = 1;\n\t} else {\n\t\trxq = (*priv->rxqs)[0];\n\t\tr = priv->rxqs_n;\n\t}\n\t/* Iterate only once when RSS is enabled. */\n\tdo {\n\t\tint ret;\n\n\t\t/* Ignore nonexistent RX queues. */\n\t\tif (rxq == NULL)\n\t\t\tcontinue;\n\t\tret = rxq_mac_addrs_add(rxq);\n\t\tif (!ret && priv->promisc)\n\t\t\tret = rxq_promiscuous_enable(rxq);\n\t\tif (!ret && priv->allmulti)\n\t\t\tret = rxq_allmulticast_enable(rxq);\n\t\tif (!ret)\n\t\t\tcontinue;\n\t\tWARN(\"%p: QP flow attachment failed: %s\",\n\t\t (void *)dev, strerror(ret));\n\t\t/* Rollback. */\n\t\twhile (i != 0) {\n\t\t\trxq = (*priv->rxqs)[--i];\n\t\t\tif (rxq != NULL) {\n\t\t\t\trxq_allmulticast_disable(rxq);\n\t\t\t\trxq_promiscuous_disable(rxq);\n\t\t\t\trxq_mac_addrs_del(rxq);\n\t\t\t}\n\t\t}\n\t\tpriv->started = 0;\n\t\treturn -ret;\n\t} while ((--r) && ((rxq = (*priv->rxqs)[++i]), i));\n\tpriv_unlock(priv);\n\treturn 0;\n}\n\n/**\n * DPDK callback to stop the device.\n *\n * Simulate device stop by detaching all configured flows.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n */\nstatic void\nmlx4_dev_stop(struct rte_eth_dev *dev)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tunsigned int i = 0;\n\tunsigned int r;\n\tstruct rxq *rxq;\n\n\tpriv_lock(priv);\n\tif (!priv->started) {\n\t\tpriv_unlock(priv);\n\t\treturn;\n\t}\n\tDEBUG(\"%p: detaching flows from all RX queues\", (void *)dev);\n\tpriv->started = 0;\n\tif (priv->rss) {\n\t\trxq = &priv->rxq_parent;\n\t\tr = 1;\n\t} else {\n\t\trxq = (*priv->rxqs)[0];\n\t\tr = priv->rxqs_n;\n\t}\n\t/* Iterate only once when RSS is enabled. */\n\tdo {\n\t\t/* Ignore nonexistent RX queues. */\n\t\tif (rxq == NULL)\n\t\t\tcontinue;\n\t\trxq_allmulticast_disable(rxq);\n\t\trxq_promiscuous_disable(rxq);\n\t\trxq_mac_addrs_del(rxq);\n\t} while ((--r) && ((rxq = (*priv->rxqs)[++i]), i));\n\tpriv_unlock(priv);\n}\n\n/**\n * Dummy DPDK callback for TX.\n *\n * This function is used to temporarily replace the real callback during\n * unsafe control operations on the queue, or in case of error.\n *\n * @param dpdk_txq\n * Generic pointer to TX queue structure.\n * @param[in] pkts\n * Packets to transmit.\n * @param pkts_n\n * Number of packets in array.\n *\n * @return\n * Number of packets successfully transmitted (<= pkts_n).\n */\nstatic uint16_t\nremoved_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n{\n\t(void)dpdk_txq;\n\t(void)pkts;\n\t(void)pkts_n;\n\treturn 0;\n}\n\n/**\n * Dummy DPDK callback for RX.\n *\n * This function is used to temporarily replace the real callback during\n * unsafe control operations on the queue, or in case of error.\n *\n * @param dpdk_rxq\n * Generic pointer to RX queue structure.\n * @param[out] pkts\n * Array to store received packets.\n * @param pkts_n\n * Maximum number of packets in array.\n *\n * @return\n * Number of packets successfully received (<= pkts_n).\n */\nstatic uint16_t\nremoved_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)\n{\n\t(void)dpdk_rxq;\n\t(void)pkts;\n\t(void)pkts_n;\n\treturn 0;\n}\n\n/**\n * DPDK callback to close the device.\n *\n * Destroy all queues and objects, free memory.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n */\nstatic void\nmlx4_dev_close(struct rte_eth_dev *dev)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tvoid *tmp;\n\tunsigned int i;\n\n\tpriv_lock(priv);\n\tDEBUG(\"%p: closing device \\\"%s\\\"\",\n\t (void *)dev,\n\t ((priv->ctx != NULL) ? priv->ctx->device->name : \"\"));\n\t/* Prevent crashes when queues are still in use. This is unfortunately\n\t * still required for DPDK 1.3 because some programs (such as testpmd)\n\t * never release them before closing the device. */\n\tdev->rx_pkt_burst = removed_rx_burst;\n\tdev->tx_pkt_burst = removed_tx_burst;\n\tif (priv->rxqs != NULL) {\n\t\t/* XXX race condition if mlx4_rx_burst() is still running. */\n\t\tusleep(1000);\n\t\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n\t\t\ttmp = (*priv->rxqs)[i];\n\t\t\tif (tmp == NULL)\n\t\t\t\tcontinue;\n\t\t\t(*priv->rxqs)[i] = NULL;\n\t\t\trxq_cleanup(tmp);\n\t\t\trte_free(tmp);\n\t\t}\n\t\tpriv->rxqs_n = 0;\n\t\tpriv->rxqs = NULL;\n\t}\n\tif (priv->txqs != NULL) {\n\t\t/* XXX race condition if mlx4_tx_burst() is still running. */\n\t\tusleep(1000);\n\t\tfor (i = 0; (i != priv->txqs_n); ++i) {\n\t\t\ttmp = (*priv->txqs)[i];\n\t\t\tif (tmp == NULL)\n\t\t\t\tcontinue;\n\t\t\t(*priv->txqs)[i] = NULL;\n\t\t\ttxq_cleanup(tmp);\n\t\t\trte_free(tmp);\n\t\t}\n\t\tpriv->txqs_n = 0;\n\t\tpriv->txqs = NULL;\n\t}\n\tif (priv->rss)\n\t\trxq_cleanup(&priv->rxq_parent);\n\tif (priv->pd != NULL) {\n\t\tassert(priv->ctx != NULL);\n\t\tclaim_zero(ibv_dealloc_pd(priv->pd));\n\t\tclaim_zero(ibv_close_device(priv->ctx));\n\t} else\n\t\tassert(priv->ctx == NULL);\n\tpriv_unlock(priv);\n\tmemset(priv, 0, sizeof(*priv));\n}\n\n/**\n * DPDK callback to get information about the device.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param[out] info\n * Info structure output buffer.\n */\nstatic void\nmlx4_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tunsigned int max;\n\n\tpriv_lock(priv);\n\t/* FIXME: we should ask the device for these values. */\n\tinfo->min_rx_bufsize = 32;\n\tinfo->max_rx_pktlen = 65536;\n\t/*\n\t * Since we need one CQ per QP, the limit is the minimum number\n\t * between the two values.\n\t */\n\tmax = ((priv->device_attr.max_cq > priv->device_attr.max_qp) ?\n\t priv->device_attr.max_qp : priv->device_attr.max_cq);\n\t/* If max >= 65535 then max = 0, max_rx_queues is uint16_t. */\n\tif (max >= 65535)\n\t\tmax = 65535;\n\tinfo->max_rx_queues = max;\n\tinfo->max_tx_queues = max;\n\tinfo->max_mac_addrs = elemof(priv->mac);\n\tinfo->rx_offload_capa =\n\t\t(priv->hw_csum ?\n\t\t (DEV_RX_OFFLOAD_IPV4_CKSUM |\n\t\t DEV_RX_OFFLOAD_UDP_CKSUM |\n\t\t DEV_RX_OFFLOAD_TCP_CKSUM) :\n\t\t 0);\n\tinfo->tx_offload_capa =\n\t\t(priv->hw_csum ?\n\t\t (DEV_TX_OFFLOAD_IPV4_CKSUM |\n\t\t DEV_TX_OFFLOAD_UDP_CKSUM |\n\t\t DEV_TX_OFFLOAD_TCP_CKSUM) :\n\t\t 0);\n\tpriv_unlock(priv);\n}\n\n/**\n * DPDK callback to get device statistics.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param[out] stats\n * Stats structure output buffer.\n */\nstatic void\nmlx4_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tstruct rte_eth_stats tmp = {0};\n\tunsigned int i;\n\tunsigned int idx;\n\n\tpriv_lock(priv);\n\t/* Add software counters. */\n\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n\t\tstruct rxq *rxq = (*priv->rxqs)[i];\n\n\t\tif (rxq == NULL)\n\t\t\tcontinue;\n\t\tidx = rxq->stats.idx;\n\t\tif (idx < RTE_ETHDEV_QUEUE_STAT_CNTRS) {\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t\t\ttmp.q_ipackets[idx] += rxq->stats.ipackets;\n\t\t\ttmp.q_ibytes[idx] += rxq->stats.ibytes;\n#endif\n\t\t\ttmp.q_errors[idx] += (rxq->stats.idropped +\n\t\t\t\t\t rxq->stats.rx_nombuf);\n\t\t}\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t\ttmp.ipackets += rxq->stats.ipackets;\n\t\ttmp.ibytes += rxq->stats.ibytes;\n#endif\n\t\ttmp.ierrors += rxq->stats.idropped;\n\t\ttmp.rx_nombuf += rxq->stats.rx_nombuf;\n\t}\n\tfor (i = 0; (i != priv->txqs_n); ++i) {\n\t\tstruct txq *txq = (*priv->txqs)[i];\n\n\t\tif (txq == NULL)\n\t\t\tcontinue;\n\t\tidx = txq->stats.idx;\n\t\tif (idx < RTE_ETHDEV_QUEUE_STAT_CNTRS) {\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t\t\ttmp.q_opackets[idx] += txq->stats.opackets;\n\t\t\ttmp.q_obytes[idx] += txq->stats.obytes;\n#endif\n\t\t\ttmp.q_errors[idx] += txq->stats.odropped;\n\t\t}\n#ifdef MLX4_PMD_SOFT_COUNTERS\n\t\ttmp.opackets += txq->stats.opackets;\n\t\ttmp.obytes += txq->stats.obytes;\n#endif\n\t\ttmp.oerrors += txq->stats.odropped;\n\t}\n#ifndef MLX4_PMD_SOFT_COUNTERS\n\t/* FIXME: retrieve and add hardware counters. */\n#endif\n\t*stats = tmp;\n\tpriv_unlock(priv);\n}\n\n/**\n * DPDK callback to clear device statistics.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n */\nstatic void\nmlx4_stats_reset(struct rte_eth_dev *dev)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tunsigned int i;\n\tunsigned int idx;\n\n\tpriv_lock(priv);\n\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n\t\tif ((*priv->rxqs)[i] == NULL)\n\t\t\tcontinue;\n\t\tidx = (*priv->rxqs)[i]->stats.idx;\n\t\t(*priv->rxqs)[i]->stats =\n\t\t\t(struct mlx4_rxq_stats){ .idx = idx };\n\t}\n\tfor (i = 0; (i != priv->txqs_n); ++i) {\n\t\tif ((*priv->txqs)[i] == NULL)\n\t\t\tcontinue;\n\t\tidx = (*priv->rxqs)[i]->stats.idx;\n\t\t(*priv->txqs)[i]->stats =\n\t\t\t(struct mlx4_txq_stats){ .idx = idx };\n\t}\n#ifndef MLX4_PMD_SOFT_COUNTERS\n\t/* FIXME: reset hardware counters. */\n#endif\n\tpriv_unlock(priv);\n}\n\n/**\n * DPDK callback to remove a MAC address.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param index\n * MAC address index.\n */\nstatic void\nmlx4_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\n\tpriv_lock(priv);\n\tDEBUG(\"%p: removing MAC address from index %\" PRIu32,\n\t (void *)dev, index);\n\tif (index >= MLX4_MAX_MAC_ADDRESSES)\n\t\tgoto end;\n\t/* Refuse to remove the broadcast address, this one is special. */\n\tif (!memcmp(priv->mac[index].addr_bytes, \"\\xff\\xff\\xff\\xff\\xff\\xff\",\n\t\t ETHER_ADDR_LEN))\n\t\tgoto end;\n\tpriv_mac_addr_del(priv, index);\nend:\n\tpriv_unlock(priv);\n}\n\n/**\n * DPDK callback to add a MAC address.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param mac_addr\n * MAC address to register.\n * @param index\n * MAC address index.\n * @param vmdq\n * VMDq pool index to associate address with (ignored).\n */\nstatic void\nmlx4_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,\n\t\t uint32_t index, uint32_t vmdq)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\n\t(void)vmdq;\n\tpriv_lock(priv);\n\tDEBUG(\"%p: adding MAC address at index %\" PRIu32,\n\t (void *)dev, index);\n\tif (index >= MLX4_MAX_MAC_ADDRESSES)\n\t\tgoto end;\n\t/* Refuse to add the broadcast address, this one is special. */\n\tif (!memcmp(mac_addr->addr_bytes, \"\\xff\\xff\\xff\\xff\\xff\\xff\",\n\t\t ETHER_ADDR_LEN))\n\t\tgoto end;\n\tpriv_mac_addr_add(priv, index,\n\t\t\t (const uint8_t (*)[ETHER_ADDR_LEN])\n\t\t\t mac_addr->addr_bytes);\nend:\n\tpriv_unlock(priv);\n}\n\n/**\n * DPDK callback to enable promiscuous mode.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n */\nstatic void\nmlx4_promiscuous_enable(struct rte_eth_dev *dev)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tunsigned int i;\n\tint ret;\n\n\tpriv_lock(priv);\n\tif (priv->promisc) {\n\t\tpriv_unlock(priv);\n\t\treturn;\n\t}\n\t/* If device isn't started, this is all we need to do. */\n\tif (!priv->started)\n\t\tgoto end;\n\tif (priv->rss) {\n\t\tret = rxq_promiscuous_enable(&priv->rxq_parent);\n\t\tif (ret) {\n\t\t\tpriv_unlock(priv);\n\t\t\treturn;\n\t\t}\n\t\tgoto end;\n\t}\n\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n\t\tif ((*priv->rxqs)[i] == NULL)\n\t\t\tcontinue;\n\t\tret = rxq_promiscuous_enable((*priv->rxqs)[i]);\n\t\tif (!ret)\n\t\t\tcontinue;\n\t\t/* Failure, rollback. */\n\t\twhile (i != 0)\n\t\t\tif ((*priv->rxqs)[--i] != NULL)\n\t\t\t\trxq_promiscuous_disable((*priv->rxqs)[i]);\n\t\tpriv_unlock(priv);\n\t\treturn;\n\t}\nend:\n\tpriv->promisc = 1;\n\tpriv_unlock(priv);\n}\n\n/**\n * DPDK callback to disable promiscuous mode.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n */\nstatic void\nmlx4_promiscuous_disable(struct rte_eth_dev *dev)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tunsigned int i;\n\n\tpriv_lock(priv);\n\tif (!priv->promisc) {\n\t\tpriv_unlock(priv);\n\t\treturn;\n\t}\n\tif (priv->rss) {\n\t\trxq_promiscuous_disable(&priv->rxq_parent);\n\t\tgoto end;\n\t}\n\tfor (i = 0; (i != priv->rxqs_n); ++i)\n\t\tif ((*priv->rxqs)[i] != NULL)\n\t\t\trxq_promiscuous_disable((*priv->rxqs)[i]);\nend:\n\tpriv->promisc = 0;\n\tpriv_unlock(priv);\n}\n\n/**\n * DPDK callback to enable allmulti mode.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n */\nstatic void\nmlx4_allmulticast_enable(struct rte_eth_dev *dev)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tunsigned int i;\n\tint ret;\n\n\tpriv_lock(priv);\n\tif (priv->allmulti) {\n\t\tpriv_unlock(priv);\n\t\treturn;\n\t}\n\t/* If device isn't started, this is all we need to do. */\n\tif (!priv->started)\n\t\tgoto end;\n\tif (priv->rss) {\n\t\tret = rxq_allmulticast_enable(&priv->rxq_parent);\n\t\tif (ret) {\n\t\t\tpriv_unlock(priv);\n\t\t\treturn;\n\t\t}\n\t\tgoto end;\n\t}\n\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n\t\tif ((*priv->rxqs)[i] == NULL)\n\t\t\tcontinue;\n\t\tret = rxq_allmulticast_enable((*priv->rxqs)[i]);\n\t\tif (!ret)\n\t\t\tcontinue;\n\t\t/* Failure, rollback. */\n\t\twhile (i != 0)\n\t\t\tif ((*priv->rxqs)[--i] != NULL)\n\t\t\t\trxq_allmulticast_disable((*priv->rxqs)[i]);\n\t\tpriv_unlock(priv);\n\t\treturn;\n\t}\nend:\n\tpriv->allmulti = 1;\n\tpriv_unlock(priv);\n}\n\n/**\n * DPDK callback to disable allmulti mode.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n */\nstatic void\nmlx4_allmulticast_disable(struct rte_eth_dev *dev)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tunsigned int i;\n\n\tpriv_lock(priv);\n\tif (!priv->allmulti) {\n\t\tpriv_unlock(priv);\n\t\treturn;\n\t}\n\tif (priv->rss) {\n\t\trxq_allmulticast_disable(&priv->rxq_parent);\n\t\tgoto end;\n\t}\n\tfor (i = 0; (i != priv->rxqs_n); ++i)\n\t\tif ((*priv->rxqs)[i] != NULL)\n\t\t\trxq_allmulticast_disable((*priv->rxqs)[i]);\nend:\n\tpriv->allmulti = 0;\n\tpriv_unlock(priv);\n}\n\n/**\n * DPDK callback to retrieve physical link information (unlocked version).\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param wait_to_complete\n * Wait for request completion (ignored).\n */\nstatic int\nmlx4_link_update_unlocked(struct rte_eth_dev *dev, int wait_to_complete)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tstruct ethtool_cmd edata = {\n\t\t.cmd = ETHTOOL_GSET\n\t};\n\tstruct ifreq ifr;\n\tstruct rte_eth_link dev_link;\n\tint link_speed = 0;\n\n\t(void)wait_to_complete;\n\tif (priv_ifreq(priv, SIOCGIFFLAGS, &ifr)) {\n\t\tWARN(\"ioctl(SIOCGIFFLAGS) failed: %s\", strerror(errno));\n\t\treturn -1;\n\t}\n\tmemset(&dev_link, 0, sizeof(dev_link));\n\tdev_link.link_status = ((ifr.ifr_flags & IFF_UP) &&\n\t\t\t\t(ifr.ifr_flags & IFF_RUNNING));\n\tifr.ifr_data = &edata;\n\tif (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {\n\t\tWARN(\"ioctl(SIOCETHTOOL, ETHTOOL_GSET) failed: %s\",\n\t\t strerror(errno));\n\t\treturn -1;\n\t}\n\tlink_speed = ethtool_cmd_speed(&edata);\n\tif (link_speed == -1)\n\t\tdev_link.link_speed = 0;\n\telse\n\t\tdev_link.link_speed = link_speed;\n\tdev_link.link_duplex = ((edata.duplex == DUPLEX_HALF) ?\n\t\t\t\tETH_LINK_HALF_DUPLEX : ETH_LINK_FULL_DUPLEX);\n\tif (memcmp(&dev_link, &dev->data->dev_link, sizeof(dev_link))) {\n\t\t/* Link status changed. */\n\t\tdev->data->dev_link = dev_link;\n\t\treturn 0;\n\t}\n\t/* Link status is still the same. */\n\treturn -1;\n}\n\n/**\n * DPDK callback to retrieve physical link information.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param wait_to_complete\n * Wait for request completion (ignored).\n */\nstatic int\nmlx4_link_update(struct rte_eth_dev *dev, int wait_to_complete)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tint ret;\n\n\tpriv_lock(priv);\n\tret = mlx4_link_update_unlocked(dev, wait_to_complete);\n\tpriv_unlock(priv);\n\treturn ret;\n}\n\n/**\n * DPDK callback to change the MTU.\n *\n * Setting the MTU affects hardware MRU (packets larger than the MTU cannot be\n * received). Use this as a hint to enable/disable scattered packets support\n * and improve performance when not needed.\n * Since failure is not an option, reconfiguring queues on the fly is not\n * recommended.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param in_mtu\n * New MTU.\n *\n * @return\n * 0 on success, negative errno value on failure.\n */\nstatic int\nmlx4_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tint ret = 0;\n\tunsigned int i;\n\tuint16_t (*rx_func)(void *, struct rte_mbuf **, uint16_t) =\n\t\tmlx4_rx_burst;\n\n\tpriv_lock(priv);\n\t/* Set kernel interface MTU first. */\n\tif (priv_set_mtu(priv, mtu)) {\n\t\tret = errno;\n\t\tWARN(\"cannot set port %u MTU to %u: %s\", priv->port, mtu,\n\t\t strerror(ret));\n\t\tgoto out;\n\t} else\n\t\tDEBUG(\"adapter port %u MTU set to %u\", priv->port, mtu);\n\tpriv->mtu = mtu;\n\t/* Temporarily replace RX handler with a fake one, assuming it has not\n\t * been copied elsewhere. */\n\tdev->rx_pkt_burst = removed_rx_burst;\n\t/* Make sure everyone has left mlx4_rx_burst() and uses\n\t * removed_rx_burst() instead. */\n\trte_wmb();\n\tusleep(1000);\n\t/* Reconfigure each RX queue. */\n\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n\t\tstruct rxq *rxq = (*priv->rxqs)[i];\n\t\tunsigned int max_frame_len;\n\t\tint sp;\n\n\t\tif (rxq == NULL)\n\t\t\tcontinue;\n\t\t/* Calculate new maximum frame length according to MTU and\n\t\t * toggle scattered support (sp) if necessary. */\n\t\tmax_frame_len = (priv->mtu + ETHER_HDR_LEN +\n\t\t\t\t (ETHER_MAX_VLAN_FRAME_LEN - ETHER_MAX_LEN));\n\t\tsp = (max_frame_len > (rxq->mb_len - RTE_PKTMBUF_HEADROOM));\n\t\t/* Provide new values to rxq_setup(). */\n\t\tdev->data->dev_conf.rxmode.jumbo_frame = sp;\n\t\tdev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame_len;\n\t\tret = rxq_rehash(dev, rxq);\n\t\tif (ret) {\n\t\t\t/* Force SP RX if that queue requires it and abort. */\n\t\t\tif (rxq->sp)\n\t\t\t\trx_func = mlx4_rx_burst_sp;\n\t\t\tbreak;\n\t\t}\n\t\t/* Reenable non-RSS queue attributes. No need to check\n\t\t * for errors at this stage. */\n\t\tif (!priv->rss) {\n\t\t\trxq_mac_addrs_add(rxq);\n\t\t\tif (priv->promisc)\n\t\t\t\trxq_promiscuous_enable(rxq);\n\t\t\tif (priv->allmulti)\n\t\t\t\trxq_allmulticast_enable(rxq);\n\t\t}\n\t\t/* Scattered burst function takes priority. */\n\t\tif (rxq->sp)\n\t\t\trx_func = mlx4_rx_burst_sp;\n\t}\n\t/* Burst functions can now be called again. */\n\trte_wmb();\n\tdev->rx_pkt_burst = rx_func;\nout:\n\tpriv_unlock(priv);\n\tassert(ret >= 0);\n\treturn -ret;\n}\n\n/**\n * DPDK callback to get flow control status.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param[out] fc_conf\n * Flow control output buffer.\n *\n * @return\n * 0 on success, negative errno value on failure.\n */\nstatic int\nmlx4_dev_get_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tstruct ifreq ifr;\n\tstruct ethtool_pauseparam ethpause = {\n\t\t.cmd = ETHTOOL_GPAUSEPARAM\n\t};\n\tint ret;\n\n\tifr.ifr_data = ðpause;\n\tpriv_lock(priv);\n\tif (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {\n\t\tret = errno;\n\t\tWARN(\"ioctl(SIOCETHTOOL, ETHTOOL_GPAUSEPARAM)\"\n\t\t \" failed: %s\",\n\t\t strerror(ret));\n\t\tgoto out;\n\t}\n\n\tfc_conf->autoneg = ethpause.autoneg;\n\tif (ethpause.rx_pause && ethpause.tx_pause)\n\t\tfc_conf->mode = RTE_FC_FULL;\n\telse if (ethpause.rx_pause)\n\t\tfc_conf->mode = RTE_FC_RX_PAUSE;\n\telse if (ethpause.tx_pause)\n\t\tfc_conf->mode = RTE_FC_TX_PAUSE;\n\telse\n\t\tfc_conf->mode = RTE_FC_NONE;\n\tret = 0;\n\nout:\n\tpriv_unlock(priv);\n\tassert(ret >= 0);\n\treturn -ret;\n}\n\n/**\n * DPDK callback to modify flow control parameters.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param[in] fc_conf\n * Flow control parameters.\n *\n * @return\n * 0 on success, negative errno value on failure.\n */\nstatic int\nmlx4_dev_set_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tstruct ifreq ifr;\n\tstruct ethtool_pauseparam ethpause = {\n\t\t.cmd = ETHTOOL_SPAUSEPARAM\n\t};\n\tint ret;\n\n\tifr.ifr_data = ðpause;\n\tethpause.autoneg = fc_conf->autoneg;\n\tif (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||\n\t (fc_conf->mode & RTE_FC_RX_PAUSE))\n\t\tethpause.rx_pause = 1;\n\telse\n\t\tethpause.rx_pause = 0;\n\n\tif (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||\n\t (fc_conf->mode & RTE_FC_TX_PAUSE))\n\t\tethpause.tx_pause = 1;\n\telse\n\t\tethpause.tx_pause = 0;\n\n\tpriv_lock(priv);\n\tif (priv_ifreq(priv, SIOCETHTOOL, &ifr)) {\n\t\tret = errno;\n\t\tWARN(\"ioctl(SIOCETHTOOL, ETHTOOL_SPAUSEPARAM)\"\n\t\t \" failed: %s\",\n\t\t strerror(ret));\n\t\tgoto out;\n\t}\n\tret = 0;\n\nout:\n\tpriv_unlock(priv);\n\tassert(ret >= 0);\n\treturn -ret;\n}\n\n/**\n * Configure a VLAN filter.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param vlan_id\n * VLAN ID to filter.\n * @param on\n * Toggle filter.\n *\n * @return\n * 0 on success, errno value on failure.\n */\nstatic int\nvlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tunsigned int i;\n\tunsigned int j = -1;\n\n\tDEBUG(\"%p: %s VLAN filter ID %\" PRIu16,\n\t (void *)dev, (on ? \"enable\" : \"disable\"), vlan_id);\n\tfor (i = 0; (i != elemof(priv->vlan_filter)); ++i) {\n\t\tif (!priv->vlan_filter[i].enabled) {\n\t\t\t/* Unused index, remember it. */\n\t\t\tj = i;\n\t\t\tcontinue;\n\t\t}\n\t\tif (priv->vlan_filter[i].id != vlan_id)\n\t\t\tcontinue;\n\t\t/* This VLAN ID is already known, use its index. */\n\t\tj = i;\n\t\tbreak;\n\t}\n\t/* Check if there's room for another VLAN filter. */\n\tif (j == (unsigned int)-1)\n\t\treturn ENOMEM;\n\t/*\n\t * VLAN filters apply to all configured MAC addresses, flow\n\t * specifications must be reconfigured accordingly.\n\t */\n\tpriv->vlan_filter[j].id = vlan_id;\n\tif ((on) && (!priv->vlan_filter[j].enabled)) {\n\t\t/*\n\t\t * Filter is disabled, enable it.\n\t\t * Rehashing flows in all RX queues is necessary.\n\t\t */\n\t\tif (priv->rss)\n\t\t\trxq_mac_addrs_del(&priv->rxq_parent);\n\t\telse\n\t\t\tfor (i = 0; (i != priv->rxqs_n); ++i)\n\t\t\t\tif ((*priv->rxqs)[i] != NULL)\n\t\t\t\t\trxq_mac_addrs_del((*priv->rxqs)[i]);\n\t\tpriv->vlan_filter[j].enabled = 1;\n\t\tif (priv->started) {\n\t\t\tif (priv->rss)\n\t\t\t\trxq_mac_addrs_add(&priv->rxq_parent);\n\t\t\telse\n\t\t\t\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n\t\t\t\t\tif ((*priv->rxqs)[i] == NULL)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\trxq_mac_addrs_add((*priv->rxqs)[i]);\n\t\t\t\t}\n\t\t}\n\t} else if ((!on) && (priv->vlan_filter[j].enabled)) {\n\t\t/*\n\t\t * Filter is enabled, disable it.\n\t\t * Rehashing flows in all RX queues is necessary.\n\t\t */\n\t\tif (priv->rss)\n\t\t\trxq_mac_addrs_del(&priv->rxq_parent);\n\t\telse\n\t\t\tfor (i = 0; (i != priv->rxqs_n); ++i)\n\t\t\t\tif ((*priv->rxqs)[i] != NULL)\n\t\t\t\t\trxq_mac_addrs_del((*priv->rxqs)[i]);\n\t\tpriv->vlan_filter[j].enabled = 0;\n\t\tif (priv->started) {\n\t\t\tif (priv->rss)\n\t\t\t\trxq_mac_addrs_add(&priv->rxq_parent);\n\t\t\telse\n\t\t\t\tfor (i = 0; (i != priv->rxqs_n); ++i) {\n\t\t\t\t\tif ((*priv->rxqs)[i] == NULL)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\trxq_mac_addrs_add((*priv->rxqs)[i]);\n\t\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\n/**\n * DPDK callback to configure a VLAN filter.\n *\n * @param dev\n * Pointer to Ethernet device structure.\n * @param vlan_id\n * VLAN ID to filter.\n * @param on\n * Toggle filter.\n *\n * @return\n * 0 on success, negative errno value on failure.\n */\nstatic int\nmlx4_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n{\n\tstruct priv *priv = dev->data->dev_private;\n\tint ret;\n\n\tpriv_lock(priv);\n\tret = vlan_filter_set(dev, vlan_id, on);\n\tpriv_unlock(priv);\n\tassert(ret >= 0);\n\treturn -ret;\n}\n\nstatic const struct eth_dev_ops mlx4_dev_ops = {\n\t.dev_configure = mlx4_dev_configure,\n\t.dev_start = mlx4_dev_start,\n\t.dev_stop = mlx4_dev_stop,\n\t.dev_close = mlx4_dev_close,\n\t.promiscuous_enable = mlx4_promiscuous_enable,\n\t.promiscuous_disable = mlx4_promiscuous_disable,\n\t.allmulticast_enable = mlx4_allmulticast_enable,\n\t.allmulticast_disable = mlx4_allmulticast_disable,\n\t.link_update = mlx4_link_update,\n\t.stats_get = mlx4_stats_get,\n\t.stats_reset = mlx4_stats_reset,\n\t.queue_stats_mapping_set = NULL,\n\t.dev_infos_get = mlx4_dev_infos_get,\n\t.vlan_filter_set = mlx4_vlan_filter_set,\n\t.vlan_tpid_set = NULL,\n\t.vlan_strip_queue_set = NULL,\n\t.vlan_offload_set = NULL,\n\t.rx_queue_setup = mlx4_rx_queue_setup,\n\t.tx_queue_setup = mlx4_tx_queue_setup,\n\t.rx_queue_release = mlx4_rx_queue_release,\n\t.tx_queue_release = mlx4_tx_queue_release,\n\t.dev_led_on = NULL,\n\t.dev_led_off = NULL,\n\t.flow_ctrl_get = mlx4_dev_get_flow_ctrl,\n\t.flow_ctrl_set = mlx4_dev_set_flow_ctrl,\n\t.priority_flow_ctrl_set = NULL,\n\t.mac_addr_remove = mlx4_mac_addr_remove,\n\t.mac_addr_add = mlx4_mac_addr_add,\n\t.mtu_set = mlx4_dev_set_mtu,\n\t.udp_tunnel_add = NULL,\n\t.udp_tunnel_del = NULL,\n\t.fdir_add_signature_filter = NULL,\n\t.fdir_update_signature_filter = NULL,\n\t.fdir_remove_signature_filter = NULL,\n\t.fdir_add_perfect_filter = NULL,\n\t.fdir_update_perfect_filter = NULL,\n\t.fdir_remove_perfect_filter = NULL,\n\t.fdir_set_masks = NULL\n};\n\n/**\n * Get PCI information from struct ibv_device.\n *\n * @param device\n * Pointer to Ethernet device structure.\n * @param[out] pci_addr\n * PCI bus address output buffer.\n *\n * @return\n * 0 on success, -1 on failure and errno is set.\n */\nstatic int\nmlx4_ibv_device_to_pci_addr(const struct ibv_device *device,\n\t\t\t struct rte_pci_addr *pci_addr)\n{\n\tFILE *file;\n\tchar line[32];\n\tMKSTR(path, \"%s/device/uevent\", device->ibdev_path);\n\n\tfile = fopen(path, \"rb\");\n\tif (file == NULL)\n\t\treturn -1;\n\twhile (fgets(line, sizeof(line), file) == line) {\n\t\tsize_t len = strlen(line);\n\t\tint ret;\n\n\t\t/* Truncate long lines. */\n\t\tif (len == (sizeof(line) - 1))\n\t\t\twhile (line[(len - 1)] != '\\n') {\n\t\t\t\tret = fgetc(file);\n\t\t\t\tif (ret == EOF)\n\t\t\t\t\tbreak;\n\t\t\t\tline[(len - 1)] = ret;\n\t\t\t}\n\t\t/* Extract information. */\n\t\tif (sscanf(line,\n\t\t\t \"PCI_SLOT_NAME=\"\n\t\t\t \"%\" SCNx16 \":%\" SCNx8 \":%\" SCNx8 \".%\" SCNx8 \"\\n\",\n\t\t\t &pci_addr->domain,\n\t\t\t &pci_addr->bus,\n\t\t\t &pci_addr->devid,\n\t\t\t &pci_addr->function) == 4) {\n\t\t\tret = 0;\n\t\t\tbreak;\n\t\t}\n\t}\n\tfclose(file);\n\treturn 0;\n}\n\n/**\n * Get MAC address by querying netdevice.\n *\n * @param[in] priv\n * struct priv for the requested device.\n * @param[out] mac\n * MAC address output buffer.\n *\n * @return\n * 0 on success, -1 on failure and errno is set.\n */\nstatic int\npriv_get_mac(struct priv *priv, uint8_t (*mac)[ETHER_ADDR_LEN])\n{\n\tstruct ifreq request;\n\n\tif (priv_ifreq(priv, SIOCGIFHWADDR, &request))\n\t\treturn -1;\n\tmemcpy(mac, request.ifr_hwaddr.sa_data, ETHER_ADDR_LEN);\n\treturn 0;\n}\n\n/* Support up to 32 adapters. */\nstatic struct {\n\tstruct rte_pci_addr pci_addr; /* associated PCI address */\n\tuint32_t ports; /* physical ports bitfield. */\n} mlx4_dev[32];\n\n/**\n * Get device index in mlx4_dev[] from PCI bus address.\n *\n * @param[in] pci_addr\n * PCI bus address to look for.\n *\n * @return\n * mlx4_dev[] index on success, -1 on failure.\n */\nstatic int\nmlx4_dev_idx(struct rte_pci_addr *pci_addr)\n{\n\tunsigned int i;\n\tint ret = -1;\n\n\tassert(pci_addr != NULL);\n\tfor (i = 0; (i != elemof(mlx4_dev)); ++i) {\n\t\tif ((mlx4_dev[i].pci_addr.domain == pci_addr->domain) &&\n\t\t (mlx4_dev[i].pci_addr.bus == pci_addr->bus) &&\n\t\t (mlx4_dev[i].pci_addr.devid == pci_addr->devid) &&\n\t\t (mlx4_dev[i].pci_addr.function == pci_addr->function))\n\t\t\treturn i;\n\t\tif ((mlx4_dev[i].ports == 0) && (ret == -1))\n\t\t\tret = i;\n\t}\n\treturn ret;\n}\n\n/**\n * Retrieve integer value from environment variable.\n *\n * @param[in] name\n * Environment variable name.\n *\n * @return\n * Integer value, 0 if the variable is not set.\n */\nstatic int\nmlx4_getenv_int(const char *name)\n{\n\tconst char *val = getenv(name);\n\n\tif (val == NULL)\n\t\treturn 0;\n\treturn atoi(val);\n}\n\nstatic struct eth_driver mlx4_driver;\n\n/**\n * DPDK callback to register a PCI device.\n *\n * This function creates an Ethernet device for each port of a given\n * PCI device.\n *\n * @param[in] pci_drv\n * PCI driver structure (mlx4_driver).\n * @param[in] pci_dev\n * PCI device information.\n *\n * @return\n * 0 on success, negative errno value on failure.\n */\nstatic int\nmlx4_pci_devinit(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n{\n\tstruct ibv_device **list;\n\tstruct ibv_device *ibv_dev;\n\tint err = 0;\n\tstruct ibv_context *attr_ctx = NULL;\n\tstruct ibv_device_attr device_attr;\n\tunsigned int vf;\n\tint idx;\n\tint i;\n\n\t(void)pci_drv;\n\tassert(pci_drv == &mlx4_driver.pci_drv);\n\t/* Get mlx4_dev[] index. */\n\tidx = mlx4_dev_idx(&pci_dev->addr);\n\tif (idx == -1) {\n\t\tERROR(\"this driver cannot support any more adapters\");\n\t\treturn -ENOMEM;\n\t}\n\tDEBUG(\"using driver device index %d\", idx);\n\n\t/* Save PCI address. */\n\tmlx4_dev[idx].pci_addr = pci_dev->addr;\n\tlist = ibv_get_device_list(&i);\n\tif (list == NULL) {\n\t\tassert(errno);\n\t\tif (errno == ENOSYS) {\n\t\t\tWARN(\"cannot list devices, is ib_uverbs loaded?\");\n\t\t\treturn 0;\n\t\t}\n\t\treturn -errno;\n\t}\n\tassert(i >= 0);\n\t/*\n\t * For each listed device, check related sysfs entry against\n\t * the provided PCI ID.\n\t */\n\twhile (i != 0) {\n\t\tstruct rte_pci_addr pci_addr;\n\n\t\t--i;\n\t\tDEBUG(\"checking device \\\"%s\\\"\", list[i]->name);\n\t\tif (mlx4_ibv_device_to_pci_addr(list[i], &pci_addr))\n\t\t\tcontinue;\n\t\tif ((pci_dev->addr.domain != pci_addr.domain) ||\n\t\t (pci_dev->addr.bus != pci_addr.bus) ||\n\t\t (pci_dev->addr.devid != pci_addr.devid) ||\n\t\t (pci_dev->addr.function != pci_addr.function))\n\t\t\tcontinue;\n\t\tvf = (pci_dev->id.device_id ==\n\t\t PCI_DEVICE_ID_MELLANOX_CONNECTX3VF);\n\t\tINFO(\"PCI information matches, using device \\\"%s\\\" (VF: %s)\",\n\t\t list[i]->name, (vf ? \"true\" : \"false\"));\n\t\tattr_ctx = ibv_open_device(list[i]);\n\t\terr = errno;\n\t\tbreak;\n\t}\n\tif (attr_ctx == NULL) {\n\t\tibv_free_device_list(list);\n\t\tswitch (err) {\n\t\tcase 0:\n\t\t\tWARN(\"cannot access device, is mlx4_ib loaded?\");\n\t\t\treturn 0;\n\t\tcase EINVAL:\n\t\t\tWARN(\"cannot use device, are drivers up to date?\");\n\t\t\treturn 0;\n\t\t}\n\t\tassert(err > 0);\n\t\treturn -err;\n\t}\n\tibv_dev = list[i];\n\n\tDEBUG(\"device opened\");\n\tif (ibv_query_device(attr_ctx, &device_attr))\n\t\tgoto error;\n\tINFO(\"%u port(s) detected\", device_attr.phys_port_cnt);\n\n\tfor (i = 0; i < device_attr.phys_port_cnt; i++) {\n\t\tuint32_t port = i + 1; /* ports are indexed from one */\n\t\tuint32_t test = (1 << i);\n\t\tstruct ibv_context *ctx = NULL;\n\t\tstruct ibv_port_attr port_attr;\n\t\tstruct ibv_pd *pd = NULL;\n\t\tstruct priv *priv = NULL;\n\t\tstruct rte_eth_dev *eth_dev;\n#ifdef HAVE_EXP_QUERY_DEVICE\n\t\tstruct ibv_exp_device_attr exp_device_attr;\n#endif /* HAVE_EXP_QUERY_DEVICE */\n\t\tstruct ether_addr mac;\n\n#ifdef HAVE_EXP_QUERY_DEVICE\n\t\texp_device_attr.comp_mask = IBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS;\n#ifdef RSS_SUPPORT\n\t\texp_device_attr.comp_mask |= IBV_EXP_DEVICE_ATTR_RSS_TBL_SZ;\n#endif /* RSS_SUPPORT */\n#endif /* HAVE_EXP_QUERY_DEVICE */\n\n\t\tDEBUG(\"using port %u (%08\" PRIx32 \")\", port, test);\n\n\t\tctx = ibv_open_device(ibv_dev);\n\t\tif (ctx == NULL)\n\t\t\tgoto port_error;\n\n\t\t/* Check port status. */\n\t\terr = ibv_query_port(ctx, port, &port_attr);\n\t\tif (err) {\n\t\t\tERROR(\"port query failed: %s\", strerror(err));\n\t\t\tgoto port_error;\n\t\t}\n\t\tif (port_attr.state != IBV_PORT_ACTIVE)\n\t\t\tWARN(\"bad state for port %d: \\\"%s\\\" (%d)\",\n\t\t\t port, ibv_port_state_str(port_attr.state),\n\t\t\t port_attr.state);\n\n\t\t/* Allocate protection domain. */\n\t\tpd = ibv_alloc_pd(ctx);\n\t\tif (pd == NULL) {\n\t\t\tERROR(\"PD allocation failure\");\n\t\t\terr = ENOMEM;\n\t\t\tgoto port_error;\n\t\t}\n\n\t\tmlx4_dev[idx].ports |= test;\n\n\t\t/* from rte_ethdev.c */\n\t\tpriv = rte_zmalloc(\"ethdev private structure\",\n\t\t\t\t sizeof(*priv),\n\t\t\t\t RTE_CACHE_LINE_SIZE);\n\t\tif (priv == NULL) {\n\t\t\tERROR(\"priv allocation failure\");\n\t\t\terr = ENOMEM;\n\t\t\tgoto port_error;\n\t\t}\n\n\t\tpriv->ctx = ctx;\n\t\tpriv->device_attr = device_attr;\n\t\tpriv->port = port;\n\t\tpriv->pd = pd;\n\t\tpriv->mtu = ETHER_MTU;\n#ifdef HAVE_EXP_QUERY_DEVICE\n\t\tif (ibv_exp_query_device(ctx, &exp_device_attr)) {\n\t\t\tERROR(\"ibv_exp_query_device() failed\");\n\t\t\tgoto port_error;\n\t\t}\n#ifdef RSS_SUPPORT\n\t\tif ((exp_device_attr.exp_device_cap_flags &\n\t\t IBV_EXP_DEVICE_QPG) &&\n\t\t (exp_device_attr.exp_device_cap_flags &\n\t\t IBV_EXP_DEVICE_UD_RSS) &&\n\t\t (exp_device_attr.comp_mask &\n\t\t IBV_EXP_DEVICE_ATTR_RSS_TBL_SZ) &&\n\t\t (exp_device_attr.max_rss_tbl_sz > 0)) {\n\t\t\tpriv->hw_qpg = 1;\n\t\t\tpriv->hw_rss = 1;\n\t\t\tpriv->max_rss_tbl_sz = exp_device_attr.max_rss_tbl_sz;\n\t\t} else {\n\t\t\tpriv->hw_qpg = 0;\n\t\t\tpriv->hw_rss = 0;\n\t\t\tpriv->max_rss_tbl_sz = 0;\n\t\t}\n\t\tpriv->hw_tss = !!(exp_device_attr.exp_device_cap_flags &\n\t\t\t\t IBV_EXP_DEVICE_UD_TSS);\n\t\tDEBUG(\"device flags: %s%s%s\",\n\t\t (priv->hw_qpg ? \"IBV_DEVICE_QPG \" : \"\"),\n\t\t (priv->hw_tss ? \"IBV_DEVICE_TSS \" : \"\"),\n\t\t (priv->hw_rss ? \"IBV_DEVICE_RSS \" : \"\"));\n\t\tif (priv->hw_rss)\n\t\t\tDEBUG(\"maximum RSS indirection table size: %u\",\n\t\t\t exp_device_attr.max_rss_tbl_sz);\n#endif /* RSS_SUPPORT */\n\n\t\tpriv->hw_csum =\n\t\t\t((exp_device_attr.exp_device_cap_flags &\n\t\t\t IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) &&\n\t\t\t (exp_device_attr.exp_device_cap_flags &\n\t\t\t IBV_EXP_DEVICE_RX_CSUM_IP_PKT));\n\t\tDEBUG(\"checksum offloading is %ssupported\",\n\t\t (priv->hw_csum ? \"\" : \"not \"));\n\n\t\tpriv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &\n\t\t\t\t\t IBV_EXP_DEVICE_VXLAN_SUPPORT);\n\t\tDEBUG(\"L2 tunnel checksum offloads are %ssupported\",\n\t\t (priv->hw_csum_l2tun ? \"\" : \"not \"));\n\n#ifdef INLINE_RECV\n\t\tpriv->inl_recv_size = mlx4_getenv_int(\"MLX4_INLINE_RECV_SIZE\");\n\n\t\tif (priv->inl_recv_size) {\n\t\t\texp_device_attr.comp_mask =\n\t\t\t\tIBV_EXP_DEVICE_ATTR_INLINE_RECV_SZ;\n\t\t\tif (ibv_exp_query_device(ctx, &exp_device_attr)) {\n\t\t\t\tINFO(\"Couldn't query device for inline-receive\"\n\t\t\t\t \" capabilities.\");\n\t\t\t\tpriv->inl_recv_size = 0;\n\t\t\t} else {\n\t\t\t\tif ((unsigned)exp_device_attr.inline_recv_sz <\n\t\t\t\t priv->inl_recv_size) {\n\t\t\t\t\tINFO(\"Max inline-receive (%d) <\"\n\t\t\t\t\t \" requested inline-receive (%u)\",\n\t\t\t\t\t exp_device_attr.inline_recv_sz,\n\t\t\t\t\t priv->inl_recv_size);\n\t\t\t\t\tpriv->inl_recv_size =\n\t\t\t\t\t\texp_device_attr.inline_recv_sz;\n\t\t\t\t}\n\t\t\t}\n\t\t\tINFO(\"Set inline receive size to %u\",\n\t\t\t priv->inl_recv_size);\n\t\t}\n#endif /* INLINE_RECV */\n#endif /* HAVE_EXP_QUERY_DEVICE */\n\n\t\t(void)mlx4_getenv_int;\n\t\tpriv->vf = vf;\n\t\t/* Configure the first MAC address by default. */\n\t\tif (priv_get_mac(priv, &mac.addr_bytes)) {\n\t\t\tERROR(\"cannot get MAC address, is mlx4_en loaded?\"\n\t\t\t \" (errno: %s)\", strerror(errno));\n\t\t\tgoto port_error;\n\t\t}\n\t\tINFO(\"port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x\",\n\t\t priv->port,\n\t\t mac.addr_bytes[0], mac.addr_bytes[1],\n\t\t mac.addr_bytes[2], mac.addr_bytes[3],\n\t\t mac.addr_bytes[4], mac.addr_bytes[5]);\n\t\t/* Register MAC and broadcast addresses. */\n\t\tclaim_zero(priv_mac_addr_add(priv, 0,\n\t\t\t\t\t (const uint8_t (*)[ETHER_ADDR_LEN])\n\t\t\t\t\t mac.addr_bytes));\n\t\tclaim_zero(priv_mac_addr_add(priv, 1,\n\t\t\t\t\t &(const uint8_t [ETHER_ADDR_LEN])\n\t\t\t\t\t { \"\\xff\\xff\\xff\\xff\\xff\\xff\" }));\n#ifndef NDEBUG\n\t\t{\n\t\t\tchar ifname[IF_NAMESIZE];\n\n\t\t\tif (priv_get_ifname(priv, &ifname) == 0)\n\t\t\t\tDEBUG(\"port %u ifname is \\\"%s\\\"\",\n\t\t\t\t priv->port, ifname);\n\t\t\telse\n\t\t\t\tDEBUG(\"port %u ifname is unknown\", priv->port);\n\t\t}\n#endif\n\t\t/* Get actual MTU if possible. */\n\t\tpriv_get_mtu(priv, &priv->mtu);\n\t\tDEBUG(\"port %u MTU is %u\", priv->port, priv->mtu);\n\n\t\t/* from rte_ethdev.c */\n\t\t{\n\t\t\tchar name[RTE_ETH_NAME_MAX_LEN];\n\n\t\t\tsnprintf(name, sizeof(name), \"%s port %u\",\n\t\t\t\t ibv_get_device_name(ibv_dev), port);\n\t\t\teth_dev = rte_eth_dev_allocate(name, RTE_ETH_DEV_PCI);\n\t\t}\n\t\tif (eth_dev == NULL) {\n\t\t\tERROR(\"can not allocate rte ethdev\");\n\t\t\terr = ENOMEM;\n\t\t\tgoto port_error;\n\t\t}\n\n\t\teth_dev->data->dev_private = priv;\n\t\teth_dev->pci_dev = pci_dev;\n\t\teth_dev->driver = &mlx4_driver;\n\t\teth_dev->data->rx_mbuf_alloc_failed = 0;\n\t\teth_dev->data->mtu = ETHER_MTU;\n\n\t\tpriv->dev = eth_dev;\n\t\teth_dev->dev_ops = &mlx4_dev_ops;\n\t\teth_dev->data->mac_addrs = priv->mac;\n\n\t\t/* Bring Ethernet device up. */\n\t\tDEBUG(\"forcing Ethernet interface up\");\n\t\tpriv_set_flags(priv, ~IFF_UP, IFF_UP);\n\t\tcontinue;\n\nport_error:\n\t\trte_free(priv);\n\t\tif (pd)\n\t\t\tclaim_zero(ibv_dealloc_pd(pd));\n\t\tif (ctx)\n\t\t\tclaim_zero(ibv_close_device(ctx));\n\t\tbreak;\n\t}\n\n\t/*\n\t * XXX if something went wrong in the loop above, there is a resource\n\t * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as\n\t * long as the dpdk does not provide a way to deallocate a ethdev and a\n\t * way to enumerate the registered ethdevs to free the previous ones.\n\t */\n\n\t/* no port found, complain */\n\tif (!mlx4_dev[idx].ports) {\n\t\terr = ENODEV;\n\t\tgoto error;\n\t}\n\nerror:\n\tif (attr_ctx)\n\t\tclaim_zero(ibv_close_device(attr_ctx));\n\tif (list)\n\t\tibv_free_device_list(list);\n\tassert(err >= 0);\n\treturn -err;\n}\n\nstatic const struct rte_pci_id mlx4_pci_id_map[] = {\n\t{\n\t\t.vendor_id = PCI_VENDOR_ID_MELLANOX,\n\t\t.device_id = PCI_DEVICE_ID_MELLANOX_CONNECTX3,\n\t\t.subsystem_vendor_id = PCI_ANY_ID,\n\t\t.subsystem_device_id = PCI_ANY_ID\n\t},\n\t{\n\t\t.vendor_id = PCI_VENDOR_ID_MELLANOX,\n\t\t.device_id = PCI_DEVICE_ID_MELLANOX_CONNECTX3PRO,\n\t\t.subsystem_vendor_id = PCI_ANY_ID,\n\t\t.subsystem_device_id = PCI_ANY_ID\n\t},\n\t{\n\t\t.vendor_id = PCI_VENDOR_ID_MELLANOX,\n\t\t.device_id = PCI_DEVICE_ID_MELLANOX_CONNECTX3VF,\n\t\t.subsystem_vendor_id = PCI_ANY_ID,\n\t\t.subsystem_device_id = PCI_ANY_ID\n\t},\n\t{\n\t\t.vendor_id = 0\n\t}\n};\n\nstatic struct eth_driver mlx4_driver = {\n\t.pci_drv = {\n\t\t.name = MLX4_DRIVER_NAME,\n\t\t.id_table = mlx4_pci_id_map,\n\t\t.devinit = mlx4_pci_devinit,\n\t},\n\t.dev_private_size = sizeof(struct priv)\n};\n\n/**\n * Driver initialization routine.\n */\nstatic int\nrte_mlx4_pmd_init(const char *name, const char *args)\n{\n\t(void)name;\n\t(void)args;\n\t/*\n\t * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use\n\t * huge pages. Calling ibv_fork_init() during init allows\n\t * applications to use fork() safely for purposes other than\n\t * using this PMD, which is not supported in forked processes.\n\t */\n\tsetenv(\"RDMAV_HUGEPAGES_SAFE\", \"1\", 1);\n\tibv_fork_init();\n\trte_eal_pci_register(&mlx4_driver.pci_drv);\n\treturn 0;\n}\n\nstatic struct rte_driver rte_mlx4_driver = {\n\t.type = PMD_PDEV,\n\t.name = MLX4_DRIVER_NAME,\n\t.init = rte_mlx4_pmd_init,\n};\n\nPMD_REGISTER_DRIVER(rte_mlx4_driver)\n" }, { "path": "drivers/net/mlx4/mlx4.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright 2012-2015 6WIND S.A.\n * Copyright 2012 Mellanox.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef RTE_PMD_MLX4_H_\n#define RTE_PMD_MLX4_H_\n\n#include \n#include \n#include \n\n/*\n * Maximum number of simultaneous MAC addresses supported.\n *\n * According to ConnectX's Programmer Reference Manual:\n * The L2 Address Match is implemented by comparing a MAC/VLAN combination\n * of 128 MAC addresses and 127 VLAN values, comprising 128x127 possible\n * L2 addresses.\n */\n#define MLX4_MAX_MAC_ADDRESSES 128\n\n/* Maximum number of simultaneous VLAN filters supported. See above. */\n#define MLX4_MAX_VLAN_IDS 127\n\n/* Request send completion once in every 64 sends, might be less. */\n#define MLX4_PMD_TX_PER_COMP_REQ 64\n\n/* Maximum number of Scatter/Gather Elements per Work Request. */\n#ifndef MLX4_PMD_SGE_WR_N\n#define MLX4_PMD_SGE_WR_N 4\n#endif\n\n/* Maximum size for inline data. */\n#ifndef MLX4_PMD_MAX_INLINE\n#define MLX4_PMD_MAX_INLINE 0\n#endif\n\n/*\n * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP\n * from which buffers are to be transmitted will have to be mapped by this\n * driver to their own Memory Region (MR). This is a slow operation.\n *\n * This value is always 1 for RX queues.\n */\n#ifndef MLX4_PMD_TX_MP_CACHE\n#define MLX4_PMD_TX_MP_CACHE 8\n#endif\n\n/*\n * If defined, only use software counters. The PMD will never ask the hardware\n * for these, and many of them won't be available.\n */\n#ifndef MLX4_PMD_SOFT_COUNTERS\n#define MLX4_PMD_SOFT_COUNTERS 1\n#endif\n\nenum {\n\tPCI_VENDOR_ID_MELLANOX = 0x15b3,\n};\n\nenum {\n\tPCI_DEVICE_ID_MELLANOX_CONNECTX3 = 0x1003,\n\tPCI_DEVICE_ID_MELLANOX_CONNECTX3VF = 0x1004,\n\tPCI_DEVICE_ID_MELLANOX_CONNECTX3PRO = 0x1007,\n};\n\n#define MLX4_DRIVER_NAME \"librte_pmd_mlx4\"\n\n/* Bit-field manipulation. */\n#define BITFIELD_DECLARE(bf, type, size)\t\t\t\t\\\n\ttype bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) +\t\t\\\n\t\t !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))]\n#define BITFIELD_DEFINE(bf, type, size)\t\t\t\t\t\\\n\tBITFIELD_DECLARE((bf), type, (size)) = { 0 }\n#define BITFIELD_SET(bf, b)\t\t\t\t\t\t\\\n\t(assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)),\t\t\t\\\n\t (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |=\t\t\\\n\t\t((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))\n#define BITFIELD_RESET(bf, b)\t\t\t\t\t\t\\\n\t(assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)),\t\t\t\\\n\t (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &=\t\t\\\n\t\t~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))\n#define BITFIELD_ISSET(bf, b)\t\t\t\t\t\t\\\n\t(assert((size_t)(b) < (sizeof(bf) * CHAR_BIT)),\t\t\t\\\n\t !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &\t\t\\\n\t ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))))\n\n/* Number of elements in array. */\n#define elemof(a) (sizeof(a) / sizeof((a)[0]))\n\n/* Cast pointer p to structure member m to its parent structure of type t. */\n#define containerof(p, t, m) ((t *)((uint8_t *)(p) - offsetof(t, m)))\n\n/* Branch prediction helpers. */\n#ifndef likely\n#define likely(c) __builtin_expect(!!(c), 1)\n#endif\n#ifndef unlikely\n#define unlikely(c) __builtin_expect(!!(c), 0)\n#endif\n\n/* Debugging */\n#ifndef NDEBUG\n#include \n#define DEBUG__(m, ...)\t\t\t\t\t\t\\\n\t(fprintf(stderr, \"%s:%d: %s(): \" m \"%c\",\t\t\\\n\t\t __FILE__, __LINE__, __func__, __VA_ARGS__),\t\\\n\t fflush(stderr),\t\t\t\t\t\\\n\t (void)0)\n/*\n * Save/restore errno around DEBUG__().\n * XXX somewhat undefined behavior, but works.\n */\n#define DEBUG_(...)\t\t\t\t\\\n\t(errno = ((int []){\t\t\t\\\n\t\t*(volatile int *)&errno,\t\\\n\t\t(DEBUG__(__VA_ARGS__), 0)\t\\\n\t})[0])\n#define DEBUG(...) DEBUG_(__VA_ARGS__, '\\n')\n#define claim_zero(...) assert((__VA_ARGS__) == 0)\n#define claim_nonzero(...) assert((__VA_ARGS__) != 0)\n#define claim_positive(...) assert((__VA_ARGS__) >= 0)\n#else /* NDEBUG */\n/* No-ops. */\n#define DEBUG(...) (void)0\n#define claim_zero(...) (__VA_ARGS__)\n#define claim_nonzero(...) (__VA_ARGS__)\n#define claim_positive(...) (__VA_ARGS__)\n#endif /* NDEBUG */\n\n#endif /* RTE_PMD_MLX4_H_ */\n" }, { "path": "drivers/net/mpipe/Makefile", "content": "#\n# Copyright 2015 EZchip Semiconductor Ltd. All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# 1. Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n#\n# 2. Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n# COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,\n# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN\n# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n# POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_pmd_mpipe.a\n\nCFLAGS += $(WERROR_FLAGS) -O3\n\nEXPORT_MAP := rte_pmd_mpipe_version.map\n\nLIBABIVER := 1\n\nSRCS-$(CONFIG_RTE_LIBRTE_MPIPE_PMD) += mpipe_tilegx.c\n\nDEPDIRS-$(CONFIG_RTE_LIBRTE_MPIPE_PMD) += lib/librte_eal lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_MPIPE_PMD) += lib/librte_mempool lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_MPIPE_PMD) += lib/librte_net lib/librte_malloc\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/mpipe/mpipe_tilegx.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 EZchip Semiconductor Ltd. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of EZchip Semiconductor nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n\n#ifdef RTE_LIBRTE_MPIPE_PMD_DEBUG\n#define PMD_DEBUG_RX(...)\tRTE_LOG(DEBUG, PMD, __VA_ARGS__)\n#define PMD_DEBUG_TX(...)\tRTE_LOG(DEBUG, PMD, __VA_ARGS__)\n#else\n#define PMD_DEBUG_RX(...)\n#define PMD_DEBUG_TX(...)\n#endif\n\n#define MPIPE_MAX_CHANNELS\t\t128\n#define MPIPE_TX_MAX_QUEUES\t\t128\n#define MPIPE_RX_MAX_QUEUES\t\t16\n#define MPIPE_TX_DESCS\t\t\t512\n#define MPIPE_RX_BUCKETS\t\t256\n#define MPIPE_RX_STACK_SIZE\t\t65536\n#define MPIPE_RX_IP_ALIGN\t\t2\n#define MPIPE_BSM_ALIGN\t\t\t128\n\n#define MPIPE_LINK_UPDATE_TIMEOUT\t10\t/* s */\n#define MPIPE_LINK_UPDATE_INTERVAL\t100000\t/* us */\n\nstruct mpipe_channel_config {\n\tint enable;\n\tint first_bucket;\n\tint num_buckets;\n\tint head_room;\n\tgxio_mpipe_rules_stacks_t stacks;\n};\n\nstruct mpipe_context {\n\trte_spinlock_t lock;\n\tgxio_mpipe_context_t context;\n\tstruct mpipe_channel_config channels[MPIPE_MAX_CHANNELS];\n};\n\nstatic struct mpipe_context mpipe_contexts[GXIO_MPIPE_INSTANCE_MAX];\nstatic int mpipe_instances;\n\n/* Per queue statistics. */\nstruct mpipe_queue_stats {\n\tuint64_t packets, bytes, errors, nomem;\n};\n\n/* Common tx/rx queue fields. */\nstruct mpipe_queue {\n\tstruct mpipe_dev_priv *priv;\t/* \"priv\" data of its device. */\n\tuint16_t nb_desc;\t\t/* Number of tx descriptors. */\n\tuint16_t port_id;\t\t/* Device index. */\n\tuint16_t stat_idx;\t\t/* Queue stats index. */\n\tuint8_t queue_idx;\t\t/* Queue index. */\n\tuint8_t link_status;\t\t/* 0 = link down. */\n\tstruct mpipe_queue_stats stats;\t/* Stat data for the queue. */\n};\n\n/* Transmit queue description. */\nstruct mpipe_tx_queue {\n\tstruct mpipe_queue q;\t\t/* Common stuff. */\n};\n\n/* Receive queue description. */\nstruct mpipe_rx_queue {\n\tstruct mpipe_queue q;\t\t/* Common stuff. */\n\tgxio_mpipe_iqueue_t iqueue;\t/* mPIPE iqueue. */\n\tgxio_mpipe_idesc_t *next_desc;\t/* Next idesc to process. */\n\tint avail_descs;\t\t/* Number of available descs. */\n\tvoid *rx_ring_mem;\t\t/* DMA ring memory. */\n};\n\nstruct mpipe_dev_priv {\n\tgxio_mpipe_context_t *context;\t/* mPIPE context. */\n\tgxio_mpipe_link_t link;\t\t/* mPIPE link for the device. */\n\tgxio_mpipe_equeue_t equeue;\t/* mPIPE equeue. */\n\tunsigned equeue_size;\t\t/* mPIPE equeue desc count. */\n\tint instance;\t\t\t/* mPIPE instance. */\n\tint ering;\t\t\t/* mPIPE eDMA ring. */\n\tint stack;\t\t\t/* mPIPE buffer stack. */\n\tint channel;\t\t\t/* Device channel. */\n\tint port_id;\t\t\t/* DPDK port index. */\n\tstruct rte_eth_dev *eth_dev;\t/* DPDK device. */\n\tstruct rte_pci_device pci_dev;\t/* PCI device data. */\n\tstruct rte_mbuf **tx_comps;\t/* TX completion array. */\n\tstruct rte_mempool *rx_mpool;\t/* mpool used by the rx queues. */\n\tunsigned rx_offset;\t\t/* Receive head room. */\n\tunsigned rx_size_code;\t\t/* mPIPE rx buffer size code. */\n\tunsigned rx_buffers;\t\t/* receive buffers on stack. */\n\tint is_xaui:1,\t\t\t/* Is this an xgbe or gbe? */\n\t initialized:1,\t\t/* Initialized port? */\n\t running:1;\t\t\t/* Running port? */\n\tstruct ether_addr mac_addr;\t/* MAC address. */\n\tunsigned nb_rx_queues;\t\t/* Configured tx queues. */\n\tunsigned nb_tx_queues;\t\t/* Configured rx queues. */\n\tint first_bucket;\t\t/* mPIPE bucket start index. */\n\tint first_ring;\t\t\t/* mPIPE notif ring start index. */\n\tint notif_group;\t\t/* mPIPE notif group. */\n\trte_atomic32_t dp_count;\t/* Active datapath thread count. */\n\tint tx_stat_mapping[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n\tint rx_stat_mapping[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n};\n\n#define mpipe_priv(dev)\t\t\t\\\n\t((struct mpipe_dev_priv*)(dev)->data->dev_private)\n\n#define mpipe_name(priv)\t\t\\\n\t((priv)->eth_dev->data->name)\n\n#define mpipe_rx_queue(priv, n)\t\t\\\n\t((struct mpipe_rx_queue *)(priv)->eth_dev->data->rx_queues[n])\n\n#define mpipe_tx_queue(priv, n)\t\t\\\n\t((struct mpipe_tx_queue *)(priv)->eth_dev->data->tx_queues[n])\n\nstatic void\nmpipe_xmit_flush(struct mpipe_dev_priv *priv);\n\nstatic void\nmpipe_recv_flush(struct mpipe_dev_priv *priv);\n\nstatic int mpipe_equeue_sizes[] = {\n\t[GXIO_MPIPE_EQUEUE_ENTRY_512]\t= 512,\n\t[GXIO_MPIPE_EQUEUE_ENTRY_2K]\t= 2048,\n\t[GXIO_MPIPE_EQUEUE_ENTRY_8K]\t= 8192,\n\t[GXIO_MPIPE_EQUEUE_ENTRY_64K]\t= 65536,\n};\n\nstatic int mpipe_iqueue_sizes[] = {\n\t[GXIO_MPIPE_IQUEUE_ENTRY_128]\t= 128,\n\t[GXIO_MPIPE_IQUEUE_ENTRY_512]\t= 512,\n\t[GXIO_MPIPE_IQUEUE_ENTRY_2K]\t= 2048,\n\t[GXIO_MPIPE_IQUEUE_ENTRY_64K]\t= 65536,\n};\n\nstatic int mpipe_buffer_sizes[] = {\n\t[GXIO_MPIPE_BUFFER_SIZE_128]\t= 128,\n\t[GXIO_MPIPE_BUFFER_SIZE_256]\t= 256,\n\t[GXIO_MPIPE_BUFFER_SIZE_512]\t= 512,\n\t[GXIO_MPIPE_BUFFER_SIZE_1024]\t= 1024,\n\t[GXIO_MPIPE_BUFFER_SIZE_1664]\t= 1664,\n\t[GXIO_MPIPE_BUFFER_SIZE_4096]\t= 4096,\n\t[GXIO_MPIPE_BUFFER_SIZE_10368]\t= 10368,\n\t[GXIO_MPIPE_BUFFER_SIZE_16384]\t= 16384,\n};\n\nstatic gxio_mpipe_context_t *\nmpipe_context(int instance)\n{\n\tif (instance < 0 || instance >= mpipe_instances)\n\t\treturn NULL;\n\treturn &mpipe_contexts[instance].context;\n}\n\nstatic int mpipe_channel_config(int instance, int channel,\n\t\t\t\tstruct mpipe_channel_config *config)\n{\n\tstruct mpipe_channel_config *data;\n\tstruct mpipe_context *context;\n\tgxio_mpipe_rules_t rules;\n\tint idx, rc = 0;\n\n\tif (instance < 0 || instance >= mpipe_instances ||\n\t channel < 0 || channel >= MPIPE_MAX_CHANNELS)\n\t\treturn -EINVAL;\n\n\tcontext = &mpipe_contexts[instance];\n\n\trte_spinlock_lock(&context->lock);\n\n\tgxio_mpipe_rules_init(&rules, &context->context);\n\n\tfor (idx = 0; idx < MPIPE_MAX_CHANNELS; idx++) {\n\t\tdata = (channel == idx) ? config : &context->channels[idx];\n\n\t\tif (!data->enable)\n\t\t\tcontinue;\n\n\t\trc = gxio_mpipe_rules_begin(&rules, data->first_bucket,\n\t\t\t\t\t data->num_buckets, &data->stacks);\n\t\tif (rc < 0) {\n\t\t\tgoto done;\n\t\t}\n\n\t\trc = gxio_mpipe_rules_add_channel(&rules, idx);\n\t\tif (rc < 0) {\n\t\t\tgoto done;\n\t\t}\n\n\t\trc = gxio_mpipe_rules_set_headroom(&rules, data->head_room);\n\t\tif (rc < 0) {\n\t\t\tgoto done;\n\t\t}\n\t}\n\n\trc = gxio_mpipe_rules_commit(&rules);\n\tif (rc == 0) {\n\t\tmemcpy(&context->channels[channel], config, sizeof(*config));\n\t}\n\ndone:\n\trte_spinlock_unlock(&context->lock);\n\n\treturn rc;\n}\n\nstatic int\nmpipe_get_size_index(int *array, int count, int size,\n\t\t bool roundup)\n{\n\tint i, last = -1;\n\n\tfor (i = 0; i < count && array[i] < size; i++) {\n\t\tif (array[i])\n\t\t\tlast = i;\n\t}\n\n\tif (roundup)\n\t\treturn i < count ? (int)i : -ENOENT;\n\telse\n\t\treturn last >= 0 ? last : -ENOENT;\n}\n\nstatic int\nmpipe_calc_size(int *array, int count, int size)\n{\n\tint index = mpipe_get_size_index(array, count, size, 1);\n\treturn index < 0 ? index : array[index];\n}\n\nstatic int mpipe_equeue_size(int size)\n{\n\tint result;\n\tresult = mpipe_calc_size(mpipe_equeue_sizes,\n\t\t\t\t RTE_DIM(mpipe_equeue_sizes), size);\n\treturn result;\n}\n\nstatic int mpipe_iqueue_size(int size)\n{\n\tint result;\n\tresult = mpipe_calc_size(mpipe_iqueue_sizes,\n\t\t\t\t RTE_DIM(mpipe_iqueue_sizes), size);\n\treturn result;\n}\n\nstatic int mpipe_buffer_size_index(int size)\n{\n\tint result;\n\tresult = mpipe_get_size_index(mpipe_buffer_sizes,\n\t\t\t\t RTE_DIM(mpipe_buffer_sizes), size, 0);\n\treturn result;\n}\n\nstatic inline int\nmpipe_dev_atomic_read_link_status(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = link;\n\tstruct rte_eth_link *src = &(dev->data->dev_link);\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic inline int\nmpipe_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = &(dev->data->dev_link);\n\tstruct rte_eth_link *src = link;\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic void\nmpipe_infos_get(struct rte_eth_dev *dev __rte_unused,\n\t\tstruct rte_eth_dev_info *dev_info)\n{\n\tdev_info->min_rx_bufsize = 128;\n\tdev_info->max_rx_pktlen = 1518;\n\tdev_info->max_tx_queues = MPIPE_TX_MAX_QUEUES;\n\tdev_info->max_rx_queues = MPIPE_RX_MAX_QUEUES;\n\tdev_info->max_mac_addrs = 1;\n\tdev_info->rx_offload_capa = 0;\n\tdev_info->tx_offload_capa = 0;\n}\n\nstatic int\nmpipe_configure(struct rte_eth_dev *dev)\n{\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\n\tif (dev->data->nb_tx_queues > MPIPE_TX_MAX_QUEUES) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Too many tx queues: %d > %d\\n\",\n\t\t\tmpipe_name(priv), dev->data->nb_tx_queues,\n\t\t\tMPIPE_TX_MAX_QUEUES);\n\t\treturn -EINVAL;\n\t}\n\tpriv->nb_tx_queues = dev->data->nb_tx_queues;\n\n\tif (dev->data->nb_rx_queues > MPIPE_RX_MAX_QUEUES) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Too many rx queues: %d > %d\\n\",\n\t\t\tmpipe_name(priv), dev->data->nb_rx_queues,\n\t\t\tMPIPE_RX_MAX_QUEUES);\n\t}\n\tpriv->nb_rx_queues = dev->data->nb_rx_queues;\n\n\treturn 0;\n}\n\nstatic inline int\nmpipe_link_compare(struct rte_eth_link *link1,\n\t\t struct rte_eth_link *link2)\n{\n\treturn ((*(uint64_t *)link1 == *(uint64_t *)link2)\n\t\t? -1 : 0);\n}\n\nstatic int\nmpipe_link_update(struct rte_eth_dev *dev, int wait_to_complete)\n{\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\tstruct rte_eth_link old, new;\n\tint64_t state, speed;\n\tint count, rc;\n\n\tmemset(&old, 0, sizeof(old));\n\tmemset(&new, 0, sizeof(new));\n\tmpipe_dev_atomic_read_link_status(dev, &old);\n\n\tfor (count = 0, rc = 0; count < MPIPE_LINK_UPDATE_TIMEOUT; count++) {\n\t\tif (!priv->initialized)\n\t\t\tbreak;\n\n\t\tstate = gxio_mpipe_link_get_attr(&priv->link,\n\t\t\t\t\t\t GXIO_MPIPE_LINK_CURRENT_STATE);\n\t\tif (state < 0)\n\t\t\tbreak;\n\n\t\tspeed = state & GXIO_MPIPE_LINK_SPEED_MASK;\n\n\t\tif (speed == GXIO_MPIPE_LINK_1G) {\n\t\t\tnew.link_speed = ETH_LINK_SPEED_1000;\n\t\t\tnew.link_duplex = ETH_LINK_FULL_DUPLEX;\n\t\t\tnew.link_status = 1;\n\t\t} else if (speed == GXIO_MPIPE_LINK_10G) {\n\t\t\tnew.link_speed = ETH_LINK_SPEED_10000;\n\t\t\tnew.link_duplex = ETH_LINK_FULL_DUPLEX;\n\t\t\tnew.link_status = 1;\n\t\t}\n\n\t\trc = mpipe_link_compare(&old, &new);\n\t\tif (rc == 0 || !wait_to_complete)\n\t\t\tbreak;\n\n\t\trte_delay_us(MPIPE_LINK_UPDATE_INTERVAL);\n\t}\n\n\tmpipe_dev_atomic_write_link_status(dev, &new);\n\treturn rc;\n}\n\nstatic int\nmpipe_set_link(struct rte_eth_dev *dev, int up)\n{\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\tint rc;\n\n\trc = gxio_mpipe_link_set_attr(&priv->link,\n\t\t\t\t GXIO_MPIPE_LINK_DESIRED_STATE,\n\t\t\t\t up ? GXIO_MPIPE_LINK_ANYSPEED : 0);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to set link %s.\\n\",\n\t\t\tmpipe_name(priv), up ? \"up\" : \"down\");\n\t} else {\n\t\tmpipe_link_update(dev, 0);\n\t}\n\n\treturn rc;\n}\n\nstatic int\nmpipe_set_link_up(struct rte_eth_dev *dev)\n{\n\treturn mpipe_set_link(dev, 1);\n}\n\nstatic int\nmpipe_set_link_down(struct rte_eth_dev *dev)\n{\n\treturn mpipe_set_link(dev, 0);\n}\n\nstatic inline void\nmpipe_dp_enter(struct mpipe_dev_priv *priv)\n{\n\t__insn_mtspr(SPR_DSTREAM_PF, 0);\n\trte_atomic32_inc(&priv->dp_count);\n}\n\nstatic inline void\nmpipe_dp_exit(struct mpipe_dev_priv *priv)\n{\n\trte_atomic32_dec(&priv->dp_count);\n}\n\nstatic inline void\nmpipe_dp_wait(struct mpipe_dev_priv *priv)\n{\n\twhile (rte_atomic32_read(&priv->dp_count) != 0) {\n\t\trte_pause();\n\t}\n}\n\nstatic inline struct rte_mbuf *\nmpipe_recv_mbuf(struct mpipe_dev_priv *priv, gxio_mpipe_idesc_t *idesc,\n\t\tint in_port)\n{\n\tvoid *va = gxio_mpipe_idesc_get_va(idesc);\n\tuint16_t size = gxio_mpipe_idesc_get_xfer_size(idesc);\n\tstruct rte_mbuf *mbuf = RTE_PTR_SUB(va, priv->rx_offset);\n\n\trte_pktmbuf_reset(mbuf);\n\tmbuf->data_off = (uintptr_t)va - (uintptr_t)mbuf->buf_addr;\n\tmbuf->port = in_port;\n\tmbuf->data_len = size;\n\tmbuf->pkt_len = size;\n\tmbuf->hash.rss = gxio_mpipe_idesc_get_flow_hash(idesc);\n\n\tPMD_DEBUG_RX(\"%s: RX mbuf %p, buffer %p, buf_addr %p, size %d\\n\",\n\t\t mpipe_name(priv), mbuf, va, mbuf->buf_addr, size);\n\n\treturn mbuf;\n}\n\nstatic inline void\nmpipe_recv_push(struct mpipe_dev_priv *priv, struct rte_mbuf *mbuf)\n{\n\tconst int offset = RTE_PKTMBUF_HEADROOM + MPIPE_RX_IP_ALIGN;\n\tvoid *buf_addr = RTE_PTR_ADD(mbuf->buf_addr, offset);\n\n\tgxio_mpipe_push_buffer(priv->context, priv->stack, buf_addr);\n\tPMD_DEBUG_RX(\"%s: Pushed mbuf %p, buffer %p into stack %d\\n\",\n\t\t mpipe_name(priv), mbuf, buf_addr, priv->stack);\n}\n\nstatic inline void\nmpipe_recv_fill_stack(struct mpipe_dev_priv *priv, int count)\n{\n\tstruct rte_mbuf *mbuf;\n\tint i;\n\n\tfor (i = 0; i < count; i++) {\n\t\tmbuf = __rte_mbuf_raw_alloc(priv->rx_mpool);\n\t\tif (!mbuf)\n\t\t\tbreak;\n\t\tmpipe_recv_push(priv, mbuf);\n\t}\n\n\tpriv->rx_buffers += count;\n\tPMD_DEBUG_RX(\"%s: Filled %d/%d buffers\\n\", mpipe_name(priv), i, count);\n}\n\nstatic inline void\nmpipe_recv_flush_stack(struct mpipe_dev_priv *priv)\n{\n\tconst int offset = priv->rx_offset & ~RTE_MEMPOOL_ALIGN_MASK;\n\tuint8_t in_port = priv->port_id;\n\tstruct rte_mbuf *mbuf;\n\tunsigned count;\n\tvoid *va;\n\n\tfor (count = 0; count < priv->rx_buffers; count++) {\n\t\tva = gxio_mpipe_pop_buffer(priv->context, priv->stack);\n\t\tif (!va)\n\t\t\tbreak;\n\t\tmbuf = RTE_PTR_SUB(va, offset);\n\n\t\tPMD_DEBUG_RX(\"%s: Flushing mbuf %p, va %p\\n\",\n\t\t\t mpipe_name(priv), mbuf, va);\n\n\t\tmbuf->data_off = (uintptr_t)va - (uintptr_t)mbuf->buf_addr;\n\t\tmbuf->refcnt = 1;\n\t\tmbuf->nb_segs = 1;\n\t\tmbuf->port = in_port;\n\t\tmbuf->packet_type = 0;\n\t\tmbuf->data_len = 0;\n\t\tmbuf->pkt_len = 0;\n\n\t\t__rte_mbuf_raw_free(mbuf);\n\t}\n\n\tPMD_DEBUG_RX(\"%s: Returned %d/%d buffers\\n\",\n\t\t mpipe_name(priv), count, priv->rx_buffers);\n\tpriv->rx_buffers -= count;\n}\n\nstatic void\nmpipe_register_segment(struct mpipe_dev_priv *priv, const struct rte_memseg *ms)\n{\n\tsize_t size = ms->hugepage_sz;\n\tuint8_t *addr, *end;\n\tint rc;\n\n\tfor (addr = ms->addr, end = addr + ms->len; addr < end; addr += size) {\n\t\trc = gxio_mpipe_register_page(priv->context, priv->stack, addr,\n\t\t\t\t\t size, 0);\n\t\tif (rc < 0)\n\t\t\tbreak;\n\t}\n\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Could not register memseg @%p, %d.\\n\",\n\t\t\tmpipe_name(priv), ms->addr, rc);\n\t} else {\n\t\tRTE_LOG(DEBUG, PMD, \"%s: Registered segment %p - %p\\n\",\n\t\t\tmpipe_name(priv), ms->addr,\n\t\t\tRTE_PTR_ADD(ms->addr, ms->len - 1));\n\t}\n}\n\nstatic int\nmpipe_recv_init(struct mpipe_dev_priv *priv)\n{\n\tconst struct rte_memseg *seg = rte_eal_get_physmem_layout();\n\tsize_t stack_size;\n\tvoid *stack_mem;\n\tint rc;\n\n\tif (!priv->rx_mpool) {\n\t\tRTE_LOG(ERR, PMD, \"%s: No buffer pool.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn -ENODEV;\n\t}\n\n\t/* Allocate one NotifRing for each queue. */\n\trc = gxio_mpipe_alloc_notif_rings(priv->context, MPIPE_RX_MAX_QUEUES,\n\t\t\t\t\t 0, 0);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate notif rings.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\tpriv->first_ring = rc;\n\n\t/* Allocate a NotifGroup. */\n\trc = gxio_mpipe_alloc_notif_groups(priv->context, 1, 0, 0);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate rx group.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\tpriv->notif_group = rc;\n\n\t/* Allocate required buckets. */\n\trc = gxio_mpipe_alloc_buckets(priv->context, MPIPE_RX_BUCKETS, 0, 0);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate buckets.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\tpriv->first_bucket = rc;\n\n\trc = gxio_mpipe_alloc_buffer_stacks(priv->context, 1, 0, 0);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate buffer stack.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\tpriv->stack = rc;\n\n\twhile (seg && seg->addr)\n\t\tmpipe_register_segment(priv, seg++);\n\n\tstack_size = gxio_mpipe_calc_buffer_stack_bytes(MPIPE_RX_STACK_SIZE);\n\tstack_mem = rte_zmalloc(NULL, stack_size, 65536);\n\tif (!stack_mem) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate buffer memory.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn -ENOMEM;\n\t} else {\n\t\tRTE_LOG(DEBUG, PMD, \"%s: Buffer stack memory %p - %p.\\n\",\n\t\t\tmpipe_name(priv), stack_mem,\n\t\t\tRTE_PTR_ADD(stack_mem, stack_size - 1));\n\t}\n\n\trc = gxio_mpipe_init_buffer_stack(priv->context, priv->stack,\n\t\t\t\t\t priv->rx_size_code, stack_mem,\n\t\t\t\t\t stack_size, 0);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to initialize buffer stack.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nmpipe_xmit_init(struct mpipe_dev_priv *priv)\n{\n\tsize_t ring_size;\n\tvoid *ring_mem;\n\tint rc;\n\n\t/* Allocate eDMA ring. */\n\trc = gxio_mpipe_alloc_edma_rings(priv->context, 1, 0, 0);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to alloc tx ring.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\tpriv->ering = rc;\n\n\trc = mpipe_equeue_size(MPIPE_TX_DESCS);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Cannot allocate %d equeue descs.\\n\",\n\t\t\tmpipe_name(priv), (int)MPIPE_TX_DESCS);\n\t\treturn -ENOMEM;\n\t}\n\tpriv->equeue_size = rc;\n\n\t/* Initialize completion array. */\n\tring_size = sizeof(priv->tx_comps[0]) * priv->equeue_size;\n\tpriv->tx_comps = rte_zmalloc(NULL, ring_size, RTE_CACHE_LINE_SIZE);\n\tif (!priv->tx_comps) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate egress comps.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Allocate eDMA ring memory. */\n\tring_size = sizeof(gxio_mpipe_edesc_t) * priv->equeue_size;\n\tring_mem = rte_zmalloc(NULL, ring_size, ring_size);\n\tif (!ring_mem) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate egress descs.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn -ENOMEM;\n\t} else {\n\t\tRTE_LOG(DEBUG, PMD, \"%s: eDMA ring memory %p - %p.\\n\",\n\t\t\tmpipe_name(priv), ring_mem,\n\t\t\tRTE_PTR_ADD(ring_mem, ring_size - 1));\n\t}\n\n\t/* Initialize eDMA ring. */\n\trc = gxio_mpipe_equeue_init(&priv->equeue, priv->context, priv->ering,\n\t\t\t\t priv->channel, ring_mem, ring_size, 0);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to init equeue\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nmpipe_link_init(struct mpipe_dev_priv *priv)\n{\n\tint rc;\n\n\t/* Open the link. */\n\trc = gxio_mpipe_link_open(&priv->link, priv->context,\n\t\t\t\t mpipe_name(priv), GXIO_MPIPE_LINK_AUTO_NONE);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to open link.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\n\t/* Get the channel index. */\n\trc = gxio_mpipe_link_channel(&priv->link);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Bad channel\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\tpriv->channel = rc;\n\n\treturn 0;\n}\n\nstatic int\nmpipe_init(struct mpipe_dev_priv *priv)\n{\n\tint rc;\n\n\tif (priv->initialized)\n\t\treturn 0;\n\n\trc = mpipe_link_init(priv);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to init link.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\n\trc = mpipe_recv_init(priv);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to init rx.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\n\trc = mpipe_xmit_init(priv);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to init tx.\\n\",\n\t\t\tmpipe_name(priv));\n\t\trte_free(priv);\n\t\treturn rc;\n\t}\n\n\tpriv->initialized = 1;\n\n\treturn 0;\n}\n\nstatic int\nmpipe_start(struct rte_eth_dev *dev)\n{\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\tstruct mpipe_channel_config config;\n\tstruct mpipe_rx_queue *rx_queue;\n\tstruct rte_eth_link eth_link;\n\tunsigned queue, buffers = 0;\n\tsize_t ring_size;\n\tvoid *ring_mem;\n\tint rc;\n\n\tmemset(ð_link, 0, sizeof(eth_link));\n\tmpipe_dev_atomic_write_link_status(dev, ð_link);\n\n\trc = mpipe_init(priv);\n\tif (rc < 0)\n\t\treturn rc;\n\n\t/* Initialize NotifRings. */\n\tfor (queue = 0; queue < priv->nb_rx_queues; queue++) {\n\t\trx_queue = mpipe_rx_queue(priv, queue);\n\t\tring_size = rx_queue->q.nb_desc * sizeof(gxio_mpipe_idesc_t);\n\n\t\tring_mem = rte_malloc(NULL, ring_size, ring_size);\n\t\tif (!ring_mem) {\n\t\t\tRTE_LOG(ERR, PMD, \"%s: Failed to alloc rx descs.\\n\",\n\t\t\t\tmpipe_name(priv));\n\t\t\treturn -ENOMEM;\n\t\t} else {\n\t\t\tRTE_LOG(DEBUG, PMD, \"%s: iDMA ring %d memory %p - %p.\\n\",\n\t\t\t\tmpipe_name(priv), queue, ring_mem,\n\t\t\t\tRTE_PTR_ADD(ring_mem, ring_size - 1));\n\t\t}\n\n\t\trc = gxio_mpipe_iqueue_init(&rx_queue->iqueue, priv->context,\n\t\t\t\t\t priv->first_ring + queue, ring_mem,\n\t\t\t\t\t ring_size, 0);\n\t\tif (rc < 0) {\n\t\t\tRTE_LOG(ERR, PMD, \"%s: Failed to init rx queue.\\n\",\n\t\t\t\tmpipe_name(priv));\n\t\t\treturn rc;\n\t\t}\n\n\t\trx_queue->rx_ring_mem = ring_mem;\n\t\tbuffers += rx_queue->q.nb_desc;\n\t}\n\n\t/* Initialize ingress NotifGroup and buckets. */\n\trc = gxio_mpipe_init_notif_group_and_buckets(priv->context,\n\t\t\tpriv->notif_group, priv->first_ring, priv->nb_rx_queues,\n\t\t\tpriv->first_bucket, MPIPE_RX_BUCKETS,\n\t\t\tGXIO_MPIPE_BUCKET_STATIC_FLOW_AFFINITY);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to init group and buckets.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\n\t/* Configure the classifier to deliver packets from this port. */\n\tconfig.enable = 1;\n\tconfig.first_bucket = priv->first_bucket;\n\tconfig.num_buckets = MPIPE_RX_BUCKETS;\n\tmemset(&config.stacks, 0xff, sizeof(config.stacks));\n\tconfig.stacks.stacks[priv->rx_size_code] = priv->stack;\n\tconfig.head_room = priv->rx_offset & RTE_MEMPOOL_ALIGN_MASK;\n\n\trc = mpipe_channel_config(priv->instance, priv->channel,\n\t\t\t\t &config);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to setup classifier.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn rc;\n\t}\n\n\t/* Fill empty buffers into the buffer stack. */\n\tmpipe_recv_fill_stack(priv, buffers);\n\n\t/* Bring up the link. */\n\tmpipe_set_link_up(dev);\n\n\t/* Start xmit/recv on queues. */\n\tfor (queue = 0; queue < priv->nb_tx_queues; queue++)\n\t\tmpipe_tx_queue(priv, queue)->q.link_status = 1;\n\tfor (queue = 0; queue < priv->nb_rx_queues; queue++)\n\t\tmpipe_rx_queue(priv, queue)->q.link_status = 1;\n\tpriv->running = 1;\n\n\treturn 0;\n}\n\nstatic void\nmpipe_stop(struct rte_eth_dev *dev)\n{\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\tstruct mpipe_channel_config config;\n\tunsigned queue;\n\tint rc;\n\n\tfor (queue = 0; queue < priv->nb_tx_queues; queue++)\n\t\tmpipe_tx_queue(priv, queue)->q.link_status = 0;\n\tfor (queue = 0; queue < priv->nb_rx_queues; queue++)\n\t\tmpipe_rx_queue(priv, queue)->q.link_status = 0;\n\n\t/* Make sure the link_status writes land. */\n\trte_wmb();\n\n\t/*\n\t * Wait for link_status change to register with straggling datapath\n\t * threads.\n\t */\n\tmpipe_dp_wait(priv);\n\n\t/* Bring down the link. */\n\tmpipe_set_link_down(dev);\n\n\t/* Remove classifier rules. */\n\tmemset(&config, 0, sizeof(config));\n\trc = mpipe_channel_config(priv->instance, priv->channel,\n\t\t\t\t &config);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to stop classifier.\\n\",\n\t\t\tmpipe_name(priv));\n\t}\n\n\t/* Flush completed xmit packets. */\n\tmpipe_xmit_flush(priv);\n\n\t/* Flush buffer stacks. */\n\tmpipe_recv_flush(priv);\n\n\tpriv->running = 0;\n}\n\nstatic void\nmpipe_close(struct rte_eth_dev *dev)\n{\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\tif (priv->running)\n\t\tmpipe_stop(dev);\n}\n\nstatic void\nmpipe_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\tstruct mpipe_tx_queue *tx_queue;\n\tstruct mpipe_rx_queue *rx_queue;\n\tunsigned i;\n\tuint16_t idx;\n\n\tmemset(stats, 0, sizeof(*stats));\n\n\tfor (i = 0; i < priv->nb_tx_queues; i++) {\n\t\ttx_queue = mpipe_tx_queue(priv, i);\n\n\t\tstats->opackets += tx_queue->q.stats.packets;\n\t\tstats->obytes += tx_queue->q.stats.bytes;\n\t\tstats->oerrors += tx_queue->q.stats.errors;\n\n\t\tidx = tx_queue->q.stat_idx;\n\t\tif (idx != (uint16_t)-1) {\n\t\t\tstats->q_opackets[idx] += tx_queue->q.stats.packets;\n\t\t\tstats->q_obytes[idx] += tx_queue->q.stats.bytes;\n\t\t\tstats->q_errors[idx] += tx_queue->q.stats.errors;\n\t\t}\n\t}\n\n\tfor (i = 0; i < priv->nb_rx_queues; i++) {\n\t\trx_queue = mpipe_rx_queue(priv, i);\n\n\t\tstats->ipackets += rx_queue->q.stats.packets;\n\t\tstats->ibytes += rx_queue->q.stats.bytes;\n\t\tstats->ierrors += rx_queue->q.stats.errors;\n\t\tstats->rx_nombuf += rx_queue->q.stats.nomem;\n\n\t\tidx = rx_queue->q.stat_idx;\n\t\tif (idx != (uint16_t)-1) {\n\t\t\tstats->q_ipackets[idx] += rx_queue->q.stats.packets;\n\t\t\tstats->q_ibytes[idx] += rx_queue->q.stats.bytes;\n\t\t\tstats->q_errors[idx] += rx_queue->q.stats.errors;\n\t\t}\n\t}\n}\n\nstatic void\nmpipe_stats_reset(struct rte_eth_dev *dev)\n{\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\tstruct mpipe_tx_queue *tx_queue;\n\tstruct mpipe_rx_queue *rx_queue;\n\tunsigned i;\n\n\tfor (i = 0; i < priv->nb_tx_queues; i++) {\n\t\ttx_queue = mpipe_tx_queue(priv, i);\n\t\tmemset(&tx_queue->q.stats, 0, sizeof(tx_queue->q.stats));\n\t}\n\n\tfor (i = 0; i < priv->nb_rx_queues; i++) {\n\t\trx_queue = mpipe_rx_queue(priv, i);\n\t\tmemset(&rx_queue->q.stats, 0, sizeof(rx_queue->q.stats));\n\t}\n}\n\nstatic int\nmpipe_queue_stats_mapping_set(struct rte_eth_dev *dev, uint16_t queue_id,\n\t\t\t uint8_t stat_idx, uint8_t is_rx)\n{\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\n\tif (is_rx) {\n\t\tpriv->rx_stat_mapping[stat_idx] = queue_id;\n\t} else {\n\t\tpriv->tx_stat_mapping[stat_idx] = queue_id;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nmpipe_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n\t\t uint16_t nb_desc, unsigned int socket_id __rte_unused,\n\t\t const struct rte_eth_txconf *tx_conf __rte_unused)\n{\n\tstruct mpipe_tx_queue *tx_queue = dev->data->tx_queues[queue_idx];\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\tuint16_t idx;\n\n\ttx_queue = rte_realloc(tx_queue, sizeof(*tx_queue),\n\t\t\t RTE_CACHE_LINE_SIZE);\n\tif (!tx_queue) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate TX queue.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn -ENOMEM;\n\t}\n\n\tmemset(&tx_queue->q, 0, sizeof(tx_queue->q));\n\ttx_queue->q.priv = priv;\n\ttx_queue->q.queue_idx = queue_idx;\n\ttx_queue->q.port_id = dev->data->port_id;\n\ttx_queue->q.nb_desc = nb_desc;\n\n\ttx_queue->q.stat_idx = -1;\n\tfor (idx = 0; idx < RTE_ETHDEV_QUEUE_STAT_CNTRS; idx++) {\n\t\tif (priv->tx_stat_mapping[idx] == queue_idx)\n\t\t\ttx_queue->q.stat_idx = idx;\n\t}\n\n\tdev->data->tx_queues[queue_idx] = tx_queue;\n\n\treturn 0;\n}\n\nstatic void\nmpipe_tx_queue_release(void *_txq)\n{\n\trte_free(_txq);\n}\n\nstatic int\nmpipe_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n\t\t uint16_t nb_desc, unsigned int socket_id __rte_unused,\n\t\t const struct rte_eth_rxconf *rx_conf __rte_unused,\n\t\t struct rte_mempool *mp)\n{\n\tstruct mpipe_rx_queue *rx_queue = dev->data->rx_queues[queue_idx];\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\tuint16_t idx;\n\tint size, rc;\n\n\trc = mpipe_iqueue_size(nb_desc);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Cannot allocate %d iqueue descs.\\n\",\n\t\t\tmpipe_name(priv), (int)nb_desc);\n\t\treturn -ENOMEM;\n\t}\n\n\tif (rc != nb_desc) {\n\t\tRTE_LOG(WARNING, PMD, \"%s: Extending RX descs from %d to %d.\\n\",\n\t\t\tmpipe_name(priv), (int)nb_desc, rc);\n\t\tnb_desc = rc;\n\t}\n\n\tsize = sizeof(*rx_queue);\n\trx_queue = rte_realloc(rx_queue, size, RTE_CACHE_LINE_SIZE);\n\tif (!rx_queue) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate RX queue.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn -ENOMEM;\n\t}\n\n\tmemset(&rx_queue->q, 0, sizeof(rx_queue->q));\n\trx_queue->q.priv = priv;\n\trx_queue->q.nb_desc = nb_desc;\n\trx_queue->q.port_id = dev->data->port_id;\n\trx_queue->q.queue_idx = queue_idx;\n\n\tif (!priv->rx_mpool) {\n\t\tint size = (rte_pktmbuf_data_room_size(mp) -\n\t\t\t RTE_PKTMBUF_HEADROOM -\n\t\t\t MPIPE_RX_IP_ALIGN);\n\n\t\tpriv->rx_offset = (sizeof(struct rte_mbuf) +\n\t\t\t\t rte_pktmbuf_priv_size(mp) +\n\t\t\t\t RTE_PKTMBUF_HEADROOM +\n\t\t\t\t MPIPE_RX_IP_ALIGN);\n\t\tif (size < 0) {\n\t\t\tRTE_LOG(ERR, PMD, \"%s: Bad buffer size %d.\\n\",\n\t\t\t\tmpipe_name(priv),\n\t\t\t\trte_pktmbuf_data_room_size(mp));\n\t\t\treturn -ENOMEM;\n\t\t}\n\n\t\tpriv->rx_size_code = mpipe_buffer_size_index(size);\n\t\tpriv->rx_mpool = mp;\n\t}\n\n\tif (priv->rx_mpool != mp) {\n\t\tRTE_LOG(WARNING, PMD, \"%s: Ignoring multiple buffer pools.\\n\",\n\t\t\tmpipe_name(priv));\n\t}\n\n\trx_queue->q.stat_idx = -1;\n\tfor (idx = 0; idx < RTE_ETHDEV_QUEUE_STAT_CNTRS; idx++) {\n\t\tif (priv->rx_stat_mapping[idx] == queue_idx)\n\t\t\trx_queue->q.stat_idx = idx;\n\t}\n\n\tdev->data->rx_queues[queue_idx] = rx_queue;\n\n\treturn 0;\n}\n\nstatic void\nmpipe_rx_queue_release(void *_rxq)\n{\n\trte_free(_rxq);\n}\n\n#define MPIPE_XGBE_ENA_HASH_MULTI\t\\\n\t(1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__ENA_HASH_MULTI_SHIFT)\n#define MPIPE_XGBE_ENA_HASH_UNI\t\t\\\n\t(1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__ENA_HASH_UNI_SHIFT)\n#define MPIPE_XGBE_COPY_ALL\t\t\\\n\t(1UL << MPIPE_XAUI_RECEIVE_CONFIGURATION__COPY_ALL_SHIFT)\n#define MPIPE_GBE_ENA_MULTI_HASH\t\\\n\t(1UL << MPIPE_GBE_NETWORK_CONFIGURATION__MULTI_HASH_ENA_SHIFT)\n#define MPIPE_GBE_ENA_UNI_HASH\t\t\\\n\t(1UL << MPIPE_GBE_NETWORK_CONFIGURATION__UNI_HASH_ENA_SHIFT)\n#define MPIPE_GBE_COPY_ALL\t\t\\\n\t(1UL << MPIPE_GBE_NETWORK_CONFIGURATION__COPY_ALL_SHIFT)\n\nstatic void\nmpipe_promiscuous_enable(struct rte_eth_dev *dev)\n{\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\tint64_t reg;\n\tint addr;\n\n\tif (priv->is_xaui) {\n\t\taddr = MPIPE_XAUI_RECEIVE_CONFIGURATION;\n\t\treg = gxio_mpipe_link_mac_rd(&priv->link, addr);\n\t\treg &= ~MPIPE_XGBE_ENA_HASH_MULTI;\n\t\treg &= ~MPIPE_XGBE_ENA_HASH_UNI;\n\t\treg |= MPIPE_XGBE_COPY_ALL;\n\t\tgxio_mpipe_link_mac_wr(&priv->link, addr, reg);\n\t} else {\n\t\taddr = MPIPE_GBE_NETWORK_CONFIGURATION;\n\t\treg = gxio_mpipe_link_mac_rd(&priv->link, addr);\n\t\treg &= ~MPIPE_GBE_ENA_MULTI_HASH;\n\t\treg &= ~MPIPE_GBE_ENA_UNI_HASH;\n\t\treg |= MPIPE_GBE_COPY_ALL;\n\t\tgxio_mpipe_link_mac_wr(&priv->link, addr, reg);\n\t}\n}\n\nstatic void\nmpipe_promiscuous_disable(struct rte_eth_dev *dev)\n{\n\tstruct mpipe_dev_priv *priv = mpipe_priv(dev);\n\tint64_t reg;\n\tint addr;\n\n\tif (priv->is_xaui) {\n\t\taddr = MPIPE_XAUI_RECEIVE_CONFIGURATION;\n\t\treg = gxio_mpipe_link_mac_rd(&priv->link, addr);\n\t\treg |= MPIPE_XGBE_ENA_HASH_MULTI;\n\t\treg |= MPIPE_XGBE_ENA_HASH_UNI;\n\t\treg &= ~MPIPE_XGBE_COPY_ALL;\n\t\tgxio_mpipe_link_mac_wr(&priv->link, addr, reg);\n\t} else {\n\t\taddr = MPIPE_GBE_NETWORK_CONFIGURATION;\n\t\treg = gxio_mpipe_link_mac_rd(&priv->link, addr);\n\t\treg |= MPIPE_GBE_ENA_MULTI_HASH;\n\t\treg |= MPIPE_GBE_ENA_UNI_HASH;\n\t\treg &= ~MPIPE_GBE_COPY_ALL;\n\t\tgxio_mpipe_link_mac_wr(&priv->link, addr, reg);\n\t}\n}\n\nstatic struct eth_dev_ops mpipe_dev_ops = {\n\t.dev_infos_get\t = mpipe_infos_get,\n\t.dev_configure\t = mpipe_configure,\n\t.dev_start\t = mpipe_start,\n\t.dev_stop\t = mpipe_stop,\n\t.dev_close\t = mpipe_close,\n\t.stats_get\t = mpipe_stats_get,\n\t.stats_reset\t = mpipe_stats_reset,\n\t.queue_stats_mapping_set = mpipe_queue_stats_mapping_set,\n\t.tx_queue_setup\t = mpipe_tx_queue_setup,\n\t.rx_queue_setup\t = mpipe_rx_queue_setup,\n\t.tx_queue_release\t = mpipe_tx_queue_release,\n\t.rx_queue_release\t = mpipe_rx_queue_release,\n\t.link_update\t = mpipe_link_update,\n\t.dev_set_link_up = mpipe_set_link_up,\n\t.dev_set_link_down = mpipe_set_link_down,\n\t.promiscuous_enable = mpipe_promiscuous_enable,\n\t.promiscuous_disable = mpipe_promiscuous_disable,\n};\n\nstatic inline void\nmpipe_xmit_null(struct mpipe_dev_priv *priv, int64_t start, int64_t end)\n{\n\tgxio_mpipe_edesc_t null_desc = { { .bound = 1, .ns = 1 } };\n\tgxio_mpipe_equeue_t *equeue = &priv->equeue;\n\tint64_t slot;\n\n\tfor (slot = start; slot < end; slot++) {\n\t\tgxio_mpipe_equeue_put_at(equeue, null_desc, slot);\n\t}\n}\n\nstatic void\nmpipe_xmit_flush(struct mpipe_dev_priv *priv)\n{\n\tgxio_mpipe_equeue_t *equeue = &priv->equeue;\n\tint64_t slot;\n\n\t/* Post a dummy descriptor and wait for its return. */\n\tslot = gxio_mpipe_equeue_reserve(equeue, 1);\n\tif (slot < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to reserve stop slot.\\n\",\n\t\t\tmpipe_name(priv));\n\t\treturn;\n\t}\n\n\tmpipe_xmit_null(priv, slot, slot + 1);\n\n\twhile (!gxio_mpipe_equeue_is_complete(equeue, slot, 1)) {\n\t\trte_pause();\n\t}\n\n\tfor (slot = 0; slot < priv->equeue_size; slot++) {\n\t\tif (priv->tx_comps[slot])\n\t\t\trte_pktmbuf_free_seg(priv->tx_comps[slot]);\n\t}\n}\n\nstatic void\nmpipe_recv_flush(struct mpipe_dev_priv *priv)\n{\n\tuint8_t in_port = priv->port_id;\n\tstruct mpipe_rx_queue *rx_queue;\n\tgxio_mpipe_iqueue_t *iqueue;\n\tgxio_mpipe_idesc_t idesc;\n\tstruct rte_mbuf *mbuf;\n\tint retries = 0;\n\tunsigned queue;\n\n\tdo {\n\t\tmpipe_recv_flush_stack(priv);\n\n\t\t/* Flush packets sitting in recv queues. */\n\t\tfor (queue = 0; queue < priv->nb_rx_queues; queue++) {\n\t\t\trx_queue = mpipe_rx_queue(priv, queue);\n\t\t\tiqueue = &rx_queue->iqueue;\n\t\t\twhile (gxio_mpipe_iqueue_try_get(iqueue, &idesc) >= 0) {\n\t\t\t\tmbuf = mpipe_recv_mbuf(priv, &idesc, in_port);\n\t\t\t\trte_pktmbuf_free(mbuf);\n\t\t\t\tpriv->rx_buffers--;\n\t\t\t}\n\t\t\trte_free(rx_queue->rx_ring_mem);\n\t\t}\n\t} while (retries++ < 10 && priv->rx_buffers);\n\n\tif (priv->rx_buffers) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Leaked %d receive buffers.\\n\",\n\t\t\tmpipe_name(priv), priv->rx_buffers);\n\t} else {\n\t\tPMD_DEBUG_RX(\"%s: Returned all receive buffers.\\n\",\n\t\t\t mpipe_name(priv));\n\t}\n}\n\nstatic inline uint16_t\nmpipe_do_xmit(struct mpipe_tx_queue *tx_queue, struct rte_mbuf **tx_pkts,\n\t uint16_t nb_pkts)\n{\n\tstruct mpipe_dev_priv *priv = tx_queue->q.priv;\n\tgxio_mpipe_equeue_t *equeue = &priv->equeue;\n\tunsigned nb_bytes = 0;\n\tunsigned nb_sent = 0;\n\tint nb_slots, i;\n\n\tPMD_DEBUG_TX(\"Trying to transmit %d packets on %s:%d.\\n\",\n\t\t nb_pkts, mpipe_name(tx_queue->q.priv),\n\t\t tx_queue->q.queue_idx);\n\n\t/* Optimistic assumption that we need exactly one slot per packet. */\n\tnb_slots = RTE_MIN(nb_pkts, MPIPE_TX_DESCS / 2);\n\n\tdo {\n\t\tstruct rte_mbuf *mbuf = NULL, *pkt = NULL;\n\t\tint64_t slot;\n\n\t\t/* Reserve eDMA ring slots. */\n\t\tslot = gxio_mpipe_equeue_try_reserve_fast(equeue, nb_slots);\n\t\tif (unlikely(slot < 0)) {\n\t\t\tbreak;\n\t\t}\n\n\t\tfor (i = 0; i < nb_slots; i++) {\n\t\t\tunsigned idx = (slot + i) & (priv->equeue_size - 1);\n\t\t\trte_prefetch0(priv->tx_comps[idx]);\n\t\t}\n\n\t\t/* Fill up slots with descriptor and completion info. */\n\t\tfor (i = 0; i < nb_slots; i++) {\n\t\t\tunsigned idx = (slot + i) & (priv->equeue_size - 1);\n\t\t\tgxio_mpipe_edesc_t desc;\n\t\t\tstruct rte_mbuf *next;\n\n\t\t\t/* Starting on a new packet? */\n\t\t\tif (likely(!mbuf)) {\n\t\t\t\tint room = nb_slots - i;\n\n\t\t\t\tpkt = mbuf = tx_pkts[nb_sent];\n\n\t\t\t\t/* Bail out if we run out of descs. */\n\t\t\t\tif (unlikely(pkt->nb_segs > room))\n\t\t\t\t\tbreak;\n\n\t\t\t\tnb_sent++;\n\t\t\t}\n\n\t\t\t/* We have a segment to send. */\n\t\t\tnext = mbuf->next;\n\n\t\t\tif (priv->tx_comps[idx])\n\t\t\t\trte_pktmbuf_free_seg(priv->tx_comps[idx]);\n\n\t\t\tdesc = (gxio_mpipe_edesc_t) { {\n\t\t\t\t.va = rte_pktmbuf_mtod(mbuf, uintptr_t),\n\t\t\t\t.xfer_size = rte_pktmbuf_data_len(mbuf),\n\t\t\t\t.bound = next ? 0 : 1,\n\t\t\t} };\n\n\t\t\tnb_bytes += mbuf->data_len;\n\t\t\tpriv->tx_comps[idx] = mbuf;\n\t\t\tgxio_mpipe_equeue_put_at(equeue, desc, slot + i);\n\n\t\t\tPMD_DEBUG_TX(\"%s:%d: Sending packet %p, len %d\\n\",\n\t\t\t\t mpipe_name(priv),\n\t\t\t\t tx_queue->q.queue_idx,\n\t\t\t\t rte_pktmbuf_mtod(mbuf, void *),\n\t\t\t\t rte_pktmbuf_data_len(mbuf));\n\n\t\t\tmbuf = next;\n\t\t}\n\n\t\tif (unlikely(nb_sent < nb_pkts)) {\n\n\t\t\t/* Fill remaining slots with null descriptors. */\n\t\t\tmpipe_xmit_null(priv, slot + i, slot + nb_slots);\n\n\t\t\t/*\n\t\t\t * Calculate exact number of descriptors needed for\n\t\t\t * the next go around.\n\t\t\t */\n\t\t\tnb_slots = 0;\n\t\t\tfor (i = nb_sent; i < nb_pkts; i++) {\n\t\t\t\tnb_slots += tx_pkts[i]->nb_segs;\n\t\t\t}\n\n\t\t\tnb_slots = RTE_MIN(nb_slots, MPIPE_TX_DESCS / 2);\n\t\t}\n\t} while (nb_sent < nb_pkts);\n\n\ttx_queue->q.stats.packets += nb_sent;\n\ttx_queue->q.stats.bytes += nb_bytes;\n\n\treturn nb_sent;\n}\n\nstatic inline uint16_t\nmpipe_do_recv(struct mpipe_rx_queue *rx_queue, struct rte_mbuf **rx_pkts,\n\t uint16_t nb_pkts)\n{\n\tstruct mpipe_dev_priv *priv = rx_queue->q.priv;\n\tgxio_mpipe_iqueue_t *iqueue = &rx_queue->iqueue;\n\tgxio_mpipe_idesc_t *first_idesc, *idesc, *last_idesc;\n\tuint8_t in_port = rx_queue->q.port_id;\n\tconst unsigned look_ahead = 8;\n\tint room = nb_pkts, rc = 0;\n\tunsigned nb_packets = 0;\n\tunsigned nb_dropped = 0;\n\tunsigned nb_nomem = 0;\n\tunsigned nb_bytes = 0;\n\tunsigned nb_descs, i;\n\n\twhile (room && !rc) {\n\t\tif (rx_queue->avail_descs < room) {\n\t\t\trc = gxio_mpipe_iqueue_try_peek(iqueue,\n\t\t\t\t\t\t\t&rx_queue->next_desc);\n\t\t\trx_queue->avail_descs = rc < 0 ? 0 : rc;\n\t\t}\n\n\t\tif (unlikely(!rx_queue->avail_descs)) {\n\t\t\tbreak;\n\t\t}\n\n\t\tnb_descs = RTE_MIN(room, rx_queue->avail_descs);\n\n\t\tfirst_idesc = rx_queue->next_desc;\n\t\tlast_idesc = first_idesc + nb_descs;\n\n\t\trx_queue->next_desc += nb_descs;\n\t\trx_queue->avail_descs -= nb_descs;\n\n\t\tfor (i = 1; i < look_ahead; i++) {\n\t\t\trte_prefetch0(first_idesc + i);\n\t\t}\n\n\t\tPMD_DEBUG_RX(\"%s:%d: Trying to receive %d packets\\n\",\n\t\t\t mpipe_name(rx_queue->q.priv),\n\t\t\t rx_queue->q.queue_idx,\n\t\t\t nb_descs);\n\n\t\tfor (idesc = first_idesc; idesc < last_idesc; idesc++) {\n\t\t\tstruct rte_mbuf *mbuf;\n\n\t\t\tPMD_DEBUG_RX(\"%s:%d: processing idesc %d/%d\\n\",\n\t\t\t\t mpipe_name(priv),\n\t\t\t\t rx_queue->q.queue_idx,\n\t\t\t\t nb_packets, nb_descs);\n\n\t\t\trte_prefetch0(idesc + look_ahead);\n\n\t\t\tPMD_DEBUG_RX(\"%s:%d: idesc %p, %s%s%s%s%s%s%s%s%s%s\"\n\t\t\t\t \"size: %d, bkt: %d, chan: %d, ring: %d, sqn: %lu, va: %lu\\n\",\n\t\t\t\t mpipe_name(priv),\n\t\t\t\t rx_queue->q.queue_idx,\n\t\t\t\t idesc,\n\t\t\t\t idesc->me ? \"me, \" : \"\",\n\t\t\t\t idesc->tr ? \"tr, \" : \"\",\n\t\t\t\t idesc->ce ? \"ce, \" : \"\",\n\t\t\t\t idesc->ct ? \"ct, \" : \"\",\n\t\t\t\t idesc->cs ? \"cs, \" : \"\",\n\t\t\t\t idesc->nr ? \"nr, \" : \"\",\n\t\t\t\t idesc->sq ? \"sq, \" : \"\",\n\t\t\t\t idesc->ts ? \"ts, \" : \"\",\n\t\t\t\t idesc->ps ? \"ps, \" : \"\",\n\t\t\t\t idesc->be ? \"be, \" : \"\",\n\t\t\t\t idesc->l2_size,\n\t\t\t\t idesc->bucket_id,\n\t\t\t\t idesc->channel,\n\t\t\t\t idesc->notif_ring,\n\t\t\t\t (unsigned long)idesc->packet_sqn,\n\t\t\t\t (unsigned long)idesc->va);\n\n\t\t\tif (unlikely(gxio_mpipe_idesc_has_error(idesc))) {\n\t\t\t\tnb_dropped++;\n\t\t\t\tgxio_mpipe_iqueue_drop(iqueue, idesc);\n\t\t\t\tPMD_DEBUG_RX(\"%s:%d: Descriptor error\\n\",\n\t\t\t\t\t mpipe_name(rx_queue->q.priv),\n\t\t\t\t\t rx_queue->q.queue_idx);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tmbuf = __rte_mbuf_raw_alloc(priv->rx_mpool);\n\t\t\tif (unlikely(!mbuf)) {\n\t\t\t\tnb_nomem++;\n\t\t\t\tgxio_mpipe_iqueue_drop(iqueue, idesc);\n\t\t\t\tPMD_DEBUG_RX(\"%s:%d: RX alloc failure\\n\",\n\t\t\t\t\t mpipe_name(rx_queue->q.priv),\n\t\t\t\t\t rx_queue->q.queue_idx);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tmpipe_recv_push(priv, mbuf);\n\n\t\t\t/* Get and setup the mbuf for the received packet. */\n\t\t\tmbuf = mpipe_recv_mbuf(priv, idesc, in_port);\n\n\t\t\t/* Update results and statistics counters. */\n\t\t\trx_pkts[nb_packets] = mbuf;\n\t\t\tnb_bytes += mbuf->pkt_len;\n\t\t\tnb_packets++;\n\t\t}\n\n\t\t/*\n\t\t * We release the ring in bursts, but do not track and release\n\t\t * buckets. This therefore breaks dynamic flow affinity, but\n\t\t * we always operate in static affinity mode, and so we're OK\n\t\t * with this optimization.\n\t\t */\n\t\tgxio_mpipe_iqueue_advance(iqueue, nb_descs);\n\t\tgxio_mpipe_credit(iqueue->context, iqueue->ring, -1, nb_descs);\n\n\t\t/*\n\t\t * Go around once more if we haven't yet peeked the queue, and\n\t\t * if we have more room to receive.\n\t\t */\n\t\troom = nb_pkts - nb_packets;\n\t}\n\n\trx_queue->q.stats.packets += nb_packets;\n\trx_queue->q.stats.bytes += nb_bytes;\n\trx_queue->q.stats.errors += nb_dropped;\n\trx_queue->q.stats.nomem += nb_nomem;\n\n\tPMD_DEBUG_RX(\"%s:%d: RX: %d/%d pkts/bytes, %d/%d drops/nomem\\n\",\n\t\t mpipe_name(rx_queue->q.priv), rx_queue->q.queue_idx,\n\t\t nb_packets, nb_bytes, nb_dropped, nb_nomem);\n\n\treturn nb_packets;\n}\n\nstatic uint16_t\nmpipe_recv_pkts(void *_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n{\n\tstruct mpipe_rx_queue *rx_queue = _rxq;\n\tuint16_t result = 0;\n\n\tif (rx_queue) {\n\t\tmpipe_dp_enter(rx_queue->q.priv);\n\t\tif (likely(rx_queue->q.link_status))\n\t\t\tresult = mpipe_do_recv(rx_queue, rx_pkts, nb_pkts);\n\t\tmpipe_dp_exit(rx_queue->q.priv);\n\t}\n\n\treturn result;\n}\n\nstatic uint16_t\nmpipe_xmit_pkts(void *_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n{\n\tstruct mpipe_tx_queue *tx_queue = _txq;\n\tuint16_t result = 0;\n\n\tif (tx_queue) {\n\t\tmpipe_dp_enter(tx_queue->q.priv);\n\t\tif (likely(tx_queue->q.link_status))\n\t\t\tresult = mpipe_do_xmit(tx_queue, tx_pkts, nb_pkts);\n\t\tmpipe_dp_exit(tx_queue->q.priv);\n\t}\n\n\treturn result;\n}\n\nstatic int\nmpipe_link_mac(const char *ifname, uint8_t *mac)\n{\n\tint rc, idx;\n\tchar name[GXIO_MPIPE_LINK_NAME_LEN];\n\n\tfor (idx = 0, rc = 0; !rc; idx++) {\n\t\trc = gxio_mpipe_link_enumerate_mac(idx, name, mac);\n\t\tif (!rc && !strncmp(name, ifname, GXIO_MPIPE_LINK_NAME_LEN))\n\t\t\treturn 0;\n\t}\n\treturn -ENODEV;\n}\n\nstatic int\nrte_pmd_mpipe_devinit(const char *ifname,\n\t\t const char *params __rte_unused)\n{\n\tgxio_mpipe_context_t *context;\n\tstruct rte_eth_dev *eth_dev;\n\tstruct mpipe_dev_priv *priv;\n\tint instance, rc;\n\tuint8_t *mac;\n\n\t/* Get the mPIPE instance that the device belongs to. */\n\tinstance = gxio_mpipe_link_instance(ifname);\n\tcontext = mpipe_context(instance);\n\tif (!context) {\n\t\tRTE_LOG(ERR, PMD, \"%s: No device for link.\\n\", ifname);\n\t\treturn -ENODEV;\n\t}\n\n\tpriv = rte_zmalloc(NULL, sizeof(*priv), 0);\n\tif (!priv) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate priv.\\n\", ifname);\n\t\treturn -ENOMEM;\n\t}\n\n\tmemset(&priv->tx_stat_mapping, 0xff, sizeof(priv->tx_stat_mapping));\n\tmemset(&priv->rx_stat_mapping, 0xff, sizeof(priv->rx_stat_mapping));\n\tpriv->context = context;\n\tpriv->instance = instance;\n\tpriv->is_xaui = (strncmp(ifname, \"xgbe\", 4) == 0);\n\tpriv->pci_dev.numa_node = instance;\n\tpriv->channel = -1;\n\n\tmac = priv->mac_addr.addr_bytes;\n\trc = mpipe_link_mac(ifname, mac);\n\tif (rc < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to enumerate link.\\n\", ifname);\n\t\trte_free(priv);\n\t\treturn -ENODEV;\n\t}\n\n\teth_dev = rte_eth_dev_allocate(ifname, RTE_ETH_DEV_VIRTUAL);\n\tif (!eth_dev) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to allocate device.\\n\", ifname);\n\t\trte_free(priv);\n\t}\n\n\tRTE_LOG(INFO, PMD, \"%s: Initialized mpipe device\"\n\t\t\"(mac %02x:%02x:%02x:%02x:%02x:%02x).\\n\",\n\t\tifname, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);\n\n\tpriv->eth_dev = eth_dev;\n\tpriv->port_id = eth_dev->data->port_id;\n\teth_dev->data->dev_private = priv;\n\teth_dev->pci_dev = &priv->pci_dev;\n\teth_dev->data->mac_addrs = &priv->mac_addr;\n\n\teth_dev->dev_ops = &mpipe_dev_ops;\n\teth_dev->rx_pkt_burst = &mpipe_recv_pkts;\n\teth_dev->tx_pkt_burst = &mpipe_xmit_pkts;\n\n\treturn 0;\n}\n\nstatic struct rte_driver pmd_mpipe_xgbe_drv = {\n\t.name = \"xgbe\",\n\t.type = PMD_VDEV,\n\t.init = rte_pmd_mpipe_devinit,\n};\n\nstatic struct rte_driver pmd_mpipe_gbe_drv = {\n\t.name = \"gbe\",\n\t.type = PMD_VDEV,\n\t.init = rte_pmd_mpipe_devinit,\n};\n\nPMD_REGISTER_DRIVER(pmd_mpipe_xgbe_drv);\nPMD_REGISTER_DRIVER(pmd_mpipe_gbe_drv);\n\nstatic void __attribute__((constructor, used))\nmpipe_init_contexts(void)\n{\n\tstruct mpipe_context *context;\n\tint rc, instance;\n\n\tfor (instance = 0; instance < GXIO_MPIPE_INSTANCE_MAX; instance++) {\n\t\tcontext = &mpipe_contexts[instance];\n\n\t\trte_spinlock_init(&context->lock);\n\t\trc = gxio_mpipe_init(&context->context, instance);\n\t\tif (rc < 0)\n\t\t\tbreak;\n\t}\n\n\tmpipe_instances = instance;\n}\n" }, { "path": "drivers/net/null/Makefile", "content": "# BSD LICENSE\n#\n# Copyright (C) IGEL Co.,Ltd.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of IGEL Co.,Ltd. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_null.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_pmd_null_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_NULL) += rte_eth_null.c\n\n#\n# Export include files\n#\nSYMLINK-y-include +=\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_NULL) += lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_NULL) += lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_NULL) += lib/librte_kvargs\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/null/rte_eth_null.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright (C) IGEL Co.,Ltd.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of IGEL Co.,Ltd. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#define ETH_NULL_PACKET_SIZE_ARG\t\"size\"\n#define ETH_NULL_PACKET_COPY_ARG\t\"copy\"\n\nstatic unsigned default_packet_size = 64;\nstatic unsigned default_packet_copy;\n\nstatic const char *valid_arguments[] = {\n\tETH_NULL_PACKET_SIZE_ARG,\n\tETH_NULL_PACKET_COPY_ARG,\n\tNULL\n};\n\nstruct pmd_internals;\n\nstruct null_queue {\n\tstruct pmd_internals *internals;\n\n\tstruct rte_mempool *mb_pool;\n\tstruct rte_mbuf *dummy_packet;\n\n\trte_atomic64_t rx_pkts;\n\trte_atomic64_t tx_pkts;\n\trte_atomic64_t err_pkts;\n};\n\nstruct pmd_internals {\n\tunsigned packet_size;\n\tunsigned packet_copy;\n\tunsigned numa_node;\n\n\tunsigned nb_rx_queues;\n\tunsigned nb_tx_queues;\n\n\tstruct null_queue rx_null_queues[1];\n\tstruct null_queue tx_null_queues[1];\n};\n\n\nstatic struct ether_addr eth_addr = { .addr_bytes = {0} };\nstatic const char *drivername = \"Null PMD\";\nstatic struct rte_eth_link pmd_link = {\n\t.link_speed = 10000,\n\t.link_duplex = ETH_LINK_FULL_DUPLEX,\n\t.link_status = 0\n};\n\nstatic uint16_t\neth_null_rx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)\n{\n\tint i;\n\tstruct null_queue *h = q;\n\tunsigned packet_size;\n\n\tif ((q == NULL) || (bufs == NULL))\n\t\treturn 0;\n\n\tpacket_size = h->internals->packet_size;\n\tfor (i = 0; i < nb_bufs; i++) {\n\t\tbufs[i] = rte_pktmbuf_alloc(h->mb_pool);\n\t\tif (!bufs[i])\n\t\t\tbreak;\n\t\tbufs[i]->data_len = (uint16_t)packet_size;\n\t\tbufs[i]->pkt_len = packet_size;\n\t\tbufs[i]->nb_segs = 1;\n\t\tbufs[i]->next = NULL;\n\t}\n\n\trte_atomic64_add(&(h->rx_pkts), i);\n\n\treturn i;\n}\n\nstatic uint16_t\neth_null_copy_rx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)\n{\n\tint i;\n\tstruct null_queue *h = q;\n\tunsigned packet_size;\n\n\tif ((q == NULL) || (bufs == NULL))\n\t\treturn 0;\n\n\tpacket_size = h->internals->packet_size;\n\tfor (i = 0; i < nb_bufs; i++) {\n\t\tbufs[i] = rte_pktmbuf_alloc(h->mb_pool);\n\t\tif (!bufs[i])\n\t\t\tbreak;\n\t\trte_memcpy(rte_pktmbuf_mtod(bufs[i], void *), h->dummy_packet,\n\t\t\t\t\tpacket_size);\n\t\tbufs[i]->data_len = (uint16_t)packet_size;\n\t\tbufs[i]->pkt_len = packet_size;\n\t\tbufs[i]->nb_segs = 1;\n\t\tbufs[i]->next = NULL;\n\t}\n\n\trte_atomic64_add(&(h->rx_pkts), i);\n\n\treturn i;\n}\n\nstatic uint16_t\neth_null_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)\n{\n\tint i;\n\tstruct null_queue *h = q;\n\n\tif ((q == NULL) || (bufs == NULL))\n\t\treturn 0;\n\n\tfor (i = 0; i < nb_bufs; i++)\n\t\trte_pktmbuf_free(bufs[i]);\n\n\trte_atomic64_add(&(h->tx_pkts), i);\n\n\treturn i;\n}\n\nstatic uint16_t\neth_null_copy_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)\n{\n\tint i;\n\tstruct null_queue *h = q;\n\tunsigned packet_size;\n\n\tif ((q == NULL) || (bufs == NULL))\n\t\treturn 0;\n\n\tpacket_size = h->internals->packet_size;\n\tfor (i = 0; i < nb_bufs; i++) {\n\t\trte_memcpy(h->dummy_packet, rte_pktmbuf_mtod(bufs[i], void *),\n\t\t\t\t\tpacket_size);\n\t\trte_pktmbuf_free(bufs[i]);\n\t}\n\n\trte_atomic64_add(&(h->tx_pkts), i);\n\n\treturn i;\n}\n\nstatic int\neth_dev_configure(struct rte_eth_dev *dev __rte_unused) { return 0; }\n\nstatic int\neth_dev_start(struct rte_eth_dev *dev)\n{\n\tif (dev == NULL)\n\t\treturn -EINVAL;\n\n\tdev->data->dev_link.link_status = 1;\n\treturn 0;\n}\n\nstatic void\neth_dev_stop(struct rte_eth_dev *dev)\n{\n\tif (dev == NULL)\n\t\treturn;\n\n\tdev->data->dev_link.link_status = 0;\n}\n\nstatic int\neth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n\t\tuint16_t nb_rx_desc __rte_unused,\n\t\tunsigned int socket_id __rte_unused,\n\t\tconst struct rte_eth_rxconf *rx_conf __rte_unused,\n\t\tstruct rte_mempool *mb_pool)\n{\n\tstruct rte_mbuf *dummy_packet;\n\tstruct pmd_internals *internals;\n\tunsigned packet_size;\n\n\tif ((dev == NULL) || (mb_pool == NULL))\n\t\treturn -EINVAL;\n\n\tif (rx_queue_id != 0)\n\t\treturn -ENODEV;\n\n\tinternals = dev->data->dev_private;\n\tpacket_size = internals->packet_size;\n\n\tinternals->rx_null_queues[rx_queue_id].mb_pool = mb_pool;\n\tdev->data->rx_queues[rx_queue_id] =\n\t\t&internals->rx_null_queues[rx_queue_id];\n\tdummy_packet = rte_zmalloc_socket(NULL,\n\t\t\tpacket_size, 0, internals->numa_node);\n\tif (dummy_packet == NULL)\n\t\treturn -ENOMEM;\n\n\tinternals->rx_null_queues[rx_queue_id].internals = internals;\n\tinternals->rx_null_queues[rx_queue_id].dummy_packet = dummy_packet;\n\n\treturn 0;\n}\n\nstatic int\neth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n\t\tuint16_t nb_tx_desc __rte_unused,\n\t\tunsigned int socket_id __rte_unused,\n\t\tconst struct rte_eth_txconf *tx_conf __rte_unused)\n{\n\tstruct rte_mbuf *dummy_packet;\n\tstruct pmd_internals *internals;\n\tunsigned packet_size;\n\n\tif (dev == NULL)\n\t\treturn -EINVAL;\n\n\tif (tx_queue_id != 0)\n\t\treturn -ENODEV;\n\n\tinternals = dev->data->dev_private;\n\tpacket_size = internals->packet_size;\n\n\tdev->data->tx_queues[tx_queue_id] =\n\t\t&internals->tx_null_queues[tx_queue_id];\n\tdummy_packet = rte_zmalloc_socket(NULL,\n\t\t\tpacket_size, 0, internals->numa_node);\n\tif (dummy_packet == NULL)\n\t\treturn -ENOMEM;\n\n\tinternals->tx_null_queues[tx_queue_id].internals = internals;\n\tinternals->tx_null_queues[tx_queue_id].dummy_packet = dummy_packet;\n\n\treturn 0;\n}\n\n\nstatic void\neth_dev_info(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_dev_info *dev_info)\n{\n\tstruct pmd_internals *internals;\n\n\tif ((dev == NULL) || (dev_info == NULL))\n\t\treturn;\n\n\tinternals = dev->data->dev_private;\n\tdev_info->driver_name = drivername;\n\tdev_info->max_mac_addrs = 1;\n\tdev_info->max_rx_pktlen = (uint32_t)-1;\n\tdev_info->max_rx_queues = (uint16_t)internals->nb_rx_queues;\n\tdev_info->max_tx_queues = (uint16_t)internals->nb_tx_queues;\n\tdev_info->min_rx_bufsize = 0;\n\tdev_info->pci_dev = NULL;\n}\n\nstatic void\neth_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *igb_stats)\n{\n\tunsigned i, num_stats;\n\tunsigned long rx_total = 0, tx_total = 0, tx_err_total = 0;\n\tconst struct pmd_internals *internal;\n\n\tif ((dev == NULL) || (igb_stats == NULL))\n\t\treturn;\n\n\tinternal = dev->data->dev_private;\n\tnum_stats = RTE_MIN((unsigned)RTE_ETHDEV_QUEUE_STAT_CNTRS,\n\t\t\tRTE_MIN(internal->nb_rx_queues,\n\t\t\t\tRTE_DIM(internal->rx_null_queues)));\n\tfor (i = 0; i < num_stats; i++) {\n\t\tigb_stats->q_ipackets[i] =\n\t\t\tinternal->rx_null_queues[i].rx_pkts.cnt;\n\t\trx_total += igb_stats->q_ipackets[i];\n\t}\n\n\tnum_stats = RTE_MIN((unsigned)RTE_ETHDEV_QUEUE_STAT_CNTRS,\n\t\t\tRTE_MIN(internal->nb_tx_queues,\n\t\t\t\tRTE_DIM(internal->tx_null_queues)));\n\tfor (i = 0; i < num_stats; i++) {\n\t\tigb_stats->q_opackets[i] =\n\t\t\tinternal->tx_null_queues[i].tx_pkts.cnt;\n\t\tigb_stats->q_errors[i] =\n\t\t\tinternal->tx_null_queues[i].err_pkts.cnt;\n\t\ttx_total += igb_stats->q_opackets[i];\n\t\ttx_err_total += igb_stats->q_errors[i];\n\t}\n\n\tigb_stats->ipackets = rx_total;\n\tigb_stats->opackets = tx_total;\n\tigb_stats->oerrors = tx_err_total;\n}\n\nstatic void\neth_stats_reset(struct rte_eth_dev *dev)\n{\n\tunsigned i;\n\tstruct pmd_internals *internal;\n\n\tif (dev == NULL)\n\t\treturn;\n\n\tinternal = dev->data->dev_private;\n\tfor (i = 0; i < RTE_DIM(internal->rx_null_queues); i++)\n\t\tinternal->rx_null_queues[i].rx_pkts.cnt = 0;\n\tfor (i = 0; i < RTE_DIM(internal->tx_null_queues); i++) {\n\t\tinternal->tx_null_queues[i].tx_pkts.cnt = 0;\n\t\tinternal->tx_null_queues[i].err_pkts.cnt = 0;\n\t}\n}\n\nstatic struct eth_driver rte_null_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_null_pmd\",\n\t\t.drv_flags = RTE_PCI_DRV_DETACHABLE,\n\t},\n};\n\nstatic void\neth_queue_release(void *q)\n{\n\tstruct null_queue *nq;\n\n\tif (q == NULL)\n\t\treturn;\n\n\tnq = q;\n\trte_free(nq->dummy_packet);\n}\n\nstatic int\neth_link_update(struct rte_eth_dev *dev __rte_unused,\n\t\tint wait_to_complete __rte_unused) { return 0; }\n\nstatic const struct eth_dev_ops ops = {\n\t.dev_start = eth_dev_start,\n\t.dev_stop = eth_dev_stop,\n\t.dev_configure = eth_dev_configure,\n\t.dev_infos_get = eth_dev_info,\n\t.rx_queue_setup = eth_rx_queue_setup,\n\t.tx_queue_setup = eth_tx_queue_setup,\n\t.rx_queue_release = eth_queue_release,\n\t.tx_queue_release = eth_queue_release,\n\t.link_update = eth_link_update,\n\t.stats_get = eth_stats_get,\n\t.stats_reset = eth_stats_reset,\n};\n\nstatic int\neth_dev_null_create(const char *name,\n\t\tconst unsigned numa_node,\n\t\tunsigned packet_size,\n\t\tunsigned packet_copy)\n{\n\tconst unsigned nb_rx_queues = 1;\n\tconst unsigned nb_tx_queues = 1;\n\tstruct rte_eth_dev_data *data = NULL;\n\tstruct rte_pci_device *pci_dev = NULL;\n\tstruct pmd_internals *internals = NULL;\n\tstruct rte_eth_dev *eth_dev = NULL;\n\n\tif (name == NULL)\n\t\treturn -EINVAL;\n\n\tRTE_LOG(INFO, PMD, \"Creating null ethdev on numa socket %u\\n\",\n\t\t\tnuma_node);\n\n\t/* now do all data allocation - for eth_dev structure, dummy pci driver\n\t * and internal (private) data\n\t */\n\tdata = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node);\n\tif (data == NULL)\n\t\tgoto error;\n\n\tpci_dev = rte_zmalloc_socket(name, sizeof(*pci_dev), 0, numa_node);\n\tif (pci_dev == NULL)\n\t\tgoto error;\n\n\tinternals = rte_zmalloc_socket(name, sizeof(*internals), 0, numa_node);\n\tif (internals == NULL)\n\t\tgoto error;\n\n\t/* reserve an ethdev entry */\n\teth_dev = rte_eth_dev_allocate(name, RTE_ETH_DEV_VIRTUAL);\n\tif (eth_dev == NULL)\n\t\tgoto error;\n\n\t/* now put it all together\n\t * - store queue data in internals,\n\t * - store numa_node info in pci_driver\n\t * - point eth_dev_data to internals and pci_driver\n\t * - and point eth_dev structure to new eth_dev_data structure\n\t */\n\t/* NOTE: we'll replace the data element, of originally allocated eth_dev\n\t * so the nulls are local per-process */\n\n\tinternals->nb_rx_queues = nb_rx_queues;\n\tinternals->nb_tx_queues = nb_tx_queues;\n\tinternals->packet_size = packet_size;\n\tinternals->packet_copy = packet_copy;\n\tinternals->numa_node = numa_node;\n\n\tpci_dev->numa_node = numa_node;\n\n\tdata->dev_private = internals;\n\tdata->port_id = eth_dev->data->port_id;\n\tdata->nb_rx_queues = (uint16_t)nb_rx_queues;\n\tdata->nb_tx_queues = (uint16_t)nb_tx_queues;\n\tdata->dev_link = pmd_link;\n\tdata->mac_addrs = ð_addr;\n\tstrncpy(data->name, eth_dev->data->name, strlen(eth_dev->data->name));\n\n\teth_dev->data = data;\n\teth_dev->dev_ops = &ops;\n\teth_dev->pci_dev = pci_dev;\n\teth_dev->driver = &rte_null_pmd;\n\n\t/* finally assign rx and tx ops */\n\tif (packet_copy) {\n\t\teth_dev->rx_pkt_burst = eth_null_copy_rx;\n\t\teth_dev->tx_pkt_burst = eth_null_copy_tx;\n\t} else {\n\t\teth_dev->rx_pkt_burst = eth_null_rx;\n\t\teth_dev->tx_pkt_burst = eth_null_tx;\n\t}\n\n\treturn 0;\n\nerror:\n\trte_free(data);\n\trte_free(pci_dev);\n\trte_free(internals);\n\n\treturn -1;\n}\n\nstatic inline int\nget_packet_size_arg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args)\n{\n\tconst char *a = value;\n\tunsigned *packet_size = extra_args;\n\n\tif ((value == NULL) || (extra_args == NULL))\n\t\treturn -EINVAL;\n\n\t*packet_size = (unsigned)strtoul(a, NULL, 0);\n\tif (*packet_size == UINT_MAX)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic inline int\nget_packet_copy_arg(const char *key __rte_unused,\n\t\tconst char *value, void *extra_args)\n{\n\tconst char *a = value;\n\tunsigned *packet_copy = extra_args;\n\n\tif ((value == NULL) || (extra_args == NULL))\n\t\treturn -EINVAL;\n\n\t*packet_copy = (unsigned)strtoul(a, NULL, 0);\n\tif (*packet_copy == UINT_MAX)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic int\nrte_pmd_null_devinit(const char *name, const char *params)\n{\n\tunsigned numa_node;\n\tunsigned packet_size = default_packet_size;\n\tunsigned packet_copy = default_packet_copy;\n\tstruct rte_kvargs *kvlist = NULL;\n\tint ret;\n\n\tif (name == NULL)\n\t\treturn -EINVAL;\n\n\tRTE_LOG(INFO, PMD, \"Initializing pmd_null for %s\\n\", name);\n\n\tnuma_node = rte_socket_id();\n\n\tif (params != NULL) {\n\t\tkvlist = rte_kvargs_parse(params, valid_arguments);\n\t\tif (kvlist == NULL)\n\t\t\treturn -1;\n\n\t\tif (rte_kvargs_count(kvlist, ETH_NULL_PACKET_SIZE_ARG) == 1) {\n\n\t\t\tret = rte_kvargs_process(kvlist,\n\t\t\t\t\tETH_NULL_PACKET_SIZE_ARG,\n\t\t\t\t\t&get_packet_size_arg, &packet_size);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto free_kvlist;\n\t\t}\n\n\t\tif (rte_kvargs_count(kvlist, ETH_NULL_PACKET_COPY_ARG) == 1) {\n\n\t\t\tret = rte_kvargs_process(kvlist,\n\t\t\t\t\tETH_NULL_PACKET_COPY_ARG,\n\t\t\t\t\t&get_packet_copy_arg, &packet_copy);\n\t\t\tif (ret < 0)\n\t\t\t\tgoto free_kvlist;\n\t\t}\n\t}\n\n\tRTE_LOG(INFO, PMD, \"Configure pmd_null: packet size is %d, \"\n\t\t\t\"packet copy is %s\\n\", packet_size,\n\t\t\tpacket_copy ? \"enabled\" : \"disabled\");\n\n\tret = eth_dev_null_create(name, numa_node, packet_size, packet_copy);\n\nfree_kvlist:\n\tif (kvlist)\n\t\trte_kvargs_free(kvlist);\n\treturn ret;\n}\n\nstatic int\nrte_pmd_null_devuninit(const char *name)\n{\n\tstruct rte_eth_dev *eth_dev = NULL;\n\n\tif (name == NULL)\n\t\treturn -EINVAL;\n\n\tRTE_LOG(INFO, PMD, \"Closing null ethdev on numa socket %u\\n\",\n\t\t\trte_socket_id());\n\n\t/* reserve an ethdev entry */\n\teth_dev = rte_eth_dev_allocated(name);\n\tif (eth_dev == NULL)\n\t\treturn -1;\n\n\trte_free(eth_dev->data->dev_private);\n\trte_free(eth_dev->data);\n\trte_free(eth_dev->pci_dev);\n\n\trte_eth_dev_release_port(eth_dev);\n\n\treturn 0;\n}\n\nstatic struct rte_driver pmd_null_drv = {\n\t.name = \"eth_null\",\n\t.type = PMD_VDEV,\n\t.init = rte_pmd_null_devinit,\n\t.uninit = rte_pmd_null_devuninit,\n};\n\nPMD_REGISTER_DRIVER(pmd_null_drv);\n" }, { "path": "drivers/net/pcap/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# Copyright(c) 2014 6WIND S.A.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_pcap.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_pmd_pcap_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_PCAP) += rte_eth_pcap.c\n\n#\n# Export include files\n#\nSYMLINK-y-include +=\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_PCAP) += lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_PCAP) += lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_PCAP) += lib/librte_kvargs\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/pcap/rte_eth_pcap.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \n\n#define RTE_ETH_PCAP_SNAPSHOT_LEN 65535\n#define RTE_ETH_PCAP_SNAPLEN ETHER_MAX_JUMBO_FRAME_LEN\n#define RTE_ETH_PCAP_PROMISC 1\n#define RTE_ETH_PCAP_TIMEOUT -1\n#define ETH_PCAP_RX_PCAP_ARG \"rx_pcap\"\n#define ETH_PCAP_TX_PCAP_ARG \"tx_pcap\"\n#define ETH_PCAP_RX_IFACE_ARG \"rx_iface\"\n#define ETH_PCAP_TX_IFACE_ARG \"tx_iface\"\n#define ETH_PCAP_IFACE_ARG \"iface\"\n\n#define ETH_PCAP_ARG_MAXLEN\t64\n\nstatic char errbuf[PCAP_ERRBUF_SIZE];\nstatic unsigned char tx_pcap_data[RTE_ETH_PCAP_SNAPLEN];\nstatic struct timeval start_time;\nstatic uint64_t start_cycles;\nstatic uint64_t hz;\n\nstruct pcap_rx_queue {\n\tpcap_t *pcap;\n\tuint8_t in_port;\n\tstruct rte_mempool *mb_pool;\n\tvolatile unsigned long rx_pkts;\n\tvolatile unsigned long rx_bytes;\n\tvolatile unsigned long err_pkts;\n\tchar name[PATH_MAX];\n\tchar type[ETH_PCAP_ARG_MAXLEN];\n};\n\nstruct pcap_tx_queue {\n\tpcap_dumper_t *dumper;\n\tpcap_t *pcap;\n\tvolatile unsigned long tx_pkts;\n\tvolatile unsigned long tx_bytes;\n\tvolatile unsigned long err_pkts;\n\tchar name[PATH_MAX];\n\tchar type[ETH_PCAP_ARG_MAXLEN];\n};\n\nstruct rx_pcaps {\n\tunsigned num_of_rx;\n\tpcap_t *pcaps[RTE_PMD_RING_MAX_RX_RINGS];\n\tconst char *names[RTE_PMD_RING_MAX_RX_RINGS];\n\tconst char *types[RTE_PMD_RING_MAX_RX_RINGS];\n};\n\nstruct tx_pcaps {\n\tunsigned num_of_tx;\n\tpcap_dumper_t *dumpers[RTE_PMD_RING_MAX_TX_RINGS];\n\tpcap_t *pcaps[RTE_PMD_RING_MAX_RX_RINGS];\n\tconst char *names[RTE_PMD_RING_MAX_RX_RINGS];\n\tconst char *types[RTE_PMD_RING_MAX_RX_RINGS];\n};\n\nstruct pmd_internals {\n\tstruct pcap_rx_queue rx_queue[RTE_PMD_RING_MAX_RX_RINGS];\n\tstruct pcap_tx_queue tx_queue[RTE_PMD_RING_MAX_TX_RINGS];\n\tunsigned nb_rx_queues;\n\tunsigned nb_tx_queues;\n\tint if_index;\n\tint single_iface;\n};\n\nconst char *valid_arguments[] = {\n\tETH_PCAP_RX_PCAP_ARG,\n\tETH_PCAP_TX_PCAP_ARG,\n\tETH_PCAP_RX_IFACE_ARG,\n\tETH_PCAP_TX_IFACE_ARG,\n\tETH_PCAP_IFACE_ARG,\n\tNULL\n};\n\nstatic int open_single_tx_pcap(const char *pcap_filename, pcap_dumper_t **dumper);\nstatic int open_single_rx_pcap(const char *pcap_filename, pcap_t **pcap);\nstatic int open_single_iface(const char *iface, pcap_t **pcap);\n\nstatic struct ether_addr eth_addr = { .addr_bytes = { 0, 0, 0, 0x1, 0x2, 0x3 } };\nstatic const char *drivername = \"Pcap PMD\";\nstatic struct rte_eth_link pmd_link = {\n\t\t.link_speed = 10000,\n\t\t.link_duplex = ETH_LINK_FULL_DUPLEX,\n\t\t.link_status = 0\n};\n\nstatic int\neth_pcap_rx_jumbo(struct rte_mempool *mb_pool,\n\t\t struct rte_mbuf *mbuf,\n\t\t const u_char *data,\n\t\t uint16_t data_len)\n{\n\tstruct rte_mbuf *m = mbuf;\n\n\t/* Copy the first segment. */\n\tuint16_t len = rte_pktmbuf_tailroom(mbuf);\n\n\trte_memcpy(rte_pktmbuf_append(mbuf, len), data, len);\n\tdata_len -= len;\n\tdata += len;\n\n\twhile (data_len > 0) {\n\t\t/* Allocate next mbuf and point to that. */\n\t\tm->next = rte_pktmbuf_alloc(mb_pool);\n\n\t\tif (unlikely(!m->next))\n\t\t\treturn -1;\n\n\t\tm = m->next;\n\n\t\t/* Headroom is not needed in chained mbufs. */\n\t\trte_pktmbuf_prepend(m, rte_pktmbuf_headroom(m));\n\t\tm->pkt_len = 0;\n\t\tm->data_len = 0;\n\n\t\t/* Copy next segment. */\n\t\tlen = RTE_MIN(rte_pktmbuf_tailroom(m), data_len);\n\t\trte_memcpy(rte_pktmbuf_append(m, len), data, len);\n\n\t\tmbuf->nb_segs++;\n\t\tdata_len -= len;\n\t\tdata += len;\n\t}\n\n\treturn mbuf->nb_segs;\n}\n\n/* Copy data from mbuf chain to a buffer suitable for writing to a PCAP file. */\nstatic void\neth_pcap_gather_data(unsigned char *data, struct rte_mbuf *mbuf)\n{\n\tuint16_t data_len = 0;\n\n\twhile (mbuf) {\n\t\trte_memcpy(data + data_len, rte_pktmbuf_mtod(mbuf, void *),\n\t\t\t mbuf->data_len);\n\n\t\tdata_len += mbuf->data_len;\n\t\tmbuf = mbuf->next;\n\t}\n}\n\nstatic uint16_t\neth_pcap_rx(void *queue,\n\t\tstruct rte_mbuf **bufs,\n\t\tuint16_t nb_pkts)\n{\n\tunsigned i;\n\tstruct pcap_pkthdr header;\n\tconst u_char *packet;\n\tstruct rte_mbuf *mbuf;\n\tstruct pcap_rx_queue *pcap_q = queue;\n\tuint16_t num_rx = 0;\n\tuint16_t buf_size;\n\tuint32_t rx_bytes = 0;\n\n\tif (unlikely(pcap_q->pcap == NULL || nb_pkts == 0))\n\t\treturn 0;\n\n\t/* Reads the given number of packets from the pcap file one by one\n\t * and copies the packet data into a newly allocated mbuf to return.\n\t */\n\tfor (i = 0; i < nb_pkts; i++) {\n\t\t/* Get the next PCAP packet */\n\t\tpacket = pcap_next(pcap_q->pcap, &header);\n\t\tif (unlikely(packet == NULL))\n\t\t\tbreak;\n\t\telse\n\t\t\tmbuf = rte_pktmbuf_alloc(pcap_q->mb_pool);\n\t\tif (unlikely(mbuf == NULL))\n\t\t\tbreak;\n\n\t\t/* Now get the space available for data in the mbuf */\n\t\tbuf_size = (uint16_t)(rte_pktmbuf_data_room_size(pcap_q->mb_pool) -\n\t\t\t\tRTE_PKTMBUF_HEADROOM);\n\n\t\tif (header.len <= buf_size) {\n\t\t\t/* pcap packet will fit in the mbuf, go ahead and copy */\n\t\t\trte_memcpy(rte_pktmbuf_mtod(mbuf, void *), packet,\n\t\t\t\t\theader.len);\n\t\t\tmbuf->data_len = (uint16_t)header.len;\n\t\t} else {\n\t\t\t/* Try read jumbo frame into multi mbufs. */\n\t\t\tif (unlikely(eth_pcap_rx_jumbo(pcap_q->mb_pool,\n\t\t\t\t\t\t mbuf,\n\t\t\t\t\t\t packet,\n\t\t\t\t\t\t header.len) == -1))\n\t\t\t\tbreak;\n\t\t}\n\n\t\tmbuf->pkt_len = (uint16_t)header.len;\n\t\tmbuf->port = pcap_q->in_port;\n\t\tbufs[num_rx] = mbuf;\n\t\tnum_rx++;\n\t\trx_bytes += header.len;\n\t}\n\tpcap_q->rx_pkts += num_rx;\n\tpcap_q->rx_bytes += rx_bytes;\n\treturn num_rx;\n}\n\nstatic inline void\ncalculate_timestamp(struct timeval *ts) {\n\tuint64_t cycles;\n\tstruct timeval cur_time;\n\n\tcycles = rte_get_timer_cycles() - start_cycles;\n\tcur_time.tv_sec = cycles / hz;\n\tcur_time.tv_usec = (cycles % hz) * 10e6 / hz;\n\ttimeradd(&start_time, &cur_time, ts);\n}\n\n/*\n * Callback to handle writing packets to a pcap file.\n */\nstatic uint16_t\neth_pcap_tx_dumper(void *queue,\n\t\tstruct rte_mbuf **bufs,\n\t\tuint16_t nb_pkts)\n{\n\tunsigned i;\n\tstruct rte_mbuf *mbuf;\n\tstruct pcap_tx_queue *dumper_q = queue;\n\tuint16_t num_tx = 0;\n\tuint32_t tx_bytes = 0;\n\tstruct pcap_pkthdr header;\n\n\tif (dumper_q->dumper == NULL || nb_pkts == 0)\n\t\treturn 0;\n\n\t/* writes the nb_pkts packets to the previously opened pcap file dumper */\n\tfor (i = 0; i < nb_pkts; i++) {\n\t\tmbuf = bufs[i];\n\t\tcalculate_timestamp(&header.ts);\n\t\theader.len = mbuf->pkt_len;\n\t\theader.caplen = header.len;\n\n\t\tif (likely(mbuf->nb_segs == 1)) {\n\t\t\tpcap_dump((u_char *)dumper_q->dumper, &header,\n\t\t\t\t rte_pktmbuf_mtod(mbuf, void*));\n\t\t} else {\n\t\t\tif (mbuf->pkt_len <= ETHER_MAX_JUMBO_FRAME_LEN) {\n\t\t\t\teth_pcap_gather_data(tx_pcap_data, mbuf);\n\t\t\t\tpcap_dump((u_char *)dumper_q->dumper, &header,\n\t\t\t\t\t tx_pcap_data);\n\t\t\t} else {\n\t\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\t\"Dropping PCAP packet. \"\n\t\t\t\t\t\"Size (%d) > max jumbo size (%d).\\n\",\n\t\t\t\t\tmbuf->pkt_len,\n\t\t\t\t\tETHER_MAX_JUMBO_FRAME_LEN);\n\n\t\t\t\trte_pktmbuf_free(mbuf);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\trte_pktmbuf_free(mbuf);\n\t\tnum_tx++;\n\t\ttx_bytes += mbuf->pkt_len;\n\t}\n\n\t/*\n\t * Since there's no place to hook a callback when the forwarding\n\t * process stops and to make sure the pcap file is actually written,\n\t * we flush the pcap dumper within each burst.\n\t */\n\tpcap_dump_flush(dumper_q->dumper);\n\tdumper_q->tx_pkts += num_tx;\n\tdumper_q->tx_bytes += tx_bytes;\n\tdumper_q->err_pkts += nb_pkts - num_tx;\n\treturn num_tx;\n}\n\n/*\n * Callback to handle sending packets through a real NIC.\n */\nstatic uint16_t\neth_pcap_tx(void *queue,\n\t\tstruct rte_mbuf **bufs,\n\t\tuint16_t nb_pkts)\n{\n\tunsigned i;\n\tint ret;\n\tstruct rte_mbuf *mbuf;\n\tstruct pcap_tx_queue *tx_queue = queue;\n\tuint16_t num_tx = 0;\n\tuint32_t tx_bytes = 0;\n\n\tif (unlikely(nb_pkts == 0 || tx_queue->pcap == NULL))\n\t\treturn 0;\n\n\tfor (i = 0; i < nb_pkts; i++) {\n\t\tmbuf = bufs[i];\n\n\t\tif (likely(mbuf->nb_segs == 1)) {\n\t\t\tret = pcap_sendpacket(tx_queue->pcap,\n\t\t\t\t\t rte_pktmbuf_mtod(mbuf, u_char *),\n\t\t\t\t\t mbuf->pkt_len);\n\t\t} else {\n\t\t\tif (mbuf->pkt_len <= ETHER_MAX_JUMBO_FRAME_LEN) {\n\t\t\t\teth_pcap_gather_data(tx_pcap_data, mbuf);\n\t\t\t\tret = pcap_sendpacket(tx_queue->pcap,\n\t\t\t\t\t\t tx_pcap_data,\n\t\t\t\t\t\t mbuf->pkt_len);\n\t\t\t} else {\n\t\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\t\"Dropping PCAP packet. \"\n\t\t\t\t\t\"Size (%d) > max jumbo size (%d).\\n\",\n\t\t\t\t\tmbuf->pkt_len,\n\t\t\t\t\tETHER_MAX_JUMBO_FRAME_LEN);\n\n\t\t\t\trte_pktmbuf_free(mbuf);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tif (unlikely(ret != 0))\n\t\t\tbreak;\n\t\tnum_tx++;\n\t\ttx_bytes += mbuf->pkt_len;\n\t\trte_pktmbuf_free(mbuf);\n\t}\n\n\ttx_queue->tx_pkts += num_tx;\n\ttx_queue->tx_bytes += tx_bytes;\n\ttx_queue->err_pkts += nb_pkts - num_tx;\n\treturn num_tx;\n}\n\nstatic int\neth_dev_start(struct rte_eth_dev *dev)\n{\n\tunsigned i;\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\tstruct pcap_tx_queue *tx;\n\tstruct pcap_rx_queue *rx;\n\n\t/* Special iface case. Single pcap is open and shared between tx/rx. */\n\tif (internals->single_iface) {\n\t\ttx = &internals->tx_queue[0];\n\t\trx = &internals->rx_queue[0];\n\n\t\tif (!tx->pcap && strcmp(tx->type, ETH_PCAP_IFACE_ARG) == 0) {\n\t\t\tif (open_single_iface(tx->name, &tx->pcap) < 0)\n\t\t\t\treturn -1;\n\t\t\trx->pcap = tx->pcap;\n\t\t}\n\t\tgoto status_up;\n\t}\n\n\t/* If not open already, open tx pcaps/dumpers */\n\tfor (i = 0; i < internals->nb_tx_queues; i++) {\n\t\ttx = &internals->tx_queue[i];\n\n\t\tif (!tx->dumper && strcmp(tx->type, ETH_PCAP_TX_PCAP_ARG) == 0) {\n\t\t\tif (open_single_tx_pcap(tx->name, &tx->dumper) < 0)\n\t\t\t\treturn -1;\n\t\t}\n\n\t\telse if (!tx->pcap && strcmp(tx->type, ETH_PCAP_TX_IFACE_ARG) == 0) {\n\t\t\tif (open_single_iface(tx->name, &tx->pcap) < 0)\n\t\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* If not open already, open rx pcaps */\n\tfor (i = 0; i < internals->nb_rx_queues; i++) {\n\t\trx = &internals->rx_queue[i];\n\n\t\tif (rx->pcap != NULL)\n\t\t\tcontinue;\n\n\t\tif (strcmp(rx->type, ETH_PCAP_RX_PCAP_ARG) == 0) {\n\t\t\tif (open_single_rx_pcap(rx->name, &rx->pcap) < 0)\n\t\t\t\treturn -1;\n\t\t}\n\n\t\telse if (strcmp(rx->type, ETH_PCAP_RX_IFACE_ARG) == 0) {\n\t\t\tif (open_single_iface(rx->name, &rx->pcap) < 0)\n\t\t\t\treturn -1;\n\t\t}\n\t}\n\nstatus_up:\n\n\tdev->data->dev_link.link_status = 1;\n\treturn 0;\n}\n\n/*\n * This function gets called when the current port gets stopped.\n * Is the only place for us to close all the tx streams dumpers.\n * If not called the dumpers will be flushed within each tx burst.\n */\nstatic void\neth_dev_stop(struct rte_eth_dev *dev)\n{\n\tunsigned i;\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\tstruct pcap_tx_queue *tx;\n\tstruct pcap_rx_queue *rx;\n\n\t/* Special iface case. Single pcap is open and shared between tx/rx. */\n\tif (internals->single_iface) {\n\t\ttx = &internals->tx_queue[0];\n\t\trx = &internals->rx_queue[0];\n\t\tpcap_close(tx->pcap);\n\t\ttx->pcap = NULL;\n\t\trx->pcap = NULL;\n\t\tgoto status_down;\n\t}\n\n\tfor (i = 0; i < internals->nb_tx_queues; i++) {\n\t\ttx = &internals->tx_queue[i];\n\n\t\tif (tx->dumper != NULL) {\n\t\t\tpcap_dump_close(tx->dumper);\n\t\t\ttx->dumper = NULL;\n\t\t}\n\n\t\tif (tx->pcap != NULL) {\n\t\t\tpcap_close(tx->pcap);\n\t\t\ttx->pcap = NULL;\n\t\t}\n\t}\n\n\tfor (i = 0; i < internals->nb_rx_queues; i++) {\n\t\trx = &internals->rx_queue[i];\n\n\t\tif (rx->pcap != NULL) {\n\t\t\tpcap_close(rx->pcap);\n\t\t\trx->pcap = NULL;\n\t\t}\n\t}\n\nstatus_down:\n\tdev->data->dev_link.link_status = 0;\n}\n\nstatic int\neth_dev_configure(struct rte_eth_dev *dev __rte_unused)\n{\n\treturn 0;\n}\n\nstatic void\neth_dev_info(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_dev_info *dev_info)\n{\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\tdev_info->driver_name = drivername;\n\tdev_info->if_index = internals->if_index;\n\tdev_info->max_mac_addrs = 1;\n\tdev_info->max_rx_pktlen = (uint32_t) -1;\n\tdev_info->max_rx_queues = (uint16_t)internals->nb_rx_queues;\n\tdev_info->max_tx_queues = (uint16_t)internals->nb_tx_queues;\n\tdev_info->min_rx_bufsize = 0;\n\tdev_info->pci_dev = NULL;\n}\n\nstatic void\neth_stats_get(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_stats *igb_stats)\n{\n\tunsigned i;\n\tunsigned long rx_packets_total = 0, rx_bytes_total = 0;\n\tunsigned long tx_packets_total = 0, tx_bytes_total = 0;\n\tunsigned long tx_packets_err_total = 0;\n\tconst struct pmd_internals *internal = dev->data->dev_private;\n\n\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS && i < internal->nb_rx_queues;\n\t\t\ti++) {\n\t\tigb_stats->q_ipackets[i] = internal->rx_queue[i].rx_pkts;\n\t\tigb_stats->q_ibytes[i] = internal->rx_queue[i].rx_bytes;\n\t\trx_packets_total += igb_stats->q_ipackets[i];\n\t\trx_bytes_total += igb_stats->q_ibytes[i];\n\t}\n\n\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS && i < internal->nb_tx_queues;\n\t\t\ti++) {\n\t\tigb_stats->q_opackets[i] = internal->tx_queue[i].tx_pkts;\n\t\tigb_stats->q_obytes[i] = internal->tx_queue[i].tx_bytes;\n\t\tigb_stats->q_errors[i] = internal->tx_queue[i].err_pkts;\n\t\ttx_packets_total += igb_stats->q_opackets[i];\n\t\ttx_bytes_total += igb_stats->q_obytes[i];\n\t\ttx_packets_err_total += igb_stats->q_errors[i];\n\t}\n\n\tigb_stats->ipackets = rx_packets_total;\n\tigb_stats->ibytes = rx_bytes_total;\n\tigb_stats->opackets = tx_packets_total;\n\tigb_stats->obytes = tx_bytes_total;\n\tigb_stats->oerrors = tx_packets_err_total;\n}\n\nstatic void\neth_stats_reset(struct rte_eth_dev *dev)\n{\n\tunsigned i;\n\tstruct pmd_internals *internal = dev->data->dev_private;\n\tfor (i = 0; i < internal->nb_rx_queues; i++) {\n\t\tinternal->rx_queue[i].rx_pkts = 0;\n\t\tinternal->rx_queue[i].rx_bytes = 0;\n\t}\n\tfor (i = 0; i < internal->nb_tx_queues; i++) {\n\t\tinternal->tx_queue[i].tx_pkts = 0;\n\t\tinternal->tx_queue[i].tx_bytes = 0;\n\t\tinternal->tx_queue[i].err_pkts = 0;\n\t}\n}\n\nstatic void\neth_dev_close(struct rte_eth_dev *dev __rte_unused)\n{\n}\n\nstatic void\neth_queue_release(void *q __rte_unused)\n{\n}\n\nstatic int\neth_link_update(struct rte_eth_dev *dev __rte_unused,\n\t\tint wait_to_complete __rte_unused)\n{\n\treturn 0;\n}\n\nstatic int\neth_rx_queue_setup(struct rte_eth_dev *dev,\n\t\tuint16_t rx_queue_id,\n\t\tuint16_t nb_rx_desc __rte_unused,\n\t\tunsigned int socket_id __rte_unused,\n\t\tconst struct rte_eth_rxconf *rx_conf __rte_unused,\n\t\tstruct rte_mempool *mb_pool)\n{\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\tstruct pcap_rx_queue *pcap_q = &internals->rx_queue[rx_queue_id];\n\tpcap_q->mb_pool = mb_pool;\n\tdev->data->rx_queues[rx_queue_id] = pcap_q;\n\tpcap_q->in_port = dev->data->port_id;\n\treturn 0;\n}\n\nstatic int\neth_tx_queue_setup(struct rte_eth_dev *dev,\n\t\tuint16_t tx_queue_id,\n\t\tuint16_t nb_tx_desc __rte_unused,\n\t\tunsigned int socket_id __rte_unused,\n\t\tconst struct rte_eth_txconf *tx_conf __rte_unused)\n{\n\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\tdev->data->tx_queues[tx_queue_id] = &internals->tx_queue[tx_queue_id];\n\treturn 0;\n}\n\nstatic const struct eth_dev_ops ops = {\n\t.dev_start = eth_dev_start,\n\t.dev_stop =\teth_dev_stop,\n\t.dev_close = eth_dev_close,\n\t.dev_configure = eth_dev_configure,\n\t.dev_infos_get = eth_dev_info,\n\t.rx_queue_setup = eth_rx_queue_setup,\n\t.tx_queue_setup = eth_tx_queue_setup,\n\t.rx_queue_release = eth_queue_release,\n\t.tx_queue_release = eth_queue_release,\n\t.link_update = eth_link_update,\n\t.stats_get = eth_stats_get,\n\t.stats_reset = eth_stats_reset,\n};\n\nstatic struct eth_driver rte_pcap_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_pcap_pmd\",\n\t\t.drv_flags = RTE_PCI_DRV_DETACHABLE,\n\t},\n};\n\n/*\n * Function handler that opens the pcap file for reading a stores a\n * reference of it for use it later on.\n */\nstatic int\nopen_rx_pcap(const char *key, const char *value, void *extra_args)\n{\n\tunsigned i;\n\tconst char *pcap_filename = value;\n\tstruct rx_pcaps *pcaps = extra_args;\n\tpcap_t *pcap = NULL;\n\n\tfor (i = 0; i < pcaps->num_of_rx; i++) {\n\t\tif (open_single_rx_pcap(pcap_filename, &pcap) < 0)\n\t\t\treturn -1;\n\n\t\tpcaps->pcaps[i] = pcap;\n\t\tpcaps->names[i] = pcap_filename;\n\t\tpcaps->types[i] = key;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nopen_single_rx_pcap(const char *pcap_filename, pcap_t **pcap)\n{\n\tif ((*pcap = pcap_open_offline(pcap_filename, errbuf)) == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"Couldn't open %s: %s\\n\", pcap_filename, errbuf);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/*\n * Opens a pcap file for writing and stores a reference to it\n * for use it later on.\n */\nstatic int\nopen_tx_pcap(const char *key, const char *value, void *extra_args)\n{\n\tunsigned i;\n\tconst char *pcap_filename = value;\n\tstruct tx_pcaps *dumpers = extra_args;\n\tpcap_dumper_t *dumper;\n\n\tfor (i = 0; i < dumpers->num_of_tx; i++) {\n\t\tif (open_single_tx_pcap(pcap_filename, &dumper) < 0)\n\t\t\treturn -1;\n\n\t\tdumpers->dumpers[i] = dumper;\n\t\tdumpers->names[i] = pcap_filename;\n\t\tdumpers->types[i] = key;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nopen_single_tx_pcap(const char *pcap_filename, pcap_dumper_t **dumper)\n{\n\tpcap_t *tx_pcap;\n\t/*\n\t * We need to create a dummy empty pcap_t to use it\n\t * with pcap_dump_open(). We create big enough an Ethernet\n\t * pcap holder.\n\t */\n\n\tif ((tx_pcap = pcap_open_dead(DLT_EN10MB, RTE_ETH_PCAP_SNAPSHOT_LEN))\n\t\t\t== NULL) {\n\t\tRTE_LOG(ERR, PMD, \"Couldn't create dead pcap\\n\");\n\t\treturn -1;\n\t}\n\n\t/* The dumper is created using the previous pcap_t reference */\n\tif ((*dumper = pcap_dump_open(tx_pcap, pcap_filename)) == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"Couldn't open %s for writing.\\n\", pcap_filename);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/*\n * pcap_open_live wrapper function\n */\nstatic inline int\nopen_iface_live(const char *iface, pcap_t **pcap) {\n\t*pcap = pcap_open_live(iface, RTE_ETH_PCAP_SNAPLEN,\n\t\t\tRTE_ETH_PCAP_PROMISC, RTE_ETH_PCAP_TIMEOUT, errbuf);\n\n\tif (*pcap == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"Couldn't open %s: %s\\n\", iface, errbuf);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/*\n * Opens an interface for reading and writing\n */\nstatic inline int\nopen_rx_tx_iface(const char *key, const char *value, void *extra_args)\n{\n\tconst char *iface = value;\n\tstruct rx_pcaps *pcaps = extra_args;\n\tpcap_t *pcap = NULL;\n\n\tif (open_single_iface(iface, &pcap) < 0)\n\t\treturn -1;\n\n\tpcaps->pcaps[0] = pcap;\n\tpcaps->names[0] = iface;\n\tpcaps->types[0] = key;\n\n\treturn 0;\n}\n\n/*\n * Opens a NIC for reading packets from it\n */\nstatic inline int\nopen_rx_iface(const char *key, const char *value, void *extra_args)\n{\n\tunsigned i;\n\tconst char *iface = value;\n\tstruct rx_pcaps *pcaps = extra_args;\n\tpcap_t *pcap = NULL;\n\n\tfor (i = 0; i < pcaps->num_of_rx; i++) {\n\t\tif (open_single_iface(iface, &pcap) < 0)\n\t\t\treturn -1;\n\t\tpcaps->pcaps[i] = pcap;\n\t\tpcaps->names[i] = iface;\n\t\tpcaps->types[i] = key;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Opens a NIC for writing packets to it\n */\nstatic int\nopen_tx_iface(const char *key, const char *value, void *extra_args)\n{\n\tunsigned i;\n\tconst char *iface = value;\n\tstruct tx_pcaps *pcaps = extra_args;\n\tpcap_t *pcap;\n\n\tfor (i = 0; i < pcaps->num_of_tx; i++) {\n\t\tif (open_single_iface(iface, &pcap) < 0)\n\t\t\treturn -1;\n\t\tpcaps->pcaps[i] = pcap;\n\t\tpcaps->names[i] = iface;\n\t\tpcaps->types[i] = key;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nopen_single_iface(const char *iface, pcap_t **pcap)\n{\n\tif (open_iface_live(iface, pcap) < 0) {\n\t\tRTE_LOG(ERR, PMD, \"Couldn't open interface %s\\n\", iface);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_pmd_init_internals(const char *name, const unsigned nb_rx_queues,\n\t\tconst unsigned nb_tx_queues,\n\t\tconst unsigned numa_node,\n\t\tstruct pmd_internals **internals,\n\t\tstruct rte_eth_dev **eth_dev,\n\t\tstruct rte_kvargs *kvlist)\n{\n\tstruct rte_eth_dev_data *data = NULL;\n\tstruct rte_pci_device *pci_dev = NULL;\n\tunsigned k_idx;\n\tstruct rte_kvargs_pair *pair = NULL;\n\n\tfor (k_idx = 0; k_idx < kvlist->count; k_idx++) {\n\t\tpair = &kvlist->pairs[k_idx];\n\t\tif (strstr(pair->key, ETH_PCAP_IFACE_ARG) != NULL)\n\t\t\tbreak;\n\t}\n\n\tRTE_LOG(INFO, PMD,\n\t\t\t\"Creating pcap-backed ethdev on numa socket %u\\n\", numa_node);\n\n\t/* now do all data allocation - for eth_dev structure, dummy pci driver\n\t * and internal (private) data\n\t */\n\tdata = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node);\n\tif (data == NULL)\n\t\tgoto error;\n\n\tpci_dev = rte_zmalloc_socket(name, sizeof(*pci_dev), 0, numa_node);\n\tif (pci_dev == NULL)\n\t\tgoto error;\n\n\t*internals = rte_zmalloc_socket(name, sizeof(**internals), 0, numa_node);\n\tif (*internals == NULL)\n\t\tgoto error;\n\n\t/* reserve an ethdev entry */\n\t*eth_dev = rte_eth_dev_allocate(name, RTE_ETH_DEV_VIRTUAL);\n\tif (*eth_dev == NULL)\n\t\tgoto error;\n\n\t/* check length of device name */\n\tif ((strlen((*eth_dev)->data->name) + 1) > sizeof(data->name))\n\t\tgoto error;\n\n\t/* now put it all together\n\t * - store queue data in internals,\n\t * - store numa_node info in pci_driver\n\t * - point eth_dev_data to internals and pci_driver\n\t * - and point eth_dev structure to new eth_dev_data structure\n\t */\n\t/* NOTE: we'll replace the data element, of originally allocated eth_dev\n\t * so the rings are local per-process */\n\n\t(*internals)->nb_rx_queues = nb_rx_queues;\n\t(*internals)->nb_tx_queues = nb_tx_queues;\n\n\tif (pair == NULL)\n\t\t(*internals)->if_index = 0;\n\telse\n\t\t(*internals)->if_index = if_nametoindex(pair->value);\n\n\tpci_dev->numa_node = numa_node;\n\n\tdata->dev_private = *internals;\n\tdata->port_id = (*eth_dev)->data->port_id;\n\tsnprintf(data->name, sizeof(data->name), \"%s\", (*eth_dev)->data->name);\n\tdata->nb_rx_queues = (uint16_t)nb_rx_queues;\n\tdata->nb_tx_queues = (uint16_t)nb_tx_queues;\n\tdata->dev_link = pmd_link;\n\tdata->mac_addrs = ð_addr;\n\tstrncpy(data->name,\n\t\t(*eth_dev)->data->name, strlen((*eth_dev)->data->name));\n\n\t(*eth_dev)->data = data;\n\t(*eth_dev)->dev_ops = &ops;\n\t(*eth_dev)->pci_dev = pci_dev;\n\t(*eth_dev)->driver = &rte_pcap_pmd;\n\n\treturn 0;\n\nerror:\n\trte_free(data);\n\trte_free(pci_dev);\n\trte_free(*internals);\n\n\treturn -1;\n}\n\nstatic int\nrte_eth_from_pcaps_n_dumpers(const char *name,\n\t\tstruct rx_pcaps *rx_queues,\n\t\tconst unsigned nb_rx_queues,\n\t\tstruct tx_pcaps *tx_queues,\n\t\tconst unsigned nb_tx_queues,\n\t\tconst unsigned numa_node,\n\t\tstruct rte_kvargs *kvlist)\n{\n\tstruct pmd_internals *internals = NULL;\n\tstruct rte_eth_dev *eth_dev = NULL;\n\tunsigned i;\n\n\t/* do some parameter checking */\n\tif (rx_queues == NULL && nb_rx_queues > 0)\n\t\treturn -1;\n\tif (tx_queues == NULL && nb_tx_queues > 0)\n\t\treturn -1;\n\n\tif (rte_pmd_init_internals(name, nb_rx_queues, nb_tx_queues, numa_node,\n\t\t\t&internals, ð_dev, kvlist) < 0)\n\t\treturn -1;\n\n\tfor (i = 0; i < nb_rx_queues; i++) {\n\t\tinternals->rx_queue[i].pcap = rx_queues->pcaps[i];\n\t\tsnprintf(internals->rx_queue[i].name,\n\t\t\tsizeof(internals->rx_queue[i].name), \"%s\",\n\t\t\trx_queues->names[i]);\n\t\tsnprintf(internals->rx_queue[i].type,\n\t\t\tsizeof(internals->rx_queue[i].type), \"%s\",\n\t\t\trx_queues->types[i]);\n\t}\n\tfor (i = 0; i < nb_tx_queues; i++) {\n\t\tinternals->tx_queue[i].dumper = tx_queues->dumpers[i];\n\t\tsnprintf(internals->tx_queue[i].name,\n\t\t\tsizeof(internals->tx_queue[i].name), \"%s\",\n\t\t\ttx_queues->names[i]);\n\t\tsnprintf(internals->tx_queue[i].type,\n\t\t\tsizeof(internals->tx_queue[i].type), \"%s\",\n\t\t\ttx_queues->types[i]);\n\t}\n\n\t/* using multiple pcaps/interfaces */\n\tinternals->single_iface = 0;\n\n\teth_dev->rx_pkt_burst = eth_pcap_rx;\n\teth_dev->tx_pkt_burst = eth_pcap_tx_dumper;\n\n\treturn 0;\n}\n\nstatic int\nrte_eth_from_pcaps(const char *name,\n\t\tstruct rx_pcaps *rx_queues,\n\t\tconst unsigned nb_rx_queues,\n\t\tstruct tx_pcaps *tx_queues,\n\t\tconst unsigned nb_tx_queues,\n\t\tconst unsigned numa_node,\n\t\tstruct rte_kvargs *kvlist,\n\t\tint single_iface)\n{\n\tstruct pmd_internals *internals = NULL;\n\tstruct rte_eth_dev *eth_dev = NULL;\n\tunsigned i;\n\n\t/* do some parameter checking */\n\tif (rx_queues == NULL && nb_rx_queues > 0)\n\t\treturn -1;\n\tif (tx_queues == NULL && nb_tx_queues > 0)\n\t\treturn -1;\n\n\tif (rte_pmd_init_internals(name, nb_rx_queues, nb_tx_queues, numa_node,\n\t\t\t&internals, ð_dev, kvlist) < 0)\n\t\treturn -1;\n\n\tfor (i = 0; i < nb_rx_queues; i++) {\n\t\tinternals->rx_queue[i].pcap = rx_queues->pcaps[i];\n\t\tsnprintf(internals->rx_queue[i].name,\n\t\t\tsizeof(internals->rx_queue[i].name), \"%s\",\n\t\t\trx_queues->names[i]);\n\t\tsnprintf(internals->rx_queue[i].type,\n\t\t\tsizeof(internals->rx_queue[i].type), \"%s\",\n\t\t\trx_queues->types[i]);\n\t}\n\tfor (i = 0; i < nb_tx_queues; i++) {\n\t\tinternals->tx_queue[i].dumper = tx_queues->dumpers[i];\n\t\tsnprintf(internals->tx_queue[i].name,\n\t\t\tsizeof(internals->tx_queue[i].name), \"%s\",\n\t\t\ttx_queues->names[i]);\n\t\tsnprintf(internals->tx_queue[i].type,\n\t\t\tsizeof(internals->tx_queue[i].type), \"%s\",\n\t\t\ttx_queues->types[i]);\n\t}\n\n\t/* store wether we are using a single interface for rx/tx or not */\n\tinternals->single_iface = single_iface;\n\n\teth_dev->rx_pkt_burst = eth_pcap_rx;\n\teth_dev->tx_pkt_burst = eth_pcap_tx;\n\n\treturn 0;\n}\n\n\nstatic int\nrte_pmd_pcap_devinit(const char *name, const char *params)\n{\n\tunsigned numa_node, using_dumpers = 0;\n\tint ret;\n\tstruct rte_kvargs *kvlist;\n\tstruct rx_pcaps pcaps;\n\tstruct tx_pcaps dumpers;\n\n\tRTE_LOG(INFO, PMD, \"Initializing pmd_pcap for %s\\n\", name);\n\n\tnuma_node = rte_socket_id();\n\n\tgettimeofday(&start_time, NULL);\n\tstart_cycles = rte_get_timer_cycles();\n\thz = rte_get_timer_hz();\n\n\tkvlist = rte_kvargs_parse(params, valid_arguments);\n\tif (kvlist == NULL)\n\t\treturn -1;\n\n\t/*\n\t * If iface argument is passed we open the NICs and use them for\n\t * reading / writing\n\t */\n\tif (rte_kvargs_count(kvlist, ETH_PCAP_IFACE_ARG) == 1) {\n\n\t\tret = rte_kvargs_process(kvlist, ETH_PCAP_IFACE_ARG,\n\t\t\t\t&open_rx_tx_iface, &pcaps);\n\t\tif (ret < 0)\n\t\t\tgoto free_kvlist;\n\t\tdumpers.pcaps[0] = pcaps.pcaps[0];\n\t\tdumpers.names[0] = pcaps.names[0];\n\t\tdumpers.types[0] = pcaps.types[0];\n\t\tret = rte_eth_from_pcaps(name, &pcaps, 1, &dumpers, 1,\n\t\t\t\tnuma_node, kvlist, 1);\n\t\tgoto free_kvlist;\n\t}\n\n\t/*\n\t * We check whether we want to open a RX stream from a real NIC or a\n\t * pcap file\n\t */\n\tif ((pcaps.num_of_rx = rte_kvargs_count(kvlist, ETH_PCAP_RX_PCAP_ARG))) {\n\t\tret = rte_kvargs_process(kvlist, ETH_PCAP_RX_PCAP_ARG,\n\t\t\t\t&open_rx_pcap, &pcaps);\n\t} else {\n\t\tpcaps.num_of_rx = rte_kvargs_count(kvlist,\n\t\t\t\tETH_PCAP_RX_IFACE_ARG);\n\t\tret = rte_kvargs_process(kvlist, ETH_PCAP_RX_IFACE_ARG,\n\t\t\t\t&open_rx_iface, &pcaps);\n\t}\n\n\tif (ret < 0)\n\t\tgoto free_kvlist;\n\n\t/*\n\t * We check whether we want to open a TX stream to a real NIC or a\n\t * pcap file\n\t */\n\tif ((dumpers.num_of_tx = rte_kvargs_count(kvlist,\n\t\t\tETH_PCAP_TX_PCAP_ARG))) {\n\t\tret = rte_kvargs_process(kvlist, ETH_PCAP_TX_PCAP_ARG,\n\t\t\t\t&open_tx_pcap, &dumpers);\n\t\tusing_dumpers = 1;\n\t} else {\n\t\tdumpers.num_of_tx = rte_kvargs_count(kvlist,\n\t\t\t\tETH_PCAP_TX_IFACE_ARG);\n\t\tret = rte_kvargs_process(kvlist, ETH_PCAP_TX_IFACE_ARG,\n\t\t\t\t&open_tx_iface, &dumpers);\n\t}\n\n\tif (ret < 0)\n\t\tgoto free_kvlist;\n\n\tif (using_dumpers)\n\t\tret = rte_eth_from_pcaps_n_dumpers(name, &pcaps, pcaps.num_of_rx,\n\t\t\t\t&dumpers, dumpers.num_of_tx, numa_node, kvlist);\n\telse\n\t\tret = rte_eth_from_pcaps(name, &pcaps, pcaps.num_of_rx, &dumpers,\n\t\t\tdumpers.num_of_tx, numa_node, kvlist, 0);\n\nfree_kvlist:\n\trte_kvargs_free(kvlist);\n\treturn ret;\n}\n\nstatic int\nrte_pmd_pcap_devuninit(const char *name)\n{\n\tstruct rte_eth_dev *eth_dev = NULL;\n\n\tRTE_LOG(INFO, PMD, \"Closing pcap ethdev on numa socket %u\\n\",\n\t\t\trte_socket_id());\n\n\tif (name == NULL)\n\t\treturn -1;\n\n\t/* reserve an ethdev entry */\n\teth_dev = rte_eth_dev_allocated(name);\n\tif (eth_dev == NULL)\n\t\treturn -1;\n\n\trte_free(eth_dev->data->dev_private);\n\trte_free(eth_dev->data);\n\trte_free(eth_dev->pci_dev);\n\n\trte_eth_dev_release_port(eth_dev);\n\n\treturn 0;\n}\n\nstatic struct rte_driver pmd_pcap_drv = {\n\t.name = \"eth_pcap\",\n\t.type = PMD_VDEV,\n\t.init = rte_pmd_pcap_devinit,\n\t.uninit = rte_pmd_pcap_devuninit,\n};\n\nPMD_REGISTER_DRIVER(pmd_pcap_drv);\n" }, { "path": "drivers/net/ring/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_ring.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_eth_ring_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_RING) += rte_eth_ring.c\n\n#\n# Export include files\n#\nSYMLINK-y-include += rte_eth_ring.h\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_RING) += lib/librte_eal lib/librte_ring\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_RING) += lib/librte_mbuf lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_RING) += lib/librte_kvargs\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/ring/rte_eth_ring.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"rte_eth_ring.h\"\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define ETH_RING_NUMA_NODE_ACTION_ARG\t\"nodeaction\"\n#define ETH_RING_ACTION_CREATE\t\t\"CREATE\"\n#define ETH_RING_ACTION_ATTACH\t\t\"ATTACH\"\n\nstatic const char *ring_ethdev_driver_name = \"Ring PMD\";\n\nstatic const char *valid_arguments[] = {\n\tETH_RING_NUMA_NODE_ACTION_ARG,\n\tNULL\n};\n\nstruct ring_queue {\n\tstruct rte_ring *rng;\n\trte_atomic64_t rx_pkts;\n\trte_atomic64_t tx_pkts;\n\trte_atomic64_t err_pkts;\n};\n\nstruct pmd_internals {\n\tunsigned nb_rx_queues;\n\tunsigned nb_tx_queues;\n\n\tstruct ring_queue rx_ring_queues[RTE_PMD_RING_MAX_RX_RINGS];\n\tstruct ring_queue tx_ring_queues[RTE_PMD_RING_MAX_TX_RINGS];\n\n\tstruct ether_addr address;\n};\n\n\nstatic const char *drivername = \"Rings PMD\";\nstatic struct rte_eth_link pmd_link = {\n\t\t.link_speed = 10000,\n\t\t.link_duplex = ETH_LINK_FULL_DUPLEX,\n\t\t.link_status = 0\n};\n\nstatic uint16_t\neth_ring_rx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)\n{\n\tvoid **ptrs = (void *)&bufs[0];\n\tstruct ring_queue *r = q;\n\tconst uint16_t nb_rx = (uint16_t)rte_ring_dequeue_burst(r->rng,\n\t\t\tptrs, nb_bufs);\n\tif (r->rng->flags & RING_F_SC_DEQ)\n\t\tr->rx_pkts.cnt += nb_rx;\n\telse\n\t\trte_atomic64_add(&(r->rx_pkts), nb_rx);\n\treturn nb_rx;\n}\n\nstatic uint16_t\neth_ring_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs)\n{\n\tvoid **ptrs = (void *)&bufs[0];\n\tstruct ring_queue *r = q;\n\tconst uint16_t nb_tx = (uint16_t)rte_ring_enqueue_burst(r->rng,\n\t\t\tptrs, nb_bufs);\n\tif (r->rng->flags & RING_F_SP_ENQ) {\n\t\tr->tx_pkts.cnt += nb_tx;\n\t\tr->err_pkts.cnt += nb_bufs - nb_tx;\n\t} else {\n\t\trte_atomic64_add(&(r->tx_pkts), nb_tx);\n\t\trte_atomic64_add(&(r->err_pkts), nb_bufs - nb_tx);\n\t}\n\treturn nb_tx;\n}\n\nstatic int\neth_dev_configure(struct rte_eth_dev *dev __rte_unused) { return 0; }\n\nstatic int\neth_dev_start(struct rte_eth_dev *dev)\n{\n\tdev->data->dev_link.link_status = 1;\n\treturn 0;\n}\n\nstatic void\neth_dev_stop(struct rte_eth_dev *dev)\n{\n\tdev->data->dev_link.link_status = 0;\n}\n\nstatic int\neth_dev_set_link_down(struct rte_eth_dev *dev)\n{\n\tdev->data->dev_link.link_status = 0;\n\treturn 0;\n}\n\nstatic int\neth_dev_set_link_up(struct rte_eth_dev *dev)\n{\n\tdev->data->dev_link.link_status = 1;\n\treturn 0;\n}\n\nstatic int\neth_rx_queue_setup(struct rte_eth_dev *dev,uint16_t rx_queue_id,\n\t\t\t\t uint16_t nb_rx_desc __rte_unused,\n\t\t\t\t unsigned int socket_id __rte_unused,\n\t\t\t\t const struct rte_eth_rxconf *rx_conf __rte_unused,\n\t\t\t\t struct rte_mempool *mb_pool __rte_unused)\n{\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\tdev->data->rx_queues[rx_queue_id] = &internals->rx_ring_queues[rx_queue_id];\n\treturn 0;\n}\n\nstatic int\neth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n\t\t\t\t uint16_t nb_tx_desc __rte_unused,\n\t\t\t\t unsigned int socket_id __rte_unused,\n\t\t\t\t const struct rte_eth_txconf *tx_conf __rte_unused)\n{\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\tdev->data->tx_queues[tx_queue_id] = &internals->tx_ring_queues[tx_queue_id];\n\treturn 0;\n}\n\n\nstatic void\neth_dev_info(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_dev_info *dev_info)\n{\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\tdev_info->driver_name = drivername;\n\tdev_info->max_mac_addrs = 1;\n\tdev_info->max_rx_pktlen = (uint32_t)-1;\n\tdev_info->max_rx_queues = (uint16_t)internals->nb_rx_queues;\n\tdev_info->max_tx_queues = (uint16_t)internals->nb_tx_queues;\n\tdev_info->min_rx_bufsize = 0;\n\tdev_info->pci_dev = NULL;\n}\n\nstatic void\neth_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *igb_stats)\n{\n\tunsigned i;\n\tunsigned long rx_total = 0, tx_total = 0, tx_err_total = 0;\n\tconst struct pmd_internals *internal = dev->data->dev_private;\n\n\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS &&\n\t\t\ti < internal->nb_rx_queues; i++) {\n\t\tigb_stats->q_ipackets[i] = internal->rx_ring_queues[i].rx_pkts.cnt;\n\t\trx_total += igb_stats->q_ipackets[i];\n\t}\n\n\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS &&\n\t\t\ti < internal->nb_tx_queues; i++) {\n\t\tigb_stats->q_opackets[i] = internal->tx_ring_queues[i].tx_pkts.cnt;\n\t\tigb_stats->q_errors[i] = internal->tx_ring_queues[i].err_pkts.cnt;\n\t\ttx_total += igb_stats->q_opackets[i];\n\t\ttx_err_total += igb_stats->q_errors[i];\n\t}\n\n\tigb_stats->ipackets = rx_total;\n\tigb_stats->opackets = tx_total;\n\tigb_stats->oerrors = tx_err_total;\n}\n\nstatic void\neth_stats_reset(struct rte_eth_dev *dev)\n{\n\tunsigned i;\n\tstruct pmd_internals *internal = dev->data->dev_private;\n\tfor (i = 0; i < internal->nb_rx_queues; i++)\n\t\tinternal->rx_ring_queues[i].rx_pkts.cnt = 0;\n\tfor (i = 0; i < internal->nb_tx_queues; i++) {\n\t\tinternal->tx_ring_queues[i].tx_pkts.cnt = 0;\n\t\tinternal->tx_ring_queues[i].err_pkts.cnt = 0;\n\t}\n}\n\nstatic void\neth_mac_addr_remove(struct rte_eth_dev *dev __rte_unused,\n\tuint32_t index __rte_unused)\n{\n}\n\nstatic void\neth_mac_addr_add(struct rte_eth_dev *dev __rte_unused,\n\tstruct ether_addr *mac_addr __rte_unused,\n\tuint32_t index __rte_unused,\n\tuint32_t vmdq __rte_unused)\n{\n}\n\nstatic void\neth_queue_release(void *q __rte_unused) { ; }\nstatic int\neth_link_update(struct rte_eth_dev *dev __rte_unused,\n\t\tint wait_to_complete __rte_unused) { return 0; }\n\nstatic const struct eth_dev_ops ops = {\n\t.dev_start = eth_dev_start,\n\t.dev_stop = eth_dev_stop,\n\t.dev_set_link_up = eth_dev_set_link_up,\n\t.dev_set_link_down = eth_dev_set_link_down,\n\t.dev_configure = eth_dev_configure,\n\t.dev_infos_get = eth_dev_info,\n\t.rx_queue_setup = eth_rx_queue_setup,\n\t.tx_queue_setup = eth_tx_queue_setup,\n\t.rx_queue_release = eth_queue_release,\n\t.tx_queue_release = eth_queue_release,\n\t.link_update = eth_link_update,\n\t.stats_get = eth_stats_get,\n\t.stats_reset = eth_stats_reset,\n\t.mac_addr_remove = eth_mac_addr_remove,\n\t.mac_addr_add = eth_mac_addr_add,\n};\n\nstatic struct eth_driver rte_ring_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_ring_pmd\",\n\t\t.drv_flags = RTE_PCI_DRV_DETACHABLE,\n\t},\n};\n\nstatic struct rte_pci_id id_table;\n\nint\nrte_eth_from_rings(const char *name, struct rte_ring *const rx_queues[],\n\t\tconst unsigned nb_rx_queues,\n\t\tstruct rte_ring *const tx_queues[],\n\t\tconst unsigned nb_tx_queues,\n\t\tconst unsigned numa_node)\n{\n\tstruct rte_eth_dev_data *data = NULL;\n\tstruct rte_pci_device *pci_dev = NULL;\n\tstruct pmd_internals *internals = NULL;\n\tstruct rte_eth_dev *eth_dev = NULL;\n\n\tunsigned i;\n\n\t/* do some parameter checking */\n\tif (rx_queues == NULL && nb_rx_queues > 0)\n\t\tgoto error;\n\tif (tx_queues == NULL && nb_tx_queues > 0)\n\t\tgoto error;\n\n\tRTE_LOG(INFO, PMD, \"Creating rings-backed ethdev on numa socket %u\\n\",\n\t\t\tnuma_node);\n\n\t/* now do all data allocation - for eth_dev structure, dummy pci driver\n\t * and internal (private) data\n\t */\n\tdata = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node);\n\tif (data == NULL)\n\t\tgoto error;\n\n\tpci_dev = rte_zmalloc_socket(name, sizeof(*pci_dev), 0, numa_node);\n\tif (pci_dev == NULL)\n\t\tgoto error;\n\n\tinternals = rte_zmalloc_socket(name, sizeof(*internals), 0, numa_node);\n\tif (internals == NULL)\n\t\tgoto error;\n\n\t/* reserve an ethdev entry */\n\teth_dev = rte_eth_dev_allocate(name, RTE_ETH_DEV_VIRTUAL);\n\tif (eth_dev == NULL)\n\t\tgoto error;\n\n\n\t/* now put it all together\n\t * - store queue data in internals,\n\t * - store numa_node info in pci_driver\n\t * - point eth_dev_data to internals and pci_driver\n\t * - and point eth_dev structure to new eth_dev_data structure\n\t */\n\t/* NOTE: we'll replace the data element, of originally allocated eth_dev\n\t * so the rings are local per-process */\n\n\tinternals->nb_rx_queues = nb_rx_queues;\n\tinternals->nb_tx_queues = nb_tx_queues;\n\tfor (i = 0; i < nb_rx_queues; i++) {\n\t\tinternals->rx_ring_queues[i].rng = rx_queues[i];\n\t}\n\tfor (i = 0; i < nb_tx_queues; i++) {\n\t\tinternals->tx_ring_queues[i].rng = tx_queues[i];\n\t}\n\n\trte_ring_pmd.pci_drv.name = ring_ethdev_driver_name;\n\trte_ring_pmd.pci_drv.id_table = &id_table;\n\n\tpci_dev->numa_node = numa_node;\n\tpci_dev->driver = &rte_ring_pmd.pci_drv;\n\n\tdata->dev_private = internals;\n\tdata->port_id = eth_dev->data->port_id;\n\tmemmove(data->name, eth_dev->data->name, sizeof(data->name));\n\tdata->nb_rx_queues = (uint16_t)nb_rx_queues;\n\tdata->nb_tx_queues = (uint16_t)nb_tx_queues;\n\tdata->dev_link = pmd_link;\n\tdata->mac_addrs = &internals->address;\n\n\teth_dev->data = data;\n\teth_dev->driver = &rte_ring_pmd;\n\teth_dev->dev_ops = &ops;\n\teth_dev->pci_dev = pci_dev;\n\tTAILQ_INIT(&(eth_dev->link_intr_cbs));\n\n\t/* finally assign rx and tx ops */\n\teth_dev->rx_pkt_burst = eth_ring_rx;\n\teth_dev->tx_pkt_burst = eth_ring_tx;\n\n\treturn data->port_id;\n\nerror:\n\trte_free(data);\n\trte_free(pci_dev);\n\trte_free(internals);\n\n\treturn -1;\n}\n\nenum dev_action{\n\tDEV_CREATE,\n\tDEV_ATTACH\n};\n\nstatic int\neth_dev_ring_create(const char *name, const unsigned numa_node,\n\t\tenum dev_action action)\n{\n\t/* rx and tx are so-called from point of view of first port.\n\t * They are inverted from the point of view of second port\n\t */\n\tstruct rte_ring *rxtx[RTE_PMD_RING_MAX_RX_RINGS];\n\tunsigned i;\n\tchar rng_name[RTE_RING_NAMESIZE];\n\tunsigned num_rings = RTE_MIN(RTE_PMD_RING_MAX_RX_RINGS,\n\t\t\tRTE_PMD_RING_MAX_TX_RINGS);\n\n\tfor (i = 0; i < num_rings; i++) {\n\t\tsnprintf(rng_name, sizeof(rng_name), \"ETH_RXTX%u_%s\", i, name);\n\t\trxtx[i] = (action == DEV_CREATE) ?\n\t\t\t\trte_ring_create(rng_name, 1024, numa_node,\n\t\t\t\t\t\tRING_F_SP_ENQ|RING_F_SC_DEQ) :\n\t\t\t\trte_ring_lookup(rng_name);\n\t\tif (rxtx[i] == NULL)\n\t\t\treturn -1;\n\t}\n\n\tif (rte_eth_from_rings(name, rxtx, num_rings, rxtx, num_rings, numa_node) < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n\nstatic int\neth_dev_ring_pair_create(const char *name, const unsigned numa_node,\n\t\tenum dev_action action)\n{\n\t/* rx and tx are so-called from point of view of first port.\n\t * They are inverted from the point of view of second port\n\t */\n\tstruct rte_ring *rx[RTE_PMD_RING_MAX_RX_RINGS];\n\tstruct rte_ring *tx[RTE_PMD_RING_MAX_TX_RINGS];\n\tunsigned i;\n\tchar rx_rng_name[RTE_RING_NAMESIZE];\n\tchar tx_rng_name[RTE_RING_NAMESIZE];\n\tunsigned num_rings = RTE_MIN(RTE_PMD_RING_MAX_RX_RINGS,\n\t\t\tRTE_PMD_RING_MAX_TX_RINGS);\n\n\tfor (i = 0; i < num_rings; i++) {\n\t\tsnprintf(rx_rng_name, sizeof(rx_rng_name), \"ETH_RX%u_%s\", i, name);\n\t\trx[i] = (action == DEV_CREATE) ?\n\t\t\t\trte_ring_create(rx_rng_name, 1024, numa_node,\n\t\t\t\t\t\tRING_F_SP_ENQ|RING_F_SC_DEQ) :\n\t\t\t\trte_ring_lookup(rx_rng_name);\n\t\tif (rx[i] == NULL)\n\t\t\treturn -1;\n\t\tsnprintf(tx_rng_name, sizeof(tx_rng_name), \"ETH_TX%u_%s\", i, name);\n\t\ttx[i] = (action == DEV_CREATE) ?\n\t\t\t\trte_ring_create(tx_rng_name, 1024, numa_node,\n\t\t\t\t\t\tRING_F_SP_ENQ|RING_F_SC_DEQ):\n\t\t\t\trte_ring_lookup(tx_rng_name);\n\t\tif (tx[i] == NULL)\n\t\t\treturn -1;\n\t}\n\n\tif (rte_eth_from_rings(rx_rng_name, rx, num_rings, tx, num_rings,\n\t\t\t\tnuma_node) < 0 ||\n\t\t\trte_eth_from_rings(tx_rng_name, tx, num_rings, rx,\n\t\t\t\tnum_rings, numa_node) < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nint\nrte_eth_ring_pair_create(const char *name, const unsigned numa_node)\n{\n\tRTE_LOG(WARNING, PMD, \"rte_eth_ring_pair_create is deprecated\\n\");\n\treturn eth_dev_ring_pair_create(name, numa_node, DEV_CREATE);\n}\n\nint\nrte_eth_ring_pair_attach(const char *name, const unsigned numa_node)\n{\n\tRTE_LOG(WARNING, PMD, \"rte_eth_ring_pair_attach is deprecated\\n\");\n\treturn eth_dev_ring_pair_create(name, numa_node, DEV_ATTACH);\n}\n\nstruct node_action_pair {\n\tchar name[PATH_MAX];\n\tunsigned node;\n\tenum dev_action action;\n};\n\nstruct node_action_list {\n\tunsigned total;\n\tunsigned count;\n\tstruct node_action_pair *list;\n};\n\nstatic int parse_kvlist (const char *key __rte_unused, const char *value, void *data)\n{\n\tstruct node_action_list *info = data;\n\tint ret;\n\tchar *name;\n\tchar *action;\n\tchar *node;\n\tchar *end;\n\n\tname = strdup(value);\n\n\tret = -EINVAL;\n\n\tif (!name) {\n\t\tRTE_LOG(WARNING, PMD, \"command line paramter is empty for ring pmd!\\n\");\n\t\tgoto out;\n\t}\n\n\tnode = strchr(name, ':');\n\tif (!node) {\n\t\tRTE_LOG(WARNING, PMD, \"could not parse node value from %s\", name);\n\t\tgoto out;\n\t}\n\n\t*node = '\\0';\n\tnode++;\n\n\taction = strchr(node, ':');\n\tif (!action) {\n\t\tRTE_LOG(WARNING, PMD, \"could not action value from %s\", node);\n\t\tgoto out;\n\t}\n\n\t*action = '\\0';\n\taction++;\n\n\t/*\n\t * Need to do some sanity checking here\n\t */\n\n\tif (strcmp(action, ETH_RING_ACTION_ATTACH) == 0)\n\t\tinfo->list[info->count].action = DEV_ATTACH;\n\telse if (strcmp(action, ETH_RING_ACTION_CREATE) == 0)\n\t\tinfo->list[info->count].action = DEV_CREATE;\n\telse\n\t\tgoto out;\n\n\terrno = 0;\n\tinfo->list[info->count].node = strtol(node, &end, 10);\n\n\tif ((errno != 0) || (*end != '\\0')) {\n\t\tRTE_LOG(WARNING, PMD, \"node value %s is unparseable as a number\\n\", node);\n\t\tgoto out;\n\t}\n\n\tsnprintf(info->list[info->count].name, sizeof(info->list[info->count].name), \"%s\", name);\n\n\tinfo->count++;\n\n\tret = 0;\nout:\n\tfree(name);\n\treturn ret;\n}\n\nstatic int\nrte_pmd_ring_devinit(const char *name, const char *params)\n{\n\tstruct rte_kvargs *kvlist = NULL;\n\tint ret = 0;\n\tstruct node_action_list *info = NULL;\n\n\tRTE_LOG(INFO, PMD, \"Initializing pmd_ring for %s\\n\", name);\n\n\tif (params == NULL || params[0] == '\\0') {\n\t\tret = eth_dev_ring_create(name, rte_socket_id(), DEV_CREATE);\n\t\tif (ret == -1) {\n\t\t\tRTE_LOG(INFO, PMD,\n\t\t\t\t\"Attach to pmd_ring for %s\\n\", name);\n\t\t\tret = eth_dev_ring_create(name, rte_socket_id(),\n\t\t\t\t\t\t DEV_ATTACH);\n\t\t}\n\t}\n\telse {\n\t\tkvlist = rte_kvargs_parse(params, valid_arguments);\n\n\t\tif (!kvlist) {\n\t\t\tRTE_LOG(INFO, PMD, \"Ignoring unsupported parameters when creating\"\n\t\t\t\t\t\" rings-backed ethernet device\\n\");\n\t\t\tret = eth_dev_ring_create(name, rte_socket_id(),\n\t\t\t\t\t\t DEV_CREATE);\n\t\t\tif (ret == -1) {\n\t\t\t\tRTE_LOG(INFO, PMD,\n\t\t\t\t\t\"Attach to pmd_ring for %s\\n\",\n\t\t\t\t\tname);\n\t\t\t\tret = eth_dev_ring_create(name, rte_socket_id(),\n\t\t\t\t\t\t\t DEV_ATTACH);\n\t\t\t}\n\t\t\treturn ret;\n\t\t} else {\n\t\t\tret = rte_kvargs_count(kvlist, ETH_RING_NUMA_NODE_ACTION_ARG);\n\t\t\tinfo = rte_zmalloc(\"struct node_action_list\",\n\t\t\t\t\t sizeof(struct node_action_list) +\n\t\t\t\t\t (sizeof(struct node_action_pair) * ret),\n\t\t\t\t\t 0);\n\t\t\tif (!info)\n\t\t\t\tgoto out_free;\n\n\t\t\tinfo->total = ret;\n\t\t\tinfo->list = (struct node_action_pair*)(info + 1);\n\n\t\t\tret = rte_kvargs_process(kvlist, ETH_RING_NUMA_NODE_ACTION_ARG,\n\t\t\t\t\t\t parse_kvlist, info);\n\n\t\t\tif (ret < 0)\n\t\t\t\tgoto out_free;\n\n\t\t\tfor (info->count = 0; info->count < info->total; info->count++) {\n\t\t\t\tret = eth_dev_ring_create(name,\n\t\t\t\t\t\t\t info->list[info->count].node,\n\t\t\t\t\t\t\t info->list[info->count].action);\n\t\t\t\tif ((ret == -1) &&\n\t\t\t\t (info->list[info->count].action == DEV_CREATE)) {\n\t\t\t\t\tRTE_LOG(INFO, PMD,\n\t\t\t\t\t\t\"Attach to pmd_ring for %s\\n\",\n\t\t\t\t\t\tname);\n\t\t\t\t\tret = eth_dev_ring_create(name,\n\t\t\t\t\t\t\tinfo->list[info->count].node,\n\t\t\t\t\t\t\tDEV_ATTACH);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\nout_free:\n\trte_kvargs_free(kvlist);\n\trte_free(info);\n\treturn ret;\n}\n\nstatic int\nrte_pmd_ring_devuninit(const char *name)\n{\n\tstruct rte_eth_dev *eth_dev = NULL;\n\n\tRTE_LOG(INFO, PMD, \"Un-Initializing pmd_ring for %s\\n\", name);\n\n\tif (name == NULL)\n\t\treturn -EINVAL;\n\n\t/* find an ethdev entry */\n\teth_dev = rte_eth_dev_allocated(name);\n\tif (eth_dev == NULL)\n\t\treturn -ENODEV;\n\n\teth_dev_stop(eth_dev);\n\trte_free(eth_dev->data->dev_private);\n\trte_free(eth_dev->data);\n\trte_free(eth_dev->pci_dev);\n\n\trte_eth_dev_release_port(eth_dev);\n\treturn 0;\n}\n\nstatic struct rte_driver pmd_ring_drv = {\n\t.name = \"eth_ring\",\n\t.type = PMD_VDEV,\n\t.init = rte_pmd_ring_devinit,\n\t.uninit = rte_pmd_ring_devuninit,\n};\n\nPMD_REGISTER_DRIVER(pmd_ring_drv);\n" }, { "path": "drivers/net/ring/rte_eth_ring.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ETH_RING_H_\n#define _RTE_ETH_RING_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n/**\n * Create a new ethdev port from a set of rings\n *\n * @param name\n * name to be given to the new ethdev port\n * @param rx_queues\n * pointer to array of rte_rings to be used as RX queues\n * @param nb_rx_queues\n * number of elements in the rx_queues array\n * @param tx_queues\n * pointer to array of rte_rings to be used as TX queues\n * @param nb_tx_queues\n * number of elements in the tx_queues array\n * @param numa_node\n * the numa node on which the memory for this port is to be allocated\n * @return\n * the port number of the newly created the ethdev or -1 on error.\n */\nint rte_eth_from_rings(const char *name,\n\t\tstruct rte_ring * const rx_queues[],\n\t\tconst unsigned nb_rx_queues,\n\t\tstruct rte_ring *const tx_queues[],\n\t\tconst unsigned nb_tx_queues,\n\t\tconst unsigned numa_node);\n\nint rte_eth_ring_pair_create(const char *name, const unsigned numa_node);\nint rte_eth_ring_pair_attach(const char *name, const unsigned numa_node);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "drivers/net/virtio/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_virtio.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_pmd_virtio_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_VIRTIO_PMD) += virtqueue.c\nSRCS-$(CONFIG_RTE_LIBRTE_VIRTIO_PMD) += virtio_pci.c\nSRCS-$(CONFIG_RTE_LIBRTE_VIRTIO_PMD) += virtio_rxtx.c\nSRCS-$(CONFIG_RTE_LIBRTE_VIRTIO_PMD) += virtio_ethdev.c\n\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_VIRTIO_PMD) += lib/librte_eal lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_VIRTIO_PMD) += lib/librte_mempool lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_VIRTIO_PMD) += lib/librte_net\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/virtio/virtio_ethdev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#ifdef RTE_EXEC_ENV_LINUXAPP\n#include \n#include \n#endif\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"virtio_ethdev.h\"\n#include \"virtio_pci.h\"\n#include \"virtio_logs.h\"\n#include \"virtqueue.h\"\n\n\nstatic int eth_virtio_dev_init(struct rte_eth_dev *eth_dev);\nstatic int eth_virtio_dev_uninit(struct rte_eth_dev *eth_dev);\nstatic int virtio_dev_configure(struct rte_eth_dev *dev);\nstatic int virtio_dev_start(struct rte_eth_dev *dev);\nstatic void virtio_dev_stop(struct rte_eth_dev *dev);\nstatic void virtio_dev_promiscuous_enable(struct rte_eth_dev *dev);\nstatic void virtio_dev_promiscuous_disable(struct rte_eth_dev *dev);\nstatic void virtio_dev_allmulticast_enable(struct rte_eth_dev *dev);\nstatic void virtio_dev_allmulticast_disable(struct rte_eth_dev *dev);\nstatic void virtio_dev_info_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_dev_info *dev_info);\nstatic int virtio_dev_link_update(struct rte_eth_dev *dev,\n\t__rte_unused int wait_to_complete);\n\nstatic void virtio_set_hwaddr(struct virtio_hw *hw);\nstatic void virtio_get_hwaddr(struct virtio_hw *hw);\n\nstatic void virtio_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);\nstatic void virtio_dev_stats_reset(struct rte_eth_dev *dev);\nstatic void virtio_dev_free_mbufs(struct rte_eth_dev *dev);\nstatic int virtio_vlan_filter_set(struct rte_eth_dev *dev,\n\t\t\t\tuint16_t vlan_id, int on);\nstatic void virtio_mac_addr_add(struct rte_eth_dev *dev,\n\t\t\t\tstruct ether_addr *mac_addr,\n\t\t\t\tuint32_t index, uint32_t vmdq __rte_unused);\nstatic void virtio_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);\nstatic void virtio_mac_addr_set(struct rte_eth_dev *dev,\n\t\t\t\tstruct ether_addr *mac_addr);\n\nstatic int virtio_dev_queue_stats_mapping_set(\n\t__rte_unused struct rte_eth_dev *eth_dev,\n\t__rte_unused uint16_t queue_id,\n\t__rte_unused uint8_t stat_idx,\n\t__rte_unused uint8_t is_rx);\n\n/*\n * The set of PCI devices this driver supports\n */\nstatic const struct rte_pci_id pci_id_virtio_map[] = {\n\n#define RTE_PCI_DEV_ID_DECL_VIRTIO(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \"rte_pci_dev_ids.h\"\n\n{ .vendor_id = 0, /* sentinel */ },\n};\n\nstatic int\nvirtio_send_command(struct virtqueue *vq, struct virtio_pmd_ctrl *ctrl,\n\t\tint *dlen, int pkt_num)\n{\n\tuint32_t head, i;\n\tint k, sum = 0;\n\tvirtio_net_ctrl_ack status = ~0;\n\tstruct virtio_pmd_ctrl result;\n\n\tctrl->status = status;\n\n\tif (!(vq && vq->hw->cvq)) {\n\t\tPMD_INIT_LOG(ERR,\n\t\t\t \"%s(): Control queue is not supported.\",\n\t\t\t __func__);\n\t\treturn -1;\n\t}\n\thead = vq->vq_desc_head_idx;\n\n\tPMD_INIT_LOG(DEBUG, \"vq->vq_desc_head_idx = %d, status = %d, \"\n\t\t\"vq->hw->cvq = %p vq = %p\",\n\t\tvq->vq_desc_head_idx, status, vq->hw->cvq, vq);\n\n\tif ((vq->vq_free_cnt < ((uint32_t)pkt_num + 2)) || (pkt_num < 1))\n\t\treturn -1;\n\n\tmemcpy(vq->virtio_net_hdr_mz->addr, ctrl,\n\t\tsizeof(struct virtio_pmd_ctrl));\n\n\t/*\n\t * Format is enforced in qemu code:\n\t * One TX packet for header;\n\t * At least one TX packet per argument;\n\t * One RX packet for ACK.\n\t */\n\tvq->vq_ring.desc[head].flags = VRING_DESC_F_NEXT;\n\tvq->vq_ring.desc[head].addr = vq->virtio_net_hdr_mz->phys_addr;\n\tvq->vq_ring.desc[head].len = sizeof(struct virtio_net_ctrl_hdr);\n\tvq->vq_free_cnt--;\n\ti = vq->vq_ring.desc[head].next;\n\n\tfor (k = 0; k < pkt_num; k++) {\n\t\tvq->vq_ring.desc[i].flags = VRING_DESC_F_NEXT;\n\t\tvq->vq_ring.desc[i].addr = vq->virtio_net_hdr_mz->phys_addr\n\t\t\t+ sizeof(struct virtio_net_ctrl_hdr)\n\t\t\t+ sizeof(ctrl->status) + sizeof(uint8_t)*sum;\n\t\tvq->vq_ring.desc[i].len = dlen[k];\n\t\tsum += dlen[k];\n\t\tvq->vq_free_cnt--;\n\t\ti = vq->vq_ring.desc[i].next;\n\t}\n\n\tvq->vq_ring.desc[i].flags = VRING_DESC_F_WRITE;\n\tvq->vq_ring.desc[i].addr = vq->virtio_net_hdr_mz->phys_addr\n\t\t\t+ sizeof(struct virtio_net_ctrl_hdr);\n\tvq->vq_ring.desc[i].len = sizeof(ctrl->status);\n\tvq->vq_free_cnt--;\n\n\tvq->vq_desc_head_idx = vq->vq_ring.desc[i].next;\n\n\tvq_update_avail_ring(vq, head);\n\tvq_update_avail_idx(vq);\n\n\tPMD_INIT_LOG(DEBUG, \"vq->vq_queue_index = %d\", vq->vq_queue_index);\n\n\tvirtqueue_notify(vq);\n\n\trte_rmb();\n\twhile (vq->vq_used_cons_idx == vq->vq_ring.used->idx) {\n\t\trte_rmb();\n\t\tusleep(100);\n\t}\n\n\twhile (vq->vq_used_cons_idx != vq->vq_ring.used->idx) {\n\t\tuint32_t idx, desc_idx, used_idx;\n\t\tstruct vring_used_elem *uep;\n\n\t\tused_idx = (uint32_t)(vq->vq_used_cons_idx\n\t\t\t\t& (vq->vq_nentries - 1));\n\t\tuep = &vq->vq_ring.used->ring[used_idx];\n\t\tidx = (uint32_t) uep->id;\n\t\tdesc_idx = idx;\n\n\t\twhile (vq->vq_ring.desc[desc_idx].flags & VRING_DESC_F_NEXT) {\n\t\t\tdesc_idx = vq->vq_ring.desc[desc_idx].next;\n\t\t\tvq->vq_free_cnt++;\n\t\t}\n\n\t\tvq->vq_ring.desc[desc_idx].next = vq->vq_desc_head_idx;\n\t\tvq->vq_desc_head_idx = idx;\n\n\t\tvq->vq_used_cons_idx++;\n\t\tvq->vq_free_cnt++;\n\t}\n\n\tPMD_INIT_LOG(DEBUG, \"vq->vq_free_cnt=%d\\nvq->vq_desc_head_idx=%d\",\n\t\t\tvq->vq_free_cnt, vq->vq_desc_head_idx);\n\n\tmemcpy(&result, vq->virtio_net_hdr_mz->addr,\n\t\t\tsizeof(struct virtio_pmd_ctrl));\n\n\treturn result.status;\n}\n\nstatic int\nvirtio_set_multiple_queues(struct rte_eth_dev *dev, uint16_t nb_queues)\n{\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tstruct virtio_pmd_ctrl ctrl;\n\tint dlen[1];\n\tint ret;\n\n\tctrl.hdr.class = VIRTIO_NET_CTRL_MQ;\n\tctrl.hdr.cmd = VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET;\n\tmemcpy(ctrl.data, &nb_queues, sizeof(uint16_t));\n\n\tdlen[0] = sizeof(uint16_t);\n\n\tret = virtio_send_command(hw->cvq, &ctrl, dlen, 1);\n\tif (ret) {\n\t\tPMD_INIT_LOG(ERR, \"Multiqueue configured but send command \"\n\t\t\t \"failed, this is too late now...\");\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nvoid\nvirtio_dev_queue_release(struct virtqueue *vq) {\n\tstruct virtio_hw *hw = vq->hw;\n\n\tif (vq) {\n\t\t/* Select and deactivate the queue */\n\t\tVIRTIO_WRITE_REG_2(hw, VIRTIO_PCI_QUEUE_SEL, vq->queue_id);\n\t\tVIRTIO_WRITE_REG_4(hw, VIRTIO_PCI_QUEUE_PFN, 0);\n\n\t\trte_free(vq);\n\t\tvq = NULL;\n\t}\n}\n\nint virtio_dev_queue_setup(struct rte_eth_dev *dev,\n\t\t\tint queue_type,\n\t\t\tuint16_t queue_idx,\n\t\t\tuint16_t vtpci_queue_idx,\n\t\t\tuint16_t nb_desc,\n\t\t\tunsigned int socket_id,\n\t\t\tstruct virtqueue **pvq)\n{\n\tchar vq_name[VIRTQUEUE_MAX_NAME_SZ];\n\tconst struct rte_memzone *mz;\n\tuint16_t vq_size;\n\tint size;\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tstruct virtqueue *vq = NULL;\n\n\t/* Write the virtqueue index to the Queue Select Field */\n\tVIRTIO_WRITE_REG_2(hw, VIRTIO_PCI_QUEUE_SEL, vtpci_queue_idx);\n\tPMD_INIT_LOG(DEBUG, \"selecting queue: %d\", vtpci_queue_idx);\n\n\t/*\n\t * Read the virtqueue size from the Queue Size field\n\t * Always power of 2 and if 0 virtqueue does not exist\n\t */\n\tvq_size = VIRTIO_READ_REG_2(hw, VIRTIO_PCI_QUEUE_NUM);\n\tPMD_INIT_LOG(DEBUG, \"vq_size: %d nb_desc:%d\", vq_size, nb_desc);\n\tif (vq_size == 0) {\n\t\tPMD_INIT_LOG(ERR, \"%s: virtqueue does not exist\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (!rte_is_power_of_2(vq_size)) {\n\t\tPMD_INIT_LOG(ERR, \"%s: virtqueue size is not powerof 2\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (queue_type == VTNET_RQ) {\n\t\tsnprintf(vq_name, sizeof(vq_name), \"port%d_rvq%d\",\n\t\t\tdev->data->port_id, queue_idx);\n\t\tvq = rte_zmalloc(vq_name, sizeof(struct virtqueue) +\n\t\t\tvq_size * sizeof(struct vq_desc_extra), RTE_CACHE_LINE_SIZE);\n\t} else if (queue_type == VTNET_TQ) {\n\t\tsnprintf(vq_name, sizeof(vq_name), \"port%d_tvq%d\",\n\t\t\tdev->data->port_id, queue_idx);\n\t\tvq = rte_zmalloc(vq_name, sizeof(struct virtqueue) +\n\t\t\tvq_size * sizeof(struct vq_desc_extra), RTE_CACHE_LINE_SIZE);\n\t} else if (queue_type == VTNET_CQ) {\n\t\tsnprintf(vq_name, sizeof(vq_name), \"port%d_cvq\",\n\t\t\tdev->data->port_id);\n\t\tvq = rte_zmalloc(vq_name, sizeof(struct virtqueue) +\n\t\t\tvq_size * sizeof(struct vq_desc_extra),\n\t\t\tRTE_CACHE_LINE_SIZE);\n\t}\n\tif (vq == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"%s: Can not allocate virtqueue\", __func__);\n\t\treturn (-ENOMEM);\n\t}\n\n\tvq->hw = hw;\n\tvq->port_id = dev->data->port_id;\n\tvq->queue_id = queue_idx;\n\tvq->vq_queue_index = vtpci_queue_idx;\n\tvq->vq_nentries = vq_size;\n\n\tif (nb_desc == 0 || nb_desc > vq_size)\n\t\tnb_desc = vq_size;\n\tvq->vq_free_cnt = nb_desc;\n\n\t/*\n\t * Reserve a memzone for vring elements\n\t */\n\tsize = vring_size(vq_size, VIRTIO_PCI_VRING_ALIGN);\n\tvq->vq_ring_size = RTE_ALIGN_CEIL(size, VIRTIO_PCI_VRING_ALIGN);\n\tPMD_INIT_LOG(DEBUG, \"vring_size: %d, rounded_vring_size: %d\", size, vq->vq_ring_size);\n\n\tmz = rte_memzone_reserve_aligned(vq_name, vq->vq_ring_size,\n\t\tsocket_id, 0, VIRTIO_PCI_VRING_ALIGN);\n\tif (mz == NULL) {\n\t\tif (rte_errno == EEXIST)\n\t\t\tmz = rte_memzone_lookup(vq_name);\n\t\tif (mz == NULL) {\n\t\t\trte_free(vq);\n\t\t\treturn -ENOMEM;\n\t\t}\n\t}\n\n\t/*\n\t * Virtio PCI device VIRTIO_PCI_QUEUE_PF register is 32bit,\n\t * and only accepts 32 bit page frame number.\n\t * Check if the allocated physical memory exceeds 16TB.\n\t */\n\tif ((mz->phys_addr + vq->vq_ring_size - 1) >> (VIRTIO_PCI_QUEUE_ADDR_SHIFT + 32)) {\n\t\tPMD_INIT_LOG(ERR, \"vring address shouldn't be above 16TB!\");\n\t\trte_free(vq);\n\t\treturn -ENOMEM;\n\t}\n\n\tmemset(mz->addr, 0, sizeof(mz->len));\n\tvq->mz = mz;\n\tvq->vq_ring_mem = mz->phys_addr;\n\tvq->vq_ring_virt_mem = mz->addr;\n\tPMD_INIT_LOG(DEBUG, \"vq->vq_ring_mem: 0x%\"PRIx64, (uint64_t)mz->phys_addr);\n\tPMD_INIT_LOG(DEBUG, \"vq->vq_ring_virt_mem: 0x%\"PRIx64, (uint64_t)(uintptr_t)mz->addr);\n\tvq->virtio_net_hdr_mz = NULL;\n\tvq->virtio_net_hdr_mem = 0;\n\n\tif (queue_type == VTNET_TQ) {\n\t\t/*\n\t\t * For each xmit packet, allocate a virtio_net_hdr\n\t\t */\n\t\tsnprintf(vq_name, sizeof(vq_name), \"port%d_tvq%d_hdrzone\",\n\t\t\tdev->data->port_id, queue_idx);\n\t\tvq->virtio_net_hdr_mz = rte_memzone_reserve_aligned(vq_name,\n\t\t\tvq_size * hw->vtnet_hdr_size,\n\t\t\tsocket_id, 0, RTE_CACHE_LINE_SIZE);\n\t\tif (vq->virtio_net_hdr_mz == NULL) {\n\t\t\tif (rte_errno == EEXIST)\n\t\t\t\tvq->virtio_net_hdr_mz =\n\t\t\t\t\trte_memzone_lookup(vq_name);\n\t\t\tif (vq->virtio_net_hdr_mz == NULL) {\n\t\t\t\trte_free(vq);\n\t\t\t\treturn -ENOMEM;\n\t\t\t}\n\t\t}\n\t\tvq->virtio_net_hdr_mem =\n\t\t\tvq->virtio_net_hdr_mz->phys_addr;\n\t\tmemset(vq->virtio_net_hdr_mz->addr, 0,\n\t\t\tvq_size * hw->vtnet_hdr_size);\n\t} else if (queue_type == VTNET_CQ) {\n\t\t/* Allocate a page for control vq command, data and status */\n\t\tsnprintf(vq_name, sizeof(vq_name), \"port%d_cvq_hdrzone\",\n\t\t\tdev->data->port_id);\n\t\tvq->virtio_net_hdr_mz = rte_memzone_reserve_aligned(vq_name,\n\t\t\tPAGE_SIZE, socket_id, 0, RTE_CACHE_LINE_SIZE);\n\t\tif (vq->virtio_net_hdr_mz == NULL) {\n\t\t\tif (rte_errno == EEXIST)\n\t\t\t\tvq->virtio_net_hdr_mz =\n\t\t\t\t\trte_memzone_lookup(vq_name);\n\t\t\tif (vq->virtio_net_hdr_mz == NULL) {\n\t\t\t\trte_free(vq);\n\t\t\t\treturn -ENOMEM;\n\t\t\t}\n\t\t}\n\t\tvq->virtio_net_hdr_mem =\n\t\t\tvq->virtio_net_hdr_mz->phys_addr;\n\t\tmemset(vq->virtio_net_hdr_mz->addr, 0, PAGE_SIZE);\n\t}\n\n\t/*\n\t * Set guest physical address of the virtqueue\n\t * in VIRTIO_PCI_QUEUE_PFN config register of device\n\t */\n\tVIRTIO_WRITE_REG_4(hw, VIRTIO_PCI_QUEUE_PFN,\n\t\t\tmz->phys_addr >> VIRTIO_PCI_QUEUE_ADDR_SHIFT);\n\t*pvq = vq;\n\treturn 0;\n}\n\nstatic int\nvirtio_dev_cq_queue_setup(struct rte_eth_dev *dev, uint16_t vtpci_queue_idx,\n\t\tuint32_t socket_id)\n{\n\tstruct virtqueue *vq;\n\tint ret;\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\tret = virtio_dev_queue_setup(dev, VTNET_CQ, VTNET_SQ_CQ_QUEUE_IDX,\n\t\t\tvtpci_queue_idx, 0, socket_id, &vq);\n\tif (ret < 0) {\n\t\tPMD_INIT_LOG(ERR, \"control vq initialization failed\");\n\t\treturn ret;\n\t}\n\n\thw->cvq = vq;\n\treturn 0;\n}\n\nstatic void\nvirtio_free_queues(struct rte_eth_dev *dev)\n{\n\tunsigned int i;\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n\t\tvirtio_dev_rx_queue_release(dev->data->rx_queues[i]);\n\n\tdev->data->nb_rx_queues = 0;\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n\t\tvirtio_dev_tx_queue_release(dev->data->tx_queues[i]);\n\n\tdev->data->nb_tx_queues = 0;\n}\n\nstatic void\nvirtio_dev_close(struct rte_eth_dev *dev)\n{\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tstruct rte_pci_device *pci_dev = dev->pci_dev;\n\n\tPMD_INIT_LOG(DEBUG, \"virtio_dev_close\");\n\n\t/* reset the NIC */\n\tif (pci_dev->driver->drv_flags & RTE_PCI_DRV_INTR_LSC)\n\t\tvtpci_irq_config(hw, VIRTIO_MSI_NO_VECTOR);\n\tvtpci_reset(hw);\n\thw->started = 0;\n\tvirtio_dev_free_mbufs(dev);\n\tvirtio_free_queues(dev);\n}\n\nstatic void\nvirtio_dev_promiscuous_enable(struct rte_eth_dev *dev)\n{\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tstruct virtio_pmd_ctrl ctrl;\n\tint dlen[1];\n\tint ret;\n\n\tif (!vtpci_with_feature(hw, VIRTIO_NET_F_CTRL_RX)) {\n\t\tPMD_INIT_LOG(INFO, \"host does not support rx control\\n\");\n\t\treturn;\n\t}\n\n\tctrl.hdr.class = VIRTIO_NET_CTRL_RX;\n\tctrl.hdr.cmd = VIRTIO_NET_CTRL_RX_PROMISC;\n\tctrl.data[0] = 1;\n\tdlen[0] = 1;\n\n\tret = virtio_send_command(hw->cvq, &ctrl, dlen, 1);\n\tif (ret)\n\t\tPMD_INIT_LOG(ERR, \"Failed to enable promisc\");\n}\n\nstatic void\nvirtio_dev_promiscuous_disable(struct rte_eth_dev *dev)\n{\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tstruct virtio_pmd_ctrl ctrl;\n\tint dlen[1];\n\tint ret;\n\n\tif (!vtpci_with_feature(hw, VIRTIO_NET_F_CTRL_RX)) {\n\t\tPMD_INIT_LOG(INFO, \"host does not support rx control\\n\");\n\t\treturn;\n\t}\n\n\tctrl.hdr.class = VIRTIO_NET_CTRL_RX;\n\tctrl.hdr.cmd = VIRTIO_NET_CTRL_RX_PROMISC;\n\tctrl.data[0] = 0;\n\tdlen[0] = 1;\n\n\tret = virtio_send_command(hw->cvq, &ctrl, dlen, 1);\n\tif (ret)\n\t\tPMD_INIT_LOG(ERR, \"Failed to disable promisc\");\n}\n\nstatic void\nvirtio_dev_allmulticast_enable(struct rte_eth_dev *dev)\n{\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tstruct virtio_pmd_ctrl ctrl;\n\tint dlen[1];\n\tint ret;\n\n\tif (!vtpci_with_feature(hw, VIRTIO_NET_F_CTRL_RX)) {\n\t\tPMD_INIT_LOG(INFO, \"host does not support rx control\\n\");\n\t\treturn;\n\t}\n\n\tctrl.hdr.class = VIRTIO_NET_CTRL_RX;\n\tctrl.hdr.cmd = VIRTIO_NET_CTRL_RX_ALLMULTI;\n\tctrl.data[0] = 1;\n\tdlen[0] = 1;\n\n\tret = virtio_send_command(hw->cvq, &ctrl, dlen, 1);\n\tif (ret)\n\t\tPMD_INIT_LOG(ERR, \"Failed to enable allmulticast\");\n}\n\nstatic void\nvirtio_dev_allmulticast_disable(struct rte_eth_dev *dev)\n{\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tstruct virtio_pmd_ctrl ctrl;\n\tint dlen[1];\n\tint ret;\n\n\tif (!vtpci_with_feature(hw, VIRTIO_NET_F_CTRL_RX)) {\n\t\tPMD_INIT_LOG(INFO, \"host does not support rx control\\n\");\n\t\treturn;\n\t}\n\n\tctrl.hdr.class = VIRTIO_NET_CTRL_RX;\n\tctrl.hdr.cmd = VIRTIO_NET_CTRL_RX_ALLMULTI;\n\tctrl.data[0] = 0;\n\tdlen[0] = 1;\n\n\tret = virtio_send_command(hw->cvq, &ctrl, dlen, 1);\n\tif (ret)\n\t\tPMD_INIT_LOG(ERR, \"Failed to disable allmulticast\");\n}\n\n/*\n * dev_ops for virtio, bare necessities for basic operation\n */\nstatic const struct eth_dev_ops virtio_eth_dev_ops = {\n\t.dev_configure = virtio_dev_configure,\n\t.dev_start = virtio_dev_start,\n\t.dev_stop = virtio_dev_stop,\n\t.dev_close = virtio_dev_close,\n\t.promiscuous_enable = virtio_dev_promiscuous_enable,\n\t.promiscuous_disable = virtio_dev_promiscuous_disable,\n\t.allmulticast_enable = virtio_dev_allmulticast_enable,\n\t.allmulticast_disable = virtio_dev_allmulticast_disable,\n\n\t.dev_infos_get = virtio_dev_info_get,\n\t.stats_get = virtio_dev_stats_get,\n\t.stats_reset = virtio_dev_stats_reset,\n\t.link_update = virtio_dev_link_update,\n\t.rx_queue_setup = virtio_dev_rx_queue_setup,\n\t.rx_queue_release = virtio_dev_rx_queue_release,\n\t.tx_queue_setup = virtio_dev_tx_queue_setup,\n\t.tx_queue_release = virtio_dev_tx_queue_release,\n\t/* collect stats per queue */\n\t.queue_stats_mapping_set = virtio_dev_queue_stats_mapping_set,\n\t.vlan_filter_set = virtio_vlan_filter_set,\n\t.mac_addr_add = virtio_mac_addr_add,\n\t.mac_addr_remove = virtio_mac_addr_remove,\n\t.mac_addr_set = virtio_mac_addr_set,\n};\n\nstatic inline int\nvirtio_dev_atomic_read_link_status(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = link;\n\tstruct rte_eth_link *src = &(dev->data->dev_link);\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * Atomically writes the link status information into global\n * structure rte_eth_dev.\n *\n * @param dev\n * - Pointer to the structure rte_eth_dev to read from.\n * - Pointer to the buffer to be saved with the link status.\n *\n * @return\n * - On success, zero.\n * - On failure, negative value.\n */\nstatic inline int\nvirtio_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = &(dev->data->dev_link);\n\tstruct rte_eth_link *src = link;\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic void\nvirtio_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tunsigned i;\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tconst struct virtqueue *txvq = dev->data->tx_queues[i];\n\t\tif (txvq == NULL)\n\t\t\tcontinue;\n\n\t\tstats->opackets += txvq->packets;\n\t\tstats->obytes += txvq->bytes;\n\t\tstats->oerrors += txvq->errors;\n\n\t\tif (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) {\n\t\t\tstats->q_opackets[i] = txvq->packets;\n\t\t\tstats->q_obytes[i] = txvq->bytes;\n\t\t}\n\t}\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tconst struct virtqueue *rxvq = dev->data->rx_queues[i];\n\t\tif (rxvq == NULL)\n\t\t\tcontinue;\n\n\t\tstats->ipackets += rxvq->packets;\n\t\tstats->ibytes += rxvq->bytes;\n\t\tstats->ierrors += rxvq->errors;\n\n\t\tif (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) {\n\t\t\tstats->q_ipackets[i] = rxvq->packets;\n\t\t\tstats->q_ibytes[i] = rxvq->bytes;\n\t\t}\n\t}\n\n\tstats->rx_nombuf = dev->data->rx_mbuf_alloc_failed;\n}\n\nstatic void\nvirtio_dev_stats_reset(struct rte_eth_dev *dev)\n{\n\tunsigned int i;\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tstruct virtqueue *txvq = dev->data->tx_queues[i];\n\t\tif (txvq == NULL)\n\t\t\tcontinue;\n\n\t\ttxvq->packets = 0;\n\t\ttxvq->bytes = 0;\n\t\ttxvq->errors = 0;\n\t}\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tstruct virtqueue *rxvq = dev->data->rx_queues[i];\n\t\tif (rxvq == NULL)\n\t\t\tcontinue;\n\n\t\trxvq->packets = 0;\n\t\trxvq->bytes = 0;\n\t\trxvq->errors = 0;\n\t}\n\n\tdev->data->rx_mbuf_alloc_failed = 0;\n}\n\nstatic void\nvirtio_set_hwaddr(struct virtio_hw *hw)\n{\n\tvtpci_write_dev_config(hw,\n\t\t\toffsetof(struct virtio_net_config, mac),\n\t\t\t&hw->mac_addr, ETHER_ADDR_LEN);\n}\n\nstatic void\nvirtio_get_hwaddr(struct virtio_hw *hw)\n{\n\tif (vtpci_with_feature(hw, VIRTIO_NET_F_MAC)) {\n\t\tvtpci_read_dev_config(hw,\n\t\t\toffsetof(struct virtio_net_config, mac),\n\t\t\t&hw->mac_addr, ETHER_ADDR_LEN);\n\t} else {\n\t\teth_random_addr(&hw->mac_addr[0]);\n\t\tvirtio_set_hwaddr(hw);\n\t}\n}\n\nstatic void\nvirtio_mac_table_set(struct virtio_hw *hw,\n\t\t const struct virtio_net_ctrl_mac *uc,\n\t\t const struct virtio_net_ctrl_mac *mc)\n{\n\tstruct virtio_pmd_ctrl ctrl;\n\tint err, len[2];\n\n\tif (!vtpci_with_feature(hw, VIRTIO_NET_F_CTRL_MAC_ADDR)) {\n\t\tPMD_DRV_LOG(INFO, \"host does not support mac table\\n\");\n\t\treturn;\n\t}\n\n\tctrl.hdr.class = VIRTIO_NET_CTRL_MAC;\n\tctrl.hdr.cmd = VIRTIO_NET_CTRL_MAC_TABLE_SET;\n\n\tlen[0] = uc->entries * ETHER_ADDR_LEN + sizeof(uc->entries);\n\tmemcpy(ctrl.data, uc, len[0]);\n\n\tlen[1] = mc->entries * ETHER_ADDR_LEN + sizeof(mc->entries);\n\tmemcpy(ctrl.data + len[0], mc, len[1]);\n\n\terr = virtio_send_command(hw->cvq, &ctrl, len, 2);\n\tif (err != 0)\n\t\tPMD_DRV_LOG(NOTICE, \"mac table set failed: %d\", err);\n}\n\nstatic void\nvirtio_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr,\n\t\t uint32_t index, uint32_t vmdq __rte_unused)\n{\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tconst struct ether_addr *addrs = dev->data->mac_addrs;\n\tunsigned int i;\n\tstruct virtio_net_ctrl_mac *uc, *mc;\n\n\tif (index >= VIRTIO_MAX_MAC_ADDRS) {\n\t\tPMD_DRV_LOG(ERR, \"mac address index %u out of range\", index);\n\t\treturn;\n\t}\n\n\tuc = alloca(VIRTIO_MAX_MAC_ADDRS * ETHER_ADDR_LEN + sizeof(uc->entries));\n\tuc->entries = 0;\n\tmc = alloca(VIRTIO_MAX_MAC_ADDRS * ETHER_ADDR_LEN + sizeof(mc->entries));\n\tmc->entries = 0;\n\n\tfor (i = 0; i < VIRTIO_MAX_MAC_ADDRS; i++) {\n\t\tconst struct ether_addr *addr\n\t\t\t= (i == index) ? mac_addr : addrs + i;\n\t\tstruct virtio_net_ctrl_mac *tbl\n\t\t\t= is_multicast_ether_addr(addr) ? mc : uc;\n\n\t\tmemcpy(&tbl->macs[tbl->entries++], addr, ETHER_ADDR_LEN);\n\t}\n\n\tvirtio_mac_table_set(hw, uc, mc);\n}\n\nstatic void\nvirtio_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)\n{\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tstruct ether_addr *addrs = dev->data->mac_addrs;\n\tstruct virtio_net_ctrl_mac *uc, *mc;\n\tunsigned int i;\n\n\tif (index >= VIRTIO_MAX_MAC_ADDRS) {\n\t\tPMD_DRV_LOG(ERR, \"mac address index %u out of range\", index);\n\t\treturn;\n\t}\n\n\tuc = alloca(VIRTIO_MAX_MAC_ADDRS * ETHER_ADDR_LEN + sizeof(uc->entries));\n\tuc->entries = 0;\n\tmc = alloca(VIRTIO_MAX_MAC_ADDRS * ETHER_ADDR_LEN + sizeof(mc->entries));\n\tmc->entries = 0;\n\n\tfor (i = 0; i < VIRTIO_MAX_MAC_ADDRS; i++) {\n\t\tstruct virtio_net_ctrl_mac *tbl;\n\n\t\tif (i == index || is_zero_ether_addr(addrs + i))\n\t\t\tcontinue;\n\n\t\ttbl = is_multicast_ether_addr(addrs + i) ? mc : uc;\n\t\tmemcpy(&tbl->macs[tbl->entries++], addrs + i, ETHER_ADDR_LEN);\n\t}\n\n\tvirtio_mac_table_set(hw, uc, mc);\n}\n\nstatic void\nvirtio_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)\n{\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\n\tmemcpy(hw->mac_addr, mac_addr, ETHER_ADDR_LEN);\n\n\t/* Use atomic update if available */\n\tif (vtpci_with_feature(hw, VIRTIO_NET_F_CTRL_MAC_ADDR)) {\n\t\tstruct virtio_pmd_ctrl ctrl;\n\t\tint len = ETHER_ADDR_LEN;\n\n\t\tctrl.hdr.class = VIRTIO_NET_CTRL_MAC;\n\t\tctrl.hdr.cmd = VIRTIO_NET_CTRL_MAC_ADDR_SET;\n\n\t\tmemcpy(ctrl.data, mac_addr, ETHER_ADDR_LEN);\n\t\tvirtio_send_command(hw->cvq, &ctrl, &len, 1);\n\t} else if (vtpci_with_feature(hw, VIRTIO_NET_F_MAC))\n\t\tvirtio_set_hwaddr(hw);\n}\n\nstatic int\nvirtio_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n{\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tstruct virtio_pmd_ctrl ctrl;\n\tint len;\n\n\tif (!vtpci_with_feature(hw, VIRTIO_NET_F_CTRL_VLAN))\n\t\treturn -ENOTSUP;\n\n\tctrl.hdr.class = VIRTIO_NET_CTRL_VLAN;\n\tctrl.hdr.cmd = on ? VIRTIO_NET_CTRL_VLAN_ADD : VIRTIO_NET_CTRL_VLAN_DEL;\n\tmemcpy(ctrl.data, &vlan_id, sizeof(vlan_id));\n\tlen = sizeof(vlan_id);\n\n\treturn virtio_send_command(hw->cvq, &ctrl, &len, 1);\n}\n\nstatic void\nvirtio_negotiate_features(struct virtio_hw *hw)\n{\n\tuint32_t host_features;\n\n\t/* Prepare guest_features: feature that driver wants to support */\n\thw->guest_features = VIRTIO_PMD_GUEST_FEATURES;\n\tPMD_INIT_LOG(DEBUG, \"guest_features before negotiate = %x\",\n\t\thw->guest_features);\n\n\t/* Read device(host) feature bits */\n\thost_features = VIRTIO_READ_REG_4(hw, VIRTIO_PCI_HOST_FEATURES);\n\tPMD_INIT_LOG(DEBUG, \"host_features before negotiate = %x\",\n\t\thost_features);\n\n\t/*\n\t * Negotiate features: Subset of device feature bits are written back\n\t * guest feature bits.\n\t */\n\thw->guest_features = vtpci_negotiate_features(hw, host_features);\n\tPMD_INIT_LOG(DEBUG, \"features after negotiate = %x\",\n\t\thw->guest_features);\n}\n\n#ifdef RTE_EXEC_ENV_LINUXAPP\nstatic int\nparse_sysfs_value(const char *filename, unsigned long *val)\n{\n\tFILE *f;\n\tchar buf[BUFSIZ];\n\tchar *end = NULL;\n\n\tf = fopen(filename, \"r\");\n\tif (f == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"%s(): cannot open sysfs value %s\",\n\t\t\t __func__, filename);\n\t\treturn -1;\n\t}\n\n\tif (fgets(buf, sizeof(buf), f) == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"%s(): cannot read sysfs value %s\",\n\t\t\t __func__, filename);\n\t\tfclose(f);\n\t\treturn -1;\n\t}\n\t*val = strtoul(buf, &end, 0);\n\tif ((buf[0] == '\\0') || (end == NULL) || (*end != '\\n')) {\n\t\tPMD_INIT_LOG(ERR, \"%s(): cannot parse sysfs value %s\",\n\t\t\t __func__, filename);\n\t\tfclose(f);\n\t\treturn -1;\n\t}\n\tfclose(f);\n\treturn 0;\n}\n\nstatic int get_uio_dev(struct rte_pci_addr *loc, char *buf, unsigned int buflen,\n\t\t\tunsigned int *uio_num)\n{\n\tstruct dirent *e;\n\tDIR *dir;\n\tchar dirname[PATH_MAX];\n\n\t/* depending on kernel version, uio can be located in uio/uioX\n\t * or uio:uioX */\n\tsnprintf(dirname, sizeof(dirname),\n\t\t SYSFS_PCI_DEVICES \"/\" PCI_PRI_FMT \"/uio\",\n\t\t loc->domain, loc->bus, loc->devid, loc->function);\n\tdir = opendir(dirname);\n\tif (dir == NULL) {\n\t\t/* retry with the parent directory */\n\t\tsnprintf(dirname, sizeof(dirname),\n\t\t\t SYSFS_PCI_DEVICES \"/\" PCI_PRI_FMT,\n\t\t\t loc->domain, loc->bus, loc->devid, loc->function);\n\t\tdir = opendir(dirname);\n\n\t\tif (dir == NULL) {\n\t\t\tPMD_INIT_LOG(ERR, \"Cannot opendir %s\", dirname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* take the first file starting with \"uio\" */\n\twhile ((e = readdir(dir)) != NULL) {\n\t\t/* format could be uio%d ...*/\n\t\tint shortprefix_len = sizeof(\"uio\") - 1;\n\t\t/* ... or uio:uio%d */\n\t\tint longprefix_len = sizeof(\"uio:uio\") - 1;\n\t\tchar *endptr;\n\n\t\tif (strncmp(e->d_name, \"uio\", 3) != 0)\n\t\t\tcontinue;\n\n\t\t/* first try uio%d */\n\t\terrno = 0;\n\t\t*uio_num = strtoull(e->d_name + shortprefix_len, &endptr, 10);\n\t\tif (errno == 0 && endptr != (e->d_name + shortprefix_len)) {\n\t\t\tsnprintf(buf, buflen, \"%s/uio%u\", dirname, *uio_num);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* then try uio:uio%d */\n\t\terrno = 0;\n\t\t*uio_num = strtoull(e->d_name + longprefix_len, &endptr, 10);\n\t\tif (errno == 0 && endptr != (e->d_name + longprefix_len)) {\n\t\t\tsnprintf(buf, buflen, \"%s/uio:uio%u\", dirname,\n\t\t\t\t *uio_num);\n\t\t\tbreak;\n\t\t}\n\t}\n\tclosedir(dir);\n\n\t/* No uio resource found */\n\tif (e == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Could not find uio resource\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nvirtio_has_msix(const struct rte_pci_addr *loc)\n{\n\tDIR *d;\n\tchar dirname[PATH_MAX];\n\n\tsnprintf(dirname, sizeof(dirname),\n\t\t SYSFS_PCI_DEVICES \"/\" PCI_PRI_FMT \"/msi_irqs\",\n\t\t loc->domain, loc->bus, loc->devid, loc->function);\n\n\td = opendir(dirname);\n\tif (d)\n\t\tclosedir(d);\n\n\treturn (d != NULL);\n}\n\n/* Extract I/O port numbers from sysfs */\nstatic int virtio_resource_init_by_uio(struct rte_pci_device *pci_dev)\n{\n\tchar dirname[PATH_MAX];\n\tchar filename[PATH_MAX];\n\tunsigned long start, size;\n\tunsigned int uio_num;\n\n\tif (get_uio_dev(&pci_dev->addr, dirname, sizeof(dirname), &uio_num) < 0)\n\t\treturn -1;\n\n\t/* get portio size */\n\tsnprintf(filename, sizeof(filename),\n\t\t \"%s/portio/port0/size\", dirname);\n\tif (parse_sysfs_value(filename, &size) < 0) {\n\t\tPMD_INIT_LOG(ERR, \"%s(): cannot parse size\",\n\t\t\t __func__);\n\t\treturn -1;\n\t}\n\n\t/* get portio start */\n\tsnprintf(filename, sizeof(filename),\n\t\t \"%s/portio/port0/start\", dirname);\n\tif (parse_sysfs_value(filename, &start) < 0) {\n\t\tPMD_INIT_LOG(ERR, \"%s(): cannot parse portio start\",\n\t\t\t __func__);\n\t\treturn -1;\n\t}\n\tpci_dev->mem_resource[0].addr = (void *)(uintptr_t)start;\n\tpci_dev->mem_resource[0].len = (uint64_t)size;\n\tPMD_INIT_LOG(DEBUG,\n\t\t \"PCI Port IO found start=0x%lx with size=0x%lx\",\n\t\t start, size);\n\n\t/* save fd */\n\tmemset(dirname, 0, sizeof(dirname));\n\tsnprintf(dirname, sizeof(dirname), \"/dev/uio%u\", uio_num);\n\tpci_dev->intr_handle.fd = open(dirname, O_RDWR);\n\tif (pci_dev->intr_handle.fd < 0) {\n\t\tPMD_INIT_LOG(ERR, \"Cannot open %s: %s\\n\",\n\t\t\tdirname, strerror(errno));\n\t\treturn -1;\n\t}\n\n\tpci_dev->intr_handle.type = RTE_INTR_HANDLE_UIO;\n\tpci_dev->driver->drv_flags |= RTE_PCI_DRV_INTR_LSC;\n\n\treturn 0;\n}\n\n/* Extract port I/O numbers from proc/ioports */\nstatic int virtio_resource_init_by_ioports(struct rte_pci_device *pci_dev)\n{\n\tuint16_t start, end;\n\tint size;\n\tFILE *fp;\n\tchar *line = NULL;\n\tchar pci_id[16];\n\tint found = 0;\n\tsize_t linesz;\n\n\tsnprintf(pci_id, sizeof(pci_id), PCI_PRI_FMT,\n\t\t pci_dev->addr.domain,\n\t\t pci_dev->addr.bus,\n\t\t pci_dev->addr.devid,\n\t\t pci_dev->addr.function);\n\n\tfp = fopen(\"/proc/ioports\", \"r\");\n\tif (fp == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"%s(): can't open ioports\", __func__);\n\t\treturn -1;\n\t}\n\n\twhile (getdelim(&line, &linesz, '\\n', fp) > 0) {\n\t\tchar *ptr = line;\n\t\tchar *left;\n\t\tint n;\n\n\t\tn = strcspn(ptr, \":\");\n\t\tptr[n] = 0;\n\t\tleft = &ptr[n+1];\n\n\t\twhile (*left && isspace(*left))\n\t\t\tleft++;\n\n\t\tif (!strncmp(left, pci_id, strlen(pci_id))) {\n\t\t\tfound = 1;\n\n\t\t\twhile (*ptr && isspace(*ptr))\n\t\t\t\tptr++;\n\n\t\t\tsscanf(ptr, \"%04hx-%04hx\", &start, &end);\n\t\t\tsize = end - start + 1;\n\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tfree(line);\n\tfclose(fp);\n\n\tif (!found)\n\t\treturn -1;\n\n\tpci_dev->mem_resource[0].addr = (void *)(uintptr_t)(uint32_t)start;\n\tpci_dev->mem_resource[0].len = (uint64_t)size;\n\tPMD_INIT_LOG(DEBUG,\n\t\t\"PCI Port IO found start=0x%x with size=0x%x\",\n\t\tstart, size);\n\n\t/* can't support lsc interrupt without uio */\n\tpci_dev->driver->drv_flags &= ~RTE_PCI_DRV_INTR_LSC;\n\n\treturn 0;\n}\n\n/* Extract I/O port numbers from sysfs */\nstatic int virtio_resource_init(struct rte_pci_device *pci_dev)\n{\n\tif (virtio_resource_init_by_uio(pci_dev) == 0)\n\t\treturn 0;\n\telse\n\t\treturn virtio_resource_init_by_ioports(pci_dev);\n}\n\n#else\nstatic int\nvirtio_has_msix(const struct rte_pci_addr *loc __rte_unused)\n{\n\t/* nic_uio does not enable interrupts, return 0 (false). */\n\treturn 0;\n}\n\nstatic int virtio_resource_init(struct rte_pci_device *pci_dev __rte_unused)\n{\n\t/* no setup required */\n\treturn 0;\n}\n#endif\n\n/*\n * Process Virtio Config changed interrupt and call the callback\n * if link state changed.\n */\nstatic void\nvirtio_interrupt_handler(__rte_unused struct rte_intr_handle *handle,\n\t\t\t void *param)\n{\n\tstruct rte_eth_dev *dev = param;\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tuint8_t isr;\n\n\t/* Read interrupt status which clears interrupt */\n\tisr = vtpci_isr(hw);\n\tPMD_DRV_LOG(INFO, \"interrupt status = %#x\", isr);\n\n\tif (rte_intr_enable(&dev->pci_dev->intr_handle) < 0)\n\t\tPMD_DRV_LOG(ERR, \"interrupt enable failed\");\n\n\tif (isr & VIRTIO_PCI_ISR_CONFIG) {\n\t\tif (virtio_dev_link_update(dev, 0) == 0)\n\t\t\t_rte_eth_dev_callback_process(dev,\n\t\t\t\t\t\t RTE_ETH_EVENT_INTR_LSC);\n\t}\n\n}\n\nstatic void\nrx_func_get(struct rte_eth_dev *eth_dev)\n{\n\tstruct virtio_hw *hw = eth_dev->data->dev_private;\n\tif (vtpci_with_feature(hw, VIRTIO_NET_F_MRG_RXBUF))\n\t\teth_dev->rx_pkt_burst = &virtio_recv_mergeable_pkts;\n\telse\n\t\teth_dev->rx_pkt_burst = &virtio_recv_pkts;\n}\n\n/*\n * This function is based on probe() function in virtio_pci.c\n * It returns 0 on success.\n */\nstatic int\neth_virtio_dev_init(struct rte_eth_dev *eth_dev)\n{\n\tstruct virtio_hw *hw = eth_dev->data->dev_private;\n\tstruct virtio_net_config *config;\n\tstruct virtio_net_config local_config;\n\tuint32_t offset_conf = sizeof(config->mac);\n\tstruct rte_pci_device *pci_dev;\n\n\tRTE_BUILD_BUG_ON(RTE_PKTMBUF_HEADROOM < sizeof(struct virtio_net_hdr));\n\n\teth_dev->dev_ops = &virtio_eth_dev_ops;\n\teth_dev->tx_pkt_burst = &virtio_xmit_pkts;\n\n\tif (rte_eal_process_type() == RTE_PROC_SECONDARY) {\n\t\trx_func_get(eth_dev);\n\t\treturn 0;\n\t}\n\n\t/* Allocate memory for storing MAC addresses */\n\teth_dev->data->mac_addrs = rte_zmalloc(\"virtio\", ETHER_ADDR_LEN, 0);\n\tif (eth_dev->data->mac_addrs == NULL) {\n\t\tPMD_INIT_LOG(ERR,\n\t\t\t\"Failed to allocate %d bytes needed to store MAC addresses\",\n\t\t\tETHER_ADDR_LEN);\n\t\treturn -ENOMEM;\n\t}\n\n\tpci_dev = eth_dev->pci_dev;\n\tif (virtio_resource_init(pci_dev) < 0)\n\t\treturn -1;\n\n\thw->use_msix = virtio_has_msix(&pci_dev->addr);\n\thw->io_base = (uint32_t)(uintptr_t)pci_dev->mem_resource[0].addr;\n\n\t/* Reset the device although not necessary at startup */\n\tvtpci_reset(hw);\n\n\t/* Tell the host we've noticed this device. */\n\tvtpci_set_status(hw, VIRTIO_CONFIG_STATUS_ACK);\n\n\t/* Tell the host we've known how to drive the device. */\n\tvtpci_set_status(hw, VIRTIO_CONFIG_STATUS_DRIVER);\n\tvirtio_negotiate_features(hw);\n\n\trx_func_get(eth_dev);\n\n\t/* Setting up rx_header size for the device */\n\tif (vtpci_with_feature(hw, VIRTIO_NET_F_MRG_RXBUF))\n\t\thw->vtnet_hdr_size = sizeof(struct virtio_net_hdr_mrg_rxbuf);\n\telse\n\t\thw->vtnet_hdr_size = sizeof(struct virtio_net_hdr);\n\n\t/* Copy the permanent MAC address to: virtio_hw */\n\tvirtio_get_hwaddr(hw);\n\tether_addr_copy((struct ether_addr *) hw->mac_addr,\n\t\t\tð_dev->data->mac_addrs[0]);\n\tPMD_INIT_LOG(DEBUG,\n\t\t \"PORT MAC: %02X:%02X:%02X:%02X:%02X:%02X\",\n\t\t hw->mac_addr[0], hw->mac_addr[1], hw->mac_addr[2],\n\t\t hw->mac_addr[3], hw->mac_addr[4], hw->mac_addr[5]);\n\n\tif (vtpci_with_feature(hw, VIRTIO_NET_F_CTRL_VQ)) {\n\t\tconfig = &local_config;\n\n\t\tif (vtpci_with_feature(hw, VIRTIO_NET_F_STATUS)) {\n\t\t\toffset_conf += sizeof(config->status);\n\t\t} else {\n\t\t\tPMD_INIT_LOG(DEBUG,\n\t\t\t\t \"VIRTIO_NET_F_STATUS is not supported\");\n\t\t\tconfig->status = 0;\n\t\t}\n\n\t\tif (vtpci_with_feature(hw, VIRTIO_NET_F_MQ)) {\n\t\t\toffset_conf += sizeof(config->max_virtqueue_pairs);\n\t\t} else {\n\t\t\tPMD_INIT_LOG(DEBUG,\n\t\t\t\t \"VIRTIO_NET_F_MQ is not supported\");\n\t\t\tconfig->max_virtqueue_pairs = 1;\n\t\t}\n\n\t\tvtpci_read_dev_config(hw, 0, (uint8_t *)config, offset_conf);\n\n\t\thw->max_rx_queues =\n\t\t\t(VIRTIO_MAX_RX_QUEUES < config->max_virtqueue_pairs) ?\n\t\t\tVIRTIO_MAX_RX_QUEUES : config->max_virtqueue_pairs;\n\t\thw->max_tx_queues =\n\t\t\t(VIRTIO_MAX_TX_QUEUES < config->max_virtqueue_pairs) ?\n\t\t\tVIRTIO_MAX_TX_QUEUES : config->max_virtqueue_pairs;\n\n\t\tvirtio_dev_cq_queue_setup(eth_dev,\n\t\t\t\t\tconfig->max_virtqueue_pairs * 2,\n\t\t\t\t\tSOCKET_ID_ANY);\n\n\t\tPMD_INIT_LOG(DEBUG, \"config->max_virtqueue_pairs=%d\",\n\t\t\t\tconfig->max_virtqueue_pairs);\n\t\tPMD_INIT_LOG(DEBUG, \"config->status=%d\", config->status);\n\t\tPMD_INIT_LOG(DEBUG,\n\t\t\t\t\"PORT MAC: %02X:%02X:%02X:%02X:%02X:%02X\",\n\t\t\t\tconfig->mac[0], config->mac[1],\n\t\t\t\tconfig->mac[2], config->mac[3],\n\t\t\t\tconfig->mac[4], config->mac[5]);\n\t} else {\n\t\thw->max_rx_queues = 1;\n\t\thw->max_tx_queues = 1;\n\t}\n\n\teth_dev->data->nb_rx_queues = hw->max_rx_queues;\n\teth_dev->data->nb_tx_queues = hw->max_tx_queues;\n\n\tPMD_INIT_LOG(DEBUG, \"hw->max_rx_queues=%d hw->max_tx_queues=%d\",\n\t\t\thw->max_rx_queues, hw->max_tx_queues);\n\tPMD_INIT_LOG(DEBUG, \"port %d vendorID=0x%x deviceID=0x%x\",\n\t\t\teth_dev->data->port_id, pci_dev->id.vendor_id,\n\t\t\tpci_dev->id.device_id);\n\n\t/* Setup interrupt callback */\n\tif (pci_dev->driver->drv_flags & RTE_PCI_DRV_INTR_LSC)\n\t\trte_intr_callback_register(&pci_dev->intr_handle,\n\t\t\t\t virtio_interrupt_handler, eth_dev);\n\n\tvirtio_dev_cq_start(eth_dev);\n\n\treturn 0;\n}\n\nstatic int\neth_virtio_dev_uninit(struct rte_eth_dev *eth_dev)\n{\n\tstruct rte_pci_device *pci_dev;\n\tstruct virtio_hw *hw = eth_dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (rte_eal_process_type() == RTE_PROC_SECONDARY)\n\t\treturn -EPERM;\n\n\tif (hw->started == 1) {\n\t\tvirtio_dev_stop(eth_dev);\n\t\tvirtio_dev_close(eth_dev);\n\t}\n\tpci_dev = eth_dev->pci_dev;\n\n\teth_dev->dev_ops = NULL;\n\teth_dev->tx_pkt_burst = NULL;\n\teth_dev->rx_pkt_burst = NULL;\n\n\tvirtio_dev_queue_release(hw->cvq);\n\n\trte_free(eth_dev->data->mac_addrs);\n\teth_dev->data->mac_addrs = NULL;\n\n\t/* reset interrupt callback */\n\tif (pci_dev->driver->drv_flags & RTE_PCI_DRV_INTR_LSC)\n\t\trte_intr_callback_unregister(&pci_dev->intr_handle,\n\t\t\t\t\t\tvirtio_interrupt_handler,\n\t\t\t\t\t\teth_dev);\n\n\tPMD_INIT_LOG(DEBUG, \"dev_uninit completed\");\n\n\treturn 0;\n}\n\nstatic struct eth_driver rte_virtio_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_virtio_pmd\",\n\t\t.id_table = pci_id_virtio_map,\n\t\t.drv_flags = RTE_PCI_DRV_DETACHABLE,\n\t},\n\t.eth_dev_init = eth_virtio_dev_init,\n\t.eth_dev_uninit = eth_virtio_dev_uninit,\n\t.dev_private_size = sizeof(struct virtio_hw),\n};\n\n/*\n * Driver initialization routine.\n * Invoked once at EAL init time.\n * Register itself as the [Poll Mode] Driver of PCI virtio devices.\n * Returns 0 on success.\n */\nstatic int\nrte_virtio_pmd_init(const char *name __rte_unused,\n\t\t const char *param __rte_unused)\n{\n\tif (rte_eal_iopl_init() != 0) {\n\t\tPMD_INIT_LOG(ERR, \"IOPL call failed - cannot use virtio PMD\");\n\t\treturn -1;\n\t}\n\n\trte_eth_driver_register(&rte_virtio_pmd);\n\treturn 0;\n}\n\n/*\n * Configure virtio device\n * It returns 0 on success.\n */\nstatic int\nvirtio_dev_configure(struct rte_eth_dev *dev)\n{\n\tconst struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tstruct rte_pci_device *pci_dev = dev->pci_dev;\n\n\tPMD_INIT_LOG(DEBUG, \"configure\");\n\n\tif (rxmode->hw_ip_checksum) {\n\t\tPMD_DRV_LOG(ERR, \"HW IP checksum not supported\");\n\t\treturn (-EINVAL);\n\t}\n\n\thw->vlan_strip = rxmode->hw_vlan_strip;\n\n\tif (rxmode->hw_vlan_filter\n\t && !vtpci_with_feature(hw, VIRTIO_NET_F_CTRL_VLAN)) {\n\t\tPMD_DRV_LOG(NOTICE,\n\t\t\t \"vlan filtering not available on this host\");\n\t\treturn -ENOTSUP;\n\t}\n\n\tif (pci_dev->driver->drv_flags & RTE_PCI_DRV_INTR_LSC)\n\t\tif (vtpci_irq_config(hw, 0) == VIRTIO_MSI_NO_VECTOR) {\n\t\t\tPMD_DRV_LOG(ERR, \"failed to set config vector\");\n\t\t\treturn -EBUSY;\n\t\t}\n\n\treturn 0;\n}\n\n\nstatic int\nvirtio_dev_start(struct rte_eth_dev *dev)\n{\n\tuint16_t nb_queues, i;\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tstruct rte_pci_device *pci_dev = dev->pci_dev;\n\n\t/* check if lsc interrupt feature is enabled */\n\tif ((dev->data->dev_conf.intr_conf.lsc) &&\n\t\t(pci_dev->driver->drv_flags & RTE_PCI_DRV_INTR_LSC)) {\n\t\tif (!vtpci_with_feature(hw, VIRTIO_NET_F_STATUS)) {\n\t\t\tPMD_DRV_LOG(ERR, \"link status not supported by host\");\n\t\t\treturn -ENOTSUP;\n\t\t}\n\n\t\tif (rte_intr_enable(&dev->pci_dev->intr_handle) < 0) {\n\t\t\tPMD_DRV_LOG(ERR, \"interrupt enable failed\");\n\t\t\treturn -EIO;\n\t\t}\n\t}\n\n\t/* Initialize Link state */\n\tvirtio_dev_link_update(dev, 0);\n\n\t/* On restart after stop do not touch queues */\n\tif (hw->started)\n\t\treturn 0;\n\n\t/* Do final configuration before rx/tx engine starts */\n\tvirtio_dev_rxtx_start(dev);\n\tvtpci_reinit_complete(hw);\n\n\thw->started = 1;\n\n\t/*Notify the backend\n\t *Otherwise the tap backend might already stop its queue due to fullness.\n\t *vhost backend will have no chance to be waked up\n\t */\n\tnb_queues = dev->data->nb_rx_queues;\n\tif (nb_queues > 1) {\n\t\tif (virtio_set_multiple_queues(dev, nb_queues) != 0)\n\t\t\treturn -EINVAL;\n\t}\n\n\tPMD_INIT_LOG(DEBUG, \"nb_queues=%d\", nb_queues);\n\n\tfor (i = 0; i < nb_queues; i++)\n\t\tvirtqueue_notify(dev->data->rx_queues[i]);\n\n\tPMD_INIT_LOG(DEBUG, \"Notified backend at initialization\");\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n\t\tVIRTQUEUE_DUMP((struct virtqueue *)dev->data->rx_queues[i]);\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++)\n\t\tVIRTQUEUE_DUMP((struct virtqueue *)dev->data->tx_queues[i]);\n\n\treturn 0;\n}\n\nstatic void virtio_dev_free_mbufs(struct rte_eth_dev *dev)\n{\n\tstruct rte_mbuf *buf;\n\tint i, mbuf_num = 0;\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tPMD_INIT_LOG(DEBUG,\n\t\t\t \"Before freeing rxq[%d] used and unused buf\", i);\n\t\tVIRTQUEUE_DUMP((struct virtqueue *)dev->data->rx_queues[i]);\n\n\t\tPMD_INIT_LOG(DEBUG, \"rx_queues[%d]=%p\",\n\t\t\t\ti, dev->data->rx_queues[i]);\n\t\twhile ((buf = (struct rte_mbuf *)virtqueue_detatch_unused(\n\t\t\t\t\tdev->data->rx_queues[i])) != NULL) {\n\t\t\trte_pktmbuf_free(buf);\n\t\t\tmbuf_num++;\n\t\t}\n\n\t\tPMD_INIT_LOG(DEBUG, \"free %d mbufs\", mbuf_num);\n\t\tPMD_INIT_LOG(DEBUG,\n\t\t\t \"After freeing rxq[%d] used and unused buf\", i);\n\t\tVIRTQUEUE_DUMP((struct virtqueue *)dev->data->rx_queues[i]);\n\t}\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tPMD_INIT_LOG(DEBUG,\n\t\t\t \"Before freeing txq[%d] used and unused bufs\",\n\t\t\t i);\n\t\tVIRTQUEUE_DUMP((struct virtqueue *)dev->data->tx_queues[i]);\n\n\t\tmbuf_num = 0;\n\t\twhile ((buf = (struct rte_mbuf *)virtqueue_detatch_unused(\n\t\t\t\t\tdev->data->tx_queues[i])) != NULL) {\n\t\t\trte_pktmbuf_free(buf);\n\n\t\t\tmbuf_num++;\n\t\t}\n\n\t\tPMD_INIT_LOG(DEBUG, \"free %d mbufs\", mbuf_num);\n\t\tPMD_INIT_LOG(DEBUG,\n\t\t\t \"After freeing txq[%d] used and unused buf\", i);\n\t\tVIRTQUEUE_DUMP((struct virtqueue *)dev->data->tx_queues[i]);\n\t}\n}\n\n/*\n * Stop device: disable interrupt and mark link down\n */\nstatic void\nvirtio_dev_stop(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_link link;\n\n\tPMD_INIT_LOG(DEBUG, \"stop\");\n\n\tif (dev->data->dev_conf.intr_conf.lsc)\n\t\trte_intr_disable(&dev->pci_dev->intr_handle);\n\n\tmemset(&link, 0, sizeof(link));\n\tvirtio_dev_atomic_write_link_status(dev, &link);\n}\n\nstatic int\nvirtio_dev_link_update(struct rte_eth_dev *dev, __rte_unused int wait_to_complete)\n{\n\tstruct rte_eth_link link, old;\n\tuint16_t status;\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\tmemset(&link, 0, sizeof(link));\n\tvirtio_dev_atomic_read_link_status(dev, &link);\n\told = link;\n\tlink.link_duplex = FULL_DUPLEX;\n\tlink.link_speed = SPEED_10G;\n\n\tif (vtpci_with_feature(hw, VIRTIO_NET_F_STATUS)) {\n\t\tPMD_INIT_LOG(DEBUG, \"Get link status from hw\");\n\t\tvtpci_read_dev_config(hw,\n\t\t\t\toffsetof(struct virtio_net_config, status),\n\t\t\t\t&status, sizeof(status));\n\t\tif ((status & VIRTIO_NET_S_LINK_UP) == 0) {\n\t\t\tlink.link_status = 0;\n\t\t\tPMD_INIT_LOG(DEBUG, \"Port %d is down\",\n\t\t\t\t dev->data->port_id);\n\t\t} else {\n\t\t\tlink.link_status = 1;\n\t\t\tPMD_INIT_LOG(DEBUG, \"Port %d is up\",\n\t\t\t\t dev->data->port_id);\n\t\t}\n\t} else {\n\t\tlink.link_status = 1; /* Link up */\n\t}\n\tvirtio_dev_atomic_write_link_status(dev, &link);\n\n\treturn (old.link_status == link.link_status) ? -1 : 0;\n}\n\nstatic void\nvirtio_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n{\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\n\tdev_info->driver_name = dev->driver->pci_drv.name;\n\tdev_info->max_rx_queues = (uint16_t)hw->max_rx_queues;\n\tdev_info->max_tx_queues = (uint16_t)hw->max_tx_queues;\n\tdev_info->min_rx_bufsize = VIRTIO_MIN_RX_BUFSIZE;\n\tdev_info->max_rx_pktlen = VIRTIO_MAX_RX_PKTLEN;\n\tdev_info->max_mac_addrs = VIRTIO_MAX_MAC_ADDRS;\n\tdev_info->default_txconf = (struct rte_eth_txconf) {\n\t\t.txq_flags = ETH_TXQ_FLAGS_NOOFFLOADS\n\t};\n}\n\n/*\n * It enables testpmd to collect per queue stats.\n */\nstatic int\nvirtio_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *eth_dev,\n__rte_unused uint16_t queue_id, __rte_unused uint8_t stat_idx,\n__rte_unused uint8_t is_rx)\n{\n\treturn 0;\n}\n\nstatic struct rte_driver rte_virtio_driver = {\n\t.type = PMD_PDEV,\n\t.init = rte_virtio_pmd_init,\n};\n\nPMD_REGISTER_DRIVER(rte_virtio_driver);\n" }, { "path": "drivers/net/virtio/virtio_ethdev.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VIRTIO_ETHDEV_H_\n#define _VIRTIO_ETHDEV_H_\n\n#include \n\n#include \"virtio_pci.h\"\n\n#define SPEED_10\t10\n#define SPEED_100\t100\n#define SPEED_1000\t1000\n#define SPEED_10G\t10000\n#define HALF_DUPLEX\t1\n#define FULL_DUPLEX\t2\n\n#ifndef PAGE_SIZE\n#define PAGE_SIZE 4096\n#endif\n\n#define VIRTIO_MAX_RX_QUEUES 128\n#define VIRTIO_MAX_TX_QUEUES 128\n#define VIRTIO_MAX_MAC_ADDRS 64\n#define VIRTIO_MIN_RX_BUFSIZE 64\n#define VIRTIO_MAX_RX_PKTLEN 9728\n\n/* Features desired/implemented by this driver. */\n#define VIRTIO_PMD_GUEST_FEATURES\t\t\\\n\t(1u << VIRTIO_NET_F_MAC\t\t |\t\\\n\t 1u << VIRTIO_NET_F_STATUS\t |\t\\\n\t 1u << VIRTIO_NET_F_MQ\t\t |\t\\\n\t 1u << VIRTIO_NET_F_CTRL_MAC_ADDR |\t\\\n\t 1u << VIRTIO_NET_F_CTRL_VQ\t |\t\\\n\t 1u << VIRTIO_NET_F_CTRL_RX\t |\t\\\n\t 1u << VIRTIO_NET_F_CTRL_VLAN\t |\t\\\n\t 1u << VIRTIO_NET_F_MRG_RXBUF)\n\n/*\n * CQ function prototype\n */\nvoid virtio_dev_cq_start(struct rte_eth_dev *dev);\n\n/*\n * RX/TX function prototypes\n */\nvoid virtio_dev_rxtx_start(struct rte_eth_dev *dev);\n\nint virtio_dev_queue_setup(struct rte_eth_dev *dev,\n\t\t\tint queue_type,\n\t\t\tuint16_t queue_idx,\n\t\t\tuint16_t vtpci_queue_idx,\n\t\t\tuint16_t nb_desc,\n\t\t\tunsigned int socket_id,\n\t\t\tstruct virtqueue **pvq);\n\nvoid virtio_dev_queue_release(struct virtqueue *vq);\n\nint virtio_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n\t\tuint16_t nb_rx_desc, unsigned int socket_id,\n\t\tconst struct rte_eth_rxconf *rx_conf,\n\t\tstruct rte_mempool *mb_pool);\n\nvoid virtio_dev_rx_queue_release(void *rxq);\n\nint virtio_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n\t\tuint16_t nb_tx_desc, unsigned int socket_id,\n\t\tconst struct rte_eth_txconf *tx_conf);\n\nvoid virtio_dev_tx_queue_release(void *txq);\n\nuint16_t virtio_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts);\n\nuint16_t virtio_recv_mergeable_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts);\n\nuint16_t virtio_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t\tuint16_t nb_pkts);\n\n\n/*\n * The VIRTIO_NET_F_GUEST_TSO[46] features permit the host to send us\n * frames larger than 1514 bytes. We do not yet support software LRO\n * via tcp_lro_rx().\n */\n#define VTNET_LRO_FEATURES (VIRTIO_NET_F_GUEST_TSO4 | \\\n\t\t\t VIRTIO_NET_F_GUEST_TSO6 | VIRTIO_NET_F_GUEST_ECN)\n\n\n#endif /* _VIRTIO_ETHDEV_H_ */\n" }, { "path": "drivers/net/virtio/virtio_logs.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VIRTIO_LOGS_H_\n#define _VIRTIO_LOGS_H_\n\n#include \n\n#ifdef RTE_LIBRTE_VIRTIO_DEBUG_INIT\n#define PMD_INIT_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, \" >>\")\n#else\n#define PMD_INIT_LOG(level, fmt, args...) do { } while(0)\n#define PMD_INIT_FUNC_TRACE() do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_VIRTIO_DEBUG_RX\n#define PMD_RX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s() rx: \" fmt , __func__, ## args)\n#else\n#define PMD_RX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_VIRTIO_DEBUG_TX\n#define PMD_TX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s() tx: \" fmt , __func__, ## args)\n#else\n#define PMD_TX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n\n#ifdef RTE_LIBRTE_VIRTIO_DEBUG_DRIVER\n#define PMD_DRV_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt , __func__, ## args)\n#else\n#define PMD_DRV_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#endif /* _VIRTIO_LOGS_H_ */\n" }, { "path": "drivers/net/virtio/virtio_pci.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n\n#include \"virtio_pci.h\"\n#include \"virtio_logs.h\"\n\nstatic uint8_t vtpci_get_status(struct virtio_hw *);\n\nvoid\nvtpci_read_dev_config(struct virtio_hw *hw, uint64_t offset,\n\t\tvoid *dst, int length)\n{\n\tuint64_t off;\n\tuint8_t *d;\n\tint size;\n\n\toff = VIRTIO_PCI_CONFIG(hw) + offset;\n\tfor (d = dst; length > 0; d += size, off += size, length -= size) {\n\t\tif (length >= 4) {\n\t\t\tsize = 4;\n\t\t\t*(uint32_t *)d = VIRTIO_READ_REG_4(hw, off);\n\t\t} else if (length >= 2) {\n\t\t\tsize = 2;\n\t\t\t*(uint16_t *)d = VIRTIO_READ_REG_2(hw, off);\n\t\t} else {\n\t\t\tsize = 1;\n\t\t\t*d = VIRTIO_READ_REG_1(hw, off);\n\t\t}\n\t}\n}\n\nvoid\nvtpci_write_dev_config(struct virtio_hw *hw, uint64_t offset,\n\t\tvoid *src, int length)\n{\n\tuint64_t off;\n\tuint8_t *s;\n\tint size;\n\n\toff = VIRTIO_PCI_CONFIG(hw) + offset;\n\tfor (s = src; length > 0; s += size, off += size, length -= size) {\n\t\tif (length >= 4) {\n\t\t\tsize = 4;\n\t\t\tVIRTIO_WRITE_REG_4(hw, off, *(uint32_t *)s);\n\t\t} else if (length >= 2) {\n\t\t\tsize = 2;\n\t\t\tVIRTIO_WRITE_REG_2(hw, off, *(uint16_t *)s);\n\t\t} else {\n\t\t\tsize = 1;\n\t\t\tVIRTIO_WRITE_REG_1(hw, off, *s);\n\t\t}\n\t}\n}\n\nuint32_t\nvtpci_negotiate_features(struct virtio_hw *hw, uint32_t host_features)\n{\n\tuint32_t features;\n\t/*\n\t * Limit negotiated features to what the driver, virtqueue, and\n\t * host all support.\n\t */\n\tfeatures = host_features & hw->guest_features;\n\n\tVIRTIO_WRITE_REG_4(hw, VIRTIO_PCI_GUEST_FEATURES, features);\n\treturn features;\n}\n\n\nvoid\nvtpci_reset(struct virtio_hw *hw)\n{\n\t/*\n\t * Setting the status to RESET sets the host device to\n\t * the original, uninitialized state.\n\t */\n\tvtpci_set_status(hw, VIRTIO_CONFIG_STATUS_RESET);\n\tvtpci_get_status(hw);\n}\n\nvoid\nvtpci_reinit_complete(struct virtio_hw *hw)\n{\n\tvtpci_set_status(hw, VIRTIO_CONFIG_STATUS_DRIVER_OK);\n}\n\nstatic uint8_t\nvtpci_get_status(struct virtio_hw *hw)\n{\n\treturn VIRTIO_READ_REG_1(hw, VIRTIO_PCI_STATUS);\n}\n\nvoid\nvtpci_set_status(struct virtio_hw *hw, uint8_t status)\n{\n\tif (status != VIRTIO_CONFIG_STATUS_RESET)\n\t\tstatus = (uint8_t)(status | vtpci_get_status(hw));\n\n\tVIRTIO_WRITE_REG_1(hw, VIRTIO_PCI_STATUS, status);\n}\n\nuint8_t\nvtpci_isr(struct virtio_hw *hw)\n{\n\n\treturn VIRTIO_READ_REG_1(hw, VIRTIO_PCI_ISR);\n}\n\n\n/* Enable one vector (0) for Link State Intrerrupt */\nuint16_t\nvtpci_irq_config(struct virtio_hw *hw, uint16_t vec)\n{\n\tVIRTIO_WRITE_REG_2(hw, VIRTIO_MSI_CONFIG_VECTOR, vec);\n\treturn VIRTIO_READ_REG_2(hw, VIRTIO_MSI_CONFIG_VECTOR);\n}\n" }, { "path": "drivers/net/virtio/virtio_pci.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VIRTIO_PCI_H_\n#define _VIRTIO_PCI_H_\n\n#include \n\n#ifdef __FreeBSD__\n#include \n#include \n#else\n#include \n#endif\n\n#include \n\nstruct virtqueue;\n\n/* VirtIO PCI vendor/device ID. */\n#define VIRTIO_PCI_VENDORID 0x1AF4\n#define VIRTIO_PCI_DEVICEID_MIN 0x1000\n#define VIRTIO_PCI_DEVICEID_MAX 0x103F\n\n/* VirtIO ABI version, this must match exactly. */\n#define VIRTIO_PCI_ABI_VERSION 0\n\n/*\n * VirtIO Header, located in BAR 0.\n */\n#define VIRTIO_PCI_HOST_FEATURES 0 /* host's supported features (32bit, RO)*/\n#define VIRTIO_PCI_GUEST_FEATURES 4 /* guest's supported features (32, RW) */\n#define VIRTIO_PCI_QUEUE_PFN 8 /* physical address of VQ (32, RW) */\n#define VIRTIO_PCI_QUEUE_NUM 12 /* number of ring entries (16, RO) */\n#define VIRTIO_PCI_QUEUE_SEL 14 /* current VQ selection (16, RW) */\n#define VIRTIO_PCI_QUEUE_NOTIFY 16 /* notify host regarding VQ (16, RW) */\n#define VIRTIO_PCI_STATUS 18 /* device status register (8, RW) */\n#define VIRTIO_PCI_ISR\t\t 19 /* interrupt status register, reading\n\t\t\t\t * also clears the register (8, RO) */\n/* Only if MSIX is enabled: */\n#define VIRTIO_MSI_CONFIG_VECTOR 20 /* configuration change vector (16, RW) */\n#define VIRTIO_MSI_QUEUE_VECTOR\t 22 /* vector for selected VQ notifications\n\t\t\t\t (16, RW) */\n\n/* The bit of the ISR which indicates a device has an interrupt. */\n#define VIRTIO_PCI_ISR_INTR 0x1\n/* The bit of the ISR which indicates a device configuration change. */\n#define VIRTIO_PCI_ISR_CONFIG 0x2\n/* Vector value used to disable MSI for queue. */\n#define VIRTIO_MSI_NO_VECTOR 0xFFFF\n\n/* VirtIO device IDs. */\n#define VIRTIO_ID_NETWORK 0x01\n#define VIRTIO_ID_BLOCK 0x02\n#define VIRTIO_ID_CONSOLE 0x03\n#define VIRTIO_ID_ENTROPY 0x04\n#define VIRTIO_ID_BALLOON 0x05\n#define VIRTIO_ID_IOMEMORY 0x06\n#define VIRTIO_ID_9P 0x09\n\n/* Status byte for guest to report progress. */\n#define VIRTIO_CONFIG_STATUS_RESET 0x00\n#define VIRTIO_CONFIG_STATUS_ACK 0x01\n#define VIRTIO_CONFIG_STATUS_DRIVER 0x02\n#define VIRTIO_CONFIG_STATUS_DRIVER_OK 0x04\n#define VIRTIO_CONFIG_STATUS_FAILED 0x80\n\n/*\n * Each virtqueue indirect descriptor list must be physically contiguous.\n * To allow us to malloc(9) each list individually, limit the number\n * supported to what will fit in one page. With 4KB pages, this is a limit\n * of 256 descriptors. If there is ever a need for more, we can switch to\n * contigmalloc(9) for the larger allocations, similar to what\n * bus_dmamem_alloc(9) does.\n *\n * Note the sizeof(struct vring_desc) is 16 bytes.\n */\n#define VIRTIO_MAX_INDIRECT ((int) (PAGE_SIZE / 16))\n\n/* The feature bitmap for virtio net */\n#define VIRTIO_NET_F_CSUM\t0\t/* Host handles pkts w/ partial csum */\n#define VIRTIO_NET_F_GUEST_CSUM\t1\t/* Guest handles pkts w/ partial csum */\n#define VIRTIO_NET_F_MAC\t5\t/* Host has given MAC address. */\n#define VIRTIO_NET_F_GUEST_TSO4\t7\t/* Guest can handle TSOv4 in. */\n#define VIRTIO_NET_F_GUEST_TSO6\t8\t/* Guest can handle TSOv6 in. */\n#define VIRTIO_NET_F_GUEST_ECN\t9\t/* Guest can handle TSO[6] w/ ECN in. */\n#define VIRTIO_NET_F_GUEST_UFO\t10\t/* Guest can handle UFO in. */\n#define VIRTIO_NET_F_HOST_TSO4\t11\t/* Host can handle TSOv4 in. */\n#define VIRTIO_NET_F_HOST_TSO6\t12\t/* Host can handle TSOv6 in. */\n#define VIRTIO_NET_F_HOST_ECN\t13\t/* Host can handle TSO[6] w/ ECN in. */\n#define VIRTIO_NET_F_HOST_UFO\t14\t/* Host can handle UFO in. */\n#define VIRTIO_NET_F_MRG_RXBUF\t15\t/* Host can merge receive buffers. */\n#define VIRTIO_NET_F_STATUS\t16\t/* virtio_net_config.status available */\n#define VIRTIO_NET_F_CTRL_VQ\t17\t/* Control channel available */\n#define VIRTIO_NET_F_CTRL_RX\t18\t/* Control channel RX mode support */\n#define VIRTIO_NET_F_CTRL_VLAN\t19\t/* Control channel VLAN filtering */\n#define VIRTIO_NET_F_CTRL_RX_EXTRA 20\t/* Extra RX mode control support */\n#define VIRTIO_NET_F_GUEST_ANNOUNCE 21\t/* Guest can announce device on the\n\t\t\t\t\t * network */\n#define VIRTIO_NET_F_MQ\t\t22\t/* Device supports Receive Flow\n\t\t\t\t\t * Steering */\n#define VIRTIO_NET_F_CTRL_MAC_ADDR 23\t/* Set MAC address */\n\n/* Do we get callbacks when the ring is completely used, even if we've\n * suppressed them? */\n#define VIRTIO_F_NOTIFY_ON_EMPTY\t24\n\n/* Can the device handle any descriptor layout? */\n#define VIRTIO_F_ANY_LAYOUT\t\t27\n\n/* We support indirect buffer descriptors */\n#define VIRTIO_RING_F_INDIRECT_DESC\t28\n\n/*\n * Some VirtIO feature bits (currently bits 28 through 31) are\n * reserved for the transport being used (eg. virtio_ring), the\n * rest are per-device feature bits.\n */\n#define VIRTIO_TRANSPORT_F_START 28\n#define VIRTIO_TRANSPORT_F_END 32\n\n/* The Guest publishes the used index for which it expects an interrupt\n * at the end of the avail ring. Host should ignore the avail->flags field. */\n/* The Host publishes the avail index for which it expects a kick\n * at the end of the used ring. Guest should ignore the used->flags field. */\n#define VIRTIO_RING_F_EVENT_IDX\t\t29\n\n#define VIRTIO_NET_S_LINK_UP\t1\t/* Link is up */\n#define VIRTIO_NET_S_ANNOUNCE\t2\t/* Announcement is needed */\n\n/*\n * Maximum number of virtqueues per device.\n */\n#define VIRTIO_MAX_VIRTQUEUES 8\n\nstruct virtio_hw {\n\tstruct virtqueue *cvq;\n\tuint32_t io_base;\n\tuint32_t guest_features;\n\tuint32_t max_tx_queues;\n\tuint32_t max_rx_queues;\n\tuint16_t vtnet_hdr_size;\n\tuint8_t\t vlan_strip;\n\tuint8_t\t use_msix;\n\tuint8_t started;\n\tuint8_t mac_addr[ETHER_ADDR_LEN];\n};\n\n/*\n * This structure is just a reference to read\n * net device specific config space; it just a chodu structure\n *\n */\nstruct virtio_net_config {\n\t/* The config defining mac address (if VIRTIO_NET_F_MAC) */\n\tuint8_t mac[ETHER_ADDR_LEN];\n\t/* See VIRTIO_NET_F_STATUS and VIRTIO_NET_S_* above */\n\tuint16_t status;\n\tuint16_t max_virtqueue_pairs;\n} __attribute__((packed));\n\n/*\n * The remaining space is defined by each driver as the per-driver\n * configuration space.\n */\n#define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20)\n\n/*\n * How many bits to shift physical queue address written to QUEUE_PFN.\n * 12 is historical, and due to x86 page size.\n */\n#define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12\n\n/* The alignment to use between consumer and producer parts of vring. */\n#define VIRTIO_PCI_VRING_ALIGN 4096\n\n#ifdef __FreeBSD__\n\nstatic inline void\noutb_p(unsigned char data, unsigned int port)\n{\n\n\toutb(port, (u_char)data);\n}\n\nstatic inline void\noutw_p(unsigned short data, unsigned int port)\n{\n\toutw(port, (u_short)data);\n}\n\nstatic inline void\noutl_p(unsigned int data, unsigned int port)\n{\n\toutl(port, (u_int)data);\n}\n#endif\n\n#define VIRTIO_PCI_REG_ADDR(hw, reg) \\\n\t(unsigned short)((hw)->io_base + (reg))\n\n#define VIRTIO_READ_REG_1(hw, reg) \\\n\tinb((VIRTIO_PCI_REG_ADDR((hw), (reg))))\n#define VIRTIO_WRITE_REG_1(hw, reg, value) \\\n\toutb_p((unsigned char)(value), (VIRTIO_PCI_REG_ADDR((hw), (reg))))\n\n#define VIRTIO_READ_REG_2(hw, reg) \\\n\tinw((VIRTIO_PCI_REG_ADDR((hw), (reg))))\n#define VIRTIO_WRITE_REG_2(hw, reg, value) \\\n\toutw_p((unsigned short)(value), (VIRTIO_PCI_REG_ADDR((hw), (reg))))\n\n#define VIRTIO_READ_REG_4(hw, reg) \\\n\tinl((VIRTIO_PCI_REG_ADDR((hw), (reg))))\n#define VIRTIO_WRITE_REG_4(hw, reg, value) \\\n\toutl_p((unsigned int)(value), (VIRTIO_PCI_REG_ADDR((hw), (reg))))\n\nstatic inline int\nvtpci_with_feature(struct virtio_hw *hw, uint32_t bit)\n{\n\treturn (hw->guest_features & (1u << bit)) != 0;\n}\n\n/*\n * Function declaration from virtio_pci.c\n */\nvoid vtpci_reset(struct virtio_hw *);\n\nvoid vtpci_reinit_complete(struct virtio_hw *);\n\nvoid vtpci_set_status(struct virtio_hw *, uint8_t);\n\nuint32_t vtpci_negotiate_features(struct virtio_hw *, uint32_t);\n\nvoid vtpci_write_dev_config(struct virtio_hw *, uint64_t, void *, int);\n\nvoid vtpci_read_dev_config(struct virtio_hw *, uint64_t, void *, int);\n\nuint8_t vtpci_isr(struct virtio_hw *);\n\nuint16_t vtpci_irq_config(struct virtio_hw *, uint16_t);\n\n#endif /* _VIRTIO_PCI_H_ */\n" }, { "path": "drivers/net/virtio/virtio_ring.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VIRTIO_RING_H_\n#define _VIRTIO_RING_H_\n\n#include \n\n#include \n\n/* This marks a buffer as continuing via the next field. */\n#define VRING_DESC_F_NEXT 1\n/* This marks a buffer as write-only (otherwise read-only). */\n#define VRING_DESC_F_WRITE 2\n/* This means the buffer contains a list of buffer descriptors. */\n#define VRING_DESC_F_INDIRECT 4\n\n/* The Host uses this in used->flags to advise the Guest: don't kick me\n * when you add a buffer. It's unreliable, so it's simply an\n * optimization. Guest will still kick if it's out of buffers. */\n#define VRING_USED_F_NO_NOTIFY 1\n/* The Guest uses this in avail->flags to advise the Host: don't\n * interrupt me when you consume a buffer. It's unreliable, so it's\n * simply an optimization. */\n#define VRING_AVAIL_F_NO_INTERRUPT 1\n\n/* VirtIO ring descriptors: 16 bytes.\n * These can chain together via \"next\". */\nstruct vring_desc {\n\tuint64_t addr; /* Address (guest-physical). */\n\tuint32_t len; /* Length. */\n\tuint16_t flags; /* The flags as indicated above. */\n\tuint16_t next; /* We chain unused descriptors via this. */\n};\n\nstruct vring_avail {\n\tuint16_t flags;\n\tuint16_t idx;\n\tuint16_t ring[0];\n};\n\n/* id is a 16bit index. uint32_t is used here for ids for padding reasons. */\nstruct vring_used_elem {\n\t/* Index of start of used descriptor chain. */\n\tuint32_t id;\n\t/* Total length of the descriptor chain which was written to. */\n\tuint32_t len;\n};\n\nstruct vring_used {\n\tuint16_t flags;\n\tuint16_t idx;\n\tstruct vring_used_elem ring[0];\n};\n\nstruct vring {\n\tunsigned int num;\n\tstruct vring_desc *desc;\n\tstruct vring_avail *avail;\n\tstruct vring_used *used;\n};\n\n/* The standard layout for the ring is a continuous chunk of memory which\n * looks like this. We assume num is a power of 2.\n *\n * struct vring {\n * // The actual descriptors (16 bytes each)\n * struct vring_desc desc[num];\n *\n * // A ring of available descriptor heads with free-running index.\n * __u16 avail_flags;\n * __u16 avail_idx;\n * __u16 available[num];\n * __u16 used_event_idx;\n *\n * // Padding to the next align boundary.\n * char pad[];\n *\n * // A ring of used descriptor heads with free-running index.\n * __u16 used_flags;\n * __u16 used_idx;\n * struct vring_used_elem used[num];\n * __u16 avail_event_idx;\n * };\n *\n * NOTE: for VirtIO PCI, align is 4096.\n */\n\n/*\n * We publish the used event index at the end of the available ring, and vice\n * versa. They are at the end for backwards compatibility.\n */\n#define vring_used_event(vr) ((vr)->avail->ring[(vr)->num])\n#define vring_avail_event(vr) (*(uint16_t *)&(vr)->used->ring[(vr)->num])\n\nstatic inline int\nvring_size(unsigned int num, unsigned long align)\n{\n\tint size;\n\n\tsize = num * sizeof(struct vring_desc);\n\tsize += sizeof(struct vring_avail) + (num * sizeof(uint16_t));\n\tsize = RTE_ALIGN_CEIL(size, align);\n\tsize += sizeof(struct vring_used) +\n\t\t(num * sizeof(struct vring_used_elem));\n\treturn size;\n}\n\nstatic inline void\nvring_init(struct vring *vr, unsigned int num, uint8_t *p,\n\tunsigned long align)\n{\n\tvr->num = num;\n\tvr->desc = (struct vring_desc *) p;\n\tvr->avail = (struct vring_avail *) (p +\n\t\tnum * sizeof(struct vring_desc));\n\tvr->used = (void *)\n\t\tRTE_ALIGN_CEIL((uintptr_t)(&vr->avail->ring[num]), align);\n}\n\n/*\n * The following is used with VIRTIO_RING_F_EVENT_IDX.\n * Assuming a given event_idx value from the other size, if we have\n * just incremented index from old to new_idx, should we trigger an\n * event?\n */\nstatic inline int\nvring_need_event(uint16_t event_idx, uint16_t new_idx, uint16_t old)\n{\n\treturn (uint16_t)(new_idx - event_idx - 1) < (uint16_t)(new_idx - old);\n}\n\n#endif /* _VIRTIO_RING_H_ */\n" }, { "path": "drivers/net/virtio/virtio_rxtx.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"virtio_logs.h\"\n#include \"virtio_ethdev.h\"\n#include \"virtqueue.h\"\n\n#ifdef RTE_LIBRTE_VIRTIO_DEBUG_DUMP\n#define VIRTIO_DUMP_PACKET(m, len) rte_pktmbuf_dump(stdout, m, len)\n#else\n#define VIRTIO_DUMP_PACKET(m, len) do { } while (0)\n#endif\n\nstatic void\nvq_ring_free_chain(struct virtqueue *vq, uint16_t desc_idx)\n{\n\tstruct vring_desc *dp, *dp_tail;\n\tstruct vq_desc_extra *dxp;\n\tuint16_t desc_idx_last = desc_idx;\n\n\tdp = &vq->vq_ring.desc[desc_idx];\n\tdxp = &vq->vq_descx[desc_idx];\n\tvq->vq_free_cnt = (uint16_t)(vq->vq_free_cnt + dxp->ndescs);\n\tif ((dp->flags & VRING_DESC_F_INDIRECT) == 0) {\n\t\twhile (dp->flags & VRING_DESC_F_NEXT) {\n\t\t\tdesc_idx_last = dp->next;\n\t\t\tdp = &vq->vq_ring.desc[dp->next];\n\t\t}\n\t}\n\tdxp->ndescs = 0;\n\n\t/*\n\t * We must append the existing free chain, if any, to the end of\n\t * newly freed chain. If the virtqueue was completely used, then\n\t * head would be VQ_RING_DESC_CHAIN_END (ASSERTed above).\n\t */\n\tif (vq->vq_desc_tail_idx == VQ_RING_DESC_CHAIN_END) {\n\t\tvq->vq_desc_head_idx = desc_idx;\n\t} else {\n\t\tdp_tail = &vq->vq_ring.desc[vq->vq_desc_tail_idx];\n\t\tdp_tail->next = desc_idx;\n\t}\n\n\tvq->vq_desc_tail_idx = desc_idx_last;\n\tdp->next = VQ_RING_DESC_CHAIN_END;\n}\n\nstatic uint16_t\nvirtqueue_dequeue_burst_rx(struct virtqueue *vq, struct rte_mbuf **rx_pkts,\n\t\t\t uint32_t *len, uint16_t num)\n{\n\tstruct vring_used_elem *uep;\n\tstruct rte_mbuf *cookie;\n\tuint16_t used_idx, desc_idx;\n\tuint16_t i;\n\n\t/* Caller does the check */\n\tfor (i = 0; i < num ; i++) {\n\t\tused_idx = (uint16_t)(vq->vq_used_cons_idx & (vq->vq_nentries - 1));\n\t\tuep = &vq->vq_ring.used->ring[used_idx];\n\t\tdesc_idx = (uint16_t) uep->id;\n\t\tlen[i] = uep->len;\n\t\tcookie = (struct rte_mbuf *)vq->vq_descx[desc_idx].cookie;\n\n\t\tif (unlikely(cookie == NULL)) {\n\t\t\tPMD_DRV_LOG(ERR, \"vring descriptor with no mbuf cookie at %u\\n\",\n\t\t\t\tvq->vq_used_cons_idx);\n\t\t\tbreak;\n\t\t}\n\n\t\trte_prefetch0(cookie);\n\t\trte_packet_prefetch(rte_pktmbuf_mtod(cookie, void *));\n\t\trx_pkts[i] = cookie;\n\t\tvq->vq_used_cons_idx++;\n\t\tvq_ring_free_chain(vq, desc_idx);\n\t\tvq->vq_descx[desc_idx].cookie = NULL;\n\t}\n\n\treturn i;\n}\n\n#ifndef DEFAULT_TX_FREE_THRESH\n#define DEFAULT_TX_FREE_THRESH 32\n#endif\n\n/* Cleanup from completed transmits. */\nstatic void\nvirtio_xmit_cleanup(struct virtqueue *vq, uint16_t num)\n{\n\tuint16_t i, used_idx, desc_idx;\n\tfor (i = 0; i < num; i++) {\n\t\tstruct vring_used_elem *uep;\n\t\tstruct vq_desc_extra *dxp;\n\n\t\tused_idx = (uint16_t)(vq->vq_used_cons_idx & (vq->vq_nentries - 1));\n\t\tuep = &vq->vq_ring.used->ring[used_idx];\n\n\t\tdesc_idx = (uint16_t) uep->id;\n\t\tdxp = &vq->vq_descx[desc_idx];\n\t\tvq->vq_used_cons_idx++;\n\t\tvq_ring_free_chain(vq, desc_idx);\n\n\t\tif (dxp->cookie != NULL) {\n\t\t\trte_pktmbuf_free(dxp->cookie);\n\t\t\tdxp->cookie = NULL;\n\t\t}\n\t}\n}\n\n\nstatic inline int\nvirtqueue_enqueue_recv_refill(struct virtqueue *vq, struct rte_mbuf *cookie)\n{\n\tstruct vq_desc_extra *dxp;\n\tstruct virtio_hw *hw = vq->hw;\n\tstruct vring_desc *start_dp;\n\tuint16_t needed = 1;\n\tuint16_t head_idx, idx;\n\n\tif (unlikely(vq->vq_free_cnt == 0))\n\t\treturn -ENOSPC;\n\tif (unlikely(vq->vq_free_cnt < needed))\n\t\treturn -EMSGSIZE;\n\n\thead_idx = vq->vq_desc_head_idx;\n\tif (unlikely(head_idx >= vq->vq_nentries))\n\t\treturn -EFAULT;\n\n\tidx = head_idx;\n\tdxp = &vq->vq_descx[idx];\n\tdxp->cookie = (void *)cookie;\n\tdxp->ndescs = needed;\n\n\tstart_dp = vq->vq_ring.desc;\n\tstart_dp[idx].addr =\n\t\t(uint64_t)(cookie->buf_physaddr + RTE_PKTMBUF_HEADROOM\n\t\t- hw->vtnet_hdr_size);\n\tstart_dp[idx].len =\n\t\tcookie->buf_len - RTE_PKTMBUF_HEADROOM + hw->vtnet_hdr_size;\n\tstart_dp[idx].flags = VRING_DESC_F_WRITE;\n\tidx = start_dp[idx].next;\n\tvq->vq_desc_head_idx = idx;\n\tif (vq->vq_desc_head_idx == VQ_RING_DESC_CHAIN_END)\n\t\tvq->vq_desc_tail_idx = idx;\n\tvq->vq_free_cnt = (uint16_t)(vq->vq_free_cnt - needed);\n\tvq_update_avail_ring(vq, head_idx);\n\n\treturn 0;\n}\n\nstatic int\nvirtqueue_enqueue_xmit(struct virtqueue *txvq, struct rte_mbuf *cookie)\n{\n\tstruct vq_desc_extra *dxp;\n\tstruct vring_desc *start_dp;\n\tuint16_t seg_num = cookie->nb_segs;\n\tuint16_t needed = 1 + seg_num;\n\tuint16_t head_idx, idx;\n\tuint16_t head_size = txvq->hw->vtnet_hdr_size;\n\n\tif (unlikely(txvq->vq_free_cnt == 0))\n\t\treturn -ENOSPC;\n\tif (unlikely(txvq->vq_free_cnt < needed))\n\t\treturn -EMSGSIZE;\n\thead_idx = txvq->vq_desc_head_idx;\n\tif (unlikely(head_idx >= txvq->vq_nentries))\n\t\treturn -EFAULT;\n\n\tidx = head_idx;\n\tdxp = &txvq->vq_descx[idx];\n\tdxp->cookie = (void *)cookie;\n\tdxp->ndescs = needed;\n\n\tstart_dp = txvq->vq_ring.desc;\n\tstart_dp[idx].addr =\n\t\ttxvq->virtio_net_hdr_mem + idx * head_size;\n\tstart_dp[idx].len = (uint32_t)head_size;\n\tstart_dp[idx].flags = VRING_DESC_F_NEXT;\n\n\tfor (; ((seg_num > 0) && (cookie != NULL)); seg_num--) {\n\t\tidx = start_dp[idx].next;\n\t\tstart_dp[idx].addr = RTE_MBUF_DATA_DMA_ADDR(cookie);\n\t\tstart_dp[idx].len = cookie->data_len;\n\t\tstart_dp[idx].flags = VRING_DESC_F_NEXT;\n\t\tcookie = cookie->next;\n\t}\n\n\tstart_dp[idx].flags &= ~VRING_DESC_F_NEXT;\n\tidx = start_dp[idx].next;\n\ttxvq->vq_desc_head_idx = idx;\n\tif (txvq->vq_desc_head_idx == VQ_RING_DESC_CHAIN_END)\n\t\ttxvq->vq_desc_tail_idx = idx;\n\ttxvq->vq_free_cnt = (uint16_t)(txvq->vq_free_cnt - needed);\n\tvq_update_avail_ring(txvq, head_idx);\n\n\treturn 0;\n}\n\nstatic inline struct rte_mbuf *\nrte_rxmbuf_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\n\tm = __rte_mbuf_raw_alloc(mp);\n\t__rte_mbuf_sanity_check_raw(m, 0);\n\n\treturn m;\n}\n\nstatic void\nvirtio_dev_vring_start(struct virtqueue *vq, int queue_type)\n{\n\tstruct rte_mbuf *m;\n\tint i, nbufs, error, size = vq->vq_nentries;\n\tstruct vring *vr = &vq->vq_ring;\n\tuint8_t *ring_mem = vq->vq_ring_virt_mem;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/*\n\t * Reinitialise since virtio port might have been stopped and restarted\n\t */\n\tmemset(vq->vq_ring_virt_mem, 0, vq->vq_ring_size);\n\tvring_init(vr, size, ring_mem, VIRTIO_PCI_VRING_ALIGN);\n\tvq->vq_used_cons_idx = 0;\n\tvq->vq_desc_head_idx = 0;\n\tvq->vq_avail_idx = 0;\n\tvq->vq_desc_tail_idx = (uint16_t)(vq->vq_nentries - 1);\n\tvq->vq_free_cnt = vq->vq_nentries;\n\tmemset(vq->vq_descx, 0, sizeof(struct vq_desc_extra) * vq->vq_nentries);\n\n\t/* Chain all the descriptors in the ring with an END */\n\tfor (i = 0; i < size - 1; i++)\n\t\tvr->desc[i].next = (uint16_t)(i + 1);\n\tvr->desc[i].next = VQ_RING_DESC_CHAIN_END;\n\n\t/*\n\t * Disable device(host) interrupting guest\n\t */\n\tvirtqueue_disable_intr(vq);\n\n\t/* Only rx virtqueue needs mbufs to be allocated at initialization */\n\tif (queue_type == VTNET_RQ) {\n\t\tif (vq->mpool == NULL)\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\"Cannot allocate initial mbufs for rx virtqueue\");\n\n\t\t/* Allocate blank mbufs for the each rx descriptor */\n\t\tnbufs = 0;\n\t\terror = ENOSPC;\n\t\twhile (!virtqueue_full(vq)) {\n\t\t\tm = rte_rxmbuf_alloc(vq->mpool);\n\t\t\tif (m == NULL)\n\t\t\t\tbreak;\n\n\t\t\t/******************************************\n\t\t\t* Enqueue allocated buffers *\n\t\t\t*******************************************/\n\t\t\terror = virtqueue_enqueue_recv_refill(vq, m);\n\n\t\t\tif (error) {\n\t\t\t\trte_pktmbuf_free(m);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tnbufs++;\n\t\t}\n\n\t\tvq_update_avail_idx(vq);\n\n\t\tPMD_INIT_LOG(DEBUG, \"Allocated %d bufs\", nbufs);\n\n\t\tVIRTIO_WRITE_REG_2(vq->hw, VIRTIO_PCI_QUEUE_SEL,\n\t\t\tvq->vq_queue_index);\n\t\tVIRTIO_WRITE_REG_4(vq->hw, VIRTIO_PCI_QUEUE_PFN,\n\t\t\tvq->mz->phys_addr >> VIRTIO_PCI_QUEUE_ADDR_SHIFT);\n\t} else if (queue_type == VTNET_TQ) {\n\t\tVIRTIO_WRITE_REG_2(vq->hw, VIRTIO_PCI_QUEUE_SEL,\n\t\t\tvq->vq_queue_index);\n\t\tVIRTIO_WRITE_REG_4(vq->hw, VIRTIO_PCI_QUEUE_PFN,\n\t\t\tvq->mz->phys_addr >> VIRTIO_PCI_QUEUE_ADDR_SHIFT);\n\t} else {\n\t\tVIRTIO_WRITE_REG_2(vq->hw, VIRTIO_PCI_QUEUE_SEL,\n\t\t\tvq->vq_queue_index);\n\t\tVIRTIO_WRITE_REG_4(vq->hw, VIRTIO_PCI_QUEUE_PFN,\n\t\t\tvq->mz->phys_addr >> VIRTIO_PCI_QUEUE_ADDR_SHIFT);\n\t}\n}\n\nvoid\nvirtio_dev_cq_start(struct rte_eth_dev *dev)\n{\n\tstruct virtio_hw *hw = dev->data->dev_private;\n\n\tif (hw->cvq) {\n\t\tvirtio_dev_vring_start(hw->cvq, VTNET_CQ);\n\t\tVIRTQUEUE_DUMP((struct virtqueue *)hw->cvq);\n\t}\n}\n\nvoid\nvirtio_dev_rxtx_start(struct rte_eth_dev *dev)\n{\n\t/*\n\t * Start receive and transmit vrings\n\t * -\tSetup vring structure for all queues\n\t * -\tInitialize descriptor for the rx vring\n\t * -\tAllocate blank mbufs for the each rx descriptor\n\t *\n\t */\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\t/* Start rx vring. */\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tvirtio_dev_vring_start(dev->data->rx_queues[i], VTNET_RQ);\n\t\tVIRTQUEUE_DUMP((struct virtqueue *)dev->data->rx_queues[i]);\n\t}\n\n\t/* Start tx vring. */\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tvirtio_dev_vring_start(dev->data->tx_queues[i], VTNET_TQ);\n\t\tVIRTQUEUE_DUMP((struct virtqueue *)dev->data->tx_queues[i]);\n\t}\n}\n\nint\nvirtio_dev_rx_queue_setup(struct rte_eth_dev *dev,\n\t\t\tuint16_t queue_idx,\n\t\t\tuint16_t nb_desc,\n\t\t\tunsigned int socket_id,\n\t\t\t__rte_unused const struct rte_eth_rxconf *rx_conf,\n\t\t\tstruct rte_mempool *mp)\n{\n\tuint16_t vtpci_queue_idx = 2 * queue_idx + VTNET_SQ_RQ_QUEUE_IDX;\n\tstruct virtqueue *vq;\n\tint ret;\n\n\tPMD_INIT_FUNC_TRACE();\n\tret = virtio_dev_queue_setup(dev, VTNET_RQ, queue_idx, vtpci_queue_idx,\n\t\t\tnb_desc, socket_id, &vq);\n\tif (ret < 0) {\n\t\tPMD_INIT_LOG(ERR, \"rvq initialization failed\");\n\t\treturn ret;\n\t}\n\n\t/* Create mempool for rx mbuf allocation */\n\tvq->mpool = mp;\n\n\tdev->data->rx_queues[queue_idx] = vq;\n\treturn 0;\n}\n\nvoid\nvirtio_dev_rx_queue_release(void *rxq)\n{\n\tvirtio_dev_queue_release(rxq);\n}\n\n/*\n * struct rte_eth_dev *dev: Used to update dev\n * uint16_t nb_desc: Defaults to values read from config space\n * unsigned int socket_id: Used to allocate memzone\n * const struct rte_eth_txconf *tx_conf: Used to setup tx engine\n * uint16_t queue_idx: Just used as an index in dev txq list\n */\nint\nvirtio_dev_tx_queue_setup(struct rte_eth_dev *dev,\n\t\t\tuint16_t queue_idx,\n\t\t\tuint16_t nb_desc,\n\t\t\tunsigned int socket_id,\n\t\t\tconst struct rte_eth_txconf *tx_conf)\n{\n\tuint8_t vtpci_queue_idx = 2 * queue_idx + VTNET_SQ_TQ_QUEUE_IDX;\n\tstruct virtqueue *vq;\n\tuint16_t tx_free_thresh;\n\tint ret;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif ((tx_conf->txq_flags & ETH_TXQ_FLAGS_NOXSUMS)\n\t != ETH_TXQ_FLAGS_NOXSUMS) {\n\t\tPMD_INIT_LOG(ERR, \"TX checksum offload not supported\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tret = virtio_dev_queue_setup(dev, VTNET_TQ, queue_idx, vtpci_queue_idx,\n\t\t\tnb_desc, socket_id, &vq);\n\tif (ret < 0) {\n\t\tPMD_INIT_LOG(ERR, \"rvq initialization failed\");\n\t\treturn ret;\n\t}\n\n\ttx_free_thresh = tx_conf->tx_free_thresh;\n\tif (tx_free_thresh == 0)\n\t\ttx_free_thresh =\n\t\t\tRTE_MIN(vq->vq_nentries / 4, DEFAULT_TX_FREE_THRESH);\n\n\tif (tx_free_thresh >= (vq->vq_nentries - 3)) {\n\t\tRTE_LOG(ERR, PMD, \"tx_free_thresh must be less than the \"\n\t\t\t\"number of TX entries minus 3 (%u).\"\n\t\t\t\" (tx_free_thresh=%u port=%u queue=%u)\\n\",\n\t\t\tvq->vq_nentries - 3,\n\t\t\ttx_free_thresh, dev->data->port_id, queue_idx);\n\t\treturn -EINVAL;\n\t}\n\n\tvq->vq_free_thresh = tx_free_thresh;\n\n\tdev->data->tx_queues[queue_idx] = vq;\n\treturn 0;\n}\n\nvoid\nvirtio_dev_tx_queue_release(void *txq)\n{\n\tvirtio_dev_queue_release(txq);\n}\n\nstatic void\nvirtio_discard_rxbuf(struct virtqueue *vq, struct rte_mbuf *m)\n{\n\tint error;\n\t/*\n\t * Requeue the discarded mbuf. This should always be\n\t * successful since it was just dequeued.\n\t */\n\terror = virtqueue_enqueue_recv_refill(vq, m);\n\tif (unlikely(error)) {\n\t\tRTE_LOG(ERR, PMD, \"cannot requeue discarded mbuf\");\n\t\trte_pktmbuf_free(m);\n\t}\n}\n\n#define VIRTIO_MBUF_BURST_SZ 64\n#define DESC_PER_CACHELINE (RTE_CACHE_LINE_SIZE / sizeof(struct vring_desc))\nuint16_t\nvirtio_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n{\n\tstruct virtqueue *rxvq = rx_queue;\n\tstruct virtio_hw *hw;\n\tstruct rte_mbuf *rxm, *new_mbuf;\n\tuint16_t nb_used, num, nb_rx;\n\tuint32_t len[VIRTIO_MBUF_BURST_SZ];\n\tstruct rte_mbuf *rcv_pkts[VIRTIO_MBUF_BURST_SZ];\n\tint error;\n\tuint32_t i, nb_enqueued;\n\tconst uint32_t hdr_size = sizeof(struct virtio_net_hdr);\n\n\tnb_used = VIRTQUEUE_NUSED(rxvq);\n\n\tvirtio_rmb();\n\n\tnum = (uint16_t)(likely(nb_used <= nb_pkts) ? nb_used : nb_pkts);\n\tnum = (uint16_t)(likely(num <= VIRTIO_MBUF_BURST_SZ) ? num : VIRTIO_MBUF_BURST_SZ);\n\tif (likely(num > DESC_PER_CACHELINE))\n\t\tnum = num - ((rxvq->vq_used_cons_idx + num) % DESC_PER_CACHELINE);\n\n\tif (num == 0)\n\t\treturn 0;\n\n\tnum = virtqueue_dequeue_burst_rx(rxvq, rcv_pkts, len, num);\n\tPMD_RX_LOG(DEBUG, \"used:%d dequeue:%d\", nb_used, num);\n\n\thw = rxvq->hw;\n\tnb_rx = 0;\n\tnb_enqueued = 0;\n\n\tfor (i = 0; i < num ; i++) {\n\t\trxm = rcv_pkts[i];\n\n\t\tPMD_RX_LOG(DEBUG, \"packet len:%d\", len[i]);\n\n\t\tif (unlikely(len[i] < hdr_size + ETHER_HDR_LEN)) {\n\t\t\tPMD_RX_LOG(ERR, \"Packet drop\");\n\t\t\tnb_enqueued++;\n\t\t\tvirtio_discard_rxbuf(rxvq, rxm);\n\t\t\trxvq->errors++;\n\t\t\tcontinue;\n\t\t}\n\n\t\trxm->port = rxvq->port_id;\n\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n\n\t\trxm->nb_segs = 1;\n\t\trxm->next = NULL;\n\t\trxm->pkt_len = (uint32_t)(len[i] - hdr_size);\n\t\trxm->data_len = (uint16_t)(len[i] - hdr_size);\n\n\t\tif (hw->vlan_strip)\n\t\t\trte_vlan_strip(rxm);\n\n\t\tVIRTIO_DUMP_PACKET(rxm, rxm->data_len);\n\n\t\trx_pkts[nb_rx++] = rxm;\n\t\trxvq->bytes += rx_pkts[nb_rx - 1]->pkt_len;\n\t}\n\n\trxvq->packets += nb_rx;\n\n\t/* Allocate new mbuf for the used descriptor */\n\terror = ENOSPC;\n\twhile (likely(!virtqueue_full(rxvq))) {\n\t\tnew_mbuf = rte_rxmbuf_alloc(rxvq->mpool);\n\t\tif (unlikely(new_mbuf == NULL)) {\n\t\t\tstruct rte_eth_dev *dev\n\t\t\t\t= &rte_eth_devices[rxvq->port_id];\n\t\t\tdev->data->rx_mbuf_alloc_failed++;\n\t\t\tbreak;\n\t\t}\n\t\terror = virtqueue_enqueue_recv_refill(rxvq, new_mbuf);\n\t\tif (unlikely(error)) {\n\t\t\trte_pktmbuf_free(new_mbuf);\n\t\t\tbreak;\n\t\t}\n\t\tnb_enqueued++;\n\t}\n\n\tif (likely(nb_enqueued)) {\n\t\tvq_update_avail_idx(rxvq);\n\n\t\tif (unlikely(virtqueue_kick_prepare(rxvq))) {\n\t\t\tvirtqueue_notify(rxvq);\n\t\t\tPMD_RX_LOG(DEBUG, \"Notified\\n\");\n\t\t}\n\t}\n\n\treturn nb_rx;\n}\n\nuint16_t\nvirtio_recv_mergeable_pkts(void *rx_queue,\n\t\t\tstruct rte_mbuf **rx_pkts,\n\t\t\tuint16_t nb_pkts)\n{\n\tstruct virtqueue *rxvq = rx_queue;\n\tstruct virtio_hw *hw;\n\tstruct rte_mbuf *rxm, *new_mbuf;\n\tuint16_t nb_used, num, nb_rx;\n\tuint32_t len[VIRTIO_MBUF_BURST_SZ];\n\tstruct rte_mbuf *rcv_pkts[VIRTIO_MBUF_BURST_SZ];\n\tstruct rte_mbuf *prev;\n\tint error;\n\tuint32_t i, nb_enqueued;\n\tuint32_t seg_num;\n\tuint16_t extra_idx;\n\tuint32_t seg_res;\n\tconst uint32_t hdr_size = sizeof(struct virtio_net_hdr_mrg_rxbuf);\n\n\tnb_used = VIRTQUEUE_NUSED(rxvq);\n\n\tvirtio_rmb();\n\n\tif (nb_used == 0)\n\t\treturn 0;\n\n\tPMD_RX_LOG(DEBUG, \"used:%d\\n\", nb_used);\n\n\thw = rxvq->hw;\n\tnb_rx = 0;\n\ti = 0;\n\tnb_enqueued = 0;\n\tseg_num = 0;\n\textra_idx = 0;\n\tseg_res = 0;\n\n\twhile (i < nb_used) {\n\t\tstruct virtio_net_hdr_mrg_rxbuf *header;\n\n\t\tif (nb_rx == nb_pkts)\n\t\t\tbreak;\n\n\t\tnum = virtqueue_dequeue_burst_rx(rxvq, rcv_pkts, len, 1);\n\t\tif (num != 1)\n\t\t\tcontinue;\n\n\t\ti++;\n\n\t\tPMD_RX_LOG(DEBUG, \"dequeue:%d\\n\", num);\n\t\tPMD_RX_LOG(DEBUG, \"packet len:%d\\n\", len[0]);\n\n\t\trxm = rcv_pkts[0];\n\n\t\tif (unlikely(len[0] < hdr_size + ETHER_HDR_LEN)) {\n\t\t\tPMD_RX_LOG(ERR, \"Packet drop\\n\");\n\t\t\tnb_enqueued++;\n\t\t\tvirtio_discard_rxbuf(rxvq, rxm);\n\t\t\trxvq->errors++;\n\t\t\tcontinue;\n\t\t}\n\n\t\theader = (struct virtio_net_hdr_mrg_rxbuf *)((char *)rxm->buf_addr +\n\t\t\tRTE_PKTMBUF_HEADROOM - hdr_size);\n\t\tseg_num = header->num_buffers;\n\n\t\tif (seg_num == 0)\n\t\t\tseg_num = 1;\n\n\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n\t\trxm->nb_segs = seg_num;\n\t\trxm->next = NULL;\n\t\trxm->pkt_len = (uint32_t)(len[0] - hdr_size);\n\t\trxm->data_len = (uint16_t)(len[0] - hdr_size);\n\n\t\trxm->port = rxvq->port_id;\n\t\trx_pkts[nb_rx] = rxm;\n\t\tprev = rxm;\n\n\t\tseg_res = seg_num - 1;\n\n\t\twhile (seg_res != 0) {\n\t\t\t/*\n\t\t\t * Get extra segments for current uncompleted packet.\n\t\t\t */\n\t\t\tuint16_t rcv_cnt =\n\t\t\t\tRTE_MIN(seg_res, RTE_DIM(rcv_pkts));\n\t\t\tif (likely(VIRTQUEUE_NUSED(rxvq) >= rcv_cnt)) {\n\t\t\t\tuint32_t rx_num =\n\t\t\t\t\tvirtqueue_dequeue_burst_rx(rxvq,\n\t\t\t\t\trcv_pkts, len, rcv_cnt);\n\t\t\t\ti += rx_num;\n\t\t\t\trcv_cnt = rx_num;\n\t\t\t} else {\n\t\t\t\tPMD_RX_LOG(ERR,\n\t\t\t\t\t\"No enough segments for packet.\\n\");\n\t\t\t\tnb_enqueued++;\n\t\t\t\tvirtio_discard_rxbuf(rxvq, rxm);\n\t\t\t\trxvq->errors++;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\textra_idx = 0;\n\n\t\t\twhile (extra_idx < rcv_cnt) {\n\t\t\t\trxm = rcv_pkts[extra_idx];\n\n\t\t\t\trxm->data_off = RTE_PKTMBUF_HEADROOM - hdr_size;\n\t\t\t\trxm->next = NULL;\n\t\t\t\trxm->pkt_len = (uint32_t)(len[extra_idx]);\n\t\t\t\trxm->data_len = (uint16_t)(len[extra_idx]);\n\n\t\t\t\tif (prev)\n\t\t\t\t\tprev->next = rxm;\n\n\t\t\t\tprev = rxm;\n\t\t\t\trx_pkts[nb_rx]->pkt_len += rxm->pkt_len;\n\t\t\t\textra_idx++;\n\t\t\t};\n\t\t\tseg_res -= rcv_cnt;\n\t\t}\n\n\t\tif (hw->vlan_strip)\n\t\t\trte_vlan_strip(rx_pkts[nb_rx]);\n\n\t\tVIRTIO_DUMP_PACKET(rx_pkts[nb_rx],\n\t\t\trx_pkts[nb_rx]->data_len);\n\n\t\trxvq->bytes += rx_pkts[nb_rx]->pkt_len;\n\t\tnb_rx++;\n\t}\n\n\trxvq->packets += nb_rx;\n\n\t/* Allocate new mbuf for the used descriptor */\n\terror = ENOSPC;\n\twhile (likely(!virtqueue_full(rxvq))) {\n\t\tnew_mbuf = rte_rxmbuf_alloc(rxvq->mpool);\n\t\tif (unlikely(new_mbuf == NULL)) {\n\t\t\tstruct rte_eth_dev *dev\n\t\t\t\t= &rte_eth_devices[rxvq->port_id];\n\t\t\tdev->data->rx_mbuf_alloc_failed++;\n\t\t\tbreak;\n\t\t}\n\t\terror = virtqueue_enqueue_recv_refill(rxvq, new_mbuf);\n\t\tif (unlikely(error)) {\n\t\t\trte_pktmbuf_free(new_mbuf);\n\t\t\tbreak;\n\t\t}\n\t\tnb_enqueued++;\n\t}\n\n\tif (likely(nb_enqueued)) {\n\t\tvq_update_avail_idx(rxvq);\n\n\t\tif (unlikely(virtqueue_kick_prepare(rxvq))) {\n\t\t\tvirtqueue_notify(rxvq);\n\t\t\tPMD_RX_LOG(DEBUG, \"Notified\");\n\t\t}\n\t}\n\n\treturn nb_rx;\n}\n\nuint16_t\nvirtio_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n{\n\tstruct virtqueue *txvq = tx_queue;\n\tstruct rte_mbuf *txm;\n\tuint16_t nb_used, nb_tx;\n\tint error;\n\n\tif (unlikely(nb_pkts < 1))\n\t\treturn nb_pkts;\n\n\tPMD_TX_LOG(DEBUG, \"%d packets to xmit\", nb_pkts);\n\tnb_used = VIRTQUEUE_NUSED(txvq);\n\n\tvirtio_rmb();\n\tif (likely(nb_used > txvq->vq_nentries - txvq->vq_free_thresh))\n\t\tvirtio_xmit_cleanup(txvq, nb_used);\n\n\tnb_tx = 0;\n\n\twhile (nb_tx < nb_pkts) {\n\t\t/* Need one more descriptor for virtio header. */\n\t\tint need = tx_pkts[nb_tx]->nb_segs - txvq->vq_free_cnt + 1;\n\n\t\t/*Positive value indicates it need free vring descriptors */\n\t\tif (unlikely(need > 0)) {\n\t\t\tnb_used = VIRTQUEUE_NUSED(txvq);\n\t\t\tvirtio_rmb();\n\t\t\tneed = RTE_MIN(need, (int)nb_used);\n\n\t\t\tvirtio_xmit_cleanup(txvq, need);\n\t\t\tneed = (int)tx_pkts[nb_tx]->nb_segs -\n\t\t\t\ttxvq->vq_free_cnt + 1;\n\t\t}\n\n\t\t/*\n\t\t * Zero or negative value indicates it has enough free\n\t\t * descriptors to use for transmitting.\n\t\t */\n\t\tif (likely(need <= 0)) {\n\t\t\ttxm = tx_pkts[nb_tx];\n\n\t\t\t/* Do VLAN tag insertion */\n\t\t\tif (unlikely(txm->ol_flags & PKT_TX_VLAN_PKT)) {\n\t\t\t\terror = rte_vlan_insert(&txm);\n\t\t\t\tif (unlikely(error)) {\n\t\t\t\t\trte_pktmbuf_free(txm);\n\t\t\t\t\t++nb_tx;\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Enqueue Packet buffers */\n\t\t\terror = virtqueue_enqueue_xmit(txvq, txm);\n\t\t\tif (unlikely(error)) {\n\t\t\t\tif (error == ENOSPC)\n\t\t\t\t\tPMD_TX_LOG(ERR, \"virtqueue_enqueue Free count = 0\");\n\t\t\t\telse if (error == EMSGSIZE)\n\t\t\t\t\tPMD_TX_LOG(ERR, \"virtqueue_enqueue Free count < 1\");\n\t\t\t\telse\n\t\t\t\t\tPMD_TX_LOG(ERR, \"virtqueue_enqueue error: %d\", error);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tnb_tx++;\n\t\t\ttxvq->bytes += txm->pkt_len;\n\t\t} else {\n\t\t\tPMD_TX_LOG(ERR, \"No free tx descriptors to transmit\");\n\t\t\tbreak;\n\t\t}\n\t}\n\n\ttxvq->packets += nb_tx;\n\n\tif (likely(nb_tx)) {\n\t\tvq_update_avail_idx(txvq);\n\n\t\tif (unlikely(virtqueue_kick_prepare(txvq))) {\n\t\t\tvirtqueue_notify(txvq);\n\t\t\tPMD_TX_LOG(DEBUG, \"Notified backend after xmit\");\n\t\t}\n\t}\n\n\treturn nb_tx;\n}\n" }, { "path": "drivers/net/virtio/virtqueue.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n\n#include \n\n#include \"virtqueue.h\"\n#include \"virtio_logs.h\"\n#include \"virtio_pci.h\"\n\nvoid\nvirtqueue_disable_intr(struct virtqueue *vq)\n{\n\t/*\n\t * Set VRING_AVAIL_F_NO_INTERRUPT to hint host\n\t * not to interrupt when it consumes packets\n\t * Note: this is only considered a hint to the host\n\t */\n\tvq->vq_ring.avail->flags |= VRING_AVAIL_F_NO_INTERRUPT;\n}\n\n/*\n * Two types of mbuf to be cleaned:\n * 1) mbuf that has been consumed by backend but not used by virtio.\n * 2) mbuf that hasn't been consued by backend.\n */\nstruct rte_mbuf *\nvirtqueue_detatch_unused(struct virtqueue *vq)\n{\n\tstruct rte_mbuf *cookie;\n\tint idx;\n\n\tif (vq != NULL)\n\t\tfor (idx = 0; idx < vq->vq_nentries; idx++) {\n\t\t\tcookie = vq->vq_descx[idx].cookie;\n\t\t\tif (cookie != NULL) {\n\t\t\t\tvq->vq_descx[idx].cookie = NULL;\n\t\t\t\treturn cookie;\n\t\t\t}\n\t\t}\n\treturn NULL;\n}\n" }, { "path": "drivers/net/virtio/virtqueue.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VIRTQUEUE_H_\n#define _VIRTQUEUE_H_\n\n#include \n\n#include \n#include \n#include \n#include \n\n#include \"virtio_pci.h\"\n#include \"virtio_ring.h\"\n#include \"virtio_logs.h\"\n\nstruct rte_mbuf;\n\n/*\n * Per virtio_config.h in Linux.\n * For virtio_pci on SMP, we don't need to order with respect to MMIO\n * accesses through relaxed memory I/O windows, so smp_mb() et al are\n * sufficient.\n *\n * This driver is for virtio_pci on SMP and therefore can assume\n * weaker (compiler barriers)\n */\n#define virtio_mb()\trte_mb()\n#define virtio_rmb()\trte_compiler_barrier()\n#define virtio_wmb()\trte_compiler_barrier()\n\n#ifdef RTE_PMD_PACKET_PREFETCH\n#define rte_packet_prefetch(p) rte_prefetch1(p)\n#else\n#define rte_packet_prefetch(p) do {} while(0)\n#endif\n\n#define VIRTQUEUE_MAX_NAME_SZ 32\n\n#define RTE_MBUF_DATA_DMA_ADDR(mb) \\\n\t(uint64_t) ((mb)->buf_physaddr + (mb)->data_off)\n\n#define VTNET_SQ_RQ_QUEUE_IDX 0\n#define VTNET_SQ_TQ_QUEUE_IDX 1\n#define VTNET_SQ_CQ_QUEUE_IDX 2\n\nenum { VTNET_RQ = 0, VTNET_TQ = 1, VTNET_CQ = 2 };\n/**\n * The maximum virtqueue size is 2^15. Use that value as the end of\n * descriptor chain terminator since it will never be a valid index\n * in the descriptor table. This is used to verify we are correctly\n * handling vq_free_cnt.\n */\n#define VQ_RING_DESC_CHAIN_END 32768\n\n/**\n * Control the RX mode, ie. promiscuous, allmulti, etc...\n * All commands require an \"out\" sg entry containing a 1 byte\n * state value, zero = disable, non-zero = enable. Commands\n * 0 and 1 are supported with the VIRTIO_NET_F_CTRL_RX feature.\n * Commands 2-5 are added with VIRTIO_NET_F_CTRL_RX_EXTRA.\n */\n#define VIRTIO_NET_CTRL_RX 0\n#define VIRTIO_NET_CTRL_RX_PROMISC 0\n#define VIRTIO_NET_CTRL_RX_ALLMULTI 1\n#define VIRTIO_NET_CTRL_RX_ALLUNI 2\n#define VIRTIO_NET_CTRL_RX_NOMULTI 3\n#define VIRTIO_NET_CTRL_RX_NOUNI 4\n#define VIRTIO_NET_CTRL_RX_NOBCAST 5\n\n/**\n * Control the MAC\n *\n * The MAC filter table is managed by the hypervisor, the guest should\n * assume the size is infinite. Filtering should be considered\n * non-perfect, ie. based on hypervisor resources, the guest may\n * received packets from sources not specified in the filter list.\n *\n * In addition to the class/cmd header, the TABLE_SET command requires\n * two out scatterlists. Each contains a 4 byte count of entries followed\n * by a concatenated byte stream of the ETH_ALEN MAC addresses. The\n * first sg list contains unicast addresses, the second is for multicast.\n * This functionality is present if the VIRTIO_NET_F_CTRL_RX feature\n * is available.\n *\n * The ADDR_SET command requests one out scatterlist, it contains a\n * 6 bytes MAC address. This functionality is present if the\n * VIRTIO_NET_F_CTRL_MAC_ADDR feature is available.\n */\nstruct virtio_net_ctrl_mac {\n\tuint32_t entries;\n\tuint8_t macs[][ETHER_ADDR_LEN];\n} __attribute__((__packed__));\n\n#define VIRTIO_NET_CTRL_MAC 1\n #define VIRTIO_NET_CTRL_MAC_TABLE_SET 0\n #define VIRTIO_NET_CTRL_MAC_ADDR_SET 1\n\n/**\n * Control VLAN filtering\n *\n * The VLAN filter table is controlled via a simple ADD/DEL interface.\n * VLAN IDs not added may be filtered by the hypervisor. Del is the\n * opposite of add. Both commands expect an out entry containing a 2\n * byte VLAN ID. VLAN filtering is available with the\n * VIRTIO_NET_F_CTRL_VLAN feature bit.\n */\n#define VIRTIO_NET_CTRL_VLAN 2\n#define VIRTIO_NET_CTRL_VLAN_ADD 0\n#define VIRTIO_NET_CTRL_VLAN_DEL 1\n\nstruct virtio_net_ctrl_hdr {\n\tuint8_t class;\n\tuint8_t cmd;\n} __attribute__((packed));\n\ntypedef uint8_t virtio_net_ctrl_ack;\n\n#define VIRTIO_NET_OK 0\n#define VIRTIO_NET_ERR 1\n\n#define VIRTIO_MAX_CTRL_DATA 2048\n\nstruct virtio_pmd_ctrl {\n\tstruct virtio_net_ctrl_hdr hdr;\n\tvirtio_net_ctrl_ack status;\n\tuint8_t data[VIRTIO_MAX_CTRL_DATA];\n};\n\nstruct virtqueue {\n\tstruct virtio_hw *hw; /**< virtio_hw structure pointer. */\n\tconst struct rte_memzone *mz; /**< mem zone to populate RX ring. */\n\tconst struct rte_memzone *virtio_net_hdr_mz; /**< memzone to populate hdr. */\n\tstruct rte_mempool *mpool; /**< mempool for mbuf allocation */\n\tuint16_t queue_id; /**< DPDK queue index. */\n\tuint8_t port_id; /**< Device port identifier. */\n\tuint16_t vq_queue_index; /**< PCI queue index */\n\n\tvoid *vq_ring_virt_mem; /**< linear address of vring*/\n\tunsigned int vq_ring_size;\n\tphys_addr_t vq_ring_mem; /**< physical address of vring */\n\n\tstruct vring vq_ring; /**< vring keeping desc, used and avail */\n\tuint16_t vq_free_cnt; /**< num of desc available */\n\tuint16_t vq_nentries; /**< vring desc numbers */\n\tuint16_t vq_free_thresh; /**< free threshold */\n\t/**\n\t * Head of the free chain in the descriptor table. If\n\t * there are no free descriptors, this will be set to\n\t * VQ_RING_DESC_CHAIN_END.\n\t */\n\tuint16_t vq_desc_head_idx;\n\tuint16_t vq_desc_tail_idx;\n\t/**\n\t * Last consumed descriptor in the used table,\n\t * trails vq_ring.used->idx.\n\t */\n\tuint16_t vq_used_cons_idx;\n\tuint16_t vq_avail_idx;\n\tphys_addr_t virtio_net_hdr_mem; /**< hdr for each xmit packet */\n\n\t/* Statistics */\n\tuint64_t\tpackets;\n\tuint64_t\tbytes;\n\tuint64_t\terrors;\n\n\tstruct vq_desc_extra {\n\t\tvoid *cookie;\n\t\tuint16_t ndescs;\n\t} vq_descx[0];\n};\n\n/* If multiqueue is provided by host, then we suppport it. */\n#define VIRTIO_NET_CTRL_MQ 4\n#define VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET 0\n#define VIRTIO_NET_CTRL_MQ_VQ_PAIRS_MIN 1\n#define VIRTIO_NET_CTRL_MQ_VQ_PAIRS_MAX 0x8000\n\n#define VIRTIO_NET_CTRL_MAC_ADDR_SET 1\n\n/**\n * This is the first element of the scatter-gather list. If you don't\n * specify GSO or CSUM features, you can simply ignore the header.\n */\nstruct virtio_net_hdr {\n#define VIRTIO_NET_HDR_F_NEEDS_CSUM 1 /**< Use csum_start,csum_offset*/\n\tuint8_t flags;\n#define VIRTIO_NET_HDR_GSO_NONE 0 /**< Not a GSO frame */\n#define VIRTIO_NET_HDR_GSO_TCPV4 1 /**< GSO frame, IPv4 TCP (TSO) */\n#define VIRTIO_NET_HDR_GSO_UDP 3 /**< GSO frame, IPv4 UDP (UFO) */\n#define VIRTIO_NET_HDR_GSO_TCPV6 4 /**< GSO frame, IPv6 TCP */\n#define VIRTIO_NET_HDR_GSO_ECN 0x80 /**< TCP has ECN set */\n\tuint8_t gso_type;\n\tuint16_t hdr_len; /**< Ethernet + IP + tcp/udp hdrs */\n\tuint16_t gso_size; /**< Bytes to append to hdr_len per frame */\n\tuint16_t csum_start; /**< Position to start checksumming from */\n\tuint16_t csum_offset; /**< Offset after that to place checksum */\n};\n\n/**\n * This is the version of the header to use when the MRG_RXBUF\n * feature has been negotiated.\n */\nstruct virtio_net_hdr_mrg_rxbuf {\n\tstruct virtio_net_hdr hdr;\n\tuint16_t num_buffers; /**< Number of merged rx buffers */\n};\n\n/**\n * Tell the backend not to interrupt us.\n */\nvoid virtqueue_disable_intr(struct virtqueue *vq);\n/**\n * Dump virtqueue internal structures, for debug purpose only.\n */\nvoid virtqueue_dump(struct virtqueue *vq);\n/**\n * Get all mbufs to be freed.\n */\nstruct rte_mbuf *virtqueue_detatch_unused(struct virtqueue *vq);\n\nstatic inline int\nvirtqueue_full(const struct virtqueue *vq)\n{\n\treturn vq->vq_free_cnt == 0;\n}\n\n#define VIRTQUEUE_NUSED(vq) ((uint16_t)((vq)->vq_ring.used->idx - (vq)->vq_used_cons_idx))\n\nstatic inline void\nvq_update_avail_idx(struct virtqueue *vq)\n{\n\tvirtio_wmb();\n\tvq->vq_ring.avail->idx = vq->vq_avail_idx;\n}\n\nstatic inline void\nvq_update_avail_ring(struct virtqueue *vq, uint16_t desc_idx)\n{\n\tuint16_t avail_idx;\n\t/*\n\t * Place the head of the descriptor chain into the next slot and make\n\t * it usable to the host. The chain is made available now rather than\n\t * deferring to virtqueue_notify() in the hopes that if the host is\n\t * currently running on another CPU, we can keep it processing the new\n\t * descriptor.\n\t */\n\tavail_idx = (uint16_t)(vq->vq_avail_idx & (vq->vq_nentries - 1));\n\tvq->vq_ring.avail->ring[avail_idx] = desc_idx;\n\tvq->vq_avail_idx++;\n}\n\nstatic inline int\nvirtqueue_kick_prepare(struct virtqueue *vq)\n{\n\treturn !(vq->vq_ring.used->flags & VRING_USED_F_NO_NOTIFY);\n}\n\nstatic inline void\nvirtqueue_notify(struct virtqueue *vq)\n{\n\t/*\n\t * Ensure updated avail->idx is visible to host.\n\t * For virtio on IA, the notificaiton is through io port operation\n\t * which is a serialization instruction itself.\n\t */\n\tVIRTIO_WRITE_REG_2(vq->hw, VIRTIO_PCI_QUEUE_NOTIFY, vq->vq_queue_index);\n}\n\n#ifdef RTE_LIBRTE_VIRTIO_DEBUG_DUMP\n#define VIRTQUEUE_DUMP(vq) do { \\\n\tuint16_t used_idx, nused; \\\n\tused_idx = (vq)->vq_ring.used->idx; \\\n\tnused = (uint16_t)(used_idx - (vq)->vq_used_cons_idx); \\\n\tPMD_INIT_LOG(DEBUG, \\\n\t \"VQ: - size=%d; free=%d; used=%d; desc_head_idx=%d;\" \\\n\t \" avail.idx=%d; used_cons_idx=%d; used.idx=%d;\" \\\n\t \" avail.flags=0x%x; used.flags=0x%x\", \\\n\t (vq)->vq_nentries, (vq)->vq_free_cnt, nused, \\\n\t (vq)->vq_desc_head_idx, (vq)->vq_ring.avail->idx, \\\n\t (vq)->vq_used_cons_idx, (vq)->vq_ring.used->idx, \\\n\t (vq)->vq_ring.avail->flags, (vq)->vq_ring.used->flags); \\\n} while (0)\n#else\n#define VIRTQUEUE_DUMP(vq) do { } while (0)\n#endif\n\n#endif /* _VIRTQUEUE_H_ */\n" }, { "path": "drivers/net/vmxnet3/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_vmxnet3_uio.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nifeq ($(CC), icc)\n#\n# CFLAGS for icc\n#\nCFLAGS_BASE_DRIVER = -wd174 -wd593 -wd869 -wd981 -wd2259\n\nelse ifeq ($(CC), clang)\n#\n# CFLAGS for clang\n#\nCFLAGS_BASE_DRIVER = -Wno-unused-parameter -Wno-unused-value\nCFLAGS_BASE_DRIVER += -Wno-strict-aliasing -Wno-format-extra-args\n\nelse\n#\n# CFLAGS for gcc\n#\nifeq ($(shell test $(GCC_VERSION) -ge 44 && echo 1), 1)\nCFLAGS += -Wno-deprecated\nendif\nCFLAGS_BASE_DRIVER = -Wno-unused-parameter -Wno-unused-value\nCFLAGS_BASE_DRIVER += -Wno-strict-aliasing -Wno-format-extra-args\n\nendif\n\nVPATH += $(SRCDIR)/base\n\nEXPORT_MAP := rte_pmd_vmxnet3_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_VMXNET3_PMD) += vmxnet3_rxtx.c\nSRCS-$(CONFIG_RTE_LIBRTE_VMXNET3_PMD) += vmxnet3_ethdev.c\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_VMXNET3_PMD) += lib/librte_eal lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_VMXNET3_PMD) += lib/librte_mempool lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_VMXNET3_PMD) += lib/librte_net\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/vmxnet3/base/README", "content": "..\n BSD LICENSE\n \n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n \n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n \n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nIntel VMXNET3 driver\n===================\n\nThis directory contains source code of FreeBSD VMXNET3 driver released by VMware.\nIn which, upt1_defs.h and vmxnet3_defs.h is introduced without any change.\nThe other 4 files: includeCheck.h, vmware_pack_begin.h, vmware_pack_end.h and vmxnet3_osdep.h\nare crated to adapt to the needs from above 2 files.\n\nUpdating the driver\n===================\n\nNOTE: The source code in this directory should not be modified apart from\nthe following file(s):\n\n vmxnet3_osdep.h\n" }, { "path": "drivers/net/vmxnet3/base/includeCheck.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _INCLUDECHECK_H\n#define _INCLUDECHECK_H\n\n#include \"vmxnet3_osdep.h\"\n\n#endif /* _INCLUDECHECK_H */\n\n" }, { "path": "drivers/net/vmxnet3/base/upt1_defs.h", "content": "/*********************************************************\n * Copyright (C) 2007 VMware, Inc. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *********************************************************/\n\n/* upt1_defs.h\n *\n * Definitions for UPTv1\n *\n * Some of the defs are duplicated in vmkapi_net_upt.h, because\n * vmkapi_net_upt.h cannot distribute with OSS yet and vmkapi headers can\n * only include vmkapi headers. Make sure they are kept in sync!\n */\n\n#ifndef _UPT1_DEFS_H\n#define _UPT1_DEFS_H\n\n#define UPT1_MAX_TX_QUEUES 64\n#define UPT1_MAX_RX_QUEUES 64\n\n#define UPT1_MAX_INTRS (UPT1_MAX_TX_QUEUES + UPT1_MAX_RX_QUEUES)\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct UPT1_TxStats {\n uint64 TSOPktsTxOK; /* TSO pkts post-segmentation */\n uint64 TSOBytesTxOK;\n uint64 ucastPktsTxOK;\n uint64 ucastBytesTxOK;\n uint64 mcastPktsTxOK;\n uint64 mcastBytesTxOK;\n uint64 bcastPktsTxOK;\n uint64 bcastBytesTxOK;\n uint64 pktsTxError;\n uint64 pktsTxDiscard;\n}\n#include \"vmware_pack_end.h\"\nUPT1_TxStats;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct UPT1_RxStats {\n uint64 LROPktsRxOK; /* LRO pkts */\n uint64 LROBytesRxOK; /* bytes from LRO pkts */\n /* the following counters are for pkts from the wire, i.e., pre-LRO */\n uint64 ucastPktsRxOK;\n uint64 ucastBytesRxOK;\n uint64 mcastPktsRxOK;\n uint64 mcastBytesRxOK;\n uint64 bcastPktsRxOK;\n uint64 bcastBytesRxOK;\n uint64 pktsRxOutOfBuf;\n uint64 pktsRxError;\n}\n#include \"vmware_pack_end.h\"\nUPT1_RxStats;\n\n/* interrupt moderation level */\n#define UPT1_IML_NONE 0 /* no interrupt moderation */\n#define UPT1_IML_HIGHEST 7 /* least intr generated */\n#define UPT1_IML_ADAPTIVE 8 /* adpative intr moderation */\n\n/* values for UPT1_RSSConf.hashFunc */\n#define UPT1_RSS_HASH_TYPE_NONE 0x0\n#define UPT1_RSS_HASH_TYPE_IPV4 0x01\n#define UPT1_RSS_HASH_TYPE_TCP_IPV4 0x02\n#define UPT1_RSS_HASH_TYPE_IPV6 0x04\n#define UPT1_RSS_HASH_TYPE_TCP_IPV6 0x08\n\n#define UPT1_RSS_HASH_FUNC_NONE 0x0\n#define UPT1_RSS_HASH_FUNC_TOEPLITZ 0x01\n\n#define UPT1_RSS_MAX_KEY_SIZE 40\n#define UPT1_RSS_MAX_IND_TABLE_SIZE 128\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct UPT1_RSSConf {\n uint16 hashType;\n uint16 hashFunc;\n uint16 hashKeySize;\n uint16 indTableSize;\n uint8 hashKey[UPT1_RSS_MAX_KEY_SIZE];\n uint8 indTable[UPT1_RSS_MAX_IND_TABLE_SIZE];\n}\n#include \"vmware_pack_end.h\"\nUPT1_RSSConf;\n\n/* features */\n#define UPT1_F_RXCSUM 0x0001 /* rx csum verification */\n#define UPT1_F_RSS 0x0002\n#define UPT1_F_RXVLAN 0x0004 /* VLAN tag stripping */\n#define UPT1_F_LRO 0x0008\n\n#endif\n" }, { "path": "drivers/net/vmxnet3/base/vmware_pack_begin.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n" }, { "path": "drivers/net/vmxnet3/base/vmware_pack_end.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n" }, { "path": "drivers/net/vmxnet3/base/vmxnet3_defs.h", "content": "/*********************************************************\n * Copyright (C) 2007 VMware, Inc. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n *********************************************************/\n\n/*\n * vmxnet3_defs.h --\n *\n * Definitions shared by device emulation and guest drivers for\n * VMXNET3 NIC\n */\n\n#ifndef _VMXNET3_DEFS_H_\n#define _VMXNET3_DEFS_H_\n\n#define INCLUDE_ALLOW_USERLEVEL\n#define INCLUDE_ALLOW_VMKERNEL\n#define INCLUDE_ALLOW_DISTRIBUTE\n#define INCLUDE_ALLOW_VMKDRIVERS\n#define INCLUDE_ALLOW_VMCORE\n#define INCLUDE_ALLOW_MODULE\n#include \"includeCheck.h\"\n\n#include \"upt1_defs.h\"\n\n/* all registers are 32 bit wide */\n/* BAR 1 */\n#define VMXNET3_REG_VRRS 0x0 /* Vmxnet3 Revision Report Selection */\n#define VMXNET3_REG_UVRS 0x8 /* UPT Version Report Selection */\n#define VMXNET3_REG_DSAL 0x10 /* Driver Shared Address Low */\n#define VMXNET3_REG_DSAH 0x18 /* Driver Shared Address High */\n#define VMXNET3_REG_CMD 0x20 /* Command */\n#define VMXNET3_REG_MACL 0x28 /* MAC Address Low */\n#define VMXNET3_REG_MACH 0x30 /* MAC Address High */\n#define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */\n#define VMXNET3_REG_ECR 0x40 /* Event Cause Register */\n\n#define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */\n#define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */\n#define VMXNET3_REG_WCMD 0xF18 /* Wireless Command */\n\n/* BAR 0 */\n#define VMXNET3_REG_IMR 0x0 /* Interrupt Mask Register */\n#define VMXNET3_REG_TXPROD 0x600 /* Tx Producer Index */\n#define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */\n#define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */\n\n#define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */\n#define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */\n\n/*\n * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at\n * offset 14h) as well as the MSI-X BAR are combined into one PhysMem region:\n * <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE-->\n * -------------------------------------------------------------------------\n * |Pass Thru Registers | Virtual Dev Registers | MSI-X Vector/PBA Table |\n * -------------------------------------------------------------------------\n * VMXNET3_MSIX_BAR_SIZE is defined in \"vmxnet3Int.h\"\n */\n#define VMXNET3_PHYSMEM_PAGES 4\n\n#define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */\n#define VMXNET3_REG_ALIGN_MASK 0x7\n\n/* I/O Mapped access to registers */\n#define VMXNET3_IO_TYPE_PT 0\n#define VMXNET3_IO_TYPE_VD 1\n#define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))\n#define VMXNET3_IO_TYPE(addr) ((addr) >> 24)\n#define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)\n\n#ifndef __le16\n#define __le16 uint16\n#endif\n#ifndef __le32\n#define __le32 uint32\n#endif\n#ifndef __le64\n#define __le64 uint64\n#endif\n\ntypedef enum {\n VMXNET3_CMD_FIRST_SET = 0xCAFE0000,\n VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,\n VMXNET3_CMD_QUIESCE_DEV,\n VMXNET3_CMD_RESET_DEV,\n VMXNET3_CMD_UPDATE_RX_MODE,\n VMXNET3_CMD_UPDATE_MAC_FILTERS,\n VMXNET3_CMD_UPDATE_VLAN_FILTERS,\n VMXNET3_CMD_UPDATE_RSSIDT,\n VMXNET3_CMD_UPDATE_IML,\n VMXNET3_CMD_UPDATE_PMCFG,\n VMXNET3_CMD_UPDATE_FEATURE,\n VMXNET3_CMD_STOP_EMULATION,\n VMXNET3_CMD_LOAD_PLUGIN,\n VMXNET3_CMD_ACTIVATE_VF,\n\n VMXNET3_CMD_FIRST_GET = 0xF00D0000,\n VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,\n VMXNET3_CMD_GET_STATS,\n VMXNET3_CMD_GET_LINK,\n VMXNET3_CMD_GET_PERM_MAC_LO,\n VMXNET3_CMD_GET_PERM_MAC_HI,\n VMXNET3_CMD_GET_DID_LO,\n VMXNET3_CMD_GET_DID_HI,\n VMXNET3_CMD_GET_DEV_EXTRA_INFO,\n VMXNET3_CMD_GET_CONF_INTR,\n VMXNET3_CMD_GET_ADAPTIVE_RING_INFO\n} Vmxnet3_Cmd;\n\n/* Adaptive Ring Info Flags */\n#define VMXNET3_DISABLE_ADAPTIVE_RING 1\n\n/*\n *\tLittle Endian layout of bitfields -\n *\tByte 0 :\t7.....len.....0\n *\tByte 1 :\trsvd gen 13.len.8\n *\tByte 2 :\t5.msscof.0 ext1 dtype\n *\tByte 3 :\t13...msscof...6\n *\n *\tBig Endian layout of bitfields -\n *\tByte 0:\t\t13...msscof...6\n *\tByte 1 :\t5.msscof.0 ext1 dtype\n *\tByte 2 :\trsvd gen 13.len.8\n *\tByte 3 :\t7.....len.....0\n *\n *\tThus, le32_to_cpu on the dword will allow the big endian driver to read\n *\tthe bit fields correctly. And cpu_to_le32 will convert bitfields\n *\tbit fields written by big endian driver to format required by device.\n */\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_TxDesc {\n __le64 addr;\n\n#ifdef __BIG_ENDIAN_BITFIELD\n uint32 msscof:14; /* MSS, checksum offset, flags */\n uint32 ext1:1;\n uint32 dtype:1; /* descriptor type */\n uint32 rsvd:1;\n uint32 gen:1; /* generation bit */\n uint32 len:14;\n#else\n uint32 len:14;\n uint32 gen:1; /* generation bit */\n uint32 rsvd:1;\n uint32 dtype:1; /* descriptor type */\n uint32 ext1:1;\n uint32 msscof:14; /* MSS, checksum offset, flags */\n#endif /* __BIG_ENDIAN_BITFIELD */\n\n#ifdef __BIG_ENDIAN_BITFIELD\n uint32 tci:16; /* Tag to Insert */\n uint32 ti:1; /* VLAN Tag Insertion */\n uint32 ext2:1;\n uint32 cq:1; /* completion request */\n uint32 eop:1; /* End Of Packet */\n uint32 om:2; /* offload mode */\n uint32 hlen:10; /* header len */\n#else\n uint32 hlen:10; /* header len */\n uint32 om:2; /* offload mode */\n uint32 eop:1; /* End Of Packet */\n uint32 cq:1; /* completion request */\n uint32 ext2:1;\n uint32 ti:1; /* VLAN Tag Insertion */\n uint32 tci:16; /* Tag to Insert */\n#endif /* __BIG_ENDIAN_BITFIELD */\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_TxDesc;\n\n/* TxDesc.OM values */\n#define VMXNET3_OM_NONE 0\n#define VMXNET3_OM_CSUM 2\n#define VMXNET3_OM_TSO 3\n\n/* fields in TxDesc we access w/o using bit fields */\n#define VMXNET3_TXD_EOP_SHIFT 12\n#define VMXNET3_TXD_CQ_SHIFT 13\n#define VMXNET3_TXD_GEN_SHIFT 14\n#define VMXNET3_TXD_EOP_DWORD_SHIFT 3\n#define VMXNET3_TXD_GEN_DWORD_SHIFT 2\n\n#define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)\n#define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)\n#define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)\n\n#define VMXNET3_TXD_GEN_SIZE 1\n#define VMXNET3_TXD_EOP_SIZE 1\n\n#define VMXNET3_HDR_COPY_SIZE 128\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_TxDataDesc {\n uint8 data[VMXNET3_HDR_COPY_SIZE];\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_TxDataDesc;\n\n#define VMXNET3_TCD_GEN_SHIFT\t31\n#define VMXNET3_TCD_GEN_SIZE\t1\n#define VMXNET3_TCD_TXIDX_SHIFT\t0\n#define VMXNET3_TCD_TXIDX_SIZE\t12\n#define VMXNET3_TCD_GEN_DWORD_SHIFT\t3\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_TxCompDesc {\n uint32 txdIdx:12; /* Index of the EOP TxDesc */\n uint32 ext1:20;\n\n __le32 ext2;\n __le32 ext3;\n\n uint32 rsvd:24;\n uint32 type:7; /* completion type */\n uint32 gen:1; /* generation bit */\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_TxCompDesc;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_RxDesc {\n __le64 addr;\n\n#ifdef __BIG_ENDIAN_BITFIELD\n uint32 gen:1; /* Generation bit */\n uint32 rsvd:15;\n uint32 dtype:1; /* Descriptor type */\n uint32 btype:1; /* Buffer Type */\n uint32 len:14;\n#else\n uint32 len:14;\n uint32 btype:1; /* Buffer Type */\n uint32 dtype:1; /* Descriptor type */\n uint32 rsvd:15;\n uint32 gen:1; /* Generation bit */\n#endif\n __le32 ext1;\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_RxDesc;\n\n/* values of RXD.BTYPE */\n#define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */\n#define VMXNET3_RXD_BTYPE_BODY 1 /* body only */\n\n/* fields in RxDesc we access w/o using bit fields */\n#define VMXNET3_RXD_BTYPE_SHIFT 14\n#define VMXNET3_RXD_GEN_SHIFT 31\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_RxCompDesc {\n#ifdef __BIG_ENDIAN_BITFIELD\n uint32 ext2:1;\n uint32 cnc:1; /* Checksum Not Calculated */\n uint32 rssType:4; /* RSS hash type used */\n uint32 rqID:10; /* rx queue/ring ID */\n uint32 sop:1; /* Start of Packet */\n uint32 eop:1; /* End of Packet */\n uint32 ext1:2;\n uint32 rxdIdx:12; /* Index of the RxDesc */\n#else\n uint32 rxdIdx:12; /* Index of the RxDesc */\n uint32 ext1:2;\n uint32 eop:1; /* End of Packet */\n uint32 sop:1; /* Start of Packet */\n uint32 rqID:10; /* rx queue/ring ID */\n uint32 rssType:4; /* RSS hash type used */\n uint32 cnc:1; /* Checksum Not Calculated */\n uint32 ext2:1;\n#endif /* __BIG_ENDIAN_BITFIELD */\n\n __le32 rssHash; /* RSS hash value */\n\n#ifdef __BIG_ENDIAN_BITFIELD\n uint32 tci:16; /* Tag stripped */\n uint32 ts:1; /* Tag is stripped */\n uint32 err:1; /* Error */\n uint32 len:14; /* data length */\n#else\n uint32 len:14; /* data length */\n uint32 err:1; /* Error */\n uint32 ts:1; /* Tag is stripped */\n uint32 tci:16; /* Tag stripped */\n#endif /* __BIG_ENDIAN_BITFIELD */\n\n\n#ifdef __BIG_ENDIAN_BITFIELD\n uint32 gen:1; /* generation bit */\n uint32 type:7; /* completion type */\n uint32 fcs:1; /* Frame CRC correct */\n uint32 frg:1; /* IP Fragment */\n uint32 v4:1; /* IPv4 */\n uint32 v6:1; /* IPv6 */\n uint32 ipc:1; /* IP Checksum Correct */\n uint32 tcp:1; /* TCP packet */\n uint32 udp:1; /* UDP packet */\n uint32 tuc:1; /* TCP/UDP Checksum Correct */\n uint32 csum:16;\n#else\n uint32 csum:16;\n uint32 tuc:1; /* TCP/UDP Checksum Correct */\n uint32 udp:1; /* UDP packet */\n uint32 tcp:1; /* TCP packet */\n uint32 ipc:1; /* IP Checksum Correct */\n uint32 v6:1; /* IPv6 */\n uint32 v4:1; /* IPv4 */\n uint32 frg:1; /* IP Fragment */\n uint32 fcs:1; /* Frame CRC correct */\n uint32 type:7; /* completion type */\n uint32 gen:1; /* generation bit */\n#endif /* __BIG_ENDIAN_BITFIELD */\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_RxCompDesc;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_RxCompDescExt {\n __le32 dword1;\n uint8 segCnt; /* Number of aggregated packets */\n uint8 dupAckCnt; /* Number of duplicate Acks */\n __le16 tsDelta; /* TCP timestamp difference */\n __le32 dword2[2];\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_RxCompDescExt;\n\n/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */\n#define VMXNET3_RCD_TUC_SHIFT 16\n#define VMXNET3_RCD_IPC_SHIFT 19\n\n/* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */\n#define VMXNET3_RCD_TYPE_SHIFT 56\n#define VMXNET3_RCD_GEN_SHIFT 63\n\n/* csum OK for TCP/UDP pkts over IP */\n#define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT)\n\n/* value of RxCompDesc.rssType */\n#define VMXNET3_RCD_RSS_TYPE_NONE 0\n#define VMXNET3_RCD_RSS_TYPE_IPV4 1\n#define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2\n#define VMXNET3_RCD_RSS_TYPE_IPV6 3\n#define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4\n\n/* a union for accessing all cmd/completion descriptors */\ntypedef union Vmxnet3_GenericDesc {\n __le64 qword[2];\n __le32 dword[4];\n __le16 word[8];\n Vmxnet3_TxDesc txd;\n Vmxnet3_RxDesc rxd;\n Vmxnet3_TxCompDesc tcd;\n Vmxnet3_RxCompDesc rcd;\n Vmxnet3_RxCompDescExt rcdExt;\n} Vmxnet3_GenericDesc;\n\n#define VMXNET3_INIT_GEN 1\n\n/* Max size of a single tx buffer */\n#define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)\n\n/* # of tx desc needed for a tx buffer size */\n#define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE)\n\n/* max # of tx descs for a non-tso pkt */\n#define VMXNET3_MAX_TXD_PER_PKT 16\n\n/* Max size of a single rx buffer */\n#define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)\n/* Minimum size of a type 0 buffer */\n#define VMXNET3_MIN_T0_BUF_SIZE 128\n#define VMXNET3_MAX_CSUM_OFFSET 1024\n\n/* Ring base address alignment */\n#define VMXNET3_RING_BA_ALIGN 512\n#define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)\n\n/* Ring size must be a multiple of 32 */\n#define VMXNET3_RING_SIZE_ALIGN 32\n#define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)\n\n/* Max ring size */\n#define VMXNET3_TX_RING_MAX_SIZE 4096\n#define VMXNET3_TC_RING_MAX_SIZE 4096\n#define VMXNET3_RX_RING_MAX_SIZE 4096\n#define VMXNET3_RC_RING_MAX_SIZE 8192\n\n/* a list of reasons for queue stop */\n\n#define VMXNET3_ERR_NOEOP 0x80000000 /* cannot find the EOP desc of a pkt */\n#define VMXNET3_ERR_TXD_REUSE 0x80000001 /* reuse a TxDesc before tx completion */\n#define VMXNET3_ERR_BIG_PKT 0x80000002 /* too many TxDesc for a pkt */\n#define VMXNET3_ERR_DESC_NOT_SPT 0x80000003 /* descriptor type not supported */\n#define VMXNET3_ERR_SMALL_BUF 0x80000004 /* type 0 buffer too small */\n#define VMXNET3_ERR_STRESS 0x80000005 /* stress option firing in vmkernel */\n#define VMXNET3_ERR_SWITCH 0x80000006 /* mode switch failure */\n#define VMXNET3_ERR_TXD_INVALID 0x80000007 /* invalid TxDesc */\n\n/* completion descriptor types */\n#define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */\n#define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */\n#define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */\n\n#define VMXNET3_GOS_BITS_UNK 0 /* unknown */\n#define VMXNET3_GOS_BITS_32 1\n#define VMXNET3_GOS_BITS_64 2\n\n#define VMXNET3_GOS_TYPE_UNK 0 /* unknown */\n#define VMXNET3_GOS_TYPE_LINUX 1\n#define VMXNET3_GOS_TYPE_WIN 2\n#define VMXNET3_GOS_TYPE_SOLARIS 3\n#define VMXNET3_GOS_TYPE_FREEBSD 4\n#define VMXNET3_GOS_TYPE_PXE 5\n\n/* All structures in DriverShared are padded to multiples of 8 bytes */\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_GOSInfo {\n#ifdef __BIG_ENDIAN_BITFIELD\n uint32 gosMisc: 10; /* other info about gos */\n uint32 gosVer: 16; /* gos version */\n uint32 gosType: 4; /* which guest */\n uint32 gosBits: 2; /* 32-bit or 64-bit? */\n#else\n uint32 gosBits: 2; /* 32-bit or 64-bit? */\n uint32 gosType: 4; /* which guest */\n uint32 gosVer: 16; /* gos version */\n uint32 gosMisc: 10; /* other info about gos */\n#endif /* __BIG_ENDIAN_BITFIELD */\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_GOSInfo;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_DriverInfo {\n __le32 version; /* driver version */\n Vmxnet3_GOSInfo gos;\n __le32 vmxnet3RevSpt; /* vmxnet3 revision supported */\n __le32 uptVerSpt; /* upt version supported */\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_DriverInfo;\n\n#define VMXNET3_REV1_MAGIC 0xbabefee1\n\n/*\n * QueueDescPA must be 128 bytes aligned. It points to an array of\n * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.\n * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by\n * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.\n */\n#define VMXNET3_QUEUE_DESC_ALIGN 128\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_MiscConf {\n Vmxnet3_DriverInfo driverInfo;\n __le64 uptFeatures;\n __le64 ddPA; /* driver data PA */\n __le64 queueDescPA; /* queue descriptor table PA */\n __le32 ddLen; /* driver data len */\n __le32 queueDescLen; /* queue descriptor table len, in bytes */\n __le32 mtu;\n __le16 maxNumRxSG;\n uint8 numTxQueues;\n uint8 numRxQueues;\n __le32 reserved[4];\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_MiscConf;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_TxQueueConf {\n __le64 txRingBasePA;\n __le64 dataRingBasePA;\n __le64 compRingBasePA;\n __le64 ddPA; /* driver data */\n __le64 reserved;\n __le32 txRingSize; /* # of tx desc */\n __le32 dataRingSize; /* # of data desc */\n __le32 compRingSize; /* # of comp desc */\n __le32 ddLen; /* size of driver data */\n uint8 intrIdx;\n uint8 _pad[7];\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_TxQueueConf;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_RxQueueConf {\n __le64 rxRingBasePA[2];\n __le64 compRingBasePA;\n __le64 ddPA; /* driver data */\n __le64 reserved;\n __le32 rxRingSize[2]; /* # of rx desc */\n __le32 compRingSize; /* # of rx comp desc */\n __le32 ddLen; /* size of driver data */\n uint8 intrIdx;\n uint8 _pad[7];\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_RxQueueConf;\n\nenum vmxnet3_intr_mask_mode {\n VMXNET3_IMM_AUTO = 0,\n VMXNET3_IMM_ACTIVE = 1,\n VMXNET3_IMM_LAZY = 2\n};\n\nenum vmxnet3_intr_type {\n VMXNET3_IT_AUTO = 0,\n VMXNET3_IT_INTX = 1,\n VMXNET3_IT_MSI = 2,\n VMXNET3_IT_MSIX = 3\n};\n\n#define VMXNET3_MAX_TX_QUEUES 8\n#define VMXNET3_MAX_RX_QUEUES 16\n/* addition 1 for events */\n#define VMXNET3_MAX_INTRS 25\n\n/* value of intrCtrl */\n#define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_IntrConf {\n Bool autoMask;\n uint8 numIntrs; /* # of interrupts */\n uint8 eventIntrIdx;\n uint8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for each intr */\n __le32 intrCtrl;\n __le32 reserved[2];\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_IntrConf;\n\n/* one bit per VLAN ID, the size is in the units of uint32 */\n#define VMXNET3_VFT_SIZE (4096 / (sizeof(uint32) * 8))\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_QueueStatus {\n Bool stopped;\n uint8 _pad[3];\n __le32 error;\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_QueueStatus;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_TxQueueCtrl {\n __le32 txNumDeferred;\n __le32 txThreshold;\n __le64 reserved;\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_TxQueueCtrl;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_RxQueueCtrl {\n Bool updateRxProd;\n uint8 _pad[7];\n __le64 reserved;\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_RxQueueCtrl;\n\n#define VMXNET3_RXM_UCAST 0x01 /* unicast only */\n#define VMXNET3_RXM_MCAST 0x02 /* multicast passing the filters */\n#define VMXNET3_RXM_BCAST 0x04 /* broadcast only */\n#define VMXNET3_RXM_ALL_MULTI 0x08 /* all multicast */\n#define VMXNET3_RXM_PROMISC 0x10 /* promiscuous */\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_RxFilterConf {\n __le32 rxMode; /* VMXNET3_RXM_xxx */\n __le16 mfTableLen; /* size of the multicast filter table */\n __le16 _pad1;\n __le64 mfTablePA; /* PA of the multicast filters table */\n __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_RxFilterConf;\n\n#define VMXNET3_PM_MAX_FILTERS 6\n#define VMXNET3_PM_MAX_PATTERN_SIZE 128\n#define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)\n\n#define VMXNET3_PM_WAKEUP_MAGIC 0x01 /* wake up on magic pkts */\n#define VMXNET3_PM_WAKEUP_FILTER 0x02 /* wake up on pkts matching filters */\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_PM_PktFilter {\n uint8 maskSize;\n uint8 patternSize;\n uint8 mask[VMXNET3_PM_MAX_MASK_SIZE];\n uint8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];\n uint8 pad[6];\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_PM_PktFilter;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_PMConf {\n __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */\n uint8 numFilters;\n uint8 pad[5];\n Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_PMConf;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_VariableLenConfDesc {\n __le32 confVer;\n __le32 confLen;\n __le64 confPA;\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_VariableLenConfDesc;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_DSDevRead {\n /* read-only region for device, read by dev in response to a SET cmd */\n Vmxnet3_MiscConf misc;\n Vmxnet3_IntrConf intrConf;\n Vmxnet3_RxFilterConf rxFilterConf;\n Vmxnet3_VariableLenConfDesc rssConfDesc;\n Vmxnet3_VariableLenConfDesc pmConfDesc;\n Vmxnet3_VariableLenConfDesc pluginConfDesc;\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_DSDevRead;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_TxQueueDesc {\n Vmxnet3_TxQueueCtrl ctrl;\n Vmxnet3_TxQueueConf conf;\n /* Driver read after a GET command */\n Vmxnet3_QueueStatus status;\n UPT1_TxStats stats;\n uint8 _pad[88]; /* 128 aligned */\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_TxQueueDesc;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_RxQueueDesc {\n Vmxnet3_RxQueueCtrl ctrl;\n Vmxnet3_RxQueueConf conf;\n /* Driver read after a GET command */\n Vmxnet3_QueueStatus status;\n UPT1_RxStats stats;\n uint8 _pad[88]; /* 128 aligned */\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_RxQueueDesc;\n\ntypedef\n#include \"vmware_pack_begin.h\"\nstruct Vmxnet3_DriverShared {\n __le32 magic;\n __le32 pad; /* make devRead start at 64-bit boundaries */\n Vmxnet3_DSDevRead devRead;\n __le32 ecr;\n __le32 reserved[5];\n}\n#include \"vmware_pack_end.h\"\nVmxnet3_DriverShared;\n\n#define VMXNET3_ECR_RQERR (1 << 0)\n#define VMXNET3_ECR_TQERR (1 << 1)\n#define VMXNET3_ECR_LINK (1 << 2)\n#define VMXNET3_ECR_DIC (1 << 3)\n#define VMXNET3_ECR_DEBUG (1 << 4)\n\n/* flip the gen bit of a ring */\n#define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)\n\n/* only use this if moving the idx won't affect the gen bit */\n#define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \\\ndo {\\\n (idx)++;\\\n if (UNLIKELY((idx) == (ring_size))) {\\\n (idx) = 0;\\\n }\\\n} while (0)\n\n#define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \\\n vfTable[vid >> 5] |= (1 << (vid & 31))\n#define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \\\n vfTable[vid >> 5] &= ~(1 << (vid & 31))\n\n#define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \\\n ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)\n\n#define VMXNET3_MAX_MTU 9000\n#define VMXNET3_MIN_MTU 60\n\n#define VMXNET3_LINK_UP (10000 << 16 | 1) // 10 Gbps, up\n#define VMXNET3_LINK_DOWN 0\n\n#define VMXWIFI_DRIVER_SHARED_LEN 8192\n\n#define VMXNET3_DID_PASSTHRU 0xFFFF\n\n#endif /* _VMXNET3_DEFS_H_ */\n" }, { "path": "drivers/net/vmxnet3/base/vmxnet3_osdep.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VMXNET3_OSDEP_H\n#define _VMXNET3_OSDEP_H\n\ntypedef uint64_t\tuint64;\ntypedef uint32_t\tuint32;\ntypedef uint16_t\tuint16;\ntypedef uint8_t\t\tuint8;\ntypedef int\t\tbool;\ntypedef char\t\tBool;\n\n#ifndef UNLIKELY\n#define UNLIKELY(x) __builtin_expect((x),0)\n#endif /* unlikely */\n\n#endif /* _VMXNET3_OSDEP_H */\n" }, { "path": "drivers/net/vmxnet3/vmxnet3_ethdev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"base/vmxnet3_defs.h\"\n\n#include \"vmxnet3_ring.h\"\n#include \"vmxnet3_logs.h\"\n#include \"vmxnet3_ethdev.h\"\n\n#define PROCESS_SYS_EVENTS 0\n\nstatic int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);\nstatic int vmxnet3_dev_configure(struct rte_eth_dev *dev);\nstatic int vmxnet3_dev_start(struct rte_eth_dev *dev);\nstatic void vmxnet3_dev_stop(struct rte_eth_dev *dev);\nstatic void vmxnet3_dev_close(struct rte_eth_dev *dev);\nstatic void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);\nstatic void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);\nstatic void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);\nstatic void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);\nstatic void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);\nstatic int vmxnet3_dev_link_update(struct rte_eth_dev *dev,\n\t\t\t\tint wait_to_complete);\nstatic void vmxnet3_dev_stats_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_stats *stats);\nstatic void vmxnet3_dev_info_get(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_dev_info *dev_info);\nstatic int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t vid, int on);\nstatic void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);\nstatic void vmxnet3_dev_vlan_offload_set_clear(struct rte_eth_dev *dev,\n\t\t\t\t\t\tint mask, int clear);\n\n#if PROCESS_SYS_EVENTS == 1\nstatic void vmxnet3_process_events(struct vmxnet3_hw *);\n#endif\n/*\n * The set of PCI devices this driver supports\n */\nstatic const struct rte_pci_id pci_id_vmxnet3_map[] = {\n\n#define RTE_PCI_DEV_ID_DECL_VMXNET3(vend, dev) {RTE_PCI_DEVICE(vend, dev)},\n#include \"rte_pci_dev_ids.h\"\n\n{ .vendor_id = 0, /* sentinel */ },\n};\n\nstatic const struct eth_dev_ops vmxnet3_eth_dev_ops = {\n\t.dev_configure = vmxnet3_dev_configure,\n\t.dev_start = vmxnet3_dev_start,\n\t.dev_stop = vmxnet3_dev_stop,\n\t.dev_close = vmxnet3_dev_close,\n\t.promiscuous_enable = vmxnet3_dev_promiscuous_enable,\n\t.promiscuous_disable = vmxnet3_dev_promiscuous_disable,\n\t.allmulticast_enable = vmxnet3_dev_allmulticast_enable,\n\t.allmulticast_disable = vmxnet3_dev_allmulticast_disable,\n\t.link_update = vmxnet3_dev_link_update,\n\t.stats_get = vmxnet3_dev_stats_get,\n\t.dev_infos_get = vmxnet3_dev_info_get,\n\t.vlan_filter_set = vmxnet3_dev_vlan_filter_set,\n\t.vlan_offload_set = vmxnet3_dev_vlan_offload_set,\n\t.rx_queue_setup = vmxnet3_dev_rx_queue_setup,\n\t.rx_queue_release = vmxnet3_dev_rx_queue_release,\n\t.tx_queue_setup = vmxnet3_dev_tx_queue_setup,\n\t.tx_queue_release = vmxnet3_dev_tx_queue_release,\n};\n\nstatic const struct rte_memzone *\ngpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,\n\t\tconst char *post_string, int socket_id, uint16_t align)\n{\n\tchar z_name[RTE_MEMZONE_NAMESIZE];\n\tconst struct rte_memzone *mz;\n\n\tsnprintf(z_name, sizeof(z_name), \"%s_%d_%s\",\n\t\t\t\t\tdev->driver->pci_drv.name, dev->data->port_id, post_string);\n\n\tmz = rte_memzone_lookup(z_name);\n\tif (mz)\n\t\treturn mz;\n\n\treturn rte_memzone_reserve_aligned(z_name, size,\n\t\t\tsocket_id, 0, align);\n}\n\n/**\n * Atomically reads the link status information from global\n * structure rte_eth_dev.\n *\n * @param dev\n * - Pointer to the structure rte_eth_dev to read from.\n * - Pointer to the buffer to be saved with the link status.\n *\n * @return\n * - On success, zero.\n * - On failure, negative value.\n */\n\nstatic int\nvmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = link;\n\tstruct rte_eth_link *src = &(dev->data->dev_link);\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * Atomically writes the link status information into global\n * structure rte_eth_dev.\n *\n * @param dev\n * - Pointer to the structure rte_eth_dev to write to.\n * - Pointer to the buffer to be saved with the link status.\n *\n * @return\n * - On success, zero.\n * - On failure, negative value.\n */\nstatic int\nvmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = &(dev->data->dev_link);\n\tstruct rte_eth_link *src = link;\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * This function is based on vmxnet3_disable_intr()\n */\nstatic void\nvmxnet3_disable_intr(struct vmxnet3_hw *hw)\n{\n\tint i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\thw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;\n\tfor (i = 0; i < VMXNET3_MAX_INTRS; i++)\n\t\t\tVMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);\n}\n\n/*\n * It returns 0 on success.\n */\nstatic int\neth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)\n{\n\tstruct rte_pci_device *pci_dev;\n\tstruct vmxnet3_hw *hw = eth_dev->data->dev_private;\n\tuint32_t mac_hi, mac_lo, ver;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\teth_dev->dev_ops = &vmxnet3_eth_dev_ops;\n\teth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;\n\teth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;\n\tpci_dev = eth_dev->pci_dev;\n\n\t/*\n\t * for secondary processes, we don't initialize any further as primary\n\t * has already done this work.\n\t */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn 0;\n\n\t/* Vendor and Device ID need to be set before init of shared code */\n\thw->device_id = pci_dev->id.device_id;\n\thw->vendor_id = pci_dev->id.vendor_id;\n\thw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;\n\thw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;\n\n\thw->num_rx_queues = 1;\n\thw->num_tx_queues = 1;\n\thw->bufs_per_pkt = 1;\n\n\t/* Check h/w version compatibility with driver. */\n\tver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);\n\tPMD_INIT_LOG(DEBUG, \"Hardware version : %d\", ver);\n\tif (ver & 0x1)\n\t\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 1);\n\telse {\n\t\tPMD_INIT_LOG(ERR, \"Incompatible h/w version, should be 0x1\");\n\t\treturn -EIO;\n\t}\n\n\t/* Check UPT version compatibility with driver. */\n\tver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);\n\tPMD_INIT_LOG(DEBUG, \"UPT hardware version : %d\", ver);\n\tif (ver & 0x1)\n\t\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);\n\telse {\n\t\tPMD_INIT_LOG(ERR, \"Incompatible UPT version.\");\n\t\treturn -EIO;\n\t}\n\n\t/* Getting MAC Address */\n\tmac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);\n\tmac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);\n\tmemcpy(hw->perm_addr , &mac_lo, 4);\n\tmemcpy(hw->perm_addr+4, &mac_hi, 2);\n\n\t/* Allocate memory for storing MAC addresses */\n\teth_dev->data->mac_addrs = rte_zmalloc(\"vmxnet3\", ETHER_ADDR_LEN *\n\t\t\t\t\t VMXNET3_MAX_MAC_ADDRS, 0);\n\tif (eth_dev->data->mac_addrs == NULL) {\n\t\tPMD_INIT_LOG(ERR,\n\t\t\t \"Failed to allocate %d bytes needed to store MAC addresses\",\n\t\t\t ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);\n\t\treturn -ENOMEM;\n\t}\n\t/* Copy the permanent MAC address */\n\tether_addr_copy((struct ether_addr *) hw->perm_addr,\n\t\t\tð_dev->data->mac_addrs[0]);\n\n\tPMD_INIT_LOG(DEBUG, \"MAC Address : %02x:%02x:%02x:%02x:%02x:%02x\",\n\t\t hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],\n\t\t hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);\n\n\t/* Put device in Quiesce Mode */\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);\n\n\treturn 0;\n}\n\nstatic struct eth_driver rte_vmxnet3_pmd = {\n\t.pci_drv = {\n\t\t.name = \"rte_vmxnet3_pmd\",\n\t\t.id_table = pci_id_vmxnet3_map,\n\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n\t},\n\t.eth_dev_init = eth_vmxnet3_dev_init,\n\t.dev_private_size = sizeof(struct vmxnet3_hw),\n};\n\n/*\n * Driver initialization routine.\n * Invoked once at EAL init time.\n * Register itself as the [Poll Mode] Driver of Virtual PCI VMXNET3 devices.\n */\nstatic int\nrte_vmxnet3_pmd_init(const char *name __rte_unused, const char *param __rte_unused)\n{\n\tPMD_INIT_FUNC_TRACE();\n\n\trte_eth_driver_register(&rte_vmxnet3_pmd);\n\treturn 0;\n}\n\nstatic int\nvmxnet3_dev_configure(struct rte_eth_dev *dev)\n{\n\tconst struct rte_memzone *mz;\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\tsize_t size;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (dev->data->nb_rx_queues > UINT8_MAX ||\n\t dev->data->nb_tx_queues > UINT8_MAX)\n\t\treturn -EINVAL;\n\n\tsize = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +\n\t\tdev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);\n\n\tif (size > UINT16_MAX)\n\t\treturn -EINVAL;\n\n\thw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;\n\thw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;\n\n\t/*\n\t * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead\n\t * on current socket\n\t */\n\tmz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),\n\t\t\t \"shared\", rte_socket_id(), 8);\n\n\tif (mz == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"ERROR: Creating shared zone\");\n\t\treturn -ENOMEM;\n\t}\n\tmemset(mz->addr, 0, mz->len);\n\n\thw->shared = mz->addr;\n\thw->sharedPA = mz->phys_addr;\n\n\t/*\n\t * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc\n\t * on current socket\n\t */\n\tmz = gpa_zone_reserve(dev, size, \"queuedesc\",\n\t\t\t rte_socket_id(), VMXNET3_QUEUE_DESC_ALIGN);\n\tif (mz == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"ERROR: Creating queue descriptors zone\");\n\t\treturn -ENOMEM;\n\t}\n\tmemset(mz->addr, 0, mz->len);\n\n\thw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;\n\thw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);\n\n\thw->queueDescPA = mz->phys_addr;\n\thw->queue_desc_len = (uint16_t)size;\n\n\tif (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {\n\n\t\t/* Allocate memory structure for UPT1_RSSConf and configure */\n\t\tmz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), \"rss_conf\",\n\t\t\t\t rte_socket_id(), RTE_CACHE_LINE_SIZE);\n\t\tif (mz == NULL) {\n\t\t\tPMD_INIT_LOG(ERR,\n\t\t\t\t \"ERROR: Creating rss_conf structure zone\");\n\t\t\treturn -ENOMEM;\n\t\t}\n\t\tmemset(mz->addr, 0, mz->len);\n\n\t\thw->rss_conf = mz->addr;\n\t\thw->rss_confPA = mz->phys_addr;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nvmxnet3_setup_driver_shared(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_conf port_conf = dev->data->dev_conf;\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\tVmxnet3_DriverShared *shared = hw->shared;\n\tVmxnet3_DSDevRead *devRead = &shared->devRead;\n\tuint32_t *mac_ptr;\n\tuint32_t val, i;\n\tint ret, mask;\n\n\tshared->magic = VMXNET3_REV1_MAGIC;\n\tdevRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;\n\n\t/* Setting up Guest OS information */\n\tdevRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ?\n\t\tVMXNET3_GOS_BITS_32 :\n\t\tVMXNET3_GOS_BITS_64;\n\tdevRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;\n\tdevRead->misc.driverInfo.vmxnet3RevSpt = 1;\n\tdevRead->misc.driverInfo.uptVerSpt = 1;\n\n\tdevRead->misc.mtu = rte_le_to_cpu_32(dev->data->mtu);\n\tdevRead->misc.queueDescPA = hw->queueDescPA;\n\tdevRead->misc.queueDescLen = hw->queue_desc_len;\n\tdevRead->misc.numTxQueues = hw->num_tx_queues;\n\tdevRead->misc.numRxQueues = hw->num_rx_queues;\n\n\t/*\n\t * Set number of interrupts to 1\n\t * PMD disables all the interrupts but this is MUST to activate device\n\t * It needs at least one interrupt for link events to handle\n\t * So we'll disable it later after device activation if needed\n\t */\n\tdevRead->intrConf.numIntrs = 1;\n\tdevRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;\n\n\tfor (i = 0; i < hw->num_tx_queues; i++) {\n\t\tVmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];\n\t\tvmxnet3_tx_queue_t *txq = dev->data->tx_queues[i];\n\n\t\ttqd->ctrl.txNumDeferred = 0;\n\t\ttqd->ctrl.txThreshold = 1;\n\t\ttqd->conf.txRingBasePA = txq->cmd_ring.basePA;\n\t\ttqd->conf.compRingBasePA = txq->comp_ring.basePA;\n\t\ttqd->conf.dataRingBasePA = txq->data_ring.basePA;\n\n\t\ttqd->conf.txRingSize = txq->cmd_ring.size;\n\t\ttqd->conf.compRingSize = txq->comp_ring.size;\n\t\ttqd->conf.dataRingSize = txq->data_ring.size;\n\t\ttqd->conf.intrIdx = txq->comp_ring.intr_idx;\n\t\ttqd->status.stopped = TRUE;\n\t\ttqd->status.error = 0;\n\t\tmemset(&tqd->stats, 0, sizeof(tqd->stats));\n\t}\n\n\tfor (i = 0; i < hw->num_rx_queues; i++) {\n\t\tVmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i];\n\t\tvmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];\n\n\t\trqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;\n\t\trqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;\n\t\trqd->conf.compRingBasePA = rxq->comp_ring.basePA;\n\n\t\trqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size;\n\t\trqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size;\n\t\trqd->conf.compRingSize = rxq->comp_ring.size;\n\t\trqd->conf.intrIdx = rxq->comp_ring.intr_idx;\n\t\trqd->status.stopped = TRUE;\n\t\trqd->status.error = 0;\n\t\tmemset(&rqd->stats, 0, sizeof(rqd->stats));\n\t}\n\n\t/* RxMode set to 0 of VMXNET3_RXM_xxx */\n\tdevRead->rxFilterConf.rxMode = 0;\n\n\t/* Setting up feature flags */\n\tif (dev->data->dev_conf.rxmode.hw_ip_checksum)\n\t\tdevRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;\n\n\tif (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {\n\t\tret = vmxnet3_rss_configure(dev);\n\t\tif (ret != VMXNET3_SUCCESS)\n\t\t\treturn ret;\n\n\t\tdevRead->misc.uptFeatures |= VMXNET3_F_RSS;\n\t\tdevRead->rssConfDesc.confVer = 1;\n\t\tdevRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);\n\t\tdevRead->rssConfDesc.confPA = hw->rss_confPA;\n\t}\n\n\tmask = 0;\n\tif (dev->data->dev_conf.rxmode.hw_vlan_strip)\n\t\tmask |= ETH_VLAN_STRIP_MASK;\n\n\tif (dev->data->dev_conf.rxmode.hw_vlan_filter)\n\t\tmask |= ETH_VLAN_FILTER_MASK;\n\n\tvmxnet3_dev_vlan_offload_set_clear(dev, mask, 1);\n\n\tPMD_INIT_LOG(DEBUG,\n\t\t \"Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x\",\n\t\t hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],\n\t\t hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);\n\n\t/* Write MAC Address back to device */\n\tmac_ptr = (uint32_t *)hw->perm_addr;\n\tval = *mac_ptr;\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);\n\n\tval = (hw->perm_addr[5] << 8) | hw->perm_addr[4];\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);\n\n\treturn VMXNET3_SUCCESS;\n}\n\n/*\n * Configure device link speed and setup link.\n * Must be called after eth_vmxnet3_dev_init. Other wise it might fail\n * It returns 0 on success.\n */\nstatic int\nvmxnet3_dev_start(struct rte_eth_dev *dev)\n{\n\tint status, ret;\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tret = vmxnet3_setup_driver_shared(dev);\n\tif (ret != VMXNET3_SUCCESS)\n\t\treturn ret;\n\n\t/* Exchange shared data with device */\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,\n\t\t\t VMXNET3_GET_ADDR_LO(hw->sharedPA));\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,\n\t\t\t VMXNET3_GET_ADDR_HI(hw->sharedPA));\n\n\t/* Activate device by register write */\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);\n\tstatus = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);\n\n\tif (status != 0) {\n\t\tPMD_INIT_LOG(ERR, \"Device activation in %s(): UNSUCCESSFUL\", __func__);\n\t\treturn -1;\n\t}\n\n\t/* Disable interrupts */\n\tvmxnet3_disable_intr(hw);\n\n\t/*\n\t * Load RX queues with blank mbufs and update next2fill index for device\n\t * Update RxMode of the device\n\t */\n\tret = vmxnet3_dev_rxtx_init(dev);\n\tif (ret != VMXNET3_SUCCESS) {\n\t\tPMD_INIT_LOG(ERR, \"Device receive init in %s: UNSUCCESSFUL\", __func__);\n\t\treturn ret;\n\t}\n\n\t/* Setting proper Rx Mode and issue Rx Mode Update command */\n\tvmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);\n\n\t/*\n\t * Don't need to handle events for now\n\t */\n#if PROCESS_SYS_EVENTS == 1\n\tevents = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR);\n\tPMD_INIT_LOG(DEBUG, \"Reading events: 0x%X\", events);\n\tvmxnet3_process_events(hw);\n#endif\n\treturn status;\n}\n\n/*\n * Stop device: disable rx and tx functions to allow for reconfiguring.\n */\nstatic void\nvmxnet3_dev_stop(struct rte_eth_dev *dev)\n{\n\tstruct rte_eth_link link;\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif (hw->adapter_stopped == TRUE) {\n\t\tPMD_INIT_LOG(DEBUG, \"Device already closed.\");\n\t\treturn;\n\t}\n\n\t/* disable interrupts */\n\tvmxnet3_disable_intr(hw);\n\n\t/* quiesce the device first */\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);\n\n\t/* reset the device */\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);\n\tPMD_INIT_LOG(DEBUG, \"Device reset.\");\n\thw->adapter_stopped = FALSE;\n\n\tvmxnet3_dev_clear_queues(dev);\n\n\t/* Clear recorded link status */\n\tmemset(&link, 0, sizeof(link));\n\tvmxnet3_dev_atomic_write_link_status(dev, &link);\n}\n\n/*\n * Reset and stop device.\n */\nstatic void\nvmxnet3_dev_close(struct rte_eth_dev *dev)\n{\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tvmxnet3_dev_stop(dev);\n\thw->adapter_stopped = TRUE;\n}\n\nstatic void\nvmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tunsigned int i;\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);\n\n\tRTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);\n\tfor (i = 0; i < hw->num_tx_queues; i++) {\n\t\tstruct UPT1_TxStats *txStats = &hw->tqd_start[i].stats;\n\n\t\tstats->q_opackets[i] = txStats->ucastPktsTxOK +\n\t\t\ttxStats->mcastPktsTxOK +\n\t\t\ttxStats->bcastPktsTxOK;\n\t\tstats->q_obytes[i] = txStats->ucastBytesTxOK +\n\t\t\ttxStats->mcastBytesTxOK +\n\t\t\ttxStats->bcastBytesTxOK;\n\n\t\tstats->opackets += stats->q_opackets[i];\n\t\tstats->obytes += stats->q_obytes[i];\n\t\tstats->oerrors += txStats->pktsTxError +\n\t\t\ttxStats->pktsTxDiscard;\n\t}\n\n\tRTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);\n\tfor (i = 0; i < hw->num_rx_queues; i++) {\n\t\tstruct UPT1_RxStats *rxStats = &hw->rqd_start[i].stats;\n\n\t\tstats->q_ipackets[i] = rxStats->ucastPktsRxOK +\n\t\t\trxStats->mcastPktsRxOK +\n\t\t\trxStats->bcastPktsRxOK;\n\n\t\tstats->q_ibytes[i] = rxStats->ucastBytesRxOK +\n\t\t\trxStats->mcastBytesRxOK +\n\t\t\trxStats->bcastBytesRxOK;\n\n\t\tstats->ipackets += stats->q_ipackets[i];\n\t\tstats->ibytes += stats->q_ibytes[i];\n\n\t\tstats->q_errors[i] = rxStats->pktsRxError;\n\t\tstats->ierrors += rxStats->pktsRxError;\n\t\tstats->imcasts += rxStats->mcastPktsRxOK;\n\t\tstats->rx_nombuf += rxStats->pktsRxOutOfBuf;\n\t}\n}\n\nstatic void\nvmxnet3_dev_info_get(__attribute__((unused))struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n{\n\tdev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;\n\tdev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;\n\tdev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;\n\tdev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */\n\tdev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;\n\n\tdev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |\n\t\t\t\t\t\tETH_TXQ_FLAGS_NOOFFLOADS;\n\tdev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;\n}\n\n/* return 0 means link status changed, -1 means not changed */\nstatic int\nvmxnet3_dev_link_update(struct rte_eth_dev *dev, __attribute__((unused)) int wait_to_complete)\n{\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\tstruct rte_eth_link old, link;\n\tuint32_t ret;\n\n\tif (dev->data->dev_started == 0)\n\t\treturn -1; /* Link status doesn't change for stopped dev */\n\n\tmemset(&link, 0, sizeof(link));\n\tvmxnet3_dev_atomic_read_link_status(dev, &old);\n\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);\n\tret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);\n\n\tif (ret & 0x1) {\n\t\tlink.link_status = 1;\n\t\tlink.link_duplex = ETH_LINK_FULL_DUPLEX;\n\t\tlink.link_speed = ETH_LINK_SPEED_10000;\n\t}\n\n\tvmxnet3_dev_atomic_write_link_status(dev, &link);\n\n\treturn (old.link_status == link.link_status) ? -1 : 0;\n}\n\n/* Updating rxmode through Vmxnet3_DriverShared structure in adapter */\nstatic void\nvmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) {\n\n\tstruct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;\n\n\tif (set)\n\t\trxConf->rxMode = rxConf->rxMode | feature;\n\telse\n\t\trxConf->rxMode = rxConf->rxMode & (~feature);\n\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);\n}\n\n/* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */\nstatic void\nvmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)\n{\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\tuint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;\n\n\tmemset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);\n\tvmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);\n\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,\n\t\t\t VMXNET3_CMD_UPDATE_VLAN_FILTERS);\n}\n\n/* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */\nstatic void\nvmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)\n{\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\tuint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;\n\n\tmemcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);\n\tvmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,\n\t\t\t VMXNET3_CMD_UPDATE_VLAN_FILTERS);\n}\n\n/* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */\nstatic void\nvmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)\n{\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\n\tvmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);\n}\n\n/* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */\nstatic void\nvmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)\n{\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\n\tvmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);\n}\n\n/* Enable/disable filter on vlan */\nstatic int\nvmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)\n{\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\tstruct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;\n\tuint32_t *vf_table = rxConf->vfTable;\n\n\t/* save state for restore */\n\tif (on)\n\t\tVMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);\n\telse\n\t\tVMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);\n\n\t/* don't change active filter if in promiscious mode */\n\tif (rxConf->rxMode & VMXNET3_RXM_PROMISC)\n\t\treturn 0;\n\n\t/* set in hardware */\n\tif (on)\n\t\tVMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);\n\telse\n\t\tVMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);\n\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,\n\t\t\t VMXNET3_CMD_UPDATE_VLAN_FILTERS);\n\treturn 0;\n}\n\nstatic void\nvmxnet3_dev_vlan_offload_set_clear(struct rte_eth_dev *dev,\n\t\t\t\t int mask, int clear)\n{\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\tVmxnet3_DSDevRead *devRead = &hw->shared->devRead;\n\tuint32_t *vf_table = devRead->rxFilterConf.vfTable;\n\n\tif (mask & ETH_VLAN_STRIP_MASK)\n\t\tdevRead->misc.uptFeatures |= UPT1_F_RXVLAN;\n\telse\n\t\tdevRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;\n\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,\n\t\t\t VMXNET3_CMD_UPDATE_FEATURE);\n\n\tif (mask & ETH_VLAN_FILTER_MASK) {\n\t\tif (clear) {\n\t\t\tmemset(hw->shadow_vfta, 0,\n\t\t\t VMXNET3_VFT_TABLE_SIZE);\n\t\t\t/* allow untagged pkts */\n\t\t\tVMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);\n\t\t}\n\t\tmemcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);\n\t} else {\n\t\t/* allow any pkts -- no filtering */\n\t\tif (clear)\n\t\t\tmemset(hw->shadow_vfta, 0xff, VMXNET3_VFT_TABLE_SIZE);\n\t\tmemset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);\n\t}\n\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,\n\t\t\t VMXNET3_CMD_UPDATE_VLAN_FILTERS);\n}\n\nstatic void\nvmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)\n{\n\tvmxnet3_dev_vlan_offload_set_clear(dev, mask, 0);\n}\n\n#if PROCESS_SYS_EVENTS == 1\nstatic void\nvmxnet3_process_events(struct vmxnet3_hw *hw)\n{\n\tuint32_t events = hw->shared->ecr;\n\n\tif (!events) {\n\t\tPMD_INIT_LOG(ERR, \"No events to process in %s()\", __func__);\n\t\treturn;\n\t}\n\n\t/*\n\t * ECR bits when written with 1b are cleared. Hence write\n\t * events back to ECR so that the bits which were set will be reset.\n\t */\n\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);\n\n\t/* Check if link state has changed */\n\tif (events & VMXNET3_ECR_LINK)\n\t\tPMD_INIT_LOG(ERR,\n\t\t\t \"Process events in %s(): VMXNET3_ECR_LINK event\", __func__);\n\n\t/* Check if there is an error on xmit/recv queues */\n\tif (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {\n\t\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_QUEUE_STATUS);\n\n\t\tif (hw->tqd_start->status.stopped)\n\t\t\tPMD_INIT_LOG(ERR, \"tq error 0x%x\",\n\t\t\t\t hw->tqd_start->status.error);\n\n\t\tif (hw->rqd_start->status.stopped)\n\t\t\tPMD_INIT_LOG(ERR, \"rq error 0x%x\",\n\t\t\t\t hw->rqd_start->status.error);\n\n\t\t/* Reset the device */\n\t\t/* Have to reset the device */\n\t}\n\n\tif (events & VMXNET3_ECR_DIC)\n\t\tPMD_INIT_LOG(ERR, \"Device implementation change event.\");\n\n\tif (events & VMXNET3_ECR_DEBUG)\n\t\tPMD_INIT_LOG(ERR, \"Debug event generated by device.\");\n\n}\n#endif\n\nstatic struct rte_driver rte_vmxnet3_driver = {\n\t.type = PMD_PDEV,\n\t.init = rte_vmxnet3_pmd_init,\n};\n\nPMD_REGISTER_DRIVER(rte_vmxnet3_driver);\n" }, { "path": "drivers/net/vmxnet3/vmxnet3_ethdev.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VMXNET3_ETHDEV_H_\n#define _VMXNET3_ETHDEV_H_\n\n#ifdef RTE_LIBRTE_VMXNET3_DEBUG_DRIVER\n#define VMXNET3_ASSERT(x) do {\t\t\t \\\n\tif (!(x)) rte_panic(\"VMXNET3: %s\\n\", #x); \\\n} while(0)\n#else\n#define VMXNET3_ASSERT(x) do { (void)(x); } while (0)\n#endif\n\n#define VMXNET3_MAX_MAC_ADDRS 1\n\n/* UPT feature to negotiate */\n#define VMXNET3_F_RXCSUM 0x0001\n#define VMXNET3_F_RSS 0x0002\n#define VMXNET3_F_RXVLAN 0x0004\n#define VMXNET3_F_LRO 0x0008\n\n/* Hash Types supported by device */\n#define VMXNET3_RSS_HASH_TYPE_NONE 0x0\n#define VMXNET3_RSS_HASH_TYPE_IPV4 0x01\n#define VMXNET3_RSS_HASH_TYPE_TCP_IPV4 0x02\n#define VMXNET3_RSS_HASH_TYPE_IPV6 0x04\n#define VMXNET3_RSS_HASH_TYPE_TCP_IPV6 0x08\n\n#define VMXNET3_RSS_HASH_FUNC_NONE 0x0\n#define VMXNET3_RSS_HASH_FUNC_TOEPLITZ 0x01\n\n#define VMXNET3_RSS_MAX_KEY_SIZE 40\n#define VMXNET3_RSS_MAX_IND_TABLE_SIZE 128\n\n#define VMXNET3_RSS_OFFLOAD_ALL ( \\\n\tETH_RSS_IPV4 | \\\n\tETH_RSS_NONFRAG_IPV4_TCP | \\\n\tETH_RSS_IPV6 | \\\n\tETH_RSS_NONFRAG_IPV6_TCP)\n\n/* RSS configuration structure - shared with device through GPA */\ntypedef\nstruct VMXNET3_RSSConf {\n\tuint16_t hashType;\n\tuint16_t hashFunc;\n\tuint16_t hashKeySize;\n\tuint16_t indTableSize;\n\tuint8_t hashKey[VMXNET3_RSS_MAX_KEY_SIZE];\n\t/*\n\t * indTable is only element that can be changed without\n\t * device quiesce-reset-update-activation cycle\n\t */\n\tuint8_t indTable[VMXNET3_RSS_MAX_IND_TABLE_SIZE];\n} VMXNET3_RSSConf;\n\ntypedef\nstruct vmxnet3_mf_table {\n\tvoid *mfTableBase; /* Multicast addresses list */\n\tuint64_t mfTablePA; /* Physical address of the list */\n\tuint16_t num_addrs; /* number of multicast addrs */\n} vmxnet3_mf_table_t;\n\nstruct vmxnet3_hw {\n\n\tuint8_t *hw_addr0;\t/* BAR0: PT-Passthrough Regs */\n\tuint8_t *hw_addr1;\t/* BAR1: VD-Virtual Device Regs */\n\t/* BAR2: MSI-X Regs */\n\t/* BAR3: Port IO */\n\tvoid *back;\n\n\tuint16_t device_id;\n\tuint16_t vendor_id;\n\tuint16_t subsystem_device_id;\n\tuint16_t subsystem_vendor_id;\n\tbool adapter_stopped;\n\n\tuint8_t perm_addr[ETHER_ADDR_LEN];\n\tuint8_t num_tx_queues;\n\tuint8_t num_rx_queues;\n\tuint8_t bufs_per_pkt;\n\n\tVmxnet3_TxQueueDesc *tqd_start;\t/* start address of all tx queue desc */\n\tVmxnet3_RxQueueDesc *rqd_start;\t/* start address of all rx queue desc */\n\n\tVmxnet3_DriverShared *shared;\n\tuint64_t sharedPA;\n\n\tuint64_t queueDescPA;\n\tuint16_t queue_desc_len;\n\n\tVMXNET3_RSSConf\t\t *rss_conf;\n\tuint64_t\t\t\t rss_confPA;\n\tvmxnet3_mf_table_t *mf_table;\n\tuint32_t\t shadow_vfta[VMXNET3_VFT_SIZE];\n#define VMXNET3_VFT_TABLE_SIZE (VMXNET3_VFT_SIZE * sizeof(uint32_t))\n};\n\n#define VMXNET3_GET_ADDR_LO(reg) ((uint32_t)(reg))\n#define VMXNET3_GET_ADDR_HI(reg) ((uint32_t)(((uint64_t)(reg)) >> 32))\n\n/* Config space read/writes */\n\n#define VMXNET3_PCI_REG(reg) (*((volatile uint32_t *)(reg)))\n\nstatic inline uint32_t vmxnet3_read_addr(volatile void *addr)\n{\n\treturn VMXNET3_PCI_REG(addr);\n}\n\n#define VMXNET3_PCI_REG_WRITE(reg, value) do { \\\n\tVMXNET3_PCI_REG((reg)) = (value); \\\n} while(0)\n\n#define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \\\n\t((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg)))\n#define VMXNET3_READ_BAR0_REG(hw, reg) \\\n\tvmxnet3_read_addr(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)))\n#define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \\\n\tVMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)), (value))\n\n#define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \\\n\t((volatile uint32_t *)((char *)(hw)->hw_addr1 + (reg)))\n#define VMXNET3_READ_BAR1_REG(hw, reg) \\\n\tvmxnet3_read_addr(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)))\n#define VMXNET3_WRITE_BAR1_REG(hw, reg, value) \\\n\tVMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)), (value))\n\n/*\n * RX/TX function prototypes\n */\n\nvoid vmxnet3_dev_clear_queues(struct rte_eth_dev *dev);\n\nvoid vmxnet3_dev_rx_queue_release(void *rxq);\nvoid vmxnet3_dev_tx_queue_release(void *txq);\n\nint vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n\t\tuint16_t nb_rx_desc, unsigned int socket_id,\n\t\tconst struct rte_eth_rxconf *rx_conf,\n\t\tstruct rte_mempool *mb_pool);\nint vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n\t\tuint16_t nb_tx_desc, unsigned int socket_id,\n\t\tconst struct rte_eth_txconf *tx_conf);\n\nint vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev);\n\nint vmxnet3_rss_configure(struct rte_eth_dev *dev);\n\nuint16_t vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n\t\tuint16_t nb_pkts);\nuint16_t vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t\tuint16_t nb_pkts);\n\n#endif /* _VMXNET3_ETHDEV_H_ */\n" }, { "path": "drivers/net/vmxnet3/vmxnet3_logs.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VMXNET3_LOGS_H_\n#define _VMXNET3_LOGS_H_\n\n#ifdef RTE_LIBRTE_VMXNET3_DEBUG_INIT\n#define PMD_INIT_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, \" >>\")\n#else\n#define PMD_INIT_LOG(level, fmt, args...) do { } while(0)\n#define PMD_INIT_FUNC_TRACE() do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_VMXNET3_DEBUG_RX\n#define PMD_RX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_RX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_VMXNET3_DEBUG_TX\n#define PMD_TX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_TX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_VMXNET3_DEBUG_TX_FREE\n#define PMD_TX_FREE_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_TX_FREE_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_VMXNET3_DEBUG_DRIVER\n#define PMD_DRV_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#else\n#define PMD_DRV_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#endif /* _VMXNET3_LOGS_H_ */\n" }, { "path": "drivers/net/vmxnet3/vmxnet3_ring.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VMXNET3_RING_H_\n#define _VMXNET3_RING_H_\n\n#define VMXNET3_RX_CMDRING_SIZE 2\n\n#define VMXNET3_DRIVER_VERSION_NUM 0x01012000\n\n/* Default ring size */\n#define VMXNET3_DEF_TX_RING_SIZE 512\n#define VMXNET3_DEF_RX_RING_SIZE 128\n\n#define VMXNET3_SUCCESS 0\n#define VMXNET3_FAIL -1\n\n#define TRUE 1\n#define FALSE 0\n\n\ntypedef struct vmxnet3_buf_info {\n\tuint16_t len;\n\tstruct rte_mbuf *m;\n\tuint64_t bufPA;\n} vmxnet3_buf_info_t;\n\ntypedef struct vmxnet3_cmd_ring {\n\tvmxnet3_buf_info_t *buf_info;\n\tuint32_t size;\n\tuint32_t next2fill;\n\tuint32_t next2comp;\n\tuint8_t gen;\n\tuint8_t rid;\n\tVmxnet3_GenericDesc *base;\n\tuint64_t basePA;\n} vmxnet3_cmd_ring_t;\n\nstatic inline void\nvmxnet3_cmd_ring_adv_next2fill(struct vmxnet3_cmd_ring *ring)\n{\n\tring->next2fill++;\n\tif (unlikely(ring->next2fill == ring->size)) {\n\t\tring->next2fill = 0;\n\t\tring->gen = (uint8_t)(ring->gen ^ 1);\n\t}\n}\n\nstatic inline void\nvmxnet3_cmd_ring_adv_next2comp(struct vmxnet3_cmd_ring *ring)\n{\n\tVMXNET3_INC_RING_IDX_ONLY(ring->next2comp, ring->size);\n}\n\nstatic inline uint32_t\nvmxnet3_cmd_ring_desc_avail(struct vmxnet3_cmd_ring *ring)\n{\n\treturn (ring->next2comp > ring->next2fill ? 0 : ring->size) +\n\t\t ring->next2comp - ring->next2fill - 1;\n}\n\nstatic inline bool\nvmxnet3_cmd_ring_desc_empty(struct vmxnet3_cmd_ring *ring)\n{\n\treturn (ring->next2comp == ring->next2fill);\n}\n\ntypedef struct vmxnet3_comp_ring {\n\tuint32_t\t size;\n\tuint32_t\t next2proc;\n\tuint8_t\t\t gen;\n\tuint8_t\t\t intr_idx;\n\tVmxnet3_GenericDesc *base;\n\tuint64_t\t basePA;\n} vmxnet3_comp_ring_t;\n\nstruct vmxnet3_data_ring {\n\tstruct Vmxnet3_TxDataDesc *base;\n\tuint32_t size;\n\tuint64_t basePA;\n};\n\nstatic inline void\nvmxnet3_comp_ring_adv_next2proc(struct vmxnet3_comp_ring *ring)\n{\n\tring->next2proc++;\n\tif (unlikely(ring->next2proc == ring->size)) {\n\t\tring->next2proc = 0;\n\t\tring->gen = (uint8_t)(ring->gen ^ 1);\n\t}\n}\n\nstruct vmxnet3_txq_stats {\n\tuint64_t\tdrop_total; /* # of pkts dropped by the driver,\n\t\t\t\t * the counters below track droppings due to\n\t\t\t\t * different reasons\n\t\t\t\t */\n\tuint64_t\tdrop_too_many_segs;\n\tuint64_t\tdrop_tso;\n\tuint64_t\ttx_ring_full;\n};\n\ntypedef struct vmxnet3_tx_ctx {\n\tint ip_type;\n\tbool is_vlan;\n\tbool is_cso;\n\n\tuint16_t evl_tag;\t\t/* only valid when is_vlan == TRUE */\n\tuint32_t eth_hdr_size; /* only valid for pkts requesting tso or csum\n\t\t\t\t\t\t\t * offloading */\n\tuint32_t ip_hdr_size;\n\tuint32_t l4_hdr_size;\n} vmxnet3_tx_ctx_t;\n\ntypedef struct vmxnet3_tx_queue {\n\tstruct vmxnet3_hw *hw;\n\tstruct vmxnet3_cmd_ring cmd_ring;\n\tstruct vmxnet3_comp_ring comp_ring;\n\tstruct vmxnet3_data_ring data_ring;\n\tuint32_t qid;\n\tstruct Vmxnet3_TxQueueDesc *shared;\n\tstruct vmxnet3_txq_stats stats;\n\tbool stopped;\n\tuint16_t queue_id; /**< Device TX queue index. */\n\tuint8_t port_id; /**< Device port identifier. */\n} vmxnet3_tx_queue_t;\n\n\nstruct vmxnet3_rxq_stats {\n\tuint64_t drop_total;\n\tuint64_t drop_err;\n\tuint64_t drop_fcs;\n\tuint64_t rx_buf_alloc_failure;\n};\n\ntypedef struct vmxnet3_rx_queue {\n\tstruct rte_mempool *mp;\n\tstruct vmxnet3_hw *hw;\n\tstruct vmxnet3_cmd_ring cmd_ring[VMXNET3_RX_CMDRING_SIZE];\n\tstruct vmxnet3_comp_ring comp_ring;\n\tuint32_t qid1;\n\tuint32_t qid2;\n\tVmxnet3_RxQueueDesc *shared;\n\tstruct vmxnet3_rxq_stats stats;\n\tbool stopped;\n\tuint16_t queue_id; /**< Device RX queue index. */\n\tuint8_t port_id; /**< Device port identifier. */\n} vmxnet3_rx_queue_t;\n\n#endif /* _VMXNET3_RING_H_ */\n" }, { "path": "drivers/net/vmxnet3/vmxnet3_rxtx.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"base/vmxnet3_defs.h\"\n#include \"vmxnet3_ring.h\"\n\n#include \"vmxnet3_logs.h\"\n#include \"vmxnet3_ethdev.h\"\n\n#define RTE_MBUF_DATA_DMA_ADDR(mb) \\\n\t(uint64_t) ((mb)->buf_physaddr + (mb)->data_off)\n\n#define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \\\n\t(uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)\n\nstatic const uint32_t rxprod_reg[2] = {VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2};\n\nstatic int vmxnet3_post_rx_bufs(vmxnet3_rx_queue_t*, uint8_t);\nstatic void vmxnet3_tq_tx_complete(vmxnet3_tx_queue_t *);\n#ifdef RTE_LIBRTE_VMXNET3_DEBUG_DRIVER_NOT_USED\nstatic void vmxnet3_rxq_dump(struct vmxnet3_rx_queue *);\nstatic void vmxnet3_txq_dump(struct vmxnet3_tx_queue *);\n#endif\n\nstatic struct rte_mbuf *\nrte_rxmbuf_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\n\tm = __rte_mbuf_raw_alloc(mp);\n\t__rte_mbuf_sanity_check_raw(m, 0);\n\treturn m;\n}\n\n#ifdef RTE_LIBRTE_VMXNET3_DEBUG_DRIVER_NOT_USED\nstatic void\nvmxnet3_rxq_dump(struct vmxnet3_rx_queue *rxq)\n{\n\tuint32_t avail = 0;\n\n\tif (rxq == NULL)\n\t\treturn;\n\n\tPMD_RX_LOG(DEBUG,\n\t\t \"RXQ: cmd0 base : 0x%p cmd1 base : 0x%p comp ring base : 0x%p.\",\n\t\t rxq->cmd_ring[0].base, rxq->cmd_ring[1].base, rxq->comp_ring.base);\n\tPMD_RX_LOG(DEBUG,\n\t\t \"RXQ: cmd0 basePA : 0x%lx cmd1 basePA : 0x%lx comp ring basePA : 0x%lx.\",\n\t\t (unsigned long)rxq->cmd_ring[0].basePA,\n\t\t (unsigned long)rxq->cmd_ring[1].basePA,\n\t\t (unsigned long)rxq->comp_ring.basePA);\n\n\tavail = vmxnet3_cmd_ring_desc_avail(&rxq->cmd_ring[0]);\n\tPMD_RX_LOG(DEBUG,\n\t\t \"RXQ:cmd0: size=%u; free=%u; next2proc=%u; queued=%u\",\n\t\t (uint32_t)rxq->cmd_ring[0].size, avail,\n\t\t rxq->comp_ring.next2proc,\n\t\t rxq->cmd_ring[0].size - avail);\n\n\tavail = vmxnet3_cmd_ring_desc_avail(&rxq->cmd_ring[1]);\n\tPMD_RX_LOG(DEBUG, \"RXQ:cmd1 size=%u; free=%u; next2proc=%u; queued=%u\",\n\t\t (uint32_t)rxq->cmd_ring[1].size, avail, rxq->comp_ring.next2proc,\n\t\t rxq->cmd_ring[1].size - avail);\n\n}\n\nstatic void\nvmxnet3_txq_dump(struct vmxnet3_tx_queue *txq)\n{\n\tuint32_t avail = 0;\n\n\tif (txq == NULL)\n\t\treturn;\n\n\tPMD_TX_LOG(DEBUG, \"TXQ: cmd base : 0x%p comp ring base : 0x%p data ring base : 0x%p.\",\n\t\t txq->cmd_ring.base, txq->comp_ring.base, txq->data_ring.base);\n\tPMD_TX_LOG(DEBUG, \"TXQ: cmd basePA : 0x%lx comp ring basePA : 0x%lx data ring basePA : 0x%lx.\",\n\t\t (unsigned long)txq->cmd_ring.basePA,\n\t\t (unsigned long)txq->comp_ring.basePA,\n\t\t (unsigned long)txq->data_ring.basePA);\n\n\tavail = vmxnet3_cmd_ring_desc_avail(&txq->cmd_ring);\n\tPMD_TX_LOG(DEBUG, \"TXQ: size=%u; free=%u; next2proc=%u; queued=%u\",\n\t\t (uint32_t)txq->cmd_ring.size, avail,\n\t\t txq->comp_ring.next2proc, txq->cmd_ring.size - avail);\n}\n#endif\n\nstatic void\nvmxnet3_cmd_ring_release_mbufs(vmxnet3_cmd_ring_t *ring)\n{\n\twhile (ring->next2comp != ring->next2fill) {\n\t\t/* No need to worry about tx desc ownership, device is quiesced by now. */\n\t\tvmxnet3_buf_info_t *buf_info = ring->buf_info + ring->next2comp;\n\n\t\tif (buf_info->m) {\n\t\t\trte_pktmbuf_free(buf_info->m);\n\t\t\tbuf_info->m = NULL;\n\t\t\tbuf_info->bufPA = 0;\n\t\t\tbuf_info->len = 0;\n\t\t}\n\t\tvmxnet3_cmd_ring_adv_next2comp(ring);\n\t}\n}\n\nstatic void\nvmxnet3_cmd_ring_release(vmxnet3_cmd_ring_t *ring)\n{\n\tvmxnet3_cmd_ring_release_mbufs(ring);\n\trte_free(ring->buf_info);\n\tring->buf_info = NULL;\n}\n\n\nvoid\nvmxnet3_dev_tx_queue_release(void *txq)\n{\n\tvmxnet3_tx_queue_t *tq = txq;\n\n\tif (tq != NULL) {\n\t\t/* Release the cmd_ring */\n\t\tvmxnet3_cmd_ring_release(&tq->cmd_ring);\n\t}\n}\n\nvoid\nvmxnet3_dev_rx_queue_release(void *rxq)\n{\n\tint i;\n\tvmxnet3_rx_queue_t *rq = rxq;\n\n\tif (rq != NULL) {\n\t\t/* Release both the cmd_rings */\n\t\tfor (i = 0; i < VMXNET3_RX_CMDRING_SIZE; i++)\n\t\t\tvmxnet3_cmd_ring_release(&rq->cmd_ring[i]);\n\t}\n}\n\nstatic void\nvmxnet3_dev_tx_queue_reset(void *txq)\n{\n\tvmxnet3_tx_queue_t *tq = txq;\n\tstruct vmxnet3_cmd_ring *ring = &tq->cmd_ring;\n\tstruct vmxnet3_comp_ring *comp_ring = &tq->comp_ring;\n\tstruct vmxnet3_data_ring *data_ring = &tq->data_ring;\n\tint size;\n\n\tif (tq != NULL) {\n\t\t/* Release the cmd_ring mbufs */\n\t\tvmxnet3_cmd_ring_release_mbufs(&tq->cmd_ring);\n\t}\n\n\t/* Tx vmxnet rings structure initialization*/\n\tring->next2fill = 0;\n\tring->next2comp = 0;\n\tring->gen = VMXNET3_INIT_GEN;\n\tcomp_ring->next2proc = 0;\n\tcomp_ring->gen = VMXNET3_INIT_GEN;\n\n\tsize = sizeof(struct Vmxnet3_TxDesc) * ring->size;\n\tsize += sizeof(struct Vmxnet3_TxCompDesc) * comp_ring->size;\n\tsize += sizeof(struct Vmxnet3_TxDataDesc) * data_ring->size;\n\n\tmemset(ring->base, 0, size);\n}\n\nstatic void\nvmxnet3_dev_rx_queue_reset(void *rxq)\n{\n\tint i;\n\tvmxnet3_rx_queue_t *rq = rxq;\n\tstruct vmxnet3_cmd_ring *ring0, *ring1;\n\tstruct vmxnet3_comp_ring *comp_ring;\n\tint size;\n\n\tif (rq != NULL) {\n\t\t/* Release both the cmd_rings mbufs */\n\t\tfor (i = 0; i < VMXNET3_RX_CMDRING_SIZE; i++)\n\t\t\tvmxnet3_cmd_ring_release_mbufs(&rq->cmd_ring[i]);\n\t}\n\n\tring0 = &rq->cmd_ring[0];\n\tring1 = &rq->cmd_ring[1];\n\tcomp_ring = &rq->comp_ring;\n\n\t/* Rx vmxnet rings structure initialization */\n\tring0->next2fill = 0;\n\tring1->next2fill = 0;\n\tring0->next2comp = 0;\n\tring1->next2comp = 0;\n\tring0->gen = VMXNET3_INIT_GEN;\n\tring1->gen = VMXNET3_INIT_GEN;\n\tcomp_ring->next2proc = 0;\n\tcomp_ring->gen = VMXNET3_INIT_GEN;\n\n\tsize = sizeof(struct Vmxnet3_RxDesc) * (ring0->size + ring1->size);\n\tsize += sizeof(struct Vmxnet3_RxCompDesc) * comp_ring->size;\n\n\tmemset(ring0->base, 0, size);\n}\n\nvoid\nvmxnet3_dev_clear_queues(struct rte_eth_dev *dev)\n{\n\tunsigned i;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tstruct vmxnet3_tx_queue *txq = dev->data->tx_queues[i];\n\n\t\tif (txq != NULL) {\n\t\t\ttxq->stopped = TRUE;\n\t\t\tvmxnet3_dev_tx_queue_reset(txq);\n\t\t}\n\t}\n\n\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n\t\tstruct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i];\n\n\t\tif (rxq != NULL) {\n\t\t\trxq->stopped = TRUE;\n\t\t\tvmxnet3_dev_rx_queue_reset(rxq);\n\t\t}\n\t}\n}\n\nstatic void\nvmxnet3_tq_tx_complete(vmxnet3_tx_queue_t *txq)\n{\n\tint completed = 0;\n\tstruct rte_mbuf *mbuf;\n\tvmxnet3_comp_ring_t *comp_ring = &txq->comp_ring;\n\tstruct Vmxnet3_TxCompDesc *tcd = (struct Vmxnet3_TxCompDesc *)\n\t\t(comp_ring->base + comp_ring->next2proc);\n\n\twhile (tcd->gen == comp_ring->gen) {\n\t\t/* Release cmd_ring descriptor and free mbuf */\n\t\tVMXNET3_ASSERT(txq->cmd_ring.base[tcd->txdIdx].txd.eop == 1);\n\t\twhile (txq->cmd_ring.next2comp != tcd->txdIdx) {\n\t\t\tmbuf = txq->cmd_ring.buf_info[txq->cmd_ring.next2comp].m;\n\t\t\ttxq->cmd_ring.buf_info[txq->cmd_ring.next2comp].m = NULL;\n\t\t\trte_pktmbuf_free_seg(mbuf);\n\n\t\t\t/* Mark the txd for which tcd was generated as completed */\n\t\t\tvmxnet3_cmd_ring_adv_next2comp(&txq->cmd_ring);\n\t\t\tcompleted++;\n\t\t}\n\n\t\tvmxnet3_comp_ring_adv_next2proc(comp_ring);\n\t\ttcd = (struct Vmxnet3_TxCompDesc *)(comp_ring->base +\n\t\t\t\t\t\t comp_ring->next2proc);\n\t}\n\n\tPMD_TX_LOG(DEBUG, \"Processed %d tx comps & command descs.\", completed);\n}\n\nuint16_t\nvmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n\t\t uint16_t nb_pkts)\n{\n\tuint16_t nb_tx;\n\tvmxnet3_tx_queue_t *txq = tx_queue;\n\tstruct vmxnet3_hw *hw = txq->hw;\n\n\tif (unlikely(txq->stopped)) {\n\t\tPMD_TX_LOG(DEBUG, \"Tx queue is stopped.\");\n\t\treturn 0;\n\t}\n\n\t/* Free up the comp_descriptors aggressively */\n\tvmxnet3_tq_tx_complete(txq);\n\n\tnb_tx = 0;\n\twhile (nb_tx < nb_pkts) {\n\t\tVmxnet3_GenericDesc *gdesc;\n\t\tvmxnet3_buf_info_t *tbi;\n\t\tuint32_t first2fill, avail, dw2;\n\t\tstruct rte_mbuf *txm = tx_pkts[nb_tx];\n\t\tstruct rte_mbuf *m_seg = txm;\n\n\t\t/* Is this packet execessively fragmented, then drop */\n\t\tif (unlikely(txm->nb_segs > VMXNET3_MAX_TXD_PER_PKT)) {\n\t\t\t++txq->stats.drop_too_many_segs;\n\t\t\t++txq->stats.drop_total;\n\t\t\trte_pktmbuf_free(txm);\n\t\t\t++nb_tx;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Is command ring full? */\n\t\tavail = vmxnet3_cmd_ring_desc_avail(&txq->cmd_ring);\n\t\tif (txm->nb_segs > avail) {\n\t\t\t++txq->stats.tx_ring_full;\n\t\t\tbreak;\n\t\t}\n\n\t\t/* use the previous gen bit for the SOP desc */\n\t\tdw2 = (txq->cmd_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;\n\t\tfirst2fill = txq->cmd_ring.next2fill;\n\t\tdo {\n\t\t\t/* Remember the transmit buffer for cleanup */\n\t\t\ttbi = txq->cmd_ring.buf_info + txq->cmd_ring.next2fill;\n\t\t\ttbi->m = m_seg;\n\n\t\t\t/* NB: the following assumes that VMXNET3 maximum\n\t\t\t transmit buffer size (16K) is greater than\n\t\t\t maximum sizeof mbuf segment size. */\n\t\t\tgdesc = txq->cmd_ring.base + txq->cmd_ring.next2fill;\n\t\t\tgdesc->txd.addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);\n\t\t\tgdesc->dword[2] = dw2 | m_seg->data_len;\n\t\t\tgdesc->dword[3] = 0;\n\n\t\t\t/* move to the next2fill descriptor */\n\t\t\tvmxnet3_cmd_ring_adv_next2fill(&txq->cmd_ring);\n\n\t\t\t/* use the right gen for non-SOP desc */\n\t\t\tdw2 = txq->cmd_ring.gen << VMXNET3_TXD_GEN_SHIFT;\n\t\t} while ((m_seg = m_seg->next) != NULL);\n\n\t\t/* Update the EOP descriptor */\n\t\tgdesc->dword[3] |= VMXNET3_TXD_EOP | VMXNET3_TXD_CQ;\n\n\t\t/* Add VLAN tag if present */\n\t\tgdesc = txq->cmd_ring.base + first2fill;\n\t\tif (txm->ol_flags & PKT_TX_VLAN_PKT) {\n\t\t\tgdesc->txd.ti = 1;\n\t\t\tgdesc->txd.tci = txm->vlan_tci;\n\t\t}\n\n\t\t/* TODO: Add transmit checksum offload here */\n\n\t\t/* flip the GEN bit on the SOP */\n\t\trte_compiler_barrier();\n\t\tgdesc->dword[2] ^= VMXNET3_TXD_GEN;\n\n\t\ttxq->shared->ctrl.txNumDeferred++;\n\t\tnb_tx++;\n\t}\n\n\tPMD_TX_LOG(DEBUG, \"vmxnet3 txThreshold: %u\", txq->shared->ctrl.txThreshold);\n\n\tif (txq->shared->ctrl.txNumDeferred >= txq->shared->ctrl.txThreshold) {\n\n\t\ttxq->shared->ctrl.txNumDeferred = 0;\n\t\t/* Notify vSwitch that packets are available. */\n\t\tVMXNET3_WRITE_BAR0_REG(hw, (VMXNET3_REG_TXPROD + txq->queue_id * VMXNET3_REG_ALIGN),\n\t\t\t\t txq->cmd_ring.next2fill);\n\t}\n\n\treturn nb_tx;\n}\n\n/*\n * Allocates mbufs and clusters. Post rx descriptors with buffer details\n * so that device can receive packets in those buffers.\n *\tRing layout:\n * Among the two rings, 1st ring contains buffers of type 0 and type1.\n * bufs_per_pkt is set such that for non-LRO cases all the buffers required\n * by a frame will fit in 1st ring (1st buf of type0 and rest of type1).\n * 2nd ring contains buffers of type 1 alone. Second ring mostly be used\n * only for LRO.\n *\n */\nstatic int\nvmxnet3_post_rx_bufs(vmxnet3_rx_queue_t *rxq, uint8_t ring_id)\n{\n\tint err = 0;\n\tuint32_t i = 0, val = 0;\n\tstruct vmxnet3_cmd_ring *ring = &rxq->cmd_ring[ring_id];\n\n\tif (ring_id == 0) {\n\t\t/* Usually: One HEAD type buf per packet\n\t\t * val = (ring->next2fill % rxq->hw->bufs_per_pkt) ?\n\t\t * VMXNET3_RXD_BTYPE_BODY : VMXNET3_RXD_BTYPE_HEAD;\n\t\t */\n\n\t\t/* We use single packet buffer so all heads here */\n\t\tval = VMXNET3_RXD_BTYPE_HEAD;\n\t} else {\n\t\t/* All BODY type buffers for 2nd ring */\n\t\tval = VMXNET3_RXD_BTYPE_BODY;\n\t}\n\n\twhile (vmxnet3_cmd_ring_desc_avail(ring) > 0) {\n\t\tstruct Vmxnet3_RxDesc *rxd;\n\t\tstruct rte_mbuf *mbuf;\n\t\tvmxnet3_buf_info_t *buf_info = &ring->buf_info[ring->next2fill];\n\n\t\trxd = (struct Vmxnet3_RxDesc *)(ring->base + ring->next2fill);\n\n\t\t/* Allocate blank mbuf for the current Rx Descriptor */\n\t\tmbuf = rte_rxmbuf_alloc(rxq->mp);\n\t\tif (unlikely(mbuf == NULL)) {\n\t\t\tPMD_RX_LOG(ERR, \"Error allocating mbuf in %s\", __func__);\n\t\t\trxq->stats.rx_buf_alloc_failure++;\n\t\t\terr = ENOMEM;\n\t\t\tbreak;\n\t\t}\n\n\t\t/*\n\t\t * Load mbuf pointer into buf_info[ring_size]\n\t\t * buf_info structure is equivalent to cookie for virtio-virtqueue\n\t\t */\n\t\tbuf_info->m = mbuf;\n\t\tbuf_info->len = (uint16_t)(mbuf->buf_len -\n\t\t\t\t\t RTE_PKTMBUF_HEADROOM);\n\t\tbuf_info->bufPA = RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf);\n\n\t\t/* Load Rx Descriptor with the buffer's GPA */\n\t\trxd->addr = buf_info->bufPA;\n\n\t\t/* After this point rxd->addr MUST not be NULL */\n\t\trxd->btype = val;\n\t\trxd->len = buf_info->len;\n\t\t/* Flip gen bit at the end to change ownership */\n\t\trxd->gen = ring->gen;\n\n\t\tvmxnet3_cmd_ring_adv_next2fill(ring);\n\t\ti++;\n\t}\n\n\t/* Return error only if no buffers are posted at present */\n\tif (vmxnet3_cmd_ring_desc_avail(ring) >= (ring->size - 1))\n\t\treturn -err;\n\telse\n\t\treturn i;\n}\n\n\n/* Receive side checksum and other offloads */\nstatic void\nvmxnet3_rx_offload(const Vmxnet3_RxCompDesc *rcd, struct rte_mbuf *rxm)\n{\n\t/* Check for hardware stripped VLAN tag */\n\tif (rcd->ts) {\n\t\trxm->ol_flags |= PKT_RX_VLAN_PKT;\n\t\trxm->vlan_tci = rte_le_to_cpu_16((uint16_t)rcd->tci);\n\t}\n\n\t/* Check for RSS */\n\tif (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE) {\n\t\trxm->ol_flags |= PKT_RX_RSS_HASH;\n\t\trxm->hash.rss = rcd->rssHash;\n\t}\n\n\t/* Check packet type, checksum errors, etc. Only support IPv4 for now. */\n\tif (rcd->v4) {\n\t\tstruct ether_hdr *eth = rte_pktmbuf_mtod(rxm, struct ether_hdr *);\n\t\tstruct ipv4_hdr *ip = (struct ipv4_hdr *)(eth + 1);\n\n\t\tif (((ip->version_ihl & 0xf) << 2) > (int)sizeof(struct ipv4_hdr))\n#ifdef RTE_NEXT_ABI\n\t\t\trxm->packet_type = RTE_PTYPE_L3_IPV4_EXT;\n#else\n\t\t\trxm->ol_flags |= PKT_RX_IPV4_HDR_EXT;\n#endif\n\t\telse\n#ifdef RTE_NEXT_ABI\n\t\t\trxm->packet_type = RTE_PTYPE_L3_IPV4;\n#else\n\t\t\trxm->ol_flags |= PKT_RX_IPV4_HDR;\n#endif\n\n\t\tif (!rcd->cnc) {\n\t\t\tif (!rcd->ipc)\n\t\t\t\trxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;\n\n\t\t\tif ((rcd->tcp || rcd->udp) && !rcd->tuc)\n\t\t\t\trxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;\n\t\t}\n\t}\n}\n\n/*\n * Process the Rx Completion Ring of given vmxnet3_rx_queue\n * for nb_pkts burst and return the number of packets received\n */\nuint16_t\nvmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n{\n\tuint16_t nb_rx;\n\tuint32_t nb_rxd, idx;\n\tuint8_t ring_idx;\n\tvmxnet3_rx_queue_t *rxq;\n\tVmxnet3_RxCompDesc *rcd;\n\tvmxnet3_buf_info_t *rbi;\n\tVmxnet3_RxDesc *rxd;\n\tstruct rte_mbuf *rxm = NULL;\n\tstruct vmxnet3_hw *hw;\n\n\tnb_rx = 0;\n\tring_idx = 0;\n\tnb_rxd = 0;\n\tidx = 0;\n\n\trxq = rx_queue;\n\thw = rxq->hw;\n\n\trcd = &rxq->comp_ring.base[rxq->comp_ring.next2proc].rcd;\n\n\tif (unlikely(rxq->stopped)) {\n\t\tPMD_RX_LOG(DEBUG, \"Rx queue is stopped.\");\n\t\treturn 0;\n\t}\n\n\twhile (rcd->gen == rxq->comp_ring.gen) {\n\t\tif (nb_rx >= nb_pkts)\n\t\t\tbreak;\n\n\t\tidx = rcd->rxdIdx;\n\t\tring_idx = (uint8_t)((rcd->rqID == rxq->qid1) ? 0 : 1);\n\t\trxd = (Vmxnet3_RxDesc *)rxq->cmd_ring[ring_idx].base + idx;\n\t\trbi = rxq->cmd_ring[ring_idx].buf_info + idx;\n\n\t\tif (unlikely(rcd->sop != 1 || rcd->eop != 1)) {\n\t\t\trte_pktmbuf_free_seg(rbi->m);\n\t\t\tPMD_RX_LOG(DEBUG, \"Packet spread across multiple buffers\\n)\");\n\t\t\tgoto rcd_done;\n\t\t}\n\n\t\tPMD_RX_LOG(DEBUG, \"rxd idx: %d ring idx: %d.\", idx, ring_idx);\n\n\t\tVMXNET3_ASSERT(rcd->len <= rxd->len);\n\t\tVMXNET3_ASSERT(rbi->m);\n\n\t\tif (unlikely(rcd->len == 0)) {\n\t\t\tPMD_RX_LOG(DEBUG, \"Rx buf was skipped. rxring[%d][%d]\\n)\",\n\t\t\t\t ring_idx, idx);\n\t\t\tVMXNET3_ASSERT(rcd->sop && rcd->eop);\n\t\t\trte_pktmbuf_free_seg(rbi->m);\n\t\t\tgoto rcd_done;\n\t\t}\n\n\t\t/* Assuming a packet is coming in a single packet buffer */\n\t\tif (unlikely(rxd->btype != VMXNET3_RXD_BTYPE_HEAD)) {\n\t\t\tPMD_RX_LOG(DEBUG,\n\t\t\t\t \"Alert : Misbehaving device, incorrect \"\n\t\t\t\t \" buffer type used. iPacket dropped.\");\n\t\t\trte_pktmbuf_free_seg(rbi->m);\n\t\t\tgoto rcd_done;\n\t\t}\n\t\tVMXNET3_ASSERT(rxd->btype == VMXNET3_RXD_BTYPE_HEAD);\n\n\t\t/* Get the packet buffer pointer from buf_info */\n\t\trxm = rbi->m;\n\n\t\t/* Clear descriptor associated buf_info to be reused */\n\t\trbi->m = NULL;\n\t\trbi->bufPA = 0;\n\n\t\t/* Update the index that we received a packet */\n\t\trxq->cmd_ring[ring_idx].next2comp = idx;\n\n\t\t/* For RCD with EOP set, check if there is frame error */\n\t\tif (unlikely(rcd->err)) {\n\t\t\trxq->stats.drop_total++;\n\t\t\trxq->stats.drop_err++;\n\n\t\t\tif (!rcd->fcs) {\n\t\t\t\trxq->stats.drop_fcs++;\n\t\t\t\tPMD_RX_LOG(ERR, \"Recv packet dropped due to frame err.\");\n\t\t\t}\n\t\t\tPMD_RX_LOG(ERR, \"Error in received packet rcd#:%d rxd:%d\",\n\t\t\t\t (int)(rcd - (struct Vmxnet3_RxCompDesc *)\n\t\t\t\t\t rxq->comp_ring.base), rcd->rxdIdx);\n\t\t\trte_pktmbuf_free_seg(rxm);\n\t\t\tgoto rcd_done;\n\t\t}\n\n\n\t\t/* Initialize newly received packet buffer */\n\t\trxm->port = rxq->port_id;\n\t\trxm->nb_segs = 1;\n\t\trxm->next = NULL;\n\t\trxm->pkt_len = (uint16_t)rcd->len;\n\t\trxm->data_len = (uint16_t)rcd->len;\n\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n\t\trxm->ol_flags = 0;\n\t\trxm->vlan_tci = 0;\n\n\t\tvmxnet3_rx_offload(rcd, rxm);\n\n\t\trx_pkts[nb_rx++] = rxm;\nrcd_done:\n\t\trxq->cmd_ring[ring_idx].next2comp = idx;\n\t\tVMXNET3_INC_RING_IDX_ONLY(rxq->cmd_ring[ring_idx].next2comp, rxq->cmd_ring[ring_idx].size);\n\n\t\t/* It's time to allocate some new buf and renew descriptors */\n\t\tvmxnet3_post_rx_bufs(rxq, ring_idx);\n\t\tif (unlikely(rxq->shared->ctrl.updateRxProd)) {\n\t\t\tVMXNET3_WRITE_BAR0_REG(hw, rxprod_reg[ring_idx] + (rxq->queue_id * VMXNET3_REG_ALIGN),\n\t\t\t\t\t rxq->cmd_ring[ring_idx].next2fill);\n\t\t}\n\n\t\t/* Advance to the next descriptor in comp_ring */\n\t\tvmxnet3_comp_ring_adv_next2proc(&rxq->comp_ring);\n\n\t\trcd = &rxq->comp_ring.base[rxq->comp_ring.next2proc].rcd;\n\t\tnb_rxd++;\n\t\tif (nb_rxd > rxq->cmd_ring[0].size) {\n\t\t\tPMD_RX_LOG(ERR,\n\t\t\t\t \"Used up quota of receiving packets,\"\n\t\t\t\t \" relinquish control.\");\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn nb_rx;\n}\n\n/*\n * Create memzone for device rings. malloc can't be used as the physical address is\n * needed. If the memzone is already created, then this function returns a ptr\n * to the old one.\n */\nstatic const struct rte_memzone *\nring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,\n\t\t uint16_t queue_id, uint32_t ring_size, int socket_id)\n{\n\tchar z_name[RTE_MEMZONE_NAMESIZE];\n\tconst struct rte_memzone *mz;\n\n\tsnprintf(z_name, sizeof(z_name), \"%s_%s_%d_%d\",\n\t\t\tdev->driver->pci_drv.name, ring_name,\n\t\t\tdev->data->port_id, queue_id);\n\n\tmz = rte_memzone_lookup(z_name);\n\tif (mz)\n\t\treturn mz;\n\n\treturn rte_memzone_reserve_aligned(z_name, ring_size,\n\t\t\tsocket_id, 0, VMXNET3_RING_BA_ALIGN);\n}\n\nint\nvmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev,\n\t\t\t uint16_t queue_idx,\n\t\t\t uint16_t nb_desc,\n\t\t\t unsigned int socket_id,\n\t\t\t __attribute__((unused)) const struct rte_eth_txconf *tx_conf)\n{\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\tconst struct rte_memzone *mz;\n\tstruct vmxnet3_tx_queue *txq;\n\tstruct vmxnet3_cmd_ring *ring;\n\tstruct vmxnet3_comp_ring *comp_ring;\n\tstruct vmxnet3_data_ring *data_ring;\n\tint size;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tif ((tx_conf->txq_flags & ETH_TXQ_FLAGS_NOXSUMS) !=\n\t ETH_TXQ_FLAGS_NOXSUMS) {\n\t\tPMD_INIT_LOG(ERR, \"TX no support for checksum offload yet\");\n\t\treturn -EINVAL;\n\t}\n\n\ttxq = rte_zmalloc(\"ethdev_tx_queue\", sizeof(struct vmxnet3_tx_queue), RTE_CACHE_LINE_SIZE);\n\tif (txq == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Can not allocate tx queue structure\");\n\t\treturn -ENOMEM;\n\t}\n\n\ttxq->queue_id = queue_idx;\n\ttxq->port_id = dev->data->port_id;\n\ttxq->shared = &hw->tqd_start[queue_idx];\n\ttxq->hw = hw;\n\ttxq->qid = queue_idx;\n\ttxq->stopped = TRUE;\n\n\tring = &txq->cmd_ring;\n\tcomp_ring = &txq->comp_ring;\n\tdata_ring = &txq->data_ring;\n\n\t/* Tx vmxnet ring length should be between 512-4096 */\n\tif (nb_desc < VMXNET3_DEF_TX_RING_SIZE) {\n\t\tPMD_INIT_LOG(ERR, \"VMXNET3 Tx Ring Size Min: %u\",\n\t\t\t VMXNET3_DEF_TX_RING_SIZE);\n\t\treturn -EINVAL;\n\t} else if (nb_desc > VMXNET3_TX_RING_MAX_SIZE) {\n\t\tPMD_INIT_LOG(ERR, \"VMXNET3 Tx Ring Size Max: %u\",\n\t\t\t VMXNET3_TX_RING_MAX_SIZE);\n\t\treturn -EINVAL;\n\t} else {\n\t\tring->size = nb_desc;\n\t\tring->size &= ~VMXNET3_RING_SIZE_MASK;\n\t}\n\tcomp_ring->size = data_ring->size = ring->size;\n\n\t/* Tx vmxnet rings structure initialization*/\n\tring->next2fill = 0;\n\tring->next2comp = 0;\n\tring->gen = VMXNET3_INIT_GEN;\n\tcomp_ring->next2proc = 0;\n\tcomp_ring->gen = VMXNET3_INIT_GEN;\n\n\tsize = sizeof(struct Vmxnet3_TxDesc) * ring->size;\n\tsize += sizeof(struct Vmxnet3_TxCompDesc) * comp_ring->size;\n\tsize += sizeof(struct Vmxnet3_TxDataDesc) * data_ring->size;\n\n\tmz = ring_dma_zone_reserve(dev, \"txdesc\", queue_idx, size, socket_id);\n\tif (mz == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"ERROR: Creating queue descriptors zone\");\n\t\treturn -ENOMEM;\n\t}\n\tmemset(mz->addr, 0, mz->len);\n\n\t/* cmd_ring initialization */\n\tring->base = mz->addr;\n\tring->basePA = mz->phys_addr;\n\n\t/* comp_ring initialization */\n\tcomp_ring->base = ring->base + ring->size;\n\tcomp_ring->basePA = ring->basePA +\n\t\t(sizeof(struct Vmxnet3_TxDesc) * ring->size);\n\n\t/* data_ring initialization */\n\tdata_ring->base = (Vmxnet3_TxDataDesc *)(comp_ring->base + comp_ring->size);\n\tdata_ring->basePA = comp_ring->basePA +\n\t\t\t(sizeof(struct Vmxnet3_TxCompDesc) * comp_ring->size);\n\n\t/* cmd_ring0 buf_info allocation */\n\tring->buf_info = rte_zmalloc(\"tx_ring_buf_info\",\n\t\t\t\t ring->size * sizeof(vmxnet3_buf_info_t), RTE_CACHE_LINE_SIZE);\n\tif (ring->buf_info == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"ERROR: Creating tx_buf_info structure\");\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Update the data portion with txq */\n\tdev->data->tx_queues[queue_idx] = txq;\n\n\treturn 0;\n}\n\nint\nvmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev,\n\t\t\t uint16_t queue_idx,\n\t\t\t uint16_t nb_desc,\n\t\t\t unsigned int socket_id,\n\t\t\t __attribute__((unused)) const struct rte_eth_rxconf *rx_conf,\n\t\t\t struct rte_mempool *mp)\n{\n\tconst struct rte_memzone *mz;\n\tstruct vmxnet3_rx_queue *rxq;\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\tstruct vmxnet3_cmd_ring *ring0, *ring1, *ring;\n\tstruct vmxnet3_comp_ring *comp_ring;\n\tint size;\n\tuint8_t i;\n\tchar mem_name[32];\n\tuint16_t buf_size;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tbuf_size = rte_pktmbuf_data_room_size(mp) -\n\t\tRTE_PKTMBUF_HEADROOM;\n\n\tif (dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) {\n\t\tPMD_INIT_LOG(ERR, \"buf_size = %u, max_pkt_len = %u, \"\n\t\t\t \"VMXNET3 don't support scatter packets yet\",\n\t\t\t buf_size, dev->data->dev_conf.rxmode.max_rx_pkt_len);\n\t\treturn -EINVAL;\n\t}\n\n\trxq = rte_zmalloc(\"ethdev_rx_queue\", sizeof(struct vmxnet3_rx_queue), RTE_CACHE_LINE_SIZE);\n\tif (rxq == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"Can not allocate rx queue structure\");\n\t\treturn -ENOMEM;\n\t}\n\n\trxq->mp = mp;\n\trxq->queue_id = queue_idx;\n\trxq->port_id = dev->data->port_id;\n\trxq->shared = &hw->rqd_start[queue_idx];\n\trxq->hw = hw;\n\trxq->qid1 = queue_idx;\n\trxq->qid2 = queue_idx + hw->num_rx_queues;\n\trxq->stopped = TRUE;\n\n\tring0 = &rxq->cmd_ring[0];\n\tring1 = &rxq->cmd_ring[1];\n\tcomp_ring = &rxq->comp_ring;\n\n\t/* Rx vmxnet rings length should be between 256-4096 */\n\tif (nb_desc < VMXNET3_DEF_RX_RING_SIZE) {\n\t\tPMD_INIT_LOG(ERR, \"VMXNET3 Rx Ring Size Min: 256\");\n\t\treturn -EINVAL;\n\t} else if (nb_desc > VMXNET3_RX_RING_MAX_SIZE) {\n\t\tPMD_INIT_LOG(ERR, \"VMXNET3 Rx Ring Size Max: 4096\");\n\t\treturn -EINVAL;\n\t} else {\n\t\tring0->size = nb_desc;\n\t\tring0->size &= ~VMXNET3_RING_SIZE_MASK;\n\t\tring1->size = ring0->size;\n\t}\n\n\tcomp_ring->size = ring0->size + ring1->size;\n\n\t/* Rx vmxnet rings structure initialization */\n\tring0->next2fill = 0;\n\tring1->next2fill = 0;\n\tring0->next2comp = 0;\n\tring1->next2comp = 0;\n\tring0->gen = VMXNET3_INIT_GEN;\n\tring1->gen = VMXNET3_INIT_GEN;\n\tcomp_ring->next2proc = 0;\n\tcomp_ring->gen = VMXNET3_INIT_GEN;\n\n\tsize = sizeof(struct Vmxnet3_RxDesc) * (ring0->size + ring1->size);\n\tsize += sizeof(struct Vmxnet3_RxCompDesc) * comp_ring->size;\n\n\tmz = ring_dma_zone_reserve(dev, \"rxdesc\", queue_idx, size, socket_id);\n\tif (mz == NULL) {\n\t\tPMD_INIT_LOG(ERR, \"ERROR: Creating queue descriptors zone\");\n\t\treturn -ENOMEM;\n\t}\n\tmemset(mz->addr, 0, mz->len);\n\n\t/* cmd_ring0 initialization */\n\tring0->base = mz->addr;\n\tring0->basePA = mz->phys_addr;\n\n\t/* cmd_ring1 initialization */\n\tring1->base = ring0->base + ring0->size;\n\tring1->basePA = ring0->basePA + sizeof(struct Vmxnet3_RxDesc) * ring0->size;\n\n\t/* comp_ring initialization */\n\tcomp_ring->base = ring1->base + ring1->size;\n\tcomp_ring->basePA = ring1->basePA + sizeof(struct Vmxnet3_RxDesc) *\n\t\tring1->size;\n\n\t/* cmd_ring0-cmd_ring1 buf_info allocation */\n\tfor (i = 0; i < VMXNET3_RX_CMDRING_SIZE; i++) {\n\n\t\tring = &rxq->cmd_ring[i];\n\t\tring->rid = i;\n\t\tsnprintf(mem_name, sizeof(mem_name), \"rx_ring_%d_buf_info\", i);\n\n\t\tring->buf_info = rte_zmalloc(mem_name, ring->size * sizeof(vmxnet3_buf_info_t), RTE_CACHE_LINE_SIZE);\n\t\tif (ring->buf_info == NULL) {\n\t\t\tPMD_INIT_LOG(ERR, \"ERROR: Creating rx_buf_info structure\");\n\t\t\treturn -ENOMEM;\n\t\t}\n\t}\n\n\t/* Update the data portion with rxq */\n\tdev->data->rx_queues[queue_idx] = rxq;\n\n\treturn 0;\n}\n\n/*\n * Initializes Receive Unit\n * Load mbufs in rx queue in advance\n */\nint\nvmxnet3_dev_rxtx_init(struct rte_eth_dev *dev)\n{\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\n\tint i, ret;\n\tuint8_t j;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tfor (i = 0; i < hw->num_rx_queues; i++) {\n\t\tvmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];\n\n\t\tfor (j = 0; j < VMXNET3_RX_CMDRING_SIZE; j++) {\n\t\t\t/* Passing 0 as alloc_num will allocate full ring */\n\t\t\tret = vmxnet3_post_rx_bufs(rxq, j);\n\t\t\tif (ret <= 0) {\n\t\t\t\tPMD_INIT_LOG(ERR, \"ERROR: Posting Rxq: %d buffers ring: %d\", i, j);\n\t\t\t\treturn -ret;\n\t\t\t}\n\t\t\t/* Updating device with the index:next2fill to fill the mbufs for coming packets */\n\t\t\tif (unlikely(rxq->shared->ctrl.updateRxProd)) {\n\t\t\t\tVMXNET3_WRITE_BAR0_REG(hw, rxprod_reg[j] + (rxq->queue_id * VMXNET3_REG_ALIGN),\n\t\t\t\t\t\t rxq->cmd_ring[j].next2fill);\n\t\t\t}\n\t\t}\n\t\trxq->stopped = FALSE;\n\t}\n\n\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n\t\tstruct vmxnet3_tx_queue *txq = dev->data->tx_queues[i];\n\n\t\ttxq->stopped = FALSE;\n\t}\n\n\treturn 0;\n}\n\nstatic uint8_t rss_intel_key[40] = {\n\t0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,\n\t0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,\n\t0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,\n\t0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,\n\t0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,\n};\n\n/*\n * Configure RSS feature\n */\nint\nvmxnet3_rss_configure(struct rte_eth_dev *dev)\n{\n\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n\tstruct VMXNET3_RSSConf *dev_rss_conf;\n\tstruct rte_eth_rss_conf *port_rss_conf;\n\tuint64_t rss_hf;\n\tuint8_t i, j;\n\n\tPMD_INIT_FUNC_TRACE();\n\n\tdev_rss_conf = hw->rss_conf;\n\tport_rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;\n\n\t/* loading hashFunc */\n\tdev_rss_conf->hashFunc = VMXNET3_RSS_HASH_FUNC_TOEPLITZ;\n\t/* loading hashKeySize */\n\tdev_rss_conf->hashKeySize = VMXNET3_RSS_MAX_KEY_SIZE;\n\t/* loading indTableSize : Must not exceed VMXNET3_RSS_MAX_IND_TABLE_SIZE (128)*/\n\tdev_rss_conf->indTableSize = (uint16_t)(hw->num_rx_queues * 4);\n\n\tif (port_rss_conf->rss_key == NULL) {\n\t\t/* Default hash key */\n\t\tport_rss_conf->rss_key = rss_intel_key;\n\t}\n\n\t/* loading hashKey */\n\tmemcpy(&dev_rss_conf->hashKey[0], port_rss_conf->rss_key, dev_rss_conf->hashKeySize);\n\n\t/* loading indTable */\n\tfor (i = 0, j = 0; i < dev_rss_conf->indTableSize; i++, j++) {\n\t\tif (j == dev->data->nb_rx_queues)\n\t\t\tj = 0;\n\t\tdev_rss_conf->indTable[i] = j;\n\t}\n\n\t/* loading hashType */\n\tdev_rss_conf->hashType = 0;\n\trss_hf = port_rss_conf->rss_hf & VMXNET3_RSS_OFFLOAD_ALL;\n\tif (rss_hf & ETH_RSS_IPV4)\n\t\tdev_rss_conf->hashType |= VMXNET3_RSS_HASH_TYPE_IPV4;\n\tif (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)\n\t\tdev_rss_conf->hashType |= VMXNET3_RSS_HASH_TYPE_TCP_IPV4;\n\tif (rss_hf & ETH_RSS_IPV6)\n\t\tdev_rss_conf->hashType |= VMXNET3_RSS_HASH_TYPE_IPV6;\n\tif (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)\n\t\tdev_rss_conf->hashType |= VMXNET3_RSS_HASH_TYPE_TCP_IPV6;\n\n\treturn VMXNET3_SUCCESS;\n}\n" }, { "path": "drivers/net/xenvirt/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pmd_xenvirt.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_eth_xenvirt_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_PMD_XENVIRT) += rte_eth_xenvirt.c rte_mempool_gntalloc.c rte_xen_lib.c\n\n#\n# Export include files\n#\nSYMLINK-y-include += rte_eth_xenvirt.h\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_XENVIRT) += lib/librte_eal lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_XENVIRT) += lib/librte_mempool lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_XENVIRT) += lib/librte_net\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PMD_XENVIRT) += lib/librte_cmdline\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "drivers/net/xenvirt/rte_eth_xenvirt.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#if __XEN_LATEST_INTERFACE_VERSION__ < 0x00040200\n#include \n#else\n#include \n#endif\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_xen_lib.h\"\n#include \"virtqueue.h\"\n#include \"rte_eth_xenvirt.h\"\n\n#define VQ_DESC_NUM 256\n#define VIRTIO_MBUF_BURST_SZ 64\n\n/* virtio_idx is increased after new device is created.*/\nstatic int virtio_idx = 0;\n\nstatic const char *drivername = \"xen dummy virtio PMD\";\n\nstatic struct rte_eth_link pmd_link = {\n\t\t.link_speed = 10000,\n\t\t.link_duplex = ETH_LINK_FULL_DUPLEX,\n\t\t.link_status = 0\n};\n\nstatic inline struct rte_mbuf *\nrte_rxmbuf_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\n\tm = __rte_mbuf_raw_alloc(mp);\n\t__rte_mbuf_sanity_check_raw(m, 0);\n\n\treturn m;\n}\n\n\nstatic uint16_t\neth_xenvirt_rx(void *q, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n{\n\tstruct virtqueue *rxvq = q;\n\tstruct rte_mbuf *rxm, *new_mbuf;\n\tuint16_t nb_used, num;\n\tuint32_t len[VIRTIO_MBUF_BURST_SZ];\n\tuint32_t i;\n\tstruct pmd_internals *pi = rxvq->internals;\n\n\tnb_used = VIRTQUEUE_NUSED(rxvq);\n\n\trte_compiler_barrier(); /* rmb */\n\tnum = (uint16_t)(likely(nb_used <= nb_pkts) ? nb_used : nb_pkts);\n\tnum = (uint16_t)(likely(num <= VIRTIO_MBUF_BURST_SZ) ? num : VIRTIO_MBUF_BURST_SZ);\n\tif (unlikely(num == 0)) return 0;\n\n\tnum = virtqueue_dequeue_burst(rxvq, rx_pkts, len, num);\n\tPMD_RX_LOG(DEBUG, \"used:%d dequeue:%d\\n\", nb_used, num);\n\tfor (i = 0; i < num ; i ++) {\n\t\trxm = rx_pkts[i];\n\t\tPMD_RX_LOG(DEBUG, \"packet len:%d\\n\", len[i]);\n\t\trxm->next = NULL;\n\t\trxm->data_off = RTE_PKTMBUF_HEADROOM;\n\t\trxm->data_len = (uint16_t)(len[i] - sizeof(struct virtio_net_hdr));\n\t\trxm->nb_segs = 1;\n\t\trxm->port = pi->port_id;\n\t\trxm->pkt_len = (uint32_t)(len[i] - sizeof(struct virtio_net_hdr));\n\t}\n\t/* allocate new mbuf for the used descriptor */\n\twhile (likely(!virtqueue_full(rxvq))) {\n\t\tnew_mbuf = rte_rxmbuf_alloc(rxvq->mpool);\n\t\tif (unlikely(new_mbuf == NULL)) {\n\t\t\tbreak;\n\t\t}\n\t\tif (unlikely(virtqueue_enqueue_recv_refill(rxvq, new_mbuf))) {\n\t\t\trte_pktmbuf_free_seg(new_mbuf);\n\t\t\tbreak;\n\t\t}\n\t}\n\tpi->eth_stats.ipackets += num;\n\treturn num;\n}\n\nstatic uint16_t\neth_xenvirt_tx(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n{\n\tstruct virtqueue *txvq = tx_queue;\n\tstruct rte_mbuf *txm;\n\tuint16_t nb_used, nb_tx, num, i;\n\tint error;\n\tuint32_t len[VIRTIO_MBUF_BURST_SZ];\n\tstruct rte_mbuf *snd_pkts[VIRTIO_MBUF_BURST_SZ];\n\tstruct pmd_internals *pi = txvq->internals;\n\n\tnb_tx = 0;\n\n\tif (unlikely(nb_pkts == 0))\n\t\treturn 0;\n\n\tPMD_TX_LOG(DEBUG, \"%d packets to xmit\", nb_pkts);\n\tnb_used = VIRTQUEUE_NUSED(txvq);\n\n\trte_compiler_barrier(); /* rmb */\n\n\tnum = (uint16_t)(likely(nb_used <= VIRTIO_MBUF_BURST_SZ) ? nb_used : VIRTIO_MBUF_BURST_SZ);\n\tnum = virtqueue_dequeue_burst(txvq, snd_pkts, len, num);\n\n\tfor (i = 0; i < num ; i ++) {\n\t\t/* mergable not supported, one segment only */\n\t\trte_pktmbuf_free_seg(snd_pkts[i]);\n\t}\n\n\twhile (nb_tx < nb_pkts) {\n\t\tif (likely(!virtqueue_full(txvq))) {\n\t\t/* TODO drop tx_pkts if it contains multiple segments */\n\t\t\ttxm = tx_pkts[nb_tx];\n\t\t\terror = virtqueue_enqueue_xmit(txvq, txm);\n\t\t\tif (unlikely(error)) {\n\t\t\t\tif (error == ENOSPC)\n\t\t\t\t\tPMD_TX_LOG(ERR, \"virtqueue_enqueue Free count = 0\\n\");\n\t\t\t\telse if (error == EMSGSIZE)\n\t\t\t\t\tPMD_TX_LOG(ERR, \"virtqueue_enqueue Free count < 1\\n\");\n\t\t\t\telse\n\t\t\t\t\tPMD_TX_LOG(ERR, \"virtqueue_enqueue error: %d\\n\", error);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tnb_tx++;\n\t\t} else {\n\t\t\tPMD_TX_LOG(ERR, \"No free tx descriptors to transmit\\n\");\n\t\t\t/* virtqueue_notify not needed in our para-virt solution */\n\t\t\tbreak;\n\t\t}\n\t}\n\tpi->eth_stats.opackets += nb_tx;\n\treturn nb_tx;\n}\n\nstatic int\neth_dev_configure(struct rte_eth_dev *dev __rte_unused)\n{\n\tRTE_LOG(ERR, PMD, \"%s\\n\", __func__);\n\treturn 0;\n}\n\n/*\n * Create a shared page between guest and host.\n * Host monitors this page if it is cleared on unmap, and then\n * do necessary clean up.\n */\nstatic void\ngntalloc_vring_flag(int vtidx)\n{\n\tchar key_str[PATH_MAX];\n\tchar val_str[PATH_MAX];\n\tuint32_t gref_tmp;\n\tvoid *ptr;\n\n\tif (grefwatch_from_alloc(&gref_tmp, &ptr)) {\n\t\tRTE_LOG(ERR, PMD, \"grefwatch_from_alloc error\\n\");\n\t\texit(0);\n\t}\n\n\t*(uint8_t *)ptr = MAP_FLAG;\n\tsnprintf(val_str, sizeof(val_str), \"%u\", gref_tmp);\n\tsnprintf(key_str, sizeof(key_str),\n\t\tDPDK_XENSTORE_PATH\"%d\"VRING_FLAG_STR, vtidx);\n\txenstore_write(key_str, val_str);\n}\n\n/*\n * Notify host this virtio device is started.\n * Host could start polling this device.\n */\nstatic void\ndev_start_notify(int vtidx)\n{\n\tchar key_str[PATH_MAX];\n\tchar val_str[PATH_MAX];\n\n\tRTE_LOG(INFO, PMD, \"%s: virtio %d is started\\n\", __func__, vtidx);\n\tgntalloc_vring_flag(vtidx);\n\n\tsnprintf(key_str, sizeof(key_str), \"%s%s%d\",\n\t\tDPDK_XENSTORE_PATH, EVENT_TYPE_START_STR,\n\t\t\tvtidx);\n\tsnprintf(val_str, sizeof(val_str), \"1\");\n\txenstore_write(key_str, val_str);\n}\n\n/*\n * Notify host this virtio device is stopped.\n * Host could stop polling this device.\n */\nstatic void\ndev_stop_notify(int vtidx)\n{\n\tRTE_SET_USED(vtidx);\n}\n\n\nstatic int\nupdate_mac_address(struct ether_addr *mac_addrs, int vtidx)\n{\n\tchar key_str[PATH_MAX];\n\tchar val_str[PATH_MAX];\n\tint rv;\n\n\tif (mac_addrs == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"%s: NULL pointer mac specified\\n\", __func__);\n\t\treturn -1;\n\t}\n\trv = snprintf(key_str, sizeof(key_str),\n\t\t\tDPDK_XENSTORE_PATH\"%d_ether_addr\", vtidx);\n\tif (rv == -1)\n\t\treturn rv;\n\trv = snprintf(val_str, sizeof(val_str), \"%02x:%02x:%02x:%02x:%02x:%02x\",\n\t\t\tmac_addrs->addr_bytes[0],\n\t\t\tmac_addrs->addr_bytes[1],\n\t\t\tmac_addrs->addr_bytes[2],\n\t\t\tmac_addrs->addr_bytes[3],\n\t\t\tmac_addrs->addr_bytes[4],\n\t\t\tmac_addrs->addr_bytes[5]);\n\tif (rv == -1)\n\t\treturn rv;\n\tif (xenstore_write(key_str, val_str))\n\t\treturn rv;\n\treturn 0;\n}\n\n\nstatic int\neth_dev_start(struct rte_eth_dev *dev)\n{\n\tstruct virtqueue *rxvq = dev->data->rx_queues[0];\n\tstruct virtqueue *txvq = dev->data->tx_queues[0];\n\tstruct rte_mbuf *m;\n\tstruct pmd_internals *pi = (struct pmd_internals *)dev->data->dev_private;\n\tint rv;\n\n\tdev->data->dev_link.link_status = 1;\n\twhile (!virtqueue_full(rxvq)) {\n\t\tm = rte_rxmbuf_alloc(rxvq->mpool);\n\t\tif (m == NULL)\n\t\t\tbreak;\n\t\t/* Enqueue allocated buffers. */\n\t\tif (virtqueue_enqueue_recv_refill(rxvq, m)) {\n\t\t\trte_pktmbuf_free_seg(m);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\trxvq->internals = pi;\n\ttxvq->internals = pi;\n\n\trv = update_mac_address(dev->data->mac_addrs, pi->virtio_idx);\n\tif (rv)\n\t\treturn -1;\n\tdev_start_notify(pi->virtio_idx);\n\n\treturn 0;\n}\n\nstatic void\neth_dev_stop(struct rte_eth_dev *dev)\n{\n\tstruct pmd_internals *pi = (struct pmd_internals *)dev->data->dev_private;\n\n\tdev->data->dev_link.link_status = 0;\n\tdev_stop_notify(pi->virtio_idx);\n}\n\n/*\n * Notify host this virtio device is closed.\n * Host could do necessary clean up to this device.\n */\nstatic void\neth_dev_close(struct rte_eth_dev *dev)\n{\n\tRTE_SET_USED(dev);\n}\n\nstatic void\neth_dev_info(struct rte_eth_dev *dev,\n\t\tstruct rte_eth_dev_info *dev_info)\n{\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\n\tRTE_SET_USED(internals);\n\tdev_info->driver_name = drivername;\n\tdev_info->max_mac_addrs = 1;\n\tdev_info->max_rx_pktlen = (uint32_t)2048;\n\tdev_info->max_rx_queues = (uint16_t)1;\n\tdev_info->max_tx_queues = (uint16_t)1;\n\tdev_info->min_rx_bufsize = 0;\n\tdev_info->pci_dev = NULL;\n}\n\nstatic void\neth_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n{\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\tif(stats)\n\t\trte_memcpy(stats, &internals->eth_stats, sizeof(*stats));\n}\n\nstatic void\neth_stats_reset(struct rte_eth_dev *dev)\n{\n\tstruct pmd_internals *internals = dev->data->dev_private;\n\t/* Reset software totals */\n\tmemset(&internals->eth_stats, 0, sizeof(internals->eth_stats));\n}\n\nstatic void\neth_queue_release(void *q __rte_unused)\n{\n}\n\nstatic int\neth_link_update(struct rte_eth_dev *dev __rte_unused,\n\t\tint wait_to_complete __rte_unused)\n{\n\treturn 0;\n}\n\n/*\n * Create shared vring between guest and host.\n * Memory is allocated through grant alloc driver, so it is not physical continuous.\n */\nstatic void *\ngntalloc_vring_create(int queue_type, uint32_t size, int vtidx)\n{\n\tchar key_str[PATH_MAX] = {0};\n\tchar val_str[PATH_MAX] = {0};\n\tvoid *va = NULL;\n\tint pg_size;\n\tuint32_t pg_num;\n\tuint32_t *gref_arr = NULL;\n\tphys_addr_t *pa_arr = NULL;\n\tuint64_t start_index;\n\tint rv;\n\n\tpg_size = getpagesize();\n\tsize = RTE_ALIGN_CEIL(size, pg_size);\n\tpg_num = size / pg_size;\n\n\tgref_arr = calloc(pg_num, sizeof(gref_arr[0]));\n\tpa_arr = calloc(pg_num, sizeof(pa_arr[0]));\n\n\tif (gref_arr == NULL || pa_arr == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"%s: calloc failed\\n\", __func__);\n\t\tgoto out;\n\t}\n\n\tva = gntalloc(size, gref_arr, &start_index);\n\tif (va == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"%s: gntalloc failed\\n\", __func__);\n\t\tgoto out;\n\t}\n\n\tif (get_phys_map(va, pa_arr, pg_num, pg_size))\n\t\tgoto out;\n\n\t/* write in xenstore gref and pfn for each page of vring */\n\tif (grant_node_create(pg_num, gref_arr, pa_arr, val_str, sizeof(val_str))) {\n\t\tgntfree(va, size, start_index);\n\t\tva = NULL;\n\t\tgoto out;\n\t}\n\n\tif (queue_type == VTNET_RQ)\n\t\trv = snprintf(key_str, sizeof(key_str), DPDK_XENSTORE_PATH\"%d\"RXVRING_XENSTORE_STR, vtidx);\n\telse\n\t\trv = snprintf(key_str, sizeof(key_str), DPDK_XENSTORE_PATH\"%d\"TXVRING_XENSTORE_STR, vtidx);\n\tif (rv == -1 || xenstore_write(key_str, val_str) == -1) {\n\t\tgntfree(va, size, start_index);\n\t\tva = NULL;\n\t}\nout:\n\tif (pa_arr)\n\t\tfree(pa_arr);\n\tif (gref_arr)\n\t\tfree(gref_arr);\n\n\treturn va;\n}\n\n\n\nstatic struct virtqueue *\nvirtio_queue_setup(struct rte_eth_dev *dev, int queue_type)\n{\n\tstruct virtqueue *vq = NULL;\n\tuint16_t vq_size = VQ_DESC_NUM;\n\tint i = 0;\n\tchar vq_name[VIRTQUEUE_MAX_NAME_SZ];\n\tsize_t size;\n\tstruct vring *vr;\n\n\t/* Allocate memory for virtqueue. */\n\tif (queue_type == VTNET_RQ) {\n\t\tsnprintf(vq_name, sizeof(vq_name), \"port%d_rvq\",\n\t\t\t\tdev->data->port_id);\n\t\tvq = rte_zmalloc(vq_name, sizeof(struct virtqueue) +\n\t\t\tvq_size * sizeof(struct vq_desc_extra), RTE_CACHE_LINE_SIZE);\n\t\tif (vq == NULL) {\n\t\t\tRTE_LOG(ERR, PMD, \"%s: unabled to allocate virtqueue\\n\", __func__);\n\t\t\treturn NULL;\n\t\t}\n\t\tmemcpy(vq->vq_name, vq_name, sizeof(vq->vq_name));\n\t} else if(queue_type == VTNET_TQ) {\n\t\tsnprintf(vq_name, sizeof(vq_name), \"port%d_tvq\",\n\t\t\tdev->data->port_id);\n\t\tvq = rte_zmalloc(vq_name, sizeof(struct virtqueue) +\n\t\t\tvq_size * sizeof(struct vq_desc_extra), RTE_CACHE_LINE_SIZE);\n\t\tif (vq == NULL) {\n\t\t\tRTE_LOG(ERR, PMD, \"%s: unabled to allocate virtqueue\\n\", __func__);\n\t\t\treturn NULL;\n\t\t}\n\t\tmemcpy(vq->vq_name, vq_name, sizeof(vq->vq_name));\n\t}\n\n\tmemcpy(vq->vq_name, vq_name, sizeof(vq->vq_name));\n\n\tvq->vq_alignment = VIRTIO_PCI_VRING_ALIGN;\n\tvq->vq_nentries = vq_size;\n\tvq->vq_free_cnt = vq_size;\n\t/* Calcuate vring size according to virtio spec */\n\tsize = vring_size(vq_size, VIRTIO_PCI_VRING_ALIGN);\n\tvq->vq_ring_size = RTE_ALIGN_CEIL(size, VIRTIO_PCI_VRING_ALIGN);\n\t/* Allocate memory for virtio vring through gntalloc driver*/\n\tvq->vq_ring_virt_mem = gntalloc_vring_create(queue_type, vq->vq_ring_size,\n\t\t((struct pmd_internals *)dev->data->dev_private)->virtio_idx);\n\tmemset(vq->vq_ring_virt_mem, 0, vq->vq_ring_size);\n\tvr = &vq->vq_ring;\n\tvring_init(vr, vq_size, vq->vq_ring_virt_mem, vq->vq_alignment);\n\t/*\n\t * Locally maintained last consumed index, this idex trails\n\t * vq_ring.used->idx.\n\t */\n\tvq->vq_used_cons_idx = 0;\n\tvq->vq_desc_head_idx = 0;\n\tvq->vq_free_cnt = vq->vq_nentries;\n\tmemset(vq->vq_descx, 0, sizeof(struct vq_desc_extra) * vq->vq_nentries);\n\n\t/* Chain all the descriptors in the ring with an END */\n\tfor (i = 0; i < vq_size - 1; i++)\n\t\tvr->desc[i].next = (uint16_t)(i + 1);\n\tvr->desc[i].next = VQ_RING_DESC_CHAIN_END;\n\n\treturn vq;\n}\n\nstatic int\neth_rx_queue_setup(struct rte_eth_dev *dev,uint16_t rx_queue_id,\n\t\t\t\tuint16_t nb_rx_desc __rte_unused,\n\t\t\t\tunsigned int socket_id __rte_unused,\n\t\t\t\tconst struct rte_eth_rxconf *rx_conf __rte_unused,\n\t\t\t\tstruct rte_mempool *mb_pool)\n{\n\tstruct virtqueue *vq;\n\tvq = dev->data->rx_queues[rx_queue_id] = virtio_queue_setup(dev, VTNET_RQ);\n\tvq->mpool = mb_pool;\n\treturn 0;\n}\n\nstatic int\neth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n\t\t\t\tuint16_t nb_tx_desc __rte_unused,\n\t\t\t\tunsigned int socket_id __rte_unused,\n\t\t\t\tconst struct rte_eth_txconf *tx_conf __rte_unused)\n{\n\tdev->data->tx_queues[tx_queue_id] = virtio_queue_setup(dev, VTNET_TQ);\n\treturn 0;\n}\n\n\n\nstatic const struct eth_dev_ops ops = {\n\t.dev_start = eth_dev_start,\n\t.dev_stop = eth_dev_stop,\n\t.dev_close = eth_dev_close,\n\t.dev_configure = eth_dev_configure,\n\t.dev_infos_get = eth_dev_info,\n\t.rx_queue_setup = eth_rx_queue_setup,\n\t.tx_queue_setup = eth_tx_queue_setup,\n\t.rx_queue_release = eth_queue_release,\n\t.tx_queue_release = eth_queue_release,\n\t.link_update = eth_link_update,\n\t.stats_get = eth_stats_get,\n\t.stats_reset = eth_stats_reset,\n};\n\n\nstatic int\nrte_eth_xenvirt_parse_args(struct xenvirt_dict *dict,\n\t\t\tconst char *name, const char *params)\n{\n\tint i;\n\tchar *pairs[RTE_ETH_XENVIRT_MAX_ARGS];\n\tint num_of_pairs;\n\tchar *pair[2];\n\tchar *args;\n\tint ret = -1;\n\n\tif (params == NULL)\n\t\treturn 0;\n\n\targs = rte_zmalloc(NULL, strlen(params) + 1, RTE_CACHE_LINE_SIZE);\n\tif (args == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"Couldn't parse %s device \\n\", name);\n\t\treturn -1;\n\t}\n\trte_memcpy(args, params, strlen(params));\n\n\tnum_of_pairs = rte_strsplit(args, strnlen(args, MAX_ARG_STRLEN),\n\t\t\t\t\tpairs,\n\t\t\t\t\tRTE_ETH_XENVIRT_MAX_ARGS ,\n\t\t\t\t\tRTE_ETH_XENVIRT_PAIRS_DELIM);\n\n\tfor (i = 0; i < num_of_pairs; i++) {\n\t\tpair[0] = NULL;\n\t\tpair[1] = NULL;\n\t\trte_strsplit(pairs[i], strnlen(pairs[i], MAX_ARG_STRLEN),\n\t\t\t\t\tpair, 2,\n\t\t\t\t\tRTE_ETH_XENVIRT_KEY_VALUE_DELIM);\n\n\t\tif (pair[0] == NULL || pair[1] == NULL || pair[0][0] == 0\n\t\t\t|| pair[1][0] == 0) {\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\"Couldn't parse %s device,\"\n\t\t\t\t\"wrong key or value \\n\", name);\n\t\t\tgoto err;\n\t\t}\n\n\t\tif (!strncmp(pair[0], RTE_ETH_XENVIRT_MAC_PARAM,\n\t\t\t\tsizeof(RTE_ETH_XENVIRT_MAC_PARAM))) {\n\t\t\tif (cmdline_parse_etheraddr(NULL,\n\t\t\t\t\t\t pair[1],\n\t\t\t\t\t\t &dict->addr,\n\t\t\t\t\t\t sizeof(dict->addr)) < 0) {\n\t\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\t\"Invalid %s device ether address\\n\",\n\t\t\t\t\tname);\n\t\t\t\tgoto err;\n\t\t\t}\n\n\t\t\tdict->addr_valid = 1;\n\t\t}\n\t}\n\n\tret = 0;\nerr:\n\trte_free(args);\n\treturn ret;\n}\n\nenum dev_action {\n\tDEV_CREATE,\n\tDEV_ATTACH\n};\n\n\nstatic int\neth_dev_xenvirt_create(const char *name, const char *params,\n\t\tconst unsigned numa_node,\n enum dev_action action)\n{\n\tstruct rte_eth_dev_data *data = NULL;\n\tstruct rte_pci_device *pci_dev = NULL;\n\tstruct pmd_internals *internals = NULL;\n\tstruct rte_eth_dev *eth_dev = NULL;\n\tstruct xenvirt_dict dict;\n\tbzero(&dict, sizeof(struct xenvirt_dict));\n\n\tRTE_LOG(INFO, PMD, \"Creating virtio rings backed ethdev on numa socket %u\\n\",\n\t\t\tnuma_node);\n\tRTE_SET_USED(action);\n\n\tif (rte_eth_xenvirt_parse_args(&dict, name, params) < 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: Failed to parse ethdev parameters\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\t/* now do all data allocation - for eth_dev structure, dummy pci driver\n\t * and internal (private) data\n\t */\n\tdata = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node);\n\tif (data == NULL)\n\t\tgoto err;\n\n\tpci_dev = rte_zmalloc_socket(name, sizeof(*pci_dev), 0, numa_node);\n\tif (pci_dev == NULL)\n\t\tgoto err;\n\n\tinternals = rte_zmalloc_socket(name, sizeof(*internals), 0, numa_node);\n\tif (internals == NULL)\n\t\tgoto err;\n\n\t/* reserve an ethdev entry */\n\teth_dev = rte_eth_dev_allocate(name, RTE_ETH_DEV_VIRTUAL);\n\tif (eth_dev == NULL)\n\t\tgoto err;\n\n\tpci_dev->numa_node = numa_node;\n\n\tdata->dev_private = internals;\n\tdata->port_id = eth_dev->data->port_id;\n\tdata->nb_rx_queues = (uint16_t)1;\n\tdata->nb_tx_queues = (uint16_t)1;\n\tdata->dev_link = pmd_link;\n\tdata->mac_addrs = rte_zmalloc(\"xen_virtio\", ETHER_ADDR_LEN, 0);\n\n\tif(dict.addr_valid)\n\t\tmemcpy(&data->mac_addrs->addr_bytes, &dict.addr, sizeof(struct ether_addr));\n\telse\n\t\teth_random_addr(&data->mac_addrs->addr_bytes[0]);\n\n\teth_dev->data = data;\n\teth_dev->dev_ops = &ops;\n\teth_dev->pci_dev = pci_dev;\n\n\teth_dev->rx_pkt_burst = eth_xenvirt_rx;\n\teth_dev->tx_pkt_burst = eth_xenvirt_tx;\n\n\tinternals->virtio_idx = virtio_idx++;\n\tinternals->port_id = eth_dev->data->port_id;\n\n\treturn 0;\n\nerr:\n\trte_free(data);\n\trte_free(pci_dev);\n\trte_free(internals);\n\n\treturn -1;\n}\n\n\n/*TODO: Support multiple process model */\nstatic int\nrte_pmd_xenvirt_devinit(const char *name, const char *params)\n{\n\tif (virtio_idx == 0) {\n\t\tif (xenstore_init() != 0) {\n\t\t\tRTE_LOG(ERR, PMD, \"%s: xenstore init failed\\n\", __func__);\n\t\t\treturn -1;\n\t\t}\n\t\tif (gntalloc_open() != 0) {\n\t\t\tRTE_LOG(ERR, PMD, \"%s: grant init failed\\n\", __func__);\n\t\t\treturn -1;\n\t\t}\n\t}\n\teth_dev_xenvirt_create(name, params, rte_socket_id(), DEV_CREATE);\n\treturn 0;\n}\n\nstatic struct rte_driver pmd_xenvirt_drv = {\n\t.name = \"eth_xenvirt\",\n\t.type = PMD_VDEV,\n\t.init = rte_pmd_xenvirt_devinit,\n};\n\nPMD_REGISTER_DRIVER(pmd_xenvirt_drv);\n" }, { "path": "drivers/net/xenvirt/rte_eth_xenvirt.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ETH_XENVIRT_H_\n#define _RTE_ETH_XENVIRT_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n\n/**\n * Creates mempool for xen virtio PMD.\n * This function uses memzone_reserve to allocate memory for meta data,\n * and uses grant alloc driver to allocate memory for data area.\n * The input parameters are exactly the same as rte_mempool_create.\n */\nstruct rte_mempool *\nrte_mempool_gntalloc_create(const char *name, unsigned elt_num, unsigned elt_size,\n\t\t unsigned cache_size, unsigned private_data_size,\n\t\t rte_mempool_ctor_t *mp_init, void *mp_init_arg,\n\t\t rte_mempool_obj_ctor_t *obj_init, void *obj_init_arg,\n\t\t int socket_id, unsigned flags);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "drivers/net/xenvirt/rte_mempool_gntalloc.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"rte_xen_lib.h\"\n#include \"rte_eth_xenvirt.h\"\n\nstruct _gntarr {\n\tuint32_t gref;\n\tphys_addr_t pa;\n\tuint64_t index;\n\tvoid *va;\n};\n\nstruct _mempool_gntalloc_info {\n\tstruct rte_mempool *mp;\n\tuint32_t pg_num;\n\tuint32_t *gref_arr;\n\tphys_addr_t *pa_arr;\n\tvoid *va;\n\tuint32_t mempool_idx;\n\tuint64_t start_index;\n};\n\n\nstatic rte_atomic32_t global_xenvirt_mempool_idx = RTE_ATOMIC32_INIT(-1);\n\nstatic int\ncompare(const void *p1, const void *p2)\n{\n\treturn ((const struct _gntarr *)p1)->pa - ((const struct _gntarr *)p2)->pa;\n}\n\n\nstatic struct _mempool_gntalloc_info\n_create_mempool(const char *name, unsigned elt_num, unsigned elt_size,\n\t\t unsigned cache_size, unsigned private_data_size,\n\t\t rte_mempool_ctor_t *mp_init, void *mp_init_arg,\n\t\t rte_mempool_obj_ctor_t *obj_init, void *obj_init_arg,\n\t\t int socket_id, unsigned flags)\n{\n\tstruct _mempool_gntalloc_info mgi;\n\tstruct rte_mempool *mp = NULL;\n\tstruct rte_mempool_objsz objsz;\n\tuint32_t pg_num, rpg_num, pg_shift, pg_sz;\n\tchar *va, *orig_va, *uv; /* uv: from which, the pages could be freed */\n\tssize_t sz, usz; /* usz: unused size */\n\t/*\n\t * for each page allocated through xen_gntalloc driver,\n\t * gref_arr:stores grant references,\n\t * pa_arr: stores physical address,\n\t * gnt_arr: stores all meta dat\n\t */\n\tuint32_t *gref_arr = NULL;\n\tphys_addr_t *pa_arr = NULL;\n\tstruct _gntarr *gnt_arr = NULL;\n\t/* start index of the grant referances, used for dealloc*/\n\tuint64_t start_index;\n\tuint32_t i, j;\n\tint rv = 0;\n\tstruct ioctl_gntalloc_dealloc_gref arg;\n\n\tmgi.mp = NULL;\n\tva = orig_va = uv = NULL;\n\tpg_num = rpg_num = 0;\n\tsz = 0;\n\n\tpg_sz = getpagesize();\n\tif (rte_is_power_of_2(pg_sz) == 0) {\n\t\tgoto out;\n\t}\n\tpg_shift = rte_bsf32(pg_sz);\n\n\trte_mempool_calc_obj_size(elt_size, flags, &objsz);\n\tsz = rte_mempool_xmem_size(elt_num, objsz.total_size, pg_shift);\n\tpg_num = sz >> pg_shift;\n\n\tpa_arr = calloc(pg_num, sizeof(pa_arr[0]));\n\tgref_arr = calloc(pg_num, sizeof(gref_arr[0]));\n\tgnt_arr = calloc(pg_num, sizeof(gnt_arr[0]));\n\tif ((gnt_arr == NULL) || (gref_arr == NULL) || (pa_arr == NULL))\n\t\tgoto out;\n\n\t/* grant index is continuous in ascending order */\n\torig_va = gntalloc(sz, gref_arr, &start_index);\n\tif (orig_va == NULL)\n\t\tgoto out;\n\n\tget_phys_map(orig_va, pa_arr, pg_num, pg_sz);\n\tfor (i = 0; i < pg_num; i++) {\n\t\tgnt_arr[i].index = start_index + i * pg_sz;\n\t\tgnt_arr[i].gref = gref_arr[i];\n\t\tgnt_arr[i].pa = pa_arr[i];\n\t\tgnt_arr[i].va = RTE_PTR_ADD(orig_va, i * pg_sz);\n\t}\n\tqsort(gnt_arr, pg_num, sizeof(struct _gntarr), compare);\n\n\tva = get_xen_virtual(sz, pg_sz);\n\tif (va == NULL) {\n\t\tgoto out;\n\t}\n\n\t/*\n\t * map one by one, as index isn't continuous now.\n\t * pg_num VMAs, doesn't linux has a limitation on this?\n\t */\n\tfor (i = 0; i < pg_num; i++) {\n\t/* update gref_arr and pa_arr after sort */\n\t\tgref_arr[i] = gnt_arr[i].gref;\n\t\tpa_arr[i] = gnt_arr[i].pa;\n\t\tgnt_arr[i].va = mmap(va + i * pg_sz, pg_sz, PROT_READ | PROT_WRITE,\n\t\t\tMAP_SHARED | MAP_FIXED, gntalloc_fd, gnt_arr[i].index);\n\t\tif ((gnt_arr[i].va == MAP_FAILED) || (gnt_arr[i].va != (va + i * pg_sz))) {\n\t\t\tRTE_LOG(ERR, PMD, \"failed to map %d pages\\n\", i);\n\t\t\tgoto mmap_failed;\n\t\t}\n\t}\n\n\t/*\n\t * Check that allocated size is big enough to hold elt_num\n\t * objects and a calcualte how many bytes are actually required.\n\t */\n\tusz = rte_mempool_xmem_usage(va, elt_num, objsz.total_size, pa_arr, pg_num, pg_shift);\n\tif (usz < 0) {\n\t\tmp = NULL;\n\t\ti = pg_num;\n\t\tgoto mmap_failed;\n\t} else {\n\t\t/* unmap unused pages if any */\n\t\tuv = RTE_PTR_ADD(va, usz);\n\t\tif ((usz = va + sz - uv) > 0) {\n\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\"%s(%s): unmap unused %zu of %zu \"\n\t\t\t\t\"mmaped bytes @%p orig:%p\\n\",\n\t\t\t\t__func__, name, usz, sz, uv, va);\n\t\t\tmunmap(uv, usz);\n\t\t\ti = (sz - usz) / pg_sz;\n\t\t\tfor (; i < pg_num; i++) {\n\t\t\t\targ.count = 1;\n\t\t\t\targ.index = gnt_arr[i].index;\n\t\t\t\trv = ioctl(gntalloc_fd, IOCTL_GNTALLOC_DEALLOC_GREF, &arg);\n\t\t\t\tif (rv) {\n\t\t\t\t\t/* shouldn't fail here */\n\t\t\t\t\tRTE_LOG(ERR, PMD, \"va=%p pa=%p index=%p %s\\n\",\n\t\t\t\t\t\tgnt_arr[i].va,\n\t\t\t\t\t\t(void *)gnt_arr[i].pa,\n\t\t\t\t\t\t(void *)arg.index, strerror(errno));\n\t\t\t\t\trte_panic(\"gntdealloc failed when freeing pages\\n\");\n\t\t\t\t}\n\t\t\t}\n\n\t\t\trpg_num = (sz - usz) >> pg_shift;\n\t\t} else\n\t\t\trpg_num = pg_num;\n\n\t\tmp = rte_mempool_xmem_create(name, elt_num, elt_size,\n\t\t\t\tcache_size, private_data_size,\n\t\t\t\tmp_init, mp_init_arg,\n\t\t\t\tobj_init, obj_init_arg,\n\t\t\t\tsocket_id, flags, va, pa_arr, rpg_num, pg_shift);\n\n\t\tRTE_VERIFY(elt_num == mp->size);\n\t}\n\tmgi.mp = mp;\n\tmgi.pg_num = rpg_num;\n\tmgi.gref_arr = gref_arr;\n\tmgi.pa_arr = pa_arr;\n\tif (mp)\n\t\tmgi.mempool_idx = rte_atomic32_add_return(&global_xenvirt_mempool_idx, 1);\n\tmgi.start_index = start_index;\n\tmgi.va = va;\n\n\tif (mp == NULL) {\n\t\ti = pg_num;\n\t\tgoto mmap_failed;\n\t}\n\n/*\n * unmap only, without deallocate grant reference.\n * unused pages have already been unmaped,\n * unmap twice will fail, but it is safe.\n */\nmmap_failed:\n\tfor (j = 0; j < i; j++) {\n\t\tif (gnt_arr[i].va)\n\t\t\tmunmap(gnt_arr[i].va, pg_sz);\n\t}\nout:\n\tif (gnt_arr)\n\t\tfree(gnt_arr);\n\tif (orig_va)\n\t\tmunmap(orig_va, sz);\n\tif (mp == NULL) {\n\t\tif (gref_arr)\n\t\t\tfree(gref_arr);\n\t\tif (pa_arr)\n\t\t\tfree(pa_arr);\n\n\t\t/* some gref has already been de-allocated from the list in the driver,\n\t\t * so dealloc one by one, and it is safe to deallocate twice\n\t\t */\n\t\tif (orig_va) {\n\t\t\tfor (i = 0; i < pg_num; i++) {\n\t\t\t\targ.index = start_index + i * pg_sz;\n\t\t\t\trv = ioctl(gntalloc_fd, IOCTL_GNTALLOC_DEALLOC_GREF, arg);\n\t\t\t}\n\t\t}\n\t}\n\treturn mgi;\n}\n\nstruct rte_mempool *\nrte_mempool_gntalloc_create(const char *name, unsigned elt_num, unsigned elt_size,\n\t\t unsigned cache_size, unsigned private_data_size,\n\t\t rte_mempool_ctor_t *mp_init, void *mp_init_arg,\n\t\t rte_mempool_obj_ctor_t *obj_init, void *obj_init_arg,\n\t\t int socket_id, unsigned flags)\n{\n\tint rv;\n\tuint32_t i;\n\tstruct _mempool_gntalloc_info mgi;\n\tstruct ioctl_gntalloc_dealloc_gref arg;\n\tint pg_sz = getpagesize();\n\n\tmgi = _create_mempool(name, elt_num, elt_size,\n\t\t\tcache_size, private_data_size,\n\t\t\tmp_init, mp_init_arg,\n\t\t\tobj_init, obj_init_arg,\n\t\t\tsocket_id, flags);\n\tif (mgi.mp) {\n\t\trv = grant_gntalloc_mbuf_pool(mgi.mp,\n\t\t\tmgi.pg_num,\n\t\t\tmgi.gref_arr,\n\t\t\tmgi.pa_arr,\n\t\t\tmgi.mempool_idx);\n\t\tfree(mgi.gref_arr);\n\t\tfree(mgi.pa_arr);\n\t\tif (rv == 0)\n\t\t\treturn mgi.mp;\n\t\t/*\n\t\t * in _create_mempool, unused pages have already been unmapped, deallocagted\n\t\t * unmap and dealloc the remained ones here.\n\t\t */\n\t\tmunmap(mgi.va, pg_sz * mgi.pg_num);\n\t\tfor (i = 0; i < mgi.pg_num; i++) {\n\t\t\targ.index = mgi.start_index + i * pg_sz;\n\t\t\trv = ioctl(gntalloc_fd, IOCTL_GNTALLOC_DEALLOC_GREF, arg);\n\t\t}\n\t\treturn NULL;\n\t}\n\treturn NULL;\n\n\n\n}\n" }, { "path": "drivers/net/xenvirt/rte_xen_lib.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#if __XEN_LATEST_INTERFACE_VERSION__ < 0x00040200\n#include \n#else\n#include \n#endif\n#include \n\n#include \n#include \n\n#include \"rte_xen_lib.h\"\n\n/*\n * The grant node format in xenstore for vring/mpool is:\n * 0_rx_vring_gref = \"gref1#, gref2#, gref3#\"\n * 0_mempool_gref = \"gref1#, gref2#, gref3#\"\n * each gref# is a grant reference for a shared page.\n * In each shared page, we store the grant_node_item items.\n */\nstruct grant_node_item {\n\tuint32_t gref;\n\tuint32_t pfn;\n} __attribute__((packed));\n\n/* fd for xen_gntalloc driver, used to allocate grant pages*/\nint gntalloc_fd = -1;\n\n/* xenstore path for local domain, now it is '/local/domain/domid/' */\nstatic char *dompath = NULL;\n/* handle to xenstore read/write operations */\nstatic struct xs_handle *xs = NULL;\n\n/*\n * Reserve a virtual address space.\n * On success, returns the pointer. On failure, returns NULL.\n */\nvoid *\nget_xen_virtual(size_t size, size_t page_sz)\n{\n\tvoid *addr;\n\tuintptr_t aligned_addr;\n\n\taddr = mmap(NULL, size + page_sz, PROT_READ, MAP_SHARED | MAP_ANONYMOUS, -1, 0);\n\tif (addr == MAP_FAILED) {\n\t\tRTE_LOG(ERR, PMD, \"failed get a virtual area\\n\");\n\t\treturn NULL;\n\t}\n\n\taligned_addr = RTE_ALIGN_CEIL((uintptr_t)addr, page_sz);\n\taddr = (void *)(aligned_addr);\n\n\treturn addr;\n}\n\n/*\n * Get the physical address for virtual memory starting at va.\n */\nint\nget_phys_map(void *va, phys_addr_t pa[], uint32_t pg_num, uint32_t pg_sz)\n{\n\tint32_t fd, rc = 0;\n\tuint32_t i, nb;\n\toff_t ofs;\n\n\tofs = (uintptr_t)va / pg_sz * sizeof(*pa);\n\tnb = pg_num * sizeof(*pa);\n\n\tif ((fd = open(PAGEMAP_FNAME, O_RDONLY)) < 0 ||\n\t\t\t(rc = pread(fd, pa, nb, ofs)) < 0 ||\n\t\t\t(rc -= nb) != 0) {\n\t\tRTE_LOG(ERR, PMD, \"%s: failed read of %u bytes from \\'%s\\' \"\n\t\t\t\"at offset %zu, error code: %d\\n\",\n\t\t\t__func__, nb, PAGEMAP_FNAME, ofs, errno);\n\t\trc = ENOENT;\n\t}\n\n\tclose(fd);\n\tfor (i = 0; i != pg_num; i++)\n\t\tpa[i] = (pa[i] & PAGEMAP_PFN_MASK) * pg_sz;\n\n\treturn rc;\n}\n\nint\ngntalloc_open(void)\n{\n\tgntalloc_fd = open(XEN_GNTALLOC_FNAME, O_RDWR);\n\treturn (gntalloc_fd != -1) ? 0 : -1;\n}\n\nvoid\ngntalloc_close(void)\n{\n\tif (gntalloc_fd != -1)\n\t\tclose(gntalloc_fd);\n\tgntalloc_fd = -1;\n}\n\nvoid *\ngntalloc(size_t size, uint32_t *gref, uint64_t *start_index)\n{\n\tint page_size = getpagesize();\n\tuint32_t i, pg_num;\n\tvoid *va;\n\tint rv;\n\tstruct ioctl_gntalloc_alloc_gref *arg;\n\tstruct ioctl_gntalloc_dealloc_gref arg_d;\n\n\tif (size % page_size) {\n\t\tRTE_LOG(ERR, PMD, \"%s: %zu isn't multiple of page size\\n\",\n\t\t\t__func__, size);\n\t\treturn NULL;\n\t}\n\n\tpg_num = size / page_size;\n\targ = malloc(sizeof(*arg) + (pg_num - 1) * sizeof(uint32_t));\n\tif (arg == NULL)\n\t\treturn NULL;\n\targ->domid = DOM0_DOMID;\n\targ->flags = GNTALLOC_FLAG_WRITABLE;\n\targ->count = pg_num;\n\n\trv = ioctl(gntalloc_fd, IOCTL_GNTALLOC_ALLOC_GREF, arg);\n\tif (rv) {\n\t\tRTE_LOG(ERR, PMD, \"%s: ioctl error\\n\", __func__);\n\t\tfree(arg);\n\t\treturn NULL;\n\t}\n\n\tva = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, gntalloc_fd, arg->index);\n\tif (va == MAP_FAILED) {\n\t\tRTE_LOG(ERR, PMD, \"%s: mmap failed\\n\", __func__);\n\t\targ_d.count = pg_num;\n\t\targ_d.index = arg->index;\n\t\tioctl(gntalloc_fd, IOCTL_GNTALLOC_DEALLOC_GREF, arg_d);\n\t\tfree(arg);\n\t\treturn NULL;\n\t}\n\n\tif (gref) {\n\t\tfor (i = 0; i < pg_num; i++) {\n\t\t\tgref[i] = arg->gref_ids[i];\n\t\t}\n\t}\n\tif (start_index)\n\t\t*start_index = arg->index;\n\n\tfree(arg);\n\n\treturn va;\n}\n\nint\ngrefwatch_from_alloc(uint32_t *gref, void **pptr)\n{\n\tint rv;\n\tvoid *ptr;\n\tint pg_size = getpagesize();\n\tstruct ioctl_gntalloc_alloc_gref arg = {\n\t\t.domid = DOM0_DOMID,\n\t\t.flags = GNTALLOC_FLAG_WRITABLE,\n\t\t.count = 1\n\t};\n\tstruct ioctl_gntalloc_dealloc_gref arg_d;\n\tstruct ioctl_gntalloc_unmap_notify notify = {\n\t\t.action = UNMAP_NOTIFY_CLEAR_BYTE\n\t};\n\n\trv = ioctl(gntalloc_fd, IOCTL_GNTALLOC_ALLOC_GREF, &arg);\n\tif (rv) {\n\t\tRTE_LOG(ERR, PMD, \"%s: ioctl error\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\tptr = (void *)mmap(NULL, pg_size, PROT_READ|PROT_WRITE, MAP_SHARED, gntalloc_fd, arg.index);\n\targ_d.index = arg.index;\n\targ_d.count = 1;\n\tif (ptr == MAP_FAILED) {\n\t\tRTE_LOG(ERR, PMD, \"%s: mmap failed\\n\", __func__);\n\t\tioctl(gntalloc_fd, IOCTL_GNTALLOC_DEALLOC_GREF, &arg_d);\n\t\treturn -1;\n\t}\n\tif (pptr)\n\t\t*pptr = ptr;\n\tif (gref)\n\t\t*gref = arg.gref_ids[0];\n\n\tnotify.index = arg.index;\n\trv = ioctl(gntalloc_fd, IOCTL_GNTALLOC_SET_UNMAP_NOTIFY, ¬ify);\n\tif (rv) {\n\t\tRTE_LOG(ERR, PMD, \"%s: unmap notify failed\\n\", __func__);\n\t\tmunmap(ptr, pg_size);\n\t\tioctl(gntalloc_fd, IOCTL_GNTALLOC_DEALLOC_GREF, &arg_d);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nvoid\ngntfree(void *va, size_t sz, uint64_t start_index)\n{\n\tstruct ioctl_gntalloc_dealloc_gref arg_d;\n\n\tif (va && sz) {\n\t\tmunmap(va, sz);\n\t\targ_d.count = sz / getpagesize();\n\t\targ_d.index = start_index;\n\t\tioctl(gntalloc_fd, IOCTL_GNTALLOC_DEALLOC_GREF, &arg_d);\n\t}\n}\n\nstatic int\nxenstore_cleanup(void)\n{\n\tchar store_path[PATH_MAX] = {0};\n\n\tif (snprintf(store_path, sizeof(store_path),\n\t\t\"%s%s\", dompath, DPDK_XENSTORE_NODE) == -1)\n\t\treturn -1;\n\n\tif (xs_rm(xs, XBT_NULL, store_path) == false) {\n\t\tRTE_LOG(ERR, PMD, \"%s: failed cleanup node\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nint\nxenstore_init(void)\n{\n\tunsigned int len, domid;\n\tchar *buf;\n\tstatic int cleanup = 0;\n\tchar *end;\n\n\txs = xs_domain_open();\n\tif (xs == NULL) {\n\t\tRTE_LOG(ERR, PMD,\"%s: xs_domain_open failed\\n\", __func__);\n\t\treturn -1;\n\t}\n\tbuf = xs_read(xs, XBT_NULL, \"domid\", &len);\n\tif (buf == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"%s: failed read domid\\n\", __func__);\n\t\treturn -1;\n\t}\n\terrno = 0;\n\tdomid = strtoul(buf, &end, 0);\n\tif (errno != 0 || end == NULL || end == buf || domid == 0)\n\t\treturn -1;\n\n\tRTE_LOG(INFO, PMD, \"retrieved dom ID = %d\\n\", domid);\n\n\tdompath = xs_get_domain_path(xs, domid);\n\tif (dompath == NULL)\n\t\treturn -1;\n\n\txs_transaction_start(xs); /* When to stop transaction */\n\n\tif (cleanup == 0) {\n\t\tif (xenstore_cleanup())\n\t\t\treturn -1;\n\t\tcleanup = 1;\n\t}\n\n\treturn 0;\n}\n\nint\nxenstore_write(const char *key_str, const char *val_str)\n{\n\tchar grant_path[PATH_MAX];\n\tint rv, len;\n\n\tif (xs == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"%s: xenstore init failed\\n\", __func__);\n\t\treturn -1;\n\t}\n\trv = snprintf(grant_path, sizeof(grant_path), \"%s%s\", dompath, key_str);\n\tif (rv == -1) {\n\t\tRTE_LOG(ERR, PMD, \"%s: snprintf %s %s failed\\n\",\n\t\t\t__func__, dompath, key_str);\n\t\treturn -1;\n\t}\n\tlen = strnlen(val_str, PATH_MAX);\n\n\tif (xs_write(xs, XBT_NULL, grant_path, val_str, len) == false) {\n\t\tRTE_LOG(ERR, PMD, \"%s: xs_write failed\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nint\ngrant_node_create(uint32_t pg_num, uint32_t *gref_arr, phys_addr_t *pa_arr, char *val_str, size_t str_size)\n{\n\tuint64_t start_index;\n\tint pg_size;\n\tuint32_t pg_shift;\n\tvoid *ptr = NULL;\n\tuint32_t count, entries_per_pg;\n\tuint32_t i, j = 0, k = 0;;\n\tuint32_t *gref_tmp;\n\tint first = 1;\n\tchar tmp_str[PATH_MAX] = {0};\n\tint rv = -1;\n\n\tpg_size = getpagesize();\n\tif (rte_is_power_of_2(pg_size) == 0) {\n\t\treturn -1;\n\t}\n\tpg_shift = rte_bsf32(pg_size);\n\tif (pg_size % sizeof(struct grant_node_item)) {\n\t\tRTE_LOG(ERR, PMD, \"pg_size isn't a multiple of grant node item\\n\");\n\t\treturn -1;\n\t}\n\n\tentries_per_pg = pg_size / sizeof(struct grant_node_item);\n\tcount = (pg_num + entries_per_pg - 1 ) / entries_per_pg;\n\tgref_tmp = malloc(count * sizeof(uint32_t));\n\tif (gref_tmp == NULL)\n\t\treturn -1;\n\tptr = gntalloc(pg_size * count, gref_tmp, &start_index);\n\tif (ptr == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"%s: gntalloc error of %d pages\\n\", __func__, count);\n\t\tfree(gref_tmp);\n\t\treturn -1;\n\t}\n\n\twhile (j < pg_num) {\n\t\tif (first) {\n\t\t\trv = snprintf(val_str, str_size, \"%u\", gref_tmp[k]);\n\t\t\tfirst = 0;\n\t\t} else {\n\t\t\tsnprintf(tmp_str, PATH_MAX, \"%s\", val_str);\n\t\t\trv = snprintf(val_str, str_size, \"%s,%u\", tmp_str, gref_tmp[k]);\n\t\t}\n\t\tk++;\n\t\tif (rv == -1)\n\t\t\tbreak;\n\n\t\tfor (i = 0; i < entries_per_pg && j < pg_num ; i++) {\n\t\t\t((struct grant_node_item *)ptr)->gref = gref_arr[j];\n\t\t\t((struct grant_node_item *)ptr)->pfn = pa_arr[j] >> pg_shift;\n\t\t\tptr = RTE_PTR_ADD(ptr, sizeof(struct grant_node_item));\n\t\t\tj++;\n\t\t}\n\t}\n\tif (rv == -1) {\n\t\tgntfree(ptr, pg_size * count, start_index);\n\t} else\n\t\trv = 0;\n\tfree(gref_tmp);\n\treturn rv;\n}\n\n\nint\ngrant_gntalloc_mbuf_pool(struct rte_mempool *mpool, uint32_t pg_num, uint32_t *gref_arr, phys_addr_t *pa_arr, int mempool_idx)\n{\n\tchar key_str[PATH_MAX] = {0};\n\tchar val_str[PATH_MAX] = {0};\n\n\tif (grant_node_create(pg_num, gref_arr, pa_arr, val_str, sizeof(val_str))) {\n\t\treturn -1;\n\t}\n\n\tif (snprintf(key_str, sizeof(key_str),\n\t\tDPDK_XENSTORE_PATH\"%d\"MEMPOOL_XENSTORE_STR, mempool_idx) == -1)\n\t\treturn -1;\n\tif (xenstore_write(key_str, val_str) == -1)\n\t\treturn -1;\n\n\tif (snprintf(key_str, sizeof(key_str),\n\t\tDPDK_XENSTORE_PATH\"%d\"MEMPOOL_VA_XENSTORE_STR, mempool_idx) == -1)\n\t\treturn -1;\n\tif (snprintf(val_str, sizeof(val_str), \"%\"PRIxPTR, (uintptr_t)mpool->elt_va_start) == -1)\n\t\treturn -1;\n\tif (xenstore_write(key_str, val_str) == -1)\n\t\treturn -1;\n\n\treturn 0;\n}\n" }, { "path": "drivers/net/xenvirt/rte_xen_lib.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_XEN_DUMMY_PMD_H\n#define _RTE_XEN_DUMMY_PMD_H\n\n#include \n\n#include \n#include \n#include \n\n#define\tPAGEMAP_FNAME \"/proc/self/pagemap\"\n#define XEN_GNTALLOC_FNAME \"/dev/xen/gntalloc\"\n#define DPDK_XENSTORE_PATH \"/control/dpdk/\"\n#define DPDK_XENSTORE_NODE \"/control/dpdk\"\n/*format 0_mempool_gref = \"1537,1524,1533\" */\n#define MEMPOOL_XENSTORE_STR \"_mempool_gref\"\n/*format 0_mempool_va = 0x80340000 */\n#define MEMPOOL_VA_XENSTORE_STR \"_mempool_va\"\n/*format 0_rx_vring_gref = \"1537,1524,1533\" */\n#define RXVRING_XENSTORE_STR \"_rx_vring_gref\"\n/*format 0_tx_vring_gref = \"1537,1524,1533\" */\n#define TXVRING_XENSTORE_STR \"_tx_vring_gref\"\n#define VRING_FLAG_STR \"_vring_flag\"\n/*format: event_type_start_0 = 1*/\n#define EVENT_TYPE_START_STR \"event_type_start_\"\n\n#define DOM0_DOMID 0\n/*\n * the pfn (page frame number) are bits 0-54 (see pagemap.txt in linux\n * Documentation).\n */\n#define PAGEMAP_PFN_BITS\t54\n#define PAGEMAP_PFN_MASK\tRTE_LEN2MASK(PAGEMAP_PFN_BITS, phys_addr_t)\n\n#define MAP_FLAG\t0xA5\n\n#define RTE_ETH_XENVIRT_PAIRS_DELIM ';'\n#define RTE_ETH_XENVIRT_KEY_VALUE_DELIM '='\n#define RTE_ETH_XENVIRT_MAX_ARGS 1\n#define RTE_ETH_XENVIRT_MAC_PARAM \"mac\"\nstruct xenvirt_dict {\n\tuint8_t addr_valid;\n\tstruct ether_addr addr;\n};\n\nextern int gntalloc_fd;\n\nint\ngntalloc_open(void);\n\nvoid\ngntalloc_close(void);\n\nvoid *\ngntalloc(size_t sz, uint32_t *gref, uint64_t *start_index);\n\nvoid\ngntfree(void *va, size_t sz, uint64_t start_index);\n\nint\nxenstore_init(void);\n\nint\nxenstore_write(const char *key_str, const char *val_str);\n\nint\nget_phys_map(void *va, phys_addr_t pa[], uint32_t pg_num, uint32_t pg_sz);\n\nvoid *\nget_xen_virtual(size_t size, size_t page_sz);\n\nint\ngrefwatch_from_alloc(uint32_t *gref, void **pptr);\n\n\nint grant_node_create(uint32_t pg_num, uint32_t *gref_arr, phys_addr_t *pa_arr, char *val_str, size_t str_size);\n\nint\ngrant_gntalloc_mbuf_pool(struct rte_mempool *mpool, uint32_t pg_num, uint32_t *gref_arr, phys_addr_t *pa_arr, int mempool_idx);\n\n#endif\n" }, { "path": "drivers/net/xenvirt/virtio_logs.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VIRTIO_LOGS_H_\n#define _VIRTIO_LOGS_H_\n\n#include \n\n#ifdef RTE_LIBRTE_VIRTIO_DEBUG_INIT\n#define PMD_INIT_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, \" >>\")\n#else\n#define PMD_INIT_LOG(level, fmt, args...) do { } while(0)\n#define PMD_INIT_FUNC_TRACE() do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_VIRTIO_DEBUG_RX\n#define PMD_RX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s() rx: \" fmt , __func__, ## args)\n#else\n#define PMD_RX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#ifdef RTE_LIBRTE_VIRTIO_DEBUG_TX\n#define PMD_TX_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s() tx: \" fmt , __func__, ## args)\n#else\n#define PMD_TX_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n\n#ifdef RTE_LIBRTE_VIRTIO_DEBUG_DRIVER\n#define PMD_DRV_LOG(level, fmt, args...) \\\n\tRTE_LOG(level, PMD, \"%s(): \" fmt , __func__, ## args)\n#else\n#define PMD_DRV_LOG(level, fmt, args...) do { } while(0)\n#endif\n\n#endif /* _VIRTIO_LOGS_H_ */\n" }, { "path": "drivers/net/xenvirt/virtqueue.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VIRTQUEUE_H_\n#define _VIRTQUEUE_H_\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"virtio_logs.h\"\n\nstruct rte_mbuf;\n\n/* The alignment to use between consumer and producer parts of vring. */\n#define VIRTIO_PCI_VRING_ALIGN 4096\n\n/*\n * Address translatio is between gva<->hva,\n * rather than gpa<->hva in virito spec.\n */\n#define RTE_MBUF_DATA_DMA_ADDR(mb) \\\n\trte_pktmbuf_mtod(mb, uint64_t)\n\nenum { VTNET_RQ = 0, VTNET_TQ = 1, VTNET_CQ = 2 };\n\n/**\n * The maximum virtqueue size is 2^15. Use that value as the end of\n * descriptor chain terminator since it will never be a valid index\n * in the descriptor table. This is used to verify we are correctly\n * handling vq_free_cnt.\n */\n#define VQ_RING_DESC_CHAIN_END 32768\n\n#define VIRTQUEUE_MAX_NAME_SZ 32\n\nstruct pmd_internals {\n\tstruct rte_eth_stats eth_stats;\n\tint port_id;\n\tint virtio_idx;\n};\n\n\nstruct virtqueue {\n\tchar vq_name[VIRTQUEUE_MAX_NAME_SZ];\n\tstruct rte_mempool *mpool; /**< mempool for mbuf allocation */\n\tuint16_t queue_id; /**< DPDK queue index. */\n\tuint16_t vq_queue_index; /**< PCI queue index */\n\tuint8_t port_id; /**< Device port identifier. */\n\n\tvoid *vq_ring_virt_mem; /**< virtual address of vring*/\n\tint vq_alignment;\n\tint vq_ring_size;\n\n\tstruct vring vq_ring; /**< vring keeping desc, used and avail */\n\tstruct pmd_internals *internals; /**< virtio device internal info. */\n\tuint16_t vq_nentries; /**< vring desc numbers */\n\tuint16_t vq_desc_head_idx;\n\tuint16_t vq_free_cnt; /**< num of desc available */\n\tuint16_t vq_used_cons_idx; /**< Last consumed desc in used table, trails vq_ring.used->idx*/\n\n\tstruct vq_desc_extra {\n\t\tvoid *cookie;\n\t\tuint16_t ndescs;\n\t} vq_descx[0] __rte_cache_aligned;\n};\n\n\n#ifdef RTE_LIBRTE_XENVIRT_DEBUG_DUMP\n#define VIRTQUEUE_DUMP(vq) do { \\\n\tuint16_t used_idx, nused; \\\n\tused_idx = (vq)->vq_ring.used->idx; \\\n\tnused = (uint16_t)(used_idx - (vq)->vq_used_cons_idx); \\\n\tPMD_INIT_LOG(DEBUG, \\\n\t \"VQ: %s - size=%d; free=%d; used=%d; desc_head_idx=%d;\" \\\n\t \" avail.idx=%d; used_cons_idx=%d; used.idx=%d;\" \\\n\t \" avail.flags=0x%x; used.flags=0x%x\\n\", \\\n\t (vq)->vq_name, (vq)->vq_nentries, (vq)->vq_free_cnt, nused, \\\n\t (vq)->vq_desc_head_idx, (vq)->vq_ring.avail->idx, \\\n\t (vq)->vq_used_cons_idx, (vq)->vq_ring.used->idx, \\\n\t (vq)->vq_ring.avail->flags, (vq)->vq_ring.used->flags); \\\n} while (0)\n#else\n#define VIRTQUEUE_DUMP(vq) do { } while (0)\n#endif\n\n\n/**\n * Dump virtqueue internal structures, for debug purpose only.\n */\nvoid virtqueue_dump(struct virtqueue *vq);\n\n/**\n * Get all mbufs to be freed.\n */\nstruct rte_mbuf * virtqueue_detatch_unused(struct virtqueue *vq);\n\nstatic inline int __attribute__((always_inline))\nvirtqueue_full(const struct virtqueue *vq)\n{\n\treturn (vq->vq_free_cnt == 0);\n}\n\n#define VIRTQUEUE_NUSED(vq) ((uint16_t)((vq)->vq_ring.used->idx - (vq)->vq_used_cons_idx))\n\nstatic inline void __attribute__((always_inline))\nvq_ring_update_avail(struct virtqueue *vq, uint16_t desc_idx)\n{\n\tuint16_t avail_idx;\n\t/*\n\t * Place the head of the descriptor chain into the next slot and make\n\t * it usable to the host. The chain is made available now rather than\n\t * deferring to virtqueue_notify() in the hopes that if the host is\n\t * currently running on another CPU, we can keep it processing the new\n\t * descriptor.\n\t */\n\tavail_idx = (uint16_t)(vq->vq_ring.avail->idx & (vq->vq_nentries - 1));\n\tvq->vq_ring.avail->ring[avail_idx] = desc_idx;\n\trte_compiler_barrier(); /* wmb , for IA memory model barrier is enough*/\n\tvq->vq_ring.avail->idx++;\n}\n\nstatic inline void __attribute__((always_inline))\nvq_ring_free_chain(struct virtqueue *vq, uint16_t desc_idx)\n{\n\tstruct vring_desc *dp;\n\tstruct vq_desc_extra *dxp;\n\n\tdp = &vq->vq_ring.desc[desc_idx];\n\tdxp = &vq->vq_descx[desc_idx];\n\tvq->vq_free_cnt = (uint16_t)(vq->vq_free_cnt + dxp->ndescs);\n\twhile (dp->flags & VRING_DESC_F_NEXT) {\n\t\tdp = &vq->vq_ring.desc[dp->next];\n\t}\n\tdxp->ndescs = 0;\n\n\t/*\n\t * We must append the existing free chain, if any, to the end of\n\t * newly freed chain. If the virtqueue was completely used, then\n\t * head would be VQ_RING_DESC_CHAIN_END (ASSERTed above).\n\t */\n\tdp->next = vq->vq_desc_head_idx;\n\tvq->vq_desc_head_idx = desc_idx;\n}\n\nstatic inline int __attribute__((always_inline))\nvirtqueue_enqueue_recv_refill(struct virtqueue *rxvq, struct rte_mbuf *cookie)\n{\n\tconst uint16_t needed = 1;\n\tconst uint16_t head_idx = rxvq->vq_desc_head_idx;\n\tstruct vring_desc *start_dp = rxvq->vq_ring.desc;\n\tstruct vq_desc_extra *dxp;\n\n\tif (unlikely(rxvq->vq_free_cnt == 0))\n\t\treturn -ENOSPC;\n\tif (unlikely(rxvq->vq_free_cnt < needed))\n\t\treturn -EMSGSIZE;\n\tif (unlikely(head_idx >= rxvq->vq_nentries))\n\t\treturn -EFAULT;\n\n\tdxp = &rxvq->vq_descx[head_idx];\n\tdxp->cookie = (void *)cookie;\n\tdxp->ndescs = needed;\n\n\tstart_dp[head_idx].addr =\n\t\t(uint64_t) ((uint64_t)cookie->buf_addr + RTE_PKTMBUF_HEADROOM - sizeof(struct virtio_net_hdr));\n\tstart_dp[head_idx].len = cookie->buf_len - RTE_PKTMBUF_HEADROOM + sizeof(struct virtio_net_hdr);\n\tstart_dp[head_idx].flags = VRING_DESC_F_WRITE;\n\trxvq->vq_desc_head_idx = start_dp[head_idx].next;\n\trxvq->vq_free_cnt = (uint16_t)(rxvq->vq_free_cnt - needed);\n\tvq_ring_update_avail(rxvq, head_idx);\n\n\treturn 0;\n}\n\nstatic inline int __attribute__((always_inline))\nvirtqueue_enqueue_xmit(struct virtqueue *txvq, struct rte_mbuf *cookie)\n{\n\n\tconst uint16_t needed = 2;\n\tstruct vring_desc *start_dp = txvq->vq_ring.desc;\n\tuint16_t head_idx = txvq->vq_desc_head_idx;\n\tuint16_t idx = head_idx;\n\tstruct vq_desc_extra *dxp;\n\n\tif (unlikely(txvq->vq_free_cnt == 0))\n\t\treturn -ENOSPC;\n\tif (unlikely(txvq->vq_free_cnt < needed))\n\t\treturn -EMSGSIZE;\n\tif (unlikely(head_idx >= txvq->vq_nentries))\n\t\treturn -EFAULT;\n\n\tdxp = &txvq->vq_descx[idx];\n\tdxp->cookie = (void *)cookie;\n\tdxp->ndescs = needed;\n\n\tstart_dp = txvq->vq_ring.desc;\n\tstart_dp[idx].addr = 0;\n/*\n * TODO: save one desc here?\n */\n\tstart_dp[idx].len = sizeof(struct virtio_net_hdr);\n\tstart_dp[idx].flags = VRING_DESC_F_NEXT;\n\tstart_dp[idx].addr = (uintptr_t)NULL;\n\tidx = start_dp[idx].next;\n\tstart_dp[idx].addr = RTE_MBUF_DATA_DMA_ADDR(cookie);\n\tstart_dp[idx].len = cookie->data_len;\n\tstart_dp[idx].flags = 0;\n\tidx = start_dp[idx].next;\n\ttxvq->vq_desc_head_idx = idx;\n\ttxvq->vq_free_cnt = (uint16_t)(txvq->vq_free_cnt - needed);\n\tvq_ring_update_avail(txvq, head_idx);\n\n\treturn 0;\n}\n\nstatic inline uint16_t __attribute__((always_inline))\nvirtqueue_dequeue_burst(struct virtqueue *vq, struct rte_mbuf **rx_pkts, uint32_t *len, uint16_t num)\n{\n\tstruct vring_used_elem *uep;\n\tstruct rte_mbuf *cookie;\n\tuint16_t used_idx, desc_idx;\n\tuint16_t i;\n\t/* Caller does the check */\n\tfor (i = 0; i < num ; i ++) {\n\t\tused_idx = (uint16_t)(vq->vq_used_cons_idx & (vq->vq_nentries - 1));\n\t\tuep = &vq->vq_ring.used->ring[used_idx];\n\t\tdesc_idx = (uint16_t) uep->id;\n\t\tcookie = (struct rte_mbuf *)vq->vq_descx[desc_idx].cookie;\n\t\tif (unlikely(cookie == NULL)) {\n\t\t\tPMD_DRV_LOG(ERR, \"vring descriptor with no mbuf cookie at %u\\n\",\n\t\t\t\tvq->vq_used_cons_idx);\n\t\t\tRTE_LOG(ERR, PMD, \"%s: inconsistent (%u, %u)\\n\", __func__, used_idx , desc_idx);\n\t\t\tbreak;\n\t\t}\n\t\tlen[i] = uep->len;\n\t\trx_pkts[i] = cookie;\n\t\tvq->vq_used_cons_idx++;\n\t\tvq_ring_free_chain(vq, desc_idx);\n\t\tvq->vq_descx[desc_idx].cookie = NULL;\n\t}\n\treturn i;\n}\n\n#endif /* _VIRTQUEUE_H_ */\n" }, { "path": "examples/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2014 6WIND S.A.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nDIRS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += bond\nDIRS-y += cmdline\nDIRS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) += distributor\nifneq ($(ICP_ROOT),)\nDIRS-y += dpdk_qat\nendif\nDIRS-y += exception_path\nDIRS-y += helloworld\nDIRS-y += ip_pipeline\nDIRS-y += ip_reassembly\nDIRS-$(CONFIG_RTE_IP_FRAG) += ip_fragmentation\nDIRS-y += ipv4_multicast\nDIRS-$(CONFIG_RTE_LIBRTE_KNI) += kni\nDIRS-y += l2fwd\nDIRS-$(CONFIG_RTE_LIBRTE_IVSHMEM) += l2fwd-ivshmem\nDIRS-$(CONFIG_RTE_LIBRTE_JOBSTATS) += l2fwd-jobstats\nDIRS-y += l3fwd\nDIRS-$(CONFIG_RTE_LIBRTE_ACL) += l3fwd-acl\nDIRS-$(CONFIG_RTE_LIBRTE_POWER) += l3fwd-power\nDIRS-y += l3fwd-vf\nDIRS-y += link_status_interrupt\nDIRS-y += load_balancer\nDIRS-y += multi_process\nDIRS-y += netmap_compat/bridge\nDIRS-$(CONFIG_RTE_LIBRTE_REORDER) += packet_ordering\nDIRS-$(CONFIG_RTE_LIBRTE_METER) += qos_meter\nDIRS-$(CONFIG_RTE_LIBRTE_SCHED) += qos_sched\nDIRS-y += quota_watermark\nDIRS-$(CONFIG_RTE_ETHDEV_RXTX_CALLBACKS) += rxtx_callbacks\nDIRS-y += skeleton\nDIRS-$(CONFIG_RTE_LIBRTE_VHOST) += tep_termination\nDIRS-$(CONFIG_RTE_LIBRTE_TIMER) += timer\nDIRS-$(CONFIG_RTE_LIBRTE_VHOST) += vhost\nDIRS-$(CONFIG_RTE_LIBRTE_XEN_DOM0) += vhost_xen\nDIRS-y += vmdq\nDIRS-y += vmdq_dcb\nDIRS-$(CONFIG_RTE_LIBRTE_POWER) += vm_power_manager\n\ninclude $(RTE_SDK)/mk/rte.extsubdir.mk\n" }, { "path": "examples/bond/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overridden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = bond_app\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\nCFLAGS += -O3\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/bond/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\n#include \n\n\n#include \"rte_byteorder.h\"\n#include \"rte_cpuflags.h\"\n#include \"rte_eth_bond.h\"\n\n#define RTE_LOGTYPE_DCB RTE_LOGTYPE_USER1\n\n#define NB_MBUF (1024*8)\n\n#define MAX_PKT_BURST 32\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n#define BURST_RX_INTERVAL_NS (10) /* RX poll interval ~100ns */\n\n/*\n * RX and TX Prefetch, Host, and Write-back threshold values should be\n * carefully set for optimal performance. Consult the network\n * controller's datasheet and supporting DPDK documentation for guidance\n * on how these parameters should be set.\n */\n#define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */\n#define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */\n#define RX_WTHRESH 4 /**< Default values of RX write-back threshold reg. */\n#define RX_FTHRESH (MAX_PKT_BURST * 2)/**< Default values of RX free threshold reg. */\n\n/*\n * These default values are optimized for use with the Intel(R) 82599 10 GbE\n * Controller and the DPDK ixgbe PMD. Consider using other values for other\n * network controllers and/or network drivers.\n */\n#define TX_PTHRESH 36 /**< Default values of TX prefetch threshold reg. */\n#define TX_HTHRESH 0 /**< Default values of TX host threshold reg. */\n#define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_RX_DESC_DEFAULT 128\n#define RTE_TX_DESC_DEFAULT 512\n\n#define BOND_IP_1\t7\n#define BOND_IP_2\t0\n#define BOND_IP_3\t0\n#define BOND_IP_4\t10\n\n/* not defined under linux */\n#ifndef NIPQUAD\n#define NIPQUAD_FMT \"%u.%u.%u.%u\"\n#endif\n\n#define MAX_PORTS\t4\n#define PRINT_MAC(addr)\t\tprintf(\"%02\"PRIx8\":%02\"PRIx8\":%02\"PRIx8 \\\n\t\t\":%02\"PRIx8\":%02\"PRIx8\":%02\"PRIx8,\t\\\n\t\taddr.addr_bytes[0], addr.addr_bytes[1], addr.addr_bytes[2], \\\n\t\taddr.addr_bytes[3], addr.addr_bytes[4], addr.addr_bytes[5])\n\nuint8_t slaves[RTE_MAX_ETHPORTS];\nuint8_t slaves_count;\n\nstatic uint8_t BOND_PORT = 0xff;\n\nstatic struct rte_mempool *mbuf_pool;\n\nstatic struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.mq_mode = ETH_MQ_RX_NONE,\n\t\t.max_rx_pkt_len = ETHER_MAX_LEN,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.rx_adv_conf = {\n\t\t.rss_conf = {\n\t\t\t.rss_key = NULL,\n\t\t\t.rss_hf = ETH_RSS_IP,\n\t\t},\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\nstatic void\nslave_port_init(uint8_t portid, struct rte_mempool *mbuf_pool)\n{\n\tint retval;\n\n\tif (portid >= rte_eth_dev_count())\n\t\trte_exit(EXIT_FAILURE, \"Invalid port\\n\");\n\n\tretval = rte_eth_dev_configure(portid, 1, 1, &port_conf);\n\tif (retval != 0)\n\t\trte_exit(EXIT_FAILURE, \"port %u: configuration failed (res=%d)\\n\",\n\t\t\t\tportid, retval);\n\n\t/* RX setup */\n\tretval = rte_eth_rx_queue_setup(portid, 0, RTE_RX_DESC_DEFAULT,\n\t\t\t\t\trte_eth_dev_socket_id(portid), NULL,\n\t\t\t\t\tmbuf_pool);\n\tif (retval < 0)\n\t\trte_exit(retval, \" port %u: RX queue 0 setup failed (res=%d)\",\n\t\t\t\tportid, retval);\n\n\t/* TX setup */\n\tretval = rte_eth_tx_queue_setup(portid, 0, RTE_TX_DESC_DEFAULT,\n\t\t\t\trte_eth_dev_socket_id(portid), NULL);\n\n\tif (retval < 0)\n\t\trte_exit(retval, \"port %u: TX queue 0 setup failed (res=%d)\",\n\t\t\t\tportid, retval);\n\n\tretval = rte_eth_dev_start(portid);\n\tif (retval < 0)\n\t\trte_exit(retval,\n\t\t\t\t\"Start port %d failed (res=%d)\",\n\t\t\t\tportid, retval);\n\n\tstruct ether_addr addr;\n\n\trte_eth_macaddr_get(portid, &addr);\n\tprintf(\"Port %u MAC: \", (unsigned)portid);\n\tPRINT_MAC(addr);\n\tprintf(\"\\n\");\n}\n\nstatic void\nbond_port_init(struct rte_mempool *mbuf_pool)\n{\n\tint retval;\n\tuint8_t i;\n\n\tretval = rte_eth_bond_create(\"bond0\", BONDING_MODE_ALB,\n\t\t\t0 /*SOCKET_ID_ANY*/);\n\tif (retval < 0)\n\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"Faled to create bond port\\n\");\n\n\tBOND_PORT = (uint8_t)retval;\n\n\tretval = rte_eth_dev_configure(BOND_PORT, 1, 1, &port_conf);\n\tif (retval != 0)\n\t\trte_exit(EXIT_FAILURE, \"port %u: configuration failed (res=%d)\\n\",\n\t\t\t\tBOND_PORT, retval);\n\n\t/* RX setup */\n\tretval = rte_eth_rx_queue_setup(BOND_PORT, 0, RTE_RX_DESC_DEFAULT,\n\t\t\t\t\trte_eth_dev_socket_id(BOND_PORT), NULL,\n\t\t\t\t\tmbuf_pool);\n\tif (retval < 0)\n\t\trte_exit(retval, \" port %u: RX queue 0 setup failed (res=%d)\",\n\t\t\t\tBOND_PORT, retval);\n\n\t/* TX setup */\n\tretval = rte_eth_tx_queue_setup(BOND_PORT, 0, RTE_TX_DESC_DEFAULT,\n\t\t\t\trte_eth_dev_socket_id(BOND_PORT), NULL);\n\n\tif (retval < 0)\n\t\trte_exit(retval, \"port %u: TX queue 0 setup failed (res=%d)\",\n\t\t\t\tBOND_PORT, retval);\n\n\tfor (i = 0; i < slaves_count; i++) {\n\t\tif (rte_eth_bond_slave_add(BOND_PORT, slaves[i]) == -1)\n\t\t\trte_exit(-1, \"Oooops! adding slave (%u) to bond (%u) failed!\\n\",\n\t\t\t\t\tslaves[i], BOND_PORT);\n\n\t}\n\n\tretval = rte_eth_dev_start(BOND_PORT);\n\tif (retval < 0)\n\t\trte_exit(retval, \"Start port %d failed (res=%d)\", BOND_PORT, retval);\n\n\trte_eth_promiscuous_enable(BOND_PORT);\n\n\tstruct ether_addr addr;\n\n\trte_eth_macaddr_get(BOND_PORT, &addr);\n\tprintf(\"Port %u MAC: \", (unsigned)BOND_PORT);\n\t\tPRINT_MAC(addr);\n\t\tprintf(\"\\n\");\n}\n\nstatic inline size_t\nget_vlan_offset(struct ether_hdr *eth_hdr, uint16_t *proto)\n{\n\tsize_t vlan_offset = 0;\n\n\tif (rte_cpu_to_be_16(ETHER_TYPE_VLAN) == *proto) {\n\t\tstruct vlan_hdr *vlan_hdr = (struct vlan_hdr *)(eth_hdr + 1);\n\n\t\tvlan_offset = sizeof(struct vlan_hdr);\n\t\t*proto = vlan_hdr->eth_proto;\n\n\t\tif (rte_cpu_to_be_16(ETHER_TYPE_VLAN) == *proto) {\n\t\t\tvlan_hdr = vlan_hdr + 1;\n\n\t\t\t*proto = vlan_hdr->eth_proto;\n\t\t\tvlan_offset += sizeof(struct vlan_hdr);\n\t\t}\n\t}\n\treturn vlan_offset;\n}\n\nstruct global_flag_stru_t {\n\tint LcoreMainIsRunning;\n\tint LcoreMainCore;\n\tuint32_t port_packets[4];\n\trte_spinlock_t lock;\n};\nstruct global_flag_stru_t global_flag_stru;\nstruct global_flag_stru_t *global_flag_stru_p = &global_flag_stru;\n\n/*\n * Main thread that does the work, reading from INPUT_PORT\n * and writing to OUTPUT_PORT\n */\nstatic int lcore_main(__attribute__((unused)) void *arg1)\n{\n\tstruct rte_mbuf *pkts[MAX_PKT_BURST] __rte_cache_aligned;\n\tstruct ether_addr d_addr;\n\n\tstruct ether_hdr *eth_hdr;\n\tstruct arp_hdr *arp_hdr;\n\tstruct ipv4_hdr *ipv4_hdr;\n\tuint16_t ether_type, offset;\n\n\tuint16_t rx_cnt;\n\tuint32_t bond_ip;\n\tint i = 0;\n\tuint8_t is_free;\n\n\tbond_ip = BOND_IP_1 | (BOND_IP_2 << 8) |\n\t\t\t\t(BOND_IP_3 << 16) | (BOND_IP_4 << 24);\n\n\trte_spinlock_trylock(&global_flag_stru_p->lock);\n\n\twhile (global_flag_stru_p->LcoreMainIsRunning) {\n\t\trte_spinlock_unlock(&global_flag_stru_p->lock);\n\t\trx_cnt = rte_eth_rx_burst(BOND_PORT, 0, pkts, MAX_PKT_BURST);\n\t\tis_free = 0;\n\n\t\t/* If didn't receive any packets, wait and go to next iteration */\n\t\tif (rx_cnt == 0) {\n\t\t\trte_delay_us(50);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Search incoming data for ARP packets and prepare response */\n\t\tfor (i = 0; i < rx_cnt; i++) {\n\t\t\tif (rte_spinlock_trylock(&global_flag_stru_p->lock) == 1) {\n\t\t\t\tglobal_flag_stru_p->port_packets[0]++;\n\t\t\t\trte_spinlock_unlock(&global_flag_stru_p->lock);\n\t\t\t}\n\t\t\teth_hdr = rte_pktmbuf_mtod(pkts[i], struct ether_hdr *);\n\t\t\tether_type = eth_hdr->ether_type;\n\t\t\tif (ether_type == rte_cpu_to_be_16(ETHER_TYPE_VLAN))\n\t\t\t\tprintf(\"VLAN taged frame, offset:\");\n\t\t\toffset = get_vlan_offset(eth_hdr, ðer_type);\n\t\t\tif (offset > 0)\n\t\t\t\tprintf(\"%d\\n\", offset);\n\t\t\tif (ether_type == rte_cpu_to_be_16(ETHER_TYPE_ARP)) {\n\t\t\t\tif (rte_spinlock_trylock(&global_flag_stru_p->lock) == 1) {\n\t\t\t\t\tglobal_flag_stru_p->port_packets[1]++;\n\t\t\t\t\trte_spinlock_unlock(&global_flag_stru_p->lock);\n\t\t\t\t}\n\t\t\t\tarp_hdr = (struct arp_hdr *)((char *)(eth_hdr + 1) + offset);\n\t\t\t\tif (arp_hdr->arp_data.arp_tip == bond_ip) {\n\t\t\t\t\tif (arp_hdr->arp_op == rte_cpu_to_be_16(ARP_OP_REQUEST)) {\n\t\t\t\t\t\tarp_hdr->arp_op = rte_cpu_to_be_16(ARP_OP_REPLY);\n\t\t\t\t\t\t/* Switch src and dst data and set bonding MAC */\n\t\t\t\t\t\tether_addr_copy(ð_hdr->s_addr, ð_hdr->d_addr);\n\t\t\t\t\t\trte_eth_macaddr_get(BOND_PORT, ð_hdr->s_addr);\n\t\t\t\t\t\tether_addr_copy(&arp_hdr->arp_data.arp_sha, &arp_hdr->arp_data.arp_tha);\n\t\t\t\t\t\tarp_hdr->arp_data.arp_tip = arp_hdr->arp_data.arp_sip;\n\t\t\t\t\t\trte_eth_macaddr_get(BOND_PORT, &d_addr);\n\t\t\t\t\t\tether_addr_copy(&d_addr, &arp_hdr->arp_data.arp_sha);\n\t\t\t\t\t\tarp_hdr->arp_data.arp_sip = bond_ip;\n\t\t\t\t\t\trte_eth_tx_burst(BOND_PORT, 0, &pkts[i], 1);\n\t\t\t\t\t\tis_free = 1;\n\t\t\t\t\t} else {\n\t\t\t\t\t\trte_eth_tx_burst(BOND_PORT, 0, NULL, 0);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else if (ether_type == rte_cpu_to_be_16(ETHER_TYPE_IPv4)) {\n\t\t\t\tif (rte_spinlock_trylock(&global_flag_stru_p->lock) == 1) {\n\t\t\t\t\tglobal_flag_stru_p->port_packets[2]++;\n\t\t\t\t\trte_spinlock_unlock(&global_flag_stru_p->lock);\n\t\t\t\t }\n\t\t\t\tipv4_hdr = (struct ipv4_hdr *)((char *)(eth_hdr + 1) + offset);\n\t\t\t\tif (ipv4_hdr->dst_addr == bond_ip) {\n\t\t\t\t\tether_addr_copy(ð_hdr->s_addr, ð_hdr->d_addr);\n\t\t\t\t\trte_eth_macaddr_get(BOND_PORT, ð_hdr->s_addr);\n\t\t\t\t\tipv4_hdr->dst_addr = ipv4_hdr->src_addr;\n\t\t\t\t\tipv4_hdr->src_addr = bond_ip;\n\t\t\t\t\trte_eth_tx_burst(BOND_PORT, 0, &pkts[i], 1);\n\t\t\t\t}\n\n\t\t\t}\n\n\t\t\t/* Free processed packets */\n\t\t\tif (is_free == 0)\n\t\t\t\trte_pktmbuf_free(pkts[i]);\n\t\t}\n\t\trte_spinlock_trylock(&global_flag_stru_p->lock);\n\t}\n\trte_spinlock_unlock(&global_flag_stru_p->lock);\n\tprintf(\"BYE lcore_main\\n\");\n\treturn 0;\n}\n\nstruct cmd_obj_send_result {\n\tcmdline_fixed_string_t action;\n\tcmdline_ipaddr_t ip;\n};\nstatic inline void get_string(struct cmd_obj_send_result *res, char *buf, uint8_t size)\n{\n\tsnprintf(buf, size, NIPQUAD_FMT,\n\t\t((unsigned)((unsigned char *)&(res->ip.addr.ipv4))[0]),\n\t\t((unsigned)((unsigned char *)&(res->ip.addr.ipv4))[1]),\n\t\t((unsigned)((unsigned char *)&(res->ip.addr.ipv4))[2]),\n\t\t((unsigned)((unsigned char *)&(res->ip.addr.ipv4))[3])\n\t\t);\n}\nstatic void cmd_obj_send_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\n\tstruct cmd_obj_send_result *res = parsed_result;\n\tchar ip_str[INET6_ADDRSTRLEN];\n\n\tstruct rte_mbuf *created_pkt;\n\tstruct ether_hdr *eth_hdr;\n\tstruct arp_hdr *arp_hdr;\n\n\tuint32_t bond_ip;\n\tsize_t pkt_size;\n\n\tif (res->ip.family == AF_INET)\n\t\tget_string(res, ip_str, INET_ADDRSTRLEN);\n\telse\n\t\tcmdline_printf(cl, \"Wrong IP format. Only IPv4 is supported\\n\");\n\n\tbond_ip = BOND_IP_1 | (BOND_IP_2 << 8) |\n\t\t\t\t(BOND_IP_3 << 16) | (BOND_IP_4 << 24);\n\n\tcreated_pkt = rte_pktmbuf_alloc(mbuf_pool);\n\tpkt_size = sizeof(struct ether_hdr) + sizeof(struct arp_hdr);\n\tcreated_pkt->data_len = pkt_size;\n\tcreated_pkt->pkt_len = pkt_size;\n\n\teth_hdr = rte_pktmbuf_mtod(created_pkt, struct ether_hdr *);\n\trte_eth_macaddr_get(BOND_PORT, ð_hdr->s_addr);\n\tmemset(ð_hdr->d_addr, 0xFF, ETHER_ADDR_LEN);\n\teth_hdr->ether_type = rte_cpu_to_be_16(ETHER_TYPE_ARP);\n\n\tarp_hdr = (struct arp_hdr *)((char *)eth_hdr + sizeof(struct ether_hdr));\n\tarp_hdr->arp_hrd = rte_cpu_to_be_16(ARP_HRD_ETHER);\n\tarp_hdr->arp_pro = rte_cpu_to_be_16(ETHER_TYPE_IPv4);\n\tarp_hdr->arp_hln = ETHER_ADDR_LEN;\n\tarp_hdr->arp_pln = sizeof(uint32_t);\n\tarp_hdr->arp_op = rte_cpu_to_be_16(ARP_OP_REQUEST);\n\n\trte_eth_macaddr_get(BOND_PORT, &arp_hdr->arp_data.arp_sha);\n\tarp_hdr->arp_data.arp_sip = bond_ip;\n\tmemset(&arp_hdr->arp_data.arp_tha, 0, ETHER_ADDR_LEN);\n\tarp_hdr->arp_data.arp_tip =\n\t\t\t ((unsigned char *)&res->ip.addr.ipv4)[0] |\n\t\t\t (((unsigned char *)&res->ip.addr.ipv4)[1] << 8) |\n\t\t\t (((unsigned char *)&res->ip.addr.ipv4)[2] << 16) |\n\t\t\t (((unsigned char *)&res->ip.addr.ipv4)[3] << 24);\n\trte_eth_tx_burst(BOND_PORT, 0, &created_pkt, 1);\n\n\trte_delay_ms(100);\n\tcmdline_printf(cl, \"\\n\");\n}\n\ncmdline_parse_token_string_t cmd_obj_action_send =\n\tTOKEN_STRING_INITIALIZER(struct cmd_obj_send_result, action, \"send\");\ncmdline_parse_token_ipaddr_t cmd_obj_ip =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_obj_send_result, ip);\n\ncmdline_parse_inst_t cmd_obj_send = {\n\t.f = cmd_obj_send_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"send client_ip\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_obj_action_send,\n\t\t(void *)&cmd_obj_ip,\n\t\tNULL,\n\t},\n};\n\nstruct cmd_start_result {\n\tcmdline_fixed_string_t start;\n};\n\nstatic void cmd_start_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tint slave_core_id = rte_lcore_id();\n\n\trte_spinlock_trylock(&global_flag_stru_p->lock);\n\tif (global_flag_stru_p->LcoreMainIsRunning == 0)\t{\n\t\tif (lcore_config[global_flag_stru_p->LcoreMainCore].state != WAIT)\t{\n\t\t\trte_spinlock_unlock(&global_flag_stru_p->lock);\n\t\t\treturn;\n\t\t}\n\t\trte_spinlock_unlock(&global_flag_stru_p->lock);\n\t} else {\n\t\tcmdline_printf(cl, \"lcore_main already running on core:%d\\n\",\n\t\t\t\tglobal_flag_stru_p->LcoreMainCore);\n\t\trte_spinlock_unlock(&global_flag_stru_p->lock);\n\t\treturn;\n\t}\n\n\t/* start lcore main on core != master_core - ARP response thread */\n\tslave_core_id = rte_get_next_lcore(rte_lcore_id(), 1, 0);\n\tif ((slave_core_id >= RTE_MAX_LCORE) || (slave_core_id == 0))\n\t\treturn;\n\n\trte_spinlock_trylock(&global_flag_stru_p->lock);\n\tglobal_flag_stru_p->LcoreMainIsRunning = 1;\n\trte_spinlock_unlock(&global_flag_stru_p->lock);\n\tcmdline_printf(cl,\n\t\t\t\"Starting lcore_main on core %d:%d \"\n\t\t\t\"Our IP:%d.%d.%d.%d\\n\",\n\t\t\tslave_core_id,\n\t\t\trte_eal_remote_launch(lcore_main, NULL, slave_core_id),\n\t\t\tBOND_IP_1,\n\t\t\tBOND_IP_2,\n\t\t\tBOND_IP_3,\n\t\t\tBOND_IP_4\n\t\t);\n}\n\ncmdline_parse_token_string_t cmd_start_start =\n\tTOKEN_STRING_INITIALIZER(struct cmd_start_result, start, \"start\");\n\ncmdline_parse_inst_t cmd_start = {\n\t.f = cmd_start_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"starts listening if not started at startup\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_start_start,\n\t\tNULL,\n\t},\n};\n\nstruct cmd_help_result {\n\tcmdline_fixed_string_t help;\n};\n\nstatic void cmd_help_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tcmdline_printf(cl,\n\t\t\t\"ALB - link bonding mode 6 example\\n\"\n\t\t\t\"send IP\t- sends one ARPrequest thru bonding for IP.\\n\"\n\t\t\t\"start\t\t- starts listening ARPs.\\n\"\n\t\t\t\"stop\t\t- stops lcore_main.\\n\"\n\t\t\t\"show\t\t- shows some bond info: ex. active slaves etc.\\n\"\n\t\t\t\"help\t\t- prints help.\\n\"\n\t\t\t\"quit\t\t- terminate all threads and quit.\\n\"\n\t\t );\n}\n\ncmdline_parse_token_string_t cmd_help_help =\n\tTOKEN_STRING_INITIALIZER(struct cmd_help_result, help, \"help\");\n\ncmdline_parse_inst_t cmd_help = {\n\t.f = cmd_help_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"show help\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_help_help,\n\t\tNULL,\n\t},\n};\n\nstruct cmd_stop_result {\n\tcmdline_fixed_string_t stop;\n};\n\nstatic void cmd_stop_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\trte_spinlock_trylock(&global_flag_stru_p->lock);\n\tif (global_flag_stru_p->LcoreMainIsRunning == 0)\t{\n\t\tcmdline_printf(cl,\n\t\t\t\t\t\"lcore_main not running on core:%d\\n\",\n\t\t\t\t\tglobal_flag_stru_p->LcoreMainCore);\n\t\trte_spinlock_unlock(&global_flag_stru_p->lock);\n\t\treturn;\n\t}\n\tglobal_flag_stru_p->LcoreMainIsRunning = 0;\n\trte_eal_wait_lcore(global_flag_stru_p->LcoreMainCore);\n\tcmdline_printf(cl,\n\t\t\t\"lcore_main stopped on core:%d\\n\",\n\t\t\tglobal_flag_stru_p->LcoreMainCore);\n\trte_spinlock_unlock(&global_flag_stru_p->lock);\n}\n\ncmdline_parse_token_string_t cmd_stop_stop =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stop_result, stop, \"stop\");\n\ncmdline_parse_inst_t cmd_stop = {\n\t.f = cmd_stop_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"this command do not handle any arguments\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_stop_stop,\n\t\tNULL,\n\t},\n};\n\nstruct cmd_quit_result {\n\tcmdline_fixed_string_t quit;\n};\n\nstatic void cmd_quit_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\trte_spinlock_trylock(&global_flag_stru_p->lock);\n\tif (global_flag_stru_p->LcoreMainIsRunning == 0)\t{\n\t\tcmdline_printf(cl,\n\t\t\t\t\t\"lcore_main not running on core:%d\\n\",\n\t\t\t\t\tglobal_flag_stru_p->LcoreMainCore);\n\t\trte_spinlock_unlock(&global_flag_stru_p->lock);\n\t\tcmdline_quit(cl);\n\t\treturn;\n\t}\n\tglobal_flag_stru_p->LcoreMainIsRunning = 0;\n\trte_eal_wait_lcore(global_flag_stru_p->LcoreMainCore);\n\tcmdline_printf(cl,\n\t\t\t\"lcore_main stopped on core:%d\\n\",\n\t\t\tglobal_flag_stru_p->LcoreMainCore);\n\trte_spinlock_unlock(&global_flag_stru_p->lock);\n\tcmdline_quit(cl);\n}\n\ncmdline_parse_token_string_t cmd_quit_quit =\n\tTOKEN_STRING_INITIALIZER(struct cmd_quit_result, quit, \"quit\");\n\ncmdline_parse_inst_t cmd_quit = {\n\t.f = cmd_quit_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"this command do not handle any arguments\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_quit_quit,\n\t\tNULL,\n\t},\n};\n\nstruct cmd_show_result {\n\tcmdline_fixed_string_t show;\n};\n\nstatic void cmd_show_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tuint8_t slaves[16] = {0};\n\tuint8_t len = 16;\n\tstruct ether_addr addr;\n\tuint8_t i = 0;\n\n\twhile (i < slaves_count)\t{\n\t\trte_eth_macaddr_get(i, &addr);\n\t\tPRINT_MAC(addr);\n\t\tprintf(\"\\n\");\n\t\ti++;\n\t}\n\n\trte_spinlock_trylock(&global_flag_stru_p->lock);\n\tcmdline_printf(cl,\n\t\t\t\"Active_slaves:%d \"\n\t\t\t\"packets received:Tot:%d Arp:%d IPv4:%d\\n\",\n\t\t\trte_eth_bond_active_slaves_get(BOND_PORT, slaves, len),\n\t\t\tglobal_flag_stru_p->port_packets[0],\n\t\t\tglobal_flag_stru_p->port_packets[1],\n\t\t\tglobal_flag_stru_p->port_packets[2]);\n\trte_spinlock_unlock(&global_flag_stru_p->lock);\n}\n\ncmdline_parse_token_string_t cmd_show_show =\n\tTOKEN_STRING_INITIALIZER(struct cmd_show_result, show, \"show\");\n\ncmdline_parse_inst_t cmd_show = {\n\t.f = cmd_show_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"this command do not handle any arguments\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_show_show,\n\t\tNULL,\n\t},\n};\n\n/****** CONTEXT (list of instruction) */\n\ncmdline_parse_ctx_t main_ctx[] = {\n\t(cmdline_parse_inst_t *)&cmd_start,\n\t(cmdline_parse_inst_t *)&cmd_obj_send,\n\t(cmdline_parse_inst_t *)&cmd_stop,\n\t(cmdline_parse_inst_t *)&cmd_show,\n\t(cmdline_parse_inst_t *)&cmd_quit,\n\t(cmdline_parse_inst_t *)&cmd_help,\n\tNULL,\n};\n\n/* prompt function, called from main on MASTER lcore */\nstatic void prompt(__attribute__((unused)) void *arg1)\n{\n\tstruct cmdline *cl;\n\n\tcl = cmdline_stdin_new(main_ctx, \"bond6>\");\n\tif (cl != NULL) {\n\t\tcmdline_interact(cl);\n\t\tcmdline_stdin_exit(cl);\n\t}\n}\n\n/* Main function, does initialisation and calls the per-lcore functions */\nint\nmain(int argc, char *argv[])\n{\n\tint ret;\n\tuint8_t nb_ports, i;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\trte_eal_devargs_dump(stdout);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Error with EAL initialization\\n\");\n\targc -= ret;\n\targv += ret;\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports == 0)\n\t\trte_exit(EXIT_FAILURE, \"Give at least one port\\n\");\n\telse if (nb_ports > MAX_PORTS)\n\t\trte_exit(EXIT_FAILURE, \"You can have max 4 ports\\n\");\n\n\tmbuf_pool = rte_pktmbuf_pool_create(\"MBUF_POOL\", NB_MBUF, 32,\n\t\t0, RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\tif (mbuf_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create mbuf pool\\n\");\n\n\t/* initialize all ports */\n\tslaves_count = nb_ports;\n\tfor (i = 0; i < nb_ports; i++) {\n\t\tslave_port_init(i, mbuf_pool);\n\t\tslaves[i] = i;\n\t}\n\n\tbond_port_init(mbuf_pool);\n\n\trte_spinlock_init(&global_flag_stru_p->lock);\n\tint slave_core_id = rte_lcore_id();\n\n\t/* check state of lcores */\n\tRTE_LCORE_FOREACH_SLAVE(slave_core_id) {\n\tif (lcore_config[slave_core_id].state != WAIT)\n\t\treturn -EBUSY;\n\t}\n\t/* start lcore main on core != master_core - ARP response thread */\n\tslave_core_id = rte_get_next_lcore(rte_lcore_id(), 1, 0);\n\tif ((slave_core_id >= RTE_MAX_LCORE) || (slave_core_id == 0))\n\t\treturn -EPERM;\n\n\tglobal_flag_stru_p->LcoreMainIsRunning = 1;\n\tglobal_flag_stru_p->LcoreMainCore = slave_core_id;\n\tprintf(\"Starting lcore_main on core %d:%d Our IP:%d.%d.%d.%d\\n\",\n\t\t\tslave_core_id,\n\t\t\trte_eal_remote_launch((lcore_function_t *)lcore_main,\n\t\t\t\t\tNULL,\n\t\t\t\t\tslave_core_id),\n\t\t\tBOND_IP_1,\n\t\t\tBOND_IP_2,\n\t\t\tBOND_IP_3,\n\t\t\tBOND_IP_4\n\t\t);\n\n\t/* Start prompt for user interact */\n\tprompt(NULL);\n\n\trte_delay_ms(100);\n\treturn 0;\n}\n" }, { "path": "examples/bond/main.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _MAIN_H_\n#define _MAIN_H_\n\nint main(int argc, char *argv[]);\n\n#endif /* ifndef _MAIN_H_ */\n" }, { "path": "examples/cmdline/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = cmdline\n\n# all source are stored in SRCS-y\nSRCS-y := main.c commands.c parse_obj_list.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\nCFLAGS_parse_obj_list.o := -D_GNU_SOURCE\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/cmdline/commands.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#ifndef __linux__\n\t#ifdef __FreeBSD__\n\t\t#include \n\t#else\n\t\t#include \n\t#endif\n#endif\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"parse_obj_list.h\"\n\nstruct object_list global_obj_list;\n\n/* not defined under linux */\n#ifndef NIPQUAD\n#define NIPQUAD_FMT \"%u.%u.%u.%u\"\n#define NIPQUAD(addr)\t\t\t\t\\\n\t(unsigned)((unsigned char *)&addr)[0],\t\\\n\t(unsigned)((unsigned char *)&addr)[1],\t\\\n\t(unsigned)((unsigned char *)&addr)[2],\t\\\n\t(unsigned)((unsigned char *)&addr)[3]\n#endif\n\n#ifndef NIP6\n#define NIP6_FMT \"%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x\"\n#define NIP6(addr)\t\t\t\t\t\\\n\t(unsigned)((addr).s6_addr[0]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[1]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[2]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[3]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[4]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[5]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[6]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[7]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[8]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[9]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[10]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[11]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[12]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[13]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[14]),\t\t\t\\\n\t(unsigned)((addr).s6_addr[15])\n#endif\n\n\n/**********************************************************/\n\nstruct cmd_obj_del_show_result {\n\tcmdline_fixed_string_t action;\n\tstruct object *obj;\n};\n\nstatic void cmd_obj_del_show_parsed(void *parsed_result,\n\t\t\t\t struct cmdline *cl,\n\t\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_obj_del_show_result *res = parsed_result;\n\tchar ip_str[INET6_ADDRSTRLEN];\n\n\tif (res->obj->ip.family == AF_INET)\n\t\tsnprintf(ip_str, sizeof(ip_str), NIPQUAD_FMT,\n\t\t\t NIPQUAD(res->obj->ip.addr.ipv4));\n\telse\n\t\tsnprintf(ip_str, sizeof(ip_str), NIP6_FMT,\n\t\t\t NIP6(res->obj->ip.addr.ipv6));\n\n\tif (strcmp(res->action, \"del\") == 0) {\n\t\tSLIST_REMOVE(&global_obj_list, res->obj, object, next);\n\t\tcmdline_printf(cl, \"Object %s removed, ip=%s\\n\",\n\t\t\t res->obj->name, ip_str);\n\t\tfree(res->obj);\n\t}\n\telse if (strcmp(res->action, \"show\") == 0) {\n\t\tcmdline_printf(cl, \"Object %s, ip=%s\\n\",\n\t\t\t res->obj->name, ip_str);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_obj_action =\n\tTOKEN_STRING_INITIALIZER(struct cmd_obj_del_show_result,\n\t\t\t\t action, \"show#del\");\nparse_token_obj_list_t cmd_obj_obj =\n\tTOKEN_OBJ_LIST_INITIALIZER(struct cmd_obj_del_show_result, obj,\n\t\t\t\t &global_obj_list);\n\ncmdline_parse_inst_t cmd_obj_del_show = {\n\t.f = cmd_obj_del_show_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"Show/del an object\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_obj_action,\n\t\t(void *)&cmd_obj_obj,\n\t\tNULL,\n\t},\n};\n\n/**********************************************************/\n\nstruct cmd_obj_add_result {\n\tcmdline_fixed_string_t action;\n\tcmdline_fixed_string_t name;\n\tcmdline_ipaddr_t ip;\n};\n\nstatic void cmd_obj_add_parsed(void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_obj_add_result *res = parsed_result;\n\tstruct object *o;\n\tchar ip_str[INET6_ADDRSTRLEN];\n\n\tSLIST_FOREACH(o, &global_obj_list, next) {\n\t\tif (!strcmp(res->name, o->name)) {\n\t\t\tcmdline_printf(cl, \"Object %s already exist\\n\", res->name);\n\t\t\treturn;\n\t\t}\n\t\tbreak;\n\t}\n\n\to = malloc(sizeof(*o));\n\tif (!o) {\n\t\tcmdline_printf(cl, \"mem error\\n\");\n\t\treturn;\n\t}\n\tsnprintf(o->name, sizeof(o->name), \"%s\", res->name);\n\to->ip = res->ip;\n\tSLIST_INSERT_HEAD(&global_obj_list, o, next);\n\n\tif (o->ip.family == AF_INET)\n\t\tsnprintf(ip_str, sizeof(ip_str), NIPQUAD_FMT,\n\t\t\t NIPQUAD(o->ip.addr.ipv4));\n\telse\n\t\tsnprintf(ip_str, sizeof(ip_str), NIP6_FMT,\n\t\t\t NIP6(o->ip.addr.ipv6));\n\n\tcmdline_printf(cl, \"Object %s added, ip=%s\\n\",\n\t\t o->name, ip_str);\n}\n\ncmdline_parse_token_string_t cmd_obj_action_add =\n\tTOKEN_STRING_INITIALIZER(struct cmd_obj_add_result, action, \"add\");\ncmdline_parse_token_string_t cmd_obj_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_obj_add_result, name, NULL);\ncmdline_parse_token_ipaddr_t cmd_obj_ip =\n\tTOKEN_IPADDR_INITIALIZER(struct cmd_obj_add_result, ip);\n\ncmdline_parse_inst_t cmd_obj_add = {\n\t.f = cmd_obj_add_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"Add an object (name, val)\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_obj_action_add,\n\t\t(void *)&cmd_obj_name,\n\t\t(void *)&cmd_obj_ip,\n\t\tNULL,\n\t},\n};\n\n/**********************************************************/\n\nstruct cmd_help_result {\n\tcmdline_fixed_string_t help;\n};\n\nstatic void cmd_help_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tcmdline_printf(cl,\n\t\t \"Demo example of command line interface in RTE\\n\\n\"\n\t\t \"This is a readline-like interface that can be used to\\n\"\n\t\t \"debug your RTE application. It supports some features\\n\"\n\t\t \"of GNU readline like completion, cut/paste, and some\\n\"\n\t\t \"other special bindings.\\n\\n\"\n\t\t \"This demo shows how rte_cmdline library can be\\n\"\n\t\t \"extended to handle a list of objects. There are\\n\"\n\t\t \"3 commands:\\n\"\n\t\t \"- add obj_name IP\\n\"\n\t\t \"- del obj_name\\n\"\n\t\t \"- show obj_name\\n\\n\");\n}\n\ncmdline_parse_token_string_t cmd_help_help =\n\tTOKEN_STRING_INITIALIZER(struct cmd_help_result, help, \"help\");\n\ncmdline_parse_inst_t cmd_help = {\n\t.f = cmd_help_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"show help\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_help_help,\n\t\tNULL,\n\t},\n};\n\n\n/**********************************************************/\n/**********************************************************/\n/****** CONTEXT (list of instruction) */\n\ncmdline_parse_ctx_t main_ctx[] = {\n\t(cmdline_parse_inst_t *)&cmd_obj_del_show,\n\t(cmdline_parse_inst_t *)&cmd_obj_add,\n\t(cmdline_parse_inst_t *)&cmd_help,\n\tNULL,\n};\n" }, { "path": "examples/cmdline/commands.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _COMMANDS_H_\n#define _COMMANDS_H_\n\nextern cmdline_parse_ctx_t main_ctx[];\n\n#endif /* _COMMANDS_H_ */\n" }, { "path": "examples/cmdline/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"commands.h\"\n\nint main(int argc, char **argv)\n{\n\tint ret;\n\tstruct cmdline *cl;\n\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_panic(\"Cannot init EAL\\n\");\n\n\tcl = cmdline_stdin_new(main_ctx, \"example> \");\n\tif (cl == NULL)\n\t\trte_panic(\"Cannot create cmdline instance\\n\");\n\tcmdline_interact(cl);\n\tcmdline_stdin_exit(cl);\n\n\treturn 0;\n}\n" }, { "path": "examples/cmdline/parse_obj_list.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n\n#include \"parse_obj_list.h\"\n\n/* This file is an example of extension of libcmdline. It provides an\n * example of objects stored in a list. */\n\nstruct cmdline_token_ops token_obj_list_ops = {\n\t.parse = parse_obj_list,\n\t.complete_get_nb = complete_get_nb_obj_list,\n\t.complete_get_elt = complete_get_elt_obj_list,\n\t.get_help = get_help_obj_list,\n};\n\nint\nparse_obj_list(cmdline_parse_token_hdr_t *tk, const char *buf, void *res,\n\tunsigned ressize)\n{\n\tstruct token_obj_list *tk2 = (struct token_obj_list *)tk;\n\tstruct token_obj_list_data *tkd = &tk2->obj_list_data;\n\tstruct object *o;\n\tunsigned int token_len = 0;\n\n\tif (*buf == 0)\n\t\treturn -1;\n\n\tif (res && ressize < sizeof(struct object *))\n\t\treturn -1;\n\n\twhile(!cmdline_isendoftoken(buf[token_len]))\n\t\ttoken_len++;\n\n\tSLIST_FOREACH(o, tkd->list, next) {\n\t\tif (token_len != strnlen(o->name, OBJ_NAME_LEN_MAX))\n\t\t\tcontinue;\n\t\tif (strncmp(buf, o->name, token_len))\n\t\t\tcontinue;\n\t\tbreak;\n\t}\n\tif (!o) /* not found */\n\t\treturn -1;\n\n\t/* store the address of object in structure */\n\tif (res)\n\t\t*(struct object **)res = o;\n\n\treturn token_len;\n}\n\nint complete_get_nb_obj_list(cmdline_parse_token_hdr_t *tk)\n{\n\tstruct token_obj_list *tk2 = (struct token_obj_list *)tk;\n\tstruct token_obj_list_data *tkd = &tk2->obj_list_data;\n\tstruct object *o;\n\tint ret = 0;\n\n\tSLIST_FOREACH(o, tkd->list, next) {\n\t\tret ++;\n\t}\n\treturn ret;\n}\n\nint complete_get_elt_obj_list(cmdline_parse_token_hdr_t *tk,\n\t\t\t int idx, char *dstbuf, unsigned int size)\n{\n\tstruct token_obj_list *tk2 = (struct token_obj_list *)tk;\n\tstruct token_obj_list_data *tkd = &tk2->obj_list_data;\n\tstruct object *o;\n\tint i = 0;\n\tunsigned len;\n\n\tSLIST_FOREACH(o, tkd->list, next) {\n\t\tif (i++ == idx)\n\t\t\tbreak;\n\t}\n\tif (!o)\n\t\treturn -1;\n\n\tlen = strnlen(o->name, OBJ_NAME_LEN_MAX);\n\tif ((len + 1) > size)\n\t\treturn -1;\n\n\tif (dstbuf)\n\t\tsnprintf(dstbuf, size, \"%s\", o->name);\n\n\treturn 0;\n}\n\n\nint get_help_obj_list(__attribute__((unused)) cmdline_parse_token_hdr_t *tk,\n\t\t char *dstbuf, unsigned int size)\n{\n\tsnprintf(dstbuf, size, \"Obj-List\");\n\treturn 0;\n}\n" }, { "path": "examples/cmdline/parse_obj_list.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _PARSE_OBJ_LIST_H_\n#define _PARSE_OBJ_LIST_H_\n\n/* This file is an example of extension of libcmdline. It provides an\n * example of objects stored in a list. */\n\n#include \n#include \n\n#define OBJ_NAME_LEN_MAX 64\n\nstruct object {\n\tSLIST_ENTRY(object) next;\n\tchar name[OBJ_NAME_LEN_MAX];\n\tcmdline_ipaddr_t ip;\n};\n\n/* define struct object_list */\nSLIST_HEAD(object_list, object);\n\n/* data is a pointer to a list */\nstruct token_obj_list_data {\n\tstruct object_list *list;\n};\n\nstruct token_obj_list {\n\tstruct cmdline_token_hdr hdr;\n\tstruct token_obj_list_data obj_list_data;\n};\ntypedef struct token_obj_list parse_token_obj_list_t;\n\nextern struct cmdline_token_ops token_obj_list_ops;\n\nint parse_obj_list(cmdline_parse_token_hdr_t *tk, const char *srcbuf, void *res,\n\tunsigned ressize);\nint complete_get_nb_obj_list(cmdline_parse_token_hdr_t *tk);\nint complete_get_elt_obj_list(cmdline_parse_token_hdr_t *tk, int idx,\n\t\t\t char *dstbuf, unsigned int size);\nint get_help_obj_list(cmdline_parse_token_hdr_t *tk, char *dstbuf, unsigned int size);\n\n#define TOKEN_OBJ_LIST_INITIALIZER(structure, field, obj_list_ptr) \\\n{\t\t\t\t\t\t\t\t \\\n\t.hdr = {\t\t\t\t\t\t \\\n\t\t.ops = &token_obj_list_ops,\t\t\t \\\n\t\t.offset = offsetof(structure, field),\t\t \\\n\t},\t\t\t\t\t\t\t \\\n\t\t.obj_list_data = {\t\t\t\t \\\n\t\t.list = obj_list_ptr,\t\t\t\t \\\n\t},\t\t\t\t\t\t\t \\\n}\n\n#endif /* _PARSE_OBJ_LIST_H_ */\n" }, { "path": "examples/distributor/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = distributor_app\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\nEXTRA_CFLAGS += -O3 -Wfatal-errors\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/distributor/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#define RX_RING_SIZE 256\n#define TX_RING_SIZE 512\n#define NUM_MBUFS ((64*1024)-1)\n#define MBUF_CACHE_SIZE 250\n#define BURST_SIZE 32\n#define RTE_RING_SZ 1024\n\n/* uncommnet below line to enable debug logs */\n/* #define DEBUG */\n\n#ifdef DEBUG\n#define LOG_LEVEL RTE_LOG_DEBUG\n#define LOG_DEBUG(log_type, fmt, args...) do {\t\\\n\tRTE_LOG(DEBUG, log_type, fmt, ##args);\t\t\\\n} while (0)\n#else\n#define LOG_LEVEL RTE_LOG_INFO\n#define LOG_DEBUG(log_type, fmt, args...) do {} while (0)\n#endif\n\n#define RTE_LOGTYPE_DISTRAPP RTE_LOGTYPE_USER1\n\n/* mask of enabled ports */\nstatic uint32_t enabled_port_mask;\nvolatile uint8_t quit_signal;\nvolatile uint8_t quit_signal_rx;\n\nstatic volatile struct app_stats {\n\tstruct {\n\t\tuint64_t rx_pkts;\n\t\tuint64_t returned_pkts;\n\t\tuint64_t enqueued_pkts;\n\t} rx __rte_cache_aligned;\n\n\tstruct {\n\t\tuint64_t dequeue_pkts;\n\t\tuint64_t tx_pkts;\n\t} tx __rte_cache_aligned;\n} app_stats;\n\nstatic const struct rte_eth_conf port_conf_default = {\n\t.rxmode = {\n\t\t.mq_mode = ETH_MQ_RX_RSS,\n\t\t.max_rx_pkt_len = ETHER_MAX_LEN,\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n\t.rx_adv_conf = {\n\t\t.rss_conf = {\n\t\t\t.rss_hf = ETH_RSS_IP | ETH_RSS_UDP |\n\t\t\t\tETH_RSS_TCP | ETH_RSS_SCTP,\n\t\t}\n\t},\n};\n\nstruct output_buffer {\n\tunsigned count;\n\tstruct rte_mbuf *mbufs[BURST_SIZE];\n};\n\n/*\n * Initialises a given port using global settings and with the rx buffers\n * coming from the mbuf_pool passed as parameter\n */\nstatic inline int\nport_init(uint8_t port, struct rte_mempool *mbuf_pool)\n{\n\tstruct rte_eth_conf port_conf = port_conf_default;\n\tconst uint16_t rxRings = 1, txRings = rte_lcore_count() - 1;\n\tint retval;\n\tuint16_t q;\n\n\tif (port >= rte_eth_dev_count())\n\t\treturn -1;\n\n\tretval = rte_eth_dev_configure(port, rxRings, txRings, &port_conf);\n\tif (retval != 0)\n\t\treturn retval;\n\n\tfor (q = 0; q < rxRings; q++) {\n\t\tretval = rte_eth_rx_queue_setup(port, q, RX_RING_SIZE,\n\t\t\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\t\t\tNULL, mbuf_pool);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\tfor (q = 0; q < txRings; q++) {\n\t\tretval = rte_eth_tx_queue_setup(port, q, TX_RING_SIZE,\n\t\t\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\t\t\tNULL);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\tretval = rte_eth_dev_start(port);\n\tif (retval < 0)\n\t\treturn retval;\n\n\tstruct rte_eth_link link;\n\trte_eth_link_get_nowait(port, &link);\n\tif (!link.link_status) {\n\t\tsleep(1);\n\t\trte_eth_link_get_nowait(port, &link);\n\t}\n\n\tif (!link.link_status) {\n\t\tprintf(\"Link down on port %\"PRIu8\"\\n\", port);\n\t\treturn 0;\n\t}\n\n\tstruct ether_addr addr;\n\trte_eth_macaddr_get(port, &addr);\n\tprintf(\"Port %u MAC: %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\n\t\t\t\" %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\"\\n\",\n\t\t\t(unsigned)port,\n\t\t\taddr.addr_bytes[0], addr.addr_bytes[1],\n\t\t\taddr.addr_bytes[2], addr.addr_bytes[3],\n\t\t\taddr.addr_bytes[4], addr.addr_bytes[5]);\n\n\trte_eth_promiscuous_enable(port);\n\n\treturn 0;\n}\n\nstruct lcore_params {\n\tunsigned worker_id;\n\tstruct rte_distributor *d;\n\tstruct rte_ring *r;\n\tstruct rte_mempool *mem_pool;\n};\n\nstatic void\nquit_workers(struct rte_distributor *d, struct rte_mempool *p)\n{\n\tconst unsigned num_workers = rte_lcore_count() - 2;\n\tunsigned i;\n\tstruct rte_mbuf *bufs[num_workers];\n\trte_mempool_get_bulk(p, (void *)bufs, num_workers);\n\n\tfor (i = 0; i < num_workers; i++)\n\t\tbufs[i]->hash.rss = i << 1;\n\n\trte_distributor_process(d, bufs, num_workers);\n\trte_mempool_put_bulk(p, (void *)bufs, num_workers);\n}\n\nstatic int\nlcore_rx(struct lcore_params *p)\n{\n\tstruct rte_distributor *d = p->d;\n\tstruct rte_mempool *mem_pool = p->mem_pool;\n\tstruct rte_ring *r = p->r;\n\tconst uint8_t nb_ports = rte_eth_dev_count();\n\tconst int socket_id = rte_socket_id();\n\tuint8_t port;\n\n\tfor (port = 0; port < nb_ports; port++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << port)) == 0)\n\t\t\tcontinue;\n\n\t\tif (rte_eth_dev_socket_id(port) > 0 &&\n\t\t\t\trte_eth_dev_socket_id(port) != socket_id)\n\t\t\tprintf(\"WARNING, port %u is on remote NUMA node to \"\n\t\t\t\t\t\"RX thread.\\n\\tPerformance will not \"\n\t\t\t\t\t\"be optimal.\\n\", port);\n\t}\n\n\tprintf(\"\\nCore %u doing packet RX.\\n\", rte_lcore_id());\n\tport = 0;\n\twhile (!quit_signal_rx) {\n\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << port)) == 0) {\n\t\t\tif (++port == nb_ports)\n\t\t\t\tport = 0;\n\t\t\tcontinue;\n\t\t}\n\t\tstruct rte_mbuf *bufs[BURST_SIZE*2];\n\t\tconst uint16_t nb_rx = rte_eth_rx_burst(port, 0, bufs,\n\t\t\t\tBURST_SIZE);\n\t\tapp_stats.rx.rx_pkts += nb_rx;\n\n\t\trte_distributor_process(d, bufs, nb_rx);\n\t\tconst uint16_t nb_ret = rte_distributor_returned_pkts(d,\n\t\t\t\tbufs, BURST_SIZE*2);\n\t\tapp_stats.rx.returned_pkts += nb_ret;\n\t\tif (unlikely(nb_ret == 0))\n\t\t\tcontinue;\n\n\t\tuint16_t sent = rte_ring_enqueue_burst(r, (void *)bufs, nb_ret);\n\t\tapp_stats.rx.enqueued_pkts += sent;\n\t\tif (unlikely(sent < nb_ret)) {\n\t\t\tLOG_DEBUG(DISTRAPP, \"%s:Packet loss due to full ring\\n\", __func__);\n\t\t\twhile (sent < nb_ret)\n\t\t\t\trte_pktmbuf_free(bufs[sent++]);\n\t\t}\n\t\tif (++port == nb_ports)\n\t\t\tport = 0;\n\t}\n\trte_distributor_process(d, NULL, 0);\n\t/* flush distributor to bring to known state */\n\trte_distributor_flush(d);\n\t/* set worker & tx threads quit flag */\n\tquit_signal = 1;\n\t/*\n\t * worker threads may hang in get packet as\n\t * distributor process is not running, just make sure workers\n\t * get packets till quit_signal is actually been\n\t * received and they gracefully shutdown\n\t */\n\tquit_workers(d, mem_pool);\n\t/* rx thread should quit at last */\n\treturn 0;\n}\n\nstatic inline void\nflush_one_port(struct output_buffer *outbuf, uint8_t outp)\n{\n\tunsigned nb_tx = rte_eth_tx_burst(outp, 0, outbuf->mbufs,\n\t\t\toutbuf->count);\n\tapp_stats.tx.tx_pkts += nb_tx;\n\n\tif (unlikely(nb_tx < outbuf->count)) {\n\t\tLOG_DEBUG(DISTRAPP, \"%s:Packet loss with tx_burst\\n\", __func__);\n\t\tdo {\n\t\t\trte_pktmbuf_free(outbuf->mbufs[nb_tx]);\n\t\t} while (++nb_tx < outbuf->count);\n\t}\n\toutbuf->count = 0;\n}\n\nstatic inline void\nflush_all_ports(struct output_buffer *tx_buffers, uint8_t nb_ports)\n{\n\tuint8_t outp;\n\tfor (outp = 0; outp < nb_ports; outp++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << outp)) == 0)\n\t\t\tcontinue;\n\n\t\tif (tx_buffers[outp].count == 0)\n\t\t\tcontinue;\n\n\t\tflush_one_port(&tx_buffers[outp], outp);\n\t}\n}\n\nstatic int\nlcore_tx(struct rte_ring *in_r)\n{\n\tstatic struct output_buffer tx_buffers[RTE_MAX_ETHPORTS];\n\tconst uint8_t nb_ports = rte_eth_dev_count();\n\tconst int socket_id = rte_socket_id();\n\tuint8_t port;\n\n\tfor (port = 0; port < nb_ports; port++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << port)) == 0)\n\t\t\tcontinue;\n\n\t\tif (rte_eth_dev_socket_id(port) > 0 &&\n\t\t\t\trte_eth_dev_socket_id(port) != socket_id)\n\t\t\tprintf(\"WARNING, port %u is on remote NUMA node to \"\n\t\t\t\t\t\"TX thread.\\n\\tPerformance will not \"\n\t\t\t\t\t\"be optimal.\\n\", port);\n\t}\n\n\tprintf(\"\\nCore %u doing packet TX.\\n\", rte_lcore_id());\n\twhile (!quit_signal) {\n\n\t\tfor (port = 0; port < nb_ports; port++) {\n\t\t\t/* skip ports that are not enabled */\n\t\t\tif ((enabled_port_mask & (1 << port)) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tstruct rte_mbuf *bufs[BURST_SIZE];\n\t\t\tconst uint16_t nb_rx = rte_ring_dequeue_burst(in_r,\n\t\t\t\t\t(void *)bufs, BURST_SIZE);\n\t\t\tapp_stats.tx.dequeue_pkts += nb_rx;\n\n\t\t\t/* if we get no traffic, flush anything we have */\n\t\t\tif (unlikely(nb_rx == 0)) {\n\t\t\t\tflush_all_ports(tx_buffers, nb_ports);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/* for traffic we receive, queue it up for transmit */\n\t\t\tuint16_t i;\n\t\t\t_mm_prefetch(bufs[0], 0);\n\t\t\t_mm_prefetch(bufs[1], 0);\n\t\t\t_mm_prefetch(bufs[2], 0);\n\t\t\tfor (i = 0; i < nb_rx; i++) {\n\t\t\t\tstruct output_buffer *outbuf;\n\t\t\t\tuint8_t outp;\n\t\t\t\t_mm_prefetch(bufs[i + 3], 0);\n\t\t\t\t/*\n\t\t\t\t * workers should update in_port to hold the\n\t\t\t\t * output port value\n\t\t\t\t */\n\t\t\t\toutp = bufs[i]->port;\n\t\t\t\t/* skip ports that are not enabled */\n\t\t\t\tif ((enabled_port_mask & (1 << outp)) == 0)\n\t\t\t\t\tcontinue;\n\n\t\t\t\toutbuf = &tx_buffers[outp];\n\t\t\t\toutbuf->mbufs[outbuf->count++] = bufs[i];\n\t\t\t\tif (outbuf->count == BURST_SIZE)\n\t\t\t\t\tflush_one_port(outbuf, outp);\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic void\nint_handler(int sig_num)\n{\n\tprintf(\"Exiting on signal %d\\n\", sig_num);\n\t/* set quit flag for rx thread to exit */\n\tquit_signal_rx = 1;\n}\n\nstatic void\nprint_stats(void)\n{\n\tstruct rte_eth_stats eth_stats;\n\tunsigned i;\n\n\tprintf(\"\\nRX thread stats:\\n\");\n\tprintf(\" - Received: %\"PRIu64\"\\n\", app_stats.rx.rx_pkts);\n\tprintf(\" - Processed: %\"PRIu64\"\\n\", app_stats.rx.returned_pkts);\n\tprintf(\" - Enqueued: %\"PRIu64\"\\n\", app_stats.rx.enqueued_pkts);\n\n\tprintf(\"\\nTX thread stats:\\n\");\n\tprintf(\" - Dequeued: %\"PRIu64\"\\n\", app_stats.tx.dequeue_pkts);\n\tprintf(\" - Transmitted: %\"PRIu64\"\\n\", app_stats.tx.tx_pkts);\n\n\tfor (i = 0; i < rte_eth_dev_count(); i++) {\n\t\trte_eth_stats_get(i, ð_stats);\n\t\tprintf(\"\\nPort %u stats:\\n\", i);\n\t\tprintf(\" - Pkts in: %\"PRIu64\"\\n\", eth_stats.ipackets);\n\t\tprintf(\" - Pkts out: %\"PRIu64\"\\n\", eth_stats.opackets);\n\t\tprintf(\" - In Errs: %\"PRIu64\"\\n\", eth_stats.ierrors);\n\t\tprintf(\" - Out Errs: %\"PRIu64\"\\n\", eth_stats.oerrors);\n\t\tprintf(\" - Mbuf Errs: %\"PRIu64\"\\n\", eth_stats.rx_nombuf);\n\t}\n}\n\nstatic int\nlcore_worker(struct lcore_params *p)\n{\n\tstruct rte_distributor *d = p->d;\n\tconst unsigned id = p->worker_id;\n\t/*\n\t * for single port, xor_val will be zero so we won't modify the output\n\t * port, otherwise we send traffic from 0 to 1, 2 to 3, and vice versa\n\t */\n\tconst unsigned xor_val = (rte_eth_dev_count() > 1);\n\tstruct rte_mbuf *buf = NULL;\n\n\tprintf(\"\\nCore %u acting as worker core.\\n\", rte_lcore_id());\n\twhile (!quit_signal) {\n\t\tbuf = rte_distributor_get_pkt(d, id, buf);\n\t\tbuf->port ^= xor_val;\n\t}\n\treturn 0;\n}\n\n/* display usage */\nstatic void\nprint_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK\\n\"\n\t\t\t\" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\",\n\t\t\tprgname);\n}\n\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:\",\n\t\t\tlgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind <= 1) {\n\t\tprint_usage(prgname);\n\t\treturn -1;\n\t}\n\n\targv[optind-1] = prgname;\n\n\toptind = 0; /* reset getopt lib */\n\treturn 0;\n}\n\n/* Main function, does initialization and calls the per-lcore functions */\nint\nmain(int argc, char *argv[])\n{\n\tstruct rte_mempool *mbuf_pool;\n\tstruct rte_distributor *d;\n\tstruct rte_ring *output_ring;\n\tunsigned lcore_id, worker_id = 0;\n\tunsigned nb_ports;\n\tuint8_t portid;\n\tuint8_t nb_ports_available;\n\n\t/* catch ctrl-c so we can print on exit */\n\tsignal(SIGINT, int_handler);\n\n\t/* init EAL */\n\tint ret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Error with EAL initialization\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid distributor parameters\\n\");\n\n\tif (rte_lcore_count() < 3)\n\t\trte_exit(EXIT_FAILURE, \"Error, This application needs at \"\n\t\t\t\t\"least 3 logical cores to run:\\n\"\n\t\t\t\t\"1 lcore for packet RX and distribution\\n\"\n\t\t\t\t\"1 lcore for packet TX\\n\"\n\t\t\t\t\"and at least 1 lcore for worker threads\\n\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports == 0)\n\t\trte_exit(EXIT_FAILURE, \"Error: no ethernet ports detected\\n\");\n\tif (nb_ports != 1 && (nb_ports & 1))\n\t\trte_exit(EXIT_FAILURE, \"Error: number of ports must be even, except \"\n\t\t\t\t\"when using a single port\\n\");\n\n\tmbuf_pool = rte_pktmbuf_pool_create(\"MBUF_POOL\",\n\t\tNUM_MBUFS * nb_ports, MBUF_CACHE_SIZE, 0,\n\t\tRTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\tif (mbuf_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create mbuf pool\\n\");\n\tnb_ports_available = nb_ports;\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"\\nSkipping disabled port %d\\n\", portid);\n\t\t\tnb_ports_available--;\n\t\t\tcontinue;\n\t\t}\n\t\t/* init port */\n\t\tprintf(\"Initializing port %u... done\\n\", (unsigned) portid);\n\n\t\tif (port_init(portid, mbuf_pool) != 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot initialize port %\"PRIu8\"\\n\",\n\t\t\t\t\tportid);\n\t}\n\n\tif (!nb_ports_available) {\n\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"All available ports are disabled. Please set portmask.\\n\");\n\t}\n\n\td = rte_distributor_create(\"PKT_DIST\", rte_socket_id(),\n\t\t\trte_lcore_count() - 2);\n\tif (d == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create distributor\\n\");\n\n\t/*\n\t * scheduler ring is read only by the transmitter core, but written to\n\t * by multiple threads\n\t */\n\toutput_ring = rte_ring_create(\"Output_ring\", RTE_RING_SZ,\n\t\t\trte_socket_id(), RING_F_SC_DEQ);\n\tif (output_ring == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create output ring\\n\");\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (worker_id == rte_lcore_count() - 2)\n\t\t\trte_eal_remote_launch((lcore_function_t *)lcore_tx,\n\t\t\t\t\toutput_ring, lcore_id);\n\t\telse {\n\t\t\tstruct lcore_params *p =\n\t\t\t\t\trte_malloc(NULL, sizeof(*p), 0);\n\t\t\tif (!p)\n\t\t\t\trte_panic(\"malloc failure\\n\");\n\t\t\t*p = (struct lcore_params){worker_id, d, output_ring, mbuf_pool};\n\n\t\t\trte_eal_remote_launch((lcore_function_t *)lcore_worker,\n\t\t\t\t\tp, lcore_id);\n\t\t}\n\t\tworker_id++;\n\t}\n\t/* call lcore_main on master core only */\n\tstruct lcore_params p = { 0, d, output_ring, mbuf_pool};\n\tlcore_rx(&p);\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\tprint_stats();\n\treturn 0;\n}\n" }, { "path": "examples/dpdk_qat/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2013 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\nifeq ($(ICP_ROOT),)\n$(error \"Please define ICP_ROOT environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifneq ($(CONFIG_RTE_EXEC_ENV),\"linuxapp\")\n$(error This application can only operate in a linuxapp environment, \\\nplease change the definition of the RTE_TARGET environment variable)\nendif\n\nLBITS := $(shell uname -p)\nifeq ($(CROSS_COMPILE),)\n ifneq ($(CONFIG_RTE_ARCH),\"x86_64\")\n ifneq ($(LBITS),i686)\n $(error The RTE_TARGET chosen is not compatible with this environment \\\n (x86_64), for this application. Please change the definition of the \\\n RTE_TARGET environment variable, or run the application on a 32-bit OS)\n endif\n endif\nendif\n\n# binary name\nAPP = dpdk_qat\n\n# all source are stored in SRCS-y\nSRCS-y := main.c crypto.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\nCFLAGS += -I$(ICP_ROOT)/quickassist/include \\\n\t\t-I$(ICP_ROOT)/quickassist/include/lac \\\n\t\t-I$(ICP_ROOT)/quickassist/lookaside/access_layer/include\n\n# From CRF 1.2 driver, library was renamed to libicp_qa_al.a\nifneq ($(wildcard $(ICP_ROOT)/build/icp_qa_al.a),)\nICP_LIBRARY_PATH = $(ICP_ROOT)/build/icp_qa_al.a\nelse\nICP_LIBRARY_PATH = $(ICP_ROOT)/build/libicp_qa_al.a\nendif\n\nLDLIBS += -L$(ICP_ROOT)/build\nLDLIBS += $(ICP_LIBRARY_PATH) \\\n -lz \\\n -losal \\\n -ladf_proxy \\\n -lcrypto\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/dpdk_qat/config_files/coleto/dh895xcc_qa_dev0.conf", "content": "[GENERAL]\nServicesEnabled = cy;dc\nConfigVersion = 2\ncyHmacAuthMode = 1\ndcTotalSRAMAvailable = 0\nFirmware_MofPath = dh895xcc/mof_firmware.bin\nFirmware_MmpPath = dh895xcc/mmp_firmware.bin\nstatsGeneral = 1\nstatsDc = 1\nstatsDh = 1\nstatsDrbg = 1\nstatsDsa = 1\nstatsEcc = 1\nstatsKeyGen = 1\nstatsLn = 1\nstatsPrime = 1\nstatsRsa = 1\nstatsSym = 1\nSRIOV_Enabled = 0\nProcDebug = 1\n\n[KERNEL]\nNumberCyInstances = 0\nNumberDcInstances = 0\n\n[SSL]\nNumberCyInstances = 8\nNumberDcInstances = 0\nNumProcesses = 1\nLimitDevAccess = 0\n\nCy0Name = \"SSL0\"\nCy0IsPolled = 1\nCy0CoreAffinity = 0\n\nCy1Name = \"SSL1\"\nCy1IsPolled = 1\nCy1CoreAffinity = 1\n\nCy2Name = \"SSL2\"\nCy2IsPolled = 1\nCy2CoreAffinity = 2\n\nCy3Name = \"SSL3\"\nCy3IsPolled = 1\nCy3CoreAffinity = 3\n\n\nCy4Name = \"SSL4\"\nCy4IsPolled = 1\nCy4CoreAffinity = 4\n\n\nCy5Name = \"SSL5\"\nCy5IsPolled = 1\nCy5CoreAffinity = 5\n\nCy6Name = \"SSL6\"\nCy6IsPolled = 1\nCy6CoreAffinity = 6\n\n\nCy7Name = \"SSL7\"\nCy7IsPolled = 1\nCy7CoreAffinity = 7\n" }, { "path": "examples/dpdk_qat/config_files/shumway/dh89xxcc_qa_dev0.conf", "content": "#########################################################################\n#\n# @par\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n# #########################################################################\n# ########################################################\n#\n# This file is the configuration for a single dh89xxcc_qa\n# device.\n#\n# Each device has up to two accelerators.\n# - The client may load balance between these\n# accelerators.\n# Each accelerator has 8 independent ring banks.\n# - The interrupt for each can be directed to a\n# specific core.\n# Each ring bank as 16 rings (hardware assisted queues).\n#\n#########################################################\n# General Section\n##############################################\n\n[GENERAL]\nServicesEnabled = cy0;cy1\n\n# Use version 2 of the config file\nConfigVersion = 2\n# Look Aside Cryptographic Configuration\ncyHmacAuthMode = 1\n\n# Look Aside Compression Configuration\ndcTotalSRAMAvailable = 0\n\n# Firmware Location Configuration\nFirmware_MofPath = mof_firmware.bin\nFirmware_MmpPath = mmp_firmware.bin\n\n#Default values for number of concurrent requests*/\nCyNumConcurrentSymRequests = 512\nCyNumConcurrentAsymRequests = 64\nDcNumConcurrentRequests = 512\n\n#Statistics, valid values: 1,0\nstatsGeneral = 1\nstatsDc = 1\nstatsDh = 1\nstatsDrbg = 1\nstatsDsa = 1\nstatsEcc = 1\nstatsKeyGen = 1\nstatsLn = 1\nstatsPrime = 1\nstatsRsa = 1\nstatsSym = 1\n\n# Enables or disables Single Root Complex IO Virtualization.\n# If this is enabled (1) then SRIOV and VT-d need to be enabled in\n# BIOS and there can be no Cy or Dc instances created in PF (Dom0).\n# If this i disabled (0) then SRIOV and VT-d need to be disabled\n# in BIOS and Cy and/or Dc instances can be used in PF (Dom0)\nSRIOV_Enabled = 0\n\n#Debug feature, if set to 1 it enables additional entries in /proc filesystem\nProcDebug = 1\n\n#######################################################\n#\n# Logical Instances Section\n# A logical instance allows each address domain\n# (kernel space and individual user space processes)\n# to configure rings (i.e. hardware assisted queues)\n# to be used by that address domain and to define the\n# behavior of that ring.\n#\n# The address domains are in the following format\n# - For kernel address domains\n# [KERNEL]\n# - For user process address domains\n# [xxxxx]\n# Where xxxxx may be any ascii value which uniquely identifies\n# the user mode process.\n# To allow the driver correctly configure the\n# logical instances associated with this user process,\n# the process must call the icp_sal_userStartMultiProcess(...)\n# passing the xxxxx string during process initialisation.\n# When the user space process is finished it must call\n# icp_sal_userStop(...) to free resources.\n# NumProcesses will indicate the maximum number of processes\n# that can call icp_sal_userStartMultiProcess on this instance.\n# Warning: the resources are preallocated: if NumProcesses\n# is too high, the driver will fail to load\n#\n# Items configurable by a logical instance are:\n# - Name of the logical instance\n# - The accelerator associated with this logical\n# instance\n# - The core the instance is affinitized to (optional)\n#\n# Note: Logical instances may not share the same ring, but\n# may share a ring bank.\n#\n# The format of the logical instances are:\n# - For crypto:\n# CyName = \"xxxx\"\n# CyAcceleratorNumber = 0-3\n# CyCoreAffinity = 0-7\n#\n# - For Data Compression\n# DcName = \"xxxx\"\n# DcAcceleratorNumber = 0-1\n# DcCoreAffinity = 0-7\n#\n# Where:\n# - n is the number of this logical instance starting at 0.\n# - xxxx may be any ascii value which identifies the logical instance.\n#\n# Note: for user space processes, a list of values can be specified for\n# the accelerator number and the core affinity: for example\n# Cy0AcceleratorNumber = 0,2\n# Cy0CoreAffinity = 0,2,4\n# These comma-separated lists will allow the multiple processes to use\n# different accelerators and cores, and will wrap around the numbers\n# in the list. In the above example, process 0 will use accelerator 0,\n# and process 1 will use accelerator 2\n#\n########################################################\n\n##############################################\n# Kernel Instances Section\n##############################################\n[KERNEL]\nNumberCyInstances = 0\nNumberDcInstances = 0\n\n##############################################\n# User Process Instance Section\n##############################################\n[SSL]\nNumberCyInstances = 16\nNumberDcInstances = 0\nNumProcesses = 1\nLimitDevAccess = 0\n\n# Crypto - User instance #0\nCy0Name = \"SSL0\"\nCy0IsPolled = 1\nCy0AcceleratorNumber = 0\n# List of core affinities\nCy0CoreAffinity = 0\n\n# Crypto - User instance #1\nCy1Name = \"SSL1\"\nCy1IsPolled = 1\nCy1AcceleratorNumber = 1\n# List of core affinities\nCy1CoreAffinity = 1\n\n# Crypto - User instance #2\nCy2Name = \"SSL2\"\nCy2IsPolled = 1\nCy2AcceleratorNumber = 2\n# List of core affinities\nCy2CoreAffinity = 2\n\n# Crypto - User instance #3\nCy3Name = \"SSL3\"\nCy3IsPolled = 1\nCy3AcceleratorNumber = 3\n# List of core affinities\nCy3CoreAffinity = 3\n\n# Crypto - User instance #4\nCy4Name = \"SSL4\"\nCy4IsPolled = 1\nCy4AcceleratorNumber = 0\n# List of core affinities\nCy4CoreAffinity = 4\n\n# Crypto - User instance #5\nCy5Name = \"SSL5\"\nCy5IsPolled = 1\nCy5AcceleratorNumber = 1\n# List of core affinities\nCy5CoreAffinity = 5\n\n# Crypto - User instance #6\nCy6Name = \"SSL6\"\nCy6IsPolled = 1\nCy6AcceleratorNumber = 2\n# List of core affinities\nCy6CoreAffinity = 6\n\n# Crypto - User instance #7\nCy7Name = \"SSL7\"\nCy7IsPolled = 1\nCy7AcceleratorNumber = 3\n# List of core affinities\nCy7CoreAffinity = 7\n\n# Crypto - User instance #8\nCy8Name = \"SSL8\"\nCy8IsPolled = 1\nCy8AcceleratorNumber = 0\n# List of core affinities\nCy8CoreAffinity = 16\n\n# Crypto - User instance #9\nCy9Name = \"SSL9\"\nCy9IsPolled = 1\nCy9AcceleratorNumber = 1\n# List of core affinities\nCy9CoreAffinity = 17\n\n# Crypto - User instance #10\nCy10Name = \"SSL10\"\nCy10IsPolled = 1\nCy10AcceleratorNumber = 2\n# List of core affinities\nCy10CoreAffinity = 18\n\n# Crypto - User instance #11\nCy11Name = \"SSL11\"\nCy11IsPolled = 1\nCy11AcceleratorNumber = 3\n# List of core affinities\nCy11CoreAffinity = 19\n\n# Crypto - User instance #12\nCy12Name = \"SSL12\"\nCy12IsPolled = 1\nCy12AcceleratorNumber = 0\n# List of core affinities\nCy12CoreAffinity = 20\n\n# Crypto - User instance #13\nCy13Name = \"SSL13\"\nCy13IsPolled = 1\nCy13AcceleratorNumber = 1\n# List of core affinities\nCy13CoreAffinity = 21\n\n# Crypto - User instance #14\nCy14Name = \"SSL14\"\nCy14IsPolled = 1\nCy14AcceleratorNumber = 2\n# List of core affinities\nCy14CoreAffinity = 22\n\n# Crypto - User instance #15\nCy15Name = \"SSL15\"\nCy15IsPolled = 1\nCy15AcceleratorNumber = 3\n# List of core affinities\nCy15CoreAffinity = 23\n\n\n\n##############################################\n# Wireless Process Instance Section\n##############################################\n[WIRELESS]\nNumberCyInstances = 0\nNumberDcInstances = 0\nNumProcesses = 0\n" }, { "path": "examples/dpdk_qat/config_files/shumway/dh89xxcc_qa_dev1.conf", "content": "#########################################################################\n#\n# @par\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n# #########################################################################\n# ########################################################\n#\n# This file is the configuration for a single dh89xxcc_qa\n# device.\n#\n# Each device has up to two accelerators.\n# - The client may load balance between these\n# accelerators.\n# Each accelerator has 8 independent ring banks.\n# - The interrupt for each can be directed to a\n# specific core.\n# Each ring bank as 16 rings (hardware assisted queues).\n#\n#########################################################\n# General Section\n##############################################\n\n[GENERAL]\nServicesEnabled = cy0;cy1\n\n# Use version 2 of the config file\nConfigVersion = 2\n# Look Aside Cryptographic Configuration\ncyHmacAuthMode = 1\n\n# Look Aside Compression Configuration\ndcTotalSRAMAvailable = 0\n\n# Firmware Location Configuration\nFirmware_MofPath = mof_firmware.bin\nFirmware_MmpPath = mmp_firmware.bin\n\n#Default values for number of concurrent requests*/\nCyNumConcurrentSymRequests = 512\nCyNumConcurrentAsymRequests = 64\nDcNumConcurrentRequests = 512\n\n#Statistics, valid values: 1,0\nstatsGeneral = 1\nstatsDc = 1\nstatsDh = 1\nstatsDrbg = 1\nstatsDsa = 1\nstatsEcc = 1\nstatsKeyGen = 1\nstatsLn = 1\nstatsPrime = 1\nstatsRsa = 1\nstatsSym = 1\n\n# Enables or disables Single Root Complex IO Virtualization.\n# If this is enabled (1) then SRIOV and VT-d need to be enabled in\n# BIOS and there can be no Cy or Dc instances created in PF (Dom0).\n# If this i disabled (0) then SRIOV and VT-d need to be disabled\n# in BIOS and Cy and/or Dc instances can be used in PF (Dom0)\nSRIOV_Enabled = 0\n\n#Debug feature, if set to 1 it enables additional entries in /proc filesystem\nProcDebug = 1\n\n#######################################################\n#\n# Logical Instances Section\n# A logical instance allows each address domain\n# (kernel space and individual user space processes)\n# to configure rings (i.e. hardware assisted queues)\n# to be used by that address domain and to define the\n# behavior of that ring.\n#\n# The address domains are in the following format\n# - For kernel address domains\n# [KERNEL]\n# - For user process address domains\n# [xxxxx]\n# Where xxxxx may be any ascii value which uniquely identifies\n# the user mode process.\n# To allow the driver correctly configure the\n# logical instances associated with this user process,\n# the process must call the icp_sal_userStartMultiProcess(...)\n# passing the xxxxx string during process initialisation.\n# When the user space process is finished it must call\n# icp_sal_userStop(...) to free resources.\n# NumProcesses will indicate the maximum number of processes\n# that can call icp_sal_userStartMultiProcess on this instance.\n# Warning: the resources are preallocated: if NumProcesses\n# is too high, the driver will fail to load\n#\n# Items configurable by a logical instance are:\n# - Name of the logical instance\n# - The accelerator associated with this logical\n# instance\n# - The core the instance is affinitized to (optional)\n#\n# Note: Logical instances may not share the same ring, but\n# may share a ring bank.\n#\n# The format of the logical instances are:\n# - For crypto:\n# CyName = \"xxxx\"\n# CyAcceleratorNumber = 0-3\n# CyCoreAffinity = 0-7\n#\n# - For Data Compression\n# DcName = \"xxxx\"\n# DcAcceleratorNumber = 0-1\n# DcCoreAffinity = 0-7\n#\n# Where:\n# - n is the number of this logical instance starting at 0.\n# - xxxx may be any ascii value which identifies the logical instance.\n#\n# Note: for user space processes, a list of values can be specified for\n# the accelerator number and the core affinity: for example\n# Cy0AcceleratorNumber = 0,2\n# Cy0CoreAffinity = 0,2,4\n# These comma-separated lists will allow the multiple processes to use\n# different accelerators and cores, and will wrap around the numbers\n# in the list. In the above example, process 0 will use accelerator 0,\n# and process 1 will use accelerator 2\n#\n########################################################\n\n##############################################\n# Kernel Instances Section\n##############################################\n[KERNEL]\nNumberCyInstances = 0\nNumberDcInstances = 0\n\n##############################################\n# User Process Instance Section\n##############################################\n[SSL]\nNumberCyInstances = 16\nNumberDcInstances = 0\nNumProcesses = 1\nLimitDevAccess = 0\n\n# Crypto - User instance #0\nCy0Name = \"SSL0\"\nCy0IsPolled = 1\nCy0AcceleratorNumber = 0\n# List of core affinities\nCy0CoreAffinity = 8\n\n# Crypto - User instance #1\nCy1Name = \"SSL1\"\nCy1IsPolled = 1\nCy1AcceleratorNumber = 1\n# List of core affinities\nCy1CoreAffinity = 9\n\n# Crypto - User instance #2\nCy2Name = \"SSL2\"\nCy2IsPolled = 1\nCy2AcceleratorNumber = 2\n# List of core affinities\nCy2CoreAffinity = 10\n\n# Crypto - User instance #3\nCy3Name = \"SSL3\"\nCy3IsPolled = 1\nCy3AcceleratorNumber = 3\n# List of core affinities\nCy3CoreAffinity = 11\n\n# Crypto - User instance #4\nCy4Name = \"SSL4\"\nCy4IsPolled = 1\nCy4AcceleratorNumber = 0\n# List of core affinities\nCy4CoreAffinity = 12\n\n# Crypto - User instance #5\nCy5Name = \"SSL5\"\nCy5IsPolled = 1\nCy5AcceleratorNumber = 1\n# List of core affinities\nCy5CoreAffinity = 13\n\n# Crypto - User instance #6\nCy6Name = \"SSL6\"\nCy6IsPolled = 1\nCy6AcceleratorNumber = 2\n# List of core affinities\nCy6CoreAffinity = 14\n\n# Crypto - User instance #7\nCy7Name = \"SSL7\"\nCy7IsPolled = 1\nCy7AcceleratorNumber = 3\n# List of core affinities\nCy7CoreAffinity = 15\n\n# Crypto - User instance #8\nCy8Name = \"SSL8\"\nCy8IsPolled = 1\nCy8AcceleratorNumber = 0\n# List of core affinities\nCy8CoreAffinity = 24\n\n# Crypto - User instance #9\nCy9Name = \"SSL9\"\nCy9IsPolled = 1\nCy9AcceleratorNumber = 1\n# List of core affinities\nCy9CoreAffinity = 25\n\n# Crypto - User instance #10\nCy10Name = \"SSL10\"\nCy10IsPolled = 1\nCy10AcceleratorNumber = 2\n# List of core affinities\nCy10CoreAffinity = 26\n\n# Crypto - User instance #11\nCy11Name = \"SSL11\"\nCy11IsPolled = 1\nCy11AcceleratorNumber = 3\n# List of core affinities\nCy11CoreAffinity = 27\n\n# Crypto - User instance #12\nCy12Name = \"SSL12\"\nCy12IsPolled = 1\nCy12AcceleratorNumber = 0\n# List of core affinities\nCy12CoreAffinity = 28\n\n# Crypto - User instance #13\nCy13Name = \"SSL13\"\nCy13IsPolled = 1\nCy13AcceleratorNumber = 1\n# List of core affinities\nCy13CoreAffinity = 29\n\n# Crypto - User instance #14\nCy14Name = \"SSL14\"\nCy14IsPolled = 1\nCy14AcceleratorNumber = 2\n# List of core affinities\nCy14CoreAffinity = 30\n\n# Crypto - User instance #15\nCy15Name = \"SSL15\"\nCy15IsPolled = 1\nCy15AcceleratorNumber = 3\n# List of core affinities\nCy15CoreAffinity = 31\n\n\n##############################################\n# Wireless Process Instance Section\n##############################################\n[WIRELESS]\nNumberCyInstances = 0\nNumberDcInstances = 0\nNumProcesses = 0\n" }, { "path": "examples/dpdk_qat/config_files/stargo/dh89xxcc_qa_dev0.conf", "content": "#########################################################################\n#\n# @par\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n# #########################################################################\n# ########################################################\n#\n# This file is the configuration for a single dh89xxcc_qa\n# device.\n#\n# Each device has up to two accelerators.\n# - The client may load balance between these\n# accelerators.\n# Each accelerator has 8 independent ring banks.\n# - The interrupt for each can be directed to a\n# specific core.\n# Each ring bank as 16 rings (hardware assisted queues).\n#\n#########################################################\n# General Section\n##############################################\n\n[GENERAL]\nServicesEnabled = cy0;cy1\n\n# Use version 2 of the config file\nConfigVersion = 2\n# Look Aside Cryptographic Configuration\ncyHmacAuthMode = 1\n\n# Look Aside Compression Configuration\ndcTotalSRAMAvailable = 0\n\n# Firmware Location Configuration\nFirmware_MofPath = mof_firmware.bin\nFirmware_MmpPath = mmp_firmware.bin\n\n#Default values for number of concurrent requests*/\nCyNumConcurrentSymRequests = 512\nCyNumConcurrentAsymRequests = 64\nDcNumConcurrentRequests = 512\n\n#Statistics, valid values: 1,0\nstatsGeneral = 1\nstatsDc = 1\nstatsDh = 1\nstatsDrbg = 1\nstatsDsa = 1\nstatsEcc = 1\nstatsKeyGen = 1\nstatsLn = 1\nstatsPrime = 1\nstatsRsa = 1\nstatsSym = 1\n\n# Enables or disables Single Root Complex IO Virtualization.\n# If this is enabled (1) then SRIOV and VT-d need to be enabled in\n# BIOS and there can be no Cy or Dc instances created in PF (Dom0).\n# If this i disabled (0) then SRIOV and VT-d need to be disabled\n# in BIOS and Cy and/or Dc instances can be used in PF (Dom0)\nSRIOV_Enabled = 0\n\n#Debug feature, if set to 1 it enables additional entries in /proc filesystem\nProcDebug = 1\n\n#######################################################\n#\n# Logical Instances Section\n# A logical instance allows each address domain\n# (kernel space and individual user space processes)\n# to configure rings (i.e. hardware assisted queues)\n# to be used by that address domain and to define the\n# behavior of that ring.\n#\n# The address domains are in the following format\n# - For kernel address domains\n# [KERNEL]\n# - For user process address domains\n# [xxxxx]\n# Where xxxxx may be any ascii value which uniquely identifies\n# the user mode process.\n# To allow the driver correctly configure the\n# logical instances associated with this user process,\n# the process must call the icp_sal_userStartMultiProcess(...)\n# passing the xxxxx string during process initialisation.\n# When the user space process is finished it must call\n# icp_sal_userStop(...) to free resources.\n# NumProcesses will indicate the maximum number of processes\n# that can call icp_sal_userStartMultiProcess on this instance.\n# Warning: the resources are preallocated: if NumProcesses\n# is too high, the driver will fail to load\n#\n# Items configurable by a logical instance are:\n# - Name of the logical instance\n# - The accelerator associated with this logical\n# instance\n# - The core the instance is affinitized to (optional)\n#\n# Note: Logical instances may not share the same ring, but\n# may share a ring bank.\n#\n# The format of the logical instances are:\n# - For crypto:\n# CyName = \"xxxx\"\n# CyAcceleratorNumber = 0-3\n# CyCoreAffinity = 0-7\n#\n# - For Data Compression\n# DcName = \"xxxx\"\n# DcAcceleratorNumber = 0-1\n# DcCoreAffinity = 0-7\n#\n# Where:\n# - n is the number of this logical instance starting at 0.\n# - xxxx may be any ascii value which identifies the logical instance.\n#\n# Note: for user space processes, a list of values can be specified for\n# the accelerator number and the core affinity: for example\n# Cy0AcceleratorNumber = 0,2\n# Cy0CoreAffinity = 0,2,4\n# These comma-separated lists will allow the multiple processes to use\n# different accelerators and cores, and will wrap around the numbers\n# in the list. In the above example, process 0 will use accelerator 0,\n# and process 1 will use accelerator 2\n#\n########################################################\n\n##############################################\n# Kernel Instances Section\n##############################################\n[KERNEL]\nNumberCyInstances = 0\nNumberDcInstances = 0\n\n##############################################\n# User Process Instance Section\n##############################################\n[SSL]\nNumberCyInstances = 8\nNumberDcInstances = 0\nNumProcesses = 1\nLimitDevAccess = 0\n\n# Crypto - User instance #0\nCy0Name = \"SSL0\"\nCy0IsPolled = 1\nCy0AcceleratorNumber = 0\n# List of core affinities\nCy0CoreAffinity = 0\n\n# Crypto - User instance #1\nCy1Name = \"SSL1\"\nCy1IsPolled = 1\nCy1AcceleratorNumber = 1\n# List of core affinities\nCy1CoreAffinity = 1\n\n# Crypto - User instance #2\nCy2Name = \"SSL2\"\nCy2IsPolled = 1\nCy2AcceleratorNumber = 2\n# List of core affinities\nCy2CoreAffinity = 2\n\n# Crypto - User instance #3\nCy3Name = \"SSL3\"\nCy3IsPolled = 1\nCy3AcceleratorNumber = 3\n# List of core affinities\nCy3CoreAffinity = 3\n\n# Crypto - User instance #4\nCy4Name = \"SSL4\"\nCy4IsPolled = 1\nCy4AcceleratorNumber = 0\n# List of core affinities\nCy4CoreAffinity = 4\n\n# Crypto - User instance #5\nCy5Name = \"SSL5\"\nCy5IsPolled = 1\nCy5AcceleratorNumber = 1\n# List of core affinities\nCy5CoreAffinity = 5\n\n# Crypto - User instance #6\nCy6Name = \"SSL6\"\nCy6IsPolled = 1\nCy6AcceleratorNumber = 2\n# List of core affinities\nCy6CoreAffinity = 6\n\n# Crypto - User instance #7\nCy7Name = \"SSL7\"\nCy7IsPolled = 1\nCy7AcceleratorNumber = 3\n# List of core affinities\nCy7CoreAffinity = 7\n\n##############################################\n# Wireless Process Instance Section\n##############################################\n[WIRELESS]\nNumberCyInstances = 0\nNumberDcInstances = 0\nNumProcesses = 0\n" }, { "path": "examples/dpdk_qat/crypto.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define CPA_CY_SYM_DP_TMP_WORKAROUND 1\n\n#include \"cpa.h\"\n#include \"cpa_types.h\"\n#include \"cpa_cy_sym_dp.h\"\n#include \"cpa_cy_common.h\"\n#include \"cpa_cy_im.h\"\n#include \"icp_sal_user.h\"\n#include \"icp_sal_poll.h\"\n\n#include \"crypto.h\"\n\n/* CIPHER KEY LENGTHS */\n#define KEY_SIZE_64_IN_BYTES\t(64 / 8)\n#define KEY_SIZE_56_IN_BYTES\t(56 / 8)\n#define KEY_SIZE_128_IN_BYTES\t(128 / 8)\n#define KEY_SIZE_168_IN_BYTES\t(168 / 8)\n#define KEY_SIZE_192_IN_BYTES\t(192 / 8)\n#define KEY_SIZE_256_IN_BYTES\t(256 / 8)\n\n/* HMAC AUTH KEY LENGTHS */\n#define AES_XCBC_AUTH_KEY_LENGTH_IN_BYTES\t(128 / 8)\n#define SHA1_AUTH_KEY_LENGTH_IN_BYTES\t\t(160 / 8)\n#define SHA224_AUTH_KEY_LENGTH_IN_BYTES\t\t(224 / 8)\n#define SHA256_AUTH_KEY_LENGTH_IN_BYTES\t\t(256 / 8)\n#define SHA384_AUTH_KEY_LENGTH_IN_BYTES\t\t(384 / 8)\n#define SHA512_AUTH_KEY_LENGTH_IN_BYTES\t\t(512 / 8)\n#define MD5_AUTH_KEY_LENGTH_IN_BYTES\t\t(128 / 8)\n#define KASUMI_AUTH_KEY_LENGTH_IN_BYTES\t\t(128 / 8)\n\n/* HASH DIGEST LENGHTS */\n#define AES_XCBC_DIGEST_LENGTH_IN_BYTES\t\t(128 / 8)\n#define AES_XCBC_96_DIGEST_LENGTH_IN_BYTES\t(96 / 8)\n#define MD5_DIGEST_LENGTH_IN_BYTES\t\t(128 / 8)\n#define SHA1_DIGEST_LENGTH_IN_BYTES\t\t(160 / 8)\n#define SHA1_96_DIGEST_LENGTH_IN_BYTES\t\t(96 / 8)\n#define SHA224_DIGEST_LENGTH_IN_BYTES\t\t(224 / 8)\n#define SHA256_DIGEST_LENGTH_IN_BYTES\t\t(256 / 8)\n#define SHA384_DIGEST_LENGTH_IN_BYTES\t\t(384 / 8)\n#define SHA512_DIGEST_LENGTH_IN_BYTES\t\t(512 / 8)\n#define KASUMI_DIGEST_LENGTH_IN_BYTES\t\t(32 / 8)\n\n#define IV_LENGTH_16_BYTES\t(16)\n#define IV_LENGTH_8_BYTES\t(8)\n\n\n/*\n * rte_memzone is used to allocate physically contiguous virtual memory.\n * In this application we allocate a single block and divide between variables\n * which require a virtual to physical mapping for use by the QAT driver.\n * Virt2phys is only performed during initialisation and not on the data-path.\n */\n\n#define LCORE_MEMZONE_SIZE\t(1 << 22)\n\nstruct lcore_memzone\n{\n\tconst struct rte_memzone *memzone;\n\tvoid *next_free_address;\n};\n\n/*\n * Size the qa software response queue.\n * Note: Head and Tail are 8 bit, therefore, the queue is\n * fixed to 256 entries.\n */\n#define CRYPTO_SOFTWARE_QUEUE_SIZE 256\n\nstruct qa_callbackQueue {\n\tuint8_t head;\n\tuint8_t tail;\n\tuint16_t numEntries;\n\tstruct rte_mbuf *qaCallbackRing[CRYPTO_SOFTWARE_QUEUE_SIZE];\n};\n\nstruct qa_core_conf {\n\tCpaCySymDpSessionCtx *encryptSessionHandleTbl[NUM_CRYPTO][NUM_HMAC];\n\tCpaCySymDpSessionCtx *decryptSessionHandleTbl[NUM_CRYPTO][NUM_HMAC];\n\tCpaInstanceHandle instanceHandle;\n\tstruct qa_callbackQueue callbackQueue;\n\tuint64_t qaOutstandingRequests;\n\tuint64_t numResponseAttempts;\n\tuint8_t kickFreq;\n\tvoid *pPacketIV;\n\tCpaPhysicalAddr packetIVPhy;\n\tstruct lcore_memzone lcoreMemzone;\n} __rte_cache_aligned;\n\n#define MAX_CORES (RTE_MAX_LCORE)\n\nstatic struct qa_core_conf qaCoreConf[MAX_CORES];\n\n/*\n *Create maximum possible key size,\n *One for cipher and one for hash\n */\nstruct glob_keys {\n\tuint8_t cipher_key[32];\n\tuint8_t hash_key[64];\n\tuint8_t iv[16];\n};\n\nstruct glob_keys g_crypto_hash_keys = {\n\t.cipher_key = {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,\n\t\t0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,\n\t\t0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,\n\t\t0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x20},\n\t.hash_key = {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,\n\t\t0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,\n\t\t0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,\n\t\t0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x20,\n\t\t0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,\n\t\t0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,\n\t\t0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,\n\t\t0x39,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,0x50},\n\t.iv = {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,\n\t\t0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10}\n};\n\n/*\n * Offsets from the start of the packet.\n *\n */\n#define PACKET_DATA_START_PHYS(p) \\\n\t\t((p)->buf_physaddr + (p)->data_off)\n\n/*\n * A fixed offset to where the crypto is to be performed, which is the first\n * byte after the Ethernet(14 bytes) and IPv4 headers(20 bytes)\n */\n#define CRYPTO_START_OFFSET\t\t(14+20)\n#define HASH_START_OFFSET\t\t(14+20)\n#define CIPHER_BLOCK_DEFAULT_SIZE\t(16)\n#define HASH_BLOCK_DEFAULT_SIZE\t\t(16)\n\n/*\n * Offset to the opdata from the start of the data portion of packet.\n * Assumption: The buffer is physically contiguous.\n * +18 takes this to the next cache line.\n */\n\n#define CRYPTO_OFFSET_TO_OPDATA\t\t(ETHER_MAX_LEN+18)\n\n/*\n * Default number of requests to place on the hardware ring before kicking the\n * ring pointers.\n */\n#define CRYPTO_BURST_TX\t(16)\n\n/*\n * Only call the qa poll function when the number responses in the software\n * queue drops below this number.\n */\n#define CRYPTO_QUEUED_RESP_POLL_THRESHOLD\t(32)\n\n/*\n * Limit the number of polls per call to get_next_response.\n */\n#define GET_NEXT_RESPONSE_FREQ\t(32)\n\n/*\n * Max number of responses to pull from the qa in one poll.\n */\n#define CRYPTO_MAX_RESPONSE_QUOTA \\\n\t\t(CRYPTO_SOFTWARE_QUEUE_SIZE-CRYPTO_QUEUED_RESP_POLL_THRESHOLD-1)\n\n#if (CRYPTO_QUEUED_RESP_POLL_THRESHOLD + CRYPTO_MAX_RESPONSE_QUOTA >= \\\n\t\tCRYPTO_SOFTWARE_QUEUE_SIZE)\n#error Its possible to overflow the qa response Q with current poll and \\\n\t\tresponse quota.\n#endif\n\nstatic void\ncrypto_callback(CpaCySymDpOpData *pOpData,\n\t\t__rte_unused CpaStatus status,\n\t\t__rte_unused CpaBoolean verifyResult)\n{\n\tuint32_t lcore_id;\n\tlcore_id = rte_lcore_id();\n\tstruct qa_callbackQueue *callbackQ = &(qaCoreConf[lcore_id].callbackQueue);\n\n\t/*\n\t * Received a completion from the QA hardware.\n\t * Place the response on the return queue.\n\t */\n\tcallbackQ->qaCallbackRing[callbackQ->head] = pOpData->pCallbackTag;\n\tcallbackQ->head++;\n\tcallbackQ->numEntries++;\n\tqaCoreConf[lcore_id].qaOutstandingRequests--;\n}\n\nstatic void\nqa_crypto_callback(CpaCySymDpOpData *pOpData, CpaStatus status,\n\t\tCpaBoolean verifyResult)\n{\n\tcrypto_callback(pOpData, status, verifyResult);\n}\n\n/*\n * Each allocation from a particular memzone lasts for the life-time of\n * the application. No freeing of previous allocations will occur.\n */\nstatic void *\nalloc_memzone_region(uint32_t length, uint32_t lcore_id)\n{\n\tchar *current_free_addr_ptr = NULL;\n\tstruct lcore_memzone *lcore_memzone = &(qaCoreConf[lcore_id].lcoreMemzone);\n\n\tcurrent_free_addr_ptr = lcore_memzone->next_free_address;\n\n\tif (current_free_addr_ptr + length >=\n\t\t(char *)lcore_memzone->memzone->addr + lcore_memzone->memzone->len) {\n\t\tprintf(\"Crypto: No memory available in memzone\\n\");\n\t\treturn NULL;\n\t}\n\tlcore_memzone->next_free_address = current_free_addr_ptr + length;\n\n\treturn (void *)current_free_addr_ptr;\n}\n\n/*\n * Virtual to Physical Address translation is only executed during initialization\n * and not on the data-path.\n */\nstatic CpaPhysicalAddr\nqa_v2p(void *ptr)\n{\n\tconst struct rte_memzone *memzone = NULL;\n\tuint32_t lcore_id = 0;\n\tRTE_LCORE_FOREACH(lcore_id) {\n\t\tmemzone = qaCoreConf[lcore_id].lcoreMemzone.memzone;\n\n\t\tif ((char*) ptr >= (char *) memzone->addr &&\n\t\t\t\t(char*) ptr < ((char*) memzone->addr + memzone->len)) {\n\t\t\treturn (CpaPhysicalAddr)\n\t\t\t\t\t(memzone->phys_addr + ((char *) ptr - (char*) memzone->addr));\n\t\t}\n\t}\n\tprintf(\"Crypto: Corresponding physical address not found in memzone\\n\");\n\treturn (CpaPhysicalAddr) 0;\n}\n\nstatic CpaStatus\ngetCoreAffinity(Cpa32U *coreAffinity, const CpaInstanceHandle instanceHandle)\n{\n\tCpaInstanceInfo2 info;\n\tCpa16U i = 0;\n\tCpaStatus status = CPA_STATUS_SUCCESS;\n\n\tbzero(&info, sizeof(CpaInstanceInfo2));\n\n\tstatus = cpaCyInstanceGetInfo2(instanceHandle, &info);\n\tif (CPA_STATUS_SUCCESS != status) {\n\t\tprintf(\"Crypto: Error getting instance info\\n\");\n\t\treturn CPA_STATUS_FAIL;\n\t}\n\tfor (i = 0; i < MAX_CORES; i++) {\n\t\tif (CPA_BITMAP_BIT_TEST(info.coreAffinity, i)) {\n\t\t\t*coreAffinity = i;\n\t\t\treturn CPA_STATUS_SUCCESS;\n\t\t}\n\t}\n\treturn CPA_STATUS_FAIL;\n}\n\nstatic CpaStatus\nget_crypto_instance_on_core(CpaInstanceHandle *pInstanceHandle,\n\t\tuint32_t lcore_id)\n{\n\tCpa16U numInstances = 0, i = 0;\n\tCpaStatus status = CPA_STATUS_FAIL;\n\tCpaInstanceHandle *pLocalInstanceHandles = NULL;\n\tCpa32U coreAffinity = 0;\n\n\tstatus = cpaCyGetNumInstances(&numInstances);\n\tif (CPA_STATUS_SUCCESS != status || numInstances == 0) {\n\t\treturn CPA_STATUS_FAIL;\n\t}\n\n\tpLocalInstanceHandles = rte_malloc(\"pLocalInstanceHandles\",\n\t\t\tsizeof(CpaInstanceHandle) * numInstances, RTE_CACHE_LINE_SIZE);\n\n\tif (NULL == pLocalInstanceHandles) {\n\t\treturn CPA_STATUS_FAIL;\n\t}\n\tstatus = cpaCyGetInstances(numInstances, pLocalInstanceHandles);\n\tif (CPA_STATUS_SUCCESS != status) {\n\t\tprintf(\"Crypto: cpaCyGetInstances failed with status: %\"PRId32\"\\n\", status);\n\t\trte_free((void *) pLocalInstanceHandles);\n\t\treturn CPA_STATUS_FAIL;\n\t}\n\n\tfor (i = 0; i < numInstances; i++) {\n\t\tstatus = getCoreAffinity(&coreAffinity, pLocalInstanceHandles[i]);\n\t\tif (CPA_STATUS_SUCCESS != status) {\n\t\t\trte_free((void *) pLocalInstanceHandles);\n\t\t\treturn CPA_STATUS_FAIL;\n\t\t}\n\t\tif (coreAffinity == lcore_id) {\n\t\t\tprintf(\"Crypto: instance found on core %d\\n\", i);\n\t\t\t*pInstanceHandle = pLocalInstanceHandles[i];\n\t\t\treturn CPA_STATUS_SUCCESS;\n\t\t}\n\t}\n\t/* core affinity not found */\n\trte_free((void *) pLocalInstanceHandles);\n\treturn CPA_STATUS_FAIL;\n}\n\nstatic CpaStatus\ninitCySymSession(const int pkt_cipher_alg,\n\t\tconst int pkt_hash_alg, const CpaCySymHashMode hashMode,\n\t\tconst CpaCySymCipherDirection crypto_direction,\n\t\tCpaCySymSessionCtx **ppSessionCtx,\n\t\tconst CpaInstanceHandle cyInstanceHandle,\n\t\tconst uint32_t lcore_id)\n{\n\tCpa32U sessionCtxSizeInBytes = 0;\n\tCpaStatus status = CPA_STATUS_FAIL;\n\tCpaBoolean isCrypto = CPA_TRUE, isHmac = CPA_TRUE;\n\tCpaCySymSessionSetupData sessionSetupData;\n\n\tbzero(&sessionSetupData, sizeof(CpaCySymSessionSetupData));\n\n\t/* Assumption: key length is set to each algorithm's max length */\n\tswitch (pkt_cipher_alg) {\n\tcase NO_CIPHER:\n\t\tisCrypto = CPA_FALSE;\n\t\tbreak;\n\tcase CIPHER_DES:\n\t\tsessionSetupData.cipherSetupData.cipherAlgorithm =\n\t\t\t\tCPA_CY_SYM_CIPHER_DES_ECB;\n\t\tsessionSetupData.cipherSetupData.cipherKeyLenInBytes =\n\t\t\t\tKEY_SIZE_64_IN_BYTES;\n\t\tbreak;\n\tcase CIPHER_DES_CBC:\n\t\tsessionSetupData.cipherSetupData.cipherAlgorithm =\n\t\t\t\tCPA_CY_SYM_CIPHER_DES_CBC;\n\t\tsessionSetupData.cipherSetupData.cipherKeyLenInBytes =\n\t\t\t\tKEY_SIZE_64_IN_BYTES;\n\t\tbreak;\n\tcase CIPHER_DES3:\n\t\tsessionSetupData.cipherSetupData.cipherAlgorithm =\n\t\t\t\tCPA_CY_SYM_CIPHER_3DES_ECB;\n\t\tsessionSetupData.cipherSetupData.cipherKeyLenInBytes =\n\t\t\t\tKEY_SIZE_192_IN_BYTES;\n\t\tbreak;\n\tcase CIPHER_DES3_CBC:\n\t\tsessionSetupData.cipherSetupData.cipherAlgorithm =\n\t\t\t\tCPA_CY_SYM_CIPHER_3DES_CBC;\n\t\tsessionSetupData.cipherSetupData.cipherKeyLenInBytes =\n\t\t\t\tKEY_SIZE_192_IN_BYTES;\n\t\tbreak;\n\tcase CIPHER_AES:\n\t\tsessionSetupData.cipherSetupData.cipherAlgorithm =\n\t\t\t\tCPA_CY_SYM_CIPHER_AES_ECB;\n\t\tsessionSetupData.cipherSetupData.cipherKeyLenInBytes =\n\t\t\t\tKEY_SIZE_128_IN_BYTES;\n\t\tbreak;\n\tcase CIPHER_AES_CBC_128:\n\t\tsessionSetupData.cipherSetupData.cipherAlgorithm =\n\t\t\t\tCPA_CY_SYM_CIPHER_AES_CBC;\n\t\tsessionSetupData.cipherSetupData.cipherKeyLenInBytes =\n\t\t\t\tKEY_SIZE_128_IN_BYTES;\n\t\tbreak;\n\tcase CIPHER_KASUMI_F8:\n\t\tsessionSetupData.cipherSetupData.cipherAlgorithm =\n\t\t\t\tCPA_CY_SYM_CIPHER_KASUMI_F8;\n\t\tsessionSetupData.cipherSetupData.cipherKeyLenInBytes =\n\t\t\t\tKEY_SIZE_128_IN_BYTES;\n\t\tbreak;\n\tdefault:\n\t\tprintf(\"Crypto: Undefined Cipher specified\\n\");\n\t\tbreak;\n\t}\n\t/* Set the cipher direction */\n\tif (isCrypto) {\n\t\tsessionSetupData.cipherSetupData.cipherDirection = crypto_direction;\n\t\tsessionSetupData.cipherSetupData.pCipherKey =\n\t\t\t\tg_crypto_hash_keys.cipher_key;\n\t\tsessionSetupData.symOperation = CPA_CY_SYM_OP_CIPHER;\n\t}\n\n\t/* Setup Hash common fields */\n\tswitch (pkt_hash_alg) {\n\tcase NO_HASH:\n\t\tisHmac = CPA_FALSE;\n\t\tbreak;\n\tcase HASH_AES_XCBC:\n\t\tsessionSetupData.hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_AES_XCBC;\n\t\tsessionSetupData.hashSetupData.digestResultLenInBytes =\n\t\t\t\tAES_XCBC_DIGEST_LENGTH_IN_BYTES;\n\t\tbreak;\n\tcase HASH_AES_XCBC_96:\n\t\tsessionSetupData.hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_AES_XCBC;\n\t\t\t\tsessionSetupData.hashSetupData.digestResultLenInBytes =\n\t\t\t\tAES_XCBC_96_DIGEST_LENGTH_IN_BYTES;\n\t\tbreak;\n\tcase HASH_MD5:\n\t\tsessionSetupData.hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_MD5;\n\t\tsessionSetupData.hashSetupData.digestResultLenInBytes =\n\t\t\t\tMD5_DIGEST_LENGTH_IN_BYTES;\n\t\tbreak;\n\tcase HASH_SHA1:\n\t\tsessionSetupData.hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1;\n\t\tsessionSetupData.hashSetupData.digestResultLenInBytes =\n\t\t\t\tSHA1_DIGEST_LENGTH_IN_BYTES;\n\t\tbreak;\n\tcase HASH_SHA1_96:\n\t\tsessionSetupData.hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA1;\n\t\tsessionSetupData.hashSetupData.digestResultLenInBytes =\n\t\t\t\tSHA1_96_DIGEST_LENGTH_IN_BYTES;\n\t break;\n\tcase HASH_SHA224:\n\t\tsessionSetupData.hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA224;\n\t\tsessionSetupData.hashSetupData.digestResultLenInBytes =\n\t\t\t\tSHA224_DIGEST_LENGTH_IN_BYTES;\n\t\tbreak;\n\tcase HASH_SHA256:\n\t\tsessionSetupData.hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA256;\n\t\tsessionSetupData.hashSetupData.digestResultLenInBytes =\n\t\t\t\tSHA256_DIGEST_LENGTH_IN_BYTES;\n\t\tbreak;\n\tcase HASH_SHA384:\n\t\tsessionSetupData.hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA384;\n\t\tsessionSetupData.hashSetupData.digestResultLenInBytes =\n\t\t\t\tSHA384_DIGEST_LENGTH_IN_BYTES;\n\t\tbreak;\n\tcase HASH_SHA512:\n\t\tsessionSetupData.hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_SHA512;\n\t\tsessionSetupData.hashSetupData.digestResultLenInBytes =\n\t\t\t\tSHA512_DIGEST_LENGTH_IN_BYTES;\n\t\tbreak;\n\tcase HASH_KASUMI_F9:\n\t\tsessionSetupData.hashSetupData.hashAlgorithm = CPA_CY_SYM_HASH_KASUMI_F9;\n\t\tsessionSetupData.hashSetupData.digestResultLenInBytes =\n\t\t\t\tKASUMI_DIGEST_LENGTH_IN_BYTES;\n\t\tbreak;\n\tdefault:\n\t\tprintf(\"Crypto: Undefined Hash specified\\n\");\n\t\tbreak;\n\t}\n\tif (isHmac) {\n\t\tsessionSetupData.hashSetupData.hashMode = hashMode;\n\t\tsessionSetupData.symOperation = CPA_CY_SYM_OP_HASH;\n\t\t/* If using authenticated hash setup key lengths */\n\t\tif (CPA_CY_SYM_HASH_MODE_AUTH == hashMode) {\n\t\t\t/* Use a common max length key */\n\t\t\tsessionSetupData.hashSetupData.authModeSetupData.authKey =\n\t\t\t\t\tg_crypto_hash_keys.hash_key;\n\t\t\tswitch (pkt_hash_alg) {\n\t\t\tcase HASH_AES_XCBC:\n\t\t\tcase HASH_AES_XCBC_96:\n\t\t\t\tsessionSetupData.hashSetupData.authModeSetupData.authKeyLenInBytes =\n\t\t\t\t\t\tAES_XCBC_AUTH_KEY_LENGTH_IN_BYTES;\n\t\t\t\tbreak;\n\t\t\tcase HASH_MD5:\n\t\t\t\tsessionSetupData.hashSetupData.authModeSetupData.authKeyLenInBytes =\n\t\t\t\t\t\tSHA1_AUTH_KEY_LENGTH_IN_BYTES;\n\t\t\t\tbreak;\n\t\t\tcase HASH_SHA1:\n\t\t\tcase HASH_SHA1_96:\n\t\t\t\tsessionSetupData.hashSetupData.authModeSetupData.authKeyLenInBytes =\n\t\t\t\t\t\tSHA1_AUTH_KEY_LENGTH_IN_BYTES;\n\t\t\t\tbreak;\n\t\t\tcase HASH_SHA224:\n\t\t\t\tsessionSetupData.hashSetupData.authModeSetupData.authKeyLenInBytes =\n\t\t\t\t\t\tSHA224_AUTH_KEY_LENGTH_IN_BYTES;\n\t\t\t\tbreak;\n\t\t\tcase HASH_SHA256:\n\t\t\t\tsessionSetupData.hashSetupData.authModeSetupData.authKeyLenInBytes =\n\t\t\t\t\t\tSHA256_AUTH_KEY_LENGTH_IN_BYTES;\n\t\t\t\tbreak;\n\t\t\tcase HASH_SHA384:\n\t\t\t\tsessionSetupData.hashSetupData.authModeSetupData.authKeyLenInBytes =\n\t\t\t\t\t\tSHA384_AUTH_KEY_LENGTH_IN_BYTES;\n\t\t\t\tbreak;\n\t\t\tcase HASH_SHA512:\n\t\t\t\tsessionSetupData.hashSetupData.authModeSetupData.authKeyLenInBytes =\n\t\t\t\t\t\tSHA512_AUTH_KEY_LENGTH_IN_BYTES;\n\t\t\t\tbreak;\n\t\t\tcase HASH_KASUMI_F9:\n\t\t\t\tsessionSetupData.hashSetupData.authModeSetupData.authKeyLenInBytes =\n\t\t\t\t\t\tKASUMI_AUTH_KEY_LENGTH_IN_BYTES;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tprintf(\"Crypto: Undefined Hash specified\\n\");\n\t\t\t\treturn CPA_STATUS_FAIL;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Only high priority supported */\n\tsessionSetupData.sessionPriority = CPA_CY_PRIORITY_HIGH;\n\n\t/* If chaining algorithms */\n\tif (isCrypto && isHmac) {\n\t\tsessionSetupData.symOperation = CPA_CY_SYM_OP_ALGORITHM_CHAINING;\n\t\t/* @assumption Alg Chain order is cipher then hash for encrypt\n\t\t * and hash then cipher then has for decrypt*/\n\t\tif (CPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT == crypto_direction) {\n\t\t\tsessionSetupData.algChainOrder =\n\t\t\t\t\tCPA_CY_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH;\n\t\t} else {\n\t\t\tsessionSetupData.algChainOrder =\n\t\t\t\t\tCPA_CY_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER;\n\t\t}\n\t}\n\tif (!isCrypto && !isHmac) {\n\t\t*ppSessionCtx = NULL;\n\t\treturn CPA_STATUS_SUCCESS;\n\t}\n\n\t/* Set flags for digest operations */\n\tsessionSetupData.digestIsAppended = CPA_FALSE;\n\tsessionSetupData.verifyDigest = CPA_TRUE;\n\n\t/* Get the session context size based on the crypto and/or hash operations*/\n\tstatus = cpaCySymDpSessionCtxGetSize(cyInstanceHandle, &sessionSetupData,\n\t\t\t&sessionCtxSizeInBytes);\n\tif (CPA_STATUS_SUCCESS != status) {\n\t\tprintf(\"Crypto: cpaCySymDpSessionCtxGetSize error, status: %\"PRId32\"\\n\",\n\t\t\t\tstatus);\n\t\treturn CPA_STATUS_FAIL;\n\t}\n\n\t*ppSessionCtx = alloc_memzone_region(sessionCtxSizeInBytes, lcore_id);\n\tif (NULL == *ppSessionCtx) {\n\t\tprintf(\"Crypto: Failed to allocate memory for Session Context\\n\");\n\t\treturn CPA_STATUS_FAIL;\n\t}\n\n\tstatus = cpaCySymDpInitSession(cyInstanceHandle, &sessionSetupData,\n\t\t\t*ppSessionCtx);\n\tif (CPA_STATUS_SUCCESS != status) {\n\t\tprintf(\"Crypto: cpaCySymDpInitSession failed with status %\"PRId32\"\\n\", status);\n\t\treturn CPA_STATUS_FAIL;\n\t}\n\treturn CPA_STATUS_SUCCESS;\n}\n\nstatic CpaStatus\ninitSessionDataTables(struct qa_core_conf *qaCoreConf,uint32_t lcore_id)\n{\n\tCpa32U i = 0, j = 0;\n\tCpaStatus status = CPA_STATUS_FAIL;\n\tfor (i = 0; i < NUM_CRYPTO; i++) {\n\t\tfor (j = 0; j < NUM_HMAC; j++) {\n\t\t\tif (((i == CIPHER_KASUMI_F8) && (j != NO_HASH) && (j != HASH_KASUMI_F9)) ||\n\t\t\t\t((i != NO_CIPHER) && (i != CIPHER_KASUMI_F8) && (j == HASH_KASUMI_F9)))\n\t\t\t\tcontinue;\n\t\t\tstatus = initCySymSession(i, j, CPA_CY_SYM_HASH_MODE_AUTH,\n\t\t\t\t\tCPA_CY_SYM_CIPHER_DIRECTION_ENCRYPT,\n\t\t\t\t\t&qaCoreConf->encryptSessionHandleTbl[i][j],\n\t\t\t\t\tqaCoreConf->instanceHandle,\n\t\t\t\t\tlcore_id);\n\t\t\tif (CPA_STATUS_SUCCESS != status) {\n\t\t\t\tprintf(\"Crypto: Failed to initialize Encrypt sessions\\n\");\n\t\t\t\treturn CPA_STATUS_FAIL;\n\t\t\t}\n\t\t\tstatus = initCySymSession(i, j, CPA_CY_SYM_HASH_MODE_AUTH,\n\t\t\t\t\tCPA_CY_SYM_CIPHER_DIRECTION_DECRYPT,\n\t\t\t\t\t&qaCoreConf->decryptSessionHandleTbl[i][j],\n\t\t\t\t\tqaCoreConf->instanceHandle,\n\t\t\t\t\tlcore_id);\n\t\t\tif (CPA_STATUS_SUCCESS != status) {\n\t\t\t\tprintf(\"Crypto: Failed to initialize Decrypt sessions\\n\");\n\t\t\t\treturn CPA_STATUS_FAIL;\n\t\t\t}\n\t\t}\n\t}\n\treturn CPA_STATUS_SUCCESS;\n}\n\nint\ncrypto_init(void)\n{\n\tif (CPA_STATUS_SUCCESS != icp_sal_userStartMultiProcess(\"SSL\",CPA_FALSE)) {\n\t\tprintf(\"Crypto: Could not start sal for user space\\n\");\n\t\treturn CPA_STATUS_FAIL;\n\t}\n\tprintf(\"Crypto: icp_sal_userStartMultiProcess(\\\"SSL\\\",CPA_FALSE)\\n\");\n\treturn 0;\n}\n\n/*\n * Per core initialisation\n */\nint\nper_core_crypto_init(uint32_t lcore_id)\n{\n\tCpaStatus status = CPA_STATUS_FAIL;\n\tchar memzone_name[RTE_MEMZONE_NAMESIZE];\n\n\tint socketID = rte_lcore_to_socket_id(lcore_id);\n\n\t/* Allocate software ring for response messages. */\n\n\tqaCoreConf[lcore_id].callbackQueue.head = 0;\n\tqaCoreConf[lcore_id].callbackQueue.tail = 0;\n\tqaCoreConf[lcore_id].callbackQueue.numEntries = 0;\n\tqaCoreConf[lcore_id].kickFreq = 0;\n\tqaCoreConf[lcore_id].qaOutstandingRequests = 0;\n\tqaCoreConf[lcore_id].numResponseAttempts = 0;\n\n\t/* Initialise and reserve lcore memzone for virt2phys translation */\n\tsnprintf(memzone_name,\n\t\t\tRTE_MEMZONE_NAMESIZE,\n\t\t\t\"lcore_%u\",\n\t\t\tlcore_id);\n\n\tqaCoreConf[lcore_id].lcoreMemzone.memzone = rte_memzone_reserve(\n\t\t\tmemzone_name,\n\t\t\tLCORE_MEMZONE_SIZE,\n\t\t\tsocketID,\n\t\t\t0);\n\tif (NULL == qaCoreConf[lcore_id].lcoreMemzone.memzone) {\n\t\tprintf(\"Crypto: Error allocating memzone on lcore %u\\n\",lcore_id);\n\t\treturn -1;\n\t}\n\tqaCoreConf[lcore_id].lcoreMemzone.next_free_address =\n\t\t\t\t\t\t\tqaCoreConf[lcore_id].lcoreMemzone.memzone->addr;\n\n\tqaCoreConf[lcore_id].pPacketIV = alloc_memzone_region(IV_LENGTH_16_BYTES,\n\t\t\t\t\t\t\tlcore_id);\n\n\tif (NULL == qaCoreConf[lcore_id].pPacketIV ) {\n\t\tprintf(\"Crypto: Failed to allocate memory for Initialization Vector\\n\");\n\t\treturn -1;\n\t}\n\n\tmemcpy(qaCoreConf[lcore_id].pPacketIV, &g_crypto_hash_keys.iv,\n\t\t\tIV_LENGTH_16_BYTES);\n\n\tqaCoreConf[lcore_id].packetIVPhy = qa_v2p(qaCoreConf[lcore_id].pPacketIV);\n\tif (0 == qaCoreConf[lcore_id].packetIVPhy) {\n\t\tprintf(\"Crypto: Invalid physical address for Initialization Vector\\n\");\n\t\treturn -1;\n\t}\n\n\t/*\n\t * Obtain the instance handle that is mapped to the current lcore.\n\t * This can fail if an instance is not mapped to a bank which has been\n\t * affinitized to the current lcore.\n\t */\n\tstatus = get_crypto_instance_on_core(&(qaCoreConf[lcore_id].instanceHandle),\n\t\t\tlcore_id);\n\tif (CPA_STATUS_SUCCESS != status) {\n\t\tprintf(\"Crypto: get_crypto_instance_on_core failed with status: %\"PRId32\"\\n\",\n\t\t\t\tstatus);\n\t\treturn -1;\n\t}\n\n\tstatus = cpaCySymDpRegCbFunc(qaCoreConf[lcore_id].instanceHandle,\n\t\t\t(CpaCySymDpCbFunc) qa_crypto_callback);\n\tif (CPA_STATUS_SUCCESS != status) {\n\t\tprintf(\"Crypto: cpaCySymDpRegCbFunc failed with status: %\"PRId32\"\\n\", status);\n\t\treturn -1;\n\t}\n\n\t/*\n\t * Set the address translation callback for virtual to physcial address\n\t * mapping. This will be called by the QAT driver during initialisation only.\n\t */\n\tstatus = cpaCySetAddressTranslation(qaCoreConf[lcore_id].instanceHandle,\n\t\t\t(CpaVirtualToPhysical) qa_v2p);\n\tif (CPA_STATUS_SUCCESS != status) {\n\t\tprintf(\"Crypto: cpaCySetAddressTranslation failed with status: %\"PRId32\"\\n\",\n\t\t\t\tstatus);\n\t\treturn -1;\n\t}\n\n\tstatus = initSessionDataTables(&qaCoreConf[lcore_id],lcore_id);\n\tif (CPA_STATUS_SUCCESS != status) {\n\t\tprintf(\"Crypto: Failed to allocate all session tables.\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic CpaStatus\nenqueueOp(CpaCySymDpOpData *opData, uint32_t lcore_id)\n{\n\n\tCpaStatus status;\n\n\t/*\n\t * Assumption is there is no requirement to do load balancing between\n\t * acceleration units - that is one acceleration unit is tied to a core.\n\t */\n\topData->instanceHandle = qaCoreConf[lcore_id].instanceHandle;\n\n\tif ((++qaCoreConf[lcore_id].kickFreq) % CRYPTO_BURST_TX == 0) {\n\t\tstatus = cpaCySymDpEnqueueOp(opData, CPA_TRUE);\n\t} else {\n\t\tstatus = cpaCySymDpEnqueueOp(opData, CPA_FALSE);\n\t}\n\n\tqaCoreConf[lcore_id].qaOutstandingRequests++;\n\n\treturn status;\n}\n\nvoid\ncrypto_flush_tx_queue(uint32_t lcore_id)\n{\n\n\tcpaCySymDpPerformOpNow(qaCoreConf[lcore_id].instanceHandle);\n}\n\nenum crypto_result\ncrypto_encrypt(struct rte_mbuf *rte_buff, enum cipher_alg c, enum hash_alg h)\n{\n\tCpaCySymDpOpData *opData =\n\t\t\trte_pktmbuf_mtod_offset(rte_buff, CpaCySymDpOpData *,\n\t\t\t\t\t\tCRYPTO_OFFSET_TO_OPDATA);\n\tuint32_t lcore_id;\n\n\tif (unlikely(c >= NUM_CRYPTO || h >= NUM_HMAC))\n\t\treturn CRYPTO_RESULT_FAIL;\n\n\tlcore_id = rte_lcore_id();\n\n\tbzero(opData, sizeof(CpaCySymDpOpData));\n\n\topData->srcBuffer = opData->dstBuffer = PACKET_DATA_START_PHYS(rte_buff);\n\topData->srcBufferLen = opData->dstBufferLen = rte_buff->data_len;\n\topData->sessionCtx = qaCoreConf[lcore_id].encryptSessionHandleTbl[c][h];\n\topData->thisPhys = PACKET_DATA_START_PHYS(rte_buff)\n\t\t\t+ CRYPTO_OFFSET_TO_OPDATA;\n\topData->pCallbackTag = rte_buff;\n\n\t/* if no crypto or hash operations are specified return fail */\n\tif (NO_CIPHER == c && NO_HASH == h)\n\t\treturn CRYPTO_RESULT_FAIL;\n\n\tif (NO_CIPHER != c) {\n\t\topData->pIv = qaCoreConf[lcore_id].pPacketIV;\n\t\topData->iv = qaCoreConf[lcore_id].packetIVPhy;\n\n\t\tif (CIPHER_AES_CBC_128 == c)\n\t\t\topData->ivLenInBytes = IV_LENGTH_16_BYTES;\n\t\telse\n\t\t\topData->ivLenInBytes = IV_LENGTH_8_BYTES;\n\n\t\topData->cryptoStartSrcOffsetInBytes = CRYPTO_START_OFFSET;\n\t\topData->messageLenToCipherInBytes = rte_buff->data_len\n\t\t\t\t- CRYPTO_START_OFFSET;\n\t\t/*\n\t\t * Work around for padding, message length has to be a multiple of\n\t\t * block size.\n\t\t */\n\t\topData->messageLenToCipherInBytes -= opData->messageLenToCipherInBytes\n\t\t\t\t% CIPHER_BLOCK_DEFAULT_SIZE;\n\t}\n\n\tif (NO_HASH != h) {\n\n\t\topData->hashStartSrcOffsetInBytes = HASH_START_OFFSET;\n\t\topData->messageLenToHashInBytes = rte_buff->data_len\n\t\t\t\t- HASH_START_OFFSET;\n\t\t/*\n\t\t * Work around for padding, message length has to be a multiple of block\n\t\t * size.\n\t\t */\n\t\topData->messageLenToHashInBytes -= opData->messageLenToHashInBytes\n\t\t\t\t% HASH_BLOCK_DEFAULT_SIZE;\n\n\t\t/*\n\t\t * Assumption: Ok ignore the passed digest pointer and place HMAC at end\n\t\t * of packet.\n\t\t */\n\t\topData->digestResult = rte_buff->buf_physaddr + rte_buff->data_len;\n\t}\n\n\tif (CPA_STATUS_SUCCESS != enqueueOp(opData, lcore_id)) {\n\t\t/*\n\t\t * Failed to place a packet on the hardware queue.\n\t\t * Most likely because the QA hardware is busy.\n\t\t */\n\t\treturn CRYPTO_RESULT_FAIL;\n\t}\n\treturn CRYPTO_RESULT_IN_PROGRESS;\n}\n\nenum crypto_result\ncrypto_decrypt(struct rte_mbuf *rte_buff, enum cipher_alg c, enum hash_alg h)\n{\n\n\tCpaCySymDpOpData *opData = rte_pktmbuf_mtod_offset(rte_buff, void *,\n\t\t\t\t\t\t\t CRYPTO_OFFSET_TO_OPDATA);\n\tuint32_t lcore_id;\n\n\tif (unlikely(c >= NUM_CRYPTO || h >= NUM_HMAC))\n\t\treturn CRYPTO_RESULT_FAIL;\n\n\tlcore_id = rte_lcore_id();\n\n\tbzero(opData, sizeof(CpaCySymDpOpData));\n\n\topData->dstBuffer = opData->srcBuffer = PACKET_DATA_START_PHYS(rte_buff);\n\topData->dstBufferLen = opData->srcBufferLen = rte_buff->data_len;\n\topData->thisPhys = PACKET_DATA_START_PHYS(rte_buff)\n\t\t\t+ CRYPTO_OFFSET_TO_OPDATA;\n\topData->sessionCtx = qaCoreConf[lcore_id].decryptSessionHandleTbl[c][h];\n\topData->pCallbackTag = rte_buff;\n\n\t/* if no crypto or hmac operations are specified return fail */\n\tif (NO_CIPHER == c && NO_HASH == h)\n\t\treturn CRYPTO_RESULT_FAIL;\n\n\tif (NO_CIPHER != c) {\n\t\topData->pIv = qaCoreConf[lcore_id].pPacketIV;\n\t\topData->iv = qaCoreConf[lcore_id].packetIVPhy;\n\n\t\tif (CIPHER_AES_CBC_128 == c)\n\t\t\topData->ivLenInBytes = IV_LENGTH_16_BYTES;\n\t\telse\n\t\t\topData->ivLenInBytes = IV_LENGTH_8_BYTES;\n\n\t\topData->cryptoStartSrcOffsetInBytes = CRYPTO_START_OFFSET;\n\t\topData->messageLenToCipherInBytes = rte_buff->data_len\n\t\t\t\t- CRYPTO_START_OFFSET;\n\n\t\t/*\n\t\t * Work around for padding, message length has to be a multiple of block\n\t\t * size.\n\t\t */\n\t\topData->messageLenToCipherInBytes -= opData->messageLenToCipherInBytes\n\t\t\t\t% CIPHER_BLOCK_DEFAULT_SIZE;\n\t}\n\tif (NO_HASH != h) {\n\t\topData->hashStartSrcOffsetInBytes = HASH_START_OFFSET;\n\t\topData->messageLenToHashInBytes = rte_buff->data_len\n\t\t\t\t- HASH_START_OFFSET;\n\t\t/*\n\t\t * Work around for padding, message length has to be a multiple of block\n\t\t * size.\n\t\t */\n\t\topData->messageLenToHashInBytes -= opData->messageLenToHashInBytes\n\t\t\t\t% HASH_BLOCK_DEFAULT_SIZE;\n\t\topData->digestResult = rte_buff->buf_physaddr + rte_buff->data_len;\n\t}\n\n\tif (CPA_STATUS_SUCCESS != enqueueOp(opData, lcore_id)) {\n\t\t/*\n\t\t * Failed to place a packet on the hardware queue.\n\t\t * Most likely because the QA hardware is busy.\n\t\t */\n\t\treturn CRYPTO_RESULT_FAIL;\n\t}\n\treturn CRYPTO_RESULT_IN_PROGRESS;\n}\n\nvoid *\ncrypto_get_next_response(void)\n{\n\tuint32_t lcore_id;\n\tlcore_id = rte_lcore_id();\n\tstruct qa_callbackQueue *callbackQ = &(qaCoreConf[lcore_id].callbackQueue);\n\tvoid *entry = NULL;\n\n\tif (callbackQ->numEntries) {\n\t\tentry = callbackQ->qaCallbackRing[callbackQ->tail];\n\t\tcallbackQ->tail++;\n\t\tcallbackQ->numEntries--;\n\t}\n\n\t/* If there are no outstanding requests no need to poll, return entry */\n\tif (qaCoreConf[lcore_id].qaOutstandingRequests == 0)\n\t\treturn entry;\n\n\tif (callbackQ->numEntries < CRYPTO_QUEUED_RESP_POLL_THRESHOLD\n\t\t\t&& qaCoreConf[lcore_id].numResponseAttempts++\n\t\t\t\t\t% GET_NEXT_RESPONSE_FREQ == 0) {\n\t\t/*\n\t\t * Only poll the hardware when there is less than\n\t\t * CRYPTO_QUEUED_RESP_POLL_THRESHOLD elements in the software queue\n\t\t */\n\t\ticp_sal_CyPollDpInstance(qaCoreConf[lcore_id].instanceHandle,\n\t\t\t\tCRYPTO_MAX_RESPONSE_QUOTA);\n\t}\n\treturn entry;\n}\n" }, { "path": "examples/dpdk_qat/crypto.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef CRYPTO_H_\n#define CRYPTO_H_\n\n/* Pass Labels/Values to crypto units */\nenum cipher_alg {\n\t/* Option to not do any cryptography */\n\tNO_CIPHER,\n\tCIPHER_DES,\n\tCIPHER_DES_CBC,\n\tCIPHER_DES3,\n\tCIPHER_DES3_CBC,\n\tCIPHER_AES,\n\tCIPHER_AES_CBC_128,\n\tCIPHER_KASUMI_F8,\n\tNUM_CRYPTO,\n};\n\nenum hash_alg {\n\t/* Option to not do any hash */\n\tNO_HASH,\n\tHASH_MD5,\n\tHASH_SHA1,\n\tHASH_SHA1_96,\n\tHASH_SHA224,\n\tHASH_SHA256,\n\tHASH_SHA384,\n\tHASH_SHA512,\n\tHASH_AES_XCBC,\n\tHASH_AES_XCBC_96,\n\tHASH_KASUMI_F9,\n\tNUM_HMAC,\n};\n\n/* Return value from crypto_{encrypt/decrypt} */\nenum crypto_result {\n\t/* Packet was successfully put into crypto queue */\n\tCRYPTO_RESULT_IN_PROGRESS,\n\t/* Cryptography has failed in some way */\n\tCRYPTO_RESULT_FAIL,\n};\n\nextern enum crypto_result crypto_encrypt(struct rte_mbuf *pkt, enum cipher_alg c,\n\t\tenum hash_alg h);\nextern enum crypto_result crypto_decrypt(struct rte_mbuf *pkt, enum cipher_alg c,\n\t\tenum hash_alg h);\n\nextern int crypto_init(void);\n\nextern int per_core_crypto_init(uint32_t lcore_id);\n\nextern void crypto_exit(void);\n\nextern void *crypto_get_next_response(void);\n\nextern void crypto_flush_tx_queue(uint32_t lcore_id);\n\n#endif /* CRYPTO_H_ */\n" }, { "path": "examples/dpdk_qat/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"crypto.h\"\n\n#define NB_MBUF (32 * 1024)\n\n#define MAX_PKT_BURST 32\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n#define TX_QUEUE_FLUSH_MASK 0xFFFFFFFF\n#define TSC_COUNT_LIMIT 1000\n\n#define ACTION_ENCRYPT 1\n#define ACTION_DECRYPT 2\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n/* ethernet addresses of ports */\nstatic struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];\n\n/* mask of enabled ports */\nstatic unsigned enabled_port_mask = 0;\nstatic int promiscuous_on = 1; /**< Ports set in promiscuous mode on by default. */\n\n/* list of enabled ports */\nstatic uint32_t dst_ports[RTE_MAX_ETHPORTS];\n\nstruct mbuf_table {\n\tuint16_t len;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST];\n};\n\nstruct lcore_rx_queue {\n\tuint8_t port_id;\n\tuint8_t queue_id;\n};\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n\n#define MAX_LCORE_PARAMS 1024\nstruct lcore_params {\n\tuint8_t port_id;\n\tuint8_t queue_id;\n\tuint8_t lcore_id;\n};\n\nstatic struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];\nstatic struct lcore_params lcore_params_array_default[] = {\n\t{0, 0, 2},\n\t{0, 1, 2},\n\t{0, 2, 2},\n\t{1, 0, 2},\n\t{1, 1, 2},\n\t{1, 2, 2},\n\t{2, 0, 2},\n\t{3, 0, 3},\n\t{3, 1, 3},\n};\n\nstatic struct lcore_params * lcore_params = lcore_params_array_default;\nstatic uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /\n\t\t\t\tsizeof(lcore_params_array_default[0]);\n\nstatic struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.mq_mode\t= ETH_MQ_RX_RSS,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 1, /**< IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.rx_adv_conf = {\n\t\t.rss_conf = {\n\t\t\t.rss_key = NULL,\n\t\t\t.rss_hf = ETH_RSS_IP,\n\t\t},\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\nstatic struct rte_mempool * pktmbuf_pool[RTE_MAX_NUMA_NODES];\n\nstruct lcore_conf {\n\tuint64_t tsc;\n\tuint64_t tsc_count;\n\tuint32_t tx_mask;\n\tuint16_t n_rx_queue;\n\tuint16_t rx_queue_list_pos;\n\tstruct lcore_rx_queue rx_queue_list[MAX_RX_QUEUE_PER_LCORE];\n\tuint16_t tx_queue_id[RTE_MAX_ETHPORTS];\n\tstruct mbuf_table rx_mbuf;\n\tuint32_t rx_mbuf_pos;\n\tuint32_t rx_curr_queue;\n\tstruct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];\n} __rte_cache_aligned;\n\nstatic struct lcore_conf lcore_conf[RTE_MAX_LCORE];\n\nstatic inline struct rte_mbuf *\nnic_rx_get_packet(struct lcore_conf *qconf)\n{\n\tstruct rte_mbuf *pkt;\n\n\tif (unlikely(qconf->n_rx_queue == 0))\n\t\treturn NULL;\n\n\t/* Look for the next queue with packets; return if none */\n\tif (unlikely(qconf->rx_mbuf_pos == qconf->rx_mbuf.len)) {\n\t\tuint32_t i;\n\n\t\tqconf->rx_mbuf_pos = 0;\n\t\tfor (i = 0; i < qconf->n_rx_queue; i++) {\n\t\t\tqconf->rx_mbuf.len = rte_eth_rx_burst(\n\t\t\t\tqconf->rx_queue_list[qconf->rx_curr_queue].port_id,\n\t\t\t\tqconf->rx_queue_list[qconf->rx_curr_queue].queue_id,\n\t\t\t\tqconf->rx_mbuf.m_table, MAX_PKT_BURST);\n\n\t\t\tqconf->rx_curr_queue++;\n\t\t\tif (unlikely(qconf->rx_curr_queue == qconf->n_rx_queue))\n\t\t\t\tqconf->rx_curr_queue = 0;\n\t\t\tif (likely(qconf->rx_mbuf.len > 0))\n\t\t\t\tbreak;\n\t\t}\n\t\tif (unlikely(i == qconf->n_rx_queue))\n\t\t\treturn NULL;\n\t}\n\n\t/* Get the next packet from the current queue; if last packet, go to next queue */\n\tpkt = qconf->rx_mbuf.m_table[qconf->rx_mbuf_pos];\n\tqconf->rx_mbuf_pos++;\n\n\treturn pkt;\n}\n\nstatic inline void\nnic_tx_flush_queues(struct lcore_conf *qconf)\n{\n\tuint8_t portid;\n\n\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\tstruct rte_mbuf **m_table = NULL;\n\t\tuint16_t queueid, len;\n\t\tuint32_t n, i;\n\n\t\tif (likely((qconf->tx_mask & (1 << portid)) == 0))\n\t\t\tcontinue;\n\n\t\tlen = qconf->tx_mbufs[portid].len;\n\t\tif (likely(len == 0))\n\t\t\tcontinue;\n\n\t\tqueueid = qconf->tx_queue_id[portid];\n\t\tm_table = qconf->tx_mbufs[portid].m_table;\n\n\t\tn = rte_eth_tx_burst(portid, queueid, m_table, len);\n\t\tfor (i = n; i < len; i++){\n\t\t\trte_pktmbuf_free(m_table[i]);\n\t\t}\n\n\t\tqconf->tx_mbufs[portid].len = 0;\n\t}\n\n\tqconf->tx_mask = TX_QUEUE_FLUSH_MASK;\n}\n\nstatic inline void\nnic_tx_send_packet(struct rte_mbuf *pkt, uint8_t port)\n{\n\tstruct lcore_conf *qconf;\n\tuint32_t lcoreid;\n\tuint16_t len;\n\n\tif (unlikely(pkt == NULL)) {\n\t\treturn;\n\t}\n\n\tlcoreid = rte_lcore_id();\n\tqconf = &lcore_conf[lcoreid];\n\n\tlen = qconf->tx_mbufs[port].len;\n\tqconf->tx_mbufs[port].m_table[len] = pkt;\n\tlen++;\n\n\t/* enough pkts to be sent */\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tuint32_t n, i;\n\t\tuint16_t queueid;\n\n\t\tqueueid = qconf->tx_queue_id[port];\n\t\tn = rte_eth_tx_burst(port, queueid, qconf->tx_mbufs[port].m_table, MAX_PKT_BURST);\n\t\tfor (i = n; i < MAX_PKT_BURST; i++){\n\t\t\trte_pktmbuf_free(qconf->tx_mbufs[port].m_table[i]);\n\t\t}\n\n\t\tqconf->tx_mask &= ~(1 << port);\n\t\tlen = 0;\n\t}\n\n\tqconf->tx_mbufs[port].len = len;\n}\n\n/* main processing loop */\nstatic __attribute__((noreturn)) int\nmain_loop(__attribute__((unused)) void *dummy)\n{\n\tuint32_t lcoreid;\n\tstruct lcore_conf *qconf;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\tlcoreid = rte_lcore_id();\n\tqconf = &lcore_conf[lcoreid];\n\n\tprintf(\"Thread %u starting...\\n\", lcoreid);\n\n\tfor (;;) {\n\t\tstruct rte_mbuf *pkt;\n\t\tuint32_t pkt_from_nic_rx = 0;\n\t\tuint8_t port;\n\n\t\t/* Flush TX queues */\n\t\tqconf->tsc_count++;\n\t\tif (unlikely(qconf->tsc_count == TSC_COUNT_LIMIT)) {\n\t\t\tuint64_t tsc, diff_tsc;\n\n\t\t\ttsc = rte_rdtsc();\n\n\t\t\tdiff_tsc = tsc - qconf->tsc;\n\t\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\t\t\t\tnic_tx_flush_queues(qconf);\n\t\t\t\tcrypto_flush_tx_queue(lcoreid);\n\t\t\t\tqconf->tsc = tsc;\n\t\t\t}\n\n\t\t\tqconf->tsc_count = 0;\n\t\t}\n\n\t\t/*\n\t\t * Check the Intel QuickAssist queues first\n\t\t *\n\t\t ***/\n\t\tpkt = (struct rte_mbuf *) crypto_get_next_response();\n\t\tif (pkt == NULL) {\n\t\t\tpkt = nic_rx_get_packet(qconf);\n\t\t\tpkt_from_nic_rx = 1;\n\t\t}\n\t\tif (pkt == NULL)\n\t\t\tcontinue;\n\t\t/* Send packet to either QAT encrypt, QAT decrypt or NIC TX */\n\t\tif (pkt_from_nic_rx) {\n\t\t\tstruct ipv4_hdr *ip = rte_pktmbuf_mtod_offset(pkt,\n\t\t\t\t\t\t\t\t struct ipv4_hdr *,\n\t\t\t\t\t\t\t\t sizeof(struct ether_hdr));\n\t\t\tif (ip->src_addr & rte_cpu_to_be_32(ACTION_ENCRYPT)) {\n\t\t\t\tif (CRYPTO_RESULT_FAIL == crypto_encrypt(pkt,\n\t\t\t\t\t(enum cipher_alg)((ip->src_addr >> 16) & 0xFF),\n\t\t\t\t\t(enum hash_alg)((ip->src_addr >> 8) & 0xFF)))\n\t\t\t\t\trte_pktmbuf_free(pkt);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (ip->src_addr & rte_cpu_to_be_32(ACTION_DECRYPT)) {\n\t\t\t\tif(CRYPTO_RESULT_FAIL == crypto_decrypt(pkt,\n\t\t\t\t\t(enum cipher_alg)((ip->src_addr >> 16) & 0xFF),\n\t\t\t\t\t(enum hash_alg)((ip->src_addr >> 8) & 0xFF)))\n\t\t\t\t\trte_pktmbuf_free(pkt);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\n\t\tport = dst_ports[pkt->port];\n\n\t\t/* Transmit the packet */\n\t\tnic_tx_send_packet(pkt, (uint8_t)port);\n\t}\n}\n\nstatic inline unsigned\nget_port_max_rx_queues(uint8_t port_id)\n{\n\tstruct rte_eth_dev_info dev_info;\n\n\trte_eth_dev_info_get(port_id, &dev_info);\n\treturn dev_info.max_rx_queues;\n}\n\nstatic inline unsigned\nget_port_max_tx_queues(uint8_t port_id)\n{\n\tstruct rte_eth_dev_info dev_info;\n\n\trte_eth_dev_info_get(port_id, &dev_info);\n\treturn dev_info.max_tx_queues;\n}\n\nstatic int\ncheck_lcore_params(void)\n{\n\tuint16_t i;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tif (lcore_params[i].queue_id >= get_port_max_rx_queues(lcore_params[i].port_id)) {\n\t\t\tprintf(\"invalid queue number: %hhu\\n\", lcore_params[i].queue_id);\n\t\t\treturn -1;\n\t\t}\n\t\tif (!rte_lcore_is_enabled(lcore_params[i].lcore_id)) {\n\t\t\tprintf(\"error: lcore %hhu is not enabled in lcore mask\\n\",\n\t\t\t\tlcore_params[i].lcore_id);\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\ncheck_port_config(const unsigned nb_ports)\n{\n\tunsigned portid;\n\tuint16_t i;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tportid = lcore_params[i].port_id;\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"port %u is not enabled in port mask\\n\", portid);\n\t\t\treturn -1;\n\t\t}\n\t\tif (portid >= nb_ports) {\n\t\t\tprintf(\"port %u is not present on the board\\n\", portid);\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic uint8_t\nget_port_n_rx_queues(const uint8_t port)\n{\n\tint queue = -1;\n\tuint16_t i;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tif (lcore_params[i].port_id == port && lcore_params[i].queue_id > queue)\n\t\t\tqueue = lcore_params[i].queue_id;\n\t}\n\treturn (uint8_t)(++queue);\n}\n\nstatic int\ninit_lcore_rx_queues(void)\n{\n\tuint16_t i, nb_rx_queue;\n\tuint8_t lcore;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tlcore = lcore_params[i].lcore_id;\n\t\tnb_rx_queue = lcore_conf[lcore].n_rx_queue;\n\t\tif (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) {\n\t\t\tprintf(\"error: too many queues (%u) for lcore: %u\\n\",\n\t\t\t\t(unsigned)nb_rx_queue + 1, (unsigned)lcore);\n\t\t\treturn -1;\n\t\t}\n\t\tlcore_conf[lcore].rx_queue_list[nb_rx_queue].port_id =\n\t\t\tlcore_params[i].port_id;\n\t\tlcore_conf[lcore].rx_queue_list[nb_rx_queue].queue_id =\n\t\t\tlcore_params[i].queue_id;\n\t\tlcore_conf[lcore].n_rx_queue++;\n\t}\n\treturn 0;\n}\n\n/* display usage */\nstatic void\nprint_usage(const char *prgname)\n{\n\tprintf (\"%s [EAL options] -- -p PORTMASK [--no-promisc]\"\n\t\t\" [--config '(port,queue,lcore)[,(port,queue,lcore)]'\\n\"\n\t\t\" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t\t\" --no-promisc: disable promiscuous mode (default is ON)\\n\"\n\t\t\" --config '(port,queue,lcore)': rx queues configuration\\n\",\n\t\tprgname);\n}\n\nstatic unsigned\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn 0;\n\n\treturn pm;\n}\n\nstatic int\nparse_config(const char *q_arg)\n{\n\tchar s[256];\n\tconst char *p, *p_end = q_arg;\n\tchar *end;\n\tenum fieldnames {\n\t\tFLD_PORT = 0,\n\t\tFLD_QUEUE,\n\t\tFLD_LCORE,\n\t\t_NUM_FLD\n\t};\n\tunsigned long int_fld[_NUM_FLD];\n\tchar *str_fld[_NUM_FLD];\n\tint i;\n\tunsigned size;\n\n\tnb_lcore_params = 0;\n\n\twhile ((p = strchr(p_end,'(')) != NULL) {\n\t\tif (nb_lcore_params >= MAX_LCORE_PARAMS) {\n\t\t\tprintf(\"exceeded max number of lcore params: %hu\\n\",\n\t\t\t\tnb_lcore_params);\n\t\t\treturn -1;\n\t\t}\n\t\t++p;\n\t\tif((p_end = strchr(p,')')) == NULL)\n\t\t\treturn -1;\n\n\t\tsize = p_end - p;\n\t\tif(size >= sizeof(s))\n\t\t\treturn -1;\n\n\t\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\t\tif (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') != _NUM_FLD)\n\t\t\treturn -1;\n\t\tfor (i = 0; i < _NUM_FLD; i++) {\n\t\t\terrno = 0;\n\t\t\tint_fld[i] = strtoul(str_fld[i], &end, 0);\n\t\t\tif (errno != 0 || end == str_fld[i] || int_fld[i] > 255)\n\t\t\t\treturn -1;\n\t\t}\n\t\tlcore_params_array[nb_lcore_params].port_id = (uint8_t)int_fld[FLD_PORT];\n\t\tlcore_params_array[nb_lcore_params].queue_id = (uint8_t)int_fld[FLD_QUEUE];\n\t\tlcore_params_array[nb_lcore_params].lcore_id = (uint8_t)int_fld[FLD_LCORE];\n\t\t++nb_lcore_params;\n\t}\n\tlcore_params = lcore_params_array;\n\treturn 0;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{\"config\", 1, 0, 0},\n\t\t{\"no-promisc\", 0, 0, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:\",\n\t\t\t\tlgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tif (strcmp(lgopts[option_index].name, \"config\") == 0) {\n\t\t\t\tret = parse_config(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"invalid config\\n\");\n\t\t\t\t\tprint_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (strcmp(lgopts[option_index].name, \"no-promisc\") == 0) {\n\t\t\t\tprintf(\"Promiscuous mode disabled\\n\");\n\t\t\t\tpromiscuous_on = 0;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (enabled_port_mask == 0) {\n\t\tprintf(\"portmask not specified\\n\");\n\t\tprint_usage(prgname);\n\t\treturn -1;\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\nstatic void\nprint_ethaddr(const char *name, const struct ether_addr *eth_addr)\n{\n\tchar buf[ETHER_ADDR_FMT_SIZE];\n\tether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);\n\tprintf(\"%s%s\", name, buf);\n}\n\nstatic int\ninit_mem(void)\n{\n\tint socketid;\n\tunsigned lcoreid;\n\tchar s[64];\n\n\tRTE_LCORE_FOREACH(lcoreid) {\n\t\tsocketid = rte_lcore_to_socket_id(lcoreid);\n\t\tif (socketid >= RTE_MAX_NUMA_NODES) {\n\t\t\tprintf(\"Socket %d of lcore %u is out of range %d\\n\",\n\t\t\t\tsocketid, lcoreid, RTE_MAX_NUMA_NODES);\n\t\t\treturn -1;\n\t\t}\n\t\tif (pktmbuf_pool[socketid] == NULL) {\n\t\t\tsnprintf(s, sizeof(s), \"mbuf_pool_%d\", socketid);\n\t\t\tpktmbuf_pool[socketid] =\n\t\t\t\trte_pktmbuf_pool_create(s, NB_MBUF, 32, 0,\n\t\t\t\t\tRTE_MBUF_DEFAULT_BUF_SIZE, socketid);\n\t\t\tif (pktmbuf_pool[socketid] == NULL) {\n\t\t\t\tprintf(\"Cannot init mbuf pool on socket %d\\n\", socketid);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tprintf(\"Allocated mbuf pool on socket %d\\n\", socketid);\n\t\t}\n\t}\n\treturn 0;\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_conf *qconf;\n\tstruct rte_eth_link link;\n\tint ret;\n\tunsigned nb_ports;\n\tuint16_t queueid;\n\tunsigned lcoreid;\n\tuint32_t nb_tx_queue;\n\tuint8_t portid, nb_rx_queue, queue, socketid, last_port;\n unsigned nb_ports_in_mask = 0;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\treturn -1;\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = parse_args(argc, argv);\n\tif (ret < 0)\n\t\treturn -1;\n\n\tif (check_lcore_params() < 0)\n\t\trte_panic(\"check_lcore_params failed\\n\");\n\n\tret = init_lcore_rx_queues();\n\tif (ret < 0)\n\t\treturn -1;\n\n\tret = init_mem();\n\tif (ret < 0)\n\t\treturn -1;\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\tif (check_port_config(nb_ports) < 0)\n\t\trte_panic(\"check_port_config failed\\n\");\n\n /* reset dst_ports */\n for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++)\n dst_ports[portid] = 0;\n last_port = 0;\n\n /*\n * Each logical core is assigned a dedicated TX queue on each port.\n */\n for (portid = 0; portid < nb_ports; portid++) {\n /* skip ports that are not enabled */\n if ((enabled_port_mask & (1 << portid)) == 0)\n continue;\n\n if (nb_ports_in_mask % 2) {\n dst_ports[portid] = last_port;\n dst_ports[last_port] = portid;\n }\n else\n last_port = portid;\n\n nb_ports_in_mask++;\n }\n if (nb_ports_in_mask % 2) {\n printf(\"Notice: odd number of ports in portmask.\\n\");\n dst_ports[last_port] = last_port;\n }\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"\\nSkipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* init port */\n\t\tprintf(\"Initializing port %d ... \", portid );\n\t\tfflush(stdout);\n\n\t\tnb_rx_queue = get_port_n_rx_queues(portid);\n\t\tif (nb_rx_queue > get_port_max_rx_queues(portid))\n\t\t\trte_panic(\"Number of rx queues %d exceeds max number of rx queues %u\"\n\t\t\t\t\" for port %d\\n\", nb_rx_queue, get_port_max_rx_queues(portid),\n\t\t\t\tportid);\n\t\tnb_tx_queue = rte_lcore_count();\n\t\tif (nb_tx_queue > get_port_max_tx_queues(portid))\n\t\t\trte_panic(\"Number of lcores %u exceeds max number of tx queues %u\"\n\t\t\t\t\" for port %d\\n\", nb_tx_queue, get_port_max_tx_queues(portid),\n\t\t\t\tportid);\n\t\tprintf(\"Creating queues: nb_rxq=%d nb_txq=%u... \",\n\t\t\tnb_rx_queue, (unsigned)nb_tx_queue );\n\t\tret = rte_eth_dev_configure(portid, nb_rx_queue,\n\t\t\t\t\t(uint16_t)nb_tx_queue, &port_conf);\n\t\tif (ret < 0)\n\t\t\trte_panic(\"Cannot configure device: err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\n\t\trte_eth_macaddr_get(portid, &ports_eth_addr[portid]);\n\t\tprint_ethaddr(\" Address:\", &ports_eth_addr[portid]);\n\t\tprintf(\", \");\n\n\t\t/* init one TX queue per couple (lcore,port) */\n\t\tqueueid = 0;\n\t\tRTE_LCORE_FOREACH(lcoreid) {\n\t\t\tsocketid = (uint8_t)rte_lcore_to_socket_id(lcoreid);\n\t\t\tprintf(\"txq=%u,%d,%d \", lcoreid, queueid, socketid);\n\t\t\tfflush(stdout);\n\t\t\tret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,\n\t\t\t\t\tsocketid,\n\t\t\t\t\tNULL);\n\t\t\tif (ret < 0)\n\t\t\t\trte_panic(\"rte_eth_tx_queue_setup: err=%d, \"\n\t\t\t\t\t\"port=%d\\n\", ret, portid);\n\n\t\t\tqconf = &lcore_conf[lcoreid];\n\t\t\tqconf->tx_queue_id[portid] = queueid;\n\t\t\tqueueid++;\n\t\t}\n\t\tprintf(\"\\n\");\n\t}\n\n\tRTE_LCORE_FOREACH(lcoreid) {\n\t\tqconf = &lcore_conf[lcoreid];\n\t\tprintf(\"\\nInitializing rx queues on lcore %u ... \", lcoreid );\n\t\tfflush(stdout);\n\t\t/* init RX queues */\n\t\tfor(queue = 0; queue < qconf->n_rx_queue; ++queue) {\n\t\t\tportid = qconf->rx_queue_list[queue].port_id;\n\t\t\tqueueid = qconf->rx_queue_list[queue].queue_id;\n\t\t\tsocketid = (uint8_t)rte_lcore_to_socket_id(lcoreid);\n\t\t\tprintf(\"rxq=%d,%d,%d \", portid, queueid, socketid);\n\t\t\tfflush(stdout);\n\n\t\t\tret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd,\n\t\t\t\t\tsocketid,\n\t\t\t\t\tNULL,\n\t\t\t\t\tpktmbuf_pool[socketid]);\n\t\t\tif (ret < 0)\n\t\t\t\trte_panic(\"rte_eth_rx_queue_setup: err=%d,\"\n\t\t\t\t\t\t\"port=%d\\n\", ret, portid);\n\t\t}\n\t}\n\n\tprintf(\"\\n\");\n\n\t/* start ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tif ((enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_panic(\"rte_eth_dev_start: err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\n\t\tprintf(\"done: Port %d \", portid);\n\n\t\t/* get link status */\n\t\trte_eth_link_get(portid, &link);\n\t\tif (link.link_status)\n\t\t\tprintf(\" Link Up - speed %u Mbps - %s\\n\",\n\t\t\t (unsigned) link.link_speed,\n\t\t\t (link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t (\"full-duplex\") : (\"half-duplex\\n\"));\n\t\telse\n\t\t\tprintf(\" Link Down\\n\");\n\t\t/*\n\t\t * If enabled, put device in promiscuous mode.\n\t\t * This allows IO forwarding mode to forward packets\n\t\t * to itself through 2 cross-connected ports of the\n\t\t * target machine.\n\t\t */\n\t\tif (promiscuous_on)\n\t\t\trte_eth_promiscuous_enable(portid);\n\t}\n\tprintf(\"Crypto: Initializing Crypto...\\n\");\n\tif (crypto_init() != 0)\n\t\treturn -1;\n\n\tRTE_LCORE_FOREACH(lcoreid) {\n\t\tif (per_core_crypto_init(lcoreid) != 0) {\n\t printf(\"Crypto: Cannot init lcore crypto on lcore %u\\n\", (unsigned)lcoreid);\n\t\t\treturn -1;\n\t\t}\n\t}\n\tprintf(\"Crypto: Initialization complete\\n\");\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcoreid) {\n\t\tif (rte_eal_wait_lcore(lcoreid) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/exception_path/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifneq ($(CONFIG_RTE_EXEC_ENV),\"linuxapp\")\n$(info This application can only operate in a linuxapp environment, \\\nplease change the definition of the RTE_TARGET environment variable)\nall:\nelse\n\n# binary name\nAPP = exception_path\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n\nendif\n" }, { "path": "examples/exception_path/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/* Macros for printing using RTE_LOG */\n#define RTE_LOGTYPE_APP RTE_LOGTYPE_USER1\n#define FATAL_ERROR(fmt, args...) rte_exit(EXIT_FAILURE, fmt \"\\n\", ##args)\n#define PRINT_INFO(fmt, args...) RTE_LOG(INFO, APP, fmt \"\\n\", ##args)\n\n/* Max ports than can be used (each port is associated with two lcores) */\n#define MAX_PORTS (RTE_MAX_LCORE / 2)\n\n/* Max size of a single packet */\n#define MAX_PACKET_SZ (2048)\n\n/* Size of the data buffer in each mbuf */\n#define MBUF_DATA_SZ (MAX_PACKET_SZ + RTE_PKTMBUF_HEADROOM)\n\n/* Number of mbufs in mempool that is created */\n#define NB_MBUF 8192\n\n/* How many packets to attempt to read from NIC in one go */\n#define PKT_BURST_SZ 32\n\n/* How many objects (mbufs) to keep in per-lcore mempool cache */\n#define MEMPOOL_CACHE_SZ PKT_BURST_SZ\n\n/* Number of RX ring descriptors */\n#define NB_RXD 128\n\n/* Number of TX ring descriptors */\n#define NB_TXD 512\n\n/*\n * RX and TX Prefetch, Host, and Write-back threshold values should be\n * carefully set for optimal performance. Consult the network\n * controller's datasheet and supporting DPDK documentation for guidance\n * on how these parameters should be set.\n */\n\n/* Options for configuring ethernet port */\nstatic const struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.header_split = 0, /* Header Split disabled */\n\t\t.hw_ip_checksum = 0, /* IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /* VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /* Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /* CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\n/* Mempool for mbufs */\nstatic struct rte_mempool * pktmbuf_pool = NULL;\n\n/* Mask of enabled ports */\nstatic uint32_t ports_mask = 0;\n\n/* Mask of cores that read from NIC and write to tap */\nstatic uint64_t input_cores_mask = 0;\n\n/* Mask of cores that read from tap and write to NIC */\nstatic uint64_t output_cores_mask = 0;\n\n/* Array storing port_id that is associated with each lcore */\nstatic uint8_t port_ids[RTE_MAX_LCORE];\n\n/* Structure type for recording lcore-specific stats */\nstruct stats {\n\tuint64_t rx;\n\tuint64_t tx;\n\tuint64_t dropped;\n};\n\n/* Array of lcore-specific stats */\nstatic struct stats lcore_stats[RTE_MAX_LCORE];\n\n/* Print out statistics on packets handled */\nstatic void\nprint_stats(void)\n{\n\tunsigned i;\n\n\tprintf(\"\\n**Exception-Path example application statistics**\\n\"\n\t \"======= ====== ============ ============ ===============\\n\"\n\t \" Lcore Port RX TX Dropped on TX\\n\"\n\t \"------- ------ ------------ ------------ ---------------\\n\");\n\tRTE_LCORE_FOREACH(i) {\n\t\tprintf(\"%6u %7u %13\"PRIu64\" %13\"PRIu64\" %16\"PRIu64\"\\n\",\n\t\t i, (unsigned)port_ids[i],\n\t\t lcore_stats[i].rx, lcore_stats[i].tx,\n\t\t lcore_stats[i].dropped);\n\t}\n\tprintf(\"======= ====== ============ ============ ===============\\n\");\n}\n\n/* Custom handling of signals to handle stats */\nstatic void\nsignal_handler(int signum)\n{\n\t/* When we receive a USR1 signal, print stats */\n\tif (signum == SIGUSR1) {\n\t\tprint_stats();\n\t}\n\n\t/* When we receive a USR2 signal, reset stats */\n\tif (signum == SIGUSR2) {\n\t\tmemset(&lcore_stats, 0, sizeof(lcore_stats));\n\t\tprintf(\"\\n**Statistics have been reset**\\n\");\n\t\treturn;\n\t}\n}\n\n/*\n * Create a tap network interface, or use existing one with same name.\n * If name[0]='\\0' then a name is automatically assigned and returned in name.\n */\nstatic int tap_create(char *name)\n{\n\tstruct ifreq ifr;\n\tint fd, ret;\n\n\tfd = open(\"/dev/net/tun\", O_RDWR);\n\tif (fd < 0)\n\t\treturn fd;\n\n\tmemset(&ifr, 0, sizeof(ifr));\n\n\t/* TAP device without packet information */\n\tifr.ifr_flags = IFF_TAP | IFF_NO_PI;\n\n\tif (name && *name)\n\t\tsnprintf(ifr.ifr_name, IFNAMSIZ, \"%s\", name);\n\n\tret = ioctl(fd, TUNSETIFF, (void *) &ifr);\n\tif (ret < 0) {\n\t\tclose(fd);\n\t\treturn ret;\n\t}\n\n\tif (name)\n\t\tsnprintf(name, IFNAMSIZ, \"%s\", ifr.ifr_name);\n\n\treturn fd;\n}\n\n/* Main processing loop */\nstatic int\nmain_loop(__attribute__((unused)) void *arg)\n{\n\tconst unsigned lcore_id = rte_lcore_id();\n\tchar tap_name[IFNAMSIZ];\n\tint tap_fd;\n\n\tif ((1ULL << lcore_id) & input_cores_mask) {\n\t\t/* Create new tap interface */\n\t\tsnprintf(tap_name, IFNAMSIZ, \"tap_dpdk_%.2u\", lcore_id);\n\t\ttap_fd = tap_create(tap_name);\n\t\tif (tap_fd < 0)\n\t\t\tFATAL_ERROR(\"Could not create tap interface \\\"%s\\\" (%d)\",\n\t\t\t\t\ttap_name, tap_fd);\n\n\t\tPRINT_INFO(\"Lcore %u is reading from port %u and writing to %s\",\n\t\t lcore_id, (unsigned)port_ids[lcore_id], tap_name);\n\t\tfflush(stdout);\n\t\t/* Loop forever reading from NIC and writing to tap */\n\t\tfor (;;) {\n\t\t\tstruct rte_mbuf *pkts_burst[PKT_BURST_SZ];\n\t\t\tunsigned i;\n\t\t\tconst unsigned nb_rx =\n\t\t\t\t\trte_eth_rx_burst(port_ids[lcore_id], 0,\n\t\t\t\t\t pkts_burst, PKT_BURST_SZ);\n\t\t\tlcore_stats[lcore_id].rx += nb_rx;\n\t\t\tfor (i = 0; likely(i < nb_rx); i++) {\n\t\t\t\tstruct rte_mbuf *m = pkts_burst[i];\n\t\t\t\t/* Ignore return val from write() */\n\t\t\t\tint ret = write(tap_fd,\n\t\t\t\t rte_pktmbuf_mtod(m, void*),\n\t\t\t\t rte_pktmbuf_data_len(m));\n\t\t\t\trte_pktmbuf_free(m);\n\t\t\t\tif (unlikely(ret < 0))\n\t\t\t\t\tlcore_stats[lcore_id].dropped++;\n\t\t\t\telse\n\t\t\t\t\tlcore_stats[lcore_id].tx++;\n\t\t\t}\n\t\t}\n\t}\n\telse if ((1ULL << lcore_id) & output_cores_mask) {\n\t\t/* Create new tap interface */\n\t\tsnprintf(tap_name, IFNAMSIZ, \"tap_dpdk_%.2u\", lcore_id);\n\t\ttap_fd = tap_create(tap_name);\n\t\tif (tap_fd < 0)\n\t\t\tFATAL_ERROR(\"Could not create tap interface \\\"%s\\\" (%d)\",\n\t\t\t\t\ttap_name, tap_fd);\n\n\t\tPRINT_INFO(\"Lcore %u is reading from %s and writing to port %u\",\n\t\t lcore_id, tap_name, (unsigned)port_ids[lcore_id]);\n\t\tfflush(stdout);\n\t\t/* Loop forever reading from tap and writing to NIC */\n\t\tfor (;;) {\n\t\t\tint ret;\n\t\t\tstruct rte_mbuf *m = rte_pktmbuf_alloc(pktmbuf_pool);\n\t\t\tif (m == NULL)\n\t\t\t\tcontinue;\n\n\t\t\tret = read(tap_fd, rte_pktmbuf_mtod(m, void *),\n\t\t\t\tMAX_PACKET_SZ);\n\t\t\tlcore_stats[lcore_id].rx++;\n\t\t\tif (unlikely(ret < 0)) {\n\t\t\t\tFATAL_ERROR(\"Reading from %s interface failed\",\n\t\t\t\t tap_name);\n\t\t\t}\n\t\t\tm->nb_segs = 1;\n\t\t\tm->next = NULL;\n\t\t\tm->pkt_len = (uint16_t)ret;\n\t\t\tm->data_len = (uint16_t)ret;\n\t\t\tret = rte_eth_tx_burst(port_ids[lcore_id], 0, &m, 1);\n\t\t\tif (unlikely(ret < 1)) {\n\t\t\t\trte_pktmbuf_free(m);\n\t\t\t\tlcore_stats[lcore_id].dropped++;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tlcore_stats[lcore_id].tx++;\n\t\t\t}\n\t\t}\n\t}\n\telse {\n\t\tPRINT_INFO(\"Lcore %u has nothing to do\", lcore_id);\n\t\treturn 0;\n\t}\n\t/*\n\t * Tap file is closed automatically when program exits. Putting close()\n\t * here will cause the compiler to give an error about unreachable code.\n\t */\n}\n\n/* Display usage instructions */\nstatic void\nprint_usage(const char *prgname)\n{\n\tPRINT_INFO(\"\\nUsage: %s [EAL options] -- -p PORTMASK -i IN_CORES -o OUT_CORES\\n\"\n\t \" -p PORTMASK: hex bitmask of ports to use\\n\"\n\t \" -i IN_CORES: hex bitmask of cores which read from NIC\\n\"\n\t \" -o OUT_CORES: hex bitmask of cores which write to NIC\",\n\t prgname);\n}\n\n/* Convert string to unsigned number. 0 is returned if error occurs */\nstatic uint64_t\nparse_unsigned(const char *portmask)\n{\n\tchar *end = NULL;\n\tuint64_t num;\n\n\tnum = strtoull(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn 0;\n\n\treturn (uint64_t)num;\n}\n\n/* Record affinities between ports and lcores in global port_ids[] array */\nstatic void\nsetup_port_lcore_affinities(void)\n{\n\tunsigned long i;\n\tuint8_t tx_port = 0;\n\tuint8_t rx_port = 0;\n\n\t/* Setup port_ids[] array, and check masks were ok */\n\tRTE_LCORE_FOREACH(i) {\n\t\tif (input_cores_mask & (1ULL << i)) {\n\t\t\t/* Skip ports that are not enabled */\n\t\t\twhile ((ports_mask & (1 << rx_port)) == 0) {\n\t\t\t\trx_port++;\n\t\t\t\tif (rx_port > (sizeof(ports_mask) * 8))\n\t\t\t\t\tgoto fail; /* not enough ports */\n\t\t\t}\n\n\t\t\tport_ids[i] = rx_port++;\n\t\t}\n\t\telse if (output_cores_mask & (1ULL << i)) {\n\t\t\t/* Skip ports that are not enabled */\n\t\t\twhile ((ports_mask & (1 << tx_port)) == 0) {\n\t\t\t\ttx_port++;\n\t\t\t\tif (tx_port > (sizeof(ports_mask) * 8))\n\t\t\t\t\tgoto fail; /* not enough ports */\n\t\t\t}\n\n\t\t\tport_ids[i] = tx_port++;\n\t\t}\n\t}\n\n\tif (rx_port != tx_port)\n\t\tgoto fail; /* uneven number of cores in masks */\n\n\tif (ports_mask & (~((1 << rx_port) - 1)))\n\t\tgoto fail; /* unused ports */\n\n\treturn;\nfail:\n\tFATAL_ERROR(\"Invalid core/port masks specified on command line\");\n}\n\n/* Parse the arguments given in the command line of the application */\nstatic void\nparse_args(int argc, char **argv)\n{\n\tint opt;\n\tconst char *prgname = argv[0];\n\n\t/* Disable printing messages within getopt() */\n\topterr = 0;\n\n\t/* Parse command line */\n\twhile ((opt = getopt(argc, argv, \"i:o:p:\")) != EOF) {\n\t\tswitch (opt) {\n\t\tcase 'i':\n\t\t\tinput_cores_mask = parse_unsigned(optarg);\n\t\t\tbreak;\n\t\tcase 'o':\n\t\t\toutput_cores_mask = parse_unsigned(optarg);\n\t\t\tbreak;\n\t\tcase 'p':\n\t\t\tports_mask = parse_unsigned(optarg);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\tFATAL_ERROR(\"Invalid option specified\");\n\t\t}\n\t}\n\n\t/* Check that options were parsed ok */\n\tif (input_cores_mask == 0) {\n\t\tprint_usage(prgname);\n\t\tFATAL_ERROR(\"IN_CORES not specified correctly\");\n\t}\n\tif (output_cores_mask == 0) {\n\t\tprint_usage(prgname);\n\t\tFATAL_ERROR(\"OUT_CORES not specified correctly\");\n\t}\n\tif (ports_mask == 0) {\n\t\tprint_usage(prgname);\n\t\tFATAL_ERROR(\"PORTMASK not specified correctly\");\n\t}\n\n\tsetup_port_lcore_affinities();\n}\n\n/* Initialise a single port on an Ethernet device */\nstatic void\ninit_port(uint8_t port)\n{\n\tint ret;\n\n\t/* Initialise device and RX/TX queues */\n\tPRINT_INFO(\"Initialising port %u ...\", (unsigned)port);\n\tfflush(stdout);\n\tret = rte_eth_dev_configure(port, 1, 1, &port_conf);\n\tif (ret < 0)\n\t\tFATAL_ERROR(\"Could not configure port%u (%d)\",\n\t\t (unsigned)port, ret);\n\n\tret = rte_eth_rx_queue_setup(port, 0, NB_RXD, rte_eth_dev_socket_id(port),\n\t\t\t\tNULL,\n\t\t\t\tpktmbuf_pool);\n\tif (ret < 0)\n\t\tFATAL_ERROR(\"Could not setup up RX queue for port%u (%d)\",\n\t\t (unsigned)port, ret);\n\n\tret = rte_eth_tx_queue_setup(port, 0, NB_TXD, rte_eth_dev_socket_id(port),\n\t\t\t\tNULL);\n\tif (ret < 0)\n\t\tFATAL_ERROR(\"Could not setup up TX queue for port%u (%d)\",\n\t\t (unsigned)port, ret);\n\n\tret = rte_eth_dev_start(port);\n\tif (ret < 0)\n\t\tFATAL_ERROR(\"Could not start port%u (%d)\", (unsigned)port, ret);\n\n\trte_eth_promiscuous_enable(port);\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\n/* Initialise ports/queues etc. and start main loop on each core */\nint\nmain(int argc, char** argv)\n{\n\tint ret;\n\tunsigned i,high_port;\n\tuint8_t nb_sys_ports, port;\n\n\t/* Associate signal_hanlder function with USR signals */\n\tsignal(SIGUSR1, signal_handler);\n\tsignal(SIGUSR2, signal_handler);\n\n\t/* Initialise EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\tFATAL_ERROR(\"Could not initialise EAL (%d)\", ret);\n\targc -= ret;\n\targv += ret;\n\n\t/* Parse application arguments (after the EAL ones) */\n\tparse_args(argc, argv);\n\n\t/* Create the mbuf pool */\n\tpktmbuf_pool = rte_pktmbuf_pool_create(\"mbuf_pool\", NB_MBUF,\n\t\t\tMEMPOOL_CACHE_SZ, 0, MBUF_DATA_SZ, rte_socket_id());\n\tif (pktmbuf_pool == NULL) {\n\t\tFATAL_ERROR(\"Could not initialise mbuf pool\");\n\t\treturn -1;\n\t}\n\n\t/* Get number of ports found in scan */\n\tnb_sys_ports = rte_eth_dev_count();\n\tif (nb_sys_ports == 0)\n\t\tFATAL_ERROR(\"No supported Ethernet device found\");\n\t/* Find highest port set in portmask */\n\tfor (high_port = (sizeof(ports_mask) * 8) - 1;\n\t\t\t(high_port != 0) && !(ports_mask & (1 << high_port));\n\t\t\thigh_port--)\n\t\t; /* empty body */\n\tif (high_port > nb_sys_ports)\n\t\tFATAL_ERROR(\"Port mask requires more ports than available\");\n\n\t/* Initialise each port */\n\tfor (port = 0; port < nb_sys_ports; port++) {\n\t\t/* Skip ports that are not enabled */\n\t\tif ((ports_mask & (1 << port)) == 0) {\n\t\t\tcontinue;\n\t\t}\n\t\tinit_port(port);\n\t}\n\tcheck_all_ports_link_status(nb_sys_ports, ports_mask);\n\n\t/* Launch per-lcore function on every lcore */\n\trte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(i) {\n\t\tif (rte_eal_wait_lcore(i) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/helloworld/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = helloworld\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/helloworld/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\nstatic int\nlcore_hello(__attribute__((unused)) void *arg)\n{\n\tunsigned lcore_id;\n\tlcore_id = rte_lcore_id();\n\tprintf(\"hello from core %u\\n\", lcore_id);\n\treturn 0;\n}\n\nint\nmain(int argc, char **argv)\n{\n\tint ret;\n\tunsigned lcore_id;\n\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_panic(\"Cannot init EAL\\n\");\n\n\t/* call lcore_hello() on every slave lcore */\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\trte_eal_remote_launch(lcore_hello, NULL, lcore_id);\n\t}\n\n\t/* call it on master lcore too */\n\tlcore_hello(NULL);\n\n\trte_eal_mp_wait_lcore();\n\treturn 0;\n}\n" }, { "path": "examples/ip_fragmentation/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = ip_fragmentation\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/ip_fragmentation/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#define RTE_LOGTYPE_IP_FRAG RTE_LOGTYPE_USER1\n\n/* allow max jumbo frame 9.5 KB */\n#define JUMBO_FRAME_MAX_SIZE\t0x2600\n\n#define\tROUNDUP_DIV(a, b)\t(((a) + (b) - 1) / (b))\n\n/*\n * Default byte size for the IPv6 Maximum Transfer Unit (MTU).\n * This value includes the size of IPv6 header.\n */\n#define\tIPV4_MTU_DEFAULT\tETHER_MTU\n#define\tIPV6_MTU_DEFAULT\tETHER_MTU\n\n/*\n * Default payload in bytes for the IPv6 packet.\n */\n#define\tIPV4_DEFAULT_PAYLOAD\t(IPV4_MTU_DEFAULT - sizeof(struct ipv4_hdr))\n#define\tIPV6_DEFAULT_PAYLOAD\t(IPV6_MTU_DEFAULT - sizeof(struct ipv6_hdr))\n\n/*\n * Max number of fragments per packet expected - defined by config file.\n */\n#define\tMAX_PACKET_FRAG RTE_LIBRTE_IP_FRAG_MAX_FRAG\n\n#define NB_MBUF 8192\n\n#define MAX_PKT_BURST\t32\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n/* Configure how many packets ahead to prefetch, when reading packets */\n#define PREFETCH_OFFSET\t3\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n/* ethernet addresses of ports */\nstatic struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];\n\n#ifndef IPv4_BYTES\n#define IPv4_BYTES_FMT \"%\" PRIu8 \".%\" PRIu8 \".%\" PRIu8 \".%\" PRIu8\n#define IPv4_BYTES(addr) \\\n\t\t(uint8_t) (((addr) >> 24) & 0xFF),\\\n\t\t(uint8_t) (((addr) >> 16) & 0xFF),\\\n\t\t(uint8_t) (((addr) >> 8) & 0xFF),\\\n\t\t(uint8_t) ((addr) & 0xFF)\n#endif\n\n#ifndef IPv6_BYTES\n#define IPv6_BYTES_FMT \"%02x%02x:%02x%02x:%02x%02x:%02x%02x:\"\\\n \"%02x%02x:%02x%02x:%02x%02x:%02x%02x\"\n#define IPv6_BYTES(addr) \\\n\taddr[0], addr[1], addr[2], addr[3], \\\n\taddr[4], addr[5], addr[6], addr[7], \\\n\taddr[8], addr[9], addr[10], addr[11],\\\n\taddr[12], addr[13],addr[14], addr[15]\n#endif\n\n#define IPV6_ADDR_LEN 16\n\n/* mask of enabled ports */\nstatic int enabled_port_mask = 0;\n\nstatic int rx_queue_per_lcore = 1;\n\n#define MBUF_TABLE_SIZE (2 * MAX(MAX_PKT_BURST, MAX_PACKET_FRAG))\n\nstruct mbuf_table {\n\tuint16_t len;\n\tstruct rte_mbuf *m_table[MBUF_TABLE_SIZE];\n};\n\nstruct rx_queue {\n\tstruct rte_mempool *direct_pool;\n\tstruct rte_mempool *indirect_pool;\n\tstruct rte_lpm *lpm;\n\tstruct rte_lpm6 *lpm6;\n\tuint8_t portid;\n};\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT 16\nstruct lcore_queue_conf {\n\tuint16_t n_rx_queue;\n\tuint16_t tx_queue_id[RTE_MAX_ETHPORTS];\n\tstruct rx_queue rx_queue_list[MAX_RX_QUEUE_PER_LCORE];\n\tstruct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];\n} __rte_cache_aligned;\nstruct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];\n\nstatic const struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.max_rx_pkt_len = JUMBO_FRAME_MAX_SIZE,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 1, /**< IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 1, /**< Jumbo Frame Support enabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\n/*\n * IPv4 forwarding table\n */\nstruct l3fwd_ipv4_route {\n\tuint32_t ip;\n\tuint8_t depth;\n\tuint8_t if_out;\n};\n\nstruct l3fwd_ipv4_route l3fwd_ipv4_route_array[] = {\n\t\t{IPv4(100,10,0,0), 16, 0},\n\t\t{IPv4(100,20,0,0), 16, 1},\n\t\t{IPv4(100,30,0,0), 16, 2},\n\t\t{IPv4(100,40,0,0), 16, 3},\n\t\t{IPv4(100,50,0,0), 16, 4},\n\t\t{IPv4(100,60,0,0), 16, 5},\n\t\t{IPv4(100,70,0,0), 16, 6},\n\t\t{IPv4(100,80,0,0), 16, 7},\n};\n\n/*\n * IPv6 forwarding table\n */\n\nstruct l3fwd_ipv6_route {\n\tuint8_t ip[IPV6_ADDR_LEN];\n\tuint8_t depth;\n\tuint8_t if_out;\n};\n\nstatic struct l3fwd_ipv6_route l3fwd_ipv6_route_array[] = {\n\t{{1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 0},\n\t{{2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 1},\n\t{{3,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 2},\n\t{{4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 3},\n\t{{5,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 4},\n\t{{6,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 5},\n\t{{7,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 6},\n\t{{8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 7},\n};\n\n#define LPM_MAX_RULES 1024\n#define LPM6_MAX_RULES 1024\n#define LPM6_NUMBER_TBL8S (1 << 16)\n\nstruct rte_lpm6_config lpm6_config = {\n\t\t.max_rules = LPM6_MAX_RULES,\n\t\t.number_tbl8s = LPM6_NUMBER_TBL8S,\n\t\t.flags = 0\n};\n\nstatic struct rte_mempool *socket_direct_pool[RTE_MAX_NUMA_NODES];\nstatic struct rte_mempool *socket_indirect_pool[RTE_MAX_NUMA_NODES];\nstatic struct rte_lpm *socket_lpm[RTE_MAX_NUMA_NODES];\nstatic struct rte_lpm6 *socket_lpm6[RTE_MAX_NUMA_NODES];\n\n/* Send burst of packets on an output interface */\nstatic inline int\nsend_burst(struct lcore_queue_conf *qconf, uint16_t n, uint8_t port)\n{\n\tstruct rte_mbuf **m_table;\n\tint ret;\n\tuint16_t queueid;\n\n\tqueueid = qconf->tx_queue_id[port];\n\tm_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;\n\n\tret = rte_eth_tx_burst(port, queueid, m_table, n);\n\tif (unlikely(ret < n)) {\n\t\tdo {\n\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t} while (++ret < n);\n\t}\n\n\treturn 0;\n}\n\nstatic inline void\nl3fwd_simple_forward(struct rte_mbuf *m, struct lcore_queue_conf *qconf,\n\t\tuint8_t queueid, uint8_t port_in)\n{\n\tstruct rx_queue *rxq;\n\tuint32_t i, len;\n\tuint8_t next_hop, port_out, ipv6;\n\tint32_t len2;\n\n\tipv6 = 0;\n\trxq = &qconf->rx_queue_list[queueid];\n\n\t/* by default, send everything back to the source port */\n\tport_out = port_in;\n\n\t/* Remove the Ethernet header and trailer from the input packet */\n\trte_pktmbuf_adj(m, (uint16_t)sizeof(struct ether_hdr));\n\n\t/* Build transmission burst */\n\tlen = qconf->tx_mbufs[port_out].len;\n\n\t/* if this is an IPv4 packet */\n#ifdef RTE_NEXT_ABI\n\tif (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {\n#else\n\tif (m->ol_flags & PKT_RX_IPV4_HDR) {\n#endif\n\t\tstruct ipv4_hdr *ip_hdr;\n\t\tuint32_t ip_dst;\n\t\t/* Read the lookup key (i.e. ip_dst) from the input packet */\n\t\tip_hdr = rte_pktmbuf_mtod(m, struct ipv4_hdr *);\n\t\tip_dst = rte_be_to_cpu_32(ip_hdr->dst_addr);\n\n\t\t/* Find destination port */\n\t\tif (rte_lpm_lookup(rxq->lpm, ip_dst, &next_hop) == 0 &&\n\t\t\t\t(enabled_port_mask & 1 << next_hop) != 0) {\n\t\t\tport_out = next_hop;\n\n\t\t\t/* Build transmission burst for new port */\n\t\t\tlen = qconf->tx_mbufs[port_out].len;\n\t\t}\n\n\t\t/* if we don't need to do any fragmentation */\n\t\tif (likely (IPV4_MTU_DEFAULT >= m->pkt_len)) {\n\t\t\tqconf->tx_mbufs[port_out].m_table[len] = m;\n\t\t\tlen2 = 1;\n\t\t} else {\n\t\t\tlen2 = rte_ipv4_fragment_packet(m,\n\t\t\t\t&qconf->tx_mbufs[port_out].m_table[len],\n\t\t\t\t(uint16_t)(MBUF_TABLE_SIZE - len),\n\t\t\t\tIPV4_MTU_DEFAULT,\n\t\t\t\trxq->direct_pool, rxq->indirect_pool);\n\n\t\t\t/* Free input packet */\n\t\t\trte_pktmbuf_free(m);\n\n\t\t\t/* If we fail to fragment the packet */\n\t\t\tif (unlikely (len2 < 0))\n\t\t\t\treturn;\n\t\t}\n#ifdef RTE_NEXT_ABI\n\t} else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {\n\t\t/* if this is an IPv6 packet */\n#else\n\t}\n\t/* if this is an IPv6 packet */\n\telse if (m->ol_flags & PKT_RX_IPV6_HDR) {\n#endif\n\t\tstruct ipv6_hdr *ip_hdr;\n\n\t\tipv6 = 1;\n\n\t\t/* Read the lookup key (i.e. ip_dst) from the input packet */\n\t\tip_hdr = rte_pktmbuf_mtod(m, struct ipv6_hdr *);\n\n\t\t/* Find destination port */\n\t\tif (rte_lpm6_lookup(rxq->lpm6, ip_hdr->dst_addr, &next_hop) == 0 &&\n\t\t\t\t(enabled_port_mask & 1 << next_hop) != 0) {\n\t\t\tport_out = next_hop;\n\n\t\t\t/* Build transmission burst for new port */\n\t\t\tlen = qconf->tx_mbufs[port_out].len;\n\t\t}\n\n\t\t/* if we don't need to do any fragmentation */\n\t\tif (likely (IPV6_MTU_DEFAULT >= m->pkt_len)) {\n\t\t\tqconf->tx_mbufs[port_out].m_table[len] = m;\n\t\t\tlen2 = 1;\n\t\t} else {\n\t\t\tlen2 = rte_ipv6_fragment_packet(m,\n\t\t\t\t&qconf->tx_mbufs[port_out].m_table[len],\n\t\t\t\t(uint16_t)(MBUF_TABLE_SIZE - len),\n\t\t\t\tIPV6_MTU_DEFAULT,\n\t\t\t\trxq->direct_pool, rxq->indirect_pool);\n\n\t\t\t/* Free input packet */\n\t\t\trte_pktmbuf_free(m);\n\n\t\t\t/* If we fail to fragment the packet */\n\t\t\tif (unlikely (len2 < 0))\n\t\t\t\treturn;\n\t\t}\n\t}\n\t/* else, just forward the packet */\n\telse {\n\t\tqconf->tx_mbufs[port_out].m_table[len] = m;\n\t\tlen2 = 1;\n\t}\n\n\tfor (i = len; i < len + len2; i ++) {\n\t\tvoid *d_addr_bytes;\n\n\t\tm = qconf->tx_mbufs[port_out].m_table[i];\n\t\tstruct ether_hdr *eth_hdr = (struct ether_hdr *)\n\t\t\trte_pktmbuf_prepend(m, (uint16_t)sizeof(struct ether_hdr));\n\t\tif (eth_hdr == NULL) {\n\t\t\trte_panic(\"No headroom in mbuf.\\n\");\n\t\t}\n\n\t\tm->l2_len = sizeof(struct ether_hdr);\n\n\t\t/* 02:00:00:00:00:xx */\n\t\td_addr_bytes = ð_hdr->d_addr.addr_bytes[0];\n\t\t*((uint64_t *)d_addr_bytes) = 0x000000000002 + ((uint64_t)port_out << 40);\n\n\t\t/* src addr */\n\t\tether_addr_copy(&ports_eth_addr[port_out], ð_hdr->s_addr);\n\t\tif (ipv6)\n\t\t\teth_hdr->ether_type = rte_be_to_cpu_16(ETHER_TYPE_IPv6);\n\t\telse\n\t\t\teth_hdr->ether_type = rte_be_to_cpu_16(ETHER_TYPE_IPv4);\n\t}\n\n\tlen += len2;\n\n\tif (likely(len < MAX_PKT_BURST)) {\n\t\tqconf->tx_mbufs[port_out].len = (uint16_t)len;\n\t\treturn;\n\t}\n\n\t/* Transmit packets */\n\tsend_burst(qconf, (uint16_t)len, port_out);\n\tqconf->tx_mbufs[port_out].len = 0;\n}\n\n/* main processing loop */\nstatic int\nmain_loop(__attribute__((unused)) void *dummy)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tunsigned lcore_id;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc;\n\tint i, j, nb_rx;\n\tuint8_t portid;\n\tstruct lcore_queue_conf *qconf;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\tprev_tsc = 0;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_queue_conf[lcore_id];\n\n\tif (qconf->n_rx_queue == 0) {\n\t\tRTE_LOG(INFO, IP_FRAG, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn 0;\n\t}\n\n\tRTE_LOG(INFO, IP_FRAG, \"entering main loop on lcore %u\\n\", lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_queue; i++) {\n\n\t\tportid = qconf->rx_queue_list[i].portid;\n\t\tRTE_LOG(INFO, IP_FRAG, \" -- lcoreid=%u portid=%d\\n\", lcore_id,\n\t\t\t\t(int) portid);\n\t}\n\n\twhile (1) {\n\n\t\tcur_tsc = rte_rdtsc();\n\n\t\t/*\n\t\t * TX burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\t/*\n\t\t\t * This could be optimized (use queueid instead of\n\t\t\t * portid), but it is not called so often\n\t\t\t */\n\t\t\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t\t\tif (qconf->tx_mbufs[portid].len == 0)\n\t\t\t\t\tcontinue;\n\t\t\t\tsend_burst(&lcore_queue_conf[lcore_id],\n\t\t\t\t\t qconf->tx_mbufs[portid].len,\n\t\t\t\t\t portid);\n\t\t\t\tqconf->tx_mbufs[portid].len = 0;\n\t\t\t}\n\n\t\t\tprev_tsc = cur_tsc;\n\t\t}\n\n\t\t/*\n\t\t * Read packet from RX queues\n\t\t */\n\t\tfor (i = 0; i < qconf->n_rx_queue; i++) {\n\n\t\t\tportid = qconf->rx_queue_list[i].portid;\n\t\t\tnb_rx = rte_eth_rx_burst(portid, 0, pkts_burst,\n\t\t\t\t\t\t MAX_PKT_BURST);\n\n\t\t\t/* Prefetch first packets */\n\t\t\tfor (j = 0; j < PREFETCH_OFFSET && j < nb_rx; j++) {\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(\n\t\t\t\t\t\tpkts_burst[j], void *));\n\t\t\t}\n\n\t\t\t/* Prefetch and forward already prefetched packets */\n\t\t\tfor (j = 0; j < (nb_rx - PREFETCH_OFFSET); j++) {\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(pkts_burst[\n\t\t\t\t\t\tj + PREFETCH_OFFSET], void *));\n\t\t\t\tl3fwd_simple_forward(pkts_burst[j], qconf, i, portid);\n\t\t\t}\n\n\t\t\t/* Forward remaining prefetched packets */\n\t\t\tfor (; j < nb_rx; j++) {\n\t\t\t\tl3fwd_simple_forward(pkts_burst[j], qconf, i, portid);\n\t\t\t}\n\t\t}\n\t}\n}\n\n/* display usage */\nstatic void\nprint_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK [-q NQ]\\n\"\n\t \" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t \" -q NQ: number of queue (=ports) per lcore (default is 1)\\n\",\n\t prgname);\n}\n\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\nstatic int\nparse_nqueue(const char *q_arg)\n{\n\tchar *end = NULL;\n\tunsigned long n;\n\n\t/* parse hexadecimal string */\n\tn = strtoul(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\tif (n == 0)\n\t\treturn -1;\n\tif (n >= MAX_RX_QUEUE_PER_LCORE)\n\t\treturn -1;\n\n\treturn n;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:q:\",\n\t\t\t\t lgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask < 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* nqueue */\n\t\tcase 'q':\n\t\t\trx_queue_per_lcore = parse_nqueue(optarg);\n\t\t\tif (rx_queue_per_lcore < 0) {\n\t\t\t\tprintf(\"invalid queue number\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tprint_usage(prgname);\n\t\t\treturn -1;\n\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (enabled_port_mask == 0) {\n\t\tprintf(\"portmask not specified\\n\");\n\t\tprint_usage(prgname);\n\t\treturn -1;\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\nstatic void\nprint_ethaddr(const char *name, struct ether_addr *eth_addr)\n{\n\tchar buf[ETHER_ADDR_FMT_SIZE];\n\tether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);\n\tprintf(\"%s%s\", name, buf);\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"\\ndone\\n\");\n\t\t}\n\t}\n}\n\nstatic int\ninit_routing_table(void)\n{\n\tstruct rte_lpm *lpm;\n\tstruct rte_lpm6 *lpm6;\n\tint socket, ret;\n\tunsigned i;\n\n\tfor (socket = 0; socket < RTE_MAX_NUMA_NODES; socket++) {\n\t\tif (socket_lpm[socket]) {\n\t\t\tlpm = socket_lpm[socket];\n\t\t\t/* populate the LPM table */\n\t\t\tfor (i = 0; i < RTE_DIM(l3fwd_ipv4_route_array); i++) {\n\t\t\t\tret = rte_lpm_add(lpm,\n\t\t\t\t\tl3fwd_ipv4_route_array[i].ip,\n\t\t\t\t\tl3fwd_ipv4_route_array[i].depth,\n\t\t\t\t\tl3fwd_ipv4_route_array[i].if_out);\n\n\t\t\t\tif (ret < 0) {\n\t\t\t\t\tRTE_LOG(ERR, IP_FRAG, \"Unable to add entry %i to the l3fwd \"\n\t\t\t\t\t\t\"LPM table\\n\", i);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\n\t\t\t\tRTE_LOG(INFO, IP_FRAG, \"Socket %i: adding route \" IPv4_BYTES_FMT\n\t\t\t\t\t\t\"/%d (port %d)\\n\",\n\t\t\t\t\tsocket,\n\t\t\t\t\tIPv4_BYTES(l3fwd_ipv4_route_array[i].ip),\n\t\t\t\t\tl3fwd_ipv4_route_array[i].depth,\n\t\t\t\t\tl3fwd_ipv4_route_array[i].if_out);\n\t\t\t}\n\t\t}\n\n\t\tif (socket_lpm6[socket]) {\n\t\t\tlpm6 = socket_lpm6[socket];\n\t\t\t/* populate the LPM6 table */\n\t\t\tfor (i = 0; i < RTE_DIM(l3fwd_ipv6_route_array); i++) {\n\t\t\t\tret = rte_lpm6_add(lpm6,\n\t\t\t\t\tl3fwd_ipv6_route_array[i].ip,\n\t\t\t\t\tl3fwd_ipv6_route_array[i].depth,\n\t\t\t\t\tl3fwd_ipv6_route_array[i].if_out);\n\n\t\t\t\tif (ret < 0) {\n\t\t\t\t\tRTE_LOG(ERR, IP_FRAG, \"Unable to add entry %i to the l3fwd \"\n\t\t\t\t\t\t\"LPM6 table\\n\", i);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\n\t\t\t\tRTE_LOG(INFO, IP_FRAG, \"Socket %i: adding route \" IPv6_BYTES_FMT\n\t\t\t\t\t\t\"/%d (port %d)\\n\",\n\t\t\t\t\tsocket,\n\t\t\t\t\tIPv6_BYTES(l3fwd_ipv6_route_array[i].ip),\n\t\t\t\t\tl3fwd_ipv6_route_array[i].depth,\n\t\t\t\t\tl3fwd_ipv6_route_array[i].if_out);\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\ninit_mem(void)\n{\n\tchar buf[PATH_MAX];\n\tstruct rte_mempool *mp;\n\tstruct rte_lpm *lpm;\n\tstruct rte_lpm6 *lpm6;\n\tint socket;\n\tunsigned lcore_id;\n\n\t/* traverse through lcores and initialize structures on each socket */\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\tcontinue;\n\n\t\tsocket = rte_lcore_to_socket_id(lcore_id);\n\n\t\tif (socket == SOCKET_ID_ANY)\n\t\t\tsocket = 0;\n\n\t\tif (socket_direct_pool[socket] == NULL) {\n\t\t\tRTE_LOG(INFO, IP_FRAG, \"Creating direct mempool on socket %i\\n\",\n\t\t\t\t\tsocket);\n\t\t\tsnprintf(buf, sizeof(buf), \"pool_direct_%i\", socket);\n\n\t\t\tmp = rte_pktmbuf_pool_create(buf, NB_MBUF, 32,\n\t\t\t\t0, RTE_MBUF_DEFAULT_BUF_SIZE, socket);\n\t\t\tif (mp == NULL) {\n\t\t\t\tRTE_LOG(ERR, IP_FRAG, \"Cannot create direct mempool\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tsocket_direct_pool[socket] = mp;\n\t\t}\n\n\t\tif (socket_indirect_pool[socket] == NULL) {\n\t\t\tRTE_LOG(INFO, IP_FRAG, \"Creating indirect mempool on socket %i\\n\",\n\t\t\t\t\tsocket);\n\t\t\tsnprintf(buf, sizeof(buf), \"pool_indirect_%i\", socket);\n\n\t\t\tmp = rte_pktmbuf_pool_create(buf, NB_MBUF, 32, 0, 0,\n\t\t\t\tsocket);\n\t\t\tif (mp == NULL) {\n\t\t\t\tRTE_LOG(ERR, IP_FRAG, \"Cannot create indirect mempool\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tsocket_indirect_pool[socket] = mp;\n\t\t}\n\n\t\tif (socket_lpm[socket] == NULL) {\n\t\t\tRTE_LOG(INFO, IP_FRAG, \"Creating LPM table on socket %i\\n\", socket);\n\t\t\tsnprintf(buf, sizeof(buf), \"IP_FRAG_LPM_%i\", socket);\n\n\t\t\tlpm = rte_lpm_create(buf, socket, LPM_MAX_RULES, 0);\n\t\t\tif (lpm == NULL) {\n\t\t\t\tRTE_LOG(ERR, IP_FRAG, \"Cannot create LPM table\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tsocket_lpm[socket] = lpm;\n\t\t}\n\n\t\tif (socket_lpm6[socket] == NULL) {\n\t\t\tRTE_LOG(INFO, IP_FRAG, \"Creating LPM6 table on socket %i\\n\", socket);\n\t\t\tsnprintf(buf, sizeof(buf), \"IP_FRAG_LPM_%i\", socket);\n\n\t\t\tlpm6 = rte_lpm6_create(\"IP_FRAG_LPM6\", socket, &lpm6_config);\n\t\t\tif (lpm6 == NULL) {\n\t\t\t\tRTE_LOG(ERR, IP_FRAG, \"Cannot create LPM table\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tsocket_lpm6[socket] = lpm6;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_queue_conf *qconf;\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_txconf *txconf;\n\tstruct rx_queue *rxq;\n\tint socket, ret;\n\tunsigned nb_ports;\n\tuint16_t queueid = 0;\n\tunsigned lcore_id = 0, rx_lcore_id = 0;\n\tuint32_t n_tx_queue, nb_lcores;\n\tuint8_t portid;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"rte_eal_init failed\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid arguments\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\telse if (nb_ports == 0)\n\t\trte_exit(EXIT_FAILURE, \"No ports found!\\n\");\n\n\tnb_lcores = rte_lcore_count();\n\n\t/* initialize structures (mempools, lpm etc.) */\n\tif (init_mem() < 0)\n\t\trte_panic(\"Cannot initialize memory structures!\\n\");\n\n\t/* check if portmask has non-existent ports */\n\tif (enabled_port_mask & ~(RTE_LEN2MASK(nb_ports, unsigned)))\n\t\trte_exit(EXIT_FAILURE, \"Non-existent ports in portmask!\\n\");\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"Skipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\n\t\tqconf = &lcore_queue_conf[rx_lcore_id];\n\n\t\t/* get the lcore_id for this port */\n\t\twhile (rte_lcore_is_enabled(rx_lcore_id) == 0 ||\n\t\t qconf->n_rx_queue == (unsigned)rx_queue_per_lcore) {\n\n\t\t\trx_lcore_id ++;\n\t\t\tif (rx_lcore_id >= RTE_MAX_LCORE)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Not enough cores\\n\");\n\n\t\t\tqconf = &lcore_queue_conf[rx_lcore_id];\n\t\t}\n\n\t\tsocket = (int) rte_lcore_to_socket_id(rx_lcore_id);\n\t\tif (socket == SOCKET_ID_ANY)\n\t\t\tsocket = 0;\n\n\t\trxq = &qconf->rx_queue_list[qconf->n_rx_queue];\n\t\trxq->portid = portid;\n\t\trxq->direct_pool = socket_direct_pool[socket];\n\t\trxq->indirect_pool = socket_indirect_pool[socket];\n\t\trxq->lpm = socket_lpm[socket];\n\t\trxq->lpm6 = socket_lpm6[socket];\n\t\tqconf->n_rx_queue++;\n\n\t\t/* init port */\n\t\tprintf(\"Initializing port %d on lcore %u...\", portid,\n\t\t rx_lcore_id);\n\t\tfflush(stdout);\n\n\t\tn_tx_queue = nb_lcores;\n\t\tif (n_tx_queue > MAX_TX_QUEUE_PER_PORT)\n\t\t\tn_tx_queue = MAX_TX_QUEUE_PER_PORT;\n\t\tret = rte_eth_dev_configure(portid, 1, (uint16_t)n_tx_queue,\n\t\t\t\t\t &port_conf);\n\t\tif (ret < 0) {\n\t\t\tprintf(\"\\n\");\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot configure device: \"\n\t\t\t\t\"err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\t\t}\n\n\t\t/* init one RX queue */\n\t\tret = rte_eth_rx_queue_setup(portid, 0, nb_rxd,\n\t\t\t\t\t socket, NULL,\n\t\t\t\t\t socket_direct_pool[socket]);\n\t\tif (ret < 0) {\n\t\t\tprintf(\"\\n\");\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup: \"\n\t\t\t\t\"err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\t\t}\n\n\t\trte_eth_macaddr_get(portid, &ports_eth_addr[portid]);\n\t\tprint_ethaddr(\" Address:\", &ports_eth_addr[portid]);\n\t\tprintf(\"\\n\");\n\n\t\t/* init one TX queue per couple (lcore,port) */\n\t\tqueueid = 0;\n\t\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tsocket = (int) rte_lcore_to_socket_id(lcore_id);\n\t\t\tprintf(\"txq=%u,%d \", lcore_id, queueid);\n\t\t\tfflush(stdout);\n\n\t\t\trte_eth_dev_info_get(portid, &dev_info);\n\t\t\ttxconf = &dev_info.default_txconf;\n\t\t\ttxconf->txq_flags = 0;\n\t\t\tret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,\n\t\t\t\t\t\t socket, txconf);\n\t\t\tif (ret < 0) {\n\t\t\t\tprintf(\"\\n\");\n\t\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup: \"\n\t\t\t\t\t\"err=%d, port=%d\\n\", ret, portid);\n\t\t\t}\n\n\t\t\tqconf = &lcore_queue_conf[lcore_id];\n\t\t\tqconf->tx_queue_id[portid] = queueid;\n\t\t\tqueueid++;\n\t\t}\n\n\t\tprintf(\"\\n\");\n\t}\n\n\tprintf(\"\\n\");\n\n\t/* start ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tcontinue;\n\t\t}\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_dev_start: err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\n\t\trte_eth_promiscuous_enable(portid);\n\t}\n\n\tif (init_routing_table() < 0)\n\t\trte_exit(EXIT_FAILURE, \"Cannot init routing table\\n\");\n\n\tcheck_all_ports_link_status((uint8_t)nb_ports, enabled_port_mask);\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/ip_pipeline/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overridden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\nDIRS-(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = ip_pipeline\n\nVPATH += $(SRCDIR)/pipeline\n\nINC += $(wildcard *.h) $(wildcard pipeline/*.h)\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) := main.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += config_parse.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += config_parse_tm.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += config_check.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += init.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += thread.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += cpu_core_map.c\n\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline_common_be.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline_common_fe.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline_master_be.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline_master.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline_passthrough_be.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline_passthrough.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline_firewall_be.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline_firewall.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline_flow_classification_be.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline_flow_classification.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline_routing_be.c\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) += pipeline_routing.c\n\nCFLAGS += -I$(SRCDIR) -I$(SRCDIR)/pipeline\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS) -Wno-error=unused-function -Wno-error=unused-variable\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/ip_pipeline/app.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_APP_H__\n#define __INCLUDE_APP_H__\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"cpu_core_map.h\"\n#include \"pipeline.h\"\n\n#define APP_PARAM_NAME_SIZE PIPELINE_NAME_SIZE\n\nstruct app_mempool_params {\n\tchar *name;\n\tuint32_t parsed;\n\tuint32_t buffer_size;\n\tuint32_t pool_size;\n\tuint32_t cache_size;\n\tuint32_t cpu_socket_id;\n};\n\nstruct app_link_params {\n\tchar *name;\n\tuint32_t parsed;\n\tuint32_t pmd_id; /* Generated based on port mask */\n\tuint32_t arp_q; /* 0 = Disabled (packets go to default queue 0) */\n\tuint32_t tcp_syn_local_q; /* 0 = Disabled (pkts go to default queue) */\n\tuint32_t ip_local_q; /* 0 = Disabled (pkts go to default queue 0) */\n\tuint32_t tcp_local_q; /* 0 = Disabled (pkts go to default queue 0) */\n\tuint32_t udp_local_q; /* 0 = Disabled (pkts go to default queue 0) */\n\tuint32_t sctp_local_q; /* 0 = Disabled (pkts go to default queue 0) */\n\tuint32_t state; /* DOWN = 0, UP = 1 */\n\tuint32_t ip; /* 0 = Invalid */\n\tuint32_t depth; /* Valid only when IP is valid */\n\tuint64_t mac_addr; /* Read from HW */\n\n\tstruct rte_eth_conf conf;\n\tuint8_t promisc;\n};\n\nstruct app_pktq_hwq_in_params {\n\tchar *name;\n\tuint32_t parsed;\n\tuint32_t mempool_id; /* Position in the app->mempool_params */\n\tuint32_t size;\n\tuint32_t burst;\n\n\tstruct rte_eth_rxconf conf;\n};\n\nstruct app_pktq_hwq_out_params {\n\tchar *name;\n\tuint32_t parsed;\n\tuint32_t size;\n\tuint32_t burst;\n\tuint32_t dropless;\n\tuint64_t n_retries;\n\tstruct rte_eth_txconf conf;\n};\n\nstruct app_pktq_swq_params {\n\tchar *name;\n\tuint32_t parsed;\n\tuint32_t size;\n\tuint32_t burst_read;\n\tuint32_t burst_write;\n\tuint32_t dropless;\n\tuint64_t n_retries;\n\tuint32_t cpu_socket_id;\n};\n\n#ifndef APP_FILE_NAME_SIZE\n#define APP_FILE_NAME_SIZE 256\n#endif\n\n#ifndef APP_MAX_SCHED_SUBPORTS\n#define APP_MAX_SCHED_SUBPORTS 8\n#endif\n\n#ifndef APP_MAX_SCHED_PIPES\n#define APP_MAX_SCHED_PIPES 4096\n#endif\n\nstruct app_pktq_tm_params {\n\tchar *name;\n\tuint32_t parsed;\n\tconst char *file_name;\n\tstruct rte_sched_port_params sched_port_params;\n\tstruct rte_sched_subport_params\n\t\tsched_subport_params[APP_MAX_SCHED_SUBPORTS];\n\tstruct rte_sched_pipe_params\n\t\tsched_pipe_profiles[RTE_SCHED_PIPE_PROFILES_PER_PORT];\n\tint sched_pipe_to_profile[APP_MAX_SCHED_SUBPORTS * APP_MAX_SCHED_PIPES];\n\tuint32_t burst_read;\n\tuint32_t burst_write;\n};\n\nstruct app_pktq_source_params {\n\tchar *name;\n\tuint32_t parsed;\n\tuint32_t mempool_id; /* Position in the app->mempool_params array */\n\tuint32_t burst;\n};\n\nstruct app_pktq_sink_params {\n\tchar *name;\n\tuint8_t parsed;\n};\n\nstruct app_msgq_params {\n\tchar *name;\n\tuint32_t parsed;\n\tuint32_t size;\n\tuint32_t cpu_socket_id;\n};\n\nenum app_pktq_in_type {\n\tAPP_PKTQ_IN_HWQ,\n\tAPP_PKTQ_IN_SWQ,\n\tAPP_PKTQ_IN_TM,\n\tAPP_PKTQ_IN_SOURCE,\n};\n\nstruct app_pktq_in_params {\n\tenum app_pktq_in_type type;\n\tuint32_t id; /* Position in the appropriate app array */\n};\n\nenum app_pktq_out_type {\n\tAPP_PKTQ_OUT_HWQ,\n\tAPP_PKTQ_OUT_SWQ,\n\tAPP_PKTQ_OUT_TM,\n\tAPP_PKTQ_OUT_SINK,\n};\n\nstruct app_pktq_out_params {\n\tenum app_pktq_out_type type;\n\tuint32_t id; /* Position in the appropriate app array */\n};\n\n#ifndef APP_PIPELINE_TYPE_SIZE\n#define APP_PIPELINE_TYPE_SIZE 64\n#endif\n\n#define APP_MAX_PIPELINE_PKTQ_IN PIPELINE_MAX_PORT_IN\n#define APP_MAX_PIPELINE_PKTQ_OUT PIPELINE_MAX_PORT_OUT\n#define APP_MAX_PIPELINE_MSGQ_IN PIPELINE_MAX_MSGQ_IN\n#define APP_MAX_PIPELINE_MSGQ_OUT PIPELINE_MAX_MSGQ_OUT\n\n#define APP_MAX_PIPELINE_ARGS PIPELINE_MAX_ARGS\n\nstruct app_pipeline_params {\n\tchar *name;\n\tuint8_t parsed;\n\n\tchar type[APP_PIPELINE_TYPE_SIZE];\n\n\tuint32_t socket_id;\n\tuint32_t core_id;\n\tuint32_t hyper_th_id;\n\n\tstruct app_pktq_in_params pktq_in[APP_MAX_PIPELINE_PKTQ_IN];\n\tstruct app_pktq_out_params pktq_out[APP_MAX_PIPELINE_PKTQ_OUT];\n\tuint32_t msgq_in[APP_MAX_PIPELINE_MSGQ_IN];\n\tuint32_t msgq_out[APP_MAX_PIPELINE_MSGQ_OUT];\n\n\tuint32_t n_pktq_in;\n\tuint32_t n_pktq_out;\n\tuint32_t n_msgq_in;\n\tuint32_t n_msgq_out;\n\n\tuint32_t timer_period;\n\n\tchar *args_name[APP_MAX_PIPELINE_ARGS];\n\tchar *args_value[APP_MAX_PIPELINE_ARGS];\n\tuint32_t n_args;\n};\n\nstruct app_pipeline_data {\n\tvoid *be;\n\tvoid *fe;\n\tuint64_t timer_period;\n};\n\nstruct app_thread_pipeline_data {\n\tvoid *be;\n\tpipeline_be_op_run f_run;\n\tpipeline_be_op_timer f_timer;\n\tuint64_t timer_period;\n\tuint64_t deadline;\n};\n\n#ifndef APP_MAX_THREAD_PIPELINES\n#define APP_MAX_THREAD_PIPELINES 16\n#endif\n\nstruct app_thread_data {\n\tstruct app_thread_pipeline_data regular[APP_MAX_THREAD_PIPELINES];\n\tstruct app_thread_pipeline_data custom[APP_MAX_THREAD_PIPELINES];\n\n\tuint32_t n_regular;\n\tuint32_t n_custom;\n\n\tuint64_t deadline;\n};\n\nstruct app_eal_params {\n\t/* Map lcore set to physical cpu set */\n\tchar *coremap;\n\n\t/* Core ID that is used as master */\n\tuint32_t master_lcore_present;\n\tuint32_t master_lcore;\n\n\t/* Number of memory channels */\n\tuint32_t channels_present;\n\tuint32_t channels;\n\n\t/* Memory to allocate (see also --socket-mem) */\n\tuint32_t memory_present;\n\tuint32_t memory;\n\n\t/* Force number of memory ranks (don't detect) */\n\tuint32_t ranks_present;\n\tuint32_t ranks;\n\n\t/* Add a PCI device in black list. */\n\tchar *pci_blacklist;\n\n\t/* Add a PCI device in white list. */\n\tchar *pci_whitelist;\n\n\t/* Add a virtual device. */\n\tchar *vdev;\n\n\t /* Use VMware TSC map instead of native RDTSC */\n\tuint32_t vmware_tsc_map_present;\n\tint vmware_tsc_map;\n\n\t /* Type of this process (primary|secondary|auto) */\n\tchar *proc_type;\n\n\t /* Set syslog facility */\n\tchar *syslog;\n\n\t/* Set default log level */\n\tuint32_t log_level_present;\n\tuint32_t log_level;\n\n\t/* Display version information on startup */\n\tuint32_t version_present;\n\tint version;\n\n\t/* This help */\n\tuint32_t help_present;\n\tint help;\n\n\t /* Use malloc instead of hugetlbfs */\n\tuint32_t no_huge_present;\n\tint no_huge;\n\n\t/* Disable PCI */\n\tuint32_t no_pci_present;\n\tint no_pci;\n\n\t/* Disable HPET */\n\tuint32_t no_hpet_present;\n\tint no_hpet;\n\n\t/* No shared config (mmap'd files) */\n\tuint32_t no_shconf_present;\n\tint no_shconf;\n\n\t/* Add driver */\n\tchar *add_driver;\n\n\t/* Memory to allocate on sockets (comma separated values)*/\n\tchar *socket_mem;\n\n\t/* Directory where hugetlbfs is mounted */\n\tchar *huge_dir;\n\n\t/* Prefix for hugepage filenames */\n\tchar *file_prefix;\n\n\t/* Base virtual address */\n\tchar *base_virtaddr;\n\n\t/* Create /dev/uioX (usually done by hotplug) */\n\tuint32_t create_uio_dev_present;\n\tint create_uio_dev;\n\n\t/* Interrupt mode for VFIO (legacy|msi|msix) */\n\tchar *vfio_intr;\n\n\t/* Support running on Xen dom0 without hugetlbfs */\n\tuint32_t xen_dom0_present;\n\tint xen_dom0;\n};\n\n#ifndef APP_APPNAME_SIZE\n#define APP_APPNAME_SIZE 256\n#endif\n\n#ifndef APP_MAX_MEMPOOLS\n#define APP_MAX_MEMPOOLS 8\n#endif\n\n#ifndef APP_MAX_LINKS\n#define APP_MAX_LINKS 16\n#endif\n\n#ifndef APP_LINK_MAX_HWQ_IN\n#define APP_LINK_MAX_HWQ_IN 64\n#endif\n\n#ifndef APP_LINK_MAX_HWQ_OUT\n#define APP_LINK_MAX_HWQ_OUT 64\n#endif\n\n#define APP_MAX_HWQ_IN (APP_MAX_LINKS * APP_LINK_MAX_HWQ_IN)\n\n#define APP_MAX_HWQ_OUT (APP_MAX_LINKS * APP_LINK_MAX_HWQ_OUT)\n\n#ifndef APP_MAX_PKTQ_SWQ\n#define APP_MAX_PKTQ_SWQ 256\n#endif\n\n#define APP_MAX_PKTQ_TM APP_MAX_LINKS\n\n#ifndef APP_MAX_PKTQ_SOURCE\n#define APP_MAX_PKTQ_SOURCE 16\n#endif\n\n#ifndef APP_MAX_PKTQ_SINK\n#define APP_MAX_PKTQ_SINK 16\n#endif\n\n#ifndef APP_MAX_MSGQ\n#define APP_MAX_MSGQ 64\n#endif\n\n#ifndef APP_MAX_PIPELINES\n#define APP_MAX_PIPELINES 64\n#endif\n\n#ifndef APP_EAL_ARGC\n#define APP_EAL_ARGC 32\n#endif\n\n#ifndef APP_MAX_PIPELINE_TYPES\n#define APP_MAX_PIPELINE_TYPES 64\n#endif\n\n#ifndef APP_MAX_THREADS\n#define APP_MAX_THREADS RTE_MAX_LCORE\n#endif\n\n#ifndef APP_MAX_CMDS\n#define APP_MAX_CMDS 64\n#endif\n\nstruct app_params {\n\t/* Config */\n\tchar app_name[APP_APPNAME_SIZE];\n\tconst char *config_file;\n\tconst char *script_file;\n\tuint64_t port_mask;\n\tuint32_t log_level;\n\n\tstruct app_eal_params eal_params;\n\tstruct app_mempool_params mempool_params[APP_MAX_MEMPOOLS];\n\tstruct app_link_params link_params[APP_MAX_LINKS];\n\tstruct app_pktq_hwq_in_params hwq_in_params[APP_MAX_HWQ_IN];\n\tstruct app_pktq_hwq_out_params hwq_out_params[APP_MAX_HWQ_OUT];\n\tstruct app_pktq_swq_params swq_params[APP_MAX_PKTQ_SWQ];\n\tstruct app_pktq_tm_params tm_params[APP_MAX_PKTQ_TM];\n\tstruct app_pktq_source_params source_params[APP_MAX_PKTQ_SOURCE];\n\tstruct app_pktq_sink_params sink_params[APP_MAX_PKTQ_SINK];\n\tstruct app_msgq_params msgq_params[APP_MAX_MSGQ];\n\tstruct app_pipeline_params pipeline_params[APP_MAX_PIPELINES];\n\n\tuint32_t n_mempools;\n\tuint32_t n_links;\n\tuint32_t n_pktq_hwq_in;\n\tuint32_t n_pktq_hwq_out;\n\tuint32_t n_pktq_swq;\n\tuint32_t n_pktq_tm;\n\tuint32_t n_pktq_source;\n\tuint32_t n_pktq_sink;\n\tuint32_t n_msgq;\n\tuint32_t n_pipelines;\n\n\t/* Init */\n\tchar *eal_argv[1 + APP_EAL_ARGC];\n\tstruct cpu_core_map *core_map;\n\tuint64_t core_mask;\n\tstruct rte_mempool *mempool[APP_MAX_MEMPOOLS];\n\tstruct rte_ring *swq[APP_MAX_PKTQ_SWQ];\n\tstruct rte_sched_port *tm[APP_MAX_PKTQ_TM];\n\tstruct rte_ring *msgq[APP_MAX_MSGQ];\n\tstruct pipeline_type pipeline_type[APP_MAX_PIPELINE_TYPES];\n\tstruct app_pipeline_data pipeline_data[APP_MAX_PIPELINES];\n\tstruct app_thread_data thread_data[APP_MAX_THREADS];\n\tcmdline_parse_ctx_t cmds[APP_MAX_CMDS + 1];\n\n\tint eal_argc;\n\tuint32_t n_pipeline_types;\n\tuint32_t n_cmds;\n};\n\n#define APP_PARAM_VALID(obj) ((obj)->name != NULL)\n\n#define APP_PARAM_COUNT(obj_array, n_objs)\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tsize_t i;\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tn_objs = 0;\t\t\t\t\t\t\t\\\n\tfor (i = 0; i < RTE_DIM(obj_array); i++)\t\t\t\\\n\t\tif (APP_PARAM_VALID(&((obj_array)[i])))\t\t\t\\\n\t\t\tn_objs++;\t\t\t\t\t\\\n}\n\n#define APP_PARAM_FIND(obj_array, key)\t\t\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\\\n\tssize_t obj_idx;\t\t\t\t\t\t\\\n\tconst ssize_t obj_count = RTE_DIM(obj_array);\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tfor (obj_idx = 0; obj_idx < obj_count; obj_idx++) {\t\t\\\n\t\tif (!APP_PARAM_VALID(&((obj_array)[obj_idx])))\t\t\\\n\t\t\tcontinue;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t\tif (strcmp(key, (obj_array)[obj_idx].name) == 0)\t\\\n\t\t\tbreak;\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n\tobj_idx < obj_count ? obj_idx : -ENOENT;\t\t\t\\\n})\n\n#define APP_PARAM_FIND_BY_ID(obj_array, prefix, id, obj)\t\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\tchar name[APP_PARAM_NAME_SIZE];\t\t\t\t\t\\\n\tssize_t pos;\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tsprintf(name, prefix \"%\" PRIu32, id);\t\t\t\t\\\n\tpos = APP_PARAM_FIND(obj_array, name);\t\t\t\t\\\n\tobj = (pos < 0) ? NULL : &((obj_array)[pos]);\t\t\t\\\n} while (0)\n\n#define APP_PARAM_GET_ID(obj, prefix, id)\t\t\t\t\\\ndo\t\t\t\t\t\t\t\t\t\\\n\tsscanf(obj->name, prefix \"%\" SCNu32, &id);\t\t\t\t\\\nwhile (0)\t\t\t\t\t\t\t\t\\\n\n#define APP_PARAM_ADD(obj_array, obj_name)\t\t\t\t\\\n({\t\t\t\t\t\t\t\t\t\\\n\tssize_t obj_idx;\t\t\t\t\t\t\\\n\tconst ssize_t obj_count = RTE_DIM(obj_array);\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tobj_idx = APP_PARAM_FIND(obj_array, obj_name);\t\t\t\\\n\tif (obj_idx < 0) {\t\t\t\t\t\t\\\n\t\tfor (obj_idx = 0; obj_idx < obj_count; obj_idx++) {\t\\\n\t\t\tif (!APP_PARAM_VALID(&((obj_array)[obj_idx])))\t\\\n\t\t\t\tbreak;\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t\tif (obj_idx < obj_count) {\t\t\t\t\\\n\t\t\t(obj_array)[obj_idx].name = strdup(obj_name); \\\n\t\t\tif ((obj_array)[obj_idx].name == NULL) \\\n\t\t\t\tobj_idx = -EINVAL;\t\t\t\\\n\t\t} else\t\t\t\t\t\t\t\\\n\t\t\tobj_idx = -ENOMEM;\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n\tobj_idx;\t\t\t\t\t\t\t\\\n})\n\n#define\tAPP_CHECK(exp, fmt, ...)\t\t\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\tif (!(exp)) {\t\t\t\t\t\t\t\\\n\t\tfprintf(stderr, fmt \"\\n\", ## __VA_ARGS__);\t\t\\\n\t\tabort();\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n} while (0)\n\nenum app_log_level {\n\tAPP_LOG_LEVEL_HIGH = 1,\n\tAPP_LOG_LEVEL_LOW,\n\tAPP_LOG_LEVELS\n};\n\n#define APP_LOG(app, level, fmt, ...)\t\t\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\tif (app->log_level >= APP_LOG_LEVEL_ ## level)\t\t\t\\\n\t\tfprintf(stdout, \"[APP] \" fmt \"\\n\", ## __VA_ARGS__);\t\\\n} while (0)\n\nstatic inline uint32_t\napp_link_get_n_rxq(struct app_params *app, struct app_link_params *link)\n{\n\tuint32_t n_rxq = 0, link_id, i;\n\tuint32_t n_pktq_hwq_in = RTE_MIN(app->n_pktq_hwq_in,\n\t\tRTE_DIM(app->hwq_in_params));\n\n\tAPP_PARAM_GET_ID(link, \"LINK\", link_id);\n\n\tfor (i = 0; i < n_pktq_hwq_in; i++) {\n\t\tstruct app_pktq_hwq_in_params *p = &app->hwq_in_params[i];\n\t\tuint32_t rxq_link_id, rxq_queue_id;\n\n\t\tsscanf(p->name, \"RXQ%\" SCNu32 \".%\" SCNu32,\n\t\t\t&rxq_link_id, &rxq_queue_id);\n\t\tif (rxq_link_id == link_id)\n\t\t\tn_rxq++;\n\t}\n\n\treturn n_rxq;\n}\n\nstatic inline uint32_t\napp_link_get_n_txq(struct app_params *app, struct app_link_params *link)\n{\n\tuint32_t n_txq = 0, link_id, i;\n\tuint32_t n_pktq_hwq_out = RTE_MIN(app->n_pktq_hwq_out,\n\t\tRTE_DIM(app->hwq_out_params));\n\n\tAPP_PARAM_GET_ID(link, \"LINK\", link_id);\n\n\tfor (i = 0; i < n_pktq_hwq_out; i++) {\n\t\tstruct app_pktq_hwq_out_params *p = &app->hwq_out_params[i];\n\t\tuint32_t txq_link_id, txq_queue_id;\n\n\t\tsscanf(p->name, \"TXQ%\" SCNu32 \".%\" SCNu32,\n\t\t\t&txq_link_id, &txq_queue_id);\n\t\tif (txq_link_id == link_id)\n\t\t\tn_txq++;\n\t}\n\n\treturn n_txq;\n}\n\nstatic inline uint32_t\napp_rxq_get_readers(struct app_params *app, struct app_pktq_hwq_in_params *rxq)\n{\n\tuint32_t pos = rxq - app->hwq_in_params;\n\tuint32_t n_pipelines = RTE_MIN(app->n_pipelines,\n\t\tRTE_DIM(app->pipeline_params));\n\tuint32_t n_readers = 0, i;\n\n\tfor (i = 0; i < n_pipelines; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\t\tuint32_t n_pktq_in = RTE_MIN(p->n_pktq_in, RTE_DIM(p->pktq_in));\n\t\tuint32_t j;\n\n\t\tfor (j = 0; j < n_pktq_in; j++) {\n\t\t\tstruct app_pktq_in_params *pktq = &p->pktq_in[j];\n\n\t\t\tif ((pktq->type == APP_PKTQ_IN_HWQ) &&\n\t\t\t\t(pktq->id == pos))\n\t\t\t\tn_readers++;\n\t\t}\n\t}\n\n\treturn n_readers;\n}\n\nstatic inline uint32_t\napp_swq_get_readers(struct app_params *app, struct app_pktq_swq_params *swq)\n{\n\tuint32_t pos = swq - app->swq_params;\n\tuint32_t n_pipelines = RTE_MIN(app->n_pipelines,\n\t\tRTE_DIM(app->pipeline_params));\n\tuint32_t n_readers = 0, i;\n\n\tfor (i = 0; i < n_pipelines; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\t\tuint32_t n_pktq_in = RTE_MIN(p->n_pktq_in, RTE_DIM(p->pktq_in));\n\t\tuint32_t j;\n\n\t\tfor (j = 0; j < n_pktq_in; j++) {\n\t\t\tstruct app_pktq_in_params *pktq = &p->pktq_in[j];\n\n\t\t\tif ((pktq->type == APP_PKTQ_IN_SWQ) &&\n\t\t\t\t(pktq->id == pos))\n\t\t\t\tn_readers++;\n\t\t}\n\t}\n\n\treturn n_readers;\n}\n\nstatic inline uint32_t\napp_tm_get_readers(struct app_params *app, struct app_pktq_tm_params *tm)\n{\n\tuint32_t pos = tm - app->tm_params;\n\tuint32_t n_pipelines = RTE_MIN(app->n_pipelines,\n\t\tRTE_DIM(app->pipeline_params));\n\tuint32_t n_readers = 0, i;\n\n\tfor (i = 0; i < n_pipelines; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\t\tuint32_t n_pktq_in = RTE_MIN(p->n_pktq_in, RTE_DIM(p->pktq_in));\n\t\tuint32_t j;\n\n\t\tfor (j = 0; j < n_pktq_in; j++) {\n\t\t\tstruct app_pktq_in_params *pktq = &p->pktq_in[j];\n\n\t\t\tif ((pktq->type == APP_PKTQ_IN_TM) &&\n\t\t\t\t(pktq->id == pos))\n\t\t\t\tn_readers++;\n\t\t}\n\t}\n\n\treturn n_readers;\n}\n\nstatic inline uint32_t\napp_source_get_readers(struct app_params *app,\nstruct app_pktq_source_params *source)\n{\n\tuint32_t pos = source - app->source_params;\n\tuint32_t n_pipelines = RTE_MIN(app->n_pipelines,\n\t\tRTE_DIM(app->pipeline_params));\n\tuint32_t n_readers = 0, i;\n\n\tfor (i = 0; i < n_pipelines; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\t\tuint32_t n_pktq_in = RTE_MIN(p->n_pktq_in, RTE_DIM(p->pktq_in));\n\t\tuint32_t j;\n\n\t\tfor (j = 0; j < n_pktq_in; j++) {\n\t\t\tstruct app_pktq_in_params *pktq = &p->pktq_in[j];\n\n\t\t\tif ((pktq->type == APP_PKTQ_IN_SOURCE) &&\n\t\t\t\t(pktq->id == pos))\n\t\t\t\tn_readers++;\n\t\t}\n\t}\n\n\treturn n_readers;\n}\n\nstatic inline uint32_t\napp_msgq_get_readers(struct app_params *app, struct app_msgq_params *msgq)\n{\n\tuint32_t pos = msgq - app->msgq_params;\n\tuint32_t n_pipelines = RTE_MIN(app->n_pipelines,\n\t\tRTE_DIM(app->pipeline_params));\n\tuint32_t n_readers = 0, i;\n\n\tfor (i = 0; i < n_pipelines; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\t\tuint32_t n_msgq_in = RTE_MIN(p->n_msgq_in, RTE_DIM(p->msgq_in));\n\t\tuint32_t j;\n\n\t\tfor (j = 0; j < n_msgq_in; j++)\n\t\t\tif (p->msgq_in[j] == pos)\n\t\t\t\tn_readers++;\n\t}\n\n\treturn n_readers;\n}\n\nstatic inline uint32_t\napp_txq_get_writers(struct app_params *app, struct app_pktq_hwq_out_params *txq)\n{\n\tuint32_t pos = txq - app->hwq_out_params;\n\tuint32_t n_pipelines = RTE_MIN(app->n_pipelines,\n\t\tRTE_DIM(app->pipeline_params));\n\tuint32_t n_writers = 0, i;\n\n\tfor (i = 0; i < n_pipelines; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\t\tuint32_t n_pktq_out = RTE_MIN(p->n_pktq_out,\n\t\t\tRTE_DIM(p->pktq_out));\n\t\tuint32_t j;\n\n\t\tfor (j = 0; j < n_pktq_out; j++) {\n\t\t\tstruct app_pktq_out_params *pktq = &p->pktq_out[j];\n\n\t\t\tif ((pktq->type == APP_PKTQ_OUT_HWQ) &&\n\t\t\t\t(pktq->id == pos))\n\t\t\t\tn_writers++;\n\t\t}\n\t}\n\n\treturn n_writers;\n}\n\nstatic inline uint32_t\napp_swq_get_writers(struct app_params *app, struct app_pktq_swq_params *swq)\n{\n\tuint32_t pos = swq - app->swq_params;\n\tuint32_t n_pipelines = RTE_MIN(app->n_pipelines,\n\t\tRTE_DIM(app->pipeline_params));\n\tuint32_t n_writers = 0, i;\n\n\tfor (i = 0; i < n_pipelines; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\t\tuint32_t n_pktq_out = RTE_MIN(p->n_pktq_out,\n\t\t\tRTE_DIM(p->pktq_out));\n\t\tuint32_t j;\n\n\t\tfor (j = 0; j < n_pktq_out; j++) {\n\t\t\tstruct app_pktq_out_params *pktq = &p->pktq_out[j];\n\n\t\t\tif ((pktq->type == APP_PKTQ_OUT_SWQ) &&\n\t\t\t\t(pktq->id == pos))\n\t\t\t\tn_writers++;\n\t\t}\n\t}\n\n\treturn n_writers;\n}\n\nstatic inline uint32_t\napp_tm_get_writers(struct app_params *app, struct app_pktq_tm_params *tm)\n{\n\tuint32_t pos = tm - app->tm_params;\n\tuint32_t n_pipelines = RTE_MIN(app->n_pipelines,\n\t\tRTE_DIM(app->pipeline_params));\n\tuint32_t n_writers = 0, i;\n\n\tfor (i = 0; i < n_pipelines; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\t\tuint32_t n_pktq_out = RTE_MIN(p->n_pktq_out,\n\t\t\tRTE_DIM(p->pktq_out));\n\t\tuint32_t j;\n\n\t\tfor (j = 0; j < n_pktq_out; j++) {\n\t\t\tstruct app_pktq_out_params *pktq = &p->pktq_out[j];\n\n\t\t\tif ((pktq->type == APP_PKTQ_OUT_TM) &&\n\t\t\t\t(pktq->id == pos))\n\t\t\t\tn_writers++;\n\t\t}\n\t}\n\n\treturn n_writers;\n}\n\nstatic inline uint32_t\napp_sink_get_writers(struct app_params *app, struct app_pktq_sink_params *sink)\n{\n\tuint32_t pos = sink - app->sink_params;\n\tuint32_t n_pipelines = RTE_MIN(app->n_pipelines,\n\t\tRTE_DIM(app->pipeline_params));\n\tuint32_t n_writers = 0, i;\n\n\tfor (i = 0; i < n_pipelines; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\t\tuint32_t n_pktq_out = RTE_MIN(p->n_pktq_out,\n\t\t\tRTE_DIM(p->pktq_out));\n\t\tuint32_t j;\n\n\t\tfor (j = 0; j < n_pktq_out; j++) {\n\t\t\tstruct app_pktq_out_params *pktq = &p->pktq_out[j];\n\n\t\t\tif ((pktq->type == APP_PKTQ_OUT_SINK) &&\n\t\t\t\t(pktq->id == pos))\n\t\t\t\tn_writers++;\n\t\t}\n\t}\n\n\treturn n_writers;\n}\n\nstatic inline uint32_t\napp_msgq_get_writers(struct app_params *app, struct app_msgq_params *msgq)\n{\n\tuint32_t pos = msgq - app->msgq_params;\n\tuint32_t n_pipelines = RTE_MIN(app->n_pipelines,\n\t\tRTE_DIM(app->pipeline_params));\n\tuint32_t n_writers = 0, i;\n\n\tfor (i = 0; i < n_pipelines; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\t\tuint32_t n_msgq_out = RTE_MIN(p->n_msgq_out,\n\t\t\tRTE_DIM(p->msgq_out));\n\t\tuint32_t j;\n\n\t\tfor (j = 0; j < n_msgq_out; j++)\n\t\t\tif (p->msgq_out[j] == pos)\n\t\t\t\tn_writers++;\n\t}\n\n\treturn n_writers;\n}\n\nstatic inline struct app_link_params *\napp_get_link_for_rxq(struct app_params *app, struct app_pktq_hwq_in_params *p)\n{\n\tchar link_name[APP_PARAM_NAME_SIZE];\n\tssize_t link_param_idx;\n\tuint32_t rxq_link_id, rxq_queue_id;\n\n\tsscanf(p->name, \"RXQ%\" SCNu32 \".%\" SCNu32,\n\t\t&rxq_link_id, &rxq_queue_id);\n\tsprintf(link_name, \"LINK%\" PRIu32, rxq_link_id);\n\tlink_param_idx = APP_PARAM_FIND(app->link_params, link_name);\n\tAPP_CHECK((link_param_idx >= 0),\n\t\t\"Cannot find %s for %s\", link_name, p->name);\n\n\treturn &app->link_params[link_param_idx];\n}\n\nstatic inline struct app_link_params *\napp_get_link_for_txq(struct app_params *app, struct app_pktq_hwq_out_params *p)\n{\n\tchar link_name[APP_PARAM_NAME_SIZE];\n\tssize_t link_param_idx;\n\tuint32_t txq_link_id, txq_queue_id;\n\n\tsscanf(p->name, \"TXQ%\" SCNu32 \".%\" SCNu32,\n\t\t&txq_link_id, &txq_queue_id);\n\tsprintf(link_name, \"LINK%\" PRIu32, txq_link_id);\n\tlink_param_idx = APP_PARAM_FIND(app->link_params, link_name);\n\tAPP_CHECK((link_param_idx >= 0),\n\t\t\"Cannot find %s for %s\", link_name, p->name);\n\n\treturn &app->link_params[link_param_idx];\n}\n\nstatic inline struct app_link_params *\napp_get_link_for_tm(struct app_params *app, struct app_pktq_tm_params *p_tm)\n{\n\tchar link_name[APP_PARAM_NAME_SIZE];\n\tuint32_t link_id;\n\tssize_t link_param_idx;\n\n\tsscanf(p_tm->name, \"TM%\" PRIu32, &link_id);\n\tsprintf(link_name, \"LINK%\" PRIu32, link_id);\n\tlink_param_idx = APP_PARAM_FIND(app->link_params, link_name);\n\tAPP_CHECK((link_param_idx >= 0),\n\t\t\"Cannot find %s for %s\", link_name, p_tm->name);\n\n\treturn &app->link_params[link_param_idx];\n}\n\nint app_config_init(struct app_params *app);\n\nint app_config_args(struct app_params *app,\n\tint argc, char **argv);\n\nint app_config_parse(struct app_params *app,\n\tconst char *file_name);\n\nint app_config_parse_tm(struct app_params *app);\n\nvoid app_config_save(struct app_params *app,\n\tconst char *file_name);\n\nint app_config_check(struct app_params *app);\n\nint app_init(struct app_params *app);\n\nint app_thread(void *arg);\n\nint app_pipeline_type_register(struct app_params *app,\n\tstruct pipeline_type *ptype);\n\nstruct pipeline_type *app_pipeline_type_find(struct app_params *app,\n\tchar *name);\n\nvoid app_link_up_internal(struct app_params *app,\n\tstruct app_link_params *cp);\n\nvoid app_link_down_internal(struct app_params *app,\n\tstruct app_link_params *cp);\n\n#endif\n" }, { "path": "examples/ip_pipeline/config/ip_pipeline.cfg", "content": "[PIPELINE0]\ntype = MASTER\ncore = 0\n\n[PIPELINE1]\ntype = PASS-THROUGH\ncore = 1\npktq_in = RXQ0.0 RXQ1.0 RXQ2.0 RXQ3.0\npktq_out = TXQ0.0 TXQ1.0 TXQ2.0 TXQ3.0\n" }, { "path": "examples/ip_pipeline/config/ip_pipeline.sh", "content": "#\n#run config/ip_pipeline.sh\n#\n\np 1 ping\n" }, { "path": "examples/ip_pipeline/config/tm_profile.cfg", "content": "; BSD LICENSE\n;\n; Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions\n; are met:\n;\n; * Redistributions of source code must retain the above copyright\n; notice, this list of conditions and the following disclaimer.\n; * Redistributions in binary form must reproduce the above copyright\n; notice, this list of conditions and the following disclaimer in\n; the documentation and/or other materials provided with the\n; distribution.\n; * Neither the name of Intel Corporation nor the names of its\n; contributors may be used to endorse or promote products derived\n; from this software without specific prior written permission.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n; \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n; This file enables the following hierarchical scheduler configuration for each\n; 10GbE output port:\n;\t* Single subport (subport 0):\n;\t\t- Subport rate set to 100% of port rate\n;\t\t- Each of the 4 traffic classes has rate set to 100% of port rate\n;\t* 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:\n;\t\t- Pipe rate set to 1/4K of port rate\n;\t\t- Each of the 4 traffic classes has rate set to 100% of pipe rate\n;\t\t- Within each traffic class, the byte-level WRR weights for the 4 queues\n; are set to 1:1:1:1\n;\n; For more details, please refer to chapter \"Quality of Service (QoS) Framework\"\n; of Intel Data Plane Development Kit (Intel DPDK) Programmer's Guide.\n\n; Port configuration\n[port]\nframe overhead = 24 ; frame overhead = Preamble (7) + SFD (1) + FCS (4) + IFG (12)\nmtu = 1522; mtu = Q-in-Q MTU (FCS not included)\nnumber of subports per port = 1\nnumber of pipes per subport = 4096\nqueue sizes = 64 64 64 64\n\n; Subport configuration\n[subport 0]\ntb rate = 1250000000 ; Bytes per second\ntb size = 1000000 ; Bytes\n\ntc 0 rate = 1250000000 ; Bytes per second\ntc 1 rate = 1250000000 ; Bytes per second\ntc 2 rate = 1250000000 ; Bytes per second\ntc 3 rate = 1250000000 ; Bytes per second\ntc period = 10 ; Milliseconds\n\npipe 0-4095 = 0 ; These pipes are configured with pipe profile 0\n\n; Pipe configuration\n[pipe profile 0]\ntb rate = 305175 ; Bytes per second\ntb size = 1000000 ; Bytes\n\ntc 0 rate = 305175 ; Bytes per second\ntc 1 rate = 305175 ; Bytes per second\ntc 2 rate = 305175 ; Bytes per second\ntc 3 rate = 305175 ; Bytes per second\ntc period = 40 ; Milliseconds\n\ntc 3 oversubscription weight = 1\n\ntc 0 wrr weights = 1 1 1 1\ntc 1 wrr weights = 1 1 1 1\ntc 2 wrr weights = 1 1 1 1\ntc 3 wrr weights = 1 1 1 1\n\n; RED params per traffic class and color (Green / Yellow / Red)\n[red]\ntc 0 wred min = 48 40 32\ntc 0 wred max = 64 64 64\ntc 0 wred inv prob = 10 10 10\ntc 0 wred weight = 9 9 9\n\ntc 1 wred min = 48 40 32\ntc 1 wred max = 64 64 64\ntc 1 wred inv prob = 10 10 10\ntc 1 wred weight = 9 9 9\n\ntc 2 wred min = 48 40 32\ntc 2 wred max = 64 64 64\ntc 2 wred inv prob = 10 10 10\ntc 2 wred weight = 9 9 9\n\ntc 3 wred min = 48 40 32\ntc 3 wred max = 64 64 64\ntc 3 wred inv prob = 10 10 10\ntc 3 wred weight = 9 9 9\n" }, { "path": "examples/ip_pipeline/config_check.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \"app.h\"\n\nstatic void\ncheck_mempools(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_mempools; i++) {\n\t\tstruct app_mempool_params *p = &app->mempool_params[i];\n\n\t\tAPP_CHECK((p->pool_size > 0),\n\t\t\t\"Mempool %s size is 0\\n\", p->name);\n\n\t\tAPP_CHECK((p->cache_size > 0),\n\t\t\t\"Mempool %s cache size is 0\\n\", p->name);\n\n\t\tAPP_CHECK(rte_is_power_of_2(p->cache_size),\n\t\t\t\"Mempool %s cache size not a power of 2\\n\", p->name);\n\t}\n}\n\nstatic void\ncheck_links(struct app_params *app)\n{\n\tuint32_t n_links_port_mask = __builtin_popcountll(app->port_mask);\n\tuint32_t i;\n\n\t/* Check that number of links matches the port mask */\n\tAPP_CHECK((app->n_links == n_links_port_mask),\n\t\t\"Not enough links provided in the PORT_MASK\\n\");\n\n\tfor (i = 0; i < app->n_links; i++) {\n\t\tstruct app_link_params *link = &app->link_params[i];\n\t\tuint32_t rxq_max, n_rxq, n_txq, link_id, i;\n\n\t\tAPP_PARAM_GET_ID(link, \"LINK\", link_id);\n\n\t\t/* Check that link RXQs are contiguous */\n\t\trxq_max = 0;\n\t\tif (link->arp_q > rxq_max)\n\t\t\trxq_max = link->arp_q;\n\t\tif (link->tcp_syn_local_q > rxq_max)\n\t\t\trxq_max = link->tcp_syn_local_q;\n\t\tif (link->ip_local_q > rxq_max)\n\t\t\trxq_max = link->ip_local_q;\n\t\tif (link->tcp_local_q > rxq_max)\n\t\t\trxq_max = link->tcp_local_q;\n\t\tif (link->udp_local_q > rxq_max)\n\t\t\trxq_max = link->udp_local_q;\n\t\tif (link->sctp_local_q > rxq_max)\n\t\t\trxq_max = link->sctp_local_q;\n\n\t\tfor (i = 1; i <= rxq_max; i++)\n\t\t\tAPP_CHECK(((link->arp_q == i) ||\n\t\t\t\t(link->tcp_syn_local_q == i) ||\n\t\t\t\t(link->ip_local_q == i) ||\n\t\t\t\t(link->tcp_local_q == i) ||\n\t\t\t\t(link->udp_local_q == i) ||\n\t\t\t\t(link->sctp_local_q == i)),\n\t\t\t\t\"%s RXQs are not contiguous (A)\\n\", link->name);\n\n\t\tn_rxq = app_link_get_n_rxq(app, link);\n\n\t\tAPP_CHECK((n_rxq == rxq_max + 1),\n\t\t\t\"%s RXQs are not contiguous (B)\\n\", link->name);\n\n\t\tfor (i = 0; i < n_rxq; i++) {\n\t\t\tchar name[APP_PARAM_NAME_SIZE];\n\t\t\tint pos;\n\n\t\t\tsprintf(name, \"RXQ%\" PRIu32 \".%\" PRIu32,\n\t\t\t\tlink_id, i);\n\t\t\tpos = APP_PARAM_FIND(app->hwq_in_params, name);\n\t\t\tAPP_CHECK((pos >= 0),\n\t\t\t\t\"%s RXQs are not contiguous (C)\\n\", link->name);\n\t\t}\n\n\t\t/* Check that link RXQs are contiguous */\n\t\tn_txq = app_link_get_n_txq(app, link);\n\n\t\tfor (i = 0; i < n_txq; i++) {\n\t\t\tchar name[APP_PARAM_NAME_SIZE];\n\t\t\tint pos;\n\n\t\t\tsprintf(name, \"TXQ%\" PRIu32 \".%\" PRIu32,\n\t\t\t\tlink_id, i);\n\t\t\tpos = APP_PARAM_FIND(app->hwq_out_params, name);\n\t\t\tAPP_CHECK((pos >= 0),\n\t\t\t\t\"%s TXQs are not contiguous\\n\", link->name);\n\t\t}\n\t}\n}\n\nstatic void\ncheck_rxqs(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_pktq_hwq_in; i++) {\n\t\tstruct app_pktq_hwq_in_params *p = &app->hwq_in_params[i];\n\t\tuint32_t n_readers = app_rxq_get_readers(app, p);\n\n\t\tAPP_CHECK((p->size > 0),\n\t\t\t\"%s size is 0\\n\", p->name);\n\n\t\tAPP_CHECK((rte_is_power_of_2(p->size)),\n\t\t\t\"%s size is not a power of 2\\n\", p->name);\n\n\t\tAPP_CHECK((p->burst > 0),\n\t\t\t\"%s burst size is 0\\n\", p->name);\n\n\t\tAPP_CHECK((p->burst <= p->size),\n\t\t\t\"%s burst size is bigger than its size\\n\", p->name);\n\n\t\tAPP_CHECK((n_readers != 0),\n\t\t\t\"%s has no reader\\n\", p->name);\n\n\t\tAPP_CHECK((n_readers == 1),\n\t\t\t\"%s has more than one reader\\n\", p->name);\n\t}\n}\n\nstatic void\ncheck_txqs(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_pktq_hwq_out; i++) {\n\t\tstruct app_pktq_hwq_out_params *p = &app->hwq_out_params[i];\n\t\tuint32_t n_writers = app_txq_get_writers(app, p);\n\n\t\tAPP_CHECK((p->size > 0),\n\t\t\t\"%s size is 0\\n\", p->name);\n\n\t\tAPP_CHECK((rte_is_power_of_2(p->size)),\n\t\t\t\"%s size is not a power of 2\\n\", p->name);\n\n\t\tAPP_CHECK((p->burst > 0),\n\t\t\t\"%s burst size is 0\\n\", p->name);\n\n\t\tAPP_CHECK((p->burst <= p->size),\n\t\t\t\"%s burst size is bigger than its size\\n\", p->name);\n\n\t\tAPP_CHECK((n_writers != 0),\n\t\t\t\"%s has no writer\\n\", p->name);\n\n\t\tAPP_CHECK((n_writers == 1),\n\t\t\t\"%s has more than one writer\\n\", p->name);\n\t}\n}\n\nstatic void\ncheck_swqs(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_pktq_swq; i++) {\n\t\tstruct app_pktq_swq_params *p = &app->swq_params[i];\n\t\tuint32_t n_readers = app_swq_get_readers(app, p);\n\t\tuint32_t n_writers = app_swq_get_writers(app, p);\n\n\t\tAPP_CHECK((p->size > 0),\n\t\t\t\"%s size is 0\\n\", p->name);\n\n\t\tAPP_CHECK((rte_is_power_of_2(p->size)),\n\t\t\t\"%s size is not a power of 2\\n\", p->name);\n\n\t\tAPP_CHECK((p->burst_read > 0),\n\t\t\t\"%s read burst size is 0\\n\", p->name);\n\n\t\tAPP_CHECK((p->burst_read <= p->size),\n\t\t\t\"%s read burst size is bigger than its size\\n\",\n\t\t\tp->name);\n\n\t\tAPP_CHECK((p->burst_write > 0),\n\t\t\t\"%s write burst size is 0\\n\", p->name);\n\n\t\tAPP_CHECK((p->burst_write <= p->size),\n\t\t\t\"%s write burst size is bigger than its size\\n\",\n\t\t\tp->name);\n\n\t\tAPP_CHECK((n_readers != 0),\n\t\t\t\"%s has no reader\\n\", p->name);\n\n\t\tAPP_CHECK((n_readers == 1),\n\t\t\t\"%s has more than one reader\\n\", p->name);\n\n\t\tAPP_CHECK((n_writers != 0),\n\t\t\t\"%s has no writer\\n\", p->name);\n\n\t\tAPP_CHECK((n_writers == 1),\n\t\t\t\"%s has more than one writer\\n\", p->name);\n\t}\n}\n\nstatic void\ncheck_tms(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_pktq_tm; i++) {\n\t\tstruct app_pktq_tm_params *p = &app->tm_params[i];\n\t\tuint32_t n_readers = app_tm_get_readers(app, p);\n\t\tuint32_t n_writers = app_tm_get_writers(app, p);\n\n\t\tAPP_CHECK((n_readers != 0),\n\t\t\t\"%s has no reader\\n\", p->name);\n\n\t\tAPP_CHECK((n_readers == 1),\n\t\t\t\"%s has more than one reader\\n\", p->name);\n\n\t\tAPP_CHECK((n_writers != 0),\n\t\t\t\"%s has no writer\\n\", p->name);\n\n\t\tAPP_CHECK((n_writers == 1),\n\t\t\t\"%s has more than one writer\\n\", p->name);\n\t}\n}\n\nstatic void\ncheck_sources(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_pktq_source; i++) {\n\t\tstruct app_pktq_source_params *p = &app->source_params[i];\n\t\tuint32_t n_readers = app_source_get_readers(app, p);\n\n\t\tAPP_CHECK((n_readers != 0),\n\t\t\t\"%s has no reader\\n\", p->name);\n\n\t\tAPP_CHECK((n_readers == 1),\n\t\t\t\"%s has more than one reader\\n\", p->name);\n\t}\n}\n\nstatic void\ncheck_sinks(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_pktq_sink; i++) {\n\t\tstruct app_pktq_sink_params *p = &app->sink_params[i];\n\t\tuint32_t n_writers = app_sink_get_writers(app, p);\n\n\t\tAPP_CHECK((n_writers != 0),\n\t\t\t\"%s has no writer\\n\", p->name);\n\n\t\tAPP_CHECK((n_writers == 1),\n\t\t\t\"%s has more than one writer\\n\", p->name);\n\t}\n}\n\nstatic void\ncheck_msgqs(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_msgq; i++) {\n\t\tstruct app_msgq_params *p = &app->msgq_params[i];\n\t\tuint32_t n_readers = app_msgq_get_readers(app, p);\n\t\tuint32_t n_writers = app_msgq_get_writers(app, p);\n\t\tuint32_t msgq_req_pipeline, msgq_rsp_pipeline;\n\t\tuint32_t msgq_req_core, msgq_rsp_core;\n\n\t\tAPP_CHECK((p->size > 0),\n\t\t\t\"%s size is 0\\n\", p->name);\n\n\t\tAPP_CHECK((rte_is_power_of_2(p->size)),\n\t\t\t\"%s size is not a power of 2\\n\", p->name);\n\n\t\tmsgq_req_pipeline = (strncmp(p->name, \"MSGQ-REQ-PIPELINE\",\n\t\t\tstrlen(\"MSGQ-REQ-PIPELINE\")) == 0);\n\n\t\tmsgq_rsp_pipeline = (strncmp(p->name, \"MSGQ-RSP-PIPELINE\",\n\t\t\tstrlen(\"MSGQ-RSP-PIPELINE\")) == 0);\n\n\t\tmsgq_req_core = (strncmp(p->name, \"MSGQ-REQ-CORE\",\n\t\t\tstrlen(\"MSGQ-REQ-CORE\")) == 0);\n\n\t\tmsgq_rsp_core = (strncmp(p->name, \"MSGQ-RSP-CORE\",\n\t\t\tstrlen(\"MSGQ-RSP-CORE\")) == 0);\n\n\t\tif ((msgq_req_pipeline == 0) &&\n\t\t\t(msgq_rsp_pipeline == 0) &&\n\t\t\t(msgq_req_core == 0) &&\n\t\t\t(msgq_rsp_core == 0)) {\n\t\t\tAPP_CHECK((n_readers != 0),\n\t\t\t\t\"%s has no reader\\n\", p->name);\n\n\t\t\tAPP_CHECK((n_readers == 1),\n\t\t\t\t\"%s has more than one reader\\n\", p->name);\n\n\t\t\tAPP_CHECK((n_writers != 0),\n\t\t\t\t\"%s has no writer\\n\", p->name);\n\n\t\t\tAPP_CHECK((n_writers == 1),\n\t\t\t\t\"%s has more than one writer\\n\", p->name);\n\t\t}\n\n\t\tif (msgq_req_pipeline) {\n\t\t\tstruct app_pipeline_params *pipeline;\n\t\t\tuint32_t pipeline_id;\n\n\t\t\tAPP_PARAM_GET_ID(p, \"MSGQ-REQ-PIPELINE\", pipeline_id);\n\n\t\t\tAPP_PARAM_FIND_BY_ID(app->pipeline_params,\n\t\t\t\t\"PIPELINE\",\n\t\t\t\tpipeline_id,\n\t\t\t\tpipeline);\n\n\t\t\tAPP_CHECK((pipeline != NULL),\n\t\t\t\t\"%s is not associated with a valid pipeline\\n\",\n\t\t\t\tp->name);\n\t\t}\n\n\t\tif (msgq_rsp_pipeline) {\n\t\t\tstruct app_pipeline_params *pipeline;\n\t\t\tuint32_t pipeline_id;\n\n\t\t\tAPP_PARAM_GET_ID(p, \"MSGQ-RSP-PIPELINE\", pipeline_id);\n\n\t\t\tAPP_PARAM_FIND_BY_ID(app->pipeline_params,\n\t\t\t\t\"PIPELINE\",\n\t\t\t\tpipeline_id,\n\t\t\t\tpipeline);\n\n\t\t\tAPP_CHECK((pipeline != NULL),\n\t\t\t\t\"%s is not associated with a valid pipeline\\n\",\n\t\t\t\tp->name);\n\t\t}\n\t}\n}\n\nstatic void\ncheck_pipelines(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_pipelines; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\n\t\tAPP_CHECK((p->n_msgq_in == p->n_msgq_out),\n\t\t\t\"%s number of input MSGQs does not match \"\n\t\t\t\"the number of output MSGQs\\n\", p->name);\n\t}\n}\n\nint\napp_config_check(struct app_params *app)\n{\n\tcheck_mempools(app);\n\tcheck_links(app);\n\tcheck_rxqs(app);\n\tcheck_txqs(app);\n\tcheck_swqs(app);\n\tcheck_tms(app);\n\tcheck_sources(app);\n\tcheck_sinks(app);\n\tcheck_msgqs(app);\n\tcheck_pipelines(app);\n\n\treturn 0;\n}\n" }, { "path": "examples/ip_pipeline/config_parse.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"app.h\"\n\n/**\n * Default config values\n **/\n\nstatic struct app_params app_params_default = {\n\t.config_file = \"./config/ip_pipeline.cfg\",\n\t.log_level = APP_LOG_LEVEL_HIGH,\n\n\t.eal_params = {\n\t\t.channels = 4,\n\t},\n};\n\nstatic const struct app_mempool_params mempool_params_default = {\n\t.parsed = 0,\n\t.buffer_size = 2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM,\n\t.pool_size = 32 * 1024,\n\t.cache_size = 256,\n\t.cpu_socket_id = 0,\n};\n\nstatic const struct app_link_params link_params_default = {\n\t.parsed = 0,\n\t.pmd_id = 0,\n\t.arp_q = 0,\n\t.tcp_syn_local_q = 0,\n\t.ip_local_q = 0,\n\t.tcp_local_q = 0,\n\t.udp_local_q = 0,\n\t.sctp_local_q = 0,\n\t.state = 0,\n\t.ip = 0,\n\t.depth = 0,\n\t.mac_addr = 0,\n\n\t.conf = {\n\t\t.link_speed = 0,\n\t\t.link_duplex = 0,\n\t\t.rxmode = {\n\t\t\t.mq_mode = ETH_MQ_RX_NONE,\n\n\t\t\t.header_split = 0, /* Header split */\n\t\t\t.hw_ip_checksum = 0, /* IP checksum offload */\n\t\t\t.hw_vlan_filter = 0, /* VLAN filtering */\n\t\t\t.hw_vlan_strip = 0, /* VLAN strip */\n\t\t\t.hw_vlan_extend = 0, /* Extended VLAN */\n\t\t\t.jumbo_frame = 0, /* Jumbo frame support */\n\t\t\t.hw_strip_crc = 0, /* CRC strip by HW */\n\t\t\t.enable_scatter = 0, /* Scattered packets RX handler */\n\n\t\t\t.max_rx_pkt_len = 9000, /* Jumbo frame max packet len */\n\t\t\t.split_hdr_size = 0, /* Header split buffer size */\n\t\t},\n\t\t.txmode = {\n\t\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t\t},\n\t\t.lpbk_mode = 0,\n\t},\n\n\t.promisc = 1,\n};\n\nstatic const struct app_pktq_hwq_in_params default_hwq_in_params = {\n\t.parsed = 0,\n\t.mempool_id = 0,\n\t.size = 128,\n\t.burst = 32,\n\n\t.conf = {\n\t\t.rx_thresh = {\n\t\t\t\t.pthresh = 8,\n\t\t\t\t.hthresh = 8,\n\t\t\t\t.wthresh = 4,\n\t\t},\n\t\t.rx_free_thresh = 64,\n\t\t.rx_drop_en = 0,\n\t\t.rx_deferred_start = 0,\n\t}\n};\n\nstatic const struct app_pktq_hwq_out_params default_hwq_out_params = {\n\t.parsed = 0,\n\t.size = 512,\n\t.burst = 32,\n\t.dropless = 0,\n\t.n_retries = 0,\n\n\t.conf = {\n\t\t.tx_thresh = {\n\t\t\t.pthresh = 36,\n\t\t\t.hthresh = 0,\n\t\t\t.wthresh = 0,\n\t\t},\n\t\t.tx_rs_thresh = 0,\n\t\t.tx_free_thresh = 0,\n\t\t.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |\n\t\t\tETH_TXQ_FLAGS_NOOFFLOADS,\n\t\t.tx_deferred_start = 0,\n\t}\n};\n\nstatic const struct app_pktq_swq_params default_swq_params = {\n\t.parsed = 0,\n\t.size = 256,\n\t.burst_read = 32,\n\t.burst_write = 32,\n\t.dropless = 0,\n\t.n_retries = 0,\n\t.cpu_socket_id = 0,\n};\n\nstruct app_pktq_tm_params default_tm_params = {\n\t.parsed = 0,\n\t.file_name = \"./config/tm_profile.cfg\",\n\t.burst_read = 64,\n\t.burst_write = 32,\n};\n\nstruct app_pktq_source_params default_source_params = {\n\t.parsed = 0,\n\t.mempool_id = 0,\n\t.burst = 32,\n};\n\nstruct app_pktq_sink_params default_sink_params = {\n\t.parsed = 0,\n};\n\nstruct app_msgq_params default_msgq_params = {\n\t.parsed = 0,\n\t.size = 64,\n\t.cpu_socket_id = 0,\n};\n\nstruct app_pipeline_params default_pipeline_params = {\n\t.parsed = 0,\n\t.socket_id = 0,\n\t.core_id = 0,\n\t.hyper_th_id = 0,\n\t.n_pktq_in = 0,\n\t.n_pktq_out = 0,\n\t.n_msgq_in = 0,\n\t.n_msgq_out = 0,\n\t.timer_period = 1,\n\t.n_args = 0,\n};\n\nstatic const char app_usage[] =\n\t\"Usage: %s [-f CONFIG_FILE] [-s SCRIPT_FILE] -p PORT_MASK \"\n\t\"[-l LOG_LEVEL]\\n\"\n\t\"\\n\"\n\t\"Arguments:\\n\"\n\t\"\\t-f CONFIG_FILE: Default config file is %s\\n\"\n\t\"\\t-p PORT_MASK: Mask of NIC port IDs in hexadecimal format\\n\"\n\t\"\\t-s SCRIPT_FILE: No CLI script file is run when not specified\\n\"\n\t\"\\t-l LOG_LEVEL: 0 = NONE, 1 = HIGH PRIO (default), 2 = LOW PRIO\\n\"\n\t\"\\n\";\n\nstatic void\napp_print_usage(char *prgname)\n{\n\trte_exit(0, app_usage, prgname, app_params_default.config_file);\n}\n\n#define skip_white_spaces(pos)\t\t\t\\\n({\t\t\t\t\t\t\\\n\t__typeof__(pos) _p = (pos);\t\t\\\n\tfor ( ; isspace(*_p); _p++);\t\t\\\n\t_p;\t\t\t\t\t\\\n})\n\n#define PARSER_IMPLICIT_PARAM_ADD_CHECK(result, section_name)\t\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\tAPP_CHECK((result != -EINVAL),\t\t\t\t\t\\\n\t\t\"CFG: [%s] name too long\", section_name);\t\t\\\n\tAPP_CHECK(result != -ENOMEM,\t\t\t\t\t\\\n\t\t\"CFG: [%s] too much sections\", section_name);\t\t\\\n\tAPP_CHECK(result >= 0,\t\t\t\t\t\t\\\n\t\t\"CFG: [%s] Unknown error while adding '%s'\",\t\t\\\n\t\tsection_name, section_name);\t\t\t\t\\\n} while (0)\n\n#define PARSER_PARAM_ADD_CHECK(result, params_array, section_name)\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\tAPP_CHECK((result != -EINVAL),\t\t\t\t\t\\\n\t\t\"CFG: [%s] name too long\", section_name);\t\t\\\n\tAPP_CHECK((result != -ENOMEM),\t\t\t\t\t\\\n\t\t\"CFG: [%s] too much sections\", section_name);\t\t\\\n\tAPP_CHECK(((result >= 0) && (params_array)[result].parsed == 0),\\\n\t\t\"CFG: [%s] duplicate section\", section_name);\t\t\\\n\tAPP_CHECK((result >= 0),\t\t\t\t\t\\\n\t\t\"CFG: [%s] Unknown error while adding '%s'\",\t\t\\\n\t\tsection_name, section_name);\t\t\t\t\\\n} while (0)\n\nstatic int\nparser_read_arg_bool(const char *p)\n{\n\tp = skip_white_spaces(p);\n\tint result = -EINVAL;\n\n\tif (((p[0] == 'y') && (p[1] == 'e') && (p[2] == 's')) ||\n\t\t((p[0] == 'Y') && (p[1] == 'E') && (p[2] == 'S'))) {\n\t\tp += 3;\n\t\tresult = 1;\n\t}\n\n\tif (((p[0] == 'o') && (p[1] == 'n')) ||\n\t\t((p[0] == 'O') && (p[1] == 'N'))) {\n\t\tp += 2;\n\t\tresult = 1;\n\t}\n\n\tif (((p[0] == 'n') && (p[1] == 'o')) ||\n\t\t((p[0] == 'N') && (p[1] == 'O'))) {\n\t\tp += 2;\n\t\tresult = 0;\n\t}\n\n\tif (((p[0] == 'o') && (p[1] == 'f') && (p[2] == 'f')) ||\n\t\t((p[0] == 'O') && (p[1] == 'F') && (p[2] == 'F'))) {\n\t\tp += 3;\n\t\tresult = 0;\n\t}\n\n\tp = skip_white_spaces(p);\n\n\tif (p[0] != '\\0')\n\t\treturn -EINVAL;\n\n\treturn result;\n}\n\n#define PARSE_ERROR(exp, section, entry)\t\t\t\t\\\nAPP_CHECK(exp, \"Parse error in section \\\"%s\\\": entry \\\"%s\\\"\\n\", section, entry)\n\n#define PARSE_ERROR_MALLOC(exp)\t\t\t\t\t\t\\\nAPP_CHECK(exp, \"Parse error: no free memory\\n\")\n\n#define PARSE_ERROR_SECTION(exp, section)\t\t\t\t\\\nAPP_CHECK(exp, \"Parse error in section \\\"%s\\\"\", section)\n\n#define PARSE_ERROR_SECTION_NO_ENTRIES(exp, section)\t\t\t\\\nAPP_CHECK(exp, \"Parse error in section \\\"%s\\\": no entries\\n\", section)\n\n#define PARSE_WARNING_IGNORED(exp, section, entry)\t\t\t\\\ndo\t\t\t\t\t\t\t\t\t\\\nif (!(exp))\t\t\t\t\t\t\t\t\\\n\tfprintf(stderr, \"Parse warning in section \\\"%s\\\": \"\t\t\\\n\t\t\"entry \\\"%s\\\" is ignored\\n\", section, entry);\t\t\\\nwhile (0)\n\n#define PARSE_ERROR_INVALID(exp, section, entry)\t\t\t\\\nAPP_CHECK(exp, \"Parse error in section \\\"%s\\\": unrecognized entry \\\"%s\\\"\\n\",\\\n\tsection, entry)\n\n#define PARSE_ERROR_DUPLICATE(exp, section, entry)\t\t\t\\\nAPP_CHECK(exp, \"Parse error in section \\\"%s\\\": duplicate entry \\\"%s\\\"\\n\",\\\n\tsection, entry)\n\nstatic int\nparser_read_uint64(uint64_t *value, const char *p)\n{\n\tchar *next;\n\tuint64_t val;\n\n\tp = skip_white_spaces(p);\n\tif (!isdigit(*p))\n\t\treturn -EINVAL;\n\n\tval = strtoul(p, &next, 10);\n\tif (p == next)\n\t\treturn -EINVAL;\n\n\tp = next;\n\tswitch (*p) {\n\tcase 'T':\n\t\tval *= 1024ULL;\n\t\t/* fall trought */\n\tcase 'G':\n\t\tval *= 1024ULL;\n\t\t/* fall trought */\n\tcase 'M':\n\t\tval *= 1024ULL;\n\t\t/* fall trought */\n\tcase 'k':\n\tcase 'K':\n\t\tval *= 1024ULL;\n\t\tp++;\n\t\tbreak;\n\t}\n\n\tp = skip_white_spaces(p);\n\tif (*p != '\\0')\n\t\treturn -EINVAL;\n\n\t*value = val;\n\treturn 0;\n}\n\nstatic int\nparser_read_uint32(uint32_t *value, const char *p)\n{\n\tuint64_t val = 0;\n\tint ret = parser_read_uint64(&val, p);\n\n\tif (ret < 0)\n\t\treturn ret;\n\telse if (val > UINT32_MAX)\n\t\treturn -ERANGE;\n\n\t*value = val;\n\treturn 0;\n}\n\nstatic int\nparse_pipeline_core(uint32_t *socket,\n\tuint32_t *core,\n\tuint32_t *ht,\n\tconst char *entry)\n{\n\tsize_t num_len;\n\tchar num[8];\n\n\tuint32_t s = 0, c = 0, h = 0, val;\n\tuint8_t s_parsed = 0, c_parsed = 0, h_parsed = 0;\n\tconst char *next = skip_white_spaces(entry);\n\tchar type;\n\n\t/* Expect or [sX][cY][h]. At least one parameter is required. */\n\twhile (*next != '\\0') {\n\t\t/* If everything parsed nothing should left */\n\t\tif (s_parsed && c_parsed && h_parsed)\n\t\t\treturn -EINVAL;\n\n\t\ttype = *next;\n\t\tswitch (type) {\n\t\tcase 's':\n\t\tcase 'S':\n\t\t\tif (s_parsed || c_parsed || h_parsed)\n\t\t\t\treturn -EINVAL;\n\t\t\ts_parsed = 1;\n\t\t\tnext++;\n\t\t\tbreak;\n\t\tcase 'c':\n\t\tcase 'C':\n\t\t\tif (c_parsed || h_parsed)\n\t\t\t\treturn -EINVAL;\n\t\t\tc_parsed = 1;\n\t\t\tnext++;\n\t\t\tbreak;\n\t\tcase 'h':\n\t\tcase 'H':\n\t\t\tif (h_parsed)\n\t\t\t\treturn -EINVAL;\n\t\t\th_parsed = 1;\n\t\t\tnext++;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* If it start from digit it must be only core id. */\n\t\t\tif (!isdigit(*next) || s_parsed || c_parsed || h_parsed)\n\t\t\t\treturn -EINVAL;\n\n\t\t\ttype = 'C';\n\t\t}\n\n\t\tfor (num_len = 0; *next != '\\0'; next++, num_len++) {\n\t\t\tif (num_len == RTE_DIM(num))\n\t\t\t\treturn -EINVAL;\n\n\t\t\tif (!isdigit(*next))\n\t\t\t\tbreak;\n\n\t\t\tnum[num_len] = *next;\n\t\t}\n\n\t\tif (num_len == 0 && type != 'h' && type != 'H')\n\t\t\treturn -EINVAL;\n\n\t\tif (num_len != 0 && (type == 'h' || type == 'H'))\n\t\t\treturn -EINVAL;\n\n\t\tnum[num_len] = '\\0';\n\t\tval = strtol(num, NULL, 10);\n\n\t\th = 0;\n\t\tswitch (type) {\n\t\tcase 's':\n\t\tcase 'S':\n\t\t\ts = val;\n\t\t\tbreak;\n\t\tcase 'c':\n\t\tcase 'C':\n\t\t\tc = val;\n\t\t\tbreak;\n\t\tcase 'h':\n\t\tcase 'H':\n\t\t\th = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t*socket = s;\n\t*core = c;\n\t*ht = h;\n\treturn 0;\n}\n\nstatic size_t\nskip_digits(const char *src)\n{\n\tsize_t i;\n\n\tfor (i = 0; isdigit(src[i]); i++);\n\n\treturn i;\n}\n\nstatic int\nvalidate_name(const char *name, const char *prefix, int num)\n{\n\tsize_t i, j;\n\n\tfor (i = 0; (name[i] != '\\0') && (prefix[i] != '\\0'); i++) {\n\t\tif (name[i] != prefix[i])\n\t\t\treturn -1;\n\t}\n\n\tif (prefix[i] != '\\0')\n\t\treturn -1;\n\n\tif (!num) {\n\t\tif (name[i] != '\\0')\n\t\t\treturn -1;\n\t\telse\n\t\t\treturn 0;\n\t}\n\n\tif (num == 2) {\n\t\tj = skip_digits(&name[i]);\n\t\ti += j;\n\t\tif ((j == 0) || (name[i] != '.'))\n\t\t\treturn -1;\n\t\ti++;\n\t}\n\n\tif (num == 1) {\n\t\tj = skip_digits(&name[i]);\n\t\ti += j;\n\t\tif ((j == 0) || (name[i] != '\\0'))\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic void\nparse_eal(struct app_params *app,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg)\n{\n\tstruct app_eal_params *p = &app->eal_params;\n\tstruct rte_cfgfile_entry *entries;\n\tint n_entries, i;\n\n\tn_entries = rte_cfgfile_section_num_entries(cfg, section_name);\n\tPARSE_ERROR_SECTION_NO_ENTRIES((n_entries > 0), section_name);\n\n\tentries = malloc(n_entries * sizeof(struct rte_cfgfile_entry));\n\tPARSE_ERROR_MALLOC(entries != NULL);\n\n\trte_cfgfile_section_entries(cfg, section_name, entries, n_entries);\n\n\tfor (i = 0; i < n_entries; i++) {\n\t\tstruct rte_cfgfile_entry *entry = &entries[i];\n\n\t\t/* coremask */\n\t\tif (strcmp(entry->name, \"c\") == 0) {\n\t\t\tPARSE_WARNING_IGNORED(0, section_name, entry->name);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* corelist */\n\t\tif (strcmp(entry->name, \"l\") == 0) {\n\t\t\tPARSE_WARNING_IGNORED(0, section_name, entry->name);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* coremap */\n\t\tif (strcmp(entry->name, \"lcores\") == 0) {\n\t\t\tPARSE_ERROR_DUPLICATE((p->coremap == NULL),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->coremap = strdup(entry->value);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* master_lcore */\n\t\tif (strcmp(entry->name, \"master_lcore\") == 0) {\n\t\t\tint status;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->master_lcore_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->master_lcore_present = 1;\n\n\t\t\tstatus = parser_read_uint32(&p->master_lcore,\n\t\t\t\tentry->value);\n\t\t\tPARSE_ERROR((status == 0), section_name, entry->name);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* channels */\n\t\tif (strcmp(entry->name, \"n\") == 0) {\n\t\t\tint status;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->channels_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->channels_present = 1;\n\n\t\t\tstatus = parser_read_uint32(&p->channels, entry->value);\n\t\t\tPARSE_ERROR((status == 0), section_name, entry->name);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* memory */\n\t\tif (strcmp(entry->name, \"m\") == 0) {\n\t\t\tint status;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->memory_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->memory_present = 1;\n\n\t\t\tstatus = parser_read_uint32(&p->memory, entry->value);\n\t\t\tPARSE_ERROR((status == 0), section_name, entry->name);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* ranks */\n\t\tif (strcmp(entry->name, \"r\") == 0) {\n\t\t\tint status;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->ranks_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->ranks_present = 1;\n\n\t\t\tstatus = parser_read_uint32(&p->ranks, entry->value);\n\t\t\tPARSE_ERROR((status == 0), section_name, entry->name);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* pci_blacklist */\n\t\tif ((strcmp(entry->name, \"pci_blacklist\") == 0) ||\n\t\t\t(strcmp(entry->name, \"b\") == 0)) {\n\t\t\tPARSE_ERROR_DUPLICATE((p->pci_blacklist == NULL),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->pci_blacklist = strdup(entry->value);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* pci_whitelist */\n\t\tif ((strcmp(entry->name, \"pci_whitelist\") == 0) ||\n\t\t\t(strcmp(entry->name, \"w\") == 0)) {\n\t\t\tPARSE_ERROR_DUPLICATE((p->pci_whitelist == NULL),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->pci_whitelist = strdup(entry->value);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* vdev */\n\t\tif (strcmp(entry->name, \"vdev\") == 0) {\n\t\t\tPARSE_ERROR_DUPLICATE((p->vdev == NULL),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->vdev = strdup(entry->value);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* vmware_tsc_map */\n\t\tif (strcmp(entry->name, \"vmware_tsc_map\") == 0) {\n\t\t\tint val;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->vmware_tsc_map_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->vmware_tsc_map_present = 1;\n\n\t\t\tval = parser_read_arg_bool(entry->value);\n\t\t\tPARSE_ERROR((val >= 0), section_name, entry->name);\n\t\t\tp->vmware_tsc_map = val;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* proc_type */\n\t\tif (strcmp(entry->name, \"proc_type\") == 0) {\n\t\t\tPARSE_ERROR_DUPLICATE((p->proc_type == NULL),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->proc_type = strdup(entry->value);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* syslog */\n\t\tif (strcmp(entry->name, \"syslog\") == 0) {\n\t\t\tPARSE_ERROR_DUPLICATE((p->syslog == NULL),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->syslog = strdup(entry->value);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* log_level */\n\t\tif (strcmp(entry->name, \"log_level\") == 0) {\n\t\t\tint status;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->log_level_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->log_level_present = 1;\n\n\t\t\tstatus = parser_read_uint32(&p->log_level,\n\t\t\t\tentry->value);\n\t\t\tPARSE_ERROR((status == 0), section_name, entry->name);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* version */\n\t\tif (strcmp(entry->name, \"v\") == 0) {\n\t\t\tint val;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->version_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->version_present = 1;\n\n\t\t\tval = parser_read_arg_bool(entry->value);\n\t\t\tPARSE_ERROR((val >= 0), section_name, entry->name);\n\t\t\tp->version = val;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* help */\n\t\tif ((strcmp(entry->name, \"help\") == 0) ||\n\t\t\t(strcmp(entry->name, \"h\") == 0)) {\n\t\t\tint val;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->help_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->help_present = 1;\n\n\t\t\tval = parser_read_arg_bool(entry->value);\n\t\t\tPARSE_ERROR((val >= 0), section_name, entry->name);\n\t\t\tp->help = val;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* no_huge */\n\t\tif (strcmp(entry->name, \"no_huge\") == 0) {\n\t\t\tint val;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->no_huge_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->no_huge_present = 1;\n\n\t\t\tval = parser_read_arg_bool(entry->value);\n\t\t\tPARSE_ERROR((val >= 0), section_name, entry->name);\n\t\t\tp->no_huge = val;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* no_pci */\n\t\tif (strcmp(entry->name, \"no_pci\") == 0) {\n\t\t\tint val;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->no_pci_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->no_pci_present = 1;\n\n\t\t\tval = parser_read_arg_bool(entry->value);\n\t\t\tPARSE_ERROR((val >= 0), section_name, entry->name);\n\t\t\tp->no_pci = val;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* no_hpet */\n\t\tif (strcmp(entry->name, \"no_hpet\") == 0) {\n\t\t\tint val;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->no_hpet_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->no_hpet_present = 1;\n\n\t\t\tval = parser_read_arg_bool(entry->value);\n\t\t\tPARSE_ERROR((val >= 0), section_name, entry->name);\n\t\t\tp->no_hpet = val;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* no_shconf */\n\t\tif (strcmp(entry->name, \"no_shconf\") == 0) {\n\t\t\tint val;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->no_shconf_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->no_shconf_present = 1;\n\n\t\t\tval = parser_read_arg_bool(entry->value);\n\t\t\tPARSE_ERROR((val >= 0), section_name, entry->name);\n\t\t\tp->no_shconf = val;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* add_driver */\n\t\tif (strcmp(entry->name, \"d\") == 0) {\n\t\t\tPARSE_ERROR_DUPLICATE((p->add_driver == NULL),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->add_driver = strdup(entry->value);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* socket_mem */\n\t\tif (strcmp(entry->name, \"socket_mem\") == 0) {\n\t\t\tPARSE_ERROR_DUPLICATE((p->socket_mem == NULL),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->socket_mem = strdup(entry->value);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* huge_dir */\n\t\tif (strcmp(entry->name, \"huge_dir\") == 0) {\n\t\t\tPARSE_ERROR_DUPLICATE((p->huge_dir == NULL),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->huge_dir = strdup(entry->value);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* file_prefix */\n\t\tif (strcmp(entry->name, \"file_prefix\") == 0) {\n\t\t\tPARSE_ERROR_DUPLICATE((p->file_prefix == NULL),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->file_prefix = strdup(entry->value);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* base_virtaddr */\n\t\tif (strcmp(entry->name, \"base_virtaddr\") == 0) {\n\t\t\tPARSE_ERROR_DUPLICATE((p->base_virtaddr == NULL),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->base_virtaddr = strdup(entry->value);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* create_uio_dev */\n\t\tif (strcmp(entry->name, \"create_uio_dev\") == 0) {\n\t\t\tint val;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->create_uio_dev_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->create_uio_dev_present = 1;\n\n\t\t\tval = parser_read_arg_bool(entry->value);\n\t\t\tPARSE_ERROR((val >= 0), section_name, entry->name);\n\t\t\tp->create_uio_dev = val;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* vfio_intr */\n\t\tif (strcmp(entry->name, \"vfio_intr\") == 0) {\n\t\t\tPARSE_ERROR_DUPLICATE((p->vfio_intr == NULL),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->vfio_intr = strdup(entry->value);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* xen_dom0 */\n\t\tif (strcmp(entry->name, \"xen_dom0\") == 0) {\n\t\t\tint val;\n\n\t\t\tPARSE_ERROR_DUPLICATE((p->xen_dom0_present == 0),\n\t\t\t\tsection_name,\n\t\t\t\tentry->name);\n\t\t\tp->xen_dom0_present = 1;\n\n\t\t\tval = parser_read_arg_bool(entry->value);\n\t\t\tPARSE_ERROR((val >= 0), section_name, entry->name);\n\t\t\tp->xen_dom0 = val;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* unrecognized */\n\t\tPARSE_ERROR_INVALID(0, section_name, entry->name);\n\t}\n\n\tfree(entries);\n}\n\nstatic int\nparse_pipeline_pktq_in(struct app_params *app,\n\tstruct app_pipeline_params *p,\n\tconst char *value)\n{\n\tconst char *next = value;\n\tchar *end;\n\tchar name[APP_PARAM_NAME_SIZE];\n\tsize_t name_len;\n\n\twhile (*next != '\\0') {\n\t\tenum app_pktq_in_type type;\n\t\tint id;\n\n\t\tend = strchr(next, ' ');\n\t\tif (!end)\n\t\t\tname_len = strlen(next);\n\t\telse\n\t\t\tname_len = end - next;\n\n\t\tif (name_len == 0 || name_len == sizeof(name))\n\t\t\treturn -EINVAL;\n\n\t\tstrncpy(name, next, name_len);\n\t\tname[name_len] = '\\0';\n\t\tnext += name_len;\n\t\tif (*next != '\\0')\n\t\t\tnext++;\n\n\t\tif (validate_name(name, \"RXQ\", 2) == 0) {\n\t\t\ttype = APP_PKTQ_IN_HWQ;\n\t\t\tid = APP_PARAM_ADD(app->hwq_in_params, name);\n\t\t} else if (validate_name(name, \"SWQ\", 1) == 0) {\n\t\t\ttype = APP_PKTQ_IN_SWQ;\n\t\t\tid = APP_PARAM_ADD(app->swq_params, name);\n\t\t} else if (validate_name(name, \"TM\", 1) == 0) {\n\t\t\ttype = APP_PKTQ_IN_TM;\n\t\t\tid = APP_PARAM_ADD(app->tm_params, name);\n\t\t} else if (validate_name(name, \"SOURCE\", 1) == 0) {\n\t\t\ttype = APP_PKTQ_IN_SOURCE;\n\t\t\tid = APP_PARAM_ADD(app->source_params, name);\n\t\t} else\n\t\t\treturn -EINVAL;\n\n\t\tif (id < 0)\n\t\t\treturn id;\n\n\t\tp->pktq_in[p->n_pktq_in].type = type;\n\t\tp->pktq_in[p->n_pktq_in].id = (uint32_t) id;\n\t\tp->n_pktq_in++;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nparse_pipeline_pktq_out(struct app_params *app,\n\tstruct app_pipeline_params *p,\n\tconst char *value)\n{\n\tconst char *next = value;\n\tchar *end;\n\tchar name[APP_PARAM_NAME_SIZE];\n\tsize_t name_len;\n\n\twhile (*next != '\\0') {\n\t\tenum app_pktq_out_type type;\n\t\tint id;\n\n\t\tend = strchr(next, ' ');\n\t\tif (!end)\n\t\t\tname_len = strlen(next);\n\t\telse\n\t\t\tname_len = end - next;\n\n\t\tif (name_len == 0 || name_len == sizeof(name))\n\t\t\treturn -EINVAL;\n\n\t\tstrncpy(name, next, name_len);\n\t\tname[name_len] = '\\0';\n\t\tnext += name_len;\n\t\tif (*next != '\\0')\n\t\t\tnext++;\n\n\t\tif (validate_name(name, \"TXQ\", 2) == 0) {\n\t\t\ttype = APP_PKTQ_OUT_HWQ;\n\t\t\tid = APP_PARAM_ADD(app->hwq_out_params, name);\n\t\t} else if (validate_name(name, \"SWQ\", 1) == 0) {\n\t\t\ttype = APP_PKTQ_OUT_SWQ;\n\t\t\tid = APP_PARAM_ADD(app->swq_params, name);\n\t\t} else if (validate_name(name, \"TM\", 1) == 0) {\n\t\t\ttype = APP_PKTQ_OUT_TM;\n\t\t\tid = APP_PARAM_ADD(app->tm_params, name);\n\t\t} else if (validate_name(name, \"SINK\", 1) == 0) {\n\t\t\ttype = APP_PKTQ_OUT_SINK;\n\t\t\tid = APP_PARAM_ADD(app->sink_params, name);\n\t\t} else\n\t\t\treturn -EINVAL;\n\n\t\tif (id < 0)\n\t\t\treturn id;\n\n\t\tp->pktq_out[p->n_pktq_out].type = type;\n\t\tp->pktq_out[p->n_pktq_out].id = id;\n\t\tp->n_pktq_out++;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nparse_pipeline_msgq_in(struct app_params *app,\n\tstruct app_pipeline_params *p,\n\tconst char *value)\n{\n\tconst char *next = value;\n\tchar *end;\n\tchar name[APP_PARAM_NAME_SIZE];\n\tsize_t name_len;\n\tssize_t idx;\n\n\twhile (*next != '\\0') {\n\t\tend = strchr(next, ' ');\n\t\tif (!end)\n\t\t\tname_len = strlen(next);\n\t\telse\n\t\t\tname_len = end - next;\n\n\t\tif (name_len == 0 || name_len == sizeof(name))\n\t\t\treturn -EINVAL;\n\n\t\tstrncpy(name, next, name_len);\n\t\tname[name_len] = '\\0';\n\t\tnext += name_len;\n\t\tif (*next != '\\0')\n\t\t\tnext++;\n\n\t\tif (validate_name(name, \"MSGQ\", 1) != 0)\n\t\t\treturn -EINVAL;\n\n\t\tidx = APP_PARAM_ADD(app->msgq_params, name);\n\t\tif (idx < 0)\n\t\t\treturn idx;\n\n\t\tp->msgq_in[p->n_msgq_in] = idx;\n\t\tp->n_msgq_in++;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nparse_pipeline_msgq_out(struct app_params *app,\n\tstruct app_pipeline_params *p,\n\tconst char *value)\n{\n\tconst char *next = value;\n\tchar *end;\n\tchar name[APP_PARAM_NAME_SIZE];\n\tsize_t name_len;\n\tssize_t idx;\n\n\twhile (*next != '\\0') {\n\t\tend = strchr(next, ' ');\n\t\tif (!end)\n\t\t\tname_len = strlen(next);\n\t\telse\n\t\t\tname_len = end - next;\n\n\t\tif (name_len == 0 || name_len == sizeof(name))\n\t\t\treturn -EINVAL;\n\n\t\tstrncpy(name, next, name_len);\n\t\tname[name_len] = '\\0';\n\t\tnext += name_len;\n\t\tif (*next != '\\0')\n\t\t\tnext++;\n\n\t\tif (validate_name(name, \"MSGQ\", 1) != 0)\n\t\t\treturn -EINVAL;\n\n\t\tidx = APP_PARAM_ADD(app->msgq_params, name);\n\t\tif (idx < 0)\n\t\t\treturn idx;\n\n\t\tp->msgq_out[p->n_msgq_out] = idx;\n\t\tp->n_msgq_out++;\n\t}\n\n\treturn 0;\n}\n\n\nstatic void\nparse_pipeline(struct app_params *app,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg)\n{\n\tchar name[CFG_NAME_LEN];\n\tstruct app_pipeline_params *param;\n\tstruct rte_cfgfile_entry *entries;\n\tssize_t param_idx;\n\tint n_entries, ret, i;\n\n\tn_entries = rte_cfgfile_section_num_entries(cfg, section_name);\n\tPARSE_ERROR_SECTION_NO_ENTRIES((n_entries > 0), section_name);\n\n\tentries = malloc(n_entries * sizeof(struct rte_cfgfile_entry));\n\tPARSE_ERROR_MALLOC(entries != NULL);\n\n\trte_cfgfile_section_entries(cfg, section_name, entries, n_entries);\n\n\tparam_idx = APP_PARAM_ADD(app->pipeline_params, section_name);\n\tPARSER_PARAM_ADD_CHECK(param_idx, app->pipeline_params, section_name);\n\n\tparam = &app->pipeline_params[param_idx];\n\tparam->parsed = 1;\n\n\tfor (i = 0; i < n_entries; i++) {\n\t\tstruct rte_cfgfile_entry *ent = &entries[i];\n\n\t\tif (strcmp(ent->name, \"type\") == 0) {\n\t\t\tret = snprintf(param->type,\n\t\t\t\tRTE_DIM(param->type),\n\t\t\t\t\"%s\",\n\t\t\t\tent->value);\n\t\t\tif ((ret > 0) && (ret < (int)RTE_DIM(param->type)))\n\t\t\t\tret = 0;\n\t\t\telse\n\t\t\t\tret = -EINVAL;\n\t\t} else if (strcmp(ent->name, \"core\") == 0)\n\t\t\tret = parse_pipeline_core(¶m->socket_id,\n\t\t\t\t¶m->core_id,\n\t\t\t\t¶m->hyper_th_id,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"pktq_in\") == 0)\n\t\t\tret = parse_pipeline_pktq_in(app, param, ent->value);\n\t\telse if (strcmp(ent->name, \"pktq_out\") == 0)\n\t\t\tret = parse_pipeline_pktq_out(app, param, ent->value);\n\t\telse if (strcmp(ent->name, \"msgq_in\") == 0)\n\t\t\tret = parse_pipeline_msgq_in(app, param, ent->value);\n\t\telse if (strcmp(ent->name, \"msgq_out\") == 0)\n\t\t\tret = parse_pipeline_msgq_out(app, param, ent->value);\n\t\telse if (strcmp(ent->name, \"timer_period\") == 0)\n\t\t\tret = parser_read_uint32(¶m->timer_period,\n\t\t\t\tent->value);\n\t\telse {\n\t\t\tparam->args_name[param->n_args] = strdup(ent->name);\n\t\t\tparam->args_value[param->n_args] = strdup(ent->value);\n\n\t\t\tAPP_CHECK((param->args_name[param->n_args] != NULL) &&\n\t\t\t\t(param->args_value[param->n_args] != NULL),\n\t\t\t\t\"CFG: [%s] out of memory\",\n\t\t\t\tsection_name);\n\n\t\t\tparam->n_args++;\n\t\t\tret = 0;\n\t\t}\n\n\t\tAPP_CHECK(ret == 0,\n\t\t\t\"CFG: [%s] entry '%s': Invalid value '%s'\\n\",\n\t\t\tsection_name,\n\t\t\tent->name,\n\t\t\tent->value);\n\t}\n\n\tsnprintf(name, sizeof(name), \"MSGQ-REQ-%s\", section_name);\n\tparam_idx = APP_PARAM_ADD(app->msgq_params, name);\n\tPARSER_IMPLICIT_PARAM_ADD_CHECK(param_idx, name);\n\tapp->msgq_params[param_idx].cpu_socket_id = param->socket_id;\n\tparam->msgq_in[param->n_msgq_in++] = param_idx;\n\n\tsnprintf(name, sizeof(name), \"MSGQ-RSP-%s\", section_name);\n\tparam_idx = APP_PARAM_ADD(app->msgq_params, name);\n\tPARSER_IMPLICIT_PARAM_ADD_CHECK(param_idx, name);\n\tapp->msgq_params[param_idx].cpu_socket_id = param->socket_id;\n\tparam->msgq_out[param->n_msgq_out++] = param_idx;\n\n\tsnprintf(name, sizeof(name), \"MSGQ-REQ-CORE-s%\" PRIu32 \"c%\" PRIu32 \"%s\",\n\t\tparam->socket_id,\n\t\tparam->core_id,\n\t\t(param->hyper_th_id) ? \"h\" : \"\");\n\tparam_idx = APP_PARAM_ADD(app->msgq_params, name);\n\tPARSER_IMPLICIT_PARAM_ADD_CHECK(param_idx, name);\n\tapp->msgq_params[param_idx].cpu_socket_id = param->socket_id;\n\n\tsnprintf(name, sizeof(name), \"MSGQ-RSP-CORE-s%\" PRIu32 \"c%\" PRIu32 \"%s\",\n\t\tparam->socket_id,\n\t\tparam->core_id,\n\t\t(param->hyper_th_id) ? \"h\" : \"\");\n\tparam_idx = APP_PARAM_ADD(app->msgq_params, name);\n\tPARSER_IMPLICIT_PARAM_ADD_CHECK(param_idx, name);\n\tapp->msgq_params[param_idx].cpu_socket_id = param->socket_id;\n\n\tfree(entries);\n}\n\nstatic void\nparse_mempool(struct app_params *app,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg)\n{\n\tstruct app_mempool_params *param;\n\tstruct rte_cfgfile_entry *entries;\n\tssize_t param_idx;\n\tint n_entries, ret, i;\n\n\tn_entries = rte_cfgfile_section_num_entries(cfg, section_name);\n\tPARSE_ERROR_SECTION_NO_ENTRIES((n_entries > 0), section_name);\n\n\tentries = malloc(n_entries * sizeof(struct rte_cfgfile_entry));\n\tPARSE_ERROR_MALLOC(entries != NULL);\n\n\trte_cfgfile_section_entries(cfg, section_name, entries, n_entries);\n\n\tparam_idx = APP_PARAM_ADD(app->mempool_params, section_name);\n\tPARSER_PARAM_ADD_CHECK(param_idx, app->mempool_params, section_name);\n\n\tparam = &app->mempool_params[param_idx];\n\tparam->parsed = 1;\n\n\tfor (i = 0; i < n_entries; i++) {\n\t\tstruct rte_cfgfile_entry *ent = &entries[i];\n\n\t\tret = -ESRCH;\n\t\tif (strcmp(ent->name, \"buffer_size\") == 0)\n\t\t\tret = parser_read_uint32(¶m->buffer_size,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"pool_size\") == 0)\n\t\t\tret = parser_read_uint32(¶m->pool_size,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"cache_size\") == 0)\n\t\t\tret = parser_read_uint32(¶m->cache_size,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"cpu\") == 0)\n\t\t\tret = parser_read_uint32(¶m->cpu_socket_id,\n\t\t\t\tent->value);\n\n\t\tAPP_CHECK(ret != -ESRCH,\n\t\t\t\"CFG: [%s] entry '%s': unknown entry\\n\",\n\t\t\tsection_name,\n\t\t\tent->name);\n\t\tAPP_CHECK(ret == 0,\n\t\t\t\"CFG: [%s] entry '%s': Invalid value '%s'\\n\",\n\t\t\tsection_name,\n\t\t\tent->name,\n\t\t\tent->value);\n\t}\n\n\tfree(entries);\n}\n\nstatic void\nparse_link(struct app_params *app,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg)\n{\n\tstruct app_link_params *param;\n\tstruct rte_cfgfile_entry *entries;\n\tint n_entries, ret, i;\n\tssize_t param_idx;\n\n\tn_entries = rte_cfgfile_section_num_entries(cfg, section_name);\n\tPARSE_ERROR_SECTION_NO_ENTRIES((n_entries > 0), section_name);\n\n\tentries = malloc(n_entries * sizeof(struct rte_cfgfile_entry));\n\tPARSE_ERROR_MALLOC(entries != NULL);\n\n\trte_cfgfile_section_entries(cfg, section_name, entries, n_entries);\n\n\tparam_idx = APP_PARAM_ADD(app->link_params, section_name);\n\tPARSER_PARAM_ADD_CHECK(param_idx, app->link_params, section_name);\n\n\tparam = &app->link_params[param_idx];\n\tparam->parsed = 1;\n\n\tfor (i = 0; i < n_entries; i++) {\n\t\tstruct rte_cfgfile_entry *ent = &entries[i];\n\n\t\tret = -ESRCH;\n\t\tif (strcmp(ent->name, \"arp_q\") == 0)\n\t\t\tret = parser_read_uint32(¶m->arp_q,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"tcp_syn_q\") == 0)\n\t\t\tret = parser_read_uint32(¶m->tcp_syn_local_q,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"ip_local_q\") == 0)\n\t\t\tret = parser_read_uint32(¶m->ip_local_q,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"tcp_local_q\") == 0)\n\t\t\tret = parser_read_uint32(¶m->tcp_local_q,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"udp_local_q\") == 0)\n\t\t\tret = parser_read_uint32(¶m->udp_local_q,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"sctp_local_q\") == 0)\n\t\t\tret = parser_read_uint32(¶m->sctp_local_q,\n\t\t\t\tent->value);\n\n\t\tAPP_CHECK(ret != -ESRCH,\n\t\t\t\"CFG: [%s] entry '%s': unknown entry\\n\",\n\t\t\tsection_name,\n\t\t\tent->name);\n\t\tAPP_CHECK(ret == 0,\n\t\t\t\"CFG: [%s] entry '%s': Invalid value '%s'\\n\",\n\t\t\tsection_name,\n\t\t\tent->name,\n\t\t\tent->value);\n\t}\n\n\tfree(entries);\n}\n\nstatic void\nparse_rxq(struct app_params *app,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg)\n{\n\tstruct app_pktq_hwq_in_params *param;\n\tstruct rte_cfgfile_entry *entries;\n\tint n_entries, ret, i;\n\tssize_t param_idx;\n\n\tn_entries = rte_cfgfile_section_num_entries(cfg, section_name);\n\tPARSE_ERROR_SECTION_NO_ENTRIES((n_entries > 0), section_name);\n\n\tentries = malloc(n_entries * sizeof(struct rte_cfgfile_entry));\n\tPARSE_ERROR_MALLOC(entries != NULL);\n\n\trte_cfgfile_section_entries(cfg, section_name, entries, n_entries);\n\n\tparam_idx = APP_PARAM_ADD(app->hwq_in_params, section_name);\n\tPARSER_PARAM_ADD_CHECK(param_idx, app->hwq_in_params, section_name);\n\n\tparam = &app->hwq_in_params[param_idx];\n\tparam->parsed = 1;\n\n\tfor (i = 0; i < n_entries; i++) {\n\t\tstruct rte_cfgfile_entry *ent = &entries[i];\n\n\t\tret = -ESRCH;\n\t\tif (strcmp(ent->name, \"mempool\") == 0) {\n\t\t\tint status = validate_name(ent->value, \"MEMPOOL\", 1);\n\t\t\tssize_t idx;\n\n\t\t\tAPP_CHECK((status == 0),\n\t\t\t\t\"CFG: [%s] entry '%s': invalid mempool\\n\",\n\t\t\t\tsection_name,\n\t\t\t\tent->name);\n\n\t\t\tidx = APP_PARAM_ADD(app->mempool_params, ent->value);\n\t\t\tPARSER_IMPLICIT_PARAM_ADD_CHECK(idx, section_name);\n\t\t\tparam->mempool_id = idx;\n\t\t\tret = 0;\n\t\t} else if (strcmp(ent->name, \"size\") == 0)\n\t\t\tret = parser_read_uint32(¶m->size,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"burst\") == 0)\n\t\t\tret = parser_read_uint32(¶m->burst,\n\t\t\t\tent->value);\n\n\t\tAPP_CHECK(ret != -ESRCH,\n\t\t\t\"CFG: [%s] entry '%s': unknown entry\\n\",\n\t\t\tsection_name,\n\t\t\tent->name);\n\t\tAPP_CHECK(ret == 0,\n\t\t\t\"CFG: [%s] entry '%s': Invalid value '%s'\\n\",\n\t\t\tsection_name,\n\t\t\tent->name,\n\t\t\tent->value);\n\t}\n\n\tfree(entries);\n}\n\nstatic void\nparse_txq(struct app_params *app,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg)\n{\n\tstruct app_pktq_hwq_out_params *param;\n\tstruct rte_cfgfile_entry *entries;\n\tint n_entries, ret, i;\n\tssize_t param_idx;\n\n\tn_entries = rte_cfgfile_section_num_entries(cfg, section_name);\n\tPARSE_ERROR_SECTION_NO_ENTRIES((n_entries > 0), section_name);\n\n\tentries = malloc(n_entries * sizeof(struct rte_cfgfile_entry));\n\tPARSE_ERROR_MALLOC(entries != NULL);\n\n\trte_cfgfile_section_entries(cfg, section_name, entries, n_entries);\n\n\tparam_idx = APP_PARAM_ADD(app->hwq_out_params, section_name);\n\tPARSER_PARAM_ADD_CHECK(param_idx, app->hwq_out_params, section_name);\n\n\tparam = &app->hwq_out_params[param_idx];\n\tparam->parsed = 1;\n\n\tfor (i = 0; i < n_entries; i++) {\n\t\tstruct rte_cfgfile_entry *ent = &entries[i];\n\n\t\tret = -ESRCH;\n\t\tif (strcmp(ent->name, \"size\") == 0)\n\t\t\tret = parser_read_uint32(¶m->size, ent->value);\n\t\telse if (strcmp(ent->name, \"burst\") == 0)\n\t\t\tret = parser_read_uint32(¶m->burst, ent->value);\n\t\telse if (strcmp(ent->name, \"dropless\") == 0) {\n\t\t\tret = parser_read_arg_bool(ent->value);\n\t\t\tif (ret >= 0) {\n\t\t\t\tparam->dropless = ret;\n\t\t\t\tret = 0;\n\t\t\t}\n\t\t}\n\n\t\tAPP_CHECK(ret != -ESRCH,\n\t\t\t\"CFG: [%s] entry '%s': unknown entry\\n\",\n\t\t\tsection_name,\n\t\t\tent->name);\n\t\tAPP_CHECK(ret == 0,\n\t\t\t\"CFG: [%s] entry '%s': Invalid value '%s'\\n\",\n\t\t\tsection_name,\n\t\t\tent->name,\n\t\t\tent->value);\n\t}\n\n\tfree(entries);\n}\n\nstatic void\nparse_swq(struct app_params *app,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg)\n{\n\tstruct app_pktq_swq_params *param;\n\tstruct rte_cfgfile_entry *entries;\n\tint n_entries, ret, i;\n\tssize_t param_idx;\n\n\tn_entries = rte_cfgfile_section_num_entries(cfg, section_name);\n\tPARSE_ERROR_SECTION_NO_ENTRIES((n_entries > 0), section_name);\n\n\tentries = malloc(n_entries * sizeof(struct rte_cfgfile_entry));\n\tPARSE_ERROR_MALLOC(entries != NULL);\n\n\trte_cfgfile_section_entries(cfg, section_name, entries, n_entries);\n\n\tparam_idx = APP_PARAM_ADD(app->swq_params, section_name);\n\tPARSER_PARAM_ADD_CHECK(param_idx, app->swq_params, section_name);\n\n\tparam = &app->swq_params[param_idx];\n\tparam->parsed = 1;\n\n\tfor (i = 0; i < n_entries; i++) {\n\t\tstruct rte_cfgfile_entry *ent = &entries[i];\n\n\t\tret = -ESRCH;\n\t\tif (strcmp(ent->name, \"size\") == 0)\n\t\t\tret = parser_read_uint32(¶m->size,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"burst_read\") == 0)\n\t\t\tret = parser_read_uint32(¶m->burst_read,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"burst_write\") == 0)\n\t\t\tret = parser_read_uint32(¶m->burst_write,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"dropless\") == 0) {\n\t\t\tret = parser_read_arg_bool(ent->value);\n\t\t\tif (ret >= 0) {\n\t\t\t\tparam->dropless = ret;\n\t\t\t\tret = 0;\n\t\t\t}\n\t\t} else if (strcmp(ent->name, \"n_retries\") == 0)\n\t\t\tret = parser_read_uint64(¶m->n_retries,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"cpu\") == 0)\n\t\t\tret = parser_read_uint32(¶m->cpu_socket_id,\n\t\t\t\tent->value);\n\n\t\tAPP_CHECK(ret != -ESRCH,\n\t\t\t\"CFG: [%s] entry '%s': unknown entry\\n\",\n\t\t\tsection_name,\n\t\t\tent->name);\n\t\tAPP_CHECK(ret == 0,\n\t\t\t\"CFG: [%s] entry '%s': Invalid value '%s'\\n\",\n\t\t\tsection_name,\n\t\t\tent->name,\n\t\t\tent->value);\n\t}\n\n\tfree(entries);\n}\n\nstatic void\nparse_tm(struct app_params *app,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg)\n{\n\tstruct app_pktq_tm_params *param;\n\tstruct rte_cfgfile_entry *entries;\n\tint n_entries, ret, i;\n\tssize_t param_idx;\n\n\tn_entries = rte_cfgfile_section_num_entries(cfg, section_name);\n\tPARSE_ERROR_SECTION_NO_ENTRIES((n_entries > 0), section_name);\n\n\tentries = malloc(n_entries * sizeof(struct rte_cfgfile_entry));\n\tPARSE_ERROR_MALLOC(entries != NULL);\n\n\trte_cfgfile_section_entries(cfg, section_name, entries, n_entries);\n\n\tparam_idx = APP_PARAM_ADD(app->tm_params, section_name);\n\tPARSER_PARAM_ADD_CHECK(param_idx, app->tm_params, section_name);\n\n\tparam = &app->tm_params[param_idx];\n\tparam->parsed = 1;\n\n\tfor (i = 0; i < n_entries; i++) {\n\t\tstruct rte_cfgfile_entry *ent = &entries[i];\n\n\t\tret = -ESRCH;\n\t\tif (strcmp(ent->name, \"cfg\") == 0) {\n\t\t\tparam->file_name = strdup(ent->value);\n\t\t\tif (param->file_name == NULL)\n\t\t\t\tret = -EINVAL;\n\n\t\t\tret = 0;\n\t\t} else if (strcmp(ent->name, \"burst_read\") == 0)\n\t\t\tret = parser_read_uint32(¶m->burst_read,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"burst_write\") == 0)\n\t\t\tret = parser_read_uint32(¶m->burst_write,\n\t\t\t\tent->value);\n\n\t\tAPP_CHECK(ret != -ESRCH,\n\t\t\t\"CFG: [%s] entry '%s': unknown entry\\n\",\n\t\t\tsection_name,\n\t\t\tent->name);\n\t\tAPP_CHECK(ret != -EBADF,\n\t\t\t\"CFG: [%s] entry '%s': TM cfg parse error '%s'\\n\",\n\t\t\tsection_name,\n\t\t\tent->name,\n\t\t\tent->value);\n\t\tAPP_CHECK(ret == 0,\n\t\t\t\"CFG: [%s] entry '%s': Invalid value '%s'\\n\",\n\t\t\tsection_name,\n\t\t\tent->name,\n\t\t\tent->value);\n\t}\n\n\tfree(entries);\n}\n\nstatic void\nparse_source(struct app_params *app,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg)\n{\n\tstruct app_pktq_source_params *param;\n\tstruct rte_cfgfile_entry *entries;\n\tint n_entries, ret, i;\n\tssize_t param_idx;\n\n\tn_entries = rte_cfgfile_section_num_entries(cfg, section_name);\n\tPARSE_ERROR_SECTION_NO_ENTRIES((n_entries > 0), section_name);\n\n\tentries = malloc(n_entries * sizeof(struct rte_cfgfile_entry));\n\tPARSE_ERROR_MALLOC(entries != NULL);\n\n\trte_cfgfile_section_entries(cfg, section_name, entries, n_entries);\n\n\tparam_idx = APP_PARAM_ADD(app->source_params, section_name);\n\tPARSER_PARAM_ADD_CHECK(param_idx, app->source_params, section_name);\n\n\tparam = &app->source_params[param_idx];\n\tparam->parsed = 1;\n\n\tfor (i = 0; i < n_entries; i++) {\n\t\tstruct rte_cfgfile_entry *ent = &entries[i];\n\n\t\tret = -ESRCH;\n\t\tif (strcmp(ent->name, \"mempool\") == 0) {\n\t\t\tint status = validate_name(ent->value, \"MEMPOOL\", 1);\n\t\t\tssize_t idx;\n\n\t\t\tAPP_CHECK((status == 0),\n\t\t\t\t\"CFG: [%s] entry '%s': invalid mempool\\n\",\n\t\t\t\t\tsection_name,\n\t\t\t\t\tent->name);\n\n\t\t\tidx = APP_PARAM_ADD(app->mempool_params, ent->value);\n\t\t\tPARSER_IMPLICIT_PARAM_ADD_CHECK(idx, section_name);\n\t\t\tparam->mempool_id = idx;\n\t\t\tret = 0;\n\t\t} else if (strcmp(ent->name, \"burst\") == 0)\n\t\t\tret = parser_read_uint32(¶m->burst, ent->value);\n\n\t\tAPP_CHECK(ret != -ESRCH,\n\t\t\t\"CFG: [%s] entry '%s': unknown entry\\n\",\n\t\t\tsection_name,\n\t\t\tent->name);\n\t\tAPP_CHECK(ret == 0,\n\t\t\t\"CFG: [%s] entry '%s': Invalid value '%s'\\n\",\n\t\t\tsection_name,\n\t\t\tent->name,\n\t\t\tent->value);\n\t}\n\n\tfree(entries);\n}\n\nstatic void\nparse_msgq_req_pipeline(struct app_params *app,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg)\n{\n\tstruct app_msgq_params *param;\n\tstruct rte_cfgfile_entry *entries;\n\tint n_entries, ret, i;\n\tssize_t param_idx;\n\n\tn_entries = rte_cfgfile_section_num_entries(cfg, section_name);\n\tPARSE_ERROR_SECTION_NO_ENTRIES((n_entries > 0), section_name);\n\n\tentries = malloc(n_entries * sizeof(struct rte_cfgfile_entry));\n\tPARSE_ERROR_MALLOC(entries != NULL);\n\n\trte_cfgfile_section_entries(cfg, section_name, entries, n_entries);\n\n\tparam_idx = APP_PARAM_ADD(app->msgq_params, section_name);\n\tPARSER_PARAM_ADD_CHECK(param_idx, app->msgq_params, section_name);\n\n\tparam = &app->msgq_params[param_idx];\n\tparam->parsed = 1;\n\n\tfor (i = 0; i < n_entries; i++) {\n\t\tstruct rte_cfgfile_entry *ent = &entries[i];\n\n\t\tret = -ESRCH;\n\t\tif (strcmp(ent->name, \"size\") == 0)\n\t\t\tret = parser_read_uint32(¶m->size, ent->value);\n\n\t\tAPP_CHECK(ret != -ESRCH,\n\t\t\t\"CFG: [%s] entry '%s': unknown entry\\n\",\n\t\t\tsection_name,\n\t\t\tent->name);\n\t\tAPP_CHECK(ret == 0,\n\t\t\t\"CFG: [%s] entry '%s': Invalid value '%s'\\n\",\n\t\t\tsection_name,\n\t\t\tent->name,\n\t\t\tent->value);\n\t}\n\n\tfree(entries);\n}\n\nstatic void\nparse_msgq_rsp_pipeline(struct app_params *app,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg)\n{\n\tstruct app_msgq_params *param;\n\tstruct rte_cfgfile_entry *entries;\n\tint n_entries, ret, i;\n\tssize_t param_idx;\n\n\tn_entries = rte_cfgfile_section_num_entries(cfg, section_name);\n\tPARSE_ERROR_SECTION_NO_ENTRIES((n_entries > 0), section_name);\n\n\tentries = malloc(n_entries * sizeof(struct rte_cfgfile_entry));\n\tPARSE_ERROR_MALLOC(entries != NULL);\n\n\trte_cfgfile_section_entries(cfg, section_name, entries, n_entries);\n\n\tparam_idx = APP_PARAM_ADD(app->msgq_params, section_name);\n\tPARSER_PARAM_ADD_CHECK(param_idx, app->msgq_params, section_name);\n\n\tparam = &app->msgq_params[param_idx];\n\tparam->parsed = 1;\n\n\tfor (i = 0; i < n_entries; i++) {\n\t\tstruct rte_cfgfile_entry *ent = &entries[i];\n\n\t\tret = -ESRCH;\n\t\tif (strcmp(ent->name, \"size\") == 0)\n\t\t\tret = parser_read_uint32(¶m->size, ent->value);\n\n\t\tAPP_CHECK(ret != -ESRCH,\n\t\t\t\"CFG: [%s] entry '%s': unknown entry\\n\",\n\t\t\tsection_name,\n\t\t\tent->name);\n\t\tAPP_CHECK(ret == 0,\n\t\t\t\"CFG: [%s] entry '%s': Invalid value '%s'\\n\",\n\t\t\tsection_name,\n\t\t\tent->name,\n\t\t\tent->value);\n\t}\n\n\tfree(entries);\n}\n\nstatic void\nparse_msgq(struct app_params *app,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg)\n{\n\tstruct app_msgq_params *param;\n\tstruct rte_cfgfile_entry *entries;\n\tint n_entries, ret, i;\n\tssize_t param_idx;\n\n\tn_entries = rte_cfgfile_section_num_entries(cfg, section_name);\n\tPARSE_ERROR_SECTION_NO_ENTRIES((n_entries > 0), section_name);\n\n\tentries = malloc(n_entries * sizeof(struct rte_cfgfile_entry));\n\tPARSE_ERROR_MALLOC(entries != NULL);\n\n\trte_cfgfile_section_entries(cfg, section_name, entries, n_entries);\n\n\tparam_idx = APP_PARAM_ADD(app->msgq_params, section_name);\n\tPARSER_PARAM_ADD_CHECK(param_idx, app->msgq_params, section_name);\n\n\tparam = &app->msgq_params[param_idx];\n\tparam->parsed = 1;\n\n\tfor (i = 0; i < n_entries; i++) {\n\t\tstruct rte_cfgfile_entry *ent = &entries[i];\n\n\t\tret = -ESRCH;\n\t\tif (strcmp(ent->name, \"size\") == 0)\n\t\t\tret = parser_read_uint32(¶m->size,\n\t\t\t\tent->value);\n\t\telse if (strcmp(ent->name, \"cpu\") == 0)\n\t\t\tret = parser_read_uint32(¶m->cpu_socket_id,\n\t\t\t\tent->value);\n\n\t\tAPP_CHECK(ret != -ESRCH,\n\t\t\t\"CFG: [%s] entry '%s': unknown entry\\n\",\n\t\t\tsection_name,\n\t\t\tent->name);\n\t\tAPP_CHECK(ret == 0,\n\t\t\t\"CFG: [%s] entry '%s': Invalid value '%s'\\n\",\n\t\t\tsection_name,\n\t\t\tent->name,\n\t\t\tent->value);\n\t}\n\n\tfree(entries);\n}\n\ntypedef void (*config_section_load)(struct app_params *p,\n\tconst char *section_name,\n\tstruct rte_cfgfile *cfg);\n\nstruct config_section {\n\tconst char prefix[CFG_NAME_LEN];\n\tint numbers;\n\tconfig_section_load load;\n};\n\nstatic const struct config_section cfg_file_scheme[] = {\n\t{\"EAL\", 0, parse_eal},\n\t{\"PIPELINE\", 1, parse_pipeline},\n\t{\"MEMPOOL\", 1, parse_mempool},\n\t{\"LINK\", 1, parse_link},\n\t{\"RXQ\", 2, parse_rxq},\n\t{\"TXQ\", 2, parse_txq},\n\t{\"SWQ\", 1, parse_swq},\n\t{\"TM\", 1, parse_tm},\n\t{\"SOURCE\", 1, parse_source},\n\t{\"MSGQ-REQ-PIPELINE\", 1, parse_msgq_req_pipeline},\n\t{\"MSGQ-RSP-PIPELINE\", 1, parse_msgq_rsp_pipeline},\n\t{\"MSGQ\", 1, parse_msgq},\n};\n\nstatic void\ncreate_implicit_mempools(struct app_params *app)\n{\n\tssize_t idx;\n\n\tidx = APP_PARAM_ADD(app->mempool_params, \"MEMPOOL0\");\n\tPARSER_IMPLICIT_PARAM_ADD_CHECK(idx, \"start-up\");\n}\n\nstatic void\nparse_port_mask(struct app_params *app, uint64_t port_mask)\n{\n\tuint32_t pmd_id, link_id;\n\n\tlink_id = 0;\n\tfor (pmd_id = 0; pmd_id < RTE_MAX_ETHPORTS; pmd_id++) {\n\t\tchar name[APP_PARAM_NAME_SIZE];\n\t\tssize_t idx;\n\n\t\tif ((port_mask & (1LLU << pmd_id)) == 0)\n\t\t\tcontinue;\n\n\t\tsnprintf(name, sizeof(name), \"LINK%\" PRIu32, link_id);\n\t\tidx = APP_PARAM_ADD(app->link_params, name);\n\t\tPARSER_IMPLICIT_PARAM_ADD_CHECK(idx, name);\n\n\t\tapp->link_params[idx].pmd_id = pmd_id;\n\t\tlink_id++;\n\t}\n}\n\nint\napp_config_parse(struct app_params *app, const char *file_name)\n{\n\tchar config_file_out[APP_FILE_NAME_SIZE];\n\tstruct rte_cfgfile *cfg;\n\tchar **section_names;\n\tint i, j, sect_count;\n\n\t/* Implicit mempools */\n\tcreate_implicit_mempools(app);\n\n\t/* Port mask */\n\tparse_port_mask(app, app->port_mask);\n\n\t/* Load application configuration file */\n\tcfg = rte_cfgfile_load(file_name, 0);\n\tAPP_CHECK(cfg != NULL, \"Unable to load config file %s\", file_name);\n\n\tsect_count = rte_cfgfile_num_sections(cfg, NULL, 0);\n\tsection_names = malloc(sect_count * sizeof(char *));\n\tfor (i = 0; i < sect_count; i++)\n\t\tsection_names[i] = malloc(CFG_NAME_LEN);\n\n\trte_cfgfile_sections(cfg, section_names, sect_count);\n\n\tfor (i = 0; i < sect_count; i++) {\n\t\tconst struct config_section *sch_s;\n\t\tint len, cfg_name_len;\n\n\t\tcfg_name_len = strlen(section_names[i]);\n\n\t\t/* Find section type */\n\t\tfor (j = 0; j < (int)RTE_DIM(cfg_file_scheme); j++) {\n\t\t\tsch_s = &cfg_file_scheme[j];\n\t\t\tlen = strlen(sch_s->prefix);\n\n\t\t\tif (cfg_name_len < len)\n\t\t\t\tcontinue;\n\n\t\t\t/* After section name we expect only '\\0' or digit or\n\t\t\t * digit dot digit, so protect against false matching,\n\t\t\t * for example: \"ABC\" should match section name\n\t\t\t * \"ABC0.0\", but it should not match section_name\n\t\t\t * \"ABCDEF\".\n\t\t\t */\n\t\t\tif ((section_names[i][len] != '\\0') &&\n\t\t\t\t!isdigit(section_names[i][len]))\n\t\t\t\tcontinue;\n\n\t\t\tif (strncmp(sch_s->prefix, section_names[i], len) == 0)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tAPP_CHECK(j < (int)RTE_DIM(cfg_file_scheme),\n\t\t\t\"Unknown section %s\",\n\t\t\tsection_names[i]);\n\n\t\tAPP_CHECK(validate_name(section_names[i],\n\t\t\tsch_s->prefix,\n\t\t\tsch_s->numbers) == 0,\n\t\t\t\"Invalid section name '%s'\",\n\t\t\tsection_names[i]);\n\n\t\tsch_s->load(app, section_names[i], cfg);\n\t}\n\n\tfor (i = 0; i < sect_count; i++)\n\t\tfree(section_names[i]);\n\n\tfree(section_names);\n\n\trte_cfgfile_close(cfg);\n\n\tAPP_PARAM_COUNT(app->mempool_params, app->n_mempools);\n\tAPP_PARAM_COUNT(app->link_params, app->n_links);\n\tAPP_PARAM_COUNT(app->hwq_in_params, app->n_pktq_hwq_in);\n\tAPP_PARAM_COUNT(app->hwq_out_params, app->n_pktq_hwq_out);\n\tAPP_PARAM_COUNT(app->swq_params, app->n_pktq_swq);\n\tAPP_PARAM_COUNT(app->tm_params, app->n_pktq_tm);\n\tAPP_PARAM_COUNT(app->source_params, app->n_pktq_source);\n\tAPP_PARAM_COUNT(app->sink_params, app->n_pktq_sink);\n\tAPP_PARAM_COUNT(app->msgq_params, app->n_msgq);\n\tAPP_PARAM_COUNT(app->pipeline_params, app->n_pipelines);\n\n\t/* Save configuration to output file */\n\tsnprintf(config_file_out,\n\t\tAPP_FILE_NAME_SIZE,\n\t\t\"%s.out\",\n\t\tapp->config_file);\n\tapp_config_save(app, config_file_out);\n\n\t/* Load TM configuration files */\n\tapp_config_parse_tm(app);\n\n\treturn 0;\n}\n\nstatic void\nsave_eal_params(struct app_params *app, FILE *f)\n{\n\tstruct app_eal_params *p = &app->eal_params;\n\n\tfprintf(f, \"[EAL]\\n\");\n\n\tif (p->coremap)\n\t\tfprintf(f, \"%s = %s\\n\", \"lcores\", p->coremap);\n\n\tif (p->master_lcore_present)\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\",\n\t\t\t\"master_lcore\", p->master_lcore);\n\n\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"n\", p->channels);\n\n\tif (p->memory_present)\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"m\", p->memory);\n\n\tif (p->ranks_present)\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"r\", p->ranks);\n\n\tif (p->pci_blacklist)\n\t\tfprintf(f, \"%s = %s\\n\", \"pci_blacklist\", p->pci_blacklist);\n\n\tif (p->pci_whitelist)\n\t\tfprintf(f, \"%s = %s\\n\", \"pci_whitelist\", p->pci_whitelist);\n\n\tif (p->vdev)\n\t\tfprintf(f, \"%s = %s\\n\", \"vdev\", p->vdev);\n\n\tif (p->vmware_tsc_map_present)\n\t\tfprintf(f, \"%s = %s\\n\", \"vmware_tsc_map\",\n\t\t\t(p->vmware_tsc_map) ? \"yes\" : \"no\");\n\n\tif (p->proc_type)\n\t\tfprintf(f, \"%s = %s\\n\", \"proc_type\", p->proc_type);\n\n\tif (p->syslog)\n\t\tfprintf(f, \"%s = %s\\n\", \"syslog\", p->syslog);\n\n\tif (p->log_level_present)\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"log_level\", p->log_level);\n\n\tif (p->version_present)\n\t\tfprintf(f, \"%s = %s\\n\",\t\"v\", (p->version) ? \"yes\" : \"no\");\n\n\tif (p->help_present)\n\t\tfprintf(f, \"%s = %s\\n\",\t\"help\", (p->help) ? \"yes\" : \"no\");\n\n\tif (p->no_huge_present)\n\t\tfprintf(f, \"%s = %s\\n\",\t\"no_huge\", (p->no_huge) ? \"yes\" : \"no\");\n\n\tif (p->no_pci_present)\n\t\tfprintf(f, \"%s = %s\\n\",\t\"no_pci\", (p->no_pci) ? \"yes\" : \"no\");\n\n\tif (p->no_hpet_present)\n\t\tfprintf(f, \"%s = %s\\n\",\t\"no_hpet\", (p->no_hpet) ? \"yes\" : \"no\");\n\n\tif (p->no_shconf_present)\n\t\tfprintf(f, \"%s = %s\\n\", \"no_shconf\",\n\t\t\t(p->no_shconf) ? \"yes\" : \"no\");\n\n\tif (p->add_driver)\n\t\tfprintf(f, \"%s = %s\\n\",\t\"d\", p->add_driver);\n\n\tif (p->socket_mem)\n\t\tfprintf(f, \"%s = %s\\n\",\t\"socket_mem\", p->socket_mem);\n\n\tif (p->huge_dir)\n\t\tfprintf(f, \"%s = %s\\n\", \"huge_dir\", p->huge_dir);\n\n\tif (p->file_prefix)\n\t\tfprintf(f, \"%s = %s\\n\", \"file_prefix\", p->file_prefix);\n\n\tif (p->base_virtaddr)\n\t\tfprintf(f, \"%s = %s\\n\",\t\"base_virtaddr\", p->base_virtaddr);\n\n\tif (p->create_uio_dev_present)\n\t\tfprintf(f, \"%s = %s\\n\", \"create_uio_dev\",\n\t\t\t(p->create_uio_dev) ? \"yes\" : \"no\");\n\n\tif (p->vfio_intr)\n\t\tfprintf(f, \"%s = %s\\n\", \"vfio_intr\", p->vfio_intr);\n\n\tif (p->xen_dom0_present)\n\t\tfprintf(f, \"%s = %s\\n\", \"xen_dom0\",\n\t\t\t(p->xen_dom0) ? \"yes\" : \"no\");\n\n\tfputc('\\n', f);\n}\n\nstatic void\nsave_mempool_params(struct app_params *app, FILE *f)\n{\n\tstruct app_mempool_params *p;\n\tsize_t i, count;\n\n\tcount = RTE_DIM(app->mempool_params);\n\tfor (i = 0; i < count; i++) {\n\t\tp = &app->mempool_params[i];\n\t\tif (!APP_PARAM_VALID(p))\n\t\t\tcontinue;\n\n\t\tfprintf(f, \"[%s]\\n\", p->name);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"buffer_size\", p->buffer_size);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"pool_size\", p->pool_size);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"cache_size\", p->cache_size);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"cpu\", p->cpu_socket_id);\n\n\t\tfputc('\\n', f);\n\t}\n}\n\nstatic void\nsave_links_params(struct app_params *app, FILE *f)\n{\n\tstruct app_link_params *p;\n\tsize_t i, count;\n\n\tcount = RTE_DIM(app->link_params);\n\tfor (i = 0; i < count; i++) {\n\t\tp = &app->link_params[i];\n\t\tif (!APP_PARAM_VALID(p))\n\t\t\tcontinue;\n\n\t\tfprintf(f, \"[%s]\\n\", p->name);\n\t\tfprintf(f, \"; %s = %\" PRIu32 \"\\n\", \"pmd_id\", p->pmd_id);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"arp_q\", p->arp_q);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"tcp_syn_local_q\",\n\t\t\tp->tcp_syn_local_q);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"ip_local_q\", p->ip_local_q);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"tcp_local_q\", p->tcp_local_q);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"udp_local_q\", p->udp_local_q);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"sctp_local_q\",\n\t\t\tp->sctp_local_q);\n\n\t\tfputc('\\n', f);\n\t}\n}\n\nstatic void\nsave_rxq_params(struct app_params *app, FILE *f)\n{\n\tstruct app_pktq_hwq_in_params *p;\n\tsize_t i, count;\n\n\tcount = RTE_DIM(app->hwq_in_params);\n\tfor (i = 0; i < count; i++) {\n\t\tp = &app->hwq_in_params[i];\n\t\tif (!APP_PARAM_VALID(p))\n\t\t\tcontinue;\n\n\t\tfprintf(f, \"[%s]\\n\", p->name);\n\t\tfprintf(f, \"%s = %s\\n\",\n\t\t\t\"mempool\",\n\t\t\tapp->mempool_params[p->mempool_id].name);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"size\", p->size);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"burst\", p->burst);\n\n\t\tfputc('\\n', f);\n\t}\n}\n\nstatic void\nsave_txq_params(struct app_params *app, FILE *f)\n{\n\tstruct app_pktq_hwq_out_params *p;\n\tsize_t i, count;\n\n\tcount = RTE_DIM(app->hwq_out_params);\n\tfor (i = 0; i < count; i++) {\n\t\tp = &app->hwq_out_params[i];\n\t\tif (!APP_PARAM_VALID(p))\n\t\t\tcontinue;\n\n\t\tfprintf(f, \"[%s]\\n\", p->name);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"size\", p->size);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"burst\", p->burst);\n\t\tfprintf(f, \"%s = %s\\n\",\n\t\t\t\"dropless\",\n\t\t\tp->dropless ? \"yes\" : \"no\");\n\n\t\tfputc('\\n', f);\n\t}\n}\n\nstatic void\nsave_swq_params(struct app_params *app, FILE *f)\n{\n\tstruct app_pktq_swq_params *p;\n\tsize_t i, count;\n\n\tcount = RTE_DIM(app->swq_params);\n\tfor (i = 0; i < count; i++) {\n\t\tp = &app->swq_params[i];\n\t\tif (!APP_PARAM_VALID(p))\n\t\t\tcontinue;\n\n\t\tfprintf(f, \"[%s]\\n\", p->name);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"size\", p->size);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"burst_read\", p->burst_read);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"burst_write\", p->burst_write);\n\t\tfprintf(f, \"%s = %s\\n\", \"dropless\", p->dropless ? \"yes\" : \"no\");\n\t\tfprintf(f, \"%s = %\" PRIu64 \"\\n\", \"n_retries\", p->n_retries);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"cpu\", p->cpu_socket_id);\n\n\t\tfputc('\\n', f);\n\t}\n}\n\nstatic void\nsave_tm_params(struct app_params *app, FILE *f)\n{\n\tstruct app_pktq_tm_params *p;\n\tsize_t i, count;\n\n\tcount = RTE_DIM(app->tm_params);\n\tfor (i = 0; i < count; i++) {\n\t\tp = &app->tm_params[i];\n\t\tif (!APP_PARAM_VALID(p))\n\t\t\tcontinue;\n\n\t\tfprintf(f, \"[%s]\\n\", p->name);\n\t\tfprintf(f, \"%s = %s\\n\", \"cfg\", p->file_name);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"burst_read\", p->burst_read);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"burst_write\", p->burst_write);\n\n\t\tfputc('\\n', f);\n\t}\n}\n\nstatic void\nsave_source_params(struct app_params *app, FILE *f)\n{\n\tstruct app_pktq_source_params *p;\n\tsize_t i, count;\n\n\tcount = RTE_DIM(app->source_params);\n\tfor (i = 0; i < count; i++) {\n\t\tp = &app->source_params[i];\n\t\tif (!APP_PARAM_VALID(p))\n\t\t\tcontinue;\n\n\t\tfprintf(f, \"[%s]\\n\", p->name);\n\t\tfprintf(f, \"%s = %s\\n\",\n\t\t\t\"mempool\",\n\t\t\tapp->mempool_params[p->mempool_id].name);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"burst\", p->burst);\n\t\tfputc('\\n', f);\n\t}\n}\n\nstatic void\nsave_msgq_params(struct app_params *app, FILE *f)\n{\n\tstruct app_msgq_params *p;\n\tsize_t i, count;\n\n\tcount = RTE_DIM(app->msgq_params);\n\tfor (i = 0; i < count; i++) {\n\t\tp = &app->msgq_params[i];\n\t\tif (!APP_PARAM_VALID(p))\n\t\t\tcontinue;\n\n\t\tfprintf(f, \"[%s]\\n\", p->name);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"size\", p->size);\n\t\tfprintf(f, \"%s = %\" PRIu32 \"\\n\", \"cpu\", p->cpu_socket_id);\n\n\t\tfputc('\\n', f);\n\t}\n}\n\nstatic void\nsave_pipeline_params(struct app_params *app, FILE *f)\n{\n\tsize_t i, count;\n\n\tcount = RTE_DIM(app->pipeline_params);\n\tfor (i = 0; i < count; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\n\t\tif (!APP_PARAM_VALID(p))\n\t\t\tcontinue;\n\n\t\t/* section name */\n\t\tfprintf(f, \"[%s]\\n\", p->name);\n\n\t\t/* type */\n\t\tfprintf(f, \"type = %s\\n\", p->type);\n\n\t\t/* core */\n\t\tfprintf(f, \"core = s%\" PRIu32 \"c%\" PRIu32 \"%s\\n\",\n\t\t\tp->socket_id,\n\t\t\tp->core_id,\n\t\t\t(p->hyper_th_id) ? \"h\" : \"\");\n\n\t\t/* pktq_in */\n\t\tif (p->n_pktq_in) {\n\t\t\tuint32_t j;\n\n\t\t\tfprintf(f, \"pktq_in =\");\n\t\t\tfor (j = 0; j < p->n_pktq_in; j++) {\n\t\t\t\tstruct app_pktq_in_params *pp = &p->pktq_in[j];\n\t\t\t\tchar *name;\n\n\t\t\t\tswitch (pp->type) {\n\t\t\t\tcase APP_PKTQ_IN_HWQ:\n\t\t\t\t\tname = app->hwq_in_params[pp->id].name;\n\t\t\t\t\tbreak;\n\t\t\t\tcase APP_PKTQ_IN_SWQ:\n\t\t\t\t\tname = app->swq_params[pp->id].name;\n\t\t\t\t\tbreak;\n\t\t\t\tcase APP_PKTQ_IN_TM:\n\t\t\t\t\tname = app->tm_params[pp->id].name;\n\t\t\t\t\tbreak;\n\t\t\t\tcase APP_PKTQ_IN_SOURCE:\n\t\t\t\t\tname = app->source_params[pp->id].name;\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tAPP_CHECK(0, \"Error\\n\");\n\t\t\t\t}\n\n\t\t\t\tfprintf(f, \" %s\", name);\n\t\t\t}\n\t\t\tfprintf(f, \"\\n\");\n\t\t}\n\n\t\t/* pktq_in */\n\t\tif (p->n_pktq_out) {\n\t\t\tuint32_t j;\n\n\t\t\tfprintf(f, \"pktq_out =\");\n\t\t\tfor (j = 0; j < p->n_pktq_out; j++) {\n\t\t\t\tstruct app_pktq_out_params *pp =\n\t\t\t\t\t&p->pktq_out[j];\n\t\t\t\tchar *name;\n\n\t\t\t\tswitch (pp->type) {\n\t\t\t\tcase APP_PKTQ_OUT_HWQ:\n\t\t\t\t\tname = app->hwq_out_params[pp->id].name;\n\t\t\t\t\tbreak;\n\t\t\t\tcase APP_PKTQ_OUT_SWQ:\n\t\t\t\t\tname = app->swq_params[pp->id].name;\n\t\t\t\t\tbreak;\n\t\t\t\tcase APP_PKTQ_OUT_TM:\n\t\t\t\t\tname = app->tm_params[pp->id].name;\n\t\t\t\t\tbreak;\n\t\t\t\tcase APP_PKTQ_OUT_SINK:\n\t\t\t\t\tname = app->sink_params[pp->id].name;\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tAPP_CHECK(0, \"Error\\n\");\n\t\t\t\t}\n\n\t\t\t\tfprintf(f, \" %s\", name);\n\t\t\t}\n\t\t\tfprintf(f, \"\\n\");\n\t\t}\n\n\t\t/* msgq_in */\n\t\tif (p->n_msgq_in) {\n\t\t\tuint32_t j;\n\n\t\t\tfprintf(f, \"msgq_in =\");\n\t\t\tfor (j = 0; j < p->n_msgq_in; j++) {\n\t\t\t\tuint32_t id = p->msgq_in[j];\n\t\t\t\tchar *name = app->msgq_params[id].name;\n\n\t\t\t\tfprintf(f, \" %s\", name);\n\t\t\t}\n\t\t\tfprintf(f, \"\\n\");\n\t\t}\n\n\t\t/* msgq_out */\n\t\tif (p->n_msgq_in) {\n\t\t\tuint32_t j;\n\n\t\t\tfprintf(f, \"msgq_out =\");\n\t\t\tfor (j = 0; j < p->n_msgq_out; j++) {\n\t\t\t\tuint32_t id = p->msgq_out[j];\n\t\t\t\tchar *name = app->msgq_params[id].name;\n\n\t\t\t\tfprintf(f, \" %s\", name);\n\t\t\t}\n\t\t\tfprintf(f, \"\\n\");\n\t\t}\n\n\t\t/* timer_period */\n\t\tfprintf(f, \"timer_period = %\" PRIu32 \"\\n\", p->timer_period);\n\n\t\t/* args */\n\t\tif (p->n_args) {\n\t\t\tuint32_t j;\n\n\t\t\tfor (j = 0; j < p->n_args; j++)\n\t\t\t\tfprintf(f, \"%s = %s\\n\", p->args_name[j],\n\t\t\t\t\tp->args_value[j]);\n\t\t}\n\n\t\tfprintf(f, \"\\n\");\n\t}\n}\n\nvoid\napp_config_save(struct app_params *app, const char *file_name)\n{\n\tFILE *file;\n\tchar *name, *dir_name;\n\tint status;\n\n\tname = strdup(file_name);\n\tdir_name = dirname(name);\n\tstatus = access(dir_name, W_OK);\n\tAPP_CHECK((status == 0),\n\t\t\"Need write access to directory \\\"%s\\\" to save configuration\\n\",\n\t\tdir_name);\n\n\tfile = fopen(file_name, \"w\");\n\tAPP_CHECK((file != NULL),\n\t\t\"Failed to save configuration to file \\\"%s\\\"\", file_name);\n\n\tsave_eal_params(app, file);\n\tsave_pipeline_params(app, file);\n\tsave_mempool_params(app, file);\n\tsave_links_params(app, file);\n\tsave_rxq_params(app, file);\n\tsave_txq_params(app, file);\n\tsave_swq_params(app, file);\n\tsave_tm_params(app, file);\n\tsave_source_params(app, file);\n\tsave_msgq_params(app, file);\n\n\tfclose(file);\n\tfree(name);\n}\n\nint\napp_config_init(struct app_params *app)\n{\n\tsize_t i;\n\n\tmemcpy(app, &app_params_default, sizeof(struct app_params));\n\n\tfor (i = 0; i < RTE_DIM(app->mempool_params); i++)\n\t\tmemcpy(&app->mempool_params[i],\n\t\t\t&mempool_params_default,\n\t\t\tsizeof(struct app_mempool_params));\n\n\tfor (i = 0; i < RTE_DIM(app->link_params); i++)\n\t\tmemcpy(&app->link_params[i],\n\t\t\t&link_params_default,\n\t\t\tsizeof(struct app_link_params));\n\n\tfor (i = 0; i < RTE_DIM(app->hwq_in_params); i++)\n\t\tmemcpy(&app->hwq_in_params[i],\n\t\t\t&default_hwq_in_params,\n\t\t\tsizeof(default_hwq_in_params));\n\n\tfor (i = 0; i < RTE_DIM(app->hwq_out_params); i++)\n\t\tmemcpy(&app->hwq_out_params[i],\n\t\t\t&default_hwq_out_params,\n\t\t\tsizeof(default_hwq_out_params));\n\n\tfor (i = 0; i < RTE_DIM(app->swq_params); i++)\n\t\tmemcpy(&app->swq_params[i],\n\t\t\t&default_swq_params,\n\t\t\tsizeof(default_swq_params));\n\n\tfor (i = 0; i < RTE_DIM(app->tm_params); i++)\n\t\tmemcpy(&app->tm_params[i],\n\t\t\t&default_tm_params,\n\t\t\tsizeof(default_tm_params));\n\n\tfor (i = 0; i < RTE_DIM(app->source_params); i++)\n\t\tmemcpy(&app->source_params[i],\n\t\t\t&default_source_params,\n\t\t\tsizeof(default_source_params));\n\n\tfor (i = 0; i < RTE_DIM(app->sink_params); i++)\n\t\tmemcpy(&app->sink_params[i],\n\t\t\t&default_sink_params,\n\t\t\tsizeof(default_sink_params));\n\n\tfor (i = 0; i < RTE_DIM(app->msgq_params); i++)\n\t\tmemcpy(&app->msgq_params[i],\n\t\t\t&default_msgq_params,\n\t\t\tsizeof(default_msgq_params));\n\n\tfor (i = 0; i < RTE_DIM(app->pipeline_params); i++)\n\t\tmemcpy(&app->pipeline_params[i],\n\t\t\t&default_pipeline_params,\n\t\t\tsizeof(default_pipeline_params));\n\n\treturn 0;\n}\n\nint\napp_config_args(struct app_params *app, int argc, char **argv)\n{\n\tint opt;\n\tint option_index, f_present, s_present, p_present, l_present;\n\tint scaned = 0;\n\n\tstatic struct option lgopts[] = {\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\t/* Copy application name */\n\tstrncpy(app->app_name, argv[0], APP_APPNAME_SIZE - 1);\n\n\tf_present = 0;\n\ts_present = 0;\n\tp_present = 0;\n\tl_present = 0;\n\n\twhile ((opt = getopt_long(argc, argv, \"f:s:p:l:\", lgopts,\n\t\t\t&option_index)) != EOF)\n\t\tswitch (opt) {\n\t\tcase 'f':\n\t\t\tif (f_present)\n\t\t\t\trte_panic(\"Error: Config file is provided \"\n\t\t\t\t\t\"more than once\\n\");\n\t\t\tf_present = 1;\n\n\t\t\tif (!strlen(optarg))\n\t\t\t\trte_panic(\"Error: Config file name is null\\n\");\n\n\t\t\tapp->config_file = strdup(optarg);\n\t\t\tif (app->config_file == NULL)\n\t\t\t\trte_panic(\"Error: Memory allocation failure\\n\");\n\n\t\t\tbreak;\n\n\t\tcase 's':\n\t\t\tif (s_present)\n\t\t\t\trte_panic(\"Error: Script file is provided \"\n\t\t\t\t\t\"more than once\\n\");\n\t\t\ts_present = 1;\n\n\t\t\tif (!strlen(optarg))\n\t\t\t\trte_panic(\"Error: Script file name is null\\n\");\n\n\t\t\tapp->script_file = strdup(optarg);\n\t\t\tif (app->script_file == NULL)\n\t\t\t\trte_panic(\"Error: Memory allocation failure\\n\");\n\n\t\t\tbreak;\n\n\t\tcase 'p':\n\t\t\tif (p_present)\n\t\t\t\trte_panic(\"Error: PORT_MASK is provided \"\n\t\t\t\t\t\"more than once\\n\");\n\t\t\tp_present = 1;\n\n\t\t\tif ((sscanf(optarg, \"%\" SCNx64 \"%n\", &app->port_mask,\n\t\t\t\t&scaned) != 1) ||\n\t\t\t\t((size_t) scaned != strlen(optarg)))\n\t\t\t\trte_panic(\"Error: PORT_MASK is not \"\n\t\t\t\t\t\"a hexadecimal integer\\n\");\n\n\t\t\tif (app->port_mask == 0)\n\t\t\t\trte_panic(\"Error: PORT_MASK is null\\n\");\n\n\t\t\tbreak;\n\n\t\tcase 'l':\n\t\t\tif (l_present)\n\t\t\t\trte_panic(\"Error: LOG_LEVEL is provided \"\n\t\t\t\t\t\"more than once\\n\");\n\t\t\tl_present = 1;\n\n\t\t\tif ((sscanf(optarg, \"%\" SCNu32 \"%n\", &app->log_level,\n\t\t\t\t&scaned) != 1) ||\n\t\t\t\t((size_t) scaned != strlen(optarg)) ||\n\t\t\t\t(app->log_level >= APP_LOG_LEVELS))\n\t\t\t\trte_panic(\"Error: LOG_LEVEL invalid value\\n\");\n\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tapp_print_usage(argv[0]);\n\t\t}\n\n\toptind = 0; /* reset getopt lib */\n\n\t/* Check that mandatory args have been provided */\n\tif (!p_present)\n\t\trte_panic(\"Error: PORT_MASK is not provided\\n\");\n\n\treturn 0;\n}\n" }, { "path": "examples/ip_pipeline/config_parse_tm.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"app.h\"\n\nstatic int\ntm_cfgfile_load_sched_port(\n\tstruct rte_cfgfile *file,\n\tstruct rte_sched_port_params *port_params)\n{\n\tconst char *entry;\n\tint j;\n\n\tentry = rte_cfgfile_get_entry(file, \"port\", \"frame overhead\");\n\tif (entry)\n\t\tport_params->frame_overhead = (uint32_t)atoi(entry);\n\n\tentry = rte_cfgfile_get_entry(file, \"port\", \"mtu\");\n\tif (entry)\n\t\tport_params->mtu = (uint32_t)atoi(entry);\n\n\tentry = rte_cfgfile_get_entry(file,\n\t\t\"port\",\n\t\t\"number of subports per port\");\n\tif (entry)\n\t\tport_params->n_subports_per_port = (uint32_t) atoi(entry);\n\n\tentry = rte_cfgfile_get_entry(file,\n\t\t\"port\",\n\t\t\"number of pipes per subport\");\n\tif (entry)\n\t\tport_params->n_pipes_per_subport = (uint32_t) atoi(entry);\n\n\tentry = rte_cfgfile_get_entry(file, \"port\", \"queue sizes\");\n\tif (entry) {\n\t\tchar *next;\n\n\t\tfor (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {\n\t\t\tport_params->qsize[j] = (uint16_t)\n\t\t\t\tstrtol(entry, &next, 10);\n\t\t\tif (next == NULL)\n\t\t\t\tbreak;\n\t\t\tentry = next;\n\t\t}\n\t}\n\n#ifdef RTE_SCHED_RED\n\tfor (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {\n\t\tchar str[32];\n\n\t\t/* Parse WRED min thresholds */\n\t\tsnprintf(str, sizeof(str), \"tc %\" PRId32 \" wred min\", j);\n\t\tentry = rte_cfgfile_get_entry(file, \"red\", str);\n\t\tif (entry) {\n\t\t\tchar *next;\n\t\t\tint k;\n\n\t\t\t/* for each packet colour (green, yellow, red) */\n\t\t\tfor (k = 0; k < e_RTE_METER_COLORS; k++) {\n\t\t\t\tport_params->red_params[j][k].min_th\n\t\t\t\t\t= (uint16_t)strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t\t}\n\n\t\t/* Parse WRED max thresholds */\n\t\tsnprintf(str, sizeof(str), \"tc %\" PRId32 \" wred max\", j);\n\t\tentry = rte_cfgfile_get_entry(file, \"red\", str);\n\t\tif (entry) {\n\t\t\tchar *next;\n\t\t\tint k;\n\n\t\t\t/* for each packet colour (green, yellow, red) */\n\t\t\tfor (k = 0; k < e_RTE_METER_COLORS; k++) {\n\t\t\t\tport_params->red_params[j][k].max_th\n\t\t\t\t\t= (uint16_t)strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t\t}\n\n\t\t/* Parse WRED inverse mark probabilities */\n\t\tsnprintf(str, sizeof(str), \"tc %\" PRId32 \" wred inv prob\", j);\n\t\tentry = rte_cfgfile_get_entry(file, \"red\", str);\n\t\tif (entry) {\n\t\t\tchar *next;\n\t\t\tint k;\n\n\t\t\t/* for each packet colour (green, yellow, red) */\n\t\t\tfor (k = 0; k < e_RTE_METER_COLORS; k++) {\n\t\t\t\tport_params->red_params[j][k].maxp_inv\n\t\t\t\t\t= (uint8_t)strtol(entry, &next, 10);\n\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t\t}\n\n\t\t/* Parse WRED EWMA filter weights */\n\t\tsnprintf(str, sizeof(str), \"tc %\" PRId32 \" wred weight\", j);\n\t\tentry = rte_cfgfile_get_entry(file, \"red\", str);\n\t\tif (entry) {\n\t\t\tchar *next;\n\t\t\tint k;\n\n\t\t\t/* for each packet colour (green, yellow, red) */\n\t\t\tfor (k = 0; k < e_RTE_METER_COLORS; k++) {\n\t\t\t\tport_params->red_params[j][k].wq_log2\n\t\t\t\t\t= (uint8_t)strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t\t}\n\t}\n#endif /* RTE_SCHED_RED */\n\n\treturn 0;\n}\n\nstatic int\ntm_cfgfile_load_sched_pipe(\n\tstruct rte_cfgfile *file,\n\tstruct rte_sched_port_params *port_params,\n\tstruct rte_sched_pipe_params *pipe_params)\n{\n\tint i, j;\n\tchar *next;\n\tconst char *entry;\n\tint profiles;\n\n\tprofiles = rte_cfgfile_num_sections(file,\n\t\t\"pipe profile\", sizeof(\"pipe profile\") - 1);\n\tport_params->n_pipe_profiles = profiles;\n\n\tfor (j = 0; j < profiles; j++) {\n\t\tchar pipe_name[32];\n\n\t\tsnprintf(pipe_name, sizeof(pipe_name),\n\t\t\t\"pipe profile %\" PRId32, j);\n\n\t\tentry = rte_cfgfile_get_entry(file, pipe_name, \"tb rate\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tb_rate = (uint32_t) atoi(entry);\n\n\t\tentry = rte_cfgfile_get_entry(file, pipe_name, \"tb size\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tb_size = (uint32_t) atoi(entry);\n\n\t\tentry = rte_cfgfile_get_entry(file, pipe_name, \"tc period\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tc_period = (uint32_t) atoi(entry);\n\n\t\tentry = rte_cfgfile_get_entry(file, pipe_name, \"tc 0 rate\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tc_rate[0] = (uint32_t) atoi(entry);\n\n\t\tentry = rte_cfgfile_get_entry(file, pipe_name, \"tc 1 rate\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tc_rate[1] = (uint32_t) atoi(entry);\n\n\t\tentry = rte_cfgfile_get_entry(file, pipe_name, \"tc 2 rate\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tc_rate[2] = (uint32_t) atoi(entry);\n\n\t\tentry = rte_cfgfile_get_entry(file, pipe_name, \"tc 3 rate\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tc_rate[3] = (uint32_t) atoi(entry);\n\n#ifdef RTE_SCHED_SUBPORT_TC_OV\n\t\tentry = rte_cfgfile_get_entry(file, pipe_name,\n\t\t\t\"tc 3 oversubscription weight\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tc_ov_weight = (uint8_t)atoi(entry);\n#endif\n\n\t\tentry = rte_cfgfile_get_entry(file,\n\t\t\tpipe_name,\n\t\t\t\"tc 0 wrr weights\");\n\t\tif (entry)\n\t\t\tfor (i = 0; i < RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; i++) {\n\t\t\t\tpipe_params[j].wrr_weights[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE*0 + i] =\n\t\t\t\t\t(uint8_t) strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\n\t\tentry = rte_cfgfile_get_entry(file, pipe_name, \"tc 1 wrr weights\");\n\t\tif (entry)\n\t\t\tfor (i = 0; i < RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; i++) {\n\t\t\t\tpipe_params[j].wrr_weights[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE*1 + i] =\n\t\t\t\t\t(uint8_t) strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\n\t\tentry = rte_cfgfile_get_entry(file, pipe_name, \"tc 2 wrr weights\");\n\t\tif (entry)\n\t\t\tfor (i = 0; i < RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; i++) {\n\t\t\t\tpipe_params[j].wrr_weights[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE*2 + i] =\n\t\t\t\t\t(uint8_t) strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\n\t\tentry = rte_cfgfile_get_entry(file, pipe_name, \"tc 3 wrr weights\");\n\t\tif (entry)\n\t\t\tfor (i = 0; i < RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; i++) {\n\t\t\t\tpipe_params[j].wrr_weights[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE*3 + i] =\n\t\t\t\t\t(uint8_t) strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\ntm_cfgfile_load_sched_subport(\n\tstruct rte_cfgfile *file,\n\tstruct rte_sched_subport_params *subport_params,\n\tint *pipe_to_profile)\n{\n\tconst char *entry;\n\tint i, j, k;\n\n\tfor (i = 0; i < APP_MAX_SCHED_SUBPORTS; i++) {\n\t\tchar sec_name[CFG_NAME_LEN];\n\n\t\tsnprintf(sec_name, sizeof(sec_name),\n\t\t\t\"subport %\" PRId32, i);\n\n\t\tif (rte_cfgfile_has_section(file, sec_name)) {\n\t\t\tentry = rte_cfgfile_get_entry(file,\n\t\t\t\tsec_name,\n\t\t\t\t\"tb rate\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tb_rate =\n\t\t\t\t\t(uint32_t) atoi(entry);\n\n\t\t\tentry = rte_cfgfile_get_entry(file,\n\t\t\t\tsec_name,\n\t\t\t\t\"tb size\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tb_size =\n\t\t\t\t\t(uint32_t) atoi(entry);\n\n\t\t\tentry = rte_cfgfile_get_entry(file,\n\t\t\t\tsec_name,\n\t\t\t\t\"tc period\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tc_period =\n\t\t\t\t\t(uint32_t) atoi(entry);\n\n\t\t\tentry = rte_cfgfile_get_entry(file,\n\t\t\t\tsec_name,\n\t\t\t\t\"tc 0 rate\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tc_rate[0] =\n\t\t\t\t\t(uint32_t) atoi(entry);\n\n\t\t\tentry = rte_cfgfile_get_entry(file,\n\t\t\t\tsec_name,\n\t\t\t\t\"tc 1 rate\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tc_rate[1] =\n\t\t\t\t\t(uint32_t) atoi(entry);\n\n\t\t\tentry = rte_cfgfile_get_entry(file,\n\t\t\t\tsec_name,\n\t\t\t\t\"tc 2 rate\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tc_rate[2] =\n\t\t\t\t\t(uint32_t) atoi(entry);\n\n\t\t\tentry = rte_cfgfile_get_entry(file,\n\t\t\t\tsec_name,\n\t\t\t\t\"tc 3 rate\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tc_rate[3] =\n\t\t\t\t\t(uint32_t) atoi(entry);\n\n\t\t\tint n_entries = rte_cfgfile_section_num_entries(file,\n\t\t\t\tsec_name);\n\t\t\tstruct rte_cfgfile_entry entries[n_entries];\n\n\t\t\trte_cfgfile_section_entries(file,\n\t\t\t\tsec_name,\n\t\t\t\tentries,\n\t\t\t\tn_entries);\n\n\t\t\tfor (j = 0; j < n_entries; j++)\n\t\t\t\tif (strncmp(\"pipe\",\n\t\t\t\t\tentries[j].name,\n\t\t\t\t\tsizeof(\"pipe\") - 1) == 0) {\n\t\t\t\t\tint profile;\n\t\t\t\t\tchar *tokens[2] = {NULL, NULL};\n\t\t\t\t\tint n_tokens;\n\t\t\t\t\tint begin, end;\n\t\t\t\t\tchar name[CFG_NAME_LEN];\n\n\t\t\t\t\tprofile = atoi(entries[j].value);\n\t\t\t\t\tstrncpy(name,\n\t\t\t\t\t\tentries[j].name,\n\t\t\t\t\t\tsizeof(name));\n\t\t\t\t\tn_tokens = rte_strsplit(\n\t\t\t\t\t\t&name[sizeof(\"pipe\")],\n\t\t\t\t\t\tstrnlen(name, CFG_NAME_LEN),\n\t\t\t\t\t\t\ttokens, 2, '-');\n\n\t\t\t\t\tbegin = atoi(tokens[0]);\n\t\t\t\t\tif (n_tokens == 2)\n\t\t\t\t\t\tend = atoi(tokens[1]);\n\t\t\t\t\telse\n\t\t\t\t\t\tend = begin;\n\n\t\t\t\t\tif ((end >= APP_MAX_SCHED_PIPES) ||\n\t\t\t\t\t\t(begin > end))\n\t\t\t\t\t\treturn -1;\n\n\t\t\t\t\tfor (k = begin; k <= end; k++) {\n\t\t\t\t\t\tchar profile_name[CFG_NAME_LEN];\n\n\t\t\t\t\t\tsnprintf(profile_name,\n\t\t\t\t\t\t\tsizeof(profile_name),\n\t\t\t\t\t\t\t\"pipe profile %\" PRId32,\n\t\t\t\t\t\t\tprofile);\n\t\t\t\t\t\tif (rte_cfgfile_has_section(file, profile_name))\n\t\t\t\t\t\t\tpipe_to_profile[i * APP_MAX_SCHED_PIPES + k] = profile;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t\t\t\"Wrong pipe profile %s\\n\",\n\t\t\t\t\t\t\t\tentries[j].value);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\ntm_cfgfile_load(struct app_pktq_tm_params *tm)\n{\n\tstruct rte_cfgfile *file;\n\tuint32_t i;\n\n\tmemset(tm->sched_subport_params, 0, sizeof(tm->sched_subport_params));\n\tmemset(tm->sched_pipe_profiles, 0, sizeof(tm->sched_pipe_profiles));\n\tmemset(&tm->sched_port_params, 0, sizeof(tm->sched_pipe_profiles));\n\tfor (i = 0; i < APP_MAX_SCHED_SUBPORTS * APP_MAX_SCHED_PIPES; i++)\n\t\ttm->sched_pipe_to_profile[i] = -1;\n\n\ttm->sched_port_params.pipe_profiles = &tm->sched_pipe_profiles[0];\n\n\tif (tm->file_name[0] == '\\0')\n\t\treturn -1;\n\n\tfile = rte_cfgfile_load(tm->file_name, 0);\n\tif (file == NULL)\n\t\treturn -1;\n\n\ttm_cfgfile_load_sched_port(file,\n\t\t&tm->sched_port_params);\n\ttm_cfgfile_load_sched_subport(file,\n\t\ttm->sched_subport_params,\n\t\ttm->sched_pipe_to_profile);\n\ttm_cfgfile_load_sched_pipe(file,\n\t\t&tm->sched_port_params,\n\t\ttm->sched_pipe_profiles);\n\n\trte_cfgfile_close(file);\n\treturn 0;\n}\n\nint\napp_config_parse_tm(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < RTE_DIM(app->tm_params); i++) {\n\t\tstruct app_pktq_tm_params *p = &app->tm_params[i];\n\t\tint status;\n\n\t\tif (!APP_PARAM_VALID(p))\n\t\t\tbreak;\n\n\t\tstatus = tm_cfgfile_load(p);\n\t\tAPP_CHECK(status == 0,\n\t\t\t\"Parse error for %s configuration file \\\"%s\\\"\\n\",\n\t\t\tp->name,\n\t\t\tp->file_name);\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/ip_pipeline/cpu_core_map.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n\n#include \"cpu_core_map.h\"\n\nstruct cpu_core_map {\n\tuint32_t n_max_sockets;\n\tuint32_t n_max_cores_per_socket;\n\tuint32_t n_max_ht_per_core;\n\tuint32_t n_sockets;\n\tuint32_t n_cores_per_socket;\n\tuint32_t n_ht_per_core;\n\tint map[0];\n};\n\nstatic inline uint32_t\ncpu_core_map_pos(struct cpu_core_map *map,\n\tuint32_t socket_id,\n\tuint32_t core_id,\n\tuint32_t ht_id)\n{\n\treturn (socket_id * map->n_max_cores_per_socket + core_id) *\n\t\tmap->n_max_ht_per_core + ht_id;\n}\n\nstatic int\ncpu_core_map_compute_eal(struct cpu_core_map *map);\n\nstatic int\ncpu_core_map_compute_linux(struct cpu_core_map *map);\n\nstatic int\ncpu_core_map_compute_and_check(struct cpu_core_map *map);\n\nstruct cpu_core_map *\ncpu_core_map_init(uint32_t n_max_sockets,\n\tuint32_t n_max_cores_per_socket,\n\tuint32_t n_max_ht_per_core,\n\tuint32_t eal_initialized)\n{\n\tuint32_t map_size, map_mem_size, i;\n\tstruct cpu_core_map *map;\n\tint status;\n\n\t/* Check input arguments */\n\tif ((n_max_sockets == 0) ||\n\t\t(n_max_cores_per_socket == 0) ||\n\t\t(n_max_ht_per_core == 0))\n\t\treturn NULL;\n\n\t/* Memory allocation */\n\tmap_size = n_max_sockets * n_max_cores_per_socket * n_max_ht_per_core;\n\tmap_mem_size = sizeof(struct cpu_core_map) + map_size * sizeof(int);\n\tmap = (struct cpu_core_map *) malloc(map_mem_size);\n\tif (map == NULL)\n\t\treturn NULL;\n\n\t/* Initialization */\n\tmap->n_max_sockets = n_max_sockets;\n\tmap->n_max_cores_per_socket = n_max_cores_per_socket;\n\tmap->n_max_ht_per_core = n_max_ht_per_core;\n\tmap->n_sockets = 0;\n\tmap->n_cores_per_socket = 0;\n\tmap->n_ht_per_core = 0;\n\n\tfor (i = 0; i < map_size; i++)\n\t\tmap->map[i] = -1;\n\n\tstatus = (eal_initialized) ?\n\t\tcpu_core_map_compute_eal(map) :\n\t\tcpu_core_map_compute_linux(map);\n\n\tif (status) {\n\t\tfree(map);\n\t\treturn NULL;\n\t}\n\n\tstatus = cpu_core_map_compute_and_check(map);\n\tif (status) {\n\t\tfree(map);\n\t\treturn NULL;\n\t}\n\n\treturn map;\n}\n\nint\ncpu_core_map_compute_eal(struct cpu_core_map *map)\n{\n\tuint32_t socket_id, core_id, ht_id;\n\n\t/* Compute map */\n\tfor (socket_id = 0; socket_id < map->n_max_sockets; socket_id++) {\n\t\tuint32_t n_detected, core_id_contig;\n\t\tint lcore_id;\n\n\t\tn_detected = 0;\n\t\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\t\tstruct lcore_config *p = &lcore_config[lcore_id];\n\n\t\t\tif ((p->detected) && (p->socket_id == socket_id))\n\t\t\t\tn_detected++;\n\t\t}\n\n\t\tcore_id_contig = 0;\n\n\t\tfor (core_id = 0; n_detected ; core_id++) {\n\t\t\tht_id = 0;\n\n\t\t\tfor (lcore_id = 0;\n\t\t\t\tlcore_id < RTE_MAX_LCORE;\n\t\t\t\tlcore_id++) {\n\t\t\t\tstruct lcore_config *p =\n\t\t\t\t\t&lcore_config[lcore_id];\n\n\t\t\t\tif ((p->detected) &&\n\t\t\t\t\t(p->socket_id == socket_id) &&\n\t\t\t\t\t(p->core_id == core_id)) {\n\t\t\t\t\tuint32_t pos = cpu_core_map_pos(map,\n\t\t\t\t\t\tsocket_id,\n\t\t\t\t\t\tcore_id_contig,\n\t\t\t\t\t\tht_id);\n\n\t\t\t\t\tmap->map[pos] = lcore_id;\n\t\t\t\t\tht_id++;\n\t\t\t\t\tn_detected--;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (ht_id) {\n\t\t\t\tcore_id_contig++;\n\t\t\t\tif (core_id_contig ==\n\t\t\t\t\tmap->n_max_cores_per_socket)\n\t\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nint\ncpu_core_map_compute_and_check(struct cpu_core_map *map)\n{\n\tuint32_t socket_id, core_id, ht_id;\n\n\t/* Compute n_ht_per_core, n_cores_per_socket, n_sockets */\n\tfor (ht_id = 0; ht_id < map->n_max_ht_per_core; ht_id++) {\n\t\tif (map->map[ht_id] == -1)\n\t\t\tbreak;\n\n\t\tmap->n_ht_per_core++;\n\t}\n\n\tif (map->n_ht_per_core == 0)\n\t\treturn -1;\n\n\tfor (core_id = 0; core_id < map->n_max_cores_per_socket; core_id++) {\n\t\tuint32_t pos = core_id * map->n_max_ht_per_core;\n\n\t\tif (map->map[pos] == -1)\n\t\t\tbreak;\n\n\t\tmap->n_cores_per_socket++;\n\t}\n\n\tif (map->n_cores_per_socket == 0)\n\t\treturn -1;\n\n\tfor (socket_id = 0; socket_id < map->n_max_sockets; socket_id++) {\n\t\tuint32_t pos = socket_id * map->n_max_cores_per_socket *\n\t\t\tmap->n_max_ht_per_core;\n\n\t\tif (map->map[pos] == -1)\n\t\t\tbreak;\n\n\t\tmap->n_sockets++;\n\t}\n\n\tif (map->n_sockets == 0)\n\t\treturn -1;\n\n\t/* Check that each socket has exactly the same number of cores\n\tand that each core has exactly the same number of hyper-threads */\n\tfor (socket_id = 0; socket_id < map->n_sockets; socket_id++) {\n\t\tfor (core_id = 0; core_id < map->n_cores_per_socket; core_id++)\n\t\t\tfor (ht_id = 0;\n\t\t\t\tht_id < map->n_max_ht_per_core;\n\t\t\t\tht_id++) {\n\t\t\t\tuint32_t pos = (socket_id *\n\t\t\t\t\tmap->n_max_cores_per_socket + core_id) *\n\t\t\t\t\tmap->n_max_ht_per_core + ht_id;\n\n\t\t\t\tif (((ht_id < map->n_ht_per_core) &&\n\t\t\t\t\t(map->map[pos] == -1)) ||\n\t\t\t\t\t((ht_id >= map->n_ht_per_core) &&\n\t\t\t\t\t(map->map[pos] != -1)))\n\t\t\t\t\treturn -1;\n\t\t\t}\n\n\t\tfor ( ; core_id < map->n_max_cores_per_socket; core_id++)\n\t\t\tfor (ht_id = 0;\n\t\t\t\tht_id < map->n_max_ht_per_core;\n\t\t\t\tht_id++) {\n\t\t\t\tuint32_t pos = cpu_core_map_pos(map,\n\t\t\t\t\tsocket_id,\n\t\t\t\t\tcore_id,\n\t\t\t\t\tht_id);\n\n\t\t\t\tif (map->map[pos] != -1)\n\t\t\t\t\treturn -1;\n\t\t\t}\n\t}\n\n\treturn 0;\n}\n\n#define FILE_LINUX_CPU_N_LCORES \\\n\t\"/sys/devices/system/cpu/present\"\n\nstatic int\ncpu_core_map_get_n_lcores_linux(void)\n{\n\tchar buffer[64], *string;\n\tFILE *fd;\n\n\tfd = fopen(FILE_LINUX_CPU_N_LCORES, \"r\");\n\tif (fd == NULL)\n\t\treturn -1;\n\n\tif (fgets(buffer, sizeof(buffer), fd) == NULL) {\n\t\tfclose(fd);\n\t\treturn -1;\n\t}\n\n\tfclose(fd);\n\n\tstring = index(buffer, '-');\n\tif (string == NULL)\n\t\treturn -1;\n\n\treturn (atoi(++string) + 1);\n}\n\n#define FILE_LINUX_CPU_CORE_ID \\\n\t\"/sys/devices/system/cpu/cpu%\" PRIu32 \"/topology/core_id\"\n\nstatic int\ncpu_core_map_get_core_id_linux(int lcore_id)\n{\n\tchar buffer[64];\n\tFILE *fd;\n\tint core_id;\n\n\tsnprintf(buffer, sizeof(buffer), FILE_LINUX_CPU_CORE_ID, lcore_id);\n\tfd = fopen(buffer, \"r\");\n\tif (fd == NULL)\n\t\treturn -1;\n\n\tif (fgets(buffer, sizeof(buffer), fd) == NULL) {\n\t\tfclose(fd);\n\t\treturn -1;\n\t}\n\n\tfclose(fd);\n\n\tcore_id = atoi(buffer);\n\treturn core_id;\n}\n\n#define FILE_LINUX_CPU_SOCKET_ID \\\n\t\"/sys/devices/system/cpu/cpu%\" PRIu32 \"/topology/physical_package_id\"\n\nstatic int\ncpu_core_map_get_socket_id_linux(int lcore_id)\n{\n\tchar buffer[64];\n\tFILE *fd;\n\tint socket_id;\n\n\tsnprintf(buffer, sizeof(buffer), FILE_LINUX_CPU_SOCKET_ID, lcore_id);\n\tfd = fopen(buffer, \"r\");\n\tif (fd == NULL)\n\t\treturn -1;\n\n\tif (fgets(buffer, sizeof(buffer), fd) == NULL) {\n\t\tfclose(fd);\n\t\treturn -1;\n\t}\n\n\tfclose(fd);\n\n\tsocket_id = atoi(buffer);\n\treturn socket_id;\n}\n\nint\ncpu_core_map_compute_linux(struct cpu_core_map *map)\n{\n\tuint32_t socket_id, core_id, ht_id;\n\tint n_lcores;\n\n\tn_lcores = cpu_core_map_get_n_lcores_linux();\n\tif (n_lcores <= 0)\n\t\treturn -1;\n\n\t/* Compute map */\n\tfor (socket_id = 0; socket_id < map->n_max_sockets; socket_id++) {\n\t\tuint32_t n_detected, core_id_contig;\n\t\tint lcore_id;\n\n\t\tn_detected = 0;\n\t\tfor (lcore_id = 0; lcore_id < n_lcores; lcore_id++) {\n\t\t\tint lcore_socket_id =\n\t\t\t\tcpu_core_map_get_socket_id_linux(lcore_id);\n\n\t\t\tif (lcore_socket_id < 0)\n\t\t\t\treturn -1;\n\n\t\t\tif (((uint32_t) lcore_socket_id) == socket_id)\n\t\t\t\tn_detected++;\n\t\t}\n\n\t\tcore_id_contig = 0;\n\n\t\tfor (core_id = 0; n_detected ; core_id++) {\n\t\t\tht_id = 0;\n\n\t\t\tfor (lcore_id = 0; lcore_id < n_lcores; lcore_id++) {\n\t\t\t\tint lcore_socket_id =\n\t\t\t\t\tcpu_core_map_get_socket_id_linux(\n\t\t\t\t\tlcore_id);\n\n\t\t\t\tif (lcore_socket_id < 0)\n\t\t\t\t\treturn -1;\n\n\t\t\t\tint lcore_core_id =\n\t\t\t\t\tcpu_core_map_get_core_id_linux(\n\t\t\t\t\t\tlcore_id);\n\n\t\t\t\tif (lcore_core_id < 0)\n\t\t\t\t\treturn -1;\n\n\t\t\t\tif (((uint32_t) lcore_socket_id == socket_id) &&\n\t\t\t\t\t((uint32_t) lcore_core_id == core_id)) {\n\t\t\t\t\tuint32_t pos = cpu_core_map_pos(map,\n\t\t\t\t\t\tsocket_id,\n\t\t\t\t\t\tcore_id_contig,\n\t\t\t\t\t\tht_id);\n\n\t\t\t\t\tmap->map[pos] = lcore_id;\n\t\t\t\t\tht_id++;\n\t\t\t\t\tn_detected--;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (ht_id) {\n\t\t\t\tcore_id_contig++;\n\t\t\t\tif (core_id_contig ==\n\t\t\t\t\tmap->n_max_cores_per_socket)\n\t\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nvoid\ncpu_core_map_print(struct cpu_core_map *map)\n{\n\tuint32_t socket_id, core_id, ht_id;\n\n\tif (map == NULL)\n\t\treturn;\n\n\tfor (socket_id = 0; socket_id < map->n_sockets; socket_id++) {\n\t\tprintf(\"Socket %\" PRIu32 \":\\n\", socket_id);\n\n\t\tfor (core_id = 0;\n\t\t\tcore_id < map->n_cores_per_socket;\n\t\t\tcore_id++) {\n\t\t\tprintf(\"[%\" PRIu32 \"] = [\", core_id);\n\n\t\t\tfor (ht_id = 0; ht_id < map->n_ht_per_core; ht_id++) {\n\t\t\t\tint lcore_id = cpu_core_map_get_lcore_id(map,\n\t\t\t\t\tsocket_id,\n\t\t\t\t\tcore_id,\n\t\t\t\t\tht_id);\n\n\t\t\t\tuint32_t core_id_noncontig =\n\t\t\t\t\tcpu_core_map_get_core_id_linux(\n\t\t\t\t\t\tlcore_id);\n\n\t\t\t\tprintf(\" %\" PRId32 \" (%\" PRIu32 \") \",\n\t\t\t\t\tlcore_id,\n\t\t\t\t\tcore_id_noncontig);\n\t\t\t}\n\n\t\t\tprintf(\"]\\n\");\n\t\t}\n\t}\n}\n\nuint32_t\ncpu_core_map_get_n_sockets(struct cpu_core_map *map)\n{\n\tif (map == NULL)\n\t\treturn 0;\n\n\treturn map->n_sockets;\n}\n\nuint32_t\ncpu_core_map_get_n_cores_per_socket(struct cpu_core_map *map)\n{\n\tif (map == NULL)\n\t\treturn 0;\n\n\treturn map->n_cores_per_socket;\n}\n\nuint32_t\ncpu_core_map_get_n_ht_per_core(struct cpu_core_map *map)\n{\n\tif (map == NULL)\n\t\treturn 0;\n\n\treturn map->n_ht_per_core;\n}\n\nint\ncpu_core_map_get_lcore_id(struct cpu_core_map *map,\n\tuint32_t socket_id,\n\tuint32_t core_id,\n\tuint32_t ht_id)\n{\n\tuint32_t pos;\n\n\tif ((map == NULL) ||\n\t\t(socket_id >= map->n_sockets) ||\n\t\t(core_id >= map->n_cores_per_socket) ||\n\t\t(ht_id >= map->n_ht_per_core))\n\t\treturn -1;\n\n\tpos = cpu_core_map_pos(map, socket_id, core_id, ht_id);\n\n\treturn map->map[pos];\n}\n\nvoid\ncpu_core_map_free(struct cpu_core_map *map)\n{\n\tif (map)\n\t\tfree(map);\n}\n" }, { "path": "examples/ip_pipeline/cpu_core_map.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_CPU_CORE_MAP_H__\n#define __INCLUDE_CPU_CORE_MAP_H__\n\n#include \n\n#include \n\nstruct cpu_core_map;\n\nstruct cpu_core_map *\ncpu_core_map_init(uint32_t n_max_sockets,\n\tuint32_t n_max_cores_per_socket,\n\tuint32_t n_max_ht_per_core,\n\tuint32_t eal_initialized);\n\nuint32_t\ncpu_core_map_get_n_sockets(struct cpu_core_map *map);\n\nuint32_t\ncpu_core_map_get_n_cores_per_socket(struct cpu_core_map *map);\n\nuint32_t\ncpu_core_map_get_n_ht_per_core(struct cpu_core_map *map);\n\nint\ncpu_core_map_get_lcore_id(struct cpu_core_map *map,\n\tuint32_t socket_id,\n\tuint32_t core_id,\n\tuint32_t ht_id);\n\nvoid cpu_core_map_print(struct cpu_core_map *map);\n\nvoid\ncpu_core_map_free(struct cpu_core_map *map);\n\n#endif\n" }, { "path": "examples/ip_pipeline/init.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"app.h\"\n#include \"pipeline.h\"\n#include \"pipeline_common_fe.h\"\n#include \"pipeline_master.h\"\n#include \"pipeline_passthrough.h\"\n#include \"pipeline_firewall.h\"\n#include \"pipeline_flow_classification.h\"\n#include \"pipeline_routing.h\"\n\n#define APP_NAME_SIZE\t32\n\nstatic void\napp_init_core_map(struct app_params *app)\n{\n\tAPP_LOG(app, HIGH, \"Initializing CPU core map ...\");\n\tapp->core_map = cpu_core_map_init(4, 32, 4, 0);\n\n\tif (app->core_map == NULL)\n\t\trte_panic(\"Cannot create CPU core map\\n\");\n\n\tif (app->log_level >= APP_LOG_LEVEL_LOW)\n\t\tcpu_core_map_print(app->core_map);\n}\n\nstatic void\napp_init_core_mask(struct app_params *app)\n{\n\tuint64_t mask = 0;\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_pipelines; i++) {\n\t\tstruct app_pipeline_params *p = &app->pipeline_params[i];\n\t\tint lcore_id;\n\n\t\tlcore_id = cpu_core_map_get_lcore_id(app->core_map,\n\t\t\tp->socket_id,\n\t\t\tp->core_id,\n\t\t\tp->hyper_th_id);\n\n\t\tif (lcore_id < 0)\n\t\t\trte_panic(\"Cannot create CPU core mask\\n\");\n\n\t\tmask |= 1LLU << lcore_id;\n\t}\n\n\tapp->core_mask = mask;\n\tAPP_LOG(app, HIGH, \"CPU core mask = 0x%016\" PRIx64, app->core_mask);\n}\n\nstatic void\napp_init_eal(struct app_params *app)\n{\n\tchar buffer[32];\n\tstruct app_eal_params *p = &app->eal_params;\n\tuint32_t n_args = 0;\n\tint status;\n\n\tapp->eal_argv[n_args++] = strdup(app->app_name);\n\n\tsnprintf(buffer, sizeof(buffer), \"-c%\" PRIx64, app->core_mask);\n\tapp->eal_argv[n_args++] = strdup(buffer);\n\n\tif (p->coremap) {\n\t\tsnprintf(buffer, sizeof(buffer), \"--lcores=%s\", p->coremap);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->master_lcore_present) {\n\t\tsnprintf(buffer,\n\t\t\tsizeof(buffer),\n\t\t\t\"--master-lcore=%\" PRIu32,\n\t\t\tp->master_lcore);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tsnprintf(buffer, sizeof(buffer), \"-n%\" PRIu32, p->channels);\n\tapp->eal_argv[n_args++] = strdup(buffer);\n\n\tif (p->memory_present) {\n\t\tsnprintf(buffer, sizeof(buffer), \"-m%\" PRIu32, p->memory);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->ranks_present) {\n\t\tsnprintf(buffer, sizeof(buffer), \"-r%\" PRIu32, p->ranks);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->pci_blacklist) {\n\t\tsnprintf(buffer,\n\t\t\tsizeof(buffer),\n\t\t\t\"--pci-blacklist=%s\",\n\t\t\tp->pci_blacklist);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->pci_whitelist) {\n\t\tsnprintf(buffer,\n\t\t\tsizeof(buffer),\n\t\t\t\"--pci-whitelist=%s\",\n\t\t\tp->pci_whitelist);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->vdev) {\n\t\tsnprintf(buffer, sizeof(buffer), \"--vdev=%s\", p->vdev);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif ((p->vmware_tsc_map_present) && p->vmware_tsc_map) {\n\t\tsnprintf(buffer, sizeof(buffer), \"--vmware-tsc-map\");\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->proc_type) {\n\t\tsnprintf(buffer,\n\t\t\tsizeof(buffer),\n\t\t\t\"--proc-type=%s\",\n\t\t\tp->proc_type);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->syslog) {\n\t\tsnprintf(buffer, sizeof(buffer), \"--syslog=%s\", p->syslog);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->log_level_present) {\n\t\tsnprintf(buffer,\n\t\t\tsizeof(buffer),\n\t\t\t\"--log-level=%\" PRIu32,\n\t\t\tp->log_level);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif ((p->version_present) && p->version) {\n\t\tsnprintf(buffer, sizeof(buffer), \"-v\");\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif ((p->help_present) && p->help) {\n\t\tsnprintf(buffer, sizeof(buffer), \"--help\");\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif ((p->no_huge_present) && p->no_huge) {\n\t\tsnprintf(buffer, sizeof(buffer), \"--no-huge\");\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif ((p->no_pci_present) && p->no_pci) {\n\t\tsnprintf(buffer, sizeof(buffer), \"--no-pci\");\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif ((p->no_hpet_present) && p->no_hpet) {\n\t\tsnprintf(buffer, sizeof(buffer), \"--no-hpet\");\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif ((p->no_shconf_present) && p->no_shconf) {\n\t\tsnprintf(buffer, sizeof(buffer), \"--no-shconf\");\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->add_driver) {\n\t\tsnprintf(buffer, sizeof(buffer), \"-d=%s\", p->add_driver);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->socket_mem) {\n\t\tsnprintf(buffer,\n\t\t\tsizeof(buffer),\n\t\t\t\"--socket-mem=%s\",\n\t\t\tp->socket_mem);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->huge_dir) {\n\t\tsnprintf(buffer, sizeof(buffer), \"--huge-dir=%s\", p->huge_dir);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->file_prefix) {\n\t\tsnprintf(buffer,\n\t\t\tsizeof(buffer),\n\t\t\t\"--file-prefix=%s\",\n\t\t\tp->file_prefix);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->base_virtaddr) {\n\t\tsnprintf(buffer,\n\t\t\tsizeof(buffer),\n\t\t\t\"--base-virtaddr=%s\",\n\t\t\tp->base_virtaddr);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif ((p->create_uio_dev_present) && p->create_uio_dev) {\n\t\tsnprintf(buffer, sizeof(buffer), \"--create-uio-dev\");\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif (p->vfio_intr) {\n\t\tsnprintf(buffer,\n\t\t\tsizeof(buffer),\n\t\t\t\"--vfio-intr=%s\",\n\t\t\tp->vfio_intr);\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tif ((p->xen_dom0_present) && (p->xen_dom0)) {\n\t\tsnprintf(buffer, sizeof(buffer), \"--xen-dom0\");\n\t\tapp->eal_argv[n_args++] = strdup(buffer);\n\t}\n\n\tsnprintf(buffer, sizeof(buffer), \"--\");\n\tapp->eal_argv[n_args++] = strdup(buffer);\n\n\tapp->eal_argc = n_args;\n\n\tAPP_LOG(app, HIGH, \"Initializing EAL ...\");\n\tstatus = rte_eal_init(app->eal_argc, app->eal_argv);\n\tif (status < 0)\n\t\trte_panic(\"EAL init error\\n\");\n}\n\nstatic void\napp_init_mempool(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_mempools; i++) {\n\t\tstruct app_mempool_params *p = &app->mempool_params[i];\n\n\t\tAPP_LOG(app, HIGH, \"Initializing %s ...\", p->name);\n\t\tapp->mempool[i] = rte_mempool_create(\n\t\t\t\tp->name,\n\t\t\t\tp->pool_size,\n\t\t\t\tp->buffer_size,\n\t\t\t\tp->cache_size,\n\t\t\t\tsizeof(struct rte_pktmbuf_pool_private),\n\t\t\t\trte_pktmbuf_pool_init, NULL,\n\t\t\t\trte_pktmbuf_init, NULL,\n\t\t\t\tp->cpu_socket_id,\n\t\t\t\t0);\n\n\t\tif (app->mempool[i] == NULL)\n\t\t\trte_panic(\"%s init error\\n\", p->name);\n\t}\n}\n\nstatic inline int\napp_link_filter_arp_add(struct app_link_params *link)\n{\n\tstruct rte_eth_ethertype_filter filter = {\n\t\t.ether_type = ETHER_TYPE_ARP,\n\t\t.flags = 0,\n\t\t.queue = link->arp_q,\n\t};\n\n\treturn rte_eth_dev_filter_ctrl(link->pmd_id,\n\t\tRTE_ETH_FILTER_ETHERTYPE,\n\t\tRTE_ETH_FILTER_ADD,\n\t\t&filter);\n}\n\nstatic inline int\napp_link_filter_tcp_syn_add(struct app_link_params *link)\n{\n\tstruct rte_eth_syn_filter filter = {\n\t\t.hig_pri = 1,\n\t\t.queue = link->tcp_syn_local_q,\n\t};\n\n\treturn rte_eth_dev_filter_ctrl(link->pmd_id,\n\t\tRTE_ETH_FILTER_SYN,\n\t\tRTE_ETH_FILTER_ADD,\n\t\t&filter);\n}\n\nstatic inline int\napp_link_filter_ip_add(struct app_link_params *l1, struct app_link_params *l2)\n{\n\tstruct rte_eth_ntuple_filter filter = {\n\t\t.flags = RTE_5TUPLE_FLAGS,\n\t\t.dst_ip = rte_bswap32(l2->ip),\n\t\t.dst_ip_mask = UINT32_MAX, /* Enable */\n\t\t.src_ip = 0,\n\t\t.src_ip_mask = 0, /* Disable */\n\t\t.dst_port = 0,\n\t\t.dst_port_mask = 0, /* Disable */\n\t\t.src_port = 0,\n\t\t.src_port_mask = 0, /* Disable */\n\t\t.proto = 0,\n\t\t.proto_mask = 0, /* Disable */\n\t\t.tcp_flags = 0,\n\t\t.priority = 1, /* Lowest */\n\t\t.queue = l1->ip_local_q,\n\t};\n\n\treturn rte_eth_dev_filter_ctrl(l1->pmd_id,\n\t\tRTE_ETH_FILTER_NTUPLE,\n\t\tRTE_ETH_FILTER_ADD,\n\t\t&filter);\n}\n\nstatic inline int\napp_link_filter_ip_del(struct app_link_params *l1, struct app_link_params *l2)\n{\n\tstruct rte_eth_ntuple_filter filter = {\n\t\t.flags = RTE_5TUPLE_FLAGS,\n\t\t.dst_ip = rte_bswap32(l2->ip),\n\t\t.dst_ip_mask = UINT32_MAX, /* Enable */\n\t\t.src_ip = 0,\n\t\t.src_ip_mask = 0, /* Disable */\n\t\t.dst_port = 0,\n\t\t.dst_port_mask = 0, /* Disable */\n\t\t.src_port = 0,\n\t\t.src_port_mask = 0, /* Disable */\n\t\t.proto = 0,\n\t\t.proto_mask = 0, /* Disable */\n\t\t.tcp_flags = 0,\n\t\t.priority = 1, /* Lowest */\n\t\t.queue = l1->ip_local_q,\n\t};\n\n\treturn rte_eth_dev_filter_ctrl(l1->pmd_id,\n\t\tRTE_ETH_FILTER_NTUPLE,\n\t\tRTE_ETH_FILTER_DELETE,\n\t\t&filter);\n}\n\nstatic inline int\napp_link_filter_tcp_add(struct app_link_params *l1, struct app_link_params *l2)\n{\n\tstruct rte_eth_ntuple_filter filter = {\n\t\t.flags = RTE_5TUPLE_FLAGS,\n\t\t.dst_ip = rte_bswap32(l2->ip),\n\t\t.dst_ip_mask = UINT32_MAX, /* Enable */\n\t\t.src_ip = 0,\n\t\t.src_ip_mask = 0, /* Disable */\n\t\t.dst_port = 0,\n\t\t.dst_port_mask = 0, /* Disable */\n\t\t.src_port = 0,\n\t\t.src_port_mask = 0, /* Disable */\n\t\t.proto = IPPROTO_TCP,\n\t\t.proto_mask = UINT8_MAX, /* Enable */\n\t\t.tcp_flags = 0,\n\t\t.priority = 2, /* Higher priority than IP */\n\t\t.queue = l1->tcp_local_q,\n\t};\n\n\treturn rte_eth_dev_filter_ctrl(l1->pmd_id,\n\t\tRTE_ETH_FILTER_NTUPLE,\n\t\tRTE_ETH_FILTER_ADD,\n\t\t&filter);\n}\n\nstatic inline int\napp_link_filter_tcp_del(struct app_link_params *l1, struct app_link_params *l2)\n{\n\tstruct rte_eth_ntuple_filter filter = {\n\t\t.flags = RTE_5TUPLE_FLAGS,\n\t\t.dst_ip = rte_bswap32(l2->ip),\n\t\t.dst_ip_mask = UINT32_MAX, /* Enable */\n\t\t.src_ip = 0,\n\t\t.src_ip_mask = 0, /* Disable */\n\t\t.dst_port = 0,\n\t\t.dst_port_mask = 0, /* Disable */\n\t\t.src_port = 0,\n\t\t.src_port_mask = 0, /* Disable */\n\t\t.proto = IPPROTO_TCP,\n\t\t.proto_mask = UINT8_MAX, /* Enable */\n\t\t.tcp_flags = 0,\n\t\t.priority = 2, /* Higher priority than IP */\n\t\t.queue = l1->tcp_local_q,\n\t};\n\n\treturn rte_eth_dev_filter_ctrl(l1->pmd_id,\n\t\tRTE_ETH_FILTER_NTUPLE,\n\t\tRTE_ETH_FILTER_DELETE,\n\t\t&filter);\n}\n\nstatic inline int\napp_link_filter_udp_add(struct app_link_params *l1, struct app_link_params *l2)\n{\n\tstruct rte_eth_ntuple_filter filter = {\n\t\t.flags = RTE_5TUPLE_FLAGS,\n\t\t.dst_ip = rte_bswap32(l2->ip),\n\t\t.dst_ip_mask = UINT32_MAX, /* Enable */\n\t\t.src_ip = 0,\n\t\t.src_ip_mask = 0, /* Disable */\n\t\t.dst_port = 0,\n\t\t.dst_port_mask = 0, /* Disable */\n\t\t.src_port = 0,\n\t\t.src_port_mask = 0, /* Disable */\n\t\t.proto = IPPROTO_UDP,\n\t\t.proto_mask = UINT8_MAX, /* Enable */\n\t\t.tcp_flags = 0,\n\t\t.priority = 2, /* Higher priority than IP */\n\t\t.queue = l1->udp_local_q,\n\t};\n\n\treturn rte_eth_dev_filter_ctrl(l1->pmd_id,\n\t\tRTE_ETH_FILTER_NTUPLE,\n\t\tRTE_ETH_FILTER_ADD,\n\t\t&filter);\n}\n\nstatic inline int\napp_link_filter_udp_del(struct app_link_params *l1, struct app_link_params *l2)\n{\n\tstruct rte_eth_ntuple_filter filter = {\n\t\t.flags = RTE_5TUPLE_FLAGS,\n\t\t.dst_ip = rte_bswap32(l2->ip),\n\t\t.dst_ip_mask = UINT32_MAX, /* Enable */\n\t\t.src_ip = 0,\n\t\t.src_ip_mask = 0, /* Disable */\n\t\t.dst_port = 0,\n\t\t.dst_port_mask = 0, /* Disable */\n\t\t.src_port = 0,\n\t\t.src_port_mask = 0, /* Disable */\n\t\t.proto = IPPROTO_UDP,\n\t\t.proto_mask = UINT8_MAX, /* Enable */\n\t\t.tcp_flags = 0,\n\t\t.priority = 2, /* Higher priority than IP */\n\t\t.queue = l1->udp_local_q,\n\t};\n\n\treturn rte_eth_dev_filter_ctrl(l1->pmd_id,\n\t\tRTE_ETH_FILTER_NTUPLE,\n\t\tRTE_ETH_FILTER_DELETE,\n\t\t&filter);\n}\n\nstatic inline int\napp_link_filter_sctp_add(struct app_link_params *l1, struct app_link_params *l2)\n{\n\tstruct rte_eth_ntuple_filter filter = {\n\t\t.flags = RTE_5TUPLE_FLAGS,\n\t\t.dst_ip = rte_bswap32(l2->ip),\n\t\t.dst_ip_mask = UINT32_MAX, /* Enable */\n\t\t.src_ip = 0,\n\t\t.src_ip_mask = 0, /* Disable */\n\t\t.dst_port = 0,\n\t\t.dst_port_mask = 0, /* Disable */\n\t\t.src_port = 0,\n\t\t.src_port_mask = 0, /* Disable */\n\t\t.proto = IPPROTO_SCTP,\n\t\t.proto_mask = UINT8_MAX, /* Enable */\n\t\t.tcp_flags = 0,\n\t\t.priority = 2, /* Higher priority than IP */\n\t\t.queue = l1->sctp_local_q,\n\t};\n\n\treturn rte_eth_dev_filter_ctrl(l1->pmd_id,\n\t\tRTE_ETH_FILTER_NTUPLE,\n\t\tRTE_ETH_FILTER_ADD,\n\t\t&filter);\n}\n\nstatic inline int\napp_link_filter_sctp_del(struct app_link_params *l1, struct app_link_params *l2)\n{\n\tstruct rte_eth_ntuple_filter filter = {\n\t\t.flags = RTE_5TUPLE_FLAGS,\n\t\t.dst_ip = rte_bswap32(l2->ip),\n\t\t.dst_ip_mask = UINT32_MAX, /* Enable */\n\t\t.src_ip = 0,\n\t\t.src_ip_mask = 0, /* Disable */\n\t\t.dst_port = 0,\n\t\t.dst_port_mask = 0, /* Disable */\n\t\t.src_port = 0,\n\t\t.src_port_mask = 0, /* Disable */\n\t\t.proto = IPPROTO_SCTP,\n\t\t.proto_mask = UINT8_MAX, /* Enable */\n\t\t.tcp_flags = 0,\n\t\t.priority = 2, /* Higher priority than IP */\n\t\t.queue = l1->sctp_local_q,\n\t};\n\n\treturn rte_eth_dev_filter_ctrl(l1->pmd_id,\n\t\tRTE_ETH_FILTER_NTUPLE,\n\t\tRTE_ETH_FILTER_DELETE,\n\t\t&filter);\n}\n\nstatic void\napp_link_set_arp_filter(struct app_params *app, struct app_link_params *cp)\n{\n\tif (cp->arp_q != 0) {\n\t\tint status = app_link_filter_arp_add(cp);\n\n\t\tAPP_LOG(app, LOW, \"%s (%\" PRIu32 \"): \"\n\t\t\t\"Adding ARP filter (queue = %\" PRIu32 \")\",\n\t\t\tcp->name, cp->pmd_id, cp->arp_q);\n\n\t\tif (status)\n\t\t\trte_panic(\"%s (%\" PRIu32 \"): \"\n\t\t\t\t\"Error adding ARP filter \"\n\t\t\t\t\"(queue = %\" PRIu32 \") (%\" PRId32 \")\\n\",\n\t\t\t\tcp->name, cp->pmd_id, cp->arp_q, status);\n\t}\n}\n\nstatic void\napp_link_set_tcp_syn_filter(struct app_params *app, struct app_link_params *cp)\n{\n\tif (cp->tcp_syn_local_q != 0) {\n\t\tint status = app_link_filter_tcp_syn_add(cp);\n\n\t\tAPP_LOG(app, LOW, \"%s (%\" PRIu32 \"): \"\n\t\t\t\"Adding TCP SYN filter (queue = %\" PRIu32 \")\",\n\t\t\tcp->name, cp->pmd_id, cp->tcp_syn_local_q);\n\n\t\tif (status)\n\t\t\trte_panic(\"%s (%\" PRIu32 \"): \"\n\t\t\t\t\"Error adding TCP SYN filter \"\n\t\t\t\t\"(queue = %\" PRIu32 \") (%\" PRId32 \")\\n\",\n\t\t\t\tcp->name, cp->pmd_id, cp->tcp_syn_local_q,\n\t\t\t\tstatus);\n\t}\n}\n\nvoid\napp_link_up_internal(struct app_params *app, struct app_link_params *cp)\n{\n\tuint32_t i;\n\tint status;\n\n\t/* For each link, add filters for IP of current link */\n\tif (cp->ip != 0) {\n\t\tfor (i = 0; i < app->n_links; i++) {\n\t\t\tstruct app_link_params *p = &app->link_params[i];\n\n\t\t\t/* IP */\n\t\t\tif (p->ip_local_q != 0) {\n\t\t\t\tint status = app_link_filter_ip_add(p, cp);\n\n\t\t\t\tAPP_LOG(app, LOW, \"%s (%\" PRIu32 \"): \"\n\t\t\t\t\t\"Adding IP filter (queue= %\" PRIu32\n\t\t\t\t\t\", IP = 0x%08\" PRIx32 \")\",\n\t\t\t\t\tp->name, p->pmd_id, p->ip_local_q,\n\t\t\t\t\tcp->ip);\n\n\t\t\t\tif (status)\n\t\t\t\t\trte_panic(\"%s (%\" PRIu32 \"): \"\n\t\t\t\t\t\t\"Error adding IP \"\n\t\t\t\t\t\t\"filter (queue= %\" PRIu32 \", \"\n\t\t\t\t\t\t\"IP = 0x%08\" PRIx32\n\t\t\t\t\t\t\") (%\" PRId32 \")\\n\",\n\t\t\t\t\t\tp->name, p->pmd_id,\n\t\t\t\t\t\tp->ip_local_q, cp->ip, status);\n\t\t\t}\n\n\t\t\t/* TCP */\n\t\t\tif (p->tcp_local_q != 0) {\n\t\t\t\tint status = app_link_filter_tcp_add(p, cp);\n\n\t\t\t\tAPP_LOG(app, LOW, \"%s (%\" PRIu32 \"): \"\n\t\t\t\t\t\"Adding TCP filter \"\n\t\t\t\t\t\"(queue = %\" PRIu32\n\t\t\t\t\t\", IP = 0x%08\" PRIx32 \")\",\n\t\t\t\t\tp->name, p->pmd_id, p->tcp_local_q,\n\t\t\t\t\tcp->ip);\n\n\t\t\t\tif (status)\n\t\t\t\t\trte_panic(\"%s (%\" PRIu32 \"): \"\n\t\t\t\t\t\t\"Error adding TCP \"\n\t\t\t\t\t\t\"filter (queue = %\" PRIu32 \", \"\n\t\t\t\t\t\t\"IP = 0x%08\" PRIx32\n\t\t\t\t\t\t\") (%\" PRId32 \")\\n\",\n\t\t\t\t\t\tp->name, p->pmd_id,\n\t\t\t\t\t\tp->tcp_local_q, cp->ip, status);\n\t\t\t}\n\n\t\t\t/* UDP */\n\t\t\tif (p->udp_local_q != 0) {\n\t\t\t\tint status = app_link_filter_udp_add(p, cp);\n\n\t\t\t\tAPP_LOG(app, LOW, \"%s (%\" PRIu32 \"): \"\n\t\t\t\t\t\"Adding UDP filter \"\n\t\t\t\t\t\"(queue = %\" PRIu32\n\t\t\t\t\t\", IP = 0x%08\" PRIx32 \")\",\n\t\t\t\t\tp->name, p->pmd_id, p->udp_local_q,\n\t\t\t\t\tcp->ip);\n\n\t\t\t\tif (status)\n\t\t\t\t\trte_panic(\"%s (%\" PRIu32 \"): \"\n\t\t\t\t\t\t\"Error adding UDP \"\n\t\t\t\t\t\t\"filter (queue = %\" PRIu32 \", \"\n\t\t\t\t\t\t\"IP = 0x%08\" PRIx32\n\t\t\t\t\t\t\") (%\" PRId32 \")\\n\",\n\t\t\t\t\t\tp->name, p->pmd_id,\n\t\t\t\t\t\tp->udp_local_q, cp->ip, status);\n\t\t\t}\n\n\t\t\t/* SCTP */\n\t\t\tif (p->sctp_local_q != 0) {\n\t\t\t\tint status = app_link_filter_sctp_add(p, cp);\n\n\t\t\t\tAPP_LOG(app, LOW, \"%s (%\" PRIu32\n\t\t\t\t\t\"): Adding SCTP filter \"\n\t\t\t\t\t\"(queue = %\" PRIu32\n\t\t\t\t\t\", IP = 0x%08\" PRIx32 \")\",\n\t\t\t\t\tp->name, p->pmd_id, p->sctp_local_q,\n\t\t\t\t\tcp->ip);\n\n\t\t\t\tif (status)\n\t\t\t\t\trte_panic(\"%s (%\" PRIu32 \"): \"\n\t\t\t\t\t\t\"Error adding SCTP \"\n\t\t\t\t\t\t\"filter (queue = %\" PRIu32 \", \"\n\t\t\t\t\t\t\"IP = 0x%08\" PRIx32\n\t\t\t\t\t\t\") (%\" PRId32 \")\\n\",\n\t\t\t\t\t\tp->name, p->pmd_id,\n\t\t\t\t\t\tp->sctp_local_q, cp->ip,\n\t\t\t\t\t\tstatus);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* PMD link up */\n\tstatus = rte_eth_dev_set_link_up(cp->pmd_id);\n\tif (status < 0)\n\t\trte_panic(\"%s (%\" PRIu32 \"): PMD set up error %\" PRId32 \"\\n\",\n\t\t\tcp->name, cp->pmd_id, status);\n\n\t/* Mark link as UP */\n\tcp->state = 1;\n}\n\nvoid\napp_link_down_internal(struct app_params *app, struct app_link_params *cp)\n{\n\tuint32_t i;\n\n\t/* PMD link down */\n\trte_eth_dev_set_link_down(cp->pmd_id);\n\n\t/* Mark link as DOWN */\n\tcp->state = 0;\n\n\t/* Return if current link IP is not valid */\n\tif (cp->ip == 0)\n\t\treturn;\n\n\t/* For each link, remove filters for IP of current link */\n\tfor (i = 0; i < app->n_links; i++) {\n\t\tstruct app_link_params *p = &app->link_params[i];\n\n\t\t/* IP */\n\t\tif (p->ip_local_q != 0) {\n\t\t\tint status = app_link_filter_ip_del(p, cp);\n\n\t\t\tAPP_LOG(app, LOW, \"%s (%\" PRIu32\n\t\t\t\t\"): Deleting IP filter \"\n\t\t\t\t\"(queue = %\" PRIu32 \", IP = 0x%\" PRIx32 \")\",\n\t\t\t\tp->name, p->pmd_id, p->ip_local_q, cp->ip);\n\n\t\t\tif (status)\n\t\t\t\trte_panic(\"%s (%\" PRIu32\n\t\t\t\t\t\"): Error deleting IP filter \"\n\t\t\t\t\t\"(queue = %\" PRIu32\n\t\t\t\t\t\", IP = 0x%\" PRIx32\n\t\t\t\t\t\") (%\" PRId32 \")\\n\",\n\t\t\t\t\tp->name, p->pmd_id, p->ip_local_q,\n\t\t\t\t\tcp->ip, status);\n\t\t}\n\n\t\t/* TCP */\n\t\tif (p->tcp_local_q != 0) {\n\t\t\tint status = app_link_filter_tcp_del(p, cp);\n\n\t\t\tAPP_LOG(app, LOW, \"%s (%\" PRIu32\n\t\t\t\t\"): Deleting TCP filter \"\n\t\t\t\t\"(queue = %\" PRIu32\n\t\t\t\t\", IP = 0x%\" PRIx32 \")\",\n\t\t\t\tp->name, p->pmd_id, p->tcp_local_q, cp->ip);\n\n\t\t\tif (status)\n\t\t\t\trte_panic(\"%s (%\" PRIu32\n\t\t\t\t\t\"): Error deleting TCP filter \"\n\t\t\t\t\t\"(queue = %\" PRIu32\n\t\t\t\t\t\", IP = 0x%\" PRIx32\n\t\t\t\t\t\") (%\" PRId32 \")\\n\",\n\t\t\t\t\tp->name, p->pmd_id, p->tcp_local_q,\n\t\t\t\t\tcp->ip, status);\n\t\t}\n\n\t\t/* UDP */\n\t\tif (p->udp_local_q != 0) {\n\t\t\tint status = app_link_filter_udp_del(p, cp);\n\n\t\t\tAPP_LOG(app, LOW, \"%s (%\" PRIu32\n\t\t\t\t\"): Deleting UDP filter \"\n\t\t\t\t\"(queue = %\" PRIu32 \", IP = 0x%\" PRIx32 \")\",\n\t\t\t\tp->name, p->pmd_id, p->udp_local_q, cp->ip);\n\n\t\t\tif (status)\n\t\t\t\trte_panic(\"%s (%\" PRIu32\n\t\t\t\t\t\"): Error deleting UDP filter \"\n\t\t\t\t\t\"(queue = %\" PRIu32\n\t\t\t\t\t\", IP = 0x%\" PRIx32\n\t\t\t\t\t\") (%\" PRId32 \")\\n\",\n\t\t\t\t\tp->name, p->pmd_id, p->udp_local_q,\n\t\t\t\t\tcp->ip, status);\n\t\t}\n\n\t\t/* SCTP */\n\t\tif (p->sctp_local_q != 0) {\n\t\t\tint status = app_link_filter_sctp_del(p, cp);\n\n\t\t\tAPP_LOG(app, LOW, \"%s (%\" PRIu32\n\t\t\t\t\"): Deleting SCTP filter \"\n\t\t\t\t\"(queue = %\" PRIu32\n\t\t\t\t\", IP = 0x%\" PRIx32 \")\",\n\t\t\t\tp->name, p->pmd_id, p->sctp_local_q, cp->ip);\n\n\t\t\tif (status)\n\t\t\t\trte_panic(\"%s (%\" PRIu32\n\t\t\t\t\t\"): Error deleting SCTP filter \"\n\t\t\t\t\t\"(queue = %\" PRIu32\n\t\t\t\t\t\", IP = 0x%\" PRIx32\n\t\t\t\t\t\") (%\" PRId32 \")\\n\",\n\t\t\t\t\tp->name, p->pmd_id, p->sctp_local_q,\n\t\t\t\t\tcp->ip, status);\n\t\t}\n\t}\n}\n\nstatic void\napp_check_link(struct app_params *app)\n{\n\tuint32_t all_links_up, i;\n\n\tall_links_up = 1;\n\n\tfor (i = 0; i < app->n_links; i++) {\n\t\tstruct app_link_params *p = &app->link_params[i];\n\t\tstruct rte_eth_link link_params;\n\n\t\tmemset(&link_params, 0, sizeof(link_params));\n\t\trte_eth_link_get(p->pmd_id, &link_params);\n\n\t\tAPP_LOG(app, HIGH, \"%s (%\" PRIu32 \") (%\" PRIu32 \" Gbps) %s\",\n\t\t\tp->name,\n\t\t\tp->pmd_id,\n\t\t\tlink_params.link_speed / 1000,\n\t\t\tlink_params.link_status ? \"UP\" : \"DOWN\");\n\n\t\tif (link_params.link_status == 0)\n\t\t\tall_links_up = 0;\n\t}\n\n\tif (all_links_up == 0)\n\t\trte_panic(\"Some links are DOWN\\n\");\n}\n\nstatic void\napp_init_link(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_links; i++) {\n\t\tstruct app_link_params *p_link = &app->link_params[i];\n\t\tuint32_t link_id, n_hwq_in, n_hwq_out, j;\n\t\tint status;\n\n\t\tsscanf(p_link->name, \"LINK%\" PRIu32, &link_id);\n\t\tn_hwq_in = app_link_get_n_rxq(app, p_link);\n\t\tn_hwq_out = app_link_get_n_txq(app, p_link);\n\n\t\tAPP_LOG(app, HIGH, \"Initializing %s (%\" PRIu32\") \"\n\t\t\t\"(%\" PRIu32 \" RXQ, %\" PRIu32 \" TXQ) ...\",\n\t\t\tp_link->name,\n\t\t\tp_link->pmd_id,\n\t\t\tn_hwq_in,\n\t\t\tn_hwq_out);\n\n\t\t/* LINK */\n\t\tstatus = rte_eth_dev_configure(\n\t\t\tp_link->pmd_id,\n\t\t\tn_hwq_in,\n\t\t\tn_hwq_out,\n\t\t\t&p_link->conf);\n\t\tif (status < 0)\n\t\t\trte_panic(\"%s (%\" PRId32 \"): \"\n\t\t\t\t\"init error (%\" PRId32 \")\\n\",\n\t\t\t\tp_link->name, p_link->pmd_id, status);\n\n\t\trte_eth_macaddr_get(p_link->pmd_id,\n\t\t\t(struct ether_addr *) &p_link->mac_addr);\n\n\t\tif (p_link->promisc)\n\t\t\trte_eth_promiscuous_enable(p_link->pmd_id);\n\n\t\t/* RXQ */\n\t\tfor (j = 0; j < app->n_pktq_hwq_in; j++) {\n\t\t\tstruct app_pktq_hwq_in_params *p_rxq =\n\t\t\t\t&app->hwq_in_params[j];\n\t\t\tuint32_t rxq_link_id, rxq_queue_id;\n\n\t\t\tsscanf(p_rxq->name, \"RXQ%\" PRIu32 \".%\" PRIu32,\n\t\t\t\t&rxq_link_id, &rxq_queue_id);\n\t\t\tif (rxq_link_id != link_id)\n\t\t\t\tcontinue;\n\n\t\t\tstatus = rte_eth_rx_queue_setup(\n\t\t\t\tp_link->pmd_id,\n\t\t\t\trxq_queue_id,\n\t\t\t\tp_rxq->size,\n\t\t\t\trte_eth_dev_socket_id(p_link->pmd_id),\n\t\t\t\t&p_rxq->conf,\n\t\t\t\tapp->mempool[p_rxq->mempool_id]);\n\t\t\tif (status < 0)\n\t\t\t\trte_panic(\"%s (%\" PRIu32 \"): \"\n\t\t\t\t\t\"%s init error (%\" PRId32 \")\\n\",\n\t\t\t\t\tp_link->name,\n\t\t\t\t\tp_link->pmd_id,\n\t\t\t\t\tp_rxq->name,\n\t\t\t\t\tstatus);\n\t\t}\n\n\t\t/* TXQ */\n\t\tfor (j = 0; j < app->n_pktq_hwq_out; j++) {\n\t\t\tstruct app_pktq_hwq_out_params *p_txq =\n\t\t\t\t&app->hwq_out_params[j];\n\t\t\tuint32_t txq_link_id, txq_queue_id;\n\n\t\t\tsscanf(p_txq->name, \"TXQ%\" PRIu32 \".%\" PRIu32,\n\t\t\t\t&txq_link_id, &txq_queue_id);\n\t\t\tif (txq_link_id != link_id)\n\t\t\t\tcontinue;\n\n\t\t\tstatus = rte_eth_tx_queue_setup(\n\t\t\t\tp_link->pmd_id,\n\t\t\t\ttxq_queue_id,\n\t\t\t\tp_txq->size,\n\t\t\t\trte_eth_dev_socket_id(p_link->pmd_id),\n\t\t\t\t&p_txq->conf);\n\t\t\tif (status < 0)\n\t\t\t\trte_panic(\"%s (%\" PRIu32 \"): \"\n\t\t\t\t\t\"%s init error (%\" PRId32 \")\\n\",\n\t\t\t\t\tp_link->name,\n\t\t\t\t\tp_link->pmd_id,\n\t\t\t\t\tp_txq->name,\n\t\t\t\t\tstatus);\n\t\t}\n\n\t\t/* LINK START */\n\t\tstatus = rte_eth_dev_start(p_link->pmd_id);\n\t\tif (status < 0)\n\t\t\trte_panic(\"Cannot start %s (error %\" PRId32 \")\\n\",\n\t\t\t\tp_link->name, status);\n\n\t\t/* LINK UP */\n\t\tapp_link_set_arp_filter(app, p_link);\n\t\tapp_link_set_tcp_syn_filter(app, p_link);\n\t\tapp_link_up_internal(app, p_link);\n\t}\n\n\tapp_check_link(app);\n}\n\nstatic void\napp_init_swq(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_pktq_swq; i++) {\n\t\tstruct app_pktq_swq_params *p = &app->swq_params[i];\n\n\t\tAPP_LOG(app, HIGH, \"Initializing %s...\", p->name);\n\t\tapp->swq[i] = rte_ring_create(\n\t\t\t\tp->name,\n\t\t\t\tp->size,\n\t\t\t\tp->cpu_socket_id,\n\t\t\t\tRING_F_SP_ENQ | RING_F_SC_DEQ);\n\n\t\tif (app->swq[i] == NULL)\n\t\t\trte_panic(\"%s init error\\n\", p->name);\n\t}\n}\n\nstatic void\napp_init_tm(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_pktq_tm; i++) {\n\t\tstruct app_pktq_tm_params *p_tm = &app->tm_params[i];\n\t\tstruct app_link_params *p_link;\n\t\tstruct rte_eth_link link_eth_params;\n\t\tstruct rte_sched_port *sched;\n\t\tuint32_t n_subports, subport_id;\n\t\tint status;\n\n\t\tp_link = app_get_link_for_tm(app, p_tm);\n\t\t/* LINK */\n\t\trte_eth_link_get(p_link->pmd_id, &link_eth_params);\n\n\t\t/* TM */\n\t\tp_tm->sched_port_params.name = p_tm->name;\n\t\tp_tm->sched_port_params.socket =\n\t\t\trte_eth_dev_socket_id(p_link->pmd_id);\n\t\tp_tm->sched_port_params.rate =\n\t\t\t(uint64_t) link_eth_params.link_speed * 1000 * 1000 / 8;\n\n\t\tAPP_LOG(app, HIGH, \"Initializing %s ...\", p_tm->name);\n\t\tsched = rte_sched_port_config(&p_tm->sched_port_params);\n\t\tif (sched == NULL)\n\t\t\trte_panic(\"%s init error\\n\", p_tm->name);\n\t\tapp->tm[i] = sched;\n\n\t\t/* Subport */\n\t\tn_subports = p_tm->sched_port_params.n_subports_per_port;\n\t\tfor (subport_id = 0; subport_id < n_subports; subport_id++) {\n\t\t\tuint32_t n_pipes_per_subport, pipe_id;\n\n\t\t\tstatus = rte_sched_subport_config(sched,\n\t\t\t\tsubport_id,\n\t\t\t\t&p_tm->sched_subport_params[subport_id]);\n\t\t\tif (status)\n\t\t\t\trte_panic(\"%s subport %\" PRIu32\n\t\t\t\t\t\" init error (%\" PRId32 \")\\n\",\n\t\t\t\t\tp_tm->name, subport_id, status);\n\n\t\t\t/* Pipe */\n\t\t\tn_pipes_per_subport =\n\t\t\t\tp_tm->sched_port_params.n_pipes_per_subport;\n\t\t\tfor (pipe_id = 0;\n\t\t\t\tpipe_id < n_pipes_per_subport;\n\t\t\t\tpipe_id++) {\n\t\t\t\tint profile_id = p_tm->sched_pipe_to_profile[\n\t\t\t\t\tsubport_id * APP_MAX_SCHED_PIPES +\n\t\t\t\t\tpipe_id];\n\n\t\t\t\tif (profile_id == -1)\n\t\t\t\t\tcontinue;\n\n\t\t\t\tstatus = rte_sched_pipe_config(sched,\n\t\t\t\t\tsubport_id,\n\t\t\t\t\tpipe_id,\n\t\t\t\t\tprofile_id);\n\t\t\t\tif (status)\n\t\t\t\t\trte_panic(\"%s subport %\" PRIu32\n\t\t\t\t\t\t\" pipe %\" PRIu32\n\t\t\t\t\t\t\" (profile %\" PRId32 \") \"\n\t\t\t\t\t\t\"init error (% \" PRId32 \")\\n\",\n\t\t\t\t\t\tp_tm->name, subport_id, pipe_id,\n\t\t\t\t\t\tprofile_id, status);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void\napp_init_msgq(struct app_params *app)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_msgq; i++) {\n\t\tstruct app_msgq_params *p = &app->msgq_params[i];\n\n\t\tAPP_LOG(app, HIGH, \"Initializing %s ...\", p->name);\n\t\tapp->msgq[i] = rte_ring_create(\n\t\t\t\tp->name,\n\t\t\t\tp->size,\n\t\t\t\tp->cpu_socket_id,\n\t\t\t\tRING_F_SP_ENQ | RING_F_SC_DEQ);\n\n\t\tif (app->msgq[i] == NULL)\n\t\t\trte_panic(\"%s init error\\n\", p->name);\n\t}\n}\n\nstatic void app_pipeline_params_get(struct app_params *app,\n\tstruct app_pipeline_params *p_in,\n\tstruct pipeline_params *p_out)\n{\n\tuint32_t i;\n\n\tstrcpy(p_out->name, p_in->name);\n\n\tp_out->socket_id = (int) p_in->socket_id;\n\n\tp_out->log_level = app->log_level;\n\n\t/* pktq_in */\n\tp_out->n_ports_in = p_in->n_pktq_in;\n\tfor (i = 0; i < p_in->n_pktq_in; i++) {\n\t\tstruct app_pktq_in_params *in = &p_in->pktq_in[i];\n\t\tstruct pipeline_port_in_params *out = &p_out->port_in[i];\n\n\t\tswitch (in->type) {\n\t\tcase APP_PKTQ_IN_HWQ:\n\t\t{\n\t\t\tstruct app_pktq_hwq_in_params *p_hwq_in =\n\t\t\t\t&app->hwq_in_params[in->id];\n\t\t\tstruct app_link_params *p_link =\n\t\t\t\tapp_get_link_for_rxq(app, p_hwq_in);\n\t\t\tuint32_t rxq_link_id, rxq_queue_id;\n\n\t\t\tsscanf(p_hwq_in->name, \"RXQ%\" SCNu32 \".%\" SCNu32,\n\t\t\t\t&rxq_link_id,\n\t\t\t\t&rxq_queue_id);\n\n\t\t\tout->type = PIPELINE_PORT_IN_ETHDEV_READER;\n\t\t\tout->params.ethdev.port_id = p_link->pmd_id;\n\t\t\tout->params.ethdev.queue_id = rxq_queue_id;\n\t\t\tout->burst_size = p_hwq_in->burst;\n\t\t\tbreak;\n\t\t}\n\t\tcase APP_PKTQ_IN_SWQ:\n\t\t\tout->type = PIPELINE_PORT_IN_RING_READER;\n\t\t\tout->params.ring.ring = app->swq[in->id];\n\t\t\tout->burst_size = app->swq_params[in->id].burst_read;\n\t\t\t/* What about frag and ras ports? */\n\t\t\tbreak;\n\t\tcase APP_PKTQ_IN_TM:\n\t\t\tout->type = PIPELINE_PORT_IN_SCHED_READER;\n\t\t\tout->params.sched.sched = app->tm[in->id];\n\t\t\tout->burst_size = app->tm_params[in->id].burst_read;\n\t\t\tbreak;\n\t\tcase APP_PKTQ_IN_SOURCE:\n\t\t\tout->type = PIPELINE_PORT_IN_SOURCE;\n\t\t\tout->params.source.mempool = app->mempool[in->id];\n\t\t\tout->burst_size = app->source_params[in->id].burst;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* pktq_out */\n\tp_out->n_ports_out = p_in->n_pktq_out;\n\tfor (i = 0; i < p_in->n_pktq_out; i++) {\n\t\tstruct app_pktq_out_params *in = &p_in->pktq_out[i];\n\t\tstruct pipeline_port_out_params *out = &p_out->port_out[i];\n\n\t\tswitch (in->type) {\n\t\tcase APP_PKTQ_OUT_HWQ:\n\t\t{\n\t\t\tstruct app_pktq_hwq_out_params *p_hwq_out =\n\t\t\t\t&app->hwq_out_params[in->id];\n\t\t\tstruct app_link_params *p_link =\n\t\t\t\tapp_get_link_for_txq(app, p_hwq_out);\n\t\t\tuint32_t txq_link_id, txq_queue_id;\n\n\t\t\tsscanf(p_hwq_out->name,\n\t\t\t\t\"TXQ%\" SCNu32 \".%\" SCNu32,\n\t\t\t\t&txq_link_id,\n\t\t\t\t&txq_queue_id);\n\n\t\t\tif (p_hwq_out->dropless == 0) {\n\t\t\t\tstruct rte_port_ethdev_writer_params *params =\n\t\t\t\t\t&out->params.ethdev;\n\n\t\t\t\tout->type = PIPELINE_PORT_OUT_ETHDEV_WRITER;\n\t\t\t\tparams->port_id = p_link->pmd_id;\n\t\t\t\tparams->queue_id = txq_queue_id;\n\t\t\t\tparams->tx_burst_sz =\n\t\t\t\t\tapp->hwq_out_params[in->id].burst;\n\t\t\t} else {\n\t\t\t\tstruct rte_port_ethdev_writer_nodrop_params\n\t\t\t\t\t*params = &out->params.ethdev_nodrop;\n\n\t\t\t\tout->type =\n\t\t\t\t\tPIPELINE_PORT_OUT_ETHDEV_WRITER_NODROP;\n\t\t\t\tparams->port_id = p_link->pmd_id;\n\t\t\t\tparams->queue_id = txq_queue_id;\n\t\t\t\tparams->tx_burst_sz = p_hwq_out->burst;\n\t\t\t\tparams->n_retries = p_hwq_out->n_retries;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\t\tcase APP_PKTQ_OUT_SWQ:\n\t\t\tif (app->swq_params[in->id].dropless == 0) {\n\t\t\t\tstruct rte_port_ring_writer_params *params =\n\t\t\t\t\t&out->params.ring;\n\n\t\t\t\tout->type = PIPELINE_PORT_OUT_RING_WRITER;\n\t\t\t\tparams->ring = app->swq[in->id];\n\t\t\t\tparams->tx_burst_sz =\n\t\t\t\t\tapp->swq_params[in->id].burst_write;\n\t\t\t} else {\n\t\t\t\tstruct rte_port_ring_writer_nodrop_params\n\t\t\t\t\t*params = &out->params.ring_nodrop;\n\n\t\t\t\tout->type =\n\t\t\t\t\tPIPELINE_PORT_OUT_RING_WRITER_NODROP;\n\t\t\t\tparams->ring = app->swq[in->id];\n\t\t\t\tparams->tx_burst_sz =\n\t\t\t\t\tapp->swq_params[in->id].burst_write;\n\t\t\t\tparams->n_retries =\n\t\t\t\t\tapp->swq_params[in->id].n_retries;\n\t\t\t}\n\t\t\t/* What about frag and ras ports? */\n\t\t\tbreak;\n\t\tcase APP_PKTQ_OUT_TM: {\n\t\t\tstruct rte_port_sched_writer_params *params =\n\t\t\t\t&out->params.sched;\n\n\t\t\tout->type = PIPELINE_PORT_OUT_SCHED_WRITER;\n\t\t\tparams->sched = app->tm[in->id];\n\t\t\tparams->tx_burst_sz =\n\t\t\t\tapp->tm_params[in->id].burst_write;\n\t\t\tbreak;\n\t\t}\n\t\tcase APP_PKTQ_OUT_SINK:\n\t\t\tout->type = PIPELINE_PORT_OUT_SINK;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* msgq */\n\tp_out->n_msgq = p_in->n_msgq_in;\n\n\tfor (i = 0; i < p_in->n_msgq_in; i++)\n\t\tp_out->msgq_in[i] = app->msgq[p_in->msgq_in[i]];\n\n\tfor (i = 0; i < p_in->n_msgq_out; i++)\n\t\tp_out->msgq_out[i] = app->msgq[p_in->msgq_out[i]];\n\n\t/* args */\n\tp_out->n_args = p_in->n_args;\n\tfor (i = 0; i < p_in->n_args; i++) {\n\t\tp_out->args_name[i] = p_in->args_name[i];\n\t\tp_out->args_value[i] = p_in->args_value[i];\n\t}\n}\n\nstatic void\napp_init_pipelines(struct app_params *app)\n{\n\tuint32_t p_id;\n\n\tfor (p_id = 0; p_id < app->n_pipelines; p_id++) {\n\t\tstruct app_pipeline_params *params =\n\t\t\t&app->pipeline_params[p_id];\n\t\tstruct app_pipeline_data *data = &app->pipeline_data[p_id];\n\t\tstruct pipeline_type *ptype;\n\t\tstruct pipeline_params pp;\n\n\t\tAPP_LOG(app, HIGH, \"Initializing %s ...\", params->name);\n\n\t\tptype = app_pipeline_type_find(app, params->type);\n\t\tif (ptype == NULL)\n\t\t\trte_panic(\"Init error: Unknown pipeline type \\\"%s\\\"\\n\",\n\t\t\t\tparams->type);\n\n\t\tapp_pipeline_params_get(app, params, &pp);\n\n\t\t/* Back-end */\n\t\tdata->be = NULL;\n\t\tif (ptype->be_ops->f_init) {\n\t\t\tdata->be = ptype->be_ops->f_init(&pp, (void *) app);\n\n\t\t\tif (data->be == NULL)\n\t\t\t\trte_panic(\"Pipeline instance \\\"%s\\\" back-end \"\n\t\t\t\t\t\"init error\\n\", params->name);\n\t\t}\n\n\t\t/* Front-end */\n\t\tdata->fe = NULL;\n\t\tif (ptype->fe_ops->f_init) {\n\t\t\tdata->fe = ptype->fe_ops->f_init(&pp, (void *) app);\n\n\t\t\tif (data->fe == NULL)\n\t\t\t\trte_panic(\"Pipeline instance \\\"%s\\\" front-end \"\n\t\t\t\t\"init error\\n\", params->name);\n\t\t}\n\n\t\tdata->timer_period = (rte_get_tsc_hz() * params->timer_period)\n\t\t\t/ 1000;\n\t}\n}\n\nstatic void\napp_init_threads(struct app_params *app)\n{\n\tuint64_t time = rte_get_tsc_cycles();\n\tuint32_t p_id;\n\n\tfor (p_id = 0; p_id < app->n_pipelines; p_id++) {\n\t\tstruct app_pipeline_params *params =\n\t\t\t&app->pipeline_params[p_id];\n\t\tstruct app_pipeline_data *data = &app->pipeline_data[p_id];\n\t\tstruct pipeline_type *ptype;\n\t\tstruct app_thread_data *t;\n\t\tstruct app_thread_pipeline_data *p;\n\t\tint lcore_id;\n\n\t\tlcore_id = cpu_core_map_get_lcore_id(app->core_map,\n\t\t\tparams->socket_id,\n\t\t\tparams->core_id,\n\t\t\tparams->hyper_th_id);\n\n\t\tif (lcore_id < 0)\n\t\t\trte_panic(\"Invalid core s%\" PRIu32 \"c%\" PRIu32 \"%s\\n\",\n\t\t\t\tparams->socket_id,\n\t\t\t\tparams->core_id,\n\t\t\t\t(params->hyper_th_id) ? \"h\" : \"\");\n\n\t\tt = &app->thread_data[lcore_id];\n\n\t\tptype = app_pipeline_type_find(app, params->type);\n\t\tif (ptype == NULL)\n\t\t\trte_panic(\"Init error: Unknown pipeline \"\n\t\t\t\t\"type \\\"%s\\\"\\n\", params->type);\n\n\t\tp = (ptype->be_ops->f_run == NULL) ?\n\t\t\t&t->regular[t->n_regular] :\n\t\t\t&t->custom[t->n_custom];\n\n\t\tp->be = data->be;\n\t\tp->f_run = ptype->be_ops->f_run;\n\t\tp->f_timer = ptype->be_ops->f_timer;\n\t\tp->timer_period = data->timer_period;\n\t\tp->deadline = time + data->timer_period;\n\n\t\tif (ptype->be_ops->f_run == NULL)\n\t\t\tt->n_regular++;\n\t\telse\n\t\t\tt->n_custom++;\n\t}\n}\n\nint app_init(struct app_params *app)\n{\n\tapp_init_core_map(app);\n\tapp_init_core_mask(app);\n\n\tapp_init_eal(app);\n\tapp_init_mempool(app);\n\tapp_init_link(app);\n\tapp_init_swq(app);\n\tapp_init_tm(app);\n\tapp_init_msgq(app);\n\n\tapp_pipeline_common_cmd_push(app);\n\tapp_pipeline_type_register(app, &pipeline_master);\n\tapp_pipeline_type_register(app, &pipeline_passthrough);\n\tapp_pipeline_type_register(app, &pipeline_flow_classification);\n\tapp_pipeline_type_register(app, &pipeline_firewall);\n\tapp_pipeline_type_register(app, &pipeline_routing);\n\n\tapp_init_pipelines(app);\n\tapp_init_threads(app);\n\n\treturn 0;\n}\n\nstatic int\napp_pipeline_type_cmd_push(struct app_params *app,\n\tstruct pipeline_type *ptype)\n{\n\tcmdline_parse_ctx_t *cmds;\n\tuint32_t n_cmds, i;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(ptype == NULL))\n\t\treturn -EINVAL;\n\n\tn_cmds = pipeline_type_cmds_count(ptype);\n\tif (n_cmds == 0)\n\t\treturn 0;\n\n\tcmds = ptype->fe_ops->cmds;\n\n\t/* Check for available slots in the application commands array */\n\tif (n_cmds > APP_MAX_CMDS - app->n_cmds)\n\t\treturn -ENOMEM;\n\n\t/* Push pipeline commands into the application */\n\tmemcpy(&app->cmds[app->n_cmds],\n\t\tcmds,\n\t\tn_cmds * sizeof(cmdline_parse_ctx_t *));\n\n\tfor (i = 0; i < n_cmds; i++)\n\t\tapp->cmds[app->n_cmds + i]->data = app;\n\n\tapp->n_cmds += n_cmds;\n\tapp->cmds[app->n_cmds] = NULL;\n\n\treturn 0;\n}\n\nint\napp_pipeline_type_register(struct app_params *app, struct pipeline_type *ptype)\n{\n\tuint32_t n_cmds, i;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(ptype == NULL) ||\n\t\t(ptype->name == NULL) ||\n\t\t(strlen(ptype->name) == 0) ||\n\t\t(ptype->be_ops->f_init == NULL) ||\n\t\t(ptype->be_ops->f_timer == NULL))\n\t\treturn -EINVAL;\n\n\t/* Check for duplicate entry */\n\tfor (i = 0; i < app->n_pipeline_types; i++)\n\t\tif (strcmp(app->pipeline_type[i].name, ptype->name) == 0)\n\t\t\treturn -EEXIST;\n\n\t/* Check for resource availability */\n\tn_cmds = pipeline_type_cmds_count(ptype);\n\tif ((app->n_pipeline_types == APP_MAX_PIPELINE_TYPES) ||\n\t\t(n_cmds > APP_MAX_CMDS - app->n_cmds))\n\t\treturn -ENOMEM;\n\n\t/* Copy pipeline type */\n\tmemcpy(&app->pipeline_type[app->n_pipeline_types++],\n\t\tptype,\n\t\tsizeof(struct pipeline_type));\n\n\t/* Copy CLI commands */\n\tif (n_cmds)\n\t\tapp_pipeline_type_cmd_push(app, ptype);\n\n\treturn 0;\n}\n\nstruct\npipeline_type *app_pipeline_type_find(struct app_params *app, char *name)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < app->n_pipeline_types; i++)\n\t\tif (strcmp(app->pipeline_type[i].name, name) == 0)\n\t\t\treturn &app->pipeline_type[i];\n\n\treturn NULL;\n}\n" }, { "path": "examples/ip_pipeline/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"app.h\"\n\nstatic struct app_params app;\n\nint\nmain(int argc, char **argv)\n{\n\trte_openlog_stream(stderr);\n\n\t/* Config */\n\tapp_config_init(&app);\n\n\tapp_config_args(&app, argc, argv);\n\n\tapp_config_parse(&app, app.config_file);\n\n\tapp_config_check(&app);\n\n\t/* Init */\n\tapp_init(&app);\n\n\t/* Run-time */\n\trte_eal_mp_remote_launch(\n\t\tapp_thread,\n\t\t(void *) &app,\n\t\tCALL_MASTER);\n\n\treturn 0;\n}\n" }, { "path": "examples/ip_pipeline/pipeline/hash_func.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef __INCLUDE_HASH_FUNC_H__\n#define __INCLUDE_HASH_FUNC_H__\n\nstatic inline uint64_t\nhash_xor_key8(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t xor0;\n\n\txor0 = seed ^ k[0];\n\n\treturn (xor0 >> 32) ^ xor0;\n}\n\nstatic inline uint64_t\nhash_xor_key16(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t xor0;\n\n\txor0 = (k[0] ^ seed) ^ k[1];\n\n\treturn (xor0 >> 32) ^ xor0;\n}\n\nstatic inline uint64_t\nhash_xor_key24(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t xor0;\n\n\txor0 = (k[0] ^ seed) ^ k[1];\n\n\txor0 ^= k[2];\n\n\treturn (xor0 >> 32) ^ xor0;\n}\n\nstatic inline uint64_t\nhash_xor_key32(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t xor0, xor1;\n\n\txor0 = (k[0] ^ seed) ^ k[1];\n\txor1 = k[2] ^ k[3];\n\n\txor0 ^= xor1;\n\n\treturn (xor0 >> 32) ^ xor0;\n}\n\nstatic inline uint64_t\nhash_xor_key40(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t xor0, xor1;\n\n\txor0 = (k[0] ^ seed) ^ k[1];\n\txor1 = k[2] ^ k[3];\n\n\txor0 ^= xor1;\n\n\txor0 ^= k[4];\n\n\treturn (xor0 >> 32) ^ xor0;\n}\n\nstatic inline uint64_t\nhash_xor_key48(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t xor0, xor1, xor2;\n\n\txor0 = (k[0] ^ seed) ^ k[1];\n\txor1 = k[2] ^ k[3];\n\txor2 = k[4] ^ k[5];\n\n\txor0 ^= xor1;\n\n\txor0 ^= xor2;\n\n\treturn (xor0 >> 32) ^ xor0;\n}\n\nstatic inline uint64_t\nhash_xor_key56(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t xor0, xor1, xor2;\n\n\txor0 = (k[0] ^ seed) ^ k[1];\n\txor1 = k[2] ^ k[3];\n\txor2 = k[4] ^ k[5];\n\n\txor0 ^= xor1;\n\txor2 ^= k[6];\n\n\txor0 ^= xor2;\n\n\treturn (xor0 >> 32) ^ xor0;\n}\n\nstatic inline uint64_t\nhash_xor_key64(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t xor0, xor1, xor2, xor3;\n\n\txor0 = (k[0] ^ seed) ^ k[1];\n\txor1 = k[2] ^ k[3];\n\txor2 = k[4] ^ k[5];\n\txor3 = k[6] ^ k[7];\n\n\txor0 ^= xor1;\n\txor2 ^= xor3;\n\n\txor0 ^= xor2;\n\n\treturn (xor0 >> 32) ^ xor0;\n}\n\n#if defined(__x86_64__)\n\n#include \n\nstatic inline uint64_t\nhash_crc_key8(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t crc0;\n\n\tcrc0 = _mm_crc32_u64(seed, k[0]);\n\n\treturn crc0;\n}\n\nstatic inline uint64_t\nhash_crc_key16(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t k0, crc0, crc1;\n\n\tk0 = k[0];\n\n\tcrc0 = _mm_crc32_u64(k0, seed);\n\tcrc1 = _mm_crc32_u64(k0 >> 32, k[1]);\n\n\tcrc0 ^= crc1;\n\n\treturn crc0;\n}\n\nstatic inline uint64_t\nhash_crc_key24(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t k0, k2, crc0, crc1;\n\n\tk0 = k[0];\n\tk2 = k[2];\n\n\tcrc0 = _mm_crc32_u64(k0, seed);\n\tcrc1 = _mm_crc32_u64(k0 >> 32, k[1]);\n\n\tcrc0 = _mm_crc32_u64(crc0, k2);\n\n\tcrc0 ^= crc1;\n\n\treturn crc0;\n}\n\nstatic inline uint64_t\nhash_crc_key32(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t k0, k2, crc0, crc1, crc2, crc3;\n\n\tk0 = k[0];\n\tk2 = k[2];\n\n\tcrc0 = _mm_crc32_u64(k0, seed);\n\tcrc1 = _mm_crc32_u64(k0 >> 32, k[1]);\n\n\tcrc2 = _mm_crc32_u64(k2, k[3]);\n\tcrc3 = k2 >> 32;\n\n\tcrc0 = _mm_crc32_u64(crc0, crc1);\n\tcrc1 = _mm_crc32_u64(crc2, crc3);\n\n\tcrc0 ^= crc1;\n\n\treturn crc0;\n}\n\nstatic inline uint64_t\nhash_crc_key40(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t k0, k2, crc0, crc1, crc2, crc3;\n\n\tk0 = k[0];\n\tk2 = k[2];\n\n\tcrc0 = _mm_crc32_u64(k0, seed);\n\tcrc1 = _mm_crc32_u64(k0 >> 32, k[1]);\n\n\tcrc2 = _mm_crc32_u64(k2, k[3]);\n\tcrc3 = _mm_crc32_u64(k2 >> 32, k[4]);\n\n\tcrc0 = _mm_crc32_u64(crc0, crc1);\n\tcrc1 = _mm_crc32_u64(crc2, crc3);\n\n\tcrc0 ^= crc1;\n\n\treturn crc0;\n}\n\nstatic inline uint64_t\nhash_crc_key48(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t k0, k2, k5, crc0, crc1, crc2, crc3;\n\n\tk0 = k[0];\n\tk2 = k[2];\n\tk5 = k[5];\n\n\tcrc0 = _mm_crc32_u64(k0, seed);\n\tcrc1 = _mm_crc32_u64(k0 >> 32, k[1]);\n\n\tcrc2 = _mm_crc32_u64(k2, k[3]);\n\tcrc3 = _mm_crc32_u64(k2 >> 32, k[4]);\n\n\tcrc0 = _mm_crc32_u64(crc0, (crc1 << 32) ^ crc2);\n\tcrc1 = _mm_crc32_u64(crc3, k5);\n\n\tcrc0 ^= crc1;\n\n\treturn crc0;\n}\n\nstatic inline uint64_t\nhash_crc_key56(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t k0, k2, k5, crc0, crc1, crc2, crc3, crc4, crc5;\n\n\tk0 = k[0];\n\tk2 = k[2];\n\tk5 = k[5];\n\n\tcrc0 = _mm_crc32_u64(k0, seed);\n\tcrc1 = _mm_crc32_u64(k0 >> 32, k[1]);\n\n\tcrc2 = _mm_crc32_u64(k2, k[3]);\n\tcrc3 = _mm_crc32_u64(k2 >> 32, k[4]);\n\n\tcrc4 = _mm_crc32_u64(k5, k[6]);\n\tcrc5 = k5 >> 32;\n\n\tcrc0 = _mm_crc32_u64(crc0, (crc1 << 32) ^ crc2);\n\tcrc1 = _mm_crc32_u64(crc3, (crc4 << 32) ^ crc5);\n\n\tcrc0 ^= crc1;\n\n\treturn crc0;\n}\n\nstatic inline uint64_t\nhash_crc_key64(void *key, __rte_unused uint32_t key_size, uint64_t seed)\n{\n\tuint64_t *k = key;\n\tuint64_t k0, k2, k5, crc0, crc1, crc2, crc3, crc4, crc5;\n\n\tk0 = k[0];\n\tk2 = k[2];\n\tk5 = k[5];\n\n\tcrc0 = _mm_crc32_u64(k0, seed);\n\tcrc1 = _mm_crc32_u64(k0 >> 32, k[1]);\n\n\tcrc2 = _mm_crc32_u64(k2, k[3]);\n\tcrc3 = _mm_crc32_u64(k2 >> 32, k[4]);\n\n\tcrc4 = _mm_crc32_u64(k5, k[6]);\n\tcrc5 = _mm_crc32_u64(k5 >> 32, k[7]);\n\n\tcrc0 = _mm_crc32_u64(crc0, (crc1 << 32) ^ crc2);\n\tcrc1 = _mm_crc32_u64(crc3, (crc4 << 32) ^ crc5);\n\n\tcrc0 ^= crc1;\n\n\treturn crc0;\n}\n\n#define hash_default_key8\t\t\thash_crc_key8\n#define hash_default_key16\t\t\thash_crc_key16\n#define hash_default_key24\t\t\thash_crc_key24\n#define hash_default_key32\t\t\thash_crc_key32\n#define hash_default_key40\t\t\thash_crc_key40\n#define hash_default_key48\t\t\thash_crc_key48\n#define hash_default_key56\t\t\thash_crc_key56\n#define hash_default_key64\t\t\thash_crc_key64\n\n#else\n\n#define hash_default_key8\t\t\thash_xor_key8\n#define hash_default_key16\t\t\thash_xor_key16\n#define hash_default_key24\t\t\thash_xor_key24\n#define hash_default_key32\t\t\thash_xor_key32\n#define hash_default_key40\t\t\thash_xor_key40\n#define hash_default_key48\t\t\thash_xor_key48\n#define hash_default_key56\t\t\thash_xor_key56\n#define hash_default_key64\t\t\thash_xor_key64\n\n#endif\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_actions_common.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef __INCLUDE_PIPELINE_ACTIONS_COMMON_H__\n#define __INCLUDE_PIPELINE_ACTIONS_COMMON_H__\n\n#define PIPELINE_PORT_IN_AH(f_ah, f_pkt_work, f_pkt4_work)\t\t\\\nstatic int\t\t\t\t\t\t\t\t\\\nf_ah(\t\t\t\t\t\t\t\t\t\\\n\tstruct rte_mbuf **pkts,\t\t\t\t\t\t\\\n\tuint32_t n_pkts,\t\t\t\t\t\t\\\n\tuint64_t *pkts_mask,\t\t\t\t\t\t\\\n\tvoid *arg)\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tuint32_t i;\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tfor (i = 0; i < (n_pkts & (~0x3LLU)); i += 4)\t\t\t\\\n\t\tf_pkt4_work(&pkts[i], arg);\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tfor ( ; i < n_pkts; i++)\t\t\t\t\t\\\n\t\tf_pkt_work(pkts[i], arg);\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t*pkts_mask = (~0LLU) >> (64 - n_pkts);\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\treturn 0;\t\t\t\t\t\t\t\\\n}\n\n#define PIPELINE_TABLE_AH_HIT(f_ah, f_pkt_work, f_pkt4_work)\t\t\\\nstatic int\t\t\t\t\t\t\t\t\\\nf_ah(\t\t\t\t\t\t\t\t\t\\\n\tstruct rte_mbuf **pkts,\t\t\t\t\t\t\\\n\tuint64_t *pkts_mask,\t\t\t\t\t\t\\\n\tstruct rte_pipeline_table_entry **entries,\t\t\t\\\n\tvoid *arg)\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tuint64_t pkts_in_mask = *pkts_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tif ((pkts_in_mask & (pkts_in_mask + 1)) == 0) {\t\t\t\\\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_in_mask);\t\\\n\t\tuint32_t i;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t\tfor (i = 0; i < (n_pkts & (~0x3LLU)); i += 4)\t\t\\\n\t\t\tf_pkt4_work(&pkts[i], &entries[i], arg);\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t\tfor ( ; i < n_pkts; i++)\t\t\t\t\\\n\t\t\tf_pkt_work(pkts[i], entries[i], arg);\t\t\\\n\t} else\t\t\t\t\t\t\t\t\\\n\t\tfor ( ; pkts_in_mask; ) {\t\t\t\t\\\n\t\t\tuint32_t pos = __builtin_ctzll(pkts_in_mask);\t\\\n\t\t\tuint64_t pkt_mask = 1LLU << pos;\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t\t\tpkts_in_mask &= ~pkt_mask;\t\t\t\\\n\t\t\tf_pkt_work(pkts[pos], entries[pos], arg);\t\\\n\t\t}\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\treturn 0;\t\t\t\t\t\t\t\\\n}\n\n#define PIPELINE_TABLE_AH_MISS(f_ah, f_pkt_work, f_pkt4_work)\t\t\\\nstatic int\t\t\t\t\t\t\t\t\\\nf_ah(\t\t\t\t\t\t\t\t\t\\\n\tstruct rte_mbuf **pkts,\t\t\t\t\t\t\\\n\tuint64_t *pkts_mask,\t\t\t\t\t\t\\\n\tstruct rte_pipeline_table_entry *entry,\t\t\t\t\\\n\tvoid *arg)\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tuint64_t pkts_in_mask = *pkts_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tif ((pkts_in_mask & (pkts_in_mask + 1)) == 0) {\t\t\t\\\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_in_mask);\t\\\n\t\tuint32_t i;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t\tfor (i = 0; i < (n_pkts & (~0x3LLU)); i += 4)\t\t\\\n\t\t\tf_pkt4_work(&pkts[i], entry, arg);\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t\tfor ( ; i < n_pkts; i++)\t\t\t\t\\\n\t\t\tf_pkt_work(pkts[i], entry, arg);\t\t\\\n\t} else\t\t\t\t\t\t\t\t\\\n\t\tfor ( ; pkts_in_mask; ) {\t\t\t\t\\\n\t\t\tuint32_t pos = __builtin_ctzll(pkts_in_mask);\t\\\n\t\t\tuint64_t pkt_mask = 1LLU << pos;\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t\t\tpkts_in_mask &= ~pkt_mask;\t\t\t\\\n\t\t\tf_pkt_work(pkts[pos], entry, arg);\t\t\\\n\t\t}\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\treturn 0;\t\t\t\t\t\t\t\\\n}\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_common_be.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \"pipeline_common_be.h\"\n\nvoid *\npipeline_msg_req_ping_handler(__rte_unused struct pipeline *p,\n\tvoid *msg)\n{\n\tstruct pipeline_msg_rsp *rsp = msg;\n\n\trsp->status = 0; /* OK */\n\n\treturn rsp;\n}\n\nvoid *\npipeline_msg_req_stats_port_in_handler(struct pipeline *p,\n\tvoid *msg)\n{\n\tstruct pipeline_stats_msg_req *req = msg;\n\tstruct pipeline_stats_port_in_msg_rsp *rsp = msg;\n\tuint32_t port_id;\n\n\t/* Check request */\n\tif (req->id >= p->n_ports_in) {\n\t\trsp->status = -1;\n\t\treturn rsp;\n\t}\n\tport_id = p->port_in_id[req->id];\n\n\t/* Process request */\n\trsp->status = rte_pipeline_port_in_stats_read(p->p,\n\t\tport_id,\n\t\t&rsp->stats,\n\t\t1);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_msg_req_stats_port_out_handler(struct pipeline *p,\n\tvoid *msg)\n{\n\tstruct pipeline_stats_msg_req *req = msg;\n\tstruct pipeline_stats_port_out_msg_rsp *rsp = msg;\n\tuint32_t port_id;\n\n\t/* Check request */\n\tif (req->id >= p->n_ports_out) {\n\t\trsp->status = -1;\n\t\treturn rsp;\n\t}\n\tport_id = p->port_out_id[req->id];\n\n\t/* Process request */\n\trsp->status = rte_pipeline_port_out_stats_read(p->p,\n\t\tport_id,\n\t\t&rsp->stats,\n\t\t1);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_msg_req_stats_table_handler(struct pipeline *p,\n\tvoid *msg)\n{\n\tstruct pipeline_stats_msg_req *req = msg;\n\tstruct pipeline_stats_table_msg_rsp *rsp = msg;\n\tuint32_t table_id;\n\n\t/* Check request */\n\tif (req->id >= p->n_tables) {\n\t\trsp->status = -1;\n\t\treturn rsp;\n\t}\n\ttable_id = p->table_id[req->id];\n\n\t/* Process request */\n\trsp->status = rte_pipeline_table_stats_read(p->p,\n\t\ttable_id,\n\t\t&rsp->stats,\n\t\t1);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_msg_req_port_in_enable_handler(struct pipeline *p,\n\tvoid *msg)\n{\n\tstruct pipeline_port_in_msg_req *req = msg;\n\tstruct pipeline_msg_rsp *rsp = msg;\n\tuint32_t port_id;\n\n\t/* Check request */\n\tif (req->port_id >= p->n_ports_in) {\n\t\trsp->status = -1;\n\t\treturn rsp;\n\t}\n\tport_id = p->port_in_id[req->port_id];\n\n\t/* Process request */\n\trsp->status = rte_pipeline_port_in_enable(p->p,\n\t\tport_id);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_msg_req_port_in_disable_handler(struct pipeline *p,\n\tvoid *msg)\n{\n\tstruct pipeline_port_in_msg_req *req = msg;\n\tstruct pipeline_msg_rsp *rsp = msg;\n\tuint32_t port_id;\n\n\t/* Check request */\n\tif (req->port_id >= p->n_ports_in) {\n\t\trsp->status = -1;\n\t\treturn rsp;\n\t}\n\tport_id = p->port_in_id[req->port_id];\n\n\t/* Process request */\n\trsp->status = rte_pipeline_port_in_disable(p->p,\n\t\tport_id);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_msg_req_invalid_handler(__rte_unused struct pipeline *p,\n\tvoid *msg)\n{\n\tstruct pipeline_msg_rsp *rsp = msg;\n\n\trsp->status = -1; /* Error */\n\n\treturn rsp;\n}\n\nint\npipeline_msg_req_handle(struct pipeline *p)\n{\n\tuint32_t msgq_id;\n\n\tfor (msgq_id = 0; msgq_id < p->n_msgq; msgq_id++) {\n\t\tfor ( ; ; ) {\n\t\t\tstruct pipeline_msg_req *req;\n\t\t\tpipeline_msg_req_handler f_handle;\n\n\t\t\treq = pipeline_msg_recv(p, msgq_id);\n\t\t\tif (req == NULL)\n\t\t\t\tbreak;\n\n\t\t\tf_handle = (req->type < PIPELINE_MSG_REQS) ?\n\t\t\t\tp->handlers[req->type] :\n\t\t\t\tpipeline_msg_req_invalid_handler;\n\n\t\t\tif (f_handle == NULL)\n\t\t\t\tf_handle = pipeline_msg_req_invalid_handler;\n\n\t\t\tpipeline_msg_send(p,\n\t\t\t\tmsgq_id,\n\t\t\t\tf_handle(p, (void *) req));\n\t\t}\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_common_be.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_COMMON_BE_H__\n#define __INCLUDE_PIPELINE_COMMON_BE_H__\n\n#include \n#include \n#include \n\n#include \"pipeline_be.h\"\n\nstruct pipeline;\n\nenum pipeline_msg_req_type {\n\tPIPELINE_MSG_REQ_PING = 0,\n\tPIPELINE_MSG_REQ_STATS_PORT_IN,\n\tPIPELINE_MSG_REQ_STATS_PORT_OUT,\n\tPIPELINE_MSG_REQ_STATS_TABLE,\n\tPIPELINE_MSG_REQ_PORT_IN_ENABLE,\n\tPIPELINE_MSG_REQ_PORT_IN_DISABLE,\n\tPIPELINE_MSG_REQ_CUSTOM,\n\tPIPELINE_MSG_REQS\n};\n\ntypedef void *(*pipeline_msg_req_handler)(struct pipeline *p, void *msg);\n\nstruct pipeline {\n\tstruct rte_pipeline *p;\n\tuint32_t port_in_id[PIPELINE_MAX_PORT_IN];\n\tuint32_t port_out_id[PIPELINE_MAX_PORT_OUT];\n\tuint32_t table_id[PIPELINE_MAX_TABLES];\n\tstruct rte_ring *msgq_in[PIPELINE_MAX_MSGQ_IN];\n\tstruct rte_ring *msgq_out[PIPELINE_MAX_MSGQ_OUT];\n\n\tuint32_t n_ports_in;\n\tuint32_t n_ports_out;\n\tuint32_t n_tables;\n\tuint32_t n_msgq;\n\n\tpipeline_msg_req_handler handlers[PIPELINE_MSG_REQS];\n\tchar name[PIPELINE_NAME_SIZE];\n\tuint32_t log_level;\n};\n\nenum pipeline_log_level {\n\tPIPELINE_LOG_LEVEL_HIGH = 1,\n\tPIPELINE_LOG_LEVEL_LOW,\n\tPIPELINE_LOG_LEVELS\n};\n\n#define PLOG(p, level, fmt, ...)\t\t\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\tif (p->log_level >= PIPELINE_LOG_LEVEL_ ## level)\t\t\\\n\t\tfprintf(stdout, \"[%s] \" fmt \"\\n\", p->name, ## __VA_ARGS__);\\\n} while (0)\n\nstatic inline void *\npipeline_msg_recv(struct pipeline *p,\n\tuint32_t msgq_id)\n{\n\tstruct rte_ring *r = p->msgq_in[msgq_id];\n\tvoid *msg;\n\tint status = rte_ring_sc_dequeue(r, &msg);\n\n\tif (status != 0)\n\t\treturn NULL;\n\n\treturn msg;\n}\n\nstatic inline void\npipeline_msg_send(struct pipeline *p,\n\tuint32_t msgq_id,\n\tvoid *msg)\n{\n\tstruct rte_ring *r = p->msgq_out[msgq_id];\n\tint status;\n\n\tdo {\n\t\tstatus = rte_ring_sp_enqueue(r, msg);\n\t} while (status == -ENOBUFS);\n}\n\nstruct pipeline_msg_req {\n\tenum pipeline_msg_req_type type;\n};\n\nstruct pipeline_stats_msg_req {\n\tenum pipeline_msg_req_type type;\n\tuint32_t id;\n};\n\nstruct pipeline_port_in_msg_req {\n\tenum pipeline_msg_req_type type;\n\tuint32_t port_id;\n};\n\nstruct pipeline_custom_msg_req {\n\tenum pipeline_msg_req_type type;\n\tuint32_t subtype;\n};\n\nstruct pipeline_msg_rsp {\n\tint status;\n};\n\nstruct pipeline_stats_port_in_msg_rsp {\n\tint status;\n\tstruct rte_pipeline_port_in_stats stats;\n};\n\nstruct pipeline_stats_port_out_msg_rsp {\n\tint status;\n\tstruct rte_pipeline_port_out_stats stats;\n};\n\nstruct pipeline_stats_table_msg_rsp {\n\tint status;\n\tstruct rte_pipeline_table_stats stats;\n};\n\nvoid *pipeline_msg_req_ping_handler(struct pipeline *p, void *msg);\nvoid *pipeline_msg_req_stats_port_in_handler(struct pipeline *p, void *msg);\nvoid *pipeline_msg_req_stats_port_out_handler(struct pipeline *p, void *msg);\nvoid *pipeline_msg_req_stats_table_handler(struct pipeline *p, void *msg);\nvoid *pipeline_msg_req_port_in_enable_handler(struct pipeline *p, void *msg);\nvoid *pipeline_msg_req_port_in_disable_handler(struct pipeline *p, void *msg);\nvoid *pipeline_msg_req_invalid_handler(struct pipeline *p, void *msg);\n\nint pipeline_msg_req_handle(struct pipeline *p);\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_common_fe.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"pipeline_common_fe.h\"\n\nint\napp_pipeline_ping(struct app_params *app,\n\tuint32_t pipeline_id)\n{\n\tstruct app_pipeline_params *p;\n\tstruct pipeline_msg_req *req;\n\tstruct pipeline_msg_rsp *rsp;\n\tint status = 0;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tAPP_PARAM_FIND_BY_ID(app->pipeline_params, \"PIPELINE\", pipeline_id, p);\n\tif (p == NULL)\n\t\treturn -1;\n\n\t/* Message buffer allocation */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\t/* Fill in request */\n\treq->type = PIPELINE_MSG_REQ_PING;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Check response */\n\tstatus = rsp->status;\n\n\t/* Message buffer free */\n\tapp_msg_free(app, rsp);\n\n\treturn status;\n}\n\nint\napp_pipeline_stats_port_in(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id,\n\tstruct rte_pipeline_port_in_stats *stats)\n{\n\tstruct app_pipeline_params *p;\n\tstruct pipeline_stats_msg_req *req;\n\tstruct pipeline_stats_port_in_msg_rsp *rsp;\n\tint status = 0;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(stats == NULL))\n\t\treturn -1;\n\n\tAPP_PARAM_FIND_BY_ID(app->pipeline_params, \"PIPELINE\", pipeline_id, p);\n\tif ((p == NULL) ||\n\t\t(port_id >= p->n_pktq_in))\n\t\treturn -1;\n\n\t/* Message buffer allocation */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\t/* Fill in request */\n\treq->type = PIPELINE_MSG_REQ_STATS_PORT_IN;\n\treq->id = port_id;\n\n\t/* Send request and wait for response */\n\trsp = (struct pipeline_stats_port_in_msg_rsp *)\n\t\tapp_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Check response */\n\tstatus = rsp->status;\n\tif (status == 0)\n\t\tmemcpy(stats, &rsp->stats, sizeof(rsp->stats));\n\n\t/* Message buffer free */\n\tapp_msg_free(app, rsp);\n\n\treturn status;\n}\n\nint\napp_pipeline_stats_port_out(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id,\n\tstruct rte_pipeline_port_out_stats *stats)\n{\n\tstruct app_pipeline_params *p;\n\tstruct pipeline_stats_msg_req *req;\n\tstruct pipeline_stats_port_out_msg_rsp *rsp;\n\tint status = 0;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(pipeline_id >= app->n_pipelines) ||\n\t\t(stats == NULL))\n\t\treturn -1;\n\n\tAPP_PARAM_FIND_BY_ID(app->pipeline_params, \"PIPELINE\", pipeline_id, p);\n\tif ((p == NULL) ||\n\t\t(port_id >= p->n_pktq_out))\n\t\treturn -1;\n\n\t/* Message buffer allocation */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\t/* Fill in request */\n\treq->type = PIPELINE_MSG_REQ_STATS_PORT_OUT;\n\treq->id = port_id;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Check response */\n\tstatus = rsp->status;\n\tif (status == 0)\n\t\tmemcpy(stats, &rsp->stats, sizeof(rsp->stats));\n\n\t/* Message buffer free */\n\tapp_msg_free(app, rsp);\n\n\treturn status;\n}\n\nint\napp_pipeline_stats_table(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t table_id,\n\tstruct rte_pipeline_table_stats *stats)\n{\n\tstruct app_pipeline_params *p;\n\tstruct pipeline_stats_msg_req *req;\n\tstruct pipeline_stats_table_msg_rsp *rsp;\n\tint status = 0;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(stats == NULL))\n\t\treturn -1;\n\n\tAPP_PARAM_FIND_BY_ID(app->pipeline_params, \"PIPELINE\", pipeline_id, p);\n\tif (p == NULL)\n\t\treturn -1;\n\n\t/* Message buffer allocation */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\t/* Fill in request */\n\treq->type = PIPELINE_MSG_REQ_STATS_TABLE;\n\treq->id = table_id;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Check response */\n\tstatus = rsp->status;\n\tif (status == 0)\n\t\tmemcpy(stats, &rsp->stats, sizeof(rsp->stats));\n\n\t/* Message buffer free */\n\tapp_msg_free(app, rsp);\n\n\treturn status;\n}\n\nint\napp_pipeline_port_in_enable(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id)\n{\n\tstruct app_pipeline_params *p;\n\tstruct pipeline_port_in_msg_req *req;\n\tstruct pipeline_msg_rsp *rsp;\n\tint status = 0;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tAPP_PARAM_FIND_BY_ID(app->pipeline_params, \"PIPELINE\", pipeline_id, p);\n\tif ((p == NULL) ||\n\t\t(port_id >= p->n_pktq_in))\n\t\treturn -1;\n\n\t/* Message buffer allocation */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\t/* Fill in request */\n\treq->type = PIPELINE_MSG_REQ_PORT_IN_ENABLE;\n\treq->port_id = port_id;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Check response */\n\tstatus = rsp->status;\n\n\t/* Message buffer free */\n\tapp_msg_free(app, rsp);\n\n\treturn status;\n}\n\nint\napp_pipeline_port_in_disable(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id)\n{\n\tstruct app_pipeline_params *p;\n\tstruct pipeline_port_in_msg_req *req;\n\tstruct pipeline_msg_rsp *rsp;\n\tint status = 0;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tAPP_PARAM_FIND_BY_ID(app->pipeline_params, \"PIPELINE\", pipeline_id, p);\n\tif ((p == NULL) ||\n\t\t(port_id >= p->n_pktq_in))\n\t\treturn -1;\n\n\t/* Message buffer allocation */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\t/* Fill in request */\n\treq->type = PIPELINE_MSG_REQ_PORT_IN_DISABLE;\n\treq->port_id = port_id;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Check response */\n\tstatus = rsp->status;\n\n\t/* Message buffer free */\n\tapp_msg_free(app, rsp);\n\n\treturn status;\n}\n\nint\napp_link_config(struct app_params *app,\n\tuint32_t link_id,\n\tuint32_t ip,\n\tuint32_t depth)\n{\n\tstruct app_link_params *p;\n\tuint32_t i, netmask, host, bcast;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tAPP_PARAM_FIND_BY_ID(app->link_params, \"LINK\", link_id, p);\n\tif (p == NULL) {\n\t\tAPP_LOG(app, HIGH, \"LINK%\" PRIu32 \" is not a valid link\",\n\t\t\tlink_id);\n\t\treturn -1;\n\t}\n\n\tif (p->state) {\n\t\tAPP_LOG(app, HIGH, \"%s is UP, please bring it DOWN first\",\n\t\t\tp->name);\n\t\treturn -1;\n\t}\n\n\tnetmask = (~0) << (32 - depth);\n\thost = ip & netmask;\n\tbcast = host | (~netmask);\n\n\tif ((ip == 0) ||\n\t\t(ip == UINT32_MAX) ||\n\t\t(ip == host) ||\n\t\t(ip == bcast)) {\n\t\tAPP_LOG(app, HIGH, \"Illegal IP address\");\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < app->n_links; i++) {\n\t\tstruct app_link_params *link = &app->link_params[i];\n\n\t\tif (strcmp(p->name, link->name) == 0)\n\t\t\tcontinue;\n\n\t\tif (link->ip == ip) {\n\t\t\tAPP_LOG(app, HIGH,\n\t\t\t\t\"%s is already assigned this IP address\",\n\t\t\t\tp->name);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif ((depth == 0) || (depth > 32)) {\n\t\tAPP_LOG(app, HIGH, \"Illegal value for depth parameter \"\n\t\t\t\"(%\" PRIu32 \")\",\n\t\t\tdepth);\n\t\treturn -1;\n\t}\n\n\t/* Save link parameters */\n\tp->ip = ip;\n\tp->depth = depth;\n\n\treturn 0;\n}\n\nint\napp_link_up(struct app_params *app,\n\tuint32_t link_id)\n{\n\tstruct app_link_params *p;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tAPP_PARAM_FIND_BY_ID(app->link_params, \"LINK\", link_id, p);\n\tif (p == NULL) {\n\t\tAPP_LOG(app, HIGH, \"LINK%\" PRIu32 \" is not a valid link\",\n\t\t\tlink_id);\n\t\treturn -1;\n\t}\n\n\t/* Check link state */\n\tif (p->state) {\n\t\tAPP_LOG(app, HIGH, \"%s is already UP\", p->name);\n\t\treturn 0;\n\t}\n\n\t/* Check that IP address is valid */\n\tif (p->ip == 0) {\n\t\tAPP_LOG(app, HIGH, \"%s IP address is not set\", p->name);\n\t\treturn 0;\n\t}\n\n\tapp_link_up_internal(app, p);\n\n\treturn 0;\n}\n\nint\napp_link_down(struct app_params *app,\n\tuint32_t link_id)\n{\n\tstruct app_link_params *p;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tAPP_PARAM_FIND_BY_ID(app->link_params, \"LINK\", link_id, p);\n\tif (p == NULL) {\n\t\tAPP_LOG(app, HIGH, \"LINK%\" PRIu32 \" is not a valid link\",\n\t\t\tlink_id);\n\t\treturn -1;\n\t}\n\n\t/* Check link state */\n\tif (p->state == 0) {\n\t\tAPP_LOG(app, HIGH, \"%s is already DOWN\", p->name);\n\t\treturn 0;\n\t}\n\n\tapp_link_down_internal(app, p);\n\n\treturn 0;\n}\n\n/*\n * ping\n */\n\nstruct cmd_ping_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t ping_string;\n};\n\nstatic void\ncmd_ping_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_ping_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_pipeline_ping(app,\tparams->pipeline_id);\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n}\n\ncmdline_parse_token_string_t cmd_ping_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_ping_result, p_string, \"p\");\n\ncmdline_parse_token_num_t cmd_ping_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_ping_result, pipeline_id, UINT32);\n\ncmdline_parse_token_string_t cmd_ping_ping_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_ping_result, ping_string, \"ping\");\n\ncmdline_parse_inst_t cmd_ping = {\n\t.f = cmd_ping_parsed,\n\t.data = NULL,\n\t.help_str = \"Pipeline ping\",\n\t.tokens = {\n\t\t(void *) &cmd_ping_p_string,\n\t\t(void *) &cmd_ping_pipeline_id,\n\t\t(void *) &cmd_ping_ping_string,\n\t\tNULL,\n\t},\n};\n\n/*\n * stats port in\n */\n\nstruct cmd_stats_port_in_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t stats_string;\n\tcmdline_fixed_string_t port_string;\n\tcmdline_fixed_string_t in_string;\n\tuint32_t port_in_id;\n\n};\nstatic void\ncmd_stats_port_in_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_stats_port_in_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct rte_pipeline_port_in_stats stats;\n\tint status;\n\n\tstatus = app_pipeline_stats_port_in(app,\n\t\t\tparams->pipeline_id,\n\t\t\tparams->port_in_id,\n\t\t\t&stats);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n\n\t/* Display stats */\n\tprintf(\"Pipeline %\" PRIu32 \" - stats for input port %\" PRIu32 \":\\n\"\n\t\t\"\\tPkts in: %\" PRIu64 \"\\n\"\n\t\t\"\\tPkts dropped by AH: %\" PRIu64 \"\\n\"\n\t\t\"\\tPkts dropped by other: %\" PRIu64 \"\\n\",\n\t\tparams->pipeline_id,\n\t\tparams->port_in_id,\n\t\tstats.stats.n_pkts_in,\n\t\tstats.n_pkts_dropped_by_ah,\n\t\tstats.stats.n_pkts_drop);\n}\n\ncmdline_parse_token_string_t cmd_stats_port_in_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stats_port_in_result, p_string,\n\t\t\"p\");\n\ncmdline_parse_token_num_t cmd_stats_port_in_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_stats_port_in_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_stats_port_in_stats_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stats_port_in_result, stats_string,\n\t\t\"stats\");\n\ncmdline_parse_token_string_t cmd_stats_port_in_port_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stats_port_in_result, port_string,\n\t\t\"port\");\n\ncmdline_parse_token_string_t cmd_stats_port_in_in_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stats_port_in_result, in_string,\n\t\t\"in\");\n\n\tcmdline_parse_token_num_t cmd_stats_port_in_port_in_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_stats_port_in_result, port_in_id,\n\t\tUINT32);\n\ncmdline_parse_inst_t cmd_stats_port_in = {\n\t.f = cmd_stats_port_in_parsed,\n\t.data = NULL,\n\t.help_str = \"Pipeline input port stats\",\n\t.tokens = {\n\t\t(void *) &cmd_stats_port_in_p_string,\n\t\t(void *) &cmd_stats_port_in_pipeline_id,\n\t\t(void *) &cmd_stats_port_in_stats_string,\n\t\t(void *) &cmd_stats_port_in_port_string,\n\t\t(void *) &cmd_stats_port_in_in_string,\n\t\t(void *) &cmd_stats_port_in_port_in_id,\n\t\tNULL,\n\t},\n};\n\n/*\n * stats port out\n */\n\nstruct cmd_stats_port_out_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t stats_string;\n\tcmdline_fixed_string_t port_string;\n\tcmdline_fixed_string_t out_string;\n\tuint32_t port_out_id;\n};\n\nstatic void\ncmd_stats_port_out_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\n\tstruct cmd_stats_port_out_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct rte_pipeline_port_out_stats stats;\n\tint status;\n\n\tstatus = app_pipeline_stats_port_out(app,\n\t\t\tparams->pipeline_id,\n\t\t\tparams->port_out_id,\n\t\t\t&stats);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n\n\t/* Display stats */\n\tprintf(\"Pipeline %\" PRIu32 \" - stats for output port %\" PRIu32 \":\\n\"\n\t\t\"\\tPkts in: %\" PRIu64 \"\\n\"\n\t\t\"\\tPkts dropped by AH: %\" PRIu64 \"\\n\"\n\t\t\"\\tPkts dropped by other: %\" PRIu64 \"\\n\",\n\t\tparams->pipeline_id,\n\t\tparams->port_out_id,\n\t\tstats.stats.n_pkts_in,\n\t\tstats.n_pkts_dropped_by_ah,\n\t\tstats.stats.n_pkts_drop);\n}\n\ncmdline_parse_token_string_t cmd_stats_port_out_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stats_port_out_result, p_string,\n\t\"p\");\n\ncmdline_parse_token_num_t cmd_stats_port_out_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_stats_port_out_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_stats_port_out_stats_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stats_port_out_result, stats_string,\n\t\t\"stats\");\n\ncmdline_parse_token_string_t cmd_stats_port_out_port_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stats_port_out_result, port_string,\n\t\t\"port\");\n\ncmdline_parse_token_string_t cmd_stats_port_out_out_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stats_port_out_result, out_string,\n\t\t\"out\");\n\ncmdline_parse_token_num_t cmd_stats_port_out_port_out_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_stats_port_out_result, port_out_id,\n\t\tUINT32);\n\ncmdline_parse_inst_t cmd_stats_port_out = {\n\t.f = cmd_stats_port_out_parsed,\n\t.data = NULL,\n\t.help_str = \"Pipeline output port stats\",\n\t.tokens = {\n\t\t(void *) &cmd_stats_port_out_p_string,\n\t\t(void *) &cmd_stats_port_out_pipeline_id,\n\t\t(void *) &cmd_stats_port_out_stats_string,\n\t\t(void *) &cmd_stats_port_out_port_string,\n\t\t(void *) &cmd_stats_port_out_out_string,\n\t\t(void *) &cmd_stats_port_out_port_out_id,\n\t\tNULL,\n\t},\n};\n\n/*\n * stats table\n */\n\nstruct cmd_stats_table_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t stats_string;\n\tcmdline_fixed_string_t table_string;\n\tuint32_t table_id;\n};\n\nstatic void\ncmd_stats_table_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_stats_table_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct rte_pipeline_table_stats stats;\n\tint status;\n\n\tstatus = app_pipeline_stats_table(app,\n\t\t\tparams->pipeline_id,\n\t\t\tparams->table_id,\n\t\t\t&stats);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n\n\t/* Display stats */\n\tprintf(\"Pipeline %\" PRIu32 \" - stats for table %\" PRIu32 \":\\n\"\n\t\t\"\\tPkts in: %\" PRIu64 \"\\n\"\n\t\t\"\\tPkts in with lookup miss: %\" PRIu64 \"\\n\"\n\t\t\"\\tPkts in with lookup hit dropped by AH: %\" PRIu64 \"\\n\"\n\t\t\"\\tPkts in with lookup hit dropped by others: %\" PRIu64 \"\\n\"\n\t\t\"\\tPkts in with lookup miss dropped by AH: %\" PRIu64 \"\\n\"\n\t\t\"\\tPkts in with lookup miss dropped by others: %\" PRIu64 \"\\n\",\n\t\tparams->pipeline_id,\n\t\tparams->table_id,\n\t\tstats.stats.n_pkts_in,\n\t\tstats.stats.n_pkts_lookup_miss,\n\t\tstats.n_pkts_dropped_by_lkp_hit_ah,\n\t\tstats.n_pkts_dropped_lkp_hit,\n\t\tstats.n_pkts_dropped_by_lkp_miss_ah,\n\t\tstats.n_pkts_dropped_lkp_miss);\n}\n\ncmdline_parse_token_string_t cmd_stats_table_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stats_table_result, p_string,\n\t\t\"p\");\n\ncmdline_parse_token_num_t cmd_stats_table_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_stats_table_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_stats_table_stats_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stats_table_result, stats_string,\n\t\t\"stats\");\n\ncmdline_parse_token_string_t cmd_stats_table_table_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_stats_table_result, table_string,\n\t\t\"table\");\n\ncmdline_parse_token_num_t cmd_stats_table_table_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_stats_table_result, table_id, UINT32);\n\ncmdline_parse_inst_t cmd_stats_table = {\n\t.f = cmd_stats_table_parsed,\n\t.data = NULL,\n\t.help_str = \"Pipeline table stats\",\n\t.tokens = {\n\t\t(void *) &cmd_stats_table_p_string,\n\t\t(void *) &cmd_stats_table_pipeline_id,\n\t\t(void *) &cmd_stats_table_stats_string,\n\t\t(void *) &cmd_stats_table_table_string,\n\t\t(void *) &cmd_stats_table_table_id,\n\t\tNULL,\n\t},\n};\n\n/*\n * port in enable\n */\n\nstruct cmd_port_in_enable_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t port_string;\n\tcmdline_fixed_string_t in_string;\n\tuint32_t port_in_id;\n\tcmdline_fixed_string_t enable_string;\n};\n\nstatic void\ncmd_port_in_enable_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_port_in_enable_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_pipeline_port_in_enable(app,\n\t\t\tparams->pipeline_id,\n\t\t\tparams->port_in_id);\n\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n}\n\ncmdline_parse_token_string_t cmd_port_in_enable_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_port_in_enable_result, p_string,\n\t\t\"p\");\n\ncmdline_parse_token_num_t cmd_port_in_enable_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_port_in_enable_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_port_in_enable_port_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_port_in_enable_result, port_string,\n\t\"port\");\n\ncmdline_parse_token_string_t cmd_port_in_enable_in_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_port_in_enable_result, in_string,\n\t\t\"in\");\n\ncmdline_parse_token_num_t cmd_port_in_enable_port_in_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_port_in_enable_result, port_in_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_port_in_enable_enable_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_port_in_enable_result,\n\t\tenable_string, \"enable\");\n\ncmdline_parse_inst_t cmd_port_in_enable = {\n\t.f = cmd_port_in_enable_parsed,\n\t.data = NULL,\n\t.help_str = \"Pipeline input port enable\",\n\t.tokens = {\n\t\t(void *) &cmd_port_in_enable_p_string,\n\t\t(void *) &cmd_port_in_enable_pipeline_id,\n\t\t(void *) &cmd_port_in_enable_port_string,\n\t\t(void *) &cmd_port_in_enable_in_string,\n\t\t(void *) &cmd_port_in_enable_port_in_id,\n\t\t(void *) &cmd_port_in_enable_enable_string,\n\t\tNULL,\n\t},\n};\n\n/*\n * port in disable\n */\n\nstruct cmd_port_in_disable_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t port_string;\n\tcmdline_fixed_string_t in_string;\n\tuint32_t port_in_id;\n\tcmdline_fixed_string_t disable_string;\n};\n\nstatic void\ncmd_port_in_disable_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_port_in_disable_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_pipeline_port_in_disable(app,\n\t\t\tparams->pipeline_id,\n\t\t\tparams->port_in_id);\n\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n}\n\ncmdline_parse_token_string_t cmd_port_in_disable_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_port_in_disable_result, p_string,\n\t\t\"p\");\n\ncmdline_parse_token_num_t cmd_port_in_disable_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_port_in_disable_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_port_in_disable_port_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_port_in_disable_result, port_string,\n\t\t\"port\");\n\ncmdline_parse_token_string_t cmd_port_in_disable_in_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_port_in_disable_result, in_string,\n\t\t\"in\");\n\ncmdline_parse_token_num_t cmd_port_in_disable_port_in_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_port_in_disable_result, port_in_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_port_in_disable_disable_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_port_in_disable_result,\n\t\tdisable_string, \"disable\");\n\ncmdline_parse_inst_t cmd_port_in_disable = {\n\t.f = cmd_port_in_disable_parsed,\n\t.data = NULL,\n\t.help_str = \"Pipeline input port disable\",\n\t.tokens = {\n\t\t(void *) &cmd_port_in_disable_p_string,\n\t\t(void *) &cmd_port_in_disable_pipeline_id,\n\t\t(void *) &cmd_port_in_disable_port_string,\n\t\t(void *) &cmd_port_in_disable_in_string,\n\t\t(void *) &cmd_port_in_disable_port_in_id,\n\t\t(void *) &cmd_port_in_disable_disable_string,\n\t\tNULL,\n\t},\n};\n\n/*\n * link config\n */\n\nstatic void\nprint_link_info(struct app_link_params *p)\n{\n\tstruct rte_eth_stats stats;\n\tstruct ether_addr *mac_addr;\n\tuint32_t netmask = (~0) << (32 - p->depth);\n\tuint32_t host = p->ip & netmask;\n\tuint32_t bcast = host | (~netmask);\n\n\tmemset(&stats, 0, sizeof(stats));\n\trte_eth_stats_get(p->pmd_id, &stats);\n\n\tmac_addr = (struct ether_addr *) &p->mac_addr;\n\n\tprintf(\"%s: flags=<%s>\\n\",\n\t\tp->name,\n\t\t(p->state) ? \"UP\" : \"DOWN\");\n\n\tif (p->ip)\n\t\tprintf(\"\\tinet %\" PRIu32 \".%\" PRIu32\n\t\t\t\".%\" PRIu32 \".%\" PRIu32\n\t\t\t\" netmask %\" PRIu32 \".%\" PRIu32\n\t\t\t\".%\" PRIu32 \".%\" PRIu32 \" \"\n\t\t\t\"broadcast %\" PRIu32 \".%\" PRIu32\n\t\t\t\".%\" PRIu32 \".%\" PRIu32 \"\\n\",\n\t\t\t(p->ip >> 24) & 0xFF,\n\t\t\t(p->ip >> 16) & 0xFF,\n\t\t\t(p->ip >> 8) & 0xFF,\n\t\t\tp->ip & 0xFF,\n\t\t\t(netmask >> 24) & 0xFF,\n\t\t\t(netmask >> 16) & 0xFF,\n\t\t\t(netmask >> 8) & 0xFF,\n\t\t\tnetmask & 0xFF,\n\t\t\t(bcast >> 24) & 0xFF,\n\t\t\t(bcast >> 16) & 0xFF,\n\t\t\t(bcast >> 8) & 0xFF,\n\t\t\tbcast & 0xFF);\n\n\tprintf(\"\\tether %02\" PRIx32 \":%02\" PRIx32 \":%02\" PRIx32\n\t\t\":%02\" PRIx32 \":%02\" PRIx32 \":%02\" PRIx32 \"\\n\",\n\t\tmac_addr->addr_bytes[0],\n\t\tmac_addr->addr_bytes[1],\n\t\tmac_addr->addr_bytes[2],\n\t\tmac_addr->addr_bytes[3],\n\t\tmac_addr->addr_bytes[4],\n\t\tmac_addr->addr_bytes[5]);\n\n\tprintf(\"\\tRX packets %\" PRIu64\n\t\t\" bytes %\" PRIu64\n\t\t\"\\n\",\n\t\tstats.ipackets,\n\t\tstats.ibytes);\n\n\tprintf(\"\\tRX mcast %\" PRIu64\n\t\t\" fdirmatch %\" PRIu64\n\t\t\" fdirmiss %\" PRIu64\n\t\t\" lb-packets %\" PRIu64\n\t\t\" lb-bytes %\" PRIu64\n\t\t\" xon %\" PRIu64\n\t\t\" xoff %\" PRIu64 \"\\n\",\n\t\tstats.imcasts,\n\t\tstats.fdirmatch,\n\t\tstats.fdirmiss,\n\t\tstats.ilbpackets,\n\t\tstats.ilbbytes,\n\t\tstats.rx_pause_xon,\n\t\tstats.rx_pause_xoff);\n\n\tprintf(\"\\tRX errors %\" PRIu64\n\t\t\" missed %\" PRIu64\n\t\t\" badcrc %\" PRIu64\n\t\t\" badlen %\" PRIu64\n\t\t\" no-mbuf %\" PRIu64\n\t\t\"\\n\",\n\t\tstats.ierrors,\n\t\tstats.imissed,\n\t\tstats.ibadcrc,\n\t\tstats.ibadlen,\n\t\tstats.rx_nombuf);\n\n\tprintf(\"\\tTX packets %\" PRIu64\n\t\t\" bytes %\" PRIu64 \"\\n\",\n\t\tstats.opackets,\n\t\tstats.obytes);\n\n\tprintf(\"\\tTX lb-packets %\" PRIu64\n\t\t\" lb-bytes %\" PRIu64\n\t\t\" xon %\" PRIu64\n\t\t\" xoff %\" PRIu64\n\t\t\"\\n\",\n\t\tstats.olbpackets,\n\t\tstats.olbbytes,\n\t\tstats.tx_pause_xon,\n\t\tstats.tx_pause_xoff);\n\n\tprintf(\"\\tTX errors %\" PRIu64\n\t\t\"\\n\",\n\t\tstats.oerrors);\n\n\tprintf(\"\\n\");\n}\n\nstruct cmd_link_config_result {\n\tcmdline_fixed_string_t link_string;\n\tuint32_t link_id;\n\tcmdline_fixed_string_t config_string;\n\tcmdline_ipaddr_t ip;\n\tuint32_t depth;\n};\n\nstatic void\ncmd_link_config_parsed(\n\tvoid *parsed_result,\n\t__attribute__((unused)) struct cmdline *cl,\n\t void *data)\n{\n\tstruct cmd_link_config_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tuint32_t link_id = params->link_id;\n\tuint32_t ip = rte_bswap32((uint32_t) params->ip.addr.ipv4.s_addr);\n\tuint32_t depth = params->depth;\n\n\tstatus = app_link_config(app, link_id, ip, depth);\n\tif (status)\n\t\tprintf(\"Command failed\\n\");\n\telse {\n\t\tstruct app_link_params *p;\n\n\t\tAPP_PARAM_FIND_BY_ID(app->link_params, \"LINK\", link_id, p);\n\t\tprint_link_info(p);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_link_config_link_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_config_result, link_string,\n\t\t\"link\");\n\ncmdline_parse_token_num_t cmd_link_config_link_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_link_config_result, link_id, UINT32);\n\ncmdline_parse_token_string_t cmd_link_config_config_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_config_result, config_string,\n\t\t\"config\");\n\ncmdline_parse_token_ipaddr_t cmd_link_config_ip =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_link_config_result, ip);\n\ncmdline_parse_token_num_t cmd_link_config_depth =\n\tTOKEN_NUM_INITIALIZER(struct cmd_link_config_result, depth, UINT32);\n\ncmdline_parse_inst_t cmd_link_config = {\n\t.f = cmd_link_config_parsed,\n\t.data = NULL,\n\t.help_str = \"Link configuration\",\n\t.tokens = {\n\t\t(void *)&cmd_link_config_link_string,\n\t\t(void *)&cmd_link_config_link_id,\n\t\t(void *)&cmd_link_config_config_string,\n\t\t(void *)&cmd_link_config_ip,\n\t\t(void *)&cmd_link_config_depth,\n\t\tNULL,\n\t},\n};\n\n/*\n * link up\n */\n\nstruct cmd_link_up_result {\n\tcmdline_fixed_string_t link_string;\n\tuint32_t link_id;\n\tcmdline_fixed_string_t up_string;\n};\n\nstatic void\ncmd_link_up_parsed(\n\tvoid *parsed_result,\n\t__attribute__((unused)) struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_link_up_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_link_up(app, params->link_id);\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n\telse {\n\t\tstruct app_link_params *p;\n\n\t\tAPP_PARAM_FIND_BY_ID(app->link_params, \"LINK\", params->link_id,\n\t\t\tp);\n\t\tprint_link_info(p);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_link_up_link_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_up_result, link_string,\n\t\t\"link\");\n\ncmdline_parse_token_num_t cmd_link_up_link_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_link_up_result, link_id, UINT32);\n\ncmdline_parse_token_string_t cmd_link_up_up_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_up_result, up_string, \"up\");\n\ncmdline_parse_inst_t cmd_link_up = {\n\t.f = cmd_link_up_parsed,\n\t.data = NULL,\n\t.help_str = \"Link UP\",\n\t.tokens = {\n\t\t(void *)&cmd_link_up_link_string,\n\t\t(void *)&cmd_link_up_link_id,\n\t\t(void *)&cmd_link_up_up_string,\n\t\tNULL,\n\t},\n};\n\n/*\n * link down\n */\n\nstruct cmd_link_down_result {\n\tcmdline_fixed_string_t link_string;\n\tuint32_t link_id;\n\tcmdline_fixed_string_t down_string;\n};\n\nstatic void\ncmd_link_down_parsed(\n\tvoid *parsed_result,\n\t__attribute__((unused)) struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_link_down_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_link_down(app, params->link_id);\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n\telse {\n\t\tstruct app_link_params *p;\n\n\t\tAPP_PARAM_FIND_BY_ID(app->link_params, \"LINK\", params->link_id,\n\t\t\tp);\n\t\tprint_link_info(p);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_link_down_link_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_down_result, link_string,\n\t\t\"link\");\n\ncmdline_parse_token_num_t cmd_link_down_link_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_link_down_result, link_id, UINT32);\n\ncmdline_parse_token_string_t cmd_link_down_down_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_down_result, down_string,\n\t\t\"down\");\n\ncmdline_parse_inst_t cmd_link_down = {\n\t.f = cmd_link_down_parsed,\n\t.data = NULL,\n\t.help_str = \"Link DOWN\",\n\t.tokens = {\n\t\t(void *) &cmd_link_down_link_string,\n\t\t(void *) &cmd_link_down_link_id,\n\t\t(void *) &cmd_link_down_down_string,\n\t\tNULL,\n\t},\n};\n\n/*\n * link ls\n */\n\nstruct cmd_link_ls_result {\n\tcmdline_fixed_string_t link_string;\n\tcmdline_fixed_string_t ls_string;\n};\n\nstatic void\ncmd_link_ls_parsed(\n\t__attribute__((unused)) void *parsed_result,\n\t__attribute__((unused)) struct cmdline *cl,\n\t void *data)\n{\n\tstruct app_params *app = data;\n\tuint32_t link_id;\n\n\tfor (link_id = 0; link_id < app->n_links; link_id++) {\n\t\tstruct app_link_params *p;\n\n\t\tAPP_PARAM_FIND_BY_ID(app->link_params, \"LINK\", link_id, p);\n\t\tprint_link_info(p);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_link_ls_link_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_ls_result, link_string,\n\t\t\"link\");\n\ncmdline_parse_token_string_t cmd_link_ls_ls_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_link_ls_result, ls_string, \"ls\");\n\ncmdline_parse_inst_t cmd_link_ls = {\n\t.f = cmd_link_ls_parsed,\n\t.data = NULL,\n\t.help_str = \"Link list\",\n\t.tokens = {\n\t\t(void *)&cmd_link_ls_link_string,\n\t\t(void *)&cmd_link_ls_ls_string,\n\t\tNULL,\n\t},\n};\n\n/*\n * quit\n */\n\nstruct cmd_quit_result {\n\tcmdline_fixed_string_t quit;\n};\n\nstatic void\ncmd_quit_parsed(\n\t__rte_unused void *parsed_result,\n\tstruct cmdline *cl,\n\t__rte_unused void *data)\n{\n\tcmdline_quit(cl);\n}\n\nstatic cmdline_parse_token_string_t cmd_quit_quit =\n\tTOKEN_STRING_INITIALIZER(struct cmd_quit_result, quit, \"quit\");\n\nstatic cmdline_parse_inst_t cmd_quit = {\n\t.f = cmd_quit_parsed,\n\t.data = NULL,\n\t.help_str = \"Quit\",\n\t.tokens = {\n\t\t(void *) &cmd_quit_quit,\n\t\tNULL,\n\t},\n};\n\n/*\n * run\n */\n\nstatic void\napp_run_file(\n\tcmdline_parse_ctx_t *ctx,\n\tconst char *file_name)\n{\n\tstruct cmdline *file_cl;\n\tint fd;\n\n\tfd = open(file_name, O_RDONLY);\n\tif (fd < 0) {\n\t\tprintf(\"Cannot open file \\\"%s\\\"\\n\", file_name);\n\t\treturn;\n\t}\n\n\tfile_cl = cmdline_new(ctx, \"\", fd, 1);\n\tcmdline_interact(file_cl);\n\tclose(fd);\n}\n\nstruct cmd_run_file_result {\n\tcmdline_fixed_string_t run_string;\n\tchar file_name[APP_FILE_NAME_SIZE];\n};\n\nstatic void\ncmd_run_parsed(\n\tvoid *parsed_result,\n\tstruct cmdline *cl,\n\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_run_file_result *params = parsed_result;\n\n\tapp_run_file(cl->ctx, params->file_name);\n}\n\ncmdline_parse_token_string_t cmd_run_run_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_run_file_result, run_string,\n\t\t\"run\");\n\ncmdline_parse_token_string_t cmd_run_file_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_run_file_result, file_name, NULL);\n\ncmdline_parse_inst_t cmd_run = {\n\t.f = cmd_run_parsed,\n\t.data = NULL,\n\t.help_str = \"Run CLI script file\",\n\t.tokens = {\n\t\t(void *) &cmd_run_run_string,\n\t\t(void *) &cmd_run_file_name,\n\t\tNULL,\n\t},\n};\n\nstatic cmdline_parse_ctx_t pipeline_common_cmds[] = {\n\t(cmdline_parse_inst_t *) &cmd_quit,\n\t(cmdline_parse_inst_t *) &cmd_run,\n\n\t(cmdline_parse_inst_t *) &cmd_link_config,\n\t(cmdline_parse_inst_t *) &cmd_link_up,\n\t(cmdline_parse_inst_t *) &cmd_link_down,\n\t(cmdline_parse_inst_t *) &cmd_link_ls,\n\n\t(cmdline_parse_inst_t *) &cmd_ping,\n\t(cmdline_parse_inst_t *) &cmd_stats_port_in,\n\t(cmdline_parse_inst_t *) &cmd_stats_port_out,\n\t(cmdline_parse_inst_t *) &cmd_stats_table,\n\t(cmdline_parse_inst_t *) &cmd_port_in_enable,\n\t(cmdline_parse_inst_t *) &cmd_port_in_disable,\n\tNULL,\n};\n\nint\napp_pipeline_common_cmd_push(struct app_params *app)\n{\n\tuint32_t n_cmds, i;\n\n\t/* Check for available slots in the application commands array */\n\tn_cmds = RTE_DIM(pipeline_common_cmds) - 1;\n\tif (n_cmds > APP_MAX_CMDS - app->n_cmds)\n\t\treturn -ENOMEM;\n\n\t/* Push pipeline commands into the application */\n\tmemcpy(&app->cmds[app->n_cmds],\n\t\tpipeline_common_cmds,\n\t\tn_cmds * sizeof(cmdline_parse_ctx_t *));\n\n\tfor (i = 0; i < n_cmds; i++)\n\t\tapp->cmds[app->n_cmds + i]->data = app;\n\n\tapp->n_cmds += n_cmds;\n\tapp->cmds[app->n_cmds] = NULL;\n\n\treturn 0;\n}\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_common_fe.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_COMMON_FE_H__\n#define __INCLUDE_PIPELINE_COMMON_FE_H__\n\n#include \n#include \n#include \n#include \n\n#include \"pipeline_common_be.h\"\n#include \"pipeline.h\"\n#include \"app.h\"\n\n#ifndef MSG_TIMEOUT_DEFAULT\n#define MSG_TIMEOUT_DEFAULT 1000\n#endif\n\nstatic inline struct app_pipeline_data *\napp_pipeline_data(struct app_params *app, uint32_t id)\n{\n\tstruct app_pipeline_params *params;\n\n\tAPP_PARAM_FIND_BY_ID(app->pipeline_params, \"PIPELINE\", id, params);\n\tif (params == NULL)\n\t\treturn NULL;\n\n\treturn &app->pipeline_data[params - app->pipeline_params];\n}\n\nstatic inline void *\napp_pipeline_data_fe(struct app_params *app, uint32_t id)\n{\n\tstruct app_pipeline_data *pipeline_data;\n\n\tpipeline_data = app_pipeline_data(app, id);\n\tif (pipeline_data == NULL)\n\t\treturn NULL;\n\n\treturn pipeline_data->fe;\n}\n\nstatic inline struct rte_ring *\napp_pipeline_msgq_in_get(struct app_params *app,\n\tuint32_t pipeline_id)\n{\n\tstruct app_msgq_params *p;\n\n\tAPP_PARAM_FIND_BY_ID(app->msgq_params,\n\t\t\"MSGQ-REQ-PIPELINE\",\n\t\tpipeline_id,\n\t\tp);\n\tif (p == NULL)\n\t\treturn NULL;\n\n\treturn app->msgq[p - app->msgq_params];\n}\n\nstatic inline struct rte_ring *\napp_pipeline_msgq_out_get(struct app_params *app,\n\tuint32_t pipeline_id)\n{\n\tstruct app_msgq_params *p;\n\n\tAPP_PARAM_FIND_BY_ID(app->msgq_params,\n\t\t\"MSGQ-RSP-PIPELINE\",\n\t\tpipeline_id,\n\t\tp);\n\tif (p == NULL)\n\t\treturn NULL;\n\n\treturn app->msgq[p - app->msgq_params];\n}\n\nstatic inline void *\napp_msg_alloc(__rte_unused struct app_params *app)\n{\n\treturn rte_malloc(NULL, 2048, RTE_CACHE_LINE_SIZE);\n}\n\nstatic inline void\napp_msg_free(__rte_unused struct app_params *app,\n\tvoid *msg)\n{\n\trte_free(msg);\n}\n\nstatic inline void\napp_msg_send(struct app_params *app,\n\tuint32_t pipeline_id,\n\tvoid *msg)\n{\n\tstruct rte_ring *r = app_pipeline_msgq_in_get(app, pipeline_id);\n\tint status;\n\n\tdo {\n\t\tstatus = rte_ring_sp_enqueue(r, msg);\n\t} while (status == -ENOBUFS);\n}\n\nstatic inline void *\napp_msg_recv(struct app_params *app,\n\tuint32_t pipeline_id)\n{\n\tstruct rte_ring *r = app_pipeline_msgq_out_get(app, pipeline_id);\n\tvoid *msg;\n\tint status = rte_ring_sc_dequeue(r, &msg);\n\n\tif (status != 0)\n\t\treturn NULL;\n\n\treturn msg;\n}\n\nstatic inline void *\napp_msg_send_recv(struct app_params *app,\n\tuint32_t pipeline_id,\n\tvoid *msg,\n\tuint32_t timeout_ms)\n{\n\tstruct rte_ring *r_req = app_pipeline_msgq_in_get(app, pipeline_id);\n\tstruct rte_ring *r_rsp = app_pipeline_msgq_out_get(app, pipeline_id);\n\tuint64_t hz = rte_get_tsc_hz();\n\tvoid *msg_recv;\n\tuint64_t deadline;\n\tint status;\n\n\t/* send */\n\tdo {\n\t\tstatus = rte_ring_sp_enqueue(r_req, (void *) msg);\n\t} while (status == -ENOBUFS);\n\n\t/* recv */\n\tdeadline = (timeout_ms) ?\n\t\t(rte_rdtsc() + ((hz * timeout_ms) / 1000)) :\n\t\tUINT64_MAX;\n\n\tdo {\n\t\tif (rte_rdtsc() > deadline)\n\t\t\treturn NULL;\n\n\t\tstatus = rte_ring_sc_dequeue(r_rsp, &msg_recv);\n\t} while (status != 0);\n\n\treturn msg_recv;\n}\n\nint\napp_pipeline_ping(struct app_params *app,\n\tuint32_t pipeline_id);\n\nint\napp_pipeline_stats_port_in(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id,\n\tstruct rte_pipeline_port_in_stats *stats);\n\nint\napp_pipeline_stats_port_out(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id,\n\tstruct rte_pipeline_port_out_stats *stats);\n\nint\napp_pipeline_stats_table(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t table_id,\n\tstruct rte_pipeline_table_stats *stats);\n\nint\napp_pipeline_port_in_enable(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id);\n\nint\napp_pipeline_port_in_disable(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id);\n\nint\napp_link_config(struct app_params *app,\n\tuint32_t link_id,\n\tuint32_t ip,\n\tuint32_t depth);\n\nint\napp_link_up(struct app_params *app,\n\tuint32_t link_id);\n\nint\napp_link_down(struct app_params *app,\n\tuint32_t link_id);\n\nint\napp_pipeline_common_cmd_push(struct app_params *app);\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_firewall.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"app.h\"\n#include \"pipeline_common_fe.h\"\n#include \"pipeline_firewall.h\"\n\nstruct app_pipeline_firewall_rule {\n\tstruct pipeline_firewall_key key;\n\tint32_t priority;\n\tuint32_t port_id;\n\tvoid *entry_ptr;\n\n\tTAILQ_ENTRY(app_pipeline_firewall_rule) node;\n};\n\nstruct app_pipeline_firewall {\n\t/* parameters */\n\tuint32_t n_ports_in;\n\tuint32_t n_ports_out;\n\n\t/* rules */\n\tTAILQ_HEAD(, app_pipeline_firewall_rule) rules;\n\tuint32_t n_rules;\n\tuint32_t default_rule_present;\n\tuint32_t default_rule_port_id;\n\tvoid *default_rule_entry_ptr;\n};\n\nstatic void\nprint_firewall_ipv4_rule(struct app_pipeline_firewall_rule *rule)\n{\n\tprintf(\"Prio = %\" PRId32 \" (SA = %\" PRIu32 \".%\" PRIu32\n\t\t\".%\" PRIu32 \".%\" PRIu32 \"/%\" PRIu32 \", \"\n\t\t\"DA = %\" PRIu32 \".%\" PRIu32\n\t\t\".%\"PRIu32 \".%\" PRIu32 \"/%\" PRIu32 \", \"\n\t\t\"SP = %\" PRIu32 \"-%\" PRIu32 \", \"\n\t\t\"DP = %\" PRIu32 \"-%\" PRIu32 \", \"\n\t\t\"Proto = %\" PRIu32 \" / 0x%\" PRIx32 \") => \"\n\t\t\"Port = %\" PRIu32 \" (entry ptr = %p)\\n\",\n\n\t\trule->priority,\n\n\t\t(rule->key.key.ipv4_5tuple.src_ip >> 24) & 0xFF,\n\t\t(rule->key.key.ipv4_5tuple.src_ip >> 16) & 0xFF,\n\t\t(rule->key.key.ipv4_5tuple.src_ip >> 8) & 0xFF,\n\t\trule->key.key.ipv4_5tuple.src_ip & 0xFF,\n\t\trule->key.key.ipv4_5tuple.src_ip_mask,\n\n\t\t(rule->key.key.ipv4_5tuple.dst_ip >> 24) & 0xFF,\n\t\t(rule->key.key.ipv4_5tuple.dst_ip >> 16) & 0xFF,\n\t\t(rule->key.key.ipv4_5tuple.dst_ip >> 8) & 0xFF,\n\t\trule->key.key.ipv4_5tuple.dst_ip & 0xFF,\n\t\trule->key.key.ipv4_5tuple.dst_ip_mask,\n\n\t\trule->key.key.ipv4_5tuple.src_port_from,\n\t\trule->key.key.ipv4_5tuple.src_port_to,\n\n\t\trule->key.key.ipv4_5tuple.dst_port_from,\n\t\trule->key.key.ipv4_5tuple.dst_port_to,\n\n\t\trule->key.key.ipv4_5tuple.proto,\n\t\trule->key.key.ipv4_5tuple.proto_mask,\n\n\t\trule->port_id,\n\t\trule->entry_ptr);\n}\n\nstatic struct app_pipeline_firewall_rule *\napp_pipeline_firewall_rule_find(struct app_pipeline_firewall *p,\n\tstruct pipeline_firewall_key *key)\n{\n\tstruct app_pipeline_firewall_rule *r;\n\n\tTAILQ_FOREACH(r, &p->rules, node)\n\t\tif (memcmp(key,\n\t\t\t&r->key,\n\t\t\tsizeof(struct pipeline_firewall_key)) == 0)\n\t\t\treturn r;\n\n\treturn NULL;\n}\n\nstatic void\napp_pipeline_firewall_ls(\n\tstruct app_params *app,\n\tuint32_t pipeline_id)\n{\n\tstruct app_pipeline_firewall *p;\n\tstruct app_pipeline_firewall_rule *rule;\n\tuint32_t n_rules;\n\tint priority;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn;\n\n\tn_rules = p->n_rules;\n\tfor (priority = 0; n_rules; priority++)\n\t\tTAILQ_FOREACH(rule, &p->rules, node)\n\t\t\tif (rule->priority == priority) {\n\t\t\t\tprint_firewall_ipv4_rule(rule);\n\t\t\t\tn_rules--;\n\t\t\t}\n\n\tif (p->default_rule_present)\n\t\tprintf(\"Default rule: port %\" PRIu32 \" (entry ptr = %p)\\n\",\n\t\t\tp->default_rule_port_id,\n\t\t\tp->default_rule_entry_ptr);\n\telse\n\t\tprintf(\"Default rule: DROP\\n\");\n\n\tprintf(\"\\n\");\n}\n\nstatic void*\napp_pipeline_firewall_init(struct pipeline_params *params,\n\t__rte_unused void *arg)\n{\n\tstruct app_pipeline_firewall *p;\n\tuint32_t size;\n\n\t/* Check input arguments */\n\tif ((params == NULL) ||\n\t\t(params->n_ports_in == 0) ||\n\t\t(params->n_ports_out == 0))\n\t\treturn NULL;\n\n\t/* Memory allocation */\n\tsize = RTE_CACHE_LINE_ROUNDUP(sizeof(struct app_pipeline_firewall));\n\tp = rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE);\n\tif (p == NULL)\n\t\treturn NULL;\n\n\t/* Initialization */\n\tp->n_ports_in = params->n_ports_in;\n\tp->n_ports_out = params->n_ports_out;\n\n\tTAILQ_INIT(&p->rules);\n\tp->n_rules = 0;\n\tp->default_rule_present = 0;\n\tp->default_rule_port_id = 0;\n\tp->default_rule_entry_ptr = NULL;\n\n\treturn (void *) p;\n}\n\nstatic int\napp_pipeline_firewall_free(void *pipeline)\n{\n\tstruct app_pipeline_firewall *p = pipeline;\n\n\t/* Check input arguments */\n\tif (p == NULL)\n\t\treturn -1;\n\n\t/* Free resources */\n\twhile (!TAILQ_EMPTY(&p->rules)) {\n\t\tstruct app_pipeline_firewall_rule *rule;\n\n\t\trule = TAILQ_FIRST(&p->rules);\n\t\tTAILQ_REMOVE(&p->rules, rule, node);\n\t\trte_free(rule);\n\t}\n\n\trte_free(p);\n\treturn 0;\n}\n\nstatic int\napp_pipeline_firewall_key_check_and_normalize(struct pipeline_firewall_key *key)\n{\n\tswitch (key->type) {\n\tcase PIPELINE_FIREWALL_IPV4_5TUPLE:\n\t{\n\t\tuint32_t src_ip_depth = key->key.ipv4_5tuple.src_ip_mask;\n\t\tuint32_t dst_ip_depth = key->key.ipv4_5tuple.dst_ip_mask;\n\t\tuint16_t src_port_from = key->key.ipv4_5tuple.src_port_from;\n\t\tuint16_t src_port_to = key->key.ipv4_5tuple.src_port_to;\n\t\tuint16_t dst_port_from = key->key.ipv4_5tuple.dst_port_from;\n\t\tuint16_t dst_port_to = key->key.ipv4_5tuple.dst_port_to;\n\n\t\tuint32_t src_ip_netmask = 0;\n\t\tuint32_t dst_ip_netmask = 0;\n\n\t\tif ((src_ip_depth > 32) ||\n\t\t\t(dst_ip_depth > 32) ||\n\t\t\t(src_port_from > src_port_to) ||\n\t\t\t(dst_port_from > dst_port_to))\n\t\t\treturn -1;\n\n\t\tif (src_ip_depth)\n\t\t\tsrc_ip_netmask = (~0) << (32 - src_ip_depth);\n\n\t\tif (dst_ip_depth)\n\t\t\tdst_ip_netmask = ((~0) << (32 - dst_ip_depth));\n\n\t\tkey->key.ipv4_5tuple.src_ip &= src_ip_netmask;\n\t\tkey->key.ipv4_5tuple.dst_ip &= dst_ip_netmask;\n\n\t\treturn 0;\n\t}\n\n\tdefault:\n\t\treturn -1;\n\t}\n}\n\nint\napp_pipeline_firewall_add_rule(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_firewall_key *key,\n\tuint32_t priority,\n\tuint32_t port_id)\n{\n\tstruct app_pipeline_firewall *p;\n\tstruct app_pipeline_firewall_rule *rule;\n\tstruct pipeline_firewall_add_msg_req *req;\n\tstruct pipeline_firewall_add_msg_rsp *rsp;\n\tint new_rule;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(key == NULL) ||\n\t\t(key->type != PIPELINE_FIREWALL_IPV4_5TUPLE))\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tif (port_id >= p->n_ports_out)\n\t\treturn -1;\n\n\tif (app_pipeline_firewall_key_check_and_normalize(key) != 0)\n\t\treturn -1;\n\n\t/* Find existing rule or allocate new rule */\n\trule = app_pipeline_firewall_rule_find(p, key);\n\tnew_rule = (rule == NULL);\n\tif (rule == NULL) {\n\t\trule = rte_malloc(NULL, sizeof(*rule), RTE_CACHE_LINE_SIZE);\n\n\t\tif (rule == NULL)\n\t\t\treturn -1;\n\t}\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL) {\n\t\tif (new_rule)\n\t\t\trte_free(rule);\n\t\treturn -1;\n\t}\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_FIREWALL_MSG_REQ_ADD;\n\tmemcpy(&req->key, key, sizeof(*key));\n\treq->priority = priority;\n\treq->port_id = port_id;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL) {\n\t\tif (new_rule)\n\t\t\trte_free(rule);\n\t\treturn -1;\n\t}\n\n\t/* Read response and write rule */\n\tif (rsp->status ||\n\t\t(rsp->entry_ptr == NULL) ||\n\t\t((new_rule == 0) && (rsp->key_found == 0)) ||\n\t\t((new_rule == 1) && (rsp->key_found == 1))) {\n\t\tapp_msg_free(app, rsp);\n\t\tif (new_rule)\n\t\t\trte_free(rule);\n\t\treturn -1;\n\t}\n\n\tmemcpy(&rule->key, key, sizeof(*key));\n\trule->priority = priority;\n\trule->port_id = port_id;\n\trule->entry_ptr = rsp->entry_ptr;\n\n\t/* Commit rule */\n\tif (new_rule) {\n\t\tTAILQ_INSERT_TAIL(&p->rules, rule, node);\n\t\tp->n_rules++;\n\t}\n\n\tprint_firewall_ipv4_rule(rule);\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\nint\napp_pipeline_firewall_delete_rule(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_firewall_key *key)\n{\n\tstruct app_pipeline_firewall *p;\n\tstruct app_pipeline_firewall_rule *rule;\n\tstruct pipeline_firewall_del_msg_req *req;\n\tstruct pipeline_firewall_del_msg_rsp *rsp;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(key == NULL) ||\n\t\t(key->type != PIPELINE_FIREWALL_IPV4_5TUPLE))\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tif (app_pipeline_firewall_key_check_and_normalize(key) != 0)\n\t\treturn -1;\n\n\t/* Find rule */\n\trule = app_pipeline_firewall_rule_find(p, key);\n\tif (rule == NULL)\n\t\treturn 0;\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_FIREWALL_MSG_REQ_DEL;\n\tmemcpy(&req->key, key, sizeof(*key));\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Read response */\n\tif (rsp->status || !rsp->key_found) {\n\t\tapp_msg_free(app, rsp);\n\t\treturn -1;\n\t}\n\n\t/* Remove rule */\n\tTAILQ_REMOVE(&p->rules, rule, node);\n\tp->n_rules--;\n\trte_free(rule);\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\nint\napp_pipeline_firewall_add_default_rule(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id)\n{\n\tstruct app_pipeline_firewall *p;\n\tstruct pipeline_firewall_add_default_msg_req *req;\n\tstruct pipeline_firewall_add_default_msg_rsp *rsp;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tif (port_id >= p->n_ports_out)\n\t\treturn -1;\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_FIREWALL_MSG_REQ_ADD_DEFAULT;\n\treq->port_id = port_id;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Read response and write rule */\n\tif (rsp->status || (rsp->entry_ptr == NULL)) {\n\t\tapp_msg_free(app, rsp);\n\t\treturn -1;\n\t}\n\n\tp->default_rule_port_id = port_id;\n\tp->default_rule_entry_ptr = rsp->entry_ptr;\n\n\t/* Commit rule */\n\tp->default_rule_present = 1;\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\nint\napp_pipeline_firewall_delete_default_rule(struct app_params *app,\n\tuint32_t pipeline_id)\n{\n\tstruct app_pipeline_firewall *p;\n\tstruct pipeline_firewall_del_default_msg_req *req;\n\tstruct pipeline_firewall_del_default_msg_rsp *rsp;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_FIREWALL_MSG_REQ_DEL_DEFAULT;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Read response and write rule */\n\tif (rsp->status) {\n\t\tapp_msg_free(app, rsp);\n\t\treturn -1;\n\t}\n\n\t/* Commit rule */\n\tp->default_rule_present = 0;\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\n/*\n * p firewall add ipv4\n */\n\nstruct cmd_firewall_add_ipv4_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t firewall_string;\n\tcmdline_fixed_string_t add_string;\n\tcmdline_fixed_string_t ipv4_string;\n\tint32_t priority;\n\tcmdline_ipaddr_t src_ip;\n\tuint32_t src_ip_mask;\n\tcmdline_ipaddr_t dst_ip;\n\tuint32_t dst_ip_mask;\n\tuint16_t src_port_from;\n\tuint16_t src_port_to;\n\tuint16_t dst_port_from;\n\tuint16_t dst_port_to;\n\tuint8_t proto;\n\tuint8_t proto_mask;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_firewall_add_ipv4_parsed(\n\tvoid *parsed_result,\n\t__attribute__((unused)) struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_firewall_add_ipv4_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_firewall_key key;\n\tint status;\n\n\tkey.type = PIPELINE_FIREWALL_IPV4_5TUPLE;\n\tkey.key.ipv4_5tuple.src_ip = rte_bswap32(\n\t\t(uint32_t) params->src_ip.addr.ipv4.s_addr);\n\tkey.key.ipv4_5tuple.src_ip_mask = params->src_ip_mask;\n\tkey.key.ipv4_5tuple.dst_ip = rte_bswap32(\n\t\t(uint32_t) params->dst_ip.addr.ipv4.s_addr);\n\tkey.key.ipv4_5tuple.dst_ip_mask = params->dst_ip_mask;\n\tkey.key.ipv4_5tuple.src_port_from = params->src_port_from;\n\tkey.key.ipv4_5tuple.src_port_to = params->src_port_to;\n\tkey.key.ipv4_5tuple.dst_port_from = params->dst_port_from;\n\tkey.key.ipv4_5tuple.dst_port_to = params->dst_port_to;\n\tkey.key.ipv4_5tuple.proto = params->proto;\n\tkey.key.ipv4_5tuple.proto_mask = params->proto_mask;\n\n\tstatus = app_pipeline_firewall_add_rule(app,\n\t\tparams->pipeline_id,\n\t\t&key,\n\t\tparams->priority,\n\t\tparams->port_id);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\ncmdline_parse_token_string_t cmd_firewall_add_ipv4_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_add_ipv4_result, p_string,\n\t\t\"p\");\n\ncmdline_parse_token_num_t cmd_firewall_add_ipv4_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_ipv4_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_firewall_add_ipv4_firewall_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_add_ipv4_result,\n\t\tfirewall_string, \"firewall\");\n\ncmdline_parse_token_string_t cmd_firewall_add_ipv4_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_add_ipv4_result,\n\t\tadd_string, \"add\");\n\ncmdline_parse_token_string_t cmd_firewall_add_ipv4_ipv4_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_add_ipv4_result,\n\t\tipv4_string, \"ipv4\");\n\ncmdline_parse_token_num_t cmd_firewall_add_ipv4_priority =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_ipv4_result, priority,\n\t\tINT32);\n\ncmdline_parse_token_ipaddr_t cmd_firewall_add_ipv4_src_ip =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_firewall_add_ipv4_result, src_ip);\n\ncmdline_parse_token_num_t cmd_firewall_add_ipv4_src_ip_mask =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_ipv4_result, src_ip_mask,\n\t\tUINT32);\n\ncmdline_parse_token_ipaddr_t cmd_firewall_add_ipv4_dst_ip =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_firewall_add_ipv4_result, dst_ip);\n\ncmdline_parse_token_num_t cmd_firewall_add_ipv4_dst_ip_mask =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_ipv4_result, dst_ip_mask,\n\t\tUINT32);\n\ncmdline_parse_token_num_t cmd_firewall_add_ipv4_src_port_from =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_ipv4_result,\n\t\tsrc_port_from, UINT16);\n\ncmdline_parse_token_num_t cmd_firewall_add_ipv4_src_port_to =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_ipv4_result,\n\t\tsrc_port_to, UINT16);\n\ncmdline_parse_token_num_t cmd_firewall_add_ipv4_dst_port_from =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_ipv4_result,\n\t\tdst_port_from, UINT16);\n\ncmdline_parse_token_num_t cmd_firewall_add_ipv4_dst_port_to =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_ipv4_result,\n\t\tdst_port_to, UINT16);\n\ncmdline_parse_token_num_t cmd_firewall_add_ipv4_proto =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_ipv4_result,\n\t\tproto, UINT8);\n\ncmdline_parse_token_num_t cmd_firewall_add_ipv4_proto_mask =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_ipv4_result,\n\t\tproto_mask, UINT8);\n\ncmdline_parse_token_num_t cmd_firewall_add_ipv4_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_ipv4_result,\n\t\tport_id, UINT8);\n\ncmdline_parse_inst_t cmd_firewall_add_ipv4 = {\n\t.f = cmd_firewall_add_ipv4_parsed,\n\t.data = NULL,\n\t.help_str = \"Firewall rule add\",\n\t.tokens = {\n\t\t(void *) &cmd_firewall_add_ipv4_p_string,\n\t\t(void *) &cmd_firewall_add_ipv4_pipeline_id,\n\t\t(void *) &cmd_firewall_add_ipv4_firewall_string,\n\t\t(void *) &cmd_firewall_add_ipv4_add_string,\n\t\t(void *) &cmd_firewall_add_ipv4_ipv4_string,\n\t\t(void *) &cmd_firewall_add_ipv4_priority,\n\t\t(void *) &cmd_firewall_add_ipv4_src_ip,\n\t\t(void *) &cmd_firewall_add_ipv4_src_ip_mask,\n\t\t(void *) &cmd_firewall_add_ipv4_dst_ip,\n\t\t(void *) &cmd_firewall_add_ipv4_dst_ip_mask,\n\t\t(void *) &cmd_firewall_add_ipv4_src_port_from,\n\t\t(void *) &cmd_firewall_add_ipv4_src_port_to,\n\t\t(void *) &cmd_firewall_add_ipv4_dst_port_from,\n\t\t(void *) &cmd_firewall_add_ipv4_dst_port_to,\n\t\t(void *) &cmd_firewall_add_ipv4_proto,\n\t\t(void *) &cmd_firewall_add_ipv4_proto_mask,\n\t\t(void *) &cmd_firewall_add_ipv4_port_id,\n\t\tNULL,\n\t},\n};\n\n/*\n * p firewall del ipv4\n */\n\nstruct cmd_firewall_del_ipv4_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t firewall_string;\n\tcmdline_fixed_string_t del_string;\n\tcmdline_fixed_string_t ipv4_string;\n\tcmdline_ipaddr_t src_ip;\n\tuint32_t src_ip_mask;\n\tcmdline_ipaddr_t dst_ip;\n\tuint32_t dst_ip_mask;\n\tuint16_t src_port_from;\n\tuint16_t src_port_to;\n\tuint16_t dst_port_from;\n\tuint16_t dst_port_to;\n\tuint8_t proto;\n\tuint8_t proto_mask;\n};\n\nstatic void\ncmd_firewall_del_ipv4_parsed(\n\tvoid *parsed_result,\n\t__attribute__((unused)) struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_firewall_del_ipv4_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_firewall_key key;\n\tint status;\n\n\tkey.type = PIPELINE_FIREWALL_IPV4_5TUPLE;\n\tkey.key.ipv4_5tuple.src_ip = rte_bswap32(\n\t\t(uint32_t) params->src_ip.addr.ipv4.s_addr);\n\tkey.key.ipv4_5tuple.src_ip_mask = params->src_ip_mask;\n\tkey.key.ipv4_5tuple.dst_ip = rte_bswap32(\n\t\t(uint32_t) params->dst_ip.addr.ipv4.s_addr);\n\tkey.key.ipv4_5tuple.dst_ip_mask = params->dst_ip_mask;\n\tkey.key.ipv4_5tuple.src_port_from = params->src_port_from;\n\tkey.key.ipv4_5tuple.src_port_to = params->src_port_to;\n\tkey.key.ipv4_5tuple.dst_port_from = params->dst_port_from;\n\tkey.key.ipv4_5tuple.dst_port_to = params->dst_port_to;\n\tkey.key.ipv4_5tuple.proto = params->proto;\n\tkey.key.ipv4_5tuple.proto_mask = params->proto_mask;\n\n\tstatus = app_pipeline_firewall_delete_rule(app,\n\t\tparams->pipeline_id,\n\t\t&key);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\ncmdline_parse_token_string_t cmd_firewall_del_ipv4_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_del_ipv4_result, p_string,\n\t\t\"p\");\n\ncmdline_parse_token_num_t cmd_firewall_del_ipv4_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_del_ipv4_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_firewall_del_ipv4_firewall_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_del_ipv4_result,\n\t\tfirewall_string, \"firewall\");\n\ncmdline_parse_token_string_t cmd_firewall_del_ipv4_del_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_del_ipv4_result,\n\t\tdel_string, \"del\");\n\ncmdline_parse_token_string_t cmd_firewall_del_ipv4_ipv4_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_del_ipv4_result,\n\t\tipv4_string, \"ipv4\");\n\ncmdline_parse_token_ipaddr_t cmd_firewall_del_ipv4_src_ip =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_firewall_del_ipv4_result, src_ip);\n\ncmdline_parse_token_num_t cmd_firewall_del_ipv4_src_ip_mask =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_del_ipv4_result, src_ip_mask,\n\t\tUINT32);\n\ncmdline_parse_token_ipaddr_t cmd_firewall_del_ipv4_dst_ip =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_firewall_del_ipv4_result, dst_ip);\n\ncmdline_parse_token_num_t cmd_firewall_del_ipv4_dst_ip_mask =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_del_ipv4_result, dst_ip_mask,\n\t\tUINT32);\n\ncmdline_parse_token_num_t cmd_firewall_del_ipv4_src_port_from =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_del_ipv4_result,\n\t\tsrc_port_from, UINT16);\n\ncmdline_parse_token_num_t cmd_firewall_del_ipv4_src_port_to =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_del_ipv4_result, src_port_to,\n\t\tUINT16);\n\ncmdline_parse_token_num_t cmd_firewall_del_ipv4_dst_port_from =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_del_ipv4_result,\n\t\tdst_port_from, UINT16);\n\ncmdline_parse_token_num_t cmd_firewall_del_ipv4_dst_port_to =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_del_ipv4_result,\n\t\tdst_port_to, UINT16);\n\ncmdline_parse_token_num_t cmd_firewall_del_ipv4_proto =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_del_ipv4_result,\n\t\tproto, UINT8);\n\ncmdline_parse_token_num_t cmd_firewall_del_ipv4_proto_mask =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_del_ipv4_result, proto_mask,\n\t\tUINT8);\n\ncmdline_parse_inst_t cmd_firewall_del_ipv4 = {\n\t.f = cmd_firewall_del_ipv4_parsed,\n\t.data = NULL,\n\t.help_str = \"Firewall rule delete\",\n\t.tokens = {\n\t\t(void *) &cmd_firewall_del_ipv4_p_string,\n\t\t(void *) &cmd_firewall_del_ipv4_pipeline_id,\n\t\t(void *) &cmd_firewall_del_ipv4_firewall_string,\n\t\t(void *) &cmd_firewall_del_ipv4_del_string,\n\t\t(void *) &cmd_firewall_del_ipv4_ipv4_string,\n\t\t(void *) &cmd_firewall_del_ipv4_src_ip,\n\t\t(void *) &cmd_firewall_del_ipv4_src_ip_mask,\n\t\t(void *) &cmd_firewall_del_ipv4_dst_ip,\n\t\t(void *) &cmd_firewall_del_ipv4_dst_ip_mask,\n\t\t(void *) &cmd_firewall_del_ipv4_src_port_from,\n\t\t(void *) &cmd_firewall_del_ipv4_src_port_to,\n\t\t(void *) &cmd_firewall_del_ipv4_dst_port_from,\n\t\t(void *) &cmd_firewall_del_ipv4_dst_port_to,\n\t\t(void *) &cmd_firewall_del_ipv4_proto,\n\t\t(void *) &cmd_firewall_del_ipv4_proto_mask,\n\t\tNULL,\n\t},\n};\n\n/*\n * p firewall add default\n */\nstruct cmd_firewall_add_default_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t firewall_string;\n\tcmdline_fixed_string_t add_string;\n\tcmdline_fixed_string_t default_string;\n\tuint8_t port_id;\n};\n\nstatic void\ncmd_firewall_add_default_parsed(\n\tvoid *parsed_result,\n\t__attribute__((unused)) struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_firewall_add_default_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_pipeline_firewall_add_default_rule(app,\n\t\tparams->pipeline_id,\n\t\tparams->port_id);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\ncmdline_parse_token_string_t cmd_firewall_add_default_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_add_default_result,\n\t\tp_string, \"p\");\n\ncmdline_parse_token_num_t cmd_firewall_add_default_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_default_result,\n\t\tpipeline_id, UINT32);\n\ncmdline_parse_token_string_t cmd_firewall_add_default_firewall_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_add_default_result,\n\tfirewall_string, \"firewall\");\n\ncmdline_parse_token_string_t cmd_firewall_add_default_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_add_default_result,\n\tadd_string, \"add\");\n\ncmdline_parse_token_string_t cmd_firewall_add_default_default_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_add_default_result,\n\t\tdefault_string, \"default\");\n\ncmdline_parse_token_num_t cmd_firewall_add_default_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_add_default_result, port_id,\n\t\tUINT8);\n\ncmdline_parse_inst_t cmd_firewall_add_default = {\n\t.f = cmd_firewall_add_default_parsed,\n\t.data = NULL,\n\t.help_str = \"Firewall default rule add\",\n\t.tokens = {\n\t\t(void *) &cmd_firewall_add_default_p_string,\n\t\t(void *) &cmd_firewall_add_default_pipeline_id,\n\t\t(void *) &cmd_firewall_add_default_firewall_string,\n\t\t(void *) &cmd_firewall_add_default_add_string,\n\t\t(void *) &cmd_firewall_add_default_default_string,\n\t\t(void *) &cmd_firewall_add_default_port_id,\n\t\tNULL,\n\t},\n};\n\n/*\n * p firewall del default\n */\nstruct cmd_firewall_del_default_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t firewall_string;\n\tcmdline_fixed_string_t del_string;\n\tcmdline_fixed_string_t default_string;\n};\n\nstatic void\ncmd_firewall_del_default_parsed(\n\tvoid *parsed_result,\n\t__attribute__((unused)) struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_firewall_del_default_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_pipeline_firewall_delete_default_rule(app,\n\t\tparams->pipeline_id);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\ncmdline_parse_token_string_t cmd_firewall_del_default_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_del_default_result,\n\t\tp_string, \"p\");\n\ncmdline_parse_token_num_t cmd_firewall_del_default_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_del_default_result,\n\t\tpipeline_id, UINT32);\n\ncmdline_parse_token_string_t cmd_firewall_del_default_firewall_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_del_default_result,\n\tfirewall_string, \"firewall\");\n\ncmdline_parse_token_string_t cmd_firewall_del_default_del_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_del_default_result,\n\t\tdel_string, \"del\");\n\ncmdline_parse_token_string_t cmd_firewall_del_default_default_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_del_default_result,\n\t\tdefault_string, \"default\");\n\ncmdline_parse_inst_t cmd_firewall_del_default = {\n\t.f = cmd_firewall_del_default_parsed,\n\t.data = NULL,\n\t.help_str = \"Firewall default rule delete\",\n\t.tokens = {\n\t\t(void *) &cmd_firewall_del_default_p_string,\n\t\t(void *) &cmd_firewall_del_default_pipeline_id,\n\t\t(void *) &cmd_firewall_del_default_firewall_string,\n\t\t(void *) &cmd_firewall_del_default_del_string,\n\t\t(void *) &cmd_firewall_del_default_default_string,\n\t\tNULL,\n\t},\n};\n\n/*\n * p firewall ls\n */\n\nstruct cmd_firewall_ls_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t firewall_string;\n\tcmdline_fixed_string_t ls_string;\n};\n\nstatic void\ncmd_firewall_ls_parsed(\n\tvoid *parsed_result,\n\t__attribute__((unused)) struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_firewall_ls_result *params = parsed_result;\n\tstruct app_params *app = data;\n\n\tapp_pipeline_firewall_ls(app, params->pipeline_id);\n}\n\ncmdline_parse_token_string_t cmd_firewall_ls_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_ls_result, p_string,\n\t\t\"p\");\n\ncmdline_parse_token_num_t cmd_firewall_ls_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_firewall_ls_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_firewall_ls_firewall_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_ls_result,\n\tfirewall_string, \"firewall\");\n\ncmdline_parse_token_string_t cmd_firewall_ls_ls_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_firewall_ls_result, ls_string,\n\t\"ls\");\n\ncmdline_parse_inst_t cmd_firewall_ls = {\n\t.f = cmd_firewall_ls_parsed,\n\t.data = NULL,\n\t.help_str = \"Firewall rule list\",\n\t.tokens = {\n\t\t(void *) &cmd_firewall_ls_p_string,\n\t\t(void *) &cmd_firewall_ls_pipeline_id,\n\t\t(void *) &cmd_firewall_ls_firewall_string,\n\t\t(void *) &cmd_firewall_ls_ls_string,\n\t\tNULL,\n\t},\n};\n\nstatic cmdline_parse_ctx_t pipeline_cmds[] = {\n\t(cmdline_parse_inst_t *) &cmd_firewall_add_ipv4,\n\t(cmdline_parse_inst_t *) &cmd_firewall_del_ipv4,\n\t(cmdline_parse_inst_t *) &cmd_firewall_add_default,\n\t(cmdline_parse_inst_t *) &cmd_firewall_del_default,\n\t(cmdline_parse_inst_t *) &cmd_firewall_ls,\n\tNULL,\n};\n\nstatic struct pipeline_fe_ops pipeline_firewall_fe_ops = {\n\t.f_init = app_pipeline_firewall_init,\n\t.f_free = app_pipeline_firewall_free,\n\t.cmds = pipeline_cmds,\n};\n\nstruct pipeline_type pipeline_firewall = {\n\t.name = \"FIREWALL\",\n\t.be_ops = &pipeline_firewall_be_ops,\n\t.fe_ops = &pipeline_firewall_fe_ops,\n};\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_firewall.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_FIREWALL_H__\n#define __INCLUDE_PIPELINE_FIREWALL_H__\n\n#include \"pipeline.h\"\n#include \"pipeline_firewall_be.h\"\n\nint\napp_pipeline_firewall_add_rule(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_firewall_key *key,\n\tuint32_t priority,\n\tuint32_t port_id);\n\nint\napp_pipeline_firewall_delete_rule(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_firewall_key *key);\n\nint\napp_pipeline_firewall_add_default_rule(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id);\n\nint\napp_pipeline_firewall_delete_default_rule(struct app_params *app,\n\tuint32_t pipeline_id);\n\nextern struct pipeline_type pipeline_firewall;\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_firewall_be.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"pipeline_firewall_be.h\"\n\nstruct pipeline_firewall {\n\tstruct pipeline p;\n\tpipeline_msg_req_handler custom_handlers[PIPELINE_FIREWALL_MSG_REQS];\n\n\tuint32_t n_rules;\n\tuint32_t n_rule_fields;\n\tstruct rte_acl_field_def *field_format;\n\tuint32_t field_format_size;\n} __rte_cache_aligned;\n\nstatic void *\npipeline_firewall_msg_req_custom_handler(struct pipeline *p, void *msg);\n\nstatic pipeline_msg_req_handler handlers[] = {\n\t[PIPELINE_MSG_REQ_PING] =\n\t\tpipeline_msg_req_ping_handler,\n\t[PIPELINE_MSG_REQ_STATS_PORT_IN] =\n\t\tpipeline_msg_req_stats_port_in_handler,\n\t[PIPELINE_MSG_REQ_STATS_PORT_OUT] =\n\t\tpipeline_msg_req_stats_port_out_handler,\n\t[PIPELINE_MSG_REQ_STATS_TABLE] =\n\t\tpipeline_msg_req_stats_table_handler,\n\t[PIPELINE_MSG_REQ_PORT_IN_ENABLE] =\n\t\tpipeline_msg_req_port_in_enable_handler,\n\t[PIPELINE_MSG_REQ_PORT_IN_DISABLE] =\n\t\tpipeline_msg_req_port_in_disable_handler,\n\t[PIPELINE_MSG_REQ_CUSTOM] =\n\t\tpipeline_firewall_msg_req_custom_handler,\n};\n\nstatic void *\npipeline_firewall_msg_req_add_handler(struct pipeline *p, void *msg);\n\nstatic void *\npipeline_firewall_msg_req_del_handler(struct pipeline *p, void *msg);\n\nstatic void *\npipeline_firewall_msg_req_add_default_handler(struct pipeline *p, void *msg);\n\nstatic void *\npipeline_firewall_msg_req_del_default_handler(struct pipeline *p, void *msg);\n\nstatic pipeline_msg_req_handler custom_handlers[] = {\n\t[PIPELINE_FIREWALL_MSG_REQ_ADD] =\n\t\tpipeline_firewall_msg_req_add_handler,\n\t[PIPELINE_FIREWALL_MSG_REQ_DEL] =\n\t\tpipeline_firewall_msg_req_del_handler,\n\t[PIPELINE_FIREWALL_MSG_REQ_ADD_DEFAULT] =\n\t\tpipeline_firewall_msg_req_add_default_handler,\n\t[PIPELINE_FIREWALL_MSG_REQ_DEL_DEFAULT] =\n\t\tpipeline_firewall_msg_req_del_default_handler,\n};\n\n/*\n * Firewall table\n */\nstruct firewall_table_entry {\n\tstruct rte_pipeline_table_entry head;\n};\n\nstatic struct rte_acl_field_def field_format_ipv4[] = {\n\t/* Protocol */\n\t[0] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t.size = sizeof(uint8_t),\n\t\t.field_index = 0,\n\t\t.input_index = 0,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\toffsetof(struct ipv4_hdr, next_proto_id),\n\t},\n\n\t/* Source IP address (IPv4) */\n\t[1] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = 1,\n\t\t.input_index = 1,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\toffsetof(struct ipv4_hdr, src_addr),\n\t},\n\n\t/* Destination IP address (IPv4) */\n\t[2] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = 2,\n\t\t.input_index = 2,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\toffsetof(struct ipv4_hdr, dst_addr),\n\t},\n\n\t/* Source Port */\n\t[3] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = 3,\n\t\t.input_index = 3,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\tsizeof(struct ipv4_hdr) +\n\t\t\toffsetof(struct tcp_hdr, src_port),\n\t},\n\n\t/* Destination Port */\n\t[4] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = 4,\n\t\t.input_index = 4,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\tsizeof(struct ipv4_hdr) +\n\t\t\toffsetof(struct tcp_hdr, dst_port),\n\t},\n};\n\n#define SIZEOF_VLAN_HDR 4\n\nstatic struct rte_acl_field_def field_format_vlan_ipv4[] = {\n\t/* Protocol */\n\t[0] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t.size = sizeof(uint8_t),\n\t\t.field_index = 0,\n\t\t.input_index = 0,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\tSIZEOF_VLAN_HDR +\n\t\t\toffsetof(struct ipv4_hdr, next_proto_id),\n\t},\n\n\t/* Source IP address (IPv4) */\n\t[1] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = 1,\n\t\t.input_index = 1,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\tSIZEOF_VLAN_HDR +\n\t\t\toffsetof(struct ipv4_hdr, src_addr),\n\t},\n\n\t/* Destination IP address (IPv4) */\n\t[2] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = 2,\n\t\t.input_index = 2,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\tSIZEOF_VLAN_HDR +\n\t\t\toffsetof(struct ipv4_hdr, dst_addr),\n\t},\n\n\t/* Source Port */\n\t[3] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = 3,\n\t\t.input_index = 3,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\tSIZEOF_VLAN_HDR +\n\t\t\tsizeof(struct ipv4_hdr) +\n\t\t\toffsetof(struct tcp_hdr, src_port),\n\t},\n\n\t/* Destination Port */\n\t[4] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = 4,\n\t\t.input_index = 4,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\tSIZEOF_VLAN_HDR +\n\t\t\tsizeof(struct ipv4_hdr) +\n\t\t\toffsetof(struct tcp_hdr, dst_port),\n\t},\n};\n\n#define SIZEOF_QINQ_HEADER 8\n\nstatic struct rte_acl_field_def field_format_qinq_ipv4[] = {\n\t/* Protocol */\n\t[0] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t.size = sizeof(uint8_t),\n\t\t.field_index = 0,\n\t\t.input_index = 0,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\tSIZEOF_QINQ_HEADER +\n\t\t\toffsetof(struct ipv4_hdr, next_proto_id),\n\t},\n\n\t/* Source IP address (IPv4) */\n\t[1] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = 1,\n\t\t.input_index = 1,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\tSIZEOF_QINQ_HEADER +\n\t\t\toffsetof(struct ipv4_hdr, src_addr),\n\t},\n\n\t/* Destination IP address (IPv4) */\n\t[2] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = 2,\n\t\t.input_index = 2,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\tSIZEOF_QINQ_HEADER +\n\t\t\toffsetof(struct ipv4_hdr, dst_addr),\n\t},\n\n\t/* Source Port */\n\t[3] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = 3,\n\t\t.input_index = 3,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\tSIZEOF_QINQ_HEADER +\n\t\t\tsizeof(struct ipv4_hdr) +\n\t\t\toffsetof(struct tcp_hdr, src_port),\n\t},\n\n\t/* Destination Port */\n\t[4] = {\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = 4,\n\t\t.input_index = 4,\n\t\t.offset = sizeof(struct ether_hdr) +\n\t\t\tSIZEOF_QINQ_HEADER +\n\t\t\tsizeof(struct ipv4_hdr) +\n\t\t\toffsetof(struct tcp_hdr, dst_port),\n\t},\n};\n\nstatic int\npipeline_firewall_parse_args(struct pipeline_firewall *p,\n\tstruct pipeline_params *params)\n{\n\tuint32_t n_rules_present = 0;\n\tuint32_t pkt_type_present = 0;\n\tuint32_t i;\n\n\t/* defaults */\n\tp->n_rules = 4 * 1024;\n\tp->n_rule_fields = RTE_DIM(field_format_ipv4);\n\tp->field_format = field_format_ipv4;\n\tp->field_format_size = sizeof(field_format_ipv4);\n\n\tfor (i = 0; i < params->n_args; i++) {\n\t\tchar *arg_name = params->args_name[i];\n\t\tchar *arg_value = params->args_value[i];\n\n\t\tif (strcmp(arg_name, \"n_rules\") == 0) {\n\t\t\tif (n_rules_present)\n\t\t\t\treturn -1;\n\t\t\tn_rules_present = 1;\n\n\t\t\tp->n_rules = atoi(arg_value);\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (strcmp(arg_name, \"pkt_type\") == 0) {\n\t\t\tif (pkt_type_present)\n\t\t\t\treturn -1;\n\t\t\tpkt_type_present = 1;\n\n\t\t\t/* ipv4 */\n\t\t\tif (strcmp(arg_value, \"ipv4\") == 0) {\n\t\t\t\tp->n_rule_fields = RTE_DIM(field_format_ipv4);\n\t\t\t\tp->field_format = field_format_ipv4;\n\t\t\t\tp->field_format_size =\n\t\t\t\t\tsizeof(field_format_ipv4);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/* vlan_ipv4 */\n\t\t\tif (strcmp(arg_value, \"vlan_ipv4\") == 0) {\n\t\t\t\tp->n_rule_fields =\n\t\t\t\t\tRTE_DIM(field_format_vlan_ipv4);\n\t\t\t\tp->field_format = field_format_vlan_ipv4;\n\t\t\t\tp->field_format_size =\n\t\t\t\t\tsizeof(field_format_vlan_ipv4);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/* qinq_ipv4 */\n\t\t\tif (strcmp(arg_value, \"qinq_ipv4\") == 0) {\n\t\t\t\tp->n_rule_fields =\n\t\t\t\t\tRTE_DIM(field_format_qinq_ipv4);\n\t\t\t\tp->field_format = field_format_qinq_ipv4;\n\t\t\t\tp->field_format_size =\n\t\t\t\t\tsizeof(field_format_qinq_ipv4);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/* other */\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* other */\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic void *\npipeline_firewall_init(struct pipeline_params *params,\n\t__rte_unused void *arg)\n{\n\tstruct pipeline *p;\n\tstruct pipeline_firewall *p_fw;\n\tuint32_t size, i;\n\n\t/* Check input arguments */\n\tif ((params == NULL) ||\n\t\t(params->n_ports_in == 0) ||\n\t\t(params->n_ports_out == 0))\n\t\treturn NULL;\n\n\t/* Memory allocation */\n\tsize = RTE_CACHE_LINE_ROUNDUP(sizeof(struct pipeline_firewall));\n\tp = rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE);\n\tp_fw = (struct pipeline_firewall *) p;\n\tif (p == NULL)\n\t\treturn NULL;\n\n\tstrcpy(p->name, params->name);\n\tp->log_level = params->log_level;\n\n\tPLOG(p, HIGH, \"Firewall\");\n\n\t/* Parse arguments */\n\tif (pipeline_firewall_parse_args(p_fw, params))\n\t\treturn NULL;\n\n\t/* Pipeline */\n\t{\n\t\tstruct rte_pipeline_params pipeline_params = {\n\t\t\t.name = params->name,\n\t\t\t.socket_id = params->socket_id,\n\t\t\t.offset_port_id = 0,\n\t\t};\n\n\t\tp->p = rte_pipeline_create(&pipeline_params);\n\t\tif (p->p == NULL) {\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Input ports */\n\tp->n_ports_in = params->n_ports_in;\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tstruct rte_pipeline_port_in_params port_params = {\n\t\t\t.ops = pipeline_port_in_params_get_ops(\n\t\t\t\t¶ms->port_in[i]),\n\t\t\t.arg_create = pipeline_port_in_params_convert(\n\t\t\t\t¶ms->port_in[i]),\n\t\t\t.f_action = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.burst_size = params->port_in[i].burst_size,\n\t\t};\n\n\t\tint status = rte_pipeline_port_in_create(p->p,\n\t\t\t&port_params,\n\t\t\t&p->port_in_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Output ports */\n\tp->n_ports_out = params->n_ports_out;\n\tfor (i = 0; i < p->n_ports_out; i++) {\n\t\tstruct rte_pipeline_port_out_params port_params = {\n\t\t\t.ops = pipeline_port_out_params_get_ops(\n\t\t\t\t¶ms->port_out[i]),\n\t\t\t.arg_create = pipeline_port_out_params_convert(\n\t\t\t\t¶ms->port_out[i]),\n\t\t\t.f_action = NULL,\n\t\t\t.f_action_bulk = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t};\n\n\t\tint status = rte_pipeline_port_out_create(p->p,\n\t\t\t&port_params,\n\t\t\t&p->port_out_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Tables */\n\tp->n_tables = 1;\n\t{\n\t\tstruct rte_table_acl_params table_acl_params = {\n\t\t\t.name = params->name,\n\t\t\t.n_rules = p_fw->n_rules,\n\t\t\t.n_rule_fields = p_fw->n_rule_fields,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t\t.ops = &rte_table_acl_ops,\n\t\t\t\t.arg_create = &table_acl_params,\n\t\t\t\t.f_action_hit = NULL,\n\t\t\t\t.f_action_miss = NULL,\n\t\t\t\t.arg_ah = NULL,\n\t\t\t\t.action_data_size =\n\t\t\t\t\tsizeof(struct firewall_table_entry) -\n\t\t\t\t\tsizeof(struct rte_pipeline_table_entry),\n\t\t\t};\n\n\t\tint status;\n\n\t\tmemcpy(table_acl_params.field_format,\n\t\t\tp_fw->field_format,\n\t\t\tp_fw->field_format_size);\n\n\t\tstatus = rte_pipeline_table_create(p->p,\n\t\t\t&table_params,\n\t\t\t&p->table_id[0]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Connecting input ports to tables */\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tint status = rte_pipeline_port_in_connect_to_table(p->p,\n\t\t\tp->port_in_id[i],\n\t\t\tp->table_id[0]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Enable input ports */\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tint status = rte_pipeline_port_in_enable(p->p,\n\t\t\tp->port_in_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Check pipeline consistency */\n\tif (rte_pipeline_check(p->p) < 0) {\n\t\trte_pipeline_free(p->p);\n\t\trte_free(p);\n\t\treturn NULL;\n\t}\n\n\t/* Message queues */\n\tp->n_msgq = params->n_msgq;\n\tfor (i = 0; i < p->n_msgq; i++)\n\t\tp->msgq_in[i] = params->msgq_in[i];\n\tfor (i = 0; i < p->n_msgq; i++)\n\t\tp->msgq_out[i] = params->msgq_out[i];\n\n\t/* Message handlers */\n\tmemcpy(p->handlers, handlers, sizeof(p->handlers));\n\tmemcpy(p_fw->custom_handlers,\n\t\tcustom_handlers,\n\t\tsizeof(p_fw->custom_handlers));\n\n\treturn p;\n}\n\nstatic int\npipeline_firewall_free(void *pipeline)\n{\n\tstruct pipeline *p = (struct pipeline *) pipeline;\n\n\t/* Check input arguments */\n\tif (p == NULL)\n\t\treturn -1;\n\n\t/* Free resources */\n\trte_pipeline_free(p->p);\n\trte_free(p);\n\treturn 0;\n}\n\nstatic int\npipeline_firewall_track(void *pipeline,\n\t__rte_unused uint32_t port_in,\n\tuint32_t *port_out)\n{\n\tstruct pipeline *p = (struct pipeline *) pipeline;\n\n\t/* Check input arguments */\n\tif ((p == NULL) ||\n\t\t(port_in >= p->n_ports_in) ||\n\t\t(port_out == NULL))\n\t\treturn -1;\n\n\tif (p->n_ports_in == 1) {\n\t\t*port_out = 0;\n\t\treturn 0;\n\t}\n\n\treturn -1;\n}\n\nstatic int\npipeline_firewall_timer(void *pipeline)\n{\n\tstruct pipeline *p = (struct pipeline *) pipeline;\n\n\tpipeline_msg_req_handle(p);\n\trte_pipeline_flush(p->p);\n\n\treturn 0;\n}\n\nvoid *\npipeline_firewall_msg_req_custom_handler(struct pipeline *p,\n\tvoid *msg)\n{\n\tstruct pipeline_firewall *p_fw = (struct pipeline_firewall *) p;\n\tstruct pipeline_custom_msg_req *req = msg;\n\tpipeline_msg_req_handler f_handle;\n\n\tf_handle = (req->subtype < PIPELINE_FIREWALL_MSG_REQS) ?\n\t\tp_fw->custom_handlers[req->subtype] :\n\t\tpipeline_msg_req_invalid_handler;\n\n\tif (f_handle == NULL)\n\t\tf_handle = pipeline_msg_req_invalid_handler;\n\n\treturn f_handle(p, req);\n}\n\nvoid *\npipeline_firewall_msg_req_add_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_firewall_add_msg_req *req = msg;\n\tstruct pipeline_firewall_add_msg_rsp *rsp = msg;\n\n\tstruct rte_table_acl_rule_add_params params;\n\tstruct firewall_table_entry entry = {\n\t\t.head = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = p->port_out_id[req->port_id]},\n\t\t},\n\t};\n\n\tmemset(¶ms, 0, sizeof(params));\n\n\tswitch (req->key.type) {\n\tcase PIPELINE_FIREWALL_IPV4_5TUPLE:\n\t\tparams.priority = req->priority;\n\t\tparams.field_value[0].value.u8 =\n\t\t\treq->key.key.ipv4_5tuple.proto;\n\t\tparams.field_value[0].mask_range.u8 =\n\t\t\treq->key.key.ipv4_5tuple.proto_mask;\n\t\tparams.field_value[1].value.u32 =\n\t\t\treq->key.key.ipv4_5tuple.src_ip;\n\t\tparams.field_value[1].mask_range.u32 =\n\t\t\treq->key.key.ipv4_5tuple.src_ip_mask;\n\t\tparams.field_value[2].value.u32 =\n\t\t\treq->key.key.ipv4_5tuple.dst_ip;\n\t\tparams.field_value[2].mask_range.u32 =\n\t\t\treq->key.key.ipv4_5tuple.dst_ip_mask;\n\t\tparams.field_value[3].value.u16 =\n\t\t\treq->key.key.ipv4_5tuple.src_port_from;\n\t\tparams.field_value[3].mask_range.u16 =\n\t\t\treq->key.key.ipv4_5tuple.src_port_to;\n\t\tparams.field_value[4].value.u16 =\n\t\t\treq->key.key.ipv4_5tuple.dst_port_from;\n\t\tparams.field_value[4].mask_range.u16 =\n\t\t\treq->key.key.ipv4_5tuple.dst_port_to;\n\t\tbreak;\n\n\tdefault:\n\t\trsp->status = -1; /* Error */\n\t\treturn rsp;\n\t}\n\n\trsp->status = rte_pipeline_table_entry_add(p->p,\n\t\tp->table_id[0],\n\t\t¶ms,\n\t\t(struct rte_pipeline_table_entry *) &entry,\n\t\t&rsp->key_found,\n\t\t(struct rte_pipeline_table_entry **) &rsp->entry_ptr);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_firewall_msg_req_del_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_firewall_del_msg_req *req = msg;\n\tstruct pipeline_firewall_del_msg_rsp *rsp = msg;\n\n\tstruct rte_table_acl_rule_delete_params params;\n\n\tmemset(¶ms, 0, sizeof(params));\n\n\tswitch (req->key.type) {\n\tcase PIPELINE_FIREWALL_IPV4_5TUPLE:\n\t\tparams.field_value[0].value.u8 =\n\t\t\treq->key.key.ipv4_5tuple.proto;\n\t\tparams.field_value[0].mask_range.u8 =\n\t\t\treq->key.key.ipv4_5tuple.proto_mask;\n\t\tparams.field_value[1].value.u32 =\n\t\t\treq->key.key.ipv4_5tuple.src_ip;\n\t\tparams.field_value[1].mask_range.u32 =\n\t\t\treq->key.key.ipv4_5tuple.src_ip_mask;\n\t\tparams.field_value[2].value.u32 =\n\t\t\treq->key.key.ipv4_5tuple.dst_ip;\n\t\tparams.field_value[2].mask_range.u32 =\n\t\t\treq->key.key.ipv4_5tuple.dst_ip_mask;\n\t\tparams.field_value[3].value.u16 =\n\t\t\treq->key.key.ipv4_5tuple.src_port_from;\n\t\tparams.field_value[3].mask_range.u16 =\n\t\t\treq->key.key.ipv4_5tuple.src_port_to;\n\t\tparams.field_value[4].value.u16 =\n\t\t\treq->key.key.ipv4_5tuple.dst_port_from;\n\t\tparams.field_value[4].mask_range.u16 =\n\t\t\treq->key.key.ipv4_5tuple.dst_port_to;\n\t\tbreak;\n\n\tdefault:\n\t\trsp->status = -1; /* Error */\n\t\treturn rsp;\n\t}\n\n\trsp->status = rte_pipeline_table_entry_delete(p->p,\n\t\tp->table_id[0],\n\t\t¶ms,\n\t\t&rsp->key_found,\n\t\tNULL);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_firewall_msg_req_add_default_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_firewall_add_default_msg_req *req = msg;\n\tstruct pipeline_firewall_add_default_msg_rsp *rsp = msg;\n\n\tstruct firewall_table_entry default_entry = {\n\t\t.head = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = p->port_out_id[req->port_id]},\n\t\t},\n\t};\n\n\trsp->status = rte_pipeline_table_default_entry_add(p->p,\n\t\tp->table_id[0],\n\t\t(struct rte_pipeline_table_entry *) &default_entry,\n\t\t(struct rte_pipeline_table_entry **) &rsp->entry_ptr);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_firewall_msg_req_del_default_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_firewall_del_default_msg_rsp *rsp = msg;\n\n\trsp->status = rte_pipeline_table_default_entry_delete(p->p,\n\t\tp->table_id[0],\n\t\tNULL);\n\n\treturn rsp;\n}\n\nstruct pipeline_be_ops pipeline_firewall_be_ops = {\n\t.f_init = pipeline_firewall_init,\n\t.f_free = pipeline_firewall_free,\n\t.f_run = NULL,\n\t.f_timer = pipeline_firewall_timer,\n\t.f_track = pipeline_firewall_track,\n};\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_firewall_be.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_FIREWALL_BE_H__\n#define __INCLUDE_PIPELINE_FIREWALL_BE_H__\n\n#include \"pipeline_common_be.h\"\n\nenum pipeline_firewall_key_type {\n\tPIPELINE_FIREWALL_IPV4_5TUPLE,\n};\n\nstruct pipeline_firewall_key_ipv4_5tuple {\n\tuint32_t src_ip;\n\tuint32_t src_ip_mask;\n\tuint32_t dst_ip;\n\tuint32_t dst_ip_mask;\n\tuint16_t src_port_from;\n\tuint16_t src_port_to;\n\tuint16_t dst_port_from;\n\tuint16_t dst_port_to;\n\tuint8_t proto;\n\tuint8_t proto_mask;\n};\n\nstruct pipeline_firewall_key {\n\tenum pipeline_firewall_key_type type;\n\tunion {\n\t\tstruct pipeline_firewall_key_ipv4_5tuple ipv4_5tuple;\n\t} key;\n};\n\nenum pipeline_firewall_msg_req_type {\n\tPIPELINE_FIREWALL_MSG_REQ_ADD = 0,\n\tPIPELINE_FIREWALL_MSG_REQ_DEL,\n\tPIPELINE_FIREWALL_MSG_REQ_ADD_DEFAULT,\n\tPIPELINE_FIREWALL_MSG_REQ_DEL_DEFAULT,\n\tPIPELINE_FIREWALL_MSG_REQS\n};\n\n/*\n * MSG ADD\n */\nstruct pipeline_firewall_add_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_firewall_msg_req_type subtype;\n\n\t/* key */\n\tstruct pipeline_firewall_key key;\n\n\t/* data */\n\tint32_t priority;\n\tuint32_t port_id;\n};\n\nstruct pipeline_firewall_add_msg_rsp {\n\tint status;\n\tint key_found;\n\tvoid *entry_ptr;\n};\n\n/*\n * MSG DEL\n */\nstruct pipeline_firewall_del_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_firewall_msg_req_type subtype;\n\n\t/* key */\n\tstruct pipeline_firewall_key key;\n};\n\nstruct pipeline_firewall_del_msg_rsp {\n\tint status;\n\tint key_found;\n};\n\n/*\n * MSG ADD DEFAULT\n */\nstruct pipeline_firewall_add_default_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_firewall_msg_req_type subtype;\n\n\t/* data */\n\tuint32_t port_id;\n};\n\nstruct pipeline_firewall_add_default_msg_rsp {\n\tint status;\n\tvoid *entry_ptr;\n};\n\n/*\n * MSG DEL DEFAULT\n */\nstruct pipeline_firewall_del_default_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_firewall_msg_req_type subtype;\n};\n\nstruct pipeline_firewall_del_default_msg_rsp {\n\tint status;\n};\n\nextern struct pipeline_be_ops pipeline_firewall_be_ops;\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_flow_classification.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"app.h\"\n#include \"pipeline_common_fe.h\"\n#include \"pipeline_flow_classification.h\"\n#include \"hash_func.h\"\n\n/*\n * Key conversion\n */\n\nstruct pkt_key_qinq {\n\tuint16_t ethertype_svlan;\n\tuint16_t svlan;\n\tuint16_t ethertype_cvlan;\n\tuint16_t cvlan;\n} __attribute__((__packed__));\n\nstruct pkt_key_ipv4_5tuple {\n\tuint8_t ttl;\n\tuint8_t proto;\n\tuint16_t checksum;\n\tuint32_t ip_src;\n\tuint32_t ip_dst;\n\tuint16_t port_src;\n\tuint16_t port_dst;\n} __attribute__((__packed__));\n\nstruct pkt_key_ipv6_5tuple {\n\tuint16_t payload_length;\n\tuint8_t proto;\n\tuint8_t hop_limit;\n\tuint8_t ip_src[16];\n\tuint8_t ip_dst[16];\n\tuint16_t port_src;\n\tuint16_t port_dst;\n} __attribute__((__packed__));\n\nstatic int\napp_pipeline_fc_key_convert(struct pipeline_fc_key *key_in,\n\tuint8_t *key_out,\n\tuint32_t *signature)\n{\n\tuint8_t buffer[PIPELINE_FC_FLOW_KEY_MAX_SIZE];\n\tvoid *key_buffer = (key_out) ? key_out : buffer;\n\n\tswitch (key_in->type) {\n\tcase FLOW_KEY_QINQ:\n\t{\n\t\tstruct pkt_key_qinq *qinq = key_buffer;\n\n\t\tqinq->ethertype_svlan = 0;\n\t\tqinq->svlan = rte_bswap16(key_in->key.qinq.svlan);\n\t\tqinq->ethertype_cvlan = 0;\n\t\tqinq->cvlan = rte_bswap16(key_in->key.qinq.cvlan);\n\n\t\tif (signature)\n\t\t\t*signature = (uint32_t) hash_default_key8(qinq, 8, 0);\n\t\treturn 0;\n\t}\n\n\tcase FLOW_KEY_IPV4_5TUPLE:\n\t{\n\t\tstruct pkt_key_ipv4_5tuple *ipv4 = key_buffer;\n\n\t\tipv4->ttl = 0;\n\t\tipv4->proto = key_in->key.ipv4_5tuple.proto;\n\t\tipv4->checksum = 0;\n\t\tipv4->ip_src = rte_bswap32(key_in->key.ipv4_5tuple.ip_src);\n\t\tipv4->ip_dst = rte_bswap32(key_in->key.ipv4_5tuple.ip_dst);\n\t\tipv4->port_src = rte_bswap16(key_in->key.ipv4_5tuple.port_src);\n\t\tipv4->port_dst = rte_bswap16(key_in->key.ipv4_5tuple.port_dst);\n\n\t\tif (signature)\n\t\t\t*signature = (uint32_t) hash_default_key16(ipv4, 16, 0);\n\t\treturn 0;\n\t}\n\n\tcase FLOW_KEY_IPV6_5TUPLE:\n\t{\n\t\tstruct pkt_key_ipv6_5tuple *ipv6 = key_buffer;\n\n\t\tmemset(ipv6, 0, 64);\n\t\tipv6->payload_length = 0;\n\t\tipv6->proto = key_in->key.ipv6_5tuple.proto;\n\t\tipv6->hop_limit = 0;\n\t\tmemcpy(&ipv6->ip_src, &key_in->key.ipv6_5tuple.ip_src, 16);\n\t\tmemcpy(&ipv6->ip_dst, &key_in->key.ipv6_5tuple.ip_dst, 16);\n\t\tipv6->port_src = rte_bswap16(key_in->key.ipv6_5tuple.port_src);\n\t\tipv6->port_dst = rte_bswap16(key_in->key.ipv6_5tuple.port_dst);\n\n\t\tif (signature)\n\t\t\t*signature = (uint32_t) hash_default_key64(ipv6, 64, 0);\n\t\treturn 0;\n\t}\n\n\tdefault:\n\t\treturn -1;\n\t}\n}\n\n/*\n * Flow classification pipeline\n */\n\nstruct app_pipeline_fc_flow {\n\tstruct pipeline_fc_key key;\n\tuint32_t port_id;\n\tuint32_t signature;\n\tvoid *entry_ptr;\n\n\tTAILQ_ENTRY(app_pipeline_fc_flow) node;\n};\n\n#define N_BUCKETS 65536\n\nstruct app_pipeline_fc {\n\t/* Parameters */\n\tuint32_t n_ports_in;\n\tuint32_t n_ports_out;\n\n\t/* Flows */\n\tTAILQ_HEAD(, app_pipeline_fc_flow) flows[N_BUCKETS];\n\tuint32_t n_flows;\n\n\t/* Default flow */\n\tuint32_t default_flow_present;\n\tuint32_t default_flow_port_id;\n\tvoid *default_flow_entry_ptr;\n};\n\nstatic struct app_pipeline_fc_flow *\napp_pipeline_fc_flow_find(struct app_pipeline_fc *p,\n\tstruct pipeline_fc_key *key)\n{\n\tstruct app_pipeline_fc_flow *f;\n\tuint32_t signature, bucket_id;\n\n\tapp_pipeline_fc_key_convert(key, NULL, &signature);\n\tbucket_id = signature & (N_BUCKETS - 1);\n\n\tTAILQ_FOREACH(f, &p->flows[bucket_id], node)\n\t\tif ((signature == f->signature) &&\n\t\t\t(memcmp(key,\n\t\t\t\t&f->key,\n\t\t\t\tsizeof(struct pipeline_fc_key)) == 0))\n\t\t\treturn f;\n\n\treturn NULL;\n}\n\nstatic void*\napp_pipeline_fc_init(struct pipeline_params *params,\n\t__rte_unused void *arg)\n{\n\tstruct app_pipeline_fc *p;\n\tuint32_t size, i;\n\n\t/* Check input arguments */\n\tif ((params == NULL) ||\n\t\t(params->n_ports_in == 0) ||\n\t\t(params->n_ports_out == 0))\n\t\treturn NULL;\n\n\t/* Memory allocation */\n\tsize = RTE_CACHE_LINE_ROUNDUP(sizeof(struct app_pipeline_fc));\n\tp = rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE);\n\tif (p == NULL)\n\t\treturn NULL;\n\n\t/* Initialization */\n\tp->n_ports_in = params->n_ports_in;\n\tp->n_ports_out = params->n_ports_out;\n\n\tfor (i = 0; i < N_BUCKETS; i++)\n\t\tTAILQ_INIT(&p->flows[i]);\n\tp->n_flows = 0;\n\n\treturn (void *) p;\n}\n\nstatic int\napp_pipeline_fc_free(void *pipeline)\n{\n\tstruct app_pipeline_fc *p = pipeline;\n\tuint32_t i;\n\n\t/* Check input arguments */\n\tif (p == NULL)\n\t\treturn -1;\n\n\t/* Free resources */\n\tfor (i = 0; i < N_BUCKETS; i++)\n\t\twhile (!TAILQ_EMPTY(&p->flows[i])) {\n\t\t\tstruct app_pipeline_fc_flow *flow;\n\n\t\t\tflow = TAILQ_FIRST(&p->flows[i]);\n\t\t\tTAILQ_REMOVE(&p->flows[i], flow, node);\n\t\t\trte_free(flow);\n\t\t}\n\n\trte_free(p);\n\treturn 0;\n}\n\nstatic int\napp_pipeline_fc_key_check(struct pipeline_fc_key *key)\n{\n\tswitch (key->type) {\n\tcase FLOW_KEY_QINQ:\n\t{\n\t\tuint16_t svlan = key->key.qinq.svlan;\n\t\tuint16_t cvlan = key->key.qinq.cvlan;\n\n\t\tif ((svlan & 0xF000) ||\n\t\t\t(cvlan & 0xF000))\n\t\t\treturn -1;\n\n\t\treturn 0;\n\t}\n\n\tcase FLOW_KEY_IPV4_5TUPLE:\n\t\treturn 0;\n\n\tcase FLOW_KEY_IPV6_5TUPLE:\n\t\treturn 0;\n\n\tdefault:\n\t\treturn -1;\n\t}\n}\n\nint\napp_pipeline_fc_add(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_fc_key *key,\n\tuint32_t port_id)\n{\n\tstruct app_pipeline_fc *p;\n\tstruct app_pipeline_fc_flow *flow;\n\n\tstruct pipeline_fc_add_msg_req *req;\n\tstruct pipeline_fc_add_msg_rsp *rsp;\n\n\tuint32_t signature;\n\tint new_flow;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(key == NULL))\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tif (port_id >= p->n_ports_out)\n\t\treturn -1;\n\n\tif (app_pipeline_fc_key_check(key) != 0)\n\t\treturn -1;\n\n\t/* Find existing flow or allocate new flow */\n\tflow = app_pipeline_fc_flow_find(p, key);\n\tnew_flow = (flow == NULL);\n\tif (flow == NULL) {\n\t\tflow = rte_malloc(NULL, sizeof(*flow), RTE_CACHE_LINE_SIZE);\n\n\t\tif (flow == NULL)\n\t\t\treturn -1;\n\t}\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_FC_MSG_REQ_FLOW_ADD;\n\tapp_pipeline_fc_key_convert(key, req->key, &signature);\n\treq->port_id = port_id;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL) {\n\t\tif (new_flow)\n\t\t\trte_free(flow);\n\t\treturn -1;\n\t}\n\n\t/* Read response and write flow */\n\tif (rsp->status ||\n\t\t(rsp->entry_ptr == NULL) ||\n\t\t((new_flow == 0) && (rsp->key_found == 0)) ||\n\t\t((new_flow == 1) && (rsp->key_found == 1))) {\n\t\tapp_msg_free(app, rsp);\n\t\tif (new_flow)\n\t\t\trte_free(flow);\n\t\treturn -1;\n\t}\n\n\tmemset(&flow->key, 0, sizeof(flow->key));\n\tmemcpy(&flow->key, key, sizeof(flow->key));\n\tflow->port_id = port_id;\n\tflow->signature = signature;\n\tflow->entry_ptr = rsp->entry_ptr;\n\n\t/* Commit rule */\n\tif (new_flow) {\n\t\tuint32_t bucket_id = signature & (N_BUCKETS - 1);\n\n\t\tTAILQ_INSERT_TAIL(&p->flows[bucket_id], flow, node);\n\t\tp->n_flows++;\n\t}\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\nint\napp_pipeline_fc_add_bulk(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_fc_key *key,\n\tuint32_t *port_id,\n\tuint32_t n_keys)\n{\n\tstruct app_pipeline_fc *p;\n\tstruct pipeline_fc_add_bulk_msg_req *req;\n\tstruct pipeline_fc_add_bulk_msg_rsp *rsp;\n\n\tstruct app_pipeline_fc_flow **flow;\n\tuint32_t *signature;\n\tint *new_flow;\n\tstruct pipeline_fc_add_bulk_flow_req *flow_req;\n\tstruct pipeline_fc_add_bulk_flow_rsp *flow_rsp;\n\n\tuint32_t i;\n\tint status;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(key == NULL) ||\n\t\t(port_id == NULL) ||\n\t\t(n_keys == 0))\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tfor (i = 0; i < n_keys; i++)\n\t\tif (port_id[i] >= p->n_ports_out)\n\t\t\treturn -1;\n\n\tfor (i = 0; i < n_keys; i++)\n\t\tif (app_pipeline_fc_key_check(&key[i]) != 0)\n\t\t\treturn -1;\n\n\t/* Memory allocation */\n\tflow = rte_malloc(NULL,\n\t\tn_keys * sizeof(struct app_pipeline_fc_flow *),\n\t\tRTE_CACHE_LINE_SIZE);\n\tif (flow == NULL)\n\t\treturn -1;\n\n\tsignature = rte_malloc(NULL,\n\t\tn_keys * sizeof(uint32_t),\n\t\tRTE_CACHE_LINE_SIZE);\n\tif (signature == NULL) {\n\t\trte_free(flow);\n\t\treturn -1;\n\t}\n\n\tnew_flow = rte_malloc(\n\t\tNULL,\n\t\tn_keys * sizeof(int),\n\t\tRTE_CACHE_LINE_SIZE);\n\tif (new_flow == NULL) {\n\t\trte_free(signature);\n\t\trte_free(flow);\n\t\treturn -1;\n\t}\n\n\tflow_req = rte_malloc(NULL,\n\t\tn_keys * sizeof(struct pipeline_fc_add_bulk_flow_req),\n\t\tRTE_CACHE_LINE_SIZE);\n\tif (flow_req == NULL) {\n\t\trte_free(new_flow);\n\t\trte_free(signature);\n\t\trte_free(flow);\n\t\treturn -1;\n\t}\n\n\tflow_rsp = rte_malloc(NULL,\n\t\tn_keys * sizeof(struct pipeline_fc_add_bulk_flow_rsp),\n\t\tRTE_CACHE_LINE_SIZE);\n\tif (flow_req == NULL) {\n\t\trte_free(flow_req);\n\t\trte_free(new_flow);\n\t\trte_free(signature);\n\t\trte_free(flow);\n\t\treturn -1;\n\t}\n\n\t/* Find existing flow or allocate new flow */\n\tfor (i = 0; i < n_keys; i++) {\n\t\tflow[i] = app_pipeline_fc_flow_find(p, &key[i]);\n\t\tnew_flow[i] = (flow[i] == NULL);\n\t\tif (flow[i] == NULL) {\n\t\t\tflow[i] = rte_zmalloc(NULL,\n\t\t\t\tsizeof(struct app_pipeline_fc_flow),\n\t\t\t\tRTE_CACHE_LINE_SIZE);\n\n\t\t\tif (flow[i] == NULL) {\n\t\t\t\tuint32_t j;\n\n\t\t\t\tfor (j = 0; j < i; j++)\n\t\t\t\t\tif (new_flow[j])\n\t\t\t\t\t\trte_free(flow[j]);\n\n\t\t\t\trte_free(flow_rsp);\n\t\t\t\trte_free(flow_req);\n\t\t\t\trte_free(new_flow);\n\t\t\t\trte_free(signature);\n\t\t\t\trte_free(flow);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL) {\n\t\tfor (i = 0; i < n_keys; i++)\n\t\t\tif (new_flow[i])\n\t\t\t\trte_free(flow[i]);\n\n\t\trte_free(flow_rsp);\n\t\trte_free(flow_req);\n\t\trte_free(new_flow);\n\t\trte_free(signature);\n\t\trte_free(flow);\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < n_keys; i++) {\n\t\tapp_pipeline_fc_key_convert(&key[i],\n\t\t\tflow_req[i].key,\n\t\t\t&signature[i]);\n\t\tflow_req[i].port_id = port_id[i];\n\t}\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_FC_MSG_REQ_FLOW_ADD_BULK;\n\treq->req = flow_req;\n\treq->rsp = flow_rsp;\n\treq->n_keys = n_keys;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, 10000);\n\tif (rsp == NULL) {\n\t\tfor (i = 0; i < n_keys; i++)\n\t\t\tif (new_flow[i])\n\t\t\t\trte_free(flow[i]);\n\n\t\trte_free(flow_rsp);\n\t\trte_free(flow_req);\n\t\trte_free(new_flow);\n\t\trte_free(signature);\n\t\trte_free(flow);\n\t\treturn -1;\n\t}\n\n\t/* Read response */\n\tstatus = 0;\n\n\tfor (i = 0; i < rsp->n_keys; i++)\n\t\tif ((flow_rsp[i].entry_ptr == NULL) ||\n\t\t\t((new_flow[i] == 0) && (flow_rsp[i].key_found == 0)) ||\n\t\t\t((new_flow[i] == 1) && (flow_rsp[i].key_found == 1)))\n\t\t\tstatus = -1;\n\n\tif (rsp->n_keys < n_keys)\n\t\tstatus = -1;\n\n\t/* Commit flows */\n\tfor (i = 0; i < rsp->n_keys; i++) {\n\t\tmemcpy(&flow[i]->key, &key[i], sizeof(flow[i]->key));\n\t\tflow[i]->port_id = port_id[i];\n\t\tflow[i]->signature = signature[i];\n\t\tflow[i]->entry_ptr = flow_rsp[i].entry_ptr;\n\n\t\tif (new_flow[i]) {\n\t\t\tuint32_t bucket_id = signature[i] & (N_BUCKETS - 1);\n\n\t\t\tTAILQ_INSERT_TAIL(&p->flows[bucket_id], flow[i], node);\n\t\t\tp->n_flows++;\n\t\t}\n\t}\n\n\t/* Free resources */\n\tapp_msg_free(app, rsp);\n\n\tfor (i = rsp->n_keys; i < n_keys; i++)\n\t\tif (new_flow[i])\n\t\t\trte_free(flow[i]);\n\n\trte_free(flow_rsp);\n\trte_free(flow_req);\n\trte_free(new_flow);\n\trte_free(signature);\n\trte_free(flow);\n\n\treturn status;\n}\n\nint\napp_pipeline_fc_del(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_fc_key *key)\n{\n\tstruct app_pipeline_fc *p;\n\tstruct app_pipeline_fc_flow *flow;\n\n\tstruct pipeline_fc_del_msg_req *req;\n\tstruct pipeline_fc_del_msg_rsp *rsp;\n\n\tuint32_t signature, bucket_id;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(key == NULL))\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tif (app_pipeline_fc_key_check(key) != 0)\n\t\treturn -1;\n\n\t/* Find rule */\n\tflow = app_pipeline_fc_flow_find(p, key);\n\tif (flow == NULL)\n\t\treturn 0;\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_FC_MSG_REQ_FLOW_DEL;\n\tapp_pipeline_fc_key_convert(key, req->key, &signature);\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Read response */\n\tif (rsp->status || !rsp->key_found) {\n\t\tapp_msg_free(app, rsp);\n\t\treturn -1;\n\t}\n\n\t/* Remove rule */\n\tbucket_id = signature & (N_BUCKETS - 1);\n\tTAILQ_REMOVE(&p->flows[bucket_id], flow, node);\n\tp->n_flows--;\n\trte_free(flow);\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\nint\napp_pipeline_fc_add_default(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id)\n{\n\tstruct app_pipeline_fc *p;\n\n\tstruct pipeline_fc_add_default_msg_req *req;\n\tstruct pipeline_fc_add_default_msg_rsp *rsp;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tif (port_id >= p->n_ports_out)\n\t\treturn -1;\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_FC_MSG_REQ_FLOW_ADD_DEFAULT;\n\treq->port_id = port_id;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Read response and write flow */\n\tif (rsp->status || (rsp->entry_ptr == NULL)) {\n\t\tapp_msg_free(app, rsp);\n\t\treturn -1;\n\t}\n\n\tp->default_flow_port_id = port_id;\n\tp->default_flow_entry_ptr = rsp->entry_ptr;\n\n\t/* Commit route */\n\tp->default_flow_present = 1;\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\nint\napp_pipeline_fc_del_default(struct app_params *app,\n\tuint32_t pipeline_id)\n{\n\tstruct app_pipeline_fc *p;\n\n\tstruct pipeline_fc_del_default_msg_req *req;\n\tstruct pipeline_fc_del_default_msg_rsp *rsp;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -EINVAL;\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_FC_MSG_REQ_FLOW_DEL_DEFAULT;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Read response */\n\tif (rsp->status) {\n\t\tapp_msg_free(app, rsp);\n\t\treturn -1;\n\t}\n\n\t/* Commit route */\n\tp->default_flow_present = 0;\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\n/*\n * Flow ls\n */\n\nstatic void\nprint_fc_qinq_flow(struct app_pipeline_fc_flow *flow)\n{\n\tprintf(\"(SVLAN = %\" PRIu32 \", \"\n\t\t\"CVLAN = %\" PRIu32 \") => \"\n\t\t\"Port = %\" PRIu32 \" \"\n\t\t\"(signature = 0x%08\" PRIx32 \", \"\n\t\t\"entry_ptr = %p)\\n\",\n\n\t\tflow->key.key.qinq.svlan,\n\t\tflow->key.key.qinq.cvlan,\n\t\tflow->port_id,\n\t\tflow->signature,\n\t\tflow->entry_ptr);\n}\n\nstatic void\nprint_fc_ipv4_5tuple_flow(struct app_pipeline_fc_flow *flow)\n{\n\tprintf(\"(SA = %\" PRIu32 \".%\" PRIu32 \".%\" PRIu32 \".%\" PRIu32 \", \"\n\t\t \"DA = %\" PRIu32 \".%\" PRIu32 \".%\" PRIu32 \".%\" PRIu32 \", \"\n\t\t \"SP = %\" PRIu32 \", \"\n\t\t \"DP = %\" PRIu32 \", \"\n\t\t \"Proto = %\" PRIu32 \") => \"\n\t\t \"Port = %\" PRIu32 \" \"\n\t\t \"(signature = 0x%08\" PRIx32 \", \"\n\t\t \"entry_ptr = %p)\\n\",\n\n\t\t (flow->key.key.ipv4_5tuple.ip_src >> 24) & 0xFF,\n\t\t (flow->key.key.ipv4_5tuple.ip_src >> 16) & 0xFF,\n\t\t (flow->key.key.ipv4_5tuple.ip_src >> 8) & 0xFF,\n\t\t flow->key.key.ipv4_5tuple.ip_src & 0xFF,\n\n\t\t (flow->key.key.ipv4_5tuple.ip_dst >> 24) & 0xFF,\n\t\t (flow->key.key.ipv4_5tuple.ip_dst >> 16) & 0xFF,\n\t\t (flow->key.key.ipv4_5tuple.ip_dst >> 8) & 0xFF,\n\t\t flow->key.key.ipv4_5tuple.ip_dst & 0xFF,\n\n\t\t flow->key.key.ipv4_5tuple.port_src,\n\t\t flow->key.key.ipv4_5tuple.port_dst,\n\n\t\t flow->key.key.ipv4_5tuple.proto,\n\n\t\t flow->port_id,\n\t\t flow->signature,\n\t\t flow->entry_ptr);\n}\n\nstatic void\nprint_fc_ipv6_5tuple_flow(struct app_pipeline_fc_flow *flow) {\n\tprintf(\"(SA = %02\" PRIx32 \"%02\" PRIx32 \":%02\" PRIx32 \"%02\" PRIx32\n\t\t\":%02\" PRIx32 \"%02\" PRIx32 \":%02\" PRIx32 \"%02\" PRIx32\n\t\t\":%02\" PRIx32 \"%02\" PRIx32 \":%02\" PRIx32 \"%02\" PRIx32\n\t\t\":%02\" PRIx32 \"%02\" PRIx32 \":%02\" PRIx32 \"%02\" PRIx32 \", \"\n\t\t\"DA = %02\" PRIx32 \"%02\" PRIx32 \":%02\" PRIx32 \"%02\" PRIx32\n\t\t\":%02\" PRIx32 \"%02\" PRIx32 \":%02\" PRIx32 \"%02\" PRIx32\n\t\t\":%02\" PRIx32 \"%02\" PRIx32 \":%02\" PRIx32 \"%02\" PRIx32\n\t\t\":%02\" PRIx32 \"%02\" PRIx32 \":%02\" PRIx32 \"%02\" PRIx32 \", \"\n\t\t\"SP = %\" PRIu32 \", \"\n\t\t\"DP = %\" PRIu32 \" \"\n\t\t\"Proto = %\" PRIu32 \" \"\n\t\t\"=> Port = %\" PRIu32 \" \"\n\t\t\"(signature = 0x%08\" PRIx32 \", \"\n\t\t\"entry_ptr = %p)\\n\",\n\n\t\tflow->key.key.ipv6_5tuple.ip_src[0],\n\t\tflow->key.key.ipv6_5tuple.ip_src[1],\n\t\tflow->key.key.ipv6_5tuple.ip_src[2],\n\t\tflow->key.key.ipv6_5tuple.ip_src[3],\n\t\tflow->key.key.ipv6_5tuple.ip_src[4],\n\t\tflow->key.key.ipv6_5tuple.ip_src[5],\n\t\tflow->key.key.ipv6_5tuple.ip_src[6],\n\t\tflow->key.key.ipv6_5tuple.ip_src[7],\n\t\tflow->key.key.ipv6_5tuple.ip_src[8],\n\t\tflow->key.key.ipv6_5tuple.ip_src[9],\n\t\tflow->key.key.ipv6_5tuple.ip_src[10],\n\t\tflow->key.key.ipv6_5tuple.ip_src[11],\n\t\tflow->key.key.ipv6_5tuple.ip_src[12],\n\t\tflow->key.key.ipv6_5tuple.ip_src[13],\n\t\tflow->key.key.ipv6_5tuple.ip_src[14],\n\t\tflow->key.key.ipv6_5tuple.ip_src[15],\n\n\t\tflow->key.key.ipv6_5tuple.ip_dst[0],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[1],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[2],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[3],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[4],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[5],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[6],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[7],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[8],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[9],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[10],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[11],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[12],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[13],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[14],\n\t\tflow->key.key.ipv6_5tuple.ip_dst[15],\n\n\t\tflow->key.key.ipv6_5tuple.port_src,\n\t\tflow->key.key.ipv6_5tuple.port_dst,\n\n\t\tflow->key.key.ipv6_5tuple.proto,\n\n\t\tflow->port_id,\n\t\tflow->signature,\n\t\tflow->entry_ptr);\n}\n\nstatic void\nprint_fc_flow(struct app_pipeline_fc_flow *flow)\n{\n\tswitch (flow->key.type) {\n\tcase FLOW_KEY_QINQ:\n\t\tprint_fc_qinq_flow(flow);\n\t\tbreak;\n\n\tcase FLOW_KEY_IPV4_5TUPLE:\n\t\tprint_fc_ipv4_5tuple_flow(flow);\n\t\tbreak;\n\n\tcase FLOW_KEY_IPV6_5TUPLE:\n\t\tprint_fc_ipv6_5tuple_flow(flow);\n\t\tbreak;\n\t}\n}\n\nstatic int\napp_pipeline_fc_ls(struct app_params *app,\n\t\tuint32_t pipeline_id)\n{\n\tstruct app_pipeline_fc *p;\n\tstruct app_pipeline_fc_flow *flow;\n\tuint32_t i;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tfor (i = 0; i < N_BUCKETS; i++)\n\t\tTAILQ_FOREACH(flow, &p->flows[i], node)\n\t\t\tprint_fc_flow(flow);\n\n\tif (p->default_flow_present)\n\t\tprintf(\"Default flow: port %\" PRIu32 \" (entry ptr = %p)\\n\",\n\t\t\tp->default_flow_port_id,\n\t\t\tp->default_flow_entry_ptr);\n\telse\n\t\tprintf(\"Default: DROP\\n\");\n\n\treturn 0;\n}\n\n/*\n * flow add qinq\n */\n\nstruct cmd_fc_add_qinq_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t flow_string;\n\tcmdline_fixed_string_t add_string;\n\tcmdline_fixed_string_t qinq_string;\n\tuint16_t svlan;\n\tuint16_t cvlan;\n\tuint32_t port;\n};\n\nstatic void\ncmd_fc_add_qinq_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_fc_add_qinq_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_fc_key key;\n\tint status;\n\n\tmemset(&key, 0, sizeof(key));\n\tkey.type = FLOW_KEY_QINQ;\n\tkey.key.qinq.svlan = params->svlan;\n\tkey.key.qinq.cvlan = params->cvlan;\n\n\tstatus = app_pipeline_fc_add(app,\n\t\tparams->pipeline_id,\n\t\t&key,\n\t\tparams->port);\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n}\n\ncmdline_parse_token_string_t cmd_fc_add_qinq_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_qinq_result, p_string, \"p\");\n\ncmdline_parse_token_num_t cmd_fc_add_qinq_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_qinq_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_fc_add_qinq_flow_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_qinq_result, flow_string,\n\t\t\"flow\");\n\ncmdline_parse_token_string_t cmd_fc_add_qinq_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_qinq_result, add_string,\n\t\t\"add\");\n\ncmdline_parse_token_string_t cmd_fc_add_qinq_qinq_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_qinq_result, qinq_string,\n\t\t\"qinq\");\n\ncmdline_parse_token_num_t cmd_fc_add_qinq_svlan =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_qinq_result, svlan, UINT16);\n\ncmdline_parse_token_num_t cmd_fc_add_qinq_cvlan =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_qinq_result, cvlan, UINT16);\n\ncmdline_parse_token_num_t cmd_fc_add_qinq_port =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_qinq_result, port, UINT32);\n\ncmdline_parse_inst_t cmd_fc_add_qinq = {\n\t.f = cmd_fc_add_qinq_parsed,\n\t.data = NULL,\n\t.help_str = \"Flow add (Q-in-Q)\",\n\t.tokens = {\n\t\t(void *) &cmd_fc_add_qinq_p_string,\n\t\t(void *) &cmd_fc_add_qinq_pipeline_id,\n\t\t(void *) &cmd_fc_add_qinq_flow_string,\n\t\t(void *) &cmd_fc_add_qinq_add_string,\n\t\t(void *) &cmd_fc_add_qinq_qinq_string,\n\t\t(void *) &cmd_fc_add_qinq_svlan,\n\t\t(void *) &cmd_fc_add_qinq_cvlan,\n\t\t(void *) &cmd_fc_add_qinq_port,\n\t\tNULL,\n\t},\n};\n\n/*\n * flow add qinq all\n */\n\nstruct cmd_fc_add_qinq_all_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t flow_string;\n\tcmdline_fixed_string_t add_string;\n\tcmdline_fixed_string_t qinq_string;\n\tcmdline_fixed_string_t all_string;\n\tuint32_t n_flows;\n\tuint32_t n_ports;\n};\n\n#ifndef N_FLOWS_BULK\n#define N_FLOWS_BULK\t\t\t\t\t4096\n#endif\n\nstatic void\ncmd_fc_add_qinq_all_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_fc_add_qinq_all_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_fc_key *key;\n\tuint32_t *port_id;\n\tuint32_t flow_id;\n\n\tkey = rte_zmalloc(NULL,\n\t\tN_FLOWS_BULK * sizeof(*key),\n\t\tRTE_CACHE_LINE_SIZE);\n\tif (key == NULL) {\n\t\tprintf(\"Memory allocation failed\\n\");\n\t\treturn;\n\t}\n\n\tport_id = rte_malloc(NULL,\n\t\tN_FLOWS_BULK * sizeof(*port_id),\n\t\tRTE_CACHE_LINE_SIZE);\n\tif (port_id == NULL) {\n\t\trte_free(key);\n\t\tprintf(\"Memory allocation failed\\n\");\n\t\treturn;\n\t}\n\n\tfor (flow_id = 0; flow_id < params->n_flows; flow_id++) {\n\t\tuint32_t pos = flow_id & (N_FLOWS_BULK - 1);\n\n\t\tkey[pos].type = FLOW_KEY_QINQ;\n\t\tkey[pos].key.qinq.svlan = flow_id >> 12;\n\t\tkey[pos].key.qinq.cvlan = flow_id & 0xFFF;\n\n\t\tport_id[pos] = flow_id % params->n_ports;\n\n\t\tif ((pos == N_FLOWS_BULK - 1) ||\n\t\t\t(flow_id == params->n_flows - 1)) {\n\t\t\tint status;\n\n\t\t\tstatus = app_pipeline_fc_add_bulk(app,\n\t\t\t\tparams->pipeline_id,\n\t\t\t\tkey,\n\t\t\t\tport_id,\n\t\t\t\tpos + 1);\n\n\t\t\tif (status != 0) {\n\t\t\t\tprintf(\"Command failed\\n\");\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\trte_free(port_id);\n\trte_free(key);\n}\n\ncmdline_parse_token_string_t cmd_fc_add_qinq_all_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_qinq_all_result, p_string,\n\t\t\"p\");\n\ncmdline_parse_token_num_t cmd_fc_add_qinq_all_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_qinq_all_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_fc_add_qinq_all_flow_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_qinq_all_result, flow_string,\n\t\t\"flow\");\n\ncmdline_parse_token_string_t cmd_fc_add_qinq_all_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_qinq_all_result, add_string,\n\t\t\"add\");\n\ncmdline_parse_token_string_t cmd_fc_add_qinq_all_qinq_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_qinq_all_result, qinq_string,\n\t\t\"qinq\");\n\ncmdline_parse_token_string_t cmd_fc_add_qinq_all_all_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_qinq_all_result, all_string,\n\t\t\"all\");\n\ncmdline_parse_token_num_t cmd_fc_add_qinq_all_n_flows =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_qinq_all_result, n_flows,\n\t\tUINT32);\n\ncmdline_parse_token_num_t cmd_fc_add_qinq_all_n_ports =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_qinq_all_result, n_ports,\n\t\tUINT32);\n\ncmdline_parse_inst_t cmd_fc_add_qinq_all = {\n\t.f = cmd_fc_add_qinq_all_parsed,\n\t.data = NULL,\n\t.help_str = \"Flow add all (Q-in-Q)\",\n\t.tokens = {\n\t\t(void *) &cmd_fc_add_qinq_all_p_string,\n\t\t(void *) &cmd_fc_add_qinq_all_pipeline_id,\n\t\t(void *) &cmd_fc_add_qinq_all_flow_string,\n\t\t(void *) &cmd_fc_add_qinq_all_add_string,\n\t\t(void *) &cmd_fc_add_qinq_all_qinq_string,\n\t\t(void *) &cmd_fc_add_qinq_all_all_string,\n\t\t(void *) &cmd_fc_add_qinq_all_n_flows,\n\t\t(void *) &cmd_fc_add_qinq_all_n_ports,\n\t\tNULL,\n\t},\n};\n\n/*\n * flow add ipv4_5tuple\n */\n\nstruct cmd_fc_add_ipv4_5tuple_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t flow_string;\n\tcmdline_fixed_string_t add_string;\n\tcmdline_fixed_string_t ipv4_5tuple_string;\n\tcmdline_ipaddr_t ip_src;\n\tcmdline_ipaddr_t ip_dst;\n\tuint16_t port_src;\n\tuint16_t port_dst;\n\tuint32_t proto;\n\tuint32_t port;\n};\n\nstatic void\ncmd_fc_add_ipv4_5tuple_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_fc_add_ipv4_5tuple_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_fc_key key;\n\tint status;\n\n\tmemset(&key, 0, sizeof(key));\n\tkey.type = FLOW_KEY_IPV4_5TUPLE;\n\tkey.key.ipv4_5tuple.ip_src = rte_bswap32(\n\t\tparams->ip_src.addr.ipv4.s_addr);\n\tkey.key.ipv4_5tuple.ip_dst = rte_bswap32(\n\t\tparams->ip_dst.addr.ipv4.s_addr);\n\tkey.key.ipv4_5tuple.port_src = params->port_src;\n\tkey.key.ipv4_5tuple.port_dst = params->port_dst;\n\tkey.key.ipv4_5tuple.proto = params->proto;\n\n\tstatus = app_pipeline_fc_add(app,\n\t\tparams->pipeline_id,\n\t\t&key,\n\t\tparams->port);\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n}\n\ncmdline_parse_token_string_t cmd_fc_add_ipv4_5tuple_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_result, p_string,\n\t\t\"p\");\n\ncmdline_parse_token_num_t cmd_fc_add_ipv4_5tuple_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_fc_add_ipv4_5tuple_flow_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_result,\n\t\tflow_string, \"flow\");\n\ncmdline_parse_token_string_t cmd_fc_add_ipv4_5tuple_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_result,\n\t\tadd_string, \"add\");\n\ncmdline_parse_token_string_t cmd_fc_add_ipv4_5tuple_ipv4_5tuple_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_result,\n\t\tipv4_5tuple_string, \"ipv4_5tuple\");\n\ncmdline_parse_token_ipaddr_t cmd_fc_add_ipv4_5tuple_ip_src =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_result, ip_src);\n\ncmdline_parse_token_ipaddr_t cmd_fc_add_ipv4_5tuple_ip_dst =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_result, ip_dst);\n\ncmdline_parse_token_num_t cmd_fc_add_ipv4_5tuple_port_src =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_result, port_src,\n\t\tUINT16);\n\ncmdline_parse_token_num_t cmd_fc_add_ipv4_5tuple_port_dst =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_result, port_dst,\n\t\tUINT16);\n\ncmdline_parse_token_num_t cmd_fc_add_ipv4_5tuple_proto =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_result, proto,\n\t\tUINT32);\n\ncmdline_parse_token_num_t cmd_fc_add_ipv4_5tuple_port =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_result, port,\n\t\tUINT32);\n\ncmdline_parse_inst_t cmd_fc_add_ipv4_5tuple = {\n\t.f = cmd_fc_add_ipv4_5tuple_parsed,\n\t.data = NULL,\n\t.help_str = \"Flow add (IPv4 5-tuple)\",\n\t.tokens = {\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_p_string,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_pipeline_id,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_flow_string,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_add_string,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_ipv4_5tuple_string,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_ip_src,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_ip_dst,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_port_src,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_port_dst,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_proto,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_port,\n\t\tNULL,\n\t},\n};\n\n/*\n * flow add ipv4_5tuple all\n */\n\nstruct cmd_fc_add_ipv4_5tuple_all_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t flow_string;\n\tcmdline_fixed_string_t add_string;\n\tcmdline_fixed_string_t ipv4_5tuple_string;\n\tcmdline_fixed_string_t all_string;\n\tuint32_t n_flows;\n\tuint32_t n_ports;\n};\n\nstatic void\ncmd_fc_add_ipv4_5tuple_all_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_fc_add_ipv4_5tuple_all_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_fc_key *key;\n\tuint32_t *port_id;\n\tuint32_t flow_id;\n\n\tkey = rte_zmalloc(NULL,\n\t\tN_FLOWS_BULK * sizeof(*key),\n\t\tRTE_CACHE_LINE_SIZE);\n\tif (key == NULL) {\n\t\tprintf(\"Memory allocation failed\\n\");\n\t\treturn;\n\t}\n\n\tport_id = rte_malloc(NULL,\n\t\tN_FLOWS_BULK * sizeof(*port_id),\n\t\tRTE_CACHE_LINE_SIZE);\n\tif (port_id == NULL) {\n\t\trte_free(key);\n\t\tprintf(\"Memory allocation failed\\n\");\n\t\treturn;\n\t}\n\n\tfor (flow_id = 0; flow_id < params->n_flows; flow_id++) {\n\t\tuint32_t pos = flow_id & (N_FLOWS_BULK - 1);\n\n\t\tkey[pos].type = FLOW_KEY_IPV4_5TUPLE;\n\t\tkey[pos].key.ipv4_5tuple.ip_src = 0;\n\t\tkey[pos].key.ipv4_5tuple.ip_dst = flow_id;\n\t\tkey[pos].key.ipv4_5tuple.port_src = 0;\n\t\tkey[pos].key.ipv4_5tuple.port_dst = 0;\n\t\tkey[pos].key.ipv4_5tuple.proto = 6;\n\n\t\tport_id[pos] = flow_id % params->n_ports;\n\n\t\tif ((pos == N_FLOWS_BULK - 1) ||\n\t\t\t(flow_id == params->n_flows - 1)) {\n\t\t\tint status;\n\n\t\t\tstatus = app_pipeline_fc_add_bulk(app,\n\t\t\t\tparams->pipeline_id,\n\t\t\t\tkey,\n\t\t\t\tport_id,\n\t\t\t\tpos + 1);\n\n\t\t\tif (status != 0) {\n\t\t\t\tprintf(\"Command failed\\n\");\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\trte_free(port_id);\n\trte_free(key);\n}\n\ncmdline_parse_token_string_t cmd_fc_add_ipv4_5tuple_all_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_all_result,\n\t\tp_string, \"p\");\n\ncmdline_parse_token_num_t cmd_fc_add_ipv4_5tuple_all_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_all_result,\n\t\tpipeline_id, UINT32);\n\ncmdline_parse_token_string_t cmd_fc_add_ipv4_5tuple_all_flow_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_all_result,\n\t\tflow_string, \"flow\");\n\ncmdline_parse_token_string_t cmd_fc_add_ipv4_5tuple_all_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_all_result,\n\t\tadd_string, \"add\");\n\ncmdline_parse_token_string_t cmd_fc_add_ipv4_5tuple_all_ipv4_5tuple_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_all_result,\n\t\tipv4_5tuple_string, \"ipv4_5tuple\");\n\ncmdline_parse_token_string_t cmd_fc_add_ipv4_5tuple_all_all_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_all_result,\n\t\tall_string, \"all\");\n\ncmdline_parse_token_num_t cmd_fc_add_ipv4_5tuple_all_n_flows =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_all_result,\n\t\tn_flows, UINT32);\n\ncmdline_parse_token_num_t cmd_fc_add_ipv4_5tuple_all_n_ports =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv4_5tuple_all_result,\n\t\tn_ports, UINT32);\n\ncmdline_parse_inst_t cmd_fc_add_ipv4_5tuple_all = {\n\t.f = cmd_fc_add_ipv4_5tuple_all_parsed,\n\t.data = NULL,\n\t.help_str = \"Flow add all (IPv4 5-tuple)\",\n\t.tokens = {\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_all_p_string,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_all_pipeline_id,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_all_flow_string,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_all_add_string,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_all_ipv4_5tuple_string,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_all_all_string,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_all_n_flows,\n\t\t(void *) &cmd_fc_add_ipv4_5tuple_all_n_ports,\n\t\tNULL,\n\t},\n};\n\n/*\n * flow add ipv6_5tuple\n */\n\nstruct cmd_fc_add_ipv6_5tuple_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t flow_string;\n\tcmdline_fixed_string_t add_string;\n\tcmdline_fixed_string_t ipv6_5tuple_string;\n\tcmdline_ipaddr_t ip_src;\n\tcmdline_ipaddr_t ip_dst;\n\tuint16_t port_src;\n\tuint16_t port_dst;\n\tuint32_t proto;\n\tuint32_t port;\n};\n\nstatic void\ncmd_fc_add_ipv6_5tuple_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_fc_add_ipv6_5tuple_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_fc_key key;\n\tint status;\n\n\tmemset(&key, 0, sizeof(key));\n\tkey.type = FLOW_KEY_IPV6_5TUPLE;\n\tmemcpy(key.key.ipv6_5tuple.ip_src,\n\t\tparams->ip_src.addr.ipv6.s6_addr,\n\t\t16);\n\tmemcpy(key.key.ipv6_5tuple.ip_dst,\n\t\tparams->ip_dst.addr.ipv6.s6_addr,\n\t\t16);\n\tkey.key.ipv6_5tuple.port_src = params->port_src;\n\tkey.key.ipv6_5tuple.port_dst = params->port_dst;\n\tkey.key.ipv6_5tuple.proto = params->proto;\n\n\tstatus = app_pipeline_fc_add(app,\n\t\tparams->pipeline_id,\n\t\t&key,\n\t\tparams->port);\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n}\n\ncmdline_parse_token_string_t cmd_fc_add_ipv6_5tuple_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_result,\n\t\tp_string, \"p\");\n\ncmdline_parse_token_num_t cmd_fc_add_ipv6_5tuple_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_fc_add_ipv6_5tuple_flow_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_result,\n\t\tflow_string, \"flow\");\n\ncmdline_parse_token_string_t cmd_fc_add_ipv6_5tuple_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_result,\n\t\tadd_string, \"add\");\n\ncmdline_parse_token_string_t cmd_fc_add_ipv6_5tuple_ipv6_5tuple_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_result,\n\t\tipv6_5tuple_string, \"ipv6_5tuple\");\n\ncmdline_parse_token_ipaddr_t cmd_fc_add_ipv6_5tuple_ip_src =\n\tTOKEN_IPV6_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_result, ip_src);\n\ncmdline_parse_token_ipaddr_t cmd_fc_add_ipv6_5tuple_ip_dst =\n\tTOKEN_IPV6_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_result, ip_dst);\n\ncmdline_parse_token_num_t cmd_fc_add_ipv6_5tuple_port_src =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_result, port_src,\n\t\tUINT16);\n\ncmdline_parse_token_num_t cmd_fc_add_ipv6_5tuple_port_dst =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_result, port_dst,\n\t\tUINT16);\n\ncmdline_parse_token_num_t cmd_fc_add_ipv6_5tuple_proto =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_result, proto,\n\t\tUINT32);\n\ncmdline_parse_token_num_t cmd_fc_add_ipv6_5tuple_port =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_result, port,\n\t\tUINT32);\n\ncmdline_parse_inst_t cmd_fc_add_ipv6_5tuple = {\n\t.f = cmd_fc_add_ipv6_5tuple_parsed,\n\t.data = NULL,\n\t.help_str = \"Flow add (IPv6 5-tuple)\",\n\t.tokens = {\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_p_string,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_pipeline_id,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_flow_string,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_add_string,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_ipv6_5tuple_string,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_ip_src,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_ip_dst,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_port_src,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_port_dst,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_proto,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_port,\n\t\tNULL,\n\t},\n};\n\n/*\n * flow add ipv6_5tuple all\n */\n\nstruct cmd_fc_add_ipv6_5tuple_all_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t flow_string;\n\tcmdline_fixed_string_t add_string;\n\tcmdline_fixed_string_t ipv6_5tuple_string;\n\tcmdline_fixed_string_t all_string;\n\tuint32_t n_flows;\n\tuint32_t n_ports;\n};\n\nstatic void\ncmd_fc_add_ipv6_5tuple_all_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_fc_add_ipv6_5tuple_all_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_fc_key *key;\n\tuint32_t *port_id;\n\tuint32_t flow_id;\n\n\tkey = rte_zmalloc(NULL,\n\t\tN_FLOWS_BULK * sizeof(*key),\n\t\tRTE_CACHE_LINE_SIZE);\n\tif (key == NULL) {\n\t\tprintf(\"Memory allocation failed\\n\");\n\t\treturn;\n\t}\n\n\tport_id = rte_malloc(NULL,\n\t\tN_FLOWS_BULK * sizeof(*port_id),\n\t\tRTE_CACHE_LINE_SIZE);\n\tif (port_id == NULL) {\n\t\trte_free(key);\n\t\tprintf(\"Memory allocation failed\\n\");\n\t\treturn;\n\t}\n\n\tfor (flow_id = 0; flow_id < params->n_flows; flow_id++) {\n\t\tuint32_t pos = flow_id & (N_FLOWS_BULK - 1);\n\t\tuint32_t *x;\n\n\t\tkey[pos].type = FLOW_KEY_IPV6_5TUPLE;\n\t\tx = (uint32_t *) key[pos].key.ipv6_5tuple.ip_dst;\n\t\t*x = rte_bswap32(flow_id);\n\t\tkey[pos].key.ipv6_5tuple.proto = 6;\n\n\t\tport_id[pos] = flow_id % params->n_ports;\n\n\t\tif ((pos == N_FLOWS_BULK - 1) ||\n\t\t\t(flow_id == params->n_flows - 1)) {\n\t\t\tint status;\n\n\t\t\tstatus = app_pipeline_fc_add_bulk(app,\n\t\t\t\tparams->pipeline_id,\n\t\t\t\tkey,\n\t\t\t\tport_id,\n\t\t\t\tpos + 1);\n\n\t\t\tif (status != 0) {\n\t\t\t\tprintf(\"Command failed\\n\");\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\trte_free(port_id);\n\trte_free(key);\n}\n\ncmdline_parse_token_string_t cmd_fc_add_ipv6_5tuple_all_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_all_result,\n\t\tp_string, \"p\");\n\ncmdline_parse_token_num_t cmd_fc_add_ipv6_5tuple_all_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_all_result,\n\t\tpipeline_id, UINT32);\n\ncmdline_parse_token_string_t cmd_fc_add_ipv6_5tuple_all_flow_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_all_result,\n\t\tflow_string, \"flow\");\n\ncmdline_parse_token_string_t cmd_fc_add_ipv6_5tuple_all_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_all_result,\n\t\tadd_string, \"add\");\n\ncmdline_parse_token_string_t cmd_fc_add_ipv6_5tuple_all_ipv6_5tuple_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_all_result,\n\t\tipv6_5tuple_string, \"ipv6_5tuple\");\n\ncmdline_parse_token_string_t cmd_fc_add_ipv6_5tuple_all_all_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_all_result,\n\t\tall_string, \"all\");\n\ncmdline_parse_token_num_t cmd_fc_add_ipv6_5tuple_all_n_flows =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_all_result,\n\t\tn_flows, UINT32);\n\ncmdline_parse_token_num_t cmd_fc_add_ipv6_5tuple_all_n_ports =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_ipv6_5tuple_all_result,\n\t\tn_ports, UINT32);\n\ncmdline_parse_inst_t cmd_fc_add_ipv6_5tuple_all = {\n\t.f = cmd_fc_add_ipv6_5tuple_all_parsed,\n\t.data = NULL,\n\t.help_str = \"Flow add all (ipv6 5-tuple)\",\n\t.tokens = {\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_all_p_string,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_all_pipeline_id,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_all_flow_string,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_all_add_string,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_all_ipv6_5tuple_string,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_all_all_string,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_all_n_flows,\n\t\t(void *) &cmd_fc_add_ipv6_5tuple_all_n_ports,\n\t\tNULL,\n\t},\n};\n\n/*\n * flow del qinq\n */\nstruct cmd_fc_del_qinq_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t flow_string;\n\tcmdline_fixed_string_t del_string;\n\tcmdline_fixed_string_t qinq_string;\n\tuint16_t svlan;\n\tuint16_t cvlan;\n};\n\nstatic void\ncmd_fc_del_qinq_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_fc_del_qinq_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_fc_key key;\n\tint status;\n\n\tmemset(&key, 0, sizeof(key));\n\tkey.type = FLOW_KEY_QINQ;\n\tkey.key.qinq.svlan = params->svlan;\n\tkey.key.qinq.cvlan = params->cvlan;\n\tstatus = app_pipeline_fc_del(app, params->pipeline_id, &key);\n\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n}\n\ncmdline_parse_token_string_t cmd_fc_del_qinq_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_qinq_result, p_string, \"p\");\n\ncmdline_parse_token_num_t cmd_fc_del_qinq_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_del_qinq_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_fc_del_qinq_flow_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_qinq_result, flow_string,\n\t\t\"flow\");\n\ncmdline_parse_token_string_t cmd_fc_del_qinq_del_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_qinq_result, del_string,\n\t\t\"del\");\n\ncmdline_parse_token_string_t cmd_fc_del_qinq_qinq_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_qinq_result, qinq_string,\n\t\t\"qinq\");\n\ncmdline_parse_token_num_t cmd_fc_del_qinq_svlan =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_del_qinq_result, svlan, UINT16);\n\ncmdline_parse_token_num_t cmd_fc_del_qinq_cvlan =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_del_qinq_result, cvlan, UINT16);\n\ncmdline_parse_inst_t cmd_fc_del_qinq = {\n\t.f = cmd_fc_del_qinq_parsed,\n\t.data = NULL,\n\t.help_str = \"Flow delete (Q-in-Q)\",\n\t.tokens = {\n\t\t(void *) &cmd_fc_del_qinq_p_string,\n\t\t(void *) &cmd_fc_del_qinq_pipeline_id,\n\t\t(void *) &cmd_fc_del_qinq_flow_string,\n\t\t(void *) &cmd_fc_del_qinq_del_string,\n\t\t(void *) &cmd_fc_del_qinq_qinq_string,\n\t\t(void *) &cmd_fc_del_qinq_svlan,\n\t\t(void *) &cmd_fc_del_qinq_cvlan,\n\t\tNULL,\n\t},\n};\n\n/*\n * flow del ipv4_5tuple\n */\n\nstruct cmd_fc_del_ipv4_5tuple_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t flow_string;\n\tcmdline_fixed_string_t del_string;\n\tcmdline_fixed_string_t ipv4_5tuple_string;\n\tcmdline_ipaddr_t ip_src;\n\tcmdline_ipaddr_t ip_dst;\n\tuint16_t port_src;\n\tuint16_t port_dst;\n\tuint32_t proto;\n};\n\nstatic void\ncmd_fc_del_ipv4_5tuple_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_fc_del_ipv4_5tuple_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_fc_key key;\n\tint status;\n\n\tmemset(&key, 0, sizeof(key));\n\tkey.type = FLOW_KEY_IPV4_5TUPLE;\n\tkey.key.ipv4_5tuple.ip_src = rte_bswap32(\n\t\tparams->ip_src.addr.ipv4.s_addr);\n\tkey.key.ipv4_5tuple.ip_dst = rte_bswap32(\n\t\tparams->ip_dst.addr.ipv4.s_addr);\n\tkey.key.ipv4_5tuple.port_src = params->port_src;\n\tkey.key.ipv4_5tuple.port_dst = params->port_dst;\n\tkey.key.ipv4_5tuple.proto = params->proto;\n\n\tstatus = app_pipeline_fc_del(app, params->pipeline_id, &key);\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n}\n\ncmdline_parse_token_string_t cmd_fc_del_ipv4_5tuple_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_ipv4_5tuple_result,\n\t\tp_string, \"p\");\n\ncmdline_parse_token_num_t cmd_fc_del_ipv4_5tuple_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_del_ipv4_5tuple_result,\n\t\tpipeline_id, UINT32);\n\ncmdline_parse_token_string_t cmd_fc_del_ipv4_5tuple_flow_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_ipv4_5tuple_result,\n\t\tflow_string, \"flow\");\n\ncmdline_parse_token_string_t cmd_fc_del_ipv4_5tuple_del_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_ipv4_5tuple_result,\n\t\tdel_string, \"del\");\n\ncmdline_parse_token_string_t cmd_fc_del_ipv4_5tuple_ipv4_5tuple_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_ipv4_5tuple_result,\n\t\tipv4_5tuple_string, \"ipv4_5tuple\");\n\ncmdline_parse_token_ipaddr_t cmd_fc_del_ipv4_5tuple_ip_src =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_fc_del_ipv4_5tuple_result,\n\t\tip_src);\n\ncmdline_parse_token_ipaddr_t cmd_fc_del_ipv4_5tuple_ip_dst =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_fc_del_ipv4_5tuple_result, ip_dst);\n\ncmdline_parse_token_num_t cmd_fc_del_ipv4_5tuple_port_src =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_del_ipv4_5tuple_result,\n\t\tport_src, UINT16);\n\ncmdline_parse_token_num_t cmd_fc_del_ipv4_5tuple_port_dst =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_del_ipv4_5tuple_result,\n\t\tport_dst, UINT16);\n\ncmdline_parse_token_num_t cmd_fc_del_ipv4_5tuple_proto =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_del_ipv4_5tuple_result,\n\t\tproto, UINT32);\n\ncmdline_parse_inst_t cmd_fc_del_ipv4_5tuple = {\n\t.f = cmd_fc_del_ipv4_5tuple_parsed,\n\t.data = NULL,\n\t.help_str = \"Flow delete (IPv4 5-tuple)\",\n\t.tokens = {\n\t\t(void *) &cmd_fc_del_ipv4_5tuple_p_string,\n\t\t(void *) &cmd_fc_del_ipv4_5tuple_pipeline_id,\n\t\t(void *) &cmd_fc_del_ipv4_5tuple_flow_string,\n\t\t(void *) &cmd_fc_del_ipv4_5tuple_del_string,\n\t\t(void *) &cmd_fc_del_ipv4_5tuple_ipv4_5tuple_string,\n\t\t(void *) &cmd_fc_del_ipv4_5tuple_ip_src,\n\t\t(void *) &cmd_fc_del_ipv4_5tuple_ip_dst,\n\t\t(void *) &cmd_fc_del_ipv4_5tuple_port_src,\n\t\t(void *) &cmd_fc_del_ipv4_5tuple_port_dst,\n\t\t(void *) &cmd_fc_del_ipv4_5tuple_proto,\n\t\tNULL,\n\t},\n};\n\n/*\n * flow del ipv6_5tuple\n */\n\nstruct cmd_fc_del_ipv6_5tuple_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t flow_string;\n\tcmdline_fixed_string_t del_string;\n\tcmdline_fixed_string_t ipv6_5tuple_string;\n\tcmdline_ipaddr_t ip_src;\n\tcmdline_ipaddr_t ip_dst;\n\tuint16_t port_src;\n\tuint16_t port_dst;\n\tuint32_t proto;\n};\n\nstatic void\ncmd_fc_del_ipv6_5tuple_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_fc_del_ipv6_5tuple_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_fc_key key;\n\tint status;\n\n\tmemset(&key, 0, sizeof(key));\n\tkey.type = FLOW_KEY_IPV6_5TUPLE;\n\tmemcpy(key.key.ipv6_5tuple.ip_src,\n\t\tparams->ip_src.addr.ipv6.s6_addr,\n\t\t16);\n\tmemcpy(key.key.ipv6_5tuple.ip_dst,\n\t\tparams->ip_dst.addr.ipv6.s6_addr,\n\t\t16);\n\tkey.key.ipv6_5tuple.port_src = params->port_src;\n\tkey.key.ipv6_5tuple.port_dst = params->port_dst;\n\tkey.key.ipv6_5tuple.proto = params->proto;\n\n\tstatus = app_pipeline_fc_del(app, params->pipeline_id, &key);\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n}\n\ncmdline_parse_token_string_t cmd_fc_del_ipv6_5tuple_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_ipv6_5tuple_result,\n\t\tp_string, \"p\");\n\ncmdline_parse_token_num_t cmd_fc_del_ipv6_5tuple_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_del_ipv6_5tuple_result,\n\t\tpipeline_id, UINT32);\n\ncmdline_parse_token_string_t cmd_fc_del_ipv6_5tuple_flow_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_ipv6_5tuple_result,\n\t\tflow_string, \"flow\");\n\ncmdline_parse_token_string_t cmd_fc_del_ipv6_5tuple_del_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_ipv6_5tuple_result,\n\t\tdel_string, \"del\");\n\ncmdline_parse_token_string_t cmd_fc_del_ipv6_5tuple_ipv6_5tuple_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_ipv6_5tuple_result,\n\t\tipv6_5tuple_string, \"ipv6_5tuple\");\n\ncmdline_parse_token_ipaddr_t cmd_fc_del_ipv6_5tuple_ip_src =\n\tTOKEN_IPV6_INITIALIZER(struct cmd_fc_del_ipv6_5tuple_result, ip_src);\n\ncmdline_parse_token_ipaddr_t cmd_fc_del_ipv6_5tuple_ip_dst =\n\tTOKEN_IPV6_INITIALIZER(struct cmd_fc_del_ipv6_5tuple_result, ip_dst);\n\ncmdline_parse_token_num_t cmd_fc_del_ipv6_5tuple_port_src =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_del_ipv6_5tuple_result, port_src,\n\t\tUINT16);\n\ncmdline_parse_token_num_t cmd_fc_del_ipv6_5tuple_port_dst =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_del_ipv6_5tuple_result, port_dst,\n\t\tUINT16);\n\ncmdline_parse_token_num_t cmd_fc_del_ipv6_5tuple_proto =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_del_ipv6_5tuple_result, proto,\n\t\tUINT32);\n\ncmdline_parse_inst_t cmd_fc_del_ipv6_5tuple = {\n\t.f = cmd_fc_del_ipv6_5tuple_parsed,\n\t.data = NULL,\n\t.help_str = \"Flow delete (IPv6 5-tuple)\",\n\t.tokens = {\n\t\t(void *) &cmd_fc_del_ipv6_5tuple_p_string,\n\t\t(void *) &cmd_fc_del_ipv6_5tuple_pipeline_id,\n\t\t(void *) &cmd_fc_del_ipv6_5tuple_flow_string,\n\t\t(void *) &cmd_fc_del_ipv6_5tuple_del_string,\n\t\t(void *) &cmd_fc_del_ipv6_5tuple_ipv6_5tuple_string,\n\t\t(void *) &cmd_fc_del_ipv6_5tuple_ip_src,\n\t\t(void *) &cmd_fc_del_ipv6_5tuple_ip_dst,\n\t\t(void *) &cmd_fc_del_ipv6_5tuple_port_src,\n\t\t(void *) &cmd_fc_del_ipv6_5tuple_port_dst,\n\t\t(void *) &cmd_fc_del_ipv6_5tuple_proto,\n\t\tNULL,\n\t},\n};\n\n/*\n * flow add default\n */\n\nstruct cmd_fc_add_default_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t flow_string;\n\tcmdline_fixed_string_t add_string;\n\tcmdline_fixed_string_t default_string;\n\tuint32_t port;\n};\n\nstatic void\ncmd_fc_add_default_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_fc_add_default_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_pipeline_fc_add_default(app, params->pipeline_id,\n\t\tparams->port);\n\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n}\n\ncmdline_parse_token_string_t cmd_fc_add_default_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_default_result, p_string,\n\t\t\"p\");\n\ncmdline_parse_token_num_t cmd_fc_add_default_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_default_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_fc_add_default_flow_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_default_result, flow_string,\n\t\t\"flow\");\n\ncmdline_parse_token_string_t cmd_fc_add_default_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_default_result, add_string,\n\t\t\"add\");\n\ncmdline_parse_token_string_t cmd_fc_add_default_default_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_add_default_result,\n\t\tdefault_string, \"default\");\n\ncmdline_parse_token_num_t cmd_fc_add_default_port =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_add_default_result, port, UINT32);\n\ncmdline_parse_inst_t cmd_fc_add_default = {\n\t.f = cmd_fc_add_default_parsed,\n\t.data = NULL,\n\t.help_str = \"Flow add default\",\n\t.tokens = {\n\t\t(void *) &cmd_fc_add_default_p_string,\n\t\t(void *) &cmd_fc_add_default_pipeline_id,\n\t\t(void *) &cmd_fc_add_default_flow_string,\n\t\t(void *) &cmd_fc_add_default_add_string,\n\t\t(void *) &cmd_fc_add_default_default_string,\n\t\t(void *) &cmd_fc_add_default_port,\n\t\tNULL,\n\t},\n};\n\n/*\n * flow del default\n */\n\nstruct cmd_fc_del_default_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t flow_string;\n\tcmdline_fixed_string_t del_string;\n\tcmdline_fixed_string_t default_string;\n};\n\nstatic void\ncmd_fc_del_default_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_fc_del_default_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_pipeline_fc_del_default(app, params->pipeline_id);\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n}\n\ncmdline_parse_token_string_t cmd_fc_del_default_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_default_result, p_string,\n\t\t\"p\");\n\ncmdline_parse_token_num_t cmd_fc_del_default_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_del_default_result, pipeline_id,\n\t\tUINT32);\n\ncmdline_parse_token_string_t cmd_fc_del_default_flow_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_default_result, flow_string,\n\t\t\"flow\");\n\ncmdline_parse_token_string_t cmd_fc_del_default_del_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_default_result, del_string,\n\t\t\"del\");\n\ncmdline_parse_token_string_t cmd_fc_del_default_default_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_del_default_result,\n\t\tdefault_string, \"default\");\n\ncmdline_parse_inst_t cmd_fc_del_default = {\n\t.f = cmd_fc_del_default_parsed,\n\t.data = NULL,\n\t.help_str = \"Flow delete default\",\n\t.tokens = {\n\t\t(void *) &cmd_fc_del_default_p_string,\n\t\t(void *) &cmd_fc_del_default_pipeline_id,\n\t\t(void *) &cmd_fc_del_default_flow_string,\n\t\t(void *) &cmd_fc_del_default_del_string,\n\t\t(void *) &cmd_fc_del_default_default_string,\n\t\tNULL,\n\t},\n};\n\n/*\n * flow ls\n */\n\nstruct cmd_fc_ls_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t pipeline_id;\n\tcmdline_fixed_string_t flow_string;\n\tcmdline_fixed_string_t ls_string;\n};\n\nstatic void\ncmd_fc_ls_parsed(\n\tvoid *parsed_result,\n\t__attribute__((unused)) struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_fc_ls_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_pipeline_fc_ls(app, params->pipeline_id);\n\tif (status != 0)\n\t\tprintf(\"Command failed\\n\");\n}\n\ncmdline_parse_token_string_t cmd_fc_ls_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_ls_result, p_string, \"p\");\n\ncmdline_parse_token_num_t cmd_fc_ls_pipeline_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_fc_ls_result, pipeline_id, UINT32);\n\ncmdline_parse_token_string_t cmd_fc_ls_flow_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_ls_result,\n\tflow_string, \"flow\");\n\ncmdline_parse_token_string_t cmd_fc_ls_ls_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_fc_ls_result, ls_string,\n\t\"ls\");\n\ncmdline_parse_inst_t cmd_fc_ls = {\n\t.f = cmd_fc_ls_parsed,\n\t.data = NULL,\n\t.help_str = \"Flow list\",\n\t.tokens = {\n\t\t(void *) &cmd_fc_ls_p_string,\n\t\t(void *) &cmd_fc_ls_pipeline_id,\n\t\t(void *) &cmd_fc_ls_flow_string,\n\t\t(void *) &cmd_fc_ls_ls_string,\n\t\tNULL,\n\t},\n};\n\nstatic cmdline_parse_ctx_t pipeline_cmds[] = {\n\t(cmdline_parse_inst_t *) &cmd_fc_add_qinq,\n\t(cmdline_parse_inst_t *) &cmd_fc_add_ipv4_5tuple,\n\t(cmdline_parse_inst_t *) &cmd_fc_add_ipv6_5tuple,\n\n\t(cmdline_parse_inst_t *) &cmd_fc_del_qinq,\n\t(cmdline_parse_inst_t *) &cmd_fc_del_ipv4_5tuple,\n\t(cmdline_parse_inst_t *) &cmd_fc_del_ipv6_5tuple,\n\n\t(cmdline_parse_inst_t *) &cmd_fc_add_default,\n\t(cmdline_parse_inst_t *) &cmd_fc_del_default,\n\n\t(cmdline_parse_inst_t *) &cmd_fc_add_qinq_all,\n\t(cmdline_parse_inst_t *) &cmd_fc_add_ipv4_5tuple_all,\n\t(cmdline_parse_inst_t *) &cmd_fc_add_ipv6_5tuple_all,\n\n\t(cmdline_parse_inst_t *) &cmd_fc_ls,\n\tNULL,\n};\n\nstatic struct pipeline_fe_ops pipeline_flow_classification_fe_ops = {\n\t.f_init = app_pipeline_fc_init,\n\t.f_free = app_pipeline_fc_free,\n\t.cmds = pipeline_cmds,\n};\n\nstruct pipeline_type pipeline_flow_classification = {\n\t.name = \"FLOW_CLASSIFICATION\",\n\t.be_ops = &pipeline_flow_classification_be_ops,\n\t.fe_ops = &pipeline_flow_classification_fe_ops,\n};\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_flow_classification.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_FLOW_CLASSIFICATION_H__\n#define __INCLUDE_PIPELINE_FLOW_CLASSIFICATION_H__\n\n#include \"pipeline.h\"\n#include \"pipeline_flow_classification_be.h\"\n\nenum flow_key_type {\n\tFLOW_KEY_QINQ,\n\tFLOW_KEY_IPV4_5TUPLE,\n\tFLOW_KEY_IPV6_5TUPLE,\n};\n\nstruct flow_key_qinq {\n\tuint16_t svlan;\n\tuint16_t cvlan;\n};\n\nstruct flow_key_ipv4_5tuple {\n\tuint32_t ip_src;\n\tuint32_t ip_dst;\n\tuint16_t port_src;\n\tuint16_t port_dst;\n\tuint32_t proto;\n};\n\nstruct flow_key_ipv6_5tuple {\n\tuint8_t ip_src[16];\n\tuint8_t ip_dst[16];\n\tuint16_t port_src;\n\tuint16_t port_dst;\n\tuint32_t proto;\n};\n\nstruct pipeline_fc_key {\n\tenum flow_key_type type;\n\tunion {\n\t\tstruct flow_key_qinq qinq;\n\t\tstruct flow_key_ipv4_5tuple ipv4_5tuple;\n\t\tstruct flow_key_ipv6_5tuple ipv6_5tuple;\n\t} key;\n};\n\nint\napp_pipeline_fc_add(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_fc_key *key,\n\tuint32_t port_id);\n\nint\napp_pipeline_fc_add_bulk(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_fc_key *key,\n\tuint32_t *port_id,\n\tuint32_t n_keys);\n\nint\napp_pipeline_fc_del(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_fc_key *key);\n\nint\napp_pipeline_fc_add_default(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id);\n\nint\napp_pipeline_fc_del_default(struct app_params *app,\n\tuint32_t pipeline_id);\n\nextern struct pipeline_type pipeline_flow_classification;\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_flow_classification_be.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n\n#include \"pipeline_flow_classification_be.h\"\n#include \"hash_func.h\"\n\nstruct pipeline_flow_classification {\n\tstruct pipeline p;\n\tpipeline_msg_req_handler custom_handlers[PIPELINE_FC_MSG_REQS];\n\n\tuint32_t n_flows;\n\tuint32_t key_offset;\n\tuint32_t key_size;\n\tuint32_t hash_offset;\n} __rte_cache_aligned;\n\nstatic void *\npipeline_fc_msg_req_custom_handler(struct pipeline *p, void *msg);\n\nstatic pipeline_msg_req_handler handlers[] = {\n\t[PIPELINE_MSG_REQ_PING] =\n\t\tpipeline_msg_req_ping_handler,\n\t[PIPELINE_MSG_REQ_STATS_PORT_IN] =\n\t\tpipeline_msg_req_stats_port_in_handler,\n\t[PIPELINE_MSG_REQ_STATS_PORT_OUT] =\n\t\tpipeline_msg_req_stats_port_out_handler,\n\t[PIPELINE_MSG_REQ_STATS_TABLE] =\n\t\tpipeline_msg_req_stats_table_handler,\n\t[PIPELINE_MSG_REQ_PORT_IN_ENABLE] =\n\t\tpipeline_msg_req_port_in_enable_handler,\n\t[PIPELINE_MSG_REQ_PORT_IN_DISABLE] =\n\t\tpipeline_msg_req_port_in_disable_handler,\n\t[PIPELINE_MSG_REQ_CUSTOM] =\n\t\tpipeline_fc_msg_req_custom_handler,\n};\n\nstatic void *\npipeline_fc_msg_req_add_handler(struct pipeline *p, void *msg);\n\nstatic void *\npipeline_fc_msg_req_add_bulk_handler(struct pipeline *p, void *msg);\n\nstatic void *\npipeline_fc_msg_req_del_handler(struct pipeline *p, void *msg);\n\nstatic void *\npipeline_fc_msg_req_add_default_handler(struct pipeline *p, void *msg);\n\nstatic void *\npipeline_fc_msg_req_del_default_handler(struct pipeline *p, void *msg);\n\nstatic pipeline_msg_req_handler custom_handlers[] = {\n\t[PIPELINE_FC_MSG_REQ_FLOW_ADD] =\n\t\tpipeline_fc_msg_req_add_handler,\n\t[PIPELINE_FC_MSG_REQ_FLOW_ADD_BULK] =\n\t\tpipeline_fc_msg_req_add_bulk_handler,\n\t[PIPELINE_FC_MSG_REQ_FLOW_DEL] =\n\t\tpipeline_fc_msg_req_del_handler,\n\t[PIPELINE_FC_MSG_REQ_FLOW_ADD_DEFAULT] =\n\t\tpipeline_fc_msg_req_add_default_handler,\n\t[PIPELINE_FC_MSG_REQ_FLOW_DEL_DEFAULT] =\n\t\tpipeline_fc_msg_req_del_default_handler,\n};\n\n/*\n * Flow table\n */\nstruct flow_table_entry {\n\tstruct rte_pipeline_table_entry head;\n};\n\nrte_table_hash_op_hash hash_func[] = {\n\thash_default_key8,\n\thash_default_key16,\n\thash_default_key24,\n\thash_default_key32,\n\thash_default_key40,\n\thash_default_key48,\n\thash_default_key56,\n\thash_default_key64\n};\n\nstatic int\npipeline_fc_parse_args(struct pipeline_flow_classification *p,\n\tstruct pipeline_params *params)\n{\n\tuint32_t n_flows_present = 0;\n\tuint32_t key_offset_present = 0;\n\tuint32_t key_size_present = 0;\n\tuint32_t hash_offset_present = 0;\n\n\tuint32_t i;\n\n\tfor (i = 0; i < params->n_args; i++) {\n\t\tchar *arg_name = params->args_name[i];\n\t\tchar *arg_value = params->args_value[i];\n\n\t\t/* n_flows */\n\t\tif (strcmp(arg_name, \"n_flows\") == 0) {\n\t\t\tif (n_flows_present)\n\t\t\t\treturn -1;\n\t\t\tn_flows_present = 1;\n\n\t\t\tp->n_flows = atoi(arg_value);\n\t\t\tif (p->n_flows == 0)\n\t\t\t\treturn -1;\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* key_offset */\n\t\tif (strcmp(arg_name, \"key_offset\") == 0) {\n\t\t\tif (key_offset_present)\n\t\t\t\treturn -1;\n\t\t\tkey_offset_present = 1;\n\n\t\t\tp->key_offset = atoi(arg_value);\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* key_size */\n\t\tif (strcmp(arg_name, \"key_size\") == 0) {\n\t\t\tif (key_size_present)\n\t\t\t\treturn -1;\n\t\t\tkey_size_present = 1;\n\n\t\t\tp->key_size = atoi(arg_value);\n\t\t\tif ((p->key_size == 0) ||\n\t\t\t\t(p->key_size > PIPELINE_FC_FLOW_KEY_MAX_SIZE) ||\n\t\t\t\t(p->key_size % 8))\n\t\t\t\treturn -1;\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* hash_offset */\n\t\tif (strcmp(arg_name, \"hash_offset\") == 0) {\n\t\t\tif (hash_offset_present)\n\t\t\t\treturn -1;\n\t\t\thash_offset_present = 1;\n\n\t\t\tp->hash_offset = atoi(arg_value);\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Unknown argument */\n\t\treturn -1;\n\t}\n\n\t/* Check that mandatory arguments are present */\n\tif ((n_flows_present == 0) ||\n\t\t(key_offset_present == 0) ||\n\t\t(key_size_present == 0) ||\n\t\t(hash_offset_present == 0))\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic void *pipeline_fc_init(struct pipeline_params *params,\n\t__rte_unused void *arg)\n{\n\tstruct pipeline *p;\n\tstruct pipeline_flow_classification *p_fc;\n\tuint32_t size, i;\n\n\t/* Check input arguments */\n\tif (params == NULL)\n\t\treturn NULL;\n\n\t/* Memory allocation */\n\tsize = RTE_CACHE_LINE_ROUNDUP(\n\t\tsizeof(struct pipeline_flow_classification));\n\tp = rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE);\n\tif (p == NULL)\n\t\treturn NULL;\n\tp_fc = (struct pipeline_flow_classification *) p;\n\n\tstrcpy(p->name, params->name);\n\tp->log_level = params->log_level;\n\n\tPLOG(p, HIGH, \"Flow classification\");\n\n\t/* Parse arguments */\n\tif (pipeline_fc_parse_args(p_fc, params))\n\t\treturn NULL;\n\n\t/* Pipeline */\n\t{\n\t\tstruct rte_pipeline_params pipeline_params = {\n\t\t\t.name = params->name,\n\t\t\t.socket_id = params->socket_id,\n\t\t\t.offset_port_id = 0,\n\t\t};\n\n\t\tp->p = rte_pipeline_create(&pipeline_params);\n\t\tif (p->p == NULL) {\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Input ports */\n\tp->n_ports_in = params->n_ports_in;\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tstruct rte_pipeline_port_in_params port_params = {\n\t\t\t.ops = pipeline_port_in_params_get_ops(\n\t\t\t\t¶ms->port_in[i]),\n\t\t\t.arg_create = pipeline_port_in_params_convert(\n\t\t\t\t¶ms->port_in[i]),\n\t\t\t.f_action = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.burst_size = params->port_in[i].burst_size,\n\t\t};\n\n\t\tint status = rte_pipeline_port_in_create(p->p,\n\t\t\t&port_params,\n\t\t\t&p->port_in_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Output ports */\n\tp->n_ports_out = params->n_ports_out;\n\tfor (i = 0; i < p->n_ports_out; i++) {\n\t\tstruct rte_pipeline_port_out_params port_params = {\n\t\t\t.ops = pipeline_port_out_params_get_ops(\n\t\t\t\t¶ms->port_out[i]),\n\t\t\t.arg_create = pipeline_port_out_params_convert(\n\t\t\t\t¶ms->port_out[i]),\n\t\t\t.f_action = NULL,\n\t\t\t.f_action_bulk = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t};\n\n\t\tint status = rte_pipeline_port_out_create(p->p,\n\t\t\t&port_params,\n\t\t\t&p->port_out_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Tables */\n\tp->n_tables = 1;\n\t{\n\t\tstruct rte_table_hash_key8_ext_params\n\t\t\ttable_hash_key8_params = {\n\t\t\t.n_entries = p_fc->n_flows,\n\t\t\t.n_entries_ext = p_fc->n_flows,\n\t\t\t.signature_offset = p_fc->hash_offset,\n\t\t\t.key_offset = p_fc->key_offset,\n\t\t\t.f_hash = hash_func[(p_fc->key_size / 8) - 1],\n\t\t\t.seed = 0,\n\t\t};\n\n\t\tstruct rte_table_hash_key16_ext_params\n\t\t\ttable_hash_key16_params = {\n\t\t\t.n_entries = p_fc->n_flows,\n\t\t\t.n_entries_ext = p_fc->n_flows,\n\t\t\t.signature_offset = p_fc->hash_offset,\n\t\t\t.key_offset = p_fc->key_offset,\n\t\t\t.f_hash = hash_func[(p_fc->key_size / 8) - 1],\n\t\t\t.seed = 0,\n\t\t};\n\n\t\tstruct rte_table_hash_ext_params\n\t\t\ttable_hash_params = {\n\t\t\t.key_size = p_fc->key_size,\n\t\t\t.n_keys = p_fc->n_flows,\n\t\t\t.n_buckets = p_fc->n_flows / 4,\n\t\t\t.n_buckets_ext = p_fc->n_flows / 4,\n\t\t\t.f_hash = hash_func[(p_fc->key_size / 8) - 1],\n\t\t\t.seed = 0,\n\t\t\t.signature_offset = p_fc->hash_offset,\n\t\t\t.key_offset = p_fc->key_offset,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = NULL, /* set below */\n\t\t\t.arg_create = NULL, /* set below */\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = sizeof(struct flow_table_entry) -\n\t\t\t\tsizeof(struct rte_pipeline_table_entry),\n\t\t};\n\n\t\tint status;\n\n\t\tswitch (p_fc->key_size) {\n\t\tcase 8:\n\t\t\ttable_params.ops = &rte_table_hash_key8_lru_ops;\n\t\t\ttable_params.arg_create = &table_hash_key8_params;\n\t\t\tbreak;\n\n\t\tcase 16:\n\t\t\ttable_params.ops = &rte_table_hash_key16_ext_ops;\n\t\t\ttable_params.arg_create = &table_hash_key16_params;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\ttable_params.ops = &rte_table_hash_ext_ops;\n\t\t\ttable_params.arg_create = &table_hash_params;\n\t\t}\n\n\t\tstatus = rte_pipeline_table_create(p->p,\n\t\t\t&table_params,\n\t\t\t&p->table_id[0]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Connecting input ports to tables */\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tint status = rte_pipeline_port_in_connect_to_table(p->p,\n\t\t\tp->port_in_id[i],\n\t\t\tp->table_id[0]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Enable input ports */\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tint status = rte_pipeline_port_in_enable(p->p,\n\t\t\tp->port_in_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Check pipeline consistency */\n\tif (rte_pipeline_check(p->p) < 0) {\n\t\trte_pipeline_free(p->p);\n\t\trte_free(p);\n\t\treturn NULL;\n\t}\n\n\t/* Message queues */\n\tp->n_msgq = params->n_msgq;\n\tfor (i = 0; i < p->n_msgq; i++)\n\t\tp->msgq_in[i] = params->msgq_in[i];\n\tfor (i = 0; i < p->n_msgq; i++)\n\t\tp->msgq_out[i] = params->msgq_out[i];\n\n\t/* Message handlers */\n\tmemcpy(p->handlers, handlers, sizeof(p->handlers));\n\tmemcpy(p_fc->custom_handlers,\n\t\tcustom_handlers,\n\t\tsizeof(p_fc->custom_handlers));\n\n\treturn p;\n}\n\nstatic int\npipeline_fc_free(void *pipeline)\n{\n\tstruct pipeline *p = (struct pipeline *) pipeline;\n\n\t/* Check input arguments */\n\tif (p == NULL)\n\t\treturn -1;\n\n\t/* Free resources */\n\trte_pipeline_free(p->p);\n\trte_free(p);\n\treturn 0;\n}\n\nstatic int\npipeline_fc_track(void *pipeline,\n\t__rte_unused uint32_t port_in,\n\tuint32_t *port_out)\n{\n\tstruct pipeline *p = (struct pipeline *) pipeline;\n\n\t/* Check input arguments */\n\tif ((p == NULL) ||\n\t\t(port_in >= p->n_ports_in) ||\n\t\t(port_out == NULL))\n\t\treturn -1;\n\n\tif (p->n_ports_in == 1) {\n\t\t*port_out = 0;\n\t\treturn 0;\n\t}\n\n\treturn -1;\n}\n\nstatic int\npipeline_fc_timer(void *pipeline)\n{\n\tstruct pipeline *p = (struct pipeline *) pipeline;\n\n\tpipeline_msg_req_handle(p);\n\trte_pipeline_flush(p->p);\n\n\treturn 0;\n}\n\nstatic void *\npipeline_fc_msg_req_custom_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_flow_classification *p_fc =\n\t\t\t(struct pipeline_flow_classification *) p;\n\tstruct pipeline_custom_msg_req *req = msg;\n\tpipeline_msg_req_handler f_handle;\n\n\tf_handle = (req->subtype < PIPELINE_FC_MSG_REQS) ?\n\t\tp_fc->custom_handlers[req->subtype] :\n\t\tpipeline_msg_req_invalid_handler;\n\n\tif (f_handle == NULL)\n\t\tf_handle = pipeline_msg_req_invalid_handler;\n\n\treturn f_handle(p, req);\n}\n\nstatic void *\npipeline_fc_msg_req_add_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_fc_add_msg_req *req = msg;\n\tstruct pipeline_fc_add_msg_rsp *rsp = msg;\n\n\tstruct flow_table_entry entry = {\n\t\t.head = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = p->port_out_id[req->port_id]},\n\t\t},\n\t};\n\n\trsp->status = rte_pipeline_table_entry_add(p->p,\n\t\tp->table_id[0],\n\t\t&req->key,\n\t\t(struct rte_pipeline_table_entry *) &entry,\n\t\t&rsp->key_found,\n\t\t(struct rte_pipeline_table_entry **) &rsp->entry_ptr);\n\n\treturn rsp;\n}\n\nstatic void *\npipeline_fc_msg_req_add_bulk_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_fc_add_bulk_msg_req *req = msg;\n\tstruct pipeline_fc_add_bulk_msg_rsp *rsp = msg;\n\tuint32_t i;\n\n\tfor (i = 0; i < req->n_keys; i++) {\n\t\tstruct pipeline_fc_add_bulk_flow_req *flow_req = &req->req[i];\n\t\tstruct pipeline_fc_add_bulk_flow_rsp *flow_rsp = &req->rsp[i];\n\n\t\tstruct flow_table_entry entry = {\n\t\t\t.head = {\n\t\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t\t{.port_id = p->port_out_id[flow_req->port_id]},\n\t\t\t},\n\t\t};\n\n\t\tint status = rte_pipeline_table_entry_add(p->p,\n\t\t\tp->table_id[0],\n\t\t\t&flow_req->key,\n\t\t\t(struct rte_pipeline_table_entry *) &entry,\n\t\t\t&flow_rsp->key_found,\n\t\t\t(struct rte_pipeline_table_entry **)\n\t\t\t\t&flow_rsp->entry_ptr);\n\n\t\tif (status)\n\t\t\tbreak;\n\t}\n\n\trsp->n_keys = i;\n\n\treturn rsp;\n}\n\nstatic void *\npipeline_fc_msg_req_del_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_fc_del_msg_req *req = msg;\n\tstruct pipeline_fc_del_msg_rsp *rsp = msg;\n\n\trsp->status = rte_pipeline_table_entry_delete(p->p,\n\t\tp->table_id[0],\n\t\t&req->key,\n\t\t&rsp->key_found,\n\t\tNULL);\n\n\treturn rsp;\n}\n\nstatic void *\npipeline_fc_msg_req_add_default_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_fc_add_default_msg_req *req = msg;\n\tstruct pipeline_fc_add_default_msg_rsp *rsp = msg;\n\n\tstruct flow_table_entry default_entry = {\n\t\t.head = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = p->port_out_id[req->port_id]},\n\t\t},\n\t};\n\n\trsp->status = rte_pipeline_table_default_entry_add(p->p,\n\t\tp->table_id[0],\n\t\t(struct rte_pipeline_table_entry *) &default_entry,\n\t\t(struct rte_pipeline_table_entry **) &rsp->entry_ptr);\n\n\treturn rsp;\n}\n\nstatic void *\npipeline_fc_msg_req_del_default_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_fc_del_default_msg_rsp *rsp = msg;\n\n\trsp->status = rte_pipeline_table_default_entry_delete(p->p,\n\t\tp->table_id[0],\n\t\tNULL);\n\n\treturn rsp;\n}\n\nstruct pipeline_be_ops pipeline_flow_classification_be_ops = {\n\t.f_init = pipeline_fc_init,\n\t.f_free = pipeline_fc_free,\n\t.f_run = NULL,\n\t.f_timer = pipeline_fc_timer,\n\t.f_track = pipeline_fc_track,\n};\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_flow_classification_be.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_FLOW_CLASSIFICATION_BE_H__\n#define __INCLUDE_PIPELINE_FLOW_CLASSIFICATION_BE_H__\n\n#include \"pipeline_common_be.h\"\n\nenum pipeline_fc_msg_req_type {\n\tPIPELINE_FC_MSG_REQ_FLOW_ADD = 0,\n\tPIPELINE_FC_MSG_REQ_FLOW_ADD_BULK,\n\tPIPELINE_FC_MSG_REQ_FLOW_DEL,\n\tPIPELINE_FC_MSG_REQ_FLOW_ADD_DEFAULT,\n\tPIPELINE_FC_MSG_REQ_FLOW_DEL_DEFAULT,\n\tPIPELINE_FC_MSG_REQS,\n};\n\n#ifndef PIPELINE_FC_FLOW_KEY_MAX_SIZE\n#define PIPELINE_FC_FLOW_KEY_MAX_SIZE 64\n#endif\n\n/*\n * MSG ADD\n */\nstruct pipeline_fc_add_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_fc_msg_req_type subtype;\n\n\tuint8_t key[PIPELINE_FC_FLOW_KEY_MAX_SIZE];\n\n\tuint32_t port_id;\n};\n\nstruct pipeline_fc_add_msg_rsp {\n\tint status;\n\tint key_found;\n\tvoid *entry_ptr;\n};\n\n/*\n * MSG ADD BULK\n */\nstruct pipeline_fc_add_bulk_flow_req {\n\tuint8_t key[PIPELINE_FC_FLOW_KEY_MAX_SIZE];\n\tuint32_t port_id;\n};\n\nstruct pipeline_fc_add_bulk_flow_rsp {\n\tint key_found;\n\tvoid *entry_ptr;\n};\n\nstruct pipeline_fc_add_bulk_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_fc_msg_req_type subtype;\n\n\tstruct pipeline_fc_add_bulk_flow_req *req;\n\tstruct pipeline_fc_add_bulk_flow_rsp *rsp;\n\tuint32_t n_keys;\n};\n\nstruct pipeline_fc_add_bulk_msg_rsp {\n\tuint32_t n_keys;\n};\n\n/*\n * MSG DEL\n */\nstruct pipeline_fc_del_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_fc_msg_req_type subtype;\n\n\tuint8_t key[PIPELINE_FC_FLOW_KEY_MAX_SIZE];\n};\n\nstruct pipeline_fc_del_msg_rsp {\n\tint status;\n\tint key_found;\n};\n\n/*\n * MSG ADD DEFAULT\n */\nstruct pipeline_fc_add_default_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_fc_msg_req_type subtype;\n\n\tuint32_t port_id;\n};\n\nstruct pipeline_fc_add_default_msg_rsp {\n\tint status;\n\tvoid *entry_ptr;\n};\n\n/*\n * MSG DEL DEFAULT\n */\nstruct pipeline_fc_del_default_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_fc_msg_req_type subtype;\n};\n\nstruct pipeline_fc_del_default_msg_rsp {\n\tint status;\n};\n\nextern struct pipeline_be_ops pipeline_flow_classification_be_ops;\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_master.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"pipeline_master.h\"\n#include \"pipeline_master_be.h\"\n\nstatic struct pipeline_fe_ops pipeline_master_fe_ops = {\n\t.f_init = NULL,\n\t.f_free = NULL,\n\t.cmds = NULL,\n};\n\nstruct pipeline_type pipeline_master = {\n\t.name = \"MASTER\",\n\t.be_ops = &pipeline_master_be_ops,\n\t.fe_ops = &pipeline_master_fe_ops,\n};\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_master.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_MASTER_H__\n#define __INCLUDE_PIPELINE_MASTER_H__\n\n#include \"pipeline.h\"\n\nextern struct pipeline_type pipeline_master;\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_master_be.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"app.h\"\n#include \"pipeline_master_be.h\"\n\nstruct pipeline_master {\n\tstruct app_params *app;\n\tstruct cmdline *cl;\n\tint script_file_done;\n} __rte_cache_aligned;\n\nstatic void*\npipeline_init(__rte_unused struct pipeline_params *params, void *arg)\n{\n\tstruct app_params *app = (struct app_params *) arg;\n\tstruct pipeline_master *p;\n\tuint32_t size;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn NULL;\n\n\t/* Memory allocation */\n\tsize = RTE_CACHE_LINE_ROUNDUP(sizeof(struct pipeline_master));\n\tp = rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE);\n\tif (p == NULL)\n\t\treturn NULL;\n\n\t/* Initialization */\n\tp->app = app;\n\n\tp->cl = cmdline_stdin_new(app->cmds, \"pipeline> \");\n\tif (p->cl == NULL) {\n\t\trte_free(p);\n\t\treturn NULL;\n\t}\n\n\tp->script_file_done = 0;\n\tif (app->script_file == NULL)\n\t\tp->script_file_done = 1;\n\n\treturn (void *) p;\n}\n\nstatic int\npipeline_free(void *pipeline)\n{\n\tstruct pipeline_master *p = (struct pipeline_master *) pipeline;\n\n\tif (p == NULL)\n\t\treturn -EINVAL;\n\n\tcmdline_stdin_exit(p->cl);\n\trte_free(p);\n\n\treturn 0;\n}\n\nstatic int\npipeline_run(void *pipeline)\n{\n\tstruct pipeline_master *p = (struct pipeline_master *) pipeline;\n\tint status;\n\n\tif (p->script_file_done == 0) {\n\t\tstruct app_params *app = p->app;\n\t\tint fd = open(app->script_file, O_RDONLY);\n\n\t\tif (fd < 0)\n\t\t\tprintf(\"Cannot open CLI script file \\\"%s\\\"\\n\",\n\t\t\t\tapp->script_file);\n\t\telse {\n\t\t\tstruct cmdline *file_cl;\n\n\t\t\tprintf(\"Running CLI script file \\\"%s\\\" ...\\n\",\n\t\t\t\tapp->script_file);\n\t\t\tfile_cl = cmdline_new(p->cl->ctx, \"\", fd, 1);\n\t\t\tcmdline_interact(file_cl);\n\t\t\tclose(fd);\n\t\t}\n\n\t\tp->script_file_done = 1;\n\t}\n\n\tstatus = cmdline_poll(p->cl);\n\tif (status < 0)\n\t\trte_panic(\"CLI poll error (%\" PRId32 \")\\n\", status);\n\telse if (status == RDLINE_EXITED) {\n\t\tcmdline_stdin_exit(p->cl);\n\t\trte_exit(0, \"Bye!\\n\");\n\t}\n\n\treturn 0;\n}\n\nstatic int\npipeline_timer(__rte_unused void *pipeline)\n{\n\treturn 0;\n}\n\nstruct pipeline_be_ops pipeline_master_be_ops = {\n\t\t.f_init = pipeline_init,\n\t\t.f_free = pipeline_free,\n\t\t.f_run = pipeline_run,\n\t\t.f_timer = pipeline_timer,\n\t\t.f_track = NULL,\n};\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_master_be.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_MASTER_BE_H__\n#define __INCLUDE_PIPELINE_MASTER_BE_H__\n\n#include \"pipeline_common_be.h\"\n\nextern struct pipeline_be_ops pipeline_master_be_ops;\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_passthrough.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"pipeline_passthrough.h\"\n#include \"pipeline_passthrough_be.h\"\n\nstatic struct pipeline_fe_ops pipeline_passthrough_fe_ops = {\n\t.f_init = NULL,\n\t.f_free = NULL,\n\t.cmds = NULL,\n};\n\nstruct pipeline_type pipeline_passthrough = {\n\t.name = \"PASS-THROUGH\",\n\t.be_ops = &pipeline_passthrough_be_ops,\n\t.fe_ops = &pipeline_passthrough_fe_ops,\n};\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_passthrough.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_PASSTHROUGH_H__\n#define __INCLUDE_PIPELINE_PASSTHROUGH_H__\n\n#include \"pipeline.h\"\n\nextern struct pipeline_type pipeline_passthrough;\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_passthrough_be.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"pipeline_passthrough_be.h\"\n#include \"pipeline_actions_common.h\"\n#include \"hash_func.h\"\n\nenum flow_key_type {\n\tFLOW_KEY_QINQ,\n\tFLOW_KEY_IPV4_5TUPLE,\n\tFLOW_KEY_IPV6_5TUPLE,\n};\n\nstruct pipeline_passthrough {\n\tstruct pipeline p;\n\n\tuint32_t key_type_valid;\n\tenum flow_key_type key_type;\n\tuint32_t key_offset_rd;\n\tuint32_t key_offset_wr;\n\tuint32_t hash_offset;\n\n\trte_table_hash_op_hash f_hash;\n\trte_pipeline_port_in_action_handler f_port_in_ah;\n} __rte_cache_aligned;\n\nstatic pipeline_msg_req_handler handlers[] = {\n\t[PIPELINE_MSG_REQ_PING] =\n\t\tpipeline_msg_req_ping_handler,\n\t[PIPELINE_MSG_REQ_STATS_PORT_IN] =\n\t\tpipeline_msg_req_stats_port_in_handler,\n\t[PIPELINE_MSG_REQ_STATS_PORT_OUT] =\n\t\tpipeline_msg_req_stats_port_out_handler,\n\t[PIPELINE_MSG_REQ_STATS_TABLE] =\n\t\tpipeline_msg_req_stats_table_handler,\n\t[PIPELINE_MSG_REQ_PORT_IN_ENABLE] =\n\t\tpipeline_msg_req_port_in_enable_handler,\n\t[PIPELINE_MSG_REQ_PORT_IN_DISABLE] =\n\t\tpipeline_msg_req_port_in_disable_handler,\n\t[PIPELINE_MSG_REQ_CUSTOM] =\n\t\tpipeline_msg_req_invalid_handler,\n};\n\nstatic inline void\npkt_work_key_qinq(\n\tstruct rte_mbuf *pkt,\n\tvoid *arg)\n{\n\tstruct pipeline_passthrough *p_pt = arg;\n\tuint32_t key_offset_rd = p_pt->key_offset_rd;\n\tuint32_t key_offset_wr = p_pt->key_offset_wr;\n\tuint32_t hash_offset = p_pt->hash_offset;\n\n\tuint64_t *key_rd = RTE_MBUF_METADATA_UINT64_PTR(pkt, key_offset_rd);\n\tuint64_t *key_wr = RTE_MBUF_METADATA_UINT64_PTR(pkt, key_offset_wr);\n\tuint32_t *hash = RTE_MBUF_METADATA_UINT32_PTR(pkt, hash_offset);\n\n\t/* Read */\n\tuint64_t key_qinq = *key_rd & rte_bswap64(0x00000FFF00000FFFLLU);\n\n\t/* Compute */\n\tuint32_t hash_qinq = p_pt->f_hash(&key_qinq, 8, 0);\n\n\t/* Write */\n\t*key_wr = key_qinq;\n\t*hash = hash_qinq;\n}\n\nstatic inline void\npkt4_work_key_qinq(\n\tstruct rte_mbuf **pkt,\n\tvoid *arg)\n{\n\tstruct pipeline_passthrough *p_pt = arg;\n\tuint32_t key_offset_rd = p_pt->key_offset_rd;\n\tuint32_t key_offset_wr = p_pt->key_offset_wr;\n\tuint32_t hash_offset = p_pt->hash_offset;\n\n\tuint64_t *key_rd0 = RTE_MBUF_METADATA_UINT64_PTR(pkt[0], key_offset_rd);\n\tuint64_t *key_wr0 = RTE_MBUF_METADATA_UINT64_PTR(pkt[0], key_offset_wr);\n\tuint32_t *hash0 = RTE_MBUF_METADATA_UINT32_PTR(pkt[0], hash_offset);\n\n\tuint64_t *key_rd1 = RTE_MBUF_METADATA_UINT64_PTR(pkt[1], key_offset_rd);\n\tuint64_t *key_wr1 = RTE_MBUF_METADATA_UINT64_PTR(pkt[1], key_offset_wr);\n\tuint32_t *hash1 = RTE_MBUF_METADATA_UINT32_PTR(pkt[1], hash_offset);\n\n\tuint64_t *key_rd2 = RTE_MBUF_METADATA_UINT64_PTR(pkt[2], key_offset_rd);\n\tuint64_t *key_wr2 = RTE_MBUF_METADATA_UINT64_PTR(pkt[2], key_offset_wr);\n\tuint32_t *hash2 = RTE_MBUF_METADATA_UINT32_PTR(pkt[2], hash_offset);\n\n\tuint64_t *key_rd3 = RTE_MBUF_METADATA_UINT64_PTR(pkt[3], key_offset_rd);\n\tuint64_t *key_wr3 = RTE_MBUF_METADATA_UINT64_PTR(pkt[3], key_offset_wr);\n\tuint32_t *hash3 = RTE_MBUF_METADATA_UINT32_PTR(pkt[3], hash_offset);\n\n\t/* Read */\n\tuint64_t key_qinq0 = *key_rd0 & rte_bswap64(0x00000FFF00000FFFLLU);\n\tuint64_t key_qinq1 = *key_rd1 & rte_bswap64(0x00000FFF00000FFFLLU);\n\tuint64_t key_qinq2 = *key_rd2 & rte_bswap64(0x00000FFF00000FFFLLU);\n\tuint64_t key_qinq3 = *key_rd3 & rte_bswap64(0x00000FFF00000FFFLLU);\n\n\t/* Compute */\n\tuint32_t hash_qinq0 = p_pt->f_hash(&key_qinq0, 8, 0);\n\tuint32_t hash_qinq1 = p_pt->f_hash(&key_qinq1, 8, 0);\n\tuint32_t hash_qinq2 = p_pt->f_hash(&key_qinq2, 8, 0);\n\tuint32_t hash_qinq3 = p_pt->f_hash(&key_qinq3, 8, 0);\n\n\t/* Write */\n\t*key_wr0 = key_qinq0;\n\t*key_wr1 = key_qinq1;\n\t*key_wr2 = key_qinq2;\n\t*key_wr3 = key_qinq3;\n\n\t*hash0 = hash_qinq0;\n\t*hash1 = hash_qinq1;\n\t*hash2 = hash_qinq2;\n\t*hash3 = hash_qinq3;\n}\n\nPIPELINE_PORT_IN_AH(port_in_ah_key_qinq, pkt_work_key_qinq, pkt4_work_key_qinq);\n\nstatic inline void\npkt_work_key_ipv4(\n\tstruct rte_mbuf *pkt,\n\tvoid *arg)\n{\n\tstruct pipeline_passthrough *p_pt = arg;\n\tuint32_t key_offset_rd = p_pt->key_offset_rd;\n\tuint32_t key_offset_wr = p_pt->key_offset_wr;\n\tuint32_t hash_offset = p_pt->hash_offset;\n\n\tuint64_t *key_rd = RTE_MBUF_METADATA_UINT64_PTR(pkt, key_offset_rd);\n\tuint64_t *key_wr = RTE_MBUF_METADATA_UINT64_PTR(pkt, key_offset_wr);\n\tuint32_t *hash = RTE_MBUF_METADATA_UINT32_PTR(pkt, hash_offset);\n\tuint64_t key_ipv4[2];\n\tuint32_t hash_ipv4;\n\n\t/* Read */\n\tkey_ipv4[0] = key_rd[0] & rte_bswap64(0x00FF0000FFFFFFFFLLU);\n\tkey_ipv4[1] = key_rd[1];\n\n\t/* Compute */\n\thash_ipv4 = p_pt->f_hash(key_ipv4, 16, 0);\n\n\t/* Write */\n\tkey_wr[0] = key_ipv4[0];\n\tkey_wr[1] = key_ipv4[1];\n\t*hash = hash_ipv4;\n}\n\nstatic inline void\npkt4_work_key_ipv4(\n\tstruct rte_mbuf **pkt,\n\tvoid *arg)\n{\n\tstruct pipeline_passthrough *p_pt = arg;\n\tuint32_t key_offset_rd = p_pt->key_offset_rd;\n\tuint32_t key_offset_wr = p_pt->key_offset_wr;\n\tuint32_t hash_offset = p_pt->hash_offset;\n\n\tuint64_t *key_rd0 = RTE_MBUF_METADATA_UINT64_PTR(pkt[0], key_offset_rd);\n\tuint64_t *key_wr0 = RTE_MBUF_METADATA_UINT64_PTR(pkt[0], key_offset_wr);\n\tuint32_t *hash0 = RTE_MBUF_METADATA_UINT32_PTR(pkt[0], hash_offset);\n\n\tuint64_t *key_rd1 = RTE_MBUF_METADATA_UINT64_PTR(pkt[1], key_offset_rd);\n\tuint64_t *key_wr1 = RTE_MBUF_METADATA_UINT64_PTR(pkt[1], key_offset_wr);\n\tuint32_t *hash1 = RTE_MBUF_METADATA_UINT32_PTR(pkt[1], hash_offset);\n\n\tuint64_t *key_rd2 = RTE_MBUF_METADATA_UINT64_PTR(pkt[2], key_offset_rd);\n\tuint64_t *key_wr2 = RTE_MBUF_METADATA_UINT64_PTR(pkt[2], key_offset_wr);\n\tuint32_t *hash2 = RTE_MBUF_METADATA_UINT32_PTR(pkt[2], hash_offset);\n\n\tuint64_t *key_rd3 = RTE_MBUF_METADATA_UINT64_PTR(pkt[3], key_offset_rd);\n\tuint64_t *key_wr3 = RTE_MBUF_METADATA_UINT64_PTR(pkt[3], key_offset_wr);\n\tuint32_t *hash3 = RTE_MBUF_METADATA_UINT32_PTR(pkt[3], hash_offset);\n\n\tuint64_t key_ipv4_0[2];\n\tuint64_t key_ipv4_1[2];\n\tuint64_t key_ipv4_2[2];\n\tuint64_t key_ipv4_3[2];\n\n\tuint32_t hash_ipv4_0;\n\tuint32_t hash_ipv4_1;\n\tuint32_t hash_ipv4_2;\n\tuint32_t hash_ipv4_3;\n\n\t/* Read */\n\tkey_ipv4_0[0] = key_rd0[0] & rte_bswap64(0x00FF0000FFFFFFFFLLU);\n\tkey_ipv4_1[0] = key_rd1[0] & rte_bswap64(0x00FF0000FFFFFFFFLLU);\n\tkey_ipv4_2[0] = key_rd2[0] & rte_bswap64(0x00FF0000FFFFFFFFLLU);\n\tkey_ipv4_3[0] = key_rd3[0] & rte_bswap64(0x00FF0000FFFFFFFFLLU);\n\n\tkey_ipv4_0[1] = key_rd0[1];\n\tkey_ipv4_1[1] = key_rd1[1];\n\tkey_ipv4_2[1] = key_rd2[1];\n\tkey_ipv4_3[1] = key_rd3[1];\n\n\t/* Compute */\n\thash_ipv4_0 = p_pt->f_hash(key_ipv4_0, 16, 0);\n\thash_ipv4_1 = p_pt->f_hash(key_ipv4_1, 16, 0);\n\thash_ipv4_2 = p_pt->f_hash(key_ipv4_2, 16, 0);\n\thash_ipv4_3 = p_pt->f_hash(key_ipv4_3, 16, 0);\n\n\t/* Write */\n\tkey_wr0[0] = key_ipv4_0[0];\n\tkey_wr1[0] = key_ipv4_1[0];\n\tkey_wr2[0] = key_ipv4_2[0];\n\tkey_wr3[0] = key_ipv4_3[0];\n\n\tkey_wr0[1] = key_ipv4_0[1];\n\tkey_wr1[1] = key_ipv4_1[1];\n\tkey_wr2[1] = key_ipv4_2[1];\n\tkey_wr3[1] = key_ipv4_3[1];\n\n\t*hash0 = hash_ipv4_0;\n\t*hash1 = hash_ipv4_1;\n\t*hash2 = hash_ipv4_2;\n\t*hash3 = hash_ipv4_3;\n}\n\nPIPELINE_PORT_IN_AH(port_in_ah_key_ipv4, pkt_work_key_ipv4, pkt4_work_key_ipv4);\n\nstatic inline void\npkt_work_key_ipv6(\n\tstruct rte_mbuf *pkt,\n\tvoid *arg)\n{\n\tstruct pipeline_passthrough *p_pt = arg;\n\tuint32_t key_offset_rd = p_pt->key_offset_rd;\n\tuint32_t key_offset_wr = p_pt->key_offset_wr;\n\tuint32_t hash_offset = p_pt->hash_offset;\n\n\tuint64_t *key_rd = RTE_MBUF_METADATA_UINT64_PTR(pkt, key_offset_rd);\n\tuint64_t *key_wr = RTE_MBUF_METADATA_UINT64_PTR(pkt, key_offset_wr);\n\tuint32_t *hash = RTE_MBUF_METADATA_UINT32_PTR(pkt, hash_offset);\n\tuint64_t key_ipv6[8];\n\tuint32_t hash_ipv6;\n\n\t/* Read */\n\tkey_ipv6[0] = key_rd[0] & rte_bswap64(0x0000FF00FFFFFFFFLLU);\n\tkey_ipv6[1] = key_rd[1];\n\tkey_ipv6[2] = key_rd[2];\n\tkey_ipv6[3] = key_rd[3];\n\tkey_ipv6[4] = key_rd[4];\n\tkey_ipv6[5] = 0;\n\tkey_ipv6[6] = 0;\n\tkey_ipv6[7] = 0;\n\n\t/* Compute */\n\thash_ipv6 = p_pt->f_hash(key_ipv6, 64, 0);\n\n\t/* Write */\n\tkey_wr[0] = key_ipv6[0];\n\tkey_wr[1] = key_ipv6[1];\n\tkey_wr[2] = key_ipv6[2];\n\tkey_wr[3] = key_ipv6[3];\n\tkey_wr[4] = key_ipv6[4];\n\tkey_wr[5] = 0;\n\tkey_wr[6] = 0;\n\tkey_wr[7] = 0;\n\t*hash = hash_ipv6;\n}\n\nstatic inline void\npkt4_work_key_ipv6(\n\tstruct rte_mbuf **pkt,\n\tvoid *arg)\n{\n\tstruct pipeline_passthrough *p_pt = arg;\n\tuint32_t key_offset_rd = p_pt->key_offset_rd;\n\tuint32_t key_offset_wr = p_pt->key_offset_wr;\n\tuint32_t hash_offset = p_pt->hash_offset;\n\n\tuint64_t *key_rd0 = RTE_MBUF_METADATA_UINT64_PTR(pkt[0], key_offset_rd);\n\tuint64_t *key_wr0 = RTE_MBUF_METADATA_UINT64_PTR(pkt[0], key_offset_wr);\n\tuint32_t *hash0 = RTE_MBUF_METADATA_UINT32_PTR(pkt[0], hash_offset);\n\n\tuint64_t *key_rd1 = RTE_MBUF_METADATA_UINT64_PTR(pkt[1], key_offset_rd);\n\tuint64_t *key_wr1 = RTE_MBUF_METADATA_UINT64_PTR(pkt[1], key_offset_wr);\n\tuint32_t *hash1 = RTE_MBUF_METADATA_UINT32_PTR(pkt[1], hash_offset);\n\n\tuint64_t *key_rd2 = RTE_MBUF_METADATA_UINT64_PTR(pkt[2], key_offset_rd);\n\tuint64_t *key_wr2 = RTE_MBUF_METADATA_UINT64_PTR(pkt[2], key_offset_wr);\n\tuint32_t *hash2 = RTE_MBUF_METADATA_UINT32_PTR(pkt[2], hash_offset);\n\n\tuint64_t *key_rd3 = RTE_MBUF_METADATA_UINT64_PTR(pkt[3], key_offset_rd);\n\tuint64_t *key_wr3 = RTE_MBUF_METADATA_UINT64_PTR(pkt[3], key_offset_wr);\n\tuint32_t *hash3 = RTE_MBUF_METADATA_UINT32_PTR(pkt[3], hash_offset);\n\n\tuint64_t key_ipv6_0[8];\n\tuint64_t key_ipv6_1[8];\n\tuint64_t key_ipv6_2[8];\n\tuint64_t key_ipv6_3[8];\n\n\tuint32_t hash_ipv6_0;\n\tuint32_t hash_ipv6_1;\n\tuint32_t hash_ipv6_2;\n\tuint32_t hash_ipv6_3;\n\n\t/* Read */\n\tkey_ipv6_0[0] = key_rd0[0] & rte_bswap64(0x0000FF00FFFFFFFFLLU);\n\tkey_ipv6_1[0] = key_rd1[0] & rte_bswap64(0x0000FF00FFFFFFFFLLU);\n\tkey_ipv6_2[0] = key_rd2[0] & rte_bswap64(0x0000FF00FFFFFFFFLLU);\n\tkey_ipv6_3[0] = key_rd3[0] & rte_bswap64(0x0000FF00FFFFFFFFLLU);\n\n\tkey_ipv6_0[1] = key_rd0[1];\n\tkey_ipv6_1[1] = key_rd1[1];\n\tkey_ipv6_2[1] = key_rd2[1];\n\tkey_ipv6_3[1] = key_rd3[1];\n\n\tkey_ipv6_0[2] = key_rd0[2];\n\tkey_ipv6_1[2] = key_rd1[2];\n\tkey_ipv6_2[2] = key_rd2[2];\n\tkey_ipv6_3[2] = key_rd3[2];\n\n\tkey_ipv6_0[3] = key_rd0[3];\n\tkey_ipv6_1[3] = key_rd1[3];\n\tkey_ipv6_2[3] = key_rd2[3];\n\tkey_ipv6_3[3] = key_rd3[3];\n\n\tkey_ipv6_0[4] = key_rd0[4];\n\tkey_ipv6_1[4] = key_rd1[4];\n\tkey_ipv6_2[4] = key_rd2[4];\n\tkey_ipv6_3[4] = key_rd3[4];\n\n\tkey_ipv6_0[5] = 0;\n\tkey_ipv6_1[5] = 0;\n\tkey_ipv6_2[5] = 0;\n\tkey_ipv6_3[5] = 0;\n\n\tkey_ipv6_0[6] = 0;\n\tkey_ipv6_1[6] = 0;\n\tkey_ipv6_2[6] = 0;\n\tkey_ipv6_3[6] = 0;\n\n\tkey_ipv6_0[7] = 0;\n\tkey_ipv6_1[7] = 0;\n\tkey_ipv6_2[7] = 0;\n\tkey_ipv6_3[7] = 0;\n\n\t/* Compute */\n\thash_ipv6_0 = p_pt->f_hash(key_ipv6_0, 64, 0);\n\thash_ipv6_1 = p_pt->f_hash(key_ipv6_1, 64, 0);\n\thash_ipv6_2 = p_pt->f_hash(key_ipv6_2, 64, 0);\n\thash_ipv6_3 = p_pt->f_hash(key_ipv6_3, 64, 0);\n\n\t/* Write */\n\tkey_wr0[0] = key_ipv6_0[0];\n\tkey_wr1[0] = key_ipv6_1[0];\n\tkey_wr2[0] = key_ipv6_2[0];\n\tkey_wr3[0] = key_ipv6_3[0];\n\n\tkey_wr0[1] = key_ipv6_0[1];\n\tkey_wr1[1] = key_ipv6_1[1];\n\tkey_wr2[1] = key_ipv6_2[1];\n\tkey_wr3[1] = key_ipv6_3[1];\n\n\tkey_wr0[2] = key_ipv6_0[2];\n\tkey_wr1[2] = key_ipv6_1[2];\n\tkey_wr2[2] = key_ipv6_2[2];\n\tkey_wr3[2] = key_ipv6_3[2];\n\n\tkey_wr0[3] = key_ipv6_0[3];\n\tkey_wr1[3] = key_ipv6_1[3];\n\tkey_wr2[3] = key_ipv6_2[3];\n\tkey_wr3[3] = key_ipv6_3[3];\n\n\tkey_wr0[4] = key_ipv6_0[4];\n\tkey_wr1[4] = key_ipv6_1[4];\n\tkey_wr2[4] = key_ipv6_2[4];\n\tkey_wr3[4] = key_ipv6_3[4];\n\n\tkey_wr0[5] = 0;\n\tkey_wr0[5] = 0;\n\tkey_wr0[5] = 0;\n\tkey_wr0[5] = 0;\n\n\tkey_wr0[6] = 0;\n\tkey_wr0[6] = 0;\n\tkey_wr0[6] = 0;\n\tkey_wr0[6] = 0;\n\n\tkey_wr0[7] = 0;\n\tkey_wr0[7] = 0;\n\tkey_wr0[7] = 0;\n\tkey_wr0[7] = 0;\n\n\t*hash0 = hash_ipv6_0;\n\t*hash1 = hash_ipv6_1;\n\t*hash2 = hash_ipv6_2;\n\t*hash3 = hash_ipv6_3;\n}\n\nPIPELINE_PORT_IN_AH(port_in_ah_key_ipv6, pkt_work_key_ipv6, pkt4_work_key_ipv6);\n\nstatic int\npipeline_passthrough_parse_args(struct pipeline_passthrough *p,\n\tstruct pipeline_params *params)\n{\n\tuint32_t key_type_present = 0;\n\tuint32_t key_offset_rd_present = 0;\n\tuint32_t key_offset_wr_present = 0;\n\tuint32_t hash_offset_present = 0;\n\tuint32_t i;\n\n\tfor (i = 0; i < params->n_args; i++) {\n\t\tchar *arg_name = params->args_name[i];\n\t\tchar *arg_value = params->args_value[i];\n\n\t\t/* key_type */\n\t\tif (strcmp(arg_name, \"key_type\") == 0) {\n\t\t\tif (key_type_present)\n\t\t\t\treturn -1;\n\t\t\tkey_type_present = 1;\n\n\t\t\tif ((strcmp(arg_value, \"q-in-q\") == 0) ||\n\t\t\t\t(strcmp(arg_value, \"qinq\") == 0))\n\t\t\t\tp->key_type = FLOW_KEY_QINQ;\n\t\t\telse if (strcmp(arg_value, \"ipv4_5tuple\") == 0)\n\t\t\t\tp->key_type = FLOW_KEY_IPV4_5TUPLE;\n\t\t\telse if (strcmp(arg_value, \"ipv6_5tuple\") == 0)\n\t\t\t\tp->key_type = FLOW_KEY_IPV6_5TUPLE;\n\t\t\telse\n\t\t\t\treturn -1;\n\n\t\t\tp->key_type_valid = 1;\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* key_offset_rd */\n\t\tif (strcmp(arg_name, \"key_offset_rd\") == 0) {\n\t\t\tif (key_offset_rd_present)\n\t\t\t\treturn -1;\n\t\t\tkey_offset_rd_present = 1;\n\n\t\t\tp->key_offset_rd = atoi(arg_value);\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* key_offset_wr */\n\t\tif (strcmp(arg_name, \"key_offset_wr\") == 0) {\n\t\t\tif (key_offset_wr_present)\n\t\t\t\treturn -1;\n\t\t\tkey_offset_wr_present = 1;\n\n\t\t\tp->key_offset_wr = atoi(arg_value);\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* hash_offset */\n\t\tif (strcmp(arg_name, \"hash_offset\") == 0) {\n\t\t\tif (hash_offset_present)\n\t\t\t\treturn -1;\n\t\t\thash_offset_present = 1;\n\n\t\t\tp->hash_offset = atoi(arg_value);\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* any other */\n\t\treturn -1;\n\t}\n\n\t/* Check that mandatory arguments are present */\n\tif ((key_offset_rd_present != key_type_present) ||\n\t\t(key_offset_wr_present != key_type_present) ||\n\t\t(hash_offset_present != key_type_present))\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic void*\npipeline_passthrough_init(struct pipeline_params *params,\n\t__rte_unused void *arg)\n{\n\tstruct pipeline *p;\n\tstruct pipeline_passthrough *p_pt;\n\tuint32_t size, i;\n\n\t/* Check input arguments */\n\tif ((params == NULL) ||\n\t\t(params->n_ports_in == 0) ||\n\t\t(params->n_ports_out == 0) ||\n\t\t(params->n_ports_in < params->n_ports_out) ||\n\t\t(params->n_ports_in % params->n_ports_out))\n\t\treturn NULL;\n\n\t/* Memory allocation */\n\tsize = RTE_CACHE_LINE_ROUNDUP(sizeof(struct pipeline_passthrough));\n\tp = rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE);\n\tp_pt = (struct pipeline_passthrough *) p;\n\tif (p == NULL)\n\t\treturn NULL;\n\n\tstrcpy(p->name, params->name);\n\tp->log_level = params->log_level;\n\n\tPLOG(p, HIGH, \"Pass-through\");\n\n\t/* Parse arguments */\n\tif (pipeline_passthrough_parse_args(p_pt, params))\n\t\treturn NULL;\n\n\tif (p_pt->key_type_valid == 0) {\n\t\tp_pt->f_hash = NULL;\n\t\tp_pt->f_port_in_ah = NULL;\n\t} else\n\t\tswitch (p_pt->key_type) {\n\t\tcase FLOW_KEY_QINQ:\n\t\t\tp_pt->f_hash = hash_default_key8;\n\t\t\tp_pt->f_port_in_ah = port_in_ah_key_qinq;\n\t\t\tbreak;\n\n\t\tcase FLOW_KEY_IPV4_5TUPLE:\n\t\t\tp_pt->f_hash = hash_default_key16;\n\t\t\tp_pt->f_port_in_ah = port_in_ah_key_ipv4;\n\t\t\tbreak;\n\n\t\tcase FLOW_KEY_IPV6_5TUPLE:\n\t\t\tp_pt->f_hash = hash_default_key64;\n\t\t\tp_pt->f_port_in_ah = port_in_ah_key_ipv6;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tp_pt->f_hash = NULL;\n\t\t\tp_pt->f_port_in_ah = NULL;\n\t\t}\n\n\t/* Pipeline */\n\t{\n\t\tstruct rte_pipeline_params pipeline_params = {\n\t\t\t.name = \"PASS-THROUGH\",\n\t\t\t.socket_id = params->socket_id,\n\t\t\t.offset_port_id = 0,\n\t\t};\n\n\t\tp->p = rte_pipeline_create(&pipeline_params);\n\t\tif (p->p == NULL) {\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Input ports */\n\tp->n_ports_in = params->n_ports_in;\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tstruct rte_pipeline_port_in_params port_params = {\n\t\t\t.ops = pipeline_port_in_params_get_ops(\n\t\t\t\t¶ms->port_in[i]),\n\t\t\t.arg_create = pipeline_port_in_params_convert(\n\t\t\t\t¶ms->port_in[i]),\n\t\t\t.f_action = p_pt->f_port_in_ah,\n\t\t\t.arg_ah = p_pt,\n\t\t\t.burst_size = params->port_in[i].burst_size,\n\t\t};\n\n\t\tint status = rte_pipeline_port_in_create(p->p,\n\t\t\t&port_params,\n\t\t\t&p->port_in_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Output ports */\n\tp->n_ports_out = params->n_ports_out;\n\tfor (i = 0; i < p->n_ports_out; i++) {\n\t\tstruct rte_pipeline_port_out_params port_params = {\n\t\t\t.ops = pipeline_port_out_params_get_ops(\n\t\t\t\t¶ms->port_out[i]),\n\t\t\t.arg_create = pipeline_port_out_params_convert(\n\t\t\t\t¶ms->port_out[i]),\n\t\t\t.f_action = NULL,\n\t\t\t.f_action_bulk = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t};\n\n\t\tint status = rte_pipeline_port_out_create(p->p,\n\t\t\t&port_params,\n\t\t\t&p->port_out_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Tables */\n\tp->n_tables = p->n_ports_in;\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_stub_ops,\n\t\t\t.arg_create = NULL,\n\t\t\t.f_action_hit = NULL,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.action_data_size = 0,\n\t\t};\n\n\t\tint status = rte_pipeline_table_create(p->p,\n\t\t\t&table_params,\n\t\t\t&p->table_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Connecting input ports to tables */\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tint status = rte_pipeline_port_in_connect_to_table(p->p,\n\t\t\tp->port_in_id[i],\n\t\t\tp->table_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Add entries to tables */\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tstruct rte_pipeline_table_entry default_entry = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = p->port_out_id[\n\t\t\t\ti / (p->n_ports_in / p->n_ports_out)]},\n\t\t};\n\n\t\tstruct rte_pipeline_table_entry *default_entry_ptr;\n\n\t\tint status = rte_pipeline_table_default_entry_add(p->p,\n\t\t\tp->table_id[i],\n\t\t\t&default_entry,\n\t\t\t&default_entry_ptr);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Enable input ports */\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tint status = rte_pipeline_port_in_enable(p->p,\n\t\t\tp->port_in_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Check pipeline consistency */\n\tif (rte_pipeline_check(p->p) < 0) {\n\t\trte_pipeline_free(p->p);\n\t\trte_free(p);\n\t\treturn NULL;\n\t}\n\n\t/* Message queues */\n\tp->n_msgq = params->n_msgq;\n\tfor (i = 0; i < p->n_msgq; i++)\n\t\tp->msgq_in[i] = params->msgq_in[i];\n\tfor (i = 0; i < p->n_msgq; i++)\n\t\tp->msgq_out[i] = params->msgq_out[i];\n\n\t/* Message handlers */\n\tmemcpy(p->handlers, handlers, sizeof(p->handlers));\n\n\treturn p;\n}\n\nstatic int\npipeline_passthrough_free(void *pipeline)\n{\n\tstruct pipeline *p = (struct pipeline *) pipeline;\n\n\t/* Check input arguments */\n\tif (p == NULL)\n\t\treturn -1;\n\n\t/* Free resources */\n\trte_pipeline_free(p->p);\n\trte_free(p);\n\treturn 0;\n}\n\nstatic int\npipeline_passthrough_timer(void *pipeline)\n{\n\tstruct pipeline *p = (struct pipeline *) pipeline;\n\n\tpipeline_msg_req_handle(p);\n\trte_pipeline_flush(p->p);\n\n\treturn 0;\n}\n\nstatic int\npipeline_passthrough_track(void *pipeline, uint32_t port_in, uint32_t *port_out)\n{\n\tstruct pipeline *p = (struct pipeline *) pipeline;\n\n\t/* Check input arguments */\n\tif ((p == NULL) ||\n\t\t(port_in >= p->n_ports_in) ||\n\t\t(port_out == NULL))\n\t\treturn -1;\n\n\t*port_out = port_in / p->n_ports_in;\n\treturn 0;\n}\n\nstruct pipeline_be_ops pipeline_passthrough_be_ops = {\n\t.f_init = pipeline_passthrough_init,\n\t.f_free = pipeline_passthrough_free,\n\t.f_run = NULL,\n\t.f_timer = pipeline_passthrough_timer,\n\t.f_track = pipeline_passthrough_track,\n};\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_passthrough_be.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_PASSTHROUGH_BE_H__\n#define __INCLUDE_PIPELINE_PASSTHROUGH_BE_H__\n\n#include \"pipeline_common_be.h\"\n\nextern struct pipeline_be_ops pipeline_passthrough_be_ops;\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_routing.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \"app.h\"\n#include \"pipeline_common_fe.h\"\n#include \"pipeline_routing.h\"\n\nstruct app_pipeline_routing_route {\n\tstruct pipeline_routing_route_key key;\n\tstruct app_pipeline_routing_route_params params;\n\tvoid *entry_ptr;\n\n\tTAILQ_ENTRY(app_pipeline_routing_route) node;\n};\n\nstruct app_pipeline_routing_arp_entry {\n\tstruct pipeline_routing_arp_key key;\n\tstruct ether_addr macaddr;\n\tvoid *entry_ptr;\n\n\tTAILQ_ENTRY(app_pipeline_routing_arp_entry) node;\n};\n\nstruct pipeline_routing {\n\t/* Parameters */\n\tuint32_t n_ports_in;\n\tuint32_t n_ports_out;\n\n\t/* Routes */\n\tTAILQ_HEAD(, app_pipeline_routing_route) routes;\n\tuint32_t n_routes;\n\n\tuint32_t default_route_present;\n\tuint32_t default_route_port_id;\n\tvoid *default_route_entry_ptr;\n\n\t/* ARP entries */\n\tTAILQ_HEAD(, app_pipeline_routing_arp_entry) arp_entries;\n\tuint32_t n_arp_entries;\n\n\tuint32_t default_arp_entry_present;\n\tuint32_t default_arp_entry_port_id;\n\tvoid *default_arp_entry_ptr;\n};\n\nstatic void *\npipeline_routing_init(struct pipeline_params *params,\n\t__rte_unused void *arg)\n{\n\tstruct pipeline_routing *p;\n\tuint32_t size;\n\n\t/* Check input arguments */\n\tif ((params == NULL) ||\n\t\t(params->n_ports_in == 0) ||\n\t\t(params->n_ports_out == 0))\n\t\treturn NULL;\n\n\t/* Memory allocation */\n\tsize = RTE_CACHE_LINE_ROUNDUP(sizeof(struct pipeline_routing));\n\tp = rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE);\n\tif (p == NULL)\n\t\treturn NULL;\n\n\t/* Initialization */\n\tp->n_ports_in = params->n_ports_in;\n\tp->n_ports_out = params->n_ports_out;\n\n\tTAILQ_INIT(&p->routes);\n\tp->n_routes = 0;\n\n\tTAILQ_INIT(&p->arp_entries);\n\tp->n_arp_entries = 0;\n\n\treturn p;\n}\n\nstatic int\napp_pipeline_routing_free(void *pipeline)\n{\n\tstruct pipeline_routing *p = pipeline;\n\n\t/* Check input arguments */\n\tif (p == NULL)\n\t\treturn -1;\n\n\t/* Free resources */\n\twhile (!TAILQ_EMPTY(&p->routes)) {\n\t\tstruct app_pipeline_routing_route *route;\n\n\t\troute = TAILQ_FIRST(&p->routes);\n\t\tTAILQ_REMOVE(&p->routes, route, node);\n\t\trte_free(route);\n\t}\n\n\twhile (!TAILQ_EMPTY(&p->arp_entries)) {\n\t\tstruct app_pipeline_routing_arp_entry *arp_entry;\n\n\t\tarp_entry = TAILQ_FIRST(&p->arp_entries);\n\t\tTAILQ_REMOVE(&p->arp_entries, arp_entry, node);\n\t\trte_free(arp_entry);\n\t}\n\n\trte_free(p);\n\treturn 0;\n}\n\nstatic struct app_pipeline_routing_route *\napp_pipeline_routing_find_route(struct pipeline_routing *p,\n\t\tconst struct pipeline_routing_route_key *key)\n{\n\tstruct app_pipeline_routing_route *it, *found;\n\n\tfound = NULL;\n\tTAILQ_FOREACH(it, &p->routes, node) {\n\t\tif ((key->type == it->key.type) &&\n\t\t\t(key->key.ipv4.ip == it->key.key.ipv4.ip) &&\n\t\t\t(key->key.ipv4.depth == it->key.key.ipv4.depth)) {\n\t\t\tfound = it;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn found;\n}\n\nstatic struct app_pipeline_routing_arp_entry *\napp_pipeline_routing_find_arp_entry(struct pipeline_routing *p,\n\t\tconst struct pipeline_routing_arp_key *key)\n{\n\tstruct app_pipeline_routing_arp_entry *it, *found;\n\n\tfound = NULL;\n\tTAILQ_FOREACH(it, &p->arp_entries, node) {\n\t\tif ((key->type == it->key.type) &&\n\t\t\t(key->key.ipv4.port_id == it->key.key.ipv4.port_id) &&\n\t\t\t(key->key.ipv4.ip == it->key.key.ipv4.ip)) {\n\t\t\tfound = it;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn found;\n}\n\nstatic void\nprint_route(const struct app_pipeline_routing_route *route)\n{\n\tif (route->key.type == PIPELINE_ROUTING_ROUTE_IPV4) {\n\t\tconst struct pipeline_routing_route_key_ipv4 *key =\n\t\t\t\t&route->key.key.ipv4;\n\n\t\tprintf(\"IP Prefix = %\" PRIu32 \".%\" PRIu32\n\t\t\t\".%\" PRIu32 \".%\" PRIu32 \"/%\" PRIu32 \" => \"\n\t\t\t\"(Port = %\" PRIu32 \", Next Hop IP = \"\n\t\t\t\"%\" PRIu32 \".%\" PRIu32 \".%\" PRIu32 \".%\" PRIu32 \")\\n\",\n\t\t\t(key->ip >> 24) & 0xFF,\n\t\t\t(key->ip >> 16) & 0xFF,\n\t\t\t(key->ip >> 8) & 0xFF,\n\t\t\tkey->ip & 0xFF,\n\n\t\t\tkey->depth,\n\t\t\troute->params.port_id,\n\n\t\t\t(route->params.ip >> 24) & 0xFF,\n\t\t\t(route->params.ip >> 16) & 0xFF,\n\t\t\t(route->params.ip >> 8) & 0xFF,\n\t\t\troute->params.ip & 0xFF);\n\t}\n}\n\nstatic void\nprint_arp_entry(const struct app_pipeline_routing_arp_entry *entry)\n{\n\tprintf(\"(Port = %\" PRIu32 \", IP = %\" PRIu32 \".%\" PRIu32\n\t\t\".%\" PRIu32 \".%\" PRIu32 \") => \"\n\t\t\"HWaddress = %02\" PRIx32 \":%02\" PRIx32 \":%02\" PRIx32\n\t\t\":%02\" PRIx32 \":%02\" PRIx32 \":%02\" PRIx32 \"\\n\",\n\t\tentry->key.key.ipv4.port_id,\n\t\t(entry->key.key.ipv4.ip >> 24) & 0xFF,\n\t\t(entry->key.key.ipv4.ip >> 16) & 0xFF,\n\t\t(entry->key.key.ipv4.ip >> 8) & 0xFF,\n\t\tentry->key.key.ipv4.ip & 0xFF,\n\n\t\tentry->macaddr.addr_bytes[0],\n\t\tentry->macaddr.addr_bytes[1],\n\t\tentry->macaddr.addr_bytes[2],\n\t\tentry->macaddr.addr_bytes[3],\n\t\tentry->macaddr.addr_bytes[4],\n\t\tentry->macaddr.addr_bytes[5]);\n}\n\nstatic int\napp_pipeline_routing_route_ls(struct app_params *app, uint32_t pipeline_id)\n{\n\tstruct pipeline_routing *p;\n\tstruct app_pipeline_routing_route *it;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -EINVAL;\n\n\tTAILQ_FOREACH(it, &p->routes, node)\n\t\tprint_route(it);\n\n\tif (p->default_route_present)\n\t\tprintf(\"Default route: port %\" PRIu32 \" (entry ptr = %p)\\n\",\n\t\t\t\tp->default_route_port_id,\n\t\t\t\tp->default_route_entry_ptr);\n\telse\n\t\tprintf(\"Default: DROP\\n\");\n\n\treturn 0;\n}\n\nint\napp_pipeline_routing_add_route(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_routing_route_key *key,\n\tstruct app_pipeline_routing_route_params *route_params)\n{\n\tstruct pipeline_routing *p;\n\n\tstruct pipeline_routing_route_add_msg_req *req;\n\tstruct pipeline_routing_route_add_msg_rsp *rsp;\n\n\tstruct app_pipeline_routing_route *entry;\n\n\tint new_entry;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(key == NULL) ||\n\t\t(route_params == NULL))\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tswitch (key->type) {\n\tcase PIPELINE_ROUTING_ROUTE_IPV4:\n\t{\n\t\tuint32_t depth = key->key.ipv4.depth;\n\t\tuint32_t netmask;\n\n\t\t/* key */\n\t\tif ((depth == 0) || (depth > 32))\n\t\t\treturn -1;\n\n\t\tnetmask = (~0) << (32 - depth);\n\t\tkey->key.ipv4.ip &= netmask;\n\n\t\t/* route params */\n\t\tif (route_params->port_id >= p->n_ports_out)\n\t\t\treturn -1;\n\t}\n\tbreak;\n\n\tdefault:\n\t\treturn -1;\n\t}\n\n\t/* Find existing rule or allocate new rule */\n\tentry = app_pipeline_routing_find_route(p, key);\n\tnew_entry = (entry == NULL);\n\tif (entry == NULL) {\n\t\tentry = rte_malloc(NULL, sizeof(*entry), RTE_CACHE_LINE_SIZE);\n\n\t\tif (entry == NULL)\n\t\t\treturn -1;\n\t}\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL) {\n\t\tif (new_entry)\n\t\t\trte_free(entry);\n\t\treturn -1;\n\t}\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_ROUTING_MSG_REQ_ROUTE_ADD;\n\tmemcpy(&req->key, key, sizeof(*key));\n\treq->flags = route_params->flags;\n\treq->port_id = route_params->port_id;\n\treq->ip = route_params->ip;\n\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL) {\n\t\tif (new_entry)\n\t\t\trte_free(entry);\n\t\treturn -1;\n\t}\n\n\t/* Read response and write entry */\n\tif (rsp->status ||\n\t\t(rsp->entry_ptr == NULL) ||\n\t\t((new_entry == 0) && (rsp->key_found == 0)) ||\n\t\t((new_entry == 1) && (rsp->key_found == 1))) {\n\t\tapp_msg_free(app, rsp);\n\t\tif (new_entry)\n\t\t\trte_free(entry);\n\t\treturn -1;\n\t}\n\n\tmemcpy(&entry->key, key, sizeof(*key));\n\tmemcpy(&entry->params, route_params, sizeof(*route_params));\n\tentry->entry_ptr = rsp->entry_ptr;\n\n\t/* Commit entry */\n\tif (new_entry) {\n\t\tTAILQ_INSERT_TAIL(&p->routes, entry, node);\n\t\tp->n_routes++;\n\t}\n\n\tprint_route(entry);\n\n\t/* Message buffer free */\n\tapp_msg_free(app, rsp);\n\treturn 0;\n}\n\nint\napp_pipeline_routing_delete_route(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_routing_route_key *key)\n{\n\tstruct pipeline_routing *p;\n\n\tstruct pipeline_routing_route_delete_msg_req *req;\n\tstruct pipeline_routing_route_delete_msg_rsp *rsp;\n\n\tstruct app_pipeline_routing_route *entry;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(key == NULL))\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tswitch (key->type) {\n\tcase PIPELINE_ROUTING_ROUTE_IPV4:\n\t{\n\t\tuint32_t depth = key->key.ipv4.depth;\n\t\tuint32_t netmask;\n\n\t\t/* key */\n\t\tif ((depth == 0) || (depth > 32))\n\t\t\treturn -1;\n\n\t\tnetmask = (~0) << (32 - depth);\n\t\tkey->key.ipv4.ip &= netmask;\n\t}\n\tbreak;\n\n\tdefault:\n\t\treturn -1;\n\t}\n\n\t/* Find rule */\n\tentry = app_pipeline_routing_find_route(p, key);\n\tif (entry == NULL)\n\t\treturn 0;\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_ROUTING_MSG_REQ_ROUTE_DEL;\n\tmemcpy(&req->key, key, sizeof(*key));\n\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Read response */\n\tif (rsp->status || !rsp->key_found) {\n\t\tapp_msg_free(app, rsp);\n\t\treturn -1;\n\t}\n\n\t/* Remove route */\n\tTAILQ_REMOVE(&p->routes, entry, node);\n\tp->n_routes--;\n\trte_free(entry);\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\nint\napp_pipeline_routing_add_default_route(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id)\n{\n\tstruct pipeline_routing *p;\n\n\tstruct pipeline_routing_route_add_default_msg_req *req;\n\tstruct pipeline_routing_route_add_default_msg_rsp *rsp;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tif (port_id >= p->n_ports_out)\n\t\treturn -1;\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_ROUTING_MSG_REQ_ROUTE_ADD_DEFAULT;\n\treq->port_id = port_id;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Read response and write route */\n\tif (rsp->status || (rsp->entry_ptr == NULL)) {\n\t\tapp_msg_free(app, rsp);\n\t\treturn -1;\n\t}\n\n\tp->default_route_port_id = port_id;\n\tp->default_route_entry_ptr = rsp->entry_ptr;\n\n\t/* Commit route */\n\tp->default_route_present = 1;\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\nint\napp_pipeline_routing_delete_default_route(struct app_params *app,\n\tuint32_t pipeline_id)\n{\n\tstruct pipeline_routing *p;\n\n\tstruct pipeline_routing_arp_delete_default_msg_req *req;\n\tstruct pipeline_routing_arp_delete_default_msg_rsp *rsp;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_ROUTING_MSG_REQ_ROUTE_DEL_DEFAULT;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Read response and write route */\n\tif (rsp->status) {\n\t\tapp_msg_free(app, rsp);\n\t\treturn -1;\n\t}\n\n\t/* Commit route */\n\tp->default_route_present = 0;\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\nstatic int\napp_pipeline_routing_arp_ls(struct app_params *app, uint32_t pipeline_id)\n{\n\tstruct pipeline_routing *p;\n\tstruct app_pipeline_routing_arp_entry *it;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -EINVAL;\n\n\tTAILQ_FOREACH(it, &p->arp_entries, node)\n\t\tprint_arp_entry(it);\n\n\tif (p->default_arp_entry_present)\n\t\tprintf(\"Default entry: port %\" PRIu32 \" (entry ptr = %p)\\n\",\n\t\t\t\tp->default_arp_entry_port_id,\n\t\t\t\tp->default_arp_entry_ptr);\n\telse\n\t\tprintf(\"Default: DROP\\n\");\n\n\treturn 0;\n}\n\nint\napp_pipeline_routing_add_arp_entry(struct app_params *app, uint32_t pipeline_id,\n\t\tstruct pipeline_routing_arp_key *key,\n\t\tstruct ether_addr *macaddr)\n{\n\tstruct pipeline_routing *p;\n\n\tstruct pipeline_routing_arp_add_msg_req *req;\n\tstruct pipeline_routing_arp_add_msg_rsp *rsp;\n\n\tstruct app_pipeline_routing_arp_entry *entry;\n\n\tint new_entry;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(key == NULL) ||\n\t\t(macaddr == NULL))\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tswitch (key->type) {\n\tcase PIPELINE_ROUTING_ARP_IPV4:\n\t{\n\t\tuint32_t port_id = key->key.ipv4.port_id;\n\n\t\t/* key */\n\t\tif (port_id >= p->n_ports_out)\n\t\t\treturn -1;\n\t}\n\tbreak;\n\n\tdefault:\n\t\treturn -1;\n\t}\n\n\t/* Find existing entry or allocate new */\n\tentry = app_pipeline_routing_find_arp_entry(p, key);\n\tnew_entry = (entry == NULL);\n\tif (entry == NULL) {\n\t\tentry = rte_malloc(NULL, sizeof(*entry), RTE_CACHE_LINE_SIZE);\n\n\t\tif (entry == NULL)\n\t\t\treturn -1;\n\t}\n\n\t/* Message buffer allocation */\n\treq = app_msg_alloc(app);\n\tif (req == NULL) {\n\t\tif (new_entry)\n\t\t\trte_free(entry);\n\t\treturn -1;\n\t}\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_ROUTING_MSG_REQ_ARP_ADD;\n\tmemcpy(&req->key, key, sizeof(*key));\n\tether_addr_copy(macaddr, &req->macaddr);\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL) {\n\t\tif (new_entry)\n\t\t\trte_free(entry);\n\t\treturn -1;\n\t}\n\n\t/* Read response and write entry */\n\tif (rsp->status ||\n\t\t(rsp->entry_ptr == NULL) ||\n\t\t((new_entry == 0) && (rsp->key_found == 0)) ||\n\t\t((new_entry == 1) && (rsp->key_found == 1))) {\n\t\tapp_msg_free(app, rsp);\n\t\tif (new_entry)\n\t\t\trte_free(entry);\n\t\treturn -1;\n\t}\n\n\tmemcpy(&entry->key, key, sizeof(*key));\n\tether_addr_copy(macaddr, &entry->macaddr);\n\tentry->entry_ptr = rsp->entry_ptr;\n\n\t/* Commit entry */\n\tif (new_entry) {\n\t\tTAILQ_INSERT_TAIL(&p->arp_entries, entry, node);\n\t\tp->n_arp_entries++;\n\t}\n\n\tprint_arp_entry(entry);\n\n\t/* Message buffer free */\n\tapp_msg_free(app, rsp);\n\treturn 0;\n}\n\nint\napp_pipeline_routing_delete_arp_entry(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_routing_arp_key *key)\n{\n\tstruct pipeline_routing *p;\n\n\tstruct pipeline_routing_arp_delete_msg_req *req;\n\tstruct pipeline_routing_arp_delete_msg_rsp *rsp;\n\n\tstruct app_pipeline_routing_arp_entry *entry;\n\n\t/* Check input arguments */\n\tif ((app == NULL) ||\n\t\t(key == NULL))\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -EINVAL;\n\n\tswitch (key->type) {\n\tcase PIPELINE_ROUTING_ARP_IPV4:\n\t{\n\t\tuint32_t port_id = key->key.ipv4.port_id;\n\n\t\t/* key */\n\t\tif (port_id >= p->n_ports_out)\n\t\t\treturn -1;\n\t}\n\tbreak;\n\n\tdefault:\n\t\treturn -1;\n\t}\n\n\t/* Find rule */\n\tentry = app_pipeline_routing_find_arp_entry(p, key);\n\tif (entry == NULL)\n\t\treturn 0;\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_ROUTING_MSG_REQ_ARP_DEL;\n\tmemcpy(&req->key, key, sizeof(*key));\n\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Read response */\n\tif (rsp->status || !rsp->key_found) {\n\t\tapp_msg_free(app, rsp);\n\t\treturn -1;\n\t}\n\n\t/* Remove entry */\n\tTAILQ_REMOVE(&p->arp_entries, entry, node);\n\tp->n_arp_entries--;\n\trte_free(entry);\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\nint\napp_pipeline_routing_add_default_arp_entry(struct app_params *app,\n\t\tuint32_t pipeline_id,\n\t\tuint32_t port_id)\n{\n\tstruct pipeline_routing *p;\n\n\tstruct pipeline_routing_arp_add_default_msg_req *req;\n\tstruct pipeline_routing_arp_add_default_msg_rsp *rsp;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -1;\n\n\tif (port_id >= p->n_ports_out)\n\t\treturn -1;\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -1;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_ROUTING_MSG_REQ_ARP_ADD_DEFAULT;\n\treq->port_id = port_id;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -1;\n\n\t/* Read response and write entry */\n\tif (rsp->status || rsp->entry_ptr == NULL) {\n\t\tapp_msg_free(app, rsp);\n\t\treturn -1;\n\t}\n\n\tp->default_arp_entry_port_id = port_id;\n\tp->default_arp_entry_ptr = rsp->entry_ptr;\n\n\t/* Commit entry */\n\tp->default_arp_entry_present = 1;\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\nint\napp_pipeline_routing_delete_default_arp_entry(struct app_params *app,\n\tuint32_t pipeline_id)\n{\n\tstruct pipeline_routing *p;\n\n\tstruct pipeline_routing_arp_delete_default_msg_req *req;\n\tstruct pipeline_routing_arp_delete_default_msg_rsp *rsp;\n\n\t/* Check input arguments */\n\tif (app == NULL)\n\t\treturn -1;\n\n\tp = app_pipeline_data_fe(app, pipeline_id);\n\tif (p == NULL)\n\t\treturn -EINVAL;\n\n\t/* Allocate and write request */\n\treq = app_msg_alloc(app);\n\tif (req == NULL)\n\t\treturn -ENOMEM;\n\n\treq->type = PIPELINE_MSG_REQ_CUSTOM;\n\treq->subtype = PIPELINE_ROUTING_MSG_REQ_ARP_DEL_DEFAULT;\n\n\t/* Send request and wait for response */\n\trsp = app_msg_send_recv(app, pipeline_id, req, MSG_TIMEOUT_DEFAULT);\n\tif (rsp == NULL)\n\t\treturn -ETIMEDOUT;\n\n\t/* Read response and write entry */\n\tif (rsp->status) {\n\t\tapp_msg_free(app, rsp);\n\t\treturn rsp->status;\n\t}\n\n\t/* Commit entry */\n\tp->default_arp_entry_present = 0;\n\n\t/* Free response */\n\tapp_msg_free(app, rsp);\n\n\treturn 0;\n}\n\n/*\n * route add\n */\n\nstruct cmd_route_add_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t p;\n\tcmdline_fixed_string_t route_string;\n\tcmdline_fixed_string_t add_string;\n\tcmdline_ipaddr_t ip;\n\tuint32_t depth;\n\tuint32_t port;\n\tcmdline_ipaddr_t nh_ip;\n};\n\nstatic void\ncmd_route_add_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_route_add_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_routing_route_key key;\n\tstruct app_pipeline_routing_route_params rt_params;\n\tint status;\n\n\t/* Create route */\n\tkey.type = PIPELINE_ROUTING_ROUTE_IPV4;\n\tkey.key.ipv4.ip = rte_bswap32((uint32_t) params->ip.addr.ipv4.s_addr);\n\tkey.key.ipv4.depth = params->depth;\n\n\trt_params.flags = 0; /* remote route */\n\trt_params.port_id = params->port;\n\trt_params.ip = rte_bswap32((uint32_t) params->nh_ip.addr.ipv4.s_addr);\n\n\tstatus = app_pipeline_routing_add_route(app,\n\t\tparams->p,\n\t\t&key,\n\t\t&rt_params);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\nstatic cmdline_parse_token_string_t cmd_route_add_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_add_result, p_string,\n\t\"p\");\n\nstatic cmdline_parse_token_num_t cmd_route_add_p =\n\tTOKEN_NUM_INITIALIZER(struct cmd_route_add_result, p, UINT32);\n\nstatic cmdline_parse_token_string_t cmd_route_add_route_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_add_result, route_string,\n\t\"route\");\n\nstatic cmdline_parse_token_string_t cmd_route_add_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_add_result, add_string,\n\t\"add\");\n\nstatic cmdline_parse_token_ipaddr_t cmd_route_add_ip =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_route_add_result, ip);\n\nstatic cmdline_parse_token_num_t cmd_route_add_depth =\n\tTOKEN_NUM_INITIALIZER(struct cmd_route_add_result, depth, UINT32);\n\nstatic cmdline_parse_token_num_t cmd_route_add_port =\n\tTOKEN_NUM_INITIALIZER(struct cmd_route_add_result, port, UINT32);\n\nstatic cmdline_parse_token_ipaddr_t cmd_route_add_nh_ip =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_route_add_result, nh_ip);\n\nstatic cmdline_parse_inst_t cmd_route_add = {\n\t.f = cmd_route_add_parsed,\n\t.data = NULL,\n\t.help_str = \"Route add\",\n\t.tokens = {\n\t\t(void *)&cmd_route_add_p_string,\n\t\t(void *)&cmd_route_add_p,\n\t\t(void *)&cmd_route_add_route_string,\n\t\t(void *)&cmd_route_add_add_string,\n\t\t(void *)&cmd_route_add_ip,\n\t\t(void *)&cmd_route_add_depth,\n\t\t(void *)&cmd_route_add_port,\n\t\t(void *)&cmd_route_add_nh_ip,\n\t\tNULL,\n\t},\n};\n\n/*\n * route del\n */\n\nstruct cmd_route_del_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t p;\n\tcmdline_fixed_string_t route_string;\n\tcmdline_fixed_string_t del_string;\n\tcmdline_ipaddr_t ip;\n\tuint32_t depth;\n};\n\nstatic void\ncmd_route_del_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_route_del_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_routing_route_key key;\n\n\tint status;\n\n\t/* Create route */\n\tkey.type = PIPELINE_ROUTING_ROUTE_IPV4;\n\tkey.key.ipv4.ip = rte_bswap32((uint32_t) params->ip.addr.ipv4.s_addr);\n\tkey.key.ipv4.depth = params->depth;\n\n\tstatus = app_pipeline_routing_delete_route(app, params->p, &key);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\nstatic cmdline_parse_token_string_t cmd_route_del_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_del_result, p_string,\n\t\"p\");\n\nstatic cmdline_parse_token_num_t cmd_route_del_p =\n\tTOKEN_NUM_INITIALIZER(struct cmd_route_del_result, p, UINT32);\n\nstatic cmdline_parse_token_string_t cmd_route_del_route_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_del_result, route_string,\n\t\"route\");\n\nstatic cmdline_parse_token_string_t cmd_route_del_del_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_del_result, del_string,\n\t\"del\");\n\nstatic cmdline_parse_token_ipaddr_t cmd_route_del_ip =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_route_del_result, ip);\n\nstatic cmdline_parse_token_num_t cmd_route_del_depth =\n\tTOKEN_NUM_INITIALIZER(struct cmd_route_del_result, depth, UINT32);\n\nstatic cmdline_parse_inst_t cmd_route_del = {\n\t.f = cmd_route_del_parsed,\n\t.data = NULL,\n\t.help_str = \"Route delete\",\n\t.tokens = {\n\t\t(void *)&cmd_route_del_p_string,\n\t\t(void *)&cmd_route_del_p,\n\t\t(void *)&cmd_route_del_route_string,\n\t\t(void *)&cmd_route_del_del_string,\n\t\t(void *)&cmd_route_del_ip,\n\t\t(void *)&cmd_route_del_depth,\n\t\tNULL,\n\t},\n};\n\n/*\n * route add default\n */\n\nstruct cmd_route_add_default_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t p;\n\tcmdline_fixed_string_t route_string;\n\tcmdline_fixed_string_t add_string;\n\tcmdline_fixed_string_t default_string;\n\tuint32_t port;\n};\n\nstatic void\ncmd_route_add_default_parsed(\n\tvoid *parsed_result,\n\t__attribute__((unused)) struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_route_add_default_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_pipeline_routing_add_default_route(app, params->p,\n\t\t\tparams->port);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\nstatic cmdline_parse_token_string_t cmd_route_add_default_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_add_default_result, p_string,\n\t\"p\");\n\nstatic cmdline_parse_token_num_t cmd_route_add_default_p =\n\tTOKEN_NUM_INITIALIZER(struct cmd_route_add_default_result, p, UINT32);\n\ncmdline_parse_token_string_t cmd_route_add_default_route_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_add_default_result,\n\t\troute_string, \"route\");\n\ncmdline_parse_token_string_t cmd_route_add_default_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_add_default_result,\n\t\tadd_string, \"add\");\n\ncmdline_parse_token_string_t cmd_route_add_default_default_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_add_default_result,\n\tdefault_string, \"default\");\n\ncmdline_parse_token_num_t cmd_route_add_default_port =\n\tTOKEN_NUM_INITIALIZER(struct cmd_route_add_default_result,\n\t\tport, UINT32);\n\ncmdline_parse_inst_t cmd_route_add_default = {\n\t.f = cmd_route_add_default_parsed,\n\t.data = NULL,\n\t.help_str = \"Route default set\",\n\t.tokens = {\n\t\t(void *)&cmd_route_add_default_p_string,\n\t\t(void *)&cmd_route_add_default_p,\n\t\t(void *)&cmd_route_add_default_route_string,\n\t\t(void *)&cmd_route_add_default_add_string,\n\t\t(void *)&cmd_route_add_default_default_string,\n\t\t(void *)&cmd_route_add_default_port,\n\t\tNULL,\n\t},\n};\n\n/*\n * route del default\n */\n\nstruct cmd_route_del_default_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t p;\n\tcmdline_fixed_string_t route_string;\n\tcmdline_fixed_string_t del_string;\n\tcmdline_fixed_string_t default_string;\n};\n\nstatic void\ncmd_route_del_default_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\t void *data)\n{\n\tstruct cmd_route_del_default_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_pipeline_routing_delete_default_route(app, params->p);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\nstatic cmdline_parse_token_string_t cmd_route_del_default_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_del_default_result, p_string,\n\t\"p\");\n\nstatic cmdline_parse_token_num_t cmd_route_del_default_p =\n\tTOKEN_NUM_INITIALIZER(struct cmd_route_del_default_result, p, UINT32);\n\nstatic cmdline_parse_token_string_t cmd_route_del_default_route_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_del_default_result,\n\t\troute_string, \"route\");\n\nstatic cmdline_parse_token_string_t cmd_route_del_default_del_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_del_default_result,\n\t\tdel_string, \"del\");\n\nstatic cmdline_parse_token_string_t cmd_route_del_default_default_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_del_default_result,\n\tdefault_string, \"default\");\n\n\nstatic cmdline_parse_inst_t cmd_route_del_default = {\n\t.f = cmd_route_del_default_parsed,\n\t.data = NULL,\n\t.help_str = \"Route default clear\",\n\t.tokens = {\n\t\t(void *)&cmd_route_del_default_p_string,\n\t\t(void *)&cmd_route_del_default_p,\n\t\t(void *)&cmd_route_del_default_route_string,\n\t\t(void *)&cmd_route_del_default_del_string,\n\t\t(void *)&cmd_route_del_default_default_string,\n\t\tNULL,\n\t},\n};\n\n/*\n * route ls\n */\n\nstruct cmd_route_ls_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t p;\n\tcmdline_fixed_string_t route_string;\n\tcmdline_fixed_string_t ls_string;\n};\n\nstatic void\ncmd_route_ls_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_route_ls_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tint status;\n\n\tstatus = app_pipeline_routing_route_ls(app, params->p);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\nstatic cmdline_parse_token_string_t cmd_route_ls_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_ls_result, p_string, \"p\");\n\nstatic cmdline_parse_token_num_t cmd_route_ls_p =\n\tTOKEN_NUM_INITIALIZER(struct cmd_route_ls_result, p, UINT32);\n\nstatic cmdline_parse_token_string_t cmd_route_ls_route_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_ls_result,\n\troute_string, \"route\");\n\nstatic cmdline_parse_token_string_t cmd_route_ls_ls_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_route_ls_result, ls_string,\n\t\"ls\");\n\nstatic cmdline_parse_inst_t cmd_route_ls = {\n\t.f = cmd_route_ls_parsed,\n\t.data = NULL,\n\t.help_str = \"Route list\",\n\t.tokens = {\n\t\t(void *)&cmd_route_ls_p_string,\n\t\t(void *)&cmd_route_ls_p,\n\t\t(void *)&cmd_route_ls_route_string,\n\t\t(void *)&cmd_route_ls_ls_string,\n\t\tNULL,\n\t},\n};\n\n/*\n * arp add\n */\n\nstruct cmd_arp_add_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t p;\n\tcmdline_fixed_string_t arp_string;\n\tcmdline_fixed_string_t add_string;\n\tuint32_t port_id;\n\tcmdline_ipaddr_t ip;\n\tstruct ether_addr macaddr;\n\n};\n\nstatic void\ncmd_arp_add_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_arp_add_result *params = parsed_result;\n\tstruct app_params *app = data;\n\n\tstruct pipeline_routing_arp_key key;\n\tint status;\n\n\tkey.type = PIPELINE_ROUTING_ARP_IPV4;\n\tkey.key.ipv4.port_id = params->port_id;\n\tkey.key.ipv4.ip = rte_cpu_to_be_32(params->ip.addr.ipv4.s_addr);\n\n\tstatus = app_pipeline_routing_add_arp_entry(app,\n\t\tparams->p,\n\t\t&key,\n\t\t¶ms->macaddr);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\nstatic cmdline_parse_token_string_t cmd_arp_add_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_add_result, p_string,\n\t\"p\");\n\nstatic cmdline_parse_token_num_t cmd_arp_add_p =\n\tTOKEN_NUM_INITIALIZER(struct cmd_arp_add_result, p, UINT32);\n\nstatic cmdline_parse_token_string_t cmd_arp_add_arp_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_add_result, arp_string, \"arp\");\n\nstatic cmdline_parse_token_string_t cmd_arp_add_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_add_result, add_string, \"add\");\n\nstatic cmdline_parse_token_num_t cmd_arp_add_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_arp_add_result, port_id, UINT32);\n\nstatic cmdline_parse_token_ipaddr_t cmd_arp_add_ip =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_arp_add_result, ip);\n\nstatic cmdline_parse_token_etheraddr_t cmd_arp_add_macaddr =\n\tTOKEN_ETHERADDR_INITIALIZER(struct cmd_arp_add_result, macaddr);\n\nstatic cmdline_parse_inst_t cmd_arp_add = {\n\t.f = cmd_arp_add_parsed,\n\t.data = NULL,\n\t.help_str = \"ARP add\",\n\t.tokens = {\n\t\t(void *)&cmd_arp_add_p_string,\n\t\t(void *)&cmd_arp_add_p,\n\t\t(void *)&cmd_arp_add_arp_string,\n\t\t(void *)&cmd_arp_add_add_string,\n\t\t(void *)&cmd_arp_add_port_id,\n\t\t(void *)&cmd_arp_add_ip,\n\t\t(void *)&cmd_arp_add_macaddr,\n\t\tNULL,\n\t},\n};\n\n/*\n * arp del\n */\n\nstruct cmd_arp_del_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t p;\n\tcmdline_fixed_string_t arp_string;\n\tcmdline_fixed_string_t del_string;\n\tuint32_t port_id;\n\tcmdline_ipaddr_t ip;\n};\n\nstatic void\ncmd_arp_del_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_arp_del_result *params = parsed_result;\n\tstruct app_params *app = data;\n\n\tstruct pipeline_routing_arp_key key;\n\tint status;\n\n\tkey.type = PIPELINE_ROUTING_ARP_IPV4;\n\tkey.key.ipv4.ip = rte_cpu_to_be_32(params->ip.addr.ipv4.s_addr);\n\tkey.key.ipv4.port_id = params->port_id;\n\n\tstatus = app_pipeline_routing_delete_arp_entry(app, params->p, &key);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\nstatic cmdline_parse_token_string_t cmd_arp_del_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_del_result, p_string,\n\t\"p\");\n\nstatic cmdline_parse_token_num_t cmd_arp_del_p =\n\tTOKEN_NUM_INITIALIZER(struct cmd_arp_del_result, p, UINT32);\n\nstatic cmdline_parse_token_string_t cmd_arp_del_arp_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_del_result, arp_string, \"arp\");\n\nstatic cmdline_parse_token_string_t cmd_arp_del_del_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_del_result, del_string, \"del\");\n\nstatic cmdline_parse_token_num_t cmd_arp_del_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_arp_del_result, port_id, UINT32);\n\nstatic cmdline_parse_token_ipaddr_t cmd_arp_del_ip =\n\tTOKEN_IPV4_INITIALIZER(struct cmd_arp_del_result, ip);\n\nstatic cmdline_parse_inst_t cmd_arp_del = {\n\t.f = cmd_arp_del_parsed,\n\t.data = NULL,\n\t.help_str = \"ARP delete\",\n\t.tokens = {\n\t\t(void *)&cmd_arp_del_p_string,\n\t\t(void *)&cmd_arp_del_p,\n\t\t(void *)&cmd_arp_del_arp_string,\n\t\t(void *)&cmd_arp_del_del_string,\n\t\t(void *)&cmd_arp_del_port_id,\n\t\t(void *)&cmd_arp_del_ip,\n\t\tNULL,\n\t},\n};\n\n/*\n * arp add default\n */\n\nstruct cmd_arp_add_default_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t p;\n\tcmdline_fixed_string_t arp_string;\n\tcmdline_fixed_string_t add_string;\n\tcmdline_fixed_string_t default_string;\n\tuint32_t port_id;\n};\n\nstatic void\ncmd_arp_add_default_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_arp_add_default_result *params = parsed_result;\n\tstruct app_params *app = data;\n\n\tint status;\n\n\tstatus = app_pipeline_routing_add_default_arp_entry(app,\n\t\tparams->p,\n\t\tparams->port_id);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\nstatic cmdline_parse_token_string_t cmd_arp_add_default_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_add_default_result, p_string,\n\t\"p\");\n\nstatic cmdline_parse_token_num_t cmd_arp_add_default_p =\n\tTOKEN_NUM_INITIALIZER(struct cmd_arp_add_default_result, p, UINT32);\n\nstatic cmdline_parse_token_string_t cmd_arp_add_default_arp_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_add_default_result, arp_string,\n\t\"arp\");\n\nstatic cmdline_parse_token_string_t cmd_arp_add_default_add_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_add_default_result, add_string,\n\t\"add\");\n\nstatic cmdline_parse_token_string_t cmd_arp_add_default_default_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_add_default_result,\n\t\tdefault_string, \"default\");\n\nstatic cmdline_parse_token_num_t cmd_arp_add_default_port_id =\n\tTOKEN_NUM_INITIALIZER(struct cmd_arp_add_default_result, port_id,\n\tUINT32);\n\nstatic cmdline_parse_inst_t cmd_arp_add_default = {\n\t.f = cmd_arp_add_default_parsed,\n\t.data = NULL,\n\t.help_str = \"ARP add default\",\n\t.tokens = {\n\t\t(void *)&cmd_arp_add_default_p_string,\n\t\t(void *)&cmd_arp_add_default_p,\n\t\t(void *)&cmd_arp_add_default_arp_string,\n\t\t(void *)&cmd_arp_add_default_add_string,\n\t\t(void *)&cmd_arp_add_default_default_string,\n\t\t(void *)&cmd_arp_add_default_port_id,\n\t\tNULL,\n\t},\n};\n\n/*\n * arp del default\n */\n\nstruct cmd_arp_del_default_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t p;\n\tcmdline_fixed_string_t arp_string;\n\tcmdline_fixed_string_t del_string;\n\tcmdline_fixed_string_t default_string;\n};\n\nstatic void\ncmd_arp_del_default_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_arp_del_default_result *params = parsed_result;\n\tstruct app_params *app = data;\n\n\tint status;\n\n\tstatus = app_pipeline_routing_delete_default_arp_entry(app, params->p);\n\n\tif (status != 0) {\n\t\tprintf(\"Command failed\\n\");\n\t\treturn;\n\t}\n}\n\nstatic cmdline_parse_token_string_t cmd_arp_del_default_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_del_default_result, p_string,\n\t\"p\");\n\nstatic cmdline_parse_token_num_t cmd_arp_del_default_p =\n\tTOKEN_NUM_INITIALIZER(struct cmd_arp_del_default_result, p, UINT32);\n\nstatic cmdline_parse_token_string_t cmd_arp_del_default_arp_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_del_default_result, arp_string,\n\t\"arp\");\n\nstatic cmdline_parse_token_string_t cmd_arp_del_default_del_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_del_default_result, del_string,\n\t\"del\");\n\nstatic cmdline_parse_token_string_t cmd_arp_del_default_default_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_del_default_result,\n\t\tdefault_string, \"default\");\n\nstatic cmdline_parse_inst_t cmd_arp_del_default = {\n\t.f = cmd_arp_del_default_parsed,\n\t.data = NULL,\n\t.help_str = \"ARP delete default\",\n\t.tokens = {\n\t\t(void *)&cmd_arp_del_default_p_string,\n\t\t(void *)&cmd_arp_del_default_p,\n\t\t(void *)&cmd_arp_del_default_arp_string,\n\t\t(void *)&cmd_arp_del_default_del_string,\n\t\t(void *)&cmd_arp_del_default_default_string,\n\t\tNULL,\n\t},\n};\n\n/*\n * arp ls\n */\n\nstruct cmd_arp_ls_result {\n\tcmdline_fixed_string_t p_string;\n\tuint32_t p;\n\tcmdline_fixed_string_t arp_string;\n\tcmdline_fixed_string_t ls_string;\n};\n\nstatic void\ncmd_arp_ls_parsed(\n\tvoid *parsed_result,\n\t__rte_unused struct cmdline *cl,\n\tvoid *data)\n{\n\tstruct cmd_arp_ls_result *params = parsed_result;\n\tstruct app_params *app = data;\n\tstruct pipeline_routing *p;\n\n\tp = app_pipeline_data_fe(app, params->p);\n\tif (p == NULL)\n\t\treturn;\n\n\tapp_pipeline_routing_arp_ls(app, params->p);\n}\n\nstatic cmdline_parse_token_string_t cmd_arp_ls_p_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_ls_result, p_string,\n\t\"p\");\n\nstatic cmdline_parse_token_num_t cmd_arp_ls_p =\n\tTOKEN_NUM_INITIALIZER(struct cmd_arp_ls_result, p, UINT32);\n\nstatic cmdline_parse_token_string_t cmd_arp_ls_arp_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_ls_result, arp_string,\n\t\"arp\");\n\nstatic cmdline_parse_token_string_t cmd_arp_ls_ls_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_arp_ls_result, ls_string,\n\t\"ls\");\n\nstatic cmdline_parse_inst_t cmd_arp_ls = {\n\t.f = cmd_arp_ls_parsed,\n\t.data = NULL,\n\t.help_str = \"ARP list\",\n\t.tokens = {\n\t\t(void *)&cmd_arp_ls_p_string,\n\t\t(void *)&cmd_arp_ls_p,\n\t\t(void *)&cmd_arp_ls_arp_string,\n\t\t(void *)&cmd_arp_ls_ls_string,\n\t\tNULL,\n\t},\n};\n\nstatic cmdline_parse_ctx_t pipeline_cmds[] = {\n\t(cmdline_parse_inst_t *)&cmd_route_add,\n\t(cmdline_parse_inst_t *)&cmd_route_del,\n\t(cmdline_parse_inst_t *)&cmd_route_add_default,\n\t(cmdline_parse_inst_t *)&cmd_route_del_default,\n\t(cmdline_parse_inst_t *)&cmd_route_ls,\n\t(cmdline_parse_inst_t *)&cmd_arp_add,\n\t(cmdline_parse_inst_t *)&cmd_arp_del,\n\t(cmdline_parse_inst_t *)&cmd_arp_add_default,\n\t(cmdline_parse_inst_t *)&cmd_arp_del_default,\n\t(cmdline_parse_inst_t *)&cmd_arp_ls,\n\tNULL,\n};\n\nstatic struct pipeline_fe_ops pipeline_routing_fe_ops = {\n\t.f_init = pipeline_routing_init,\n\t.f_free = app_pipeline_routing_free,\n\t.cmds = pipeline_cmds,\n};\n\nstruct pipeline_type pipeline_routing = {\n\t.name = \"ROUTING\",\n\t.be_ops = &pipeline_routing_be_ops,\n\t.fe_ops = &pipeline_routing_fe_ops,\n};\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_routing.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_ROUTING_H__\n#define __INCLUDE_PIPELINE_ROUTING_H__\n\n#include \"pipeline.h\"\n#include \"pipeline_routing_be.h\"\n\n/*\n * Route\n */\n\nstruct app_pipeline_routing_route_params {\n\tuint32_t flags;\n\tuint32_t port_id; /* Output port ID */\n\tuint32_t ip; /* IP address for the next hop (only for remote routes) */\n};\n\nint\napp_pipeline_routing_add_route(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_routing_route_key *key,\n\tstruct app_pipeline_routing_route_params *route_params);\n\nint\napp_pipeline_routing_delete_route(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_routing_route_key *key);\n\nint\napp_pipeline_routing_add_default_route(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id);\n\nint\napp_pipeline_routing_delete_default_route(struct app_params *app,\n\tuint32_t pipeline_id);\n\n/*\n * ARP\n */\n\nint\napp_pipeline_routing_add_arp_entry(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_routing_arp_key *key,\n\tstruct ether_addr *macaddr);\n\nint\napp_pipeline_routing_delete_arp_entry(struct app_params *app,\n\tuint32_t pipeline_id,\n\tstruct pipeline_routing_arp_key *key);\n\nint\napp_pipeline_routing_add_default_arp_entry(struct app_params *app,\n\tuint32_t pipeline_id,\n\tuint32_t port_id);\n\nint\napp_pipeline_routing_delete_default_arp_entry(struct app_params *app,\n\tuint32_t pipeline_id);\n\n/*\n * Pipeline type\n */\nextern struct pipeline_type pipeline_routing;\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_routing_be.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"pipeline_routing_be.h\"\n#include \"pipeline_actions_common.h\"\n#include \"hash_func.h\"\n\nstruct pipeline_routing {\n\tstruct pipeline p;\n\tpipeline_msg_req_handler custom_handlers[PIPELINE_ROUTING_MSG_REQS];\n\n\tuint32_t n_routes;\n\tuint32_t n_arp_entries;\n\tuint32_t ip_da_offset;\n\tuint32_t arp_key_offset;\n} __rte_cache_aligned;\n\nstatic void *\npipeline_routing_msg_req_custom_handler(struct pipeline *p, void *msg);\n\nstatic pipeline_msg_req_handler handlers[] = {\n\t[PIPELINE_MSG_REQ_PING] =\n\t\tpipeline_msg_req_ping_handler,\n\t[PIPELINE_MSG_REQ_STATS_PORT_IN] =\n\t\tpipeline_msg_req_stats_port_in_handler,\n\t[PIPELINE_MSG_REQ_STATS_PORT_OUT] =\n\t\tpipeline_msg_req_stats_port_out_handler,\n\t[PIPELINE_MSG_REQ_STATS_TABLE] =\n\t\tpipeline_msg_req_stats_table_handler,\n\t[PIPELINE_MSG_REQ_PORT_IN_ENABLE] =\n\t\tpipeline_msg_req_port_in_enable_handler,\n\t[PIPELINE_MSG_REQ_PORT_IN_DISABLE] =\n\t\tpipeline_msg_req_port_in_disable_handler,\n\t[PIPELINE_MSG_REQ_CUSTOM] =\n\t\tpipeline_routing_msg_req_custom_handler,\n};\n\nstatic void *\npipeline_routing_msg_req_route_add_handler(struct pipeline *p,\n\tvoid *msg);\n\nstatic void *\npipeline_routing_msg_req_route_del_handler(struct pipeline *p,\n\tvoid *msg);\n\nstatic void *\npipeline_routing_msg_req_route_add_default_handler(struct pipeline *p,\n\tvoid *msg);\n\nstatic void *\npipeline_routing_msg_req_route_del_default_handler(struct pipeline *p,\n\tvoid *msg);\n\nstatic void *\npipeline_routing_msg_req_arp_add_handler(struct pipeline *p,\n\tvoid *msg);\n\nstatic void *\npipeline_routing_msg_req_arp_del_handler(struct pipeline *p,\n\tvoid *msg);\n\nstatic void *\npipeline_routing_msg_req_arp_add_default_handler(struct pipeline *p,\n\tvoid *msg);\n\nstatic void *\npipeline_routing_msg_req_arp_del_default_handler(struct pipeline *p,\n\tvoid *msg);\n\nstatic pipeline_msg_req_handler custom_handlers[] = {\n\t[PIPELINE_ROUTING_MSG_REQ_ROUTE_ADD] =\n\t\tpipeline_routing_msg_req_route_add_handler,\n\t[PIPELINE_ROUTING_MSG_REQ_ROUTE_DEL] =\n\t\tpipeline_routing_msg_req_route_del_handler,\n\t[PIPELINE_ROUTING_MSG_REQ_ROUTE_ADD_DEFAULT] =\n\t\tpipeline_routing_msg_req_route_add_default_handler,\n\t[PIPELINE_ROUTING_MSG_REQ_ROUTE_DEL_DEFAULT] =\n\t\tpipeline_routing_msg_req_route_del_default_handler,\n\t[PIPELINE_ROUTING_MSG_REQ_ARP_ADD] =\n\t\tpipeline_routing_msg_req_arp_add_handler,\n\t[PIPELINE_ROUTING_MSG_REQ_ARP_DEL] =\n\t\tpipeline_routing_msg_req_arp_del_handler,\n\t[PIPELINE_ROUTING_MSG_REQ_ARP_ADD_DEFAULT] =\n\t\tpipeline_routing_msg_req_arp_add_default_handler,\n\t[PIPELINE_ROUTING_MSG_REQ_ARP_DEL_DEFAULT] =\n\t\tpipeline_routing_msg_req_arp_del_default_handler,\n};\n\n/*\n * Routing table\n */\nstruct routing_table_entry {\n\tstruct rte_pipeline_table_entry head;\n\tuint32_t flags;\n\tuint32_t port_id; /* Output port ID */\n\tuint32_t ip; /* Next hop IP address (only valid for remote routes) */\n};\n\nstatic inline void\npkt_work_routing(\n\tstruct rte_mbuf *pkt,\n\tstruct rte_pipeline_table_entry *table_entry,\n\tvoid *arg)\n{\n\tstruct routing_table_entry *entry =\n\t\t(struct routing_table_entry *) table_entry;\n\tstruct pipeline_routing *p_rt = arg;\n\n\tstruct pipeline_routing_arp_key_ipv4 *arp_key =\n\t\t(struct pipeline_routing_arp_key_ipv4 *)\n\t\tRTE_MBUF_METADATA_UINT8_PTR(pkt, p_rt->arp_key_offset);\n\tuint32_t ip = RTE_MBUF_METADATA_UINT32(pkt, p_rt->ip_da_offset);\n\n\tarp_key->port_id = entry->port_id;\n\tarp_key->ip = entry->ip;\n\tif (entry->flags & PIPELINE_ROUTING_ROUTE_LOCAL)\n\t\tarp_key->ip = ip;\n}\n\nstatic inline void\npkt4_work_routing(\n\tstruct rte_mbuf **pkts,\n\tstruct rte_pipeline_table_entry **table_entries,\n\tvoid *arg)\n{\n\tstruct routing_table_entry *entry0 =\n\t\t(struct routing_table_entry *) table_entries[0];\n\tstruct routing_table_entry *entry1 =\n\t\t(struct routing_table_entry *) table_entries[1];\n\tstruct routing_table_entry *entry2 =\n\t\t(struct routing_table_entry *) table_entries[2];\n\tstruct routing_table_entry *entry3 =\n\t\t(struct routing_table_entry *) table_entries[3];\n\tstruct pipeline_routing *p_rt = arg;\n\n\tstruct pipeline_routing_arp_key_ipv4 *arp_key0 =\n\t\t(struct pipeline_routing_arp_key_ipv4 *)\n\t\tRTE_MBUF_METADATA_UINT8_PTR(pkts[0], p_rt->arp_key_offset);\n\tstruct pipeline_routing_arp_key_ipv4 *arp_key1 =\n\t\t(struct pipeline_routing_arp_key_ipv4 *)\n\t\tRTE_MBUF_METADATA_UINT8_PTR(pkts[1], p_rt->arp_key_offset);\n\tstruct pipeline_routing_arp_key_ipv4 *arp_key2 =\n\t\t(struct pipeline_routing_arp_key_ipv4 *)\n\t\tRTE_MBUF_METADATA_UINT8_PTR(pkts[2], p_rt->arp_key_offset);\n\tstruct pipeline_routing_arp_key_ipv4 *arp_key3 =\n\t\t(struct pipeline_routing_arp_key_ipv4 *)\n\t\tRTE_MBUF_METADATA_UINT8_PTR(pkts[3], p_rt->arp_key_offset);\n\n\tuint32_t ip0 = RTE_MBUF_METADATA_UINT32(pkts[0], p_rt->ip_da_offset);\n\tuint32_t ip1 = RTE_MBUF_METADATA_UINT32(pkts[1], p_rt->ip_da_offset);\n\tuint32_t ip2 = RTE_MBUF_METADATA_UINT32(pkts[2], p_rt->ip_da_offset);\n\tuint32_t ip3 = RTE_MBUF_METADATA_UINT32(pkts[3], p_rt->ip_da_offset);\n\n\tarp_key0->port_id = entry0->port_id;\n\tarp_key1->port_id = entry1->port_id;\n\tarp_key2->port_id = entry2->port_id;\n\tarp_key3->port_id = entry3->port_id;\n\n\tarp_key0->ip = entry0->ip;\n\tif (entry0->flags & PIPELINE_ROUTING_ROUTE_LOCAL)\n\t\tarp_key0->ip = ip0;\n\n\tarp_key1->ip = entry1->ip;\n\tif (entry1->flags & PIPELINE_ROUTING_ROUTE_LOCAL)\n\t\tarp_key1->ip = ip1;\n\n\tarp_key2->ip = entry2->ip;\n\tif (entry2->flags & PIPELINE_ROUTING_ROUTE_LOCAL)\n\t\tarp_key2->ip = ip2;\n\n\tarp_key3->ip = entry3->ip;\n\tif (entry3->flags & PIPELINE_ROUTING_ROUTE_LOCAL)\n\t\tarp_key3->ip = ip3;\n}\n\nPIPELINE_TABLE_AH_HIT(routing_table_ah_hit,\n\tpkt_work_routing,\n\tpkt4_work_routing);\n\n/*\n * ARP table\n */\nstruct arp_table_entry {\n\tstruct rte_pipeline_table_entry head;\n\tuint64_t macaddr;\n};\n\nstatic inline void\npkt_work_arp(\n\tstruct rte_mbuf *pkt,\n\tstruct rte_pipeline_table_entry *table_entry,\n\t__rte_unused void *arg)\n{\n\tstruct arp_table_entry *entry = (struct arp_table_entry *) table_entry;\n\n\t/* Read: pkt buffer - mbuf */\n\tuint8_t *raw = rte_pktmbuf_mtod(pkt, uint8_t *);\n\n\t/* Read: table entry */\n\tuint64_t mac_addr_dst = entry->macaddr;\n\tuint64_t mac_addr_src = 0;\n\n\t/* Compute: Ethernet header */\n\tuint64_t slab0 = mac_addr_dst | (mac_addr_src << 48);\n\tuint32_t slab1 = mac_addr_src >> 16;\n\n\t/* Write: pkt buffer - pkt headers */\n\t*((uint64_t *) raw) = slab0;\n\t*((uint32_t *) (raw + 8)) = slab1;\n}\n\nstatic inline void\npkt4_work_arp(\n\tstruct rte_mbuf **pkts,\n\tstruct rte_pipeline_table_entry **table_entries,\n\t__rte_unused void *arg)\n{\n\tstruct arp_table_entry *entry0 =\n\t\t(struct arp_table_entry *) table_entries[0];\n\tstruct arp_table_entry *entry1 =\n\t\t(struct arp_table_entry *) table_entries[1];\n\tstruct arp_table_entry *entry2 =\n\t\t(struct arp_table_entry *) table_entries[2];\n\tstruct arp_table_entry *entry3 =\n\t\t(struct arp_table_entry *) table_entries[3];\n\n\t/* Read: pkt buffer - mbuf */\n\tuint8_t *raw0 = rte_pktmbuf_mtod(pkts[0], uint8_t *);\n\tuint8_t *raw1 = rte_pktmbuf_mtod(pkts[1], uint8_t *);\n\tuint8_t *raw2 = rte_pktmbuf_mtod(pkts[2], uint8_t *);\n\tuint8_t *raw3 = rte_pktmbuf_mtod(pkts[3], uint8_t *);\n\n\t/* Read: table entry */\n\tuint64_t mac_addr_dst0 = entry0->macaddr;\n\tuint64_t mac_addr_dst1 = entry1->macaddr;\n\tuint64_t mac_addr_dst2 = entry2->macaddr;\n\tuint64_t mac_addr_dst3 = entry3->macaddr;\n\n\tuint64_t mac_addr_src0 = 0;\n\tuint64_t mac_addr_src1 = 0;\n\tuint64_t mac_addr_src2 = 0;\n\tuint64_t mac_addr_src3 = 0;\n\n\t/* Compute: Ethernet header */\n\tuint64_t pkt0_slab0 = mac_addr_dst0 | (mac_addr_src0 << 48);\n\tuint64_t pkt1_slab0 = mac_addr_dst1 | (mac_addr_src1 << 48);\n\tuint64_t pkt2_slab0 = mac_addr_dst2 | (mac_addr_src2 << 48);\n\tuint64_t pkt3_slab0 = mac_addr_dst3 | (mac_addr_src3 << 48);\n\n\tuint32_t pkt0_slab1 = mac_addr_src0 >> 16;\n\tuint32_t pkt1_slab1 = mac_addr_src1 >> 16;\n\tuint32_t pkt2_slab1 = mac_addr_src2 >> 16;\n\tuint32_t pkt3_slab1 = mac_addr_src3 >> 16;\n\n\t/* Write: pkt buffer - pkt headers */\n\t*((uint64_t *) raw0) = pkt0_slab0;\n\t*((uint32_t *) (raw0 + 8)) = pkt0_slab1;\n\t*((uint64_t *) raw1) = pkt1_slab0;\n\t*((uint32_t *) (raw1 + 8)) = pkt1_slab1;\n\t*((uint64_t *) raw2) = pkt2_slab0;\n\t*((uint32_t *) (raw2 + 8)) = pkt2_slab1;\n\t*((uint64_t *) raw3) = pkt3_slab0;\n\t*((uint32_t *) (raw3 + 8)) = pkt3_slab1;\n}\n\nPIPELINE_TABLE_AH_HIT(arp_table_ah_hit,\n\tpkt_work_arp,\n\tpkt4_work_arp);\n\nstatic int\npipeline_routing_parse_args(struct pipeline_routing *p,\n\tstruct pipeline_params *params)\n{\n\tuint32_t n_routes_present = 0;\n\tuint32_t n_arp_entries_present = 0;\n\tuint32_t ip_da_offset_present = 0;\n\tuint32_t arp_key_offset_present = 0;\n\tuint32_t i;\n\n\tfor (i = 0; i < params->n_args; i++) {\n\t\tchar *arg_name = params->args_name[i];\n\t\tchar *arg_value = params->args_value[i];\n\n\t\t/* n_routes */\n\t\tif (strcmp(arg_name, \"n_routes\") == 0) {\n\t\t\tif (n_routes_present)\n\t\t\t\treturn -1;\n\t\t\tn_routes_present = 1;\n\n\t\t\tp->n_routes = atoi(arg_value);\n\t\t\tif (p->n_routes == 0)\n\t\t\t\treturn -1;\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* n_arp_entries */\n\t\tif (strcmp(arg_name, \"n_arp_entries\") == 0) {\n\t\t\tif (n_arp_entries_present)\n\t\t\t\treturn -1;\n\t\t\tn_arp_entries_present = 1;\n\n\t\t\tp->n_arp_entries = atoi(arg_value);\n\t\t\tif (p->n_arp_entries == 0)\n\t\t\t\treturn -1;\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* ip_da_offset */\n\t\tif (strcmp(arg_name, \"ip_da_offset\") == 0) {\n\t\t\tif (ip_da_offset_present)\n\t\t\t\treturn -1;\n\t\t\tip_da_offset_present = 1;\n\n\t\t\tp->ip_da_offset = atoi(arg_value);\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* arp_key_offset */\n\t\tif (strcmp(arg_name, \"arp_key_offset\") == 0) {\n\t\t\tif (arp_key_offset_present)\n\t\t\t\treturn -1;\n\t\t\tarp_key_offset_present = 1;\n\n\t\t\tp->arp_key_offset = atoi(arg_value);\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* any other */\n\t\treturn -1;\n\t}\n\n\t/* Check that mandatory arguments are present */\n\tif ((n_routes_present == 0) ||\n\t\t(n_arp_entries_present == 0) ||\n\t\t(ip_da_offset_present == 0) ||\n\t\t(n_arp_entries_present && (arp_key_offset_present == 0)))\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic void *\npipeline_routing_init(struct pipeline_params *params,\n\t__rte_unused void *arg)\n{\n\tstruct pipeline *p;\n\tstruct pipeline_routing *p_rt;\n\tuint32_t size, i;\n\n\t/* Check input arguments */\n\tif ((params == NULL) ||\n\t\t(params->n_ports_in == 0) ||\n\t\t(params->n_ports_out == 0))\n\t\treturn NULL;\n\n\t/* Memory allocation */\n\tsize = RTE_CACHE_LINE_ROUNDUP(sizeof(struct pipeline_routing));\n\tp = rte_zmalloc(NULL, size, RTE_CACHE_LINE_SIZE);\n\tp_rt = (struct pipeline_routing *) p;\n\tif (p == NULL)\n\t\treturn NULL;\n\n\tstrcpy(p->name, params->name);\n\tp->log_level = params->log_level;\n\n\tPLOG(p, HIGH, \"Routing\");\n\n\t/* Parse arguments */\n\tif (pipeline_routing_parse_args(p_rt, params))\n\t\treturn NULL;\n\n\t/* Pipeline */\n\t{\n\t\tstruct rte_pipeline_params pipeline_params = {\n\t\t\t.name = params->name,\n\t\t\t.socket_id = params->socket_id,\n\t\t\t.offset_port_id = 0,\n\t\t};\n\n\t\tp->p = rte_pipeline_create(&pipeline_params);\n\t\tif (p->p == NULL) {\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Input ports */\n\tp->n_ports_in = params->n_ports_in;\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tstruct rte_pipeline_port_in_params port_params = {\n\t\t\t.ops = pipeline_port_in_params_get_ops(\n\t\t\t\t¶ms->port_in[i]),\n\t\t\t.arg_create = pipeline_port_in_params_convert(\n\t\t\t\t¶ms->port_in[i]),\n\t\t\t.f_action = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t\t.burst_size = params->port_in[i].burst_size,\n\t\t};\n\n\t\tint status = rte_pipeline_port_in_create(p->p,\n\t\t\t&port_params,\n\t\t\t&p->port_in_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Output ports */\n\tp->n_ports_out = params->n_ports_out;\n\tfor (i = 0; i < p->n_ports_out; i++) {\n\t\tstruct rte_pipeline_port_out_params port_params = {\n\t\t\t.ops = pipeline_port_out_params_get_ops(\n\t\t\t\t¶ms->port_out[i]),\n\t\t\t.arg_create = pipeline_port_out_params_convert(\n\t\t\t\t¶ms->port_out[i]),\n\t\t\t.f_action = NULL,\n\t\t\t.f_action_bulk = NULL,\n\t\t\t.arg_ah = NULL,\n\t\t};\n\n\t\tint status = rte_pipeline_port_out_create(p->p,\n\t\t\t&port_params,\n\t\t\t&p->port_out_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Routing table */\n\tp->n_tables = 1;\n\t{\n\t\tstruct rte_table_lpm_params table_lpm_params = {\n\t\t\t.n_rules = p_rt->n_routes,\n\t\t\t.entry_unique_size = sizeof(struct routing_table_entry),\n\t\t\t.offset = p_rt->ip_da_offset,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t\t.ops = &rte_table_lpm_ops,\n\t\t\t\t.arg_create = &table_lpm_params,\n\t\t\t\t.f_action_hit = routing_table_ah_hit,\n\t\t\t\t.f_action_miss = NULL,\n\t\t\t\t.arg_ah = p_rt,\n\t\t\t\t.action_data_size =\n\t\t\t\t\tsizeof(struct routing_table_entry) -\n\t\t\t\t\tsizeof(struct rte_pipeline_table_entry),\n\t\t\t};\n\n\t\tint status;\n\n\t\tstatus = rte_pipeline_table_create(p->p,\n\t\t\t&table_params,\n\t\t\t&p->table_id[0]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* ARP table configuration */\n\tif (p_rt->n_arp_entries) {\n\t\tstruct rte_table_hash_key8_ext_params table_arp_params = {\n\t\t\t.n_entries = p_rt->n_arp_entries,\n\t\t\t.n_entries_ext = p_rt->n_arp_entries,\n\t\t\t.f_hash = hash_default_key8,\n\t\t\t.seed = 0,\n\t\t\t.signature_offset = 0, /* Unused */\n\t\t\t.key_offset = p_rt->arp_key_offset,\n\t\t};\n\n\t\tstruct rte_pipeline_table_params table_params = {\n\t\t\t.ops = &rte_table_hash_key8_ext_dosig_ops,\n\t\t\t.arg_create = &table_arp_params,\n\t\t\t.f_action_hit = arp_table_ah_hit,\n\t\t\t.f_action_miss = NULL,\n\t\t\t.arg_ah = p_rt,\n\t\t\t.action_data_size = sizeof(struct arp_table_entry) -\n\t\t\t\tsizeof(struct rte_pipeline_table_entry),\n\t\t};\n\n\t\tint status;\n\n\t\tstatus = rte_pipeline_table_create(p->p,\n\t\t\t&table_params,\n\t\t\t&p->table_id[1]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\n\t\tp->n_tables++;\n\t}\n\n\t/* Connecting input ports to tables */\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tint status = rte_pipeline_port_in_connect_to_table(p->p,\n\t\t\tp->port_in_id[i],\n\t\t\tp->table_id[0]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Enable input ports */\n\tfor (i = 0; i < p->n_ports_in; i++) {\n\t\tint status = rte_pipeline_port_in_enable(p->p,\n\t\t\tp->port_in_id[i]);\n\n\t\tif (status) {\n\t\t\trte_pipeline_free(p->p);\n\t\t\trte_free(p);\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* Check pipeline consistency */\n\tif (rte_pipeline_check(p->p) < 0) {\n\t\trte_pipeline_free(p->p);\n\t\trte_free(p);\n\t\treturn NULL;\n\t}\n\n\t/* Message queues */\n\tp->n_msgq = params->n_msgq;\n\tfor (i = 0; i < p->n_msgq; i++)\n\t\tp->msgq_in[i] = params->msgq_in[i];\n\tfor (i = 0; i < p->n_msgq; i++)\n\t\tp->msgq_out[i] = params->msgq_out[i];\n\n\t/* Message handlers */\n\tmemcpy(p->handlers, handlers, sizeof(p->handlers));\n\tmemcpy(p_rt->custom_handlers,\n\t\tcustom_handlers,\n\t\tsizeof(p_rt->custom_handlers));\n\n\treturn p;\n}\n\nstatic int\npipeline_routing_free(void *pipeline)\n{\n\tstruct pipeline *p = (struct pipeline *) pipeline;\n\n\t/* Check input arguments */\n\tif (p == NULL)\n\t\treturn -1;\n\n\t/* Free resources */\n\trte_pipeline_free(p->p);\n\trte_free(p);\n\treturn 0;\n}\n\nstatic int\npipeline_routing_track(void *pipeline,\n\t__rte_unused uint32_t port_in,\n\tuint32_t *port_out)\n{\n\tstruct pipeline *p = (struct pipeline *) pipeline;\n\n\t/* Check input arguments */\n\tif ((p == NULL) ||\n\t\t(port_in >= p->n_ports_in) ||\n\t\t(port_out == NULL))\n\t\treturn -1;\n\n\tif (p->n_ports_in == 1) {\n\t\t*port_out = 0;\n\t\treturn 0;\n\t}\n\n\treturn -1;\n}\n\nstatic int\npipeline_routing_timer(void *pipeline)\n{\n\tstruct pipeline *p = (struct pipeline *) pipeline;\n\n\tpipeline_msg_req_handle(p);\n\trte_pipeline_flush(p->p);\n\n\treturn 0;\n}\n\nvoid *\npipeline_routing_msg_req_custom_handler(struct pipeline *p,\n\tvoid *msg)\n{\n\tstruct pipeline_routing *p_rt = (struct pipeline_routing *) p;\n\tstruct pipeline_custom_msg_req *req = msg;\n\tpipeline_msg_req_handler f_handle;\n\n\tf_handle = (req->subtype < PIPELINE_ROUTING_MSG_REQS) ?\n\t\tp_rt->custom_handlers[req->subtype] :\n\t\tpipeline_msg_req_invalid_handler;\n\n\tif (f_handle == NULL)\n\t\tf_handle = pipeline_msg_req_invalid_handler;\n\n\treturn f_handle(p, req);\n}\n\nvoid *\npipeline_routing_msg_req_route_add_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_routing_route_add_msg_req *req = msg;\n\tstruct pipeline_routing_route_add_msg_rsp *rsp = msg;\n\n\tstruct rte_table_lpm_key key = {\n\t\t.ip = req->key.key.ipv4.ip,\n\t\t.depth = req->key.key.ipv4.depth,\n\t};\n\n\tstruct routing_table_entry entry = {\n\t\t.head = {\n\t\t\t.action = RTE_PIPELINE_ACTION_TABLE,\n\t\t\t{.table_id = p->table_id[1]},\n\t\t},\n\n\t\t.flags = req->flags,\n\t\t.port_id = req->port_id,\n\t\t.ip = rte_bswap32(req->ip),\n\t};\n\n\tif (req->key.type != PIPELINE_ROUTING_ROUTE_IPV4) {\n\t\trsp->status = -1;\n\t\treturn rsp;\n\t}\n\n\trsp->status = rte_pipeline_table_entry_add(p->p,\n\t\tp->table_id[0],\n\t\t&key,\n\t\t(struct rte_pipeline_table_entry *) &entry,\n\t\t&rsp->key_found,\n\t\t(struct rte_pipeline_table_entry **) &rsp->entry_ptr);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_routing_msg_req_route_del_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_routing_route_delete_msg_req *req = msg;\n\tstruct pipeline_routing_route_delete_msg_rsp *rsp = msg;\n\n\tstruct rte_table_lpm_key key = {\n\t\t.ip = req->key.key.ipv4.ip,\n\t\t.depth = req->key.key.ipv4.depth,\n\t};\n\n\tif (req->key.type != PIPELINE_ROUTING_ROUTE_IPV4) {\n\t\trsp->status = -1;\n\t\treturn rsp;\n\t}\n\n\trsp->status = rte_pipeline_table_entry_delete(p->p,\n\t\tp->table_id[0],\n\t\t&key,\n\t\t&rsp->key_found,\n\t\tNULL);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_routing_msg_req_route_add_default_handler(struct pipeline *p,\n\tvoid *msg)\n{\n\tstruct pipeline_routing_route_add_default_msg_req *req = msg;\n\tstruct pipeline_routing_route_add_default_msg_rsp *rsp = msg;\n\n\tstruct routing_table_entry default_entry = {\n\t\t.head = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = p->port_out_id[req->port_id]},\n\t\t},\n\n\t\t.flags = 0,\n\t\t.port_id = 0,\n\t\t.ip = 0,\n\t};\n\n\trsp->status = rte_pipeline_table_default_entry_add(p->p,\n\t\tp->table_id[0],\n\t\t(struct rte_pipeline_table_entry *) &default_entry,\n\t\t(struct rte_pipeline_table_entry **) &rsp->entry_ptr);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_routing_msg_req_route_del_default_handler(struct pipeline *p,\n\tvoid *msg)\n{\n\tstruct pipeline_routing_route_delete_default_msg_rsp *rsp = msg;\n\n\trsp->status = rte_pipeline_table_default_entry_delete(p->p,\n\t\tp->table_id[0],\n\t\tNULL);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_routing_msg_req_arp_add_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_routing_arp_add_msg_req *req = msg;\n\tstruct pipeline_routing_arp_add_msg_rsp *rsp = msg;\n\n\tstruct pipeline_routing_arp_key_ipv4 key = {\n\t\t.port_id = req->key.key.ipv4.port_id,\n\t\t.ip = rte_bswap32(req->key.key.ipv4.ip),\n\t};\n\n\tstruct arp_table_entry entry = {\n\t\t.head = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = p->port_out_id[req->key.key.ipv4.port_id]},\n\t\t},\n\n\t\t.macaddr = 0, /* set below */\n\t};\n\n\tif (req->key.type != PIPELINE_ROUTING_ARP_IPV4) {\n\t\trsp->status = -1;\n\t\treturn rsp;\n\t}\n\n\t*((struct ether_addr *) &entry.macaddr) = req->macaddr;\n\n\trsp->status = rte_pipeline_table_entry_add(p->p,\n\t\tp->table_id[1],\n\t\t&key,\n\t\t(struct rte_pipeline_table_entry *) &entry,\n\t\t&rsp->key_found,\n\t\t(struct rte_pipeline_table_entry **) &rsp->entry_ptr);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_routing_msg_req_arp_del_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_routing_arp_delete_msg_req *req = msg;\n\tstruct pipeline_routing_arp_delete_msg_rsp *rsp = msg;\n\n\tstruct pipeline_routing_arp_key_ipv4 key = {\n\t\t.port_id = req->key.key.ipv4.port_id,\n\t\t.ip = rte_bswap32(req->key.key.ipv4.ip),\n\t};\n\n\tif (req->key.type != PIPELINE_ROUTING_ARP_IPV4) {\n\t\trsp->status = -1;\n\t\treturn rsp;\n\t}\n\n\trsp->status = rte_pipeline_table_entry_delete(p->p,\n\t\tp->table_id[1],\n\t\t&key,\n\t\t&rsp->key_found,\n\t\tNULL);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_routing_msg_req_arp_add_default_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_routing_arp_add_default_msg_req *req = msg;\n\tstruct pipeline_routing_arp_add_default_msg_rsp *rsp = msg;\n\n\tstruct arp_table_entry default_entry = {\n\t\t.head = {\n\t\t\t.action = RTE_PIPELINE_ACTION_PORT,\n\t\t\t{.port_id = p->port_out_id[req->port_id]},\n\t\t},\n\n\t\t.macaddr = 0,\n\t};\n\n\trsp->status = rte_pipeline_table_default_entry_add(p->p,\n\t\tp->table_id[1],\n\t\t(struct rte_pipeline_table_entry *) &default_entry,\n\t\t(struct rte_pipeline_table_entry **) &rsp->entry_ptr);\n\n\treturn rsp;\n}\n\nvoid *\npipeline_routing_msg_req_arp_del_default_handler(struct pipeline *p, void *msg)\n{\n\tstruct pipeline_routing_arp_delete_default_msg_rsp *rsp = msg;\n\n\trsp->status = rte_pipeline_table_default_entry_delete(p->p,\n\t\tp->table_id[1],\n\t\tNULL);\n\n\treturn rsp;\n}\n\nstruct pipeline_be_ops pipeline_routing_be_ops = {\n\t.f_init = pipeline_routing_init,\n\t.f_free = pipeline_routing_free,\n\t.f_run = NULL,\n\t.f_timer = pipeline_routing_timer,\n\t.f_track = pipeline_routing_track,\n};\n" }, { "path": "examples/ip_pipeline/pipeline/pipeline_routing_be.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_ROUTING_BE_H__\n#define __INCLUDE_PIPELINE_ROUTING_BE_H__\n\n#include \n\n#include \"pipeline_common_be.h\"\n\n/*\n * Route\n */\nenum pipeline_routing_route_key_type {\n\tPIPELINE_ROUTING_ROUTE_IPV4,\n};\n\nstruct pipeline_routing_route_key_ipv4 {\n\tuint32_t ip;\n\tuint32_t depth;\n};\n\nstruct pipeline_routing_route_key {\n\tenum pipeline_routing_route_key_type type;\n\tunion {\n\t\tstruct pipeline_routing_route_key_ipv4 ipv4;\n\t} key;\n};\n\nenum pipeline_routing_route_flags {\n\tPIPELINE_ROUTING_ROUTE_LOCAL = 1 << 0, /* 0 = remote; 1 = local */\n};\n\n/*\n * ARP\n */\nenum pipeline_routing_arp_key_type {\n\tPIPELINE_ROUTING_ARP_IPV4,\n};\n\nstruct pipeline_routing_arp_key_ipv4 {\n\tuint32_t port_id;\n\tuint32_t ip;\n};\n\nstruct pipeline_routing_arp_key {\n\tenum pipeline_routing_arp_key_type type;\n\tunion {\n\t\tstruct pipeline_routing_arp_key_ipv4 ipv4;\n\t} key;\n};\n\n/*\n * Messages\n */\nenum pipeline_routing_msg_req_type {\n\tPIPELINE_ROUTING_MSG_REQ_ROUTE_ADD,\n\tPIPELINE_ROUTING_MSG_REQ_ROUTE_DEL,\n\tPIPELINE_ROUTING_MSG_REQ_ROUTE_ADD_DEFAULT,\n\tPIPELINE_ROUTING_MSG_REQ_ROUTE_DEL_DEFAULT,\n\tPIPELINE_ROUTING_MSG_REQ_ARP_ADD,\n\tPIPELINE_ROUTING_MSG_REQ_ARP_DEL,\n\tPIPELINE_ROUTING_MSG_REQ_ARP_ADD_DEFAULT,\n\tPIPELINE_ROUTING_MSG_REQ_ARP_DEL_DEFAULT,\n\tPIPELINE_ROUTING_MSG_REQS\n};\n\n/*\n * MSG ROUTE ADD\n */\nstruct pipeline_routing_route_add_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_routing_msg_req_type subtype;\n\n\t/* key */\n\tstruct pipeline_routing_route_key key;\n\n\t/* data */\n\tuint32_t flags;\n\tuint32_t port_id; /* Output port ID */\n\tuint32_t ip; /* Next hop IP address (only valid for remote routes) */\n};\n\nstruct pipeline_routing_route_add_msg_rsp {\n\tint status;\n\tint key_found;\n\tvoid *entry_ptr;\n};\n\n/*\n * MSG ROUTE DELETE\n */\nstruct pipeline_routing_route_delete_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_routing_msg_req_type subtype;\n\n\t/* key */\n\tstruct pipeline_routing_route_key key;\n};\n\nstruct pipeline_routing_route_delete_msg_rsp {\n\tint status;\n\tint key_found;\n};\n\n/*\n * MSG ROUTE ADD DEFAULT\n */\nstruct pipeline_routing_route_add_default_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_routing_msg_req_type subtype;\n\n\t/* data */\n\tuint32_t port_id;\n};\n\nstruct pipeline_routing_route_add_default_msg_rsp {\n\tint status;\n\tvoid *entry_ptr;\n};\n\n/*\n * MSG ROUTE DELETE DEFAULT\n */\nstruct pipeline_routing_route_delete_default_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_routing_msg_req_type subtype;\n};\n\nstruct pipeline_routing_route_delete_default_msg_rsp {\n\tint status;\n};\n\n/*\n * MSG ARP ADD\n */\nstruct pipeline_routing_arp_add_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_routing_msg_req_type subtype;\n\n\t/* key */\n\tstruct pipeline_routing_arp_key key;\n\n\t/* data */\n\tstruct ether_addr macaddr;\n};\n\nstruct pipeline_routing_arp_add_msg_rsp {\n\tint status;\n\tint key_found;\n\tvoid *entry_ptr;\n};\n\n/*\n * MSG ARP DELETE\n */\nstruct pipeline_routing_arp_delete_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_routing_msg_req_type subtype;\n\n\t/* key */\n\tstruct pipeline_routing_arp_key key;\n};\n\nstruct pipeline_routing_arp_delete_msg_rsp {\n\tint status;\n\tint key_found;\n};\n\n/*\n * MSG ARP ADD DEFAULT\n */\nstruct pipeline_routing_arp_add_default_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_routing_msg_req_type subtype;\n\n\t/* data */\n\tuint32_t port_id;\n};\n\nstruct pipeline_routing_arp_add_default_msg_rsp {\n\tint status;\n\tvoid *entry_ptr;\n};\n\n/*\n * MSG ARP DELETE DEFAULT\n */\nstruct pipeline_routing_arp_delete_default_msg_req {\n\tenum pipeline_msg_req_type type;\n\tenum pipeline_routing_msg_req_type subtype;\n};\n\nstruct pipeline_routing_arp_delete_default_msg_rsp {\n\tint status;\n};\n\nextern struct pipeline_be_ops pipeline_routing_be_ops;\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_H__\n#define __INCLUDE_PIPELINE_H__\n\n#include \n\n#include \"pipeline_be.h\"\n\n/*\n * Pipeline type front-end operations\n */\n\ntypedef void* (*pipeline_fe_op_init)(struct pipeline_params *params, void *arg);\n\ntypedef int (*pipeline_fe_op_free)(void *pipeline);\n\nstruct pipeline_fe_ops {\n\tpipeline_fe_op_init f_init;\n\tpipeline_fe_op_free f_free;\n\tcmdline_parse_ctx_t *cmds;\n};\n\n/*\n * Pipeline type\n */\n\nstruct pipeline_type {\n\tconst char *name;\n\n\t/* pipeline back-end */\n\tstruct pipeline_be_ops *be_ops;\n\n\t/* pipeline front-end */\n\tstruct pipeline_fe_ops *fe_ops;\n};\n\nstatic inline uint32_t\npipeline_type_cmds_count(struct pipeline_type *ptype)\n{\n\tcmdline_parse_ctx_t *cmds;\n\tuint32_t n_cmds;\n\n\tif (ptype->fe_ops == NULL)\n\t\treturn 0;\n\n\tcmds = ptype->fe_ops->cmds;\n\tif (cmds == NULL)\n\t\treturn 0;\n\n\tfor (n_cmds = 0; cmds[n_cmds]; n_cmds++);\n\n\treturn n_cmds;\n}\n\n#endif\n" }, { "path": "examples/ip_pipeline/pipeline_be.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_PIPELINE_BE_H__\n#define __INCLUDE_PIPELINE_BE_H__\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\nenum pipeline_port_in_type {\n\tPIPELINE_PORT_IN_ETHDEV_READER,\n\tPIPELINE_PORT_IN_RING_READER,\n\tPIPELINE_PORT_IN_RING_READER_IPV4_FRAG,\n\tPIPELINE_PORT_IN_RING_READER_IPV6_FRAG,\n\tPIPELINE_PORT_IN_SCHED_READER,\n\tPIPELINE_PORT_IN_SOURCE,\n};\n\nstruct pipeline_port_in_params {\n\tenum pipeline_port_in_type type;\n\tunion {\n\t\tstruct rte_port_ethdev_reader_params ethdev;\n\t\tstruct rte_port_ring_reader_params ring;\n\t\tstruct rte_port_ring_reader_ipv4_frag_params ring_ipv4_frag;\n\t\tstruct rte_port_ring_reader_ipv6_frag_params ring_ipv6_frag;\n\t\tstruct rte_port_sched_reader_params sched;\n\t\tstruct rte_port_source_params source;\n\t} params;\n\tuint32_t burst_size;\n};\n\nstatic inline void *\npipeline_port_in_params_convert(struct pipeline_port_in_params *p)\n{\n\tswitch (p->type) {\n\tcase PIPELINE_PORT_IN_ETHDEV_READER:\n\t\treturn (void *) &p->params.ethdev;\n\tcase PIPELINE_PORT_IN_RING_READER:\n\t\treturn (void *) &p->params.ring;\n\tcase PIPELINE_PORT_IN_RING_READER_IPV4_FRAG:\n\t\treturn (void *) &p->params.ring_ipv4_frag;\n\tcase PIPELINE_PORT_IN_RING_READER_IPV6_FRAG:\n\t\treturn (void *) &p->params.ring_ipv6_frag;\n\tcase PIPELINE_PORT_IN_SCHED_READER:\n\t\treturn (void *) &p->params.sched;\n\tcase PIPELINE_PORT_IN_SOURCE:\n\t\treturn (void *) &p->params.source;\n\tdefault:\n\t\treturn NULL;\n\t}\n}\n\nstatic inline struct rte_port_in_ops *\npipeline_port_in_params_get_ops(struct pipeline_port_in_params *p)\n{\n\tswitch (p->type) {\n\tcase PIPELINE_PORT_IN_ETHDEV_READER:\n\t\treturn &rte_port_ethdev_reader_ops;\n\tcase PIPELINE_PORT_IN_RING_READER:\n\t\treturn &rte_port_ring_reader_ops;\n\tcase PIPELINE_PORT_IN_RING_READER_IPV4_FRAG:\n\t\treturn &rte_port_ring_reader_ipv4_frag_ops;\n\tcase PIPELINE_PORT_IN_RING_READER_IPV6_FRAG:\n\t\treturn &rte_port_ring_reader_ipv6_frag_ops;\n\tcase PIPELINE_PORT_IN_SCHED_READER:\n\t\treturn &rte_port_sched_reader_ops;\n\tcase PIPELINE_PORT_IN_SOURCE:\n\t\treturn &rte_port_source_ops;\n\tdefault:\n\t\treturn NULL;\n\t}\n}\n\nenum pipeline_port_out_type {\n\tPIPELINE_PORT_OUT_ETHDEV_WRITER,\n\tPIPELINE_PORT_OUT_ETHDEV_WRITER_NODROP,\n\tPIPELINE_PORT_OUT_RING_WRITER,\n\tPIPELINE_PORT_OUT_RING_WRITER_NODROP,\n\tPIPELINE_PORT_OUT_RING_WRITER_IPV4_RAS,\n\tPIPELINE_PORT_OUT_RING_WRITER_IPV6_RAS,\n\tPIPELINE_PORT_OUT_SCHED_WRITER,\n\tPIPELINE_PORT_OUT_SINK,\n};\n\nstruct pipeline_port_out_params {\n\tenum pipeline_port_out_type type;\n\tunion {\n\t\tstruct rte_port_ethdev_writer_params ethdev;\n\t\tstruct rte_port_ethdev_writer_nodrop_params ethdev_nodrop;\n\t\tstruct rte_port_ring_writer_params ring;\n\t\tstruct rte_port_ring_writer_nodrop_params ring_nodrop;\n\t\tstruct rte_port_ring_writer_ipv4_ras_params ring_ipv4_ras;\n\t\tstruct rte_port_ring_writer_ipv6_ras_params ring_ipv6_ras;\n\t\tstruct rte_port_sched_writer_params sched;\n\t} params;\n};\n\nstatic inline void *\npipeline_port_out_params_convert(struct pipeline_port_out_params *p)\n{\n\tswitch (p->type) {\n\tcase PIPELINE_PORT_OUT_ETHDEV_WRITER:\n\t\treturn (void *) &p->params.ethdev;\n\tcase PIPELINE_PORT_OUT_ETHDEV_WRITER_NODROP:\n\t\treturn (void *) &p->params.ethdev_nodrop;\n\tcase PIPELINE_PORT_OUT_RING_WRITER:\n\t\treturn (void *) &p->params.ring;\n\tcase PIPELINE_PORT_OUT_RING_WRITER_NODROP:\n\t\treturn (void *) &p->params.ring_nodrop;\n\tcase PIPELINE_PORT_OUT_RING_WRITER_IPV4_RAS:\n\t\treturn (void *) &p->params.ring_ipv4_ras;\n\tcase PIPELINE_PORT_OUT_RING_WRITER_IPV6_RAS:\n\t\treturn (void *) &p->params.ring_ipv6_ras;\n\tcase PIPELINE_PORT_OUT_SCHED_WRITER:\n\t\treturn (void *) &p->params.sched;\n\tcase PIPELINE_PORT_OUT_SINK:\n\tdefault:\n\t\treturn NULL;\n\t}\n}\n\nstatic inline void *\npipeline_port_out_params_get_ops(struct pipeline_port_out_params *p)\n{\n\tswitch (p->type) {\n\tcase PIPELINE_PORT_OUT_ETHDEV_WRITER:\n\t\treturn &rte_port_ethdev_writer_ops;\n\tcase PIPELINE_PORT_OUT_ETHDEV_WRITER_NODROP:\n\t\treturn &rte_port_ethdev_writer_nodrop_ops;\n\tcase PIPELINE_PORT_OUT_RING_WRITER:\n\t\treturn &rte_port_ring_writer_ops;\n\tcase PIPELINE_PORT_OUT_RING_WRITER_NODROP:\n\t\treturn &rte_port_ring_writer_nodrop_ops;\n\tcase PIPELINE_PORT_OUT_RING_WRITER_IPV4_RAS:\n\t\treturn &rte_port_ring_writer_ipv4_ras_ops;\n\tcase PIPELINE_PORT_OUT_RING_WRITER_IPV6_RAS:\n\t\treturn &rte_port_ring_writer_ipv6_ras_ops;\n\tcase PIPELINE_PORT_OUT_SCHED_WRITER:\n\t\treturn &rte_port_sched_writer_ops;\n\tcase PIPELINE_PORT_OUT_SINK:\n\t\treturn &rte_port_sink_ops;\n\tdefault:\n\t\treturn NULL;\n\t}\n}\n\n#ifndef PIPELINE_NAME_SIZE\n#define PIPELINE_NAME_SIZE 32\n#endif\n\n#ifndef PIPELINE_MAX_PORT_IN\n#define PIPELINE_MAX_PORT_IN 16\n#endif\n\n#ifndef PIPELINE_MAX_PORT_OUT\n#define PIPELINE_MAX_PORT_OUT 16\n#endif\n\n#ifndef PIPELINE_MAX_TABLES\n#define PIPELINE_MAX_TABLES 16\n#endif\n\n#ifndef PIPELINE_MAX_MSGQ_IN\n#define PIPELINE_MAX_MSGQ_IN 16\n#endif\n\n#ifndef PIPELINE_MAX_MSGQ_OUT\n#define PIPELINE_MAX_MSGQ_OUT 16\n#endif\n\n#ifndef PIPELINE_MAX_ARGS\n#define PIPELINE_MAX_ARGS 32\n#endif\n\nstruct pipeline_params {\n\tchar name[PIPELINE_NAME_SIZE];\n\n\tstruct pipeline_port_in_params port_in[PIPELINE_MAX_PORT_IN];\n\tstruct pipeline_port_out_params port_out[PIPELINE_MAX_PORT_OUT];\n\tstruct rte_ring *msgq_in[PIPELINE_MAX_MSGQ_IN];\n\tstruct rte_ring *msgq_out[PIPELINE_MAX_MSGQ_OUT];\n\n\tuint32_t n_ports_in;\n\tuint32_t n_ports_out;\n\tuint32_t n_msgq;\n\n\tint socket_id;\n\n\tchar *args_name[PIPELINE_MAX_ARGS];\n\tchar *args_value[PIPELINE_MAX_ARGS];\n\tuint32_t n_args;\n\n\tuint32_t log_level;\n};\n\n/*\n * Pipeline type back-end operations\n */\n\ntypedef void* (*pipeline_be_op_init)(struct pipeline_params *params,\n\tvoid *arg);\n\ntypedef int (*pipeline_be_op_free)(void *pipeline);\n\ntypedef int (*pipeline_be_op_run)(void *pipeline);\n\ntypedef int (*pipeline_be_op_timer)(void *pipeline);\n\ntypedef int (*pipeline_be_op_track)(void *pipeline,\n\tuint32_t port_in,\n\tuint32_t *port_out);\n\nstruct pipeline_be_ops {\n\tpipeline_be_op_init f_init;\n\tpipeline_be_op_free f_free;\n\tpipeline_be_op_run f_run;\n\tpipeline_be_op_timer f_timer;\n\tpipeline_be_op_track f_track;\n};\n\n#endif\n" }, { "path": "examples/ip_pipeline/thread.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \"pipeline_common_be.h\"\n#include \"app.h\"\n\nint app_thread(void *arg)\n{\n\tstruct app_params *app = (struct app_params *) arg;\n\tuint32_t core_id = rte_lcore_id(), i, j;\n\tstruct app_thread_data *t = &app->thread_data[core_id];\n\tuint32_t n_regular = RTE_MIN(t->n_regular, RTE_DIM(t->regular));\n\tuint32_t n_custom = RTE_MIN(t->n_custom, RTE_DIM(t->custom));\n\n\tfor (i = 0; ; i++) {\n\t\t/* Run regular pipelines */\n\t\tfor (j = 0; j < n_regular; j++) {\n\t\t\tstruct app_thread_pipeline_data *data = &t->regular[j];\n\t\t\tstruct pipeline *p = data->be;\n\n\t\t\trte_pipeline_run(p->p);\n\t\t}\n\n\t\t/* Run custom pipelines */\n\t\tfor (j = 0; j < n_custom; j++) {\n\t\t\tstruct app_thread_pipeline_data *data = &t->custom[j];\n\n\t\t\tdata->f_run(data->be);\n\t\t}\n\n\t\t/* Timer */\n\t\tif ((i & 0xF) == 0) {\n\t\t\tuint64_t time = rte_get_tsc_cycles();\n\t\t\tuint64_t t_deadline = UINT64_MAX;\n\n\t\t\tif (time < t->deadline)\n\t\t\t\tcontinue;\n\n\t\t\t/* Timer for regular pipelines */\n\t\t\tfor (j = 0; j < n_regular; j++) {\n\t\t\t\tstruct app_thread_pipeline_data *data =\n\t\t\t\t\t&t->regular[j];\n\t\t\t\tuint64_t p_deadline = data->deadline;\n\n\t\t\t\tif (p_deadline <= time) {\n\t\t\t\t\tdata->f_timer(data->be);\n\t\t\t\t\tp_deadline = time + data->timer_period;\n\t\t\t\t\tdata->deadline = p_deadline;\n\t\t\t\t}\n\n\t\t\t\tif (p_deadline < t_deadline)\n\t\t\t\t\tt_deadline = p_deadline;\n\t\t\t}\n\n\t\t\t/* Timer for custom pipelines */\n\t\t\tfor (j = 0; j < n_custom; j++) {\n\t\t\t\tstruct app_thread_pipeline_data *data =\n\t\t\t\t\t&t->custom[j];\n\t\t\t\tuint64_t p_deadline = data->deadline;\n\n\t\t\t\tif (p_deadline <= time) {\n\t\t\t\t\tdata->f_timer(data->be);\n\t\t\t\t\tp_deadline = time + data->timer_period;\n\t\t\t\t\tdata->deadline = p_deadline;\n\t\t\t\t}\n\n\t\t\t\tif (p_deadline < t_deadline)\n\t\t\t\t\tt_deadline = p_deadline;\n\t\t\t}\n\n\t\t\tt->deadline = t_deadline;\n\t\t}\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/ip_reassembly/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = ip_reassembly\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/ip_reassembly/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#define MAX_PKT_BURST 32\n\n\n#define RTE_LOGTYPE_IP_RSMBL RTE_LOGTYPE_USER1\n\n#define MAX_JUMBO_PKT_LEN 9600\n\n#define\tBUF_SIZE\tRTE_MBUF_DEFAULT_DATAROOM\n#define MBUF_SIZE\t\\\n\t(BUF_SIZE + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)\n\n#define NB_MBUF 8192\n\n/* allow max jumbo frame 9.5 KB */\n#define JUMBO_FRAME_MAX_SIZE\t0x2600\n\n#define\tMAX_FLOW_NUM\tUINT16_MAX\n#define\tMIN_FLOW_NUM\t1\n#define\tDEF_FLOW_NUM\t0x1000\n\n/* TTL numbers are in ms. */\n#define\tMAX_FLOW_TTL\t(3600 * MS_PER_S)\n#define\tMIN_FLOW_TTL\t1\n#define\tDEF_FLOW_TTL\tMS_PER_S\n\n#define MAX_FRAG_NUM RTE_LIBRTE_IP_FRAG_MAX_FRAG\n\n/* Should be power of two. */\n#define\tIP_FRAG_TBL_BUCKET_ENTRIES\t16\n\nstatic uint32_t max_flow_num = DEF_FLOW_NUM;\nstatic uint32_t max_flow_ttl = DEF_FLOW_TTL;\n\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n#define NB_SOCKETS 8\n\n/* Configure how many packets ahead to prefetch, when reading packets */\n#define PREFETCH_OFFSET\t3\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\n\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n/* ethernet addresses of ports */\nstatic struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];\n\n#ifndef IPv4_BYTES\n#define IPv4_BYTES_FMT \"%\" PRIu8 \".%\" PRIu8 \".%\" PRIu8 \".%\" PRIu8\n#define IPv4_BYTES(addr) \\\n\t\t(uint8_t) (((addr) >> 24) & 0xFF),\\\n\t\t(uint8_t) (((addr) >> 16) & 0xFF),\\\n\t\t(uint8_t) (((addr) >> 8) & 0xFF),\\\n\t\t(uint8_t) ((addr) & 0xFF)\n#endif\n\n#ifndef IPv6_BYTES\n#define IPv6_BYTES_FMT \"%02x%02x:%02x%02x:%02x%02x:%02x%02x:\"\\\n \"%02x%02x:%02x%02x:%02x%02x:%02x%02x\"\n#define IPv6_BYTES(addr) \\\n\taddr[0], addr[1], addr[2], addr[3], \\\n\taddr[4], addr[5], addr[6], addr[7], \\\n\taddr[8], addr[9], addr[10], addr[11],\\\n\taddr[12], addr[13],addr[14], addr[15]\n#endif\n\n#define IPV6_ADDR_LEN 16\n\n/* mask of enabled ports */\nstatic uint32_t enabled_port_mask = 0;\n\nstatic int rx_queue_per_lcore = 1;\n\nstruct mbuf_table {\n\tuint32_t len;\n\tuint32_t head;\n\tuint32_t tail;\n\tstruct rte_mbuf *m_table[0];\n};\n\nstruct rx_queue {\n\tstruct rte_ip_frag_tbl *frag_tbl;\n\tstruct rte_mempool *pool;\n\tstruct rte_lpm *lpm;\n\tstruct rte_lpm6 *lpm6;\n\tuint8_t portid;\n};\n\nstruct tx_lcore_stat {\n\tuint64_t call;\n\tuint64_t drop;\n\tuint64_t queue;\n\tuint64_t send;\n};\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT 16\n#define MAX_RX_QUEUE_PER_PORT 128\n\nstruct lcore_queue_conf {\n\tuint16_t n_rx_queue;\n\tstruct rx_queue rx_queue_list[MAX_RX_QUEUE_PER_LCORE];\n\tuint16_t tx_queue_id[RTE_MAX_ETHPORTS];\n\tstruct rte_ip_frag_death_row death_row;\n\tstruct mbuf_table *tx_mbufs[RTE_MAX_ETHPORTS];\n\tstruct tx_lcore_stat tx_stat;\n} __rte_cache_aligned;\nstatic struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];\n\nstatic struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.mq_mode = ETH_MQ_RX_RSS,\n\t\t.max_rx_pkt_len = JUMBO_FRAME_MAX_SIZE,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 1, /**< IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 1, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.rx_adv_conf = {\n\t\t\t.rss_conf = {\n\t\t\t\t.rss_key = NULL,\n\t\t\t\t.rss_hf = ETH_RSS_IP,\n\t\t},\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\n/*\n * IPv4 forwarding table\n */\nstruct l3fwd_ipv4_route {\n\tuint32_t ip;\n\tuint8_t depth;\n\tuint8_t if_out;\n};\n\nstruct l3fwd_ipv4_route l3fwd_ipv4_route_array[] = {\n\t\t{IPv4(100,10,0,0), 16, 0},\n\t\t{IPv4(100,20,0,0), 16, 1},\n\t\t{IPv4(100,30,0,0), 16, 2},\n\t\t{IPv4(100,40,0,0), 16, 3},\n\t\t{IPv4(100,50,0,0), 16, 4},\n\t\t{IPv4(100,60,0,0), 16, 5},\n\t\t{IPv4(100,70,0,0), 16, 6},\n\t\t{IPv4(100,80,0,0), 16, 7},\n};\n\n/*\n * IPv6 forwarding table\n */\n\nstruct l3fwd_ipv6_route {\n\tuint8_t ip[IPV6_ADDR_LEN];\n\tuint8_t depth;\n\tuint8_t if_out;\n};\n\nstatic struct l3fwd_ipv6_route l3fwd_ipv6_route_array[] = {\n\t{{1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 0},\n\t{{2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 1},\n\t{{3,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 2},\n\t{{4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 3},\n\t{{5,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 4},\n\t{{6,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 5},\n\t{{7,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 6},\n\t{{8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 7},\n};\n\n#define LPM_MAX_RULES 1024\n#define LPM6_MAX_RULES 1024\n#define LPM6_NUMBER_TBL8S (1 << 16)\n\nstruct rte_lpm6_config lpm6_config = {\n\t\t.max_rules = LPM6_MAX_RULES,\n\t\t.number_tbl8s = LPM6_NUMBER_TBL8S,\n\t\t.flags = 0\n};\n\nstatic struct rte_lpm *socket_lpm[RTE_MAX_NUMA_NODES];\nstatic struct rte_lpm6 *socket_lpm6[RTE_MAX_NUMA_NODES];\n\n#ifdef RTE_LIBRTE_IP_FRAG_TBL_STAT\n#define TX_LCORE_STAT_UPDATE(s, f, v) ((s)->f += (v))\n#else\n#define TX_LCORE_STAT_UPDATE(s, f, v) do {} while (0)\n#endif /* RTE_LIBRTE_IP_FRAG_TBL_STAT */\n\n/*\n * If number of queued packets reached given threahold, then\n * send burst of packets on an output interface.\n */\nstatic inline uint32_t\nsend_burst(struct lcore_queue_conf *qconf, uint32_t thresh, uint8_t port)\n{\n\tuint32_t fill, len, k, n;\n\tstruct mbuf_table *txmb;\n\n\ttxmb = qconf->tx_mbufs[port];\n\tlen = txmb->len;\n\n\tif ((int32_t)(fill = txmb->head - txmb->tail) < 0)\n\t\tfill += len;\n\n\tif (fill >= thresh) {\n\t\tn = RTE_MIN(len - txmb->tail, fill);\n\n\t\tk = rte_eth_tx_burst(port, qconf->tx_queue_id[port],\n\t\t\ttxmb->m_table + txmb->tail, (uint16_t)n);\n\n\t\tTX_LCORE_STAT_UPDATE(&qconf->tx_stat, call, 1);\n\t\tTX_LCORE_STAT_UPDATE(&qconf->tx_stat, send, k);\n\n\t\tfill -= k;\n\t\tif ((txmb->tail += k) == len)\n\t\t\ttxmb->tail = 0;\n\t}\n\n\treturn (fill);\n}\n\n/* Enqueue a single packet, and send burst if queue is filled */\nstatic inline int\nsend_single_packet(struct rte_mbuf *m, uint8_t port)\n{\n\tuint32_t fill, lcore_id, len;\n\tstruct lcore_queue_conf *qconf;\n\tstruct mbuf_table *txmb;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_queue_conf[lcore_id];\n\n\ttxmb = qconf->tx_mbufs[port];\n\tlen = txmb->len;\n\n\tfill = send_burst(qconf, MAX_PKT_BURST, port);\n\n\tif (fill == len - 1) {\n\t\tTX_LCORE_STAT_UPDATE(&qconf->tx_stat, drop, 1);\n\t\trte_pktmbuf_free(txmb->m_table[txmb->tail]);\n\t\tif (++txmb->tail == len)\n\t\t\ttxmb->tail = 0;\n\t}\n\n\tTX_LCORE_STAT_UPDATE(&qconf->tx_stat, queue, 1);\n\ttxmb->m_table[txmb->head] = m;\n\tif(++txmb->head == len)\n\t\ttxmb->head = 0;\n\n\treturn (0);\n}\n\nstatic inline void\nreassemble(struct rte_mbuf *m, uint8_t portid, uint32_t queue,\n\tstruct lcore_queue_conf *qconf, uint64_t tms)\n{\n\tstruct ether_hdr *eth_hdr;\n\tstruct rte_ip_frag_tbl *tbl;\n\tstruct rte_ip_frag_death_row *dr;\n\tstruct rx_queue *rxq;\n\tvoid *d_addr_bytes;\n\tuint8_t next_hop, dst_port;\n\n\trxq = &qconf->rx_queue_list[queue];\n\n\teth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\tdst_port = portid;\n\n\t/* if packet is IPv4 */\n#ifdef RTE_NEXT_ABI\n\tif (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {\n#else\n\tif (m->ol_flags & (PKT_RX_IPV4_HDR)) {\n#endif\n\t\tstruct ipv4_hdr *ip_hdr;\n\t\tuint32_t ip_dst;\n\n\t\tip_hdr = (struct ipv4_hdr *)(eth_hdr + 1);\n\n\t\t /* if it is a fragmented packet, then try to reassemble. */\n\t\tif (rte_ipv4_frag_pkt_is_fragmented(ip_hdr)) {\n\t\t\tstruct rte_mbuf *mo;\n\n\t\t\ttbl = rxq->frag_tbl;\n\t\t\tdr = &qconf->death_row;\n\n\t\t\t/* prepare mbuf: setup l2_len/l3_len. */\n\t\t\tm->l2_len = sizeof(*eth_hdr);\n\t\t\tm->l3_len = sizeof(*ip_hdr);\n\n\t\t\t/* process this fragment. */\n\t\t\tmo = rte_ipv4_frag_reassemble_packet(tbl, dr, m, tms, ip_hdr);\n\t\t\tif (mo == NULL)\n\t\t\t\t/* no packet to send out. */\n\t\t\t\treturn;\n\n\t\t\t/* we have our packet reassembled. */\n\t\t\tif (mo != m) {\n\t\t\t\tm = mo;\n\t\t\t\teth_hdr = rte_pktmbuf_mtod(m,\n\t\t\t\t\tstruct ether_hdr *);\n\t\t\t\tip_hdr = (struct ipv4_hdr *)(eth_hdr + 1);\n\t\t\t}\n\t\t}\n\t\tip_dst = rte_be_to_cpu_32(ip_hdr->dst_addr);\n\n\t\t/* Find destination port */\n\t\tif (rte_lpm_lookup(rxq->lpm, ip_dst, &next_hop) == 0 &&\n\t\t\t\t(enabled_port_mask & 1 << next_hop) != 0) {\n\t\t\tdst_port = next_hop;\n\t\t}\n\n\t\teth_hdr->ether_type = rte_be_to_cpu_16(ETHER_TYPE_IPv4);\n#ifdef RTE_NEXT_ABI\n\t} else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {\n\t\t/* if packet is IPv6 */\n#else\n\t}\n\t/* if packet is IPv6 */\n\telse if (m->ol_flags & (PKT_RX_IPV6_HDR | PKT_RX_IPV6_HDR_EXT)) {\n#endif\n\t\tstruct ipv6_extension_fragment *frag_hdr;\n\t\tstruct ipv6_hdr *ip_hdr;\n\n\t\tip_hdr = (struct ipv6_hdr *)(eth_hdr + 1);\n\n\t\tfrag_hdr = rte_ipv6_frag_get_ipv6_fragment_header(ip_hdr);\n\n\t\tif (frag_hdr != NULL) {\n\t\t\tstruct rte_mbuf *mo;\n\n\t\t\ttbl = rxq->frag_tbl;\n\t\t\tdr = &qconf->death_row;\n\n\t\t\t/* prepare mbuf: setup l2_len/l3_len. */\n\t\t\tm->l2_len = sizeof(*eth_hdr);\n\t\t\tm->l3_len = sizeof(*ip_hdr) + sizeof(*frag_hdr);\n\n\t\t\tmo = rte_ipv6_frag_reassemble_packet(tbl, dr, m, tms, ip_hdr, frag_hdr);\n\t\t\tif (mo == NULL)\n\t\t\t\treturn;\n\n\t\t\tif (mo != m) {\n\t\t\t\tm = mo;\n\t\t\t\teth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\t\t\t\tip_hdr = (struct ipv6_hdr *)(eth_hdr + 1);\n\t\t\t}\n\t\t}\n\n\t\t/* Find destination port */\n\t\tif (rte_lpm6_lookup(rxq->lpm6, ip_hdr->dst_addr, &next_hop) == 0 &&\n\t\t\t\t(enabled_port_mask & 1 << next_hop) != 0) {\n\t\t\tdst_port = next_hop;\n\t\t}\n\n\t\teth_hdr->ether_type = rte_be_to_cpu_16(ETHER_TYPE_IPv6);\n\t}\n\t/* if packet wasn't IPv4 or IPv6, it's forwarded to the port it came from */\n\n\t/* 02:00:00:00:00:xx */\n\td_addr_bytes = ð_hdr->d_addr.addr_bytes[0];\n\t*((uint64_t *)d_addr_bytes) = 0x000000000002 + ((uint64_t)dst_port << 40);\n\n\t/* src addr */\n\tether_addr_copy(&ports_eth_addr[dst_port], ð_hdr->s_addr);\n\n\tsend_single_packet(m, dst_port);\n}\n\n/* main processing loop */\nstatic int\nmain_loop(__attribute__((unused)) void *dummy)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tunsigned lcore_id;\n\tuint64_t diff_tsc, cur_tsc, prev_tsc;\n\tint i, j, nb_rx;\n\tuint8_t portid;\n\tstruct lcore_queue_conf *qconf;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\tprev_tsc = 0;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_queue_conf[lcore_id];\n\n\tif (qconf->n_rx_queue == 0) {\n\t\tRTE_LOG(INFO, IP_RSMBL, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn 0;\n\t}\n\n\tRTE_LOG(INFO, IP_RSMBL, \"entering main loop on lcore %u\\n\", lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_queue; i++) {\n\n\t\tportid = qconf->rx_queue_list[i].portid;\n\t\tRTE_LOG(INFO, IP_RSMBL, \" -- lcoreid=%u portid=%hhu\\n\", lcore_id,\n\t\t\tportid);\n\t}\n\n\twhile (1) {\n\n\t\tcur_tsc = rte_rdtsc();\n\n\t\t/*\n\t\t * TX burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\t/*\n\t\t\t * This could be optimized (use queueid instead of\n\t\t\t * portid), but it is not called so often\n\t\t\t */\n\t\t\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t\t\tif ((enabled_port_mask & (1 << portid)) != 0)\n\t\t\t\t\tsend_burst(qconf, 1, portid);\n\t\t\t}\n\n\t\t\tprev_tsc = cur_tsc;\n\t\t}\n\n\t\t/*\n\t\t * Read packet from RX queues\n\t\t */\n\t\tfor (i = 0; i < qconf->n_rx_queue; ++i) {\n\n\t\t\tportid = qconf->rx_queue_list[i].portid;\n\n\t\t\tnb_rx = rte_eth_rx_burst(portid, 0, pkts_burst,\n\t\t\t\tMAX_PKT_BURST);\n\n\t\t\t/* Prefetch first packets */\n\t\t\tfor (j = 0; j < PREFETCH_OFFSET && j < nb_rx; j++) {\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(\n\t\t\t\t\t\tpkts_burst[j], void *));\n\t\t\t}\n\n\t\t\t/* Prefetch and forward already prefetched packets */\n\t\t\tfor (j = 0; j < (nb_rx - PREFETCH_OFFSET); j++) {\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(pkts_burst[\n\t\t\t\t\tj + PREFETCH_OFFSET], void *));\n\t\t\t\treassemble(pkts_burst[j], portid,\n\t\t\t\t\ti, qconf, cur_tsc);\n\t\t\t}\n\n\t\t\t/* Forward remaining prefetched packets */\n\t\t\tfor (; j < nb_rx; j++) {\n\t\t\t\treassemble(pkts_burst[j], portid,\n\t\t\t\t\ti, qconf, cur_tsc);\n\t\t\t}\n\n\t\t\trte_ip_frag_free_death_row(&qconf->death_row,\n\t\t\t\tPREFETCH_OFFSET);\n\t\t}\n\t}\n}\n\n/* display usage */\nstatic void\nprint_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK [-q NQ]\"\n\t\t\" [--max-pkt-len PKTLEN]\"\n\t\t\" [--maxflows=] [--flowttl=[(s|ms)]]\\n\"\n\t\t\" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t\t\" -q NQ: number of RX queues per lcore\\n\"\n\t\t\" --maxflows=: optional, maximum number of flows \"\n\t\t\"supported\\n\"\n\t\t\" --flowttl=[(s|ms)]: optional, maximum TTL for each \"\n\t\t\"flow\\n\",\n\t\tprgname);\n}\n\nstatic uint32_t\nparse_flow_num(const char *str, uint32_t min, uint32_t max, uint32_t *val)\n{\n\tchar *end;\n\tuint64_t v;\n\n\t/* parse decimal string */\n\terrno = 0;\n\tv = strtoul(str, &end, 10);\n\tif (errno != 0 || *end != '\\0')\n\t\treturn (-EINVAL);\n\n\tif (v < min || v > max)\n\t\treturn (-EINVAL);\n\n\t*val = (uint32_t)v;\n\treturn (0);\n}\n\nstatic int\nparse_flow_ttl(const char *str, uint32_t min, uint32_t max, uint32_t *val)\n{\n\tchar *end;\n\tuint64_t v;\n\n\tstatic const char frmt_sec[] = \"s\";\n\tstatic const char frmt_msec[] = \"ms\";\n\n\t/* parse decimal string */\n\terrno = 0;\n\tv = strtoul(str, &end, 10);\n\tif (errno != 0)\n\t\treturn (-EINVAL);\n\n\tif (*end != '\\0') {\n\t\tif (strncmp(frmt_sec, end, sizeof(frmt_sec)) == 0)\n\t\t\tv *= MS_PER_S;\n\t\telse if (strncmp(frmt_msec, end, sizeof (frmt_msec)) != 0)\n\t\t\treturn (-EINVAL);\n\t}\n\n\tif (v < min || v > max)\n\t\treturn (-EINVAL);\n\n\t*val = (uint32_t)v;\n\treturn (0);\n}\n\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\nstatic int\nparse_nqueue(const char *q_arg)\n{\n\tchar *end = NULL;\n\tunsigned long n;\n\n\tprintf(\"%p\\n\", q_arg);\n\n\t/* parse hexadecimal string */\n\tn = strtoul(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\tif (n == 0)\n\t\treturn -1;\n\tif (n >= MAX_RX_QUEUE_PER_LCORE)\n\t\treturn -1;\n\n\treturn n;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{\"max-pkt-len\", 1, 0, 0},\n\t\t{\"maxflows\", 1, 0, 0},\n\t\t{\"flowttl\", 1, 0, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:q:\",\n\t\t\t\tlgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* nqueue */\n\t\tcase 'q':\n\t\t\trx_queue_per_lcore = parse_nqueue(optarg);\n\t\t\tif (rx_queue_per_lcore < 0) {\n\t\t\t\tprintf(\"invalid queue number\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tif (!strncmp(lgopts[option_index].name,\n\t\t\t\t\t\"maxflows\", 8)) {\n\t\t\t\tif ((ret = parse_flow_num(optarg, MIN_FLOW_NUM,\n\t\t\t\t\t\tMAX_FLOW_NUM,\n\t\t\t\t\t\t&max_flow_num)) != 0) {\n\t\t\t\t\tprintf(\"invalid value: \\\"%s\\\" for \"\n\t\t\t\t\t\t\"parameter %s\\n\",\n\t\t\t\t\t\toptarg,\n\t\t\t\t\t\tlgopts[option_index].name);\n\t\t\t\t\tprint_usage(prgname);\n\t\t\t\t\treturn (ret);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (!strncmp(lgopts[option_index].name, \"flowttl\", 7)) {\n\t\t\t\tif ((ret = parse_flow_ttl(optarg, MIN_FLOW_TTL,\n\t\t\t\t\t\tMAX_FLOW_TTL,\n\t\t\t\t\t\t&max_flow_ttl)) != 0) {\n\t\t\t\t\tprintf(\"invalid value: \\\"%s\\\" for \"\n\t\t\t\t\t\t\"parameter %s\\n\",\n\t\t\t\t\t\toptarg,\n\t\t\t\t\t\tlgopts[option_index].name);\n\t\t\t\t\tprint_usage(prgname);\n\t\t\t\t\treturn (ret);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\nstatic void\nprint_ethaddr(const char *name, const struct ether_addr *eth_addr)\n{\n\tchar buf[ETHER_ADDR_FMT_SIZE];\n\tether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);\n\tprintf(\"%s%s\", name, buf);\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"\\ndone\\n\");\n\t\t}\n\t}\n}\n\nstatic int\ninit_routing_table(void)\n{\n\tstruct rte_lpm *lpm;\n\tstruct rte_lpm6 *lpm6;\n\tint socket, ret;\n\tunsigned i;\n\n\tfor (socket = 0; socket < RTE_MAX_NUMA_NODES; socket++) {\n\t\tif (socket_lpm[socket]) {\n\t\t\tlpm = socket_lpm[socket];\n\t\t\t/* populate the LPM table */\n\t\t\tfor (i = 0; i < RTE_DIM(l3fwd_ipv4_route_array); i++) {\n\t\t\t\tret = rte_lpm_add(lpm,\n\t\t\t\t\tl3fwd_ipv4_route_array[i].ip,\n\t\t\t\t\tl3fwd_ipv4_route_array[i].depth,\n\t\t\t\t\tl3fwd_ipv4_route_array[i].if_out);\n\n\t\t\t\tif (ret < 0) {\n\t\t\t\t\tRTE_LOG(ERR, IP_RSMBL, \"Unable to add entry %i to the l3fwd \"\n\t\t\t\t\t\t\"LPM table\\n\", i);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\n\t\t\t\tRTE_LOG(INFO, IP_RSMBL, \"Socket %i: adding route \" IPv4_BYTES_FMT\n\t\t\t\t\t\t\"/%d (port %d)\\n\",\n\t\t\t\t\tsocket,\n\t\t\t\t\tIPv4_BYTES(l3fwd_ipv4_route_array[i].ip),\n\t\t\t\t\tl3fwd_ipv4_route_array[i].depth,\n\t\t\t\t\tl3fwd_ipv4_route_array[i].if_out);\n\t\t\t}\n\t\t}\n\n\t\tif (socket_lpm6[socket]) {\n\t\t\tlpm6 = socket_lpm6[socket];\n\t\t\t/* populate the LPM6 table */\n\t\t\tfor (i = 0; i < RTE_DIM(l3fwd_ipv6_route_array); i++) {\n\t\t\t\tret = rte_lpm6_add(lpm6,\n\t\t\t\t\tl3fwd_ipv6_route_array[i].ip,\n\t\t\t\t\tl3fwd_ipv6_route_array[i].depth,\n\t\t\t\t\tl3fwd_ipv6_route_array[i].if_out);\n\n\t\t\t\tif (ret < 0) {\n\t\t\t\t\tRTE_LOG(ERR, IP_RSMBL, \"Unable to add entry %i to the l3fwd \"\n\t\t\t\t\t\t\"LPM6 table\\n\", i);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\n\t\t\t\tRTE_LOG(INFO, IP_RSMBL, \"Socket %i: adding route \" IPv6_BYTES_FMT\n\t\t\t\t\t\t\"/%d (port %d)\\n\",\n\t\t\t\t\tsocket,\n\t\t\t\t\tIPv6_BYTES(l3fwd_ipv6_route_array[i].ip),\n\t\t\t\t\tl3fwd_ipv6_route_array[i].depth,\n\t\t\t\t\tl3fwd_ipv6_route_array[i].if_out);\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\nsetup_port_tbl(struct lcore_queue_conf *qconf, uint32_t lcore, int socket,\n\tuint32_t port)\n{\n\tstruct mbuf_table *mtb;\n\tuint32_t n;\n\tsize_t sz;\n\n\tn = RTE_MAX(max_flow_num, 2UL * MAX_PKT_BURST);\n\tsz = sizeof (*mtb) + sizeof (mtb->m_table[0]) * n;\n\n\tif ((mtb = rte_zmalloc_socket(__func__, sz, RTE_CACHE_LINE_SIZE,\n\t\t\tsocket)) == NULL) {\n\t\tRTE_LOG(ERR, IP_RSMBL, \"%s() for lcore: %u, port: %u \"\n\t\t\t\"failed to allocate %zu bytes\\n\",\n\t\t\t__func__, lcore, port, sz);\n\t\treturn -1;\n\t}\n\n\tmtb->len = n;\n\tqconf->tx_mbufs[port] = mtb;\n\n\treturn 0;\n}\n\nstatic int\nsetup_queue_tbl(struct rx_queue *rxq, uint32_t lcore, uint32_t queue)\n{\n\tint socket;\n\tuint32_t nb_mbuf;\n\tuint64_t frag_cycles;\n\tchar buf[RTE_MEMPOOL_NAMESIZE];\n\n\tsocket = rte_lcore_to_socket_id(lcore);\n\tif (socket == SOCKET_ID_ANY)\n\t\tsocket = 0;\n\n\tfrag_cycles = (rte_get_tsc_hz() + MS_PER_S - 1) / MS_PER_S *\n\t\tmax_flow_ttl;\n\n\tif ((rxq->frag_tbl = rte_ip_frag_table_create(max_flow_num,\n\t\t\tIP_FRAG_TBL_BUCKET_ENTRIES, max_flow_num, frag_cycles,\n\t\t\tsocket)) == NULL) {\n\t\tRTE_LOG(ERR, IP_RSMBL, \"ip_frag_tbl_create(%u) on \"\n\t\t\t\"lcore: %u for queue: %u failed\\n\",\n\t\t\tmax_flow_num, lcore, queue);\n\t\treturn -1;\n\t}\n\n\t/*\n\t * At any given moment up to \n\t * mbufs could be stored int the fragment table.\n\t * Plus, each TX queue can hold up to packets.\n\t */\n\n\tnb_mbuf = RTE_MAX(max_flow_num, 2UL * MAX_PKT_BURST) * MAX_FRAG_NUM;\n\tnb_mbuf *= (port_conf.rxmode.max_rx_pkt_len + BUF_SIZE - 1) / BUF_SIZE;\n\tnb_mbuf *= 2; /* ipv4 and ipv6 */\n\tnb_mbuf += RTE_TEST_RX_DESC_DEFAULT + RTE_TEST_TX_DESC_DEFAULT;\n\n\tnb_mbuf = RTE_MAX(nb_mbuf, (uint32_t)NB_MBUF);\n\n\tsnprintf(buf, sizeof(buf), \"mbuf_pool_%u_%u\", lcore, queue);\n\n\tif ((rxq->pool = rte_mempool_create(buf, nb_mbuf, MBUF_SIZE, 0,\n\t\t\tsizeof(struct rte_pktmbuf_pool_private),\n\t\t\trte_pktmbuf_pool_init, NULL, rte_pktmbuf_init, NULL,\n\t\t\tsocket, MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET)) == NULL) {\n\t\tRTE_LOG(ERR, IP_RSMBL, \"mempool_create(%s) failed\", buf);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\ninit_mem(void)\n{\n\tchar buf[PATH_MAX];\n\tstruct rte_lpm *lpm;\n\tstruct rte_lpm6 *lpm6;\n\tint socket;\n\tunsigned lcore_id;\n\n\t/* traverse through lcores and initialize structures on each socket */\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\tcontinue;\n\n\t\tsocket = rte_lcore_to_socket_id(lcore_id);\n\n\t\tif (socket == SOCKET_ID_ANY)\n\t\t\tsocket = 0;\n\n\t\tif (socket_lpm[socket] == NULL) {\n\t\t\tRTE_LOG(INFO, IP_RSMBL, \"Creating LPM table on socket %i\\n\", socket);\n\t\t\tsnprintf(buf, sizeof(buf), \"IP_RSMBL_LPM_%i\", socket);\n\n\t\t\tlpm = rte_lpm_create(buf, socket, LPM_MAX_RULES, 0);\n\t\t\tif (lpm == NULL) {\n\t\t\t\tRTE_LOG(ERR, IP_RSMBL, \"Cannot create LPM table\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tsocket_lpm[socket] = lpm;\n\t\t}\n\n\t\tif (socket_lpm6[socket] == NULL) {\n\t\t\tRTE_LOG(INFO, IP_RSMBL, \"Creating LPM6 table on socket %i\\n\", socket);\n\t\t\tsnprintf(buf, sizeof(buf), \"IP_RSMBL_LPM_%i\", socket);\n\n\t\t\tlpm6 = rte_lpm6_create(\"IP_RSMBL_LPM6\", socket, &lpm6_config);\n\t\t\tif (lpm6 == NULL) {\n\t\t\t\tRTE_LOG(ERR, IP_RSMBL, \"Cannot create LPM table\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tsocket_lpm6[socket] = lpm6;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic void\nqueue_dump_stat(void)\n{\n\tuint32_t i, lcore;\n\tconst struct lcore_queue_conf *qconf;\n\n\tfor (lcore = 0; lcore < RTE_MAX_LCORE; lcore++) {\n\t\tif (rte_lcore_is_enabled(lcore) == 0)\n\t\t\tcontinue;\n\n\t\tqconf = &lcore_queue_conf[lcore];\n\t\tfor (i = 0; i < qconf->n_rx_queue; i++) {\n\n\t\t\tfprintf(stdout, \" -- lcoreid=%u portid=%hhu \"\n\t\t\t\t\"frag tbl stat:\\n\",\n\t\t\t\tlcore, qconf->rx_queue_list[i].portid);\n\t\t\trte_ip_frag_table_statistics_dump(stdout,\n\t\t\t\t\tqconf->rx_queue_list[i].frag_tbl);\n\t\t\tfprintf(stdout, \"TX bursts:\\t%\" PRIu64 \"\\n\"\n\t\t\t\t\"TX packets _queued:\\t%\" PRIu64 \"\\n\"\n\t\t\t\t\"TX packets dropped:\\t%\" PRIu64 \"\\n\"\n\t\t\t\t\"TX packets send:\\t%\" PRIu64 \"\\n\",\n\t\t\t\tqconf->tx_stat.call,\n\t\t\t\tqconf->tx_stat.queue,\n\t\t\t\tqconf->tx_stat.drop,\n\t\t\t\tqconf->tx_stat.send);\n\t\t}\n\t}\n}\n\nstatic void\nsignal_handler(int signum)\n{\n\tqueue_dump_stat();\n\tif (signum != SIGUSR1)\n\t\trte_exit(0, \"received signal: %d, exiting\\n\", signum);\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_queue_conf *qconf;\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_txconf *txconf;\n\tstruct rx_queue *rxq;\n\tint ret, socket;\n\tunsigned nb_ports;\n\tuint16_t queueid;\n\tunsigned lcore_id = 0, rx_lcore_id = 0;\n\tuint32_t n_tx_queue, nb_lcores;\n\tuint8_t portid;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid EAL parameters\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid IP reassembly parameters\\n\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\telse if (nb_ports == 0)\n\t\trte_exit(EXIT_FAILURE, \"No ports found!\\n\");\n\n\tnb_lcores = rte_lcore_count();\n\n\t/* initialize structures (mempools, lpm etc.) */\n\tif (init_mem() < 0)\n\t\trte_panic(\"Cannot initialize memory structures!\\n\");\n\n\t/* check if portmask has non-existent ports */\n\tif (enabled_port_mask & ~(RTE_LEN2MASK(nb_ports, unsigned)))\n\t\trte_exit(EXIT_FAILURE, \"Non-existent ports in portmask!\\n\");\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"\\nSkipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\n\t\tqconf = &lcore_queue_conf[rx_lcore_id];\n\n\t\t/* get the lcore_id for this port */\n\t\twhile (rte_lcore_is_enabled(rx_lcore_id) == 0 ||\n\t\t\t qconf->n_rx_queue == (unsigned)rx_queue_per_lcore) {\n\n\t\t\trx_lcore_id++;\n\t\t\tif (rx_lcore_id >= RTE_MAX_LCORE)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Not enough cores\\n\");\n\n\t\t\tqconf = &lcore_queue_conf[rx_lcore_id];\n\t\t}\n\n\t\tsocket = rte_lcore_to_socket_id(portid);\n\t\tif (socket == SOCKET_ID_ANY)\n\t\t\tsocket = 0;\n\n\t\tqueueid = qconf->n_rx_queue;\n\t\trxq = &qconf->rx_queue_list[queueid];\n\t\trxq->portid = portid;\n\t\trxq->lpm = socket_lpm[socket];\n\t\trxq->lpm6 = socket_lpm6[socket];\n\t\tif (setup_queue_tbl(rxq, rx_lcore_id, queueid) < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Failed to set up queue table\\n\");\n\t\tqconf->n_rx_queue++;\n\n\t\t/* init port */\n\t\tprintf(\"Initializing port %d ... \", portid );\n\t\tfflush(stdout);\n\n\t\tn_tx_queue = nb_lcores;\n\t\tif (n_tx_queue > MAX_TX_QUEUE_PER_PORT)\n\t\t\tn_tx_queue = MAX_TX_QUEUE_PER_PORT;\n\t\tret = rte_eth_dev_configure(portid, 1, (uint16_t)n_tx_queue,\n\t\t\t\t\t &port_conf);\n\t\tif (ret < 0) {\n\t\t\tprintf(\"\\n\");\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot configure device: \"\n\t\t\t\t\"err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\t\t}\n\n\t\t/* init one RX queue */\n\t\tret = rte_eth_rx_queue_setup(portid, 0, nb_rxd,\n\t\t\t\t\t socket, NULL,\n\t\t\t\t\t rxq->pool);\n\t\tif (ret < 0) {\n\t\t\tprintf(\"\\n\");\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup: \"\n\t\t\t\t\"err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\t\t}\n\n\t\trte_eth_macaddr_get(portid, &ports_eth_addr[portid]);\n\t\tprint_ethaddr(\" Address:\", &ports_eth_addr[portid]);\n\t\tprintf(\"\\n\");\n\n\t\t/* init one TX queue per couple (lcore,port) */\n\t\tqueueid = 0;\n\t\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tsocket = (int) rte_lcore_to_socket_id(lcore_id);\n\n\t\t\tprintf(\"txq=%u,%d,%d \", lcore_id, queueid, socket);\n\t\t\tfflush(stdout);\n\n\t\t\trte_eth_dev_info_get(portid, &dev_info);\n\t\t\ttxconf = &dev_info.default_txconf;\n\t\t\ttxconf->txq_flags = 0;\n\n\t\t\tret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,\n\t\t\t\t\tsocket, txconf);\n\t\t\tif (ret < 0)\n\t\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup: err=%d, \"\n\t\t\t\t\t\"port=%d\\n\", ret, portid);\n\n\t\t\tqconf = &lcore_queue_conf[lcore_id];\n\t\t\tqconf->tx_queue_id[portid] = queueid;\n\t\t\tsetup_port_tbl(qconf, lcore_id, socket, portid);\n\t\t\tqueueid++;\n\t\t}\n\t\tprintf(\"\\n\");\n\t}\n\n\tprintf(\"\\n\");\n\n\t/* start ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tcontinue;\n\t\t}\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_dev_start: err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\n\t\trte_eth_promiscuous_enable(portid);\n\t}\n\n\tif (init_routing_table() < 0)\n\t\trte_exit(EXIT_FAILURE, \"Cannot init routing table\\n\");\n\n\tcheck_all_ports_link_status((uint8_t)nb_ports, enabled_port_mask);\n\n\tsignal(SIGUSR1, signal_handler);\n\tsignal(SIGTERM, signal_handler);\n\tsignal(SIGINT, signal_handler);\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/ipv4_multicast/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = ipv4_multicast\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/ipv4_multicast/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define RTE_LOGTYPE_IPv4_MULTICAST RTE_LOGTYPE_USER1\n\n#define MAX_PORTS 16\n\n#define\tMCAST_CLONE_PORTS\t2\n#define\tMCAST_CLONE_SEGS\t2\n\n#define\tPKT_MBUF_DATA_SIZE\tRTE_MBUF_DEFAULT_BUF_SIZE\n#define\tNB_PKT_MBUF\t8192\n\n#define\tHDR_MBUF_DATA_SIZE\t(2 * RTE_PKTMBUF_HEADROOM)\n#define\tNB_HDR_MBUF\t(NB_PKT_MBUF * MAX_PORTS)\n\n#define\tNB_CLONE_MBUF\t(NB_PKT_MBUF * MCAST_CLONE_PORTS * MCAST_CLONE_SEGS * 2)\n\n/* allow max jumbo frame 9.5 KB */\n#define\tJUMBO_FRAME_MAX_SIZE\t0x2600\n\n#define MAX_PKT_BURST 32\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n/* Configure how many packets ahead to prefetch, when reading packets */\n#define PREFETCH_OFFSET\t3\n\n/*\n * Construct Ethernet multicast address from IPv4 multicast address.\n * Citing RFC 1112, section 6.4:\n * \"An IP host group address is mapped to an Ethernet multicast address\n * by placing the low-order 23-bits of the IP address into the low-order\n * 23 bits of the Ethernet multicast address 01-00-5E-00-00-00 (hex).\"\n */\n#define\tETHER_ADDR_FOR_IPV4_MCAST(x)\t\\\n\t(rte_cpu_to_be_64(0x01005e000000ULL | ((x) & 0x7fffff)) >> 16)\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n/* ethernet addresses of ports */\nstatic struct ether_addr ports_eth_addr[MAX_PORTS];\n\n/* mask of enabled ports */\nstatic uint32_t enabled_port_mask = 0;\n\nstatic uint8_t nb_ports = 0;\n\nstatic int rx_queue_per_lcore = 1;\n\nstruct mbuf_table {\n\tuint16_t len;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST];\n};\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT 16\nstruct lcore_queue_conf {\n\tuint64_t tx_tsc;\n\tuint16_t n_rx_queue;\n\tuint8_t rx_queue_list[MAX_RX_QUEUE_PER_LCORE];\n\tuint16_t tx_queue_id[MAX_PORTS];\n\tstruct mbuf_table tx_mbufs[MAX_PORTS];\n} __rte_cache_aligned;\nstatic struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];\n\nstatic const struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.max_rx_pkt_len = JUMBO_FRAME_MAX_SIZE,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 1, /**< Jumbo Frame Support enabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\nstatic struct rte_mempool *packet_pool, *header_pool, *clone_pool;\n\n\n/* Multicast */\nstatic struct rte_fbk_hash_params mcast_hash_params = {\n\t.name = \"MCAST_HASH\",\n\t.entries = 1024,\n\t.entries_per_bucket = 4,\n\t.socket_id = 0,\n\t.hash_func = NULL,\n\t.init_val = 0,\n};\n\nstruct rte_fbk_hash_table *mcast_hash = NULL;\n\nstruct mcast_group_params {\n\tuint32_t ip;\n\tuint16_t port_mask;\n};\n\nstatic struct mcast_group_params mcast_group_table[] = {\n\t\t{IPv4(224,0,0,101), 0x1},\n\t\t{IPv4(224,0,0,102), 0x2},\n\t\t{IPv4(224,0,0,103), 0x3},\n\t\t{IPv4(224,0,0,104), 0x4},\n\t\t{IPv4(224,0,0,105), 0x5},\n\t\t{IPv4(224,0,0,106), 0x6},\n\t\t{IPv4(224,0,0,107), 0x7},\n\t\t{IPv4(224,0,0,108), 0x8},\n\t\t{IPv4(224,0,0,109), 0x9},\n\t\t{IPv4(224,0,0,110), 0xA},\n\t\t{IPv4(224,0,0,111), 0xB},\n\t\t{IPv4(224,0,0,112), 0xC},\n\t\t{IPv4(224,0,0,113), 0xD},\n\t\t{IPv4(224,0,0,114), 0xE},\n\t\t{IPv4(224,0,0,115), 0xF},\n};\n\n#define N_MCAST_GROUPS \\\n\t(sizeof (mcast_group_table) / sizeof (mcast_group_table[0]))\n\n\n/* Send burst of packets on an output interface */\nstatic void\nsend_burst(struct lcore_queue_conf *qconf, uint8_t port)\n{\n\tstruct rte_mbuf **m_table;\n\tuint16_t n, queueid;\n\tint ret;\n\n\tqueueid = qconf->tx_queue_id[port];\n\tm_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;\n\tn = qconf->tx_mbufs[port].len;\n\n\tret = rte_eth_tx_burst(port, queueid, m_table, n);\n\twhile (unlikely (ret < n)) {\n\t\trte_pktmbuf_free(m_table[ret]);\n\t\tret++;\n\t}\n\n\tqconf->tx_mbufs[port].len = 0;\n}\n\n/* Get number of bits set. */\nstatic inline uint32_t\nbitcnt(uint32_t v)\n{\n\tuint32_t n;\n\n\tfor (n = 0; v != 0; v &= v - 1, n++)\n\t\t;\n\n\treturn (n);\n}\n\n/**\n * Create the output multicast packet based on the given input packet.\n * There are two approaches for creating outgoing packet, though both\n * are based on data zero-copy idea, they differ in few details:\n * First one creates a clone of the input packet, e.g - walk though all\n * segments of the input packet, and for each of them create a new packet\n * mbuf and attach that new mbuf to the segment (refer to rte_pktmbuf_clone()\n * for more details). Then new mbuf is allocated for the packet header\n * and is prepended to the 'clone' mbuf.\n * Second approach doesn't make a clone, it just increment refcnt for all\n * input packet segments. Then it allocates new mbuf for the packet header\n * and prepends it to the input packet.\n * Basically first approach reuses only input packet's data, but creates\n * it's own copy of packet's metadata. Second approach reuses both input's\n * packet data and metadata.\n * The advantage of first approach - is that each outgoing packet has it's\n * own copy of metadata, so we can safely modify data pointer of the\n * input packet. That allows us to skip creation if the output packet for\n * the last destination port, but instead modify input packet's header inplace,\n * e.g: for N destination ports we need to invoke mcast_out_pkt (N-1) times.\n * The advantage of second approach - less work for each outgoing packet,\n * e.g: we skip \"clone\" operation completely. Though it comes with a price -\n * input packet's metadata has to be intact. So for N destination ports we\n * need to invoke mcast_out_pkt N times.\n * So for small number of outgoing ports (and segments in the input packet)\n * first approach will be faster.\n * As number of outgoing ports (and/or input segments) will grow,\n * second way will become more preferable.\n *\n * @param pkt\n * Input packet mbuf.\n * @param use_clone\n * Control which of the two approaches described above should be used:\n * - 0 - use second approach:\n * Don't \"clone\" input packet.\n * Prepend new header directly to the input packet\n * - 1 - use first approach:\n * Make a \"clone\" of input packet first.\n * Prepend new header to the clone of the input packet\n * @return\n * - The pointer to the new outgoing packet.\n * - NULL if operation failed.\n */\nstatic inline struct rte_mbuf *\nmcast_out_pkt(struct rte_mbuf *pkt, int use_clone)\n{\n\tstruct rte_mbuf *hdr;\n\n\t/* Create new mbuf for the header. */\n\tif (unlikely ((hdr = rte_pktmbuf_alloc(header_pool)) == NULL))\n\t\treturn (NULL);\n\n\t/* If requested, then make a new clone packet. */\n\tif (use_clone != 0 &&\n\t unlikely ((pkt = rte_pktmbuf_clone(pkt, clone_pool)) == NULL)) {\n\t\trte_pktmbuf_free(hdr);\n\t\treturn (NULL);\n\t}\n\n\t/* prepend new header */\n\thdr->next = pkt;\n\n\n\t/* update header's fields */\n\thdr->pkt_len = (uint16_t)(hdr->data_len + pkt->pkt_len);\n\thdr->nb_segs = (uint8_t)(pkt->nb_segs + 1);\n\n\t/* copy metadata from source packet*/\n\thdr->port = pkt->port;\n\thdr->vlan_tci = pkt->vlan_tci;\n\thdr->vlan_tci_outer = pkt->vlan_tci_outer;\n\thdr->tx_offload = pkt->tx_offload;\n\thdr->hash = pkt->hash;\n\n\thdr->ol_flags = pkt->ol_flags;\n\n\t__rte_mbuf_sanity_check(hdr, 1);\n\treturn (hdr);\n}\n\n/*\n * Write new Ethernet header to the outgoing packet,\n * and put it into the outgoing queue for the given port.\n */\nstatic inline void\nmcast_send_pkt(struct rte_mbuf *pkt, struct ether_addr *dest_addr,\n\t\tstruct lcore_queue_conf *qconf, uint8_t port)\n{\n\tstruct ether_hdr *ethdr;\n\tuint16_t len;\n\n\t/* Construct Ethernet header. */\n\tethdr = (struct ether_hdr *)rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(*ethdr));\n\tRTE_MBUF_ASSERT(ethdr != NULL);\n\n\tether_addr_copy(dest_addr, ðdr->d_addr);\n\tether_addr_copy(&ports_eth_addr[port], ðdr->s_addr);\n\tethdr->ether_type = rte_be_to_cpu_16(ETHER_TYPE_IPv4);\n\n\t/* Put new packet into the output queue */\n\tlen = qconf->tx_mbufs[port].len;\n\tqconf->tx_mbufs[port].m_table[len] = pkt;\n\tqconf->tx_mbufs[port].len = ++len;\n\n\t/* Transmit packets */\n\tif (unlikely(MAX_PKT_BURST == len))\n\t\tsend_burst(qconf, port);\n}\n\n/* Multicast forward of the input packet */\nstatic inline void\nmcast_forward(struct rte_mbuf *m, struct lcore_queue_conf *qconf)\n{\n\tstruct rte_mbuf *mc;\n\tstruct ipv4_hdr *iphdr;\n\tuint32_t dest_addr, port_mask, port_num, use_clone;\n\tint32_t hash;\n\tuint8_t port;\n\tunion {\n\t\tuint64_t as_int;\n\t\tstruct ether_addr as_addr;\n\t} dst_eth_addr;\n\n\t/* Remove the Ethernet header from the input packet */\n\tiphdr = (struct ipv4_hdr *)rte_pktmbuf_adj(m, (uint16_t)sizeof(struct ether_hdr));\n\tRTE_MBUF_ASSERT(iphdr != NULL);\n\n\tdest_addr = rte_be_to_cpu_32(iphdr->dst_addr);\n\n\t/*\n\t * Check that it is a valid multicast address and\n\t * we have some active ports assigned to it.\n\t */\n\tif(!IS_IPV4_MCAST(dest_addr) ||\n\t (hash = rte_fbk_hash_lookup(mcast_hash, dest_addr)) <= 0 ||\n\t (port_mask = hash & enabled_port_mask) == 0) {\n\t\trte_pktmbuf_free(m);\n\t\treturn;\n\t}\n\n\t/* Calculate number of destination ports. */\n\tport_num = bitcnt(port_mask);\n\n\t/* Should we use rte_pktmbuf_clone() or not. */\n\tuse_clone = (port_num <= MCAST_CLONE_PORTS &&\n\t m->nb_segs <= MCAST_CLONE_SEGS);\n\n\t/* Mark all packet's segments as referenced port_num times */\n\tif (use_clone == 0)\n\t\trte_pktmbuf_refcnt_update(m, (uint16_t)port_num);\n\n\t/* construct destination ethernet address */\n\tdst_eth_addr.as_int = ETHER_ADDR_FOR_IPV4_MCAST(dest_addr);\n\n\tfor (port = 0; use_clone != port_mask; port_mask >>= 1, port++) {\n\n\t\t/* Prepare output packet and send it out. */\n\t\tif ((port_mask & 1) != 0) {\n\t\t\tif (likely ((mc = mcast_out_pkt(m, use_clone)) != NULL))\n\t\t\t\tmcast_send_pkt(mc, &dst_eth_addr.as_addr,\n\t\t\t\t\t\tqconf, port);\n\t\t\telse if (use_clone == 0)\n\t\t\t\trte_pktmbuf_free(m);\n\t\t}\n\t}\n\n\t/*\n\t * If we making clone packets, then, for the last destination port,\n\t * we can overwrite input packet's metadata.\n\t */\n\tif (use_clone != 0)\n\t\tmcast_send_pkt(m, &dst_eth_addr.as_addr, qconf, port);\n\telse\n\t\trte_pktmbuf_free(m);\n}\n\n/* Send burst of outgoing packet, if timeout expires. */\nstatic inline void\nsend_timeout_burst(struct lcore_queue_conf *qconf)\n{\n\tuint64_t cur_tsc;\n\tuint8_t portid;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\tcur_tsc = rte_rdtsc();\n\tif (likely (cur_tsc < qconf->tx_tsc + drain_tsc))\n\t\treturn;\n\n\tfor (portid = 0; portid < MAX_PORTS; portid++) {\n\t\tif (qconf->tx_mbufs[portid].len != 0)\n\t\t\tsend_burst(qconf, portid);\n\t}\n\tqconf->tx_tsc = cur_tsc;\n}\n\n/* main processing loop */\nstatic int\nmain_loop(__rte_unused void *dummy)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tunsigned lcore_id;\n\tint i, j, nb_rx;\n\tuint8_t portid;\n\tstruct lcore_queue_conf *qconf;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_queue_conf[lcore_id];\n\n\n\tif (qconf->n_rx_queue == 0) {\n\t\tRTE_LOG(INFO, IPv4_MULTICAST, \"lcore %u has nothing to do\\n\",\n\t\t lcore_id);\n\t\treturn 0;\n\t}\n\n\tRTE_LOG(INFO, IPv4_MULTICAST, \"entering main loop on lcore %u\\n\",\n\t lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_queue; i++) {\n\n\t\tportid = qconf->rx_queue_list[i];\n\t\tRTE_LOG(INFO, IPv4_MULTICAST, \" -- lcoreid=%u portid=%d\\n\",\n\t\t lcore_id, (int) portid);\n\t}\n\n\twhile (1) {\n\n\t\t/*\n\t\t * Read packet from RX queues\n\t\t */\n\t\tfor (i = 0; i < qconf->n_rx_queue; i++) {\n\n\t\t\tportid = qconf->rx_queue_list[i];\n\t\t\tnb_rx = rte_eth_rx_burst(portid, 0, pkts_burst,\n\t\t\t\t\t\t MAX_PKT_BURST);\n\n\t\t\t/* Prefetch first packets */\n\t\t\tfor (j = 0; j < PREFETCH_OFFSET && j < nb_rx; j++) {\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(\n\t\t\t\t\t\tpkts_burst[j], void *));\n\t\t\t}\n\n\t\t\t/* Prefetch and forward already prefetched packets */\n\t\t\tfor (j = 0; j < (nb_rx - PREFETCH_OFFSET); j++) {\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(pkts_burst[\n\t\t\t\t\t\tj + PREFETCH_OFFSET], void *));\n\t\t\t\tmcast_forward(pkts_burst[j], qconf);\n\t\t\t}\n\n\t\t\t/* Forward remaining prefetched packets */\n\t\t\tfor (; j < nb_rx; j++) {\n\t\t\t\tmcast_forward(pkts_burst[j], qconf);\n\t\t\t}\n\t\t}\n\n\t\t/* Send out packets from TX queues */\n\t\tsend_timeout_burst(qconf);\n\t}\n}\n\n/* display usage */\nstatic void\nprint_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK [-q NQ]\\n\"\n\t \" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t \" -q NQ: number of queue (=ports) per lcore (default is 1)\\n\",\n\t prgname);\n}\n\nstatic uint32_t\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn 0;\n\n\treturn ((uint32_t)pm);\n}\n\nstatic int\nparse_nqueue(const char *q_arg)\n{\n\tchar *end = NULL;\n\tunsigned long n;\n\n\t/* parse numerical string */\n\terrno = 0;\n\tn = strtoul(q_arg, &end, 0);\n\tif (errno != 0 || end == NULL || *end != '\\0' ||\n\t\t\tn == 0 || n >= MAX_RX_QUEUE_PER_LCORE)\n\t\treturn (-1);\n\n\treturn (n);\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:q:\",\n\t\t\t\t lgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* nqueue */\n\t\tcase 'q':\n\t\t\trx_queue_per_lcore = parse_nqueue(optarg);\n\t\t\tif (rx_queue_per_lcore < 0) {\n\t\t\t\tprintf(\"invalid queue number\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\nstatic void\nprint_ethaddr(const char *name, struct ether_addr *eth_addr)\n{\n\tchar buf[ETHER_ADDR_FMT_SIZE];\n\tether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);\n\tprintf(\"%s%s\", name, buf);\n}\n\nstatic int\ninit_mcast_hash(void)\n{\n\tuint32_t i;\n\n\tmcast_hash_params.socket_id = rte_socket_id();\n\tmcast_hash = rte_fbk_hash_create(&mcast_hash_params);\n\tif (mcast_hash == NULL){\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < N_MCAST_GROUPS; i ++){\n\t\tif (rte_fbk_hash_add_key(mcast_hash,\n\t\t\tmcast_group_table[i].ip,\n\t\t\tmcast_group_table[i].port_mask) < 0) {\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_queue_conf *qconf;\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_txconf *txconf;\n\tint ret;\n\tuint16_t queueid;\n\tunsigned lcore_id = 0, rx_lcore_id = 0;\n\tuint32_t n_tx_queue, nb_lcores;\n\tuint8_t portid;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid EAL parameters\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid IPV4_MULTICAST parameters\\n\");\n\n\t/* create the mbuf pools */\n\tpacket_pool = rte_pktmbuf_pool_create(\"packet_pool\", NB_PKT_MBUF, 32,\n\t\t0, PKT_MBUF_DATA_SIZE, rte_socket_id());\n\n\tif (packet_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot init packet mbuf pool\\n\");\n\n\theader_pool = rte_pktmbuf_pool_create(\"header_pool\", NB_HDR_MBUF, 32,\n\t\t0, HDR_MBUF_DATA_SIZE, rte_socket_id());\n\n\tif (header_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot init header mbuf pool\\n\");\n\n\tclone_pool = rte_pktmbuf_pool_create(\"clone_pool\", NB_CLONE_MBUF, 32,\n\t\t0, 0, rte_socket_id());\n\n\tif (clone_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot init clone mbuf pool\\n\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports == 0)\n\t\trte_exit(EXIT_FAILURE, \"No physical ports!\\n\");\n\tif (nb_ports > MAX_PORTS)\n\t\tnb_ports = MAX_PORTS;\n\n\tnb_lcores = rte_lcore_count();\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"Skipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\n\t\tqconf = &lcore_queue_conf[rx_lcore_id];\n\n\t\t/* get the lcore_id for this port */\n\t\twhile (rte_lcore_is_enabled(rx_lcore_id) == 0 ||\n\t\t qconf->n_rx_queue == (unsigned)rx_queue_per_lcore) {\n\n\t\t\trx_lcore_id ++;\n\t\t\tqconf = &lcore_queue_conf[rx_lcore_id];\n\n\t\t\tif (rx_lcore_id >= RTE_MAX_LCORE)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Not enough cores\\n\");\n\t\t}\n\t\tqconf->rx_queue_list[qconf->n_rx_queue] = portid;\n\t\tqconf->n_rx_queue++;\n\n\t\t/* init port */\n\t\tprintf(\"Initializing port %d on lcore %u... \", portid,\n\t\t rx_lcore_id);\n\t\tfflush(stdout);\n\n\t\tn_tx_queue = nb_lcores;\n\t\tif (n_tx_queue > MAX_TX_QUEUE_PER_PORT)\n\t\t\tn_tx_queue = MAX_TX_QUEUE_PER_PORT;\n\t\tret = rte_eth_dev_configure(portid, 1, (uint16_t)n_tx_queue,\n\t\t\t\t\t &port_conf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot configure device: err=%d, port=%d\\n\",\n\t\t\t\t ret, portid);\n\n\t\trte_eth_macaddr_get(portid, &ports_eth_addr[portid]);\n\t\tprint_ethaddr(\" Address:\", &ports_eth_addr[portid]);\n\t\tprintf(\", \");\n\n\t\t/* init one RX queue */\n\t\tqueueid = 0;\n\t\tprintf(\"rxq=%hu \", queueid);\n\t\tfflush(stdout);\n\t\tret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd,\n\t\t\t\t\t rte_eth_dev_socket_id(portid),\n\t\t\t\t\t NULL,\n\t\t\t\t\t packet_pool);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup: err=%d, port=%d\\n\",\n\t\t\t\t ret, portid);\n\n\t\t/* init one TX queue per couple (lcore,port) */\n\t\tqueueid = 0;\n\n\t\tRTE_LCORE_FOREACH(lcore_id) {\n\t\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\t\tcontinue;\n\t\t\tprintf(\"txq=%u,%hu \", lcore_id, queueid);\n\t\t\tfflush(stdout);\n\n\t\t\trte_eth_dev_info_get(portid, &dev_info);\n\t\t\ttxconf = &dev_info.default_txconf;\n\t\t\ttxconf->txq_flags = 0;\n\t\t\tret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,\n\t\t\t\t\t\t rte_lcore_to_socket_id(lcore_id), txconf);\n\t\t\tif (ret < 0)\n\t\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup: err=%d, \"\n\t\t\t\t\t \"port=%d\\n\", ret, portid);\n\n\t\t\tqconf = &lcore_queue_conf[lcore_id];\n\t\t\tqconf->tx_queue_id[portid] = queueid;\n\t\t\tqueueid++;\n\t\t}\n\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_dev_start: err=%d, port=%d\\n\",\n\t\t\t\t ret, portid);\n\n\t\tprintf(\"done:\\n\");\n\t}\n\n\tcheck_all_ports_link_status(nb_ports, enabled_port_mask);\n\n\t/* initialize the multicast hash */\n\tint retval = init_mcast_hash();\n\tif (retval != 0)\n\t\trte_exit(EXIT_FAILURE, \"Cannot build the multicast hash\\n\");\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/kni/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifneq ($(CONFIG_RTE_EXEC_ENV),\"linuxapp\")\n$(error This application can only operate in a linuxapp environment, \\\nplease change the definition of the RTE_TARGET environment variable)\nendif\n\n# binary name\nAPP = kni\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/kni/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/* Macros for printing using RTE_LOG */\n#define RTE_LOGTYPE_APP RTE_LOGTYPE_USER1\n\n/* Max size of a single packet */\n#define MAX_PACKET_SZ 2048\n\n/* Size of the data buffer in each mbuf */\n#define MBUF_DATA_SZ (MAX_PACKET_SZ + RTE_PKTMBUF_HEADROOM)\n\n/* Number of mbufs in mempool that is created */\n#define NB_MBUF (8192 * 16)\n\n/* How many packets to attempt to read from NIC in one go */\n#define PKT_BURST_SZ 32\n\n/* How many objects (mbufs) to keep in per-lcore mempool cache */\n#define MEMPOOL_CACHE_SZ PKT_BURST_SZ\n\n/* Number of RX ring descriptors */\n#define NB_RXD 128\n\n/* Number of TX ring descriptors */\n#define NB_TXD 512\n\n/* Total octets in ethernet header */\n#define KNI_ENET_HEADER_SIZE 14\n\n/* Total octets in the FCS */\n#define KNI_ENET_FCS_SIZE 4\n\n#define KNI_US_PER_SECOND 1000000\n#define KNI_SECOND_PER_DAY 86400\n\n#define KNI_MAX_KTHREAD 32\n/*\n * Structure of port parameters\n */\nstruct kni_port_params {\n\tuint8_t port_id;/* Port ID */\n\tunsigned lcore_rx; /* lcore ID for RX */\n\tunsigned lcore_tx; /* lcore ID for TX */\n\tuint32_t nb_lcore_k; /* Number of lcores for KNI multi kernel threads */\n\tuint32_t nb_kni; /* Number of KNI devices to be created */\n\tunsigned lcore_k[KNI_MAX_KTHREAD]; /* lcore ID list for kthreads */\n\tstruct rte_kni *kni[KNI_MAX_KTHREAD]; /* KNI context pointers */\n} __rte_cache_aligned;\n\nstatic struct kni_port_params *kni_port_params_array[RTE_MAX_ETHPORTS];\n\n\n/* Options for configuring ethernet port */\nstatic struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.header_split = 0, /* Header Split disabled */\n\t\t.hw_ip_checksum = 0, /* IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /* VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /* Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /* CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\n/* Mempool for mbufs */\nstatic struct rte_mempool * pktmbuf_pool = NULL;\n\n/* Mask of enabled ports */\nstatic uint32_t ports_mask = 0;\n/* Ports set in promiscuous mode off by default. */\nstatic int promiscuous_on = 0;\n\n/* Structure type for recording kni interface specific stats */\nstruct kni_interface_stats {\n\t/* number of pkts received from NIC, and sent to KNI */\n\tuint64_t rx_packets;\n\n\t/* number of pkts received from NIC, but failed to send to KNI */\n\tuint64_t rx_dropped;\n\n\t/* number of pkts received from KNI, and sent to NIC */\n\tuint64_t tx_packets;\n\n\t/* number of pkts received from KNI, but failed to send to NIC */\n\tuint64_t tx_dropped;\n};\n\n/* kni device statistics array */\nstatic struct kni_interface_stats kni_stats[RTE_MAX_ETHPORTS];\n\nstatic int kni_change_mtu(uint8_t port_id, unsigned new_mtu);\nstatic int kni_config_network_interface(uint8_t port_id, uint8_t if_up);\n\nstatic rte_atomic32_t kni_stop = RTE_ATOMIC32_INIT(0);\n\n/* Print out statistics on packets handled */\nstatic void\nprint_stats(void)\n{\n\tuint8_t i;\n\n\tprintf(\"\\n**KNI example application statistics**\\n\"\n\t \"====== ============== ============ ============ ============ ============\\n\"\n\t \" Port Lcore(RX/TX) rx_packets rx_dropped tx_packets tx_dropped\\n\"\n\t \"------ -------------- ------------ ------------ ------------ ------------\\n\");\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif (!kni_port_params_array[i])\n\t\t\tcontinue;\n\n\t\tprintf(\"%7d %10u/%2u %13\"PRIu64\" %13\"PRIu64\" %13\"PRIu64\" \"\n\t\t\t\t\t\t\t\"%13\"PRIu64\"\\n\", i,\n\t\t\t\t\tkni_port_params_array[i]->lcore_rx,\n\t\t\t\t\tkni_port_params_array[i]->lcore_tx,\n\t\t\t\t\t\tkni_stats[i].rx_packets,\n\t\t\t\t\t\tkni_stats[i].rx_dropped,\n\t\t\t\t\t\tkni_stats[i].tx_packets,\n\t\t\t\t\t\tkni_stats[i].tx_dropped);\n\t}\n\tprintf(\"====== ============== ============ ============ ============ ============\\n\");\n}\n\n/* Custom handling of signals to handle stats and kni processing */\nstatic void\nsignal_handler(int signum)\n{\n\t/* When we receive a USR1 signal, print stats */\n\tif (signum == SIGUSR1) {\n\t\tprint_stats();\n\t}\n\n\t/* When we receive a USR2 signal, reset stats */\n\tif (signum == SIGUSR2) {\n\t\tmemset(&kni_stats, 0, sizeof(kni_stats));\n\t\tprintf(\"\\n**Statistics have been reset**\\n\");\n\t\treturn;\n\t}\n\n\t/* When we receive a RTMIN or SIGINT signal, stop kni processing */\n\tif (signum == SIGRTMIN || signum == SIGINT){\n\t\tprintf(\"SIGRTMIN is received, and the KNI processing is \"\n\t\t\t\t\t\t\t\"going to stop\\n\");\n\t\trte_atomic32_inc(&kni_stop);\n\t\treturn;\n }\n}\n\nstatic void\nkni_burst_free_mbufs(struct rte_mbuf **pkts, unsigned num)\n{\n\tunsigned i;\n\n\tif (pkts == NULL)\n\t\treturn;\n\n\tfor (i = 0; i < num; i++) {\n\t\trte_pktmbuf_free(pkts[i]);\n\t\tpkts[i] = NULL;\n\t}\n}\n\n/**\n * Interface to burst rx and enqueue mbufs into rx_q\n */\nstatic void\nkni_ingress(struct kni_port_params *p)\n{\n\tuint8_t i, port_id;\n\tunsigned nb_rx, num;\n\tuint32_t nb_kni;\n\tstruct rte_mbuf *pkts_burst[PKT_BURST_SZ];\n\n\tif (p == NULL)\n\t\treturn;\n\n\tnb_kni = p->nb_kni;\n\tport_id = p->port_id;\n\tfor (i = 0; i < nb_kni; i++) {\n\t\t/* Burst rx from eth */\n\t\tnb_rx = rte_eth_rx_burst(port_id, 0, pkts_burst, PKT_BURST_SZ);\n\t\tif (unlikely(nb_rx > PKT_BURST_SZ)) {\n\t\t\tRTE_LOG(ERR, APP, \"Error receiving from eth\\n\");\n\t\t\treturn;\n\t\t}\n\t\t/* Burst tx to kni */\n\t\tnum = rte_kni_tx_burst(p->kni[i], pkts_burst, nb_rx);\n\t\tkni_stats[port_id].rx_packets += num;\n\n\t\trte_kni_handle_request(p->kni[i]);\n\t\tif (unlikely(num < nb_rx)) {\n\t\t\t/* Free mbufs not tx to kni interface */\n\t\t\tkni_burst_free_mbufs(&pkts_burst[num], nb_rx - num);\n\t\t\tkni_stats[port_id].rx_dropped += nb_rx - num;\n\t\t}\n\t}\n}\n\n/**\n * Interface to dequeue mbufs from tx_q and burst tx\n */\nstatic void\nkni_egress(struct kni_port_params *p)\n{\n\tuint8_t i, port_id;\n\tunsigned nb_tx, num;\n\tuint32_t nb_kni;\n\tstruct rte_mbuf *pkts_burst[PKT_BURST_SZ];\n\n\tif (p == NULL)\n\t\treturn;\n\n\tnb_kni = p->nb_kni;\n\tport_id = p->port_id;\n\tfor (i = 0; i < nb_kni; i++) {\n\t\t/* Burst rx from kni */\n\t\tnum = rte_kni_rx_burst(p->kni[i], pkts_burst, PKT_BURST_SZ);\n\t\tif (unlikely(num > PKT_BURST_SZ)) {\n\t\t\tRTE_LOG(ERR, APP, \"Error receiving from KNI\\n\");\n\t\t\treturn;\n\t\t}\n\t\t/* Burst tx to eth */\n\t\tnb_tx = rte_eth_tx_burst(port_id, 0, pkts_burst, (uint16_t)num);\n\t\tkni_stats[port_id].tx_packets += nb_tx;\n\t\tif (unlikely(nb_tx < num)) {\n\t\t\t/* Free mbufs not tx to NIC */\n\t\t\tkni_burst_free_mbufs(&pkts_burst[nb_tx], num - nb_tx);\n\t\t\tkni_stats[port_id].tx_dropped += num - nb_tx;\n\t\t}\n\t}\n}\n\nstatic int\nmain_loop(__rte_unused void *arg)\n{\n\tuint8_t i, nb_ports = rte_eth_dev_count();\n\tint32_t f_stop;\n\tconst unsigned lcore_id = rte_lcore_id();\n\tenum lcore_rxtx {\n\t\tLCORE_NONE,\n\t\tLCORE_RX,\n\t\tLCORE_TX,\n\t\tLCORE_MAX\n\t};\n\tenum lcore_rxtx flag = LCORE_NONE;\n\n\tnb_ports = (uint8_t)(nb_ports < RTE_MAX_ETHPORTS ?\n\t\t\t\tnb_ports : RTE_MAX_ETHPORTS);\n\tfor (i = 0; i < nb_ports; i++) {\n\t\tif (!kni_port_params_array[i])\n\t\t\tcontinue;\n\t\tif (kni_port_params_array[i]->lcore_rx == (uint8_t)lcore_id) {\n\t\t\tflag = LCORE_RX;\n\t\t\tbreak;\n\t\t} else if (kni_port_params_array[i]->lcore_tx ==\n\t\t\t\t\t\t(uint8_t)lcore_id) {\n\t\t\tflag = LCORE_TX;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (flag == LCORE_RX) {\n\t\tRTE_LOG(INFO, APP, \"Lcore %u is reading from port %d\\n\",\n\t\t\t\t\tkni_port_params_array[i]->lcore_rx,\n\t\t\t\t\tkni_port_params_array[i]->port_id);\n\t\twhile (1) {\n\t\t\tf_stop = rte_atomic32_read(&kni_stop);\n\t\t\tif (f_stop)\n\t\t\t\tbreak;\n\t\t\tkni_ingress(kni_port_params_array[i]);\n\t\t}\n\t} else if (flag == LCORE_TX) {\n\t\tRTE_LOG(INFO, APP, \"Lcore %u is writing to port %d\\n\",\n\t\t\t\t\tkni_port_params_array[i]->lcore_tx,\n\t\t\t\t\tkni_port_params_array[i]->port_id);\n\t\twhile (1) {\n\t\t\tf_stop = rte_atomic32_read(&kni_stop);\n\t\t\tif (f_stop)\n\t\t\t\tbreak;\n\t\t\tkni_egress(kni_port_params_array[i]);\n\t\t}\n\t} else\n\t\tRTE_LOG(INFO, APP, \"Lcore %u has nothing to do\\n\", lcore_id);\n\n\treturn 0;\n}\n\n/* Display usage instructions */\nstatic void\nprint_usage(const char *prgname)\n{\n\tRTE_LOG(INFO, APP, \"\\nUsage: %s [EAL options] -- -p PORTMASK -P \"\n\t\t \"[--config (port,lcore_rx,lcore_tx,lcore_kthread...)\"\n\t\t \"[,(port,lcore_rx,lcore_tx,lcore_kthread...)]]\\n\"\n\t\t \" -p PORTMASK: hex bitmask of ports to use\\n\"\n\t\t \" -P : enable promiscuous mode\\n\"\n\t\t \" --config (port,lcore_rx,lcore_tx,lcore_kthread...): \"\n\t\t \"port and lcore configurations\\n\",\n\t prgname);\n}\n\n/* Convert string to unsigned number. 0 is returned if error occurs */\nstatic uint32_t\nparse_unsigned(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long num;\n\n\tnum = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn 0;\n\n\treturn (uint32_t)num;\n}\n\nstatic void\nprint_config(void)\n{\n\tuint32_t i, j;\n\tstruct kni_port_params **p = kni_port_params_array;\n\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif (!p[i])\n\t\t\tcontinue;\n\t\tRTE_LOG(DEBUG, APP, \"Port ID: %d\\n\", p[i]->port_id);\n\t\tRTE_LOG(DEBUG, APP, \"Rx lcore ID: %u, Tx lcore ID: %u\\n\",\n\t\t\t\t\tp[i]->lcore_rx, p[i]->lcore_tx);\n\t\tfor (j = 0; j < p[i]->nb_lcore_k; j++)\n\t\t\tRTE_LOG(DEBUG, APP, \"Kernel thread lcore ID: %u\\n\",\n\t\t\t\t\t\t\tp[i]->lcore_k[j]);\n\t}\n}\n\nstatic int\nparse_config(const char *arg)\n{\n\tconst char *p, *p0 = arg;\n\tchar s[256], *end;\n\tunsigned size;\n\tenum fieldnames {\n\t\tFLD_PORT = 0,\n\t\tFLD_LCORE_RX,\n\t\tFLD_LCORE_TX,\n\t\t_NUM_FLD = KNI_MAX_KTHREAD + 3,\n\t};\n\tint i, j, nb_token;\n\tchar *str_fld[_NUM_FLD];\n\tunsigned long int_fld[_NUM_FLD];\n\tuint8_t port_id, nb_kni_port_params = 0;\n\n\tmemset(&kni_port_params_array, 0, sizeof(kni_port_params_array));\n\twhile (((p = strchr(p0, '(')) != NULL) &&\n\t\tnb_kni_port_params < RTE_MAX_ETHPORTS) {\n\t\tp++;\n\t\tif ((p0 = strchr(p, ')')) == NULL)\n\t\t\tgoto fail;\n\t\tsize = p0 - p;\n\t\tif (size >= sizeof(s)) {\n\t\t\tprintf(\"Invalid config parameters\\n\");\n\t\t\tgoto fail;\n\t\t}\n\t\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\t\tnb_token = rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',');\n\t\tif (nb_token <= FLD_LCORE_TX) {\n\t\t\tprintf(\"Invalid config parameters\\n\");\n\t\t\tgoto fail;\n\t\t}\n\t\tfor (i = 0; i < nb_token; i++) {\n\t\t\terrno = 0;\n\t\t\tint_fld[i] = strtoul(str_fld[i], &end, 0);\n\t\t\tif (errno != 0 || end == str_fld[i]) {\n\t\t\t\tprintf(\"Invalid config parameters\\n\");\n\t\t\t\tgoto fail;\n\t\t\t}\n\t\t}\n\n\t\ti = 0;\n\t\tport_id = (uint8_t)int_fld[i++];\n\t\tif (port_id >= RTE_MAX_ETHPORTS) {\n\t\t\tprintf(\"Port ID %d could not exceed the maximum %d\\n\",\n\t\t\t\t\t\tport_id, RTE_MAX_ETHPORTS);\n\t\t\tgoto fail;\n\t\t}\n\t\tif (kni_port_params_array[port_id]) {\n\t\t\tprintf(\"Port %d has been configured\\n\", port_id);\n\t\t\tgoto fail;\n\t\t}\n\t\tkni_port_params_array[port_id] =\n\t\t\trte_zmalloc(\"KNI_port_params\",\n\t\t\t\t sizeof(struct kni_port_params), RTE_CACHE_LINE_SIZE);\n\t\tkni_port_params_array[port_id]->port_id = port_id;\n\t\tkni_port_params_array[port_id]->lcore_rx =\n\t\t\t\t\t(uint8_t)int_fld[i++];\n\t\tkni_port_params_array[port_id]->lcore_tx =\n\t\t\t\t\t(uint8_t)int_fld[i++];\n\t\tif (kni_port_params_array[port_id]->lcore_rx >= RTE_MAX_LCORE ||\n\t\tkni_port_params_array[port_id]->lcore_tx >= RTE_MAX_LCORE) {\n\t\t\tprintf(\"lcore_rx %u or lcore_tx %u ID could not \"\n\t\t\t\t\t\t\"exceed the maximum %u\\n\",\n\t\t\t\tkni_port_params_array[port_id]->lcore_rx,\n\t\t\t\tkni_port_params_array[port_id]->lcore_tx,\n\t\t\t\t\t\t(unsigned)RTE_MAX_LCORE);\n\t\t\tgoto fail;\n\t\t}\n\t\tfor (j = 0; i < nb_token && j < KNI_MAX_KTHREAD; i++, j++)\n\t\t\tkni_port_params_array[port_id]->lcore_k[j] =\n\t\t\t\t\t\t(uint8_t)int_fld[i];\n\t\tkni_port_params_array[port_id]->nb_lcore_k = j;\n\t}\n\tprint_config();\n\n\treturn 0;\n\nfail:\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif (kni_port_params_array[i]) {\n\t\t\trte_free(kni_port_params_array[i]);\n\t\t\tkni_port_params_array[i] = NULL;\n\t\t}\n\t}\n\n\treturn -1;\n}\n\nstatic int\nvalidate_parameters(uint32_t portmask)\n{\n\tuint32_t i;\n\n\tif (!portmask) {\n\t\tprintf(\"No port configured in port mask\\n\");\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif (((portmask & (1 << i)) && !kni_port_params_array[i]) ||\n\t\t\t(!(portmask & (1 << i)) && kni_port_params_array[i]))\n\t\t\trte_exit(EXIT_FAILURE, \"portmask is not consistent \"\n\t\t\t\t\"to port ids specified in --config\\n\");\n\n\t\tif (kni_port_params_array[i] && !rte_lcore_is_enabled(\\\n\t\t\t(unsigned)(kni_port_params_array[i]->lcore_rx)))\n\t\t\trte_exit(EXIT_FAILURE, \"lcore id %u for \"\n\t\t\t\t\t\"port %d receiving not enabled\\n\",\n\t\t\t\t\tkni_port_params_array[i]->lcore_rx,\n\t\t\t\t\tkni_port_params_array[i]->port_id);\n\n\t\tif (kni_port_params_array[i] && !rte_lcore_is_enabled(\\\n\t\t\t(unsigned)(kni_port_params_array[i]->lcore_tx)))\n\t\t\trte_exit(EXIT_FAILURE, \"lcore id %u for \"\n\t\t\t\t\t\"port %d transmitting not enabled\\n\",\n\t\t\t\t\tkni_port_params_array[i]->lcore_tx,\n\t\t\t\t\tkni_port_params_array[i]->port_id);\n\n\t}\n\n\treturn 0;\n}\n\n#define CMDLINE_OPT_CONFIG \"config\"\n\n/* Parse the arguments given in the command line of the application */\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt, longindex, ret = 0;\n\tconst char *prgname = argv[0];\n\tstatic struct option longopts[] = {\n\t\t{CMDLINE_OPT_CONFIG, required_argument, NULL, 0},\n\t\t{NULL, 0, NULL, 0}\n\t};\n\n\t/* Disable printing messages within getopt() */\n\topterr = 0;\n\n\t/* Parse command line */\n\twhile ((opt = getopt_long(argc, argv, \"p:P\", longopts,\n\t\t\t\t\t\t&longindex)) != EOF) {\n\t\tswitch (opt) {\n\t\tcase 'p':\n\t\t\tports_mask = parse_unsigned(optarg);\n\t\t\tbreak;\n\t\tcase 'P':\n\t\t\tpromiscuous_on = 1;\n\t\t\tbreak;\n\t\tcase 0:\n\t\t\tif (!strncmp(longopts[longindex].name,\n\t\t\t\t CMDLINE_OPT_CONFIG,\n\t\t\t\t sizeof(CMDLINE_OPT_CONFIG))) {\n\t\t\t\tret = parse_config(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"Invalid config\\n\");\n\t\t\t\t\tprint_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\trte_exit(EXIT_FAILURE, \"Invalid option specified\\n\");\n\t\t}\n\t}\n\n\t/* Check that options were parsed ok */\n\tif (validate_parameters(ports_mask) < 0) {\n\t\tprint_usage(prgname);\n\t\trte_exit(EXIT_FAILURE, \"Invalid parameters\\n\");\n\t}\n\n\treturn ret;\n}\n\n/* Initialize KNI subsystem */\nstatic void\ninit_kni(void)\n{\n\tunsigned int num_of_kni_ports = 0, i;\n\tstruct kni_port_params **params = kni_port_params_array;\n\n\t/* Calculate the maximum number of KNI interfaces that will be used */\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif (kni_port_params_array[i]) {\n\t\t\tnum_of_kni_ports += (params[i]->nb_lcore_k ?\n\t\t\t\tparams[i]->nb_lcore_k : 1);\n\t\t}\n\t}\n\n\t/* Invoke rte KNI init to preallocate the ports */\n\trte_kni_init(num_of_kni_ports);\n}\n\n/* Initialise a single port on an Ethernet device */\nstatic void\ninit_port(uint8_t port)\n{\n\tint ret;\n\n\t/* Initialise device and RX/TX queues */\n\tRTE_LOG(INFO, APP, \"Initialising port %u ...\\n\", (unsigned)port);\n\tfflush(stdout);\n\tret = rte_eth_dev_configure(port, 1, 1, &port_conf);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Could not configure port%u (%d)\\n\",\n\t\t (unsigned)port, ret);\n\n\tret = rte_eth_rx_queue_setup(port, 0, NB_RXD,\n\t\trte_eth_dev_socket_id(port), NULL, pktmbuf_pool);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Could not setup up RX queue for \"\n\t\t\t\t\"port%u (%d)\\n\", (unsigned)port, ret);\n\n\tret = rte_eth_tx_queue_setup(port, 0, NB_TXD,\n\t\trte_eth_dev_socket_id(port), NULL);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Could not setup up TX queue for \"\n\t\t\t\t\"port%u (%d)\\n\", (unsigned)port, ret);\n\n\tret = rte_eth_dev_start(port);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Could not start port%u (%d)\\n\",\n\t\t\t\t\t\t(unsigned)port, ret);\n\n\tif (promiscuous_on)\n\t\trte_eth_promiscuous_enable(port);\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\\n\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\n/* Callback for request of changing MTU */\nstatic int\nkni_change_mtu(uint8_t port_id, unsigned new_mtu)\n{\n\tint ret;\n\tstruct rte_eth_conf conf;\n\n\tif (port_id >= rte_eth_dev_count()) {\n\t\tRTE_LOG(ERR, APP, \"Invalid port id %d\\n\", port_id);\n\t\treturn -EINVAL;\n\t}\n\n\tRTE_LOG(INFO, APP, \"Change MTU of port %d to %u\\n\", port_id, new_mtu);\n\n\t/* Stop specific port */\n\trte_eth_dev_stop(port_id);\n\n\tmemcpy(&conf, &port_conf, sizeof(conf));\n\t/* Set new MTU */\n\tif (new_mtu > ETHER_MAX_LEN)\n\t\tconf.rxmode.jumbo_frame = 1;\n\telse\n\t\tconf.rxmode.jumbo_frame = 0;\n\n\t/* mtu + length of header + length of FCS = max pkt length */\n\tconf.rxmode.max_rx_pkt_len = new_mtu + KNI_ENET_HEADER_SIZE +\n\t\t\t\t\t\t\tKNI_ENET_FCS_SIZE;\n\tret = rte_eth_dev_configure(port_id, 1, 1, &conf);\n\tif (ret < 0) {\n\t\tRTE_LOG(ERR, APP, \"Fail to reconfigure port %d\\n\", port_id);\n\t\treturn ret;\n\t}\n\n\t/* Restart specific port */\n\tret = rte_eth_dev_start(port_id);\n\tif (ret < 0) {\n\t\tRTE_LOG(ERR, APP, \"Fail to restart port %d\\n\", port_id);\n\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\n/* Callback for request of configuring network interface up/down */\nstatic int\nkni_config_network_interface(uint8_t port_id, uint8_t if_up)\n{\n\tint ret = 0;\n\n\tif (port_id >= rte_eth_dev_count() || port_id >= RTE_MAX_ETHPORTS) {\n\t\tRTE_LOG(ERR, APP, \"Invalid port id %d\\n\", port_id);\n\t\treturn -EINVAL;\n\t}\n\n\tRTE_LOG(INFO, APP, \"Configure network interface of %d %s\\n\",\n\t\t\t\t\tport_id, if_up ? \"up\" : \"down\");\n\n\tif (if_up != 0) { /* Configure network interface up */\n\t\trte_eth_dev_stop(port_id);\n\t\tret = rte_eth_dev_start(port_id);\n\t} else /* Configure network interface down */\n\t\trte_eth_dev_stop(port_id);\n\n\tif (ret < 0)\n\t\tRTE_LOG(ERR, APP, \"Failed to start port %d\\n\", port_id);\n\n\treturn ret;\n}\n\nstatic int\nkni_alloc(uint8_t port_id)\n{\n\tuint8_t i;\n\tstruct rte_kni *kni;\n\tstruct rte_kni_conf conf;\n\tstruct kni_port_params **params = kni_port_params_array;\n\n\tif (port_id >= RTE_MAX_ETHPORTS || !params[port_id])\n\t\treturn -1;\n\n\tparams[port_id]->nb_kni = params[port_id]->nb_lcore_k ?\n\t\t\t\tparams[port_id]->nb_lcore_k : 1;\n\n\tfor (i = 0; i < params[port_id]->nb_kni; i++) {\n\t\t/* Clear conf at first */\n\t\tmemset(&conf, 0, sizeof(conf));\n\t\tif (params[port_id]->nb_lcore_k) {\n\t\t\tsnprintf(conf.name, RTE_KNI_NAMESIZE,\n\t\t\t\t\t\"vEth%u_%u\", port_id, i);\n\t\t\tconf.core_id = params[port_id]->lcore_k[i];\n\t\t\tconf.force_bind = 1;\n\t\t} else\n\t\t\tsnprintf(conf.name, RTE_KNI_NAMESIZE,\n\t\t\t\t\t\t\"vEth%u\", port_id);\n\t\tconf.group_id = (uint16_t)port_id;\n\t\tconf.mbuf_size = MAX_PACKET_SZ;\n\t\t/*\n\t\t * The first KNI device associated to a port\n\t\t * is the master, for multiple kernel thread\n\t\t * environment.\n\t\t */\n\t\tif (i == 0) {\n\t\t\tstruct rte_kni_ops ops;\n\t\t\tstruct rte_eth_dev_info dev_info;\n\n\t\t\tmemset(&dev_info, 0, sizeof(dev_info));\n\t\t\trte_eth_dev_info_get(port_id, &dev_info);\n\t\t\tconf.addr = dev_info.pci_dev->addr;\n\t\t\tconf.id = dev_info.pci_dev->id;\n\n\t\t\tmemset(&ops, 0, sizeof(ops));\n\t\t\tops.port_id = port_id;\n\t\t\tops.change_mtu = kni_change_mtu;\n\t\t\tops.config_network_if = kni_config_network_interface;\n\n\t\t\tkni = rte_kni_alloc(pktmbuf_pool, &conf, &ops);\n\t\t} else\n\t\t\tkni = rte_kni_alloc(pktmbuf_pool, &conf, NULL);\n\n\t\tif (!kni)\n\t\t\trte_exit(EXIT_FAILURE, \"Fail to create kni for \"\n\t\t\t\t\t\t\"port: %d\\n\", port_id);\n\t\tparams[port_id]->kni[i] = kni;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nkni_free_kni(uint8_t port_id)\n{\n\tuint8_t i;\n\tstruct kni_port_params **p = kni_port_params_array;\n\n\tif (port_id >= RTE_MAX_ETHPORTS || !p[port_id])\n\t\treturn -1;\n\n\tfor (i = 0; i < p[port_id]->nb_kni; i++) {\n\t\trte_kni_release(p[port_id]->kni[i]);\n\t\tp[port_id]->kni[i] = NULL;\n\t}\n\trte_eth_dev_stop(port_id);\n\n\treturn 0;\n}\n\n/* Initialise ports/queues etc. and start main loop on each core */\nint\nmain(int argc, char** argv)\n{\n\tint ret;\n\tuint8_t nb_sys_ports, port;\n\tunsigned i;\n\n\t/* Associate signal_hanlder function with USR signals */\n\tsignal(SIGUSR1, signal_handler);\n\tsignal(SIGUSR2, signal_handler);\n\tsignal(SIGRTMIN, signal_handler);\n\tsignal(SIGINT, signal_handler);\n\n\t/* Initialise EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Could not initialise EAL (%d)\\n\", ret);\n\targc -= ret;\n\targv += ret;\n\n\t/* Parse application arguments (after the EAL ones) */\n\tret = parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Could not parse input parameters\\n\");\n\n\t/* Create the mbuf pool */\n\tpktmbuf_pool = rte_pktmbuf_pool_create(\"mbuf_pool\", NB_MBUF,\n\t\tMEMPOOL_CACHE_SZ, 0, MBUF_DATA_SZ, rte_socket_id());\n\tif (pktmbuf_pool == NULL) {\n\t\trte_exit(EXIT_FAILURE, \"Could not initialise mbuf pool\\n\");\n\t\treturn -1;\n\t}\n\n\t/* Get number of ports found in scan */\n\tnb_sys_ports = rte_eth_dev_count();\n\tif (nb_sys_ports == 0)\n\t\trte_exit(EXIT_FAILURE, \"No supported Ethernet device found\\n\");\n\n\t/* Check if the configured port ID is valid */\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++)\n\t\tif (kni_port_params_array[i] && i >= nb_sys_ports)\n\t\t\trte_exit(EXIT_FAILURE, \"Configured invalid \"\n\t\t\t\t\t\t\"port ID %u\\n\", i);\n\n\t/* Initialize KNI subsystem */\n\tinit_kni();\n\n\t/* Initialise each port */\n\tfor (port = 0; port < nb_sys_ports; port++) {\n\t\t/* Skip ports that are not enabled */\n\t\tif (!(ports_mask & (1 << port)))\n\t\t\tcontinue;\n\t\tinit_port(port);\n\n\t\tif (port >= RTE_MAX_ETHPORTS)\n\t\t\trte_exit(EXIT_FAILURE, \"Can not use more than \"\n\t\t\t\t\"%d ports for kni\\n\", RTE_MAX_ETHPORTS);\n\n\t\tkni_alloc(port);\n\t}\n\tcheck_all_ports_link_status(nb_sys_ports, ports_mask);\n\n\t/* Launch per-lcore function on every lcore */\n\trte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(i) {\n\t\tif (rte_eal_wait_lcore(i) < 0)\n\t\t\treturn -1;\n\t}\n\n\t/* Release resources */\n\tfor (port = 0; port < nb_sys_ports; port++) {\n\t\tif (!(ports_mask & (1 << port)))\n\t\t\tcontinue;\n\t\tkni_free_kni(port);\n\t}\n#ifdef RTE_LIBRTE_XEN_DOM0\n\trte_kni_close();\n#endif\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++)\n\t\tif (kni_port_params_array[i]) {\n\t\t\trte_free(kni_port_params_array[i]);\n\t\t\tkni_port_params_array[i] = NULL;\n\t\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/l2fwd/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = l2fwd\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/l2fwd/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define RTE_LOGTYPE_L2FWD RTE_LOGTYPE_USER1\n\n#define NB_MBUF 8192\n\n#define MAX_PKT_BURST 32\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n/* ethernet addresses of ports */\nstatic struct ether_addr l2fwd_ports_eth_addr[RTE_MAX_ETHPORTS];\n\n/* mask of enabled ports */\nstatic uint32_t l2fwd_enabled_port_mask = 0;\n\n/* list of enabled ports */\nstatic uint32_t l2fwd_dst_ports[RTE_MAX_ETHPORTS];\n\nstatic unsigned int l2fwd_rx_queue_per_lcore = 1;\n\nstruct mbuf_table {\n\tunsigned len;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST];\n};\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT 16\nstruct lcore_queue_conf {\n\tunsigned n_rx_port;\n\tunsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE];\n\tstruct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];\n\n} __rte_cache_aligned;\nstruct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];\n\nstatic const struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\nstruct rte_mempool * l2fwd_pktmbuf_pool = NULL;\n\n/* Per-port statistics struct */\nstruct l2fwd_port_statistics {\n\tuint64_t tx;\n\tuint64_t rx;\n\tuint64_t dropped;\n} __rte_cache_aligned;\nstruct l2fwd_port_statistics port_statistics[RTE_MAX_ETHPORTS];\n\n/* A tsc-based timer responsible for triggering statistics printout */\n#define TIMER_MILLISECOND 2000000ULL /* around 1ms at 2 Ghz */\n#define MAX_TIMER_PERIOD 86400 /* 1 day max */\nstatic int64_t timer_period = 10 * TIMER_MILLISECOND * 1000; /* default period is 10 seconds */\n\n/* Print out statistics on packets dropped */\nstatic void\nprint_stats(void)\n{\n\tuint64_t total_packets_dropped, total_packets_tx, total_packets_rx;\n\tunsigned portid;\n\n\ttotal_packets_dropped = 0;\n\ttotal_packets_tx = 0;\n\ttotal_packets_rx = 0;\n\n\tconst char clr[] = { 27, '[', '2', 'J', '\\0' };\n\tconst char topLeft[] = { 27, '[', '1', ';', '1', 'H','\\0' };\n\n\t\t/* Clear screen and move to top left */\n\tprintf(\"%s%s\", clr, topLeft);\n\n\tprintf(\"\\nPort statistics ====================================\");\n\n\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t/* skip disabled ports */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\t\tprintf(\"\\nStatistics for port %u ------------------------------\"\n\t\t\t \"\\nPackets sent: %24\"PRIu64\n\t\t\t \"\\nPackets received: %20\"PRIu64\n\t\t\t \"\\nPackets dropped: %21\"PRIu64,\n\t\t\t portid,\n\t\t\t port_statistics[portid].tx,\n\t\t\t port_statistics[portid].rx,\n\t\t\t port_statistics[portid].dropped);\n\n\t\ttotal_packets_dropped += port_statistics[portid].dropped;\n\t\ttotal_packets_tx += port_statistics[portid].tx;\n\t\ttotal_packets_rx += port_statistics[portid].rx;\n\t}\n\tprintf(\"\\nAggregate statistics ===============================\"\n\t\t \"\\nTotal packets sent: %18\"PRIu64\n\t\t \"\\nTotal packets received: %14\"PRIu64\n\t\t \"\\nTotal packets dropped: %15\"PRIu64,\n\t\t total_packets_tx,\n\t\t total_packets_rx,\n\t\t total_packets_dropped);\n\tprintf(\"\\n====================================================\\n\");\n}\n\n/* Send the burst of packets on an output interface */\nstatic int\nl2fwd_send_burst(struct lcore_queue_conf *qconf, unsigned n, uint8_t port)\n{\n\tstruct rte_mbuf **m_table;\n\tunsigned ret;\n\tunsigned queueid =0;\n\n\tm_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;\n\n\tret = rte_eth_tx_burst(port, (uint16_t) queueid, m_table, (uint16_t) n);\n\tport_statistics[port].tx += ret;\n\tif (unlikely(ret < n)) {\n\t\tport_statistics[port].dropped += (n - ret);\n\t\tdo {\n\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t} while (++ret < n);\n\t}\n\n\treturn 0;\n}\n\n/* Enqueue packets for TX and prepare them to be sent */\nstatic int\nl2fwd_send_packet(struct rte_mbuf *m, uint8_t port)\n{\n\tunsigned lcore_id, len;\n\tstruct lcore_queue_conf *qconf;\n\n\tlcore_id = rte_lcore_id();\n\n\tqconf = &lcore_queue_conf[lcore_id];\n\tlen = qconf->tx_mbufs[port].len;\n\tqconf->tx_mbufs[port].m_table[len] = m;\n\tlen++;\n\n\t/* enough pkts to be sent */\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tl2fwd_send_burst(qconf, MAX_PKT_BURST, port);\n\t\tlen = 0;\n\t}\n\n\tqconf->tx_mbufs[port].len = len;\n\treturn 0;\n}\n\nstatic void\nl2fwd_simple_forward(struct rte_mbuf *m, unsigned portid)\n{\n\tstruct ether_hdr *eth;\n\tvoid *tmp;\n\tunsigned dst_port;\n\n\tdst_port = l2fwd_dst_ports[portid];\n\teth = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\t/* 02:00:00:00:00:xx */\n\ttmp = ð->d_addr.addr_bytes[0];\n\t*((uint64_t *)tmp) = 0x000000000002 + ((uint64_t)dst_port << 40);\n\n\t/* src addr */\n\tether_addr_copy(&l2fwd_ports_eth_addr[dst_port], ð->s_addr);\n\n\tl2fwd_send_packet(m, (uint8_t) dst_port);\n}\n\n/* main processing loop */\nstatic void\nl2fwd_main_loop(void)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_mbuf *m;\n\tunsigned lcore_id;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc, timer_tsc;\n\tunsigned i, j, portid, nb_rx;\n\tstruct lcore_queue_conf *qconf;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\tprev_tsc = 0;\n\ttimer_tsc = 0;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_queue_conf[lcore_id];\n\n\tif (qconf->n_rx_port == 0) {\n\t\tRTE_LOG(INFO, L2FWD, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn;\n\t}\n\n\tRTE_LOG(INFO, L2FWD, \"entering main loop on lcore %u\\n\", lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\n\t\tportid = qconf->rx_port_list[i];\n\t\tRTE_LOG(INFO, L2FWD, \" -- lcoreid=%u portid=%u\\n\", lcore_id,\n\t\t\tportid);\n\t}\n\n\twhile (1) {\n\n\t\tcur_tsc = rte_rdtsc();\n\n\t\t/*\n\t\t * TX burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t\t\tif (qconf->tx_mbufs[portid].len == 0)\n\t\t\t\t\tcontinue;\n\t\t\t\tl2fwd_send_burst(&lcore_queue_conf[lcore_id],\n\t\t\t\t\t\t qconf->tx_mbufs[portid].len,\n\t\t\t\t\t\t (uint8_t) portid);\n\t\t\t\tqconf->tx_mbufs[portid].len = 0;\n\t\t\t}\n\n\t\t\t/* if timer is enabled */\n\t\t\tif (timer_period > 0) {\n\n\t\t\t\t/* advance the timer */\n\t\t\t\ttimer_tsc += diff_tsc;\n\n\t\t\t\t/* if timer has reached its timeout */\n\t\t\t\tif (unlikely(timer_tsc >= (uint64_t) timer_period)) {\n\n\t\t\t\t\t/* do this only on master core */\n\t\t\t\t\tif (lcore_id == rte_get_master_lcore()) {\n\t\t\t\t\t\tprint_stats();\n\t\t\t\t\t\t/* reset the timer */\n\t\t\t\t\t\ttimer_tsc = 0;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tprev_tsc = cur_tsc;\n\t\t}\n\n\t\t/*\n\t\t * Read packet from RX queues\n\t\t */\n\t\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\n\t\t\tportid = qconf->rx_port_list[i];\n\t\t\tnb_rx = rte_eth_rx_burst((uint8_t) portid, 0,\n\t\t\t\t\t\t pkts_burst, MAX_PKT_BURST);\n\n\t\t\tport_statistics[portid].rx += nb_rx;\n\n\t\t\tfor (j = 0; j < nb_rx; j++) {\n\t\t\t\tm = pkts_burst[j];\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(m, void *));\n\t\t\t\tl2fwd_simple_forward(m, portid);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic int\nl2fwd_launch_one_lcore(__attribute__((unused)) void *dummy)\n{\n\tl2fwd_main_loop();\n\treturn 0;\n}\n\n/* display usage */\nstatic void\nl2fwd_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK [-q NQ]\\n\"\n\t \" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t \" -q NQ: number of queue (=ports) per lcore (default is 1)\\n\"\n\t\t \" -T PERIOD: statistics will be refreshed each PERIOD seconds (0 to disable, 10 default, 86400 maximum)\\n\",\n\t prgname);\n}\n\nstatic int\nl2fwd_parse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\nstatic unsigned int\nl2fwd_parse_nqueue(const char *q_arg)\n{\n\tchar *end = NULL;\n\tunsigned long n;\n\n\t/* parse hexadecimal string */\n\tn = strtoul(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn 0;\n\tif (n == 0)\n\t\treturn 0;\n\tif (n >= MAX_RX_QUEUE_PER_LCORE)\n\t\treturn 0;\n\n\treturn n;\n}\n\nstatic int\nl2fwd_parse_timer_period(const char *q_arg)\n{\n\tchar *end = NULL;\n\tint n;\n\n\t/* parse number string */\n\tn = strtol(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\tif (n >= MAX_TIMER_PERIOD)\n\t\treturn -1;\n\n\treturn n;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nl2fwd_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:q:T:\",\n\t\t\t\t lgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tl2fwd_enabled_port_mask = l2fwd_parse_portmask(optarg);\n\t\t\tif (l2fwd_enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tl2fwd_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* nqueue */\n\t\tcase 'q':\n\t\t\tl2fwd_rx_queue_per_lcore = l2fwd_parse_nqueue(optarg);\n\t\t\tif (l2fwd_rx_queue_per_lcore == 0) {\n\t\t\t\tprintf(\"invalid queue number\\n\");\n\t\t\t\tl2fwd_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* timer period */\n\t\tcase 'T':\n\t\t\ttimer_period = l2fwd_parse_timer_period(optarg) * 1000 * TIMER_MILLISECOND;\n\t\t\tif (timer_period < 0) {\n\t\t\t\tprintf(\"invalid timer period\\n\");\n\t\t\t\tl2fwd_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tl2fwd_usage(prgname);\n\t\t\treturn -1;\n\n\t\tdefault:\n\t\t\tl2fwd_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_queue_conf *qconf;\n\tstruct rte_eth_dev_info dev_info;\n\tint ret;\n\tuint8_t nb_ports;\n\tuint8_t nb_ports_available;\n\tuint8_t portid, last_port;\n\tunsigned lcore_id, rx_lcore_id;\n\tunsigned nb_ports_in_mask = 0;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid EAL arguments\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = l2fwd_parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid L2FWD arguments\\n\");\n\n\t/* create the mbuf pool */\n\tl2fwd_pktmbuf_pool = rte_pktmbuf_pool_create(\"mbuf_pool\", NB_MBUF, 32,\n\t\t0, RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\tif (l2fwd_pktmbuf_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot init mbuf pool\\n\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports == 0)\n\t\trte_exit(EXIT_FAILURE, \"No Ethernet ports - bye\\n\");\n\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\t/* reset l2fwd_dst_ports */\n\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++)\n\t\tl2fwd_dst_ports[portid] = 0;\n\tlast_port = 0;\n\n\t/*\n\t * Each logical core is assigned a dedicated TX queue on each port.\n\t */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\n\t\tif (nb_ports_in_mask % 2) {\n\t\t\tl2fwd_dst_ports[portid] = last_port;\n\t\t\tl2fwd_dst_ports[last_port] = portid;\n\t\t}\n\t\telse\n\t\t\tlast_port = portid;\n\n\t\tnb_ports_in_mask++;\n\n\t\trte_eth_dev_info_get(portid, &dev_info);\n\t}\n\tif (nb_ports_in_mask % 2) {\n\t\tprintf(\"Notice: odd number of ports in portmask.\\n\");\n\t\tl2fwd_dst_ports[last_port] = last_port;\n\t}\n\n\trx_lcore_id = 0;\n\tqconf = NULL;\n\n\t/* Initialize the port/queue configuration of each logical core */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\n\t\t/* get the lcore_id for this port */\n\t\twhile (rte_lcore_is_enabled(rx_lcore_id) == 0 ||\n\t\t lcore_queue_conf[rx_lcore_id].n_rx_port ==\n\t\t l2fwd_rx_queue_per_lcore) {\n\t\t\trx_lcore_id++;\n\t\t\tif (rx_lcore_id >= RTE_MAX_LCORE)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Not enough cores\\n\");\n\t\t}\n\n\t\tif (qconf != &lcore_queue_conf[rx_lcore_id])\n\t\t\t/* Assigned a new logical core in the loop above. */\n\t\t\tqconf = &lcore_queue_conf[rx_lcore_id];\n\n\t\tqconf->rx_port_list[qconf->n_rx_port] = portid;\n\t\tqconf->n_rx_port++;\n\t\tprintf(\"Lcore %u: RX port %u\\n\", rx_lcore_id, (unsigned) portid);\n\t}\n\n\tnb_ports_available = nb_ports;\n\n\t/* Initialise each port */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"Skipping disabled port %u\\n\", (unsigned) portid);\n\t\t\tnb_ports_available--;\n\t\t\tcontinue;\n\t\t}\n\t\t/* init port */\n\t\tprintf(\"Initializing port %u... \", (unsigned) portid);\n\t\tfflush(stdout);\n\t\tret = rte_eth_dev_configure(portid, 1, 1, &port_conf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot configure device: err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\trte_eth_macaddr_get(portid,&l2fwd_ports_eth_addr[portid]);\n\n\t\t/* init one RX queue */\n\t\tfflush(stdout);\n\t\tret = rte_eth_rx_queue_setup(portid, 0, nb_rxd,\n\t\t\t\t\t rte_eth_dev_socket_id(portid),\n\t\t\t\t\t NULL,\n\t\t\t\t\t l2fwd_pktmbuf_pool);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup:err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\t/* init one TX queue on each port */\n\t\tfflush(stdout);\n\t\tret = rte_eth_tx_queue_setup(portid, 0, nb_txd,\n\t\t\t\trte_eth_dev_socket_id(portid),\n\t\t\t\tNULL);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup:err=%d, port=%u\\n\",\n\t\t\t\tret, (unsigned) portid);\n\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_dev_start:err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\tprintf(\"done: \\n\");\n\n\t\trte_eth_promiscuous_enable(portid);\n\n\t\tprintf(\"Port %u, MAC address: %02X:%02X:%02X:%02X:%02X:%02X\\n\\n\",\n\t\t\t\t(unsigned) portid,\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[0],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[1],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[2],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[3],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[4],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[5]);\n\n\t\t/* initialize port stats */\n\t\tmemset(&port_statistics, 0, sizeof(port_statistics));\n\t}\n\n\tif (!nb_ports_available) {\n\t\trte_exit(EXIT_FAILURE,\n\t\t\t\"All available ports are disabled. Please set portmask.\\n\");\n\t}\n\n\tcheck_all_ports_link_status(nb_ports, l2fwd_enabled_port_mask);\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(l2fwd_launch_one_lcore, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/l2fwd-ivshmem/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-ivshmem-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nDIRS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += host guest\n\ninclude $(RTE_SDK)/mk/rte.extsubdir.mk\n" }, { "path": "examples/l2fwd-ivshmem/guest/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-ivshmem-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = guest\n\n# all source are stored in SRCS-y\nSRCS-y := guest.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/l2fwd-ivshmem/guest/guest.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"../include/common.h\"\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT 16\nstruct lcore_queue_conf {\n\tunsigned n_rx_port;\n\tunsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE];\n\tstruct mbuf_table rx_mbufs[RTE_MAX_ETHPORTS];\n\tstruct vm_port_param * port_param[MAX_RX_QUEUE_PER_LCORE];\n} __rte_cache_aligned;\nstatic struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];\n\n/* Print out statistics on packets dropped */\nstatic void\nprint_stats(void)\n{\n\tuint64_t total_packets_dropped, total_packets_tx, total_packets_rx;\n\tunsigned portid;\n\n\ttotal_packets_dropped = 0;\n\ttotal_packets_tx = 0;\n\ttotal_packets_rx = 0;\n\n\tconst char clr[] = { 27, '[', '2', 'J', '\\0' };\n\tconst char topLeft[] = { 27, '[', '1', ';', '1', 'H','\\0' };\n\n\t\t/* Clear screen and move to top left */\n\tprintf(\"%s%s\", clr, topLeft);\n\n\tprintf(\"\\nPort statistics ====================================\");\n\n\tfor (portid = 0; portid < ctrl->nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tprintf(\"\\nStatistics for port %u ------------------------------\"\n\t\t\t \"\\nPackets sent: %24\"PRIu64\n\t\t\t \"\\nPackets received: %20\"PRIu64\n\t\t\t \"\\nPackets dropped: %21\"PRIu64,\n\t\t\t portid,\n\t\t\t ctrl->vm_ports[portid].stats.tx,\n\t\t\t ctrl->vm_ports[portid].stats.rx,\n\t\t\t ctrl->vm_ports[portid].stats.dropped);\n\n\t\ttotal_packets_dropped += ctrl->vm_ports[portid].stats.dropped;\n\t\ttotal_packets_tx += ctrl->vm_ports[portid].stats.tx;\n\t\ttotal_packets_rx += ctrl->vm_ports[portid].stats.rx;\n\t}\n\tprintf(\"\\nAggregate statistics ===============================\"\n\t\t \"\\nTotal packets sent: %18\"PRIu64\n\t\t \"\\nTotal packets received: %14\"PRIu64\n\t\t \"\\nTotal packets dropped: %15\"PRIu64,\n\t\t total_packets_tx,\n\t\t total_packets_rx,\n\t\t total_packets_dropped);\n\tprintf(\"\\n====================================================\\n\");\n}\n\n/* display usage */\nstatic void\nl2fwd_ivshmem_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- [-q NQ -T PERIOD]\\n\"\n\t\t \" -q NQ: number of queue (=ports) per lcore (default is 1)\\n\"\n\t\t \" -T PERIOD: statistics will be refreshed each PERIOD seconds (0 to disable, 10 default, 86400 maximum)\\n\",\n\t prgname);\n}\n\nstatic unsigned int\nl2fwd_ivshmem_parse_nqueue(const char *q_arg)\n{\n\tchar *end = NULL;\n\tunsigned long n;\n\n\t/* parse hexadecimal string */\n\tn = strtoul(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn 0;\n\tif (n == 0)\n\t\treturn 0;\n\tif (n >= MAX_RX_QUEUE_PER_LCORE)\n\t\treturn 0;\n\n\treturn n;\n}\n\nstatic int\nl2fwd_ivshmem_parse_timer_period(const char *q_arg)\n{\n\tchar *end = NULL;\n\tint n;\n\n\t/* parse number string */\n\tn = strtol(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\tif (n >= MAX_TIMER_PERIOD)\n\t\treturn -1;\n\n\treturn n;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nl2fwd_ivshmem_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"q:p:T:\",\n\t\t\t\t lgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\n\t\t/* nqueue */\n\t\tcase 'q':\n\t\t\tl2fwd_ivshmem_rx_queue_per_lcore = l2fwd_ivshmem_parse_nqueue(optarg);\n\t\t\tif (l2fwd_ivshmem_rx_queue_per_lcore == 0) {\n\t\t\t\tprintf(\"invalid queue number\\n\");\n\t\t\t\tl2fwd_ivshmem_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* timer period */\n\t\tcase 'T':\n\t\t\ttimer_period = l2fwd_ivshmem_parse_timer_period(optarg) * 1000 * TIMER_MILLISECOND;\n\t\t\tif (timer_period < 0) {\n\t\t\t\tprintf(\"invalid timer period\\n\");\n\t\t\t\tl2fwd_ivshmem_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tl2fwd_ivshmem_usage(prgname);\n\t\t\treturn -1;\n\n\t\tdefault:\n\t\t\tl2fwd_ivshmem_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\n/*\n * this loop is getting packets from RX rings of each port, and puts them\n * into TX rings of destination ports.\n */\nstatic void\nfwd_loop(void)\n{\n\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_mbuf **m_table;\n\tstruct rte_mbuf *m;\n\tstruct rte_ring *rx, *tx;\n\tunsigned lcore_id, len;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc, timer_tsc;\n\tunsigned i, j, portid, nb_rx;\n\tstruct lcore_queue_conf *qconf;\n\tstruct ether_hdr *eth;\n\tvoid *tmp;\n\n\tprev_tsc = 0;\n\ttimer_tsc = 0;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_queue_conf[lcore_id];\n\n\tif (qconf->n_rx_port == 0) {\n\t\tRTE_LOG(INFO, L2FWD_IVSHMEM, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn;\n\t}\n\n\tRTE_LOG(INFO, L2FWD_IVSHMEM, \"entering main loop on lcore %u\\n\", lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\t\tportid = qconf->rx_port_list[i];\n\t\tRTE_LOG(INFO, L2FWD_IVSHMEM, \" -- lcoreid=%u portid=%u\\n\", lcore_id,\n\t\t\tportid);\n\t}\n\n\twhile (ctrl->state == STATE_FWD) {\n\t\tcur_tsc = rte_rdtsc();\n\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\n\t\t/*\n\t\t * Read packet from RX queues and send it to TX queues\n\t\t */\n\t\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\n\t\t\tportid = qconf->rx_port_list[i];\n\n\t\t\tlen = qconf->rx_mbufs[portid].len;\n\n\t\t\trx = ctrl->vm_ports[portid].rx_ring;\n\t\t\ttx = ctrl->vm_ports[portid].dst->tx_ring;\n\n\t\t\tm_table = qconf->rx_mbufs[portid].m_table;\n\n\t\t\t/* if we have something in the queue, try and transmit it down */\n\t\t\tif (len != 0) {\n\n\t\t\t\t/* if we succeed in sending the packets down, mark queue as free */\n\t\t\t\tif (rte_ring_enqueue_bulk(tx, (void**) m_table, len) == 0) {\n\t\t\t\t\tctrl->vm_ports[portid].stats.tx += len;\n\t\t\t\t\tqconf->rx_mbufs[portid].len = 0;\n\t\t\t\t\tlen = 0;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tnb_rx = rte_ring_count(rx);\n\n\t\t\tnb_rx = RTE_MIN(nb_rx, (unsigned) MAX_PKT_BURST);\n\n\t\t\tif (nb_rx == 0)\n\t\t\t\tcontinue;\n\n\t\t\t/* if we can get packets into the m_table */\n\t\t\tif (nb_rx < (RTE_DIM(qconf->rx_mbufs[portid].m_table) - len)) {\n\n\t\t\t\t/* this situation cannot exist, so if we fail to dequeue, that\n\t\t\t\t * means something went horribly wrong, hence the failure. */\n\t\t\t\tif (rte_ring_dequeue_bulk(rx, (void**) pkts_burst, nb_rx) < 0) {\n\t\t\t\t\tctrl->state = STATE_FAIL;\n\t\t\t\t\treturn;\n\t\t\t\t}\n\n\t\t\t\tctrl->vm_ports[portid].stats.rx += nb_rx;\n\n\t\t\t\t/* put packets into the queue */\n\t\t\t\tfor (j = 0; j < nb_rx; j++) {\n\t\t\t\t\tm = pkts_burst[j];\n\n\t\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(m, void *));\n\n\t\t\t\t\tm_table[len + j] = m;\n\n\t\t\t\t\teth = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\t\t\t\t\t/* 02:00:00:00:00:xx */\n\t\t\t\t\ttmp = ð->d_addr.addr_bytes[0];\n\t\t\t\t\t*((uint64_t *)tmp) = 0x000000000002 + ((uint64_t)portid << 40);\n\n\t\t\t\t\t/* src addr */\n\t\t\t\t\tether_addr_copy(&ctrl->vm_ports[portid].dst->ethaddr,\n\t\t\t\t\t\t\tð->s_addr);\n\t\t\t\t}\n\t\t\t\tqconf->rx_mbufs[portid].len += nb_rx;\n\n\t\t\t}\n\n\t\t}\n\n\t\t/* if timer is enabled */\n\t\tif (timer_period > 0) {\n\n\t\t\t/* advance the timer */\n\t\t\ttimer_tsc += diff_tsc;\n\n\t\t\t/* if timer has reached its timeout */\n\t\t\tif (unlikely(timer_tsc >= (uint64_t) timer_period)) {\n\n\t\t\t\t/* do this only on master core */\n\t\t\t\tif (lcore_id == rte_get_master_lcore()) {\n\t\t\t\t\tprint_stats();\n\t\t\t\t\t/* reset the timer */\n\t\t\t\t\ttimer_tsc = 0;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tprev_tsc = cur_tsc;\n\t}\n}\n\nstatic int\nl2fwd_ivshmem_launch_one_lcore(__attribute__((unused)) void *dummy)\n{\n\tfwd_loop();\n\treturn 0;\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_queue_conf *qconf;\n\tconst struct rte_memzone * mz;\n\tint ret;\n\tuint8_t portid;\n\tunsigned rx_lcore_id, lcore_id;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid EAL arguments\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = l2fwd_ivshmem_parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid l2fwd-ivshmem arguments\\n\");\n\n\t/* find control structure */\n\tmz = rte_memzone_lookup(CTRL_MZ_NAME);\n\tif (mz == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot find control memzone\\n\");\n\n\tctrl = (struct ivshmem_ctrl*) mz->addr;\n\n\t/* lock the ctrl so that we don't have conflicts with anything else */\n\trte_spinlock_lock(&ctrl->lock);\n\n\tif (ctrl->state == STATE_FWD)\n\t\trte_exit(EXIT_FAILURE, \"Forwarding already started!\\n\");\n\n\trx_lcore_id = 0;\n\tqconf = NULL;\n\n\t/* Initialize the port/queue configuration of each logical core */\n\tfor (portid = 0; portid < ctrl->nb_ports; portid++) {\n\n\t\t/* get the lcore_id for this port */\n\t\twhile (rte_lcore_is_enabled(rx_lcore_id) == 0 ||\n\t\t\t lcore_queue_conf[rx_lcore_id].n_rx_port ==\n\t\t\t l2fwd_ivshmem_rx_queue_per_lcore) {\n\t\t\trx_lcore_id++;\n\t\t\tif (rx_lcore_id >= RTE_MAX_LCORE)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Not enough cores\\n\");\n\t\t}\n\n\t\tif (qconf != &lcore_queue_conf[rx_lcore_id])\n\t\t\t/* Assigned a new logical core in the loop above. */\n\t\t\tqconf = &lcore_queue_conf[rx_lcore_id];\n\n\t\tqconf->rx_port_list[qconf->n_rx_port] = portid;\n\t\tqconf->port_param[qconf->n_rx_port] = &ctrl->vm_ports[portid];\n\t\tqconf->n_rx_port++;\n\n\t\tprintf(\"Lcore %u: RX port %u\\n\", rx_lcore_id, (unsigned) portid);\n\t}\n\n\tsigsetup();\n\n\t/* indicate that we are ready to forward */\n\tctrl->state = STATE_FWD;\n\n\t/* unlock */\n\trte_spinlock_unlock(&ctrl->lock);\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(l2fwd_ivshmem_launch_one_lcore, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/l2fwd-ivshmem/host/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-ivshmem-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = host\n\n# all source are stored in SRCS-y\nSRCS-y := host.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/l2fwd-ivshmem/host/host.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"../include/common.h\"\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n/* mask of enabled ports */\nstatic uint32_t l2fwd_ivshmem_enabled_port_mask = 0;\n\nstatic struct ether_addr l2fwd_ivshmem_ports_eth_addr[RTE_MAX_ETHPORTS];\n\n#define NB_MBUF 8192\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT 16\nstruct lcore_queue_conf {\n\tunsigned n_rx_port;\n\tunsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE];\n\tstruct vm_port_param * port_param[MAX_RX_QUEUE_PER_LCORE];\n\tstruct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];\n\tstruct mbuf_table rx_mbufs[RTE_MAX_ETHPORTS];\n} __rte_cache_aligned;\nstatic struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];\n\nstatic const struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\n#define METADATA_NAME \"l2fwd_ivshmem\"\n#define CMDLINE_OPT_FWD_CONF \"fwd-conf\"\n\n#define QEMU_CMD_FMT \"/tmp/ivshmem_qemu_cmdline_%s\"\n\nstruct port_statistics port_statistics[RTE_MAX_ETHPORTS];\n\nstruct rte_mempool * l2fwd_ivshmem_pktmbuf_pool = NULL;\n\n/* Print out statistics on packets dropped */\nstatic void\nprint_stats(void)\n{\n\tuint64_t total_packets_dropped, total_packets_tx, total_packets_rx;\n\tuint64_t total_vm_packets_dropped, total_vm_packets_tx, total_vm_packets_rx;\n\tunsigned portid;\n\n\ttotal_packets_dropped = 0;\n\ttotal_packets_tx = 0;\n\ttotal_packets_rx = 0;\n\ttotal_vm_packets_tx = 0;\n\ttotal_vm_packets_rx = 0;\n\n\tconst char clr[] = { 27, '[', '2', 'J', '\\0' };\n\tconst char topLeft[] = { 27, '[', '1', ';', '1', 'H','\\0' };\n\n\t\t/* Clear screen and move to top left */\n\tprintf(\"%s%s\", clr, topLeft);\n\n\tprintf(\"\\nPort statistics ====================================\");\n\n\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t/* skip disabled ports */\n\t\tif ((l2fwd_ivshmem_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\t\tprintf(\"\\nStatistics for port %u ------------------------------\"\n\t\t\t \"\\nPackets sent: %24\"PRIu64\n\t\t\t \"\\nPackets received: %20\"PRIu64\n\t\t\t \"\\nPackets dropped: %21\"PRIu64,\n\t\t\t portid,\n\t\t\t port_statistics[portid].tx,\n\t\t\t port_statistics[portid].rx,\n\t\t\t port_statistics[portid].dropped);\n\n\t\ttotal_packets_dropped += port_statistics[portid].dropped;\n\t\ttotal_packets_tx += port_statistics[portid].tx;\n\t\ttotal_packets_rx += port_statistics[portid].rx;\n\t}\n\n\tprintf(\"\\nVM statistics ======================================\");\n\tfor (portid = 0; portid < ctrl->nb_ports; portid++) {\n\t\tprintf(\"\\nStatistics for port %u ------------------------------\"\n\t\t\t \"\\nPackets sent: %24\"PRIu64\n\t\t\t \"\\nPackets received: %20\"PRIu64,\n\t\t\t portid,\n\t\t\t ctrl->vm_ports[portid].stats.tx,\n\t\t\t ctrl->vm_ports[portid].stats.rx);\n\n\t\ttotal_vm_packets_dropped += ctrl->vm_ports[portid].stats.dropped;\n\t\ttotal_vm_packets_tx += ctrl->vm_ports[portid].stats.tx;\n\t\ttotal_vm_packets_rx += ctrl->vm_ports[portid].stats.rx;\n\t}\n\tprintf(\"\\nAggregate statistics ===============================\"\n\t\t\t \"\\nTotal packets sent: %18\"PRIu64\n\t\t\t \"\\nTotal packets received: %14\"PRIu64\n\t\t\t \"\\nTotal packets dropped: %15\"PRIu64\n\t\t\t \"\\nTotal VM packets sent: %15\"PRIu64\n\t\t\t \"\\nTotal VM packets received: %11\"PRIu64,\n\t\t\t total_packets_tx,\n\t\t\t total_packets_rx,\n\t\t\t total_packets_dropped,\n\t\t\t total_vm_packets_tx,\n\t\t\t total_vm_packets_rx);\n\tprintf(\"\\n====================================================\\n\");\n}\n\nstatic int\nprint_to_file(const char *cmdline, const char *config_name)\n{\n\tFILE *file;\n\tchar path[PATH_MAX];\n\n\tsnprintf(path, sizeof(path), QEMU_CMD_FMT, config_name);\n\tfile = fopen(path, \"w\");\n\tif (file == NULL) {\n\t\tRTE_LOG(ERR, L2FWD_IVSHMEM, \"Could not open '%s' \\n\", path);\n\t\treturn -1;\n\t}\n\n\tRTE_LOG(DEBUG, L2FWD_IVSHMEM, \"QEMU command line for config '%s': %s \\n\",\n\t\t\tconfig_name, cmdline);\n\n\tfprintf(file, \"%s\\n\", cmdline);\n\tfclose(file);\n\treturn 0;\n}\n\nstatic int\ngenerate_ivshmem_cmdline(const char *config_name)\n{\n\tchar cmdline[PATH_MAX];\n\tif (rte_ivshmem_metadata_cmdline_generate(cmdline, sizeof(cmdline),\n\t\t\tconfig_name) < 0)\n\t\treturn -1;\n\n\tif (print_to_file(cmdline, config_name) < 0)\n\t\treturn -1;\n\n\trte_ivshmem_metadata_dump(stdout, config_name);\n\treturn 0;\n}\n\n/* display usage */\nstatic void\nl2fwd_ivshmem_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK [-q NQ -T PERIOD]\\n\"\n\t\t \" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t\t \" -q NQ: number of queue (=ports) per lcore (default is 1)\\n\"\n\t\t \" -T PERIOD: statistics will be refreshed each PERIOD seconds \"\n\t\t \"(0 to disable, 10 default, 86400 maximum)\\n\",\n\t prgname);\n}\n\nstatic unsigned int\nl2fwd_ivshmem_parse_nqueue(const char *q_arg)\n{\n\tchar *end = NULL;\n\tunsigned long n;\n\n\t/* parse hexadecimal string */\n\tn = strtoul(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn 0;\n\tif (n == 0)\n\t\treturn 0;\n\tif (n >= MAX_RX_QUEUE_PER_LCORE)\n\t\treturn 0;\n\n\treturn n;\n}\n\nstatic int\nl2fwd_ivshmem_parse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\nstatic int\nl2fwd_ivshmem_parse_timer_period(const char *q_arg)\n{\n\tchar *end = NULL;\n\tint n;\n\n\t/* parse number string */\n\tn = strtol(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\tif (n >= MAX_TIMER_PERIOD)\n\t\treturn -1;\n\n\treturn n;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nl2fwd_ivshmem_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t\t{CMDLINE_OPT_FWD_CONF, 1, 0, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"q:p:T:\",\n\t\t\t\t lgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tl2fwd_ivshmem_enabled_port_mask = l2fwd_ivshmem_parse_portmask(optarg);\n\t\t\tif (l2fwd_ivshmem_enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tl2fwd_ivshmem_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* nqueue */\n\t\tcase 'q':\n\t\t\tl2fwd_ivshmem_rx_queue_per_lcore = l2fwd_ivshmem_parse_nqueue(optarg);\n\t\t\tif (l2fwd_ivshmem_rx_queue_per_lcore == 0) {\n\t\t\t\tprintf(\"invalid queue number\\n\");\n\t\t\t\tl2fwd_ivshmem_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* timer period */\n\t\tcase 'T':\n\t\t\ttimer_period = l2fwd_ivshmem_parse_timer_period(optarg) * 1000 * TIMER_MILLISECOND;\n\t\t\tif (timer_period < 0) {\n\t\t\t\tprintf(\"invalid timer period\\n\");\n\t\t\t\tl2fwd_ivshmem_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tl2fwd_ivshmem_usage(prgname);\n\t\t\treturn -1;\n\n\t\tdefault:\n\t\t\tl2fwd_ivshmem_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\n/* Send the burst of packets on an output interface */\nstatic int\nl2fwd_ivshmem_send_burst(struct lcore_queue_conf *qconf, unsigned n, uint8_t port)\n{\n\tstruct rte_mbuf **m_table;\n\tunsigned ret;\n\tunsigned queueid =0;\n\n\tm_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;\n\n\tret = rte_eth_tx_burst(port, (uint16_t) queueid, m_table, (uint16_t) n);\n\tport_statistics[port].tx += ret;\n\tif (unlikely(ret < n)) {\n\t\tport_statistics[port].dropped += (n - ret);\n\t\tdo {\n\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t} while (++ret < n);\n\t}\n\n\treturn 0;\n}\n\n/* Enqueue packets for TX and prepare them to be sent on the network */\nstatic int\nl2fwd_ivshmem_send_packet(struct rte_mbuf *m, uint8_t port)\n{\n\tunsigned lcore_id, len;\n\tstruct lcore_queue_conf *qconf;\n\n\tlcore_id = rte_lcore_id();\n\n\tqconf = &lcore_queue_conf[lcore_id];\n\tlen = qconf->tx_mbufs[port].len;\n\tqconf->tx_mbufs[port].m_table[len] = m;\n\tlen++;\n\n\t/* enough pkts to be sent */\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tl2fwd_ivshmem_send_burst(qconf, MAX_PKT_BURST, port);\n\t\tlen = 0;\n\t}\n\n\tqconf->tx_mbufs[port].len = len;\n\treturn 0;\n}\n\nstatic int\nl2fwd_ivshmem_receive_burst(struct lcore_queue_conf *qconf, unsigned portid,\n\t\tunsigned vm_port)\n{\n\tstruct rte_mbuf ** m;\n\tstruct rte_ring * rx;\n\tunsigned len, pkt_idx;\n\n\tm = qconf->rx_mbufs[portid].m_table;\n\tlen = qconf->rx_mbufs[portid].len;\n\trx = qconf->port_param[vm_port]->rx_ring;\n\n\t/* if enqueueing failed, ring is probably full, so drop the packets */\n\tif (rte_ring_enqueue_bulk(rx, (void**) m, len) < 0) {\n\t\tport_statistics[portid].dropped += len;\n\n\t\tpkt_idx = 0;\n\t\tdo {\n\t\t\trte_pktmbuf_free(m[pkt_idx]);\n\t\t} while (++pkt_idx < len);\n\t}\n\telse\n\t\t/* increment rx stats by however many packets we managed to receive */\n\t\tport_statistics[portid].rx += len;\n\n\treturn 0;\n}\n\n/* Enqueue packets for RX and prepare them to be sent to VM */\nstatic int\nl2fwd_ivshmem_receive_packets(struct rte_mbuf ** m, unsigned n, unsigned portid,\n\t\tunsigned vm_port)\n{\n\tunsigned lcore_id, len, pkt_idx;\n\tstruct lcore_queue_conf *qconf;\n\n\tlcore_id = rte_lcore_id();\n\n\tqconf = &lcore_queue_conf[lcore_id];\n\n\tlen = qconf->rx_mbufs[portid].len;\n\tpkt_idx = 0;\n\n\t/* enqueue packets */\n\twhile (pkt_idx < n && len < MAX_PKT_BURST * 2) {\n\t\tqconf->rx_mbufs[portid].m_table[len++] = m[pkt_idx++];\n\t}\n\n\t/* increment queue len by however many packets we managed to receive */\n\tqconf->rx_mbufs[portid].len += pkt_idx;\n\n\t/* drop the unreceived packets */\n\tif (unlikely(pkt_idx < n)) {\n\t\tport_statistics[portid].dropped += n - pkt_idx;\n\t\tdo {\n\t\t\trte_pktmbuf_free(m[pkt_idx]);\n\t\t} while (++pkt_idx < n);\n\t}\n\n\t/* drain the queue halfway through the maximum capacity */\n\tif (unlikely(qconf->rx_mbufs[portid].len >= MAX_PKT_BURST))\n\t\tl2fwd_ivshmem_receive_burst(qconf, portid, vm_port);\n\n\treturn 0;\n}\n\n/* loop for host forwarding mode.\n * the data flow is as follows:\n * 1) get packets from TX queue and send it out from a given port\n * 2) RX packets from given port and enqueue them on RX ring\n * 3) dequeue packets from TX ring and put them on TX queue for a given port\n */\nstatic void\nfwd_loop(void)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST * 2];\n\tstruct rte_mbuf *m;\n\tunsigned lcore_id;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc, timer_tsc;\n\tunsigned i, j, portid, nb_rx;\n\tstruct lcore_queue_conf *qconf;\n\tstruct rte_ring *tx;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\tprev_tsc = 0;\n\ttimer_tsc = 0;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_queue_conf[lcore_id];\n\n\tif (qconf->n_rx_port == 0) {\n\t\tRTE_LOG(INFO, L2FWD_IVSHMEM, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn;\n\t}\n\n\tRTE_LOG(INFO, L2FWD_IVSHMEM, \"entering main loop on lcore %u\\n\", lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\n\t\tportid = qconf->rx_port_list[i];\n\t\tRTE_LOG(INFO, L2FWD_IVSHMEM, \" -- lcoreid=%u portid=%u\\n\", lcore_id,\n\t\t\tportid);\n\t}\n\n\twhile (ctrl->state == STATE_FWD) {\n\n\t\tcur_tsc = rte_rdtsc();\n\n\t\t/*\n\t\t * Burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\t/*\n\t\t\t * TX\n\t\t\t */\n\t\t\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t\t\tif (qconf->tx_mbufs[portid].len == 0)\n\t\t\t\t\tcontinue;\n\t\t\t\tl2fwd_ivshmem_send_burst(qconf,\n\t\t\t\t\t\t qconf->tx_mbufs[portid].len,\n\t\t\t\t\t\t (uint8_t) portid);\n\t\t\t\tqconf->tx_mbufs[portid].len = 0;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * RX\n\t\t\t */\n\t\t\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\t\t\t\tportid = qconf->rx_port_list[i];\n\t\t\t\tif (qconf->rx_mbufs[portid].len == 0)\n\t\t\t\t\tcontinue;\n\t\t\t\tl2fwd_ivshmem_receive_burst(qconf, portid, i);\n\t\t\t\tqconf->rx_mbufs[portid].len = 0;\n\t\t\t}\n\n\t\t\t/* if timer is enabled */\n\t\t\tif (timer_period > 0) {\n\n\t\t\t\t/* advance the timer */\n\t\t\t\ttimer_tsc += diff_tsc;\n\n\t\t\t\t/* if timer has reached its timeout */\n\t\t\t\tif (unlikely(timer_tsc >= (uint64_t) timer_period)) {\n\n\t\t\t\t\t/* do this only on master core */\n\t\t\t\t\tif (lcore_id == rte_get_master_lcore()) {\n\t\t\t\t\t\tprint_stats();\n\t\t\t\t\t\t/* reset the timer */\n\t\t\t\t\t\ttimer_tsc = 0;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tprev_tsc = cur_tsc;\n\t\t}\n\n\t\t/*\n\t\t * packet RX and forwarding\n\t\t */\n\t\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\n\t\t\t/* RX packets from port and put them on RX ring */\n\t\t\tportid = qconf->rx_port_list[i];\n\t\t\tnb_rx = rte_eth_rx_burst((uint8_t) portid, 0,\n\t\t\t\t\t\t pkts_burst, MAX_PKT_BURST);\n\n\t\t\tif (nb_rx != 0)\n\t\t\t\tl2fwd_ivshmem_receive_packets(pkts_burst, nb_rx, portid, i);\n\n\t\t\t/* dequeue packets from TX ring and send them to TX queue */\n\t\t\ttx = qconf->port_param[i]->tx_ring;\n\n\t\t\tnb_rx = rte_ring_count(tx);\n\n\t\t\tnb_rx = RTE_MIN(nb_rx, (unsigned) MAX_PKT_BURST);\n\n\t\t\tif (nb_rx == 0)\n\t\t\t\tcontinue;\n\n\t\t\t/* should not happen */\n\t\t\tif (unlikely(rte_ring_dequeue_bulk(tx, (void**) pkts_burst, nb_rx) < 0)) {\n\t\t\t\tctrl->state = STATE_FAIL;\n\t\t\t\treturn;\n\t\t\t}\n\n\t\t\tfor (j = 0; j < nb_rx; j++) {\n\t\t\t\tm = pkts_burst[j];\n\t\t\t\tl2fwd_ivshmem_send_packet(m, portid);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic int\nl2fwd_ivshmem_launch_one_lcore(__attribute__((unused)) void *dummy)\n{\n\tfwd_loop();\n\treturn 0;\n}\n\nint main(int argc, char **argv)\n{\n\tchar name[RTE_RING_NAMESIZE];\n\tstruct rte_ring *r;\n\tstruct lcore_queue_conf *qconf;\n\tstruct rte_eth_dev_info dev_info;\n\tuint8_t portid, port_nr;\n\tuint8_t nb_ports, nb_ports_available;\n\tuint8_t nb_ports_in_mask;\n\tint ret;\n\tunsigned lcore_id, rx_lcore_id;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid EAL arguments\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = l2fwd_ivshmem_parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid l2fwd-ivshmem arguments\\n\");\n\n\t/* create a shared mbuf pool */\n\tl2fwd_ivshmem_pktmbuf_pool =\n\t\trte_pktmbuf_pool_create(MBUF_MP_NAME, NB_MBUF, 32,\n\t\t\t0, RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\tif (l2fwd_ivshmem_pktmbuf_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot init mbuf pool\\n\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports == 0)\n\t\trte_exit(EXIT_FAILURE, \"No Ethernet ports - bye\\n\");\n\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\t/*\n\t * reserve memzone to communicate with VMs - we cannot use rte_malloc here\n\t * because while it is technically possible, it is a very bad idea to share\n\t * the heap between two primary processes.\n\t */\n\tctrl_mz = rte_memzone_reserve(CTRL_MZ_NAME, sizeof(struct ivshmem_ctrl),\n\t\t\tSOCKET_ID_ANY, 0);\n\tif (ctrl_mz == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot reserve control memzone\\n\");\n\tctrl = (struct ivshmem_ctrl*) ctrl_mz->addr;\n\n\tmemset(ctrl, 0, sizeof(struct ivshmem_ctrl));\n\n\t/*\n\t * Each port is assigned an output port.\n\t */\n\tnb_ports_in_mask = 0;\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_ivshmem_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\t\tif (portid % 2) {\n\t\t\tctrl->vm_ports[nb_ports_in_mask].dst = &ctrl->vm_ports[nb_ports_in_mask-1];\n\t\t\tctrl->vm_ports[nb_ports_in_mask-1].dst = &ctrl->vm_ports[nb_ports_in_mask];\n\t\t}\n\n\t\tnb_ports_in_mask++;\n\n\t\trte_eth_dev_info_get(portid, &dev_info);\n\t}\n\tif (nb_ports_in_mask % 2) {\n\t\tprintf(\"Notice: odd number of ports in portmask.\\n\");\n\t\tctrl->vm_ports[nb_ports_in_mask-1].dst =\n\t\t\t\t&ctrl->vm_ports[nb_ports_in_mask-1];\n\t}\n\n\trx_lcore_id = 0;\n\tqconf = NULL;\n\n\tprintf(\"Initializing ports configuration...\\n\");\n\n\tnb_ports_available = nb_ports;\n\n\t/* Initialise each port */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_ivshmem_enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"Skipping disabled port %u\\n\", (unsigned) portid);\n\t\t\tnb_ports_available--;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* init port */\n\t\tprintf(\"Initializing port %u... \", (unsigned) portid);\n\t\tfflush(stdout);\n\t\tret = rte_eth_dev_configure(portid, 1, 1, &port_conf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot configure device: err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\trte_eth_macaddr_get(portid,&l2fwd_ivshmem_ports_eth_addr[portid]);\n\n\t\t/* init one RX queue */\n\t\tfflush(stdout);\n\t\tret = rte_eth_rx_queue_setup(portid, 0, nb_rxd,\n\t\t\t\t\t\t rte_eth_dev_socket_id(portid),\n\t\t\t\t\t\t NULL,\n\t\t\t\t\t\t l2fwd_ivshmem_pktmbuf_pool);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup:err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\t/* init one TX queue on each port */\n\t\tfflush(stdout);\n\t\tret = rte_eth_tx_queue_setup(portid, 0, nb_txd,\n\t\t\t\trte_eth_dev_socket_id(portid),\n\t\t\t\tNULL);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup:err=%d, port=%u\\n\",\n\t\t\t\tret, (unsigned) portid);\n\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_dev_start:err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\tprintf(\"done: \\n\");\n\n\t\trte_eth_promiscuous_enable(portid);\n\n\t\tprintf(\"Port %u, MAC address: %02X:%02X:%02X:%02X:%02X:%02X\\n\\n\",\n\t\t\t\t(unsigned) portid,\n\t\t\t\tl2fwd_ivshmem_ports_eth_addr[portid].addr_bytes[0],\n\t\t\t\tl2fwd_ivshmem_ports_eth_addr[portid].addr_bytes[1],\n\t\t\t\tl2fwd_ivshmem_ports_eth_addr[portid].addr_bytes[2],\n\t\t\t\tl2fwd_ivshmem_ports_eth_addr[portid].addr_bytes[3],\n\t\t\t\tl2fwd_ivshmem_ports_eth_addr[portid].addr_bytes[4],\n\t\t\t\tl2fwd_ivshmem_ports_eth_addr[portid].addr_bytes[5]);\n\n\t\t/* initialize port stats */\n\t\tmemset(&port_statistics, 0, sizeof(port_statistics));\n\t}\n\n\tif (!nb_ports_available) {\n\t\trte_exit(EXIT_FAILURE,\n\t\t\t\"All available ports are disabled. Please set portmask.\\n\");\n\t}\n\tport_nr = 0;\n\n\t/* Initialize the port/queue configuration of each logical core */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tif ((l2fwd_ivshmem_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\n\t\t/* get the lcore_id for this port */\n\t\twhile (rte_lcore_is_enabled(rx_lcore_id) == 0 ||\n\t\t\t lcore_queue_conf[rx_lcore_id].n_rx_port ==\n\t\t\t\t\t l2fwd_ivshmem_rx_queue_per_lcore) {\n\t\t\trx_lcore_id++;\n\t\t\tif (rx_lcore_id >= RTE_MAX_LCORE)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Not enough cores\\n\");\n\t\t}\n\n\t\tif (qconf != &lcore_queue_conf[rx_lcore_id])\n\t\t\t/* Assigned a new logical core in the loop above. */\n\t\t\tqconf = &lcore_queue_conf[rx_lcore_id];\n\n\n\t\trte_eth_macaddr_get(portid, &ctrl->vm_ports[port_nr].ethaddr);\n\n\t\tqconf->rx_port_list[qconf->n_rx_port] = portid;\n\t\tqconf->port_param[qconf->n_rx_port] = &ctrl->vm_ports[port_nr];\n\t\tqconf->n_rx_port++;\n\t\tport_nr++;\n\t\tprintf(\"Lcore %u: RX port %u\\n\", rx_lcore_id, (unsigned) portid);\n\t}\n\n\tcheck_all_ports_link_status(nb_ports_available, l2fwd_ivshmem_enabled_port_mask);\n\n\t/* create rings for each VM port (several ports can be on the same VM).\n\t * note that we store the pointers in ctrl - that way, they are the same\n\t * and valid across all VMs because ctrl is also in DPDK memory */\n\tfor (portid = 0; portid < nb_ports_available; portid++) {\n\n\t\t/* RX ring. SP/SC because it's only used by host and a single VM */\n\t\tsnprintf(name, sizeof(name), \"%s%i\", RX_RING_PREFIX, portid);\n\t\tr = rte_ring_create(name, NB_MBUF,\n\t\t\t\tSOCKET_ID_ANY, RING_F_SP_ENQ | RING_F_SC_DEQ);\n\t\tif (r == NULL)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot create ring %s\\n\", name);\n\n\t\tctrl->vm_ports[portid].rx_ring = r;\n\n\t\t/* TX ring. SP/SC because it's only used by host and a single VM */\n\t\tsnprintf(name, sizeof(name), \"%s%i\", TX_RING_PREFIX, portid);\n\t\tr = rte_ring_create(name, NB_MBUF,\n\t\t\t\tSOCKET_ID_ANY, RING_F_SP_ENQ | RING_F_SC_DEQ);\n\t\tif (r == NULL)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot create ring %s\\n\", name);\n\n\t\tctrl->vm_ports[portid].tx_ring = r;\n\t}\n\n\t/* create metadata, output cmdline */\n\tif (rte_ivshmem_metadata_create(METADATA_NAME) < 0)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create IVSHMEM metadata\\n\");\n\n\tif (rte_ivshmem_metadata_add_memzone(ctrl_mz, METADATA_NAME))\n\t\trte_exit(EXIT_FAILURE, \"Cannot add memzone to IVSHMEM metadata\\n\");\n\n\tif (rte_ivshmem_metadata_add_mempool(l2fwd_ivshmem_pktmbuf_pool, METADATA_NAME))\n\t\trte_exit(EXIT_FAILURE, \"Cannot add mbuf mempool to IVSHMEM metadata\\n\");\n\n\tfor (portid = 0; portid < nb_ports_available; portid++) {\n\t\tif (rte_ivshmem_metadata_add_ring(ctrl->vm_ports[portid].rx_ring,\n\t\t\t\tMETADATA_NAME) < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot add ring %s to IVSHMEM metadata\\n\",\n\t\t\t\t\tctrl->vm_ports[portid].rx_ring->name);\n\t\tif (rte_ivshmem_metadata_add_ring(ctrl->vm_ports[portid].tx_ring,\n\t\t\t\tMETADATA_NAME) < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot add ring %s to IVSHMEM metadata\\n\",\n\t\t\t\t\tctrl->vm_ports[portid].tx_ring->name);\n\t}\n\tgenerate_ivshmem_cmdline(METADATA_NAME);\n\n\tctrl->nb_ports = nb_ports_available;\n\n\tprintf(\"Waiting for VM to initialize...\\n\");\n\n\t/* wait for VM to initialize */\n\twhile (ctrl->state != STATE_FWD) {\n\t\tif (ctrl->state == STATE_FAIL)\n\t\t\trte_exit(EXIT_FAILURE, \"VM reported failure\\n\");\n\n\t\tsleep(1);\n\t}\n\n\tprintf(\"Done!\\n\");\n\n\tsigsetup();\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(l2fwd_ivshmem_launch_one_lcore, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\tif (ctrl->state == STATE_FAIL)\n\t\trte_exit(EXIT_FAILURE, \"VM reported failure\\n\");\n\n\treturn 0;\n}\n" }, { "path": "examples/l2fwd-ivshmem/include/common.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _IVSHMEM_COMMON_H_\n#define _IVSHMEM_COMMON_H_\n\n#define RTE_LOGTYPE_L2FWD_IVSHMEM RTE_LOGTYPE_USER1\n\n#define CTRL_MZ_NAME \"CTRL_MEMZONE\"\n#define MBUF_MP_NAME \"MBUF_MEMPOOL\"\n#define RX_RING_PREFIX \"RX_\"\n#define TX_RING_PREFIX \"TX_\"\n\n/* A tsc-based timer responsible for triggering statistics printout */\n#define TIMER_MILLISECOND 2000000ULL /* around 1ms at 2 Ghz */\n#define MAX_TIMER_PERIOD 86400 /* 1 day max */\nstatic int64_t timer_period = 10 * TIMER_MILLISECOND * 1000; /* default period is 10 seconds */\n\n#define DIM(x)\\\n\t(sizeof(x)/sizeof(x)[0])\n\n#define MAX_PKT_BURST 32\n\nconst struct rte_memzone * ctrl_mz;\n\nenum l2fwd_state {\n\tSTATE_NONE = 0,\n\tSTATE_FWD,\n\tSTATE_EXIT,\n\tSTATE_FAIL\n};\n\n/* Per-port statistics struct */\nstruct port_statistics {\n\tuint64_t tx;\n\tuint64_t rx;\n\tuint64_t dropped;\n} __rte_cache_aligned;\n\nstruct mbuf_table {\n\tunsigned len;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST * 2]; /**< allow up to two bursts */\n};\n\nstruct vm_port_param {\n\tstruct rte_ring * rx_ring; /**< receiving ring for current port */\n\tstruct rte_ring * tx_ring; /**< transmitting ring for current port */\n\tstruct vm_port_param * dst; /**< current port's destination port */\n\tvolatile struct port_statistics stats; /**< statistics for current port */\n\tstruct ether_addr ethaddr; /**< Ethernet address of the port */\n};\n\n/* control structure, to synchronize host and VM */\nstruct ivshmem_ctrl {\n\trte_spinlock_t lock;\n\tuint8_t nb_ports; /**< total nr of ports */\n\tvolatile enum l2fwd_state state; /**< report state */\n\tstruct vm_port_param vm_ports[RTE_MAX_ETHPORTS];\n};\n\nstruct ivshmem_ctrl * ctrl;\n\nstatic unsigned int l2fwd_ivshmem_rx_queue_per_lcore = 1;\n\nstatic void sighandler(int __rte_unused s)\n{\n\tctrl->state = STATE_EXIT;\n}\n\nstatic void sigsetup(void)\n{\n\t struct sigaction sigIntHandler;\n\n\t sigIntHandler.sa_handler = sighandler;\n\t sigemptyset(&sigIntHandler.sa_mask);\n\t sigIntHandler.sa_flags = 0;\n\n\t sigaction(SIGINT, &sigIntHandler, NULL);\n}\n\n#endif /* _IVSHMEM_COMMON_H_ */\n" }, { "path": "examples/l2fwd-jobstats/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overridden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = l2fwd-jobstats\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/l2fwd-jobstats/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#define RTE_LOGTYPE_L2FWD RTE_LOGTYPE_USER1\n\n#define NB_MBUF 8192\n\n#define MAX_PKT_BURST 32\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n/* ethernet addresses of ports */\nstatic struct ether_addr l2fwd_ports_eth_addr[RTE_MAX_ETHPORTS];\n\n/* mask of enabled ports */\nstatic uint32_t l2fwd_enabled_port_mask;\n\n/* list of enabled ports */\nstatic uint32_t l2fwd_dst_ports[RTE_MAX_ETHPORTS];\n\n#define UPDATE_STEP_UP 1\n#define UPDATE_STEP_DOWN 32\n\nstatic unsigned int l2fwd_rx_queue_per_lcore = 1;\n\nstruct mbuf_table {\n\tuint64_t next_flush_time;\n\tunsigned len;\n\tstruct rte_mbuf *mbufs[MAX_PKT_BURST];\n};\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT 16\nstruct lcore_queue_conf {\n\tunsigned n_rx_port;\n\tunsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE];\n\tstruct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];\n\n\tstruct rte_timer rx_timers[MAX_RX_QUEUE_PER_LCORE];\n\tstruct rte_jobstats port_fwd_jobs[MAX_RX_QUEUE_PER_LCORE];\n\n\tstruct rte_timer flush_timer;\n\tstruct rte_jobstats flush_job;\n\tstruct rte_jobstats idle_job;\n\tstruct rte_jobstats_context jobs_context;\n\n\trte_atomic16_t stats_read_pending;\n\trte_spinlock_t lock;\n} __rte_cache_aligned;\nstruct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];\n\nstatic const struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\nstruct rte_mempool *l2fwd_pktmbuf_pool = NULL;\n\n/* Per-port statistics struct */\nstruct l2fwd_port_statistics {\n\tuint64_t tx;\n\tuint64_t rx;\n\tuint64_t dropped;\n} __rte_cache_aligned;\nstruct l2fwd_port_statistics port_statistics[RTE_MAX_ETHPORTS];\n\n/* 1 day max */\n#define MAX_TIMER_PERIOD 86400\n/* default period is 10 seconds */\nstatic int64_t timer_period = 10;\n/* default timer frequency */\nstatic double hz;\n/* BURST_TX_DRAIN_US converted to cycles */\nuint64_t drain_tsc;\n/* Convert cycles to ns */\nstatic inline double\ncycles_to_ns(uint64_t cycles)\n{\n\tdouble t = cycles;\n\n\tt *= (double)NS_PER_S;\n\tt /= hz;\n\treturn t;\n}\n\nstatic void\nshow_lcore_stats(unsigned lcore_id)\n{\n\tstruct lcore_queue_conf *qconf = &lcore_queue_conf[lcore_id];\n\tstruct rte_jobstats_context *ctx = &qconf->jobs_context;\n\tstruct rte_jobstats *job;\n\tuint8_t i;\n\n\t/* LCore statistics. */\n\tuint64_t stats_period, loop_count;\n\tuint64_t exec, exec_min, exec_max;\n\tuint64_t management, management_min, management_max;\n\tuint64_t busy, busy_min, busy_max;\n\n\t/* Jobs statistics. */\n\tconst uint8_t port_cnt = qconf->n_rx_port;\n\tuint64_t jobs_exec_cnt[port_cnt], jobs_period[port_cnt];\n\tuint64_t jobs_exec[port_cnt], jobs_exec_min[port_cnt],\n\t\t\t\tjobs_exec_max[port_cnt];\n\n\tuint64_t flush_exec_cnt, flush_period;\n\tuint64_t flush_exec, flush_exec_min, flush_exec_max;\n\n\tuint64_t idle_exec_cnt;\n\tuint64_t idle_exec, idle_exec_min, idle_exec_max;\n\tuint64_t collection_time = rte_get_timer_cycles();\n\n\t/* Ask forwarding thread to give us stats. */\n\trte_atomic16_set(&qconf->stats_read_pending, 1);\n\trte_spinlock_lock(&qconf->lock);\n\trte_atomic16_set(&qconf->stats_read_pending, 0);\n\n\t/* Collect context statistics. */\n\tstats_period = ctx->state_time - ctx->start_time;\n\tloop_count = ctx->loop_cnt;\n\n\texec = ctx->exec_time;\n\texec_min = ctx->min_exec_time;\n\texec_max = ctx->max_exec_time;\n\n\tmanagement = ctx->management_time;\n\tmanagement_min = ctx->min_management_time;\n\tmanagement_max = ctx->max_management_time;\n\n\trte_jobstats_context_reset(ctx);\n\n\tfor (i = 0; i < port_cnt; i++) {\n\t\tjob = &qconf->port_fwd_jobs[i];\n\n\t\tjobs_exec_cnt[i] = job->exec_cnt;\n\t\tjobs_period[i] = job->period;\n\n\t\tjobs_exec[i] = job->exec_time;\n\t\tjobs_exec_min[i] = job->min_exec_time;\n\t\tjobs_exec_max[i] = job->max_exec_time;\n\n\t\trte_jobstats_reset(job);\n\t}\n\n\tflush_exec_cnt = qconf->flush_job.exec_cnt;\n\tflush_period = qconf->flush_job.period;\n\tflush_exec = qconf->flush_job.exec_time;\n\tflush_exec_min = qconf->flush_job.min_exec_time;\n\tflush_exec_max = qconf->flush_job.max_exec_time;\n\trte_jobstats_reset(&qconf->flush_job);\n\n\tidle_exec_cnt = qconf->idle_job.exec_cnt;\n\tidle_exec = qconf->idle_job.exec_time;\n\tidle_exec_min = qconf->idle_job.min_exec_time;\n\tidle_exec_max = qconf->idle_job.max_exec_time;\n\trte_jobstats_reset(&qconf->idle_job);\n\n\trte_spinlock_unlock(&qconf->lock);\n\n\texec -= idle_exec;\n\tbusy = exec + management;\n\tbusy_min = exec_min + management_min;\n\tbusy_max = exec_max + management_max;\n\n\n\tcollection_time = rte_get_timer_cycles() - collection_time;\n\n#define STAT_FMT \"\\n%-18s %'14.0f %6.1f%% %'10.0f %'10.0f %'10.0f\"\n\n\tprintf(\"\\n----------------\"\n\t\t\t\"\\nLCore %3u: statistics (time in ns, collected in %'9.0f)\"\n\t\t\t\"\\n%-18s %14s %7s %10s %10s %10s \"\n\t\t\t\"\\n%-18s %'14.0f\"\n\t\t\t\"\\n%-18s %'14\" PRIu64\n\t\t\tSTAT_FMT /* Exec */\n\t\t\tSTAT_FMT /* Management */\n\t\t\tSTAT_FMT /* Busy */\n\t\t\tSTAT_FMT, /* Idle */\n\t\t\tlcore_id, cycles_to_ns(collection_time),\n\t\t\t\"Stat type\", \"total\", \"%total\", \"avg\", \"min\", \"max\",\n\t\t\t\"Stats duration:\", cycles_to_ns(stats_period),\n\t\t\t\"Loop count:\", loop_count,\n\t\t\t\"Exec time\",\n\t\t\tcycles_to_ns(exec), exec * 100.0 / stats_period,\n\t\t\tcycles_to_ns(loop_count ? exec / loop_count : 0),\n\t\t\tcycles_to_ns(exec_min),\n\t\t\tcycles_to_ns(exec_max),\n\t\t\t\"Management time\",\n\t\t\tcycles_to_ns(management), management * 100.0 / stats_period,\n\t\t\tcycles_to_ns(loop_count ? management / loop_count : 0),\n\t\t\tcycles_to_ns(management_min),\n\t\t\tcycles_to_ns(management_max),\n\t\t\t\"Exec + management\",\n\t\t\tcycles_to_ns(busy), busy * 100.0 / stats_period,\n\t\t\tcycles_to_ns(loop_count ? busy / loop_count : 0),\n\t\t\tcycles_to_ns(busy_min),\n\t\t\tcycles_to_ns(busy_max),\n\t\t\t\"Idle (job)\",\n\t\t\tcycles_to_ns(idle_exec), idle_exec * 100.0 / stats_period,\n\t\t\tcycles_to_ns(idle_exec_cnt ? idle_exec / idle_exec_cnt : 0),\n\t\t\tcycles_to_ns(idle_exec_min),\n\t\t\tcycles_to_ns(idle_exec_max));\n\n\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\t\tjob = &qconf->port_fwd_jobs[i];\n\t\tprintf(\"\\n\\nJob %\" PRIu32 \": %-20s \"\n\t\t\t\t\"\\n%-18s %'14\" PRIu64\n\t\t\t\t\"\\n%-18s %'14.0f\"\n\t\t\t\tSTAT_FMT,\n\t\t\t\ti, job->name,\n\t\t\t\t\"Exec count:\", jobs_exec_cnt[i],\n\t\t\t\t\"Exec period: \", cycles_to_ns(jobs_period[i]),\n\t\t\t\t\"Exec time\",\n\t\t\t\tcycles_to_ns(jobs_exec[i]), jobs_exec[i] * 100.0 / stats_period,\n\t\t\t\tcycles_to_ns(jobs_exec_cnt[i] ? jobs_exec[i] / jobs_exec_cnt[i]\n\t\t\t\t\t\t: 0),\n\t\t\t\tcycles_to_ns(jobs_exec_min[i]),\n\t\t\t\tcycles_to_ns(jobs_exec_max[i]));\n\t}\n\n\tif (qconf->n_rx_port > 0) {\n\t\tjob = &qconf->flush_job;\n\t\tprintf(\"\\n\\nJob %\" PRIu32 \": %-20s \"\n\t\t\t\t\"\\n%-18s %'14\" PRIu64\n\t\t\t\t\"\\n%-18s %'14.0f\"\n\t\t\t\tSTAT_FMT,\n\t\t\t\ti, job->name,\n\t\t\t\t\"Exec count:\", flush_exec_cnt,\n\t\t\t\t\"Exec period: \", cycles_to_ns(flush_period),\n\t\t\t\t\"Exec time\",\n\t\t\t\tcycles_to_ns(flush_exec), flush_exec * 100.0 / stats_period,\n\t\t\t\tcycles_to_ns(flush_exec_cnt ? flush_exec / flush_exec_cnt : 0),\n\t\t\t\tcycles_to_ns(flush_exec_min),\n\t\t\t\tcycles_to_ns(flush_exec_max));\n\t}\n}\n\n/* Print out statistics on packets dropped */\nstatic void\nshow_stats_cb(__rte_unused void *param)\n{\n\tuint64_t total_packets_dropped, total_packets_tx, total_packets_rx;\n\tunsigned portid, lcore_id;\n\n\ttotal_packets_dropped = 0;\n\ttotal_packets_tx = 0;\n\ttotal_packets_rx = 0;\n\n\tconst char clr[] = { 27, '[', '2', 'J', '\\0' };\n\tconst char topLeft[] = { 27, '[', '1', ';', '1', 'H', '\\0' };\n\n\t/* Clear screen and move to top left */\n\tprintf(\"%s%s\"\n\t\t\t\"\\nPort statistics ===================================\",\n\t\t\tclr, topLeft);\n\n\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t/* skip disabled ports */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\t\tprintf(\"\\nStatistics for port %u ------------------------------\"\n\t\t\t\t\"\\nPackets sent: %24\"PRIu64\n\t\t\t\t\"\\nPackets received: %20\"PRIu64\n\t\t\t\t\"\\nPackets dropped: %21\"PRIu64,\n\t\t\t\tportid,\n\t\t\t\tport_statistics[portid].tx,\n\t\t\t\tport_statistics[portid].rx,\n\t\t\t\tport_statistics[portid].dropped);\n\n\t\ttotal_packets_dropped += port_statistics[portid].dropped;\n\t\ttotal_packets_tx += port_statistics[portid].tx;\n\t\ttotal_packets_rx += port_statistics[portid].rx;\n\t}\n\n\tprintf(\"\\nAggregate statistics ===============================\"\n\t\t\t\"\\nTotal packets sent: %18\"PRIu64\n\t\t\t\"\\nTotal packets received: %14\"PRIu64\n\t\t\t\"\\nTotal packets dropped: %15\"PRIu64\n\t\t\t\"\\n====================================================\",\n\t\t\ttotal_packets_tx,\n\t\t\ttotal_packets_rx,\n\t\t\ttotal_packets_dropped);\n\n\tRTE_LCORE_FOREACH(lcore_id) {\n\t\tif (lcore_queue_conf[lcore_id].n_rx_port > 0)\n\t\t\tshow_lcore_stats(lcore_id);\n\t}\n\n\tprintf(\"\\n====================================================\\n\");\n\trte_eal_alarm_set(timer_period * US_PER_S, show_stats_cb, NULL);\n}\n\n/* Send the burst of packets on an output interface */\nstatic void\nl2fwd_send_burst(struct lcore_queue_conf *qconf, uint8_t port)\n{\n\tstruct mbuf_table *m_table;\n\tuint16_t ret;\n\tuint16_t queueid = 0;\n\tuint16_t n;\n\n\tm_table = &qconf->tx_mbufs[port];\n\tn = m_table->len;\n\n\tm_table->next_flush_time = rte_get_timer_cycles() + drain_tsc;\n\tm_table->len = 0;\n\n\tret = rte_eth_tx_burst(port, queueid, m_table->mbufs, n);\n\n\tport_statistics[port].tx += ret;\n\tif (unlikely(ret < n)) {\n\t\tport_statistics[port].dropped += (n - ret);\n\t\tdo {\n\t\t\trte_pktmbuf_free(m_table->mbufs[ret]);\n\t\t} while (++ret < n);\n\t}\n}\n\n/* Enqueue packets for TX and prepare them to be sent */\nstatic int\nl2fwd_send_packet(struct rte_mbuf *m, uint8_t port)\n{\n\tconst unsigned lcore_id = rte_lcore_id();\n\tstruct lcore_queue_conf *qconf = &lcore_queue_conf[lcore_id];\n\tstruct mbuf_table *m_table = &qconf->tx_mbufs[port];\n\tuint16_t len = qconf->tx_mbufs[port].len;\n\n\tm_table->mbufs[len] = m;\n\n\tlen++;\n\tm_table->len = len;\n\n\t/* Enough pkts to be sent. */\n\tif (unlikely(len == MAX_PKT_BURST))\n\t\tl2fwd_send_burst(qconf, port);\n\n\treturn 0;\n}\n\nstatic void\nl2fwd_simple_forward(struct rte_mbuf *m, unsigned portid)\n{\n\tstruct ether_hdr *eth;\n\tvoid *tmp;\n\tunsigned dst_port;\n\n\tdst_port = l2fwd_dst_ports[portid];\n\teth = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\t/* 02:00:00:00:00:xx */\n\ttmp = ð->d_addr.addr_bytes[0];\n\t*((uint64_t *)tmp) = 0x000000000002 + ((uint64_t)dst_port << 40);\n\n\t/* src addr */\n\tether_addr_copy(&l2fwd_ports_eth_addr[dst_port], ð->s_addr);\n\n\tl2fwd_send_packet(m, (uint8_t) dst_port);\n}\n\nstatic void\nl2fwd_job_update_cb(struct rte_jobstats *job, int64_t result)\n{\n\tint64_t err = job->target - result;\n\tint64_t histeresis = job->target / 8;\n\n\tif (err < -histeresis) {\n\t\tif (job->min_period + UPDATE_STEP_DOWN < job->period)\n\t\t\tjob->period -= UPDATE_STEP_DOWN;\n\t} else if (err > histeresis) {\n\t\tif (job->period + UPDATE_STEP_UP < job->max_period)\n\t\t\tjob->period += UPDATE_STEP_UP;\n\t}\n}\n\nstatic void\nl2fwd_fwd_job(__rte_unused struct rte_timer *timer, void *arg)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_mbuf *m;\n\n\tconst uint8_t port_idx = (uintptr_t) arg;\n\tconst unsigned lcore_id = rte_lcore_id();\n\tstruct lcore_queue_conf *qconf = &lcore_queue_conf[lcore_id];\n\tstruct rte_jobstats *job = &qconf->port_fwd_jobs[port_idx];\n\tconst uint8_t portid = qconf->rx_port_list[port_idx];\n\n\tuint8_t j;\n\tuint16_t total_nb_rx;\n\n\trte_jobstats_start(&qconf->jobs_context, job);\n\n\t/* Call rx burst 2 times. This allow rte_jobstats logic to see if this\n\t * function must be called more frequently. */\n\n\ttotal_nb_rx = rte_eth_rx_burst((uint8_t) portid, 0, pkts_burst,\n\t\t\tMAX_PKT_BURST);\n\n\tfor (j = 0; j < total_nb_rx; j++) {\n\t\tm = pkts_burst[j];\n\t\trte_prefetch0(rte_pktmbuf_mtod(m, void *));\n\t\tl2fwd_simple_forward(m, portid);\n\t}\n\n\tif (total_nb_rx == MAX_PKT_BURST) {\n\t\tconst uint16_t nb_rx = rte_eth_rx_burst((uint8_t) portid, 0, pkts_burst,\n\t\t\t\tMAX_PKT_BURST);\n\n\t\ttotal_nb_rx += nb_rx;\n\t\tfor (j = 0; j < nb_rx; j++) {\n\t\t\tm = pkts_burst[j];\n\t\t\trte_prefetch0(rte_pktmbuf_mtod(m, void *));\n\t\t\tl2fwd_simple_forward(m, portid);\n\t\t}\n\t}\n\n\tport_statistics[portid].rx += total_nb_rx;\n\n\t/* Adjust period time in which we are running here. */\n\tif (rte_jobstats_finish(job, total_nb_rx) != 0) {\n\t\trte_timer_reset(&qconf->rx_timers[port_idx], job->period, PERIODICAL,\n\t\t\t\tlcore_id, l2fwd_fwd_job, arg);\n\t}\n}\n\nstatic void\nl2fwd_flush_job(__rte_unused struct rte_timer *timer, __rte_unused void *arg)\n{\n\tuint64_t now;\n\tunsigned lcore_id;\n\tstruct lcore_queue_conf *qconf;\n\tstruct mbuf_table *m_table;\n\tuint8_t portid;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_queue_conf[lcore_id];\n\n\trte_jobstats_start(&qconf->jobs_context, &qconf->flush_job);\n\n\tnow = rte_get_timer_cycles();\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_queue_conf[lcore_id];\n\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\tm_table = &qconf->tx_mbufs[portid];\n\t\tif (m_table->len == 0 || m_table->next_flush_time <= now)\n\t\t\tcontinue;\n\n\t\tl2fwd_send_burst(qconf, portid);\n\t}\n\n\n\t/* Pass target to indicate that this job is happy of time interwal\n\t * in which it was called. */\n\trte_jobstats_finish(&qconf->flush_job, qconf->flush_job.target);\n}\n\n/* main processing loop */\nstatic void\nl2fwd_main_loop(void)\n{\n\tunsigned lcore_id;\n\tunsigned i, portid;\n\tstruct lcore_queue_conf *qconf;\n\tuint8_t stats_read_pending = 0;\n\tuint8_t need_manage;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_queue_conf[lcore_id];\n\n\tif (qconf->n_rx_port == 0) {\n\t\tRTE_LOG(INFO, L2FWD, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn;\n\t}\n\n\tRTE_LOG(INFO, L2FWD, \"entering main loop on lcore %u\\n\", lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\n\t\tportid = qconf->rx_port_list[i];\n\t\tRTE_LOG(INFO, L2FWD, \" -- lcoreid=%u portid=%u\\n\", lcore_id,\n\t\t\tportid);\n\t}\n\n\trte_jobstats_init(&qconf->idle_job, \"idle\", 0, 0, 0, 0);\n\n\tfor (;;) {\n\t\trte_spinlock_lock(&qconf->lock);\n\n\t\tdo {\n\t\t\trte_jobstats_context_start(&qconf->jobs_context);\n\n\t\t\t/* Do the Idle job:\n\t\t\t * - Read stats_read_pending flag\n\t\t\t * - check if some real job need to be executed\n\t\t\t */\n\t\t\trte_jobstats_start(&qconf->jobs_context, &qconf->idle_job);\n\n\t\t\tdo {\n\t\t\t\tuint8_t i;\n\t\t\t\tuint64_t now = rte_get_timer_cycles();\n\n\t\t\t\tneed_manage = qconf->flush_timer.expire < now;\n\t\t\t\t/* Check if we was esked to give a stats. */\n\t\t\t\tstats_read_pending =\n\t\t\t\t\t\trte_atomic16_read(&qconf->stats_read_pending);\n\t\t\t\tneed_manage |= stats_read_pending;\n\n\t\t\t\tfor (i = 0; i < qconf->n_rx_port && !need_manage; i++)\n\t\t\t\t\tneed_manage = qconf->rx_timers[i].expire < now;\n\n\t\t\t} while (!need_manage);\n\t\t\trte_jobstats_finish(&qconf->idle_job, qconf->idle_job.target);\n\n\t\t\trte_timer_manage();\n\t\t\trte_jobstats_context_finish(&qconf->jobs_context);\n\t\t} while (likely(stats_read_pending == 0));\n\n\t\trte_spinlock_unlock(&qconf->lock);\n\t\trte_pause();\n\t}\n}\n\nstatic int\nl2fwd_launch_one_lcore(__attribute__((unused)) void *dummy)\n{\n\tl2fwd_main_loop();\n\treturn 0;\n}\n\n/* display usage */\nstatic void\nl2fwd_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK [-q NQ]\\n\"\n\t \" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t \" -q NQ: number of queue (=ports) per lcore (default is 1)\\n\"\n\t\t \" -T PERIOD: statistics will be refreshed each PERIOD seconds (0 to disable, 10 default, 86400 maximum)\\n\"\n\t\t \" -l set system default locale instead of default (\\\"C\\\" locale) for thousands separator in stats.\",\n\t prgname);\n}\n\nstatic int\nl2fwd_parse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\nstatic unsigned int\nl2fwd_parse_nqueue(const char *q_arg)\n{\n\tchar *end = NULL;\n\tunsigned long n;\n\n\t/* parse hexadecimal string */\n\tn = strtoul(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn 0;\n\tif (n == 0)\n\t\treturn 0;\n\tif (n >= MAX_RX_QUEUE_PER_LCORE)\n\t\treturn 0;\n\n\treturn n;\n}\n\nstatic int\nl2fwd_parse_timer_period(const char *q_arg)\n{\n\tchar *end = NULL;\n\tint n;\n\n\t/* parse number string */\n\tn = strtol(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\tif (n >= MAX_TIMER_PERIOD)\n\t\treturn -1;\n\n\treturn n;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nl2fwd_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:q:T:l\",\n\t\t\t\t lgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tl2fwd_enabled_port_mask = l2fwd_parse_portmask(optarg);\n\t\t\tif (l2fwd_enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tl2fwd_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* nqueue */\n\t\tcase 'q':\n\t\t\tl2fwd_rx_queue_per_lcore = l2fwd_parse_nqueue(optarg);\n\t\t\tif (l2fwd_rx_queue_per_lcore == 0) {\n\t\t\t\tprintf(\"invalid queue number\\n\");\n\t\t\t\tl2fwd_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* timer period */\n\t\tcase 'T':\n\t\t\ttimer_period = l2fwd_parse_timer_period(optarg);\n\t\t\tif (timer_period < 0) {\n\t\t\t\tprintf(\"invalid timer period\\n\");\n\t\t\t\tl2fwd_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* For thousands separator in printf. */\n\t\tcase 'l':\n\t\t\tsetlocale(LC_ALL, \"\");\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tl2fwd_usage(prgname);\n\t\t\treturn -1;\n\n\t\tdefault:\n\t\t\tl2fwd_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_queue_conf *qconf;\n\tstruct rte_eth_dev_info dev_info;\n\tunsigned lcore_id, rx_lcore_id;\n\tunsigned nb_ports_in_mask = 0;\n\tint ret;\n\tchar name[RTE_JOBSTATS_NAMESIZE];\n\tuint8_t nb_ports;\n\tuint8_t nb_ports_available;\n\tuint8_t portid, last_port;\n\tuint8_t i;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid EAL arguments\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = l2fwd_parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid L2FWD arguments\\n\");\n\n\trte_timer_subsystem_init();\n\n\t/* fetch default timer frequency. */\n\thz = rte_get_timer_hz();\n\n\t/* create the mbuf pool */\n\tl2fwd_pktmbuf_pool =\n\t\trte_pktmbuf_pool_create(\"mbuf_pool\", NB_MBUF, 32,\n\t\t\t0, RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\tif (l2fwd_pktmbuf_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot init mbuf pool\\n\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports == 0)\n\t\trte_exit(EXIT_FAILURE, \"No Ethernet ports - bye\\n\");\n\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\t/* reset l2fwd_dst_ports */\n\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++)\n\t\tl2fwd_dst_ports[portid] = 0;\n\tlast_port = 0;\n\n\t/*\n\t * Each logical core is assigned a dedicated TX queue on each port.\n\t */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\n\t\tif (nb_ports_in_mask % 2) {\n\t\t\tl2fwd_dst_ports[portid] = last_port;\n\t\t\tl2fwd_dst_ports[last_port] = portid;\n\t\t} else\n\t\t\tlast_port = portid;\n\n\t\tnb_ports_in_mask++;\n\n\t\trte_eth_dev_info_get(portid, &dev_info);\n\t}\n\tif (nb_ports_in_mask % 2) {\n\t\tprintf(\"Notice: odd number of ports in portmask.\\n\");\n\t\tl2fwd_dst_ports[last_port] = last_port;\n\t}\n\n\trx_lcore_id = 0;\n\tqconf = NULL;\n\n\t/* Initialize the port/queue configuration of each logical core */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\n\t\t/* get the lcore_id for this port */\n\t\twhile (rte_lcore_is_enabled(rx_lcore_id) == 0 ||\n\t\t lcore_queue_conf[rx_lcore_id].n_rx_port ==\n\t\t l2fwd_rx_queue_per_lcore) {\n\t\t\trx_lcore_id++;\n\t\t\tif (rx_lcore_id >= RTE_MAX_LCORE)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Not enough cores\\n\");\n\t\t}\n\n\t\tif (qconf != &lcore_queue_conf[rx_lcore_id])\n\t\t\t/* Assigned a new logical core in the loop above. */\n\t\t\tqconf = &lcore_queue_conf[rx_lcore_id];\n\n\t\tqconf->rx_port_list[qconf->n_rx_port] = portid;\n\t\tqconf->n_rx_port++;\n\t\tprintf(\"Lcore %u: RX port %u\\n\", rx_lcore_id, (unsigned) portid);\n\t}\n\n\tnb_ports_available = nb_ports;\n\n\t/* Initialise each port */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"Skipping disabled port %u\\n\", (unsigned) portid);\n\t\t\tnb_ports_available--;\n\t\t\tcontinue;\n\t\t}\n\t\t/* init port */\n\t\tprintf(\"Initializing port %u... \", (unsigned) portid);\n\t\tfflush(stdout);\n\t\tret = rte_eth_dev_configure(portid, 1, 1, &port_conf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot configure device: err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\trte_eth_macaddr_get(portid, &l2fwd_ports_eth_addr[portid]);\n\n\t\t/* init one RX queue */\n\t\tfflush(stdout);\n\t\tret = rte_eth_rx_queue_setup(portid, 0, nb_rxd,\n\t\t\t\t\t rte_eth_dev_socket_id(portid),\n\t\t\t\t\t NULL,\n\t\t\t\t\t l2fwd_pktmbuf_pool);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup:err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\t/* init one TX queue on each port */\n\t\tfflush(stdout);\n\t\tret = rte_eth_tx_queue_setup(portid, 0, nb_txd,\n\t\t\t\trte_eth_dev_socket_id(portid),\n\t\t\t\tNULL);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup:err=%d, port=%u\\n\",\n\t\t\t\tret, (unsigned) portid);\n\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_dev_start:err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\tprintf(\"done:\\n\");\n\n\t\trte_eth_promiscuous_enable(portid);\n\n\t\tprintf(\"Port %u, MAC address: %02X:%02X:%02X:%02X:%02X:%02X\\n\\n\",\n\t\t\t\t(unsigned) portid,\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[0],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[1],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[2],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[3],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[4],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[5]);\n\n\t\t/* initialize port stats */\n\t\tmemset(&port_statistics, 0, sizeof(port_statistics));\n\t}\n\n\tif (!nb_ports_available) {\n\t\trte_exit(EXIT_FAILURE,\n\t\t\t\"All available ports are disabled. Please set portmask.\\n\");\n\t}\n\n\tcheck_all_ports_link_status(nb_ports, l2fwd_enabled_port_mask);\n\n\tdrain_tsc = (hz + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\tRTE_LCORE_FOREACH(lcore_id) {\n\t\tqconf = &lcore_queue_conf[lcore_id];\n\n\t\trte_spinlock_init(&qconf->lock);\n\n\t\tif (rte_jobstats_context_init(&qconf->jobs_context) != 0)\n\t\t\trte_panic(\"Jobs stats context for core %u init failed\\n\", lcore_id);\n\n\t\tif (qconf->n_rx_port == 0) {\n\t\t\tRTE_LOG(INFO, L2FWD,\n\t\t\t\t\"lcore %u: no ports so no jobs stats context initialization\\n\",\n\t\t\t\tlcore_id);\n\t\t\tcontinue;\n\t\t}\n\t\t/* Add flush job.\n\t\t * Set fixed period by setting min = max = initial period. Set target to\n\t\t * zero as it is irrelevant for this job. */\n\t\trte_jobstats_init(&qconf->flush_job, \"flush\", drain_tsc, drain_tsc,\n\t\t\t\tdrain_tsc, 0);\n\n\t\trte_timer_init(&qconf->flush_timer);\n\t\tret = rte_timer_reset(&qconf->flush_timer, drain_tsc, PERIODICAL,\n\t\t\t\tlcore_id, &l2fwd_flush_job, NULL);\n\n\t\tif (ret < 0) {\n\t\t\trte_exit(1, \"Failed to reset flush job timer for lcore %u: %s\",\n\t\t\t\t\tlcore_id, rte_strerror(-ret));\n\t\t}\n\n\t\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\t\t\tstruct rte_jobstats *job = &qconf->port_fwd_jobs[i];\n\n\t\t\tportid = qconf->rx_port_list[i];\n\t\t\tprintf(\"Setting forward jon for port %u\\n\", portid);\n\n\t\t\tsnprintf(name, RTE_DIM(name), \"port %u fwd\", portid);\n\t\t\t/* Setup forward job.\n\t\t\t * Set min, max and initial period. Set target to MAX_PKT_BURST as\n\t\t\t * this is desired optimal RX/TX burst size. */\n\t\t\trte_jobstats_init(job, name, 0, drain_tsc, 0, MAX_PKT_BURST);\n\t\t\trte_jobstats_set_update_period_function(job, l2fwd_job_update_cb);\n\n\t\t\trte_timer_init(&qconf->rx_timers[i]);\n\t\t\tret = rte_timer_reset(&qconf->rx_timers[i], 0, PERIODICAL, lcore_id,\n\t\t\t\t\t&l2fwd_fwd_job, (void *)(uintptr_t)i);\n\n\t\t\tif (ret < 0) {\n\t\t\t\trte_exit(1, \"Failed to reset lcore %u port %u job timer: %s\",\n\t\t\t\t\t\tlcore_id, qconf->rx_port_list[i], rte_strerror(-ret));\n\t\t\t}\n\t\t}\n\t}\n\n\tif (timer_period)\n\t\trte_eal_alarm_set(timer_period * MS_PER_S, show_stats_cb, NULL);\n\telse\n\t\tRTE_LOG(INFO, L2FWD, \"Stats display disabled\\n\");\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(l2fwd_launch_one_lcore, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/l3fwd/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = l3fwd\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3 $(USER_FLAGS)\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/l3fwd/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#define APP_LOOKUP_EXACT_MATCH 0\n#define APP_LOOKUP_LPM 1\n#define DO_RFC_1812_CHECKS\n\n#ifndef APP_LOOKUP_METHOD\n#define APP_LOOKUP_METHOD APP_LOOKUP_LPM\n#endif\n\n/*\n * When set to zero, simple forwaring path is eanbled.\n * When set to one, optimized forwarding path is enabled.\n * Note that LPM optimisation path uses SSE4.1 instructions.\n */\n#if ((APP_LOOKUP_METHOD == APP_LOOKUP_LPM) && !defined(__SSE4_1__))\n#define ENABLE_MULTI_BUFFER_OPTIMIZE\t0\n#else\n#define ENABLE_MULTI_BUFFER_OPTIMIZE\t1\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n#include \n#elif (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\n#include \n#include \n#else\n#error \"APP_LOOKUP_METHOD set to incorrect value\"\n#endif\n\n#ifndef IPv6_BYTES\n#define IPv6_BYTES_FMT \"%02x%02x:%02x%02x:%02x%02x:%02x%02x:\"\\\n \"%02x%02x:%02x%02x:%02x%02x:%02x%02x\"\n#define IPv6_BYTES(addr) \\\n\taddr[0], addr[1], addr[2], addr[3], \\\n\taddr[4], addr[5], addr[6], addr[7], \\\n\taddr[8], addr[9], addr[10], addr[11],\\\n\taddr[12], addr[13],addr[14], addr[15]\n#endif\n\n\n#define RTE_LOGTYPE_L3FWD RTE_LOGTYPE_USER1\n\n#define MAX_JUMBO_PKT_LEN 9600\n\n#define IPV6_ADDR_LEN 16\n\n#define MEMPOOL_CACHE_SIZE 256\n\n/*\n * This expression is used to calculate the number of mbufs needed depending on user input, taking\n * into account memory for rx and tx hardware rings, cache per lcore and mtable per port per lcore.\n * RTE_MAX is used to ensure that NB_MBUF never goes below a minimum value of 8192\n */\n\n#define NB_MBUF RTE_MAX\t(\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t(nb_ports*nb_rx_queue*RTE_TEST_RX_DESC_DEFAULT +\t\t\t\t\t\t\t\\\n\t\t\t\tnb_ports*nb_lcores*MAX_PKT_BURST +\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\tnb_ports*n_tx_queue*RTE_TEST_TX_DESC_DEFAULT +\t\t\t\t\t\t\t\t\\\n\t\t\t\tnb_lcores*MEMPOOL_CACHE_SIZE),\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t(unsigned)8192)\n\n#define MAX_PKT_BURST 32\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n/*\n * Try to avoid TX buffering if we have at least MAX_TX_BURST packets to send.\n */\n#define\tMAX_TX_BURST\t(MAX_PKT_BURST / 2)\n\n#define NB_SOCKETS 8\n\n/* Configure how many packets ahead to prefetch, when reading packets */\n#define PREFETCH_OFFSET\t3\n\n/* Used to mark destination port as 'invalid'. */\n#define\tBAD_PORT\t((uint16_t)-1)\n\n#define FWDSTEP\t4\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n/* ethernet addresses of ports */\nstatic uint64_t dest_eth_addr[RTE_MAX_ETHPORTS];\nstatic struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];\n\nstatic __m128i val_eth[RTE_MAX_ETHPORTS];\n\n/* replace first 12B of the ethernet header. */\n#define\tMASK_ETH\t0x3f\n\n/* mask of enabled ports */\nstatic uint32_t enabled_port_mask = 0;\nstatic int promiscuous_on = 0; /**< Ports set in promiscuous mode off by default. */\nstatic int numa_on = 1; /**< NUMA is enabled by default. */\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\nstatic int ipv6 = 0; /**< ipv6 is false by default. */\n#endif\n\nstruct mbuf_table {\n\tuint16_t len;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST];\n};\n\nstruct lcore_rx_queue {\n\tuint8_t port_id;\n\tuint8_t queue_id;\n} __rte_cache_aligned;\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT RTE_MAX_ETHPORTS\n#define MAX_RX_QUEUE_PER_PORT 128\n\n#define MAX_LCORE_PARAMS 1024\nstruct lcore_params {\n\tuint8_t port_id;\n\tuint8_t queue_id;\n\tuint8_t lcore_id;\n} __rte_cache_aligned;\n\nstatic struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];\nstatic struct lcore_params lcore_params_array_default[] = {\n\t{0, 0, 2},\n\t{0, 1, 2},\n\t{0, 2, 2},\n\t{1, 0, 2},\n\t{1, 1, 2},\n\t{1, 2, 2},\n\t{2, 0, 2},\n\t{3, 0, 3},\n\t{3, 1, 3},\n};\n\nstatic struct lcore_params * lcore_params = lcore_params_array_default;\nstatic uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /\n\t\t\t\tsizeof(lcore_params_array_default[0]);\n\nstatic struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.mq_mode = ETH_MQ_RX_RSS,\n\t\t.max_rx_pkt_len = ETHER_MAX_LEN,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 1, /**< IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.rx_adv_conf = {\n\t\t.rss_conf = {\n\t\t\t.rss_key = NULL,\n\t\t\t.rss_hf = ETH_RSS_IP,\n\t\t},\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\nstatic struct rte_mempool * pktmbuf_pool[NB_SOCKETS];\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n\n#ifdef RTE_MACHINE_CPUFLAG_SSE4_2\n#include \n#define DEFAULT_HASH_FUNC rte_hash_crc\n#else\n#include \n#define DEFAULT_HASH_FUNC rte_jhash\n#endif\n\nstruct ipv4_5tuple {\n uint32_t ip_dst;\n uint32_t ip_src;\n uint16_t port_dst;\n uint16_t port_src;\n uint8_t proto;\n} __attribute__((__packed__));\n\nunion ipv4_5tuple_host {\n\tstruct {\n\t\tuint8_t pad0;\n\t\tuint8_t proto;\n\t\tuint16_t pad1;\n\t\tuint32_t ip_src;\n\t\tuint32_t ip_dst;\n\t\tuint16_t port_src;\n\t\tuint16_t port_dst;\n\t};\n\t__m128i xmm;\n};\n\n#define XMM_NUM_IN_IPV6_5TUPLE 3\n\nstruct ipv6_5tuple {\n uint8_t ip_dst[IPV6_ADDR_LEN];\n uint8_t ip_src[IPV6_ADDR_LEN];\n uint16_t port_dst;\n uint16_t port_src;\n uint8_t proto;\n} __attribute__((__packed__));\n\nunion ipv6_5tuple_host {\n\tstruct {\n\t\tuint16_t pad0;\n\t\tuint8_t proto;\n\t\tuint8_t pad1;\n\t\tuint8_t ip_src[IPV6_ADDR_LEN];\n\t\tuint8_t ip_dst[IPV6_ADDR_LEN];\n\t\tuint16_t port_src;\n\t\tuint16_t port_dst;\n\t\tuint64_t reserve;\n\t};\n\t__m128i xmm[XMM_NUM_IN_IPV6_5TUPLE];\n};\n\nstruct ipv4_l3fwd_route {\n\tstruct ipv4_5tuple key;\n\tuint8_t if_out;\n};\n\nstruct ipv6_l3fwd_route {\n\tstruct ipv6_5tuple key;\n\tuint8_t if_out;\n};\n\nstatic struct ipv4_l3fwd_route ipv4_l3fwd_route_array[] = {\n\t{{IPv4(101,0,0,0), IPv4(100,10,0,1), 101, 11, IPPROTO_TCP}, 0},\n\t{{IPv4(201,0,0,0), IPv4(200,20,0,1), 102, 12, IPPROTO_TCP}, 1},\n\t{{IPv4(111,0,0,0), IPv4(100,30,0,1), 101, 11, IPPROTO_TCP}, 2},\n\t{{IPv4(211,0,0,0), IPv4(200,40,0,1), 102, 12, IPPROTO_TCP}, 3},\n};\n\nstatic struct ipv6_l3fwd_route ipv6_l3fwd_route_array[] = {\n\t{{\n\t{0xfe, 0x80, 0, 0, 0, 0, 0, 0, 0x02, 0x1e, 0x67, 0xff, 0xfe, 0, 0, 0},\n\t{0xfe, 0x80, 0, 0, 0, 0, 0, 0, 0x02, 0x1b, 0x21, 0xff, 0xfe, 0x91, 0x38, 0x05},\n\t101, 11, IPPROTO_TCP}, 0},\n\n\t{{\n\t{0xfe, 0x90, 0, 0, 0, 0, 0, 0, 0x02, 0x1e, 0x67, 0xff, 0xfe, 0, 0, 0},\n\t{0xfe, 0x90, 0, 0, 0, 0, 0, 0, 0x02, 0x1b, 0x21, 0xff, 0xfe, 0x91, 0x38, 0x05},\n\t102, 12, IPPROTO_TCP}, 1},\n\n\t{{\n\t{0xfe, 0xa0, 0, 0, 0, 0, 0, 0, 0x02, 0x1e, 0x67, 0xff, 0xfe, 0, 0, 0},\n\t{0xfe, 0xa0, 0, 0, 0, 0, 0, 0, 0x02, 0x1b, 0x21, 0xff, 0xfe, 0x91, 0x38, 0x05},\n\t101, 11, IPPROTO_TCP}, 2},\n\n\t{{\n\t{0xfe, 0xb0, 0, 0, 0, 0, 0, 0, 0x02, 0x1e, 0x67, 0xff, 0xfe, 0, 0, 0},\n\t{0xfe, 0xb0, 0, 0, 0, 0, 0, 0, 0x02, 0x1b, 0x21, 0xff, 0xfe, 0x91, 0x38, 0x05},\n\t102, 12, IPPROTO_TCP}, 3},\n};\n\ntypedef struct rte_hash lookup_struct_t;\nstatic lookup_struct_t *ipv4_l3fwd_lookup_struct[NB_SOCKETS];\nstatic lookup_struct_t *ipv6_l3fwd_lookup_struct[NB_SOCKETS];\n\n#ifdef RTE_ARCH_X86_64\n/* default to 4 million hash entries (approx) */\n#define L3FWD_HASH_ENTRIES\t\t1024*1024*4\n#else\n/* 32-bit has less address-space for hugepage memory, limit to 1M entries */\n#define L3FWD_HASH_ENTRIES\t\t1024*1024*1\n#endif\n#define HASH_ENTRY_NUMBER_DEFAULT\t4\n\nstatic uint32_t hash_entry_number = HASH_ENTRY_NUMBER_DEFAULT;\n\nstatic inline uint32_t\nipv4_hash_crc(const void *data, __rte_unused uint32_t data_len,\n\tuint32_t init_val)\n{\n\tconst union ipv4_5tuple_host *k;\n\tuint32_t t;\n\tconst uint32_t *p;\n\n\tk = data;\n\tt = k->proto;\n\tp = (const uint32_t *)&k->port_src;\n\n#ifdef RTE_MACHINE_CPUFLAG_SSE4_2\n\tinit_val = rte_hash_crc_4byte(t, init_val);\n\tinit_val = rte_hash_crc_4byte(k->ip_src, init_val);\n\tinit_val = rte_hash_crc_4byte(k->ip_dst, init_val);\n\tinit_val = rte_hash_crc_4byte(*p, init_val);\n#else /* RTE_MACHINE_CPUFLAG_SSE4_2 */\n\tinit_val = rte_jhash_1word(t, init_val);\n\tinit_val = rte_jhash_1word(k->ip_src, init_val);\n\tinit_val = rte_jhash_1word(k->ip_dst, init_val);\n\tinit_val = rte_jhash_1word(*p, init_val);\n#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */\n\treturn (init_val);\n}\n\nstatic inline uint32_t\nipv6_hash_crc(const void *data, __rte_unused uint32_t data_len, uint32_t init_val)\n{\n\tconst union ipv6_5tuple_host *k;\n\tuint32_t t;\n\tconst uint32_t *p;\n#ifdef RTE_MACHINE_CPUFLAG_SSE4_2\n\tconst uint32_t *ip_src0, *ip_src1, *ip_src2, *ip_src3;\n\tconst uint32_t *ip_dst0, *ip_dst1, *ip_dst2, *ip_dst3;\n#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */\n\n\tk = data;\n\tt = k->proto;\n\tp = (const uint32_t *)&k->port_src;\n\n#ifdef RTE_MACHINE_CPUFLAG_SSE4_2\n\tip_src0 = (const uint32_t *) k->ip_src;\n\tip_src1 = (const uint32_t *)(k->ip_src+4);\n\tip_src2 = (const uint32_t *)(k->ip_src+8);\n\tip_src3 = (const uint32_t *)(k->ip_src+12);\n\tip_dst0 = (const uint32_t *) k->ip_dst;\n\tip_dst1 = (const uint32_t *)(k->ip_dst+4);\n\tip_dst2 = (const uint32_t *)(k->ip_dst+8);\n\tip_dst3 = (const uint32_t *)(k->ip_dst+12);\n\tinit_val = rte_hash_crc_4byte(t, init_val);\n\tinit_val = rte_hash_crc_4byte(*ip_src0, init_val);\n\tinit_val = rte_hash_crc_4byte(*ip_src1, init_val);\n\tinit_val = rte_hash_crc_4byte(*ip_src2, init_val);\n\tinit_val = rte_hash_crc_4byte(*ip_src3, init_val);\n\tinit_val = rte_hash_crc_4byte(*ip_dst0, init_val);\n\tinit_val = rte_hash_crc_4byte(*ip_dst1, init_val);\n\tinit_val = rte_hash_crc_4byte(*ip_dst2, init_val);\n\tinit_val = rte_hash_crc_4byte(*ip_dst3, init_val);\n\tinit_val = rte_hash_crc_4byte(*p, init_val);\n#else /* RTE_MACHINE_CPUFLAG_SSE4_2 */\n\tinit_val = rte_jhash_1word(t, init_val);\n\tinit_val = rte_jhash(k->ip_src, sizeof(uint8_t) * IPV6_ADDR_LEN, init_val);\n\tinit_val = rte_jhash(k->ip_dst, sizeof(uint8_t) * IPV6_ADDR_LEN, init_val);\n\tinit_val = rte_jhash_1word(*p, init_val);\n#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */\n\treturn (init_val);\n}\n\n#define IPV4_L3FWD_NUM_ROUTES \\\n\t(sizeof(ipv4_l3fwd_route_array) / sizeof(ipv4_l3fwd_route_array[0]))\n\n#define IPV6_L3FWD_NUM_ROUTES \\\n\t(sizeof(ipv6_l3fwd_route_array) / sizeof(ipv6_l3fwd_route_array[0]))\n\nstatic uint8_t ipv4_l3fwd_out_if[L3FWD_HASH_ENTRIES] __rte_cache_aligned;\nstatic uint8_t ipv6_l3fwd_out_if[L3FWD_HASH_ENTRIES] __rte_cache_aligned;\n\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\nstruct ipv4_l3fwd_route {\n\tuint32_t ip;\n\tuint8_t depth;\n\tuint8_t if_out;\n};\n\nstruct ipv6_l3fwd_route {\n\tuint8_t ip[16];\n\tuint8_t depth;\n\tuint8_t if_out;\n};\n\nstatic struct ipv4_l3fwd_route ipv4_l3fwd_route_array[] = {\n\t{IPv4(1,1,1,0), 24, 0},\n\t{IPv4(2,1,1,0), 24, 1},\n\t{IPv4(3,1,1,0), 24, 2},\n\t{IPv4(4,1,1,0), 24, 3},\n\t{IPv4(5,1,1,0), 24, 4},\n\t{IPv4(6,1,1,0), 24, 5},\n\t{IPv4(7,1,1,0), 24, 6},\n\t{IPv4(8,1,1,0), 24, 7},\n};\n\nstatic struct ipv6_l3fwd_route ipv6_l3fwd_route_array[] = {\n\t{{1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 0},\n\t{{2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 1},\n\t{{3,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 2},\n\t{{4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 3},\n\t{{5,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 4},\n\t{{6,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 5},\n\t{{7,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 6},\n\t{{8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1}, 48, 7},\n};\n\n#define IPV4_L3FWD_NUM_ROUTES \\\n\t(sizeof(ipv4_l3fwd_route_array) / sizeof(ipv4_l3fwd_route_array[0]))\n#define IPV6_L3FWD_NUM_ROUTES \\\n\t(sizeof(ipv6_l3fwd_route_array) / sizeof(ipv6_l3fwd_route_array[0]))\n\n#define IPV4_L3FWD_LPM_MAX_RULES 1024\n#define IPV6_L3FWD_LPM_MAX_RULES 1024\n#define IPV6_L3FWD_LPM_NUMBER_TBL8S (1 << 16)\n\ntypedef struct rte_lpm lookup_struct_t;\ntypedef struct rte_lpm6 lookup6_struct_t;\nstatic lookup_struct_t *ipv4_l3fwd_lookup_struct[NB_SOCKETS];\nstatic lookup6_struct_t *ipv6_l3fwd_lookup_struct[NB_SOCKETS];\n#endif\n\nstruct lcore_conf {\n\tuint16_t n_rx_queue;\n\tstruct lcore_rx_queue rx_queue_list[MAX_RX_QUEUE_PER_LCORE];\n\tuint16_t tx_queue_id[RTE_MAX_ETHPORTS];\n\tstruct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];\n\tlookup_struct_t * ipv4_lookup_struct;\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\n\tlookup6_struct_t * ipv6_lookup_struct;\n#else\n\tlookup_struct_t * ipv6_lookup_struct;\n#endif\n} __rte_cache_aligned;\n\nstatic struct lcore_conf lcore_conf[RTE_MAX_LCORE];\n\n/* Send burst of packets on an output interface */\nstatic inline int\nsend_burst(struct lcore_conf *qconf, uint16_t n, uint8_t port)\n{\n\tstruct rte_mbuf **m_table;\n\tint ret;\n\tuint16_t queueid;\n\n\tqueueid = qconf->tx_queue_id[port];\n\tm_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;\n\n\tret = rte_eth_tx_burst(port, queueid, m_table, n);\n\tif (unlikely(ret < n)) {\n\t\tdo {\n\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t} while (++ret < n);\n\t}\n\n\treturn 0;\n}\n\n/* Enqueue a single packet, and send burst if queue is filled */\nstatic inline int\nsend_single_packet(struct rte_mbuf *m, uint8_t port)\n{\n\tuint32_t lcore_id;\n\tuint16_t len;\n\tstruct lcore_conf *qconf;\n\n\tlcore_id = rte_lcore_id();\n\n\tqconf = &lcore_conf[lcore_id];\n\tlen = qconf->tx_mbufs[port].len;\n\tqconf->tx_mbufs[port].m_table[len] = m;\n\tlen++;\n\n\t/* enough pkts to be sent */\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tsend_burst(qconf, MAX_PKT_BURST, port);\n\t\tlen = 0;\n\t}\n\n\tqconf->tx_mbufs[port].len = len;\n\treturn 0;\n}\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\nstatic inline __attribute__((always_inline)) void\nsend_packetsx4(struct lcore_conf *qconf, uint8_t port,\n\tstruct rte_mbuf *m[], uint32_t num)\n{\n\tuint32_t len, j, n;\n\n\tlen = qconf->tx_mbufs[port].len;\n\n\t/*\n\t * If TX buffer for that queue is empty, and we have enough packets,\n\t * then send them straightway.\n\t */\n\tif (num >= MAX_TX_BURST && len == 0) {\n\t\tn = rte_eth_tx_burst(port, qconf->tx_queue_id[port], m, num);\n\t\tif (unlikely(n < num)) {\n\t\t\tdo {\n\t\t\t\trte_pktmbuf_free(m[n]);\n\t\t\t} while (++n < num);\n\t\t}\n\t\treturn;\n\t}\n\n\t/*\n\t * Put packets into TX buffer for that queue.\n\t */\n\n\tn = len + num;\n\tn = (n > MAX_PKT_BURST) ? MAX_PKT_BURST - len : num;\n\n\tj = 0;\n\tswitch (n % FWDSTEP) {\n\twhile (j < n) {\n\tcase 0:\n\t\tqconf->tx_mbufs[port].m_table[len + j] = m[j];\n\t\tj++;\n\tcase 3:\n\t\tqconf->tx_mbufs[port].m_table[len + j] = m[j];\n\t\tj++;\n\tcase 2:\n\t\tqconf->tx_mbufs[port].m_table[len + j] = m[j];\n\t\tj++;\n\tcase 1:\n\t\tqconf->tx_mbufs[port].m_table[len + j] = m[j];\n\t\tj++;\n\t}\n\t}\n\n\tlen += n;\n\n\t/* enough pkts to be sent */\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\n\t\tsend_burst(qconf, MAX_PKT_BURST, port);\n\n\t\t/* copy rest of the packets into the TX buffer. */\n\t\tlen = num - n;\n\t\tj = 0;\n\t\tswitch (len % FWDSTEP) {\n\t\twhile (j < len) {\n\t\tcase 0:\n\t\t\tqconf->tx_mbufs[port].m_table[j] = m[n + j];\n\t\t\tj++;\n\t\tcase 3:\n\t\t\tqconf->tx_mbufs[port].m_table[j] = m[n + j];\n\t\t\tj++;\n\t\tcase 2:\n\t\t\tqconf->tx_mbufs[port].m_table[j] = m[n + j];\n\t\t\tj++;\n\t\tcase 1:\n\t\t\tqconf->tx_mbufs[port].m_table[j] = m[n + j];\n\t\t\tj++;\n\t\t}\n\t\t}\n\t}\n\n\tqconf->tx_mbufs[port].len = len;\n}\n#endif /* APP_LOOKUP_LPM */\n\n#ifdef DO_RFC_1812_CHECKS\nstatic inline int\nis_valid_ipv4_pkt(struct ipv4_hdr *pkt, uint32_t link_len)\n{\n\t/* From http://www.rfc-editor.org/rfc/rfc1812.txt section 5.2.2 */\n\t/*\n\t * 1. The packet length reported by the Link Layer must be large\n\t * enough to hold the minimum length legal IP datagram (20 bytes).\n\t */\n\tif (link_len < sizeof(struct ipv4_hdr))\n\t\treturn -1;\n\n\t/* 2. The IP checksum must be correct. */\n\t/* this is checked in H/W */\n\n\t/*\n\t * 3. The IP version number must be 4. If the version number is not 4\n\t * then the packet may be another version of IP, such as IPng or\n\t * ST-II.\n\t */\n\tif (((pkt->version_ihl) >> 4) != 4)\n\t\treturn -3;\n\t/*\n\t * 4. The IP header length field must be large enough to hold the\n\t * minimum length legal IP datagram (20 bytes = 5 words).\n\t */\n\tif ((pkt->version_ihl & 0xf) < 5)\n\t\treturn -4;\n\n\t/*\n\t * 5. The IP total length field must be large enough to hold the IP\n\t * datagram header, whose length is specified in the IP header length\n\t * field.\n\t */\n\tif (rte_cpu_to_be_16(pkt->total_length) < sizeof(struct ipv4_hdr))\n\t\treturn -5;\n\n\treturn 0;\n}\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n\nstatic __m128i mask0;\nstatic __m128i mask1;\nstatic __m128i mask2;\nstatic inline uint8_t\nget_ipv4_dst_port(void *ipv4_hdr, uint8_t portid, lookup_struct_t * ipv4_l3fwd_lookup_struct)\n{\n\tint ret = 0;\n\tunion ipv4_5tuple_host key;\n\n\tipv4_hdr = (uint8_t *)ipv4_hdr + offsetof(struct ipv4_hdr, time_to_live);\n\t__m128i data = _mm_loadu_si128((__m128i*)(ipv4_hdr));\n\t/* Get 5 tuple: dst port, src port, dst IP address, src IP address and protocol */\n\tkey.xmm = _mm_and_si128(data, mask0);\n\t/* Find destination port */\n\tret = rte_hash_lookup(ipv4_l3fwd_lookup_struct, (const void *)&key);\n\treturn (uint8_t)((ret < 0)? portid : ipv4_l3fwd_out_if[ret]);\n}\n\nstatic inline uint8_t\nget_ipv6_dst_port(void *ipv6_hdr, uint8_t portid, lookup_struct_t * ipv6_l3fwd_lookup_struct)\n{\n\tint ret = 0;\n\tunion ipv6_5tuple_host key;\n\n\tipv6_hdr = (uint8_t *)ipv6_hdr + offsetof(struct ipv6_hdr, payload_len);\n\t__m128i data0 = _mm_loadu_si128((__m128i*)(ipv6_hdr));\n\t__m128i data1 = _mm_loadu_si128((__m128i*)(((uint8_t*)ipv6_hdr)+sizeof(__m128i)));\n\t__m128i data2 = _mm_loadu_si128((__m128i*)(((uint8_t*)ipv6_hdr)+sizeof(__m128i)+sizeof(__m128i)));\n\t/* Get part of 5 tuple: src IP address lower 96 bits and protocol */\n\tkey.xmm[0] = _mm_and_si128(data0, mask1);\n\t/* Get part of 5 tuple: dst IP address lower 96 bits and src IP address higher 32 bits */\n\tkey.xmm[1] = data1;\n\t/* Get part of 5 tuple: dst port and src port and dst IP address higher 32 bits */\n\tkey.xmm[2] = _mm_and_si128(data2, mask2);\n\n\t/* Find destination port */\n\tret = rte_hash_lookup(ipv6_l3fwd_lookup_struct, (const void *)&key);\n\treturn (uint8_t)((ret < 0)? portid : ipv6_l3fwd_out_if[ret]);\n}\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\n\nstatic inline uint8_t\nget_ipv4_dst_port(void *ipv4_hdr, uint8_t portid, lookup_struct_t * ipv4_l3fwd_lookup_struct)\n{\n\tuint8_t next_hop;\n\n\treturn (uint8_t) ((rte_lpm_lookup(ipv4_l3fwd_lookup_struct,\n\t\trte_be_to_cpu_32(((struct ipv4_hdr *)ipv4_hdr)->dst_addr),\n\t\t&next_hop) == 0) ? next_hop : portid);\n}\n\nstatic inline uint8_t\nget_ipv6_dst_port(void *ipv6_hdr, uint8_t portid, lookup6_struct_t * ipv6_l3fwd_lookup_struct)\n{\n\tuint8_t next_hop;\n\treturn (uint8_t) ((rte_lpm6_lookup(ipv6_l3fwd_lookup_struct,\n\t\t\t((struct ipv6_hdr*)ipv6_hdr)->dst_addr, &next_hop) == 0)?\n\t\t\tnext_hop : portid);\n}\n#endif\n\nstatic inline void l3fwd_simple_forward(struct rte_mbuf *m, uint8_t portid,\n\tstruct lcore_conf *qconf) __attribute__((unused));\n\n#if ((APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH) && \\\n\t(ENABLE_MULTI_BUFFER_OPTIMIZE == 1))\n\n#define MASK_ALL_PKTS 0xff\n#define EXCLUDE_1ST_PKT 0xfe\n#define EXCLUDE_2ND_PKT 0xfd\n#define EXCLUDE_3RD_PKT 0xfb\n#define EXCLUDE_4TH_PKT 0xf7\n#define EXCLUDE_5TH_PKT 0xef\n#define EXCLUDE_6TH_PKT 0xdf\n#define EXCLUDE_7TH_PKT 0xbf\n#define EXCLUDE_8TH_PKT 0x7f\n\nstatic inline void\nsimple_ipv4_fwd_8pkts(struct rte_mbuf *m[8], uint8_t portid, struct lcore_conf *qconf)\n{\n\tstruct ether_hdr *eth_hdr[8];\n\tstruct ipv4_hdr *ipv4_hdr[8];\n\tuint8_t dst_port[8];\n\tint32_t ret[8];\n\tunion ipv4_5tuple_host key[8];\n\t__m128i data[8];\n\n\teth_hdr[0] = rte_pktmbuf_mtod(m[0], struct ether_hdr *);\n\teth_hdr[1] = rte_pktmbuf_mtod(m[1], struct ether_hdr *);\n\teth_hdr[2] = rte_pktmbuf_mtod(m[2], struct ether_hdr *);\n\teth_hdr[3] = rte_pktmbuf_mtod(m[3], struct ether_hdr *);\n\teth_hdr[4] = rte_pktmbuf_mtod(m[4], struct ether_hdr *);\n\teth_hdr[5] = rte_pktmbuf_mtod(m[5], struct ether_hdr *);\n\teth_hdr[6] = rte_pktmbuf_mtod(m[6], struct ether_hdr *);\n\teth_hdr[7] = rte_pktmbuf_mtod(m[7], struct ether_hdr *);\n\n\t/* Handle IPv4 headers.*/\n\tipv4_hdr[0] = rte_pktmbuf_mtod_offset(m[0], struct ipv4_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv4_hdr[1] = rte_pktmbuf_mtod_offset(m[1], struct ipv4_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv4_hdr[2] = rte_pktmbuf_mtod_offset(m[2], struct ipv4_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv4_hdr[3] = rte_pktmbuf_mtod_offset(m[3], struct ipv4_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv4_hdr[4] = rte_pktmbuf_mtod_offset(m[4], struct ipv4_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv4_hdr[5] = rte_pktmbuf_mtod_offset(m[5], struct ipv4_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv4_hdr[6] = rte_pktmbuf_mtod_offset(m[6], struct ipv4_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv4_hdr[7] = rte_pktmbuf_mtod_offset(m[7], struct ipv4_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\n#ifdef DO_RFC_1812_CHECKS\n\t/* Check to make sure the packet is valid (RFC1812) */\n\tuint8_t valid_mask = MASK_ALL_PKTS;\n\tif (is_valid_ipv4_pkt(ipv4_hdr[0], m[0]->pkt_len) < 0) {\n\t\trte_pktmbuf_free(m[0]);\n\t\tvalid_mask &= EXCLUDE_1ST_PKT;\n\t}\n\tif (is_valid_ipv4_pkt(ipv4_hdr[1], m[1]->pkt_len) < 0) {\n\t\trte_pktmbuf_free(m[1]);\n\t\tvalid_mask &= EXCLUDE_2ND_PKT;\n\t}\n\tif (is_valid_ipv4_pkt(ipv4_hdr[2], m[2]->pkt_len) < 0) {\n\t\trte_pktmbuf_free(m[2]);\n\t\tvalid_mask &= EXCLUDE_3RD_PKT;\n\t}\n\tif (is_valid_ipv4_pkt(ipv4_hdr[3], m[3]->pkt_len) < 0) {\n\t\trte_pktmbuf_free(m[3]);\n\t\tvalid_mask &= EXCLUDE_4TH_PKT;\n\t}\n\tif (is_valid_ipv4_pkt(ipv4_hdr[4], m[4]->pkt_len) < 0) {\n\t\trte_pktmbuf_free(m[4]);\n\t\tvalid_mask &= EXCLUDE_5TH_PKT;\n\t}\n\tif (is_valid_ipv4_pkt(ipv4_hdr[5], m[5]->pkt_len) < 0) {\n\t\trte_pktmbuf_free(m[5]);\n\t\tvalid_mask &= EXCLUDE_6TH_PKT;\n\t}\n\tif (is_valid_ipv4_pkt(ipv4_hdr[6], m[6]->pkt_len) < 0) {\n\t\trte_pktmbuf_free(m[6]);\n\t\tvalid_mask &= EXCLUDE_7TH_PKT;\n\t}\n\tif (is_valid_ipv4_pkt(ipv4_hdr[7], m[7]->pkt_len) < 0) {\n\t\trte_pktmbuf_free(m[7]);\n\t\tvalid_mask &= EXCLUDE_8TH_PKT;\n\t}\n\tif (unlikely(valid_mask != MASK_ALL_PKTS)) {\n\t\tif (valid_mask == 0){\n\t\t\treturn;\n\t\t} else {\n\t\t\tuint8_t i = 0;\n\t\t\tfor (i = 0; i < 8; i++) {\n\t\t\t\tif ((0x1 << i) & valid_mask) {\n\t\t\t\t\tl3fwd_simple_forward(m[i], portid, qconf);\n\t\t\t\t}\n\t\t\t}\n\t\t\treturn;\n\t\t}\n\t}\n#endif // End of #ifdef DO_RFC_1812_CHECKS\n\n\tdata[0] = _mm_loadu_si128(rte_pktmbuf_mtod_offset(m[0], __m128i *,\n\t\t\t\t\tsizeof(struct ether_hdr) +\n\t\t\t\t\toffsetof(struct ipv4_hdr, time_to_live)));\n\tdata[1] = _mm_loadu_si128(rte_pktmbuf_mtod_offset(m[1], __m128i *,\n\t\t\t\t\tsizeof(struct ether_hdr) +\n\t\t\t\t\toffsetof(struct ipv4_hdr, time_to_live)));\n\tdata[2] = _mm_loadu_si128(rte_pktmbuf_mtod_offset(m[2], __m128i *,\n\t\t\t\t\tsizeof(struct ether_hdr) +\n\t\t\t\t\toffsetof(struct ipv4_hdr, time_to_live)));\n\tdata[3] = _mm_loadu_si128(rte_pktmbuf_mtod_offset(m[3], __m128i *,\n\t\t\t\t\tsizeof(struct ether_hdr) +\n\t\t\t\t\toffsetof(struct ipv4_hdr, time_to_live)));\n\tdata[4] = _mm_loadu_si128(rte_pktmbuf_mtod_offset(m[4], __m128i *,\n\t\t\t\t\tsizeof(struct ether_hdr) +\n\t\t\t\t\toffsetof(struct ipv4_hdr, time_to_live)));\n\tdata[5] = _mm_loadu_si128(rte_pktmbuf_mtod_offset(m[5], __m128i *,\n\t\t\t\t\tsizeof(struct ether_hdr) +\n\t\t\t\t\toffsetof(struct ipv4_hdr, time_to_live)));\n\tdata[6] = _mm_loadu_si128(rte_pktmbuf_mtod_offset(m[6], __m128i *,\n\t\t\t\t\tsizeof(struct ether_hdr) +\n\t\t\t\t\toffsetof(struct ipv4_hdr, time_to_live)));\n\tdata[7] = _mm_loadu_si128(rte_pktmbuf_mtod_offset(m[7], __m128i *,\n\t\t\t\t\tsizeof(struct ether_hdr) +\n\t\t\t\t\toffsetof(struct ipv4_hdr, time_to_live)));\n\n\tkey[0].xmm = _mm_and_si128(data[0], mask0);\n\tkey[1].xmm = _mm_and_si128(data[1], mask0);\n\tkey[2].xmm = _mm_and_si128(data[2], mask0);\n\tkey[3].xmm = _mm_and_si128(data[3], mask0);\n\tkey[4].xmm = _mm_and_si128(data[4], mask0);\n\tkey[5].xmm = _mm_and_si128(data[5], mask0);\n\tkey[6].xmm = _mm_and_si128(data[6], mask0);\n\tkey[7].xmm = _mm_and_si128(data[7], mask0);\n\n\tconst void *key_array[8] = {&key[0], &key[1], &key[2], &key[3],\n\t\t\t\t&key[4], &key[5], &key[6], &key[7]};\n\n\trte_hash_lookup_multi(qconf->ipv4_lookup_struct, &key_array[0], 8, ret);\n\tdst_port[0] = (uint8_t) ((ret[0] < 0) ? portid : ipv4_l3fwd_out_if[ret[0]]);\n\tdst_port[1] = (uint8_t) ((ret[1] < 0) ? portid : ipv4_l3fwd_out_if[ret[1]]);\n\tdst_port[2] = (uint8_t) ((ret[2] < 0) ? portid : ipv4_l3fwd_out_if[ret[2]]);\n\tdst_port[3] = (uint8_t) ((ret[3] < 0) ? portid : ipv4_l3fwd_out_if[ret[3]]);\n\tdst_port[4] = (uint8_t) ((ret[4] < 0) ? portid : ipv4_l3fwd_out_if[ret[4]]);\n\tdst_port[5] = (uint8_t) ((ret[5] < 0) ? portid : ipv4_l3fwd_out_if[ret[5]]);\n\tdst_port[6] = (uint8_t) ((ret[6] < 0) ? portid : ipv4_l3fwd_out_if[ret[6]]);\n\tdst_port[7] = (uint8_t) ((ret[7] < 0) ? portid : ipv4_l3fwd_out_if[ret[7]]);\n\n\tif (dst_port[0] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[0]) == 0)\n\t\tdst_port[0] = portid;\n\tif (dst_port[1] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[1]) == 0)\n\t\tdst_port[1] = portid;\n\tif (dst_port[2] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[2]) == 0)\n\t\tdst_port[2] = portid;\n\tif (dst_port[3] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[3]) == 0)\n\t\tdst_port[3] = portid;\n\tif (dst_port[4] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[4]) == 0)\n\t\tdst_port[4] = portid;\n\tif (dst_port[5] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[5]) == 0)\n\t\tdst_port[5] = portid;\n\tif (dst_port[6] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[6]) == 0)\n\t\tdst_port[6] = portid;\n\tif (dst_port[7] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[7]) == 0)\n\t\tdst_port[7] = portid;\n\n#ifdef DO_RFC_1812_CHECKS\n\t/* Update time to live and header checksum */\n\t--(ipv4_hdr[0]->time_to_live);\n\t--(ipv4_hdr[1]->time_to_live);\n\t--(ipv4_hdr[2]->time_to_live);\n\t--(ipv4_hdr[3]->time_to_live);\n\t++(ipv4_hdr[0]->hdr_checksum);\n\t++(ipv4_hdr[1]->hdr_checksum);\n\t++(ipv4_hdr[2]->hdr_checksum);\n\t++(ipv4_hdr[3]->hdr_checksum);\n\t--(ipv4_hdr[4]->time_to_live);\n\t--(ipv4_hdr[5]->time_to_live);\n\t--(ipv4_hdr[6]->time_to_live);\n\t--(ipv4_hdr[7]->time_to_live);\n\t++(ipv4_hdr[4]->hdr_checksum);\n\t++(ipv4_hdr[5]->hdr_checksum);\n\t++(ipv4_hdr[6]->hdr_checksum);\n\t++(ipv4_hdr[7]->hdr_checksum);\n#endif\n\n\t/* dst addr */\n\t*(uint64_t *)ð_hdr[0]->d_addr = dest_eth_addr[dst_port[0]];\n\t*(uint64_t *)ð_hdr[1]->d_addr = dest_eth_addr[dst_port[1]];\n\t*(uint64_t *)ð_hdr[2]->d_addr = dest_eth_addr[dst_port[2]];\n\t*(uint64_t *)ð_hdr[3]->d_addr = dest_eth_addr[dst_port[3]];\n\t*(uint64_t *)ð_hdr[4]->d_addr = dest_eth_addr[dst_port[4]];\n\t*(uint64_t *)ð_hdr[5]->d_addr = dest_eth_addr[dst_port[5]];\n\t*(uint64_t *)ð_hdr[6]->d_addr = dest_eth_addr[dst_port[6]];\n\t*(uint64_t *)ð_hdr[7]->d_addr = dest_eth_addr[dst_port[7]];\n\n\t/* src addr */\n\tether_addr_copy(&ports_eth_addr[dst_port[0]], ð_hdr[0]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[1]], ð_hdr[1]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[2]], ð_hdr[2]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[3]], ð_hdr[3]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[4]], ð_hdr[4]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[5]], ð_hdr[5]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[6]], ð_hdr[6]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[7]], ð_hdr[7]->s_addr);\n\n\tsend_single_packet(m[0], (uint8_t)dst_port[0]);\n\tsend_single_packet(m[1], (uint8_t)dst_port[1]);\n\tsend_single_packet(m[2], (uint8_t)dst_port[2]);\n\tsend_single_packet(m[3], (uint8_t)dst_port[3]);\n\tsend_single_packet(m[4], (uint8_t)dst_port[4]);\n\tsend_single_packet(m[5], (uint8_t)dst_port[5]);\n\tsend_single_packet(m[6], (uint8_t)dst_port[6]);\n\tsend_single_packet(m[7], (uint8_t)dst_port[7]);\n\n}\n\nstatic inline void get_ipv6_5tuple(struct rte_mbuf* m0, __m128i mask0, __m128i mask1,\n\t\t\t\t union ipv6_5tuple_host * key)\n{\n __m128i tmpdata0 = _mm_loadu_si128(rte_pktmbuf_mtod_offset(m0, __m128i *, sizeof(struct ether_hdr) + offsetof(struct ipv6_hdr, payload_len)));\n __m128i tmpdata1 = _mm_loadu_si128(rte_pktmbuf_mtod_offset(m0, __m128i *, sizeof(struct ether_hdr) + offsetof(struct ipv6_hdr, payload_len) + sizeof(__m128i)));\n __m128i tmpdata2 = _mm_loadu_si128(rte_pktmbuf_mtod_offset(m0, __m128i *, sizeof(struct ether_hdr) + offsetof(struct ipv6_hdr, payload_len) + sizeof(__m128i) + sizeof(__m128i)));\n key->xmm[0] = _mm_and_si128(tmpdata0, mask0);\n key->xmm[1] = tmpdata1;\n key->xmm[2] = _mm_and_si128(tmpdata2, mask1);\n\treturn;\n}\n\nstatic inline void\nsimple_ipv6_fwd_8pkts(struct rte_mbuf *m[8], uint8_t portid, struct lcore_conf *qconf)\n{\n\tstruct ether_hdr *eth_hdr[8];\n\t__attribute__((unused)) struct ipv6_hdr *ipv6_hdr[8];\n\tuint8_t dst_port[8];\n\tint32_t ret[8];\n\tunion ipv6_5tuple_host key[8];\n\n\teth_hdr[0] = rte_pktmbuf_mtod(m[0], struct ether_hdr *);\n\teth_hdr[1] = rte_pktmbuf_mtod(m[1], struct ether_hdr *);\n\teth_hdr[2] = rte_pktmbuf_mtod(m[2], struct ether_hdr *);\n\teth_hdr[3] = rte_pktmbuf_mtod(m[3], struct ether_hdr *);\n\teth_hdr[4] = rte_pktmbuf_mtod(m[4], struct ether_hdr *);\n\teth_hdr[5] = rte_pktmbuf_mtod(m[5], struct ether_hdr *);\n\teth_hdr[6] = rte_pktmbuf_mtod(m[6], struct ether_hdr *);\n\teth_hdr[7] = rte_pktmbuf_mtod(m[7], struct ether_hdr *);\n\n\t/* Handle IPv6 headers.*/\n\tipv6_hdr[0] = rte_pktmbuf_mtod_offset(m[0], struct ipv6_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv6_hdr[1] = rte_pktmbuf_mtod_offset(m[1], struct ipv6_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv6_hdr[2] = rte_pktmbuf_mtod_offset(m[2], struct ipv6_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv6_hdr[3] = rte_pktmbuf_mtod_offset(m[3], struct ipv6_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv6_hdr[4] = rte_pktmbuf_mtod_offset(m[4], struct ipv6_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv6_hdr[5] = rte_pktmbuf_mtod_offset(m[5], struct ipv6_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv6_hdr[6] = rte_pktmbuf_mtod_offset(m[6], struct ipv6_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\tipv6_hdr[7] = rte_pktmbuf_mtod_offset(m[7], struct ipv6_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\n\tget_ipv6_5tuple(m[0], mask1, mask2, &key[0]);\n\tget_ipv6_5tuple(m[1], mask1, mask2, &key[1]);\n\tget_ipv6_5tuple(m[2], mask1, mask2, &key[2]);\n\tget_ipv6_5tuple(m[3], mask1, mask2, &key[3]);\n\tget_ipv6_5tuple(m[4], mask1, mask2, &key[4]);\n\tget_ipv6_5tuple(m[5], mask1, mask2, &key[5]);\n\tget_ipv6_5tuple(m[6], mask1, mask2, &key[6]);\n\tget_ipv6_5tuple(m[7], mask1, mask2, &key[7]);\n\n\tconst void *key_array[8] = {&key[0], &key[1], &key[2], &key[3],\n\t\t\t\t&key[4], &key[5], &key[6], &key[7]};\n\n\trte_hash_lookup_multi(qconf->ipv6_lookup_struct, &key_array[0], 4, ret);\n\tdst_port[0] = (uint8_t) ((ret[0] < 0) ? portid:ipv6_l3fwd_out_if[ret[0]]);\n\tdst_port[1] = (uint8_t) ((ret[1] < 0) ? portid:ipv6_l3fwd_out_if[ret[1]]);\n\tdst_port[2] = (uint8_t) ((ret[2] < 0) ? portid:ipv6_l3fwd_out_if[ret[2]]);\n\tdst_port[3] = (uint8_t) ((ret[3] < 0) ? portid:ipv6_l3fwd_out_if[ret[3]]);\n\tdst_port[4] = (uint8_t) ((ret[4] < 0) ? portid:ipv6_l3fwd_out_if[ret[4]]);\n\tdst_port[5] = (uint8_t) ((ret[5] < 0) ? portid:ipv6_l3fwd_out_if[ret[5]]);\n\tdst_port[6] = (uint8_t) ((ret[6] < 0) ? portid:ipv6_l3fwd_out_if[ret[6]]);\n\tdst_port[7] = (uint8_t) ((ret[7] < 0) ? portid:ipv6_l3fwd_out_if[ret[7]]);\n\n\tif (dst_port[0] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[0]) == 0)\n\t\tdst_port[0] = portid;\n\tif (dst_port[1] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[1]) == 0)\n\t\tdst_port[1] = portid;\n\tif (dst_port[2] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[2]) == 0)\n\t\tdst_port[2] = portid;\n\tif (dst_port[3] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[3]) == 0)\n\t\tdst_port[3] = portid;\n\tif (dst_port[4] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[4]) == 0)\n\t\tdst_port[4] = portid;\n\tif (dst_port[5] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[5]) == 0)\n\t\tdst_port[5] = portid;\n\tif (dst_port[6] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[6]) == 0)\n\t\tdst_port[6] = portid;\n\tif (dst_port[7] >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port[7]) == 0)\n\t\tdst_port[7] = portid;\n\n\t/* dst addr */\n\t*(uint64_t *)ð_hdr[0]->d_addr = dest_eth_addr[dst_port[0]];\n\t*(uint64_t *)ð_hdr[1]->d_addr = dest_eth_addr[dst_port[1]];\n\t*(uint64_t *)ð_hdr[2]->d_addr = dest_eth_addr[dst_port[2]];\n\t*(uint64_t *)ð_hdr[3]->d_addr = dest_eth_addr[dst_port[3]];\n\t*(uint64_t *)ð_hdr[4]->d_addr = dest_eth_addr[dst_port[4]];\n\t*(uint64_t *)ð_hdr[5]->d_addr = dest_eth_addr[dst_port[5]];\n\t*(uint64_t *)ð_hdr[6]->d_addr = dest_eth_addr[dst_port[6]];\n\t*(uint64_t *)ð_hdr[7]->d_addr = dest_eth_addr[dst_port[7]];\n\n\t/* src addr */\n\tether_addr_copy(&ports_eth_addr[dst_port[0]], ð_hdr[0]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[1]], ð_hdr[1]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[2]], ð_hdr[2]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[3]], ð_hdr[3]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[4]], ð_hdr[4]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[5]], ð_hdr[5]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[6]], ð_hdr[6]->s_addr);\n\tether_addr_copy(&ports_eth_addr[dst_port[7]], ð_hdr[7]->s_addr);\n\n\tsend_single_packet(m[0], (uint8_t)dst_port[0]);\n\tsend_single_packet(m[1], (uint8_t)dst_port[1]);\n\tsend_single_packet(m[2], (uint8_t)dst_port[2]);\n\tsend_single_packet(m[3], (uint8_t)dst_port[3]);\n\tsend_single_packet(m[4], (uint8_t)dst_port[4]);\n\tsend_single_packet(m[5], (uint8_t)dst_port[5]);\n\tsend_single_packet(m[6], (uint8_t)dst_port[6]);\n\tsend_single_packet(m[7], (uint8_t)dst_port[7]);\n\n}\n#endif /* APP_LOOKUP_METHOD */\n\nstatic inline __attribute__((always_inline)) void\nl3fwd_simple_forward(struct rte_mbuf *m, uint8_t portid, struct lcore_conf *qconf)\n{\n\tstruct ether_hdr *eth_hdr;\n\tstruct ipv4_hdr *ipv4_hdr;\n\tuint8_t dst_port;\n\n\teth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n#ifdef RTE_NEXT_ABI\n\tif (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {\n#else\n\tif (m->ol_flags & PKT_RX_IPV4_HDR) {\n#endif\n\t\t/* Handle IPv4 headers.*/\n\t\tipv4_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,\n\t\t\t\t\t\t sizeof(struct ether_hdr));\n\n#ifdef DO_RFC_1812_CHECKS\n\t\t/* Check to make sure the packet is valid (RFC1812) */\n\t\tif (is_valid_ipv4_pkt(ipv4_hdr, m->pkt_len) < 0) {\n\t\t\trte_pktmbuf_free(m);\n\t\t\treturn;\n\t\t}\n#endif\n\n\t\t dst_port = get_ipv4_dst_port(ipv4_hdr, portid,\n\t\t\tqconf->ipv4_lookup_struct);\n\t\tif (dst_port >= RTE_MAX_ETHPORTS ||\n\t\t\t\t(enabled_port_mask & 1 << dst_port) == 0)\n\t\t\tdst_port = portid;\n\n#ifdef DO_RFC_1812_CHECKS\n\t\t/* Update time to live and header checksum */\n\t\t--(ipv4_hdr->time_to_live);\n\t\t++(ipv4_hdr->hdr_checksum);\n#endif\n\t\t/* dst addr */\n\t\t*(uint64_t *)ð_hdr->d_addr = dest_eth_addr[dst_port];\n\n\t\t/* src addr */\n\t\tether_addr_copy(&ports_eth_addr[dst_port], ð_hdr->s_addr);\n\n\t\tsend_single_packet(m, dst_port);\n#ifdef RTE_NEXT_ABI\n\t} else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {\n#else\n\t} else {\n#endif\n\t\t/* Handle IPv6 headers.*/\n\t\tstruct ipv6_hdr *ipv6_hdr;\n\n\t\tipv6_hdr = rte_pktmbuf_mtod_offset(m, struct ipv6_hdr *,\n\t\t\t\t\t\t sizeof(struct ether_hdr));\n\n\t\tdst_port = get_ipv6_dst_port(ipv6_hdr, portid, qconf->ipv6_lookup_struct);\n\n\t\tif (dst_port >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port) == 0)\n\t\t\tdst_port = portid;\n\n\t\t/* dst addr */\n\t\t*(uint64_t *)ð_hdr->d_addr = dest_eth_addr[dst_port];\n\n\t\t/* src addr */\n\t\tether_addr_copy(&ports_eth_addr[dst_port], ð_hdr->s_addr);\n\n\t\tsend_single_packet(m, dst_port);\n#ifdef RTE_NEXT_ABI\n\t} else\n\t\t/* Free the mbuf that contains non-IPV4/IPV6 packet */\n\t\trte_pktmbuf_free(m);\n#else\n\t}\n#endif\n}\n\n#if ((APP_LOOKUP_METHOD == APP_LOOKUP_LPM) && \\\n\t(ENABLE_MULTI_BUFFER_OPTIMIZE == 1))\n#ifdef DO_RFC_1812_CHECKS\n\n#define\tIPV4_MIN_VER_IHL\t0x45\n#define\tIPV4_MAX_VER_IHL\t0x4f\n#define\tIPV4_MAX_VER_IHL_DIFF\t(IPV4_MAX_VER_IHL - IPV4_MIN_VER_IHL)\n\n/* Minimum value of IPV4 total length (20B) in network byte order. */\n#define\tIPV4_MIN_LEN_BE\t(sizeof(struct ipv4_hdr) << 8)\n\n/*\n * From http://www.rfc-editor.org/rfc/rfc1812.txt section 5.2.2:\n * - The IP version number must be 4.\n * - The IP header length field must be large enough to hold the\n * minimum length legal IP datagram (20 bytes = 5 words).\n * - The IP total length field must be large enough to hold the IP\n * datagram header, whose length is specified in the IP header length\n * field.\n * If we encounter invalid IPV4 packet, then set destination port for it\n * to BAD_PORT value.\n */\nstatic inline __attribute__((always_inline)) void\n#ifdef RTE_NEXT_ABI\nrfc1812_process(struct ipv4_hdr *ipv4_hdr, uint16_t *dp, uint32_t ptype)\n#else\nrfc1812_process(struct ipv4_hdr *ipv4_hdr, uint16_t *dp, uint32_t flags)\n#endif\n{\n\tuint8_t ihl;\n\n#ifdef RTE_NEXT_ABI\n\tif (RTE_ETH_IS_IPV4_HDR(ptype)) {\n#else\n\tif ((flags & PKT_RX_IPV4_HDR) != 0) {\n#endif\n\t\tihl = ipv4_hdr->version_ihl - IPV4_MIN_VER_IHL;\n\n\t\tipv4_hdr->time_to_live--;\n\t\tipv4_hdr->hdr_checksum++;\n\n\t\tif (ihl > IPV4_MAX_VER_IHL_DIFF ||\n\t\t\t\t((uint8_t)ipv4_hdr->total_length == 0 &&\n\t\t\t\tipv4_hdr->total_length < IPV4_MIN_LEN_BE)) {\n\t\t\tdp[0] = BAD_PORT;\n\t\t}\n\t}\n}\n\n#else\n#define\trfc1812_process(mb, dp)\tdo { } while (0)\n#endif /* DO_RFC_1812_CHECKS */\n#endif /* APP_LOOKUP_LPM && ENABLE_MULTI_BUFFER_OPTIMIZE */\n\n\n#if ((APP_LOOKUP_METHOD == APP_LOOKUP_LPM) && \\\n\t(ENABLE_MULTI_BUFFER_OPTIMIZE == 1))\n\nstatic inline __attribute__((always_inline)) uint16_t\nget_dst_port(const struct lcore_conf *qconf, struct rte_mbuf *pkt,\n\tuint32_t dst_ipv4, uint8_t portid)\n{\n\tuint8_t next_hop;\n\tstruct ipv6_hdr *ipv6_hdr;\n\tstruct ether_hdr *eth_hdr;\n\n#ifdef RTE_NEXT_ABI\n\tif (RTE_ETH_IS_IPV4_HDR(pkt->packet_type)) {\n#else\n\tif (pkt->ol_flags & PKT_RX_IPV4_HDR) {\n#endif\n\t\tif (rte_lpm_lookup(qconf->ipv4_lookup_struct, dst_ipv4,\n\t\t\t\t&next_hop) != 0)\n\t\t\tnext_hop = portid;\n#ifdef RTE_NEXT_ABI\n\t} else if (RTE_ETH_IS_IPV6_HDR(pkt->packet_type)) {\n#else\n\t} else if (pkt->ol_flags & PKT_RX_IPV6_HDR) {\n#endif\n\t\teth_hdr = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\t\tipv6_hdr = (struct ipv6_hdr *)(eth_hdr + 1);\n\t\tif (rte_lpm6_lookup(qconf->ipv6_lookup_struct,\n\t\t\t\tipv6_hdr->dst_addr, &next_hop) != 0)\n\t\t\tnext_hop = portid;\n\t} else {\n\t\tnext_hop = portid;\n\t}\n\n\treturn next_hop;\n}\n\nstatic inline void\nprocess_packet(struct lcore_conf *qconf, struct rte_mbuf *pkt,\n\tuint16_t *dst_port, uint8_t portid)\n{\n\tstruct ether_hdr *eth_hdr;\n\tstruct ipv4_hdr *ipv4_hdr;\n\tuint32_t dst_ipv4;\n\tuint16_t dp;\n\t__m128i te, ve;\n\n\teth_hdr = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\tipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1);\n\n\tdst_ipv4 = ipv4_hdr->dst_addr;\n\tdst_ipv4 = rte_be_to_cpu_32(dst_ipv4);\n\tdp = get_dst_port(qconf, pkt, dst_ipv4, portid);\n\n\tte = _mm_load_si128((__m128i *)eth_hdr);\n\tve = val_eth[dp];\n\n\tdst_port[0] = dp;\n#ifdef RTE_NEXT_ABI\n\trfc1812_process(ipv4_hdr, dst_port, pkt->packet_type);\n#else\n\trfc1812_process(ipv4_hdr, dst_port, pkt->ol_flags);\n#endif\n\n\tte = _mm_blend_epi16(te, ve, MASK_ETH);\n\t_mm_store_si128((__m128i *)eth_hdr, te);\n}\n\n#ifdef RTE_NEXT_ABI\n/*\n * Read packet_type and destination IPV4 addresses from 4 mbufs.\n */\nstatic inline void\nprocessx4_step1(struct rte_mbuf *pkt[FWDSTEP],\n\t\t__m128i *dip,\n\t\tuint32_t *ipv4_flag)\n{\n\tstruct ipv4_hdr *ipv4_hdr;\n\tstruct ether_hdr *eth_hdr;\n\tuint32_t x0, x1, x2, x3;\n\n\teth_hdr = rte_pktmbuf_mtod(pkt[0], struct ether_hdr *);\n\tipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1);\n\tx0 = ipv4_hdr->dst_addr;\n\tipv4_flag[0] = pkt[0]->packet_type & RTE_PTYPE_L3_IPV4;\n\n\teth_hdr = rte_pktmbuf_mtod(pkt[1], struct ether_hdr *);\n\tipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1);\n\tx1 = ipv4_hdr->dst_addr;\n\tipv4_flag[0] &= pkt[1]->packet_type;\n\n\teth_hdr = rte_pktmbuf_mtod(pkt[2], struct ether_hdr *);\n\tipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1);\n\tx2 = ipv4_hdr->dst_addr;\n\tipv4_flag[0] &= pkt[2]->packet_type;\n\n\teth_hdr = rte_pktmbuf_mtod(pkt[3], struct ether_hdr *);\n\tipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1);\n\tx3 = ipv4_hdr->dst_addr;\n\tipv4_flag[0] &= pkt[3]->packet_type;\n\n\tdip[0] = _mm_set_epi32(x3, x2, x1, x0);\n}\n#else /* RTE_NEXT_ABI */\n/*\n * Read ol_flags and destination IPV4 addresses from 4 mbufs.\n */\nstatic inline void\nprocessx4_step1(struct rte_mbuf *pkt[FWDSTEP], __m128i *dip, uint32_t *flag)\n{\n\tstruct ipv4_hdr *ipv4_hdr;\n\tstruct ether_hdr *eth_hdr;\n\tuint32_t x0, x1, x2, x3;\n\n\teth_hdr = rte_pktmbuf_mtod(pkt[0], struct ether_hdr *);\n\tipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1);\n\tx0 = ipv4_hdr->dst_addr;\n\tflag[0] = pkt[0]->ol_flags & PKT_RX_IPV4_HDR;\n\n\teth_hdr = rte_pktmbuf_mtod(pkt[1], struct ether_hdr *);\n\tipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1);\n\tx1 = ipv4_hdr->dst_addr;\n\tflag[0] &= pkt[1]->ol_flags;\n\n\teth_hdr = rte_pktmbuf_mtod(pkt[2], struct ether_hdr *);\n\tipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1);\n\tx2 = ipv4_hdr->dst_addr;\n\tflag[0] &= pkt[2]->ol_flags;\n\n\teth_hdr = rte_pktmbuf_mtod(pkt[3], struct ether_hdr *);\n\tipv4_hdr = (struct ipv4_hdr *)(eth_hdr + 1);\n\tx3 = ipv4_hdr->dst_addr;\n\tflag[0] &= pkt[3]->ol_flags;\n\n\tdip[0] = _mm_set_epi32(x3, x2, x1, x0);\n}\n#endif /* RTE_NEXT_ABI */\n\n/*\n * Lookup into LPM for destination port.\n * If lookup fails, use incoming port (portid) as destination port.\n */\nstatic inline void\n#ifdef RTE_NEXT_ABI\nprocessx4_step2(const struct lcore_conf *qconf,\n\t\t__m128i dip,\n\t\tuint32_t ipv4_flag,\n\t\tuint8_t portid,\n\t\tstruct rte_mbuf *pkt[FWDSTEP],\n\t\tuint16_t dprt[FWDSTEP])\n#else\nprocessx4_step2(const struct lcore_conf *qconf, __m128i dip, uint32_t flag,\n\tuint8_t portid, struct rte_mbuf *pkt[FWDSTEP], uint16_t dprt[FWDSTEP])\n#endif /* RTE_NEXT_ABI */\n{\n\trte_xmm_t dst;\n\tconst __m128i bswap_mask = _mm_set_epi8(12, 13, 14, 15, 8, 9, 10, 11,\n\t\t\t\t\t\t4, 5, 6, 7, 0, 1, 2, 3);\n\n\t/* Byte swap 4 IPV4 addresses. */\n\tdip = _mm_shuffle_epi8(dip, bswap_mask);\n\n\t/* if all 4 packets are IPV4. */\n#ifdef RTE_NEXT_ABI\n\tif (likely(ipv4_flag)) {\n#else\n\tif (likely(flag != 0)) {\n#endif\n\t\trte_lpm_lookupx4(qconf->ipv4_lookup_struct, dip, dprt, portid);\n\t} else {\n\t\tdst.x = dip;\n\t\tdprt[0] = get_dst_port(qconf, pkt[0], dst.u32[0], portid);\n\t\tdprt[1] = get_dst_port(qconf, pkt[1], dst.u32[1], portid);\n\t\tdprt[2] = get_dst_port(qconf, pkt[2], dst.u32[2], portid);\n\t\tdprt[3] = get_dst_port(qconf, pkt[3], dst.u32[3], portid);\n\t}\n}\n\n/*\n * Update source and destination MAC addresses in the ethernet header.\n * Perform RFC1812 checks and updates for IPV4 packets.\n */\nstatic inline void\nprocessx4_step3(struct rte_mbuf *pkt[FWDSTEP], uint16_t dst_port[FWDSTEP])\n{\n\t__m128i te[FWDSTEP];\n\t__m128i ve[FWDSTEP];\n\t__m128i *p[FWDSTEP];\n\n\tp[0] = rte_pktmbuf_mtod(pkt[0], __m128i *);\n\tp[1] = rte_pktmbuf_mtod(pkt[1], __m128i *);\n\tp[2] = rte_pktmbuf_mtod(pkt[2], __m128i *);\n\tp[3] = rte_pktmbuf_mtod(pkt[3], __m128i *);\n\n\tve[0] = val_eth[dst_port[0]];\n\tte[0] = _mm_load_si128(p[0]);\n\n\tve[1] = val_eth[dst_port[1]];\n\tte[1] = _mm_load_si128(p[1]);\n\n\tve[2] = val_eth[dst_port[2]];\n\tte[2] = _mm_load_si128(p[2]);\n\n\tve[3] = val_eth[dst_port[3]];\n\tte[3] = _mm_load_si128(p[3]);\n\n\t/* Update first 12 bytes, keep rest bytes intact. */\n\tte[0] = _mm_blend_epi16(te[0], ve[0], MASK_ETH);\n\tte[1] = _mm_blend_epi16(te[1], ve[1], MASK_ETH);\n\tte[2] = _mm_blend_epi16(te[2], ve[2], MASK_ETH);\n\tte[3] = _mm_blend_epi16(te[3], ve[3], MASK_ETH);\n\n\t_mm_store_si128(p[0], te[0]);\n\t_mm_store_si128(p[1], te[1]);\n\t_mm_store_si128(p[2], te[2]);\n\t_mm_store_si128(p[3], te[3]);\n\n#ifdef RTE_NEXT_ABI\n\trfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[0] + 1),\n\t\t&dst_port[0], pkt[0]->packet_type);\n\trfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[1] + 1),\n\t\t&dst_port[1], pkt[1]->packet_type);\n\trfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[2] + 1),\n\t\t&dst_port[2], pkt[2]->packet_type);\n\trfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[3] + 1),\n\t\t&dst_port[3], pkt[3]->packet_type);\n#else /* RTE_NEXT_ABI */\n\trfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[0] + 1),\n\t\t&dst_port[0], pkt[0]->ol_flags);\n\trfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[1] + 1),\n\t\t&dst_port[1], pkt[1]->ol_flags);\n\trfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[2] + 1),\n\t\t&dst_port[2], pkt[2]->ol_flags);\n\trfc1812_process((struct ipv4_hdr *)((struct ether_hdr *)p[3] + 1),\n\t\t&dst_port[3], pkt[3]->ol_flags);\n#endif /* RTE_NEXT_ABI */\n}\n\n/*\n * We group consecutive packets with the same destionation port into one burst.\n * To avoid extra latency this is done together with some other packet\n * processing, but after we made a final decision about packet's destination.\n * To do this we maintain:\n * pnum - array of number of consecutive packets with the same dest port for\n * each packet in the input burst.\n * lp - pointer to the last updated element in the pnum.\n * dlp - dest port value lp corresponds to.\n */\n\n#define\tGRPSZ\t(1 << FWDSTEP)\n#define\tGRPMSK\t(GRPSZ - 1)\n\n#define GROUP_PORT_STEP(dlp, dcp, lp, pn, idx)\tdo { \\\n\tif (likely((dlp) == (dcp)[(idx)])) { \\\n\t\t(lp)[0]++; \\\n\t} else { \\\n\t\t(dlp) = (dcp)[idx]; \\\n\t\t(lp) = (pn) + (idx); \\\n\t\t(lp)[0] = 1; \\\n\t} \\\n} while (0)\n\n/*\n * Group consecutive packets with the same destination port in bursts of 4.\n * Suppose we have array of destionation ports:\n * dst_port[] = {a, b, c, d,, e, ... }\n * dp1 should contain: , dp2: .\n * We doing 4 comparisions at once and the result is 4 bit mask.\n * This mask is used as an index into prebuild array of pnum values.\n */\nstatic inline uint16_t *\nport_groupx4(uint16_t pn[FWDSTEP + 1], uint16_t *lp, __m128i dp1, __m128i dp2)\n{\n\tstatic const struct {\n\t\tuint64_t pnum; /* prebuild 4 values for pnum[]. */\n\t\tint32_t idx; /* index for new last updated elemnet. */\n\t\tuint16_t lpv; /* add value to the last updated element. */\n\t} gptbl[GRPSZ] = {\n\t{\n\t\t/* 0: a != b, b != c, c != d, d != e */\n\t\t.pnum = UINT64_C(0x0001000100010001),\n\t\t.idx = 4,\n\t\t.lpv = 0,\n\t},\n\t{\n\t\t/* 1: a == b, b != c, c != d, d != e */\n\t\t.pnum = UINT64_C(0x0001000100010002),\n\t\t.idx = 4,\n\t\t.lpv = 1,\n\t},\n\t{\n\t\t/* 2: a != b, b == c, c != d, d != e */\n\t\t.pnum = UINT64_C(0x0001000100020001),\n\t\t.idx = 4,\n\t\t.lpv = 0,\n\t},\n\t{\n\t\t/* 3: a == b, b == c, c != d, d != e */\n\t\t.pnum = UINT64_C(0x0001000100020003),\n\t\t.idx = 4,\n\t\t.lpv = 2,\n\t},\n\t{\n\t\t/* 4: a != b, b != c, c == d, d != e */\n\t\t.pnum = UINT64_C(0x0001000200010001),\n\t\t.idx = 4,\n\t\t.lpv = 0,\n\t},\n\t{\n\t\t/* 5: a == b, b != c, c == d, d != e */\n\t\t.pnum = UINT64_C(0x0001000200010002),\n\t\t.idx = 4,\n\t\t.lpv = 1,\n\t},\n\t{\n\t\t/* 6: a != b, b == c, c == d, d != e */\n\t\t.pnum = UINT64_C(0x0001000200030001),\n\t\t.idx = 4,\n\t\t.lpv = 0,\n\t},\n\t{\n\t\t/* 7: a == b, b == c, c == d, d != e */\n\t\t.pnum = UINT64_C(0x0001000200030004),\n\t\t.idx = 4,\n\t\t.lpv = 3,\n\t},\n\t{\n\t\t/* 8: a != b, b != c, c != d, d == e */\n\t\t.pnum = UINT64_C(0x0002000100010001),\n\t\t.idx = 3,\n\t\t.lpv = 0,\n\t},\n\t{\n\t\t/* 9: a == b, b != c, c != d, d == e */\n\t\t.pnum = UINT64_C(0x0002000100010002),\n\t\t.idx = 3,\n\t\t.lpv = 1,\n\t},\n\t{\n\t\t/* 0xa: a != b, b == c, c != d, d == e */\n\t\t.pnum = UINT64_C(0x0002000100020001),\n\t\t.idx = 3,\n\t\t.lpv = 0,\n\t},\n\t{\n\t\t/* 0xb: a == b, b == c, c != d, d == e */\n\t\t.pnum = UINT64_C(0x0002000100020003),\n\t\t.idx = 3,\n\t\t.lpv = 2,\n\t},\n\t{\n\t\t/* 0xc: a != b, b != c, c == d, d == e */\n\t\t.pnum = UINT64_C(0x0002000300010001),\n\t\t.idx = 2,\n\t\t.lpv = 0,\n\t},\n\t{\n\t\t/* 0xd: a == b, b != c, c == d, d == e */\n\t\t.pnum = UINT64_C(0x0002000300010002),\n\t\t.idx = 2,\n\t\t.lpv = 1,\n\t},\n\t{\n\t\t/* 0xe: a != b, b == c, c == d, d == e */\n\t\t.pnum = UINT64_C(0x0002000300040001),\n\t\t.idx = 1,\n\t\t.lpv = 0,\n\t},\n\t{\n\t\t/* 0xf: a == b, b == c, c == d, d == e */\n\t\t.pnum = UINT64_C(0x0002000300040005),\n\t\t.idx = 0,\n\t\t.lpv = 4,\n\t},\n\t};\n\n\tunion {\n\t\tuint16_t u16[FWDSTEP + 1];\n\t\tuint64_t u64;\n\t} *pnum = (void *)pn;\n\n\tint32_t v;\n\n\tdp1 = _mm_cmpeq_epi16(dp1, dp2);\n\tdp1 = _mm_unpacklo_epi16(dp1, dp1);\n\tv = _mm_movemask_ps((__m128)dp1);\n\n\t/* update last port counter. */\n\tlp[0] += gptbl[v].lpv;\n\n\t/* if dest port value has changed. */\n\tif (v != GRPMSK) {\n\t\tlp = pnum->u16 + gptbl[v].idx;\n\t\tlp[0] = 1;\n\t\tpnum->u64 = gptbl[v].pnum;\n\t}\n\n\treturn lp;\n}\n\n#endif /* APP_LOOKUP_METHOD */\n\n/* main processing loop */\nstatic int\nmain_loop(__attribute__((unused)) void *dummy)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tunsigned lcore_id;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc;\n\tint i, j, nb_rx;\n\tuint8_t portid, queueid;\n\tstruct lcore_conf *qconf;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) /\n\t\tUS_PER_S * BURST_TX_DRAIN_US;\n\n#if ((APP_LOOKUP_METHOD == APP_LOOKUP_LPM) && \\\n\t(ENABLE_MULTI_BUFFER_OPTIMIZE == 1))\n\tint32_t k;\n\tuint16_t dlp;\n\tuint16_t *lp;\n\tuint16_t dst_port[MAX_PKT_BURST];\n\t__m128i dip[MAX_PKT_BURST / FWDSTEP];\n#ifdef RTE_NEXT_ABI\n\tuint32_t ipv4_flag[MAX_PKT_BURST / FWDSTEP];\n#else\n\tuint32_t flag[MAX_PKT_BURST / FWDSTEP];\n#endif\n\tuint16_t pnum[MAX_PKT_BURST + 1];\n#endif\n\n\tprev_tsc = 0;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_conf[lcore_id];\n\n\tif (qconf->n_rx_queue == 0) {\n\t\tRTE_LOG(INFO, L3FWD, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn 0;\n\t}\n\n\tRTE_LOG(INFO, L3FWD, \"entering main loop on lcore %u\\n\", lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_queue; i++) {\n\n\t\tportid = qconf->rx_queue_list[i].port_id;\n\t\tqueueid = qconf->rx_queue_list[i].queue_id;\n\t\tRTE_LOG(INFO, L3FWD, \" -- lcoreid=%u portid=%hhu rxqueueid=%hhu\\n\", lcore_id,\n\t\t\tportid, queueid);\n\t}\n\n\twhile (1) {\n\n\t\tcur_tsc = rte_rdtsc();\n\n\t\t/*\n\t\t * TX burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\t/*\n\t\t\t * This could be optimized (use queueid instead of\n\t\t\t * portid), but it is not called so often\n\t\t\t */\n\t\t\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t\t\tif (qconf->tx_mbufs[portid].len == 0)\n\t\t\t\t\tcontinue;\n\t\t\t\tsend_burst(qconf,\n\t\t\t\t\tqconf->tx_mbufs[portid].len,\n\t\t\t\t\tportid);\n\t\t\t\tqconf->tx_mbufs[portid].len = 0;\n\t\t\t}\n\n\t\t\tprev_tsc = cur_tsc;\n\t\t}\n\n\t\t/*\n\t\t * Read packet from RX queues\n\t\t */\n\t\tfor (i = 0; i < qconf->n_rx_queue; ++i) {\n\t\t\tportid = qconf->rx_queue_list[i].port_id;\n\t\t\tqueueid = qconf->rx_queue_list[i].queue_id;\n\t\t\tnb_rx = rte_eth_rx_burst(portid, queueid, pkts_burst,\n\t\t\t\tMAX_PKT_BURST);\n\t\t\tif (nb_rx == 0)\n\t\t\t\tcontinue;\n\n#if (ENABLE_MULTI_BUFFER_OPTIMIZE == 1)\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n\t\t\t{\n\t\t\t\t/*\n\t\t\t\t * Send nb_rx - nb_rx%8 packets\n\t\t\t\t * in groups of 8.\n\t\t\t\t */\n\t\t\t\tint32_t n = RTE_ALIGN_FLOOR(nb_rx, 8);\n\t\t\t\tfor (j = 0; j < n; j += 8) {\n#ifdef RTE_NEXT_ABI\n\t\t\t\t\tuint32_t pkt_type =\n\t\t\t\t\t\tpkts_burst[j]->packet_type &\n\t\t\t\t\t\tpkts_burst[j+1]->packet_type &\n\t\t\t\t\t\tpkts_burst[j+2]->packet_type &\n\t\t\t\t\t\tpkts_burst[j+3]->packet_type &\n\t\t\t\t\t\tpkts_burst[j+4]->packet_type &\n\t\t\t\t\t\tpkts_burst[j+5]->packet_type &\n\t\t\t\t\t\tpkts_burst[j+6]->packet_type &\n\t\t\t\t\t\tpkts_burst[j+7]->packet_type;\n\t\t\t\t\tif (pkt_type & RTE_PTYPE_L3_IPV4) {\n\t\t\t\t\t\tsimple_ipv4_fwd_8pkts(\n\t\t\t\t\t\t&pkts_burst[j], portid, qconf);\n\t\t\t\t\t} else if (pkt_type &\n\t\t\t\t\t\tRTE_PTYPE_L3_IPV6) {\n#else /* RTE_NEXT_ABI */\n\t\t\t\t\tuint32_t ol_flag = pkts_burst[j]->ol_flags\n\t\t\t\t\t\t\t& pkts_burst[j+1]->ol_flags\n\t\t\t\t\t\t\t& pkts_burst[j+2]->ol_flags\n\t\t\t\t\t\t\t& pkts_burst[j+3]->ol_flags\n\t\t\t\t\t\t\t& pkts_burst[j+4]->ol_flags\n\t\t\t\t\t\t\t& pkts_burst[j+5]->ol_flags\n\t\t\t\t\t\t\t& pkts_burst[j+6]->ol_flags\n\t\t\t\t\t\t\t& pkts_burst[j+7]->ol_flags;\n\t\t\t\t\tif (ol_flag & PKT_RX_IPV4_HDR ) {\n\t\t\t\t\t\tsimple_ipv4_fwd_8pkts(&pkts_burst[j],\n\t\t\t\t\t\t\t\t\tportid, qconf);\n\t\t\t\t\t} else if (ol_flag & PKT_RX_IPV6_HDR) {\n#endif /* RTE_NEXT_ABI */\n\t\t\t\t\t\tsimple_ipv6_fwd_8pkts(&pkts_burst[j],\n\t\t\t\t\t\t\t\t\tportid, qconf);\n\t\t\t\t\t} else {\n\t\t\t\t\t\tl3fwd_simple_forward(pkts_burst[j],\n\t\t\t\t\t\t\t\t\tportid, qconf);\n\t\t\t\t\t\tl3fwd_simple_forward(pkts_burst[j+1],\n\t\t\t\t\t\t\t\t\tportid, qconf);\n\t\t\t\t\t\tl3fwd_simple_forward(pkts_burst[j+2],\n\t\t\t\t\t\t\t\t\tportid, qconf);\n\t\t\t\t\t\tl3fwd_simple_forward(pkts_burst[j+3],\n\t\t\t\t\t\t\t\t\tportid, qconf);\n\t\t\t\t\t\tl3fwd_simple_forward(pkts_burst[j+4],\n\t\t\t\t\t\t\t\t\tportid, qconf);\n\t\t\t\t\t\tl3fwd_simple_forward(pkts_burst[j+5],\n\t\t\t\t\t\t\t\t\tportid, qconf);\n\t\t\t\t\t\tl3fwd_simple_forward(pkts_burst[j+6],\n\t\t\t\t\t\t\t\t\tportid, qconf);\n\t\t\t\t\t\tl3fwd_simple_forward(pkts_burst[j+7],\n\t\t\t\t\t\t\t\t\tportid, qconf);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tfor (; j < nb_rx ; j++) {\n\t\t\t\t\tl3fwd_simple_forward(pkts_burst[j],\n\t\t\t\t\t\t\t\tportid, qconf);\n\t\t\t\t}\n\t\t\t}\n#elif (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\n\n\t\t\tk = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP);\n\t\t\tfor (j = 0; j != k; j += FWDSTEP) {\n\t\t\t\tprocessx4_step1(&pkts_burst[j],\n\t\t\t\t\t&dip[j / FWDSTEP],\n#ifdef RTE_NEXT_ABI\n\t\t\t\t\t&ipv4_flag[j / FWDSTEP]);\n#else\n\t\t\t\t\t&flag[j / FWDSTEP]);\n#endif\n\t\t\t}\n\n\t\t\tk = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP);\n\t\t\tfor (j = 0; j != k; j += FWDSTEP) {\n\t\t\t\tprocessx4_step2(qconf, dip[j / FWDSTEP],\n#ifdef RTE_NEXT_ABI\n\t\t\t\t\tipv4_flag[j / FWDSTEP], portid,\n#else\n\t\t\t\t\tflag[j / FWDSTEP], portid,\n#endif\n\t\t\t\t\t&pkts_burst[j], &dst_port[j]);\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Finish packet processing and group consecutive\n\t\t\t * packets with the same destination port.\n\t\t\t */\n\t\t\tk = RTE_ALIGN_FLOOR(nb_rx, FWDSTEP);\n\t\t\tif (k != 0) {\n\t\t\t\t__m128i dp1, dp2;\n\n\t\t\t\tlp = pnum;\n\t\t\t\tlp[0] = 1;\n\n\t\t\t\tprocessx4_step3(pkts_burst, dst_port);\n\n\t\t\t\t/* dp1: */\n\t\t\t\tdp1 = _mm_loadu_si128((__m128i *)dst_port);\n\n\t\t\t\tfor (j = FWDSTEP; j != k; j += FWDSTEP) {\n\t\t\t\t\tprocessx4_step3(&pkts_burst[j],\n\t\t\t\t\t\t&dst_port[j]);\n\n\t\t\t\t\t/*\n\t\t\t\t\t * dp2:\n\t\t\t\t\t * \n\t\t\t\t\t */\n\t\t\t\t\tdp2 = _mm_loadu_si128((__m128i *)\n\t\t\t\t\t\t&dst_port[j - FWDSTEP + 1]);\n\t\t\t\t\tlp = port_groupx4(&pnum[j - FWDSTEP],\n\t\t\t\t\t\tlp, dp1, dp2);\n\n\t\t\t\t\t/*\n\t\t\t\t\t * dp1:\n\t\t\t\t\t * \n\t\t\t\t\t */\n\t\t\t\t\tdp1 = _mm_srli_si128(dp2,\n\t\t\t\t\t\t(FWDSTEP - 1) *\n\t\t\t\t\t\tsizeof(dst_port[0]));\n\t\t\t\t}\n\n\t\t\t\t/*\n\t\t\t\t * dp2: \n\t\t\t\t */\n\t\t\t\tdp2 = _mm_shufflelo_epi16(dp1, 0xf9);\n\t\t\t\tlp = port_groupx4(&pnum[j - FWDSTEP], lp,\n\t\t\t\t\tdp1, dp2);\n\n\t\t\t\t/*\n\t\t\t\t * remove values added by the last repeated\n\t\t\t\t * dst port.\n\t\t\t\t */\n\t\t\t\tlp[0]--;\n\t\t\t\tdlp = dst_port[j - 1];\n\t\t\t} else {\n\t\t\t\t/* set dlp and lp to the never used values. */\n\t\t\t\tdlp = BAD_PORT - 1;\n\t\t\t\tlp = pnum + MAX_PKT_BURST;\n\t\t\t}\n\n\t\t\t/* Process up to last 3 packets one by one. */\n\t\t\tswitch (nb_rx % FWDSTEP) {\n\t\t\tcase 3:\n\t\t\t\tprocess_packet(qconf, pkts_burst[j],\n\t\t\t\t\tdst_port + j, portid);\n\t\t\t\tGROUP_PORT_STEP(dlp, dst_port, lp, pnum, j);\n\t\t\t\tj++;\n\t\t\tcase 2:\n\t\t\t\tprocess_packet(qconf, pkts_burst[j],\n\t\t\t\t\tdst_port + j, portid);\n\t\t\t\tGROUP_PORT_STEP(dlp, dst_port, lp, pnum, j);\n\t\t\t\tj++;\n\t\t\tcase 1:\n\t\t\t\tprocess_packet(qconf, pkts_burst[j],\n\t\t\t\t\tdst_port + j, portid);\n\t\t\t\tGROUP_PORT_STEP(dlp, dst_port, lp, pnum, j);\n\t\t\t\tj++;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Send packets out, through destination port.\n\t\t\t * Consecuteve pacekts with the same destination port\n\t\t\t * are already grouped together.\n\t\t\t * If destination port for the packet equals BAD_PORT,\n\t\t\t * then free the packet without sending it out.\n\t\t\t */\n\t\t\tfor (j = 0; j < nb_rx; j += k) {\n\n\t\t\t\tint32_t m;\n\t\t\t\tuint16_t pn;\n\n\t\t\t\tpn = dst_port[j];\n\t\t\t\tk = pnum[j];\n\n\t\t\t\tif (likely(pn != BAD_PORT)) {\n\t\t\t\t\tsend_packetsx4(qconf, pn,\n\t\t\t\t\t\tpkts_burst + j, k);\n\t\t\t\t} else {\n\t\t\t\t\tfor (m = j; m != j + k; m++)\n\t\t\t\t\t\trte_pktmbuf_free(pkts_burst[m]);\n\t\t\t\t}\n\t\t\t}\n\n#endif /* APP_LOOKUP_METHOD */\n#else /* ENABLE_MULTI_BUFFER_OPTIMIZE == 0 */\n\n\t\t\t/* Prefetch first packets */\n\t\t\tfor (j = 0; j < PREFETCH_OFFSET && j < nb_rx; j++) {\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(\n\t\t\t\t\t\tpkts_burst[j], void *));\n\t\t\t}\n\n\t\t\t/* Prefetch and forward already prefetched packets */\n\t\t\tfor (j = 0; j < (nb_rx - PREFETCH_OFFSET); j++) {\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(pkts_burst[\n\t\t\t\t\t\tj + PREFETCH_OFFSET], void *));\n\t\t\t\tl3fwd_simple_forward(pkts_burst[j], portid,\n\t\t\t\t\tqconf);\n\t\t\t}\n\n\t\t\t/* Forward remaining prefetched packets */\n\t\t\tfor (; j < nb_rx; j++) {\n\t\t\t\tl3fwd_simple_forward(pkts_burst[j], portid,\n\t\t\t\t\tqconf);\n\t\t\t}\n#endif /* ENABLE_MULTI_BUFFER_OPTIMIZE */\n\n\t\t}\n\t}\n}\n\nstatic int\ncheck_lcore_params(void)\n{\n\tuint8_t queue, lcore;\n\tuint16_t i;\n\tint socketid;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tqueue = lcore_params[i].queue_id;\n\t\tif (queue >= MAX_RX_QUEUE_PER_PORT) {\n\t\t\tprintf(\"invalid queue number: %hhu\\n\", queue);\n\t\t\treturn -1;\n\t\t}\n\t\tlcore = lcore_params[i].lcore_id;\n\t\tif (!rte_lcore_is_enabled(lcore)) {\n\t\t\tprintf(\"error: lcore %hhu is not enabled in lcore mask\\n\", lcore);\n\t\t\treturn -1;\n\t\t}\n\t\tif ((socketid = rte_lcore_to_socket_id(lcore) != 0) &&\n\t\t\t(numa_on == 0)) {\n\t\t\tprintf(\"warning: lcore %hhu is on socket %d with numa off \\n\",\n\t\t\t\tlcore, socketid);\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\ncheck_port_config(const unsigned nb_ports)\n{\n\tunsigned portid;\n\tuint16_t i;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tportid = lcore_params[i].port_id;\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"port %u is not enabled in port mask\\n\", portid);\n\t\t\treturn -1;\n\t\t}\n\t\tif (portid >= nb_ports) {\n\t\t\tprintf(\"port %u is not present on the board\\n\", portid);\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic uint8_t\nget_port_n_rx_queues(const uint8_t port)\n{\n\tint queue = -1;\n\tuint16_t i;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tif (lcore_params[i].port_id == port && lcore_params[i].queue_id > queue)\n\t\t\tqueue = lcore_params[i].queue_id;\n\t}\n\treturn (uint8_t)(++queue);\n}\n\nstatic int\ninit_lcore_rx_queues(void)\n{\n\tuint16_t i, nb_rx_queue;\n\tuint8_t lcore;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tlcore = lcore_params[i].lcore_id;\n\t\tnb_rx_queue = lcore_conf[lcore].n_rx_queue;\n\t\tif (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) {\n\t\t\tprintf(\"error: too many queues (%u) for lcore: %u\\n\",\n\t\t\t\t(unsigned)nb_rx_queue + 1, (unsigned)lcore);\n\t\t\treturn -1;\n\t\t} else {\n\t\t\tlcore_conf[lcore].rx_queue_list[nb_rx_queue].port_id =\n\t\t\t\tlcore_params[i].port_id;\n\t\t\tlcore_conf[lcore].rx_queue_list[nb_rx_queue].queue_id =\n\t\t\t\tlcore_params[i].queue_id;\n\t\t\tlcore_conf[lcore].n_rx_queue++;\n\t\t}\n\t}\n\treturn 0;\n}\n\n/* display usage */\nstatic void\nprint_usage(const char *prgname)\n{\n\tprintf (\"%s [EAL options] -- -p PORTMASK -P\"\n\t\t\" [--config (port,queue,lcore)[,(port,queue,lcore]]\"\n\t\t\" [--enable-jumbo [--max-pkt-len PKTLEN]]\\n\"\n\t\t\" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t\t\" -P : enable promiscuous mode\\n\"\n\t\t\" --config (port,queue,lcore): rx queues configuration\\n\"\n\t\t\" --eth-dest=X,MM:MM:MM:MM:MM:MM: optional, ethernet destination for port X\\n\"\n\t\t\" --no-numa: optional, disable numa awareness\\n\"\n\t\t\" --ipv6: optional, specify it if running ipv6 packets\\n\"\n\t\t\" --enable-jumbo: enable jumbo frame\"\n\t\t\" which max packet len is PKTLEN in decimal (64-9600)\\n\"\n\t\t\" --hash-entry-num: specify the hash entry number in hexadecimal to be setup\\n\",\n\t\tprgname);\n}\n\nstatic int parse_max_pkt_len(const char *pktlen)\n{\n\tchar *end = NULL;\n\tunsigned long len;\n\n\t/* parse decimal string */\n\tlen = strtoul(pktlen, &end, 10);\n\tif ((pktlen[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (len == 0)\n\t\treturn -1;\n\n\treturn len;\n}\n\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\nstatic int\nparse_hash_entry_number(const char *hash_entry_num)\n{\n\tchar *end = NULL;\n\tunsigned long hash_en;\n\t/* parse hexadecimal string */\n\thash_en = strtoul(hash_entry_num, &end, 16);\n\tif ((hash_entry_num[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (hash_en == 0)\n\t\treturn -1;\n\n\treturn hash_en;\n}\n#endif\n\nstatic int\nparse_config(const char *q_arg)\n{\n\tchar s[256];\n\tconst char *p, *p0 = q_arg;\n\tchar *end;\n\tenum fieldnames {\n\t\tFLD_PORT = 0,\n\t\tFLD_QUEUE,\n\t\tFLD_LCORE,\n\t\t_NUM_FLD\n\t};\n\tunsigned long int_fld[_NUM_FLD];\n\tchar *str_fld[_NUM_FLD];\n\tint i;\n\tunsigned size;\n\n\tnb_lcore_params = 0;\n\n\twhile ((p = strchr(p0,'(')) != NULL) {\n\t\t++p;\n\t\tif((p0 = strchr(p,')')) == NULL)\n\t\t\treturn -1;\n\n\t\tsize = p0 - p;\n\t\tif(size >= sizeof(s))\n\t\t\treturn -1;\n\n\t\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\t\tif (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') != _NUM_FLD)\n\t\t\treturn -1;\n\t\tfor (i = 0; i < _NUM_FLD; i++){\n\t\t\terrno = 0;\n\t\t\tint_fld[i] = strtoul(str_fld[i], &end, 0);\n\t\t\tif (errno != 0 || end == str_fld[i] || int_fld[i] > 255)\n\t\t\t\treturn -1;\n\t\t}\n\t\tif (nb_lcore_params >= MAX_LCORE_PARAMS) {\n\t\t\tprintf(\"exceeded max number of lcore params: %hu\\n\",\n\t\t\t\tnb_lcore_params);\n\t\t\treturn -1;\n\t\t}\n\t\tlcore_params_array[nb_lcore_params].port_id = (uint8_t)int_fld[FLD_PORT];\n\t\tlcore_params_array[nb_lcore_params].queue_id = (uint8_t)int_fld[FLD_QUEUE];\n\t\tlcore_params_array[nb_lcore_params].lcore_id = (uint8_t)int_fld[FLD_LCORE];\n\t\t++nb_lcore_params;\n\t}\n\tlcore_params = lcore_params_array;\n\treturn 0;\n}\n\nstatic void\nparse_eth_dest(const char *optarg)\n{\n\tuint8_t portid;\n\tchar *port_end;\n\tuint8_t c, *dest, peer_addr[6];\n\n\terrno = 0;\n\tportid = strtoul(optarg, &port_end, 10);\n\tif (errno != 0 || port_end == optarg || *port_end++ != ',')\n\t\trte_exit(EXIT_FAILURE,\n\t\t\"Invalid eth-dest: %s\", optarg);\n\tif (portid >= RTE_MAX_ETHPORTS)\n\t\trte_exit(EXIT_FAILURE,\n\t\t\"eth-dest: port %d >= RTE_MAX_ETHPORTS(%d)\\n\",\n\t\tportid, RTE_MAX_ETHPORTS);\n\n\tif (cmdline_parse_etheraddr(NULL, port_end,\n\t\t&peer_addr, sizeof(peer_addr)) < 0)\n\t\trte_exit(EXIT_FAILURE,\n\t\t\"Invalid ethernet address: %s\\n\",\n\t\tport_end);\n\tdest = (uint8_t *)&dest_eth_addr[portid];\n\tfor (c = 0; c < 6; c++)\n\t\tdest[c] = peer_addr[c];\n\t*(uint64_t *)(val_eth + portid) = dest_eth_addr[portid];\n}\n\n#define CMD_LINE_OPT_CONFIG \"config\"\n#define CMD_LINE_OPT_ETH_DEST \"eth-dest\"\n#define CMD_LINE_OPT_NO_NUMA \"no-numa\"\n#define CMD_LINE_OPT_IPV6 \"ipv6\"\n#define CMD_LINE_OPT_ENABLE_JUMBO \"enable-jumbo\"\n#define CMD_LINE_OPT_HASH_ENTRY_NUM \"hash-entry-num\"\n\n/* Parse the argument given in the command line of the application */\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{CMD_LINE_OPT_CONFIG, 1, 0, 0},\n\t\t{CMD_LINE_OPT_ETH_DEST, 1, 0, 0},\n\t\t{CMD_LINE_OPT_NO_NUMA, 0, 0, 0},\n\t\t{CMD_LINE_OPT_IPV6, 0, 0, 0},\n\t\t{CMD_LINE_OPT_ENABLE_JUMBO, 0, 0, 0},\n\t\t{CMD_LINE_OPT_HASH_ENTRY_NUM, 1, 0, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:P\",\n\t\t\t\tlgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'P':\n\t\t\tprintf(\"Promiscuous mode selected\\n\");\n\t\t\tpromiscuous_on = 1;\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tif (!strncmp(lgopts[option_index].name, CMD_LINE_OPT_CONFIG,\n\t\t\t\tsizeof (CMD_LINE_OPT_CONFIG))) {\n\t\t\t\tret = parse_config(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"invalid config\\n\");\n\t\t\t\t\tprint_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (!strncmp(lgopts[option_index].name, CMD_LINE_OPT_ETH_DEST,\n\t\t\t\tsizeof(CMD_LINE_OPT_CONFIG))) {\n\t\t\t\t\tparse_eth_dest(optarg);\n\t\t\t}\n\n\t\t\tif (!strncmp(lgopts[option_index].name, CMD_LINE_OPT_NO_NUMA,\n\t\t\t\tsizeof(CMD_LINE_OPT_NO_NUMA))) {\n\t\t\t\tprintf(\"numa is disabled \\n\");\n\t\t\t\tnuma_on = 0;\n\t\t\t}\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n\t\t\tif (!strncmp(lgopts[option_index].name, CMD_LINE_OPT_IPV6,\n\t\t\t\tsizeof(CMD_LINE_OPT_IPV6))) {\n\t\t\t\tprintf(\"ipv6 is specified \\n\");\n\t\t\t\tipv6 = 1;\n\t\t\t}\n#endif\n\n\t\t\tif (!strncmp(lgopts[option_index].name, CMD_LINE_OPT_ENABLE_JUMBO,\n\t\t\t\tsizeof (CMD_LINE_OPT_ENABLE_JUMBO))) {\n\t\t\t\tstruct option lenopts = {\"max-pkt-len\", required_argument, 0, 0};\n\n\t\t\t\tprintf(\"jumbo frame is enabled - disabling simple TX path\\n\");\n\t\t\t\tport_conf.rxmode.jumbo_frame = 1;\n\n\t\t\t\t/* if no max-pkt-len set, use the default value ETHER_MAX_LEN */\n\t\t\t\tif (0 == getopt_long(argc, argvopt, \"\", &lenopts, &option_index)) {\n\t\t\t\t\tret = parse_max_pkt_len(optarg);\n\t\t\t\t\tif ((ret < 64) || (ret > MAX_JUMBO_PKT_LEN)){\n\t\t\t\t\t\tprintf(\"invalid packet length\\n\");\n\t\t\t\t\t\tprint_usage(prgname);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\tport_conf.rxmode.max_rx_pkt_len = ret;\n\t\t\t\t}\n\t\t\t\tprintf(\"set jumbo frame max packet length to %u\\n\",\n\t\t\t\t\t\t(unsigned int)port_conf.rxmode.max_rx_pkt_len);\n\t\t\t}\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n\t\t\tif (!strncmp(lgopts[option_index].name, CMD_LINE_OPT_HASH_ENTRY_NUM,\n\t\t\t\tsizeof(CMD_LINE_OPT_HASH_ENTRY_NUM))) {\n\t\t\t\tret = parse_hash_entry_number(optarg);\n\t\t\t\tif ((ret > 0) && (ret <= L3FWD_HASH_ENTRIES)) {\n\t\t\t\t\thash_entry_number = ret;\n\t\t\t\t} else {\n\t\t\t\t\tprintf(\"invalid hash entry number\\n\");\n\t\t\t\t\tprint_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n#endif\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\nstatic void\nprint_ethaddr(const char *name, const struct ether_addr *eth_addr)\n{\n\tchar buf[ETHER_ADDR_FMT_SIZE];\n\tether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);\n\tprintf(\"%s%s\", name, buf);\n}\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n\nstatic void convert_ipv4_5tuple(struct ipv4_5tuple* key1,\n\t\tunion ipv4_5tuple_host* key2)\n{\n\tkey2->ip_dst = rte_cpu_to_be_32(key1->ip_dst);\n\tkey2->ip_src = rte_cpu_to_be_32(key1->ip_src);\n\tkey2->port_dst = rte_cpu_to_be_16(key1->port_dst);\n\tkey2->port_src = rte_cpu_to_be_16(key1->port_src);\n\tkey2->proto = key1->proto;\n\tkey2->pad0 = 0;\n\tkey2->pad1 = 0;\n\treturn;\n}\n\nstatic void convert_ipv6_5tuple(struct ipv6_5tuple* key1,\n union ipv6_5tuple_host* key2)\n{\n\tuint32_t i;\n\tfor (i = 0; i < 16; i++)\n\t{\n\t\tkey2->ip_dst[i] = key1->ip_dst[i];\n\t\tkey2->ip_src[i] = key1->ip_src[i];\n\t}\n\tkey2->port_dst = rte_cpu_to_be_16(key1->port_dst);\n\tkey2->port_src = rte_cpu_to_be_16(key1->port_src);\n\tkey2->proto = key1->proto;\n\tkey2->pad0 = 0;\n\tkey2->pad1 = 0;\n\tkey2->reserve = 0;\n\treturn;\n}\n\n#define BYTE_VALUE_MAX 256\n#define ALL_32_BITS 0xffffffff\n#define BIT_8_TO_15 0x0000ff00\nstatic inline void\npopulate_ipv4_few_flow_into_table(const struct rte_hash* h)\n{\n\tuint32_t i;\n\tint32_t ret;\n\tuint32_t array_len = sizeof(ipv4_l3fwd_route_array)/sizeof(ipv4_l3fwd_route_array[0]);\n\n\tmask0 = _mm_set_epi32(ALL_32_BITS, ALL_32_BITS, ALL_32_BITS, BIT_8_TO_15);\n\tfor (i = 0; i < array_len; i++) {\n\t\tstruct ipv4_l3fwd_route entry;\n\t\tunion ipv4_5tuple_host newkey;\n\t\tentry = ipv4_l3fwd_route_array[i];\n\t\tconvert_ipv4_5tuple(&entry.key, &newkey);\n\t\tret = rte_hash_add_key (h,(void *) &newkey);\n\t\tif (ret < 0) {\n\t\t\trte_exit(EXIT_FAILURE, \"Unable to add entry %\" PRIu32\n\t\t\t\t\" to the l3fwd hash.\\n\", i);\n\t\t}\n\t\tipv4_l3fwd_out_if[ret] = entry.if_out;\n\t}\n\tprintf(\"Hash: Adding 0x%\" PRIx32 \" keys\\n\", array_len);\n}\n\n#define BIT_16_TO_23 0x00ff0000\nstatic inline void\npopulate_ipv6_few_flow_into_table(const struct rte_hash* h)\n{\n\tuint32_t i;\n\tint32_t ret;\n\tuint32_t array_len = sizeof(ipv6_l3fwd_route_array)/sizeof(ipv6_l3fwd_route_array[0]);\n\n\tmask1 = _mm_set_epi32(ALL_32_BITS, ALL_32_BITS, ALL_32_BITS, BIT_16_TO_23);\n\tmask2 = _mm_set_epi32(0, 0, ALL_32_BITS, ALL_32_BITS);\n\tfor (i = 0; i < array_len; i++) {\n\t\tstruct ipv6_l3fwd_route entry;\n\t\tunion ipv6_5tuple_host newkey;\n\t\tentry = ipv6_l3fwd_route_array[i];\n\t\tconvert_ipv6_5tuple(&entry.key, &newkey);\n\t\tret = rte_hash_add_key (h, (void *) &newkey);\n\t\tif (ret < 0) {\n\t\t\trte_exit(EXIT_FAILURE, \"Unable to add entry %\" PRIu32\n\t\t\t\t\" to the l3fwd hash.\\n\", i);\n\t\t}\n\t\tipv6_l3fwd_out_if[ret] = entry.if_out;\n\t}\n\tprintf(\"Hash: Adding 0x%\" PRIx32 \"keys\\n\", array_len);\n}\n\n#define NUMBER_PORT_USED 4\nstatic inline void\npopulate_ipv4_many_flow_into_table(const struct rte_hash* h,\n unsigned int nr_flow)\n{\n\tunsigned i;\n\tmask0 = _mm_set_epi32(ALL_32_BITS, ALL_32_BITS, ALL_32_BITS, BIT_8_TO_15);\n\tfor (i = 0; i < nr_flow; i++) {\n\t\tstruct ipv4_l3fwd_route entry;\n\t\tunion ipv4_5tuple_host newkey;\n\t\tuint8_t a = (uint8_t) ((i/NUMBER_PORT_USED)%BYTE_VALUE_MAX);\n\t\tuint8_t b = (uint8_t) (((i/NUMBER_PORT_USED)/BYTE_VALUE_MAX)%BYTE_VALUE_MAX);\n\t\tuint8_t c = (uint8_t) ((i/NUMBER_PORT_USED)/(BYTE_VALUE_MAX*BYTE_VALUE_MAX));\n\t\t/* Create the ipv4 exact match flow */\n\t\tmemset(&entry, 0, sizeof(entry));\n\t\tswitch (i & (NUMBER_PORT_USED -1)) {\n\t\tcase 0:\n\t\t\tentry = ipv4_l3fwd_route_array[0];\n\t\t\tentry.key.ip_dst = IPv4(101,c,b,a);\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\tentry = ipv4_l3fwd_route_array[1];\n\t\t\tentry.key.ip_dst = IPv4(201,c,b,a);\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\tentry = ipv4_l3fwd_route_array[2];\n\t\t\tentry.key.ip_dst = IPv4(111,c,b,a);\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\tentry = ipv4_l3fwd_route_array[3];\n\t\t\tentry.key.ip_dst = IPv4(211,c,b,a);\n\t\t\tbreak;\n\t\t};\n\t\tconvert_ipv4_5tuple(&entry.key, &newkey);\n\t\tint32_t ret = rte_hash_add_key(h,(void *) &newkey);\n\t\tif (ret < 0) {\n\t\t\trte_exit(EXIT_FAILURE, \"Unable to add entry %u\\n\", i);\n\t\t}\n\t\tipv4_l3fwd_out_if[ret] = (uint8_t) entry.if_out;\n\n\t}\n\tprintf(\"Hash: Adding 0x%x keys\\n\", nr_flow);\n}\n\nstatic inline void\npopulate_ipv6_many_flow_into_table(const struct rte_hash* h,\n unsigned int nr_flow)\n{\n\tunsigned i;\n\tmask1 = _mm_set_epi32(ALL_32_BITS, ALL_32_BITS, ALL_32_BITS, BIT_16_TO_23);\n\tmask2 = _mm_set_epi32(0, 0, ALL_32_BITS, ALL_32_BITS);\n\tfor (i = 0; i < nr_flow; i++) {\n\t\tstruct ipv6_l3fwd_route entry;\n\t\tunion ipv6_5tuple_host newkey;\n\t\tuint8_t a = (uint8_t) ((i/NUMBER_PORT_USED)%BYTE_VALUE_MAX);\n\t\tuint8_t b = (uint8_t) (((i/NUMBER_PORT_USED)/BYTE_VALUE_MAX)%BYTE_VALUE_MAX);\n\t\tuint8_t c = (uint8_t) ((i/NUMBER_PORT_USED)/(BYTE_VALUE_MAX*BYTE_VALUE_MAX));\n\t\t/* Create the ipv6 exact match flow */\n\t\tmemset(&entry, 0, sizeof(entry));\n\t\tswitch (i & (NUMBER_PORT_USED - 1)) {\n\t\tcase 0: entry = ipv6_l3fwd_route_array[0]; break;\n\t\tcase 1: entry = ipv6_l3fwd_route_array[1]; break;\n\t\tcase 2: entry = ipv6_l3fwd_route_array[2]; break;\n\t\tcase 3: entry = ipv6_l3fwd_route_array[3]; break;\n\t\t};\n\t\tentry.key.ip_dst[13] = c;\n\t\tentry.key.ip_dst[14] = b;\n\t\tentry.key.ip_dst[15] = a;\n\t\tconvert_ipv6_5tuple(&entry.key, &newkey);\n\t\tint32_t ret = rte_hash_add_key(h,(void *) &newkey);\n\t\tif (ret < 0) {\n\t\t\trte_exit(EXIT_FAILURE, \"Unable to add entry %u\\n\", i);\n\t\t}\n\t\tipv6_l3fwd_out_if[ret] = (uint8_t) entry.if_out;\n\n\t}\n\tprintf(\"Hash: Adding 0x%x keys\\n\", nr_flow);\n}\n\nstatic void\nsetup_hash(int socketid)\n{\n struct rte_hash_parameters ipv4_l3fwd_hash_params = {\n .name = NULL,\n .entries = L3FWD_HASH_ENTRIES,\n .key_len = sizeof(union ipv4_5tuple_host),\n .hash_func = ipv4_hash_crc,\n .hash_func_init_val = 0,\n };\n\n struct rte_hash_parameters ipv6_l3fwd_hash_params = {\n .name = NULL,\n .entries = L3FWD_HASH_ENTRIES,\n .key_len = sizeof(union ipv6_5tuple_host),\n .hash_func = ipv6_hash_crc,\n .hash_func_init_val = 0,\n };\n\n char s[64];\n\n\t/* create ipv4 hash */\n\tsnprintf(s, sizeof(s), \"ipv4_l3fwd_hash_%d\", socketid);\n\tipv4_l3fwd_hash_params.name = s;\n\tipv4_l3fwd_hash_params.socket_id = socketid;\n\tipv4_l3fwd_lookup_struct[socketid] = rte_hash_create(&ipv4_l3fwd_hash_params);\n\tif (ipv4_l3fwd_lookup_struct[socketid] == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Unable to create the l3fwd hash on \"\n\t\t\t\t\"socket %d\\n\", socketid);\n\n\t/* create ipv6 hash */\n\tsnprintf(s, sizeof(s), \"ipv6_l3fwd_hash_%d\", socketid);\n\tipv6_l3fwd_hash_params.name = s;\n\tipv6_l3fwd_hash_params.socket_id = socketid;\n\tipv6_l3fwd_lookup_struct[socketid] = rte_hash_create(&ipv6_l3fwd_hash_params);\n\tif (ipv6_l3fwd_lookup_struct[socketid] == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Unable to create the l3fwd hash on \"\n\t\t\t\t\"socket %d\\n\", socketid);\n\n\tif (hash_entry_number != HASH_ENTRY_NUMBER_DEFAULT) {\n\t\t/* For testing hash matching with a large number of flows we\n\t\t * generate millions of IP 5-tuples with an incremented dst\n\t\t * address to initialize the hash table. */\n\t\tif (ipv6 == 0) {\n\t\t\t/* populate the ipv4 hash */\n\t\t\tpopulate_ipv4_many_flow_into_table(\n\t\t\t\tipv4_l3fwd_lookup_struct[socketid], hash_entry_number);\n\t\t} else {\n\t\t\t/* populate the ipv6 hash */\n\t\t\tpopulate_ipv6_many_flow_into_table(\n\t\t\t\tipv6_l3fwd_lookup_struct[socketid], hash_entry_number);\n\t\t}\n\t} else {\n\t\t/* Use data in ipv4/ipv6 l3fwd lookup table directly to initialize the hash table */\n\t\tif (ipv6 == 0) {\n\t\t\t/* populate the ipv4 hash */\n\t\t\tpopulate_ipv4_few_flow_into_table(ipv4_l3fwd_lookup_struct[socketid]);\n\t\t} else {\n\t\t\t/* populate the ipv6 hash */\n\t\t\tpopulate_ipv6_few_flow_into_table(ipv6_l3fwd_lookup_struct[socketid]);\n\t\t}\n\t}\n}\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\nstatic void\nsetup_lpm(int socketid)\n{\n\tstruct rte_lpm6_config config;\n\tunsigned i;\n\tint ret;\n\tchar s[64];\n\n\t/* create the LPM table */\n\tsnprintf(s, sizeof(s), \"IPV4_L3FWD_LPM_%d\", socketid);\n\tipv4_l3fwd_lookup_struct[socketid] = rte_lpm_create(s, socketid,\n\t\t\t\tIPV4_L3FWD_LPM_MAX_RULES, 0);\n\tif (ipv4_l3fwd_lookup_struct[socketid] == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Unable to create the l3fwd LPM table\"\n\t\t\t\t\" on socket %d\\n\", socketid);\n\n\t/* populate the LPM table */\n\tfor (i = 0; i < IPV4_L3FWD_NUM_ROUTES; i++) {\n\n\t\t/* skip unused ports */\n\t\tif ((1 << ipv4_l3fwd_route_array[i].if_out &\n\t\t\t\tenabled_port_mask) == 0)\n\t\t\tcontinue;\n\n\t\tret = rte_lpm_add(ipv4_l3fwd_lookup_struct[socketid],\n\t\t\tipv4_l3fwd_route_array[i].ip,\n\t\t\tipv4_l3fwd_route_array[i].depth,\n\t\t\tipv4_l3fwd_route_array[i].if_out);\n\n\t\tif (ret < 0) {\n\t\t\trte_exit(EXIT_FAILURE, \"Unable to add entry %u to the \"\n\t\t\t\t\"l3fwd LPM table on socket %d\\n\",\n\t\t\t\ti, socketid);\n\t\t}\n\n\t\tprintf(\"LPM: Adding route 0x%08x / %d (%d)\\n\",\n\t\t\t(unsigned)ipv4_l3fwd_route_array[i].ip,\n\t\t\tipv4_l3fwd_route_array[i].depth,\n\t\t\tipv4_l3fwd_route_array[i].if_out);\n\t}\n\n\t/* create the LPM6 table */\n\tsnprintf(s, sizeof(s), \"IPV6_L3FWD_LPM_%d\", socketid);\n\n\tconfig.max_rules = IPV6_L3FWD_LPM_MAX_RULES;\n\tconfig.number_tbl8s = IPV6_L3FWD_LPM_NUMBER_TBL8S;\n\tconfig.flags = 0;\n\tipv6_l3fwd_lookup_struct[socketid] = rte_lpm6_create(s, socketid,\n\t\t\t\t&config);\n\tif (ipv6_l3fwd_lookup_struct[socketid] == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Unable to create the l3fwd LPM table\"\n\t\t\t\t\" on socket %d\\n\", socketid);\n\n\t/* populate the LPM table */\n\tfor (i = 0; i < IPV6_L3FWD_NUM_ROUTES; i++) {\n\n\t\t/* skip unused ports */\n\t\tif ((1 << ipv6_l3fwd_route_array[i].if_out &\n\t\t\t\tenabled_port_mask) == 0)\n\t\t\tcontinue;\n\n\t\tret = rte_lpm6_add(ipv6_l3fwd_lookup_struct[socketid],\n\t\t\tipv6_l3fwd_route_array[i].ip,\n\t\t\tipv6_l3fwd_route_array[i].depth,\n\t\t\tipv6_l3fwd_route_array[i].if_out);\n\n\t\tif (ret < 0) {\n\t\t\trte_exit(EXIT_FAILURE, \"Unable to add entry %u to the \"\n\t\t\t\t\"l3fwd LPM table on socket %d\\n\",\n\t\t\t\ti, socketid);\n\t\t}\n\n\t\tprintf(\"LPM: Adding route %s / %d (%d)\\n\",\n\t\t\t\"IPV6\",\n\t\t\tipv6_l3fwd_route_array[i].depth,\n\t\t\tipv6_l3fwd_route_array[i].if_out);\n\t}\n}\n#endif\n\nstatic int\ninit_mem(unsigned nb_mbuf)\n{\n\tstruct lcore_conf *qconf;\n\tint socketid;\n\tunsigned lcore_id;\n\tchar s[64];\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\tcontinue;\n\n\t\tif (numa_on)\n\t\t\tsocketid = rte_lcore_to_socket_id(lcore_id);\n\t\telse\n\t\t\tsocketid = 0;\n\n\t\tif (socketid >= NB_SOCKETS) {\n\t\t\trte_exit(EXIT_FAILURE, \"Socket %d of lcore %u is out of range %d\\n\",\n\t\t\t\tsocketid, lcore_id, NB_SOCKETS);\n\t\t}\n\t\tif (pktmbuf_pool[socketid] == NULL) {\n\t\t\tsnprintf(s, sizeof(s), \"mbuf_pool_%d\", socketid);\n\t\t\tpktmbuf_pool[socketid] =\n\t\t\t\trte_pktmbuf_pool_create(s, nb_mbuf,\n\t\t\t\t\tMEMPOOL_CACHE_SIZE, 0,\n\t\t\t\t\tRTE_MBUF_DEFAULT_BUF_SIZE, socketid);\n\t\t\tif (pktmbuf_pool[socketid] == NULL)\n\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t\"Cannot init mbuf pool on socket %d\\n\", socketid);\n\t\t\telse\n\t\t\t\tprintf(\"Allocated mbuf pool on socket %d\\n\", socketid);\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\n\t\t\tsetup_lpm(socketid);\n#else\n\t\t\tsetup_hash(socketid);\n#endif\n\t\t}\n\t\tqconf = &lcore_conf[lcore_id];\n\t\tqconf->ipv4_lookup_struct = ipv4_l3fwd_lookup_struct[socketid];\n\t\tqconf->ipv6_lookup_struct = ipv6_l3fwd_lookup_struct[socketid];\n\t}\n\treturn 0;\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_conf *qconf;\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_txconf *txconf;\n\tint ret;\n\tunsigned nb_ports;\n\tuint16_t queueid;\n\tunsigned lcore_id;\n\tuint32_t n_tx_queue, nb_lcores;\n\tuint8_t portid, nb_rx_queue, queue, socketid;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid EAL parameters\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* pre-init dst MACs for all ports to 02:00:00:00:00:xx */\n\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\tdest_eth_addr[portid] = ETHER_LOCAL_ADMIN_ADDR + ((uint64_t)portid << 40);\n\t\t*(uint64_t *)(val_eth + portid) = dest_eth_addr[portid];\n\t}\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid L3FWD parameters\\n\");\n\n\tif (check_lcore_params() < 0)\n\t\trte_exit(EXIT_FAILURE, \"check_lcore_params failed\\n\");\n\n\tret = init_lcore_rx_queues();\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"init_lcore_rx_queues failed\\n\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\tif (check_port_config(nb_ports) < 0)\n\t\trte_exit(EXIT_FAILURE, \"check_port_config failed\\n\");\n\n\tnb_lcores = rte_lcore_count();\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"\\nSkipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* init port */\n\t\tprintf(\"Initializing port %d ... \", portid );\n\t\tfflush(stdout);\n\n\t\tnb_rx_queue = get_port_n_rx_queues(portid);\n\t\tn_tx_queue = nb_lcores;\n\t\tif (n_tx_queue > MAX_TX_QUEUE_PER_PORT)\n\t\t\tn_tx_queue = MAX_TX_QUEUE_PER_PORT;\n\t\tprintf(\"Creating queues: nb_rxq=%d nb_txq=%u... \",\n\t\t\tnb_rx_queue, (unsigned)n_tx_queue );\n\t\tret = rte_eth_dev_configure(portid, nb_rx_queue,\n\t\t\t\t\t(uint16_t)n_tx_queue, &port_conf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot configure device: err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\n\t\trte_eth_macaddr_get(portid, &ports_eth_addr[portid]);\n\t\tprint_ethaddr(\" Address:\", &ports_eth_addr[portid]);\n\t\tprintf(\", \");\n\t\tprint_ethaddr(\"Destination:\",\n\t\t\t(const struct ether_addr *)&dest_eth_addr[portid]);\n\t\tprintf(\", \");\n\n\t\t/*\n\t\t * prepare src MACs for each port.\n\t\t */\n\t\tether_addr_copy(&ports_eth_addr[portid],\n\t\t\t(struct ether_addr *)(val_eth + portid) + 1);\n\n\t\t/* init memory */\n\t\tret = init_mem(NB_MBUF);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"init_mem failed\\n\");\n\n\t\t/* init one TX queue per couple (lcore,port) */\n\t\tqueueid = 0;\n\t\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (numa_on)\n\t\t\t\tsocketid = (uint8_t)rte_lcore_to_socket_id(lcore_id);\n\t\t\telse\n\t\t\t\tsocketid = 0;\n\n\t\t\tprintf(\"txq=%u,%d,%d \", lcore_id, queueid, socketid);\n\t\t\tfflush(stdout);\n\n\t\t\trte_eth_dev_info_get(portid, &dev_info);\n\t\t\ttxconf = &dev_info.default_txconf;\n\t\t\tif (port_conf.rxmode.jumbo_frame)\n\t\t\t\ttxconf->txq_flags = 0;\n\t\t\tret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,\n\t\t\t\t\t\t socketid, txconf);\n\t\t\tif (ret < 0)\n\t\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup: err=%d, \"\n\t\t\t\t\t\"port=%d\\n\", ret, portid);\n\n\t\t\tqconf = &lcore_conf[lcore_id];\n\t\t\tqconf->tx_queue_id[portid] = queueid;\n\t\t\tqueueid++;\n\t\t}\n\t\tprintf(\"\\n\");\n\t}\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\tcontinue;\n\t\tqconf = &lcore_conf[lcore_id];\n\t\tprintf(\"\\nInitializing rx queues on lcore %u ... \", lcore_id );\n\t\tfflush(stdout);\n\t\t/* init RX queues */\n\t\tfor(queue = 0; queue < qconf->n_rx_queue; ++queue) {\n\t\t\tportid = qconf->rx_queue_list[queue].port_id;\n\t\t\tqueueid = qconf->rx_queue_list[queue].queue_id;\n\n\t\t\tif (numa_on)\n\t\t\t\tsocketid = (uint8_t)rte_lcore_to_socket_id(lcore_id);\n\t\t\telse\n\t\t\t\tsocketid = 0;\n\n\t\t\tprintf(\"rxq=%d,%d,%d \", portid, queueid, socketid);\n\t\t\tfflush(stdout);\n\n\t\t\tret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd,\n\t\t\t\t\tsocketid,\n\t\t\t\t\tNULL,\n\t\t\t\t\tpktmbuf_pool[socketid]);\n\t\t\tif (ret < 0)\n\t\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup: err=%d,\"\n\t\t\t\t\t\t\"port=%d\\n\", ret, portid);\n\t\t}\n\t}\n\n\tprintf(\"\\n\");\n\n\t/* start ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tcontinue;\n\t\t}\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_dev_start: err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\n\t\t/*\n\t\t * If enabled, put device in promiscuous mode.\n\t\t * This allows IO forwarding mode to forward packets\n\t\t * to itself through 2 cross-connected ports of the\n\t\t * target machine.\n\t\t */\n\t\tif (promiscuous_on)\n\t\t\trte_eth_promiscuous_enable(portid);\n\t}\n\n\tcheck_all_ports_link_status((uint8_t)nb_ports, enabled_port_mask);\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/l3fwd-acl/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = l3fwd-acl\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/l3fwd-acl/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define DO_RFC_1812_CHECKS\n\n#define RTE_LOGTYPE_L3FWD RTE_LOGTYPE_USER1\n\n#define MAX_JUMBO_PKT_LEN 9600\n\n#define MEMPOOL_CACHE_SIZE 256\n\n/*\n * This expression is used to calculate the number of mbufs needed\n * depending on user input, taking into account memory for rx and tx hardware\n * rings, cache per lcore and mtable per port per lcore.\n * RTE_MAX is used to ensure that NB_MBUF never goes below a\n * minimum value of 8192\n */\n\n#define NB_MBUF\tRTE_MAX(\\\n\t(nb_ports * nb_rx_queue*RTE_TEST_RX_DESC_DEFAULT +\t\\\n\tnb_ports * nb_lcores * MAX_PKT_BURST +\t\t\t\\\n\tnb_ports * n_tx_queue * RTE_TEST_TX_DESC_DEFAULT +\t\\\n\tnb_lcores * MEMPOOL_CACHE_SIZE),\t\t\t\\\n\t(unsigned)8192)\n\n#define MAX_PKT_BURST 32\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n#define NB_SOCKETS 8\n\n/* Configure how many packets ahead to prefetch, when reading packets */\n#define PREFETCH_OFFSET\t3\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n/* ethernet addresses of ports */\nstatic struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];\n\n/* mask of enabled ports */\nstatic uint32_t enabled_port_mask;\nstatic int promiscuous_on; /**< Ports set in promiscuous mode off by default. */\nstatic int numa_on = 1; /**< NUMA is enabled by default. */\n\nstruct mbuf_table {\n\tuint16_t len;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST];\n};\n\nstruct lcore_rx_queue {\n\tuint8_t port_id;\n\tuint8_t queue_id;\n} __rte_cache_aligned;\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT RTE_MAX_ETHPORTS\n#define MAX_RX_QUEUE_PER_PORT 128\n\n#define MAX_LCORE_PARAMS 1024\nstruct lcore_params {\n\tuint8_t port_id;\n\tuint8_t queue_id;\n\tuint8_t lcore_id;\n} __rte_cache_aligned;\n\nstatic struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];\nstatic struct lcore_params lcore_params_array_default[] = {\n\t{0, 0, 2},\n\t{0, 1, 2},\n\t{0, 2, 2},\n\t{1, 0, 2},\n\t{1, 1, 2},\n\t{1, 2, 2},\n\t{2, 0, 2},\n\t{3, 0, 3},\n\t{3, 1, 3},\n};\n\nstatic struct lcore_params *lcore_params = lcore_params_array_default;\nstatic uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /\n\t\t\t\tsizeof(lcore_params_array_default[0]);\n\nstatic struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.mq_mode\t= ETH_MQ_RX_RSS,\n\t\t.max_rx_pkt_len = ETHER_MAX_LEN,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 1, /**< IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.rx_adv_conf = {\n\t\t.rss_conf = {\n\t\t\t.rss_key = NULL,\n\t\t\t.rss_hf = ETH_RSS_IP | ETH_RSS_UDP |\n\t\t\t\tETH_RSS_TCP | ETH_RSS_SCTP,\n\t\t},\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\nstatic struct rte_mempool *pktmbuf_pool[NB_SOCKETS];\n\n/***********************start of ACL part******************************/\n#ifdef DO_RFC_1812_CHECKS\nstatic inline int\nis_valid_ipv4_pkt(struct ipv4_hdr *pkt, uint32_t link_len);\n#endif\nstatic inline int\nsend_single_packet(struct rte_mbuf *m, uint8_t port);\n\n#define MAX_ACL_RULE_NUM\t100000\n#define DEFAULT_MAX_CATEGORIES\t1\n#define L3FWD_ACL_IPV4_NAME\t\"l3fwd-acl-ipv4\"\n#define L3FWD_ACL_IPV6_NAME\t\"l3fwd-acl-ipv6\"\n#define ACL_LEAD_CHAR\t\t('@')\n#define ROUTE_LEAD_CHAR\t\t('R')\n#define COMMENT_LEAD_CHAR\t('#')\n#define OPTION_CONFIG\t\t\"config\"\n#define OPTION_NONUMA\t\t\"no-numa\"\n#define OPTION_ENBJMO\t\t\"enable-jumbo\"\n#define OPTION_RULE_IPV4\t\"rule_ipv4\"\n#define OPTION_RULE_IPV6\t\"rule_ipv6\"\n#define OPTION_SCALAR\t\t\"scalar\"\n#define ACL_DENY_SIGNATURE\t0xf0000000\n#define RTE_LOGTYPE_L3FWDACL\tRTE_LOGTYPE_USER3\n#define acl_log(format, ...)\tRTE_LOG(ERR, L3FWDACL, format, ##__VA_ARGS__)\n#define uint32_t_to_char(ip, a, b, c, d) do {\\\n\t\t*a = (unsigned char)(ip >> 24 & 0xff);\\\n\t\t*b = (unsigned char)(ip >> 16 & 0xff);\\\n\t\t*c = (unsigned char)(ip >> 8 & 0xff);\\\n\t\t*d = (unsigned char)(ip & 0xff);\\\n\t} while (0)\n#define OFF_ETHHEAD\t(sizeof(struct ether_hdr))\n#define OFF_IPV42PROTO (offsetof(struct ipv4_hdr, next_proto_id))\n#define OFF_IPV62PROTO (offsetof(struct ipv6_hdr, proto))\n#define MBUF_IPV4_2PROTO(m)\t\\\n\trte_pktmbuf_mtod_offset((m), uint8_t *, OFF_ETHHEAD + OFF_IPV42PROTO)\n#define MBUF_IPV6_2PROTO(m)\t\\\n\trte_pktmbuf_mtod_offset((m), uint8_t *, OFF_ETHHEAD + OFF_IPV62PROTO)\n\n#define GET_CB_FIELD(in, fd, base, lim, dlm)\tdo { \\\n\tunsigned long val; \\\n\tchar *end; \\\n\terrno = 0; \\\n\tval = strtoul((in), &end, (base)); \\\n\tif (errno != 0 || end[0] != (dlm) || val > (lim)) \\\n\t\treturn -EINVAL; \\\n\t(fd) = (typeof(fd))val; \\\n\t(in) = end + 1; \\\n} while (0)\n\n/*\n * ACL rules should have higher priorities than route ones to ensure ACL rule\n * always be found when input packets have multi-matches in the database.\n * A exception case is performance measure, which can define route rules with\n * higher priority and route rules will always be returned in each lookup.\n * Reserve range from ACL_RULE_PRIORITY_MAX + 1 to\n * RTE_ACL_MAX_PRIORITY for route entries in performance measure\n */\n#define ACL_RULE_PRIORITY_MAX 0x10000000\n\n/*\n * Forward port info save in ACL lib starts from 1\n * since ACL assume 0 is invalid.\n * So, need add 1 when saving and minus 1 when forwarding packets.\n */\n#define FWD_PORT_SHIFT 1\n\n/*\n * Rule and trace formats definitions.\n */\n\nenum {\n\tPROTO_FIELD_IPV4,\n\tSRC_FIELD_IPV4,\n\tDST_FIELD_IPV4,\n\tSRCP_FIELD_IPV4,\n\tDSTP_FIELD_IPV4,\n\tNUM_FIELDS_IPV4\n};\n\nstruct rte_acl_field_def ipv4_defs[NUM_FIELDS_IPV4] = {\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t.size = sizeof(uint8_t),\n\t\t.field_index = PROTO_FIELD_IPV4,\n\t\t.input_index = RTE_ACL_IPV4VLAN_PROTO,\n\t\t.offset = 0,\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = SRC_FIELD_IPV4,\n\t\t.input_index = RTE_ACL_IPV4VLAN_SRC,\n\t\t.offset = offsetof(struct ipv4_hdr, src_addr) -\n\t\t\toffsetof(struct ipv4_hdr, next_proto_id),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = DST_FIELD_IPV4,\n\t\t.input_index = RTE_ACL_IPV4VLAN_DST,\n\t\t.offset = offsetof(struct ipv4_hdr, dst_addr) -\n\t\t\toffsetof(struct ipv4_hdr, next_proto_id),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = SRCP_FIELD_IPV4,\n\t\t.input_index = RTE_ACL_IPV4VLAN_PORTS,\n\t\t.offset = sizeof(struct ipv4_hdr) -\n\t\t\toffsetof(struct ipv4_hdr, next_proto_id),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = DSTP_FIELD_IPV4,\n\t\t.input_index = RTE_ACL_IPV4VLAN_PORTS,\n\t\t.offset = sizeof(struct ipv4_hdr) -\n\t\t\toffsetof(struct ipv4_hdr, next_proto_id) +\n\t\t\tsizeof(uint16_t),\n\t},\n};\n\n#define\tIPV6_ADDR_LEN\t16\n#define\tIPV6_ADDR_U16\t(IPV6_ADDR_LEN / sizeof(uint16_t))\n#define\tIPV6_ADDR_U32\t(IPV6_ADDR_LEN / sizeof(uint32_t))\n\nenum {\n\tPROTO_FIELD_IPV6,\n\tSRC1_FIELD_IPV6,\n\tSRC2_FIELD_IPV6,\n\tSRC3_FIELD_IPV6,\n\tSRC4_FIELD_IPV6,\n\tDST1_FIELD_IPV6,\n\tDST2_FIELD_IPV6,\n\tDST3_FIELD_IPV6,\n\tDST4_FIELD_IPV6,\n\tSRCP_FIELD_IPV6,\n\tDSTP_FIELD_IPV6,\n\tNUM_FIELDS_IPV6\n};\n\nstruct rte_acl_field_def ipv6_defs[NUM_FIELDS_IPV6] = {\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t.size = sizeof(uint8_t),\n\t\t.field_index = PROTO_FIELD_IPV6,\n\t\t.input_index = PROTO_FIELD_IPV6,\n\t\t.offset = 0,\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = SRC1_FIELD_IPV6,\n\t\t.input_index = SRC1_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_hdr, src_addr) -\n\t\t\toffsetof(struct ipv6_hdr, proto),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = SRC2_FIELD_IPV6,\n\t\t.input_index = SRC2_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_hdr, src_addr) -\n\t\t\toffsetof(struct ipv6_hdr, proto) + sizeof(uint32_t),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = SRC3_FIELD_IPV6,\n\t\t.input_index = SRC3_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_hdr, src_addr) -\n\t\t\toffsetof(struct ipv6_hdr, proto) + 2 * sizeof(uint32_t),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = SRC4_FIELD_IPV6,\n\t\t.input_index = SRC4_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_hdr, src_addr) -\n\t\t\toffsetof(struct ipv6_hdr, proto) + 3 * sizeof(uint32_t),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = DST1_FIELD_IPV6,\n\t\t.input_index = DST1_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_hdr, dst_addr)\n\t\t\t\t- offsetof(struct ipv6_hdr, proto),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = DST2_FIELD_IPV6,\n\t\t.input_index = DST2_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_hdr, dst_addr) -\n\t\t\toffsetof(struct ipv6_hdr, proto) + sizeof(uint32_t),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = DST3_FIELD_IPV6,\n\t\t.input_index = DST3_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_hdr, dst_addr) -\n\t\t\toffsetof(struct ipv6_hdr, proto) + 2 * sizeof(uint32_t),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t.size = sizeof(uint32_t),\n\t\t.field_index = DST4_FIELD_IPV6,\n\t\t.input_index = DST4_FIELD_IPV6,\n\t\t.offset = offsetof(struct ipv6_hdr, dst_addr) -\n\t\t\toffsetof(struct ipv6_hdr, proto) + 3 * sizeof(uint32_t),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = SRCP_FIELD_IPV6,\n\t\t.input_index = SRCP_FIELD_IPV6,\n\t\t.offset = sizeof(struct ipv6_hdr) -\n\t\t\toffsetof(struct ipv6_hdr, proto),\n\t},\n\t{\n\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t.size = sizeof(uint16_t),\n\t\t.field_index = DSTP_FIELD_IPV6,\n\t\t.input_index = SRCP_FIELD_IPV6,\n\t\t.offset = sizeof(struct ipv6_hdr) -\n\t\t\toffsetof(struct ipv6_hdr, proto) + sizeof(uint16_t),\n\t},\n};\n\nenum {\n\tCB_FLD_SRC_ADDR,\n\tCB_FLD_DST_ADDR,\n\tCB_FLD_SRC_PORT_LOW,\n\tCB_FLD_SRC_PORT_DLM,\n\tCB_FLD_SRC_PORT_HIGH,\n\tCB_FLD_DST_PORT_LOW,\n\tCB_FLD_DST_PORT_DLM,\n\tCB_FLD_DST_PORT_HIGH,\n\tCB_FLD_PROTO,\n\tCB_FLD_USERDATA,\n\tCB_FLD_NUM,\n};\n\nRTE_ACL_RULE_DEF(acl4_rule, RTE_DIM(ipv4_defs));\nRTE_ACL_RULE_DEF(acl6_rule, RTE_DIM(ipv6_defs));\n\nstruct acl_search_t {\n\tconst uint8_t *data_ipv4[MAX_PKT_BURST];\n\tstruct rte_mbuf *m_ipv4[MAX_PKT_BURST];\n\tuint32_t res_ipv4[MAX_PKT_BURST];\n\tint num_ipv4;\n\n\tconst uint8_t *data_ipv6[MAX_PKT_BURST];\n\tstruct rte_mbuf *m_ipv6[MAX_PKT_BURST];\n\tuint32_t res_ipv6[MAX_PKT_BURST];\n\tint num_ipv6;\n};\n\nstatic struct {\n\tchar mapped[NB_SOCKETS];\n\tstruct rte_acl_ctx *acx_ipv4[NB_SOCKETS];\n\tstruct rte_acl_ctx *acx_ipv6[NB_SOCKETS];\n#ifdef L3FWDACL_DEBUG\n\tstruct acl4_rule *rule_ipv4;\n\tstruct acl6_rule *rule_ipv6;\n#endif\n} acl_config;\n\nstatic struct{\n\tconst char *rule_ipv4_name;\n\tconst char *rule_ipv6_name;\n\tint scalar;\n} parm_config;\n\nconst char cb_port_delim[] = \":\";\n\nstatic inline void\nprint_one_ipv4_rule(struct acl4_rule *rule, int extra)\n{\n\tunsigned char a, b, c, d;\n\n\tuint32_t_to_char(rule->field[SRC_FIELD_IPV4].value.u32,\n\t\t\t&a, &b, &c, &d);\n\tprintf(\"%hhu.%hhu.%hhu.%hhu/%u \", a, b, c, d,\n\t\t\trule->field[SRC_FIELD_IPV4].mask_range.u32);\n\tuint32_t_to_char(rule->field[DST_FIELD_IPV4].value.u32,\n\t\t\t&a, &b, &c, &d);\n\tprintf(\"%hhu.%hhu.%hhu.%hhu/%u \", a, b, c, d,\n\t\t\trule->field[DST_FIELD_IPV4].mask_range.u32);\n\tprintf(\"%hu : %hu %hu : %hu 0x%hhx/0x%hhx \",\n\t\trule->field[SRCP_FIELD_IPV4].value.u16,\n\t\trule->field[SRCP_FIELD_IPV4].mask_range.u16,\n\t\trule->field[DSTP_FIELD_IPV4].value.u16,\n\t\trule->field[DSTP_FIELD_IPV4].mask_range.u16,\n\t\trule->field[PROTO_FIELD_IPV4].value.u8,\n\t\trule->field[PROTO_FIELD_IPV4].mask_range.u8);\n\tif (extra)\n\t\tprintf(\"0x%x-0x%x-0x%x \",\n\t\t\trule->data.category_mask,\n\t\t\trule->data.priority,\n\t\t\trule->data.userdata);\n}\n\nstatic inline void\nprint_one_ipv6_rule(struct acl6_rule *rule, int extra)\n{\n\tunsigned char a, b, c, d;\n\n\tuint32_t_to_char(rule->field[SRC1_FIELD_IPV6].value.u32,\n\t\t&a, &b, &c, &d);\n\tprintf(\"%.2x%.2x:%.2x%.2x\", a, b, c, d);\n\tuint32_t_to_char(rule->field[SRC2_FIELD_IPV6].value.u32,\n\t\t&a, &b, &c, &d);\n\tprintf(\":%.2x%.2x:%.2x%.2x\", a, b, c, d);\n\tuint32_t_to_char(rule->field[SRC3_FIELD_IPV6].value.u32,\n\t\t&a, &b, &c, &d);\n\tprintf(\":%.2x%.2x:%.2x%.2x\", a, b, c, d);\n\tuint32_t_to_char(rule->field[SRC4_FIELD_IPV6].value.u32,\n\t\t&a, &b, &c, &d);\n\tprintf(\":%.2x%.2x:%.2x%.2x/%u \", a, b, c, d,\n\t\t\trule->field[SRC1_FIELD_IPV6].mask_range.u32\n\t\t\t+ rule->field[SRC2_FIELD_IPV6].mask_range.u32\n\t\t\t+ rule->field[SRC3_FIELD_IPV6].mask_range.u32\n\t\t\t+ rule->field[SRC4_FIELD_IPV6].mask_range.u32);\n\n\tuint32_t_to_char(rule->field[DST1_FIELD_IPV6].value.u32,\n\t\t&a, &b, &c, &d);\n\tprintf(\"%.2x%.2x:%.2x%.2x\", a, b, c, d);\n\tuint32_t_to_char(rule->field[DST2_FIELD_IPV6].value.u32,\n\t\t&a, &b, &c, &d);\n\tprintf(\":%.2x%.2x:%.2x%.2x\", a, b, c, d);\n\tuint32_t_to_char(rule->field[DST3_FIELD_IPV6].value.u32,\n\t\t&a, &b, &c, &d);\n\tprintf(\":%.2x%.2x:%.2x%.2x\", a, b, c, d);\n\tuint32_t_to_char(rule->field[DST4_FIELD_IPV6].value.u32,\n\t\t&a, &b, &c, &d);\n\tprintf(\":%.2x%.2x:%.2x%.2x/%u \", a, b, c, d,\n\t\t\trule->field[DST1_FIELD_IPV6].mask_range.u32\n\t\t\t+ rule->field[DST2_FIELD_IPV6].mask_range.u32\n\t\t\t+ rule->field[DST3_FIELD_IPV6].mask_range.u32\n\t\t\t+ rule->field[DST4_FIELD_IPV6].mask_range.u32);\n\n\tprintf(\"%hu : %hu %hu : %hu 0x%hhx/0x%hhx \",\n\t\trule->field[SRCP_FIELD_IPV6].value.u16,\n\t\trule->field[SRCP_FIELD_IPV6].mask_range.u16,\n\t\trule->field[DSTP_FIELD_IPV6].value.u16,\n\t\trule->field[DSTP_FIELD_IPV6].mask_range.u16,\n\t\trule->field[PROTO_FIELD_IPV6].value.u8,\n\t\trule->field[PROTO_FIELD_IPV6].mask_range.u8);\n\tif (extra)\n\t\tprintf(\"0x%x-0x%x-0x%x \",\n\t\t\trule->data.category_mask,\n\t\t\trule->data.priority,\n\t\t\trule->data.userdata);\n}\n\n/* Bypass comment and empty lines */\nstatic inline int\nis_bypass_line(char *buff)\n{\n\tint i = 0;\n\n\t/* comment line */\n\tif (buff[0] == COMMENT_LEAD_CHAR)\n\t\treturn 1;\n\t/* empty line */\n\twhile (buff[i] != '\\0') {\n\t\tif (!isspace(buff[i]))\n\t\t\treturn 0;\n\t\ti++;\n\t}\n\treturn 1;\n}\n\n#ifdef L3FWDACL_DEBUG\nstatic inline void\ndump_acl4_rule(struct rte_mbuf *m, uint32_t sig)\n{\n\tuint32_t offset = sig & ~ACL_DENY_SIGNATURE;\n\tunsigned char a, b, c, d;\n\tstruct ipv4_hdr *ipv4_hdr = rte_pktmbuf_mtod_offset(m,\n\t\t\t\t\t\t\t struct ipv4_hdr *,\n\t\t\t\t\t\t\t sizeof(struct ether_hdr));\n\n\tuint32_t_to_char(rte_bswap32(ipv4_hdr->src_addr), &a, &b, &c, &d);\n\tprintf(\"Packet Src:%hhu.%hhu.%hhu.%hhu \", a, b, c, d);\n\tuint32_t_to_char(rte_bswap32(ipv4_hdr->dst_addr), &a, &b, &c, &d);\n\tprintf(\"Dst:%hhu.%hhu.%hhu.%hhu \", a, b, c, d);\n\n\tprintf(\"Src port:%hu,Dst port:%hu \",\n\t\t\trte_bswap16(*(uint16_t *)(ipv4_hdr + 1)),\n\t\t\trte_bswap16(*((uint16_t *)(ipv4_hdr + 1) + 1)));\n\tprintf(\"hit ACL %d - \", offset);\n\n\tprint_one_ipv4_rule(acl_config.rule_ipv4 + offset, 1);\n\n\tprintf(\"\\n\\n\");\n}\n\nstatic inline void\ndump_acl6_rule(struct rte_mbuf *m, uint32_t sig)\n{\n\tunsigned i;\n\tuint32_t offset = sig & ~ACL_DENY_SIGNATURE;\n\tstruct ipv6_hdr *ipv6_hdr = rte_pktmbuf_mtod_offset(m,\n\t\t\t\t\t\t\t struct ipv6_hdr *,\n\t\t\t\t\t\t\t sizeof(struct ether_hdr));\n\n\tprintf(\"Packet Src\");\n\tfor (i = 0; i < RTE_DIM(ipv6_hdr->src_addr); i += sizeof(uint16_t))\n\t\tprintf(\":%.2x%.2x\",\n\t\t\tipv6_hdr->src_addr[i], ipv6_hdr->src_addr[i + 1]);\n\n\tprintf(\"\\nDst\");\n\tfor (i = 0; i < RTE_DIM(ipv6_hdr->dst_addr); i += sizeof(uint16_t))\n\t\tprintf(\":%.2x%.2x\",\n\t\t\tipv6_hdr->dst_addr[i], ipv6_hdr->dst_addr[i + 1]);\n\n\tprintf(\"\\nSrc port:%hu,Dst port:%hu \",\n\t\t\trte_bswap16(*(uint16_t *)(ipv6_hdr + 1)),\n\t\t\trte_bswap16(*((uint16_t *)(ipv6_hdr + 1) + 1)));\n\tprintf(\"hit ACL %d - \", offset);\n\n\tprint_one_ipv6_rule(acl_config.rule_ipv6 + offset, 1);\n\n\tprintf(\"\\n\\n\");\n}\n#endif /* L3FWDACL_DEBUG */\n\nstatic inline void\ndump_ipv4_rules(struct acl4_rule *rule, int num, int extra)\n{\n\tint i;\n\n\tfor (i = 0; i < num; i++, rule++) {\n\t\tprintf(\"\\t%d:\", i + 1);\n\t\tprint_one_ipv4_rule(rule, extra);\n\t\tprintf(\"\\n\");\n\t}\n}\n\nstatic inline void\ndump_ipv6_rules(struct acl6_rule *rule, int num, int extra)\n{\n\tint i;\n\n\tfor (i = 0; i < num; i++, rule++) {\n\t\tprintf(\"\\t%d:\", i + 1);\n\t\tprint_one_ipv6_rule(rule, extra);\n\t\tprintf(\"\\n\");\n\t}\n}\n\n#ifdef DO_RFC_1812_CHECKS\nstatic inline void\nprepare_one_packet(struct rte_mbuf **pkts_in, struct acl_search_t *acl,\n\tint index)\n{\n\tstruct ipv4_hdr *ipv4_hdr;\n\tstruct rte_mbuf *pkt = pkts_in[index];\n\n#ifdef RTE_NEXT_ABI\n\tif (RTE_ETH_IS_IPV4_HDR(pkt->packet_type)) {\n#else\n\tint type = pkt->ol_flags & (PKT_RX_IPV4_HDR | PKT_RX_IPV6_HDR);\n\n\tif (type == PKT_RX_IPV4_HDR) {\n#endif\n\t\tipv4_hdr = rte_pktmbuf_mtod_offset(pkt, struct ipv4_hdr *,\n\t\t\t\t\t\t sizeof(struct ether_hdr));\n\n\t\t/* Check to make sure the packet is valid (RFC1812) */\n\t\tif (is_valid_ipv4_pkt(ipv4_hdr, pkt->pkt_len) >= 0) {\n\n\t\t\t/* Update time to live and header checksum */\n\t\t\t--(ipv4_hdr->time_to_live);\n\t\t\t++(ipv4_hdr->hdr_checksum);\n\n\t\t\t/* Fill acl structure */\n\t\t\tacl->data_ipv4[acl->num_ipv4] = MBUF_IPV4_2PROTO(pkt);\n\t\t\tacl->m_ipv4[(acl->num_ipv4)++] = pkt;\n\n\t\t} else {\n\t\t\t/* Not a valid IPv4 packet */\n\t\t\trte_pktmbuf_free(pkt);\n\t\t}\n#ifdef RTE_NEXT_ABI\n\t} else if (RTE_ETH_IS_IPV6_HDR(pkt->packet_type)) {\n#else\n\t} else if (type == PKT_RX_IPV6_HDR) {\n#endif\n\t\t/* Fill acl structure */\n\t\tacl->data_ipv6[acl->num_ipv6] = MBUF_IPV6_2PROTO(pkt);\n\t\tacl->m_ipv6[(acl->num_ipv6)++] = pkt;\n\n\t} else {\n\t\t/* Unknown type, drop the packet */\n\t\trte_pktmbuf_free(pkt);\n\t}\n}\n\n#else\nstatic inline void\nprepare_one_packet(struct rte_mbuf **pkts_in, struct acl_search_t *acl,\n\tint index)\n{\n\tstruct rte_mbuf *pkt = pkts_in[index];\n\n#ifdef RTE_NEXT_ABI\n\tif (RTE_ETH_IS_IPV4_HDR(pkt->packet_type)) {\n#else\n\tint type = pkt->ol_flags & (PKT_RX_IPV4_HDR | PKT_RX_IPV6_HDR);\n\n\tif (type == PKT_RX_IPV4_HDR) {\n#endif\n\t\t/* Fill acl structure */\n\t\tacl->data_ipv4[acl->num_ipv4] = MBUF_IPV4_2PROTO(pkt);\n\t\tacl->m_ipv4[(acl->num_ipv4)++] = pkt;\n\n#ifdef RTE_NEXT_ABI\n\t} else if (RTE_ETH_IS_IPV6_HDR(pkt->packet_type)) {\n#else\n\t} else if (type == PKT_RX_IPV6_HDR) {\n#endif\n\t\t/* Fill acl structure */\n\t\tacl->data_ipv6[acl->num_ipv6] = MBUF_IPV6_2PROTO(pkt);\n\t\tacl->m_ipv6[(acl->num_ipv6)++] = pkt;\n\t} else {\n\t\t/* Unknown type, drop the packet */\n\t\trte_pktmbuf_free(pkt);\n\t}\n}\n#endif /* DO_RFC_1812_CHECKS */\n\nstatic inline void\nprepare_acl_parameter(struct rte_mbuf **pkts_in, struct acl_search_t *acl,\n\tint nb_rx)\n{\n\tint i;\n\n\tacl->num_ipv4 = 0;\n\tacl->num_ipv6 = 0;\n\n\t/* Prefetch first packets */\n\tfor (i = 0; i < PREFETCH_OFFSET && i < nb_rx; i++) {\n\t\trte_prefetch0(rte_pktmbuf_mtod(\n\t\t\t\tpkts_in[i], void *));\n\t}\n\n\tfor (i = 0; i < (nb_rx - PREFETCH_OFFSET); i++) {\n\t\trte_prefetch0(rte_pktmbuf_mtod(pkts_in[\n\t\t\t\ti + PREFETCH_OFFSET], void *));\n\t\tprepare_one_packet(pkts_in, acl, i);\n\t}\n\n\t/* Process left packets */\n\tfor (; i < nb_rx; i++)\n\t\tprepare_one_packet(pkts_in, acl, i);\n}\n\nstatic inline void\nsend_one_packet(struct rte_mbuf *m, uint32_t res)\n{\n\tif (likely((res & ACL_DENY_SIGNATURE) == 0 && res != 0)) {\n\t\t/* forward packets */\n\t\tsend_single_packet(m,\n\t\t\t(uint8_t)(res - FWD_PORT_SHIFT));\n\t} else{\n\t\t/* in the ACL list, drop it */\n#ifdef L3FWDACL_DEBUG\n\t\tif ((res & ACL_DENY_SIGNATURE) != 0) {\n#ifdef RTE_NEXT_ABI\n\t\t\tif (RTE_ETH_IS_IPV4_HDR(m->packet_type))\n\t\t\t\tdump_acl4_rule(m, res);\n\t\t\telse if (RTE_ETH_IS_IPV6_HDR(m->packet_type))\n\t\t\t\tdump_acl6_rule(m, res);\n#else\n\t\t\tif (m->ol_flags & PKT_RX_IPV4_HDR)\n\t\t\t\tdump_acl4_rule(m, res);\n\t\t\telse\n\t\t\t\tdump_acl6_rule(m, res);\n#endif /* RTE_NEXT_ABI */\n\t\t}\n#endif\n\t\trte_pktmbuf_free(m);\n\t}\n}\n\n\n\nstatic inline void\nsend_packets(struct rte_mbuf **m, uint32_t *res, int num)\n{\n\tint i;\n\n\t/* Prefetch first packets */\n\tfor (i = 0; i < PREFETCH_OFFSET && i < num; i++) {\n\t\trte_prefetch0(rte_pktmbuf_mtod(\n\t\t\t\tm[i], void *));\n\t}\n\n\tfor (i = 0; i < (num - PREFETCH_OFFSET); i++) {\n\t\trte_prefetch0(rte_pktmbuf_mtod(m[\n\t\t\t\ti + PREFETCH_OFFSET], void *));\n\t\tsend_one_packet(m[i], res[i]);\n\t}\n\n\t/* Process left packets */\n\tfor (; i < num; i++)\n\t\tsend_one_packet(m[i], res[i]);\n}\n\n/*\n * Parses IPV6 address, exepcts the following format:\n * XXXX:XXXX:XXXX:XXXX:XXXX:XXXX:XXXX:XXXX (where X - is a hexedecimal digit).\n */\nstatic int\nparse_ipv6_addr(const char *in, const char **end, uint32_t v[IPV6_ADDR_U32],\n\tchar dlm)\n{\n\tuint32_t addr[IPV6_ADDR_U16];\n\n\tGET_CB_FIELD(in, addr[0], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[1], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[2], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[3], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[4], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[5], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[6], 16, UINT16_MAX, ':');\n\tGET_CB_FIELD(in, addr[7], 16, UINT16_MAX, dlm);\n\n\t*end = in;\n\n\tv[0] = (addr[0] << 16) + addr[1];\n\tv[1] = (addr[2] << 16) + addr[3];\n\tv[2] = (addr[4] << 16) + addr[5];\n\tv[3] = (addr[6] << 16) + addr[7];\n\n\treturn 0;\n}\n\nstatic int\nparse_ipv6_net(const char *in, struct rte_acl_field field[4])\n{\n\tint32_t rc;\n\tconst char *mp;\n\tuint32_t i, m, v[4];\n\tconst uint32_t nbu32 = sizeof(uint32_t) * CHAR_BIT;\n\n\t/* get address. */\n\trc = parse_ipv6_addr(in, &mp, v, '/');\n\tif (rc != 0)\n\t\treturn rc;\n\n\t/* get mask. */\n\tGET_CB_FIELD(mp, m, 0, CHAR_BIT * sizeof(v), 0);\n\n\t/* put all together. */\n\tfor (i = 0; i != RTE_DIM(v); i++) {\n\t\tif (m >= (i + 1) * nbu32)\n\t\t\tfield[i].mask_range.u32 = nbu32;\n\t\telse\n\t\t\tfield[i].mask_range.u32 = m > (i * nbu32) ?\n\t\t\t\tm - (i * 32) : 0;\n\n\t\tfield[i].value.u32 = v[i];\n\t}\n\n\treturn 0;\n}\n\nstatic int\nparse_cb_ipv6_rule(char *str, struct rte_acl_rule *v, int has_userdata)\n{\n\tint i, rc;\n\tchar *s, *sp, *in[CB_FLD_NUM];\n\tstatic const char *dlm = \" \\t\\n\";\n\tint dim = has_userdata ? CB_FLD_NUM : CB_FLD_USERDATA;\n\ts = str;\n\n\tfor (i = 0; i != dim; i++, s = NULL) {\n\t\tin[i] = strtok_r(s, dlm, &sp);\n\t\tif (in[i] == NULL)\n\t\t\treturn -EINVAL;\n\t}\n\n\trc = parse_ipv6_net(in[CB_FLD_SRC_ADDR], v->field + SRC1_FIELD_IPV6);\n\tif (rc != 0) {\n\t\tacl_log(\"failed to read source address/mask: %s\\n\",\n\t\t\tin[CB_FLD_SRC_ADDR]);\n\t\treturn rc;\n\t}\n\n\trc = parse_ipv6_net(in[CB_FLD_DST_ADDR], v->field + DST1_FIELD_IPV6);\n\tif (rc != 0) {\n\t\tacl_log(\"failed to read destination address/mask: %s\\n\",\n\t\t\tin[CB_FLD_DST_ADDR]);\n\t\treturn rc;\n\t}\n\n\t/* source port. */\n\tGET_CB_FIELD(in[CB_FLD_SRC_PORT_LOW],\n\t\tv->field[SRCP_FIELD_IPV6].value.u16,\n\t\t0, UINT16_MAX, 0);\n\tGET_CB_FIELD(in[CB_FLD_SRC_PORT_HIGH],\n\t\tv->field[SRCP_FIELD_IPV6].mask_range.u16,\n\t\t0, UINT16_MAX, 0);\n\n\tif (strncmp(in[CB_FLD_SRC_PORT_DLM], cb_port_delim,\n\t\t\tsizeof(cb_port_delim)) != 0)\n\t\treturn -EINVAL;\n\n\t/* destination port. */\n\tGET_CB_FIELD(in[CB_FLD_DST_PORT_LOW],\n\t\tv->field[DSTP_FIELD_IPV6].value.u16,\n\t\t0, UINT16_MAX, 0);\n\tGET_CB_FIELD(in[CB_FLD_DST_PORT_HIGH],\n\t\tv->field[DSTP_FIELD_IPV6].mask_range.u16,\n\t\t0, UINT16_MAX, 0);\n\n\tif (strncmp(in[CB_FLD_DST_PORT_DLM], cb_port_delim,\n\t\t\tsizeof(cb_port_delim)) != 0)\n\t\treturn -EINVAL;\n\n\tif (v->field[SRCP_FIELD_IPV6].mask_range.u16\n\t\t\t< v->field[SRCP_FIELD_IPV6].value.u16\n\t\t\t|| v->field[DSTP_FIELD_IPV6].mask_range.u16\n\t\t\t< v->field[DSTP_FIELD_IPV6].value.u16)\n\t\treturn -EINVAL;\n\n\tGET_CB_FIELD(in[CB_FLD_PROTO], v->field[PROTO_FIELD_IPV6].value.u8,\n\t\t0, UINT8_MAX, '/');\n\tGET_CB_FIELD(in[CB_FLD_PROTO], v->field[PROTO_FIELD_IPV6].mask_range.u8,\n\t\t0, UINT8_MAX, 0);\n\n\tif (has_userdata)\n\t\tGET_CB_FIELD(in[CB_FLD_USERDATA], v->data.userdata,\n\t\t\t0, UINT32_MAX, 0);\n\n\treturn 0;\n}\n\n/*\n * Parse ClassBench rules file.\n * Expected format:\n * '@''/' \\\n * '/' \\\n * \":\" \\\n * \":\" \\\n * '/'\n */\nstatic int\nparse_ipv4_net(const char *in, uint32_t *addr, uint32_t *mask_len)\n{\n\tuint8_t a, b, c, d, m;\n\n\tGET_CB_FIELD(in, a, 0, UINT8_MAX, '.');\n\tGET_CB_FIELD(in, b, 0, UINT8_MAX, '.');\n\tGET_CB_FIELD(in, c, 0, UINT8_MAX, '.');\n\tGET_CB_FIELD(in, d, 0, UINT8_MAX, '/');\n\tGET_CB_FIELD(in, m, 0, sizeof(uint32_t) * CHAR_BIT, 0);\n\n\taddr[0] = IPv4(a, b, c, d);\n\tmask_len[0] = m;\n\n\treturn 0;\n}\n\nstatic int\nparse_cb_ipv4vlan_rule(char *str, struct rte_acl_rule *v, int has_userdata)\n{\n\tint i, rc;\n\tchar *s, *sp, *in[CB_FLD_NUM];\n\tstatic const char *dlm = \" \\t\\n\";\n\tint dim = has_userdata ? CB_FLD_NUM : CB_FLD_USERDATA;\n\ts = str;\n\n\tfor (i = 0; i != dim; i++, s = NULL) {\n\t\tin[i] = strtok_r(s, dlm, &sp);\n\t\tif (in[i] == NULL)\n\t\t\treturn -EINVAL;\n\t}\n\n\trc = parse_ipv4_net(in[CB_FLD_SRC_ADDR],\n\t\t\t&v->field[SRC_FIELD_IPV4].value.u32,\n\t\t\t&v->field[SRC_FIELD_IPV4].mask_range.u32);\n\tif (rc != 0) {\n\t\t\tacl_log(\"failed to read source address/mask: %s\\n\",\n\t\t\tin[CB_FLD_SRC_ADDR]);\n\t\treturn rc;\n\t}\n\n\trc = parse_ipv4_net(in[CB_FLD_DST_ADDR],\n\t\t\t&v->field[DST_FIELD_IPV4].value.u32,\n\t\t\t&v->field[DST_FIELD_IPV4].mask_range.u32);\n\tif (rc != 0) {\n\t\tacl_log(\"failed to read destination address/mask: %s\\n\",\n\t\t\tin[CB_FLD_DST_ADDR]);\n\t\treturn rc;\n\t}\n\n\tGET_CB_FIELD(in[CB_FLD_SRC_PORT_LOW],\n\t\tv->field[SRCP_FIELD_IPV4].value.u16,\n\t\t0, UINT16_MAX, 0);\n\tGET_CB_FIELD(in[CB_FLD_SRC_PORT_HIGH],\n\t\tv->field[SRCP_FIELD_IPV4].mask_range.u16,\n\t\t0, UINT16_MAX, 0);\n\n\tif (strncmp(in[CB_FLD_SRC_PORT_DLM], cb_port_delim,\n\t\t\tsizeof(cb_port_delim)) != 0)\n\t\treturn -EINVAL;\n\n\tGET_CB_FIELD(in[CB_FLD_DST_PORT_LOW],\n\t\tv->field[DSTP_FIELD_IPV4].value.u16,\n\t\t0, UINT16_MAX, 0);\n\tGET_CB_FIELD(in[CB_FLD_DST_PORT_HIGH],\n\t\tv->field[DSTP_FIELD_IPV4].mask_range.u16,\n\t\t0, UINT16_MAX, 0);\n\n\tif (strncmp(in[CB_FLD_DST_PORT_DLM], cb_port_delim,\n\t\t\tsizeof(cb_port_delim)) != 0)\n\t\treturn -EINVAL;\n\n\tif (v->field[SRCP_FIELD_IPV4].mask_range.u16\n\t\t\t< v->field[SRCP_FIELD_IPV4].value.u16\n\t\t\t|| v->field[DSTP_FIELD_IPV4].mask_range.u16\n\t\t\t< v->field[DSTP_FIELD_IPV4].value.u16)\n\t\treturn -EINVAL;\n\n\tGET_CB_FIELD(in[CB_FLD_PROTO], v->field[PROTO_FIELD_IPV4].value.u8,\n\t\t0, UINT8_MAX, '/');\n\tGET_CB_FIELD(in[CB_FLD_PROTO], v->field[PROTO_FIELD_IPV4].mask_range.u8,\n\t\t0, UINT8_MAX, 0);\n\n\tif (has_userdata)\n\t\tGET_CB_FIELD(in[CB_FLD_USERDATA], v->data.userdata, 0,\n\t\t\tUINT32_MAX, 0);\n\n\treturn 0;\n}\n\nstatic int\nadd_rules(const char *rule_path,\n\t\tstruct rte_acl_rule **proute_base,\n\t\tunsigned int *proute_num,\n\t\tstruct rte_acl_rule **pacl_base,\n\t\tunsigned int *pacl_num, uint32_t rule_size,\n\t\tint (*parser)(char *, struct rte_acl_rule*, int))\n{\n\tuint8_t *acl_rules, *route_rules;\n\tstruct rte_acl_rule *next;\n\tunsigned int acl_num = 0, route_num = 0, total_num = 0;\n\tunsigned int acl_cnt = 0, route_cnt = 0;\n\tchar buff[LINE_MAX];\n\tFILE *fh = fopen(rule_path, \"rb\");\n\tunsigned int i = 0;\n\n\tif (fh == NULL)\n\t\trte_exit(EXIT_FAILURE, \"%s: Open %s failed\\n\", __func__,\n\t\t\trule_path);\n\n\twhile ((fgets(buff, LINE_MAX, fh) != NULL)) {\n\t\tif (buff[0] == ROUTE_LEAD_CHAR)\n\t\t\troute_num++;\n\t\telse if (buff[0] == ACL_LEAD_CHAR)\n\t\t\tacl_num++;\n\t}\n\n\tif (0 == route_num)\n\t\trte_exit(EXIT_FAILURE, \"Not find any route entries in %s!\\n\",\n\t\t\t\trule_path);\n\n\tfseek(fh, 0, SEEK_SET);\n\n\tacl_rules = calloc(acl_num, rule_size);\n\n\tif (NULL == acl_rules)\n\t\trte_exit(EXIT_FAILURE, \"%s: failed to malloc memory\\n\",\n\t\t\t__func__);\n\n\troute_rules = calloc(route_num, rule_size);\n\n\tif (NULL == route_rules)\n\t\trte_exit(EXIT_FAILURE, \"%s: failed to malloc memory\\n\",\n\t\t\t__func__);\n\n\ti = 0;\n\twhile (fgets(buff, LINE_MAX, fh) != NULL) {\n\t\ti++;\n\n\t\tif (is_bypass_line(buff))\n\t\t\tcontinue;\n\n\t\tchar s = buff[0];\n\n\t\t/* Route entry */\n\t\tif (s == ROUTE_LEAD_CHAR)\n\t\t\tnext = (struct rte_acl_rule *)(route_rules +\n\t\t\t\troute_cnt * rule_size);\n\n\t\t/* ACL entry */\n\t\telse if (s == ACL_LEAD_CHAR)\n\t\t\tnext = (struct rte_acl_rule *)(acl_rules +\n\t\t\t\tacl_cnt * rule_size);\n\n\t\t/* Illegal line */\n\t\telse\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"%s Line %u: should start with leading \"\n\t\t\t\t\"char %c or %c\\n\",\n\t\t\t\trule_path, i, ROUTE_LEAD_CHAR, ACL_LEAD_CHAR);\n\n\t\tif (parser(buff + 1, next, s == ROUTE_LEAD_CHAR) != 0)\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"%s Line %u: parse rules error\\n\",\n\t\t\t\trule_path, i);\n\n\t\tif (s == ROUTE_LEAD_CHAR) {\n\t\t\t/* Check the forwarding port number */\n\t\t\tif ((enabled_port_mask & (1 << next->data.userdata)) ==\n\t\t\t\t\t0)\n\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\"%s Line %u: fwd number illegal:%u\\n\",\n\t\t\t\t\trule_path, i, next->data.userdata);\n\t\t\tnext->data.userdata += FWD_PORT_SHIFT;\n\t\t\troute_cnt++;\n\t\t} else {\n\t\t\tnext->data.userdata = ACL_DENY_SIGNATURE + acl_cnt;\n\t\t\tacl_cnt++;\n\t\t}\n\n\t\tnext->data.priority = RTE_ACL_MAX_PRIORITY - total_num;\n\t\tnext->data.category_mask = -1;\n\t\ttotal_num++;\n\t}\n\n\tfclose(fh);\n\n\t*pacl_base = (struct rte_acl_rule *)acl_rules;\n\t*pacl_num = acl_num;\n\t*proute_base = (struct rte_acl_rule *)route_rules;\n\t*proute_num = route_cnt;\n\n\treturn 0;\n}\n\nstatic void\ndump_acl_config(void)\n{\n\tprintf(\"ACL option are:\\n\");\n\tprintf(OPTION_RULE_IPV4\": %s\\n\", parm_config.rule_ipv4_name);\n\tprintf(OPTION_RULE_IPV6\": %s\\n\", parm_config.rule_ipv6_name);\n\tprintf(OPTION_SCALAR\": %d\\n\", parm_config.scalar);\n}\n\nstatic int\ncheck_acl_config(void)\n{\n\tif (parm_config.rule_ipv4_name == NULL) {\n\t\tacl_log(\"ACL IPv4 rule file not specified\\n\");\n\t\treturn -1;\n\t} else if (parm_config.rule_ipv6_name == NULL) {\n\t\tacl_log(\"ACL IPv6 rule file not specified\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic struct rte_acl_ctx*\nsetup_acl(struct rte_acl_rule *route_base,\n\t\tstruct rte_acl_rule *acl_base, unsigned int route_num,\n\t\tunsigned int acl_num, int ipv6, int socketid)\n{\n\tchar name[PATH_MAX];\n\tstruct rte_acl_param acl_param;\n\tstruct rte_acl_config acl_build_param;\n\tstruct rte_acl_ctx *context;\n\tint dim = ipv6 ? RTE_DIM(ipv6_defs) : RTE_DIM(ipv4_defs);\n\n\t/* Create ACL contexts */\n\tsnprintf(name, sizeof(name), \"%s%d\",\n\t\t\tipv6 ? L3FWD_ACL_IPV6_NAME : L3FWD_ACL_IPV4_NAME,\n\t\t\tsocketid);\n\n\tacl_param.name = name;\n\tacl_param.socket_id = socketid;\n\tacl_param.rule_size = RTE_ACL_RULE_SZ(dim);\n\tacl_param.max_rule_num = MAX_ACL_RULE_NUM;\n\n\tif ((context = rte_acl_create(&acl_param)) == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Failed to create ACL context\\n\");\n\n\tif (parm_config.scalar && rte_acl_set_ctx_classify(context,\n\t\t\tRTE_ACL_CLASSIFY_SCALAR) != 0)\n\t\trte_exit(EXIT_FAILURE,\n\t\t\t\"Failed to setup classify method for ACL context\\n\");\n\n\tif (rte_acl_add_rules(context, route_base, route_num) < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"add rules failed\\n\");\n\n\tif (rte_acl_add_rules(context, acl_base, acl_num) < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"add rules failed\\n\");\n\n\t/* Perform builds */\n\tmemset(&acl_build_param, 0, sizeof(acl_build_param));\n\n\tacl_build_param.num_categories = DEFAULT_MAX_CATEGORIES;\n\tacl_build_param.num_fields = dim;\n\tmemcpy(&acl_build_param.defs, ipv6 ? ipv6_defs : ipv4_defs,\n\t\tipv6 ? sizeof(ipv6_defs) : sizeof(ipv4_defs));\n\n\tif (rte_acl_build(context, &acl_build_param) != 0)\n\t\trte_exit(EXIT_FAILURE, \"Failed to build ACL trie\\n\");\n\n\trte_acl_dump(context);\n\n\treturn context;\n}\n\nstatic int\napp_acl_init(void)\n{\n\tunsigned lcore_id;\n\tunsigned int i;\n\tint socketid;\n\tstruct rte_acl_rule *acl_base_ipv4, *route_base_ipv4,\n\t\t*acl_base_ipv6, *route_base_ipv6;\n\tunsigned int acl_num_ipv4 = 0, route_num_ipv4 = 0,\n\t\tacl_num_ipv6 = 0, route_num_ipv6 = 0;\n\n\tif (check_acl_config() != 0)\n\t\trte_exit(EXIT_FAILURE, \"Failed to get valid ACL options\\n\");\n\n\tdump_acl_config();\n\n\t/* Load rules from the input file */\n\tif (add_rules(parm_config.rule_ipv4_name, &route_base_ipv4,\n\t\t\t&route_num_ipv4, &acl_base_ipv4, &acl_num_ipv4,\n\t\t\tsizeof(struct acl4_rule), &parse_cb_ipv4vlan_rule) < 0)\n\t\trte_exit(EXIT_FAILURE, \"Failed to add rules\\n\");\n\n\tacl_log(\"IPv4 Route entries %u:\\n\", route_num_ipv4);\n\tdump_ipv4_rules((struct acl4_rule *)route_base_ipv4, route_num_ipv4, 1);\n\n\tacl_log(\"IPv4 ACL entries %u:\\n\", acl_num_ipv4);\n\tdump_ipv4_rules((struct acl4_rule *)acl_base_ipv4, acl_num_ipv4, 1);\n\n\tif (add_rules(parm_config.rule_ipv6_name, &route_base_ipv6,\n\t\t\t&route_num_ipv6,\n\t\t\t&acl_base_ipv6, &acl_num_ipv6,\n\t\t\tsizeof(struct acl6_rule), &parse_cb_ipv6_rule) < 0)\n\t\trte_exit(EXIT_FAILURE, \"Failed to add rules\\n\");\n\n\tacl_log(\"IPv6 Route entries %u:\\n\", route_num_ipv6);\n\tdump_ipv6_rules((struct acl6_rule *)route_base_ipv6, route_num_ipv6, 1);\n\n\tacl_log(\"IPv6 ACL entries %u:\\n\", acl_num_ipv6);\n\tdump_ipv6_rules((struct acl6_rule *)acl_base_ipv6, acl_num_ipv6, 1);\n\n\tmemset(&acl_config, 0, sizeof(acl_config));\n\n\t/* Check sockets a context should be created on */\n\tif (!numa_on)\n\t\tacl_config.mapped[0] = 1;\n\telse {\n\t\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tsocketid = rte_lcore_to_socket_id(lcore_id);\n\t\t\tif (socketid >= NB_SOCKETS) {\n\t\t\t\tacl_log(\"Socket %d of lcore %u is out \"\n\t\t\t\t\t\"of range %d\\n\",\n\t\t\t\t\tsocketid, lcore_id, NB_SOCKETS);\n\t\t\t\tfree(route_base_ipv4);\n\t\t\t\tfree(route_base_ipv6);\n\t\t\t\tfree(acl_base_ipv4);\n\t\t\t\tfree(acl_base_ipv6);\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tacl_config.mapped[socketid] = 1;\n\t\t}\n\t}\n\n\tfor (i = 0; i < NB_SOCKETS; i++) {\n\t\tif (acl_config.mapped[i]) {\n\t\t\tacl_config.acx_ipv4[i] = setup_acl(route_base_ipv4,\n\t\t\t\tacl_base_ipv4, route_num_ipv4, acl_num_ipv4,\n\t\t\t\t0, i);\n\n\t\t\tacl_config.acx_ipv6[i] = setup_acl(route_base_ipv6,\n\t\t\t\tacl_base_ipv6, route_num_ipv6, acl_num_ipv6,\n\t\t\t\t1, i);\n\t\t}\n\t}\n\n\tfree(route_base_ipv4);\n\tfree(route_base_ipv6);\n\n#ifdef L3FWDACL_DEBUG\n\tacl_config.rule_ipv4 = (struct acl4_rule *)acl_base_ipv4;\n\tacl_config.rule_ipv6 = (struct acl6_rule *)acl_base_ipv6;\n#else\n\tfree(acl_base_ipv4);\n\tfree(acl_base_ipv6);\n#endif\n\n\treturn 0;\n}\n\n/***********************end of ACL part******************************/\n\nstruct lcore_conf {\n\tuint16_t n_rx_queue;\n\tstruct lcore_rx_queue rx_queue_list[MAX_RX_QUEUE_PER_LCORE];\n\tuint16_t tx_queue_id[RTE_MAX_ETHPORTS];\n\tstruct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];\n} __rte_cache_aligned;\n\nstatic struct lcore_conf lcore_conf[RTE_MAX_LCORE];\n\n/* Send burst of packets on an output interface */\nstatic inline int\nsend_burst(struct lcore_conf *qconf, uint16_t n, uint8_t port)\n{\n\tstruct rte_mbuf **m_table;\n\tint ret;\n\tuint16_t queueid;\n\n\tqueueid = qconf->tx_queue_id[port];\n\tm_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;\n\n\tret = rte_eth_tx_burst(port, queueid, m_table, n);\n\tif (unlikely(ret < n)) {\n\t\tdo {\n\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t} while (++ret < n);\n\t}\n\n\treturn 0;\n}\n\n/* Enqueue a single packet, and send burst if queue is filled */\nstatic inline int\nsend_single_packet(struct rte_mbuf *m, uint8_t port)\n{\n\tuint32_t lcore_id;\n\tuint16_t len;\n\tstruct lcore_conf *qconf;\n\n\tlcore_id = rte_lcore_id();\n\n\tqconf = &lcore_conf[lcore_id];\n\tlen = qconf->tx_mbufs[port].len;\n\tqconf->tx_mbufs[port].m_table[len] = m;\n\tlen++;\n\n\t/* enough pkts to be sent */\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tsend_burst(qconf, MAX_PKT_BURST, port);\n\t\tlen = 0;\n\t}\n\n\tqconf->tx_mbufs[port].len = len;\n\treturn 0;\n}\n\n#ifdef DO_RFC_1812_CHECKS\nstatic inline int\nis_valid_ipv4_pkt(struct ipv4_hdr *pkt, uint32_t link_len)\n{\n\t/* From http://www.rfc-editor.org/rfc/rfc1812.txt section 5.2.2 */\n\t/*\n\t * 1. The packet length reported by the Link Layer must be large\n\t * enough to hold the minimum length legal IP datagram (20 bytes).\n\t */\n\tif (link_len < sizeof(struct ipv4_hdr))\n\t\treturn -1;\n\n\t/* 2. The IP checksum must be correct. */\n\t/* this is checked in H/W */\n\n\t/*\n\t * 3. The IP version number must be 4. If the version number is not 4\n\t * then the packet may be another version of IP, such as IPng or\n\t * ST-II.\n\t */\n\tif (((pkt->version_ihl) >> 4) != 4)\n\t\treturn -3;\n\t/*\n\t * 4. The IP header length field must be large enough to hold the\n\t * minimum length legal IP datagram (20 bytes = 5 words).\n\t */\n\tif ((pkt->version_ihl & 0xf) < 5)\n\t\treturn -4;\n\n\t/*\n\t * 5. The IP total length field must be large enough to hold the IP\n\t * datagram header, whose length is specified in the IP header length\n\t * field.\n\t */\n\tif (rte_cpu_to_be_16(pkt->total_length) < sizeof(struct ipv4_hdr))\n\t\treturn -5;\n\n\treturn 0;\n}\n#endif\n\n/* main processing loop */\nstatic int\nmain_loop(__attribute__((unused)) void *dummy)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tunsigned lcore_id;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc;\n\tint i, nb_rx;\n\tuint8_t portid, queueid;\n\tstruct lcore_conf *qconf;\n\tint socketid;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1)\n\t\t\t/ US_PER_S * BURST_TX_DRAIN_US;\n\n\tprev_tsc = 0;\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_conf[lcore_id];\n\tsocketid = rte_lcore_to_socket_id(lcore_id);\n\n\tif (qconf->n_rx_queue == 0) {\n\t\tRTE_LOG(INFO, L3FWD, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn 0;\n\t}\n\n\tRTE_LOG(INFO, L3FWD, \"entering main loop on lcore %u\\n\", lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_queue; i++) {\n\n\t\tportid = qconf->rx_queue_list[i].port_id;\n\t\tqueueid = qconf->rx_queue_list[i].queue_id;\n\t\tRTE_LOG(INFO, L3FWD,\n\t\t\t\" -- lcoreid=%u portid=%hhu rxqueueid=%hhu\\n\",\n\t\t\tlcore_id, portid, queueid);\n\t}\n\n\twhile (1) {\n\n\t\tcur_tsc = rte_rdtsc();\n\n\t\t/*\n\t\t * TX burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\t/*\n\t\t\t * This could be optimized (use queueid instead of\n\t\t\t * portid), but it is not called so often\n\t\t\t */\n\t\t\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t\t\tif (qconf->tx_mbufs[portid].len == 0)\n\t\t\t\t\tcontinue;\n\t\t\t\tsend_burst(&lcore_conf[lcore_id],\n\t\t\t\t\tqconf->tx_mbufs[portid].len,\n\t\t\t\t\tportid);\n\t\t\t\tqconf->tx_mbufs[portid].len = 0;\n\t\t\t}\n\n\t\t\tprev_tsc = cur_tsc;\n\t\t}\n\n\t\t/*\n\t\t * Read packet from RX queues\n\t\t */\n\t\tfor (i = 0; i < qconf->n_rx_queue; ++i) {\n\n\t\t\tportid = qconf->rx_queue_list[i].port_id;\n\t\t\tqueueid = qconf->rx_queue_list[i].queue_id;\n\t\t\tnb_rx = rte_eth_rx_burst(portid, queueid,\n\t\t\t\tpkts_burst, MAX_PKT_BURST);\n\n\t\t\tif (nb_rx > 0) {\n\t\t\t\tstruct acl_search_t acl_search;\n\n\t\t\t\tprepare_acl_parameter(pkts_burst, &acl_search,\n\t\t\t\t\tnb_rx);\n\n\t\t\t\tif (acl_search.num_ipv4) {\n\t\t\t\t\trte_acl_classify(\n\t\t\t\t\t\tacl_config.acx_ipv4[socketid],\n\t\t\t\t\t\tacl_search.data_ipv4,\n\t\t\t\t\t\tacl_search.res_ipv4,\n\t\t\t\t\t\tacl_search.num_ipv4,\n\t\t\t\t\t\tDEFAULT_MAX_CATEGORIES);\n\n\t\t\t\t\tsend_packets(acl_search.m_ipv4,\n\t\t\t\t\t\tacl_search.res_ipv4,\n\t\t\t\t\t\tacl_search.num_ipv4);\n\t\t\t\t}\n\n\t\t\t\tif (acl_search.num_ipv6) {\n\t\t\t\t\trte_acl_classify(\n\t\t\t\t\t\tacl_config.acx_ipv6[socketid],\n\t\t\t\t\t\tacl_search.data_ipv6,\n\t\t\t\t\t\tacl_search.res_ipv6,\n\t\t\t\t\t\tacl_search.num_ipv6,\n\t\t\t\t\t\tDEFAULT_MAX_CATEGORIES);\n\n\t\t\t\t\tsend_packets(acl_search.m_ipv6,\n\t\t\t\t\t\tacl_search.res_ipv6,\n\t\t\t\t\t\tacl_search.num_ipv6);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic int\ncheck_lcore_params(void)\n{\n\tuint8_t queue, lcore;\n\tuint16_t i;\n\tint socketid;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tqueue = lcore_params[i].queue_id;\n\t\tif (queue >= MAX_RX_QUEUE_PER_PORT) {\n\t\t\tprintf(\"invalid queue number: %hhu\\n\", queue);\n\t\t\treturn -1;\n\t\t}\n\t\tlcore = lcore_params[i].lcore_id;\n\t\tif (!rte_lcore_is_enabled(lcore)) {\n\t\t\tprintf(\"error: lcore %hhu is not enabled in \"\n\t\t\t\t\"lcore mask\\n\", lcore);\n\t\t\treturn -1;\n\t\t}\n\t\tsocketid = rte_lcore_to_socket_id(lcore);\n\t\tif (socketid != 0 && numa_on == 0) {\n\t\t\tprintf(\"warning: lcore %hhu is on socket %d \"\n\t\t\t\t\"with numa off\\n\",\n\t\t\t\tlcore, socketid);\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\ncheck_port_config(const unsigned nb_ports)\n{\n\tunsigned portid;\n\tuint16_t i;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tportid = lcore_params[i].port_id;\n\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"port %u is not enabled in port mask\\n\", portid);\n\t\t\treturn -1;\n\t\t}\n\t\tif (portid >= nb_ports) {\n\t\t\tprintf(\"port %u is not present on the board\\n\", portid);\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic uint8_t\nget_port_n_rx_queues(const uint8_t port)\n{\n\tint queue = -1;\n\tuint16_t i;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tif (lcore_params[i].port_id == port &&\n\t\t\t\tlcore_params[i].queue_id > queue)\n\t\t\tqueue = lcore_params[i].queue_id;\n\t}\n\treturn (uint8_t)(++queue);\n}\n\nstatic int\ninit_lcore_rx_queues(void)\n{\n\tuint16_t i, nb_rx_queue;\n\tuint8_t lcore;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tlcore = lcore_params[i].lcore_id;\n\t\tnb_rx_queue = lcore_conf[lcore].n_rx_queue;\n\t\tif (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) {\n\t\t\tprintf(\"error: too many queues (%u) for lcore: %u\\n\",\n\t\t\t\t(unsigned)nb_rx_queue + 1, (unsigned)lcore);\n\t\t\treturn -1;\n\t\t} else {\n\t\t\tlcore_conf[lcore].rx_queue_list[nb_rx_queue].port_id =\n\t\t\t\tlcore_params[i].port_id;\n\t\t\tlcore_conf[lcore].rx_queue_list[nb_rx_queue].queue_id =\n\t\t\t\tlcore_params[i].queue_id;\n\t\t\tlcore_conf[lcore].n_rx_queue++;\n\t\t}\n\t}\n\treturn 0;\n}\n\n/* display usage */\nstatic void\nprint_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK -P\"\n\t\t\"--\"OPTION_RULE_IPV4\"=FILE\"\n\t\t\"--\"OPTION_RULE_IPV6\"=FILE\"\n\t\t\" [--\"OPTION_CONFIG\" (port,queue,lcore)[,(port,queue,lcore]]\"\n\t\t\" [--\"OPTION_ENBJMO\" [--max-pkt-len PKTLEN]]\\n\"\n\t\t\" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t\t\" -P : enable promiscuous mode\\n\"\n\t\t\" --\"OPTION_CONFIG\": (port,queue,lcore): \"\n\t\t\"rx queues configuration\\n\"\n\t\t\" --\"OPTION_NONUMA\": optional, disable numa awareness\\n\"\n\t\t\" --\"OPTION_ENBJMO\": enable jumbo frame\"\n\t\t\" which max packet len is PKTLEN in decimal (64-9600)\\n\"\n\t\t\" --\"OPTION_RULE_IPV4\"=FILE: specify the ipv4 rules entries \"\n\t\t\"file. \"\n\t\t\"Each rule occupy one line. \"\n\t\t\"2 kinds of rules are supported. \"\n\t\t\"One is ACL entry at while line leads with character '%c', \"\n\t\t\"another is route entry at while line leads with \"\n\t\t\"character '%c'.\\n\"\n\t\t\" --\"OPTION_RULE_IPV6\"=FILE: specify the ipv6 rules \"\n\t\t\"entries file.\\n\"\n\t\t\" --\"OPTION_SCALAR\": Use scalar function to do lookup\\n\",\n\t\tprgname, ACL_LEAD_CHAR, ROUTE_LEAD_CHAR);\n}\n\nstatic int\nparse_max_pkt_len(const char *pktlen)\n{\n\tchar *end = NULL;\n\tunsigned long len;\n\n\t/* parse decimal string */\n\tlen = strtoul(pktlen, &end, 10);\n\tif ((pktlen[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (len == 0)\n\t\treturn -1;\n\n\treturn len;\n}\n\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\nstatic int\nparse_config(const char *q_arg)\n{\n\tchar s[256];\n\tconst char *p, *p0 = q_arg;\n\tchar *end;\n\tenum fieldnames {\n\t\tFLD_PORT = 0,\n\t\tFLD_QUEUE,\n\t\tFLD_LCORE,\n\t\t_NUM_FLD\n\t};\n\tunsigned long int_fld[_NUM_FLD];\n\tchar *str_fld[_NUM_FLD];\n\tint i;\n\tunsigned size;\n\n\tnb_lcore_params = 0;\n\n\twhile ((p = strchr(p0, '(')) != NULL) {\n\t\t++p;\n\t\tif ((p0 = strchr(p, ')')) == NULL)\n\t\t\treturn -1;\n\n\t\tsize = p0 - p;\n\t\tif (size >= sizeof(s))\n\t\t\treturn -1;\n\n\t\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\t\tif (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') !=\n\t\t\t\t_NUM_FLD)\n\t\t\treturn -1;\n\t\tfor (i = 0; i < _NUM_FLD; i++) {\n\t\t\terrno = 0;\n\t\t\tint_fld[i] = strtoul(str_fld[i], &end, 0);\n\t\t\tif (errno != 0 || end == str_fld[i] || int_fld[i] > 255)\n\t\t\t\treturn -1;\n\t\t}\n\t\tif (nb_lcore_params >= MAX_LCORE_PARAMS) {\n\t\t\tprintf(\"exceeded max number of lcore params: %hu\\n\",\n\t\t\t\tnb_lcore_params);\n\t\t\treturn -1;\n\t\t}\n\t\tlcore_params_array[nb_lcore_params].port_id =\n\t\t\t(uint8_t)int_fld[FLD_PORT];\n\t\tlcore_params_array[nb_lcore_params].queue_id =\n\t\t\t(uint8_t)int_fld[FLD_QUEUE];\n\t\tlcore_params_array[nb_lcore_params].lcore_id =\n\t\t\t(uint8_t)int_fld[FLD_LCORE];\n\t\t++nb_lcore_params;\n\t}\n\tlcore_params = lcore_params_array;\n\treturn 0;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{OPTION_CONFIG, 1, 0, 0},\n\t\t{OPTION_NONUMA, 0, 0, 0},\n\t\t{OPTION_ENBJMO, 0, 0, 0},\n\t\t{OPTION_RULE_IPV4, 1, 0, 0},\n\t\t{OPTION_RULE_IPV6, 1, 0, 0},\n\t\t{OPTION_SCALAR, 0, 0, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:P\",\n\t\t\t\tlgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'P':\n\t\t\tprintf(\"Promiscuous mode selected\\n\");\n\t\t\tpromiscuous_on = 1;\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tif (!strncmp(lgopts[option_index].name,\n\t\t\t\t\tOPTION_CONFIG,\n\t\t\t\t\tsizeof(OPTION_CONFIG))) {\n\t\t\t\tret = parse_config(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"invalid config\\n\");\n\t\t\t\t\tprint_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (!strncmp(lgopts[option_index].name,\n\t\t\t\t\tOPTION_NONUMA,\n\t\t\t\t\tsizeof(OPTION_NONUMA))) {\n\t\t\t\tprintf(\"numa is disabled\\n\");\n\t\t\t\tnuma_on = 0;\n\t\t\t}\n\n\t\t\tif (!strncmp(lgopts[option_index].name,\n\t\t\t\t\tOPTION_ENBJMO, sizeof(OPTION_ENBJMO))) {\n\t\t\t\tstruct option lenopts = {\n\t\t\t\t\t\"max-pkt-len\",\n\t\t\t\t\trequired_argument,\n\t\t\t\t\t0,\n\t\t\t\t\t0\n\t\t\t\t};\n\n\t\t\t\tprintf(\"jumbo frame is enabled\\n\");\n\t\t\t\tport_conf.rxmode.jumbo_frame = 1;\n\n\t\t\t\t/*\n\t\t\t\t * if no max-pkt-len set, then use the\n\t\t\t\t * default value ETHER_MAX_LEN\n\t\t\t\t */\n\t\t\t\tif (0 == getopt_long(argc, argvopt, \"\",\n\t\t\t\t\t\t&lenopts, &option_index)) {\n\t\t\t\t\tret = parse_max_pkt_len(optarg);\n\t\t\t\t\tif ((ret < 64) ||\n\t\t\t\t\t\t(ret > MAX_JUMBO_PKT_LEN)) {\n\t\t\t\t\t\tprintf(\"invalid packet \"\n\t\t\t\t\t\t\t\"length\\n\");\n\t\t\t\t\t\tprint_usage(prgname);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\tport_conf.rxmode.max_rx_pkt_len = ret;\n\t\t\t\t}\n\t\t\t\tprintf(\"set jumbo frame max packet length \"\n\t\t\t\t\t\"to %u\\n\",\n\t\t\t\t\t(unsigned int)\n\t\t\t\t\tport_conf.rxmode.max_rx_pkt_len);\n\t\t\t}\n\n\t\t\tif (!strncmp(lgopts[option_index].name,\n\t\t\t\t\tOPTION_RULE_IPV4,\n\t\t\t\t\tsizeof(OPTION_RULE_IPV4)))\n\t\t\t\tparm_config.rule_ipv4_name = optarg;\n\n\t\t\tif (!strncmp(lgopts[option_index].name,\n\t\t\t\t\tOPTION_RULE_IPV6,\n\t\t\t\t\tsizeof(OPTION_RULE_IPV6))) {\n\t\t\t\tparm_config.rule_ipv6_name = optarg;\n\t\t\t}\n\n\t\t\tif (!strncmp(lgopts[option_index].name,\n\t\t\t\t\tOPTION_SCALAR, sizeof(OPTION_SCALAR)))\n\t\t\t\tparm_config.scalar = 1;\n\n\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\nstatic void\nprint_ethaddr(const char *name, const struct ether_addr *eth_addr)\n{\n\tchar buf[ETHER_ADDR_FMT_SIZE];\n\tether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);\n\tprintf(\"%s%s\", name, buf);\n}\n\nstatic int\ninit_mem(unsigned nb_mbuf)\n{\n\tint socketid;\n\tunsigned lcore_id;\n\tchar s[64];\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\tcontinue;\n\n\t\tif (numa_on)\n\t\t\tsocketid = rte_lcore_to_socket_id(lcore_id);\n\t\telse\n\t\t\tsocketid = 0;\n\n\t\tif (socketid >= NB_SOCKETS) {\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"Socket %d of lcore %u is out of range %d\\n\",\n\t\t\t\tsocketid, lcore_id, NB_SOCKETS);\n\t\t}\n\t\tif (pktmbuf_pool[socketid] == NULL) {\n\t\t\tsnprintf(s, sizeof(s), \"mbuf_pool_%d\", socketid);\n\t\t\tpktmbuf_pool[socketid] =\n\t\t\t\trte_pktmbuf_pool_create(s, nb_mbuf,\n\t\t\t\t\tMEMPOOL_CACHE_SIZE, 0,\n\t\t\t\t\tRTE_MBUF_DEFAULT_BUF_SIZE,\n\t\t\t\t\tsocketid);\n\t\t\tif (pktmbuf_pool[socketid] == NULL)\n\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\"Cannot init mbuf pool on socket %d\\n\",\n\t\t\t\t\tsocketid);\n\t\t\telse\n\t\t\t\tprintf(\"Allocated mbuf pool on socket %d\\n\",\n\t\t\t\t\tsocketid);\n\t\t}\n\t}\n\treturn 0;\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_conf *qconf;\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_txconf *txconf;\n\tint ret;\n\tunsigned nb_ports;\n\tuint16_t queueid;\n\tunsigned lcore_id;\n\tuint32_t n_tx_queue, nb_lcores;\n\tuint8_t portid, nb_rx_queue, queue, socketid;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid EAL parameters\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid L3FWD parameters\\n\");\n\n\tif (check_lcore_params() < 0)\n\t\trte_exit(EXIT_FAILURE, \"check_lcore_params failed\\n\");\n\n\tret = init_lcore_rx_queues();\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"init_lcore_rx_queues failed\\n\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\tif (check_port_config(nb_ports) < 0)\n\t\trte_exit(EXIT_FAILURE, \"check_port_config failed\\n\");\n\n\t/* Add ACL rules and route entries, build trie */\n\tif (app_acl_init() < 0)\n\t\trte_exit(EXIT_FAILURE, \"app_acl_init failed\\n\");\n\n\tnb_lcores = rte_lcore_count();\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"\\nSkipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* init port */\n\t\tprintf(\"Initializing port %d ... \", portid);\n\t\tfflush(stdout);\n\n\t\tnb_rx_queue = get_port_n_rx_queues(portid);\n\t\tn_tx_queue = nb_lcores;\n\t\tif (n_tx_queue > MAX_TX_QUEUE_PER_PORT)\n\t\t\tn_tx_queue = MAX_TX_QUEUE_PER_PORT;\n\t\tprintf(\"Creating queues: nb_rxq=%d nb_txq=%u... \",\n\t\t\tnb_rx_queue, (unsigned)n_tx_queue);\n\t\tret = rte_eth_dev_configure(portid, nb_rx_queue,\n\t\t\t\t\t(uint16_t)n_tx_queue, &port_conf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"Cannot configure device: err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\n\t\trte_eth_macaddr_get(portid, &ports_eth_addr[portid]);\n\t\tprint_ethaddr(\" Address:\", &ports_eth_addr[portid]);\n\t\tprintf(\", \");\n\n\t\t/* init memory */\n\t\tret = init_mem(NB_MBUF);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"init_mem failed\\n\");\n\n\t\t/* init one TX queue per couple (lcore,port) */\n\t\tqueueid = 0;\n\t\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (numa_on)\n\t\t\t\tsocketid = (uint8_t)\n\t\t\t\t\trte_lcore_to_socket_id(lcore_id);\n\t\t\telse\n\t\t\t\tsocketid = 0;\n\n\t\t\tprintf(\"txq=%u,%d,%d \", lcore_id, queueid, socketid);\n\t\t\tfflush(stdout);\n\n\t\t\trte_eth_dev_info_get(portid, &dev_info);\n\t\t\ttxconf = &dev_info.default_txconf;\n\t\t\tif (port_conf.rxmode.jumbo_frame)\n\t\t\t\ttxconf->txq_flags = 0;\n\t\t\tret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,\n\t\t\t\t\t\t socketid, txconf);\n\t\t\tif (ret < 0)\n\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\"rte_eth_tx_queue_setup: err=%d, \"\n\t\t\t\t\t\"port=%d\\n\", ret, portid);\n\n\t\t\tqconf = &lcore_conf[lcore_id];\n\t\t\tqconf->tx_queue_id[portid] = queueid;\n\t\t\tqueueid++;\n\t\t}\n\t\tprintf(\"\\n\");\n\t}\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\tcontinue;\n\t\tqconf = &lcore_conf[lcore_id];\n\t\tprintf(\"\\nInitializing rx queues on lcore %u ... \", lcore_id);\n\t\tfflush(stdout);\n\t\t/* init RX queues */\n\t\tfor (queue = 0; queue < qconf->n_rx_queue; ++queue) {\n\t\t\tportid = qconf->rx_queue_list[queue].port_id;\n\t\t\tqueueid = qconf->rx_queue_list[queue].queue_id;\n\n\t\t\tif (numa_on)\n\t\t\t\tsocketid = (uint8_t)\n\t\t\t\t\trte_lcore_to_socket_id(lcore_id);\n\t\t\telse\n\t\t\t\tsocketid = 0;\n\n\t\t\tprintf(\"rxq=%d,%d,%d \", portid, queueid, socketid);\n\t\t\tfflush(stdout);\n\n\t\t\tret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd,\n\t\t\t\t\tsocketid, NULL,\n\t\t\t\t\tpktmbuf_pool[socketid]);\n\t\t\tif (ret < 0)\n\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\"rte_eth_rx_queue_setup: err=%d,\"\n\t\t\t\t\t\"port=%d\\n\", ret, portid);\n\t\t}\n\t}\n\n\tprintf(\"\\n\");\n\n\t/* start ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tif ((enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"rte_eth_dev_start: err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\n\t\t/*\n\t\t * If enabled, put device in promiscuous mode.\n\t\t * This allows IO forwarding mode to forward packets\n\t\t * to itself through 2 cross-connected ports of the\n\t\t * target machine.\n\t\t */\n\t\tif (promiscuous_on)\n\t\t\trte_eth_promiscuous_enable(portid);\n\t}\n\n\tcheck_all_ports_link_status((uint8_t)nb_ports, enabled_port_mask);\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/l3fwd-power/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = l3fwd-power\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/l3fwd-power/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define RTE_LOGTYPE_L3FWD_POWER RTE_LOGTYPE_USER1\n\n#define MAX_PKT_BURST 32\n\n#define MIN_ZERO_POLL_COUNT 10\n\n/* around 100ms at 2 Ghz */\n#define TIMER_RESOLUTION_CYCLES 200000000ULL\n/* 100 ms interval */\n#define TIMER_NUMBER_PER_SECOND 10\n/* 100000 us */\n#define SCALING_PERIOD (1000000/TIMER_NUMBER_PER_SECOND)\n#define SCALING_DOWN_TIME_RATIO_THRESHOLD 0.25\n\n#define APP_LOOKUP_EXACT_MATCH 0\n#define APP_LOOKUP_LPM 1\n#define DO_RFC_1812_CHECKS\n\n#ifndef APP_LOOKUP_METHOD\n#define APP_LOOKUP_METHOD APP_LOOKUP_LPM\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n#include \n#elif (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\n#include \n#else\n#error \"APP_LOOKUP_METHOD set to incorrect value\"\n#endif\n\n#ifndef IPv6_BYTES\n#define IPv6_BYTES_FMT \"%02x%02x:%02x%02x:%02x%02x:%02x%02x:\"\\\n \"%02x%02x:%02x%02x:%02x%02x:%02x%02x\"\n#define IPv6_BYTES(addr) \\\n\taddr[0], addr[1], addr[2], addr[3], \\\n\taddr[4], addr[5], addr[6], addr[7], \\\n\taddr[8], addr[9], addr[10], addr[11],\\\n\taddr[12], addr[13],addr[14], addr[15]\n#endif\n\n#define MAX_JUMBO_PKT_LEN 9600\n\n#define IPV6_ADDR_LEN 16\n\n#define MEMPOOL_CACHE_SIZE 256\n\n/*\n * This expression is used to calculate the number of mbufs needed depending on\n * user input, taking into account memory for rx and tx hardware rings, cache\n * per lcore and mtable per port per lcore. RTE_MAX is used to ensure that\n * NB_MBUF never goes below a minimum value of 8192.\n */\n\n#define NB_MBUF RTE_MAX\t( \\\n\t(nb_ports*nb_rx_queue*RTE_TEST_RX_DESC_DEFAULT + \\\n\tnb_ports*nb_lcores*MAX_PKT_BURST + \\\n\tnb_ports*n_tx_queue*RTE_TEST_TX_DESC_DEFAULT + \\\n\tnb_lcores*MEMPOOL_CACHE_SIZE), \\\n\t(unsigned)8192)\n\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n#define NB_SOCKETS 8\n\n/* Configure how many packets ahead to prefetch, when reading packets */\n#define PREFETCH_OFFSET\t3\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n/* ethernet addresses of ports */\nstatic struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];\n\n/* ethernet addresses of ports */\nstatic rte_spinlock_t locks[RTE_MAX_ETHPORTS];\n\n/* mask of enabled ports */\nstatic uint32_t enabled_port_mask = 0;\n/* Ports set in promiscuous mode off by default. */\nstatic int promiscuous_on = 0;\n/* NUMA is enabled by default. */\nstatic int numa_on = 1;\n\nenum freq_scale_hint_t\n{\n\tFREQ_LOWER = -1,\n\tFREQ_CURRENT = 0,\n\tFREQ_HIGHER = 1,\n\tFREQ_HIGHEST = 2\n};\n\nstruct mbuf_table {\n\tuint16_t len;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST];\n};\n\nstruct lcore_rx_queue {\n\tuint8_t port_id;\n\tuint8_t queue_id;\n\tenum freq_scale_hint_t freq_up_hint;\n\tuint32_t zero_rx_packet_count;\n\tuint32_t idle_hint;\n} __rte_cache_aligned;\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT RTE_MAX_ETHPORTS\n#define MAX_RX_QUEUE_PER_PORT 128\n\n#define MAX_RX_QUEUE_INTERRUPT_PER_PORT 16\n\n\n#define MAX_LCORE_PARAMS 1024\nstruct lcore_params {\n\tuint8_t port_id;\n\tuint8_t queue_id;\n\tuint8_t lcore_id;\n} __rte_cache_aligned;\n\nstatic struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];\nstatic struct lcore_params lcore_params_array_default[] = {\n\t{0, 0, 2},\n\t{0, 1, 2},\n\t{0, 2, 2},\n\t{1, 0, 2},\n\t{1, 1, 2},\n\t{1, 2, 2},\n\t{2, 0, 2},\n\t{3, 0, 3},\n\t{3, 1, 3},\n};\n\nstatic struct lcore_params * lcore_params = lcore_params_array_default;\nstatic uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /\n\t\t\t\tsizeof(lcore_params_array_default[0]);\n\nstatic struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.mq_mode = ETH_MQ_RX_RSS,\n\t\t.max_rx_pkt_len = ETHER_MAX_LEN,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 1, /**< IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.rx_adv_conf = {\n\t\t.rss_conf = {\n\t\t\t.rss_key = NULL,\n\t\t\t.rss_hf = ETH_RSS_UDP,\n\t\t},\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n\t.intr_conf = {\n\t\t.lsc = 1,\n#ifdef RTE_NEXT_ABI\n\t\t.rxq = 1,\n#endif\n\t},\n};\n\nstatic struct rte_mempool * pktmbuf_pool[NB_SOCKETS];\n\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n\n#ifdef RTE_MACHINE_CPUFLAG_SSE4_2\n#include \n#define DEFAULT_HASH_FUNC rte_hash_crc\n#else\n#include \n#define DEFAULT_HASH_FUNC rte_jhash\n#endif\n\nstruct ipv4_5tuple {\n\tuint32_t ip_dst;\n\tuint32_t ip_src;\n\tuint16_t port_dst;\n\tuint16_t port_src;\n\tuint8_t proto;\n} __attribute__((__packed__));\n\nstruct ipv6_5tuple {\n\tuint8_t ip_dst[IPV6_ADDR_LEN];\n\tuint8_t ip_src[IPV6_ADDR_LEN];\n\tuint16_t port_dst;\n\tuint16_t port_src;\n\tuint8_t proto;\n} __attribute__((__packed__));\n\nstruct ipv4_l3fwd_route {\n\tstruct ipv4_5tuple key;\n\tuint8_t if_out;\n};\n\nstruct ipv6_l3fwd_route {\n\tstruct ipv6_5tuple key;\n\tuint8_t if_out;\n};\n\nstatic struct ipv4_l3fwd_route ipv4_l3fwd_route_array[] = {\n\t{{IPv4(100,10,0,1), IPv4(200,10,0,1), 101, 11, IPPROTO_TCP}, 0},\n\t{{IPv4(100,20,0,2), IPv4(200,20,0,2), 102, 12, IPPROTO_TCP}, 1},\n\t{{IPv4(100,30,0,3), IPv4(200,30,0,3), 103, 13, IPPROTO_TCP}, 2},\n\t{{IPv4(100,40,0,4), IPv4(200,40,0,4), 104, 14, IPPROTO_TCP}, 3},\n};\n\nstatic struct ipv6_l3fwd_route ipv6_l3fwd_route_array[] = {\n\t{\n\t\t{\n\t\t\t{0xfe, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t\t 0x02, 0x1b, 0x21, 0xff, 0xfe, 0x91, 0x38, 0x05},\n\t\t\t{0xfe, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\t\t\t 0x02, 0x1e, 0x67, 0xff, 0xfe, 0x0d, 0xb6, 0x0a},\n\t\t\t 1, 10, IPPROTO_UDP\n\t\t}, 4\n\t},\n};\n\ntypedef struct rte_hash lookup_struct_t;\nstatic lookup_struct_t *ipv4_l3fwd_lookup_struct[NB_SOCKETS];\nstatic lookup_struct_t *ipv6_l3fwd_lookup_struct[NB_SOCKETS];\n\n#define L3FWD_HASH_ENTRIES\t1024\n\n#define IPV4_L3FWD_NUM_ROUTES \\\n\t(sizeof(ipv4_l3fwd_route_array) / sizeof(ipv4_l3fwd_route_array[0]))\n\n#define IPV6_L3FWD_NUM_ROUTES \\\n\t(sizeof(ipv6_l3fwd_route_array) / sizeof(ipv6_l3fwd_route_array[0]))\n\nstatic uint8_t ipv4_l3fwd_out_if[L3FWD_HASH_ENTRIES] __rte_cache_aligned;\nstatic uint8_t ipv6_l3fwd_out_if[L3FWD_HASH_ENTRIES] __rte_cache_aligned;\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\nstruct ipv4_l3fwd_route {\n\tuint32_t ip;\n\tuint8_t depth;\n\tuint8_t if_out;\n};\n\nstatic struct ipv4_l3fwd_route ipv4_l3fwd_route_array[] = {\n\t{IPv4(1,1,1,0), 24, 0},\n\t{IPv4(2,1,1,0), 24, 1},\n\t{IPv4(3,1,1,0), 24, 2},\n\t{IPv4(4,1,1,0), 24, 3},\n\t{IPv4(5,1,1,0), 24, 4},\n\t{IPv4(6,1,1,0), 24, 5},\n\t{IPv4(7,1,1,0), 24, 6},\n\t{IPv4(8,1,1,0), 24, 7},\n};\n\n#define IPV4_L3FWD_NUM_ROUTES \\\n\t(sizeof(ipv4_l3fwd_route_array) / sizeof(ipv4_l3fwd_route_array[0]))\n\n#define IPV4_L3FWD_LPM_MAX_RULES 1024\n\ntypedef struct rte_lpm lookup_struct_t;\nstatic lookup_struct_t *ipv4_l3fwd_lookup_struct[NB_SOCKETS];\n#endif\n\nstruct lcore_conf {\n\tuint16_t n_rx_queue;\n\tstruct lcore_rx_queue rx_queue_list[MAX_RX_QUEUE_PER_LCORE];\n\tuint16_t tx_queue_id[RTE_MAX_ETHPORTS];\n\tstruct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];\n\tlookup_struct_t * ipv4_lookup_struct;\n\tlookup_struct_t * ipv6_lookup_struct;\n} __rte_cache_aligned;\n\nstruct lcore_stats {\n\t/* total sleep time in ms since last frequency scaling down */\n\tuint32_t sleep_time;\n\t/* number of long sleep recently */\n\tuint32_t nb_long_sleep;\n\t/* freq. scaling up trend */\n\tuint32_t trend;\n\t/* total packet processed recently */\n\tuint64_t nb_rx_processed;\n\t/* total iterations looped recently */\n\tuint64_t nb_iteration_looped;\n\tuint32_t padding[9];\n} __rte_cache_aligned;\n\nstatic struct lcore_conf lcore_conf[RTE_MAX_LCORE] __rte_cache_aligned;\nstatic struct lcore_stats stats[RTE_MAX_LCORE] __rte_cache_aligned;\nstatic struct rte_timer power_timers[RTE_MAX_LCORE];\n\nstatic inline uint32_t power_idle_heuristic(uint32_t zero_rx_packet_count);\nstatic inline enum freq_scale_hint_t power_freq_scaleup_heuristic( \\\n\t\t\tunsigned lcore_id, uint8_t port_id, uint16_t queue_id);\n\n/* exit signal handler */\nstatic void\nsignal_exit_now(int sigtype)\n{\n\tunsigned lcore_id;\n\tint ret;\n\n\tif (sigtype == SIGINT) {\n\t\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\t\tcontinue;\n\n\t\t\t/* init power management library */\n\t\t\tret = rte_power_exit(lcore_id);\n\t\t\tif (ret)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Power management \"\n\t\t\t\t\t\"library de-initialization failed on \"\n\t\t\t\t\t\t\t\"core%u\\n\", lcore_id);\n\t\t}\n\t}\n\n\trte_exit(EXIT_SUCCESS, \"User forced exit\\n\");\n}\n\n/* Freqency scale down timer callback */\nstatic void\npower_timer_cb(__attribute__((unused)) struct rte_timer *tim,\n\t\t\t __attribute__((unused)) void *arg)\n{\n\tuint64_t hz;\n\tfloat sleep_time_ratio;\n\tunsigned lcore_id = rte_lcore_id();\n\n\t/* accumulate total execution time in us when callback is invoked */\n\tsleep_time_ratio = (float)(stats[lcore_id].sleep_time) /\n\t\t\t\t\t(float)SCALING_PERIOD;\n\t/**\n\t * check whether need to scale down frequency a step if it sleep a lot.\n\t */\n\tif (sleep_time_ratio >= SCALING_DOWN_TIME_RATIO_THRESHOLD) {\n\t\tif (rte_power_freq_down)\n\t\t\trte_power_freq_down(lcore_id);\n\t}\n\telse if ( (unsigned)(stats[lcore_id].nb_rx_processed /\n\t\tstats[lcore_id].nb_iteration_looped) < MAX_PKT_BURST) {\n\t\t/**\n\t\t * scale down a step if average packet per iteration less\n\t\t * than expectation.\n\t\t */\n\t\tif (rte_power_freq_down)\n\t\t\trte_power_freq_down(lcore_id);\n\t}\n\n\t/**\n\t * initialize another timer according to current frequency to ensure\n\t * timer interval is relatively fixed.\n\t */\n\thz = rte_get_timer_hz();\n\trte_timer_reset(&power_timers[lcore_id], hz/TIMER_NUMBER_PER_SECOND,\n\t\t\t\tSINGLE, lcore_id, power_timer_cb, NULL);\n\n\tstats[lcore_id].nb_rx_processed = 0;\n\tstats[lcore_id].nb_iteration_looped = 0;\n\n\tstats[lcore_id].sleep_time = 0;\n}\n\n/* Send burst of packets on an output interface */\nstatic inline int\nsend_burst(struct lcore_conf *qconf, uint16_t n, uint8_t port)\n{\n\tstruct rte_mbuf **m_table;\n\tint ret;\n\tuint16_t queueid;\n\n\tqueueid = qconf->tx_queue_id[port];\n\tm_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;\n\n\tret = rte_eth_tx_burst(port, queueid, m_table, n);\n\tif (unlikely(ret < n)) {\n\t\tdo {\n\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t} while (++ret < n);\n\t}\n\n\treturn 0;\n}\n\n/* Enqueue a single packet, and send burst if queue is filled */\nstatic inline int\nsend_single_packet(struct rte_mbuf *m, uint8_t port)\n{\n\tuint32_t lcore_id;\n\tuint16_t len;\n\tstruct lcore_conf *qconf;\n\n\tlcore_id = rte_lcore_id();\n\n\tqconf = &lcore_conf[lcore_id];\n\tlen = qconf->tx_mbufs[port].len;\n\tqconf->tx_mbufs[port].m_table[len] = m;\n\tlen++;\n\n\t/* enough pkts to be sent */\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tsend_burst(qconf, MAX_PKT_BURST, port);\n\t\tlen = 0;\n\t}\n\n\tqconf->tx_mbufs[port].len = len;\n\treturn 0;\n}\n\n#ifdef DO_RFC_1812_CHECKS\nstatic inline int\nis_valid_ipv4_pkt(struct ipv4_hdr *pkt, uint32_t link_len)\n{\n\t/* From http://www.rfc-editor.org/rfc/rfc1812.txt section 5.2.2 */\n\t/*\n\t * 1. The packet length reported by the Link Layer must be large\n\t * enough to hold the minimum length legal IP datagram (20 bytes).\n\t */\n\tif (link_len < sizeof(struct ipv4_hdr))\n\t\treturn -1;\n\n\t/* 2. The IP checksum must be correct. */\n\t/* this is checked in H/W */\n\n\t/*\n\t * 3. The IP version number must be 4. If the version number is not 4\n\t * then the packet may be another version of IP, such as IPng or\n\t * ST-II.\n\t */\n\tif (((pkt->version_ihl) >> 4) != 4)\n\t\treturn -3;\n\t/*\n\t * 4. The IP header length field must be large enough to hold the\n\t * minimum length legal IP datagram (20 bytes = 5 words).\n\t */\n\tif ((pkt->version_ihl & 0xf) < 5)\n\t\treturn -4;\n\n\t/*\n\t * 5. The IP total length field must be large enough to hold the IP\n\t * datagram header, whose length is specified in the IP header length\n\t * field.\n\t */\n\tif (rte_cpu_to_be_16(pkt->total_length) < sizeof(struct ipv4_hdr))\n\t\treturn -5;\n\n\treturn 0;\n}\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\nstatic void\nprint_ipv4_key(struct ipv4_5tuple key)\n{\n\tprintf(\"IP dst = %08x, IP src = %08x, port dst = %d, port src = %d, \"\n\t\t\"proto = %d\\n\", (unsigned)key.ip_dst, (unsigned)key.ip_src,\n\t\t\t\tkey.port_dst, key.port_src, key.proto);\n}\nstatic void\nprint_ipv6_key(struct ipv6_5tuple key)\n{\n\tprintf( \"IP dst = \" IPv6_BYTES_FMT \", IP src = \" IPv6_BYTES_FMT \", \"\n\t \"port dst = %d, port src = %d, proto = %d\\n\",\n\t IPv6_BYTES(key.ip_dst), IPv6_BYTES(key.ip_src),\n\t key.port_dst, key.port_src, key.proto);\n}\n\nstatic inline uint8_t\nget_ipv4_dst_port(struct ipv4_hdr *ipv4_hdr, uint8_t portid,\n\t\tlookup_struct_t * ipv4_l3fwd_lookup_struct)\n{\n\tstruct ipv4_5tuple key;\n\tstruct tcp_hdr *tcp;\n\tstruct udp_hdr *udp;\n\tint ret = 0;\n\n\tkey.ip_dst = rte_be_to_cpu_32(ipv4_hdr->dst_addr);\n\tkey.ip_src = rte_be_to_cpu_32(ipv4_hdr->src_addr);\n\tkey.proto = ipv4_hdr->next_proto_id;\n\n\tswitch (ipv4_hdr->next_proto_id) {\n\tcase IPPROTO_TCP:\n\t\ttcp = (struct tcp_hdr *)((unsigned char *)ipv4_hdr +\n\t\t\t\t\tsizeof(struct ipv4_hdr));\n\t\tkey.port_dst = rte_be_to_cpu_16(tcp->dst_port);\n\t\tkey.port_src = rte_be_to_cpu_16(tcp->src_port);\n\t\tbreak;\n\n\tcase IPPROTO_UDP:\n\t\tudp = (struct udp_hdr *)((unsigned char *)ipv4_hdr +\n\t\t\t\t\tsizeof(struct ipv4_hdr));\n\t\tkey.port_dst = rte_be_to_cpu_16(udp->dst_port);\n\t\tkey.port_src = rte_be_to_cpu_16(udp->src_port);\n\t\tbreak;\n\n\tdefault:\n\t\tkey.port_dst = 0;\n\t\tkey.port_src = 0;\n\t\tbreak;\n\t}\n\n\t/* Find destination port */\n\tret = rte_hash_lookup(ipv4_l3fwd_lookup_struct, (const void *)&key);\n\treturn (uint8_t)((ret < 0)? portid : ipv4_l3fwd_out_if[ret]);\n}\n\nstatic inline uint8_t\nget_ipv6_dst_port(struct ipv6_hdr *ipv6_hdr, uint8_t portid,\n\t\t\tlookup_struct_t *ipv6_l3fwd_lookup_struct)\n{\n\tstruct ipv6_5tuple key;\n\tstruct tcp_hdr *tcp;\n\tstruct udp_hdr *udp;\n\tint ret = 0;\n\n\tmemcpy(key.ip_dst, ipv6_hdr->dst_addr, IPV6_ADDR_LEN);\n\tmemcpy(key.ip_src, ipv6_hdr->src_addr, IPV6_ADDR_LEN);\n\n\tkey.proto = ipv6_hdr->proto;\n\n\tswitch (ipv6_hdr->proto) {\n\tcase IPPROTO_TCP:\n\t\ttcp = (struct tcp_hdr *)((unsigned char *) ipv6_hdr +\n\t\t\t\t\tsizeof(struct ipv6_hdr));\n\t\tkey.port_dst = rte_be_to_cpu_16(tcp->dst_port);\n\t\tkey.port_src = rte_be_to_cpu_16(tcp->src_port);\n\t\tbreak;\n\n\tcase IPPROTO_UDP:\n\t\tudp = (struct udp_hdr *)((unsigned char *) ipv6_hdr +\n\t\t\t\t\tsizeof(struct ipv6_hdr));\n\t\tkey.port_dst = rte_be_to_cpu_16(udp->dst_port);\n\t\tkey.port_src = rte_be_to_cpu_16(udp->src_port);\n\t\tbreak;\n\n\tdefault:\n\t\tkey.port_dst = 0;\n\t\tkey.port_src = 0;\n\t\tbreak;\n\t}\n\n\t/* Find destination port */\n\tret = rte_hash_lookup(ipv6_l3fwd_lookup_struct, (const void *)&key);\n\treturn (uint8_t)((ret < 0)? portid : ipv6_l3fwd_out_if[ret]);\n}\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\nstatic inline uint8_t\nget_ipv4_dst_port(struct ipv4_hdr *ipv4_hdr, uint8_t portid,\n\t\tlookup_struct_t *ipv4_l3fwd_lookup_struct)\n{\n\tuint8_t next_hop;\n\n\treturn (uint8_t) ((rte_lpm_lookup(ipv4_l3fwd_lookup_struct,\n\t\t\trte_be_to_cpu_32(ipv4_hdr->dst_addr), &next_hop) == 0)?\n\t\t\tnext_hop : portid);\n}\n#endif\n\nstatic inline void\nl3fwd_simple_forward(struct rte_mbuf *m, uint8_t portid,\n\t\t\t\tstruct lcore_conf *qconf)\n{\n\tstruct ether_hdr *eth_hdr;\n\tstruct ipv4_hdr *ipv4_hdr;\n\tvoid *d_addr_bytes;\n\tuint8_t dst_port;\n\n\teth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n#ifdef RTE_NEXT_ABI\n\tif (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {\n#else\n\tif (m->ol_flags & PKT_RX_IPV4_HDR) {\n#endif\n\t\t/* Handle IPv4 headers.*/\n\t\tipv4_hdr =\n\t\t\trte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,\n\t\t\t\t\t\tsizeof(struct ether_hdr));\n\n#ifdef DO_RFC_1812_CHECKS\n\t\t/* Check to make sure the packet is valid (RFC1812) */\n\t\tif (is_valid_ipv4_pkt(ipv4_hdr, m->pkt_len) < 0) {\n\t\t\trte_pktmbuf_free(m);\n\t\t\treturn;\n\t\t}\n#endif\n\n\t\tdst_port = get_ipv4_dst_port(ipv4_hdr, portid,\n\t\t\t\t\tqconf->ipv4_lookup_struct);\n\t\tif (dst_port >= RTE_MAX_ETHPORTS ||\n\t\t\t\t(enabled_port_mask & 1 << dst_port) == 0)\n\t\t\tdst_port = portid;\n\n\t\t/* 02:00:00:00:00:xx */\n\t\td_addr_bytes = ð_hdr->d_addr.addr_bytes[0];\n\t\t*((uint64_t *)d_addr_bytes) =\n\t\t\t0x000000000002 + ((uint64_t)dst_port << 40);\n\n#ifdef DO_RFC_1812_CHECKS\n\t\t/* Update time to live and header checksum */\n\t\t--(ipv4_hdr->time_to_live);\n\t\t++(ipv4_hdr->hdr_checksum);\n#endif\n\n\t\t/* src addr */\n\t\tether_addr_copy(&ports_eth_addr[dst_port], ð_hdr->s_addr);\n\n\t\tsend_single_packet(m, dst_port);\n#ifdef RTE_NEXT_ABI\n\t} else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {\n#else\n\t}\n\telse {\n#endif\n\t\t/* Handle IPv6 headers.*/\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n\t\tstruct ipv6_hdr *ipv6_hdr;\n\n\t\tipv6_hdr =\n\t\t\trte_pktmbuf_mtod_offset(m, struct ipv6_hdr *,\n\t\t\t\t\t\tsizeof(struct ether_hdr));\n\n\t\tdst_port = get_ipv6_dst_port(ipv6_hdr, portid,\n\t\t\t\t\tqconf->ipv6_lookup_struct);\n\n\t\tif (dst_port >= RTE_MAX_ETHPORTS ||\n\t\t\t\t(enabled_port_mask & 1 << dst_port) == 0)\n\t\t\tdst_port = portid;\n\n\t\t/* 02:00:00:00:00:xx */\n\t\td_addr_bytes = ð_hdr->d_addr.addr_bytes[0];\n\t\t*((uint64_t *)d_addr_bytes) =\n\t\t\t0x000000000002 + ((uint64_t)dst_port << 40);\n\n\t\t/* src addr */\n\t\tether_addr_copy(&ports_eth_addr[dst_port], ð_hdr->s_addr);\n\n\t\tsend_single_packet(m, dst_port);\n#else\n\t\t/* We don't currently handle IPv6 packets in LPM mode. */\n\t\trte_pktmbuf_free(m);\n#endif\n\t}\n\n}\n\n#define MINIMUM_SLEEP_TIME 1\n#define SUSPEND_THRESHOLD 300\n\nstatic inline uint32_t\npower_idle_heuristic(uint32_t zero_rx_packet_count)\n{\n\t/* If zero count is less than 100, sleep 1us */\n\tif (zero_rx_packet_count < SUSPEND_THRESHOLD)\n\t\treturn MINIMUM_SLEEP_TIME;\n\t/* If zero count is less than 1000, sleep 100 us which is the\n\t\tminimum latency switching from C3/C6 to C0\n\t*/\n\telse\n\t\treturn SUSPEND_THRESHOLD;\n\n\treturn 0;\n}\n\nstatic inline enum freq_scale_hint_t\npower_freq_scaleup_heuristic(unsigned lcore_id,\n\t\t\t uint8_t port_id,\n\t\t\t uint16_t queue_id)\n{\n/**\n * HW Rx queue size is 128 by default, Rx burst read at maximum 32 entries\n * per iteration\n */\n#define FREQ_GEAR1_RX_PACKET_THRESHOLD MAX_PKT_BURST\n#define FREQ_GEAR2_RX_PACKET_THRESHOLD (MAX_PKT_BURST*2)\n#define FREQ_GEAR3_RX_PACKET_THRESHOLD (MAX_PKT_BURST*3)\n#define FREQ_UP_TREND1_ACC 1\n#define FREQ_UP_TREND2_ACC 100\n#define FREQ_UP_THRESHOLD 10000\n\n\tif (likely(rte_eth_rx_descriptor_done(port_id, queue_id,\n\t\t\tFREQ_GEAR3_RX_PACKET_THRESHOLD) > 0)) {\n\t\tstats[lcore_id].trend = 0;\n\t\treturn FREQ_HIGHEST;\n\t} else if (likely(rte_eth_rx_descriptor_done(port_id, queue_id,\n\t\t\tFREQ_GEAR2_RX_PACKET_THRESHOLD) > 0))\n\t\tstats[lcore_id].trend += FREQ_UP_TREND2_ACC;\n\telse if (likely(rte_eth_rx_descriptor_done(port_id, queue_id,\n\t\t\tFREQ_GEAR1_RX_PACKET_THRESHOLD) > 0))\n\t\tstats[lcore_id].trend += FREQ_UP_TREND1_ACC;\n\n\tif (likely(stats[lcore_id].trend > FREQ_UP_THRESHOLD)) {\n\t\tstats[lcore_id].trend = 0;\n\t\treturn FREQ_HIGHER;\n\t}\n\n\treturn FREQ_CURRENT;\n}\n\n/**\n * force polling thread sleep until one-shot rx interrupt triggers\n * @param port_id\n * Port id.\n * @param queue_id\n * Rx queue id.\n * @return\n * 0 on success\n */\nstatic int\nsleep_until_rx_interrupt(int num)\n{\n\tstruct rte_epoll_event event[num];\n\tint n, i;\n\tuint8_t port_id, queue_id;\n\tvoid *data;\n\n\tRTE_LOG(INFO, L3FWD_POWER,\n\t\t\"lcore %u sleeps until interrupt triggers\\n\",\n\t\trte_lcore_id());\n\n\tn = rte_epoll_wait(RTE_EPOLL_PER_THREAD, event, num, -1);\n\tfor (i = 0; i < n; i++) {\n\t\tdata = event[i].epdata.data;\n\t\tport_id = ((uintptr_t)data) >> CHAR_BIT;\n\t\tqueue_id = ((uintptr_t)data) &\n\t\t\tRTE_LEN2MASK(CHAR_BIT, uint8_t);\n\t\tRTE_LOG(INFO, L3FWD_POWER,\n\t\t\t\"lcore %u is waked up from rx interrupt on\"\n\t\t\t\" port %d queue %d\\n\",\n\t\t\trte_lcore_id(), port_id, queue_id);\n\t}\n\n\treturn 0;\n}\n\nstatic void turn_on_intr(struct lcore_conf *qconf)\n{\n\tint i;\n\tstruct lcore_rx_queue *rx_queue;\n\tuint8_t port_id, queue_id;\n\n\tfor (i = 0; i < qconf->n_rx_queue; ++i) {\n\t\trx_queue = &(qconf->rx_queue_list[i]);\n\t\tport_id = rx_queue->port_id;\n\t\tqueue_id = rx_queue->queue_id;\n\n\t\trte_spinlock_lock(&(locks[port_id]));\n\t\trte_eth_dev_rx_intr_enable(port_id, queue_id);\n\t\trte_spinlock_unlock(&(locks[port_id]));\n\t}\n}\n\nstatic int event_register(struct lcore_conf *qconf)\n{\n\tstruct lcore_rx_queue *rx_queue;\n\tuint8_t portid, queueid;\n\tuint32_t data;\n\tint ret;\n\tint i;\n\n\tfor (i = 0; i < qconf->n_rx_queue; ++i) {\n\t\trx_queue = &(qconf->rx_queue_list[i]);\n\t\tportid = rx_queue->port_id;\n\t\tqueueid = rx_queue->queue_id;\n\t\tdata = portid << CHAR_BIT | queueid;\n\n\t\tret = rte_eth_dev_rx_intr_ctl_q(portid, queueid,\n\t\t\t\t\t\tRTE_EPOLL_PER_THREAD,\n\t\t\t\t\t\tRTE_INTR_EVENT_ADD,\n\t\t\t\t\t\t(void *)((uintptr_t)data));\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\treturn 0;\n}\n\n/* main processing loop */\nstatic int\nmain_loop(__attribute__((unused)) void *dummy)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tunsigned lcore_id;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc;\n\tuint64_t prev_tsc_power = 0, cur_tsc_power, diff_tsc_power;\n\tint i, j, nb_rx;\n\tuint8_t portid, queueid;\n\tstruct lcore_conf *qconf;\n\tstruct lcore_rx_queue *rx_queue;\n\tenum freq_scale_hint_t lcore_scaleup_hint;\n\tuint32_t lcore_rx_idle_count = 0;\n\tuint32_t lcore_idle_hint = 0;\n\tint intr_en = 0;\n\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\tprev_tsc = 0;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_conf[lcore_id];\n\n\tif (qconf->n_rx_queue == 0) {\n\t\tRTE_LOG(INFO, L3FWD_POWER, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn 0;\n\t}\n\n\tRTE_LOG(INFO, L3FWD_POWER, \"entering main loop on lcore %u\\n\", lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_queue; i++) {\n\t\tportid = qconf->rx_queue_list[i].port_id;\n\t\tqueueid = qconf->rx_queue_list[i].queue_id;\n\t\tRTE_LOG(INFO, L3FWD_POWER, \" -- lcoreid=%u portid=%hhu \"\n\t\t\t\"rxqueueid=%hhu\\n\", lcore_id, portid, queueid);\n\t}\n\n\t/* add into event wait list */\n\tif (event_register(qconf) == 0)\n\t\tintr_en = 1;\n\telse\n\t\tRTE_LOG(INFO, L3FWD_POWER, \"RX interrupt won't enable.\\n\");\n\n\twhile (1) {\n\t\tstats[lcore_id].nb_iteration_looped++;\n\n\t\tcur_tsc = rte_rdtsc();\n\t\tcur_tsc_power = cur_tsc;\n\n\t\t/*\n\t\t * TX burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\t/*\n\t\t\t * This could be optimized (use queueid instead of\n\t\t\t * portid), but it is not called so often\n\t\t\t */\n\t\t\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t\t\tif (qconf->tx_mbufs[portid].len == 0)\n\t\t\t\t\tcontinue;\n\t\t\t\tsend_burst(&lcore_conf[lcore_id],\n\t\t\t\t\tqconf->tx_mbufs[portid].len,\n\t\t\t\t\tportid);\n\t\t\t\tqconf->tx_mbufs[portid].len = 0;\n\t\t\t}\n\n\t\t\tprev_tsc = cur_tsc;\n\t\t}\n\n\t\tdiff_tsc_power = cur_tsc_power - prev_tsc_power;\n\t\tif (diff_tsc_power > TIMER_RESOLUTION_CYCLES) {\n\t\t\trte_timer_manage();\n\t\t\tprev_tsc_power = cur_tsc_power;\n\t\t}\n\nstart_rx:\n\t\t/*\n\t\t * Read packet from RX queues\n\t\t */\n\t\tlcore_scaleup_hint = FREQ_CURRENT;\n\t\tlcore_rx_idle_count = 0;\n\t\tfor (i = 0; i < qconf->n_rx_queue; ++i) {\n\t\t\trx_queue = &(qconf->rx_queue_list[i]);\n\t\t\trx_queue->idle_hint = 0;\n\t\t\tportid = rx_queue->port_id;\n\t\t\tqueueid = rx_queue->queue_id;\n\n\t\t\tnb_rx = rte_eth_rx_burst(portid, queueid, pkts_burst,\n\t\t\t\t\t\t\t\tMAX_PKT_BURST);\n\n\t\t\tstats[lcore_id].nb_rx_processed += nb_rx;\n\t\t\tif (unlikely(nb_rx == 0)) {\n\t\t\t\t/**\n\t\t\t\t * no packet received from rx queue, try to\n\t\t\t\t * sleep for a while forcing CPU enter deeper\n\t\t\t\t * C states.\n\t\t\t\t */\n\t\t\t\trx_queue->zero_rx_packet_count++;\n\n\t\t\t\tif (rx_queue->zero_rx_packet_count <=\n\t\t\t\t\t\t\tMIN_ZERO_POLL_COUNT)\n\t\t\t\t\tcontinue;\n\n\t\t\t\trx_queue->idle_hint = power_idle_heuristic(\\\n\t\t\t\t\trx_queue->zero_rx_packet_count);\n\t\t\t\tlcore_rx_idle_count++;\n\t\t\t} else {\n\t\t\t\trx_queue->zero_rx_packet_count = 0;\n\n\t\t\t\t/**\n\t\t\t\t * do not scale up frequency immediately as\n\t\t\t\t * user to kernel space communication is costly\n\t\t\t\t * which might impact packet I/O for received\n\t\t\t\t * packets.\n\t\t\t\t */\n\t\t\t\trx_queue->freq_up_hint =\n\t\t\t\t\tpower_freq_scaleup_heuristic(lcore_id,\n\t\t\t\t\t\t\tportid, queueid);\n\t\t\t}\n\n\t\t\t/* Prefetch first packets */\n\t\t\tfor (j = 0; j < PREFETCH_OFFSET && j < nb_rx; j++) {\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(\n\t\t\t\t\t\tpkts_burst[j], void *));\n\t\t\t}\n\n\t\t\t/* Prefetch and forward already prefetched packets */\n\t\t\tfor (j = 0; j < (nb_rx - PREFETCH_OFFSET); j++) {\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(pkts_burst[\n\t\t\t\t\t\tj + PREFETCH_OFFSET], void *));\n\t\t\t\tl3fwd_simple_forward(pkts_burst[j], portid,\n\t\t\t\t\t\t\t\tqconf);\n\t\t\t}\n\n\t\t\t/* Forward remaining prefetched packets */\n\t\t\tfor (; j < nb_rx; j++) {\n\t\t\t\tl3fwd_simple_forward(pkts_burst[j], portid,\n\t\t\t\t\t\t\t\tqconf);\n\t\t\t}\n\t\t}\n\n\t\tif (likely(lcore_rx_idle_count != qconf->n_rx_queue)) {\n\t\t\tfor (i = 1, lcore_scaleup_hint =\n\t\t\t\tqconf->rx_queue_list[0].freq_up_hint;\n\t\t\t\t\ti < qconf->n_rx_queue; ++i) {\n\t\t\t\trx_queue = &(qconf->rx_queue_list[i]);\n\t\t\t\tif (rx_queue->freq_up_hint >\n\t\t\t\t\t\tlcore_scaleup_hint)\n\t\t\t\t\tlcore_scaleup_hint =\n\t\t\t\t\t\trx_queue->freq_up_hint;\n\t\t\t}\n\n\t\t\tif (lcore_scaleup_hint == FREQ_HIGHEST) {\n\t\t\t\tif (rte_power_freq_max)\n\t\t\t\t\trte_power_freq_max(lcore_id);\n\t\t\t} else if (lcore_scaleup_hint == FREQ_HIGHER) {\n\t\t\t\tif (rte_power_freq_up)\n\t\t\t\t\trte_power_freq_up(lcore_id);\n\t\t\t}\n\t\t} else {\n\t\t\t/**\n\t\t\t * All Rx queues empty in recent consecutive polls,\n\t\t\t * sleep in a conservative manner, meaning sleep as\n\t\t\t * less as possible.\n\t\t\t */\n\t\t\tfor (i = 1, lcore_idle_hint =\n\t\t\t\tqconf->rx_queue_list[0].idle_hint;\n\t\t\t\t\ti < qconf->n_rx_queue; ++i) {\n\t\t\t\trx_queue = &(qconf->rx_queue_list[i]);\n\t\t\t\tif (rx_queue->idle_hint < lcore_idle_hint)\n\t\t\t\t\tlcore_idle_hint = rx_queue->idle_hint;\n\t\t\t}\n\n\t\t\tif (lcore_idle_hint < SUSPEND_THRESHOLD)\n\t\t\t\t/**\n\t\t\t\t * execute \"pause\" instruction to avoid context\n\t\t\t\t * switch which generally take hundred of\n\t\t\t\t * microseconds for short sleep.\n\t\t\t\t */\n\t\t\t\trte_delay_us(lcore_idle_hint);\n\t\t\telse {\n\t\t\t\t/* suspend until rx interrupt trigges */\n\t\t\t\tif (intr_en) {\n\t\t\t\t\tturn_on_intr(qconf);\n\t\t\t\t\tsleep_until_rx_interrupt(\n\t\t\t\t\t\tqconf->n_rx_queue);\n\t\t\t\t}\n\t\t\t\t/* start receiving packets immediately */\n\t\t\t\tgoto start_rx;\n\t\t\t}\n\t\t\tstats[lcore_id].sleep_time += lcore_idle_hint;\n\t\t}\n\t}\n}\n\nstatic int\ncheck_lcore_params(void)\n{\n\tuint8_t queue, lcore;\n\tuint16_t i;\n\tint socketid;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tqueue = lcore_params[i].queue_id;\n\t\tif (queue >= MAX_RX_QUEUE_PER_PORT) {\n\t\t\tprintf(\"invalid queue number: %hhu\\n\", queue);\n\t\t\treturn -1;\n\t\t}\n\t\tlcore = lcore_params[i].lcore_id;\n\t\tif (!rte_lcore_is_enabled(lcore)) {\n\t\t\tprintf(\"error: lcore %hhu is not enabled in lcore \"\n\t\t\t\t\t\t\t\"mask\\n\", lcore);\n\t\t\treturn -1;\n\t\t}\n\t\tif ((socketid = rte_lcore_to_socket_id(lcore) != 0) &&\n\t\t\t\t\t\t\t(numa_on == 0)) {\n\t\t\tprintf(\"warning: lcore %hhu is on socket %d with numa \"\n\t\t\t\t\t\t\"off\\n\", lcore, socketid);\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\ncheck_port_config(const unsigned nb_ports)\n{\n\tunsigned portid;\n\tuint16_t i;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tportid = lcore_params[i].port_id;\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"port %u is not enabled in port mask\\n\",\n\t\t\t\t\t\t\t\tportid);\n\t\t\treturn -1;\n\t\t}\n\t\tif (portid >= nb_ports) {\n\t\t\tprintf(\"port %u is not present on the board\\n\",\n\t\t\t\t\t\t\t\tportid);\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic uint8_t\nget_port_n_rx_queues(const uint8_t port)\n{\n\tint queue = -1;\n\tuint16_t i;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tif (lcore_params[i].port_id == port &&\n\t\t\t\tlcore_params[i].queue_id > queue)\n\t\t\tqueue = lcore_params[i].queue_id;\n\t}\n\treturn (uint8_t)(++queue);\n}\n\nstatic int\ninit_lcore_rx_queues(void)\n{\n\tuint16_t i, nb_rx_queue;\n\tuint8_t lcore;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tlcore = lcore_params[i].lcore_id;\n\t\tnb_rx_queue = lcore_conf[lcore].n_rx_queue;\n\t\tif (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) {\n\t\t\tprintf(\"error: too many queues (%u) for lcore: %u\\n\",\n\t\t\t\t(unsigned)nb_rx_queue + 1, (unsigned)lcore);\n\t\t\treturn -1;\n\t\t} else {\n\t\t\tlcore_conf[lcore].rx_queue_list[nb_rx_queue].port_id =\n\t\t\t\tlcore_params[i].port_id;\n\t\t\tlcore_conf[lcore].rx_queue_list[nb_rx_queue].queue_id =\n\t\t\t\tlcore_params[i].queue_id;\n\t\t\tlcore_conf[lcore].n_rx_queue++;\n\t\t}\n\t}\n\treturn 0;\n}\n\n/* display usage */\nstatic void\nprint_usage(const char *prgname)\n{\n\tprintf (\"%s [EAL options] -- -p PORTMASK -P\"\n\t\t\" [--config (port,queue,lcore)[,(port,queue,lcore]]\"\n\t\t\" [--enable-jumbo [--max-pkt-len PKTLEN]]\\n\"\n\t\t\" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t\t\" -P : enable promiscuous mode\\n\"\n\t\t\" --config (port,queue,lcore): rx queues configuration\\n\"\n\t\t\" --no-numa: optional, disable numa awareness\\n\"\n\t\t\" --enable-jumbo: enable jumbo frame\"\n\t\t\" which max packet len is PKTLEN in decimal (64-9600)\\n\",\n\t\tprgname);\n}\n\nstatic int parse_max_pkt_len(const char *pktlen)\n{\n\tchar *end = NULL;\n\tunsigned long len;\n\n\t/* parse decimal string */\n\tlen = strtoul(pktlen, &end, 10);\n\tif ((pktlen[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (len == 0)\n\t\treturn -1;\n\n\treturn len;\n}\n\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\nstatic int\nparse_config(const char *q_arg)\n{\n\tchar s[256];\n\tconst char *p, *p0 = q_arg;\n\tchar *end;\n\tenum fieldnames {\n\t\tFLD_PORT = 0,\n\t\tFLD_QUEUE,\n\t\tFLD_LCORE,\n\t\t_NUM_FLD\n\t};\n\tunsigned long int_fld[_NUM_FLD];\n\tchar *str_fld[_NUM_FLD];\n\tint i;\n\tunsigned size;\n\n\tnb_lcore_params = 0;\n\n\twhile ((p = strchr(p0,'(')) != NULL) {\n\t\t++p;\n\t\tif((p0 = strchr(p,')')) == NULL)\n\t\t\treturn -1;\n\n\t\tsize = p0 - p;\n\t\tif(size >= sizeof(s))\n\t\t\treturn -1;\n\n\t\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\t\tif (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') !=\n\t\t\t\t\t\t\t\t_NUM_FLD)\n\t\t\treturn -1;\n\t\tfor (i = 0; i < _NUM_FLD; i++){\n\t\t\terrno = 0;\n\t\t\tint_fld[i] = strtoul(str_fld[i], &end, 0);\n\t\t\tif (errno != 0 || end == str_fld[i] || int_fld[i] >\n\t\t\t\t\t\t\t\t\t255)\n\t\t\t\treturn -1;\n\t\t}\n\t\tif (nb_lcore_params >= MAX_LCORE_PARAMS) {\n\t\t\tprintf(\"exceeded max number of lcore params: %hu\\n\",\n\t\t\t\tnb_lcore_params);\n\t\t\treturn -1;\n\t\t}\n\t\tlcore_params_array[nb_lcore_params].port_id =\n\t\t\t\t(uint8_t)int_fld[FLD_PORT];\n\t\tlcore_params_array[nb_lcore_params].queue_id =\n\t\t\t\t(uint8_t)int_fld[FLD_QUEUE];\n\t\tlcore_params_array[nb_lcore_params].lcore_id =\n\t\t\t\t(uint8_t)int_fld[FLD_LCORE];\n\t\t++nb_lcore_params;\n\t}\n\tlcore_params = lcore_params_array;\n\n\treturn 0;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{\"config\", 1, 0, 0},\n\t\t{\"no-numa\", 0, 0, 0},\n\t\t{\"enable-jumbo\", 0, 0, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:P\",\n\t\t\t\tlgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 'P':\n\t\t\tprintf(\"Promiscuous mode selected\\n\");\n\t\t\tpromiscuous_on = 1;\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tif (!strncmp(lgopts[option_index].name, \"config\", 6)) {\n\t\t\t\tret = parse_config(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"invalid config\\n\");\n\t\t\t\t\tprint_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (!strncmp(lgopts[option_index].name,\n\t\t\t\t\t\t\"no-numa\", 7)) {\n\t\t\t\tprintf(\"numa is disabled \\n\");\n\t\t\t\tnuma_on = 0;\n\t\t\t}\n\n\t\t\tif (!strncmp(lgopts[option_index].name,\n\t\t\t\t\t\"enable-jumbo\", 12)) {\n\t\t\t\tstruct option lenopts =\n\t\t\t\t\t{\"max-pkt-len\", required_argument, \\\n\t\t\t\t\t\t\t\t\t0, 0};\n\n\t\t\t\tprintf(\"jumbo frame is enabled \\n\");\n\t\t\t\tport_conf.rxmode.jumbo_frame = 1;\n\n\t\t\t\t/**\n\t\t\t\t * if no max-pkt-len set, use the default value\n\t\t\t\t * ETHER_MAX_LEN\n\t\t\t\t */\n\t\t\t\tif (0 == getopt_long(argc, argvopt, \"\",\n\t\t\t\t\t\t&lenopts, &option_index)) {\n\t\t\t\t\tret = parse_max_pkt_len(optarg);\n\t\t\t\t\tif ((ret < 64) ||\n\t\t\t\t\t\t(ret > MAX_JUMBO_PKT_LEN)){\n\t\t\t\t\t\tprintf(\"invalid packet \"\n\t\t\t\t\t\t\t\t\"length\\n\");\n\t\t\t\t\t\tprint_usage(prgname);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\tport_conf.rxmode.max_rx_pkt_len = ret;\n\t\t\t\t}\n\t\t\t\tprintf(\"set jumbo frame \"\n\t\t\t\t\t\"max packet length to %u\\n\",\n\t\t\t\t(unsigned int)port_conf.rxmode.max_rx_pkt_len);\n\t\t\t}\n\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\nstatic void\nprint_ethaddr(const char *name, const struct ether_addr *eth_addr)\n{\n\tchar buf[ETHER_ADDR_FMT_SIZE];\n\tether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);\n\tprintf(\"%s%s\", name, buf);\n}\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\nstatic void\nsetup_hash(int socketid)\n{\n\tstruct rte_hash_parameters ipv4_l3fwd_hash_params = {\n\t\t.name = NULL,\n\t\t.entries = L3FWD_HASH_ENTRIES,\n\t\t.key_len = sizeof(struct ipv4_5tuple),\n\t\t.hash_func = DEFAULT_HASH_FUNC,\n\t\t.hash_func_init_val = 0,\n\t};\n\n\tstruct rte_hash_parameters ipv6_l3fwd_hash_params = {\n\t\t.name = NULL,\n\t\t.entries = L3FWD_HASH_ENTRIES,\n\t\t.key_len = sizeof(struct ipv6_5tuple),\n\t\t.hash_func = DEFAULT_HASH_FUNC,\n\t\t.hash_func_init_val = 0,\n\t};\n\n\tunsigned i;\n\tint ret;\n\tchar s[64];\n\n\t/* create ipv4 hash */\n\trte_snprintf(s, sizeof(s), \"ipv4_l3fwd_hash_%d\", socketid);\n\tipv4_l3fwd_hash_params.name = s;\n\tipv4_l3fwd_hash_params.socket_id = socketid;\n\tipv4_l3fwd_lookup_struct[socketid] =\n\t\trte_hash_create(&ipv4_l3fwd_hash_params);\n\tif (ipv4_l3fwd_lookup_struct[socketid] == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Unable to create the l3fwd hash on \"\n\t\t\t\t\"socket %d\\n\", socketid);\n\n\t/* create ipv6 hash */\n\trte_snprintf(s, sizeof(s), \"ipv6_l3fwd_hash_%d\", socketid);\n\tipv6_l3fwd_hash_params.name = s;\n\tipv6_l3fwd_hash_params.socket_id = socketid;\n\tipv6_l3fwd_lookup_struct[socketid] =\n\t\trte_hash_create(&ipv6_l3fwd_hash_params);\n\tif (ipv6_l3fwd_lookup_struct[socketid] == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Unable to create the l3fwd hash on \"\n\t\t\t\t\"socket %d\\n\", socketid);\n\n\n\t/* populate the ipv4 hash */\n\tfor (i = 0; i < IPV4_L3FWD_NUM_ROUTES; i++) {\n\t\tret = rte_hash_add_key (ipv4_l3fwd_lookup_struct[socketid],\n\t\t\t\t(void *) &ipv4_l3fwd_route_array[i].key);\n\t\tif (ret < 0) {\n\t\t\trte_exit(EXIT_FAILURE, \"Unable to add entry %u to the\"\n\t\t\t\t\"l3fwd hash on socket %d\\n\", i, socketid);\n\t\t}\n\t\tipv4_l3fwd_out_if[ret] = ipv4_l3fwd_route_array[i].if_out;\n\t\tprintf(\"Hash: Adding key\\n\");\n\t\tprint_ipv4_key(ipv4_l3fwd_route_array[i].key);\n\t}\n\n\t/* populate the ipv6 hash */\n\tfor (i = 0; i < IPV6_L3FWD_NUM_ROUTES; i++) {\n\t\tret = rte_hash_add_key (ipv6_l3fwd_lookup_struct[socketid],\n\t\t\t\t(void *) &ipv6_l3fwd_route_array[i].key);\n\t\tif (ret < 0) {\n\t\t\trte_exit(EXIT_FAILURE, \"Unable to add entry %u to the\"\n\t\t\t\t\"l3fwd hash on socket %d\\n\", i, socketid);\n\t\t}\n\t\tipv6_l3fwd_out_if[ret] = ipv6_l3fwd_route_array[i].if_out;\n\t\tprintf(\"Hash: Adding key\\n\");\n\t\tprint_ipv6_key(ipv6_l3fwd_route_array[i].key);\n\t}\n}\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\nstatic void\nsetup_lpm(int socketid)\n{\n\tunsigned i;\n\tint ret;\n\tchar s[64];\n\n\t/* create the LPM table */\n\tsnprintf(s, sizeof(s), \"IPV4_L3FWD_LPM_%d\", socketid);\n\tipv4_l3fwd_lookup_struct[socketid] = rte_lpm_create(s, socketid,\n\t\t\t\tIPV4_L3FWD_LPM_MAX_RULES, 0);\n\tif (ipv4_l3fwd_lookup_struct[socketid] == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Unable to create the l3fwd LPM table\"\n\t\t\t\t\" on socket %d\\n\", socketid);\n\n\t/* populate the LPM table */\n\tfor (i = 0; i < IPV4_L3FWD_NUM_ROUTES; i++) {\n\t\tret = rte_lpm_add(ipv4_l3fwd_lookup_struct[socketid],\n\t\t\tipv4_l3fwd_route_array[i].ip,\n\t\t\tipv4_l3fwd_route_array[i].depth,\n\t\t\tipv4_l3fwd_route_array[i].if_out);\n\n\t\tif (ret < 0) {\n\t\t\trte_exit(EXIT_FAILURE, \"Unable to add entry %u to the \"\n\t\t\t\t\"l3fwd LPM table on socket %d\\n\",\n\t\t\t\ti, socketid);\n\t\t}\n\n\t\tprintf(\"LPM: Adding route 0x%08x / %d (%d)\\n\",\n\t\t\t(unsigned)ipv4_l3fwd_route_array[i].ip,\n\t\t\tipv4_l3fwd_route_array[i].depth,\n\t\t\tipv4_l3fwd_route_array[i].if_out);\n\t}\n}\n#endif\n\nstatic int\ninit_mem(unsigned nb_mbuf)\n{\n\tstruct lcore_conf *qconf;\n\tint socketid;\n\tunsigned lcore_id;\n\tchar s[64];\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\tcontinue;\n\n\t\tif (numa_on)\n\t\t\tsocketid = rte_lcore_to_socket_id(lcore_id);\n\t\telse\n\t\t\tsocketid = 0;\n\n\t\tif (socketid >= NB_SOCKETS) {\n\t\t\trte_exit(EXIT_FAILURE, \"Socket %d of lcore %u is \"\n\t\t\t\t\t\"out of range %d\\n\", socketid,\n\t\t\t\t\t\tlcore_id, NB_SOCKETS);\n\t\t}\n\t\tif (pktmbuf_pool[socketid] == NULL) {\n\t\t\tsnprintf(s, sizeof(s), \"mbuf_pool_%d\", socketid);\n\t\t\tpktmbuf_pool[socketid] =\n\t\t\t\trte_pktmbuf_pool_create(s, nb_mbuf,\n\t\t\t\t\tMEMPOOL_CACHE_SIZE, 0,\n\t\t\t\t\tRTE_MBUF_DEFAULT_BUF_SIZE,\n\t\t\t\t\tsocketid);\n\t\t\tif (pktmbuf_pool[socketid] == NULL)\n\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\"Cannot init mbuf pool on socket %d\\n\",\n\t\t\t\t\t\t\t\tsocketid);\n\t\t\telse\n\t\t\t\tprintf(\"Allocated mbuf pool on socket %d\\n\",\n\t\t\t\t\t\t\t\tsocketid);\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\n\t\t\tsetup_lpm(socketid);\n#else\n\t\t\tsetup_hash(socketid);\n#endif\n\t\t}\n\t\tqconf = &lcore_conf[lcore_id];\n\t\tqconf->ipv4_lookup_struct = ipv4_l3fwd_lookup_struct[socketid];\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n\t\tqconf->ipv6_lookup_struct = ipv6_l3fwd_lookup_struct[socketid];\n#endif\n\t}\n\treturn 0;\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_conf *qconf;\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_txconf *txconf;\n\tint ret;\n\tunsigned nb_ports;\n\tuint16_t queueid;\n\tunsigned lcore_id;\n\tuint64_t hz;\n\tuint32_t n_tx_queue, nb_lcores;\n\tuint32_t dev_rxq_num, dev_txq_num;\n\tuint8_t portid, nb_rx_queue, queue, socketid;\n\n\t/* catch SIGINT and restore cpufreq governor to ondemand */\n\tsignal(SIGINT, signal_exit_now);\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid EAL parameters\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* init RTE timer library to be used late */\n\trte_timer_subsystem_init();\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid L3FWD parameters\\n\");\n\n\tif (check_lcore_params() < 0)\n\t\trte_exit(EXIT_FAILURE, \"check_lcore_params failed\\n\");\n\n\tret = init_lcore_rx_queues();\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"init_lcore_rx_queues failed\\n\");\n\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\tif (check_port_config(nb_ports) < 0)\n\t\trte_exit(EXIT_FAILURE, \"check_port_config failed\\n\");\n\n\tnb_lcores = rte_lcore_count();\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"\\nSkipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* init port */\n\t\tprintf(\"Initializing port %d ... \", portid );\n\t\tfflush(stdout);\n\n\t\trte_eth_dev_info_get(portid, &dev_info);\n\t\tdev_rxq_num = dev_info.max_rx_queues;\n\t\tdev_txq_num = dev_info.max_tx_queues;\n\n\t\tnb_rx_queue = get_port_n_rx_queues(portid);\n\t\tif (nb_rx_queue > dev_rxq_num)\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"Cannot configure not existed rxq: \"\n\t\t\t\t\"port=%d\\n\", portid);\n\n\t\tn_tx_queue = nb_lcores;\n\t\tif (n_tx_queue > dev_txq_num)\n\t\t\tn_tx_queue = dev_txq_num;\n\t\tprintf(\"Creating queues: nb_rxq=%d nb_txq=%u... \",\n\t\t\tnb_rx_queue, (unsigned)n_tx_queue );\n\t\tret = rte_eth_dev_configure(portid, nb_rx_queue,\n\t\t\t\t\t(uint16_t)n_tx_queue, &port_conf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot configure device: \"\n\t\t\t\t\t\"err=%d, port=%d\\n\", ret, portid);\n\n\t\trte_eth_macaddr_get(portid, &ports_eth_addr[portid]);\n\t\tprint_ethaddr(\" Address:\", &ports_eth_addr[portid]);\n\t\tprintf(\", \");\n\n\t\t/* init memory */\n\t\tret = init_mem(NB_MBUF);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"init_mem failed\\n\");\n\n\t\t/* init one TX queue per couple (lcore,port) */\n\t\tqueueid = 0;\n\t\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (queueid >= dev_txq_num)\n\t\t\t\tcontinue;\n\n\t\t\tif (numa_on)\n\t\t\t\tsocketid = \\\n\t\t\t\t(uint8_t)rte_lcore_to_socket_id(lcore_id);\n\t\t\telse\n\t\t\t\tsocketid = 0;\n\n\t\t\tprintf(\"txq=%u,%d,%d \", lcore_id, queueid, socketid);\n\t\t\tfflush(stdout);\n\n\t\t\trte_eth_dev_info_get(portid, &dev_info);\n\t\t\ttxconf = &dev_info.default_txconf;\n\t\t\tif (port_conf.rxmode.jumbo_frame)\n\t\t\t\ttxconf->txq_flags = 0;\n\t\t\tret = rte_eth_tx_queue_setup(portid, queueid, nb_txd,\n\t\t\t\t\t\t socketid, txconf);\n\t\t\tif (ret < 0)\n\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\"rte_eth_tx_queue_setup: err=%d, \"\n\t\t\t\t\t\t\"port=%d\\n\", ret, portid);\n\n\t\t\tqconf = &lcore_conf[lcore_id];\n\t\t\tqconf->tx_queue_id[portid] = queueid;\n\t\t\tqueueid++;\n\t\t}\n\t\tprintf(\"\\n\");\n\t}\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\tcontinue;\n\n\t\t/* init power management library */\n\t\tret = rte_power_init(lcore_id);\n\t\tif (ret)\n\t\t\tRTE_LOG(ERR, POWER,\n\t\t\t\t\"Library initialization failed on core %u\\n\", lcore_id);\n\n\t\t/* init timer structures for each enabled lcore */\n\t\trte_timer_init(&power_timers[lcore_id]);\n\t\thz = rte_get_timer_hz();\n\t\trte_timer_reset(&power_timers[lcore_id],\n\t\t\thz/TIMER_NUMBER_PER_SECOND, SINGLE, lcore_id,\n\t\t\t\t\t\tpower_timer_cb, NULL);\n\n\t\tqconf = &lcore_conf[lcore_id];\n\t\tprintf(\"\\nInitializing rx queues on lcore %u ... \", lcore_id );\n\t\tfflush(stdout);\n\t\t/* init RX queues */\n\t\tfor(queue = 0; queue < qconf->n_rx_queue; ++queue) {\n\t\t\tportid = qconf->rx_queue_list[queue].port_id;\n\t\t\tqueueid = qconf->rx_queue_list[queue].queue_id;\n\n\t\t\tif (numa_on)\n\t\t\t\tsocketid = \\\n\t\t\t\t(uint8_t)rte_lcore_to_socket_id(lcore_id);\n\t\t\telse\n\t\t\t\tsocketid = 0;\n\n\t\t\tprintf(\"rxq=%d,%d,%d \", portid, queueid, socketid);\n\t\t\tfflush(stdout);\n\n\t\t\tret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd,\n\t\t\t\tsocketid, NULL,\n\t\t\t\tpktmbuf_pool[socketid]);\n\t\t\tif (ret < 0)\n\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\"rte_eth_rx_queue_setup: err=%d, \"\n\t\t\t\t\t\t\"port=%d\\n\", ret, portid);\n\t\t}\n\t}\n\n\tprintf(\"\\n\");\n\n\t/* start ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tcontinue;\n\t\t}\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_dev_start: err=%d, \"\n\t\t\t\t\t\t\"port=%d\\n\", ret, portid);\n\t\t/*\n\t\t * If enabled, put device in promiscuous mode.\n\t\t * This allows IO forwarding mode to forward packets\n\t\t * to itself through 2 cross-connected ports of the\n\t\t * target machine.\n\t\t */\n\t\tif (promiscuous_on)\n\t\t\trte_eth_promiscuous_enable(portid);\n\t\t/* initialize spinlock for each port */\n\t\trte_spinlock_init(&(locks[portid]));\n\t}\n\n\tcheck_all_ports_link_status((uint8_t)nb_ports, enabled_port_mask);\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/l3fwd-vf/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = l3fwd-vf\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3 $(USER_FLAGS)\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/l3fwd-vf/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define APP_LOOKUP_EXACT_MATCH 0\n#define APP_LOOKUP_LPM 1\n#define DO_RFC_1812_CHECKS\n\n//#define APP_LOOKUP_METHOD APP_LOOKUP_EXACT_MATCH\n#ifndef APP_LOOKUP_METHOD\n#define APP_LOOKUP_METHOD APP_LOOKUP_LPM\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n#include \n#elif (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\n#include \n#else\n#error \"APP_LOOKUP_METHOD set to incorrect value\"\n#endif\n\n#define RTE_LOGTYPE_L3FWD RTE_LOGTYPE_USER1\n\n#define MEMPOOL_CACHE_SIZE 256\n\n/*\n * This expression is used to calculate the number of mbufs needed depending on user input, taking\n * into account memory for rx and tx hardware rings, cache per lcore and mtable per port per lcore.\n * RTE_MAX is used to ensure that NB_MBUF never goes below a minimum value of 8192\n */\n\n#define NB_MBUF RTE_MAX\t(\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t(nb_ports*nb_rx_queue*RTE_TEST_RX_DESC_DEFAULT +\t\t\t\t\t\t\t\\\n\t\t\t\tnb_ports*nb_lcores*MAX_PKT_BURST +\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\tnb_ports*n_tx_queue*RTE_TEST_TX_DESC_DEFAULT +\t\t\t\t\t\t\t\t\\\n\t\t\t\tnb_lcores*MEMPOOL_CACHE_SIZE),\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t(unsigned)8192)\n\n/*\n * RX and TX Prefetch, Host, and Write-back threshold values should be\n * carefully set for optimal performance. Consult the network\n * controller's datasheet and supporting DPDK documentation for guidance\n * on how these parameters should be set.\n */\n#define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */\n#define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */\n#define RX_WTHRESH 4 /**< Default values of RX write-back threshold reg. */\n\n/*\n * These default values are optimized for use with the Intel(R) 82599 10 GbE\n * Controller and the DPDK ixgbe PMD. Consider using other values for other\n * network controllers and/or network drivers.\n */\n#define TX_PTHRESH 36 /**< Default values of TX prefetch threshold reg. */\n#define TX_HTHRESH 0 /**< Default values of TX host threshold reg. */\n#define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */\n\n#define MAX_PKT_BURST 32\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n#define NB_SOCKETS 8\n\n#define SOCKET0 0\n\n/* Configure how many packets ahead to prefetch, when reading packets */\n#define PREFETCH_OFFSET\t3\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n/* ethernet addresses of ports */\nstatic struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];\n\n/* mask of enabled ports */\nstatic uint32_t enabled_port_mask = 0;\nstatic int numa_on = 1; /**< NUMA is enabled by default. */\n\nstruct mbuf_table {\n\tuint16_t len;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST];\n};\n\nstruct lcore_rx_queue {\n\tuint8_t port_id;\n\tuint8_t queue_id;\n} __rte_cache_aligned;\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT 1\n#define MAX_RX_QUEUE_PER_PORT 1\n\n#define MAX_LCORE_PARAMS 1024\nstruct lcore_params {\n\tuint8_t port_id;\n\tuint8_t queue_id;\n\tuint8_t lcore_id;\n} __rte_cache_aligned;\n\nstatic struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];\nstatic struct lcore_params lcore_params_array_default[] = {\n\t{0, 0, 2},\n\t{0, 1, 2},\n\t{0, 2, 2},\n\t{1, 0, 2},\n\t{1, 1, 2},\n\t{1, 2, 2},\n\t{2, 0, 2},\n\t{3, 0, 3},\n\t{3, 1, 3},\n};\n\nstatic struct lcore_params * lcore_params = lcore_params_array_default;\nstatic uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /\n\t\t\t\tsizeof(lcore_params_array_default[0]);\n\nstatic struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.mq_mode\t= ETH_MQ_RX_RSS,\n\t\t.max_rx_pkt_len = ETHER_MAX_LEN,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 1, /**< IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.rx_adv_conf = {\n\t\t.rss_conf = {\n\t\t\t.rss_key = NULL,\n\t\t\t.rss_hf = ETH_RSS_IP,\n\t\t},\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\nstatic struct rte_mempool * pktmbuf_pool[NB_SOCKETS];\n\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\n\n#ifdef RTE_MACHINE_CPUFLAG_SSE4_2\n#include \n#define DEFAULT_HASH_FUNC rte_hash_crc\n#else\n#include \n#define DEFAULT_HASH_FUNC rte_jhash\n#endif\n\nstruct ipv4_5tuple {\n\tuint32_t ip_dst;\n\tuint32_t ip_src;\n\tuint16_t port_dst;\n\tuint16_t port_src;\n\tuint8_t proto;\n} __attribute__((__packed__));\n\nstruct l3fwd_route {\n\tstruct ipv4_5tuple key;\n\tuint8_t if_out;\n};\n\nstatic struct l3fwd_route l3fwd_route_array[] = {\n\t{{IPv4(100,10,0,1), IPv4(200,10,0,1), 101, 11, IPPROTO_TCP}, 0},\n\t{{IPv4(100,20,0,2), IPv4(200,20,0,2), 102, 12, IPPROTO_TCP}, 1},\n\t{{IPv4(100,30,0,3), IPv4(200,30,0,3), 103, 13, IPPROTO_TCP}, 2},\n\t{{IPv4(100,40,0,4), IPv4(200,40,0,4), 104, 14, IPPROTO_TCP}, 3},\n};\n\ntypedef struct rte_hash lookup_struct_t;\nstatic lookup_struct_t *l3fwd_lookup_struct[NB_SOCKETS];\n\n#define L3FWD_HASH_ENTRIES\t1024\nstruct rte_hash_parameters l3fwd_hash_params = {\n\t.name = \"l3fwd_hash_0\",\n\t.entries = L3FWD_HASH_ENTRIES,\n\t.key_len = sizeof(struct ipv4_5tuple),\n\t.hash_func = DEFAULT_HASH_FUNC,\n\t.hash_func_init_val = 0,\n\t.socket_id = SOCKET0,\n};\n\n#define L3FWD_NUM_ROUTES \\\n\t(sizeof(l3fwd_route_array) / sizeof(l3fwd_route_array[0]))\n\nstatic uint8_t l3fwd_out_if[L3FWD_HASH_ENTRIES] __rte_cache_aligned;\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\nstruct l3fwd_route {\n\tuint32_t ip;\n\tuint8_t depth;\n\tuint8_t if_out;\n};\n\nstatic struct l3fwd_route l3fwd_route_array[] = {\n\t{IPv4(1,1,1,0), 24, 0},\n\t{IPv4(2,1,1,0), 24, 1},\n\t{IPv4(3,1,1,0), 24, 2},\n\t{IPv4(4,1,1,0), 24, 3},\n\t{IPv4(5,1,1,0), 24, 4},\n\t{IPv4(6,1,1,0), 24, 5},\n\t{IPv4(7,1,1,0), 24, 6},\n\t{IPv4(8,1,1,0), 24, 7},\n};\n\n#define L3FWD_NUM_ROUTES \\\n\t(sizeof(l3fwd_route_array) / sizeof(l3fwd_route_array[0]))\n\n#define L3FWD_LPM_MAX_RULES 1024\n\ntypedef struct rte_lpm lookup_struct_t;\nstatic lookup_struct_t *l3fwd_lookup_struct[NB_SOCKETS];\n#endif\n\nstruct lcore_conf {\n\tuint16_t n_rx_queue;\n\tstruct lcore_rx_queue rx_queue_list[MAX_RX_QUEUE_PER_LCORE];\n\tuint16_t tx_queue_id;\n\tstruct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];\n\tlookup_struct_t * lookup_struct;\n} __rte_cache_aligned;\n\nstatic struct lcore_conf lcore_conf[RTE_MAX_LCORE];\nstatic rte_spinlock_t spinlock_conf[RTE_MAX_ETHPORTS] = {RTE_SPINLOCK_INITIALIZER};\n/* Send burst of packets on an output interface */\nstatic inline int\nsend_burst(struct lcore_conf *qconf, uint16_t n, uint8_t port)\n{\n\tstruct rte_mbuf **m_table;\n\tint ret;\n\tuint16_t queueid;\n\n\tqueueid = qconf->tx_queue_id;\n\tm_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;\n\n\trte_spinlock_lock(&spinlock_conf[port]);\n\tret = rte_eth_tx_burst(port, queueid, m_table, n);\n\trte_spinlock_unlock(&spinlock_conf[port]);\n\n\tif (unlikely(ret < n)) {\n\t\tdo {\n\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t} while (++ret < n);\n\t}\n\n\treturn 0;\n}\n\n/* Enqueue a single packet, and send burst if queue is filled */\nstatic inline int\nsend_single_packet(struct rte_mbuf *m, uint8_t port)\n{\n\tuint32_t lcore_id;\n\tuint16_t len;\n\tstruct lcore_conf *qconf;\n\n\tlcore_id = rte_lcore_id();\n\n\tqconf = &lcore_conf[lcore_id];\n\tlen = qconf->tx_mbufs[port].len;\n\tqconf->tx_mbufs[port].m_table[len] = m;\n\tlen++;\n\n\t/* enough pkts to be sent */\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tsend_burst(qconf, MAX_PKT_BURST, port);\n\t\tlen = 0;\n\t}\n\n\tqconf->tx_mbufs[port].len = len;\n\treturn 0;\n}\n\n#ifdef DO_RFC_1812_CHECKS\nstatic inline int\nis_valid_ipv4_pkt(struct ipv4_hdr *pkt, uint32_t link_len)\n{\n\t/* From http://www.rfc-editor.org/rfc/rfc1812.txt section 5.2.2 */\n\t/*\n\t * 1. The packet length reported by the Link Layer must be large\n\t * enough to hold the minimum length legal IP datagram (20 bytes).\n\t */\n\tif (link_len < sizeof(struct ipv4_hdr))\n\t\treturn -1;\n\n\t/* 2. The IP checksum must be correct. */\n\t/* this is checked in H/W */\n\n\t/*\n\t * 3. The IP version number must be 4. If the version number is not 4\n\t * then the packet may be another version of IP, such as IPng or\n\t * ST-II.\n\t */\n\tif (((pkt->version_ihl) >> 4) != 4)\n\t\treturn -3;\n\t/*\n\t * 4. The IP header length field must be large enough to hold the\n\t * minimum length legal IP datagram (20 bytes = 5 words).\n\t */\n\tif ((pkt->version_ihl & 0xf) < 5)\n\t\treturn -4;\n\n\t/*\n\t * 5. The IP total length field must be large enough to hold the IP\n\t * datagram header, whose length is specified in the IP header length\n\t * field.\n\t */\n\tif (rte_cpu_to_be_16(pkt->total_length) < sizeof(struct ipv4_hdr))\n\t\treturn -5;\n\n\treturn 0;\n}\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\nstatic void\nprint_key(struct ipv4_5tuple key)\n{\n\tprintf(\"IP dst = %08x, IP src = %08x, port dst = %d, port src = %d, proto = %d\\n\",\n\t (unsigned)key.ip_dst, (unsigned)key.ip_src, key.port_dst, key.port_src, key.proto);\n}\n\nstatic inline uint8_t\nget_dst_port(struct ipv4_hdr *ipv4_hdr, uint8_t portid, lookup_struct_t * l3fwd_lookup_struct)\n{\n\tstruct ipv4_5tuple key;\n\tstruct tcp_hdr *tcp;\n\tstruct udp_hdr *udp;\n\tint ret = 0;\n\n\tkey.ip_dst = rte_be_to_cpu_32(ipv4_hdr->dst_addr);\n\tkey.ip_src = rte_be_to_cpu_32(ipv4_hdr->src_addr);\n\tkey.proto = ipv4_hdr->next_proto_id;\n\n\tswitch (ipv4_hdr->next_proto_id) {\n\tcase IPPROTO_TCP:\n\t\ttcp = (struct tcp_hdr *)((unsigned char *) ipv4_hdr +\n\t\t\t\t\tsizeof(struct ipv4_hdr));\n\t\tkey.port_dst = rte_be_to_cpu_16(tcp->dst_port);\n\t\tkey.port_src = rte_be_to_cpu_16(tcp->src_port);\n\t\tbreak;\n\n\tcase IPPROTO_UDP:\n\t\tudp = (struct udp_hdr *)((unsigned char *) ipv4_hdr +\n\t\t\t\t\tsizeof(struct ipv4_hdr));\n\t\tkey.port_dst = rte_be_to_cpu_16(udp->dst_port);\n\t\tkey.port_src = rte_be_to_cpu_16(udp->src_port);\n\t\tbreak;\n\n\tdefault:\n\t\tkey.port_dst = 0;\n\t\tkey.port_src = 0;\n\t}\n\n\t/* Find destination port */\n\tret = rte_hash_lookup(l3fwd_lookup_struct, (const void *)&key);\n\treturn (uint8_t)((ret < 0)? portid : l3fwd_out_if[ret]);\n}\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\nstatic inline uint8_t\nget_dst_port(struct ipv4_hdr *ipv4_hdr, uint8_t portid, lookup_struct_t * l3fwd_lookup_struct)\n{\n\tuint8_t next_hop;\n\n\treturn (uint8_t) ((rte_lpm_lookup(l3fwd_lookup_struct,\n\t\t\trte_be_to_cpu_32(ipv4_hdr->dst_addr), &next_hop) == 0)?\n\t\t\tnext_hop : portid);\n}\n#endif\n\nstatic inline void\nl3fwd_simple_forward(struct rte_mbuf *m, uint8_t portid, lookup_struct_t * l3fwd_lookup_struct)\n{\n\tstruct ether_hdr *eth_hdr;\n\tstruct ipv4_hdr *ipv4_hdr;\n\tvoid *tmp;\n\tuint8_t dst_port;\n\n\teth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\tipv4_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,\n\t\t\t\t\t sizeof(struct ether_hdr));\n\n#ifdef DO_RFC_1812_CHECKS\n\t/* Check to make sure the packet is valid (RFC1812) */\n\tif (is_valid_ipv4_pkt(ipv4_hdr, m->pkt_len) < 0) {\n\t\trte_pktmbuf_free(m);\n\t\treturn;\n\t}\n#endif\n\n\tdst_port = get_dst_port(ipv4_hdr, portid, l3fwd_lookup_struct);\n\tif (dst_port >= RTE_MAX_ETHPORTS || (enabled_port_mask & 1 << dst_port) == 0)\n\t\tdst_port = portid;\n\n\t/* 02:00:00:00:00:xx */\n\ttmp = ð_hdr->d_addr.addr_bytes[0];\n\t*((uint64_t *)tmp) = 0x000000000002 + ((uint64_t)dst_port << 40);\n\n#ifdef DO_RFC_1812_CHECKS\n\t/* Update time to live and header checksum */\n\t--(ipv4_hdr->time_to_live);\n\t++(ipv4_hdr->hdr_checksum);\n#endif\n\n\t/* src addr */\n\tether_addr_copy(&ports_eth_addr[dst_port], ð_hdr->s_addr);\n\n\tsend_single_packet(m, dst_port);\n\n}\n\n/* main processing loop */\nstatic int\nmain_loop(__attribute__((unused)) void *dummy)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tunsigned lcore_id;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc;\n\tint i, j, nb_rx;\n\tuint8_t portid, queueid;\n\tstruct lcore_conf *qconf;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\tprev_tsc = 0;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_conf[lcore_id];\n\n\tif (qconf->n_rx_queue == 0) {\n\t\tRTE_LOG(INFO, L3FWD, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn 0;\n\t}\n\n\tRTE_LOG(INFO, L3FWD, \"entering main loop on lcore %u\\n\", lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_queue; i++) {\n\n\t\tportid = qconf->rx_queue_list[i].port_id;\n\t\tqueueid = qconf->rx_queue_list[i].queue_id;\n\t\tRTE_LOG(INFO, L3FWD, \" -- lcoreid=%u portid=%hhu rxqueueid=%hhu\\n\", lcore_id,\n\t\t\tportid, queueid);\n\t}\n\n\twhile (1) {\n\n\t\tcur_tsc = rte_rdtsc();\n\n\t\t/*\n\t\t * TX burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\t/*\n\t\t\t * This could be optimized (use queueid instead of\n\t\t\t * portid), but it is not called so often\n\t\t\t */\n\t\t\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t\t\tif (qconf->tx_mbufs[portid].len == 0)\n\t\t\t\t\tcontinue;\n\t\t\t\tsend_burst(&lcore_conf[lcore_id],\n\t\t\t\t\tqconf->tx_mbufs[portid].len,\n\t\t\t\t\tportid);\n\t\t\t\tqconf->tx_mbufs[portid].len = 0;\n\t\t\t}\n\n\t\t\tprev_tsc = cur_tsc;\n\t\t}\n\n\t\t/*\n\t\t * Read packet from RX queues\n\t\t */\n\t\tfor (i = 0; i < qconf->n_rx_queue; ++i) {\n\n\t\t\tportid = qconf->rx_queue_list[i].port_id;\n\t\t\tqueueid = qconf->rx_queue_list[i].queue_id;\n\t\t\tnb_rx = rte_eth_rx_burst(portid, queueid, pkts_burst, MAX_PKT_BURST);\n\n\t\t\t/* Prefetch first packets */\n\t\t\tfor (j = 0; j < PREFETCH_OFFSET && j < nb_rx; j++) {\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(\n\t\t\t\t\t\tpkts_burst[j], void *));\n\t\t\t}\n\n\t\t\t/* Prefetch and forward already prefetched packets */\n\t\t\tfor (j = 0; j < (nb_rx - PREFETCH_OFFSET); j++) {\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(pkts_burst[\n\t\t\t\t\t\tj + PREFETCH_OFFSET], void *));\n\t\t\t\tl3fwd_simple_forward(pkts_burst[j], portid, qconf->lookup_struct);\n\t\t\t}\n\n\t\t\t/* Forward remaining prefetched packets */\n\t\t\tfor (; j < nb_rx; j++) {\n\t\t\t\tl3fwd_simple_forward(pkts_burst[j], portid, qconf->lookup_struct);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic int\ncheck_lcore_params(void)\n{\n\tuint8_t queue, lcore;\n\tuint16_t i;\n\tint socketid;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tqueue = lcore_params[i].queue_id;\n\t\tif (queue >= MAX_RX_QUEUE_PER_PORT) {\n\t\t\tprintf(\"invalid queue number: %hhu\\n\", queue);\n\t\t\treturn -1;\n\t\t}\n\t\tlcore = lcore_params[i].lcore_id;\n\t\tif (!rte_lcore_is_enabled(lcore)) {\n\t\t\tprintf(\"error: lcore %hhu is not enabled in lcore mask\\n\", lcore);\n\t\t\treturn -1;\n\t\t}\n\t\tif ((socketid = rte_lcore_to_socket_id(lcore) != 0) &&\n\t\t\t(numa_on == 0)) {\n\t\t\tprintf(\"warning: lcore %hhu is on socket %d with numa off \\n\",\n\t\t\t\tlcore, socketid);\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\ncheck_port_config(const unsigned nb_ports)\n{\n\tunsigned portid;\n\tuint16_t i;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tportid = lcore_params[i].port_id;\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"port %u is not enabled in port mask\\n\", portid);\n\t\t\treturn -1;\n\t\t}\n\t\tif (portid >= nb_ports) {\n\t\t\tprintf(\"port %u is not present on the board\\n\", portid);\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic uint8_t\nget_port_n_rx_queues(const uint8_t port)\n{\n\tint queue = -1;\n\tuint16_t i;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tif (lcore_params[i].port_id == port && lcore_params[i].queue_id > queue)\n\t\t\tqueue = lcore_params[i].queue_id;\n\t}\n\treturn (uint8_t)(++queue);\n}\n\nstatic int\ninit_lcore_rx_queues(void)\n{\n\tuint16_t i, nb_rx_queue;\n\tuint8_t lcore;\n\n\tfor (i = 0; i < nb_lcore_params; ++i) {\n\t\tlcore = lcore_params[i].lcore_id;\n\t\tnb_rx_queue = lcore_conf[lcore].n_rx_queue;\n\t\tif (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) {\n\t\t\tprintf(\"error: too many queues (%u) for lcore: %u\\n\",\n\t\t\t\t(unsigned)nb_rx_queue + 1, (unsigned)lcore);\n\t\t\treturn -1;\n\t\t} else {\n\t\t\tlcore_conf[lcore].rx_queue_list[nb_rx_queue].port_id =\n\t\t\t\tlcore_params[i].port_id;\n\t\t\tlcore_conf[lcore].rx_queue_list[nb_rx_queue].queue_id =\n\t\t\t\tlcore_params[i].queue_id;\n\t\t\tlcore_conf[lcore].n_rx_queue++;\n\t\t}\n\t}\n\treturn 0;\n}\n\n/* display usage */\nstatic void\nprint_usage(const char *prgname)\n{\n\tprintf (\"%s [EAL options] -- -p PORTMASK\"\n\t\t\" [--config (port,queue,lcore)[,(port,queue,lcore]]\\n\"\n\t\t\" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t\t\" --config (port,queue,lcore): rx queues configuration\\n\"\n\t\t\" --no-numa: optional, disable numa awareness\\n\",\n\t\tprgname);\n}\n\n/* Custom handling of signals to handle process terminal */\nstatic void\nsignal_handler(int signum)\n{\n\tuint8_t portid;\n\tuint8_t nb_ports = rte_eth_dev_count();\n\n\t/* When we receive a SIGINT signal */\n\tif (signum == SIGINT) {\n\t\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t\t/* skip ports that are not enabled */\n\t\t\tif ((enabled_port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\trte_eth_dev_close(portid);\n\t\t}\n\t}\n\trte_exit(EXIT_SUCCESS, \"\\n User forced exit\\n\");\n}\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\nstatic int\nparse_config(const char *q_arg)\n{\n\tchar s[256];\n\tconst char *p, *p0 = q_arg;\n\tchar *end;\n\tenum fieldnames {\n\t\tFLD_PORT = 0,\n\t\tFLD_QUEUE,\n\t\tFLD_LCORE,\n\t\t_NUM_FLD\n\t};\n\tunsigned long int_fld[_NUM_FLD];\n\tchar *str_fld[_NUM_FLD];\n\tint i;\n\tunsigned size;\n\n\tnb_lcore_params = 0;\n\n\twhile ((p = strchr(p0,'(')) != NULL) {\n\t\t++p;\n\t\tif((p0 = strchr(p,')')) == NULL)\n\t\t\treturn -1;\n\n\t\tsize = p0 - p;\n\t\tif(size >= sizeof(s))\n\t\t\treturn -1;\n\n\t\tsnprintf(s, sizeof(s), \"%.*s\", size, p);\n\t\tif (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') != _NUM_FLD)\n\t\t\treturn -1;\n\t\tfor (i = 0; i < _NUM_FLD; i++){\n\t\t\terrno = 0;\n\t\t\tint_fld[i] = strtoul(str_fld[i], &end, 0);\n\t\t\tif (errno != 0 || end == str_fld[i] || int_fld[i] > 255)\n\t\t\t\treturn -1;\n\t\t}\n\t\tif (nb_lcore_params >= MAX_LCORE_PARAMS) {\n\t\t\tprintf(\"exceeded max number of lcore params: %hu\\n\",\n\t\t\t\tnb_lcore_params);\n\t\t\treturn -1;\n\t\t}\n\t\tlcore_params_array[nb_lcore_params].port_id = (uint8_t)int_fld[FLD_PORT];\n\t\tlcore_params_array[nb_lcore_params].queue_id = (uint8_t)int_fld[FLD_QUEUE];\n\t\tlcore_params_array[nb_lcore_params].lcore_id = (uint8_t)int_fld[FLD_LCORE];\n\t\t++nb_lcore_params;\n\t}\n\tlcore_params = lcore_params_array;\n\treturn 0;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{\"config\", 1, 0, 0},\n\t\t{\"no-numa\", 0, 0, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:\",\n\t\t\t\tlgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tif (!strcmp(lgopts[option_index].name, \"config\")) {\n\t\t\t\tret = parse_config(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"invalid config\\n\");\n\t\t\t\t\tprint_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (!strcmp(lgopts[option_index].name, \"no-numa\")) {\n\t\t\t\tprintf(\"numa is disabled \\n\");\n\t\t\t\tnuma_on = 0;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\nstatic void\nprint_ethaddr(const char *name, const struct ether_addr *eth_addr)\n{\n\tchar buf[ETHER_ADDR_FMT_SIZE];\n\tether_format_addr(buf, ETHER_ADDR_FMT_SIZE, eth_addr);\n\tprintf(\"%s%s\", name, buf);\n}\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_EXACT_MATCH)\nstatic void\nsetup_hash(int socketid)\n{\n\tunsigned i;\n\tint ret;\n\tchar s[64];\n\n\t/* create hashes */\n\tsnprintf(s, sizeof(s), \"l3fwd_hash_%d\", socketid);\n\tl3fwd_hash_params.name = s;\n\tl3fwd_hash_params.socket_id = socketid;\n\tl3fwd_lookup_struct[socketid] = rte_hash_create(&l3fwd_hash_params);\n\tif (l3fwd_lookup_struct[socketid] == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Unable to create the l3fwd hash on \"\n\t\t\t\t\"socket %d\\n\", socketid);\n\n\t/* populate the hash */\n\tfor (i = 0; i < L3FWD_NUM_ROUTES; i++) {\n\t\tret = rte_hash_add_key (l3fwd_lookup_struct[socketid],\n\t\t\t\t(void *) &l3fwd_route_array[i].key);\n\t\tif (ret < 0) {\n\t\t\trte_exit(EXIT_FAILURE, \"Unable to add entry %u to the\"\n\t\t\t\t\"l3fwd hash on socket %d\\n\", i, socketid);\n\t\t}\n\t\tl3fwd_out_if[ret] = l3fwd_route_array[i].if_out;\n\t\tprintf(\"Hash: Adding key\\n\");\n\t\tprint_key(l3fwd_route_array[i].key);\n\t}\n}\n#endif\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\nstatic void\nsetup_lpm(int socketid)\n{\n\tunsigned i;\n\tint ret;\n\tchar s[64];\n\n\t/* create the LPM table */\n\tsnprintf(s, sizeof(s), \"L3FWD_LPM_%d\", socketid);\n\tl3fwd_lookup_struct[socketid] = rte_lpm_create(s, socketid,\n\t\t\t\tL3FWD_LPM_MAX_RULES, 0);\n\tif (l3fwd_lookup_struct[socketid] == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Unable to create the l3fwd LPM table\"\n\t\t\t\t\" on socket %d\\n\", socketid);\n\n\t/* populate the LPM table */\n\tfor (i = 0; i < L3FWD_NUM_ROUTES; i++) {\n\t\tret = rte_lpm_add(l3fwd_lookup_struct[socketid],\n\t\t\tl3fwd_route_array[i].ip,\n\t\t\tl3fwd_route_array[i].depth,\n\t\t\tl3fwd_route_array[i].if_out);\n\n\t\tif (ret < 0) {\n\t\t\trte_exit(EXIT_FAILURE, \"Unable to add entry %u to the \"\n\t\t\t\t\"l3fwd LPM table on socket %d\\n\",\n\t\t\t\ti, socketid);\n\t\t}\n\n\t\tprintf(\"LPM: Adding route 0x%08x / %d (%d)\\n\",\n\t\t\t(unsigned)l3fwd_route_array[i].ip,\n\t\t\tl3fwd_route_array[i].depth,\n\t\t\tl3fwd_route_array[i].if_out);\n\t}\n}\n#endif\n\nstatic int\ninit_mem(unsigned nb_mbuf)\n{\n\tstruct lcore_conf *qconf;\n\tint socketid;\n\tunsigned lcore_id;\n\tchar s[64];\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\tcontinue;\n\n\t\tif (numa_on)\n\t\t\tsocketid = rte_lcore_to_socket_id(lcore_id);\n\t\telse\n\t\t\tsocketid = 0;\n\n\t\tif (socketid >= NB_SOCKETS) {\n\t\t\trte_exit(EXIT_FAILURE, \"Socket %d of lcore %u is out of range %d\\n\",\n\t\t\t\tsocketid, lcore_id, NB_SOCKETS);\n\t\t}\n\t\tif (pktmbuf_pool[socketid] == NULL) {\n\t\t\tsnprintf(s, sizeof(s), \"mbuf_pool_%d\", socketid);\n\t\t\tpktmbuf_pool[socketid] = rte_pktmbuf_pool_create(s,\n\t\t\t\tnb_mbuf, MEMPOOL_CACHE_SIZE, 0,\n\t\t\t\tRTE_MBUF_DEFAULT_BUF_SIZE, socketid);\n\t\t\tif (pktmbuf_pool[socketid] == NULL)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Cannot init mbuf pool on socket %d\\n\", socketid);\n\t\t\telse\n\t\t\t\tprintf(\"Allocated mbuf pool on socket %d\\n\", socketid);\n\n#if (APP_LOOKUP_METHOD == APP_LOOKUP_LPM)\n\t\t\tsetup_lpm(socketid);\n#else\n\t\t\tsetup_hash(socketid);\n#endif\n\t\t}\n\t\tqconf = &lcore_conf[lcore_id];\n\t\tqconf->lookup_struct = l3fwd_lookup_struct[socketid];\n\t}\n\treturn 0;\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_conf *qconf;\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_txconf *txconf;\n\tint ret;\n\tunsigned nb_ports;\n\tuint16_t queueid;\n\tunsigned lcore_id;\n\tuint32_t nb_lcores;\n\tuint16_t n_tx_queue;\n\tuint8_t portid, nb_rx_queue, queue, socketid;\n\n\tsignal(SIGINT, signal_handler);\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid EAL parameters\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid L3FWD-VF parameters\\n\");\n\n\tif (check_lcore_params() < 0)\n\t\trte_exit(EXIT_FAILURE, \"check_lcore_params failed\\n\");\n\n\tret = init_lcore_rx_queues();\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"init_lcore_rx_queues failed\\n\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\tif (check_port_config(nb_ports) < 0)\n\t\trte_exit(EXIT_FAILURE, \"check_port_config failed\\n\");\n\n\tnb_lcores = rte_lcore_count();\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"\\nSkipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* init port */\n\t\tprintf(\"Initializing port %d ... \", portid );\n\t\tfflush(stdout);\n\n\t\t/* must always equal(=1) */\n\t\tnb_rx_queue = get_port_n_rx_queues(portid);\n\t\tn_tx_queue = MAX_TX_QUEUE_PER_PORT;\n\n\t\tprintf(\"Creating queues: nb_rxq=%d nb_txq=%u... \",\n\t\t\tnb_rx_queue, (unsigned)1 );\n\t\tret = rte_eth_dev_configure(portid, nb_rx_queue, n_tx_queue, &port_conf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot configure device: err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\n\t\trte_eth_macaddr_get(portid, &ports_eth_addr[portid]);\n\t\tprint_ethaddr(\" Address:\", &ports_eth_addr[portid]);\n\t\tprintf(\", \");\n\n\t\tret = init_mem(NB_MBUF);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"init_mem failed\\n\");\n\n\t\t/* init one TX queue */\n\t\tsocketid = (uint8_t)rte_lcore_to_socket_id(rte_get_master_lcore());\n\n\t\tprintf(\"txq=%d,%d,%d \", portid, 0, socketid);\n\t\tfflush(stdout);\n\n\t\trte_eth_dev_info_get(portid, &dev_info);\n\t\ttxconf = &dev_info.default_txconf;\n\t\tif (port_conf.rxmode.jumbo_frame)\n\t\t\ttxconf->txq_flags = 0;\n\t\tret = rte_eth_tx_queue_setup(portid, 0, nb_txd,\n\t\t\t\t\t\t socketid, txconf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup: err=%d, \"\n\t\t\t\t\"port=%d\\n\", ret, portid);\n\n\t\tprintf(\"\\n\");\n\t}\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tif (rte_lcore_is_enabled(lcore_id) == 0)\n\t\t\tcontinue;\n\t\tqconf = &lcore_conf[lcore_id];\n\t\tqconf->tx_queue_id = 0;\n\n\t\tprintf(\"\\nInitializing rx queues on lcore %u ... \", lcore_id );\n\t\tfflush(stdout);\n\t\t/* init RX queues */\n\t\tfor(queue = 0; queue < qconf->n_rx_queue; ++queue) {\n\t\t\tportid = qconf->rx_queue_list[queue].port_id;\n\t\t\tqueueid = qconf->rx_queue_list[queue].queue_id;\n\n\t\t\tif (numa_on)\n\t\t\t\tsocketid = (uint8_t)rte_lcore_to_socket_id(lcore_id);\n\t\t\telse\n\t\t\t\tsocketid = 0;\n\n\t\t\tprintf(\"rxq=%d,%d,%d \", portid, queueid, socketid);\n\t\t\tfflush(stdout);\n\n\t\t\tret = rte_eth_rx_queue_setup(portid, queueid, nb_rxd,\n\t\t\t\t\t\tsocketid, NULL,\n\t\t\t\t\t\tpktmbuf_pool[socketid]);\n\t\t\tif (ret < 0)\n\t\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup: err=%d,\"\n\t\t\t\t\t\t\"port=%d\\n\", ret, portid);\n\t\t}\n\t}\n\tprintf(\"\\n\");\n\n\t/* start ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tcontinue;\n\t\t}\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_dev_start: err=%d, port=%d\\n\",\n\t\t\t\tret, portid);\n\n\t\tprintf(\"done: Port %d\\n\", portid);\n\n\t}\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/link_status_interrupt/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = link_status_interrupt\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/link_status_interrupt/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define RTE_LOGTYPE_LSI RTE_LOGTYPE_USER1\n\n#define NB_MBUF 8192\n\n#define MAX_PKT_BURST 32\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n/* ethernet addresses of ports */\nstatic struct ether_addr lsi_ports_eth_addr[RTE_MAX_ETHPORTS];\n\n/* mask of enabled ports */\nstatic uint32_t lsi_enabled_port_mask = 0;\n\nstatic unsigned int lsi_rx_queue_per_lcore = 1;\n\n/* destination port for L2 forwarding */\nstatic unsigned lsi_dst_ports[RTE_MAX_ETHPORTS] = {0};\n\n#define MAX_PKT_BURST 32\nstruct mbuf_table {\n\tunsigned len;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST];\n};\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT 16\nstruct lcore_queue_conf {\n\tunsigned n_rx_port;\n\tunsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE];\n\tunsigned tx_queue_id;\n\tstruct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];\n\n} __rte_cache_aligned;\nstruct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];\n\nstatic const struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n\t.intr_conf = {\n\t\t.lsc = 1, /**< lsc interrupt feature enabled */\n\t},\n};\n\nstruct rte_mempool * lsi_pktmbuf_pool = NULL;\n\n/* Per-port statistics struct */\nstruct lsi_port_statistics {\n\tuint64_t tx;\n\tuint64_t rx;\n\tuint64_t dropped;\n} __rte_cache_aligned;\nstruct lsi_port_statistics port_statistics[RTE_MAX_ETHPORTS];\n\n/* A tsc-based timer responsible for triggering statistics printout */\n#define TIMER_MILLISECOND 2000000ULL /* around 1ms at 2 Ghz */\n#define MAX_TIMER_PERIOD 86400 /* 1 day max */\nstatic int64_t timer_period = 10 * TIMER_MILLISECOND * 1000; /* default period is 10 seconds */\n\n/* Print out statistics on packets dropped */\nstatic void\nprint_stats(void)\n{\n\tstruct rte_eth_link link;\n\tuint64_t total_packets_dropped, total_packets_tx, total_packets_rx;\n\tunsigned portid;\n\n\ttotal_packets_dropped = 0;\n\ttotal_packets_tx = 0;\n\ttotal_packets_rx = 0;\n\n\tconst char clr[] = { 27, '[', '2', 'J', '\\0' };\n\tconst char topLeft[] = { 27, '[', '1', ';', '1', 'H','\\0' };\n\n\t\t/* Clear screen and move to top left */\n\tprintf(\"%s%s\", clr, topLeft);\n\n\tprintf(\"\\nPort statistics ====================================\");\n\n\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((lsi_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\n\t\tmemset(&link, 0, sizeof(link));\n\t\trte_eth_link_get_nowait((uint8_t)portid, &link);\n\t\tprintf(\"\\nStatistics for port %u ------------------------------\"\n\t\t\t \"\\nLink status: %25s\"\n\t\t\t \"\\nLink speed: %26u\"\n\t\t\t \"\\nLink duplex: %25s\"\n\t\t\t \"\\nPackets sent: %24\"PRIu64\n\t\t\t \"\\nPackets received: %20\"PRIu64\n\t\t\t \"\\nPackets dropped: %21\"PRIu64,\n\t\t\t portid,\n\t\t\t (link.link_status ? \"Link up\" : \"Link down\"),\n\t\t\t (unsigned)link.link_speed,\n\t\t\t (link.link_duplex == ETH_LINK_FULL_DUPLEX ? \\\n\t\t\t\t\t\"full-duplex\" : \"half-duplex\"),\n\t\t\t port_statistics[portid].tx,\n\t\t\t port_statistics[portid].rx,\n\t\t\t port_statistics[portid].dropped);\n\n\t\ttotal_packets_dropped += port_statistics[portid].dropped;\n\t\ttotal_packets_tx += port_statistics[portid].tx;\n\t\ttotal_packets_rx += port_statistics[portid].rx;\n\t}\n\tprintf(\"\\nAggregate statistics ===============================\"\n\t\t \"\\nTotal packets sent: %18\"PRIu64\n\t\t \"\\nTotal packets received: %14\"PRIu64\n\t\t \"\\nTotal packets dropped: %15\"PRIu64,\n\t\t total_packets_tx,\n\t\t total_packets_rx,\n\t\t total_packets_dropped);\n\tprintf(\"\\n====================================================\\n\");\n}\n\n/* Send the packet on an output interface */\nstatic int\nlsi_send_burst(struct lcore_queue_conf *qconf, unsigned n, uint8_t port)\n{\n\tstruct rte_mbuf **m_table;\n\tunsigned ret;\n\tunsigned queueid;\n\n\tqueueid = (uint16_t) qconf->tx_queue_id;\n\tm_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;\n\n\tret = rte_eth_tx_burst(port, (uint16_t) queueid, m_table, (uint16_t) n);\n\tport_statistics[port].tx += ret;\n\tif (unlikely(ret < n)) {\n\t\tport_statistics[port].dropped += (n - ret);\n\t\tdo {\n\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t} while (++ret < n);\n\t}\n\n\treturn 0;\n}\n\n/* Send the packet on an output interface */\nstatic int\nlsi_send_packet(struct rte_mbuf *m, uint8_t port)\n{\n\tunsigned lcore_id, len;\n\tstruct lcore_queue_conf *qconf;\n\n\tlcore_id = rte_lcore_id();\n\n\tqconf = &lcore_queue_conf[lcore_id];\n\tlen = qconf->tx_mbufs[port].len;\n\tqconf->tx_mbufs[port].m_table[len] = m;\n\tlen++;\n\n\t/* enough pkts to be sent */\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tlsi_send_burst(qconf, MAX_PKT_BURST, port);\n\t\tlen = 0;\n\t}\n\n\tqconf->tx_mbufs[port].len = len;\n\treturn 0;\n}\n\nstatic void\nlsi_simple_forward(struct rte_mbuf *m, unsigned portid)\n{\n\tstruct ether_hdr *eth;\n\tvoid *tmp;\n\tunsigned dst_port = lsi_dst_ports[portid];\n\n\teth = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\t/* 02:00:00:00:00:xx */\n\ttmp = ð->d_addr.addr_bytes[0];\n\t*((uint64_t *)tmp) = 0x000000000002 + ((uint64_t)dst_port << 40);\n\n\t/* src addr */\n\tether_addr_copy(&lsi_ports_eth_addr[dst_port], ð->s_addr);\n\n\tlsi_send_packet(m, (uint8_t) dst_port);\n}\n\n/* main processing loop */\nstatic void\nlsi_main_loop(void)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_mbuf *m;\n\tunsigned lcore_id;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc, timer_tsc;\n\tunsigned i, j, portid, nb_rx;\n\tstruct lcore_queue_conf *qconf;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\tprev_tsc = 0;\n\ttimer_tsc = 0;\n\n\tlcore_id = rte_lcore_id();\n\tqconf = &lcore_queue_conf[lcore_id];\n\n\tif (qconf->n_rx_port == 0) {\n\t\tRTE_LOG(INFO, LSI, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn;\n\t}\n\n\tRTE_LOG(INFO, LSI, \"entering main loop on lcore %u\\n\", lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\n\t\tportid = qconf->rx_port_list[i];\n\t\tRTE_LOG(INFO, LSI, \" -- lcoreid=%u portid=%u\\n\", lcore_id,\n\t\t\tportid);\n\t}\n\n\twhile (1) {\n\n\t\tcur_tsc = rte_rdtsc();\n\n\t\t/*\n\t\t * TX burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\t/* this could be optimized (use queueid instead of\n\t\t\t * portid), but it is not called so often */\n\t\t\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t\t\tif (qconf->tx_mbufs[portid].len == 0)\n\t\t\t\t\tcontinue;\n\t\t\t\tlsi_send_burst(&lcore_queue_conf[lcore_id],\n\t\t\t\t\t\t qconf->tx_mbufs[portid].len,\n\t\t\t\t\t\t (uint8_t) portid);\n\t\t\t\tqconf->tx_mbufs[portid].len = 0;\n\t\t\t}\n\n\t\t\t/* if timer is enabled */\n\t\t\tif (timer_period > 0) {\n\n\t\t\t\t/* advance the timer */\n\t\t\t\ttimer_tsc += diff_tsc;\n\n\t\t\t\t/* if timer has reached its timeout */\n\t\t\t\tif (unlikely(timer_tsc >= (uint64_t) timer_period)) {\n\n\t\t\t\t\t/* do this only on master core */\n\t\t\t\t\tif (lcore_id == rte_get_master_lcore()) {\n\t\t\t\t\t\tprint_stats();\n\t\t\t\t\t\t/* reset the timer */\n\t\t\t\t\t\ttimer_tsc = 0;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tprev_tsc = cur_tsc;\n\t\t}\n\n\t\t/*\n\t\t * Read packet from RX queues\n\t\t */\n\t\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\n\t\t\tportid = qconf->rx_port_list[i];\n\t\t\tnb_rx = rte_eth_rx_burst((uint8_t) portid, 0,\n\t\t\t\t\t\t pkts_burst, MAX_PKT_BURST);\n\n\t\t\tport_statistics[portid].rx += nb_rx;\n\n\t\t\tfor (j = 0; j < nb_rx; j++) {\n\t\t\t\tm = pkts_burst[j];\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(m, void *));\n\t\t\t\tlsi_simple_forward(m, portid);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic int\nlsi_launch_one_lcore(__attribute__((unused)) void *dummy)\n{\n\tlsi_main_loop();\n\treturn 0;\n}\n\n/* display usage */\nstatic void\nlsi_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK [-q NQ]\\n\"\n\t\t\" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t\t\" -q NQ: number of queue (=ports) per lcore (default is 1)\\n\"\n\t\t\" -T PERIOD: statistics will be refreshed each PERIOD seconds (0 to disable, 10 default, 86400 maximum)\\n\",\n\t\t\tprgname);\n}\n\nstatic int\nlsi_parse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\nstatic unsigned int\nlsi_parse_nqueue(const char *q_arg)\n{\n\tchar *end = NULL;\n\tunsigned long n;\n\n\t/* parse hexadecimal string */\n\tn = strtoul(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn 0;\n\tif (n == 0)\n\t\treturn 0;\n\tif (n >= MAX_RX_QUEUE_PER_LCORE)\n\t\treturn 0;\n\n\treturn n;\n}\n\nstatic int\nlsi_parse_timer_period(const char *q_arg)\n{\n\tchar *end = NULL;\n\tint n;\n\n\t/* parse number string */\n\tn = strtol(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\tif (n >= MAX_TIMER_PERIOD)\n\t\treturn -1;\n\n\treturn n;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nlsi_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:q:T:\",\n\t\t\t\t lgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tlsi_enabled_port_mask = lsi_parse_portmask(optarg);\n\t\t\tif (lsi_enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tlsi_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* nqueue */\n\t\tcase 'q':\n\t\t\tlsi_rx_queue_per_lcore = lsi_parse_nqueue(optarg);\n\t\t\tif (lsi_rx_queue_per_lcore == 0) {\n\t\t\t\tprintf(\"invalid queue number\\n\");\n\t\t\t\tlsi_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* timer period */\n\t\tcase 'T':\n\t\t\ttimer_period = lsi_parse_timer_period(optarg) * 1000 * TIMER_MILLISECOND;\n\t\t\tif (timer_period < 0) {\n\t\t\t\tprintf(\"invalid timer period\\n\");\n\t\t\t\tlsi_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tlsi_usage(prgname);\n\t\t\treturn -1;\n\n\t\tdefault:\n\t\t\tlsi_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\n/**\n * It will be called as the callback for specified port after a LSI interrupt\n * has been fully handled. This callback needs to be implemented carefully as\n * it will be called in the interrupt host thread which is different from the\n * application main thread.\n *\n * @param port_id\n * Port id.\n * @param type\n * event type.\n * @param param\n * Pointer to(address of) the parameters.\n *\n * @return\n * void.\n */\nstatic void\nlsi_event_callback(uint8_t port_id, enum rte_eth_event_type type, void *param)\n{\n\tstruct rte_eth_link link;\n\n\tRTE_SET_USED(param);\n\n\tprintf(\"\\n\\nIn registered callback...\\n\");\n\tprintf(\"Event type: %s\\n\", type == RTE_ETH_EVENT_INTR_LSC ? \"LSC interrupt\" : \"unknown event\");\n\trte_eth_link_get_nowait(port_id, &link);\n\tif (link.link_status) {\n\t\tprintf(\"Port %d Link Up - speed %u Mbps - %s\\n\\n\",\n\t\t\t\tport_id, (unsigned)link.link_speed,\n\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t(\"full-duplex\") : (\"half-duplex\"));\n\t} else\n\t\tprintf(\"Port %d Link Down\\n\\n\", port_id);\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_queue_conf *qconf;\n\tstruct rte_eth_dev_info dev_info;\n\tint ret;\n\tuint8_t nb_ports;\n\tuint8_t portid, portid_last = 0;\n\tunsigned lcore_id, rx_lcore_id;\n\tunsigned nb_ports_in_mask = 0;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"rte_eal_init failed\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = lsi_parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid arguments\");\n\n\t/* create the mbuf pool */\n\tlsi_pktmbuf_pool =\n\t\trte_pktmbuf_pool_create(\"mbuf_pool\", NB_MBUF, 32, 0,\n\t\t\tRTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\tif (lsi_pktmbuf_pool == NULL)\n\t\trte_panic(\"Cannot init mbuf pool\\n\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports == 0)\n\t\trte_panic(\"No Ethernet port - bye\\n\");\n\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\t/*\n\t * Each logical core is assigned a dedicated TX queue on each port.\n\t */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((lsi_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\n\t\t/* save the destination port id */\n\t\tif (nb_ports_in_mask % 2) {\n\t\t\tlsi_dst_ports[portid] = portid_last;\n\t\t\tlsi_dst_ports[portid_last] = portid;\n\t\t}\n\t\telse\n\t\t\tportid_last = portid;\n\n\t\tnb_ports_in_mask++;\n\n\t\trte_eth_dev_info_get(portid, &dev_info);\n\t}\n\tif (nb_ports_in_mask < 2 || nb_ports_in_mask % 2)\n\t\trte_exit(EXIT_FAILURE, \"Current enabled port number is %u, \"\n\t\t\t\t\"but it should be even and at least 2\\n\",\n\t\t\t\tnb_ports_in_mask);\n\n\trx_lcore_id = 0;\n\tqconf = &lcore_queue_conf[rx_lcore_id];\n\n\t/* Initialize the port/queue configuration of each logical core */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((lsi_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\n\t\t/* get the lcore_id for this port */\n\t\twhile (rte_lcore_is_enabled(rx_lcore_id) == 0 ||\n\t\t lcore_queue_conf[rx_lcore_id].n_rx_port ==\n\t\t lsi_rx_queue_per_lcore) {\n\n\t\t\trx_lcore_id++;\n\t\t\tif (rx_lcore_id >= RTE_MAX_LCORE)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Not enough cores\\n\");\n\t\t}\n\t\tif (qconf != &lcore_queue_conf[rx_lcore_id])\n\t\t\t/* Assigned a new logical core in the loop above. */\n\t\t\tqconf = &lcore_queue_conf[rx_lcore_id];\n\n\t\tqconf->rx_port_list[qconf->n_rx_port] = portid;\n\t\tqconf->n_rx_port++;\n\t\tprintf(\"Lcore %u: RX port %u\\n\",rx_lcore_id, (unsigned) portid);\n\t}\n\n\t/* Initialise each port */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((lsi_enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"Skipping disabled port %u\\n\", (unsigned) portid);\n\t\t\tcontinue;\n\t\t}\n\t\t/* init port */\n\t\tprintf(\"Initializing port %u... \", (unsigned) portid);\n\t\tfflush(stdout);\n\t\tret = rte_eth_dev_configure(portid, 1, 1, &port_conf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot configure device: err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\t/* register lsi interrupt callback, need to be after\n\t\t * rte_eth_dev_configure(). if (intr_conf.lsc == 0), no\n\t\t * lsc interrupt will be present, and below callback to\n\t\t * be registered will never be called.\n\t\t */\n\t\trte_eth_dev_callback_register(portid,\n\t\t\tRTE_ETH_EVENT_INTR_LSC, lsi_event_callback, NULL);\n\n\t\trte_eth_macaddr_get(portid,\n\t\t\t\t &lsi_ports_eth_addr[portid]);\n\n\t\t/* init one RX queue */\n\t\tfflush(stdout);\n\t\tret = rte_eth_rx_queue_setup(portid, 0, nb_rxd,\n\t\t\t\t\t rte_eth_dev_socket_id(portid),\n\t\t\t\t\t NULL,\n\t\t\t\t\t lsi_pktmbuf_pool);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup: err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\t/* init one TX queue logical core on each port */\n\t\tfflush(stdout);\n\t\tret = rte_eth_tx_queue_setup(portid, 0, nb_txd,\n\t\t\t\trte_eth_dev_socket_id(portid),\n\t\t\t\tNULL);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup: err=%d,port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_dev_start: err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\t\tprintf(\"done:\\n\");\n\n\t\tprintf(\"Port %u, MAC address: %02X:%02X:%02X:%02X:%02X:%02X\\n\\n\",\n\t\t\t\t(unsigned) portid,\n\t\t\t\tlsi_ports_eth_addr[portid].addr_bytes[0],\n\t\t\t\tlsi_ports_eth_addr[portid].addr_bytes[1],\n\t\t\t\tlsi_ports_eth_addr[portid].addr_bytes[2],\n\t\t\t\tlsi_ports_eth_addr[portid].addr_bytes[3],\n\t\t\t\tlsi_ports_eth_addr[portid].addr_bytes[4],\n\t\t\t\tlsi_ports_eth_addr[portid].addr_bytes[5]);\n\n\t\t/* initialize port stats */\n\t\tmemset(&port_statistics, 0, sizeof(port_statistics));\n\t}\n\n\tcheck_all_ports_link_status(nb_ports, lsi_enabled_port_mask);\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(lsi_launch_one_lcore, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/load_balancer/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = load_balancer\n\n# all source are stored in SRCS-y\nSRCS-y := main.c config.c init.c runtime.c\n\nCFLAGS += -O3 -g\nCFLAGS += $(WERROR_FLAGS)\nCFLAGS_config.o := -D_GNU_SOURCE\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/load_balancer/config.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\nstruct app_params app;\n\nstatic const char usage[] =\n\" \\n\"\n\" load_balancer -- \\n\"\n\" \\n\"\n\"Application manadatory parameters: \\n\"\n\" --rx \\\"(PORT, QUEUE, LCORE), ...\\\" : List of NIC RX ports and queues \\n\"\n\" handled by the I/O RX lcores \\n\"\n\" --tx \\\"(PORT, LCORE), ...\\\" : List of NIC TX ports handled by the I/O TX \\n\"\n\" lcores \\n\"\n\" --w \\\"LCORE, ...\\\" : List of the worker lcores \\n\"\n\" --lpm \\\"IP / PREFIX => PORT; ...\\\" : List of LPM rules used by the worker \\n\"\n\" lcores for packet forwarding \\n\"\n\" \\n\"\n\"Application optional parameters: \\n\"\n\" --rsz \\\"A, B, C, D\\\" : Ring sizes \\n\"\n\" A = Size (in number of buffer descriptors) of each of the NIC RX \\n\"\n\" rings read by the I/O RX lcores (default value is %u) \\n\"\n\" B = Size (in number of elements) of each of the SW rings used by the\\n\"\n\" I/O RX lcores to send packets to worker lcores (default value is\\n\"\n\" %u) \\n\"\n\" C = Size (in number of elements) of each of the SW rings used by the\\n\"\n\" worker lcores to send packets to I/O TX lcores (default value is\\n\"\n\" %u) \\n\"\n\" D = Size (in number of buffer descriptors) of each of the NIC TX \\n\"\n\" rings written by I/O TX lcores (default value is %u) \\n\"\n\" --bsz \\\"(A, B), (C, D), (E, F)\\\" : Burst sizes \\n\"\n\" A = I/O RX lcore read burst size from NIC RX (default value is %u) \\n\"\n\" B = I/O RX lcore write burst size to output SW rings (default value \\n\"\n\" is %u) \\n\"\n\" C = Worker lcore read burst size from input SW rings (default value \\n\"\n\" is %u) \\n\"\n\" D = Worker lcore write burst size to output SW rings (default value \\n\"\n\" is %u) \\n\"\n\" E = I/O TX lcore read burst size from input SW rings (default value \\n\"\n\" is %u) \\n\"\n\" F = I/O TX lcore write burst size to NIC TX (default value is %u) \\n\"\n\" --pos-lb POS : Position of the 1-byte field within the input packet used by\\n\"\n\" the I/O RX lcores to identify the worker lcore for the current \\n\"\n\" packet (default value is %u) \\n\";\n\nvoid\napp_print_usage(void)\n{\n\tprintf(usage,\n\t\tAPP_DEFAULT_NIC_RX_RING_SIZE,\n\t\tAPP_DEFAULT_RING_RX_SIZE,\n\t\tAPP_DEFAULT_RING_TX_SIZE,\n\t\tAPP_DEFAULT_NIC_TX_RING_SIZE,\n\t\tAPP_DEFAULT_BURST_SIZE_IO_RX_READ,\n\t\tAPP_DEFAULT_BURST_SIZE_IO_RX_WRITE,\n\t\tAPP_DEFAULT_BURST_SIZE_WORKER_READ,\n\t\tAPP_DEFAULT_BURST_SIZE_WORKER_WRITE,\n\t\tAPP_DEFAULT_BURST_SIZE_IO_TX_READ,\n\t\tAPP_DEFAULT_BURST_SIZE_IO_TX_WRITE,\n\t\tAPP_DEFAULT_IO_RX_LB_POS\n\t);\n}\n\n#ifndef APP_ARG_RX_MAX_CHARS\n#define APP_ARG_RX_MAX_CHARS 4096\n#endif\n\n#ifndef APP_ARG_RX_MAX_TUPLES\n#define APP_ARG_RX_MAX_TUPLES 128\n#endif\n\nstatic int\nstr_to_unsigned_array(\n\tconst char *s, size_t sbuflen,\n\tchar separator,\n\tunsigned num_vals,\n\tunsigned *vals)\n{\n\tchar str[sbuflen+1];\n\tchar *splits[num_vals];\n\tchar *endptr = NULL;\n\tint i, num_splits = 0;\n\n\t/* copy s so we don't modify original string */\n\tsnprintf(str, sizeof(str), \"%s\", s);\n\tnum_splits = rte_strsplit(str, sizeof(str), splits, num_vals, separator);\n\n\terrno = 0;\n\tfor (i = 0; i < num_splits; i++) {\n\t\tvals[i] = strtoul(splits[i], &endptr, 0);\n\t\tif (errno != 0 || *endptr != '\\0')\n\t\t\treturn -1;\n\t}\n\n\treturn num_splits;\n}\n\nstatic int\nstr_to_unsigned_vals(\n\tconst char *s,\n\tsize_t sbuflen,\n\tchar separator,\n\tunsigned num_vals, ...)\n{\n\tunsigned i, vals[num_vals];\n\tva_list ap;\n\n\tnum_vals = str_to_unsigned_array(s, sbuflen, separator, num_vals, vals);\n\n\tva_start(ap, num_vals);\n\tfor (i = 0; i < num_vals; i++) {\n\t\tunsigned *u = va_arg(ap, unsigned *);\n\t\t*u = vals[i];\n\t}\n\tva_end(ap);\n\treturn num_vals;\n}\n\nstatic int\nparse_arg_rx(const char *arg)\n{\n\tconst char *p0 = arg, *p = arg;\n\tuint32_t n_tuples;\n\n\tif (strnlen(arg, APP_ARG_RX_MAX_CHARS + 1) == APP_ARG_RX_MAX_CHARS + 1) {\n\t\treturn -1;\n\t}\n\n\tn_tuples = 0;\n\twhile ((p = strchr(p0,'(')) != NULL) {\n\t\tstruct app_lcore_params *lp;\n\t\tuint32_t port, queue, lcore, i;\n\n\t\tp0 = strchr(p++, ')');\n\t\tif ((p0 == NULL) ||\n\t\t (str_to_unsigned_vals(p, p0 - p, ',', 3, &port, &queue, &lcore) != 3)) {\n\t\t\treturn -2;\n\t\t}\n\n\t\t/* Enable port and queue for later initialization */\n\t\tif ((port >= APP_MAX_NIC_PORTS) || (queue >= APP_MAX_RX_QUEUES_PER_NIC_PORT)) {\n\t\t\treturn -3;\n\t\t}\n\t\tif (app.nic_rx_queue_mask[port][queue] != 0) {\n\t\t\treturn -4;\n\t\t}\n\t\tapp.nic_rx_queue_mask[port][queue] = 1;\n\n\t\t/* Check and assign (port, queue) to I/O lcore */\n\t\tif (rte_lcore_is_enabled(lcore) == 0) {\n\t\t\treturn -5;\n\t\t}\n\n\t\tif (lcore >= APP_MAX_LCORES) {\n\t\t\treturn -6;\n\t\t}\n\t\tlp = &app.lcore_params[lcore];\n\t\tif (lp->type == e_APP_LCORE_WORKER) {\n\t\t\treturn -7;\n\t\t}\n\t\tlp->type = e_APP_LCORE_IO;\n\t\tconst size_t n_queues = RTE_MIN(lp->io.rx.n_nic_queues,\n\t\t RTE_DIM(lp->io.rx.nic_queues));\n\t\tfor (i = 0; i < n_queues; i ++) {\n\t\t\tif ((lp->io.rx.nic_queues[i].port == port) &&\n\t\t\t (lp->io.rx.nic_queues[i].queue == queue)) {\n\t\t\t\treturn -8;\n\t\t\t}\n\t\t}\n\t\tif (lp->io.rx.n_nic_queues >= APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE) {\n\t\t\treturn -9;\n\t\t}\n\t\tlp->io.rx.nic_queues[lp->io.rx.n_nic_queues].port = (uint8_t) port;\n\t\tlp->io.rx.nic_queues[lp->io.rx.n_nic_queues].queue = (uint8_t) queue;\n\t\tlp->io.rx.n_nic_queues ++;\n\n\t\tn_tuples ++;\n\t\tif (n_tuples > APP_ARG_RX_MAX_TUPLES) {\n\t\t\treturn -10;\n\t\t}\n\t}\n\n\tif (n_tuples == 0) {\n\t\treturn -11;\n\t}\n\n\treturn 0;\n}\n\n#ifndef APP_ARG_TX_MAX_CHARS\n#define APP_ARG_TX_MAX_CHARS 4096\n#endif\n\n#ifndef APP_ARG_TX_MAX_TUPLES\n#define APP_ARG_TX_MAX_TUPLES 128\n#endif\n\nstatic int\nparse_arg_tx(const char *arg)\n{\n\tconst char *p0 = arg, *p = arg;\n\tuint32_t n_tuples;\n\n\tif (strnlen(arg, APP_ARG_TX_MAX_CHARS + 1) == APP_ARG_TX_MAX_CHARS + 1) {\n\t\treturn -1;\n\t}\n\n\tn_tuples = 0;\n\twhile ((p = strchr(p0,'(')) != NULL) {\n\t\tstruct app_lcore_params *lp;\n\t\tuint32_t port, lcore, i;\n\n\t\tp0 = strchr(p++, ')');\n\t\tif ((p0 == NULL) ||\n\t\t (str_to_unsigned_vals(p, p0 - p, ',', 2, &port, &lcore) != 2)) {\n\t\t\treturn -2;\n\t\t}\n\n\t\t/* Enable port and queue for later initialization */\n\t\tif (port >= APP_MAX_NIC_PORTS) {\n\t\t\treturn -3;\n\t\t}\n\t\tif (app.nic_tx_port_mask[port] != 0) {\n\t\t\treturn -4;\n\t\t}\n\t\tapp.nic_tx_port_mask[port] = 1;\n\n\t\t/* Check and assign (port, queue) to I/O lcore */\n\t\tif (rte_lcore_is_enabled(lcore) == 0) {\n\t\t\treturn -5;\n\t\t}\n\n\t\tif (lcore >= APP_MAX_LCORES) {\n\t\t\treturn -6;\n\t\t}\n\t\tlp = &app.lcore_params[lcore];\n\t\tif (lp->type == e_APP_LCORE_WORKER) {\n\t\t\treturn -7;\n\t\t}\n\t\tlp->type = e_APP_LCORE_IO;\n\t\tconst size_t n_ports = RTE_MIN(lp->io.tx.n_nic_ports,\n\t\t RTE_DIM(lp->io.tx.nic_ports));\n\t\tfor (i = 0; i < n_ports; i ++) {\n\t\t\tif (lp->io.tx.nic_ports[i] == port) {\n\t\t\t\treturn -8;\n\t\t\t}\n\t\t}\n\t\tif (lp->io.tx.n_nic_ports >= APP_MAX_NIC_TX_PORTS_PER_IO_LCORE) {\n\t\t\treturn -9;\n\t\t}\n\t\tlp->io.tx.nic_ports[lp->io.tx.n_nic_ports] = (uint8_t) port;\n\t\tlp->io.tx.n_nic_ports ++;\n\n\t\tn_tuples ++;\n\t\tif (n_tuples > APP_ARG_TX_MAX_TUPLES) {\n\t\t\treturn -10;\n\t\t}\n\t}\n\n\tif (n_tuples == 0) {\n\t\treturn -11;\n\t}\n\n\treturn 0;\n}\n\n#ifndef APP_ARG_W_MAX_CHARS\n#define APP_ARG_W_MAX_CHARS 4096\n#endif\n\n#ifndef APP_ARG_W_MAX_TUPLES\n#define APP_ARG_W_MAX_TUPLES APP_MAX_WORKER_LCORES\n#endif\n\nstatic int\nparse_arg_w(const char *arg)\n{\n\tconst char *p = arg;\n\tuint32_t n_tuples;\n\n\tif (strnlen(arg, APP_ARG_W_MAX_CHARS + 1) == APP_ARG_W_MAX_CHARS + 1) {\n\t\treturn -1;\n\t}\n\n\tn_tuples = 0;\n\twhile (*p != 0) {\n\t\tstruct app_lcore_params *lp;\n\t\tuint32_t lcore;\n\n\t\terrno = 0;\n\t\tlcore = strtoul(p, NULL, 0);\n\t\tif ((errno != 0)) {\n\t\t\treturn -2;\n\t\t}\n\n\t\t/* Check and enable worker lcore */\n\t\tif (rte_lcore_is_enabled(lcore) == 0) {\n\t\t\treturn -3;\n\t\t}\n\n\t\tif (lcore >= APP_MAX_LCORES) {\n\t\t\treturn -4;\n\t\t}\n\t\tlp = &app.lcore_params[lcore];\n\t\tif (lp->type == e_APP_LCORE_IO) {\n\t\t\treturn -5;\n\t\t}\n\t\tlp->type = e_APP_LCORE_WORKER;\n\n\t\tn_tuples ++;\n\t\tif (n_tuples > APP_ARG_W_MAX_TUPLES) {\n\t\t\treturn -6;\n\t\t}\n\n\t\tp = strchr(p, ',');\n\t\tif (p == NULL) {\n\t\t\tbreak;\n\t\t}\n\t\tp ++;\n\t}\n\n\tif (n_tuples == 0) {\n\t\treturn -7;\n\t}\n\n\tif ((n_tuples & (n_tuples - 1)) != 0) {\n\t\treturn -8;\n\t}\n\n\treturn 0;\n}\n\n#ifndef APP_ARG_LPM_MAX_CHARS\n#define APP_ARG_LPM_MAX_CHARS 4096\n#endif\n\nstatic int\nparse_arg_lpm(const char *arg)\n{\n\tconst char *p = arg, *p0;\n\n\tif (strnlen(arg, APP_ARG_LPM_MAX_CHARS + 1) == APP_ARG_TX_MAX_CHARS + 1) {\n\t\treturn -1;\n\t}\n\n\twhile (*p != 0) {\n\t\tuint32_t ip_a, ip_b, ip_c, ip_d, ip, depth, if_out;\n\t\tchar *endptr;\n\n\t\tp0 = strchr(p, '/');\n\t\tif ((p0 == NULL) ||\n\t\t (str_to_unsigned_vals(p, p0 - p, '.', 4, &ip_a, &ip_b, &ip_c, &ip_d) != 4)) {\n\t\t\treturn -2;\n\t\t}\n\n\t\tp = p0 + 1;\n\t\terrno = 0;\n\t\tdepth = strtoul(p, &endptr, 0);\n\t\tif (errno != 0 || *endptr != '=') {\n\t\t\treturn -3;\n\t\t}\n\t\tp = strchr(p, '>');\n\t\tif (p == NULL) {\n\t\t\treturn -4;\n\t\t}\n\t\tif_out = strtoul(++p, &endptr, 0);\n\t\tif (errno != 0 || (*endptr != '\\0' && *endptr != ';')) {\n\t\t\treturn -5;\n\t\t}\n\n\t\tif ((ip_a >= 256) || (ip_b >= 256) || (ip_c >= 256) || (ip_d >= 256) ||\n\t\t (depth == 0) || (depth >= 32) ||\n\t\t\t (if_out >= APP_MAX_NIC_PORTS)) {\n\t\t\treturn -6;\n\t\t}\n\t\tip = (ip_a << 24) | (ip_b << 16) | (ip_c << 8) | ip_d;\n\n\t\tif (app.n_lpm_rules >= APP_MAX_LPM_RULES) {\n\t\t\treturn -7;\n\t\t}\n\t\tapp.lpm_rules[app.n_lpm_rules].ip = ip;\n\t\tapp.lpm_rules[app.n_lpm_rules].depth = (uint8_t) depth;\n\t\tapp.lpm_rules[app.n_lpm_rules].if_out = (uint8_t) if_out;\n\t\tapp.n_lpm_rules ++;\n\n\t\tp = strchr(p, ';');\n\t\tif (p == NULL) {\n\t\t\treturn -8;\n\t\t}\n\t\tp ++;\n\t}\n\n\tif (app.n_lpm_rules == 0) {\n\t\treturn -9;\n\t}\n\n\treturn 0;\n}\n\nstatic int\napp_check_lpm_table(void)\n{\n\tuint32_t rule;\n\n\t/* For each rule, check that the output I/F is enabled */\n\tfor (rule = 0; rule < app.n_lpm_rules; rule ++)\n\t{\n\t\tuint32_t port = app.lpm_rules[rule].if_out;\n\n\t\tif (app.nic_tx_port_mask[port] == 0) {\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\napp_check_every_rx_port_is_tx_enabled(void)\n{\n\tuint8_t port;\n\n\tfor (port = 0; port < APP_MAX_NIC_PORTS; port ++) {\n\t\tif ((app_get_nic_rx_queues_per_port(port) > 0) && (app.nic_tx_port_mask[port] == 0)) {\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n#ifndef APP_ARG_RSZ_CHARS\n#define APP_ARG_RSZ_CHARS 63\n#endif\n\nstatic int\nparse_arg_rsz(const char *arg)\n{\n\tif (strnlen(arg, APP_ARG_RSZ_CHARS + 1) == APP_ARG_RSZ_CHARS + 1) {\n\t\treturn -1;\n\t}\n\n\tif (str_to_unsigned_vals(arg, APP_ARG_RSZ_CHARS, ',', 4,\n\t\t\t&app.nic_rx_ring_size,\n\t\t\t&app.ring_rx_size,\n\t\t\t&app.ring_tx_size,\n\t\t\t&app.nic_tx_ring_size) != 4)\n\t\treturn -2;\n\n\n\tif ((app.nic_rx_ring_size == 0) ||\n\t\t(app.nic_tx_ring_size == 0) ||\n\t\t(app.ring_rx_size == 0) ||\n\t\t(app.ring_tx_size == 0)) {\n\t\treturn -3;\n\t}\n\n\treturn 0;\n}\n\n#ifndef APP_ARG_BSZ_CHARS\n#define APP_ARG_BSZ_CHARS 63\n#endif\n\nstatic int\nparse_arg_bsz(const char *arg)\n{\n\tconst char *p = arg, *p0;\n\tif (strnlen(arg, APP_ARG_BSZ_CHARS + 1) == APP_ARG_BSZ_CHARS + 1) {\n\t\treturn -1;\n\t}\n\n\tp0 = strchr(p++, ')');\n\tif ((p0 == NULL) ||\n\t (str_to_unsigned_vals(p, p0 - p, ',', 2, &app.burst_size_io_rx_read, &app.burst_size_io_rx_write) != 2)) {\n\t\treturn -2;\n\t}\n\n\tp = strchr(p0, '(');\n\tif (p == NULL) {\n\t\treturn -3;\n\t}\n\n\tp0 = strchr(p++, ')');\n\tif ((p0 == NULL) ||\n\t (str_to_unsigned_vals(p, p0 - p, ',', 2, &app.burst_size_worker_read, &app.burst_size_worker_write) != 2)) {\n\t\treturn -4;\n\t}\n\n\tp = strchr(p0, '(');\n\tif (p == NULL) {\n\t\treturn -5;\n\t}\n\n\tp0 = strchr(p++, ')');\n\tif ((p0 == NULL) ||\n\t (str_to_unsigned_vals(p, p0 - p, ',', 2, &app.burst_size_io_tx_read, &app.burst_size_io_tx_write) != 2)) {\n\t\treturn -6;\n\t}\n\n\tif ((app.burst_size_io_rx_read == 0) ||\n\t\t(app.burst_size_io_rx_write == 0) ||\n\t\t(app.burst_size_worker_read == 0) ||\n\t\t(app.burst_size_worker_write == 0) ||\n\t\t(app.burst_size_io_tx_read == 0) ||\n\t\t(app.burst_size_io_tx_write == 0)) {\n\t\treturn -7;\n\t}\n\n\tif ((app.burst_size_io_rx_read > APP_MBUF_ARRAY_SIZE) ||\n\t\t(app.burst_size_io_rx_write > APP_MBUF_ARRAY_SIZE) ||\n\t\t(app.burst_size_worker_read > APP_MBUF_ARRAY_SIZE) ||\n\t\t(app.burst_size_worker_write > APP_MBUF_ARRAY_SIZE) ||\n\t\t((2 * app.burst_size_io_tx_read) > APP_MBUF_ARRAY_SIZE) ||\n\t\t(app.burst_size_io_tx_write > APP_MBUF_ARRAY_SIZE)) {\n\t\treturn -8;\n\t}\n\n\treturn 0;\n}\n\n#ifndef APP_ARG_NUMERICAL_SIZE_CHARS\n#define APP_ARG_NUMERICAL_SIZE_CHARS 15\n#endif\n\nstatic int\nparse_arg_pos_lb(const char *arg)\n{\n\tuint32_t x;\n\tchar *endpt;\n\n\tif (strnlen(arg, APP_ARG_NUMERICAL_SIZE_CHARS + 1) == APP_ARG_NUMERICAL_SIZE_CHARS + 1) {\n\t\treturn -1;\n\t}\n\n\terrno = 0;\n\tx = strtoul(arg, &endpt, 10);\n\tif (errno != 0 || endpt == arg || *endpt != '\\0'){\n\t\treturn -2;\n\t}\n\n\tif (x >= 64) {\n\t\treturn -3;\n\t}\n\n\tapp.pos_lb = (uint8_t) x;\n\n\treturn 0;\n}\n\n/* Parse the argument given in the command line of the application */\nint\napp_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{\"rx\", 1, 0, 0},\n\t\t{\"tx\", 1, 0, 0},\n\t\t{\"w\", 1, 0, 0},\n\t\t{\"lpm\", 1, 0, 0},\n\t\t{\"rsz\", 1, 0, 0},\n\t\t{\"bsz\", 1, 0, 0},\n\t\t{\"pos-lb\", 1, 0, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\tuint32_t arg_w = 0;\n\tuint32_t arg_rx = 0;\n\tuint32_t arg_tx = 0;\n\tuint32_t arg_lpm = 0;\n\tuint32_t arg_rsz = 0;\n\tuint32_t arg_bsz = 0;\n\tuint32_t arg_pos_lb = 0;\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"\",\n\t\t\t\tlgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tif (!strcmp(lgopts[option_index].name, \"rx\")) {\n\t\t\t\targ_rx = 1;\n\t\t\t\tret = parse_arg_rx(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"Incorrect value for --rx argument (%d)\\n\", ret);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[option_index].name, \"tx\")) {\n\t\t\t\targ_tx = 1;\n\t\t\t\tret = parse_arg_tx(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"Incorrect value for --tx argument (%d)\\n\", ret);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[option_index].name, \"w\")) {\n\t\t\t\targ_w = 1;\n\t\t\t\tret = parse_arg_w(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"Incorrect value for --w argument (%d)\\n\", ret);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[option_index].name, \"lpm\")) {\n\t\t\t\targ_lpm = 1;\n\t\t\t\tret = parse_arg_lpm(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"Incorrect value for --lpm argument (%d)\\n\", ret);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[option_index].name, \"rsz\")) {\n\t\t\t\targ_rsz = 1;\n\t\t\t\tret = parse_arg_rsz(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"Incorrect value for --rsz argument (%d)\\n\", ret);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[option_index].name, \"bsz\")) {\n\t\t\t\targ_bsz = 1;\n\t\t\t\tret = parse_arg_bsz(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"Incorrect value for --bsz argument (%d)\\n\", ret);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (!strcmp(lgopts[option_index].name, \"pos-lb\")) {\n\t\t\t\targ_pos_lb = 1;\n\t\t\t\tret = parse_arg_pos_lb(optarg);\n\t\t\t\tif (ret) {\n\t\t\t\t\tprintf(\"Incorrect value for --pos-lb argument (%d)\\n\", ret);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* Check that all mandatory arguments are provided */\n\tif ((arg_rx == 0) || (arg_tx == 0) || (arg_w == 0) || (arg_lpm == 0)){\n\t\tprintf(\"Not all mandatory arguments are present\\n\");\n\t\treturn -1;\n\t}\n\n\t/* Assign default values for the optional arguments not provided */\n\tif (arg_rsz == 0) {\n\t\tapp.nic_rx_ring_size = APP_DEFAULT_NIC_RX_RING_SIZE;\n\t\tapp.nic_tx_ring_size = APP_DEFAULT_NIC_TX_RING_SIZE;\n\t\tapp.ring_rx_size = APP_DEFAULT_RING_RX_SIZE;\n\t\tapp.ring_tx_size = APP_DEFAULT_RING_TX_SIZE;\n\t}\n\n\tif (arg_bsz == 0) {\n\t\tapp.burst_size_io_rx_read = APP_DEFAULT_BURST_SIZE_IO_RX_READ;\n\t\tapp.burst_size_io_rx_write = APP_DEFAULT_BURST_SIZE_IO_RX_WRITE;\n\t\tapp.burst_size_io_tx_read = APP_DEFAULT_BURST_SIZE_IO_TX_READ;\n\t\tapp.burst_size_io_tx_write = APP_DEFAULT_BURST_SIZE_IO_TX_WRITE;\n\t\tapp.burst_size_worker_read = APP_DEFAULT_BURST_SIZE_WORKER_READ;\n\t\tapp.burst_size_worker_write = APP_DEFAULT_BURST_SIZE_WORKER_WRITE;\n\t}\n\n\tif (arg_pos_lb == 0) {\n\t\tapp.pos_lb = APP_DEFAULT_IO_RX_LB_POS;\n\t}\n\n\t/* Check cross-consistency of arguments */\n\tif ((ret = app_check_lpm_table()) < 0) {\n\t\tprintf(\"At least one LPM rule is inconsistent (%d)\\n\", ret);\n\t\treturn -1;\n\t}\n\tif (app_check_every_rx_port_is_tx_enabled() < 0) {\n\t\tprintf(\"On LPM lookup miss, packet is sent back on the input port.\\n\");\n\t\tprintf(\"At least one RX port is not enabled for TX.\\n\");\n\t\treturn -2;\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind - 1] = prgname;\n\n\tret = optind - 1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\nint\napp_get_nic_rx_queues_per_port(uint8_t port)\n{\n\tuint32_t i, count;\n\n\tif (port >= APP_MAX_NIC_PORTS) {\n\t\treturn -1;\n\t}\n\n\tcount = 0;\n\tfor (i = 0; i < APP_MAX_RX_QUEUES_PER_NIC_PORT; i ++) {\n\t\tif (app.nic_rx_queue_mask[port][i] == 1) {\n\t\t\tcount ++;\n\t\t}\n\t}\n\n\treturn count;\n}\n\nint\napp_get_lcore_for_nic_rx(uint8_t port, uint8_t queue, uint32_t *lcore_out)\n{\n\tuint32_t lcore;\n\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_io *lp = &app.lcore_params[lcore].io;\n\t\tuint32_t i;\n\n\t\tif (app.lcore_params[lcore].type != e_APP_LCORE_IO) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tconst size_t n_queues = RTE_MIN(lp->rx.n_nic_queues,\n\t\t RTE_DIM(lp->rx.nic_queues));\n\t\tfor (i = 0; i < n_queues; i ++) {\n\t\t\tif ((lp->rx.nic_queues[i].port == port) &&\n\t\t\t (lp->rx.nic_queues[i].queue == queue)) {\n\t\t\t\t*lcore_out = lcore;\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn -1;\n}\n\nint\napp_get_lcore_for_nic_tx(uint8_t port, uint32_t *lcore_out)\n{\n\tuint32_t lcore;\n\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_io *lp = &app.lcore_params[lcore].io;\n\t\tuint32_t i;\n\n\t\tif (app.lcore_params[lcore].type != e_APP_LCORE_IO) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tconst size_t n_ports = RTE_MIN(lp->tx.n_nic_ports,\n\t\t RTE_DIM(lp->tx.nic_ports));\n\t\tfor (i = 0; i < n_ports; i ++) {\n\t\t\tif (lp->tx.nic_ports[i] == port) {\n\t\t\t\t*lcore_out = lcore;\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn -1;\n}\n\nint\napp_is_socket_used(uint32_t socket)\n{\n\tuint32_t lcore;\n\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tif (app.lcore_params[lcore].type == e_APP_LCORE_DISABLED) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (socket == rte_lcore_to_socket_id(lcore)) {\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nuint32_t\napp_get_lcores_io_rx(void)\n{\n\tuint32_t lcore, count;\n\n\tcount = 0;\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_io *lp_io = &app.lcore_params[lcore].io;\n\n\t\tif ((app.lcore_params[lcore].type != e_APP_LCORE_IO) ||\n\t\t (lp_io->rx.n_nic_queues == 0)) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tcount ++;\n\t}\n\n\treturn count;\n}\n\nuint32_t\napp_get_lcores_worker(void)\n{\n\tuint32_t lcore, count;\n\n\tcount = 0;\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tif (app.lcore_params[lcore].type != e_APP_LCORE_WORKER) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tcount ++;\n\t}\n\n\tif (count > APP_MAX_WORKER_LCORES) {\n\t\trte_panic(\"Algorithmic error (too many worker lcores)\\n\");\n\t\treturn 0;\n\t}\n\n\treturn count;\n}\n\nvoid\napp_print_params(void)\n{\n\tunsigned port, queue, lcore, rule, i, j;\n\n\t/* Print NIC RX configuration */\n\tprintf(\"NIC RX ports: \");\n\tfor (port = 0; port < APP_MAX_NIC_PORTS; port ++) {\n\t\tuint32_t n_rx_queues = app_get_nic_rx_queues_per_port((uint8_t) port);\n\n\t\tif (n_rx_queues == 0) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tprintf(\"%u (\", port);\n\t\tfor (queue = 0; queue < APP_MAX_RX_QUEUES_PER_NIC_PORT; queue ++) {\n\t\t\tif (app.nic_rx_queue_mask[port][queue] == 1) {\n\t\t\t\tprintf(\"%u \", queue);\n\t\t\t}\n\t\t}\n\t\tprintf(\") \");\n\t}\n\tprintf(\";\\n\");\n\n\t/* Print I/O lcore RX params */\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_io *lp = &app.lcore_params[lcore].io;\n\n\t\tif ((app.lcore_params[lcore].type != e_APP_LCORE_IO) ||\n\t\t (lp->rx.n_nic_queues == 0)) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tprintf(\"I/O lcore %u (socket %u): \", lcore, rte_lcore_to_socket_id(lcore));\n\n\t\tprintf(\"RX ports \");\n\t\tfor (i = 0; i < lp->rx.n_nic_queues; i ++) {\n\t\t\tprintf(\"(%u, %u) \",\n\t\t\t\t(unsigned) lp->rx.nic_queues[i].port,\n\t\t\t\t(unsigned) lp->rx.nic_queues[i].queue);\n\t\t}\n\t\tprintf(\"; \");\n\n\t\tprintf(\"Output rings \");\n\t\tfor (i = 0; i < lp->rx.n_rings; i ++) {\n\t\t\tprintf(\"%p \", lp->rx.rings[i]);\n\t\t}\n\t\tprintf(\";\\n\");\n\t}\n\n\t/* Print worker lcore RX params */\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_worker *lp = &app.lcore_params[lcore].worker;\n\n\t\tif (app.lcore_params[lcore].type != e_APP_LCORE_WORKER) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tprintf(\"Worker lcore %u (socket %u) ID %u: \",\n\t\t\tlcore,\n\t\t\trte_lcore_to_socket_id(lcore),\n\t\t\t(unsigned)lp->worker_id);\n\n\t\tprintf(\"Input rings \");\n\t\tfor (i = 0; i < lp->n_rings_in; i ++) {\n\t\t\tprintf(\"%p \", lp->rings_in[i]);\n\t\t}\n\n\t\tprintf(\";\\n\");\n\t}\n\n\tprintf(\"\\n\");\n\n\t/* Print NIC TX configuration */\n\tprintf(\"NIC TX ports: \");\n\tfor (port = 0; port < APP_MAX_NIC_PORTS; port ++) {\n\t\tif (app.nic_tx_port_mask[port] == 1) {\n\t\t\tprintf(\"%u \", port);\n\t\t}\n\t}\n\tprintf(\";\\n\");\n\n\t/* Print I/O TX lcore params */\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_io *lp = &app.lcore_params[lcore].io;\n\t\tuint32_t n_workers = app_get_lcores_worker();\n\n\t\tif ((app.lcore_params[lcore].type != e_APP_LCORE_IO) ||\n\t\t (lp->tx.n_nic_ports == 0)) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tprintf(\"I/O lcore %u (socket %u): \", lcore, rte_lcore_to_socket_id(lcore));\n\n\t\tprintf(\"Input rings per TX port \");\n\t\tfor (i = 0; i < lp->tx.n_nic_ports; i ++) {\n\t\t\tport = lp->tx.nic_ports[i];\n\n\t\t\tprintf(\"%u (\", port);\n\t\t\tfor (j = 0; j < n_workers; j ++) {\n\t\t\t\tprintf(\"%p \", lp->tx.rings[port][j]);\n\t\t\t}\n\t\t\tprintf(\") \");\n\n\t\t}\n\n\t\tprintf(\";\\n\");\n\t}\n\n\t/* Print worker lcore TX params */\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_worker *lp = &app.lcore_params[lcore].worker;\n\n\t\tif (app.lcore_params[lcore].type != e_APP_LCORE_WORKER) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tprintf(\"Worker lcore %u (socket %u) ID %u: \\n\",\n\t\t\tlcore,\n\t\t\trte_lcore_to_socket_id(lcore),\n\t\t\t(unsigned)lp->worker_id);\n\n\t\tprintf(\"Output rings per TX port \");\n\t\tfor (port = 0; port < APP_MAX_NIC_PORTS; port ++) {\n\t\t\tif (lp->rings_out[port] != NULL) {\n\t\t\t\tprintf(\"%u (%p) \", port, lp->rings_out[port]);\n\t\t\t}\n\t\t}\n\n\t\tprintf(\";\\n\");\n\t}\n\n\t/* Print LPM rules */\n\tprintf(\"LPM rules: \\n\");\n\tfor (rule = 0; rule < app.n_lpm_rules; rule ++) {\n\t\tuint32_t ip = app.lpm_rules[rule].ip;\n\t\tuint8_t depth = app.lpm_rules[rule].depth;\n\t\tuint8_t if_out = app.lpm_rules[rule].if_out;\n\n\t\tprintf(\"\\t%u: %u.%u.%u.%u/%u => %u;\\n\",\n\t\t\trule,\n\t\t\t(unsigned) (ip & 0xFF000000) >> 24,\n\t\t\t(unsigned) (ip & 0x00FF0000) >> 16,\n\t\t\t(unsigned) (ip & 0x0000FF00) >> 8,\n\t\t\t(unsigned) ip & 0x000000FF,\n\t\t\t(unsigned) depth,\n\t\t\t(unsigned) if_out\n\t\t);\n\t}\n\n\t/* Rings */\n\tprintf(\"Ring sizes: NIC RX = %u; Worker in = %u; Worker out = %u; NIC TX = %u;\\n\",\n\t\t(unsigned) app.nic_rx_ring_size,\n\t\t(unsigned) app.ring_rx_size,\n\t\t(unsigned) app.ring_tx_size,\n\t\t(unsigned) app.nic_tx_ring_size);\n\n\t/* Bursts */\n\tprintf(\"Burst sizes: I/O RX (rd = %u, wr = %u); Worker (rd = %u, wr = %u); I/O TX (rd = %u, wr = %u)\\n\",\n\t\t(unsigned) app.burst_size_io_rx_read,\n\t\t(unsigned) app.burst_size_io_rx_write,\n\t\t(unsigned) app.burst_size_worker_read,\n\t\t(unsigned) app.burst_size_worker_write,\n\t\t(unsigned) app.burst_size_io_tx_read,\n\t\t(unsigned) app.burst_size_io_tx_write);\n}\n" }, { "path": "examples/load_balancer/init.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\nstatic struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.mq_mode\t= ETH_MQ_RX_RSS,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 1, /**< IP checksum offload enabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.rx_adv_conf = {\n\t\t.rss_conf = {\n\t\t\t.rss_key = NULL,\n\t\t\t.rss_hf = ETH_RSS_IP,\n\t\t},\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\nstatic void\napp_assign_worker_ids(void)\n{\n\tuint32_t lcore, worker_id;\n\n\t/* Assign ID for each worker */\n\tworker_id = 0;\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_worker *lp_worker = &app.lcore_params[lcore].worker;\n\n\t\tif (app.lcore_params[lcore].type != e_APP_LCORE_WORKER) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tlp_worker->worker_id = worker_id;\n\t\tworker_id ++;\n\t}\n}\n\nstatic void\napp_init_mbuf_pools(void)\n{\n\tunsigned socket, lcore;\n\n\t/* Init the buffer pools */\n\tfor (socket = 0; socket < APP_MAX_SOCKETS; socket ++) {\n\t\tchar name[32];\n\t\tif (app_is_socket_used(socket) == 0) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tsnprintf(name, sizeof(name), \"mbuf_pool_%u\", socket);\n\t\tprintf(\"Creating the mbuf pool for socket %u ...\\n\", socket);\n\t\tapp.pools[socket] = rte_pktmbuf_pool_create(\n\t\t\tname, APP_DEFAULT_MEMPOOL_BUFFERS,\n\t\t\tAPP_DEFAULT_MEMPOOL_CACHE_SIZE,\n\t\t\t0, APP_DEFAULT_MBUF_DATA_SIZE, socket);\n\t\tif (app.pools[socket] == NULL) {\n\t\t\trte_panic(\"Cannot create mbuf pool on socket %u\\n\", socket);\n\t\t}\n\t}\n\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tif (app.lcore_params[lcore].type == e_APP_LCORE_DISABLED) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tsocket = rte_lcore_to_socket_id(lcore);\n\t\tapp.lcore_params[lcore].pool = app.pools[socket];\n\t}\n}\n\nstatic void\napp_init_lpm_tables(void)\n{\n\tunsigned socket, lcore;\n\n\t/* Init the LPM tables */\n\tfor (socket = 0; socket < APP_MAX_SOCKETS; socket ++) {\n\t\tchar name[32];\n\t\tuint32_t rule;\n\n\t\tif (app_is_socket_used(socket) == 0) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tsnprintf(name, sizeof(name), \"lpm_table_%u\", socket);\n\t\tprintf(\"Creating the LPM table for socket %u ...\\n\", socket);\n\t\tapp.lpm_tables[socket] = rte_lpm_create(\n\t\t\tname,\n\t\t\tsocket,\n\t\t\tAPP_MAX_LPM_RULES,\n\t\t\t0);\n\t\tif (app.lpm_tables[socket] == NULL) {\n\t\t\trte_panic(\"Unable to create LPM table on socket %u\\n\", socket);\n\t\t}\n\n\t\tfor (rule = 0; rule < app.n_lpm_rules; rule ++) {\n\t\t\tint ret;\n\n\t\t\tret = rte_lpm_add(app.lpm_tables[socket],\n\t\t\t\tapp.lpm_rules[rule].ip,\n\t\t\t\tapp.lpm_rules[rule].depth,\n\t\t\t\tapp.lpm_rules[rule].if_out);\n\n\t\t\tif (ret < 0) {\n\t\t\t\trte_panic(\"Unable to add entry %u (%x/%u => %u) to the LPM table on socket %u (%d)\\n\",\n\t\t\t\t\t(unsigned) rule,\n\t\t\t\t\t(unsigned) app.lpm_rules[rule].ip,\n\t\t\t\t\t(unsigned) app.lpm_rules[rule].depth,\n\t\t\t\t\t(unsigned) app.lpm_rules[rule].if_out,\n\t\t\t\t\tsocket,\n\t\t\t\t\tret);\n\t\t\t}\n\t\t}\n\n\t}\n\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tif (app.lcore_params[lcore].type != e_APP_LCORE_WORKER) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tsocket = rte_lcore_to_socket_id(lcore);\n\t\tapp.lcore_params[lcore].worker.lpm_table = app.lpm_tables[socket];\n\t}\n}\n\nstatic void\napp_init_rings_rx(void)\n{\n\tunsigned lcore;\n\n\t/* Initialize the rings for the RX side */\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_io *lp_io = &app.lcore_params[lcore].io;\n\t\tunsigned socket_io, lcore_worker;\n\n\t\tif ((app.lcore_params[lcore].type != e_APP_LCORE_IO) ||\n\t\t (lp_io->rx.n_nic_queues == 0)) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tsocket_io = rte_lcore_to_socket_id(lcore);\n\n\t\tfor (lcore_worker = 0; lcore_worker < APP_MAX_LCORES; lcore_worker ++) {\n\t\t\tchar name[32];\n\t\t\tstruct app_lcore_params_worker *lp_worker = &app.lcore_params[lcore_worker].worker;\n\t\t\tstruct rte_ring *ring = NULL;\n\n\t\t\tif (app.lcore_params[lcore_worker].type != e_APP_LCORE_WORKER) {\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tprintf(\"Creating ring to connect I/O lcore %u (socket %u) with worker lcore %u ...\\n\",\n\t\t\t\tlcore,\n\t\t\t\tsocket_io,\n\t\t\t\tlcore_worker);\n\t\t\tsnprintf(name, sizeof(name), \"app_ring_rx_s%u_io%u_w%u\",\n\t\t\t\tsocket_io,\n\t\t\t\tlcore,\n\t\t\t\tlcore_worker);\n\t\t\tring = rte_ring_create(\n\t\t\t\tname,\n\t\t\t\tapp.ring_rx_size,\n\t\t\t\tsocket_io,\n\t\t\t\tRING_F_SP_ENQ | RING_F_SC_DEQ);\n\t\t\tif (ring == NULL) {\n\t\t\t\trte_panic(\"Cannot create ring to connect I/O core %u with worker core %u\\n\",\n\t\t\t\t\tlcore,\n\t\t\t\t\tlcore_worker);\n\t\t\t}\n\n\t\t\tlp_io->rx.rings[lp_io->rx.n_rings] = ring;\n\t\t\tlp_io->rx.n_rings ++;\n\n\t\t\tlp_worker->rings_in[lp_worker->n_rings_in] = ring;\n\t\t\tlp_worker->n_rings_in ++;\n\t\t}\n\t}\n\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_io *lp_io = &app.lcore_params[lcore].io;\n\n\t\tif ((app.lcore_params[lcore].type != e_APP_LCORE_IO) ||\n\t\t (lp_io->rx.n_nic_queues == 0)) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (lp_io->rx.n_rings != app_get_lcores_worker()) {\n\t\t\trte_panic(\"Algorithmic error (I/O RX rings)\\n\");\n\t\t}\n\t}\n\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_worker *lp_worker = &app.lcore_params[lcore].worker;\n\n\t\tif (app.lcore_params[lcore].type != e_APP_LCORE_WORKER) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (lp_worker->n_rings_in != app_get_lcores_io_rx()) {\n\t\t\trte_panic(\"Algorithmic error (worker input rings)\\n\");\n\t\t}\n\t}\n}\n\nstatic void\napp_init_rings_tx(void)\n{\n\tunsigned lcore;\n\n\t/* Initialize the rings for the TX side */\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_worker *lp_worker = &app.lcore_params[lcore].worker;\n\t\tunsigned port;\n\n\t\tif (app.lcore_params[lcore].type != e_APP_LCORE_WORKER) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tfor (port = 0; port < APP_MAX_NIC_PORTS; port ++) {\n\t\t\tchar name[32];\n\t\t\tstruct app_lcore_params_io *lp_io = NULL;\n\t\t\tstruct rte_ring *ring;\n\t\t\tuint32_t socket_io, lcore_io;\n\n\t\t\tif (app.nic_tx_port_mask[port] == 0) {\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (app_get_lcore_for_nic_tx((uint8_t) port, &lcore_io) < 0) {\n\t\t\t\trte_panic(\"Algorithmic error (no I/O core to handle TX of port %u)\\n\",\n\t\t\t\t\tport);\n\t\t\t}\n\n\t\t\tlp_io = &app.lcore_params[lcore_io].io;\n\t\t\tsocket_io = rte_lcore_to_socket_id(lcore_io);\n\n\t\t\tprintf(\"Creating ring to connect worker lcore %u with TX port %u (through I/O lcore %u) (socket %u) ...\\n\",\n\t\t\t\tlcore, port, (unsigned)lcore_io, (unsigned)socket_io);\n\t\t\tsnprintf(name, sizeof(name), \"app_ring_tx_s%u_w%u_p%u\", socket_io, lcore, port);\n\t\t\tring = rte_ring_create(\n\t\t\t\tname,\n\t\t\t\tapp.ring_tx_size,\n\t\t\t\tsocket_io,\n\t\t\t\tRING_F_SP_ENQ | RING_F_SC_DEQ);\n\t\t\tif (ring == NULL) {\n\t\t\t\trte_panic(\"Cannot create ring to connect worker core %u with TX port %u\\n\",\n\t\t\t\t\tlcore,\n\t\t\t\t\tport);\n\t\t\t}\n\n\t\t\tlp_worker->rings_out[port] = ring;\n\t\t\tlp_io->tx.rings[port][lp_worker->worker_id] = ring;\n\t\t}\n\t}\n\n\tfor (lcore = 0; lcore < APP_MAX_LCORES; lcore ++) {\n\t\tstruct app_lcore_params_io *lp_io = &app.lcore_params[lcore].io;\n\t\tunsigned i;\n\n\t\tif ((app.lcore_params[lcore].type != e_APP_LCORE_IO) ||\n\t\t (lp_io->tx.n_nic_ports == 0)) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tfor (i = 0; i < lp_io->tx.n_nic_ports; i ++){\n\t\t\tunsigned port, j;\n\n\t\t\tport = lp_io->tx.nic_ports[i];\n\t\t\tfor (j = 0; j < app_get_lcores_worker(); j ++) {\n\t\t\t\tif (lp_io->tx.rings[port][j] == NULL) {\n\t\t\t\t\trte_panic(\"Algorithmic error (I/O TX rings)\\n\");\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\tuint32_t n_rx_queues, n_tx_queues;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tn_rx_queues = app_get_nic_rx_queues_per_port(portid);\n\t\t\tn_tx_queues = app.nic_tx_port_mask[portid];\n\t\t\tif ((n_rx_queues == 0) && (n_tx_queues == 0))\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\nstatic void\napp_init_nics(void)\n{\n\tunsigned socket;\n\tuint32_t lcore;\n\tuint8_t port, queue;\n\tint ret;\n\tuint32_t n_rx_queues, n_tx_queues;\n\n\t/* Init NIC ports and queues, then start the ports */\n\tfor (port = 0; port < APP_MAX_NIC_PORTS; port ++) {\n\t\tstruct rte_mempool *pool;\n\n\t\tn_rx_queues = app_get_nic_rx_queues_per_port(port);\n\t\tn_tx_queues = app.nic_tx_port_mask[port];\n\n\t\tif ((n_rx_queues == 0) && (n_tx_queues == 0)) {\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Init port */\n\t\tprintf(\"Initializing NIC port %u ...\\n\", (unsigned) port);\n\t\tret = rte_eth_dev_configure(\n\t\t\tport,\n\t\t\t(uint8_t) n_rx_queues,\n\t\t\t(uint8_t) n_tx_queues,\n\t\t\t&port_conf);\n\t\tif (ret < 0) {\n\t\t\trte_panic(\"Cannot init NIC port %u (%d)\\n\", (unsigned) port, ret);\n\t\t}\n\t\trte_eth_promiscuous_enable(port);\n\n\t\t/* Init RX queues */\n\t\tfor (queue = 0; queue < APP_MAX_RX_QUEUES_PER_NIC_PORT; queue ++) {\n\t\t\tif (app.nic_rx_queue_mask[port][queue] == 0) {\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tapp_get_lcore_for_nic_rx(port, queue, &lcore);\n\t\t\tsocket = rte_lcore_to_socket_id(lcore);\n\t\t\tpool = app.lcore_params[lcore].pool;\n\n\t\t\tprintf(\"Initializing NIC port %u RX queue %u ...\\n\",\n\t\t\t\t(unsigned) port,\n\t\t\t\t(unsigned) queue);\n\t\t\tret = rte_eth_rx_queue_setup(\n\t\t\t\tport,\n\t\t\t\tqueue,\n\t\t\t\t(uint16_t) app.nic_rx_ring_size,\n\t\t\t\tsocket,\n\t\t\t\tNULL,\n\t\t\t\tpool);\n\t\t\tif (ret < 0) {\n\t\t\t\trte_panic(\"Cannot init RX queue %u for port %u (%d)\\n\",\n\t\t\t\t\t(unsigned) queue,\n\t\t\t\t\t(unsigned) port,\n\t\t\t\t\tret);\n\t\t\t}\n\t\t}\n\n\t\t/* Init TX queues */\n\t\tif (app.nic_tx_port_mask[port] == 1) {\n\t\t\tapp_get_lcore_for_nic_tx(port, &lcore);\n\t\t\tsocket = rte_lcore_to_socket_id(lcore);\n\t\t\tprintf(\"Initializing NIC port %u TX queue 0 ...\\n\",\n\t\t\t\t(unsigned) port);\n\t\t\tret = rte_eth_tx_queue_setup(\n\t\t\t\tport,\n\t\t\t\t0,\n\t\t\t\t(uint16_t) app.nic_tx_ring_size,\n\t\t\t\tsocket,\n\t\t\t\tNULL);\n\t\t\tif (ret < 0) {\n\t\t\t\trte_panic(\"Cannot init TX queue 0 for port %d (%d)\\n\",\n\t\t\t\t\tport,\n\t\t\t\t\tret);\n\t\t\t}\n\t\t}\n\n\t\t/* Start port */\n\t\tret = rte_eth_dev_start(port);\n\t\tif (ret < 0) {\n\t\t\trte_panic(\"Cannot start port %d (%d)\\n\", port, ret);\n\t\t}\n\t}\n\n\tcheck_all_ports_link_status(APP_MAX_NIC_PORTS, (~0x0));\n}\n\nvoid\napp_init(void)\n{\n\tapp_assign_worker_ids();\n\tapp_init_mbuf_pools();\n\tapp_init_lpm_tables();\n\tapp_init_rings_rx();\n\tapp_init_rings_tx();\n\tapp_init_nics();\n\n\tprintf(\"Initialization completed.\\n\");\n}\n" }, { "path": "examples/load_balancer/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\nint\nmain(int argc, char **argv)\n{\n\tuint32_t lcore;\n\tint ret;\n\n\t/* Init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\treturn -1;\n\targc -= ret;\n\targv += ret;\n\n\t/* Parse application arguments (after the EAL ones) */\n\tret = app_parse_args(argc, argv);\n\tif (ret < 0) {\n\t\tapp_print_usage();\n\t\treturn -1;\n\t}\n\n\t/* Init */\n\tapp_init();\n\tapp_print_params();\n\n\t/* Launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(app_lcore_main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\tif (rte_eal_wait_lcore(lcore) < 0) {\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/load_balancer/main.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _MAIN_H_\n#define _MAIN_H_\n\n/* Logical cores */\n#ifndef APP_MAX_SOCKETS\n#define APP_MAX_SOCKETS 2\n#endif\n\n#ifndef APP_MAX_LCORES\n#define APP_MAX_LCORES RTE_MAX_LCORE\n#endif\n\n#ifndef APP_MAX_NIC_PORTS\n#define APP_MAX_NIC_PORTS RTE_MAX_ETHPORTS\n#endif\n\n#ifndef APP_MAX_RX_QUEUES_PER_NIC_PORT\n#define APP_MAX_RX_QUEUES_PER_NIC_PORT 128\n#endif\n\n#ifndef APP_MAX_TX_QUEUES_PER_NIC_PORT\n#define APP_MAX_TX_QUEUES_PER_NIC_PORT 128\n#endif\n\n#ifndef APP_MAX_IO_LCORES\n#define APP_MAX_IO_LCORES 16\n#endif\n#if (APP_MAX_IO_LCORES > APP_MAX_LCORES)\n#error \"APP_MAX_IO_LCORES is too big\"\n#endif\n\n#ifndef APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE\n#define APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE 16\n#endif\n\n#ifndef APP_MAX_NIC_TX_PORTS_PER_IO_LCORE\n#define APP_MAX_NIC_TX_PORTS_PER_IO_LCORE 16\n#endif\n#if (APP_MAX_NIC_TX_PORTS_PER_IO_LCORE > APP_MAX_NIC_PORTS)\n#error \"APP_MAX_NIC_TX_PORTS_PER_IO_LCORE too big\"\n#endif\n\n#ifndef APP_MAX_WORKER_LCORES\n#define APP_MAX_WORKER_LCORES 16\n#endif\n#if (APP_MAX_WORKER_LCORES > APP_MAX_LCORES)\n#error \"APP_MAX_WORKER_LCORES is too big\"\n#endif\n\n\n/* Mempools */\n#ifndef APP_DEFAULT_MBUF_DATA_SIZE\n#define APP_DEFAULT_MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE\n#endif\n\n#ifndef APP_DEFAULT_MEMPOOL_BUFFERS\n#define APP_DEFAULT_MEMPOOL_BUFFERS 8192 * 4\n#endif\n\n#ifndef APP_DEFAULT_MEMPOOL_CACHE_SIZE\n#define APP_DEFAULT_MEMPOOL_CACHE_SIZE 256\n#endif\n\n/* LPM Tables */\n#ifndef APP_MAX_LPM_RULES\n#define APP_MAX_LPM_RULES 1024\n#endif\n\n/* NIC RX */\n#ifndef APP_DEFAULT_NIC_RX_RING_SIZE\n#define APP_DEFAULT_NIC_RX_RING_SIZE 1024\n#endif\n\n/*\n * RX and TX Prefetch, Host, and Write-back threshold values should be\n * carefully set for optimal performance. Consult the network\n * controller's datasheet and supporting DPDK documentation for guidance\n * on how these parameters should be set.\n */\n#ifndef APP_DEFAULT_NIC_RX_PTHRESH\n#define APP_DEFAULT_NIC_RX_PTHRESH 8\n#endif\n\n#ifndef APP_DEFAULT_NIC_RX_HTHRESH\n#define APP_DEFAULT_NIC_RX_HTHRESH 8\n#endif\n\n#ifndef APP_DEFAULT_NIC_RX_WTHRESH\n#define APP_DEFAULT_NIC_RX_WTHRESH 4\n#endif\n\n#ifndef APP_DEFAULT_NIC_RX_FREE_THRESH\n#define APP_DEFAULT_NIC_RX_FREE_THRESH 64\n#endif\n\n#ifndef APP_DEFAULT_NIC_RX_DROP_EN\n#define APP_DEFAULT_NIC_RX_DROP_EN 0\n#endif\n\n/* NIC TX */\n#ifndef APP_DEFAULT_NIC_TX_RING_SIZE\n#define APP_DEFAULT_NIC_TX_RING_SIZE 1024\n#endif\n\n/*\n * These default values are optimized for use with the Intel(R) 82599 10 GbE\n * Controller and the DPDK ixgbe PMD. Consider using other values for other\n * network controllers and/or network drivers.\n */\n#ifndef APP_DEFAULT_NIC_TX_PTHRESH\n#define APP_DEFAULT_NIC_TX_PTHRESH 36\n#endif\n\n#ifndef APP_DEFAULT_NIC_TX_HTHRESH\n#define APP_DEFAULT_NIC_TX_HTHRESH 0\n#endif\n\n#ifndef APP_DEFAULT_NIC_TX_WTHRESH\n#define APP_DEFAULT_NIC_TX_WTHRESH 0\n#endif\n\n#ifndef APP_DEFAULT_NIC_TX_FREE_THRESH\n#define APP_DEFAULT_NIC_TX_FREE_THRESH 0\n#endif\n\n#ifndef APP_DEFAULT_NIC_TX_RS_THRESH\n#define APP_DEFAULT_NIC_TX_RS_THRESH 0\n#endif\n\n/* Software Rings */\n#ifndef APP_DEFAULT_RING_RX_SIZE\n#define APP_DEFAULT_RING_RX_SIZE 1024\n#endif\n\n#ifndef APP_DEFAULT_RING_TX_SIZE\n#define APP_DEFAULT_RING_TX_SIZE 1024\n#endif\n\n/* Bursts */\n#ifndef APP_MBUF_ARRAY_SIZE\n#define APP_MBUF_ARRAY_SIZE 512\n#endif\n\n#ifndef APP_DEFAULT_BURST_SIZE_IO_RX_READ\n#define APP_DEFAULT_BURST_SIZE_IO_RX_READ 144\n#endif\n#if (APP_DEFAULT_BURST_SIZE_IO_RX_READ > APP_MBUF_ARRAY_SIZE)\n#error \"APP_DEFAULT_BURST_SIZE_IO_RX_READ is too big\"\n#endif\n\n#ifndef APP_DEFAULT_BURST_SIZE_IO_RX_WRITE\n#define APP_DEFAULT_BURST_SIZE_IO_RX_WRITE 144\n#endif\n#if (APP_DEFAULT_BURST_SIZE_IO_RX_WRITE > APP_MBUF_ARRAY_SIZE)\n#error \"APP_DEFAULT_BURST_SIZE_IO_RX_WRITE is too big\"\n#endif\n\n#ifndef APP_DEFAULT_BURST_SIZE_IO_TX_READ\n#define APP_DEFAULT_BURST_SIZE_IO_TX_READ 144\n#endif\n#if (APP_DEFAULT_BURST_SIZE_IO_TX_READ > APP_MBUF_ARRAY_SIZE)\n#error \"APP_DEFAULT_BURST_SIZE_IO_TX_READ is too big\"\n#endif\n\n#ifndef APP_DEFAULT_BURST_SIZE_IO_TX_WRITE\n#define APP_DEFAULT_BURST_SIZE_IO_TX_WRITE 144\n#endif\n#if (APP_DEFAULT_BURST_SIZE_IO_TX_WRITE > APP_MBUF_ARRAY_SIZE)\n#error \"APP_DEFAULT_BURST_SIZE_IO_TX_WRITE is too big\"\n#endif\n\n#ifndef APP_DEFAULT_BURST_SIZE_WORKER_READ\n#define APP_DEFAULT_BURST_SIZE_WORKER_READ 144\n#endif\n#if ((2 * APP_DEFAULT_BURST_SIZE_WORKER_READ) > APP_MBUF_ARRAY_SIZE)\n#error \"APP_DEFAULT_BURST_SIZE_WORKER_READ is too big\"\n#endif\n\n#ifndef APP_DEFAULT_BURST_SIZE_WORKER_WRITE\n#define APP_DEFAULT_BURST_SIZE_WORKER_WRITE 144\n#endif\n#if (APP_DEFAULT_BURST_SIZE_WORKER_WRITE > APP_MBUF_ARRAY_SIZE)\n#error \"APP_DEFAULT_BURST_SIZE_WORKER_WRITE is too big\"\n#endif\n\n/* Load balancing logic */\n#ifndef APP_DEFAULT_IO_RX_LB_POS\n#define APP_DEFAULT_IO_RX_LB_POS 29\n#endif\n#if (APP_DEFAULT_IO_RX_LB_POS >= 64)\n#error \"APP_DEFAULT_IO_RX_LB_POS is too big\"\n#endif\n\nstruct app_mbuf_array {\n\tstruct rte_mbuf *array[APP_MBUF_ARRAY_SIZE];\n\tuint32_t n_mbufs;\n};\n\nenum app_lcore_type {\n\te_APP_LCORE_DISABLED = 0,\n\te_APP_LCORE_IO,\n\te_APP_LCORE_WORKER\n};\n\nstruct app_lcore_params_io {\n\t/* I/O RX */\n\tstruct {\n\t\t/* NIC */\n\t\tstruct {\n\t\t\tuint8_t port;\n\t\t\tuint8_t queue;\n\t\t} nic_queues[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];\n\t\tuint32_t n_nic_queues;\n\n\t\t/* Rings */\n\t\tstruct rte_ring *rings[APP_MAX_WORKER_LCORES];\n\t\tuint32_t n_rings;\n\n\t\t/* Internal buffers */\n\t\tstruct app_mbuf_array mbuf_in;\n\t\tstruct app_mbuf_array mbuf_out[APP_MAX_WORKER_LCORES];\n\t\tuint8_t mbuf_out_flush[APP_MAX_WORKER_LCORES];\n\n\t\t/* Stats */\n\t\tuint32_t nic_queues_count[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];\n\t\tuint32_t nic_queues_iters[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];\n\t\tuint32_t rings_count[APP_MAX_WORKER_LCORES];\n\t\tuint32_t rings_iters[APP_MAX_WORKER_LCORES];\n\t} rx;\n\n\t/* I/O TX */\n\tstruct {\n\t\t/* Rings */\n\t\tstruct rte_ring *rings[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];\n\n\t\t/* NIC */\n\t\tuint8_t nic_ports[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];\n\t\tuint32_t n_nic_ports;\n\n\t\t/* Internal buffers */\n\t\tstruct app_mbuf_array mbuf_out[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];\n\t\tuint8_t mbuf_out_flush[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];\n\n\t\t/* Stats */\n\t\tuint32_t rings_count[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];\n\t\tuint32_t rings_iters[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];\n\t\tuint32_t nic_ports_count[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];\n\t\tuint32_t nic_ports_iters[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];\n\t} tx;\n};\n\nstruct app_lcore_params_worker {\n\t/* Rings */\n\tstruct rte_ring *rings_in[APP_MAX_IO_LCORES];\n\tuint32_t n_rings_in;\n\tstruct rte_ring *rings_out[APP_MAX_NIC_PORTS];\n\n\t/* LPM table */\n\tstruct rte_lpm *lpm_table;\n\tuint32_t worker_id;\n\n\t/* Internal buffers */\n\tstruct app_mbuf_array mbuf_in;\n\tstruct app_mbuf_array mbuf_out[APP_MAX_NIC_PORTS];\n\tuint8_t mbuf_out_flush[APP_MAX_NIC_PORTS];\n\n\t/* Stats */\n\tuint32_t rings_in_count[APP_MAX_IO_LCORES];\n\tuint32_t rings_in_iters[APP_MAX_IO_LCORES];\n\tuint32_t rings_out_count[APP_MAX_NIC_PORTS];\n\tuint32_t rings_out_iters[APP_MAX_NIC_PORTS];\n};\n\nstruct app_lcore_params {\n\tunion {\n\t\tstruct app_lcore_params_io io;\n\t\tstruct app_lcore_params_worker worker;\n\t};\n\tenum app_lcore_type type;\n\tstruct rte_mempool *pool;\n} __rte_cache_aligned;\n\nstruct app_lpm_rule {\n\tuint32_t ip;\n\tuint8_t depth;\n\tuint8_t if_out;\n};\n\nstruct app_params {\n\t/* lcore */\n\tstruct app_lcore_params lcore_params[APP_MAX_LCORES];\n\n\t/* NIC */\n\tuint8_t nic_rx_queue_mask[APP_MAX_NIC_PORTS][APP_MAX_RX_QUEUES_PER_NIC_PORT];\n\tuint8_t nic_tx_port_mask[APP_MAX_NIC_PORTS];\n\n\t/* mbuf pools */\n\tstruct rte_mempool *pools[APP_MAX_SOCKETS];\n\n\t/* LPM tables */\n\tstruct rte_lpm *lpm_tables[APP_MAX_SOCKETS];\n\tstruct app_lpm_rule lpm_rules[APP_MAX_LPM_RULES];\n\tuint32_t n_lpm_rules;\n\n\t/* rings */\n\tuint32_t nic_rx_ring_size;\n\tuint32_t nic_tx_ring_size;\n\tuint32_t ring_rx_size;\n\tuint32_t ring_tx_size;\n\n\t/* burst size */\n\tuint32_t burst_size_io_rx_read;\n\tuint32_t burst_size_io_rx_write;\n\tuint32_t burst_size_io_tx_read;\n\tuint32_t burst_size_io_tx_write;\n\tuint32_t burst_size_worker_read;\n\tuint32_t burst_size_worker_write;\n\n\t/* load balancing */\n\tuint8_t pos_lb;\n} __rte_cache_aligned;\n\nextern struct app_params app;\n\nint app_parse_args(int argc, char **argv);\nvoid app_print_usage(void);\nvoid app_init(void);\nint app_lcore_main_loop(void *arg);\n\nint app_get_nic_rx_queues_per_port(uint8_t port);\nint app_get_lcore_for_nic_rx(uint8_t port, uint8_t queue, uint32_t *lcore_out);\nint app_get_lcore_for_nic_tx(uint8_t port, uint32_t *lcore_out);\nint app_is_socket_used(uint32_t socket);\nuint32_t app_get_lcores_io_rx(void);\nuint32_t app_get_lcores_worker(void);\nvoid app_print_params(void);\n\n#endif /* _MAIN_H_ */\n" }, { "path": "examples/load_balancer/runtime.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\n#ifndef APP_LCORE_IO_FLUSH\n#define APP_LCORE_IO_FLUSH 1000000\n#endif\n\n#ifndef APP_LCORE_WORKER_FLUSH\n#define APP_LCORE_WORKER_FLUSH 1000000\n#endif\n\n#ifndef APP_STATS\n#define APP_STATS 1000000\n#endif\n\n#define APP_IO_RX_DROP_ALL_PACKETS 0\n#define APP_WORKER_DROP_ALL_PACKETS 0\n#define APP_IO_TX_DROP_ALL_PACKETS 0\n\n#ifndef APP_IO_RX_PREFETCH_ENABLE\n#define APP_IO_RX_PREFETCH_ENABLE 1\n#endif\n\n#ifndef APP_WORKER_PREFETCH_ENABLE\n#define APP_WORKER_PREFETCH_ENABLE 1\n#endif\n\n#ifndef APP_IO_TX_PREFETCH_ENABLE\n#define APP_IO_TX_PREFETCH_ENABLE 1\n#endif\n\n#if APP_IO_RX_PREFETCH_ENABLE\n#define APP_IO_RX_PREFETCH0(p) rte_prefetch0(p)\n#define APP_IO_RX_PREFETCH1(p) rte_prefetch1(p)\n#else\n#define APP_IO_RX_PREFETCH0(p)\n#define APP_IO_RX_PREFETCH1(p)\n#endif\n\n#if APP_WORKER_PREFETCH_ENABLE\n#define APP_WORKER_PREFETCH0(p) rte_prefetch0(p)\n#define APP_WORKER_PREFETCH1(p) rte_prefetch1(p)\n#else\n#define APP_WORKER_PREFETCH0(p)\n#define APP_WORKER_PREFETCH1(p)\n#endif\n\n#if APP_IO_TX_PREFETCH_ENABLE\n#define APP_IO_TX_PREFETCH0(p) rte_prefetch0(p)\n#define APP_IO_TX_PREFETCH1(p) rte_prefetch1(p)\n#else\n#define APP_IO_TX_PREFETCH0(p)\n#define APP_IO_TX_PREFETCH1(p)\n#endif\n\nstatic inline void\napp_lcore_io_rx_buffer_to_send (\n\tstruct app_lcore_params_io *lp,\n\tuint32_t worker,\n\tstruct rte_mbuf *mbuf,\n\tuint32_t bsz)\n{\n\tuint32_t pos;\n\tint ret;\n\n\tpos = lp->rx.mbuf_out[worker].n_mbufs;\n\tlp->rx.mbuf_out[worker].array[pos ++] = mbuf;\n\tif (likely(pos < bsz)) {\n\t\tlp->rx.mbuf_out[worker].n_mbufs = pos;\n\t\treturn;\n\t}\n\n\tret = rte_ring_sp_enqueue_bulk(\n\t\tlp->rx.rings[worker],\n\t\t(void **) lp->rx.mbuf_out[worker].array,\n\t\tbsz);\n\n\tif (unlikely(ret == -ENOBUFS)) {\n\t\tuint32_t k;\n\t\tfor (k = 0; k < bsz; k ++) {\n\t\t\tstruct rte_mbuf *m = lp->rx.mbuf_out[worker].array[k];\n\t\t\trte_pktmbuf_free(m);\n\t\t}\n\t}\n\n\tlp->rx.mbuf_out[worker].n_mbufs = 0;\n\tlp->rx.mbuf_out_flush[worker] = 0;\n\n#if APP_STATS\n\tlp->rx.rings_iters[worker] ++;\n\tif (likely(ret == 0)) {\n\t\tlp->rx.rings_count[worker] ++;\n\t}\n\tif (unlikely(lp->rx.rings_iters[worker] == APP_STATS)) {\n\t\tunsigned lcore = rte_lcore_id();\n\n\t\tprintf(\"\\tI/O RX %u out (worker %u): enq success rate = %.2f\\n\",\n\t\t\tlcore,\n\t\t\t(unsigned)worker,\n\t\t\t((double) lp->rx.rings_count[worker]) / ((double) lp->rx.rings_iters[worker]));\n\t\tlp->rx.rings_iters[worker] = 0;\n\t\tlp->rx.rings_count[worker] = 0;\n\t}\n#endif\n}\n\nstatic inline void\napp_lcore_io_rx(\n\tstruct app_lcore_params_io *lp,\n\tuint32_t n_workers,\n\tuint32_t bsz_rd,\n\tuint32_t bsz_wr,\n\tuint8_t pos_lb)\n{\n\tstruct rte_mbuf *mbuf_1_0, *mbuf_1_1, *mbuf_2_0, *mbuf_2_1;\n\tuint8_t *data_1_0, *data_1_1 = NULL;\n\tuint32_t i;\n\n\tfor (i = 0; i < lp->rx.n_nic_queues; i ++) {\n\t\tuint8_t port = lp->rx.nic_queues[i].port;\n\t\tuint8_t queue = lp->rx.nic_queues[i].queue;\n\t\tuint32_t n_mbufs, j;\n\n\t\tn_mbufs = rte_eth_rx_burst(\n\t\t\tport,\n\t\t\tqueue,\n\t\t\tlp->rx.mbuf_in.array,\n\t\t\t(uint16_t) bsz_rd);\n\n\t\tif (unlikely(n_mbufs == 0)) {\n\t\t\tcontinue;\n\t\t}\n\n#if APP_STATS\n\t\tlp->rx.nic_queues_iters[i] ++;\n\t\tlp->rx.nic_queues_count[i] += n_mbufs;\n\t\tif (unlikely(lp->rx.nic_queues_iters[i] == APP_STATS)) {\n\t\t\tstruct rte_eth_stats stats;\n\t\t\tunsigned lcore = rte_lcore_id();\n\n\t\t\trte_eth_stats_get(port, &stats);\n\n\t\t\tprintf(\"I/O RX %u in (NIC port %u): NIC drop ratio = %.2f avg burst size = %.2f\\n\",\n\t\t\t\tlcore,\n\t\t\t\t(unsigned) port,\n\t\t\t\t(double) stats.imissed / (double) (stats.imissed + stats.ipackets),\n\t\t\t\t((double) lp->rx.nic_queues_count[i]) / ((double) lp->rx.nic_queues_iters[i]));\n\t\t\tlp->rx.nic_queues_iters[i] = 0;\n\t\t\tlp->rx.nic_queues_count[i] = 0;\n\t\t}\n#endif\n\n#if APP_IO_RX_DROP_ALL_PACKETS\n\t\tfor (j = 0; j < n_mbufs; j ++) {\n\t\t\tstruct rte_mbuf *pkt = lp->rx.mbuf_in.array[j];\n\t\t\trte_pktmbuf_free(pkt);\n\t\t}\n\n\t\tcontinue;\n#endif\n\n\t\tmbuf_1_0 = lp->rx.mbuf_in.array[0];\n\t\tmbuf_1_1 = lp->rx.mbuf_in.array[1];\n\t\tdata_1_0 = rte_pktmbuf_mtod(mbuf_1_0, uint8_t *);\n\t\tif (likely(n_mbufs > 1)) {\n\t\t\tdata_1_1 = rte_pktmbuf_mtod(mbuf_1_1, uint8_t *);\n\t\t}\n\n\t\tmbuf_2_0 = lp->rx.mbuf_in.array[2];\n\t\tmbuf_2_1 = lp->rx.mbuf_in.array[3];\n\t\tAPP_IO_RX_PREFETCH0(mbuf_2_0);\n\t\tAPP_IO_RX_PREFETCH0(mbuf_2_1);\n\n\t\tfor (j = 0; j + 3 < n_mbufs; j += 2) {\n\t\t\tstruct rte_mbuf *mbuf_0_0, *mbuf_0_1;\n\t\t\tuint8_t *data_0_0, *data_0_1;\n\t\t\tuint32_t worker_0, worker_1;\n\n\t\t\tmbuf_0_0 = mbuf_1_0;\n\t\t\tmbuf_0_1 = mbuf_1_1;\n\t\t\tdata_0_0 = data_1_0;\n\t\t\tdata_0_1 = data_1_1;\n\n\t\t\tmbuf_1_0 = mbuf_2_0;\n\t\t\tmbuf_1_1 = mbuf_2_1;\n\t\t\tdata_1_0 = rte_pktmbuf_mtod(mbuf_2_0, uint8_t *);\n\t\t\tdata_1_1 = rte_pktmbuf_mtod(mbuf_2_1, uint8_t *);\n\t\t\tAPP_IO_RX_PREFETCH0(data_1_0);\n\t\t\tAPP_IO_RX_PREFETCH0(data_1_1);\n\n\t\t\tmbuf_2_0 = lp->rx.mbuf_in.array[j+4];\n\t\t\tmbuf_2_1 = lp->rx.mbuf_in.array[j+5];\n\t\t\tAPP_IO_RX_PREFETCH0(mbuf_2_0);\n\t\t\tAPP_IO_RX_PREFETCH0(mbuf_2_1);\n\n\t\t\tworker_0 = data_0_0[pos_lb] & (n_workers - 1);\n\t\t\tworker_1 = data_0_1[pos_lb] & (n_workers - 1);\n\n\t\t\tapp_lcore_io_rx_buffer_to_send(lp, worker_0, mbuf_0_0, bsz_wr);\n\t\t\tapp_lcore_io_rx_buffer_to_send(lp, worker_1, mbuf_0_1, bsz_wr);\n\t\t}\n\n\t\t/* Handle the last 1, 2 (when n_mbufs is even) or 3 (when n_mbufs is odd) packets */\n\t\tfor ( ; j < n_mbufs; j += 1) {\n\t\t\tstruct rte_mbuf *mbuf;\n\t\t\tuint8_t *data;\n\t\t\tuint32_t worker;\n\n\t\t\tmbuf = mbuf_1_0;\n\t\t\tmbuf_1_0 = mbuf_1_1;\n\t\t\tmbuf_1_1 = mbuf_2_0;\n\t\t\tmbuf_2_0 = mbuf_2_1;\n\n\t\t\tdata = rte_pktmbuf_mtod(mbuf, uint8_t *);\n\n\t\t\tAPP_IO_RX_PREFETCH0(mbuf_1_0);\n\n\t\t\tworker = data[pos_lb] & (n_workers - 1);\n\n\t\t\tapp_lcore_io_rx_buffer_to_send(lp, worker, mbuf, bsz_wr);\n\t\t}\n\t}\n}\n\nstatic inline void\napp_lcore_io_rx_flush(struct app_lcore_params_io *lp, uint32_t n_workers)\n{\n\tuint32_t worker;\n\n\tfor (worker = 0; worker < n_workers; worker ++) {\n\t\tint ret;\n\n\t\tif (likely((lp->rx.mbuf_out_flush[worker] == 0) ||\n\t\t (lp->rx.mbuf_out[worker].n_mbufs == 0))) {\n\t\t\tlp->rx.mbuf_out_flush[worker] = 1;\n\t\t\tcontinue;\n\t\t}\n\n\t\tret = rte_ring_sp_enqueue_bulk(\n\t\t\tlp->rx.rings[worker],\n\t\t\t(void **) lp->rx.mbuf_out[worker].array,\n\t\t\tlp->rx.mbuf_out[worker].n_mbufs);\n\n\t\tif (unlikely(ret < 0)) {\n\t\t\tuint32_t k;\n\t\t\tfor (k = 0; k < lp->rx.mbuf_out[worker].n_mbufs; k ++) {\n\t\t\t\tstruct rte_mbuf *pkt_to_free = lp->rx.mbuf_out[worker].array[k];\n\t\t\t\trte_pktmbuf_free(pkt_to_free);\n\t\t\t}\n\t\t}\n\n\t\tlp->rx.mbuf_out[worker].n_mbufs = 0;\n\t\tlp->rx.mbuf_out_flush[worker] = 1;\n\t}\n}\n\nstatic inline void\napp_lcore_io_tx(\n\tstruct app_lcore_params_io *lp,\n\tuint32_t n_workers,\n\tuint32_t bsz_rd,\n\tuint32_t bsz_wr)\n{\n\tuint32_t worker;\n\n\tfor (worker = 0; worker < n_workers; worker ++) {\n\t\tuint32_t i;\n\n\t\tfor (i = 0; i < lp->tx.n_nic_ports; i ++) {\n\t\t\tuint8_t port = lp->tx.nic_ports[i];\n\t\t\tstruct rte_ring *ring = lp->tx.rings[port][worker];\n\t\t\tuint32_t n_mbufs, n_pkts;\n\t\t\tint ret;\n\n\t\t\tn_mbufs = lp->tx.mbuf_out[port].n_mbufs;\n\t\t\tret = rte_ring_sc_dequeue_bulk(\n\t\t\t\tring,\n\t\t\t\t(void **) &lp->tx.mbuf_out[port].array[n_mbufs],\n\t\t\t\tbsz_rd);\n\n\t\t\tif (unlikely(ret == -ENOENT)) {\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tn_mbufs += bsz_rd;\n\n#if APP_IO_TX_DROP_ALL_PACKETS\n\t\t\t{\n\t\t\t\tuint32_t j;\n\t\t\t\tAPP_IO_TX_PREFETCH0(lp->tx.mbuf_out[port].array[0]);\n\t\t\t\tAPP_IO_TX_PREFETCH0(lp->tx.mbuf_out[port].array[1]);\n\n\t\t\t\tfor (j = 0; j < n_mbufs; j ++) {\n\t\t\t\t\tif (likely(j < n_mbufs - 2)) {\n\t\t\t\t\t\tAPP_IO_TX_PREFETCH0(lp->tx.mbuf_out[port].array[j + 2]);\n\t\t\t\t\t}\n\n\t\t\t\t\trte_pktmbuf_free(lp->tx.mbuf_out[port].array[j]);\n\t\t\t\t}\n\n\t\t\t\tlp->tx.mbuf_out[port].n_mbufs = 0;\n\n\t\t\t\tcontinue;\n\t\t\t}\n#endif\n\n\t\t\tif (unlikely(n_mbufs < bsz_wr)) {\n\t\t\t\tlp->tx.mbuf_out[port].n_mbufs = n_mbufs;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tn_pkts = rte_eth_tx_burst(\n\t\t\t\tport,\n\t\t\t\t0,\n\t\t\t\tlp->tx.mbuf_out[port].array,\n\t\t\t\t(uint16_t) n_mbufs);\n\n#if APP_STATS\n\t\t\tlp->tx.nic_ports_iters[port] ++;\n\t\t\tlp->tx.nic_ports_count[port] += n_pkts;\n\t\t\tif (unlikely(lp->tx.nic_ports_iters[port] == APP_STATS)) {\n\t\t\t\tunsigned lcore = rte_lcore_id();\n\n\t\t\t\tprintf(\"\\t\\t\\tI/O TX %u out (port %u): avg burst size = %.2f\\n\",\n\t\t\t\t\tlcore,\n\t\t\t\t\t(unsigned) port,\n\t\t\t\t\t((double) lp->tx.nic_ports_count[port]) / ((double) lp->tx.nic_ports_iters[port]));\n\t\t\t\tlp->tx.nic_ports_iters[port] = 0;\n\t\t\t\tlp->tx.nic_ports_count[port] = 0;\n\t\t\t}\n#endif\n\n\t\t\tif (unlikely(n_pkts < n_mbufs)) {\n\t\t\t\tuint32_t k;\n\t\t\t\tfor (k = n_pkts; k < n_mbufs; k ++) {\n\t\t\t\t\tstruct rte_mbuf *pkt_to_free = lp->tx.mbuf_out[port].array[k];\n\t\t\t\t\trte_pktmbuf_free(pkt_to_free);\n\t\t\t\t}\n\t\t\t}\n\t\t\tlp->tx.mbuf_out[port].n_mbufs = 0;\n\t\t\tlp->tx.mbuf_out_flush[port] = 0;\n\t\t}\n\t}\n}\n\nstatic inline void\napp_lcore_io_tx_flush(struct app_lcore_params_io *lp)\n{\n\tuint8_t port;\n\n\tfor (port = 0; port < lp->tx.n_nic_ports; port ++) {\n\t\tuint32_t n_pkts;\n\n\t\tif (likely((lp->tx.mbuf_out_flush[port] == 0) ||\n\t\t (lp->tx.mbuf_out[port].n_mbufs == 0))) {\n\t\t\tlp->tx.mbuf_out_flush[port] = 1;\n\t\t\tcontinue;\n\t\t}\n\n\t\tn_pkts = rte_eth_tx_burst(\n\t\t\tport,\n\t\t\t0,\n\t\t\tlp->tx.mbuf_out[port].array,\n\t\t\t(uint16_t) lp->tx.mbuf_out[port].n_mbufs);\n\n\t\tif (unlikely(n_pkts < lp->tx.mbuf_out[port].n_mbufs)) {\n\t\t\tuint32_t k;\n\t\t\tfor (k = n_pkts; k < lp->tx.mbuf_out[port].n_mbufs; k ++) {\n\t\t\t\tstruct rte_mbuf *pkt_to_free = lp->tx.mbuf_out[port].array[k];\n\t\t\t\trte_pktmbuf_free(pkt_to_free);\n\t\t\t}\n\t\t}\n\n\t\tlp->tx.mbuf_out[port].n_mbufs = 0;\n\t\tlp->tx.mbuf_out_flush[port] = 1;\n\t}\n}\n\nstatic void\napp_lcore_main_loop_io(void)\n{\n\tuint32_t lcore = rte_lcore_id();\n\tstruct app_lcore_params_io *lp = &app.lcore_params[lcore].io;\n\tuint32_t n_workers = app_get_lcores_worker();\n\tuint64_t i = 0;\n\n\tuint32_t bsz_rx_rd = app.burst_size_io_rx_read;\n\tuint32_t bsz_rx_wr = app.burst_size_io_rx_write;\n\tuint32_t bsz_tx_rd = app.burst_size_io_tx_read;\n\tuint32_t bsz_tx_wr = app.burst_size_io_tx_write;\n\n\tuint8_t pos_lb = app.pos_lb;\n\n\tfor ( ; ; ) {\n\t\tif (APP_LCORE_IO_FLUSH && (unlikely(i == APP_LCORE_IO_FLUSH))) {\n\t\t\tif (likely(lp->rx.n_nic_queues > 0)) {\n\t\t\t\tapp_lcore_io_rx_flush(lp, n_workers);\n\t\t\t}\n\n\t\t\tif (likely(lp->tx.n_nic_ports > 0)) {\n\t\t\t\tapp_lcore_io_tx_flush(lp);\n\t\t\t}\n\n\t\t\ti = 0;\n\t\t}\n\n\t\tif (likely(lp->rx.n_nic_queues > 0)) {\n\t\t\tapp_lcore_io_rx(lp, n_workers, bsz_rx_rd, bsz_rx_wr, pos_lb);\n\t\t}\n\n\t\tif (likely(lp->tx.n_nic_ports > 0)) {\n\t\t\tapp_lcore_io_tx(lp, n_workers, bsz_tx_rd, bsz_tx_wr);\n\t\t}\n\n\t\ti ++;\n\t}\n}\n\nstatic inline void\napp_lcore_worker(\n\tstruct app_lcore_params_worker *lp,\n\tuint32_t bsz_rd,\n\tuint32_t bsz_wr)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < lp->n_rings_in; i ++) {\n\t\tstruct rte_ring *ring_in = lp->rings_in[i];\n\t\tuint32_t j;\n\t\tint ret;\n\n\t\tret = rte_ring_sc_dequeue_bulk(\n\t\t\tring_in,\n\t\t\t(void **) lp->mbuf_in.array,\n\t\t\tbsz_rd);\n\n\t\tif (unlikely(ret == -ENOENT)) {\n\t\t\tcontinue;\n\t\t}\n\n#if APP_WORKER_DROP_ALL_PACKETS\n\t\tfor (j = 0; j < bsz_rd; j ++) {\n\t\t\tstruct rte_mbuf *pkt = lp->mbuf_in.array[j];\n\t\t\trte_pktmbuf_free(pkt);\n\t\t}\n\n\t\tcontinue;\n#endif\n\n\t\tAPP_WORKER_PREFETCH1(rte_pktmbuf_mtod(lp->mbuf_in.array[0], unsigned char *));\n\t\tAPP_WORKER_PREFETCH0(lp->mbuf_in.array[1]);\n\n\t\tfor (j = 0; j < bsz_rd; j ++) {\n\t\t\tstruct rte_mbuf *pkt;\n\t\t\tstruct ipv4_hdr *ipv4_hdr;\n\t\t\tuint32_t ipv4_dst, pos;\n\t\t\tuint8_t port;\n\n\t\t\tif (likely(j < bsz_rd - 1)) {\n\t\t\t\tAPP_WORKER_PREFETCH1(rte_pktmbuf_mtod(lp->mbuf_in.array[j+1], unsigned char *));\n\t\t\t}\n\t\t\tif (likely(j < bsz_rd - 2)) {\n\t\t\t\tAPP_WORKER_PREFETCH0(lp->mbuf_in.array[j+2]);\n\t\t\t}\n\n\t\t\tpkt = lp->mbuf_in.array[j];\n\t\t\tipv4_hdr = rte_pktmbuf_mtod_offset(pkt,\n\t\t\t\t\t\t\t struct ipv4_hdr *,\n\t\t\t\t\t\t\t sizeof(struct ether_hdr));\n\t\t\tipv4_dst = rte_be_to_cpu_32(ipv4_hdr->dst_addr);\n\n\t\t\tif (unlikely(rte_lpm_lookup(lp->lpm_table, ipv4_dst, &port) != 0)) {\n\t\t\t\tport = pkt->port;\n\t\t\t}\n\n\t\t\tpos = lp->mbuf_out[port].n_mbufs;\n\n\t\t\tlp->mbuf_out[port].array[pos ++] = pkt;\n\t\t\tif (likely(pos < bsz_wr)) {\n\t\t\t\tlp->mbuf_out[port].n_mbufs = pos;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tret = rte_ring_sp_enqueue_bulk(\n\t\t\t\tlp->rings_out[port],\n\t\t\t\t(void **) lp->mbuf_out[port].array,\n\t\t\t\tbsz_wr);\n\n#if APP_STATS\n\t\t\tlp->rings_out_iters[port] ++;\n\t\t\tif (ret == 0) {\n\t\t\t\tlp->rings_out_count[port] += 1;\n\t\t\t}\n\t\t\tif (lp->rings_out_iters[port] == APP_STATS){\n\t\t\t\tprintf(\"\\t\\tWorker %u out (NIC port %u): enq success rate = %.2f\\n\",\n\t\t\t\t\t(unsigned) lp->worker_id,\n\t\t\t\t\t(unsigned) port,\n\t\t\t\t\t((double) lp->rings_out_count[port]) / ((double) lp->rings_out_iters[port]));\n\t\t\t\tlp->rings_out_iters[port] = 0;\n\t\t\t\tlp->rings_out_count[port] = 0;\n\t\t\t}\n#endif\n\n\t\t\tif (unlikely(ret == -ENOBUFS)) {\n\t\t\t\tuint32_t k;\n\t\t\t\tfor (k = 0; k < bsz_wr; k ++) {\n\t\t\t\t\tstruct rte_mbuf *pkt_to_free = lp->mbuf_out[port].array[k];\n\t\t\t\t\trte_pktmbuf_free(pkt_to_free);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tlp->mbuf_out[port].n_mbufs = 0;\n\t\t\tlp->mbuf_out_flush[port] = 0;\n\t\t}\n\t}\n}\n\nstatic inline void\napp_lcore_worker_flush(struct app_lcore_params_worker *lp)\n{\n\tuint32_t port;\n\n\tfor (port = 0; port < APP_MAX_NIC_PORTS; port ++) {\n\t\tint ret;\n\n\t\tif (unlikely(lp->rings_out[port] == NULL)) {\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (likely((lp->mbuf_out_flush[port] == 0) ||\n\t\t (lp->mbuf_out[port].n_mbufs == 0))) {\n\t\t\tlp->mbuf_out_flush[port] = 1;\n\t\t\tcontinue;\n\t\t}\n\n\t\tret = rte_ring_sp_enqueue_bulk(\n\t\t\tlp->rings_out[port],\n\t\t\t(void **) lp->mbuf_out[port].array,\n\t\t\tlp->mbuf_out[port].n_mbufs);\n\n\t\tif (unlikely(ret < 0)) {\n\t\t\tuint32_t k;\n\t\t\tfor (k = 0; k < lp->mbuf_out[port].n_mbufs; k ++) {\n\t\t\t\tstruct rte_mbuf *pkt_to_free = lp->mbuf_out[port].array[k];\n\t\t\t\trte_pktmbuf_free(pkt_to_free);\n\t\t\t}\n\t\t}\n\n\t\tlp->mbuf_out[port].n_mbufs = 0;\n\t\tlp->mbuf_out_flush[port] = 1;\n\t}\n}\n\nstatic void\napp_lcore_main_loop_worker(void) {\n\tuint32_t lcore = rte_lcore_id();\n\tstruct app_lcore_params_worker *lp = &app.lcore_params[lcore].worker;\n\tuint64_t i = 0;\n\n\tuint32_t bsz_rd = app.burst_size_worker_read;\n\tuint32_t bsz_wr = app.burst_size_worker_write;\n\n\tfor ( ; ; ) {\n\t\tif (APP_LCORE_WORKER_FLUSH && (unlikely(i == APP_LCORE_WORKER_FLUSH))) {\n\t\t\tapp_lcore_worker_flush(lp);\n\t\t\ti = 0;\n\t\t}\n\n\t\tapp_lcore_worker(lp, bsz_rd, bsz_wr);\n\n\t\ti ++;\n\t}\n}\n\nint\napp_lcore_main_loop(__attribute__((unused)) void *arg)\n{\n\tstruct app_lcore_params *lp;\n\tunsigned lcore;\n\n\tlcore = rte_lcore_id();\n\tlp = &app.lcore_params[lcore];\n\n\tif (lp->type == e_APP_LCORE_IO) {\n\t\tprintf(\"Logical core %u (I/O) main loop.\\n\", lcore);\n\t\tapp_lcore_main_loop_io();\n\t}\n\n\tif (lp->type == e_APP_LCORE_WORKER) {\n\t\tprintf(\"Logical core %u (worker %u) main loop.\\n\",\n\t\t\tlcore,\n\t\t\t(unsigned) lp->worker.worker_id);\n\t\tapp_lcore_main_loop_worker();\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/multi_process/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nDIRS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += client_server_mp\nDIRS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += simple_mp\nDIRS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += symmetric_mp\n\ninclude $(RTE_SDK)/mk/rte.extsubdir.mk\n" }, { "path": "examples/multi_process/client_server_mp/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nDIRS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += mp_client\nDIRS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += mp_server\n\ninclude $(RTE_SDK)/mk/rte.extsubdir.mk\n" }, { "path": "examples/multi_process/client_server_mp/mp_client/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = mp_client\n\n# all source are stored in SRCS-y\nSRCS-y := client.c\n\nCFLAGS += $(WERROR_FLAGS) -O3\nCFLAGS += -I$(SRCDIR)/../shared\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/multi_process/client_server_mp/mp_client/client.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"common.h\"\n\n/* Number of packets to attempt to read from queue */\n#define PKT_READ_SIZE ((uint16_t)32)\n\n/* our client id number - tells us which rx queue to read, and NIC TX\n * queue to write to. */\nstatic uint8_t client_id = 0;\n\nstruct mbuf_queue {\n#define MBQ_CAPACITY 32\n\tstruct rte_mbuf *bufs[MBQ_CAPACITY];\n\tuint16_t top;\n};\n\n/* maps input ports to output ports for packets */\nstatic uint8_t output_ports[RTE_MAX_ETHPORTS];\n\n/* buffers up a set of packet that are ready to send */\nstatic struct mbuf_queue output_bufs[RTE_MAX_ETHPORTS];\n\n/* shared data from server. We update statistics here */\nstatic volatile struct tx_stats *tx_stats;\n\n\n/*\n * print a usage message\n */\nstatic void\nusage(const char *progname)\n{\n\tprintf(\"Usage: %s [EAL args] -- -n \\n\\n\", progname);\n}\n\n/*\n * Convert the client id number from a string to an int.\n */\nstatic int\nparse_client_num(const char *client)\n{\n\tchar *end = NULL;\n\tunsigned long temp;\n\n\tif (client == NULL || *client == '\\0')\n\t\treturn -1;\n\n\ttemp = strtoul(client, &end, 10);\n\tif (end == NULL || *end != '\\0')\n\t\treturn -1;\n\n\tclient_id = (uint8_t)temp;\n\treturn 0;\n}\n\n/*\n * Parse the application arguments to the client app.\n */\nstatic int\nparse_app_args(int argc, char *argv[])\n{\n\tint option_index, opt;\n\tchar **argvopt = argv;\n\tconst char *progname = NULL;\n\tstatic struct option lgopts[] = { /* no long options */\n\t\t{NULL, 0, 0, 0 }\n\t};\n\tprogname = argv[0];\n\n\twhile ((opt = getopt_long(argc, argvopt, \"n:\", lgopts,\n\t\t&option_index)) != EOF){\n\t\tswitch (opt){\n\t\t\tcase 'n':\n\t\t\t\tif (parse_client_num(optarg) != 0){\n\t\t\t\t\tusage(progname);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tusage(progname);\n\t\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\n/*\n * set up output ports so that all traffic on port gets sent out\n * its paired port. Index using actual port numbers since that is\n * what comes in the mbuf structure.\n */\nstatic void configure_output_ports(const struct port_info *ports)\n{\n\tint i;\n\tif (ports->num_ports > RTE_MAX_ETHPORTS)\n\t\trte_exit(EXIT_FAILURE, \"Too many ethernet ports. RTE_MAX_ETHPORTS = %u\\n\",\n\t\t\t\t(unsigned)RTE_MAX_ETHPORTS);\n\tfor (i = 0; i < ports->num_ports - 1; i+=2){\n\t\tuint8_t p1 = ports->id[i];\n\t\tuint8_t p2 = ports->id[i+1];\n\t\toutput_ports[p1] = p2;\n\t\toutput_ports[p2] = p1;\n\t}\n}\n\n\nstatic inline void\nsend_packets(uint8_t port)\n{\n\tuint16_t i, sent;\n\tstruct mbuf_queue *mbq = &output_bufs[port];\n\n\tif (unlikely(mbq->top == 0))\n\t\treturn;\n\n\tsent = rte_eth_tx_burst(port, client_id, mbq->bufs, mbq->top);\n\tif (unlikely(sent < mbq->top)){\n\t\tfor (i = sent; i < mbq->top; i++)\n\t\t\trte_pktmbuf_free(mbq->bufs[i]);\n\t\ttx_stats->tx_drop[port] += (mbq->top - sent);\n\t}\n\ttx_stats->tx[port] += sent;\n\tmbq->top = 0;\n}\n\n/*\n * Enqueue a packet to be sent on a particular port, but\n * don't send it yet. Only when the buffer is full.\n */\nstatic inline void\nenqueue_packet(struct rte_mbuf *buf, uint8_t port)\n{\n\tstruct mbuf_queue *mbq = &output_bufs[port];\n\tmbq->bufs[mbq->top++] = buf;\n\n\tif (mbq->top == MBQ_CAPACITY)\n\t\tsend_packets(port);\n}\n\n/*\n * This function performs routing of packets\n * Just sends each input packet out an output port based solely on the input\n * port it arrived on.\n */\nstatic void\nhandle_packet(struct rte_mbuf *buf)\n{\n\tconst uint8_t in_port = buf->port;\n\tconst uint8_t out_port = output_ports[in_port];\n\n\tenqueue_packet(buf, out_port);\n}\n\n/*\n * Application main function - loops through\n * receiving and processing packets. Never returns\n */\nint\nmain(int argc, char *argv[])\n{\n\tconst struct rte_memzone *mz;\n\tstruct rte_ring *rx_ring;\n\tstruct rte_mempool *mp;\n\tstruct port_info *ports;\n\tint need_flush = 0; /* indicates whether we have unsent packets */\n\tint retval;\n\tvoid *pkts[PKT_READ_SIZE];\n\n\tif ((retval = rte_eal_init(argc, argv)) < 0)\n\t\treturn -1;\n\targc -= retval;\n\targv += retval;\n\n\tif (parse_app_args(argc, argv) < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid command-line arguments\\n\");\n\n\tif (rte_eth_dev_count() == 0)\n\t\trte_exit(EXIT_FAILURE, \"No Ethernet ports - bye\\n\");\n\n\trx_ring = rte_ring_lookup(get_rx_queue_name(client_id));\n\tif (rx_ring == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot get RX ring - is server process running?\\n\");\n\n\tmp = rte_mempool_lookup(PKTMBUF_POOL_NAME);\n\tif (mp == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot get mempool for mbufs\\n\");\n\n\tmz = rte_memzone_lookup(MZ_PORT_INFO);\n\tif (mz == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot get port info structure\\n\");\n\tports = mz->addr;\n\ttx_stats = &(ports->tx_stats[client_id]);\n\n\tconfigure_output_ports(ports);\n\n\tRTE_LOG(INFO, APP, \"Finished Process Init.\\n\");\n\n\tprintf(\"\\nClient process %d handling packets\\n\", client_id);\n\tprintf(\"[Press Ctrl-C to quit ...]\\n\");\n\n\tfor (;;) {\n\t\tuint16_t i, rx_pkts = PKT_READ_SIZE;\n\t\tuint8_t port;\n\n\t\t/* try dequeuing max possible packets first, if that fails, get the\n\t\t * most we can. Loop body should only execute once, maximum */\n\t\twhile (rx_pkts > 0 &&\n\t\t\t\tunlikely(rte_ring_dequeue_bulk(rx_ring, pkts, rx_pkts) != 0))\n\t\t\trx_pkts = (uint16_t)RTE_MIN(rte_ring_count(rx_ring), PKT_READ_SIZE);\n\n\t\tif (unlikely(rx_pkts == 0)){\n\t\t\tif (need_flush)\n\t\t\t\tfor (port = 0; port < ports->num_ports; port++)\n\t\t\t\t\tsend_packets(ports->id[port]);\n\t\t\tneed_flush = 0;\n\t\t\tcontinue;\n\t\t}\n\n\t\tfor (i = 0; i < rx_pkts; i++)\n\t\t\thandle_packet(pkts[i]);\n\n\t\tneed_flush = 1;\n\t}\n}\n" }, { "path": "examples/multi_process/client_server_mp/mp_server/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifneq ($(CONFIG_RTE_EXEC_ENV),\"linuxapp\")\n$(error This application can only operate in a linuxapp environment, \\\nplease change the definition of the RTE_TARGET environment variable)\nendif\n\n# binary name\nAPP = mp_server\n\n# all source are stored in SRCS-y\nSRCS-y := main.c init.c args.c\n\nINC := $(wildcard *.h)\n\nCFLAGS += $(WERROR_FLAGS) -O3\nCFLAGS += -I$(SRCDIR)/../shared\n\n# for newer gcc, e.g. 4.4, no-strict-aliasing may not be necessary\n# and so the next line can be removed in those cases.\nEXTRA_CFLAGS += -fno-strict-aliasing\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/multi_process/client_server_mp/mp_server/args.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \"common.h\"\n#include \"args.h\"\n#include \"init.h\"\n\n/* global var for number of clients - extern in header */\nuint8_t num_clients;\n\nstatic const char *progname;\n\n/**\n * Prints out usage information to stdout\n */\nstatic void\nusage(void)\n{\n\tprintf(\n\t \"%s [EAL options] -- -p PORTMASK -n NUM_CLIENTS [-s NUM_SOCKETS]\\n\"\n\t \" -p PORTMASK: hexadecimal bitmask of ports to use\\n\"\n\t \" -n NUM_CLIENTS: number of client processes to use\\n\"\n\t , progname);\n}\n\n/**\n * The ports to be used by the application are passed in\n * the form of a bitmask. This function parses the bitmask\n * and places the port numbers to be used into the port[]\n * array variable\n */\nstatic int\nparse_portmask(uint8_t max_ports, const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\tuint8_t count = 0;\n\n\tif (portmask == NULL || *portmask == '\\0')\n\t\treturn -1;\n\n\t/* convert parameter to a number and verify */\n\tpm = strtoul(portmask, &end, 16);\n\tif (end == NULL || *end != '\\0' || pm == 0)\n\t\treturn -1;\n\n\t/* loop through bits of the mask and mark ports */\n\twhile (pm != 0){\n\t\tif (pm & 0x01){ /* bit is set in mask, use port */\n\t\t\tif (count >= max_ports)\n\t\t\t\tprintf(\"WARNING: requested port %u not present\"\n\t\t\t\t\" - ignoring\\n\", (unsigned)count);\n\t\t\telse\n\t\t\t ports->id[ports->num_ports++] = count;\n\t\t}\n\t\tpm = (pm >> 1);\n\t\tcount++;\n\t}\n\n\treturn 0;\n}\n\n/**\n * Take the number of clients parameter passed to the app\n * and convert to a number to store in the num_clients variable\n */\nstatic int\nparse_num_clients(const char *clients)\n{\n\tchar *end = NULL;\n\tunsigned long temp;\n\n\tif (clients == NULL || *clients == '\\0')\n\t\treturn -1;\n\n\ttemp = strtoul(clients, &end, 10);\n\tif (end == NULL || *end != '\\0' || temp == 0)\n\t\treturn -1;\n\n\tnum_clients = (uint8_t)temp;\n\treturn 0;\n}\n\n/**\n * The application specific arguments follow the DPDK-specific\n * arguments which are stripped by the DPDK init. This function\n * processes these application arguments, printing usage info\n * on error.\n */\nint\nparse_app_args(uint8_t max_ports, int argc, char *argv[])\n{\n\tint option_index, opt;\n\tchar **argvopt = argv;\n\tstatic struct option lgopts[] = { /* no long options */\n\t\t{NULL, 0, 0, 0 }\n\t};\n\tprogname = argv[0];\n\n\twhile ((opt = getopt_long(argc, argvopt, \"n:p:\", lgopts,\n\t\t&option_index)) != EOF){\n\t\tswitch (opt){\n\t\t\tcase 'p':\n\t\t\t\tif (parse_portmask(max_ports, optarg) != 0){\n\t\t\t\t\tusage();\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 'n':\n\t\t\t\tif (parse_num_clients(optarg) != 0){\n\t\t\t\t\tusage();\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tprintf(\"ERROR: Unknown option '%c'\\n\", opt);\n\t\t\t\tusage();\n\t\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (ports->num_ports == 0 || num_clients == 0){\n\t\tusage();\n\t\treturn -1;\n\t}\n\n\tif (ports->num_ports % 2 != 0){\n\t\tprintf(\"ERROR: application requires an even number of ports to use\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n" }, { "path": "examples/multi_process/client_server_mp/mp_server/args.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _ARGS_H_\n#define _ARGS_H_\n\nint parse_app_args(uint8_t max_ports, int argc, char *argv[]);\n\n#endif /* ifndef _ARGS_H_ */\n" }, { "path": "examples/multi_process/client_server_mp/mp_server/init.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"common.h\"\n#include \"args.h\"\n#include \"init.h\"\n\n#define MBUFS_PER_CLIENT 1536\n#define MBUFS_PER_PORT 1536\n#define MBUF_CACHE_SIZE 512\n\n#define RTE_MP_RX_DESC_DEFAULT 512\n#define RTE_MP_TX_DESC_DEFAULT 512\n#define CLIENT_QUEUE_RINGSIZE 128\n\n#define NO_FLAGS 0\n\n/* The mbuf pool for packet rx */\nstruct rte_mempool *pktmbuf_pool;\n\n/* array of info/queues for clients */\nstruct client *clients = NULL;\n\n/* the port details */\nstruct port_info *ports;\n\n/**\n * Initialise the mbuf pool for packet reception for the NIC, and any other\n * buffer pools needed by the app - currently none.\n */\nstatic int\ninit_mbuf_pools(void)\n{\n\tconst unsigned num_mbufs = (num_clients * MBUFS_PER_CLIENT) \\\n\t\t\t+ (ports->num_ports * MBUFS_PER_PORT);\n\n\t/* don't pass single-producer/single-consumer flags to mbuf create as it\n\t * seems faster to use a cache instead */\n\tprintf(\"Creating mbuf pool '%s' [%u mbufs] ...\\n\",\n\t\t\tPKTMBUF_POOL_NAME, num_mbufs);\n\tpktmbuf_pool = rte_pktmbuf_pool_create(PKTMBUF_POOL_NAME, num_mbufs,\n\t\tMBUF_CACHE_SIZE, 0, RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\n\treturn (pktmbuf_pool == NULL); /* 0 on success */\n}\n\n/**\n * Initialise an individual port:\n * - configure number of rx and tx rings\n * - set up each rx ring, to pull from the main mbuf pool\n * - set up each tx ring\n * - start the port and report its status to stdout\n */\nstatic int\ninit_port(uint8_t port_num)\n{\n\t/* for port configuration all features are off by default */\n\tconst struct rte_eth_conf port_conf = {\n\t\t.rxmode = {\n\t\t\t.mq_mode = ETH_MQ_RX_RSS\n\t\t}\n\t};\n\tconst uint16_t rx_rings = 1, tx_rings = num_clients;\n\tconst uint16_t rx_ring_size = RTE_MP_RX_DESC_DEFAULT;\n\tconst uint16_t tx_ring_size = RTE_MP_TX_DESC_DEFAULT;\n\n\tuint16_t q;\n\tint retval;\n\n\tprintf(\"Port %u init ... \", (unsigned)port_num);\n\tfflush(stdout);\n\n\t/* Standard DPDK port initialisation - config port, then set up\n\t * rx and tx rings */\n\tif ((retval = rte_eth_dev_configure(port_num, rx_rings, tx_rings,\n\t\t&port_conf)) != 0)\n\t\treturn retval;\n\n\tfor (q = 0; q < rx_rings; q++) {\n\t\tretval = rte_eth_rx_queue_setup(port_num, q, rx_ring_size,\n\t\t\t\trte_eth_dev_socket_id(port_num),\n\t\t\t\tNULL, pktmbuf_pool);\n\t\tif (retval < 0) return retval;\n\t}\n\n\tfor ( q = 0; q < tx_rings; q ++ ) {\n\t\tretval = rte_eth_tx_queue_setup(port_num, q, tx_ring_size,\n\t\t\t\trte_eth_dev_socket_id(port_num),\n\t\t\t\tNULL);\n\t\tif (retval < 0) return retval;\n\t}\n\n\trte_eth_promiscuous_enable(port_num);\n\n\tretval = rte_eth_dev_start(port_num);\n\tif (retval < 0) return retval;\n\n\tprintf( \"done: \\n\");\n\n\treturn 0;\n}\n\n/**\n * Set up the DPDK rings which will be used to pass packets, via\n * pointers, between the multi-process server and client processes.\n * Each client needs one RX queue.\n */\nstatic int\ninit_shm_rings(void)\n{\n\tunsigned i;\n\tunsigned socket_id;\n\tconst char * q_name;\n\tconst unsigned ringsize = CLIENT_QUEUE_RINGSIZE;\n\n\tclients = rte_malloc(\"client details\",\n\t\tsizeof(*clients) * num_clients, 0);\n\tif (clients == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot allocate memory for client program details\\n\");\n\n\tfor (i = 0; i < num_clients; i++) {\n\t\t/* Create an RX queue for each client */\n\t\tsocket_id = rte_socket_id();\n\t\tq_name = get_rx_queue_name(i);\n\t\tclients[i].rx_q = rte_ring_create(q_name,\n\t\t\t\tringsize, socket_id,\n\t\t\t\tRING_F_SP_ENQ | RING_F_SC_DEQ ); /* single prod, single cons */\n\t\tif (clients[i].rx_q == NULL)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot create rx ring queue for client %u\\n\", i);\n\t}\n\treturn 0;\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << ports->id[portid])) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(ports->id[portid], &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", ports->id[portid],\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)ports->id[portid]);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\n/**\n * Main init function for the multi-process server app,\n * calls subfunctions to do each stage of the initialisation.\n */\nint\ninit(int argc, char *argv[])\n{\n\tint retval;\n\tconst struct rte_memzone *mz;\n\tuint8_t i, total_ports;\n\n\t/* init EAL, parsing EAL args */\n\tretval = rte_eal_init(argc, argv);\n\tif (retval < 0)\n\t\treturn -1;\n\targc -= retval;\n\targv += retval;\n\n\t/* get total number of ports */\n\ttotal_ports = rte_eth_dev_count();\n\n\t/* set up array for port data */\n\tmz = rte_memzone_reserve(MZ_PORT_INFO, sizeof(*ports),\n\t\t\t\trte_socket_id(), NO_FLAGS);\n\tif (mz == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot reserve memory zone for port information\\n\");\n\tmemset(mz->addr, 0, sizeof(*ports));\n\tports = mz->addr;\n\n\t/* parse additional, application arguments */\n\tretval = parse_app_args(total_ports, argc, argv);\n\tif (retval != 0)\n\t\treturn -1;\n\n\t/* initialise mbuf pools */\n\tretval = init_mbuf_pools();\n\tif (retval != 0)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create needed mbuf pools\\n\");\n\n\t/* now initialise the ports we will use */\n\tfor (i = 0; i < ports->num_ports; i++) {\n\t\tretval = init_port(ports->id[i]);\n\t\tif (retval != 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot initialise port %u\\n\",\n\t\t\t\t\t(unsigned)i);\n\t}\n\n\tcheck_all_ports_link_status(ports->num_ports, (~0x0));\n\n\t/* initialise the client queues/rings for inter-eu comms */\n\tinit_shm_rings();\n\n\treturn 0;\n}\n" }, { "path": "examples/multi_process/client_server_mp/mp_server/init.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _INIT_H_\n#define _INIT_H_\n\n/*\n * #include \n * #include \"args.h\"\n */\n\n/*\n * Define a client structure with all needed info, including\n * stats from the clients.\n */\nstruct client {\n\tstruct rte_ring *rx_q;\n\tunsigned client_id;\n\t/* these stats hold how many packets the client will actually receive,\n\t * and how many packets were dropped because the client's queue was full.\n\t * The port-info stats, in contrast, record how many packets were received\n\t * or transmitted on an actual NIC port.\n\t */\n\tstruct {\n\t\tvolatile uint64_t rx;\n\t\tvolatile uint64_t rx_drop;\n\t} stats;\n};\n\nextern struct client *clients;\n\n/* the shared port information: port numbers, rx and tx stats etc. */\nextern struct port_info *ports;\n\nextern struct rte_mempool *pktmbuf_pool;\nextern uint8_t num_clients;\nextern unsigned num_sockets;\nextern struct port_info *ports;\n\nint init(int argc, char *argv[]);\n\n#endif /* ifndef _INIT_H_ */\n" }, { "path": "examples/multi_process/client_server_mp/mp_server/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"common.h\"\n#include \"args.h\"\n#include \"init.h\"\n\n/*\n * When doing reads from the NIC or the client queues,\n * use this batch size\n */\n#define PACKET_READ_SIZE 32\n\n/*\n * Local buffers to put packets in, used to send packets in bursts to the\n * clients\n */\nstruct client_rx_buf {\n\tstruct rte_mbuf *buffer[PACKET_READ_SIZE];\n\tuint16_t count;\n};\n\n/* One buffer per client rx queue - dynamically allocate array */\nstatic struct client_rx_buf *cl_rx_buf;\n\nstatic const char *\nget_printable_mac_addr(uint8_t port)\n{\n\tstatic const char err_address[] = \"00:00:00:00:00:00\";\n\tstatic char addresses[RTE_MAX_ETHPORTS][sizeof(err_address)];\n\n\tif (unlikely(port >= RTE_MAX_ETHPORTS))\n\t\treturn err_address;\n\tif (unlikely(addresses[port][0]=='\\0')){\n\t\tstruct ether_addr mac;\n\t\trte_eth_macaddr_get(port, &mac);\n\t\tsnprintf(addresses[port], sizeof(addresses[port]),\n\t\t\t\t\"%02x:%02x:%02x:%02x:%02x:%02x\\n\",\n\t\t\t\tmac.addr_bytes[0], mac.addr_bytes[1], mac.addr_bytes[2],\n\t\t\t\tmac.addr_bytes[3], mac.addr_bytes[4], mac.addr_bytes[5]);\n\t}\n\treturn addresses[port];\n}\n\n/*\n * This function displays the recorded statistics for each port\n * and for each client. It uses ANSI terminal codes to clear\n * screen when called. It is called from a single non-master\n * thread in the server process, when the process is run with more\n * than one lcore enabled.\n */\nstatic void\ndo_stats_display(void)\n{\n\tunsigned i, j;\n\tconst char clr[] = { 27, '[', '2', 'J', '\\0' };\n\tconst char topLeft[] = { 27, '[', '1', ';', '1', 'H','\\0' };\n\tuint64_t port_tx[RTE_MAX_ETHPORTS], port_tx_drop[RTE_MAX_ETHPORTS];\n\tuint64_t client_tx[MAX_CLIENTS], client_tx_drop[MAX_CLIENTS];\n\n\t/* to get TX stats, we need to do some summing calculations */\n\tmemset(port_tx, 0, sizeof(port_tx));\n\tmemset(port_tx_drop, 0, sizeof(port_tx_drop));\n\tmemset(client_tx, 0, sizeof(client_tx));\n\tmemset(client_tx_drop, 0, sizeof(client_tx_drop));\n\n\tfor (i = 0; i < num_clients; i++){\n\t\tconst volatile struct tx_stats *tx = &ports->tx_stats[i];\n\t\tfor (j = 0; j < ports->num_ports; j++){\n\t\t\t/* assign to local variables here, save re-reading volatile vars */\n\t\t\tconst uint64_t tx_val = tx->tx[ports->id[j]];\n\t\t\tconst uint64_t drop_val = tx->tx_drop[ports->id[j]];\n\t\t\tport_tx[j] += tx_val;\n\t\t\tport_tx_drop[j] += drop_val;\n\t\t\tclient_tx[i] += tx_val;\n\t\t\tclient_tx_drop[i] += drop_val;\n\t\t}\n\t}\n\n\t/* Clear screen and move to top left */\n\tprintf(\"%s%s\", clr, topLeft);\n\n\tprintf(\"PORTS\\n\");\n\tprintf(\"-----\\n\");\n\tfor (i = 0; i < ports->num_ports; i++)\n\t\tprintf(\"Port %u: '%s'\\t\", (unsigned)ports->id[i],\n\t\t\t\tget_printable_mac_addr(ports->id[i]));\n\tprintf(\"\\n\\n\");\n\tfor (i = 0; i < ports->num_ports; i++){\n\t\tprintf(\"Port %u - rx: %9\"PRIu64\"\\t\"\n\t\t\t\t\"tx: %9\"PRIu64\"\\n\",\n\t\t\t\t(unsigned)ports->id[i], ports->rx_stats.rx[i],\n\t\t\t\tport_tx[i]);\n\t}\n\n\tprintf(\"\\nCLIENTS\\n\");\n\tprintf(\"-------\\n\");\n\tfor (i = 0; i < num_clients; i++){\n\t\tconst unsigned long long rx = clients[i].stats.rx;\n\t\tconst unsigned long long rx_drop = clients[i].stats.rx_drop;\n\t\tprintf(\"Client %2u - rx: %9llu, rx_drop: %9llu\\n\"\n\t\t\t\t\" tx: %9\"PRIu64\", tx_drop: %9\"PRIu64\"\\n\",\n\t\t\t\ti, rx, rx_drop, client_tx[i], client_tx_drop[i]);\n\t}\n\n\tprintf(\"\\n\");\n}\n\n/*\n * The function called from each non-master lcore used by the process.\n * The test_and_set function is used to randomly pick a single lcore on which\n * the code to display the statistics will run. Otherwise, the code just\n * repeatedly sleeps.\n */\nstatic int\nsleep_lcore(__attribute__((unused)) void *dummy)\n{\n\t/* Used to pick a display thread - static, so zero-initialised */\n\tstatic rte_atomic32_t display_stats;\n\n\t/* Only one core should display stats */\n\tif (rte_atomic32_test_and_set(&display_stats)) {\n\t\tconst unsigned sleeptime = 1;\n\t\tprintf(\"Core %u displaying statistics\\n\", rte_lcore_id());\n\n\t\t/* Longer initial pause so above printf is seen */\n\t\tsleep(sleeptime * 3);\n\n\t\t/* Loop forever: sleep always returns 0 or <= param */\n\t\twhile (sleep(sleeptime) <= sleeptime)\n\t\t\tdo_stats_display();\n\t}\n\treturn 0;\n}\n\n/*\n * Function to set all the client statistic values to zero.\n * Called at program startup.\n */\nstatic void\nclear_stats(void)\n{\n\tunsigned i;\n\n\tfor (i = 0; i < num_clients; i++)\n\t\tclients[i].stats.rx = clients[i].stats.rx_drop = 0;\n}\n\n/*\n * send a burst of traffic to a client, assuming there are packets\n * available to be sent to this client\n */\nstatic void\nflush_rx_queue(uint16_t client)\n{\n\tuint16_t j;\n\tstruct client *cl;\n\n\tif (cl_rx_buf[client].count == 0)\n\t\treturn;\n\n\tcl = &clients[client];\n\tif (rte_ring_enqueue_bulk(cl->rx_q, (void **)cl_rx_buf[client].buffer,\n\t\t\tcl_rx_buf[client].count) != 0){\n\t\tfor (j = 0; j < cl_rx_buf[client].count; j++)\n\t\t\trte_pktmbuf_free(cl_rx_buf[client].buffer[j]);\n\t\tcl->stats.rx_drop += cl_rx_buf[client].count;\n\t}\n\telse\n\t\tcl->stats.rx += cl_rx_buf[client].count;\n\n\tcl_rx_buf[client].count = 0;\n}\n\n/*\n * marks a packet down to be sent to a particular client process\n */\nstatic inline void\nenqueue_rx_packet(uint8_t client, struct rte_mbuf *buf)\n{\n\tcl_rx_buf[client].buffer[cl_rx_buf[client].count++] = buf;\n}\n\n/*\n * This function takes a group of packets and routes them\n * individually to the client process. Very simply round-robins the packets\n * without checking any of the packet contents.\n */\nstatic void\nprocess_packets(uint32_t port_num __rte_unused,\n\t\tstruct rte_mbuf *pkts[], uint16_t rx_count)\n{\n\tuint16_t i;\n\tuint8_t client = 0;\n\n\tfor (i = 0; i < rx_count; i++) {\n\t\tenqueue_rx_packet(client, pkts[i]);\n\n\t\tif (++client == num_clients)\n\t\t\tclient = 0;\n\t}\n\n\tfor (i = 0; i < num_clients; i++)\n\t\tflush_rx_queue(i);\n}\n\n/*\n * Function called by the master lcore of the DPDK process.\n */\nstatic void\ndo_packet_forwarding(void)\n{\n\tunsigned port_num = 0; /* indexes the port[] array */\n\n\tfor (;;) {\n\t\tstruct rte_mbuf *buf[PACKET_READ_SIZE];\n\t\tuint16_t rx_count;\n\n\t\t/* read a port */\n\t\trx_count = rte_eth_rx_burst(ports->id[port_num], 0, \\\n\t\t\t\tbuf, PACKET_READ_SIZE);\n\t\tports->rx_stats.rx[port_num] += rx_count;\n\n\t\t/* Now process the NIC packets read */\n\t\tif (likely(rx_count > 0))\n\t\t\tprocess_packets(port_num, buf, rx_count);\n\n\t\t/* move to next port */\n\t\tif (++port_num == ports->num_ports)\n\t\t\tport_num = 0;\n\t}\n}\n\nint\nmain(int argc, char *argv[])\n{\n\t/* initialise the system */\n\tif (init(argc, argv) < 0 )\n\t\treturn -1;\n\tRTE_LOG(INFO, APP, \"Finished Process Init.\\n\");\n\n\tcl_rx_buf = calloc(num_clients, sizeof(cl_rx_buf[0]));\n\n\t/* clear statistics */\n\tclear_stats();\n\n\t/* put all other cores to sleep bar master */\n\trte_eal_mp_remote_launch(sleep_lcore, NULL, SKIP_MASTER);\n\n\tdo_packet_forwarding();\n\treturn 0;\n}\n" }, { "path": "examples/multi_process/client_server_mp/shared/common.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _COMMON_H_\n#define _COMMON_H_\n\n#define MAX_CLIENTS 16\n\n/*\n * Shared port info, including statistics information for display by server.\n * Structure will be put in a memzone.\n * - All port id values share one cache line as this data will be read-only\n * during operation.\n * - All rx statistic values share cache lines, as this data is written only\n * by the server process. (rare reads by stats display)\n * - The tx statistics have values for all ports per cache line, but the stats\n * themselves are written by the clients, so we have a distinct set, on different\n * cache lines for each client to use.\n */\nstruct rx_stats{\n\tuint64_t rx[RTE_MAX_ETHPORTS];\n} __rte_cache_aligned;\n\nstruct tx_stats{\n\tuint64_t tx[RTE_MAX_ETHPORTS];\n\tuint64_t tx_drop[RTE_MAX_ETHPORTS];\n} __rte_cache_aligned;\n\nstruct port_info {\n\tuint8_t num_ports;\n\tuint8_t id[RTE_MAX_ETHPORTS];\n\tvolatile struct rx_stats rx_stats;\n\tvolatile struct tx_stats tx_stats[MAX_CLIENTS];\n};\n\n/* define common names for structures shared between server and client */\n#define MP_CLIENT_RXQ_NAME \"MProc_Client_%u_RX\"\n#define PKTMBUF_POOL_NAME \"MProc_pktmbuf_pool\"\n#define MZ_PORT_INFO \"MProc_port_info\"\n\n/*\n * Given the rx queue name template above, get the queue name\n */\nstatic inline const char *\nget_rx_queue_name(unsigned id)\n{\n\t/* buffer for return value. Size calculated by %u being replaced\n\t * by maximum 3 digits (plus an extra byte for safety) */\n\tstatic char buffer[sizeof(MP_CLIENT_RXQ_NAME) + 2];\n\n\tsnprintf(buffer, sizeof(buffer) - 1, MP_CLIENT_RXQ_NAME, id);\n\treturn buffer;\n}\n\n#define RTE_LOGTYPE_APP RTE_LOGTYPE_USER1\n\n#endif\n" }, { "path": "examples/multi_process/l2fwd_fork/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = l2fwd_fork\n\n# all source are stored in SRCS-y\nSRCS-y := main.c flib.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/multi_process/l2fwd_fork/flib.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"flib.h\"\n\n#define SIG_PARENT_EXIT SIGUSR1\n\nstruct lcore_stat {\n\tpid_t pid; /**< pthread identifier */\n\tlcore_function_t *f; /**< function to call */\n\tvoid *arg; /**< argument of function */\n\tslave_exit_notify *cb_fn;\n} __rte_cache_aligned;\n\n\nstatic struct lcore_stat *core_cfg;\nstatic uint16_t *lcore_cfg = NULL;\n\n/* signal handler to be notified after parent leaves */\nstatic void\nsighand_parent_exit(int sig)\n{\n\tprintf(\"lcore = %u : Find parent leaves, sig=%d\\n\", rte_lcore_id(),\n\t\t\tsig);\n\tprintf(\"Child leaving\\n\");\n\texit(0);\n\n\treturn;\n}\n\n/**\n * Real function entrance ran in slave process\n **/\nstatic int\nslave_proc_func(void)\n{\n\tstruct rte_config *config;\n\tunsigned slave_id = rte_lcore_id();\n\tstruct lcore_stat *cfg = &core_cfg[slave_id];\n\n\tif (prctl(PR_SET_PDEATHSIG, SIG_PARENT_EXIT, 0, 0, 0, 0) != 0)\n\t\tprintf(\"Warning: Slave can't register for being notified in\"\n \"case master process exited\\n\");\n\telse {\n\t\tstruct sigaction act;\n\t\tmemset(&act, 0 , sizeof(act));\n\t\tact.sa_handler = sighand_parent_exit;\n\t\tif (sigaction(SIG_PARENT_EXIT, &act, NULL) != 0)\n\t\t\tprintf(\"Fail to register signal handler:%d\\n\", SIG_PARENT_EXIT);\n\t}\n\n\t/* Set slave process to SECONDARY to avoid operation like dev_start/stop etc */\n\tconfig = rte_eal_get_configuration();\n\tif (NULL == config)\n\t\tprintf(\"Warning:Can't get rte_config\\n\");\n\telse\n\t\tconfig->process_type = RTE_PROC_SECONDARY;\n\n\tprintf(\"Core %u is ready (pid=%d)\\n\", slave_id, (int)cfg->pid);\n\n\texit(cfg->f(cfg->arg));\n}\n\n/**\n * function entrance ran in master thread, which will spawn slave process and wait until\n * specific slave exited.\n **/\nstatic int\nlcore_func(void *arg __attribute__((unused)))\n{\n\tunsigned slave_id = rte_lcore_id();\n\tstruct lcore_stat *cfg = &core_cfg[slave_id];\n\tint pid, stat;\n\n\tif (rte_get_master_lcore() == slave_id)\n\t\treturn cfg->f(cfg->arg);\n\n\t/* fork a slave process */\n\tpid = fork();\n\n\tif (pid == -1) {\n\t\tprintf(\"Failed to fork\\n\");\n\t\treturn -1;\n\t} else if (pid == 0) /* child */\n\t\treturn slave_proc_func();\n\telse { /* parent */\n\t\tcfg->pid = pid;\n\n\t\twaitpid(pid, &stat, 0);\n\n\t\tcfg->pid = 0;\n\t\tcfg->f = NULL;\n\t\tcfg->arg = NULL;\n\t\t/* Notify slave's exit if applicable */\n\t\tif(cfg->cb_fn)\n\t\t\tcfg->cb_fn(slave_id, stat);\n\t\treturn stat;\n\t}\n}\n\nstatic int\nlcore_id_init(void)\n{\n\tint i;\n\t/* Setup lcore ID allocation map */\n\tlcore_cfg = rte_zmalloc(\"LCORE_ID_MAP\",\n\t\t\t\t\t\tsizeof(uint16_t) * RTE_MAX_LCORE,\n\t\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n\n\tif(lcore_cfg == NULL)\n\t\trte_panic(\"Failed to malloc\\n\");\n\n\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n\t\tif (rte_lcore_is_enabled(i))\n\t\t\tlcore_cfg[i] = 1;\n\t}\n\treturn 0;\n}\n\nint\nflib_assign_lcore_id(void)\n{\n\tunsigned i;\n\tint ret;\n\n\t/**\n\t * thread assigned a lcore id previously, or a slave thread. But still have\n\t * a bug here: If the core mask includes core 0, and that core call this\n\t * function, it still can get a new lcore id.\n\t **/\n\tif (rte_lcore_id() != 0)\n\t\treturn -1;\n\n\tdo {\n\t\t/* Find a lcore id not used yet, avoid to use lcore ID 0 */\n\t\tfor (i = 1; i < RTE_MAX_LCORE; i++) {\n\t\t\tif (lcore_cfg[i] == 0)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (i == RTE_MAX_LCORE)\n\t\t\treturn -1;\n\n\t\t/* Assign new lcore id to this thread */\n\n\t\tret = rte_atomic16_cmpset(&lcore_cfg[i], 0, 1);\n\t} while (unlikely(ret == 0));\n\n\tRTE_PER_LCORE(_lcore_id) = i;\n\treturn i;\n}\n\nvoid\nflib_free_lcore_id(unsigned lcore_id)\n{\n\t/* id is not valid or belongs to pinned core id */\n\tif (lcore_id >= RTE_MAX_LCORE || lcore_id == 0 ||\n\t\trte_lcore_is_enabled(lcore_id))\n\t\treturn;\n\n\tlcore_cfg[lcore_id] = 0;\n}\n\nint\nflib_register_slave_exit_notify(unsigned slave_id,\n\tslave_exit_notify *cb)\n{\n\tif (cb == NULL)\n\t\treturn -EFAULT;\n\n\tif (!rte_lcore_is_enabled(slave_id))\n\t\treturn -ENOENT;\n\n\tcore_cfg[slave_id].cb_fn = cb;\n\n\treturn 0;\n}\n\nenum slave_stat\nflib_query_slave_status(unsigned slave_id)\n{\n\tif (!rte_lcore_is_enabled(slave_id))\n\t\treturn ST_FREEZE;\n\t/* pid only be set when slave process spawned */\n\tif (core_cfg[slave_id].pid != 0)\n\t\treturn ST_RUN;\n\telse\n\t\treturn ST_IDLE;\n}\n\nint\nflib_remote_launch(lcore_function_t *f,\n\t\t\t\t\tvoid *arg, unsigned slave_id)\n{\n\tif (f == NULL)\n\t\treturn -1;\n\n\tif (!rte_lcore_is_enabled(slave_id))\n\t\treturn -1;\n\n\t/* Wait until specific lcore state change to WAIT */\n\trte_eal_wait_lcore(slave_id);\n\n\tcore_cfg[slave_id].f = f;\n\tcore_cfg[slave_id].arg = arg;\n\n\treturn rte_eal_remote_launch(lcore_func, NULL, slave_id);\n}\n\nint\nflib_mp_remote_launch(lcore_function_t *f, void *arg,\n\t\t\tenum rte_rmt_call_master_t call_master)\n{\n\tint i;\n\n\tRTE_LCORE_FOREACH_SLAVE(i) {\n\t\tcore_cfg[i].arg = arg;\n\t\tcore_cfg[i].f = f;\n\t}\n\n\treturn rte_eal_mp_remote_launch(lcore_func, NULL, call_master);\n}\n\nint\nflib_init(void)\n{\n\tif ((core_cfg = rte_zmalloc(\"core_cfg\",\n\t\tsizeof(struct lcore_stat) * RTE_MAX_LCORE,\n\t\tRTE_CACHE_LINE_SIZE)) == NULL ) {\n\t\tprintf(\"rte_zmalloc failed\\n\");\n\t\treturn -1;\n\t}\n\n\tif (lcore_id_init() != 0) {\n\t\tprintf(\"lcore_id_init failed\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/multi_process/l2fwd_fork/flib.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __FLIB_H\n#define __FLIB_H\n\n/* callback function pointer when specific slave leaves */\ntypedef void (slave_exit_notify)(unsigned slaveid, int stat);\n\nenum slave_stat{\n\tST_FREEZE = 1,\n\tST_IDLE,\n\tST_RUN,\n\tST_ZOMBIE,\t/* Not implemented yet */\n};\n\n/**\n * Initialize the fork lib.\n *\n * @return\n * - 0 : fork lib initialized successfully\n * - -1 : fork lib initialized failed\n */\nint flib_init(void);\n\n/**\n * Check that every SLAVE lcores are in WAIT state, then call\n * flib_remote_launch() for all of them. If call_master is true\n * (set to CALL_MASTER), also call the function on the master lcore.\n *\n * @param f:\n *\tfunction pointer need to run\n * @param arg:\n *\targument for f to carry\n * @param call_master\n *\t- SKIP_MASTER : only launch function on slave lcores\n *\t- CALL_MASTER : launch function on master and slave lcores\n * @return\n * - 0 : function execute successfully\n * - -1 : function execute failed\n */\nint flib_mp_remote_launch(lcore_function_t *f,\n\t\tvoid *arg, enum rte_rmt_call_master_t call_master);\n\n/**\n * Send a message to a slave lcore identified by slave_id to call a\n * function f with argument arg.\n *\n * @param f:\n *\tfunction pointer need to run\n * @param arg:\n *\targument for f to carry\n * @param slave_id\n *\tslave lcore id to run on\n * @return\n * - 0 : function execute successfully\n * - -1 : function execute failed\n */\nint flib_remote_launch(lcore_function_t *f,\n\t\t\t\t\tvoid *arg, unsigned slave_id);\n\n/**\n * Query the running stat for specific slave, wont' work in with master id\n *\n * @param slave_id:\n *\tlcore id which should not be master id\n * @return\n * - ST_FREEZE : lcore is not in enabled core mask\n *\t - ST_IDLE : lcore is idle\n * - ST_RUN : lcore is running something\n */\nenum slave_stat\nflib_query_slave_status(unsigned slave_id);\n\n/**\n * Register a callback function to be notified in case specific slave exit.\n *\n * @param slave_id:\n *\tlcore id which should not be master id\n * @param cb:\n *\tcallback pointer to register\n * @return\n * - 0 : function execute successfully\n * - -EFAULT : argument error\n * - -ENOENT : slave_id not correct\n */\nint flib_register_slave_exit_notify(unsigned slave_id,\n\tslave_exit_notify *cb);\n\n/**\n * Assign a lcore ID to non-slave thread. Non-slave thread refers to thread that\n * not created by function rte_eal_remote_launch or rte_eal_mp_remote_launch.\n * These threads can either bind lcore or float among differnt lcores.\n * This lcore ID will be unique in multi-thread or multi-process DPDK running\n * environment, then it can benefit from using the cache mechanism provided in\n * mempool library.\n * After calling successfully, use rte_lcore_id() to get the assigned lcore ID, but\n * other lcore funtions can't guarantee to work correctly.\n *\n * @return\n * - -1 : can't assign a lcore id with 3 possibilities.\n * - it's not non-slave thread.\n * - it had assign a lcore id previously\n * - the lcore id is running out.\n * - > 0 : the assigned lcore id.\n */\nint flib_assign_lcore_id(void);\n\n/**\n * Free the lcore_id that assigned in flib_assign_lcore_id().\n * call it in case non-slave thread is leaving or left.\n *\n * @param lcore_id\n * The identifier of the lcore, which MUST be between 1 and\n * RTE_MAX_LCORE-1.\n */\nvoid flib_free_lcore_id(unsigned lcore_id);\n\n#endif /* __FLIB_H */\n" }, { "path": "examples/multi_process/l2fwd_fork/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#define _GNU_SOURCE\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"flib.h\"\n\n#define RTE_LOGTYPE_L2FWD RTE_LOGTYPE_USER1\n#define MBUF_NAME\t\"mbuf_pool_%d\"\n#define MBUF_SIZE\t\\\n(RTE_MBUF_DEFAULT_DATAROOM + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)\n#define NB_MBUF 8192\n#define RING_MASTER_NAME\t\"l2fwd_ring_m2s_\"\n#define RING_SLAVE_NAME\t\t\"l2fwd_ring_s2m_\"\n#define MAX_NAME_LEN\t32\n/* RECREATE flag indicate needs initialize resource and launch slave_core again */\n#define SLAVE_RECREATE_FLAG 0x1\n/* RESTART flag indicate needs restart port and send START command again */\n#define SLAVE_RESTART_FLAG 0x2\n#define INVALID_MAPPING_ID\t((unsigned)LCORE_ID_ANY)\n/* Maximum message buffer per slave */\n#define NB_CORE_MSGBUF\t32\nenum l2fwd_cmd{\n\tCMD_START,\n\tCMD_STOP,\n};\n\n#define MAX_PKT_BURST 32\n#define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\nstatic uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;\nstatic uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;\n\n/* ethernet addresses of ports */\nstatic struct ether_addr l2fwd_ports_eth_addr[RTE_MAX_ETHPORTS];\n\n/* mask of enabled ports */\nstatic uint32_t l2fwd_enabled_port_mask = 0;\n\n/* list of enabled ports */\nstatic uint32_t l2fwd_dst_ports[RTE_MAX_ETHPORTS];\n\nstatic unsigned int l2fwd_rx_queue_per_lcore = 1;\n\nstruct mbuf_table {\n\tunsigned len;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST];\n};\n\n#define MAX_RX_QUEUE_PER_LCORE 16\n#define MAX_TX_QUEUE_PER_PORT 16\nstruct lcore_queue_conf {\n\tunsigned n_rx_port;\n\tunsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE];\n\tstruct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];\n\n} __rte_cache_aligned;\nstruct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];\n\nstruct lcore_resource_struct {\n\tint enabled;\t/* Only set in case this lcore involved into packet forwarding */\n\tint flags; \t /* Set only slave need to restart or recreate */\n\tunsigned lcore_id; /* lcore ID */\n\tunsigned pair_id; \t/* dependency lcore ID on port */\n\tchar ring_name[2][MAX_NAME_LEN];\n\t/* ring[0] for master send cmd, slave read */\n\t/* ring[1] for slave send ack, master read */\n\tstruct rte_ring *ring[2];\n\tint port_num;\t\t\t\t\t/* Total port numbers */\n\tuint8_t port[RTE_MAX_ETHPORTS]; /* Port id for that lcore to receive packets */\n}__attribute__((packed)) __rte_cache_aligned;\n\nstatic struct lcore_resource_struct lcore_resource[RTE_MAX_LCORE];\nstatic struct rte_mempool *message_pool;\nstatic rte_spinlock_t res_lock = RTE_SPINLOCK_INITIALIZER;\n/* use floating processes */\nstatic int float_proc = 0;\n/* Save original cpu affinity */\nstruct cpu_aff_arg{\n\tcpu_set_t set;\n\tsize_t size;\n}cpu_aff;\n\nstatic const struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\nstatic struct rte_mempool * l2fwd_pktmbuf_pool[RTE_MAX_ETHPORTS];\n\n/* Per-port statistics struct */\nstruct l2fwd_port_statistics {\n\tuint64_t tx;\n\tuint64_t rx;\n\tuint64_t dropped;\n} __rte_cache_aligned;\nstruct l2fwd_port_statistics *port_statistics;\n/**\n * pointer to lcore ID mapping array, used to return lcore id in case slave\n * process exited unexpectedly, use only floating process option applied\n **/\nunsigned *mapping_id;\n\n/* A tsc-based timer responsible for triggering statistics printout */\n#define TIMER_MILLISECOND 2000000ULL /* around 1ms at 2 Ghz */\n#define MAX_TIMER_PERIOD 86400 /* 1 day max */\nstatic int64_t timer_period = 10 * TIMER_MILLISECOND * 1000; /* default period is 10 seconds */\n\nstatic int l2fwd_launch_one_lcore(void *dummy);\n\n/* Print out statistics on packets dropped */\nstatic void\nprint_stats(void)\n{\n\tuint64_t total_packets_dropped, total_packets_tx, total_packets_rx;\n\tunsigned portid;\n\n\ttotal_packets_dropped = 0;\n\ttotal_packets_tx = 0;\n\ttotal_packets_rx = 0;\n\n\tconst char clr[] = { 27, '[', '2', 'J', '\\0' };\n\tconst char topLeft[] = { 27, '[', '1', ';', '1', 'H','\\0' };\n\n\t\t/* Clear screen and move to top left */\n\tprintf(\"%s%s\", clr, topLeft);\n\n\tprintf(\"\\nPort statistics ====================================\");\n\n\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t/* skip disabled ports */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\t\tprintf(\"\\nStatistics for port %u ------------------------------\"\n\t\t\t \"\\nPackets sent: %24\"PRIu64\n\t\t\t \"\\nPackets received: %20\"PRIu64\n\t\t\t \"\\nPackets dropped: %21\"PRIu64,\n\t\t\t portid,\n\t\t\t port_statistics[portid].tx,\n\t\t\t port_statistics[portid].rx,\n\t\t\t port_statistics[portid].dropped);\n\n\t\ttotal_packets_dropped += port_statistics[portid].dropped;\n\t\ttotal_packets_tx += port_statistics[portid].tx;\n\t\ttotal_packets_rx += port_statistics[portid].rx;\n\t}\n\tprintf(\"\\nAggregate statistics ===============================\"\n\t\t \"\\nTotal packets sent: %18\"PRIu64\n\t\t \"\\nTotal packets received: %14\"PRIu64\n\t\t \"\\nTotal packets dropped: %15\"PRIu64,\n\t\t total_packets_tx,\n\t\t total_packets_rx,\n\t\t total_packets_dropped);\n\tprintf(\"\\n====================================================\\n\");\n}\n\nstatic int\nclear_cpu_affinity(void)\n{\n\tint s;\n\n\ts = sched_setaffinity(0, cpu_aff.size, &cpu_aff.set);\n\tif (s != 0) {\n\t\tprintf(\"sched_setaffinity failed:%s\\n\", strerror(errno));\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nget_cpu_affinity(void)\n{\n\tint s;\n\n\tcpu_aff.size = sizeof(cpu_set_t);\n\tCPU_ZERO(&cpu_aff.set);\n\n\ts = sched_getaffinity(0, cpu_aff.size, &cpu_aff.set);\n\tif (s != 0) {\n\t\tprintf(\"sched_getaffinity failed:%s\\n\", strerror(errno));\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/**\n * This fnciton demonstrates the approach to create ring in first instance\n * or re-attach an existed ring in later instance.\n **/\nstatic struct rte_ring *\ncreate_ring(const char *name, unsigned count,\n\t\t\t\t\tint socket_id,unsigned flags)\n{\n\tstruct rte_ring *ring;\n\n\tif (name == NULL)\n\t\treturn NULL;\n\n\t/* If already create, just attached it */\n\tif (likely((ring = rte_ring_lookup(name)) != NULL))\n\t\treturn ring;\n\n\t/* First call it, create one */\n\treturn rte_ring_create(name, count, socket_id, flags);\n}\n\n/* Malloc with rte_malloc on structures that shared by master and slave */\nstatic int\nl2fwd_malloc_shared_struct(void)\n{\n\tport_statistics = rte_zmalloc(\"port_stat\",\n\t\t\t\t\t\tsizeof(struct l2fwd_port_statistics) * RTE_MAX_ETHPORTS,\n\t\t\t\t\t\t0);\n\tif (port_statistics == NULL)\n\t\treturn -1;\n\n\t/* allocate mapping_id array */\n\tif (float_proc) {\n\t\tint i;\n\t\tmapping_id = rte_malloc(\"mapping_id\", sizeof(unsigned) * RTE_MAX_LCORE,\n\t\t\t\t\t\t\t\t0);\n\n\t\tif (mapping_id == NULL)\n\t\t\treturn -1;\n\n\t\tfor (i = 0 ;i < RTE_MAX_LCORE; i++)\n\t\t\tmapping_id[i] = INVALID_MAPPING_ID;\n\t}\n\treturn 0;\n}\n\n/* Create ring which used for communicate among master and slave */\nstatic int\ncreate_ms_ring(unsigned slaveid)\n{\n\tunsigned flag = RING_F_SP_ENQ | RING_F_SC_DEQ;\n\tstruct lcore_resource_struct *res = &lcore_resource[slaveid];\n\tunsigned socketid = rte_socket_id();\n\n\t/* Always assume create ring on master socket_id */\n\t/* Default only create a ring size 32 */\n\tsnprintf(res->ring_name[0], MAX_NAME_LEN, \"%s%u\",\n\t\t\tRING_MASTER_NAME, slaveid);\n\tif ((res->ring[0] = create_ring(res->ring_name[0], NB_CORE_MSGBUF,\n\t\t\t\tsocketid, flag)) == NULL) {\n\t\tprintf(\"Create m2s ring %s failed\\n\", res->ring_name[0]);\n\t\treturn -1;\n\t}\n\n\tsnprintf(res->ring_name[1], MAX_NAME_LEN, \"%s%u\",\n\t\t\tRING_SLAVE_NAME, slaveid);\n\tif ((res->ring[1] = create_ring(res->ring_name[1], NB_CORE_MSGBUF,\n\t\tsocketid, flag)) == NULL) {\n\t\tprintf(\"Create s2m ring %s failed\\n\", res->ring_name[1]);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* send command to pair in paired master and slave ring */\nstatic inline int\nsendcmd(unsigned slaveid, enum l2fwd_cmd cmd, int is_master)\n{\n\tstruct lcore_resource_struct *res = &lcore_resource[slaveid];\n\tvoid *msg;\n\tint fd = !is_master;\n\n\t/* Only check master, it must be enabled and running if it is slave */\n\tif (is_master && !res->enabled)\n\t\treturn -1;\n\n\tif (res->ring[fd] == NULL)\n\t\treturn -1;\n\n\tif (rte_mempool_get(message_pool, &msg) < 0) {\n\t\tprintf(\"Error to get message buffer\\n\");\n\t\treturn -1;\n\t}\n\n\t*(enum l2fwd_cmd *)msg = cmd;\n\n\tif (rte_ring_enqueue(res->ring[fd], msg) != 0) {\n\t\tprintf(\"Enqueue error\\n\");\n\t\trte_mempool_put(message_pool, msg);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* Get command from pair in paired master and slave ring */\nstatic inline int\ngetcmd(unsigned slaveid, enum l2fwd_cmd *cmd, int is_master)\n{\n\tstruct lcore_resource_struct *res = &lcore_resource[slaveid];\n\tvoid *msg;\n\tint fd = !!is_master;\n\tint ret;\n\t/* Only check master, it must be enabled and running if it is slave */\n\tif (is_master && (!res->enabled))\n\t\treturn -1;\n\n\tif (res->ring[fd] == NULL)\n\t\treturn -1;\n\n\tret = rte_ring_dequeue(res->ring[fd], &msg);\n\n\tif (ret == 0) {\n\t\t*cmd = *(enum l2fwd_cmd *)msg;\n\t\trte_mempool_put(message_pool, msg);\n\t}\n\treturn ret;\n}\n\n/* Master send command to slave and wait until ack received or error met */\nstatic int\nmaster_sendcmd_with_ack(unsigned slaveid, enum l2fwd_cmd cmd)\n{\n\tenum l2fwd_cmd ack_cmd;\n\tint ret = -1;\n\n\tif (sendcmd(slaveid, cmd, 1) != 0)\n\t\trte_exit(EXIT_FAILURE, \"Failed to send message\\n\");\n\n\t/* Get ack */\n\twhile (1) {\n\t\tret = getcmd(slaveid, &ack_cmd, 1);\n\t\tif (ret == 0 && cmd == ack_cmd)\n\t\t\tbreak;\n\n\t\t/* If slave not running yet, return an error */\n\t\tif (flib_query_slave_status(slaveid) != ST_RUN) {\n\t\t\tret = -ENOENT;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn ret;\n}\n\n/* restart all port that assigned to that slave lcore */\nstatic int\nreset_slave_all_ports(unsigned slaveid)\n{\n\tstruct lcore_resource_struct *slave = &lcore_resource[slaveid];\n\tint i, ret = 0;\n\n\t/* stop/start port */\n\tfor (i = 0; i < slave->port_num; i++) {\n\t\tchar buf_name[RTE_MEMPOOL_NAMESIZE];\n\t\tstruct rte_mempool *pool;\n\t\tprintf(\"Stop port :%d\\n\", slave->port[i]);\n\t\trte_eth_dev_stop(slave->port[i]);\n\t\tsnprintf(buf_name, RTE_MEMPOOL_NAMESIZE, MBUF_NAME, slave->port[i]);\n\t\tpool = rte_mempool_lookup(buf_name);\n\t\tif (pool)\n\t\t\tprintf(\"Port %d mempool free object is %u(%u)\\n\", slave->port[i],\n\t\t\t\trte_mempool_count(pool), (unsigned)NB_MBUF);\n\t\telse\n\t\t\tprintf(\"Can't find mempool %s\\n\", buf_name);\n\n\t\tprintf(\"Start port :%d\\n\", slave->port[i]);\n\t\tret = rte_eth_dev_start(slave->port[i]);\n\t\tif (ret != 0)\n\t\t\tbreak;\n\t}\n\treturn ret;\n}\n\nstatic int\nreset_shared_structures(unsigned slaveid)\n{\n\tint ret;\n\t/* Only port are shared resource here */\n\tret = reset_slave_all_ports(slaveid);\n\n\treturn ret;\n}\n\n/**\n * Call this function to re-create resource that needed for slave process that\n * exited in last instance\n **/\nstatic int\ninit_slave_res(unsigned slaveid)\n{\n\tstruct lcore_resource_struct *slave = &lcore_resource[slaveid];\n\tenum l2fwd_cmd cmd;\n\n\tif (!slave->enabled) {\n\t\tprintf(\"Something wrong with lcore=%u enabled=%d\\n\",slaveid,\n\t\t\tslave->enabled);\n\t\treturn -1;\n\t}\n\n\t/* Initialize ring */\n\tif (create_ms_ring(slaveid) != 0)\n\t\trte_exit(EXIT_FAILURE, \"failed to create ring for slave %u\\n\",\n\t\t\t\tslaveid);\n\n\t/* drain un-read buffer if have */\n\twhile (getcmd(slaveid, &cmd, 1) == 0);\n\twhile (getcmd(slaveid, &cmd, 0) == 0);\n\n\treturn 0;\n}\n\nstatic int\nrecreate_one_slave(unsigned slaveid)\n{\n\tint ret = 0;\n\t/* Re-initialize resource for stalled slave */\n\tif ((ret = init_slave_res(slaveid)) != 0) {\n\t\tprintf(\"Init slave=%u failed\\n\", slaveid);\n\t\treturn ret;\n\t}\n\n\tif ((ret = flib_remote_launch(l2fwd_launch_one_lcore, NULL, slaveid))\n\t\t!= 0)\n\t\tprintf(\"Launch slave %u failed\\n\", slaveid);\n\n\treturn ret;\n}\n\n/**\n * remapping resource belong to slave_id to new lcore that gets from flib_assign_lcore_id(),\n * used only floating process option applied.\n *\n * @param slaveid\n * original lcore_id that apply for remapping\n */\nstatic void\nremapping_slave_resource(unsigned slaveid, unsigned map_id)\n{\n\n\t/* remapping lcore_resource */\n\tmemcpy(&lcore_resource[map_id], &lcore_resource[slaveid],\n\t\t\tsizeof(struct lcore_resource_struct));\n\n\t/* remapping lcore_queue_conf */\n\tmemcpy(&lcore_queue_conf[map_id], &lcore_queue_conf[slaveid],\n\t\t\tsizeof(struct lcore_queue_conf));\n}\n\nstatic int\nreset_pair(unsigned slaveid, unsigned pairid)\n{\n\tint ret;\n\tif ((ret = reset_shared_structures(slaveid)) != 0)\n\t\tgoto back;\n\n\tif((ret = reset_shared_structures(pairid)) != 0)\n\t\tgoto back;\n\n\tif (float_proc) {\n\t\tunsigned map_id = mapping_id[slaveid];\n\n\t\tif (map_id != INVALID_MAPPING_ID) {\n\t\t\tprintf(\"%u return mapping id %u\\n\", slaveid, map_id);\n\t\t\tflib_free_lcore_id(map_id);\n\t\t\tmapping_id[slaveid] = INVALID_MAPPING_ID;\n\t\t}\n\n\t\tmap_id = mapping_id[pairid];\n\t\tif (map_id != INVALID_MAPPING_ID) {\n\t\t\tprintf(\"%u return mapping id %u\\n\", pairid, map_id);\n\t\t\tflib_free_lcore_id(map_id);\n\t\t\tmapping_id[pairid] = INVALID_MAPPING_ID;\n\t\t}\n\t}\n\n\tif((ret = recreate_one_slave(slaveid)) != 0)\n\t\tgoto back;\n\n\tret = recreate_one_slave(pairid);\n\nback:\n\treturn ret;\n}\n\nstatic void\nslave_exit_cb(unsigned slaveid, __attribute__((unused))int stat)\n{\n\tstruct lcore_resource_struct *slave = &lcore_resource[slaveid];\n\n\tprintf(\"Get slave %u leave info\\n\", slaveid);\n\tif (!slave->enabled) {\n\t\tprintf(\"Lcore=%u not registered for it's exit\\n\", slaveid);\n\t\treturn;\n\t}\n\trte_spinlock_lock(&res_lock);\n\n\t/* Change the state and wait master to start them */\n\tslave->flags = SLAVE_RECREATE_FLAG;\n\n\trte_spinlock_unlock(&res_lock);\n}\n\n/* Send the packet on an output interface */\nstatic int\nl2fwd_send_burst(struct lcore_queue_conf *qconf, unsigned n, uint8_t port)\n{\n\tstruct rte_mbuf **m_table;\n\tunsigned ret;\n\tunsigned queueid =0;\n\n\tm_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;\n\n\tret = rte_eth_tx_burst(port, (uint16_t) queueid, m_table, (uint16_t) n);\n\tport_statistics[port].tx += ret;\n\tif (unlikely(ret < n)) {\n\t\tport_statistics[port].dropped += (n - ret);\n\t\tdo {\n\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t} while (++ret < n);\n\t}\n\n\treturn 0;\n}\n\n/* Send the packet on an output interface */\nstatic int\nl2fwd_send_packet(struct rte_mbuf *m, uint8_t port)\n{\n\tunsigned lcore_id, len;\n\tstruct lcore_queue_conf *qconf;\n\n\tlcore_id = rte_lcore_id();\n\n\tqconf = &lcore_queue_conf[lcore_id];\n\tlen = qconf->tx_mbufs[port].len;\n\tqconf->tx_mbufs[port].m_table[len] = m;\n\tlen++;\n\n\t/* enough pkts to be sent */\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tl2fwd_send_burst(qconf, MAX_PKT_BURST, port);\n\t\tlen = 0;\n\t}\n\n\tqconf->tx_mbufs[port].len = len;\n\treturn 0;\n}\n\nstatic void\nl2fwd_simple_forward(struct rte_mbuf *m, unsigned portid)\n{\n\tstruct ether_hdr *eth;\n\tvoid *tmp;\n\tunsigned dst_port;\n\n\tdst_port = l2fwd_dst_ports[portid];\n\teth = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\t/* 02:00:00:00:00:xx */\n\ttmp = ð->d_addr.addr_bytes[0];\n\t*((uint64_t *)tmp) = 0x000000000002 + ((uint64_t)dst_port << 40);\n\n\t/* src addr */\n\tether_addr_copy(&l2fwd_ports_eth_addr[dst_port], ð->s_addr);\n\n\tl2fwd_send_packet(m, (uint8_t) dst_port);\n}\n\n/* main processing loop */\nstatic void\nl2fwd_main_loop(void)\n{\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_mbuf *m;\n\tunsigned lcore_id;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc;\n\tunsigned i, j, portid, nb_rx;\n\tstruct lcore_queue_conf *qconf;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\tprev_tsc = 0;\n\n\tlcore_id = rte_lcore_id();\n\n\tqconf = &lcore_queue_conf[lcore_id];\n\n\tif (qconf->n_rx_port == 0) {\n\t\tRTE_LOG(INFO, L2FWD, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn;\n\t}\n\n\tRTE_LOG(INFO, L2FWD, \"entering main loop on lcore %u\\n\", lcore_id);\n\n\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\t\tportid = qconf->rx_port_list[i];\n\t\tRTE_LOG(INFO, L2FWD, \" -- lcoreid=%u portid=%u\\n\", lcore_id,\n\t\t\tportid);\n\t}\n\n\twhile (1) {\n\t\tenum l2fwd_cmd cmd;\n\t\tcur_tsc = rte_rdtsc();\n\n\t\tif (unlikely(getcmd(lcore_id, &cmd, 0) == 0)) {\n\t\t\tsendcmd(lcore_id, cmd, 0);\n\n\t\t\t/* If get stop command, stop forwarding and exit */\n\t\t\tif (cmd == CMD_STOP) {\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\n\t\t/*\n\t\t * TX burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {\n\t\t\t\tif (qconf->tx_mbufs[portid].len == 0)\n\t\t\t\t\tcontinue;\n\t\t\t\tl2fwd_send_burst(&lcore_queue_conf[lcore_id],\n\t\t\t\t\t\t qconf->tx_mbufs[portid].len,\n\t\t\t\t\t\t (uint8_t) portid);\n\t\t\t\tqconf->tx_mbufs[portid].len = 0;\n\t\t\t}\n\t\t}\n\n\t\t/*\n\t\t * Read packet from RX queues\n\t\t */\n\t\tfor (i = 0; i < qconf->n_rx_port; i++) {\n\n\t\t\tportid = qconf->rx_port_list[i];\n\t\t\tnb_rx = rte_eth_rx_burst((uint8_t) portid, 0,\n\t\t\t\t\t\t pkts_burst, MAX_PKT_BURST);\n\n\t\t\tport_statistics[portid].rx += nb_rx;\n\n\t\t\tfor (j = 0; j < nb_rx; j++) {\n\t\t\t\tm = pkts_burst[j];\n\t\t\t\trte_prefetch0(rte_pktmbuf_mtod(m, void *));\n\t\t\t\tl2fwd_simple_forward(m, portid);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic int\nl2fwd_launch_one_lcore(__attribute__((unused)) void *dummy)\n{\n\tunsigned lcore_id = rte_lcore_id();\n\n\tif (float_proc) {\n\t\tunsigned flcore_id;\n\n\t\t/* Change it to floating process, also change it's lcore_id */\n\t\tclear_cpu_affinity();\n\t\tRTE_PER_LCORE(_lcore_id) = 0;\n\t\t/* Get a lcore_id */\n\t\tif (flib_assign_lcore_id() < 0 ) {\n\t\t\tprintf(\"flib_assign_lcore_id failed\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tflcore_id = rte_lcore_id();\n\t\t/* Set mapping id, so master can return it after slave exited */\n\t\tmapping_id[lcore_id] = flcore_id;\n\t\tprintf(\"Org lcore_id = %u, cur lcore_id = %u\\n\",\n\t\t\t\tlcore_id, flcore_id);\n\t\tremapping_slave_resource(lcore_id, flcore_id);\n\t}\n\n\tl2fwd_main_loop();\n\n\t/* return lcore_id before return */\n\tif (float_proc) {\n\t\tflib_free_lcore_id(rte_lcore_id());\n\t\tmapping_id[lcore_id] = INVALID_MAPPING_ID;\n\t}\n\treturn 0;\n}\n\n/* display usage */\nstatic void\nl2fwd_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK -s COREMASK [-q NQ] -f\\n\"\n\t \" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\"\n\t \" -q NQ: number of queue (=ports) per lcore (default is 1)\\n\"\n\t \" -f use floating process which won't bind to any core to run\\n\"\n\t\t \" -T PERIOD: statistics will be refreshed each PERIOD seconds (0 to disable, 10 default, 86400 maximum)\\n\",\n\t prgname);\n}\n\nstatic int\nl2fwd_parse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\nstatic unsigned int\nl2fwd_parse_nqueue(const char *q_arg)\n{\n\tchar *end = NULL;\n\tunsigned long n;\n\n\t/* parse hexadecimal string */\n\tn = strtoul(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn 0;\n\tif (n == 0)\n\t\treturn 0;\n\tif (n >= MAX_RX_QUEUE_PER_LCORE)\n\t\treturn 0;\n\n\treturn n;\n}\n\nstatic int\nl2fwd_parse_timer_period(const char *q_arg)\n{\n\tchar *end = NULL;\n\tint n;\n\n\t/* parse number string */\n\tn = strtol(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\tif (n >= MAX_TIMER_PERIOD)\n\t\treturn -1;\n\n\treturn n;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nl2fwd_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{NULL, 0, 0, 0}\n\t};\n\tint has_pmask = 0;\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:q:T:f\",\n\t\t\t\t lgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tl2fwd_enabled_port_mask = l2fwd_parse_portmask(optarg);\n\t\t\tif (l2fwd_enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tl2fwd_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\thas_pmask = 1;\n\t\t\tbreak;\n\n\t\t/* nqueue */\n\t\tcase 'q':\n\t\t\tl2fwd_rx_queue_per_lcore = l2fwd_parse_nqueue(optarg);\n\t\t\tif (l2fwd_rx_queue_per_lcore == 0) {\n\t\t\t\tprintf(\"invalid queue number\\n\");\n\t\t\t\tl2fwd_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* timer period */\n\t\tcase 'T':\n\t\t\ttimer_period = l2fwd_parse_timer_period(optarg) * 1000 * TIMER_MILLISECOND;\n\t\t\tif (timer_period < 0) {\n\t\t\t\tprintf(\"invalid timer period\\n\");\n\t\t\t\tl2fwd_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* use floating process */\n\t\tcase 'f':\n\t\t\tfloat_proc = 1;\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tl2fwd_usage(prgname);\n\t\t\treturn -1;\n\n\t\tdefault:\n\t\t\tl2fwd_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tif (!has_pmask) {\n\t\tl2fwd_usage(prgname);\n\t\treturn -1;\n\t}\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\nint\nmain(int argc, char **argv)\n{\n\tstruct lcore_queue_conf *qconf;\n\tstruct rte_eth_dev_info dev_info;\n\tint ret;\n\tuint8_t nb_ports;\n\tuint8_t nb_ports_available;\n\tuint8_t portid, last_port;\n\tunsigned rx_lcore_id;\n\tunsigned nb_ports_in_mask = 0;\n\tunsigned i;\n\tint flags = 0;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc, timer_tsc;\n\n\t/* Save cpu_affinity first, restore it in case it's floating process option */\n\tif (get_cpu_affinity() != 0)\n\t\trte_exit(EXIT_FAILURE, \"get_cpu_affinity error\\n\");\n\n\t/* Also tries to set cpu affinity to detect whether it will fail in child process */\n\tif(clear_cpu_affinity() != 0)\n\t\trte_exit(EXIT_FAILURE, \"clear_cpu_affinity error\\n\");\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid EAL arguments\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse application arguments (after the EAL ones) */\n\tret = l2fwd_parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid L2FWD arguments\\n\");\n\n\t/*flib init */\n\tif (flib_init() != 0)\n\t\trte_exit(EXIT_FAILURE, \"flib init error\");\n\n\t/**\n\t * Allocated structures that slave lcore would change. For those that slaves are\n\t * read only, needn't use malloc to share and global or static variables is ok since\n\t * slave inherit all the knowledge that master initialized.\n\t **/\n\tif (l2fwd_malloc_shared_struct() != 0)\n\t\trte_exit(EXIT_FAILURE, \"malloc mem failed\\n\");\n\n\t/* Initialize lcore_resource structures */\n\tmemset(lcore_resource, 0, sizeof(lcore_resource));\n\tfor (i = 0; i < RTE_MAX_LCORE; i++)\n\t\tlcore_resource[i].lcore_id = i;\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports == 0)\n\t\trte_exit(EXIT_FAILURE, \"No Ethernet ports - bye\\n\");\n\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\t/* create the mbuf pool */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\t\tchar buf_name[RTE_MEMPOOL_NAMESIZE];\n\t\tflags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;\n\t\tsnprintf(buf_name, RTE_MEMPOOL_NAMESIZE, MBUF_NAME, portid);\n\t\tl2fwd_pktmbuf_pool[portid] =\n\t\t\trte_mempool_create(buf_name, NB_MBUF,\n\t\t\t\t\t MBUF_SIZE, 32,\n\t\t\t\t\t sizeof(struct rte_pktmbuf_pool_private),\n\t\t\t\t\t rte_pktmbuf_pool_init, NULL,\n\t\t\t\t\t rte_pktmbuf_init, NULL,\n\t\t\t\t\t rte_socket_id(), flags);\n\t\tif (l2fwd_pktmbuf_pool[portid] == NULL)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot init mbuf pool\\n\");\n\n\t\tprintf(\"Create mbuf %s\\n\", buf_name);\n\t}\n\n\t/* reset l2fwd_dst_ports */\n\tfor (portid = 0; portid < RTE_MAX_ETHPORTS; portid++)\n\t\tl2fwd_dst_ports[portid] = 0;\n\tlast_port = 0;\n\n\t/*\n\t * Each logical core is assigned a dedicated TX queue on each port.\n\t */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\n\t\tif (nb_ports_in_mask % 2) {\n\t\t\tl2fwd_dst_ports[portid] = last_port;\n\t\t\tl2fwd_dst_ports[last_port] = portid;\n\t\t}\n\t\telse\n\t\t\tlast_port = portid;\n\n\t\tnb_ports_in_mask++;\n\n\t\trte_eth_dev_info_get(portid, &dev_info);\n\t}\n\tif (nb_ports_in_mask % 2) {\n\t\tprintf(\"Notice: odd number of ports in portmask.\\n\");\n\t\tl2fwd_dst_ports[last_port] = last_port;\n\t}\n\n\trx_lcore_id = 0;\n\tqconf = NULL;\n\n\t/* Initialize the port/queue configuration of each logical core */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tstruct lcore_resource_struct *res;\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\n\t\t/* get the lcore_id for this port */\n\t\t/* skip master lcore */\n\t\twhile (rte_lcore_is_enabled(rx_lcore_id) == 0 ||\n\t\t\t rte_get_master_lcore() == rx_lcore_id ||\n\t\t lcore_queue_conf[rx_lcore_id].n_rx_port ==\n\t\t l2fwd_rx_queue_per_lcore) {\n\n\t\t\trx_lcore_id++;\n\t\t\tif (rx_lcore_id >= RTE_MAX_LCORE)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Not enough cores\\n\");\n\t\t}\n\n\t\tif (qconf != &lcore_queue_conf[rx_lcore_id])\n\t\t\t/* Assigned a new logical core in the loop above. */\n\t\t\tqconf = &lcore_queue_conf[rx_lcore_id];\n\n\t\tqconf->rx_port_list[qconf->n_rx_port] = portid;\n\t\tqconf->n_rx_port++;\n\n\t\t/* Save the port resource info into lcore_resource strucutres */\n\t\tres = &lcore_resource[rx_lcore_id];\n\t\tres->enabled = 1;\n\t\tres->port[res->port_num++] = portid;\n\n\t\tprintf(\"Lcore %u: RX port %u\\n\", rx_lcore_id, (unsigned) portid);\n\t}\n\n\tnb_ports_available = nb_ports;\n\n\t/* Initialise each port */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"Skipping disabled port %u\\n\", (unsigned) portid);\n\t\t\tnb_ports_available--;\n\t\t\tcontinue;\n\t\t}\n\t\t/* init port */\n\t\tprintf(\"Initializing port %u... \", (unsigned) portid);\n\t\tfflush(stdout);\n\t\tret = rte_eth_dev_configure(portid, 1, 1, &port_conf);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot configure device: err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\trte_eth_macaddr_get(portid,&l2fwd_ports_eth_addr[portid]);\n\n\t\t/* init one RX queue */\n\t\tfflush(stdout);\n\t\tret = rte_eth_rx_queue_setup(portid, 0, nb_rxd,\n\t\t\t\t\t rte_eth_dev_socket_id(portid),\n\t\t\t\t\t NULL,\n\t\t\t\t\t l2fwd_pktmbuf_pool[portid]);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_rx_queue_setup:err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\t/* init one TX queue on each port */\n\t\tfflush(stdout);\n\t\tret = rte_eth_tx_queue_setup(portid, 0, nb_txd,\n\t\t\t\trte_eth_dev_socket_id(portid),\n\t\t\t\tNULL);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup:err=%d, port=%u\\n\",\n\t\t\t\tret, (unsigned) portid);\n\n\t\t/* Start device */\n\t\tret = rte_eth_dev_start(portid);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"rte_eth_dev_start:err=%d, port=%u\\n\",\n\t\t\t\t ret, (unsigned) portid);\n\n\t\tprintf(\"done: \\n\");\n\n\t\trte_eth_promiscuous_enable(portid);\n\n\t\tprintf(\"Port %u, MAC address: %02X:%02X:%02X:%02X:%02X:%02X\\n\\n\",\n\t\t\t\t(unsigned) portid,\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[0],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[1],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[2],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[3],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[4],\n\t\t\t\tl2fwd_ports_eth_addr[portid].addr_bytes[5]);\n\n\t\t/* initialize port stats */\n\t\t//memset(&port_statistics, 0, sizeof(port_statistics));\n\t}\n\n\tif (!nb_ports_available) {\n\t\trte_exit(EXIT_FAILURE,\n\t\t\t\"All available ports are disabled. Please set portmask.\\n\");\n\t}\n\n\tcheck_all_ports_link_status(nb_ports, l2fwd_enabled_port_mask);\n\n\t/* Record pair lcore */\n\t/**\n\t * Since l2fwd example would create pair between different neighbour port, that's\n\t * port 0 receive and forward to port 1, the same to port 1, these 2 ports will have\n\t * dependency. If one port stopped working (killed, for example), the port need to\n\t * be stopped/started again. During the time, another port need to wait until stop/start\n\t * procedure completed. So, record the pair relationship for those lcores working\n\t * on ports.\n\t **/\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tuint32_t pair_port;\n\t\tunsigned lcore = 0, pair_lcore = 0;\n\t\tunsigned j, find_lcore, find_pair_lcore;\n\t\t/* skip ports that are not enabled */\n\t\tif ((l2fwd_enabled_port_mask & (1 << portid)) == 0)\n\t\t\tcontinue;\n\n\t\t/* Find pair ports' lcores */\n\t\tfind_lcore = find_pair_lcore = 0;\n\t\tpair_port = l2fwd_dst_ports[portid];\n\t\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n\t\t\tif (!rte_lcore_is_enabled(i))\n\t\t\t\tcontinue;\n\t\t\tfor (j = 0; j < lcore_queue_conf[i].n_rx_port;j++) {\n\t\t\t\tif (lcore_queue_conf[i].rx_port_list[j] == portid) {\n\t\t\t\t\tlcore = i;\n\t\t\t\t\tfind_lcore = 1;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (lcore_queue_conf[i].rx_port_list[j] == pair_port) {\n\t\t\t\t\tpair_lcore = i;\n\t\t\t\t\tfind_pair_lcore = 1;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (find_lcore && find_pair_lcore)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (!find_lcore || !find_pair_lcore)\n\t\t\trte_exit(EXIT_FAILURE, \"Not find port=%d pair\\n\", portid);\n\n\t\tprintf(\"lcore %u and %u paired\\n\", lcore, pair_lcore);\n\t\tlcore_resource[lcore].pair_id = pair_lcore;\n\t\tlcore_resource[pair_lcore].pair_id = lcore;\n\t}\n\n\t/* Create message buffer for all master and slave */\n\tmessage_pool = rte_mempool_create(\"ms_msg_pool\",\n\t\t\t NB_CORE_MSGBUF * RTE_MAX_LCORE,\n\t\t\t sizeof(enum l2fwd_cmd), NB_CORE_MSGBUF / 2,\n\t\t\t 0,\n\t\t\t rte_pktmbuf_pool_init, NULL,\n\t\t\t rte_pktmbuf_init, NULL,\n\t\t\t rte_socket_id(), 0);\n\n\tif (message_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Create msg mempool failed\\n\");\n\n\t/* Create ring for each master and slave pair, also register cb when slave leaves */\n\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n\t\t/**\n\t\t * Only create ring and register slave_exit cb in case that core involved into\n\t\t * packet forwarding\n\t\t **/\n\t\tif (lcore_resource[i].enabled) {\n\t\t\t/* Create ring for master and slave communication */\n\t\t\tret = create_ms_ring(i);\n\t\t\tif (ret != 0)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Create ring for lcore=%u failed\",\n\t\t\t\ti);\n\n\t\t\tif (flib_register_slave_exit_notify(i,\n\t\t\t\tslave_exit_cb) != 0)\n\t\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\t\t\"Register master_trace_slave_exit failed\");\n\t\t}\n\t}\n\n\t/* launch per-lcore init on every lcore except master */\n\tflib_mp_remote_launch(l2fwd_launch_one_lcore, NULL, SKIP_MASTER);\n\n\t/* print statistics 10 second */\n\tprev_tsc = cur_tsc = rte_rdtsc();\n\ttimer_tsc = 0;\n\twhile (1) {\n\t\tsleep(1);\n\t\tcur_tsc = rte_rdtsc();\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\t/* if timer is enabled */\n\t\tif (timer_period > 0) {\n\n\t\t\t/* advance the timer */\n\t\t\ttimer_tsc += diff_tsc;\n\n\t\t\t/* if timer has reached its timeout */\n\t\t\tif (unlikely(timer_tsc >= (uint64_t) timer_period)) {\n\n\t\t\t\tprint_stats();\n\t\t\t\t/* reset the timer */\n\t\t\t\ttimer_tsc = 0;\n\t\t\t}\n\t\t}\n\n\t\tprev_tsc = cur_tsc;\n\n\t\t/* Check any slave need restart or recreate */\n\t\trte_spinlock_lock(&res_lock);\n\t\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n\t\t\tstruct lcore_resource_struct *res = &lcore_resource[i];\n\t\t\tstruct lcore_resource_struct *pair = &lcore_resource[res->pair_id];\n\n\t\t\t/* If find slave exited, try to reset pair */\n\t\t\tif (res->enabled && res->flags && pair->enabled) {\n\t\t\t\tif (!pair->flags) {\n\t\t\t\t\tmaster_sendcmd_with_ack(pair->lcore_id, CMD_STOP);\n\t\t\t\t\trte_spinlock_unlock(&res_lock);\n\t\t\t\t\tsleep(1);\n\t\t\t\t\trte_spinlock_lock(&res_lock);\n\t\t\t\t\tif (pair->flags)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tif (reset_pair(res->lcore_id, pair->lcore_id) != 0)\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"failed to reset slave\");\n\t\t\t\tres->flags = 0;\n\t\t\t\tpair->flags = 0;\n\t\t\t}\n\t\t}\n\t\trte_spinlock_unlock(&res_lock);\n\t}\n\n}\n" }, { "path": "examples/multi_process/simple_mp/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = simple_mp\n\n# all source are stored in SRCS-y\nSRCS-y := main.c mp_commands.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/multi_process/simple_mp/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * This sample application is a simple multi-process application which\n * demostrates sharing of queues and memory pools between processes, and\n * using those queues/pools for communication between the processes.\n *\n * Application is designed to run with two processes, a primary and a\n * secondary, and each accepts commands on the commandline, the most\n * important of which is \"send\", which just sends a string to the other\n * process.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \"mp_commands.h\"\n\n#define RTE_LOGTYPE_APP RTE_LOGTYPE_USER1\n\nstatic const char *_MSG_POOL = \"MSG_POOL\";\nstatic const char *_SEC_2_PRI = \"SEC_2_PRI\";\nstatic const char *_PRI_2_SEC = \"PRI_2_SEC\";\nconst unsigned string_size = 64;\n\nstruct rte_ring *send_ring, *recv_ring;\nstruct rte_mempool *message_pool;\nvolatile int quit = 0;\n\nstatic int\nlcore_recv(__attribute__((unused)) void *arg)\n{\n\tunsigned lcore_id = rte_lcore_id();\n\n\tprintf(\"Starting core %u\\n\", lcore_id);\n\twhile (!quit){\n\t\tvoid *msg;\n\t\tif (rte_ring_dequeue(recv_ring, &msg) < 0){\n\t\t\tusleep(5);\n\t\t\tcontinue;\n\t\t}\n\t\tprintf(\"core %u: Received '%s'\\n\", lcore_id, (char *)msg);\n\t\trte_mempool_put(message_pool, msg);\n\t}\n\n\treturn 0;\n}\n\nint\nmain(int argc, char **argv)\n{\n\tconst unsigned flags = 0;\n\tconst unsigned ring_size = 64;\n\tconst unsigned pool_size = 1024;\n\tconst unsigned pool_cache = 32;\n\tconst unsigned priv_data_sz = 0;\n\n\tint ret;\n\tunsigned lcore_id;\n\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Cannot init EAL\\n\");\n\n\tif (rte_eal_process_type() == RTE_PROC_PRIMARY){\n\t\tsend_ring = rte_ring_create(_PRI_2_SEC, ring_size, rte_socket_id(), flags);\n\t\trecv_ring = rte_ring_create(_SEC_2_PRI, ring_size, rte_socket_id(), flags);\n\t\tmessage_pool = rte_mempool_create(_MSG_POOL, pool_size,\n\t\t\t\tstring_size, pool_cache, priv_data_sz,\n\t\t\t\tNULL, NULL, NULL, NULL,\n\t\t\t\trte_socket_id(), flags);\n\t} else {\n\t\trecv_ring = rte_ring_lookup(_PRI_2_SEC);\n\t\tsend_ring = rte_ring_lookup(_SEC_2_PRI);\n\t\tmessage_pool = rte_mempool_lookup(_MSG_POOL);\n\t}\n\tif (send_ring == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Problem getting sending ring\\n\");\n\tif (recv_ring == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Problem getting receiving ring\\n\");\n\tif (message_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Problem getting message pool\\n\");\n\n\tRTE_LOG(INFO, APP, \"Finished Process Init.\\n\");\n\n\t/* call lcore_recv() on every slave lcore */\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\trte_eal_remote_launch(lcore_recv, NULL, lcore_id);\n\t}\n\n\t/* call cmd prompt on master lcore */\n\tstruct cmdline *cl = cmdline_stdin_new(simple_mp_ctx, \"\\nsimple_mp > \");\n\tif (cl == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create cmdline instance\\n\");\n\tcmdline_interact(cl);\n\tcmdline_stdin_exit(cl);\n\n\trte_eal_mp_wait_lcore();\n\treturn 0;\n}\n" }, { "path": "examples/multi_process/simple_mp/mp_commands.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \"mp_commands.h\"\n\n/**********************************************************/\n\nstruct cmd_send_result {\n\tcmdline_fixed_string_t action;\n\tcmdline_fixed_string_t message;\n};\n\nstatic void cmd_send_parsed(void *parsed_result,\n\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tvoid *msg = NULL;\n\tstruct cmd_send_result *res = parsed_result;\n\n\tif (rte_mempool_get(message_pool, &msg) < 0)\n\t\trte_panic(\"Failed to get message buffer\\n\");\n\tsnprintf((char *)msg, string_size, \"%s\", res->message);\n\tif (rte_ring_enqueue(send_ring, msg) < 0) {\n\t\tprintf(\"Failed to send message - message discarded\\n\");\n\t\trte_mempool_put(message_pool, msg);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_send_action =\n\tTOKEN_STRING_INITIALIZER(struct cmd_send_result, action, \"send\");\ncmdline_parse_token_string_t cmd_send_message =\n\tTOKEN_STRING_INITIALIZER(struct cmd_send_result, message, NULL);\n\ncmdline_parse_inst_t cmd_send = {\n\t.f = cmd_send_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"send a string to another process\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t\t(void *)&cmd_send_action,\n\t\t\t(void *)&cmd_send_message,\n\t\t\tNULL,\n\t},\n};\n\n/**********************************************************/\n\nstruct cmd_quit_result {\n\tcmdline_fixed_string_t quit;\n};\n\nstatic void cmd_quit_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tquit = 1;\n\tcmdline_quit(cl);\n}\n\ncmdline_parse_token_string_t cmd_quit_quit =\n\tTOKEN_STRING_INITIALIZER(struct cmd_quit_result, quit, \"quit\");\n\ncmdline_parse_inst_t cmd_quit = {\n\t.f = cmd_quit_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"close the application\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_quit_quit,\n\t\tNULL,\n\t},\n};\n\n/**********************************************************/\n\nstruct cmd_help_result {\n\tcmdline_fixed_string_t help;\n};\n\nstatic void cmd_help_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tcmdline_printf(cl, \"Simple demo example of multi-process in RTE\\n\\n\"\n\t\t\t\"This is a readline-like interface that can be used to\\n\"\n\t\t\t\"send commands to the simple app. Commands supported are:\\n\\n\"\n\t\t\t\"- send [string]\\n\" \"- help\\n\" \"- quit\\n\\n\");\n}\n\ncmdline_parse_token_string_t cmd_help_help =\n\tTOKEN_STRING_INITIALIZER(struct cmd_help_result, help, \"help\");\n\ncmdline_parse_inst_t cmd_help = {\n\t.f = cmd_help_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"show help\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_help_help,\n\t\tNULL,\n\t},\n};\n\n/****** CONTEXT (list of instruction) */\ncmdline_parse_ctx_t simple_mp_ctx[] = {\n\t\t(cmdline_parse_inst_t *)&cmd_send,\n\t\t(cmdline_parse_inst_t *)&cmd_quit,\n\t\t(cmdline_parse_inst_t *)&cmd_help,\n\tNULL,\n};\n" }, { "path": "examples/multi_process/simple_mp/mp_commands.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _SIMPLE_MP_COMMANDS_H_\n#define _SIMPLE_MP_COMMANDS_H_\n\nextern const unsigned string_size;\nextern struct rte_ring *send_ring;\nextern struct rte_mempool *message_pool;\nextern volatile int quit;\n\nextern cmdline_parse_ctx_t simple_mp_ctx[];\n\n#endif /* _SIMPLE_MP_COMMANDS_H_ */\n" }, { "path": "examples/multi_process/symmetric_mp/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = symmetric_mp\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/multi_process/symmetric_mp/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Sample application demostrating how to do packet I/O in a multi-process\n * environment. The same code can be run as a primary process and as a\n * secondary process, just with a different proc-id parameter in each case\n * (apart from the EAL flag to indicate a secondary process).\n *\n * Each process will read from the same ports, given by the port-mask\n * parameter, which should be the same in each case, just using a different\n * queue per port as determined by the proc-id parameter.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define RTE_LOGTYPE_APP RTE_LOGTYPE_USER1\n\n#define NB_MBUFS 64*1024 /* use 64k mbufs */\n#define MBUF_CACHE_SIZE 256\n#define PKT_BURST 32\n#define RX_RING_SIZE 128\n#define TX_RING_SIZE 512\n\n#define PARAM_PROC_ID \"proc-id\"\n#define PARAM_NUM_PROCS \"num-procs\"\n\n/* for each lcore, record the elements of the ports array to use */\nstruct lcore_ports{\n\tunsigned start_port;\n\tunsigned num_ports;\n};\n\n/* structure to record the rx and tx packets. Put two per cache line as ports\n * used in pairs */\nstruct port_stats{\n\tunsigned rx;\n\tunsigned tx;\n\tunsigned drop;\n} __attribute__((aligned(RTE_CACHE_LINE_SIZE / 2)));\n\nstatic int proc_id = -1;\nstatic unsigned num_procs = 0;\n\nstatic uint8_t ports[RTE_MAX_ETHPORTS];\nstatic unsigned num_ports = 0;\n\nstatic struct lcore_ports lcore_ports[RTE_MAX_LCORE];\nstatic struct port_stats pstats[RTE_MAX_ETHPORTS];\n\n/* prints the usage statement and quits with an error message */\nstatic void\nsmp_usage(const char *prgname, const char *errmsg)\n{\n\tprintf(\"\\nError: %s\\n\",errmsg);\n\tprintf(\"\\n%s [EAL options] -- -p \"\n\t\t\t\"--\"PARAM_NUM_PROCS\" \"\n\t\t\t\" --\"PARAM_PROC_ID\" \\n\"\n\t\t\t\"-p : a hex bitmask indicating what ports are to be used\\n\"\n\t\t\t\"--num-procs: the number of processes which will be used\\n\"\n\t\t\t\"--proc-id : the id of the current process (id < num-procs)\\n\"\n\t\t\t\"\\n\",\n\t\t\tprgname);\n\texit(1);\n}\n\n\n/* signal handler configured for SIGTERM and SIGINT to print stats on exit */\nstatic void\nprint_stats(int signum)\n{\n\tunsigned i;\n\tprintf(\"\\nExiting on signal %d\\n\\n\", signum);\n\tfor (i = 0; i < num_ports; i++){\n\t\tconst uint8_t p_num = ports[i];\n\t\tprintf(\"Port %u: RX - %u, TX - %u, Drop - %u\\n\", (unsigned)p_num,\n\t\t\t\tpstats[p_num].rx, pstats[p_num].tx, pstats[p_num].drop);\n\t}\n\texit(0);\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nsmp_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tunsigned i, port_mask = 0;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t\t{PARAM_NUM_PROCS, 1, 0, 0},\n\t\t\t{PARAM_PROC_ID, 1, 0, 0},\n\t\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:\", \\\n\t\t\tlgopts, &option_index)) != EOF) {\n\n\t\tswitch (opt) {\n\t\tcase 'p':\n\t\t\tport_mask = strtoull(optarg, NULL, 16);\n\t\t\tbreak;\n\t\t\t/* long options */\n\t\tcase 0:\n\t\t\tif (strncmp(lgopts[option_index].name, PARAM_NUM_PROCS, 8) == 0)\n\t\t\t\tnum_procs = atoi(optarg);\n\t\t\telse if (strncmp(lgopts[option_index].name, PARAM_PROC_ID, 7) == 0)\n\t\t\t\tproc_id = atoi(optarg);\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tsmp_usage(prgname, \"Cannot parse all command-line arguments\\n\");\n\t\t}\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\n\tif (proc_id < 0)\n\t\tsmp_usage(prgname, \"Invalid or missing proc-id parameter\\n\");\n\tif (rte_eal_process_type() == RTE_PROC_PRIMARY && num_procs == 0)\n\t\tsmp_usage(prgname, \"Invalid or missing num-procs parameter\\n\");\n\tif (port_mask == 0)\n\t\tsmp_usage(prgname, \"Invalid or missing port mask\\n\");\n\n\t/* get the port numbers from the port mask */\n\tfor(i = 0; i < rte_eth_dev_count(); i++)\n\t\tif(port_mask & (1 << i))\n\t\t\tports[num_ports++] = (uint8_t)i;\n\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\n\treturn (ret);\n}\n\n/*\n * Initialises a given port using global settings and with the rx buffers\n * coming from the mbuf_pool passed as parameter\n */\nstatic inline int\nsmp_port_init(uint8_t port, struct rte_mempool *mbuf_pool, uint16_t num_queues)\n{\n\tstruct rte_eth_conf port_conf = {\n\t\t\t.rxmode = {\n\t\t\t\t.mq_mode\t= ETH_MQ_RX_RSS,\n\t\t\t\t.split_hdr_size = 0,\n\t\t\t\t.header_split = 0, /**< Header Split disabled */\n\t\t\t\t.hw_ip_checksum = 1, /**< IP checksum offload enabled */\n\t\t\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t\t\t},\n\t\t\t.rx_adv_conf = {\n\t\t\t\t.rss_conf = {\n\t\t\t\t\t.rss_key = NULL,\n\t\t\t\t\t.rss_hf = ETH_RSS_IP,\n\t\t\t\t},\n\t\t\t},\n\t\t\t.txmode = {\n\t\t\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t\t\t}\n\t};\n\tconst uint16_t rx_rings = num_queues, tx_rings = num_queues;\n\tstruct rte_eth_dev_info info;\n\tint retval;\n\tuint16_t q;\n\n\tif (rte_eal_process_type() == RTE_PROC_SECONDARY)\n\t\treturn 0;\n\n\tif (port >= rte_eth_dev_count())\n\t\treturn -1;\n\n\tprintf(\"# Initialising port %u... \", (unsigned)port);\n\tfflush(stdout);\n\n\trte_eth_dev_info_get(port, &info);\n\tinfo.default_rxconf.rx_drop_en = 1;\n\n\tretval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);\n\tif (retval < 0)\n\t\treturn retval;\n\n\tfor (q = 0; q < rx_rings; q ++) {\n\t\tretval = rte_eth_rx_queue_setup(port, q, RX_RING_SIZE,\n\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\t&info.default_rxconf,\n\t\t\t\tmbuf_pool);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\tfor (q = 0; q < tx_rings; q ++) {\n\t\tretval = rte_eth_tx_queue_setup(port, q, TX_RING_SIZE,\n\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\tNULL);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\trte_eth_promiscuous_enable(port);\n\n\tretval = rte_eth_dev_start(port);\n\tif (retval < 0)\n\t\treturn retval;\n\n\treturn 0;\n}\n\n/* Goes through each of the lcores and calculates what ports should\n * be used by that core. Fills in the global lcore_ports[] array.\n */\nstatic void\nassign_ports_to_cores(void)\n{\n\n\tconst unsigned lcores = rte_eal_get_configuration()->lcore_count;\n\tconst unsigned port_pairs = num_ports / 2;\n\tconst unsigned pairs_per_lcore = port_pairs / lcores;\n\tunsigned extra_pairs = port_pairs % lcores;\n\tunsigned ports_assigned = 0;\n\tunsigned i;\n\n\tRTE_LCORE_FOREACH(i) {\n\t\tlcore_ports[i].start_port = ports_assigned;\n\t\tlcore_ports[i].num_ports = pairs_per_lcore * 2;\n\t\tif (extra_pairs > 0) {\n\t\t\tlcore_ports[i].num_ports += 2;\n\t\t\textra_pairs--;\n\t\t}\n\t\tports_assigned += lcore_ports[i].num_ports;\n\t}\n}\n\n/* Main function used by the processing threads.\n * Prints out some configuration details for the thread and then begins\n * performing packet RX and TX.\n */\nstatic int\nlcore_main(void *arg __rte_unused)\n{\n\tconst unsigned id = rte_lcore_id();\n\tconst unsigned start_port = lcore_ports[id].start_port;\n\tconst unsigned end_port = start_port + lcore_ports[id].num_ports;\n\tconst uint16_t q_id = (uint16_t)proc_id;\n\tunsigned p, i;\n\tchar msgbuf[256];\n\tint msgbufpos = 0;\n\n\tif (start_port == end_port){\n\t\tprintf(\"Lcore %u has nothing to do\\n\", id);\n\t\treturn 0;\n\t}\n\n\t/* build up message in msgbuf before printing to decrease likelihood\n\t * of multi-core message interleaving.\n\t */\n\tmsgbufpos += snprintf(msgbuf, sizeof(msgbuf) - msgbufpos,\n\t\t\t\"Lcore %u using ports \", id);\n\tfor (p = start_port; p < end_port; p++){\n\t\tmsgbufpos += snprintf(msgbuf + msgbufpos, sizeof(msgbuf) - msgbufpos,\n\t\t\t\t\"%u \", (unsigned)ports[p]);\n\t}\n\tprintf(\"%s\\n\", msgbuf);\n\tprintf(\"lcore %u using queue %u of each port\\n\", id, (unsigned)q_id);\n\n\t/* handle packet I/O from the ports, reading and writing to the\n\t * queue number corresponding to our process number (not lcore id)\n\t */\n\n\tfor (;;) {\n\t\tstruct rte_mbuf *buf[PKT_BURST];\n\n\t\tfor (p = start_port; p < end_port; p++) {\n\t\t\tconst uint8_t src = ports[p];\n\t\t\tconst uint8_t dst = ports[p ^ 1]; /* 0 <-> 1, 2 <-> 3 etc */\n\t\t\tconst uint16_t rx_c = rte_eth_rx_burst(src, q_id, buf, PKT_BURST);\n\t\t\tif (rx_c == 0)\n\t\t\t\tcontinue;\n\t\t\tpstats[src].rx += rx_c;\n\n\t\t\tconst uint16_t tx_c = rte_eth_tx_burst(dst, q_id, buf, rx_c);\n\t\t\tpstats[dst].tx += tx_c;\n\t\t\tif (tx_c != rx_c) {\n\t\t\t\tpstats[dst].drop += (rx_c - tx_c);\n\t\t\t\tfor (i = tx_c; i < rx_c; i++)\n\t\t\t\t\trte_pktmbuf_free(buf[i]);\n\t\t\t}\n\t\t}\n\t}\n}\n\n/* Check the link status of all ports in up to 9s, and print them finally */\nstatic void\ncheck_all_ports_link_status(uint8_t port_num, uint32_t port_mask)\n{\n#define CHECK_INTERVAL 100 /* 100ms */\n#define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */\n\tuint8_t portid, count, all_ports_up, print_flag = 0;\n\tstruct rte_eth_link link;\n\n\tprintf(\"\\nChecking link status\");\n\tfflush(stdout);\n\tfor (count = 0; count <= MAX_CHECK_TIME; count++) {\n\t\tall_ports_up = 1;\n\t\tfor (portid = 0; portid < port_num; portid++) {\n\t\t\tif ((port_mask & (1 << portid)) == 0)\n\t\t\t\tcontinue;\n\t\t\tmemset(&link, 0, sizeof(link));\n\t\t\trte_eth_link_get_nowait(portid, &link);\n\t\t\t/* print link status if flag set */\n\t\t\tif (print_flag == 1) {\n\t\t\t\tif (link.link_status)\n\t\t\t\t\tprintf(\"Port %d Link Up - speed %u \"\n\t\t\t\t\t\t\"Mbps - %s\\n\", (uint8_t)portid,\n\t\t\t\t\t\t(unsigned)link.link_speed,\n\t\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t\t\t\telse\n\t\t\t\t\tprintf(\"Port %d Link Down\\n\",\n\t\t\t\t\t\t\t(uint8_t)portid);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* clear all_ports_up flag if any link down */\n\t\t\tif (link.link_status == 0) {\n\t\t\t\tall_ports_up = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* after finally printing all link status, get out */\n\t\tif (print_flag == 1)\n\t\t\tbreak;\n\n\t\tif (all_ports_up == 0) {\n\t\t\tprintf(\".\");\n\t\t\tfflush(stdout);\n\t\t\trte_delay_ms(CHECK_INTERVAL);\n\t\t}\n\n\t\t/* set the print_flag if all ports up or timeout */\n\t\tif (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {\n\t\t\tprint_flag = 1;\n\t\t\tprintf(\"done\\n\");\n\t\t}\n\t}\n}\n\n/* Main function.\n * Performs initialisation and then calls the lcore_main on each core\n * to do the packet-processing work.\n */\nint\nmain(int argc, char **argv)\n{\n\tstatic const char *_SMP_MBUF_POOL = \"SMP_MBUF_POOL\";\n\tint ret;\n\tunsigned i;\n\tenum rte_proc_type_t proc_type;\n\tstruct rte_mempool *mp;\n\n\t/* set up signal handlers to print stats on exit */\n\tsignal(SIGINT, print_stats);\n\tsignal(SIGTERM, print_stats);\n\n\t/* initialise the EAL for all */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Cannot init EAL\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* determine the NIC devices available */\n\tif (rte_eth_dev_count() == 0)\n\t\trte_exit(EXIT_FAILURE, \"No Ethernet ports - bye\\n\");\n\n\t/* parse application arguments (those after the EAL ones) */\n\tsmp_parse_args(argc, argv);\n\n\tproc_type = rte_eal_process_type();\n\tmp = (proc_type == RTE_PROC_SECONDARY) ?\n\t\t\trte_mempool_lookup(_SMP_MBUF_POOL) :\n\t\t\trte_pktmbuf_pool_create(_SMP_MBUF_POOL, NB_MBUFS,\n\t\t\t\tMBUF_CACHE_SIZE, 0, RTE_MBUF_DEFAULT_BUF_SIZE,\n\t\t\t\trte_socket_id());\n\tif (mp == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot get memory pool for buffers\\n\");\n\n\tif (num_ports & 1)\n\t\trte_exit(EXIT_FAILURE, \"Application must use an even number of ports\\n\");\n\tfor(i = 0; i < num_ports; i++){\n\t\tif(proc_type == RTE_PROC_PRIMARY)\n\t\t\tif (smp_port_init(ports[i], mp, (uint16_t)num_procs) < 0)\n\t\t\t\trte_exit(EXIT_FAILURE, \"Error initialising ports\\n\");\n\t}\n\n\tif (proc_type == RTE_PROC_PRIMARY)\n\t\tcheck_all_ports_link_status((uint8_t)num_ports, (~0x0));\n\n\tassign_ports_to_cores();\n\n\tRTE_LOG(INFO, APP, \"Finished Process Init.\\n\");\n\n\trte_eal_mp_remote_launch(lcore_main, NULL, CALL_MASTER);\n\n\treturn 0;\n}\n" }, { "path": "examples/netmap_compat/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\nunexport RTE_SRCDIR RTE_OUTPUT RTE_EXTMK\n\nDIRS-y += bridge\n\n.PHONY: all clean $(DIRS-y)\n\nall: $(DIRS-y)\nclean: $(DIRS-y)\n\n$(DIRS-y):\n\t$(MAKE) -C $@ $(MAKECMDGOALS) O=$(RTE_OUTPUT)\n" }, { "path": "examples/netmap_compat/bridge/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define the RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifneq ($(CONFIG_RTE_EXEC_ENV),\"linuxapp\")\n$(info This application can only operate in a linuxapp environment, \\\nplease change the definition of the RTE_TARGET environment variable)\nall:\nelse\n\n# binary name\nAPP = bridge\n\n# for compat_netmap.c\nVPATH := $(SRCDIR)/../lib\n\n# all source are stored in SRCS-y\nSRCS-y := bridge.c\nSRCS-y += compat_netmap.c\n\nCFLAGS += -O3 -I$(SRCDIR)/../lib -I$(SRCDIR)/../netmap\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n\nendif\n" }, { "path": "examples/netmap_compat/bridge/bridge.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \"compat_netmap.h\"\n\n\n#define BUF_SIZE\tRTE_MBUF_DEFAULT_DATAROOM\n#define MBUF_DATA_SIZE\t(BUF_SIZE + RTE_PKTMBUF_HEADROOM)\n\n#define MBUF_PER_POOL\t8192\n\nstruct rte_eth_conf eth_conf = {\n\t.rxmode = {\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0,\n\t\t.hw_ip_checksum = 0,\n\t\t.hw_vlan_filter = 0,\n\t\t.jumbo_frame = 0,\n\t\t.hw_strip_crc = 0,\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\n#define\tMAX_QUEUE_NUM\t1\n#define\tRX_QUEUE_NUM\t1\n#define\tTX_QUEUE_NUM\t1\n\n#define\tMAX_DESC_NUM\t0x400\n#define\tRX_DESC_NUM\t0x100\n#define\tTX_DESC_NUM\t0x200\n\n#define\tRX_SYNC_NUM\t0x20\n#define\tTX_SYNC_NUM\t0x20\n\nstruct rte_netmap_port_conf port_conf = {\n\t.eth_conf = ð_conf,\n\t.socket_id = SOCKET_ID_ANY,\n\t.nr_tx_rings = TX_QUEUE_NUM,\n\t.nr_rx_rings = RX_QUEUE_NUM,\n\t.nr_tx_slots = TX_DESC_NUM,\n\t.nr_rx_slots = RX_DESC_NUM,\n\t.tx_burst = TX_SYNC_NUM,\n\t.rx_burst = RX_SYNC_NUM,\n};\n\nstruct rte_netmap_conf netmap_conf = {\n\t.socket_id = SOCKET_ID_ANY,\n\t.max_bufsz = BUF_SIZE,\n\t.max_rings = MAX_QUEUE_NUM,\n\t.max_slots = MAX_DESC_NUM,\n};\n\nstatic int stop = 0;\n\n#define\tMAX_PORT_NUM\t2\n\nstruct netmap_port {\n\tint fd;\n\tstruct netmap_if *nmif;\n\tstruct netmap_ring *rx_ring;\n\tstruct netmap_ring *tx_ring;\n\tconst char *str;\n\tuint8_t id;\n};\n\nstatic struct {\n\tuint32_t num;\n\tstruct netmap_port p[MAX_PORT_NUM];\n\tvoid *mem;\n} ports;\n\nstatic void\nusage(const char *prgname)\n{\n\tfprintf(stderr, \"Usage: %s [EAL args] -- [OPTION]...\\n\"\n\t\t\"-h, --help \\t Show this help message and exit\\n\"\n\t\t\"-i INTERFACE_A \\t Interface (DPDK port number) to use\\n\"\n\t\t\"[ -i INTERFACE_B \\t Interface (DPDK port number) to use ]\\n\",\n\t\tprgname);\n}\n\nstatic uint8_t\nparse_portid(const char *portid_str)\n{\n\tchar *end;\n\tunsigned id;\n\n\tid = strtoul(portid_str, &end, 10);\n\n\tif (end == portid_str || *end != '\\0' || id > RTE_MAX_ETHPORTS)\n\t\trte_exit(EXIT_FAILURE, \"Invalid port number\\n\");\n\n\treturn (uint8_t) id;\n}\n\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt;\n\n\twhile ((opt = getopt(argc, argv, \"hi:\")) != -1) {\n\t\tswitch (opt) {\n\t\tcase 'h':\n\t\t\tusage(argv[0]);\n\t\t\trte_exit(EXIT_SUCCESS, \"exiting...\");\n\t\t\tbreak;\n\t\tcase 'i':\n\t\t\tif (ports.num >= RTE_DIM(ports.p)) {\n\t\t\t\tusage(argv[0]);\n\t\t\t\trte_exit(EXIT_FAILURE, \"configs with %u \"\n\t\t\t\t\t\"ports are not supported\\n\",\n\t\t\t\t\tports.num + 1);\n\n\t\t\t}\n\n\t\t\tports.p[ports.num].str = optarg;\n\t\t\tports.p[ports.num].id = parse_portid(optarg);\n\t\t\tports.num++;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tusage(argv[0]);\n\t\t\trte_exit(EXIT_FAILURE, \"invalid option: %c\\n\", opt);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic void sigint_handler(__rte_unused int sig)\n{\n\tstop = 1;\n\tsignal(SIGINT, SIG_DFL);\n}\n\nstatic void move(int n, struct netmap_ring *rx, struct netmap_ring *tx)\n{\n\tuint32_t tmp;\n\n\twhile (n-- > 0) {\n\t\ttmp = tx->slot[tx->cur].buf_idx;\n\n\t\ttx->slot[tx->cur].buf_idx = rx->slot[rx->cur].buf_idx;\n\t\ttx->slot[tx->cur].len = rx->slot[rx->cur].len;\n\t\ttx->slot[tx->cur].flags |= NS_BUF_CHANGED;\n\t\ttx->cur = NETMAP_RING_NEXT(tx, tx->cur);\n\t\ttx->avail--;\n\n\t\trx->slot[rx->cur].buf_idx = tmp;\n\t\trx->slot[rx->cur].flags |= NS_BUF_CHANGED;\n\t\trx->cur = NETMAP_RING_NEXT(rx, rx->cur);\n\t\trx->avail--;\n\t}\n}\n\nstatic int\nnetmap_port_open(uint32_t idx)\n{\n\tint err;\n\tstruct netmap_port *port;\n\tstruct nmreq req;\n\n\tport = ports.p + idx;\n\n\tport->fd = rte_netmap_open(\"/dev/netmap\", O_RDWR);\n\n\tsnprintf(req.nr_name, sizeof(req.nr_name), \"%s\", port->str);\n\treq.nr_version = NETMAP_API;\n\treq.nr_ringid = 0;\n\n\terr = rte_netmap_ioctl(port->fd, NIOCGINFO, &req);\n\tif (err) {\n\t\tprintf(\"[E] NIOCGINFO ioctl failed (error %d)\\n\", err);\n\t\treturn (err);\n\t}\n\n\tsnprintf(req.nr_name, sizeof(req.nr_name), \"%s\", port->str);\n\treq.nr_version = NETMAP_API;\n\treq.nr_ringid = 0;\n\n\terr = rte_netmap_ioctl(port->fd, NIOCREGIF, &req);\n\tif (err) {\n\t\tprintf(\"[E] NIOCREGIF ioctl failed (error %d)\\n\", err);\n\t\treturn (err);\n\t}\n\n\t/* mmap only once. */\n\tif (ports.mem == NULL)\n\t\tports.mem = rte_netmap_mmap(NULL, req.nr_memsize,\n\t\t\tPROT_WRITE | PROT_READ, MAP_PRIVATE, port->fd, 0);\n\n\tif (ports.mem == MAP_FAILED) {\n\t\tprintf(\"[E] NETMAP mmap failed for fd: %d)\\n\", port->fd);\n\t\treturn (-ENOMEM);\n\t}\n\n\tport->nmif = NETMAP_IF(ports.mem, req.nr_offset);\n\n\tport->tx_ring = NETMAP_TXRING(port->nmif, 0);\n\tport->rx_ring = NETMAP_RXRING(port->nmif, 0);\n\n\treturn (0);\n}\n\n\nint main(int argc, char *argv[])\n{\n\tint err, ret;\n\tuint32_t i, pmsk;\n\tstruct nmreq req;\n\tstruct pollfd pollfd[MAX_PORT_NUM];\n\tstruct rte_mempool *pool;\n\tstruct netmap_ring *rx_ring, *tx_ring;\n\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Cannot initialize EAL\\n\");\n\n\targc -= ret;\n\targv += ret;\n\n\tparse_args(argc, argv);\n\n\tif (ports.num == 0)\n\t\trte_exit(EXIT_FAILURE, \"no ports specified\\n\");\n\n\tif (rte_eth_dev_count() < 1)\n\t\trte_exit(EXIT_FAILURE, \"Not enough ethernet ports available\\n\");\n\n\tpool = rte_pktmbuf_pool_create(\"mbuf_pool\", MBUF_PER_POOL, 32, 0,\n\t\tMBUF_DATA_SIZE, rte_socket_id());\n\tif (pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Couldn't create mempool\\n\");\n\n\tnetmap_conf.socket_id = rte_socket_id();\n\terr = rte_netmap_init(&netmap_conf);\n\n\tif (err < 0)\n\t\trte_exit(EXIT_FAILURE,\n\t\t\t\"Couldn't initialize librte_compat_netmap\\n\");\n\telse\n\t\tprintf(\"librte_compat_netmap initialized\\n\");\n\n\tport_conf.pool = pool;\n\tport_conf.socket_id = rte_socket_id();\n\n\tfor (i = 0; i != ports.num; i++) {\n\n\t\terr = rte_netmap_init_port(ports.p[i].id, &port_conf);\n\t\tif (err < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Couldn't setup port %hhu\\n\",\n\t\t\t\tports.p[i].id);\n\n\t\trte_eth_promiscuous_enable(ports.p[i].id);\n\t}\n\n\tfor (i = 0; i != ports.num; i++) {\n\n\t\terr = netmap_port_open(i);\n\t\tif (err) {\n\t\t\trte_exit(EXIT_FAILURE, \"Couldn't set port %hhu \"\n\t\t\t\t\"under NETMAP control\\n\",\n\t\t\t\tports.p[i].id);\n\t\t}\n\t\telse\n\t\t\tprintf(\"Port %hhu now in Netmap mode\\n\", ports.p[i].id);\n\t}\n\n\tmemset(pollfd, 0, sizeof(pollfd));\n\n\tfor (i = 0; i != ports.num; i++) {\n\t\tpollfd[i].fd = ports.p[i].fd;\n\t\tpollfd[i].events = POLLIN | POLLOUT;\n\t}\n\n\tsignal(SIGINT, sigint_handler);\n\n\tpmsk = ports.num - 1;\n\n\tprintf(\"Bridge up and running!\\n\");\n\n\twhile (!stop) {\n\t\tuint32_t n_pkts;\n\n\t\tpollfd[0].revents = 0;\n\t\tpollfd[1].revents = 0;\n\n\t\tret = rte_netmap_poll(pollfd, ports.num, 0);\n\t\tif (ret < 0) {\n\t \t\tstop = 1;\n\t \t\tprintf(\"[E] poll returned with error %d\\n\", ret);\n\t\t}\n\n\t\tif (((pollfd[0].revents | pollfd[1].revents) & POLLERR) != 0) {\n\t\t\tprintf(\"POLLERR!\\n\");\n\t\t}\n\n\t\tif ((pollfd[0].revents & POLLIN) != 0 &&\n\t\t\t\t(pollfd[pmsk].revents & POLLOUT) != 0) {\n\n\t\t\trx_ring = ports.p[0].rx_ring;\n\t\t\ttx_ring = ports.p[pmsk].tx_ring;\n\n\t\t\tn_pkts = RTE_MIN(rx_ring->avail, tx_ring->avail);\n\t\t\tmove(n_pkts, rx_ring, tx_ring);\n\t\t}\n\n\t\tif (pmsk != 0 && (pollfd[pmsk].revents & POLLIN) != 0 &&\n\t\t\t\t(pollfd[0].revents & POLLOUT) != 0) {\n\n\t\t\trx_ring = ports.p[pmsk].rx_ring;\n\t\t\ttx_ring = ports.p[0].tx_ring;\n\n\t\t\tn_pkts = RTE_MIN(rx_ring->avail, tx_ring->avail);\n\t\t\tmove(n_pkts, rx_ring, tx_ring);\n\t\t}\n\t}\n\n\tprintf(\"Bridge stopped!\\n\");\n\n\tfor (i = 0; i != ports.num; i++) {\n\t\terr = rte_netmap_ioctl(ports.p[i].fd, NIOCUNREGIF, &req);\n\t\tif (err) {\n\t\t\tprintf(\"[E] NIOCUNREGIF ioctl failed (error %d)\\n\",\n\t\t\t\terr);\n\t\t}\n\t\telse\n\t\t\tprintf(\"Port %hhu unregistered from Netmap mode\\n\", ports.p[i].id);\n\n\t\trte_netmap_close(ports.p[i].fd);\n\t}\n\treturn 0;\n}\n" }, { "path": "examples/netmap_compat/lib/compat_netmap.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"compat_netmap.h\"\n\nstruct netmap_port {\n\tstruct rte_mempool *pool;\n\tstruct netmap_if *nmif;\n\tstruct rte_eth_conf eth_conf;\n\tstruct rte_eth_txconf tx_conf;\n\tstruct rte_eth_rxconf rx_conf;\n\tint32_t socket_id;\n\tuint16_t nr_tx_rings;\n\tuint16_t nr_rx_rings;\n\tuint32_t nr_tx_slots;\n\tuint32_t nr_rx_slots;\n\tuint16_t tx_burst;\n\tuint16_t rx_burst;\n\tuint32_t fd;\n};\n\nstruct fd_port {\n\tuint32_t port;\n};\n\n#define\tFD_PORT_FREE\tUINT32_MAX\n#define\tFD_PORT_RSRV\t(FD_PORT_FREE - 1)\n\nstruct netmap_state {\n\tstruct rte_netmap_conf conf;\n\tuintptr_t buf_start;\n\tvoid *mem;\n\tuint32_t mem_sz;\n\tuint32_t netif_memsz;\n};\n\n\n#define COMPAT_NETMAP_MAX_NOFILE\t(2 * RTE_MAX_ETHPORTS)\n#define COMPAT_NETMAP_MAX_BURST\t\t64\n#define COMPAT_NETMAP_MAX_PKT_PER_SYNC\t(2 * COMPAT_NETMAP_MAX_BURST)\n\nstatic struct netmap_port ports[RTE_MAX_ETHPORTS];\nstatic struct netmap_state netmap;\n\nstatic struct fd_port fd_port[COMPAT_NETMAP_MAX_NOFILE];\nstatic const int next_fd_start = RLIMIT_NOFILE + 1;\nstatic rte_spinlock_t netmap_lock;\n\n#define\tIDX_TO_FD(x)\t((x) + next_fd_start)\n#define\tFD_TO_IDX(x)\t((x) - next_fd_start)\n#define\tFD_VALID(x)\t((x) >= next_fd_start && \\\n\t(x) < (typeof (x))(RTE_DIM(fd_port) + next_fd_start))\n\n#define\tPORT_NUM_RINGS\t(2 * netmap.conf.max_rings)\n#define\tPORT_NUM_SLOTS\t(PORT_NUM_RINGS * netmap.conf.max_slots)\n\n#define\tBUF_IDX(port, ring, slot) \\\n\t(((port) * PORT_NUM_RINGS + (ring)) * netmap.conf.max_slots + \\\n\t(slot))\n\n#define NETMAP_IF_RING_OFS(rid, rings, slots) ({\\\n\tstruct netmap_if *_if; \\\n\tstruct netmap_ring *_rg; \\\n\tsizeof(*_if) + \\\n\t(rings) * sizeof(_if->ring_ofs[0]) + \\\n\t(rid) * sizeof(*_rg) + \\\n\t(slots) * sizeof(_rg->slot[0]); \\\n\t})\n\nstatic void netmap_unregif(uint32_t idx, uint32_t port);\n\n\nstatic int32_t\nifname_to_portid(const char *ifname, uint8_t *port)\n{\n\tchar *endptr;\n\tuint64_t portid;\n\n\terrno = 0;\n\tportid = strtoul(ifname, &endptr, 10);\n\tif (endptr == ifname || *endptr != '\\0' ||\n\t\t\tportid >= RTE_DIM(ports) || errno != 0)\n\t\treturn (-EINVAL);\n\n\t*port = (uint8_t)portid;\n\treturn (0);\n}\n\n/**\n * Given a dpdk mbuf, fill in the Netmap slot in ring r and its associated\n * buffer with the data held by the mbuf.\n * Note that mbuf chains are not supported.\n */\nstatic void\nmbuf_to_slot(struct rte_mbuf *mbuf, struct netmap_ring *r, uint32_t index)\n{\n\tchar *data;\n\tuint16_t length;\n\n\tdata = rte_pktmbuf_mtod(mbuf, char *);\n\tlength = rte_pktmbuf_data_len(mbuf);\n\n\tif (length > r->nr_buf_size)\n\t\tlength = 0;\n\n\tr->slot[index].len = length;\n\trte_memcpy(NETMAP_BUF(r, r->slot[index].buf_idx), data, length);\n}\n\n/**\n * Given a Netmap ring and a slot index for that ring, construct a dpdk mbuf\n * from the data held in the buffer associated with the slot.\n * Allocation/deallocation of the dpdk mbuf are the responsability of the\n * caller.\n * Note that mbuf chains are not supported.\n */\nstatic void\nslot_to_mbuf(struct netmap_ring *r, uint32_t index, struct rte_mbuf *mbuf)\n{\n\tchar *data;\n\tuint16_t length;\n\n\trte_pktmbuf_reset(mbuf);\n\tlength = r->slot[index].len;\n\tdata = rte_pktmbuf_append(mbuf, length);\n\n\tif (data != NULL)\n\t rte_memcpy(data, NETMAP_BUF(r, r->slot[index].buf_idx), length);\n}\n\nstatic int32_t\nfd_reserve(void)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i != RTE_DIM(fd_port) && fd_port[i].port != FD_PORT_FREE;\n\t\t\ti++)\n\t\t;\n\n\tif (i == RTE_DIM(fd_port))\n\t\treturn (-ENOMEM);\n\n\tfd_port[i].port = FD_PORT_RSRV;\n\treturn (IDX_TO_FD(i));\n}\n\nstatic int32_t\nfd_release(int32_t fd)\n{\n\tuint32_t idx, port;\n\n\tidx = FD_TO_IDX(fd);\n\n\tif (!FD_VALID(fd) || (port = fd_port[idx].port) == FD_PORT_FREE)\n\t\treturn (-EINVAL);\n\n\t/* if we still have a valid port attached, release the port */\n\tif (port < RTE_DIM(ports) && ports[port].fd == idx) {\n\t\tnetmap_unregif(idx, port);\n\t}\n\n\tfd_port[idx].port = FD_PORT_FREE;\n\treturn (0);\n}\n\nstatic int\ncheck_nmreq(struct nmreq *req, uint8_t *port)\n{\n\tint32_t rc;\n\tuint8_t portid;\n\n\tif (req == NULL)\n\t\treturn (-EINVAL);\n\n\tif (req->nr_version != NETMAP_API) {\n\t\treq->nr_version = NETMAP_API;\n\t\treturn (-EINVAL);\n\t}\n\n\tif ((rc = ifname_to_portid(req->nr_name, &portid)) != 0) {\n\t \tRTE_LOG(ERR, USER1, \"Invalid interface name:\\\"%s\\\" \"\n\t\t\t\"in NIOCGINFO call\\n\", req->nr_name);\n\t\treturn (rc);\n\t}\n\n\tif (ports[portid].pool == NULL) {\n\t \tRTE_LOG(ERR, USER1, \"Misconfigured portid %hhu\\n\", portid);\n\t\treturn (-EINVAL);\n\t}\n\n\t*port = portid;\n\treturn (0);\n}\n\n/**\n * Simulate a Netmap NIOCGINFO ioctl: given a struct nmreq holding an interface\n * name (a port number in our case), fill the struct nmreq in with advisory\n * information about the interface: number of rings and their size, total memory\n * required in the map, ...\n * Those are preconfigured using rte_eth_{,tx,rx}conf and\n * rte_netmap_port_conf structures\n * and calls to rte_netmap_init_port() in the Netmap application.\n */\nstatic int\nioctl_niocginfo(__rte_unused int fd, void * param)\n{\n\tuint8_t portid;\n\tstruct nmreq *req;\n\tint32_t rc;\n\n\treq = (struct nmreq *)param;\n\tif ((rc = check_nmreq(req, &portid)) != 0)\n\t\treturn (rc);\n\n\treq->nr_tx_rings = (uint16_t)(ports[portid].nr_tx_rings - 1);\n\treq->nr_rx_rings = (uint16_t)(ports[portid].nr_rx_rings - 1);\n\treq->nr_tx_slots = ports[portid].nr_tx_slots;\n\treq->nr_rx_slots = ports[portid].nr_rx_slots;\n\n\t/* in current implementation we have all NETIFs shared aone region. */\n\treq->nr_memsize = netmap.mem_sz;\n\treq->nr_offset = 0;\n\n\treturn (0);\n}\n\nstatic void\nnetmap_ring_setup(struct netmap_ring *ring, uint8_t port, uint32_t ringid,\n\tuint32_t num_slots)\n{\n\tuint32_t j;\n\n\tring->buf_ofs = netmap.buf_start - (uintptr_t)ring;\n\tring->num_slots = num_slots;\n\tring->cur = 0;\n\tring->reserved = 0;\n\tring->nr_buf_size = netmap.conf.max_bufsz;\n\tring->flags = 0;\n\tring->ts.tv_sec = 0;\n\tring->ts.tv_usec = 0;\n\n\tfor (j = 0; j < ring->num_slots; j++) {\n\t\tring->slot[j].buf_idx = BUF_IDX(port, ringid, j);\n\t\tring->slot[j].len = 0;\n\t\tring->flags = 0;\n\t}\n}\n\nstatic int\nnetmap_regif(struct nmreq *req, uint32_t idx, uint8_t port)\n{\n\tstruct netmap_if *nmif;\n\tstruct netmap_ring *ring;\n\tuint32_t i, slots, start_ring;\n\tint32_t rc;\n\n\tif (ports[port].fd < RTE_DIM(fd_port)) {\n\t \tRTE_LOG(ERR, USER1, \"port %hhu already in use by fd: %u\\n\",\n\t\t\tport, IDX_TO_FD(ports[port].fd));\n\t\treturn (-EBUSY);\n\t}\n\tif (fd_port[idx].port != FD_PORT_RSRV) {\n\t \tRTE_LOG(ERR, USER1, \"fd: %u is misconfigured\\n\",\n\t\t\tIDX_TO_FD(idx));\n\t\treturn (-EBUSY);\n\t}\n\n\tnmif = ports[port].nmif;\n\n\t/* setup netmap_if fields. */\n\tmemset(nmif, 0, netmap.netif_memsz);\n\n\t/* only ALL rings supported right now. */\n\tif (req->nr_ringid != 0)\n\t\treturn (-EINVAL);\n\n\tsnprintf(nmif->ni_name, sizeof(nmif->ni_name), \"%s\", req->nr_name);\n\tnmif->ni_version = req->nr_version;\n\n\t/* Netmap uses ni_(r|t)x_rings + 1 */\n\tnmif->ni_rx_rings = ports[port].nr_rx_rings - 1;\n\tnmif->ni_tx_rings = ports[port].nr_tx_rings - 1;\n\n\t/*\n\t * Setup TX rings and slots.\n\t * Refer to the comments in netmap.h for details\n\t */\n\n\tslots = 0;\n\tfor (i = 0; i < nmif->ni_tx_rings + 1; i++) {\n\n\t\tnmif->ring_ofs[i] = NETMAP_IF_RING_OFS(i,\n\t\t\tPORT_NUM_RINGS, slots);\n\n\t\tring = NETMAP_TXRING(nmif, i);\n\t\tnetmap_ring_setup(ring, port, i, ports[port].nr_tx_slots);\n\t\tring->avail = ring->num_slots;\n\n\t\tslots += ports[port].nr_tx_slots;\n\t}\n\n\t/*\n\t * Setup RX rings and slots.\n\t * Refer to the comments in netmap.h for details\n\t */\n\n\tstart_ring = i;\n\n\tfor (; i < nmif->ni_rx_rings + 1 + start_ring; i++) {\n\n\t\tnmif->ring_ofs[i] = NETMAP_IF_RING_OFS(i,\n\t\t\tPORT_NUM_RINGS, slots);\n\n\t\tring = NETMAP_RXRING(nmif, (i - start_ring));\n\t\tnetmap_ring_setup(ring, port, i, ports[port].nr_rx_slots);\n\t\tring->avail = 0;\n\n\t\tslots += ports[port].nr_rx_slots;\n\t}\n\n\tif ((rc = rte_eth_dev_start(port)) < 0) {\n\t\tRTE_LOG(ERR, USER1,\n\t\t\t\"Couldn't start ethernet device %s (error %d)\\n\",\n\t\t\treq->nr_name, rc);\n\t return (rc);\n\t}\n\n\t/* setup fdi <--> port relationtip. */\n\tports[port].fd = idx;\n\tfd_port[idx].port = port;\n\n\treq->nr_memsize = netmap.mem_sz;\n\treq->nr_offset = (uintptr_t)nmif - (uintptr_t)netmap.mem;\n\n\treturn (0);\n}\n\n/**\n * Simulate a Netmap NIOCREGIF ioctl:\n */\nstatic int\nioctl_niocregif(int32_t fd, void * param)\n{\n\tuint8_t portid;\n\tint32_t rc;\n\tuint32_t idx;\n\tstruct nmreq *req;\n\n\treq = (struct nmreq *)param;\n\tif ((rc = check_nmreq(req, &portid)) != 0)\n\t\treturn (rc);\n\n\tidx = FD_TO_IDX(fd);\n\n\trte_spinlock_lock(&netmap_lock);\n\trc = netmap_regif(req, idx, portid);\n\trte_spinlock_unlock(&netmap_lock);\n\n\treturn (rc);\n}\n\nstatic void\nnetmap_unregif(uint32_t idx, uint32_t port)\n{\n\tfd_port[idx].port = FD_PORT_RSRV;\n\tports[port].fd = UINT32_MAX;\n\trte_eth_dev_stop((uint8_t)port);\n}\n\n/**\n * Simulate a Netmap NIOCUNREGIF ioctl: put an interface running in Netmap\n * mode back in \"normal\" mode. In our case, we just stop the port associated\n * with this file descriptor.\n */\nstatic int\nioctl_niocunregif(int fd)\n{\n\tuint32_t idx, port;\n\tint32_t rc;\n\n\tidx = FD_TO_IDX(fd);\n\n\trte_spinlock_lock(&netmap_lock);\n\n\tport = fd_port[idx].port;\n\tif (port < RTE_DIM(ports) && ports[port].fd == idx) {\n\t\tnetmap_unregif(idx, port);\n\t\trc = 0;\n\t} else {\n\t\tRTE_LOG(ERR, USER1,\n\t\t\t\"%s: %d is not associated with valid port\\n\",\n\t\t\t__func__, fd);\n\t\trc = -EINVAL;\n\t}\n\n\trte_spinlock_unlock(&netmap_lock);\n\treturn (rc);\n}\n\n/**\n * A call to rx_sync_ring will try to fill a Netmap RX ring with as many\n * packets as it can hold coming from its dpdk port.\n */\nstatic inline int\nrx_sync_ring(struct netmap_ring *ring, uint8_t port, uint16_t ring_number,\n\tuint16_t max_burst)\n{\n\tint32_t i, n_rx;\n\tuint16_t burst_size;\n\tuint32_t cur_slot, n_free_slots;\n\tstruct rte_mbuf *rx_mbufs[COMPAT_NETMAP_MAX_BURST];\n\n\tn_free_slots = ring->num_slots - (ring->avail + ring->reserved);\n\tn_free_slots = RTE_MIN(n_free_slots, max_burst);\n\tcur_slot = (ring->cur + ring->avail) & (ring->num_slots - 1);\n\n\twhile (n_free_slots) {\n\t\tburst_size = (uint16_t)RTE_MIN(n_free_slots, RTE_DIM(rx_mbufs));\n\n\t\t/* receive up to burst_size packets from the NIC's queue */\n\t\tn_rx = rte_eth_rx_burst(port, ring_number, rx_mbufs,\n\t\t\tburst_size);\n\n\t\tif (n_rx == 0)\n\t\t\treturn 0;\n\t\tif (unlikely(n_rx < 0))\n\t\t\treturn -1;\n\n\t\t/* Put those n_rx packets in the Netmap structures */\n\t\tfor (i = 0; i < n_rx ; i++) {\n\t\t\tmbuf_to_slot(rx_mbufs[i], ring, cur_slot);\n\t\t\trte_pktmbuf_free(rx_mbufs[i]);\n\t\t\tcur_slot = NETMAP_RING_NEXT(ring, cur_slot);\n\t\t}\n\n\t\t/* Update the Netmap ring structure to reflect the change */\n\t\tring->avail += n_rx;\n\t\tn_free_slots -= n_rx;\n\t}\n\n\treturn 0;\n}\n\nstatic inline int\nrx_sync_if(uint32_t port)\n{\n\tuint16_t burst;\n\tuint32_t i, rc;\n\tstruct netmap_if *nifp;\n\tstruct netmap_ring *r;\n\n\tnifp = ports[port].nmif;\n\tburst = ports[port].rx_burst;\n\trc = 0;\n\n\tfor (i = 0; i < nifp->ni_rx_rings + 1; i++) {\n\t\tr = NETMAP_RXRING(nifp, i);\n\t\trx_sync_ring(r, (uint8_t)port, (uint16_t)i, burst);\n\t\trc += r->avail;\n\t}\n\n\treturn (rc);\n}\n\n/**\n * Simulate a Netmap NIOCRXSYNC ioctl:\n */\nstatic int\nioctl_niocrxsync(int fd)\n{\n\tuint32_t idx, port;\n\n\tidx = FD_TO_IDX(fd);\n\tif ((port = fd_port[idx].port) < RTE_DIM(ports) &&\n\t\t\tports[port].fd == idx) {\n\t\treturn (rx_sync_if(fd_port[idx].port));\n\t} else {\n\t\treturn (-EINVAL);\n\t}\n}\n\n/**\n * A call to tx_sync_ring will try to empty a Netmap TX ring by converting its\n * buffers into rte_mbufs and sending them out on the rings's dpdk port.\n */\nstatic int\ntx_sync_ring(struct netmap_ring *ring, uint8_t port, uint16_t ring_number,\n\tstruct rte_mempool *pool, uint16_t max_burst)\n{\n\tuint32_t i, n_tx;\n\tuint16_t burst_size;\n\tuint32_t cur_slot, n_used_slots;\n\tstruct rte_mbuf *tx_mbufs[COMPAT_NETMAP_MAX_BURST];\n\n\tn_used_slots = ring->num_slots - ring->avail;\n\tn_used_slots = RTE_MIN(n_used_slots, max_burst);\n\tcur_slot = (ring->cur + ring->avail) & (ring->num_slots - 1);\n\n\twhile (n_used_slots) {\n\t\tburst_size = (uint16_t)RTE_MIN(n_used_slots, RTE_DIM(tx_mbufs));\n\n\t\tfor (i = 0; i < burst_size; i++) {\n\t\t\ttx_mbufs[i] = rte_pktmbuf_alloc(pool);\n\t\t\tif (tx_mbufs[i] == NULL)\n\t\t\t\tgoto err;\n\n\t\t\tslot_to_mbuf(ring, cur_slot, tx_mbufs[i]);\n\t\t\tcur_slot = NETMAP_RING_NEXT(ring, cur_slot);\n\t\t}\n\n\t\tn_tx = rte_eth_tx_burst(port, ring_number, tx_mbufs,\n\t\t\tburst_size);\n\n\t\t/* Update the Netmap ring structure to reflect the change */\n\t\tring->avail += n_tx;\n\t\tn_used_slots -= n_tx;\n\n\t\t/* Return the mbufs that failed to transmit to their pool */\n\t\tif (unlikely(n_tx != burst_size)) {\n\t\t\tfor (i = n_tx; i < burst_size; i++)\n\t\t\t\trte_pktmbuf_free(tx_mbufs[i]);\n\t \tbreak;\n\t\t}\n\t}\n\n\treturn 0;\n\nerr:\n\tfor (; i == 0; --i)\n\t\trte_pktmbuf_free(tx_mbufs[i]);\n\n\tRTE_LOG(ERR, USER1,\n\t\t\"Couldn't get mbuf from mempool is the mempool too small?\\n\");\n\treturn -1;\n}\n\nstatic int\ntx_sync_if(uint32_t port)\n{\n\tuint16_t burst;\n\tuint32_t i, rc;\n\tstruct netmap_if *nifp;\n\tstruct netmap_ring *r;\n\tstruct rte_mempool *mp;\n\n\tnifp = ports[port].nmif;\n\tmp = ports[port].pool;\n\tburst = ports[port].tx_burst;\n\trc = 0;\n\n\tfor (i = 0; i < nifp->ni_tx_rings + 1; i++) {\n\t\tr = NETMAP_TXRING(nifp, i);\n\t\ttx_sync_ring(r, (uint8_t)port, (uint16_t)i, mp, burst);\n\t\trc += r->avail;\n\t}\n\n\treturn (rc);\n}\n\n/**\n * Simulate a Netmap NIOCTXSYNC ioctl:\n */\nstatic inline int\nioctl_nioctxsync(int fd)\n{\n\tuint32_t idx, port;\n\n\tidx = FD_TO_IDX(fd);\n\tif ((port = fd_port[idx].port) < RTE_DIM(ports) &&\n\t\t\tports[port].fd == idx) {\n\t\treturn (tx_sync_if(fd_port[idx].port));\n\t} else {\n\t\treturn (-EINVAL);\n\t}\n}\n\n/**\n * Give the library a mempool of rte_mbufs with which it can do the\n * rte_mbuf <--> netmap slot conversions.\n */\nint\nrte_netmap_init(const struct rte_netmap_conf *conf)\n{\n\tsize_t buf_ofs, nmif_sz, sz;\n\tsize_t port_rings, port_slots, port_bufs;\n\tuint32_t i, port_num;\n\n\tport_num = RTE_MAX_ETHPORTS;\n\tport_rings = 2 * conf->max_rings;\n\tport_slots = port_rings * conf->max_slots;\n\tport_bufs = port_slots;\n\n\tnmif_sz = NETMAP_IF_RING_OFS(port_rings, port_rings, port_slots);\n\tsz = nmif_sz * port_num;\n\n\tbuf_ofs = RTE_ALIGN_CEIL(sz, RTE_CACHE_LINE_SIZE);\n\tsz = buf_ofs + port_bufs * conf->max_bufsz * port_num;\n\n\tif (sz > UINT32_MAX ||\n\t\t\t(netmap.mem = rte_zmalloc_socket(__func__, sz,\n\t\t\tRTE_CACHE_LINE_SIZE, conf->socket_id)) == NULL) {\n\t\tRTE_LOG(ERR, USER1, \"%s: failed to allocate %zu bytes\\n\",\n\t\t\t__func__, sz);\n\t\treturn (-ENOMEM);\n\t}\n\n\tnetmap.mem_sz = sz;\n\tnetmap.netif_memsz = nmif_sz;\n\tnetmap.buf_start = (uintptr_t)netmap.mem + buf_ofs;\n\tnetmap.conf = *conf;\n\n\trte_spinlock_init(&netmap_lock);\n\n\t/* Mark all ports as unused and set NETIF pointer. */\n\tfor (i = 0; i != RTE_DIM(ports); i++) {\n\t\tports[i].fd = UINT32_MAX;\n\t\tports[i].nmif = (struct netmap_if *)\n\t\t\t((uintptr_t)netmap.mem + nmif_sz * i);\n\t}\n\n\t/* Mark all fd_ports as unused. */\n\tfor (i = 0; i != RTE_DIM(fd_port); i++) {\n\t\tfd_port[i].port = FD_PORT_FREE;\n\t}\n\n\treturn (0);\n}\n\n\nint\nrte_netmap_init_port(uint8_t portid, const struct rte_netmap_port_conf *conf)\n{\n\tint32_t ret;\n\tuint16_t i;\n\tuint16_t rx_slots, tx_slots;\n\n\tif (conf == NULL ||\n\t\t\tportid >= RTE_DIM(ports) ||\n\t\t\tconf->nr_tx_rings > netmap.conf.max_rings ||\n\t\t\tconf->nr_rx_rings > netmap.conf.max_rings) {\n\t\tRTE_LOG(ERR, USER1, \"%s(%hhu): invalid parameters\\n\",\n\t\t\t__func__, portid);\n\t\treturn (-EINVAL);\n\t}\n\n\t\trx_slots = (uint16_t)rte_align32pow2(conf->nr_rx_slots);\n\t\ttx_slots = (uint16_t)rte_align32pow2(conf->nr_tx_slots);\n\n\tif (tx_slots > netmap.conf.max_slots ||\n\t\t\trx_slots > netmap.conf.max_slots) {\n\t\tRTE_LOG(ERR, USER1, \"%s(%hhu): invalid parameters\\n\",\n\t\t\t__func__, portid);\n\t\treturn (-EINVAL);\n\t}\n\n\tret = rte_eth_dev_configure(portid, conf->nr_rx_rings,\n\t\tconf->nr_tx_rings, conf->eth_conf);\n\n\tif (ret < 0) {\n\t RTE_LOG(ERR, USER1, \"Couldn't configure port %hhu\\n\", portid);\n\t return (ret);\n\t}\n\n\tfor (i = 0; i < conf->nr_tx_rings; i++) {\n\t\tret = rte_eth_tx_queue_setup(portid, i, tx_slots,\n\t\t\tconf->socket_id, NULL);\n\n\t\tif (ret < 0) {\n\t\t\tRTE_LOG(ERR, USER1,\n\t\t\t\t\"Couldn't configure TX queue %\"PRIu16\" of \"\n\t\t\t\t\"port %\"PRIu8\"\\n\",\n\t\t\t\ti, portid);\n\t\t\treturn (ret);\n\t\t}\n\n\t\tret = rte_eth_rx_queue_setup(portid, i, rx_slots,\n\t\t\tconf->socket_id, NULL, conf->pool);\n\n\t\tif (ret < 0) {\n\t\t\tRTE_LOG(ERR, USER1,\n\t\t\t\t\"Couldn't configure RX queue %\"PRIu16\" of \"\n\t\t\t\t\"port %\"PRIu8\"\\n\",\n\t\t\t\ti, portid);\n\t\t\treturn (ret);\n\t\t}\n\t}\n\n\t/* copy config to the private storage. */\n\tports[portid].eth_conf = conf->eth_conf[0];\n\tports[portid].pool = conf->pool;\n\tports[portid].socket_id = conf->socket_id;\n\tports[portid].nr_tx_rings = conf->nr_tx_rings;\n\tports[portid].nr_rx_rings = conf->nr_rx_rings;\n\tports[portid].nr_tx_slots = tx_slots;\n\tports[portid].nr_rx_slots = rx_slots;\n\tports[portid].tx_burst = conf->tx_burst;\n\tports[portid].rx_burst = conf->rx_burst;\n\n\treturn (0);\n}\n\nint\nrte_netmap_close(__rte_unused int fd)\n{\n\tint32_t rc;\n\n\trte_spinlock_lock(&netmap_lock);\n\trc = fd_release(fd);\n\trte_spinlock_unlock(&netmap_lock);\n\n\tif (rc < 0) {\n\t\terrno =-rc;\n\t\trc = -1;\n\t}\n\treturn (rc);\n}\n\nint rte_netmap_ioctl(int fd, uint32_t op, void *param)\n{\n\tint ret;\n\n\tif (!FD_VALID(fd)) {\n\t errno = EBADF;\n\t return (-1);\n\t}\n\n\tswitch (op) {\n\n\t case NIOCGINFO:\n\t ret = ioctl_niocginfo(fd, param);\n\t break;\n\n\t case NIOCREGIF:\n\t ret = ioctl_niocregif(fd, param);\n\t break;\n\n\t case NIOCUNREGIF:\n\t ret = ioctl_niocunregif(fd);\n\t break;\n\n\t case NIOCRXSYNC:\n\t ret = ioctl_niocrxsync(fd);\n\t break;\n\n\t case NIOCTXSYNC:\n\t ret = ioctl_nioctxsync(fd);\n\t break;\n\n\t default:\n\t ret = -ENOTTY;\n\t}\n\n\tif (ret < 0) {\n\t\terrno = -ret;\n\t\tret = -1;\n\t} else {\n\t\tret = 0;\n\t}\n\n\treturn (ret);\n}\n\nvoid *\nrte_netmap_mmap(void *addr, size_t length,\n\tint prot, int flags, int fd, off_t offset)\n{\n\tstatic const int cprot = PROT_WRITE | PROT_READ;\n\n\tif (!FD_VALID(fd) || length + offset > netmap.mem_sz ||\n\t\t\t(prot & cprot) != cprot ||\n\t\t\t((flags & MAP_FIXED) != 0 && addr != NULL)) {\n\n\t\terrno = EINVAL;\n\t\treturn (MAP_FAILED);\n\t}\n\n\treturn (void *)((uintptr_t)netmap.mem + (uintptr_t)offset);\n}\n\n/**\n * Return a \"fake\" file descriptor with a value above RLIMIT_NOFILE so that\n * any attempt to use that file descriptor with the usual API will fail.\n */\nint\nrte_netmap_open(__rte_unused const char *pathname, __rte_unused int flags)\n{\n\tint fd;\n\n\trte_spinlock_lock(&netmap_lock);\n\tfd = fd_reserve();\n\trte_spinlock_unlock(&netmap_lock);\n\n\tif (fd < 0) {\n\t\terrno = -fd;\n\t\tfd = -1;\n\t}\n\treturn (fd);\n}\n\n/**\n * Doesn't support timeout other than 0 or infinite (negative) timeout\n */\nint\nrte_netmap_poll(struct pollfd *fds, nfds_t nfds, int timeout)\n{\n\tint32_t count_it, ret;\n\tuint32_t i, idx, port;\n\tuint32_t want_rx, want_tx;\n\n\tret = 0;\n\tdo {\n\t\tfor (i = 0; i < nfds; i++) {\n\n\t\t\tcount_it = 0;\n\n\t\t\tif (!FD_VALID(fds[i].fd) || fds[i].events == 0) {\n\t\t\t\tfds[i].revents = 0;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tidx = FD_TO_IDX(fds[i].fd);\n\t\t\tif ((port = fd_port[idx].port) >= RTE_DIM(ports) ||\n\t\tports[port].fd != idx) {\n\n\t\t\t\tfds[i].revents |= POLLERR;\n\t\t\t\tret++;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\twant_rx = fds[i].events & (POLLIN | POLLRDNORM);\n\t\t\twant_tx = fds[i].events & (POLLOUT | POLLWRNORM);\n\n\t\t\tif (want_rx && rx_sync_if(port) > 0) {\n\t\t\t\tfds[i].revents = (uint16_t)\n\t\t\t\t\t(fds[i].revents | want_rx);\n\t\t\t\tcount_it = 1;\n\t\t\t}\n\t\t\tif (want_tx && tx_sync_if(port) > 0) {\n\t\t\t\tfds[i].revents = (uint16_t)\n\t\t\t\t\t(fds[i].revents | want_tx);\n\t\t\t\tcount_it = 1;\n\t\t\t}\n\n\t\t\tret += count_it;\n\t\t}\n\t}\n\twhile ((ret == 0 && timeout < 0) || timeout);\n\n\treturn ret;\n}\n" }, { "path": "examples/netmap_compat/lib/compat_netmap.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_COMPAT_NETMAP_H_\n\n#include \n#include \n#include \n\n#include \n#include \n\n#include \"netmap.h\"\n#include \"netmap_user.h\"\n\n/**\n * One can overwrite Netmap macros here as needed\n */\n\nstruct rte_netmap_conf {\n\tint32_t socket_id;\n\tuint32_t max_rings; /* number of rings(queues) per netmap_if(port) */\n\tuint32_t max_slots; /* number of slots(descriptors) per netmap ring. */\n\tuint16_t max_bufsz; /* size of each netmap buffer. */\n};\n\nstruct rte_netmap_port_conf {\n\tstruct rte_eth_conf *eth_conf;\n\tstruct rte_mempool *pool;\n\tint32_t socket_id;\n\tuint16_t nr_tx_rings;\n\tuint16_t nr_rx_rings;\n\tuint32_t nr_tx_slots;\n\tuint32_t nr_rx_slots;\n\tuint16_t tx_burst;\n\tuint16_t rx_burst;\n};\n\nint rte_netmap_init(const struct rte_netmap_conf *conf);\nint rte_netmap_init_port(uint8_t portid,\n\tconst struct rte_netmap_port_conf *conf);\n\nint rte_netmap_close(int fd);\nint rte_netmap_ioctl(int fd, uint32_t op, void *param);\nint rte_netmap_open(const char *pathname, int flags);\nint rte_netmap_poll(struct pollfd *fds, nfds_t nfds, int timeout);\nvoid *rte_netmap_mmap(void *addr, size_t length, int prot, int flags, int fd,\n\t off_t offset);\n\n#endif /* _RTE_COMPAT_NETMAP_H_ */\n" }, { "path": "examples/netmap_compat/netmap/netmap.h", "content": "/*\n * Copyright (C) 2011 Matteo Landi, Luigi Rizzo. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are\n * met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the\n * distribution.\n *\n * 3. Neither the name of the authors nor the names of their contributors\n * may be used to endorse or promote products derived from this\n * software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY MATTEO LANDI AND CONTRIBUTORS \"AS IS\" AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTEO LANDI OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * $FreeBSD: head/sys/net/netmap.h 231198 2012-02-08 11:43:29Z luigi $\n * $Id: netmap.h 10879 2012-04-12 22:48:59Z luigi $\n *\n * Definitions of constants and the structures used by the netmap\n * framework, for the part visible to both kernel and userspace.\n * Detailed info on netmap is available with \"man netmap\" or at\n *\n *\thttp://info.iet.unipi.it/~luigi/netmap/\n */\n\n#ifndef _NET_NETMAP_H_\n#define _NET_NETMAP_H_\n\n/*\n * --- Netmap data structures ---\n *\n * The data structures used by netmap are shown below. Those in\n * capital letters are in an mmapp()ed area shared with userspace,\n * while others are private to the kernel.\n * Shared structures do not contain pointers but only memory\n * offsets, so that addressing is portable between kernel and userspace.\n\n\n softc\n+----------------+\n| standard fields|\n| if_pspare[0] ----------+\n+----------------+ |\n |\n+----------------+<------+\n|(netmap_adapter)|\n| | netmap_kring\n| tx_rings *--------------------------------->+---------------+\n| | netmap_kring | ring *---------.\n| rx_rings *--------->+---------------+ | nr_hwcur | |\n+----------------+ | ring *--------. | nr_hwavail | V\n | nr_hwcur | | | selinfo | |\n | nr_hwavail | | +---------------+ .\n | selinfo | | | ... | .\n +---------------+ | |(ntx+1 entries)|\n | .... | | | |\n |(nrx+1 entries)| | +---------------+\n | | |\n KERNEL +---------------+ |\n |\n ====================================================================\n |\n USERSPACE | NETMAP_RING\n +---->+-------------+\n / | cur |\n NETMAP_IF (nifp, one per file desc.) / | avail |\n +---------------+ / | buf_ofs |\n | ni_tx_rings | / +=============+\n | ni_rx_rings | / | buf_idx | slot[0]\n | | / | len, flags |\n | | / +-------------+\n +===============+ / | buf_idx | slot[1]\n | txring_ofs[0] | (rel.to nifp)--' | len, flags |\n | txring_ofs[1] | +-------------+\n (num_rings+1 entries) (nr_num_slots entries)\n | txring_ofs[n] | | buf_idx | slot[n-1]\n +---------------+ | len, flags |\n | rxring_ofs[0] | +-------------+\n | rxring_ofs[1] |\n (num_rings+1 entries)\n | txring_ofs[n] |\n +---------------+\n\n * The private descriptor ('softc' or 'adapter') of each interface\n * is extended with a \"struct netmap_adapter\" containing netmap-related\n * info (see description in dev/netmap/netmap_kernel.h.\n * Among other things, tx_rings and rx_rings point to the arrays of\n * \"struct netmap_kring\" which in turn reache the various\n * \"struct netmap_ring\", shared with userspace.\n\n * The NETMAP_RING is the userspace-visible replica of the NIC ring.\n * Each slot has the index of a buffer, its length and some flags.\n * In user space, the buffer address is computed as\n *\t(char *)ring + buf_ofs + index*NETMAP_BUF_SIZE\n * In the kernel, buffers do not necessarily need to be contiguous,\n * and the virtual and physical addresses are derived through\n * a lookup table.\n * To associate a different buffer to a slot, applications must\n * write the new index in buf_idx, and set NS_BUF_CHANGED flag to\n * make sure that the kernel updates the hardware ring as needed.\n *\n * Normally the driver is not requested to report the result of\n * transmissions (this can dramatically speed up operation).\n * However the user may request to report completion by setting\n * NS_REPORT.\n */\nstruct netmap_slot {\n\tuint32_t buf_idx; /* buffer index */\n\tuint16_t len;\t/* packet length, to be copied to/from the hw ring */\n\tuint16_t flags;\t/* buf changed, etc. */\n#define\tNS_BUF_CHANGED\t0x0001\t/* must resync the map, buffer changed */\n#define\tNS_REPORT\t0x0002\t/* ask the hardware to report results\n\t\t\t\t * e.g. by generating an interrupt\n\t\t\t\t */\n};\n\n/*\n * Netmap representation of a TX or RX ring (also known as \"queue\").\n * This is a queue implemented as a fixed-size circular array.\n * At the software level, two fields are important: avail and cur.\n *\n * In TX rings:\n *\tavail\tindicates the number of slots available for transmission.\n *\t\tIt is updated by the kernel after every netmap system call.\n *\t\tIt MUST BE decremented by the application when it appends a\n *\t\tpacket.\n *\tcur\tindicates the slot to use for the next packet\n *\t\tto send (i.e. the \"tail\" of the queue).\n *\t\tIt MUST BE incremented by the application before\n *\t\tnetmap system calls to reflect the number of newly\n *\t\tsent packets.\n *\t\tIt is checked by the kernel on netmap system calls\n *\t\t(normally unmodified by the kernel unless invalid).\n *\n * The kernel side of netmap uses two additional fields in its own\n * private ring structure, netmap_kring:\n *\tnr_hwcur is a copy of nr_cur on an NIOCTXSYNC.\n *\tnr_hwavail is the number of slots known as available by the\n *\t\thardware. It is updated on an INTR (inc by the\n *\t\tnumber of packets sent) and on a NIOCTXSYNC\n *\t\t(decrease by nr_cur - nr_hwcur)\n *\t\tA special case, nr_hwavail is -1 if the transmit\n *\t\tside is idle (no pending transmits).\n *\n * In RX rings:\n *\tavail\tis the number of packets available (possibly 0).\n *\t\tIt MUST BE decremented by the application when it consumes\n *\t\ta packet, and it is updated to nr_hwavail on a NIOCRXSYNC\n *\tcur\tindicates the first slot that contains a packet not\n *\t\tprocessed yet (the \"head\" of the queue).\n *\t\tIt MUST BE incremented by the software when it consumes\n *\t\ta packet.\n *\treserved\tindicates the number of buffers before 'cur'\n *\t\tthat the application has still in use. Normally 0,\n *\t\tit MUST BE incremented by the application when it\n *\t\tdoes not return the buffer immediately, and decremented\n *\t\twhen the buffer is finally freed.\n *\n * The kernel side of netmap uses two additional fields in the kring:\n *\tnr_hwcur is a copy of nr_cur on an NIOCRXSYNC\n *\tnr_hwavail is the number of packets available. It is updated\n *\t\ton INTR (inc by the number of new packets arrived)\n *\t\tand on NIOCRXSYNC (decreased by nr_cur - nr_hwcur).\n *\n * DATA OWNERSHIP/LOCKING:\n *\tThe netmap_ring is owned by the user program and it is only\n *\taccessed or modified in the upper half of the kernel during\n *\ta system call.\n *\n *\tThe netmap_kring is only modified by the upper half of the kernel.\n */\nstruct netmap_ring {\n\t/*\n\t * nr_buf_base_ofs is meant to be used through macros.\n\t * It contains the offset of the buffer region from this\n\t * descriptor.\n\t */\n\tssize_t\tbuf_ofs;\n\tuint32_t\tnum_slots;\t/* number of slots in the ring. */\n\tuint32_t\tavail;\t\t/* number of usable slots */\n\tuint32_t cur;\t\t/* 'current' r/w position */\n\tuint32_t\treserved;\t/* not refilled before current */\n\n\tuint16_t\tnr_buf_size;\n\tuint16_t\tflags;\n#define\tNR_TIMESTAMP\t0x0002\t\t/* set timestamp on *sync() */\n\n\tstruct timeval\tts;\t\t/* time of last *sync() */\n\n\t/* the slots follow. This struct has variable size */\n\tstruct netmap_slot slot[0];\t/* array of slots. */\n};\n\n\n/*\n * Netmap representation of an interface and its queue(s).\n * There is one netmap_if for each file descriptor on which we want\n * to select/poll. We assume that on each interface has the same number\n * of receive and transmit queues.\n * select/poll operates on one or all pairs depending on the value of\n * nmr_queueid passed on the ioctl.\n */\nstruct netmap_if {\n\tchar\t\tni_name[IFNAMSIZ]; /* name of the interface. */\n\tu_int\tni_version;\t/* API version, currently unused */\n\tu_int\tni_rx_rings;\t/* number of rx rings */\n\tu_int\tni_tx_rings;\t/* if zero, same as ni_rx_rings */\n\t/*\n\t * The following array contains the offset of each netmap ring\n\t * from this structure. The first ni_tx_queues+1 entries refer\n\t * to the tx rings, the next ni_rx_queues+1 refer to the rx rings\n\t * (the last entry in each block refers to the host stack rings).\n\t * The area is filled up by the kernel on NIOCREG,\n\t * and then only read by userspace code.\n\t */\n\tssize_t\tring_ofs[0];\n};\n\n#ifndef NIOCREGIF\n/*\n * ioctl names and related fields\n *\n * NIOCGINFO takes a struct ifreq, the interface name is the input,\n *\tthe outputs are number of queues and number of descriptor\n *\tfor each queue (useful to set number of threads etc.).\n *\n * NIOCREGIF takes an interface name within a struct ifreq,\n *\tand activates netmap mode on the interface (if possible).\n *\n * NIOCUNREGIF unregisters the interface associated to the fd.\n *\n * NIOCTXSYNC, NIOCRXSYNC synchronize tx or rx queues,\n *\twhose identity is set in NIOCREGIF through nr_ringid\n */\n\n/*\n * struct nmreq overlays a struct ifreq\n */\nstruct nmreq {\n\tchar\t\tnr_name[IFNAMSIZ];\n\tuint32_t\tnr_version;\t/* API version */\n#define\tNETMAP_API\t3\t\t/* current version */\n\tuint32_t\tnr_offset;\t/* nifp offset in the shared region */\n\tuint32_t\tnr_memsize;\t/* size of the shared region */\n\tuint32_t\tnr_tx_slots;\t/* slots in tx rings */\n\tuint32_t\tnr_rx_slots;\t/* slots in rx rings */\n\tuint16_t\tnr_tx_rings;\t/* number of tx rings */\n\tuint16_t\tnr_rx_rings;\t/* number of rx rings */\n\tuint16_t\tnr_ringid;\t/* ring(s) we care about */\n#define NETMAP_HW_RING\t0x4000\t\t/* low bits indicate one hw ring */\n#define NETMAP_SW_RING\t0x2000\t\t/* process the sw ring */\n#define NETMAP_NO_TX_POLL\t0x1000\t/* no automatic txsync on poll */\n#define NETMAP_RING_MASK 0xfff\t\t/* the ring number */\n\tuint16_t\tspare1;\n\tuint32_t\tspare2[4];\n};\n\n/*\n * FreeBSD uses the size value embedded in the _IOWR to determine\n * how much to copy in/out. So we need it to match the actual\n * data structure we pass. We put some spares in the structure\n * to ease compatibility with other versions\n */\n#define NIOCGINFO\t_IOWR('i', 145, struct nmreq) /* return IF info */\n#define NIOCREGIF\t_IOWR('i', 146, struct nmreq) /* interface register */\n#define NIOCUNREGIF\t_IO('i', 147) /* interface unregister */\n#define NIOCTXSYNC\t_IO('i', 148) /* sync tx queues */\n#define NIOCRXSYNC\t_IO('i', 149) /* sync rx queues */\n#endif /* !NIOCREGIF */\n\n#endif /* _NET_NETMAP_H_ */\n" }, { "path": "examples/netmap_compat/netmap/netmap_user.h", "content": "/*\n * Copyright (C) 2011 Matteo Landi, Luigi Rizzo. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are\n * met:\n *\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the\n * distribution.\n *\n * 3. Neither the name of the authors nor the names of their contributors\n * may be used to endorse or promote products derived from this\n * software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY MATTEO LANDI AND CONTRIBUTORS \"AS IS\" AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL MATTEO LANDI OR CONTRIBUTORS\n * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF\n * THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * $FreeBSD: head/sys/net/netmap_user.h 231198 2012-02-08 11:43:29Z luigi $\n * $Id: netmap_user.h 10879 2012-04-12 22:48:59Z luigi $\n *\n * This header contains the macros used to manipulate netmap structures\n * and packets in userspace. See netmap(4) for more information.\n *\n * The address of the struct netmap_if, say nifp, is computed from the\n * value returned from ioctl(.., NIOCREG, ...) and the mmap region:\n *\tioctl(fd, NIOCREG, &req);\n *\tmem = mmap(0, ... );\n *\tnifp = NETMAP_IF(mem, req.nr_nifp);\n *\t\t(so simple, we could just do it manually)\n *\n * From there:\n *\tstruct netmap_ring *NETMAP_TXRING(nifp, index)\n *\tstruct netmap_ring *NETMAP_RXRING(nifp, index)\n *\t\twe can access ring->nr_cur, ring->nr_avail, ring->nr_flags\n *\n *\tring->slot[i] gives us the i-th slot (we can access\n *\t\tdirectly plen, flags, bufindex)\n *\n *\tchar *buf = NETMAP_BUF(ring, index) returns a pointer to\n *\t\tthe i-th buffer\n *\n * Since rings are circular, we have macros to compute the next index\n *\ti = NETMAP_RING_NEXT(ring, i);\n */\n\n#ifndef _NET_NETMAP_USER_H_\n#define _NET_NETMAP_USER_H_\n\n#define NETMAP_IF(b, o)\t(struct netmap_if *)((char *)(b) + (o))\n\n#define NETMAP_TXRING(nifp, index)\t\t\t\\\n\t((struct netmap_ring *)((char *)(nifp) +\t\\\n\t\t(nifp)->ring_ofs[index] ) )\n\n#define NETMAP_RXRING(nifp, index)\t\t\t\\\n\t((struct netmap_ring *)((char *)(nifp) +\t\\\n\t (nifp)->ring_ofs[index + (nifp)->ni_tx_rings + 1] ) )\n\n#define NETMAP_BUF(ring, index)\t\t\t\t\\\n\t((char *)(ring) + (ring)->buf_ofs + ((index)*(ring)->nr_buf_size))\n\n#define NETMAP_BUF_IDX(ring, buf)\t\t\t\\\n\t( ((char *)(buf) - ((char *)(ring) + (ring)->buf_ofs) ) / \\\n\t\t(ring)->nr_buf_size )\n\n#define\tNETMAP_RING_NEXT(r, i)\t\t\t\t\\\n\t((i)+1 == (r)->num_slots ? 0 : (i) + 1 )\n\n#define\tNETMAP_RING_FIRST_RESERVED(r)\t\t\t\\\n\t( (r)->cur < (r)->reserved ?\t\t\t\\\n\t (r)->cur + (r)->num_slots - (r)->reserved :\t\\\n\t (r)->cur - (r)->reserved )\n\n/*\n * Return 1 if the given tx ring is empty.\n */\n#define NETMAP_TX_RING_EMPTY(r)\t((r)->avail >= (r)->num_slots - 1)\n\n#endif /* _NET_NETMAP_USER_H_ */\n" }, { "path": "examples/packet_ordering/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overridden by command line or environment\nRTE_TARGET ?= x86_64-ivshmem-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = packet_ordering\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/packet_ordering/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define RX_DESC_PER_QUEUE 128\n#define TX_DESC_PER_QUEUE 512\n\n#define MAX_PKTS_BURST 32\n#define REORDER_BUFFER_SIZE 8192\n#define MBUF_PER_POOL 65535\n#define MBUF_POOL_CACHE_SIZE 250\n\n#define RING_SIZE 16384\n\n/* uncommnet below line to enable debug logs */\n/* #define DEBUG */\n\n#ifdef DEBUG\n#define LOG_LEVEL RTE_LOG_DEBUG\n#define LOG_DEBUG(log_type, fmt, args...) RTE_LOG(DEBUG, log_type, fmt, ##args)\n#else\n#define LOG_LEVEL RTE_LOG_INFO\n#define LOG_DEBUG(log_type, fmt, args...) do {} while (0)\n#endif\n\n/* Macros for printing using RTE_LOG */\n#define RTE_LOGTYPE_REORDERAPP RTE_LOGTYPE_USER1\n\nunsigned int portmask;\nunsigned int disable_reorder;\nvolatile uint8_t quit_signal;\n\nstatic struct rte_mempool *mbuf_pool;\n\nstatic struct rte_eth_conf port_conf_default;\n\nstruct worker_thread_args {\n\tstruct rte_ring *ring_in;\n\tstruct rte_ring *ring_out;\n};\n\nstruct send_thread_args {\n\tstruct rte_ring *ring_in;\n\tstruct rte_reorder_buffer *buffer;\n};\n\nstruct output_buffer {\n\tunsigned count;\n\tstruct rte_mbuf *mbufs[MAX_PKTS_BURST];\n};\n\nvolatile struct app_stats {\n\tstruct {\n\t\tuint64_t rx_pkts;\n\t\tuint64_t enqueue_pkts;\n\t\tuint64_t enqueue_failed_pkts;\n\t} rx __rte_cache_aligned;\n\n\tstruct {\n\t\tuint64_t dequeue_pkts;\n\t\tuint64_t enqueue_pkts;\n\t\tuint64_t enqueue_failed_pkts;\n\t} wkr __rte_cache_aligned;\n\n\tstruct {\n\t\tuint64_t dequeue_pkts;\n\t\t/* Too early pkts transmitted directly w/o reordering */\n\t\tuint64_t early_pkts_txtd_woro;\n\t\t/* Too early pkts failed from direct transmit */\n\t\tuint64_t early_pkts_tx_failed_woro;\n\t\tuint64_t ro_tx_pkts;\n\t\tuint64_t ro_tx_failed_pkts;\n\t} tx __rte_cache_aligned;\n} app_stats;\n\n/**\n * Get the last enabled lcore ID\n *\n * @return\n * The last enabled lcore ID.\n */\nstatic unsigned int\nget_last_lcore_id(void)\n{\n\tint i;\n\n\tfor (i = RTE_MAX_LCORE - 1; i >= 0; i--)\n\t\tif (rte_lcore_is_enabled(i))\n\t\t\treturn i;\n\treturn 0;\n}\n\n/**\n * Get the previous enabled lcore ID\n * @param id\n * The current lcore ID\n * @return\n * The previous enabled lcore ID or the current lcore\n * ID if it is the first available core.\n */\nstatic unsigned int\nget_previous_lcore_id(unsigned int id)\n{\n\tint i;\n\n\tfor (i = id - 1; i >= 0; i--)\n\t\tif (rte_lcore_is_enabled(i))\n\t\t\treturn i;\n\treturn id;\n}\n\nstatic inline void\npktmbuf_free_bulk(struct rte_mbuf *mbuf_table[], unsigned n)\n{\n\tunsigned int i;\n\n\tfor (i = 0; i < n; i++)\n\t\trte_pktmbuf_free(mbuf_table[i]);\n}\n\n/* display usage */\nstatic void\nprint_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK\\n\"\n\t\t\t\" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\",\n\t\t\tprgname);\n}\n\nstatic int\nparse_portmask(const char *portmask)\n{\n\tunsigned long pm;\n\tchar *end = NULL;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt;\n\tint option_index;\n\tchar **argvopt;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{\"disable-reorder\", 0, 0, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:\",\n\t\t\t\t\tlgopts, &option_index)) != EOF) {\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tportmask = parse_portmask(optarg);\n\t\t\tif (portmask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\t\t/* long options */\n\t\tcase 0:\n\t\t\tif (!strcmp(lgopts[option_index].name, \"disable-reorder\")) {\n\t\t\t\tprintf(\"reorder disabled\\n\");\n\t\t\t\tdisable_reorder = 1;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\tif (optind <= 1) {\n\t\tprint_usage(prgname);\n\t\treturn -1;\n\t}\n\n\targv[optind-1] = prgname;\n\toptind = 0; /* reset getopt lib */\n\treturn 0;\n}\n\nstatic inline int\nconfigure_eth_port(uint8_t port_id)\n{\n\tstruct ether_addr addr;\n\tconst uint16_t rxRings = 1, txRings = 1;\n\tconst uint8_t nb_ports = rte_eth_dev_count();\n\tint ret;\n\tuint16_t q;\n\n\tif (port_id > nb_ports)\n\t\treturn -1;\n\n\tret = rte_eth_dev_configure(port_id, rxRings, txRings, &port_conf_default);\n\tif (ret != 0)\n\t\treturn ret;\n\n\tfor (q = 0; q < rxRings; q++) {\n\t\tret = rte_eth_rx_queue_setup(port_id, q, RX_DESC_PER_QUEUE,\n\t\t\t\trte_eth_dev_socket_id(port_id), NULL,\n\t\t\t\tmbuf_pool);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t}\n\n\tfor (q = 0; q < txRings; q++) {\n\t\tret = rte_eth_tx_queue_setup(port_id, q, TX_DESC_PER_QUEUE,\n\t\t\t\trte_eth_dev_socket_id(port_id), NULL);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\t}\n\n\tret = rte_eth_dev_start(port_id);\n\tif (ret < 0)\n\t\treturn ret;\n\n\trte_eth_macaddr_get(port_id, &addr);\n\tprintf(\"Port %u MAC: %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\n\t\t\t\" %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\"\\n\",\n\t\t\t(unsigned)port_id,\n\t\t\taddr.addr_bytes[0], addr.addr_bytes[1],\n\t\t\taddr.addr_bytes[2], addr.addr_bytes[3],\n\t\t\taddr.addr_bytes[4], addr.addr_bytes[5]);\n\n\trte_eth_promiscuous_enable(port_id);\n\n\treturn 0;\n}\n\nstatic void\nprint_stats(void)\n{\n\tconst uint8_t nb_ports = rte_eth_dev_count();\n\tunsigned i;\n\tstruct rte_eth_stats eth_stats;\n\n\tprintf(\"\\nRX thread stats:\\n\");\n\tprintf(\" - Pkts rxd:\t\t\t\t%\"PRIu64\"\\n\",\n\t\t\t\t\t\tapp_stats.rx.rx_pkts);\n\tprintf(\" - Pkts enqd to workers ring:\t\t%\"PRIu64\"\\n\",\n\t\t\t\t\t\tapp_stats.rx.enqueue_pkts);\n\n\tprintf(\"\\nWorker thread stats:\\n\");\n\tprintf(\" - Pkts deqd from workers ring:\t\t%\"PRIu64\"\\n\",\n\t\t\t\t\t\tapp_stats.wkr.dequeue_pkts);\n\tprintf(\" - Pkts enqd to tx ring:\t\t%\"PRIu64\"\\n\",\n\t\t\t\t\t\tapp_stats.wkr.enqueue_pkts);\n\tprintf(\" - Pkts enq to tx failed:\t\t%\"PRIu64\"\\n\",\n\t\t\t\t\t\tapp_stats.wkr.enqueue_failed_pkts);\n\n\tprintf(\"\\nTX stats:\\n\");\n\tprintf(\" - Pkts deqd from tx ring:\t\t%\"PRIu64\"\\n\",\n\t\t\t\t\t\tapp_stats.tx.dequeue_pkts);\n\tprintf(\" - Ro Pkts transmitted:\t\t\t%\"PRIu64\"\\n\",\n\t\t\t\t\t\tapp_stats.tx.ro_tx_pkts);\n\tprintf(\" - Ro Pkts tx failed:\t\t\t%\"PRIu64\"\\n\",\n\t\t\t\t\t\tapp_stats.tx.ro_tx_failed_pkts);\n\tprintf(\" - Pkts transmitted w/o reorder:\t%\"PRIu64\"\\n\",\n\t\t\t\t\t\tapp_stats.tx.early_pkts_txtd_woro);\n\tprintf(\" - Pkts tx failed w/o reorder:\t\t%\"PRIu64\"\\n\",\n\t\t\t\t\t\tapp_stats.tx.early_pkts_tx_failed_woro);\n\n\tfor (i = 0; i < nb_ports; i++) {\n\t\trte_eth_stats_get(i, ð_stats);\n\t\tprintf(\"\\nPort %u stats:\\n\", i);\n\t\tprintf(\" - Pkts in: %\"PRIu64\"\\n\", eth_stats.ipackets);\n\t\tprintf(\" - Pkts out: %\"PRIu64\"\\n\", eth_stats.opackets);\n\t\tprintf(\" - In Errs: %\"PRIu64\"\\n\", eth_stats.ierrors);\n\t\tprintf(\" - Out Errs: %\"PRIu64\"\\n\", eth_stats.oerrors);\n\t\tprintf(\" - Mbuf Errs: %\"PRIu64\"\\n\", eth_stats.rx_nombuf);\n\t}\n}\n\nstatic void\nint_handler(int sig_num)\n{\n\tprintf(\"Exiting on signal %d\\n\", sig_num);\n\tquit_signal = 1;\n}\n\n/**\n * This thread receives mbufs from the port and affects them an internal\n * sequence number to keep track of their order of arrival through an\n * mbuf structure.\n * The mbufs are then passed to the worker threads via the rx_to_workers\n * ring.\n */\nstatic int\nrx_thread(struct rte_ring *ring_out)\n{\n\tconst uint8_t nb_ports = rte_eth_dev_count();\n\tuint32_t seqn = 0;\n\tuint16_t i, ret = 0;\n\tuint16_t nb_rx_pkts;\n\tuint8_t port_id;\n\tstruct rte_mbuf *pkts[MAX_PKTS_BURST];\n\n\tRTE_LOG(INFO, REORDERAPP, \"%s() started on lcore %u\\n\", __func__,\n\t\t\t\t\t\t\trte_lcore_id());\n\n\twhile (!quit_signal) {\n\n\t\tfor (port_id = 0; port_id < nb_ports; port_id++) {\n\t\t\tif ((portmask & (1 << port_id)) != 0) {\n\n\t\t\t\t/* receive packets */\n\t\t\t\tnb_rx_pkts = rte_eth_rx_burst(port_id, 0,\n\t\t\t\t\t\t\t\tpkts, MAX_PKTS_BURST);\n\t\t\t\tif (nb_rx_pkts == 0) {\n\t\t\t\t\tLOG_DEBUG(REORDERAPP,\n\t\t\t\t\t\"%s():Received zero packets\\n\",\t__func__);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tapp_stats.rx.rx_pkts += nb_rx_pkts;\n\n\t\t\t\t/* mark sequence number */\n\t\t\t\tfor (i = 0; i < nb_rx_pkts; )\n\t\t\t\t\tpkts[i++]->seqn = seqn++;\n\n\t\t\t\t/* enqueue to rx_to_workers ring */\n\t\t\t\tret = rte_ring_enqueue_burst(ring_out, (void *) pkts,\n\t\t\t\t\t\t\t\tnb_rx_pkts);\n\t\t\t\tapp_stats.rx.enqueue_pkts += ret;\n\t\t\t\tif (unlikely(ret < nb_rx_pkts)) {\n\t\t\t\t\tapp_stats.rx.enqueue_failed_pkts +=\n\t\t\t\t\t\t\t\t\t(nb_rx_pkts-ret);\n\t\t\t\t\tpktmbuf_free_bulk(&pkts[ret], nb_rx_pkts - ret);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\n/**\n * This thread takes bursts of packets from the rx_to_workers ring and\n * Changes the input port value to output port value. And feds it to\n * workers_to_tx\n */\nstatic int\nworker_thread(void *args_ptr)\n{\n\tconst uint8_t nb_ports = rte_eth_dev_count();\n\tuint16_t i, ret = 0;\n\tuint16_t burst_size = 0;\n\tstruct worker_thread_args *args;\n\tstruct rte_mbuf *burst_buffer[MAX_PKTS_BURST] = { NULL };\n\tstruct rte_ring *ring_in, *ring_out;\n\tconst unsigned xor_val = (nb_ports > 1);\n\n\targs = (struct worker_thread_args *) args_ptr;\n\tring_in = args->ring_in;\n\tring_out = args->ring_out;\n\n\tRTE_LOG(INFO, REORDERAPP, \"%s() started on lcore %u\\n\", __func__,\n\t\t\t\t\t\t\trte_lcore_id());\n\n\twhile (!quit_signal) {\n\n\t\t/* dequeue the mbufs from rx_to_workers ring */\n\t\tburst_size = rte_ring_dequeue_burst(ring_in,\n\t\t\t\t(void *)burst_buffer, MAX_PKTS_BURST);\n\t\tif (unlikely(burst_size == 0))\n\t\t\tcontinue;\n\n\t\t__sync_fetch_and_add(&app_stats.wkr.dequeue_pkts, burst_size);\n\n\t\t/* just do some operation on mbuf */\n\t\tfor (i = 0; i < burst_size;)\n\t\t\tburst_buffer[i++]->port ^= xor_val;\n\n\t\t/* enqueue the modified mbufs to workers_to_tx ring */\n\t\tret = rte_ring_enqueue_burst(ring_out, (void *)burst_buffer, burst_size);\n\t\t__sync_fetch_and_add(&app_stats.wkr.enqueue_pkts, ret);\n\t\tif (unlikely(ret < burst_size)) {\n\t\t\t/* Return the mbufs to their respective pool, dropping packets */\n\t\t\t__sync_fetch_and_add(&app_stats.wkr.enqueue_failed_pkts,\n\t\t\t\t\t(int)burst_size - ret);\n\t\t\tpktmbuf_free_bulk(&burst_buffer[ret], burst_size - ret);\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic inline void\nflush_one_port(struct output_buffer *outbuf, uint8_t outp)\n{\n\tunsigned nb_tx = rte_eth_tx_burst(outp, 0, outbuf->mbufs,\n\t\t\toutbuf->count);\n\tapp_stats.tx.ro_tx_pkts += nb_tx;\n\n\tif (unlikely(nb_tx < outbuf->count)) {\n\t\t/* free the mbufs which failed from transmit */\n\t\tapp_stats.tx.ro_tx_failed_pkts += (outbuf->count - nb_tx);\n\t\tLOG_DEBUG(REORDERAPP, \"%s:Packet loss with tx_burst\\n\", __func__);\n\t\tpktmbuf_free_bulk(&outbuf->mbufs[nb_tx], outbuf->count - nb_tx);\n\t}\n\toutbuf->count = 0;\n}\n\n/**\n * Dequeue mbufs from the workers_to_tx ring and reorder them before\n * transmitting.\n */\nstatic int\nsend_thread(struct send_thread_args *args)\n{\n\tint ret;\n\tunsigned int i, dret;\n\tuint16_t nb_dq_mbufs;\n\tuint8_t outp;\n\tstatic struct output_buffer tx_buffers[RTE_MAX_ETHPORTS];\n\tstruct rte_mbuf *mbufs[MAX_PKTS_BURST];\n\tstruct rte_mbuf *rombufs[MAX_PKTS_BURST] = {NULL};\n\n\tRTE_LOG(INFO, REORDERAPP, \"%s() started on lcore %u\\n\", __func__, rte_lcore_id());\n\n\twhile (!quit_signal) {\n\n\t\t/* deque the mbufs from workers_to_tx ring */\n\t\tnb_dq_mbufs = rte_ring_dequeue_burst(args->ring_in,\n\t\t\t\t(void *)mbufs, MAX_PKTS_BURST);\n\n\t\tif (unlikely(nb_dq_mbufs == 0))\n\t\t\tcontinue;\n\n\t\tapp_stats.tx.dequeue_pkts += nb_dq_mbufs;\n\n\t\tfor (i = 0; i < nb_dq_mbufs; i++) {\n\t\t\t/* send dequeued mbufs for reordering */\n\t\t\tret = rte_reorder_insert(args->buffer, mbufs[i]);\n\n\t\t\tif (ret == -1 && rte_errno == ERANGE) {\n\t\t\t\t/* Too early pkts should be transmitted out directly */\n\t\t\t\tLOG_DEBUG(REORDERAPP, \"%s():Cannot reorder early packet \"\n\t\t\t\t\t\t\"direct enqueuing to TX\\n\", __func__);\n\t\t\t\toutp = mbufs[i]->port;\n\t\t\t\tif ((portmask & (1 << outp)) == 0) {\n\t\t\t\t\trte_pktmbuf_free(mbufs[i]);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\tif (rte_eth_tx_burst(outp, 0, (void *)mbufs[i], 1) != 1) {\n\t\t\t\t\trte_pktmbuf_free(mbufs[i]);\n\t\t\t\t\tapp_stats.tx.early_pkts_tx_failed_woro++;\n\t\t\t\t} else\n\t\t\t\t\tapp_stats.tx.early_pkts_txtd_woro++;\n\t\t\t} else if (ret == -1 && rte_errno == ENOSPC) {\n\t\t\t\t/**\n\t\t\t\t * Early pkts just outside of window should be dropped\n\t\t\t\t */\n\t\t\t\trte_pktmbuf_free(mbufs[i]);\n\t\t\t}\n\t\t}\n\n\t\t/*\n\t\t * drain MAX_PKTS_BURST of reordered\n\t\t * mbufs for transmit\n\t\t */\n\t\tdret = rte_reorder_drain(args->buffer, rombufs, MAX_PKTS_BURST);\n\t\tfor (i = 0; i < dret; i++) {\n\n\t\t\tstruct output_buffer *outbuf;\n\t\t\tuint8_t outp1;\n\n\t\t\toutp1 = rombufs[i]->port;\n\t\t\t/* skip ports that are not enabled */\n\t\t\tif ((portmask & (1 << outp1)) == 0) {\n\t\t\t\trte_pktmbuf_free(rombufs[i]);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\toutbuf = &tx_buffers[outp1];\n\t\t\toutbuf->mbufs[outbuf->count++] = rombufs[i];\n\t\t\tif (outbuf->count == MAX_PKTS_BURST)\n\t\t\t\tflush_one_port(outbuf, outp1);\n\t\t}\n\t}\n\treturn 0;\n}\n\n/**\n * Dequeue mbufs from the workers_to_tx ring and transmit them\n */\nstatic int\ntx_thread(struct rte_ring *ring_in)\n{\n\tuint32_t i, dqnum;\n\tuint8_t outp;\n\tstatic struct output_buffer tx_buffers[RTE_MAX_ETHPORTS];\n\tstruct rte_mbuf *mbufs[MAX_PKTS_BURST];\n\tstruct output_buffer *outbuf;\n\n\tRTE_LOG(INFO, REORDERAPP, \"%s() started on lcore %u\\n\", __func__,\n\t\t\t\t\t\t\trte_lcore_id());\n\twhile (!quit_signal) {\n\n\t\t/* deque the mbufs from workers_to_tx ring */\n\t\tdqnum = rte_ring_dequeue_burst(ring_in,\n\t\t\t\t(void *)mbufs, MAX_PKTS_BURST);\n\n\t\tif (unlikely(dqnum == 0))\n\t\t\tcontinue;\n\n\t\tapp_stats.tx.dequeue_pkts += dqnum;\n\n\t\tfor (i = 0; i < dqnum; i++) {\n\t\t\toutp = mbufs[i]->port;\n\t\t\t/* skip ports that are not enabled */\n\t\t\tif ((portmask & (1 << outp)) == 0) {\n\t\t\t\trte_pktmbuf_free(mbufs[i]);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\toutbuf = &tx_buffers[outp];\n\t\t\toutbuf->mbufs[outbuf->count++] = mbufs[i];\n\t\t\tif (outbuf->count == MAX_PKTS_BURST)\n\t\t\t\tflush_one_port(outbuf, outp);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nint\nmain(int argc, char **argv)\n{\n\tint ret;\n\tunsigned nb_ports;\n\tunsigned int lcore_id, last_lcore_id, master_lcore_id;\n\tuint8_t port_id;\n\tuint8_t nb_ports_available;\n\tstruct worker_thread_args worker_args = {NULL, NULL};\n\tstruct send_thread_args send_args = {NULL, NULL};\n\tstruct rte_ring *rx_to_workers;\n\tstruct rte_ring *workers_to_tx;\n\n\t/* catch ctrl-c so we can print on exit */\n\tsignal(SIGINT, int_handler);\n\n\t/* Initialize EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\treturn -1;\n\n\targc -= ret;\n\targv += ret;\n\n\t/* Parse the application specific arguments */\n\tret = parse_args(argc, argv);\n\tif (ret < 0)\n\t\treturn -1;\n\n\t/* Check if we have enought cores */\n\tif (rte_lcore_count() < 3)\n\t\trte_exit(EXIT_FAILURE, \"Error, This application needs at \"\n\t\t\t\t\"least 3 logical cores to run:\\n\"\n\t\t\t\t\"1 lcore for packet RX\\n\"\n\t\t\t\t\"1 lcore for packet TX\\n\"\n\t\t\t\t\"and at least 1 lcore for worker threads\\n\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports == 0)\n\t\trte_exit(EXIT_FAILURE, \"Error: no ethernet ports detected\\n\");\n\tif (nb_ports != 1 && (nb_ports & 1))\n\t\trte_exit(EXIT_FAILURE, \"Error: number of ports must be even, except \"\n\t\t\t\t\"when using a single port\\n\");\n\n\tmbuf_pool = rte_pktmbuf_pool_create(\"mbuf_pool\", MBUF_PER_POOL,\n\t\t\tMBUF_POOL_CACHE_SIZE, 0, RTE_MBUF_DEFAULT_BUF_SIZE,\n\t\t\trte_socket_id());\n\tif (mbuf_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"%s\\n\", rte_strerror(rte_errno));\n\n\tnb_ports_available = nb_ports;\n\n\t/* initialize all ports */\n\tfor (port_id = 0; port_id < nb_ports; port_id++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((portmask & (1 << port_id)) == 0) {\n\t\t\tprintf(\"\\nSkipping disabled port %d\\n\", port_id);\n\t\t\tnb_ports_available--;\n\t\t\tcontinue;\n\t\t}\n\t\t/* init port */\n\t\tprintf(\"Initializing port %u... done\\n\", (unsigned) port_id);\n\n\t\tif (configure_eth_port(port_id) != 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot initialize port %\"PRIu8\"\\n\",\n\t\t\t\t\tport_id);\n\t}\n\n\tif (!nb_ports_available) {\n\t\trte_exit(EXIT_FAILURE,\n\t\t\t\"All available ports are disabled. Please set portmask.\\n\");\n\t}\n\n\t/* Create rings for inter core communication */\n\trx_to_workers = rte_ring_create(\"rx_to_workers\", RING_SIZE, rte_socket_id(),\n\t\t\tRING_F_SP_ENQ);\n\tif (rx_to_workers == NULL)\n\t\trte_exit(EXIT_FAILURE, \"%s\\n\", rte_strerror(rte_errno));\n\n\tworkers_to_tx = rte_ring_create(\"workers_to_tx\", RING_SIZE, rte_socket_id(),\n\t\t\tRING_F_SC_DEQ);\n\tif (workers_to_tx == NULL)\n\t\trte_exit(EXIT_FAILURE, \"%s\\n\", rte_strerror(rte_errno));\n\n\tif (!disable_reorder) {\n\t\tsend_args.buffer = rte_reorder_create(\"PKT_RO\", rte_socket_id(),\n\t\t\t\tREORDER_BUFFER_SIZE);\n\t\tif (send_args.buffer == NULL)\n\t\t\trte_exit(EXIT_FAILURE, \"%s\\n\", rte_strerror(rte_errno));\n\t}\n\n\tlast_lcore_id = get_last_lcore_id();\n\tmaster_lcore_id = rte_get_master_lcore();\n\n\tworker_args.ring_in = rx_to_workers;\n\tworker_args.ring_out = workers_to_tx;\n\n\t/* Start worker_thread() on all the available slave cores but the last 1 */\n\tfor (lcore_id = 0; lcore_id <= get_previous_lcore_id(last_lcore_id); lcore_id++)\n\t\tif (rte_lcore_is_enabled(lcore_id) && lcore_id != master_lcore_id)\n\t\t\trte_eal_remote_launch(worker_thread, (void *)&worker_args,\n\t\t\t\t\tlcore_id);\n\n\tif (disable_reorder) {\n\t\t/* Start tx_thread() on the last slave core */\n\t\trte_eal_remote_launch((lcore_function_t *)tx_thread, workers_to_tx,\n\t\t\t\tlast_lcore_id);\n\t} else {\n\t\tsend_args.ring_in = workers_to_tx;\n\t\t/* Start send_thread() on the last slave core */\n\t\trte_eal_remote_launch((lcore_function_t *)send_thread,\n\t\t\t\t(void *)&send_args, last_lcore_id);\n\t}\n\n\t/* Start rx_thread() on the master core */\n\trx_thread(rx_to_workers);\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\tprint_stats();\n\treturn 0;\n}\n" }, { "path": "examples/qos_meter/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = qos_meter\n\n# all source are stored in SRCS-y\nSRCS-y := main.c rte_policer.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/qos_meter/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/*\n * Traffic metering configuration\n *\n */\n#define APP_MODE_FWD 0\n#define APP_MODE_SRTCM_COLOR_BLIND 1\n#define APP_MODE_SRTCM_COLOR_AWARE 2\n#define APP_MODE_TRTCM_COLOR_BLIND 3\n#define APP_MODE_TRTCM_COLOR_AWARE 4\n\n#define APP_MODE\tAPP_MODE_SRTCM_COLOR_BLIND\n\n\n#include \"main.h\"\n\n\n#define APP_PKT_FLOW_POS 33\n#define APP_PKT_COLOR_POS 5\n\n\n#if APP_PKT_FLOW_POS > 64 || APP_PKT_COLOR_POS > 64\n#error Byte offset needs to be less than 64\n#endif\n\n/*\n * Buffer pool configuration\n *\n ***/\n#define NB_MBUF 8192\n#define MEMPOOL_CACHE_SIZE 256\n\nstatic struct rte_mempool *pool = NULL;\n\n/*\n * NIC configuration\n *\n ***/\nstatic struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.mq_mode\t= ETH_MQ_RX_RSS,\n\t\t.max_rx_pkt_len = ETHER_MAX_LEN,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0,\n\t\t.hw_ip_checksum = 1,\n\t\t.hw_vlan_filter = 0,\n\t\t.jumbo_frame = 0,\n\t\t.hw_strip_crc = 0,\n\t},\n\t.rx_adv_conf = {\n\t\t.rss_conf = {\n\t\t\t.rss_key = NULL,\n\t\t\t.rss_hf = ETH_RSS_IP,\n\t\t},\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_DCB_NONE,\n\t},\n};\n\n#define NIC_RX_QUEUE_DESC 128\n#define NIC_TX_QUEUE_DESC 512\n\n#define NIC_RX_QUEUE 0\n#define NIC_TX_QUEUE 0\n\n/*\n * Packet RX/TX\n *\n ***/\n#define PKT_RX_BURST_MAX 32\n#define PKT_TX_BURST_MAX 32\n#define TIME_TX_DRAIN 200000ULL\n\nstatic uint8_t port_rx;\nstatic uint8_t port_tx;\nstatic struct rte_mbuf *pkts_rx[PKT_RX_BURST_MAX];\nstatic struct rte_mbuf *pkts_tx[PKT_TX_BURST_MAX];\nstatic uint16_t pkts_tx_len = 0;\n\n\nstruct rte_meter_srtcm_params app_srtcm_params[] = {\n\t{.cir = 1000000 * 46, .cbs = 2048, .ebs = 2048},\n};\n\nstruct rte_meter_trtcm_params app_trtcm_params[] = {\n\t{.cir = 1000000 * 46, .pir = 1500000 * 46, .cbs = 2048, .pbs = 2048},\n};\n\n#define APP_FLOWS_MAX 256\n\nFLOW_METER app_flows[APP_FLOWS_MAX];\n\nstatic void\napp_configure_flow_table(void)\n{\n\tuint32_t i, j;\n\n\tfor (i = 0, j = 0; i < APP_FLOWS_MAX; i ++, j = (j + 1) % RTE_DIM(PARAMS)){\n\t\tFUNC_CONFIG(&app_flows[i], &PARAMS[j]);\n\t}\n}\n\nstatic inline void\napp_set_pkt_color(uint8_t *pkt_data, enum policer_action color)\n{\n\tpkt_data[APP_PKT_COLOR_POS] = (uint8_t)color;\n}\n\nstatic inline int\napp_pkt_handle(struct rte_mbuf *pkt, uint64_t time)\n{\n\tuint8_t input_color, output_color;\n\tuint8_t *pkt_data = rte_pktmbuf_mtod(pkt, uint8_t *);\n\tuint32_t pkt_len = rte_pktmbuf_pkt_len(pkt) - sizeof(struct ether_hdr);\n\tuint8_t flow_id = (uint8_t)(pkt_data[APP_PKT_FLOW_POS] & (APP_FLOWS_MAX - 1));\n\tinput_color = pkt_data[APP_PKT_COLOR_POS];\n\tenum policer_action action;\n\n\t/* color input is not used for blind modes */\n\toutput_color = (uint8_t) FUNC_METER(&app_flows[flow_id], time, pkt_len,\n\t\t(enum rte_meter_color) input_color);\n\n\t/* Apply policing and set the output color */\n\taction = policer_table[input_color][output_color];\n\tapp_set_pkt_color(pkt_data, action);\n\n\treturn action;\n}\n\n\nstatic __attribute__((noreturn)) int\nmain_loop(__attribute__((unused)) void *dummy)\n{\n\tuint64_t current_time, last_time = rte_rdtsc();\n\tuint32_t lcore_id = rte_lcore_id();\n\n\tprintf(\"Core %u: port RX = %d, port TX = %d\\n\", lcore_id, port_rx, port_tx);\n\n\twhile (1) {\n\t\tuint64_t time_diff;\n\t\tint i, nb_rx;\n\n\t\t/* Mechanism to avoid stale packets in the output buffer */\n\t\tcurrent_time = rte_rdtsc();\n\t\ttime_diff = current_time - last_time;\n\t\tif (unlikely(time_diff > TIME_TX_DRAIN)) {\n\t\t\tint ret;\n\n\t\t\tif (pkts_tx_len == 0) {\n\t\t\t\tlast_time = current_time;\n\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\t/* Write packet burst to NIC TX */\n\t\t\tret = rte_eth_tx_burst(port_tx, NIC_TX_QUEUE, pkts_tx, pkts_tx_len);\n\n\t\t\t/* Free buffers for any packets not written successfully */\n\t\t\tif (unlikely(ret < pkts_tx_len)) {\n\t\t\t\tfor ( ; ret < pkts_tx_len; ret ++) {\n\t\t\t\t\trte_pktmbuf_free(pkts_tx[ret]);\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Empty the output buffer */\n\t\t\tpkts_tx_len = 0;\n\n\t\t\tlast_time = current_time;\n\t\t}\n\n\t\t/* Read packet burst from NIC RX */\n\t\tnb_rx = rte_eth_rx_burst(port_rx, NIC_RX_QUEUE, pkts_rx, PKT_RX_BURST_MAX);\n\n\t\t/* Handle packets */\n\t\tfor (i = 0; i < nb_rx; i ++) {\n\t\t\tstruct rte_mbuf *pkt = pkts_rx[i];\n\n\t\t\t/* Handle current packet */\n\t\t\tif (app_pkt_handle(pkt, current_time) == DROP)\n\t\t\t\trte_pktmbuf_free(pkt);\n\t\t\telse {\n\t\t\t\tpkts_tx[pkts_tx_len] = pkt;\n\t\t\t\tpkts_tx_len ++;\n\t\t\t}\n\n\t\t\t/* Write packets from output buffer to NIC TX when full burst is available */\n\t\t\tif (unlikely(pkts_tx_len == PKT_TX_BURST_MAX)) {\n\t\t\t\t/* Write packet burst to NIC TX */\n\t\t\t\tint ret = rte_eth_tx_burst(port_tx, NIC_TX_QUEUE, pkts_tx, PKT_TX_BURST_MAX);\n\n\t\t\t\t/* Free buffers for any packets not written successfully */\n\t\t\t\tif (unlikely(ret < PKT_TX_BURST_MAX)) {\n\t\t\t\t\tfor ( ; ret < PKT_TX_BURST_MAX; ret ++) {\n\t\t\t\t\t\trte_pktmbuf_free(pkts_tx[ret]);\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\t/* Empty the output buffer */\n\t\t\t\tpkts_tx_len = 0;\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic void\nprint_usage(const char *prgname)\n{\n\tprintf (\"%s [EAL options] -- -p PORTMASK\\n\"\n\t\t\" -p PORTMASK: hexadecimal bitmask of ports to configure\\n\",\n\t\tprgname);\n}\n\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\nparse_args(int argc, char **argv)\n{\n\tint opt;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstatic struct option lgopts[] = {\n\t\t{NULL, 0, 0, 0}\n\t};\n\tuint64_t port_mask, i, mask;\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, \"p:\", lgopts, &option_index)) != EOF) {\n\t\tswitch (opt) {\n\t\tcase 'p':\n\t\t\tport_mask = parse_portmask(optarg);\n\t\t\tif (port_mask == 0) {\n\t\t\t\tprintf(\"invalid port mask (null port mask)\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tfor (i = 0, mask = 1; i < 64; i ++, mask <<= 1){\n\t\t\t\tif (mask & port_mask){\n\t\t\t\t\tport_rx = i;\n\t\t\t\t\tport_mask &= ~ mask;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tfor (i = 0, mask = 1; i < 64; i ++, mask <<= 1){\n\t\t\t\tif (mask & port_mask){\n\t\t\t\t\tport_tx = i;\n\t\t\t\t\tport_mask &= ~ mask;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (port_mask != 0) {\n\t\t\t\tprintf(\"invalid port mask (more than 2 ports)\\n\");\n\t\t\t\tprint_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tprint_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (optind <= 1) {\n\t\tprint_usage(prgname);\n\t\treturn -1;\n\t}\n\n\targv[optind-1] = prgname;\n\n\toptind = 0; /* reset getopt lib */\n\treturn 0;\n}\n\nint\nmain(int argc, char **argv)\n{\n\tuint32_t lcore_id;\n\tint ret;\n\n\t/* EAL init */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid EAL parameters\\n\");\n\targc -= ret;\n\targv += ret;\n\tif (rte_lcore_count() != 1) {\n\t\trte_exit(EXIT_FAILURE, \"This application does not accept more than one core. \"\n\t\t\"Please adjust the \\\"-c COREMASK\\\" parameter accordingly.\\n\");\n\t}\n\n\t/* Application non-EAL arguments parse */\n\tret = parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid input arguments\\n\");\n\n\t/* Buffer pool init */\n\tpool = rte_pktmbuf_pool_create(\"pool\", NB_MBUF, MEMPOOL_CACHE_SIZE,\n\t\t0, RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\tif (pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Buffer pool creation error\\n\");\n\n\t/* NIC init */\n\tret = rte_eth_dev_configure(port_rx, 1, 1, &port_conf);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Port %d configuration error (%d)\\n\", port_rx, ret);\n\n\tret = rte_eth_rx_queue_setup(port_rx, NIC_RX_QUEUE, NIC_RX_QUEUE_DESC,\n\t\t\t\trte_eth_dev_socket_id(port_rx),\n\t\t\t\tNULL, pool);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Port %d RX queue setup error (%d)\\n\", port_rx, ret);\n\n\tret = rte_eth_tx_queue_setup(port_rx, NIC_TX_QUEUE, NIC_TX_QUEUE_DESC,\n\t\t\t\trte_eth_dev_socket_id(port_rx),\n\t\t\t\tNULL);\n\tif (ret < 0)\n\trte_exit(EXIT_FAILURE, \"Port %d TX queue setup error (%d)\\n\", port_rx, ret);\n\n\tret = rte_eth_dev_configure(port_tx, 1, 1, &port_conf);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Port %d configuration error (%d)\\n\", port_tx, ret);\n\n\tret = rte_eth_rx_queue_setup(port_tx, NIC_RX_QUEUE, NIC_RX_QUEUE_DESC,\n\t\t\t\trte_eth_dev_socket_id(port_tx),\n\t\t\t\tNULL, pool);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Port %d RX queue setup error (%d)\\n\", port_tx, ret);\n\n\tret = rte_eth_tx_queue_setup(port_tx, NIC_TX_QUEUE, NIC_TX_QUEUE_DESC,\n\t\t\t\trte_eth_dev_socket_id(port_tx),\n\t\t\t\tNULL);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Port %d TX queue setup error (%d)\\n\", port_tx, ret);\n\n\tret = rte_eth_dev_start(port_rx);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Port %d start error (%d)\\n\", port_rx, ret);\n\n\tret = rte_eth_dev_start(port_tx);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Port %d start error (%d)\\n\", port_tx, ret);\n\n\trte_eth_promiscuous_enable(port_rx);\n\n\trte_eth_promiscuous_enable(port_tx);\n\n\t/* App configuration */\n\tapp_configure_flow_table();\n\n\t/* Launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(main_loop, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/qos_meter/main.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _MAIN_H_\n#define _MAIN_H_\n\nenum policer_action {\n GREEN = e_RTE_METER_GREEN,\n YELLOW = e_RTE_METER_YELLOW,\n RED = e_RTE_METER_RED,\n DROP = 3,\n};\n\nenum policer_action policer_table[e_RTE_METER_COLORS][e_RTE_METER_COLORS] =\n{\n\t{ GREEN, RED, RED},\n\t{ DROP, YELLOW, RED},\n\t{ DROP, DROP, RED}\n};\n\n#if APP_MODE == APP_MODE_FWD\n\n#define FUNC_METER(a,b,c,d) color, flow_id=flow_id, pkt_len=pkt_len, time=time\n#define FUNC_CONFIG(a,b)\n#define PARAMS\tapp_srtcm_params\n#define FLOW_METER int\n\n#elif APP_MODE == APP_MODE_SRTCM_COLOR_BLIND\n\n#define FUNC_METER(a,b,c,d) rte_meter_srtcm_color_blind_check(a,b,c)\n#define FUNC_CONFIG rte_meter_srtcm_config\n#define PARAMS app_srtcm_params\n#define FLOW_METER struct rte_meter_srtcm\n\n#elif (APP_MODE == APP_MODE_SRTCM_COLOR_AWARE)\n\n#define FUNC_METER rte_meter_srtcm_color_aware_check\n#define FUNC_CONFIG rte_meter_srtcm_config\n#define PARAMS app_srtcm_params\n#define FLOW_METER struct rte_meter_srtcm\n\n#elif (APP_MODE == APP_MODE_TRTCM_COLOR_BLIND)\n\n#define FUNC_METER(a,b,c,d) rte_meter_trtcm_color_blind_check(a,b,c)\n#define FUNC_CONFIG rte_meter_trtcm_config\n#define PARAMS app_trtcm_params\n#define FLOW_METER struct rte_meter_trtcm\n\n#elif (APP_MODE == APP_MODE_TRTCM_COLOR_AWARE)\n\n#define FUNC_METER rte_meter_trtcm_color_aware_check\n#define FUNC_CONFIG rte_meter_trtcm_config\n#define PARAMS app_trtcm_params\n#define FLOW_METER struct rte_meter_trtcm\n\n#else\n#error Invalid value for APP_MODE\n#endif\n\n\n\n\n#endif /* _MAIN_H_ */\n" }, { "path": "examples/qos_meter/rte_policer.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \"rte_policer.h\"\n\nint\nrte_phb_config(struct rte_phb *phb_table, uint32_t phb_table_index,\n\tenum rte_meter_color pre_meter, enum rte_meter_color post_meter, enum rte_phb_action action)\n{\n\tstruct rte_phb *phb = NULL;\n\n\t/* User argument checking */\n\tif (phb_table == NULL) {\n\t\treturn -1;\n\t}\n\n\tif ((pre_meter > e_RTE_METER_RED) || (post_meter > e_RTE_METER_RED) || (pre_meter > post_meter)) {\n\t\treturn -2;\n\t}\n\n\t/* Set action in PHB table entry */\n\tphb = &phb_table[phb_table_index];\n\tphb->actions[pre_meter][post_meter] = action;\n\n\n\treturn 0;\n}\n" }, { "path": "examples/qos_meter/rte_policer.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_POLICER_H__\n#define __INCLUDE_RTE_POLICER_H__\n\n#include \n#include \n\nenum rte_phb_action {\n\te_RTE_PHB_ACTION_GREEN = e_RTE_METER_GREEN,\n\te_RTE_PHB_ACTION_YELLOW = e_RTE_METER_YELLOW,\n\te_RTE_PHB_ACTION_RED = e_RTE_METER_RED,\n\te_RTE_PHB_ACTION_DROP = 3,\n};\n\nstruct rte_phb {\n\tenum rte_phb_action actions[e_RTE_METER_COLORS][e_RTE_METER_COLORS];\n};\n\nint\nrte_phb_config(struct rte_phb *phb_table, uint32_t phb_table_index,\n\tenum rte_meter_color pre_meter, enum rte_meter_color post_meter, enum rte_phb_action action);\n\nstatic inline enum rte_phb_action\npolicer_run(struct rte_phb *phb_table, uint32_t phb_table_index, enum rte_meter_color pre_meter, enum rte_meter_color post_meter)\n{\n\tstruct rte_phb *phb = &phb_table[phb_table_index];\n\tenum rte_phb_action action = phb->actions[pre_meter][post_meter];\n\n\treturn action;\n}\n\n#endif\n" }, { "path": "examples/qos_sched/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifneq ($(CONFIG_RTE_EXEC_ENV),\"linuxapp\")\n$(info This application can only operate in a linuxapp environment, \\\nplease change the definition of the RTE_TARGET environment variable)\nall:\nelse\n\n# binary name\nAPP = qos_sched\n\n# all source are stored in SRCS-y\nSRCS-y := main.c args.c init.c app_thread.c cfg_file.c cmdline.c stats.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\nCFLAGS_args.o := -D_GNU_SOURCE\nCFLAGS_cfg_file.o := -D_GNU_SOURCE\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n\nendif\n" }, { "path": "examples/qos_sched/app_thread.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\n/*\n * QoS parameters are encoded as follows:\n *\t\tOuter VLAN ID defines subport\n *\t\tInner VLAN ID defines pipe\n *\t\tDestination IP 0.0.XXX.0 defines traffic class\n *\t\tDestination IP host (0.0.0.XXX) defines queue\n * Values below define offset to each field from start of frame\n */\n#define SUBPORT_OFFSET\t7\n#define PIPE_OFFSET\t\t9\n#define TC_OFFSET\t\t20\n#define QUEUE_OFFSET\t20\n#define COLOR_OFFSET\t19\n\nstatic inline int\nget_pkt_sched(struct rte_mbuf *m, uint32_t *subport, uint32_t *pipe,\n\t\t\tuint32_t *traffic_class, uint32_t *queue, uint32_t *color)\n{\n\tuint16_t *pdata = rte_pktmbuf_mtod(m, uint16_t *);\n\n\t*subport = (rte_be_to_cpu_16(pdata[SUBPORT_OFFSET]) & 0x0FFF) &\n\t\t\t(port_params.n_subports_per_port - 1); /* Outer VLAN ID*/\n\t*pipe = (rte_be_to_cpu_16(pdata[PIPE_OFFSET]) & 0x0FFF) &\n\t\t\t(port_params.n_pipes_per_subport - 1); /* Inner VLAN ID */\n\t*traffic_class = (pdata[QUEUE_OFFSET] & 0x0F) &\n\t\t\t(RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE - 1); /* Destination IP */\n\t*queue = ((pdata[QUEUE_OFFSET] >> 8) & 0x0F) &\n\t\t\t(RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS - 1) ; /* Destination IP */\n\t*color = pdata[COLOR_OFFSET] & 0x03; \t/* Destination IP */\n\n\treturn 0;\n}\n\nvoid\napp_rx_thread(struct thread_conf **confs)\n{\n\tuint32_t i, nb_rx;\n\tstruct rte_mbuf *rx_mbufs[burst_conf.rx_burst] __rte_cache_aligned;\n\tstruct thread_conf *conf;\n\tint conf_idx = 0;\n\n\tuint32_t subport;\n\tuint32_t pipe;\n\tuint32_t traffic_class;\n\tuint32_t queue;\n\tuint32_t color;\n\n\twhile ((conf = confs[conf_idx])) {\n\t\tnb_rx = rte_eth_rx_burst(conf->rx_port, conf->rx_queue, rx_mbufs,\n\t\t\t\tburst_conf.rx_burst);\n\n\t\tif (likely(nb_rx != 0)) {\n\t\t\tAPP_STATS_ADD(conf->stat.nb_rx, nb_rx);\n\n\t\t\tfor(i = 0; i < nb_rx; i++) {\n\t\t\t\tget_pkt_sched(rx_mbufs[i],\n\t\t\t\t\t\t&subport, &pipe, &traffic_class, &queue, &color);\n\t\t\t\trte_sched_port_pkt_write(rx_mbufs[i], subport, pipe,\n\t\t\t\t\t\ttraffic_class, queue, (enum rte_meter_color) color);\n\t\t\t}\n\n\t\t\tif (unlikely(rte_ring_sp_enqueue_bulk(conf->rx_ring,\n\t\t\t\t\t\t\t\t(void **)rx_mbufs, nb_rx) != 0)) {\n\t\t\t\tfor(i = 0; i < nb_rx; i++) {\n\t\t\t\t\trte_pktmbuf_free(rx_mbufs[i]);\n\n\t\t\t\t\tAPP_STATS_ADD(conf->stat.nb_drop, 1);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tconf_idx++;\n\t\tif (confs[conf_idx] == NULL)\n\t\t\tconf_idx = 0;\n\t}\n}\n\n\n\n/* Send the packet to an output interface\n * For performance reason function returns number of packets dropped, not sent,\n * so 0 means that all packets were sent successfully\n */\n\nstatic inline void\napp_send_burst(struct thread_conf *qconf)\n{\n\tstruct rte_mbuf **mbufs;\n\tuint32_t n, ret;\n\n\tmbufs = (struct rte_mbuf **)qconf->m_table;\n\tn = qconf->n_mbufs;\n\n\tdo {\n\t\tret = rte_eth_tx_burst(qconf->tx_port, qconf->tx_queue, mbufs, (uint16_t)n);\n\t\t/* we cannot drop the packets, so re-send */\n\t\t/* update number of packets to be sent */\n\t\tn -= ret;\n\t\tmbufs = (struct rte_mbuf **)&mbufs[ret];\n\t} while (n);\n}\n\n\n/* Send the packet to an output interface */\nstatic void\napp_send_packets(struct thread_conf *qconf, struct rte_mbuf **mbufs, uint32_t nb_pkt)\n{\n\tuint32_t i, len;\n\n\tlen = qconf->n_mbufs;\n\tfor(i = 0; i < nb_pkt; i++) {\n\t\tqconf->m_table[len] = mbufs[i];\n\t\tlen++;\n\t\t/* enough pkts to be sent */\n\t\tif (unlikely(len == burst_conf.tx_burst)) {\n\t\t\tqconf->n_mbufs = len;\n\t\t\tapp_send_burst(qconf);\n\t\t\tlen = 0;\n\t\t}\n\t}\n\n\tqconf->n_mbufs = len;\n}\n\nvoid\napp_tx_thread(struct thread_conf **confs)\n{\n\tstruct rte_mbuf *mbufs[burst_conf.qos_dequeue];\n\tstruct thread_conf *conf;\n\tint conf_idx = 0;\n\tint retval;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\twhile ((conf = confs[conf_idx])) {\n\t\tretval = rte_ring_sc_dequeue_bulk(conf->tx_ring, (void **)mbufs,\n\t\t\t\t\tburst_conf.qos_dequeue);\n\t\tif (likely(retval == 0)) {\n\t\t\tapp_send_packets(conf, mbufs, burst_conf.qos_dequeue);\n\n\t\t\tconf->counter = 0; /* reset empty read loop counter */\n\t\t}\n\n\t\tconf->counter++;\n\n\t\t/* drain ring and TX queues */\n\t\tif (unlikely(conf->counter > drain_tsc)) {\n\t\t\t/* now check is there any packets left to be transmitted */\n\t\t\tif (conf->n_mbufs != 0) {\n\t\t\t\tapp_send_burst(conf);\n\n\t\t\t\tconf->n_mbufs = 0;\n\t\t\t}\n\t\t\tconf->counter = 0;\n\t\t}\n\n\t\tconf_idx++;\n\t\tif (confs[conf_idx] == NULL)\n\t\t\tconf_idx = 0;\n\t}\n}\n\n\nvoid\napp_worker_thread(struct thread_conf **confs)\n{\n\tstruct rte_mbuf *mbufs[burst_conf.ring_burst];\n\tstruct thread_conf *conf;\n\tint conf_idx = 0;\n\n\twhile ((conf = confs[conf_idx])) {\n\t\tuint32_t nb_pkt;\n\t\tint retval;\n\n\t\t/* Read packet from the ring */\n\t\tretval = rte_ring_sc_dequeue_bulk(conf->rx_ring, (void **)mbufs,\n\t\t\t\t\tburst_conf.ring_burst);\n\t\tif (likely(retval == 0)) {\n\t\t\tint nb_sent = rte_sched_port_enqueue(conf->sched_port, mbufs,\n\t\t\t\t\tburst_conf.ring_burst);\n\n\t\t\tAPP_STATS_ADD(conf->stat.nb_drop, burst_conf.ring_burst - nb_sent);\n\t\t\tAPP_STATS_ADD(conf->stat.nb_rx, burst_conf.ring_burst);\n\t\t}\n\n\t\tnb_pkt = rte_sched_port_dequeue(conf->sched_port, mbufs,\n\t\t\t\t\tburst_conf.qos_dequeue);\n\t\tif (likely(nb_pkt > 0))\n\t\t\twhile (rte_ring_sp_enqueue_bulk(conf->tx_ring, (void **)mbufs, nb_pkt) != 0);\n\n\t\tconf_idx++;\n\t\tif (confs[conf_idx] == NULL)\n\t\t\tconf_idx = 0;\n\t}\n}\n\n\nvoid\napp_mixed_thread(struct thread_conf **confs)\n{\n\tstruct rte_mbuf *mbufs[burst_conf.ring_burst];\n\tstruct thread_conf *conf;\n\tint conf_idx = 0;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\n\twhile ((conf = confs[conf_idx])) {\n\t\tuint32_t nb_pkt;\n\t\tint retval;\n\n\t\t/* Read packet from the ring */\n\t\tretval = rte_ring_sc_dequeue_bulk(conf->rx_ring, (void **)mbufs,\n\t\t\t\t\tburst_conf.ring_burst);\n\t\tif (likely(retval == 0)) {\n\t\t\tint nb_sent = rte_sched_port_enqueue(conf->sched_port, mbufs,\n\t\t\t\t\tburst_conf.ring_burst);\n\n\t\t\tAPP_STATS_ADD(conf->stat.nb_drop, burst_conf.ring_burst - nb_sent);\n\t\t\tAPP_STATS_ADD(conf->stat.nb_rx, burst_conf.ring_burst);\n\t\t}\n\n\n\t\tnb_pkt = rte_sched_port_dequeue(conf->sched_port, mbufs,\n\t\t\t\t\tburst_conf.qos_dequeue);\n\t\tif (likely(nb_pkt > 0)) {\n\t\t\tapp_send_packets(conf, mbufs, nb_pkt);\n\n\t\t\tconf->counter = 0; /* reset empty read loop counter */\n\t\t}\n\n\t\tconf->counter++;\n\n\t\t/* drain ring and TX queues */\n\t\tif (unlikely(conf->counter > drain_tsc)) {\n\n\t\t\t/* now check is there any packets left to be transmitted */\n\t\t\tif (conf->n_mbufs != 0) {\n\t\t\t\tapp_send_burst(conf);\n\n\t\t\t\tconf->n_mbufs = 0;\n\t\t\t}\n\t\t\tconf->counter = 0;\n\t\t}\n\n\t\tconf_idx++;\n\t\tif (confs[conf_idx] == NULL)\n\t\t\tconf_idx = 0;\n\t}\n}\n" }, { "path": "examples/qos_sched/args.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\n#define APP_NAME \"qos_sched\"\n#define MAX_OPT_VALUES 8\n#define SYS_CPU_DIR \"/sys/devices/system/cpu/cpu%u/topology/\"\n\nstatic uint32_t app_master_core = 1;\nstatic uint32_t app_numa_mask;\nstatic uint64_t app_used_core_mask = 0;\nstatic uint64_t app_used_port_mask = 0;\nstatic uint64_t app_used_rx_port_mask = 0;\nstatic uint64_t app_used_tx_port_mask = 0;\n\n\nstatic const char usage[] =\n\t\" \\n\"\n\t\" %s \\n\"\n\t\" \\n\"\n\t\"Application mandatory parameters: \\n\"\n\t\" --pfc \\\"RX PORT, TX PORT, RX LCORE, WT LCORE\\\" : Packet flow configuration \\n\"\n\t\" multiple pfc can be configured in command line \\n\"\n\t\" \\n\"\n\t\"Application optional parameters: \\n\"\n \" --i : run in interactive mode (default value is %u) \\n\"\n\t\" --mst I : master core index (default value is %u) \\n\"\n\t\" --rsz \\\"A, B, C\\\" : Ring sizes \\n\"\n\t\" A = Size (in number of buffer descriptors) of each of the NIC RX \\n\"\n\t\" rings read by the I/O RX lcores (default value is %u) \\n\"\n\t\" B = Size (in number of elements) of each of the SW rings used by the\\n\"\n\t\" I/O RX lcores to send packets to worker lcores (default value is\\n\"\n\t\" %u) \\n\"\n\t\" C = Size (in number of buffer descriptors) of each of the NIC TX \\n\"\n\t\" rings written by worker lcores (default value is %u) \\n\"\n\t\" --bsz \\\"A, B, C, D\\\": Burst sizes \\n\"\n\t\" A = I/O RX lcore read burst size from NIC RX (default value is %u) \\n\"\n\t\" B = I/O RX lcore write burst size to output SW rings, \\n\"\n\t\" Worker lcore read burst size from input SW rings, \\n\"\n\t\" QoS enqueue size (default value is %u) \\n\"\n\t\" C = QoS dequeue size (default value is %u) \\n\"\n\t\" D = Worker lcore write burst size to NIC TX (default value is %u) \\n\"\n\t\" --msz M : Mempool size (in number of mbufs) for each pfc (default %u) \\n\"\n\t\" --rth \\\"A, B, C\\\" : RX queue threshold parameters \\n\"\n\t\" A = RX prefetch threshold (default value is %u) \\n\"\n\t\" B = RX host threshold (default value is %u) \\n\"\n\t\" C = RX write-back threshold (default value is %u) \\n\"\n\t\" --tth \\\"A, B, C\\\" : TX queue threshold parameters \\n\"\n\t\" A = TX prefetch threshold (default value is %u) \\n\"\n\t\" B = TX host threshold (default value is %u) \\n\"\n\t\" C = TX write-back threshold (default value is %u) \\n\"\n\t\" --cfg FILE : profile configuration to load \\n\"\n;\n\n/* display usage */\nstatic void\napp_usage(const char *prgname)\n{\n\tprintf(usage, prgname, APP_INTERACTIVE_DEFAULT, app_master_core,\n\t\tAPP_RX_DESC_DEFAULT, APP_RING_SIZE, APP_TX_DESC_DEFAULT,\n\t\tMAX_PKT_RX_BURST, PKT_ENQUEUE, PKT_DEQUEUE,\n\t\tMAX_PKT_TX_BURST, NB_MBUF,\n\t\tRX_PTHRESH, RX_HTHRESH, RX_WTHRESH,\n\t\tTX_PTHRESH, TX_HTHRESH, TX_WTHRESH\n\t\t);\n}\n\nstatic inline int str_is(const char *str, const char *is)\n{\n\treturn (strcmp(str, is) == 0);\n}\n\n/* returns core mask used by DPDK */\nstatic uint64_t\napp_eal_core_mask(void)\n{\n\tuint32_t i;\n\tuint64_t cm = 0;\n\tstruct rte_config *cfg = rte_eal_get_configuration();\n\n\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n\t\tif (cfg->lcore_role[i] == ROLE_RTE)\n\t\t\tcm |= (1ULL << i);\n\t}\n\n\tcm |= (1ULL << cfg->master_lcore);\n\n\treturn cm;\n}\n\n\n/* returns total number of cores presented in a system */\nstatic uint32_t\napp_cpu_core_count(void)\n{\n\tint i, len;\n\tchar path[PATH_MAX];\n\tuint32_t ncores = 0;\n\n\tfor(i = 0; i < RTE_MAX_LCORE; i++) {\n\t\tlen = snprintf(path, sizeof(path), SYS_CPU_DIR, i);\n\t\tif (len <= 0 || (unsigned)len >= sizeof(path))\n\t\t\tcontinue;\n\n\t\tif (access(path, F_OK) == 0)\n\t\t\tncores++;\n\t}\n\n\treturn ncores;\n}\n\n/* returns:\n\t number of values parsed\n\t-1 in case of error\n*/\nstatic int\napp_parse_opt_vals(const char *conf_str, char separator, uint32_t n_vals, uint32_t *opt_vals)\n{\n\tchar *string;\n\tuint32_t i, n_tokens;\n\tchar *tokens[MAX_OPT_VALUES];\n\n\tif (conf_str == NULL || opt_vals == NULL || n_vals == 0 || n_vals > MAX_OPT_VALUES)\n\t\treturn -1;\n\n\t/* duplicate configuration string before splitting it to tokens */\n\tstring = strdup(conf_str);\n\tif (string == NULL)\n\t\treturn -1;\n\n\tn_tokens = rte_strsplit(string, strnlen(string, 32), tokens, n_vals, separator);\n\n\tfor(i = 0; i < n_tokens; i++) {\n\t\topt_vals[i] = (uint32_t)atol(tokens[i]);\n\t}\n\n\tfree(string);\n\n\treturn n_tokens;\n}\n\nstatic int\napp_parse_ring_conf(const char *conf_str)\n{\n\tint ret;\n\tuint32_t vals[3];\n\n\tret = app_parse_opt_vals(conf_str, ',', 3, vals);\n\tif (ret != 3)\n\t\treturn ret;\n\n\tring_conf.rx_size = vals[0];\n\tring_conf.ring_size = vals[1];\n\tring_conf.tx_size = vals[2];\n\n\treturn 0;\n}\n\nstatic int\napp_parse_rth_conf(const char *conf_str)\n{\n\tint ret;\n\tuint32_t vals[3];\n\n\tret = app_parse_opt_vals(conf_str, ',', 3, vals);\n\tif (ret != 3)\n\t\treturn ret;\n\n\trx_thresh.pthresh = (uint8_t)vals[0];\n\trx_thresh.hthresh = (uint8_t)vals[1];\n\trx_thresh.wthresh = (uint8_t)vals[2];\n\n\treturn 0;\n}\n\nstatic int\napp_parse_tth_conf(const char *conf_str)\n{\n\tint ret;\n\tuint32_t vals[3];\n\n\tret = app_parse_opt_vals(conf_str, ',', 3, vals);\n\tif (ret != 3)\n\t\treturn ret;\n\n\ttx_thresh.pthresh = (uint8_t)vals[0];\n\ttx_thresh.hthresh = (uint8_t)vals[1];\n\ttx_thresh.wthresh = (uint8_t)vals[2];\n\n\treturn 0;\n}\n\nstatic int\napp_parse_flow_conf(const char *conf_str)\n{\n\tint ret;\n\tuint32_t vals[5];\n\tstruct flow_conf *pconf;\n\tuint64_t mask;\n\n\tret = app_parse_opt_vals(conf_str, ',', 6, vals);\n\tif (ret < 4 || ret > 5)\n\t\treturn ret;\n\n\tpconf = &qos_conf[nb_pfc];\n\n\tpconf->rx_port = (uint8_t)vals[0];\n\tpconf->tx_port = (uint8_t)vals[1];\n\tpconf->rx_core = (uint8_t)vals[2];\n\tpconf->wt_core = (uint8_t)vals[3];\n\tif (ret == 5)\n\t\tpconf->tx_core = (uint8_t)vals[4];\n\telse\n\t\tpconf->tx_core = pconf->wt_core;\n\n\tif (pconf->rx_core == pconf->wt_core) {\n\t\tRTE_LOG(ERR, APP, \"pfc %u: rx thread and worker thread cannot share same core\\n\", nb_pfc);\n\t\treturn -1;\n\t}\n\n\tif (pconf->rx_port >= RTE_MAX_ETHPORTS) {\n\t\tRTE_LOG(ERR, APP, \"pfc %u: invalid rx port %\"PRIu8\" index\\n\",\n\t\t\t\tnb_pfc, pconf->rx_port);\n\t\treturn -1;\n\t}\n\tif (pconf->tx_port >= RTE_MAX_ETHPORTS) {\n\t\tRTE_LOG(ERR, APP, \"pfc %u: invalid tx port %\"PRIu8\" index\\n\",\n\t\t\t\tnb_pfc, pconf->rx_port);\n\t\treturn -1;\n\t}\n\n\tmask = 1lu << pconf->rx_port;\n\tif (app_used_rx_port_mask & mask) {\n\t\tRTE_LOG(ERR, APP, \"pfc %u: rx port %\"PRIu8\" is used already\\n\",\n\t\t\t\tnb_pfc, pconf->rx_port);\n\t\treturn -1;\n\t}\n\tapp_used_rx_port_mask |= mask;\n\tapp_used_port_mask |= mask;\n\n\tmask = 1lu << pconf->tx_port;\n\tif (app_used_tx_port_mask & mask) {\n\t\tRTE_LOG(ERR, APP, \"pfc %u: port %\"PRIu8\" is used already\\n\",\n\t\t\t\tnb_pfc, pconf->tx_port);\n\t\treturn -1;\n\t}\n\tapp_used_tx_port_mask |= mask;\n\tapp_used_port_mask |= mask;\n\n\tmask = 1lu << pconf->rx_core;\n\tapp_used_core_mask |= mask;\n\n\tmask = 1lu << pconf->wt_core;\n\tapp_used_core_mask |= mask;\n\n\tmask = 1lu << pconf->tx_core;\n\tapp_used_core_mask |= mask;\n\n\tnb_pfc++;\n\n\treturn 0;\n}\n\nstatic int\napp_parse_burst_conf(const char *conf_str)\n{\n\tint ret;\n\tuint32_t vals[4];\n\n\tret = app_parse_opt_vals(conf_str, ',', 4, vals);\n\tif (ret != 4)\n\t\treturn ret;\n\n\tburst_conf.rx_burst = (uint16_t)vals[0];\n\tburst_conf.ring_burst = (uint16_t)vals[1];\n\tburst_conf.qos_dequeue = (uint16_t)vals[2];\n\tburst_conf.tx_burst = (uint16_t)vals[3];\n\n\treturn 0;\n}\n\n/*\n * Parses the argument given in the command line of the application,\n * calculates mask for used cores and initializes EAL with calculated core mask\n */\nint\napp_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tint option_index;\n\tconst char *optname;\n\tchar *prgname = argv[0];\n\tuint32_t i, nb_lcores;\n\n\tstatic struct option lgopts[] = {\n\t\t{ \"pfc\", 1, 0, 0 },\n\t\t{ \"mst\", 1, 0, 0 },\n\t\t{ \"rsz\", 1, 0, 0 },\n\t\t{ \"bsz\", 1, 0, 0 },\n\t\t{ \"msz\", 1, 0, 0 },\n\t\t{ \"rth\", 1, 0, 0 },\n\t\t{ \"tth\", 1, 0, 0 },\n\t\t{ \"cfg\", 1, 0, 0 },\n\t\t{ NULL, 0, 0, 0 }\n\t};\n\n\t/* initialize EAL first */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\treturn -1;\n\n\targc -= ret;\n\targv += ret;\n\n\t/* set en_US locale to print big numbers with ',' */\n\tsetlocale(LC_NUMERIC, \"en_US.utf-8\");\n\n\twhile ((opt = getopt_long(argc, argv, \"i\",\n\t\tlgopts, &option_index)) != EOF) {\n\n\t\t\tswitch (opt) {\n\t\t\tcase 'i':\n\t\t\t\tprintf(\"Interactive-mode selected\\n\");\n\t\t\t\tinteractive = 1;\n\t\t\t\tbreak;\n\t\t\t/* long options */\n\t\t\tcase 0:\n\t\t\t\toptname = lgopts[option_index].name;\n\t\t\t\tif (str_is(optname, \"pfc\")) {\n\t\t\t\t\tret = app_parse_flow_conf(optarg);\n\t\t\t\t\tif (ret) {\n\t\t\t\t\t\tRTE_LOG(ERR, APP, \"Invalid pipe configuration %s\\n\", optarg);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (str_is(optname, \"mst\")) {\n\t\t\t\t\tapp_master_core = (uint32_t)atoi(optarg);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (str_is(optname, \"rsz\")) {\n\t\t\t\t\tret = app_parse_ring_conf(optarg);\n\t\t\t\t\tif (ret) {\n\t\t\t\t\t\tRTE_LOG(ERR, APP, \"Invalid ring configuration %s\\n\", optarg);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (str_is(optname, \"bsz\")) {\n\t\t\t\t\tret = app_parse_burst_conf(optarg);\n\t\t\t\t\tif (ret) {\n\t\t\t\t\t\tRTE_LOG(ERR, APP, \"Invalid burst configuration %s\\n\", optarg);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (str_is(optname, \"msz\")) {\n\t\t\t\t\tmp_size = atoi(optarg);\n\t\t\t\t\tif (mp_size <= 0) {\n\t\t\t\t\t\tRTE_LOG(ERR, APP, \"Invalid mempool size %s\\n\", optarg);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (str_is(optname, \"rth\")) {\n\t\t\t\t\tret = app_parse_rth_conf(optarg);\n\t\t\t\t\tif (ret) {\n\t\t\t\t\t\tRTE_LOG(ERR, APP, \"Invalid RX threshold configuration %s\\n\", optarg);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (str_is(optname, \"tth\")) {\n\t\t\t\t\tret = app_parse_tth_conf(optarg);\n\t\t\t\t\tif (ret) {\n\t\t\t\t\t\tRTE_LOG(ERR, APP, \"Invalid TX threshold configuration %s\\n\", optarg);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tif (str_is(optname, \"cfg\")) {\n\t\t\t\t\tcfg_profile = optarg;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\tapp_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t}\n\n\t/* check master core index validity */\n\tfor(i = 0; i <= app_master_core; i++) {\n\t\tif (app_used_core_mask & (1u << app_master_core)) {\n\t\t\tRTE_LOG(ERR, APP, \"Master core index is not configured properly\\n\");\n\t\t\tapp_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\tapp_used_core_mask |= 1u << app_master_core;\n\n\tif ((app_used_core_mask != app_eal_core_mask()) ||\n\t\t\t(app_master_core != rte_get_master_lcore())) {\n\t\tRTE_LOG(ERR, APP, \"EAL core mask not configured properly, must be %\" PRIx64\n\t\t\t\t\" instead of %\" PRIx64 \"\\n\" , app_used_core_mask, app_eal_core_mask());\n\t\treturn -1;\n\t}\n\n\tif (nb_pfc == 0) {\n\t\tRTE_LOG(ERR, APP, \"Packet flow not configured!\\n\");\n\t\tapp_usage(prgname);\n\t\treturn -1;\n\t}\n\n\t/* sanity check for cores assignment */\n\tnb_lcores = app_cpu_core_count();\n\n\tfor(i = 0; i < nb_pfc; i++) {\n\t\tif (qos_conf[i].rx_core >= nb_lcores) {\n\t\t\tRTE_LOG(ERR, APP, \"pfc %u: invalid RX lcore index %u\\n\", i + 1,\n\t\t\t\t\tqos_conf[i].rx_core);\n\t\t\treturn -1;\n\t\t}\n\t\tif (qos_conf[i].wt_core >= nb_lcores) {\n\t\t\tRTE_LOG(ERR, APP, \"pfc %u: invalid WT lcore index %u\\n\", i + 1,\n\t\t\t\t\tqos_conf[i].wt_core);\n\t\t\treturn -1;\n\t\t}\n\t\tuint32_t rx_sock = rte_lcore_to_socket_id(qos_conf[i].rx_core);\n\t\tuint32_t wt_sock = rte_lcore_to_socket_id(qos_conf[i].wt_core);\n\t\tif (rx_sock != wt_sock) {\n\t\t\tRTE_LOG(ERR, APP, \"pfc %u: RX and WT must be on the same socket\\n\", i + 1);\n\t\t\treturn -1;\n\t\t}\n\t\tapp_numa_mask |= 1 << rte_lcore_to_socket_id(qos_conf[i].rx_core);\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/qos_sched/cfg_file.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"cfg_file.h\"\n#include \"main.h\"\n\n\n/** when we resize a file structure, how many extra entries\n * for new sections do we add in */\n#define CFG_ALLOC_SECTION_BATCH 8\n/** when we resize a section structure, how many extra entries\n * for new entries do we add in */\n#define CFG_ALLOC_ENTRY_BATCH 16\n\nstatic unsigned\n_strip(char *str, unsigned len)\n{\n\tint newlen = len;\n\tif (len == 0)\n\t\treturn 0;\n\n\tif (isspace(str[len-1])) {\n\t\t/* strip trailing whitespace */\n\t\twhile (newlen > 0 && isspace(str[newlen - 1]))\n\t\t\tstr[--newlen] = '\\0';\n\t}\n\n\tif (isspace(str[0])) {\n\t\t/* strip leading whitespace */\n\t\tint i,start = 1;\n\t\twhile (isspace(str[start]) && start < newlen)\n\t\t\tstart++\n\t\t\t; /* do nothing */\n\t\tnewlen -= start;\n\t\tfor (i = 0; i < newlen; i++)\n\t\t\tstr[i] = str[i+start];\n\t\tstr[i] = '\\0';\n\t}\n\treturn newlen;\n}\n\nstruct cfg_file *\ncfg_load(const char *filename, int flags)\n{\n\tint allocated_sections = CFG_ALLOC_SECTION_BATCH;\n\tint allocated_entries = 0;\n\tint curr_section = -1;\n\tint curr_entry = -1;\n\tchar buffer[256];\n\tint lineno = 0;\n\tstruct cfg_file *cfg = NULL;\n\n\tFILE *f = fopen(filename, \"r\");\n\tif (f == NULL)\n\t\treturn NULL;\n\n\tcfg = malloc(sizeof(*cfg) +\tsizeof(cfg->sections[0]) * allocated_sections);\n\tif (cfg == NULL)\n\t\tgoto error2;\n\n\tmemset(cfg->sections, 0, sizeof(cfg->sections[0]) * allocated_sections);\n\n\twhile (fgets(buffer, sizeof(buffer), f) != NULL) {\n\t\tchar *pos = NULL;\n\t\tsize_t len = strnlen(buffer, sizeof(buffer));\n\t\tlineno++;\n\t\tif (len >=sizeof(buffer) - 1 && buffer[len-1] != '\\n'){\n\t\t\tprintf(\"Error line %d - no \\\\n found on string. \"\n\t\t\t\t\t\"Check if line too long\\n\", lineno);\n\t\t\tgoto error1;\n\t\t}\n\t\tif ((pos = memchr(buffer, ';', sizeof(buffer))) != NULL) {\n\t\t\t*pos = '\\0';\n\t\t\tlen = pos - buffer;\n\t\t}\n\n\t\tlen = _strip(buffer, len);\n\t\tif (buffer[0] != '[' && memchr(buffer, '=', len) == NULL)\n\t\t\tcontinue;\n\n\t\tif (buffer[0] == '[') {\n\t\t\t/* section heading line */\n\t\t\tchar *end = memchr(buffer, ']', len);\n\t\t\tif (end == NULL) {\n\t\t\t\tprintf(\"Error line %d - no terminating '[' found\\n\", lineno);\n\t\t\t\tgoto error1;\n\t\t\t}\n\t\t\t*end = '\\0';\n\t\t\t_strip(&buffer[1], end - &buffer[1]);\n\n\t\t\t/* close off old section and add start new one */\n\t\t\tif (curr_section >= 0)\n\t\t\t\tcfg->sections[curr_section]->num_entries = curr_entry + 1;\n\t\t\tcurr_section++;\n\n\t\t\t/* resize overall struct if we don't have room for more sections */\n\t\t\tif (curr_section == allocated_sections) {\n\t\t\t\tallocated_sections += CFG_ALLOC_SECTION_BATCH;\n\t\t\t\tstruct cfg_file *n_cfg = realloc(cfg, sizeof(*cfg) +\n\t\t\t\t\t\tsizeof(cfg->sections[0]) * allocated_sections);\n\t\t\t\tif (n_cfg == NULL) {\n\t\t\t\t\tprintf(\"Error - no more memory\\n\");\n\t\t\t\t\tgoto error1;\n\t\t\t\t}\n\t\t\t\tcfg = n_cfg;\n\t\t\t}\n\n\t\t\t/* allocate space for new section */\n\t\t\tallocated_entries = CFG_ALLOC_ENTRY_BATCH;\n\t\t\tcurr_entry = -1;\n\t\t\tcfg->sections[curr_section] = malloc(sizeof(*cfg->sections[0]) +\n\t\t\t\t\tsizeof(cfg->sections[0]->entries[0]) * allocated_entries);\n\t\t\tif (cfg->sections[curr_section] == NULL) {\n\t\t\t\tprintf(\"Error - no more memory\\n\");\n\t\t\t\tgoto error1;\n\t\t\t}\n\n\t\t\tsnprintf(cfg->sections[curr_section]->name,\n\t\t\t\t\tsizeof(cfg->sections[0]->name),\n\t\t\t\t\t\"%s\", &buffer[1]);\n\t\t}\n\t\telse {\n\t\t\t/* value line */\n\t\t\tif (curr_section < 0) {\n\t\t\t\tprintf(\"Error line %d - value outside of section\\n\", lineno);\n\t\t\t\tgoto error1;\n\t\t\t}\n\n\t\t\tstruct cfg_section *sect = cfg->sections[curr_section];\n\t\t\tchar *split[2];\n\t\t\tif (rte_strsplit(buffer, sizeof(buffer), split, 2, '=') != 2) {\n\t\t\t\tprintf(\"Error at line %d - cannot split string\\n\", lineno);\n\t\t\t\tgoto error1;\n\t\t\t}\n\n\t\t\tcurr_entry++;\n\t\t\tif (curr_entry == allocated_entries) {\n\t\t\t\tallocated_entries += CFG_ALLOC_ENTRY_BATCH;\n\t\t\t\tstruct cfg_section *n_sect = realloc(sect, sizeof(*sect) +\n\t\t\t\t\t\tsizeof(sect->entries[0]) * allocated_entries);\n\t\t\t\tif (n_sect == NULL) {\n\t\t\t\t\tprintf(\"Error - no more memory\\n\");\n\t\t\t\t\tgoto error1;\n\t\t\t\t}\n\t\t\t\tsect = cfg->sections[curr_section] = n_sect;\n\t\t\t}\n\n\t\t\tsect->entries[curr_entry] = malloc(sizeof(*sect->entries[0]));\n\t\t\tif (sect->entries[curr_entry] == NULL) {\n\t\t\t\tprintf(\"Error - no more memory\\n\");\n\t\t\t\tgoto error1;\n\t\t\t}\n\n\t\t\tstruct cfg_entry *entry = sect->entries[curr_entry];\n\t\t\tsnprintf(entry->name, sizeof(entry->name), \"%s\", split[0]);\n\t\t\tsnprintf(entry->value, sizeof(entry->value), \"%s\", split[1]);\n\t\t\t_strip(entry->name, strnlen(entry->name, sizeof(entry->name)));\n\t\t\t_strip(entry->value, strnlen(entry->value, sizeof(entry->value)));\n\t\t}\n\t}\n\tfclose(f);\n\tcfg->flags = flags;\n\tcfg->sections[curr_section]->num_entries = curr_entry + 1;\n\tcfg->num_sections = curr_section + 1;\n\treturn cfg;\n\nerror1:\n\tcfg_close(cfg);\nerror2:\n\tfclose(f);\n\treturn NULL;\n}\n\n\nint cfg_close(struct cfg_file *cfg)\n{\n\tint i, j;\n\n\tif (cfg == NULL)\n\t\treturn -1;\n\n\tfor(i = 0; i < cfg->num_sections; i++) {\n\t\tif (cfg->sections[i] != NULL) {\n\t\t\tif (cfg->sections[i]->num_entries) {\n\t\t\t\tfor(j = 0; j < cfg->sections[i]->num_entries; j++) {\n\t\t\t\t\tif (cfg->sections[i]->entries[j] != NULL)\n\t\t\t\t\t\tfree(cfg->sections[i]->entries[j]);\n\t\t\t\t}\n\t\t\t}\n\t\t\tfree(cfg->sections[i]);\n\t\t}\n\t}\n\tfree(cfg);\n\n\treturn 0;\n}\n\nint\ncfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port_params)\n{\n\tconst char *entry;\n\tint j;\n\n\tif (!cfg || !port_params)\n\t\treturn -1;\n\n\tentry = rte_cfgfile_get_entry(cfg, \"port\", \"frame overhead\");\n\tif (entry)\n\t\tport_params->frame_overhead = (uint32_t)atoi(entry);\n\n\tentry = rte_cfgfile_get_entry(cfg, \"port\", \"number of subports per port\");\n\tif (entry)\n\t\tport_params->n_subports_per_port = (uint32_t)atoi(entry);\n\n\tentry = rte_cfgfile_get_entry(cfg, \"port\", \"number of pipes per subport\");\n\tif (entry)\n\t\tport_params->n_pipes_per_subport = (uint32_t)atoi(entry);\n\n\tentry = rte_cfgfile_get_entry(cfg, \"port\", \"queue sizes\");\n\tif (entry) {\n\t\tchar *next;\n\n\t\tfor(j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {\n\t\t\tport_params->qsize[j] = (uint16_t)strtol(entry, &next, 10);\n\t\t\tif (next == NULL)\n\t\t\t\tbreak;\n\t\t\tentry = next;\n\t\t}\n\t}\n\n#ifdef RTE_SCHED_RED\n\tfor (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {\n\t\tchar str[32];\n\n\t\t/* Parse WRED min thresholds */\n\t\tsnprintf(str, sizeof(str), \"tc %d wred min\", j);\n\t\tentry = rte_cfgfile_get_entry(cfg, \"red\", str);\n\t\tif (entry) {\n\t\t\tchar *next;\n\t\t\tint k;\n\t\t\t/* for each packet colour (green, yellow, red) */\n\t\t\tfor (k = 0; k < e_RTE_METER_COLORS; k++) {\n\t\t\t\tport_params->red_params[j][k].min_th\n\t\t\t\t\t= (uint16_t)strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t\t}\n\n\t\t/* Parse WRED max thresholds */\n\t\tsnprintf(str, sizeof(str), \"tc %d wred max\", j);\n\t\tentry = rte_cfgfile_get_entry(cfg, \"red\", str);\n\t\tif (entry) {\n\t\t\tchar *next;\n\t\t\tint k;\n\t\t\t/* for each packet colour (green, yellow, red) */\n\t\t\tfor (k = 0; k < e_RTE_METER_COLORS; k++) {\n\t\t\t\tport_params->red_params[j][k].max_th\n\t\t\t\t\t= (uint16_t)strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t\t}\n\n\t\t/* Parse WRED inverse mark probabilities */\n\t\tsnprintf(str, sizeof(str), \"tc %d wred inv prob\", j);\n\t\tentry = rte_cfgfile_get_entry(cfg, \"red\", str);\n\t\tif (entry) {\n\t\t\tchar *next;\n\t\t\tint k;\n\t\t\t/* for each packet colour (green, yellow, red) */\n\t\t\tfor (k = 0; k < e_RTE_METER_COLORS; k++) {\n\t\t\t\tport_params->red_params[j][k].maxp_inv\n\t\t\t\t\t= (uint8_t)strtol(entry, &next, 10);\n\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t\t}\n\n\t\t/* Parse WRED EWMA filter weights */\n\t\tsnprintf(str, sizeof(str), \"tc %d wred weight\", j);\n\t\tentry = rte_cfgfile_get_entry(cfg, \"red\", str);\n\t\tif (entry) {\n\t\t\tchar *next;\n\t\t\tint k;\n\t\t\t/* for each packet colour (green, yellow, red) */\n\t\t\tfor (k = 0; k < e_RTE_METER_COLORS; k++) {\n\t\t\t\tport_params->red_params[j][k].wq_log2\n\t\t\t\t\t= (uint8_t)strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t\t}\n\t}\n#endif /* RTE_SCHED_RED */\n\n\treturn 0;\n}\n\nint\ncfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe_params)\n{\n\tint i, j;\n\tchar *next;\n\tconst char *entry;\n\tint profiles;\n\n\tif (!cfg || !pipe_params)\n\t\treturn -1;\n\n\tprofiles = rte_cfgfile_num_sections(cfg, \"pipe profile\", sizeof(\"pipe profile\") - 1);\n\tport_params.n_pipe_profiles = profiles;\n\n\tfor (j = 0; j < profiles; j++) {\n\t\tchar pipe_name[32];\n\t\tsnprintf(pipe_name, sizeof(pipe_name), \"pipe profile %d\", j);\n\n\t\tentry = rte_cfgfile_get_entry(cfg, pipe_name, \"tb rate\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tb_rate = (uint32_t)atoi(entry);\n\n\t\tentry = rte_cfgfile_get_entry(cfg, pipe_name, \"tb size\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tb_size = (uint32_t)atoi(entry);\n\n\t\tentry = rte_cfgfile_get_entry(cfg, pipe_name, \"tc period\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tc_period = (uint32_t)atoi(entry);\n\n\t\tentry = rte_cfgfile_get_entry(cfg, pipe_name, \"tc 0 rate\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tc_rate[0] = (uint32_t)atoi(entry);\n\n\t\tentry = rte_cfgfile_get_entry(cfg, pipe_name, \"tc 1 rate\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tc_rate[1] = (uint32_t)atoi(entry);\n\n\t\tentry = rte_cfgfile_get_entry(cfg, pipe_name, \"tc 2 rate\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tc_rate[2] = (uint32_t)atoi(entry);\n\n\t\tentry = rte_cfgfile_get_entry(cfg, pipe_name, \"tc 3 rate\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tc_rate[3] = (uint32_t)atoi(entry);\n\n#ifdef RTE_SCHED_SUBPORT_TC_OV\n\t\tentry = rte_cfgfile_get_entry(cfg, pipe_name, \"tc 3 oversubscription weight\");\n\t\tif (entry)\n\t\t\tpipe_params[j].tc_ov_weight = (uint8_t)atoi(entry);\n#endif\n\n\t\tentry = rte_cfgfile_get_entry(cfg, pipe_name, \"tc 0 wrr weights\");\n\t\tif (entry) {\n\t\t\tfor(i = 0; i < RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; i++) {\n\t\t\t\tpipe_params[j].wrr_weights[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE*0 + i] =\n\t\t\t\t\t(uint8_t)strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t\t}\n\t\tentry = rte_cfgfile_get_entry(cfg, pipe_name, \"tc 1 wrr weights\");\n\t\tif (entry) {\n\t\t\tfor(i = 0; i < RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; i++) {\n\t\t\t\tpipe_params[j].wrr_weights[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE*1 + i] =\n\t\t\t\t\t(uint8_t)strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t\t}\n\t\tentry = rte_cfgfile_get_entry(cfg, pipe_name, \"tc 2 wrr weights\");\n\t\tif (entry) {\n\t\t\tfor(i = 0; i < RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; i++) {\n\t\t\t\tpipe_params[j].wrr_weights[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE*2 + i] =\n\t\t\t\t\t(uint8_t)strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t\t}\n\t\tentry = rte_cfgfile_get_entry(cfg, pipe_name, \"tc 3 wrr weights\");\n\t\tif (entry) {\n\t\t\tfor(i = 0; i < RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; i++) {\n\t\t\t\tpipe_params[j].wrr_weights[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE*3 + i] =\n\t\t\t\t\t(uint8_t)strtol(entry, &next, 10);\n\t\t\t\tif (next == NULL)\n\t\t\t\t\tbreak;\n\t\t\t\tentry = next;\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\nint\ncfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)\n{\n\tconst char *entry;\n\tint i, j, k;\n\n\tif (!cfg || !subport_params)\n\t\treturn -1;\n\n\tmemset(app_pipe_to_profile, -1, sizeof(app_pipe_to_profile));\n\n\tfor (i = 0; i < MAX_SCHED_SUBPORTS; i++) {\n\t\tchar sec_name[CFG_NAME_LEN];\n\t\tsnprintf(sec_name, sizeof(sec_name), \"subport %d\", i);\n\n\t\tif (rte_cfgfile_has_section(cfg, sec_name)) {\n\t\t\tentry = rte_cfgfile_get_entry(cfg, sec_name, \"tb rate\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tb_rate = (uint32_t)atoi(entry);\n\n\t\t\tentry = rte_cfgfile_get_entry(cfg, sec_name, \"tb size\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tb_size = (uint32_t)atoi(entry);\n\n\t\t\tentry = rte_cfgfile_get_entry(cfg, sec_name, \"tc period\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tc_period = (uint32_t)atoi(entry);\n\n\t\t\tentry = rte_cfgfile_get_entry(cfg, sec_name, \"tc 0 rate\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tc_rate[0] = (uint32_t)atoi(entry);\n\n\t\t\tentry = rte_cfgfile_get_entry(cfg, sec_name, \"tc 1 rate\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tc_rate[1] = (uint32_t)atoi(entry);\n\n\t\t\tentry = rte_cfgfile_get_entry(cfg, sec_name, \"tc 2 rate\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tc_rate[2] = (uint32_t)atoi(entry);\n\n\t\t\tentry = rte_cfgfile_get_entry(cfg, sec_name, \"tc 3 rate\");\n\t\t\tif (entry)\n\t\t\t\tsubport_params[i].tc_rate[3] = (uint32_t)atoi(entry);\n\n\t\t\tint n_entries = rte_cfgfile_section_num_entries(cfg, sec_name);\n\t\t\tstruct rte_cfgfile_entry entries[n_entries];\n\n\t\t\trte_cfgfile_section_entries(cfg, sec_name, entries, n_entries);\n\n\t\t\tfor (j = 0; j < n_entries; j++) {\n\t\t\t\tif (strncmp(\"pipe\", entries[j].name, sizeof(\"pipe\") - 1) == 0) {\n\t\t\t\t\tint profile;\n\t\t\t\t\tchar *tokens[2] = {NULL, NULL};\n\t\t\t\t\tint n_tokens;\n\t\t\t\t\tint begin, end;\n\n\t\t\t\t\tprofile = atoi(entries[j].value);\n\t\t\t\t\tn_tokens = rte_strsplit(&entries[j].name[sizeof(\"pipe\")],\n\t\t\t\t\t\t\tstrnlen(entries[j].name, CFG_NAME_LEN), tokens, 2, '-');\n\n\t\t\t\t\tbegin = atoi(tokens[0]);\n\t\t\t\t\tif (n_tokens == 2)\n\t\t\t\t\t\tend = atoi(tokens[1]);\n\t\t\t\t\telse\n\t\t\t\t\t\tend = begin;\n\n\t\t\t\t\tif (end >= MAX_SCHED_PIPES || begin > end)\n\t\t\t\t\t\treturn -1;\n\n\t\t\t\t\tfor (k = begin; k <= end; k++) {\n\t\t\t\t\t\tchar profile_name[CFG_NAME_LEN];\n\n\t\t\t\t\t\tsnprintf(profile_name, sizeof(profile_name),\n\t\t\t\t\t\t\t\t\"pipe profile %d\", profile);\n\t\t\t\t\t\tif (rte_cfgfile_has_section(cfg, profile_name))\n\t\t\t\t\t\t\tapp_pipe_to_profile[i][k] = profile;\n\t\t\t\t\t\telse\n\t\t\t\t\t\t\trte_exit(EXIT_FAILURE, \"Wrong pipe profile %s\\n\",\n\t\t\t\t\t\t\t\t\tentries[j].value);\n\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/qos_sched/cfg_file.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __CFG_FILE_H__\n#define __CFG_FILE_H__\n\n#include \n#include \n\n#define CFG_NAME_LEN 32\n#define CFG_VALUE_LEN 64\n\nstruct cfg_entry {\n\tchar name[CFG_NAME_LEN];\n\tchar value[CFG_VALUE_LEN];\n};\n\nstruct cfg_section {\n\tchar name[CFG_NAME_LEN];\n\tint num_entries;\n\tstruct cfg_entry *entries[0];\n};\n\nstruct cfg_file {\n\tint flags;\n\tint num_sections;\n\tstruct cfg_section *sections[0];\n};\n\n\nint cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);\n\nint cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);\n\nint cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);\n\n/* reads a config file from disk and returns a handle to the config\n * 'flags' is reserved for future use and must be 0\n */\nstruct cfg_file *cfg_load(const char *filename, int flags);\n\n/* cleans up memory allocated by cfg_load() */\nint cfg_close(struct cfg_file *cfg);\n\n#endif\n" }, { "path": "examples/qos_sched/cmdline.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\n/* *** Help command with introduction. *** */\nstruct cmd_help_result {\n\tcmdline_fixed_string_t help;\n};\n\nstatic void cmd_help_parsed(__attribute__((unused)) void *parsed_result,\n struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n\tcmdline_printf(\n\t\tcl,\n\t\t\"\\n\"\n\t\t\"The following commands are currently available:\\n\\n\"\n\t\t\"Control:\\n\"\n\t\t\" quit : Quit the application.\\n\"\n\t\t\"\\nStatistics:\\n\"\n\t\t\" stats app : Show app statistics.\\n\"\n\t\t\" stats port X subport Y : Show stats of a specific subport.\\n\"\n\t\t\" stats port X subport Y pipe Z : Show stats of a specific pipe.\\n\"\n\t\t\"\\nAverage queue size:\\n\"\n\t\t\" qavg port X subport Y : Show average queue size per subport.\\n\"\n\t\t\" qavg port X subport Y tc Z : Show average queue size per subport and TC.\\n\"\n\t\t\" qavg port X subport Y pipe Z : Show average queue size per pipe.\\n\"\n\t\t\" qavg port X subport Y pipe Z tc A : Show average queue size per pipe and TC.\\n\"\n\t\t\" qavg port X subport Y pipe Z tc A q B : Show average queue size of a specific queue.\\n\"\n\t\t\" qavg [n|period] X : Set number of times and peiod (us).\\n\\n\"\n\t);\n\n}\n\ncmdline_parse_token_string_t cmd_help_help =\n\tTOKEN_STRING_INITIALIZER(struct cmd_help_result, help, \"help\");\n\ncmdline_parse_inst_t cmd_help = {\n\t.f = cmd_help_parsed,\n\t.data = NULL,\n\t.help_str = \"show help\",\n\t.tokens = {\n\t\t(void *)&cmd_help_help,\n\t\tNULL,\n\t},\n};\n\n/* *** QUIT *** */\nstruct cmd_quit_result {\n\tcmdline_fixed_string_t quit;\n};\n\nstatic void cmd_quit_parsed(__attribute__((unused)) void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tcmdline_quit(cl);\n}\n\ncmdline_parse_token_string_t cmd_quit_quit =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_quit_result, quit, \"quit\");\n\ncmdline_parse_inst_t cmd_quit = {\n\t.f = cmd_quit_parsed,\n\t.data = NULL,\n\t.help_str = \"exit application\",\n\t.tokens = {\n\t\t(void *)&cmd_quit_quit,\n\t\tNULL,\n\t\t},\n};\n\n/* *** SET QAVG PARAMETERS *** */\nstruct cmd_setqavg_result {\n cmdline_fixed_string_t qavg_string;\n cmdline_fixed_string_t param_string;\n uint32_t number;\n};\n\nstatic void cmd_setqavg_parsed(void *parsed_result,\n __attribute__((unused)) struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n struct cmd_setqavg_result *res = parsed_result;\n\n\tif (!strcmp(res->param_string, \"period\"))\n\t\tqavg_period = res->number;\n\telse if (!strcmp(res->param_string, \"n\"))\n\t\tqavg_ntimes = res->number;\n\telse\n\t\tprintf(\"\\nUnknown parameter.\\n\\n\");\n}\n\ncmdline_parse_token_string_t cmd_setqavg_qavg_string =\n TOKEN_STRING_INITIALIZER(struct cmd_setqavg_result, qavg_string,\n \"qavg\");\ncmdline_parse_token_string_t cmd_setqavg_param_string =\n TOKEN_STRING_INITIALIZER(struct cmd_setqavg_result, param_string,\n \"period#n\");\ncmdline_parse_token_num_t cmd_setqavg_number =\n TOKEN_NUM_INITIALIZER(struct cmd_setqavg_result, number,\n UINT32);\n\ncmdline_parse_inst_t cmd_setqavg = {\n .f = cmd_setqavg_parsed,\n .data = NULL,\n .help_str = \"Show subport stats.\",\n .tokens = {\n (void *)&cmd_setqavg_qavg_string,\n (void *)&cmd_setqavg_param_string,\n (void *)&cmd_setqavg_number,\n NULL,\n },\n};\n\n/* *** SHOW APP STATS *** */\nstruct cmd_appstats_result {\n\tcmdline_fixed_string_t stats_string;\n\tcmdline_fixed_string_t app_string;\n};\n\nstatic void cmd_appstats_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t\t__attribute__((unused)) void *data)\n{\n\tapp_stat();\n}\n\ncmdline_parse_token_string_t cmd_appstats_stats_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_appstats_result, stats_string,\n\t\t\t\t\"stats\");\ncmdline_parse_token_string_t cmd_appstats_app_string =\n\tTOKEN_STRING_INITIALIZER(struct cmd_appstats_result, app_string,\n\t\t\t\t\"app\");\n\ncmdline_parse_inst_t cmd_appstats = {\n\t.f = cmd_appstats_parsed,\n\t.data = NULL,\n\t.help_str = \"Show app stats.\",\n\t.tokens = {\n\t\t(void *)&cmd_appstats_stats_string,\n\t\t(void *)&cmd_appstats_app_string,\n\t\tNULL,\n\t},\n};\n\n/* *** SHOW SUBPORT STATS *** */\nstruct cmd_subportstats_result {\n cmdline_fixed_string_t stats_string;\n cmdline_fixed_string_t port_string;\n\tuint8_t port_number;\n cmdline_fixed_string_t subport_string;\n uint32_t subport_number;\n};\n\nstatic void cmd_subportstats_parsed(void *parsed_result,\n __attribute__((unused)) struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n\tstruct cmd_subportstats_result *res = parsed_result;\n\n\tif (subport_stat(res->port_number, res->subport_number) < 0)\n\t\tprintf (\"\\nStats not available for these parameters. Check that both the port and subport are correct.\\n\\n\");\n}\n\ncmdline_parse_token_string_t cmd_subportstats_stats_string =\n TOKEN_STRING_INITIALIZER(struct cmd_subportstats_result, stats_string,\n \"stats\");\ncmdline_parse_token_string_t cmd_subportstats_port_string =\n TOKEN_STRING_INITIALIZER(struct cmd_subportstats_result, port_string,\n \"port\");\ncmdline_parse_token_string_t cmd_subportstats_subport_string =\n TOKEN_STRING_INITIALIZER(struct cmd_subportstats_result, subport_string,\n \"subport\");\ncmdline_parse_token_num_t cmd_subportstats_subport_number =\n TOKEN_NUM_INITIALIZER(struct cmd_subportstats_result, subport_number,\n UINT32);\ncmdline_parse_token_num_t cmd_subportstats_port_number =\n TOKEN_NUM_INITIALIZER(struct cmd_subportstats_result, port_number,\n UINT8);\n\ncmdline_parse_inst_t cmd_subportstats = {\n .f = cmd_subportstats_parsed,\n .data = NULL,\n .help_str = \"Show subport stats.\",\n .tokens = {\n (void *)&cmd_subportstats_stats_string,\n (void *)&cmd_subportstats_port_string,\n (void *)&cmd_subportstats_port_number,\n (void *)&cmd_subportstats_subport_string,\n (void *)&cmd_subportstats_subport_number,\n NULL,\n },\n};\n\n/* *** SHOW PIPE STATS *** */\nstruct cmd_pipestats_result {\n cmdline_fixed_string_t stats_string;\n cmdline_fixed_string_t port_string;\n uint8_t port_number;\n cmdline_fixed_string_t subport_string;\n uint32_t subport_number;\n cmdline_fixed_string_t pipe_string;\n uint32_t pipe_number;\n};\n\nstatic void cmd_pipestats_parsed(void *parsed_result,\n __attribute__((unused)) struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n struct cmd_pipestats_result *res = parsed_result;\n\n if (pipe_stat(res->port_number, res->subport_number, res->pipe_number) < 0)\n printf (\"\\nStats not available for these parameters. Check that both the port and subport are correct.\\n\\n\");\n}\n\ncmdline_parse_token_string_t cmd_pipestats_stats_string =\n TOKEN_STRING_INITIALIZER(struct cmd_pipestats_result, stats_string,\n \"stats\");\ncmdline_parse_token_string_t cmd_pipestats_port_string =\n TOKEN_STRING_INITIALIZER(struct cmd_pipestats_result, port_string,\n \"port\");\ncmdline_parse_token_num_t cmd_pipestats_port_number =\n TOKEN_NUM_INITIALIZER(struct cmd_pipestats_result, port_number,\n UINT8);\ncmdline_parse_token_string_t cmd_pipestats_subport_string =\n TOKEN_STRING_INITIALIZER(struct cmd_pipestats_result, subport_string,\n \"subport\");\ncmdline_parse_token_num_t cmd_pipestats_subport_number =\n TOKEN_NUM_INITIALIZER(struct cmd_pipestats_result, subport_number,\n UINT32);\ncmdline_parse_token_string_t cmd_pipestats_pipe_string =\n TOKEN_STRING_INITIALIZER(struct cmd_pipestats_result, pipe_string,\n \"pipe\");\ncmdline_parse_token_num_t cmd_pipestats_pipe_number =\n TOKEN_NUM_INITIALIZER(struct cmd_pipestats_result, pipe_number,\n UINT32);\n\ncmdline_parse_inst_t cmd_pipestats = {\n .f = cmd_pipestats_parsed,\n .data = NULL,\n .help_str = \"Show pipe stats.\",\n .tokens = {\n (void *)&cmd_pipestats_stats_string,\n (void *)&cmd_pipestats_port_string,\n (void *)&cmd_pipestats_port_number,\n (void *)&cmd_pipestats_subport_string,\n (void *)&cmd_pipestats_subport_number,\n (void *)&cmd_pipestats_pipe_string,\n (void *)&cmd_pipestats_pipe_number,\n NULL,\n },\n};\n\n/* *** SHOW AVERAGE QUEUE SIZE (QUEUE) *** */\nstruct cmd_avg_q_result {\n cmdline_fixed_string_t qavg_string;\n cmdline_fixed_string_t port_string;\n uint8_t port_number;\n cmdline_fixed_string_t subport_string;\n uint32_t subport_number;\n cmdline_fixed_string_t pipe_string;\n uint32_t pipe_number;\n cmdline_fixed_string_t tc_string;\n uint8_t tc_number;\n cmdline_fixed_string_t q_string;\n uint8_t q_number;\n};\n\nstatic void cmd_avg_q_parsed(void *parsed_result,\n __attribute__((unused)) struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n struct cmd_avg_q_result *res = parsed_result;\n\n if (qavg_q(res->port_number, res->subport_number, res->pipe_number, res->tc_number, res->q_number) < 0)\n printf (\"\\nStats not available for these parameters. Check that both the port and subport are correct.\\n\\n\");\n}\n\ncmdline_parse_token_string_t cmd_avg_q_qavg_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_q_result, qavg_string,\n \"qavg\");\ncmdline_parse_token_string_t cmd_avg_q_port_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_q_result, port_string,\n \"port\");\ncmdline_parse_token_num_t cmd_avg_q_port_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_q_result, port_number,\n UINT8);\ncmdline_parse_token_string_t cmd_avg_q_subport_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_q_result, subport_string,\n \"subport\");\ncmdline_parse_token_num_t cmd_avg_q_subport_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_q_result, subport_number,\n UINT32);\ncmdline_parse_token_string_t cmd_avg_q_pipe_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_q_result, pipe_string,\n \"pipe\");\ncmdline_parse_token_num_t cmd_avg_q_pipe_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_q_result, pipe_number,\n UINT32);\ncmdline_parse_token_string_t cmd_avg_q_tc_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_q_result, tc_string,\n \"tc\");\ncmdline_parse_token_num_t cmd_avg_q_tc_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_q_result, tc_number,\n UINT8);\ncmdline_parse_token_string_t cmd_avg_q_q_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_q_result, q_string,\n \"q\");\ncmdline_parse_token_num_t cmd_avg_q_q_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_q_result, q_number,\n UINT8);\n\ncmdline_parse_inst_t cmd_avg_q = {\n .f = cmd_avg_q_parsed,\n .data = NULL,\n .help_str = \"Show pipe stats.\",\n .tokens = {\n (void *)&cmd_avg_q_qavg_string,\n (void *)&cmd_avg_q_port_string,\n (void *)&cmd_avg_q_port_number,\n (void *)&cmd_avg_q_subport_string,\n (void *)&cmd_avg_q_subport_number,\n (void *)&cmd_avg_q_pipe_string,\n (void *)&cmd_avg_q_pipe_number,\n (void *)&cmd_avg_q_tc_string,\n (void *)&cmd_avg_q_tc_number,\n (void *)&cmd_avg_q_q_string,\n (void *)&cmd_avg_q_q_number,\n NULL,\n },\n};\n\n/* *** SHOW AVERAGE QUEUE SIZE (tc/pipe) *** */\nstruct cmd_avg_tcpipe_result {\n cmdline_fixed_string_t qavg_string;\n cmdline_fixed_string_t port_string;\n uint8_t port_number;\n cmdline_fixed_string_t subport_string;\n uint32_t subport_number;\n cmdline_fixed_string_t pipe_string;\n uint32_t pipe_number;\n cmdline_fixed_string_t tc_string;\n uint8_t tc_number;\n};\n\nstatic void cmd_avg_tcpipe_parsed(void *parsed_result,\n __attribute__((unused)) struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n struct cmd_avg_tcpipe_result *res = parsed_result;\n\n if (qavg_tcpipe(res->port_number, res->subport_number, res->pipe_number, res->tc_number) < 0)\n printf (\"\\nStats not available for these parameters. Check that both the port and subport are correct.\\n\\n\");\n}\n\ncmdline_parse_token_string_t cmd_avg_tcpipe_qavg_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_tcpipe_result, qavg_string,\n \"qavg\");\ncmdline_parse_token_string_t cmd_avg_tcpipe_port_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_tcpipe_result, port_string,\n \"port\");\ncmdline_parse_token_num_t cmd_avg_tcpipe_port_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_tcpipe_result, port_number,\n UINT8);\ncmdline_parse_token_string_t cmd_avg_tcpipe_subport_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_tcpipe_result, subport_string,\n \"subport\");\ncmdline_parse_token_num_t cmd_avg_tcpipe_subport_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_tcpipe_result, subport_number,\n UINT32);\ncmdline_parse_token_string_t cmd_avg_tcpipe_pipe_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_tcpipe_result, pipe_string,\n \"pipe\");\ncmdline_parse_token_num_t cmd_avg_tcpipe_pipe_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_tcpipe_result, pipe_number,\n UINT32);\ncmdline_parse_token_string_t cmd_avg_tcpipe_tc_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_tcpipe_result, tc_string,\n \"tc\");\ncmdline_parse_token_num_t cmd_avg_tcpipe_tc_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_tcpipe_result, tc_number,\n UINT8);\n\ncmdline_parse_inst_t cmd_avg_tcpipe = {\n .f = cmd_avg_tcpipe_parsed,\n .data = NULL,\n .help_str = \"Show pipe stats.\",\n .tokens = {\n (void *)&cmd_avg_tcpipe_qavg_string,\n (void *)&cmd_avg_tcpipe_port_string,\n (void *)&cmd_avg_tcpipe_port_number,\n (void *)&cmd_avg_tcpipe_subport_string,\n (void *)&cmd_avg_tcpipe_subport_number,\n (void *)&cmd_avg_tcpipe_pipe_string,\n (void *)&cmd_avg_tcpipe_pipe_number,\n (void *)&cmd_avg_tcpipe_tc_string,\n (void *)&cmd_avg_tcpipe_tc_number,\n NULL,\n },\n};\n\n/* *** SHOW AVERAGE QUEUE SIZE (pipe) *** */\nstruct cmd_avg_pipe_result {\n cmdline_fixed_string_t qavg_string;\n cmdline_fixed_string_t port_string;\n uint8_t port_number;\n cmdline_fixed_string_t subport_string;\n uint32_t subport_number;\n cmdline_fixed_string_t pipe_string;\n uint32_t pipe_number;\n};\n\nstatic void cmd_avg_pipe_parsed(void *parsed_result,\n __attribute__((unused)) struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n struct cmd_avg_pipe_result *res = parsed_result;\n\n if (qavg_pipe(res->port_number, res->subport_number, res->pipe_number) < 0)\n printf (\"\\nStats not available for these parameters. Check that both the port and subport are correct.\\n\\n\");\n}\n\ncmdline_parse_token_string_t cmd_avg_pipe_qavg_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_pipe_result, qavg_string,\n \"qavg\");\ncmdline_parse_token_string_t cmd_avg_pipe_port_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_pipe_result, port_string,\n \"port\");\ncmdline_parse_token_num_t cmd_avg_pipe_port_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_pipe_result, port_number,\n UINT8);\ncmdline_parse_token_string_t cmd_avg_pipe_subport_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_pipe_result, subport_string,\n \"subport\");\ncmdline_parse_token_num_t cmd_avg_pipe_subport_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_pipe_result, subport_number,\n UINT32);\ncmdline_parse_token_string_t cmd_avg_pipe_pipe_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_pipe_result, pipe_string,\n \"pipe\");\ncmdline_parse_token_num_t cmd_avg_pipe_pipe_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_pipe_result, pipe_number,\n UINT32);\n\ncmdline_parse_inst_t cmd_avg_pipe = {\n .f = cmd_avg_pipe_parsed,\n .data = NULL,\n .help_str = \"Show pipe stats.\",\n .tokens = {\n (void *)&cmd_avg_pipe_qavg_string,\n (void *)&cmd_avg_pipe_port_string,\n (void *)&cmd_avg_pipe_port_number,\n (void *)&cmd_avg_pipe_subport_string,\n (void *)&cmd_avg_pipe_subport_number,\n (void *)&cmd_avg_pipe_pipe_string,\n (void *)&cmd_avg_pipe_pipe_number,\n NULL,\n },\n};\n\n/* *** SHOW AVERAGE QUEUE SIZE (tc/subport) *** */\nstruct cmd_avg_tcsubport_result {\n cmdline_fixed_string_t qavg_string;\n cmdline_fixed_string_t port_string;\n uint8_t port_number;\n cmdline_fixed_string_t subport_string;\n uint32_t subport_number;\n cmdline_fixed_string_t tc_string;\n uint8_t tc_number;\n};\n\nstatic void cmd_avg_tcsubport_parsed(void *parsed_result,\n __attribute__((unused)) struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n struct cmd_avg_tcsubport_result *res = parsed_result;\n\n if (qavg_tcsubport(res->port_number, res->subport_number, res->tc_number) < 0)\n printf (\"\\nStats not available for these parameters. Check that both the port and subport are correct.\\n\\n\");\n}\n\ncmdline_parse_token_string_t cmd_avg_tcsubport_qavg_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_tcsubport_result, qavg_string,\n \"qavg\");\ncmdline_parse_token_string_t cmd_avg_tcsubport_port_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_tcsubport_result, port_string,\n \"port\");\ncmdline_parse_token_num_t cmd_avg_tcsubport_port_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_tcsubport_result, port_number,\n UINT8);\ncmdline_parse_token_string_t cmd_avg_tcsubport_subport_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_tcsubport_result, subport_string,\n \"subport\");\ncmdline_parse_token_num_t cmd_avg_tcsubport_subport_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_tcsubport_result, subport_number,\n UINT32);\ncmdline_parse_token_string_t cmd_avg_tcsubport_tc_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_tcsubport_result, tc_string,\n \"tc\");\ncmdline_parse_token_num_t cmd_avg_tcsubport_tc_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_tcsubport_result, tc_number,\n UINT8);\n\ncmdline_parse_inst_t cmd_avg_tcsubport = {\n .f = cmd_avg_tcsubport_parsed,\n .data = NULL,\n .help_str = \"Show pipe stats.\",\n .tokens = {\n (void *)&cmd_avg_tcsubport_qavg_string,\n (void *)&cmd_avg_tcsubport_port_string,\n (void *)&cmd_avg_tcsubport_port_number,\n (void *)&cmd_avg_tcsubport_subport_string,\n (void *)&cmd_avg_tcsubport_subport_number,\n (void *)&cmd_avg_tcsubport_tc_string,\n (void *)&cmd_avg_tcsubport_tc_number,\n NULL,\n },\n};\n\n/* *** SHOW AVERAGE QUEUE SIZE (subport) *** */\nstruct cmd_avg_subport_result {\n cmdline_fixed_string_t qavg_string;\n cmdline_fixed_string_t port_string;\n uint8_t port_number;\n cmdline_fixed_string_t subport_string;\n uint32_t subport_number;\n};\n\nstatic void cmd_avg_subport_parsed(void *parsed_result,\n __attribute__((unused)) struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n struct cmd_avg_subport_result *res = parsed_result;\n\n if (qavg_subport(res->port_number, res->subport_number) < 0)\n printf (\"\\nStats not available for these parameters. Check that both the port and subport are correct.\\n\\n\");\n}\n\ncmdline_parse_token_string_t cmd_avg_subport_qavg_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_subport_result, qavg_string,\n \"qavg\");\ncmdline_parse_token_string_t cmd_avg_subport_port_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_subport_result, port_string,\n \"port\");\ncmdline_parse_token_num_t cmd_avg_subport_port_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_subport_result, port_number,\n UINT8);\ncmdline_parse_token_string_t cmd_avg_subport_subport_string =\n TOKEN_STRING_INITIALIZER(struct cmd_avg_subport_result, subport_string,\n \"subport\");\ncmdline_parse_token_num_t cmd_avg_subport_subport_number =\n TOKEN_NUM_INITIALIZER(struct cmd_avg_subport_result, subport_number,\n UINT32);\n\ncmdline_parse_inst_t cmd_avg_subport = {\n .f = cmd_avg_subport_parsed,\n .data = NULL,\n .help_str = \"Show pipe stats.\",\n .tokens = {\n (void *)&cmd_avg_subport_qavg_string,\n (void *)&cmd_avg_subport_port_string,\n (void *)&cmd_avg_subport_port_number,\n (void *)&cmd_avg_subport_subport_string,\n (void *)&cmd_avg_subport_subport_number,\n NULL,\n },\n};\n\n/* ******************************************************************************** */\n\n/* list of instructions */\ncmdline_parse_ctx_t main_ctx[] = {\n\t(cmdline_parse_inst_t *)&cmd_help,\n\t(cmdline_parse_inst_t *)&cmd_setqavg,\n\t(cmdline_parse_inst_t *)&cmd_appstats,\n\t(cmdline_parse_inst_t *)&cmd_subportstats,\n (cmdline_parse_inst_t *)&cmd_pipestats,\n\t(cmdline_parse_inst_t *)&cmd_avg_q,\n\t(cmdline_parse_inst_t *)&cmd_avg_tcpipe,\n\t(cmdline_parse_inst_t *)&cmd_avg_pipe,\n\t(cmdline_parse_inst_t *)&cmd_avg_tcsubport,\n\t(cmdline_parse_inst_t *)&cmd_avg_subport,\n\t(cmdline_parse_inst_t *)&cmd_quit,\n\tNULL,\n};\n\n/* prompt function, called from main on MASTER lcore */\nvoid\nprompt(void)\n{\n\tstruct cmdline *cl;\n\n\tcl = cmdline_stdin_new(main_ctx, \"qos_sched> \");\n\tif (cl == NULL) {\n\t\treturn;\n\t}\n\tcmdline_interact(cl);\n\tcmdline_stdin_exit(cl);\n}\n" }, { "path": "examples/qos_sched/init.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n#include \"cfg_file.h\"\n\nuint32_t app_numa_mask = 0;\nstatic uint32_t app_inited_port_mask = 0;\n\nint app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES];\n\n#define MAX_NAME_LEN 32\n\nstruct ring_conf ring_conf = {\n\t.rx_size = APP_RX_DESC_DEFAULT,\n\t.ring_size = APP_RING_SIZE,\n\t.tx_size = APP_TX_DESC_DEFAULT,\n};\n\nstruct burst_conf burst_conf = {\n\t.rx_burst = MAX_PKT_RX_BURST,\n\t.ring_burst = PKT_ENQUEUE,\n\t.qos_dequeue = PKT_DEQUEUE,\n\t.tx_burst = MAX_PKT_TX_BURST,\n};\n\nstruct ring_thresh rx_thresh = {\n\t.pthresh = RX_PTHRESH,\n\t.hthresh = RX_HTHRESH,\n\t.wthresh = RX_WTHRESH,\n};\n\nstruct ring_thresh tx_thresh = {\n\t.pthresh = TX_PTHRESH,\n\t.hthresh = TX_HTHRESH,\n\t.wthresh = TX_WTHRESH,\n};\n\nuint32_t nb_pfc;\nconst char *cfg_profile = NULL;\nint mp_size = NB_MBUF;\nstruct flow_conf qos_conf[MAX_DATA_STREAMS];\n\nstatic const struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.max_rx_pkt_len = ETHER_MAX_LEN,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_DCB_NONE,\n\t},\n};\n\nstatic int\napp_init_port(uint8_t portid, struct rte_mempool *mp)\n{\n\tint ret;\n\tstruct rte_eth_link link;\n\tstruct rte_eth_rxconf rx_conf;\n\tstruct rte_eth_txconf tx_conf;\n\n\t/* check if port already initialized (multistream configuration) */\n\tif (app_inited_port_mask & (1u << portid))\n\t\treturn 0;\n\n\trx_conf.rx_thresh.pthresh = rx_thresh.pthresh;\n\trx_conf.rx_thresh.hthresh = rx_thresh.hthresh;\n\trx_conf.rx_thresh.wthresh = rx_thresh.wthresh;\n\trx_conf.rx_free_thresh = 32;\n\trx_conf.rx_drop_en = 0;\n\n\ttx_conf.tx_thresh.pthresh = tx_thresh.pthresh;\n\ttx_conf.tx_thresh.hthresh = tx_thresh.hthresh;\n\ttx_conf.tx_thresh.wthresh = tx_thresh.wthresh;\n\ttx_conf.tx_free_thresh = 0;\n\ttx_conf.tx_rs_thresh = 0;\n\ttx_conf.txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | ETH_TXQ_FLAGS_NOOFFLOADS;\n\n\t/* init port */\n\tRTE_LOG(INFO, APP, \"Initializing port %\"PRIu8\"... \", portid);\n\tfflush(stdout);\n\tret = rte_eth_dev_configure(portid, 1, 1, &port_conf);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Cannot configure device: \"\n\t\t\t\t\"err=%d, port=%\"PRIu8\"\\n\", ret, portid);\n\n\t/* init one RX queue */\n\tfflush(stdout);\n\tret = rte_eth_rx_queue_setup(portid, 0, (uint16_t)ring_conf.rx_size,\n\t\trte_eth_dev_socket_id(portid), &rx_conf, mp);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup: \"\n\t\t\t\t\"err=%d, port=%\"PRIu8\"\\n\", ret, portid);\n\n\t/* init one TX queue */\n\tfflush(stdout);\n\tret = rte_eth_tx_queue_setup(portid, 0,\n\t\t(uint16_t)ring_conf.tx_size, rte_eth_dev_socket_id(portid), &tx_conf);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"rte_eth_tx_queue_setup: err=%d, \"\n\t\t\t\t\"port=%\"PRIu8\" queue=%d\\n\", ret, portid, 0);\n\n\t/* Start device */\n\tret = rte_eth_dev_start(portid);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"rte_pmd_port_start: \"\n\t\t\t\t\"err=%d, port=%\"PRIu8\"\\n\", ret, portid);\n\n\tprintf(\"done: \");\n\n\t/* get link status */\n\trte_eth_link_get(portid, &link);\n\tif (link.link_status) {\n\t\tprintf(\" Link Up - speed %u Mbps - %s\\n\",\n\t\t\t(uint32_t) link.link_speed,\n\t\t\t(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?\n\t\t\t(\"full-duplex\") : (\"half-duplex\\n\"));\n\t} else {\n\t\tprintf(\" Link Down\\n\");\n\t}\n\trte_eth_promiscuous_enable(portid);\n\n\t/* mark port as initialized */\n\tapp_inited_port_mask |= 1u << portid;\n\n\treturn 0;\n}\n\nstatic struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {\n\t{\n\t\t.tb_rate = 1250000000,\n\t\t.tb_size = 1000000,\n\n\t\t.tc_rate = {1250000000, 1250000000, 1250000000, 1250000000},\n\t\t.tc_period = 10,\n\t},\n};\n\nstatic struct rte_sched_pipe_params pipe_profiles[RTE_SCHED_PIPE_PROFILES_PER_PORT] = {\n\t{ /* Profile #0 */\n\t\t.tb_rate = 305175,\n\t\t.tb_size = 1000000,\n\n\t\t.tc_rate = {305175, 305175, 305175, 305175},\n\t\t.tc_period = 40,\n#ifdef RTE_SCHED_SUBPORT_TC_OV\n\t\t.tc_ov_weight = 1,\n#endif\n\n\t\t.wrr_weights = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},\n\t},\n};\n\nstruct rte_sched_port_params port_params = {\n\t.name = \"port_scheduler_0\",\n\t.socket = 0, /* computed */\n\t.rate = 0, /* computed */\n\t.mtu = 6 + 6 + 4 + 4 + 2 + 1500,\n\t.frame_overhead = RTE_SCHED_FRAME_OVERHEAD_DEFAULT,\n\t.n_subports_per_port = 1,\n\t.n_pipes_per_subport = 4096,\n\t.qsize = {64, 64, 64, 64},\n\t.pipe_profiles = pipe_profiles,\n\t.n_pipe_profiles = sizeof(pipe_profiles) / sizeof(struct rte_sched_pipe_params),\n\n#ifdef RTE_SCHED_RED\n\t.red_params = {\n\t\t/* Traffic Class 0 Colors Green / Yellow / Red */\n\t\t[0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n\t\t[0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n\t\t[0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n\n\t\t/* Traffic Class 1 - Colors Green / Yellow / Red */\n\t\t[1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n\t\t[1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n\t\t[1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n\n\t\t/* Traffic Class 2 - Colors Green / Yellow / Red */\n\t\t[2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n\t\t[2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n\t\t[2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n\n\t\t/* Traffic Class 3 - Colors Green / Yellow / Red */\n\t\t[3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n\t\t[3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},\n\t\t[3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}\n\t}\n#endif /* RTE_SCHED_RED */\n};\n\nstatic struct rte_sched_port *\napp_init_sched_port(uint32_t portid, uint32_t socketid)\n{\n\tstatic char port_name[32]; /* static as referenced from global port_params*/\n\tstruct rte_eth_link link;\n\tstruct rte_sched_port *port = NULL;\n\tuint32_t pipe, subport;\n\tint err;\n\n\trte_eth_link_get((uint8_t)portid, &link);\n\n\tport_params.socket = socketid;\n\tport_params.rate = (uint64_t) link.link_speed * 1000 * 1000 / 8;\n\tsnprintf(port_name, sizeof(port_name), \"port_%d\", portid);\n\tport_params.name = port_name;\n\n\tport = rte_sched_port_config(&port_params);\n\tif (port == NULL){\n\t\trte_exit(EXIT_FAILURE, \"Unable to config sched port\\n\");\n\t}\n\n\tfor (subport = 0; subport < port_params.n_subports_per_port; subport ++) {\n\t\terr = rte_sched_subport_config(port, subport, &subport_params[subport]);\n\t\tif (err) {\n\t\t\trte_exit(EXIT_FAILURE, \"Unable to config sched subport %u, err=%d\\n\",\n\t\t\t\t\tsubport, err);\n\t\t}\n\n\t\tfor (pipe = 0; pipe < port_params.n_pipes_per_subport; pipe ++) {\n\t\t\tif (app_pipe_to_profile[subport][pipe] != -1) {\n\t\t\t\terr = rte_sched_pipe_config(port, subport, pipe,\n\t\t\t\t\t\tapp_pipe_to_profile[subport][pipe]);\n\t\t\t\tif (err) {\n\t\t\t\t\trte_exit(EXIT_FAILURE, \"Unable to config sched pipe %u \"\n\t\t\t\t\t\t\t\"for profile %d, err=%d\\n\", pipe,\n\t\t\t\t\t\t\tapp_pipe_to_profile[subport][pipe], err);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn port;\n}\n\nstatic int\napp_load_cfg_profile(const char *profile)\n{\n\tif (profile == NULL)\n\t\treturn 0;\n\tstruct rte_cfgfile *file = rte_cfgfile_load(profile, 0);\n\tif (file == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot load configuration profile %s\\n\", profile);\n\n\tcfg_load_port(file, &port_params);\n\tcfg_load_subport(file, subport_params);\n\tcfg_load_pipe(file, pipe_profiles);\n\n\trte_cfgfile_close(file);\n\n\treturn 0;\n}\n\nint app_init(void)\n{\n\tuint32_t i;\n\tchar ring_name[MAX_NAME_LEN];\n\tchar pool_name[MAX_NAME_LEN];\n\n\tif (rte_eth_dev_count() == 0)\n\t\trte_exit(EXIT_FAILURE, \"No Ethernet port - bye\\n\");\n\n\t/* load configuration profile */\n\tif (app_load_cfg_profile(cfg_profile) != 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid configuration profile\\n\");\n\n\t/* Initialize each active flow */\n\tfor(i = 0; i < nb_pfc; i++) {\n\t\tuint32_t socket = rte_lcore_to_socket_id(qos_conf[i].rx_core);\n\t\tstruct rte_ring *ring;\n\n\t\tsnprintf(ring_name, MAX_NAME_LEN, \"ring-%u-%u\", i, qos_conf[i].rx_core);\n\t\tring = rte_ring_lookup(ring_name);\n\t\tif (ring == NULL)\n\t\t\tqos_conf[i].rx_ring = rte_ring_create(ring_name, ring_conf.ring_size,\n\t\t\t \tsocket, RING_F_SP_ENQ | RING_F_SC_DEQ);\n\t\telse\n\t\t\tqos_conf[i].rx_ring = ring;\n\n\t\tsnprintf(ring_name, MAX_NAME_LEN, \"ring-%u-%u\", i, qos_conf[i].tx_core);\n\t\tring = rte_ring_lookup(ring_name);\n\t\tif (ring == NULL)\n\t\t\tqos_conf[i].tx_ring = rte_ring_create(ring_name, ring_conf.ring_size,\n\t\t\t\tsocket, RING_F_SP_ENQ | RING_F_SC_DEQ);\n\t\telse\n\t\t\tqos_conf[i].tx_ring = ring;\n\n\n\t\t/* create the mbuf pools for each RX Port */\n\t\tsnprintf(pool_name, MAX_NAME_LEN, \"mbuf_pool%u\", i);\n\t\tqos_conf[i].mbuf_pool = rte_pktmbuf_pool_create(pool_name,\n\t\t\tmp_size, burst_conf.rx_burst * 4, 0,\n\t\t\tRTE_MBUF_DEFAULT_BUF_SIZE,\n\t\t\trte_eth_dev_socket_id(qos_conf[i].rx_port));\n\t\tif (qos_conf[i].mbuf_pool == NULL)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot init mbuf pool for socket %u\\n\", i);\n\n\t\tapp_init_port(qos_conf[i].rx_port, qos_conf[i].mbuf_pool);\n\t\tapp_init_port(qos_conf[i].tx_port, qos_conf[i].mbuf_pool);\n\n\t\tqos_conf[i].sched_port = app_init_sched_port(qos_conf[i].tx_port, socket);\n\t}\n\n\tRTE_LOG(INFO, APP, \"time stamp clock running at %\" PRIu64 \" Hz\\n\",\n\t\t\t rte_get_timer_hz());\n\n\tRTE_LOG(INFO, APP, \"Ring sizes: NIC RX = %u, Mempool = %d SW queue = %u,\"\n\t\t\t \"NIC TX = %u\\n\", ring_conf.rx_size, mp_size, ring_conf.ring_size,\n\t\t\t ring_conf.tx_size);\n\n\tRTE_LOG(INFO, APP, \"Burst sizes: RX read = %hu, RX write = %hu,\\n\"\n\t\t\t\t\t\t \" Worker read/QoS enqueue = %hu,\\n\"\n\t\t\t\t\t\t \" QoS dequeue = %hu, Worker write = %hu\\n\",\n\t\tburst_conf.rx_burst, burst_conf.ring_burst, burst_conf.ring_burst,\n\t\tburst_conf.qos_dequeue, burst_conf.tx_burst);\n\n\tRTE_LOG(INFO, APP, \"NIC thresholds RX (p = %hhu, h = %hhu, w = %hhu),\"\n\t\t\t\t \"TX (p = %hhu, h = %hhu, w = %hhu)\\n\",\n\t\trx_thresh.pthresh, rx_thresh.hthresh, rx_thresh.wthresh,\n\t\ttx_thresh.pthresh, tx_thresh.hthresh, tx_thresh.wthresh);\n\n\treturn 0;\n}\n" }, { "path": "examples/qos_sched/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"main.h\"\n\n#define APP_MODE_NONE 0\n#define APP_RX_MODE 1\n#define APP_WT_MODE 2\n#define APP_TX_MODE 4\n\nuint8_t interactive = APP_INTERACTIVE_DEFAULT;\nuint32_t qavg_period = APP_QAVG_PERIOD;\nuint32_t qavg_ntimes = APP_QAVG_NTIMES;\n\n/* main processing loop */\nstatic int\napp_main_loop(__attribute__((unused))void *dummy)\n{\n\tuint32_t lcore_id;\n\tuint32_t i, mode;\n\tuint32_t rx_idx = 0;\n\tuint32_t wt_idx = 0;\n\tuint32_t tx_idx = 0;\n\tstruct thread_conf *rx_confs[MAX_DATA_STREAMS];\n\tstruct thread_conf *wt_confs[MAX_DATA_STREAMS];\n\tstruct thread_conf *tx_confs[MAX_DATA_STREAMS];\n\n\tmemset(rx_confs, 0, sizeof(rx_confs));\n\tmemset(wt_confs, 0, sizeof(wt_confs));\n\tmemset(tx_confs, 0, sizeof(tx_confs));\n\n\n\tmode = APP_MODE_NONE;\n\tlcore_id = rte_lcore_id();\n\n\tfor (i = 0; i < nb_pfc; i++) {\n\t\tstruct flow_conf *flow = &qos_conf[i];\n\n\t\tif (flow->rx_core == lcore_id) {\n\t\t\tflow->rx_thread.rx_port = flow->rx_port;\n\t\t\tflow->rx_thread.rx_ring = flow->rx_ring;\n\t\t\tflow->rx_thread.rx_queue = flow->rx_queue;\n\n\t\t\trx_confs[rx_idx++] = &flow->rx_thread;\n\n\t\t\tmode |= APP_RX_MODE;\n\t\t}\n\t\tif (flow->tx_core == lcore_id) {\n\t\t\tflow->tx_thread.tx_port = flow->tx_port;\n\t\t\tflow->tx_thread.tx_ring = flow->tx_ring;\n\t\t\tflow->tx_thread.tx_queue = flow->tx_queue;\n\n\t\t\ttx_confs[tx_idx++] = &flow->tx_thread;\n\n\t\t\tmode |= APP_TX_MODE;\n\t\t}\n\t\tif (flow->wt_core == lcore_id) {\n\t\t\tflow->wt_thread.rx_ring = flow->rx_ring;\n\t\t\tflow->wt_thread.tx_ring = flow->tx_ring;\n\t\t\tflow->wt_thread.tx_port = flow->tx_port;\n\t\t\tflow->wt_thread.sched_port = flow->sched_port;\n\n\t\t\twt_confs[wt_idx++] = &flow->wt_thread;\n\n\t\t\tmode |= APP_WT_MODE;\n\t\t}\n\t}\n\n\tif (mode == APP_MODE_NONE) {\n\t\tRTE_LOG(INFO, APP, \"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn -1;\n\t}\n\n\tif (mode == (APP_RX_MODE | APP_WT_MODE)) {\n\t\tRTE_LOG(INFO, APP, \"lcore %u was configured for both RX and WT !!!\\n\",\n\t\t\t\t lcore_id);\n\t\treturn -1;\n\t}\n\n\tRTE_LOG(INFO, APP, \"entering main loop on lcore %u\\n\", lcore_id);\n\t/* initialize mbuf memory */\n\tif (mode == APP_RX_MODE) {\n\t\tfor (i = 0; i < rx_idx; i++) {\n\t\t\tRTE_LOG(INFO, APP, \"flow %u lcoreid %u \"\n\t\t\t\t\t\"reading port %\"PRIu8\"\\n\",\n\t\t\t\t\ti, lcore_id, rx_confs[i]->rx_port);\n\t\t}\n\n\t\tapp_rx_thread(rx_confs);\n\t}\n\telse if (mode == (APP_TX_MODE | APP_WT_MODE)) {\n\t\tfor (i = 0; i < wt_idx; i++) {\n\t\t\twt_confs[i]->m_table = rte_malloc(\"table_wt\", sizeof(struct rte_mbuf *)\n\t\t\t\t\t* burst_conf.tx_burst, RTE_CACHE_LINE_SIZE);\n\n\t\t\tif (wt_confs[i]->m_table == NULL)\n\t\t\t\trte_panic(\"flow %u unable to allocate memory buffer\\n\", i);\n\n\t\t\tRTE_LOG(INFO, APP, \"flow %u lcoreid %u sched+write \"\n\t\t\t\t\t\"port %\"PRIu8\"\\n\",\n\t\t\t\t\ti, lcore_id, wt_confs[i]->tx_port);\n\t\t}\n\n\t\tapp_mixed_thread(wt_confs);\n\t}\n\telse if (mode == APP_TX_MODE) {\n\t\tfor (i = 0; i < tx_idx; i++) {\n\t\t\ttx_confs[i]->m_table = rte_malloc(\"table_tx\", sizeof(struct rte_mbuf *)\n\t\t\t\t\t* burst_conf.tx_burst, RTE_CACHE_LINE_SIZE);\n\n\t\t\tif (tx_confs[i]->m_table == NULL)\n\t\t\t\trte_panic(\"flow %u unable to allocate memory buffer\\n\", i);\n\n\t\t\tRTE_LOG(INFO, APP, \"flow %u lcoreid %u \"\n\t\t\t\t\t\"writing port %\"PRIu8\"\\n\",\n\t\t\t\t\ti, lcore_id, tx_confs[i]->tx_port);\n\t\t}\n\n\t\tapp_tx_thread(tx_confs);\n\t}\n\telse if (mode == APP_WT_MODE){\n\t\tfor (i = 0; i < wt_idx; i++) {\n\t\t\tRTE_LOG(INFO, APP, \"flow %u lcoreid %u scheduling \\n\", i, lcore_id);\n\t\t}\n\n\t\tapp_worker_thread(wt_confs);\n\t}\n\n\treturn 0;\n}\n\nvoid\napp_stat(void)\n{\n\tuint32_t i;\n\tstruct rte_eth_stats stats;\n\tstatic struct rte_eth_stats rx_stats[MAX_DATA_STREAMS];\n\tstatic struct rte_eth_stats tx_stats[MAX_DATA_STREAMS];\n\n\t/* print statistics */\n\tfor(i = 0; i < nb_pfc; i++) {\n\t\tstruct flow_conf *flow = &qos_conf[i];\n\n\t\trte_eth_stats_get(flow->rx_port, &stats);\n\t\tprintf(\"\\nRX port %\"PRIu8\": rx: %\"PRIu64 \" err: %\"PRIu64\n\t\t\t\t\" no_mbuf: %\"PRIu64 \"\\n\",\n\t\t\t\tflow->rx_port,\n\t\t\t\tstats.ipackets - rx_stats[i].ipackets,\n\t\t\t\tstats.ierrors - rx_stats[i].ierrors,\n\t\t\t\tstats.rx_nombuf - rx_stats[i].rx_nombuf);\n\t\tmemcpy(&rx_stats[i], &stats, sizeof(stats));\n\n\t\trte_eth_stats_get(flow->tx_port, &stats);\n\t\tprintf(\"TX port %\"PRIu8\": tx: %\" PRIu64 \" err: %\" PRIu64 \"\\n\",\n\t\t\t\tflow->tx_port,\n\t\t\t\tstats.opackets - tx_stats[i].opackets,\n\t\t\t\tstats.oerrors - tx_stats[i].oerrors);\n\t\tmemcpy(&tx_stats[i], &stats, sizeof(stats));\n\n\t\t//printf(\"MP = %d\\n\", rte_mempool_count(conf->app_pktmbuf_pool));\n\n#if APP_COLLECT_STAT\n\t\tprintf(\"-------+------------+------------+\\n\");\n\t\tprintf(\" | received | dropped |\\n\");\n\t\tprintf(\"-------+------------+------------+\\n\");\n\t\tprintf(\" RX | %10\" PRIu64 \" | %10\" PRIu64 \" |\\n\",\n\t\t\tflow->rx_thread.stat.nb_rx,\n\t\t\tflow->rx_thread.stat.nb_drop);\n\t\tprintf(\"QOS+TX | %10\" PRIu64 \" | %10\" PRIu64 \" | pps: %\"PRIu64 \" \\n\",\n\t\t\tflow->wt_thread.stat.nb_rx,\n\t\t\tflow->wt_thread.stat.nb_drop,\n\t\t\tflow->wt_thread.stat.nb_rx - flow->wt_thread.stat.nb_drop);\n\t\tprintf(\"-------+------------+------------+\\n\");\n\n\t\tmemset(&flow->rx_thread.stat, 0, sizeof(struct thread_stat));\n\t\tmemset(&flow->wt_thread.stat, 0, sizeof(struct thread_stat));\n#endif\n\t}\n}\n\nint\nmain(int argc, char **argv)\n{\n\tint ret;\n\n\tret = app_parse_args(argc, argv);\n\tif (ret < 0)\n\t\treturn -1;\n\n\tret = app_init();\n\tif (ret < 0)\n\t\treturn -1;\n\n\t/* launch per-lcore init on every lcore */\n\trte_eal_mp_remote_launch(app_main_loop, NULL, SKIP_MASTER);\n\n\tif (interactive) {\n\t\tsleep(1);\n\t\tprompt();\n\t}\n\telse {\n\t\t/* print statistics every second */\n\t\twhile(1) {\n\t\t\tsleep(1);\n\t\t\tapp_stat();\n\t\t}\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/qos_sched/main.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _MAIN_H_\n#define _MAIN_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n#define RTE_LOGTYPE_APP RTE_LOGTYPE_USER1\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define APP_INTERACTIVE_DEFAULT 0\n\n#define APP_RX_DESC_DEFAULT 128\n#define APP_TX_DESC_DEFAULT 256\n\n#define APP_RING_SIZE (8*1024)\n#define NB_MBUF (2*1024*1024)\n\n#define MAX_PKT_RX_BURST 64\n#define PKT_ENQUEUE 64\n#define PKT_DEQUEUE 32\n#define MAX_PKT_TX_BURST 64\n\n#define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */\n#define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */\n#define RX_WTHRESH 4 /**< Default values of RX write-back threshold reg. */\n\n#define TX_PTHRESH 36 /**< Default values of TX prefetch threshold reg. */\n#define TX_HTHRESH 0 /**< Default values of TX host threshold reg. */\n#define TX_WTHRESH 0 /**< Default values of TX write-back threshold reg. */\n\n#define BURST_TX_DRAIN_US 100\n\n#define MAX_DATA_STREAMS (RTE_MAX_LCORE/2)\n#define MAX_SCHED_SUBPORTS\t\t8\n#define MAX_SCHED_PIPES\t\t4096\n\n#ifndef APP_COLLECT_STAT\n#define APP_COLLECT_STAT\t\t1\n#endif\n\n#if APP_COLLECT_STAT\n#define APP_STATS_ADD(stat,val) (stat) += (val)\n#else\n#define APP_STATS_ADD(stat,val) do {(void) (val);} while (0)\n#endif\n\n#define APP_QAVG_NTIMES 10\n#define APP_QAVG_PERIOD 100\n\nstruct thread_stat\n{\n\tuint64_t nb_rx;\n\tuint64_t nb_drop;\n};\n\n\nstruct thread_conf\n{\n\tuint32_t counter;\n\tuint32_t n_mbufs;\n\tstruct rte_mbuf **m_table;\n\n\tuint8_t rx_port;\n\tuint8_t tx_port;\n\tuint16_t rx_queue;\n\tuint16_t tx_queue;\n\tstruct rte_ring *rx_ring;\n\tstruct rte_ring *tx_ring;\n\tstruct rte_sched_port *sched_port;\n\n#if APP_COLLECT_STAT\n\tstruct thread_stat stat;\n#endif\n} __rte_cache_aligned;\n\n\nstruct flow_conf\n{\n\tuint32_t rx_core;\n\tuint32_t wt_core;\n\tuint32_t tx_core;\n\tuint8_t rx_port;\n\tuint8_t tx_port;\n\tuint16_t rx_queue;\n\tuint16_t tx_queue;\n\tstruct rte_ring *rx_ring;\n\tstruct rte_ring *tx_ring;\n\tstruct rte_sched_port *sched_port;\n\tstruct rte_mempool *mbuf_pool;\n\n\tstruct thread_conf rx_thread;\n\tstruct thread_conf wt_thread;\n\tstruct thread_conf tx_thread;\n};\n\n\nstruct ring_conf\n{\n\tuint32_t rx_size;\n\tuint32_t ring_size;\n\tuint32_t tx_size;\n};\n\nstruct burst_conf\n{\n\tuint16_t rx_burst;\n\tuint16_t ring_burst;\n\tuint16_t qos_dequeue;\n\tuint16_t tx_burst;\n};\n\nstruct ring_thresh\n{\n\tuint8_t pthresh; /**< Ring prefetch threshold. */\n\tuint8_t hthresh; /**< Ring host threshold. */\n\tuint8_t wthresh; /**< Ring writeback threshold. */\n};\n\nextern uint8_t interactive;\nextern uint32_t qavg_period;\nextern uint32_t qavg_ntimes;\nextern uint32_t nb_pfc;\nextern const char *cfg_profile;\nextern int mp_size;\nextern struct flow_conf qos_conf[];\nextern int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES];\n\nextern struct ring_conf ring_conf;\nextern struct burst_conf burst_conf;\nextern struct ring_thresh rx_thresh;\nextern struct ring_thresh tx_thresh;\n\nextern struct rte_sched_port_params port_params;\n\nint app_parse_args(int argc, char **argv);\nint app_init(void);\n\nvoid prompt(void);\nvoid app_rx_thread(struct thread_conf **qconf);\nvoid app_tx_thread(struct thread_conf **qconf);\nvoid app_worker_thread(struct thread_conf **qconf);\nvoid app_mixed_thread(struct thread_conf **qconf);\n\nvoid app_stat(void);\nint subport_stat(uint8_t port_id, uint32_t subport_id);\nint pipe_stat(uint8_t port_id, uint32_t subport_id, uint32_t pipe_id);\nint qavg_q(uint8_t port_id, uint32_t subport_id, uint32_t pipe_id, uint8_t tc, uint8_t q);\nint qavg_tcpipe(uint8_t port_id, uint32_t subport_id, uint32_t pipe_id, uint8_t tc);\nint qavg_pipe(uint8_t port_id, uint32_t subport_id, uint32_t pipe_id);\nint qavg_tcsubport(uint8_t port_id, uint32_t subport_id, uint8_t tc);\nint qavg_subport(uint8_t port_id, uint32_t subport_id);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _MAIN_H_ */\n" }, { "path": "examples/qos_sched/profile.cfg", "content": "; BSD LICENSE\n;\n; Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions\n; are met:\n;\n; * Redistributions of source code must retain the above copyright\n; notice, this list of conditions and the following disclaimer.\n; * Redistributions in binary form must reproduce the above copyright\n; notice, this list of conditions and the following disclaimer in\n; the documentation and/or other materials provided with the\n; distribution.\n; * Neither the name of Intel Corporation nor the names of its\n; contributors may be used to endorse or promote products derived\n; from this software without specific prior written permission.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n; \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n; This file enables the following hierarchical scheduler configuration for each\n; 10GbE output port:\n;\t* Single subport (subport 0):\n;\t\t- Subport rate set to 100% of port rate\n;\t\t- Each of the 4 traffic classes has rate set to 100% of port rate\n;\t* 4K pipes per subport 0 (pipes 0 .. 4095) with identical configuration:\n;\t\t- Pipe rate set to 1/4K of port rate\n;\t\t- Each of the 4 traffic classes has rate set to 100% of pipe rate\n;\t\t- Within each traffic class, the byte-level WRR weights for the 4 queues\n; are set to 1:1:1:1\n;\n; For more details, please refer to chapter \"Quality of Service (QoS) Framework\"\n; of Intel Data Plane Development Kit (Intel DPDK) Programmer's Guide.\n\n; Port configuration\n[port]\nframe overhead = 24\nnumber of subports per port = 1\nnumber of pipes per subport = 4096\nqueue sizes = 64 64 64 64\n\n; Subport configuration\n[subport 0]\ntb rate = 1250000000 ; Bytes per second\ntb size = 1000000 ; Bytes\n\ntc 0 rate = 1250000000 ; Bytes per second\ntc 1 rate = 1250000000 ; Bytes per second\ntc 2 rate = 1250000000 ; Bytes per second\ntc 3 rate = 1250000000 ; Bytes per second\ntc period = 10 ; Milliseconds\n\npipe 0-4095 = 0 ; These pipes are configured with pipe profile 0\n\n; Pipe configuration\n[pipe profile 0]\ntb rate = 305175 ; Bytes per second\ntb size = 1000000 ; Bytes\n\ntc 0 rate = 305175 ; Bytes per second\ntc 1 rate = 305175 ; Bytes per second\ntc 2 rate = 305175 ; Bytes per second\ntc 3 rate = 305175 ; Bytes per second\ntc period = 40 ; Milliseconds\n\ntc 3 oversubscription weight = 1\n\ntc 0 wrr weights = 1 1 1 1\ntc 1 wrr weights = 1 1 1 1\ntc 2 wrr weights = 1 1 1 1\ntc 3 wrr weights = 1 1 1 1\n\n; RED params per traffic class and color (Green / Yellow / Red)\n[red]\ntc 0 wred min = 48 40 32\ntc 0 wred max = 64 64 64\ntc 0 wred inv prob = 10 10 10\ntc 0 wred weight = 9 9 9\n\ntc 1 wred min = 48 40 32\ntc 1 wred max = 64 64 64\ntc 1 wred inv prob = 10 10 10\ntc 1 wred weight = 9 9 9\n\ntc 2 wred min = 48 40 32\ntc 2 wred max = 64 64 64\ntc 2 wred inv prob = 10 10 10\ntc 2 wred weight = 9 9 9\n\ntc 3 wred min = 48 40 32\ntc 3 wred max = 64 64 64\ntc 3 wred inv prob = 10 10 10\ntc 3 wred weight = 9 9 9\n" }, { "path": "examples/qos_sched/profile_ov.cfg", "content": "; BSD LICENSE\n;\n; Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n; All rights reserved.\n;\n; Redistribution and use in source and binary forms, with or without\n; modification, are permitted provided that the following conditions\n; are met:\n;\n; * Redistributions of source code must retain the above copyright\n; notice, this list of conditions and the following disclaimer.\n; * Redistributions in binary form must reproduce the above copyright\n; notice, this list of conditions and the following disclaimer in\n; the documentation and/or other materials provided with the\n; distribution.\n; * Neither the name of Intel Corporation nor the names of its\n; contributors may be used to endorse or promote products derived\n; from this software without specific prior written permission.\n;\n; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n; \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n; LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n; A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n; OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n; DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n; THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n; Port configuration\n[port]\nframe overhead = 24\nnumber of subports per port = 1\nnumber of pipes per subport = 32\nqueue sizes = 64 64 64 64\n\n; Subport configuration\n[subport 0]\ntb rate = 8400000 ; Bytes per second\ntb size = 100000 ; Bytes\n\ntc 0 rate = 8400000 ; Bytes per second\ntc 1 rate = 8400000 ; Bytes per second\ntc 2 rate = 8400000 ; Bytes per second\ntc 3 rate = 8400000 ; Bytes per second\ntc period = 10 ; Milliseconds\n\npipe 0-31 = 0 ; These pipes are configured with pipe profile 0\n\n; Pipe configuration\n[pipe profile 0]\ntb rate = 16800000 ; Bytes per second\ntb size = 1000000 ; Bytes\n\ntc 0 rate = 16800000 ; Bytes per second\ntc 1 rate = 16800000 ; Bytes per second\ntc 2 rate = 16800000 ; Bytes per second\ntc 3 rate = 16800000 ; Bytes per second\ntc period = 28 ; Milliseconds\n\ntc 3 oversubscription weight = 1\n\ntc 0 wrr weights = 1 1 1 1\ntc 1 wrr weights = 1 1 1 1\ntc 2 wrr weights = 1 1 1 1\ntc 3 wrr weights = 1 1 1 1\n\n; RED params per traffic class and color (Green / Yellow / Red)\n[red]\ntc 0 wred min = 48 40 32\ntc 0 wred max = 64 64 64\ntc 0 wred inv prob = 10 10 10\ntc 0 wred weight = 9 9 9\n\ntc 1 wred min = 48 40 32\ntc 1 wred max = 64 64 64\ntc 1 wred inv prob = 10 10 10\ntc 1 wred weight = 9 9 9\n\ntc 2 wred min = 48 40 32\ntc 2 wred max = 64 64 64\ntc 2 wred inv prob = 10 10 10\ntc 2 wred weight = 9 9 9\n\ntc 3 wred min = 48 40 32\ntc 3 wred max = 64 64 64\ntc 3 wred inv prob = 10 10 10\ntc 3 wred weight = 9 9 9\n" }, { "path": "examples/qos_sched/stats.c", "content": "/*-\n * * BSD LICENSE\n * *\n * * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * * All rights reserved.\n * *\n * * Redistribution and use in source and binary forms, with or without\n * * modification, are permitted provided that the following conditions\n * * are met:\n * *\n * * * Redistributions of source code must retain the above copyright\n * * notice, this list of conditions and the following disclaimer.\n * * * Redistributions in binary form must reproduce the above copyright\n * * notice, this list of conditions and the following disclaimer in\n * * the documentation and/or other materials provided with the\n * * distribution.\n * * * Neither the name of Intel Corporation nor the names of its\n * * contributors may be used to endorse or promote products derived\n * * from this software without specific prior written permission.\n * *\n * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n * */\n\n#include \n#include \n\n#include \"main.h\"\n\nint\nqavg_q(uint8_t port_id, uint32_t subport_id, uint32_t pipe_id, uint8_t tc, uint8_t q)\n{\n struct rte_sched_queue_stats stats;\n struct rte_sched_port *port;\n uint16_t qlen;\n uint32_t queue_id, count, i;\n uint32_t average;\n\n for (i = 0; i < nb_pfc; i++) {\n if (qos_conf[i].tx_port == port_id)\n break;\n }\n if (i == nb_pfc || subport_id >= port_params.n_subports_per_port || pipe_id >= port_params.n_pipes_per_subport\n || tc >= RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE || q >= RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS)\n return -1;\n\n port = qos_conf[i].sched_port;\n\n queue_id = RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * (subport_id * port_params.n_pipes_per_subport + pipe_id);\n queue_id = queue_id + (tc * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + q);\n\n average = 0;\n\n for (count = 0; count < qavg_ntimes; count++) {\n rte_sched_queue_read_stats(port, queue_id, &stats, &qlen);\n average += qlen;\n usleep(qavg_period);\n }\n\n average /= qavg_ntimes;\n\n printf(\"\\nAverage queue size: %\" PRIu32 \" bytes.\\n\\n\", average);\n\n return 0;\n}\n\nint\nqavg_tcpipe(uint8_t port_id, uint32_t subport_id, uint32_t pipe_id, uint8_t tc)\n{\n struct rte_sched_queue_stats stats;\n struct rte_sched_port *port;\n uint16_t qlen;\n uint32_t queue_id, count, i;\n uint32_t average, part_average;\n\n for (i = 0; i < nb_pfc; i++) {\n if (qos_conf[i].tx_port == port_id)\n break;\n }\n if (i == nb_pfc || subport_id >= port_params.n_subports_per_port || pipe_id >= port_params.n_pipes_per_subport\n || tc >= RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE)\n return -1;\n\n port = qos_conf[i].sched_port;\n\n queue_id = RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * (subport_id * port_params.n_pipes_per_subport + pipe_id);\n\n average = 0;\n\n for (count = 0; count < qavg_ntimes; count++) {\n part_average = 0;\n for (i = 0; i < RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; i++) {\n rte_sched_queue_read_stats(port, queue_id + (tc * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + i), &stats, &qlen);\n part_average += qlen;\n }\n average += part_average / RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;\n usleep(qavg_period);\n }\n\n average /= qavg_ntimes;\n\n printf(\"\\nAverage queue size: %\" PRIu32 \" bytes.\\n\\n\", average);\n\n return 0;\n}\n\nint\nqavg_pipe(uint8_t port_id, uint32_t subport_id, uint32_t pipe_id)\n{\n struct rte_sched_queue_stats stats;\n struct rte_sched_port *port;\n uint16_t qlen;\n uint32_t queue_id, count, i;\n uint32_t average, part_average;\n\n for (i = 0; i < nb_pfc; i++) {\n if (qos_conf[i].tx_port == port_id)\n break;\n }\n if (i == nb_pfc || subport_id >= port_params.n_subports_per_port || pipe_id >= port_params.n_pipes_per_subport)\n return -1;\n\n port = qos_conf[i].sched_port;\n\n queue_id = RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * (subport_id * port_params.n_pipes_per_subport + pipe_id);\n\n average = 0;\n\n for (count = 0; count < qavg_ntimes; count++) {\n part_average = 0;\n for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; i++) {\n rte_sched_queue_read_stats(port, queue_id + i, &stats, &qlen);\n part_average += qlen;\n }\n average += part_average / (RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS);\n usleep(qavg_period);\n }\n\n average /= qavg_ntimes;\n\n printf(\"\\nAverage queue size: %\" PRIu32 \" bytes.\\n\\n\", average);\n\n return 0;\n}\n\nint\nqavg_tcsubport(uint8_t port_id, uint32_t subport_id, uint8_t tc)\n{\n struct rte_sched_queue_stats stats;\n struct rte_sched_port *port;\n uint16_t qlen;\n uint32_t queue_id, count, i, j;\n uint32_t average, part_average;\n\n for (i = 0; i < nb_pfc; i++) {\n if (qos_conf[i].tx_port == port_id)\n break;\n }\n if (i == nb_pfc || subport_id >= port_params.n_subports_per_port || tc >= RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE)\n return -1;\n\n port = qos_conf[i].sched_port;\n\n average = 0;\n\n for (count = 0; count < qavg_ntimes; count++) {\n part_average = 0;\n for (i = 0; i < port_params.n_pipes_per_subport; i++) {\n queue_id = RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * (subport_id * port_params.n_pipes_per_subport + i);\n\n for (j = 0; j < RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; j++) {\n rte_sched_queue_read_stats(port, queue_id + (tc * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + j), &stats, &qlen);\n part_average += qlen;\n }\n }\n\n average += part_average / (port_params.n_pipes_per_subport * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS);\n usleep(qavg_period);\n }\n\n average /= qavg_ntimes;\n\n printf(\"\\nAverage queue size: %\" PRIu32 \" bytes.\\n\\n\", average);\n\n return 0;\n}\n\nint\nqavg_subport(uint8_t port_id, uint32_t subport_id)\n{\n struct rte_sched_queue_stats stats;\n struct rte_sched_port *port;\n uint16_t qlen;\n uint32_t queue_id, count, i, j;\n uint32_t average, part_average;\n\n for (i = 0; i < nb_pfc; i++) {\n if (qos_conf[i].tx_port == port_id)\n break;\n }\n if (i == nb_pfc || subport_id >= port_params.n_subports_per_port)\n return -1;\n\n port = qos_conf[i].sched_port;\n\n average = 0;\n\n for (count = 0; count < qavg_ntimes; count++) {\n part_average = 0;\n for (i = 0; i < port_params.n_pipes_per_subport; i++) {\n queue_id = RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * (subport_id * port_params.n_pipes_per_subport + i);\n\n for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; j++) {\n rte_sched_queue_read_stats(port, queue_id + j, &stats, &qlen);\n part_average += qlen;\n }\n }\n\n average += part_average / (port_params.n_pipes_per_subport * RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS);\n usleep(qavg_period);\n }\n\n average /= qavg_ntimes;\n\n printf(\"\\nAverage queue size: %\" PRIu32 \" bytes.\\n\\n\", average);\n\n return 0;\n}\n\nint\nsubport_stat(uint8_t port_id, uint32_t subport_id)\n{\n struct rte_sched_subport_stats stats;\n struct rte_sched_port *port;\n uint32_t tc_ov[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n uint8_t i;\n\n for (i = 0; i < nb_pfc; i++) {\n if (qos_conf[i].tx_port == port_id)\n break;\n }\n if (i == nb_pfc || subport_id >= port_params.n_subports_per_port)\n return -1;\n\n port = qos_conf[i].sched_port;\n\tmemset (tc_ov, 0, sizeof(tc_ov));\n\n rte_sched_subport_read_stats(port, subport_id, &stats, tc_ov);\n\n printf(\"\\n\");\n printf(\"+----+-------------+-------------+-------------+-------------+-------------+\\n\");\n printf(\"| TC | Pkts OK |Pkts Dropped | Bytes OK |Bytes Dropped| OV Status |\\n\");\n printf(\"+----+-------------+-------------+-------------+-------------+-------------+\\n\");\n\n for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n printf(\"| %d | %11\" PRIu32 \" | %11\" PRIu32 \" | %11\" PRIu32 \" | %11\" PRIu32 \" | %11\" PRIu32 \" |\\n\", i,\n stats.n_pkts_tc[i], stats.n_pkts_tc_dropped[i],\n stats.n_bytes_tc[i], stats.n_bytes_tc_dropped[i], tc_ov[i]);\n printf(\"+----+-------------+-------------+-------------+-------------+-------------+\\n\");\n }\n printf(\"\\n\");\n\n return 0;\n}\n\nint\npipe_stat(uint8_t port_id, uint32_t subport_id, uint32_t pipe_id)\n{\n struct rte_sched_queue_stats stats;\n struct rte_sched_port *port;\n uint16_t qlen;\n uint8_t i, j;\n uint32_t queue_id;\n\n for (i = 0; i < nb_pfc; i++) {\n if (qos_conf[i].tx_port == port_id)\n break;\n }\n if (i == nb_pfc || subport_id >= port_params.n_subports_per_port || pipe_id >= port_params.n_pipes_per_subport)\n return -1;\n\n port = qos_conf[i].sched_port;\n\n queue_id = RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * (subport_id * port_params.n_pipes_per_subport + pipe_id);\n\n printf(\"\\n\");\n printf(\"+----+-------+-------------+-------------+-------------+-------------+-------------+\\n\");\n printf(\"| TC | Queue | Pkts OK |Pkts Dropped | Bytes OK |Bytes Dropped| Length |\\n\");\n printf(\"+----+-------+-------------+-------------+-------------+-------------+-------------+\\n\");\n\n for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n for (j = 0; j < RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; j++) {\n\n rte_sched_queue_read_stats(port, queue_id + (i * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + j), &stats, &qlen);\n\n printf(\"| %d | %d | %11\" PRIu32 \" | %11\" PRIu32 \" | %11\" PRIu32 \" | %11\" PRIu32 \" | %11i |\\n\", i, j,\n stats.n_pkts, stats.n_pkts_dropped, stats.n_bytes, stats.n_bytes_dropped, qlen);\n printf(\"+----+-------+-------------+-------------+-------------+-------------+-------------+\\n\");\n }\n if (i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE - 1)\n printf(\"+----+-------+-------------+-------------+-------------+-------------+-------------+\\n\");\n }\n printf(\"\\n\");\n\n return 0;\n}\n" }, { "path": "examples/quota_watermark/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nDIRS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += qw\nDIRS-$(CONFIG_RTE_EXEC_ENV_LINUXAPP) += qwctl\n\ninclude $(RTE_SDK)/mk/rte.extsubdir.mk\n" }, { "path": "examples/quota_watermark/include/conf.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _CONF_H_\n#define _CONF_H_\n\n#define RING_SIZE 1024\n#define MAX_PKT_QUOTA 64\n\n#define RX_DESC_PER_QUEUE 128\n#define TX_DESC_PER_QUEUE 512\n\n#define MBUF_DATA_SIZE RTE_MBUF_DEFAULT_BUF_SIZE\n#define MBUF_PER_POOL 8192\n\n#define QUOTA_WATERMARK_MEMZONE_NAME \"qw_global_vars\"\n\n#endif /* _CONF_H_ */\n" }, { "path": "examples/quota_watermark/qw/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = qw\n\n# all source are stored in SRCS-y\nSRCS-y := args.c init.c main.c\n\nCFLAGS += -O3 -DQW_SOFTWARE_FC\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/quota_watermark/qw/args.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n\n#include \"args.h\"\n\n\nunsigned int portmask = 0;\n\n\nstatic void\nusage(const char *prgname)\n{\n fprintf(stderr, \"Usage: %s [EAL args] -- -p \\n\"\n \"-p PORTMASK: hexadecimal bitmask of NIC ports to configure\\n\",\n prgname);\n}\n\nstatic unsigned long\nparse_portmask(const char *portmask_str)\n{\n\treturn strtoul(portmask_str, NULL, 16);\n}\n\nstatic void\ncheck_core_count(void)\n{\n if (rte_lcore_count() < 3)\n rte_exit(EXIT_FAILURE, \"At least 3 cores need to be passed in the coremask\\n\");\n}\n\nstatic void\ncheck_portmask_value(unsigned int portmask)\n{\n unsigned int port_nb = 0;\n\n port_nb = __builtin_popcount(portmask);\n\n if (port_nb == 0)\n rte_exit(EXIT_FAILURE, \"At least 2 ports need to be passed in the portmask\\n\");\n\n if (port_nb % 2 != 0)\n rte_exit(EXIT_FAILURE, \"An even number of ports is required in the portmask\\n\");\n}\n\nint\nparse_qw_args(int argc, char **argv)\n{\n int opt;\n\n while ((opt = getopt(argc, argv, \"h:p:\")) != -1) {\n switch (opt) {\n case 'h':\n usage(argv[0]);\n break;\n case 'p':\n portmask = parse_portmask(optarg);\n break;\n default:\n usage(argv[0]);\n }\n }\n\n check_core_count();\n check_portmask_value(portmask);\n\n return 0;\n}\n" }, { "path": "examples/quota_watermark/qw/args.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _ARGS_H_\n#define _ARGS_H_\n\nextern unsigned int portmask;\n\nint parse_qw_args(int argc, char **argv);\n\n#endif /* _ARGS_H_ */\n" }, { "path": "examples/quota_watermark/qw/init.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"args.h\"\n#include \"init.h\"\n#include \"main.h\"\n#include \"../include/conf.h\"\n\n\nstatic const struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_DCB_NONE,\n\t},\n};\n\nstatic struct rte_eth_fc_conf fc_conf = {\n .mode = RTE_FC_TX_PAUSE,\n .high_water = 80 * 510 / 100,\n .low_water = 60 * 510 / 100,\n .pause_time = 1337,\n .send_xon = 0,\n};\n\n\nvoid configure_eth_port(uint8_t port_id)\n{\n int ret;\n\n rte_eth_dev_stop(port_id);\n\n ret = rte_eth_dev_configure(port_id, 1, 1, &port_conf);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Cannot configure port %u (error %d)\\n\",\n (unsigned) port_id, ret);\n\n /* Initialize the port's RX queue */\n ret = rte_eth_rx_queue_setup(port_id, 0, RX_DESC_PER_QUEUE,\n\t\t\t\trte_eth_dev_socket_id(port_id),\n\t\t\t\tNULL,\n\t\t\t\tmbuf_pool);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Failed to setup RX queue on \"\n \"port %u (error %d)\\n\", (unsigned) port_id, ret);\n\n /* Initialize the port's TX queue */\n ret = rte_eth_tx_queue_setup(port_id, 0, TX_DESC_PER_QUEUE,\n\t\t\t\trte_eth_dev_socket_id(port_id),\n\t\t\t\tNULL);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Failed to setup TX queue on \"\n \"port %u (error %d)\\n\", (unsigned) port_id, ret);\n\n /* Initialize the port's flow control */\n ret = rte_eth_dev_flow_ctrl_set(port_id, &fc_conf);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Failed to setup hardware flow control on \"\n \"port %u (error %d)\\n\", (unsigned) port_id, ret);\n\n /* Start the port */\n ret = rte_eth_dev_start(port_id);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Failed to start port %u (error %d)\\n\",\n (unsigned) port_id, ret);\n\n /* Put it in promiscuous mode */\n rte_eth_promiscuous_enable(port_id);\n}\n\nvoid\ninit_dpdk(void)\n{\n if (rte_eth_dev_count() < 2)\n rte_exit(EXIT_FAILURE, \"Not enough ethernet port available\\n\");\n}\n\nvoid init_ring(int lcore_id, uint8_t port_id)\n{\n struct rte_ring *ring;\n char ring_name[RTE_RING_NAMESIZE];\n\n snprintf(ring_name, RTE_RING_NAMESIZE,\n\t\t\"core%d_port%d\", lcore_id, port_id);\n ring = rte_ring_create(ring_name, RING_SIZE, rte_socket_id(),\n RING_F_SP_ENQ | RING_F_SC_DEQ);\n\n if (ring == NULL)\n rte_exit(EXIT_FAILURE, \"%s\\n\", rte_strerror(rte_errno));\n\n rte_ring_set_water_mark(ring, 80 * RING_SIZE / 100);\n\n rings[lcore_id][port_id] = ring;\n}\n\nvoid\npair_ports(void)\n{\n uint8_t i, j;\n\n /* Pair ports with their \"closest neighbour\" in the portmask */\n for (i = 0; i < RTE_MAX_ETHPORTS; i++)\n if (is_bit_set(i, portmask))\n for (j = (uint8_t) (i + 1); j < RTE_MAX_ETHPORTS; j++)\n if (is_bit_set(j, portmask)) {\n port_pairs[i] = j;\n port_pairs[j] = i;\n i = j;\n break;\n }\n}\n\nvoid\nsetup_shared_variables(void)\n{\n const struct rte_memzone *qw_memzone;\n\n qw_memzone = rte_memzone_reserve(QUOTA_WATERMARK_MEMZONE_NAME, 2 * sizeof(int),\n rte_socket_id(), RTE_MEMZONE_2MB);\n if (qw_memzone == NULL)\n rte_exit(EXIT_FAILURE, \"%s\\n\", rte_strerror(rte_errno));\n\n quota = qw_memzone->addr;\n low_watermark = (unsigned int *) qw_memzone->addr + sizeof(int);\n}\n" }, { "path": "examples/quota_watermark/qw/init.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _INIT_H_\n#define _INIT_H_\n\nvoid configure_eth_port(uint8_t port_id);\nvoid init_dpdk(void);\nvoid init_ring(int lcore_id, uint8_t port_id);\nvoid pair_ports(void);\nvoid setup_shared_variables(void);\n\n#endif /* _INIT_H_ */\n" }, { "path": "examples/quota_watermark/qw/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"args.h\"\n#include \"main.h\"\n#include \"init.h\"\n#include \"../include/conf.h\"\n\n\n#ifdef QW_SOFTWARE_FC\n#define SEND_PAUSE_FRAME(port_id, duration) send_pause_frame(port_id, duration)\n#else\n#define SEND_PAUSE_FRAME(port_id, duration) do { } while(0)\n#endif\n\n#define ETHER_TYPE_FLOW_CONTROL 0x8808\n\nstruct ether_fc_frame {\n uint16_t opcode;\n uint16_t param;\n} __attribute__((__packed__));\n\n\nint *quota;\nunsigned int *low_watermark;\n\nuint8_t port_pairs[RTE_MAX_ETHPORTS];\n\nstruct rte_ring *rings[RTE_MAX_LCORE][RTE_MAX_ETHPORTS];\nstruct rte_mempool *mbuf_pool;\n\n\nstatic void send_pause_frame(uint8_t port_id, uint16_t duration)\n{\n struct rte_mbuf *mbuf;\n struct ether_fc_frame *pause_frame;\n struct ether_hdr *hdr;\n struct ether_addr mac_addr;\n\n RTE_LOG(DEBUG, USER1, \"Sending PAUSE frame (duration=%d) on port %d\\n\",\n duration, port_id);\n\n /* Get a mbuf from the pool */\n mbuf = rte_pktmbuf_alloc(mbuf_pool);\n if (unlikely(mbuf == NULL))\n return;\n\n /* Prepare a PAUSE frame */\n hdr = rte_pktmbuf_mtod(mbuf, struct ether_hdr *);\n pause_frame = (struct ether_fc_frame *) &hdr[1];\n\n rte_eth_macaddr_get(port_id, &mac_addr);\n ether_addr_copy(&mac_addr, &hdr->s_addr);\n\n void *tmp = &hdr->d_addr.addr_bytes[0];\n *((uint64_t *)tmp) = 0x010000C28001ULL;\n\n hdr->ether_type = rte_cpu_to_be_16(ETHER_TYPE_FLOW_CONTROL);\n\n pause_frame->opcode = rte_cpu_to_be_16(0x0001);\n pause_frame->param = rte_cpu_to_be_16(duration);\n\n mbuf->pkt_len = 60;\n mbuf->data_len = 60;\n\n rte_eth_tx_burst(port_id, 0, &mbuf, 1);\n}\n\n/**\n * Get the previous enabled lcore ID\n *\n * @param lcore_id\n * The current lcore ID.\n * @return\n * The previous enabled lcore_id or -1 if not found.\n */\nstatic unsigned int\nget_previous_lcore_id(unsigned int lcore_id)\n{\n int i;\n\n for (i = lcore_id - 1; i >= 0; i--)\n if (rte_lcore_is_enabled(i))\n return i;\n\n return -1;\n}\n\n/**\n * Get the last enabled lcore ID\n *\n * @return\n * The last enabled lcore_id.\n */\nstatic unsigned int\nget_last_lcore_id(void)\n{\n int i;\n\n for (i = RTE_MAX_LCORE; i >= 0; i--)\n if (rte_lcore_is_enabled(i))\n return i;\n\n return 0;\n}\n\nstatic void\nreceive_stage(__attribute__((unused)) void *args)\n{\n int i, ret;\n\n uint8_t port_id;\n uint16_t nb_rx_pkts;\n\n unsigned int lcore_id;\n\n struct rte_mbuf *pkts[MAX_PKT_QUOTA];\n struct rte_ring *ring;\n enum ring_state ring_state[RTE_MAX_ETHPORTS] = { RING_READY };\n\n lcore_id = rte_lcore_id();\n\n RTE_LOG(INFO, USER1,\n \"%s() started on core %u\\n\", __func__, lcore_id);\n\n while (1) {\n\n /* Process each port round robin style */\n for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {\n\n if (!is_bit_set(port_id, portmask))\n continue;\n\n ring = rings[lcore_id][port_id];\n\n if (ring_state[port_id] != RING_READY) {\n if (rte_ring_count(ring) > *low_watermark)\n continue;\n else\n ring_state[port_id] = RING_READY;\n }\n\n /* Enqueue received packets on the RX ring */\n nb_rx_pkts = rte_eth_rx_burst(port_id, 0, pkts, (uint16_t) *quota);\n ret = rte_ring_enqueue_bulk(ring, (void *) pkts, nb_rx_pkts);\n if (ret == -EDQUOT) {\n ring_state[port_id] = RING_OVERLOADED;\n send_pause_frame(port_id, 1337);\n }\n\n else if (ret == -ENOBUFS) {\n\n /* Return mbufs to the pool, effectively dropping packets */\n for (i = 0; i < nb_rx_pkts; i++)\n rte_pktmbuf_free(pkts[i]);\n }\n }\n }\n}\n\nstatic void\npipeline_stage(__attribute__((unused)) void *args)\n{\n int i, ret;\n int nb_dq_pkts;\n\n uint8_t port_id;\n\n unsigned int lcore_id, previous_lcore_id;\n\n void *pkts[MAX_PKT_QUOTA];\n struct rte_ring *rx, *tx;\n enum ring_state ring_state[RTE_MAX_ETHPORTS] = { RING_READY };\n\n lcore_id = rte_lcore_id();\n previous_lcore_id = get_previous_lcore_id(lcore_id);\n\n RTE_LOG(INFO, USER1,\n \"%s() started on core %u - processing packets from core %u\\n\",\n __func__, lcore_id, previous_lcore_id);\n\n while (1) {\n\n for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {\n\n if (!is_bit_set(port_id, portmask))\n continue;\n\n tx = rings[lcore_id][port_id];\n rx = rings[previous_lcore_id][port_id];\n\n if (ring_state[port_id] != RING_READY) {\n if (rte_ring_count(tx) > *low_watermark)\n continue;\n else\n ring_state[port_id] = RING_READY;\n }\n\n /* Dequeue up to quota mbuf from rx */\n nb_dq_pkts = rte_ring_dequeue_burst(rx, pkts, *quota);\n if (unlikely(nb_dq_pkts < 0))\n continue;\n\n /* Enqueue them on tx */\n ret = rte_ring_enqueue_bulk(tx, pkts, nb_dq_pkts);\n if (ret == -EDQUOT)\n ring_state[port_id] = RING_OVERLOADED;\n\n else if (ret == -ENOBUFS) {\n\n /* Return mbufs to the pool, effectively dropping packets */\n for (i = 0; i < nb_dq_pkts; i++)\n rte_pktmbuf_free(pkts[i]);\n }\n }\n }\n}\n\nstatic void\nsend_stage(__attribute__((unused)) void *args)\n{\n\tuint16_t nb_dq_pkts;\n\n uint8_t port_id;\n uint8_t dest_port_id;\n\n unsigned int lcore_id, previous_lcore_id;\n\n struct rte_ring *tx;\n struct rte_mbuf *tx_pkts[MAX_PKT_QUOTA];\n\n lcore_id = rte_lcore_id();\n previous_lcore_id = get_previous_lcore_id(lcore_id);\n\n RTE_LOG(INFO, USER1,\n \"%s() started on core %u - processing packets from core %u\\n\",\n __func__, lcore_id, previous_lcore_id);\n\n while (1) {\n\n /* Process each ring round robin style */\n for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {\n\n if (!is_bit_set(port_id, portmask))\n continue;\n\n dest_port_id = port_pairs[port_id];\n tx = rings[previous_lcore_id][port_id];\n\n if (rte_ring_empty(tx))\n continue;\n\n /* Dequeue packets from tx and send them */\n nb_dq_pkts = (uint16_t) rte_ring_dequeue_burst(tx, (void *) tx_pkts, *quota);\n rte_eth_tx_burst(dest_port_id, 0, tx_pkts, nb_dq_pkts);\n\n /* TODO: Check if nb_dq_pkts == nb_tx_pkts? */\n }\n }\n}\n\nint\nmain(int argc, char **argv)\n{\n int ret;\n unsigned int lcore_id, master_lcore_id, last_lcore_id;\n\n uint8_t port_id;\n\n rte_set_log_level(RTE_LOG_INFO);\n\n ret = rte_eal_init(argc, argv);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Cannot initialize EAL\\n\");\n\n argc -= ret;\n argv += ret;\n\n init_dpdk();\n setup_shared_variables();\n\n *quota = 32;\n *low_watermark = 60 * RING_SIZE / 100;\n\n last_lcore_id = get_last_lcore_id();\n master_lcore_id = rte_get_master_lcore();\n\n /* Parse the application's arguments */\n ret = parse_qw_args(argc, argv);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Invalid quota/watermark argument(s)\\n\");\n\n /* Create a pool of mbuf to store packets */\n mbuf_pool = rte_pktmbuf_pool_create(\"mbuf_pool\", MBUF_PER_POOL, 32, 0,\n\t MBUF_DATA_SIZE, rte_socket_id());\n if (mbuf_pool == NULL)\n rte_panic(\"%s\\n\", rte_strerror(rte_errno));\n\n for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++)\n if (is_bit_set(port_id, portmask)) {\n configure_eth_port(port_id);\n init_ring(master_lcore_id, port_id);\n }\n\n pair_ports();\n\n /* Start pipeline_connect() on all the available slave lcore but the last */\n for (lcore_id = 0 ; lcore_id < last_lcore_id; lcore_id++) {\n if (rte_lcore_is_enabled(lcore_id) && lcore_id != master_lcore_id) {\n\n for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++)\n if (is_bit_set(port_id, portmask))\n init_ring(lcore_id, port_id);\n\n /* typecast is a workaround for GCC 4.3 bug */\n rte_eal_remote_launch((int (*)(void *))pipeline_stage, NULL, lcore_id);\n }\n }\n\n /* Start send_stage() on the last slave core */\n /* typecast is a workaround for GCC 4.3 bug */\n rte_eal_remote_launch((int (*)(void *))send_stage, NULL, last_lcore_id);\n\n /* Start receive_stage() on the master core */\n receive_stage(NULL);\n\n return 0;\n}\n" }, { "path": "examples/quota_watermark/qw/main.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _MAIN_H_\n#define _MAIN_H_\n\n#include \"../include/conf.h\"\n\nenum ring_state {\n RING_READY,\n RING_OVERLOADED,\n};\n\nextern int *quota;\nextern unsigned int *low_watermark;\n\nextern uint8_t port_pairs[RTE_MAX_ETHPORTS];\n\nextern struct rte_ring *rings[RTE_MAX_LCORE][RTE_MAX_ETHPORTS];\nextern struct rte_mempool *mbuf_pool;\n\n\nstatic inline int\nis_bit_set(int i, unsigned int mask)\n{\n return ((1 << i) & mask);\n}\n\n#endif /* _MAIN_H_ */\n" }, { "path": "examples/quota_watermark/qwctl/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = qwctl\n\n# all source are stored in SRCS-y\nSRCS-y := commands.c qwctl.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/quota_watermark/qwctl/commands.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"qwctl.h\"\n#include \"../include/conf.h\"\n\n\n/**\n * help command\n */\n\nstruct cmd_help_tokens {\n cmdline_fixed_string_t verb;\n};\n\ncmdline_parse_token_string_t cmd_help_verb =\n TOKEN_STRING_INITIALIZER(struct cmd_help_tokens, verb, \"help\");\n\nstatic void\ncmd_help_handler(__attribute__((unused)) void *parsed_result,\n struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n cmdline_printf(cl, \"Available commands:\\n\"\n \"- help\\n\"\n \"- set [ring_name|variable] \\n\"\n \"- show [ring_name|variable]\\n\"\n \"\\n\"\n \"Available variables:\\n\"\n \"- low_watermark\\n\"\n \"- quota\\n\"\n \"- ring names follow the core%%u_port%%u format\\n\");\n}\n\ncmdline_parse_inst_t cmd_help = {\n .f = cmd_help_handler,\n .data = NULL,\n .help_str = \"show help\",\n .tokens = {\n (void *) &cmd_help_verb,\n NULL,\n },\n};\n\n\n/**\n * set command\n */\n\nstruct cmd_set_tokens {\n cmdline_fixed_string_t verb;\n cmdline_fixed_string_t variable;\n uint32_t value;\n};\n\ncmdline_parse_token_string_t cmd_set_verb =\n TOKEN_STRING_INITIALIZER(struct cmd_set_tokens, verb, \"set\");\n\ncmdline_parse_token_string_t cmd_set_variable =\n TOKEN_STRING_INITIALIZER(struct cmd_set_tokens, variable, NULL);\n\ncmdline_parse_token_num_t cmd_set_value =\n TOKEN_NUM_INITIALIZER(struct cmd_set_tokens, value, UINT32);\n\nstatic void\ncmd_set_handler(__attribute__((unused)) void *parsed_result,\n struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n struct cmd_set_tokens *tokens = parsed_result;\n struct rte_ring *ring;\n\n if (!strcmp(tokens->variable, \"quota\")) {\n\n if (tokens->value > 0 && tokens->value <= MAX_PKT_QUOTA)\n *quota = tokens->value;\n else\n cmdline_printf(cl, \"quota must be between 1 and %u\\n\", MAX_PKT_QUOTA);\n }\n\n else if (!strcmp(tokens->variable, \"low_watermark\")) {\n\n if (tokens->value <= 100)\n *low_watermark = tokens->value * RING_SIZE / 100;\n else\n cmdline_printf(cl, \"low_watermark must be between 0%% and 100%%\\n\");\n }\n\n else {\n\n ring = rte_ring_lookup(tokens->variable);\n if (ring == NULL)\n cmdline_printf(cl, \"Cannot find ring \\\"%s\\\"\\n\", tokens->variable);\n else\n if (tokens->value >= *low_watermark * 100 / RING_SIZE\n && tokens->value <= 100)\n rte_ring_set_water_mark(ring, tokens->value * RING_SIZE / 100);\n else\n cmdline_printf(cl, \"ring high watermark must be between %u%% \"\n \"and 100%%\\n\", *low_watermark * 100 / RING_SIZE);\n }\n}\n\ncmdline_parse_inst_t cmd_set = {\n .f = cmd_set_handler,\n .data = NULL,\n .help_str = \"Set a variable value\",\n .tokens = {\n (void *) &cmd_set_verb,\n (void *) &cmd_set_variable,\n (void *) &cmd_set_value,\n NULL,\n },\n};\n\n\n/**\n * show command\n */\n\nstruct cmd_show_tokens {\n cmdline_fixed_string_t verb;\n cmdline_fixed_string_t variable;\n};\n\ncmdline_parse_token_string_t cmd_show_verb =\n TOKEN_STRING_INITIALIZER(struct cmd_show_tokens, verb, \"show\");\n\ncmdline_parse_token_string_t cmd_show_variable =\n TOKEN_STRING_INITIALIZER(struct cmd_show_tokens, variable, NULL);\n\n\nstatic void\ncmd_show_handler(__attribute__((unused)) void *parsed_result,\n struct cmdline *cl,\n __attribute__((unused)) void *data)\n{\n struct cmd_show_tokens *tokens = parsed_result;\n struct rte_ring *ring;\n\n if (!strcmp(tokens->variable, \"quota\"))\n cmdline_printf(cl, \"Global quota: %d\\n\", *quota);\n\n else if (!strcmp(tokens->variable, \"low_watermark\"))\n cmdline_printf(cl, \"Global low_watermark: %u\\n\", *low_watermark);\n\n else {\n\n ring = rte_ring_lookup(tokens->variable);\n if (ring == NULL)\n cmdline_printf(cl, \"Cannot find ring \\\"%s\\\"\\n\", tokens->variable);\n else\n rte_ring_dump(stdout, ring);\n }\n}\n\ncmdline_parse_inst_t cmd_show = {\n .f = cmd_show_handler,\n .data = NULL,\n .help_str = \"Show a variable value\",\n .tokens = {\n (void *) &cmd_show_verb,\n (void *) &cmd_show_variable,\n NULL,\n },\n};\n\n\ncmdline_parse_ctx_t qwctl_ctx[] = {\n\t(cmdline_parse_inst_t *)&cmd_help,\n\t(cmdline_parse_inst_t *)&cmd_set,\n\t(cmdline_parse_inst_t *)&cmd_show,\n\tNULL,\n};\n" }, { "path": "examples/quota_watermark/qwctl/commands.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _COMMANDS_H_\n#define _COMMANDS_H_\n\n#include \n\nextern cmdline_parse_ctx_t qwctl_ctx[];\n\n#endif /* _COMMANDS_H_ */\n" }, { "path": "examples/quota_watermark/qwctl/qwctl.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n\n#include \"qwctl.h\"\n#include \"commands.h\"\n#include \"../include/conf.h\"\n\n\nint *quota;\nunsigned int *low_watermark;\n\n\nstatic void\nsetup_shared_variables(void)\n{\n const struct rte_memzone *qw_memzone;\n\n qw_memzone = rte_memzone_lookup(QUOTA_WATERMARK_MEMZONE_NAME);\n if (qw_memzone == NULL)\n rte_exit(EXIT_FAILURE, \"Couldn't find memzone\\n\");\n\n quota = qw_memzone->addr;\n low_watermark = (unsigned int *) qw_memzone->addr + sizeof(int);\n}\n\nint main(int argc, char **argv)\n{\n int ret;\n struct cmdline *cl;\n\n rte_set_log_level(RTE_LOG_INFO);\n\n ret = rte_eal_init(argc, argv);\n if (ret < 0)\n rte_exit(EXIT_FAILURE, \"Cannot initialize EAL\\n\");\n\n setup_shared_variables();\n\n cl = cmdline_stdin_new(qwctl_ctx, \"qwctl> \");\n if (cl == NULL)\n rte_exit(EXIT_FAILURE, \"Cannot create cmdline instance\\n\");\n\n cmdline_interact(cl);\n cmdline_stdin_exit(cl);\n\n return 0;\n}\n" }, { "path": "examples/quota_watermark/qwctl/qwctl.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _MAIN_H_\n#define _MAIN_H_\n\nextern int *quota;\nextern unsigned int *low_watermark;\n\n#endif /* _MAIN_H_ */\n" }, { "path": "examples/rxtx_callbacks/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overridden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = rxtx_callbacks\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\nEXTRA_CFLAGS += -O3 -g -Wfatal-errors\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/rxtx_callbacks/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define RX_RING_SIZE 128\n#define TX_RING_SIZE 512\n\n#define NUM_MBUFS 8191\n#define MBUF_CACHE_SIZE 250\n#define BURST_SIZE 32\n\nstatic const struct rte_eth_conf port_conf_default = {\n\t.rxmode = { .max_rx_pkt_len = ETHER_MAX_LEN, },\n};\n\nstatic unsigned nb_ports;\n\nstatic struct {\n\tuint64_t total_cycles;\n\tuint64_t total_pkts;\n} latency_numbers;\n\n\nstatic uint16_t\nadd_timestamps(uint8_t port __rte_unused, uint16_t qidx __rte_unused,\n\t\tstruct rte_mbuf **pkts, uint16_t nb_pkts,\n\t\tuint16_t max_pkts __rte_unused, void *_ __rte_unused)\n{\n\tunsigned i;\n\tuint64_t now = rte_rdtsc();\n\n\tfor (i = 0; i < nb_pkts; i++)\n\t\tpkts[i]->udata64 = now;\n\treturn nb_pkts;\n}\n\nstatic uint16_t\ncalc_latency(uint8_t port __rte_unused, uint16_t qidx __rte_unused,\n\t\tstruct rte_mbuf **pkts, uint16_t nb_pkts, void *_ __rte_unused)\n{\n\tuint64_t cycles = 0;\n\tuint64_t now = rte_rdtsc();\n\tunsigned i;\n\n\tfor (i = 0; i < nb_pkts; i++)\n\t\tcycles += now - pkts[i]->udata64;\n\tlatency_numbers.total_cycles += cycles;\n\tlatency_numbers.total_pkts += nb_pkts;\n\n\tif (latency_numbers.total_pkts > (100 * 1000 * 1000ULL)) {\n\t\tprintf(\"Latency = %\"PRIu64\" cycles\\n\",\n\t\tlatency_numbers.total_cycles / latency_numbers.total_pkts);\n\t\tlatency_numbers.total_cycles = latency_numbers.total_pkts = 0;\n\t}\n\treturn nb_pkts;\n}\n\n/*\n * Initialises a given port using global settings and with the rx buffers\n * coming from the mbuf_pool passed as parameter\n */\nstatic inline int\nport_init(uint8_t port, struct rte_mempool *mbuf_pool)\n{\n\tstruct rte_eth_conf port_conf = port_conf_default;\n\tconst uint16_t rx_rings = 1, tx_rings = 1;\n\tint retval;\n\tuint16_t q;\n\n\tif (port >= rte_eth_dev_count())\n\t\treturn -1;\n\n\tretval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);\n\tif (retval != 0)\n\t\treturn retval;\n\n\tfor (q = 0; q < rx_rings; q++) {\n\t\tretval = rte_eth_rx_queue_setup(port, q, RX_RING_SIZE,\n\t\t\t\trte_eth_dev_socket_id(port), NULL, mbuf_pool);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\tfor (q = 0; q < tx_rings; q++) {\n\t\tretval = rte_eth_tx_queue_setup(port, q, TX_RING_SIZE,\n\t\t\t\trte_eth_dev_socket_id(port), NULL);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\tretval = rte_eth_dev_start(port);\n\tif (retval < 0)\n\t\treturn retval;\n\n\tstruct ether_addr addr;\n\n\trte_eth_macaddr_get(port, &addr);\n\tprintf(\"Port %u MAC: %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\n\t\t\t\" %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\"\\n\",\n\t\t\t(unsigned)port,\n\t\t\taddr.addr_bytes[0], addr.addr_bytes[1],\n\t\t\taddr.addr_bytes[2], addr.addr_bytes[3],\n\t\t\taddr.addr_bytes[4], addr.addr_bytes[5]);\n\n\trte_eth_promiscuous_enable(port);\n\trte_eth_add_rx_callback(port, 0, add_timestamps, NULL);\n\trte_eth_add_tx_callback(port, 0, calc_latency, NULL);\n\n\treturn 0;\n}\n\n/*\n * Main thread that does the work, reading from INPUT_PORT\n * and writing to OUTPUT_PORT\n */\nstatic __attribute__((noreturn)) void\nlcore_main(void)\n{\n\tuint8_t port;\n\n\tfor (port = 0; port < nb_ports; port++)\n\t\tif (rte_eth_dev_socket_id(port) > 0 &&\n\t\t\t\trte_eth_dev_socket_id(port) !=\n\t\t\t\t\t\t(int)rte_socket_id())\n\t\t\tprintf(\"WARNING, port %u is on remote NUMA node to \"\n\t\t\t\t\t\"polling thread.\\n\\tPerformance will \"\n\t\t\t\t\t\"not be optimal.\\n\", port);\n\n\tprintf(\"\\nCore %u forwarding packets. [Ctrl+C to quit]\\n\",\n\t\t\trte_lcore_id());\n\tfor (;;) {\n\t\tfor (port = 0; port < nb_ports; port++) {\n\t\t\tstruct rte_mbuf *bufs[BURST_SIZE];\n\t\t\tconst uint16_t nb_rx = rte_eth_rx_burst(port, 0,\n\t\t\t\t\tbufs, BURST_SIZE);\n\t\t\tif (unlikely(nb_rx == 0))\n\t\t\t\tcontinue;\n\t\t\tconst uint16_t nb_tx = rte_eth_tx_burst(port ^ 1, 0,\n\t\t\t\t\tbufs, nb_rx);\n\t\t\tif (unlikely(nb_tx < nb_rx)) {\n\t\t\t\tuint16_t buf;\n\n\t\t\t\tfor (buf = nb_tx; buf < nb_rx; buf++)\n\t\t\t\t\trte_pktmbuf_free(bufs[buf]);\n\t\t\t}\n\t\t}\n\t}\n}\n\n/* Main function, does initialisation and calls the per-lcore functions */\nint\nmain(int argc, char *argv[])\n{\n\tstruct rte_mempool *mbuf_pool;\n\tuint8_t portid;\n\n\t/* init EAL */\n\tint ret = rte_eal_init(argc, argv);\n\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Error with EAL initialization\\n\");\n\targc -= ret;\n\targv += ret;\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports < 2 || (nb_ports & 1))\n\t\trte_exit(EXIT_FAILURE, \"Error: number of ports must be even\\n\");\n\n\tmbuf_pool = rte_pktmbuf_pool_create(\"MBUF_POOL\",\n\t\tNUM_MBUFS * nb_ports, MBUF_CACHE_SIZE, 0,\n\t\tRTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\tif (mbuf_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create mbuf pool\\n\");\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++)\n\t\tif (port_init(portid, mbuf_pool) != 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot init port %\"PRIu8\"\\n\",\n\t\t\t\t\tportid);\n\n\tif (rte_lcore_count() > 1)\n\t\tprintf(\"\\nWARNING: Too much enabled lcores - \"\n\t\t\t\"App uses only 1 lcore\\n\");\n\n\t/* call lcore_main on master core only */\n\tlcore_main();\n\treturn 0;\n}\n" }, { "path": "examples/skeleton/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overridden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = basicfwd\n\n# all source are stored in SRCS-y\nSRCS-y := basicfwd.c\n\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\nEXTRA_CFLAGS += -O3 -g -Wfatal-errors\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/skeleton/basicfwd.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define RX_RING_SIZE 128\n#define TX_RING_SIZE 512\n\n#define NUM_MBUFS 8191\n#define MBUF_CACHE_SIZE 250\n#define BURST_SIZE 32\n\nstatic const struct rte_eth_conf port_conf_default = {\n\t.rxmode = { .max_rx_pkt_len = ETHER_MAX_LEN }\n};\n\n/* basicfwd.c: Basic DPDK skeleton forwarding example. */\n\n/*\n * Initializes a given port using global settings and with the RX buffers\n * coming from the mbuf_pool passed as a parameter.\n */\nstatic inline int\nport_init(uint8_t port, struct rte_mempool *mbuf_pool)\n{\n\tstruct rte_eth_conf port_conf = port_conf_default;\n\tconst uint16_t rx_rings = 1, tx_rings = 1;\n\tint retval;\n\tuint16_t q;\n\n\tif (port >= rte_eth_dev_count())\n\t\treturn -1;\n\n\t/* Configure the Ethernet device. */\n\tretval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);\n\tif (retval != 0)\n\t\treturn retval;\n\n\t/* Allocate and set up 1 RX queue per Ethernet port. */\n\tfor (q = 0; q < rx_rings; q++) {\n\t\tretval = rte_eth_rx_queue_setup(port, q, RX_RING_SIZE,\n\t\t\t\trte_eth_dev_socket_id(port), NULL, mbuf_pool);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\t/* Allocate and set up 1 TX queue per Ethernet port. */\n\tfor (q = 0; q < tx_rings; q++) {\n\t\tretval = rte_eth_tx_queue_setup(port, q, TX_RING_SIZE,\n\t\t\t\trte_eth_dev_socket_id(port), NULL);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\t/* Start the Ethernet port. */\n\tretval = rte_eth_dev_start(port);\n\tif (retval < 0)\n\t\treturn retval;\n\n\t/* Display the port MAC address. */\n\tstruct ether_addr addr;\n\trte_eth_macaddr_get(port, &addr);\n\tprintf(\"Port %u MAC: %02\" PRIx8 \" %02\" PRIx8 \" %02\" PRIx8\n\t\t\t \" %02\" PRIx8 \" %02\" PRIx8 \" %02\" PRIx8 \"\\n\",\n\t\t\t(unsigned)port,\n\t\t\taddr.addr_bytes[0], addr.addr_bytes[1],\n\t\t\taddr.addr_bytes[2], addr.addr_bytes[3],\n\t\t\taddr.addr_bytes[4], addr.addr_bytes[5]);\n\n\t/* Enable RX in promiscuous mode for the Ethernet device. */\n\trte_eth_promiscuous_enable(port);\n\n\treturn 0;\n}\n\n/*\n * The lcore main. This is the main thread that does the work, reading from\n * an input port and writing to an output port.\n */\nstatic __attribute__((noreturn)) void\nlcore_main(void)\n{\n\tconst uint8_t nb_ports = rte_eth_dev_count();\n\tuint8_t port;\n\n\t/*\n\t * Check that the port is on the same NUMA node as the polling thread\n\t * for best performance.\n\t */\n\tfor (port = 0; port < nb_ports; port++)\n\t\tif (rte_eth_dev_socket_id(port) > 0 &&\n\t\t\t\trte_eth_dev_socket_id(port) !=\n\t\t\t\t\t\t(int)rte_socket_id())\n\t\t\tprintf(\"WARNING, port %u is on remote NUMA node to \"\n\t\t\t\t\t\"polling thread.\\n\\tPerformance will \"\n\t\t\t\t\t\"not be optimal.\\n\", port);\n\n\tprintf(\"\\nCore %u forwarding packets. [Ctrl+C to quit]\\n\",\n\t\t\trte_lcore_id());\n\n\t/* Run until the application is quit or killed. */\n\tfor (;;) {\n\t\t/*\n\t\t * Receive packets on a port and forward them on the paired\n\t\t * port. The mapping is 0 -> 1, 1 -> 0, 2 -> 3, 3 -> 2, etc.\n\t\t */\n\t\tfor (port = 0; port < nb_ports; port++) {\n\n\t\t\t/* Get burst of RX packets, from first port of pair. */\n\t\t\tstruct rte_mbuf *bufs[BURST_SIZE];\n\t\t\tconst uint16_t nb_rx = rte_eth_rx_burst(port, 0,\n\t\t\t\t\tbufs, BURST_SIZE);\n\n\t\t\tif (unlikely(nb_rx == 0))\n\t\t\t\tcontinue;\n\n\t\t\t/* Send burst of TX packets, to second port of pair. */\n\t\t\tconst uint16_t nb_tx = rte_eth_tx_burst(port ^ 1, 0,\n\t\t\t\t\tbufs, nb_rx);\n\n\t\t\t/* Free any unsent packets. */\n\t\t\tif (unlikely(nb_tx < nb_rx)) {\n\t\t\t\tuint16_t buf;\n\t\t\t\tfor (buf = nb_tx; buf < nb_rx; buf++)\n\t\t\t\t\trte_pktmbuf_free(bufs[buf]);\n\t\t\t}\n\t\t}\n\t}\n}\n\n/*\n * The main function, which does initialization and calls the per-lcore\n * functions.\n */\nint\nmain(int argc, char *argv[])\n{\n\tstruct rte_mempool *mbuf_pool;\n\tunsigned nb_ports;\n\tuint8_t portid;\n\n\t/* Initialize the Environment Abstraction Layer (EAL). */\n\tint ret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Error with EAL initialization\\n\");\n\n\targc -= ret;\n\targv += ret;\n\n\t/* Check that there is an even number of ports to send/receive on. */\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports < 2 || (nb_ports & 1))\n\t\trte_exit(EXIT_FAILURE, \"Error: number of ports must be even\\n\");\n\n\t/* Creates a new mempool in memory to hold the mbufs. */\n\tmbuf_pool = rte_pktmbuf_pool_create(\"MBUF_POOL\", NUM_MBUFS * nb_ports,\n\t\tMBUF_CACHE_SIZE, 0, RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\n\tif (mbuf_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create mbuf pool\\n\");\n\n\t/* Initialize all ports. */\n\tfor (portid = 0; portid < nb_ports; portid++)\n\t\tif (port_init(portid, mbuf_pool) != 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot init port %\"PRIu8 \"\\n\",\n\t\t\t\t\tportid);\n\n\tif (rte_lcore_count() > 1)\n\t\tprintf(\"\\nWARNING: Too many lcores enabled. Only 1 used.\\n\");\n\n\t/* Call lcore_main on the master core only. */\n\tlcore_main();\n\n\treturn 0;\n}\n" }, { "path": "examples/tep_termination/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overridden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifneq ($(CONFIG_RTE_EXEC_ENV),\"linuxapp\")\n$(error This application can only operate in a linuxapp environment, \\\nplease change the definition of the RTE_TARGET environment variable)\nendif\n\n# binary name\nAPP = tep_termination\n\n# all source are stored in SRCS-y\nSRCS-y := main.c vxlan_setup.c vxlan.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/tep_termination/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n#include \"vxlan.h\"\n#include \"vxlan_setup.h\"\n\n/* the maximum number of external ports supported */\n#define MAX_SUP_PORTS 1\n\n/**\n * Calculate the number of buffers needed per port\n */\n#define NUM_MBUFS_PER_PORT ((MAX_QUEUES * RTE_TEST_RX_DESC_DEFAULT) +\\\n\t\t\t\t(nb_switching_cores * MAX_PKT_BURST) +\\\n\t\t\t\t(nb_switching_cores * \\\n\t\t\t\tRTE_TEST_TX_DESC_DEFAULT) +\\\n\t\t\t\t(nb_switching_cores * MBUF_CACHE_SIZE))\n\n#define MBUF_CACHE_SIZE 128\n#define MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)\n\n#define MAX_PKT_BURST 32\t/* Max burst size for RX/TX */\n#define BURST_TX_DRAIN_US 100\t/* TX drain every ~100us */\n\n/* Defines how long we wait between retries on RX */\n#define BURST_RX_WAIT_US 15\n\n#define BURST_RX_RETRIES 4\t/* Number of retries on RX. */\n\n#define JUMBO_FRAME_MAX_SIZE 0x2600\n\n/* State of virtio device. */\n#define DEVICE_MAC_LEARNING 0\n#define DEVICE_RX\t 1\n#define DEVICE_SAFE_REMOVE 2\n\n/* Config_core_flag status definitions. */\n#define REQUEST_DEV_REMOVAL 1\n#define ACK_DEV_REMOVAL 0\n\n/* Configurable number of RX/TX ring descriptors */\n#define RTE_TEST_RX_DESC_DEFAULT 1024\n#define RTE_TEST_TX_DESC_DEFAULT 512\n\n/* Get first 4 bytes in mbuf headroom. */\n#define MBUF_HEADROOM_UINT32(mbuf) (*(uint32_t *)((uint8_t *)(mbuf) \\\n\t\t+ sizeof(struct rte_mbuf)))\n\n#define INVALID_PORT_ID 0xFF\n\n/* Size of buffers used for snprintfs. */\n#define MAX_PRINT_BUFF 6072\n\n/* Maximum character device basename size. */\n#define MAX_BASENAME_SZ 20\n\n/* Maximum long option length for option parsing. */\n#define MAX_LONG_OPT_SZ 64\n\n/* Used to compare MAC addresses. */\n#define MAC_ADDR_CMP 0xFFFFFFFFFFFFULL\n\n#define CMD_LINE_OPT_NB_DEVICES \"nb-devices\"\n#define CMD_LINE_OPT_UDP_PORT \"udp-port\"\n#define CMD_LINE_OPT_TX_CHECKSUM \"tx-checksum\"\n#define CMD_LINE_OPT_TSO_SEGSZ \"tso-segsz\"\n#define CMD_LINE_OPT_FILTER_TYPE \"filter-type\"\n#define CMD_LINE_OPT_ENCAP \"encap\"\n#define CMD_LINE_OPT_DECAP \"decap\"\n#define CMD_LINE_OPT_RX_RETRY \"rx-retry\"\n#define CMD_LINE_OPT_RX_RETRY_DELAY \"rx-retry-delay\"\n#define CMD_LINE_OPT_RX_RETRY_NUM \"rx-retry-num\"\n#define CMD_LINE_OPT_STATS \"stats\"\n#define CMD_LINE_OPT_DEV_BASENAME \"dev-basename\"\n\n/* mask of enabled ports */\nstatic uint32_t enabled_port_mask;\n\n/*Number of switching cores enabled*/\nstatic uint32_t nb_switching_cores;\n\n/* number of devices/queues to support*/\nuint16_t nb_devices = 2;\n\n/* max ring descriptor, ixgbe, i40e, e1000 all are 4096. */\n#define MAX_RING_DESC 4096\n\nstruct vpool {\n\tstruct rte_mempool *pool;\n\tstruct rte_ring *ring;\n\tuint32_t buf_size;\n} vpool_array[MAX_QUEUES+MAX_QUEUES];\n\n/* UDP tunneling port */\nuint16_t udp_port = 4789;\n\n/* enable/disable inner TX checksum */\nuint8_t tx_checksum = 0;\n\n/* TCP segment size */\nuint16_t tso_segsz = 0;\n\n/* enable/disable decapsulation */\nuint8_t rx_decap = 1;\n\n/* enable/disable encapsulation */\nuint8_t tx_encap = 1;\n\n/* RX filter type for tunneling packet */\nuint8_t filter_idx = 1;\n\n/* overlay packet operation */\nstruct ol_switch_ops overlay_options = {\n\t.port_configure = vxlan_port_init,\n\t.tunnel_setup = vxlan_link,\n\t.tunnel_destroy = vxlan_unlink,\n\t.tx_handle = vxlan_tx_pkts,\n\t.rx_handle = vxlan_rx_pkts,\n\t.param_handle = NULL,\n};\n\n/* Enable stats. */\nuint32_t enable_stats = 0;\n/* Enable retries on RX. */\nstatic uint32_t enable_retry = 1;\n/* Specify timeout (in useconds) between retries on RX. */\nstatic uint32_t burst_rx_delay_time = BURST_RX_WAIT_US;\n/* Specify the number of retries on RX. */\nstatic uint32_t burst_rx_retry_num = BURST_RX_RETRIES;\n\n/* Character device basename. Can be set by user. */\nstatic char dev_basename[MAX_BASENAME_SZ] = \"vhost-net\";\n\nstatic unsigned lcore_ids[RTE_MAX_LCORE];\nuint8_t ports[RTE_MAX_ETHPORTS];\n\nstatic unsigned nb_ports; /**< The number of ports specified in command line */\n\n/* ethernet addresses of ports */\nstruct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];\n\n/* heads for the main used and free linked lists for the data path. */\nstatic struct virtio_net_data_ll *ll_root_used;\nstatic struct virtio_net_data_ll *ll_root_free;\n\n/**\n * Array of data core structures containing information on\n * individual core linked lists.\n */\nstatic struct lcore_info lcore_info[RTE_MAX_LCORE];\n\n/* Used for queueing bursts of TX packets. */\nstruct mbuf_table {\n\tunsigned len;\n\tunsigned txq_id;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST];\n};\n\n/* TX queue for each data core. */\nstruct mbuf_table lcore_tx_queue[RTE_MAX_LCORE];\n\nstruct device_statistics dev_statistics[MAX_DEVICES];\n\n/**\n * Set character device basename.\n */\nstatic int\nus_vhost_parse_basename(const char *q_arg)\n{\n\t/* parse number string */\n\tif (strlen(q_arg) >= MAX_BASENAME_SZ)\n\t\treturn -1;\n\telse\n\t\tsnprintf((char *)&dev_basename, MAX_BASENAME_SZ, \"%s\", q_arg);\n\n\treturn 0;\n}\n\n/**\n * Parse the portmask provided at run time.\n */\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\n/**\n * Parse num options at run time.\n */\nstatic int\nparse_num_opt(const char *q_arg, uint32_t max_valid_value)\n{\n\tchar *end = NULL;\n\tunsigned long num;\n\n\t/* parse unsigned int string */\n\tnum = strtoul(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (num > max_valid_value)\n\t\treturn -1;\n\n\treturn num;\n}\n\n/**\n * Display usage\n */\nstatic void\ntep_termination_usage(const char *prgname)\n{\n\tRTE_LOG(INFO, VHOST_CONFIG, \"%s [EAL options] -- -p PORTMASK\\n\"\n\t\" --udp-port: UDP destination port for VXLAN packet\\n\"\n\t\"\t\t--nb-devices[1-64]: The number of virtIO device\\n\"\n\t\" --tx-checksum [0|1]: inner Tx checksum offload\\n\"\n\t\" --tso-segsz [0-N]: TCP segment size\\n\"\n\t\" --decap [0|1]: tunneling packet decapsulation\\n\"\n\t\" --encap [0|1]: tunneling packet encapsulation\\n\"\n\t\" --filter-type[1-3]: filter type for tunneling packet\\n\"\n\t\" 1: Inner MAC and tenent ID\\n\"\n\t\" 2: Inner MAC and VLAN, and tenent ID\\n\"\n\t\" 3: Outer MAC, Inner MAC and tenent ID\\n\"\n\t\"\t\t-p PORTMASK: Set mask for ports to be used by application\\n\"\n\t\"\t\t--rx-retry [0|1]: disable/enable(default) retries on rx.\"\n\t\"\t\t Enable retry if destintation queue is full\\n\"\n\t\"\t\t--rx-retry-delay [0-N]: timeout(in usecond) between retries on RX.\"\n\t\"\t\t This makes effect only if retries on rx enabled\\n\"\n\t\"\t\t--rx-retry-num [0-N]: the number of retries on rx.\"\n\t\"\t\t This makes effect only if retries on rx enabled\\n\"\n\t\"\t\t--stats [0-N]: 0: Disable stats, N: Time in seconds to print stats\\n\"\n\t\"\t\t--dev-basename: The basename to be used for the character device.\\n\",\n\t prgname);\n}\n\n/**\n * Parse the arguments given in the command line of the application.\n */\nstatic int\ntep_termination_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tint option_index;\n\tunsigned i;\n\tconst char *prgname = argv[0];\n\tstatic struct option long_option[] = {\n\t\t{CMD_LINE_OPT_NB_DEVICES, required_argument, NULL, 0},\n\t\t{CMD_LINE_OPT_UDP_PORT, required_argument, NULL, 0},\n\t\t{CMD_LINE_OPT_TX_CHECKSUM, required_argument, NULL, 0},\n\t\t{CMD_LINE_OPT_TSO_SEGSZ, required_argument, NULL, 0},\n\t\t{CMD_LINE_OPT_DECAP, required_argument, NULL, 0},\n\t\t{CMD_LINE_OPT_ENCAP, required_argument, NULL, 0},\n\t\t{CMD_LINE_OPT_FILTER_TYPE, required_argument, NULL, 0},\n\t\t{CMD_LINE_OPT_RX_RETRY, required_argument, NULL, 0},\n\t\t{CMD_LINE_OPT_RX_RETRY_DELAY, required_argument, NULL, 0},\n\t\t{CMD_LINE_OPT_RX_RETRY_NUM, required_argument, NULL, 0},\n\t\t{CMD_LINE_OPT_STATS, required_argument, NULL, 0},\n\t\t{CMD_LINE_OPT_DEV_BASENAME, required_argument, NULL, 0},\n\t\t{NULL, 0, 0, 0},\n\t};\n\n\t/* Parse command line */\n\twhile ((opt = getopt_long(argc, argv, \"p:\",\n\t\t\tlong_option, &option_index)) != EOF) {\n\t\tswitch (opt) {\n\t\t/* Portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\"Invalid portmask\\n\");\n\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 0:\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\tCMD_LINE_OPT_NB_DEVICES,\n\t\t\t\tsizeof(CMD_LINE_OPT_NB_DEVICES))) {\n\t\t\t\tret = parse_num_opt(optarg, MAX_DEVICES);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\"Invalid argument for nb-devices [0-%d]\\n\",\n\t\t\t\t\tMAX_DEVICES);\n\t\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else\n\t\t\t\t\tnb_devices = ret;\n\t\t\t}\n\n\t\t\t/* Enable/disable retries on RX. */\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\tCMD_LINE_OPT_RX_RETRY,\n\t\t\t\tsizeof(CMD_LINE_OPT_RX_RETRY))) {\n\t\t\t\tret = parse_num_opt(optarg, 1);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument for rx-retry [0|1]\\n\");\n\t\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else\n\t\t\t\t\tenable_retry = ret;\n\t\t\t}\n\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\tCMD_LINE_OPT_TSO_SEGSZ,\n\t\t\t\tsizeof(CMD_LINE_OPT_TSO_SEGSZ))) {\n\t\t\t\tret = parse_num_opt(optarg, INT16_MAX);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument for TCP segment size [0-N]\\n\");\n\t\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else\n\t\t\t\t\ttso_segsz = ret;\n\t\t\t}\n\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\t\tCMD_LINE_OPT_UDP_PORT,\n\t\t\t\t\tsizeof(CMD_LINE_OPT_UDP_PORT))) {\n\t\t\t\tret = parse_num_opt(optarg, INT16_MAX);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument for UDP port [0-N]\\n\");\n\t\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else\n\t\t\t\t\tudp_port = ret;\n\t\t\t}\n\n\t\t\t/* Specify the retries delay time (in useconds) on RX.*/\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\tCMD_LINE_OPT_RX_RETRY_DELAY,\n\t\t\t\tsizeof(CMD_LINE_OPT_RX_RETRY_DELAY))) {\n\t\t\t\tret = parse_num_opt(optarg, INT32_MAX);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument for rx-retry-delay [0-N]\\n\");\n\t\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else\n\t\t\t\t\tburst_rx_delay_time = ret;\n\t\t\t}\n\n\t\t\t/* Specify the retries number on RX. */\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\tCMD_LINE_OPT_RX_RETRY_NUM,\n\t\t\t\tsizeof(CMD_LINE_OPT_RX_RETRY_NUM))) {\n\t\t\t\tret = parse_num_opt(optarg, INT32_MAX);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument for rx-retry-num [0-N]\\n\");\n\t\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else\n\t\t\t\t\tburst_rx_retry_num = ret;\n\t\t\t}\n\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\tCMD_LINE_OPT_TX_CHECKSUM,\n\t\t\t\tsizeof(CMD_LINE_OPT_TX_CHECKSUM))) {\n\t\t\t\tret = parse_num_opt(optarg, 1);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument for tx-checksum [0|1]\\n\");\n\t\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else\n\t\t\t\t\ttx_checksum = ret;\n\t\t\t}\n\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\t\tCMD_LINE_OPT_FILTER_TYPE,\n\t\t\t\t\tsizeof(CMD_LINE_OPT_FILTER_TYPE))) {\n\t\t\t\tret = parse_num_opt(optarg, 3);\n\t\t\t\tif ((ret == -1) || (ret == 0)) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument for filter type [1-3]\\n\");\n\t\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else\n\t\t\t\t\tfilter_idx = ret - 1;\n\t\t\t}\n\n\t\t\t/* Enable/disable encapsulation on RX. */\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\tCMD_LINE_OPT_DECAP,\n\t\t\t\tsizeof(CMD_LINE_OPT_DECAP))) {\n\t\t\t\tret = parse_num_opt(optarg, 1);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument for decap [0|1]\\n\");\n\t\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else\n\t\t\t\t\trx_decap = ret;\n\t\t\t}\n\n\t\t\t/* Enable/disable encapsulation on TX. */\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\tCMD_LINE_OPT_ENCAP,\n\t\t\t\tsizeof(CMD_LINE_OPT_ENCAP))) {\n\t\t\t\tret = parse_num_opt(optarg, 1);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument for encap [0|1]\\n\");\n\t\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else\n\t\t\t\t\ttx_encap = ret;\n\t\t\t}\n\n\t\t\t/* Enable/disable stats. */\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\tCMD_LINE_OPT_STATS,\n\t\t\t\tsizeof(CMD_LINE_OPT_STATS))) {\n\t\t\t\tret = parse_num_opt(optarg, INT32_MAX);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\t\"Invalid argument for stats [0..N]\\n\");\n\t\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else\n\t\t\t\t\tenable_stats = ret;\n\t\t\t}\n\n\t\t\t/* Set character device basename. */\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\tCMD_LINE_OPT_DEV_BASENAME,\n\t\t\t\tsizeof(CMD_LINE_OPT_DEV_BASENAME))) {\n\t\t\t\tif (us_vhost_parse_basename(optarg) == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument for character \"\n\t\t\t\t\t\t\"device basename (Max %d characters)\\n\",\n\t\t\t\t\t\tMAX_BASENAME_SZ);\n\t\t\t\t\ttep_termination_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tbreak;\n\n\t\t\t/* Invalid option - print options. */\n\t\tdefault:\n\t\t\ttep_termination_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif (enabled_port_mask & (1 << i))\n\t\t\tports[nb_ports++] = (uint8_t)i;\n\t}\n\n\tif ((nb_ports == 0) || (nb_ports > MAX_SUP_PORTS)) {\n\t\tRTE_LOG(INFO, VHOST_PORT, \"Current enabled port number is %u,\"\n\t\t\t\"but only %u port can be enabled\\n\", nb_ports,\n\t\t\tMAX_SUP_PORTS);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/**\n * Update the global var NB_PORTS and array PORTS\n * according to system ports number and return valid ports number\n */\nstatic unsigned\ncheck_ports_num(unsigned max_nb_ports)\n{\n\tunsigned valid_nb_ports = nb_ports;\n\tunsigned portid;\n\n\tif (nb_ports > max_nb_ports) {\n\t\tRTE_LOG(INFO, VHOST_PORT, \"\\nSpecified port number(%u) \"\n\t\t\t\" exceeds total system port number(%u)\\n\",\n\t\t\tnb_ports, max_nb_ports);\n\t\tnb_ports = max_nb_ports;\n\t}\n\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\tif (ports[portid] >= max_nb_ports) {\n\t\t\tRTE_LOG(INFO, VHOST_PORT,\n\t\t\t\t\"\\nSpecified port ID(%u) exceeds max \"\n\t\t\t\t\" system port ID(%u)\\n\",\n\t\t\t\tports[portid], (max_nb_ports - 1));\n\t\t\tports[portid] = INVALID_PORT_ID;\n\t\t\tvalid_nb_ports--;\n\t\t}\n\t}\n\treturn valid_nb_ports;\n}\n\n/**\n * This function routes the TX packet to the correct interface. This may be a local device\n * or the physical port.\n */\nstatic inline void __attribute__((always_inline))\nvirtio_tx_route(struct vhost_dev *vdev, struct rte_mbuf *m)\n{\n\tstruct mbuf_table *tx_q;\n\tstruct rte_mbuf **m_table;\n\tunsigned len, ret = 0;\n\tconst uint16_t lcore_id = rte_lcore_id();\n\tstruct virtio_net *dev = vdev->dev;\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") TX: MAC address is external\\n\",\n\t\tdev->device_fh);\n\n\t/* Add packet to the port tx queue */\n\ttx_q = &lcore_tx_queue[lcore_id];\n\tlen = tx_q->len;\n\n\ttx_q->m_table[len] = m;\n\tlen++;\n\tif (enable_stats) {\n\t\tdev_statistics[dev->device_fh].tx_total++;\n\t\tdev_statistics[dev->device_fh].tx++;\n\t}\n\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tm_table = (struct rte_mbuf **)tx_q->m_table;\n\t\tret = overlay_options.tx_handle(ports[0],\n\t\t\t(uint16_t)tx_q->txq_id, m_table,\n\t\t\t(uint16_t)tx_q->len);\n\n\t\t/* Free any buffers not handled by TX and update\n\t\t * the port stats.\n\t\t */\n\t\tif (unlikely(ret < len)) {\n\t\t\tdo {\n\t\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t\t} while (++ret < len);\n\t\t}\n\n\t\tlen = 0;\n\t}\n\n\ttx_q->len = len;\n\treturn;\n}\n\n/**\n * This function is called by each data core. It handles all\n * RX/TX registered with the core. For TX the specific lcore\n * linked list is used. For RX, MAC addresses are compared\n * with all devices in the main linked list.\n */\nstatic int\nswitch_worker(__rte_unused void *arg)\n{\n\tstruct rte_mempool *mbuf_pool = arg;\n\tstruct virtio_net *dev = NULL;\n\tstruct vhost_dev *vdev = NULL;\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct virtio_net_data_ll *dev_ll;\n\tstruct mbuf_table *tx_q;\n\tvolatile struct lcore_ll_info *lcore_ll;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1)\n\t\t\t\t\t/ US_PER_S * BURST_TX_DRAIN_US;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc, ret_count = 0;\n\tunsigned i, ret = 0;\n\tconst uint16_t lcore_id = rte_lcore_id();\n\tconst uint16_t num_cores = (uint16_t)rte_lcore_count();\n\tuint16_t rx_count = 0;\n\tuint16_t tx_count;\n\tuint32_t retry = 0;\n\n\tRTE_LOG(INFO, VHOST_DATA, \"Procesing on Core %u started\\n\", lcore_id);\n\tlcore_ll = lcore_info[lcore_id].lcore_ll;\n\tprev_tsc = 0;\n\n\ttx_q = &lcore_tx_queue[lcore_id];\n\tfor (i = 0; i < num_cores; i++) {\n\t\tif (lcore_ids[i] == lcore_id) {\n\t\t\ttx_q->txq_id = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\twhile (1) {\n\t\tcur_tsc = rte_rdtsc();\n\t\t/*\n\t\t * TX burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\tif (tx_q->len) {\n\t\t\t\tLOG_DEBUG(VHOST_DATA, \"TX queue drained after \"\n\t\t\t\t\t\"timeout with burst size %u\\n\",\n\t\t\t\t\ttx_q->len);\n\t\t\t\tret = overlay_options.tx_handle(ports[0],\n\t\t\t\t\t(uint16_t)tx_q->txq_id,\n\t\t\t\t\t(struct rte_mbuf **)tx_q->m_table,\n\t\t\t\t\t(uint16_t)tx_q->len);\n\t\t\t\tif (unlikely(ret < tx_q->len)) {\n\t\t\t\t\tdo {\n\t\t\t\t\t\trte_pktmbuf_free(tx_q->m_table[ret]);\n\t\t\t\t\t} while (++ret < tx_q->len);\n\t\t\t\t}\n\n\t\t\t\ttx_q->len = 0;\n\t\t\t}\n\n\t\t\tprev_tsc = cur_tsc;\n\n\t\t}\n\n\t\trte_prefetch0(lcore_ll->ll_root_used);\n\n\t\t/**\n\t\t * Inform the configuration core that we have exited\n\t\t * the linked list and that no devices are\n\t\t * in use if requested.\n\t\t */\n\t\tif (lcore_ll->dev_removal_flag == REQUEST_DEV_REMOVAL)\n\t\t\tlcore_ll->dev_removal_flag = ACK_DEV_REMOVAL;\n\n\t\t/*\n\t\t * Process devices\n\t\t */\n\t\tdev_ll = lcore_ll->ll_root_used;\n\n\t\twhile (dev_ll != NULL) {\n\t\t\tvdev = dev_ll->vdev;\n\t\t\tdev = vdev->dev;\n\n\t\t\tif (unlikely(vdev->remove)) {\n\t\t\t\tdev_ll = dev_ll->next;\n\t\t\t\toverlay_options.tunnel_destroy(vdev);\n\t\t\t\tvdev->ready = DEVICE_SAFE_REMOVE;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (likely(vdev->ready == DEVICE_RX)) {\n\t\t\t\t/* Handle guest RX */\n\t\t\t\trx_count = rte_eth_rx_burst(ports[0],\n\t\t\t\t\tvdev->rx_q, pkts_burst, MAX_PKT_BURST);\n\n\t\t\t\tif (rx_count) {\n\t\t\t\t\t/*\n\t\t\t\t\t* Retry is enabled and the queue is\n\t\t\t\t\t* full then we wait and retry to\n\t\t\t\t\t* avoid packet loss. Here MAX_PKT_BURST\n\t\t\t\t\t* must be less than virtio queue size\n\t\t\t\t\t*/\n\t\t\t\t\tif (enable_retry && unlikely(rx_count >\n\t\t\t\t\t\trte_vring_available_entries(dev, VIRTIO_RXQ))) {\n\t\t\t\t\t\tfor (retry = 0; retry < burst_rx_retry_num;\n\t\t\t\t\t\t\tretry++) {\n\t\t\t\t\t\t\trte_delay_us(burst_rx_delay_time);\n\t\t\t\t\t\t\tif (rx_count <= rte_vring_available_entries(dev, VIRTIO_RXQ))\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\n\t\t\t\t\tret_count = overlay_options.rx_handle(dev, pkts_burst, rx_count);\n\t\t\t\t\tif (enable_stats) {\n\t\t\t\t\t\trte_atomic64_add(\n\t\t\t\t\t\t&dev_statistics[dev->device_fh].rx_total_atomic,\n\t\t\t\t\t\trx_count);\n\t\t\t\t\t\trte_atomic64_add(\n\t\t\t\t\t\t&dev_statistics[dev->device_fh].rx_atomic, ret_count);\n\t\t\t\t\t}\n\t\t\t\t\twhile (likely(rx_count)) {\n\t\t\t\t\t\trx_count--;\n\t\t\t\t\t\trte_pktmbuf_free(pkts_burst[rx_count]);\n\t\t\t\t\t}\n\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (likely(!vdev->remove)) {\n\t\t\t\t/* Handle guest TX*/\n\t\t\t\ttx_count = rte_vhost_dequeue_burst(dev,\n\t\t\t\t\t\tVIRTIO_TXQ, mbuf_pool,\n\t\t\t\t\t\tpkts_burst, MAX_PKT_BURST);\n\t\t\t\t/* If this is the first received packet we need to learn the MAC */\n\t\t\t\tif (unlikely(vdev->ready == DEVICE_MAC_LEARNING) && tx_count) {\n\t\t\t\t\tif (vdev->remove ||\n\t\t\t\t\t\t(overlay_options.tunnel_setup(vdev, pkts_burst[0]) == -1)) {\n\t\t\t\t\t\twhile (tx_count)\n\t\t\t\t\t\t\trte_pktmbuf_free(pkts_burst[--tx_count]);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\twhile (tx_count)\n\t\t\t\t\tvirtio_tx_route(vdev, pkts_burst[--tx_count]);\n\t\t\t}\n\n\t\t\t/* move to the next device in the list */\n\t\t\tdev_ll = dev_ll->next;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/**\n * Add an entry to a used linked list. A free entry must first be found\n * in the free linked list using get_data_ll_free_entry();\n */\nstatic void\nadd_data_ll_entry(struct virtio_net_data_ll **ll_root_addr,\n\tstruct virtio_net_data_ll *ll_dev)\n{\n\tstruct virtio_net_data_ll *ll = *ll_root_addr;\n\n\t/* Set next as NULL and use a compiler barrier to avoid reordering. */\n\tll_dev->next = NULL;\n\trte_compiler_barrier();\n\n\t/* If ll == NULL then this is the first device. */\n\tif (ll) {\n\t\t/* Increment to the tail of the linked list. */\n\t\twhile (ll->next != NULL)\n\t\t\tll = ll->next;\n\n\t\tll->next = ll_dev;\n\t} else {\n\t\t*ll_root_addr = ll_dev;\n\t}\n}\n\n/**\n * Remove an entry from a used linked list. The entry must then be added to\n * the free linked list using put_data_ll_free_entry().\n */\nstatic void\nrm_data_ll_entry(struct virtio_net_data_ll **ll_root_addr,\n\tstruct virtio_net_data_ll *ll_dev,\n\tstruct virtio_net_data_ll *ll_dev_last)\n{\n\tstruct virtio_net_data_ll *ll = *ll_root_addr;\n\n\tif (unlikely((ll == NULL) || (ll_dev == NULL)))\n\t\treturn;\n\n\tif (ll_dev == ll)\n\t\t*ll_root_addr = ll_dev->next;\n\telse\n\t\tif (likely(ll_dev_last != NULL))\n\t\t\tll_dev_last->next = ll_dev->next;\n\t\telse\n\t\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\t\"Remove entry form ll failed.\\n\");\n}\n\n/**\n * Find and return an entry from the free linked list.\n */\nstatic struct virtio_net_data_ll *\nget_data_ll_free_entry(struct virtio_net_data_ll **ll_root_addr)\n{\n\tstruct virtio_net_data_ll *ll_free = *ll_root_addr;\n\tstruct virtio_net_data_ll *ll_dev;\n\n\tif (ll_free == NULL)\n\t\treturn NULL;\n\n\tll_dev = ll_free;\n\t*ll_root_addr = ll_free->next;\n\n\treturn ll_dev;\n}\n\n/**\n * Place an entry back on to the free linked list.\n */\nstatic void\nput_data_ll_free_entry(struct virtio_net_data_ll **ll_root_addr,\n\tstruct virtio_net_data_ll *ll_dev)\n{\n\tstruct virtio_net_data_ll *ll_free = *ll_root_addr;\n\n\tif (ll_dev == NULL)\n\t\treturn;\n\n\tll_dev->next = ll_free;\n\t*ll_root_addr = ll_dev;\n}\n\n/**\n * Creates a linked list of a given size.\n */\nstatic struct virtio_net_data_ll *\nalloc_data_ll(uint32_t size)\n{\n\tstruct virtio_net_data_ll *ll_new;\n\tuint32_t i;\n\n\t/* Malloc and then chain the linked list. */\n\tll_new = malloc(size * sizeof(struct virtio_net_data_ll));\n\tif (ll_new == NULL) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"Failed to allocate memory for ll_new.\\n\");\n\t\treturn NULL;\n\t}\n\n\tfor (i = 0; i < size - 1; i++) {\n\t\tll_new[i].vdev = NULL;\n\t\tll_new[i].next = &ll_new[i+1];\n\t}\n\tll_new[i].next = NULL;\n\n\treturn ll_new;\n}\n\n/**\n * Create the main linked list along with each individual cores\n * linked list. A used and a free list are created to manage entries.\n */\nstatic int\ninit_data_ll(void)\n{\n\tint lcore;\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\tlcore_info[lcore].lcore_ll =\n\t\t\tmalloc(sizeof(struct lcore_ll_info));\n\t\tif (lcore_info[lcore].lcore_ll == NULL) {\n\t\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\t\"Failed to allocate memory for lcore_ll.\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tlcore_info[lcore].lcore_ll->device_num = 0;\n\t\tlcore_info[lcore].lcore_ll->dev_removal_flag = ACK_DEV_REMOVAL;\n\t\tlcore_info[lcore].lcore_ll->ll_root_used = NULL;\n\t\tif (nb_devices % nb_switching_cores)\n\t\t\tlcore_info[lcore].lcore_ll->ll_root_free =\n\t\t\t\talloc_data_ll((nb_devices / nb_switching_cores)\n\t\t\t\t\t\t+ 1);\n\t\telse\n\t\t\tlcore_info[lcore].lcore_ll->ll_root_free =\n\t\t\t\talloc_data_ll(nb_devices / nb_switching_cores);\n\t}\n\n\t/* Allocate devices up to a maximum of MAX_DEVICES. */\n\tll_root_free = alloc_data_ll(MIN((nb_devices), MAX_DEVICES));\n\n\treturn 0;\n}\n\n/**\n * Remove a device from the specific data core linked list and\n * from the main linked list. Synchonization occurs through the use\n * of the lcore dev_removal_flag. Device is made volatile here\n * to avoid re-ordering of dev->remove=1 which can cause an infinite\n * loop in the rte_pause loop.\n */\nstatic void\ndestroy_device(volatile struct virtio_net *dev)\n{\n\tstruct virtio_net_data_ll *ll_lcore_dev_cur;\n\tstruct virtio_net_data_ll *ll_main_dev_cur;\n\tstruct virtio_net_data_ll *ll_lcore_dev_last = NULL;\n\tstruct virtio_net_data_ll *ll_main_dev_last = NULL;\n\tstruct vhost_dev *vdev;\n\tint lcore;\n\n\tdev->flags &= ~VIRTIO_DEV_RUNNING;\n\n\tvdev = (struct vhost_dev *)dev->priv;\n\n\t/* set the remove flag. */\n\tvdev->remove = 1;\n\twhile (vdev->ready != DEVICE_SAFE_REMOVE)\n\t\trte_pause();\n\n\t/* Search for entry to be removed from lcore ll */\n\tll_lcore_dev_cur = lcore_info[vdev->coreid].lcore_ll->ll_root_used;\n\twhile (ll_lcore_dev_cur != NULL) {\n\t\tif (ll_lcore_dev_cur->vdev == vdev) {\n\t\t\tbreak;\n\t\t} else {\n\t\t\tll_lcore_dev_last = ll_lcore_dev_cur;\n\t\t\tll_lcore_dev_cur = ll_lcore_dev_cur->next;\n\t\t}\n\t}\n\n\tif (ll_lcore_dev_cur == NULL) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") Failed to find the dev to be destroy.\\n\",\n\t\t\tdev->device_fh);\n\t\treturn;\n\t}\n\n\t/* Search for entry to be removed from main ll */\n\tll_main_dev_cur = ll_root_used;\n\tll_main_dev_last = NULL;\n\twhile (ll_main_dev_cur != NULL) {\n\t\tif (ll_main_dev_cur->vdev == vdev) {\n\t\t\tbreak;\n\t\t} else {\n\t\t\tll_main_dev_last = ll_main_dev_cur;\n\t\t\tll_main_dev_cur = ll_main_dev_cur->next;\n\t\t}\n\t}\n\n\t/* Remove entries from the lcore and main ll. */\n\trm_data_ll_entry(&lcore_info[vdev->coreid].lcore_ll->ll_root_used,\n\t\t\tll_lcore_dev_cur, ll_lcore_dev_last);\n\trm_data_ll_entry(&ll_root_used, ll_main_dev_cur, ll_main_dev_last);\n\n\t/* Set the dev_removal_flag on each lcore. */\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\tlcore_info[lcore].lcore_ll->dev_removal_flag =\n\t\t\tREQUEST_DEV_REMOVAL;\n\t}\n\n\t/*\n\t * Once each core has set the dev_removal_flag to\n\t * ACK_DEV_REMOVAL we can be sure that they can no longer access\n\t * the device removed from the linked lists and that the devices\n\t * are no longer in use.\n\t */\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\twhile (lcore_info[lcore].lcore_ll->dev_removal_flag\n\t\t\t!= ACK_DEV_REMOVAL)\n\t\t\trte_pause();\n\t}\n\n\t/* Add the entries back to the lcore and main free ll.*/\n\tput_data_ll_free_entry(&lcore_info[vdev->coreid].lcore_ll->ll_root_free,\n\t\t\t\tll_lcore_dev_cur);\n\tput_data_ll_free_entry(&ll_root_free, ll_main_dev_cur);\n\n\t/* Decrement number of device on the lcore. */\n\tlcore_info[vdev->coreid].lcore_ll->device_num--;\n\n\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") Device has been removed \"\n\t\t\"from data core\\n\", dev->device_fh);\n\n\trte_free(vdev);\n\n}\n\n/**\n * A new device is added to a data core. First the device is added\n * to the main linked list and the allocated to a specific data core.\n */\nstatic int\nnew_device(struct virtio_net *dev)\n{\n\tstruct virtio_net_data_ll *ll_dev;\n\tint lcore, core_add = 0;\n\tuint32_t device_num_min = nb_devices;\n\tstruct vhost_dev *vdev;\n\n\tvdev = rte_zmalloc(\"vhost device\", sizeof(*vdev), RTE_CACHE_LINE_SIZE);\n\tif (vdev == NULL) {\n\t\tRTE_LOG(INFO, VHOST_DATA,\n\t\t\t\"(%\"PRIu64\") Couldn't allocate memory for vhost dev\\n\",\n\t\t\tdev->device_fh);\n\t\treturn -1;\n\t}\n\tvdev->dev = dev;\n\tdev->priv = vdev;\n\t/* Add device to main ll */\n\tll_dev = get_data_ll_free_entry(&ll_root_free);\n\tif (ll_dev == NULL) {\n\t\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") No free entry found in\"\n\t\t\t\" linked list Device limit of %d devices per core\"\n\t\t\t\" has been reached\\n\", dev->device_fh, nb_devices);\n\t\tif (vdev->regions_hpa)\n\t\t\trte_free(vdev->regions_hpa);\n\t\trte_free(vdev);\n\t\treturn -1;\n\t}\n\tll_dev->vdev = vdev;\n\tadd_data_ll_entry(&ll_root_used, ll_dev);\n\tvdev->rx_q = dev->device_fh;\n\n\t/* reset ready flag */\n\tvdev->ready = DEVICE_MAC_LEARNING;\n\tvdev->remove = 0;\n\n\t/* Find a suitable lcore to add the device. */\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\tif (lcore_info[lcore].lcore_ll->device_num < device_num_min) {\n\t\t\tdevice_num_min = lcore_info[lcore].lcore_ll->device_num;\n\t\t\tcore_add = lcore;\n\t\t}\n\t}\n\t/* Add device to lcore ll */\n\tll_dev = get_data_ll_free_entry(&lcore_info[core_add].lcore_ll->ll_root_free);\n\tif (ll_dev == NULL) {\n\t\tRTE_LOG(INFO, VHOST_DATA,\n\t\t\t\"(%\"PRIu64\") Failed to add device to data core\\n\",\n\t\t\tdev->device_fh);\n\t\tvdev->ready = DEVICE_SAFE_REMOVE;\n\t\tdestroy_device(dev);\n\t\trte_free(vdev->regions_hpa);\n\t\trte_free(vdev);\n\t\treturn -1;\n\t}\n\tll_dev->vdev = vdev;\n\tvdev->coreid = core_add;\n\n\tadd_data_ll_entry(&lcore_info[vdev->coreid].lcore_ll->ll_root_used,\n\t\t\tll_dev);\n\n\t/* Initialize device stats */\n\tmemset(&dev_statistics[dev->device_fh], 0,\n\t\tsizeof(struct device_statistics));\n\n\t/* Disable notifications. */\n\trte_vhost_enable_guest_notification(dev, VIRTIO_RXQ, 0);\n\trte_vhost_enable_guest_notification(dev, VIRTIO_TXQ, 0);\n\tlcore_info[vdev->coreid].lcore_ll->device_num++;\n\tdev->flags |= VIRTIO_DEV_RUNNING;\n\n\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") Device has been added to data core %d\\n\",\n\t\tdev->device_fh, vdev->coreid);\n\n\treturn 0;\n}\n\n/**\n * These callback allow devices to be added to the data core when configuration\n * has been fully complete.\n */\nstatic const struct virtio_net_device_ops virtio_net_device_ops = {\n\t.new_device = new_device,\n\t.destroy_device = destroy_device,\n};\n\n/**\n * This is a thread will wake up after a period to print stats if the user has\n * enabled them.\n */\nstatic void\nprint_stats(void)\n{\n\tstruct virtio_net_data_ll *dev_ll;\n\tuint64_t tx_dropped, rx_dropped;\n\tuint64_t tx, tx_total, rx, rx_total, rx_ip_csum, rx_l4_csum;\n\tuint32_t device_fh;\n\tconst char clr[] = { 27, '[', '2', 'J', '\\0' };\n\tconst char top_left[] = { 27, '[', '1', ';', '1', 'H', '\\0' };\n\n\twhile (1) {\n\t\tsleep(enable_stats);\n\n\t\t/* Clear screen and move to top left */\n\t\tprintf(\"%s%s\", clr, top_left);\n\n\t\tprintf(\"\\nDevice statistics ================================\");\n\n\t\tdev_ll = ll_root_used;\n\t\twhile (dev_ll != NULL) {\n\t\t\tdevice_fh = (uint32_t)dev_ll->vdev->dev->device_fh;\n\t\t\ttx_total = dev_statistics[device_fh].tx_total;\n\t\t\ttx = dev_statistics[device_fh].tx;\n\t\t\ttx_dropped = tx_total - tx;\n\n\t\t\trx_total = rte_atomic64_read(\n\t\t\t\t&dev_statistics[device_fh].rx_total_atomic);\n\t\t\trx = rte_atomic64_read(\n\t\t\t\t&dev_statistics[device_fh].rx_atomic);\n\t\t\trx_dropped = rx_total - rx;\n\t\t\trx_ip_csum = rte_atomic64_read(\n\t\t\t\t&dev_statistics[device_fh].rx_bad_ip_csum);\n\t\t\trx_l4_csum = rte_atomic64_read(\n\t\t\t\t&dev_statistics[device_fh].rx_bad_l4_csum);\n\n\t\t\tprintf(\"\\nStatistics for device %\"PRIu32\" ----------\"\n\t\t\t\t\t\"\\nTX total:\t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nTX dropped:\t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nTX successful:\t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nRX total:\t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nRX bad IP csum: %\"PRIu64\"\"\n\t\t\t\t\t\"\\nRX bad L4 csum: %\"PRIu64\"\"\n\t\t\t\t\t\"\\nRX dropped:\t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nRX successful:\t\t%\"PRIu64\"\",\n\t\t\t\t\tdevice_fh,\n\t\t\t\t\ttx_total,\n\t\t\t\t\ttx_dropped,\n\t\t\t\t\ttx,\n\t\t\t\t\trx_total,\n\t\t\t\t\trx_ip_csum,\n\t\t\t\t\trx_l4_csum,\n\t\t\t\t\trx_dropped,\n\t\t\t\t\trx);\n\n\t\t\tdev_ll = dev_ll->next;\n\t\t}\n\t\tprintf(\"\\n================================================\\n\");\n\t}\n}\n\n/**\n * Main function, does initialisation and calls the per-lcore functions. The CUSE\n * device is also registered here to handle the IOCTLs.\n */\nint\nmain(int argc, char *argv[])\n{\n\tstruct rte_mempool *mbuf_pool = NULL;\n\tunsigned lcore_id, core_id = 0;\n\tunsigned nb_ports, valid_nb_ports;\n\tint ret;\n\tuint8_t portid;\n\tuint16_t queue_id;\n\tstatic pthread_t tid;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Error with EAL initialization\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse app arguments */\n\tret = tep_termination_parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid argument\\n\");\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++)\n\t\tif (rte_lcore_is_enabled(lcore_id))\n\t\t\tlcore_ids[core_id++] = lcore_id;\n\n\t/* set the number of swithcing cores available */\n\tnb_switching_cores = rte_lcore_count()-1;\n\n\t/* Get the number of physical ports. */\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\t/*\n\t * Update the global var NB_PORTS and global array PORTS\n\t * and get value of var VALID_NB_PORTS according to system ports number\n\t */\n\tvalid_nb_ports = check_ports_num(nb_ports);\n\n\tif ((valid_nb_ports == 0) || (valid_nb_ports > MAX_SUP_PORTS)) {\n\t\trte_exit(EXIT_FAILURE, \"Current enabled port number is %u,\"\n\t\t\t\"but only %u port can be enabled\\n\", nb_ports,\n\t\t\tMAX_SUP_PORTS);\n\t}\n\t/* Create the mbuf pool. */\n\tmbuf_pool = rte_mempool_create(\n\t\t\t\"MBUF_POOL\",\n\t\t\tNUM_MBUFS_PER_PORT\n\t\t\t* valid_nb_ports,\n\t\t\tMBUF_SIZE, MBUF_CACHE_SIZE,\n\t\t\tsizeof(struct rte_pktmbuf_pool_private),\n\t\t\trte_pktmbuf_pool_init, NULL,\n\t\t\trte_pktmbuf_init, NULL,\n\t\t\trte_socket_id(), 0);\n\tif (mbuf_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create mbuf pool\\n\");\n\n\tfor (queue_id = 0; queue_id < MAX_QUEUES + 1; queue_id++)\n\t\tvpool_array[queue_id].pool = mbuf_pool;\n\n\t/* Set log level. */\n\trte_set_log_level(LOG_LEVEL);\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tRTE_LOG(INFO, VHOST_PORT,\n\t\t\t\t\"Skipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\t\tif (overlay_options.port_configure(portid, mbuf_pool) != 0)\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"Cannot initialize network ports\\n\");\n\t}\n\n\t/* Initialise all linked lists. */\n\tif (init_data_ll() == -1)\n\t\trte_exit(EXIT_FAILURE, \"Failed to initialize linked list\\n\");\n\n\t/* Initialize device stats */\n\tmemset(&dev_statistics, 0, sizeof(dev_statistics));\n\n\t/* Enable stats if the user option is set. */\n\tif (enable_stats)\n\t\tpthread_create(&tid, NULL, (void *)print_stats, NULL);\n\n\t/* Launch all data cores. */\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\trte_eal_remote_launch(switch_worker,\n\t\t\tmbuf_pool, lcore_id);\n\t}\n\trte_vhost_feature_disable(1ULL << VIRTIO_NET_F_MRG_RXBUF);\n\n\t/* Register CUSE device to handle IOCTLs. */\n\tret = rte_vhost_driver_register((char *)&dev_basename);\n\tif (ret != 0)\n\t\trte_exit(EXIT_FAILURE, \"CUSE device setup failure.\\n\");\n\n\trte_vhost_driver_callback_register(&virtio_net_device_ops);\n\n\t/* Start CUSE session. */\n\trte_vhost_driver_session_start();\n\n\treturn 0;\n}\n" }, { "path": "examples/tep_termination/main.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _MAIN_H_\n#define _MAIN_H_\n\n#include \n\n#ifdef DEBUG\n#define LOG_LEVEL RTE_LOG_DEBUG\n#define LOG_DEBUG(log_type, fmt, args...) RTE_LOG(DEBUG, log_type, fmt, ##args)\n#else\n#define LOG_LEVEL RTE_LOG_INFO\n#define LOG_DEBUG(log_type, fmt, args...) do {} while (0)\n#endif\n\n/* Macros for printing using RTE_LOG */\n#define RTE_LOGTYPE_VHOST_CONFIG RTE_LOGTYPE_USER1\n#define RTE_LOGTYPE_VHOST_DATA RTE_LOGTYPE_USER2\n#define RTE_LOGTYPE_VHOST_PORT RTE_LOGTYPE_USER3\n\n/* State of virtio device. */\n#define DEVICE_MAC_LEARNING\t0\n#define DEVICE_RX\t\t1\n#define DEVICE_SAFE_REMOVE\t2\n\n#define MAX_QUEUES 512\n\n/* Max burst size for RX/TX */\n#define MAX_PKT_BURST 32\n\n/* Max number of devices. Limited by the application. */\n#define MAX_DEVICES 64\n\n/* Per-device statistics struct */\nstruct device_statistics {\n\tuint64_t tx_total;\n\trte_atomic64_t rx_total_atomic;\n\tuint64_t rx_total;\n\tuint64_t tx;\n\trte_atomic64_t rx_atomic;\n\t/**< Bad inner IP csum for tunneling pkt */\n\trte_atomic64_t rx_bad_ip_csum;\n\t/**< Bad inner L4 csum for tunneling pkt */\n\trte_atomic64_t rx_bad_l4_csum;\n} __rte_cache_aligned;\n\n/**\n * Device linked list structure for data path.\n */\nstruct vhost_dev {\n\t/**< Pointer to device created by vhost lib. */\n\tstruct virtio_net *dev;\n\t/**< Number of memory regions for gpa to hpa translation. */\n\tuint32_t nregions_hpa;\n\t/**< Memory region information for gpa to hpa translation. */\n\tstruct virtio_memory_regions_hpa *regions_hpa;\n\t/**< Device MAC address (Obtained on first TX packet). */\n\tstruct ether_addr mac_address;\n\t/**< RX queue number. */\n\tuint16_t rx_q;\n\t/**< Data core that the device is added to. */\n\tuint16_t coreid;\n\t/**< A device is set as ready if the MAC address has been set. */\n\tvolatile uint8_t ready;\n\t/**< Device is marked for removal from the data core. */\n\tvolatile uint8_t remove;\n} __rte_cache_aligned;\n\n/**\n * Structure containing data core specific information.\n */\nstruct lcore_ll_info {\n\t/**< Pointer to head in free linked list. */\n\tstruct virtio_net_data_ll *ll_root_free;\n\t/**< Pointer to head of used linked list. */\n\tstruct virtio_net_data_ll *ll_root_used;\n\t/**< Number of devices on lcore. */\n\tuint32_t device_num;\n\t/**< Flag to synchronize device removal. */\n\tvolatile uint8_t dev_removal_flag;\n};\n\nstruct lcore_info {\n\t/**< Pointer to data core specific lcore_ll_info struct */\n\tstruct lcore_ll_info\t*lcore_ll;\n};\n\nstruct virtio_net_data_ll {\n\t/**< Pointer to device created by configuration core. */\n\tstruct vhost_dev *vdev;\n\t/**< Pointer to next device in linked list. */\n\tstruct virtio_net_data_ll *next;\n};\n\nuint32_t\nvirtio_dev_rx(struct virtio_net *dev, struct rte_mbuf **pkts, uint32_t count);\n\n#endif /* _MAIN_H_ */\n" }, { "path": "examples/tep_termination/vxlan.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n#include \"vxlan.h\"\n\nstatic uint16_t\nget_psd_sum(void *l3_hdr, uint16_t ethertype, uint64_t ol_flags)\n{\n\tif (ethertype == ETHER_TYPE_IPv4)\n\t\treturn rte_ipv4_phdr_cksum(l3_hdr, ol_flags);\n\telse /* assume ethertype == ETHER_TYPE_IPv6 */\n\t\treturn rte_ipv6_phdr_cksum(l3_hdr, ol_flags);\n}\n\n/**\n * Parse an ethernet header to fill the ethertype, outer_l2_len, outer_l3_len and\n * ipproto. This function is able to recognize IPv4/IPv6 with one optional vlan\n * header.\n */\nstatic void\nparse_ethernet(struct ether_hdr *eth_hdr, union tunnel_offload_info *info,\n\t\tuint8_t *l4_proto)\n{\n\tstruct ipv4_hdr *ipv4_hdr;\n\tstruct ipv6_hdr *ipv6_hdr;\n\tuint16_t ethertype;\n\n\tinfo->outer_l2_len = sizeof(struct ether_hdr);\n\tethertype = rte_be_to_cpu_16(eth_hdr->ether_type);\n\n\tif (ethertype == ETHER_TYPE_VLAN) {\n\t\tstruct vlan_hdr *vlan_hdr = (struct vlan_hdr *)(eth_hdr + 1);\n\t\tinfo->outer_l2_len += sizeof(struct vlan_hdr);\n\t\tethertype = rte_be_to_cpu_16(vlan_hdr->eth_proto);\n\t}\n\n\tswitch (ethertype) {\n\tcase ETHER_TYPE_IPv4:\n\t\tipv4_hdr = (struct ipv4_hdr *)\n\t\t\t((char *)eth_hdr + info->outer_l2_len);\n\t\tinfo->outer_l3_len = sizeof(struct ipv4_hdr);\n\t\t*l4_proto = ipv4_hdr->next_proto_id;\n\t\tbreak;\n\tcase ETHER_TYPE_IPv6:\n\t\tipv6_hdr = (struct ipv6_hdr *)\n\t\t\t((char *)eth_hdr + info->outer_l2_len);\n\t\tinfo->outer_l3_len = sizeof(struct ipv6_hdr);\n\t\t*l4_proto = ipv6_hdr->proto;\n\t\tbreak;\n\tdefault:\n\t\tinfo->outer_l3_len = 0;\n\t\t*l4_proto = 0;\n\t\tbreak;\n\t}\n}\n\n/**\n * Calculate the checksum of a packet in hardware\n */\nstatic uint64_t\nprocess_inner_cksums(struct ether_hdr *eth_hdr, union tunnel_offload_info *info)\n{\n\tvoid *l3_hdr = NULL;\n\tuint8_t l4_proto;\n\tuint16_t ethertype;\n\tstruct ipv4_hdr *ipv4_hdr;\n\tstruct ipv6_hdr *ipv6_hdr;\n\tstruct udp_hdr *udp_hdr;\n\tstruct tcp_hdr *tcp_hdr;\n\tstruct sctp_hdr *sctp_hdr;\n\tuint64_t ol_flags = 0;\n\n\tinfo->l2_len = sizeof(struct ether_hdr);\n\tethertype = rte_be_to_cpu_16(eth_hdr->ether_type);\n\n\tif (ethertype == ETHER_TYPE_VLAN) {\n\t\tstruct vlan_hdr *vlan_hdr = (struct vlan_hdr *)(eth_hdr + 1);\n\t\tinfo->l2_len += sizeof(struct vlan_hdr);\n\t\tethertype = rte_be_to_cpu_16(vlan_hdr->eth_proto);\n\t}\n\n\tl3_hdr = (char *)eth_hdr + info->l2_len;\n\n\tif (ethertype == ETHER_TYPE_IPv4) {\n\t\tipv4_hdr = (struct ipv4_hdr *)l3_hdr;\n\t\tipv4_hdr->hdr_checksum = 0;\n\t\tol_flags |= PKT_TX_IPV4;\n\t\tol_flags |= PKT_TX_IP_CKSUM;\n\t\tinfo->l3_len = sizeof(struct ipv4_hdr);\n\t\tl4_proto = ipv4_hdr->next_proto_id;\n\t} else if (ethertype == ETHER_TYPE_IPv6) {\n\t\tipv6_hdr = (struct ipv6_hdr *)l3_hdr;\n\t\tinfo->l3_len = sizeof(struct ipv6_hdr);\n\t\tl4_proto = ipv6_hdr->proto;\n\t\tol_flags |= PKT_TX_IPV6;\n\t} else\n\t\treturn 0; /* packet type not supported, nothing to do */\n\n\tif (l4_proto == IPPROTO_UDP) {\n\t\tudp_hdr = (struct udp_hdr *)((char *)l3_hdr + info->l3_len);\n\t\tol_flags |= PKT_TX_UDP_CKSUM;\n\t\tudp_hdr->dgram_cksum = get_psd_sum(l3_hdr,\n\t\t\t\tethertype, ol_flags);\n\t} else if (l4_proto == IPPROTO_TCP) {\n\t\ttcp_hdr = (struct tcp_hdr *)((char *)l3_hdr + info->l3_len);\n\t\tol_flags |= PKT_TX_TCP_CKSUM;\n\t\ttcp_hdr->cksum = get_psd_sum(l3_hdr, ethertype,\n\t\t\t\tol_flags);\n\t\tif (tso_segsz != 0) {\n\t\t\tol_flags |= PKT_TX_TCP_SEG;\n\t\t\tinfo->tso_segsz = tso_segsz;\n\t\t\tinfo->l4_len = sizeof(struct tcp_hdr);\n\t\t}\n\n\t} else if (l4_proto == IPPROTO_SCTP) {\n\t\tsctp_hdr = (struct sctp_hdr *)((char *)l3_hdr + info->l3_len);\n\t\tsctp_hdr->cksum = 0;\n\t\tol_flags |= PKT_TX_SCTP_CKSUM;\n\t}\n\n\treturn ol_flags;\n}\n\nint\ndecapsulation(struct rte_mbuf *pkt)\n{\n\tuint8_t l4_proto = 0;\n\tuint16_t outer_header_len;\n\tstruct udp_hdr *udp_hdr;\n\tunion tunnel_offload_info info = { .data = 0 };\n\tstruct ether_hdr *phdr = rte_pktmbuf_mtod(pkt, struct ether_hdr *);\n\n\tparse_ethernet(phdr, &info, &l4_proto);\n\n\tif (l4_proto != IPPROTO_UDP)\n\t\treturn -1;\n\n\tudp_hdr = (struct udp_hdr *)((char *)phdr +\n\t\tinfo.outer_l2_len + info.outer_l3_len);\n\n\t/** check udp destination port, 4789 is the default vxlan port\n\t * (rfc7348) or that the rx offload flag is set (i40e only\n\t * currently)*/\n\tif (udp_hdr->dst_port != rte_cpu_to_be_16(DEFAULT_VXLAN_PORT) &&\n#ifdef RTE_NEXT_ABI\n\t\t(pkt->packet_type & RTE_PTYPE_TUNNEL_MASK) == 0)\n#else\n\t\t\t(pkt->ol_flags & (PKT_RX_TUNNEL_IPV4_HDR |\n\t\t\t\tPKT_RX_TUNNEL_IPV6_HDR)) == 0)\n#endif\n\t\treturn -1;\n\touter_header_len = info.outer_l2_len + info.outer_l3_len\n\t\t+ sizeof(struct udp_hdr) + sizeof(struct vxlan_hdr);\n\n\trte_pktmbuf_adj(pkt, outer_header_len);\n\n\treturn 0;\n}\n\nvoid\nencapsulation(struct rte_mbuf *m, uint8_t queue_id)\n{\n\tuint vport_id;\n\tuint64_t ol_flags = 0;\n\tuint32_t old_len = m->pkt_len, hash;\n\tunion tunnel_offload_info tx_offload = { .data = 0 };\n\tstruct ether_hdr *phdr = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\t/*Allocate space for new ethernet, IPv4, UDP and VXLAN headers*/\n\tstruct ether_hdr *pneth = (struct ether_hdr *) rte_pktmbuf_prepend(m,\n\t\tsizeof(struct ether_hdr) + sizeof(struct ipv4_hdr)\n\t\t+ sizeof(struct udp_hdr) + sizeof(struct vxlan_hdr));\n\n\tstruct ipv4_hdr *ip = (struct ipv4_hdr *) &pneth[1];\n\tstruct udp_hdr *udp = (struct udp_hdr *) &ip[1];\n\tstruct vxlan_hdr *vxlan = (struct vxlan_hdr *) &udp[1];\n\n\t/* convert TX queue ID to vport ID */\n\tvport_id = queue_id - 1;\n\n\t/* replace original Ethernet header with ours */\n\tpneth = rte_memcpy(pneth, &app_l2_hdr[vport_id],\n\t\tsizeof(struct ether_hdr));\n\n\t/* copy in IP header */\n\tip = rte_memcpy(ip, &app_ip_hdr[vport_id],\n\t\tsizeof(struct ipv4_hdr));\n\tip->total_length = rte_cpu_to_be_16(m->data_len\n\t\t\t\t- sizeof(struct ether_hdr));\n\n\t/* outer IP checksum */\n\tol_flags |= PKT_TX_OUTER_IP_CKSUM;\n\tip->hdr_checksum = 0;\n\n\t/* inner IP checksum offload */\n\tif (tx_checksum) {\n\t\tol_flags |= process_inner_cksums(phdr, &tx_offload);\n\t\tm->l2_len = tx_offload.l2_len;\n\t\tm->l3_len = tx_offload.l3_len;\n\t\tm->l4_len = tx_offload.l4_len;\n\t\tm->l2_len += ETHER_VXLAN_HLEN;\n\t}\n\n\tm->outer_l2_len = sizeof(struct ether_hdr);\n\tm->outer_l3_len = sizeof(struct ipv4_hdr);\n\n\tm->ol_flags |= ol_flags;\n\tm->tso_segsz = tx_offload.tso_segsz;\n\n\t/*VXLAN HEADER*/\n\tvxlan->vx_flags = rte_cpu_to_be_32(VXLAN_HF_VNI);\n\tvxlan->vx_vni = rte_cpu_to_be_32(vxdev.out_key << 8);\n\n\t/*UDP HEADER*/\n\tudp->dgram_cksum = 0;\n\tudp->dgram_len = rte_cpu_to_be_16(old_len\n\t\t\t\t+ sizeof(struct udp_hdr)\n\t\t\t\t+ sizeof(struct vxlan_hdr));\n\n\tudp->dst_port = rte_cpu_to_be_16(vxdev.dst_port);\n\thash = rte_hash_crc(phdr, 2 * ETHER_ADDR_LEN, phdr->ether_type);\n\tudp->src_port = rte_cpu_to_be_16((((uint64_t) hash * PORT_RANGE) >> 32)\n\t\t\t\t\t+ PORT_MIN);\n\n\treturn;\n}\n" }, { "path": "examples/tep_termination/vxlan.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VXLAN_H_\n#define _VXLAN_H_\n\n#include \n#include \n\n#define PORT_MIN\t49152\n#define PORT_MAX\t65535\n#define PORT_RANGE ((PORT_MAX - PORT_MIN) + 1)\n\n#define VXLAN_N_PORTS 2\n#define VXLAN_HF_VNI 0x08000000\n#define DEFAULT_VXLAN_PORT 4789\n\nextern struct ipv4_hdr app_ip_hdr[VXLAN_N_PORTS];\nextern struct ether_hdr app_l2_hdr[VXLAN_N_PORTS];\nextern uint8_t tx_checksum;\nextern uint16_t tso_segsz;\n\nstruct vxlan_port {\n\tuint32_t vport_id; /**< VirtIO port id */\n\tuint32_t peer_ip; /**< remote VTEP IP address */\n\tstruct ether_addr peer_mac; /**< remote VTEP MAC address */\n\tstruct ether_addr vport_mac; /**< VirtIO port MAC address */\n} __rte_cache_aligned;\n\nstruct vxlan_conf {\n\tuint16_t dst_port; /**< VXLAN UDP destination port */\n\tuint32_t port_ip; /**< DPDK port IP address*/\n\tuint32_t in_key; /**< VLAN ID */\n\tuint32_t out_key; /**< VXLAN VNI */\n\tstruct vxlan_port port[VXLAN_N_PORTS]; /**< VXLAN configuration */\n} __rte_cache_aligned;\n\nextern struct vxlan_conf vxdev;\n\n/* structure that caches offload info for the current packet */\nunion tunnel_offload_info {\n\tuint64_t data;\n\tstruct {\n\t\tuint64_t l2_len:7; /**< L2 (MAC) Header Length. */\n\t\tuint64_t l3_len:9; /**< L3 (IP) Header Length. */\n\t\tuint64_t l4_len:8; /**< L4 Header Length. */\n\t\tuint64_t tso_segsz:16; /**< TCP TSO segment size */\n\t\tuint64_t outer_l2_len:7; /**< outer L2 Header Length */\n\t\tuint64_t outer_l3_len:16; /**< outer L3 Header Length */\n\t};\n} __rte_cache_aligned;\n\nint decapsulation(struct rte_mbuf *pkt);\nvoid encapsulation(struct rte_mbuf *m, uint8_t queue_id);\n\n#endif /* _VXLAN_H_ */\n" }, { "path": "examples/tep_termination/vxlan_setup.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n#include \"rte_virtio_net.h\"\n#include \"vxlan.h\"\n#include \"vxlan_setup.h\"\n\n#define IPV4_HEADER_LEN 20\n#define UDP_HEADER_LEN 8\n#define VXLAN_HEADER_LEN 8\n\n#define IP_VERSION 0x40\n#define IP_HDRLEN 0x05 /* default IP header length == five 32-bits words. */\n#define IP_DEFTTL 64 /* from RFC 1340. */\n#define IP_VHL_DEF (IP_VERSION | IP_HDRLEN)\n\n#define IP_DN_FRAGMENT_FLAG 0x0040\n\n/* Used to compare MAC addresses. */\n#define MAC_ADDR_CMP 0xFFFFFFFFFFFFULL\n\n/* Configurable number of RX/TX ring descriptors */\n#define RTE_TEST_RX_DESC_DEFAULT 1024\n#define RTE_TEST_TX_DESC_DEFAULT 512\n\n/* Default inner VLAN ID */\n#define INNER_VLAN_ID 100\n\n/* VXLAN device */\nstruct vxlan_conf vxdev;\n\nstruct ipv4_hdr app_ip_hdr[VXLAN_N_PORTS];\nstruct ether_hdr app_l2_hdr[VXLAN_N_PORTS];\n\n/* local VTEP IP address */\nuint8_t vxlan_multicast_ips[2][4] = { {239, 1, 1, 1 }, {239, 1, 2, 1 } };\n\n/* Remote VTEP IP address */\nuint8_t vxlan_overlay_ips[2][4] = { {192, 168, 10, 1}, {192, 168, 30, 1} };\n\n/* Remote VTEP MAC address */\nuint8_t peer_mac[6] = {0x00, 0x11, 0x01, 0x00, 0x00, 0x01};\n\n/* VXLAN RX filter type */\nuint8_t tep_filter_type[] = {RTE_TUNNEL_FILTER_IMAC_TENID,\n\t\t\tRTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,\n\t\t\tRTE_TUNNEL_FILTER_OMAC_TENID_IMAC,};\n\n/* Options for configuring ethernet port */\nstatic const struct rte_eth_conf port_conf = {\n\t.rxmode = {\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n};\n\n/**\n * The one or two device(s) that belongs to the same tenant ID can\n * be assigned in a VM.\n */\nconst uint16_t tenant_id_conf[] = {\n\t1000, 1000, 1001, 1001, 1002, 1002, 1003, 1003,\n\t1004, 1004, 1005, 1005, 1006, 1006, 1007, 1007,\n\t1008, 1008, 1009, 1009, 1010, 1010, 1011, 1011,\n\t1012, 1012, 1013, 1013, 1014, 1014, 1015, 1015,\n\t1016, 1016, 1017, 1017, 1018, 1018, 1019, 1019,\n\t1020, 1020, 1021, 1021, 1022, 1022, 1023, 1023,\n\t1024, 1024, 1025, 1025, 1026, 1026, 1027, 1027,\n\t1028, 1028, 1029, 1029, 1030, 1030, 1031, 1031,\n};\n\n/**\n * Initialises a given port using global settings and with the rx buffers\n * coming from the mbuf_pool passed as parameter\n */\nint\nvxlan_port_init(uint8_t port, struct rte_mempool *mbuf_pool)\n{\n\tint retval;\n\tuint16_t q;\n\tstruct rte_eth_dev_info dev_info;\n\tuint16_t rx_rings, tx_rings = (uint16_t)rte_lcore_count();\n\tconst uint16_t rx_ring_size = RTE_TEST_RX_DESC_DEFAULT;\n\tconst uint16_t tx_ring_size = RTE_TEST_TX_DESC_DEFAULT;\n\tstruct rte_eth_udp_tunnel tunnel_udp;\n\tstruct rte_eth_rxconf *rxconf;\n\tstruct rte_eth_txconf *txconf;\n\tstruct vxlan_conf *pconf = &vxdev;\n\n\tpconf->dst_port = udp_port;\n\n\trte_eth_dev_info_get(port, &dev_info);\n\n\tif (dev_info.max_rx_queues > MAX_QUEUES) {\n\t\trte_exit(EXIT_FAILURE,\n\t\t\t\"please define MAX_QUEUES no less than %u in %s\\n\",\n\t\t\tdev_info.max_rx_queues, __FILE__);\n\t}\n\n\trxconf = &dev_info.default_rxconf;\n\ttxconf = &dev_info.default_txconf;\n\ttxconf->txq_flags = 0;\n\n\tif (port >= rte_eth_dev_count())\n\t\treturn -1;\n\n\trx_rings = nb_devices;\n\n\t/* Configure ethernet device. */\n\tretval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);\n\tif (retval != 0)\n\t\treturn retval;\n\n\t/* Setup the queues. */\n\tfor (q = 0; q < rx_rings; q++) {\n\t\tretval = rte_eth_rx_queue_setup(port, q, rx_ring_size,\n\t\t\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\t\t\trxconf,\n\t\t\t\t\t\tmbuf_pool);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\tfor (q = 0; q < tx_rings; q++) {\n\t\tretval = rte_eth_tx_queue_setup(port, q, tx_ring_size,\n\t\t\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\t\t\ttxconf);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\t/* Start the device. */\n\tretval = rte_eth_dev_start(port);\n\tif (retval < 0)\n\t\treturn retval;\n\n\t/* Configure UDP port for UDP tunneling */\n\ttunnel_udp.udp_port = udp_port;\n\ttunnel_udp.prot_type = RTE_TUNNEL_TYPE_VXLAN;\n\tretval = rte_eth_dev_udp_tunnel_add(port, &tunnel_udp);\n\tif (retval < 0)\n\t\treturn retval;\n\trte_eth_macaddr_get(port, &ports_eth_addr[port]);\n\tRTE_LOG(INFO, PORT, \"Port %u MAC: %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\n\t\t\t\" %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\"\\n\",\n\t\t\t(unsigned)port,\n\t\t\tports_eth_addr[port].addr_bytes[0],\n\t\t\tports_eth_addr[port].addr_bytes[1],\n\t\t\tports_eth_addr[port].addr_bytes[2],\n\t\t\tports_eth_addr[port].addr_bytes[3],\n\t\t\tports_eth_addr[port].addr_bytes[4],\n\t\t\tports_eth_addr[port].addr_bytes[5]);\n\n\tif (tso_segsz != 0) {\n\t\tstruct rte_eth_dev_info dev_info;\n\t\trte_eth_dev_info_get(port, &dev_info);\n\t\tif ((dev_info.tx_offload_capa & DEV_TX_OFFLOAD_TCP_TSO) == 0)\n\t\t\tRTE_LOG(WARNING, PORT,\n\t\t\t\t\"hardware TSO offload is not supported\\n\");\n\t}\n\treturn 0;\n}\n\nstatic int\nvxlan_rx_process(struct rte_mbuf *pkt)\n{\n\tint ret = 0;\n\n\tif (rx_decap)\n\t\tret = decapsulation(pkt);\n\n\treturn ret;\n}\n\nstatic void\nvxlan_tx_process(uint8_t queue_id, struct rte_mbuf *pkt)\n{\n\tif (tx_encap)\n\t\tencapsulation(pkt, queue_id);\n\n\treturn;\n}\n\n/*\n * This function learns the MAC address of the device and set init\n * L2 header and L3 header info.\n */\nint\nvxlan_link(struct vhost_dev *vdev, struct rte_mbuf *m)\n{\n\tint i, ret;\n\tstruct ether_hdr *pkt_hdr;\n\tstruct virtio_net *dev = vdev->dev;\n\tuint64_t portid = dev->device_fh;\n\tstruct ipv4_hdr *ip;\n\n\tstruct rte_eth_tunnel_filter_conf tunnel_filter_conf;\n\n\tif (unlikely(portid > VXLAN_N_PORTS)) {\n\t\tRTE_LOG(INFO, VHOST_DATA,\n\t\t\t\"(%\"PRIu64\") WARNING: Not configuring device,\"\n\t\t\t\"as already have %d ports for VXLAN.\",\n\t\t\tdev->device_fh, VXLAN_N_PORTS);\n\t\treturn -1;\n\t}\n\n\t/* Learn MAC address of guest device from packet */\n\tpkt_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\tif (is_same_ether_addr(&(pkt_hdr->s_addr), &vdev->mac_address)) {\n\t\tRTE_LOG(INFO, VHOST_DATA,\n\t\t\t\"(%\"PRIu64\") WARNING: This device is using an existing\"\n\t\t\t\" MAC address and has not been registered.\\n\",\n\t\t\tdev->device_fh);\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < ETHER_ADDR_LEN; i++) {\n\t\tvdev->mac_address.addr_bytes[i] =\n\t\t\tvxdev.port[portid].vport_mac.addr_bytes[i] =\n\t\t\tpkt_hdr->s_addr.addr_bytes[i];\n\t\tvxdev.port[portid].peer_mac.addr_bytes[i] = peer_mac[i];\n\t}\n\n\tmemset(&tunnel_filter_conf, 0,\n\t\tsizeof(struct rte_eth_tunnel_filter_conf));\n\n\ttunnel_filter_conf.outer_mac = &ports_eth_addr[0];\n\ttunnel_filter_conf.filter_type = tep_filter_type[filter_idx];\n\n\t/* inner MAC */\n\ttunnel_filter_conf.inner_mac = &vdev->mac_address;\n\n\ttunnel_filter_conf.queue_id = vdev->rx_q;\n\ttunnel_filter_conf.tenant_id = tenant_id_conf[vdev->rx_q];\n\n\tif (tep_filter_type[filter_idx] == RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID)\n\t\ttunnel_filter_conf.inner_vlan = INNER_VLAN_ID;\n\n\ttunnel_filter_conf.tunnel_type = RTE_TUNNEL_TYPE_VXLAN;\n\n\tret = rte_eth_dev_filter_ctrl(ports[0],\n\t\tRTE_ETH_FILTER_TUNNEL,\n\t\tRTE_ETH_FILTER_ADD,\n\t\t&tunnel_filter_conf);\n\tif (ret) {\n\t\tRTE_LOG(ERR, VHOST_DATA,\n\t\t\t\"%d Failed to add device MAC address to cloud filter\\n\",\n\t\tvdev->rx_q);\n\t\treturn -1;\n\t}\n\n\t/* Print out inner MAC and VNI info. */\n\tRTE_LOG(INFO, VHOST_DATA,\n\t\t\"(%d) MAC_ADDRESS %02x:%02x:%02x:%02x:%02x:%02x and VNI %d registered\\n\",\n\t\tvdev->rx_q,\n\t\tvdev->mac_address.addr_bytes[0],\n\t\tvdev->mac_address.addr_bytes[1],\n\t\tvdev->mac_address.addr_bytes[2],\n\t\tvdev->mac_address.addr_bytes[3],\n\t\tvdev->mac_address.addr_bytes[4],\n\t\tvdev->mac_address.addr_bytes[5],\n\t\ttenant_id_conf[vdev->rx_q]);\n\n\tvxdev.port[portid].vport_id = portid;\n\n\tfor (i = 0; i < 4; i++) {\n\t\t/* Local VTEP IP */\n\t\tvxdev.port_ip |= vxlan_multicast_ips[portid][i] << (8 * i);\n\t\t/* Remote VTEP IP */\n\t\tvxdev.port[portid].peer_ip |=\n\t\t\tvxlan_overlay_ips[portid][i] << (8 * i);\n\t}\n\n\tvxdev.out_key = tenant_id_conf[vdev->rx_q];\n\tether_addr_copy(&vxdev.port[portid].peer_mac,\n\t\t\t&app_l2_hdr[portid].d_addr);\n\tether_addr_copy(&ports_eth_addr[0],\n\t\t\t&app_l2_hdr[portid].s_addr);\n\tapp_l2_hdr[portid].ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);\n\n\tip = &app_ip_hdr[portid];\n\tip->version_ihl = IP_VHL_DEF;\n\tip->type_of_service = 0;\n\tip->total_length = 0;\n\tip->packet_id = 0;\n\tip->fragment_offset = IP_DN_FRAGMENT_FLAG;\n\tip->time_to_live = IP_DEFTTL;\n\tip->next_proto_id = IPPROTO_UDP;\n\tip->hdr_checksum = 0;\n\tip->src_addr = vxdev.port_ip;\n\tip->dst_addr = vxdev.port[portid].peer_ip;\n\n\t/* Set device as ready for RX. */\n\tvdev->ready = DEVICE_RX;\n\n\treturn 0;\n}\n\n/**\n * Removes cloud filter. Ensures that nothing is adding buffers to the RX\n * queue before disabling RX on the device.\n */\nvoid\nvxlan_unlink(struct vhost_dev *vdev)\n{\n\tunsigned i = 0, rx_count;\n\tint ret;\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct rte_eth_tunnel_filter_conf tunnel_filter_conf;\n\n\tif (vdev->ready == DEVICE_RX) {\n\t\tmemset(&tunnel_filter_conf, 0,\n\t\t\tsizeof(struct rte_eth_tunnel_filter_conf));\n\n\t\ttunnel_filter_conf.outer_mac = &ports_eth_addr[0];\n\t\ttunnel_filter_conf.inner_mac = &vdev->mac_address;\n\t\ttunnel_filter_conf.tenant_id = tenant_id_conf[vdev->rx_q];\n\t\ttunnel_filter_conf.filter_type = tep_filter_type[filter_idx];\n\n\t\tif (tep_filter_type[filter_idx] ==\n\t\t\tRTE_TUNNEL_FILTER_IMAC_IVLAN_TENID)\n\t\t\ttunnel_filter_conf.inner_vlan = INNER_VLAN_ID;\n\n\t\ttunnel_filter_conf.queue_id = vdev->rx_q;\n\t\ttunnel_filter_conf.tunnel_type = RTE_TUNNEL_TYPE_VXLAN;\n\n\t\tret = rte_eth_dev_filter_ctrl(ports[0],\n\t\t\t\tRTE_ETH_FILTER_TUNNEL,\n\t\t\t\tRTE_ETH_FILTER_DELETE,\n\t\t\t\t&tunnel_filter_conf);\n\t\tif (ret) {\n\t\t\tRTE_LOG(ERR, VHOST_DATA,\n\t\t\t\t\"%d Failed to add device MAC address to cloud filter\\n\",\n\t\t\t\tvdev->rx_q);\n\t\t\treturn;\n\t\t}\n\t\tfor (i = 0; i < ETHER_ADDR_LEN; i++)\n\t\t\tvdev->mac_address.addr_bytes[i] = 0;\n\n\t\t/* Clear out the receive buffers */\n\t\trx_count = rte_eth_rx_burst(ports[0],\n\t\t\t\t(uint16_t)vdev->rx_q,\n\t\t\t\tpkts_burst, MAX_PKT_BURST);\n\n\t\twhile (rx_count) {\n\t\t\tfor (i = 0; i < rx_count; i++)\n\t\t\t\trte_pktmbuf_free(pkts_burst[i]);\n\n\t\t\trx_count = rte_eth_rx_burst(ports[0],\n\t\t\t\t\t(uint16_t)vdev->rx_q,\n\t\t\t\t\tpkts_burst, MAX_PKT_BURST);\n\t\t}\n\t\tvdev->ready = DEVICE_MAC_LEARNING;\n\t}\n}\n\n/* Transmit packets after encapsulating */\nint\nvxlan_tx_pkts(uint8_t port_id, uint16_t queue_id,\n\t\tstruct rte_mbuf **tx_pkts, uint16_t nb_pkts) {\n\tint ret = 0;\n\tuint16_t i;\n\n\tfor (i = 0; i < nb_pkts; i++)\n\t\tvxlan_tx_process(queue_id, tx_pkts[i]);\n\n\tret = rte_eth_tx_burst(port_id, queue_id, tx_pkts, nb_pkts);\n\n\treturn ret;\n}\n\n/* Check for decapsulation and pass packets directly to VIRTIO device */\nint\nvxlan_rx_pkts(struct virtio_net *dev, struct rte_mbuf **pkts_burst,\n\t\tuint32_t rx_count)\n{\n\tuint32_t i = 0;\n\tuint32_t count = 0;\n\tint ret;\n\tstruct rte_mbuf *pkts_valid[rx_count];\n\n\tfor (i = 0; i < rx_count; i++) {\n\t\tif (enable_stats) {\n\t\t\trte_atomic64_add(\n\t\t\t\t&dev_statistics[dev->device_fh].rx_bad_ip_csum,\n\t\t\t\t(pkts_burst[i]->ol_flags & PKT_RX_IP_CKSUM_BAD)\n\t\t\t\t!= 0);\n\t\t\trte_atomic64_add(\n\t\t\t\t&dev_statistics[dev->device_fh].rx_bad_ip_csum,\n\t\t\t\t(pkts_burst[i]->ol_flags & PKT_RX_L4_CKSUM_BAD)\n\t\t\t\t!= 0);\n\t\t}\n\t\tret = vxlan_rx_process(pkts_burst[i]);\n\t\tif (unlikely(ret < 0))\n\t\t\tcontinue;\n\n\t\tpkts_valid[count] = pkts_burst[i];\n\t\t\tcount++;\n\t}\n\n\tret = rte_vhost_enqueue_burst(dev, VIRTIO_RXQ, pkts_valid, count);\n\treturn ret;\n}\n" }, { "path": "examples/tep_termination/vxlan_setup.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef VXLAN_SETUP_H_\n#define VXLAN_SETUP_H_\n\nextern uint16_t nb_devices;\nextern uint16_t udp_port;\nextern uint8_t filter_idx;\nextern uint8_t ports[RTE_MAX_ETHPORTS];\nextern struct ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];\nextern uint32_t enable_stats;\nextern struct device_statistics dev_statistics[MAX_DEVICES];\nextern uint8_t rx_decap;\nextern uint8_t tx_encap;\n\ntypedef int (*ol_port_configure_t)(uint8_t port,\n\t\t\t\t struct rte_mempool *mbuf_pool);\n\ntypedef int (*ol_tunnel_setup_t)(struct vhost_dev *vdev,\n\t\t\t\t struct rte_mbuf *m);\n\ntypedef void (*ol_tunnel_destroy_t)(struct vhost_dev *vdev);\n\ntypedef int (*ol_tx_handle_t)(uint8_t port_id, uint16_t queue_id,\n\t\t\t struct rte_mbuf **tx_pkts, uint16_t nb_pkts);\n\ntypedef int (*ol_rx_handle_t)(struct virtio_net *dev, struct rte_mbuf **pkts,\n\t\t\t uint32_t count);\n\ntypedef int (*ol_param_handle)(struct virtio_net *dev);\n\nstruct ol_switch_ops {\n\tol_port_configure_t port_configure;\n\tol_tunnel_setup_t tunnel_setup;\n\tol_tunnel_destroy_t tunnel_destroy;\n\tol_tx_handle_t tx_handle;\n\tol_rx_handle_t rx_handle;\n\tol_param_handle param_handle;\n};\n\nint\nvxlan_port_init(uint8_t port, struct rte_mempool *mbuf_pool);\n\nint\nvxlan_link(struct vhost_dev *vdev, struct rte_mbuf *m);\n\nvoid\nvxlan_unlink(struct vhost_dev *vdev);\n\nint\nvxlan_tx_pkts(uint8_t port_id, uint16_t queue_id,\n\t\t\tstruct rte_mbuf **tx_pkts, uint16_t nb_pkts);\nint\nvxlan_rx_pkts(struct virtio_net *dev, struct rte_mbuf **pkts, uint32_t count);\n\n#endif /* VXLAN_SETUP_H_ */\n" }, { "path": "examples/timer/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = timer\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/timer/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define TIMER_RESOLUTION_CYCLES 20000000ULL /* around 10ms at 2 Ghz */\n\nstatic struct rte_timer timer0;\nstatic struct rte_timer timer1;\n\n/* timer0 callback */\nstatic void\ntimer0_cb(__attribute__((unused)) struct rte_timer *tim,\n\t __attribute__((unused)) void *arg)\n{\n\tstatic unsigned counter = 0;\n\tunsigned lcore_id = rte_lcore_id();\n\n\tprintf(\"%s() on lcore %u\\n\", __func__, lcore_id);\n\n\t/* this timer is automatically reloaded until we decide to\n\t * stop it, when counter reaches 20. */\n\tif ((counter ++) == 20)\n\t\trte_timer_stop(tim);\n}\n\n/* timer1 callback */\nstatic void\ntimer1_cb(__attribute__((unused)) struct rte_timer *tim,\n\t __attribute__((unused)) void *arg)\n{\n\tunsigned lcore_id = rte_lcore_id();\n\tuint64_t hz;\n\n\tprintf(\"%s() on lcore %u\\n\", __func__, lcore_id);\n\n\t/* reload it on another lcore */\n\thz = rte_get_timer_hz();\n\tlcore_id = rte_get_next_lcore(lcore_id, 0, 1);\n\trte_timer_reset(tim, hz/3, SINGLE, lcore_id, timer1_cb, NULL);\n}\n\nstatic __attribute__((noreturn)) int\nlcore_mainloop(__attribute__((unused)) void *arg)\n{\n\tuint64_t prev_tsc = 0, cur_tsc, diff_tsc;\n\tunsigned lcore_id;\n\n\tlcore_id = rte_lcore_id();\n\tprintf(\"Starting mainloop on core %u\\n\", lcore_id);\n\n\twhile (1) {\n\t\t/*\n\t\t * Call the timer handler on each core: as we don't\n\t\t * need a very precise timer, so only call\n\t\t * rte_timer_manage() every ~10ms (at 2Ghz). In a real\n\t\t * application, this will enhance performances as\n\t\t * reading the HPET timer is not efficient.\n\t\t */\n\t\tcur_tsc = rte_rdtsc();\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (diff_tsc > TIMER_RESOLUTION_CYCLES) {\n\t\t\trte_timer_manage();\n\t\t\tprev_tsc = cur_tsc;\n\t\t}\n\t}\n}\n\nint\nmain(int argc, char **argv)\n{\n\tint ret;\n\tuint64_t hz;\n\tunsigned lcore_id;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_panic(\"Cannot init EAL\\n\");\n\n\t/* init RTE timer library */\n\trte_timer_subsystem_init();\n\n\t/* init timer structures */\n\trte_timer_init(&timer0);\n\trte_timer_init(&timer1);\n\n\t/* load timer0, every second, on master lcore, reloaded automatically */\n\thz = rte_get_timer_hz();\n\tlcore_id = rte_lcore_id();\n\trte_timer_reset(&timer0, hz, PERIODICAL, lcore_id, timer0_cb, NULL);\n\n\t/* load timer1, every second/3, on next lcore, reloaded manually */\n\tlcore_id = rte_get_next_lcore(lcore_id, 0, 1);\n\trte_timer_reset(&timer1, hz/3, SINGLE, lcore_id, timer1_cb, NULL);\n\n\t/* call lcore_mainloop() on every slave lcore */\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\trte_eal_remote_launch(lcore_mainloop, NULL, lcore_id);\n\t}\n\n\t/* call it on master lcore too */\n\t(void) lcore_mainloop(NULL);\n\n\treturn 0;\n}\n" }, { "path": "examples/vhost/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifneq ($(CONFIG_RTE_EXEC_ENV),\"linuxapp\")\n$(info This application can only operate in a linuxapp environment, \\\nplease change the definition of the RTE_TARGET environment variable)\nall:\nelse\n\n# binary name\nAPP = vhost-switch\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += -O2 -D_FILE_OFFSET_BITS=64\nCFLAGS += $(WERROR_FLAGS)\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n\nendif\n" }, { "path": "examples/vhost/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n\n#define MAX_QUEUES 512\n\n/* the maximum number of external ports supported */\n#define MAX_SUP_PORTS 1\n\n/*\n * Calculate the number of buffers needed per port\n */\n#define NUM_MBUFS_PER_PORT ((MAX_QUEUES*RTE_TEST_RX_DESC_DEFAULT) +\t\t\\\n\t\t\t\t\t\t\t(num_switching_cores*MAX_PKT_BURST) + \t\t\t\\\n\t\t\t\t\t\t\t(num_switching_cores*RTE_TEST_TX_DESC_DEFAULT) +\\\n\t\t\t\t\t\t\t(num_switching_cores*MBUF_CACHE_SIZE))\n\n#define MBUF_CACHE_SIZE\t128\n#define MBUF_DATA_SIZE\tRTE_MBUF_DEFAULT_BUF_SIZE\n\n/*\n * No frame data buffer allocated from host are required for zero copy\n * implementation, guest will allocate the frame data buffer, and vhost\n * directly use it.\n */\n#define VIRTIO_DESCRIPTOR_LEN_ZCP\tRTE_MBUF_DEFAULT_DATAROOM\n#define MBUF_DATA_SIZE_ZCP\t\tRTE_MBUF_DEFAULT_BUF_SIZE\n#define MBUF_CACHE_SIZE_ZCP 0\n\n#define MAX_PKT_BURST 32\t\t/* Max burst size for RX/TX */\n#define BURST_TX_DRAIN_US 100\t/* TX drain every ~100us */\n\n#define BURST_RX_WAIT_US 15\t/* Defines how long we wait between retries on RX */\n#define BURST_RX_RETRIES 4\t\t/* Number of retries on RX. */\n\n#define JUMBO_FRAME_MAX_SIZE 0x2600\n\n/* State of virtio device. */\n#define DEVICE_MAC_LEARNING 0\n#define DEVICE_RX\t\t\t1\n#define DEVICE_SAFE_REMOVE\t2\n\n/* Config_core_flag status definitions. */\n#define REQUEST_DEV_REMOVAL 1\n#define ACK_DEV_REMOVAL 0\n\n/* Configurable number of RX/TX ring descriptors */\n#define RTE_TEST_RX_DESC_DEFAULT 1024\n#define RTE_TEST_TX_DESC_DEFAULT 512\n\n/*\n * Need refine these 2 macros for legacy and DPDK based front end:\n * Max vring avail descriptor/entries from guest - MAX_PKT_BURST\n * And then adjust power 2.\n */\n/*\n * For legacy front end, 128 descriptors,\n * half for virtio header, another half for mbuf.\n */\n#define RTE_TEST_RX_DESC_DEFAULT_ZCP 32 /* legacy: 32, DPDK virt FE: 128. */\n#define RTE_TEST_TX_DESC_DEFAULT_ZCP 64 /* legacy: 64, DPDK virt FE: 64. */\n\n/* Get first 4 bytes in mbuf headroom. */\n#define MBUF_HEADROOM_UINT32(mbuf) (*(uint32_t *)((uint8_t *)(mbuf) \\\n\t\t+ sizeof(struct rte_mbuf)))\n\n/* true if x is a power of 2 */\n#define POWEROF2(x) ((((x)-1) & (x)) == 0)\n\n#define INVALID_PORT_ID 0xFF\n\n/* Max number of devices. Limited by vmdq. */\n#define MAX_DEVICES 64\n\n/* Size of buffers used for snprintfs. */\n#define MAX_PRINT_BUFF 6072\n\n/* Maximum character device basename size. */\n#define MAX_BASENAME_SZ 10\n\n/* Maximum long option length for option parsing. */\n#define MAX_LONG_OPT_SZ 64\n\n/* Used to compare MAC addresses. */\n#define MAC_ADDR_CMP 0xFFFFFFFFFFFFULL\n\n/* Number of descriptors per cacheline. */\n#define DESC_PER_CACHELINE (RTE_CACHE_LINE_SIZE / sizeof(struct vring_desc))\n\n#define MBUF_EXT_MEM(mb) (rte_mbuf_from_indirect(mb) != (mb))\n\n/* mask of enabled ports */\nstatic uint32_t enabled_port_mask = 0;\n\n/* Promiscuous mode */\nstatic uint32_t promiscuous;\n\n/*Number of switching cores enabled*/\nstatic uint32_t num_switching_cores = 0;\n\n/* number of devices/queues to support*/\nstatic uint32_t num_queues = 0;\nstatic uint32_t num_devices;\n\n/*\n * Enable zero copy, pkts buffer will directly dma to hw descriptor,\n * disabled on default.\n */\nstatic uint32_t zero_copy;\nstatic int mergeable;\n\n/* Do vlan strip on host, enabled on default */\nstatic uint32_t vlan_strip = 1;\n\n/* number of descriptors to apply*/\nstatic uint32_t num_rx_descriptor = RTE_TEST_RX_DESC_DEFAULT_ZCP;\nstatic uint32_t num_tx_descriptor = RTE_TEST_TX_DESC_DEFAULT_ZCP;\n\n/* max ring descriptor, ixgbe, i40e, e1000 all are 4096. */\n#define MAX_RING_DESC 4096\n\nstruct vpool {\n\tstruct rte_mempool *pool;\n\tstruct rte_ring *ring;\n\tuint32_t buf_size;\n} vpool_array[MAX_QUEUES+MAX_QUEUES];\n\n/* Enable VM2VM communications. If this is disabled then the MAC address compare is skipped. */\ntypedef enum {\n\tVM2VM_DISABLED = 0,\n\tVM2VM_SOFTWARE = 1,\n\tVM2VM_HARDWARE = 2,\n\tVM2VM_LAST\n} vm2vm_type;\nstatic vm2vm_type vm2vm_mode = VM2VM_SOFTWARE;\n\n/* The type of host physical address translated from guest physical address. */\ntypedef enum {\n\tPHYS_ADDR_CONTINUOUS = 0,\n\tPHYS_ADDR_CROSS_SUBREG = 1,\n\tPHYS_ADDR_INVALID = 2,\n\tPHYS_ADDR_LAST\n} hpa_type;\n\n/* Enable stats. */\nstatic uint32_t enable_stats = 0;\n/* Enable retries on RX. */\nstatic uint32_t enable_retry = 1;\n/* Specify timeout (in useconds) between retries on RX. */\nstatic uint32_t burst_rx_delay_time = BURST_RX_WAIT_US;\n/* Specify the number of retries on RX. */\nstatic uint32_t burst_rx_retry_num = BURST_RX_RETRIES;\n\n/* Character device basename. Can be set by user. */\nstatic char dev_basename[MAX_BASENAME_SZ] = \"vhost-net\";\n\n/* empty vmdq configuration structure. Filled in programatically */\nstatic struct rte_eth_conf vmdq_conf_default = {\n\t.rxmode = {\n\t\t.mq_mode = ETH_MQ_RX_VMDQ_ONLY,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t/*\n\t\t * It is necessary for 1G NIC such as I350,\n\t\t * this fixes bug of ipv4 forwarding in guest can't\n\t\t * forward pakets from one virtio dev to another virtio dev.\n\t\t */\n\t\t.hw_vlan_strip = 1, /**< VLAN strip enabled. */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n\t.rx_adv_conf = {\n\t\t/*\n\t\t * should be overridden separately in code with\n\t\t * appropriate values\n\t\t */\n\t\t.vmdq_rx_conf = {\n\t\t\t.nb_queue_pools = ETH_8_POOLS,\n\t\t\t.enable_default_pool = 0,\n\t\t\t.default_pool = 0,\n\t\t\t.nb_pool_maps = 0,\n\t\t\t.pool_map = {{0, 0},},\n\t\t},\n\t},\n};\n\nstatic unsigned lcore_ids[RTE_MAX_LCORE];\nstatic uint8_t ports[RTE_MAX_ETHPORTS];\nstatic unsigned num_ports = 0; /**< The number of ports specified in command line */\nstatic uint16_t num_pf_queues, num_vmdq_queues;\nstatic uint16_t vmdq_pool_base, vmdq_queue_base;\nstatic uint16_t queues_per_pool;\n\nstatic const uint16_t external_pkt_default_vlan_tag = 2000;\nconst uint16_t vlan_tags[] = {\n\t1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,\n\t1008, 1009, 1010, 1011,\t1012, 1013, 1014, 1015,\n\t1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,\n\t1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031,\n\t1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,\n\t1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047,\n\t1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,\n\t1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063,\n};\n\n/* ethernet addresses of ports */\nstatic struct ether_addr vmdq_ports_eth_addr[RTE_MAX_ETHPORTS];\n\n/* heads for the main used and free linked lists for the data path. */\nstatic struct virtio_net_data_ll *ll_root_used = NULL;\nstatic struct virtio_net_data_ll *ll_root_free = NULL;\n\n/* Array of data core structures containing information on individual core linked lists. */\nstatic struct lcore_info lcore_info[RTE_MAX_LCORE];\n\n/* Used for queueing bursts of TX packets. */\nstruct mbuf_table {\n\tunsigned len;\n\tunsigned txq_id;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST];\n};\n\n/* TX queue for each data core. */\nstruct mbuf_table lcore_tx_queue[RTE_MAX_LCORE];\n\n/* TX queue fori each virtio device for zero copy. */\nstruct mbuf_table tx_queue_zcp[MAX_QUEUES];\n\n/* Vlan header struct used to insert vlan tags on TX. */\nstruct vlan_ethhdr {\n\tunsigned char h_dest[ETH_ALEN];\n\tunsigned char h_source[ETH_ALEN];\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\n/* IPv4 Header */\nstruct ipv4_hdr {\n\tuint8_t version_ihl;\t\t/**< version and header length */\n\tuint8_t type_of_service;\t/**< type of service */\n\tuint16_t total_length;\t\t/**< length of packet */\n\tuint16_t packet_id;\t\t/**< packet ID */\n\tuint16_t fragment_offset;\t/**< fragmentation offset */\n\tuint8_t time_to_live;\t\t/**< time to live */\n\tuint8_t next_proto_id;\t\t/**< protocol ID */\n\tuint16_t hdr_checksum;\t\t/**< header checksum */\n\tuint32_t src_addr;\t\t/**< source address */\n\tuint32_t dst_addr;\t\t/**< destination address */\n} __attribute__((__packed__));\n\n/* Header lengths. */\n#define VLAN_HLEN 4\n#define VLAN_ETH_HLEN 18\n\n/* Per-device statistics struct */\nstruct device_statistics {\n\tuint64_t tx_total;\n\trte_atomic64_t rx_total_atomic;\n\tuint64_t rx_total;\n\tuint64_t tx;\n\trte_atomic64_t rx_atomic;\n\tuint64_t rx;\n} __rte_cache_aligned;\nstruct device_statistics dev_statistics[MAX_DEVICES];\n\n/*\n * Builds up the correct configuration for VMDQ VLAN pool map\n * according to the pool & queue limits.\n */\nstatic inline int\nget_eth_conf(struct rte_eth_conf *eth_conf, uint32_t num_devices)\n{\n\tstruct rte_eth_vmdq_rx_conf conf;\n\tstruct rte_eth_vmdq_rx_conf *def_conf =\n\t\t&vmdq_conf_default.rx_adv_conf.vmdq_rx_conf;\n\tunsigned i;\n\n\tmemset(&conf, 0, sizeof(conf));\n\tconf.nb_queue_pools = (enum rte_eth_nb_pools)num_devices;\n\tconf.nb_pool_maps = num_devices;\n\tconf.enable_loop_back = def_conf->enable_loop_back;\n\tconf.rx_mode = def_conf->rx_mode;\n\n\tfor (i = 0; i < conf.nb_pool_maps; i++) {\n\t\tconf.pool_map[i].vlan_id = vlan_tags[ i ];\n\t\tconf.pool_map[i].pools = (1UL << i);\n\t}\n\n\t(void)(rte_memcpy(eth_conf, &vmdq_conf_default, sizeof(*eth_conf)));\n\t(void)(rte_memcpy(ð_conf->rx_adv_conf.vmdq_rx_conf, &conf,\n\t\t sizeof(eth_conf->rx_adv_conf.vmdq_rx_conf)));\n\treturn 0;\n}\n\n/*\n * Validate the device number according to the max pool number gotten form\n * dev_info. If the device number is invalid, give the error message and\n * return -1. Each device must have its own pool.\n */\nstatic inline int\nvalidate_num_devices(uint32_t max_nb_devices)\n{\n\tif (num_devices > max_nb_devices) {\n\t\tRTE_LOG(ERR, VHOST_PORT, \"invalid number of devices\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/*\n * Initialises a given port using global settings and with the rx buffers\n * coming from the mbuf_pool passed as parameter\n */\nstatic inline int\nport_init(uint8_t port)\n{\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_conf port_conf;\n\tstruct rte_eth_rxconf *rxconf;\n\tstruct rte_eth_txconf *txconf;\n\tint16_t rx_rings, tx_rings;\n\tuint16_t rx_ring_size, tx_ring_size;\n\tint retval;\n\tuint16_t q;\n\n\t/* The max pool number from dev_info will be used to validate the pool number specified in cmd line */\n\trte_eth_dev_info_get (port, &dev_info);\n\n\tif (dev_info.max_rx_queues > MAX_QUEUES) {\n\t\trte_exit(EXIT_FAILURE,\n\t\t\t\"please define MAX_QUEUES no less than %u in %s\\n\",\n\t\t\tdev_info.max_rx_queues, __FILE__);\n\t}\n\n\trxconf = &dev_info.default_rxconf;\n\ttxconf = &dev_info.default_txconf;\n\trxconf->rx_drop_en = 1;\n\n\t/* Enable vlan offload */\n\ttxconf->txq_flags &= ~ETH_TXQ_FLAGS_NOVLANOFFL;\n\n\t/*\n\t * Zero copy defers queue RX/TX start to the time when guest\n\t * finishes its startup and packet buffers from that guest are\n\t * available.\n\t */\n\tif (zero_copy) {\n\t\trxconf->rx_deferred_start = 1;\n\t\trxconf->rx_drop_en = 0;\n\t\ttxconf->tx_deferred_start = 1;\n\t}\n\n\t/*configure the number of supported virtio devices based on VMDQ limits */\n\tnum_devices = dev_info.max_vmdq_pools;\n\n\tif (zero_copy) {\n\t\trx_ring_size = num_rx_descriptor;\n\t\ttx_ring_size = num_tx_descriptor;\n\t\ttx_rings = dev_info.max_tx_queues;\n\t} else {\n\t\trx_ring_size = RTE_TEST_RX_DESC_DEFAULT;\n\t\ttx_ring_size = RTE_TEST_TX_DESC_DEFAULT;\n\t\ttx_rings = (uint16_t)rte_lcore_count();\n\t}\n\n\tretval = validate_num_devices(MAX_DEVICES);\n\tif (retval < 0)\n\t\treturn retval;\n\n\t/* Get port configuration. */\n\tretval = get_eth_conf(&port_conf, num_devices);\n\tif (retval < 0)\n\t\treturn retval;\n\t/* NIC queues are divided into pf queues and vmdq queues. */\n\tnum_pf_queues = dev_info.max_rx_queues - dev_info.vmdq_queue_num;\n\tqueues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;\n\tnum_vmdq_queues = num_devices * queues_per_pool;\n\tnum_queues = num_pf_queues + num_vmdq_queues;\n\tvmdq_queue_base = dev_info.vmdq_queue_base;\n\tvmdq_pool_base = dev_info.vmdq_pool_base;\n\tprintf(\"pf queue num: %u, configured vmdq pool num: %u, each vmdq pool has %u queues\\n\",\n\t\tnum_pf_queues, num_devices, queues_per_pool);\n\n\tif (port >= rte_eth_dev_count()) return -1;\n\n\trx_rings = (uint16_t)dev_info.max_rx_queues;\n\t/* Configure ethernet device. */\n\tretval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);\n\tif (retval != 0)\n\t\treturn retval;\n\n\t/* Setup the queues. */\n\tfor (q = 0; q < rx_rings; q ++) {\n\t\tretval = rte_eth_rx_queue_setup(port, q, rx_ring_size,\n\t\t\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\t\t\trxconf,\n\t\t\t\t\t\tvpool_array[q].pool);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\tfor (q = 0; q < tx_rings; q ++) {\n\t\tretval = rte_eth_tx_queue_setup(port, q, tx_ring_size,\n\t\t\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\t\t\ttxconf);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\t/* Start the device. */\n\tretval = rte_eth_dev_start(port);\n\tif (retval < 0) {\n\t\tRTE_LOG(ERR, VHOST_DATA, \"Failed to start the device.\\n\");\n\t\treturn retval;\n\t}\n\n\tif (promiscuous)\n\t\trte_eth_promiscuous_enable(port);\n\n\trte_eth_macaddr_get(port, &vmdq_ports_eth_addr[port]);\n\tRTE_LOG(INFO, VHOST_PORT, \"Max virtio devices supported: %u\\n\", num_devices);\n\tRTE_LOG(INFO, VHOST_PORT, \"Port %u MAC: %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\n\t\t\t\" %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\"\\n\",\n\t\t\t(unsigned)port,\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[0],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[1],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[2],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[3],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[4],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[5]);\n\n\treturn 0;\n}\n\n/*\n * Set character device basename.\n */\nstatic int\nus_vhost_parse_basename(const char *q_arg)\n{\n\t/* parse number string */\n\n\tif (strnlen(q_arg, MAX_BASENAME_SZ) > MAX_BASENAME_SZ)\n\t\treturn -1;\n\telse\n\t\tsnprintf((char*)&dev_basename, MAX_BASENAME_SZ, \"%s\", q_arg);\n\n\treturn 0;\n}\n\n/*\n * Parse the portmask provided at run time.\n */\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\terrno = 0;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0') || (errno != 0))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n\n}\n\n/*\n * Parse num options at run time.\n */\nstatic int\nparse_num_opt(const char *q_arg, uint32_t max_valid_value)\n{\n\tchar *end = NULL;\n\tunsigned long num;\n\n\terrno = 0;\n\n\t/* parse unsigned int string */\n\tnum = strtoul(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0') || (errno != 0))\n\t\treturn -1;\n\n\tif (num > max_valid_value)\n\t\treturn -1;\n\n\treturn num;\n\n}\n\n/*\n * Display usage\n */\nstatic void\nus_vhost_usage(const char *prgname)\n{\n\tRTE_LOG(INFO, VHOST_CONFIG, \"%s [EAL options] -- -p PORTMASK\\n\"\n\t\"\t\t--vm2vm [0|1|2]\\n\"\n\t\"\t\t--rx_retry [0|1] --mergeable [0|1] --stats [0-N]\\n\"\n\t\"\t\t--dev-basename \\n\"\n\t\"\t\t--nb-devices ND\\n\"\n\t\"\t\t-p PORTMASK: Set mask for ports to be used by application\\n\"\n\t\"\t\t--vm2vm [0|1|2]: disable/software(default)/hardware vm2vm comms\\n\"\n\t\"\t\t--rx-retry [0|1]: disable/enable(default) retries on rx. Enable retry if destintation queue is full\\n\"\n\t\"\t\t--rx-retry-delay [0-N]: timeout(in usecond) between retries on RX. This makes effect only if retries on rx enabled\\n\"\n\t\"\t\t--rx-retry-num [0-N]: the number of retries on rx. This makes effect only if retries on rx enabled\\n\"\n\t\"\t\t--mergeable [0|1]: disable(default)/enable RX mergeable buffers\\n\"\n\t\"\t\t--vlan-strip [0|1]: disable/enable(default) RX VLAN strip on host\\n\"\n\t\"\t\t--stats [0-N]: 0: Disable stats, N: Time in seconds to print stats\\n\"\n\t\"\t\t--dev-basename: The basename to be used for the character device.\\n\"\n\t\"\t\t--zero-copy [0|1]: disable(default)/enable rx/tx \"\n\t\t\t\"zero copy\\n\"\n\t\"\t\t--rx-desc-num [0-N]: the number of descriptors on rx, \"\n\t\t\t\"used only when zero copy is enabled.\\n\"\n\t\"\t\t--tx-desc-num [0-N]: the number of descriptors on tx, \"\n\t\t\t\"used only when zero copy is enabled.\\n\",\n\t prgname);\n}\n\n/*\n * Parse the arguments given in the command line of the application.\n */\nstatic int\nus_vhost_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tint option_index;\n\tunsigned i;\n\tconst char *prgname = argv[0];\n\tstatic struct option long_option[] = {\n\t\t{\"vm2vm\", required_argument, NULL, 0},\n\t\t{\"rx-retry\", required_argument, NULL, 0},\n\t\t{\"rx-retry-delay\", required_argument, NULL, 0},\n\t\t{\"rx-retry-num\", required_argument, NULL, 0},\n\t\t{\"mergeable\", required_argument, NULL, 0},\n\t\t{\"vlan-strip\", required_argument, NULL, 0},\n\t\t{\"stats\", required_argument, NULL, 0},\n\t\t{\"dev-basename\", required_argument, NULL, 0},\n\t\t{\"zero-copy\", required_argument, NULL, 0},\n\t\t{\"rx-desc-num\", required_argument, NULL, 0},\n\t\t{\"tx-desc-num\", required_argument, NULL, 0},\n\t\t{NULL, 0, 0, 0},\n\t};\n\n\t/* Parse command line */\n\twhile ((opt = getopt_long(argc, argv, \"p:P\",\n\t\t\tlong_option, &option_index)) != EOF) {\n\t\tswitch (opt) {\n\t\t/* Portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG, \"Invalid portmask\\n\");\n\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase 'P':\n\t\t\tpromiscuous = 1;\n\t\t\tvmdq_conf_default.rx_adv_conf.vmdq_rx_conf.rx_mode =\n\t\t\t\tETH_VMDQ_ACCEPT_BROADCAST |\n\t\t\t\tETH_VMDQ_ACCEPT_MULTICAST;\n\t\t\trte_vhost_feature_enable(1ULL << VIRTIO_NET_F_CTRL_RX);\n\n\t\t\tbreak;\n\n\t\tcase 0:\n\t\t\t/* Enable/disable vm2vm comms. */\n\t\t\tif (!strncmp(long_option[option_index].name, \"vm2vm\",\n\t\t\t\tMAX_LONG_OPT_SZ)) {\n\t\t\t\tret = parse_num_opt(optarg, (VM2VM_LAST - 1));\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument for \"\n\t\t\t\t\t\t\"vm2vm [0|1|2]\\n\");\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else {\n\t\t\t\t\tvm2vm_mode = (vm2vm_type)ret;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Enable/disable retries on RX. */\n\t\t\tif (!strncmp(long_option[option_index].name, \"rx-retry\", MAX_LONG_OPT_SZ)) {\n\t\t\t\tret = parse_num_opt(optarg, 1);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG, \"Invalid argument for rx-retry [0|1]\\n\");\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else {\n\t\t\t\t\tenable_retry = ret;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Specify the retries delay time (in useconds) on RX. */\n\t\t\tif (!strncmp(long_option[option_index].name, \"rx-retry-delay\", MAX_LONG_OPT_SZ)) {\n\t\t\t\tret = parse_num_opt(optarg, INT32_MAX);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG, \"Invalid argument for rx-retry-delay [0-N]\\n\");\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else {\n\t\t\t\t\tburst_rx_delay_time = ret;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Specify the retries number on RX. */\n\t\t\tif (!strncmp(long_option[option_index].name, \"rx-retry-num\", MAX_LONG_OPT_SZ)) {\n\t\t\t\tret = parse_num_opt(optarg, INT32_MAX);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG, \"Invalid argument for rx-retry-num [0-N]\\n\");\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else {\n\t\t\t\t\tburst_rx_retry_num = ret;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Enable/disable RX mergeable buffers. */\n\t\t\tif (!strncmp(long_option[option_index].name, \"mergeable\", MAX_LONG_OPT_SZ)) {\n\t\t\t\tret = parse_num_opt(optarg, 1);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG, \"Invalid argument for mergeable [0|1]\\n\");\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else {\n\t\t\t\t\tmergeable = !!ret;\n\t\t\t\t\tif (ret) {\n\t\t\t\t\t\tvmdq_conf_default.rxmode.jumbo_frame = 1;\n\t\t\t\t\t\tvmdq_conf_default.rxmode.max_rx_pkt_len\n\t\t\t\t\t\t\t= JUMBO_FRAME_MAX_SIZE;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Enable/disable RX VLAN strip on host. */\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\t\"vlan-strip\", MAX_LONG_OPT_SZ)) {\n\t\t\t\tret = parse_num_opt(optarg, 1);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument for VLAN strip [0|1]\\n\");\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else {\n\t\t\t\t\tvlan_strip = !!ret;\n\t\t\t\t\tvmdq_conf_default.rxmode.hw_vlan_strip =\n\t\t\t\t\t\tvlan_strip;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Enable/disable stats. */\n\t\t\tif (!strncmp(long_option[option_index].name, \"stats\", MAX_LONG_OPT_SZ)) {\n\t\t\t\tret = parse_num_opt(optarg, INT32_MAX);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG, \"Invalid argument for stats [0..N]\\n\");\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else {\n\t\t\t\t\tenable_stats = ret;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Set character device basename. */\n\t\t\tif (!strncmp(long_option[option_index].name, \"dev-basename\", MAX_LONG_OPT_SZ)) {\n\t\t\t\tif (us_vhost_parse_basename(optarg) == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG, \"Invalid argument for character device basename (Max %d characters)\\n\", MAX_BASENAME_SZ);\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Enable/disable rx/tx zero copy. */\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\t\"zero-copy\", MAX_LONG_OPT_SZ)) {\n\t\t\t\tret = parse_num_opt(optarg, 1);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\t\"Invalid argument\"\n\t\t\t\t\t\t\" for zero-copy [0|1]\\n\");\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else\n\t\t\t\t\tzero_copy = ret;\n\t\t\t}\n\n\t\t\t/* Specify the descriptor number on RX. */\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\t\"rx-desc-num\", MAX_LONG_OPT_SZ)) {\n\t\t\t\tret = parse_num_opt(optarg, MAX_RING_DESC);\n\t\t\t\tif ((ret == -1) || (!POWEROF2(ret))) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\"Invalid argument for rx-desc-num[0-N],\"\n\t\t\t\t\t\"power of 2 required.\\n\");\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else {\n\t\t\t\t\tnum_rx_descriptor = ret;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Specify the descriptor number on TX. */\n\t\t\tif (!strncmp(long_option[option_index].name,\n\t\t\t\t\"tx-desc-num\", MAX_LONG_OPT_SZ)) {\n\t\t\t\tret = parse_num_opt(optarg, MAX_RING_DESC);\n\t\t\t\tif ((ret == -1) || (!POWEROF2(ret))) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\t\t\"Invalid argument for tx-desc-num [0-N],\"\n\t\t\t\t\t\"power of 2 required.\\n\");\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else {\n\t\t\t\t\tnum_tx_descriptor = ret;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tbreak;\n\n\t\t\t/* Invalid option - print options. */\n\t\tdefault:\n\t\t\tus_vhost_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif (enabled_port_mask & (1 << i))\n\t\t\tports[num_ports++] = (uint8_t)i;\n\t}\n\n\tif ((num_ports == 0) || (num_ports > MAX_SUP_PORTS)) {\n\t\tRTE_LOG(INFO, VHOST_PORT, \"Current enabled port number is %u,\"\n\t\t\t\"but only %u port can be enabled\\n\",num_ports, MAX_SUP_PORTS);\n\t\treturn -1;\n\t}\n\n\tif ((zero_copy == 1) && (vm2vm_mode == VM2VM_SOFTWARE)) {\n\t\tRTE_LOG(INFO, VHOST_PORT,\n\t\t\t\"Vhost zero copy doesn't support software vm2vm,\"\n\t\t\t\"please specify 'vm2vm 2' to use hardware vm2vm.\\n\");\n\t\treturn -1;\n\t}\n\n\tif ((zero_copy == 1) && (vmdq_conf_default.rxmode.jumbo_frame == 1)) {\n\t\tRTE_LOG(INFO, VHOST_PORT,\n\t\t\t\"Vhost zero copy doesn't support jumbo frame,\"\n\t\t\t\"please specify '--mergeable 0' to disable the \"\n\t\t\t\"mergeable feature.\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Update the global var NUM_PORTS and array PORTS according to system ports number\n * and return valid ports number\n */\nstatic unsigned check_ports_num(unsigned nb_ports)\n{\n\tunsigned valid_num_ports = num_ports;\n\tunsigned portid;\n\n\tif (num_ports > nb_ports) {\n\t\tRTE_LOG(INFO, VHOST_PORT, \"\\nSpecified port number(%u) exceeds total system port number(%u)\\n\",\n\t\t\tnum_ports, nb_ports);\n\t\tnum_ports = nb_ports;\n\t}\n\n\tfor (portid = 0; portid < num_ports; portid ++) {\n\t\tif (ports[portid] >= nb_ports) {\n\t\t\tRTE_LOG(INFO, VHOST_PORT, \"\\nSpecified port ID(%u) exceeds max system port ID(%u)\\n\",\n\t\t\t\tports[portid], (nb_ports - 1));\n\t\t\tports[portid] = INVALID_PORT_ID;\n\t\t\tvalid_num_ports--;\n\t\t}\n\t}\n\treturn valid_num_ports;\n}\n\n/*\n * Macro to print out packet contents. Wrapped in debug define so that the\n * data path is not effected when debug is disabled.\n */\n#ifdef DEBUG\n#define PRINT_PACKET(device, addr, size, header) do {\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tchar *pkt_addr = (char*)(addr);\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tunsigned int index;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tchar packet[MAX_PRINT_BUFF];\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif ((header))\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tsnprintf(packet, MAX_PRINT_BUFF, \"(%\"PRIu64\") Header size %d: \", (device->device_fh), (size));\t\t\t\t\\\n\telse\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tsnprintf(packet, MAX_PRINT_BUFF, \"(%\"PRIu64\") Packet size %d: \", (device->device_fh), (size));\t\t\t\t\\\n\tfor (index = 0; index < (size); index++) {\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tsnprintf(packet + strnlen(packet, MAX_PRINT_BUFF), MAX_PRINT_BUFF - strnlen(packet, MAX_PRINT_BUFF),\t\\\n\t\t\t\"%02hhx \", pkt_addr[index]);\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tsnprintf(packet + strnlen(packet, MAX_PRINT_BUFF), MAX_PRINT_BUFF - strnlen(packet, MAX_PRINT_BUFF), \"\\n\");\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tLOG_DEBUG(VHOST_DATA, \"%s\", packet);\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n} while(0)\n#else\n#define PRINT_PACKET(device, addr, size, header) do{} while(0)\n#endif\n\n/*\n * Function to convert guest physical addresses to vhost physical addresses.\n * This is used to convert virtio buffer addresses.\n */\nstatic inline uint64_t __attribute__((always_inline))\ngpa_to_hpa(struct vhost_dev *vdev, uint64_t guest_pa,\n\tuint32_t buf_len, hpa_type *addr_type)\n{\n\tstruct virtio_memory_regions_hpa *region;\n\tuint32_t regionidx;\n\tuint64_t vhost_pa = 0;\n\n\t*addr_type = PHYS_ADDR_INVALID;\n\n\tfor (regionidx = 0; regionidx < vdev->nregions_hpa; regionidx++) {\n\t\tregion = &vdev->regions_hpa[regionidx];\n\t\tif ((guest_pa >= region->guest_phys_address) &&\n\t\t\t(guest_pa <= region->guest_phys_address_end)) {\n\t\t\tvhost_pa = region->host_phys_addr_offset + guest_pa;\n\t\t\tif (likely((guest_pa + buf_len - 1)\n\t\t\t\t<= region->guest_phys_address_end))\n\t\t\t\t*addr_type = PHYS_ADDR_CONTINUOUS;\n\t\t\telse\n\t\t\t\t*addr_type = PHYS_ADDR_CROSS_SUBREG;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") GPA %p| HPA %p\\n\",\n\t\tvdev->dev->device_fh, (void *)(uintptr_t)guest_pa,\n\t\t(void *)(uintptr_t)vhost_pa);\n\n\treturn vhost_pa;\n}\n\n/*\n * Compares a packet destination MAC address to a device MAC address.\n */\nstatic inline int __attribute__((always_inline))\nether_addr_cmp(struct ether_addr *ea, struct ether_addr *eb)\n{\n\treturn (((*(uint64_t *)ea ^ *(uint64_t *)eb) & MAC_ADDR_CMP) == 0);\n}\n\n/*\n * This function learns the MAC address of the device and registers this along with a\n * vlan tag to a VMDQ.\n */\nstatic int\nlink_vmdq(struct vhost_dev *vdev, struct rte_mbuf *m)\n{\n\tstruct ether_hdr *pkt_hdr;\n\tstruct virtio_net_data_ll *dev_ll;\n\tstruct virtio_net *dev = vdev->dev;\n\tint i, ret;\n\n\t/* Learn MAC address of guest device from packet */\n\tpkt_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\tdev_ll = ll_root_used;\n\n\twhile (dev_ll != NULL) {\n\t\tif (ether_addr_cmp(&(pkt_hdr->s_addr), &dev_ll->vdev->mac_address)) {\n\t\t\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") WARNING: This device is using an existing MAC address and has not been registered.\\n\", dev->device_fh);\n\t\t\treturn -1;\n\t\t}\n\t\tdev_ll = dev_ll->next;\n\t}\n\n\tfor (i = 0; i < ETHER_ADDR_LEN; i++)\n\t\tvdev->mac_address.addr_bytes[i] = pkt_hdr->s_addr.addr_bytes[i];\n\n\t/* vlan_tag currently uses the device_id. */\n\tvdev->vlan_tag = vlan_tags[dev->device_fh];\n\n\t/* Print out VMDQ registration info. */\n\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") MAC_ADDRESS %02x:%02x:%02x:%02x:%02x:%02x and VLAN_TAG %d registered\\n\",\n\t\tdev->device_fh,\n\t\tvdev->mac_address.addr_bytes[0], vdev->mac_address.addr_bytes[1],\n\t\tvdev->mac_address.addr_bytes[2], vdev->mac_address.addr_bytes[3],\n\t\tvdev->mac_address.addr_bytes[4], vdev->mac_address.addr_bytes[5],\n\t\tvdev->vlan_tag);\n\n\t/* Register the MAC address. */\n\tret = rte_eth_dev_mac_addr_add(ports[0], &vdev->mac_address,\n\t\t\t\t(uint32_t)dev->device_fh + vmdq_pool_base);\n\tif (ret)\n\t\tRTE_LOG(ERR, VHOST_DATA, \"(%\"PRIu64\") Failed to add device MAC address to VMDQ\\n\",\n\t\t\t\t\tdev->device_fh);\n\n\t/* Enable stripping of the vlan tag as we handle routing. */\n\tif (vlan_strip)\n\t\trte_eth_dev_set_vlan_strip_on_queue(ports[0],\n\t\t\t(uint16_t)vdev->vmdq_rx_q, 1);\n\n\t/* Set device as ready for RX. */\n\tvdev->ready = DEVICE_RX;\n\n\treturn 0;\n}\n\n/*\n * Removes MAC address and vlan tag from VMDQ. Ensures that nothing is adding buffers to the RX\n * queue before disabling RX on the device.\n */\nstatic inline void\nunlink_vmdq(struct vhost_dev *vdev)\n{\n\tunsigned i = 0;\n\tunsigned rx_count;\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\n\tif (vdev->ready == DEVICE_RX) {\n\t\t/*clear MAC and VLAN settings*/\n\t\trte_eth_dev_mac_addr_remove(ports[0], &vdev->mac_address);\n\t\tfor (i = 0; i < 6; i++)\n\t\t\tvdev->mac_address.addr_bytes[i] = 0;\n\n\t\tvdev->vlan_tag = 0;\n\n\t\t/*Clear out the receive buffers*/\n\t\trx_count = rte_eth_rx_burst(ports[0],\n\t\t\t\t\t(uint16_t)vdev->vmdq_rx_q, pkts_burst, MAX_PKT_BURST);\n\n\t\twhile (rx_count) {\n\t\t\tfor (i = 0; i < rx_count; i++)\n\t\t\t\trte_pktmbuf_free(pkts_burst[i]);\n\n\t\t\trx_count = rte_eth_rx_burst(ports[0],\n\t\t\t\t\t(uint16_t)vdev->vmdq_rx_q, pkts_burst, MAX_PKT_BURST);\n\t\t}\n\n\t\tvdev->ready = DEVICE_MAC_LEARNING;\n\t}\n}\n\n/*\n * Check if the packet destination MAC address is for a local device. If so then put\n * the packet on that devices RX queue. If not then return.\n */\nstatic inline int __attribute__((always_inline))\nvirtio_tx_local(struct vhost_dev *vdev, struct rte_mbuf *m)\n{\n\tstruct virtio_net_data_ll *dev_ll;\n\tstruct ether_hdr *pkt_hdr;\n\tuint64_t ret = 0;\n\tstruct virtio_net *dev = vdev->dev;\n\tstruct virtio_net *tdev; /* destination virito device */\n\n\tpkt_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\t/*get the used devices list*/\n\tdev_ll = ll_root_used;\n\n\twhile (dev_ll != NULL) {\n\t\tif ((dev_ll->vdev->ready == DEVICE_RX) && ether_addr_cmp(&(pkt_hdr->d_addr),\n\t\t\t\t &dev_ll->vdev->mac_address)) {\n\n\t\t\t/* Drop the packet if the TX packet is destined for the TX device. */\n\t\t\tif (dev_ll->vdev->dev->device_fh == dev->device_fh) {\n\t\t\t\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") TX: Source and destination MAC addresses are the same. Dropping packet.\\n\",\n\t\t\t\t\t\t\tdev->device_fh);\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t\ttdev = dev_ll->vdev->dev;\n\n\n\t\t\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") TX: MAC address is local\\n\", tdev->device_fh);\n\n\t\t\tif (unlikely(dev_ll->vdev->remove)) {\n\t\t\t\t/*drop the packet if the device is marked for removal*/\n\t\t\t\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") Device is marked for removal\\n\", tdev->device_fh);\n\t\t\t} else {\n\t\t\t\t/*send the packet to the local virtio device*/\n\t\t\t\tret = rte_vhost_enqueue_burst(tdev, VIRTIO_RXQ, &m, 1);\n\t\t\t\tif (enable_stats) {\n\t\t\t\t\trte_atomic64_add(\n\t\t\t\t\t&dev_statistics[tdev->device_fh].rx_total_atomic,\n\t\t\t\t\t1);\n\t\t\t\t\trte_atomic64_add(\n\t\t\t\t\t&dev_statistics[tdev->device_fh].rx_atomic,\n\t\t\t\t\tret);\n\t\t\t\t\tdev_statistics[tdev->device_fh].tx_total++;\n\t\t\t\t\tdev_statistics[tdev->device_fh].tx += ret;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\treturn 0;\n\t\t}\n\t\tdev_ll = dev_ll->next;\n\t}\n\n\treturn -1;\n}\n\n/*\n * Check if the destination MAC of a packet is one local VM,\n * and get its vlan tag, and offset if it is.\n */\nstatic inline int __attribute__((always_inline))\nfind_local_dest(struct virtio_net *dev, struct rte_mbuf *m,\n\tuint32_t *offset, uint16_t *vlan_tag)\n{\n\tstruct virtio_net_data_ll *dev_ll = ll_root_used;\n\tstruct ether_hdr *pkt_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\twhile (dev_ll != NULL) {\n\t\tif ((dev_ll->vdev->ready == DEVICE_RX)\n\t\t\t&& ether_addr_cmp(&(pkt_hdr->d_addr),\n\t\t&dev_ll->vdev->mac_address)) {\n\t\t\t/*\n\t\t\t * Drop the packet if the TX packet is\n\t\t\t * destined for the TX device.\n\t\t\t */\n\t\t\tif (dev_ll->vdev->dev->device_fh == dev->device_fh) {\n\t\t\t\tLOG_DEBUG(VHOST_DATA,\n\t\t\t\t\"(%\"PRIu64\") TX: Source and destination\"\n\t\t\t\t\" MAC addresses are the same. Dropping \"\n\t\t\t\t\"packet.\\n\",\n\t\t\t\tdev_ll->vdev->dev->device_fh);\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * HW vlan strip will reduce the packet length\n\t\t\t * by minus length of vlan tag, so need restore\n\t\t\t * the packet length by plus it.\n\t\t\t */\n\t\t\t*offset = VLAN_HLEN;\n\t\t\t*vlan_tag =\n\t\t\t(uint16_t)\n\t\t\tvlan_tags[(uint16_t)dev_ll->vdev->dev->device_fh];\n\n\t\t\tLOG_DEBUG(VHOST_DATA,\n\t\t\t\"(%\"PRIu64\") TX: pkt to local VM device id:\"\n\t\t\t\"(%\"PRIu64\") vlan tag: %d.\\n\",\n\t\t\tdev->device_fh, dev_ll->vdev->dev->device_fh,\n\t\t\t(int)*vlan_tag);\n\n\t\t\tbreak;\n\t\t}\n\t\tdev_ll = dev_ll->next;\n\t}\n\treturn 0;\n}\n\n/*\n * This function routes the TX packet to the correct interface. This may be a local device\n * or the physical port.\n */\nstatic inline void __attribute__((always_inline))\nvirtio_tx_route(struct vhost_dev *vdev, struct rte_mbuf *m, uint16_t vlan_tag)\n{\n\tstruct mbuf_table *tx_q;\n\tstruct rte_mbuf **m_table;\n\tunsigned len, ret, offset = 0;\n\tconst uint16_t lcore_id = rte_lcore_id();\n\tstruct virtio_net *dev = vdev->dev;\n\tstruct ether_hdr *nh;\n\n\t/*check if destination is local VM*/\n\tif ((vm2vm_mode == VM2VM_SOFTWARE) && (virtio_tx_local(vdev, m) == 0)) {\n\t\trte_pktmbuf_free(m);\n\t\treturn;\n\t}\n\n\tif (unlikely(vm2vm_mode == VM2VM_HARDWARE)) {\n\t\tif (unlikely(find_local_dest(dev, m, &offset, &vlan_tag) != 0)) {\n\t\t\trte_pktmbuf_free(m);\n\t\t\treturn;\n\t\t}\n\t}\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") TX: MAC address is external\\n\", dev->device_fh);\n\n\t/*Add packet to the port tx queue*/\n\ttx_q = &lcore_tx_queue[lcore_id];\n\tlen = tx_q->len;\n\n\tnh = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\tif (unlikely(nh->ether_type == rte_cpu_to_be_16(ETHER_TYPE_VLAN))) {\n\t\t/* Guest has inserted the vlan tag. */\n\t\tstruct vlan_hdr *vh = (struct vlan_hdr *) (nh + 1);\n\t\tuint16_t vlan_tag_be = rte_cpu_to_be_16(vlan_tag);\n\t\tif ((vm2vm_mode == VM2VM_HARDWARE) &&\n\t\t\t(vh->vlan_tci != vlan_tag_be))\n\t\t\tvh->vlan_tci = vlan_tag_be;\n\t} else {\n\t\tm->ol_flags = PKT_TX_VLAN_PKT;\n\n\t\t/*\n\t\t * Find the right seg to adjust the data len when offset is\n\t\t * bigger than tail room size.\n\t\t */\n\t\tif (unlikely(vm2vm_mode == VM2VM_HARDWARE)) {\n\t\t\tif (likely(offset <= rte_pktmbuf_tailroom(m)))\n\t\t\t\tm->data_len += offset;\n\t\t\telse {\n\t\t\t\tstruct rte_mbuf *seg = m;\n\n\t\t\t\twhile ((seg->next != NULL) &&\n\t\t\t\t\t(offset > rte_pktmbuf_tailroom(seg)))\n\t\t\t\t\tseg = seg->next;\n\n\t\t\t\tseg->data_len += offset;\n\t\t\t}\n\t\t\tm->pkt_len += offset;\n\t\t}\n\n\t\tm->vlan_tci = vlan_tag;\n\t}\n\n\ttx_q->m_table[len] = m;\n\tlen++;\n\tif (enable_stats) {\n\t\tdev_statistics[dev->device_fh].tx_total++;\n\t\tdev_statistics[dev->device_fh].tx++;\n\t}\n\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tm_table = (struct rte_mbuf **)tx_q->m_table;\n\t\tret = rte_eth_tx_burst(ports[0], (uint16_t)tx_q->txq_id, m_table, (uint16_t) len);\n\t\t/* Free any buffers not handled by TX and update the port stats. */\n\t\tif (unlikely(ret < len)) {\n\t\t\tdo {\n\t\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t\t} while (++ret < len);\n\t\t}\n\n\t\tlen = 0;\n\t}\n\n\ttx_q->len = len;\n\treturn;\n}\n/*\n * This function is called by each data core. It handles all RX/TX registered with the\n * core. For TX the specific lcore linked list is used. For RX, MAC addresses are compared\n * with all devices in the main linked list.\n */\nstatic int\nswitch_worker(__attribute__((unused)) void *arg)\n{\n\tstruct rte_mempool *mbuf_pool = arg;\n\tstruct virtio_net *dev = NULL;\n\tstruct vhost_dev *vdev = NULL;\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct virtio_net_data_ll *dev_ll;\n\tstruct mbuf_table *tx_q;\n\tvolatile struct lcore_ll_info *lcore_ll;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc, ret_count = 0;\n\tunsigned ret, i;\n\tconst uint16_t lcore_id = rte_lcore_id();\n\tconst uint16_t num_cores = (uint16_t)rte_lcore_count();\n\tuint16_t rx_count = 0;\n\tuint16_t tx_count;\n\tuint32_t retry = 0;\n\n\tRTE_LOG(INFO, VHOST_DATA, \"Procesing on Core %u started\\n\", lcore_id);\n\tlcore_ll = lcore_info[lcore_id].lcore_ll;\n\tprev_tsc = 0;\n\n\ttx_q = &lcore_tx_queue[lcore_id];\n\tfor (i = 0; i < num_cores; i ++) {\n\t\tif (lcore_ids[i] == lcore_id) {\n\t\t\ttx_q->txq_id = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\twhile(1) {\n\t\tcur_tsc = rte_rdtsc();\n\t\t/*\n\t\t * TX burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\tif (tx_q->len) {\n\t\t\t\tLOG_DEBUG(VHOST_DATA, \"TX queue drained after timeout with burst size %u \\n\", tx_q->len);\n\n\t\t\t\t/*Tx any packets in the queue*/\n\t\t\t\tret = rte_eth_tx_burst(ports[0], (uint16_t)tx_q->txq_id,\n\t\t\t\t\t\t\t\t\t (struct rte_mbuf **)tx_q->m_table,\n\t\t\t\t\t\t\t\t\t (uint16_t)tx_q->len);\n\t\t\t\tif (unlikely(ret < tx_q->len)) {\n\t\t\t\t\tdo {\n\t\t\t\t\t\trte_pktmbuf_free(tx_q->m_table[ret]);\n\t\t\t\t\t} while (++ret < tx_q->len);\n\t\t\t\t}\n\n\t\t\t\ttx_q->len = 0;\n\t\t\t}\n\n\t\t\tprev_tsc = cur_tsc;\n\n\t\t}\n\n\t\trte_prefetch0(lcore_ll->ll_root_used);\n\t\t/*\n\t\t * Inform the configuration core that we have exited the linked list and that no devices are\n\t\t * in use if requested.\n\t\t */\n\t\tif (lcore_ll->dev_removal_flag == REQUEST_DEV_REMOVAL)\n\t\t\tlcore_ll->dev_removal_flag = ACK_DEV_REMOVAL;\n\n\t\t/*\n\t\t * Process devices\n\t\t */\n\t\tdev_ll = lcore_ll->ll_root_used;\n\n\t\twhile (dev_ll != NULL) {\n\t\t\t/*get virtio device ID*/\n\t\t\tvdev = dev_ll->vdev;\n\t\t\tdev = vdev->dev;\n\n\t\t\tif (unlikely(vdev->remove)) {\n\t\t\t\tdev_ll = dev_ll->next;\n\t\t\t\tunlink_vmdq(vdev);\n\t\t\t\tvdev->ready = DEVICE_SAFE_REMOVE;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (likely(vdev->ready == DEVICE_RX)) {\n\t\t\t\t/*Handle guest RX*/\n\t\t\t\trx_count = rte_eth_rx_burst(ports[0],\n\t\t\t\t\tvdev->vmdq_rx_q, pkts_burst, MAX_PKT_BURST);\n\n\t\t\t\tif (rx_count) {\n\t\t\t\t\t/*\n\t\t\t\t\t* Retry is enabled and the queue is full then we wait and retry to avoid packet loss\n\t\t\t\t\t* Here MAX_PKT_BURST must be less than virtio queue size\n\t\t\t\t\t*/\n\t\t\t\t\tif (enable_retry && unlikely(rx_count > rte_vring_available_entries(dev, VIRTIO_RXQ))) {\n\t\t\t\t\t\tfor (retry = 0; retry < burst_rx_retry_num; retry++) {\n\t\t\t\t\t\t\trte_delay_us(burst_rx_delay_time);\n\t\t\t\t\t\t\tif (rx_count <= rte_vring_available_entries(dev, VIRTIO_RXQ))\n\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\tret_count = rte_vhost_enqueue_burst(dev, VIRTIO_RXQ, pkts_burst, rx_count);\n\t\t\t\t\tif (enable_stats) {\n\t\t\t\t\t\trte_atomic64_add(\n\t\t\t\t\t\t&dev_statistics[dev_ll->vdev->dev->device_fh].rx_total_atomic,\n\t\t\t\t\t\trx_count);\n\t\t\t\t\t\trte_atomic64_add(\n\t\t\t\t\t\t&dev_statistics[dev_ll->vdev->dev->device_fh].rx_atomic, ret_count);\n\t\t\t\t\t}\n\t\t\t\t\twhile (likely(rx_count)) {\n\t\t\t\t\t\trx_count--;\n\t\t\t\t\t\trte_pktmbuf_free(pkts_burst[rx_count]);\n\t\t\t\t\t}\n\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (likely(!vdev->remove)) {\n\t\t\t\t/* Handle guest TX*/\n\t\t\t\ttx_count = rte_vhost_dequeue_burst(dev, VIRTIO_TXQ, mbuf_pool, pkts_burst, MAX_PKT_BURST);\n\t\t\t\t/* If this is the first received packet we need to learn the MAC and setup VMDQ */\n\t\t\t\tif (unlikely(vdev->ready == DEVICE_MAC_LEARNING) && tx_count) {\n\t\t\t\t\tif (vdev->remove || (link_vmdq(vdev, pkts_burst[0]) == -1)) {\n\t\t\t\t\t\twhile (tx_count)\n\t\t\t\t\t\t\trte_pktmbuf_free(pkts_burst[--tx_count]);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\twhile (tx_count)\n\t\t\t\t\tvirtio_tx_route(vdev, pkts_burst[--tx_count], (uint16_t)dev->device_fh);\n\t\t\t}\n\n\t\t\t/*move to the next device in the list*/\n\t\t\tdev_ll = dev_ll->next;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/*\n * This function gets available ring number for zero copy rx.\n * Only one thread will call this funciton for a paticular virtio device,\n * so, it is designed as non-thread-safe function.\n */\nstatic inline uint32_t __attribute__((always_inline))\nget_available_ring_num_zcp(struct virtio_net *dev)\n{\n\tstruct vhost_virtqueue *vq = dev->virtqueue[VIRTIO_RXQ];\n\tuint16_t avail_idx;\n\n\tavail_idx = *((volatile uint16_t *)&vq->avail->idx);\n\treturn (uint32_t)(avail_idx - vq->last_used_idx_res);\n}\n\n/*\n * This function gets available ring index for zero copy rx,\n * it will retry 'burst_rx_retry_num' times till it get enough ring index.\n * Only one thread will call this funciton for a paticular virtio device,\n * so, it is designed as non-thread-safe function.\n */\nstatic inline uint32_t __attribute__((always_inline))\nget_available_ring_index_zcp(struct virtio_net *dev,\n\tuint16_t *res_base_idx, uint32_t count)\n{\n\tstruct vhost_virtqueue *vq = dev->virtqueue[VIRTIO_RXQ];\n\tuint16_t avail_idx;\n\tuint32_t retry = 0;\n\tuint16_t free_entries;\n\n\t*res_base_idx = vq->last_used_idx_res;\n\tavail_idx = *((volatile uint16_t *)&vq->avail->idx);\n\tfree_entries = (avail_idx - *res_base_idx);\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") in get_available_ring_index_zcp: \"\n\t\t\t\"avail idx: %d, \"\n\t\t\t\"res base idx:%d, free entries:%d\\n\",\n\t\t\tdev->device_fh, avail_idx, *res_base_idx,\n\t\t\tfree_entries);\n\n\t/*\n\t * If retry is enabled and the queue is full then we wait\n\t * and retry to avoid packet loss.\n\t */\n\tif (enable_retry && unlikely(count > free_entries)) {\n\t\tfor (retry = 0; retry < burst_rx_retry_num; retry++) {\n\t\t\trte_delay_us(burst_rx_delay_time);\n\t\t\tavail_idx = *((volatile uint16_t *)&vq->avail->idx);\n\t\t\tfree_entries = (avail_idx - *res_base_idx);\n\t\t\tif (count <= free_entries)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\t/*check that we have enough buffers*/\n\tif (unlikely(count > free_entries))\n\t\tcount = free_entries;\n\n\tif (unlikely(count == 0)) {\n\t\tLOG_DEBUG(VHOST_DATA,\n\t\t\t\"(%\"PRIu64\") Fail in get_available_ring_index_zcp: \"\n\t\t\t\"avail idx: %d, res base idx:%d, free entries:%d\\n\",\n\t\t\tdev->device_fh, avail_idx,\n\t\t\t*res_base_idx, free_entries);\n\t\treturn 0;\n\t}\n\n\tvq->last_used_idx_res = *res_base_idx + count;\n\n\treturn count;\n}\n\n/*\n * This function put descriptor back to used list.\n */\nstatic inline void __attribute__((always_inline))\nput_desc_to_used_list_zcp(struct vhost_virtqueue *vq, uint16_t desc_idx)\n{\n\tuint16_t res_cur_idx = vq->last_used_idx;\n\tvq->used->ring[res_cur_idx & (vq->size - 1)].id = (uint32_t)desc_idx;\n\tvq->used->ring[res_cur_idx & (vq->size - 1)].len = 0;\n\trte_compiler_barrier();\n\t*(volatile uint16_t *)&vq->used->idx += 1;\n\tvq->last_used_idx += 1;\n\n\t/* Kick the guest if necessary. */\n\tif (!(vq->avail->flags & VRING_AVAIL_F_NO_INTERRUPT))\n\t\teventfd_write((int)vq->callfd, 1);\n}\n\n/*\n * This function get available descriptor from vitio vring and un-attached mbuf\n * from vpool->ring, and then attach them together. It needs adjust the offset\n * for buff_addr and phys_addr accroding to PMD implementation, otherwise the\n * frame data may be put to wrong location in mbuf.\n */\nstatic inline void __attribute__((always_inline))\nattach_rxmbuf_zcp(struct virtio_net *dev)\n{\n\tuint16_t res_base_idx, desc_idx;\n\tuint64_t buff_addr, phys_addr;\n\tstruct vhost_virtqueue *vq;\n\tstruct vring_desc *desc;\n\tstruct rte_mbuf *mbuf = NULL;\n\tstruct vpool *vpool;\n\thpa_type addr_type;\n\tstruct vhost_dev *vdev = (struct vhost_dev *)dev->priv;\n\n\tvpool = &vpool_array[vdev->vmdq_rx_q];\n\tvq = dev->virtqueue[VIRTIO_RXQ];\n\n\tdo {\n\t\tif (unlikely(get_available_ring_index_zcp(vdev->dev, &res_base_idx,\n\t\t\t\t1) != 1))\n\t\t\treturn;\n\t\tdesc_idx = vq->avail->ring[(res_base_idx) & (vq->size - 1)];\n\n\t\tdesc = &vq->desc[desc_idx];\n\t\tif (desc->flags & VRING_DESC_F_NEXT) {\n\t\t\tdesc = &vq->desc[desc->next];\n\t\t\tbuff_addr = gpa_to_vva(dev, desc->addr);\n\t\t\tphys_addr = gpa_to_hpa(vdev, desc->addr, desc->len,\n\t\t\t\t\t&addr_type);\n\t\t} else {\n\t\t\tbuff_addr = gpa_to_vva(dev,\n\t\t\t\t\tdesc->addr + vq->vhost_hlen);\n\t\t\tphys_addr = gpa_to_hpa(vdev,\n\t\t\t\t\tdesc->addr + vq->vhost_hlen,\n\t\t\t\t\tdesc->len, &addr_type);\n\t\t}\n\n\t\tif (unlikely(addr_type == PHYS_ADDR_INVALID)) {\n\t\t\tRTE_LOG(ERR, VHOST_DATA, \"(%\"PRIu64\") Invalid frame buffer\"\n\t\t\t\t\" address found when attaching RX frame buffer\"\n\t\t\t\t\" address!\\n\", dev->device_fh);\n\t\t\tput_desc_to_used_list_zcp(vq, desc_idx);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/*\n\t\t * Check if the frame buffer address from guest crosses\n\t\t * sub-region or not.\n\t\t */\n\t\tif (unlikely(addr_type == PHYS_ADDR_CROSS_SUBREG)) {\n\t\t\tRTE_LOG(ERR, VHOST_DATA,\n\t\t\t\t\"(%\"PRIu64\") Frame buffer address cross \"\n\t\t\t\t\"sub-regioin found when attaching RX frame \"\n\t\t\t\t\"buffer address!\\n\",\n\t\t\t\tdev->device_fh);\n\t\t\tput_desc_to_used_list_zcp(vq, desc_idx);\n\t\t\tcontinue;\n\t\t}\n\t} while (unlikely(phys_addr == 0));\n\n\trte_ring_sc_dequeue(vpool->ring, (void **)&mbuf);\n\tif (unlikely(mbuf == NULL)) {\n\t\tLOG_DEBUG(VHOST_DATA,\n\t\t\t\"(%\"PRIu64\") in attach_rxmbuf_zcp: \"\n\t\t\t\"ring_sc_dequeue fail.\\n\",\n\t\t\tdev->device_fh);\n\t\tput_desc_to_used_list_zcp(vq, desc_idx);\n\t\treturn;\n\t}\n\n\tif (unlikely(vpool->buf_size > desc->len)) {\n\t\tLOG_DEBUG(VHOST_DATA,\n\t\t\t\"(%\"PRIu64\") in attach_rxmbuf_zcp: frame buffer \"\n\t\t\t\"length(%d) of descriptor idx: %d less than room \"\n\t\t\t\"size required: %d\\n\",\n\t\t\tdev->device_fh, desc->len, desc_idx, vpool->buf_size);\n\t\tput_desc_to_used_list_zcp(vq, desc_idx);\n\t\trte_ring_sp_enqueue(vpool->ring, (void *)mbuf);\n\t\treturn;\n\t}\n\n\tmbuf->buf_addr = (void *)(uintptr_t)(buff_addr - RTE_PKTMBUF_HEADROOM);\n\tmbuf->data_off = RTE_PKTMBUF_HEADROOM;\n\tmbuf->buf_physaddr = phys_addr - RTE_PKTMBUF_HEADROOM;\n\tmbuf->data_len = desc->len;\n\tMBUF_HEADROOM_UINT32(mbuf) = (uint32_t)desc_idx;\n\n\tLOG_DEBUG(VHOST_DATA,\n\t\t\"(%\"PRIu64\") in attach_rxmbuf_zcp: res base idx:%d, \"\n\t\t\"descriptor idx:%d\\n\",\n\t\tdev->device_fh, res_base_idx, desc_idx);\n\n\t__rte_mbuf_raw_free(mbuf);\n\n\treturn;\n}\n\n/*\n * Detach an attched packet mbuf -\n * - restore original mbuf address and length values.\n * - reset pktmbuf data and data_len to their default values.\n * All other fields of the given packet mbuf will be left intact.\n *\n * @param m\n * The attached packet mbuf.\n */\nstatic inline void pktmbuf_detach_zcp(struct rte_mbuf *m)\n{\n\tconst struct rte_mempool *mp = m->pool;\n\tvoid *buf = rte_mbuf_to_baddr(m);\n\tuint32_t buf_ofs;\n\tuint32_t buf_len = mp->elt_size - sizeof(*m);\n\tm->buf_physaddr = rte_mempool_virt2phy(mp, m) + sizeof(*m);\n\n\tm->buf_addr = buf;\n\tm->buf_len = (uint16_t)buf_len;\n\n\tbuf_ofs = (RTE_PKTMBUF_HEADROOM <= m->buf_len) ?\n\t\t\tRTE_PKTMBUF_HEADROOM : m->buf_len;\n\tm->data_off = buf_ofs;\n\n\tm->data_len = 0;\n}\n\n/*\n * This function is called after packets have been transimited. It fetchs mbuf\n * from vpool->pool, detached it and put into vpool->ring. It also update the\n * used index and kick the guest if necessary.\n */\nstatic inline uint32_t __attribute__((always_inline))\ntxmbuf_clean_zcp(struct virtio_net *dev, struct vpool *vpool)\n{\n\tstruct rte_mbuf *mbuf;\n\tstruct vhost_virtqueue *vq = dev->virtqueue[VIRTIO_TXQ];\n\tuint32_t used_idx = vq->last_used_idx & (vq->size - 1);\n\tuint32_t index = 0;\n\tuint32_t mbuf_count = rte_mempool_count(vpool->pool);\n\n\tLOG_DEBUG(VHOST_DATA,\n\t\t\"(%\"PRIu64\") in txmbuf_clean_zcp: mbuf count in mempool before \"\n\t\t\"clean is: %d\\n\",\n\t\tdev->device_fh, mbuf_count);\n\tLOG_DEBUG(VHOST_DATA,\n\t\t\"(%\"PRIu64\") in txmbuf_clean_zcp: mbuf count in ring before \"\n\t\t\"clean is : %d\\n\",\n\t\tdev->device_fh, rte_ring_count(vpool->ring));\n\n\tfor (index = 0; index < mbuf_count; index++) {\n\t\tmbuf = __rte_mbuf_raw_alloc(vpool->pool);\n\t\tif (likely(MBUF_EXT_MEM(mbuf)))\n\t\t\tpktmbuf_detach_zcp(mbuf);\n\t\trte_ring_sp_enqueue(vpool->ring, mbuf);\n\n\t\t/* Update used index buffer information. */\n\t\tvq->used->ring[used_idx].id = MBUF_HEADROOM_UINT32(mbuf);\n\t\tvq->used->ring[used_idx].len = 0;\n\n\t\tused_idx = (used_idx + 1) & (vq->size - 1);\n\t}\n\n\tLOG_DEBUG(VHOST_DATA,\n\t\t\"(%\"PRIu64\") in txmbuf_clean_zcp: mbuf count in mempool after \"\n\t\t\"clean is: %d\\n\",\n\t\tdev->device_fh, rte_mempool_count(vpool->pool));\n\tLOG_DEBUG(VHOST_DATA,\n\t\t\"(%\"PRIu64\") in txmbuf_clean_zcp: mbuf count in ring after \"\n\t\t\"clean is : %d\\n\",\n\t\tdev->device_fh, rte_ring_count(vpool->ring));\n\tLOG_DEBUG(VHOST_DATA,\n\t\t\"(%\"PRIu64\") in txmbuf_clean_zcp: before updated \"\n\t\t\"vq->last_used_idx:%d\\n\",\n\t\tdev->device_fh, vq->last_used_idx);\n\n\tvq->last_used_idx += mbuf_count;\n\n\tLOG_DEBUG(VHOST_DATA,\n\t\t\"(%\"PRIu64\") in txmbuf_clean_zcp: after updated \"\n\t\t\"vq->last_used_idx:%d\\n\",\n\t\tdev->device_fh, vq->last_used_idx);\n\n\trte_compiler_barrier();\n\n\t*(volatile uint16_t *)&vq->used->idx += mbuf_count;\n\n\t/* Kick guest if required. */\n\tif (!(vq->avail->flags & VRING_AVAIL_F_NO_INTERRUPT))\n\t\teventfd_write((int)vq->callfd, 1);\n\n\treturn 0;\n}\n\n/*\n * This function is called when a virtio device is destroy.\n * It fetchs mbuf from vpool->pool, and detached it, and put into vpool->ring.\n */\nstatic void mbuf_destroy_zcp(struct vpool *vpool)\n{\n\tstruct rte_mbuf *mbuf = NULL;\n\tuint32_t index, mbuf_count = rte_mempool_count(vpool->pool);\n\n\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\"in mbuf_destroy_zcp: mbuf count in mempool before \"\n\t\t\"mbuf_destroy_zcp is: %d\\n\",\n\t\tmbuf_count);\n\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\"in mbuf_destroy_zcp: mbuf count in ring before \"\n\t\t\"mbuf_destroy_zcp is : %d\\n\",\n\t\trte_ring_count(vpool->ring));\n\n\tfor (index = 0; index < mbuf_count; index++) {\n\t\tmbuf = __rte_mbuf_raw_alloc(vpool->pool);\n\t\tif (likely(mbuf != NULL)) {\n\t\t\tif (likely(MBUF_EXT_MEM(mbuf)))\n\t\t\t\tpktmbuf_detach_zcp(mbuf);\n\t\t\trte_ring_sp_enqueue(vpool->ring, (void *)mbuf);\n\t\t}\n\t}\n\n\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\"in mbuf_destroy_zcp: mbuf count in mempool after \"\n\t\t\"mbuf_destroy_zcp is: %d\\n\",\n\t\trte_mempool_count(vpool->pool));\n\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\"in mbuf_destroy_zcp: mbuf count in ring after \"\n\t\t\"mbuf_destroy_zcp is : %d\\n\",\n\t\trte_ring_count(vpool->ring));\n}\n\n/*\n * This function update the use flag and counter.\n */\nstatic inline uint32_t __attribute__((always_inline))\nvirtio_dev_rx_zcp(struct virtio_net *dev, struct rte_mbuf **pkts,\n\tuint32_t count)\n{\n\tstruct vhost_virtqueue *vq;\n\tstruct vring_desc *desc;\n\tstruct rte_mbuf *buff;\n\t/* The virtio_hdr is initialised to 0. */\n\tstruct virtio_net_hdr_mrg_rxbuf virtio_hdr\n\t\t= {{0, 0, 0, 0, 0, 0}, 0};\n\tuint64_t buff_hdr_addr = 0;\n\tuint32_t head[MAX_PKT_BURST], packet_len = 0;\n\tuint32_t head_idx, packet_success = 0;\n\tuint16_t res_cur_idx;\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") virtio_dev_rx()\\n\", dev->device_fh);\n\n\tif (count == 0)\n\t\treturn 0;\n\n\tvq = dev->virtqueue[VIRTIO_RXQ];\n\tcount = (count > MAX_PKT_BURST) ? MAX_PKT_BURST : count;\n\n\tres_cur_idx = vq->last_used_idx;\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") Current Index %d| End Index %d\\n\",\n\t\tdev->device_fh, res_cur_idx, res_cur_idx + count);\n\n\t/* Retrieve all of the head indexes first to avoid caching issues. */\n\tfor (head_idx = 0; head_idx < count; head_idx++)\n\t\thead[head_idx] = MBUF_HEADROOM_UINT32(pkts[head_idx]);\n\n\t/*Prefetch descriptor index. */\n\trte_prefetch0(&vq->desc[head[packet_success]]);\n\n\twhile (packet_success != count) {\n\t\t/* Get descriptor from available ring */\n\t\tdesc = &vq->desc[head[packet_success]];\n\n\t\tbuff = pkts[packet_success];\n\t\tLOG_DEBUG(VHOST_DATA,\n\t\t\t\"(%\"PRIu64\") in dev_rx_zcp: update the used idx for \"\n\t\t\t\"pkt[%d] descriptor idx: %d\\n\",\n\t\t\tdev->device_fh, packet_success,\n\t\t\tMBUF_HEADROOM_UINT32(buff));\n\n\t\tPRINT_PACKET(dev,\n\t\t\t(uintptr_t)(((uint64_t)(uintptr_t)buff->buf_addr)\n\t\t\t+ RTE_PKTMBUF_HEADROOM),\n\t\t\trte_pktmbuf_data_len(buff), 0);\n\n\t\t/* Buffer address translation for virtio header. */\n\t\tbuff_hdr_addr = gpa_to_vva(dev, desc->addr);\n\t\tpacket_len = rte_pktmbuf_data_len(buff) + vq->vhost_hlen;\n\n\t\t/*\n\t\t * If the descriptors are chained the header and data are\n\t\t * placed in separate buffers.\n\t\t */\n\t\tif (desc->flags & VRING_DESC_F_NEXT) {\n\t\t\tdesc->len = vq->vhost_hlen;\n\t\t\tdesc = &vq->desc[desc->next];\n\t\t\tdesc->len = rte_pktmbuf_data_len(buff);\n\t\t} else {\n\t\t\tdesc->len = packet_len;\n\t\t}\n\n\t\t/* Update used ring with desc information */\n\t\tvq->used->ring[res_cur_idx & (vq->size - 1)].id\n\t\t\t= head[packet_success];\n\t\tvq->used->ring[res_cur_idx & (vq->size - 1)].len\n\t\t\t= packet_len;\n\t\tres_cur_idx++;\n\t\tpacket_success++;\n\n\t\t/* A header is required per buffer. */\n\t\trte_memcpy((void *)(uintptr_t)buff_hdr_addr,\n\t\t\t(const void *)&virtio_hdr, vq->vhost_hlen);\n\n\t\tPRINT_PACKET(dev, (uintptr_t)buff_hdr_addr, vq->vhost_hlen, 1);\n\n\t\tif (likely(packet_success < count)) {\n\t\t\t/* Prefetch descriptor index. */\n\t\t\trte_prefetch0(&vq->desc[head[packet_success]]);\n\t\t}\n\t}\n\n\trte_compiler_barrier();\n\n\tLOG_DEBUG(VHOST_DATA,\n\t\t\"(%\"PRIu64\") in dev_rx_zcp: before update used idx: \"\n\t\t\"vq.last_used_idx: %d, vq->used->idx: %d\\n\",\n\t\tdev->device_fh, vq->last_used_idx, vq->used->idx);\n\n\t*(volatile uint16_t *)&vq->used->idx += count;\n\tvq->last_used_idx += count;\n\n\tLOG_DEBUG(VHOST_DATA,\n\t\t\"(%\"PRIu64\") in dev_rx_zcp: after update used idx: \"\n\t\t\"vq.last_used_idx: %d, vq->used->idx: %d\\n\",\n\t\tdev->device_fh, vq->last_used_idx, vq->used->idx);\n\n\t/* Kick the guest if necessary. */\n\tif (!(vq->avail->flags & VRING_AVAIL_F_NO_INTERRUPT))\n\t\teventfd_write((int)vq->callfd, 1);\n\n\treturn count;\n}\n\n/*\n * This function routes the TX packet to the correct interface.\n * This may be a local device or the physical port.\n */\nstatic inline void __attribute__((always_inline))\nvirtio_tx_route_zcp(struct virtio_net *dev, struct rte_mbuf *m,\n\tuint32_t desc_idx, uint8_t need_copy)\n{\n\tstruct mbuf_table *tx_q;\n\tstruct rte_mbuf **m_table;\n\tstruct rte_mbuf *mbuf = NULL;\n\tunsigned len, ret, offset = 0;\n\tstruct vpool *vpool;\n\tuint16_t vlan_tag = (uint16_t)vlan_tags[(uint16_t)dev->device_fh];\n\tuint16_t vmdq_rx_q = ((struct vhost_dev *)dev->priv)->vmdq_rx_q;\n\n\t/*Add packet to the port tx queue*/\n\ttx_q = &tx_queue_zcp[vmdq_rx_q];\n\tlen = tx_q->len;\n\n\t/* Allocate an mbuf and populate the structure. */\n\tvpool = &vpool_array[MAX_QUEUES + vmdq_rx_q];\n\trte_ring_sc_dequeue(vpool->ring, (void **)&mbuf);\n\tif (unlikely(mbuf == NULL)) {\n\t\tstruct vhost_virtqueue *vq = dev->virtqueue[VIRTIO_TXQ];\n\t\tRTE_LOG(ERR, VHOST_DATA,\n\t\t\t\"(%\"PRIu64\") Failed to allocate memory for mbuf.\\n\",\n\t\t\tdev->device_fh);\n\t\tput_desc_to_used_list_zcp(vq, desc_idx);\n\t\treturn;\n\t}\n\n\tif (vm2vm_mode == VM2VM_HARDWARE) {\n\t\t/* Avoid using a vlan tag from any vm for external pkt, such as\n\t\t * vlan_tags[dev->device_fh], oterwise, it conflicts when pool\n\t\t * selection, MAC address determines it as an external pkt\n\t\t * which should go to network, while vlan tag determine it as\n\t\t * a vm2vm pkt should forward to another vm. Hardware confuse\n\t\t * such a ambiguous situation, so pkt will lost.\n\t\t */\n\t\tvlan_tag = external_pkt_default_vlan_tag;\n\t\tif (find_local_dest(dev, m, &offset, &vlan_tag) != 0) {\n\t\t\tMBUF_HEADROOM_UINT32(mbuf) = (uint32_t)desc_idx;\n\t\t\t__rte_mbuf_raw_free(mbuf);\n\t\t\treturn;\n\t\t}\n\t}\n\n\tmbuf->nb_segs = m->nb_segs;\n\tmbuf->next = m->next;\n\tmbuf->data_len = m->data_len + offset;\n\tmbuf->pkt_len = mbuf->data_len;\n\tif (unlikely(need_copy)) {\n\t\t/* Copy the packet contents to the mbuf. */\n\t\trte_memcpy(rte_pktmbuf_mtod(mbuf, void *),\n\t\t\trte_pktmbuf_mtod(m, void *),\n\t\t\tm->data_len);\n\t} else {\n\t\tmbuf->data_off = m->data_off;\n\t\tmbuf->buf_physaddr = m->buf_physaddr;\n\t\tmbuf->buf_addr = m->buf_addr;\n\t}\n\tmbuf->ol_flags = PKT_TX_VLAN_PKT;\n\tmbuf->vlan_tci = vlan_tag;\n\tmbuf->l2_len = sizeof(struct ether_hdr);\n\tmbuf->l3_len = sizeof(struct ipv4_hdr);\n\tMBUF_HEADROOM_UINT32(mbuf) = (uint32_t)desc_idx;\n\n\ttx_q->m_table[len] = mbuf;\n\tlen++;\n\n\tLOG_DEBUG(VHOST_DATA,\n\t\t\"(%\"PRIu64\") in tx_route_zcp: pkt: nb_seg: %d, next:%s\\n\",\n\t\tdev->device_fh,\n\t\tmbuf->nb_segs,\n\t\t(mbuf->next == NULL) ? \"null\" : \"non-null\");\n\n\tif (enable_stats) {\n\t\tdev_statistics[dev->device_fh].tx_total++;\n\t\tdev_statistics[dev->device_fh].tx++;\n\t}\n\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tm_table = (struct rte_mbuf **)tx_q->m_table;\n\t\tret = rte_eth_tx_burst(ports[0],\n\t\t\t(uint16_t)tx_q->txq_id, m_table, (uint16_t) len);\n\n\t\t/*\n\t\t * Free any buffers not handled by TX and update\n\t\t * the port stats.\n\t\t */\n\t\tif (unlikely(ret < len)) {\n\t\t\tdo {\n\t\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t\t} while (++ret < len);\n\t\t}\n\n\t\tlen = 0;\n\t\ttxmbuf_clean_zcp(dev, vpool);\n\t}\n\n\ttx_q->len = len;\n\n\treturn;\n}\n\n/*\n * This function TX all available packets in virtio TX queue for one\n * virtio-net device. If it is first packet, it learns MAC address and\n * setup VMDQ.\n */\nstatic inline void __attribute__((always_inline))\nvirtio_dev_tx_zcp(struct virtio_net *dev)\n{\n\tstruct rte_mbuf m;\n\tstruct vhost_virtqueue *vq;\n\tstruct vring_desc *desc;\n\tuint64_t buff_addr = 0, phys_addr;\n\tuint32_t head[MAX_PKT_BURST];\n\tuint32_t i;\n\tuint16_t free_entries, packet_success = 0;\n\tuint16_t avail_idx;\n\tuint8_t need_copy = 0;\n\thpa_type addr_type;\n\tstruct vhost_dev *vdev = (struct vhost_dev *)dev->priv;\n\n\tvq = dev->virtqueue[VIRTIO_TXQ];\n\tavail_idx = *((volatile uint16_t *)&vq->avail->idx);\n\n\t/* If there are no available buffers then return. */\n\tif (vq->last_used_idx_res == avail_idx)\n\t\treturn;\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") virtio_dev_tx()\\n\", dev->device_fh);\n\n\t/* Prefetch available ring to retrieve head indexes. */\n\trte_prefetch0(&vq->avail->ring[vq->last_used_idx_res & (vq->size - 1)]);\n\n\t/* Get the number of free entries in the ring */\n\tfree_entries = (avail_idx - vq->last_used_idx_res);\n\n\t/* Limit to MAX_PKT_BURST. */\n\tfree_entries\n\t\t= (free_entries > MAX_PKT_BURST) ? MAX_PKT_BURST : free_entries;\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") Buffers available %d\\n\",\n\t\tdev->device_fh, free_entries);\n\n\t/* Retrieve all of the head indexes first to avoid caching issues. */\n\tfor (i = 0; i < free_entries; i++)\n\t\thead[i]\n\t\t\t= vq->avail->ring[(vq->last_used_idx_res + i)\n\t\t\t& (vq->size - 1)];\n\n\tvq->last_used_idx_res += free_entries;\n\n\t/* Prefetch descriptor index. */\n\trte_prefetch0(&vq->desc[head[packet_success]]);\n\trte_prefetch0(&vq->used->ring[vq->last_used_idx & (vq->size - 1)]);\n\n\twhile (packet_success < free_entries) {\n\t\tdesc = &vq->desc[head[packet_success]];\n\n\t\t/* Discard first buffer as it is the virtio header */\n\t\tdesc = &vq->desc[desc->next];\n\n\t\t/* Buffer address translation. */\n\t\tbuff_addr = gpa_to_vva(dev, desc->addr);\n\t\t/* Need check extra VLAN_HLEN size for inserting VLAN tag */\n\t\tphys_addr = gpa_to_hpa(vdev, desc->addr, desc->len + VLAN_HLEN,\n\t\t\t&addr_type);\n\n\t\tif (likely(packet_success < (free_entries - 1)))\n\t\t\t/* Prefetch descriptor index. */\n\t\t\trte_prefetch0(&vq->desc[head[packet_success + 1]]);\n\n\t\tif (unlikely(addr_type == PHYS_ADDR_INVALID)) {\n\t\t\tRTE_LOG(ERR, VHOST_DATA,\n\t\t\t\t\"(%\"PRIu64\") Invalid frame buffer address found\"\n\t\t\t\t\"when TX packets!\\n\",\n\t\t\t\tdev->device_fh);\n\t\t\tpacket_success++;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Prefetch buffer address. */\n\t\trte_prefetch0((void *)(uintptr_t)buff_addr);\n\n\t\t/*\n\t\t * Setup dummy mbuf. This is copied to a real mbuf if\n\t\t * transmitted out the physical port.\n\t\t */\n\t\tm.data_len = desc->len;\n\t\tm.nb_segs = 1;\n\t\tm.next = NULL;\n\t\tm.data_off = 0;\n\t\tm.buf_addr = (void *)(uintptr_t)buff_addr;\n\t\tm.buf_physaddr = phys_addr;\n\n\t\t/*\n\t\t * Check if the frame buffer address from guest crosses\n\t\t * sub-region or not.\n\t\t */\n\t\tif (unlikely(addr_type == PHYS_ADDR_CROSS_SUBREG)) {\n\t\t\tRTE_LOG(ERR, VHOST_DATA,\n\t\t\t\t\"(%\"PRIu64\") Frame buffer address cross \"\n\t\t\t\t\"sub-regioin found when attaching TX frame \"\n\t\t\t\t\"buffer address!\\n\",\n\t\t\t\tdev->device_fh);\n\t\t\tneed_copy = 1;\n\t\t} else\n\t\t\tneed_copy = 0;\n\n\t\tPRINT_PACKET(dev, (uintptr_t)buff_addr, desc->len, 0);\n\n\t\t/*\n\t\t * If this is the first received packet we need to learn\n\t\t * the MAC and setup VMDQ\n\t\t */\n\t\tif (unlikely(vdev->ready == DEVICE_MAC_LEARNING)) {\n\t\t\tif (vdev->remove || (link_vmdq(vdev, &m) == -1)) {\n\t\t\t\t/*\n\t\t\t\t * Discard frame if device is scheduled for\n\t\t\t\t * removal or a duplicate MAC address is found.\n\t\t\t\t */\n\t\t\t\tpacket_success += free_entries;\n\t\t\t\tvq->last_used_idx += packet_success;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tvirtio_tx_route_zcp(dev, &m, head[packet_success], need_copy);\n\t\tpacket_success++;\n\t}\n}\n\n/*\n * This function is called by each data core. It handles all RX/TX registered\n * with the core. For TX the specific lcore linked list is used. For RX, MAC\n * addresses are compared with all devices in the main linked list.\n */\nstatic int\nswitch_worker_zcp(__attribute__((unused)) void *arg)\n{\n\tstruct virtio_net *dev = NULL;\n\tstruct vhost_dev *vdev = NULL;\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct virtio_net_data_ll *dev_ll;\n\tstruct mbuf_table *tx_q;\n\tvolatile struct lcore_ll_info *lcore_ll;\n\tconst uint64_t drain_tsc\n\t\t= (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S\n\t\t* BURST_TX_DRAIN_US;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc, ret_count = 0;\n\tunsigned ret;\n\tconst uint16_t lcore_id = rte_lcore_id();\n\tuint16_t count_in_ring, rx_count = 0;\n\n\tRTE_LOG(INFO, VHOST_DATA, \"Procesing on Core %u started\\n\", lcore_id);\n\n\tlcore_ll = lcore_info[lcore_id].lcore_ll;\n\tprev_tsc = 0;\n\n\twhile (1) {\n\t\tcur_tsc = rte_rdtsc();\n\n\t\t/* TX burst queue drain */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\t\t\t/*\n\t\t\t * Get mbuf from vpool.pool and detach mbuf and\n\t\t\t * put back into vpool.ring.\n\t\t\t */\n\t\t\tdev_ll = lcore_ll->ll_root_used;\n\t\t\twhile ((dev_ll != NULL) && (dev_ll->vdev != NULL)) {\n\t\t\t\t/* Get virtio device ID */\n\t\t\t\tvdev = dev_ll->vdev;\n\t\t\t\tdev = vdev->dev;\n\n\t\t\t\tif (likely(!vdev->remove)) {\n\t\t\t\t\ttx_q = &tx_queue_zcp[(uint16_t)vdev->vmdq_rx_q];\n\t\t\t\t\tif (tx_q->len) {\n\t\t\t\t\t\tLOG_DEBUG(VHOST_DATA,\n\t\t\t\t\t\t\"TX queue drained after timeout\"\n\t\t\t\t\t\t\" with burst size %u\\n\",\n\t\t\t\t\t\ttx_q->len);\n\n\t\t\t\t\t\t/*\n\t\t\t\t\t\t * Tx any packets in the queue\n\t\t\t\t\t\t */\n\t\t\t\t\t\tret = rte_eth_tx_burst(\n\t\t\t\t\t\t\tports[0],\n\t\t\t\t\t\t\t(uint16_t)tx_q->txq_id,\n\t\t\t\t\t\t\t(struct rte_mbuf **)\n\t\t\t\t\t\t\ttx_q->m_table,\n\t\t\t\t\t\t\t(uint16_t)tx_q->len);\n\t\t\t\t\t\tif (unlikely(ret < tx_q->len)) {\n\t\t\t\t\t\t\tdo {\n\t\t\t\t\t\t\t\trte_pktmbuf_free(\n\t\t\t\t\t\t\t\t\ttx_q->m_table[ret]);\n\t\t\t\t\t\t\t} while (++ret < tx_q->len);\n\t\t\t\t\t\t}\n\t\t\t\t\t\ttx_q->len = 0;\n\n\t\t\t\t\t\ttxmbuf_clean_zcp(dev,\n\t\t\t\t\t\t\t&vpool_array[MAX_QUEUES+vdev->vmdq_rx_q]);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tdev_ll = dev_ll->next;\n\t\t\t}\n\t\t\tprev_tsc = cur_tsc;\n\t\t}\n\n\t\trte_prefetch0(lcore_ll->ll_root_used);\n\n\t\t/*\n\t\t * Inform the configuration core that we have exited the linked\n\t\t * list and that no devices are in use if requested.\n\t\t */\n\t\tif (lcore_ll->dev_removal_flag == REQUEST_DEV_REMOVAL)\n\t\t\tlcore_ll->dev_removal_flag = ACK_DEV_REMOVAL;\n\n\t\t/* Process devices */\n\t\tdev_ll = lcore_ll->ll_root_used;\n\n\t\twhile ((dev_ll != NULL) && (dev_ll->vdev != NULL)) {\n\t\t\tvdev = dev_ll->vdev;\n\t\t\tdev = vdev->dev;\n\t\t\tif (unlikely(vdev->remove)) {\n\t\t\t\tdev_ll = dev_ll->next;\n\t\t\t\tunlink_vmdq(vdev);\n\t\t\t\tvdev->ready = DEVICE_SAFE_REMOVE;\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (likely(vdev->ready == DEVICE_RX)) {\n\t\t\t\tuint32_t index = vdev->vmdq_rx_q;\n\t\t\t\tuint16_t i;\n\t\t\t\tcount_in_ring\n\t\t\t\t= rte_ring_count(vpool_array[index].ring);\n\t\t\t\tuint16_t free_entries\n\t\t\t\t= (uint16_t)get_available_ring_num_zcp(dev);\n\n\t\t\t\t/*\n\t\t\t\t * Attach all mbufs in vpool.ring and put back\n\t\t\t\t * into vpool.pool.\n\t\t\t\t */\n\t\t\t\tfor (i = 0;\n\t\t\t\ti < RTE_MIN(free_entries,\n\t\t\t\tRTE_MIN(count_in_ring, MAX_PKT_BURST));\n\t\t\t\ti++)\n\t\t\t\t\tattach_rxmbuf_zcp(dev);\n\n\t\t\t\t/* Handle guest RX */\n\t\t\t\trx_count = rte_eth_rx_burst(ports[0],\n\t\t\t\t\tvdev->vmdq_rx_q, pkts_burst,\n\t\t\t\t\tMAX_PKT_BURST);\n\n\t\t\t\tif (rx_count) {\n\t\t\t\t\tret_count = virtio_dev_rx_zcp(dev,\n\t\t\t\t\t\t\tpkts_burst, rx_count);\n\t\t\t\t\tif (enable_stats) {\n\t\t\t\t\t\tdev_statistics[dev->device_fh].rx_total\n\t\t\t\t\t\t\t+= rx_count;\n\t\t\t\t\t\tdev_statistics[dev->device_fh].rx\n\t\t\t\t\t\t\t+= ret_count;\n\t\t\t\t\t}\n\t\t\t\t\twhile (likely(rx_count)) {\n\t\t\t\t\t\trx_count--;\n\t\t\t\t\t\tpktmbuf_detach_zcp(\n\t\t\t\t\t\t\tpkts_burst[rx_count]);\n\t\t\t\t\t\trte_ring_sp_enqueue(\n\t\t\t\t\t\t\tvpool_array[index].ring,\n\t\t\t\t\t\t\t(void *)pkts_burst[rx_count]);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (likely(!vdev->remove))\n\t\t\t\t/* Handle guest TX */\n\t\t\t\tvirtio_dev_tx_zcp(dev);\n\n\t\t\t/* Move to the next device in the list */\n\t\t\tdev_ll = dev_ll->next;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n\n/*\n * Add an entry to a used linked list. A free entry must first be found\n * in the free linked list using get_data_ll_free_entry();\n */\nstatic void\nadd_data_ll_entry(struct virtio_net_data_ll **ll_root_addr,\n\tstruct virtio_net_data_ll *ll_dev)\n{\n\tstruct virtio_net_data_ll *ll = *ll_root_addr;\n\n\t/* Set next as NULL and use a compiler barrier to avoid reordering. */\n\tll_dev->next = NULL;\n\trte_compiler_barrier();\n\n\t/* If ll == NULL then this is the first device. */\n\tif (ll) {\n\t\t/* Increment to the tail of the linked list. */\n\t\twhile ((ll->next != NULL) )\n\t\t\tll = ll->next;\n\n\t\tll->next = ll_dev;\n\t} else {\n\t\t*ll_root_addr = ll_dev;\n\t}\n}\n\n/*\n * Remove an entry from a used linked list. The entry must then be added to\n * the free linked list using put_data_ll_free_entry().\n */\nstatic void\nrm_data_ll_entry(struct virtio_net_data_ll **ll_root_addr,\n\tstruct virtio_net_data_ll *ll_dev,\n\tstruct virtio_net_data_ll *ll_dev_last)\n{\n\tstruct virtio_net_data_ll *ll = *ll_root_addr;\n\n\tif (unlikely((ll == NULL) || (ll_dev == NULL)))\n\t\treturn;\n\n\tif (ll_dev == ll)\n\t\t*ll_root_addr = ll_dev->next;\n\telse\n\t\tif (likely(ll_dev_last != NULL))\n\t\t\tll_dev_last->next = ll_dev->next;\n\t\telse\n\t\t\tRTE_LOG(ERR, VHOST_CONFIG, \"Remove entry form ll failed.\\n\");\n}\n\n/*\n * Find and return an entry from the free linked list.\n */\nstatic struct virtio_net_data_ll *\nget_data_ll_free_entry(struct virtio_net_data_ll **ll_root_addr)\n{\n\tstruct virtio_net_data_ll *ll_free = *ll_root_addr;\n\tstruct virtio_net_data_ll *ll_dev;\n\n\tif (ll_free == NULL)\n\t\treturn NULL;\n\n\tll_dev = ll_free;\n\t*ll_root_addr = ll_free->next;\n\n\treturn ll_dev;\n}\n\n/*\n * Place an entry back on to the free linked list.\n */\nstatic void\nput_data_ll_free_entry(struct virtio_net_data_ll **ll_root_addr,\n\tstruct virtio_net_data_ll *ll_dev)\n{\n\tstruct virtio_net_data_ll *ll_free = *ll_root_addr;\n\n\tif (ll_dev == NULL)\n\t\treturn;\n\n\tll_dev->next = ll_free;\n\t*ll_root_addr = ll_dev;\n}\n\n/*\n * Creates a linked list of a given size.\n */\nstatic struct virtio_net_data_ll *\nalloc_data_ll(uint32_t size)\n{\n\tstruct virtio_net_data_ll *ll_new;\n\tuint32_t i;\n\n\t/* Malloc and then chain the linked list. */\n\tll_new = malloc(size * sizeof(struct virtio_net_data_ll));\n\tif (ll_new == NULL) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG, \"Failed to allocate memory for ll_new.\\n\");\n\t\treturn NULL;\n\t}\n\n\tfor (i = 0; i < size - 1; i++) {\n\t\tll_new[i].vdev = NULL;\n\t\tll_new[i].next = &ll_new[i+1];\n\t}\n\tll_new[i].next = NULL;\n\n\treturn (ll_new);\n}\n\n/*\n * Create the main linked list along with each individual cores linked list. A used and a free list\n * are created to manage entries.\n */\nstatic int\ninit_data_ll (void)\n{\n\tint lcore;\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\tlcore_info[lcore].lcore_ll = malloc(sizeof(struct lcore_ll_info));\n\t\tif (lcore_info[lcore].lcore_ll == NULL) {\n\t\t\tRTE_LOG(ERR, VHOST_CONFIG, \"Failed to allocate memory for lcore_ll.\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tlcore_info[lcore].lcore_ll->device_num = 0;\n\t\tlcore_info[lcore].lcore_ll->dev_removal_flag = ACK_DEV_REMOVAL;\n\t\tlcore_info[lcore].lcore_ll->ll_root_used = NULL;\n\t\tif (num_devices % num_switching_cores)\n\t\t\tlcore_info[lcore].lcore_ll->ll_root_free = alloc_data_ll((num_devices / num_switching_cores) + 1);\n\t\telse\n\t\t\tlcore_info[lcore].lcore_ll->ll_root_free = alloc_data_ll(num_devices / num_switching_cores);\n\t}\n\n\t/* Allocate devices up to a maximum of MAX_DEVICES. */\n\tll_root_free = alloc_data_ll(MIN((num_devices), MAX_DEVICES));\n\n\treturn 0;\n}\n\n/*\n * Remove a device from the specific data core linked list and from the main linked list. Synchonization\n * occurs through the use of the lcore dev_removal_flag. Device is made volatile here to avoid re-ordering\n * of dev->remove=1 which can cause an infinite loop in the rte_pause loop.\n */\nstatic void\ndestroy_device (volatile struct virtio_net *dev)\n{\n\tstruct virtio_net_data_ll *ll_lcore_dev_cur;\n\tstruct virtio_net_data_ll *ll_main_dev_cur;\n\tstruct virtio_net_data_ll *ll_lcore_dev_last = NULL;\n\tstruct virtio_net_data_ll *ll_main_dev_last = NULL;\n\tstruct vhost_dev *vdev;\n\tint lcore;\n\n\tdev->flags &= ~VIRTIO_DEV_RUNNING;\n\n\tvdev = (struct vhost_dev *)dev->priv;\n\t/*set the remove flag. */\n\tvdev->remove = 1;\n\twhile(vdev->ready != DEVICE_SAFE_REMOVE) {\n\t\trte_pause();\n\t}\n\n\t/* Search for entry to be removed from lcore ll */\n\tll_lcore_dev_cur = lcore_info[vdev->coreid].lcore_ll->ll_root_used;\n\twhile (ll_lcore_dev_cur != NULL) {\n\t\tif (ll_lcore_dev_cur->vdev == vdev) {\n\t\t\tbreak;\n\t\t} else {\n\t\t\tll_lcore_dev_last = ll_lcore_dev_cur;\n\t\t\tll_lcore_dev_cur = ll_lcore_dev_cur->next;\n\t\t}\n\t}\n\n\tif (ll_lcore_dev_cur == NULL) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") Failed to find the dev to be destroy.\\n\",\n\t\t\tdev->device_fh);\n\t\treturn;\n\t}\n\n\t/* Search for entry to be removed from main ll */\n\tll_main_dev_cur = ll_root_used;\n\tll_main_dev_last = NULL;\n\twhile (ll_main_dev_cur != NULL) {\n\t\tif (ll_main_dev_cur->vdev == vdev) {\n\t\t\tbreak;\n\t\t} else {\n\t\t\tll_main_dev_last = ll_main_dev_cur;\n\t\t\tll_main_dev_cur = ll_main_dev_cur->next;\n\t\t}\n\t}\n\n\t/* Remove entries from the lcore and main ll. */\n\trm_data_ll_entry(&lcore_info[vdev->coreid].lcore_ll->ll_root_used, ll_lcore_dev_cur, ll_lcore_dev_last);\n\trm_data_ll_entry(&ll_root_used, ll_main_dev_cur, ll_main_dev_last);\n\n\t/* Set the dev_removal_flag on each lcore. */\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\tlcore_info[lcore].lcore_ll->dev_removal_flag = REQUEST_DEV_REMOVAL;\n\t}\n\n\t/*\n\t * Once each core has set the dev_removal_flag to ACK_DEV_REMOVAL we can be sure that\n\t * they can no longer access the device removed from the linked lists and that the devices\n\t * are no longer in use.\n\t */\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\twhile (lcore_info[lcore].lcore_ll->dev_removal_flag != ACK_DEV_REMOVAL) {\n\t\t\trte_pause();\n\t\t}\n\t}\n\n\t/* Add the entries back to the lcore and main free ll.*/\n\tput_data_ll_free_entry(&lcore_info[vdev->coreid].lcore_ll->ll_root_free, ll_lcore_dev_cur);\n\tput_data_ll_free_entry(&ll_root_free, ll_main_dev_cur);\n\n\t/* Decrement number of device on the lcore. */\n\tlcore_info[vdev->coreid].lcore_ll->device_num--;\n\n\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") Device has been removed from data core\\n\", dev->device_fh);\n\n\tif (zero_copy) {\n\t\tstruct vpool *vpool = &vpool_array[vdev->vmdq_rx_q];\n\n\t\t/* Stop the RX queue. */\n\t\tif (rte_eth_dev_rx_queue_stop(ports[0], vdev->vmdq_rx_q) != 0) {\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"(%\"PRIu64\") In destroy_device: Failed to stop \"\n\t\t\t\t\"rx queue:%d\\n\",\n\t\t\t\tdev->device_fh,\n\t\t\t\tvdev->vmdq_rx_q);\n\t\t}\n\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") in destroy_device: Start put mbuf in \"\n\t\t\t\"mempool back to ring for RX queue: %d\\n\",\n\t\t\tdev->device_fh, vdev->vmdq_rx_q);\n\n\t\tmbuf_destroy_zcp(vpool);\n\n\t\t/* Stop the TX queue. */\n\t\tif (rte_eth_dev_tx_queue_stop(ports[0], vdev->vmdq_rx_q) != 0) {\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"(%\"PRIu64\") In destroy_device: Failed to \"\n\t\t\t\t\"stop tx queue:%d\\n\",\n\t\t\t\tdev->device_fh, vdev->vmdq_rx_q);\n\t\t}\n\n\t\tvpool = &vpool_array[vdev->vmdq_rx_q + MAX_QUEUES];\n\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") destroy_device: Start put mbuf in mempool \"\n\t\t\t\"back to ring for TX queue: %d, dev:(%\"PRIu64\")\\n\",\n\t\t\tdev->device_fh, (vdev->vmdq_rx_q + MAX_QUEUES),\n\t\t\tdev->device_fh);\n\n\t\tmbuf_destroy_zcp(vpool);\n\t\trte_free(vdev->regions_hpa);\n\t}\n\trte_free(vdev);\n\n}\n\n/*\n * Calculate the region count of physical continous regions for one particular\n * region of whose vhost virtual address is continous. The particular region\n * start from vva_start, with size of 'size' in argument.\n */\nstatic uint32_t\ncheck_hpa_regions(uint64_t vva_start, uint64_t size)\n{\n\tuint32_t i, nregions = 0, page_size = getpagesize();\n\tuint64_t cur_phys_addr = 0, next_phys_addr = 0;\n\tif (vva_start % page_size) {\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"in check_countinous: vva start(%p) mod page_size(%d) \"\n\t\t\t\"has remainder\\n\",\n\t\t\t(void *)(uintptr_t)vva_start, page_size);\n\t\treturn 0;\n\t}\n\tif (size % page_size) {\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"in check_countinous: \"\n\t\t\t\"size((%\"PRIu64\")) mod page_size(%d) has remainder\\n\",\n\t\t\tsize, page_size);\n\t\treturn 0;\n\t}\n\tfor (i = 0; i < size - page_size; i = i + page_size) {\n\t\tcur_phys_addr\n\t\t\t= rte_mem_virt2phy((void *)(uintptr_t)(vva_start + i));\n\t\tnext_phys_addr = rte_mem_virt2phy(\n\t\t\t(void *)(uintptr_t)(vva_start + i + page_size));\n\t\tif ((cur_phys_addr + page_size) != next_phys_addr) {\n\t\t\t++nregions;\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"in check_continuous: hva addr:(%p) is not \"\n\t\t\t\t\"continuous with hva addr:(%p), diff:%d\\n\",\n\t\t\t\t(void *)(uintptr_t)(vva_start + (uint64_t)i),\n\t\t\t\t(void *)(uintptr_t)(vva_start + (uint64_t)i\n\t\t\t\t+ page_size), page_size);\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"in check_continuous: hpa addr:(%p) is not \"\n\t\t\t\t\"continuous with hpa addr:(%p), \"\n\t\t\t\t\"diff:(%\"PRIu64\")\\n\",\n\t\t\t\t(void *)(uintptr_t)cur_phys_addr,\n\t\t\t\t(void *)(uintptr_t)next_phys_addr,\n\t\t\t\t(next_phys_addr-cur_phys_addr));\n\t\t}\n\t}\n\treturn nregions;\n}\n\n/*\n * Divide each region whose vhost virtual address is continous into a few\n * sub-regions, make sure the physical address within each sub-region are\n * continous. And fill offset(to GPA) and size etc. information of each\n * sub-region into regions_hpa.\n */\nstatic uint32_t\nfill_hpa_memory_regions(struct virtio_memory_regions_hpa *mem_region_hpa, struct virtio_memory *virtio_memory)\n{\n\tuint32_t regionidx, regionidx_hpa = 0, i, k, page_size = getpagesize();\n\tuint64_t cur_phys_addr = 0, next_phys_addr = 0, vva_start;\n\n\tif (mem_region_hpa == NULL)\n\t\treturn 0;\n\n\tfor (regionidx = 0; regionidx < virtio_memory->nregions; regionidx++) {\n\t\tvva_start = virtio_memory->regions[regionidx].guest_phys_address +\n\t\t\tvirtio_memory->regions[regionidx].address_offset;\n\t\tmem_region_hpa[regionidx_hpa].guest_phys_address\n\t\t\t= virtio_memory->regions[regionidx].guest_phys_address;\n\t\tmem_region_hpa[regionidx_hpa].host_phys_addr_offset =\n\t\t\trte_mem_virt2phy((void *)(uintptr_t)(vva_start)) -\n\t\t\tmem_region_hpa[regionidx_hpa].guest_phys_address;\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"in fill_hpa_regions: guest phys addr start[%d]:(%p)\\n\",\n\t\t\tregionidx_hpa,\n\t\t\t(void *)(uintptr_t)\n\t\t\t(mem_region_hpa[regionidx_hpa].guest_phys_address));\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"in fill_hpa_regions: host phys addr start[%d]:(%p)\\n\",\n\t\t\tregionidx_hpa,\n\t\t\t(void *)(uintptr_t)\n\t\t\t(mem_region_hpa[regionidx_hpa].host_phys_addr_offset));\n\t\tfor (i = 0, k = 0;\n\t\t\ti < virtio_memory->regions[regionidx].memory_size -\n\t\t\t\tpage_size;\n\t\t\ti += page_size) {\n\t\t\tcur_phys_addr = rte_mem_virt2phy(\n\t\t\t\t\t(void *)(uintptr_t)(vva_start + i));\n\t\t\tnext_phys_addr = rte_mem_virt2phy(\n\t\t\t\t\t(void *)(uintptr_t)(vva_start +\n\t\t\t\t\ti + page_size));\n\t\t\tif ((cur_phys_addr + page_size) != next_phys_addr) {\n\t\t\t\tmem_region_hpa[regionidx_hpa].guest_phys_address_end =\n\t\t\t\t\tmem_region_hpa[regionidx_hpa].guest_phys_address +\n\t\t\t\t\tk + page_size;\n\t\t\t\tmem_region_hpa[regionidx_hpa].memory_size\n\t\t\t\t\t= k + page_size;\n\t\t\t\tLOG_DEBUG(VHOST_CONFIG, \"in fill_hpa_regions: guest \"\n\t\t\t\t\t\"phys addr end [%d]:(%p)\\n\",\n\t\t\t\t\tregionidx_hpa,\n\t\t\t\t\t(void *)(uintptr_t)\n\t\t\t\t\t(mem_region_hpa[regionidx_hpa].guest_phys_address_end));\n\t\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\t\"in fill_hpa_regions: guest phys addr \"\n\t\t\t\t\t\"size [%d]:(%p)\\n\",\n\t\t\t\t\tregionidx_hpa,\n\t\t\t\t\t(void *)(uintptr_t)\n\t\t\t\t\t(mem_region_hpa[regionidx_hpa].memory_size));\n\t\t\t\tmem_region_hpa[regionidx_hpa + 1].guest_phys_address\n\t\t\t\t\t= mem_region_hpa[regionidx_hpa].guest_phys_address_end;\n\t\t\t\t++regionidx_hpa;\n\t\t\t\tmem_region_hpa[regionidx_hpa].host_phys_addr_offset =\n\t\t\t\t\tnext_phys_addr -\n\t\t\t\t\tmem_region_hpa[regionidx_hpa].guest_phys_address;\n\t\t\t\tLOG_DEBUG(VHOST_CONFIG, \"in fill_hpa_regions: guest\"\n\t\t\t\t\t\" phys addr start[%d]:(%p)\\n\",\n\t\t\t\t\tregionidx_hpa,\n\t\t\t\t\t(void *)(uintptr_t)\n\t\t\t\t\t(mem_region_hpa[regionidx_hpa].guest_phys_address));\n\t\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\t\"in fill_hpa_regions: host phys addr \"\n\t\t\t\t\t\"start[%d]:(%p)\\n\",\n\t\t\t\t\tregionidx_hpa,\n\t\t\t\t\t(void *)(uintptr_t)\n\t\t\t\t\t(mem_region_hpa[regionidx_hpa].host_phys_addr_offset));\n\t\t\t\tk = 0;\n\t\t\t} else {\n\t\t\t\tk += page_size;\n\t\t\t}\n\t\t}\n\t\tmem_region_hpa[regionidx_hpa].guest_phys_address_end\n\t\t\t= mem_region_hpa[regionidx_hpa].guest_phys_address\n\t\t\t+ k + page_size;\n\t\tmem_region_hpa[regionidx_hpa].memory_size = k + page_size;\n\t\tLOG_DEBUG(VHOST_CONFIG, \"in fill_hpa_regions: guest phys addr end \"\n\t\t\t\"[%d]:(%p)\\n\", regionidx_hpa,\n\t\t\t(void *)(uintptr_t)\n\t\t\t(mem_region_hpa[regionidx_hpa].guest_phys_address_end));\n\t\tLOG_DEBUG(VHOST_CONFIG, \"in fill_hpa_regions: guest phys addr size \"\n\t\t\t\"[%d]:(%p)\\n\", regionidx_hpa,\n\t\t\t(void *)(uintptr_t)\n\t\t\t(mem_region_hpa[regionidx_hpa].memory_size));\n\t\t++regionidx_hpa;\n\t}\n\treturn regionidx_hpa;\n}\n\n/*\n * A new device is added to a data core. First the device is added to the main linked list\n * and the allocated to a specific data core.\n */\nstatic int\nnew_device (struct virtio_net *dev)\n{\n\tstruct virtio_net_data_ll *ll_dev;\n\tint lcore, core_add = 0;\n\tuint32_t device_num_min = num_devices;\n\tstruct vhost_dev *vdev;\n\tuint32_t regionidx;\n\n\tvdev = rte_zmalloc(\"vhost device\", sizeof(*vdev), RTE_CACHE_LINE_SIZE);\n\tif (vdev == NULL) {\n\t\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") Couldn't allocate memory for vhost dev\\n\",\n\t\t\tdev->device_fh);\n\t\treturn -1;\n\t}\n\tvdev->dev = dev;\n\tdev->priv = vdev;\n\n\tif (zero_copy) {\n\t\tvdev->nregions_hpa = dev->mem->nregions;\n\t\tfor (regionidx = 0; regionidx < dev->mem->nregions; regionidx++) {\n\t\t\tvdev->nregions_hpa\n\t\t\t\t+= check_hpa_regions(\n\t\t\t\t\tdev->mem->regions[regionidx].guest_phys_address\n\t\t\t\t\t+ dev->mem->regions[regionidx].address_offset,\n\t\t\t\t\tdev->mem->regions[regionidx].memory_size);\n\n\t\t}\n\n\t\tvdev->regions_hpa = rte_calloc(\"vhost hpa region\",\n\t\t\t\t\t vdev->nregions_hpa,\n\t\t\t\t\t sizeof(struct virtio_memory_regions_hpa),\n\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n\t\tif (vdev->regions_hpa == NULL) {\n\t\t\tRTE_LOG(ERR, VHOST_CONFIG, \"Cannot allocate memory for hpa region\\n\");\n\t\t\trte_free(vdev);\n\t\t\treturn -1;\n\t\t}\n\n\n\t\tif (fill_hpa_memory_regions(\n\t\t\tvdev->regions_hpa, dev->mem\n\t\t\t) != vdev->nregions_hpa) {\n\n\t\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\t\"hpa memory regions number mismatch: \"\n\t\t\t\t\"[%d]\\n\", vdev->nregions_hpa);\n\t\t\trte_free(vdev->regions_hpa);\n\t\t\trte_free(vdev);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\n\t/* Add device to main ll */\n\tll_dev = get_data_ll_free_entry(&ll_root_free);\n\tif (ll_dev == NULL) {\n\t\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") No free entry found in linked list. Device limit \"\n\t\t\t\"of %d devices per core has been reached\\n\",\n\t\t\tdev->device_fh, num_devices);\n\t\tif (vdev->regions_hpa)\n\t\t\trte_free(vdev->regions_hpa);\n\t\trte_free(vdev);\n\t\treturn -1;\n\t}\n\tll_dev->vdev = vdev;\n\tadd_data_ll_entry(&ll_root_used, ll_dev);\n\tvdev->vmdq_rx_q\n\t\t= dev->device_fh * queues_per_pool + vmdq_queue_base;\n\n\tif (zero_copy) {\n\t\tuint32_t index = vdev->vmdq_rx_q;\n\t\tuint32_t count_in_ring, i;\n\t\tstruct mbuf_table *tx_q;\n\n\t\tcount_in_ring = rte_ring_count(vpool_array[index].ring);\n\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") in new_device: mbuf count in mempool \"\n\t\t\t\"before attach is: %d\\n\",\n\t\t\tdev->device_fh,\n\t\t\trte_mempool_count(vpool_array[index].pool));\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") in new_device: mbuf count in ring \"\n\t\t\t\"before attach is : %d\\n\",\n\t\t\tdev->device_fh, count_in_ring);\n\n\t\t/*\n\t\t * Attach all mbufs in vpool.ring and put back intovpool.pool.\n\t\t */\n\t\tfor (i = 0; i < count_in_ring; i++)\n\t\t\tattach_rxmbuf_zcp(dev);\n\n\t\tLOG_DEBUG(VHOST_CONFIG, \"(%\"PRIu64\") in new_device: mbuf count in \"\n\t\t\t\"mempool after attach is: %d\\n\",\n\t\t\tdev->device_fh,\n\t\t\trte_mempool_count(vpool_array[index].pool));\n\t\tLOG_DEBUG(VHOST_CONFIG, \"(%\"PRIu64\") in new_device: mbuf count in \"\n\t\t\t\"ring after attach is : %d\\n\",\n\t\t\tdev->device_fh,\n\t\t\trte_ring_count(vpool_array[index].ring));\n\n\t\ttx_q = &tx_queue_zcp[(uint16_t)vdev->vmdq_rx_q];\n\t\ttx_q->txq_id = vdev->vmdq_rx_q;\n\n\t\tif (rte_eth_dev_tx_queue_start(ports[0], vdev->vmdq_rx_q) != 0) {\n\t\t\tstruct vpool *vpool = &vpool_array[vdev->vmdq_rx_q];\n\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"(%\"PRIu64\") In new_device: Failed to start \"\n\t\t\t\t\"tx queue:%d\\n\",\n\t\t\t\tdev->device_fh, vdev->vmdq_rx_q);\n\n\t\t\tmbuf_destroy_zcp(vpool);\n\t\t\trte_free(vdev->regions_hpa);\n\t\t\trte_free(vdev);\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (rte_eth_dev_rx_queue_start(ports[0], vdev->vmdq_rx_q) != 0) {\n\t\t\tstruct vpool *vpool = &vpool_array[vdev->vmdq_rx_q];\n\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"(%\"PRIu64\") In new_device: Failed to start \"\n\t\t\t\t\"rx queue:%d\\n\",\n\t\t\t\tdev->device_fh, vdev->vmdq_rx_q);\n\n\t\t\t/* Stop the TX queue. */\n\t\t\tif (rte_eth_dev_tx_queue_stop(ports[0],\n\t\t\t\tvdev->vmdq_rx_q) != 0) {\n\t\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\t\"(%\"PRIu64\") In new_device: Failed to \"\n\t\t\t\t\t\"stop tx queue:%d\\n\",\n\t\t\t\t\tdev->device_fh, vdev->vmdq_rx_q);\n\t\t\t}\n\n\t\t\tmbuf_destroy_zcp(vpool);\n\t\t\trte_free(vdev->regions_hpa);\n\t\t\trte_free(vdev);\n\t\t\treturn -1;\n\t\t}\n\n\t}\n\n\t/*reset ready flag*/\n\tvdev->ready = DEVICE_MAC_LEARNING;\n\tvdev->remove = 0;\n\n\t/* Find a suitable lcore to add the device. */\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\tif (lcore_info[lcore].lcore_ll->device_num < device_num_min) {\n\t\t\tdevice_num_min = lcore_info[lcore].lcore_ll->device_num;\n\t\t\tcore_add = lcore;\n\t\t}\n\t}\n\t/* Add device to lcore ll */\n\tll_dev = get_data_ll_free_entry(&lcore_info[core_add].lcore_ll->ll_root_free);\n\tif (ll_dev == NULL) {\n\t\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") Failed to add device to data core\\n\", dev->device_fh);\n\t\tvdev->ready = DEVICE_SAFE_REMOVE;\n\t\tdestroy_device(dev);\n\t\trte_free(vdev->regions_hpa);\n\t\trte_free(vdev);\n\t\treturn -1;\n\t}\n\tll_dev->vdev = vdev;\n\tvdev->coreid = core_add;\n\n\tadd_data_ll_entry(&lcore_info[vdev->coreid].lcore_ll->ll_root_used, ll_dev);\n\n\t/* Initialize device stats */\n\tmemset(&dev_statistics[dev->device_fh], 0, sizeof(struct device_statistics));\n\n\t/* Disable notifications. */\n\trte_vhost_enable_guest_notification(dev, VIRTIO_RXQ, 0);\n\trte_vhost_enable_guest_notification(dev, VIRTIO_TXQ, 0);\n\tlcore_info[vdev->coreid].lcore_ll->device_num++;\n\tdev->flags |= VIRTIO_DEV_RUNNING;\n\n\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") Device has been added to data core %d\\n\", dev->device_fh, vdev->coreid);\n\n\treturn 0;\n}\n\n/*\n * These callback allow devices to be added to the data core when configuration\n * has been fully complete.\n */\nstatic const struct virtio_net_device_ops virtio_net_device_ops =\n{\n\t.new_device = new_device,\n\t.destroy_device = destroy_device,\n};\n\n/*\n * This is a thread will wake up after a period to print stats if the user has\n * enabled them.\n */\nstatic void\nprint_stats(void)\n{\n\tstruct virtio_net_data_ll *dev_ll;\n\tuint64_t tx_dropped, rx_dropped;\n\tuint64_t tx, tx_total, rx, rx_total;\n\tuint32_t device_fh;\n\tconst char clr[] = { 27, '[', '2', 'J', '\\0' };\n\tconst char top_left[] = { 27, '[', '1', ';', '1', 'H','\\0' };\n\n\twhile(1) {\n\t\tsleep(enable_stats);\n\n\t\t/* Clear screen and move to top left */\n\t\tprintf(\"%s%s\", clr, top_left);\n\n\t\tprintf(\"\\nDevice statistics ====================================\");\n\n\t\tdev_ll = ll_root_used;\n\t\twhile (dev_ll != NULL) {\n\t\t\tdevice_fh = (uint32_t)dev_ll->vdev->dev->device_fh;\n\t\t\ttx_total = dev_statistics[device_fh].tx_total;\n\t\t\ttx = dev_statistics[device_fh].tx;\n\t\t\ttx_dropped = tx_total - tx;\n\t\t\tif (zero_copy == 0) {\n\t\t\t\trx_total = rte_atomic64_read(\n\t\t\t\t\t&dev_statistics[device_fh].rx_total_atomic);\n\t\t\t\trx = rte_atomic64_read(\n\t\t\t\t\t&dev_statistics[device_fh].rx_atomic);\n\t\t\t} else {\n\t\t\t\trx_total = dev_statistics[device_fh].rx_total;\n\t\t\t\trx = dev_statistics[device_fh].rx;\n\t\t\t}\n\t\t\trx_dropped = rx_total - rx;\n\n\t\t\tprintf(\"\\nStatistics for device %\"PRIu32\" ------------------------------\"\n\t\t\t\t\t\"\\nTX total: \t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nTX dropped: \t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nTX successful: \t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nRX total: \t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nRX dropped: \t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nRX successful: \t\t%\"PRIu64\"\",\n\t\t\t\t\tdevice_fh,\n\t\t\t\t\ttx_total,\n\t\t\t\t\ttx_dropped,\n\t\t\t\t\ttx,\n\t\t\t\t\trx_total,\n\t\t\t\t\trx_dropped,\n\t\t\t\t\trx);\n\n\t\t\tdev_ll = dev_ll->next;\n\t\t}\n\t\tprintf(\"\\n======================================================\\n\");\n\t}\n}\n\nstatic void\nsetup_mempool_tbl(int socket, uint32_t index, char *pool_name,\n\tchar *ring_name, uint32_t nb_mbuf)\n{\n\tvpool_array[index].pool\t= rte_pktmbuf_pool_create(pool_name, nb_mbuf,\n\t\tMBUF_CACHE_SIZE_ZCP, 0, MBUF_DATA_SIZE_ZCP, socket);\n\tif (vpool_array[index].pool != NULL) {\n\t\tvpool_array[index].ring\n\t\t\t= rte_ring_create(ring_name,\n\t\t\t\trte_align32pow2(nb_mbuf + 1),\n\t\t\t\tsocket, RING_F_SP_ENQ | RING_F_SC_DEQ);\n\t\tif (likely(vpool_array[index].ring != NULL)) {\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"in setup_mempool_tbl: mbuf count in \"\n\t\t\t\t\"mempool is: %d\\n\",\n\t\t\t\trte_mempool_count(vpool_array[index].pool));\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"in setup_mempool_tbl: mbuf count in \"\n\t\t\t\t\"ring is: %d\\n\",\n\t\t\t\trte_ring_count(vpool_array[index].ring));\n\t\t} else {\n\t\t\trte_exit(EXIT_FAILURE, \"ring_create(%s) failed\",\n\t\t\t\tring_name);\n\t\t}\n\n\t\t/* Need consider head room. */\n\t\tvpool_array[index].buf_size = VIRTIO_DESCRIPTOR_LEN_ZCP;\n\t} else {\n\t\trte_exit(EXIT_FAILURE, \"mempool_create(%s) failed\", pool_name);\n\t}\n}\n\n/* When we receive a INT signal, unregister vhost driver */\nstatic void\nsigint_handler(__rte_unused int signum)\n{\n\t/* Unregister vhost driver. */\n\tint ret = rte_vhost_driver_unregister((char *)&dev_basename);\n\tif (ret != 0)\n\t\trte_exit(EXIT_FAILURE, \"vhost driver unregister failure.\\n\");\n\texit(0);\n}\n\n/*\n * Main function, does initialisation and calls the per-lcore functions. The CUSE\n * device is also registered here to handle the IOCTLs.\n */\nint\nmain(int argc, char *argv[])\n{\n\tstruct rte_mempool *mbuf_pool = NULL;\n\tunsigned lcore_id, core_id = 0;\n\tunsigned nb_ports, valid_num_ports;\n\tint ret;\n\tuint8_t portid;\n\tuint16_t queue_id;\n\tstatic pthread_t tid;\n\n\tsignal(SIGINT, sigint_handler);\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Error with EAL initialization\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse app arguments */\n\tret = us_vhost_parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid argument\\n\");\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id ++)\n\t\tif (rte_lcore_is_enabled(lcore_id))\n\t\t\tlcore_ids[core_id ++] = lcore_id;\n\n\tif (rte_lcore_count() > RTE_MAX_LCORE)\n\t\trte_exit(EXIT_FAILURE,\"Not enough cores\\n\");\n\n\t/*set the number of swithcing cores available*/\n\tnum_switching_cores = rte_lcore_count()-1;\n\n\t/* Get the number of physical ports. */\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\t/*\n\t * Update the global var NUM_PORTS and global array PORTS\n\t * and get value of var VALID_NUM_PORTS according to system ports number\n\t */\n\tvalid_num_ports = check_ports_num(nb_ports);\n\n\tif ((valid_num_ports == 0) || (valid_num_ports > MAX_SUP_PORTS)) {\n\t\tRTE_LOG(INFO, VHOST_PORT, \"Current enabled port number is %u,\"\n\t\t\t\"but only %u port can be enabled\\n\",num_ports, MAX_SUP_PORTS);\n\t\treturn -1;\n\t}\n\n\tif (zero_copy == 0) {\n\t\t/* Create the mbuf pool. */\n\t\tmbuf_pool = rte_pktmbuf_pool_create(\"MBUF_POOL\",\n\t\t\tNUM_MBUFS_PER_PORT * valid_num_ports, MBUF_CACHE_SIZE,\n\t\t\t0, MBUF_DATA_SIZE, rte_socket_id());\n\t\tif (mbuf_pool == NULL)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot create mbuf pool\\n\");\n\n\t\tfor (queue_id = 0; queue_id < MAX_QUEUES + 1; queue_id++)\n\t\t\tvpool_array[queue_id].pool = mbuf_pool;\n\n\t\tif (vm2vm_mode == VM2VM_HARDWARE) {\n\t\t\t/* Enable VT loop back to let L2 switch to do it. */\n\t\t\tvmdq_conf_default.rx_adv_conf.vmdq_rx_conf.enable_loop_back = 1;\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"Enable loop back for L2 switch in vmdq.\\n\");\n\t\t}\n\t} else {\n\t\tuint32_t nb_mbuf;\n\t\tchar pool_name[RTE_MEMPOOL_NAMESIZE];\n\t\tchar ring_name[RTE_MEMPOOL_NAMESIZE];\n\n\t\tnb_mbuf = num_rx_descriptor\n\t\t\t+ num_switching_cores * MBUF_CACHE_SIZE_ZCP\n\t\t\t+ num_switching_cores * MAX_PKT_BURST;\n\n\t\tfor (queue_id = 0; queue_id < MAX_QUEUES; queue_id++) {\n\t\t\tsnprintf(pool_name, sizeof(pool_name),\n\t\t\t\t\"rxmbuf_pool_%u\", queue_id);\n\t\t\tsnprintf(ring_name, sizeof(ring_name),\n\t\t\t\t\"rxmbuf_ring_%u\", queue_id);\n\t\t\tsetup_mempool_tbl(rte_socket_id(), queue_id,\n\t\t\t\tpool_name, ring_name, nb_mbuf);\n\t\t}\n\n\t\tnb_mbuf = num_tx_descriptor\n\t\t\t\t+ num_switching_cores * MBUF_CACHE_SIZE_ZCP\n\t\t\t\t+ num_switching_cores * MAX_PKT_BURST;\n\n\t\tfor (queue_id = 0; queue_id < MAX_QUEUES; queue_id++) {\n\t\t\tsnprintf(pool_name, sizeof(pool_name),\n\t\t\t\t\"txmbuf_pool_%u\", queue_id);\n\t\t\tsnprintf(ring_name, sizeof(ring_name),\n\t\t\t\t\"txmbuf_ring_%u\", queue_id);\n\t\t\tsetup_mempool_tbl(rte_socket_id(),\n\t\t\t\t(queue_id + MAX_QUEUES),\n\t\t\t\tpool_name, ring_name, nb_mbuf);\n\t\t}\n\n\t\tif (vm2vm_mode == VM2VM_HARDWARE) {\n\t\t\t/* Enable VT loop back to let L2 switch to do it. */\n\t\t\tvmdq_conf_default.rx_adv_conf.vmdq_rx_conf.enable_loop_back = 1;\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"Enable loop back for L2 switch in vmdq.\\n\");\n\t\t}\n\t}\n\t/* Set log level. */\n\trte_set_log_level(LOG_LEVEL);\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tRTE_LOG(INFO, VHOST_PORT,\n\t\t\t\t\"Skipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\t\tif (port_init(portid) != 0)\n\t\t\trte_exit(EXIT_FAILURE,\n\t\t\t\t\"Cannot initialize network ports\\n\");\n\t}\n\n\t/* Initialise all linked lists. */\n\tif (init_data_ll() == -1)\n\t\trte_exit(EXIT_FAILURE, \"Failed to initialize linked list\\n\");\n\n\t/* Initialize device stats */\n\tmemset(&dev_statistics, 0, sizeof(dev_statistics));\n\n\t/* Enable stats if the user option is set. */\n\tif (enable_stats)\n\t\tpthread_create(&tid, NULL, (void*)print_stats, NULL );\n\n\t/* Launch all data cores. */\n\tif (zero_copy == 0) {\n\t\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\t\trte_eal_remote_launch(switch_worker,\n\t\t\t\tmbuf_pool, lcore_id);\n\t\t}\n\t} else {\n\t\tuint32_t count_in_mempool, index, i;\n\t\tfor (index = 0; index < 2*MAX_QUEUES; index++) {\n\t\t\t/* For all RX and TX queues. */\n\t\t\tcount_in_mempool\n\t\t\t\t= rte_mempool_count(vpool_array[index].pool);\n\n\t\t\t/*\n\t\t\t * Transfer all un-attached mbufs from vpool.pool\n\t\t\t * to vpoo.ring.\n\t\t\t */\n\t\t\tfor (i = 0; i < count_in_mempool; i++) {\n\t\t\t\tstruct rte_mbuf *mbuf\n\t\t\t\t\t= __rte_mbuf_raw_alloc(\n\t\t\t\t\t\tvpool_array[index].pool);\n\t\t\t\trte_ring_sp_enqueue(vpool_array[index].ring,\n\t\t\t\t\t\t(void *)mbuf);\n\t\t\t}\n\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"in main: mbuf count in mempool at initial \"\n\t\t\t\t\"is: %d\\n\", count_in_mempool);\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"in main: mbuf count in ring at initial is :\"\n\t\t\t\t\" %d\\n\",\n\t\t\t\trte_ring_count(vpool_array[index].ring));\n\t\t}\n\n\t\tRTE_LCORE_FOREACH_SLAVE(lcore_id)\n\t\t\trte_eal_remote_launch(switch_worker_zcp, NULL,\n\t\t\t\tlcore_id);\n\t}\n\n\tif (mergeable == 0)\n\t\trte_vhost_feature_disable(1ULL << VIRTIO_NET_F_MRG_RXBUF);\n\n\t/* Register vhost(cuse or user) driver to handle vhost messages. */\n\tret = rte_vhost_driver_register((char *)&dev_basename);\n\tif (ret != 0)\n\t\trte_exit(EXIT_FAILURE, \"vhost driver register failure.\\n\");\n\n\trte_vhost_driver_callback_register(&virtio_net_device_ops);\n\n\t/* Start CUSE session. */\n\trte_vhost_driver_session_start();\n\treturn 0;\n\n}\n" }, { "path": "examples/vhost/main.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _MAIN_H_\n#define _MAIN_H_\n\n//#define DEBUG\n\n#ifdef DEBUG\n#define LOG_LEVEL RTE_LOG_DEBUG\n#define LOG_DEBUG(log_type, fmt, args...) do {\t\\\n\tRTE_LOG(DEBUG, log_type, fmt, ##args);\t\t\\\n} while (0)\n#else\n#define LOG_LEVEL RTE_LOG_INFO\n#define LOG_DEBUG(log_type, fmt, args...) do{} while(0)\n#endif\n\n/* Macros for printing using RTE_LOG */\n#define RTE_LOGTYPE_VHOST_CONFIG RTE_LOGTYPE_USER1\n#define RTE_LOGTYPE_VHOST_DATA RTE_LOGTYPE_USER2\n#define RTE_LOGTYPE_VHOST_PORT RTE_LOGTYPE_USER3\n\n/**\n * Information relating to memory regions including offsets to\n * addresses in host physical space.\n */\nstruct virtio_memory_regions_hpa {\n\t/**< Base guest physical address of region. */\n\tuint64_t guest_phys_address;\n\t/**< End guest physical address of region. */\n\tuint64_t guest_phys_address_end;\n\t/**< Size of region. */\n\tuint64_t memory_size;\n\t/**< Offset of region for gpa to hpa translation. */\n\tuint64_t host_phys_addr_offset;\n};\n\n/*\n * Device linked list structure for data path.\n */\nstruct vhost_dev {\n\t/**< Pointer to device created by vhost lib. */\n\tstruct virtio_net *dev;\n\t/**< Number of memory regions for gpa to hpa translation. */\n\tuint32_t nregions_hpa;\n\t/**< Memory region information for gpa to hpa translation. */\n\tstruct virtio_memory_regions_hpa *regions_hpa;\n\t/**< Device MAC address (Obtained on first TX packet). */\n\tstruct ether_addr mac_address;\n\t/**< RX VMDQ queue number. */\n\tuint16_t vmdq_rx_q;\n\t/**< Vlan tag assigned to the pool */\n\tuint32_t vlan_tag;\n\t/**< Data core that the device is added to. */\n\tuint16_t coreid;\n\t/**< A device is set as ready if the MAC address has been set. */\n\tvolatile uint8_t ready;\n\t/**< Device is marked for removal from the data core. */\n\tvolatile uint8_t remove;\n} __rte_cache_aligned;\n\nstruct virtio_net_data_ll\n{\n\tstruct vhost_dev\t\t*vdev;\t/* Pointer to device created by configuration core. */\n\tstruct virtio_net_data_ll\t*next; /* Pointer to next device in linked list. */\n};\n\n/*\n * Structure containing data core specific information.\n */\nstruct lcore_ll_info\n{\n\tstruct virtio_net_data_ll\t*ll_root_free; \t\t/* Pointer to head in free linked list. */\n\tstruct virtio_net_data_ll\t*ll_root_used;\t\t/* Pointer to head of used linked list. */\n\tuint32_t \t\t\t\t\tdevice_num;\t\t\t/* Number of devices on lcore. */\n\tvolatile uint8_t\t\t\tdev_removal_flag;\t/* Flag to synchronize device removal. */\n};\n\nstruct lcore_info\n{\n\tstruct lcore_ll_info\t*lcore_ll;\t/* Pointer to data core specific lcore_ll_info struct */\n};\n\n#endif /* _MAIN_H_ */\n" }, { "path": "examples/vhost_xen/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = vhost-switch\n\n# all source are stored in SRCS-y\nSRCS-y := main.c vhost_monitor.c xenstore_parse.c\n\nCFLAGS += -O2 -I/usr/local/include -D_FILE_OFFSET_BITS=64 -Wno-unused-parameter\nCFLAGS += $(WERROR_FLAGS)\nLDFLAGS += -lxenstore\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/vhost_xen/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"main.h\"\n#include \"virtio-net.h\"\n#include \"xen_vhost.h\"\n\n#define MAX_QUEUES 128\n\n/* the maximum number of external ports supported */\n#define MAX_SUP_PORTS 1\n\n/*\n * Calculate the number of buffers needed per port\n */\n#define NUM_MBUFS_PER_PORT ((MAX_QUEUES*RTE_TEST_RX_DESC_DEFAULT) +\t\t\\\n\t\t\t\t\t\t\t(num_switching_cores*MAX_PKT_BURST) + \t\t\t\\\n\t\t\t\t\t\t\t(num_switching_cores*RTE_TEST_TX_DESC_DEFAULT) +\\\n\t\t\t\t\t\t\t(num_switching_cores*MBUF_CACHE_SIZE))\n\n#define MBUF_CACHE_SIZE 64\n\n/*\n * RX and TX Prefetch, Host, and Write-back threshold values should be\n * carefully set for optimal performance. Consult the network\n * controller's datasheet and supporting DPDK documentation for guidance\n * on how these parameters should be set.\n */\n#define RX_PTHRESH 8 /* Default values of RX prefetch threshold reg. */\n#define RX_HTHRESH 8 /* Default values of RX host threshold reg. */\n#define RX_WTHRESH 4 /* Default values of RX write-back threshold reg. */\n\n/*\n * These default values are optimized for use with the Intel(R) 82599 10 GbE\n * Controller and the DPDK ixgbe PMD. Consider using other values for other\n * network controllers and/or network drivers.\n */\n#define TX_PTHRESH 36 /* Default values of TX prefetch threshold reg. */\n#define TX_HTHRESH 0 /* Default values of TX host threshold reg. */\n#define TX_WTHRESH 0 /* Default values of TX write-back threshold reg. */\n\n#define MAX_PKT_BURST 32\t\t/* Max burst size for RX/TX */\n#define MAX_MRG_PKT_BURST 16\t/* Max burst for merge buffers. Set to 1 due to performance issue. */\n#define BURST_TX_DRAIN_US 100\t/* TX drain every ~100us */\n\n/* State of virtio device. */\n#define DEVICE_NOT_READY 0\n#define DEVICE_READY 1\n#define DEVICE_SAFE_REMOVE 2\n\n/* Config_core_flag status definitions. */\n#define REQUEST_DEV_REMOVAL 1\n#define ACK_DEV_REMOVAL 0\n\n/* Configurable number of RX/TX ring descriptors */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\n\n#define INVALID_PORT_ID 0xFF\n\n/* Max number of devices. Limited by vmdq. */\n#define MAX_DEVICES 64\n\n/* Size of buffers used for snprintfs. */\n#define MAX_PRINT_BUFF 6072\n\n\n/* Maximum long option length for option parsing. */\n#define MAX_LONG_OPT_SZ 64\n\n/* Used to compare MAC addresses. */\n#define MAC_ADDR_CMP 0xFFFFFFFFFFFF\n\n/* mask of enabled ports */\nstatic uint32_t enabled_port_mask = 0;\n\n/*Number of switching cores enabled*/\nstatic uint32_t num_switching_cores = 0;\n\n/* number of devices/queues to support*/\nstatic uint32_t num_queues = 0;\nuint32_t num_devices = 0;\n\n/* Enable VM2VM communications. If this is disabled then the MAC address compare is skipped. */\nstatic uint32_t enable_vm2vm = 1;\n/* Enable stats. */\nstatic uint32_t enable_stats = 0;\n\n/* empty vmdq configuration structure. Filled in programatically */\nstatic const struct rte_eth_conf vmdq_conf_default = {\n\t.rxmode = {\n\t\t.mq_mode = ETH_MQ_RX_VMDQ_ONLY,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t/*\n\t\t * It is necessary for 1G NIC such as I350,\n\t\t * this fixes bug of ipv4 forwarding in guest can't\n\t\t * forward pakets from one virtio dev to another virtio dev.\n\t\t */\n\t\t.hw_vlan_strip = 1, /**< VLAN strip enabled. */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t\t.hw_strip_crc = 0, /**< CRC stripped by hardware */\n\t},\n\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n\t.rx_adv_conf = {\n\t\t/*\n\t\t * should be overridden separately in code with\n\t\t * appropriate values\n\t\t */\n\t\t.vmdq_rx_conf = {\n\t\t\t.nb_queue_pools = ETH_8_POOLS,\n\t\t\t.enable_default_pool = 0,\n\t\t\t.default_pool = 0,\n\t\t\t.nb_pool_maps = 0,\n\t\t\t.pool_map = {{0, 0},},\n\t\t},\n\t},\n};\n\nstatic unsigned lcore_ids[RTE_MAX_LCORE];\nstatic uint8_t ports[RTE_MAX_ETHPORTS];\nstatic unsigned num_ports = 0; /**< The number of ports specified in command line */\n\nconst uint16_t vlan_tags[] = {\n\t1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,\n\t1008, 1009, 1010, 1011,\t1012, 1013, 1014, 1015,\n\t1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,\n\t1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031,\n\t1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,\n\t1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047,\n\t1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,\n\t1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063,\n};\n\n/* ethernet addresses of ports */\nstatic struct ether_addr vmdq_ports_eth_addr[RTE_MAX_ETHPORTS];\n\n/* heads for the main used and free linked lists for the data path. */\nstatic struct virtio_net_data_ll *ll_root_used = NULL;\nstatic struct virtio_net_data_ll *ll_root_free = NULL;\n\n/* Array of data core structures containing information on individual core linked lists. */\nstatic struct lcore_info lcore_info[RTE_MAX_LCORE];\n\n/* Used for queueing bursts of TX packets. */\nstruct mbuf_table {\n\tunsigned len;\n\tunsigned txq_id;\n\tstruct rte_mbuf *m_table[MAX_PKT_BURST];\n};\n\n/* TX queue for each data core. */\nstruct mbuf_table lcore_tx_queue[RTE_MAX_LCORE];\n\n/* Vlan header struct used to insert vlan tags on TX. */\nstruct vlan_ethhdr {\n\tunsigned char h_dest[ETH_ALEN];\n\tunsigned char h_source[ETH_ALEN];\n\t__be16 h_vlan_proto;\n\t__be16 h_vlan_TCI;\n\t__be16 h_vlan_encapsulated_proto;\n};\n\n/* Header lengths. */\n#define VLAN_HLEN 4\n#define VLAN_ETH_HLEN 18\n\n/* Per-device statistics struct */\nstruct device_statistics {\n\tuint64_t tx_total;\n\trte_atomic64_t rx_total;\n\tuint64_t tx;\n\trte_atomic64_t rx;\n} __rte_cache_aligned;\nstruct device_statistics dev_statistics[MAX_DEVICES];\n\n/*\n * Builds up the correct configuration for VMDQ VLAN pool map\n * according to the pool & queue limits.\n */\nstatic inline int\nget_eth_conf(struct rte_eth_conf *eth_conf, uint32_t num_devices)\n{\n\tstruct rte_eth_vmdq_rx_conf conf;\n\tunsigned i;\n\n\tmemset(&conf, 0, sizeof(conf));\n\tconf.nb_queue_pools = (enum rte_eth_nb_pools)num_devices;\n\tconf.nb_pool_maps = num_devices;\n\n\tfor (i = 0; i < conf.nb_pool_maps; i++) {\n\t\tconf.pool_map[i].vlan_id = vlan_tags[ i ];\n\t\tconf.pool_map[i].pools = (1UL << i);\n\t}\n\n\t(void)(rte_memcpy(eth_conf, &vmdq_conf_default, sizeof(*eth_conf)));\n\t(void)(rte_memcpy(ð_conf->rx_adv_conf.vmdq_rx_conf, &conf,\n\t\t sizeof(eth_conf->rx_adv_conf.vmdq_rx_conf)));\n\treturn 0;\n}\n\n/*\n * Validate the device number according to the max pool number gotten form dev_info\n * If the device number is invalid, give the error message and return -1.\n * Each device must have its own pool.\n */\nstatic inline int\nvalidate_num_devices(uint32_t max_nb_devices)\n{\n\tif (num_devices > max_nb_devices) {\n\t\tRTE_LOG(ERR, VHOST_PORT, \"invalid number of devices\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/*\n * Initialises a given port using global settings and with the rx buffers\n * coming from the mbuf_pool passed as parameter\n */\nstatic inline int\nport_init(uint8_t port, struct rte_mempool *mbuf_pool)\n{\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_rxconf *rxconf;\n\tstruct rte_eth_conf port_conf;\n\tuint16_t rx_rings, tx_rings = (uint16_t)rte_lcore_count();\n\tconst uint16_t rx_ring_size = RTE_TEST_RX_DESC_DEFAULT, tx_ring_size = RTE_TEST_TX_DESC_DEFAULT;\n\tint retval;\n\tuint16_t q;\n\n\t/* The max pool number from dev_info will be used to validate the pool number specified in cmd line */\n\trte_eth_dev_info_get (port, &dev_info);\n\n\t/*configure the number of supported virtio devices based on VMDQ limits */\n\tnum_devices = dev_info.max_vmdq_pools;\n\tnum_queues = dev_info.max_rx_queues;\n\n\tretval = validate_num_devices(MAX_DEVICES);\n\tif (retval < 0)\n\t\treturn retval;\n\n\t/* Get port configuration. */\n\tretval = get_eth_conf(&port_conf, num_devices);\n\tif (retval < 0)\n\t\treturn retval;\n\n\tif (port >= rte_eth_dev_count()) return -1;\n\n\trx_rings = (uint16_t)num_queues,\n\t/* Configure ethernet device. */\n\tretval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);\n\tif (retval != 0)\n\t\treturn retval;\n\n\trte_eth_dev_info_get(port, &dev_info);\n\trxconf = &dev_info.default_rxconf;\n\trxconf->rx_drop_en = 1;\n\t/* Setup the queues. */\n\tfor (q = 0; q < rx_rings; q ++) {\n\t\tretval = rte_eth_rx_queue_setup(port, q, rx_ring_size,\n\t\t\t\t\t\trte_eth_dev_socket_id(port), rxconf,\n\t\t\t\t\t\tmbuf_pool);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\tfor (q = 0; q < tx_rings; q ++) {\n\t\tretval = rte_eth_tx_queue_setup(port, q, tx_ring_size,\n\t\t\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\t\t\tNULL);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\t/* Start the device. */\n\tretval = rte_eth_dev_start(port);\n\tif (retval < 0)\n\t\treturn retval;\n\n\trte_eth_macaddr_get(port, &vmdq_ports_eth_addr[port]);\n\tRTE_LOG(INFO, VHOST_PORT, \"Max virtio devices supported: %u\\n\", num_devices);\n\tRTE_LOG(INFO, VHOST_PORT, \"Port %u MAC: %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\n\t\t\t\" %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\"\\n\",\n\t\t\t(unsigned)port,\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[0],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[1],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[2],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[3],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[4],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[5]);\n\n\treturn 0;\n}\n\n/*\n * Parse the portmask provided at run time.\n */\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\terrno = 0;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0') || (errno != 0))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n\n}\n\n/*\n * Parse num options at run time.\n */\nstatic int\nparse_num_opt(const char *q_arg, uint32_t max_valid_value)\n{\n\tchar *end = NULL;\n\tunsigned long num;\n\n\terrno = 0;\n\n\t/* parse unsigned int string */\n\tnum = strtoul(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0') || (errno != 0))\n\t\treturn -1;\n\n\tif (num > max_valid_value)\n\t\treturn -1;\n\n\treturn num;\n\n}\n\n/*\n * Display usage\n */\nstatic void\nus_vhost_usage(const char *prgname)\n{\n\tRTE_LOG(INFO, VHOST_CONFIG, \"%s [EAL options] -- -p PORTMASK --vm2vm [0|1] --stats [0-N] --nb-devices ND\\n\"\n\t\"\t\t-p PORTMASK: Set mask for ports to be used by application\\n\"\n\t\"\t\t--vm2vm [0|1]: disable/enable(default) vm2vm comms\\n\"\n\t\"\t\t--stats [0-N]: 0: Disable stats, N: Time in seconds to print stats\\n\",\n\t prgname);\n}\n\n/*\n * Parse the arguments given in the command line of the application.\n */\nstatic int\nus_vhost_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tint option_index;\n\tunsigned i;\n\tconst char *prgname = argv[0];\n\tstatic struct option long_option[] = {\n\t\t{\"vm2vm\", required_argument, NULL, 0},\n\t\t{\"stats\", required_argument, NULL, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\t/* Parse command line */\n\twhile ((opt = getopt_long(argc, argv, \"p:\",long_option, &option_index)) != EOF) {\n\t\tswitch (opt) {\n\t\t/* Portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG, \"Invalid portmask\\n\");\n\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase 0:\n\t\t\t/* Enable/disable vm2vm comms. */\n\t\t\tif (!strncmp(long_option[option_index].name, \"vm2vm\", MAX_LONG_OPT_SZ)) {\n\t\t\t\tret = parse_num_opt(optarg, 1);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG, \"Invalid argument for vm2vm [0|1]\\n\");\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else {\n\t\t\t\t\tenable_vm2vm = ret;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Enable/disable stats. */\n\t\t\tif (!strncmp(long_option[option_index].name, \"stats\", MAX_LONG_OPT_SZ)) {\n\t\t\t\tret = parse_num_opt(optarg, INT32_MAX);\n\t\t\t\tif (ret == -1) {\n\t\t\t\t\tRTE_LOG(INFO, VHOST_CONFIG, \"Invalid argument for stats [0..N]\\n\");\n\t\t\t\t\tus_vhost_usage(prgname);\n\t\t\t\t\treturn -1;\n\t\t\t\t} else {\n\t\t\t\t\tenable_stats = ret;\n\t\t\t\t}\n\t\t\t}\n\t\t\tbreak;\n\n\t\t\t/* Invalid option - print options. */\n\t\tdefault:\n\t\t\tus_vhost_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif (enabled_port_mask & (1 << i))\n\t\t\tports[num_ports++] = (uint8_t)i;\n\t}\n\n\tif ((num_ports == 0) || (num_ports > MAX_SUP_PORTS)) {\n\t\tRTE_LOG(INFO, VHOST_PORT, \"Current enabled port number is %u,\"\n\t\t\t\"but only %u port can be enabled\\n\",num_ports, MAX_SUP_PORTS);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Update the global var NUM_PORTS and array PORTS according to system ports number\n * and return valid ports number\n */\nstatic unsigned check_ports_num(unsigned nb_ports)\n{\n\tunsigned valid_num_ports = num_ports;\n\tunsigned portid;\n\n\tif (num_ports > nb_ports) {\n\t\tRTE_LOG(INFO, VHOST_PORT, \"\\nSpecified port number(%u) exceeds total system port number(%u)\\n\",\n\t\t\tnum_ports, nb_ports);\n\t\tnum_ports = nb_ports;\n\t}\n\n\tfor (portid = 0; portid < num_ports; portid ++) {\n\t\tif (ports[portid] >= nb_ports) {\n\t\t\tRTE_LOG(INFO, VHOST_PORT, \"\\nSpecified port ID(%u) exceeds max system port ID(%u)\\n\",\n\t\t\t\tports[portid], (nb_ports - 1));\n\t\t\tports[portid] = INVALID_PORT_ID;\n\t\t\tvalid_num_ports--;\n\t\t}\n\t}\n\treturn valid_num_ports;\n}\n\n/*\n * Macro to print out packet contents. Wrapped in debug define so that the\n * data path is not effected when debug is disabled.\n */\n#ifdef DEBUG\n#define PRINT_PACKET(device, addr, size, header) do {\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tchar *pkt_addr = (char*)(addr);\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tunsigned int index;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tchar packet[MAX_PRINT_BUFF];\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif ((header))\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tsnprintf(packet, MAX_PRINT_BUFF, \"(%\"PRIu64\") Header size %d: \", (device->device_fh), (size));\t\t\t\t\\\n\telse\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tsnprintf(packet, MAX_PRINT_BUFF, \"(%\"PRIu64\") Packet size %d: \", (device->device_fh), (size));\t\t\t\t\\\n\tfor (index = 0; index < (size); index++) {\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tsnprintf(packet + strnlen(packet, MAX_PRINT_BUFF), MAX_PRINT_BUFF - strnlen(packet, MAX_PRINT_BUFF),\t\\\n\t\t\t\"%02hhx \", pkt_addr[index]);\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tsnprintf(packet + strnlen(packet, MAX_PRINT_BUFF), MAX_PRINT_BUFF - strnlen(packet, MAX_PRINT_BUFF), \"\\n\");\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tLOG_DEBUG(VHOST_DATA, \"%s\", packet);\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n} while(0)\n#else\n#define PRINT_PACKET(device, addr, size, header) do{} while(0)\n#endif\n\n/*\n * Function to convert guest physical addresses to vhost virtual addresses. This\n * is used to convert virtio buffer addresses.\n */\nstatic inline uint64_t __attribute__((always_inline))\ngpa_to_vva(struct virtio_net *dev, uint64_t guest_pa)\n{\n\tstruct virtio_memory_regions *region;\n\tuint32_t regionidx;\n\tuint64_t vhost_va = 0;\n\n\tfor (regionidx = 0; regionidx < dev->mem->nregions; regionidx++) {\n\t\tregion = &dev->mem->regions[regionidx];\n\t\tif ((guest_pa >= region->guest_phys_address) &&\n\t\t\t(guest_pa <= region->guest_phys_address_end)) {\n\t\t\tvhost_va = region->address_offset + guest_pa;\n\t\t\tbreak;\n\t\t}\n\t}\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") GPA %p| VVA %p\\n\",\n\t\tdev->device_fh, (void*)(uintptr_t)guest_pa, (void*)(uintptr_t)vhost_va);\n\n\treturn vhost_va;\n}\n\n/*\n * This function adds buffers to the virtio devices RX virtqueue. Buffers can\n * be received from the physical port or from another virtio device. A packet\n * count is returned to indicate the number of packets that were succesfully\n * added to the RX queue.\n */\nstatic inline uint32_t __attribute__((always_inline))\nvirtio_dev_rx(struct virtio_net *dev, struct rte_mbuf **pkts, uint32_t count)\n{\n\tstruct vhost_virtqueue *vq;\n\tstruct vring_desc *desc;\n\tstruct rte_mbuf *buff;\n\t/* The virtio_hdr is initialised to 0. */\n\tstruct virtio_net_hdr_mrg_rxbuf virtio_hdr = {{0,0,0,0,0,0},0};\n\tuint64_t buff_addr = 0;\n\tuint64_t buff_hdr_addr = 0;\n\tuint32_t head[MAX_PKT_BURST], packet_len = 0;\n\tuint32_t head_idx, packet_success = 0;\n\tuint16_t avail_idx, res_cur_idx;\n\tuint16_t res_base_idx, res_end_idx;\n\tuint16_t free_entries;\n\tuint8_t success = 0;\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") virtio_dev_rx()\\n\", dev->device_fh);\n\tvq = dev->virtqueue_rx;\n\tcount = (count > MAX_PKT_BURST) ? MAX_PKT_BURST : count;\n\t/* As many data cores may want access to available buffers, they need to be reserved. */\n\tdo {\n\n\t\tres_base_idx = vq->last_used_idx_res;\n\n\t\tavail_idx = *((volatile uint16_t *)&vq->avail->idx);\n\n\t\tfree_entries = (avail_idx - res_base_idx);\n\n\t\t/*check that we have enough buffers*/\n\t\tif (unlikely(count > free_entries))\n\t\t\tcount = free_entries;\n\n\t\tif (count == 0)\n\t\t\treturn 0;\n\n\t\tres_end_idx = res_base_idx + count;\n\t\t/* vq->last_used_idx_res is atomically updated. */\n\t\tsuccess = rte_atomic16_cmpset(&vq->last_used_idx_res, res_base_idx,\n\t\t\t\t\t\t\t\t\tres_end_idx);\n\t} while (unlikely(success == 0));\n\tres_cur_idx = res_base_idx;\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") Current Index %d| End Index %d\\n\", dev->device_fh, res_cur_idx, res_end_idx);\n\n\t/* Prefetch available ring to retrieve indexes. */\n\trte_prefetch0(&vq->avail->ring[res_cur_idx & (vq->size - 1)]);\n\n\t/* Retrieve all of the head indexes first to avoid caching issues. */\n\tfor (head_idx = 0; head_idx < count; head_idx++)\n\t\thead[head_idx] = vq->avail->ring[(res_cur_idx + head_idx) & (vq->size - 1)];\n\n\t/*Prefetch descriptor index. */\n\trte_prefetch0(&vq->desc[head[packet_success]]);\n\n\twhile (res_cur_idx != res_end_idx) {\n\t\t/* Get descriptor from available ring */\n\t\tdesc = &vq->desc[head[packet_success]];\n\t\t/* Prefetch descriptor address. */\n\t\trte_prefetch0(desc);\n\n\t\tbuff = pkts[packet_success];\n\n\t\t/* Convert from gpa to vva (guest physical addr -> vhost virtual addr) */\n\t\tbuff_addr = gpa_to_vva(dev, desc->addr);\n\t\t/* Prefetch buffer address. */\n\t\trte_prefetch0((void*)(uintptr_t)buff_addr);\n\n\t\t{\n\t\t\t/* Copy virtio_hdr to packet and increment buffer address */\n\t\t\tbuff_hdr_addr = buff_addr;\n\t\t\tpacket_len = rte_pktmbuf_data_len(buff) + vq->vhost_hlen;\n\n\t\t\t/*\n\t\t\t * If the descriptors are chained the header and data are placed in\n\t\t\t * separate buffers.\n\t\t\t */\n\t\t\tif (desc->flags & VRING_DESC_F_NEXT) {\n\t\t\t\tdesc->len = vq->vhost_hlen;\n\t\t\t\tdesc = &vq->desc[desc->next];\n\t\t\t\t/* Buffer address translation. */\n\t\t\t\tbuff_addr = gpa_to_vva(dev, desc->addr);\n\t\t\t\tdesc->len = rte_pktmbuf_data_len(buff);\n\t\t\t} else {\n\t\t\t\tbuff_addr += vq->vhost_hlen;\n\t\t\t\tdesc->len = packet_len;\n\t\t\t}\n\t\t}\n\n\t\t/* Update used ring with desc information */\n\t\tvq->used->ring[res_cur_idx & (vq->size - 1)].id = head[packet_success];\n\t\tvq->used->ring[res_cur_idx & (vq->size - 1)].len = packet_len;\n\n\t\t/* Copy mbuf data to buffer */\n\t\trte_memcpy((void *)(uintptr_t)buff_addr, (const void*)buff->data, rte_pktmbuf_data_len(buff));\n\n\t\tres_cur_idx++;\n\t\tpacket_success++;\n\n\t\t/* mergeable is disabled then a header is required per buffer. */\n\t\trte_memcpy((void *)(uintptr_t)buff_hdr_addr, (const void*)&virtio_hdr, vq->vhost_hlen);\n\t\tif (res_cur_idx < res_end_idx) {\n\t\t\t/* Prefetch descriptor index. */\n\t\t\trte_prefetch0(&vq->desc[head[packet_success]]);\n\t\t}\n\t}\n\n\trte_compiler_barrier();\n\n\t/* Wait until it's our turn to add our buffer to the used ring. */\n\twhile (unlikely(vq->last_used_idx != res_base_idx))\n\t\trte_pause();\n\n\t*(volatile uint16_t *)&vq->used->idx += count;\n\n\tvq->last_used_idx = res_end_idx;\n\n\treturn count;\n}\n\n/*\n * Compares a packet destination MAC address to a device MAC address.\n */\nstatic inline int __attribute__((always_inline))\nether_addr_cmp(struct ether_addr *ea, struct ether_addr *eb)\n{\n\treturn (((*(uint64_t *)ea ^ *(uint64_t *)eb) & MAC_ADDR_CMP) == 0);\n}\n\n/*\n * This function registers mac along with a\n * vlan tag to a VMDQ.\n */\nstatic int\nlink_vmdq(struct virtio_net *dev)\n{\n\tint ret;\n\tstruct virtio_net_data_ll *dev_ll;\n\n\tdev_ll = ll_root_used;\n\n\twhile (dev_ll != NULL) {\n\t\tif ((dev != dev_ll->dev) && ether_addr_cmp(&dev->mac_address, &dev_ll->dev->mac_address)) {\n\t\t\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") WARNING: This device is using an existing MAC address and has not been registered.\\n\", dev->device_fh);\n\t\t\treturn -1;\n\t\t}\n\t\tdev_ll = dev_ll->next;\n\t}\n\n\t/* vlan_tag currently uses the device_id. */\n\tdev->vlan_tag = vlan_tags[dev->device_fh];\n\tdev->vmdq_rx_q = dev->device_fh * (num_queues/num_devices);\n\n\t/* Print out VMDQ registration info. */\n\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") MAC_ADDRESS %02x:%02x:%02x:%02x:%02x:%02x and VLAN_TAG %d registered\\n\",\n\t\tdev->device_fh,\n\t\tdev->mac_address.addr_bytes[0], dev->mac_address.addr_bytes[1],\n\t\tdev->mac_address.addr_bytes[2], dev->mac_address.addr_bytes[3],\n\t\tdev->mac_address.addr_bytes[4], dev->mac_address.addr_bytes[5],\n\t\tdev->vlan_tag);\n\n\t/* Register the MAC address. */\n\tret = rte_eth_dev_mac_addr_add(ports[0], &dev->mac_address, (uint32_t)dev->device_fh);\n\tif (ret) {\n\t\tRTE_LOG(ERR, VHOST_DATA, \"(%\"PRIu64\") Failed to add device MAC address to VMDQ\\n\",\n\t\t\t\t\t\t\t\t\t\tdev->device_fh);\n\t\treturn -1;\n\t}\n\n\t/* Enable stripping of the vlan tag as we handle routing. */\n\trte_eth_dev_set_vlan_strip_on_queue(ports[0], dev->vmdq_rx_q, 1);\n\n\trte_compiler_barrier();\n\t/* Set device as ready for RX. */\n\tdev->ready = DEVICE_READY;\n\n\treturn 0;\n}\n\n/*\n * Removes MAC address and vlan tag from VMDQ. Ensures that nothing is adding buffers to the RX\n * queue before disabling RX on the device.\n */\nstatic inline void\nunlink_vmdq(struct virtio_net *dev)\n{\n\tunsigned i = 0;\n\tunsigned rx_count;\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\n\tif (dev->ready == DEVICE_READY) {\n\t\t/*clear MAC and VLAN settings*/\n\t\trte_eth_dev_mac_addr_remove(ports[0], &dev->mac_address);\n\t\tfor (i = 0; i < 6; i++)\n\t\t\tdev->mac_address.addr_bytes[i] = 0;\n\n\t\tdev->vlan_tag = 0;\n\n\t\t/*Clear out the receive buffers*/\n\t\trx_count = rte_eth_rx_burst(ports[0],\n\t\t\t\t\t(uint16_t)dev->vmdq_rx_q, pkts_burst, MAX_PKT_BURST);\n\n\t\twhile (rx_count) {\n\t\t\tfor (i = 0; i < rx_count; i++)\n\t\t\t\trte_pktmbuf_free(pkts_burst[i]);\n\n\t\t\trx_count = rte_eth_rx_burst(ports[0],\n\t\t\t\t\t(uint16_t)dev->vmdq_rx_q, pkts_burst, MAX_PKT_BURST);\n\t\t}\n\n\t\tdev->ready = DEVICE_NOT_READY;\n\t}\n}\n\n/*\n * Check if the packet destination MAC address is for a local device. If so then put\n * the packet on that devices RX queue. If not then return.\n */\nstatic inline unsigned __attribute__((always_inline))\nvirtio_tx_local(struct virtio_net *dev, struct rte_mbuf *m)\n{\n\tstruct virtio_net_data_ll *dev_ll;\n\tstruct ether_hdr *pkt_hdr;\n\tuint64_t ret = 0;\n\n\tpkt_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\t/*get the used devices list*/\n\tdev_ll = ll_root_used;\n\n\twhile (dev_ll != NULL) {\n\t\tif (likely(dev_ll->dev->ready == DEVICE_READY) && ether_addr_cmp(&(pkt_hdr->d_addr),\n\t\t\t\t &dev_ll->dev->mac_address)) {\n\n\t\t\t/* Drop the packet if the TX packet is destined for the TX device. */\n\t\t\tif (dev_ll->dev->device_fh == dev->device_fh) {\n\t\t\t\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") TX: Source and destination MAC addresses are the same. Dropping packet.\\n\",\n\t\t\t\t\t\t\tdev_ll->dev->device_fh);\n\t\t\t\treturn 0;\n\t\t\t}\n\n\n\t\t\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") TX: MAC address is local\\n\", dev_ll->dev->device_fh);\n\n\t\t\tif (dev_ll->dev->remove) {\n\t\t\t\t/*drop the packet if the device is marked for removal*/\n\t\t\t\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") Device is marked for removal\\n\", dev_ll->dev->device_fh);\n\t\t\t} else {\n\t\t\t\t/*send the packet to the local virtio device*/\n\t\t\t\tret = virtio_dev_rx(dev_ll->dev, &m, 1);\n\t\t\t\tif (enable_stats) {\n\t\t\t\t\trte_atomic64_add(&dev_statistics[dev_ll->dev->device_fh].rx_total, 1);\n\t\t\t\t\trte_atomic64_add(&dev_statistics[dev_ll->dev->device_fh].rx, ret);\n\t\t\t\t\tdev_statistics[dev->device_fh].tx_total++;\n\t\t\t\t\tdev_statistics[dev->device_fh].tx += ret;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\treturn 0;\n\t\t}\n\t\tdev_ll = dev_ll->next;\n\t}\n\n\treturn -1;\n}\n\n/*\n * This function routes the TX packet to the correct interface. This may be a local device\n * or the physical port.\n */\nstatic inline void __attribute__((always_inline))\nvirtio_tx_route(struct virtio_net* dev, struct rte_mbuf *m, struct rte_mempool *mbuf_pool, uint16_t vlan_tag)\n{\n\tstruct mbuf_table *tx_q;\n\tstruct vlan_ethhdr *vlan_hdr;\n\tstruct rte_mbuf **m_table;\n\tstruct rte_mbuf *mbuf;\n\tunsigned len, ret;\n\tconst uint16_t lcore_id = rte_lcore_id();\n\n\t/*check if destination is local VM*/\n\tif (enable_vm2vm && (virtio_tx_local(dev, m) == 0)) {\n\t\treturn;\n\t}\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") TX: MAC address is external\\n\", dev->device_fh);\n\n\t/*Add packet to the port tx queue*/\n\ttx_q = &lcore_tx_queue[lcore_id];\n\tlen = tx_q->len;\n\n\t/* Allocate an mbuf and populate the structure. */\n\tmbuf = rte_pktmbuf_alloc(mbuf_pool);\n\tif(!mbuf)\n\t\treturn;\n\n\tmbuf->data_len = m->data_len + VLAN_HLEN;\n\tmbuf->pkt_len = mbuf->data_len;\n\n\t/* Copy ethernet header to mbuf. */\n\trte_memcpy(rte_pktmbuf_mtod(mbuf, void*),\n\t\t\trte_pktmbuf_mtod(m, const void*), ETH_HLEN);\n\n\n\t/* Setup vlan header. Bytes need to be re-ordered for network with htons()*/\n\tvlan_hdr = rte_pktmbuf_mtod(mbuf, struct vlan_ethhdr *);\n\tvlan_hdr->h_vlan_encapsulated_proto = vlan_hdr->h_vlan_proto;\n\tvlan_hdr->h_vlan_proto = htons(ETH_P_8021Q);\n\tvlan_hdr->h_vlan_TCI = htons(vlan_tag);\n\n\t/* Copy the remaining packet contents to the mbuf. */\n\trte_memcpy(rte_pktmbuf_mtod_offset(mbuf, void *, VLAN_ETH_HLEN),\n\t\trte_pktmbuf_mtod_offset(m, const void *, ETH_HLEN),\n\t\t(m->data_len - ETH_HLEN));\n\ttx_q->m_table[len] = mbuf;\n\tlen++;\n\tif (enable_stats) {\n\t\tdev_statistics[dev->device_fh].tx_total++;\n\t\tdev_statistics[dev->device_fh].tx++;\n\t}\n\n\tif (unlikely(len == MAX_PKT_BURST)) {\n\t\tm_table = (struct rte_mbuf **)tx_q->m_table;\n\t\tret = rte_eth_tx_burst(ports[0], (uint16_t)tx_q->txq_id, m_table, (uint16_t) len);\n\t\t/* Free any buffers not handled by TX and update the port stats. */\n\t\tif (unlikely(ret < len)) {\n\t\t\tdo {\n\t\t\t\trte_pktmbuf_free(m_table[ret]);\n\t\t\t} while (++ret < len);\n\t\t}\n\n\t\tlen = 0;\n\t}\n\n\ttx_q->len = len;\n\treturn;\n}\n\nstatic inline void __attribute__((always_inline))\nvirtio_dev_tx(struct virtio_net* dev, struct rte_mempool *mbuf_pool)\n{\n\tstruct rte_mbuf m;\n\tstruct vhost_virtqueue *vq;\n\tstruct vring_desc *desc;\n\tuint64_t buff_addr = 0;\n\tuint32_t head[MAX_PKT_BURST];\n\tuint32_t used_idx;\n\tuint32_t i;\n\tuint16_t free_entries, packet_success = 0;\n\tuint16_t avail_idx;\n\n\tvq = dev->virtqueue_tx;\n\tavail_idx = *((volatile uint16_t *)&vq->avail->idx);\n\n\t/* If there are no available buffers then return. */\n\tif (vq->last_used_idx == avail_idx)\n\t\treturn;\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") virtio_dev_tx()\\n\", dev->device_fh);\n\n\t/* Prefetch available ring to retrieve head indexes. */\n\trte_prefetch0(&vq->avail->ring[vq->last_used_idx & (vq->size - 1)]);\n\n\t/*get the number of free entries in the ring*/\n\tfree_entries = avail_idx - vq->last_used_idx;\n\tfree_entries = unlikely(free_entries < MAX_PKT_BURST) ? free_entries : MAX_PKT_BURST;\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") Buffers available %d\\n\", dev->device_fh, free_entries);\n\t/* Retrieve all of the head indexes first to avoid caching issues. */\n\tfor (i = 0; i < free_entries; i++)\n\t\thead[i] = vq->avail->ring[(vq->last_used_idx + i) & (vq->size - 1)];\n\n\t/* Prefetch descriptor index. */\n\trte_prefetch0(&vq->desc[head[packet_success]]);\n\n\twhile (packet_success < free_entries) {\n\t\tdesc = &vq->desc[head[packet_success]];\n\t\t/* Prefetch descriptor address. */\n\t\trte_prefetch0(desc);\n\n\t\tif (packet_success < (free_entries - 1)) {\n\t\t\t/* Prefetch descriptor index. */\n\t\t\trte_prefetch0(&vq->desc[head[packet_success+1]]);\n\t\t}\n\n\t\t/* Update used index buffer information. */\n\t\tused_idx = vq->last_used_idx & (vq->size - 1);\n\t\tvq->used->ring[used_idx].id = head[packet_success];\n\t\tvq->used->ring[used_idx].len = 0;\n\n\t\t/* Discard first buffer as it is the virtio header */\n\t\tdesc = &vq->desc[desc->next];\n\n\t\t/* Buffer address translation. */\n\t\tbuff_addr = gpa_to_vva(dev, desc->addr);\n\t\t/* Prefetch buffer address. */\n\t\trte_prefetch0((void*)(uintptr_t)buff_addr);\n\n\t\t/* Setup dummy mbuf. This is copied to a real mbuf if transmitted out the physical port. */\n\t\tm.data_len = desc->len;\n\t\tm.data_off = 0;\n\t\tm.nb_segs = 1;\n\n\t\tvirtio_tx_route(dev, &m, mbuf_pool, 0);\n\n\t\tvq->last_used_idx++;\n\t\tpacket_success++;\n\t}\n\n\trte_compiler_barrier();\n\tvq->used->idx += packet_success;\n\t/* Kick guest if required. */\n}\n\n/*\n * This function is called by each data core. It handles all RX/TX registered with the\n * core. For TX the specific lcore linked list is used. For RX, MAC addresses are compared\n * with all devices in the main linked list.\n */\nstatic int\nswitch_worker(__attribute__((unused)) void *arg)\n{\n\tstruct rte_mempool *mbuf_pool = arg;\n\tstruct virtio_net *dev = NULL;\n\tstruct rte_mbuf *pkts_burst[MAX_PKT_BURST];\n\tstruct virtio_net_data_ll *dev_ll;\n\tstruct mbuf_table *tx_q;\n\tvolatile struct lcore_ll_info *lcore_ll;\n\tconst uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;\n\tuint64_t prev_tsc, diff_tsc, cur_tsc, ret_count = 0;\n\tunsigned ret, i;\n\tconst uint16_t lcore_id = rte_lcore_id();\n\tconst uint16_t num_cores = (uint16_t)rte_lcore_count();\n\tuint16_t rx_count = 0;\n\n\tRTE_LOG(INFO, VHOST_DATA, \"Procesing on Core %u started \\n\", lcore_id);\n\tlcore_ll = lcore_info[lcore_id].lcore_ll;\n\tprev_tsc = 0;\n\n\ttx_q = &lcore_tx_queue[lcore_id];\n\tfor (i = 0; i < num_cores; i ++) {\n\t\tif (lcore_ids[i] == lcore_id) {\n\t\t\ttx_q->txq_id = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\twhile(1) {\n\t\tcur_tsc = rte_rdtsc();\n\t\t/*\n\t\t * TX burst queue drain\n\t\t */\n\t\tdiff_tsc = cur_tsc - prev_tsc;\n\t\tif (unlikely(diff_tsc > drain_tsc)) {\n\n\t\t\tif (tx_q->len) {\n\t\t\t\tLOG_DEBUG(VHOST_DATA, \"TX queue drained after timeout with burst size %u \\n\", tx_q->len);\n\n\t\t\t\t/*Tx any packets in the queue*/\n\t\t\t\tret = rte_eth_tx_burst(ports[0], (uint16_t)tx_q->txq_id,\n\t\t\t\t\t\t\t\t\t (struct rte_mbuf **)tx_q->m_table,\n\t\t\t\t\t\t\t\t\t (uint16_t)tx_q->len);\n\t\t\t\tif (unlikely(ret < tx_q->len)) {\n\t\t\t\t\tdo {\n\t\t\t\t\t\trte_pktmbuf_free(tx_q->m_table[ret]);\n\t\t\t\t\t} while (++ret < tx_q->len);\n\t\t\t\t}\n\n\t\t\t\ttx_q->len = 0;\n\t\t\t}\n\n\t\t\tprev_tsc = cur_tsc;\n\n\t\t}\n\n\t\t/*\n\t\t * Inform the configuration core that we have exited the linked list and that no devices are\n\t\t * in use if requested.\n\t\t */\n\t\tif (lcore_ll->dev_removal_flag == REQUEST_DEV_REMOVAL)\n\t\t\tlcore_ll->dev_removal_flag = ACK_DEV_REMOVAL;\n\n\t\t/*\n\t\t * Process devices\n\t \t */\n\t\tdev_ll = lcore_ll->ll_root_used;\n\n\t\twhile (dev_ll != NULL) {\n\t\t\t/*get virtio device ID*/\n\t\t\tdev = dev_ll->dev;\n\n\t\t\tif (unlikely(dev->remove)) {\n\t\t\t\tdev_ll = dev_ll->next;\n\t\t\t\tunlink_vmdq(dev);\n\t\t\t\tdev->ready = DEVICE_SAFE_REMOVE;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (likely(dev->ready == DEVICE_READY)) {\n\t\t\t\t/*Handle guest RX*/\n\t\t\t\trx_count = rte_eth_rx_burst(ports[0],\n\t\t\t\t\t(uint16_t)dev->vmdq_rx_q, pkts_burst, MAX_PKT_BURST);\n\n\t\t\t\tif (rx_count) {\n\t\t\t\t\tret_count = virtio_dev_rx(dev, pkts_burst, rx_count);\n\t\t\t\t\tif (enable_stats) {\n\t\t\t\t\t\trte_atomic64_add(&dev_statistics[dev_ll->dev->device_fh].rx_total, rx_count);\n\t\t\t\t\t\trte_atomic64_add(&dev_statistics[dev_ll->dev->device_fh].rx, ret_count);\n\t\t\t\t\t}\n\t\t\t\t\twhile (likely(rx_count)) {\n\t\t\t\t\t\trx_count--;\n\t\t\t\t\t\trte_pktmbuf_free_seg(pkts_burst[rx_count]);\n\t\t\t\t\t}\n\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tif (likely(!dev->remove))\n\t\t\t\t/*Handle guest TX*/\n\t\t\t\tvirtio_dev_tx(dev, mbuf_pool);\n\n\t\t\t/*move to the next device in the list*/\n\t\t\tdev_ll = dev_ll->next;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/*\n * Add an entry to a used linked list. A free entry must first be found in the free linked list\n * using get_data_ll_free_entry();\n */\nstatic void\nadd_data_ll_entry(struct virtio_net_data_ll **ll_root_addr, struct virtio_net_data_ll *ll_dev)\n{\n\tstruct virtio_net_data_ll *ll = *ll_root_addr;\n\n\t/* Set next as NULL and use a compiler barrier to avoid reordering. */\n\tll_dev->next = NULL;\n\trte_compiler_barrier();\n\n\t/* If ll == NULL then this is the first device. */\n\tif (ll) {\n\t\t/* Increment to the tail of the linked list. */\n\t\twhile ((ll->next != NULL) )\n\t\t\tll = ll->next;\n\n\t\tll->next = ll_dev;\n\t} else {\n\t\t*ll_root_addr = ll_dev;\n\t}\n}\n\n/*\n * Remove an entry from a used linked list. The entry must then be added to the free linked list\n * using put_data_ll_free_entry().\n */\nstatic void\nrm_data_ll_entry(struct virtio_net_data_ll **ll_root_addr, struct virtio_net_data_ll *ll_dev, struct virtio_net_data_ll *ll_dev_last)\n{\n\tstruct virtio_net_data_ll *ll = *ll_root_addr;\n\n\tif (ll_dev == ll)\n\t\t*ll_root_addr = ll_dev->next;\n\telse\n\t\tll_dev_last->next = ll_dev->next;\n}\n\n/*\n * Find and return an entry from the free linked list.\n */\nstatic struct virtio_net_data_ll *\nget_data_ll_free_entry(struct virtio_net_data_ll **ll_root_addr)\n{\n\tstruct virtio_net_data_ll *ll_free = *ll_root_addr;\n\tstruct virtio_net_data_ll *ll_dev;\n\n\tif (ll_free == NULL)\n\t\treturn NULL;\n\n\tll_dev = ll_free;\n\t*ll_root_addr = ll_free->next;\n\n\treturn ll_dev;\n}\n\n/*\n * Place an entry back on to the free linked list.\n */\nstatic void\nput_data_ll_free_entry(struct virtio_net_data_ll **ll_root_addr, struct virtio_net_data_ll *ll_dev)\n{\n\tstruct virtio_net_data_ll *ll_free = *ll_root_addr;\n\n\tll_dev->next = ll_free;\n\t*ll_root_addr = ll_dev;\n}\n\n/*\n * Creates a linked list of a given size.\n */\nstatic struct virtio_net_data_ll *\nalloc_data_ll(uint32_t size)\n{\n\tstruct virtio_net_data_ll *ll_new;\n\tuint32_t i;\n\n\t/* Malloc and then chain the linked list. */\n\tll_new = malloc(size * sizeof(struct virtio_net_data_ll));\n\tif (ll_new == NULL) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG, \"Failed to allocate memory for ll_new.\\n\");\n\t\treturn NULL;\n\t}\n\n\tfor (i = 0; i < size - 1; i++) {\n\t\tll_new[i].dev = NULL;\n\t\tll_new[i].next = &ll_new[i+1];\n\t}\n\tll_new[i].next = NULL;\n\n\treturn (ll_new);\n}\n\n/*\n * Create the main linked list along with each individual cores linked list. A used and a free list\n * are created to manage entries.\n */\nstatic int\ninit_data_ll (void)\n{\n\tint lcore;\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\tlcore_info[lcore].lcore_ll = malloc(sizeof(struct lcore_ll_info));\n\t\tif (lcore_info[lcore].lcore_ll == NULL) {\n\t\t\tRTE_LOG(ERR, VHOST_CONFIG, \"Failed to allocate memory for lcore_ll.\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tlcore_info[lcore].lcore_ll->device_num = 0;\n\t\tlcore_info[lcore].lcore_ll->dev_removal_flag = ACK_DEV_REMOVAL;\n\t\tlcore_info[lcore].lcore_ll->ll_root_used = NULL;\n\t\tif (num_devices % num_switching_cores)\n\t\t\tlcore_info[lcore].lcore_ll->ll_root_free = alloc_data_ll((num_devices / num_switching_cores) + 1);\n\t\telse\n\t\t\tlcore_info[lcore].lcore_ll->ll_root_free = alloc_data_ll(num_devices / num_switching_cores);\n\t}\n\n\t/* Allocate devices up to a maximum of MAX_DEVICES. */\n\tll_root_free = alloc_data_ll(MIN((num_devices), MAX_DEVICES));\n\n\treturn 0;\n}\n/*\n * Remove a device from the specific data core linked list and from the main linked list. The\n * rx/tx thread must be set the flag to indicate that it is safe to remove the device.\n * used.\n */\nstatic void\ndestroy_device (volatile struct virtio_net *dev)\n{\n\tstruct virtio_net_data_ll *ll_lcore_dev_cur;\n\tstruct virtio_net_data_ll *ll_main_dev_cur;\n\tstruct virtio_net_data_ll *ll_lcore_dev_last = NULL;\n\tstruct virtio_net_data_ll *ll_main_dev_last = NULL;\n\tint lcore;\n\n\tdev->flags &= ~VIRTIO_DEV_RUNNING;\n\n\t/*set the remove flag. */\n\tdev->remove = 1;\n\n\twhile(dev->ready != DEVICE_SAFE_REMOVE) {\n\t\trte_pause();\n\t}\n\n\t/* Search for entry to be removed from lcore ll */\n\tll_lcore_dev_cur = lcore_info[dev->coreid].lcore_ll->ll_root_used;\n\twhile (ll_lcore_dev_cur != NULL) {\n\t\tif (ll_lcore_dev_cur->dev == dev) {\n\t\t\tbreak;\n\t\t} else {\n\t\t\tll_lcore_dev_last = ll_lcore_dev_cur;\n\t\t\tll_lcore_dev_cur = ll_lcore_dev_cur->next;\n\t\t}\n\t}\n\n\t/* Search for entry to be removed from main ll */\n\tll_main_dev_cur = ll_root_used;\n\tll_main_dev_last = NULL;\n\twhile (ll_main_dev_cur != NULL) {\n\t\tif (ll_main_dev_cur->dev == dev) {\n\t\t\tbreak;\n\t\t} else {\n\t\t\tll_main_dev_last = ll_main_dev_cur;\n\t\t\tll_main_dev_cur = ll_main_dev_cur->next;\n\t\t}\n\t}\n\n\tif (ll_lcore_dev_cur == NULL || ll_main_dev_cur == NULL) {\n\t\tRTE_LOG(ERR, XENHOST, \"%s: could find device in per_cpu list or main_list\\n\", __func__);\n\t\treturn;\n\t}\n\n\t/* Remove entries from the lcore and main ll. */\n\trm_data_ll_entry(&lcore_info[ll_lcore_dev_cur->dev->coreid].lcore_ll->ll_root_used, ll_lcore_dev_cur, ll_lcore_dev_last);\n\trm_data_ll_entry(&ll_root_used, ll_main_dev_cur, ll_main_dev_last);\n\n\t/* Set the dev_removal_flag on each lcore. */\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\tlcore_info[lcore].lcore_ll->dev_removal_flag = REQUEST_DEV_REMOVAL;\n\t}\n\n\t/*\n\t * Once each core has set the dev_removal_flag to ACK_DEV_REMOVAL we can be sure that\n\t * they can no longer access the device removed from the linked lists and that the devices\n\t * are no longer in use.\n\t */\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\twhile (lcore_info[lcore].lcore_ll->dev_removal_flag != ACK_DEV_REMOVAL) {\n\t\t\trte_pause();\n\t\t}\n\t}\n\n\t/* Add the entries back to the lcore and main free ll.*/\n\tput_data_ll_free_entry(&lcore_info[ll_lcore_dev_cur->dev->coreid].lcore_ll->ll_root_free, ll_lcore_dev_cur);\n\tput_data_ll_free_entry(&ll_root_free, ll_main_dev_cur);\n\n\t/* Decrement number of device on the lcore. */\n\tlcore_info[ll_lcore_dev_cur->dev->coreid].lcore_ll->device_num--;\n\n\tRTE_LOG(INFO, VHOST_DATA, \" #####(%\"PRIu64\") Device has been removed from data core\\n\", dev->device_fh);\n}\n\n/*\n * A new device is added to a data core. First the device is added to the main linked list\n * and the allocated to a specific data core.\n */\nstatic int\nnew_device (struct virtio_net *dev)\n{\n\tstruct virtio_net_data_ll *ll_dev;\n\tint lcore, core_add = 0;\n\tuint32_t device_num_min = num_devices;\n\n\t/* Add device to main ll */\n\tll_dev = get_data_ll_free_entry(&ll_root_free);\n\tif (ll_dev == NULL) {\n\t\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") No free entry found in linked list. Device limit \"\n\t\t\t\"of %d devices per core has been reached\\n\",\n\t\t\tdev->device_fh, num_devices);\n\t\treturn -1;\n\t}\n\tll_dev->dev = dev;\n\tadd_data_ll_entry(&ll_root_used, ll_dev);\n\n\t/*reset ready flag*/\n\tdev->ready = DEVICE_NOT_READY;\n\tdev->remove = 0;\n\n\t/* Find a suitable lcore to add the device. */\n\tRTE_LCORE_FOREACH_SLAVE(lcore) {\n\t\tif (lcore_info[lcore].lcore_ll->device_num < device_num_min) {\n\t\t\tdevice_num_min = lcore_info[lcore].lcore_ll->device_num;\n\t\t\tcore_add = lcore;\n\t\t}\n\t}\n\t/* Add device to lcore ll */\n\tll_dev->dev->coreid = core_add;\n\tll_dev = get_data_ll_free_entry(&lcore_info[ll_dev->dev->coreid].lcore_ll->ll_root_free);\n\tif (ll_dev == NULL) {\n\t\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") Failed to add device to data core\\n\", dev->device_fh);\n\t\tdestroy_device(dev);\n\t\treturn -1;\n\t}\n\tll_dev->dev = dev;\n\tadd_data_ll_entry(&lcore_info[ll_dev->dev->coreid].lcore_ll->ll_root_used, ll_dev);\n\n\t/* Initialize device stats */\n\tmemset(&dev_statistics[dev->device_fh], 0, sizeof(struct device_statistics));\n\n\tlcore_info[ll_dev->dev->coreid].lcore_ll->device_num++;\n\tdev->flags |= VIRTIO_DEV_RUNNING;\n\n\tRTE_LOG(INFO, VHOST_DATA, \"(%\"PRIu64\") Device has been added to data core %d\\n\", dev->device_fh, dev->coreid);\n\n\tlink_vmdq(dev);\n\n\treturn 0;\n}\n\n/*\n * These callback allow devices to be added to the data core when configuration\n * has been fully complete.\n */\nstatic const struct virtio_net_device_ops virtio_net_device_ops =\n{\n\t.new_device = new_device,\n\t.destroy_device = destroy_device,\n};\n\n/*\n * This is a thread will wake up after a period to print stats if the user has\n * enabled them.\n */\nstatic void\nprint_stats(void)\n{\n\tstruct virtio_net_data_ll *dev_ll;\n\tuint64_t tx_dropped, rx_dropped;\n\tuint64_t tx, tx_total, rx, rx_total;\n\tuint32_t device_fh;\n\tconst char clr[] = { 27, '[', '2', 'J', '\\0' };\n\tconst char top_left[] = { 27, '[', '1', ';', '1', 'H','\\0' };\n\n\twhile(1) {\n\t\tsleep(enable_stats);\n\n\t\t/* Clear screen and move to top left */\n\t\tprintf(\"%s%s\", clr, top_left);\n\n\t\tprintf(\"\\nDevice statistics ====================================\");\n\n\t\tdev_ll = ll_root_used;\n\t\twhile (dev_ll != NULL) {\n\t\t\tdevice_fh = (uint32_t)dev_ll->dev->device_fh;\n\t\t\ttx_total = dev_statistics[device_fh].tx_total;\n\t\t\ttx = dev_statistics[device_fh].tx;\n\t\t\ttx_dropped = tx_total - tx;\n\t\t\trx_total = rte_atomic64_read(&dev_statistics[device_fh].rx_total);\n\t\t\trx = rte_atomic64_read(&dev_statistics[device_fh].rx);\n\t\t\trx_dropped = rx_total - rx;\n\n\t\t\tprintf(\"\\nStatistics for device %\"PRIu32\" ------------------------------\"\n\t\t\t\t\t\"\\nTX total: \t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nTX dropped: \t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nTX successful: \t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nRX total: \t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nRX dropped: \t\t%\"PRIu64\"\"\n\t\t\t\t\t\"\\nRX successful: \t\t%\"PRIu64\"\",\n\t\t\t\t\tdevice_fh,\n\t\t\t\t\ttx_total,\n\t\t\t\t\ttx_dropped,\n\t\t\t\t\ttx,\n\t\t\t\t\trx_total,\n\t\t\t\t\trx_dropped,\n\t\t\t\t\trx);\n\n\t\t\tdev_ll = dev_ll->next;\n\t\t}\n\t\tprintf(\"\\n======================================================\\n\");\n\t}\n}\n\n\nint init_virtio_net(struct virtio_net_device_ops const * const ops);\n\n/*\n * Main function, does initialisation and calls the per-lcore functions. The CUSE\n * device is also registered here to handle the IOCTLs.\n */\nint\nmain(int argc, char *argv[])\n{\n\tstruct rte_mempool *mbuf_pool;\n\tunsigned lcore_id, core_id = 0;\n\tunsigned nb_ports, valid_num_ports;\n\tint ret;\n\tuint8_t portid;\n\tstatic pthread_t tid;\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Error with EAL initialization\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse app arguments */\n\tret = us_vhost_parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid argument\\n\");\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id ++)\n\t\tif (rte_lcore_is_enabled(lcore_id))\n\t\t\tlcore_ids[core_id ++] = lcore_id;\n\n\tif (rte_lcore_count() > RTE_MAX_LCORE)\n\t\trte_exit(EXIT_FAILURE,\"Not enough cores\\n\");\n\n\t/*set the number of swithcing cores available*/\n\tnum_switching_cores = rte_lcore_count()-1;\n\n\t/* Get the number of physical ports. */\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\t/*\n\t * Update the global var NUM_PORTS and global array PORTS\n\t * and get value of var VALID_NUM_PORTS according to system ports number\n\t */\n\tvalid_num_ports = check_ports_num(nb_ports);\n\n\tif ((valid_num_ports == 0) || (valid_num_ports > MAX_SUP_PORTS)) {\n\t\tRTE_LOG(INFO, VHOST_PORT, \"Current enabled port number is %u,\"\n\t\t\t\"but only %u port can be enabled\\n\",num_ports, MAX_SUP_PORTS);\n\t\treturn -1;\n\t}\n\n\t/* Create the mbuf pool. */\n\tmbuf_pool = rte_pktmbuf_pool_create(\"MBUF_POOL\",\n\t\tNUM_MBUFS_PER_PORT * valid_num_ports, MBUF_CACHE_SIZE, 0,\n\t\tRTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\tif (mbuf_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create mbuf pool\\n\");\n\n\t/* Set log level. */\n\trte_set_log_level(LOG_LEVEL);\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tRTE_LOG(INFO, VHOST_PORT, \"Skipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\t\tif (port_init(portid, mbuf_pool) != 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot initialize network ports\\n\");\n\t}\n\n\t/* Initialise all linked lists. */\n\tif (init_data_ll() == -1)\n\t\trte_exit(EXIT_FAILURE, \"Failed to initialize linked list\\n\");\n\n\t/* Initialize device stats */\n\tmemset(&dev_statistics, 0, sizeof(dev_statistics));\n\n\t/* Enable stats if the user option is set. */\n\tif (enable_stats)\n\t\tpthread_create(&tid, NULL, (void*)print_stats, NULL );\n\n\t/* Launch all data cores. */\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\trte_eal_remote_launch(switch_worker, mbuf_pool, lcore_id);\n\t}\n\n\tinit_virtio_xen(&virtio_net_device_ops);\n\n\tvirtio_monitor_loop();\n\treturn 0;\n}\n" }, { "path": "examples/vhost_xen/main.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _MAIN_H_\n#define _MAIN_H_\n\n//#define DEBUG\n\n#ifdef DEBUG\n#define LOG_LEVEL RTE_LOG_DEBUG\n#define LOG_DEBUG(log_type, fmt, args...) \\\n\tRTE_LOG(DEBUG, log_type, fmt, ##args)\n#else\n#define LOG_LEVEL RTE_LOG_INFO\n#define LOG_DEBUG(log_type, fmt, args...) do{} while(0)\n#endif\n\n/* Macros for printing using RTE_LOG */\n#define RTE_LOGTYPE_VHOST_CONFIG RTE_LOGTYPE_USER1\n#define RTE_LOGTYPE_VHOST_DATA RTE_LOGTYPE_USER2\n#define RTE_LOGTYPE_VHOST_PORT RTE_LOGTYPE_USER3\n\n/*\n * Device linked list structure for data path.\n */\nstruct virtio_net_data_ll\n{\n\tstruct virtio_net *dev; /* Pointer to device created by configuration core. */\n\tstruct virtio_net_data_ll *next; /* Pointer to next device in linked list. */\n};\n\n/*\n * Structure containing data core specific information.\n */\nstruct lcore_ll_info\n{\n\tstruct virtio_net_data_ll *ll_root_free; \t/* Pointer to head in free linked list. */\n\tstruct virtio_net_data_ll *ll_root_used;\t /* Pointer to head of used linked list. */\n\tuint32_t device_num; /* Number of devices on lcore. */\n\tvolatile uint8_t dev_removal_flag; /* Flag to synchronize device removal. */\n};\n\nstruct lcore_info\n{\n\tstruct lcore_ll_info\t*lcore_ll;\t/* Pointer to data core specific lcore_ll_info struct */\n};\n#endif /* _MAIN_H_ */\n" }, { "path": "examples/vhost_xen/vhost_monitor.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#if __XEN_LATEST_INTERFACE_VERSION__ < 0x00040200\n#include \n#else\n#include \n#endif\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"virtio-net.h\"\n#include \"xen_vhost.h\"\n\nstruct virtio_watch {\n\tstruct xs_handle *xs;\n\tint watch_fd;\n};\n\n\n/* device ops to add/remove device to/from data core. */\nstatic struct virtio_net_device_ops const *notify_ops;\n\n/* root address of the linked list in the configuration core. */\nstatic struct virtio_net_config_ll *ll_root = NULL;\n\n/* root address of VM. */\nstatic struct xen_guestlist guest_root;\n\nstatic struct virtio_watch watch;\n\nstatic void\nvq_vring_init(struct vhost_virtqueue *vq, unsigned int num, uint8_t *p,\n\tunsigned long align)\n{\n\tvq->size = num;\n\tvq->desc = (struct vring_desc *) p;\n\tvq->avail = (struct vring_avail *) (p +\n\t\tnum * sizeof(struct vring_desc));\n\tvq->used = (void *)\n\t\tRTE_ALIGN_CEIL( (uintptr_t)(&vq->avail->ring[num]), align);\n\n}\n\nstatic int\ninit_watch(void)\n{\n\tstruct xs_handle *xs;\n\tint ret;\n\tint fd;\n\n\t/* get a connection to the daemon */\n\txs = xs_daemon_open();\n\tif (xs == NULL) {\n\t\tRTE_LOG(ERR, XENHOST, \"xs_daemon_open failed\\n\");\n\t\treturn (-1);\n\t}\n\n\tret = xs_watch(xs, \"/local/domain\", \"mytoken\");\n\tif (ret == 0) {\n\t\tRTE_LOG(ERR, XENHOST, \"%s: xs_watch failed\\n\", __func__);\n\t\txs_daemon_close(xs);\n\t\treturn (-1);\n\t}\n\n\t/* We are notified of read availability on the watch via the file descriptor. */\n\tfd = xs_fileno(xs);\n\twatch.xs = xs;\n\twatch.watch_fd = fd;\n\n\tTAILQ_INIT(&guest_root);\n\treturn 0;\n}\n\nstatic struct xen_guest *\nget_xen_guest(int dom_id)\n{\n\tstruct xen_guest *guest = NULL;\n\n\tTAILQ_FOREACH(guest, &guest_root, next) {\n\t\tif(guest->dom_id == dom_id)\n\t\t\treturn guest;\n\t}\n\n\treturn (NULL);\n}\n\n\nstatic struct xen_guest *\nadd_xen_guest(int32_t dom_id)\n{\n\tstruct xen_guest *guest = NULL;\n\n\tif ((guest = get_xen_guest(dom_id)) != NULL)\n\t\treturn guest;\n\n\tguest = calloc(1, sizeof(struct xen_guest));\n\tif (guest) {\n\t\tRTE_LOG(ERR, XENHOST, \" %s: return newly created guest with %d rings\\n\", __func__, guest->vring_num);\n\t\tTAILQ_INSERT_TAIL(&guest_root, guest, next);\n\t\tguest->dom_id = dom_id;\n\t}\n\n\treturn guest;\n}\n\nstatic void\ncleanup_device(struct virtio_net_config_ll *ll_dev)\n{\n\tif (ll_dev == NULL)\n\t\treturn;\n\tif (ll_dev->dev.virtqueue_rx) {\n\t\trte_free(ll_dev->dev.virtqueue_rx);\n\t\tll_dev->dev.virtqueue_rx = NULL;\n\t}\n\tif (ll_dev->dev.virtqueue_tx) {\n\t\trte_free(ll_dev->dev.virtqueue_tx);\n\t\tll_dev->dev.virtqueue_tx = NULL;\n\t}\n\tfree(ll_dev);\n}\n\n/*\n * Add entry containing a device to the device configuration linked list.\n */\nstatic void\nadd_config_ll_entry(struct virtio_net_config_ll *new_ll_dev)\n{\n\tstruct virtio_net_config_ll *ll_dev = ll_root;\n\n\t/* If ll_dev == NULL then this is the first device so go to else */\n\tif (ll_dev) {\n\t\t/* If the 1st device_id != 0 then we insert our device here. */\n\t\tif (ll_dev->dev.device_fh != 0)\t{\n\t\t\tnew_ll_dev->dev.device_fh = 0;\n\t\t\tnew_ll_dev->next = ll_dev;\n\t\t\tll_root = new_ll_dev;\n\t\t} else {\n\t\t\t/* increment through the ll until we find un unused device_id,\n\t\t\t * insert the device at that entry\n\t\t\t */\n\t\t\twhile ((ll_dev->next != NULL) && (ll_dev->dev.device_fh == (ll_dev->next->dev.device_fh - 1)))\n\t\t\t\tll_dev = ll_dev->next;\n\n\t\t\tnew_ll_dev->dev.device_fh = ll_dev->dev.device_fh + 1;\n\t\t\tnew_ll_dev->next = ll_dev->next;\n\t\t\tll_dev->next = new_ll_dev;\n\t\t}\n\t} else {\n\t\tll_root = new_ll_dev;\n\t\tll_root->dev.device_fh = 0;\n\t}\n}\n\n\n/*\n * Remove an entry from the device configuration linked list.\n */\nstatic struct virtio_net_config_ll *\nrm_config_ll_entry(struct virtio_net_config_ll *ll_dev, struct virtio_net_config_ll *ll_dev_last)\n{\n\t/* First remove the device and then clean it up. */\n\tif (ll_dev == ll_root) {\n\t\tll_root = ll_dev->next;\n\t\tcleanup_device(ll_dev);\n\t\treturn ll_root;\n\t} else {\n\t\tll_dev_last->next = ll_dev->next;\n\t\tcleanup_device(ll_dev);\n\t\treturn ll_dev_last->next;\n\t}\n}\n\n/*\n * Retrieves an entry from the devices configuration linked list.\n */\nstatic struct virtio_net_config_ll *\nget_config_ll_entry(unsigned int virtio_idx, unsigned int dom_id)\n{\n\tstruct virtio_net_config_ll *ll_dev = ll_root;\n\n\t/* Loop through linked list until the dom_id is found. */\n\twhile (ll_dev != NULL) {\n\t\tif (ll_dev->dev.dom_id == dom_id && ll_dev->dev.virtio_idx == virtio_idx)\n\t\t\treturn ll_dev;\n\t\tll_dev = ll_dev->next;\n\t}\n\n\treturn NULL;\n}\n\n/*\n * Initialise all variables in device structure.\n */\nstatic void\ninit_dev(struct virtio_net *dev)\n{\n\tRTE_SET_USED(dev);\n}\n\n\nstatic struct\nvirtio_net_config_ll *new_device(unsigned int virtio_idx, struct xen_guest *guest)\n{\n\tstruct virtio_net_config_ll *new_ll_dev;\n\tstruct vhost_virtqueue *virtqueue_rx, *virtqueue_tx;\n\tsize_t size, vq_ring_size, vq_size = VQ_DESC_NUM;\n\tvoid *vq_ring_virt_mem;\n\tuint64_t gpa;\n\tuint32_t i;\n\n\t/* Setup device and virtqueues. */\n\tnew_ll_dev = calloc(1, sizeof(struct virtio_net_config_ll));\n\tvirtqueue_rx = rte_zmalloc(NULL, sizeof(struct vhost_virtqueue), RTE_CACHE_LINE_SIZE);\n\tvirtqueue_tx = rte_zmalloc(NULL, sizeof(struct vhost_virtqueue), RTE_CACHE_LINE_SIZE);\n\tif (new_ll_dev == NULL || virtqueue_rx == NULL || virtqueue_tx == NULL)\n\t\tgoto err;\n\n\tnew_ll_dev->dev.virtqueue_rx = virtqueue_rx;\n\tnew_ll_dev->dev.virtqueue_tx = virtqueue_tx;\n\tnew_ll_dev->dev.dom_id = guest->dom_id;\n\tnew_ll_dev->dev.virtio_idx = virtio_idx;\n\t/* Initialise device and virtqueues. */\n\tinit_dev(&new_ll_dev->dev);\n\n\tsize = vring_size(vq_size, VIRTIO_PCI_VRING_ALIGN);\n\tvq_ring_size = RTE_ALIGN_CEIL(size, VIRTIO_PCI_VRING_ALIGN);\n\t(void)vq_ring_size;\n\n\tvq_ring_virt_mem = guest->vring[virtio_idx].rxvring_addr;\n\tvq_vring_init(virtqueue_rx, vq_size, vq_ring_virt_mem, VIRTIO_PCI_VRING_ALIGN);\n\tvirtqueue_rx->size = vq_size;\n\tvirtqueue_rx->vhost_hlen = sizeof(struct virtio_net_hdr);\n\n\tvq_ring_virt_mem = guest->vring[virtio_idx].txvring_addr;\n\tvq_vring_init(virtqueue_tx, vq_size, vq_ring_virt_mem, VIRTIO_PCI_VRING_ALIGN);\n\tvirtqueue_tx->size = vq_size;\n\tmemcpy(&new_ll_dev->dev.mac_address, &guest->vring[virtio_idx].addr, sizeof(struct ether_addr));\n\n\t/* virtio_memory has to be one per domid */\n\tnew_ll_dev->dev.mem = malloc(sizeof(struct virtio_memory) + sizeof(struct virtio_memory_regions) * MAX_XENVIRT_MEMPOOL);\n\tnew_ll_dev->dev.mem->nregions = guest->pool_num;\n\tfor (i = 0; i < guest->pool_num; i++) {\n\t\tgpa = new_ll_dev->dev.mem->regions[i].guest_phys_address = (uint64_t)guest->mempool[i].gva;\n\t\tnew_ll_dev->dev.mem->regions[i].guest_phys_address_end = gpa + guest->mempool[i].mempfn_num * getpagesize();\n\t\tnew_ll_dev->dev.mem->regions[i].address_offset = (uint64_t)guest->mempool[i].hva - gpa;\n\t}\n\n\tnew_ll_dev->next = NULL;\n\n\t/* Add entry to device configuration linked list. */\n\tadd_config_ll_entry(new_ll_dev);\n\treturn new_ll_dev;\nerr:\n\tif (new_ll_dev)\n\t\tfree(new_ll_dev);\n\trte_free(virtqueue_rx);\n\trte_free(virtqueue_tx);\n\n\treturn NULL;\n}\n\nstatic void\ndestroy_guest(struct xen_guest *guest)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < guest->vring_num; i++)\n\t\tcleanup_vring(&guest->vring[i]);\n\t/* clean mempool */\n\tfor (i = 0; i < guest->pool_num; i++)\n\t\tcleanup_mempool(&guest->mempool[i]);\n\tfree(guest);\n\n\treturn;\n}\n\n/*\n * This function will cleanup the device and remove it from device configuration linked list.\n */\nstatic void\ndestroy_device(unsigned int virtio_idx, unsigned int dom_id)\n{\n\tstruct virtio_net_config_ll *ll_dev_cur_ctx, *ll_dev_last = NULL;\n\tstruct virtio_net_config_ll *ll_dev_cur = ll_root;\n\n\t/* clean virtio device */\n\tstruct xen_guest *guest = NULL;\n\tguest = get_xen_guest(dom_id);\n\tif (guest == NULL)\n\t\treturn;\n\n\t/* Find the linked list entry for the device to be removed. */\n\tll_dev_cur_ctx = get_config_ll_entry(virtio_idx, dom_id);\n\twhile (ll_dev_cur != NULL) {\n\t\t/* If the device is found or a device that doesn't exist is found then it is removed. */\n\t\tif (ll_dev_cur == ll_dev_cur_ctx) {\n\t\t\tif ((ll_dev_cur->dev.flags & VIRTIO_DEV_RUNNING))\n\t\t\t\tnotify_ops->destroy_device(&(ll_dev_cur->dev));\n\t\t\tll_dev_cur = rm_config_ll_entry(ll_dev_cur, ll_dev_last);\n\t\t} else {\n\t\t\tll_dev_last = ll_dev_cur;\n\t\t\tll_dev_cur = ll_dev_cur->next;\n\t\t}\n\t}\n\tRTE_LOG(INFO, XENHOST, \" %s guest:%p vring:%p rxvring:%p txvring:%p flag:%p\\n\",\n\t\t__func__, guest, &guest->vring[virtio_idx], guest->vring[virtio_idx].rxvring_addr, guest->vring[virtio_idx].txvring_addr, guest->vring[virtio_idx].flag);\n\tcleanup_vring(&guest->vring[virtio_idx]);\n\tguest->vring[virtio_idx].removed = 1;\n\tguest->vring_num -= 1;\n}\n\n\n\n\nstatic void\nwatch_unmap_event(void)\n{\n\tint i;\n\tstruct xen_guest *guest = NULL;\n\tbool remove_request;\n\n\tTAILQ_FOREACH(guest, &guest_root, next) {\n\t\tfor (i = 0; i < MAX_VIRTIO; i++) {\n\t\t\tif (guest->vring[i].dom_id && guest->vring[i].removed == 0 && *guest->vring[i].flag == 0) {\n\t\t\t\tRTE_LOG(INFO, XENHOST, \"\\n\\n\");\n\t\t\t\tRTE_LOG(INFO, XENHOST, \" #####%s: (%d, %d) to be removed\\n\",\n\t\t\t\t\t__func__,\n\t\t\t\t\tguest->vring[i].dom_id,\n\t\t\t\t\ti);\n\t\t\t\tdestroy_device(i, guest->dom_id);\n\t\t\t\tRTE_LOG(INFO, XENHOST, \" %s: DOM %u, vring num: %d\\n\",\n\t\t\t\t\t__func__,\n\t\t\t\t\tguest->dom_id,\n\t\t\t\t\tguest->vring_num);\n\t\t\t}\n\t\t}\n\t}\n\n_find_next_remove:\n\tguest = NULL;\n\tremove_request = false;\n\tTAILQ_FOREACH(guest, &guest_root, next) {\n\t\tif (guest->vring_num == 0) {\n\t\t\tremove_request = true;\n\t\t\tbreak;\n\t\t}\n\t}\n\tif (remove_request == true) {\n\t\tTAILQ_REMOVE(&guest_root, guest, next);\n\t\tRTE_LOG(INFO, XENHOST, \" #####%s: destroy guest (%d)\\n\", __func__, guest->dom_id);\n\t\tdestroy_guest(guest);\n\t\tgoto _find_next_remove;\n\t}\n\treturn;\n}\n\n/*\n * OK, if the guest starts first, it is ok.\n * if host starts first, it is ok.\n * if guest starts, and has run for sometime, and host stops and restarts,\n * then last_used_idx 0? how to solve this. */\n\nstatic void virtio_init(void)\n{\n\tuint32_t len, e_num;\n\tuint32_t i,j;\n\tchar **dom;\n\tchar *status;\n\tint dom_id;\n\tchar path[PATH_MAX];\n\tchar node[PATH_MAX];\n\txs_transaction_t th;\n\tstruct xen_guest *guest;\n\tstruct virtio_net_config_ll *net_config;\n\tchar *end;\n\tint val;\n\n\t/* init env for watch the node */\n\tif (init_watch() < 0)\n\t\treturn;\n\n\tdom = xs_directory(watch.xs, XBT_NULL, \"/local/domain\", &e_num);\n\n\tfor (i = 0; i < e_num; i++) {\n\t\terrno = 0;\n\t\tdom_id = strtol(dom[i], &end, 0);\n\t\tif (errno != 0 || end == NULL || dom_id == 0)\n\t\t\tcontinue;\n\n\t\tfor (j = 0; j < RTE_MAX_ETHPORTS; j++) {\n\t\t\tsnprintf(node, PATH_MAX, \"%s%d\", VIRTIO_START, j);\n\t\t\tsnprintf(path, PATH_MAX, XEN_VM_NODE_FMT,\n\t\t\t\t\tdom_id, node);\n\n\t\t\tth = xs_transaction_start(watch.xs);\n\t\t\tstatus = xs_read(watch.xs, th, path, &len);\n\t\t\txs_transaction_end(watch.xs, th, false);\n\n\t\t\tif (status == NULL)\n\t\t\t\tbreak;\n\n\t\t\t/* if there's any valid virtio device */\n\t\t\terrno = 0;\n\t\t\tval = strtol(status, &end, 0);\n\t\t\tif (errno != 0 || end == NULL || dom_id == 0)\n\t\t\t\tval = 0;\n\t\t\tif (val == 1) {\n\t\t\t\tguest = add_xen_guest(dom_id);\n\t\t\t\tif (guest == NULL)\n\t\t\t\t\tcontinue;\n\t\t\t\tRTE_LOG(INFO, XENHOST, \" there's a new virtio existed, new a virtio device\\n\\n\");\n\n\t\t\t\tRTE_LOG(INFO, XENHOST, \" parse_vringnode dom_id %d virtioidx %d\\n\",dom_id,j);\n\t\t\t\tif (parse_vringnode(guest, j)) {\n\t\t\t\t\tRTE_LOG(ERR, XENHOST, \" there is invalid information in xenstore\\n\");\n\t\t\t\t\tTAILQ_REMOVE(&guest_root, guest, next);\n\t\t\t\t\tdestroy_guest(guest);\n\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\t/*if pool_num > 0, then mempool has already been parsed*/\n\t\t\t\tif (guest->pool_num == 0 && parse_mempoolnode(guest)) {\n\t\t\t\t\tRTE_LOG(ERR, XENHOST, \" there is error information in xenstore\\n\");\n\t\t\t\t\tTAILQ_REMOVE(&guest_root, guest, next);\n\t\t\t\t\tdestroy_guest(guest);\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\n\t\t\t\tnet_config = new_device(j, guest);\n\t\t\t\t/* every thing is ready now, added into data core */\n\t\t\t\tnotify_ops->new_device(&net_config->dev);\n\t\t\t}\n\t\t}\n\t}\n\n\tfree(dom);\n\treturn;\n}\n\nvoid\nvirtio_monitor_loop(void)\n{\n\tchar **vec;\n\txs_transaction_t th;\n\tchar *buf;\n\tunsigned int len;\n\tunsigned int dom_id;\n\tuint32_t virtio_idx;\n\tstruct xen_guest *guest;\n\tstruct virtio_net_config_ll *net_config;\n\tenum fieldnames {\n\t\tFLD_NULL = 0,\n\t\tFLD_LOCAL,\n\t\tFLD_DOMAIN,\n\t\tFLD_ID,\n\t\tFLD_CONTROL,\n\t\tFLD_DPDK,\n\t\tFLD_NODE,\n\t\t_NUM_FLD\n\t};\n\tchar *str_fld[_NUM_FLD];\n\tchar *str;\n\tchar *end;\n\n\tvirtio_init();\n\twhile (1) {\n\t\twatch_unmap_event();\n\n\t\tusleep(50);\n\t\tvec = xs_check_watch(watch.xs);\n\n\t\tif (vec == NULL)\n\t\t\tcontinue;\n\n\t\tth = xs_transaction_start(watch.xs);\n\n\t\tbuf = xs_read(watch.xs, th, vec[XS_WATCH_PATH],&len);\n\t\txs_transaction_end(watch.xs, th, false);\n\n\t\tif (buf) {\n\t\t\t/* theres' some node for vhost existed */\n\t\t\tif (rte_strsplit(vec[XS_WATCH_PATH], strnlen(vec[XS_WATCH_PATH], PATH_MAX),\n\t\t\t\t\t\tstr_fld, _NUM_FLD, '/') == _NUM_FLD) {\n\t\t\t\tif (strstr(str_fld[FLD_NODE], VIRTIO_START)) {\n\t\t\t\t\terrno = 0;\n\t\t\t\t\tstr = str_fld[FLD_ID];\n\t\t\t\t\tdom_id = strtoul(str, &end, 0);\n\t\t\t\t\tif (errno != 0 || end == NULL || end == str ) {\n\t\t\t\t\t\tRTE_LOG(INFO, XENHOST, \"invalid domain id\\n\");\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\n\t\t\t\t\terrno = 0;\n\t\t\t\t\tstr = str_fld[FLD_NODE] + sizeof(VIRTIO_START) - 1;\n\t\t\t\t\tvirtio_idx = strtoul(str, &end, 0);\n\t\t\t\t\tif (errno != 0 || end == NULL || end == str\n\t\t\t\t\t\t\t|| virtio_idx > MAX_VIRTIO) {\n\t\t\t\t\t\tRTE_LOG(INFO, XENHOST, \"invalid virtio idx\\n\");\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\t\t\t\t\tRTE_LOG(INFO, XENHOST, \" #####virtio dev (%d, %d) is started\\n\", dom_id, virtio_idx);\n\n\t\t\t\t\tguest = add_xen_guest(dom_id);\n\t\t\t\t\tif (guest == NULL)\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\tguest->dom_id = dom_id;\n\t\t\t\t\tif (parse_vringnode(guest, virtio_idx)) {\n\t\t\t\t\t\tRTE_LOG(ERR, XENHOST, \" there is invalid information in xenstore\\n\");\n\t\t\t\t\t\t/*guest newly created? guest existed ?*/\n\t\t\t\t\t\tTAILQ_REMOVE(&guest_root, guest, next);\n\t\t\t\t\t\tdestroy_guest(guest);\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\t\t\t\t\t/*if pool_num > 0, then mempool has already been parsed*/\n\t\t\t\t\tif (guest->pool_num == 0 && parse_mempoolnode(guest)) {\n\t\t\t\t\t\tRTE_LOG(ERR, XENHOST, \" there is error information in xenstore\\n\");\n\t\t\t\t\t\tTAILQ_REMOVE(&guest_root, guest, next);\n\t\t\t\t\t\tdestroy_guest(guest);\n\t\t\t\t\t\tcontinue;\n\t\t\t\t\t}\n\n\n\t\t\t\t\tnet_config = new_device(virtio_idx, guest);\n\t\t\t\t\tRTE_LOG(INFO, XENHOST, \" Add to dataplane core\\n\");\n\t\t\t\t\tnotify_ops->new_device(&net_config->dev);\n\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tfree(vec);\n\t}\n\treturn;\n}\n\n/*\n * Register ops so that we can add/remove device to data core.\n */\nint\ninit_virtio_xen(struct virtio_net_device_ops const *const ops)\n{\n\tnotify_ops = ops;\n\tif (xenhost_init())\n\t\treturn -1;\n\treturn 0;\n}\n" }, { "path": "examples/vhost_xen/virtio-net.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VIRTIO_NET_H_\n#define _VIRTIO_NET_H_\n\n#include \n\n#define VQ_DESC_NUM 256\n/* Used to indicate that the device is running on a data core */\n#define VIRTIO_DEV_RUNNING 1\n\n/*\n * Structure contains variables relevant to TX/RX virtqueues.\n */\nstruct vhost_virtqueue\n{\n\tstruct vring_desc *desc; /* Virtqueue descriptor ring. */\n\tstruct vring_avail *avail; /* Virtqueue available ring. */\n\tstruct vring_used *used; /* Virtqueue used ring. */\n\tuint32_t size; /* Size of descriptor ring. */\n\tuint32_t vhost_hlen; /* Vhost header length (varies depending on RX merge buffers. */\n\tvolatile uint16_t last_used_idx; /* Last index used on the available ring */\n\tvolatile uint16_t last_used_idx_res; /* Used for multiple devices reserving buffers. */\n} __rte_cache_aligned;\n\n/*\n * Device structure contains all configuration information relating to the device.\n */\nstruct virtio_net\n{\n\tstruct vhost_virtqueue\t*virtqueue_tx;\t/* Contains all TX virtqueue information. */\n\tstruct vhost_virtqueue\t*virtqueue_rx;\t/* Contains all RX virtqueue information. */\n\tstruct virtio_memory *mem; /* QEMU memory and memory region information. */\n\tstruct ether_addr mac_address; /* Device MAC address (Obtained on first TX packet). */\n\tuint32_t flags; /* Device flags. Only used to check if device is running on data core. */\n\tuint32_t vlan_tag; /* Vlan tag for device. Currently set to device_id (0-63). */\n\tuint32_t vmdq_rx_q;\n\tuint64_t device_fh; /* device identifier. */\n\tuint16_t coreid;\n\tvolatile uint8_t ready; /* A device is set as ready if the MAC address has been set. */\n\tvolatile uint8_t remove; /* Device is marked for removal from the data core. */\n\tuint32_t virtio_idx; /* Index of virtio device */\n\tuint32_t dom_id; /* Domain id of xen guest */\n} ___rte_cache_aligned;\n\n/*\n * Device linked list structure for configuration.\n */\nstruct virtio_net_config_ll\n{\n\tstruct virtio_net\t\tdev;\t/* Virtio device. */\n\tstruct virtio_net_config_ll\t*next; /* Next entry on linked list. */\n};\n\n/*\n * Information relating to memory regions including offsets to addresses in QEMUs memory file.\n */\nstruct virtio_memory_regions {\n\tuint64_t\tguest_phys_address; /* Base guest physical address of region. */\n\tuint64_t\tguest_phys_address_end;\t/* End guest physical address of region. */\n\tuint64_t\tmemory_size;\t\t/* Size of region. */\n\tuint64_t\tuserspace_address; /* Base userspace address of region. */\n\tuint64_t\taddress_offset; /* Offset of region for address translation. */\n};\n\n/*\n * Memory structure includes region and mapping information.\n */\nstruct virtio_memory {\n\tuint32_t\t\t\tnregions;\t/* Number of memory regions. */\n\tstruct virtio_memory_regions \tregions[0];\t/* Memory region information. */\n};\n\n/*\n * Device operations to add/remove device.\n */\nstruct virtio_net_device_ops {\n\tint (* new_device)(struct virtio_net *);\t/* Add device. */\n\tvoid (* destroy_device)\t(volatile struct virtio_net *);\t/* Remove device. */\n};\n\nstruct vhost_net_device_ops const * get_virtio_net_callbacks(void);\n\n#endif\n" }, { "path": "examples/vhost_xen/xen_vhost.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _XEN_VHOST_H_\n#define _XEN_VHOST_H_\n\n#include \n\n#include \n\n#include \"virtio-net.h\"\n\n#define RTE_LOGTYPE_XENHOST RTE_LOGTYPE_USER1\n\n#define XEN_VM_ROOTNODE_FMT \"/local/domain/%d/control/dpdk\"\n#define XEN_VM_NODE_FMT \"/local/domain/%d/control/dpdk/%s\"\n#define XEN_MEMPOOL_SUFFIX \"mempool_gref\"\n#define XEN_RXVRING_SUFFIX \"rx_vring_gref\"\n#define XEN_TXVRING_SUFFIX \"tx_vring_gref\"\n#define XEN_GVA_SUFFIX \"mempool_va\"\n#define XEN_VRINGFLAG_SUFFIX \"vring_flag\"\n#define XEN_ADDR_SUFFIX \"ether_addr\"\n#define VIRTIO_START \"event_type_start_\"\n\n#define XEN_GREF_SPLITTOKEN ','\n\n#define MAX_XENVIRT_MEMPOOL 16\n#define MAX_VIRTIO 32\n#define MAX_GREF_PER_NODE 64 /* 128 MB memory */\n\n#define PAGE_SIZE 4096\n#define PAGE_PFNNUM (PAGE_SIZE / sizeof(uint32_t))\n\n#define XEN_GNTDEV_FNAME \"/dev/xen/gntdev\"\n\n/* xen grant reference info in one grant node */\nstruct xen_gnt {\n\tuint32_t gref;\t/* grant reference for this node */\n\tunion {\n\t\tint gref;\t\t/* grant reference */\n\t\tuint32_t pfn_num;\t/* guest pfn number of grant reference */\n\t} gref_pfn[PAGE_PFNNUM];\n}__attribute__((__packed__));\n\n\n/* structure for mempool or vring node list */\nstruct xen_gntnode {\n\tuint32_t gnt_num; /* grant reference number */\n\tstruct xen_gnt *gnt_info; /* grant reference info */\n};\n\n\nstruct xen_vring {\n\tuint32_t dom_id;\n\tuint32_t virtio_idx; /* index of virtio device */\n\tvoid *rxvring_addr; /* mapped virtual address of rxvring */\n\tvoid *txvring_addr; /* mapped virtual address of txvring */\n\tuint32_t rxpfn_num; /* number of gpfn for rxvring */\n\tuint32_t txpfn_num;\t/* number of gpfn for txvring */\n\tuint32_t *rxpfn_tbl; /* array of rxvring gpfn */\n\tuint32_t *txpfn_tbl;\t/* array of txvring gpfn */\n\tuint64_t *rx_pindex; /* index used to release rx grefs */\n\tuint64_t *tx_pindex; /* index used to release tx grefs */\n\tuint64_t flag_index;\n\tuint8_t *flag; \t/* cleared to zero on guest unmap */\n\tstruct ether_addr addr; /* ethernet address of virtio device */\n\tuint8_t removed;\n\n};\n\nstruct xen_mempool {\n\tuint32_t dom_id; /* guest domain id */\n\tuint32_t pool_idx; /* index of memory pool */\n\tvoid *gva; /* guest virtual address of mbuf pool */\n\tvoid *hva; /* host virtual address of mbuf pool */\n\tuint32_t mempfn_num; /* number of gpfn for mbuf pool */\n\tuint32_t *mempfn_tbl; /* array of mbuf pool gpfn */\n\tuint64_t *pindex; /* index used to release grefs */\n};\n\nstruct xen_guest {\n\tTAILQ_ENTRY(xen_guest) next;\n\tint32_t dom_id; /* guest domain id */\n\tuint32_t pool_num; /* number of mbuf pool of the guest */\n\tuint32_t vring_num; /* number of virtio ports of the guest */\n\t/* array contain the guest mbuf pool info */\n\tstruct xen_mempool mempool[MAX_XENVIRT_MEMPOOL];\n\t/* array contain the guest rx/tx vring info */\n\tstruct xen_vring vring[MAX_VIRTIO];\n};\n\nTAILQ_HEAD(xen_guestlist, xen_guest);\n\nint\nparse_mempoolnode(struct xen_guest *guest);\n\nint\nxenhost_init(void);\n\nint\nparse_vringnode(struct xen_guest *guest, uint32_t virtio_idx);\n\nint\nparse_mempoolnode(struct xen_guest *guest);\n\nvoid\ncleanup_mempool(struct xen_mempool *mempool);\n\nvoid\ncleanup_vring(struct xen_vring *vring);\n\nvoid\nvirtio_monitor_loop(void);\n\nint\ninit_virtio_xen(struct virtio_net_device_ops const * const);\n\n#endif\n" }, { "path": "examples/vhost_xen/xenstore_parse.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#if __XEN_LATEST_INTERFACE_VERSION__ < 0x00040200\n#include \n#else\n#include \n#endif\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"xen_vhost.h\"\n\n/* xenstore handle */\nstatic struct xs_handle *xs = NULL;\n\n/* gntdev file descriptor to map grant pages */\nstatic int d_fd = -1;\n\n/*\n * The grant node format in xenstore for vring/mpool is like:\n * idx#_rx_vring_gref = \"gref1#, gref2#, gref3#\"\n * idx#_mempool_gref = \"gref1#, gref2#, gref3#\"\n * each gref# is the grant reference for a shared page.\n * In each shared page, we store the grant_node_item items.\n */\nstruct grant_node_item {\n\tuint32_t gref;\n\tuint32_t pfn;\n} __attribute__((packed));\n\nint cmdline_parse_etheraddr(void *tk, const char *srcbuf,\n\tvoid *res, unsigned ressize);\n\n/* Map grant ref refid at addr_ori*/\nstatic void *\nxen_grant_mmap(void *addr_ori, int domid, int refid, uint64_t *pindex)\n{\n\tstruct ioctl_gntdev_map_grant_ref arg;\n\tvoid *addr = NULL;\n\tint pg_sz = getpagesize();\n\n\targ.count = 1;\n\targ.refs[0].domid = domid;\n\targ.refs[0].ref = refid;\n\n\tint rv = ioctl(d_fd, IOCTL_GNTDEV_MAP_GRANT_REF, &arg);\n\tif (rv) {\n\t\tRTE_LOG(ERR, XENHOST, \" %s: (%d,%d) %s (ioctl failed)\\n\", __func__,\n\t\t\t\tdomid, refid, strerror(errno));\n\t\treturn NULL;\n\t}\n\n\tif (addr_ori == NULL)\n\t\taddr = mmap(addr_ori, pg_sz, PROT_READ|PROT_WRITE, MAP_SHARED,\n\t\t\t\td_fd, arg.index);\n\telse\n\t\taddr = mmap(addr_ori, pg_sz, PROT_READ|PROT_WRITE, MAP_SHARED | MAP_FIXED,\n\t\t\t\td_fd, arg.index);\n\n\tif (addr == MAP_FAILED) {\n\t\tRTE_LOG(ERR, XENHOST, \" %s: (%d, %d) %s (map failed)\\n\", __func__,\n\t\t\t\tdomid, refid, strerror(errno));\n\t\treturn NULL;\n\t}\n\n\tif (pindex)\n\t\t*pindex = arg.index;\n\n\treturn addr;\n}\n\n/* Unmap one grant ref, and munmap must be called before this */\nstatic int\nxen_unmap_grant_ref(uint64_t index)\n{\n\tstruct ioctl_gntdev_unmap_grant_ref arg;\n\tint rv;\n\n\targ.count = 1;\n\targ.index = index;\n\trv = ioctl(d_fd, IOCTL_GNTDEV_UNMAP_GRANT_REF, &arg);\n\tif (rv) {\n\t\tRTE_LOG(ERR, XENHOST, \" %s: index 0x%\" PRIx64 \"unmap failed\\n\", __func__, index);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/*\n * Reserve a virtual address space.\n * On success, returns the pointer. On failure, returns NULL.\n */\nstatic void *\nget_xen_virtual(size_t size, size_t page_sz)\n{\n\tvoid *addr;\n\tuintptr_t aligned_addr;\n\n\taddr = mmap(NULL, size + page_sz, PROT_READ, MAP_SHARED | MAP_ANONYMOUS, -1, 0);\n\tif (addr == MAP_FAILED) {\n\t\tRTE_LOG(ERR, XENHOST, \"failed get a virtual area\\n\");\n\t\treturn NULL;\n\t}\n\n\taligned_addr = RTE_ALIGN_CEIL((uintptr_t)addr, page_sz);\n\tmunmap(addr, aligned_addr - (uintptr_t)addr);\n\tmunmap((void *)(aligned_addr + size), page_sz + (uintptr_t)addr - aligned_addr);\n\taddr = (void *)(aligned_addr);\n\n\treturn addr;\n}\n\nstatic void\nfree_xen_virtual(void *addr, size_t size, size_t page_sz __rte_unused)\n{\n\tif (addr)\n\t\tmunmap(addr, size);\n}\n\n/*\n * Returns val str in xenstore.\n * @param path\n * Full path string for key\n * @return\n * Pointer to Val str, NULL on failure\n */\nstatic char *\nxen_read_node(char *path, uint32_t *len)\n{\n\tchar *buf;\n\n\tbuf = xs_read(xs, XBT_NULL, path, len);\n\treturn buf;\n}\n\nstatic int\ncal_pagenum(struct xen_gnt *gnt)\n{\n\tunsigned int i;\n\t/*\n\t * the items in the page are in the format of\n\t * gref#,pfn#,...,gref#,pfn#\n\t * FIXME, 0 is reserved by system, use it as terminator.\n\t */\n\tfor (i = 0; i < (PAGE_PFNNUM) / 2; i++) {\n\t\tif (gnt->gref_pfn[i * 2].gref <= 0)\n\t\t\tbreak;\n\t}\n\n\treturn i;\n}\n\n/* Frees memory allocated to a grant node */\nstatic void\nxen_free_gntnode(struct xen_gntnode *gntnode)\n{\n\tif (gntnode == NULL)\n\t\treturn;\n\tif (gntnode->gnt_info)\n\t\tfree(gntnode->gnt_info);\n\tfree(gntnode);\n}\n\n/*\n * Parse a grant node.\n * @param domid\n * Guest domain id.\n * @param path\n * Full path string for a grant node, like for the following (key, val) pair\n * idx#_mempool_gref = \"gref#, gref#, gref#\"\n * path = 'local/domain/domid/control/dpdk/idx#_mempool_gref'\n * gref# is a shared page contain packed (gref,pfn) entries\n * @return\n * Returns the pointer to xen_gntnode\n */\nstatic struct xen_gntnode *\nparse_gntnode(int dom_id, char *path)\n{\n\tchar **gref_list = NULL;\n\tuint32_t i, len, gref_num;\n\tvoid *addr = NULL;\n\tchar *buf = NULL;\n\tstruct xen_gntnode *gntnode = NULL;\n\tstruct xen_gnt *gnt = NULL;\n\tint pg_sz = getpagesize();\n\tchar *end;\n\tuint64_t index;\n\n\tif ((buf = xen_read_node(path, &len)) == NULL)\n\t\tgoto err;\n\n\tgref_list = malloc(MAX_GREF_PER_NODE * sizeof(char *));\n\tif (gref_list == NULL)\n\t\tgoto err;\n\n\tgref_num = rte_strsplit(buf, len, gref_list, MAX_GREF_PER_NODE,\n\t\t\tXEN_GREF_SPLITTOKEN);\n\tif (gref_num == 0) {\n\t\tRTE_LOG(ERR, XENHOST, \" %s: invalid grant node format\\n\", __func__);\n\t\tgoto err;\n\t}\n\n\tgntnode = calloc(1, sizeof(struct xen_gntnode));\n\tgnt = calloc(gref_num, sizeof(struct xen_gnt));\n\tif (gnt == NULL || gntnode == NULL)\n\t\tgoto err;\n\n\tfor (i = 0; i < gref_num; i++) {\n\t\terrno = 0;\n\t\tgnt[i].gref = strtol(gref_list[i], &end, 0);\n\t\tif (errno != 0 || end == NULL || end == gref_list[i] ||\n\t\t\t(*end != '\\0' && *end != XEN_GREF_SPLITTOKEN)) {\n\t\t\tRTE_LOG(ERR, XENHOST, \" %s: parse grant node item failed\\n\", __func__);\n\t\t\tgoto err;\n\t\t}\n\t\taddr = xen_grant_mmap(NULL, dom_id, gnt[i].gref, &index);\n\t\tif (addr == NULL) {\n\t\t\tRTE_LOG(ERR, XENHOST, \" %s: map gref %u failed\\n\", __func__, gnt[i].gref);\n\t\t\tgoto err;\n\t\t}\n\t\tRTE_LOG(INFO, XENHOST, \" %s: map gref %u to %p\\n\", __func__, gnt[i].gref, addr);\n\t\tmemcpy(gnt[i].gref_pfn, addr, pg_sz);\n\t\tif (munmap(addr, pg_sz)) {\n\t\t\tRTE_LOG(INFO, XENHOST, \" %s: unmap gref %u failed\\n\", __func__, gnt[i].gref);\n\t\t\tgoto err;\n\t\t}\n\t\tif (xen_unmap_grant_ref(index)) {\n\t\t\tRTE_LOG(INFO, XENHOST, \" %s: release gref %u failed\\n\", __func__, gnt[i].gref);\n\t\t\tgoto err;\n\t\t}\n\n\t}\n\n\tgntnode->gnt_num = gref_num;\n\tgntnode->gnt_info = gnt;\n\n\tfree(buf);\n\tfree(gref_list);\n\treturn gntnode;\n\nerr:\n\tif (gnt)\n\t\tfree(gnt);\n\tif (gntnode)\n\t\tfree(gntnode);\n\tif (gref_list)\n\t\tfree(gref_list);\n\tif (buf)\n\t\tfree(buf);\n\treturn NULL;\n}\n\n/*\n * This function maps grant node of vring or mbuf pool to a continous virtual address space,\n * and returns mapped address, pfn array, index array\n * @param gntnode\n * Pointer to grant node\n * @param domid\n * Guest domain id\n * @param ppfn\n * Pointer to pfn array, caller should free this array\n * @param pgs\n * Pointer to number of pages\n * @param ppindex\n * Pointer to index array, used to release grefs when to free this node\n * @return\n * Pointer to mapped virtual address, NULL on failure\n */\nstatic void *\nmap_gntnode(struct xen_gntnode *gntnode, int domid, uint32_t **ppfn, uint32_t *pgs, uint64_t **ppindex)\n{\n\tstruct xen_gnt *gnt;\n\tuint32_t i, j;\n\tsize_t total_pages = 0;\n\tvoid *addr;\n\tuint32_t *pfn;\n\tuint64_t *pindex;\n\tuint32_t pfn_num = 0;\n\tint pg_sz;\n\n\tif (gntnode == NULL)\n\t\treturn NULL;\n\n\tpg_sz = getpagesize();\n\tfor (i = 0; i < gntnode->gnt_num; i++) {\n\t\tgnt = gntnode->gnt_info + i;\n\t\ttotal_pages += cal_pagenum(gnt);\n\t}\n\tif ((addr = get_xen_virtual(total_pages * pg_sz, pg_sz)) == NULL) {\n\t\tRTE_LOG(ERR, XENHOST, \" %s: failed get_xen_virtual\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tpfn = calloc(total_pages, (size_t)sizeof(uint32_t));\n\tpindex = calloc(total_pages, (size_t)sizeof(uint64_t));\n\tif (pfn == NULL || pindex == NULL) {\n\t\tfree_xen_virtual(addr, total_pages * pg_sz, pg_sz);\n\t\tfree(pfn);\n\t\tfree(pindex);\n\t\treturn NULL;\n\t}\n\n\tRTE_LOG(INFO, XENHOST, \" %s: total pages:%zu, map to [%p, %p]\\n\", __func__, total_pages, addr, RTE_PTR_ADD(addr, total_pages * pg_sz - 1));\n\tfor (i = 0; i < gntnode->gnt_num; i++) {\n\t\tgnt = gntnode->gnt_info + i;\n\t\tfor (j = 0; j < (PAGE_PFNNUM) / 2; j++) {\n\t\t\tif ((gnt->gref_pfn[j * 2].gref) <= 0)\n\t\t\t\tgoto _end;\n\t\t\t/*alternative: batch map, or through libxc*/\n\t\t\tif (xen_grant_mmap(RTE_PTR_ADD(addr, pfn_num * pg_sz),\n\t\t\t\t\tdomid,\n\t\t\t\t\tgnt->gref_pfn[j * 2].gref,\n\t\t\t\t\t&pindex[pfn_num]) == NULL) {\n\t\t\t\tgoto mmap_failed;\n\t\t\t}\n\t\t\tpfn[pfn_num] = gnt->gref_pfn[j * 2 + 1].pfn_num;\n\t\t\tpfn_num++;\n\t\t}\n\t}\n\nmmap_failed:\n\tif (pfn_num)\n\t\tmunmap(addr, pfn_num * pg_sz);\n\tfor (i = 0; i < pfn_num; i++) {\n\t\txen_unmap_grant_ref(pindex[i]);\n\t}\n\tfree(pindex);\n\tfree(pfn);\n\treturn NULL;\n\n_end:\n\tif (ppindex)\n\t\t*ppindex = pindex;\n\telse\n\t\tfree(pindex);\n\tif (ppfn)\n\t\t*ppfn = pfn;\n\telse\n\t\tfree(pfn);\n\tif (pgs)\n\t\t*pgs = total_pages;\n\n\treturn addr;\n}\n\nstatic int\nparse_mpool_va(struct xen_mempool *mempool)\n{\n\tchar path[PATH_MAX] = {0};\n\tchar *buf;\n\tuint32_t len;\n\tchar *end;\n\tint ret = -1;\n\n\terrno = 0;\n\tsnprintf(path, sizeof(path),\n\t\tXEN_VM_ROOTNODE_FMT\"/%d_\"XEN_GVA_SUFFIX,\n\t\tmempool->dom_id, mempool->pool_idx);\n\n\tif((buf = xen_read_node(path, &len)) == NULL)\n\t\tgoto out;\n\tmempool->gva = (void *)strtoul(buf, &end, 16);\n\tif (errno != 0 || end == NULL || end == buf || *end != '\\0') {\n\t\tmempool->gva = NULL;\n\t\tgoto out;\n\t}\n\tret = 0;\nout:\n\tif (buf)\n\t\tfree(buf);\n\treturn ret;\n}\n\n/*\n * map mbuf pool\n */\nstatic int\nmap_mempoolnode(struct xen_gntnode *gntnode,\n\t\t\tstruct xen_mempool *mempool)\n{\n\tif (gntnode == NULL || mempool == NULL)\n\t\treturn -1;\n\n\tmempool->hva =\n\t\tmap_gntnode(gntnode, mempool->dom_id, &mempool->mempfn_tbl, &mempool->mempfn_num, &mempool->pindex);\n\n\tRTE_LOG(INFO, XENHOST, \" %s: map mempool at %p\\n\", __func__, (void *)mempool->hva);\n\tif (mempool->hva)\n\t\treturn 0;\n\telse {\n\t\treturn -1;\n\t}\n}\n\nvoid\ncleanup_mempool(struct xen_mempool *mempool)\n{\n\tint pg_sz = getpagesize();\n\tuint32_t i;\n\n\tif (mempool->hva)\n\t\tmunmap(mempool->hva, mempool->mempfn_num * pg_sz);\n\tmempool->hva = NULL;\n\n\tif (mempool->pindex) {\n\t\tRTE_LOG(INFO, XENHOST, \" %s: unmap dom %02u mempool%02u %u grefs\\n\",\n\t\t\t__func__,\n\t\t\tmempool->dom_id,\n\t\t\tmempool->pool_idx,\n\t\t\tmempool->mempfn_num);\n\t\tfor (i = 0; i < mempool->mempfn_num; i ++) {\n\t\t\txen_unmap_grant_ref(mempool->pindex[i]);\n\t\t}\n\t}\n\tmempool->pindex = NULL;\n\n\tif (mempool->mempfn_tbl)\n\t\tfree(mempool->mempfn_tbl);\n\tmempool->mempfn_tbl = NULL;\n}\n\n/*\n * process mempool node idx#_mempool_gref, idx = 0, 1, 2...\n * untill we encounter a node that doesn't exist.\n */\nint\nparse_mempoolnode(struct xen_guest *guest)\n{\n\tuint32_t i, len;\n\tchar path[PATH_MAX] = {0};\n\tstruct xen_gntnode *gntnode = NULL;\n\tstruct xen_mempool *mempool = NULL;\n\tchar *buf;\n\n\tbzero(&guest->mempool, MAX_XENVIRT_MEMPOOL * sizeof(guest->mempool[0]));\n\tguest->pool_num = 0;\n\n\twhile (1) {\n\t\t/* check if null terminated */\n\t\tsnprintf(path, sizeof(path),\n\t\t\tXEN_VM_ROOTNODE_FMT\"/%d_\"XEN_MEMPOOL_SUFFIX,\n\t\t\tguest->dom_id,\n\t\t\tguest->pool_num);\n\n\t\tif ((buf = xen_read_node(path, &len)) != NULL) {\n\t\t\t/* this node exists */\n\t\t\tfree(buf);\n\t\t} else {\n\t\t\tif (guest->pool_num == 0) {\n\t\t\t\tRTE_LOG(ERR, PMD, \"no mempool found\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\n\t\tmempool = &guest->mempool[guest->pool_num];\n\t\tmempool->dom_id = guest->dom_id;\n\t\tmempool->pool_idx = guest->pool_num;\n\n\t\tRTE_LOG(INFO, XENHOST, \" %s: mempool %u parse gntnode %s\\n\", __func__, guest->pool_num, path);\n\t\tgntnode = parse_gntnode(guest->dom_id, path);\n\t\tif (gntnode == NULL)\n\t\t\tgoto err;\n\n\t\tif (parse_mpool_va(mempool))\n\t\t\tgoto err;\n\n\t\tRTE_LOG(INFO, XENHOST, \" %s: mempool %u map gntnode %s\\n\", __func__, guest->pool_num, path);\n\t\tif (map_mempoolnode(gntnode, mempool))\n\t\t\tgoto err;\n\n\t\txen_free_gntnode(gntnode);\n\t\tguest->pool_num++;\n\t}\n\n\treturn 0;\nerr:\n\tif (gntnode)\n\t\txen_free_gntnode(gntnode);\n\tfor (i = 0; i < MAX_XENVIRT_MEMPOOL ; i++) {\n\t\tcleanup_mempool(&guest->mempool[i]);\n\t}\n\t/* reinitialise mempool */\n\tbzero(&guest->mempool, MAX_XENVIRT_MEMPOOL * sizeof(guest->mempool[0]));\n\treturn -1;\n}\n\nstatic int\nxen_map_vringflag(struct xen_vring *vring)\n{\n\tchar path[PATH_MAX] = {0};\n\tchar *buf;\n\tuint32_t len,gref;\n\tint pg_sz = getpagesize();\n\tchar *end;\n\n\tsnprintf(path, sizeof(path),\n\t\tXEN_VM_ROOTNODE_FMT\"/%d_\"XEN_VRINGFLAG_SUFFIX,\n\t\tvring->dom_id, vring->virtio_idx);\n\n\tif((buf = xen_read_node(path, &len)) == NULL)\n\t\tgoto err;\n\n\terrno = 0;\n\tgref = strtol(buf, &end, 0);\n\tif (errno != 0 || end == NULL || end == buf) {\n\t\tgoto err;\n\t}\n\tvring->flag = xen_grant_mmap(0, vring->dom_id, gref, &vring->flag_index);\n\tif (vring->flag == NULL || *vring->flag == 0)\n\t\tgoto err;\n\n\tfree(buf);\n\treturn 0;\nerr:\n\tif (buf)\n\t\tfree(buf);\n\tif (vring->flag) {\n\t\tmunmap(vring->flag, pg_sz);\n\t\tvring->flag = NULL;\n\t\txen_unmap_grant_ref(vring->flag_index);\n\t}\n\treturn -1;\n}\n\n\nstatic int\nxen_map_rxvringnode(struct xen_gntnode *gntnode,\n\t\t\t\tstruct xen_vring *vring)\n{\n\tvring->rxvring_addr =\n\t\tmap_gntnode(gntnode, vring->dom_id, &vring->rxpfn_tbl, &vring->rxpfn_num, &vring->rx_pindex);\n\tRTE_LOG(INFO, XENHOST, \" %s: map rx vring at %p\\n\", __func__, (void *)vring->rxvring_addr);\n\tif (vring->rxvring_addr)\n\t\treturn 0;\n\telse\n\t\treturn -1;\n}\n\nstatic int\nxen_map_txvringnode(struct xen_gntnode *gntnode,\n\t\t\t\tstruct xen_vring *vring)\n{\n\tvring->txvring_addr =\n\t\tmap_gntnode(gntnode, vring->dom_id, &vring->txpfn_tbl, &vring->txpfn_num, &vring->tx_pindex);\n\tRTE_LOG(INFO, XENHOST, \" %s: map tx vring at %p\\n\", __func__, (void *)vring->txvring_addr);\n\tif (vring->txvring_addr)\n\t\treturn 0;\n\telse\n\t\treturn -1;\n}\n\nvoid\ncleanup_vring(struct xen_vring *vring)\n{\n\tint pg_sz = getpagesize();\n\tuint32_t i;\n\n\tRTE_LOG(INFO, XENHOST, \" %s: cleanup dom %u vring %u\\n\", __func__, vring->dom_id, vring->virtio_idx);\n\tif (vring->rxvring_addr) {\n\t\tmunmap(vring->rxvring_addr, vring->rxpfn_num * pg_sz);\n\t\tRTE_LOG(INFO, XENHOST, \" %s: unmap rx vring [%p, %p]\\n\",\n\t\t\t__func__,\n\t\t\tvring->rxvring_addr,\n\t\t\tRTE_PTR_ADD(vring->rxvring_addr,\n\t\t\tvring->rxpfn_num * pg_sz - 1));\n\t}\n\tvring->rxvring_addr = NULL;\n\n\n\tif (vring->rx_pindex) {\n\t\tRTE_LOG(INFO, XENHOST, \" %s: unmap rx vring %u grefs\\n\", __func__, vring->rxpfn_num);\n\t\tfor (i = 0; i < vring->rxpfn_num; i++) {\n\t\t\txen_unmap_grant_ref(vring->rx_pindex[i]);\n\t\t}\n\t}\n\tvring->rx_pindex = NULL;\n\n\tif (vring->rxpfn_tbl)\n\t\tfree(vring->rxpfn_tbl);\n\tvring->rxpfn_tbl = NULL;\n\n\tif (vring->txvring_addr) {\n\t\tmunmap(vring->txvring_addr, vring->txpfn_num * pg_sz);\n\t\tRTE_LOG(INFO, XENHOST, \" %s: unmap tx vring [%p, %p]\\n\",\n\t\t\t__func__,\n\t\t\tvring->txvring_addr,\n\t\t\tRTE_PTR_ADD(vring->txvring_addr,\n\t\t\tvring->txpfn_num * pg_sz - 1));\n\t}\n\tvring->txvring_addr = NULL;\n\n\tif (vring->tx_pindex) {\n\t\tRTE_LOG(INFO, XENHOST, \" %s: unmap tx vring %u grefs\\n\", __func__, vring->txpfn_num);\n\t\tfor (i = 0; i < vring->txpfn_num; i++) {\n\t\t\txen_unmap_grant_ref(vring->tx_pindex[i]);\n\t\t}\n\t}\n\tvring->tx_pindex = NULL;\n\n\tif (vring->txpfn_tbl)\n\t\tfree(vring->txpfn_tbl);\n\tvring->txpfn_tbl = NULL;\n\n\tif (vring->flag) {\n\t\tif (!munmap((void *)vring->flag, pg_sz))\n\t\t\tRTE_LOG(INFO, XENHOST, \" %s: unmap flag page at %p\\n\", __func__, vring->flag);\n\t\tif (!xen_unmap_grant_ref(vring->flag_index))\n\t\t\tRTE_LOG(INFO, XENHOST, \" %s: release flag ref index 0x%\" PRIx64 \"\\n\", __func__, vring->flag_index);\n\t}\n\tvring->flag = NULL;\n\treturn;\n}\n\n\n\nstatic int\nxen_parse_etheraddr(struct xen_vring *vring)\n{\n\tchar path[PATH_MAX] = {0};\n\tchar *buf;\n\tuint32_t len;\n\tint ret = -1;\n\n\tsnprintf(path, sizeof(path),\n\t\tXEN_VM_ROOTNODE_FMT\"/%d_\"XEN_ADDR_SUFFIX,\n\t\tvring->dom_id, vring->virtio_idx);\n\n\tif ((buf = xen_read_node(path, &len)) == NULL)\n\t\tgoto out;\n\n\tif (cmdline_parse_etheraddr(NULL, buf, &vring->addr,\n\t\t\tsizeof(vring->addr)) < 0)\n\t\tgoto out;\n\tret = 0;\nout:\n\tif (buf)\n\t\tfree(buf);\n\treturn ret;\n}\n\n\nint\nparse_vringnode(struct xen_guest *guest, uint32_t virtio_idx)\n{\n\tchar path[PATH_MAX] = {0};\n\tstruct xen_gntnode *rx_gntnode = NULL;\n\tstruct xen_gntnode *tx_gntnode = NULL;\n\tstruct xen_vring *vring = NULL;\n\n\t/*check if null terminated */\n\tsnprintf(path, sizeof(path),\n\t\tXEN_VM_ROOTNODE_FMT\"/%d_\"XEN_RXVRING_SUFFIX,\n\t\tguest->dom_id,\n\t\tvirtio_idx);\n\n\tRTE_LOG(INFO, XENHOST, \" %s: virtio %u parse rx gntnode %s\\n\", __func__, virtio_idx, path);\n\trx_gntnode = parse_gntnode(guest->dom_id, path);\n\tif (rx_gntnode == NULL)\n\t\tgoto err;\n\n\t/*check if null terminated */\n\tsnprintf(path, sizeof(path),\n\t\tXEN_VM_ROOTNODE_FMT\"/%d_\"XEN_TXVRING_SUFFIX,\n\t\tguest->dom_id,\n\t\tvirtio_idx);\n\n\tRTE_LOG(INFO, XENHOST, \" %s: virtio %u parse tx gntnode %s\\n\", __func__, virtio_idx, path);\n\ttx_gntnode = parse_gntnode(guest->dom_id, path);\n\tif (tx_gntnode == NULL)\n\t\tgoto err;\n\n\tvring = &guest->vring[virtio_idx];\n\tbzero(vring, sizeof(*vring));\n\tvring->dom_id = guest->dom_id;\n\tvring->virtio_idx = virtio_idx;\n\n\tif (xen_parse_etheraddr(vring) != 0)\n\t\tgoto err;\n\n\tRTE_LOG(INFO, XENHOST, \" %s: virtio %u map rx gntnode %s\\n\", __func__, virtio_idx, path);\n\tif (xen_map_rxvringnode(rx_gntnode, vring) != 0)\n\t\tgoto err;\n\n\tRTE_LOG(INFO, XENHOST, \" %s: virtio %u map tx gntnode %s\\n\", __func__, virtio_idx, path);\n\tif (xen_map_txvringnode(tx_gntnode, vring) != 0)\n\t\tgoto err;\n\n\tif (xen_map_vringflag(vring) != 0)\n\t\tgoto err;\n\n\tguest->vring_num++;\n\n\txen_free_gntnode(rx_gntnode);\n\txen_free_gntnode(tx_gntnode);\n\n\treturn 0;\n\nerr:\n\tif (rx_gntnode)\n\t\txen_free_gntnode(rx_gntnode);\n\tif (tx_gntnode)\n\t\txen_free_gntnode(tx_gntnode);\n\tif (vring) {\n\t\tcleanup_vring(vring);\n\t\tbzero(vring, sizeof(*vring));\n\t}\n\treturn -1;\n}\n\n/*\n * Open xen grant dev driver\n * @return\n * 0 on success, -1 on failure.\n */\nstatic int\nxen_grant_init(void)\n{\n\td_fd = open(XEN_GNTDEV_FNAME, O_RDWR);\n\n\treturn d_fd == -1? (-1): (0);\n}\n\n/*\n * Initialise xenstore handle and open grant dev driver.\n * @return\n * 0 on success, -1 on failure.\n */\nint\nxenhost_init(void)\n{\n\txs = xs_daemon_open();\n\tif (xs == NULL) {\n\t\trte_panic(\"failed initialize xen daemon handler\");\n\t\treturn -1;\n\t}\n\tif (xen_grant_init())\n\t\treturn -1;\n\treturn 0;\n}\n" }, { "path": "examples/vm_power_manager/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overridden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = vm_power_mgr\n\n# all source are stored in SRCS-y\nSRCS-y := main.c vm_power_cli.c power_manager.c channel_manager.c\nSRCS-y += channel_monitor.c\n\nCFLAGS += -O3 -I$(RTE_SDK)/lib/librte_power/\nCFLAGS += $(WERROR_FLAGS)\n\nLDLIBS += -lvirt\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/vm_power_manager/channel_manager.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"channel_manager.h\"\n#include \"channel_commands.h\"\n#include \"channel_monitor.h\"\n\n\n#define RTE_LOGTYPE_CHANNEL_MANAGER RTE_LOGTYPE_USER1\n\n#define ITERATIVE_BITMASK_CHECK_64(mask_u64b, i) \\\n\t\tfor (i = 0; mask_u64b; mask_u64b &= ~(1ULL << i++)) \\\n\t\tif ((mask_u64b >> i) & 1) \\\n\n/* Global pointer to libvirt connection */\nstatic virConnectPtr global_vir_conn_ptr;\n\nstatic unsigned char *global_cpumaps;\nstatic virVcpuInfo *global_vircpuinfo;\nstatic size_t global_maplen;\n\nstatic unsigned global_n_host_cpus;\n\n/*\n * Represents a single Virtual Machine\n */\nstruct virtual_machine_info {\n\tchar name[CHANNEL_MGR_MAX_NAME_LEN];\n\trte_atomic64_t pcpu_mask[CHANNEL_CMDS_MAX_CPUS];\n\tstruct channel_info *channels[CHANNEL_CMDS_MAX_VM_CHANNELS];\n\tuint64_t channel_mask;\n\tuint8_t num_channels;\n\tenum vm_status status;\n\tvirDomainPtr domainPtr;\n\tvirDomainInfo info;\n\trte_spinlock_t config_spinlock;\n\tLIST_ENTRY(virtual_machine_info) vms_info;\n};\n\nLIST_HEAD(, virtual_machine_info) vm_list_head;\n\nstatic struct virtual_machine_info *\nfind_domain_by_name(const char *name)\n{\n\tstruct virtual_machine_info *info;\n\tLIST_FOREACH(info, &vm_list_head, vms_info) {\n\t\tif (!strncmp(info->name, name, CHANNEL_MGR_MAX_NAME_LEN-1))\n\t\t\treturn info;\n\t}\n\treturn NULL;\n}\n\nstatic int\nupdate_pcpus_mask(struct virtual_machine_info *vm_info)\n{\n\tvirVcpuInfoPtr cpuinfo;\n\tunsigned i, j;\n\tint n_vcpus;\n\tuint64_t mask;\n\n\tmemset(global_cpumaps, 0, CHANNEL_CMDS_MAX_CPUS*global_maplen);\n\n\tif (!virDomainIsActive(vm_info->domainPtr)) {\n\t\tn_vcpus = virDomainGetVcpuPinInfo(vm_info->domainPtr,\n\t\t\t\tvm_info->info.nrVirtCpu, global_cpumaps, global_maplen,\n\t\t\t\tVIR_DOMAIN_AFFECT_CONFIG);\n\t\tif (n_vcpus < 0) {\n\t\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Error getting vCPU info for \"\n\t\t\t\t\t\"in-active VM '%s'\\n\", vm_info->name);\n\t\t\treturn -1;\n\t\t}\n\t\tgoto update_pcpus;\n\t}\n\n\tmemset(global_vircpuinfo, 0, sizeof(*global_vircpuinfo)*\n\t\t\tCHANNEL_CMDS_MAX_CPUS);\n\n\tcpuinfo = global_vircpuinfo;\n\n\tn_vcpus = virDomainGetVcpus(vm_info->domainPtr, cpuinfo,\n\t\t\tCHANNEL_CMDS_MAX_CPUS, global_cpumaps, global_maplen);\n\tif (n_vcpus < 0) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Error getting vCPU info for \"\n\t\t\t\t\"active VM '%s'\\n\", vm_info->name);\n\t\treturn -1;\n\t}\nupdate_pcpus:\n\tif (n_vcpus >= CHANNEL_CMDS_MAX_CPUS) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Number of vCPUS(%u) is out of range \"\n\t\t\t\t\"0...%d\\n\", n_vcpus, CHANNEL_CMDS_MAX_CPUS-1);\n\t\treturn -1;\n\t}\n\tif (n_vcpus != vm_info->info.nrVirtCpu) {\n\t\tRTE_LOG(INFO, CHANNEL_MANAGER, \"Updating the number of vCPUs for VM '%s\"\n\t\t\t\t\" from %d -> %d\\n\", vm_info->name, vm_info->info.nrVirtCpu,\n\t\t\t\tn_vcpus);\n\t\tvm_info->info.nrVirtCpu = n_vcpus;\n\t}\n\tfor (i = 0; i < vm_info->info.nrVirtCpu; i++) {\n\t\tmask = 0;\n\t\tfor (j = 0; j < global_n_host_cpus; j++) {\n\t\t\tif (VIR_CPU_USABLE(global_cpumaps, global_maplen, i, j) > 0) {\n\t\t\t\tmask |= 1ULL << j;\n\t\t\t}\n\t\t}\n\t\trte_atomic64_set(&vm_info->pcpu_mask[i], mask);\n\t}\n\treturn 0;\n}\n\nint\nset_pcpus_mask(char *vm_name, unsigned vcpu, uint64_t core_mask)\n{\n\tunsigned i = 0;\n\tint flags = VIR_DOMAIN_AFFECT_LIVE|VIR_DOMAIN_AFFECT_CONFIG;\n\tstruct virtual_machine_info *vm_info;\n\tuint64_t mask = core_mask;\n\n\tif (vcpu >= CHANNEL_CMDS_MAX_CPUS) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"vCPU(%u) exceeds max allowable(%d)\\n\",\n\t\t\t\tvcpu, CHANNEL_CMDS_MAX_CPUS-1);\n\t\treturn -1;\n\t}\n\n\tvm_info = find_domain_by_name(vm_name);\n\tif (vm_info == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"VM '%s' not found\\n\", vm_name);\n\t\treturn -1;\n\t}\n\n\tif (!virDomainIsActive(vm_info->domainPtr)) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Unable to set vCPU(%u) to pCPU \"\n\t\t\t\t\"mask(0x%\"PRIx64\") for VM '%s', VM is not active\\n\",\n\t\t\t\tvcpu, core_mask, vm_info->name);\n\t\treturn -1;\n\t}\n\n\tif (vcpu >= vm_info->info.nrVirtCpu) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"vCPU(%u) exceeds the assigned number of \"\n\t\t\t\t\"vCPUs(%u)\\n\", vcpu, vm_info->info.nrVirtCpu);\n\t\treturn -1;\n\t}\n\tmemset(global_cpumaps, 0 , CHANNEL_CMDS_MAX_CPUS * global_maplen);\n\tITERATIVE_BITMASK_CHECK_64(mask, i) {\n\t\tVIR_USE_CPU(global_cpumaps, i);\n\t\tif (i >= global_n_host_cpus) {\n\t\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"CPU(%u) exceeds the available \"\n\t\t\t\t\t\"number of CPUs(%u)\\n\", i, global_n_host_cpus);\n\t\t\treturn -1;\n\t\t}\n\t}\n\tif (virDomainPinVcpuFlags(vm_info->domainPtr, vcpu, global_cpumaps,\n\t\t\tglobal_maplen, flags) < 0) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Unable to set vCPU(%u) to pCPU \"\n\t\t\t\t\"mask(0x%\"PRIx64\") for VM '%s'\\n\", vcpu, core_mask,\n\t\t\t\tvm_info->name);\n\t\treturn -1;\n\t}\n\trte_atomic64_set(&vm_info->pcpu_mask[vcpu], core_mask);\n\treturn 0;\n\n}\n\nint\nset_pcpu(char *vm_name, unsigned vcpu, unsigned core_num)\n{\n\tuint64_t mask = 1ULL << core_num;\n\n\treturn set_pcpus_mask(vm_name, vcpu, mask);\n}\n\nuint64_t\nget_pcpus_mask(struct channel_info *chan_info, unsigned vcpu)\n{\n\tstruct virtual_machine_info *vm_info =\n\t\t\t(struct virtual_machine_info *)chan_info->priv_info;\n\treturn rte_atomic64_read(&vm_info->pcpu_mask[vcpu]);\n}\n\nstatic inline int\nchannel_exists(struct virtual_machine_info *vm_info, unsigned channel_num)\n{\n\trte_spinlock_lock(&(vm_info->config_spinlock));\n\tif (vm_info->channel_mask & (1ULL << channel_num)) {\n\t\trte_spinlock_unlock(&(vm_info->config_spinlock));\n\t\treturn 1;\n\t}\n\trte_spinlock_unlock(&(vm_info->config_spinlock));\n\treturn 0;\n}\n\n\n\nstatic int\nopen_non_blocking_channel(struct channel_info *info)\n{\n\tint ret, flags;\n\tstruct sockaddr_un sock_addr;\n\tfd_set soc_fd_set;\n\tstruct timeval tv;\n\n\tinfo->fd = socket(AF_UNIX, SOCK_STREAM, 0);\n\tif (info->fd == -1) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Error(%s) creating socket for '%s'\\n\",\n\t\t\t\tstrerror(errno),\n\t\t\t\tinfo->channel_path);\n\t\treturn -1;\n\t}\n\tsock_addr.sun_family = AF_UNIX;\n\tmemcpy(&sock_addr.sun_path, info->channel_path,\n\t\t\tstrlen(info->channel_path)+1);\n\n\t/* Get current flags */\n\tflags = fcntl(info->fd, F_GETFL, 0);\n\tif (flags < 0) {\n\t\tRTE_LOG(WARNING, CHANNEL_MANAGER, \"Error(%s) fcntl get flags socket for\"\n\t\t\t\t\"'%s'\\n\", strerror(errno), info->channel_path);\n\t\treturn 1;\n\t}\n\t/* Set to Non Blocking */\n\tflags |= O_NONBLOCK;\n\tif (fcntl(info->fd, F_SETFL, flags) < 0) {\n\t\tRTE_LOG(WARNING, CHANNEL_MANAGER, \"Error(%s) setting non-blocking \"\n\t\t\t\t\"socket for '%s'\\n\", strerror(errno), info->channel_path);\n\t\treturn -1;\n\t}\n\tret = connect(info->fd, (struct sockaddr *)&sock_addr,\n\t\t\tsizeof(sock_addr));\n\tif (ret < 0) {\n\t\t/* ECONNREFUSED error is given when VM is not active */\n\t\tif (errno == ECONNREFUSED) {\n\t\t\tRTE_LOG(WARNING, CHANNEL_MANAGER, \"VM is not active or has not \"\n\t\t\t\t\t\"activated its endpoint to channel %s\\n\",\n\t\t\t\t\tinfo->channel_path);\n\t\t\treturn -1;\n\t\t}\n\t\t/* Wait for tv_sec if in progress */\n\t\telse if (errno == EINPROGRESS) {\n\t\t\ttv.tv_sec = 2;\n\t\t\ttv.tv_usec = 0;\n\t\t\tFD_ZERO(&soc_fd_set);\n\t\t\tFD_SET(info->fd, &soc_fd_set);\n\t\t\tif (select(info->fd+1, NULL, &soc_fd_set, NULL, &tv) > 0) {\n\t\t\t\tRTE_LOG(WARNING, CHANNEL_MANAGER, \"Timeout or error on channel \"\n\t\t\t\t\t\t\"'%s'\\n\", info->channel_path);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t} else {\n\t\t\t/* Any other error */\n\t\t\tRTE_LOG(WARNING, CHANNEL_MANAGER, \"Error(%s) connecting socket\"\n\t\t\t\t\t\" for '%s'\\n\", strerror(errno), info->channel_path);\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\nstatic int\nsetup_channel_info(struct virtual_machine_info **vm_info_dptr,\n\t\tstruct channel_info **chan_info_dptr, unsigned channel_num)\n{\n\tstruct channel_info *chan_info = *chan_info_dptr;\n\tstruct virtual_machine_info *vm_info = *vm_info_dptr;\n\n\tchan_info->channel_num = channel_num;\n\tchan_info->priv_info = (void *)vm_info;\n\tchan_info->status = CHANNEL_MGR_CHANNEL_DISCONNECTED;\n\tif (open_non_blocking_channel(chan_info) < 0) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Could not open channel: \"\n\t\t\t\t\"'%s' for VM '%s'\\n\",\n\t\t\t\tchan_info->channel_path, vm_info->name);\n\t\treturn -1;\n\t}\n\tif (add_channel_to_monitor(&chan_info) < 0) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Could add channel: \"\n\t\t\t\t\"'%s' to epoll ctl for VM '%s'\\n\",\n\t\t\t\tchan_info->channel_path, vm_info->name);\n\t\treturn -1;\n\n\t}\n\trte_spinlock_lock(&(vm_info->config_spinlock));\n\tvm_info->num_channels++;\n\tvm_info->channel_mask |= 1ULL << channel_num;\n\tvm_info->channels[channel_num] = chan_info;\n\tchan_info->status = CHANNEL_MGR_CHANNEL_CONNECTED;\n\trte_spinlock_unlock(&(vm_info->config_spinlock));\n\treturn 0;\n}\n\nint\nadd_all_channels(const char *vm_name)\n{\n\tDIR *d;\n\tstruct dirent *dir;\n\tstruct virtual_machine_info *vm_info;\n\tstruct channel_info *chan_info;\n\tchar *token, *remaining, *tail_ptr;\n\tchar socket_name[PATH_MAX];\n\tunsigned channel_num;\n\tint num_channels_enabled = 0;\n\n\t/* verify VM exists */\n\tvm_info = find_domain_by_name(vm_name);\n\tif (vm_info == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"VM: '%s' not found\"\n\t\t\t\t\" during channel discovery\\n\", vm_name);\n\t\treturn 0;\n\t}\n\tif (!virDomainIsActive(vm_info->domainPtr)) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"VM: '%s' is not active\\n\", vm_name);\n\t\tvm_info->status = CHANNEL_MGR_VM_INACTIVE;\n\t\treturn 0;\n\t}\n\td = opendir(CHANNEL_MGR_SOCKET_PATH);\n\tif (d == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Error opening directory '%s': %s\\n\",\n\t\t\t\tCHANNEL_MGR_SOCKET_PATH, strerror(errno));\n\t\treturn -1;\n\t}\n\twhile ((dir = readdir(d)) != NULL) {\n\t\tif (!strncmp(dir->d_name, \".\", 1) ||\n\t\t\t\t!strncmp(dir->d_name, \"..\", 2))\n\t\t\tcontinue;\n\n\t\tsnprintf(socket_name, sizeof(socket_name), \"%s\", dir->d_name);\n\t\tremaining = socket_name;\n\t\t/* Extract vm_name from \".\" */\n\t\ttoken = strsep(&remaining, \".\");\n\t\tif (remaining == NULL)\n\t\t\tcontinue;\n\t\tif (strncmp(vm_name, token, CHANNEL_MGR_MAX_NAME_LEN))\n\t\t\tcontinue;\n\n\t\t/* remaining should contain only */\n\t\terrno = 0;\n\t\tchannel_num = (unsigned)strtol(remaining, &tail_ptr, 0);\n\t\tif ((errno != 0) || (remaining[0] == '\\0') ||\n\t\t\t\ttail_ptr == NULL || (*tail_ptr != '\\0')) {\n\t\t\tRTE_LOG(WARNING, CHANNEL_MANAGER, \"Malformed channel name\"\n\t\t\t\t\t\"'%s' found it should be in the form of \"\n\t\t\t\t\t\"'.(decimal)'\\n\",\n\t\t\t\t\tdir->d_name);\n\t\t\tcontinue;\n\t\t}\n\t\tif (channel_num >= CHANNEL_CMDS_MAX_VM_CHANNELS) {\n\t\t\tRTE_LOG(WARNING, CHANNEL_MANAGER, \"Channel number(%u) is \"\n\t\t\t\t\t\"greater than max allowable: %d, skipping '%s%s'\\n\",\n\t\t\t\t\tchannel_num, CHANNEL_CMDS_MAX_VM_CHANNELS-1,\n\t\t\t\t\tCHANNEL_MGR_SOCKET_PATH, dir->d_name);\n\t\t\tcontinue;\n\t\t}\n\t\t/* if channel has not been added previously */\n\t\tif (channel_exists(vm_info, channel_num))\n\t\t\tcontinue;\n\n\t\tchan_info = rte_malloc(NULL, sizeof(*chan_info),\n\t\t\t\tRTE_CACHE_LINE_SIZE);\n\t\tif (chan_info == NULL) {\n\t\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Error allocating memory for \"\n\t\t\t\t\"channel '%s%s'\\n\", CHANNEL_MGR_SOCKET_PATH, dir->d_name);\n\t\t\tcontinue;\n\t\t}\n\n\t\tsnprintf(chan_info->channel_path,\n\t\t\t\tsizeof(chan_info->channel_path), \"%s%s\",\n\t\t\t\tCHANNEL_MGR_SOCKET_PATH, dir->d_name);\n\n\t\tif (setup_channel_info(&vm_info, &chan_info, channel_num) < 0) {\n\t\t\trte_free(chan_info);\n\t\t\tcontinue;\n\t\t}\n\n\t\tnum_channels_enabled++;\n\t}\n\tclosedir(d);\n\treturn num_channels_enabled;\n}\n\nint\nadd_channels(const char *vm_name, unsigned *channel_list,\n\t\tunsigned len_channel_list)\n{\n\tstruct virtual_machine_info *vm_info;\n\tstruct channel_info *chan_info;\n\tchar socket_path[PATH_MAX];\n\tunsigned i;\n\tint num_channels_enabled = 0;\n\n\tvm_info = find_domain_by_name(vm_name);\n\tif (vm_info == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Unable to add channels: VM '%s' \"\n\t\t\t\t\"not found\\n\", vm_name);\n\t\treturn 0;\n\t}\n\n\tif (!virDomainIsActive(vm_info->domainPtr)) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"VM: '%s' is not active\\n\", vm_name);\n\t\tvm_info->status = CHANNEL_MGR_VM_INACTIVE;\n\t\treturn 0;\n\t}\n\n\tfor (i = 0; i < len_channel_list; i++) {\n\n\t\tif (channel_list[i] >= CHANNEL_CMDS_MAX_VM_CHANNELS) {\n\t\t\tRTE_LOG(INFO, CHANNEL_MANAGER, \"Channel(%u) is out of range \"\n\t\t\t\t\t\t\t\"0...%d\\n\", channel_list[i],\n\t\t\t\t\t\t\tCHANNEL_CMDS_MAX_VM_CHANNELS-1);\n\t\t\tcontinue;\n\t\t}\n\t\tif (channel_exists(vm_info, channel_list[i])) {\n\t\t\tRTE_LOG(INFO, CHANNEL_MANAGER, \"Channel already exists, skipping \"\n\t\t\t\t\t\"'%s.%u'\\n\", vm_name, i);\n\t\t\tcontinue;\n\t\t}\n\n\t\tsnprintf(socket_path, sizeof(socket_path), \"%s%s.%u\",\n\t\t\t\tCHANNEL_MGR_SOCKET_PATH, vm_name, channel_list[i]);\n\t\terrno = 0;\n\t\tif (access(socket_path, F_OK) < 0) {\n\t\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Channel path '%s' error: \"\n\t\t\t\t\t\"%s\\n\", socket_path, strerror(errno));\n\t\t\tcontinue;\n\t\t}\n\t\tchan_info = rte_malloc(NULL, sizeof(*chan_info),\n\t\t\t\tRTE_CACHE_LINE_SIZE);\n\t\tif (chan_info == NULL) {\n\t\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Error allocating memory for \"\n\t\t\t\t\t\"channel '%s'\\n\", socket_path);\n\t\t\tcontinue;\n\t\t}\n\t\tsnprintf(chan_info->channel_path,\n\t\t\t\tsizeof(chan_info->channel_path), \"%s%s.%u\",\n\t\t\t\tCHANNEL_MGR_SOCKET_PATH, vm_name, channel_list[i]);\n\t\tif (setup_channel_info(&vm_info, &chan_info, channel_list[i]) < 0) {\n\t\t\trte_free(chan_info);\n\t\t\tcontinue;\n\t\t}\n\t\tnum_channels_enabled++;\n\n\t}\n\treturn num_channels_enabled;\n}\n\nint\nremove_channel(struct channel_info **chan_info_dptr)\n{\n\tstruct virtual_machine_info *vm_info;\n\tstruct channel_info *chan_info = *chan_info_dptr;\n\n\tclose(chan_info->fd);\n\n\tvm_info = (struct virtual_machine_info *)chan_info->priv_info;\n\n\trte_spinlock_lock(&(vm_info->config_spinlock));\n\tvm_info->channel_mask &= ~(1ULL << chan_info->channel_num);\n\tvm_info->num_channels--;\n\trte_spinlock_unlock(&(vm_info->config_spinlock));\n\n\trte_free(chan_info);\n\treturn 0;\n}\n\nint\nset_channel_status_all(const char *vm_name, enum channel_status status)\n{\n\tstruct virtual_machine_info *vm_info;\n\tunsigned i;\n\tuint64_t mask;\n\tint num_channels_changed = 0;\n\n\tif (!(status == CHANNEL_MGR_CHANNEL_CONNECTED ||\n\t\t\tstatus == CHANNEL_MGR_CHANNEL_DISABLED)) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Channels can only be enabled or \"\n\t\t\t\t\"disabled: Unable to change status for VM '%s'\\n\", vm_name);\n\t}\n\tvm_info = find_domain_by_name(vm_name);\n\tif (vm_info == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Unable to disable channels: VM '%s' \"\n\t\t\t\t\"not found\\n\", vm_name);\n\t\treturn 0;\n\t}\n\n\trte_spinlock_lock(&(vm_info->config_spinlock));\n\tmask = vm_info->channel_mask;\n\tITERATIVE_BITMASK_CHECK_64(mask, i) {\n\t\tvm_info->channels[i]->status = status;\n\t\tnum_channels_changed++;\n\t}\n\trte_spinlock_unlock(&(vm_info->config_spinlock));\n\treturn num_channels_changed;\n\n}\n\nint\nset_channel_status(const char *vm_name, unsigned *channel_list,\n\t\tunsigned len_channel_list, enum channel_status status)\n{\n\tstruct virtual_machine_info *vm_info;\n\tunsigned i;\n\tint num_channels_changed = 0;\n\n\tif (!(status == CHANNEL_MGR_CHANNEL_CONNECTED ||\n\t\t\tstatus == CHANNEL_MGR_CHANNEL_DISABLED)) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Channels can only be enabled or \"\n\t\t\t\t\"disabled: Unable to change status for VM '%s'\\n\", vm_name);\n\t}\n\tvm_info = find_domain_by_name(vm_name);\n\tif (vm_info == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Unable to add channels: VM '%s' \"\n\t\t\t\t\"not found\\n\", vm_name);\n\t\treturn 0;\n\t}\n\tfor (i = 0; i < len_channel_list; i++) {\n\t\tif (channel_exists(vm_info, channel_list[i])) {\n\t\t\trte_spinlock_lock(&(vm_info->config_spinlock));\n\t\t\tvm_info->channels[channel_list[i]]->status = status;\n\t\t\trte_spinlock_unlock(&(vm_info->config_spinlock));\n\t\t\tnum_channels_changed++;\n\t\t}\n\t}\n\treturn num_channels_changed;\n}\n\nint\nget_info_vm(const char *vm_name, struct vm_info *info)\n{\n\tstruct virtual_machine_info *vm_info;\n\tunsigned i, channel_num = 0;\n\tuint64_t mask;\n\n\tvm_info = find_domain_by_name(vm_name);\n\tif (vm_info == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"VM '%s' not found\\n\", vm_name);\n\t\treturn -1;\n\t}\n\tinfo->status = CHANNEL_MGR_VM_ACTIVE;\n\tif (!virDomainIsActive(vm_info->domainPtr))\n\t\tinfo->status = CHANNEL_MGR_VM_INACTIVE;\n\n\trte_spinlock_lock(&(vm_info->config_spinlock));\n\n\tmask = vm_info->channel_mask;\n\tITERATIVE_BITMASK_CHECK_64(mask, i) {\n\t\tinfo->channels[channel_num].channel_num = i;\n\t\tmemcpy(info->channels[channel_num].channel_path,\n\t\t\t\tvm_info->channels[i]->channel_path, UNIX_PATH_MAX);\n\t\tinfo->channels[channel_num].status = vm_info->channels[i]->status;\n\t\tinfo->channels[channel_num].fd = vm_info->channels[i]->fd;\n\t\tchannel_num++;\n\t}\n\n\tinfo->num_channels = channel_num;\n\tinfo->num_vcpus = vm_info->info.nrVirtCpu;\n\trte_spinlock_unlock(&(vm_info->config_spinlock));\n\n\tmemcpy(info->name, vm_info->name, sizeof(vm_info->name));\n\tfor (i = 0; i < info->num_vcpus; i++) {\n\t\tinfo->pcpu_mask[i] = rte_atomic64_read(&vm_info->pcpu_mask[i]);\n\t}\n\treturn 0;\n}\n\nint\nadd_vm(const char *vm_name)\n{\n\tstruct virtual_machine_info *new_domain;\n\tvirDomainPtr dom_ptr;\n\tint i;\n\n\tif (find_domain_by_name(vm_name) != NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Unable to add VM: VM '%s' \"\n\t\t\t\t\"already exists\\n\", vm_name);\n\t\treturn -1;\n\t}\n\n\tif (global_vir_conn_ptr == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"No connection to hypervisor exists\\n\");\n\t\treturn -1;\n\t}\n\tdom_ptr = virDomainLookupByName(global_vir_conn_ptr, vm_name);\n\tif (dom_ptr == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Error on VM lookup with libvirt: \"\n\t\t\t\t\"VM '%s' not found\\n\", vm_name);\n\t\treturn -1;\n\t}\n\n\tnew_domain = rte_malloc(\"virtual_machine_info\", sizeof(*new_domain),\n\t\t\tRTE_CACHE_LINE_SIZE);\n\tif (new_domain == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Unable to allocate memory for VM \"\n\t\t\t\t\"info\\n\");\n\t\treturn -1;\n\t}\n\tnew_domain->domainPtr = dom_ptr;\n\tif (virDomainGetInfo(new_domain->domainPtr, &new_domain->info) != 0) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Unable to get libvirt VM info\\n\");\n\t\trte_free(new_domain);\n\t\treturn -1;\n\t}\n\tif (new_domain->info.nrVirtCpu > CHANNEL_CMDS_MAX_CPUS) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Error the number of virtual CPUs(%u) is \"\n\t\t\t\t\"greater than allowable(%d)\\n\", new_domain->info.nrVirtCpu,\n\t\t\t\tCHANNEL_CMDS_MAX_CPUS);\n\t\trte_free(new_domain);\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; i < CHANNEL_CMDS_MAX_CPUS; i++) {\n\t\trte_atomic64_init(&new_domain->pcpu_mask[i]);\n\t}\n\tif (update_pcpus_mask(new_domain) < 0) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Error getting physical CPU pinning\\n\");\n\t\trte_free(new_domain);\n\t\treturn -1;\n\t}\n\tstrncpy(new_domain->name, vm_name, sizeof(new_domain->name));\n\tnew_domain->channel_mask = 0;\n\tnew_domain->num_channels = 0;\n\n\tif (!virDomainIsActive(dom_ptr))\n\t\tnew_domain->status = CHANNEL_MGR_VM_INACTIVE;\n\telse\n\t\tnew_domain->status = CHANNEL_MGR_VM_ACTIVE;\n\n\trte_spinlock_init(&(new_domain->config_spinlock));\n\tLIST_INSERT_HEAD(&vm_list_head, new_domain, vms_info);\n\treturn 0;\n}\n\nint\nremove_vm(const char *vm_name)\n{\n\tstruct virtual_machine_info *vm_info = find_domain_by_name(vm_name);\n\n\tif (vm_info == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Unable to remove VM: VM '%s' \"\n\t\t\t\t\"not found\\n\", vm_name);\n\t\treturn -1;\n\t}\n\trte_spinlock_lock(&vm_info->config_spinlock);\n\tif (vm_info->num_channels != 0) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Unable to remove VM '%s', there are \"\n\t\t\t\t\"%\"PRId8\" channels still active\\n\",\n\t\t\t\tvm_name, vm_info->num_channels);\n\t\trte_spinlock_unlock(&vm_info->config_spinlock);\n\t\treturn -1;\n\t}\n\tLIST_REMOVE(vm_info, vms_info);\n\trte_spinlock_unlock(&vm_info->config_spinlock);\n\trte_free(vm_info);\n\treturn 0;\n}\n\nstatic void\ndisconnect_hypervisor(void)\n{\n\tif (global_vir_conn_ptr != NULL) {\n\t\tvirConnectClose(global_vir_conn_ptr);\n\t\tglobal_vir_conn_ptr = NULL;\n\t}\n}\n\nstatic int\nconnect_hypervisor(const char *path)\n{\n\tif (global_vir_conn_ptr != NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Error connecting to %s, connection \"\n\t\t\t\t\"already established\\n\", path);\n\t\treturn -1;\n\t}\n\tglobal_vir_conn_ptr = virConnectOpen(path);\n\tif (global_vir_conn_ptr == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Error failed to open connection to \"\n\t\t\t\t\"Hypervisor '%s'\\n\", path);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nint\nchannel_manager_init(const char *path)\n{\n\tint n_cpus;\n\n\tLIST_INIT(&vm_list_head);\n\tif (connect_hypervisor(path) < 0) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Unable to initialize channel manager\\n\");\n\t\treturn -1;\n\t}\n\n\tglobal_maplen = VIR_CPU_MAPLEN(CHANNEL_CMDS_MAX_CPUS);\n\n\tglobal_vircpuinfo = rte_zmalloc(NULL, sizeof(*global_vircpuinfo) *\n\t\t\tCHANNEL_CMDS_MAX_CPUS, RTE_CACHE_LINE_SIZE);\n\tif (global_vircpuinfo == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Error allocating memory for CPU Info\\n\");\n\t\tgoto error;\n\t}\n\tglobal_cpumaps = rte_zmalloc(NULL, CHANNEL_CMDS_MAX_CPUS * global_maplen,\n\t\t\tRTE_CACHE_LINE_SIZE);\n\tif (global_cpumaps == NULL) {\n\t\tgoto error;\n\t}\n\n\tn_cpus = virNodeGetCPUMap(global_vir_conn_ptr, NULL, NULL, 0);\n\tif (n_cpus <= 0) {\n\t\tRTE_LOG(ERR, CHANNEL_MANAGER, \"Unable to get the number of Host \"\n\t\t\t\t\"CPUs\\n\");\n\t\tgoto error;\n\t}\n\tglobal_n_host_cpus = (unsigned)n_cpus;\n\n\tif (global_n_host_cpus > CHANNEL_CMDS_MAX_CPUS) {\n\t\tRTE_LOG(WARNING, CHANNEL_MANAGER, \"The number of host CPUs(%u) exceeds the \"\n\t\t\t\t\"maximum of %u. No cores over %u should be used.\\n\",\n\t\t\t\tglobal_n_host_cpus, CHANNEL_CMDS_MAX_CPUS,\n\t\t\t\tCHANNEL_CMDS_MAX_CPUS - 1);\n\t\tglobal_n_host_cpus = CHANNEL_CMDS_MAX_CPUS;\n\t}\n\n\treturn 0;\nerror:\n\tdisconnect_hypervisor();\n\treturn -1;\n}\n\nvoid\nchannel_manager_exit(void)\n{\n\tunsigned i;\n\tuint64_t mask;\n\tstruct virtual_machine_info *vm_info;\n\n\tLIST_FOREACH(vm_info, &vm_list_head, vms_info) {\n\n\t\trte_spinlock_lock(&(vm_info->config_spinlock));\n\n\t\tmask = vm_info->channel_mask;\n\t\tITERATIVE_BITMASK_CHECK_64(mask, i) {\n\t\t\tremove_channel_from_monitor(vm_info->channels[i]);\n\t\t\tclose(vm_info->channels[i]->fd);\n\t\t\trte_free(vm_info->channels[i]);\n\t\t}\n\t\trte_spinlock_unlock(&(vm_info->config_spinlock));\n\n\t\tLIST_REMOVE(vm_info, vms_info);\n\t\trte_free(vm_info);\n\t}\n\n\trte_free(global_cpumaps);\n\trte_free(global_vircpuinfo);\n\tdisconnect_hypervisor();\n}\n" }, { "path": "examples/vm_power_manager/channel_manager.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef CHANNEL_MANAGER_H_\n#define CHANNEL_MANAGER_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n#include \n#include \"channel_commands.h\"\n\n/* Maximum name length including '\\0' terminator */\n#define CHANNEL_MGR_MAX_NAME_LEN 64\n\n/* Maximum number of channels to each Virtual Machine */\n#define CHANNEL_MGR_MAX_CHANNELS 64\n\n/* Hypervisor Path for libvirt(qemu/KVM) */\n#define CHANNEL_MGR_DEFAULT_HV_PATH \"qemu:///system\"\n\n/* File socket directory */\n#define CHANNEL_MGR_SOCKET_PATH \"/tmp/powermonitor/\"\n\n#ifndef UNIX_PATH_MAX\nstruct sockaddr_un _sockaddr_un;\n#define UNIX_PATH_MAX sizeof(_sockaddr_un.sun_path)\n#endif\n\n/* Communication Channel Status */\nenum channel_status { CHANNEL_MGR_CHANNEL_DISCONNECTED = 0,\n\tCHANNEL_MGR_CHANNEL_CONNECTED,\n\tCHANNEL_MGR_CHANNEL_DISABLED,\n\tCHANNEL_MGR_CHANNEL_PROCESSING};\n\n/* VM libvirt(qemu/KVM) connection status */\nenum vm_status { CHANNEL_MGR_VM_INACTIVE = 0, CHANNEL_MGR_VM_ACTIVE};\n\n/*\n * Represents a single and exclusive VM channel that exists between a guest and\n * the host.\n */\nstruct channel_info {\n\tchar channel_path[UNIX_PATH_MAX]; /**< Path to host socket */\n\tvolatile uint32_t status; /**< Connection status(enum channel_status) */\n\tint fd; /**< AF_UNIX socket fd */\n\tunsigned channel_num; /**< CHANNEL_MGR_SOCKET_PATH/.channel_num */\n\tvoid *priv_info; /**< Pointer to private info, do not modify */\n};\n\n/* Represents a single VM instance used to return internal information about\n * a VM */\nstruct vm_info {\n\tchar name[CHANNEL_MGR_MAX_NAME_LEN]; /**< VM name */\n\tenum vm_status status; /**< libvirt status */\n\tuint64_t pcpu_mask[CHANNEL_CMDS_MAX_CPUS]; /**< pCPU mask for each vCPU */\n\tunsigned num_vcpus; /**< number of vCPUS */\n\tstruct channel_info channels[CHANNEL_MGR_MAX_CHANNELS]; /**< Array of channel_info */\n\tunsigned num_channels; /**< Number of channels */\n};\n\n/**\n * Initialize the Channel Manager resources and connect to the Hypervisor\n * specified in path.\n * This must be successfully called first before calling any other functions.\n * It must only be call once;\n *\n * @param path\n * Must be a local path, e.g. qemu:///system.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint channel_manager_init(const char *path);\n\n/**\n * Free resources associated with the Channel Manager.\n *\n * @param path\n * Must be a local path, e.g. qemu:///system.\n *\n * @return\n * None\n */\nvoid channel_manager_exit(void);\n\n/**\n * Get the Physical CPU mask for VM lcore channel(vcpu), result is assigned to\n * core_mask.\n * It is not thread-safe.\n *\n * @param chan_info\n * Pointer to struct channel_info\n *\n * @param vcpu\n * The virtual CPU to query.\n *\n *\n * @return\n * - 0 on error.\n * - >0 on success.\n */\nuint64_t get_pcpus_mask(struct channel_info *chan_info, unsigned vcpu);\n\n/**\n * Set the Physical CPU mask for the specified vCPU.\n * It is not thread-safe.\n *\n * @param name\n * Virtual Machine name to lookup\n *\n * @param vcpu\n * The virtual CPU to set.\n *\n * @param core_mask\n * The core mask of the physical CPU(s) to bind the vCPU\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint set_pcpus_mask(char *vm_name, unsigned vcpu, uint64_t core_mask);\n\n/**\n * Set the Physical CPU for the specified vCPU.\n * It is not thread-safe.\n *\n * @param name\n * Virtual Machine name to lookup\n *\n * @param vcpu\n * The virtual CPU to set.\n *\n * @param core_num\n * The core number of the physical CPU(s) to bind the vCPU\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint set_pcpu(char *vm_name, unsigned vcpu, unsigned core_num);\n/**\n * Add a VM as specified by name to the Channel Manager. The name must\n * correspond to a valid libvirt domain name.\n * This is required prior to adding channels.\n * It is not thread-safe.\n *\n * @param name\n * Virtual Machine name to lookup.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint add_vm(const char *name);\n\n/**\n * Remove a previously added Virtual Machine from the Channel Manager\n * It is not thread-safe.\n *\n * @param name\n * Virtual Machine name to lookup.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint remove_vm(const char *name);\n\n/**\n * Add all available channels to the VM as specified by name.\n * Channels in the form of paths\n * (CHANNEL_MGR_SOCKET_PATH/.) will only be parsed.\n * It is not thread-safe.\n *\n * @param name\n * Virtual Machine name to lookup.\n *\n * @return\n * - N the number of channels added for the VM\n */\nint add_all_channels(const char *vm_name);\n\n/**\n * Add the channel numbers in channel_list to the domain specified by name.\n * Channels in the form of paths\n * (CHANNEL_MGR_SOCKET_PATH/.) will only be parsed.\n * It is not thread-safe.\n *\n * @param name\n * Virtual Machine name to add channels.\n *\n * @param channel_list\n * Pointer to list of unsigned integers, representing the channel number to add\n * It must be allocated outside of this function.\n *\n * @param num_channels\n * The amount of channel numbers in channel_list\n *\n * @return\n * - N the number of channels added for the VM\n * - 0 for error\n */\nint add_channels(const char *vm_name, unsigned *channel_list,\n\t\tunsigned num_channels);\n\n/**\n * Remove a channel definition from the channel manager. This must only be\n * called from the channel monitor thread.\n *\n * @param chan_info\n * Pointer to a valid struct channel_info.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint remove_channel(struct channel_info **chan_info_dptr);\n\n/**\n * For all channels associated with a Virtual Machine name, update the\n * connection status. Valid states are CHANNEL_MGR_CHANNEL_CONNECTED or\n * CHANNEL_MGR_CHANNEL_DISABLED only.\n *\n *\n * @param name\n * Virtual Machine name to modify all channels.\n *\n * @param status\n * The status to set each channel\n *\n * @param num_channels\n * The amount of channel numbers in channel_list\n *\n * @return\n * - N the number of channels added for the VM\n * - 0 for error\n */\nint set_channel_status_all(const char *name, enum channel_status status);\n\n/**\n * For all channels in channel_list associated with a Virtual Machine name\n * update the connection status of each.\n * Valid states are CHANNEL_MGR_CHANNEL_CONNECTED or\n * CHANNEL_MGR_CHANNEL_DISABLED only.\n * It is not thread-safe.\n *\n * @param name\n * Virtual Machine name to add channels.\n *\n * @param channel_list\n * Pointer to list of unsigned integers, representing the channel numbers to\n * modify.\n * It must be allocated outside of this function.\n *\n * @param num_channels\n * The amount of channel numbers in channel_list\n *\n * @return\n * - N the number of channels modified for the VM\n * - 0 for error\n */\nint set_channel_status(const char *vm_name, unsigned *channel_list,\n\t\tunsigned len_channel_list, enum channel_status status);\n\n/**\n * Populates a pointer to struct vm_info associated with vm_name.\n *\n * @param vm_name\n * The name of the virtual machine to lookup.\n *\n * @param vm_info\n * Pointer to a struct vm_info, this must be allocated prior to calling this\n * function.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint get_info_vm(const char *vm_name, struct vm_info *info);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* CHANNEL_MANAGER_H_ */\n" }, { "path": "examples/vm_power_manager/channel_monitor.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n\n#include \"channel_monitor.h\"\n#include \"channel_commands.h\"\n#include \"channel_manager.h\"\n#include \"power_manager.h\"\n\n#define RTE_LOGTYPE_CHANNEL_MONITOR RTE_LOGTYPE_USER1\n\n#define MAX_EVENTS 256\n\n\nstatic volatile unsigned run_loop = 1;\nstatic int global_event_fd;\nstatic struct epoll_event *global_events_list;\n\nvoid channel_monitor_exit(void)\n{\n\trun_loop = 0;\n\trte_free(global_events_list);\n}\n\nstatic int\nprocess_request(struct channel_packet *pkt, struct channel_info *chan_info)\n{\n\tuint64_t core_mask;\n\n\tif (chan_info == NULL)\n\t\treturn -1;\n\n\tif (rte_atomic32_cmpset(&(chan_info->status), CHANNEL_MGR_CHANNEL_CONNECTED,\n\t\t\tCHANNEL_MGR_CHANNEL_PROCESSING) == 0)\n\t\treturn -1;\n\n\tif (pkt->command == CPU_POWER) {\n\t\tcore_mask = get_pcpus_mask(chan_info, pkt->resource_id);\n\t\tif (core_mask == 0) {\n\t\t\tRTE_LOG(ERR, CHANNEL_MONITOR, \"Error get physical CPU mask for \"\n\t\t\t\t\"channel '%s' using vCPU(%u)\\n\", chan_info->channel_path,\n\t\t\t\t(unsigned)pkt->unit);\n\t\t\treturn -1;\n\t\t}\n\t\tif (__builtin_popcountll(core_mask) == 1) {\n\n\t\t\tunsigned core_num = __builtin_ffsll(core_mask) - 1;\n\n\t\t\tswitch (pkt->unit) {\n\t\t\tcase(CPU_POWER_SCALE_MIN):\n\t\t\t\t\tpower_manager_scale_core_min(core_num);\n\t\t\tbreak;\n\t\t\tcase(CPU_POWER_SCALE_MAX):\n\t\t\t\t\tpower_manager_scale_core_max(core_num);\n\t\t\tbreak;\n\t\t\tcase(CPU_POWER_SCALE_DOWN):\n\t\t\t\t\tpower_manager_scale_core_down(core_num);\n\t\t\tbreak;\n\t\t\tcase(CPU_POWER_SCALE_UP):\n\t\t\t\t\tpower_manager_scale_core_up(core_num);\n\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else {\n\t\t\tswitch (pkt->unit) {\n\t\t\tcase(CPU_POWER_SCALE_MIN):\n\t\t\t\t\tpower_manager_scale_mask_min(core_mask);\n\t\t\tbreak;\n\t\t\tcase(CPU_POWER_SCALE_MAX):\n\t\t\t\t\tpower_manager_scale_mask_max(core_mask);\n\t\t\tbreak;\n\t\t\tcase(CPU_POWER_SCALE_DOWN):\n\t\t\t\t\tpower_manager_scale_mask_down(core_mask);\n\t\t\tbreak;\n\t\t\tcase(CPU_POWER_SCALE_UP):\n\t\t\t\t\tpower_manager_scale_mask_up(core_mask);\n\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t}\n\t}\n\t/* Return is not checked as channel status may have been set to DISABLED\n\t * from management thread\n\t */\n\trte_atomic32_cmpset(&(chan_info->status), CHANNEL_MGR_CHANNEL_PROCESSING,\n\t\t\tCHANNEL_MGR_CHANNEL_CONNECTED);\n\treturn 0;\n\n}\n\nint\nadd_channel_to_monitor(struct channel_info **chan_info)\n{\n\tstruct channel_info *info = *chan_info;\n\tstruct epoll_event event;\n\n\tevent.events = EPOLLIN;\n\tevent.data.ptr = info;\n\tif (epoll_ctl(global_event_fd, EPOLL_CTL_ADD, info->fd, &event) < 0) {\n\t\tRTE_LOG(ERR, CHANNEL_MONITOR, \"Unable to add channel '%s' \"\n\t\t\t\t\"to epoll\\n\", info->channel_path);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nint\nremove_channel_from_monitor(struct channel_info *chan_info)\n{\n\tif (epoll_ctl(global_event_fd, EPOLL_CTL_DEL, chan_info->fd, NULL) < 0) {\n\t\tRTE_LOG(ERR, CHANNEL_MONITOR, \"Unable to remove channel '%s' \"\n\t\t\t\t\"from epoll\\n\", chan_info->channel_path);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nint\nchannel_monitor_init(void)\n{\n\tglobal_event_fd = epoll_create1(0);\n\tif (global_event_fd == 0) {\n\t\tRTE_LOG(ERR, CHANNEL_MONITOR, \"Error creating epoll context with \"\n\t\t\t\t\"error %s\\n\", strerror(errno));\n\t\treturn -1;\n\t}\n\tglobal_events_list = rte_malloc(\"epoll_events\", sizeof(*global_events_list)\n\t\t\t* MAX_EVENTS, RTE_CACHE_LINE_SIZE);\n\tif (global_events_list == NULL) {\n\t\tRTE_LOG(ERR, CHANNEL_MONITOR, \"Unable to rte_malloc for \"\n\t\t\t\t\"epoll events\\n\");\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nvoid\nrun_channel_monitor(void)\n{\n\twhile (run_loop) {\n\t\tint n_events, i;\n\n\t\tn_events = epoll_wait(global_event_fd, global_events_list,\n\t\t\t\tMAX_EVENTS, 1);\n\t\tif (!run_loop)\n\t\t\tbreak;\n\t\tfor (i = 0; i < n_events; i++) {\n\t\t\tstruct channel_info *chan_info = (struct channel_info *)\n\t\t\t\t\tglobal_events_list[i].data.ptr;\n\t\t\tif ((global_events_list[i].events & EPOLLERR) ||\n\t\t\t\t\t(global_events_list[i].events & EPOLLHUP)) {\n\t\t\t\tRTE_LOG(DEBUG, CHANNEL_MONITOR, \"Remote closed connection for \"\n\t\t\t\t\t\t\"channel '%s'\\n\", chan_info->channel_path);\n\t\t\t\tremove_channel(&chan_info);\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tif (global_events_list[i].events & EPOLLIN) {\n\n\t\t\t\tint n_bytes, err = 0;\n\t\t\t\tstruct channel_packet pkt;\n\t\t\t\tvoid *buffer = &pkt;\n\t\t\t\tint buffer_len = sizeof(pkt);\n\n\t\t\t\twhile (buffer_len > 0) {\n\t\t\t\t\tn_bytes = read(chan_info->fd, buffer, buffer_len);\n\t\t\t\t\tif (n_bytes == buffer_len)\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tif (n_bytes == -1) {\n\t\t\t\t\t\terr = errno;\n\t\t\t\t\t\tRTE_LOG(DEBUG, CHANNEL_MONITOR, \"Received error on \"\n\t\t\t\t\t\t\t\t\"channel '%s' read: %s\\n\",\n\t\t\t\t\t\t\t\tchan_info->channel_path, strerror(err));\n\t\t\t\t\t\tremove_channel(&chan_info);\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t\tbuffer = (char *)buffer + n_bytes;\n\t\t\t\t\tbuffer_len -= n_bytes;\n\t\t\t\t}\n\t\t\t\tif (!err)\n\t\t\t\t\tprocess_request(&pkt, chan_info);\n\t\t\t}\n\t\t}\n\t}\n}\n" }, { "path": "examples/vm_power_manager/channel_monitor.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef CHANNEL_MONITOR_H_\n#define CHANNEL_MONITOR_H_\n\n#include \"channel_manager.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Setup the Channel Monitor resources required to initialize epoll.\n * Must be called first before calling other functions.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint channel_monitor_init(void);\n\n/**\n * Run the channel monitor, loops forever on on epoll_wait.\n *\n *\n * @return\n * None\n */\nvoid run_channel_monitor(void);\n\n/**\n * Exit the Channel Monitor, exiting the epoll_wait loop and events processing.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nvoid channel_monitor_exit(void);\n\n/**\n * Add an open channel to monitor via epoll. A pointer to struct channel_info\n * will be registered with epoll for event processing.\n * It is thread-safe.\n *\n * @param chan_info\n * Pointer to struct channel_info pointer.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint add_channel_to_monitor(struct channel_info **chan_info);\n\n/**\n * Remove a previously added channel from epoll control.\n *\n * @param chan_info\n * Pointer to struct channel_info.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint remove_channel_from_monitor(struct channel_info *chan_info);\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* CHANNEL_MONITOR_H_ */\n" }, { "path": "examples/vm_power_manager/guest_cli/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overridden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = guest_vm_power_mgr\n\n# all source are stored in SRCS-y\nSRCS-y := main.c vm_power_cli_guest.c\n\nCFLAGS += -O3 -I$(RTE_SDK)/lib/librte_power/\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/vm_power_manager/guest_cli/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n*/\n#include \n\n#include \n#include \n#include \n#include \n\n#include \"vm_power_cli_guest.h\"\n\nstatic void\nsig_handler(int signo)\n{\n\tprintf(\"Received signal %d, exiting...\\n\", signo);\n\tunsigned lcore_id;\n\n\tRTE_LCORE_FOREACH(lcore_id) {\n\t\trte_power_exit(lcore_id);\n\t}\n\n}\n\nint\nmain(int argc, char **argv)\n{\n\tint ret;\n\tunsigned lcore_id;\n\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_panic(\"Cannot init EAL\\n\");\n\n\tsignal(SIGINT, sig_handler);\n\tsignal(SIGTERM, sig_handler);\n\n\trte_power_set_env(PM_ENV_KVM_VM);\n\tRTE_LCORE_FOREACH(lcore_id) {\n\t\trte_power_init(lcore_id);\n\t}\n\trun_cli(NULL);\n\n\treturn 0;\n}\n" }, { "path": "examples/vm_power_manager/guest_cli/vm_power_cli_guest.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"vm_power_cli_guest.h\"\n\n\n#define CHANNEL_PATH \"/dev/virtio-ports/virtio.serial.port.poweragent\"\n\n\n#define RTE_LOGTYPE_GUEST_CHANNEL RTE_LOGTYPE_USER1\n\nstruct cmd_quit_result {\n\tcmdline_fixed_string_t quit;\n};\n\nstatic void cmd_quit_parsed(__attribute__((unused)) void *parsed_result,\n\t\t\t\t__attribute__((unused)) struct cmdline *cl,\n\t\t\t __attribute__((unused)) void *data)\n{\n\tunsigned lcore_id;\n\n\tRTE_LCORE_FOREACH(lcore_id) {\n\t\trte_power_exit(lcore_id);\n\t}\n\tcmdline_quit(cl);\n}\n\ncmdline_parse_token_string_t cmd_quit_quit =\n\tTOKEN_STRING_INITIALIZER(struct cmd_quit_result, quit, \"quit\");\n\ncmdline_parse_inst_t cmd_quit = {\n\t.f = cmd_quit_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"close the application\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_quit_quit,\n\t\tNULL,\n\t},\n};\n\n/* *** VM operations *** */\n\nstruct cmd_set_cpu_freq_result {\n\tcmdline_fixed_string_t set_cpu_freq;\n\tuint8_t lcore_id;\n\tcmdline_fixed_string_t cmd;\n};\n\nstatic void\ncmd_set_cpu_freq_parsed(void *parsed_result, struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tint ret = -1;\n\tstruct cmd_set_cpu_freq_result *res = parsed_result;\n\n\tif (!strcmp(res->cmd , \"up\"))\n\t\tret = rte_power_freq_up(res->lcore_id);\n\telse if (!strcmp(res->cmd , \"down\"))\n\t\tret = rte_power_freq_down(res->lcore_id);\n\telse if (!strcmp(res->cmd , \"min\"))\n\t\tret = rte_power_freq_min(res->lcore_id);\n\telse if (!strcmp(res->cmd , \"max\"))\n\t\tret = rte_power_freq_max(res->lcore_id);\n\tif (ret != 1)\n\t\tcmdline_printf(cl, \"Error sending message: %s\\n\", strerror(ret));\n}\n\ncmdline_parse_token_string_t cmd_set_cpu_freq =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_cpu_freq_result,\n\t\t\tset_cpu_freq, \"set_cpu_freq\");\ncmdline_parse_token_string_t cmd_set_cpu_freq_core_num =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_cpu_freq_result,\n\t\t\tlcore_id, UINT8);\ncmdline_parse_token_string_t cmd_set_cpu_freq_cmd_cmd =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_cpu_freq_result,\n\t\t\tcmd, \"up#down#min#max\");\n\ncmdline_parse_inst_t cmd_set_cpu_freq_set = {\n\t.f = cmd_set_cpu_freq_parsed,\n\t.data = NULL,\n\t.help_str = \"set_cpu_freq , Set the current \"\n\t\t\t\"frequency for the specified core by scaling up/down/min/max\",\n\t.tokens = {\n\t\t(void *)&cmd_set_cpu_freq,\n\t\t(void *)&cmd_set_cpu_freq_core_num,\n\t\t(void *)&cmd_set_cpu_freq_cmd_cmd,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_ctx_t main_ctx[] = {\n\t\t(cmdline_parse_inst_t *)&cmd_quit,\n\t\t(cmdline_parse_inst_t *)&cmd_set_cpu_freq_set,\n\t\tNULL,\n};\n\nvoid\nrun_cli(__attribute__((unused)) void *arg)\n{\n\tstruct cmdline *cl;\n\n\tcl = cmdline_stdin_new(main_ctx, \"vmpower(guest)> \");\n\tif (cl == NULL)\n\t\treturn;\n\n\tcmdline_interact(cl);\n\tcmdline_stdin_exit(cl);\n}\n" }, { "path": "examples/vm_power_manager/guest_cli/vm_power_cli_guest.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef VM_POWER_CLI_H_\n#define VM_POWER_CLI_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"channel_commands.h\"\n\nint guest_channel_host_connect(unsigned lcore_id);\n\nint guest_channel_send_msg(struct channel_packet *pkt, unsigned lcore_id);\n\nvoid guest_channel_host_disconnect(unsigned lcore_id);\n\nvoid run_cli(__attribute__((unused)) void *arg);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* VM_POWER_CLI_H_ */\n" }, { "path": "examples/vm_power_manager/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"channel_manager.h\"\n#include \"channel_monitor.h\"\n#include \"power_manager.h\"\n#include \"vm_power_cli.h\"\n\nstatic int\nrun_monitor(__attribute__((unused)) void *arg)\n{\n\tif (channel_monitor_init() < 0) {\n\t\tprintf(\"Unable to initialize channel monitor\\n\");\n\t\treturn -1;\n\t}\n\trun_channel_monitor();\n\treturn 0;\n}\n\nstatic void\nsig_handler(int signo)\n{\n\tprintf(\"Received signal %d, exiting...\\n\", signo);\n\tchannel_monitor_exit();\n\tchannel_manager_exit();\n\tpower_manager_exit();\n\n}\n\nint\nmain(int argc, char **argv)\n{\n\tint ret;\n\tunsigned lcore_id;\n\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_panic(\"Cannot init EAL\\n\");\n\n\tsignal(SIGINT, sig_handler);\n\tsignal(SIGTERM, sig_handler);\n\n\tlcore_id = rte_get_next_lcore(-1, 1, 0);\n\tif (lcore_id == RTE_MAX_LCORE) {\n\t\tRTE_LOG(ERR, EAL, \"A minimum of two cores are required to run \"\n\t\t\t\t\"application\\n\");\n\t\treturn 0;\n\t}\n\trte_eal_remote_launch(run_monitor, NULL, lcore_id);\n\n\tif (power_manager_init() < 0) {\n\t\tprintf(\"Unable to initialize power manager\\n\");\n\t\treturn -1;\n\t}\n\tif (channel_manager_init(CHANNEL_MGR_DEFAULT_HV_PATH) < 0) {\n\t\tprintf(\"Unable to initialize channel manager\\n\");\n\t\treturn -1;\n\t}\n\trun_cli(NULL);\n\n\trte_eal_mp_wait_lcore();\n\treturn 0;\n}\n" }, { "path": "examples/vm_power_manager/power_manager.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \n#include \n#include \n#include \n\n#include \"power_manager.h\"\n\n#define RTE_LOGTYPE_POWER_MANAGER RTE_LOGTYPE_USER1\n\n#define POWER_SCALE_CORE(DIRECTION, core_num , ret) do { \\\n\tif (core_num >= POWER_MGR_MAX_CPUS) \\\n\t\treturn -1; \\\n\tif (!(global_enabled_cpus & (1ULL << core_num))) \\\n\t\treturn -1; \\\n\trte_spinlock_lock(&global_core_freq_info[core_num].power_sl); \\\n\tret = rte_power_freq_##DIRECTION(core_num); \\\n\trte_spinlock_unlock(&global_core_freq_info[core_num].power_sl); \\\n} while (0)\n\n#define POWER_SCALE_MASK(DIRECTION, core_mask, ret) do { \\\n\tint i; \\\n\tfor (i = 0; core_mask; core_mask &= ~(1 << i++)) { \\\n\t\tif ((core_mask >> i) & 1) { \\\n\t\t\tif (!(global_enabled_cpus & (1ULL << i))) \\\n\t\t\t\tcontinue; \\\n\t\t\trte_spinlock_lock(&global_core_freq_info[i].power_sl); \\\n\t\t\tif (rte_power_freq_##DIRECTION(i) != 1) \\\n\t\t\t\tret = -1; \\\n\t\t\trte_spinlock_unlock(&global_core_freq_info[i].power_sl); \\\n\t\t} \\\n\t} \\\n} while (0)\n\nstruct freq_info {\n\trte_spinlock_t power_sl;\n\tuint32_t freqs[RTE_MAX_LCORE_FREQS];\n\tunsigned num_freqs;\n} __rte_cache_aligned;\n\nstatic struct freq_info global_core_freq_info[POWER_MGR_MAX_CPUS];\n\nstatic uint64_t global_enabled_cpus;\n\n#define SYSFS_CPU_PATH \"/sys/devices/system/cpu/cpu%u/topology/core_id\"\n\nstatic unsigned\nset_host_cpus_mask(void)\n{\n\tchar path[PATH_MAX];\n\tunsigned i;\n\tunsigned num_cpus = 0;\n\n\tfor (i = 0; i < POWER_MGR_MAX_CPUS; i++) {\n\t\tsnprintf(path, sizeof(path), SYSFS_CPU_PATH, i);\n\t\tif (access(path, F_OK) == 0) {\n\t\t\tglobal_enabled_cpus |= 1ULL << i;\n\t\t\tnum_cpus++;\n\t\t} else\n\t\t\treturn num_cpus;\n\t}\n\treturn num_cpus;\n}\n\nint\npower_manager_init(void)\n{\n\tunsigned i, num_cpus;\n\tuint64_t cpu_mask;\n\tint ret = 0;\n\n\tnum_cpus = set_host_cpus_mask();\n\tif (num_cpus == 0) {\n\t\tRTE_LOG(ERR, POWER_MANAGER, \"Unable to detected host CPUs, please \"\n\t\t\t\"ensure that sufficient privileges exist to inspect sysfs\\n\");\n\t\treturn -1;\n\t}\n\trte_power_set_env(PM_ENV_ACPI_CPUFREQ);\n\tcpu_mask = global_enabled_cpus;\n\tfor (i = 0; cpu_mask; cpu_mask &= ~(1 << i++)) {\n\t\tif (rte_power_init(i) < 0 || rte_power_freqs(i,\n\t\t\t\tglobal_core_freq_info[i].freqs,\n\t\t\t\tRTE_MAX_LCORE_FREQS) == 0) {\n\t\t\tRTE_LOG(ERR, POWER_MANAGER, \"Unable to initialize power manager \"\n\t\t\t\t\t\"for core %u\\n\", i);\n\t\t\tglobal_enabled_cpus &= ~(1 << i);\n\t\t\tnum_cpus--;\n\t\t\tret = -1;\n\t\t}\n\t\trte_spinlock_init(&global_core_freq_info[i].power_sl);\n\t}\n\tRTE_LOG(INFO, POWER_MANAGER, \"Detected %u host CPUs , enabled core mask:\"\n\t\t\t\t\t\" 0x%\"PRIx64\"\\n\", num_cpus, global_enabled_cpus);\n\treturn ret;\n\n}\n\nuint32_t\npower_manager_get_current_frequency(unsigned core_num)\n{\n\tuint32_t freq, index;\n\n\tif (core_num >= POWER_MGR_MAX_CPUS) {\n\t\tRTE_LOG(ERR, POWER_MANAGER, \"Core(%u) is out of range 0...%d\\n\",\n\t\t\t\tcore_num, POWER_MGR_MAX_CPUS-1);\n\t\treturn -1;\n\t}\n\tif (!(global_enabled_cpus & (1ULL << core_num)))\n\t\treturn 0;\n\n\trte_spinlock_lock(&global_core_freq_info[core_num].power_sl);\n\tindex = rte_power_get_freq(core_num);\n\trte_spinlock_unlock(&global_core_freq_info[core_num].power_sl);\n\tif (index >= POWER_MGR_MAX_CPUS)\n\t\tfreq = 0;\n\telse\n\t\tfreq = global_core_freq_info[core_num].freqs[index];\n\n\treturn freq;\n}\n\nint\npower_manager_exit(void)\n{\n\tunsigned int i;\n\tint ret = 0;\n\n\tfor (i = 0; global_enabled_cpus; global_enabled_cpus &= ~(1 << i++)) {\n\t\tif (rte_power_exit(i) < 0) {\n\t\t\tRTE_LOG(ERR, POWER_MANAGER, \"Unable to shutdown power manager \"\n\t\t\t\t\t\"for core %u\\n\", i);\n\t\t\tret = -1;\n\t\t}\n\t}\n\tglobal_enabled_cpus = 0;\n\treturn ret;\n}\n\nint\npower_manager_scale_mask_up(uint64_t core_mask)\n{\n\tint ret = 0;\n\n\tPOWER_SCALE_MASK(up, core_mask, ret);\n\treturn ret;\n}\n\nint\npower_manager_scale_mask_down(uint64_t core_mask)\n{\n\tint ret = 0;\n\n\tPOWER_SCALE_MASK(down, core_mask, ret);\n\treturn ret;\n}\n\nint\npower_manager_scale_mask_min(uint64_t core_mask)\n{\n\tint ret = 0;\n\n\tPOWER_SCALE_MASK(min, core_mask, ret);\n\treturn ret;\n}\n\nint\npower_manager_scale_mask_max(uint64_t core_mask)\n{\n\tint ret = 0;\n\n\tPOWER_SCALE_MASK(max, core_mask, ret);\n\treturn ret;\n}\n\nint\npower_manager_scale_core_up(unsigned core_num)\n{\n\tint ret = 0;\n\n\tPOWER_SCALE_CORE(up, core_num, ret);\n\treturn ret;\n}\n\nint\npower_manager_scale_core_down(unsigned core_num)\n{\n\tint ret = 0;\n\n\tPOWER_SCALE_CORE(down, core_num, ret);\n\treturn ret;\n}\n\nint\npower_manager_scale_core_min(unsigned core_num)\n{\n\tint ret = 0;\n\n\tPOWER_SCALE_CORE(min, core_num, ret);\n\treturn ret;\n}\n\nint\npower_manager_scale_core_max(unsigned core_num)\n{\n\tint ret = 0;\n\n\tPOWER_SCALE_CORE(max, core_num, ret);\n\treturn ret;\n}\n" }, { "path": "examples/vm_power_manager/power_manager.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef POWER_MANAGER_H_\n#define POWER_MANAGER_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Maximum number of CPUS to manage */\n#define POWER_MGR_MAX_CPUS 64\n/**\n * Initialize power management.\n * Initializes resources and verifies the number of CPUs on the system.\n * Wraps librte_power int rte_power_init(unsigned lcore_id);\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint power_manager_init(void);\n\n/**\n * Exit power management. Must be called prior to exiting the application.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint power_manager_exit(void);\n\n/**\n * Scale up the frequency of the cores specified in core_mask.\n * It is thread-safe.\n *\n * @param core_mask\n * The uint64_t bit-mask of cores to change frequency.\n *\n * @return\n * - 1 on success.\n * - Negative on error.\n */\nint power_manager_scale_mask_up(uint64_t core_mask);\n\n/**\n * Scale down the frequency of the cores specified in core_mask.\n * It is thread-safe.\n *\n * @param core_mask\n * The uint64_t bit-mask of cores to change frequency.\n *\n * @return\n * - 1 on success.\n * - Negative on error.\n */\nint power_manager_scale_mask_down(uint64_t core_mask);\n\n/**\n * Scale to the minimum frequency of the cores specified in core_mask.\n * It is thread-safe.\n *\n * @param core_mask\n * The uint64_t bit-mask of cores to change frequency.\n *\n * @return\n * - 1 on success.\n * - Negative on error.\n */\nint power_manager_scale_mask_min(uint64_t core_mask);\n\n/**\n * Scale to the maximum frequency of the cores specified in core_mask.\n * It is thread-safe.\n *\n * @param core_mask\n * The uint64_t bit-mask of cores to change frequency.\n *\n * @return\n * - 1 on success.\n * - Negative on error.\n */\nint power_manager_scale_mask_max(uint64_t core_mask);\n\n/**\n * Scale up frequency for the core specified by core_num.\n * It is thread-safe.\n *\n * @param core_num\n * The core number to change frequency\n *\n * @return\n * - 1 on success.\n * - Negative on error.\n */\nint power_manager_scale_core_up(unsigned core_num);\n\n/**\n * Scale down frequency for the core specified by core_num.\n * It is thread-safe.\n *\n * @param core_num\n * The core number to change frequency\n *\n * @return\n * - 1 on success.\n * - 0 if frequency not changed.\n * - Negative on error.\n */\nint power_manager_scale_core_down(unsigned core_num);\n\n/**\n * Scale to minimum frequency for the core specified by core_num.\n * It is thread-safe.\n *\n * @param core_num\n * The core number to change frequency\n *\n * @return\n * - 1 on success.\n * - 0 if frequency not changed.\n * - Negative on error.\n */\nint power_manager_scale_core_min(unsigned core_num);\n\n/**\n * Scale to maximum frequency for the core specified by core_num.\n * It is thread-safe.\n *\n * @param core_num\n * The core number to change frequency\n *\n * @return\n * - 1 on success.\n * - 0 if frequency not changed.\n * - Negative on error.\n */\nint power_manager_scale_core_max(unsigned core_num);\n\n/**\n * Get the current freuency of the core specified by core_num\n *\n * @param core_num\n * The core number to get the current frequency\n *\n * @return\n * - 0 on error\n * - >0 for current frequency.\n */\nuint32_t power_manager_get_current_frequency(unsigned core_num);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* POWER_MANAGER_H_ */\n" }, { "path": "examples/vm_power_manager/vm_power_cli.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"vm_power_cli.h\"\n#include \"channel_manager.h\"\n#include \"channel_monitor.h\"\n#include \"power_manager.h\"\n#include \"channel_commands.h\"\n\nstruct cmd_quit_result {\n\tcmdline_fixed_string_t quit;\n};\n\nstatic void cmd_quit_parsed(__attribute__((unused)) void *parsed_result,\n\t\tstruct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tchannel_monitor_exit();\n\tchannel_manager_exit();\n\tpower_manager_exit();\n\tcmdline_quit(cl);\n}\n\ncmdline_parse_token_string_t cmd_quit_quit =\n\tTOKEN_STRING_INITIALIZER(struct cmd_quit_result, quit, \"quit\");\n\ncmdline_parse_inst_t cmd_quit = {\n\t.f = cmd_quit_parsed, /* function to call */\n\t.data = NULL, /* 2nd arg of func */\n\t.help_str = \"close the application\",\n\t.tokens = { /* token list, NULL terminated */\n\t\t(void *)&cmd_quit_quit,\n\t\tNULL,\n\t},\n};\n\n/* *** VM operations *** */\nstruct cmd_show_vm_result {\n\tcmdline_fixed_string_t show_vm;\n\tcmdline_fixed_string_t vm_name;\n};\n\nstatic void\ncmd_show_vm_parsed(void *parsed_result, struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_show_vm_result *res = parsed_result;\n\tstruct vm_info info;\n\tunsigned i;\n\n\tif (get_info_vm(res->vm_name, &info) != 0)\n\t\treturn;\n\tcmdline_printf(cl, \"VM: '%s', status = \", info.name);\n\tif (info.status == CHANNEL_MGR_VM_ACTIVE)\n\t\tcmdline_printf(cl, \"ACTIVE\\n\");\n\telse\n\t\tcmdline_printf(cl, \"INACTIVE\\n\");\n\tcmdline_printf(cl, \"Channels %u\\n\", info.num_channels);\n\tfor (i = 0; i < info.num_channels; i++) {\n\t\tcmdline_printf(cl, \" [%u]: %s, status = \", i,\n\t\t\t\tinfo.channels[i].channel_path);\n\t\tswitch (info.channels[i].status) {\n\t\tcase CHANNEL_MGR_CHANNEL_CONNECTED:\n\t\t\tcmdline_printf(cl, \"CONNECTED\\n\");\n\t\t\tbreak;\n\t\tcase CHANNEL_MGR_CHANNEL_DISCONNECTED:\n\t\t\tcmdline_printf(cl, \"DISCONNECTED\\n\");\n\t\t\tbreak;\n\t\tcase CHANNEL_MGR_CHANNEL_DISABLED:\n\t\t\tcmdline_printf(cl, \"DISABLED\\n\");\n\t\t\tbreak;\n\t\tcase CHANNEL_MGR_CHANNEL_PROCESSING:\n\t\t\tcmdline_printf(cl, \"PROCESSING\\n\");\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tcmdline_printf(cl, \"UNKNOWN\\n\");\n\t\t\tbreak;\n\t\t}\n\t}\n\tcmdline_printf(cl, \"Virtual CPU(s): %u\\n\", info.num_vcpus);\n\tfor (i = 0; i < info.num_vcpus; i++) {\n\t\tcmdline_printf(cl, \" [%u]: Physical CPU Mask 0x%\"PRIx64\"\\n\", i,\n\t\t\t\tinfo.pcpu_mask[i]);\n\t}\n}\n\n\n\ncmdline_parse_token_string_t cmd_vm_show =\n\tTOKEN_STRING_INITIALIZER(struct cmd_show_vm_result,\n\t\t\t\tshow_vm, \"show_vm\");\ncmdline_parse_token_string_t cmd_show_vm_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_show_vm_result,\n\t\t\tvm_name, NULL);\n\ncmdline_parse_inst_t cmd_show_vm_set = {\n\t.f = cmd_show_vm_parsed,\n\t.data = NULL,\n\t.help_str = \"show_vm , prints the information on the \"\n\t\t\t\"specified VM(s), the information lists the number of vCPUS, the \"\n\t\t\t\"pinning to pCPU(s) as a bit mask, along with any communication \"\n\t\t\t\"channels associated with each VM\",\n\t.tokens = {\n\t\t(void *)&cmd_vm_show,\n\t\t(void *)&cmd_show_vm_name,\n\t\tNULL,\n\t},\n};\n\n/* *** vCPU to pCPU mapping operations *** */\nstruct cmd_set_pcpu_mask_result {\n\tcmdline_fixed_string_t set_pcpu_mask;\n\tcmdline_fixed_string_t vm_name;\n\tuint8_t vcpu;\n\tuint64_t core_mask;\n};\n\nstatic void\ncmd_set_pcpu_mask_parsed(void *parsed_result, struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_pcpu_mask_result *res = parsed_result;\n\n\tif (set_pcpus_mask(res->vm_name, res->vcpu, res->core_mask) == 0)\n\t\tcmdline_printf(cl, \"Pinned vCPU(%\"PRId8\") to pCPU core \"\n\t\t\t\t\"mask(0x%\"PRIx64\")\\n\", res->vcpu, res->core_mask);\n\telse\n\t\tcmdline_printf(cl, \"Unable to pin vCPU(%\"PRId8\") to pCPU core \"\n\t\t\t\t\"mask(0x%\"PRIx64\")\\n\", res->vcpu, res->core_mask);\n}\n\ncmdline_parse_token_string_t cmd_set_pcpu_mask =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_set_pcpu_mask_result,\n\t\t\t\tset_pcpu_mask, \"set_pcpu_mask\");\ncmdline_parse_token_string_t cmd_set_pcpu_mask_vm_name =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_set_pcpu_mask_result,\n\t\t\t\tvm_name, NULL);\ncmdline_parse_token_num_t set_pcpu_mask_vcpu =\n\t\tTOKEN_NUM_INITIALIZER(struct cmd_set_pcpu_mask_result,\n\t\t\t\tvcpu, UINT8);\ncmdline_parse_token_num_t set_pcpu_mask_core_mask =\n\t\tTOKEN_NUM_INITIALIZER(struct cmd_set_pcpu_mask_result,\n\t\t\t\tcore_mask, UINT64);\n\n\ncmdline_parse_inst_t cmd_set_pcpu_mask_set = {\n\t\t.f = cmd_set_pcpu_mask_parsed,\n\t\t.data = NULL,\n\t\t.help_str = \"set_pcpu_mask , Set the binding \"\n\t\t\t\t\"of Virtual CPU on VM to the Physical CPU mask.\",\n\t\t\t\t.tokens = {\n\t\t\t\t\t\t(void *)&cmd_set_pcpu_mask,\n\t\t\t\t\t\t(void *)&cmd_set_pcpu_mask_vm_name,\n\t\t\t\t\t\t(void *)&set_pcpu_mask_vcpu,\n\t\t\t\t\t\t(void *)&set_pcpu_mask_core_mask,\n\t\t\t\t\t\tNULL,\n\t\t},\n};\n\nstruct cmd_set_pcpu_result {\n\tcmdline_fixed_string_t set_pcpu;\n\tcmdline_fixed_string_t vm_name;\n\tuint8_t vcpu;\n\tuint8_t core;\n};\n\nstatic void\ncmd_set_pcpu_parsed(void *parsed_result, struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_pcpu_result *res = parsed_result;\n\n\tif (set_pcpu(res->vm_name, res->vcpu, res->core) == 0)\n\t\tcmdline_printf(cl, \"Pinned vCPU(%\"PRId8\") to pCPU core \"\n\t\t\t\t\"%\"PRId8\")\\n\", res->vcpu, res->core);\n\telse\n\t\tcmdline_printf(cl, \"Unable to pin vCPU(%\"PRId8\") to pCPU core \"\n\t\t\t\t\"%\"PRId8\")\\n\", res->vcpu, res->core);\n}\n\ncmdline_parse_token_string_t cmd_set_pcpu =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_set_pcpu_result,\n\t\t\t\tset_pcpu, \"set_pcpu\");\ncmdline_parse_token_string_t cmd_set_pcpu_vm_name =\n\t\tTOKEN_STRING_INITIALIZER(struct cmd_set_pcpu_result,\n\t\t\t\tvm_name, NULL);\ncmdline_parse_token_num_t set_pcpu_vcpu =\n\t\tTOKEN_NUM_INITIALIZER(struct cmd_set_pcpu_result,\n\t\t\t\tvcpu, UINT8);\ncmdline_parse_token_num_t set_pcpu_core =\n\t\tTOKEN_NUM_INITIALIZER(struct cmd_set_pcpu_result,\n\t\t\t\tcore, UINT64);\n\n\ncmdline_parse_inst_t cmd_set_pcpu_set = {\n\t\t.f = cmd_set_pcpu_parsed,\n\t\t.data = NULL,\n\t\t.help_str = \"set_pcpu , Set the binding \"\n\t\t\t\t\"of Virtual CPU on VM to the Physical CPU.\",\n\t\t\t\t.tokens = {\n\t\t\t\t\t\t(void *)&cmd_set_pcpu,\n\t\t\t\t\t\t(void *)&cmd_set_pcpu_vm_name,\n\t\t\t\t\t\t(void *)&set_pcpu_vcpu,\n\t\t\t\t\t\t(void *)&set_pcpu_core,\n\t\t\t\t\t\tNULL,\n\t\t},\n};\n\nstruct cmd_vm_op_result {\n\tcmdline_fixed_string_t op_vm;\n\tcmdline_fixed_string_t vm_name;\n};\n\nstatic void\ncmd_vm_op_parsed(void *parsed_result, struct cmdline *cl,\n\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_vm_op_result *res = parsed_result;\n\n\tif (!strcmp(res->op_vm, \"add_vm\")) {\n\t\tif (add_vm(res->vm_name) < 0)\n\t\t\tcmdline_printf(cl, \"Unable to add VM '%s'\\n\", res->vm_name);\n\t} else if (remove_vm(res->vm_name) < 0)\n\t\tcmdline_printf(cl, \"Unable to remove VM '%s'\\n\", res->vm_name);\n}\n\ncmdline_parse_token_string_t cmd_vm_op =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vm_op_result,\n\t\t\top_vm, \"add_vm#rm_vm\");\ncmdline_parse_token_string_t cmd_vm_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_vm_op_result,\n\t\t\tvm_name, NULL);\n\ncmdline_parse_inst_t cmd_vm_op_set = {\n\t.f = cmd_vm_op_parsed,\n\t.data = NULL,\n\t.help_str = \"add_vm|rm_vm , add a VM for \"\n\t\t\t\"subsequent operations with the CLI or remove a previously added \"\n\t\t\t\"VM from the VM Power Manager\",\n\t.tokens = {\n\t\t(void *)&cmd_vm_op,\n\t\t(void *)&cmd_vm_name,\n\tNULL,\n\t},\n};\n\n/* *** VM channel operations *** */\nstruct cmd_channels_op_result {\n\tcmdline_fixed_string_t op;\n\tcmdline_fixed_string_t vm_name;\n\tcmdline_fixed_string_t channel_list;\n};\nstatic void\ncmd_channels_op_parsed(void *parsed_result, struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tunsigned num_channels = 0, channel_num, i;\n\tint channels_added;\n\tunsigned channel_list[CHANNEL_CMDS_MAX_VM_CHANNELS];\n\tchar *token, *remaining, *tail_ptr;\n\tstruct cmd_channels_op_result *res = parsed_result;\n\n\tif (!strcmp(res->channel_list, \"all\")) {\n\t\tchannels_added = add_all_channels(res->vm_name);\n\t\tcmdline_printf(cl, \"Added %d channels for VM '%s'\\n\",\n\t\t\t\tchannels_added, res->vm_name);\n\t\treturn;\n\t}\n\n\tremaining = res->channel_list;\n\twhile (1) {\n\t\tif (remaining == NULL || remaining[0] == '\\0')\n\t\t\tbreak;\n\n\t\ttoken = strsep(&remaining, \",\");\n\t\tif (token == NULL)\n\t\t\tbreak;\n\t\terrno = 0;\n\t\tchannel_num = (unsigned)strtol(token, &tail_ptr, 10);\n\t\tif ((errno != 0) || tail_ptr == NULL || (*tail_ptr != '\\0'))\n\t\t\tbreak;\n\n\t\tif (channel_num == CHANNEL_CMDS_MAX_VM_CHANNELS) {\n\t\t\tcmdline_printf(cl, \"Channel number '%u' exceeds the maximum number \"\n\t\t\t\t\t\"of allowable channels(%u) for VM '%s'\\n\", channel_num,\n\t\t\t\t\tCHANNEL_CMDS_MAX_VM_CHANNELS, res->vm_name);\n\t\t\treturn;\n\t\t}\n\t\tchannel_list[num_channels++] = channel_num;\n\t}\n\tfor (i = 0; i < num_channels; i++)\n\t\tcmdline_printf(cl, \"[%u]: Adding channel %u\\n\", i, channel_list[i]);\n\n\tchannels_added = add_channels(res->vm_name, channel_list,\n\t\t\tnum_channels);\n\tcmdline_printf(cl, \"Enabled %d channels for '%s'\\n\", channels_added,\n\t\t\tres->vm_name);\n}\n\ncmdline_parse_token_string_t cmd_channels_op =\n\tTOKEN_STRING_INITIALIZER(struct cmd_channels_op_result,\n\t\t\t\top, \"add_channels\");\ncmdline_parse_token_string_t cmd_channels_vm_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_channels_op_result,\n\t\t\tvm_name, NULL);\ncmdline_parse_token_string_t cmd_channels_list =\n\tTOKEN_STRING_INITIALIZER(struct cmd_channels_op_result,\n\t\t\tchannel_list, NULL);\n\ncmdline_parse_inst_t cmd_channels_op_set = {\n\t.f = cmd_channels_op_parsed,\n\t.data = NULL,\n\t.help_str = \"add_channels |all, add \"\n\t\t\t\"communication channels for the specified VM, the \"\n\t\t\t\"virtio channels must be enabled in the VM \"\n\t\t\t\"configuration(qemu/libvirt) and the associated VM must be active. \"\n\t\t\t\" is a comma-separated list of channel numbers to add, using \"\n\t\t\t\"the keyword 'all' will attempt to add all channels for the VM\",\n\t.tokens = {\n\t\t(void *)&cmd_channels_op,\n\t\t(void *)&cmd_channels_vm_name,\n\t\t(void *)&cmd_channels_list,\n\t\tNULL,\n\t},\n};\n\nstruct cmd_channels_status_op_result {\n\tcmdline_fixed_string_t op;\n\tcmdline_fixed_string_t vm_name;\n\tcmdline_fixed_string_t channel_list;\n\tcmdline_fixed_string_t status;\n};\n\nstatic void\ncmd_channels_status_op_parsed(void *parsed_result, struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tunsigned num_channels = 0, channel_num;\n\tint changed;\n\tunsigned channel_list[CHANNEL_CMDS_MAX_VM_CHANNELS];\n\tchar *token, *remaining, *tail_ptr;\n\tstruct cmd_channels_status_op_result *res = parsed_result;\n\tenum channel_status status;\n\n\tif (!strcmp(res->status, \"enabled\"))\n\t\tstatus = CHANNEL_MGR_CHANNEL_CONNECTED;\n\telse\n\t\tstatus = CHANNEL_MGR_CHANNEL_DISABLED;\n\n\tif (!strcmp(res->channel_list, \"all\")) {\n\t\tchanged = set_channel_status_all(res->vm_name, status);\n\t\tcmdline_printf(cl, \"Updated status of %d channels \"\n\t\t\t\t\"for VM '%s'\\n\", changed, res->vm_name);\n\t\treturn;\n\t}\n\tremaining = res->channel_list;\n\twhile (1) {\n\t\tif (remaining == NULL || remaining[0] == '\\0')\n\t\t\tbreak;\n\t\ttoken = strsep(&remaining, \",\");\n\t\tif (token == NULL)\n\t\t\tbreak;\n\t\terrno = 0;\n\t\tchannel_num = (unsigned)strtol(token, &tail_ptr, 10);\n\t\tif ((errno != 0) || tail_ptr == NULL || (*tail_ptr != '\\0'))\n\t\t\tbreak;\n\n\t\tif (channel_num == CHANNEL_CMDS_MAX_VM_CHANNELS) {\n\t\t\tcmdline_printf(cl, \"%u exceeds the maximum number of allowable \"\n\t\t\t\t\t\"channels(%u) for VM '%s'\\n\", channel_num,\n\t\t\t\t\tCHANNEL_CMDS_MAX_VM_CHANNELS, res->vm_name);\n\t\t\treturn;\n\t\t}\n\t\tchannel_list[num_channels++] = channel_num;\n\t}\n\tchanged = set_channel_status(res->vm_name, channel_list, num_channels,\n\t\t\tstatus);\n\tcmdline_printf(cl, \"Updated status of %d channels \"\n\t\t\t\t\t\"for VM '%s'\\n\", changed, res->vm_name);\n}\n\ncmdline_parse_token_string_t cmd_channels_status_op =\n\tTOKEN_STRING_INITIALIZER(struct cmd_channels_status_op_result,\n\t\t\t\top, \"set_channel_status\");\ncmdline_parse_token_string_t cmd_channels_status_vm_name =\n\tTOKEN_STRING_INITIALIZER(struct cmd_channels_status_op_result,\n\t\t\tvm_name, NULL);\ncmdline_parse_token_string_t cmd_channels_status_list =\n\tTOKEN_STRING_INITIALIZER(struct cmd_channels_status_op_result,\n\t\t\tchannel_list, NULL);\ncmdline_parse_token_string_t cmd_channels_status =\n\tTOKEN_STRING_INITIALIZER(struct cmd_channels_status_op_result,\n\t\t\tstatus, \"enabled#disabled\");\n\ncmdline_parse_inst_t cmd_channels_status_op_set = {\n\t.f = cmd_channels_status_op_parsed,\n\t.data = NULL,\n\t.help_str = \"set_channel_status |all enabled|disabled, \"\n\t\t\t\" enable or disable the communication channels in \"\n\t\t\t\"list(comma-separated) for the specified VM, alternatively \"\n\t\t\t\"list can be replaced with keyword 'all'. \"\n\t\t\t\"Disabled channels will still receive packets on the host, \"\n\t\t\t\"however the commands they specify will be ignored. \"\n\t\t\t\"Set status to 'enabled' to begin processing requests again.\",\n\t.tokens = {\n\t\t(void *)&cmd_channels_status_op,\n\t\t(void *)&cmd_channels_status_vm_name,\n\t\t(void *)&cmd_channels_status_list,\n\t\t(void *)&cmd_channels_status,\n\t\tNULL,\n\t},\n};\n\n/* *** CPU Frequency operations *** */\nstruct cmd_show_cpu_freq_mask_result {\n\tcmdline_fixed_string_t show_cpu_freq_mask;\n\tuint64_t core_mask;\n};\n\nstatic void\ncmd_show_cpu_freq_mask_parsed(void *parsed_result, struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_show_cpu_freq_mask_result *res = parsed_result;\n\tunsigned i;\n\tuint64_t mask = res->core_mask;\n\tuint32_t freq;\n\n\tfor (i = 0; mask; mask &= ~(1ULL << i++)) {\n\t\tif ((mask >> i) & 1) {\n\t\t\tfreq = power_manager_get_current_frequency(i);\n\t\t\tif (freq > 0)\n\t\t\t\tcmdline_printf(cl, \"Core %u: %\"PRId32\"\\n\", i, freq);\n\t\t}\n\t}\n}\n\ncmdline_parse_token_string_t cmd_show_cpu_freq_mask =\n\tTOKEN_STRING_INITIALIZER(struct cmd_show_cpu_freq_mask_result,\n\t\t\tshow_cpu_freq_mask, \"show_cpu_freq_mask\");\ncmdline_parse_token_num_t cmd_show_cpu_freq_mask_core_mask =\n\tTOKEN_NUM_INITIALIZER(struct cmd_show_cpu_freq_mask_result,\n\t\t\tcore_mask, UINT64);\n\ncmdline_parse_inst_t cmd_show_cpu_freq_mask_set = {\n\t.f = cmd_show_cpu_freq_mask_parsed,\n\t.data = NULL,\n\t.help_str = \"show_cpu_freq_mask , Get the current frequency for each \"\n\t\t\t\"core specified in the mask\",\n\t.tokens = {\n\t\t(void *)&cmd_show_cpu_freq_mask,\n\t\t(void *)&cmd_show_cpu_freq_mask_core_mask,\n\t\tNULL,\n\t},\n};\n\nstruct cmd_set_cpu_freq_mask_result {\n\tcmdline_fixed_string_t set_cpu_freq_mask;\n\tuint64_t core_mask;\n\tcmdline_fixed_string_t cmd;\n};\n\nstatic void\ncmd_set_cpu_freq_mask_parsed(void *parsed_result, struct cmdline *cl,\n\t\t\t__attribute__((unused)) void *data)\n{\n\tstruct cmd_set_cpu_freq_mask_result *res = parsed_result;\n\tint ret = -1;\n\n\tif (!strcmp(res->cmd , \"up\"))\n\t\tret = power_manager_scale_mask_up(res->core_mask);\n\telse if (!strcmp(res->cmd , \"down\"))\n\t\tret = power_manager_scale_mask_down(res->core_mask);\n\telse if (!strcmp(res->cmd , \"min\"))\n\t\tret = power_manager_scale_mask_min(res->core_mask);\n\telse if (!strcmp(res->cmd , \"max\"))\n\t\tret = power_manager_scale_mask_max(res->core_mask);\n\tif (ret < 0) {\n\t\tcmdline_printf(cl, \"Error scaling core_mask(0x%\"PRIx64\") '%s' , not \"\n\t\t\t\t\"all cores specified have been scaled\\n\",\n\t\t\t\tres->core_mask, res->cmd);\n\t};\n}\n\ncmdline_parse_token_string_t cmd_set_cpu_freq_mask =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_cpu_freq_mask_result,\n\t\t\tset_cpu_freq_mask, \"set_cpu_freq_mask\");\ncmdline_parse_token_num_t cmd_set_cpu_freq_mask_core_mask =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_cpu_freq_mask_result,\n\t\t\tcore_mask, UINT64);\ncmdline_parse_token_string_t cmd_set_cpu_freq_mask_result =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_cpu_freq_mask_result,\n\t\t\tcmd, \"up#down#min#max\");\n\ncmdline_parse_inst_t cmd_set_cpu_freq_mask_set = {\n\t.f = cmd_set_cpu_freq_mask_parsed,\n\t.data = NULL,\n\t.help_str = \"set_cpu_freq , Set the current \"\n\t\t\t\"frequency for the cores specified in by scaling \"\n\t\t\t\"each up/down/min/max.\",\n\t.tokens = {\n\t\t(void *)&cmd_set_cpu_freq_mask,\n\t\t(void *)&cmd_set_cpu_freq_mask_core_mask,\n\t\t(void *)&cmd_set_cpu_freq_mask_result,\n\t\tNULL,\n\t},\n};\n\n\n\nstruct cmd_show_cpu_freq_result {\n\tcmdline_fixed_string_t show_cpu_freq;\n\tuint8_t core_num;\n};\n\nstatic void\ncmd_show_cpu_freq_parsed(void *parsed_result, struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tstruct cmd_show_cpu_freq_result *res = parsed_result;\n\tuint32_t curr_freq = power_manager_get_current_frequency(res->core_num);\n\n\tif (curr_freq == 0) {\n\t\tcmdline_printf(cl, \"Unable to get frequency for core %u\\n\",\n\t\t\t\tres->core_num);\n\t\treturn;\n\t}\n\tcmdline_printf(cl, \"Core %u frequency: %\"PRId32\"\\n\", res->core_num,\n\t\t\tcurr_freq);\n}\n\ncmdline_parse_token_string_t cmd_show_cpu_freq =\n\tTOKEN_STRING_INITIALIZER(struct cmd_show_cpu_freq_result,\n\t\t\tshow_cpu_freq, \"show_cpu_freq\");\n\ncmdline_parse_token_num_t cmd_show_cpu_freq_core_num =\n\tTOKEN_NUM_INITIALIZER(struct cmd_show_cpu_freq_result,\n\t\t\tcore_num, UINT8);\n\ncmdline_parse_inst_t cmd_show_cpu_freq_set = {\n\t.f = cmd_show_cpu_freq_parsed,\n\t.data = NULL,\n\t.help_str = \"Get the current frequency for the specified core\",\n\t.tokens = {\n\t\t(void *)&cmd_show_cpu_freq,\n\t\t(void *)&cmd_show_cpu_freq_core_num,\n\t\tNULL,\n\t},\n};\n\nstruct cmd_set_cpu_freq_result {\n\tcmdline_fixed_string_t set_cpu_freq;\n\tuint8_t core_num;\n\tcmdline_fixed_string_t cmd;\n};\n\nstatic void\ncmd_set_cpu_freq_parsed(void *parsed_result, struct cmdline *cl,\n\t\t __attribute__((unused)) void *data)\n{\n\tint ret = -1;\n\tstruct cmd_set_cpu_freq_result *res = parsed_result;\n\n\tif (!strcmp(res->cmd , \"up\"))\n\t\tret = power_manager_scale_core_up(res->core_num);\n\telse if (!strcmp(res->cmd , \"down\"))\n\t\tret = power_manager_scale_core_down(res->core_num);\n\telse if (!strcmp(res->cmd , \"min\"))\n\t\tret = power_manager_scale_core_min(res->core_num);\n\telse if (!strcmp(res->cmd , \"max\"))\n\t\tret = power_manager_scale_core_max(res->core_num);\n\tif (ret < 0) {\n\t\tcmdline_printf(cl, \"Error scaling core(%u) '%s'\\n\", res->core_num,\n\t\t\t\tres->cmd);\n\t}\n}\n\ncmdline_parse_token_string_t cmd_set_cpu_freq =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_cpu_freq_result,\n\t\t\tset_cpu_freq, \"set_cpu_freq\");\ncmdline_parse_token_num_t cmd_set_cpu_freq_core_num =\n\tTOKEN_NUM_INITIALIZER(struct cmd_set_cpu_freq_result,\n\t\t\tcore_num, UINT8);\ncmdline_parse_token_string_t cmd_set_cpu_freq_cmd_cmd =\n\tTOKEN_STRING_INITIALIZER(struct cmd_set_cpu_freq_result,\n\t\t\tcmd, \"up#down#min#max\");\n\ncmdline_parse_inst_t cmd_set_cpu_freq_set = {\n\t.f = cmd_set_cpu_freq_parsed,\n\t.data = NULL,\n\t.help_str = \"set_cpu_freq , Set the current \"\n\t\t\t\"frequency for the specified core by scaling up/down/min/max\",\n\t.tokens = {\n\t\t(void *)&cmd_set_cpu_freq,\n\t\t(void *)&cmd_set_cpu_freq_core_num,\n\t\t(void *)&cmd_set_cpu_freq_cmd_cmd,\n\t\tNULL,\n\t},\n};\n\ncmdline_parse_ctx_t main_ctx[] = {\n\t\t(cmdline_parse_inst_t *)&cmd_quit,\n\t\t(cmdline_parse_inst_t *)&cmd_vm_op_set,\n\t\t(cmdline_parse_inst_t *)&cmd_channels_op_set,\n\t\t(cmdline_parse_inst_t *)&cmd_channels_status_op_set,\n\t\t(cmdline_parse_inst_t *)&cmd_show_vm_set,\n\t\t(cmdline_parse_inst_t *)&cmd_show_cpu_freq_mask_set,\n\t\t(cmdline_parse_inst_t *)&cmd_set_cpu_freq_mask_set,\n\t\t(cmdline_parse_inst_t *)&cmd_show_cpu_freq_set,\n\t\t(cmdline_parse_inst_t *)&cmd_set_cpu_freq_set,\n\t\t(cmdline_parse_inst_t *)&cmd_set_pcpu_mask_set,\n\t\t(cmdline_parse_inst_t *)&cmd_set_pcpu_set,\n\t\tNULL,\n};\n\nvoid\nrun_cli(__attribute__((unused)) void *arg)\n{\n\tstruct cmdline *cl;\n\n\tcl = cmdline_stdin_new(main_ctx, \"vmpower> \");\n\tif (cl == NULL)\n\t\treturn;\n\n\tcmdline_interact(cl);\n\tcmdline_stdin_exit(cl);\n}\n" }, { "path": "examples/vm_power_manager/vm_power_cli.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef VM_POWER_CLI_H_\n#define VM_POWER_CLI_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nvoid run_cli(__attribute__((unused)) void *arg);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* VM_POWER_CLI_H_ */\n" }, { "path": "examples/vmdq/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = vmdq_app\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += $(WERROR_FLAGS)\n\nEXTRA_CFLAGS += -O3\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/vmdq/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define MAX_QUEUES 128\n/*\n * For 10 GbE, 128 queues require roughly\n * 128*512 (RX/TX_queue_nb * RX/TX_ring_descriptors_nb) per port.\n */\n#define NUM_MBUFS_PER_PORT (128*512)\n#define MBUF_CACHE_SIZE 64\n\n#define MAX_PKT_BURST 32\n\n/*\n * Configurable number of RX/TX ring descriptors\n */\n#define RTE_TEST_RX_DESC_DEFAULT 128\n#define RTE_TEST_TX_DESC_DEFAULT 512\n\n#define INVALID_PORT_ID 0xFF\n\n/* mask of enabled ports */\nstatic uint32_t enabled_port_mask;\n\n/* number of pools (if user does not specify any, 8 by default */\nstatic uint32_t num_queues = 8;\nstatic uint32_t num_pools = 8;\n\n/* empty vmdq configuration structure. Filled in programatically */\nstatic const struct rte_eth_conf vmdq_conf_default = {\n\t.rxmode = {\n\t\t.mq_mode = ETH_MQ_RX_VMDQ_ONLY,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t},\n\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n\t.rx_adv_conf = {\n\t\t/*\n\t\t * should be overridden separately in code with\n\t\t * appropriate values\n\t\t */\n\t\t.vmdq_rx_conf = {\n\t\t\t.nb_queue_pools = ETH_8_POOLS,\n\t\t\t.enable_default_pool = 0,\n\t\t\t.default_pool = 0,\n\t\t\t.nb_pool_maps = 0,\n\t\t\t.pool_map = {{0, 0},},\n\t\t},\n\t},\n};\n\nstatic unsigned lcore_ids[RTE_MAX_LCORE];\nstatic uint8_t ports[RTE_MAX_ETHPORTS];\nstatic unsigned num_ports; /**< The number of ports specified in command line */\n\n/* array used for printing out statistics */\nvolatile unsigned long rxPackets[MAX_QUEUES] = {0};\n\nconst uint16_t vlan_tags[] = {\n\t0, 1, 2, 3, 4, 5, 6, 7,\n\t8, 9, 10, 11,\t12, 13, 14, 15,\n\t16, 17, 18, 19, 20, 21, 22, 23,\n\t24, 25, 26, 27, 28, 29, 30, 31,\n\t32, 33, 34, 35, 36, 37, 38, 39,\n\t40, 41, 42, 43, 44, 45, 46, 47,\n\t48, 49, 50, 51, 52, 53, 54, 55,\n\t56, 57, 58, 59, 60, 61, 62, 63,\n};\nconst uint16_t num_vlans = RTE_DIM(vlan_tags);\nstatic uint16_t num_pf_queues, num_vmdq_queues;\nstatic uint16_t vmdq_pool_base, vmdq_queue_base;\n/* pool mac addr template, pool mac addr is like: 52 54 00 12 port# pool# */\nstatic struct ether_addr pool_addr_template = {\n\t.addr_bytes = {0x52, 0x54, 0x00, 0x12, 0x00, 0x00}\n};\n\n/* ethernet addresses of ports */\nstatic struct ether_addr vmdq_ports_eth_addr[RTE_MAX_ETHPORTS];\n\n#define MAX_QUEUE_NUM_10G 128\n#define MAX_QUEUE_NUM_1G 8\n#define MAX_POOL_MAP_NUM_10G 64\n#define MAX_POOL_MAP_NUM_1G 32\n#define MAX_POOL_NUM_10G 64\n#define MAX_POOL_NUM_1G 8\n/*\n * Builds up the correct configuration for vmdq based on the vlan tags array\n * given above, and determine the queue number and pool map number according to\n * valid pool number\n */\nstatic inline int\nget_eth_conf(struct rte_eth_conf *eth_conf, uint32_t num_pools)\n{\n\tstruct rte_eth_vmdq_rx_conf conf;\n\tunsigned i;\n\n\tconf.nb_queue_pools = (enum rte_eth_nb_pools)num_pools;\n\tconf.nb_pool_maps = num_pools;\n\tconf.enable_default_pool = 0;\n\tconf.default_pool = 0; /* set explicit value, even if not used */\n\n\tfor (i = 0; i < conf.nb_pool_maps; i++) {\n\t\tconf.pool_map[i].vlan_id = vlan_tags[i];\n\t\tconf.pool_map[i].pools = (1UL << (i % num_pools));\n\t}\n\n\t(void)(rte_memcpy(eth_conf, &vmdq_conf_default, sizeof(*eth_conf)));\n\t(void)(rte_memcpy(ð_conf->rx_adv_conf.vmdq_rx_conf, &conf,\n\t\t sizeof(eth_conf->rx_adv_conf.vmdq_rx_conf)));\n\treturn 0;\n}\n\n/*\n * Initialises a given port using global settings and with the rx buffers\n * coming from the mbuf_pool passed as parameter\n */\nstatic inline int\nport_init(uint8_t port, struct rte_mempool *mbuf_pool)\n{\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_rxconf *rxconf;\n\tstruct rte_eth_conf port_conf;\n\tuint16_t rxRings, txRings;\n\tconst uint16_t rxRingSize = RTE_TEST_RX_DESC_DEFAULT, txRingSize = RTE_TEST_TX_DESC_DEFAULT;\n\tint retval;\n\tuint16_t q;\n\tuint16_t queues_per_pool;\n\tuint32_t max_nb_pools;\n\n\t/*\n\t * The max pool number from dev_info will be used to validate the pool\n\t * number specified in cmd line\n\t */\n\trte_eth_dev_info_get(port, &dev_info);\n\tmax_nb_pools = (uint32_t)dev_info.max_vmdq_pools;\n\t/*\n\t * We allow to process part of VMDQ pools specified by num_pools in\n\t * command line.\n\t */\n\tif (num_pools > max_nb_pools) {\n\t\tprintf(\"num_pools %d >max_nb_pools %d\\n\",\n\t\t\tnum_pools, max_nb_pools);\n\t\treturn -1;\n\t}\n\tretval = get_eth_conf(&port_conf, max_nb_pools);\n\tif (retval < 0)\n\t\treturn retval;\n\n\t/*\n\t * NIC queues are divided into pf queues and vmdq queues.\n\t */\n\t/* There is assumption here all ports have the same configuration! */\n\tnum_pf_queues = dev_info.max_rx_queues - dev_info.vmdq_queue_num;\n\tqueues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;\n\tnum_vmdq_queues = num_pools * queues_per_pool;\n\tnum_queues = num_pf_queues + num_vmdq_queues;\n\tvmdq_queue_base = dev_info.vmdq_queue_base;\n\tvmdq_pool_base = dev_info.vmdq_pool_base;\n\n\tprintf(\"pf queue num: %u, configured vmdq pool num: %u,\"\n\t\t\" each vmdq pool has %u queues\\n\",\n\t\tnum_pf_queues, num_pools, queues_per_pool);\n\tprintf(\"vmdq queue base: %d pool base %d\\n\",\n\t\tvmdq_queue_base, vmdq_pool_base);\n\tif (port >= rte_eth_dev_count())\n\t\treturn -1;\n\n\t/*\n\t * Though in this example, we only receive packets from the first queue\n\t * of each pool and send packets through first rte_lcore_count() tx\n\t * queues of vmdq queues, all queues including pf queues are setup.\n\t * This is because VMDQ queues doesn't always start from zero, and the\n\t * PMD layer doesn't support selectively initialising part of rx/tx\n\t * queues.\n\t */\n\trxRings = (uint16_t)dev_info.max_rx_queues;\n\ttxRings = (uint16_t)dev_info.max_tx_queues;\n\tretval = rte_eth_dev_configure(port, rxRings, txRings, &port_conf);\n\tif (retval != 0)\n\t\treturn retval;\n\n\trte_eth_dev_info_get(port, &dev_info);\n\trxconf = &dev_info.default_rxconf;\n\trxconf->rx_drop_en = 1;\n\tfor (q = 0; q < rxRings; q++) {\n\t\tretval = rte_eth_rx_queue_setup(port, q, rxRingSize,\n\t\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\t\trxconf,\n\t\t\t\t\tmbuf_pool);\n\t\tif (retval < 0) {\n\t\t\tprintf(\"initialise rx queue %d failed\\n\", q);\n\t\t\treturn retval;\n\t\t}\n\t}\n\n\tfor (q = 0; q < txRings; q++) {\n\t\tretval = rte_eth_tx_queue_setup(port, q, txRingSize,\n\t\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\t\tNULL);\n\t\tif (retval < 0) {\n\t\t\tprintf(\"initialise tx queue %d failed\\n\", q);\n\t\t\treturn retval;\n\t\t}\n\t}\n\n\tretval = rte_eth_dev_start(port);\n\tif (retval < 0) {\n\t\tprintf(\"port %d start failed\\n\", port);\n\t\treturn retval;\n\t}\n\n\trte_eth_macaddr_get(port, &vmdq_ports_eth_addr[port]);\n\tprintf(\"Port %u MAC: %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\n\t\t\t\" %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\"\\n\",\n\t\t\t(unsigned)port,\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[0],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[1],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[2],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[3],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[4],\n\t\t\tvmdq_ports_eth_addr[port].addr_bytes[5]);\n\n\t/*\n\t * Set mac for each pool.\n\t * There is no default mac for the pools in i40.\n\t * Removes this after i40e fixes this issue.\n\t */\n\tfor (q = 0; q < num_pools; q++) {\n\t\tstruct ether_addr mac;\n\t\tmac = pool_addr_template;\n\t\tmac.addr_bytes[4] = port;\n\t\tmac.addr_bytes[5] = q;\n\t\tprintf(\"Port %u vmdq pool %u set mac %02x:%02x:%02x:%02x:%02x:%02x\\n\",\n\t\t\tport, q,\n\t\t\tmac.addr_bytes[0], mac.addr_bytes[1],\n\t\t\tmac.addr_bytes[2], mac.addr_bytes[3],\n\t\t\tmac.addr_bytes[4], mac.addr_bytes[5]);\n\t\tretval = rte_eth_dev_mac_addr_add(port, &mac,\n\t\t\t\tq + vmdq_pool_base);\n\t\tif (retval) {\n\t\t\tprintf(\"mac addr add failed at pool %d\\n\", q);\n\t\t\treturn retval;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/* Check num_pools parameter and set it if OK*/\nstatic int\nvmdq_parse_num_pools(const char *q_arg)\n{\n\tchar *end = NULL;\n\tint n;\n\n\t/* parse number string */\n\tn = strtol(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (num_pools > num_vlans) {\n\t\tprintf(\"num_pools %d > num_vlans %d\\n\", num_pools, num_vlans);\n\t\treturn -1;\n\t}\n\n\tnum_pools = n;\n\n\treturn 0;\n}\n\n\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\n/* Display usage */\nstatic void\nvmdq_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK]\\n\"\n\t\" --nb-pools NP: number of pools\\n\",\n\t prgname);\n}\n\n/* Parse the argument (num_pools) given in the command line of the application */\nstatic int\nvmdq_parse_args(int argc, char **argv)\n{\n\tint opt;\n\tint option_index;\n\tunsigned i;\n\tconst char *prgname = argv[0];\n\tstatic struct option long_option[] = {\n\t\t{\"nb-pools\", required_argument, NULL, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\t/* Parse command line */\n\twhile ((opt = getopt_long(argc, argv, \"p:\", long_option,\n\t\t&option_index)) != EOF) {\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tvmdq_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 0:\n\t\t\tif (vmdq_parse_num_pools(optarg) == -1) {\n\t\t\t\tprintf(\"invalid number of pools\\n\");\n\t\t\t\tvmdq_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tvmdq_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif (enabled_port_mask & (1 << i))\n\t\t\tports[num_ports++] = (uint8_t)i;\n\t}\n\n\tif (num_ports < 2 || num_ports % 2) {\n\t\tprintf(\"Current enabled port number is %u,\"\n\t\t\t\"but it should be even and at least 2\\n\", num_ports);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic void\nupdate_mac_address(struct rte_mbuf *m, unsigned dst_port)\n{\n\tstruct ether_hdr *eth;\n\tvoid *tmp;\n\n\teth = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\t/* 02:00:00:00:00:xx */\n\ttmp = ð->d_addr.addr_bytes[0];\n\t*((uint64_t *)tmp) = 0x000000000002 + ((uint64_t)dst_port << 40);\n\n\t/* src addr */\n\tether_addr_copy(&vmdq_ports_eth_addr[dst_port], ð->s_addr);\n}\n\n/* When we receive a HUP signal, print out our stats */\nstatic void\nsighup_handler(int signum)\n{\n\tunsigned q;\n\tfor (q = 0; q < num_queues; q++) {\n\t\tif (q % (num_queues/num_pools) == 0)\n\t\t\tprintf(\"\\nPool %u: \", q/(num_queues/num_pools));\n\t\tprintf(\"%lu \", rxPackets[q]);\n\t}\n\tprintf(\"\\nFinished handling signal %d\\n\", signum);\n}\n\n/*\n * Main thread that does the work, reading from INPUT_PORT\n * and writing to OUTPUT_PORT\n */\nstatic int\nlcore_main(__attribute__((__unused__)) void *dummy)\n{\n\tconst uint16_t lcore_id = (uint16_t)rte_lcore_id();\n\tconst uint16_t num_cores = (uint16_t)rte_lcore_count();\n\tuint16_t core_id = 0;\n\tuint16_t startQueue, endQueue;\n\tuint16_t q, i, p;\n\tconst uint16_t remainder = (uint16_t)(num_vmdq_queues % num_cores);\n\n\tfor (i = 0; i < num_cores; i++)\n\t\tif (lcore_ids[i] == lcore_id) {\n\t\t\tcore_id = i;\n\t\t\tbreak;\n\t\t}\n\n\tif (remainder != 0) {\n\t\tif (core_id < remainder) {\n\t\t\tstartQueue = (uint16_t)(core_id *\n\t\t\t\t\t(num_vmdq_queues / num_cores + 1));\n\t\t\tendQueue = (uint16_t)(startQueue +\n\t\t\t\t\t(num_vmdq_queues / num_cores) + 1);\n\t\t} else {\n\t\t\tstartQueue = (uint16_t)(core_id *\n\t\t\t\t\t(num_vmdq_queues / num_cores) +\n\t\t\t\t\tremainder);\n\t\t\tendQueue = (uint16_t)(startQueue +\n\t\t\t\t\t(num_vmdq_queues / num_cores));\n\t\t}\n\t} else {\n\t\tstartQueue = (uint16_t)(core_id *\n\t\t\t\t(num_vmdq_queues / num_cores));\n\t\tendQueue = (uint16_t)(startQueue +\n\t\t\t\t(num_vmdq_queues / num_cores));\n\t}\n\n\t/* vmdq queue idx doesn't always start from zero.*/\n\tstartQueue += vmdq_queue_base;\n\tendQueue += vmdq_queue_base;\n\tprintf(\"core %u(lcore %u) reading queues %i-%i\\n\", (unsigned)core_id,\n\t\t(unsigned)lcore_id, startQueue, endQueue - 1);\n\n\tif (startQueue == endQueue) {\n\t\tprintf(\"lcore %u has nothing to do\\n\", lcore_id);\n\t\treturn 0;\n\t}\n\n\tfor (;;) {\n\t\tstruct rte_mbuf *buf[MAX_PKT_BURST];\n\t\tconst uint16_t buf_size = sizeof(buf) / sizeof(buf[0]);\n\n\t\tfor (p = 0; p < num_ports; p++) {\n\t\t\tconst uint8_t sport = ports[p];\n\t\t\t/* 0 <-> 1, 2 <-> 3 etc */\n\t\t\tconst uint8_t dport = ports[p ^ 1];\n\t\t\tif ((sport == INVALID_PORT_ID) || (dport == INVALID_PORT_ID))\n\t\t\t\tcontinue;\n\n\t\t\tfor (q = startQueue; q < endQueue; q++) {\n\t\t\t\tconst uint16_t rxCount = rte_eth_rx_burst(sport,\n\t\t\t\t\tq, buf, buf_size);\n\n\t\t\t\tif (unlikely(rxCount == 0))\n\t\t\t\t\tcontinue;\n\n\t\t\t\trxPackets[q] += rxCount;\n\n\t\t\t\tfor (i = 0; i < rxCount; i++)\n\t\t\t\t\tupdate_mac_address(buf[i], dport);\n\n\t\t\t\tconst uint16_t txCount = rte_eth_tx_burst(dport,\n\t\t\t\t\tvmdq_queue_base + core_id,\n\t\t\t\t\tbuf,\n\t\t\t\t\trxCount);\n\n\t\t\t\tif (txCount != rxCount) {\n\t\t\t\t\tfor (i = txCount; i < rxCount; i++)\n\t\t\t\t\t\trte_pktmbuf_free(buf[i]);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\n/*\n * Update the global var NUM_PORTS and array PORTS according to system ports number\n * and return valid ports number\n */\nstatic unsigned check_ports_num(unsigned nb_ports)\n{\n\tunsigned valid_num_ports = num_ports;\n\tunsigned portid;\n\n\tif (num_ports > nb_ports) {\n\t\tprintf(\"\\nSpecified port number(%u) exceeds total system port number(%u)\\n\",\n\t\t\tnum_ports, nb_ports);\n\t\tnum_ports = nb_ports;\n\t}\n\n\tfor (portid = 0; portid < num_ports; portid++) {\n\t\tif (ports[portid] >= nb_ports) {\n\t\t\tprintf(\"\\nSpecified port ID(%u) exceeds max system port ID(%u)\\n\",\n\t\t\t\tports[portid], (nb_ports - 1));\n\t\t\tports[portid] = INVALID_PORT_ID;\n\t\t\tvalid_num_ports--;\n\t\t}\n\t}\n\treturn valid_num_ports;\n}\n\n/* Main function, does initialisation and calls the per-lcore functions */\nint\nmain(int argc, char *argv[])\n{\n\tstruct rte_mempool *mbuf_pool;\n\tunsigned lcore_id, core_id = 0;\n\tint ret;\n\tunsigned nb_ports, valid_num_ports;\n\tuint8_t portid;\n\n\tsignal(SIGHUP, sighup_handler);\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Error with EAL initialization\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse app arguments */\n\tret = vmdq_parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid VMDQ argument\\n\");\n\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++)\n\t\tif (rte_lcore_is_enabled(lcore_id))\n\t\t\tlcore_ids[core_id++] = lcore_id;\n\n\tif (rte_lcore_count() > RTE_MAX_LCORE)\n\t\trte_exit(EXIT_FAILURE, \"Not enough cores\\n\");\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n\t/*\n\t * Update the global var NUM_PORTS and global array PORTS\n\t * and get value of var VALID_NUM_PORTS according to system ports number\n\t */\n\tvalid_num_ports = check_ports_num(nb_ports);\n\n\tif (valid_num_ports < 2 || valid_num_ports % 2) {\n\t\tprintf(\"Current valid ports number is %u\\n\", valid_num_ports);\n\t\trte_exit(EXIT_FAILURE, \"Error with valid ports number is not even or less than 2\\n\");\n\t}\n\n\tmbuf_pool = rte_pktmbuf_pool_create(\"MBUF_POOL\",\n\t\tNUM_MBUFS_PER_PORT * nb_ports, MBUF_CACHE_SIZE,\n\t\t0, RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\tif (mbuf_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create mbuf pool\\n\");\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"\\nSkipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\t\tif (port_init(portid, mbuf_pool) != 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot initialize network ports\\n\");\n\t}\n\n\t/* call lcore_main() on every lcore */\n\trte_eal_mp_remote_launch(lcore_main, NULL, CALL_MASTER);\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (rte_eal_wait_lcore(lcore_id) < 0)\n\t\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "examples/vmdq_dcb/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq ($(RTE_SDK),)\n$(error \"Please define RTE_SDK environment variable\")\nendif\n\n# Default target, can be overriden by command line or environment\nRTE_TARGET ?= x86_64-native-linuxapp-gcc\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# binary name\nAPP = vmdq_dcb_app\n\n# all source are stored in SRCS-y\nSRCS-y := main.c\n\nCFLAGS += $(WERROR_FLAGS)\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_main.o += -Wno-return-type\nendif\n\nEXTRA_CFLAGS += -O3 -g\n\ninclude $(RTE_SDK)/mk/rte.extapp.mk\n" }, { "path": "examples/vmdq_dcb/main.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/* basic constants used in application */\n#define NUM_QUEUES 128\n\n#define NUM_MBUFS 64*1024\n#define MBUF_CACHE_SIZE 64\n\n#define INVALID_PORT_ID 0xFF\n\n/* mask of enabled ports */\nstatic uint32_t enabled_port_mask = 0;\n\n/* number of pools (if user does not specify any, 16 by default */\nstatic enum rte_eth_nb_pools num_pools = ETH_16_POOLS;\n\n/* empty vmdq+dcb configuration structure. Filled in programatically */\nstatic const struct rte_eth_conf vmdq_dcb_conf_default = {\n\t.rxmode = {\n\t\t.mq_mode = ETH_MQ_RX_VMDQ_DCB,\n\t\t.split_hdr_size = 0,\n\t\t.header_split = 0, /**< Header Split disabled */\n\t\t.hw_ip_checksum = 0, /**< IP checksum offload disabled */\n\t\t.hw_vlan_filter = 0, /**< VLAN filtering disabled */\n\t\t.jumbo_frame = 0, /**< Jumbo Frame Support disabled */\n\t},\n\t.txmode = {\n\t\t.mq_mode = ETH_MQ_TX_NONE,\n\t},\n\t.rx_adv_conf = {\n\t\t/*\n\t\t * should be overridden separately in code with\n\t\t * appropriate values\n\t\t */\n\t\t.vmdq_dcb_conf = {\n\t\t\t.nb_queue_pools = ETH_16_POOLS,\n\t\t\t.enable_default_pool = 0,\n\t\t\t.default_pool = 0,\n\t\t\t.nb_pool_maps = 0,\n\t\t\t.pool_map = {{0, 0},},\n\t\t\t.dcb_queue = {0},\n\t\t},\n\t},\n};\n\nstatic uint8_t ports[RTE_MAX_ETHPORTS];\nstatic unsigned num_ports = 0;\n\n/* array used for printing out statistics */\nvolatile unsigned long rxPackets[ NUM_QUEUES ] = {0};\n\nconst uint16_t vlan_tags[] = {\n\t0, 1, 2, 3, 4, 5, 6, 7,\n\t8, 9, 10, 11,\t12, 13, 14, 15,\n\t16, 17, 18, 19, 20, 21, 22, 23,\n\t24, 25, 26, 27, 28, 29, 30, 31\n};\n\n/* Builds up the correct configuration for vmdq+dcb based on the vlan tags array\n * given above, and the number of traffic classes available for use. */\nstatic inline int\nget_eth_conf(struct rte_eth_conf *eth_conf, enum rte_eth_nb_pools num_pools)\n{\n\tstruct rte_eth_vmdq_dcb_conf conf;\n\tunsigned i;\n\n\tif (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS ) return -1;\n\n\tconf.nb_queue_pools = num_pools;\n\tconf.enable_default_pool = 0;\n\tconf.default_pool = 0; /* set explicit value, even if not used */\n\tconf.nb_pool_maps = sizeof( vlan_tags )/sizeof( vlan_tags[ 0 ]);\n\tfor (i = 0; i < conf.nb_pool_maps; i++){\n\t\tconf.pool_map[i].vlan_id = vlan_tags[ i ];\n\t\tconf.pool_map[i].pools = 1 << (i % num_pools);\n\t}\n\tfor (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++){\n\t\tconf.dcb_queue[i] = (uint8_t)(i % (NUM_QUEUES/num_pools));\n\t}\n\t(void)(rte_memcpy(eth_conf, &vmdq_dcb_conf_default, sizeof(*eth_conf)));\n\t(void)(rte_memcpy(ð_conf->rx_adv_conf.vmdq_dcb_conf, &conf,\n\t\t sizeof(eth_conf->rx_adv_conf.vmdq_dcb_conf)));\n\treturn 0;\n}\n\n/*\n * Initialises a given port using global settings and with the rx buffers\n * coming from the mbuf_pool passed as parameter\n */\nstatic inline int\nport_init(uint8_t port, struct rte_mempool *mbuf_pool)\n{\n\tstruct rte_eth_conf port_conf;\n\tconst uint16_t rxRings = ETH_VMDQ_DCB_NUM_QUEUES,\n\t\ttxRings = (uint16_t)rte_lcore_count();\n\tconst uint16_t rxRingSize = 128, txRingSize = 512;\n\tint retval;\n\tuint16_t q;\n\n\tretval = get_eth_conf(&port_conf, num_pools);\n\tif (retval < 0)\n\t\treturn retval;\n\n\tif (port >= rte_eth_dev_count()) return -1;\n\n\tretval = rte_eth_dev_configure(port, rxRings, txRings, &port_conf);\n\tif (retval != 0)\n\t\treturn retval;\n\n\tfor (q = 0; q < rxRings; q ++) {\n\t\tretval = rte_eth_rx_queue_setup(port, q, rxRingSize,\n\t\t\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\t\t\tNULL,\n\t\t\t\t\t\tmbuf_pool);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\tfor (q = 0; q < txRings; q ++) {\n\t\tretval = rte_eth_tx_queue_setup(port, q, txRingSize,\n\t\t\t\t\t\trte_eth_dev_socket_id(port),\n\t\t\t\t\t\tNULL);\n\t\tif (retval < 0)\n\t\t\treturn retval;\n\t}\n\n\tretval = rte_eth_dev_start(port);\n\tif (retval < 0)\n\t\treturn retval;\n\n\tstruct ether_addr addr;\n\trte_eth_macaddr_get(port, &addr);\n\tprintf(\"Port %u MAC: %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\n\t\t\t\" %02\"PRIx8\" %02\"PRIx8\" %02\"PRIx8\"\\n\",\n\t\t\t(unsigned)port,\n\t\t\taddr.addr_bytes[0], addr.addr_bytes[1], addr.addr_bytes[2],\n\t\t\taddr.addr_bytes[3], addr.addr_bytes[4], addr.addr_bytes[5]);\n\n\treturn 0;\n}\n\n/* Check num_pools parameter and set it if OK*/\nstatic int\nvmdq_parse_num_pools(const char *q_arg)\n{\n\tchar *end = NULL;\n\tint n;\n\n\t/* parse number string */\n\tn = strtol(q_arg, &end, 10);\n\tif ((q_arg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\tif (n != 16 && n != 32)\n\t\treturn -1;\n\tif (n == 16)\n\t\tnum_pools = ETH_16_POOLS;\n\telse\n\t\tnum_pools = ETH_32_POOLS;\n\n\treturn 0;\n}\n\nstatic int\nparse_portmask(const char *portmask)\n{\n\tchar *end = NULL;\n\tunsigned long pm;\n\n\t/* parse hexadecimal string */\n\tpm = strtoul(portmask, &end, 16);\n\tif ((portmask[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\treturn -1;\n\n\tif (pm == 0)\n\t\treturn -1;\n\n\treturn pm;\n}\n\n/* Display usage */\nstatic void\nvmdq_usage(const char *prgname)\n{\n\tprintf(\"%s [EAL options] -- -p PORTMASK]\\n\"\n\t \" --nb-pools NP: number of pools (16 default, 32)\\n\",\n\t prgname);\n}\n\n/* Parse the argument (num_pools) given in the command line of the application */\nstatic int\nvmdq_parse_args(int argc, char **argv)\n{\n\tint opt;\n\tint option_index;\n\tunsigned i;\n\tconst char *prgname = argv[0];\n\tstatic struct option long_option[] = {\n\t\t{\"nb-pools\", required_argument, NULL, 0},\n\t\t{NULL, 0, 0, 0}\n\t};\n\n\t/* Parse command line */\n\twhile ((opt = getopt_long(argc, argv, \"p:\",long_option,&option_index)) != EOF) {\n\t\tswitch (opt) {\n\t\t/* portmask */\n\t\tcase 'p':\n\t\t\tenabled_port_mask = parse_portmask(optarg);\n\t\t\tif (enabled_port_mask == 0) {\n\t\t\t\tprintf(\"invalid portmask\\n\");\n\t\t\t\tvmdq_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 0:\n\t\t\tif (vmdq_parse_num_pools(optarg) == -1){\n\t\t\t\tprintf(\"invalid number of pools\\n\");\n\t\t\t\tvmdq_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tvmdq_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tfor(i = 0; i < RTE_MAX_ETHPORTS; i++)\n\t{\n\t\tif (enabled_port_mask & (1 << i))\n\t\t\tports[num_ports++] = (uint8_t)i;\n\t}\n\n\tif (num_ports < 2 || num_ports % 2) {\n\t\tprintf(\"Current enabled port number is %u,\"\n\t\t\t\"but it should be even and at least 2\\n\",num_ports);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n\n/* When we receive a HUP signal, print out our stats */\nstatic void\nsighup_handler(int signum)\n{\n\tunsigned q;\n\tfor (q = 0; q < NUM_QUEUES; q ++) {\n\t\tif (q % (NUM_QUEUES/num_pools) == 0)\n\t\t\tprintf(\"\\nPool %u: \", q/(NUM_QUEUES/num_pools));\n\t\tprintf(\"%lu \", rxPackets[ q ]);\n\t}\n\tprintf(\"\\nFinished handling signal %d\\n\", signum);\n}\n\n/*\n * Main thread that does the work, reading from INPUT_PORT\n * and writing to OUTPUT_PORT\n */\nstatic __attribute__((noreturn)) int\nlcore_main(void *arg)\n{\n\tconst uintptr_t core_num = (uintptr_t)arg;\n\tconst unsigned num_cores = rte_lcore_count();\n\tuint16_t startQueue = (uint16_t)(core_num * (NUM_QUEUES/num_cores));\n\tuint16_t endQueue = (uint16_t)(startQueue + (NUM_QUEUES/num_cores));\n\tuint16_t q, i, p;\n\n\tprintf(\"Core %u(lcore %u) reading queues %i-%i\\n\", (unsigned)core_num,\n\t rte_lcore_id(), startQueue, endQueue - 1);\n\n\tfor (;;) {\n\t\tstruct rte_mbuf *buf[32];\n\t\tconst uint16_t buf_size = sizeof(buf) / sizeof(buf[0]);\n\t\tfor (p = 0; p < num_ports; p++) {\n\t\t\tconst uint8_t src = ports[p];\n\t\t\tconst uint8_t dst = ports[p ^ 1]; /* 0 <-> 1, 2 <-> 3 etc */\n\n\t\t\tif ((src == INVALID_PORT_ID) || (dst == INVALID_PORT_ID))\n\t\t\t\tcontinue;\n\n\t\t\tfor (q = startQueue; q < endQueue; q++) {\n\t\t\t\tconst uint16_t rxCount = rte_eth_rx_burst(src,\n\t\t\t\t\tq, buf, buf_size);\n\t\t\t\tif (rxCount == 0)\n\t\t\t\t\tcontinue;\n\t\t\t\trxPackets[q] += rxCount;\n\n\t\t\t\tconst uint16_t txCount = rte_eth_tx_burst(dst,\n\t\t\t\t\t(uint16_t)core_num, buf, rxCount);\n\t\t\t\tif (txCount != rxCount) {\n\t\t\t\t\tfor (i = txCount; i < rxCount; i++)\n\t\t\t\t\t\trte_pktmbuf_free(buf[i]);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n}\n\n/*\n * Update the global var NUM_PORTS and array PORTS according to system ports number\n * and return valid ports number\n */\nstatic unsigned check_ports_num(unsigned nb_ports)\n{\n\tunsigned valid_num_ports = num_ports;\n\tunsigned portid;\n\n\tif (num_ports > nb_ports) {\n\t\tprintf(\"\\nSpecified port number(%u) exceeds total system port number(%u)\\n\",\n\t\t\tnum_ports, nb_ports);\n\t\tnum_ports = nb_ports;\n\t}\n\n\tfor (portid = 0; portid < num_ports; portid ++) {\n\t\tif (ports[portid] >= nb_ports) {\n\t\t\tprintf(\"\\nSpecified port ID(%u) exceeds max system port ID(%u)\\n\",\n\t\t\t\tports[portid], (nb_ports - 1));\n\t\t\tports[portid] = INVALID_PORT_ID;\n\t\t\tvalid_num_ports --;\n\t\t}\n\t}\n\treturn valid_num_ports;\n}\n\n\n/* Main function, does initialisation and calls the per-lcore functions */\nint\nmain(int argc, char *argv[])\n{\n\tunsigned cores;\n\tstruct rte_mempool *mbuf_pool;\n\tunsigned lcore_id;\n\tuintptr_t i;\n\tint ret;\n\tunsigned nb_ports, valid_num_ports;\n\tuint8_t portid;\n\n\tsignal(SIGHUP, sighup_handler);\n\n\t/* init EAL */\n\tret = rte_eal_init(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Error with EAL initialization\\n\");\n\targc -= ret;\n\targv += ret;\n\n\t/* parse app arguments */\n\tret = vmdq_parse_args(argc, argv);\n\tif (ret < 0)\n\t\trte_exit(EXIT_FAILURE, \"Invalid VMDQ argument\\n\");\n\n\tcores = rte_lcore_count();\n\tif ((cores & (cores - 1)) != 0 || cores > 128) {\n\t\trte_exit(EXIT_FAILURE,\"This program can only run on an even\"\n\t\t\t\t\"number of cores(1-128)\\n\\n\");\n\t}\n\n\tnb_ports = rte_eth_dev_count();\n\tif (nb_ports > RTE_MAX_ETHPORTS)\n\t\tnb_ports = RTE_MAX_ETHPORTS;\n\n /*\n\t * Update the global var NUM_PORTS and global array PORTS\n\t * and get value of var VALID_NUM_PORTS according to system ports number\n\t */\n\tvalid_num_ports = check_ports_num(nb_ports);\n\n\tif (valid_num_ports < 2 || valid_num_ports % 2) {\n\t\tprintf(\"Current valid ports number is %u\\n\", valid_num_ports);\n\t\trte_exit(EXIT_FAILURE, \"Error with valid ports number is not even or less than 2\\n\");\n\t}\n\n\tmbuf_pool = rte_pktmbuf_pool_create(\"MBUF_POOL\", NUM_MBUFS * nb_ports,\n\t\tMBUF_CACHE_SIZE, 0, RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());\n\tif (mbuf_pool == NULL)\n\t\trte_exit(EXIT_FAILURE, \"Cannot create mbuf pool\\n\");\n\n\t/* initialize all ports */\n\tfor (portid = 0; portid < nb_ports; portid++) {\n\t\t/* skip ports that are not enabled */\n\t\tif ((enabled_port_mask & (1 << portid)) == 0) {\n\t\t\tprintf(\"\\nSkipping disabled port %d\\n\", portid);\n\t\t\tcontinue;\n\t\t}\n\t\tif (port_init(portid, mbuf_pool) != 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Cannot initialize network ports\\n\");\n\t}\n\n\t/* call lcore_main() on every slave lcore */\n\ti = 0;\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\trte_eal_remote_launch(lcore_main, (void*)i++, lcore_id);\n\t}\n\t/* call on master too */\n\t(void) lcore_main((void*)i);\n\n\treturn 0;\n}\n" }, { "path": "lib/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nDIRS-y += librte_compat\nDIRS-$(CONFIG_RTE_LIBRTE_EAL) += librte_eal\nDIRS-$(CONFIG_RTE_LIBRTE_EAL) += librte_malloc\nDIRS-$(CONFIG_RTE_LIBRTE_RING) += librte_ring\nDIRS-$(CONFIG_RTE_LIBRTE_MEMPOOL) += librte_mempool\nDIRS-$(CONFIG_RTE_LIBRTE_MBUF) += librte_mbuf\nDIRS-$(CONFIG_RTE_LIBRTE_TIMER) += librte_timer\nDIRS-$(CONFIG_RTE_LIBRTE_CFGFILE) += librte_cfgfile\nDIRS-$(CONFIG_RTE_LIBRTE_CMDLINE) += librte_cmdline\nDIRS-$(CONFIG_RTE_LIBRTE_ETHER) += librte_ether\nDIRS-$(CONFIG_RTE_LIBRTE_VHOST) += librte_vhost\nDIRS-$(CONFIG_RTE_LIBRTE_HASH) += librte_hash\nDIRS-$(CONFIG_RTE_LIBRTE_LPM) += librte_lpm\nDIRS-$(CONFIG_RTE_LIBRTE_ACL) += librte_acl\nDIRS-$(CONFIG_RTE_LIBRTE_NET) += librte_net\nDIRS-$(CONFIG_RTE_LIBRTE_IP_FRAG) += librte_ip_frag\nDIRS-$(CONFIG_RTE_LIBRTE_JOBSTATS) += librte_jobstats\nDIRS-$(CONFIG_RTE_LIBRTE_POWER) += librte_power\nDIRS-$(CONFIG_RTE_LIBRTE_METER) += librte_meter\nDIRS-$(CONFIG_RTE_LIBRTE_SCHED) += librte_sched\nDIRS-$(CONFIG_RTE_LIBRTE_KVARGS) += librte_kvargs\nDIRS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) += librte_distributor\nDIRS-$(CONFIG_RTE_LIBRTE_PORT) += librte_port\nDIRS-$(CONFIG_RTE_LIBRTE_TABLE) += librte_table\nDIRS-$(CONFIG_RTE_LIBRTE_PIPELINE) += librte_pipeline\nDIRS-$(CONFIG_RTE_LIBRTE_REORDER) += librte_reorder\n\nifeq ($(CONFIG_RTE_EXEC_ENV_LINUXAPP),y)\nDIRS-$(CONFIG_RTE_LIBRTE_KNI) += librte_kni\nDIRS-$(CONFIG_RTE_LIBRTE_IVSHMEM) += librte_ivshmem\nendif\n\ninclude $(RTE_SDK)/mk/rte.sharelib.mk\ninclude $(RTE_SDK)/mk/rte.subdir.mk\n" }, { "path": "lib/librte_acl/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_acl.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR)\n\nEXPORT_MAP := rte_acl_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_ACL) += tb_mem.c\n\nSRCS-$(CONFIG_RTE_LIBRTE_ACL) += rte_acl.c\nSRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_bld.c\nSRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_gen.c\nSRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_scalar.c\nSRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_sse.c\n\nCFLAGS_acl_run_sse.o += -msse4.1\n\n#\n# If the compiler supports AVX2 instructions,\n# then add support for AVX2 classify method.\n#\n\nCC_AVX2_SUPPORT=$(shell $(CC) -march=core-avx2 -dM -E - &1 | \\\ngrep -q AVX2 && echo 1)\n\nifeq ($(CC_AVX2_SUPPORT), 1)\n\tSRCS-$(CONFIG_RTE_LIBRTE_ACL) += acl_run_avx2.c\n\tCFLAGS_rte_acl.o += -DCC_AVX2_SUPPORT\n\tifeq ($(CC), icc)\n\tCFLAGS_acl_run_avx2.o += -march=core-avx2\n\telse\n\tCFLAGS_acl_run_avx2.o += -mavx2\n\tendif\nendif\n\n# install this header file\nSYMLINK-$(CONFIG_RTE_LIBRTE_ACL)-include := rte_acl_osdep.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_ACL)-include += rte_acl.h\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_ACL) += lib/librte_eal\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_acl/acl.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef\t_ACL_H_\n#define\t_ACL_H_\n\n#ifdef __cplusplus\nextern\"C\" {\n#endif /* __cplusplus */\n\n#define RTE_ACL_QUAD_MAX\t5\n#define RTE_ACL_QUAD_SIZE\t4\n#define RTE_ACL_QUAD_SINGLE\tUINT64_C(0x7f7f7f7f00000000)\n\n#define RTE_ACL_SINGLE_TRIE_SIZE\t2000\n\n#define RTE_ACL_DFA_MAX\t\tUINT8_MAX\n#define RTE_ACL_DFA_SIZE\t(UINT8_MAX + 1)\n\n#define\tRTE_ACL_DFA_GR64_SIZE\t64\n#define\tRTE_ACL_DFA_GR64_NUM\t(RTE_ACL_DFA_SIZE / RTE_ACL_DFA_GR64_SIZE)\n#define\tRTE_ACL_DFA_GR64_BIT\t\\\n\t(CHAR_BIT * sizeof(uint32_t) / RTE_ACL_DFA_GR64_NUM)\n\ntypedef int bits_t;\n\n#define\tRTE_ACL_BIT_SET_SIZE\t((UINT8_MAX + 1) / (sizeof(bits_t) * CHAR_BIT))\n\nstruct rte_acl_bitset {\n\tbits_t bits[RTE_ACL_BIT_SET_SIZE];\n};\n\n#define\tRTE_ACL_NODE_DFA\t(0 << RTE_ACL_TYPE_SHIFT)\n#define\tRTE_ACL_NODE_SINGLE\t(1U << RTE_ACL_TYPE_SHIFT)\n#define\tRTE_ACL_NODE_QRANGE\t(3U << RTE_ACL_TYPE_SHIFT)\n#define\tRTE_ACL_NODE_MATCH\t(4U << RTE_ACL_TYPE_SHIFT)\n#define\tRTE_ACL_NODE_TYPE\t(7U << RTE_ACL_TYPE_SHIFT)\n#define\tRTE_ACL_NODE_UNDEFINED\tUINT32_MAX\n\n/*\n * ACL RT structure is a set of multibit tries (with stride == 8)\n * represented by an array of transitions. The next position is calculated\n * based on the current position and the input byte.\n * Each transition is 64 bit value with the following format:\n * | node_type_specific : 32 | node_type : 3 | node_addr : 29 |\n * For all node types except RTE_ACL_NODE_MATCH, node_addr is an index\n * to the start of the node in the transtions array.\n * Few different node types are used:\n * RTE_ACL_NODE_MATCH:\n * node_addr value is and index into an array that contains the return value\n * and its priority for each category.\n * Upper 32 bits of the transition value are not used for that node type.\n * RTE_ACL_NODE_QRANGE:\n * that node consist of up to 5 transitions.\n * Upper 32 bits are interpreted as 4 signed character values which\n * are ordered from smallest(INT8_MIN) to largest (INT8_MAX).\n * These values define 5 ranges:\n * INT8_MIN <= range[0] <= ((int8_t *)&transition)[4]\n * ((int8_t *)&transition)[4] < range[1] <= ((int8_t *)&transition)[5]\n * ((int8_t *)&transition)[5] < range[2] <= ((int8_t *)&transition)[6]\n * ((int8_t *)&transition)[6] < range[3] <= ((int8_t *)&transition)[7]\n * ((int8_t *)&transition)[7] < range[4] <= INT8_MAX\n * So for input byte value within range[i] i-th transition within that node\n * will be used.\n * RTE_ACL_NODE_SINGLE:\n * always transitions to the same node regardless of the input value.\n * RTE_ACL_NODE_DFA:\n * that node consits of up to 256 transitions.\n * In attempt to conserve space all transitions are divided into 4 consecutive\n * groups, by 64 transitions per group:\n * group64[i] contains transitions[i * 64, .. i * 64 + 63].\n * Upper 32 bits are interpreted as 4 unsigned character values one per group,\n * which contain index to the start of the given group within the node.\n * So to calculate transition index within the node for given input byte value:\n * input_byte - ((uint8_t *)&transition)[4 + input_byte / 64].\n */\n\n/*\n * Structure of a node is a set of ptrs and each ptr has a bit map\n * of values associated with this transition.\n */\nstruct rte_acl_ptr_set {\n\tstruct rte_acl_bitset values;\t/* input values associated with ptr */\n\tstruct rte_acl_node *ptr;\t/* transition to next node */\n};\n\nstruct rte_acl_classifier_results {\n\tint results[RTE_ACL_MAX_CATEGORIES];\n};\n\nstruct rte_acl_match_results {\n\tuint32_t results[RTE_ACL_MAX_CATEGORIES];\n\tint32_t priority[RTE_ACL_MAX_CATEGORIES];\n};\n\nstruct rte_acl_node {\n\tuint64_t node_index; /* index for this node */\n\tuint32_t level; /* level 0-n in the trie */\n\tuint32_t ref_count; /* ref count for this node */\n\tstruct rte_acl_bitset values;\n\t/* set of all values that map to another node\n\t * (union of bits in each transition.\n\t */\n\tuint32_t num_ptrs; /* number of ptr_set in use */\n\tuint32_t max_ptrs; /* number of allocated ptr_set */\n\tuint32_t min_add; /* number of ptr_set per allocation */\n\tstruct rte_acl_ptr_set *ptrs; /* transitions array for this node */\n\tint32_t match_flag;\n\tint32_t match_index; /* index to match data */\n\tuint32_t node_type;\n\tint32_t fanout;\n\t/* number of ranges (transitions w/ consecutive bits) */\n\tint32_t id;\n\tstruct rte_acl_match_results *mrt; /* only valid when match_flag != 0 */\n\tunion {\n\t\tchar transitions[RTE_ACL_QUAD_SIZE];\n\t\t/* boundaries for ranged node */\n\t\tuint8_t dfa_gr64[RTE_ACL_DFA_GR64_NUM];\n\t};\n\tstruct rte_acl_node *next;\n\t/* free list link or pointer to duplicate node during merge */\n\tstruct rte_acl_node *prev;\n\t/* points to node from which this node was duplicated */\n};\n\n/*\n * Types of tries used to generate runtime structure(s)\n */\nenum {\n\tRTE_ACL_FULL_TRIE = 0,\n\tRTE_ACL_NOSRC_TRIE = 1,\n\tRTE_ACL_NODST_TRIE = 2,\n\tRTE_ACL_NOPORTS_TRIE = 4,\n\tRTE_ACL_NOVLAN_TRIE = 8,\n\tRTE_ACL_UNUSED_TRIE = 0x80000000\n};\n\n\n/** MAX number of tries per one ACL context.*/\n#define RTE_ACL_MAX_TRIES\t8\n\n/** Max number of characters in PM name.*/\n#define RTE_ACL_NAMESIZE\t32\n\n\nstruct rte_acl_trie {\n\tuint32_t type;\n\tuint32_t count;\n\tuint32_t root_index;\n\tconst uint32_t *data_index;\n\tuint32_t num_data_indexes;\n};\n\nstruct rte_acl_bld_trie {\n\tstruct rte_acl_node *trie;\n};\n\nstruct rte_acl_ctx {\n\tchar name[RTE_ACL_NAMESIZE];\n\t/** Name of the ACL context. */\n\tint32_t socket_id;\n\t/** Socket ID to allocate memory from. */\n\tenum rte_acl_classify_alg alg;\n\tvoid *rules;\n\tuint32_t max_rules;\n\tuint32_t rule_sz;\n\tuint32_t num_rules;\n\tuint32_t num_categories;\n\tuint32_t num_tries;\n\tuint32_t match_index;\n\tuint64_t no_match;\n\tuint64_t idle;\n\tuint64_t *trans_table;\n\tuint32_t *data_indexes;\n\tstruct rte_acl_trie trie[RTE_ACL_MAX_TRIES];\n\tvoid *mem;\n\tsize_t mem_sz;\n\tstruct rte_acl_config config; /* copy of build config. */\n};\n\nint rte_acl_gen(struct rte_acl_ctx *ctx, struct rte_acl_trie *trie,\n\tstruct rte_acl_bld_trie *node_bld_trie, uint32_t num_tries,\n\tuint32_t num_categories, uint32_t data_index_sz, size_t max_size);\n\ntypedef int (*rte_acl_classify_t)\n(const struct rte_acl_ctx *, const uint8_t **, uint32_t *, uint32_t, uint32_t);\n\n/*\n * Different implementations of ACL classify.\n */\nint\nrte_acl_classify_scalar(const struct rte_acl_ctx *ctx, const uint8_t **data,\n\tuint32_t *results, uint32_t num, uint32_t categories);\n\nint\nrte_acl_classify_sse(const struct rte_acl_ctx *ctx, const uint8_t **data,\n\tuint32_t *results, uint32_t num, uint32_t categories);\n\nint\nrte_acl_classify_avx2(const struct rte_acl_ctx *ctx, const uint8_t **data,\n\tuint32_t *results, uint32_t num, uint32_t categories);\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* _ACL_H_ */\n" }, { "path": "lib/librte_acl/acl_bld.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \"tb_mem.h\"\n#include \"acl.h\"\n\n#define\tACL_POOL_ALIGN\t\t8\n#define\tACL_POOL_ALLOC_MIN\t0x800000\n\n/* number of pointers per alloc */\n#define ACL_PTR_ALLOC\t32\n\n/* macros for dividing rule sets heuristics */\n#define NODE_MAX\t0x4000\n#define NODE_MIN\t0x800\n\n/* TALLY are statistics per field */\nenum {\n\tTALLY_0 = 0, /* number of rules that are 0% or more wild. */\n\tTALLY_25,\t /* number of rules that are 25% or more wild. */\n\tTALLY_50,\n\tTALLY_75,\n\tTALLY_100,\n\tTALLY_DEACTIVATED, /* deactivated fields (100% wild in all rules). */\n\tTALLY_DEPTH,\n\t/* number of rules that are 100% wild for this field and higher. */\n\tTALLY_NUM\n};\n\nstatic const uint32_t wild_limits[TALLY_DEACTIVATED] = {0, 25, 50, 75, 100};\n\nenum {\n\tACL_INTERSECT_NONE = 0,\n\tACL_INTERSECT_A = 1, /* set A is a superset of A and B intersect */\n\tACL_INTERSECT_B = 2, /* set B is a superset of A and B intersect */\n\tACL_INTERSECT = 4,\t/* sets A and B intersect */\n};\n\nenum {\n\tACL_PRIORITY_EQUAL = 0,\n\tACL_PRIORITY_NODE_A = 1,\n\tACL_PRIORITY_NODE_B = 2,\n\tACL_PRIORITY_MIXED = 3\n};\n\n\nstruct acl_mem_block {\n\tuint32_t block_size;\n\tvoid *mem_ptr;\n};\n\n#define\tMEM_BLOCK_NUM\t16\n\n/* Single ACL rule, build representation.*/\nstruct rte_acl_build_rule {\n\tstruct rte_acl_build_rule *next;\n\tstruct rte_acl_config *config;\n\t/**< configuration for each field in the rule. */\n\tconst struct rte_acl_rule *f;\n\tuint32_t *wildness;\n};\n\n/* Context for build phase */\nstruct acl_build_context {\n\tconst struct rte_acl_ctx *acx;\n\tstruct rte_acl_build_rule *build_rules;\n\tstruct rte_acl_config cfg;\n\tint32_t node_max;\n\tint32_t cur_node_max;\n\tuint32_t node;\n\tuint32_t num_nodes;\n\tuint32_t category_mask;\n\tuint32_t num_rules;\n\tuint32_t node_id;\n\tuint32_t src_mask;\n\tuint32_t num_build_rules;\n\tuint32_t num_tries;\n\tstruct tb_mem_pool pool;\n\tstruct rte_acl_trie tries[RTE_ACL_MAX_TRIES];\n\tstruct rte_acl_bld_trie bld_tries[RTE_ACL_MAX_TRIES];\n\tuint32_t data_indexes[RTE_ACL_MAX_TRIES][RTE_ACL_MAX_FIELDS];\n\n\t/* memory free lists for nodes and blocks used for node ptrs */\n\tstruct acl_mem_block blocks[MEM_BLOCK_NUM];\n\tstruct rte_acl_node *node_free_list;\n};\n\nstatic int acl_merge_trie(struct acl_build_context *context,\n\tstruct rte_acl_node *node_a, struct rte_acl_node *node_b,\n\tuint32_t level, struct rte_acl_node **node_c);\n\nstatic void\nacl_deref_ptr(struct acl_build_context *context,\n\tstruct rte_acl_node *node, int index);\n\nstatic void *\nacl_build_alloc(struct acl_build_context *context, size_t n, size_t s)\n{\n\tuint32_t m;\n\tvoid *p;\n\tsize_t alloc_size = n * s;\n\n\t/*\n\t * look for memory in free lists\n\t */\n\tfor (m = 0; m < RTE_DIM(context->blocks); m++) {\n\t\tif (context->blocks[m].block_size ==\n\t\t alloc_size && context->blocks[m].mem_ptr != NULL) {\n\t\t\tp = context->blocks[m].mem_ptr;\n\t\t\tcontext->blocks[m].mem_ptr = *((void **)p);\n\t\t\tmemset(p, 0, alloc_size);\n\t\t\treturn p;\n\t\t}\n\t}\n\n\t/*\n\t * return allocation from memory pool\n\t */\n\tp = tb_alloc(&context->pool, alloc_size);\n\treturn p;\n}\n\n/*\n * Free memory blocks (kept in context for reuse).\n */\nstatic void\nacl_build_free(struct acl_build_context *context, size_t s, void *p)\n{\n\tuint32_t n;\n\n\tfor (n = 0; n < RTE_DIM(context->blocks); n++) {\n\t\tif (context->blocks[n].block_size == s) {\n\t\t\t*((void **)p) = context->blocks[n].mem_ptr;\n\t\t\tcontext->blocks[n].mem_ptr = p;\n\t\t\treturn;\n\t\t}\n\t}\n\tfor (n = 0; n < RTE_DIM(context->blocks); n++) {\n\t\tif (context->blocks[n].block_size == 0) {\n\t\t\tcontext->blocks[n].block_size = s;\n\t\t\t*((void **)p) = NULL;\n\t\t\tcontext->blocks[n].mem_ptr = p;\n\t\t\treturn;\n\t\t}\n\t}\n}\n\n/*\n * Allocate and initialize a new node.\n */\nstatic struct rte_acl_node *\nacl_alloc_node(struct acl_build_context *context, int level)\n{\n\tstruct rte_acl_node *node;\n\n\tif (context->node_free_list != NULL) {\n\t\tnode = context->node_free_list;\n\t\tcontext->node_free_list = node->next;\n\t\tmemset(node, 0, sizeof(struct rte_acl_node));\n\t} else {\n\t\tnode = acl_build_alloc(context, sizeof(struct rte_acl_node), 1);\n\t}\n\n\tif (node != NULL) {\n\t\tnode->num_ptrs = 0;\n\t\tnode->level = level;\n\t\tnode->node_type = RTE_ACL_NODE_UNDEFINED;\n\t\tnode->node_index = RTE_ACL_NODE_UNDEFINED;\n\t\tcontext->num_nodes++;\n\t\tnode->id = context->node_id++;\n\t}\n\treturn node;\n}\n\n/*\n * Dereference all nodes to which this node points\n */\nstatic void\nacl_free_node(struct acl_build_context *context,\n\tstruct rte_acl_node *node)\n{\n\tuint32_t n;\n\n\tif (node->prev != NULL)\n\t\tnode->prev->next = NULL;\n\tfor (n = 0; n < node->num_ptrs; n++)\n\t\tacl_deref_ptr(context, node, n);\n\n\t/* free mrt if this is a match node */\n\tif (node->mrt != NULL) {\n\t\tacl_build_free(context, sizeof(struct rte_acl_match_results),\n\t\t\tnode->mrt);\n\t\tnode->mrt = NULL;\n\t}\n\n\t/* free transitions to other nodes */\n\tif (node->ptrs != NULL) {\n\t\tacl_build_free(context,\n\t\t\tnode->max_ptrs * sizeof(struct rte_acl_ptr_set),\n\t\t\tnode->ptrs);\n\t\tnode->ptrs = NULL;\n\t}\n\n\t/* put it on the free list */\n\tcontext->num_nodes--;\n\tnode->next = context->node_free_list;\n\tcontext->node_free_list = node;\n}\n\n\n/*\n * Include src bitset in dst bitset\n */\nstatic void\nacl_include(struct rte_acl_bitset *dst, struct rte_acl_bitset *src, bits_t mask)\n{\n\tuint32_t n;\n\n\tfor (n = 0; n < RTE_ACL_BIT_SET_SIZE; n++)\n\t\tdst->bits[n] = (dst->bits[n] & mask) | src->bits[n];\n}\n\n/*\n * Set dst to bits of src1 that are not in src2\n */\nstatic int\nacl_exclude(struct rte_acl_bitset *dst,\n\tstruct rte_acl_bitset *src1,\n\tstruct rte_acl_bitset *src2)\n{\n\tuint32_t n;\n\tbits_t all_bits = 0;\n\n\tfor (n = 0; n < RTE_ACL_BIT_SET_SIZE; n++) {\n\t\tdst->bits[n] = src1->bits[n] & ~src2->bits[n];\n\t\tall_bits |= dst->bits[n];\n\t}\n\treturn all_bits != 0;\n}\n\n/*\n * Add a pointer (ptr) to a node.\n */\nstatic int\nacl_add_ptr(struct acl_build_context *context,\n\tstruct rte_acl_node *node,\n\tstruct rte_acl_node *ptr,\n\tstruct rte_acl_bitset *bits)\n{\n\tuint32_t n, num_ptrs;\n\tstruct rte_acl_ptr_set *ptrs = NULL;\n\n\t/*\n\t * If there's already a pointer to the same node, just add to the bitset\n\t */\n\tfor (n = 0; n < node->num_ptrs; n++) {\n\t\tif (node->ptrs[n].ptr != NULL) {\n\t\t\tif (node->ptrs[n].ptr == ptr) {\n\t\t\t\tacl_include(&node->ptrs[n].values, bits, -1);\n\t\t\t\tacl_include(&node->values, bits, -1);\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* if there's no room for another pointer, make room */\n\tif (node->num_ptrs >= node->max_ptrs) {\n\t\t/* add room for more pointers */\n\t\tnum_ptrs = node->max_ptrs + ACL_PTR_ALLOC;\n\t\tptrs = acl_build_alloc(context, num_ptrs, sizeof(*ptrs));\n\n\t\t/* copy current points to new memory allocation */\n\t\tif (node->ptrs != NULL) {\n\t\t\tmemcpy(ptrs, node->ptrs,\n\t\t\t\tnode->num_ptrs * sizeof(*ptrs));\n\t\t\tacl_build_free(context, node->max_ptrs * sizeof(*ptrs),\n\t\t\t\tnode->ptrs);\n\t\t}\n\t\tnode->ptrs = ptrs;\n\t\tnode->max_ptrs = num_ptrs;\n\t}\n\n\t/* Find available ptr and add a new pointer to this node */\n\tfor (n = node->min_add; n < node->max_ptrs; n++) {\n\t\tif (node->ptrs[n].ptr == NULL) {\n\t\t\tnode->ptrs[n].ptr = ptr;\n\t\t\tacl_include(&node->ptrs[n].values, bits, 0);\n\t\t\tacl_include(&node->values, bits, -1);\n\t\t\tif (ptr != NULL)\n\t\t\t\tptr->ref_count++;\n\t\t\tif (node->num_ptrs <= n)\n\t\t\t\tnode->num_ptrs = n + 1;\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/*\n * Add a pointer for a range of values\n */\nstatic int\nacl_add_ptr_range(struct acl_build_context *context,\n\tstruct rte_acl_node *root,\n\tstruct rte_acl_node *node,\n\tuint8_t low,\n\tuint8_t high)\n{\n\tuint32_t n;\n\tstruct rte_acl_bitset bitset;\n\n\t/* clear the bitset values */\n\tfor (n = 0; n < RTE_ACL_BIT_SET_SIZE; n++)\n\t\tbitset.bits[n] = 0;\n\n\t/* for each bit in range, add bit to set */\n\tfor (n = 0; n < UINT8_MAX + 1; n++)\n\t\tif (n >= low && n <= high)\n\t\t\tbitset.bits[n / (sizeof(bits_t) * 8)] |=\n\t\t\t\t1 << (n % (sizeof(bits_t) * 8));\n\n\treturn acl_add_ptr(context, root, node, &bitset);\n}\n\n/*\n * Generate a bitset from a byte value and mask.\n */\nstatic int\nacl_gen_mask(struct rte_acl_bitset *bitset, uint32_t value, uint32_t mask)\n{\n\tint range = 0;\n\tuint32_t n;\n\n\t/* clear the bitset values */\n\tfor (n = 0; n < RTE_ACL_BIT_SET_SIZE; n++)\n\t\tbitset->bits[n] = 0;\n\n\t/* for each bit in value/mask, add bit to set */\n\tfor (n = 0; n < UINT8_MAX + 1; n++) {\n\t\tif ((n & mask) == value) {\n\t\t\trange++;\n\t\t\tbitset->bits[n / (sizeof(bits_t) * 8)] |=\n\t\t\t\t1 << (n % (sizeof(bits_t) * 8));\n\t\t}\n\t}\n\treturn range;\n}\n\n/*\n * Determine how A and B intersect.\n * Determine if A and/or B are supersets of the intersection.\n */\nstatic int\nacl_intersect_type(const struct rte_acl_bitset *a_bits,\n\tconst struct rte_acl_bitset *b_bits,\n\tstruct rte_acl_bitset *intersect)\n{\n\tuint32_t n;\n\tbits_t intersect_bits = 0;\n\tbits_t a_superset = 0;\n\tbits_t b_superset = 0;\n\n\t/*\n\t * calculate and store intersection and check if A and/or B have\n\t * bits outside the intersection (superset)\n\t */\n\tfor (n = 0; n < RTE_ACL_BIT_SET_SIZE; n++) {\n\t\tintersect->bits[n] = a_bits->bits[n] & b_bits->bits[n];\n\t\ta_superset |= a_bits->bits[n] ^ intersect->bits[n];\n\t\tb_superset |= b_bits->bits[n] ^ intersect->bits[n];\n\t\tintersect_bits |= intersect->bits[n];\n\t}\n\n\tn = (intersect_bits == 0 ? ACL_INTERSECT_NONE : ACL_INTERSECT) |\n\t\t(b_superset == 0 ? 0 : ACL_INTERSECT_B) |\n\t\t(a_superset == 0 ? 0 : ACL_INTERSECT_A);\n\n\treturn n;\n}\n\n/*\n * Duplicate a node\n */\nstatic struct rte_acl_node *\nacl_dup_node(struct acl_build_context *context, struct rte_acl_node *node)\n{\n\tuint32_t n;\n\tstruct rte_acl_node *next;\n\n\tnext = acl_alloc_node(context, node->level);\n\n\t/* allocate the pointers */\n\tif (node->num_ptrs > 0) {\n\t\tnext->ptrs = acl_build_alloc(context,\n\t\t\tnode->max_ptrs,\n\t\t\tsizeof(struct rte_acl_ptr_set));\n\t\tnext->max_ptrs = node->max_ptrs;\n\t}\n\n\t/* copy over the pointers */\n\tfor (n = 0; n < node->num_ptrs; n++) {\n\t\tif (node->ptrs[n].ptr != NULL) {\n\t\t\tnext->ptrs[n].ptr = node->ptrs[n].ptr;\n\t\t\tnext->ptrs[n].ptr->ref_count++;\n\t\t\tacl_include(&next->ptrs[n].values,\n\t\t\t\t&node->ptrs[n].values, -1);\n\t\t}\n\t}\n\n\tnext->num_ptrs = node->num_ptrs;\n\n\t/* copy over node's match results */\n\tif (node->match_flag == 0)\n\t\tnext->match_flag = 0;\n\telse {\n\t\tnext->match_flag = -1;\n\t\tnext->mrt = acl_build_alloc(context, 1, sizeof(*next->mrt));\n\t\tmemcpy(next->mrt, node->mrt, sizeof(*next->mrt));\n\t}\n\n\t/* copy over node's bitset */\n\tacl_include(&next->values, &node->values, -1);\n\n\tnode->next = next;\n\tnext->prev = node;\n\n\treturn next;\n}\n\n/*\n * Dereference a pointer from a node\n */\nstatic void\nacl_deref_ptr(struct acl_build_context *context,\n\tstruct rte_acl_node *node, int index)\n{\n\tstruct rte_acl_node *ref_node;\n\n\t/* De-reference the node at the specified pointer */\n\tif (node != NULL && node->ptrs[index].ptr != NULL) {\n\t\tref_node = node->ptrs[index].ptr;\n\t\tref_node->ref_count--;\n\t\tif (ref_node->ref_count == 0)\n\t\t\tacl_free_node(context, ref_node);\n\t}\n}\n\n/*\n * acl_exclude rte_acl_bitset from src and copy remaining pointer to dst\n */\nstatic int\nacl_copy_ptr(struct acl_build_context *context,\n\tstruct rte_acl_node *dst,\n\tstruct rte_acl_node *src,\n\tint index,\n\tstruct rte_acl_bitset *b_bits)\n{\n\tint rc;\n\tstruct rte_acl_bitset bits;\n\n\tif (b_bits != NULL)\n\t\tif (!acl_exclude(&bits, &src->ptrs[index].values, b_bits))\n\t\t\treturn 0;\n\n\trc = acl_add_ptr(context, dst, src->ptrs[index].ptr, &bits);\n\tif (rc < 0)\n\t\treturn rc;\n\treturn 1;\n}\n\n/*\n * Fill in gaps in ptrs list with the ptr at the end of the list\n */\nstatic void\nacl_compact_node_ptrs(struct rte_acl_node *node_a)\n{\n\tuint32_t n;\n\tint min_add = node_a->min_add;\n\n\twhile (node_a->num_ptrs > 0 &&\n\t\t\tnode_a->ptrs[node_a->num_ptrs - 1].ptr == NULL)\n\t\tnode_a->num_ptrs--;\n\n\tfor (n = min_add; n + 1 < node_a->num_ptrs; n++) {\n\n\t\t/* if this entry is empty */\n\t\tif (node_a->ptrs[n].ptr == NULL) {\n\n\t\t\t/* move the last pointer to this entry */\n\t\t\tacl_include(&node_a->ptrs[n].values,\n\t\t\t\t&node_a->ptrs[node_a->num_ptrs - 1].values,\n\t\t\t\t0);\n\t\t\tnode_a->ptrs[n].ptr =\n\t\t\t\tnode_a->ptrs[node_a->num_ptrs - 1].ptr;\n\n\t\t\t/*\n\t\t\t * mark the end as empty and adjust the number\n\t\t\t * of used pointer enum_tries\n\t\t\t */\n\t\t\tnode_a->ptrs[node_a->num_ptrs - 1].ptr = NULL;\n\t\t\twhile (node_a->num_ptrs > 0 &&\n\t\t\t\tnode_a->ptrs[node_a->num_ptrs - 1].ptr == NULL)\n\t\t\t\tnode_a->num_ptrs--;\n\t\t}\n\t}\n}\n\nstatic int\nacl_resolve_leaf(struct acl_build_context *context,\n\tstruct rte_acl_node *node_a,\n\tstruct rte_acl_node *node_b,\n\tstruct rte_acl_node **node_c)\n{\n\tuint32_t n;\n\tint combined_priority = ACL_PRIORITY_EQUAL;\n\n\tfor (n = 0; n < context->cfg.num_categories; n++) {\n\t\tif (node_a->mrt->priority[n] != node_b->mrt->priority[n]) {\n\t\t\tcombined_priority |= (node_a->mrt->priority[n] >\n\t\t\t\tnode_b->mrt->priority[n]) ?\n\t\t\t\tACL_PRIORITY_NODE_A : ACL_PRIORITY_NODE_B;\n\t\t}\n\t}\n\n\t/*\n\t * if node a is higher or equal priority for all categories,\n\t * then return node_a.\n\t */\n\tif (combined_priority == ACL_PRIORITY_NODE_A ||\n\t\t\tcombined_priority == ACL_PRIORITY_EQUAL) {\n\t\t*node_c = node_a;\n\t\treturn 0;\n\t}\n\n\t/*\n\t * if node b is higher or equal priority for all categories,\n\t * then return node_b.\n\t */\n\tif (combined_priority == ACL_PRIORITY_NODE_B) {\n\t\t*node_c = node_b;\n\t\treturn 0;\n\t}\n\n\t/*\n\t * mixed priorities - create a new node with the highest priority\n\t * for each category.\n\t */\n\n\t/* force new duplication. */\n\tnode_a->next = NULL;\n\n\t*node_c = acl_dup_node(context, node_a);\n\tfor (n = 0; n < context->cfg.num_categories; n++) {\n\t\tif ((*node_c)->mrt->priority[n] < node_b->mrt->priority[n]) {\n\t\t\t(*node_c)->mrt->priority[n] = node_b->mrt->priority[n];\n\t\t\t(*node_c)->mrt->results[n] = node_b->mrt->results[n];\n\t\t}\n\t}\n\treturn 0;\n}\n\n/*\n * Merge nodes A and B together,\n * returns a node that is the path for the intersection\n *\n * If match node (leaf on trie)\n *\tFor each category\n *\t\treturn node = highest priority result\n *\n * Create C as a duplicate of A to point to child intersections\n * If any pointers in C intersect with any in B\n *\tFor each intersection\n *\t\tmerge children\n *\t\tremove intersection from C pointer\n *\t\tadd a pointer from C to child intersection node\n * Compact the pointers in A and B\n * Copy any B pointers that are outside of the intersection to C\n * If C has no references to the B trie\n * free C and return A\n * Else If C has no references to the A trie\n * free C and return B\n * Else\n * return C\n */\nstatic int\nacl_merge_trie(struct acl_build_context *context,\n\tstruct rte_acl_node *node_a, struct rte_acl_node *node_b,\n\tuint32_t level, struct rte_acl_node **return_c)\n{\n\tuint32_t n, m, ptrs_c, ptrs_b;\n\tuint32_t min_add_c, min_add_b;\n\tint node_intersect_type;\n\tstruct rte_acl_bitset node_intersect;\n\tstruct rte_acl_node *node_c;\n\tstruct rte_acl_node *node_a_next;\n\tint node_b_refs;\n\tint node_a_refs;\n\n\tnode_c = node_a;\n\tnode_a_next = node_a->next;\n\tmin_add_c = 0;\n\tmin_add_b = 0;\n\tnode_a_refs = node_a->num_ptrs;\n\tnode_b_refs = 0;\n\tnode_intersect_type = 0;\n\n\t/* Resolve leaf nodes (matches) */\n\tif (node_a->match_flag != 0) {\n\t\tacl_resolve_leaf(context, node_a, node_b, return_c);\n\t\treturn 0;\n\t}\n\n\t/*\n\t * Create node C as a copy of node A, and do: C = merge(A,B);\n\t * If node A can be used instead (A==C), then later we'll\n\t * destroy C and return A.\n\t */\n\tif (level > 0)\n\t\tnode_c = acl_dup_node(context, node_a);\n\n\t/*\n\t * If the two node transitions intersect then merge the transitions.\n\t * Check intersection for entire node (all pointers)\n\t */\n\tnode_intersect_type = acl_intersect_type(&node_c->values,\n\t\t&node_b->values,\n\t\t&node_intersect);\n\n\tif (node_intersect_type & ACL_INTERSECT) {\n\n\t\tmin_add_b = node_b->min_add;\n\t\tnode_b->min_add = node_b->num_ptrs;\n\t\tptrs_b = node_b->num_ptrs;\n\n\t\tmin_add_c = node_c->min_add;\n\t\tnode_c->min_add = node_c->num_ptrs;\n\t\tptrs_c = node_c->num_ptrs;\n\n\t\tfor (n = 0; n < ptrs_c; n++) {\n\t\t\tif (node_c->ptrs[n].ptr == NULL) {\n\t\t\t\tnode_a_refs--;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\tnode_c->ptrs[n].ptr->next = NULL;\n\t\t\tfor (m = 0; m < ptrs_b; m++) {\n\n\t\t\t\tstruct rte_acl_bitset child_intersect;\n\t\t\t\tint child_intersect_type;\n\t\t\t\tstruct rte_acl_node *child_node_c = NULL;\n\n\t\t\t\tif (node_b->ptrs[m].ptr == NULL ||\n\t\t\t\t\t\tnode_c->ptrs[n].ptr ==\n\t\t\t\t\t\tnode_b->ptrs[m].ptr)\n\t\t\t\t\t\tcontinue;\n\n\t\t\t\tchild_intersect_type = acl_intersect_type(\n\t\t\t\t\t&node_c->ptrs[n].values,\n\t\t\t\t\t&node_b->ptrs[m].values,\n\t\t\t\t\t&child_intersect);\n\n\t\t\t\tif ((child_intersect_type & ACL_INTERSECT) !=\n\t\t\t\t\t\t0) {\n\t\t\t\t\tif (acl_merge_trie(context,\n\t\t\t\t\t\t\tnode_c->ptrs[n].ptr,\n\t\t\t\t\t\t\tnode_b->ptrs[m].ptr,\n\t\t\t\t\t\t\tlevel + 1,\n\t\t\t\t\t\t\t&child_node_c))\n\t\t\t\t\t\treturn 1;\n\n\t\t\t\t\tif (child_node_c != NULL &&\n\t\t\t\t\t\t\tchild_node_c !=\n\t\t\t\t\t\t\tnode_c->ptrs[n].ptr) {\n\n\t\t\t\t\t\tnode_b_refs++;\n\n\t\t\t\t\t\t/*\n\t\t\t\t\t\t * Added link from C to\n\t\t\t\t\t\t * child_C for all transitions\n\t\t\t\t\t\t * in the intersection.\n\t\t\t\t\t\t */\n\t\t\t\t\t\tacl_add_ptr(context, node_c,\n\t\t\t\t\t\t\tchild_node_c,\n\t\t\t\t\t\t\t&child_intersect);\n\n\t\t\t\t\t\t/*\n\t\t\t\t\t\t * inc refs if pointer is not\n\t\t\t\t\t\t * to node b.\n\t\t\t\t\t\t */\n\t\t\t\t\t\tnode_a_refs += (child_node_c !=\n\t\t\t\t\t\t\tnode_b->ptrs[m].ptr);\n\n\t\t\t\t\t\t/*\n\t\t\t\t\t\t * Remove intersection from C\n\t\t\t\t\t\t * pointer.\n\t\t\t\t\t\t */\n\t\t\t\t\t\tif (!acl_exclude(\n\t\t\t\t\t\t\t&node_c->ptrs[n].values,\n\t\t\t\t\t\t\t&node_c->ptrs[n].values,\n\t\t\t\t\t\t\t&child_intersect)) {\n\t\t\t\t\t\t\tacl_deref_ptr(context,\n\t\t\t\t\t\t\t\tnode_c, n);\n\t\t\t\t\t\t\tnode_c->ptrs[n].ptr =\n\t\t\t\t\t\t\t\tNULL;\n\t\t\t\t\t\t\tnode_a_refs--;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* Compact pointers */\n\t\tnode_c->min_add = min_add_c;\n\t\tacl_compact_node_ptrs(node_c);\n\t\tnode_b->min_add = min_add_b;\n\t\tacl_compact_node_ptrs(node_b);\n\t}\n\n\t/*\n\t * Copy pointers outside of the intersection from B to C\n\t */\n\tif ((node_intersect_type & ACL_INTERSECT_B) != 0) {\n\t\tnode_b_refs++;\n\t\tfor (m = 0; m < node_b->num_ptrs; m++)\n\t\t\tif (node_b->ptrs[m].ptr != NULL)\n\t\t\t\tacl_copy_ptr(context, node_c,\n\t\t\t\t\tnode_b, m, &node_intersect);\n\t}\n\n\t/*\n\t * Free node C if top of trie is contained in A or B\n\t * if node C is a duplicate of node A &&\n\t * node C was not an existing duplicate\n\t */\n\tif (node_c != node_a && node_c != node_a_next) {\n\n\t\t/*\n\t\t * if the intersection has no references to the\n\t\t * B side, then it is contained in A\n\t\t */\n\t\tif (node_b_refs == 0) {\n\t\t\tacl_free_node(context, node_c);\n\t\t\tnode_c = node_a;\n\t\t} else {\n\t\t\t/*\n\t\t\t * if the intersection has no references to the\n\t\t\t * A side, then it is contained in B.\n\t\t\t */\n\t\t\tif (node_a_refs == 0) {\n\t\t\t\tacl_free_node(context, node_c);\n\t\t\t\tnode_c = node_b;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (return_c != NULL)\n\t\t*return_c = node_c;\n\n\tif (level == 0)\n\t\tacl_free_node(context, node_b);\n\n\treturn 0;\n}\n\n/*\n * Reset current runtime fields before next build:\n * - free allocated RT memory.\n * - reset all RT related fields to zero.\n */\nstatic void\nacl_build_reset(struct rte_acl_ctx *ctx)\n{\n\trte_free(ctx->mem);\n\tmemset(&ctx->num_categories, 0,\n\t\tsizeof(*ctx) - offsetof(struct rte_acl_ctx, num_categories));\n}\n\nstatic void\nacl_gen_range(struct acl_build_context *context,\n\tconst uint8_t *hi, const uint8_t *lo, int size, int level,\n\tstruct rte_acl_node *root, struct rte_acl_node *end)\n{\n\tstruct rte_acl_node *node, *prev;\n\tuint32_t n;\n\n\tprev = root;\n\tfor (n = size - 1; n > 0; n--) {\n\t\tnode = acl_alloc_node(context, level++);\n\t\tacl_add_ptr_range(context, prev, node, lo[n], hi[n]);\n\t\tprev = node;\n\t}\n\tacl_add_ptr_range(context, prev, end, lo[0], hi[0]);\n}\n\nstatic struct rte_acl_node *\nacl_gen_range_trie(struct acl_build_context *context,\n\tconst void *min, const void *max,\n\tint size, int level, struct rte_acl_node **pend)\n{\n\tint32_t n;\n\tstruct rte_acl_node *root;\n\tconst uint8_t *lo = (const uint8_t *)min;\n\tconst uint8_t *hi = (const uint8_t *)max;\n\n\t*pend = acl_alloc_node(context, level+size);\n\troot = acl_alloc_node(context, level++);\n\n\tif (lo[size - 1] == hi[size - 1]) {\n\t\tacl_gen_range(context, hi, lo, size, level, root, *pend);\n\t} else {\n\t\tuint8_t limit_lo[64];\n\t\tuint8_t limit_hi[64];\n\t\tuint8_t hi_ff = UINT8_MAX;\n\t\tuint8_t lo_00 = 0;\n\n\t\tmemset(limit_lo, 0, RTE_DIM(limit_lo));\n\t\tmemset(limit_hi, UINT8_MAX, RTE_DIM(limit_hi));\n\n\t\tfor (n = size - 2; n >= 0; n--) {\n\t\t\thi_ff = (uint8_t)(hi_ff & hi[n]);\n\t\t\tlo_00 = (uint8_t)(lo_00 | lo[n]);\n\t\t}\n\n\t\tif (hi_ff != UINT8_MAX) {\n\t\t\tlimit_lo[size - 1] = hi[size - 1];\n\t\t\tacl_gen_range(context, hi, limit_lo, size, level,\n\t\t\t\troot, *pend);\n\t\t}\n\n\t\tif (lo_00 != 0) {\n\t\t\tlimit_hi[size - 1] = lo[size - 1];\n\t\t\tacl_gen_range(context, limit_hi, lo, size, level,\n\t\t\t\troot, *pend);\n\t\t}\n\n\t\tif (hi[size - 1] - lo[size - 1] > 1 ||\n\t\t\t\tlo_00 == 0 ||\n\t\t\t\thi_ff == UINT8_MAX) {\n\t\t\tlimit_lo[size-1] = (uint8_t)(lo[size-1] + (lo_00 != 0));\n\t\t\tlimit_hi[size-1] = (uint8_t)(hi[size-1] -\n\t\t\t\t(hi_ff != UINT8_MAX));\n\t\t\tacl_gen_range(context, limit_hi, limit_lo, size,\n\t\t\t\tlevel, root, *pend);\n\t\t}\n\t}\n\treturn root;\n}\n\nstatic struct rte_acl_node *\nacl_gen_mask_trie(struct acl_build_context *context,\n\tconst void *value, const void *mask,\n\tint size, int level, struct rte_acl_node **pend)\n{\n\tint32_t n;\n\tstruct rte_acl_node *root;\n\tstruct rte_acl_node *node, *prev;\n\tstruct rte_acl_bitset bits;\n\tconst uint8_t *val = (const uint8_t *)value;\n\tconst uint8_t *msk = (const uint8_t *)mask;\n\n\troot = acl_alloc_node(context, level++);\n\tprev = root;\n\n\tfor (n = size - 1; n >= 0; n--) {\n\t\tnode = acl_alloc_node(context, level++);\n\t\tacl_gen_mask(&bits, val[n] & msk[n], msk[n]);\n\t\tacl_add_ptr(context, prev, node, &bits);\n\t\tprev = node;\n\t}\n\n\t*pend = prev;\n\treturn root;\n}\n\nstatic struct rte_acl_node *\nbuild_trie(struct acl_build_context *context, struct rte_acl_build_rule *head,\n\tstruct rte_acl_build_rule **last, uint32_t *count)\n{\n\tuint32_t n, m;\n\tint field_index, node_count;\n\tstruct rte_acl_node *trie;\n\tstruct rte_acl_build_rule *prev, *rule;\n\tstruct rte_acl_node *end, *merge, *root, *end_prev;\n\tconst struct rte_acl_field *fld;\n\n\tprev = head;\n\trule = head;\n\t*last = prev;\n\n\ttrie = acl_alloc_node(context, 0);\n\n\twhile (rule != NULL) {\n\n\t\troot = acl_alloc_node(context, 0);\n\n\t\troot->ref_count = 1;\n\t\tend = root;\n\n\t\tfor (n = 0; n < rule->config->num_fields; n++) {\n\n\t\t\tfield_index = rule->config->defs[n].field_index;\n\t\t\tfld = rule->f->field + field_index;\n\t\t\tend_prev = end;\n\n\t\t\t/* build a mini-trie for this field */\n\t\t\tswitch (rule->config->defs[n].type) {\n\n\t\t\tcase RTE_ACL_FIELD_TYPE_BITMASK:\n\t\t\t\tmerge = acl_gen_mask_trie(context,\n\t\t\t\t\t&fld->value,\n\t\t\t\t\t&fld->mask_range,\n\t\t\t\t\trule->config->defs[n].size,\n\t\t\t\t\tend->level + 1,\n\t\t\t\t\t&end);\n\t\t\t\tbreak;\n\n\t\t\tcase RTE_ACL_FIELD_TYPE_MASK:\n\t\t\t{\n\t\t\t\t/*\n\t\t\t\t * set msb for the size of the field and\n\t\t\t\t * all higher bits.\n\t\t\t\t */\n\t\t\t\tuint64_t mask;\n\t\t\t\tmask = RTE_ACL_MASKLEN_TO_BITMASK(\n\t\t\t\t\tfld->mask_range.u32,\n\t\t\t\t\trule->config->defs[n].size);\n\n\t\t\t\t/* gen a mini-trie for this field */\n\t\t\t\tmerge = acl_gen_mask_trie(context,\n\t\t\t\t\t&fld->value,\n\t\t\t\t\t(char *)&mask,\n\t\t\t\t\trule->config->defs[n].size,\n\t\t\t\t\tend->level + 1,\n\t\t\t\t\t&end);\n\t\t\t}\n\t\t\tbreak;\n\n\t\t\tcase RTE_ACL_FIELD_TYPE_RANGE:\n\t\t\t\tmerge = acl_gen_range_trie(context,\n\t\t\t\t\t&rule->f->field[field_index].value,\n\t\t\t\t\t&rule->f->field[field_index].mask_range,\n\t\t\t\t\trule->config->defs[n].size,\n\t\t\t\t\tend->level + 1,\n\t\t\t\t\t&end);\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\tRTE_LOG(ERR, ACL,\n\t\t\t\t\t\"Error in rule[%u] type - %hhu\\n\",\n\t\t\t\t\trule->f->data.userdata,\n\t\t\t\t\trule->config->defs[n].type);\n\t\t\t\treturn NULL;\n\t\t\t}\n\n\t\t\t/* merge this field on to the end of the rule */\n\t\t\tif (acl_merge_trie(context, end_prev, merge, 0,\n\t\t\t\t\tNULL) != 0) {\n\t\t\t\treturn NULL;\n\t\t\t}\n\t\t}\n\n\t\tend->match_flag = ++context->num_build_rules;\n\n\t\t/*\n\t\t * Setup the results for this rule.\n\t\t * The result and priority of each category.\n\t\t */\n\t\tif (end->mrt == NULL)\n\t\t\tend->mrt = acl_build_alloc(context, 1,\n\t\t\t\tsizeof(*end->mrt));\n\n\t\tfor (m = context->cfg.num_categories; 0 != m--; ) {\n\t\t\tif (rule->f->data.category_mask & (1 << m)) {\n\t\t\t\tend->mrt->results[m] = rule->f->data.userdata;\n\t\t\t\tend->mrt->priority[m] = rule->f->data.priority;\n\t\t\t} else {\n\t\t\t\tend->mrt->results[m] = 0;\n\t\t\t\tend->mrt->priority[m] = 0;\n\t\t\t}\n\t\t}\n\n\t\tnode_count = context->num_nodes;\n\t\t(*count)++;\n\n\t\t/* merge this rule into the trie */\n\t\tif (acl_merge_trie(context, trie, root, 0, NULL))\n\t\t\treturn NULL;\n\n\t\tnode_count = context->num_nodes - node_count;\n\t\tif (node_count > context->cur_node_max) {\n\t\t\t*last = prev;\n\t\t\treturn trie;\n\t\t}\n\n\t\tprev = rule;\n\t\trule = rule->next;\n\t}\n\n\t*last = NULL;\n\treturn trie;\n}\n\nstatic void\nacl_calc_wildness(struct rte_acl_build_rule *head,\n\tconst struct rte_acl_config *config)\n{\n\tuint32_t n;\n\tstruct rte_acl_build_rule *rule;\n\n\tfor (rule = head; rule != NULL; rule = rule->next) {\n\n\t\tfor (n = 0; n < config->num_fields; n++) {\n\n\t\t\tdouble wild = 0;\n\t\t\tuint32_t bit_len = CHAR_BIT * config->defs[n].size;\n\t\t\tuint64_t msk_val = RTE_LEN2MASK(bit_len,\n\t\t\t\ttypeof(msk_val));\n\t\t\tdouble size = bit_len;\n\t\t\tint field_index = config->defs[n].field_index;\n\t\t\tconst struct rte_acl_field *fld = rule->f->field +\n\t\t\t\tfield_index;\n\n\t\t\tswitch (rule->config->defs[n].type) {\n\t\t\tcase RTE_ACL_FIELD_TYPE_BITMASK:\n\t\t\t\twild = (size - __builtin_popcountll(\n\t\t\t\t\tfld->mask_range.u64 & msk_val)) /\n\t\t\t\t\tsize;\n\t\t\t\tbreak;\n\n\t\t\tcase RTE_ACL_FIELD_TYPE_MASK:\n\t\t\t\twild = (size - fld->mask_range.u32) / size;\n\t\t\t\tbreak;\n\n\t\t\tcase RTE_ACL_FIELD_TYPE_RANGE:\n\t\t\t\twild = (fld->mask_range.u64 & msk_val) -\n\t\t\t\t\t(fld->value.u64 & msk_val);\n\t\t\t\twild = wild / msk_val;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\trule->wildness[field_index] = (uint32_t)(wild * 100);\n\t\t}\n\t}\n}\n\nstatic void\nacl_rule_stats(struct rte_acl_build_rule *head, struct rte_acl_config *config)\n{\n\tstruct rte_acl_build_rule *rule;\n\tuint32_t n, m, fields_deactivated = 0;\n\tuint32_t start = 0, deactivate = 0;\n\tint tally[RTE_ACL_MAX_LEVELS][TALLY_NUM];\n\n\tmemset(tally, 0, sizeof(tally));\n\n\tfor (rule = head; rule != NULL; rule = rule->next) {\n\n\t\tfor (n = 0; n < config->num_fields; n++) {\n\t\t\tuint32_t field_index = config->defs[n].field_index;\n\n\t\t\ttally[n][TALLY_0]++;\n\t\t\tfor (m = 1; m < RTE_DIM(wild_limits); m++) {\n\t\t\t\tif (rule->wildness[field_index] >=\n\t\t\t\t\t\twild_limits[m])\n\t\t\t\t\ttally[n][m]++;\n\t\t\t}\n\t\t}\n\n\t\tfor (n = config->num_fields - 1; n > 0; n--) {\n\t\t\tuint32_t field_index = config->defs[n].field_index;\n\n\t\t\tif (rule->wildness[field_index] == 100)\n\t\t\t\ttally[n][TALLY_DEPTH]++;\n\t\t\telse\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\t/*\n\t * Look for any field that is always wild and drop it from the config\n\t * Only deactivate if all fields for a given input loop are deactivated.\n\t */\n\tfor (n = 1; n < config->num_fields; n++) {\n\t\tif (config->defs[n].input_index !=\n\t\t\t\tconfig->defs[n - 1].input_index) {\n\t\t\tfor (m = start; m < n; m++)\n\t\t\t\ttally[m][TALLY_DEACTIVATED] = deactivate;\n\t\t\tfields_deactivated += deactivate;\n\t\t\tstart = n;\n\t\t\tdeactivate = 1;\n\t\t}\n\n\t\t/* if the field is not always completely wild */\n\t\tif (tally[n][TALLY_100] != tally[n][TALLY_0])\n\t\t\tdeactivate = 0;\n\t}\n\n\tfor (m = start; m < n; m++)\n\t\ttally[m][TALLY_DEACTIVATED] = deactivate;\n\n\tfields_deactivated += deactivate;\n\n\t/* remove deactivated fields */\n\tif (fields_deactivated) {\n\t\tuint32_t k, l = 0;\n\n\t\tfor (k = 0; k < config->num_fields; k++) {\n\t\t\tif (tally[k][TALLY_DEACTIVATED] == 0) {\n\t\t\t\tmemmove(&tally[l][0], &tally[k][0],\n\t\t\t\t\tTALLY_NUM * sizeof(tally[0][0]));\n\t\t\t\tmemmove(&config->defs[l++],\n\t\t\t\t\t&config->defs[k],\n\t\t\t\t\tsizeof(struct rte_acl_field_def));\n\t\t\t}\n\t\t}\n\t\tconfig->num_fields = l;\n\t}\n}\n\nstatic int\nrule_cmp_wildness(struct rte_acl_build_rule *r1, struct rte_acl_build_rule *r2)\n{\n\tuint32_t n;\n\n\tfor (n = 1; n < r1->config->num_fields; n++) {\n\t\tint field_index = r1->config->defs[n].field_index;\n\n\t\tif (r1->wildness[field_index] != r2->wildness[field_index])\n\t\t\treturn (r1->wildness[field_index] -\n\t\t\t\tr2->wildness[field_index]);\n\t}\n\treturn 0;\n}\n\n/*\n * Sort list of rules based on the rules wildness.\n */\nstatic struct rte_acl_build_rule *\nsort_rules(struct rte_acl_build_rule *head)\n{\n\tstruct rte_acl_build_rule *new_head;\n\tstruct rte_acl_build_rule *l, *r, **p;\n\n\tnew_head = NULL;\n\twhile (head != NULL) {\n\n\t\t/* remove element from the head of the old list. */\n\t\tr = head;\n\t\thead = r->next;\n\t\tr->next = NULL;\n\n\t\t/* walk through new sorted list to find a proper place. */\n\t\tfor (p = &new_head;\n\t\t\t\t(l = *p) != NULL &&\n\t\t\t\trule_cmp_wildness(l, r) >= 0;\n\t\t\t\tp = &l->next)\n\t\t\t;\n\n\t\t/* insert element into the new sorted list. */\n\t\tr->next = *p;\n\t\t*p = r;\n\t}\n\n\treturn new_head;\n}\n\nstatic uint32_t\nacl_build_index(const struct rte_acl_config *config, uint32_t *data_index)\n{\n\tuint32_t n, m;\n\tint32_t last_header;\n\n\tm = 0;\n\tlast_header = -1;\n\n\tfor (n = 0; n < config->num_fields; n++) {\n\t\tif (last_header != config->defs[n].input_index) {\n\t\t\tlast_header = config->defs[n].input_index;\n\t\t\tdata_index[m++] = config->defs[n].offset;\n\t\t}\n\t}\n\n\treturn m;\n}\n\nstatic struct rte_acl_build_rule *\nbuild_one_trie(struct acl_build_context *context,\n\tstruct rte_acl_build_rule *rule_sets[RTE_ACL_MAX_TRIES],\n\tuint32_t n, int32_t node_max)\n{\n\tstruct rte_acl_build_rule *last;\n\tstruct rte_acl_config *config;\n\n\tconfig = rule_sets[n]->config;\n\n\tacl_rule_stats(rule_sets[n], config);\n\trule_sets[n] = sort_rules(rule_sets[n]);\n\n\tcontext->tries[n].type = RTE_ACL_FULL_TRIE;\n\tcontext->tries[n].count = 0;\n\n\tcontext->tries[n].num_data_indexes = acl_build_index(config,\n\t\tcontext->data_indexes[n]);\n\tcontext->tries[n].data_index = context->data_indexes[n];\n\n\tcontext->cur_node_max = node_max;\n\n\tcontext->bld_tries[n].trie = build_trie(context, rule_sets[n],\n\t\t&last, &context->tries[n].count);\n\n\treturn last;\n}\n\nstatic int\nacl_build_tries(struct acl_build_context *context,\n\tstruct rte_acl_build_rule *head)\n{\n\tuint32_t n, num_tries;\n\tstruct rte_acl_config *config;\n\tstruct rte_acl_build_rule *last;\n\tstruct rte_acl_build_rule *rule_sets[RTE_ACL_MAX_TRIES];\n\n\tconfig = head->config;\n\trule_sets[0] = head;\n\n\t/* initialize tries */\n\tfor (n = 0; n < RTE_DIM(context->tries); n++) {\n\t\tcontext->tries[n].type = RTE_ACL_UNUSED_TRIE;\n\t\tcontext->bld_tries[n].trie = NULL;\n\t\tcontext->tries[n].count = 0;\n\t}\n\n\tcontext->tries[0].type = RTE_ACL_FULL_TRIE;\n\n\t/* calc wildness of each field of each rule */\n\tacl_calc_wildness(head, config);\n\n\tfor (n = 0;; n = num_tries) {\n\n\t\tnum_tries = n + 1;\n\n\t\tlast = build_one_trie(context, rule_sets, n, context->node_max);\n\t\tif (context->bld_tries[n].trie == NULL) {\n\t\t\tRTE_LOG(ERR, ACL, \"Build of %u-th trie failed\\n\", n);\n\t\t\treturn -ENOMEM;\n\t\t}\n\n\t\t/* Build of the last trie completed. */\n\t\tif (last == NULL)\n\t\t\tbreak;\n\n\t\tif (num_tries == RTE_DIM(context->tries)) {\n\t\t\tRTE_LOG(ERR, ACL,\n\t\t\t\t\"Exceeded max number of tries: %u\\n\",\n\t\t\t\tnum_tries);\n\t\t\treturn -ENOMEM;\n\t\t}\n\n\t\t/* Trie is getting too big, split remaining rule set. */\n\t\trule_sets[num_tries] = last->next;\n\t\tlast->next = NULL;\n\t\tacl_free_node(context, context->bld_tries[n].trie);\n\n\t\t/* Create a new copy of config for remaining rules. */\n\t\tconfig = acl_build_alloc(context, 1, sizeof(*config));\n\t\tmemcpy(config, rule_sets[n]->config, sizeof(*config));\n\n\t\t/* Make remaining rules use new config. */\n\t\tfor (head = rule_sets[num_tries]; head != NULL;\n\t\t\t\thead = head->next)\n\t\t\thead->config = config;\n\n\t\t/*\n\t\t * Rebuild the trie for the reduced rule-set.\n\t\t * Don't try to split it any further.\n\t\t */\n\t\tlast = build_one_trie(context, rule_sets, n, INT32_MAX);\n\t\tif (context->bld_tries[n].trie == NULL || last != NULL) {\n\t\t\tRTE_LOG(ERR, ACL, \"Build of %u-th trie failed\\n\", n);\n\t\t\treturn -ENOMEM;\n\t\t}\n\n\t}\n\n\tcontext->num_tries = num_tries;\n\treturn 0;\n}\n\nstatic void\nacl_build_log(const struct acl_build_context *ctx)\n{\n\tuint32_t n;\n\n\tRTE_LOG(DEBUG, ACL, \"Build phase for ACL \\\"%s\\\":\\n\"\n\t\t\"node limit for tree split: %u\\n\"\n\t\t\"nodes created: %u\\n\"\n\t\t\"memory consumed: %zu\\n\",\n\t\tctx->acx->name,\n\t\tctx->node_max,\n\t\tctx->num_nodes,\n\t\tctx->pool.alloc);\n\n\tfor (n = 0; n < RTE_DIM(ctx->tries); n++) {\n\t\tif (ctx->tries[n].count != 0)\n\t\t\tRTE_LOG(DEBUG, ACL,\n\t\t\t\t\"trie %u: number of rules: %u, indexes: %u\\n\",\n\t\t\t\tn, ctx->tries[n].count,\n\t\t\t\tctx->tries[n].num_data_indexes);\n\t}\n}\n\nstatic int\nacl_build_rules(struct acl_build_context *bcx)\n{\n\tstruct rte_acl_build_rule *br, *head;\n\tconst struct rte_acl_rule *rule;\n\tuint32_t *wp;\n\tuint32_t fn, i, n, num;\n\tsize_t ofs, sz;\n\n\tfn = bcx->cfg.num_fields;\n\tn = bcx->acx->num_rules;\n\tofs = n * sizeof(*br);\n\tsz = ofs + n * fn * sizeof(*wp);\n\n\tbr = tb_alloc(&bcx->pool, sz);\n\n\twp = (uint32_t *)((uintptr_t)br + ofs);\n\tnum = 0;\n\thead = NULL;\n\n\tfor (i = 0; i != n; i++) {\n\t\trule = (const struct rte_acl_rule *)\n\t\t\t((uintptr_t)bcx->acx->rules + bcx->acx->rule_sz * i);\n\t\tif ((rule->data.category_mask & bcx->category_mask) != 0) {\n\t\t\tbr[num].next = head;\n\t\t\tbr[num].config = &bcx->cfg;\n\t\t\tbr[num].f = rule;\n\t\t\tbr[num].wildness = wp;\n\t\t\twp += fn;\n\t\t\thead = br + num;\n\t\t\tnum++;\n\t\t}\n\t}\n\n\tbcx->num_rules = num;\n\tbcx->build_rules = head;\n\n\treturn 0;\n}\n\n/*\n * Copy data_indexes for each trie into RT location.\n */\nstatic void\nacl_set_data_indexes(struct rte_acl_ctx *ctx)\n{\n\tuint32_t i, n, ofs;\n\n\tofs = 0;\n\tfor (i = 0; i != ctx->num_tries; i++) {\n\t\tn = ctx->trie[i].num_data_indexes;\n\t\tmemcpy(ctx->data_indexes + ofs, ctx->trie[i].data_index,\n\t\t\tn * sizeof(ctx->data_indexes[0]));\n\t\tctx->trie[i].data_index = ctx->data_indexes + ofs;\n\t\tofs += RTE_ACL_MAX_FIELDS;\n\t}\n}\n\n/*\n * Internal routine, performs 'build' phase of trie generation:\n * - setups build context.\n * - analizes given set of rules.\n * - builds internal tree(s).\n */\nstatic int\nacl_bld(struct acl_build_context *bcx, struct rte_acl_ctx *ctx,\n\tconst struct rte_acl_config *cfg, uint32_t node_max)\n{\n\tint32_t rc;\n\n\t/* setup build context. */\n\tmemset(bcx, 0, sizeof(*bcx));\n\tbcx->acx = ctx;\n\tbcx->pool.alignment = ACL_POOL_ALIGN;\n\tbcx->pool.min_alloc = ACL_POOL_ALLOC_MIN;\n\tbcx->cfg = *cfg;\n\tbcx->category_mask = RTE_LEN2MASK(bcx->cfg.num_categories,\n\t\ttypeof(bcx->category_mask));\n\tbcx->node_max = node_max;\n\n\trc = sigsetjmp(bcx->pool.fail, 0);\n\n\t/* build phase runs out of memory. */\n\tif (rc != 0) {\n\t\tRTE_LOG(ERR, ACL,\n\t\t\t\"ACL context: %s, %s() failed with error code: %d\\n\",\n\t\t\tbcx->acx->name, __func__, rc);\n\t\treturn rc;\n\t}\n\n\t/* Create a build rules copy. */\n\trc = acl_build_rules(bcx);\n\tif (rc != 0)\n\t\treturn rc;\n\n\t/* No rules to build for that context+config */\n\tif (bcx->build_rules == NULL) {\n\t\trc = -EINVAL;\n\t} else {\n\t\t/* build internal trie representation. */\n\t\trc = acl_build_tries(bcx, bcx->build_rules);\n\t}\n\treturn rc;\n}\n\n/*\n * Check that parameters for acl_build() are valid.\n */\nstatic int\nacl_check_bld_param(struct rte_acl_ctx *ctx, const struct rte_acl_config *cfg)\n{\n\tstatic const size_t field_sizes[] = {\n\t\tsizeof(uint8_t), sizeof(uint16_t),\n\t\tsizeof(uint32_t), sizeof(uint64_t),\n\t};\n\n\tuint32_t i, j;\n\n\tif (ctx == NULL || cfg == NULL || cfg->num_categories == 0 ||\n\t\t\tcfg->num_categories > RTE_ACL_MAX_CATEGORIES ||\n\t\t\tcfg->num_fields == 0 ||\n\t\t\tcfg->num_fields > RTE_ACL_MAX_FIELDS)\n\t\treturn -EINVAL;\n\n\tfor (i = 0; i != cfg->num_fields; i++) {\n\t\tif (cfg->defs[i].type > RTE_ACL_FIELD_TYPE_BITMASK) {\n\t\t\tRTE_LOG(ERR, ACL,\n\t\t\t\"ACL context: %s, invalid type: %hhu for %u-th field\\n\",\n\t\t\tctx->name, cfg->defs[i].type, i);\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tfor (j = 0;\n\t\t\t\tj != RTE_DIM(field_sizes) &&\n\t\t\t\tcfg->defs[i].size != field_sizes[j];\n\t\t\t\tj++)\n\t\t\t;\n\n\t\tif (j == RTE_DIM(field_sizes)) {\n\t\t\tRTE_LOG(ERR, ACL,\n\t\t\t\"ACL context: %s, invalid size: %hhu for %u-th field\\n\",\n\t\t\tctx->name, cfg->defs[i].size, i);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nint\nrte_acl_build(struct rte_acl_ctx *ctx, const struct rte_acl_config *cfg)\n{\n\tint32_t rc;\n\tuint32_t n;\n\tsize_t max_size;\n\tstruct acl_build_context bcx;\n\n\trc = acl_check_bld_param(ctx, cfg);\n\tif (rc != 0)\n\t\treturn rc;\n\n\tacl_build_reset(ctx);\n\n\tif (cfg->max_size == 0) {\n\t\tn = NODE_MIN;\n\t\tmax_size = SIZE_MAX;\n\t} else {\n\t\tn = NODE_MAX;\n\t\tmax_size = cfg->max_size;\n\t}\n\n\tfor (rc = -ERANGE; n >= NODE_MIN && rc == -ERANGE; n /= 2) {\n\n\t\t/* perform build phase. */\n\t\trc = acl_bld(&bcx, ctx, cfg, n);\n\n\t\tif (rc == 0) {\n\t\t\t/* allocate and fill run-time structures. */\n\t\t\trc = rte_acl_gen(ctx, bcx.tries, bcx.bld_tries,\n\t\t\t\tbcx.num_tries, bcx.cfg.num_categories,\n\t\t\t\tRTE_ACL_MAX_FIELDS * RTE_DIM(bcx.tries) *\n\t\t\t\tsizeof(ctx->data_indexes[0]), max_size);\n\t\t\tif (rc == 0) {\n\t\t\t\t/* set data indexes. */\n\t\t\t\tacl_set_data_indexes(ctx);\n\n\t\t\t\t/* copy in build config. */\n\t\t\t\tctx->config = *cfg;\n\t\t\t}\n\t\t}\n\n\t\tacl_build_log(&bcx);\n\n\t\t/* cleanup after build. */\n\t\ttb_free_pool(&bcx.pool);\n\t}\n\n\treturn rc;\n}\n" }, { "path": "lib/librte_acl/acl_gen.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \"acl.h\"\n\n#define\tQRANGE_MIN\t((uint8_t)INT8_MIN)\n\n#define\tRTE_ACL_VERIFY(exp)\tdo { \\\n\tif (!(exp)) \\\n\t\trte_panic(\"line %d\\tassert \\\"\" #exp \"\\\" failed\\n\", __LINE__); \\\n} while (0)\n\nstruct acl_node_counters {\n\tint32_t match;\n\tint32_t match_used;\n\tint32_t single;\n\tint32_t quad;\n\tint32_t quad_vectors;\n\tint32_t dfa;\n\tint32_t dfa_gr64;\n};\n\nstruct rte_acl_indices {\n\tint32_t dfa_index;\n\tint32_t quad_index;\n\tint32_t single_index;\n\tint32_t match_index;\n\tint32_t match_start;\n};\n\nstatic void\nacl_gen_log_stats(const struct rte_acl_ctx *ctx,\n\tconst struct acl_node_counters *counts,\n\tconst struct rte_acl_indices *indices,\n\tsize_t max_size)\n{\n\tRTE_LOG(DEBUG, ACL, \"Gen phase for ACL \\\"%s\\\":\\n\"\n\t\t\"runtime memory footprint on socket %d:\\n\"\n\t\t\"single nodes/bytes used: %d/%zu\\n\"\n\t\t\"quad nodes/vectors/bytes used: %d/%d/%zu\\n\"\n\t\t\"DFA nodes/group64/bytes used: %d/%d/%zu\\n\"\n\t\t\"match nodes/bytes used: %d/%zu\\n\"\n\t\t\"total: %zu bytes\\n\"\n\t\t\"max limit: %zu bytes\\n\",\n\t\tctx->name, ctx->socket_id,\n\t\tcounts->single, counts->single * sizeof(uint64_t),\n\t\tcounts->quad, counts->quad_vectors,\n\t\t(indices->quad_index - indices->dfa_index) * sizeof(uint64_t),\n\t\tcounts->dfa, counts->dfa_gr64,\n\t\tindices->dfa_index * sizeof(uint64_t),\n\t\tcounts->match,\n\t\tcounts->match * sizeof(struct rte_acl_match_results),\n\t\tctx->mem_sz,\n\t\tmax_size);\n}\n\nstatic uint64_t\nacl_dfa_gen_idx(const struct rte_acl_node *node, uint32_t index)\n{\n\tuint64_t idx;\n\tuint32_t i;\n\n\tidx = 0;\n\tfor (i = 0; i != RTE_DIM(node->dfa_gr64); i++) {\n\t\tRTE_ACL_VERIFY(node->dfa_gr64[i] < RTE_ACL_DFA_GR64_NUM);\n\t\tRTE_ACL_VERIFY(node->dfa_gr64[i] < node->fanout);\n\t\tidx |= (i - node->dfa_gr64[i]) <<\n\t\t\t(6 + RTE_ACL_DFA_GR64_BIT * i);\n\t}\n\n\treturn idx << (CHAR_BIT * sizeof(index)) | index | node->node_type;\n}\n\nstatic void\nacl_dfa_fill_gr64(const struct rte_acl_node *node,\n\tconst uint64_t src[RTE_ACL_DFA_SIZE], uint64_t dst[RTE_ACL_DFA_SIZE])\n{\n\tuint32_t i;\n\n\tfor (i = 0; i != RTE_DIM(node->dfa_gr64); i++) {\n\t\tmemcpy(dst + node->dfa_gr64[i] * RTE_ACL_DFA_GR64_SIZE,\n\t\t\tsrc + i * RTE_ACL_DFA_GR64_SIZE,\n\t\t\tRTE_ACL_DFA_GR64_SIZE * sizeof(dst[0]));\n\t}\n}\n\nstatic uint32_t\nacl_dfa_count_gr64(const uint64_t array_ptr[RTE_ACL_DFA_SIZE],\n\tuint8_t gr64[RTE_ACL_DFA_GR64_NUM])\n{\n\tuint32_t i, j, k;\n\n\tk = 0;\n\tfor (i = 0; i != RTE_ACL_DFA_GR64_NUM; i++) {\n\t\tgr64[i] = i;\n\t\tfor (j = 0; j != i; j++) {\n\t\t\tif (memcmp(array_ptr + i * RTE_ACL_DFA_GR64_SIZE,\n\t\t\t\t\tarray_ptr + j * RTE_ACL_DFA_GR64_SIZE,\n\t\t\t\t\tRTE_ACL_DFA_GR64_SIZE *\n\t\t\t\t\tsizeof(array_ptr[0])) == 0)\n\t\t\t\tbreak;\n\t\t}\n\t\tgr64[i] = (j != i) ? gr64[j] : k++;\n\t}\n\n\treturn k;\n}\n\nstatic uint32_t\nacl_node_fill_dfa(const struct rte_acl_node *node,\n\tuint64_t dfa[RTE_ACL_DFA_SIZE], uint64_t no_match, int32_t resolved)\n{\n\tuint32_t n, x;\n\tuint32_t ranges, last_bit;\n\tstruct rte_acl_node *child;\n\tstruct rte_acl_bitset *bits;\n\n\tranges = 0;\n\tlast_bit = 0;\n\n\tfor (n = 0; n < RTE_ACL_DFA_SIZE; n++)\n\t\tdfa[n] = no_match;\n\n\tfor (x = 0; x < node->num_ptrs; x++) {\n\n\t\tchild = node->ptrs[x].ptr;\n\t\tif (child == NULL)\n\t\t\tcontinue;\n\n\t\tbits = &node->ptrs[x].values;\n\t\tfor (n = 0; n < RTE_ACL_DFA_SIZE; n++) {\n\n\t\t\tif (bits->bits[n / (sizeof(bits_t) * CHAR_BIT)] &\n\t\t\t\t(1 << (n % (sizeof(bits_t) * CHAR_BIT)))) {\n\n\t\t\t\tdfa[n] = resolved ? child->node_index : x;\n\t\t\t\tranges += (last_bit == 0);\n\t\t\t\tlast_bit = 1;\n\t\t\t} else {\n\t\t\t\tlast_bit = 0;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn ranges;\n}\n\n/*\n* Counts the number of groups of sequential bits that are\n* either 0 or 1, as specified by the zero_one parameter. This is used to\n* calculate the number of ranges in a node to see if it fits in a quad range\n* node.\n*/\nstatic int\nacl_count_sequential_groups(struct rte_acl_bitset *bits, int zero_one)\n{\n\tint n, ranges, last_bit;\n\n\tranges = 0;\n\tlast_bit = zero_one ^ 1;\n\n\tfor (n = QRANGE_MIN; n < UINT8_MAX + 1; n++) {\n\t\tif (bits->bits[n / (sizeof(bits_t) * 8)] &\n\t\t\t\t(1 << (n % (sizeof(bits_t) * 8)))) {\n\t\t\tif (zero_one == 1 && last_bit != 1)\n\t\t\t\tranges++;\n\t\t\tlast_bit = 1;\n\t\t} else {\n\t\t\tif (zero_one == 0 && last_bit != 0)\n\t\t\t\tranges++;\n\t\t\tlast_bit = 0;\n\t\t}\n\t}\n\tfor (n = 0; n < QRANGE_MIN; n++) {\n\t\tif (bits->bits[n / (sizeof(bits_t) * 8)] &\n\t\t\t\t(1 << (n % (sizeof(bits_t) * 8)))) {\n\t\t\tif (zero_one == 1 && last_bit != 1)\n\t\t\t\tranges++;\n\t\t\tlast_bit = 1;\n\t\t} else {\n\t\t\tif (zero_one == 0 && last_bit != 0)\n\t\t\t\tranges++;\n\t\t\tlast_bit = 0;\n\t\t}\n\t}\n\n\treturn ranges;\n}\n\n/*\n * Count number of ranges spanned by the node's pointers\n */\nstatic int\nacl_count_fanout(struct rte_acl_node *node)\n{\n\tuint32_t n;\n\tint ranges;\n\n\tif (node->fanout != 0)\n\t\treturn node->fanout;\n\n\tranges = acl_count_sequential_groups(&node->values, 0);\n\n\tfor (n = 0; n < node->num_ptrs; n++) {\n\t\tif (node->ptrs[n].ptr != NULL)\n\t\t\tranges += acl_count_sequential_groups(\n\t\t\t\t&node->ptrs[n].values, 1);\n\t}\n\n\tnode->fanout = ranges;\n\treturn node->fanout;\n}\n\n/*\n * Determine the type of nodes and count each type\n */\nstatic void\nacl_count_trie_types(struct acl_node_counters *counts,\n\tstruct rte_acl_node *node, uint64_t no_match, int force_dfa)\n{\n\tuint32_t n;\n\tint num_ptrs;\n\tuint64_t dfa[RTE_ACL_DFA_SIZE];\n\n\t/* skip if this node has been counted */\n\tif (node->node_type != (uint32_t)RTE_ACL_NODE_UNDEFINED)\n\t\treturn;\n\n\tif (node->match_flag != 0 || node->num_ptrs == 0) {\n\t\tcounts->match++;\n\t\tnode->node_type = RTE_ACL_NODE_MATCH;\n\t\treturn;\n\t}\n\n\tnum_ptrs = acl_count_fanout(node);\n\n\t/* Force type to dfa */\n\tif (force_dfa)\n\t\tnum_ptrs = RTE_ACL_DFA_SIZE;\n\n\t/* determine node type based on number of ranges */\n\tif (num_ptrs == 1) {\n\t\tcounts->single++;\n\t\tnode->node_type = RTE_ACL_NODE_SINGLE;\n\t} else if (num_ptrs <= RTE_ACL_QUAD_MAX) {\n\t\tcounts->quad++;\n\t\tcounts->quad_vectors += node->fanout;\n\t\tnode->node_type = RTE_ACL_NODE_QRANGE;\n\t} else {\n\t\tcounts->dfa++;\n\t\tnode->node_type = RTE_ACL_NODE_DFA;\n\t\tif (force_dfa != 0) {\n\t\t\t/* always expand to a max number of nodes. */\n\t\t\tfor (n = 0; n != RTE_DIM(node->dfa_gr64); n++)\n\t\t\t\tnode->dfa_gr64[n] = n;\n\t\t\tnode->fanout = n;\n\t\t} else {\n\t\t\tacl_node_fill_dfa(node, dfa, no_match, 0);\n\t\t\tnode->fanout = acl_dfa_count_gr64(dfa, node->dfa_gr64);\n\t\t}\n\t\tcounts->dfa_gr64 += node->fanout;\n\t}\n\n\t/*\n\t * recursively count the types of all children\n\t */\n\tfor (n = 0; n < node->num_ptrs; n++) {\n\t\tif (node->ptrs[n].ptr != NULL)\n\t\t\tacl_count_trie_types(counts, node->ptrs[n].ptr,\n\t\t\t\tno_match, 0);\n\t}\n}\n\nstatic void\nacl_add_ptrs(struct rte_acl_node *node, uint64_t *node_array, uint64_t no_match,\n\tint resolved)\n{\n\tuint32_t x;\n\tint32_t m;\n\tuint64_t *node_a, index, dfa[RTE_ACL_DFA_SIZE];\n\n\tacl_node_fill_dfa(node, dfa, no_match, resolved);\n\n\t/*\n\t * Rather than going from 0 to 256, the range count and\n\t * the layout are from 80-ff then 0-7f due to signed compare\n\t * for SSE (cmpgt).\n\t */\n\tif (node->node_type == RTE_ACL_NODE_QRANGE) {\n\n\t\tm = 0;\n\t\tnode_a = node_array;\n\t\tindex = dfa[QRANGE_MIN];\n\t\t*node_a++ = index;\n\n\t\tfor (x = QRANGE_MIN + 1; x < UINT8_MAX + 1; x++) {\n\t\t\tif (dfa[x] != index) {\n\t\t\t\tindex = dfa[x];\n\t\t\t\t*node_a++ = index;\n\t\t\t\tnode->transitions[m++] = (uint8_t)(x - 1);\n\t\t\t}\n\t\t}\n\n\t\tfor (x = 0; x < INT8_MAX + 1; x++) {\n\t\t\tif (dfa[x] != index) {\n\t\t\t\tindex = dfa[x];\n\t\t\t\t*node_a++ = index;\n\t\t\t\tnode->transitions[m++] = (uint8_t)(x - 1);\n\t\t\t}\n\t\t}\n\n\t\t/* fill unused locations with max value - nothing is greater */\n\t\tfor (; m < RTE_ACL_QUAD_SIZE; m++)\n\t\t\tnode->transitions[m] = INT8_MAX;\n\n\t\tRTE_ACL_VERIFY(m <= RTE_ACL_QUAD_SIZE);\n\n\t} else if (node->node_type == RTE_ACL_NODE_DFA && resolved) {\n\t\tacl_dfa_fill_gr64(node, dfa, node_array);\n\t}\n}\n\n/*\n * Routine that allocates space for this node and recursively calls\n * to allocate space for each child. Once all the children are allocated,\n * then resolve all transitions for this node.\n */\nstatic void\nacl_gen_node(struct rte_acl_node *node, uint64_t *node_array,\n\tuint64_t no_match, struct rte_acl_indices *index, int num_categories)\n{\n\tuint32_t n, sz, *qtrp;\n\tuint64_t *array_ptr;\n\tstruct rte_acl_match_results *match;\n\n\tif (node->node_index != RTE_ACL_NODE_UNDEFINED)\n\t\treturn;\n\n\tarray_ptr = NULL;\n\n\tswitch (node->node_type) {\n\tcase RTE_ACL_NODE_DFA:\n\t\tarray_ptr = &node_array[index->dfa_index];\n\t\tnode->node_index = acl_dfa_gen_idx(node, index->dfa_index);\n\t\tsz = node->fanout * RTE_ACL_DFA_GR64_SIZE;\n\t\tindex->dfa_index += sz;\n\t\tfor (n = 0; n < sz; n++)\n\t\t\tarray_ptr[n] = no_match;\n\t\tbreak;\n\tcase RTE_ACL_NODE_SINGLE:\n\t\tnode->node_index = RTE_ACL_QUAD_SINGLE | index->single_index |\n\t\t\tnode->node_type;\n\t\tarray_ptr = &node_array[index->single_index];\n\t\tindex->single_index += 1;\n\t\tarray_ptr[0] = no_match;\n\t\tbreak;\n\tcase RTE_ACL_NODE_QRANGE:\n\t\tarray_ptr = &node_array[index->quad_index];\n\t\tacl_add_ptrs(node, array_ptr, no_match, 0);\n\t\tqtrp = (uint32_t *)node->transitions;\n\t\tnode->node_index = qtrp[0];\n\t\tnode->node_index <<= sizeof(index->quad_index) * CHAR_BIT;\n\t\tnode->node_index |= index->quad_index | node->node_type;\n\t\tindex->quad_index += node->fanout;\n\t\tbreak;\n\tcase RTE_ACL_NODE_MATCH:\n\t\tmatch = ((struct rte_acl_match_results *)\n\t\t\t(node_array + index->match_start));\n\t\tfor (n = 0; n != RTE_DIM(match->results); n++)\n\t\t\tRTE_ACL_VERIFY(match->results[0] == 0);\n\t\tmemcpy(match + index->match_index, node->mrt,\n\t\t\tsizeof(*node->mrt));\n\t\tnode->node_index = index->match_index | node->node_type;\n\t\tindex->match_index += 1;\n\t\tbreak;\n\tcase RTE_ACL_NODE_UNDEFINED:\n\t\tRTE_ACL_VERIFY(node->node_type !=\n\t\t\t(uint32_t)RTE_ACL_NODE_UNDEFINED);\n\t\tbreak;\n\t}\n\n\t/* recursively allocate space for all children */\n\tfor (n = 0; n < node->num_ptrs; n++) {\n\t\tif (node->ptrs[n].ptr != NULL)\n\t\t\tacl_gen_node(node->ptrs[n].ptr,\n\t\t\t\tnode_array,\n\t\t\t\tno_match,\n\t\t\t\tindex,\n\t\t\t\tnum_categories);\n\t}\n\n\t/* All children are resolved, resolve this node's pointers */\n\tswitch (node->node_type) {\n\tcase RTE_ACL_NODE_DFA:\n\t\tacl_add_ptrs(node, array_ptr, no_match, 1);\n\t\tbreak;\n\tcase RTE_ACL_NODE_SINGLE:\n\t\tfor (n = 0; n < node->num_ptrs; n++) {\n\t\t\tif (node->ptrs[n].ptr != NULL)\n\t\t\t\tarray_ptr[0] = node->ptrs[n].ptr->node_index;\n\t\t}\n\t\tbreak;\n\tcase RTE_ACL_NODE_QRANGE:\n\t\tacl_add_ptrs(node, array_ptr, no_match, 1);\n\t\tbreak;\n\tcase RTE_ACL_NODE_MATCH:\n\t\tbreak;\n\tcase RTE_ACL_NODE_UNDEFINED:\n\t\tRTE_ACL_VERIFY(node->node_type !=\n\t\t\t(uint32_t)RTE_ACL_NODE_UNDEFINED);\n\t\tbreak;\n\t}\n}\n\nstatic void\nacl_calc_counts_indices(struct acl_node_counters *counts,\n\tstruct rte_acl_indices *indices,\n\tstruct rte_acl_bld_trie *node_bld_trie, uint32_t num_tries,\n\tuint64_t no_match)\n{\n\tuint32_t n;\n\n\tmemset(indices, 0, sizeof(*indices));\n\tmemset(counts, 0, sizeof(*counts));\n\n\t/* Get stats on nodes */\n\tfor (n = 0; n < num_tries; n++) {\n\t\tacl_count_trie_types(counts, node_bld_trie[n].trie,\n\t\t\tno_match, 1);\n\t}\n\n\tindices->dfa_index = RTE_ACL_DFA_SIZE + 1;\n\tindices->quad_index = indices->dfa_index +\n\t\tcounts->dfa_gr64 * RTE_ACL_DFA_GR64_SIZE;\n\tindices->single_index = indices->quad_index + counts->quad_vectors;\n\tindices->match_start = indices->single_index + counts->single + 1;\n\tindices->match_start = RTE_ALIGN(indices->match_start,\n\t\t(XMM_SIZE / sizeof(uint64_t)));\n\tindices->match_index = 1;\n}\n\n/*\n * Generate the runtime structure using build structure\n */\nint\nrte_acl_gen(struct rte_acl_ctx *ctx, struct rte_acl_trie *trie,\n\tstruct rte_acl_bld_trie *node_bld_trie, uint32_t num_tries,\n\tuint32_t num_categories, uint32_t data_index_sz, size_t max_size)\n{\n\tvoid *mem;\n\tsize_t total_size;\n\tuint64_t *node_array, no_match;\n\tuint32_t n, match_index;\n\tstruct rte_acl_match_results *match;\n\tstruct acl_node_counters counts;\n\tstruct rte_acl_indices indices;\n\n\tno_match = RTE_ACL_NODE_MATCH;\n\n\t/* Fill counts and indices arrays from the nodes. */\n\tacl_calc_counts_indices(&counts, &indices,\n\t\tnode_bld_trie, num_tries, no_match);\n\n\t/* Allocate runtime memory (align to cache boundary) */\n\ttotal_size = RTE_ALIGN(data_index_sz, RTE_CACHE_LINE_SIZE) +\n\t\tindices.match_start * sizeof(uint64_t) +\n\t\t(counts.match + 1) * sizeof(struct rte_acl_match_results) +\n\t\tXMM_SIZE;\n\n\tif (total_size > max_size) {\n\t\tRTE_LOG(DEBUG, ACL,\n\t\t\t\"Gen phase for ACL ctx \\\"%s\\\" exceeds max_size limit, \"\n\t\t\t\"bytes required: %zu, allowed: %zu\\n\",\n\t\t\tctx->name, total_size, max_size);\n\t\treturn -ERANGE;\n\t}\n\n\tmem = rte_zmalloc_socket(ctx->name, total_size, RTE_CACHE_LINE_SIZE,\n\t\t\tctx->socket_id);\n\tif (mem == NULL) {\n\t\tRTE_LOG(ERR, ACL,\n\t\t\t\"allocation of %zu bytes on socket %d for %s failed\\n\",\n\t\t\ttotal_size, ctx->socket_id, ctx->name);\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Fill the runtime structure */\n\tmatch_index = indices.match_start;\n\tnode_array = (uint64_t *)((uintptr_t)mem +\n\t\tRTE_ALIGN(data_index_sz, RTE_CACHE_LINE_SIZE));\n\n\t/*\n\t * Setup the NOMATCH node (a SINGLE at the\n\t * highest index, that points to itself)\n\t */\n\n\tnode_array[RTE_ACL_DFA_SIZE] = RTE_ACL_DFA_SIZE | RTE_ACL_NODE_SINGLE;\n\n\tfor (n = 0; n < RTE_ACL_DFA_SIZE; n++)\n\t\tnode_array[n] = no_match;\n\n\t/* NOMATCH result at index 0 */\n\tmatch = ((struct rte_acl_match_results *)(node_array + match_index));\n\tmemset(match, 0, sizeof(*match));\n\n\tfor (n = 0; n < num_tries; n++) {\n\n\t\tacl_gen_node(node_bld_trie[n].trie, node_array, no_match,\n\t\t\t&indices, num_categories);\n\n\t\tif (node_bld_trie[n].trie->node_index == no_match)\n\t\t\ttrie[n].root_index = 0;\n\t\telse\n\t\t\ttrie[n].root_index = node_bld_trie[n].trie->node_index;\n\t}\n\n\tctx->mem = mem;\n\tctx->mem_sz = total_size;\n\tctx->data_indexes = mem;\n\tctx->num_tries = num_tries;\n\tctx->num_categories = num_categories;\n\tctx->match_index = match_index;\n\tctx->no_match = no_match;\n\tctx->idle = node_array[RTE_ACL_DFA_SIZE];\n\tctx->trans_table = node_array;\n\tmemcpy(ctx->trie, trie, sizeof(ctx->trie));\n\n\tacl_gen_log_stats(ctx, &counts, &indices, max_size);\n\treturn 0;\n}\n" }, { "path": "lib/librte_acl/acl_run.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef\t_ACL_RUN_H_\n#define\t_ACL_RUN_H_\n\n#include \n#include \"acl.h\"\n\n#define MAX_SEARCHES_AVX16\t16\n#define MAX_SEARCHES_SSE8\t8\n#define MAX_SEARCHES_SSE4\t4\n#define MAX_SEARCHES_SCALAR\t2\n\n#define GET_NEXT_4BYTES(prm, idx)\t\\\n\t(*((const int32_t *)((prm)[(idx)].data + *(prm)[idx].data_index++)))\n\n\n#define RTE_ACL_NODE_INDEX\t((uint32_t)~RTE_ACL_NODE_TYPE)\n\n#define\tSCALAR_QRANGE_MULT\t0x01010101\n#define\tSCALAR_QRANGE_MASK\t0x7f7f7f7f\n#define\tSCALAR_QRANGE_MIN\t0x80808080\n\n/*\n * Structure to manage N parallel trie traversals.\n * The runtime trie traversal routines can process 8, 4, or 2 tries\n * in parallel. Each packet may require multiple trie traversals (up to 4).\n * This structure is used to fill the slots (0 to n-1) for parallel processing\n * with the trie traversals needed for each packet.\n */\nstruct acl_flow_data {\n\tuint32_t num_packets;\n\t/* number of packets processed */\n\tuint32_t started;\n\t/* number of trie traversals in progress */\n\tuint32_t trie;\n\t/* current trie index (0 to N-1) */\n\tuint32_t cmplt_size;\n\tuint32_t total_packets;\n\tuint32_t categories;\n\t/* number of result categories per packet. */\n\t/* maximum number of packets to process */\n\tconst uint64_t *trans;\n\tconst uint8_t **data;\n\tuint32_t *results;\n\tstruct completion *last_cmplt;\n\tstruct completion *cmplt_array;\n};\n\n/*\n * Structure to maintain running results for\n * a single packet (up to 4 tries).\n */\nstruct completion {\n\tuint32_t *results; /* running results. */\n\tint32_t priority[RTE_ACL_MAX_CATEGORIES]; /* running priorities. */\n\tuint32_t count; /* num of remaining tries */\n\t/* true for allocated struct */\n} __attribute__((aligned(XMM_SIZE)));\n\n/*\n * One parms structure for each slot in the search engine.\n */\nstruct parms {\n\tconst uint8_t *data;\n\t/* input data for this packet */\n\tconst uint32_t *data_index;\n\t/* data indirection for this trie */\n\tstruct completion *cmplt;\n\t/* completion data for this packet */\n};\n\n/*\n * Define an global idle node for unused engine slots\n */\nstatic const uint32_t idle[UINT8_MAX + 1];\n\n/*\n * Allocate a completion structure to manage the tries for a packet.\n */\nstatic inline struct completion *\nalloc_completion(struct completion *p, uint32_t size, uint32_t tries,\n\tuint32_t *results)\n{\n\tuint32_t n;\n\n\tfor (n = 0; n < size; n++) {\n\n\t\tif (p[n].count == 0) {\n\n\t\t\t/* mark as allocated and set number of tries. */\n\t\t\tp[n].count = tries;\n\t\t\tp[n].results = results;\n\t\t\treturn &(p[n]);\n\t\t}\n\t}\n\n\t/* should never get here */\n\treturn NULL;\n}\n\n/*\n * Resolve priority for a single result trie.\n */\nstatic inline void\nresolve_single_priority(uint64_t transition, int n,\n\tconst struct rte_acl_ctx *ctx, struct parms *parms,\n\tconst struct rte_acl_match_results *p)\n{\n\tif (parms[n].cmplt->count == ctx->num_tries ||\n\t\t\tparms[n].cmplt->priority[0] <=\n\t\t\tp[transition].priority[0]) {\n\n\t\tparms[n].cmplt->priority[0] = p[transition].priority[0];\n\t\tparms[n].cmplt->results[0] = p[transition].results[0];\n\t}\n}\n\n/*\n * Routine to fill a slot in the parallel trie traversal array (parms) from\n * the list of packets (flows).\n */\nstatic inline uint64_t\nacl_start_next_trie(struct acl_flow_data *flows, struct parms *parms, int n,\n\tconst struct rte_acl_ctx *ctx)\n{\n\tuint64_t transition;\n\n\t/* if there are any more packets to process */\n\tif (flows->num_packets < flows->total_packets) {\n\t\tparms[n].data = flows->data[flows->num_packets];\n\t\tparms[n].data_index = ctx->trie[flows->trie].data_index;\n\n\t\t/* if this is the first trie for this packet */\n\t\tif (flows->trie == 0) {\n\t\t\tflows->last_cmplt = alloc_completion(flows->cmplt_array,\n\t\t\t\tflows->cmplt_size, ctx->num_tries,\n\t\t\t\tflows->results +\n\t\t\t\tflows->num_packets * flows->categories);\n\t\t}\n\n\t\t/* set completion parameters and starting index for this slot */\n\t\tparms[n].cmplt = flows->last_cmplt;\n\t\ttransition =\n\t\t\tflows->trans[parms[n].data[*parms[n].data_index++] +\n\t\t\tctx->trie[flows->trie].root_index];\n\n\t\t/*\n\t\t * if this is the last trie for this packet,\n\t\t * then setup next packet.\n\t\t */\n\t\tflows->trie++;\n\t\tif (flows->trie >= ctx->num_tries) {\n\t\t\tflows->trie = 0;\n\t\t\tflows->num_packets++;\n\t\t}\n\n\t\t/* keep track of number of active trie traversals */\n\t\tflows->started++;\n\n\t/* no more tries to process, set slot to an idle position */\n\t} else {\n\t\ttransition = ctx->idle;\n\t\tparms[n].data = (const uint8_t *)idle;\n\t\tparms[n].data_index = idle;\n\t}\n\treturn transition;\n}\n\nstatic inline void\nacl_set_flow(struct acl_flow_data *flows, struct completion *cmplt,\n\tuint32_t cmplt_size, const uint8_t **data, uint32_t *results,\n\tuint32_t data_num, uint32_t categories, const uint64_t *trans)\n{\n\tflows->num_packets = 0;\n\tflows->started = 0;\n\tflows->trie = 0;\n\tflows->last_cmplt = NULL;\n\tflows->cmplt_array = cmplt;\n\tflows->total_packets = data_num;\n\tflows->categories = categories;\n\tflows->cmplt_size = cmplt_size;\n\tflows->data = data;\n\tflows->results = results;\n\tflows->trans = trans;\n}\n\ntypedef void (*resolve_priority_t)\n(uint64_t transition, int n, const struct rte_acl_ctx *ctx,\n\tstruct parms *parms, const struct rte_acl_match_results *p,\n\tuint32_t categories);\n\n/*\n * Detect matches. If a match node transition is found, then this trie\n * traversal is complete and fill the slot with the next trie\n * to be processed.\n */\nstatic inline uint64_t\nacl_match_check(uint64_t transition, int slot,\n\tconst struct rte_acl_ctx *ctx, struct parms *parms,\n\tstruct acl_flow_data *flows, resolve_priority_t resolve_priority)\n{\n\tconst struct rte_acl_match_results *p;\n\n\tp = (const struct rte_acl_match_results *)\n\t\t(flows->trans + ctx->match_index);\n\n\tif (transition & RTE_ACL_NODE_MATCH) {\n\n\t\t/* Remove flags from index and decrement active traversals */\n\t\ttransition &= RTE_ACL_NODE_INDEX;\n\t\tflows->started--;\n\n\t\t/* Resolve priorities for this trie and running results */\n\t\tif (flows->categories == 1)\n\t\t\tresolve_single_priority(transition, slot, ctx,\n\t\t\t\tparms, p);\n\t\telse\n\t\t\tresolve_priority(transition, slot, ctx, parms,\n\t\t\t\tp, flows->categories);\n\n\t\t/* Count down completed tries for this search request */\n\t\tparms[slot].cmplt->count--;\n\n\t\t/* Fill the slot with the next trie or idle trie */\n\t\ttransition = acl_start_next_trie(flows, parms, slot, ctx);\n\t}\n\n\treturn transition;\n}\n\n#endif /* _ACL_RUN_H_ */\n" }, { "path": "lib/librte_acl/acl_run_avx2.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n\n#include \"acl_run_avx2.h\"\n\n/*\n * Note, that to be able to use AVX2 classify method,\n * both compiler and target cpu have to support AVX2 instructions.\n */\nint\nrte_acl_classify_avx2(const struct rte_acl_ctx *ctx, const uint8_t **data,\n\tuint32_t *results, uint32_t num, uint32_t categories)\n{\n\tif (likely(num >= MAX_SEARCHES_AVX16))\n\t\treturn search_avx2x16(ctx, data, results, num, categories);\n\telse if (num >= MAX_SEARCHES_SSE8)\n\t\treturn search_sse_8(ctx, data, results, num, categories);\n\telse if (num >= MAX_SEARCHES_SSE4)\n\t\treturn search_sse_4(ctx, data, results, num, categories);\n\telse\n\t\treturn rte_acl_classify_scalar(ctx, data, results, num,\n\t\t\tcategories);\n}\n" }, { "path": "lib/librte_acl/acl_run_avx2.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"acl_run_sse.h\"\n\nstatic const rte_ymm_t ymm_match_mask = {\n\t.u32 = {\n\t\tRTE_ACL_NODE_MATCH,\n\t\tRTE_ACL_NODE_MATCH,\n\t\tRTE_ACL_NODE_MATCH,\n\t\tRTE_ACL_NODE_MATCH,\n\t\tRTE_ACL_NODE_MATCH,\n\t\tRTE_ACL_NODE_MATCH,\n\t\tRTE_ACL_NODE_MATCH,\n\t\tRTE_ACL_NODE_MATCH,\n\t},\n};\n\nstatic const rte_ymm_t ymm_index_mask = {\n\t.u32 = {\n\t\tRTE_ACL_NODE_INDEX,\n\t\tRTE_ACL_NODE_INDEX,\n\t\tRTE_ACL_NODE_INDEX,\n\t\tRTE_ACL_NODE_INDEX,\n\t\tRTE_ACL_NODE_INDEX,\n\t\tRTE_ACL_NODE_INDEX,\n\t\tRTE_ACL_NODE_INDEX,\n\t\tRTE_ACL_NODE_INDEX,\n\t},\n};\n\nstatic const rte_ymm_t ymm_shuffle_input = {\n\t.u32 = {\n\t\t0x00000000, 0x04040404, 0x08080808, 0x0c0c0c0c,\n\t\t0x00000000, 0x04040404, 0x08080808, 0x0c0c0c0c,\n\t},\n};\n\nstatic const rte_ymm_t ymm_ones_16 = {\n\t.u16 = {\n\t\t1, 1, 1, 1, 1, 1, 1, 1,\n\t\t1, 1, 1, 1, 1, 1, 1, 1,\n\t},\n};\n\nstatic const rte_ymm_t ymm_range_base = {\n\t.u32 = {\n\t\t0xffffff00, 0xffffff04, 0xffffff08, 0xffffff0c,\n\t\t0xffffff00, 0xffffff04, 0xffffff08, 0xffffff0c,\n\t},\n};\n\n/*\n * Process 8 transitions in parallel.\n * tr_lo contains low 32 bits for 8 transition.\n * tr_hi contains high 32 bits for 8 transition.\n * next_input contains up to 4 input bytes for 8 flows.\n */\nstatic inline __attribute__((always_inline)) ymm_t\ntransition8(ymm_t next_input, const uint64_t *trans, ymm_t *tr_lo, ymm_t *tr_hi)\n{\n\tconst int32_t *tr;\n\tymm_t addr;\n\n\ttr = (const int32_t *)(uintptr_t)trans;\n\n\t/* Calculate the address (array index) for all 8 transitions. */\n\tACL_TR_CALC_ADDR(mm256, 256, addr, ymm_index_mask.y, next_input,\n\t\tymm_shuffle_input.y, ymm_ones_16.y, ymm_range_base.y,\n\t\t*tr_lo, *tr_hi);\n\n\t/* load lower 32 bits of 8 transactions at once. */\n\t*tr_lo = _mm256_i32gather_epi32(tr, addr, sizeof(trans[0]));\n\n\tnext_input = _mm256_srli_epi32(next_input, CHAR_BIT);\n\n\t/* load high 32 bits of 8 transactions at once. */\n\t*tr_hi = _mm256_i32gather_epi32(tr + 1, addr, sizeof(trans[0]));\n\n\treturn next_input;\n}\n\n/*\n * Process matches for 8 flows.\n * tr_lo contains low 32 bits for 8 transition.\n * tr_hi contains high 32 bits for 8 transition.\n */\nstatic inline void\nacl_process_matches_avx2x8(const struct rte_acl_ctx *ctx,\n\tstruct parms *parms, struct acl_flow_data *flows, uint32_t slot,\n\tymm_t matches, ymm_t *tr_lo, ymm_t *tr_hi)\n{\n\tymm_t t0, t1;\n\tymm_t lo, hi;\n\txmm_t l0, l1;\n\tuint32_t i;\n\tuint64_t tr[MAX_SEARCHES_SSE8];\n\n\tl1 = _mm256_extracti128_si256(*tr_lo, 1);\n\tl0 = _mm256_castsi256_si128(*tr_lo);\n\n\tfor (i = 0; i != RTE_DIM(tr) / 2; i++) {\n\n\t\t/*\n\t\t * Extract low 32bits of each transition.\n\t\t * That's enough to process the match.\n\t\t */\n\t\ttr[i] = (uint32_t)_mm_cvtsi128_si32(l0);\n\t\ttr[i + 4] = (uint32_t)_mm_cvtsi128_si32(l1);\n\n\t\tl0 = _mm_srli_si128(l0, sizeof(uint32_t));\n\t\tl1 = _mm_srli_si128(l1, sizeof(uint32_t));\n\n\t\ttr[i] = acl_match_check(tr[i], slot + i,\n\t\t\tctx, parms, flows, resolve_priority_sse);\n\t\ttr[i + 4] = acl_match_check(tr[i + 4], slot + i + 4,\n\t\t\tctx, parms, flows, resolve_priority_sse);\n\t}\n\n\t/* Collect new transitions into 2 YMM registers. */\n\tt0 = _mm256_set_epi64x(tr[5], tr[4], tr[1], tr[0]);\n\tt1 = _mm256_set_epi64x(tr[7], tr[6], tr[3], tr[2]);\n\n\t/* For each transition: put low 32 into tr_lo and high 32 into tr_hi */\n\tACL_TR_HILO(mm256, __m256, t0, t1, lo, hi);\n\n\t/* Keep transitions wth NOMATCH intact. */\n\t*tr_lo = _mm256_blendv_epi8(*tr_lo, lo, matches);\n\t*tr_hi = _mm256_blendv_epi8(*tr_hi, hi, matches);\n}\n\nstatic inline void\nacl_match_check_avx2x8(const struct rte_acl_ctx *ctx, struct parms *parms,\n\tstruct acl_flow_data *flows, uint32_t slot,\n\tymm_t *tr_lo, ymm_t *tr_hi, ymm_t match_mask)\n{\n\tuint32_t msk;\n\tymm_t matches, temp;\n\n\t/* test for match node */\n\ttemp = _mm256_and_si256(match_mask, *tr_lo);\n\tmatches = _mm256_cmpeq_epi32(temp, match_mask);\n\tmsk = _mm256_movemask_epi8(matches);\n\n\twhile (msk != 0) {\n\n\t\tacl_process_matches_avx2x8(ctx, parms, flows, slot,\n\t\t\tmatches, tr_lo, tr_hi);\n\t\ttemp = _mm256_and_si256(match_mask, *tr_lo);\n\t\tmatches = _mm256_cmpeq_epi32(temp, match_mask);\n\t\tmsk = _mm256_movemask_epi8(matches);\n\t}\n}\n\n/*\n * Execute trie traversal for up to 16 flows in parallel.\n */\nstatic inline int\nsearch_avx2x16(const struct rte_acl_ctx *ctx, const uint8_t **data,\n\tuint32_t *results, uint32_t total_packets, uint32_t categories)\n{\n\tuint32_t n;\n\tstruct acl_flow_data flows;\n\tuint64_t index_array[MAX_SEARCHES_AVX16];\n\tstruct completion cmplt[MAX_SEARCHES_AVX16];\n\tstruct parms parms[MAX_SEARCHES_AVX16];\n\tymm_t input[2], tr_lo[2], tr_hi[2];\n\tymm_t t0, t1;\n\n\tacl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results,\n\t\ttotal_packets, categories, ctx->trans_table);\n\n\tfor (n = 0; n < RTE_DIM(cmplt); n++) {\n\t\tcmplt[n].count = 0;\n\t\tindex_array[n] = acl_start_next_trie(&flows, parms, n, ctx);\n\t}\n\n\tt0 = _mm256_set_epi64x(index_array[5], index_array[4],\n\t\tindex_array[1], index_array[0]);\n\tt1 = _mm256_set_epi64x(index_array[7], index_array[6],\n\t\tindex_array[3], index_array[2]);\n\n\tACL_TR_HILO(mm256, __m256, t0, t1, tr_lo[0], tr_hi[0]);\n\n\tt0 = _mm256_set_epi64x(index_array[13], index_array[12],\n\t\tindex_array[9], index_array[8]);\n\tt1 = _mm256_set_epi64x(index_array[15], index_array[14],\n\t\tindex_array[11], index_array[10]);\n\n\tACL_TR_HILO(mm256, __m256, t0, t1, tr_lo[1], tr_hi[1]);\n\n\t /* Check for any matches. */\n\tacl_match_check_avx2x8(ctx, parms, &flows, 0, &tr_lo[0], &tr_hi[0],\n\t\tymm_match_mask.y);\n\tacl_match_check_avx2x8(ctx, parms, &flows, 8, &tr_lo[1], &tr_hi[1],\n\t\tymm_match_mask.y);\n\n\twhile (flows.started > 0) {\n\n\t\tuint32_t in[MAX_SEARCHES_SSE8];\n\n\t\t/* Gather 4 bytes of input data for first 8 flows. */\n\t\tin[0] = GET_NEXT_4BYTES(parms, 0);\n\t\tin[4] = GET_NEXT_4BYTES(parms, 4);\n\t\tin[1] = GET_NEXT_4BYTES(parms, 1);\n\t\tin[5] = GET_NEXT_4BYTES(parms, 5);\n\t\tin[2] = GET_NEXT_4BYTES(parms, 2);\n\t\tin[6] = GET_NEXT_4BYTES(parms, 6);\n\t\tin[3] = GET_NEXT_4BYTES(parms, 3);\n\t\tin[7] = GET_NEXT_4BYTES(parms, 7);\n\t\tinput[0] = _mm256_set_epi32(in[7], in[6], in[5], in[4],\n\t\t\tin[3], in[2], in[1], in[0]);\n\n\t\t/* Gather 4 bytes of input data for last 8 flows. */\n\t\tin[0] = GET_NEXT_4BYTES(parms, 8);\n\t\tin[4] = GET_NEXT_4BYTES(parms, 12);\n\t\tin[1] = GET_NEXT_4BYTES(parms, 9);\n\t\tin[5] = GET_NEXT_4BYTES(parms, 13);\n\t\tin[2] = GET_NEXT_4BYTES(parms, 10);\n\t\tin[6] = GET_NEXT_4BYTES(parms, 14);\n\t\tin[3] = GET_NEXT_4BYTES(parms, 11);\n\t\tin[7] = GET_NEXT_4BYTES(parms, 15);\n\t\tinput[1] = _mm256_set_epi32(in[7], in[6], in[5], in[4],\n\t\t\tin[3], in[2], in[1], in[0]);\n\n\t\tinput[0] = transition8(input[0], flows.trans,\n\t\t\t&tr_lo[0], &tr_hi[0]);\n\t\tinput[1] = transition8(input[1], flows.trans,\n\t\t\t&tr_lo[1], &tr_hi[1]);\n\n\t\tinput[0] = transition8(input[0], flows.trans,\n\t\t\t&tr_lo[0], &tr_hi[0]);\n\t\tinput[1] = transition8(input[1], flows.trans,\n\t\t\t&tr_lo[1], &tr_hi[1]);\n\n\t\tinput[0] = transition8(input[0], flows.trans,\n\t\t\t&tr_lo[0], &tr_hi[0]);\n\t\tinput[1] = transition8(input[1], flows.trans,\n\t\t\t&tr_lo[1], &tr_hi[1]);\n\n\t\tinput[0] = transition8(input[0], flows.trans,\n\t\t\t&tr_lo[0], &tr_hi[0]);\n\t\tinput[1] = transition8(input[1], flows.trans,\n\t\t\t&tr_lo[1], &tr_hi[1]);\n\n\t\t /* Check for any matches. */\n\t\tacl_match_check_avx2x8(ctx, parms, &flows, 0,\n\t\t\t&tr_lo[0], &tr_hi[0], ymm_match_mask.y);\n\t\tacl_match_check_avx2x8(ctx, parms, &flows, 8,\n\t\t\t&tr_lo[1], &tr_hi[1], ymm_match_mask.y);\n\t}\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_acl/acl_run_scalar.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"acl_run.h\"\n\n/*\n * Resolve priority for multiple results (scalar version).\n * This consists comparing the priority of the current traversal with the\n * running set of results for the packet.\n * For each result, keep a running array of the result (rule number) and\n * its priority for each category.\n */\nstatic inline void\nresolve_priority_scalar(uint64_t transition, int n,\n\tconst struct rte_acl_ctx *ctx, struct parms *parms,\n\tconst struct rte_acl_match_results *p, uint32_t categories)\n{\n\tuint32_t i;\n\tint32_t *saved_priority;\n\tuint32_t *saved_results;\n\tconst int32_t *priority;\n\tconst uint32_t *results;\n\n\tsaved_results = parms[n].cmplt->results;\n\tsaved_priority = parms[n].cmplt->priority;\n\n\t/* results and priorities for completed trie */\n\tresults = p[transition].results;\n\tpriority = p[transition].priority;\n\n\t/* if this is not the first completed trie */\n\tif (parms[n].cmplt->count != ctx->num_tries) {\n\t\tfor (i = 0; i < categories; i += RTE_ACL_RESULTS_MULTIPLIER) {\n\n\t\t\tif (saved_priority[i] <= priority[i]) {\n\t\t\t\tsaved_priority[i] = priority[i];\n\t\t\t\tsaved_results[i] = results[i];\n\t\t\t}\n\t\t\tif (saved_priority[i + 1] <= priority[i + 1]) {\n\t\t\t\tsaved_priority[i + 1] = priority[i + 1];\n\t\t\t\tsaved_results[i + 1] = results[i + 1];\n\t\t\t}\n\t\t\tif (saved_priority[i + 2] <= priority[i + 2]) {\n\t\t\t\tsaved_priority[i + 2] = priority[i + 2];\n\t\t\t\tsaved_results[i + 2] = results[i + 2];\n\t\t\t}\n\t\t\tif (saved_priority[i + 3] <= priority[i + 3]) {\n\t\t\t\tsaved_priority[i + 3] = priority[i + 3];\n\t\t\t\tsaved_results[i + 3] = results[i + 3];\n\t\t\t}\n\t\t}\n\t} else {\n\t\tfor (i = 0; i < categories; i += RTE_ACL_RESULTS_MULTIPLIER) {\n\t\t\tsaved_priority[i] = priority[i];\n\t\t\tsaved_priority[i + 1] = priority[i + 1];\n\t\t\tsaved_priority[i + 2] = priority[i + 2];\n\t\t\tsaved_priority[i + 3] = priority[i + 3];\n\n\t\t\tsaved_results[i] = results[i];\n\t\t\tsaved_results[i + 1] = results[i + 1];\n\t\t\tsaved_results[i + 2] = results[i + 2];\n\t\t\tsaved_results[i + 3] = results[i + 3];\n\t\t}\n\t}\n}\n\nstatic inline uint32_t\nscan_forward(uint32_t input, uint32_t max)\n{\n\treturn (input == 0) ? max : rte_bsf32(input);\n}\n\nstatic inline uint64_t\nscalar_transition(const uint64_t *trans_table, uint64_t transition,\n\tuint8_t input)\n{\n\tuint32_t addr, index, ranges, x, a, b, c;\n\n\t/* break transition into component parts */\n\tranges = transition >> (sizeof(index) * CHAR_BIT);\n\tindex = transition & ~RTE_ACL_NODE_INDEX;\n\taddr = transition ^ index;\n\n\tif (index != RTE_ACL_NODE_DFA) {\n\t\t/* calc address for a QRANGE/SINGLE node */\n\t\tc = (uint32_t)input * SCALAR_QRANGE_MULT;\n\t\ta = ranges | SCALAR_QRANGE_MIN;\n\t\ta -= (c & SCALAR_QRANGE_MASK);\n\t\tb = c & SCALAR_QRANGE_MIN;\n\t\ta &= SCALAR_QRANGE_MIN;\n\t\ta ^= (ranges ^ b) & (a ^ b);\n\t\tx = scan_forward(a, 32) >> 3;\n\t} else {\n\t\t/* calc address for a DFA node */\n\t\tx = ranges >> (input /\n\t\t\tRTE_ACL_DFA_GR64_SIZE * RTE_ACL_DFA_GR64_BIT);\n\t\tx &= UINT8_MAX;\n\t\tx = input - x;\n\t}\n\n\taddr += x;\n\n\t/* pickup next transition */\n\ttransition = *(trans_table + addr);\n\treturn transition;\n}\n\nint\nrte_acl_classify_scalar(const struct rte_acl_ctx *ctx, const uint8_t **data,\n\tuint32_t *results, uint32_t num, uint32_t categories)\n{\n\tint n;\n\tuint64_t transition0, transition1;\n\tuint32_t input0, input1;\n\tstruct acl_flow_data flows;\n\tuint64_t index_array[MAX_SEARCHES_SCALAR];\n\tstruct completion cmplt[MAX_SEARCHES_SCALAR];\n\tstruct parms parms[MAX_SEARCHES_SCALAR];\n\n\tacl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results, num,\n\t\tcategories, ctx->trans_table);\n\n\tfor (n = 0; n < MAX_SEARCHES_SCALAR; n++) {\n\t\tcmplt[n].count = 0;\n\t\tindex_array[n] = acl_start_next_trie(&flows, parms, n, ctx);\n\t}\n\n\ttransition0 = index_array[0];\n\ttransition1 = index_array[1];\n\n\twhile ((transition0 | transition1) & RTE_ACL_NODE_MATCH) {\n\t\ttransition0 = acl_match_check(transition0,\n\t\t\t0, ctx, parms, &flows, resolve_priority_scalar);\n\t\ttransition1 = acl_match_check(transition1,\n\t\t\t1, ctx, parms, &flows, resolve_priority_scalar);\n\t}\n\n\twhile (flows.started > 0) {\n\n\t\tinput0 = GET_NEXT_4BYTES(parms, 0);\n\t\tinput1 = GET_NEXT_4BYTES(parms, 1);\n\n\t\tfor (n = 0; n < 4; n++) {\n\n\t\t\ttransition0 = scalar_transition(flows.trans,\n\t\t\t\ttransition0, (uint8_t)input0);\n\t\t\tinput0 >>= CHAR_BIT;\n\n\t\t\ttransition1 = scalar_transition(flows.trans,\n\t\t\t\ttransition1, (uint8_t)input1);\n\t\t\tinput1 >>= CHAR_BIT;\n\t\t}\n\n\t\twhile ((transition0 | transition1) & RTE_ACL_NODE_MATCH) {\n\t\t\ttransition0 = acl_match_check(transition0,\n\t\t\t\t0, ctx, parms, &flows, resolve_priority_scalar);\n\t\t\ttransition1 = acl_match_check(transition1,\n\t\t\t\t1, ctx, parms, &flows, resolve_priority_scalar);\n\t\t}\n\t}\n\treturn 0;\n}\n" }, { "path": "lib/librte_acl/acl_run_sse.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"acl_run_sse.h\"\n\nint\nrte_acl_classify_sse(const struct rte_acl_ctx *ctx, const uint8_t **data,\n\tuint32_t *results, uint32_t num, uint32_t categories)\n{\n\tif (likely(num >= MAX_SEARCHES_SSE8))\n\t\treturn search_sse_8(ctx, data, results, num, categories);\n\telse if (num >= MAX_SEARCHES_SSE4)\n\t\treturn search_sse_4(ctx, data, results, num, categories);\n\telse\n\t\treturn rte_acl_classify_scalar(ctx, data, results, num,\n\t\t\tcategories);\n}\n" }, { "path": "lib/librte_acl/acl_run_sse.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"acl_run.h\"\n#include \"acl_vect.h\"\n\nenum {\n\tSHUFFLE32_SLOT1 = 0xe5,\n\tSHUFFLE32_SLOT2 = 0xe6,\n\tSHUFFLE32_SLOT3 = 0xe7,\n\tSHUFFLE32_SWAP64 = 0x4e,\n};\n\nstatic const rte_xmm_t xmm_shuffle_input = {\n\t.u32 = {0x00000000, 0x04040404, 0x08080808, 0x0c0c0c0c},\n};\n\nstatic const rte_xmm_t xmm_ones_16 = {\n\t.u16 = {1, 1, 1, 1, 1, 1, 1, 1},\n};\n\nstatic const rte_xmm_t xmm_match_mask = {\n\t.u32 = {\n\t\tRTE_ACL_NODE_MATCH,\n\t\tRTE_ACL_NODE_MATCH,\n\t\tRTE_ACL_NODE_MATCH,\n\t\tRTE_ACL_NODE_MATCH,\n\t},\n};\n\nstatic const rte_xmm_t xmm_index_mask = {\n\t.u32 = {\n\t\tRTE_ACL_NODE_INDEX,\n\t\tRTE_ACL_NODE_INDEX,\n\t\tRTE_ACL_NODE_INDEX,\n\t\tRTE_ACL_NODE_INDEX,\n\t},\n};\n\nstatic const rte_xmm_t xmm_range_base = {\n\t.u32 = {\n\t\t0xffffff00, 0xffffff04, 0xffffff08, 0xffffff0c,\n\t},\n};\n\n/*\n * Resolve priority for multiple results (sse version).\n * This consists comparing the priority of the current traversal with the\n * running set of results for the packet.\n * For each result, keep a running array of the result (rule number) and\n * its priority for each category.\n */\nstatic inline void\nresolve_priority_sse(uint64_t transition, int n, const struct rte_acl_ctx *ctx,\n\tstruct parms *parms, const struct rte_acl_match_results *p,\n\tuint32_t categories)\n{\n\tuint32_t x;\n\txmm_t results, priority, results1, priority1, selector;\n\txmm_t *saved_results, *saved_priority;\n\n\tfor (x = 0; x < categories; x += RTE_ACL_RESULTS_MULTIPLIER) {\n\n\t\tsaved_results = (xmm_t *)(&parms[n].cmplt->results[x]);\n\t\tsaved_priority =\n\t\t\t(xmm_t *)(&parms[n].cmplt->priority[x]);\n\n\t\t/* get results and priorities for completed trie */\n\t\tresults = _mm_loadu_si128(\n\t\t\t(const xmm_t *)&p[transition].results[x]);\n\t\tpriority = _mm_loadu_si128(\n\t\t\t(const xmm_t *)&p[transition].priority[x]);\n\n\t\t/* if this is not the first completed trie */\n\t\tif (parms[n].cmplt->count != ctx->num_tries) {\n\n\t\t\t/* get running best results and their priorities */\n\t\t\tresults1 = _mm_loadu_si128(saved_results);\n\t\t\tpriority1 = _mm_loadu_si128(saved_priority);\n\n\t\t\t/* select results that are highest priority */\n\t\t\tselector = _mm_cmpgt_epi32(priority1, priority);\n\t\t\tresults = _mm_blendv_epi8(results, results1, selector);\n\t\t\tpriority = _mm_blendv_epi8(priority, priority1,\n\t\t\t\tselector);\n\t\t}\n\n\t\t/* save running best results and their priorities */\n\t\t_mm_storeu_si128(saved_results, results);\n\t\t_mm_storeu_si128(saved_priority, priority);\n\t}\n}\n\n/*\n * Extract transitions from an XMM register and check for any matches\n */\nstatic void\nacl_process_matches(xmm_t *indices, int slot, const struct rte_acl_ctx *ctx,\n\tstruct parms *parms, struct acl_flow_data *flows)\n{\n\tuint64_t transition1, transition2;\n\n\t/* extract transition from low 64 bits. */\n\ttransition1 = _mm_cvtsi128_si64(*indices);\n\n\t/* extract transition from high 64 bits. */\n\t*indices = _mm_shuffle_epi32(*indices, SHUFFLE32_SWAP64);\n\ttransition2 = _mm_cvtsi128_si64(*indices);\n\n\ttransition1 = acl_match_check(transition1, slot, ctx,\n\t\tparms, flows, resolve_priority_sse);\n\ttransition2 = acl_match_check(transition2, slot + 1, ctx,\n\t\tparms, flows, resolve_priority_sse);\n\n\t/* update indices with new transitions. */\n\t*indices = _mm_set_epi64x(transition2, transition1);\n}\n\n/*\n * Check for any match in 4 transitions (contained in 2 SSE registers)\n */\nstatic inline __attribute__((always_inline)) void\nacl_match_check_x4(int slot, const struct rte_acl_ctx *ctx, struct parms *parms,\n\tstruct acl_flow_data *flows, xmm_t *indices1, xmm_t *indices2,\n\txmm_t match_mask)\n{\n\txmm_t temp;\n\n\t/* put low 32 bits of each transition into one register */\n\ttemp = (xmm_t)_mm_shuffle_ps((__m128)*indices1, (__m128)*indices2,\n\t\t0x88);\n\t/* test for match node */\n\ttemp = _mm_and_si128(match_mask, temp);\n\n\twhile (!_mm_testz_si128(temp, temp)) {\n\t\tacl_process_matches(indices1, slot, ctx, parms, flows);\n\t\tacl_process_matches(indices2, slot + 2, ctx, parms, flows);\n\n\t\ttemp = (xmm_t)_mm_shuffle_ps((__m128)*indices1,\n\t\t\t\t\t(__m128)*indices2,\n\t\t\t\t\t0x88);\n\t\ttemp = _mm_and_si128(match_mask, temp);\n\t}\n}\n\n/*\n * Process 4 transitions (in 2 XMM registers) in parallel\n */\nstatic inline __attribute__((always_inline)) xmm_t\ntransition4(xmm_t next_input, const uint64_t *trans,\n\txmm_t *indices1, xmm_t *indices2)\n{\n\txmm_t addr, tr_lo, tr_hi;\n\tuint64_t trans0, trans2;\n\n\t/* Shuffle low 32 into tr_lo and high 32 into tr_hi */\n\tACL_TR_HILO(mm, __m128, *indices1, *indices2, tr_lo, tr_hi);\n\n\t /* Calculate the address (array index) for all 4 transitions. */\n\tACL_TR_CALC_ADDR(mm, 128, addr, xmm_index_mask.x, next_input,\n\t\txmm_shuffle_input.x, xmm_ones_16.x, xmm_range_base.x,\n\t\ttr_lo, tr_hi);\n\n\t /* Gather 64 bit transitions and pack back into 2 registers. */\n\n\ttrans0 = trans[_mm_cvtsi128_si32(addr)];\n\n\t/* get slot 2 */\n\n\t/* {x0, x1, x2, x3} -> {x2, x1, x2, x3} */\n\taddr = _mm_shuffle_epi32(addr, SHUFFLE32_SLOT2);\n\ttrans2 = trans[_mm_cvtsi128_si32(addr)];\n\n\t/* get slot 1 */\n\n\t/* {x2, x1, x2, x3} -> {x1, x1, x2, x3} */\n\taddr = _mm_shuffle_epi32(addr, SHUFFLE32_SLOT1);\n\t*indices1 = _mm_set_epi64x(trans[_mm_cvtsi128_si32(addr)], trans0);\n\n\t/* get slot 3 */\n\n\t/* {x1, x1, x2, x3} -> {x3, x1, x2, x3} */\n\taddr = _mm_shuffle_epi32(addr, SHUFFLE32_SLOT3);\n\t*indices2 = _mm_set_epi64x(trans[_mm_cvtsi128_si32(addr)], trans2);\n\n\treturn _mm_srli_epi32(next_input, CHAR_BIT);\n}\n\n/*\n * Execute trie traversal with 8 traversals in parallel\n */\nstatic inline int\nsearch_sse_8(const struct rte_acl_ctx *ctx, const uint8_t **data,\n\tuint32_t *results, uint32_t total_packets, uint32_t categories)\n{\n\tint n;\n\tstruct acl_flow_data flows;\n\tuint64_t index_array[MAX_SEARCHES_SSE8];\n\tstruct completion cmplt[MAX_SEARCHES_SSE8];\n\tstruct parms parms[MAX_SEARCHES_SSE8];\n\txmm_t input0, input1;\n\txmm_t indices1, indices2, indices3, indices4;\n\n\tacl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results,\n\t\ttotal_packets, categories, ctx->trans_table);\n\n\tfor (n = 0; n < MAX_SEARCHES_SSE8; n++) {\n\t\tcmplt[n].count = 0;\n\t\tindex_array[n] = acl_start_next_trie(&flows, parms, n, ctx);\n\t}\n\n\t/*\n\t * indices1 contains index_array[0,1]\n\t * indices2 contains index_array[2,3]\n\t * indices3 contains index_array[4,5]\n\t * indices4 contains index_array[6,7]\n\t */\n\n\tindices1 = _mm_loadu_si128((xmm_t *) &index_array[0]);\n\tindices2 = _mm_loadu_si128((xmm_t *) &index_array[2]);\n\n\tindices3 = _mm_loadu_si128((xmm_t *) &index_array[4]);\n\tindices4 = _mm_loadu_si128((xmm_t *) &index_array[6]);\n\n\t /* Check for any matches. */\n\tacl_match_check_x4(0, ctx, parms, &flows,\n\t\t&indices1, &indices2, xmm_match_mask.x);\n\tacl_match_check_x4(4, ctx, parms, &flows,\n\t\t&indices3, &indices4, xmm_match_mask.x);\n\n\twhile (flows.started > 0) {\n\n\t\t/* Gather 4 bytes of input data for each stream. */\n\t\tinput0 = _mm_cvtsi32_si128(GET_NEXT_4BYTES(parms, 0));\n\t\tinput1 = _mm_cvtsi32_si128(GET_NEXT_4BYTES(parms, 4));\n\n\t\tinput0 = _mm_insert_epi32(input0, GET_NEXT_4BYTES(parms, 1), 1);\n\t\tinput1 = _mm_insert_epi32(input1, GET_NEXT_4BYTES(parms, 5), 1);\n\n\t\tinput0 = _mm_insert_epi32(input0, GET_NEXT_4BYTES(parms, 2), 2);\n\t\tinput1 = _mm_insert_epi32(input1, GET_NEXT_4BYTES(parms, 6), 2);\n\n\t\tinput0 = _mm_insert_epi32(input0, GET_NEXT_4BYTES(parms, 3), 3);\n\t\tinput1 = _mm_insert_epi32(input1, GET_NEXT_4BYTES(parms, 7), 3);\n\n\t\t /* Process the 4 bytes of input on each stream. */\n\n\t\tinput0 = transition4(input0, flows.trans,\n\t\t\t&indices1, &indices2);\n\t\tinput1 = transition4(input1, flows.trans,\n\t\t\t&indices3, &indices4);\n\n\t\tinput0 = transition4(input0, flows.trans,\n\t\t\t&indices1, &indices2);\n\t\tinput1 = transition4(input1, flows.trans,\n\t\t\t&indices3, &indices4);\n\n\t\tinput0 = transition4(input0, flows.trans,\n\t\t\t&indices1, &indices2);\n\t\tinput1 = transition4(input1, flows.trans,\n\t\t\t&indices3, &indices4);\n\n\t\tinput0 = transition4(input0, flows.trans,\n\t\t\t&indices1, &indices2);\n\t\tinput1 = transition4(input1, flows.trans,\n\t\t\t&indices3, &indices4);\n\n\t\t /* Check for any matches. */\n\t\tacl_match_check_x4(0, ctx, parms, &flows,\n\t\t\t&indices1, &indices2, xmm_match_mask.x);\n\t\tacl_match_check_x4(4, ctx, parms, &flows,\n\t\t\t&indices3, &indices4, xmm_match_mask.x);\n\t}\n\n\treturn 0;\n}\n\n/*\n * Execute trie traversal with 4 traversals in parallel\n */\nstatic inline int\nsearch_sse_4(const struct rte_acl_ctx *ctx, const uint8_t **data,\n\t uint32_t *results, int total_packets, uint32_t categories)\n{\n\tint n;\n\tstruct acl_flow_data flows;\n\tuint64_t index_array[MAX_SEARCHES_SSE4];\n\tstruct completion cmplt[MAX_SEARCHES_SSE4];\n\tstruct parms parms[MAX_SEARCHES_SSE4];\n\txmm_t input, indices1, indices2;\n\n\tacl_set_flow(&flows, cmplt, RTE_DIM(cmplt), data, results,\n\t\ttotal_packets, categories, ctx->trans_table);\n\n\tfor (n = 0; n < MAX_SEARCHES_SSE4; n++) {\n\t\tcmplt[n].count = 0;\n\t\tindex_array[n] = acl_start_next_trie(&flows, parms, n, ctx);\n\t}\n\n\tindices1 = _mm_loadu_si128((xmm_t *) &index_array[0]);\n\tindices2 = _mm_loadu_si128((xmm_t *) &index_array[2]);\n\n\t/* Check for any matches. */\n\tacl_match_check_x4(0, ctx, parms, &flows,\n\t\t&indices1, &indices2, xmm_match_mask.x);\n\n\twhile (flows.started > 0) {\n\n\t\t/* Gather 4 bytes of input data for each stream. */\n\t\tinput = _mm_cvtsi32_si128(GET_NEXT_4BYTES(parms, 0));\n\t\tinput = _mm_insert_epi32(input, GET_NEXT_4BYTES(parms, 1), 1);\n\t\tinput = _mm_insert_epi32(input, GET_NEXT_4BYTES(parms, 2), 2);\n\t\tinput = _mm_insert_epi32(input, GET_NEXT_4BYTES(parms, 3), 3);\n\n\t\t/* Process the 4 bytes of input on each stream. */\n\t\tinput = transition4(input, flows.trans, &indices1, &indices2);\n\t\tinput = transition4(input, flows.trans, &indices1, &indices2);\n\t\tinput = transition4(input, flows.trans, &indices1, &indices2);\n\t\tinput = transition4(input, flows.trans, &indices1, &indices2);\n\n\t\t/* Check for any matches. */\n\t\tacl_match_check_x4(0, ctx, parms, &flows,\n\t\t\t&indices1, &indices2, xmm_match_mask.x);\n\t}\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_acl/acl_vect.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ACL_VECT_H_\n#define _RTE_ACL_VECT_H_\n\n/**\n * @file\n *\n * RTE ACL SSE/AVX related header.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/*\n * Takes 2 SIMD registers containing N transitions eachi (tr0, tr1).\n * Shuffles it into different representation:\n * lo - contains low 32 bits of given N transitions.\n * hi - contains high 32 bits of given N transitions.\n */\n#define\tACL_TR_HILO(P, TC, tr0, tr1, lo, hi) do { \\\n\tlo = (typeof(lo))_##P##_shuffle_ps((TC)(tr0), (TC)(tr1), 0x88); \\\n\thi = (typeof(hi))_##P##_shuffle_ps((TC)(tr0), (TC)(tr1), 0xdd); \\\n} while (0)\n\n\n/*\n * Calculate the address of the next transition for\n * all types of nodes. Note that only DFA nodes and range\n * nodes actually transition to another node. Match\n * nodes not supposed to be encountered here.\n * For quad range nodes:\n * Calculate number of range boundaries that are less than the\n * input value. Range boundaries for each node are in signed 8 bit,\n * ordered from -128 to 127.\n * This is effectively a popcnt of bytes that are greater than the\n * input byte.\n * Single nodes are processed in the same ways as quad range nodes.\n*/\n#define ACL_TR_CALC_ADDR(P, S,\t\t\t\t\t\\\n\taddr, index_mask, next_input, shuffle_input,\t\t\\\n\tones_16, range_base, tr_lo, tr_hi) do {\t\\\n\t\t\t\t\t\t\t\t\\\n\ttypeof(addr) in, node_type, r, t;\t\t\t\\\n\ttypeof(addr) dfa_msk, dfa_ofs, quad_ofs;\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tt = _##P##_xor_si##S(index_mask, index_mask);\t\t\\\n\tin = _##P##_shuffle_epi8(next_input, shuffle_input);\t\\\n\t\t\t\t\t\t\t\t\\\n\t/* Calc node type and node addr */\t\t\t\\\n\tnode_type = _##P##_andnot_si##S(index_mask, tr_lo);\t\\\n\taddr = _##P##_and_si##S(index_mask, tr_lo);\t\t\\\n\t\t\t\t\t\t\t\t\\\n\t/* mask for DFA type(0) nodes */\t\t\t\\\n\tdfa_msk = _##P##_cmpeq_epi32(node_type, t);\t\t\\\n\t\t\t\t\t\t\t\t\\\n\t/* DFA calculations. */\t\t\t\t\t\\\n\tr = _##P##_srli_epi32(in, 30);\t\t\t\t\\\n\tr = _##P##_add_epi8(r, range_base);\t\t\t\\\n\tt = _##P##_srli_epi32(in, 24);\t\t\t\t\\\n\tr = _##P##_shuffle_epi8(tr_hi, r);\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tdfa_ofs = _##P##_sub_epi32(t, r);\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\t/* QUAD/SINGLE caluclations. */\t\t\t\t\\\n\tt = _##P##_cmpgt_epi8(in, tr_hi);\t\t\t\\\n\tt = _##P##_sign_epi8(t, t);\t\t\t\t\\\n\tt = _##P##_maddubs_epi16(t, t);\t\t\t\t\\\n\tquad_ofs = _##P##_madd_epi16(t, ones_16);\t\t\\\n\t\t\t\t\t\t\t\t\\\n\t/* blend DFA and QUAD/SINGLE. */\t\t\t\\\n\tt = _##P##_blendv_epi8(quad_ofs, dfa_ofs, dfa_msk);\t\\\n\t\t\t\t\t\t\t\t\\\n\t/* calculate address for next transitions. */\t\t\\\n\taddr = _##P##_add_epi32(addr, t);\t\t\t\\\n} while (0)\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_ACL_VECT_H_ */\n" }, { "path": "lib/librte_acl/rte_acl.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \"acl.h\"\n\n#define\tBIT_SIZEOF(x)\t(sizeof(x) * CHAR_BIT)\n\nTAILQ_HEAD(rte_acl_list, rte_tailq_entry);\n\nstatic struct rte_tailq_elem rte_acl_tailq = {\n\t.name = \"RTE_ACL\",\n};\nEAL_REGISTER_TAILQ(rte_acl_tailq)\n\n/*\n * If the compiler doesn't support AVX2 instructions,\n * then the dummy one would be used instead for AVX2 classify method.\n */\nint __attribute__ ((weak))\nrte_acl_classify_avx2(__rte_unused const struct rte_acl_ctx *ctx,\n\t__rte_unused const uint8_t **data,\n\t__rte_unused uint32_t *results,\n\t__rte_unused uint32_t num,\n\t__rte_unused uint32_t categories)\n{\n\treturn -ENOTSUP;\n}\n\nstatic const rte_acl_classify_t classify_fns[] = {\n\t[RTE_ACL_CLASSIFY_DEFAULT] = rte_acl_classify_scalar,\n\t[RTE_ACL_CLASSIFY_SCALAR] = rte_acl_classify_scalar,\n\t[RTE_ACL_CLASSIFY_SSE] = rte_acl_classify_sse,\n\t[RTE_ACL_CLASSIFY_AVX2] = rte_acl_classify_avx2,\n};\n\n/* by default, use always available scalar code path. */\nstatic enum rte_acl_classify_alg rte_acl_default_classify =\n\tRTE_ACL_CLASSIFY_SCALAR;\n\nstatic void\nrte_acl_set_default_classify(enum rte_acl_classify_alg alg)\n{\n\trte_acl_default_classify = alg;\n}\n\nextern int\nrte_acl_set_ctx_classify(struct rte_acl_ctx *ctx, enum rte_acl_classify_alg alg)\n{\n\tif (ctx == NULL || (uint32_t)alg >= RTE_DIM(classify_fns))\n\t\treturn -EINVAL;\n\n\tctx->alg = alg;\n\treturn 0;\n}\n\n/*\n * Select highest available classify method as default one.\n * Note that CLASSIFY_AVX2 should be set as a default only\n * if both conditions are met:\n * at build time compiler supports AVX2 and target cpu supports AVX2.\n */\nstatic void __attribute__((constructor))\nrte_acl_init(void)\n{\n\tenum rte_acl_classify_alg alg = RTE_ACL_CLASSIFY_DEFAULT;\n\n#ifdef CC_AVX2_SUPPORT\n\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))\n\t\talg = RTE_ACL_CLASSIFY_AVX2;\n\telse if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))\n#else\n\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))\n#endif\n\t\talg = RTE_ACL_CLASSIFY_SSE;\n\n\trte_acl_set_default_classify(alg);\n}\n\nint\nrte_acl_classify_alg(const struct rte_acl_ctx *ctx, const uint8_t **data,\n\tuint32_t *results, uint32_t num, uint32_t categories,\n\tenum rte_acl_classify_alg alg)\n{\n\tif (categories != 1 &&\n\t\t\t((RTE_ACL_RESULTS_MULTIPLIER - 1) & categories) != 0)\n\t\treturn -EINVAL;\n\n\treturn classify_fns[alg](ctx, data, results, num, categories);\n}\n\nint\nrte_acl_classify(const struct rte_acl_ctx *ctx, const uint8_t **data,\n\tuint32_t *results, uint32_t num, uint32_t categories)\n{\n\treturn rte_acl_classify_alg(ctx, data, results, num, categories,\n\t\tctx->alg);\n}\n\nstruct rte_acl_ctx *\nrte_acl_find_existing(const char *name)\n{\n\tstruct rte_acl_ctx *ctx = NULL;\n\tstruct rte_acl_list *acl_list;\n\tstruct rte_tailq_entry *te;\n\n\tacl_list = RTE_TAILQ_CAST(rte_acl_tailq.head, rte_acl_list);\n\n\trte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);\n\tTAILQ_FOREACH(te, acl_list, next) {\n\t\tctx = (struct rte_acl_ctx *) te->data;\n\t\tif (strncmp(name, ctx->name, sizeof(ctx->name)) == 0)\n\t\t\tbreak;\n\t}\n\trte_rwlock_read_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\tif (te == NULL) {\n\t\trte_errno = ENOENT;\n\t\treturn NULL;\n\t}\n\treturn ctx;\n}\n\nvoid\nrte_acl_free(struct rte_acl_ctx *ctx)\n{\n\tstruct rte_acl_list *acl_list;\n\tstruct rte_tailq_entry *te;\n\n\tif (ctx == NULL)\n\t\treturn;\n\n\tacl_list = RTE_TAILQ_CAST(rte_acl_tailq.head, rte_acl_list);\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* find our tailq entry */\n\tTAILQ_FOREACH(te, acl_list, next) {\n\t\tif (te->data == (void *) ctx)\n\t\t\tbreak;\n\t}\n\tif (te == NULL) {\n\t\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\t\treturn;\n\t}\n\n\tTAILQ_REMOVE(acl_list, te, next);\n\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\trte_free(ctx->mem);\n\trte_free(ctx);\n\trte_free(te);\n}\n\nstruct rte_acl_ctx *\nrte_acl_create(const struct rte_acl_param *param)\n{\n\tsize_t sz;\n\tstruct rte_acl_ctx *ctx;\n\tstruct rte_acl_list *acl_list;\n\tstruct rte_tailq_entry *te;\n\tchar name[sizeof(ctx->name)];\n\n\tacl_list = RTE_TAILQ_CAST(rte_acl_tailq.head, rte_acl_list);\n\n\t/* check that input parameters are valid. */\n\tif (param == NULL || param->name == NULL) {\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\tsnprintf(name, sizeof(name), \"ACL_%s\", param->name);\n\n\t/* calculate amount of memory required for pattern set. */\n\tsz = sizeof(*ctx) + param->max_rule_num * param->rule_size;\n\n\t/* get EAL TAILQ lock. */\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* if we already have one with that name */\n\tTAILQ_FOREACH(te, acl_list, next) {\n\t\tctx = (struct rte_acl_ctx *) te->data;\n\t\tif (strncmp(param->name, ctx->name, sizeof(ctx->name)) == 0)\n\t\t\tbreak;\n\t}\n\n\t/* if ACL with such name doesn't exist, then create a new one. */\n\tif (te == NULL) {\n\t\tctx = NULL;\n\t\tte = rte_zmalloc(\"ACL_TAILQ_ENTRY\", sizeof(*te), 0);\n\n\t\tif (te == NULL) {\n\t\t\tRTE_LOG(ERR, ACL, \"Cannot allocate tailq entry!\\n\");\n\t\t\tgoto exit;\n\t\t}\n\n\t\tctx = rte_zmalloc_socket(name, sz, RTE_CACHE_LINE_SIZE, param->socket_id);\n\n\t\tif (ctx == NULL) {\n\t\t\tRTE_LOG(ERR, ACL,\n\t\t\t\t\"allocation of %zu bytes on socket %d for %s failed\\n\",\n\t\t\t\tsz, param->socket_id, name);\n\t\t\trte_free(te);\n\t\t\tgoto exit;\n\t\t}\n\t\t/* init new allocated context. */\n\t\tctx->rules = ctx + 1;\n\t\tctx->max_rules = param->max_rule_num;\n\t\tctx->rule_sz = param->rule_size;\n\t\tctx->socket_id = param->socket_id;\n\t\tctx->alg = rte_acl_default_classify;\n\t\tsnprintf(ctx->name, sizeof(ctx->name), \"%s\", param->name);\n\n\t\tte->data = (void *) ctx;\n\n\t\tTAILQ_INSERT_TAIL(acl_list, te, next);\n\t}\n\nexit:\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\treturn ctx;\n}\n\nstatic int\nacl_add_rules(struct rte_acl_ctx *ctx, const void *rules, uint32_t num)\n{\n\tuint8_t *pos;\n\n\tif (num + ctx->num_rules > ctx->max_rules)\n\t\treturn -ENOMEM;\n\n\tpos = ctx->rules;\n\tpos += ctx->rule_sz * ctx->num_rules;\n\tmemcpy(pos, rules, num * ctx->rule_sz);\n\tctx->num_rules += num;\n\n\treturn 0;\n}\n\nstatic int\nacl_check_rule(const struct rte_acl_rule_data *rd)\n{\n\tif ((RTE_LEN2MASK(RTE_ACL_MAX_CATEGORIES, typeof(rd->category_mask)) &\n\t\t\trd->category_mask) == 0 ||\n\t\t\trd->priority > RTE_ACL_MAX_PRIORITY ||\n\t\t\trd->priority < RTE_ACL_MIN_PRIORITY ||\n\t\t\trd->userdata == RTE_ACL_INVALID_USERDATA)\n\t\treturn -EINVAL;\n\treturn 0;\n}\n\nint\nrte_acl_add_rules(struct rte_acl_ctx *ctx, const struct rte_acl_rule *rules,\n\tuint32_t num)\n{\n\tconst struct rte_acl_rule *rv;\n\tuint32_t i;\n\tint32_t rc;\n\n\tif (ctx == NULL || rules == NULL || 0 == ctx->rule_sz)\n\t\treturn -EINVAL;\n\n\tfor (i = 0; i != num; i++) {\n\t\trv = (const struct rte_acl_rule *)\n\t\t\t((uintptr_t)rules + i * ctx->rule_sz);\n\t\trc = acl_check_rule(&rv->data);\n\t\tif (rc != 0) {\n\t\t\tRTE_LOG(ERR, ACL, \"%s(%s): rule #%u is invalid\\n\",\n\t\t\t\t__func__, ctx->name, i + 1);\n\t\t\treturn rc;\n\t\t}\n\t}\n\n\treturn acl_add_rules(ctx, rules, num);\n}\n\n/*\n * Reset all rules.\n * Note that RT structures are not affected.\n */\nvoid\nrte_acl_reset_rules(struct rte_acl_ctx *ctx)\n{\n\tif (ctx != NULL)\n\t\tctx->num_rules = 0;\n}\n\n/*\n * Reset all rules and destroys RT structures.\n */\nvoid\nrte_acl_reset(struct rte_acl_ctx *ctx)\n{\n\tif (ctx != NULL) {\n\t\trte_acl_reset_rules(ctx);\n\t\trte_acl_build(ctx, &ctx->config);\n\t}\n}\n\n/*\n * Dump ACL context to the stdout.\n */\nvoid\nrte_acl_dump(const struct rte_acl_ctx *ctx)\n{\n\tif (!ctx)\n\t\treturn;\n\tprintf(\"acl context <%s>@%p\\n\", ctx->name, ctx);\n\tprintf(\" socket_id=%\"PRId32\"\\n\", ctx->socket_id);\n\tprintf(\" alg=%\"PRId32\"\\n\", ctx->alg);\n\tprintf(\" max_rules=%\"PRIu32\"\\n\", ctx->max_rules);\n\tprintf(\" rule_size=%\"PRIu32\"\\n\", ctx->rule_sz);\n\tprintf(\" num_rules=%\"PRIu32\"\\n\", ctx->num_rules);\n\tprintf(\" num_categories=%\"PRIu32\"\\n\", ctx->num_categories);\n\tprintf(\" num_tries=%\"PRIu32\"\\n\", ctx->num_tries);\n}\n\n/*\n * Dump all ACL contexts to the stdout.\n */\nvoid\nrte_acl_list_dump(void)\n{\n\tstruct rte_acl_ctx *ctx;\n\tstruct rte_acl_list *acl_list;\n\tstruct rte_tailq_entry *te;\n\n\tacl_list = RTE_TAILQ_CAST(rte_acl_tailq.head, rte_acl_list);\n\n\trte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);\n\tTAILQ_FOREACH(te, acl_list, next) {\n\t\tctx = (struct rte_acl_ctx *) te->data;\n\t\trte_acl_dump(ctx);\n\t}\n\trte_rwlock_read_unlock(RTE_EAL_TAILQ_RWLOCK);\n}\n\n/*\n * Support for legacy ipv4vlan rules.\n */\n\nRTE_ACL_RULE_DEF(acl_ipv4vlan_rule, RTE_ACL_IPV4VLAN_NUM_FIELDS);\n\nstatic int\nacl_ipv4vlan_check_rule(const struct rte_acl_ipv4vlan_rule *rule)\n{\n\tif (rule->src_port_low > rule->src_port_high ||\n\t\t\trule->dst_port_low > rule->dst_port_high ||\n\t\t\trule->src_mask_len > BIT_SIZEOF(rule->src_addr) ||\n\t\t\trule->dst_mask_len > BIT_SIZEOF(rule->dst_addr))\n\t\treturn -EINVAL;\n\n\treturn acl_check_rule(&rule->data);\n}\n\nstatic void\nacl_ipv4vlan_convert_rule(const struct rte_acl_ipv4vlan_rule *ri,\n\tstruct acl_ipv4vlan_rule *ro)\n{\n\tro->data = ri->data;\n\n\tro->field[RTE_ACL_IPV4VLAN_PROTO_FIELD].value.u8 = ri->proto;\n\tro->field[RTE_ACL_IPV4VLAN_VLAN1_FIELD].value.u16 = ri->vlan;\n\tro->field[RTE_ACL_IPV4VLAN_VLAN2_FIELD].value.u16 = ri->domain;\n\tro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].value.u32 = ri->src_addr;\n\tro->field[RTE_ACL_IPV4VLAN_DST_FIELD].value.u32 = ri->dst_addr;\n\tro->field[RTE_ACL_IPV4VLAN_SRCP_FIELD].value.u16 = ri->src_port_low;\n\tro->field[RTE_ACL_IPV4VLAN_DSTP_FIELD].value.u16 = ri->dst_port_low;\n\n\tro->field[RTE_ACL_IPV4VLAN_PROTO_FIELD].mask_range.u8 = ri->proto_mask;\n\tro->field[RTE_ACL_IPV4VLAN_VLAN1_FIELD].mask_range.u16 = ri->vlan_mask;\n\tro->field[RTE_ACL_IPV4VLAN_VLAN2_FIELD].mask_range.u16 =\n\t\tri->domain_mask;\n\tro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].mask_range.u32 =\n\t\tri->src_mask_len;\n\tro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32 = ri->dst_mask_len;\n\tro->field[RTE_ACL_IPV4VLAN_SRCP_FIELD].mask_range.u16 =\n\t\tri->src_port_high;\n\tro->field[RTE_ACL_IPV4VLAN_DSTP_FIELD].mask_range.u16 =\n\t\tri->dst_port_high;\n}\n\nint\nrte_acl_ipv4vlan_add_rules(struct rte_acl_ctx *ctx,\n\tconst struct rte_acl_ipv4vlan_rule *rules,\n\tuint32_t num)\n{\n\tint32_t rc;\n\tuint32_t i;\n\tstruct acl_ipv4vlan_rule rv;\n\n\tif (ctx == NULL || rules == NULL || ctx->rule_sz != sizeof(rv))\n\t\treturn -EINVAL;\n\n\t/* check input rules. */\n\tfor (i = 0; i != num; i++) {\n\t\trc = acl_ipv4vlan_check_rule(rules + i);\n\t\tif (rc != 0) {\n\t\t\tRTE_LOG(ERR, ACL, \"%s(%s): rule #%u is invalid\\n\",\n\t\t\t\t__func__, ctx->name, i + 1);\n\t\t\treturn rc;\n\t\t}\n\t}\n\n\tif (num + ctx->num_rules > ctx->max_rules)\n\t\treturn -ENOMEM;\n\n\t/* perform conversion to the internal format and add to the context. */\n\tfor (i = 0, rc = 0; i != num && rc == 0; i++) {\n\t\tacl_ipv4vlan_convert_rule(rules + i, &rv);\n\t\trc = acl_add_rules(ctx, &rv, 1);\n\t}\n\n\treturn rc;\n}\n\nstatic void\nacl_ipv4vlan_config(struct rte_acl_config *cfg,\n\tconst uint32_t layout[RTE_ACL_IPV4VLAN_NUM],\n\tuint32_t num_categories)\n{\n\tstatic const struct rte_acl_field_def\n\t\tipv4_defs[RTE_ACL_IPV4VLAN_NUM_FIELDS] = {\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t\t.size = sizeof(uint8_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_PROTO_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_PROTO,\n\t\t},\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t\t.size = sizeof(uint16_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_VLAN1_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_VLAN,\n\t\t},\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_BITMASK,\n\t\t\t.size = sizeof(uint16_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_VLAN2_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_VLAN,\n\t\t},\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t\t.size = sizeof(uint32_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_SRC_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_SRC,\n\t\t},\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_MASK,\n\t\t\t.size = sizeof(uint32_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_DST_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_DST,\n\t\t},\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t\t.size = sizeof(uint16_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_SRCP_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_PORTS,\n\t\t},\n\t\t{\n\t\t\t.type = RTE_ACL_FIELD_TYPE_RANGE,\n\t\t\t.size = sizeof(uint16_t),\n\t\t\t.field_index = RTE_ACL_IPV4VLAN_DSTP_FIELD,\n\t\t\t.input_index = RTE_ACL_IPV4VLAN_PORTS,\n\t\t},\n\t};\n\n\tmemcpy(&cfg->defs, ipv4_defs, sizeof(ipv4_defs));\n\tcfg->num_fields = RTE_DIM(ipv4_defs);\n\n\tcfg->defs[RTE_ACL_IPV4VLAN_PROTO_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_PROTO];\n\tcfg->defs[RTE_ACL_IPV4VLAN_VLAN1_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_VLAN];\n\tcfg->defs[RTE_ACL_IPV4VLAN_VLAN2_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_VLAN] +\n\t\tcfg->defs[RTE_ACL_IPV4VLAN_VLAN1_FIELD].size;\n\tcfg->defs[RTE_ACL_IPV4VLAN_SRC_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_SRC];\n\tcfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_DST];\n\tcfg->defs[RTE_ACL_IPV4VLAN_SRCP_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_PORTS];\n\tcfg->defs[RTE_ACL_IPV4VLAN_DSTP_FIELD].offset =\n\t\tlayout[RTE_ACL_IPV4VLAN_PORTS] +\n\t\tcfg->defs[RTE_ACL_IPV4VLAN_SRCP_FIELD].size;\n\n\tcfg->num_categories = num_categories;\n}\n\nint\nrte_acl_ipv4vlan_build(struct rte_acl_ctx *ctx,\n\tconst uint32_t layout[RTE_ACL_IPV4VLAN_NUM],\n\tuint32_t num_categories)\n{\n\tstruct rte_acl_config cfg;\n\n\tif (ctx == NULL || layout == NULL)\n\t\treturn -EINVAL;\n\n\tmemset(&cfg, 0, sizeof(cfg));\n\tacl_ipv4vlan_config(&cfg, layout, num_categories);\n\treturn rte_acl_build(ctx, &cfg);\n}\n" }, { "path": "lib/librte_acl/rte_acl.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ACL_H_\n#define _RTE_ACL_H_\n\n/**\n * @file\n *\n * RTE Classifier.\n */\n\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define\tRTE_ACL_MAX_CATEGORIES\t16\n\n#define\tRTE_ACL_RESULTS_MULTIPLIER\t(XMM_SIZE / sizeof(uint32_t))\n\n#define RTE_ACL_MAX_LEVELS 64\n#define RTE_ACL_MAX_FIELDS 64\n\nunion rte_acl_field_types {\n\tuint8_t u8;\n\tuint16_t u16;\n\tuint32_t u32;\n\tuint64_t u64;\n};\n\nenum {\n\tRTE_ACL_FIELD_TYPE_MASK = 0,\n\tRTE_ACL_FIELD_TYPE_RANGE,\n\tRTE_ACL_FIELD_TYPE_BITMASK\n};\n\n/**\n * ACL Field definition.\n * Each field in the ACL rule has an associate definition.\n * It defines the type of field, its size, its offset in the input buffer,\n * the field index, and the input index.\n * For performance reasons, the inner loop of the search function is unrolled\n * to process four input bytes at a time. This requires the input to be grouped\n * into sets of 4 consecutive bytes. The loop processes the first input byte as\n * part of the setup and then subsequent bytes must be in groups of 4\n * consecutive bytes.\n */\nstruct rte_acl_field_def {\n\tuint8_t type; /**< type - RTE_ACL_FIELD_TYPE_*. */\n\tuint8_t\t size; /**< size of field 1,2,4, or 8. */\n\tuint8_t\t field_index; /**< index of field inside the rule. */\n\tuint8_t input_index; /**< 0-N input index. */\n\tuint32_t offset; /**< offset to start of field. */\n};\n\n/**\n * ACL build configuration.\n * Defines the fields of an ACL trie and number of categories to build with.\n */\nstruct rte_acl_config {\n\tuint32_t num_categories; /**< Number of categories to build with. */\n\tuint32_t num_fields; /**< Number of field definitions. */\n\tstruct rte_acl_field_def defs[RTE_ACL_MAX_FIELDS];\n\t/**< array of field definitions. */\n\tsize_t max_size;\n\t/**< max memory limit for internal run-time structures. */\n};\n\n/**\n * Defines the value of a field for a rule.\n */\nstruct rte_acl_field {\n\tunion rte_acl_field_types value;\n\t/**< a 1,2,4, or 8 byte value of the field. */\n\tunion rte_acl_field_types mask_range;\n\t/**<\n\t * depending on field type:\n\t * mask -> 1.2.3.4/32 value=0x1020304, mask_range=32,\n\t * range -> 0 : 65535 value=0, mask_range=65535,\n\t * bitmask -> 0x06/0xff value=6, mask_range=0xff.\n\t */\n};\n\nenum {\n\tRTE_ACL_TYPE_SHIFT = 29,\n\tRTE_ACL_MAX_INDEX = RTE_LEN2MASK(RTE_ACL_TYPE_SHIFT, uint32_t),\n\tRTE_ACL_MAX_PRIORITY = RTE_ACL_MAX_INDEX,\n\tRTE_ACL_MIN_PRIORITY = 0,\n};\n\n#define\tRTE_ACL_INVALID_USERDATA\t0\n\n#define\tRTE_ACL_MASKLEN_TO_BITMASK(v, s)\t\\\n((v) == 0 ? (v) : (typeof(v))((uint64_t)-1 << ((s) * CHAR_BIT - (v))))\n\n/**\n * Miscellaneous data for ACL rule.\n */\nstruct rte_acl_rule_data {\n\tuint32_t category_mask; /**< Mask of categories for that rule. */\n\tint32_t priority; /**< Priority for that rule. */\n\tuint32_t userdata; /**< Associated with the rule user data. */\n};\n\n/**\n * Defines single ACL rule.\n * data - miscellaneous data for the rule.\n * field[] - value and mask or range for each field.\n */\n#define\tRTE_ACL_RULE_DEF(name, fld_num)\tstruct name {\\\n\tstruct rte_acl_rule_data data; \\\n\tstruct rte_acl_field field[fld_num]; \\\n}\n\nRTE_ACL_RULE_DEF(rte_acl_rule, 0);\n\n#define\tRTE_ACL_RULE_SZ(fld_num)\t\\\n\t(sizeof(struct rte_acl_rule) + sizeof(struct rte_acl_field) * (fld_num))\n\n\n/** Max number of characters in name.*/\n#define\tRTE_ACL_NAMESIZE\t\t32\n\n/**\n * Parameters used when creating the ACL context.\n */\nstruct rte_acl_param {\n\tconst char *name; /**< Name of the ACL context. */\n\tint socket_id; /**< Socket ID to allocate memory for. */\n\tuint32_t rule_size; /**< Size of each rule. */\n\tuint32_t max_rule_num; /**< Maximum number of rules. */\n};\n\n\n/**\n * Create a new ACL context.\n *\n * @param param\n * Parameters used to create and initialise the ACL context.\n * @return\n * Pointer to ACL context structure that is used in future ACL\n * operations, or NULL on error, with error code set in rte_errno.\n * Possible rte_errno errors include:\n * - EINVAL - invalid parameter passed to function\n */\nstruct rte_acl_ctx *\nrte_acl_create(const struct rte_acl_param *param);\n\n/**\n * Find an existing ACL context object and return a pointer to it.\n *\n * @param name\n * Name of the ACL context as passed to rte_acl_create()\n * @return\n * Pointer to ACL context or NULL if object not found\n * with rte_errno set appropriately. Possible rte_errno values include:\n * - ENOENT - value not available for return\n */\nstruct rte_acl_ctx *\nrte_acl_find_existing(const char *name);\n\n/**\n * De-allocate all memory used by ACL context.\n *\n * @param ctx\n * ACL context to free\n */\nvoid\nrte_acl_free(struct rte_acl_ctx *ctx);\n\n/**\n * Add rules to an existing ACL context.\n * This function is not multi-thread safe.\n *\n * @param ctx\n * ACL context to add patterns to.\n * @param rules\n * Array of rules to add to the ACL context.\n * Note that all fields in rte_acl_rule structures are expected\n * to be in host byte order.\n * Each rule expected to be in the same format and not exceed size\n * specified at ACL context creation time.\n * @param num\n * Number of elements in the input array of rules.\n * @return\n * - -ENOMEM if there is no space in the ACL context for these rules.\n * - -EINVAL if the parameters are invalid.\n * - Zero if operation completed successfully.\n */\nint\nrte_acl_add_rules(struct rte_acl_ctx *ctx, const struct rte_acl_rule *rules,\n\tuint32_t num);\n\n/**\n * Delete all rules from the ACL context.\n * This function is not multi-thread safe.\n * Note that internal run-time structures are not affected.\n *\n * @param ctx\n * ACL context to delete rules from.\n */\nvoid\nrte_acl_reset_rules(struct rte_acl_ctx *ctx);\n\n/**\n * Analyze set of rules and build required internal run-time structures.\n * This function is not multi-thread safe.\n *\n * @param ctx\n * ACL context to build.\n * @param cfg\n * Pointer to struct rte_acl_config - defines build parameters.\n * @return\n * - -ENOMEM if couldn't allocate enough memory.\n * - -EINVAL if the parameters are invalid.\n * - Negative error code if operation failed.\n * - Zero if operation completed successfully.\n */\nint\nrte_acl_build(struct rte_acl_ctx *ctx, const struct rte_acl_config *cfg);\n\n/**\n * Delete all rules from the ACL context and\n * destroy all internal run-time structures.\n * This function is not multi-thread safe.\n *\n * @param ctx\n * ACL context to reset.\n */\nvoid\nrte_acl_reset(struct rte_acl_ctx *ctx);\n\n/**\n * Available implementations of ACL classify.\n */\nenum rte_acl_classify_alg {\n\tRTE_ACL_CLASSIFY_DEFAULT = 0,\n\tRTE_ACL_CLASSIFY_SCALAR = 1, /**< generic implementation. */\n\tRTE_ACL_CLASSIFY_SSE = 2, /**< requires SSE4.1 support. */\n\tRTE_ACL_CLASSIFY_AVX2 = 3, /**< requires AVX2 support. */\n\tRTE_ACL_CLASSIFY_NUM /* should always be the last one. */\n};\n\n/**\n * Perform search for a matching ACL rule for each input data buffer.\n * Each input data buffer can have up to *categories* matches.\n * That implies that results array should be big enough to hold\n * (categories * num) elements.\n * Also categories parameter should be either one or multiple of\n * RTE_ACL_RESULTS_MULTIPLIER and can't be bigger than RTE_ACL_MAX_CATEGORIES.\n * If more than one rule is applicable for given input buffer and\n * given category, then rule with highest priority will be returned as a match.\n * Note, that it is a caller's responsibility to ensure that input parameters\n * are valid and point to correct memory locations.\n *\n * @param ctx\n * ACL context to search with.\n * @param data\n * Array of pointers to input data buffers to perform search.\n * Note that all fields in input data buffers supposed to be in network\n * byte order (MSB).\n * @param results\n * Array of search results, *categories* results per each input data buffer.\n * @param num\n * Number of elements in the input data buffers array.\n * @param categories\n * Number of maximum possible matches for each input buffer, one possible\n * match per category.\n * @return\n * zero on successful completion.\n * -EINVAL for incorrect arguments.\n */\nextern int\nrte_acl_classify(const struct rte_acl_ctx *ctx,\n\t\t const uint8_t **data,\n\t\t uint32_t *results, uint32_t num,\n\t\t uint32_t categories);\n\n/**\n * Perform search using specified algorithm for a matching ACL rule for\n * each input data buffer.\n * Each input data buffer can have up to *categories* matches.\n * That implies that results array should be big enough to hold\n * (categories * num) elements.\n * Also categories parameter should be either one or multiple of\n * RTE_ACL_RESULTS_MULTIPLIER and can't be bigger than RTE_ACL_MAX_CATEGORIES.\n * If more than one rule is applicable for given input buffer and\n * given category, then rule with highest priority will be returned as a match.\n * Note, that it is a caller's responsibility to ensure that input parameters\n * are valid and point to correct memory locations.\n *\n * @param ctx\n * ACL context to search with.\n * @param data\n * Array of pointers to input data buffers to perform search.\n * Note that all fields in input data buffers supposed to be in network\n * byte order (MSB).\n * @param results\n * Array of search results, *categories* results per each input data buffer.\n * @param num\n * Number of elements in the input data buffers array.\n * @param categories\n * Number of maximum possible matches for each input buffer, one possible\n * match per category.\n * @param alg\n * Algorithm to be used for the search.\n * It is the caller responsibility to ensure that the value refers to the\n * existing algorithm, and that it could be run on the given CPU.\n * @return\n * zero on successful completion.\n * -EINVAL for incorrect arguments.\n */\nextern int\nrte_acl_classify_alg(const struct rte_acl_ctx *ctx,\n\t\t const uint8_t **data,\n\t\t uint32_t *results, uint32_t num,\n\t\t uint32_t categories,\n\t\t enum rte_acl_classify_alg alg);\n\n/*\n * Override the default classifier function for a given ACL context.\n * @param ctx\n * ACL context to change classify function for.\n * @param alg\n * New default classify algorithm for given ACL context.\n * It is the caller responsibility to ensure that the value refers to the\n * existing algorithm, and that it could be run on the given CPU.\n * @return\n * - -EINVAL if the parameters are invalid.\n * - Zero if operation completed successfully.\n */\nextern int\nrte_acl_set_ctx_classify(struct rte_acl_ctx *ctx,\n\tenum rte_acl_classify_alg alg);\n\n/**\n * Dump an ACL context structure to the console.\n *\n * @param ctx\n * ACL context to dump.\n */\nvoid\nrte_acl_dump(const struct rte_acl_ctx *ctx);\n\n/**\n * Dump all ACL context structures to the console.\n */\nvoid\nrte_acl_list_dump(void);\n\n/**\n * Legacy support for 7-tuple IPv4 and VLAN rule.\n * This structure and corresponding API is deprecated.\n */\nstruct rte_acl_ipv4vlan_rule {\n\tstruct rte_acl_rule_data data; /**< Miscellaneous data for the rule. */\n\tuint8_t proto; /**< IPv4 protocol ID. */\n\tuint8_t proto_mask; /**< IPv4 protocol ID mask. */\n\tuint16_t vlan; /**< VLAN ID. */\n\tuint16_t vlan_mask; /**< VLAN ID mask. */\n\tuint16_t domain; /**< VLAN domain. */\n\tuint16_t domain_mask; /**< VLAN domain mask. */\n\tuint32_t src_addr; /**< IPv4 source address. */\n\tuint32_t src_mask_len; /**< IPv4 source address mask. */\n\tuint32_t dst_addr; /**< IPv4 destination address. */\n\tuint32_t dst_mask_len; /**< IPv4 destination address mask. */\n\tuint16_t src_port_low; /**< L4 source port low. */\n\tuint16_t src_port_high; /**< L4 source port high. */\n\tuint16_t dst_port_low; /**< L4 destination port low. */\n\tuint16_t dst_port_high; /**< L4 destination port high. */\n};\n\n/**\n * Specifies fields layout inside rte_acl_rule for rte_acl_ipv4vlan_rule.\n */\nenum {\n\tRTE_ACL_IPV4VLAN_PROTO_FIELD,\n\tRTE_ACL_IPV4VLAN_VLAN1_FIELD,\n\tRTE_ACL_IPV4VLAN_VLAN2_FIELD,\n\tRTE_ACL_IPV4VLAN_SRC_FIELD,\n\tRTE_ACL_IPV4VLAN_DST_FIELD,\n\tRTE_ACL_IPV4VLAN_SRCP_FIELD,\n\tRTE_ACL_IPV4VLAN_DSTP_FIELD,\n\tRTE_ACL_IPV4VLAN_NUM_FIELDS\n};\n\n/**\n * Macro to define rule size for rte_acl_ipv4vlan_rule.\n */\n#define\tRTE_ACL_IPV4VLAN_RULE_SZ\t\\\n\tRTE_ACL_RULE_SZ(RTE_ACL_IPV4VLAN_NUM_FIELDS)\n\n/*\n * That effectively defines order of IPV4VLAN classifications:\n * - PROTO\n * - VLAN (TAG and DOMAIN)\n * - SRC IP ADDRESS\n * - DST IP ADDRESS\n * - PORTS (SRC and DST)\n */\nenum {\n\tRTE_ACL_IPV4VLAN_PROTO,\n\tRTE_ACL_IPV4VLAN_VLAN,\n\tRTE_ACL_IPV4VLAN_SRC,\n\tRTE_ACL_IPV4VLAN_DST,\n\tRTE_ACL_IPV4VLAN_PORTS,\n\tRTE_ACL_IPV4VLAN_NUM\n};\n\n/**\n * Add ipv4vlan rules to an existing ACL context.\n * This function is not multi-thread safe.\n *\n * @param ctx\n * ACL context to add patterns to.\n * @param rules\n * Array of rules to add to the ACL context.\n * Note that all fields in rte_acl_ipv4vlan_rule structures are expected\n * to be in host byte order.\n * @param num\n * Number of elements in the input array of rules.\n * @return\n * - -ENOMEM if there is no space in the ACL context for these rules.\n * - -EINVAL if the parameters are invalid.\n * - Zero if operation completed successfully.\n */\nint\nrte_acl_ipv4vlan_add_rules(struct rte_acl_ctx *ctx,\n\tconst struct rte_acl_ipv4vlan_rule *rules,\n\tuint32_t num);\n\n/**\n * Analyze set of ipv4vlan rules and build required internal\n * run-time structures.\n * This function is not multi-thread safe.\n *\n * @param ctx\n * ACL context to build.\n * @param layout\n * Layout of input data to search through.\n * @param num_categories\n * Maximum number of categories to use in that build.\n * @return\n * - -ENOMEM if couldn't allocate enough memory.\n * - -EINVAL if the parameters are invalid.\n * - Negative error code if operation failed.\n * - Zero if operation completed successfully.\n */\nint\nrte_acl_ipv4vlan_build(struct rte_acl_ctx *ctx,\n\tconst uint32_t layout[RTE_ACL_IPV4VLAN_NUM],\n\tuint32_t num_categories);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_ACL_H_ */\n" }, { "path": "lib/librte_acl/rte_acl_osdep.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ACL_OSDEP_H_\n#define _RTE_ACL_OSDEP_H_\n\n/**\n * @file\n *\n * RTE ACL DPDK/OS dependent file.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/*\n * Common defines.\n */\n\n#define DIM(x) RTE_DIM(x)\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#endif /* _RTE_ACL_OSDEP_H_ */\n" }, { "path": "lib/librte_acl/tb_mem.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \"tb_mem.h\"\n\n/*\n * Memory management routines for temporary memory.\n * That memory is used only during build phase and is released after\n * build is finished.\n * Note, that tb_pool/tb_alloc() are not supposed to return NULL.\n * Instead, in the case of failure to allocate memory,\n * it would do siglongjmp(pool->fail).\n * It is responsibility of the caller to save the proper context/environment,\n * in the pool->fail before calling tb_alloc() for the given pool first time.\n */\n\nstatic struct tb_mem_block *\ntb_pool(struct tb_mem_pool *pool, size_t sz)\n{\n\tstruct tb_mem_block *block;\n\tuint8_t *ptr;\n\tsize_t size;\n\n\tsize = sz + pool->alignment - 1;\n\tblock = calloc(1, size + sizeof(*pool->block));\n\tif (block == NULL) {\n\t\tRTE_LOG(ERR, MALLOC, \"%s(%zu)\\n failed, currently allocated \"\n\t\t\t\"by pool: %zu bytes\\n\", __func__, sz, pool->alloc);\n\t\tsiglongjmp(pool->fail, -ENOMEM);\n\t\treturn NULL;\n\t}\n\n\tblock->pool = pool;\n\n\tblock->next = pool->block;\n\tpool->block = block;\n\n\tpool->alloc += size;\n\n\tptr = (uint8_t *)(block + 1);\n\tblock->mem = RTE_PTR_ALIGN_CEIL(ptr, pool->alignment);\n\tblock->size = size - (block->mem - ptr);\n\n\treturn block;\n}\n\nvoid *\ntb_alloc(struct tb_mem_pool *pool, size_t size)\n{\n\tstruct tb_mem_block *block;\n\tvoid *ptr;\n\tsize_t new_sz;\n\n\tsize = RTE_ALIGN_CEIL(size, pool->alignment);\n\n\tblock = pool->block;\n\tif (block == NULL || block->size < size) {\n\t\tnew_sz = (size > pool->min_alloc) ? size : pool->min_alloc;\n\t\tblock = tb_pool(pool, new_sz);\n\t}\n\tptr = block->mem;\n\tblock->size -= size;\n\tblock->mem += size;\n\treturn ptr;\n}\n\nvoid\ntb_free_pool(struct tb_mem_pool *pool)\n{\n\tstruct tb_mem_block *next, *block;\n\n\tfor (block = pool->block; block != NULL; block = next) {\n\t\tnext = block->next;\n\t\tfree(block);\n\t}\n\tpool->block = NULL;\n\tpool->alloc = 0;\n}\n" }, { "path": "lib/librte_acl/tb_mem.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _TB_MEM_H_\n#define _TB_MEM_H_\n\n/**\n * @file\n *\n * RTE ACL temporary (build phase) memory management.\n * Contains structures and functions to manage temporary (used by build only)\n * memory. Memory allocated in large blocks to speed 'free' when trie is\n * destructed (finish of build phase).\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n\nstruct tb_mem_block {\n\tstruct tb_mem_block *next;\n\tstruct tb_mem_pool *pool;\n\tsize_t size;\n\tuint8_t *mem;\n};\n\nstruct tb_mem_pool {\n\tstruct tb_mem_block *block;\n\tsize_t alignment;\n\tsize_t min_alloc;\n\tsize_t alloc;\n\t/* jump target in case of memory allocation failure. */\n\tsigjmp_buf fail;\n};\n\nvoid *tb_alloc(struct tb_mem_pool *pool, size_t size);\nvoid tb_free_pool(struct tb_mem_pool *pool);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _TB_MEM_H_ */\n" }, { "path": "lib/librte_cfgfile/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_cfgfile.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_cfgfile_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_CFGFILE) += rte_cfgfile.c\n\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_CFGFILE)-include += rte_cfgfile.h\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_CFGFILE) += lib/librte_eal\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_cfgfile/rte_cfgfile.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_cfgfile.h\"\n\nstruct rte_cfgfile_section {\n\tchar name[CFG_NAME_LEN];\n\tint num_entries;\n\tstruct rte_cfgfile_entry *entries[0];\n};\n\nstruct rte_cfgfile {\n\tint flags;\n\tint num_sections;\n\tstruct rte_cfgfile_section *sections[0];\n};\n\n/** when we resize a file structure, how many extra entries\n * for new sections do we add in */\n#define CFG_ALLOC_SECTION_BATCH 8\n/** when we resize a section structure, how many extra entries\n * for new entries do we add in */\n#define CFG_ALLOC_ENTRY_BATCH 16\n\nstatic unsigned\n_strip(char *str, unsigned len)\n{\n\tint newlen = len;\n\tif (len == 0)\n\t\treturn 0;\n\n\tif (isspace(str[len-1])) {\n\t\t/* strip trailing whitespace */\n\t\twhile (newlen > 0 && isspace(str[newlen - 1]))\n\t\t\tstr[--newlen] = '\\0';\n\t}\n\n\tif (isspace(str[0])) {\n\t\t/* strip leading whitespace */\n\t\tint i, start = 1;\n\t\twhile (isspace(str[start]) && start < newlen)\n\t\t\tstart++\n\t\t\t; /* do nothing */\n\t\tnewlen -= start;\n\t\tfor (i = 0; i < newlen; i++)\n\t\t\tstr[i] = str[i+start];\n\t\tstr[i] = '\\0';\n\t}\n\treturn newlen;\n}\n\nstruct rte_cfgfile *\nrte_cfgfile_load(const char *filename, int flags)\n{\n\tint allocated_sections = CFG_ALLOC_SECTION_BATCH;\n\tint allocated_entries = 0;\n\tint curr_section = -1;\n\tint curr_entry = -1;\n\tchar buffer[256] = {0};\n\tint lineno = 0;\n\tstruct rte_cfgfile *cfg = NULL;\n\n\tFILE *f = fopen(filename, \"r\");\n\tif (f == NULL)\n\t\treturn NULL;\n\n\tcfg = malloc(sizeof(*cfg) + sizeof(cfg->sections[0]) *\n\t\tallocated_sections);\n\tif (cfg == NULL)\n\t\tgoto error2;\n\n\tmemset(cfg->sections, 0, sizeof(cfg->sections[0]) * allocated_sections);\n\n\twhile (fgets(buffer, sizeof(buffer), f) != NULL) {\n\t\tchar *pos = NULL;\n\t\tsize_t len = strnlen(buffer, sizeof(buffer));\n\t\tlineno++;\n\t\tif ((len >= sizeof(buffer) - 1) && (buffer[len-1] != '\\n')) {\n\t\t\tprintf(\"Error line %d - no \\\\n found on string. \"\n\t\t\t\t\t\"Check if line too long\\n\", lineno);\n\t\t\tgoto error1;\n\t\t}\n\t\tpos = memchr(buffer, ';', sizeof(buffer));\n\t\tif (pos != NULL) {\n\t\t\t*pos = '\\0';\n\t\t\tlen = pos - buffer;\n\t\t}\n\n\t\tlen = _strip(buffer, len);\n\t\tif (buffer[0] != '[' && memchr(buffer, '=', len) == NULL)\n\t\t\tcontinue;\n\n\t\tif (buffer[0] == '[') {\n\t\t\t/* section heading line */\n\t\t\tchar *end = memchr(buffer, ']', len);\n\t\t\tif (end == NULL) {\n\t\t\t\tprintf(\"Error line %d - no terminating '['\"\n\t\t\t\t\t\"character found\\n\", lineno);\n\t\t\t\tgoto error1;\n\t\t\t}\n\t\t\t*end = '\\0';\n\t\t\t_strip(&buffer[1], end - &buffer[1]);\n\n\t\t\t/* close off old section and add start new one */\n\t\t\tif (curr_section >= 0)\n\t\t\t\tcfg->sections[curr_section]->num_entries =\n\t\t\t\t\tcurr_entry + 1;\n\t\t\tcurr_section++;\n\n\t\t\t/* resize overall struct if we don't have room for more\n\t\t\tsections */\n\t\t\tif (curr_section == allocated_sections) {\n\t\t\t\tallocated_sections += CFG_ALLOC_SECTION_BATCH;\n\t\t\t\tstruct rte_cfgfile *n_cfg = realloc(cfg,\n\t\t\t\t\tsizeof(*cfg) + sizeof(cfg->sections[0])\n\t\t\t\t\t* allocated_sections);\n\t\t\t\tif (n_cfg == NULL) {\n\t\t\t\t\tprintf(\"Error - no more memory\\n\");\n\t\t\t\t\tgoto error1;\n\t\t\t\t}\n\t\t\t\tcfg = n_cfg;\n\t\t\t}\n\n\t\t\t/* allocate space for new section */\n\t\t\tallocated_entries = CFG_ALLOC_ENTRY_BATCH;\n\t\t\tcurr_entry = -1;\n\t\t\tcfg->sections[curr_section] = malloc(\n\t\t\t\tsizeof(*cfg->sections[0]) +\n\t\t\t\tsizeof(cfg->sections[0]->entries[0]) *\n\t\t\t\tallocated_entries);\n\t\t\tif (cfg->sections[curr_section] == NULL) {\n\t\t\t\tprintf(\"Error - no more memory\\n\");\n\t\t\t\tgoto error1;\n\t\t\t}\n\n\t\t\tsnprintf(cfg->sections[curr_section]->name,\n\t\t\t\t\tsizeof(cfg->sections[0]->name),\n\t\t\t\t\t\"%s\", &buffer[1]);\n\t\t} else {\n\t\t\t/* value line */\n\t\t\tif (curr_section < 0) {\n\t\t\t\tprintf(\"Error line %d - value outside of\"\n\t\t\t\t\t\"section\\n\", lineno);\n\t\t\t\tgoto error1;\n\t\t\t}\n\n\t\t\tstruct rte_cfgfile_section *sect =\n\t\t\t\tcfg->sections[curr_section];\n\t\t\tchar *split[2];\n\t\t\tif (rte_strsplit(buffer, sizeof(buffer), split, 2, '=')\n\t\t\t\t!= 2) {\n\t\t\t\tprintf(\"Error at line %d - cannot split \"\n\t\t\t\t\t\"string\\n\", lineno);\n\t\t\t\tgoto error1;\n\t\t\t}\n\n\t\t\tcurr_entry++;\n\t\t\tif (curr_entry == allocated_entries) {\n\t\t\t\tallocated_entries += CFG_ALLOC_ENTRY_BATCH;\n\t\t\t\tstruct rte_cfgfile_section *n_sect = realloc(\n\t\t\t\t\tsect, sizeof(*sect) +\n\t\t\t\t\tsizeof(sect->entries[0]) *\n\t\t\t\t\tallocated_entries);\n\t\t\t\tif (n_sect == NULL) {\n\t\t\t\t\tprintf(\"Error - no more memory\\n\");\n\t\t\t\t\tgoto error1;\n\t\t\t\t}\n\t\t\t\tsect = cfg->sections[curr_section] = n_sect;\n\t\t\t}\n\n\t\t\tsect->entries[curr_entry] = malloc(\n\t\t\t\tsizeof(*sect->entries[0]));\n\t\t\tif (sect->entries[curr_entry] == NULL) {\n\t\t\t\tprintf(\"Error - no more memory\\n\");\n\t\t\t\tgoto error1;\n\t\t\t}\n\n\t\t\tstruct rte_cfgfile_entry *entry = sect->entries[\n\t\t\t\tcurr_entry];\n\t\t\tsnprintf(entry->name, sizeof(entry->name), \"%s\",\n\t\t\t\tsplit[0]);\n\t\t\tsnprintf(entry->value, sizeof(entry->value), \"%s\",\n\t\t\t\tsplit[1]);\n\t\t\t_strip(entry->name, strnlen(entry->name,\n\t\t\t\tsizeof(entry->name)));\n\t\t\t_strip(entry->value, strnlen(entry->value,\n\t\t\t\tsizeof(entry->value)));\n\t\t}\n\t}\n\tfclose(f);\n\tcfg->flags = flags;\n\tcfg->num_sections = curr_section + 1;\n\t/* curr_section will still be -1 if we have an empty file */\n\tif (curr_section >= 0)\n\t\tcfg->sections[curr_section]->num_entries = curr_entry + 1;\n\treturn cfg;\n\nerror1:\n\trte_cfgfile_close(cfg);\nerror2:\n\tfclose(f);\n\treturn NULL;\n}\n\n\nint rte_cfgfile_close(struct rte_cfgfile *cfg)\n{\n\tint i, j;\n\n\tif (cfg == NULL)\n\t\treturn -1;\n\n\tfor (i = 0; i < cfg->num_sections; i++) {\n\t\tif (cfg->sections[i] != NULL) {\n\t\t\tif (cfg->sections[i]->num_entries) {\n\t\t\t\tfor (j = 0; j < cfg->sections[i]->num_entries;\n\t\t\t\t\tj++) {\n\t\t\t\t\tif (cfg->sections[i]->entries[j] !=\n\t\t\t\t\t\tNULL)\n\t\t\t\t\t\tfree(cfg->sections[i]->\n\t\t\t\t\t\t\tentries[j]);\n\t\t\t\t}\n\t\t\t}\n\t\t\tfree(cfg->sections[i]);\n\t\t}\n\t}\n\tfree(cfg);\n\n\treturn 0;\n}\n\nint\nrte_cfgfile_num_sections(struct rte_cfgfile *cfg, const char *sectionname,\nsize_t length)\n{\n\tint i;\n\tint num_sections = 0;\n\tfor (i = 0; i < cfg->num_sections; i++) {\n\t\tif (strncmp(cfg->sections[i]->name, sectionname, length) == 0)\n\t\t\tnum_sections++;\n\t}\n\treturn num_sections;\n}\n\nint\nrte_cfgfile_sections(struct rte_cfgfile *cfg, char *sections[],\n\tint max_sections)\n{\n\tint i;\n\n\tfor (i = 0; i < cfg->num_sections && i < max_sections; i++)\n\t\tsnprintf(sections[i], CFG_NAME_LEN, \"%s\",\n\t\tcfg->sections[i]->name);\n\n\treturn i;\n}\n\nstatic const struct rte_cfgfile_section *\n_get_section(struct rte_cfgfile *cfg, const char *sectionname)\n{\n\tint i;\n\tfor (i = 0; i < cfg->num_sections; i++) {\n\t\tif (strncmp(cfg->sections[i]->name, sectionname,\n\t\t\t\tsizeof(cfg->sections[0]->name)) == 0)\n\t\t\treturn cfg->sections[i];\n\t}\n\treturn NULL;\n}\n\nint\nrte_cfgfile_has_section(struct rte_cfgfile *cfg, const char *sectionname)\n{\n\treturn (_get_section(cfg, sectionname) != NULL);\n}\n\nint\nrte_cfgfile_section_num_entries(struct rte_cfgfile *cfg,\n\tconst char *sectionname)\n{\n\tconst struct rte_cfgfile_section *s = _get_section(cfg, sectionname);\n\tif (s == NULL)\n\t\treturn -1;\n\treturn s->num_entries;\n}\n\n\nint\nrte_cfgfile_section_entries(struct rte_cfgfile *cfg, const char *sectionname,\n\t\tstruct rte_cfgfile_entry *entries, int max_entries)\n{\n\tint i;\n\tconst struct rte_cfgfile_section *sect = _get_section(cfg, sectionname);\n\tif (sect == NULL)\n\t\treturn -1;\n\tfor (i = 0; i < max_entries && i < sect->num_entries; i++)\n\t\tentries[i] = *sect->entries[i];\n\treturn i;\n}\n\nconst char *\nrte_cfgfile_get_entry(struct rte_cfgfile *cfg, const char *sectionname,\n\t\tconst char *entryname)\n{\n\tint i;\n\tconst struct rte_cfgfile_section *sect = _get_section(cfg, sectionname);\n\tif (sect == NULL)\n\t\treturn NULL;\n\tfor (i = 0; i < sect->num_entries; i++)\n\t\tif (strncmp(sect->entries[i]->name, entryname, CFG_NAME_LEN)\n\t\t\t== 0)\n\t\t\treturn sect->entries[i]->value;\n\treturn NULL;\n}\n\nint\nrte_cfgfile_has_entry(struct rte_cfgfile *cfg, const char *sectionname,\n\t\tconst char *entryname)\n{\n\treturn (rte_cfgfile_get_entry(cfg, sectionname, entryname) != NULL);\n}\n" }, { "path": "lib/librte_cfgfile/rte_cfgfile.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_CFGFILE_H__\n#define __INCLUDE_RTE_CFGFILE_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n* @file\n* RTE Configuration File\n*\n* This library allows reading application defined parameters from standard\n* format configuration file.\n*\n***/\n\n#define CFG_NAME_LEN 32\n#define CFG_VALUE_LEN 64\n\n/** Configuration file */\nstruct rte_cfgfile;\n\n/** Configuration file entry */\nstruct rte_cfgfile_entry {\n\tchar name[CFG_NAME_LEN]; /**< Name */\n\tchar value[CFG_VALUE_LEN]; /**< Value */\n};\n\n/**\n* Open config file\n*\n* @param filename\n* Config file name\n* @param flags\n* Config file flags, Reserved for future use. Must be set to 0.\n* @return\n* Handle to configuration file\n*/\nstruct rte_cfgfile *rte_cfgfile_load(const char *filename, int flags);\n\n/**\n* Get number of sections in config file\n*\n* @param cfg\n* Config file\n* @param sec_name\n* Section name\n* @param length\n* Maximum section name length\n* @return\n* 0 on success, error code otherwise\n*/\nint rte_cfgfile_num_sections(struct rte_cfgfile *cfg, const char *sec_name,\n\tsize_t length);\n\n/**\n* Get name of all config file sections.\n*\n* Fills in the array sections with the name of all the sections in the file\n* (up to the number of max_sections sections).\n*\n* @param cfg\n* Config file\n* @param sections\n* Array containing section names after successful invocation. Each elemen\n* of this array should be preallocated by the user with at least\n* CFG_NAME_LEN characters.\n* @param max_sections\n* Maximum number of section names to be stored in sections array\n* @return\n* 0 on success, error code otherwise\n*/\nint rte_cfgfile_sections(struct rte_cfgfile *cfg, char *sections[],\n\tint max_sections);\n\n/**\n* Check if given section exists in config file\n*\n* @param cfg\n* Config file\n* @param sectionname\n* Section name\n* @return\n* TRUE (value different than 0) if section exists, FALSE (value 0) otherwise\n*/\nint rte_cfgfile_has_section(struct rte_cfgfile *cfg, const char *sectionname);\n\n/**\n* Get number of entries in given config file section\n*\n* @param cfg\n* Config file\n* @param sectionname\n* Section name\n* @return\n* Number of entries in section\n*/\nint rte_cfgfile_section_num_entries(struct rte_cfgfile *cfg,\n\tconst char *sectionname);\n\n/** Get section entries as key-value pairs\n*\n* @param cfg\n* Config file\n* @param sectionname\n* Section name\n* @param entries\n* Pre-allocated array of at least max_entries entries where the section\n* entries are stored as key-value pair after successful invocation\n* @param max_entries\n* Maximum number of section entries to be stored in entries array\n* @return\n* 0 on success, error code otherwise\n*/\nint rte_cfgfile_section_entries(struct rte_cfgfile *cfg,\n\tconst char *sectionname,\n\tstruct rte_cfgfile_entry *entries,\n\tint max_entries);\n\n/** Get value of the named entry in named config file section\n*\n* @param cfg\n* Config file\n* @param sectionname\n* Section name\n* @param entryname\n* Entry name\n* @return\n* Entry value\n*/\nconst char *rte_cfgfile_get_entry(struct rte_cfgfile *cfg,\n\tconst char *sectionname,\n\tconst char *entryname);\n\n/** Check if given entry exists in named config file section\n*\n* @param cfg\n* Config file\n* @param sectionname\n* Section name\n* @param entryname\n* Entry name\n* @return\n* TRUE (value different than 0) if entry exists, FALSE (value 0) otherwise\n*/\nint rte_cfgfile_has_entry(struct rte_cfgfile *cfg, const char *sectionname,\n\tconst char *entryname);\n\n/** Close config file\n*\n* @param cfg\n* Config file\n* @return\n* 0 on success, error code otherwise\n*/\nint rte_cfgfile_close(struct rte_cfgfile *cfg);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_cmdline/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_cmdline.a\n\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3\n\nEXPORT_MAP := rte_cmdline_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) := cmdline.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += cmdline_cirbuf.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += cmdline_parse.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += cmdline_parse_etheraddr.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += cmdline_parse_ipaddr.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += cmdline_parse_num.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += cmdline_parse_string.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += cmdline_rdline.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += cmdline_vt100.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += cmdline_socket.c\nSRCS-$(CONFIG_RTE_LIBRTE_CMDLINE) += cmdline_parse_portlist.c\n\nCFLAGS += -D_GNU_SOURCE\n\n# install includes\nINCS := cmdline.h cmdline_parse.h cmdline_parse_num.h cmdline_parse_ipaddr.h\nINCS += cmdline_parse_etheraddr.h cmdline_parse_string.h cmdline_rdline.h\nINCS += cmdline_vt100.h cmdline_socket.h cmdline_cirbuf.h cmdline_parse_portlist.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_CMDLINE)-include := $(INCS)\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_CMDLINE) += lib/librte_eal\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_cmdline/cmdline.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"cmdline_parse.h\"\n#include \"cmdline_rdline.h\"\n#include \"cmdline.h\"\n\nstatic void\ncmdline_valid_buffer(struct rdline *rdl, const char *buf,\n\t\t __attribute__((unused)) unsigned int size)\n{\n\tstruct cmdline *cl = rdl->opaque;\n\tint ret;\n\tret = cmdline_parse(cl, buf);\n\tif (ret == CMDLINE_PARSE_AMBIGUOUS)\n\t\tcmdline_printf(cl, \"Ambiguous command\\n\");\n\telse if (ret == CMDLINE_PARSE_NOMATCH)\n\t\tcmdline_printf(cl, \"Command not found\\n\");\n\telse if (ret == CMDLINE_PARSE_BAD_ARGS)\n\t\tcmdline_printf(cl, \"Bad arguments\\n\");\n}\n\nstatic int\ncmdline_complete_buffer(struct rdline *rdl, const char *buf,\n\t\t\tchar *dstbuf, unsigned int dstsize,\n\t\t\tint *state)\n{\n\tstruct cmdline *cl = rdl->opaque;\n\treturn cmdline_complete(cl, buf, state, dstbuf, dstsize);\n}\n\nint\ncmdline_write_char(struct rdline *rdl, char c)\n{\n\tint ret = -1;\n\tstruct cmdline *cl;\n\n\tif (!rdl)\n\t\treturn -1;\n\n\tcl = rdl->opaque;\n\n\tif (cl->s_out >= 0)\n\t\tret = write(cl->s_out, &c, 1);\n\n\treturn ret;\n}\n\n\nvoid\ncmdline_set_prompt(struct cmdline *cl, const char *prompt)\n{\n\tif (!cl || !prompt)\n\t\treturn;\n\tsnprintf(cl->prompt, sizeof(cl->prompt), \"%s\", prompt);\n}\n\nstruct cmdline *\ncmdline_new(cmdline_parse_ctx_t *ctx, const char *prompt, int s_in, int s_out)\n{\n\tstruct cmdline *cl;\n\n\tif (!ctx || !prompt)\n\t\treturn NULL;\n\n\tcl = malloc(sizeof(struct cmdline));\n\tif (cl == NULL)\n\t\treturn NULL;\n\tmemset(cl, 0, sizeof(struct cmdline));\n\tcl->s_in = s_in;\n\tcl->s_out = s_out;\n\tcl->ctx = ctx;\n\n\trdline_init(&cl->rdl, cmdline_write_char,\n\t\t cmdline_valid_buffer, cmdline_complete_buffer);\n\tcl->rdl.opaque = cl;\n\tcmdline_set_prompt(cl, prompt);\n\trdline_newline(&cl->rdl, cl->prompt);\n\n\treturn cl;\n}\n\nvoid\ncmdline_free(struct cmdline *cl)\n{\n\tdprintf(\"called\\n\");\n\n\tif (!cl)\n\t\treturn;\n\n\tif (cl->s_in > 2)\n\t\tclose(cl->s_in);\n\tif (cl->s_out != cl->s_in && cl->s_out > 2)\n\t\tclose(cl->s_out);\n\tfree(cl);\n}\n\nvoid\ncmdline_printf(const struct cmdline *cl, const char *fmt, ...)\n{\n\tva_list ap;\n\n\tif (!cl || !fmt)\n\t\treturn;\n\n#ifdef _GNU_SOURCE\n\tif (cl->s_out < 0)\n\t\treturn;\n\tva_start(ap, fmt);\n\tvdprintf(cl->s_out, fmt, ap);\n\tva_end(ap);\n#else\n\tint ret;\n\tchar *buf;\n\n\tif (cl->s_out < 0)\n\t\treturn;\n\n\tbuf = malloc(BUFSIZ);\n\tif (buf == NULL)\n\t\treturn;\n\tva_start(ap, fmt);\n\tret = vsnprintf(buf, BUFSIZ, fmt, ap);\n\tva_end(ap);\n\tif (ret < 0) {\n\t\tfree(buf);\n\t\treturn;\n\t}\n\tif (ret >= BUFSIZ)\n\t\tret = BUFSIZ - 1;\n\twrite(cl->s_out, buf, ret);\n\tfree(buf);\n#endif\n}\n\nint\ncmdline_in(struct cmdline *cl, const char *buf, int size)\n{\n\tconst char *history, *buffer;\n\tsize_t histlen, buflen;\n\tint ret = 0;\n\tint i, same;\n\n\tif (!cl || !buf)\n\t\treturn -1;\n\n\tfor (i=0; irdl, buf[i]);\n\n\t\tif (ret == RDLINE_RES_VALIDATED) {\n\t\t\tbuffer = rdline_get_buffer(&cl->rdl);\n\t\t\thistory = rdline_get_history_item(&cl->rdl, 0);\n\t\t\tif (history) {\n\t\t\t\thistlen = strnlen(history, RDLINE_BUF_SIZE);\n\t\t\t\tsame = !memcmp(buffer, history, histlen) &&\n\t\t\t\t\tbuffer[histlen] == '\\n';\n\t\t\t}\n\t\t\telse\n\t\t\t\tsame = 0;\n\t\t\tbuflen = strnlen(buffer, RDLINE_BUF_SIZE);\n\t\t\tif (buflen > 1 && !same)\n\t\t\t\trdline_add_history(&cl->rdl, buffer);\n\t\t\trdline_newline(&cl->rdl, cl->prompt);\n\t\t}\n\t\telse if (ret == RDLINE_RES_EOF)\n\t\t\treturn -1;\n\t\telse if (ret == RDLINE_RES_EXITED)\n\t\t\treturn -1;\n\t}\n\treturn i;\n}\n\nvoid\ncmdline_quit(struct cmdline *cl)\n{\n\tif (!cl)\n\t\treturn;\n\trdline_quit(&cl->rdl);\n}\n\nint\ncmdline_poll(struct cmdline *cl)\n{\n\tstruct pollfd pfd;\n\tint status;\n\tssize_t read_status;\n\tchar c;\n\n\tif (!cl)\n\t\treturn -EINVAL;\n\telse if (cl->rdl.status == RDLINE_EXITED)\n\t\treturn RDLINE_EXITED;\n\n\tpfd.fd = cl->s_in;\n\tpfd.events = POLLIN;\n\tpfd.revents = 0;\n\n\tstatus = poll(&pfd, 1, 0);\n\tif (status < 0)\n\t\treturn status;\n\telse if (status > 0) {\n\t\tc = -1;\n\t\tread_status = read(cl->s_in, &c, 1);\n\t\tif (read_status < 0)\n\t\t\treturn read_status;\n\n\t\tstatus = cmdline_in(cl, &c, 1);\n\t\tif (status < 0 && cl->rdl.status != RDLINE_EXITED)\n\t\t\treturn status;\n\t}\n\n\treturn cl->rdl.status;\n}\n\nvoid\ncmdline_interact(struct cmdline *cl)\n{\n\tchar c;\n\n\tif (!cl)\n\t\treturn;\n\n\tc = -1;\n\twhile (1) {\n\t\tif (read(cl->s_in, &c, 1) <= 0)\n\t\t\tbreak;\n\t\tif (cmdline_in(cl, &c, 1) < 0)\n\t\t\tbreak;\n\t}\n}\n" }, { "path": "lib/librte_cmdline/cmdline.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _CMDLINE_H_\n#define _CMDLINE_H_\n\n#include \n#include \n\n/**\n * @file\n *\n * Command line API\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct cmdline {\n\tint s_in;\n\tint s_out;\n\tcmdline_parse_ctx_t *ctx;\n\tstruct rdline rdl;\n\tchar prompt[RDLINE_PROMPT_SIZE];\n\tstruct termios oldterm;\n};\n\nstruct cmdline *cmdline_new(cmdline_parse_ctx_t *ctx, const char *prompt, int s_in, int s_out);\nvoid cmdline_set_prompt(struct cmdline *cl, const char *prompt);\nvoid cmdline_free(struct cmdline *cl);\nvoid cmdline_printf(const struct cmdline *cl, const char *fmt, ...)\n\t__attribute__((format(printf,2,3)));\nint cmdline_in(struct cmdline *cl, const char *buf, int size);\nint cmdline_write_char(struct rdline *rdl, char c);\n\n/**\n * This function is nonblocking equivalent of ``cmdline_interact()``. It polls\n * *cl* for one character and interpret it. If return value is *RDLINE_EXITED*\n * it mean that ``cmdline_quit()`` was invoked.\n *\n * @param cl\n * The command line object.\n *\n * @return\n * On success return object status - one of *enum rdline_status*.\n * On error return negative value.\n */\nint cmdline_poll(struct cmdline *cl);\n\nvoid cmdline_interact(struct cmdline *cl);\nvoid cmdline_quit(struct cmdline *cl);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _CMDLINE_SOCKET_H_ */\n" }, { "path": "lib/librte_cmdline/cmdline_cirbuf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \"cmdline_cirbuf.h\"\n\n\nint\ncirbuf_init(struct cirbuf *cbuf, char *buf, unsigned int start, unsigned int maxlen)\n{\n\tif (!cbuf || !buf)\n\t\treturn -EINVAL;\n\tcbuf->maxlen = maxlen;\n\tcbuf->len = 0;\n\tcbuf->start = start;\n\tcbuf->end = start;\n\tcbuf->buf = buf;\n\treturn 0;\n}\n\n/* multiple add */\n\nint\ncirbuf_add_buf_head(struct cirbuf *cbuf, const char *c, unsigned int n)\n{\n\tunsigned int e;\n\n\tif (!cbuf || !c || !n || n > CIRBUF_GET_FREELEN(cbuf))\n\t\treturn -EINVAL;\n\n\te = CIRBUF_IS_EMPTY(cbuf) ? 1 : 0;\n\n\tif (n < cbuf->start + e) {\n\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", 0, cbuf->start - n + e, n);\n\t\tmemcpy(cbuf->buf + cbuf->start - n + e, c, n);\n\t}\n\telse {\n\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", + n - (cbuf->start + e), 0,\n\t\t\tcbuf->start + e);\n\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", cbuf->maxlen - n +\n\t\t\t(cbuf->start + e), 0, n - (cbuf->start + e));\n\t\tmemcpy(cbuf->buf, c + n - (cbuf->start + e) , cbuf->start + e);\n\t\tmemcpy(cbuf->buf + cbuf->maxlen - n + (cbuf->start + e), c,\n\t\t n - (cbuf->start + e));\n\t}\n\tcbuf->len += n;\n\tcbuf->start += (cbuf->maxlen - n + e);\n\tcbuf->start %= cbuf->maxlen;\n\treturn n;\n}\n\n/* multiple add */\n\nint\ncirbuf_add_buf_tail(struct cirbuf *cbuf, const char *c, unsigned int n)\n{\n\tunsigned int e;\n\n\tif (!cbuf || !c || !n || n > CIRBUF_GET_FREELEN(cbuf))\n\t\treturn -EINVAL;\n\n\te = CIRBUF_IS_EMPTY(cbuf) ? 1 : 0;\n\n\tif (n < cbuf->maxlen - cbuf->end - 1 + e) {\n\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", 0, cbuf->end + !e, n);\n\t\tmemcpy(cbuf->buf + cbuf->end + !e, c, n);\n\t}\n\telse {\n\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", cbuf->end + !e, 0,\n\t\t\tcbuf->maxlen - cbuf->end - 1 + e);\n\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", cbuf->maxlen - cbuf->end - 1 +\n\t\t\te, 0, n - cbuf->maxlen + cbuf->end + 1 - e);\n\t\tmemcpy(cbuf->buf + cbuf->end + !e, c, cbuf->maxlen -\n\t\t cbuf->end - 1 + e);\n\t\tmemcpy(cbuf->buf, c + cbuf->maxlen - cbuf->end - 1 + e,\n\t\t n - cbuf->maxlen + cbuf->end + 1 - e);\n\t}\n\tcbuf->len += n;\n\tcbuf->end += n - e;\n\tcbuf->end %= cbuf->maxlen;\n\treturn n;\n}\n\n/* add at head */\n\nstatic inline void\n__cirbuf_add_head(struct cirbuf * cbuf, char c)\n{\n\tif (!CIRBUF_IS_EMPTY(cbuf)) {\n\t\tcbuf->start += (cbuf->maxlen - 1);\n\t\tcbuf->start %= cbuf->maxlen;\n\t}\n\tcbuf->buf[cbuf->start] = c;\n\tcbuf->len ++;\n}\n\nint\ncirbuf_add_head_safe(struct cirbuf * cbuf, char c)\n{\n\tif (cbuf && !CIRBUF_IS_FULL(cbuf)) {\n\t\t__cirbuf_add_head(cbuf, c);\n\t\treturn 0;\n\t}\n\treturn -EINVAL;\n}\n\nvoid\ncirbuf_add_head(struct cirbuf * cbuf, char c)\n{\n\t__cirbuf_add_head(cbuf, c);\n}\n\n/* add at tail */\n\nstatic inline void\n__cirbuf_add_tail(struct cirbuf * cbuf, char c)\n{\n\tif (!CIRBUF_IS_EMPTY(cbuf)) {\n\t\tcbuf->end ++;\n\t\tcbuf->end %= cbuf->maxlen;\n\t}\n\tcbuf->buf[cbuf->end] = c;\n\tcbuf->len ++;\n}\n\nint\ncirbuf_add_tail_safe(struct cirbuf * cbuf, char c)\n{\n\tif (cbuf && !CIRBUF_IS_FULL(cbuf)) {\n\t\t__cirbuf_add_tail(cbuf, c);\n\t\treturn 0;\n\t}\n\treturn -EINVAL;\n}\n\nvoid\ncirbuf_add_tail(struct cirbuf * cbuf, char c)\n{\n\t__cirbuf_add_tail(cbuf, c);\n}\n\n\nstatic inline void\n__cirbuf_shift_left(struct cirbuf *cbuf)\n{\n\tunsigned int i;\n\tchar tmp = cbuf->buf[cbuf->start];\n\n\tfor (i=0 ; ilen ; i++) {\n\t\tcbuf->buf[(cbuf->start+i)%cbuf->maxlen] =\n\t\t\tcbuf->buf[(cbuf->start+i+1)%cbuf->maxlen];\n\t}\n\tcbuf->buf[(cbuf->start-1+cbuf->maxlen)%cbuf->maxlen] = tmp;\n\tcbuf->start += (cbuf->maxlen - 1);\n\tcbuf->start %= cbuf->maxlen;\n\tcbuf->end += (cbuf->maxlen - 1);\n\tcbuf->end %= cbuf->maxlen;\n}\n\nstatic inline void\n__cirbuf_shift_right(struct cirbuf *cbuf)\n{\n\tunsigned int i;\n\tchar tmp = cbuf->buf[cbuf->end];\n\n\tfor (i=0 ; ilen ; i++) {\n\t\tcbuf->buf[(cbuf->end+cbuf->maxlen-i)%cbuf->maxlen] =\n\t\t\tcbuf->buf[(cbuf->end+cbuf->maxlen-i-1)%cbuf->maxlen];\n\t}\n\tcbuf->buf[(cbuf->end+1)%cbuf->maxlen] = tmp;\n\tcbuf->start += 1;\n\tcbuf->start %= cbuf->maxlen;\n\tcbuf->end += 1;\n\tcbuf->end %= cbuf->maxlen;\n}\n\n/* XXX we could do a better algorithm here... */\nint\ncirbuf_align_left(struct cirbuf * cbuf)\n{\n\tif (!cbuf)\n\t\treturn -EINVAL;\n\n\tif (cbuf->start < cbuf->maxlen/2) {\n\t\twhile (cbuf->start != 0) {\n\t\t\t__cirbuf_shift_left(cbuf);\n\t\t}\n\t}\n\telse {\n\t\twhile (cbuf->start != 0) {\n\t\t\t__cirbuf_shift_right(cbuf);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/* XXX we could do a better algorithm here... */\nint\ncirbuf_align_right(struct cirbuf * cbuf)\n{\n\tif (!cbuf)\n\t\treturn -EINVAL;\n\n\tif (cbuf->start >= cbuf->maxlen/2) {\n\t\twhile (cbuf->end != cbuf->maxlen-1) {\n\t\t\t__cirbuf_shift_left(cbuf);\n\t\t}\n\t}\n\telse {\n\t\twhile (cbuf->start != cbuf->maxlen-1) {\n\t\t\t__cirbuf_shift_right(cbuf);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/* buffer del */\n\nint\ncirbuf_del_buf_head(struct cirbuf *cbuf, unsigned int size)\n{\n\tif (!cbuf || !size || size > CIRBUF_GET_LEN(cbuf))\n\t\treturn -EINVAL;\n\n\tcbuf->len -= size;\n\tif (CIRBUF_IS_EMPTY(cbuf)) {\n\t\tcbuf->start += size - 1;\n\t\tcbuf->start %= cbuf->maxlen;\n\t}\n\telse {\n\t\tcbuf->start += size;\n\t\tcbuf->start %= cbuf->maxlen;\n\t}\n\treturn 0;\n}\n\n/* buffer del */\n\nint\ncirbuf_del_buf_tail(struct cirbuf *cbuf, unsigned int size)\n{\n\tif (!cbuf || !size || size > CIRBUF_GET_LEN(cbuf))\n\t\treturn -EINVAL;\n\n\tcbuf->len -= size;\n\tif (CIRBUF_IS_EMPTY(cbuf)) {\n\t\tcbuf->end += (cbuf->maxlen - size + 1);\n\t\tcbuf->end %= cbuf->maxlen;\n\t}\n\telse {\n\t\tcbuf->end += (cbuf->maxlen - size);\n\t\tcbuf->end %= cbuf->maxlen;\n\t}\n\treturn 0;\n}\n\n/* del at head */\n\nstatic inline void\n__cirbuf_del_head(struct cirbuf * cbuf)\n{\n\tcbuf->len --;\n\tif (!CIRBUF_IS_EMPTY(cbuf)) {\n\t\tcbuf->start ++;\n\t\tcbuf->start %= cbuf->maxlen;\n\t}\n}\n\nint\ncirbuf_del_head_safe(struct cirbuf * cbuf)\n{\n\tif (cbuf && !CIRBUF_IS_EMPTY(cbuf)) {\n\t\t__cirbuf_del_head(cbuf);\n\t\treturn 0;\n\t}\n\treturn -EINVAL;\n}\n\nvoid\ncirbuf_del_head(struct cirbuf * cbuf)\n{\n\t__cirbuf_del_head(cbuf);\n}\n\n/* del at tail */\n\nstatic inline void\n__cirbuf_del_tail(struct cirbuf * cbuf)\n{\n\tcbuf->len --;\n\tif (!CIRBUF_IS_EMPTY(cbuf)) {\n\t\tcbuf->end += (cbuf->maxlen - 1);\n\t\tcbuf->end %= cbuf->maxlen;\n\t}\n}\n\nint\ncirbuf_del_tail_safe(struct cirbuf * cbuf)\n{\n\tif (cbuf && !CIRBUF_IS_EMPTY(cbuf)) {\n\t\t__cirbuf_del_tail(cbuf);\n\t\treturn 0;\n\t}\n\treturn -EINVAL;\n}\n\nvoid\ncirbuf_del_tail(struct cirbuf * cbuf)\n{\n\t__cirbuf_del_tail(cbuf);\n}\n\n/* convert to buffer */\n\nint\ncirbuf_get_buf_head(struct cirbuf *cbuf, char *c, unsigned int size)\n{\n\tunsigned int n;\n\n\tif (!cbuf || !c)\n\t\treturn -EINVAL;\n\n\tn = (size < CIRBUF_GET_LEN(cbuf)) ? size : CIRBUF_GET_LEN(cbuf);\n\n\tif (!n)\n\t\treturn 0;\n\n\tif (cbuf->start <= cbuf->end) {\n\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", cbuf->start, 0, n);\n\t\tmemcpy(c, cbuf->buf + cbuf->start , n);\n\t}\n\telse {\n\t\t/* check if we need to go from end to the beginning */\n\t\tif (n <= cbuf->maxlen - cbuf->start) {\n\t\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", 0, cbuf->start, n);\n\t\t\tmemcpy(c, cbuf->buf + cbuf->start , n);\n\t\t}\n\t\telse {\n\t\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", cbuf->start, 0,\n\t\t\t\tcbuf->maxlen - cbuf->start);\n\t\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", 0, cbuf->maxlen - cbuf->start,\n\t\t\t\tn - cbuf->maxlen + cbuf->start);\n\t\t\tmemcpy(c, cbuf->buf + cbuf->start , cbuf->maxlen - cbuf->start);\n\t\t\tmemcpy(c + cbuf->maxlen - cbuf->start, cbuf->buf,\n\t\t\t\t n - cbuf->maxlen + cbuf->start);\n\t\t}\n\t}\n\treturn n;\n}\n\n/* convert to buffer */\n\nint\ncirbuf_get_buf_tail(struct cirbuf *cbuf, char *c, unsigned int size)\n{\n\tunsigned int n;\n\n\tif (!cbuf || !c)\n\t\treturn -EINVAL;\n\n\tn = (size < CIRBUF_GET_LEN(cbuf)) ? size : CIRBUF_GET_LEN(cbuf);\n\n\tif (!n)\n\t\treturn 0;\n\n\tif (cbuf->start <= cbuf->end) {\n\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", cbuf->end - n + 1, 0, n);\n\t\tmemcpy(c, cbuf->buf + cbuf->end - n + 1, n);\n\t}\n\telse {\n\t\t/* check if we need to go from end to the beginning */\n\t\tif (n <= cbuf->end + 1) {\n\t\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", 0, cbuf->end - n + 1, n);\n\t\t\tmemcpy(c, cbuf->buf + cbuf->end - n + 1, n);\n\t\t}\n\t\telse {\n\t\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\", 0,\n\t\t\t\tcbuf->maxlen - cbuf->start, cbuf->end + 1);\n\t\t\tdprintf(\"s[%d] -> d[%d] (%d)\\n\",\n\t\t\t\tcbuf->maxlen - n + cbuf->end + 1, 0, n - cbuf->end - 1);\n\t\t\tmemcpy(c + cbuf->maxlen - cbuf->start,\n\t\t\t\t\t cbuf->buf, cbuf->end + 1);\n\t\t\tmemcpy(c, cbuf->buf + cbuf->maxlen - n + cbuf->end +1,\n\t\t\t\t n - cbuf->end - 1);\n\t\t}\n\t}\n\treturn n;\n}\n\n/* get head or get tail */\n\nchar\ncirbuf_get_head(struct cirbuf * cbuf)\n{\n\treturn cbuf->buf[cbuf->start];\n}\n\n/* get head or get tail */\n\nchar\ncirbuf_get_tail(struct cirbuf * cbuf)\n{\n\treturn cbuf->buf[cbuf->end];\n}\n" }, { "path": "lib/librte_cmdline/cmdline_cirbuf.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _CIRBUF_H_\n#define _CIRBUF_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * This structure is the header of a cirbuf type.\n */\nstruct cirbuf {\n\tunsigned int maxlen; /**< total len of the fifo (number of elements) */\n\tunsigned int start; /**< indice of the first elt */\n\tunsigned int end; /**< indice of the last elt */\n\tunsigned int len; /**< current len of fifo */\n\tchar *buf;\n};\n\n#ifdef RTE_LIBRTE_CMDLINE_DEBUG\n#define dprintf_(fmt, ...) printf(\"line %3.3d - \" fmt \"%.0s\", __LINE__, __VA_ARGS__)\n#define dprintf(...) dprintf_(__VA_ARGS__, \"dummy\")\n#else\n#define dprintf(...) (void)0\n#endif\n\n\n/**\n * Init the circular buffer\n */\nint cirbuf_init(struct cirbuf *cbuf, char *buf, unsigned int start, unsigned int maxlen);\n\n\n/**\n * Return 1 if the circular buffer is full\n */\n#define CIRBUF_IS_FULL(cirbuf) ((cirbuf)->maxlen == (cirbuf)->len)\n\n/**\n * Return 1 if the circular buffer is empty\n */\n#define CIRBUF_IS_EMPTY(cirbuf) ((cirbuf)->len == 0)\n\n/**\n * return current size of the circular buffer (number of used elements)\n */\n#define CIRBUF_GET_LEN(cirbuf) ((cirbuf)->len)\n\n/**\n * return size of the circular buffer (used + free elements)\n */\n#define CIRBUF_GET_MAXLEN(cirbuf) ((cirbuf)->maxlen)\n\n/**\n * return the number of free elts\n */\n#define CIRBUF_GET_FREELEN(cirbuf) ((cirbuf)->maxlen - (cirbuf)->len)\n\n/**\n * Iterator for a circular buffer\n * c: struct cirbuf pointer\n * i: an integer type internally used in the macro\n * e: char that takes the value for each iteration\n */\n#define CIRBUF_FOREACH(c, i, e) \\\n\tfor ( i=0, e=(c)->buf[(c)->start] ; \\\n\t\ti<((c)->len) ; \\\n\t\ti ++, e=(c)->buf[((c)->start+i)%((c)->maxlen)])\n\n\n/**\n * Add a character at head of the circular buffer. Return 0 on success, or\n * a negative value on error.\n */\nint cirbuf_add_head_safe(struct cirbuf *cbuf, char c);\n\n/**\n * Add a character at head of the circular buffer. You _must_ check that you\n * have enough free space in the buffer before calling this func.\n */\nvoid cirbuf_add_head(struct cirbuf *cbuf, char c);\n\n/**\n * Add a character at tail of the circular buffer. Return 0 on success, or\n * a negative value on error.\n */\nint cirbuf_add_tail_safe(struct cirbuf *cbuf, char c);\n\n/**\n * Add a character at tail of the circular buffer. You _must_ check that you\n * have enough free space in the buffer before calling this func.\n */\nvoid cirbuf_add_tail(struct cirbuf *cbuf, char c);\n\n/**\n * Remove a char at the head of the circular buffer. Return 0 on\n * success, or a negative value on error.\n */\nint cirbuf_del_head_safe(struct cirbuf *cbuf);\n\n/**\n * Remove a char at the head of the circular buffer. You _must_ check\n * that buffer is not empty before calling the function.\n */\nvoid cirbuf_del_head(struct cirbuf *cbuf);\n\n/**\n * Remove a char at the tail of the circular buffer. Return 0 on\n * success, or a negative value on error.\n */\nint cirbuf_del_tail_safe(struct cirbuf *cbuf);\n\n/**\n * Remove a char at the tail of the circular buffer. You _must_ check\n * that buffer is not empty before calling the function.\n */\nvoid cirbuf_del_tail(struct cirbuf *cbuf);\n\n/**\n * Return the head of the circular buffer. You _must_ check that\n * buffer is not empty before calling the function.\n */\nchar cirbuf_get_head(struct cirbuf *cbuf);\n\n/**\n * Return the tail of the circular buffer. You _must_ check that\n * buffer is not empty before calling the function.\n */\nchar cirbuf_get_tail(struct cirbuf *cbuf);\n\n/**\n * Add a buffer at head of the circular buffer. 'c' is a pointer to a\n * buffer, and n is the number of char to add. Return the number of\n * copied bytes on success, or a negative value on error.\n */\nint cirbuf_add_buf_head(struct cirbuf *cbuf, const char *c, unsigned int n);\n\n/**\n * Add a buffer at tail of the circular buffer. 'c' is a pointer to a\n * buffer, and n is the number of char to add. Return the number of\n * copied bytes on success, or a negative value on error.\n */\nint cirbuf_add_buf_tail(struct cirbuf *cbuf, const char *c, unsigned int n);\n\n/**\n * Remove chars at the head of the circular buffer. Return 0 on\n * success, or a negative value on error.\n */\nint cirbuf_del_buf_head(struct cirbuf *cbuf, unsigned int size);\n\n/**\n * Remove chars at the tail of the circular buffer. Return 0 on\n * success, or a negative value on error.\n */\nint cirbuf_del_buf_tail(struct cirbuf *cbuf, unsigned int size);\n\n/**\n * Copy a maximum of 'size' characters from the head of the circular\n * buffer to a flat one pointed by 'c'. Return the number of copied\n * chars.\n */\nint cirbuf_get_buf_head(struct cirbuf *cbuf, char *c, unsigned int size);\n\n/**\n * Copy a maximum of 'size' characters from the tail of the circular\n * buffer to a flat one pointed by 'c'. Return the number of copied\n * chars.\n */\nint cirbuf_get_buf_tail(struct cirbuf *cbuf, char *c, unsigned int size);\n\n\n/**\n * Set the start of the data to the index 0 of the internal buffer.\n */\nint cirbuf_align_left(struct cirbuf *cbuf);\n\n/**\n * Set the end of the data to the last index of the internal buffer.\n */\nint cirbuf_align_right(struct cirbuf *cbuf);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _CIRBUF_H_ */\n" }, { "path": "lib/librte_cmdline/cmdline_parse.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \n\n#include \"cmdline_rdline.h\"\n#include \"cmdline_parse.h\"\n#include \"cmdline.h\"\n\n#ifdef RTE_LIBRTE_CMDLINE_DEBUG\n#define debug_printf printf\n#else\n#define debug_printf(args...) do {} while(0)\n#endif\n\n#define CMDLINE_BUFFER_SIZE 64\n\n/* isblank() needs _XOPEN_SOURCE >= 600 || _ISOC99_SOURCE, so use our\n * own. */\nstatic int\nisblank2(char c)\n{\n\tif (c == ' ' ||\n\t c == '\\t' )\n\t\treturn 1;\n\treturn 0;\n}\n\nstatic int\nisendofline(char c)\n{\n\tif (c == '\\n' ||\n\t c == '\\r' )\n\t\treturn 1;\n\treturn 0;\n}\n\nstatic int\niscomment(char c)\n{\n\tif (c == '#')\n\t\treturn 1;\n\treturn 0;\n}\n\nint\ncmdline_isendoftoken(char c)\n{\n\tif (!c || iscomment(c) || isblank2(c) || isendofline(c))\n\t\treturn 1;\n\treturn 0;\n}\n\nstatic unsigned int\nnb_common_chars(const char * s1, const char * s2)\n{\n\tunsigned int i=0;\n\n\twhile (*s1==*s2 && *s1) {\n\t\ts1++;\n\t\ts2++;\n\t\ti++;\n\t}\n\treturn i;\n}\n\n/**\n * try to match the buffer with an instruction (only the first\n * nb_match_token tokens if != 0). Return 0 if we match all the\n * tokens, else the number of matched tokens, else -1.\n */\nstatic int\nmatch_inst(cmdline_parse_inst_t *inst, const char *buf,\n\t unsigned int nb_match_token, void *resbuf, unsigned resbuf_size)\n{\n\tunsigned int token_num=0;\n\tcmdline_parse_token_hdr_t * token_p;\n\tunsigned int i=0;\n\tint n = 0;\n\tstruct cmdline_token_hdr token_hdr;\n\n\ttoken_p = inst->tokens[token_num];\n\tif (token_p)\n\t\tmemcpy(&token_hdr, token_p, sizeof(token_hdr));\n\n\t/* check if we match all tokens of inst */\n\twhile (token_p && (!nb_match_token || iparse(token_p, buf, NULL, 0);\n\t\t} else {\n\t\t\tunsigned rb_sz;\n\n\t\t\tif (token_hdr.offset > resbuf_size) {\n\t\t\t\tprintf(\"Parse error(%s:%d): Token offset(%u) \"\n\t\t\t\t\t\"exceeds maximum size(%u)\\n\",\n\t\t\t\t\t__FILE__, __LINE__,\n\t\t\t\t\ttoken_hdr.offset, resbuf_size);\n\t\t\t\treturn -ENOBUFS;\n\t\t\t}\n\t\t\trb_sz = resbuf_size - token_hdr.offset;\n\n\t\t\tn = token_hdr.ops->parse(token_p, buf, (char *)resbuf +\n\t\t\t\ttoken_hdr.offset, rb_sz);\n\t\t}\n\n\t\tif (n < 0)\n\t\t\tbreak;\n\n\t\tdebug_printf(\"TK parsed (len=%d)\\n\", n);\n\t\ti++;\n\t\tbuf += n;\n\n\t\ttoken_num ++;\n\t\ttoken_p = inst->tokens[token_num];\n\t\tif (token_p)\n\t\t\tmemcpy(&token_hdr, token_p, sizeof(token_hdr));\n\t}\n\n\t/* does not match */\n\tif (i==0)\n\t\treturn -1;\n\n\t/* in case we want to match a specific num of token */\n\tif (nb_match_token) {\n\t\tif (i == nb_match_token) {\n\t\t\treturn 0;\n\t\t}\n\t\treturn i;\n\t}\n\n\t/* we don't match all the tokens */\n\tif (token_p) {\n\t\treturn i;\n\t}\n\n\t/* are there are some tokens more */\n\twhile (isblank2(*buf)) {\n\t\tbuf++;\n\t}\n\n\t/* end of buf */\n\tif ( isendofline(*buf) || iscomment(*buf) )\n\t\treturn 0;\n\n\t/* garbage after inst */\n\treturn i;\n}\n\n\nint\ncmdline_parse(struct cmdline *cl, const char * buf)\n{\n\tunsigned int inst_num=0;\n\tcmdline_parse_inst_t *inst;\n\tconst char *curbuf;\n\tchar result_buf[CMDLINE_PARSE_RESULT_BUFSIZE];\n\tvoid (*f)(void *, struct cmdline *, void *) = NULL;\n\tvoid *data = NULL;\n\tint comment = 0;\n\tint linelen = 0;\n\tint parse_it = 0;\n\tint err = CMDLINE_PARSE_NOMATCH;\n\tint tok;\n\tcmdline_parse_ctx_t *ctx;\n#ifdef RTE_LIBRTE_CMDLINE_DEBUG\n\tchar debug_buf[BUFSIZ];\n#endif\n\n\tif (!cl || !buf)\n\t\treturn CMDLINE_PARSE_BAD_ARGS;\n\n\tctx = cl->ctx;\n\n\t/*\n\t * - look if the buffer contains at least one line\n\t * - look if line contains only spaces or comments\n\t * - count line length\n\t */\n\tcurbuf = buf;\n\twhile (! isendofline(*curbuf)) {\n\t\tif ( *curbuf == '\\0' ) {\n\t\t\tdebug_printf(\"Incomplete buf (len=%d)\\n\", linelen);\n\t\t\treturn 0;\n\t\t}\n\t\tif ( iscomment(*curbuf) ) {\n\t\t\tcomment = 1;\n\t\t}\n\t\tif ( ! isblank2(*curbuf) && ! comment) {\n\t\t\tparse_it = 1;\n\t\t}\n\t\tcurbuf++;\n\t\tlinelen++;\n\t}\n\n\t/* skip all endofline chars */\n\twhile (isendofline(buf[linelen])) {\n\t\tlinelen++;\n\t}\n\n\t/* empty line */\n\tif ( parse_it == 0 ) {\n\t\tdebug_printf(\"Empty line (len=%d)\\n\", linelen);\n\t\treturn linelen;\n\t}\n\n#ifdef RTE_LIBRTE_CMDLINE_DEBUG\n\tsnprintf(debug_buf, (linelen>64 ? 64 : linelen), \"%s\", buf);\n\tdebug_printf(\"Parse line : len=%d, <%s>\\n\", linelen, debug_buf);\n#endif\n\n\t/* parse it !! */\n\tinst = ctx[inst_num];\n\twhile (inst) {\n\t\tdebug_printf(\"INST %d\\n\", inst_num);\n\n\t\t/* fully parsed */\n\t\ttok = match_inst(inst, buf, 0, result_buf, sizeof(result_buf));\n\n\t\tif (tok > 0) /* we matched at least one token */\n\t\t\terr = CMDLINE_PARSE_BAD_ARGS;\n\n\t\telse if (!tok) {\n\t\t\tdebug_printf(\"INST fully parsed\\n\");\n\t\t\t/* skip spaces */\n\t\t\twhile (isblank2(*curbuf)) {\n\t\t\t\tcurbuf++;\n\t\t\t}\n\n\t\t\t/* if end of buf -> there is no garbage after inst */\n\t\t\tif (isendofline(*curbuf) || iscomment(*curbuf)) {\n\t\t\t\tif (!f) {\n\t\t\t\t\tmemcpy(&f, &inst->f, sizeof(f));\n\t\t\t\t\tmemcpy(&data, &inst->data, sizeof(data));\n\t\t\t\t}\n\t\t\t\telse {\n\t\t\t\t\t/* more than 1 inst matches */\n\t\t\t\t\terr = CMDLINE_PARSE_AMBIGUOUS;\n\t\t\t\t\tf=NULL;\n\t\t\t\t\tdebug_printf(\"Ambiguous cmd\\n\");\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tinst_num ++;\n\t\tinst = ctx[inst_num];\n\t}\n\n\t/* call func */\n\tif (f) {\n\t\tf(result_buf, cl, data);\n\t}\n\n\t/* no match */\n\telse {\n\t\tdebug_printf(\"No match err=%d\\n\", err);\n\t\treturn err;\n\t}\n\n\treturn linelen;\n}\n\nint\ncmdline_complete(struct cmdline *cl, const char *buf, int *state,\n\t\t char *dst, unsigned int size)\n{\n\tconst char *partial_tok = buf;\n\tunsigned int inst_num = 0;\n\tcmdline_parse_inst_t *inst;\n\tcmdline_parse_token_hdr_t *token_p;\n\tstruct cmdline_token_hdr token_hdr;\n\tchar tmpbuf[CMDLINE_BUFFER_SIZE], comp_buf[CMDLINE_BUFFER_SIZE];\n\tunsigned int partial_tok_len;\n\tint comp_len = -1;\n\tint tmp_len = -1;\n\tint nb_token = 0;\n\tunsigned int i, n;\n\tint l;\n\tunsigned int nb_completable;\n\tunsigned int nb_non_completable;\n\tint local_state = 0;\n\tconst char *help_str;\n\tcmdline_parse_ctx_t *ctx;\n\n\tif (!cl || !buf || !state || !dst)\n\t\treturn -1;\n\n\tctx = cl->ctx;\n\n\tdebug_printf(\"%s called\\n\", __func__);\n\tmemset(&token_hdr, 0, sizeof(token_hdr));\n\n\t/* count the number of complete token to parse */\n\tfor (i=0 ; buf[i] ; i++) {\n\t\tif (!isblank2(buf[i]) && isblank2(buf[i+1]))\n\t\t\tnb_token++;\n\t\tif (isblank2(buf[i]) && !isblank2(buf[i+1]))\n\t\t\tpartial_tok = buf+i+1;\n\t}\n\tpartial_tok_len = strnlen(partial_tok, RDLINE_BUF_SIZE);\n\n\t/* first call -> do a first pass */\n\tif (*state <= 0) {\n\t\tdebug_printf(\"try complete <%s>\\n\", buf);\n\t\tdebug_printf(\"there is %d complete tokens, <%s> is incomplete\\n\",\n\t\t\t nb_token, partial_tok);\n\n\t\tnb_completable = 0;\n\t\tnb_non_completable = 0;\n\n\t\tinst = ctx[inst_num];\n\t\twhile (inst) {\n\t\t\t/* parse the first tokens of the inst */\n\t\t\tif (nb_token && match_inst(inst, buf, nb_token, NULL, 0))\n\t\t\t\tgoto next;\n\n\t\t\tdebug_printf(\"instruction match\\n\");\n\t\t\ttoken_p = inst->tokens[nb_token];\n\t\t\tif (token_p)\n\t\t\t\tmemcpy(&token_hdr, token_p, sizeof(token_hdr));\n\n\t\t\t/* non completable */\n\t\t\tif (!token_p ||\n\t\t\t !token_hdr.ops->complete_get_nb ||\n\t\t\t !token_hdr.ops->complete_get_elt ||\n\t\t\t (n = token_hdr.ops->complete_get_nb(token_p)) == 0) {\n\t\t\t\tnb_non_completable++;\n\t\t\t\tgoto next;\n\t\t\t}\n\n\t\t\tdebug_printf(\"%d choices for this token\\n\", n);\n\t\t\tfor (i=0 ; icomplete_get_elt(token_p, i,\n\t\t\t\t\t\t\t\t tmpbuf,\n\t\t\t\t\t\t\t\t sizeof(tmpbuf)) < 0)\n\t\t\t\t\tcontinue;\n\n\t\t\t\t/* we have at least room for one char */\n\t\t\t\ttmp_len = strnlen(tmpbuf, sizeof(tmpbuf));\n\t\t\t\tif (tmp_len < CMDLINE_BUFFER_SIZE - 1) {\n\t\t\t\t\ttmpbuf[tmp_len] = ' ';\n\t\t\t\t\ttmpbuf[tmp_len+1] = 0;\n\t\t\t\t}\n\n\t\t\t\tdebug_printf(\" choice <%s>\\n\", tmpbuf);\n\n\t\t\t\t/* does the completion match the\n\t\t\t\t * beginning of the word ? */\n\t\t\t\tif (!strncmp(partial_tok, tmpbuf,\n\t\t\t\t\t partial_tok_len)) {\n\t\t\t\t\tif (comp_len == -1) {\n\t\t\t\t\t\tsnprintf(comp_buf, sizeof(comp_buf),\n\t\t\t\t\t\t\t \"%s\", tmpbuf + partial_tok_len);\n\t\t\t\t\t\tcomp_len =\n\t\t\t\t\t\t\tstrnlen(tmpbuf + partial_tok_len,\n\t\t\t\t\t\t\t\t\tsizeof(tmpbuf) - partial_tok_len);\n\n\t\t\t\t\t}\n\t\t\t\t\telse {\n\t\t\t\t\t\tcomp_len =\n\t\t\t\t\t\t\tnb_common_chars(comp_buf,\n\t\t\t\t\t\t\t\t\ttmpbuf+partial_tok_len);\n\t\t\t\t\t\tcomp_buf[comp_len] = 0;\n\t\t\t\t\t}\n\t\t\t\t\tnb_completable++;\n\t\t\t\t}\n\t\t\t}\n\t\tnext:\n\t\t\tdebug_printf(\"next\\n\");\n\t\t\tinst_num ++;\n\t\t\tinst = ctx[inst_num];\n\t\t}\n\n\t\tdebug_printf(\"total choices %d for this completion\\n\",\n\t\t\t nb_completable);\n\n\t\t/* no possible completion */\n\t\tif (nb_completable == 0 && nb_non_completable == 0)\n\t\t\treturn 0;\n\n\t\t/* if multichoice is not required */\n\t\tif (*state == 0 && partial_tok_len > 0) {\n\t\t\t/* one or several choices starting with the\n\t\t\t same chars */\n\t\t\tif (comp_len > 0) {\n\t\t\t\tif ((unsigned)(comp_len + 1) > size)\n\t\t\t\t\treturn 0;\n\n\t\t\t\tsnprintf(dst, size, \"%s\", comp_buf);\n\t\t\t\tdst[comp_len] = 0;\n\t\t\t\treturn 2;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* init state correctly */\n\tif (*state == -1)\n\t\t*state = 0;\n\n\tdebug_printf(\"Multiple choice STATE=%d\\n\", *state);\n\n\tinst_num = 0;\n\tinst = ctx[inst_num];\n\twhile (inst) {\n\t\t/* we need to redo it */\n\t\tinst = ctx[inst_num];\n\n\t\tif (nb_token && match_inst(inst, buf, nb_token, NULL, 0))\n\t\t\tgoto next2;\n\n\t\ttoken_p = inst->tokens[nb_token];\n\t\tif (token_p)\n\t\t\tmemcpy(&token_hdr, token_p, sizeof(token_hdr));\n\n\t\t/* one choice for this token */\n\t\tif (!token_p ||\n\t\t !token_hdr.ops->complete_get_nb ||\n\t\t !token_hdr.ops->complete_get_elt ||\n\t\t (n = token_hdr.ops->complete_get_nb(token_p)) == 0) {\n\t\t\tif (local_state < *state) {\n\t\t\t\tlocal_state++;\n\t\t\t\tgoto next2;\n\t\t\t}\n\t\t\t(*state)++;\n\t\t\tif (token_p && token_hdr.ops->get_help) {\n\t\t\t\ttoken_hdr.ops->get_help(token_p, tmpbuf,\n\t\t\t\t\t\t\tsizeof(tmpbuf));\n\t\t\t\thelp_str = inst->help_str;\n\t\t\t\tif (help_str)\n\t\t\t\t\tsnprintf(dst, size, \"[%s]: %s\", tmpbuf,\n\t\t\t\t\t\t help_str);\n\t\t\t\telse\n\t\t\t\t\tsnprintf(dst, size, \"[%s]: No help\",\n\t\t\t\t\t\t tmpbuf);\n\t\t\t}\n\t\t\telse {\n\t\t\t\tsnprintf(dst, size, \"[RETURN]\");\n\t\t\t}\n\t\t\treturn 1;\n\t\t}\n\n\t\t/* several choices */\n\t\tfor (i=0 ; icomplete_get_elt(token_p, i, tmpbuf,\n\t\t\t\t\t\t\t sizeof(tmpbuf)) < 0)\n\t\t\t\tcontinue;\n\t\t\t/* we have at least room for one char */\n\t\t\ttmp_len = strnlen(tmpbuf, sizeof(tmpbuf));\n\t\t\tif (tmp_len < CMDLINE_BUFFER_SIZE - 1) {\n\t\t\t\ttmpbuf[tmp_len] = ' ';\n\t\t\t\ttmpbuf[tmp_len + 1] = 0;\n\t\t\t}\n\n\t\t\tdebug_printf(\" choice <%s>\\n\", tmpbuf);\n\n\t\t\t/* does the completion match the beginning of\n\t\t\t * the word ? */\n\t\t\tif (!strncmp(partial_tok, tmpbuf,\n\t\t\t\t partial_tok_len)) {\n\t\t\t\tif (local_state < *state) {\n\t\t\t\t\tlocal_state++;\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t\t(*state)++;\n\t\t\t\tl=snprintf(dst, size, \"%s\", tmpbuf);\n\t\t\t\tif (l>=0 && token_hdr.ops->get_help) {\n\t\t\t\t\ttoken_hdr.ops->get_help(token_p, tmpbuf,\n\t\t\t\t\t\t\t\tsizeof(tmpbuf));\n\t\t\t\t\thelp_str = inst->help_str;\n\t\t\t\t\tif (help_str)\n\t\t\t\t\t\tsnprintf(dst+l, size-l, \"[%s]: %s\",\n\t\t\t\t\t\t\t tmpbuf, help_str);\n\t\t\t\t\telse\n\t\t\t\t\t\tsnprintf(dst+l, size-l,\n\t\t\t\t\t\t\t \"[%s]: No help\", tmpbuf);\n\t\t\t\t}\n\n\t\t\t\treturn 1;\n\t\t\t}\n\t\t}\n\tnext2:\n\t\tinst_num ++;\n\t\tinst = ctx[inst_num];\n\t}\n\treturn 0;\n}\n" }, { "path": "lib/librte_cmdline/cmdline_parse.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _CMDLINE_PARSE_H_\n#define _CMDLINE_PARSE_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#ifndef offsetof\n#define offsetof(type, field) ((size_t) &( ((type *)0)->field) )\n#endif\n\n/* return status for parsing */\n#define CMDLINE_PARSE_SUCCESS 0\n#define CMDLINE_PARSE_AMBIGUOUS -1\n#define CMDLINE_PARSE_NOMATCH -2\n#define CMDLINE_PARSE_BAD_ARGS -3\n\n/* return status for completion */\n#define CMDLINE_PARSE_COMPLETE_FINISHED 0\n#define CMDLINE_PARSE_COMPLETE_AGAIN 1\n#define CMDLINE_PARSE_COMPLETED_BUFFER 2\n\n/* maximum buffer size for parsed result */\n#define CMDLINE_PARSE_RESULT_BUFSIZE 8192\n\n/**\n * Stores a pointer to the ops struct, and the offset: the place to\n * write the parsed result in the destination structure.\n */\nstruct cmdline_token_hdr {\n\tstruct cmdline_token_ops *ops;\n\tunsigned int offset;\n};\ntypedef struct cmdline_token_hdr cmdline_parse_token_hdr_t;\n\n/**\n * A token is defined by this structure.\n *\n * parse() takes the token as first argument, then the source buffer\n * starting at the token we want to parse. The 3rd arg is a pointer\n * where we store the parsed data (as binary). It returns the number of\n * parsed chars on success and a negative value on error.\n *\n * complete_get_nb() returns the number of possible values for this\n * token if completion is possible. If it is NULL or if it returns 0,\n * no completion is possible.\n *\n * complete_get_elt() copy in dstbuf (the size is specified in the\n * parameter) the i-th possible completion for this token. returns 0\n * on success or and a negative value on error.\n *\n * get_help() fills the dstbuf with the help for the token. It returns\n * -1 on error and 0 on success.\n */\nstruct cmdline_token_ops {\n\t/** parse(token ptr, buf, res pts, buf len) */\n\tint (*parse)(cmdline_parse_token_hdr_t *, const char *, void *,\n\t\tunsigned int);\n\t/** return the num of possible choices for this token */\n\tint (*complete_get_nb)(cmdline_parse_token_hdr_t *);\n\t/** return the elt x for this token (token, idx, dstbuf, size) */\n\tint (*complete_get_elt)(cmdline_parse_token_hdr_t *, int, char *,\n\t\tunsigned int);\n\t/** get help for this token (token, dstbuf, size) */\n\tint (*get_help)(cmdline_parse_token_hdr_t *, char *, unsigned int);\n};\n\nstruct cmdline;\n/**\n * Store a instruction, which is a pointer to a callback function and\n * its parameter that is called when the instruction is parsed, a help\n * string, and a list of token composing this instruction.\n */\nstruct cmdline_inst {\n\t/* f(parsed_struct, data) */\n\tvoid (*f)(void *, struct cmdline *, void *);\n\tvoid *data;\n\tconst char *help_str;\n\tcmdline_parse_token_hdr_t *tokens[];\n};\ntypedef struct cmdline_inst cmdline_parse_inst_t;\n\n/**\n * A context is identified by its name, and contains a list of\n * instruction\n *\n */\ntypedef cmdline_parse_inst_t *cmdline_parse_ctx_t;\n\n/**\n * Try to parse a buffer according to the specified context. The\n * argument buf must ends with \"\\n\\0\". The function returns\n * CMDLINE_PARSE_AMBIGUOUS, CMDLINE_PARSE_NOMATCH or\n * CMDLINE_PARSE_BAD_ARGS on error. Else it calls the associated\n * function (defined in the context) and returns 0\n * (CMDLINE_PARSE_SUCCESS).\n */\nint cmdline_parse(struct cmdline *cl, const char *buf);\n\n/**\n * complete() must be called with *state==0 (try to complete) or\n * with *state==-1 (just display choices), then called without\n * modifying *state until it returns CMDLINE_PARSE_COMPLETED_BUFFER or\n * CMDLINE_PARSE_COMPLETED_BUFFER.\n *\n * It returns < 0 on error.\n *\n * Else it returns:\n * - CMDLINE_PARSE_COMPLETED_BUFFER on completion (one possible\n * choice). In this case, the chars are appended in dst buffer.\n * - CMDLINE_PARSE_COMPLETE_AGAIN if there is several possible\n * choices. In this case, you must call the function again,\n * keeping the value of state intact.\n * - CMDLINE_PARSE_COMPLETED_BUFFER when the iteration is\n * finished. The dst is not valid for this last call.\n *\n * The returned dst buf ends with \\0.\n */\nint cmdline_complete(struct cmdline *cl, const char *buf, int *state,\n\t\t char *dst, unsigned int size);\n\n\n/* return true if(!c || iscomment(c) || isblank(c) ||\n * isendofline(c)) */\nint cmdline_isendoftoken(char c);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _CMDLINE_PARSE_H_ */\n" }, { "path": "lib/librte_cmdline/cmdline_parse_etheraddr.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"cmdline_parse.h\"\n#include \"cmdline_parse_etheraddr.h\"\n\nstruct cmdline_token_ops cmdline_token_etheraddr_ops = {\n\t.parse = cmdline_parse_etheraddr,\n\t.complete_get_nb = NULL,\n\t.complete_get_elt = NULL,\n\t.get_help = cmdline_get_help_etheraddr,\n};\n\n/* the format can be either XX:XX:XX:XX:XX:XX or XXXX:XXXX:XXXX */\n#define ETHER_ADDRSTRLENLONG 18\n#define ETHER_ADDRSTRLENSHORT 15\n\n#ifdef __linux__\n#define ea_oct ether_addr_octet\n#else\n#define ea_oct octet\n#endif\n\n\nstatic struct ether_addr *\nmy_ether_aton(const char *a)\n{\n\tint i;\n\tchar *end;\n\tunsigned long o[ETHER_ADDR_LEN];\n\tstatic struct ether_addr ether_addr;\n\n\ti = 0;\n\tdo {\n\t\terrno = 0;\n\t\to[i] = strtoul(a, &end, 16);\n\t\tif (errno != 0 || end == a || (end[0] != ':' && end[0] != 0))\n\t\t\treturn NULL;\n\t\ta = end + 1;\n\t} while (++i != sizeof (o) / sizeof (o[0]) && end[0] != 0);\n\n\t/* Junk at the end of line */\n\tif (end[0] != 0)\n\t\treturn NULL;\n\n\t/* Support the format XX:XX:XX:XX:XX:XX */\n\tif (i == ETHER_ADDR_LEN) {\n\t\twhile (i-- != 0) {\n\t\t\tif (o[i] > UINT8_MAX)\n\t\t\t\treturn NULL;\n\t\t\tether_addr.ea_oct[i] = (uint8_t)o[i];\n\t\t}\n\t/* Support the format XXXX:XXXX:XXXX */\n\t} else if (i == ETHER_ADDR_LEN / 2) {\n\t\twhile (i-- != 0) {\n\t\t\tif (o[i] > UINT16_MAX)\n\t\t\t\treturn NULL;\n\t\t\tether_addr.ea_oct[i * 2] = (uint8_t)(o[i] >> 8);\n\t\t\tether_addr.ea_oct[i * 2 + 1] = (uint8_t)(o[i] & 0xff);\n\t\t}\n\t/* unknown format */\n\t} else\n\t\treturn NULL;\n\n\treturn (struct ether_addr *)ðer_addr;\n}\n\nint\ncmdline_parse_etheraddr(__attribute__((unused)) cmdline_parse_token_hdr_t *tk,\n\tconst char *buf, void *res, unsigned ressize)\n{\n\tunsigned int token_len = 0;\n\tchar ether_str[ETHER_ADDRSTRLENLONG+1];\n\tstruct ether_addr *tmp;\n\n\tif (res && ressize < sizeof(struct ether_addr))\n\t\treturn -1;\n\n\tif (!buf || ! *buf)\n\t\treturn -1;\n\n\twhile (!cmdline_isendoftoken(buf[token_len]))\n\t\ttoken_len++;\n\n\t/* if token doesn't match possible string lengths... */\n\tif ((token_len != ETHER_ADDRSTRLENLONG - 1) &&\n\t\t\t(token_len != ETHER_ADDRSTRLENSHORT - 1))\n\t\treturn -1;\n\n\tsnprintf(ether_str, token_len+1, \"%s\", buf);\n\n\ttmp = my_ether_aton(ether_str);\n\tif (tmp == NULL)\n\t\treturn -1;\n\tif (res)\n\t\tmemcpy(res, tmp, sizeof(struct ether_addr));\n\treturn token_len;\n}\n\nint\ncmdline_get_help_etheraddr(__attribute__((unused)) cmdline_parse_token_hdr_t *tk,\n\t\t\t char *dstbuf, unsigned int size)\n{\n\tint ret;\n\n\tret = snprintf(dstbuf, size, \"Ethernet address\");\n\tif (ret < 0)\n\t\treturn -1;\n\treturn 0;\n}\n" }, { "path": "lib/librte_cmdline/cmdline_parse_etheraddr.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _PARSE_ETHERADDR_H_\n#define _PARSE_ETHERADDR_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct cmdline_token_etheraddr {\n\tstruct cmdline_token_hdr hdr;\n};\ntypedef struct cmdline_token_etheraddr cmdline_parse_token_etheraddr_t;\n\nextern struct cmdline_token_ops cmdline_token_etheraddr_ops;\n\nint cmdline_parse_etheraddr(cmdline_parse_token_hdr_t *tk, const char *srcbuf,\n\tvoid *res, unsigned ressize);\nint cmdline_get_help_etheraddr(cmdline_parse_token_hdr_t *tk, char *dstbuf,\n\tunsigned int size);\n\n#define TOKEN_ETHERADDR_INITIALIZER(structure, field) \\\n{ \\\n\t/* hdr */ \\\n\t{ \\\n\t\t&cmdline_token_etheraddr_ops, /* ops */ \\\n\t\toffsetof(structure, field), /* offset */ \\\n\t}, \\\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* _PARSE_ETHERADDR_H_ */\n" }, { "path": "lib/librte_cmdline/cmdline_parse_ipaddr.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * For inet_ntop() functions:\n *\n * Copyright (c) 1996 by Internet Software Consortium.\n *\n * Permission to use, copy, modify, and distribute this software for any\n * purpose with or without fee is hereby granted, provided that the above\n * copyright notice and this permission notice appear in all copies.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\" AND INTERNET SOFTWARE CONSORTIUM DISCLAIMS\n * ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES\n * OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL INTERNET SOFTWARE\n * CONSORTIUM BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL\n * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR\n * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS\n * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS\n * SOFTWARE.\n */\n\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#ifndef __linux__\n#ifndef __FreeBSD__\n#include \n#else\n#include \n#endif\n#endif\n\n#include \n\n#include \"cmdline_parse.h\"\n#include \"cmdline_parse_ipaddr.h\"\n\nstruct cmdline_token_ops cmdline_token_ipaddr_ops = {\n\t.parse = cmdline_parse_ipaddr,\n\t.complete_get_nb = NULL,\n\t.complete_get_elt = NULL,\n\t.get_help = cmdline_get_help_ipaddr,\n};\n\n#define INADDRSZ 4\n#define IN6ADDRSZ 16\n#define PREFIXMAX 128\n#define V4PREFIXMAX 32\n\n/*\n * WARNING: Don't even consider trying to compile this on a system where\n * sizeof(int) < 4. sizeof(int) > 4 is fine; all the world's not a VAX.\n */\n\nstatic int inet_pton4(const char *src, unsigned char *dst);\nstatic int inet_pton6(const char *src, unsigned char *dst);\n\n/* int\n * inet_pton(af, src, dst)\n * convert from presentation format (which usually means ASCII printable)\n * to network format (which is usually some kind of binary format).\n * return:\n * 1 if the address was valid for the specified address family\n * 0 if the address wasn't valid (`dst' is untouched in this case)\n * -1 if some other error occurred (`dst' is untouched in this case, too)\n * author:\n * Paul Vixie, 1996.\n */\nstatic int\nmy_inet_pton(int af, const char *src, void *dst)\n{\n\tswitch (af) {\n\t\tcase AF_INET:\n\t\t\treturn inet_pton4(src, dst);\n\t\tcase AF_INET6:\n\t\t\treturn inet_pton6(src, dst);\n\t\tdefault:\n\t\t\terrno = EAFNOSUPPORT;\n\t\t\treturn -1;\n\t}\n\t/* NOTREACHED */\n}\n\n/* int\n * inet_pton4(src, dst)\n * like inet_aton() but without all the hexadecimal and shorthand.\n * return:\n * 1 if `src' is a valid dotted quad, else 0.\n * notice:\n * does not touch `dst' unless it's returning 1.\n * author:\n * Paul Vixie, 1996.\n */\nstatic int\ninet_pton4(const char *src, unsigned char *dst)\n{\n\tstatic const char digits[] = \"0123456789\";\n\tint saw_digit, octets, ch;\n\tunsigned char tmp[INADDRSZ], *tp;\n\n\tsaw_digit = 0;\n\toctets = 0;\n\t*(tp = tmp) = 0;\n\twhile ((ch = *src++) != '\\0') {\n\t\tconst char *pch;\n\n\t\tif ((pch = strchr(digits, ch)) != NULL) {\n\t\t\tunsigned int new = *tp * 10 + (pch - digits);\n\n\t\t\tif (new > 255)\n\t\t\t\treturn 0;\n\t\t\tif (! saw_digit) {\n\t\t\t\tif (++octets > 4)\n\t\t\t\t\treturn 0;\n\t\t\t\tsaw_digit = 1;\n\t\t\t}\n\t\t\t*tp = (unsigned char)new;\n\t\t} else if (ch == '.' && saw_digit) {\n\t\t\tif (octets == 4)\n\t\t\t\treturn 0;\n\t\t\t*++tp = 0;\n\t\t\tsaw_digit = 0;\n\t\t} else\n\t\t\treturn 0;\n\t}\n\tif (octets < 4)\n\t\treturn 0;\n\n\tmemcpy(dst, tmp, INADDRSZ);\n\treturn 1;\n}\n\n/* int\n * inet_pton6(src, dst)\n * convert presentation level address to network order binary form.\n * return:\n * 1 if `src' is a valid [RFC1884 2.2] address, else 0.\n * notice:\n * (1) does not touch `dst' unless it's returning 1.\n * (2) :: in a full address is silently ignored.\n * credit:\n * inspired by Mark Andrews.\n * author:\n * Paul Vixie, 1996.\n */\nstatic int\ninet_pton6(const char *src, unsigned char *dst)\n{\n\tstatic const char xdigits_l[] = \"0123456789abcdef\",\n\t\txdigits_u[] = \"0123456789ABCDEF\";\n\tunsigned char tmp[IN6ADDRSZ], *tp = 0, *endp = 0, *colonp = 0;\n\tconst char *xdigits = 0, *curtok = 0;\n\tint ch = 0, saw_xdigit = 0, count_xdigit = 0;\n\tunsigned int val = 0;\n\tunsigned dbloct_count = 0;\n\n\tmemset((tp = tmp), '\\0', IN6ADDRSZ);\n\tendp = tp + IN6ADDRSZ;\n\tcolonp = NULL;\n\t/* Leading :: requires some special handling. */\n\tif (*src == ':')\n\t\tif (*++src != ':')\n\t\t\treturn 0;\n\tcurtok = src;\n\tsaw_xdigit = count_xdigit = 0;\n\tval = 0;\n\n\twhile ((ch = *src++) != '\\0') {\n\t\tconst char *pch;\n\n\t\tif ((pch = strchr((xdigits = xdigits_l), ch)) == NULL)\n\t\t\tpch = strchr((xdigits = xdigits_u), ch);\n\t\tif (pch != NULL) {\n\t\t\tif (count_xdigit >= 4)\n\t\t\t\treturn 0;\n\t\t\tval <<= 4;\n\t\t\tval |= (pch - xdigits);\n\t\t\tif (val > 0xffff)\n\t\t\t\treturn 0;\n\t\t\tsaw_xdigit = 1;\n\t\t\tcount_xdigit++;\n\t\t\tcontinue;\n\t\t}\n\t\tif (ch == ':') {\n\t\t\tcurtok = src;\n\t\t\tif (!saw_xdigit) {\n\t\t\t\tif (colonp)\n\t\t\t\t\treturn 0;\n\t\t\t\tcolonp = tp;\n\t\t\t\tcontinue;\n\t\t\t} else if (*src == '\\0') {\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t\tif (tp + sizeof(int16_t) > endp)\n\t\t\t\treturn 0;\n\t\t\t*tp++ = (unsigned char) ((val >> 8) & 0xff);\n\t\t\t*tp++ = (unsigned char) (val & 0xff);\n\t\t\tsaw_xdigit = 0;\n\t\t\tcount_xdigit = 0;\n\t\t\tval = 0;\n\t\t\tdbloct_count++;\n\t\t\tcontinue;\n\t\t}\n\t\tif (ch == '.' && ((tp + INADDRSZ) <= endp) &&\n\t\t inet_pton4(curtok, tp) > 0) {\n\t\t\ttp += INADDRSZ;\n\t\t\tsaw_xdigit = 0;\n\t\t\tdbloct_count += 2;\n\t\t\tbreak; /* '\\0' was seen by inet_pton4(). */\n\t\t}\n\t\treturn 0;\n\t}\n\tif (saw_xdigit) {\n\t\tif (tp + sizeof(int16_t) > endp)\n\t\t\treturn 0;\n\t\t*tp++ = (unsigned char) ((val >> 8) & 0xff);\n\t\t*tp++ = (unsigned char) (val & 0xff);\n\t\tdbloct_count++;\n\t}\n\tif (colonp != NULL) {\n\t\t/* if we already have 8 double octets, having a colon means error */\n\t\tif (dbloct_count == 8)\n\t\t\treturn 0;\n\n\t\t/*\n\t\t * Since some memmove()'s erroneously fail to handle\n\t\t * overlapping regions, we'll do the shift by hand.\n\t\t */\n\t\tconst int n = tp - colonp;\n\t\tint i;\n\n\t\tfor (i = 1; i <= n; i++) {\n\t\t\tendp[- i] = colonp[n - i];\n\t\t\tcolonp[n - i] = 0;\n\t\t}\n\t\ttp = endp;\n\t}\n\tif (tp != endp)\n\t\treturn 0;\n\tmemcpy(dst, tmp, IN6ADDRSZ);\n\treturn 1;\n}\n\nint\ncmdline_parse_ipaddr(cmdline_parse_token_hdr_t *tk, const char *buf, void *res,\n\tunsigned ressize)\n{\n\tstruct cmdline_token_ipaddr *tk2;\n\tunsigned int token_len = 0;\n\tchar ip_str[INET6_ADDRSTRLEN+4+1]; /* '+4' is for prefixlen (if any) */\n\tcmdline_ipaddr_t ipaddr;\n\tchar *prefix, *prefix_end;\n\tlong prefixlen = 0;\n\n\tif (res && ressize < sizeof(cmdline_ipaddr_t))\n\t\treturn -1;\n\n\tif (!buf || !tk || ! *buf)\n\t\treturn -1;\n\n\ttk2 = (struct cmdline_token_ipaddr *)tk;\n\n\twhile (!cmdline_isendoftoken(buf[token_len]))\n\t\ttoken_len++;\n\n\t/* if token is too big... */\n\tif (token_len >= INET6_ADDRSTRLEN+4)\n\t\treturn -1;\n\n\tsnprintf(ip_str, token_len+1, \"%s\", buf);\n\n\t/* convert the network prefix */\n\tif (tk2->ipaddr_data.flags & CMDLINE_IPADDR_NETWORK) {\n\t\tprefix = strrchr(ip_str, '/');\n\t\tif (prefix == NULL)\n\t\t\treturn -1;\n\t\t*prefix = '\\0';\n\t\tprefix ++;\n\t\terrno = 0;\n\t\tprefixlen = strtol(prefix, &prefix_end, 10);\n\t\tif (errno || (*prefix_end != '\\0')\n\t\t\t|| prefixlen < 0 || prefixlen > PREFIXMAX)\n\t\t\treturn -1;\n\t\tipaddr.prefixlen = prefixlen;\n\t}\n\telse {\n\t\tipaddr.prefixlen = 0;\n\t}\n\n\t/* convert the IP addr */\n\tif ((tk2->ipaddr_data.flags & CMDLINE_IPADDR_V4) &&\n\t my_inet_pton(AF_INET, ip_str, &ipaddr.addr.ipv4) == 1 &&\n\t\tprefixlen <= V4PREFIXMAX) {\n\t\tipaddr.family = AF_INET;\n\t\tif (res)\n\t\t\tmemcpy(res, &ipaddr, sizeof(ipaddr));\n\t\treturn token_len;\n\t}\n\tif ((tk2->ipaddr_data.flags & CMDLINE_IPADDR_V6) &&\n\t my_inet_pton(AF_INET6, ip_str, &ipaddr.addr.ipv6) == 1) {\n\t\tipaddr.family = AF_INET6;\n\t\tif (res)\n\t\t\tmemcpy(res, &ipaddr, sizeof(ipaddr));\n\t\treturn token_len;\n\t}\n\treturn -1;\n\n}\n\nint cmdline_get_help_ipaddr(cmdline_parse_token_hdr_t *tk, char *dstbuf,\n\t\t\t unsigned int size)\n{\n\tstruct cmdline_token_ipaddr *tk2;\n\n\tif (!tk || !dstbuf)\n\t\treturn -1;\n\n\ttk2 = (struct cmdline_token_ipaddr *)tk;\n\n\tswitch (tk2->ipaddr_data.flags) {\n\tcase CMDLINE_IPADDR_V4:\n\t\tsnprintf(dstbuf, size, \"IPv4\");\n\t\tbreak;\n\tcase CMDLINE_IPADDR_V6:\n\t\tsnprintf(dstbuf, size, \"IPv6\");\n\t\tbreak;\n\tcase CMDLINE_IPADDR_V4|CMDLINE_IPADDR_V6:\n\t\tsnprintf(dstbuf, size, \"IPv4/IPv6\");\n\t\tbreak;\n\tcase CMDLINE_IPADDR_NETWORK|CMDLINE_IPADDR_V4:\n\t\tsnprintf(dstbuf, size, \"IPv4 network\");\n\t\tbreak;\n\tcase CMDLINE_IPADDR_NETWORK|CMDLINE_IPADDR_V6:\n\t\tsnprintf(dstbuf, size, \"IPv6 network\");\n\t\tbreak;\n\tcase CMDLINE_IPADDR_NETWORK|CMDLINE_IPADDR_V4|CMDLINE_IPADDR_V6:\n\t\tsnprintf(dstbuf, size, \"IPv4/IPv6 network\");\n\t\tbreak;\n\tdefault:\n\t\tsnprintf(dstbuf, size, \"IPaddr (bad flags)\");\n\t\tbreak;\n\t}\n\treturn 0;\n}\n" }, { "path": "lib/librte_cmdline/cmdline_parse_ipaddr.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _PARSE_IPADDR_H_\n#define _PARSE_IPADDR_H_\n\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define CMDLINE_IPADDR_V4 0x01\n#define CMDLINE_IPADDR_V6 0x02\n#define CMDLINE_IPADDR_NETWORK 0x04\n\nstruct cmdline_ipaddr {\n\tuint8_t family;\n\tunion {\n\t\tstruct in_addr ipv4;\n\t\tstruct in6_addr ipv6;\n\t} addr;\n\tunsigned int prefixlen; /* in case of network only */\n};\ntypedef struct cmdline_ipaddr cmdline_ipaddr_t;\n\nstruct cmdline_token_ipaddr_data {\n\tuint8_t flags;\n};\n\nstruct cmdline_token_ipaddr {\n\tstruct cmdline_token_hdr hdr;\n\tstruct cmdline_token_ipaddr_data ipaddr_data;\n};\ntypedef struct cmdline_token_ipaddr cmdline_parse_token_ipaddr_t;\n\nextern struct cmdline_token_ops cmdline_token_ipaddr_ops;\n\nint cmdline_parse_ipaddr(cmdline_parse_token_hdr_t *tk, const char *srcbuf,\n\tvoid *res, unsigned ressize);\nint cmdline_get_help_ipaddr(cmdline_parse_token_hdr_t *tk, char *dstbuf,\n\tunsigned int size);\n\n#define TOKEN_IPADDR_INITIALIZER(structure, field) \\\n{ \\\n\t/* hdr */ \\\n\t{ \\\n\t\t&cmdline_token_ipaddr_ops, /* ops */ \\\n\t\toffsetof(structure, field), /* offset */ \\\n\t}, \\\n\t/* ipaddr_data */ \\\n\t{ \\\n\t\tCMDLINE_IPADDR_V4 | /* flags */ \\\n\t\tCMDLINE_IPADDR_V6, \\\n\t}, \\\n}\n\n#define TOKEN_IPV4_INITIALIZER(structure, field) \\\n{ \\\n\t/* hdr */ \\\n\t{ \\\n\t\t&cmdline_token_ipaddr_ops, /* ops */ \\\n\t\toffsetof(structure, field), /* offset */ \\\n\t}, \\\n\t/* ipaddr_data */ \\\n\t{ \\\n\t\tCMDLINE_IPADDR_V4, /* flags */ \\\n\t}, \\\n}\n\n#define TOKEN_IPV6_INITIALIZER(structure, field) \\\n{ \\\n\t/* hdr */ \\\n\t{ \\\n\t\t&cmdline_token_ipaddr_ops, /* ops */ \\\n\t\toffsetof(structure, field), /* offset */ \\\n\t}, \\\n\t/* ipaddr_data */ \\\n\t{ \\\n\t\tCMDLINE_IPADDR_V6, /* flags */ \\\n\t}, \\\n}\n\n#define TOKEN_IPNET_INITIALIZER(structure, field) \\\n{ \\\n\t/* hdr */ \\\n\t{ \\\n\t\t&cmdline_token_ipaddr_ops, /* ops */ \\\n\t\toffsetof(structure, field), /* offset */ \\\n\t}, \\\n\t/* ipaddr_data */ \\\n\t{ \\\n\t\tCMDLINE_IPADDR_V4 | /* flags */ \\\n\t\tCMDLINE_IPADDR_V6 | \\\n\t\tCMDLINE_IPADDR_NETWORK, \\\n\t}, \\\n}\n\n#define TOKEN_IPV4NET_INITIALIZER(structure, field) \\\n{ \\\n\t/* hdr */ \\\n\t{ \\\n\t\t&cmdline_token_ipaddr_ops, /* ops */ \\\n\t\toffsetof(structure, field), /* offset */ \\\n\t}, \\\n\t/* ipaddr_data */ \\\n\t{ \\\n\t\tCMDLINE_IPADDR_V4 | /* flags */ \\\n\t\tCMDLINE_IPADDR_NETWORK, \\\n\t}, \\\n}\n\n#define TOKEN_IPV6NET_INITIALIZER(structure, field) \\\n{ \\\n\t/* hdr */ \\\n\t{ \\\n\t\t&cmdline_token_ipaddr_ops, /* ops */ \\\n\t\toffsetof(structure, field), /* offset */ \\\n\t}, \\\n\t/* ipaddr_data */ \\\n\t{ \\\n\t\tCMDLINE_IPADDR_V4 | /* flags */ \\\n\t\tCMDLINE_IPADDR_NETWORK, \\\n\t}, \\\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _PARSE_IPADDR_H_ */\n" }, { "path": "lib/librte_cmdline/cmdline_parse_num.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"cmdline_parse.h\"\n#include \"cmdline_parse_num.h\"\n\n#ifdef RTE_LIBRTE_CMDLINE_DEBUG\n#define debug_printf(args...) printf(args)\n#else\n#define debug_printf(args...) do {} while(0)\n#endif\n\nstruct cmdline_token_ops cmdline_token_num_ops = {\n\t.parse = cmdline_parse_num,\n\t.complete_get_nb = NULL,\n\t.complete_get_elt = NULL,\n\t.get_help = cmdline_get_help_num,\n};\n\n\nenum num_parse_state_t {\n\tSTART,\n\tDEC_NEG,\n\tBIN,\n\tHEX,\n\n\tERROR,\n\n\tFIRST_OK, /* not used */\n\tZERO_OK,\n\tHEX_OK,\n\tOCTAL_OK,\n\tBIN_OK,\n\tDEC_NEG_OK,\n\tDEC_POS_OK,\n};\n\n/* Keep it sync with enum in .h */\nstatic const char * num_help[] = {\n\t\"UINT8\", \"UINT16\", \"UINT32\", \"UINT64\",\n\t\"INT8\", \"INT16\", \"INT32\", \"INT64\",\n};\n\nstatic inline int\nadd_to_res(unsigned int c, uint64_t *res, unsigned int base)\n{\n\t/* overflow */\n\tif ( (UINT64_MAX - c) / base < *res ) {\n\t\treturn -1;\n\t}\n\n\t*res = (uint64_t) (*res * base + c);\n\treturn 0;\n}\n\nstatic int\ncheck_res_size(struct cmdline_token_num_data *nd, unsigned ressize)\n{\n\tswitch (nd->type) {\n\tcase INT8:\n\tcase UINT8:\n\t\tif (ressize < sizeof(int8_t))\n\t\t\treturn -1;\n\t\tbreak;\n\tcase INT16:\n\tcase UINT16:\n\t\tif (ressize < sizeof(int16_t))\n\t\t\treturn -1;\n\t\tbreak;\n\tcase INT32:\n\tcase UINT32:\n\t\tif (ressize < sizeof(int32_t))\n\t\t\treturn -1;\n\t\tbreak;\n\tcase INT64:\n\tcase UINT64:\n\t\tif (ressize < sizeof(int64_t))\n\t\t\treturn -1;\n\t\tbreak;\n\tdefault:\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/* parse an int */\nint\ncmdline_parse_num(cmdline_parse_token_hdr_t *tk, const char *srcbuf, void *res,\n\tunsigned ressize)\n{\n\tstruct cmdline_token_num_data nd;\n\tenum num_parse_state_t st = START;\n\tconst char * buf;\n\tchar c;\n\tuint64_t res1 = 0;\n\n\tif (!tk)\n\t\treturn -1;\n\n\tif (!srcbuf || !*srcbuf)\n\t\treturn -1;\n\n\tbuf = srcbuf;\n\tc = *buf;\n\n\tmemcpy(&nd, &((struct cmdline_token_num *)tk)->num_data, sizeof(nd));\n\n\t/* check that we have enough room in res */\n\tif (res) {\n\t\tif (check_res_size(&nd, ressize) < 0)\n\t\t\treturn -1;\n\t}\n\n\twhile ( st != ERROR && c && ! cmdline_isendoftoken(c) ) {\n\t\tdebug_printf(\"%c %x -> \", c, c);\n\t\tswitch (st) {\n\t\tcase START:\n\t\t\tif (c == '-') {\n\t\t\t\tst = DEC_NEG;\n\t\t\t}\n\t\t\telse if (c == '0') {\n\t\t\t\tst = ZERO_OK;\n\t\t\t}\n\t\t\telse if (c >= '1' && c <= '9') {\n\t\t\t\tif (add_to_res(c - '0', &res1, 10) < 0)\n\t\t\t\t\tst = ERROR;\n\t\t\t\telse\n\t\t\t\t\tst = DEC_POS_OK;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase ZERO_OK:\n\t\t\tif (c == 'x') {\n\t\t\t\tst = HEX;\n\t\t\t}\n\t\t\telse if (c == 'b') {\n\t\t\t\tst = BIN;\n\t\t\t}\n\t\t\telse if (c >= '0' && c <= '7') {\n\t\t\t\tif (add_to_res(c - '0', &res1, 10) < 0)\n\t\t\t\t\tst = ERROR;\n\t\t\t\telse\n\t\t\t\t\tst = OCTAL_OK;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase DEC_NEG:\n\t\t\tif (c >= '0' && c <= '9') {\n\t\t\t\tif (add_to_res(c - '0', &res1, 10) < 0)\n\t\t\t\t\tst = ERROR;\n\t\t\t\telse\n\t\t\t\t\tst = DEC_NEG_OK;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase DEC_NEG_OK:\n\t\t\tif (c >= '0' && c <= '9') {\n\t\t\t\tif (add_to_res(c - '0', &res1, 10) < 0)\n\t\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase DEC_POS_OK:\n\t\t\tif (c >= '0' && c <= '9') {\n\t\t\t\tif (add_to_res(c - '0', &res1, 10) < 0)\n\t\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase HEX:\n\t\t\tst = HEX_OK;\n\t\t\t/* no break */\n\t\tcase HEX_OK:\n\t\t\tif (c >= '0' && c <= '9') {\n\t\t\t\tif (add_to_res(c - '0', &res1, 16) < 0)\n\t\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\telse if (c >= 'a' && c <= 'f') {\n\t\t\t\tif (add_to_res(c - 'a' + 10, &res1, 16) < 0)\n\t\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\telse if (c >= 'A' && c <= 'F') {\n\t\t\t\tif (add_to_res(c - 'A' + 10, &res1, 16) < 0)\n\t\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\tbreak;\n\n\n\t\tcase OCTAL_OK:\n\t\t\tif (c >= '0' && c <= '7') {\n\t\t\t\tif (add_to_res(c - '0', &res1, 8) < 0)\n\t\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase BIN:\n\t\t\tst = BIN_OK;\n\t\t\t/* no break */\n\t\tcase BIN_OK:\n\t\t\tif (c >= '0' && c <= '1') {\n\t\t\t\tif (add_to_res(c - '0', &res1, 2) < 0)\n\t\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tst = ERROR;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tdebug_printf(\"not impl \");\n\n\t\t}\n\n\t\tdebug_printf(\"(%\"PRIu64\")\\n\", res1);\n\n\t\tbuf ++;\n\t\tc = *buf;\n\n\t\t/* token too long */\n\t\tif (buf-srcbuf > 127)\n\t\t\treturn -1;\n\t}\n\n\tswitch (st) {\n\tcase ZERO_OK:\n\tcase DEC_POS_OK:\n\tcase HEX_OK:\n\tcase OCTAL_OK:\n\tcase BIN_OK:\n\t\tif ( nd.type == INT8 && res1 <= INT8_MAX ) {\n\t\t\tif (res) *(int8_t *)res = (int8_t) res1;\n\t\t\treturn buf-srcbuf;\n\t\t}\n\t\telse if ( nd.type == INT16 && res1 <= INT16_MAX ) {\n\t\t\tif (res) *(int16_t *)res = (int16_t) res1;\n\t\t\treturn buf-srcbuf;\n\t\t}\n\t\telse if ( nd.type == INT32 && res1 <= INT32_MAX ) {\n\t\t\tif (res) *(int32_t *)res = (int32_t) res1;\n\t\t\treturn buf-srcbuf;\n\t\t}\n\t\telse if ( nd.type == INT64 && res1 <= INT64_MAX ) {\n\t\t\tif (res) *(int64_t *)res = (int64_t) res1;\n\t\t\treturn buf-srcbuf;\n\t\t}\n\t\telse if ( nd.type == UINT8 && res1 <= UINT8_MAX ) {\n\t\t\tif (res) *(uint8_t *)res = (uint8_t) res1;\n\t\t\treturn buf-srcbuf;\n\t\t}\n\t\telse if (nd.type == UINT16 && res1 <= UINT16_MAX ) {\n\t\t\tif (res) *(uint16_t *)res = (uint16_t) res1;\n\t\t\treturn buf-srcbuf;\n\t\t}\n\t\telse if ( nd.type == UINT32 && res1 <= UINT32_MAX ) {\n\t\t\tif (res) *(uint32_t *)res = (uint32_t) res1;\n\t\t\treturn buf-srcbuf;\n\t\t}\n\t\telse if ( nd.type == UINT64 ) {\n\t\t\tif (res) *(uint64_t *)res = res1;\n\t\t\treturn buf-srcbuf;\n\t\t}\n\t\telse {\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\n\tcase DEC_NEG_OK:\n\t\tif ( nd.type == INT8 && res1 <= INT8_MAX + 1 ) {\n\t\t\tif (res) *(int8_t *)res = (int8_t) (-res1);\n\t\t\treturn buf-srcbuf;\n\t\t}\n\t\telse if ( nd.type == INT16 && res1 <= (uint16_t)INT16_MAX + 1 ) {\n\t\t\tif (res) *(int16_t *)res = (int16_t) (-res1);\n\t\t\treturn buf-srcbuf;\n\t\t}\n\t\telse if ( nd.type == INT32 && res1 <= (uint32_t)INT32_MAX + 1 ) {\n\t\t\tif (res) *(int32_t *)res = (int32_t) (-res1);\n\t\t\treturn buf-srcbuf;\n\t\t}\n\t\telse if ( nd.type == INT64 && res1 <= (uint64_t)INT64_MAX + 1 ) {\n\t\t\tif (res) *(int64_t *)res = (int64_t) (-res1);\n\t\t\treturn buf-srcbuf;\n\t\t}\n\t\telse {\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tdebug_printf(\"error\\n\");\n\t\treturn -1;\n\t}\n}\n\n\n/* parse an int */\nint\ncmdline_get_help_num(cmdline_parse_token_hdr_t *tk, char *dstbuf, unsigned int size)\n{\n\tstruct cmdline_token_num_data nd;\n\tint ret;\n\n\tif (!tk)\n\t\treturn -1;\n\n\tmemcpy(&nd, &((struct cmdline_token_num *)tk)->num_data, sizeof(nd));\n\n\t/* should not happen.... don't so this test */\n\t/* if (nd.type >= (sizeof(num_help)/sizeof(const char *))) */\n\t/* return -1; */\n\n\tret = snprintf(dstbuf, size, \"%s\", num_help[nd.type]);\n\tif (ret < 0)\n\t\treturn -1;\n\tdstbuf[size-1] = '\\0';\n\treturn 0;\n}\n" }, { "path": "lib/librte_cmdline/cmdline_parse_num.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _PARSE_NUM_H_\n#define _PARSE_NUM_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nenum cmdline_numtype {\n\tUINT8 = 0,\n\tUINT16,\n\tUINT32,\n\tUINT64,\n\tINT8,\n\tINT16,\n\tINT32,\n\tINT64\n};\n\nstruct cmdline_token_num_data {\n\tenum cmdline_numtype type;\n};\n\nstruct cmdline_token_num {\n\tstruct cmdline_token_hdr hdr;\n\tstruct cmdline_token_num_data num_data;\n};\ntypedef struct cmdline_token_num cmdline_parse_token_num_t;\n\nextern struct cmdline_token_ops cmdline_token_num_ops;\n\nint cmdline_parse_num(cmdline_parse_token_hdr_t *tk,\n\tconst char *srcbuf, void *res, unsigned ressize);\nint cmdline_get_help_num(cmdline_parse_token_hdr_t *tk,\n\tchar *dstbuf, unsigned int size);\n\n#define TOKEN_NUM_INITIALIZER(structure, field, numtype) \\\n{ \\\n\t/* hdr */ \\\n\t{ \\\n\t\t&cmdline_token_num_ops, /* ops */ \\\n\t\toffsetof(structure, field), /* offset */ \\\n\t}, \\\n\t/* num_data */ \\\n\t{ \\\n\t\tnumtype, /* type */ \\\n\t}, \\\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _PARSE_NUM_H_ */\n" }, { "path": "lib/librte_cmdline/cmdline_parse_portlist.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2010, Keith Wiles \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \"cmdline_parse.h\"\n#include \"cmdline_parse_portlist.h\"\n\nstruct cmdline_token_ops cmdline_token_portlist_ops = {\n\t.parse = cmdline_parse_portlist,\n\t.complete_get_nb = NULL,\n\t.complete_get_elt = NULL,\n\t.get_help = cmdline_get_help_portlist,\n};\n\nstatic void\nparse_set_list(cmdline_portlist_t *pl, size_t low, size_t high)\n{\n\tdo {\n\t\tpl->map |= (1 << low++);\n\t} while (low <= high);\n}\n\nstatic int\nparse_ports(cmdline_portlist_t *pl, const char *str)\n{\n\tsize_t ps, pe;\n\tconst char *first, *last;\n\tchar *end;\n\n\tfor (first = str, last = first;\n\t first != NULL && last != NULL;\n\t first = last + 1) {\n\n\t\tlast = strchr(first, ',');\n\n\t\terrno = 0;\n\t\tps = strtoul(first, &end, 10);\n\t\tif (errno != 0 || end == first ||\n\t\t (end[0] != '-' && end[0] != 0 && end != last))\n\t\t\treturn -1;\n\n\t\t/* Support for N-M portlist format */\n\t\tif (end[0] == '-') {\n\t\t\terrno = 0;\n\t\t\tfirst = end + 1;\n\t\t\tpe = strtoul(first, &end, 10);\n\t\t\tif (errno != 0 || end == first ||\n\t\t\t (end[0] != 0 && end != last))\n\t\t\t\treturn -1;\n\t\t} else {\n\t\t\tpe = ps;\n\t\t}\n\n\t\tif (ps > pe || pe >= sizeof (pl->map) * 8)\n\t\t\treturn -1;\n\n\t\tparse_set_list(pl, ps, pe);\n\t}\n\n\treturn 0;\n}\n\nint\ncmdline_parse_portlist(__attribute__((unused)) cmdline_parse_token_hdr_t *tk,\n\tconst char *buf, void *res, unsigned ressize)\n{\n\tunsigned int token_len = 0;\n\tchar portlist_str[PORTLIST_TOKEN_SIZE+1];\n\tcmdline_portlist_t *pl;\n\n\tif (!buf || ! *buf)\n\t\treturn -1;\n\n\tif (res && ressize < sizeof(cmdline_portlist_t))\n\t\treturn -1;\n\n\tpl = res;\n\n\twhile (!cmdline_isendoftoken(buf[token_len]) &&\n\t (token_len < PORTLIST_TOKEN_SIZE))\n\t\ttoken_len++;\n\n\tif (token_len >= PORTLIST_TOKEN_SIZE)\n\t\treturn -1;\n\n\tsnprintf(portlist_str, token_len+1, \"%s\", buf);\n\n\tif (pl) {\n\t\tpl->map = 0;\n\t\tif (strcmp(\"all\", portlist_str) == 0)\n\t\t\tpl->map\t= UINT32_MAX;\n\t\telse if (parse_ports(pl, portlist_str) != 0)\n\t\t\treturn -1;\n\t}\n\n\treturn token_len;\n}\n\nint\ncmdline_get_help_portlist(__attribute__((unused)) cmdline_parse_token_hdr_t *tk,\n\t\tchar *dstbuf, unsigned int size)\n{\n\tint ret;\n\tret = snprintf(dstbuf, size, \"range of ports as 3,4-6,8-19,20\");\n\tif (ret < 0)\n\t\treturn -1;\n\treturn 0;\n}\n" }, { "path": "lib/librte_cmdline/cmdline_parse_portlist.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2010, Keith Wiles \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _PARSE_PORTLIST_H_\n#define _PARSE_PORTLIST_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* size of a parsed string */\n#define PORTLIST_TOKEN_SIZE\t128\n#define PORTLIST_MAX_TOKENS\t32\n\ntypedef struct cmdline_portlist {\n\tuint32_t\t\tmap;\n} cmdline_portlist_t;\n\nstruct cmdline_token_portlist {\n\tstruct cmdline_token_hdr hdr;\n};\ntypedef struct cmdline_token_portlist cmdline_parse_token_portlist_t;\n\nextern struct cmdline_token_ops cmdline_token_portlist_ops;\n\nint cmdline_parse_portlist(cmdline_parse_token_hdr_t *tk,\n\tconst char *srcbuf, void *res, unsigned ressize);\nint cmdline_get_help_portlist(cmdline_parse_token_hdr_t *tk,\n\tchar *dstbuf, unsigned int size);\n\n#define TOKEN_PORTLIST_INITIALIZER(structure, field) \\\n{ \\\n\t/* hdr */ \\\n\t{ \\\n\t\t&cmdline_token_portlist_ops, /* ops */ \\\n\t\toffsetof(structure, field), /* offset */ \\\n\t}, \\\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _PARSE_PORTLIST_H_ */\n" }, { "path": "lib/librte_cmdline/cmdline_parse_string.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"cmdline_parse.h\"\n#include \"cmdline_parse_string.h\"\n\nstruct cmdline_token_ops cmdline_token_string_ops = {\n\t.parse = cmdline_parse_string,\n\t.complete_get_nb = cmdline_complete_get_nb_string,\n\t.complete_get_elt = cmdline_complete_get_elt_string,\n\t.get_help = cmdline_get_help_string,\n};\n\n#define MULTISTRING_HELP \"Mul-choice STRING\"\n#define ANYSTRING_HELP \"Any STRING\"\n#define FIXEDSTRING_HELP \"Fixed STRING\"\n\nstatic unsigned int\nget_token_len(const char *s)\n{\n\tchar c;\n\tunsigned int i=0;\n\n\tc = s[i];\n\twhile (c!='#' && c!='\\0') {\n\t\ti++;\n\t\tc = s[i];\n\t}\n\treturn i;\n}\n\nstatic const char *\nget_next_token(const char *s)\n{\n\tunsigned int i;\n\ti = get_token_len(s);\n\tif (s[i] == '#')\n\t\treturn s+i+1;\n\treturn NULL;\n}\n\nint\ncmdline_parse_string(cmdline_parse_token_hdr_t *tk, const char *buf, void *res,\n\tunsigned ressize)\n{\n\tstruct cmdline_token_string *tk2;\n\tstruct cmdline_token_string_data *sd;\n\tunsigned int token_len;\n\tconst char *str;\n\n\tif (res && ressize < STR_TOKEN_SIZE)\n\t\treturn -1;\n\n\tif (!tk || !buf || ! *buf)\n\t\treturn -1;\n\n\ttk2 = (struct cmdline_token_string *)tk;\n\n\tsd = &tk2->string_data;\n\n\t/* fixed string */\n\tif (sd->str) {\n\t\tstr = sd->str;\n\t\tdo {\n\t\t\ttoken_len = get_token_len(str);\n\n\t\t\t/* if token is too big... */\n\t\t\tif (token_len >= STR_TOKEN_SIZE - 1) {\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif ( strncmp(buf, str, token_len) ) {\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif ( !cmdline_isendoftoken(*(buf+token_len)) ) {\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tbreak;\n\t\t} while ( (str = get_next_token(str)) != NULL );\n\n\t\tif (!str)\n\t\t\treturn -1;\n\t}\n\t/* unspecified string */\n\telse {\n\t\ttoken_len = 0;\n\t\twhile(!cmdline_isendoftoken(buf[token_len]) &&\n\t\t token_len < (STR_TOKEN_SIZE-1))\n\t\t\ttoken_len++;\n\n\t\t/* return if token too long */\n\t\tif (token_len >= STR_TOKEN_SIZE - 1) {\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (res) {\n\t\t/* we are sure that token_len is < STR_TOKEN_SIZE-1 */\n\t\tsnprintf(res, STR_TOKEN_SIZE, \"%s\", buf);\n\t\t*((char *)res + token_len) = 0;\n\t}\n\n\n\treturn token_len;\n}\n\nint cmdline_complete_get_nb_string(cmdline_parse_token_hdr_t *tk)\n{\n\tstruct cmdline_token_string *tk2;\n\tstruct cmdline_token_string_data *sd;\n\tconst char *str;\n\tint ret = 1;\n\n\tif (!tk)\n\t\treturn -1;\n\n\ttk2 = (struct cmdline_token_string *)tk;\n\tsd = &tk2->string_data;\n\n\tif (!sd->str)\n\t\treturn 0;\n\n\tstr = sd->str;\n\twhile( (str = get_next_token(str)) != NULL ) {\n\t\tret++;\n\t}\n\treturn ret;\n}\n\nint cmdline_complete_get_elt_string(cmdline_parse_token_hdr_t *tk, int idx,\n\t\t\t\t char *dstbuf, unsigned int size)\n{\n\tstruct cmdline_token_string *tk2;\n\tstruct cmdline_token_string_data *sd;\n\tconst char *s;\n\tunsigned int len;\n\n\tif (!tk || !dstbuf || idx < 0)\n\t\treturn -1;\n\n\ttk2 = (struct cmdline_token_string *)tk;\n\tsd = &tk2->string_data;\n\n\ts = sd->str;\n\n\twhile (idx-- && s)\n\t\ts = get_next_token(s);\n\n\tif (!s)\n\t\treturn -1;\n\n\tlen = get_token_len(s);\n\tif (len > size - 1)\n\t\treturn -1;\n\n\tmemcpy(dstbuf, s, len);\n\tdstbuf[len] = '\\0';\n\treturn 0;\n}\n\n\nint cmdline_get_help_string(cmdline_parse_token_hdr_t *tk, char *dstbuf,\n\t\t\t unsigned int size)\n{\n\tstruct cmdline_token_string *tk2;\n\tstruct cmdline_token_string_data *sd;\n\tconst char *s;\n\n\tif (!tk || !dstbuf)\n\t\treturn -1;\n\n\ttk2 = (struct cmdline_token_string *)tk;\n\tsd = &tk2->string_data;\n\n\ts = sd->str;\n\n\tif (s) {\n\t\tif (get_next_token(s))\n\t\t\tsnprintf(dstbuf, size, MULTISTRING_HELP);\n\t\telse\n\t\t\tsnprintf(dstbuf, size, FIXEDSTRING_HELP);\n\t} else\n\t\tsnprintf(dstbuf, size, ANYSTRING_HELP);\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_cmdline/cmdline_parse_string.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _PARSE_STRING_H_\n#define _PARSE_STRING_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* size of a parsed string */\n#define STR_TOKEN_SIZE 128\n\ntypedef char cmdline_fixed_string_t[STR_TOKEN_SIZE];\n\nstruct cmdline_token_string_data {\n\tconst char *str;\n};\n\nstruct cmdline_token_string {\n\tstruct cmdline_token_hdr hdr;\n\tstruct cmdline_token_string_data string_data;\n};\ntypedef struct cmdline_token_string cmdline_parse_token_string_t;\n\nextern struct cmdline_token_ops cmdline_token_string_ops;\n\nint cmdline_parse_string(cmdline_parse_token_hdr_t *tk, const char *srcbuf,\n\tvoid *res, unsigned ressize);\nint cmdline_complete_get_nb_string(cmdline_parse_token_hdr_t *tk);\nint cmdline_complete_get_elt_string(cmdline_parse_token_hdr_t *tk, int idx,\n\t\t\t\t char *dstbuf, unsigned int size);\nint cmdline_get_help_string(cmdline_parse_token_hdr_t *tk, char *dstbuf,\n\t\t\t unsigned int size);\n\n#define TOKEN_STRING_INITIALIZER(structure, field, string) \\\n{ \\\n\t/* hdr */ \\\n\t{ \\\n\t\t&cmdline_token_string_ops, /* ops */ \\\n\t\toffsetof(structure, field), /* offset */ \\\n\t}, \\\n\t/* string_data */ \\\n\t{ \\\n\t\tstring, /* str */ \\\n\t}, \\\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _PARSE_STRING_H_ */\n" }, { "path": "lib/librte_cmdline/cmdline_rdline.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"cmdline_cirbuf.h\"\n#include \"cmdline_rdline.h\"\n\nstatic void rdline_puts(struct rdline *rdl, const char *buf);\nstatic void rdline_miniprintf(struct rdline *rdl,\n\t\t\t const char *buf, unsigned int val);\n\nstatic void rdline_remove_old_history_item(struct rdline *rdl);\nstatic void rdline_remove_first_history_item(struct rdline *rdl);\nstatic unsigned int rdline_get_history_size(struct rdline *rdl);\n\n\n/* isblank() needs _XOPEN_SOURCE >= 600 || _ISOC99_SOURCE, so use our\n * own. */\nstatic int\nisblank2(char c)\n{\n\tif (c == ' ' ||\n\t c == '\\t' )\n\t\treturn 1;\n\treturn 0;\n}\n\nint\nrdline_init(struct rdline *rdl,\n\t\t rdline_write_char_t *write_char,\n\t\t rdline_validate_t *validate,\n\t\t rdline_complete_t *complete)\n{\n\tif (!rdl || !write_char || !validate || !complete)\n\t\treturn -EINVAL;\n\tmemset(rdl, 0, sizeof(*rdl));\n\trdl->validate = validate;\n\trdl->complete = complete;\n\trdl->write_char = write_char;\n\trdl->status = RDLINE_INIT;\n\treturn cirbuf_init(&rdl->history, rdl->history_buf, 0, RDLINE_HISTORY_BUF_SIZE);\n}\n\nvoid\nrdline_newline(struct rdline *rdl, const char *prompt)\n{\n\tunsigned int i;\n\n\tif (!rdl || !prompt)\n\t\treturn;\n\n\tvt100_init(&rdl->vt100);\n\tcirbuf_init(&rdl->left, rdl->left_buf, 0, RDLINE_BUF_SIZE);\n\tcirbuf_init(&rdl->right, rdl->right_buf, 0, RDLINE_BUF_SIZE);\n\n\trdl->prompt_size = strnlen(prompt, RDLINE_PROMPT_SIZE-1);\n\tif (prompt != rdl->prompt)\n\t\tmemcpy(rdl->prompt, prompt, rdl->prompt_size);\n\trdl->prompt[RDLINE_PROMPT_SIZE-1] = '\\0';\n\n\tfor (i=0 ; iprompt_size ; i++)\n\t\trdl->write_char(rdl, rdl->prompt[i]);\n\trdl->status = RDLINE_RUNNING;\n\n\trdl->history_cur_line = -1;\n}\n\nvoid\nrdline_stop(struct rdline *rdl)\n{\n\tif (!rdl)\n\t\treturn;\n\trdl->status = RDLINE_INIT;\n}\n\nvoid\nrdline_quit(struct rdline *rdl)\n{\n\tif (!rdl)\n\t\treturn;\n\trdl->status = RDLINE_EXITED;\n}\n\nvoid\nrdline_restart(struct rdline *rdl)\n{\n\tif (!rdl)\n\t\treturn;\n\trdl->status = RDLINE_RUNNING;\n}\n\nvoid\nrdline_reset(struct rdline *rdl)\n{\n\tif (!rdl)\n\t\treturn;\n\tvt100_init(&rdl->vt100);\n\tcirbuf_init(&rdl->left, rdl->left_buf, 0, RDLINE_BUF_SIZE);\n\tcirbuf_init(&rdl->right, rdl->right_buf, 0, RDLINE_BUF_SIZE);\n\n\trdl->status = RDLINE_RUNNING;\n\n\trdl->history_cur_line = -1;\n}\n\nconst char *\nrdline_get_buffer(struct rdline *rdl)\n{\n\tif (!rdl)\n\t\treturn NULL;\n\tunsigned int len_l, len_r;\n\tcirbuf_align_left(&rdl->left);\n\tcirbuf_align_left(&rdl->right);\n\n\tlen_l = CIRBUF_GET_LEN(&rdl->left);\n\tlen_r = CIRBUF_GET_LEN(&rdl->right);\n\tmemcpy(rdl->left_buf+len_l, rdl->right_buf, len_r);\n\n\trdl->left_buf[len_l + len_r] = '\\n';\n\trdl->left_buf[len_l + len_r + 1] = '\\0';\n\treturn rdl->left_buf;\n}\n\nstatic void\ndisplay_right_buffer(struct rdline *rdl, int force)\n{\n\tunsigned int i;\n\tchar tmp;\n\n\tif (!force && CIRBUF_IS_EMPTY(&rdl->right))\n\t\treturn;\n\n\trdline_puts(rdl, vt100_clear_right);\n\tCIRBUF_FOREACH(&rdl->right, i, tmp) {\n\t\trdl->write_char(rdl, tmp);\n\t}\n\tif (!CIRBUF_IS_EMPTY(&rdl->right))\n\t\trdline_miniprintf(rdl, vt100_multi_left,\n\t\t\t\t CIRBUF_GET_LEN(&rdl->right));\n}\n\nvoid\nrdline_redisplay(struct rdline *rdl)\n{\n\tunsigned int i;\n\tchar tmp;\n\n\tif (!rdl)\n\t\treturn;\n\n\trdline_puts(rdl, vt100_home);\n\tfor (i=0 ; iprompt_size ; i++)\n\t\trdl->write_char(rdl, rdl->prompt[i]);\n\tCIRBUF_FOREACH(&rdl->left, i, tmp) {\n\t\trdl->write_char(rdl, tmp);\n\t}\n\tdisplay_right_buffer(rdl, 1);\n}\n\nint\nrdline_char_in(struct rdline *rdl, char c)\n{\n\tunsigned int i;\n\tint cmd;\n\tchar tmp;\n\tchar *buf;\n\n\tif (!rdl)\n\t\treturn -EINVAL;\n\n\tif (rdl->status == RDLINE_EXITED)\n\t\treturn RDLINE_RES_EXITED;\n\tif (rdl->status != RDLINE_RUNNING)\n\t\treturn RDLINE_RES_NOT_RUNNING;\n\n\tcmd = vt100_parser(&rdl->vt100, c);\n\tif (cmd == -2)\n\t\treturn RDLINE_RES_SUCCESS;\n\n\tif (cmd >= 0) {\n\t\tswitch (cmd) {\n\t\t/* move caret 1 char to the left */\n\t\tcase CMDLINE_KEY_CTRL_B:\n\t\tcase CMDLINE_KEY_LEFT_ARR:\n\t\t\tif (CIRBUF_IS_EMPTY(&rdl->left))\n\t\t\t\tbreak;\n\t\t\ttmp = cirbuf_get_tail(&rdl->left);\n\t\t\tcirbuf_del_tail(&rdl->left);\n\t\t\tcirbuf_add_head(&rdl->right, tmp);\n\t\t\trdline_puts(rdl, vt100_left_arr);\n\t\t\tbreak;\n\n\t\t/* move caret 1 char to the right */\n\t\tcase CMDLINE_KEY_CTRL_F:\n\t\tcase CMDLINE_KEY_RIGHT_ARR:\n\t\t\tif (CIRBUF_IS_EMPTY(&rdl->right))\n\t\t\t\tbreak;\n\t\t\ttmp = cirbuf_get_head(&rdl->right);\n\t\t\tcirbuf_del_head(&rdl->right);\n\t\t\tcirbuf_add_tail(&rdl->left, tmp);\n\t\t\trdline_puts(rdl, vt100_right_arr);\n\t\t\tbreak;\n\n\t\t/* move caret 1 word to the left */\n\t\t/* keyboard equivalent: Alt+B */\n\t\tcase CMDLINE_KEY_WLEFT:\n\t\t\twhile (! CIRBUF_IS_EMPTY(&rdl->left) &&\n\t\t\t (tmp = cirbuf_get_tail(&rdl->left)) &&\n\t\t\t isblank2(tmp)) {\n\t\t\t\trdline_puts(rdl, vt100_left_arr);\n\t\t\t\tcirbuf_del_tail(&rdl->left);\n\t\t\t\tcirbuf_add_head(&rdl->right, tmp);\n\t\t\t}\n\t\t\twhile (! CIRBUF_IS_EMPTY(&rdl->left) &&\n\t\t\t (tmp = cirbuf_get_tail(&rdl->left)) &&\n\t\t\t !isblank2(tmp)) {\n\t\t\t\trdline_puts(rdl, vt100_left_arr);\n\t\t\t\tcirbuf_del_tail(&rdl->left);\n\t\t\t\tcirbuf_add_head(&rdl->right, tmp);\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* move caret 1 word to the right */\n\t\t/* keyboard equivalent: Alt+F */\n\t\tcase CMDLINE_KEY_WRIGHT:\n\t\t\twhile (! CIRBUF_IS_EMPTY(&rdl->right) &&\n\t\t\t (tmp = cirbuf_get_head(&rdl->right)) &&\n\t\t\t isblank2(tmp)) {\n\t\t\t\trdline_puts(rdl, vt100_right_arr);\n\t\t\t\tcirbuf_del_head(&rdl->right);\n\t\t\t\tcirbuf_add_tail(&rdl->left, tmp);\n\t\t\t}\n\t\t\twhile (! CIRBUF_IS_EMPTY(&rdl->right) &&\n\t\t\t (tmp = cirbuf_get_head(&rdl->right)) &&\n\t\t\t !isblank2(tmp)) {\n\t\t\t\trdline_puts(rdl, vt100_right_arr);\n\t\t\t\tcirbuf_del_head(&rdl->right);\n\t\t\t\tcirbuf_add_tail(&rdl->left, tmp);\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* move caret to the left */\n\t\tcase CMDLINE_KEY_CTRL_A:\n\t\t\tif (CIRBUF_IS_EMPTY(&rdl->left))\n\t\t\t\tbreak;\n\t\t\trdline_miniprintf(rdl, vt100_multi_left,\n\t\t\t\t\t\tCIRBUF_GET_LEN(&rdl->left));\n\t\t\twhile (! CIRBUF_IS_EMPTY(&rdl->left)) {\n\t\t\t\ttmp = cirbuf_get_tail(&rdl->left);\n\t\t\t\tcirbuf_del_tail(&rdl->left);\n\t\t\t\tcirbuf_add_head(&rdl->right, tmp);\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* move caret to the right */\n\t\tcase CMDLINE_KEY_CTRL_E:\n\t\t\tif (CIRBUF_IS_EMPTY(&rdl->right))\n\t\t\t\tbreak;\n\t\t\trdline_miniprintf(rdl, vt100_multi_right,\n\t\t\t\t\t\tCIRBUF_GET_LEN(&rdl->right));\n\t\t\twhile (! CIRBUF_IS_EMPTY(&rdl->right)) {\n\t\t\t\ttmp = cirbuf_get_head(&rdl->right);\n\t\t\t\tcirbuf_del_head(&rdl->right);\n\t\t\t\tcirbuf_add_tail(&rdl->left, tmp);\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* delete 1 char from the left */\n\t\tcase CMDLINE_KEY_BKSPACE:\n\t\t\tif(!cirbuf_del_tail_safe(&rdl->left)) {\n\t\t\t\trdline_puts(rdl, vt100_bs);\n\t\t\t\tdisplay_right_buffer(rdl, 1);\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* delete 1 char from the right */\n\t\tcase CMDLINE_KEY_SUPPR:\n\t\tcase CMDLINE_KEY_CTRL_D:\n\t\t\tif (cmd == CMDLINE_KEY_CTRL_D &&\n\t\t\t CIRBUF_IS_EMPTY(&rdl->left) &&\n\t\t\t CIRBUF_IS_EMPTY(&rdl->right)) {\n\t\t\t\treturn RDLINE_RES_EOF;\n\t\t\t}\n\t\t\tif (!cirbuf_del_head_safe(&rdl->right)) {\n\t\t\t\tdisplay_right_buffer(rdl, 1);\n\t\t\t}\n\t\t\tbreak;\n\n\t\t/* delete 1 word from the left */\n\t\tcase CMDLINE_KEY_META_BKSPACE:\n\t\tcase CMDLINE_KEY_CTRL_W:\n\t\t\twhile (! CIRBUF_IS_EMPTY(&rdl->left) && isblank2(cirbuf_get_tail(&rdl->left))) {\n\t\t\t\trdline_puts(rdl, vt100_bs);\n\t\t\t\tcirbuf_del_tail(&rdl->left);\n\t\t\t}\n\t\t\twhile (! CIRBUF_IS_EMPTY(&rdl->left) && !isblank2(cirbuf_get_tail(&rdl->left))) {\n\t\t\t\trdline_puts(rdl, vt100_bs);\n\t\t\t\tcirbuf_del_tail(&rdl->left);\n\t\t\t}\n\t\t\tdisplay_right_buffer(rdl, 1);\n\t\t\tbreak;\n\n\t\t/* delete 1 word from the right */\n\t\tcase CMDLINE_KEY_META_D:\n\t\t\twhile (! CIRBUF_IS_EMPTY(&rdl->right) && isblank2(cirbuf_get_head(&rdl->right)))\n\t\t\t\tcirbuf_del_head(&rdl->right);\n\t\t\twhile (! CIRBUF_IS_EMPTY(&rdl->right) && !isblank2(cirbuf_get_head(&rdl->right)))\n\t\t\t\tcirbuf_del_head(&rdl->right);\n\t\t\tdisplay_right_buffer(rdl, 1);\n\t\t\tbreak;\n\n\t\t/* set kill buffer to contents on the right side of caret */\n\t\tcase CMDLINE_KEY_CTRL_K:\n\t\t\tcirbuf_get_buf_head(&rdl->right, rdl->kill_buf, RDLINE_BUF_SIZE);\n\t\t\trdl->kill_size = CIRBUF_GET_LEN(&rdl->right);\n\t\t\tcirbuf_del_buf_head(&rdl->right, rdl->kill_size);\n\t\t\trdline_puts(rdl, vt100_clear_right);\n\t\t\tbreak;\n\n\t\t/* paste contents of kill buffer to the left side of caret */\n\t\tcase CMDLINE_KEY_CTRL_Y:\n\t\t\ti=0;\n\t\t\twhile(CIRBUF_GET_LEN(&rdl->right) + CIRBUF_GET_LEN(&rdl->left) <\n\t\t\t RDLINE_BUF_SIZE &&\n\t\t\t i < rdl->kill_size) {\n\t\t\t\tcirbuf_add_tail(&rdl->left, rdl->kill_buf[i]);\n\t\t\t\trdl->write_char(rdl, rdl->kill_buf[i]);\n\t\t\t\ti++;\n\t\t\t}\n\t\t\tdisplay_right_buffer(rdl, 0);\n\t\t\tbreak;\n\n\t\t/* clear and newline */\n\t\tcase CMDLINE_KEY_CTRL_C:\n\t\t\trdline_puts(rdl, \"\\r\\n\");\n\t\t\trdline_newline(rdl, rdl->prompt);\n\t\t\tbreak;\n\n\t\t/* redisplay (helps when prompt is lost in other output) */\n\t\tcase CMDLINE_KEY_CTRL_L:\n\t\t\trdline_redisplay(rdl);\n\t\t\tbreak;\n\n\t\t/* autocomplete */\n\t\tcase CMDLINE_KEY_TAB:\n\t\tcase CMDLINE_KEY_HELP:\n\t\t\tcirbuf_align_left(&rdl->left);\n\t\t\trdl->left_buf[CIRBUF_GET_LEN(&rdl->left)] = '\\0';\n\t\t\tif (rdl->complete) {\n\t\t\t\tchar tmp_buf[BUFSIZ];\n\t\t\t\tint complete_state;\n\t\t\t\tint ret;\n\t\t\t\tunsigned int tmp_size;\n\n\t\t\t\tif (cmd == CMDLINE_KEY_TAB)\n\t\t\t\t\tcomplete_state = 0;\n\t\t\t\telse\n\t\t\t\t\tcomplete_state = -1;\n\n\t\t\t\t/* see in parse.h for help on complete() */\n\t\t\t\tret = rdl->complete(rdl, rdl->left_buf,\n\t\t\t\t\t\t tmp_buf, sizeof(tmp_buf),\n\t\t\t\t\t\t &complete_state);\n\t\t\t\t/* no completion or error */\n\t\t\t\tif (ret <= 0) {\n\t\t\t\t\treturn RDLINE_RES_COMPLETE;\n\t\t\t\t}\n\n\t\t\t\ttmp_size = strnlen(tmp_buf, sizeof(tmp_buf));\n\t\t\t\t/* add chars */\n\t\t\t\tif (ret == RDLINE_RES_COMPLETE) {\n\t\t\t\t\ti=0;\n\t\t\t\t\twhile(CIRBUF_GET_LEN(&rdl->right) + CIRBUF_GET_LEN(&rdl->left) <\n\t\t\t\t\t RDLINE_BUF_SIZE &&\n\t\t\t\t\t i < tmp_size) {\n\t\t\t\t\t\tcirbuf_add_tail(&rdl->left, tmp_buf[i]);\n\t\t\t\t\t\trdl->write_char(rdl, tmp_buf[i]);\n\t\t\t\t\t\ti++;\n\t\t\t\t\t}\n\t\t\t\t\tdisplay_right_buffer(rdl, 1);\n\t\t\t\t\treturn RDLINE_RES_COMPLETE; /* ?? */\n\t\t\t\t}\n\n\t\t\t\t/* choice */\n\t\t\t\trdline_puts(rdl, \"\\r\\n\");\n\t\t\t\twhile (ret) {\n\t\t\t\t\trdl->write_char(rdl, ' ');\n\t\t\t\t\tfor (i=0 ; tmp_buf[i] ; i++)\n\t\t\t\t\t\trdl->write_char(rdl, tmp_buf[i]);\n\t\t\t\t\trdline_puts(rdl, \"\\r\\n\");\n\t\t\t\t\tret = rdl->complete(rdl, rdl->left_buf,\n\t\t\t\t\t\t\t tmp_buf, sizeof(tmp_buf),\n\t\t\t\t\t\t\t &complete_state);\n\t\t\t\t}\n\n\t\t\t\trdline_redisplay(rdl);\n\t\t\t}\n\t\t\treturn RDLINE_RES_COMPLETE;\n\n\t\t/* complete buffer */\n\t\tcase CMDLINE_KEY_RETURN:\n\t\tcase CMDLINE_KEY_RETURN2:\n\t\t\trdline_get_buffer(rdl);\n\t\t\trdl->status = RDLINE_INIT;\n\t\t\trdline_puts(rdl, \"\\r\\n\");\n\t\t\tif (rdl->history_cur_line != -1)\n\t\t\t\trdline_remove_first_history_item(rdl);\n\n\t\t\tif (rdl->validate)\n\t\t\t\trdl->validate(rdl, rdl->left_buf, CIRBUF_GET_LEN(&rdl->left)+2);\n\t\t\t/* user may have stopped rdline */\n\t\t\tif (rdl->status == RDLINE_EXITED)\n\t\t\t\treturn RDLINE_RES_EXITED;\n\t\t\treturn RDLINE_RES_VALIDATED;\n\n\t\t/* previous element in history */\n\t\tcase CMDLINE_KEY_UP_ARR:\n\t\tcase CMDLINE_KEY_CTRL_P:\n\t\t\tif (rdl->history_cur_line == 0) {\n\t\t\t\trdline_remove_first_history_item(rdl);\n\t\t\t}\n\t\t\tif (rdl->history_cur_line <= 0) {\n\t\t\t\trdline_add_history(rdl, rdline_get_buffer(rdl));\n\t\t\t\trdl->history_cur_line = 0;\n\t\t\t}\n\n\t\t\tbuf = rdline_get_history_item(rdl, rdl->history_cur_line + 1);\n\t\t\tif (!buf)\n\t\t\t\tbreak;\n\n\t\t\trdl->history_cur_line ++;\n\t\t\tvt100_init(&rdl->vt100);\n\t\t\tcirbuf_init(&rdl->left, rdl->left_buf, 0, RDLINE_BUF_SIZE);\n\t\t\tcirbuf_init(&rdl->right, rdl->right_buf, 0, RDLINE_BUF_SIZE);\n\t\t\tcirbuf_add_buf_tail(&rdl->left, buf, strnlen(buf, RDLINE_BUF_SIZE));\n\t\t\trdline_redisplay(rdl);\n\t\t\tbreak;\n\n\t\t/* next element in history */\n\t\tcase CMDLINE_KEY_DOWN_ARR:\n\t\tcase CMDLINE_KEY_CTRL_N:\n\t\t\tif (rdl->history_cur_line - 1 < 0)\n\t\t\t\tbreak;\n\n\t\t\trdl->history_cur_line --;\n\t\t\tbuf = rdline_get_history_item(rdl, rdl->history_cur_line);\n\t\t\tif (!buf)\n\t\t\t\tbreak;\n\t\t\tvt100_init(&rdl->vt100);\n\t\t\tcirbuf_init(&rdl->left, rdl->left_buf, 0, RDLINE_BUF_SIZE);\n\t\t\tcirbuf_init(&rdl->right, rdl->right_buf, 0, RDLINE_BUF_SIZE);\n\t\t\tcirbuf_add_buf_tail(&rdl->left, buf, strnlen(buf, RDLINE_BUF_SIZE));\n\t\t\trdline_redisplay(rdl);\n\n\t\t\tbreak;\n\n\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\treturn RDLINE_RES_SUCCESS;\n\t}\n\n\tif (!isprint((int)c))\n\t\treturn RDLINE_RES_SUCCESS;\n\n\t/* standard chars */\n\tif (CIRBUF_GET_LEN(&rdl->left) + CIRBUF_GET_LEN(&rdl->right) >= RDLINE_BUF_SIZE)\n\t\treturn RDLINE_RES_SUCCESS;\n\n\tif (cirbuf_add_tail_safe(&rdl->left, c))\n\t\treturn RDLINE_RES_SUCCESS;\n\n\trdl->write_char(rdl, c);\n\tdisplay_right_buffer(rdl, 0);\n\n\treturn RDLINE_RES_SUCCESS;\n}\n\n\n/* HISTORY */\n\nstatic void\nrdline_remove_old_history_item(struct rdline * rdl)\n{\n\tchar tmp;\n\n\twhile (! CIRBUF_IS_EMPTY(&rdl->history) ) {\n\t\ttmp = cirbuf_get_head(&rdl->history);\n\t\tcirbuf_del_head(&rdl->history);\n\t\tif (!tmp)\n\t\t\tbreak;\n\t}\n}\n\nstatic void\nrdline_remove_first_history_item(struct rdline * rdl)\n{\n\tchar tmp;\n\n\tif ( CIRBUF_IS_EMPTY(&rdl->history) ) {\n\t\treturn;\n\t}\n\telse {\n\t\tcirbuf_del_tail(&rdl->history);\n\t}\n\n\twhile (! CIRBUF_IS_EMPTY(&rdl->history) ) {\n\t\ttmp = cirbuf_get_tail(&rdl->history);\n\t\tif (!tmp)\n\t\t\tbreak;\n\t\tcirbuf_del_tail(&rdl->history);\n\t}\n}\n\nstatic unsigned int\nrdline_get_history_size(struct rdline * rdl)\n{\n\tunsigned int i, tmp, ret=0;\n\n\tCIRBUF_FOREACH(&rdl->history, i, tmp) {\n\t\tif (tmp == 0)\n\t\t\tret ++;\n\t}\n\n\treturn ret;\n}\n\nchar *\nrdline_get_history_item(struct rdline * rdl, unsigned int idx)\n{\n\tunsigned int len, i, tmp;\n\n\tif (!rdl)\n\t\treturn NULL;\n\n\tlen = rdline_get_history_size(rdl);\n\tif ( idx >= len ) {\n\t\treturn NULL;\n\t}\n\n\tcirbuf_align_left(&rdl->history);\n\n\tCIRBUF_FOREACH(&rdl->history, i, tmp) {\n\t\tif ( idx == len - 1) {\n\t\t\treturn rdl->history_buf + i;\n\t\t}\n\t\tif (tmp == 0)\n\t\t\tlen --;\n\t}\n\n\treturn NULL;\n}\n\nint\nrdline_add_history(struct rdline * rdl, const char * buf)\n{\n\tunsigned int len, i;\n\n\tif (!rdl || !buf)\n\t\treturn -EINVAL;\n\n\tlen = strnlen(buf, RDLINE_BUF_SIZE);\n\tfor (i=0; i= RDLINE_HISTORY_BUF_SIZE )\n\t\treturn -1;\n\n\twhile ( len >= CIRBUF_GET_FREELEN(&rdl->history) ) {\n\t\trdline_remove_old_history_item(rdl);\n\t}\n\n\tcirbuf_add_buf_tail(&rdl->history, buf, len);\n\tcirbuf_add_tail(&rdl->history, 0);\n\n\treturn 0;\n}\n\nvoid\nrdline_clear_history(struct rdline * rdl)\n{\n\tif (!rdl)\n\t\treturn;\n\tcirbuf_init(&rdl->history, rdl->history_buf, 0, RDLINE_HISTORY_BUF_SIZE);\n}\n\n\n/* STATIC USEFUL FUNCS */\n\nstatic void\nrdline_puts(struct rdline * rdl, const char * buf)\n{\n\tchar c;\n\twhile ( (c = *(buf++)) != '\\0' ) {\n\t\trdl->write_char(rdl, c);\n\t}\n}\n\n/* a very very basic printf with one arg and one format 'u' */\nstatic void\nrdline_miniprintf(struct rdline *rdl, const char * buf, unsigned int val)\n{\n\tchar c, started=0, div=100;\n\n\twhile ( (c=*(buf++)) ) {\n\t\tif (c != '%') {\n\t\t\trdl->write_char(rdl, c);\n\t\t\tcontinue;\n\t\t}\n\t\tc = *(buf++);\n\t\tif (c != 'u') {\n\t\t\trdl->write_char(rdl, '%');\n\t\t\trdl->write_char(rdl, c);\n\t\t\tcontinue;\n\t\t}\n\t\t/* val is never more than 255 */\n\t\twhile (div) {\n\t\t\tc = (char)(val / div);\n\t\t\tif (c || started) {\n\t\t\t\trdl->write_char(rdl, (char)(c+'0'));\n\t\t\t\tstarted = 1;\n\t\t\t}\n\t\t\tval %= div;\n\t\t\tdiv /= 10;\n\t\t}\n\t}\n}\n" }, { "path": "lib/librte_cmdline/cmdline_rdline.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RDLINE_H_\n#define _RDLINE_H_\n\n/**\n * This file is a small equivalent to the GNU readline library, but it\n * was originally designed for small systems, like Atmel AVR\n * microcontrollers (8 bits). Indeed, we don't use any malloc that is\n * sometimes not implemented (or just not recommended) on such\n * systems.\n *\n * Obviously, it does not support as many things as the GNU readline,\n * but at least it supports some interesting features like a kill\n * buffer and a command history.\n *\n * It also have a feature that does not have the GNU readline (as far\n * as I know): we can have several instances of it running at the same\n * time, even on a monothread program, since it works with callbacks.\n *\n * The lib is designed for a client-side or a server-side use:\n * - server-side: the server receives all data from a socket, including\n * control chars, like arrows, tabulations, ... The client is\n * very simple, it can be a telnet or a minicom through a serial line.\n * - client-side: the client receives its data through its stdin for\n * instance.\n */\n\n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* configuration */\n#define RDLINE_BUF_SIZE 256\n#define RDLINE_PROMPT_SIZE 32\n#define RDLINE_VT100_BUF_SIZE 8\n#define RDLINE_HISTORY_BUF_SIZE BUFSIZ\n#define RDLINE_HISTORY_MAX_LINE 64\n\nenum rdline_status {\n\tRDLINE_INIT,\n\tRDLINE_RUNNING,\n\tRDLINE_EXITED\n};\n\nstruct rdline;\n\ntypedef int (rdline_write_char_t)(struct rdline *rdl, char);\ntypedef void (rdline_validate_t)(struct rdline *rdl,\n\t\t\t\t const char *buf, unsigned int size);\ntypedef int (rdline_complete_t)(struct rdline *rdl, const char *buf,\n\t\t\t\tchar *dstbuf, unsigned int dstsize,\n\t\t\t\tint *state);\n\nstruct rdline {\n\tenum rdline_status status;\n\t/* rdline bufs */\n\tstruct cirbuf left;\n\tstruct cirbuf right;\n\tchar left_buf[RDLINE_BUF_SIZE+2]; /* reserve 2 chars for the \\n\\0 */\n\tchar right_buf[RDLINE_BUF_SIZE];\n\n\tchar prompt[RDLINE_PROMPT_SIZE];\n\tunsigned int prompt_size;\n\n\tchar kill_buf[RDLINE_BUF_SIZE];\n\tunsigned int kill_size;\n\n\t/* history */\n\tstruct cirbuf history;\n\tchar history_buf[RDLINE_HISTORY_BUF_SIZE];\n\tint history_cur_line;\n\n\t/* callbacks and func pointers */\n\trdline_write_char_t *write_char;\n\trdline_validate_t *validate;\n\trdline_complete_t *complete;\n\n\t/* vt100 parser */\n\tstruct cmdline_vt100 vt100;\n\n\t/* opaque pointer */\n\tvoid *opaque;\n};\n\n/**\n * Init fields for a struct rdline. Call this only once at the beginning\n * of your program.\n * \\param rdl A pointer to an uninitialized struct rdline\n * \\param write_char The function used by the function to write a character\n * \\param validate A pointer to the function to execute when the\n * user validates the buffer.\n * \\param complete A pointer to the function to execute when the\n * user completes the buffer.\n */\nint rdline_init(struct rdline *rdl,\n\t\t rdline_write_char_t *write_char,\n\t\t rdline_validate_t *validate,\n\t\t rdline_complete_t *complete);\n\n\n/**\n * Init the current buffer, and display a prompt.\n * \\param rdl A pointer to a struct rdline\n * \\param prompt A string containing the prompt\n */\nvoid rdline_newline(struct rdline *rdl, const char *prompt);\n\n/**\n * Call it and all received chars will be ignored.\n * \\param rdl A pointer to a struct rdline\n */\nvoid rdline_stop(struct rdline *rdl);\n\n/**\n * Same than rdline_stop() except that next calls to rdline_char_in()\n * will return RDLINE_RES_EXITED.\n * \\param rdl A pointer to a struct rdline\n */\nvoid rdline_quit(struct rdline *rdl);\n\n/**\n * Restart after a call to rdline_stop() or rdline_quit()\n * \\param rdl A pointer to a struct rdline\n */\nvoid rdline_restart(struct rdline *rdl);\n\n/**\n * Redisplay the current buffer\n * \\param rdl A pointer to a struct rdline\n */\nvoid rdline_redisplay(struct rdline *rdl);\n\n/**\n * Reset the current buffer and setup for a new line.\n * \\param rdl A pointer to a struct rdline\n */\nvoid rdline_reset(struct rdline *rdl);\n\n\n/* return status for rdline_char_in() */\n#define RDLINE_RES_SUCCESS 0\n#define RDLINE_RES_VALIDATED 1\n#define RDLINE_RES_COMPLETE 2\n#define RDLINE_RES_NOT_RUNNING -1\n#define RDLINE_RES_EOF -2\n#define RDLINE_RES_EXITED -3\n\n/**\n * append a char to the readline buffer.\n * Return RDLINE_RES_VALIDATE when the line has been validated.\n * Return RDLINE_RES_COMPLETE when the user asked to complete the buffer.\n * Return RDLINE_RES_NOT_RUNNING if it is not running.\n * Return RDLINE_RES_EOF if EOF (ctrl-d on an empty line).\n * Else return RDLINE_RES_SUCCESS.\n * XXX error case when the buffer is full ?\n *\n * \\param rdl A pointer to a struct rdline\n * \\param c The character to append\n */\nint rdline_char_in(struct rdline *rdl, char c);\n\n/**\n * Return the current buffer, terminated by '\\0'.\n * \\param rdl A pointer to a struct rdline\n */\nconst char *rdline_get_buffer(struct rdline *rdl);\n\n\n/**\n * Add the buffer to history.\n * return < 0 on error.\n * \\param rdl A pointer to a struct rdline\n * \\param buf A buffer that is terminated by '\\0'\n */\nint rdline_add_history(struct rdline *rdl, const char *buf);\n\n/**\n * Clear current history\n * \\param rdl A pointer to a struct rdline\n */\nvoid rdline_clear_history(struct rdline *rdl);\n\n/**\n * Get the i-th history item\n */\nchar *rdline_get_history_item(struct rdline *rdl, unsigned int i);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RDLINE_H_ */\n" }, { "path": "lib/librte_cmdline/cmdline_socket.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"cmdline_parse.h\"\n#include \"cmdline_rdline.h\"\n#include \"cmdline_socket.h\"\n#include \"cmdline.h\"\n\nstruct cmdline *\ncmdline_file_new(cmdline_parse_ctx_t *ctx, const char *prompt, const char *path)\n{\n\tint fd;\n\n\t/* everything else is checked in cmdline_new() */\n\tif (!path)\n\t\treturn NULL;\n\n\tfd = open(path, O_RDONLY, 0);\n\tif (fd < 0) {\n\t\tdprintf(\"open() failed\\n\");\n\t\treturn NULL;\n\t}\n\treturn cmdline_new(ctx, prompt, fd, -1);\n}\n\nstruct cmdline *\ncmdline_stdin_new(cmdline_parse_ctx_t *ctx, const char *prompt)\n{\n\tstruct cmdline *cl;\n\tstruct termios oldterm, term;\n\n\ttcgetattr(0, &oldterm);\n\tmemcpy(&term, &oldterm, sizeof(term));\n\tterm.c_lflag &= ~(ICANON | ECHO | ISIG);\n\ttcsetattr(0, TCSANOW, &term);\n\tsetbuf(stdin, NULL);\n\n\tcl = cmdline_new(ctx, prompt, 0, 1);\n\n\tif (cl)\n\t\tmemcpy(&cl->oldterm, &oldterm, sizeof(term));\n\n\treturn cl;\n}\n\nvoid\ncmdline_stdin_exit(struct cmdline *cl)\n{\n\tif (!cl)\n\t\treturn;\n\n\ttcsetattr(fileno(stdin), TCSANOW, &cl->oldterm);\n}\n" }, { "path": "lib/librte_cmdline/cmdline_socket.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _CMDLINE_SOCKET_H_\n#define _CMDLINE_SOCKET_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct cmdline *cmdline_file_new(cmdline_parse_ctx_t *ctx, const char *prompt, const char *path);\nstruct cmdline *cmdline_stdin_new(cmdline_parse_ctx_t *ctx, const char *prompt);\nvoid cmdline_stdin_exit(struct cmdline *cl);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _CMDLINE_SOCKET_H_ */\n" }, { "path": "lib/librte_cmdline/cmdline_vt100.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"cmdline_vt100.h\"\n\nconst char *cmdline_vt100_commands[] = {\n\tvt100_up_arr,\n\tvt100_down_arr,\n\tvt100_right_arr,\n\tvt100_left_arr,\n\t\"\\177\",\n\t\"\\n\",\n\t\"\\001\",\n\t\"\\005\",\n\t\"\\013\",\n\t\"\\031\",\n\t\"\\003\",\n\t\"\\006\",\n\t\"\\002\",\n\tvt100_suppr,\n\tvt100_tab,\n\t\"\\004\",\n\t\"\\014\",\n\t\"\\r\",\n\t\"\\033\\177\",\n\tvt100_word_left,\n\tvt100_word_right,\n\t\"?\",\n\t\"\\027\",\n\t\"\\020\",\n\t\"\\016\",\n\t\"\\033\\144\",\n};\n\nvoid\nvt100_init(struct cmdline_vt100 *vt)\n{\n\tif (!vt)\n\t\treturn;\n\tvt->state = CMDLINE_VT100_INIT;\n}\n\n\nstatic int\nmatch_command(char *buf, unsigned int size)\n{\n\tconst char *cmd;\n\tsize_t cmdlen;\n\tunsigned int i = 0;\n\n\tfor (i=0 ; ibufpos >= CMDLINE_VT100_BUF_SIZE) {\n\t\tvt->state = CMDLINE_VT100_INIT;\n\t\tvt->bufpos = 0;\n\t}\n\n\tvt->buf[vt->bufpos++] = c;\n\tsize = vt->bufpos;\n\n\tswitch (vt->state) {\n\tcase CMDLINE_VT100_INIT:\n\t\tif (c == 033) {\n\t\t\tvt->state = CMDLINE_VT100_ESCAPE;\n\t\t}\n\t\telse {\n\t\t\tvt->bufpos = 0;\n\t\t\tgoto match_command;\n\t\t}\n\t\tbreak;\n\n\tcase CMDLINE_VT100_ESCAPE:\n\t\tif (c == 0133) {\n\t\t\tvt->state = CMDLINE_VT100_ESCAPE_CSI;\n\t\t}\n\t\telse if (c >= 060 && c <= 0177) { /* XXX 0177 ? */\n\t\t\tvt->bufpos = 0;\n\t\t\tvt->state = CMDLINE_VT100_INIT;\n\t\t\tgoto match_command;\n\t\t}\n\t\tbreak;\n\n\tcase CMDLINE_VT100_ESCAPE_CSI:\n\t\tif (c >= 0100 && c <= 0176) {\n\t\t\tvt->bufpos = 0;\n\t\t\tvt->state = CMDLINE_VT100_INIT;\n\t\t\tgoto match_command;\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tvt->bufpos = 0;\n\t\tbreak;\n\t}\n\n\treturn -2;\n\n match_command:\n\treturn match_command(vt->buf, size);\n}\n" }, { "path": "lib/librte_cmdline/cmdline_vt100.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 2009, Olivier MATZ \n * All rights reserved.\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * * Neither the name of the University of California, Berkeley nor the\n * names of its contributors may be used to endorse or promote products\n * derived from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY\n * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY\n * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND\n * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _CMDLINE_VT100_H_\n#define _CMDLINE_VT100_H_\n\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define vt100_bell \"\\007\"\n#define vt100_bs \"\\010\"\n#define vt100_bs_clear \"\\010 \\010\"\n#define vt100_tab \"\\011\"\n#define vt100_crnl \"\\012\\015\"\n#define vt100_clear_right \"\\033[0K\"\n#define vt100_clear_left \"\\033[1K\"\n#define vt100_clear_down \"\\033[0J\"\n#define vt100_clear_up \"\\033[1J\"\n#define vt100_clear_line \"\\033[2K\"\n#define vt100_clear_screen \"\\033[2J\"\n#define vt100_up_arr \"\\033\\133\\101\"\n#define vt100_down_arr \"\\033\\133\\102\"\n#define vt100_right_arr \"\\033\\133\\103\"\n#define vt100_left_arr \"\\033\\133\\104\"\n#define vt100_multi_right \"\\033\\133%uC\"\n#define vt100_multi_left \"\\033\\133%uD\"\n#define vt100_suppr \"\\033\\133\\063\\176\"\n#define vt100_home \"\\033M\\033E\"\n#define vt100_word_left \"\\033\\142\"\n#define vt100_word_right \"\\033\\146\"\n\n/* Result of parsing : it must be synchronized with\n * cmdline_vt100_commands[] in vt100.c */\n#define CMDLINE_KEY_UP_ARR 0\n#define CMDLINE_KEY_DOWN_ARR 1\n#define CMDLINE_KEY_RIGHT_ARR 2\n#define CMDLINE_KEY_LEFT_ARR 3\n#define CMDLINE_KEY_BKSPACE 4\n#define CMDLINE_KEY_RETURN 5\n#define CMDLINE_KEY_CTRL_A 6\n#define CMDLINE_KEY_CTRL_E 7\n#define CMDLINE_KEY_CTRL_K 8\n#define CMDLINE_KEY_CTRL_Y 9\n#define CMDLINE_KEY_CTRL_C 10\n#define CMDLINE_KEY_CTRL_F 11\n#define CMDLINE_KEY_CTRL_B 12\n#define CMDLINE_KEY_SUPPR 13\n#define CMDLINE_KEY_TAB 14\n#define CMDLINE_KEY_CTRL_D 15\n#define CMDLINE_KEY_CTRL_L 16\n#define CMDLINE_KEY_RETURN2 17\n#define CMDLINE_KEY_META_BKSPACE 18\n#define CMDLINE_KEY_WLEFT 19\n#define CMDLINE_KEY_WRIGHT 20\n#define CMDLINE_KEY_HELP 21\n#define CMDLINE_KEY_CTRL_W 22\n#define CMDLINE_KEY_CTRL_P 23\n#define CMDLINE_KEY_CTRL_N 24\n#define CMDLINE_KEY_META_D 25\n\nextern const char *cmdline_vt100_commands[];\n\nenum cmdline_vt100_parser_state {\n\tCMDLINE_VT100_INIT,\n\tCMDLINE_VT100_ESCAPE,\n\tCMDLINE_VT100_ESCAPE_CSI\n};\n\n#define CMDLINE_VT100_BUF_SIZE 8\nstruct cmdline_vt100 {\n\tuint8_t bufpos;\n\tchar buf[CMDLINE_VT100_BUF_SIZE];\n\tenum cmdline_vt100_parser_state state;\n};\n\n/**\n * Init\n */\nvoid vt100_init(struct cmdline_vt100 *vt);\n\n/**\n * Input a new character.\n * Return -1 if the character is not part of a control sequence\n * Return -2 if c is not the last char of a control sequence\n * Else return the index in vt100_commands[]\n */\nint vt100_parser(struct cmdline_vt100 *vt, char c);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_compat/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2013 Neil Horman \n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n\nLIBABIVER := 1\n\n# install includes\nSYMLINK-y-include := rte_compat.h\n\ninclude $(RTE_SDK)/mk/rte.install.mk\n" }, { "path": "lib/librte_compat/rte_compat.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 Neil Horman .\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_COMPAT_H_\n#define _RTE_COMPAT_H_\n#include \n\n#ifdef RTE_BUILD_SHARED_LIB\n\n/*\n * Provides backwards compatibility when updating exported functions.\n * When a symol is exported from a library to provide an API, it also provides a\n * calling convention (ABI) that is embodied in its name, return type,\n * arguments, etc. On occasion that function may need to change to accommodate\n * new functionality, behavior, etc. When that occurs, it is desireable to\n * allow for backwards compatibility for a time with older binaries that are\n * dynamically linked to the dpdk. To support that, the __vsym and\n * VERSION_SYMBOL macros are created. They, in conjunction with the\n * _version.map file for a given library allow for multiple versions of\n * a symbol to exist in a shared library so that older binaries need not be\n * immediately recompiled.\n *\n * Refer to the guidelines document in the docs subdirectory for details on the\n * use of these macros\n */\n\n/*\n * Macro Parameters:\n * b - function base name\n * e - function version extension, to be concatenated with base name\n * n - function symbol version string to be applied\n * f - function prototype\n * p - full function symbol name\n */\n\n/*\n * VERSION_SYMBOL\n * Creates a symbol version table entry binding symbol @DPDK_ to the internal\n * function name _\n */\n#define VERSION_SYMBOL(b, e, n) __asm__(\".symver \" RTE_STR(b) RTE_STR(e) \", \" RTE_STR(b) \"@DPDK_\" RTE_STR(n))\n\n/*\n * BIND_DEFAULT_SYMBOL\n * Creates a symbol version entry instructing the linker to bind references to\n * symbol to the internal symbol _\n */\n#define BIND_DEFAULT_SYMBOL(b, e, n) __asm__(\".symver \" RTE_STR(b) RTE_STR(e) \", \" RTE_STR(b) \"@@DPDK_\" RTE_STR(n))\n#define __vsym __attribute__((used))\n\n/*\n * MAP_STATIC_SYMBOL\n * If a function has been bifurcated into multiple versions, none of which\n * are defined as the exported symbol name in the map file, this macro can be\n * used to alias a specific version of the symbol to its exported name. For\n * example, if you have 2 versions of a function foo_v1 and foo_v2, where the\n * former is mapped to foo@DPDK_1 and the latter is mapped to foo@DPDK_2 when\n * building a shared library, this macro can be used to map either foo_v1 or\n * foo_v2 to the symbol foo when building a static library, e.g.:\n * MAP_STATIC_SYMBOL(void foo(), foo_v2);\n */\n#define MAP_STATIC_SYMBOL(f, p)\n\n#else\n/*\n * No symbol versioning in use\n */\n#define VERSION_SYMBOL(b, e, n)\n#define __vsym\n#define BIND_DEFAULT_SYMBOL(b, e, n)\n#define MAP_STATIC_SYMBOL(f, p) f __attribute__((alias(RTE_STR(p))))\n/*\n * RTE_BUILD_SHARED_LIB=n\n */\n#endif\n\n\n#endif /* _RTE_COMPAT_H_ */\n" }, { "path": "lib/librte_distributor/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_distributor.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR)\n\nEXPORT_MAP := rte_distributor_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) := rte_distributor.c\n\n# install this header file\nSYMLINK-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR)-include := rte_distributor.h\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) += lib/librte_eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) += lib/librte_mbuf\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_distributor/rte_distributor.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \"rte_distributor.h\"\n\n#define NO_FLAGS 0\n#define RTE_DISTRIB_PREFIX \"DT_\"\n\n/* we will use the bottom four bits of pointer for flags, shifting out\n * the top four bits to make room (since a 64-bit pointer actually only uses\n * 48 bits). An arithmetic-right-shift will then appropriately restore the\n * original pointer value with proper sign extension into the top bits. */\n#define RTE_DISTRIB_FLAG_BITS 4\n#define RTE_DISTRIB_FLAGS_MASK (0x0F)\n#define RTE_DISTRIB_NO_BUF 0 /**< empty flags: no buffer requested */\n#define RTE_DISTRIB_GET_BUF (1) /**< worker requests a buffer, returns old */\n#define RTE_DISTRIB_RETURN_BUF (2) /**< worker returns a buffer, no request */\n\n#define RTE_DISTRIB_BACKLOG_SIZE 8\n#define RTE_DISTRIB_BACKLOG_MASK (RTE_DISTRIB_BACKLOG_SIZE - 1)\n\n#define RTE_DISTRIB_MAX_RETURNS 128\n#define RTE_DISTRIB_RETURNS_MASK (RTE_DISTRIB_MAX_RETURNS - 1)\n\n/**\n * Maximum number of workers allowed.\n * Be aware of increasing the limit, becaus it is limited by how we track\n * in-flight tags. See @in_flight_bitmask and @rte_distributor_process\n */\n#define RTE_DISTRIB_MAX_WORKERS\t64\n\n/**\n * Buffer structure used to pass the pointer data between cores. This is cache\n * line aligned, but to improve performance and prevent adjacent cache-line\n * prefetches of buffers for other workers, e.g. when worker 1's buffer is on\n * the next cache line to worker 0, we pad this out to three cache lines.\n * Only 64-bits of the memory is actually used though.\n */\nunion rte_distributor_buffer {\n\tvolatile int64_t bufptr64;\n\tchar pad[RTE_CACHE_LINE_SIZE*3];\n} __rte_cache_aligned;\n\nstruct rte_distributor_backlog {\n\tunsigned start;\n\tunsigned count;\n\tint64_t pkts[RTE_DISTRIB_BACKLOG_SIZE];\n};\n\nstruct rte_distributor_returned_pkts {\n\tunsigned start;\n\tunsigned count;\n\tstruct rte_mbuf *mbufs[RTE_DISTRIB_MAX_RETURNS];\n};\n\nstruct rte_distributor {\n\tTAILQ_ENTRY(rte_distributor) next; /**< Next in list. */\n\n\tchar name[RTE_DISTRIBUTOR_NAMESIZE]; /**< Name of the ring. */\n\tunsigned num_workers; /**< Number of workers polling */\n\n\tuint32_t in_flight_tags[RTE_DISTRIB_MAX_WORKERS];\n\t\t/**< Tracks the tag being processed per core */\n\tuint64_t in_flight_bitmask;\n\t\t/**< on/off bits for in-flight tags.\n\t\t * Note that if RTE_DISTRIB_MAX_WORKERS is larger than 64 then\n\t\t * the bitmask has to expand.\n\t\t */\n\n\tstruct rte_distributor_backlog backlog[RTE_DISTRIB_MAX_WORKERS];\n\n\tunion rte_distributor_buffer bufs[RTE_DISTRIB_MAX_WORKERS];\n\n\tstruct rte_distributor_returned_pkts returns;\n};\n\nTAILQ_HEAD(rte_distributor_list, rte_distributor);\n\nstatic struct rte_tailq_elem rte_distributor_tailq = {\n\t.name = \"RTE_DISTRIBUTOR\",\n};\nEAL_REGISTER_TAILQ(rte_distributor_tailq)\n\n/**** APIs called by workers ****/\n\nvoid\nrte_distributor_request_pkt(struct rte_distributor *d,\n\t\tunsigned worker_id, struct rte_mbuf *oldpkt)\n{\n\tunion rte_distributor_buffer *buf = &d->bufs[worker_id];\n\tint64_t req = (((int64_t)(uintptr_t)oldpkt) << RTE_DISTRIB_FLAG_BITS)\n\t\t\t| RTE_DISTRIB_GET_BUF;\n\twhile (unlikely(buf->bufptr64 & RTE_DISTRIB_FLAGS_MASK))\n\t\trte_pause();\n\tbuf->bufptr64 = req;\n}\n\nstruct rte_mbuf *\nrte_distributor_poll_pkt(struct rte_distributor *d,\n\t\tunsigned worker_id)\n{\n\tunion rte_distributor_buffer *buf = &d->bufs[worker_id];\n\tif (buf->bufptr64 & RTE_DISTRIB_GET_BUF)\n\t\treturn NULL;\n\n\t/* since bufptr64 is signed, this should be an arithmetic shift */\n\tint64_t ret = buf->bufptr64 >> RTE_DISTRIB_FLAG_BITS;\n\treturn (struct rte_mbuf *)((uintptr_t)ret);\n}\n\nstruct rte_mbuf *\nrte_distributor_get_pkt(struct rte_distributor *d,\n\t\tunsigned worker_id, struct rte_mbuf *oldpkt)\n{\n\tstruct rte_mbuf *ret;\n\trte_distributor_request_pkt(d, worker_id, oldpkt);\n\twhile ((ret = rte_distributor_poll_pkt(d, worker_id)) == NULL)\n\t\trte_pause();\n\treturn ret;\n}\n\nint\nrte_distributor_return_pkt(struct rte_distributor *d,\n\t\tunsigned worker_id, struct rte_mbuf *oldpkt)\n{\n\tunion rte_distributor_buffer *buf = &d->bufs[worker_id];\n\tuint64_t req = (((int64_t)(uintptr_t)oldpkt) << RTE_DISTRIB_FLAG_BITS)\n\t\t\t| RTE_DISTRIB_RETURN_BUF;\n\tbuf->bufptr64 = req;\n\treturn 0;\n}\n\n/**** APIs called on distributor core ***/\n\n/* as name suggests, adds a packet to the backlog for a particular worker */\nstatic int\nadd_to_backlog(struct rte_distributor_backlog *bl, int64_t item)\n{\n\tif (bl->count == RTE_DISTRIB_BACKLOG_SIZE)\n\t\treturn -1;\n\n\tbl->pkts[(bl->start + bl->count++) & (RTE_DISTRIB_BACKLOG_MASK)]\n\t\t\t= item;\n\treturn 0;\n}\n\n/* takes the next packet for a worker off the backlog */\nstatic int64_t\nbacklog_pop(struct rte_distributor_backlog *bl)\n{\n\tbl->count--;\n\treturn bl->pkts[bl->start++ & RTE_DISTRIB_BACKLOG_MASK];\n}\n\n/* stores a packet returned from a worker inside the returns array */\nstatic inline void\nstore_return(uintptr_t oldbuf, struct rte_distributor *d,\n\t\tunsigned *ret_start, unsigned *ret_count)\n{\n\t/* store returns in a circular buffer - code is branch-free */\n\td->returns.mbufs[(*ret_start + *ret_count) & RTE_DISTRIB_RETURNS_MASK]\n\t\t\t= (void *)oldbuf;\n\t*ret_start += (*ret_count == RTE_DISTRIB_RETURNS_MASK) & !!(oldbuf);\n\t*ret_count += (*ret_count != RTE_DISTRIB_RETURNS_MASK) & !!(oldbuf);\n}\n\nstatic inline void\nhandle_worker_shutdown(struct rte_distributor *d, unsigned wkr)\n{\n\td->in_flight_tags[wkr] = 0;\n\td->in_flight_bitmask &= ~(1UL << wkr);\n\td->bufs[wkr].bufptr64 = 0;\n\tif (unlikely(d->backlog[wkr].count != 0)) {\n\t\t/* On return of a packet, we need to move the\n\t\t * queued packets for this core elsewhere.\n\t\t * Easiest solution is to set things up for\n\t\t * a recursive call. That will cause those\n\t\t * packets to be queued up for the next free\n\t\t * core, i.e. it will return as soon as a\n\t\t * core becomes free to accept the first\n\t\t * packet, as subsequent ones will be added to\n\t\t * the backlog for that core.\n\t\t */\n\t\tstruct rte_mbuf *pkts[RTE_DISTRIB_BACKLOG_SIZE];\n\t\tunsigned i;\n\t\tstruct rte_distributor_backlog *bl = &d->backlog[wkr];\n\n\t\tfor (i = 0; i < bl->count; i++) {\n\t\t\tunsigned idx = (bl->start + i) &\n\t\t\t\t\tRTE_DISTRIB_BACKLOG_MASK;\n\t\t\tpkts[i] = (void *)((uintptr_t)(bl->pkts[idx] >>\n\t\t\t\t\tRTE_DISTRIB_FLAG_BITS));\n\t\t}\n\t\t/* recursive call.\n\t\t * Note that the tags were set before first level call\n\t\t * to rte_distributor_process.\n\t\t */\n\t\trte_distributor_process(d, pkts, i);\n\t\tbl->count = bl->start = 0;\n\t}\n}\n\n/* this function is called when process() fn is called without any new\n * packets. It goes through all the workers and clears any returned packets\n * to do a partial flush.\n */\nstatic int\nprocess_returns(struct rte_distributor *d)\n{\n\tunsigned wkr;\n\tunsigned flushed = 0;\n\tunsigned ret_start = d->returns.start,\n\t\t\tret_count = d->returns.count;\n\n\tfor (wkr = 0; wkr < d->num_workers; wkr++) {\n\n\t\tconst int64_t data = d->bufs[wkr].bufptr64;\n\t\tuintptr_t oldbuf = 0;\n\n\t\tif (data & RTE_DISTRIB_GET_BUF) {\n\t\t\tflushed++;\n\t\t\tif (d->backlog[wkr].count)\n\t\t\t\td->bufs[wkr].bufptr64 =\n\t\t\t\t\t\tbacklog_pop(&d->backlog[wkr]);\n\t\t\telse {\n\t\t\t\td->bufs[wkr].bufptr64 = RTE_DISTRIB_GET_BUF;\n\t\t\t\td->in_flight_tags[wkr] = 0;\n\t\t\t\td->in_flight_bitmask &= ~(1UL << wkr);\n\t\t\t}\n\t\t\toldbuf = data >> RTE_DISTRIB_FLAG_BITS;\n\t\t} else if (data & RTE_DISTRIB_RETURN_BUF) {\n\t\t\thandle_worker_shutdown(d, wkr);\n\t\t\toldbuf = data >> RTE_DISTRIB_FLAG_BITS;\n\t\t}\n\n\t\tstore_return(oldbuf, d, &ret_start, &ret_count);\n\t}\n\n\td->returns.start = ret_start;\n\td->returns.count = ret_count;\n\n\treturn flushed;\n}\n\n/* process a set of packets to distribute them to workers */\nint\nrte_distributor_process(struct rte_distributor *d,\n\t\tstruct rte_mbuf **mbufs, unsigned num_mbufs)\n{\n\tunsigned next_idx = 0;\n\tunsigned wkr = 0;\n\tstruct rte_mbuf *next_mb = NULL;\n\tint64_t next_value = 0;\n\tuint32_t new_tag = 0;\n\tunsigned ret_start = d->returns.start,\n\t\t\tret_count = d->returns.count;\n\n\tif (unlikely(num_mbufs == 0))\n\t\treturn process_returns(d);\n\n\twhile (next_idx < num_mbufs || next_mb != NULL) {\n\n\t\tint64_t data = d->bufs[wkr].bufptr64;\n\t\tuintptr_t oldbuf = 0;\n\n\t\tif (!next_mb) {\n\t\t\tnext_mb = mbufs[next_idx++];\n\t\t\tnext_value = (((int64_t)(uintptr_t)next_mb)\n\t\t\t\t\t<< RTE_DISTRIB_FLAG_BITS);\n\t\t\t/*\n\t\t\t * User is advocated to set tag vaue for each\n\t\t\t * mbuf before calling rte_distributor_process.\n\t\t\t * User defined tags are used to identify flows,\n\t\t\t * or sessions.\n\t\t\t */\n\t\t\tnew_tag = next_mb->hash.usr;\n\n\t\t\t/*\n\t\t\t * Note that if RTE_DISTRIB_MAX_WORKERS is larger than 64\n\t\t\t * then the size of match has to be expanded.\n\t\t\t */\n\t\t\tuint64_t match = 0;\n\t\t\tunsigned i;\n\t\t\t/*\n\t\t\t * to scan for a match use \"xor\" and \"not\" to get a 0/1\n\t\t\t * value, then use shifting to merge to single \"match\"\n\t\t\t * variable, where a one-bit indicates a match for the\n\t\t\t * worker given by the bit-position\n\t\t\t */\n\t\t\tfor (i = 0; i < d->num_workers; i++)\n\t\t\t\tmatch |= (!(d->in_flight_tags[i] ^ new_tag)\n\t\t\t\t\t<< i);\n\n\t\t\t/* Only turned-on bits are considered as match */\n\t\t\tmatch &= d->in_flight_bitmask;\n\n\t\t\tif (match) {\n\t\t\t\tnext_mb = NULL;\n\t\t\t\tunsigned worker = __builtin_ctzl(match);\n\t\t\t\tif (add_to_backlog(&d->backlog[worker],\n\t\t\t\t\t\tnext_value) < 0)\n\t\t\t\t\tnext_idx--;\n\t\t\t}\n\t\t}\n\n\t\tif ((data & RTE_DISTRIB_GET_BUF) &&\n\t\t\t\t(d->backlog[wkr].count || next_mb)) {\n\n\t\t\tif (d->backlog[wkr].count)\n\t\t\t\td->bufs[wkr].bufptr64 =\n\t\t\t\t\t\tbacklog_pop(&d->backlog[wkr]);\n\n\t\t\telse {\n\t\t\t\td->bufs[wkr].bufptr64 = next_value;\n\t\t\t\td->in_flight_tags[wkr] = new_tag;\n\t\t\t\td->in_flight_bitmask |= (1UL << wkr);\n\t\t\t\tnext_mb = NULL;\n\t\t\t}\n\t\t\toldbuf = data >> RTE_DISTRIB_FLAG_BITS;\n\t\t} else if (data & RTE_DISTRIB_RETURN_BUF) {\n\t\t\thandle_worker_shutdown(d, wkr);\n\t\t\toldbuf = data >> RTE_DISTRIB_FLAG_BITS;\n\t\t}\n\n\t\t/* store returns in a circular buffer */\n\t\tstore_return(oldbuf, d, &ret_start, &ret_count);\n\n\t\tif (++wkr == d->num_workers)\n\t\t\twkr = 0;\n\t}\n\t/* to finish, check all workers for backlog and schedule work for them\n\t * if they are ready */\n\tfor (wkr = 0; wkr < d->num_workers; wkr++)\n\t\tif (d->backlog[wkr].count &&\n\t\t\t\t(d->bufs[wkr].bufptr64 & RTE_DISTRIB_GET_BUF)) {\n\n\t\t\tint64_t oldbuf = d->bufs[wkr].bufptr64 >>\n\t\t\t\t\tRTE_DISTRIB_FLAG_BITS;\n\t\t\tstore_return(oldbuf, d, &ret_start, &ret_count);\n\n\t\t\td->bufs[wkr].bufptr64 = backlog_pop(&d->backlog[wkr]);\n\t\t}\n\n\td->returns.start = ret_start;\n\td->returns.count = ret_count;\n\treturn num_mbufs;\n}\n\n/* return to the caller, packets returned from workers */\nint\nrte_distributor_returned_pkts(struct rte_distributor *d,\n\t\tstruct rte_mbuf **mbufs, unsigned max_mbufs)\n{\n\tstruct rte_distributor_returned_pkts *returns = &d->returns;\n\tunsigned retval = (max_mbufs < returns->count) ?\n\t\t\tmax_mbufs : returns->count;\n\tunsigned i;\n\n\tfor (i = 0; i < retval; i++) {\n\t\tunsigned idx = (returns->start + i) & RTE_DISTRIB_RETURNS_MASK;\n\t\tmbufs[i] = returns->mbufs[idx];\n\t}\n\treturns->start += i;\n\treturns->count -= i;\n\n\treturn retval;\n}\n\n/* return the number of packets in-flight in a distributor, i.e. packets\n * being workered on or queued up in a backlog. */\nstatic inline unsigned\ntotal_outstanding(const struct rte_distributor *d)\n{\n\tunsigned wkr, total_outstanding;\n\n\ttotal_outstanding = __builtin_popcountl(d->in_flight_bitmask);\n\n\tfor (wkr = 0; wkr < d->num_workers; wkr++)\n\t\ttotal_outstanding += d->backlog[wkr].count;\n\n\treturn total_outstanding;\n}\n\n/* flush the distributor, so that there are no outstanding packets in flight or\n * queued up. */\nint\nrte_distributor_flush(struct rte_distributor *d)\n{\n\tconst unsigned flushed = total_outstanding(d);\n\n\twhile (total_outstanding(d) > 0)\n\t\trte_distributor_process(d, NULL, 0);\n\n\treturn flushed;\n}\n\n/* clears the internal returns array in the distributor */\nvoid\nrte_distributor_clear_returns(struct rte_distributor *d)\n{\n\td->returns.start = d->returns.count = 0;\n#ifndef __OPTIMIZE__\n\tmemset(d->returns.mbufs, 0, sizeof(d->returns.mbufs));\n#endif\n}\n\n/* creates a distributor instance */\nstruct rte_distributor *\nrte_distributor_create(const char *name,\n\t\tunsigned socket_id,\n\t\tunsigned num_workers)\n{\n\tstruct rte_distributor *d;\n\tstruct rte_distributor_list *distributor_list;\n\tchar mz_name[RTE_MEMZONE_NAMESIZE];\n\tconst struct rte_memzone *mz;\n\n\t/* compilation-time checks */\n\tRTE_BUILD_BUG_ON((sizeof(*d) & RTE_CACHE_LINE_MASK) != 0);\n\tRTE_BUILD_BUG_ON((RTE_DISTRIB_MAX_WORKERS & 7) != 0);\n\tRTE_BUILD_BUG_ON(RTE_DISTRIB_MAX_WORKERS >\n\t\t\t\tsizeof(d->in_flight_bitmask) * CHAR_BIT);\n\n\tif (name == NULL || num_workers >= RTE_DISTRIB_MAX_WORKERS) {\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\tsnprintf(mz_name, sizeof(mz_name), RTE_DISTRIB_PREFIX\"%s\", name);\n\tmz = rte_memzone_reserve(mz_name, sizeof(*d), socket_id, NO_FLAGS);\n\tif (mz == NULL) {\n\t\trte_errno = ENOMEM;\n\t\treturn NULL;\n\t}\n\n\td = mz->addr;\n\tsnprintf(d->name, sizeof(d->name), \"%s\", name);\n\td->num_workers = num_workers;\n\n\tdistributor_list = RTE_TAILQ_CAST(rte_distributor_tailq.head,\n\t\t\t\t\t rte_distributor_list);\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\tTAILQ_INSERT_TAIL(distributor_list, d, next);\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\treturn d;\n}\n" }, { "path": "lib/librte_distributor/rte_distributor.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_DISTRIBUTE_H_\n#define _RTE_DISTRIBUTE_H_\n\n/**\n * @file\n * RTE distributor\n *\n * The distributor is a component which is designed to pass packets\n * one-at-a-time to workers, with dynamic load balancing.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define RTE_DISTRIBUTOR_NAMESIZE 32 /**< Length of name for instance */\n\nstruct rte_distributor;\nstruct rte_mbuf;\n\n/**\n * Function to create a new distributor instance\n *\n * Reserves the memory needed for the distributor operation and\n * initializes the distributor to work with the configured number of workers.\n *\n * @param name\n * The name to be given to the distributor instance.\n * @param socket_id\n * The NUMA node on which the memory is to be allocated\n * @param num_workers\n * The maximum number of workers that will request packets from this\n * distributor\n * @return\n * The newly created distributor instance\n */\nstruct rte_distributor *\nrte_distributor_create(const char *name, unsigned socket_id,\n\t\tunsigned num_workers);\n\n/* *** APIS to be called on the distributor lcore *** */\n/*\n * The following APIs are the public APIs which are designed for use on a\n * single lcore which acts as the distributor lcore for a given distributor\n * instance. These functions cannot be called on multiple cores simultaneously\n * without using locking to protect access to the internals of the distributor.\n *\n * NOTE: a given lcore cannot act as both a distributor lcore and a worker lcore\n * for the same distributor instance, otherwise deadlock will result.\n */\n\n/**\n * Process a set of packets by distributing them among workers that request\n * packets. The distributor will ensure that no two packets that have the\n * same flow id, or tag, in the mbuf will be procesed at the same time.\n *\n * The user is advocated to set tag for each mbuf before calling this function.\n * If user doesn't set the tag, the tag value can be various values depending on\n * driver implementation and configuration.\n *\n * This is not multi-thread safe and should only be called on a single lcore.\n *\n * @param d\n * The distributor instance to be used\n * @param mbufs\n * The mbufs to be distributed\n * @param num_mbufs\n * The number of mbufs in the mbufs array\n * @return\n * The number of mbufs processed.\n */\nint\nrte_distributor_process(struct rte_distributor *d,\n\t\tstruct rte_mbuf **mbufs, unsigned num_mbufs);\n\n/**\n * Get a set of mbufs that have been returned to the distributor by workers\n *\n * This should only be called on the same lcore as rte_distributor_process()\n *\n * @param d\n * The distributor instance to be used\n * @param mbufs\n * The mbufs pointer array to be filled in\n * @param max_mbufs\n * The size of the mbufs array\n * @return\n * The number of mbufs returned in the mbufs array.\n */\nint\nrte_distributor_returned_pkts(struct rte_distributor *d,\n\t\tstruct rte_mbuf **mbufs, unsigned max_mbufs);\n\n/**\n * Flush the distributor component, so that there are no in-flight or\n * backlogged packets awaiting processing\n *\n * This should only be called on the same lcore as rte_distributor_process()\n *\n * @param d\n * The distributor instance to be used\n * @return\n * The number of queued/in-flight packets that were completed by this call.\n */\nint\nrte_distributor_flush(struct rte_distributor *d);\n\n/**\n * Clears the array of returned packets used as the source for the\n * rte_distributor_returned_pkts() API call.\n *\n * This should only be called on the same lcore as rte_distributor_process()\n *\n * @param d\n * The distributor instance to be used\n */\nvoid\nrte_distributor_clear_returns(struct rte_distributor *d);\n\n/* *** APIS to be called on the worker lcores *** */\n/*\n * The following APIs are the public APIs which are designed for use on\n * multiple lcores which act as workers for a distributor. Each lcore should use\n * a unique worker id when requesting packets.\n *\n * NOTE: a given lcore cannot act as both a distributor lcore and a worker lcore\n * for the same distributor instance, otherwise deadlock will result.\n */\n\n/**\n * API called by a worker to get a new packet to process. Any previous packet\n * given to the worker is assumed to have completed processing, and may be\n * optionally returned to the distributor via the oldpkt parameter.\n *\n * @param d\n * The distributor instance to be used\n * @param worker_id\n * The worker instance number to use - must be less that num_workers passed\n * at distributor creation time.\n * @param oldpkt\n * The previous packet, if any, being processed by the worker\n *\n * @return\n * A new packet to be processed by the worker thread.\n */\nstruct rte_mbuf *\nrte_distributor_get_pkt(struct rte_distributor *d,\n\t\tunsigned worker_id, struct rte_mbuf *oldpkt);\n\n/**\n * API called by a worker to return a completed packet without requesting a\n * new packet, for example, because a worker thread is shutting down\n *\n * @param d\n * The distributor instance to be used\n * @param worker_id\n * The worker instance number to use - must be less that num_workers passed\n * at distributor creation time.\n * @param mbuf\n * The previous packet being processed by the worker\n */\nint\nrte_distributor_return_pkt(struct rte_distributor *d, unsigned worker_id,\n\t\tstruct rte_mbuf *mbuf);\n\n/**\n * API called by a worker to request a new packet to process.\n * Any previous packet given to the worker is assumed to have completed\n * processing, and may be optionally returned to the distributor via\n * the oldpkt parameter.\n * Unlike rte_distributor_get_pkt(), this function does not wait for a new\n * packet to be provided by the distributor.\n *\n * NOTE: after calling this function, rte_distributor_poll_pkt() should\n * be used to poll for the packet requested. The rte_distributor_get_pkt()\n * API should *not* be used to try and retrieve the new packet.\n *\n * @param d\n * The distributor instance to be used\n * @param worker_id\n * The worker instance number to use - must be less that num_workers passed\n * at distributor creation time.\n * @param oldpkt\n * The previous packet, if any, being processed by the worker\n */\nvoid\nrte_distributor_request_pkt(struct rte_distributor *d,\n\t\tunsigned worker_id, struct rte_mbuf *oldpkt);\n\n/**\n * API called by a worker to check for a new packet that was previously\n * requested by a call to rte_distributor_request_pkt(). It does not wait\n * for the new packet to be available, but returns NULL if the request has\n * not yet been fulfilled by the distributor.\n *\n * @param d\n * The distributor instance to be used\n * @param worker_id\n * The worker instance number to use - must be less that num_workers passed\n * at distributor creation time.\n *\n * @return\n * A new packet to be processed by the worker thread, or NULL if no\n * packet is yet available.\n */\nstruct rte_mbuf *\nrte_distributor_poll_pkt(struct rte_distributor *d,\n\t\tunsigned worker_id);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_eal/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nDIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += common\nDIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += linuxapp\nDIRS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += common\nDIRS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += bsdapp\n\ninclude $(RTE_SDK)/mk/rte.subdir.mk\n" }, { "path": "lib/librte_eal/bsdapp/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nDIRS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal\nDIRS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += contigmem\nDIRS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += nic_uio\n\ninclude $(RTE_SDK)/mk/rte.subdir.mk\n" }, { "path": "lib/librte_eal/bsdapp/contigmem/BSDmakefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\nKMOD=\tcontigmem\nSRCS=\tcontigmem.c device_if.h bus_if.h\n\n.include \n" }, { "path": "lib/librte_eal/bsdapp/contigmem/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# module name and path\n#\nMODULE = contigmem\n\n#\n# CFLAGS\n#\nMODULE_CFLAGS += -I$(SRCDIR)\nMODULE_CFLAGS += -I$(RTE_OUTPUT)/include\nMODULE_CFLAGS += -Winline -Wall -Werror\nMODULE_CFLAGS += -include $(RTE_OUTPUT)/include/rte_config.h\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-y := contigmem.c\n\ninclude $(RTE_SDK)/mk/rte.bsdmodule.mk\n" }, { "path": "lib/librte_eal/bsdapp/contigmem/contigmem.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n__FBSDID(\"$FreeBSD$\");\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \n#include \n#include \n#include \n#include \n\nstatic int contigmem_load(void);\nstatic int contigmem_unload(void);\nstatic int contigmem_physaddr(SYSCTL_HANDLER_ARGS);\n\nstatic d_mmap_t contigmem_mmap;\nstatic d_mmap_single_t contigmem_mmap_single;\nstatic d_open_t contigmem_open;\n\nstatic int contigmem_num_buffers = RTE_CONTIGMEM_DEFAULT_NUM_BUFS;\nstatic int64_t contigmem_buffer_size = RTE_CONTIGMEM_DEFAULT_BUF_SIZE;\n\nstatic eventhandler_tag contigmem_eh_tag;\nstatic void *contigmem_buffers[RTE_CONTIGMEM_MAX_NUM_BUFS];\nstatic struct cdev *contigmem_cdev = NULL;\n\nTUNABLE_INT(\"hw.contigmem.num_buffers\", &contigmem_num_buffers);\nTUNABLE_QUAD(\"hw.contigmem.buffer_size\", &contigmem_buffer_size);\n\nstatic SYSCTL_NODE(_hw, OID_AUTO, contigmem, CTLFLAG_RD, 0, \"contigmem\");\n\nSYSCTL_INT(_hw_contigmem, OID_AUTO, num_buffers, CTLFLAG_RD,\n\t&contigmem_num_buffers, 0, \"Number of contigmem buffers allocated\");\nSYSCTL_QUAD(_hw_contigmem, OID_AUTO, buffer_size, CTLFLAG_RD,\n\t&contigmem_buffer_size, 0, \"Size of each contiguous buffer\");\n\nstatic SYSCTL_NODE(_hw_contigmem, OID_AUTO, physaddr, CTLFLAG_RD, 0,\n\t\"physaddr\");\n\nMALLOC_DEFINE(M_CONTIGMEM, \"contigmem\", \"contigmem(4) allocations\");\n\nstatic int contigmem_modevent(module_t mod, int type, void *arg)\n{\n\tint error = 0;\n\n\tswitch (type) {\n\tcase MOD_LOAD:\n\t\terror = contigmem_load();\n\t\tbreak;\n\tcase MOD_UNLOAD:\n\t\terror = contigmem_unload();\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn error;\n}\n\nmoduledata_t contigmem_mod = {\n\t\"contigmem\",\n\t(modeventhand_t)contigmem_modevent,\n\t0\n};\n\nDECLARE_MODULE(contigmem, contigmem_mod, SI_SUB_DRIVERS, SI_ORDER_ANY);\nMODULE_VERSION(contigmem, 1);\n\nstatic struct cdevsw contigmem_ops = {\n\t.d_name = \"contigmem\",\n\t.d_version = D_VERSION,\n\t.d_mmap = contigmem_mmap,\n\t.d_mmap_single = contigmem_mmap_single,\n\t.d_open = contigmem_open,\n};\n\nstatic int\ncontigmem_load()\n{\n\tchar index_string[8], description[32];\n\tint i;\n\n\tif (contigmem_num_buffers > RTE_CONTIGMEM_MAX_NUM_BUFS) {\n\t\tprintf(\"%d buffers requested is greater than %d allowed\\n\",\n\t\t\t\tcontigmem_num_buffers, RTE_CONTIGMEM_MAX_NUM_BUFS);\n\t\treturn EINVAL;\n\t}\n\n\tif (contigmem_buffer_size < PAGE_SIZE ||\n\t\t\t(contigmem_buffer_size & (contigmem_buffer_size - 1)) != 0) {\n\t\tprintf(\"buffer size 0x%lx is not greater than PAGE_SIZE and \"\n\t\t\t\t\"power of two\\n\", contigmem_buffer_size);\n\t\treturn EINVAL;\n\t}\n\n\tfor (i = 0; i < contigmem_num_buffers; i++) {\n\t\tcontigmem_buffers[i] =\n\t\t\t\tcontigmalloc(contigmem_buffer_size, M_CONTIGMEM, M_ZERO, 0,\n\t\t\tBUS_SPACE_MAXADDR, contigmem_buffer_size, 0);\n\n\t\tif (contigmem_buffers[i] == NULL) {\n\t\t\tprintf(\"contigmalloc failed for buffer %d\\n\", i);\n\t\t\treturn ENOMEM;\n\t\t}\n\n\t\tprintf(\"%2u: virt=%p phys=%p\\n\", i, contigmem_buffers[i],\n\t\t\t\t(void *)pmap_kextract((vm_offset_t)contigmem_buffers[i]));\n\n\t\tsnprintf(index_string, sizeof(index_string), \"%d\", i);\n\t\tsnprintf(description, sizeof(description),\n\t\t\t\t\"phys addr for buffer %d\", i);\n\t\tSYSCTL_ADD_PROC(NULL,\n\t\t\t\t&SYSCTL_NODE_CHILDREN(_hw_contigmem, physaddr), OID_AUTO,\n\t\t\t\tindex_string, CTLTYPE_U64 | CTLFLAG_RD,\n\t\t\t\t(void *)(uintptr_t)i, 0, contigmem_physaddr, \"LU\",\n\t\t\t\tdescription);\n\t}\n\n\tcontigmem_cdev = make_dev_credf(0, &contigmem_ops, 0, NULL, UID_ROOT,\n\t\t\tGID_WHEEL, 0600, \"contigmem\");\n\n\treturn 0;\n}\n\nstatic int\ncontigmem_unload()\n{\n\tint i;\n\n\tif (contigmem_cdev != NULL)\n\t\tdestroy_dev(contigmem_cdev);\n\n\tif (contigmem_eh_tag != NULL)\n\t\tEVENTHANDLER_DEREGISTER(process_exit, contigmem_eh_tag);\n\n\tfor (i = 0; i < RTE_CONTIGMEM_MAX_NUM_BUFS; i++)\n\t\tif (contigmem_buffers[i] != NULL)\n\t\t\tcontigfree(contigmem_buffers[i], contigmem_buffer_size,\n\t\t\t\t\tM_CONTIGMEM);\n\n\treturn 0;\n}\n\nstatic int\ncontigmem_physaddr(SYSCTL_HANDLER_ARGS)\n{\n\tuint64_t\tphysaddr;\n\tint\t\tindex = (int)(uintptr_t)arg1;\n\n\tphysaddr = (uint64_t)vtophys(contigmem_buffers[index]);\n\treturn sysctl_handle_64(oidp, &physaddr, 0, req);\n}\n\nstatic int\ncontigmem_open(struct cdev *cdev, int fflags, int devtype,\n\t\tstruct thread *td)\n{\n\treturn 0;\n}\n\nstatic int\ncontigmem_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr,\n\t\tint prot, vm_memattr_t *memattr)\n{\n\n\t*paddr = offset;\n\treturn 0;\n}\n\nstatic int\ncontigmem_mmap_single(struct cdev *cdev, vm_ooffset_t *offset, vm_size_t size,\n\t\tstruct vm_object **obj, int nprot)\n{\n\t/*\n\t * The buffer index is encoded in the offset. Divide the offset by\n\t * PAGE_SIZE to get the index of the buffer requested by the user\n\t * app.\n\t */\n\tif ((*offset/PAGE_SIZE) >= contigmem_num_buffers)\n\t\treturn EINVAL;\n\n\t*offset = (vm_ooffset_t)vtophys(contigmem_buffers[*offset/PAGE_SIZE]);\n\t*obj = vm_pager_allocate(OBJT_DEVICE, cdev, size, nprot, *offset,\n\t\t\tcurthread->td_ucred);\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/bsdapp/eal/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nLIB = librte_eal.a\n\nVPATH += $(RTE_SDK)/lib/librte_eal/common\n\nCFLAGS += -I$(SRCDIR)/include\nCFLAGS += -I$(RTE_SDK)/lib/librte_eal/common\nCFLAGS += -I$(RTE_SDK)/lib/librte_eal/common/include\nCFLAGS += -I$(RTE_SDK)/lib/librte_ring\nCFLAGS += -I$(RTE_SDK)/lib/librte_mempool\nCFLAGS += $(WERROR_FLAGS) -O3\n\nEXPORT_MAP := rte_eal_version.map\n\nLIBABIVER := 1\n\n# specific to linuxapp exec-env\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) := eal.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_memory.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_hugepage_info.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_thread.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_log.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_pci.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_debug.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_lcore.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_timer.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_interrupts.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_alarm.c\n\n# from common dir\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_lcore.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_timer.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_memzone.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_log.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_launch.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_pci.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_pci_uio.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_memory.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_tailqs.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_errno.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_cpuflags.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_string_fns.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_hexdump.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_devargs.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_dev.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_options.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += eal_common_thread.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += rte_malloc.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += malloc_elem.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += malloc_heap.c\n\nCFLAGS_eal.o := -D_GNU_SOURCE\n#CFLAGS_eal_thread.o := -D_GNU_SOURCE\nCFLAGS_eal_log.o := -D_GNU_SOURCE\nCFLAGS_eal_common_log.o := -D_GNU_SOURCE\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_eal_thread.o += -Wno-return-type\nCFLAGS_eal_hpet.o += -Wno-return-type\nendif\n\nINC := rte_interrupts.h\n\nSYMLINK-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP)-include/exec-env := \\\n\t$(addprefix include/exec-env/,$(INC))\n\nDEPDIRS-$(CONFIG_RTE_LIBRTE_EAL_BSDAPP) += lib/librte_eal/common\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_eal/bsdapp/eal/eal.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_thread.h\"\n#include \"eal_internal_cfg.h\"\n#include \"eal_filesystem.h\"\n#include \"eal_hugepages.h\"\n#include \"eal_options.h\"\n\n#define MEMSIZE_IF_NO_HUGE_PAGE (64ULL * 1024ULL * 1024ULL)\n\n/* Allow the application to print its usage message too if set */\nstatic rte_usage_hook_t\trte_application_usage_hook = NULL;\n/* early configuration structure, when memory config is not mmapped */\nstatic struct rte_mem_config early_mem_config;\n\n/* define fd variable here, because file needs to be kept open for the\n * duration of the program, as we hold a write lock on it in the primary proc */\nstatic int mem_cfg_fd = -1;\n\nstatic struct flock wr_lock = {\n\t\t.l_type = F_WRLCK,\n\t\t.l_whence = SEEK_SET,\n\t\t.l_start = offsetof(struct rte_mem_config, memseg),\n\t\t.l_len = sizeof(early_mem_config.memseg),\n};\n\n/* Address of global and public configuration */\nstatic struct rte_config rte_config = {\n\t\t.mem_config = &early_mem_config,\n};\n\n/* internal configuration (per-core) */\nstruct lcore_config lcore_config[RTE_MAX_LCORE];\n\n/* internal configuration */\nstruct internal_config internal_config;\n\n/* used by rte_rdtsc() */\nint rte_cycles_vmware_tsc_map;\n\n/* Return a pointer to the configuration structure */\nstruct rte_config *\nrte_eal_get_configuration(void)\n{\n\treturn &rte_config;\n}\n\n/* parse a sysfs (or other) file containing one integer value */\nint\neal_parse_sysfs_value(const char *filename, unsigned long *val)\n{\n\tFILE *f;\n\tchar buf[BUFSIZ];\n\tchar *end = NULL;\n\n\tif ((f = fopen(filename, \"r\")) == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot open sysfs value %s\\n\",\n\t\t\t__func__, filename);\n\t\treturn -1;\n\t}\n\n\tif (fgets(buf, sizeof(buf), f) == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot read sysfs value %s\\n\",\n\t\t\t__func__, filename);\n\t\tfclose(f);\n\t\treturn -1;\n\t}\n\t*val = strtoul(buf, &end, 0);\n\tif ((buf[0] == '\\0') || (end == NULL) || (*end != '\\n')) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot parse sysfs value %s\\n\",\n\t\t\t\t__func__, filename);\n\t\tfclose(f);\n\t\treturn -1;\n\t}\n\tfclose(f);\n\treturn 0;\n}\n\n\n/* create memory configuration in shared/mmap memory. Take out\n * a write lock on the memsegs, so we can auto-detect primary/secondary.\n * This means we never close the file while running (auto-close on exit).\n * We also don't lock the whole file, so that in future we can use read-locks\n * on other parts, e.g. memzones, to detect if there are running secondary\n * processes. */\nstatic void\nrte_eal_config_create(void)\n{\n\tvoid *rte_mem_cfg_addr;\n\tint retval;\n\n\tconst char *pathname = eal_runtime_config_path();\n\n\tif (internal_config.no_shconf)\n\t\treturn;\n\n\tif (mem_cfg_fd < 0){\n\t\tmem_cfg_fd = open(pathname, O_RDWR | O_CREAT, 0660);\n\t\tif (mem_cfg_fd < 0)\n\t\t\trte_panic(\"Cannot open '%s' for rte_mem_config\\n\", pathname);\n\t}\n\n\tretval = ftruncate(mem_cfg_fd, sizeof(*rte_config.mem_config));\n\tif (retval < 0){\n\t\tclose(mem_cfg_fd);\n\t\trte_panic(\"Cannot resize '%s' for rte_mem_config\\n\", pathname);\n\t}\n\n\tretval = fcntl(mem_cfg_fd, F_SETLK, &wr_lock);\n\tif (retval < 0){\n\t\tclose(mem_cfg_fd);\n\t\trte_exit(EXIT_FAILURE, \"Cannot create lock on '%s'. Is another primary \"\n\t\t\t\t\"process running?\\n\", pathname);\n\t}\n\n\trte_mem_cfg_addr = mmap(NULL, sizeof(*rte_config.mem_config),\n\t\t\t\tPROT_READ | PROT_WRITE, MAP_SHARED, mem_cfg_fd, 0);\n\n\tif (rte_mem_cfg_addr == MAP_FAILED){\n\t\trte_panic(\"Cannot mmap memory for rte_config\\n\");\n\t}\n\tmemcpy(rte_mem_cfg_addr, &early_mem_config, sizeof(early_mem_config));\n\trte_config.mem_config = (struct rte_mem_config *) rte_mem_cfg_addr;\n}\n\n/* attach to an existing shared memory config */\nstatic void\nrte_eal_config_attach(void)\n{\n\tvoid *rte_mem_cfg_addr;\n\tconst char *pathname = eal_runtime_config_path();\n\n\tif (internal_config.no_shconf)\n\t\treturn;\n\n\tif (mem_cfg_fd < 0){\n\t\tmem_cfg_fd = open(pathname, O_RDWR);\n\t\tif (mem_cfg_fd < 0)\n\t\t\trte_panic(\"Cannot open '%s' for rte_mem_config\\n\", pathname);\n\t}\n\n\trte_mem_cfg_addr = mmap(NULL, sizeof(*rte_config.mem_config),\n\t\t\t\tPROT_READ | PROT_WRITE, MAP_SHARED, mem_cfg_fd, 0);\n\tclose(mem_cfg_fd);\n\tif (rte_mem_cfg_addr == MAP_FAILED)\n\t\trte_panic(\"Cannot mmap memory for rte_config\\n\");\n\n\trte_config.mem_config = (struct rte_mem_config *) rte_mem_cfg_addr;\n}\n\n/* Detect if we are a primary or a secondary process */\nenum rte_proc_type_t\neal_proc_type_detect(void)\n{\n\tenum rte_proc_type_t ptype = RTE_PROC_PRIMARY;\n\tconst char *pathname = eal_runtime_config_path();\n\n\t/* if we can open the file but not get a write-lock we are a secondary\n\t * process. NOTE: if we get a file handle back, we keep that open\n\t * and don't close it to prevent a race condition between multiple opens */\n\tif (((mem_cfg_fd = open(pathname, O_RDWR)) >= 0) &&\n\t\t\t(fcntl(mem_cfg_fd, F_SETLK, &wr_lock) < 0))\n\t\tptype = RTE_PROC_SECONDARY;\n\n\tRTE_LOG(INFO, EAL, \"Auto-detected process type: %s\\n\",\n\t\t\tptype == RTE_PROC_PRIMARY ? \"PRIMARY\" : \"SECONDARY\");\n\n\treturn ptype;\n}\n\n/* Sets up rte_config structure with the pointer to shared memory config.*/\nstatic void\nrte_config_init(void)\n{\n\trte_config.process_type = internal_config.process_type;\n\n\tswitch (rte_config.process_type){\n\tcase RTE_PROC_PRIMARY:\n\t\trte_eal_config_create();\n\t\tbreak;\n\tcase RTE_PROC_SECONDARY:\n\t\trte_eal_config_attach();\n\t\trte_eal_mcfg_wait_complete(rte_config.mem_config);\n\t\tbreak;\n\tcase RTE_PROC_AUTO:\n\tcase RTE_PROC_INVALID:\n\t\trte_panic(\"Invalid process type\\n\");\n\t}\n}\n\n/* display usage */\nstatic void\neal_usage(const char *prgname)\n{\n\tprintf(\"\\nUsage: %s \", prgname);\n\teal_common_usage();\n\t/* Allow the application to print its usage message too if hook is set */\n\tif ( rte_application_usage_hook ) {\n\t\tprintf(\"===== Application Usage =====\\n\\n\");\n\t\trte_application_usage_hook(prgname);\n\t}\n}\n\n/* Set a per-application usage message */\nrte_usage_hook_t\nrte_set_application_usage_hook( rte_usage_hook_t usage_func )\n{\n\trte_usage_hook_t\told_func;\n\n\t/* Will be NULL on the first call to denote the last usage routine. */\n\told_func\t\t\t\t\t= rte_application_usage_hook;\n\trte_application_usage_hook\t= usage_func;\n\n\treturn old_func;\n}\n\nstatic inline size_t\neal_get_hugepage_mem_size(void)\n{\n\tuint64_t size = 0;\n\tunsigned i, j;\n\n\tfor (i = 0; i < internal_config.num_hugepage_sizes; i++) {\n\t\tstruct hugepage_info *hpi = &internal_config.hugepage_info[i];\n\t\tif (hpi->hugedir != NULL) {\n\t\t\tfor (j = 0; j < RTE_MAX_NUMA_NODES; j++) {\n\t\t\t\tsize += hpi->hugepage_sz * hpi->num_pages[j];\n\t\t\t}\n\t\t}\n\t}\n\n\treturn (size < SIZE_MAX) ? (size_t)(size) : SIZE_MAX;\n}\n\n/* Parse the arguments for --log-level only */\nstatic void\neal_log_level_parse(int argc, char **argv)\n{\n\tint opt;\n\tchar **argvopt;\n\tint option_index;\n\n\targvopt = argv;\n\n\teal_reset_internal_config(&internal_config);\n\n\twhile ((opt = getopt_long(argc, argvopt, eal_short_options,\n\t\t\t\t eal_long_options, &option_index)) != EOF) {\n\n\t\tint ret;\n\n\t\t/* getopt is not happy, stop right now */\n\t\tif (opt == '?')\n\t\t\tbreak;\n\n\t\tret = (opt == OPT_LOG_LEVEL_NUM) ?\n\t\t\teal_parse_common_option(opt, optarg, &internal_config) : 0;\n\n\t\t/* common parser is not happy */\n\t\tif (ret < 0)\n\t\t\tbreak;\n\t}\n\n\toptind = 0; /* reset getopt lib */\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\neal_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, eal_short_options,\n\t\t\t\t eal_long_options, &option_index)) != EOF) {\n\n\t\tint ret;\n\n\t\t/* getopt is not happy, stop right now */\n\t\tif (opt == '?') {\n\t\t\teal_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\n\t\tret = eal_parse_common_option(opt, optarg, &internal_config);\n\t\t/* common parser is not happy */\n\t\tif (ret < 0) {\n\t\t\teal_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t\t/* common parser handled this option */\n\t\tif (ret == 0)\n\t\t\tcontinue;\n\n\t\tswitch (opt) {\n\t\tcase 'h':\n\t\t\teal_usage(prgname);\n\t\t\texit(EXIT_SUCCESS);\n\t\tdefault:\n\t\t\tif (opt < OPT_LONG_MIN_NUM && isprint(opt)) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Option %c is not supported \"\n\t\t\t\t\t\"on FreeBSD\\n\", opt);\n\t\t\t} else if (opt >= OPT_LONG_MIN_NUM &&\n\t\t\t\t opt < OPT_LONG_MAX_NUM) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Option %s is not supported \"\n\t\t\t\t\t\"on FreeBSD\\n\",\n\t\t\t\t\teal_long_options[option_index].name);\n\t\t\t} else {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Option %d is not supported \"\n\t\t\t\t\t\"on FreeBSD\\n\", opt);\n\t\t\t}\n\t\t\teal_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (eal_adjust_config(&internal_config) != 0)\n\t\treturn -1;\n\n\t/* sanity checks */\n\tif (eal_check_common_options(&internal_config) != 0) {\n\t\teal_usage(prgname);\n\t\treturn -1;\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\nstatic void\neal_check_mem_on_local_socket(void)\n{\n\tconst struct rte_memseg *ms;\n\tint i, socket_id;\n\n\tsocket_id = rte_lcore_to_socket_id(rte_config.master_lcore);\n\n\tms = rte_eal_get_physmem_layout();\n\n\tfor (i = 0; i < RTE_MAX_MEMSEG; i++)\n\t\tif (ms[i].socket_id == socket_id &&\n\t\t\t\tms[i].len > 0)\n\t\t\treturn;\n\n\tRTE_LOG(WARNING, EAL, \"WARNING: Master core has no \"\n\t\t\t\"memory on local socket!\\n\");\n}\n\nstatic int\nsync_func(__attribute__((unused)) void *arg)\n{\n\treturn 0;\n}\n\ninline static void\nrte_eal_mcfg_complete(void)\n{\n\t/* ALL shared mem_config related INIT DONE */\n\tif (rte_config.process_type == RTE_PROC_PRIMARY)\n\t\trte_config.mem_config->magic = RTE_MAGIC;\n}\n\n/* return non-zero if hugepages are enabled. */\nint rte_eal_has_hugepages(void)\n{\n\treturn !internal_config.no_hugetlbfs;\n}\n\n/* Abstraction for port I/0 privilege */\nint\nrte_eal_iopl_init(void)\n{\n\tstatic int fd;\n\n\tfd = open(\"/dev/io\", O_RDWR);\n\tif (fd < 0)\n\t\treturn -1;\n\t/* keep fd open for iopl */\n\treturn 0;\n}\n\n/* Launch threads, called at application init(). */\nint\nrte_eal_init(int argc, char **argv)\n{\n\tint i, fctret, ret;\n\tpthread_t thread_id;\n\tstatic rte_atomic32_t run_once = RTE_ATOMIC32_INIT(0);\n\tchar cpuset[RTE_CPU_AFFINITY_STR_LEN];\n\n\tif (!rte_atomic32_test_and_set(&run_once))\n\t\treturn -1;\n\n\tthread_id = pthread_self();\n\n\tif (rte_eal_log_early_init() < 0)\n\t\trte_panic(\"Cannot init early logs\\n\");\n\n\teal_log_level_parse(argc, argv);\n\n\t/* set log level as early as possible */\n\trte_set_log_level(internal_config.log_level);\n\n\tif (rte_eal_cpu_init() < 0)\n\t\trte_panic(\"Cannot detect lcores\\n\");\n\n\tfctret = eal_parse_args(argc, argv);\n\tif (fctret < 0)\n\t\texit(1);\n\n\tif (internal_config.no_hugetlbfs == 0 &&\n\t\t\tinternal_config.process_type != RTE_PROC_SECONDARY &&\n\t\t\teal_hugepage_info_init() < 0)\n\t\trte_panic(\"Cannot get hugepage information\\n\");\n\n\tif (internal_config.memory == 0 && internal_config.force_sockets == 0) {\n\t\tif (internal_config.no_hugetlbfs)\n\t\t\tinternal_config.memory = MEMSIZE_IF_NO_HUGE_PAGE;\n\t\telse\n\t\t\tinternal_config.memory = eal_get_hugepage_mem_size();\n\t}\n\n\tif (internal_config.vmware_tsc_map == 1) {\n#ifdef RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT\n\t\trte_cycles_vmware_tsc_map = 1;\n\t\tRTE_LOG (DEBUG, EAL, \"Using VMWARE TSC MAP, \"\n\t\t\t\t\"you must have monitor_control.pseudo_perfctr = TRUE\\n\");\n#else\n\t\tRTE_LOG (WARNING, EAL, \"Ignoring --vmware-tsc-map because \"\n\t\t\t\t\"RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT is not set\\n\");\n#endif\n\t}\n\n\trte_srand(rte_rdtsc());\n\n\trte_config_init();\n\n\tif (rte_eal_memory_init() < 0)\n\t\trte_panic(\"Cannot init memory\\n\");\n\n\tif (rte_eal_memzone_init() < 0)\n\t\trte_panic(\"Cannot init memzone\\n\");\n\n\tif (rte_eal_tailqs_init() < 0)\n\t\trte_panic(\"Cannot init tail queues for objects\\n\");\n\n/*\tif (rte_eal_log_init(argv[0], internal_config.syslog_facility) < 0)\n\t\trte_panic(\"Cannot init logs\\n\");*/\n\n\tif (rte_eal_alarm_init() < 0)\n\t\trte_panic(\"Cannot init interrupt-handling thread\\n\");\n\n\tif (rte_eal_intr_init() < 0)\n\t\trte_panic(\"Cannot init interrupt-handling thread\\n\");\n\n\tif (rte_eal_timer_init() < 0)\n\t\trte_panic(\"Cannot init HPET or TSC timers\\n\");\n\n\tif (rte_eal_pci_init() < 0)\n\t\trte_panic(\"Cannot init PCI\\n\");\n\n\teal_check_mem_on_local_socket();\n\n\trte_eal_mcfg_complete();\n\n\teal_thread_init_master(rte_config.master_lcore);\n\n\tret = eal_thread_dump_affinity(cpuset, RTE_CPU_AFFINITY_STR_LEN);\n\n\tRTE_LOG(DEBUG, EAL, \"Master lcore %u is ready (tid=%p;cpuset=[%s%s])\\n\",\n\t\trte_config.master_lcore, thread_id, cpuset,\n\t\tret == 0 ? \"\" : \"...\");\n\n\tif (rte_eal_dev_init() < 0)\n\t\trte_panic(\"Cannot init pmd devices\\n\");\n\n\tRTE_LCORE_FOREACH_SLAVE(i) {\n\n\t\t/*\n\t\t * create communication pipes between master thread\n\t\t * and children\n\t\t */\n\t\tif (pipe(lcore_config[i].pipe_master2slave) < 0)\n\t\t\trte_panic(\"Cannot create pipe\\n\");\n\t\tif (pipe(lcore_config[i].pipe_slave2master) < 0)\n\t\t\trte_panic(\"Cannot create pipe\\n\");\n\n\t\tlcore_config[i].state = WAIT;\n\n\t\t/* create a thread for each lcore */\n\t\tret = pthread_create(&lcore_config[i].thread_id, NULL,\n\t\t\t\t eal_thread_loop, NULL);\n\t\tif (ret != 0)\n\t\t\trte_panic(\"Cannot create thread\\n\");\n\t}\n\n\t/*\n\t * Launch a dummy function on all slave lcores, so that master lcore\n\t * knows they are all ready when this function returns.\n\t */\n\trte_eal_mp_remote_launch(sync_func, NULL, SKIP_MASTER);\n\trte_eal_mp_wait_lcore();\n\n\t/* Probe & Initialize PCI devices */\n\tif (rte_eal_pci_probe())\n\t\trte_panic(\"Cannot probe PCI\\n\");\n\n\treturn fctret;\n}\n\n/* get core role */\nenum rte_lcore_role_t\nrte_eal_lcore_role(unsigned lcore_id)\n{\n\treturn rte_config.lcore_role[lcore_id];\n}\n\nenum rte_proc_type_t\nrte_eal_process_type(void)\n{\n\treturn rte_config.process_type;\n}\n" }, { "path": "lib/librte_eal/bsdapp/eal/eal_alarm.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n\n#include \n#include \n#include \"eal_private.h\"\n\nint\nrte_eal_alarm_init(void)\n{\n\treturn 0;\n}\n\n\nint\nrte_eal_alarm_set(uint64_t us __rte_unused,\n\t\trte_eal_alarm_callback cb_fn __rte_unused,\n\t\tvoid *cb_arg __rte_unused)\n{\n\treturn -ENOTSUP;\n}\n\nint\nrte_eal_alarm_cancel(rte_eal_alarm_callback cb_fn __rte_unused,\n\t\tvoid *cb_arg __rte_unused)\n{\n\treturn -ENOTSUP;\n}\n" }, { "path": "lib/librte_eal/bsdapp/eal/eal_debug.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#define BACKTRACE_SIZE 256\n\n/* dump the stack of the calling core */\nvoid rte_dump_stack(void)\n{\n\tvoid *func[BACKTRACE_SIZE];\n\tchar **symb = NULL;\n\tint size;\n\n\tsize = backtrace(func, BACKTRACE_SIZE);\n\tsymb = backtrace_symbols(func, size);\n\twhile (size > 0) {\n\t\trte_log(RTE_LOG_ERR, RTE_LOGTYPE_EAL,\n\t\t\t\"%d: [%s]\\n\", size, symb[size - 1]);\n\t\tsize --;\n\t}\n}\n\n/* not implemented in this environment */\nvoid rte_dump_registers(void)\n{\n\treturn;\n}\n\n/* call abort(), it will generate a coredump if enabled */\nvoid __rte_panic(const char *funcname, const char *format, ...)\n{\n\tva_list ap;\n\n\t/* disable history */\n\trte_log_set_history(0);\n\n\trte_log(RTE_LOG_CRIT, RTE_LOGTYPE_EAL, \"PANIC in %s():\\n\", funcname);\n\tva_start(ap, format);\n\trte_vlog(RTE_LOG_CRIT, RTE_LOGTYPE_EAL, format, ap);\n\tva_end(ap);\n\trte_dump_stack();\n\trte_dump_registers();\n\tabort();\n}\n\n/*\n * Like rte_panic this terminates the application. However, no traceback is\n * provided and no core-dump is generated.\n */\nvoid\nrte_exit(int exit_code, const char *format, ...)\n{\n\tva_list ap;\n\n\t/* disable history */\n\trte_log_set_history(0);\n\n\tif (exit_code != 0)\n\t\tRTE_LOG(CRIT, EAL, \"Error - exiting with code: %d\\n\"\n\t\t\t\t\" Cause: \", exit_code);\n\n\tva_start(ap, format);\n\trte_vlog(RTE_LOG_CRIT, RTE_LOGTYPE_EAL, format, ap);\n\tva_end(ap);\n\n#ifndef RTE_EAL_ALWAYS_PANIC_ON_ERROR\n\texit(exit_code);\n#else\n\trte_dump_stack();\n\trte_dump_registers();\n\tabort();\n#endif\n}\n" }, { "path": "lib/librte_eal/bsdapp/eal/eal_hugepage_info.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \"eal_hugepages.h\"\n#include \"eal_internal_cfg.h\"\n#include \"eal_filesystem.h\"\n\n#define CONTIGMEM_DEV \"/dev/contigmem\"\n\n/*\n * Uses mmap to create a shared memory area for storage of data\n * Used in this file to store the hugepage file map on disk\n */\nstatic void *\ncreate_shared_memory(const char *filename, const size_t mem_size)\n{\n\tvoid *retval;\n\tint fd = open(filename, O_CREAT | O_RDWR, 0666);\n\tif (fd < 0)\n\t\treturn NULL;\n\tif (ftruncate(fd, mem_size) < 0) {\n\t\tclose(fd);\n\t\treturn NULL;\n\t}\n\tretval = mmap(NULL, mem_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);\n\tclose(fd);\n\treturn retval;\n}\n\n/*\n * No hugepage support on freebsd, but we dummy it, using contigmem driver\n */\nint\neal_hugepage_info_init(void)\n{\n\tsize_t sysctl_size;\n\tint num_buffers, fd, error;\n\tint64_t buffer_size;\n\t/* re-use the linux \"internal config\" structure for our memory data */\n\tstruct hugepage_info *hpi = &internal_config.hugepage_info[0];\n\tstruct hugepage_info *tmp_hpi;\n\n\tsysctl_size = sizeof(num_buffers);\n\terror = sysctlbyname(\"hw.contigmem.num_buffers\", &num_buffers,\n\t\t\t&sysctl_size, NULL, 0);\n\n\tif (error != 0) {\n\t\tRTE_LOG(ERR, EAL, \"could not read sysctl hw.contigmem.num_buffers\");\n\t\treturn -1;\n\t}\n\n\tsysctl_size = sizeof(buffer_size);\n\terror = sysctlbyname(\"hw.contigmem.buffer_size\", &buffer_size,\n\t\t\t&sysctl_size, NULL, 0);\n\n\tif (error != 0) {\n\t\tRTE_LOG(ERR, EAL, \"could not read sysctl hw.contigmem.buffer_size\");\n\t\treturn -1;\n\t}\n\n\tfd = open(CONTIGMEM_DEV, O_RDWR);\n\tif (fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"could not open \"CONTIGMEM_DEV\"\\n\");\n\t\treturn -1;\n\t}\n\n\tif (buffer_size >= 1<<30)\n\t\tRTE_LOG(INFO, EAL, \"Contigmem driver has %d buffers, each of size %dGB\\n\",\n\t\t\t\tnum_buffers, (int)(buffer_size>>30));\n\telse if (buffer_size >= 1<<20)\n\t\tRTE_LOG(INFO, EAL, \"Contigmem driver has %d buffers, each of size %dMB\\n\",\n\t\t\t\tnum_buffers, (int)(buffer_size>>20));\n\telse\n\t\tRTE_LOG(INFO, EAL, \"Contigmem driver has %d buffers, each of size %dKB\\n\",\n\t\t\t\tnum_buffers, (int)(buffer_size>>10));\n\n\tinternal_config.num_hugepage_sizes = 1;\n\thpi->hugedir = CONTIGMEM_DEV;\n\thpi->hugepage_sz = buffer_size;\n\thpi->num_pages[0] = num_buffers;\n\thpi->lock_descriptor = fd;\n\n\ttmp_hpi = create_shared_memory(eal_hugepage_info_path(),\n\t\t\t\t\tsizeof(struct hugepage_info));\n\tif (tmp_hpi == NULL ) {\n\t\tRTE_LOG(ERR, EAL, \"Failed to create shared memory!\\n\");\n\t\treturn -1;\n\t}\n\n\tmemcpy(tmp_hpi, hpi, sizeof(struct hugepage_info));\n\n\tif ( munmap(tmp_hpi, sizeof(struct hugepage_info)) < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Failed to unmap shared memory!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/bsdapp/eal/eal_interrupts.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \"eal_private.h\"\n\nint\nrte_intr_callback_register(struct rte_intr_handle *intr_handle __rte_unused,\n\t\t\trte_intr_callback_fn cb __rte_unused,\n\t\t\tvoid *cb_arg __rte_unused)\n{\n\treturn -ENOTSUP;\n}\n\nint\nrte_intr_callback_unregister(struct rte_intr_handle *intr_handle __rte_unused,\n\t\t\trte_intr_callback_fn cb_fn __rte_unused,\n\t\t\tvoid *cb_arg __rte_unused)\n{\n\treturn -ENOTSUP;\n}\n\nint\nrte_intr_enable(struct rte_intr_handle *intr_handle __rte_unused)\n{\n\treturn -ENOTSUP;\n}\n\nint\nrte_intr_disable(struct rte_intr_handle *intr_handle __rte_unused)\n{\n\treturn -ENOTSUP;\n}\n\nint\nrte_eal_intr_init(void)\n{\n\treturn 0;\n}\n\nint\nrte_intr_rx_ctl(struct rte_intr_handle *intr_handle,\n\t\tint epfd, int op, unsigned int vec, void *data)\n{\n\tRTE_SET_USED(intr_handle);\n\tRTE_SET_USED(epfd);\n\tRTE_SET_USED(op);\n\tRTE_SET_USED(vec);\n\tRTE_SET_USED(data);\n\n\treturn -ENOTSUP;\n}\n\nint\nrte_intr_efd_enable(struct rte_intr_handle *intr_handle, uint32_t nb_efd)\n{\n\tRTE_SET_USED(intr_handle);\n\tRTE_SET_USED(nb_efd);\n\n\treturn 0;\n}\n\nvoid\nrte_intr_efd_disable(struct rte_intr_handle *intr_handle)\n{\n\tRTE_SET_USED(intr_handle);\n}\n\nint\nrte_intr_dp_is_en(struct rte_intr_handle *intr_handle)\n{\n\tRTE_SET_USED(intr_handle);\n\treturn 0;\n}\n\nint\nrte_intr_allow_others(struct rte_intr_handle *intr_handle)\n{\n\tRTE_SET_USED(intr_handle);\n\treturn 1;\n}\n" }, { "path": "lib/librte_eal/bsdapp/eal/eal_lcore.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_thread.h\"\n\n/* No topology information available on FreeBSD including NUMA info */\nunsigned\neal_cpu_core_id(__rte_unused unsigned lcore_id)\n{\n\treturn 0;\n}\n\nstatic int\neal_get_ncpus(void)\n{\n\tint mib[2] = {CTL_HW, HW_NCPU};\n\tint ncpu;\n\tsize_t len = sizeof(ncpu);\n\n\tsysctl(mib, 2, &ncpu, &len, NULL, 0);\n\tRTE_LOG(INFO, EAL, \"Sysctl reports %d cpus\\n\", ncpu);\n\treturn ncpu;\n}\n\nunsigned\neal_cpu_socket_id(__rte_unused unsigned cpu_id)\n{\n\treturn 0;\n}\n\n/* Check if a cpu is present by the presence of the\n * cpu information for it.\n */\nint\neal_cpu_detected(unsigned lcore_id)\n{\n\tconst unsigned ncpus = eal_get_ncpus();\n\treturn (lcore_id < ncpus);\n}\n" }, { "path": "lib/librte_eal/bsdapp/eal/eal_log.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n\n/*\n * set the log to default function, called during eal init process,\n * once memzones are available.\n */\nint\nrte_eal_log_init(const char *id __rte_unused, int facility __rte_unused)\n{\n\tif (rte_eal_common_log_init(stderr) < 0)\n\t\treturn -1;\n\treturn 0;\n}\n\nint\nrte_eal_log_early_init(void)\n{\n\trte_openlog_stream(stderr);\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/bsdapp/eal/eal_memory.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \"eal_private.h\"\n#include \"eal_internal_cfg.h\"\n#include \"eal_filesystem.h\"\n\n#define EAL_PAGE_SIZE (sysconf(_SC_PAGESIZE))\n\n/*\n * Get physical address of any mapped virtual address in the current process.\n */\nphys_addr_t\nrte_mem_virt2phy(const void *virtaddr)\n{\n\t/* XXX not implemented. This function is only used by\n\t * rte_mempool_virt2phy() when hugepages are disabled. */\n\t(void)virtaddr;\n\treturn RTE_BAD_PHYS_ADDR;\n}\n\nint\nrte_eal_hugepage_init(void)\n{\n\tstruct rte_mem_config *mcfg;\n\tuint64_t total_mem = 0;\n\tvoid *addr;\n\tunsigned i, j, seg_idx = 0;\n\n\t/* get pointer to global configuration */\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\t/* for debug purposes, hugetlbfs can be disabled */\n\tif (internal_config.no_hugetlbfs) {\n\t\taddr = malloc(internal_config.memory);\n\t\tmcfg->memseg[0].phys_addr = (phys_addr_t)(uintptr_t)addr;\n\t\tmcfg->memseg[0].addr = addr;\n\t\tmcfg->memseg[0].hugepage_sz = RTE_PGSIZE_4K;\n\t\tmcfg->memseg[0].len = internal_config.memory;\n\t\tmcfg->memseg[0].socket_id = 0;\n\t\treturn 0;\n\t}\n\n\t/* map all hugepages and sort them */\n\tfor (i = 0; i < internal_config.num_hugepage_sizes; i ++){\n\t\tstruct hugepage_info *hpi;\n\n\t\thpi = &internal_config.hugepage_info[i];\n\t\tfor (j = 0; j < hpi->num_pages[0]; j++) {\n\t\t\tstruct rte_memseg *seg;\n\t\t\tuint64_t physaddr;\n\t\t\tint error;\n\t\t\tsize_t sysctl_size = sizeof(physaddr);\n\t\t\tchar physaddr_str[64];\n\n\t\t\taddr = mmap(NULL, hpi->hugepage_sz, PROT_READ|PROT_WRITE,\n\t\t\t\t MAP_SHARED, hpi->lock_descriptor,\n\t\t\t\t j * EAL_PAGE_SIZE);\n\t\t\tif (addr == MAP_FAILED) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Failed to mmap buffer %u from %s\\n\",\n\t\t\t\t\t\tj, hpi->hugedir);\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tsnprintf(physaddr_str, sizeof(physaddr_str), \"hw.contigmem\"\n\t\t\t\t\t\".physaddr.%d\", j);\n\t\t\terror = sysctlbyname(physaddr_str, &physaddr, &sysctl_size,\n\t\t\t\t\tNULL, 0);\n\t\t\tif (error < 0) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Failed to get physical addr for buffer %u \"\n\t\t\t\t\t\t\"from %s\\n\", j, hpi->hugedir);\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tseg = &mcfg->memseg[seg_idx++];\n\t\t\tseg->addr = addr;\n\t\t\tseg->phys_addr = physaddr;\n\t\t\tseg->hugepage_sz = hpi->hugepage_sz;\n\t\t\tseg->len = hpi->hugepage_sz;\n\t\t\tseg->nchannel = mcfg->nchannel;\n\t\t\tseg->nrank = mcfg->nrank;\n\t\t\tseg->socket_id = 0;\n\n\t\t\tRTE_LOG(INFO, EAL, \"Mapped memory segment %u @ %p: physaddr:0x%\"\n\t\t\t\t\tPRIx64\", len %zu\\n\",\n\t\t\t\t\tseg_idx, addr, physaddr, hpi->hugepage_sz);\n\t\t\tif (total_mem >= internal_config.memory ||\n\t\t\t\t\tseg_idx >= RTE_MAX_MEMSEG)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\treturn 0;\n}\n\nint\nrte_eal_hugepage_attach(void)\n{\n\tconst struct hugepage_info *hpi;\n\tint fd_hugepage_info, fd_hugepage = -1;\n\tunsigned i = 0;\n\tstruct rte_mem_config *mcfg = rte_eal_get_configuration()->mem_config;\n\n\t/* Obtain a file descriptor for hugepage_info */\n\tfd_hugepage_info = open(eal_hugepage_info_path(), O_RDONLY);\n\tif (fd_hugepage_info < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Could not open %s\\n\", eal_hugepage_info_path());\n\t\treturn -1;\n\t}\n\n\t/* Map the shared hugepage_info into the process address spaces */\n\thpi = mmap(NULL, sizeof(struct hugepage_info), PROT_READ, MAP_PRIVATE,\n\t\t\tfd_hugepage_info, 0);\n\tif (hpi == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Could not mmap %s\\n\", eal_hugepage_info_path());\n\t\tgoto error;\n\t}\n\n\t/* Obtain a file descriptor for contiguous memory */\n\tfd_hugepage = open(hpi->hugedir, O_RDWR);\n\tif (fd_hugepage < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Could not open %s\\n\", hpi->hugedir);\n\t\tgoto error;\n\t}\n\n\t/* Map the contiguous memory into each memory segment */\n\tfor (i = 0; i < hpi->num_pages[0]; i++) {\n\n\t\tvoid *addr;\n\t\tstruct rte_memseg *seg = &mcfg->memseg[i];\n\n\t\taddr = mmap(seg->addr, hpi->hugepage_sz, PROT_READ|PROT_WRITE,\n\t\t\t MAP_SHARED|MAP_FIXED, fd_hugepage,\n\t\t\t i * EAL_PAGE_SIZE);\n\t\tif (addr == MAP_FAILED || addr != seg->addr) {\n\t\t\tRTE_LOG(ERR, EAL, \"Failed to mmap buffer %u from %s\\n\",\n\t\t\t\ti, hpi->hugedir);\n\t\t\tgoto error;\n\t\t}\n\n\t}\n\n\t/* hugepage_info is no longer required */\n\tmunmap((void *)(uintptr_t)hpi, sizeof(struct hugepage_info));\n\tclose(fd_hugepage_info);\n\tclose(fd_hugepage);\n\treturn 0;\n\nerror:\n\tif (fd_hugepage_info >= 0)\n\t\tclose(fd_hugepage_info);\n\tif (fd_hugepage >= 0)\n\t\tclose(fd_hugepage);\n\treturn -1;\n}\n" }, { "path": "lib/librte_eal/bsdapp/eal/eal_pci.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_filesystem.h\"\n#include \"eal_private.h\"\n\n/**\n * @file\n * PCI probing under linux\n *\n * This code is used to simulate a PCI probe by parsing information in\n * sysfs. Moreover, when a registered driver matches a device, the\n * kernel driver currently using it is unloaded and replaced by\n * igb_uio module, which is a very minimal userland driver for Intel\n * network card, only providing access to PCI BAR to applications, and\n * enabling bus master.\n */\n\n/* unbind kernel driver for this device */\nint\npci_unbind_kernel_driver(struct rte_pci_device *dev __rte_unused)\n{\n\tRTE_LOG(ERR, EAL, \"RTE_PCI_DRV_FORCE_UNBIND flag is not implemented \"\n\t\t\"for BSD\\n\");\n\treturn -ENOTSUP;\n}\n\n/* Map pci device */\nint\npci_map_device(struct rte_pci_device *dev)\n{\n\tint ret = -1;\n\n\t/* try mapping the NIC resources */\n\tswitch (dev->kdrv) {\n\tcase RTE_KDRV_NIC_UIO:\n\t\t/* map resources for devices that use uio */\n\t\tret = pci_uio_map_resource(dev);\n\t\tbreak;\n\tdefault:\n\t\tRTE_LOG(DEBUG, EAL,\n\t\t\t\" Not managed by a supported kernel driver, skipped\\n\");\n\t\tret = 1;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n/* Unmap pci device */\nvoid\npci_unmap_device(struct rte_pci_device *dev)\n{\n\t/* try unmapping the NIC resources */\n\tswitch (dev->kdrv) {\n\tcase RTE_KDRV_NIC_UIO:\n\t\t/* unmap resources for devices that use uio */\n\t\tpci_uio_unmap_resource(dev);\n\t\tbreak;\n\tdefault:\n\t\tRTE_LOG(DEBUG, EAL,\n\t\t\t\" Not managed by a supported kernel driver, skipped\\n\");\n\t\tbreak;\n\t}\n}\n\nvoid\npci_uio_free_resource(struct rte_pci_device *dev,\n\t\tstruct mapped_pci_resource *uio_res)\n{\n\trte_free(uio_res);\n\n\tif (dev->intr_handle.fd) {\n\t\tclose(dev->intr_handle.fd);\n\t\tdev->intr_handle.fd = -1;\n\t\tdev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;\n\t}\n}\n\nint\npci_uio_alloc_resource(struct rte_pci_device *dev,\n\t\tstruct mapped_pci_resource **uio_res)\n{\n\tchar devname[PATH_MAX]; /* contains the /dev/uioX */\n\tstruct rte_pci_addr *loc;\n\n\tloc = &dev->addr;\n\n\tsnprintf(devname, sizeof(devname), \"/dev/uio@pci:%u:%u:%u\",\n\t\t\tdev->addr.bus, dev->addr.devid, dev->addr.function);\n\n\tif (access(devname, O_RDWR) < 0) {\n\t\tRTE_LOG(WARNING, EAL, \" \"PCI_PRI_FMT\" not managed by UIO driver, \"\n\t\t\t\t\"skipping\\n\", loc->domain, loc->bus, loc->devid, loc->function);\n\t\treturn 1;\n\t}\n\n\t/* save fd if in primary process */\n\tdev->intr_handle.fd = open(devname, O_RDWR);\n\tif (dev->intr_handle.fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot open %s: %s\\n\",\n\t\t\tdevname, strerror(errno));\n\t\tgoto error;\n\t}\n\tdev->intr_handle.type = RTE_INTR_HANDLE_UIO;\n\n\t/* allocate the mapping details for secondary processes*/\n\t*uio_res = rte_zmalloc(\"UIO_RES\", sizeof(**uio_res), 0);\n\tif (*uio_res == NULL) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"%s(): cannot store uio mmap details\\n\", __func__);\n\t\tgoto error;\n\t}\n\n\tsnprintf((*uio_res)->path, sizeof((*uio_res)->path), \"%s\", devname);\n\tmemcpy(&(*uio_res)->pci_addr, &dev->addr, sizeof((*uio_res)->pci_addr));\n\n\treturn 0;\n\nerror:\n\tpci_uio_free_resource(dev, *uio_res);\n\treturn -1;\n}\n\nint\npci_uio_map_resource_by_index(struct rte_pci_device *dev, int res_idx,\n\t\tstruct mapped_pci_resource *uio_res, int map_idx)\n{\n\tint fd;\n\tchar *devname;\n\tvoid *mapaddr;\n\tuint64_t offset;\n\tuint64_t pagesz;\n\tstruct pci_map *maps;\n\n\tmaps = uio_res->maps;\n\tdevname = uio_res->path;\n\tpagesz = sysconf(_SC_PAGESIZE);\n\n\t/* allocate memory to keep path */\n\tmaps[map_idx].path = rte_malloc(NULL, strlen(devname) + 1, 0);\n\tif (maps[map_idx].path == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot allocate memory for path: %s\\n\",\n\t\t\t\tstrerror(errno));\n\t\treturn -1;\n\t}\n\n\t/*\n\t * open resource file, to mmap it\n\t */\n\tfd = open(devname, O_RDWR);\n\tif (fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot open %s: %s\\n\",\n\t\t\t\tdevname, strerror(errno));\n\t\tgoto error;\n\t}\n\n\t/* if matching map is found, then use it */\n\toffset = res_idx * pagesz;\n\tmapaddr = pci_map_resource(NULL, fd, (off_t)offset,\n\t\t\t(size_t)dev->mem_resource[res_idx].len, 0);\n\tclose(fd);\n\tif (mapaddr == MAP_FAILED)\n\t\tgoto error;\n\n\tmaps[map_idx].phaddr = dev->mem_resource[res_idx].phys_addr;\n\tmaps[map_idx].size = dev->mem_resource[res_idx].len;\n\tmaps[map_idx].addr = mapaddr;\n\tmaps[map_idx].offset = offset;\n\tstrcpy(maps[map_idx].path, devname);\n\tdev->mem_resource[res_idx].addr = mapaddr;\n\n\treturn 0;\n\nerror:\n\trte_free(maps[map_idx].path);\n\treturn -1;\n}\n\nstatic int\npci_scan_one(int dev_pci_fd, struct pci_conf *conf)\n{\n\tstruct rte_pci_device *dev;\n\tstruct pci_bar_io bar;\n\tunsigned i, max;\n\n\tdev = malloc(sizeof(*dev));\n\tif (dev == NULL) {\n\t\treturn -1;\n\t}\n\n\tmemset(dev, 0, sizeof(*dev));\n\tdev->addr.domain = conf->pc_sel.pc_domain;\n\tdev->addr.bus = conf->pc_sel.pc_bus;\n\tdev->addr.devid = conf->pc_sel.pc_dev;\n\tdev->addr.function = conf->pc_sel.pc_func;\n\n\t/* get vendor id */\n\tdev->id.vendor_id = conf->pc_vendor;\n\n\t/* get device id */\n\tdev->id.device_id = conf->pc_device;\n\n\t/* get subsystem_vendor id */\n\tdev->id.subsystem_vendor_id = conf->pc_subvendor;\n\n\t/* get subsystem_device id */\n\tdev->id.subsystem_device_id = conf->pc_subdevice;\n\n\t/* TODO: get max_vfs */\n\tdev->max_vfs = 0;\n\n\t/* FreeBSD has no NUMA support (yet) */\n\tdev->numa_node = 0;\n\n\t/* FreeBSD has only one pass through driver */\n\tdev->kdrv = RTE_KDRV_NIC_UIO;\n\n\t/* parse resources */\n\tswitch (conf->pc_hdr & PCIM_HDRTYPE) {\n\tcase PCIM_HDRTYPE_NORMAL:\n\t\tmax = PCIR_MAX_BAR_0;\n\t\tbreak;\n\tcase PCIM_HDRTYPE_BRIDGE:\n\t\tmax = PCIR_MAX_BAR_1;\n\t\tbreak;\n\tcase PCIM_HDRTYPE_CARDBUS:\n\t\tmax = PCIR_MAX_BAR_2;\n\t\tbreak;\n\tdefault:\n\t\tgoto skipdev;\n\t}\n\n\tfor (i = 0; i <= max; i++) {\n\t\tbar.pbi_sel = conf->pc_sel;\n\t\tbar.pbi_reg = PCIR_BAR(i);\n\t\tif (ioctl(dev_pci_fd, PCIOCGETBAR, &bar) < 0)\n\t\t\tcontinue;\n\n\t\tdev->mem_resource[i].len = bar.pbi_length;\n\t\tif (PCI_BAR_IO(bar.pbi_base)) {\n\t\t\tdev->mem_resource[i].addr = (void *)(bar.pbi_base & ~((uint64_t)0xf));\n\t\t\tcontinue;\n\t\t}\n\t\tdev->mem_resource[i].phys_addr = bar.pbi_base & ~((uint64_t)0xf);\n\t}\n\n\t/* device is valid, add in list (sorted) */\n\tif (TAILQ_EMPTY(&pci_device_list)) {\n\t\tTAILQ_INSERT_TAIL(&pci_device_list, dev, next);\n\t}\n\telse {\n\t\tstruct rte_pci_device *dev2 = NULL;\n\t\tint ret;\n\n\t\tTAILQ_FOREACH(dev2, &pci_device_list, next) {\n\t\t\tret = rte_eal_compare_pci_addr(&dev->addr, &dev2->addr);\n\t\t\tif (ret > 0)\n\t\t\t\tcontinue;\n\t\t\telse if (ret < 0) {\n\t\t\t\tTAILQ_INSERT_BEFORE(dev2, dev, next);\n\t\t\t\treturn 0;\n\t\t\t} else { /* already registered */\n\t\t\t\tdev2->kdrv = dev->kdrv;\n\t\t\t\tdev2->max_vfs = dev->max_vfs;\n\t\t\t\tmemmove(dev2->mem_resource,\n\t\t\t\t\tdev->mem_resource,\n\t\t\t\t\tsizeof(dev->mem_resource));\n\t\t\t\tfree(dev);\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t\tTAILQ_INSERT_TAIL(&pci_device_list, dev, next);\n\t}\n\n\treturn 0;\n\nskipdev:\n\tfree(dev);\n\treturn 0;\n}\n\n/*\n * Scan the content of the PCI bus, and add the devices in the devices\n * list. Call pci_scan_one() for each pci entry found.\n */\nint\nrte_eal_pci_scan(void)\n{\n\tint fd;\n\tunsigned dev_count = 0;\n\tstruct pci_conf matches[16];\n\tstruct pci_conf_io conf_io = {\n\t\t\t.pat_buf_len = 0,\n\t\t\t.num_patterns = 0,\n\t\t\t.patterns = NULL,\n\t\t\t.match_buf_len = sizeof(matches),\n\t\t\t.matches = &matches[0],\n\t};\n\n\tfd = open(\"/dev/pci\", O_RDONLY);\n\tif (fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): error opening /dev/pci\\n\", __func__);\n\t\tgoto error;\n\t}\n\n\tdo {\n\t\tunsigned i;\n\t\tif (ioctl(fd, PCIOCGETCONF, &conf_io) < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"%s(): error with ioctl on /dev/pci: %s\\n\",\n\t\t\t\t\t__func__, strerror(errno));\n\t\t\tgoto error;\n\t\t}\n\n\t\tfor (i = 0; i < conf_io.num_matches; i++)\n\t\t\tif (pci_scan_one(fd, &matches[i]) < 0)\n\t\t\t\tgoto error;\n\n\t\tdev_count += conf_io.num_matches;\n\t} while(conf_io.status == PCI_GETCONF_MORE_DEVS);\n\n\tclose(fd);\n\n\tRTE_LOG(ERR, EAL, \"PCI scan found %u devices\\n\", dev_count);\n\treturn 0;\n\nerror:\n\tif (fd >= 0)\n\t\tclose(fd);\n\treturn -1;\n}\n\n/* Read PCI config space. */\nint rte_eal_pci_read_config(const struct rte_pci_device *dev,\n\t\t\t void *buf, size_t len, off_t offset)\n{\n\tint fd = -1;\n\tstruct pci_io pi = {\n\t\t.pi_sel = {\n\t\t\t.pc_domain = dev->addr.domain,\n\t\t\t.pc_bus = dev->addr.bus,\n\t\t\t.pc_dev = dev->addr.devid,\n\t\t\t.pc_func = dev->addr.function,\n\t\t},\n\t\t.pi_reg = offset,\n\t\t.pi_width = len,\n\t};\n\n\tif (len == 3 || len > sizeof(pi.pi_data)) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): invalid pci read length\\n\", __func__);\n\t\tgoto error;\n\t}\n\n\tfd = open(\"/dev/pci\", O_RDONLY);\n\tif (fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): error opening /dev/pci\\n\", __func__);\n\t\tgoto error;\n\t}\n\n\tif (ioctl(fd, PCIOCREAD, &pi) < 0)\n\t\tgoto error;\n\tclose(fd);\n\n\tmemcpy(buf, &pi.pi_data, len);\n\treturn 0;\n\n error:\n\tif (fd >= 0)\n\t\tclose(fd);\n\treturn -1;\n}\n\n/* Write PCI config space. */\nint rte_eal_pci_write_config(const struct rte_pci_device *dev,\n\t\t\t const void *buf, size_t len, off_t offset)\n{\n\tint fd = -1;\n\n\tstruct pci_io pi = {\n\t\t.pi_sel = {\n\t\t\t.pc_domain = dev->addr.domain,\n\t\t\t.pc_bus = dev->addr.bus,\n\t\t\t.pc_dev = dev->addr.devid,\n\t\t\t.pc_func = dev->addr.function,\n\t\t},\n\t\t.pi_reg = offset,\n\t\t.pi_data = *(const uint32_t *)buf,\n\t\t.pi_width = len,\n\t};\n\n\tif (len == 3 || len > sizeof(pi.pi_data)) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): invalid pci read length\\n\", __func__);\n\t\tgoto error;\n\t}\n\n\tmemcpy(&pi.pi_data, buf, len);\n\n\tfd = open(\"/dev/pci\", O_RDONLY);\n\tif (fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): error opening /dev/pci\\n\", __func__);\n\t\tgoto error;\n\t}\n\n\tif (ioctl(fd, PCIOCWRITE, &pi) < 0)\n\t\tgoto error;\n\n\tclose(fd);\n\treturn 0;\n\n error:\n\tif (fd >= 0)\n\t\tclose(fd);\n\treturn -1;\n}\n\n/* Init the PCI EAL subsystem */\nint\nrte_eal_pci_init(void)\n{\n\tTAILQ_INIT(&pci_driver_list);\n\tTAILQ_INIT(&pci_device_list);\n\n\t/* for debug purposes, PCI can be disabled */\n\tif (internal_config.no_pci)\n\t\treturn 0;\n\n\tif (rte_eal_pci_scan() < 0) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): Cannot scan PCI bus\\n\", __func__);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/bsdapp/eal/eal_thread.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_thread.h\"\n\nRTE_DEFINE_PER_LCORE(unsigned, _lcore_id) = LCORE_ID_ANY;\nRTE_DEFINE_PER_LCORE(unsigned, _socket_id) = (unsigned)SOCKET_ID_ANY;\nRTE_DEFINE_PER_LCORE(rte_cpuset_t, _cpuset);\n\n/*\n * Send a message to a slave lcore identified by slave_id to call a\n * function f with argument arg. Once the execution is done, the\n * remote lcore switch in FINISHED state.\n */\nint\nrte_eal_remote_launch(int (*f)(void *), void *arg, unsigned slave_id)\n{\n\tint n;\n\tchar c = 0;\n\tint m2s = lcore_config[slave_id].pipe_master2slave[1];\n\tint s2m = lcore_config[slave_id].pipe_slave2master[0];\n\n\tif (lcore_config[slave_id].state != WAIT)\n\t\treturn -EBUSY;\n\n\tlcore_config[slave_id].f = f;\n\tlcore_config[slave_id].arg = arg;\n\n\t/* send message */\n\tn = 0;\n\twhile (n == 0 || (n < 0 && errno == EINTR))\n\t\tn = write(m2s, &c, 1);\n\tif (n < 0)\n\t\trte_panic(\"cannot write on configuration pipe\\n\");\n\n\t/* wait ack */\n\tdo {\n\t\tn = read(s2m, &c, 1);\n\t} while (n < 0 && errno == EINTR);\n\n\tif (n <= 0)\n\t\trte_panic(\"cannot read on configuration pipe\\n\");\n\n\treturn 0;\n}\n\n/* set affinity for current thread */\nstatic int\neal_thread_set_affinity(void)\n{\n\tunsigned lcore_id = rte_lcore_id();\n\n\t/* acquire system unique id */\n\trte_gettid();\n\n\t/* update EAL thread core affinity */\n\treturn rte_thread_set_affinity(&lcore_config[lcore_id].cpuset);\n}\n\nvoid eal_thread_init_master(unsigned lcore_id)\n{\n\t/* set the lcore ID in per-lcore memory area */\n\tRTE_PER_LCORE(_lcore_id) = lcore_id;\n\n\t/* set CPU affinity */\n\tif (eal_thread_set_affinity() < 0)\n\t\trte_panic(\"cannot set affinity\\n\");\n}\n\n/* main loop of threads */\n__attribute__((noreturn)) void *\neal_thread_loop(__attribute__((unused)) void *arg)\n{\n\tchar c;\n\tint n, ret;\n\tunsigned lcore_id;\n\tpthread_t thread_id;\n\tint m2s, s2m;\n\tchar cpuset[RTE_CPU_AFFINITY_STR_LEN];\n\n\tthread_id = pthread_self();\n\n\t/* retrieve our lcore_id from the configuration structure */\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (thread_id == lcore_config[lcore_id].thread_id)\n\t\t\tbreak;\n\t}\n\tif (lcore_id == RTE_MAX_LCORE)\n\t\trte_panic(\"cannot retrieve lcore id\\n\");\n\n\tm2s = lcore_config[lcore_id].pipe_master2slave[0];\n\ts2m = lcore_config[lcore_id].pipe_slave2master[1];\n\n\t/* set the lcore ID in per-lcore memory area */\n\tRTE_PER_LCORE(_lcore_id) = lcore_id;\n\n\t/* set CPU affinity */\n\tif (eal_thread_set_affinity() < 0)\n\t\trte_panic(\"cannot set affinity\\n\");\n\n\tret = eal_thread_dump_affinity(cpuset, RTE_CPU_AFFINITY_STR_LEN);\n\n\tRTE_LOG(DEBUG, EAL, \"lcore %u is ready (tid=%p;cpuset=[%s%s])\\n\",\n\t\tlcore_id, thread_id, cpuset, ret == 0 ? \"\" : \"...\");\n\n\t/* read on our pipe to get commands */\n\twhile (1) {\n\t\tvoid *fct_arg;\n\n\t\t/* wait command */\n\t\tdo {\n\t\t\tn = read(m2s, &c, 1);\n\t\t} while (n < 0 && errno == EINTR);\n\n\t\tif (n <= 0)\n\t\t\trte_panic(\"cannot read on configuration pipe\\n\");\n\n\t\tlcore_config[lcore_id].state = RUNNING;\n\n\t\t/* send ack */\n\t\tn = 0;\n\t\twhile (n == 0 || (n < 0 && errno == EINTR))\n\t\t\tn = write(s2m, &c, 1);\n\t\tif (n < 0)\n\t\t\trte_panic(\"cannot write on configuration pipe\\n\");\n\n\t\tif (lcore_config[lcore_id].f == NULL)\n\t\t\trte_panic(\"NULL function pointer\\n\");\n\n\t\t/* call the function and store the return value */\n\t\tfct_arg = lcore_config[lcore_id].arg;\n\t\tret = lcore_config[lcore_id].f(fct_arg);\n\t\tlcore_config[lcore_id].ret = ret;\n\t\trte_wmb();\n\t\tlcore_config[lcore_id].state = FINISHED;\n\t}\n\n\t/* never reached */\n\t/* pthread_exit(NULL); */\n\t/* return NULL; */\n}\n\n/* require calling thread tid by gettid() */\nint rte_sys_gettid(void)\n{\n\tlong lwpid;\n\tthr_self(&lwpid);\n\treturn (int)lwpid;\n}\n" }, { "path": "lib/librte_eal/bsdapp/eal/eal_timer.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_internal_cfg.h\"\n\n#ifdef RTE_LIBEAL_USE_HPET\n#warning HPET is not supported in FreeBSD\n#endif\n\nenum timer_source eal_timer_source = EAL_TIMER_TSC;\n\nuint64_t\nget_tsc_freq(void)\n{\n\tsize_t sz;\n\tint tmp;\n\tuint64_t tsc_hz;\n\n\tsz = sizeof(tmp);\n\ttmp = 0;\n\n\tif (sysctlbyname(\"kern.timecounter.smp_tsc\", &tmp, &sz, NULL, 0))\n\t\tRTE_LOG(WARNING, EAL, \"%s\\n\", strerror(errno));\n\telse if (tmp != 1)\n\t\tRTE_LOG(WARNING, EAL, \"TSC is not safe to use in SMP mode\\n\");\n\n\ttmp = 0;\n\n\tif (sysctlbyname(\"kern.timecounter.invariant_tsc\", &tmp, &sz, NULL, 0))\n\t\tRTE_LOG(WARNING, EAL, \"%s\\n\", strerror(errno));\n\telse if (tmp != 1)\n\t\tRTE_LOG(WARNING, EAL, \"TSC is not invariant\\n\");\n\n\tsz = sizeof(tsc_hz);\n\tif (sysctlbyname(\"machdep.tsc_freq\", &tsc_hz, &sz, NULL, 0)) {\n\t\tRTE_LOG(WARNING, EAL, \"%s\\n\", strerror(errno));\n\t\treturn 0;\n\t}\n\n\treturn tsc_hz;\n}\n\nint\nrte_eal_timer_init(void)\n{\n\tset_tsc_freq();\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/bsdapp/eal/include/exec-env/rte_dom0_common.h", "content": "/*-\n * This file is provided under a dual BSD/LGPLv2 license. When using or\n * redistributing this file, you may do so under either license.\n *\n * GNU LESSER GENERAL PUBLIC LICENSE\n *\n * Copyright(c) 2007-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2.1 of the GNU Lesser General Public License\n * as published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * Lesser General Public License for more details.\n *\n * You should have received a copy of the GNU Lesser General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n *\n * Contact Information:\n * Intel Corporation\n *\n *\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n */\n\n#ifndef _RTE_DOM0_COMMON_H_\n#define _RTE_DOM0_COMMON_H_\n\n#ifdef __KERNEL__\n#include \n#endif\n\n#define DOM0_NAME_MAX 256\n#define DOM0_MM_DEV \"/dev/dom0_mm\"\n\n#define DOM0_CONTIG_NUM_ORDER 9 /**< 2M order */\n#define DOM0_NUM_MEMSEG 512 /**< Maximum nb. of memory segment. */\n#define DOM0_MEMBLOCK_SIZE 0x200000 /**< Maximum nb. of memory block(2M). */\n#define DOM0_CONFIG_MEMSIZE 4096 /**< Maximum config memory size(4G). */\n#define DOM0_NUM_MEMBLOCK (DOM0_CONFIG_MEMSIZE / 2) /**< Maximum nb. of 2M memory block. */\n\n#define RTE_DOM0_IOCTL_PREPARE_MEMSEG _IOWR(0, 1 , struct memory_info)\n#define RTE_DOM0_IOCTL_ATTACH_TO_MEMSEG _IOWR(0, 2 , char *)\n#define RTE_DOM0_IOCTL_GET_NUM_MEMSEG _IOWR(0, 3, int)\n#define RTE_DOM0_IOCTL_GET_MEMSEG_INFO _IOWR(0, 4, void *)\n\n/**\n * A structure used to store memory information.\n */\nstruct memory_info {\n\tchar name[DOM0_NAME_MAX];\n\tuint64_t size;\n};\n\n/**\n * A structure used to store memory segment information.\n */\nstruct memseg_info {\n\tuint32_t idx;\n\tuint64_t pfn;\n\tuint64_t size;\n\tuint64_t mfn[DOM0_NUM_MEMBLOCK];\n};\n\n/**\n * A structure used to store memory block information.\n */\nstruct memblock_info {\n\tuint8_t exchange_flag;\n\tuint64_t vir_addr;\n\tuint64_t pfn;\n\tuint64_t mfn;\n};\n#endif /* _RTE_DOM0_COMMON_H_ */\n" }, { "path": "lib/librte_eal/bsdapp/eal/include/exec-env/rte_interrupts.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_INTERRUPTS_H_\n#error \"don't include this file directly, please include generic \"\n#endif\n\n#ifndef _RTE_BSDAPP_INTERRUPTS_H_\n#define _RTE_BSDAPP_INTERRUPTS_H_\n\nenum rte_intr_handle_type {\n\tRTE_INTR_HANDLE_UNKNOWN = 0,\n\tRTE_INTR_HANDLE_UIO, /**< uio device handle */\n\tRTE_INTR_HANDLE_ALARM, /**< alarm handle */\n\tRTE_INTR_HANDLE_MAX\n};\n\n/** Handle for interrupts. */\nstruct rte_intr_handle {\n\tint fd; /**< file descriptor */\n\tint uio_cfg_fd; /**< UIO config file descriptor */\n\tenum rte_intr_handle_type type; /**< handle type */\n#ifdef RTE_NEXT_ABI\n\tint max_intr; /**< max interrupt requested */\n\tuint32_t nb_efd; /**< number of available efds */\n\tint *intr_vec; /**< intr vector number array */\n#endif\n};\n\n/**\n * @param intr_handle\n * Pointer to the interrupt handle.\n * @param epfd\n * Epoll instance fd which the intr vector associated to.\n * @param op\n * The operation be performed for the vector.\n * Operation type of {ADD, DEL}.\n * @param vec\n * RX intr vector number added to the epoll instance wait list.\n * @param data\n * User raw data.\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nint\nrte_intr_rx_ctl(struct rte_intr_handle *intr_handle,\n\t\tint epfd, int op, unsigned int vec, void *data);\n\n/**\n * It enables the fastpath event fds if it's necessary.\n * It creates event fds when multi-vectors allowed,\n * otherwise it multiplexes the single event fds.\n *\n * @param intr_handle\n * Pointer to the interrupt handle.\n * @param nb_vec\n * Number of interrupt vector trying to enable.\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nint\nrte_intr_efd_enable(struct rte_intr_handle *intr_handle, uint32_t nb_efd);\n\n/**\n * It disable the fastpath event fds.\n * It deletes registered eventfds and closes the open fds.\n *\n * @param intr_handle\n * Pointer to the interrupt handle.\n */\nvoid\nrte_intr_efd_disable(struct rte_intr_handle *intr_handle);\n\n/**\n * The fastpath interrupt is enabled or not.\n *\n * @param intr_handle\n * Pointer to the interrupt handle.\n */\nint rte_intr_dp_is_en(struct rte_intr_handle *intr_handle);\n\n/**\n * The interrupt handle instance allows other cause or not.\n * Other cause stands for none fastpath interrupt.\n *\n * @param intr_handle\n * Pointer to the interrupt handle.\n */\nint rte_intr_allow_others(struct rte_intr_handle *intr_handle);\n\n#endif /* _RTE_BSDAPP_INTERRUPTS_H_ */\n" }, { "path": "lib/librte_eal/bsdapp/nic_uio/BSDmakefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\nKMOD=\tnic_uio\nSRCS=\tnic_uio.c device_if.h bus_if.h pci_if.h\n\n.include \n" }, { "path": "lib/librte_eal/bsdapp/nic_uio/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# module name and path\n#\nMODULE = nic_uio\n\n#\n# CFLAGS\n#\nMODULE_CFLAGS += -I$(SRCDIR)\nMODULE_CFLAGS += -I$(RTE_OUTPUT)/include\nMODULE_CFLAGS += -Winline -Wall -Werror\nMODULE_CFLAGS += -include $(RTE_OUTPUT)/include/rte_config.h\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-y := nic_uio.c\n\ninclude $(RTE_SDK)/mk/rte.bsdmodule.mk\n" }, { "path": "lib/librte_eal/bsdapp/nic_uio/nic_uio.c", "content": "/* -\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n__FBSDID(\"$FreeBSD$\");\n\n#include /* defines used in kernel.h */\n#include \n#include /* types used in module initialization */\n#include /* cdevsw struct */\n#include /* structs, prototypes for pci bus stuff and DEVMETHOD */\n#include \n#include \n#include \n#include \n\n#include \n#include /* For pci_get macros! */\n#include /* The softc holds our per-instance data. */\n#include \n#include \n#include \n#include \n#include \n\n\n#define MAX_BARS (PCIR_MAX_BAR_0 + 1)\n\n#define MAX_DETACHED_DEVICES\t128\nstatic device_t detached_devices[MAX_DETACHED_DEVICES] = {};\nstatic int num_detached = 0;\n\nstruct nic_uio_softc {\n\tdevice_t dev_t;\n\tstruct cdev *my_cdev;\n\tint bar_id[MAX_BARS];\n\tstruct resource *bar_res[MAX_BARS];\n\tu_long bar_start[MAX_BARS];\n\tu_long bar_size[MAX_BARS];\n};\n\n/* Function prototypes */\nstatic d_open_t nic_uio_open;\nstatic d_close_t nic_uio_close;\nstatic d_mmap_t nic_uio_mmap;\nstatic d_mmap_single_t nic_uio_mmap_single;\nstatic int nic_uio_probe(device_t dev);\nstatic int nic_uio_attach(device_t dev);\nstatic int nic_uio_detach(device_t dev);\nstatic int nic_uio_shutdown(void);\nstatic int nic_uio_modevent(module_t mod, int type, void *arg);\n\nstatic struct cdevsw uio_cdevsw = {\n\t\t.d_name = \"nic_uio\",\n\t\t.d_version = D_VERSION,\n\t\t.d_open = nic_uio_open,\n\t\t.d_close = nic_uio_close,\n\t\t.d_mmap = nic_uio_mmap,\n\t\t.d_mmap_single = nic_uio_mmap_single,\n};\n\nstatic device_method_t nic_uio_methods[] = {\n\tDEVMETHOD(device_probe, nic_uio_probe),\n\tDEVMETHOD(device_attach, nic_uio_attach),\n\tDEVMETHOD(device_detach, nic_uio_detach),\n\tDEVMETHOD_END\n};\n\nstruct device {\n int vend;\n int dev;\n};\n\nstruct pci_bdf {\n\tuint32_t bus;\n\tuint32_t devid;\n\tuint32_t function;\n};\n\nstatic devclass_t nic_uio_devclass;\n\nDEFINE_CLASS_0(nic_uio, nic_uio_driver, nic_uio_methods, sizeof(struct nic_uio_softc));\nDRIVER_MODULE(nic_uio, pci, nic_uio_driver, nic_uio_devclass, nic_uio_modevent, 0);\n\nstatic int\nnic_uio_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr,\n\t\tint prot, vm_memattr_t *memattr)\n{\n\t*paddr = offset;\n\treturn 0;\n}\n\nstatic int\nnic_uio_mmap_single(struct cdev *cdev, vm_ooffset_t *offset, vm_size_t size,\n\t\tstruct vm_object **obj, int nprot)\n{\n\t/*\n\t * The BAR index is encoded in the offset. Divide the offset by\n\t * PAGE_SIZE to get the index of the bar requested by the user\n\t * app.\n\t */\n\tunsigned bar = *offset/PAGE_SIZE;\n\tstruct nic_uio_softc *sc = cdev->si_drv1;\n\n\tif (bar >= MAX_BARS)\n\t\treturn EINVAL;\n\n\tif (sc->bar_res[bar] == NULL) {\n\t\tsc->bar_id[bar] = PCIR_BAR(bar);\n\n\t\tif (PCI_BAR_IO(pci_read_config(sc->dev_t, sc->bar_id[bar], 4)))\n\t\t\tsc->bar_res[bar] = bus_alloc_resource_any(sc->dev_t, SYS_RES_IOPORT,\n\t\t\t\t\t&sc->bar_id[bar], RF_ACTIVE);\n\t\telse\n\t\t\tsc->bar_res[bar] = bus_alloc_resource_any(sc->dev_t, SYS_RES_MEMORY,\n\t\t\t\t\t&sc->bar_id[bar], RF_ACTIVE);\n\t}\n\tif (sc->bar_res[bar] == NULL)\n\t\treturn ENXIO;\n\n\tsc->bar_start[bar] = rman_get_start(sc->bar_res[bar]);\n\tsc->bar_size[bar] = rman_get_size(sc->bar_res[bar]);\n\n\tdevice_printf(sc->dev_t, \"Bar %u @ %lx, size %lx\\n\", bar,\n\t\t\tsc->bar_start[bar], sc->bar_size[bar]);\n\n\t*offset = sc->bar_start[bar];\n\t*obj = vm_pager_allocate(OBJT_DEVICE, cdev, size, nprot, *offset,\n\t\t\t\tcurthread->td_ucred);\n\treturn 0;\n}\n\n\nint\nnic_uio_open(struct cdev *dev, int oflags, int devtype, struct thread *td)\n{\n\treturn 0;\n}\n\nint\nnic_uio_close(struct cdev *dev, int fflag, int devtype, struct thread *td)\n{\n\treturn 0;\n}\n\nstatic int\nnic_uio_probe (device_t dev)\n{\n\tint i;\n\tunsigned int bus = pci_get_bus(dev);\n\tunsigned int device = pci_get_slot(dev);\n\tunsigned int function = pci_get_function(dev);\n\n\tfor (i = 0; i < num_detached; i++)\n\t\tif (bus == pci_get_bus(detached_devices[i]) &&\n\t\t device == pci_get_slot(detached_devices[i]) &&\n\t\t function == pci_get_function(detached_devices[i])) {\n\t\t\tdevice_set_desc(dev, \"DPDK PCI Device\");\n\t\t\treturn BUS_PROBE_SPECIFIC;\n\t\t}\n\n\treturn ENXIO;\n}\n\nstatic int\nnic_uio_attach(device_t dev)\n{\n\tint i;\n\tstruct nic_uio_softc *sc;\n\n\tsc = device_get_softc(dev);\n\tsc->dev_t = dev;\n\tsc->my_cdev = make_dev(&uio_cdevsw, device_get_unit(dev),\n\t\t\tUID_ROOT, GID_WHEEL, 0600, \"uio@pci:%u:%u:%u\",\n\t\t\tpci_get_bus(dev), pci_get_slot(dev), pci_get_function(dev));\n\tif (sc->my_cdev == NULL)\n\t\treturn ENXIO;\n\tsc->my_cdev->si_drv1 = sc;\n\n\tfor (i = 0; i < MAX_BARS; i++)\n\t\tsc->bar_res[i] = NULL;\n\n\tpci_enable_busmaster(dev);\n\n\treturn 0;\n}\n\nstatic int\nnic_uio_detach(device_t dev)\n{\n\tint i;\n\tstruct nic_uio_softc *sc;\n\tsc = device_get_softc(dev);\n\n\tfor (i = 0; i < MAX_BARS; i++)\n\t\tif (sc->bar_res[i] != NULL) {\n\n\t\t\tif (PCI_BAR_IO(pci_read_config(dev, sc->bar_id[i], 4)))\n\t\t\t\tbus_release_resource(dev, SYS_RES_IOPORT, sc->bar_id[i],\n\t\t\t\t\t\tsc->bar_res[i]);\n\t\t\telse\n\t\t\t\tbus_release_resource(dev, SYS_RES_MEMORY, sc->bar_id[i],\n\t\t\t\t\t\tsc->bar_res[i]);\n\t\t}\n\n\tif (sc->my_cdev != NULL)\n\t\tdestroy_dev(sc->my_cdev);\n\treturn 0;\n}\n\nstatic void\nnic_uio_load(void)\n{\n\tuint32_t bus, device, function;\n\tdevice_t dev;\n\tchar bdf_str[256];\n\tchar *token, *remaining;\n\n\tmemset(bdf_str, 0, sizeof(bdf_str));\n\tTUNABLE_STR_FETCH(\"hw.nic_uio.bdfs\", bdf_str, sizeof(bdf_str));\n\tremaining = bdf_str;\n\t/*\n\t * Users should specify PCI BDFs in the format \"b:d:f,b:d:f,b:d:f\".\n\t * But the code below does not try differentiate between : and ,\n\t * and just blindly uses 3 tokens at a time to construct a\n\t * bus/device/function tuple.\n\t *\n\t * There is no checking on strtol() return values, but this should\n\t * be OK. Worst case is it cannot convert and returns 0. This\n\t * could give us a different BDF than intended, but as long as the\n\t * PCI device/vendor ID does not match it will not matter.\n\t */\n\twhile (1) {\n\t\tif (remaining == NULL || remaining[0] == '\\0')\n\t\t\tbreak;\n\t\ttoken = strsep(&remaining, \",:\");\n\t\tif (token == NULL)\n\t\t\tbreak;\n\t\tbus = strtol(token, NULL, 10);\n\t\ttoken = strsep(&remaining, \",:\");\n\t\tif (token == NULL)\n\t\t\tbreak;\n\t\tdevice = strtol(token, NULL, 10);\n\t\ttoken = strsep(&remaining, \",:\");\n\t\tif (token == NULL)\n\t\t\tbreak;\n\t\tfunction = strtol(token, NULL, 10);\n\n\t\tdev = pci_find_bsf(bus, device, function);\n\t\tif (dev == NULL)\n\t\t\tcontinue;\n\n\t\tif (num_detached < MAX_DETACHED_DEVICES) {\n\t\t\tprintf(\"nic_uio_load: detaching and storing dev=%p\\n\",\n\t\t\t dev);\n\t\t\tdetached_devices[num_detached++] = dev;\n\t\t} else {\n\t\t\tprintf(\"nic_uio_load: reached MAX_DETACHED_DEVICES=%d. dev=%p won't be reattached\\n\",\n\t\t\t MAX_DETACHED_DEVICES, dev);\n\t\t}\n\t\tdevice_detach(dev);\n\t}\n}\n\nstatic void\nnic_uio_unload(void)\n{\n\tint i;\n\tprintf(\"nic_uio_unload: entered...\\n\");\n\n\tfor (i = 0; i < num_detached; i++) {\n\t\tprintf(\"nic_uio_unload: calling to device_probe_and_attach for dev=%p...\\n\",\n\t\t\tdetached_devices[i]);\n\t\tdevice_probe_and_attach(detached_devices[i]);\n\t\tprintf(\"nic_uio_unload: done.\\n\");\n\t}\n\n\tprintf(\"nic_uio_unload: leaving...\\n\");\n}\n\nstatic int\nnic_uio_shutdown(void)\n{\n\treturn 0;\n}\n\nstatic int\nnic_uio_modevent(module_t mod, int type, void *arg)\n{\n\n\tswitch (type) {\n\tcase MOD_LOAD:\n\t\tnic_uio_load();\n\t\tbreak;\n\tcase MOD_UNLOAD:\n\t\tnic_uio_unload();\n\t\tbreak;\n\tcase MOD_SHUTDOWN:\n\t\tnic_uio_shutdown();\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/common/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nINC := rte_branch_prediction.h rte_common.h\nINC += rte_debug.h rte_eal.h rte_errno.h rte_launch.h rte_lcore.h\nINC += rte_log.h rte_memory.h rte_memzone.h rte_pci.h\nINC += rte_pci_dev_ids.h rte_per_lcore.h rte_random.h\nINC += rte_tailq.h rte_interrupts.h rte_alarm.h\nINC += rte_string_fns.h rte_version.h\nINC += rte_eal_memconfig.h rte_malloc_heap.h\nINC += rte_hexdump.h rte_devargs.h rte_dev.h\nINC += rte_pci_dev_feature_defs.h rte_pci_dev_features.h\nINC += rte_malloc.h\n\nifeq ($(CONFIG_RTE_INSECURE_FUNCTION_WARNING),y)\nINC += rte_warnings.h\nendif\n\nGENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h\nGENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h\n# defined in mk/arch/$(RTE_ARCH)/rte.vars.mk\nARCH_DIR ?= $(RTE_ARCH)\nARCH_INC := $(notdir $(wildcard $(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h))\n\nSYMLINK-$(CONFIG_RTE_LIBRTE_EAL)-include := $(addprefix include/,$(INC))\nSYMLINK-$(CONFIG_RTE_LIBRTE_EAL)-include += \\\n\t$(addprefix include/arch/$(ARCH_DIR)/,$(ARCH_INC))\nSYMLINK-$(CONFIG_RTE_LIBRTE_EAL)-include/generic := \\\n\t$(addprefix include/generic/,$(GENERIC_INC))\n\ninclude $(RTE_SDK)/mk/rte.install.mk\n" }, { "path": "lib/librte_eal/common/eal_common_cpuflags.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n\n/*\n * This should prevent use of advanced instruction sets in this file. Otherwise\n * the check function itself could cause a crash.\n */\n#ifdef __INTEL_COMPILER\n#pragma optimize (\"\", off)\n#else\n#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)\n#if GCC_VERSION > 404000\n#pragma GCC optimize (\"O0\")\n#endif\n#endif\n\n/**\n * Checks if the machine is adequate for running the binary. If it is not, the\n * program exits with status 1.\n * The function attribute forces this function to be called before main(). But\n * with ICC, the check is generated by the compiler.\n */\n#ifndef __INTEL_COMPILER\nvoid __attribute__ ((__constructor__))\n#else\nvoid\n#endif\nrte_cpu_check_supported(void)\n{\n\t/* This is generated at compile-time by the build system */\n\tstatic const enum rte_cpu_flag_t compile_time_flags[] = {\n\t\t\tRTE_COMPILE_TIME_CPUFLAGS\n\t};\n\tunsigned count = RTE_DIM(compile_time_flags), i;\n\tint ret;\n\n\tfor (i = 0; i < count; i++) {\n\t\tret = rte_cpu_get_flag_enabled(compile_time_flags[i]);\n\n\t\tif (ret < 0) {\n\t\t\tfprintf(stderr,\n\t\t\t\t\"ERROR: CPU feature flag lookup failed with error %d\\n\",\n\t\t\t\tret);\n\t\t\texit(1);\n\t\t}\n\t\tif (!ret) {\n\t\t\tfprintf(stderr,\n\t\t\t \"ERROR: This system does not support \\\"%s\\\".\\n\"\n\t\t\t \"Please check that RTE_MACHINE is set correctly.\\n\",\n\t\t\t cpu_feature_table[compile_time_flags[i]].name);\n\t\t\texit(1);\n\t\t}\n\t}\n}\n" }, { "path": "lib/librte_eal/common/eal_common_dev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n\n/** Global list of device drivers. */\nstatic struct rte_driver_list dev_driver_list =\n\tTAILQ_HEAD_INITIALIZER(dev_driver_list);\n\n/* register a driver */\nvoid\nrte_eal_driver_register(struct rte_driver *driver)\n{\n\tTAILQ_INSERT_TAIL(&dev_driver_list, driver, next);\n}\n\n/* unregister a driver */\nvoid\nrte_eal_driver_unregister(struct rte_driver *driver)\n{\n\tTAILQ_REMOVE(&dev_driver_list, driver, next);\n}\n\nint\nrte_eal_vdev_init(const char *name, const char *args)\n{\n\tstruct rte_driver *driver;\n\n\tif (name == NULL)\n\t\treturn -EINVAL;\n\n\tTAILQ_FOREACH(driver, &dev_driver_list, next) {\n\t\tif (driver->type != PMD_VDEV)\n\t\t\tcontinue;\n\n\t\t/*\n\t\t * search a driver prefix in virtual device name.\n\t\t * For example, if the driver is pcap PMD, driver->name\n\t\t * will be \"eth_pcap\", but \"name\" will be \"eth_pcapN\".\n\t\t * So use strncmp to compare.\n\t\t */\n\t\tif (!strncmp(driver->name, name, strlen(driver->name)))\n\t\t\treturn driver->init(name, args);\n\t}\n\n\tRTE_LOG(ERR, EAL, \"no driver found for %s\\n\", name);\n\treturn -EINVAL;\n}\n\nint\nrte_eal_dev_init(void)\n{\n\tstruct rte_devargs *devargs;\n\tstruct rte_driver *driver;\n\n\t/*\n\t * Note that the dev_driver_list is populated here\n\t * from calls made to rte_eal_driver_register from constructor functions\n\t * embedded into PMD modules via the PMD_REGISTER_DRIVER macro\n\t */\n\n\t/* call the init function for each virtual device */\n\tTAILQ_FOREACH(devargs, &devargs_list, next) {\n\n\t\tif (devargs->type != RTE_DEVTYPE_VIRTUAL)\n\t\t\tcontinue;\n\n\t\tif (rte_eal_vdev_init(devargs->virtual.drv_name,\n\t\t\t\t\tdevargs->args)) {\n\t\t\tRTE_LOG(ERR, EAL, \"failed to initialize %s device\\n\",\n\t\t\t\t\tdevargs->virtual.drv_name);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* Once the vdevs are initalized, start calling all the pdev drivers */\n\tTAILQ_FOREACH(driver, &dev_driver_list, next) {\n\t\tif (driver->type != PMD_PDEV)\n\t\t\tcontinue;\n\t\t/* PDEV drivers don't get passed any parameters */\n\t\tdriver->init(NULL, NULL);\n\t}\n\treturn 0;\n}\n\nint\nrte_eal_vdev_uninit(const char *name)\n{\n\tstruct rte_driver *driver;\n\n\tif (name == NULL)\n\t\treturn -EINVAL;\n\n\tTAILQ_FOREACH(driver, &dev_driver_list, next) {\n\t\tif (driver->type != PMD_VDEV)\n\t\t\tcontinue;\n\n\t\t/*\n\t\t * search a driver prefix in virtual device name.\n\t\t * For example, if the driver is pcap PMD, driver->name\n\t\t * will be \"eth_pcap\", but \"name\" will be \"eth_pcapN\".\n\t\t * So use strncmp to compare.\n\t\t */\n\t\tif (!strncmp(driver->name, name, strlen(driver->name)))\n\t\t\treturn driver->uninit(name);\n\t}\n\n\tRTE_LOG(ERR, EAL, \"no driver found for %s\\n\", name);\n\treturn -EINVAL;\n}\n" }, { "path": "lib/librte_eal/common/eal_common_devargs.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright 2014 6WIND S.A.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A nor the names of its contributors\n * may be used to endorse or promote products derived from this\n * software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/* This file manages the list of devices and their arguments, as given\n * by the user at startup\n *\n * Code here should not call rte_log since the EAL environment\n * may not be initialized.\n */\n\n#include \n#include \n\n#include \n#include \n#include \"eal_private.h\"\n\n/** Global list of user devices */\nstruct rte_devargs_list devargs_list =\n\tTAILQ_HEAD_INITIALIZER(devargs_list);\n\nint\nrte_eal_parse_devargs_str(const char *devargs_str,\n\t\t\tchar **drvname, char **drvargs)\n{\n\tchar *sep;\n\n\tif ((devargs_str) == NULL || (drvname) == NULL || (drvargs == NULL))\n\t\treturn -1;\n\n\t*drvname = strdup(devargs_str);\n\tif (drvname == NULL)\n\t\treturn -1;\n\n\t/* set the first ',' to '\\0' to split name and arguments */\n\tsep = strchr(*drvname, ',');\n\tif (sep != NULL) {\n\t\tsep[0] = '\\0';\n\t\t*drvargs = strdup(sep + 1);\n\t} else {\n\t\t*drvargs = strdup(\"\");\n\t}\n\n\tif (*drvargs == NULL) {\n\t\tfree(*drvname);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/* store a whitelist parameter for later parsing */\nint\nrte_eal_devargs_add(enum rte_devtype devtype, const char *devargs_str)\n{\n\tstruct rte_devargs *devargs = NULL;\n\tchar *buf = NULL;\n\tint ret;\n\n\t/* use malloc instead of rte_malloc as it's called early at init */\n\tdevargs = malloc(sizeof(*devargs));\n\tif (devargs == NULL)\n\t\tgoto fail;\n\n\tmemset(devargs, 0, sizeof(*devargs));\n\tdevargs->type = devtype;\n\n\tif (rte_eal_parse_devargs_str(devargs_str, &buf, &devargs->args))\n\t\tgoto fail;\n\n\tswitch (devargs->type) {\n\tcase RTE_DEVTYPE_WHITELISTED_PCI:\n\tcase RTE_DEVTYPE_BLACKLISTED_PCI:\n\t\t/* try to parse pci identifier */\n\t\tif (eal_parse_pci_BDF(buf, &devargs->pci.addr) != 0 &&\n\t\t eal_parse_pci_DomBDF(buf, &devargs->pci.addr) != 0)\n\t\t\tgoto fail;\n\n\t\tbreak;\n\tcase RTE_DEVTYPE_VIRTUAL:\n\t\t/* save driver name */\n\t\tret = snprintf(devargs->virtual.drv_name,\n\t\t\t sizeof(devargs->virtual.drv_name), \"%s\", buf);\n\t\tif (ret < 0 || ret >= (int)sizeof(devargs->virtual.drv_name))\n\t\t\tgoto fail;\n\n\t\tbreak;\n\t}\n\n\tfree(buf);\n\tTAILQ_INSERT_TAIL(&devargs_list, devargs, next);\n\treturn 0;\n\nfail:\n\tif (buf)\n\t\tfree(buf);\n\tif (devargs) {\n\t\tfree(devargs->args);\n\t\tfree(devargs);\n\t}\n\n\treturn -1;\n}\n\n/* count the number of devices of a specified type */\nunsigned int\nrte_eal_devargs_type_count(enum rte_devtype devtype)\n{\n\tstruct rte_devargs *devargs;\n\tunsigned int count = 0;\n\n\tTAILQ_FOREACH(devargs, &devargs_list, next) {\n\t\tif (devargs->type != devtype)\n\t\t\tcontinue;\n\t\tcount++;\n\t}\n\treturn count;\n}\n\n/* dump the user devices on the console */\nvoid\nrte_eal_devargs_dump(FILE *f)\n{\n\tstruct rte_devargs *devargs;\n\n\tfprintf(f, \"User device white list:\\n\");\n\tTAILQ_FOREACH(devargs, &devargs_list, next) {\n\t\tif (devargs->type == RTE_DEVTYPE_WHITELISTED_PCI)\n\t\t\tfprintf(f, \" PCI whitelist \" PCI_PRI_FMT \" %s\\n\",\n\t\t\t devargs->pci.addr.domain,\n\t\t\t devargs->pci.addr.bus,\n\t\t\t devargs->pci.addr.devid,\n\t\t\t devargs->pci.addr.function,\n\t\t\t devargs->args);\n\t\telse if (devargs->type == RTE_DEVTYPE_BLACKLISTED_PCI)\n\t\t\tfprintf(f, \" PCI blacklist \" PCI_PRI_FMT \" %s\\n\",\n\t\t\t devargs->pci.addr.domain,\n\t\t\t devargs->pci.addr.bus,\n\t\t\t devargs->pci.addr.devid,\n\t\t\t devargs->pci.addr.function,\n\t\t\t devargs->args);\n\t\telse if (devargs->type == RTE_DEVTYPE_VIRTUAL)\n\t\t\tfprintf(f, \" VIRTUAL %s %s\\n\",\n\t\t\t devargs->virtual.drv_name,\n\t\t\t devargs->args);\n\t\telse\n\t\t\tfprintf(f, \" UNKNOWN %s\\n\", devargs->args);\n\t}\n}\n" }, { "path": "lib/librte_eal/common/eal_common_errno.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\nRTE_DEFINE_PER_LCORE(int, _rte_errno);\n\nconst char *\nrte_strerror(int errnum)\n{\n#define RETVAL_SZ 256\n\tstatic RTE_DEFINE_PER_LCORE(char[RETVAL_SZ], retval);\n\n\t/* since some implementations of strerror_r throw an error\n\t * themselves if errnum is too big, we handle that case here */\n\tif (errnum > RTE_MAX_ERRNO)\n\t\tsnprintf(RTE_PER_LCORE(retval), RETVAL_SZ,\n#ifdef RTE_EXEC_ENV_BSDAPP\n\t\t\t\t\"Unknown error: %d\", errnum);\n#else\n\t\t\t\t\"Unknown error %d\", errnum);\n#endif\n\telse\n\t\tswitch (errnum){\n\t\tcase E_RTE_SECONDARY:\n\t\t\treturn \"Invalid call in secondary process\";\n\t\tcase E_RTE_NO_CONFIG:\n\t\t\treturn \"Missing rte_config structure\";\n\t\tdefault:\n\t\t\tstrerror_r(errnum, RTE_PER_LCORE(retval), RETVAL_SZ);\n\t\t}\n\n\treturn RTE_PER_LCORE(retval);\n}\n" }, { "path": "lib/librte_eal/common/eal_common_hexdump.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n\n#define LINE_LEN 128\n\n/**************************************************************************//**\n*\n* rte_hexdump - Dump out memory in a special hex dump format.\n*\n* DESCRIPTION\n* Dump out the message buffer in a special hex dump output format with characters\n* printed for each line of 16 hex values.\n*\n* RETURNS: N/A\n*\n* SEE ALSO:\n*/\n\nvoid\nrte_hexdump(FILE *f, const char * title, const void * buf, unsigned int len)\n{\n unsigned int i, out, ofs;\n const unsigned char *data = buf;\n char line[LINE_LEN]; /* space needed 8+16*3+3+16 == 75 */\n\n fprintf(f, \"%s at [%p], len=%u\\n\", (title)? title : \" Dump data\", data, len);\n ofs = 0;\n while (ofs < len) {\n /* format the line in the buffer, then use printf to output to screen */\n out = snprintf(line, LINE_LEN, \"%08X:\", ofs);\n for (i = 0; ((ofs + i) < len) && (i < 16); i++)\n out += snprintf(line+out, LINE_LEN - out, \" %02X\", (data[ofs+i] & 0xff));\n for(; i <= 16; i++)\n out += snprintf(line+out, LINE_LEN - out, \" | \");\n for(i = 0; (ofs < len) && (i < 16); i++, ofs++) {\n unsigned char c = data[ofs];\n if ( (c < ' ') || (c > '~'))\n c = '.';\n out += snprintf(line+out, LINE_LEN - out, \"%c\", c);\n }\n fprintf(f, \"%s\\n\", line);\n }\n fflush(f);\n}\n\n/**************************************************************************//**\n*\n* rte_memdump - Dump out memory in hex bytes with colons.\n*\n* DESCRIPTION\n* Dump out the message buffer in hex bytes with colons xx:xx:xx:xx:...\n*\n* RETURNS: N/A\n*\n* SEE ALSO:\n*/\n\nvoid\nrte_memdump(FILE *f, const char * title, const void * buf, unsigned int len)\n{\n unsigned int i, out;\n const unsigned char *data = buf;\n char line[LINE_LEN];\n\n if ( title )\n\tfprintf(f, \"%s: \", title);\n\n line[0] = '\\0';\n for (i = 0, out = 0; i < len; i++) {\n\t// Make sure we do not overrun the line buffer length.\n\t\tif ( out >= (LINE_LEN - 4) ) {\n\t\t\tfprintf(f, \"%s\", line);\n\t\t\tout = 0;\n\t\t\tline[out] = '\\0';\n\t\t}\n\t\tout += snprintf(line+out, LINE_LEN - out, \"%02x%s\",\n\t\t\t\t(data[i] & 0xff), ((i+1) < len)? \":\" : \"\");\n }\n if ( out > 0 )\n\tfprintf(f, \"%s\", line);\n fprintf(f, \"\\n\");\n\n fflush(f);\n}\n" }, { "path": "lib/librte_eal/common/eal_common_launch.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/*\n * Wait until a lcore finished its job.\n */\nint\nrte_eal_wait_lcore(unsigned slave_id)\n{\n\tif (lcore_config[slave_id].state == WAIT)\n\t\treturn 0;\n\n\twhile (lcore_config[slave_id].state != WAIT &&\n\t lcore_config[slave_id].state != FINISHED);\n\n\trte_rmb();\n\n\t/* we are in finished state, go to wait state */\n\tlcore_config[slave_id].state = WAIT;\n\treturn lcore_config[slave_id].ret;\n}\n\n/*\n * Check that every SLAVE lcores are in WAIT state, then call\n * rte_eal_remote_launch() for all of them. If call_master is true\n * (set to CALL_MASTER), also call the function on the master lcore.\n */\nint\nrte_eal_mp_remote_launch(int (*f)(void *), void *arg,\n\t\t\t enum rte_rmt_call_master_t call_master)\n{\n\tint lcore_id;\n\tint master = rte_get_master_lcore();\n\n\t/* check state of lcores */\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (lcore_config[lcore_id].state != WAIT)\n\t\t\treturn -EBUSY;\n\t}\n\n\t/* send messages to cores */\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\trte_eal_remote_launch(f, arg, lcore_id);\n\t}\n\n\tif (call_master == CALL_MASTER) {\n\t\tlcore_config[master].ret = f(arg);\n\t\tlcore_config[master].state = FINISHED;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Return the state of the lcore identified by slave_id.\n */\nenum rte_lcore_state_t\nrte_eal_get_lcore_state(unsigned lcore_id)\n{\n\treturn lcore_config[lcore_id].state;\n}\n\n/*\n * Do a rte_eal_wait_lcore() for every lcore. The return values are\n * ignored.\n */\nvoid\nrte_eal_mp_wait_lcore(void)\n{\n\tunsigned lcore_id;\n\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\trte_eal_wait_lcore(lcore_id);\n\t}\n}\n" }, { "path": "lib/librte_eal/common/eal_common_lcore.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_thread.h\"\n\n/*\n * Parse /sys/devices/system/cpu to get the number of physical and logical\n * processors on the machine. The function will fill the cpu_info\n * structure.\n */\nint\nrte_eal_cpu_init(void)\n{\n\t/* pointer to global configuration */\n\tstruct rte_config *config = rte_eal_get_configuration();\n\tunsigned lcore_id;\n\tunsigned count = 0;\n\n\t/*\n\t * Parse the maximum set of logical cores, detect the subset of running\n\t * ones and enable them by default.\n\t */\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\t/* init cpuset for per lcore config */\n\t\tCPU_ZERO(&lcore_config[lcore_id].cpuset);\n\n\t\t/* in 1:1 mapping, record related cpu detected state */\n\t\tlcore_config[lcore_id].detected = eal_cpu_detected(lcore_id);\n\t\tif (lcore_config[lcore_id].detected == 0) {\n\t\t\tconfig->lcore_role[lcore_id] = ROLE_OFF;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* By default, lcore 1:1 map to cpu id */\n\t\tCPU_SET(lcore_id, &lcore_config[lcore_id].cpuset);\n\n\t\t/* By default, each detected core is enabled */\n\t\tconfig->lcore_role[lcore_id] = ROLE_RTE;\n\t\tlcore_config[lcore_id].core_id = eal_cpu_core_id(lcore_id);\n\t\tlcore_config[lcore_id].socket_id = eal_cpu_socket_id(lcore_id);\n\t\tif (lcore_config[lcore_id].socket_id >= RTE_MAX_NUMA_NODES)\n#ifdef RTE_EAL_ALLOW_INV_SOCKET_ID\n\t\t\tlcore_config[lcore_id].socket_id = 0;\n#else\n\t\t\trte_panic(\"Socket ID (%u) is greater than \"\n\t\t\t\t\"RTE_MAX_NUMA_NODES (%d)\\n\",\n\t\t\t\tlcore_config[lcore_id].socket_id,\n\t\t\t\tRTE_MAX_NUMA_NODES);\n#endif\n\n\t\tRTE_LOG(DEBUG, EAL, \"Detected lcore %u as \"\n\t\t\t\t\"core %u on socket %u\\n\",\n\t\t\t\tlcore_id, lcore_config[lcore_id].core_id,\n\t\t\t\tlcore_config[lcore_id].socket_id);\n\t\tcount++;\n\t}\n\t/* Set the count of enabled logical cores of the EAL configuration */\n\tconfig->lcore_count = count;\n\tRTE_LOG(DEBUG, EAL,\n\t\t\"Support maximum %u logical core(s) by configuration.\\n\",\n\t\tRTE_MAX_LCORE);\n\tRTE_LOG(DEBUG, EAL, \"Detected %u lcore(s)\\n\", config->lcore_count);\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/common/eal_common_log.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n\n#define LOG_ELT_SIZE 2048\n\n#define LOG_HISTORY_MP_NAME \"log_history\"\n\nSTAILQ_HEAD(log_history_list, log_history);\n\n/**\n * The structure of a message log in the log history.\n */\nstruct log_history {\n\tSTAILQ_ENTRY(log_history) next;\n\tunsigned size;\n\tchar buf[0];\n};\n\nstatic struct rte_mempool *log_history_mp = NULL;\nstatic unsigned log_history_size = 0;\nstatic struct log_history_list log_history;\n\n/* global log structure */\nstruct rte_logs rte_logs = {\n\t.type = ~0,\n\t.level = RTE_LOG_DEBUG,\n\t.file = NULL,\n};\n\nstatic rte_spinlock_t log_dump_lock = RTE_SPINLOCK_INITIALIZER;\nstatic rte_spinlock_t log_list_lock = RTE_SPINLOCK_INITIALIZER;\nstatic FILE *default_log_stream;\nstatic int history_enabled = 1;\n\n/**\n * This global structure stores some informations about the message\n * that is currently beeing processed by one lcore\n */\nstruct log_cur_msg {\n\tuint32_t loglevel; /**< log level - see rte_log.h */\n\tuint32_t logtype; /**< log type - see rte_log.h */\n} __rte_cache_aligned;\nstatic struct log_cur_msg log_cur_msg[RTE_MAX_LCORE]; /**< per core log */\n\n\n/* default logs */\n\nint\nrte_log_add_in_history(const char *buf, size_t size)\n{\n\tstruct log_history *hist_buf = NULL;\n\tstatic const unsigned hist_buf_size = LOG_ELT_SIZE - sizeof(*hist_buf);\n\tvoid *obj;\n\n\tif (history_enabled == 0)\n\t\treturn 0;\n\n\trte_spinlock_lock(&log_list_lock);\n\n\t/* get a buffer for adding in history */\n\tif (log_history_size > RTE_LOG_HISTORY) {\n\t\thist_buf = STAILQ_FIRST(&log_history);\n\t\tif (hist_buf) {\n\t\t\tSTAILQ_REMOVE_HEAD(&log_history, next);\n\t\t\tlog_history_size--;\n\t\t}\n\t}\n\telse {\n\t\tif (rte_mempool_mc_get(log_history_mp, &obj) < 0)\n\t\t\tobj = NULL;\n\t\thist_buf = obj;\n\t}\n\n\t/* no buffer */\n\tif (hist_buf == NULL) {\n\t\trte_spinlock_unlock(&log_list_lock);\n\t\treturn -ENOBUFS;\n\t}\n\n\t/* not enough room for msg, buffer go back in mempool */\n\tif (size >= hist_buf_size) {\n\t\trte_mempool_mp_put(log_history_mp, hist_buf);\n\t\trte_spinlock_unlock(&log_list_lock);\n\t\treturn -ENOBUFS;\n\t}\n\n\t/* add in history */\n\tmemcpy(hist_buf->buf, buf, size);\n\thist_buf->buf[size] = hist_buf->buf[hist_buf_size-1] = '\\0';\n\thist_buf->size = size;\n\tSTAILQ_INSERT_TAIL(&log_history, hist_buf, next);\n\tlog_history_size++;\n\trte_spinlock_unlock(&log_list_lock);\n\n\treturn 0;\n}\n\nvoid\nrte_log_set_history(int enable)\n{\n\thistory_enabled = enable;\n}\n\n/* Change the stream that will be used by logging system */\nint\nrte_openlog_stream(FILE *f)\n{\n\tif (f == NULL)\n\t\trte_logs.file = default_log_stream;\n\telse\n\t\trte_logs.file = f;\n\treturn 0;\n}\n\n/* Set global log level */\nvoid\nrte_set_log_level(uint32_t level)\n{\n\trte_logs.level = (uint32_t)level;\n}\n\n/* Get global log level */\nuint32_t\nrte_get_log_level(void)\n{\n\treturn rte_logs.level;\n}\n\n/* Set global log type */\nvoid\nrte_set_log_type(uint32_t type, int enable)\n{\n\tif (enable)\n\t\trte_logs.type |= type;\n\telse\n\t\trte_logs.type &= (~type);\n}\n\n/* Get global log type */\nuint32_t\nrte_get_log_type(void)\n{\n\treturn rte_logs.type;\n}\n\n/* get the current loglevel for the message beeing processed */\nint rte_log_cur_msg_loglevel(void)\n{\n\tunsigned lcore_id;\n\tlcore_id = rte_lcore_id();\n\tif (lcore_id >= RTE_MAX_LCORE)\n\t\treturn rte_get_log_level();\n\treturn log_cur_msg[lcore_id].loglevel;\n}\n\n/* get the current logtype for the message beeing processed */\nint rte_log_cur_msg_logtype(void)\n{\n\tunsigned lcore_id;\n\tlcore_id = rte_lcore_id();\n\tif (lcore_id >= RTE_MAX_LCORE)\n\t\treturn rte_get_log_type();\n\treturn log_cur_msg[lcore_id].logtype;\n}\n\n/* Dump log history to file */\nvoid\nrte_log_dump_history(FILE *out)\n{\n\tstruct log_history_list tmp_log_history;\n\tstruct log_history *hist_buf;\n\tunsigned i;\n\n\t/* only one dump at a time */\n\trte_spinlock_lock(&log_dump_lock);\n\n\t/* save list, and re-init to allow logging during dump */\n\trte_spinlock_lock(&log_list_lock);\n\ttmp_log_history = log_history;\n\tSTAILQ_INIT(&log_history);\n\tlog_history_size = 0;\n\trte_spinlock_unlock(&log_list_lock);\n\n\tfor (i=0; ibuf, hist_buf->size, 1, out) == 0) {\n\t\t\trte_mempool_mp_put(log_history_mp, hist_buf);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* put back message structure in pool */\n\t\trte_mempool_mp_put(log_history_mp, hist_buf);\n\t}\n\tfflush(out);\n\n\trte_spinlock_unlock(&log_dump_lock);\n}\n\n/*\n * Generates a log message The message will be sent in the stream\n * defined by the previous call to rte_openlog_stream().\n */\nint\nrte_vlog(uint32_t level, uint32_t logtype, const char *format, va_list ap)\n{\n\tint ret;\n\tFILE *f = rte_logs.file;\n\tunsigned lcore_id;\n\n\tif ((level > rte_logs.level) || !(logtype & rte_logs.type))\n\t\treturn 0;\n\n\t/* save loglevel and logtype in a global per-lcore variable */\n\tlcore_id = rte_lcore_id();\n\tif (lcore_id < RTE_MAX_LCORE) {\n\t\tlog_cur_msg[lcore_id].loglevel = level;\n\t\tlog_cur_msg[lcore_id].logtype = logtype;\n\t}\n\n\tret = vfprintf(f, format, ap);\n\tfflush(f);\n\treturn ret;\n}\n\n/*\n * Generates a log message The message will be sent in the stream\n * defined by the previous call to rte_openlog_stream().\n * No need to check level here, done by rte_vlog().\n */\nint\nrte_log(uint32_t level, uint32_t logtype, const char *format, ...)\n{\n\tva_list ap;\n\tint ret;\n\n\tva_start(ap, format);\n\tret = rte_vlog(level, logtype, format, ap);\n\tva_end(ap);\n\treturn ret;\n}\n\n/*\n * called by environment-specific log init function to initialize log\n * history\n */\nint\nrte_eal_common_log_init(FILE *default_log)\n{\n\tSTAILQ_INIT(&log_history);\n\n\t/* reserve RTE_LOG_HISTORY*2 elements, so we can dump and\n\t * keep logging during this time */\n\tlog_history_mp = rte_mempool_create(LOG_HISTORY_MP_NAME, RTE_LOG_HISTORY*2,\n\t\t\t\tLOG_ELT_SIZE, 0, 0,\n\t\t\t\tNULL, NULL,\n\t\t\t\tNULL, NULL,\n\t\t\t\tSOCKET_ID_ANY, 0);\n\n\tif ((log_history_mp == NULL) &&\n\t ((log_history_mp = rte_mempool_lookup(LOG_HISTORY_MP_NAME)) == NULL)){\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot create log_history mempool\\n\",\n\t\t\t__func__);\n\t\treturn -1;\n\t}\n\n\tdefault_log_stream = default_log;\n\trte_openlog_stream(default_log);\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/common/eal_common_memory.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_internal_cfg.h\"\n\n/*\n * Return a pointer to a read-only table of struct rte_physmem_desc\n * elements, containing the layout of all addressable physical\n * memory. The last element of the table contains a NULL address.\n */\nconst struct rte_memseg *\nrte_eal_get_physmem_layout(void)\n{\n\treturn rte_eal_get_configuration()->mem_config->memseg;\n}\n\n\n/* get the total size of memory */\nuint64_t\nrte_eal_get_physmem_size(void)\n{\n\tconst struct rte_mem_config *mcfg;\n\tunsigned i = 0;\n\tuint64_t total_len = 0;\n\n\t/* get pointer to global configuration */\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\tfor (i = 0; i < RTE_MAX_MEMSEG; i++) {\n\t\tif (mcfg->memseg[i].addr == NULL)\n\t\t\tbreak;\n\n\t\ttotal_len += mcfg->memseg[i].len;\n\t}\n\n\treturn total_len;\n}\n\n/* Dump the physical memory layout on console */\nvoid\nrte_dump_physmem_layout(FILE *f)\n{\n\tconst struct rte_mem_config *mcfg;\n\tunsigned i = 0;\n\n\t/* get pointer to global configuration */\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\tfor (i = 0; i < RTE_MAX_MEMSEG; i++) {\n\t\tif (mcfg->memseg[i].addr == NULL)\n\t\t\tbreak;\n\n\t\tfprintf(f, \"Segment %u: phys:0x%\"PRIx64\", len:%zu, \"\n\t\t \"virt:%p, socket_id:%\"PRId32\", \"\n\t\t \"hugepage_sz:%\"PRIu64\", nchannel:%\"PRIx32\", \"\n\t\t \"nrank:%\"PRIx32\"\\n\", i,\n\t\t mcfg->memseg[i].phys_addr,\n\t\t mcfg->memseg[i].len,\n\t\t mcfg->memseg[i].addr,\n\t\t mcfg->memseg[i].socket_id,\n\t\t mcfg->memseg[i].hugepage_sz,\n\t\t mcfg->memseg[i].nchannel,\n\t\t mcfg->memseg[i].nrank);\n\t}\n}\n\n/* return the number of memory channels */\nunsigned rte_memory_get_nchannel(void)\n{\n\treturn rte_eal_get_configuration()->mem_config->nchannel;\n}\n\n/* return the number of memory rank */\nunsigned rte_memory_get_nrank(void)\n{\n\treturn rte_eal_get_configuration()->mem_config->nrank;\n}\n\nstatic int\nrte_eal_memdevice_init(void)\n{\n\tstruct rte_config *config;\n\n\tif (rte_eal_process_type() == RTE_PROC_SECONDARY)\n\t\treturn 0;\n\n\tconfig = rte_eal_get_configuration();\n\tconfig->mem_config->nchannel = internal_config.force_nchannel;\n\tconfig->mem_config->nrank = internal_config.force_nrank;\n\n\treturn 0;\n}\n\n/* init memory subsystem */\nint\nrte_eal_memory_init(void)\n{\n\tRTE_LOG(INFO, EAL, \"Setting up physically contiguous memory...\\n\");\n\n\tconst int retval = rte_eal_process_type() == RTE_PROC_PRIMARY ?\n\t\t\trte_eal_hugepage_init() :\n\t\t\trte_eal_hugepage_attach();\n\tif (retval < 0)\n\t\treturn -1;\n\n\tif (internal_config.no_shconf == 0 && rte_eal_memdevice_init() < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/common/eal_common_memzone.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"malloc_heap.h\"\n#include \"malloc_elem.h\"\n#include \"eal_private.h\"\n\nstatic inline const struct rte_memzone *\nmemzone_lookup_thread_unsafe(const char *name)\n{\n\tconst struct rte_mem_config *mcfg;\n\tconst struct rte_memzone *mz;\n\tunsigned i = 0;\n\n\t/* get pointer to global configuration */\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\t/*\n\t * the algorithm is not optimal (linear), but there are few\n\t * zones and this function should be called at init only\n\t */\n\tfor (i = 0; i < RTE_MAX_MEMZONE; i++) {\n\t\tmz = &mcfg->memzone[i];\n\t\tif (mz->addr != NULL && !strncmp(name, mz->name, RTE_MEMZONE_NAMESIZE))\n\t\t\treturn &mcfg->memzone[i];\n\t}\n\n\treturn NULL;\n}\n\nstatic inline struct rte_memzone *\nget_next_free_memzone(void)\n{\n\tstruct rte_mem_config *mcfg;\n\tunsigned i = 0;\n\n\t/* get pointer to global configuration */\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\tfor (i = 0; i < RTE_MAX_MEMZONE; i++) {\n\t\tif (mcfg->memzone[i].addr == NULL)\n\t\t\treturn &mcfg->memzone[i];\n\t}\n\n\treturn NULL;\n}\n\n/* This function will return the greatest free block if a heap has been\n * specified. If no heap has been specified, it will return the heap and\n * length of the greatest free block available in all heaps */\nstatic size_t\nfind_heap_max_free_elem(int *s, unsigned align)\n{\n\tstruct rte_mem_config *mcfg;\n\tstruct rte_malloc_socket_stats stats;\n\tint i, socket = *s;\n\tsize_t len = 0;\n\n\t/* get pointer to global configuration */\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\tfor (i = 0; i < RTE_MAX_NUMA_NODES; i++) {\n\t\tif ((socket != SOCKET_ID_ANY) && (socket != i))\n\t\t\tcontinue;\n\n\t\tmalloc_heap_get_stats(&mcfg->malloc_heaps[i], &stats);\n\t\tif (stats.greatest_free_size > len) {\n\t\t\tlen = stats.greatest_free_size;\n\t\t\t*s = i;\n\t\t}\n\t}\n\n\treturn (len - MALLOC_ELEM_OVERHEAD - align);\n}\n\nstatic const struct rte_memzone *\nmemzone_reserve_aligned_thread_unsafe(const char *name, size_t len,\n\t\tint socket_id, unsigned flags, unsigned align, unsigned bound)\n{\n\tstruct rte_mem_config *mcfg;\n\tsize_t requested_len;\n\tint socket, i;\n\n\t/* get pointer to global configuration */\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\t/* no more room in config */\n\tif (mcfg->memzone_cnt >= RTE_MAX_MEMZONE) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): No more room in config\\n\", __func__);\n\t\trte_errno = ENOSPC;\n\t\treturn NULL;\n\t}\n\n\t/* zone already exist */\n\tif ((memzone_lookup_thread_unsafe(name)) != NULL) {\n\t\tRTE_LOG(DEBUG, EAL, \"%s(): memzone <%s> already exists\\n\",\n\t\t\t__func__, name);\n\t\trte_errno = EEXIST;\n\t\treturn NULL;\n\t}\n\n\t/* if alignment is not a power of two */\n\tif (align && !rte_is_power_of_2(align)) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): Invalid alignment: %u\\n\", __func__,\n\t\t\t\talign);\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\t/* alignment less than cache size is not allowed */\n\tif (align < RTE_CACHE_LINE_SIZE)\n\t\talign = RTE_CACHE_LINE_SIZE;\n\n\t/* align length on cache boundary. Check for overflow before doing so */\n\tif (len > SIZE_MAX - RTE_CACHE_LINE_MASK) {\n\t\trte_errno = EINVAL; /* requested size too big */\n\t\treturn NULL;\n\t}\n\n\tlen += RTE_CACHE_LINE_MASK;\n\tlen &= ~((size_t) RTE_CACHE_LINE_MASK);\n\n\t/* save minimal requested length */\n\trequested_len = RTE_MAX((size_t)RTE_CACHE_LINE_SIZE, len);\n\n\t/* check that boundary condition is valid */\n\tif (bound != 0 && (requested_len > bound || !rte_is_power_of_2(bound))) {\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\tif ((socket_id != SOCKET_ID_ANY) && (socket_id >= RTE_MAX_NUMA_NODES)) {\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\tif (!rte_eal_has_hugepages())\n\t\tsocket_id = SOCKET_ID_ANY;\n\n\tif (len == 0) {\n\t\tif (bound != 0)\n\t\t\trequested_len = bound;\n\t\telse\n\t\t\trequested_len = find_heap_max_free_elem(&socket_id, align);\n\t}\n\n\tif (socket_id == SOCKET_ID_ANY)\n\t\tsocket = malloc_get_numa_socket();\n\telse\n\t\tsocket = socket_id;\n\n\t/* allocate memory on heap */\n\tvoid *mz_addr = malloc_heap_alloc(&mcfg->malloc_heaps[socket], NULL,\n\t\t\trequested_len, flags, align, bound);\n\n\tif ((mz_addr == NULL) && (socket_id == SOCKET_ID_ANY)) {\n\t\t/* try other heaps */\n\t\tfor (i = 0; i < RTE_MAX_NUMA_NODES; i++) {\n\t\t\tif (socket == i)\n\t\t\t\tcontinue;\n\n\t\t\tmz_addr = malloc_heap_alloc(&mcfg->malloc_heaps[i],\n\t\t\t\t\tNULL, requested_len, flags, align, bound);\n\t\t\tif (mz_addr != NULL)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (mz_addr == NULL) {\n\t\trte_errno = ENOMEM;\n\t\treturn NULL;\n\t}\n\n\tconst struct malloc_elem *elem = malloc_elem_from_data(mz_addr);\n\n\t/* fill the zone in config */\n\tstruct rte_memzone *mz = get_next_free_memzone();\n\n\tif (mz == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): Cannot find free memzone but there is room \"\n\t\t\t\t\"in config!\\n\", __func__);\n\t\trte_errno = ENOSPC;\n\t\treturn NULL;\n\t}\n\n\tmcfg->memzone_cnt++;\n\tsnprintf(mz->name, sizeof(mz->name), \"%s\", name);\n\tmz->phys_addr = rte_malloc_virt2phy(mz_addr);\n\tmz->addr = mz_addr;\n\tmz->len = (requested_len == 0 ? elem->size : requested_len);\n\tmz->hugepage_sz = elem->ms->hugepage_sz;\n\tmz->socket_id = elem->ms->socket_id;\n\tmz->flags = 0;\n\tmz->memseg_id = elem->ms - rte_eal_get_configuration()->mem_config->memseg;\n\n\treturn mz;\n}\n\nstatic const struct rte_memzone *\nrte_memzone_reserve_thread_safe(const char *name, size_t len,\n\t\t\t\tint socket_id, unsigned flags, unsigned align,\n\t\t\t\tunsigned bound)\n{\n\tstruct rte_mem_config *mcfg;\n\tconst struct rte_memzone *mz = NULL;\n\n\t/* get pointer to global configuration */\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\trte_rwlock_write_lock(&mcfg->mlock);\n\n\tmz = memzone_reserve_aligned_thread_unsafe(\n\t\tname, len, socket_id, flags, align, bound);\n\n\trte_rwlock_write_unlock(&mcfg->mlock);\n\n\treturn mz;\n}\n\n/*\n * Return a pointer to a correctly filled memzone descriptor (with a\n * specified alignment and boundary). If the allocation cannot be done,\n * return NULL.\n */\nconst struct rte_memzone *\nrte_memzone_reserve_bounded(const char *name, size_t len, int socket_id,\n\t\t\t unsigned flags, unsigned align, unsigned bound)\n{\n\treturn rte_memzone_reserve_thread_safe(name, len, socket_id, flags,\n\t\t\t\t\t align, bound);\n}\n\n/*\n * Return a pointer to a correctly filled memzone descriptor (with a\n * specified alignment). If the allocation cannot be done, return NULL.\n */\nconst struct rte_memzone *\nrte_memzone_reserve_aligned(const char *name, size_t len, int socket_id,\n\t\t\t unsigned flags, unsigned align)\n{\n\treturn rte_memzone_reserve_thread_safe(name, len, socket_id, flags,\n\t\t\t\t\t align, 0);\n}\n\n/*\n * Return a pointer to a correctly filled memzone descriptor. If the\n * allocation cannot be done, return NULL.\n */\nconst struct rte_memzone *\nrte_memzone_reserve(const char *name, size_t len, int socket_id,\n\t\t unsigned flags)\n{\n\treturn rte_memzone_reserve_thread_safe(name, len, socket_id,\n\t\t\t\t\t flags, RTE_CACHE_LINE_SIZE, 0);\n}\n\nint\nrte_memzone_free(const struct rte_memzone *mz)\n{\n\tstruct rte_mem_config *mcfg;\n\tint ret = 0;\n\tvoid *addr;\n\tunsigned idx;\n\n\tif (mz == NULL)\n\t\treturn -EINVAL;\n\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\trte_rwlock_write_lock(&mcfg->mlock);\n\n\tidx = ((uintptr_t)mz - (uintptr_t)mcfg->memzone);\n\tidx = idx / sizeof(struct rte_memzone);\n\n\taddr = mcfg->memzone[idx].addr;\n#ifdef RTE_LIBRTE_IVSHMEM\n\t/*\n\t * If ioremap_addr is set, it's an IVSHMEM memzone and we cannot\n\t * free it.\n\t */\n\tif (mcfg->memzone[idx].ioremap_addr != 0)\n\t\tret = -EINVAL;\n#endif\n\tif (addr == NULL)\n\t\tret = -EINVAL;\n\telse if (mcfg->memzone_cnt == 0) {\n\t\trte_panic(\"%s(): memzone address not NULL but memzone_cnt is 0!\\n\",\n\t\t\t\t__func__);\n\t} else {\n\t\tmemset(&mcfg->memzone[idx], 0, sizeof(mcfg->memzone[idx]));\n\t\tmcfg->memzone_cnt--;\n\t}\n\n\trte_rwlock_write_unlock(&mcfg->mlock);\n\n\trte_free(addr);\n\n\treturn ret;\n}\n\n/*\n * Lookup for the memzone identified by the given name\n */\nconst struct rte_memzone *\nrte_memzone_lookup(const char *name)\n{\n\tstruct rte_mem_config *mcfg;\n\tconst struct rte_memzone *memzone = NULL;\n\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\trte_rwlock_read_lock(&mcfg->mlock);\n\n\tmemzone = memzone_lookup_thread_unsafe(name);\n\n\trte_rwlock_read_unlock(&mcfg->mlock);\n\n\treturn memzone;\n}\n\n/* Dump all reserved memory zones on console */\nvoid\nrte_memzone_dump(FILE *f)\n{\n\tstruct rte_mem_config *mcfg;\n\tunsigned i = 0;\n\n\t/* get pointer to global configuration */\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\trte_rwlock_read_lock(&mcfg->mlock);\n\t/* dump all zones */\n\tfor (i=0; imemzone[i].addr == NULL)\n\t\t\tbreak;\n\t\tfprintf(f, \"Zone %u: name:<%s>, phys:0x%\"PRIx64\", len:0x%zx\"\n\t\t \", virt:%p, socket_id:%\"PRId32\", flags:%\"PRIx32\"\\n\", i,\n\t\t mcfg->memzone[i].name,\n\t\t mcfg->memzone[i].phys_addr,\n\t\t mcfg->memzone[i].len,\n\t\t mcfg->memzone[i].addr,\n\t\t mcfg->memzone[i].socket_id,\n\t\t mcfg->memzone[i].flags);\n\t}\n\trte_rwlock_read_unlock(&mcfg->mlock);\n}\n\n/*\n * Init the memzone subsystem\n */\nint\nrte_eal_memzone_init(void)\n{\n\tstruct rte_mem_config *mcfg;\n\tconst struct rte_memseg *memseg;\n\n\t/* get pointer to global configuration */\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\t/* secondary processes don't need to initialise anything */\n\tif (rte_eal_process_type() == RTE_PROC_SECONDARY)\n\t\treturn 0;\n\n\tmemseg = rte_eal_get_physmem_layout();\n\tif (memseg == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): Cannot get physical layout\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\trte_rwlock_write_lock(&mcfg->mlock);\n\n\t/* delete all zones */\n\tmcfg->memzone_cnt = 0;\n\tmemset(mcfg->memzone, 0, sizeof(mcfg->memzone));\n\n\trte_rwlock_write_unlock(&mcfg->mlock);\n\n\treturn rte_eal_malloc_heap_init();\n}\n\n/* Walk all reserved memory zones */\nvoid rte_memzone_walk(void (*func)(const struct rte_memzone *, void *),\n\t\t void *arg)\n{\n\tstruct rte_mem_config *mcfg;\n\tunsigned i;\n\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\trte_rwlock_read_lock(&mcfg->mlock);\n\tfor (i=0; imemzone[i].addr != NULL)\n\t\t\t(*func)(&mcfg->memzone[i], arg);\n\t}\n\trte_rwlock_read_unlock(&mcfg->mlock);\n}\n" }, { "path": "lib/librte_eal/common/eal_common_options.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2014 6WIND S.A.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_internal_cfg.h\"\n#include \"eal_options.h\"\n#include \"eal_filesystem.h\"\n\n#define BITS_PER_HEX 4\n\nconst char\neal_short_options[] =\n\t\"b:\" /* pci-blacklist */\n\t\"c:\" /* coremask */\n\t\"d:\" /* driver */\n\t\"h\" /* help */\n\t\"l:\" /* corelist */\n\t\"m:\" /* memory size */\n\t\"n:\" /* memory channels */\n\t\"r:\" /* memory ranks */\n\t\"v\" /* version */\n\t\"w:\" /* pci-whitelist */\n\t;\n\nconst struct option\neal_long_options[] = {\n\t{OPT_BASE_VIRTADDR, 1, NULL, OPT_BASE_VIRTADDR_NUM },\n\t{OPT_CREATE_UIO_DEV, 0, NULL, OPT_CREATE_UIO_DEV_NUM },\n\t{OPT_FILE_PREFIX, 1, NULL, OPT_FILE_PREFIX_NUM },\n\t{OPT_HELP, 0, NULL, OPT_HELP_NUM },\n\t{OPT_HUGE_DIR, 1, NULL, OPT_HUGE_DIR_NUM },\n\t{OPT_LCORES, 1, NULL, OPT_LCORES_NUM },\n\t{OPT_LOG_LEVEL, 1, NULL, OPT_LOG_LEVEL_NUM },\n\t{OPT_MASTER_LCORE, 1, NULL, OPT_MASTER_LCORE_NUM },\n\t{OPT_NO_HPET, 0, NULL, OPT_NO_HPET_NUM },\n\t{OPT_NO_HUGE, 0, NULL, OPT_NO_HUGE_NUM },\n\t{OPT_NO_PCI, 0, NULL, OPT_NO_PCI_NUM },\n\t{OPT_NO_SHCONF, 0, NULL, OPT_NO_SHCONF_NUM },\n\t{OPT_PCI_BLACKLIST, 1, NULL, OPT_PCI_BLACKLIST_NUM },\n\t{OPT_PCI_WHITELIST, 1, NULL, OPT_PCI_WHITELIST_NUM },\n\t{OPT_PROC_TYPE, 1, NULL, OPT_PROC_TYPE_NUM },\n\t{OPT_SOCKET_MEM, 1, NULL, OPT_SOCKET_MEM_NUM },\n\t{OPT_SYSLOG, 1, NULL, OPT_SYSLOG_NUM },\n\t{OPT_VDEV, 1, NULL, OPT_VDEV_NUM },\n\t{OPT_VFIO_INTR, 1, NULL, OPT_VFIO_INTR_NUM },\n\t{OPT_VMWARE_TSC_MAP, 0, NULL, OPT_VMWARE_TSC_MAP_NUM },\n\t{OPT_XEN_DOM0, 0, NULL, OPT_XEN_DOM0_NUM },\n\t{0, 0, NULL, 0 }\n};\n\nstatic int lcores_parsed;\nstatic int master_lcore_parsed;\nstatic int mem_parsed;\n\nvoid\neal_reset_internal_config(struct internal_config *internal_cfg)\n{\n\tint i;\n\n\tinternal_cfg->memory = 0;\n\tinternal_cfg->force_nrank = 0;\n\tinternal_cfg->force_nchannel = 0;\n\tinternal_cfg->hugefile_prefix = HUGEFILE_PREFIX_DEFAULT;\n\tinternal_cfg->hugepage_dir = NULL;\n\tinternal_cfg->force_sockets = 0;\n\t/* zero out the NUMA config */\n\tfor (i = 0; i < RTE_MAX_NUMA_NODES; i++)\n\t\tinternal_cfg->socket_mem[i] = 0;\n\t/* zero out hugedir descriptors */\n\tfor (i = 0; i < MAX_HUGEPAGE_SIZES; i++)\n\t\tinternal_cfg->hugepage_info[i].lock_descriptor = -1;\n\tinternal_cfg->base_virtaddr = 0;\n\n\tinternal_cfg->syslog_facility = LOG_DAEMON;\n\t/* default value from build option */\n\tinternal_cfg->log_level = RTE_LOG_LEVEL;\n\n\tinternal_cfg->xen_dom0_support = 0;\n\n\t/* if set to NONE, interrupt mode is determined automatically */\n\tinternal_cfg->vfio_intr_mode = RTE_INTR_MODE_NONE;\n\n#ifdef RTE_LIBEAL_USE_HPET\n\tinternal_cfg->no_hpet = 0;\n#else\n\tinternal_cfg->no_hpet = 1;\n#endif\n\tinternal_cfg->vmware_tsc_map = 0;\n\tinternal_cfg->create_uio_dev = 0;\n}\n\n/*\n * Parse the coremask given as argument (hexadecimal string) and fill\n * the global configuration (core role and core count) with the parsed\n * value.\n */\nstatic int xdigit2val(unsigned char c)\n{\n\tint val;\n\n\tif (isdigit(c))\n\t\tval = c - '0';\n\telse if (isupper(c))\n\t\tval = c - 'A' + 10;\n\telse\n\t\tval = c - 'a' + 10;\n\treturn val;\n}\n\nstatic int\neal_parse_coremask(const char *coremask)\n{\n\tstruct rte_config *cfg = rte_eal_get_configuration();\n\tint i, j, idx = 0;\n\tunsigned count = 0;\n\tchar c;\n\tint val;\n\n\tif (coremask == NULL)\n\t\treturn -1;\n\t/* Remove all blank characters ahead and after .\n\t * Remove 0x/0X if exists.\n\t */\n\twhile (isblank(*coremask))\n\t\tcoremask++;\n\tif (coremask[0] == '0' && ((coremask[1] == 'x')\n\t\t|| (coremask[1] == 'X')))\n\t\tcoremask += 2;\n\ti = strlen(coremask);\n\twhile ((i > 0) && isblank(coremask[i - 1]))\n\t\ti--;\n\tif (i == 0)\n\t\treturn -1;\n\n\tfor (i = i - 1; i >= 0 && idx < RTE_MAX_LCORE; i--) {\n\t\tc = coremask[i];\n\t\tif (isxdigit(c) == 0) {\n\t\t\t/* invalid characters */\n\t\t\treturn -1;\n\t\t}\n\t\tval = xdigit2val(c);\n\t\tfor (j = 0; j < BITS_PER_HEX && idx < RTE_MAX_LCORE; j++, idx++)\n\t\t{\n\t\t\tif ((1 << j) & val) {\n\t\t\t\tif (!lcore_config[idx].detected) {\n\t\t\t\t\tRTE_LOG(ERR, EAL, \"lcore %u \"\n\t\t\t\t\t \"unavailable\\n\", idx);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t\tcfg->lcore_role[idx] = ROLE_RTE;\n\t\t\t\tlcore_config[idx].core_index = count;\n\t\t\t\tcount++;\n\t\t\t} else {\n\t\t\t\tcfg->lcore_role[idx] = ROLE_OFF;\n\t\t\t\tlcore_config[idx].core_index = -1;\n\t\t\t}\n\t\t}\n\t}\n\tfor (; i >= 0; i--)\n\t\tif (coremask[i] != '0')\n\t\t\treturn -1;\n\tfor (; idx < RTE_MAX_LCORE; idx++) {\n\t\tcfg->lcore_role[idx] = ROLE_OFF;\n\t\tlcore_config[idx].core_index = -1;\n\t}\n\tif (count == 0)\n\t\treturn -1;\n\t/* Update the count of enabled logical cores of the EAL configuration */\n\tcfg->lcore_count = count;\n\tlcores_parsed = 1;\n\treturn 0;\n}\n\nstatic int\neal_parse_corelist(const char *corelist)\n{\n\tstruct rte_config *cfg = rte_eal_get_configuration();\n\tint i, idx = 0;\n\tunsigned count = 0;\n\tchar *end = NULL;\n\tint min, max;\n\n\tif (corelist == NULL)\n\t\treturn -1;\n\n\t/* Remove all blank characters ahead and after */\n\twhile (isblank(*corelist))\n\t\tcorelist++;\n\ti = strlen(corelist);\n\twhile ((i > 0) && isblank(corelist[i - 1]))\n\t\ti--;\n\n\t/* Reset config */\n\tfor (idx = 0; idx < RTE_MAX_LCORE; idx++) {\n\t\tcfg->lcore_role[idx] = ROLE_OFF;\n\t\tlcore_config[idx].core_index = -1;\n\t}\n\n\t/* Get list of cores */\n\tmin = RTE_MAX_LCORE;\n\tdo {\n\t\twhile (isblank(*corelist))\n\t\t\tcorelist++;\n\t\tif (*corelist == '\\0')\n\t\t\treturn -1;\n\t\terrno = 0;\n\t\tidx = strtoul(corelist, &end, 10);\n\t\tif (errno || end == NULL)\n\t\t\treturn -1;\n\t\twhile (isblank(*end))\n\t\t\tend++;\n\t\tif (*end == '-') {\n\t\t\tmin = idx;\n\t\t} else if ((*end == ',') || (*end == '\\0')) {\n\t\t\tmax = idx;\n\t\t\tif (min == RTE_MAX_LCORE)\n\t\t\t\tmin = idx;\n\t\t\tfor (idx = min; idx <= max; idx++) {\n\t\t\t\tif (cfg->lcore_role[idx] != ROLE_RTE) {\n\t\t\t\t\tcfg->lcore_role[idx] = ROLE_RTE;\n\t\t\t\t\tlcore_config[idx].core_index = count;\n\t\t\t\t\tcount++;\n\t\t\t\t}\n\t\t\t}\n\t\t\tmin = RTE_MAX_LCORE;\n\t\t} else\n\t\t\treturn -1;\n\t\tcorelist = end + 1;\n\t} while (*end != '\\0');\n\n\tif (count == 0)\n\t\treturn -1;\n\n\t/* Update the count of enabled logical cores of the EAL configuration */\n\tcfg->lcore_count = count;\n\n\tlcores_parsed = 1;\n\treturn 0;\n}\n\n/* Changes the lcore id of the master thread */\nstatic int\neal_parse_master_lcore(const char *arg)\n{\n\tchar *parsing_end;\n\tstruct rte_config *cfg = rte_eal_get_configuration();\n\n\terrno = 0;\n\tcfg->master_lcore = (uint32_t) strtol(arg, &parsing_end, 0);\n\tif (errno || parsing_end[0] != 0)\n\t\treturn -1;\n\tif (cfg->master_lcore >= RTE_MAX_LCORE)\n\t\treturn -1;\n\tmaster_lcore_parsed = 1;\n\treturn 0;\n}\n\n/*\n * Parse elem, the elem could be single number/range or '(' ')' group\n * 1) A single number elem, it's just a simple digit. e.g. 9\n * 2) A single range elem, two digits with a '-' between. e.g. 2-6\n * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)\n * Within group elem, '-' used for a range separator;\n * ',' used for a single number.\n */\nstatic int\neal_parse_set(const char *input, uint16_t set[], unsigned num)\n{\n\tunsigned idx;\n\tconst char *str = input;\n\tchar *end = NULL;\n\tunsigned min, max;\n\n\tmemset(set, 0, num * sizeof(uint16_t));\n\n\twhile (isblank(*str))\n\t\tstr++;\n\n\t/* only digit or left bracket is qualify for start point */\n\tif ((!isdigit(*str) && *str != '(') || *str == '\\0')\n\t\treturn -1;\n\n\t/* process single number or single range of number */\n\tif (*str != '(') {\n\t\terrno = 0;\n\t\tidx = strtoul(str, &end, 10);\n\t\tif (errno || end == NULL || idx >= num)\n\t\t\treturn -1;\n\t\telse {\n\t\t\twhile (isblank(*end))\n\t\t\t\tend++;\n\n\t\t\tmin = idx;\n\t\t\tmax = idx;\n\t\t\tif (*end == '-') {\n\t\t\t\t/* process single - */\n\t\t\t\tend++;\n\t\t\t\twhile (isblank(*end))\n\t\t\t\t\tend++;\n\t\t\t\tif (!isdigit(*end))\n\t\t\t\t\treturn -1;\n\n\t\t\t\terrno = 0;\n\t\t\t\tidx = strtoul(end, &end, 10);\n\t\t\t\tif (errno || end == NULL || idx >= num)\n\t\t\t\t\treturn -1;\n\t\t\t\tmax = idx;\n\t\t\t\twhile (isblank(*end))\n\t\t\t\t\tend++;\n\t\t\t\tif (*end != ',' && *end != '\\0')\n\t\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tif (*end != ',' && *end != '\\0' &&\n\t\t\t *end != '@')\n\t\t\t\treturn -1;\n\n\t\t\tfor (idx = RTE_MIN(min, max);\n\t\t\t idx <= RTE_MAX(min, max); idx++)\n\t\t\t\tset[idx] = 1;\n\n\t\t\treturn end - input;\n\t\t}\n\t}\n\n\t/* process set within bracket */\n\tstr++;\n\twhile (isblank(*str))\n\t\tstr++;\n\tif (*str == '\\0')\n\t\treturn -1;\n\n\tmin = RTE_MAX_LCORE;\n\tdo {\n\n\t\t/* go ahead to the first digit */\n\t\twhile (isblank(*str))\n\t\t\tstr++;\n\t\tif (!isdigit(*str))\n\t\t\treturn -1;\n\n\t\t/* get the digit value */\n\t\terrno = 0;\n\t\tidx = strtoul(str, &end, 10);\n\t\tif (errno || end == NULL || idx >= num)\n\t\t\treturn -1;\n\n\t\t/* go ahead to separator '-',',' and ')' */\n\t\twhile (isblank(*end))\n\t\t\tend++;\n\t\tif (*end == '-') {\n\t\t\tif (min == RTE_MAX_LCORE)\n\t\t\t\tmin = idx;\n\t\t\telse /* avoid continuous '-' */\n\t\t\t\treturn -1;\n\t\t} else if ((*end == ',') || (*end == ')')) {\n\t\t\tmax = idx;\n\t\t\tif (min == RTE_MAX_LCORE)\n\t\t\t\tmin = idx;\n\t\t\tfor (idx = RTE_MIN(min, max);\n\t\t\t idx <= RTE_MAX(min, max); idx++)\n\t\t\t\tset[idx] = 1;\n\n\t\t\tmin = RTE_MAX_LCORE;\n\t\t} else\n\t\t\treturn -1;\n\n\t\tstr = end + 1;\n\t} while (*end != '\\0' && *end != ')');\n\n\treturn str - input;\n}\n\n/* convert from set array to cpuset bitmap */\nstatic int\nconvert_to_cpuset(rte_cpuset_t *cpusetp,\n\t uint16_t *set, unsigned num)\n{\n\tunsigned idx;\n\n\tCPU_ZERO(cpusetp);\n\n\tfor (idx = 0; idx < num; idx++) {\n\t\tif (!set[idx])\n\t\t\tcontinue;\n\n\t\tif (!lcore_config[idx].detected) {\n\t\t\tRTE_LOG(ERR, EAL, \"core %u \"\n\t\t\t\t\"unavailable\\n\", idx);\n\t\t\treturn -1;\n\t\t}\n\n\t\tCPU_SET(idx, cpusetp);\n\t}\n\n\treturn 0;\n}\n\n/*\n * The format pattern: --lcores='[<,lcores[@cpus]>...]'\n * lcores, cpus could be a single digit/range or a group.\n * '(' and ')' are necessary if it's a group.\n * If not supply '@cpus', the value of cpus uses the same as lcores.\n * e.g. '1,2@(5-7),(3-5)@(0,2),(0,6),7-8' means start 9 EAL thread as below\n * lcore 0 runs on cpuset 0x41 (cpu 0,6)\n * lcore 1 runs on cpuset 0x2 (cpu 1)\n * lcore 2 runs on cpuset 0xe0 (cpu 5,6,7)\n * lcore 3,4,5 runs on cpuset 0x5 (cpu 0,2)\n * lcore 6 runs on cpuset 0x41 (cpu 0,6)\n * lcore 7 runs on cpuset 0x80 (cpu 7)\n * lcore 8 runs on cpuset 0x100 (cpu 8)\n */\nstatic int\neal_parse_lcores(const char *lcores)\n{\n\tstruct rte_config *cfg = rte_eal_get_configuration();\n\tstatic uint16_t set[RTE_MAX_LCORE];\n\tunsigned idx = 0;\n\tint i;\n\tunsigned count = 0;\n\tconst char *lcore_start = NULL;\n\tconst char *end = NULL;\n\tint offset;\n\trte_cpuset_t cpuset;\n\tint lflags = 0;\n\tint ret = -1;\n\n\tif (lcores == NULL)\n\t\treturn -1;\n\n\t/* Remove all blank characters ahead and after */\n\twhile (isblank(*lcores))\n\t\tlcores++;\n\ti = strlen(lcores);\n\twhile ((i > 0) && isblank(lcores[i - 1]))\n\t\ti--;\n\n\tCPU_ZERO(&cpuset);\n\n\t/* Reset lcore config */\n\tfor (idx = 0; idx < RTE_MAX_LCORE; idx++) {\n\t\tcfg->lcore_role[idx] = ROLE_OFF;\n\t\tlcore_config[idx].core_index = -1;\n\t\tCPU_ZERO(&lcore_config[idx].cpuset);\n\t}\n\n\t/* Get list of cores */\n\tdo {\n\t\twhile (isblank(*lcores))\n\t\t\tlcores++;\n\t\tif (*lcores == '\\0')\n\t\t\tgoto err;\n\n\t\t/* record lcore_set start point */\n\t\tlcore_start = lcores;\n\n\t\t/* go across a complete bracket */\n\t\tif (*lcore_start == '(') {\n\t\t\tlcores += strcspn(lcores, \")\");\n\t\t\tif (*lcores++ == '\\0')\n\t\t\t\tgoto err;\n\t\t}\n\n\t\t/* scan the separator '@', ','(next) or '\\0'(finish) */\n\t\tlcores += strcspn(lcores, \"@,\");\n\n\t\tif (*lcores == '@') {\n\t\t\t/* explicit assign cpu_set */\n\t\t\toffset = eal_parse_set(lcores + 1, set, RTE_DIM(set));\n\t\t\tif (offset < 0)\n\t\t\t\tgoto err;\n\n\t\t\t/* prepare cpu_set and update the end cursor */\n\t\t\tif (0 > convert_to_cpuset(&cpuset,\n\t\t\t\t\t\t set, RTE_DIM(set)))\n\t\t\t\tgoto err;\n\t\t\tend = lcores + 1 + offset;\n\t\t} else { /* ',' or '\\0' */\n\t\t\t/* haven't given cpu_set, current loop done */\n\t\t\tend = lcores;\n\n\t\t\t/* go back to check - */\n\t\t\toffset = strcspn(lcore_start, \"(-\");\n\t\t\tif (offset < (end - lcore_start) &&\n\t\t\t *(lcore_start + offset) != '(')\n\t\t\t\tlflags = 1;\n\t\t}\n\n\t\tif (*end != ',' && *end != '\\0')\n\t\t\tgoto err;\n\n\t\t/* parse lcore_set from start point */\n\t\tif (0 > eal_parse_set(lcore_start, set, RTE_DIM(set)))\n\t\t\tgoto err;\n\n\t\t/* without '@', by default using lcore_set as cpu_set */\n\t\tif (*lcores != '@' &&\n\t\t 0 > convert_to_cpuset(&cpuset, set, RTE_DIM(set)))\n\t\t\tgoto err;\n\n\t\t/* start to update lcore_set */\n\t\tfor (idx = 0; idx < RTE_MAX_LCORE; idx++) {\n\t\t\tif (!set[idx])\n\t\t\t\tcontinue;\n\n\t\t\tif (cfg->lcore_role[idx] != ROLE_RTE) {\n\t\t\t\tlcore_config[idx].core_index = count;\n\t\t\t\tcfg->lcore_role[idx] = ROLE_RTE;\n\t\t\t\tcount++;\n\t\t\t}\n\n\t\t\tif (lflags) {\n\t\t\t\tCPU_ZERO(&cpuset);\n\t\t\t\tCPU_SET(idx, &cpuset);\n\t\t\t}\n\t\t\trte_memcpy(&lcore_config[idx].cpuset, &cpuset,\n\t\t\t\t sizeof(rte_cpuset_t));\n\t\t}\n\n\t\tlcores = end + 1;\n\t} while (*end != '\\0');\n\n\tif (count == 0)\n\t\tgoto err;\n\n\tcfg->lcore_count = count;\n\tlcores_parsed = 1;\n\tret = 0;\n\nerr:\n\n\treturn ret;\n}\n\nstatic int\neal_parse_syslog(const char *facility, struct internal_config *conf)\n{\n\tint i;\n\tstatic struct {\n\t\tconst char *name;\n\t\tint value;\n\t} map[] = {\n\t\t{ \"auth\", LOG_AUTH },\n\t\t{ \"cron\", LOG_CRON },\n\t\t{ \"daemon\", LOG_DAEMON },\n\t\t{ \"ftp\", LOG_FTP },\n\t\t{ \"kern\", LOG_KERN },\n\t\t{ \"lpr\", LOG_LPR },\n\t\t{ \"mail\", LOG_MAIL },\n\t\t{ \"news\", LOG_NEWS },\n\t\t{ \"syslog\", LOG_SYSLOG },\n\t\t{ \"user\", LOG_USER },\n\t\t{ \"uucp\", LOG_UUCP },\n\t\t{ \"local0\", LOG_LOCAL0 },\n\t\t{ \"local1\", LOG_LOCAL1 },\n\t\t{ \"local2\", LOG_LOCAL2 },\n\t\t{ \"local3\", LOG_LOCAL3 },\n\t\t{ \"local4\", LOG_LOCAL4 },\n\t\t{ \"local5\", LOG_LOCAL5 },\n\t\t{ \"local6\", LOG_LOCAL6 },\n\t\t{ \"local7\", LOG_LOCAL7 },\n\t\t{ NULL, 0 }\n\t};\n\n\tfor (i = 0; map[i].name; i++) {\n\t\tif (!strcmp(facility, map[i].name)) {\n\t\t\tconf->syslog_facility = map[i].value;\n\t\t\treturn 0;\n\t\t}\n\t}\n\treturn -1;\n}\n\nstatic int\neal_parse_log_level(const char *level, uint32_t *log_level)\n{\n\tchar *end;\n\tunsigned long tmp;\n\n\terrno = 0;\n\ttmp = strtoul(level, &end, 0);\n\n\t/* check for errors */\n\tif ((errno != 0) || (level[0] == '\\0') ||\n\t end == NULL || (*end != '\\0'))\n\t\treturn -1;\n\n\t/* log_level is a uint32_t */\n\tif (tmp >= UINT32_MAX)\n\t\treturn -1;\n\n\t*log_level = tmp;\n\treturn 0;\n}\n\nstatic enum rte_proc_type_t\neal_parse_proc_type(const char *arg)\n{\n\tif (strncasecmp(arg, \"primary\", sizeof(\"primary\")) == 0)\n\t\treturn RTE_PROC_PRIMARY;\n\tif (strncasecmp(arg, \"secondary\", sizeof(\"secondary\")) == 0)\n\t\treturn RTE_PROC_SECONDARY;\n\tif (strncasecmp(arg, \"auto\", sizeof(\"auto\")) == 0)\n\t\treturn RTE_PROC_AUTO;\n\n\treturn RTE_PROC_INVALID;\n}\n\nint\neal_parse_common_option(int opt, const char *optarg,\n\t\t\tstruct internal_config *conf)\n{\n\tswitch (opt) {\n\t/* blacklist */\n\tcase 'b':\n\t\tif (rte_eal_devargs_add(RTE_DEVTYPE_BLACKLISTED_PCI,\n\t\t\t\toptarg) < 0) {\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\t/* whitelist */\n\tcase 'w':\n\t\tif (rte_eal_devargs_add(RTE_DEVTYPE_WHITELISTED_PCI,\n\t\t\t\toptarg) < 0) {\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\t/* coremask */\n\tcase 'c':\n\t\tif (eal_parse_coremask(optarg) < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"invalid coremask\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\t/* corelist */\n\tcase 'l':\n\t\tif (eal_parse_corelist(optarg) < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"invalid core list\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\t/* size of memory */\n\tcase 'm':\n\t\tconf->memory = atoi(optarg);\n\t\tconf->memory *= 1024ULL;\n\t\tconf->memory *= 1024ULL;\n\t\tmem_parsed = 1;\n\t\tbreak;\n\t/* force number of channels */\n\tcase 'n':\n\t\tconf->force_nchannel = atoi(optarg);\n\t\tif (conf->force_nchannel == 0 ||\n\t\t conf->force_nchannel > 4) {\n\t\t\tRTE_LOG(ERR, EAL, \"invalid channel number\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\t/* force number of ranks */\n\tcase 'r':\n\t\tconf->force_nrank = atoi(optarg);\n\t\tif (conf->force_nrank == 0 ||\n\t\t conf->force_nrank > 16) {\n\t\t\tRTE_LOG(ERR, EAL, \"invalid rank number\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\tcase 'v':\n\t\t/* since message is explicitly requested by user, we\n\t\t * write message at highest log level so it can always\n\t\t * be seen\n\t\t * even if info or warning messages are disabled */\n\t\tRTE_LOG(CRIT, EAL, \"RTE Version: '%s'\\n\", rte_version());\n\t\tbreak;\n\n\t/* long options */\n\tcase OPT_NO_HUGE_NUM:\n\t\tconf->no_hugetlbfs = 1;\n\t\tbreak;\n\n\tcase OPT_NO_PCI_NUM:\n\t\tconf->no_pci = 1;\n\t\tbreak;\n\n\tcase OPT_NO_HPET_NUM:\n\t\tconf->no_hpet = 1;\n\t\tbreak;\n\n\tcase OPT_VMWARE_TSC_MAP_NUM:\n\t\tconf->vmware_tsc_map = 1;\n\t\tbreak;\n\n\tcase OPT_NO_SHCONF_NUM:\n\t\tconf->no_shconf = 1;\n\t\tbreak;\n\n\tcase OPT_PROC_TYPE_NUM:\n\t\tconf->process_type = eal_parse_proc_type(optarg);\n\t\tbreak;\n\n\tcase OPT_MASTER_LCORE_NUM:\n\t\tif (eal_parse_master_lcore(optarg) < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"invalid parameter for --\"\n\t\t\t\t\tOPT_MASTER_LCORE \"\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\n\tcase OPT_VDEV_NUM:\n\t\tif (rte_eal_devargs_add(RTE_DEVTYPE_VIRTUAL,\n\t\t\t\toptarg) < 0) {\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\n\tcase OPT_SYSLOG_NUM:\n\t\tif (eal_parse_syslog(optarg, conf) < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"invalid parameters for --\"\n\t\t\t\t\tOPT_SYSLOG \"\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\n\tcase OPT_LOG_LEVEL_NUM: {\n\t\tuint32_t log;\n\n\t\tif (eal_parse_log_level(optarg, &log) < 0) {\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\"invalid parameters for --\"\n\t\t\t\tOPT_LOG_LEVEL \"\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tconf->log_level = log;\n\t\tbreak;\n\t}\n\tcase OPT_LCORES_NUM:\n\t\tif (eal_parse_lcores(optarg) < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"invalid parameter for --\"\n\t\t\t\tOPT_LCORES \"\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tbreak;\n\n\t/* don't know what to do, leave this to caller */\n\tdefault:\n\t\treturn 1;\n\n\t}\n\n\treturn 0;\n}\n\nint\neal_adjust_config(struct internal_config *internal_cfg)\n{\n\tint i;\n\tstruct rte_config *cfg = rte_eal_get_configuration();\n\n\tif (internal_config.process_type == RTE_PROC_AUTO)\n\t\tinternal_config.process_type = eal_proc_type_detect();\n\n\t/* default master lcore is the first one */\n\tif (!master_lcore_parsed)\n\t\tcfg->master_lcore = rte_get_next_lcore(-1, 0, 0);\n\n\t/* if no memory amounts were requested, this will result in 0 and\n\t * will be overridden later, right after eal_hugepage_info_init() */\n\tfor (i = 0; i < RTE_MAX_NUMA_NODES; i++)\n\t\tinternal_cfg->memory += internal_cfg->socket_mem[i];\n\n\treturn 0;\n}\n\nint\neal_check_common_options(struct internal_config *internal_cfg)\n{\n\tstruct rte_config *cfg = rte_eal_get_configuration();\n\n\tif (!lcores_parsed) {\n\t\tRTE_LOG(ERR, EAL, \"CPU cores must be enabled with options \"\n\t\t\t\"-c, -l or --lcores\\n\");\n\t\treturn -1;\n\t}\n\tif (cfg->lcore_role[cfg->master_lcore] != ROLE_RTE) {\n\t\tRTE_LOG(ERR, EAL, \"Master lcore is not enabled for DPDK\\n\");\n\t\treturn -1;\n\t}\n\n\tif (internal_cfg->process_type == RTE_PROC_INVALID) {\n\t\tRTE_LOG(ERR, EAL, \"Invalid process type specified\\n\");\n\t\treturn -1;\n\t}\n\tif (internal_cfg->process_type == RTE_PROC_PRIMARY &&\n\t\t\tinternal_cfg->force_nchannel == 0) {\n\t\tRTE_LOG(ERR, EAL, \"Number of memory channels (-n) not \"\n\t\t\t\"specified\\n\");\n\t\treturn -1;\n\t}\n\tif (index(internal_cfg->hugefile_prefix, '%') != NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Invalid char, '%%', in --\"OPT_FILE_PREFIX\" \"\n\t\t\t\"option\\n\");\n\t\treturn -1;\n\t}\n\tif (mem_parsed && internal_cfg->force_sockets == 1) {\n\t\tRTE_LOG(ERR, EAL, \"Options -m and --\"OPT_SOCKET_MEM\" cannot \"\n\t\t\t\"be specified at the same time\\n\");\n\t\treturn -1;\n\t}\n\tif (internal_cfg->no_hugetlbfs && internal_cfg->force_sockets == 1) {\n\t\tRTE_LOG(ERR, EAL, \"Option --\"OPT_SOCKET_MEM\" cannot \"\n\t\t\t\"be specified together with --\"OPT_NO_HUGE\"\\n\");\n\t\treturn -1;\n\t}\n\n\tif (rte_eal_devargs_type_count(RTE_DEVTYPE_WHITELISTED_PCI) != 0 &&\n\t\trte_eal_devargs_type_count(RTE_DEVTYPE_BLACKLISTED_PCI) != 0) {\n\t\tRTE_LOG(ERR, EAL, \"Options blacklist (-b) and whitelist (-w) \"\n\t\t\t\"cannot be used at the same time\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nvoid\neal_common_usage(void)\n{\n\tprintf(\"-c COREMASK|-l CORELIST -n CHANNELS [options]\\n\\n\"\n\t \"EAL common options:\\n\"\n\t \" -c COREMASK Hexadecimal bitmask of cores to run on\\n\"\n\t \" -l CORELIST List of cores to run on\\n\"\n\t \" The argument format is [-c2][,c3[-c4],...]\\n\"\n\t \" where c1, c2, etc are core indexes between 0 and %d\\n\"\n\t \" --\"OPT_LCORES\" COREMAP Map lcore set to physical cpu set\\n\"\n\t \" The argument format is\\n\"\n\t \" '[<,lcores[@cpus]>...]'\\n\"\n\t \" lcores and cpus list are grouped by '(' and ')'\\n\"\n\t \" Within the group, '-' is used for range separator,\\n\"\n\t \" ',' is used for single number separator.\\n\"\n\t \" '( )' can be omitted for single element group,\\n\"\n\t \" '@' can be omitted if cpus and lcores have the same value\\n\"\n\t \" --\"OPT_MASTER_LCORE\" ID Core ID that is used as master\\n\"\n\t \" -n CHANNELS Number of memory channels\\n\"\n\t \" -m MB Memory to allocate (see also --\"OPT_SOCKET_MEM\")\\n\"\n\t \" -r RANKS Force number of memory ranks (don't detect)\\n\"\n\t \" -b, --\"OPT_PCI_BLACKLIST\" Add a PCI device in black list.\\n\"\n\t \" Prevent EAL from using this PCI device. The argument\\n\"\n\t \" format is .\\n\"\n\t \" -w, --\"OPT_PCI_WHITELIST\" Add a PCI device in white list.\\n\"\n\t \" Only use the specified PCI devices. The argument format\\n\"\n\t \" is <[domain:]bus:devid.func>. This option can be present\\n\"\n\t \" several times (once per device).\\n\"\n\t \" [NOTE: PCI whitelist cannot be used with -b option]\\n\"\n\t \" --\"OPT_VDEV\" Add a virtual device.\\n\"\n\t \" The argument format is [,key=val,...]\\n\"\n\t \" (ex: --vdev=eth_pcap0,iface=eth2).\\n\"\n\t \" --\"OPT_VMWARE_TSC_MAP\" Use VMware TSC map instead of native RDTSC\\n\"\n\t \" --\"OPT_PROC_TYPE\" Type of this process (primary|secondary|auto)\\n\"\n\t \" --\"OPT_SYSLOG\" Set syslog facility\\n\"\n\t \" --\"OPT_LOG_LEVEL\" Set default log level\\n\"\n\t \" -v Display version information on startup\\n\"\n\t \" -h, --help This help\\n\"\n\t \"\\nEAL options for DEBUG use only:\\n\"\n\t \" --\"OPT_NO_HUGE\" Use malloc instead of hugetlbfs\\n\"\n\t \" --\"OPT_NO_PCI\" Disable PCI\\n\"\n\t \" --\"OPT_NO_HPET\" Disable HPET\\n\"\n\t \" --\"OPT_NO_SHCONF\" No shared config (mmap'd files)\\n\"\n\t \"\\n\", RTE_MAX_LCORE);\n}\n" }, { "path": "lib/librte_eal/common/eal_common_pci.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n/* BSD LICENSE\n *\n * Copyright 2013-2014 6WIND S.A.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n\nstruct pci_driver_list pci_driver_list;\nstruct pci_device_list pci_device_list;\n\nstatic struct rte_devargs *pci_devargs_lookup(struct rte_pci_device *dev)\n{\n\tstruct rte_devargs *devargs;\n\n\tTAILQ_FOREACH(devargs, &devargs_list, next) {\n\t\tif (devargs->type != RTE_DEVTYPE_BLACKLISTED_PCI &&\n\t\t\tdevargs->type != RTE_DEVTYPE_WHITELISTED_PCI)\n\t\t\tcontinue;\n\t\tif (!rte_eal_compare_pci_addr(&dev->addr, &devargs->pci.addr))\n\t\t\treturn devargs;\n\t}\n\treturn NULL;\n}\n\n/* map a particular resource from a file */\nvoid *\npci_map_resource(void *requested_addr, int fd, off_t offset, size_t size,\n\t\t int additional_flags)\n{\n\tvoid *mapaddr;\n\n\t/* Map the PCI memory resource of device */\n\tmapaddr = mmap(requested_addr, size, PROT_READ | PROT_WRITE,\n\t\t\tMAP_SHARED | additional_flags, fd, offset);\n\tif (mapaddr == MAP_FAILED) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot mmap(%d, %p, 0x%lx, 0x%lx): %s (%p)\\n\",\n\t\t\t__func__, fd, requested_addr,\n\t\t\t(unsigned long)size, (unsigned long)offset,\n\t\t\tstrerror(errno), mapaddr);\n\t} else\n\t\tRTE_LOG(DEBUG, EAL, \" PCI memory mapped at %p\\n\", mapaddr);\n\n\treturn mapaddr;\n}\n\n/* unmap a particular resource */\nvoid\npci_unmap_resource(void *requested_addr, size_t size)\n{\n\tif (requested_addr == NULL)\n\t\treturn;\n\n\t/* Unmap the PCI memory resource of device */\n\tif (munmap(requested_addr, size)) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot munmap(%p, 0x%lx): %s\\n\",\n\t\t\t__func__, requested_addr, (unsigned long)size,\n\t\t\tstrerror(errno));\n\t} else\n\t\tRTE_LOG(DEBUG, EAL, \" PCI memory unmapped at %p\\n\",\n\t\t\t\trequested_addr);\n}\n\n/*\n * If vendor/device ID match, call the devinit() function of the\n * driver.\n */\nstatic int\nrte_eal_pci_probe_one_driver(struct rte_pci_driver *dr, struct rte_pci_device *dev)\n{\n\tint ret;\n\tconst struct rte_pci_id *id_table;\n\n\tfor (id_table = dr->id_table; id_table->vendor_id != 0; id_table++) {\n\n\t\t/* check if device's identifiers match the driver's ones */\n\t\tif (id_table->vendor_id != dev->id.vendor_id &&\n\t\t\t\tid_table->vendor_id != PCI_ANY_ID)\n\t\t\tcontinue;\n\t\tif (id_table->device_id != dev->id.device_id &&\n\t\t\t\tid_table->device_id != PCI_ANY_ID)\n\t\t\tcontinue;\n\t\tif (id_table->subsystem_vendor_id != dev->id.subsystem_vendor_id &&\n\t\t\t\tid_table->subsystem_vendor_id != PCI_ANY_ID)\n\t\t\tcontinue;\n\t\tif (id_table->subsystem_device_id != dev->id.subsystem_device_id &&\n\t\t\t\tid_table->subsystem_device_id != PCI_ANY_ID)\n\t\t\tcontinue;\n\n\t\tstruct rte_pci_addr *loc = &dev->addr;\n\n\t\tRTE_LOG(DEBUG, EAL, \"PCI device \"PCI_PRI_FMT\" on NUMA socket %i\\n\",\n\t\t\t\tloc->domain, loc->bus, loc->devid, loc->function,\n\t\t\t\tdev->numa_node);\n\n\t\tRTE_LOG(DEBUG, EAL, \" probe driver: %x:%x %s\\n\", dev->id.vendor_id,\n\t\t\t\tdev->id.device_id, dr->name);\n\n\t\t/* no initialization when blacklisted, return without error */\n\t\tif (dev->devargs != NULL &&\n\t\t\tdev->devargs->type == RTE_DEVTYPE_BLACKLISTED_PCI) {\n\t\t\tRTE_LOG(DEBUG, EAL, \" Device is blacklisted, not initializing\\n\");\n\t\t\treturn 1;\n\t\t}\n\n\t\tif (dr->drv_flags & RTE_PCI_DRV_NEED_MAPPING) {\n#ifdef RTE_PCI_CONFIG\n\t\t\t/*\n\t\t\t * Set PCIe config space for high performance.\n\t\t\t * Return value can be ignored.\n\t\t\t */\n\t\t\tpci_config_space_set(dev);\n#endif\n\t\t\t/* map resources for devices that use igb_uio */\n\t\t\tret = pci_map_device(dev);\n\t\t\tif (ret != 0)\n\t\t\t\treturn ret;\n\t\t} else if (dr->drv_flags & RTE_PCI_DRV_FORCE_UNBIND &&\n\t\t\t\trte_eal_process_type() == RTE_PROC_PRIMARY) {\n\t\t\t/* unbind current driver */\n\t\t\tif (pci_unbind_kernel_driver(dev) < 0)\n\t\t\t\treturn -1;\n\t\t}\n\n\t\t/* reference driver structure */\n\t\tdev->driver = dr;\n\n\t\t/* call the driver devinit() function */\n\t\treturn dr->devinit(dr, dev);\n\t}\n\t/* return positive value if driver is not found */\n\treturn 1;\n}\n\n/*\n * If vendor/device ID match, call the devuninit() function of the\n * driver.\n */\nstatic int\nrte_eal_pci_detach_dev(struct rte_pci_driver *dr,\n\t\tstruct rte_pci_device *dev)\n{\n\tconst struct rte_pci_id *id_table;\n\n\tif ((dr == NULL) || (dev == NULL))\n\t\treturn -EINVAL;\n\n\tfor (id_table = dr->id_table; id_table->vendor_id != 0; id_table++) {\n\n\t\t/* check if device's identifiers match the driver's ones */\n\t\tif (id_table->vendor_id != dev->id.vendor_id &&\n\t\t\t\tid_table->vendor_id != PCI_ANY_ID)\n\t\t\tcontinue;\n\t\tif (id_table->device_id != dev->id.device_id &&\n\t\t\t\tid_table->device_id != PCI_ANY_ID)\n\t\t\tcontinue;\n\t\tif (id_table->subsystem_vendor_id != dev->id.subsystem_vendor_id &&\n\t\t\t\tid_table->subsystem_vendor_id != PCI_ANY_ID)\n\t\t\tcontinue;\n\t\tif (id_table->subsystem_device_id != dev->id.subsystem_device_id &&\n\t\t\t\tid_table->subsystem_device_id != PCI_ANY_ID)\n\t\t\tcontinue;\n\n\t\tstruct rte_pci_addr *loc = &dev->addr;\n\n\t\tRTE_LOG(DEBUG, EAL, \"PCI device \"PCI_PRI_FMT\" on NUMA socket %i\\n\",\n\t\t\t\tloc->domain, loc->bus, loc->devid,\n\t\t\t\tloc->function, dev->numa_node);\n\n\t\tRTE_LOG(DEBUG, EAL, \" remove driver: %x:%x %s\\n\", dev->id.vendor_id,\n\t\t\t\tdev->id.device_id, dr->name);\n\n\t\tif (dr->devuninit && (dr->devuninit(dev) < 0))\n\t\t\treturn -1;\t/* negative value is an error */\n\n\t\t/* clear driver structure */\n\t\tdev->driver = NULL;\n\n\t\tif (dr->drv_flags & RTE_PCI_DRV_NEED_MAPPING)\n\t\t\t/* unmap resources for devices that use igb_uio */\n\t\t\tpci_unmap_device(dev);\n\n\t\treturn 0;\n\t}\n\n\t/* return positive value if driver is not found */\n\treturn 1;\n}\n\n/*\n * If vendor/device ID match, call the devinit() function of all\n * registered driver for the given device. Return -1 if initialization\n * failed, return 1 if no driver is found for this device.\n */\nstatic int\npci_probe_all_drivers(struct rte_pci_device *dev)\n{\n\tstruct rte_pci_driver *dr = NULL;\n\tint rc = 0;\n\n\tif (dev == NULL)\n\t\treturn -1;\n\n\tTAILQ_FOREACH(dr, &pci_driver_list, next) {\n\t\trc = rte_eal_pci_probe_one_driver(dr, dev);\n\t\tif (rc < 0)\n\t\t\t/* negative value is an error */\n\t\t\treturn -1;\n\t\tif (rc > 0)\n\t\t\t/* positive value means driver not found */\n\t\t\tcontinue;\n\t\treturn 0;\n\t}\n\treturn 1;\n}\n\n/*\n * If vendor/device ID match, call the devuninit() function of all\n * registered driver for the given device. Return -1 if initialization\n * failed, return 1 if no driver is found for this device.\n */\nstatic int\npci_detach_all_drivers(struct rte_pci_device *dev)\n{\n\tstruct rte_pci_driver *dr = NULL;\n\tint rc = 0;\n\n\tif (dev == NULL)\n\t\treturn -1;\n\n\tTAILQ_FOREACH(dr, &pci_driver_list, next) {\n\t\trc = rte_eal_pci_detach_dev(dr, dev);\n\t\tif (rc < 0)\n\t\t\t/* negative value is an error */\n\t\t\treturn -1;\n\t\tif (rc > 0)\n\t\t\t/* positive value means driver not found */\n\t\t\tcontinue;\n\t\treturn 0;\n\t}\n\treturn 1;\n}\n\n/*\n * Find the pci device specified by pci address, then invoke probe function of\n * the driver of the devive.\n */\nint\nrte_eal_pci_probe_one(const struct rte_pci_addr *addr)\n{\n\tstruct rte_pci_device *dev = NULL;\n\tint ret = 0;\n\n\tif (addr == NULL)\n\t\treturn -1;\n\n\tTAILQ_FOREACH(dev, &pci_device_list, next) {\n\t\tif (rte_eal_compare_pci_addr(&dev->addr, addr))\n\t\t\tcontinue;\n\n\t\tret = pci_probe_all_drivers(dev);\n\t\tif (ret < 0)\n\t\t\tgoto err_return;\n\t\treturn 0;\n\t}\n\treturn -1;\n\nerr_return:\n\tRTE_LOG(WARNING, EAL, \"Requested device \" PCI_PRI_FMT\n\t\t\t\" cannot be used\\n\", dev->addr.domain, dev->addr.bus,\n\t\t\tdev->addr.devid, dev->addr.function);\n\treturn -1;\n}\n\nint __attribute__ ((deprecated))\nrte_eal_pci_close_one(const struct rte_pci_addr *addr)\n{\n\treturn rte_eal_pci_detach(addr);\n}\n\n/*\n * Detach device specified by its pci address.\n */\nint\nrte_eal_pci_detach(const struct rte_pci_addr *addr)\n{\n\tstruct rte_pci_device *dev = NULL;\n\tint ret = 0;\n\n\tif (addr == NULL)\n\t\treturn -1;\n\n\tTAILQ_FOREACH(dev, &pci_device_list, next) {\n\t\tif (rte_eal_compare_pci_addr(&dev->addr, addr))\n\t\t\tcontinue;\n\n\t\tret = pci_detach_all_drivers(dev);\n\t\tif (ret < 0)\n\t\t\tgoto err_return;\n\n\t\tTAILQ_REMOVE(&pci_device_list, dev, next);\n\t\treturn 0;\n\t}\n\treturn -1;\n\nerr_return:\n\tRTE_LOG(WARNING, EAL, \"Requested device \" PCI_PRI_FMT\n\t\t\t\" cannot be used\\n\", dev->addr.domain, dev->addr.bus,\n\t\t\tdev->addr.devid, dev->addr.function);\n\treturn -1;\n}\n\n/*\n * Scan the content of the PCI bus, and call the devinit() function for\n * all registered drivers that have a matching entry in its id_table\n * for discovered devices.\n */\nint\nrte_eal_pci_probe(void)\n{\n\tstruct rte_pci_device *dev = NULL;\n\tstruct rte_devargs *devargs;\n\tint probe_all = 0;\n\tint ret = 0;\n\n\tif (rte_eal_devargs_type_count(RTE_DEVTYPE_WHITELISTED_PCI) == 0)\n\t\tprobe_all = 1;\n\n\tTAILQ_FOREACH(dev, &pci_device_list, next) {\n\n\t\t/* set devargs in PCI structure */\n\t\tdevargs = pci_devargs_lookup(dev);\n\t\tif (devargs != NULL)\n\t\t\tdev->devargs = devargs;\n\n\t\t/* probe all or only whitelisted devices */\n\t\tif (probe_all)\n\t\t\tret = pci_probe_all_drivers(dev);\n\t\telse if (devargs != NULL &&\n\t\t\tdevargs->type == RTE_DEVTYPE_WHITELISTED_PCI)\n\t\t\tret = pci_probe_all_drivers(dev);\n\t\tif (ret < 0)\n\t\t\trte_exit(EXIT_FAILURE, \"Requested device \" PCI_PRI_FMT\n\t\t\t\t \" cannot be used\\n\", dev->addr.domain, dev->addr.bus,\n\t\t\t\t dev->addr.devid, dev->addr.function);\n\t}\n\n\treturn 0;\n}\n\n/* dump one device */\nstatic int\npci_dump_one_device(FILE *f, struct rte_pci_device *dev)\n{\n\tint i;\n\n\tfprintf(f, PCI_PRI_FMT, dev->addr.domain, dev->addr.bus,\n\t dev->addr.devid, dev->addr.function);\n\tfprintf(f, \" - vendor:%x device:%x\\n\", dev->id.vendor_id,\n\t dev->id.device_id);\n\n\tfor (i = 0; i != sizeof(dev->mem_resource) /\n\t\tsizeof(dev->mem_resource[0]); i++) {\n\t\tfprintf(f, \" %16.16\"PRIx64\" %16.16\"PRIx64\"\\n\",\n\t\t\tdev->mem_resource[i].phys_addr,\n\t\t\tdev->mem_resource[i].len);\n\t}\n\treturn 0;\n}\n\n/* dump devices on the bus */\nvoid\nrte_eal_pci_dump(FILE *f)\n{\n\tstruct rte_pci_device *dev = NULL;\n\n\tTAILQ_FOREACH(dev, &pci_device_list, next) {\n\t\tpci_dump_one_device(f, dev);\n\t}\n}\n\n/* register a driver */\nvoid\nrte_eal_pci_register(struct rte_pci_driver *driver)\n{\n\tTAILQ_INSERT_TAIL(&pci_driver_list, driver, next);\n}\n\n/* unregister a driver */\nvoid\nrte_eal_pci_unregister(struct rte_pci_driver *driver)\n{\n\tTAILQ_REMOVE(&pci_driver_list, driver, next);\n}\n" }, { "path": "lib/librte_eal/common/eal_common_pci_uio.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n\nstatic struct rte_tailq_elem rte_uio_tailq = {\n\t.name = \"UIO_RESOURCE_LIST\",\n};\nEAL_REGISTER_TAILQ(rte_uio_tailq)\n\nstatic int\npci_uio_map_secondary(struct rte_pci_device *dev)\n{\n\tint fd, i;\n\tstruct mapped_pci_resource *uio_res;\n\tstruct mapped_pci_res_list *uio_res_list =\n\t\t\tRTE_TAILQ_CAST(rte_uio_tailq.head, mapped_pci_res_list);\n\n\tTAILQ_FOREACH(uio_res, uio_res_list, next) {\n\n\t\t/* skip this element if it doesn't match our PCI address */\n\t\tif (rte_eal_compare_pci_addr(&uio_res->pci_addr, &dev->addr))\n\t\t\tcontinue;\n\n\t\tfor (i = 0; i != uio_res->nb_maps; i++) {\n\t\t\t/*\n\t\t\t * open devname, to mmap it\n\t\t\t */\n\t\t\tfd = open(uio_res->maps[i].path, O_RDWR);\n\t\t\tif (fd < 0) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Cannot open %s: %s\\n\",\n\t\t\t\t\tuio_res->maps[i].path, strerror(errno));\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tvoid *mapaddr = pci_map_resource(uio_res->maps[i].addr,\n\t\t\t\t\tfd, (off_t)uio_res->maps[i].offset,\n\t\t\t\t\t(size_t)uio_res->maps[i].size, 0);\n\t\t\t/* fd is not needed in slave process, close it */\n\t\t\tclose(fd);\n\t\t\tif (mapaddr != uio_res->maps[i].addr) {\n\t\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\t\"Cannot mmap device resource file %s to address: %p\\n\",\n\t\t\t\t\tuio_res->maps[i].path,\n\t\t\t\t\tuio_res->maps[i].addr);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\t\treturn 0;\n\t}\n\n\tRTE_LOG(ERR, EAL, \"Cannot find resource for device\\n\");\n\treturn 1;\n}\n\n/* map the PCI resource of a PCI device in virtual memory */\nint\npci_uio_map_resource(struct rte_pci_device *dev)\n{\n\tint i, map_idx = 0, ret;\n\tuint64_t phaddr;\n\tstruct mapped_pci_resource *uio_res = NULL;\n\tstruct mapped_pci_res_list *uio_res_list =\n\t\tRTE_TAILQ_CAST(rte_uio_tailq.head, mapped_pci_res_list);\n\n\tdev->intr_handle.fd = -1;\n\tdev->intr_handle.uio_cfg_fd = -1;\n\tdev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;\n\n\t/* secondary processes - use already recorded details */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn pci_uio_map_secondary(dev);\n\n\t/* allocate uio resource */\n\tret = pci_uio_alloc_resource(dev, &uio_res);\n\tif (ret)\n\t\treturn ret;\n\n\t/* Map all BARs */\n\tfor (i = 0; i != PCI_MAX_RESOURCE; i++) {\n\t\t/* skip empty BAR */\n\t\tphaddr = dev->mem_resource[i].phys_addr;\n\t\tif (phaddr == 0)\n\t\t\tcontinue;\n\n\t\tret = pci_uio_map_resource_by_index(dev, i,\n\t\t\t\tuio_res, map_idx);\n\t\tif (ret)\n\t\t\tgoto error;\n\n\t\tmap_idx++;\n\t}\n\n\tuio_res->nb_maps = map_idx;\n\n\tTAILQ_INSERT_TAIL(uio_res_list, uio_res, next);\n\n\treturn 0;\nerror:\n\tfor (i = 0; i < map_idx; i++) {\n\t\tpci_unmap_resource(uio_res->maps[i].addr,\n\t\t\t\t(size_t)uio_res->maps[i].size);\n\t\trte_free(uio_res->maps[i].path);\n\t}\n\tpci_uio_free_resource(dev, uio_res);\n\treturn -1;\n}\n\nstatic void\npci_uio_unmap(struct mapped_pci_resource *uio_res)\n{\n\tint i;\n\n\tif (uio_res == NULL)\n\t\treturn;\n\n\tfor (i = 0; i != uio_res->nb_maps; i++) {\n\t\tpci_unmap_resource(uio_res->maps[i].addr,\n\t\t\t\t(size_t)uio_res->maps[i].size);\n\t\trte_free(uio_res->maps[i].path);\n\t}\n}\n\nstatic struct mapped_pci_resource *\npci_uio_find_resource(struct rte_pci_device *dev)\n{\n\tstruct mapped_pci_resource *uio_res;\n\tstruct mapped_pci_res_list *uio_res_list =\n\t\t\tRTE_TAILQ_CAST(rte_uio_tailq.head, mapped_pci_res_list);\n\n\tif (dev == NULL)\n\t\treturn NULL;\n\n\tTAILQ_FOREACH(uio_res, uio_res_list, next) {\n\n\t\t/* skip this element if it doesn't match our PCI address */\n\t\tif (!rte_eal_compare_pci_addr(&uio_res->pci_addr, &dev->addr))\n\t\t\treturn uio_res;\n\t}\n\treturn NULL;\n}\n\n/* unmap the PCI resource of a PCI device in virtual memory */\nvoid\npci_uio_unmap_resource(struct rte_pci_device *dev)\n{\n\tstruct mapped_pci_resource *uio_res;\n\tstruct mapped_pci_res_list *uio_res_list =\n\t\t\tRTE_TAILQ_CAST(rte_uio_tailq.head, mapped_pci_res_list);\n\n\tif (dev == NULL)\n\t\treturn;\n\n\t/* find an entry for the device */\n\tuio_res = pci_uio_find_resource(dev);\n\tif (uio_res == NULL)\n\t\treturn;\n\n\t/* secondary processes - just free maps */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn pci_uio_unmap(uio_res);\n\n\tTAILQ_REMOVE(uio_res_list, uio_res, next);\n\n\t/* unmap all resources */\n\tpci_uio_unmap(uio_res);\n\n\t/* free uio resource */\n\trte_free(uio_res);\n\n\t/* close fd if in primary process */\n\tclose(dev->intr_handle.fd);\n\tif (dev->intr_handle.uio_cfg_fd >= 0) {\n\t\tclose(dev->intr_handle.uio_cfg_fd);\n\t\tdev->intr_handle.uio_cfg_fd = -1;\n\t}\n\n\tdev->intr_handle.fd = -1;\n\tdev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;\n}\n" }, { "path": "lib/librte_eal/common/eal_common_string_fns.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n\n/* split string into tokens */\nint\nrte_strsplit(char *string, int stringlen,\n\t char **tokens, int maxtokens, char delim)\n{\n\tint i, tok = 0;\n\tint tokstart = 1; /* first token is right at start of string */\n\n\tif (string == NULL || tokens == NULL)\n\t\tgoto einval_error;\n\n\tfor (i = 0; i < stringlen; i++) {\n\t\tif (string[i] == '\\0' || tok >= maxtokens)\n\t\t\tbreak;\n\t\tif (tokstart) {\n\t\t\ttokstart = 0;\n\t\t\ttokens[tok++] = &string[i];\n\t\t}\n\t\tif (string[i] == delim) {\n\t\t\tstring[i] = '\\0';\n\t\t\ttokstart = 1;\n\t\t}\n\t}\n\treturn tok;\n\neinval_error:\n\terrno = EINVAL;\n\treturn -1;\n}\n" }, { "path": "lib/librte_eal/common/eal_common_tailqs.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n\nTAILQ_HEAD(rte_tailq_elem_head, rte_tailq_elem);\n/* local tailq list */\nstatic struct rte_tailq_elem_head rte_tailq_elem_head =\n\tTAILQ_HEAD_INITIALIZER(rte_tailq_elem_head);\n\n/* number of tailqs registered, -1 before call to rte_eal_tailqs_init */\nstatic int rte_tailqs_count = -1;\n\nstruct rte_tailq_head *\nrte_eal_tailq_lookup(const char *name)\n{\n\tunsigned i;\n\tstruct rte_mem_config *mcfg = rte_eal_get_configuration()->mem_config;\n\n\tif (name == NULL)\n\t\treturn NULL;\n\n\tfor (i = 0; i < RTE_MAX_TAILQ; i++) {\n\t\tif (!strncmp(name, mcfg->tailq_head[i].name,\n\t\t\t RTE_TAILQ_NAMESIZE-1))\n\t\t\treturn &mcfg->tailq_head[i];\n\t}\n\n\treturn NULL;\n}\n\nvoid\nrte_dump_tailq(FILE *f)\n{\n\tstruct rte_mem_config *mcfg;\n\tunsigned i = 0;\n\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\trte_rwlock_read_lock(&mcfg->qlock);\n\tfor (i = 0; i < RTE_MAX_TAILQ; i++) {\n\t\tconst struct rte_tailq_head *tailq = &mcfg->tailq_head[i];\n\t\tconst struct rte_tailq_entry_head *head = &tailq->tailq_head;\n\n\t\tfprintf(f, \"Tailq %u: qname:<%s>, tqh_first:%p, tqh_last:%p\\n\",\n\t\t\ti, tailq->name, head->tqh_first, head->tqh_last);\n\t}\n\trte_rwlock_read_unlock(&mcfg->qlock);\n}\n\nstatic struct rte_tailq_head *\nrte_eal_tailq_create(const char *name)\n{\n\tstruct rte_tailq_head *head = NULL;\n\n\tif (!rte_eal_tailq_lookup(name) &&\n\t (rte_tailqs_count + 1 < RTE_MAX_TAILQ)) {\n\t\tstruct rte_mem_config *mcfg;\n\n\t\tmcfg = rte_eal_get_configuration()->mem_config;\n\t\thead = &mcfg->tailq_head[rte_tailqs_count];\n\t\tsnprintf(head->name, sizeof(head->name) - 1, \"%s\", name);\n\t\tTAILQ_INIT(&head->tailq_head);\n\t\trte_tailqs_count++;\n\t}\n\n\treturn head;\n}\n\n/* local register, used to store \"early\" tailqs before rte_eal_init() and to\n * ensure secondary process only registers tailqs once. */\nstatic int\nrte_eal_tailq_local_register(struct rte_tailq_elem *t)\n{\n\tstruct rte_tailq_elem *temp;\n\n\tTAILQ_FOREACH(temp, &rte_tailq_elem_head, next) {\n\t\tif (!strncmp(t->name, temp->name, sizeof(temp->name)))\n\t\t\treturn -1;\n\t}\n\n\tTAILQ_INSERT_TAIL(&rte_tailq_elem_head, t, next);\n\treturn 0;\n}\n\nstatic void\nrte_eal_tailq_update(struct rte_tailq_elem *t)\n{\n\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n\t\t/* primary process is the only one that creates */\n\t\tt->head = rte_eal_tailq_create(t->name);\n\t} else {\n\t\tt->head = rte_eal_tailq_lookup(t->name);\n\t}\n}\n\nint\nrte_eal_tailq_register(struct rte_tailq_elem *t)\n{\n\tif (rte_eal_tailq_local_register(t) < 0) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"%s tailq is already registered\\n\", t->name);\n\t\tgoto error;\n\t}\n\n\t/* if a register happens after rte_eal_tailqs_init(), then we can update\n\t * tailq head */\n\tif (rte_tailqs_count >= 0) {\n\t\trte_eal_tailq_update(t);\n\t\tif (t->head == NULL) {\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\"Cannot initialize tailq: %s\\n\", t->name);\n\t\t\tTAILQ_REMOVE(&rte_tailq_elem_head, t, next);\n\t\t\tgoto error;\n\t\t}\n\t}\n\n\treturn 0;\n\nerror:\n\tt->head = NULL;\n\treturn -1;\n}\n\nint\nrte_eal_tailqs_init(void)\n{\n\tstruct rte_tailq_elem *t;\n\n\trte_tailqs_count = 0;\n\n\tTAILQ_FOREACH(t, &rte_tailq_elem_head, next) {\n\t\t/* second part of register job for \"early\" tailqs, see\n\t\t * rte_eal_tailq_register and EAL_REGISTER_TAILQ */\n\t\trte_eal_tailq_update(t);\n\t\tif (t->head == NULL) {\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\"Cannot initialize tailq: %s\\n\", t->name);\n\t\t\t/* no need to TAILQ_REMOVE, we are going to panic in\n\t\t\t * rte_eal_init() */\n\t\t\tgoto fail;\n\t\t}\n\t}\n\n\treturn 0;\n\nfail:\n\trte_dump_tailq(stderr);\n\treturn -1;\n}\n" }, { "path": "lib/librte_eal/common/eal_common_thread.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"eal_thread.h\"\n\nRTE_DECLARE_PER_LCORE(unsigned , _socket_id);\n\nunsigned rte_socket_id(void)\n{\n\treturn RTE_PER_LCORE(_socket_id);\n}\n\nint eal_cpuset_socket_id(rte_cpuset_t *cpusetp)\n{\n\tunsigned cpu = 0;\n\tint socket_id = SOCKET_ID_ANY;\n\tint sid;\n\n\tif (cpusetp == NULL)\n\t\treturn SOCKET_ID_ANY;\n\n\tdo {\n\t\tif (!CPU_ISSET(cpu, cpusetp))\n\t\t\tcontinue;\n\n\t\tif (socket_id == SOCKET_ID_ANY)\n\t\t\tsocket_id = eal_cpu_socket_id(cpu);\n\n\t\tsid = eal_cpu_socket_id(cpu);\n\t\tif (socket_id != sid) {\n\t\t\tsocket_id = SOCKET_ID_ANY;\n\t\t\tbreak;\n\t\t}\n\n\t} while (++cpu < RTE_MAX_LCORE);\n\n\treturn socket_id;\n}\n\nint\nrte_thread_set_affinity(rte_cpuset_t *cpusetp)\n{\n\tint s;\n\tunsigned lcore_id;\n\tpthread_t tid;\n\n\ttid = pthread_self();\n\n\ts = pthread_setaffinity_np(tid, sizeof(rte_cpuset_t), cpusetp);\n\tif (s != 0) {\n\t\tRTE_LOG(ERR, EAL, \"pthread_setaffinity_np failed\\n\");\n\t\treturn -1;\n\t}\n\n\t/* store socket_id in TLS for quick access */\n\tRTE_PER_LCORE(_socket_id) =\n\t\teal_cpuset_socket_id(cpusetp);\n\n\t/* store cpuset in TLS for quick access */\n\tmemmove(&RTE_PER_LCORE(_cpuset), cpusetp,\n\t\tsizeof(rte_cpuset_t));\n\n\tlcore_id = rte_lcore_id();\n\tif (lcore_id != (unsigned)LCORE_ID_ANY) {\n\t\t/* EAL thread will update lcore_config */\n\t\tlcore_config[lcore_id].socket_id = RTE_PER_LCORE(_socket_id);\n\t\tmemmove(&lcore_config[lcore_id].cpuset, cpusetp,\n\t\t\tsizeof(rte_cpuset_t));\n\t}\n\n\treturn 0;\n}\n\nvoid\nrte_thread_get_affinity(rte_cpuset_t *cpusetp)\n{\n\tassert(cpusetp);\n\tmemmove(cpusetp, &RTE_PER_LCORE(_cpuset),\n\t\tsizeof(rte_cpuset_t));\n}\n\nint\neal_thread_dump_affinity(char *str, unsigned size)\n{\n\trte_cpuset_t cpuset;\n\tunsigned cpu;\n\tint ret;\n\tunsigned int out = 0;\n\n\trte_thread_get_affinity(&cpuset);\n\n\tfor (cpu = 0; cpu < RTE_MAX_LCORE; cpu++) {\n\t\tif (!CPU_ISSET(cpu, &cpuset))\n\t\t\tcontinue;\n\n\t\tret = snprintf(str + out,\n\t\t\t size - out, \"%u,\", cpu);\n\t\tif (ret < 0 || (unsigned)ret >= size - out) {\n\t\t\t/* string will be truncated */\n\t\t\tret = -1;\n\t\t\tgoto exit;\n\t\t}\n\n\t\tout += ret;\n\t}\n\n\tret = 0;\nexit:\n\t/* remove the last separator */\n\tif (out > 0)\n\t\tstr[out - 1] = '\\0';\n\n\treturn ret;\n}\n" }, { "path": "lib/librte_eal/common/eal_common_timer.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"eal_private.h\"\n\n/* The frequency of the RDTSC timer resolution */\nstatic uint64_t eal_tsc_resolution_hz;\n\nvoid\nrte_delay_us(unsigned us)\n{\n\tconst uint64_t start = rte_get_timer_cycles();\n\tconst uint64_t ticks = (uint64_t)us * rte_get_timer_hz() / 1E6;\n\twhile ((rte_get_timer_cycles() - start) < ticks)\n\t\trte_pause();\n}\n\nuint64_t\nrte_get_tsc_hz(void)\n{\n\treturn eal_tsc_resolution_hz;\n}\n\nstatic uint64_t\nestimate_tsc_freq(void)\n{\n\tRTE_LOG(WARNING, EAL, \"WARNING: TSC frequency estimated roughly\"\n\t\t\" - clock timings may be less accurate.\\n\");\n\t/* assume that the sleep(1) will sleep for 1 second */\n\tuint64_t start = rte_rdtsc();\n\tsleep(1);\n\treturn rte_rdtsc() - start;\n}\n\nvoid\nset_tsc_freq(void)\n{\n\tuint64_t freq = get_tsc_freq();\n\n\tif (!freq)\n\t\tfreq = estimate_tsc_freq();\n\n\tRTE_LOG(INFO, EAL, \"TSC frequency is ~%\" PRIu64 \" KHz\\n\", freq / 1000);\n\teal_tsc_resolution_hz = freq;\n}\n" }, { "path": "lib/librte_eal/common/eal_filesystem.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/**\n * @file\n * Stores functions and path defines for files and directories\n * on the filesystem for Linux, that are used by the Linux EAL.\n */\n\n#ifndef EAL_FILESYSTEM_H\n#define EAL_FILESYSTEM_H\n\n/** Path of rte config file. */\n#define RUNTIME_CONFIG_FMT \"%s/.%s_config\"\n\n#include \n#include \n#include \n#include \n\n#include \n#include \"eal_internal_cfg.h\"\n\nstatic const char *default_config_dir = \"/var/run\";\n\nstatic inline const char *\neal_runtime_config_path(void)\n{\n\tstatic char buffer[PATH_MAX]; /* static so auto-zeroed */\n\tconst char *directory = default_config_dir;\n\tconst char *home_dir = getenv(\"HOME\");\n\n\tif (getuid() != 0 && home_dir != NULL)\n\t\tdirectory = home_dir;\n\tsnprintf(buffer, sizeof(buffer) - 1, RUNTIME_CONFIG_FMT, directory,\n\t\t\tinternal_config.hugefile_prefix);\n\treturn buffer;\n}\n\n/** Path of hugepage info file. */\n#define HUGEPAGE_INFO_FMT \"%s/.%s_hugepage_info\"\n\nstatic inline const char *\neal_hugepage_info_path(void)\n{\n\tstatic char buffer[PATH_MAX]; /* static so auto-zeroed */\n\tconst char *directory = default_config_dir;\n\tconst char *home_dir = getenv(\"HOME\");\n\n\tif (getuid() != 0 && home_dir != NULL)\n\t\tdirectory = home_dir;\n\tsnprintf(buffer, sizeof(buffer) - 1, HUGEPAGE_INFO_FMT, directory,\n\t\t\tinternal_config.hugefile_prefix);\n\treturn buffer;\n}\n\n/** String format for hugepage map files. */\n#define HUGEFILE_FMT \"%s/%smap_%d\"\n#define TEMP_HUGEFILE_FMT \"%s/%smap_temp_%d\"\n\nstatic inline const char *\neal_get_hugefile_path(char *buffer, size_t buflen, const char *hugedir, int f_id)\n{\n\tsnprintf(buffer, buflen, HUGEFILE_FMT, hugedir,\n\t\t\tinternal_config.hugefile_prefix, f_id);\n\tbuffer[buflen - 1] = '\\0';\n\treturn buffer;\n}\n\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\nstatic inline const char *\neal_get_hugefile_temp_path(char *buffer, size_t buflen, const char *hugedir, int f_id)\n{\n\tsnprintf(buffer, buflen, TEMP_HUGEFILE_FMT, hugedir,\n\t\t\tinternal_config.hugefile_prefix, f_id);\n\tbuffer[buflen - 1] = '\\0';\n\treturn buffer;\n}\n#endif\n\n/** define the default filename prefix for the %s values above */\n#define HUGEFILE_PREFIX_DEFAULT \"rte\"\n\n/** Function to read a single numeric value from a file on the filesystem.\n * Used to read information from files on /sys */\nint eal_parse_sysfs_value(const char *filename, unsigned long *val);\n\n#endif /* EAL_FILESYSTEM_H */\n" }, { "path": "lib/librte_eal/common/eal_hugepages.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef EAL_HUGEPAGES_H\n#define EAL_HUGEPAGES_H\n\n#include \n#include \n#include \n\n#define MAX_HUGEPAGE_PATH PATH_MAX\n\n/**\n * Structure used to store informations about hugepages that we mapped\n * through the files in hugetlbfs.\n */\nstruct hugepage_file {\n\tvoid *orig_va; /**< virtual addr of first mmap() */\n\tvoid *final_va; /**< virtual addr of 2nd mmap() */\n\tuint64_t physaddr; /**< physical addr */\n\tsize_t size; /**< the page size */\n\tint socket_id; /**< NUMA socket ID */\n\tint file_id; /**< the '%d' in HUGEFILE_FMT */\n\tint memseg_id; /**< the memory segment to which page belongs */\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\tint repeated;\t\t/**< number of times the page size is repeated */\n#endif\n\tchar filepath[MAX_HUGEPAGE_PATH]; /**< path to backing file on filesystem */\n};\n\n/**\n * Read the information from linux on what hugepages are available\n * for the EAL to use\n */\nint eal_hugepage_info_init(void);\n\n#endif /* EAL_HUGEPAGES_H */\n" }, { "path": "lib/librte_eal/common/eal_internal_cfg.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/**\n * @file\n * Holds the structures for the eal internal configuration\n */\n\n#ifndef EAL_INTERNAL_CFG_H\n#define EAL_INTERNAL_CFG_H\n\n#include \n#include \n\n#define MAX_HUGEPAGE_SIZES 3 /**< support up to 3 page sizes */\n\n/*\n * internal configuration structure for the number, size and\n * mount points of hugepages\n */\nstruct hugepage_info {\n\tuint64_t hugepage_sz; /**< size of a huge page */\n\tconst char *hugedir; /**< dir where hugetlbfs is mounted */\n\tuint32_t num_pages[RTE_MAX_NUMA_NODES];\n\t\t\t\t/**< number of hugepages of that size on each socket */\n\tint lock_descriptor; /**< file descriptor for hugepage dir */\n};\n\n/**\n * internal configuration\n */\nstruct internal_config {\n\tvolatile size_t memory; /**< amount of asked memory */\n\tvolatile unsigned force_nchannel; /**< force number of channels */\n\tvolatile unsigned force_nrank; /**< force number of ranks */\n\tvolatile unsigned no_hugetlbfs; /**< true to disable hugetlbfs */\n\tvolatile unsigned xen_dom0_support; /**< support app running on Xen Dom0*/\n\tvolatile unsigned no_pci; /**< true to disable PCI */\n\tvolatile unsigned no_hpet; /**< true to disable HPET */\n\tvolatile unsigned vmware_tsc_map; /**< true to use VMware TSC mapping\n\t\t\t\t\t\t\t\t\t\t* instead of native TSC */\n\tvolatile unsigned no_shconf; /**< true if there is no shared config */\n\tvolatile unsigned create_uio_dev; /**< true to create /dev/uioX devices */\n\tvolatile enum rte_proc_type_t process_type; /**< multi-process proc type */\n\t/** true to try allocating memory on specific sockets */\n\tvolatile unsigned force_sockets;\n\tvolatile uint64_t socket_mem[RTE_MAX_NUMA_NODES]; /**< amount of memory per socket */\n\tuintptr_t base_virtaddr; /**< base address to try and reserve memory from */\n\tvolatile int syslog_facility;\t /**< facility passed to openlog() */\n\tvolatile uint32_t log_level;\t /**< default log level */\n\t/** default interrupt mode for VFIO */\n\tvolatile enum rte_intr_mode vfio_intr_mode;\n\tconst char *hugefile_prefix; /**< the base filename of hugetlbfs files */\n\tconst char *hugepage_dir; /**< specific hugetlbfs directory to use */\n\n\tunsigned num_hugepage_sizes; /**< how many sizes on this system */\n\tstruct hugepage_info hugepage_info[MAX_HUGEPAGE_SIZES];\n};\nextern struct internal_config internal_config; /**< Global EAL configuration. */\n\nvoid eal_reset_internal_config(struct internal_config *internal_cfg);\n\n#endif /* EAL_INTERNAL_CFG_H */\n" }, { "path": "lib/librte_eal/common/eal_options.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014 6WIND S.A.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef EAL_OPTIONS_H\n#define EAL_OPTIONS_H\n\nenum {\n\t/* long options mapped to a short option */\n#define OPT_HELP \"help\"\n\tOPT_HELP_NUM = 'h',\n#define OPT_PCI_BLACKLIST \"pci-blacklist\"\n\tOPT_PCI_BLACKLIST_NUM = 'b',\n#define OPT_PCI_WHITELIST \"pci-whitelist\"\n\tOPT_PCI_WHITELIST_NUM = 'w',\n\n\t/* first long only option value must be >= 256, so that we won't\n\t * conflict with short options */\n\tOPT_LONG_MIN_NUM = 256,\n#define OPT_BASE_VIRTADDR \"base-virtaddr\"\n\tOPT_BASE_VIRTADDR_NUM,\n#define OPT_CREATE_UIO_DEV \"create-uio-dev\"\n\tOPT_CREATE_UIO_DEV_NUM,\n#define OPT_FILE_PREFIX \"file-prefix\"\n\tOPT_FILE_PREFIX_NUM,\n#define OPT_HUGE_DIR \"huge-dir\"\n\tOPT_HUGE_DIR_NUM,\n#define OPT_LCORES \"lcores\"\n\tOPT_LCORES_NUM,\n#define OPT_LOG_LEVEL \"log-level\"\n\tOPT_LOG_LEVEL_NUM,\n#define OPT_MASTER_LCORE \"master-lcore\"\n\tOPT_MASTER_LCORE_NUM,\n#define OPT_PROC_TYPE \"proc-type\"\n\tOPT_PROC_TYPE_NUM,\n#define OPT_NO_HPET \"no-hpet\"\n\tOPT_NO_HPET_NUM,\n#define OPT_NO_HUGE \"no-huge\"\n\tOPT_NO_HUGE_NUM,\n#define OPT_NO_PCI \"no-pci\"\n\tOPT_NO_PCI_NUM,\n#define OPT_NO_SHCONF \"no-shconf\"\n\tOPT_NO_SHCONF_NUM,\n#define OPT_SOCKET_MEM \"socket-mem\"\n\tOPT_SOCKET_MEM_NUM,\n#define OPT_SYSLOG \"syslog\"\n\tOPT_SYSLOG_NUM,\n#define OPT_VDEV \"vdev\"\n\tOPT_VDEV_NUM,\n#define OPT_VFIO_INTR \"vfio-intr\"\n\tOPT_VFIO_INTR_NUM,\n#define OPT_VMWARE_TSC_MAP \"vmware-tsc-map\"\n\tOPT_VMWARE_TSC_MAP_NUM,\n#define OPT_XEN_DOM0 \"xen-dom0\"\n\tOPT_XEN_DOM0_NUM,\n\tOPT_LONG_MAX_NUM\n};\n\nextern const char eal_short_options[];\nextern const struct option eal_long_options[];\n\nint eal_parse_common_option(int opt, const char *argv,\n\t\t\t struct internal_config *conf);\nint eal_adjust_config(struct internal_config *internal_cfg);\nint eal_check_common_options(struct internal_config *internal_cfg);\nvoid eal_common_usage(void);\nenum rte_proc_type_t eal_proc_type_detect(void);\n\n#endif /* EAL_OPTIONS_H */\n" }, { "path": "lib/librte_eal/common/eal_private.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _EAL_PRIVATE_H_\n#define _EAL_PRIVATE_H_\n\n#include \n#include \n\n/**\n * Initialize the memzone subsystem (private to eal).\n *\n * @return\n * - 0 on success\n * - Negative on error\n */\nint rte_eal_memzone_init(void);\n\n/**\n * Common log initialization function (private to eal).\n *\n * Called by environment-specific log initialization function to initialize\n * log history.\n *\n * @param default_log\n * The default log stream to be used.\n * @return\n * - 0 on success\n * - Negative on error\n */\nint rte_eal_common_log_init(FILE *default_log);\n\n/**\n * Fill configuration with number of physical and logical processors\n *\n * This function is private to EAL.\n *\n * Parse /proc/cpuinfo to get the number of physical and logical\n * processors on the machine.\n *\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_cpu_init(void);\n\n/**\n * Map memory\n *\n * This function is private to EAL.\n *\n * Fill configuration structure with these infos, and return 0 on success.\n *\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_memory_init(void);\n\n/**\n * Configure timers\n *\n * This function is private to EAL.\n *\n * Mmap memory areas used by HPET (high precision event timer) that will\n * provide our time reference, and configure the TSC frequency also for it\n * to be used as a reference.\n *\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_timer_init(void);\n\n/**\n * Init early logs\n *\n * This function is private to EAL.\n *\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_log_early_init(void);\n\n/**\n * Init the default log stream\n *\n * This function is private to EAL.\n *\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_log_init(const char *id, int facility);\n\n/**\n * Init the default log stream\n *\n * This function is private to EAL.\n *\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_pci_init(void);\n\n#ifdef RTE_LIBRTE_IVSHMEM\n/**\n * Init the memory from IVSHMEM devices\n *\n * This function is private to EAL.\n *\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_ivshmem_init(void);\n\n/**\n * Init objects in IVSHMEM devices\n *\n * This function is private to EAL.\n *\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_ivshmem_obj_init(void);\n#endif\n\nstruct rte_pci_driver;\nstruct rte_pci_device;\n\n/**\n * Unbind kernel driver for this device\n *\n * This function is private to EAL.\n *\n * @return\n * 0 on success, negative on error\n */\nint pci_unbind_kernel_driver(struct rte_pci_device *dev);\n\n/**\n * Map this device\n *\n * This function is private to EAL.\n *\n * @return\n * 0 on success, negative on error and positive if no driver\n * is found for the device.\n */\nint pci_map_device(struct rte_pci_device *dev);\n\n/**\n * Unmap this device\n *\n * This function is private to EAL.\n */\nvoid pci_unmap_device(struct rte_pci_device *dev);\n\n/**\n * Map the PCI resource of a PCI device in virtual memory\n *\n * This function is private to EAL.\n *\n * @return\n * 0 on success, negative on error\n */\nint pci_uio_map_resource(struct rte_pci_device *dev);\n\n/**\n * Unmap the PCI resource of a PCI device\n *\n * This function is private to EAL.\n */\nvoid pci_uio_unmap_resource(struct rte_pci_device *dev);\n\n/**\n * Allocate uio resource for PCI device\n *\n * This function is private to EAL.\n *\n * @param dev\n * PCI device to allocate uio resource\n * @param uio_res\n * Pointer to uio resource.\n * If the function returns 0, the pointer will be filled.\n * @return\n * 0 on success, negative on error\n */\nint pci_uio_alloc_resource(struct rte_pci_device *dev,\n\t\tstruct mapped_pci_resource **uio_res);\n\n/**\n * Free uio resource for PCI device\n *\n * This function is private to EAL.\n *\n * @param dev\n * PCI device to free uio resource\n * @param uio_res\n * Pointer to uio resource.\n */\nvoid pci_uio_free_resource(struct rte_pci_device *dev,\n\t\tstruct mapped_pci_resource *uio_res);\n\n/**\n * Map device memory to uio resource\n *\n * This function is private to EAL.\n *\n * @param dev\n * PCI device that has memory information.\n * @param res_idx\n * Memory resource index of the PCI device.\n * @param uio_res\n * uio resource that will keep mapping information.\n * @param map_idx\n * Mapping information index of the uio resource.\n * @return\n * 0 on success, negative on error\n */\nint pci_uio_map_resource_by_index(struct rte_pci_device *dev, int res_idx,\n\t\tstruct mapped_pci_resource *uio_res, int map_idx);\n\n/**\n * Init tail queues for non-EAL library structures. This is to allow\n * the rings, mempools, etc. lists to be shared among multiple processes\n *\n * This function is private to EAL\n *\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_tailqs_init(void);\n\n/**\n * Init interrupt handling.\n *\n * This function is private to EAL.\n *\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_intr_init(void);\n\n/**\n * Init alarm mechanism. This is to allow a callback be called after\n * specific time.\n *\n * This function is private to EAL.\n *\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_alarm_init(void);\n\n/**\n * This function initialises any virtual devices\n *\n * This function is private to the EAL.\n */\nint rte_eal_dev_init(void);\n\n/**\n * Function is to check if the kernel module(like, vfio, vfio_iommu_type1,\n * etc.) loaded.\n *\n * @param module_name\n *\tThe module's name which need to be checked\n *\n * @return\n *\t-1 means some error happens(NULL pointer or open failure)\n *\t0 means the module not loaded\n *\t1 means the module loaded\n */\nint rte_eal_check_module(const char *module_name);\n\n/**\n * Get cpu core_id.\n *\n * This function is private to the EAL.\n */\nunsigned eal_cpu_core_id(unsigned lcore_id);\n\n/**\n * Check if cpu is present.\n *\n * This function is private to the EAL.\n */\nint eal_cpu_detected(unsigned lcore_id);\n\n/**\n * Set TSC frequency from precise value or estimation\n *\n * This function is private to the EAL.\n */\nvoid set_tsc_freq(void);\n\n/**\n * Get precise TSC frequency from system\n *\n * This function is private to the EAL.\n */\nuint64_t get_tsc_freq(void);\n\n/**\n * Prepare physical memory mapping\n * i.e. hugepages on Linux and\n * contigmem on BSD.\n *\n * This function is private to the EAL.\n */\nint rte_eal_hugepage_init(void);\n\n/**\n * Creates memory mapping in secondary process\n * i.e. hugepages on Linux and\n * contigmem on BSD.\n *\n * This function is private to the EAL.\n */\nint rte_eal_hugepage_attach(void);\n\n#endif /* _EAL_PRIVATE_H_ */\n" }, { "path": "lib/librte_eal/common/eal_thread.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef EAL_THREAD_H\n#define EAL_THREAD_H\n\n#include \n\n/**\n * basic loop of thread, called for each thread by eal_init().\n *\n * @param arg\n * opaque pointer\n */\n__attribute__((noreturn)) void *eal_thread_loop(void *arg);\n\n/**\n * Init per-lcore info for master thread\n *\n * @param lcore_id\n * identifier of master lcore\n */\nvoid eal_thread_init_master(unsigned lcore_id);\n\n/**\n * Get the NUMA socket id from cpu id.\n * This function is private to EAL.\n *\n * @param cpu_id\n * The logical process id.\n * @return\n * socket_id or SOCKET_ID_ANY\n */\nunsigned eal_cpu_socket_id(unsigned cpu_id);\n\n/**\n * Get the NUMA socket id from cpuset.\n * This function is private to EAL.\n *\n * @param cpusetp\n * The point to a valid cpu set.\n * @return\n * socket_id or SOCKET_ID_ANY\n */\nint eal_cpuset_socket_id(rte_cpuset_t *cpusetp);\n\n/**\n * Default buffer size to use with eal_thread_dump_affinity()\n */\n#define RTE_CPU_AFFINITY_STR_LEN 256\n\n/**\n * Dump the current pthread cpuset.\n * This function is private to EAL.\n *\n * Note:\n * If the dump size is greater than the size of given buffer,\n * the string will be truncated and with '\\0' at the end.\n *\n * @param str\n * The string buffer the cpuset will dump to.\n * @param size\n * The string buffer size.\n * @return\n * 0 for success, -1 if truncation happens.\n */\nint\neal_thread_dump_affinity(char *str, unsigned size);\n\n#endif /* EAL_THREAD_H */\n" }, { "path": "lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) IBM Corporation 2014.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of IBM Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n/*\n * Inspired from FreeBSD src/sys/powerpc/include/atomic.h\n * Copyright (c) 2008 Marcel Moolenaar\n * Copyright (c) 2001 Benno Rice\n * Copyright (c) 2001 David E. O'Brien\n * Copyright (c) 1998 Doug Rabson\n * All rights reserved.\n */\n\n#ifndef _RTE_ATOMIC_PPC_64_H_\n#define _RTE_ATOMIC_PPC_64_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_atomic.h\"\n\n/**\n * General memory barrier.\n *\n * Guarantees that the LOAD and STORE operations generated before the\n * barrier occur before the LOAD and STORE operations generated after.\n */\n#define\trte_mb() {asm volatile(\"sync\" : : : \"memory\"); }\n\n/**\n * Write memory barrier.\n *\n * Guarantees that the STORE operations generated before the barrier\n * occur before the STORE operations generated after.\n */\n#define\trte_wmb() {asm volatile(\"sync\" : : : \"memory\"); }\n\n/**\n * Read memory barrier.\n *\n * Guarantees that the LOAD operations generated before the barrier\n * occur before the LOAD operations generated after.\n */\n#define\trte_rmb() {asm volatile(\"sync\" : : : \"memory\"); }\n\n/*------------------------- 16 bit atomic operations -------------------------*/\n/* To be compatible with Power7, use GCC built-in functions for 16 bit\n * operations */\n\n#ifndef RTE_FORCE_INTRINSICS\nstatic inline int\nrte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)\n{\n\treturn __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE,\n\t\t__ATOMIC_ACQUIRE) ? 1 : 0;\n}\n\nstatic inline int rte_atomic16_test_and_set(rte_atomic16_t *v)\n{\n\treturn rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);\n}\n\nstatic inline void\nrte_atomic16_inc(rte_atomic16_t *v)\n{\n\t__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);\n}\n\nstatic inline void\nrte_atomic16_dec(rte_atomic16_t *v)\n{\n\t__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);\n}\n\nstatic inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)\n{\n\treturn (__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);\n}\n\nstatic inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)\n{\n\treturn (__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);\n}\n\n/*------------------------- 32 bit atomic operations -------------------------*/\n\nstatic inline int\nrte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)\n{\n\tunsigned int ret = 0;\n\n\tasm volatile(\n\t\t\t\"\\tlwsync\\n\"\n\t\t\t\"1:\\tlwarx %[ret], 0, %[dst]\\n\"\n\t\t\t\"cmplw %[exp], %[ret]\\n\"\n\t\t\t\"bne 2f\\n\"\n\t\t\t\"stwcx. %[src], 0, %[dst]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t\"li %[ret], 1\\n\"\n\t\t\t\"b 3f\\n\"\n\t\t\t\"2:\\n\"\n\t\t\t\"stwcx. %[ret], 0, %[dst]\\n\"\n\t\t\t\"li %[ret], 0\\n\"\n\t\t\t\"3:\\n\"\n\t\t\t\"isync\\n\"\n\t\t\t: [ret] \"=&r\" (ret), \"=m\" (*dst)\n\t\t\t: [dst] \"r\" (dst),\n\t\t\t [exp] \"r\" (exp),\n\t\t\t [src] \"r\" (src),\n\t\t\t \"m\" (*dst)\n\t\t\t: \"cc\", \"memory\");\n\n\treturn ret;\n}\n\nstatic inline int rte_atomic32_test_and_set(rte_atomic32_t *v)\n{\n\treturn rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);\n}\n\nstatic inline void\nrte_atomic32_inc(rte_atomic32_t *v)\n{\n\tint t;\n\n\tasm volatile(\n\t\t\t\"1: lwarx %[t],0,%[cnt]\\n\"\n\t\t\t\"addic %[t],%[t],1\\n\"\n\t\t\t\"stwcx. %[t],0,%[cnt]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t: [t] \"=&r\" (t), \"=m\" (v->cnt)\n\t\t\t: [cnt] \"r\" (&v->cnt), \"m\" (v->cnt)\n\t\t\t: \"cc\", \"xer\", \"memory\");\n}\n\nstatic inline void\nrte_atomic32_dec(rte_atomic32_t *v)\n{\n\tint t;\n\n\tasm volatile(\n\t\t\t\"1: lwarx %[t],0,%[cnt]\\n\"\n\t\t\t\"addic %[t],%[t],-1\\n\"\n\t\t\t\"stwcx. %[t],0,%[cnt]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t: [t] \"=&r\" (t), \"=m\" (v->cnt)\n\t\t\t: [cnt] \"r\" (&v->cnt), \"m\" (v->cnt)\n\t\t\t: \"cc\", \"xer\", \"memory\");\n}\n\nstatic inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)\n{\n\tint ret;\n\n\tasm volatile(\n\t\t\t\"\\n\\tlwsync\\n\"\n\t\t\t\"1: lwarx %[ret],0,%[cnt]\\n\"\n\t\t\t\"addic\t%[ret],%[ret],1\\n\"\n\t\t\t\"stwcx. %[ret],0,%[cnt]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t\"isync\\n\"\n\t\t\t: [ret] \"=&r\" (ret)\n\t\t\t: [cnt] \"r\" (&v->cnt)\n\t\t\t: \"cc\", \"xer\", \"memory\");\n\n\treturn (ret == 0);\n}\n\nstatic inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)\n{\n\tint ret;\n\n\tasm volatile(\n\t\t\t\"\\n\\tlwsync\\n\"\n\t\t\t\"1: lwarx %[ret],0,%[cnt]\\n\"\n\t\t\t\"addic %[ret],%[ret],-1\\n\"\n\t\t\t\"stwcx. %[ret],0,%[cnt]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t\"isync\\n\"\n\t\t\t: [ret] \"=&r\" (ret)\n\t\t\t: [cnt] \"r\" (&v->cnt)\n\t\t\t: \"cc\", \"xer\", \"memory\");\n\n\treturn (ret == 0);\n}\n/*------------------------- 64 bit atomic operations -------------------------*/\n\nstatic inline int\nrte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)\n{\n\tunsigned int ret = 0;\n\n\tasm volatile (\n\t\t\t\"\\tlwsync\\n\"\n\t\t\t\"1: ldarx %[ret], 0, %[dst]\\n\"\n\t\t\t\"cmpld %[exp], %[ret]\\n\"\n\t\t\t\"bne 2f\\n\"\n\t\t\t\"stdcx. %[src], 0, %[dst]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t\"li %[ret], 1\\n\"\n\t\t\t\"b 3f\\n\"\n\t\t\t\"2:\\n\"\n\t\t\t\"stdcx. %[ret], 0, %[dst]\\n\"\n\t\t\t\"li %[ret], 0\\n\"\n\t\t\t\"3:\\n\"\n\t\t\t\"isync\\n\"\n\t\t\t: [ret] \"=&r\" (ret), \"=m\" (*dst)\n\t\t\t: [dst] \"r\" (dst),\n\t\t\t [exp] \"r\" (exp),\n\t\t\t [src] \"r\" (src),\n\t\t\t \"m\" (*dst)\n\t\t\t: \"cc\", \"memory\");\n\treturn ret;\n}\n\nstatic inline void\nrte_atomic64_init(rte_atomic64_t *v)\n{\n\tv->cnt = 0;\n}\n\nstatic inline int64_t\nrte_atomic64_read(rte_atomic64_t *v)\n{\n\tlong ret;\n\n\tasm volatile(\"ld%U1%X1 %[ret],%[cnt]\"\n\t\t: [ret] \"=r\"(ret)\n\t\t: [cnt] \"m\"(v->cnt));\n\n\treturn ret;\n}\n\nstatic inline void\nrte_atomic64_set(rte_atomic64_t *v, int64_t new_value)\n{\n\tasm volatile(\"std%U0%X0 %[new_value],%[cnt]\"\n\t\t: [cnt] \"=m\"(v->cnt)\n\t\t: [new_value] \"r\"(new_value));\n}\n\nstatic inline void\nrte_atomic64_add(rte_atomic64_t *v, int64_t inc)\n{\n\tlong t;\n\n\tasm volatile(\n\t\t\t\"1: ldarx %[t],0,%[cnt]\\n\"\n\t\t\t\"add %[t],%[inc],%[t]\\n\"\n\t\t\t\"stdcx. %[t],0,%[cnt]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t: [t] \"=&r\" (t), \"=m\" (v->cnt)\n\t\t\t: [cnt] \"r\" (&v->cnt), [inc] \"r\" (inc), \"m\" (v->cnt)\n\t\t\t: \"cc\", \"memory\");\n}\n\nstatic inline void\nrte_atomic64_sub(rte_atomic64_t *v, int64_t dec)\n{\n\tlong t;\n\n\tasm volatile(\n\t\t\t\"1: ldarx %[t],0,%[cnt]\\n\"\n\t\t\t\"subf %[t],%[dec],%[t]\\n\"\n\t\t\t\"stdcx. %[t],0,%[cnt]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t: [t] \"=&r\" (t), \"+m\" (v->cnt)\n\t\t\t: [cnt] \"r\" (&v->cnt), [dec] \"r\" (dec), \"m\" (v->cnt)\n\t\t\t: \"cc\", \"memory\");\n}\n\nstatic inline void\nrte_atomic64_inc(rte_atomic64_t *v)\n{\n\tlong t;\n\n\tasm volatile(\n\t\t\t\"1: ldarx %[t],0,%[cnt]\\n\"\n\t\t\t\"addic %[t],%[t],1\\n\"\n\t\t\t\"stdcx. %[t],0,%[cnt]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t: [t] \"=&r\" (t), \"+m\" (v->cnt)\n\t\t\t: [cnt] \"r\" (&v->cnt), \"m\" (v->cnt)\n\t\t\t: \"cc\", \"xer\", \"memory\");\n}\n\nstatic inline void\nrte_atomic64_dec(rte_atomic64_t *v)\n{\n\tlong t;\n\n\tasm volatile(\n\t\t\t\"1: ldarx %[t],0,%[cnt]\\n\"\n\t\t\t\"addic %[t],%[t],-1\\n\"\n\t\t\t\"stdcx. %[t],0,%[cnt]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t: [t] \"=&r\" (t), \"+m\" (v->cnt)\n\t\t\t: [cnt] \"r\" (&v->cnt), \"m\" (v->cnt)\n\t\t\t: \"cc\", \"xer\", \"memory\");\n}\n\nstatic inline int64_t\nrte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)\n{\n\tlong ret;\n\n\tasm volatile(\n\t\t\t\"\\n\\tlwsync\\n\"\n\t\t\t\"1: ldarx %[ret],0,%[cnt]\\n\"\n\t\t\t\"add %[ret],%[inc],%[ret]\\n\"\n\t\t\t\"stdcx. %[ret],0,%[cnt]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t\"isync\\n\"\n\t\t\t: [ret] \"=&r\" (ret)\n\t\t\t: [inc] \"r\" (inc), [cnt] \"r\" (&v->cnt)\n\t\t\t: \"cc\", \"memory\");\n\n\treturn ret;\n}\n\nstatic inline int64_t\nrte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)\n{\n\tlong ret;\n\n\tasm volatile(\n\t\t\t\"\\n\\tlwsync\\n\"\n\t\t\t\"1: ldarx %[ret],0,%[cnt]\\n\"\n\t\t\t\"subf %[ret],%[dec],%[ret]\\n\"\n\t\t\t\"stdcx. %[ret],0,%[cnt]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t\"isync\\n\"\n\t\t\t: [ret] \"=&r\" (ret)\n\t\t\t: [dec] \"r\" (dec), [cnt] \"r\" (&v->cnt)\n\t\t\t: \"cc\", \"memory\");\n\n\treturn ret;\n}\n\nstatic inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)\n{\n\tlong ret;\n\n\tasm volatile(\n\t\t\t\"\\n\\tlwsync\\n\"\n\t\t\t\"1: ldarx %[ret],0,%[cnt]\\n\"\n\t\t\t\"addic %[ret],%[ret],1\\n\"\n\t\t\t\"stdcx. %[ret],0,%[cnt]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t\"isync\\n\"\n\t\t\t: [ret] \"=&r\" (ret)\n\t\t\t: [cnt] \"r\" (&v->cnt)\n\t\t\t: \"cc\", \"xer\", \"memory\");\n\n\treturn (ret == 0);\n}\n\nstatic inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)\n{\n\tlong ret;\n\n\tasm volatile(\n\t\t\t\"\\n\\tlwsync\\n\"\n\t\t\t\"1: ldarx %[ret],0,%[cnt]\\n\"\n\t\t\t\"addic %[ret],%[ret],-1\\n\"\n\t\t\t\"stdcx. %[ret],0,%[cnt]\\n\"\n\t\t\t\"bne- 1b\\n\"\n\t\t\t\"isync\\n\"\n\t\t\t: [ret] \"=&r\" (ret)\n\t\t\t: [cnt] \"r\" (&v->cnt)\n\t\t\t: \"cc\", \"xer\", \"memory\");\n\n\treturn (ret == 0);\n}\n\nstatic inline int rte_atomic64_test_and_set(rte_atomic64_t *v)\n{\n\treturn rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);\n}\n\n/**\n * Atomically set a 64-bit counter to 0.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void rte_atomic64_clear(rte_atomic64_t *v)\n{\n\tv->cnt = 0;\n}\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_ATOMIC_PPC_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/ppc_64/rte_byteorder.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) IBM Corporation 2014.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of IBM Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n/* Inspired from FreeBSD src/sys/powerpc/include/endian.h\n * Copyright (c) 1987, 1991, 1993\n * The Regents of the University of California. All rights reserved.\n*/\n\n#ifndef _RTE_BYTEORDER_PPC_64_H_\n#define _RTE_BYTEORDER_PPC_64_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_byteorder.h\"\n\n/*\n * An architecture-optimized byte swap for a 16-bit value.\n *\n * Do not use this function directly. The preferred function is rte_bswap16().\n */\nstatic inline uint16_t rte_arch_bswap16(uint16_t _x)\n{\n\treturn ((_x >> 8) | ((_x << 8) & 0xff00));\n}\n\n/*\n * An architecture-optimized byte swap for a 32-bit value.\n *\n * Do not use this function directly. The preferred function is rte_bswap32().\n */\nstatic inline uint32_t rte_arch_bswap32(uint32_t _x)\n{\n\treturn ((_x >> 24) | ((_x >> 8) & 0xff00) | ((_x << 8) & 0xff0000) |\n\t\t((_x << 24) & 0xff000000));\n}\n\n/*\n * An architecture-optimized byte swap for a 64-bit value.\n *\n * Do not use this function directly. The preferred function is rte_bswap64().\n */\n/* 64-bit mode */\nstatic inline uint64_t rte_arch_bswap64(uint64_t _x)\n{\n\treturn ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) |\n\t\t((_x >> 8) & 0xff000000) | ((_x << 8) & (0xffULL << 32)) |\n\t\t((_x << 24) & (0xffULL << 40)) |\n\t\t((_x << 40) & (0xffULL << 48)) | ((_x << 56)));\n}\n\n#ifndef RTE_FORCE_INTRINSICS\n#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ?\t\t\\\n\t\t\t\t rte_constant_bswap16(x) :\t\t\\\n\t\t\t\t rte_arch_bswap16(x)))\n\n#define rte_bswap32(x) ((uint32_t)(__builtin_constant_p(x) ?\t\t\\\n\t\t\t\t rte_constant_bswap32(x) :\t\t\\\n\t\t\t\t rte_arch_bswap32(x)))\n\n#define rte_bswap64(x) ((uint64_t)(__builtin_constant_p(x) ?\t\t\\\n\t\t\t\t rte_constant_bswap64(x) :\t\t\\\n\t\t\t\t rte_arch_bswap64(x)))\n#else\n/*\n * __builtin_bswap16 is only available gcc 4.8 and upwards\n */\n#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 8)\n#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ?\t\t\\\n\t\t\t\t rte_constant_bswap16(x) :\t\t\\\n\t\t\t\t rte_arch_bswap16(x)))\n#endif\n#endif\n\n/* Power 8 have both little endian and big endian mode\n * Power 7 only support big endian\n */\n#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n\n#define rte_cpu_to_le_16(x) (x)\n#define rte_cpu_to_le_32(x) (x)\n#define rte_cpu_to_le_64(x) (x)\n\n#define rte_cpu_to_be_16(x) rte_bswap16(x)\n#define rte_cpu_to_be_32(x) rte_bswap32(x)\n#define rte_cpu_to_be_64(x) rte_bswap64(x)\n\n#define rte_le_to_cpu_16(x) (x)\n#define rte_le_to_cpu_32(x) (x)\n#define rte_le_to_cpu_64(x) (x)\n\n#define rte_be_to_cpu_16(x) rte_bswap16(x)\n#define rte_be_to_cpu_32(x) rte_bswap32(x)\n#define rte_be_to_cpu_64(x) rte_bswap64(x)\n\n#else /* RTE_BIG_ENDIAN */\n\n#define rte_cpu_to_le_16(x) rte_bswap16(x)\n#define rte_cpu_to_le_32(x) rte_bswap32(x)\n#define rte_cpu_to_le_64(x) rte_bswap64(x)\n\n#define rte_cpu_to_be_16(x) (x)\n#define rte_cpu_to_be_32(x) (x)\n#define rte_cpu_to_be_64(x) (x)\n\n#define rte_le_to_cpu_16(x) rte_bswap16(x)\n#define rte_le_to_cpu_32(x) rte_bswap32(x)\n#define rte_le_to_cpu_64(x) rte_bswap64(x)\n\n#define rte_be_to_cpu_16(x) (x)\n#define rte_be_to_cpu_32(x) (x)\n#define rte_be_to_cpu_64(x) (x)\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_BYTEORDER_PPC_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/ppc_64/rte_cpuflags.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) IBM Corporation 2014.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of IBM Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_CPUFLAGS_PPC_64_H_\n#define _RTE_CPUFLAGS_PPC_64_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n#include \n#include \n\n#include \"generic/rte_cpuflags.h\"\n\n/* Symbolic values for the entries in the auxiliary table */\n#define AT_HWCAP 16\n#define AT_HWCAP2 26\n\n/* software based registers */\nenum cpu_register_t __RTE_REGISTER_UNDERLYING_TYPE {\n\tREG_HWCAP = 0,\n\tREG_HWCAP2,\n};\n\n/**\n * Enumeration of all CPU features supported\n */\nenum rte_cpu_flag_t __RTE_CPUFLAG_UNDERLYING_TYPE {\n\tRTE_CPUFLAG_PPC_LE = 0,\n\tRTE_CPUFLAG_TRUE_LE,\n\tRTE_CPUFLAG_PSERIES_PERFMON_COMPAT,\n\tRTE_CPUFLAG_VSX,\n\tRTE_CPUFLAG_ARCH_2_06,\n\tRTE_CPUFLAG_POWER6_EXT,\n\tRTE_CPUFLAG_DFP,\n\tRTE_CPUFLAG_PA6T,\n\tRTE_CPUFLAG_ARCH_2_05,\n\tRTE_CPUFLAG_ICACHE_SNOOP,\n\tRTE_CPUFLAG_SMT,\n\tRTE_CPUFLAG_BOOKE,\n\tRTE_CPUFLAG_CELLBE,\n\tRTE_CPUFLAG_POWER5_PLUS,\n\tRTE_CPUFLAG_POWER5,\n\tRTE_CPUFLAG_POWER4,\n\tRTE_CPUFLAG_NOTB,\n\tRTE_CPUFLAG_EFP_DOUBLE,\n\tRTE_CPUFLAG_EFP_SINGLE,\n\tRTE_CPUFLAG_SPE,\n\tRTE_CPUFLAG_UNIFIED_CACHE,\n\tRTE_CPUFLAG_4xxMAC,\n\tRTE_CPUFLAG_MMU,\n\tRTE_CPUFLAG_FPU,\n\tRTE_CPUFLAG_ALTIVEC,\n\tRTE_CPUFLAG_PPC601,\n\tRTE_CPUFLAG_PPC64,\n\tRTE_CPUFLAG_PPC32,\n\tRTE_CPUFLAG_TAR,\n\tRTE_CPUFLAG_LSEL,\n\tRTE_CPUFLAG_EBB,\n\tRTE_CPUFLAG_DSCR,\n\tRTE_CPUFLAG_HTM,\n\tRTE_CPUFLAG_ARCH_2_07,\n\t/* The last item */\n\tRTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */\n};\n\nstatic const struct feature_entry cpu_feature_table[] = {\n\tFEAT_DEF(PPC_LE, 0x00000001, 0, REG_HWCAP, 0)\n\tFEAT_DEF(TRUE_LE, 0x00000001, 0, REG_HWCAP, 1)\n\tFEAT_DEF(PSERIES_PERFMON_COMPAT, 0x00000001, 0, REG_HWCAP, 6)\n\tFEAT_DEF(VSX, 0x00000001, 0, REG_HWCAP, 7)\n\tFEAT_DEF(ARCH_2_06, 0x00000001, 0, REG_HWCAP, 8)\n\tFEAT_DEF(POWER6_EXT, 0x00000001, 0, REG_HWCAP, 9)\n\tFEAT_DEF(DFP, 0x00000001, 0, REG_HWCAP, 10)\n\tFEAT_DEF(PA6T, 0x00000001, 0, REG_HWCAP, 11)\n\tFEAT_DEF(ARCH_2_05, 0x00000001, 0, REG_HWCAP, 12)\n\tFEAT_DEF(ICACHE_SNOOP, 0x00000001, 0, REG_HWCAP, 13)\n\tFEAT_DEF(SMT, 0x00000001, 0, REG_HWCAP, 14)\n\tFEAT_DEF(BOOKE, 0x00000001, 0, REG_HWCAP, 15)\n\tFEAT_DEF(CELLBE, 0x00000001, 0, REG_HWCAP, 16)\n\tFEAT_DEF(POWER5_PLUS, 0x00000001, 0, REG_HWCAP, 17)\n\tFEAT_DEF(POWER5, 0x00000001, 0, REG_HWCAP, 18)\n\tFEAT_DEF(POWER4, 0x00000001, 0, REG_HWCAP, 19)\n\tFEAT_DEF(NOTB, 0x00000001, 0, REG_HWCAP, 20)\n\tFEAT_DEF(EFP_DOUBLE, 0x00000001, 0, REG_HWCAP, 21)\n\tFEAT_DEF(EFP_SINGLE, 0x00000001, 0, REG_HWCAP, 22)\n\tFEAT_DEF(SPE, 0x00000001, 0, REG_HWCAP, 23)\n\tFEAT_DEF(UNIFIED_CACHE, 0x00000001, 0, REG_HWCAP, 24)\n\tFEAT_DEF(4xxMAC, 0x00000001, 0, REG_HWCAP, 25)\n\tFEAT_DEF(MMU, 0x00000001, 0, REG_HWCAP, 26)\n\tFEAT_DEF(FPU, 0x00000001, 0, REG_HWCAP, 27)\n\tFEAT_DEF(ALTIVEC, 0x00000001, 0, REG_HWCAP, 28)\n\tFEAT_DEF(PPC601, 0x00000001, 0, REG_HWCAP, 29)\n\tFEAT_DEF(PPC64, 0x00000001, 0, REG_HWCAP, 30)\n\tFEAT_DEF(PPC32, 0x00000001, 0, REG_HWCAP, 31)\n\tFEAT_DEF(TAR, 0x00000001, 0, REG_HWCAP2, 26)\n\tFEAT_DEF(LSEL, 0x00000001, 0, REG_HWCAP2, 27)\n\tFEAT_DEF(EBB, 0x00000001, 0, REG_HWCAP2, 28)\n\tFEAT_DEF(DSCR, 0x00000001, 0, REG_HWCAP2, 29)\n\tFEAT_DEF(HTM, 0x00000001, 0, REG_HWCAP2, 30)\n\tFEAT_DEF(ARCH_2_07, 0x00000001, 0, REG_HWCAP2, 31)\n};\n\n/*\n * Read AUXV software register and get cpu features for Power\n */\nstatic inline void\nrte_cpu_get_features(__attribute__((unused)) uint32_t leaf,\n\t__attribute__((unused)) uint32_t subleaf, cpuid_registers_t out)\n{\n\tint auxv_fd;\n\tElf64_auxv_t auxv;\n\n\tauxv_fd = open(\"/proc/self/auxv\", O_RDONLY);\n\tassert(auxv_fd);\n\twhile (read(auxv_fd, &auxv,\n\t\tsizeof(Elf64_auxv_t)) == sizeof(Elf64_auxv_t)) {\n\t\tif (auxv.a_type == AT_HWCAP)\n\t\t\tout[REG_HWCAP] = auxv.a_un.a_val;\n\t\telse if (auxv.a_type == AT_HWCAP2)\n\t\t\tout[REG_HWCAP2] = auxv.a_un.a_val;\n\t}\n}\n\n/*\n * Checks if a particular flag is available on current machine.\n */\nstatic inline int\nrte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)\n{\n\tconst struct feature_entry *feat;\n\tcpuid_registers_t regs = {0};\n\n\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n\t\t/* Flag does not match anything in the feature tables */\n\t\treturn -ENOENT;\n\n\tfeat = &cpu_feature_table[feature];\n\n\tif (!feat->leaf)\n\t\t/* This entry in the table wasn't filled out! */\n\t\treturn -EFAULT;\n\n\t/* get the cpuid leaf containing the desired feature */\n\trte_cpu_get_features(feat->leaf, feat->subleaf, regs);\n\n\t/* check if the feature is enabled */\n\treturn (regs[feat->reg] >> feat->bit) & 1;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_CPUFLAGS_PPC_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/ppc_64/rte_cycles.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) IBM Corporation 2014.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of IBM Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_CYCLES_PPC_64_H_\n#define _RTE_CYCLES_PPC_64_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_cycles.h\"\n\n#include \n\n/**\n * Read the time base register.\n *\n * @return\n * The time base for this lcore.\n */\nstatic inline uint64_t\nrte_rdtsc(void)\n{\n\tunion {\n\t\tuint64_t tsc_64;\n\t\tstruct {\n#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n\t\t\tuint32_t hi_32;\n\t\t\tuint32_t lo_32;\n#else\n\t\t\tuint32_t lo_32;\n\t\t\tuint32_t hi_32;\n#endif\n\t\t};\n\t} tsc;\n\tuint32_t tmp;\n\n\tasm volatile(\n\t\t\t\"0:\\n\"\n\t\t\t\"mftbu %[hi32]\\n\"\n\t\t\t\"mftb %[lo32]\\n\"\n\t\t\t\"mftbu %[tmp]\\n\"\n\t\t\t\"cmpw %[tmp],%[hi32]\\n\"\n\t\t\t\"bne 0b\\n\"\n\t\t\t: [hi32] \"=r\"(tsc.hi_32), [lo32] \"=r\"(tsc.lo_32),\n\t\t\t[tmp] \"=r\"(tmp)\n\t\t );\n\treturn tsc.tsc_64;\n}\n\nstatic inline uint64_t\nrte_rdtsc_precise(void)\n{\n\trte_mb();\n\treturn rte_rdtsc();\n}\n\nstatic inline uint64_t\nrte_get_tsc_cycles(void) { return rte_rdtsc(); }\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_CYCLES_PPC_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/ppc_64/rte_memcpy.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) IBM Corporation 2014.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of IBM Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_MEMCPY_PPC_64_H_\n#define _RTE_MEMCPY_PPC_64_H_\n\n#include \n#include \n/*To include altivec.h, GCC version must >= 4.8 */\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_memcpy.h\"\n\nstatic inline void\nrte_mov16(uint8_t *dst, const uint8_t *src)\n{\n\tvec_vsx_st(vec_vsx_ld(0, src), 0, dst);\n}\n\nstatic inline void\nrte_mov32(uint8_t *dst, const uint8_t *src)\n{\n\tvec_vsx_st(vec_vsx_ld(0, src), 0, dst);\n\tvec_vsx_st(vec_vsx_ld(16, src), 16, dst);\n}\n\nstatic inline void\nrte_mov48(uint8_t *dst, const uint8_t *src)\n{\n\tvec_vsx_st(vec_vsx_ld(0, src), 0, dst);\n\tvec_vsx_st(vec_vsx_ld(16, src), 16, dst);\n\tvec_vsx_st(vec_vsx_ld(32, src), 32, dst);\n}\n\nstatic inline void\nrte_mov64(uint8_t *dst, const uint8_t *src)\n{\n\tvec_vsx_st(vec_vsx_ld(0, src), 0, dst);\n\tvec_vsx_st(vec_vsx_ld(16, src), 16, dst);\n\tvec_vsx_st(vec_vsx_ld(32, src), 32, dst);\n\tvec_vsx_st(vec_vsx_ld(48, src), 48, dst);\n}\n\nstatic inline void\nrte_mov128(uint8_t *dst, const uint8_t *src)\n{\n\tvec_vsx_st(vec_vsx_ld(0, src), 0, dst);\n\tvec_vsx_st(vec_vsx_ld(16, src), 16, dst);\n\tvec_vsx_st(vec_vsx_ld(32, src), 32, dst);\n\tvec_vsx_st(vec_vsx_ld(48, src), 48, dst);\n\tvec_vsx_st(vec_vsx_ld(64, src), 64, dst);\n\tvec_vsx_st(vec_vsx_ld(80, src), 80, dst);\n\tvec_vsx_st(vec_vsx_ld(96, src), 96, dst);\n\tvec_vsx_st(vec_vsx_ld(112, src), 112, dst);\n}\n\nstatic inline void\nrte_mov256(uint8_t *dst, const uint8_t *src)\n{\n\trte_mov128(dst, src);\n\trte_mov128(dst + 128, src + 128);\n}\n\n#define rte_memcpy(dst, src, n) \\\n\t({ (__builtin_constant_p(n)) ? \\\n\tmemcpy((dst), (src), (n)) : \\\n\trte_memcpy_func((dst), (src), (n)); })\n\nstatic inline void *\nrte_memcpy_func(void *dst, const void *src, size_t n)\n{\n\tvoid *ret = dst;\n\n\t/* We can't copy < 16 bytes using XMM registers so do it manually. */\n\tif (n < 16) {\n\t\tif (n & 0x01) {\n\t\t\t*(uint8_t *)dst = *(const uint8_t *)src;\n\t\t\tdst = (uint8_t *)dst + 1;\n\t\t\tsrc = (const uint8_t *)src + 1;\n\t\t}\n\t\tif (n & 0x02) {\n\t\t\t*(uint16_t *)dst = *(const uint16_t *)src;\n\t\t\tdst = (uint16_t *)dst + 1;\n\t\t\tsrc = (const uint16_t *)src + 1;\n\t\t}\n\t\tif (n & 0x04) {\n\t\t\t*(uint32_t *)dst = *(const uint32_t *)src;\n\t\t\tdst = (uint32_t *)dst + 1;\n\t\t\tsrc = (const uint32_t *)src + 1;\n\t\t}\n\t\tif (n & 0x08)\n\t\t\t*(uint64_t *)dst = *(const uint64_t *)src;\n\t\treturn ret;\n\t}\n\n\t/* Special fast cases for <= 128 bytes */\n\tif (n <= 32) {\n\t\trte_mov16((uint8_t *)dst, (const uint8_t *)src);\n\t\trte_mov16((uint8_t *)dst - 16 + n,\n\t\t\t(const uint8_t *)src - 16 + n);\n\t\treturn ret;\n\t}\n\n\tif (n <= 64) {\n\t\trte_mov32((uint8_t *)dst, (const uint8_t *)src);\n\t\trte_mov32((uint8_t *)dst - 32 + n,\n\t\t\t(const uint8_t *)src - 32 + n);\n\t\treturn ret;\n\t}\n\n\tif (n <= 128) {\n\t\trte_mov64((uint8_t *)dst, (const uint8_t *)src);\n\t\trte_mov64((uint8_t *)dst - 64 + n,\n\t\t\t(const uint8_t *)src - 64 + n);\n\t\treturn ret;\n\t}\n\n\t/*\n\t * For large copies > 128 bytes. This combination of 256, 64 and 16 byte\n\t * copies was found to be faster than doing 128 and 32 byte copies as\n\t * well.\n\t */\n\tfor ( ; n >= 256; n -= 256) {\n\t\trte_mov256((uint8_t *)dst, (const uint8_t *)src);\n\t\tdst = (uint8_t *)dst + 256;\n\t\tsrc = (const uint8_t *)src + 256;\n\t}\n\n\t/*\n\t * We split the remaining bytes (which will be less than 256) into\n\t * 64byte (2^6) chunks.\n\t * Using incrementing integers in the case labels of a switch statement\n\t * enourages the compiler to use a jump table. To get incrementing\n\t * integers, we shift the 2 relevant bits to the LSB position to first\n\t * get decrementing integers, and then subtract.\n\t */\n\tswitch (3 - (n >> 6)) {\n\tcase 0x00:\n\t\trte_mov64((uint8_t *)dst, (const uint8_t *)src);\n\t\tn -= 64;\n\t\tdst = (uint8_t *)dst + 64;\n\t\tsrc = (const uint8_t *)src + 64; /* fallthrough */\n\tcase 0x01:\n\t\trte_mov64((uint8_t *)dst, (const uint8_t *)src);\n\t\tn -= 64;\n\t\tdst = (uint8_t *)dst + 64;\n\t\tsrc = (const uint8_t *)src + 64; /* fallthrough */\n\tcase 0x02:\n\t\trte_mov64((uint8_t *)dst, (const uint8_t *)src);\n\t\tn -= 64;\n\t\tdst = (uint8_t *)dst + 64;\n\t\tsrc = (const uint8_t *)src + 64; /* fallthrough */\n\tdefault:\n\t\t;\n\t}\n\n\t/*\n\t * We split the remaining bytes (which will be less than 64) into\n\t * 16byte (2^4) chunks, using the same switch structure as above.\n\t */\n\tswitch (3 - (n >> 4)) {\n\tcase 0x00:\n\t\trte_mov16((uint8_t *)dst, (const uint8_t *)src);\n\t\tn -= 16;\n\t\tdst = (uint8_t *)dst + 16;\n\t\tsrc = (const uint8_t *)src + 16; /* fallthrough */\n\tcase 0x01:\n\t\trte_mov16((uint8_t *)dst, (const uint8_t *)src);\n\t\tn -= 16;\n\t\tdst = (uint8_t *)dst + 16;\n\t\tsrc = (const uint8_t *)src + 16; /* fallthrough */\n\tcase 0x02:\n\t\trte_mov16((uint8_t *)dst, (const uint8_t *)src);\n\t\tn -= 16;\n\t\tdst = (uint8_t *)dst + 16;\n\t\tsrc = (const uint8_t *)src + 16; /* fallthrough */\n\tdefault:\n\t\t;\n\t}\n\n\t/* Copy any remaining bytes, without going beyond end of buffers */\n\tif (n != 0)\n\t\trte_mov16((uint8_t *)dst - 16 + n,\n\t\t\t(const uint8_t *)src - 16 + n);\n\treturn ret;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_MEMCPY_PPC_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) IBM Corporation 2014.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of IBM Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_PREFETCH_PPC_64_H_\n#define _RTE_PREFETCH_PPC_64_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_prefetch.h\"\n\nstatic inline void rte_prefetch0(const volatile void *p)\n{\n\tasm volatile (\"dcbt 0,%[p],1\" : : [p] \"r\" (p));\n}\n\nstatic inline void rte_prefetch1(const volatile void *p)\n{\n\tasm volatile (\"dcbt 0,%[p],1\" : : [p] \"r\" (p));\n}\n\nstatic inline void rte_prefetch2(const volatile void *p)\n{\n\tasm volatile (\"dcbt 0,%[p],1\" : : [p] \"r\" (p));\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_PREFETCH_PPC_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/ppc_64/rte_rwlock.h", "content": "#ifndef _RTE_RWLOCK_PPC_64_H_\n#define _RTE_RWLOCK_PPC_64_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_rwlock.h\"\n\nstatic inline void\nrte_rwlock_read_lock_tm(rte_rwlock_t *rwl)\n{\n\trte_rwlock_read_lock(rwl);\n}\n\nstatic inline void\nrte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)\n{\n\trte_rwlock_read_unlock(rwl);\n}\n\nstatic inline void\nrte_rwlock_write_lock_tm(rte_rwlock_t *rwl)\n{\n\trte_rwlock_write_lock(rwl);\n}\n\nstatic inline void\nrte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)\n{\n\trte_rwlock_write_unlock(rwl);\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_RWLOCK_PPC_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/ppc_64/rte_spinlock.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) IBM Corporation 2014.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of IBM Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_SPINLOCK_PPC_64_H_\n#define _RTE_SPINLOCK_PPC_64_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \"generic/rte_spinlock.h\"\n\n/* Fixme: Use intrinsics to implement the spinlock on Power architecture */\n\n#ifndef RTE_FORCE_INTRINSICS\n\nstatic inline void\nrte_spinlock_lock(rte_spinlock_t *sl)\n{\n\twhile (__sync_lock_test_and_set(&sl->locked, 1))\n\t\twhile (sl->locked)\n\t\t\trte_pause();\n}\n\nstatic inline void\nrte_spinlock_unlock(rte_spinlock_t *sl)\n{\n\t__sync_lock_release(&sl->locked);\n}\n\nstatic inline int\nrte_spinlock_trylock(rte_spinlock_t *sl)\n{\n\treturn (__sync_lock_test_and_set(&sl->locked, 1) == 0);\n}\n\n#endif\n\nstatic inline int rte_tm_supported(void)\n{\n\treturn 0;\n}\n\nstatic inline void\nrte_spinlock_lock_tm(rte_spinlock_t *sl)\n{\n\trte_spinlock_lock(sl); /* fall-back */\n}\n\nstatic inline int\nrte_spinlock_trylock_tm(rte_spinlock_t *sl)\n{\n\treturn rte_spinlock_trylock(sl);\n}\n\nstatic inline void\nrte_spinlock_unlock_tm(rte_spinlock_t *sl)\n{\n\trte_spinlock_unlock(sl);\n}\n\nstatic inline void\nrte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)\n{\n\trte_spinlock_recursive_lock(slr); /* fall-back */\n}\n\nstatic inline void\nrte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)\n{\n\trte_spinlock_recursive_unlock(slr);\n}\n\nstatic inline int\nrte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)\n{\n\treturn rte_spinlock_recursive_trylock(slr);\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_SPINLOCK_PPC_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/tile/rte_atomic.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) EZchip Semiconductor Ltd. 2015.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of EZchip Semiconductor nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_ATOMIC_TILE_H_\n#define _RTE_ATOMIC_TILE_H_\n\n#ifndef RTE_FORCE_INTRINSICS\n# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_atomic.h\"\n\n/**\n * General memory barrier.\n *\n * Guarantees that the LOAD and STORE operations generated before the\n * barrier occur before the LOAD and STORE operations generated after.\n * This function is architecture dependent.\n */\nstatic inline void rte_mb(void)\n{\n\t__sync_synchronize();\n}\n\n/**\n * Write memory barrier.\n *\n * Guarantees that the STORE operations generated before the barrier\n * occur before the STORE operations generated after.\n * This function is architecture dependent.\n */\nstatic inline void rte_wmb(void)\n{\n\t__sync_synchronize();\n}\n\n/**\n * Read memory barrier.\n *\n * Guarantees that the LOAD operations generated before the barrier\n * occur before the LOAD operations generated after.\n * This function is architecture dependent.\n */\nstatic inline void rte_rmb(void)\n{\n\t__sync_synchronize();\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_ATOMIC_TILE_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/tile/rte_byteorder.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) EZchip Semiconductor Ltd. 2015.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of EZchip Semiconductor nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_BYTEORDER_TILE_H_\n#define _RTE_BYTEORDER_TILE_H_\n\n#ifndef RTE_FORCE_INTRINSICS\n# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_byteorder.h\"\n\n#if !(__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8))\n#define rte_bswap16(x) rte_constant_bswap16(x)\n#endif\n\n#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n\n#define rte_cpu_to_le_16(x) (x)\n#define rte_cpu_to_le_32(x) (x)\n#define rte_cpu_to_le_64(x) (x)\n\n#define rte_cpu_to_be_16(x) rte_bswap16(x)\n#define rte_cpu_to_be_32(x) rte_bswap32(x)\n#define rte_cpu_to_be_64(x) rte_bswap64(x)\n\n#define rte_le_to_cpu_16(x) (x)\n#define rte_le_to_cpu_32(x) (x)\n#define rte_le_to_cpu_64(x) (x)\n\n#define rte_be_to_cpu_16(x) rte_bswap16(x)\n#define rte_be_to_cpu_32(x) rte_bswap32(x)\n#define rte_be_to_cpu_64(x) rte_bswap64(x)\n\n#else /* RTE_BIG_ENDIAN */\n\n#define rte_cpu_to_le_16(x) rte_bswap16(x)\n#define rte_cpu_to_le_32(x) rte_bswap32(x)\n#define rte_cpu_to_le_64(x) rte_bswap64(x)\n\n#define rte_cpu_to_be_16(x) (x)\n#define rte_cpu_to_be_32(x) (x)\n#define rte_cpu_to_be_64(x) (x)\n\n#define rte_le_to_cpu_16(x) rte_bswap16(x)\n#define rte_le_to_cpu_32(x) rte_bswap32(x)\n#define rte_le_to_cpu_64(x) rte_bswap64(x)\n\n#define rte_be_to_cpu_16(x) (x)\n#define rte_be_to_cpu_32(x) (x)\n#define rte_be_to_cpu_64(x) (x)\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_BYTEORDER_TILE_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/tile/rte_cpuflags.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) EZchip Semiconductor Ltd. 2015.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of EZchip Semiconductor nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_CPUFLAGS_TILE_H_\n#define _RTE_CPUFLAGS_TILE_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n#include \n#include \n\n#include \"generic/rte_cpuflags.h\"\n\n/* software based registers */\nenum cpu_register_t __RTE_REGISTER_UNDERLYING_TYPE {\n\tREG_DUMMY = 0\n};\n\n/**\n * Enumeration of all CPU features supported\n */\nenum rte_cpu_flag_t __RTE_CPUFLAG_UNDERLYING_TYPE {\n\tRTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */\n};\n\nstatic const struct feature_entry cpu_feature_table[] = {\n};\n\n/*\n * Read AUXV software register and get cpu features for Power\n */\nstatic inline void\nrte_cpu_get_features(__attribute__((unused)) uint32_t leaf,\n\t\t __attribute__((unused)) uint32_t subleaf,\n\t\t __attribute__((unused)) cpuid_registers_t out)\n{\n}\n\n/*\n * Checks if a particular flag is available on current machine.\n */\nstatic inline int\nrte_cpu_get_flag_enabled(__attribute__((unused)) enum rte_cpu_flag_t feature)\n{\n\treturn -ENOENT;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_CPUFLAGS_TILE_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/tile/rte_cycles.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) EZchip Semiconductor Ltd. 2015.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of EZchip Semiconductor nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_CYCLES_TILE_H_\n#define _RTE_CYCLES_TILE_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n#include \"generic/rte_cycles.h\"\n\n/**\n * Read the time base register.\n *\n * @return\n * The time base for this lcore.\n */\nstatic inline uint64_t\nrte_rdtsc(void)\n{\n\treturn get_cycle_count();\n}\n\nstatic inline uint64_t\nrte_rdtsc_precise(void)\n{\n\trte_mb();\n\treturn rte_rdtsc();\n}\n\nstatic inline uint64_t\nrte_get_tsc_cycles(void) { return rte_rdtsc(); }\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_CYCLES_TILE_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/tile/rte_memcpy.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) EZchip Semiconductor Ltd. 2015.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of EZchip Semiconductor nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_MEMCPY_TILE_H_\n#define _RTE_MEMCPY_TILE_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n\n#include \"generic/rte_memcpy.h\"\n\nstatic inline void\nrte_mov16(uint8_t *dst, const uint8_t *src)\n{\n\tmemcpy(dst, src, 16);\n}\n\nstatic inline void\nrte_mov32(uint8_t *dst, const uint8_t *src)\n{\n\tmemcpy(dst, src, 32);\n}\n\nstatic inline void\nrte_mov48(uint8_t *dst, const uint8_t *src)\n{\n\tmemcpy(dst, src, 48);\n}\n\nstatic inline void\nrte_mov64(uint8_t *dst, const uint8_t *src)\n{\n\tmemcpy(dst, src, 64);\n}\n\nstatic inline void\nrte_mov128(uint8_t *dst, const uint8_t *src)\n{\n\tmemcpy(dst, src, 128);\n}\n\nstatic inline void\nrte_mov256(uint8_t *dst, const uint8_t *src)\n{\n\tmemcpy(dst, src, 256);\n}\n\n#define rte_memcpy(d, s, n)\tmemcpy((d), (s), (n))\n\nstatic inline void *\nrte_memcpy_func(void *dst, const void *src, size_t n)\n{\n\treturn memcpy(dst, src, n);\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_MEMCPY_TILE_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/tile/rte_prefetch.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) EZchip Semiconductor Ltd. 2015.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of EZchip Semiconductor nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_PREFETCH_TILE_H_\n#define _RTE_PREFETCH_TILE_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_prefetch.h\"\n\nstatic inline void rte_prefetch0(const volatile void *p)\n{\n\t__builtin_prefetch((const void *)(uintptr_t)p, 0, 3);\n}\n\nstatic inline void rte_prefetch1(const volatile void *p)\n{\n\t__builtin_prefetch((const void *)(uintptr_t)p, 0, 2);\n}\n\nstatic inline void rte_prefetch2(const volatile void *p)\n{\n\t__builtin_prefetch((const void *)(uintptr_t)p, 0, 1);\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_PREFETCH_TILE_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/tile/rte_rwlock.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) EZchip Semiconductor Ltd. 2015.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of EZchip Semiconductor nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_RWLOCK_TILE_H_\n#define _RTE_RWLOCK_TILE_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_rwlock.h\"\n\nstatic inline void\nrte_rwlock_read_lock_tm(rte_rwlock_t *rwl)\n{\n\trte_rwlock_read_lock(rwl);\n}\n\nstatic inline void\nrte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)\n{\n\trte_rwlock_read_unlock(rwl);\n}\n\nstatic inline void\nrte_rwlock_write_lock_tm(rte_rwlock_t *rwl)\n{\n\trte_rwlock_write_lock(rwl);\n}\n\nstatic inline void\nrte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)\n{\n\trte_rwlock_write_unlock(rwl);\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_RWLOCK_TILE_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/tile/rte_spinlock.h", "content": "/*\n * BSD LICENSE\n *\n * Copyright (C) EZchip Semiconductor Ltd. 2015.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of EZchip Semiconductor nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*/\n\n#ifndef _RTE_SPINLOCK_TILE_H_\n#define _RTE_SPINLOCK_TILE_H_\n\n#ifndef RTE_FORCE_INTRINSICS\n# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \"generic/rte_spinlock.h\"\n\nstatic inline int rte_tm_supported(void)\n{\n\treturn 0;\n}\n\nstatic inline void\nrte_spinlock_lock_tm(rte_spinlock_t *sl)\n{\n\trte_spinlock_lock(sl); /* fall-back */\n}\n\nstatic inline int\nrte_spinlock_trylock_tm(rte_spinlock_t *sl)\n{\n\treturn rte_spinlock_trylock(sl);\n}\n\nstatic inline void\nrte_spinlock_unlock_tm(rte_spinlock_t *sl)\n{\n\trte_spinlock_unlock(sl);\n}\n\nstatic inline void\nrte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)\n{\n\trte_spinlock_recursive_lock(slr); /* fall-back */\n}\n\nstatic inline void\nrte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)\n{\n\trte_spinlock_recursive_unlock(slr);\n}\n\nstatic inline int\nrte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)\n{\n\treturn rte_spinlock_recursive_trylock(slr);\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_SPINLOCK_TILE_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_atomic.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ATOMIC_X86_H_\n#define _RTE_ATOMIC_X86_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \"generic/rte_atomic.h\"\n\n#if RTE_MAX_LCORE == 1\n#define MPLOCKED /**< No need to insert MP lock prefix. */\n#else\n#define MPLOCKED \"lock ; \" /**< Insert MP lock prefix. */\n#endif\n\n#define\trte_mb() _mm_mfence()\n\n#define\trte_wmb() _mm_sfence()\n\n#define\trte_rmb() _mm_lfence()\n\n/*------------------------- 16 bit atomic operations -------------------------*/\n\n#ifndef RTE_FORCE_INTRINSICS\nstatic inline int\nrte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)\n{\n\tuint8_t res;\n\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"cmpxchgw %[src], %[dst];\"\n\t\t\t\"sete %[res];\"\n\t\t\t: [res] \"=a\" (res), /* output */\n\t\t\t [dst] \"=m\" (*dst)\n\t\t\t: [src] \"r\" (src), /* input */\n\t\t\t \"a\" (exp),\n\t\t\t \"m\" (*dst)\n\t\t\t: \"memory\"); /* no-clobber list */\n\treturn res;\n}\n\nstatic inline int rte_atomic16_test_and_set(rte_atomic16_t *v)\n{\n\treturn rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);\n}\n\nstatic inline void\nrte_atomic16_inc(rte_atomic16_t *v)\n{\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"incw %[cnt]\"\n\t\t\t: [cnt] \"=m\" (v->cnt) /* output */\n\t\t\t: \"m\" (v->cnt) /* input */\n\t\t\t);\n}\n\nstatic inline void\nrte_atomic16_dec(rte_atomic16_t *v)\n{\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"decw %[cnt]\"\n\t\t\t: [cnt] \"=m\" (v->cnt) /* output */\n\t\t\t: \"m\" (v->cnt) /* input */\n\t\t\t);\n}\n\nstatic inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)\n{\n\tuint8_t ret;\n\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"incw %[cnt] ; \"\n\t\t\t\"sete %[ret]\"\n\t\t\t: [cnt] \"+m\" (v->cnt), /* output */\n\t\t\t [ret] \"=qm\" (ret)\n\t\t\t);\n\treturn (ret != 0);\n}\n\nstatic inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)\n{\n\tuint8_t ret;\n\n\tasm volatile(MPLOCKED\n\t\t\t\"decw %[cnt] ; \"\n\t\t\t\"sete %[ret]\"\n\t\t\t: [cnt] \"+m\" (v->cnt), /* output */\n\t\t\t [ret] \"=qm\" (ret)\n\t\t\t);\n\treturn (ret != 0);\n}\n\n/*------------------------- 32 bit atomic operations -------------------------*/\n\nstatic inline int\nrte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)\n{\n\tuint8_t res;\n\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"cmpxchgl %[src], %[dst];\"\n\t\t\t\"sete %[res];\"\n\t\t\t: [res] \"=a\" (res), /* output */\n\t\t\t [dst] \"=m\" (*dst)\n\t\t\t: [src] \"r\" (src), /* input */\n\t\t\t \"a\" (exp),\n\t\t\t \"m\" (*dst)\n\t\t\t: \"memory\"); /* no-clobber list */\n\treturn res;\n}\n\nstatic inline int rte_atomic32_test_and_set(rte_atomic32_t *v)\n{\n\treturn rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);\n}\n\nstatic inline void\nrte_atomic32_inc(rte_atomic32_t *v)\n{\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"incl %[cnt]\"\n\t\t\t: [cnt] \"=m\" (v->cnt) /* output */\n\t\t\t: \"m\" (v->cnt) /* input */\n\t\t\t);\n}\n\nstatic inline void\nrte_atomic32_dec(rte_atomic32_t *v)\n{\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"decl %[cnt]\"\n\t\t\t: [cnt] \"=m\" (v->cnt) /* output */\n\t\t\t: \"m\" (v->cnt) /* input */\n\t\t\t);\n}\n\nstatic inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)\n{\n\tuint8_t ret;\n\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"incl %[cnt] ; \"\n\t\t\t\"sete %[ret]\"\n\t\t\t: [cnt] \"+m\" (v->cnt), /* output */\n\t\t\t [ret] \"=qm\" (ret)\n\t\t\t);\n\treturn (ret != 0);\n}\n\nstatic inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)\n{\n\tuint8_t ret;\n\n\tasm volatile(MPLOCKED\n\t\t\t\"decl %[cnt] ; \"\n\t\t\t\"sete %[ret]\"\n\t\t\t: [cnt] \"+m\" (v->cnt), /* output */\n\t\t\t [ret] \"=qm\" (ret)\n\t\t\t);\n\treturn (ret != 0);\n}\n#endif\n\n#ifdef RTE_ARCH_I686\n#include \"rte_atomic_32.h\"\n#else\n#include \"rte_atomic_64.h\"\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_ATOMIC_X86_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_atomic_32.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Inspired from FreeBSD src/sys/i386/include/atomic.h\n * Copyright (c) 1998 Doug Rabson\n * All rights reserved.\n */\n\n#ifndef _RTE_ATOMIC_I686_H_\n#define _RTE_ATOMIC_I686_H_\n\n/*------------------------- 64 bit atomic operations -------------------------*/\n\n#ifndef RTE_FORCE_INTRINSICS\nstatic inline int\nrte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)\n{\n\tuint8_t res;\n\tunion {\n\t\tstruct {\n\t\t\tuint32_t l32;\n\t\t\tuint32_t h32;\n\t\t};\n\t\tuint64_t u64;\n\t} _exp, _src;\n\n\t_exp.u64 = exp;\n\t_src.u64 = src;\n\n#ifndef __PIC__\n asm volatile (\n MPLOCKED\n \"cmpxchg8b (%[dst]);\"\n \"setz %[res];\"\n : [res] \"=a\" (res) /* result in eax */\n : [dst] \"S\" (dst), /* esi */\n \"b\" (_src.l32), /* ebx */\n \"c\" (_src.h32), /* ecx */\n \"a\" (_exp.l32), /* eax */\n \"d\" (_exp.h32) /* edx */\n\t\t\t: \"memory\" ); /* no-clobber list */\n#else\n\tasm volatile (\n \"mov %%ebx, %%edi\\n\"\n\t\t\tMPLOCKED\n\t\t\t\"cmpxchg8b (%[dst]);\"\n\t\t\t\"setz %[res];\"\n \"xchgl %%ebx, %%edi;\\n\"\n\t\t\t: [res] \"=a\" (res) /* result in eax */\n\t\t\t: [dst] \"S\" (dst), /* esi */\n\t\t\t \"D\" (_src.l32), /* ebx */\n\t\t\t \"c\" (_src.h32), /* ecx */\n\t\t\t \"a\" (_exp.l32), /* eax */\n\t\t\t \"d\" (_exp.h32) /* edx */\n\t\t\t: \"memory\" ); /* no-clobber list */\n#endif\n\n\treturn res;\n}\n\nstatic inline void\nrte_atomic64_init(rte_atomic64_t *v)\n{\n\tint success = 0;\n\tuint64_t tmp;\n\n\twhile (success == 0) {\n\t\ttmp = v->cnt;\n\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n\t\t tmp, 0);\n\t}\n}\n\nstatic inline int64_t\nrte_atomic64_read(rte_atomic64_t *v)\n{\n\tint success = 0;\n\tuint64_t tmp;\n\n\twhile (success == 0) {\n\t\ttmp = v->cnt;\n\t\t/* replace the value by itself */\n\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n\t\t tmp, tmp);\n\t}\n\treturn tmp;\n}\n\nstatic inline void\nrte_atomic64_set(rte_atomic64_t *v, int64_t new_value)\n{\n\tint success = 0;\n\tuint64_t tmp;\n\n\twhile (success == 0) {\n\t\ttmp = v->cnt;\n\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n\t\t tmp, new_value);\n\t}\n}\n\nstatic inline void\nrte_atomic64_add(rte_atomic64_t *v, int64_t inc)\n{\n\tint success = 0;\n\tuint64_t tmp;\n\n\twhile (success == 0) {\n\t\ttmp = v->cnt;\n\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n\t\t tmp, tmp + inc);\n\t}\n}\n\nstatic inline void\nrte_atomic64_sub(rte_atomic64_t *v, int64_t dec)\n{\n\tint success = 0;\n\tuint64_t tmp;\n\n\twhile (success == 0) {\n\t\ttmp = v->cnt;\n\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n\t\t tmp, tmp - dec);\n\t}\n}\n\nstatic inline void\nrte_atomic64_inc(rte_atomic64_t *v)\n{\n\trte_atomic64_add(v, 1);\n}\n\nstatic inline void\nrte_atomic64_dec(rte_atomic64_t *v)\n{\n\trte_atomic64_sub(v, 1);\n}\n\nstatic inline int64_t\nrte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)\n{\n\tint success = 0;\n\tuint64_t tmp;\n\n\twhile (success == 0) {\n\t\ttmp = v->cnt;\n\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n\t\t tmp, tmp + inc);\n\t}\n\n\treturn tmp + inc;\n}\n\nstatic inline int64_t\nrte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)\n{\n\tint success = 0;\n\tuint64_t tmp;\n\n\twhile (success == 0) {\n\t\ttmp = v->cnt;\n\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n\t\t tmp, tmp - dec);\n\t}\n\n\treturn tmp - dec;\n}\n\nstatic inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)\n{\n\treturn rte_atomic64_add_return(v, 1) == 0;\n}\n\nstatic inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)\n{\n\treturn rte_atomic64_sub_return(v, 1) == 0;\n}\n\nstatic inline int rte_atomic64_test_and_set(rte_atomic64_t *v)\n{\n\treturn rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);\n}\n\nstatic inline void rte_atomic64_clear(rte_atomic64_t *v)\n{\n\trte_atomic64_set(v, 0);\n}\n#endif\n\n#endif /* _RTE_ATOMIC_I686_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_atomic_64.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Inspired from FreeBSD src/sys/amd64/include/atomic.h\n * Copyright (c) 1998 Doug Rabson\n * All rights reserved.\n */\n\n#ifndef _RTE_ATOMIC_X86_64_H_\n#define _RTE_ATOMIC_X86_64_H_\n\n/*------------------------- 64 bit atomic operations -------------------------*/\n\n#ifndef RTE_FORCE_INTRINSICS\nstatic inline int\nrte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)\n{\n\tuint8_t res;\n\n\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"cmpxchgq %[src], %[dst];\"\n\t\t\t\"sete %[res];\"\n\t\t\t: [res] \"=a\" (res), /* output */\n\t\t\t [dst] \"=m\" (*dst)\n\t\t\t: [src] \"r\" (src), /* input */\n\t\t\t \"a\" (exp),\n\t\t\t \"m\" (*dst)\n\t\t\t: \"memory\"); /* no-clobber list */\n\n\treturn res;\n}\n\nstatic inline void\nrte_atomic64_init(rte_atomic64_t *v)\n{\n\tv->cnt = 0;\n}\n\nstatic inline int64_t\nrte_atomic64_read(rte_atomic64_t *v)\n{\n\treturn v->cnt;\n}\n\nstatic inline void\nrte_atomic64_set(rte_atomic64_t *v, int64_t new_value)\n{\n\tv->cnt = new_value;\n}\n\nstatic inline void\nrte_atomic64_add(rte_atomic64_t *v, int64_t inc)\n{\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"addq %[inc], %[cnt]\"\n\t\t\t: [cnt] \"=m\" (v->cnt) /* output */\n\t\t\t: [inc] \"ir\" (inc), /* input */\n\t\t\t \"m\" (v->cnt)\n\t\t\t);\n}\n\nstatic inline void\nrte_atomic64_sub(rte_atomic64_t *v, int64_t dec)\n{\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"subq %[dec], %[cnt]\"\n\t\t\t: [cnt] \"=m\" (v->cnt) /* output */\n\t\t\t: [dec] \"ir\" (dec), /* input */\n\t\t\t \"m\" (v->cnt)\n\t\t\t);\n}\n\nstatic inline void\nrte_atomic64_inc(rte_atomic64_t *v)\n{\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"incq %[cnt]\"\n\t\t\t: [cnt] \"=m\" (v->cnt) /* output */\n\t\t\t: \"m\" (v->cnt) /* input */\n\t\t\t);\n}\n\nstatic inline void\nrte_atomic64_dec(rte_atomic64_t *v)\n{\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"decq %[cnt]\"\n\t\t\t: [cnt] \"=m\" (v->cnt) /* output */\n\t\t\t: \"m\" (v->cnt) /* input */\n\t\t\t);\n}\n\nstatic inline int64_t\nrte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)\n{\n\tint64_t prev = inc;\n\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"xaddq %[prev], %[cnt]\"\n\t\t\t: [prev] \"+r\" (prev), /* output */\n\t\t\t [cnt] \"=m\" (v->cnt)\n\t\t\t: \"m\" (v->cnt) /* input */\n\t\t\t);\n\treturn prev + inc;\n}\n\nstatic inline int64_t\nrte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)\n{\n\treturn rte_atomic64_add_return(v, -dec);\n}\n\nstatic inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)\n{\n\tuint8_t ret;\n\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"incq %[cnt] ; \"\n\t\t\t\"sete %[ret]\"\n\t\t\t: [cnt] \"+m\" (v->cnt), /* output */\n\t\t\t [ret] \"=qm\" (ret)\n\t\t\t);\n\n\treturn ret != 0;\n}\n\nstatic inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)\n{\n\tuint8_t ret;\n\n\tasm volatile(\n\t\t\tMPLOCKED\n\t\t\t\"decq %[cnt] ; \"\n\t\t\t\"sete %[ret]\"\n\t\t\t: [cnt] \"+m\" (v->cnt), /* output */\n\t\t\t [ret] \"=qm\" (ret)\n\t\t\t);\n\treturn ret != 0;\n}\n\nstatic inline int rte_atomic64_test_and_set(rte_atomic64_t *v)\n{\n\treturn rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);\n}\n\nstatic inline void rte_atomic64_clear(rte_atomic64_t *v)\n{\n\tv->cnt = 0;\n}\n#endif\n\n#endif /* _RTE_ATOMIC_X86_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_byteorder.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_BYTEORDER_X86_H_\n#define _RTE_BYTEORDER_X86_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_byteorder.h\"\n\n#ifndef RTE_BYTE_ORDER\n#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN\n#endif\n\n/*\n * An architecture-optimized byte swap for a 16-bit value.\n *\n * Do not use this function directly. The preferred function is rte_bswap16().\n */\nstatic inline uint16_t rte_arch_bswap16(uint16_t _x)\n{\n\tregister uint16_t x = _x;\n\tasm volatile (\"xchgb %b[x1],%h[x2]\"\n\t\t : [x1] \"=Q\" (x)\n\t\t : [x2] \"0\" (x)\n\t\t );\n\treturn x;\n}\n\n/*\n * An architecture-optimized byte swap for a 32-bit value.\n *\n * Do not use this function directly. The preferred function is rte_bswap32().\n */\nstatic inline uint32_t rte_arch_bswap32(uint32_t _x)\n{\n\tregister uint32_t x = _x;\n\tasm volatile (\"bswap %[x]\"\n\t\t : [x] \"+r\" (x)\n\t\t );\n\treturn x;\n}\n\n#ifndef RTE_FORCE_INTRINSICS\n#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ?\t\t\\\n\t\t\t\t rte_constant_bswap16(x) :\t\t\\\n\t\t\t\t rte_arch_bswap16(x)))\n\n#define rte_bswap32(x) ((uint32_t)(__builtin_constant_p(x) ?\t\t\\\n\t\t\t\t rte_constant_bswap32(x) :\t\t\\\n\t\t\t\t rte_arch_bswap32(x)))\n\n#define rte_bswap64(x) ((uint64_t)(__builtin_constant_p(x) ?\t\t\\\n\t\t\t\t rte_constant_bswap64(x) :\t\t\\\n\t\t\t\t rte_arch_bswap64(x)))\n#else\n/*\n * __builtin_bswap16 is only available gcc 4.8 and upwards\n */\n#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 8)\n#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ?\t\t\\\n\t\t\t\t rte_constant_bswap16(x) :\t\t\\\n\t\t\t\t rte_arch_bswap16(x)))\n#endif\n#endif\n\n#define rte_cpu_to_le_16(x) (x)\n#define rte_cpu_to_le_32(x) (x)\n#define rte_cpu_to_le_64(x) (x)\n\n#define rte_cpu_to_be_16(x) rte_bswap16(x)\n#define rte_cpu_to_be_32(x) rte_bswap32(x)\n#define rte_cpu_to_be_64(x) rte_bswap64(x)\n\n#define rte_le_to_cpu_16(x) (x)\n#define rte_le_to_cpu_32(x) (x)\n#define rte_le_to_cpu_64(x) (x)\n\n#define rte_be_to_cpu_16(x) rte_bswap16(x)\n#define rte_be_to_cpu_32(x) rte_bswap32(x)\n#define rte_be_to_cpu_64(x) rte_bswap64(x)\n\n#ifdef RTE_ARCH_I686\n#include \"rte_byteorder_32.h\"\n#else\n#include \"rte_byteorder_64.h\"\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_BYTEORDER_X86_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_byteorder_32.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_BYTEORDER_I686_H_\n#define _RTE_BYTEORDER_I686_H_\n\n/*\n * An architecture-optimized byte swap for a 64-bit value.\n *\n * Do not use this function directly. The preferred function is rte_bswap64().\n */\n/* Compat./Leg. mode */\nstatic inline uint64_t rte_arch_bswap64(uint64_t x)\n{\n\tuint64_t ret = 0;\n\tret |= ((uint64_t)rte_arch_bswap32(x & 0xffffffffUL) << 32);\n\tret |= ((uint64_t)rte_arch_bswap32((x >> 32) & 0xffffffffUL));\n\treturn ret;\n}\n\n#endif /* _RTE_BYTEORDER_I686_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_byteorder_64.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_BYTEORDER_X86_64_H_\n#define _RTE_BYTEORDER_X86_64_H_\n\n/*\n * An architecture-optimized byte swap for a 64-bit value.\n *\n * Do not use this function directly. The preferred function is rte_bswap64().\n */\n/* 64-bit mode */\nstatic inline uint64_t rte_arch_bswap64(uint64_t _x)\n{\n\tregister uint64_t x = _x;\n\tasm volatile (\"bswap %[x]\"\n\t\t : [x] \"+r\" (x)\n\t\t );\n\treturn x;\n}\n\n#endif /* _RTE_BYTEORDER_X86_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_cpuflags.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_CPUFLAGS_X86_64_H_\n#define _RTE_CPUFLAGS_X86_64_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n#include \n#include \n\n#include \"generic/rte_cpuflags.h\"\n\nenum rte_cpu_flag_t __RTE_CPUFLAG_UNDERLYING_TYPE {\n\t/* (EAX 01h) ECX features*/\n\tRTE_CPUFLAG_SSE3 = 0, /**< SSE3 */\n\tRTE_CPUFLAG_PCLMULQDQ, /**< PCLMULQDQ */\n\tRTE_CPUFLAG_DTES64, /**< DTES64 */\n\tRTE_CPUFLAG_MONITOR, /**< MONITOR */\n\tRTE_CPUFLAG_DS_CPL, /**< DS_CPL */\n\tRTE_CPUFLAG_VMX, /**< VMX */\n\tRTE_CPUFLAG_SMX, /**< SMX */\n\tRTE_CPUFLAG_EIST, /**< EIST */\n\tRTE_CPUFLAG_TM2, /**< TM2 */\n\tRTE_CPUFLAG_SSSE3, /**< SSSE3 */\n\tRTE_CPUFLAG_CNXT_ID, /**< CNXT_ID */\n\tRTE_CPUFLAG_FMA, /**< FMA */\n\tRTE_CPUFLAG_CMPXCHG16B, /**< CMPXCHG16B */\n\tRTE_CPUFLAG_XTPR, /**< XTPR */\n\tRTE_CPUFLAG_PDCM, /**< PDCM */\n\tRTE_CPUFLAG_PCID, /**< PCID */\n\tRTE_CPUFLAG_DCA, /**< DCA */\n\tRTE_CPUFLAG_SSE4_1, /**< SSE4_1 */\n\tRTE_CPUFLAG_SSE4_2, /**< SSE4_2 */\n\tRTE_CPUFLAG_X2APIC, /**< X2APIC */\n\tRTE_CPUFLAG_MOVBE, /**< MOVBE */\n\tRTE_CPUFLAG_POPCNT, /**< POPCNT */\n\tRTE_CPUFLAG_TSC_DEADLINE, /**< TSC_DEADLINE */\n\tRTE_CPUFLAG_AES, /**< AES */\n\tRTE_CPUFLAG_XSAVE, /**< XSAVE */\n\tRTE_CPUFLAG_OSXSAVE, /**< OSXSAVE */\n\tRTE_CPUFLAG_AVX, /**< AVX */\n\tRTE_CPUFLAG_F16C, /**< F16C */\n\tRTE_CPUFLAG_RDRAND, /**< RDRAND */\n\n\t/* (EAX 01h) EDX features */\n\tRTE_CPUFLAG_FPU, /**< FPU */\n\tRTE_CPUFLAG_VME, /**< VME */\n\tRTE_CPUFLAG_DE, /**< DE */\n\tRTE_CPUFLAG_PSE, /**< PSE */\n\tRTE_CPUFLAG_TSC, /**< TSC */\n\tRTE_CPUFLAG_MSR, /**< MSR */\n\tRTE_CPUFLAG_PAE, /**< PAE */\n\tRTE_CPUFLAG_MCE, /**< MCE */\n\tRTE_CPUFLAG_CX8, /**< CX8 */\n\tRTE_CPUFLAG_APIC, /**< APIC */\n\tRTE_CPUFLAG_SEP, /**< SEP */\n\tRTE_CPUFLAG_MTRR, /**< MTRR */\n\tRTE_CPUFLAG_PGE, /**< PGE */\n\tRTE_CPUFLAG_MCA, /**< MCA */\n\tRTE_CPUFLAG_CMOV, /**< CMOV */\n\tRTE_CPUFLAG_PAT, /**< PAT */\n\tRTE_CPUFLAG_PSE36, /**< PSE36 */\n\tRTE_CPUFLAG_PSN, /**< PSN */\n\tRTE_CPUFLAG_CLFSH, /**< CLFSH */\n\tRTE_CPUFLAG_DS, /**< DS */\n\tRTE_CPUFLAG_ACPI, /**< ACPI */\n\tRTE_CPUFLAG_MMX, /**< MMX */\n\tRTE_CPUFLAG_FXSR, /**< FXSR */\n\tRTE_CPUFLAG_SSE, /**< SSE */\n\tRTE_CPUFLAG_SSE2, /**< SSE2 */\n\tRTE_CPUFLAG_SS, /**< SS */\n\tRTE_CPUFLAG_HTT, /**< HTT */\n\tRTE_CPUFLAG_TM, /**< TM */\n\tRTE_CPUFLAG_PBE, /**< PBE */\n\n\t/* (EAX 06h) EAX features */\n\tRTE_CPUFLAG_DIGTEMP, /**< DIGTEMP */\n\tRTE_CPUFLAG_TRBOBST, /**< TRBOBST */\n\tRTE_CPUFLAG_ARAT, /**< ARAT */\n\tRTE_CPUFLAG_PLN, /**< PLN */\n\tRTE_CPUFLAG_ECMD, /**< ECMD */\n\tRTE_CPUFLAG_PTM, /**< PTM */\n\n\t/* (EAX 06h) ECX features */\n\tRTE_CPUFLAG_MPERF_APERF_MSR, /**< MPERF_APERF_MSR */\n\tRTE_CPUFLAG_ACNT2, /**< ACNT2 */\n\tRTE_CPUFLAG_ENERGY_EFF, /**< ENERGY_EFF */\n\n\t/* (EAX 07h, ECX 0h) EBX features */\n\tRTE_CPUFLAG_FSGSBASE, /**< FSGSBASE */\n\tRTE_CPUFLAG_BMI1, /**< BMI1 */\n\tRTE_CPUFLAG_HLE, /**< Hardware Lock elision */\n\tRTE_CPUFLAG_AVX2, /**< AVX2 */\n\tRTE_CPUFLAG_SMEP, /**< SMEP */\n\tRTE_CPUFLAG_BMI2, /**< BMI2 */\n\tRTE_CPUFLAG_ERMS, /**< ERMS */\n\tRTE_CPUFLAG_INVPCID, /**< INVPCID */\n\tRTE_CPUFLAG_RTM, /**< Transactional memory */\n\n\t/* (EAX 80000001h) ECX features */\n\tRTE_CPUFLAG_LAHF_SAHF, /**< LAHF_SAHF */\n\tRTE_CPUFLAG_LZCNT, /**< LZCNT */\n\n\t/* (EAX 80000001h) EDX features */\n\tRTE_CPUFLAG_SYSCALL, /**< SYSCALL */\n\tRTE_CPUFLAG_XD, /**< XD */\n\tRTE_CPUFLAG_1GB_PG, /**< 1GB_PG */\n\tRTE_CPUFLAG_RDTSCP, /**< RDTSCP */\n\tRTE_CPUFLAG_EM64T, /**< EM64T */\n\n\t/* (EAX 80000007h) EDX features */\n\tRTE_CPUFLAG_INVTSC, /**< INVTSC */\n\n\t/* The last item */\n\tRTE_CPUFLAG_NUMFLAGS, /**< This should always be the last! */\n};\n\nenum cpu_register_t __RTE_REGISTER_UNDERLYING_TYPE {\n\tRTE_REG_EAX = 0,\n\tRTE_REG_EBX,\n\tRTE_REG_ECX,\n\tRTE_REG_EDX,\n};\n\nstatic const struct feature_entry cpu_feature_table[] = {\n\tFEAT_DEF(SSE3, 0x00000001, 0, RTE_REG_ECX, 0)\n\tFEAT_DEF(PCLMULQDQ, 0x00000001, 0, RTE_REG_ECX, 1)\n\tFEAT_DEF(DTES64, 0x00000001, 0, RTE_REG_ECX, 2)\n\tFEAT_DEF(MONITOR, 0x00000001, 0, RTE_REG_ECX, 3)\n\tFEAT_DEF(DS_CPL, 0x00000001, 0, RTE_REG_ECX, 4)\n\tFEAT_DEF(VMX, 0x00000001, 0, RTE_REG_ECX, 5)\n\tFEAT_DEF(SMX, 0x00000001, 0, RTE_REG_ECX, 6)\n\tFEAT_DEF(EIST, 0x00000001, 0, RTE_REG_ECX, 7)\n\tFEAT_DEF(TM2, 0x00000001, 0, RTE_REG_ECX, 8)\n\tFEAT_DEF(SSSE3, 0x00000001, 0, RTE_REG_ECX, 9)\n\tFEAT_DEF(CNXT_ID, 0x00000001, 0, RTE_REG_ECX, 10)\n\tFEAT_DEF(FMA, 0x00000001, 0, RTE_REG_ECX, 12)\n\tFEAT_DEF(CMPXCHG16B, 0x00000001, 0, RTE_REG_ECX, 13)\n\tFEAT_DEF(XTPR, 0x00000001, 0, RTE_REG_ECX, 14)\n\tFEAT_DEF(PDCM, 0x00000001, 0, RTE_REG_ECX, 15)\n\tFEAT_DEF(PCID, 0x00000001, 0, RTE_REG_ECX, 17)\n\tFEAT_DEF(DCA, 0x00000001, 0, RTE_REG_ECX, 18)\n\tFEAT_DEF(SSE4_1, 0x00000001, 0, RTE_REG_ECX, 19)\n\tFEAT_DEF(SSE4_2, 0x00000001, 0, RTE_REG_ECX, 20)\n\tFEAT_DEF(X2APIC, 0x00000001, 0, RTE_REG_ECX, 21)\n\tFEAT_DEF(MOVBE, 0x00000001, 0, RTE_REG_ECX, 22)\n\tFEAT_DEF(POPCNT, 0x00000001, 0, RTE_REG_ECX, 23)\n\tFEAT_DEF(TSC_DEADLINE, 0x00000001, 0, RTE_REG_ECX, 24)\n\tFEAT_DEF(AES, 0x00000001, 0, RTE_REG_ECX, 25)\n\tFEAT_DEF(XSAVE, 0x00000001, 0, RTE_REG_ECX, 26)\n\tFEAT_DEF(OSXSAVE, 0x00000001, 0, RTE_REG_ECX, 27)\n\tFEAT_DEF(AVX, 0x00000001, 0, RTE_REG_ECX, 28)\n\tFEAT_DEF(F16C, 0x00000001, 0, RTE_REG_ECX, 29)\n\tFEAT_DEF(RDRAND, 0x00000001, 0, RTE_REG_ECX, 30)\n\n\tFEAT_DEF(FPU, 0x00000001, 0, RTE_REG_EDX, 0)\n\tFEAT_DEF(VME, 0x00000001, 0, RTE_REG_EDX, 1)\n\tFEAT_DEF(DE, 0x00000001, 0, RTE_REG_EDX, 2)\n\tFEAT_DEF(PSE, 0x00000001, 0, RTE_REG_EDX, 3)\n\tFEAT_DEF(TSC, 0x00000001, 0, RTE_REG_EDX, 4)\n\tFEAT_DEF(MSR, 0x00000001, 0, RTE_REG_EDX, 5)\n\tFEAT_DEF(PAE, 0x00000001, 0, RTE_REG_EDX, 6)\n\tFEAT_DEF(MCE, 0x00000001, 0, RTE_REG_EDX, 7)\n\tFEAT_DEF(CX8, 0x00000001, 0, RTE_REG_EDX, 8)\n\tFEAT_DEF(APIC, 0x00000001, 0, RTE_REG_EDX, 9)\n\tFEAT_DEF(SEP, 0x00000001, 0, RTE_REG_EDX, 11)\n\tFEAT_DEF(MTRR, 0x00000001, 0, RTE_REG_EDX, 12)\n\tFEAT_DEF(PGE, 0x00000001, 0, RTE_REG_EDX, 13)\n\tFEAT_DEF(MCA, 0x00000001, 0, RTE_REG_EDX, 14)\n\tFEAT_DEF(CMOV, 0x00000001, 0, RTE_REG_EDX, 15)\n\tFEAT_DEF(PAT, 0x00000001, 0, RTE_REG_EDX, 16)\n\tFEAT_DEF(PSE36, 0x00000001, 0, RTE_REG_EDX, 17)\n\tFEAT_DEF(PSN, 0x00000001, 0, RTE_REG_EDX, 18)\n\tFEAT_DEF(CLFSH, 0x00000001, 0, RTE_REG_EDX, 19)\n\tFEAT_DEF(DS, 0x00000001, 0, RTE_REG_EDX, 21)\n\tFEAT_DEF(ACPI, 0x00000001, 0, RTE_REG_EDX, 22)\n\tFEAT_DEF(MMX, 0x00000001, 0, RTE_REG_EDX, 23)\n\tFEAT_DEF(FXSR, 0x00000001, 0, RTE_REG_EDX, 24)\n\tFEAT_DEF(SSE, 0x00000001, 0, RTE_REG_EDX, 25)\n\tFEAT_DEF(SSE2, 0x00000001, 0, RTE_REG_EDX, 26)\n\tFEAT_DEF(SS, 0x00000001, 0, RTE_REG_EDX, 27)\n\tFEAT_DEF(HTT, 0x00000001, 0, RTE_REG_EDX, 28)\n\tFEAT_DEF(TM, 0x00000001, 0, RTE_REG_EDX, 29)\n\tFEAT_DEF(PBE, 0x00000001, 0, RTE_REG_EDX, 31)\n\n\tFEAT_DEF(DIGTEMP, 0x00000006, 0, RTE_REG_EAX, 0)\n\tFEAT_DEF(TRBOBST, 0x00000006, 0, RTE_REG_EAX, 1)\n\tFEAT_DEF(ARAT, 0x00000006, 0, RTE_REG_EAX, 2)\n\tFEAT_DEF(PLN, 0x00000006, 0, RTE_REG_EAX, 4)\n\tFEAT_DEF(ECMD, 0x00000006, 0, RTE_REG_EAX, 5)\n\tFEAT_DEF(PTM, 0x00000006, 0, RTE_REG_EAX, 6)\n\n\tFEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, RTE_REG_ECX, 0)\n\tFEAT_DEF(ACNT2, 0x00000006, 0, RTE_REG_ECX, 1)\n\tFEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX, 3)\n\n\tFEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX, 0)\n\tFEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX, 2)\n\tFEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX, 4)\n\tFEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX, 5)\n\tFEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX, 6)\n\tFEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX, 7)\n\tFEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX, 8)\n\tFEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10)\n\tFEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11)\n\n\tFEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0)\n\tFEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4)\n\n\tFEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11)\n\tFEAT_DEF(XD, 0x80000001, 0, RTE_REG_EDX, 20)\n\tFEAT_DEF(1GB_PG, 0x80000001, 0, RTE_REG_EDX, 26)\n\tFEAT_DEF(RDTSCP, 0x80000001, 0, RTE_REG_EDX, 27)\n\tFEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)\n\n\tFEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX, 8)\n};\n\nstatic inline void\nrte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)\n{\n#if defined(__i386__) && defined(__PIC__)\n /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */\n asm volatile(\"movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0\"\n\t\t : \"=r\" (out[RTE_REG_EBX]),\n\t\t \"=a\" (out[RTE_REG_EAX]),\n\t\t \"=c\" (out[RTE_REG_ECX]),\n\t\t \"=d\" (out[RTE_REG_EDX])\n\t\t : \"a\" (leaf), \"c\" (subleaf));\n#else\n\n asm volatile(\"cpuid\"\n\t\t : \"=a\" (out[RTE_REG_EAX]),\n\t\t \"=b\" (out[RTE_REG_EBX]),\n\t\t \"=c\" (out[RTE_REG_ECX]),\n\t\t \"=d\" (out[RTE_REG_EDX])\n\t\t : \"a\" (leaf), \"c\" (subleaf));\n\n#endif\n}\n\nstatic inline int\nrte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)\n{\n\tconst struct feature_entry *feat;\n\tcpuid_registers_t regs;\n\n\n\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n\t\t/* Flag does not match anything in the feature tables */\n\t\treturn -ENOENT;\n\n\tfeat = &cpu_feature_table[feature];\n\n\tif (!feat->leaf)\n\t\t/* This entry in the table wasn't filled out! */\n\t\treturn -EFAULT;\n\n\trte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);\n\tif (((regs[RTE_REG_EAX] ^ feat->leaf) & 0xffff0000) ||\n\t regs[RTE_REG_EAX] < feat->leaf)\n\t\treturn 0;\n\n\t/* get the cpuid leaf containing the desired feature */\n\trte_cpu_get_features(feat->leaf, feat->subleaf, regs);\n\n\t/* check if the feature is enabled */\n\treturn (regs[feat->reg] >> feat->bit) & 1;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_CPUFLAGS_X86_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_cycles.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n/* BSD LICENSE\n *\n * Copyright(c) 2013 6WIND.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_CYCLES_X86_64_H_\n#define _RTE_CYCLES_X86_64_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_cycles.h\"\n\n#ifdef RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT\n/* Global switch to use VMWARE mapping of TSC instead of RDTSC */\nextern int rte_cycles_vmware_tsc_map;\n#include \n#endif\n\nstatic inline uint64_t\nrte_rdtsc(void)\n{\n\tunion {\n\t\tuint64_t tsc_64;\n\t\tstruct {\n\t\t\tuint32_t lo_32;\n\t\t\tuint32_t hi_32;\n\t\t};\n\t} tsc;\n\n#ifdef RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT\n\tif (unlikely(rte_cycles_vmware_tsc_map)) {\n\t\t/* ecx = 0x10000 corresponds to the physical TSC for VMware */\n\t\tasm volatile(\"rdpmc\" :\n\t\t \"=a\" (tsc.lo_32),\n\t\t \"=d\" (tsc.hi_32) :\n\t\t \"c\"(0x10000));\n\t\treturn tsc.tsc_64;\n\t}\n#endif\n\n\tasm volatile(\"rdtsc\" :\n\t\t \"=a\" (tsc.lo_32),\n\t\t \"=d\" (tsc.hi_32));\n\treturn tsc.tsc_64;\n}\n\nstatic inline uint64_t\nrte_rdtsc_precise(void)\n{\n\trte_mb();\n\treturn rte_rdtsc();\n}\n\nstatic inline uint64_t\nrte_get_tsc_cycles(void) { return rte_rdtsc(); }\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_CYCLES_X86_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_memcpy.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_MEMCPY_X86_64_H_\n#define _RTE_MEMCPY_X86_64_H_\n\n/**\n * @file\n *\n * Functions for SSE/AVX/AVX2 implementation of memcpy().\n */\n\n#include \n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Copy bytes from one location to another. The locations must not overlap.\n *\n * @note This is implemented as a macro, so it's address should not be taken\n * and care is needed as parameter expressions may be evaluated multiple times.\n *\n * @param dst\n * Pointer to the destination of the data.\n * @param src\n * Pointer to the source data.\n * @param n\n * Number of bytes to copy.\n * @return\n * Pointer to the destination data.\n */\nstatic inline void *\nrte_memcpy(void *dst, const void *src, size_t n) __attribute__((always_inline));\n\n#ifdef RTE_MACHINE_CPUFLAG_AVX2\n\n/**\n * AVX2 implementation below\n */\n\n/**\n * Copy 16 bytes from one location to another,\n * locations should not overlap.\n */\nstatic inline void\nrte_mov16(uint8_t *dst, const uint8_t *src)\n{\n\t__m128i xmm0;\n\n\txmm0 = _mm_loadu_si128((const __m128i *)src);\n\t_mm_storeu_si128((__m128i *)dst, xmm0);\n}\n\n/**\n * Copy 32 bytes from one location to another,\n * locations should not overlap.\n */\nstatic inline void\nrte_mov32(uint8_t *dst, const uint8_t *src)\n{\n\t__m256i ymm0;\n\n\tymm0 = _mm256_loadu_si256((const __m256i *)src);\n\t_mm256_storeu_si256((__m256i *)dst, ymm0);\n}\n\n/**\n * Copy 64 bytes from one location to another,\n * locations should not overlap.\n */\nstatic inline void\nrte_mov64(uint8_t *dst, const uint8_t *src)\n{\n\trte_mov32((uint8_t *)dst + 0 * 32, (const uint8_t *)src + 0 * 32);\n\trte_mov32((uint8_t *)dst + 1 * 32, (const uint8_t *)src + 1 * 32);\n}\n\n/**\n * Copy 128 bytes from one location to another,\n * locations should not overlap.\n */\nstatic inline void\nrte_mov128(uint8_t *dst, const uint8_t *src)\n{\n\trte_mov32((uint8_t *)dst + 0 * 32, (const uint8_t *)src + 0 * 32);\n\trte_mov32((uint8_t *)dst + 1 * 32, (const uint8_t *)src + 1 * 32);\n\trte_mov32((uint8_t *)dst + 2 * 32, (const uint8_t *)src + 2 * 32);\n\trte_mov32((uint8_t *)dst + 3 * 32, (const uint8_t *)src + 3 * 32);\n}\n\n/**\n * Copy 256 bytes from one location to another,\n * locations should not overlap.\n */\nstatic inline void\nrte_mov256(uint8_t *dst, const uint8_t *src)\n{\n\trte_mov32((uint8_t *)dst + 0 * 32, (const uint8_t *)src + 0 * 32);\n\trte_mov32((uint8_t *)dst + 1 * 32, (const uint8_t *)src + 1 * 32);\n\trte_mov32((uint8_t *)dst + 2 * 32, (const uint8_t *)src + 2 * 32);\n\trte_mov32((uint8_t *)dst + 3 * 32, (const uint8_t *)src + 3 * 32);\n\trte_mov32((uint8_t *)dst + 4 * 32, (const uint8_t *)src + 4 * 32);\n\trte_mov32((uint8_t *)dst + 5 * 32, (const uint8_t *)src + 5 * 32);\n\trte_mov32((uint8_t *)dst + 6 * 32, (const uint8_t *)src + 6 * 32);\n\trte_mov32((uint8_t *)dst + 7 * 32, (const uint8_t *)src + 7 * 32);\n}\n\n/**\n * Copy 64-byte blocks from one location to another,\n * locations should not overlap.\n */\nstatic inline void\nrte_mov64blocks(uint8_t *dst, const uint8_t *src, size_t n)\n{\n\t__m256i ymm0, ymm1;\n\n\twhile (n >= 64) {\n\t\tymm0 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 0 * 32));\n\t\tn -= 64;\n\t\tymm1 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 1 * 32));\n\t\tsrc = (const uint8_t *)src + 64;\n\t\t_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 0 * 32), ymm0);\n\t\t_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 1 * 32), ymm1);\n\t\tdst = (uint8_t *)dst + 64;\n\t}\n}\n\n/**\n * Copy 256-byte blocks from one location to another,\n * locations should not overlap.\n */\nstatic inline void\nrte_mov256blocks(uint8_t *dst, const uint8_t *src, size_t n)\n{\n\t__m256i ymm0, ymm1, ymm2, ymm3, ymm4, ymm5, ymm6, ymm7;\n\n\twhile (n >= 256) {\n\t\tymm0 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 0 * 32));\n\t\tn -= 256;\n\t\tymm1 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 1 * 32));\n\t\tymm2 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 2 * 32));\n\t\tymm3 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 3 * 32));\n\t\tymm4 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 4 * 32));\n\t\tymm5 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 5 * 32));\n\t\tymm6 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 6 * 32));\n\t\tymm7 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 7 * 32));\n\t\tsrc = (const uint8_t *)src + 256;\n\t\t_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 0 * 32), ymm0);\n\t\t_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 1 * 32), ymm1);\n\t\t_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 2 * 32), ymm2);\n\t\t_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 3 * 32), ymm3);\n\t\t_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 4 * 32), ymm4);\n\t\t_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 5 * 32), ymm5);\n\t\t_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 6 * 32), ymm6);\n\t\t_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 7 * 32), ymm7);\n\t\tdst = (uint8_t *)dst + 256;\n\t}\n}\n\nstatic inline void *\nrte_memcpy(void *dst, const void *src, size_t n)\n{\n\tuintptr_t dstu = (uintptr_t)dst;\n\tuintptr_t srcu = (uintptr_t)src;\n\tvoid *ret = dst;\n\tsize_t dstofss;\n\tsize_t bits;\n\n\t/**\n\t * Copy less than 16 bytes\n\t */\n\tif (n < 16) {\n\t\tif (n & 0x01) {\n\t\t\t*(uint8_t *)dstu = *(const uint8_t *)srcu;\n\t\t\tsrcu = (uintptr_t)((const uint8_t *)srcu + 1);\n\t\t\tdstu = (uintptr_t)((uint8_t *)dstu + 1);\n\t\t}\n\t\tif (n & 0x02) {\n\t\t\t*(uint16_t *)dstu = *(const uint16_t *)srcu;\n\t\t\tsrcu = (uintptr_t)((const uint16_t *)srcu + 1);\n\t\t\tdstu = (uintptr_t)((uint16_t *)dstu + 1);\n\t\t}\n\t\tif (n & 0x04) {\n\t\t\t*(uint32_t *)dstu = *(const uint32_t *)srcu;\n\t\t\tsrcu = (uintptr_t)((const uint32_t *)srcu + 1);\n\t\t\tdstu = (uintptr_t)((uint32_t *)dstu + 1);\n\t\t}\n\t\tif (n & 0x08) {\n\t\t\t*(uint64_t *)dstu = *(const uint64_t *)srcu;\n\t\t}\n\t\treturn ret;\n\t}\n\n\t/**\n\t * Fast way when copy size doesn't exceed 512 bytes\n\t */\n\tif (n <= 32) {\n\t\trte_mov16((uint8_t *)dst, (const uint8_t *)src);\n\t\trte_mov16((uint8_t *)dst - 16 + n, (const uint8_t *)src - 16 + n);\n\t\treturn ret;\n\t}\n\tif (n <= 64) {\n\t\trte_mov32((uint8_t *)dst, (const uint8_t *)src);\n\t\trte_mov32((uint8_t *)dst - 32 + n, (const uint8_t *)src - 32 + n);\n\t\treturn ret;\n\t}\n\tif (n <= 512) {\n\t\tif (n >= 256) {\n\t\t\tn -= 256;\n\t\t\trte_mov256((uint8_t *)dst, (const uint8_t *)src);\n\t\t\tsrc = (const uint8_t *)src + 256;\n\t\t\tdst = (uint8_t *)dst + 256;\n\t\t}\n\t\tif (n >= 128) {\n\t\t\tn -= 128;\n\t\t\trte_mov128((uint8_t *)dst, (const uint8_t *)src);\n\t\t\tsrc = (const uint8_t *)src + 128;\n\t\t\tdst = (uint8_t *)dst + 128;\n\t\t}\n\t\tif (n >= 64) {\n\t\t\tn -= 64;\n\t\t\trte_mov64((uint8_t *)dst, (const uint8_t *)src);\n\t\t\tsrc = (const uint8_t *)src + 64;\n\t\t\tdst = (uint8_t *)dst + 64;\n\t\t}\nCOPY_BLOCK_64_BACK31:\n\t\tif (n > 32) {\n\t\t\trte_mov32((uint8_t *)dst, (const uint8_t *)src);\n\t\t\trte_mov32((uint8_t *)dst - 32 + n, (const uint8_t *)src - 32 + n);\n\t\t\treturn ret;\n\t\t}\n\t\tif (n > 0) {\n\t\t\trte_mov32((uint8_t *)dst - 32 + n, (const uint8_t *)src - 32 + n);\n\t\t}\n\t\treturn ret;\n\t}\n\n\t/**\n\t * Make store aligned when copy size exceeds 512 bytes\n\t */\n\tdstofss = 32 - ((uintptr_t)dst & 0x1F);\n\tn -= dstofss;\n\trte_mov32((uint8_t *)dst, (const uint8_t *)src);\n\tsrc = (const uint8_t *)src + dstofss;\n\tdst = (uint8_t *)dst + dstofss;\n\n\t/**\n\t * Copy 256-byte blocks.\n\t * Use copy block function for better instruction order control,\n\t * which is important when load is unaligned.\n\t */\n\trte_mov256blocks((uint8_t *)dst, (const uint8_t *)src, n);\n\tbits = n;\n\tn = n & 255;\n\tbits -= n;\n\tsrc = (const uint8_t *)src + bits;\n\tdst = (uint8_t *)dst + bits;\n\n\t/**\n\t * Copy 64-byte blocks.\n\t * Use copy block function for better instruction order control,\n\t * which is important when load is unaligned.\n\t */\n\tif (n >= 64) {\n\t\trte_mov64blocks((uint8_t *)dst, (const uint8_t *)src, n);\n\t\tbits = n;\n\t\tn = n & 63;\n\t\tbits -= n;\n\t\tsrc = (const uint8_t *)src + bits;\n\t\tdst = (uint8_t *)dst + bits;\n\t}\n\n\t/**\n\t * Copy whatever left\n\t */\n\tgoto COPY_BLOCK_64_BACK31;\n}\n\n#else /* RTE_MACHINE_CPUFLAG_AVX2 */\n\n/**\n * SSE & AVX implementation below\n */\n\n/**\n * Copy 16 bytes from one location to another,\n * locations should not overlap.\n */\nstatic inline void\nrte_mov16(uint8_t *dst, const uint8_t *src)\n{\n\t__m128i xmm0;\n\n\txmm0 = _mm_loadu_si128((const __m128i *)(const __m128i *)src);\n\t_mm_storeu_si128((__m128i *)dst, xmm0);\n}\n\n/**\n * Copy 32 bytes from one location to another,\n * locations should not overlap.\n */\nstatic inline void\nrte_mov32(uint8_t *dst, const uint8_t *src)\n{\n\trte_mov16((uint8_t *)dst + 0 * 16, (const uint8_t *)src + 0 * 16);\n\trte_mov16((uint8_t *)dst + 1 * 16, (const uint8_t *)src + 1 * 16);\n}\n\n/**\n * Copy 64 bytes from one location to another,\n * locations should not overlap.\n */\nstatic inline void\nrte_mov64(uint8_t *dst, const uint8_t *src)\n{\n\trte_mov16((uint8_t *)dst + 0 * 16, (const uint8_t *)src + 0 * 16);\n\trte_mov16((uint8_t *)dst + 1 * 16, (const uint8_t *)src + 1 * 16);\n\trte_mov16((uint8_t *)dst + 2 * 16, (const uint8_t *)src + 2 * 16);\n\trte_mov16((uint8_t *)dst + 3 * 16, (const uint8_t *)src + 3 * 16);\n}\n\n/**\n * Copy 128 bytes from one location to another,\n * locations should not overlap.\n */\nstatic inline void\nrte_mov128(uint8_t *dst, const uint8_t *src)\n{\n\trte_mov16((uint8_t *)dst + 0 * 16, (const uint8_t *)src + 0 * 16);\n\trte_mov16((uint8_t *)dst + 1 * 16, (const uint8_t *)src + 1 * 16);\n\trte_mov16((uint8_t *)dst + 2 * 16, (const uint8_t *)src + 2 * 16);\n\trte_mov16((uint8_t *)dst + 3 * 16, (const uint8_t *)src + 3 * 16);\n\trte_mov16((uint8_t *)dst + 4 * 16, (const uint8_t *)src + 4 * 16);\n\trte_mov16((uint8_t *)dst + 5 * 16, (const uint8_t *)src + 5 * 16);\n\trte_mov16((uint8_t *)dst + 6 * 16, (const uint8_t *)src + 6 * 16);\n\trte_mov16((uint8_t *)dst + 7 * 16, (const uint8_t *)src + 7 * 16);\n}\n\n/**\n * Copy 256 bytes from one location to another,\n * locations should not overlap.\n */\nstatic inline void\nrte_mov256(uint8_t *dst, const uint8_t *src)\n{\n\trte_mov16((uint8_t *)dst + 0 * 16, (const uint8_t *)src + 0 * 16);\n\trte_mov16((uint8_t *)dst + 1 * 16, (const uint8_t *)src + 1 * 16);\n\trte_mov16((uint8_t *)dst + 2 * 16, (const uint8_t *)src + 2 * 16);\n\trte_mov16((uint8_t *)dst + 3 * 16, (const uint8_t *)src + 3 * 16);\n\trte_mov16((uint8_t *)dst + 4 * 16, (const uint8_t *)src + 4 * 16);\n\trte_mov16((uint8_t *)dst + 5 * 16, (const uint8_t *)src + 5 * 16);\n\trte_mov16((uint8_t *)dst + 6 * 16, (const uint8_t *)src + 6 * 16);\n\trte_mov16((uint8_t *)dst + 7 * 16, (const uint8_t *)src + 7 * 16);\n\trte_mov16((uint8_t *)dst + 8 * 16, (const uint8_t *)src + 8 * 16);\n\trte_mov16((uint8_t *)dst + 9 * 16, (const uint8_t *)src + 9 * 16);\n\trte_mov16((uint8_t *)dst + 10 * 16, (const uint8_t *)src + 10 * 16);\n\trte_mov16((uint8_t *)dst + 11 * 16, (const uint8_t *)src + 11 * 16);\n\trte_mov16((uint8_t *)dst + 12 * 16, (const uint8_t *)src + 12 * 16);\n\trte_mov16((uint8_t *)dst + 13 * 16, (const uint8_t *)src + 13 * 16);\n\trte_mov16((uint8_t *)dst + 14 * 16, (const uint8_t *)src + 14 * 16);\n\trte_mov16((uint8_t *)dst + 15 * 16, (const uint8_t *)src + 15 * 16);\n}\n\n/**\n * Macro for copying unaligned block from one location to another with constant load offset,\n * 47 bytes leftover maximum,\n * locations should not overlap.\n * Requirements:\n * - Store is aligned\n * - Load offset is , which must be immediate value within [1, 15]\n * - For , make sure bit backwards & <16 - offset> bit forwards are available for loading\n * - , , must be variables\n * - __m128i ~ must be pre-defined\n */\n#define MOVEUNALIGNED_LEFT47_IMM(dst, src, len, offset) \\\n({ \\\n int tmp; \\\n while (len >= 128 + 16 - offset) { \\\n xmm0 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 0 * 16)); \\\n len -= 128; \\\n xmm1 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 1 * 16)); \\\n xmm2 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 2 * 16)); \\\n xmm3 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 3 * 16)); \\\n xmm4 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 4 * 16)); \\\n xmm5 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 5 * 16)); \\\n xmm6 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 6 * 16)); \\\n xmm7 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 7 * 16)); \\\n xmm8 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 8 * 16)); \\\n src = (const uint8_t *)src + 128; \\\n _mm_storeu_si128((__m128i *)((uint8_t *)dst + 0 * 16), _mm_alignr_epi8(xmm1, xmm0, offset)); \\\n _mm_storeu_si128((__m128i *)((uint8_t *)dst + 1 * 16), _mm_alignr_epi8(xmm2, xmm1, offset)); \\\n _mm_storeu_si128((__m128i *)((uint8_t *)dst + 2 * 16), _mm_alignr_epi8(xmm3, xmm2, offset)); \\\n _mm_storeu_si128((__m128i *)((uint8_t *)dst + 3 * 16), _mm_alignr_epi8(xmm4, xmm3, offset)); \\\n _mm_storeu_si128((__m128i *)((uint8_t *)dst + 4 * 16), _mm_alignr_epi8(xmm5, xmm4, offset)); \\\n _mm_storeu_si128((__m128i *)((uint8_t *)dst + 5 * 16), _mm_alignr_epi8(xmm6, xmm5, offset)); \\\n _mm_storeu_si128((__m128i *)((uint8_t *)dst + 6 * 16), _mm_alignr_epi8(xmm7, xmm6, offset)); \\\n _mm_storeu_si128((__m128i *)((uint8_t *)dst + 7 * 16), _mm_alignr_epi8(xmm8, xmm7, offset)); \\\n dst = (uint8_t *)dst + 128; \\\n } \\\n tmp = len; \\\n len = ((len - 16 + offset) & 127) + 16 - offset; \\\n tmp -= len; \\\n src = (const uint8_t *)src + tmp; \\\n dst = (uint8_t *)dst + tmp; \\\n if (len >= 32 + 16 - offset) { \\\n while (len >= 32 + 16 - offset) { \\\n xmm0 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 0 * 16)); \\\n len -= 32; \\\n xmm1 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 1 * 16)); \\\n xmm2 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 2 * 16)); \\\n src = (const uint8_t *)src + 32; \\\n _mm_storeu_si128((__m128i *)((uint8_t *)dst + 0 * 16), _mm_alignr_epi8(xmm1, xmm0, offset)); \\\n _mm_storeu_si128((__m128i *)((uint8_t *)dst + 1 * 16), _mm_alignr_epi8(xmm2, xmm1, offset)); \\\n dst = (uint8_t *)dst + 32; \\\n } \\\n tmp = len; \\\n len = ((len - 16 + offset) & 31) + 16 - offset; \\\n tmp -= len; \\\n src = (const uint8_t *)src + tmp; \\\n dst = (uint8_t *)dst + tmp; \\\n } \\\n})\n\n/**\n * Macro for copying unaligned block from one location to another,\n * 47 bytes leftover maximum,\n * locations should not overlap.\n * Use switch here because the aligning instruction requires immediate value for shift count.\n * Requirements:\n * - Store is aligned\n * - Load offset is , which must be within [1, 15]\n * - For , make sure bit backwards & <16 - offset> bit forwards are available for loading\n * - , , must be variables\n * - __m128i ~ used in MOVEUNALIGNED_LEFT47_IMM must be pre-defined\n */\n#define MOVEUNALIGNED_LEFT47(dst, src, len, offset) \\\n({ \\\n switch (offset) { \\\n case 0x01: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x01); break; \\\n case 0x02: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x02); break; \\\n case 0x03: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x03); break; \\\n case 0x04: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x04); break; \\\n case 0x05: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x05); break; \\\n case 0x06: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x06); break; \\\n case 0x07: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x07); break; \\\n case 0x08: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x08); break; \\\n case 0x09: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x09); break; \\\n case 0x0A: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x0A); break; \\\n case 0x0B: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x0B); break; \\\n case 0x0C: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x0C); break; \\\n case 0x0D: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x0D); break; \\\n case 0x0E: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x0E); break; \\\n case 0x0F: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x0F); break; \\\n default:; \\\n } \\\n})\n\nstatic inline void *\nrte_memcpy(void *dst, const void *src, size_t n)\n{\n\t__m128i xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8;\n\tuintptr_t dstu = (uintptr_t)dst;\n\tuintptr_t srcu = (uintptr_t)src;\n\tvoid *ret = dst;\n\tsize_t dstofss;\n\tsize_t srcofs;\n\n\t/**\n\t * Copy less than 16 bytes\n\t */\n\tif (n < 16) {\n\t\tif (n & 0x01) {\n\t\t\t*(uint8_t *)dstu = *(const uint8_t *)srcu;\n\t\t\tsrcu = (uintptr_t)((const uint8_t *)srcu + 1);\n\t\t\tdstu = (uintptr_t)((uint8_t *)dstu + 1);\n\t\t}\n\t\tif (n & 0x02) {\n\t\t\t*(uint16_t *)dstu = *(const uint16_t *)srcu;\n\t\t\tsrcu = (uintptr_t)((const uint16_t *)srcu + 1);\n\t\t\tdstu = (uintptr_t)((uint16_t *)dstu + 1);\n\t\t}\n\t\tif (n & 0x04) {\n\t\t\t*(uint32_t *)dstu = *(const uint32_t *)srcu;\n\t\t\tsrcu = (uintptr_t)((const uint32_t *)srcu + 1);\n\t\t\tdstu = (uintptr_t)((uint32_t *)dstu + 1);\n\t\t}\n\t\tif (n & 0x08) {\n\t\t\t*(uint64_t *)dstu = *(const uint64_t *)srcu;\n\t\t}\n\t\treturn ret;\n\t}\n\n\t/**\n\t * Fast way when copy size doesn't exceed 512 bytes\n\t */\n\tif (n <= 32) {\n\t\trte_mov16((uint8_t *)dst, (const uint8_t *)src);\n\t\trte_mov16((uint8_t *)dst - 16 + n, (const uint8_t *)src - 16 + n);\n\t\treturn ret;\n\t}\n\tif (n <= 48) {\n\t\trte_mov32((uint8_t *)dst, (const uint8_t *)src);\n\t\trte_mov16((uint8_t *)dst - 16 + n, (const uint8_t *)src - 16 + n);\n\t\treturn ret;\n\t}\n\tif (n <= 64) {\n\t\trte_mov32((uint8_t *)dst, (const uint8_t *)src);\n\t\trte_mov16((uint8_t *)dst + 32, (const uint8_t *)src + 32);\n\t\trte_mov16((uint8_t *)dst - 16 + n, (const uint8_t *)src - 16 + n);\n\t\treturn ret;\n\t}\n\tif (n <= 128) {\n\t\tgoto COPY_BLOCK_128_BACK15;\n\t}\n\tif (n <= 512) {\n\t\tif (n >= 256) {\n\t\t\tn -= 256;\n\t\t\trte_mov128((uint8_t *)dst, (const uint8_t *)src);\n\t\t\trte_mov128((uint8_t *)dst + 128, (const uint8_t *)src + 128);\n\t\t\tsrc = (const uint8_t *)src + 256;\n\t\t\tdst = (uint8_t *)dst + 256;\n\t\t}\nCOPY_BLOCK_255_BACK15:\n\t\tif (n >= 128) {\n\t\t\tn -= 128;\n\t\t\trte_mov128((uint8_t *)dst, (const uint8_t *)src);\n\t\t\tsrc = (const uint8_t *)src + 128;\n\t\t\tdst = (uint8_t *)dst + 128;\n\t\t}\nCOPY_BLOCK_128_BACK15:\n\t\tif (n >= 64) {\n\t\t\tn -= 64;\n\t\t\trte_mov64((uint8_t *)dst, (const uint8_t *)src);\n\t\t\tsrc = (const uint8_t *)src + 64;\n\t\t\tdst = (uint8_t *)dst + 64;\n\t\t}\nCOPY_BLOCK_64_BACK15:\n\t\tif (n >= 32) {\n\t\t\tn -= 32;\n\t\t\trte_mov32((uint8_t *)dst, (const uint8_t *)src);\n\t\t\tsrc = (const uint8_t *)src + 32;\n\t\t\tdst = (uint8_t *)dst + 32;\n\t\t}\n\t\tif (n > 16) {\n\t\t\trte_mov16((uint8_t *)dst, (const uint8_t *)src);\n\t\t\trte_mov16((uint8_t *)dst - 16 + n, (const uint8_t *)src - 16 + n);\n\t\t\treturn ret;\n\t\t}\n\t\tif (n > 0) {\n\t\t\trte_mov16((uint8_t *)dst - 16 + n, (const uint8_t *)src - 16 + n);\n\t\t}\n\t\treturn ret;\n\t}\n\n\t/**\n\t * Make store aligned when copy size exceeds 512 bytes,\n\t * and make sure the first 15 bytes are copied, because\n\t * unaligned copy functions require up to 15 bytes\n\t * backwards access.\n\t */\n\tdstofss = 16 - ((uintptr_t)dst & 0x0F) + 16;\n\tn -= dstofss;\n\trte_mov32((uint8_t *)dst, (const uint8_t *)src);\n\tsrc = (const uint8_t *)src + dstofss;\n\tdst = (uint8_t *)dst + dstofss;\n\tsrcofs = ((uintptr_t)src & 0x0F);\n\n\t/**\n\t * For aligned copy\n\t */\n\tif (srcofs == 0) {\n\t\t/**\n\t\t * Copy 256-byte blocks\n\t\t */\n\t\tfor (; n >= 256; n -= 256) {\n\t\t\trte_mov256((uint8_t *)dst, (const uint8_t *)src);\n\t\t\tdst = (uint8_t *)dst + 256;\n\t\t\tsrc = (const uint8_t *)src + 256;\n\t\t}\n\n\t\t/**\n\t\t * Copy whatever left\n\t\t */\n\t\tgoto COPY_BLOCK_255_BACK15;\n\t}\n\n\t/**\n\t * For copy with unaligned load\n\t */\n\tMOVEUNALIGNED_LEFT47(dst, src, n, srcofs);\n\n\t/**\n\t * Copy whatever left\n\t */\n\tgoto COPY_BLOCK_64_BACK15;\n}\n\n#endif /* RTE_MACHINE_CPUFLAG_AVX2 */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_MEMCPY_X86_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_prefetch.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_PREFETCH_X86_64_H_\n#define _RTE_PREFETCH_X86_64_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_prefetch.h\"\n\nstatic inline void rte_prefetch0(const volatile void *p)\n{\n\tasm volatile (\"prefetcht0 %[p]\" : : [p] \"m\" (*(const volatile char *)p));\n}\n\nstatic inline void rte_prefetch1(const volatile void *p)\n{\n\tasm volatile (\"prefetcht1 %[p]\" : : [p] \"m\" (*(const volatile char *)p));\n}\n\nstatic inline void rte_prefetch2(const volatile void *p)\n{\n\tasm volatile (\"prefetcht2 %[p]\" : : [p] \"m\" (*(const volatile char *)p));\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_PREFETCH_X86_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_rtm.h", "content": "#ifndef _RTE_RTM_H_\n#define _RTE_RTM_H_ 1\n\n/*\n * Copyright (c) 2012,2013 Intel Corporation\n * Author: Andi Kleen\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that: (1) source code distributions\n * retain the above copyright notice and this paragraph in its entirety, (2)\n * distributions including binary code include the above copyright notice and\n * this paragraph in its entirety in the documentation or other materials\n * provided with the distribution\n *\n * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED\n * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF\n * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.\n */\n\n/* Official RTM intrinsics interface matching gcc/icc, but works\n on older gcc compatible compilers and binutils. */\n\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n#define RTE_XBEGIN_STARTED\t\t(~0u)\n#define RTE_XABORT_EXPLICIT\t\t(1 << 0)\n#define RTE_XABORT_RETRY\t\t(1 << 1)\n#define RTE_XABORT_CONFLICT\t\t(1 << 2)\n#define RTE_XABORT_CAPACITY\t\t(1 << 3)\n#define RTE_XABORT_DEBUG\t\t(1 << 4)\n#define RTE_XABORT_NESTED\t\t(1 << 5)\n#define RTE_XABORT_CODE(x)\t\t(((x) >> 24) & 0xff)\n\nstatic __attribute__((__always_inline__)) inline\nunsigned int rte_xbegin(void)\n{\n\tunsigned int ret = RTE_XBEGIN_STARTED;\n\n\tasm volatile(\".byte 0xc7,0xf8 ; .long 0\" : \"+a\" (ret) :: \"memory\");\n\treturn ret;\n}\n\nstatic __attribute__((__always_inline__)) inline\nvoid rte_xend(void)\n{\n\t asm volatile(\".byte 0x0f,0x01,0xd5\" ::: \"memory\");\n}\n\nstatic __attribute__((__always_inline__)) inline\nvoid rte_xabort(const unsigned int status)\n{\n\tasm volatile(\".byte 0xc6,0xf8,%P0\" :: \"i\" (status) : \"memory\");\n}\n\nstatic __attribute__((__always_inline__)) inline\nint rte_xtest(void)\n{\n\tunsigned char out;\n\n\tasm volatile(\".byte 0x0f,0x01,0xd6 ; setnz %0\" :\n\t\t\"=r\" (out) :: \"memory\");\n\treturn out;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_RTM_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_rwlock.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_RWLOCK_X86_64_H_\n#define _RTE_RWLOCK_X86_64_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_rwlock.h\"\n#include \"rte_spinlock.h\"\n\nstatic inline void\nrte_rwlock_read_lock_tm(rte_rwlock_t *rwl)\n{\n\tif (likely(rte_try_tm(&rwl->cnt)))\n\t\treturn;\n\trte_rwlock_read_lock(rwl);\n}\n\nstatic inline void\nrte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)\n{\n\tif (unlikely(rwl->cnt))\n\t\trte_rwlock_read_unlock(rwl);\n\telse\n\t\trte_xend();\n}\n\nstatic inline void\nrte_rwlock_write_lock_tm(rte_rwlock_t *rwl)\n{\n\tif (likely(rte_try_tm(&rwl->cnt)))\n\t\treturn;\n\trte_rwlock_write_lock(rwl);\n}\n\nstatic inline void\nrte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)\n{\n\tif (unlikely(rwl->cnt))\n\t\trte_rwlock_write_unlock(rwl);\n\telse\n\t\trte_xend();\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_RWLOCK_X86_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_spinlock.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_SPINLOCK_X86_64_H_\n#define _RTE_SPINLOCK_X86_64_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"generic/rte_spinlock.h\"\n#include \"rte_rtm.h\"\n#include \"rte_cpuflags.h\"\n#include \"rte_branch_prediction.h\"\n#include \"rte_common.h\"\n\n#define RTE_RTM_MAX_RETRIES (10)\n#define RTE_XABORT_LOCK_BUSY (0xff)\n\n#ifndef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_spinlock_lock(rte_spinlock_t *sl)\n{\n\tint lock_val = 1;\n\tasm volatile (\n\t\t\t\"1:\\n\"\n\t\t\t\"xchg %[locked], %[lv]\\n\"\n\t\t\t\"test %[lv], %[lv]\\n\"\n\t\t\t\"jz 3f\\n\"\n\t\t\t\"2:\\n\"\n\t\t\t\"pause\\n\"\n\t\t\t\"cmpl $0, %[locked]\\n\"\n\t\t\t\"jnz 2b\\n\"\n\t\t\t\"jmp 1b\\n\"\n\t\t\t\"3:\\n\"\n\t\t\t: [locked] \"=m\" (sl->locked), [lv] \"=q\" (lock_val)\n\t\t\t: \"[lv]\" (lock_val)\n\t\t\t: \"memory\");\n}\n\nstatic inline void\nrte_spinlock_unlock (rte_spinlock_t *sl)\n{\n\tint unlock_val = 0;\n\tasm volatile (\n\t\t\t\"xchg %[locked], %[ulv]\\n\"\n\t\t\t: [locked] \"=m\" (sl->locked), [ulv] \"=q\" (unlock_val)\n\t\t\t: \"[ulv]\" (unlock_val)\n\t\t\t: \"memory\");\n}\n\nstatic inline int\nrte_spinlock_trylock (rte_spinlock_t *sl)\n{\n\tint lockval = 1;\n\n\tasm volatile (\n\t\t\t\"xchg %[locked], %[lockval]\"\n\t\t\t: [locked] \"=m\" (sl->locked), [lockval] \"=q\" (lockval)\n\t\t\t: \"[lockval]\" (lockval)\n\t\t\t: \"memory\");\n\n\treturn (lockval == 0);\n}\n#endif\n\nstatic uint8_t rtm_supported; /* cache the flag to avoid the overhead\n\t\t\t\t of the rte_cpu_get_flag_enabled function */\n\nstatic inline void __attribute__((constructor))\nrte_rtm_init(void)\n{\n\trtm_supported = rte_cpu_get_flag_enabled(RTE_CPUFLAG_RTM);\n}\n\nstatic inline int rte_tm_supported(void)\n{\n\treturn rtm_supported;\n}\n\nstatic inline int\nrte_try_tm(volatile int *lock)\n{\n\tif (!rtm_supported)\n\t\treturn 0;\n\n\tint retries = RTE_RTM_MAX_RETRIES;\n\n\twhile (likely(retries--)) {\n\n\t\tunsigned int status = rte_xbegin();\n\n\t\tif (likely(RTE_XBEGIN_STARTED == status)) {\n\t\t\tif (unlikely(*lock))\n\t\t\t\trte_xabort(RTE_XABORT_LOCK_BUSY);\n\t\t\telse\n\t\t\t\treturn 1;\n\t\t}\n\t\twhile (*lock)\n\t\t\trte_pause();\n\n\t\tif ((status & RTE_XABORT_EXPLICIT) &&\n\t\t\t(RTE_XABORT_CODE(status) == RTE_XABORT_LOCK_BUSY))\n\t\t\tcontinue;\n\n\t\tif ((status & RTE_XABORT_RETRY) == 0) /* do not retry */\n\t\t\tbreak;\n\t}\n\treturn 0;\n}\n\nstatic inline void\nrte_spinlock_lock_tm(rte_spinlock_t *sl)\n{\n\tif (likely(rte_try_tm(&sl->locked)))\n\t\treturn;\n\n\trte_spinlock_lock(sl); /* fall-back */\n}\n\nstatic inline int\nrte_spinlock_trylock_tm(rte_spinlock_t *sl)\n{\n\tif (likely(rte_try_tm(&sl->locked)))\n\t\treturn 1;\n\n\treturn rte_spinlock_trylock(sl);\n}\n\nstatic inline void\nrte_spinlock_unlock_tm(rte_spinlock_t *sl)\n{\n\tif (unlikely(sl->locked))\n\t\trte_spinlock_unlock(sl);\n\telse\n\t\trte_xend();\n}\n\nstatic inline void\nrte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)\n{\n\tif (likely(rte_try_tm(&slr->sl.locked)))\n\t\treturn;\n\n\trte_spinlock_recursive_lock(slr); /* fall-back */\n}\n\nstatic inline void\nrte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)\n{\n\tif (unlikely(slr->sl.locked))\n\t\trte_spinlock_recursive_unlock(slr);\n\telse\n\t\trte_xend();\n}\n\nstatic inline int\nrte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)\n{\n\tif (likely(rte_try_tm(&slr->sl.locked)))\n\t\treturn 1;\n\n\treturn rte_spinlock_recursive_trylock(slr);\n}\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_SPINLOCK_X86_64_H_ */\n" }, { "path": "lib/librte_eal/common/include/arch/x86/rte_vect.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_VECT_H_\n#define _RTE_VECT_H_\n\n/**\n * @file\n *\n * RTE SSE/AVX related header.\n */\n\n#if (defined(__ICC) || (__GNUC__ == 4 && __GNUC_MINOR__ < 4))\n\n#ifdef __SSE__\n#include \n#endif\n\n#ifdef __SSE2__\n#include \n#endif\n\n#ifdef __SSE3__\n#include \n#endif\n\n#if defined(__SSE4_2__) || defined(__SSE4_1__)\n#include \n#endif\n\n#if defined(__AVX__)\n#include \n#endif\n\n#else\n\n#include \n\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef __m128i xmm_t;\n\n#define\tXMM_SIZE\t(sizeof(xmm_t))\n#define\tXMM_MASK\t(XMM_SIZE - 1)\n\ntypedef union rte_xmm {\n\txmm_t x;\n\tuint8_t u8[XMM_SIZE / sizeof(uint8_t)];\n\tuint16_t u16[XMM_SIZE / sizeof(uint16_t)];\n\tuint32_t u32[XMM_SIZE / sizeof(uint32_t)];\n\tuint64_t u64[XMM_SIZE / sizeof(uint64_t)];\n\tdouble pd[XMM_SIZE / sizeof(double)];\n} rte_xmm_t;\n\n#ifdef __AVX__\n\ntypedef __m256i ymm_t;\n\n#define\tYMM_SIZE\t(sizeof(ymm_t))\n#define\tYMM_MASK\t(YMM_SIZE - 1)\n\ntypedef union rte_ymm {\n\tymm_t y;\n\txmm_t x[YMM_SIZE / sizeof(xmm_t)];\n\tuint8_t u8[YMM_SIZE / sizeof(uint8_t)];\n\tuint16_t u16[YMM_SIZE / sizeof(uint16_t)];\n\tuint32_t u32[YMM_SIZE / sizeof(uint32_t)];\n\tuint64_t u64[YMM_SIZE / sizeof(uint64_t)];\n\tdouble pd[YMM_SIZE / sizeof(double)];\n} rte_ymm_t;\n\n#endif /* __AVX__ */\n\n#ifdef RTE_ARCH_I686\n#define _mm_cvtsi128_si64(a) ({ \\\n\trte_xmm_t m; \\\n\tm.x = (a); \\\n\t(m.u64[0]); \\\n})\n#endif\n\n/*\n * Prior to version 12.1 icc doesn't support _mm_set_epi64x.\n */\n#if (defined(__ICC) && __ICC < 1210)\n#define _mm_set_epi64x(a, b) ({ \\\n\trte_xmm_t m; \\\n\tm.u64[0] = b; \\\n\tm.u64[1] = a; \\\n\t(m.x); \\\n})\n#endif /* (defined(__ICC) && __ICC < 1210) */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_VECT_H_ */\n" }, { "path": "lib/librte_eal/common/include/generic/rte_atomic.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ATOMIC_H_\n#define _RTE_ATOMIC_H_\n\n/**\n * @file\n * Atomic Operations\n *\n * This file defines a generic API for atomic operations.\n */\n\n#include \n\n#ifdef __DOXYGEN__\n\n/**\n * General memory barrier.\n *\n * Guarantees that the LOAD and STORE operations generated before the\n * barrier occur before the LOAD and STORE operations generated after.\n * This function is architecture dependent.\n */\nstatic inline void rte_mb(void);\n\n/**\n * Write memory barrier.\n *\n * Guarantees that the STORE operations generated before the barrier\n * occur before the STORE operations generated after.\n * This function is architecture dependent.\n */\nstatic inline void rte_wmb(void);\n\n/**\n * Read memory barrier.\n *\n * Guarantees that the LOAD operations generated before the barrier\n * occur before the LOAD operations generated after.\n * This function is architecture dependent.\n */\nstatic inline void rte_rmb(void);\n\n#endif /* __DOXYGEN__ */\n\n/**\n * Compiler barrier.\n *\n * Guarantees that operation reordering does not occur at compile time\n * for operations directly before and after the barrier.\n */\n#define\trte_compiler_barrier() do {\t\t\\\n\tasm volatile (\"\" : : : \"memory\");\t\\\n} while(0)\n\n/*------------------------- 16 bit atomic operations -------------------------*/\n\n/**\n * Atomic compare and set.\n *\n * (atomic) equivalent to:\n * if (*dst == exp)\n * *dst = src (all 16-bit words)\n *\n * @param dst\n * The destination location into which the value will be written.\n * @param exp\n * The expected value.\n * @param src\n * The new value.\n * @return\n * Non-zero on success; 0 on failure.\n */\nstatic inline int\nrte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int\nrte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)\n{\n\treturn __sync_bool_compare_and_swap(dst, exp, src);\n}\n#endif\n\n/**\n * The atomic counter structure.\n */\ntypedef struct {\n\tvolatile int16_t cnt; /**< An internal counter value. */\n} rte_atomic16_t;\n\n/**\n * Static initializer for an atomic counter.\n */\n#define RTE_ATOMIC16_INIT(val) { (val) }\n\n/**\n * Initialize an atomic counter.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void\nrte_atomic16_init(rte_atomic16_t *v)\n{\n\tv->cnt = 0;\n}\n\n/**\n * Atomically read a 16-bit value from a counter.\n *\n * @param v\n * A pointer to the atomic counter.\n * @return\n * The value of the counter.\n */\nstatic inline int16_t\nrte_atomic16_read(const rte_atomic16_t *v)\n{\n\treturn v->cnt;\n}\n\n/**\n * Atomically set a counter to a 16-bit value.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param new_value\n * The new value for the counter.\n */\nstatic inline void\nrte_atomic16_set(rte_atomic16_t *v, int16_t new_value)\n{\n\tv->cnt = new_value;\n}\n\n/**\n * Atomically add a 16-bit value to an atomic counter.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param inc\n * The value to be added to the counter.\n */\nstatic inline void\nrte_atomic16_add(rte_atomic16_t *v, int16_t inc)\n{\n\t__sync_fetch_and_add(&v->cnt, inc);\n}\n\n/**\n * Atomically subtract a 16-bit value from an atomic counter.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param dec\n * The value to be subtracted from the counter.\n */\nstatic inline void\nrte_atomic16_sub(rte_atomic16_t *v, int16_t dec)\n{\n\t__sync_fetch_and_sub(&v->cnt, dec);\n}\n\n/**\n * Atomically increment a counter by one.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void\nrte_atomic16_inc(rte_atomic16_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_atomic16_inc(rte_atomic16_t *v)\n{\n\trte_atomic16_add(v, 1);\n}\n#endif\n\n/**\n * Atomically decrement a counter by one.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void\nrte_atomic16_dec(rte_atomic16_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_atomic16_dec(rte_atomic16_t *v)\n{\n\trte_atomic16_sub(v, 1);\n}\n#endif\n\n/**\n * Atomically add a 16-bit value to a counter and return the result.\n *\n * Atomically adds the 16-bits value (inc) to the atomic counter (v) and\n * returns the value of v after addition.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param inc\n * The value to be added to the counter.\n * @return\n * The value of v after the addition.\n */\nstatic inline int16_t\nrte_atomic16_add_return(rte_atomic16_t *v, int16_t inc)\n{\n\treturn __sync_add_and_fetch(&v->cnt, inc);\n}\n\n/**\n * Atomically subtract a 16-bit value from a counter and return\n * the result.\n *\n * Atomically subtracts the 16-bit value (inc) from the atomic counter\n * (v) and returns the value of v after the subtraction.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param dec\n * The value to be subtracted from the counter.\n * @return\n * The value of v after the subtraction.\n */\nstatic inline int16_t\nrte_atomic16_sub_return(rte_atomic16_t *v, int16_t dec)\n{\n\treturn __sync_sub_and_fetch(&v->cnt, dec);\n}\n\n/**\n * Atomically increment a 16-bit counter by one and test.\n *\n * Atomically increments the atomic counter (v) by one and returns true if\n * the result is 0, or false in all other cases.\n *\n * @param v\n * A pointer to the atomic counter.\n * @return\n * True if the result after the increment operation is 0; false otherwise.\n */\nstatic inline int rte_atomic16_inc_and_test(rte_atomic16_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)\n{\n\treturn (__sync_add_and_fetch(&v->cnt, 1) == 0);\n}\n#endif\n\n/**\n * Atomically decrement a 16-bit counter by one and test.\n *\n * Atomically decrements the atomic counter (v) by one and returns true if\n * the result is 0, or false in all other cases.\n *\n * @param v\n * A pointer to the atomic counter.\n * @return\n * True if the result after the decrement operation is 0; false otherwise.\n */\nstatic inline int rte_atomic16_dec_and_test(rte_atomic16_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)\n{\n\treturn (__sync_sub_and_fetch(&v->cnt, 1) == 0);\n}\n#endif\n\n/**\n * Atomically test and set a 16-bit atomic counter.\n *\n * If the counter value is already set, return 0 (failed). Otherwise, set\n * the counter value to 1 and return 1 (success).\n *\n * @param v\n * A pointer to the atomic counter.\n * @return\n * 0 if failed; else 1, success.\n */\nstatic inline int rte_atomic16_test_and_set(rte_atomic16_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int rte_atomic16_test_and_set(rte_atomic16_t *v)\n{\n\treturn rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);\n}\n#endif\n\n/**\n * Atomically set a 16-bit counter to 0.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void rte_atomic16_clear(rte_atomic16_t *v)\n{\n\tv->cnt = 0;\n}\n\n/*------------------------- 32 bit atomic operations -------------------------*/\n\n/**\n * Atomic compare and set.\n *\n * (atomic) equivalent to:\n * if (*dst == exp)\n * *dst = src (all 32-bit words)\n *\n * @param dst\n * The destination location into which the value will be written.\n * @param exp\n * The expected value.\n * @param src\n * The new value.\n * @return\n * Non-zero on success; 0 on failure.\n */\nstatic inline int\nrte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int\nrte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)\n{\n\treturn __sync_bool_compare_and_swap(dst, exp, src);\n}\n#endif\n\n/**\n * The atomic counter structure.\n */\ntypedef struct {\n\tvolatile int32_t cnt; /**< An internal counter value. */\n} rte_atomic32_t;\n\n/**\n * Static initializer for an atomic counter.\n */\n#define RTE_ATOMIC32_INIT(val) { (val) }\n\n/**\n * Initialize an atomic counter.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void\nrte_atomic32_init(rte_atomic32_t *v)\n{\n\tv->cnt = 0;\n}\n\n/**\n * Atomically read a 32-bit value from a counter.\n *\n * @param v\n * A pointer to the atomic counter.\n * @return\n * The value of the counter.\n */\nstatic inline int32_t\nrte_atomic32_read(const rte_atomic32_t *v)\n{\n\treturn v->cnt;\n}\n\n/**\n * Atomically set a counter to a 32-bit value.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param new_value\n * The new value for the counter.\n */\nstatic inline void\nrte_atomic32_set(rte_atomic32_t *v, int32_t new_value)\n{\n\tv->cnt = new_value;\n}\n\n/**\n * Atomically add a 32-bit value to an atomic counter.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param inc\n * The value to be added to the counter.\n */\nstatic inline void\nrte_atomic32_add(rte_atomic32_t *v, int32_t inc)\n{\n\t__sync_fetch_and_add(&v->cnt, inc);\n}\n\n/**\n * Atomically subtract a 32-bit value from an atomic counter.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param dec\n * The value to be subtracted from the counter.\n */\nstatic inline void\nrte_atomic32_sub(rte_atomic32_t *v, int32_t dec)\n{\n\t__sync_fetch_and_sub(&v->cnt, dec);\n}\n\n/**\n * Atomically increment a counter by one.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void\nrte_atomic32_inc(rte_atomic32_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_atomic32_inc(rte_atomic32_t *v)\n{\n\trte_atomic32_add(v, 1);\n}\n#endif\n\n/**\n * Atomically decrement a counter by one.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void\nrte_atomic32_dec(rte_atomic32_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_atomic32_dec(rte_atomic32_t *v)\n{\n\trte_atomic32_sub(v,1);\n}\n#endif\n\n/**\n * Atomically add a 32-bit value to a counter and return the result.\n *\n * Atomically adds the 32-bits value (inc) to the atomic counter (v) and\n * returns the value of v after addition.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param inc\n * The value to be added to the counter.\n * @return\n * The value of v after the addition.\n */\nstatic inline int32_t\nrte_atomic32_add_return(rte_atomic32_t *v, int32_t inc)\n{\n\treturn __sync_add_and_fetch(&v->cnt, inc);\n}\n\n/**\n * Atomically subtract a 32-bit value from a counter and return\n * the result.\n *\n * Atomically subtracts the 32-bit value (inc) from the atomic counter\n * (v) and returns the value of v after the subtraction.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param dec\n * The value to be subtracted from the counter.\n * @return\n * The value of v after the subtraction.\n */\nstatic inline int32_t\nrte_atomic32_sub_return(rte_atomic32_t *v, int32_t dec)\n{\n\treturn __sync_sub_and_fetch(&v->cnt, dec);\n}\n\n/**\n * Atomically increment a 32-bit counter by one and test.\n *\n * Atomically increments the atomic counter (v) by one and returns true if\n * the result is 0, or false in all other cases.\n *\n * @param v\n * A pointer to the atomic counter.\n * @return\n * True if the result after the increment operation is 0; false otherwise.\n */\nstatic inline int rte_atomic32_inc_and_test(rte_atomic32_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)\n{\n\treturn (__sync_add_and_fetch(&v->cnt, 1) == 0);\n}\n#endif\n\n/**\n * Atomically decrement a 32-bit counter by one and test.\n *\n * Atomically decrements the atomic counter (v) by one and returns true if\n * the result is 0, or false in all other cases.\n *\n * @param v\n * A pointer to the atomic counter.\n * @return\n * True if the result after the decrement operation is 0; false otherwise.\n */\nstatic inline int rte_atomic32_dec_and_test(rte_atomic32_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)\n{\n\treturn (__sync_sub_and_fetch(&v->cnt, 1) == 0);\n}\n#endif\n\n/**\n * Atomically test and set a 32-bit atomic counter.\n *\n * If the counter value is already set, return 0 (failed). Otherwise, set\n * the counter value to 1 and return 1 (success).\n *\n * @param v\n * A pointer to the atomic counter.\n * @return\n * 0 if failed; else 1, success.\n */\nstatic inline int rte_atomic32_test_and_set(rte_atomic32_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int rte_atomic32_test_and_set(rte_atomic32_t *v)\n{\n\treturn rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);\n}\n#endif\n\n/**\n * Atomically set a 32-bit counter to 0.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void rte_atomic32_clear(rte_atomic32_t *v)\n{\n\tv->cnt = 0;\n}\n\n/*------------------------- 64 bit atomic operations -------------------------*/\n\n/**\n * An atomic compare and set function used by the mutex functions.\n * (atomic) equivalent to:\n * if (*dst == exp)\n * *dst = src (all 64-bit words)\n *\n * @param dst\n * The destination into which the value will be written.\n * @param exp\n * The expected value.\n * @param src\n * The new value.\n * @return\n * Non-zero on success; 0 on failure.\n */\nstatic inline int\nrte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int\nrte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)\n{\n\treturn __sync_bool_compare_and_swap(dst, exp, src);\n}\n#endif\n\n/**\n * The atomic counter structure.\n */\ntypedef struct {\n\tvolatile int64_t cnt; /**< Internal counter value. */\n} rte_atomic64_t;\n\n/**\n * Static initializer for an atomic counter.\n */\n#define RTE_ATOMIC64_INIT(val) { (val) }\n\n/**\n * Initialize the atomic counter.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void\nrte_atomic64_init(rte_atomic64_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_atomic64_init(rte_atomic64_t *v)\n{\n#ifdef __LP64__\n\tv->cnt = 0;\n#else\n\tint success = 0;\n\tuint64_t tmp;\n\n\twhile (success == 0) {\n\t\ttmp = v->cnt;\n\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n\t\t tmp, 0);\n\t}\n#endif\n}\n#endif\n\n/**\n * Atomically read a 64-bit counter.\n *\n * @param v\n * A pointer to the atomic counter.\n * @return\n * The value of the counter.\n */\nstatic inline int64_t\nrte_atomic64_read(rte_atomic64_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int64_t\nrte_atomic64_read(rte_atomic64_t *v)\n{\n#ifdef __LP64__\n\treturn v->cnt;\n#else\n\tint success = 0;\n\tuint64_t tmp;\n\n\twhile (success == 0) {\n\t\ttmp = v->cnt;\n\t\t/* replace the value by itself */\n\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n\t\t tmp, tmp);\n\t}\n\treturn tmp;\n#endif\n}\n#endif\n\n/**\n * Atomically set a 64-bit counter.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param new_value\n * The new value of the counter.\n */\nstatic inline void\nrte_atomic64_set(rte_atomic64_t *v, int64_t new_value);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_atomic64_set(rte_atomic64_t *v, int64_t new_value)\n{\n#ifdef __LP64__\n\tv->cnt = new_value;\n#else\n\tint success = 0;\n\tuint64_t tmp;\n\n\twhile (success == 0) {\n\t\ttmp = v->cnt;\n\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n\t\t tmp, new_value);\n\t}\n#endif\n}\n#endif\n\n/**\n * Atomically add a 64-bit value to a counter.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param inc\n * The value to be added to the counter.\n */\nstatic inline void\nrte_atomic64_add(rte_atomic64_t *v, int64_t inc);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_atomic64_add(rte_atomic64_t *v, int64_t inc)\n{\n\t__sync_fetch_and_add(&v->cnt, inc);\n}\n#endif\n\n/**\n * Atomically subtract a 64-bit value from a counter.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param dec\n * The value to be subtracted from the counter.\n */\nstatic inline void\nrte_atomic64_sub(rte_atomic64_t *v, int64_t dec);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_atomic64_sub(rte_atomic64_t *v, int64_t dec)\n{\n\t__sync_fetch_and_sub(&v->cnt, dec);\n}\n#endif\n\n/**\n * Atomically increment a 64-bit counter by one and test.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void\nrte_atomic64_inc(rte_atomic64_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_atomic64_inc(rte_atomic64_t *v)\n{\n\trte_atomic64_add(v, 1);\n}\n#endif\n\n/**\n * Atomically decrement a 64-bit counter by one and test.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void\nrte_atomic64_dec(rte_atomic64_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_atomic64_dec(rte_atomic64_t *v)\n{\n\trte_atomic64_sub(v, 1);\n}\n#endif\n\n/**\n * Add a 64-bit value to an atomic counter and return the result.\n *\n * Atomically adds the 64-bit value (inc) to the atomic counter (v) and\n * returns the value of v after the addition.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param inc\n * The value to be added to the counter.\n * @return\n * The value of v after the addition.\n */\nstatic inline int64_t\nrte_atomic64_add_return(rte_atomic64_t *v, int64_t inc);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int64_t\nrte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)\n{\n\treturn __sync_add_and_fetch(&v->cnt, inc);\n}\n#endif\n\n/**\n * Subtract a 64-bit value from an atomic counter and return the result.\n *\n * Atomically subtracts the 64-bit value (dec) from the atomic counter (v)\n * and returns the value of v after the subtraction.\n *\n * @param v\n * A pointer to the atomic counter.\n * @param dec\n * The value to be subtracted from the counter.\n * @return\n * The value of v after the subtraction.\n */\nstatic inline int64_t\nrte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int64_t\nrte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)\n{\n\treturn __sync_sub_and_fetch(&v->cnt, dec);\n}\n#endif\n\n/**\n * Atomically increment a 64-bit counter by one and test.\n *\n * Atomically increments the atomic counter (v) by one and returns\n * true if the result is 0, or false in all other cases.\n *\n * @param v\n * A pointer to the atomic counter.\n * @return\n * True if the result after the addition is 0; false otherwise.\n */\nstatic inline int rte_atomic64_inc_and_test(rte_atomic64_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)\n{\n\treturn rte_atomic64_add_return(v, 1) == 0;\n}\n#endif\n\n/**\n * Atomically decrement a 64-bit counter by one and test.\n *\n * Atomically decrements the atomic counter (v) by one and returns true if\n * the result is 0, or false in all other cases.\n *\n * @param v\n * A pointer to the atomic counter.\n * @return\n * True if the result after subtraction is 0; false otherwise.\n */\nstatic inline int rte_atomic64_dec_and_test(rte_atomic64_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)\n{\n\treturn rte_atomic64_sub_return(v, 1) == 0;\n}\n#endif\n\n/**\n * Atomically test and set a 64-bit atomic counter.\n *\n * If the counter value is already set, return 0 (failed). Otherwise, set\n * the counter value to 1 and return 1 (success).\n *\n * @param v\n * A pointer to the atomic counter.\n * @return\n * 0 if failed; else 1, success.\n */\nstatic inline int rte_atomic64_test_and_set(rte_atomic64_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int rte_atomic64_test_and_set(rte_atomic64_t *v)\n{\n\treturn rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);\n}\n#endif\n\n/**\n * Atomically set a 64-bit counter to 0.\n *\n * @param v\n * A pointer to the atomic counter.\n */\nstatic inline void rte_atomic64_clear(rte_atomic64_t *v);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void rte_atomic64_clear(rte_atomic64_t *v)\n{\n\trte_atomic64_set(v, 0);\n}\n#endif\n\n#endif /* _RTE_ATOMIC_H_ */\n" }, { "path": "lib/librte_eal/common/include/generic/rte_byteorder.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_BYTEORDER_H_\n#define _RTE_BYTEORDER_H_\n\n/**\n * @file\n *\n * Byte Swap Operations\n *\n * This file defines a generic API for byte swap operations. Part of\n * the implementation is architecture-specific.\n */\n\n#include \n#ifdef RTE_EXEC_ENV_BSDAPP\n#include \n#else\n#include \n#endif\n\n/*\n * Compile-time endianness detection\n */\n#define RTE_BIG_ENDIAN 1\n#define RTE_LITTLE_ENDIAN 2\n#if defined __BYTE_ORDER__\n#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__\n#define RTE_BYTE_ORDER RTE_BIG_ENDIAN\n#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__\n#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN\n#endif /* __BYTE_ORDER__ */\n#elif defined __BYTE_ORDER\n#if __BYTE_ORDER == __BIG_ENDIAN\n#define RTE_BYTE_ORDER RTE_BIG_ENDIAN\n#elif __BYTE_ORDER == __LITTLE_ENDIAN\n#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN\n#endif /* __BYTE_ORDER */\n#elif defined __BIG_ENDIAN__\n#define RTE_BYTE_ORDER RTE_BIG_ENDIAN\n#elif defined __LITTLE_ENDIAN__\n#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN\n#endif\n\n/*\n * An internal function to swap bytes in a 16-bit value.\n *\n * It is used by rte_bswap16() when the value is constant. Do not use\n * this function directly; rte_bswap16() is preferred.\n */\nstatic inline uint16_t\nrte_constant_bswap16(uint16_t x)\n{\n\treturn (uint16_t)(((x & 0x00ffU) << 8) |\n\t\t((x & 0xff00U) >> 8));\n}\n\n/*\n * An internal function to swap bytes in a 32-bit value.\n *\n * It is used by rte_bswap32() when the value is constant. Do not use\n * this function directly; rte_bswap32() is preferred.\n */\nstatic inline uint32_t\nrte_constant_bswap32(uint32_t x)\n{\n\treturn ((x & 0x000000ffUL) << 24) |\n\t\t((x & 0x0000ff00UL) << 8) |\n\t\t((x & 0x00ff0000UL) >> 8) |\n\t\t((x & 0xff000000UL) >> 24);\n}\n\n/*\n * An internal function to swap bytes of a 64-bit value.\n *\n * It is used by rte_bswap64() when the value is constant. Do not use\n * this function directly; rte_bswap64() is preferred.\n */\nstatic inline uint64_t\nrte_constant_bswap64(uint64_t x)\n{\n\treturn ((x & 0x00000000000000ffULL) << 56) |\n\t\t((x & 0x000000000000ff00ULL) << 40) |\n\t\t((x & 0x0000000000ff0000ULL) << 24) |\n\t\t((x & 0x00000000ff000000ULL) << 8) |\n\t\t((x & 0x000000ff00000000ULL) >> 8) |\n\t\t((x & 0x0000ff0000000000ULL) >> 24) |\n\t\t((x & 0x00ff000000000000ULL) >> 40) |\n\t\t((x & 0xff00000000000000ULL) >> 56);\n}\n\n\n#ifdef __DOXYGEN__\n\n/**\n * Swap bytes in a 16-bit value.\n */\nstatic uint16_t rte_bswap16(uint16_t _x);\n\n/**\n * Swap bytes in a 32-bit value.\n */\nstatic uint32_t rte_bswap32(uint32_t x);\n\n/**\n * Swap bytes in a 64-bit value.\n */\nstatic uint64_t rte_bswap64(uint64_t x);\n\n/**\n * Convert a 16-bit value from CPU order to little endian.\n */\nstatic uint16_t rte_cpu_to_le_16(uint16_t x);\n\n/**\n * Convert a 32-bit value from CPU order to little endian.\n */\nstatic uint32_t rte_cpu_to_le_32(uint32_t x);\n\n/**\n * Convert a 64-bit value from CPU order to little endian.\n */\nstatic uint64_t rte_cpu_to_le_64(uint64_t x);\n\n\n/**\n * Convert a 16-bit value from CPU order to big endian.\n */\nstatic uint16_t rte_cpu_to_be_16(uint16_t x);\n\n/**\n * Convert a 32-bit value from CPU order to big endian.\n */\nstatic uint32_t rte_cpu_to_be_32(uint32_t x);\n\n/**\n * Convert a 64-bit value from CPU order to big endian.\n */\nstatic uint64_t rte_cpu_to_be_64(uint64_t x);\n\n\n/**\n * Convert a 16-bit value from little endian to CPU order.\n */\nstatic uint16_t rte_le_to_cpu_16(uint16_t x);\n\n/**\n * Convert a 32-bit value from little endian to CPU order.\n */\nstatic uint32_t rte_le_to_cpu_32(uint32_t x);\n\n/**\n * Convert a 64-bit value from little endian to CPU order.\n */\nstatic uint64_t rte_le_to_cpu_64(uint64_t x);\n\n\n/**\n * Convert a 16-bit value from big endian to CPU order.\n */\nstatic uint16_t rte_be_to_cpu_16(uint16_t x);\n\n/**\n * Convert a 32-bit value from big endian to CPU order.\n */\nstatic uint32_t rte_be_to_cpu_32(uint32_t x);\n\n/**\n * Convert a 64-bit value from big endian to CPU order.\n */\nstatic uint64_t rte_be_to_cpu_64(uint64_t x);\n\n#endif /* __DOXYGEN__ */\n\n#ifdef RTE_FORCE_INTRINSICS\n#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n#define rte_bswap16(x) __builtin_bswap16(x)\n#endif\n\n#define rte_bswap32(x) __builtin_bswap32(x)\n\n#define rte_bswap64(x) __builtin_bswap64(x)\n\n#endif\n\n#endif /* _RTE_BYTEORDER_H_ */\n" }, { "path": "lib/librte_eal/common/include/generic/rte_cpuflags.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_CPUFLAGS_H_\n#define _RTE_CPUFLAGS_H_\n\n/**\n * @file\n * Architecture specific API to determine available CPU features at runtime.\n */\n\n#include \n#include \n#include \n#include \n\n#ifdef __cplusplus\n#define __RTE_CPUFLAG_UNDERLYING_TYPE : unsigned int\n#define __RTE_REGISTER_UNDERLYING_TYPE : unsigned int\n#else\n#define __RTE_CPUFLAG_UNDERLYING_TYPE\n#define __RTE_REGISTER_UNDERLYING_TYPE\n#endif\n\n/**\n * Enumeration of all CPU features supported\n */\nenum rte_cpu_flag_t __RTE_CPUFLAG_UNDERLYING_TYPE;\n\n/**\n * Enumeration of CPU registers\n */\nenum cpu_register_t __RTE_REGISTER_UNDERLYING_TYPE;\n\ntypedef uint32_t cpuid_registers_t[4];\n\n#define CPU_FLAG_NAME_MAX_LEN 64\n\n/**\n * Struct to hold a processor feature entry\n */\nstruct feature_entry {\n\tuint32_t leaf;\t\t\t\t/**< cpuid leaf */\n\tuint32_t subleaf;\t\t\t/**< cpuid subleaf */\n\tuint32_t reg;\t\t\t\t/**< cpuid register */\n\tuint32_t bit;\t\t\t\t/**< cpuid register bit */\n\tchar name[CPU_FLAG_NAME_MAX_LEN]; /**< String for printing */\n};\n\n#define FEAT_DEF(name, leaf, subleaf, reg, bit) \\\n\t[RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name },\n\n/**\n * An array that holds feature entries\n *\n * Defined in arch-specific rte_cpuflags.h.\n */\n#ifdef __DOXYGEN__\nstatic const struct feature_entry cpu_feature_table[];\n#endif\n\n/**\n * Execute CPUID instruction and get contents of a specific register\n *\n * This function, when compiled with GCC, will generate architecture-neutral\n * code, as per GCC manual.\n */\nstatic inline void\nrte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out);\n\n/**\n * Function for checking a CPU flag availability\n *\n * @param feature\n * CPU flag to query CPU for\n * @return\n * 1 if flag is available\n * 0 if flag is not available\n * -ENOENT if flag is invalid\n */\nstatic inline int\nrte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature);\n\n/**\n * This function checks that the currently used CPU supports the CPU features\n * that were specified at compile time. It is called automatically within the\n * EAL, so does not need to be used by applications.\n */\nvoid\nrte_cpu_check_supported(void);\n\n#endif /* _RTE_CPUFLAGS_H_ */\n" }, { "path": "lib/librte_eal/common/include/generic/rte_cycles.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n/* BSD LICENSE\n *\n * Copyright(c) 2013 6WIND.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_CYCLES_H_\n#define _RTE_CYCLES_H_\n\n/**\n * @file\n *\n * Simple Time Reference Functions (Cycles and HPET).\n */\n\n#include \n#include \n#include \n\n#define MS_PER_S 1000\n#define US_PER_S 1000000\n#define NS_PER_S 1000000000\n\nenum timer_source {\n\tEAL_TIMER_TSC = 0,\n\tEAL_TIMER_HPET\n};\nextern enum timer_source eal_timer_source;\n\n/**\n * Get the measured frequency of the RDTSC counter\n *\n * @return\n * The TSC frequency for this lcore\n */\nuint64_t\nrte_get_tsc_hz(void);\n\n/**\n * Return the number of TSC cycles since boot\n *\n * @return\n * the number of cycles\n */\nstatic inline uint64_t\nrte_get_tsc_cycles(void);\n\n#ifdef RTE_LIBEAL_USE_HPET\n/**\n * Return the number of HPET cycles since boot\n *\n * This counter is global for all execution units. The number of\n * cycles in one second can be retrieved using rte_get_hpet_hz().\n *\n * @return\n * the number of cycles\n */\nuint64_t\nrte_get_hpet_cycles(void);\n\n/**\n * Get the number of HPET cycles in one second.\n *\n * @return\n * The number of cycles in one second.\n */\nuint64_t\nrte_get_hpet_hz(void);\n\n/**\n * Initialise the HPET for use. This must be called before the rte_get_hpet_hz\n * and rte_get_hpet_cycles APIs are called. If this function does not succeed,\n * then the HPET functions are unavailable and should not be called.\n *\n * @param make_default\n *\tIf set, the hpet timer becomes the default timer whose values are\n *\treturned by the rte_get_timer_hz/cycles API calls\n *\n * @return\n *\t0 on success,\n *\t-1 on error, and the make_default parameter is ignored.\n */\nint rte_eal_hpet_init(int make_default);\n\n#endif\n\n/**\n * Get the number of cycles since boot from the default timer.\n *\n * @return\n * The number of cycles\n */\nstatic inline uint64_t\nrte_get_timer_cycles(void)\n{\n\tswitch(eal_timer_source) {\n\tcase EAL_TIMER_TSC:\n\t\treturn rte_get_tsc_cycles();\n\tcase EAL_TIMER_HPET:\n#ifdef RTE_LIBEAL_USE_HPET\n\t\treturn rte_get_hpet_cycles();\n#endif\n\tdefault: rte_panic(\"Invalid timer source specified\\n\");\n\t}\n}\n\n/**\n * Get the number of cycles in one second for the default timer.\n *\n * @return\n * The number of cycles in one second.\n */\nstatic inline uint64_t\nrte_get_timer_hz(void)\n{\n\tswitch(eal_timer_source) {\n\tcase EAL_TIMER_TSC:\n\t\treturn rte_get_tsc_hz();\n\tcase EAL_TIMER_HPET:\n#ifdef RTE_LIBEAL_USE_HPET\n\t\treturn rte_get_hpet_hz();\n#endif\n\tdefault: rte_panic(\"Invalid timer source specified\\n\");\n\t}\n}\n\n/**\n * Wait at least us microseconds.\n *\n * @param us\n * The number of microseconds to wait.\n */\nvoid\nrte_delay_us(unsigned us);\n\n/**\n * Wait at least ms milliseconds.\n *\n * @param ms\n * The number of milliseconds to wait.\n */\nstatic inline void\nrte_delay_ms(unsigned ms)\n{\n\trte_delay_us(ms * 1000);\n}\n\n#endif /* _RTE_CYCLES_H_ */\n" }, { "path": "lib/librte_eal/common/include/generic/rte_memcpy.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_MEMCPY_H_\n#define _RTE_MEMCPY_H_\n\n/**\n * @file\n *\n * Functions for vectorised implementation of memcpy().\n */\n\n/**\n * Copy 16 bytes from one location to another using optimised\n * instructions. The locations should not overlap.\n *\n * @param dst\n * Pointer to the destination of the data.\n * @param src\n * Pointer to the source data.\n */\nstatic inline void\nrte_mov16(uint8_t *dst, const uint8_t *src);\n\n/**\n * Copy 32 bytes from one location to another using optimised\n * instructions. The locations should not overlap.\n *\n * @param dst\n * Pointer to the destination of the data.\n * @param src\n * Pointer to the source data.\n */\nstatic inline void\nrte_mov32(uint8_t *dst, const uint8_t *src);\n\n/**\n * Copy 48 bytes from one location to another using optimised\n * instructions. The locations should not overlap.\n *\n * @param dst\n * Pointer to the destination of the data.\n * @param src\n * Pointer to the source data.\n */\nstatic inline void\nrte_mov48(uint8_t *dst, const uint8_t *src);\n\n/**\n * Copy 64 bytes from one location to another using optimised\n * instructions. The locations should not overlap.\n *\n * @param dst\n * Pointer to the destination of the data.\n * @param src\n * Pointer to the source data.\n */\nstatic inline void\nrte_mov64(uint8_t *dst, const uint8_t *src);\n\n/**\n * Copy 128 bytes from one location to another using optimised\n * instructions. The locations should not overlap.\n *\n * @param dst\n * Pointer to the destination of the data.\n * @param src\n * Pointer to the source data.\n */\nstatic inline void\nrte_mov128(uint8_t *dst, const uint8_t *src);\n\n/**\n * Copy 256 bytes from one location to another using optimised\n * instructions. The locations should not overlap.\n *\n * @param dst\n * Pointer to the destination of the data.\n * @param src\n * Pointer to the source data.\n */\nstatic inline void\nrte_mov256(uint8_t *dst, const uint8_t *src);\n\n#ifdef __DOXYGEN__\n\n/**\n * Copy bytes from one location to another. The locations must not overlap.\n *\n * @note This is implemented as a macro, so it's address should not be taken\n * and care is needed as parameter expressions may be evaluated multiple times.\n *\n * @param dst\n * Pointer to the destination of the data.\n * @param src\n * Pointer to the source data.\n * @param n\n * Number of bytes to copy.\n * @return\n * Pointer to the destination data.\n */\nstatic void *\nrte_memcpy(void *dst, const void *src, size_t n);\n\n#endif /* __DOXYGEN__ */\n\n/*\n * memcpy() function used by rte_memcpy macro\n */\nstatic inline void *\nrte_memcpy_func(void *dst, const void *src, size_t n) __attribute__((always_inline));\n\n\n#endif /* _RTE_MEMCPY_H_ */\n" }, { "path": "lib/librte_eal/common/include/generic/rte_prefetch.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_PREFETCH_H_\n#define _RTE_PREFETCH_H_\n\n/**\n * @file\n *\n * Prefetch operations.\n *\n * This file defines an API for prefetch macros / inline-functions,\n * which are architecture-dependent. Prefetching occurs when a\n * processor requests an instruction or data from memory to cache\n * before it is actually needed, potentially speeding up the execution of the\n * program.\n */\n\n/**\n * Prefetch a cache line into all cache levels.\n * @param p\n * Address to prefetch\n */\nstatic inline void rte_prefetch0(const volatile void *p);\n\n/**\n * Prefetch a cache line into all cache levels except the 0th cache level.\n * @param p\n * Address to prefetch\n */\nstatic inline void rte_prefetch1(const volatile void *p);\n\n/**\n * Prefetch a cache line into all cache levels except the 0th and 1th cache\n * levels.\n * @param p\n * Address to prefetch\n */\nstatic inline void rte_prefetch2(const volatile void *p);\n\n#endif /* _RTE_PREFETCH_H_ */\n" }, { "path": "lib/librte_eal/common/include/generic/rte_rwlock.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_RWLOCK_H_\n#define _RTE_RWLOCK_H_\n\n/**\n * @file\n *\n * RTE Read-Write Locks\n *\n * This file defines an API for read-write locks. The lock is used to\n * protect data that allows multiple readers in parallel, but only\n * one writer. All readers are blocked until the writer is finished\n * writing.\n *\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n\n/**\n * The rte_rwlock_t type.\n *\n * cnt is -1 when write lock is held, and > 0 when read locks are held.\n */\ntypedef struct {\n\tvolatile int32_t cnt; /**< -1 when W lock held, > 0 when R locks held. */\n} rte_rwlock_t;\n\n/**\n * A static rwlock initializer.\n */\n#define RTE_RWLOCK_INITIALIZER { 0 }\n\n/**\n * Initialize the rwlock to an unlocked state.\n *\n * @param rwl\n * A pointer to the rwlock structure.\n */\nstatic inline void\nrte_rwlock_init(rte_rwlock_t *rwl)\n{\n\trwl->cnt = 0;\n}\n\n/**\n * Take a read lock. Loop until the lock is held.\n *\n * @param rwl\n * A pointer to a rwlock structure.\n */\nstatic inline void\nrte_rwlock_read_lock(rte_rwlock_t *rwl)\n{\n\tint32_t x;\n\tint success = 0;\n\n\twhile (success == 0) {\n\t\tx = rwl->cnt;\n\t\t/* write lock is held */\n\t\tif (x < 0) {\n\t\t\trte_pause();\n\t\t\tcontinue;\n\t\t}\n\t\tsuccess = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt,\n\t\t\t\t\t x, x + 1);\n\t}\n}\n\n/**\n * Release a read lock.\n *\n * @param rwl\n * A pointer to the rwlock structure.\n */\nstatic inline void\nrte_rwlock_read_unlock(rte_rwlock_t *rwl)\n{\n\trte_atomic32_dec((rte_atomic32_t *)(intptr_t)&rwl->cnt);\n}\n\n/**\n * Take a write lock. Loop until the lock is held.\n *\n * @param rwl\n * A pointer to a rwlock structure.\n */\nstatic inline void\nrte_rwlock_write_lock(rte_rwlock_t *rwl)\n{\n\tint32_t x;\n\tint success = 0;\n\n\twhile (success == 0) {\n\t\tx = rwl->cnt;\n\t\t/* a lock is held */\n\t\tif (x != 0) {\n\t\t\trte_pause();\n\t\t\tcontinue;\n\t\t}\n\t\tsuccess = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt,\n\t\t\t\t\t 0, -1);\n\t}\n}\n\n/**\n * Release a write lock.\n *\n * @param rwl\n * A pointer to a rwlock structure.\n */\nstatic inline void\nrte_rwlock_write_unlock(rte_rwlock_t *rwl)\n{\n\trte_atomic32_inc((rte_atomic32_t *)(intptr_t)&rwl->cnt);\n}\n\n/**\n * Try to execute critical section in a hardware memory transaction, if it\n * fails or not available take a read lock\n *\n * NOTE: An attempt to perform a HW I/O operation inside a hardware memory\n * transaction always aborts the transaction since the CPU is not able to\n * roll-back should the transaction fail. Therefore, hardware transactional\n * locks are not advised to be used around rte_eth_rx_burst() and\n * rte_eth_tx_burst() calls.\n *\n * @param rwl\n * A pointer to a rwlock structure.\n */\nstatic inline void\nrte_rwlock_read_lock_tm(rte_rwlock_t *rwl);\n\n/**\n * Commit hardware memory transaction or release the read lock if the lock is used as a fall-back\n *\n * @param rwl\n * A pointer to the rwlock structure.\n */\nstatic inline void\nrte_rwlock_read_unlock_tm(rte_rwlock_t *rwl);\n\n/**\n * Try to execute critical section in a hardware memory transaction, if it\n * fails or not available take a write lock\n *\n * NOTE: An attempt to perform a HW I/O operation inside a hardware memory\n * transaction always aborts the transaction since the CPU is not able to\n * roll-back should the transaction fail. Therefore, hardware transactional\n * locks are not advised to be used around rte_eth_rx_burst() and\n * rte_eth_tx_burst() calls.\n *\n * @param rwl\n * A pointer to a rwlock structure.\n */\nstatic inline void\nrte_rwlock_write_lock_tm(rte_rwlock_t *rwl);\n\n/**\n * Commit hardware memory transaction or release the write lock if the lock is used as a fall-back\n *\n * @param rwl\n * A pointer to a rwlock structure.\n */\nstatic inline void\nrte_rwlock_write_unlock_tm(rte_rwlock_t *rwl);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_RWLOCK_H_ */\n" }, { "path": "lib/librte_eal/common/include/generic/rte_spinlock.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_SPINLOCK_H_\n#define _RTE_SPINLOCK_H_\n\n/**\n * @file\n *\n * RTE Spinlocks\n *\n * This file defines an API for read-write locks, which are implemented\n * in an architecture-specific way. This kind of lock simply waits in\n * a loop repeatedly checking until the lock becomes available.\n *\n * All locks must be initialised before use, and only initialised once.\n *\n */\n\n#include \n#ifdef RTE_FORCE_INTRINSICS\n#include \n#endif\n\n/**\n * The rte_spinlock_t type.\n */\ntypedef struct {\n\tvolatile int locked; /**< lock status 0 = unlocked, 1 = locked */\n} rte_spinlock_t;\n\n/**\n * A static spinlock initializer.\n */\n#define RTE_SPINLOCK_INITIALIZER { 0 }\n\n/**\n * Initialize the spinlock to an unlocked state.\n *\n * @param sl\n * A pointer to the spinlock.\n */\nstatic inline void\nrte_spinlock_init(rte_spinlock_t *sl)\n{\n\tsl->locked = 0;\n}\n\n/**\n * Take the spinlock.\n *\n * @param sl\n * A pointer to the spinlock.\n */\nstatic inline void\nrte_spinlock_lock(rte_spinlock_t *sl);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_spinlock_lock(rte_spinlock_t *sl)\n{\n\twhile (__sync_lock_test_and_set(&sl->locked, 1))\n\t\twhile(sl->locked)\n\t\t\trte_pause();\n}\n#endif\n\n/**\n * Release the spinlock.\n *\n * @param sl\n * A pointer to the spinlock.\n */\nstatic inline void\nrte_spinlock_unlock (rte_spinlock_t *sl);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline void\nrte_spinlock_unlock (rte_spinlock_t *sl)\n{\n\t__sync_lock_release(&sl->locked);\n}\n#endif\n\n/**\n * Try to take the lock.\n *\n * @param sl\n * A pointer to the spinlock.\n * @return\n * 1 if the lock is successfully taken; 0 otherwise.\n */\nstatic inline int\nrte_spinlock_trylock (rte_spinlock_t *sl);\n\n#ifdef RTE_FORCE_INTRINSICS\nstatic inline int\nrte_spinlock_trylock (rte_spinlock_t *sl)\n{\n\treturn (__sync_lock_test_and_set(&sl->locked,1) == 0);\n}\n#endif\n\n/**\n * Test if the lock is taken.\n *\n * @param sl\n * A pointer to the spinlock.\n * @return\n * 1 if the lock is currently taken; 0 otherwise.\n */\nstatic inline int rte_spinlock_is_locked (rte_spinlock_t *sl)\n{\n\treturn sl->locked;\n}\n\n/**\n * Test if hardware transactional memory (lock elision) is supported\n *\n * @return\n * 1 if the hardware transactional memory is supported; 0 otherwise.\n */\nstatic inline int rte_tm_supported(void);\n\n/**\n * Try to execute critical section in a hardware memory transaction,\n * if it fails or not available take the spinlock.\n *\n * NOTE: An attempt to perform a HW I/O operation inside a hardware memory\n * transaction always aborts the transaction since the CPU is not able to\n * roll-back should the transaction fail. Therefore, hardware transactional\n * locks are not advised to be used around rte_eth_rx_burst() and\n * rte_eth_tx_burst() calls.\n *\n * @param sl\n * A pointer to the spinlock.\n */\nstatic inline void\nrte_spinlock_lock_tm(rte_spinlock_t *sl);\n\n/**\n * Commit hardware memory transaction or release the spinlock if\n * the spinlock is used as a fall-back\n *\n * @param sl\n * A pointer to the spinlock.\n */\nstatic inline void\nrte_spinlock_unlock_tm(rte_spinlock_t *sl);\n\n/**\n * Try to execute critical section in a hardware memory transaction,\n * if it fails or not available try to take the lock.\n *\n * NOTE: An attempt to perform a HW I/O operation inside a hardware memory\n * transaction always aborts the transaction since the CPU is not able to\n * roll-back should the transaction fail. Therefore, hardware transactional\n * locks are not advised to be used around rte_eth_rx_burst() and\n * rte_eth_tx_burst() calls.\n *\n * @param sl\n * A pointer to the spinlock.\n * @return\n * 1 if the hardware memory transaction is successfully started\n * or lock is successfully taken; 0 otherwise.\n */\nstatic inline int\nrte_spinlock_trylock_tm(rte_spinlock_t *sl);\n\n/**\n * The rte_spinlock_recursive_t type.\n */\ntypedef struct {\n\trte_spinlock_t sl; /**< the actual spinlock */\n\tvolatile int user; /**< core id using lock, -1 for unused */\n\tvolatile int count; /**< count of time this lock has been called */\n} rte_spinlock_recursive_t;\n\n/**\n * A static recursive spinlock initializer.\n */\n#define RTE_SPINLOCK_RECURSIVE_INITIALIZER {RTE_SPINLOCK_INITIALIZER, -1, 0}\n\n/**\n * Initialize the recursive spinlock to an unlocked state.\n *\n * @param slr\n * A pointer to the recursive spinlock.\n */\nstatic inline void rte_spinlock_recursive_init(rte_spinlock_recursive_t *slr)\n{\n\trte_spinlock_init(&slr->sl);\n\tslr->user = -1;\n\tslr->count = 0;\n}\n\n/**\n * Take the recursive spinlock.\n *\n * @param slr\n * A pointer to the recursive spinlock.\n */\nstatic inline void rte_spinlock_recursive_lock(rte_spinlock_recursive_t *slr)\n{\n\tint id = rte_gettid();\n\n\tif (slr->user != id) {\n\t\trte_spinlock_lock(&slr->sl);\n\t\tslr->user = id;\n\t}\n\tslr->count++;\n}\n/**\n * Release the recursive spinlock.\n *\n * @param slr\n * A pointer to the recursive spinlock.\n */\nstatic inline void rte_spinlock_recursive_unlock(rte_spinlock_recursive_t *slr)\n{\n\tif (--(slr->count) == 0) {\n\t\tslr->user = -1;\n\t\trte_spinlock_unlock(&slr->sl);\n\t}\n\n}\n\n/**\n * Try to take the recursive lock.\n *\n * @param slr\n * A pointer to the recursive spinlock.\n * @return\n * 1 if the lock is successfully taken; 0 otherwise.\n */\nstatic inline int rte_spinlock_recursive_trylock(rte_spinlock_recursive_t *slr)\n{\n\tint id = rte_gettid();\n\n\tif (slr->user != id) {\n\t\tif (rte_spinlock_trylock(&slr->sl) == 0)\n\t\t\treturn 0;\n\t\tslr->user = id;\n\t}\n\tslr->count++;\n\treturn 1;\n}\n\n\n/**\n * Try to execute critical section in a hardware memory transaction,\n * if it fails or not available take the recursive spinlocks\n *\n * NOTE: An attempt to perform a HW I/O operation inside a hardware memory\n * transaction always aborts the transaction since the CPU is not able to\n * roll-back should the transaction fail. Therefore, hardware transactional\n * locks are not advised to be used around rte_eth_rx_burst() and\n * rte_eth_tx_burst() calls.\n *\n * @param slr\n * A pointer to the recursive spinlock.\n */\nstatic inline void rte_spinlock_recursive_lock_tm(\n\trte_spinlock_recursive_t *slr);\n\n/**\n * Commit hardware memory transaction or release the recursive spinlock\n * if the recursive spinlock is used as a fall-back\n *\n * @param slr\n * A pointer to the recursive spinlock.\n */\nstatic inline void rte_spinlock_recursive_unlock_tm(\n\trte_spinlock_recursive_t *slr);\n\n/**\n * Try to execute critical section in a hardware memory transaction,\n * if it fails or not available try to take the recursive lock\n *\n * NOTE: An attempt to perform a HW I/O operation inside a hardware memory\n * transaction always aborts the transaction since the CPU is not able to\n * roll-back should the transaction fail. Therefore, hardware transactional\n * locks are not advised to be used around rte_eth_rx_burst() and\n * rte_eth_tx_burst() calls.\n *\n * @param slr\n * A pointer to the recursive spinlock.\n * @return\n * 1 if the hardware memory transaction is successfully started\n * or lock is successfully taken; 0 otherwise.\n */\nstatic inline int rte_spinlock_recursive_trylock_tm(\n\trte_spinlock_recursive_t *slr);\n\n#endif /* _RTE_SPINLOCK_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_alarm.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ALARM_H_\n#define _RTE_ALARM_H_\n\n/**\n * @file\n *\n * Alarm functions\n *\n * Simple alarm-clock functionality supplied by eal.\n * Does not require hpet support.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n/**\n * Signature of callback back function called when an alarm goes off.\n */\ntypedef void (*rte_eal_alarm_callback)(void *arg);\n\n/**\n * Function to set a callback to be triggered when us microseconds\n * have expired. Accuracy of timing to the microsecond is not guaranteed. The\n * alarm function will not be called *before* the requested time, but may\n * be called a short period of time afterwards.\n * The alarm handler will be called only once. There is no need to call\n * \"rte_eal_alarm_cancel\" from within the callback function.\n *\n * @param us\n * The time in microseconds before the callback is called\n * @param cb\n * The function to be called when the alarm expires\n * @param cb_arg\n * Pointer parameter to be passed to the callback function\n *\n * @return\n * On success, zero.\n * On failure, a negative error number\n */\nint rte_eal_alarm_set(uint64_t us, rte_eal_alarm_callback cb, void *cb_arg);\n\n/**\n * Function to cancel an alarm callback which has been registered before. If\n * used outside alarm callback it wait for all callbacks to finish execution.\n *\n * @param cb_fn\n * alarm callback\n * @param cb_arg\n * Pointer parameter to be passed to the callback function. To remove all\n * copies of a given callback function, irrespective of parameter, (void *)-1\n * can be used here.\n *\n * @return\n * - value greater than 0 and rte_errno not changed - returned value is\n * the number of canceled alarm callback functions\n * - value greater or equal 0 and rte_errno set to EINPROGRESS, at least one\n * alarm could not be canceled because cancellation was requested from alarm\n * callback context. Returned value is the number of succesfuly canceled\n * alarm callbacks\n * - 0 and rte_errno set to ENOENT - no alarm found\n * - -1 and rte_errno set to EINVAL - invalid parameter (NULL callback)\n */\nint rte_eal_alarm_cancel(rte_eal_alarm_callback cb_fn, void *cb_arg);\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* _RTE_ALARM_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_branch_prediction.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/**\n * @file\n * Branch Prediction Helpers in RTE\n */\n\n#ifndef _RTE_BRANCH_PREDICTION_H_\n#define _RTE_BRANCH_PREDICTION_H_\n\n/**\n * Check if a branch is likely to be taken.\n *\n * This compiler builtin allows the developer to indicate if a branch is\n * likely to be taken. Example:\n *\n * if (likely(x > 1))\n * do_stuff();\n *\n */\n#ifndef likely\n#define likely(x) __builtin_expect((x),1)\n#endif /* likely */\n\n/**\n * Check if a branch is unlikely to be taken.\n *\n * This compiler builtin allows the developer to indicate if a branch is\n * unlikely to be taken. Example:\n *\n * if (unlikely(x < 1))\n * do_stuff();\n *\n */\n#ifndef unlikely\n#define unlikely(x) __builtin_expect((x),0)\n#endif /* unlikely */\n\n#endif /* _RTE_BRANCH_PREDICTION_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_common.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_COMMON_H_\n#define _RTE_COMMON_H_\n\n/**\n * @file\n *\n * Generic, commonly-used macro and inline function definitions\n * for Intel DPDK.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n#include \n#include \n#include \n\n#ifndef typeof\n#define typeof __typeof__\n#endif\n\n#ifndef asm\n#define asm __asm__\n#endif\n\n#ifdef RTE_ARCH_STRICT_ALIGN\ntypedef uint64_t unaligned_uint64_t __attribute__ ((aligned(1)));\ntypedef uint32_t unaligned_uint32_t __attribute__ ((aligned(1)));\ntypedef uint16_t unaligned_uint16_t __attribute__ ((aligned(1)));\n#else\ntypedef uint64_t unaligned_uint64_t;\ntypedef uint32_t unaligned_uint32_t;\ntypedef uint16_t unaligned_uint16_t;\n#endif\n\n/*********** Macros to eliminate unused variable warnings ********/\n\n/**\n * short definition to mark a function parameter unused\n */\n#define __rte_unused __attribute__((__unused__))\n\n/**\n * definition to mark a variable or function parameter as used so\n * as to avoid a compiler warning\n */\n#define RTE_SET_USED(x) (void)(x)\n\n/*********** Macros for pointer arithmetic ********/\n\n/**\n * add a byte-value offset from a pointer\n */\n#define RTE_PTR_ADD(ptr, x) ((void*)((uintptr_t)(ptr) + (x)))\n\n/**\n * subtract a byte-value offset from a pointer\n */\n#define RTE_PTR_SUB(ptr, x) ((void*)((uintptr_t)ptr - (x)))\n\n/**\n * get the difference between two pointer values, i.e. how far apart\n * in bytes are the locations they point two. It is assumed that\n * ptr1 is greater than ptr2.\n */\n#define RTE_PTR_DIFF(ptr1, ptr2) ((uintptr_t)(ptr1) - (uintptr_t)(ptr2))\n\n/*********** Macros/static functions for doing alignment ********/\n\n\n/**\n * Macro to align a pointer to a given power-of-two. The resultant\n * pointer will be a pointer of the same type as the first parameter, and\n * point to an address no higher than the first parameter. Second parameter\n * must be a power-of-two value.\n */\n#define RTE_PTR_ALIGN_FLOOR(ptr, align) \\\n\t((typeof(ptr))RTE_ALIGN_FLOOR((uintptr_t)ptr, align))\n\n/**\n * Macro to align a value to a given power-of-two. The resultant value\n * will be of the same type as the first parameter, and will be no\n * bigger than the first parameter. Second parameter must be a\n * power-of-two value.\n */\n#define RTE_ALIGN_FLOOR(val, align) \\\n\t(typeof(val))((val) & (~((typeof(val))((align) - 1))))\n\n/**\n * Macro to align a pointer to a given power-of-two. The resultant\n * pointer will be a pointer of the same type as the first parameter, and\n * point to an address no lower than the first parameter. Second parameter\n * must be a power-of-two value.\n */\n#define RTE_PTR_ALIGN_CEIL(ptr, align) \\\n\tRTE_PTR_ALIGN_FLOOR((typeof(ptr))RTE_PTR_ADD(ptr, (align) - 1), align)\n\n/**\n * Macro to align a value to a given power-of-two. The resultant value\n * will be of the same type as the first parameter, and will be no lower\n * than the first parameter. Second parameter must be a power-of-two\n * value.\n */\n#define RTE_ALIGN_CEIL(val, align) \\\n\tRTE_ALIGN_FLOOR(((val) + ((typeof(val)) (align) - 1)), align)\n\n/**\n * Macro to align a pointer to a given power-of-two. The resultant\n * pointer will be a pointer of the same type as the first parameter, and\n * point to an address no lower than the first parameter. Second parameter\n * must be a power-of-two value.\n * This function is the same as RTE_PTR_ALIGN_CEIL\n */\n#define RTE_PTR_ALIGN(ptr, align) RTE_PTR_ALIGN_CEIL(ptr, align)\n\n/**\n * Macro to align a value to a given power-of-two. The resultant\n * value will be of the same type as the first parameter, and\n * will be no lower than the first parameter. Second parameter\n * must be a power-of-two value.\n * This function is the same as RTE_ALIGN_CEIL\n */\n#define RTE_ALIGN(val, align) RTE_ALIGN_CEIL(val, align)\n\n/**\n * Checks if a pointer is aligned to a given power-of-two value\n *\n * @param ptr\n * The pointer whose alignment is to be checked\n * @param align\n * The power-of-two value to which the ptr should be aligned\n *\n * @return\n * True(1) where the pointer is correctly aligned, false(0) otherwise\n */\nstatic inline int\nrte_is_aligned(void *ptr, unsigned align)\n{\n\treturn RTE_PTR_ALIGN(ptr, align) == ptr;\n}\n\n/*********** Macros for compile type checks ********/\n\n/**\n * Triggers an error at compilation time if the condition is true.\n */\n#ifndef __OPTIMIZE__\n#define RTE_BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))\n#else\nextern int RTE_BUILD_BUG_ON_detected_error;\n#define RTE_BUILD_BUG_ON(condition) do { \\\n\t((void)sizeof(char[1 - 2*!!(condition)])); \\\n\tif (condition) \\\n\t\tRTE_BUILD_BUG_ON_detected_error = 1; \\\n} while(0)\n#endif\n\n/*********** Macros to work with powers of 2 ********/\n\n/**\n * Returns true if n is a power of 2\n * @param n\n * Number to check\n * @return 1 if true, 0 otherwise\n */\nstatic inline int\nrte_is_power_of_2(uint32_t n)\n{\n\treturn n && !(n & (n - 1));\n}\n\n/**\n * Aligns input parameter to the next power of 2\n *\n * @param x\n * The integer value to algin\n *\n * @return\n * Input parameter aligned to the next power of 2\n */\nstatic inline uint32_t\nrte_align32pow2(uint32_t x)\n{\n\tx--;\n\tx |= x >> 1;\n\tx |= x >> 2;\n\tx |= x >> 4;\n\tx |= x >> 8;\n\tx |= x >> 16;\n\n\treturn x + 1;\n}\n\n/**\n * Aligns 64b input parameter to the next power of 2\n *\n * @param v\n * The 64b value to align\n *\n * @return\n * Input parameter aligned to the next power of 2\n */\nstatic inline uint64_t\nrte_align64pow2(uint64_t v)\n{\n\tv--;\n\tv |= v >> 1;\n\tv |= v >> 2;\n\tv |= v >> 4;\n\tv |= v >> 8;\n\tv |= v >> 16;\n\tv |= v >> 32;\n\n\treturn v + 1;\n}\n\n/*********** Macros for calculating min and max **********/\n\n/**\n * Macro to return the minimum of two numbers\n */\n#define RTE_MIN(a, b) ({ \\\n\t\ttypeof (a) _a = (a); \\\n\t\ttypeof (b) _b = (b); \\\n\t\t_a < _b ? _a : _b; \\\n\t})\n\n/**\n * Macro to return the maximum of two numbers\n */\n#define RTE_MAX(a, b) ({ \\\n\t\ttypeof (a) _a = (a); \\\n\t\ttypeof (b) _b = (b); \\\n\t\t_a > _b ? _a : _b; \\\n\t})\n\n/*********** Other general functions / macros ********/\n\n#ifdef __SSE2__\n#include \n/**\n * PAUSE instruction for tight loops (avoid busy waiting)\n */\nstatic inline void\nrte_pause (void)\n{\n\t_mm_pause();\n}\n#else\nstatic inline void\nrte_pause(void) {}\n#endif\n\n/**\n * Searches the input parameter for the least significant set bit\n * (starting from zero).\n * If a least significant 1 bit is found, its bit index is returned.\n * If the content of the input parameter is zero, then the content of the return\n * value is undefined.\n * @param v\n * input parameter, should not be zero.\n * @return\n * least significant set bit in the input parameter.\n */\nstatic inline uint32_t\nrte_bsf32(uint32_t v)\n{\n\treturn __builtin_ctz(v);\n}\n\n#ifndef offsetof\n/** Return the offset of a field in a structure. */\n#define offsetof(TYPE, MEMBER) __builtin_offsetof (TYPE, MEMBER)\n#endif\n\n#define _RTE_STR(x) #x\n/** Take a macro value and get a string version of it */\n#define RTE_STR(x) _RTE_STR(x)\n\n/** Mask value of type \"tp\" for the first \"ln\" bit set. */\n#define\tRTE_LEN2MASK(ln, tp)\t\\\n\t((tp)((uint64_t)-1 >> (sizeof(uint64_t) * CHAR_BIT - (ln))))\n\n/** Number of elements in the array. */\n#define\tRTE_DIM(a)\t(sizeof (a) / sizeof ((a)[0]))\n\n/**\n * Converts a numeric string to the equivalent uint64_t value.\n * As well as straight number conversion, also recognises the suffixes\n * k, m and g for kilobytes, megabytes and gigabytes respectively.\n *\n * If a negative number is passed in i.e. a string with the first non-black\n * character being \"-\", zero is returned. Zero is also returned in the case of\n * an error with the strtoull call in the function.\n *\n * @param str\n * String containing number to convert.\n * @return\n * Number.\n */\nstatic inline uint64_t\nrte_str_to_size(const char *str)\n{\n\tchar *endptr;\n\tunsigned long long size;\n\n\twhile (isspace((int)*str))\n\t\tstr++;\n\tif (*str == '-')\n\t\treturn 0;\n\n\terrno = 0;\n\tsize = strtoull(str, &endptr, 0);\n\tif (errno)\n\t\treturn 0;\n\n\tif (*endptr == ' ')\n\t\tendptr++; /* allow 1 space gap */\n\n\tswitch (*endptr){\n\tcase 'G': case 'g': size *= 1024; /* fall-through */\n\tcase 'M': case 'm': size *= 1024; /* fall-through */\n\tcase 'K': case 'k': size *= 1024; /* fall-through */\n\tdefault:\n\t\tbreak;\n\t}\n\treturn size;\n}\n\n/**\n * Function to terminate the application immediately, printing an error\n * message and returning the exit_code back to the shell.\n *\n * This function never returns\n *\n * @param exit_code\n * The exit code to be returned by the application\n * @param format\n * The format string to be used for printing the message. This can include\n * printf format characters which will be expanded using any further parameters\n * to the function.\n */\nvoid\nrte_exit(int exit_code, const char *format, ...)\n\t__attribute__((noreturn))\n\t__attribute__((format(printf, 2, 3)));\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_eal/common/include/rte_debug.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_DEBUG_H_\n#define _RTE_DEBUG_H_\n\n/**\n * @file\n *\n * Debug Functions in RTE\n *\n * This file defines a generic API for debug operations. Part of\n * the implementation is architecture-specific.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Dump the stack of the calling core to the console.\n */\nvoid rte_dump_stack(void);\n\n/**\n * Dump the registers of the calling core to the console.\n *\n * Note: Not implemented in a userapp environment; use gdb instead.\n */\nvoid rte_dump_registers(void);\n\n/**\n * Provide notification of a critical non-recoverable error and terminate\n * execution abnormally.\n *\n * Display the format string and its expanded arguments (printf-like).\n *\n * In a linuxapp environment, this function dumps the stack and calls\n * abort() resulting in a core dump if enabled.\n *\n * The function never returns.\n *\n * @param ...\n * The format string, followed by the variable list of arguments.\n */\n#define rte_panic(...) rte_panic_(__func__, __VA_ARGS__, \"dummy\")\n#define rte_panic_(func, format, ...) __rte_panic(func, format \"%.0s\", __VA_ARGS__)\n\n#define\tRTE_VERIFY(exp)\tdo { \\\n\tif (!(exp)) \\\n\t\trte_panic(\"line %d\\tassert \\\"\" #exp \"\\\" failed\\n\", __LINE__); \\\n} while (0)\n\n/*\n * Provide notification of a critical non-recoverable error and stop.\n *\n * This function should not be called directly. Refer to rte_panic() macro\n * documentation.\n */\nvoid __rte_panic(const char *funcname , const char *format, ...)\n#ifdef __GNUC__\n#if (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 2))\n\t__attribute__((cold))\n#endif\n#endif\n\t__attribute__((noreturn))\n\t__attribute__((format(printf, 2, 3)));\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_DEBUG_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_dev.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_DEV_H_\n#define _RTE_DEV_H_\n\n/**\n * @file\n *\n * RTE PMD Driver Registration Interface\n *\n * This file manages the list of device drivers.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n/** Double linked list of device drivers. */\nTAILQ_HEAD(rte_driver_list, rte_driver);\n\n/**\n * Initialization function called for each device driver once.\n */\ntypedef int (rte_dev_init_t)(const char *name, const char *args);\n\n/**\n * Uninitilization function called for each device driver once.\n */\ntypedef int (rte_dev_uninit_t)(const char *name);\n\n/**\n * Driver type enumeration\n */\nenum pmd_type {\n\tPMD_VDEV = 0,\n\tPMD_PDEV = 1,\n};\n\n/**\n * A structure describing a device driver.\n */\nstruct rte_driver {\n\tTAILQ_ENTRY(rte_driver) next; /**< Next in list. */\n\tenum pmd_type type;\t\t /**< PMD Driver type */\n\tconst char *name; /**< Driver name. */\n\trte_dev_init_t *init; /**< Device init. function. */\n\trte_dev_uninit_t *uninit; /**< Device uninit. function. */\n};\n\n/**\n * Register a device driver.\n *\n * @param driver\n * A pointer to a rte_dev structure describing the driver\n * to be registered.\n */\nvoid rte_eal_driver_register(struct rte_driver *driver);\n\n/**\n * Unregister a device driver.\n *\n * @param driver\n * A pointer to a rte_dev structure describing the driver\n * to be unregistered.\n */\nvoid rte_eal_driver_unregister(struct rte_driver *driver);\n\n/**\n * Initalize all the registered drivers in this process\n */\nint rte_eal_dev_init(void);\n\n/**\n * Initialize a driver specified by name.\n *\n * @param name\n * The pointer to a driver name to be initialized.\n * @param args\n * The pointer to arguments used by driver initialization.\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_vdev_init(const char *name, const char *args);\n\n/**\n * Uninitalize a driver specified by name.\n *\n * @param name\n * The pointer to a driver name to be initialized.\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_vdev_uninit(const char *name);\n\n#define PMD_REGISTER_DRIVER(d)\\\nvoid devinitfn_ ##d(void);\\\nvoid __attribute__((constructor, used)) devinitfn_ ##d(void)\\\n{\\\n\trte_eal_driver_register(&d);\\\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_VDEV_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_devargs.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright 2014 6WIND S.A.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A nor the names of its contributors\n * may be used to endorse or promote products derived from this\n * software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_DEVARGS_H_\n#define _RTE_DEVARGS_H_\n\n/**\n * @file\n *\n * RTE devargs: list of devices and their user arguments\n *\n * This file stores a list of devices and their arguments given by\n * the user when a DPDK application is started. These devices can be PCI\n * devices or virtual devices. These devices are stored at startup in a\n * list of rte_devargs structures.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n#include \n\n/**\n * Type of generic device\n */\nenum rte_devtype {\n\tRTE_DEVTYPE_WHITELISTED_PCI,\n\tRTE_DEVTYPE_BLACKLISTED_PCI,\n\tRTE_DEVTYPE_VIRTUAL,\n};\n\n/**\n * Structure that stores a device given by the user with its arguments\n *\n * A user device is a physical or a virtual device given by the user to\n * the DPDK application at startup through command line arguments.\n *\n * The structure stores the configuration of the device, its PCI\n * identifier if it's a PCI device or the driver name if it's a virtual\n * device.\n */\nstruct rte_devargs {\n\t/** Next in list. */\n\tTAILQ_ENTRY(rte_devargs) next;\n\t/** Type of device. */\n\tenum rte_devtype type;\n\tunion {\n\t\t/** Used if type is RTE_DEVTYPE_*_PCI. */\n\t\tstruct {\n\t\t\t/** PCI location. */\n\t\t\tstruct rte_pci_addr addr;\n\t\t} pci;\n\t\t/** Used if type is RTE_DEVTYPE_VIRTUAL. */\n\t\tstruct {\n\t\t\t/** Driver name. */\n\t\t\tchar drv_name[32];\n\t\t} virtual;\n\t};\n\t/** Arguments string as given by user or \"\" for no argument. */\n\tchar *args;\n};\n\n/** user device double-linked queue type definition */\nTAILQ_HEAD(rte_devargs_list, rte_devargs);\n\n/** Global list of user devices */\nextern struct rte_devargs_list devargs_list;\n\n/**\n * Parse a devargs string.\n *\n * For PCI devices, the format of arguments string is \"PCI_ADDR\" or\n * \"PCI_ADDR,key=val,key2=val2,...\". Examples: \"08:00.1\", \"0000:5:00.0\",\n * \"04:00.0,arg=val\".\n *\n * For virtual devices, the format of arguments string is \"DRIVER_NAME*\"\n * or \"DRIVER_NAME*,key=val,key2=val2,...\". Examples: \"eth_ring\",\n * \"eth_ring0\", \"eth_pmdAnything,arg=0:arg2=1\".\n *\n * The function parses the arguments string to get driver name and driver\n * arguments.\n *\n * @param devargs_str\n * The arguments as given by the user.\n * @param drvname\n * The pointer to the string to store parsed driver name.\n * @param drvargs\n * The pointer to the string to store parsed driver arguments.\n *\n * @return\n * - 0 on success\n * - A negative value on error\n */\nint rte_eal_parse_devargs_str(const char *devargs_str,\n\t\t\t\tchar **drvname, char **drvargs);\n\n/**\n * Add a device to the user device list\n *\n * For PCI devices, the format of arguments string is \"PCI_ADDR\" or\n * \"PCI_ADDR,key=val,key2=val2,...\". Examples: \"08:00.1\", \"0000:5:00.0\",\n * \"04:00.0,arg=val\".\n *\n * For virtual devices, the format of arguments string is \"DRIVER_NAME*\"\n * or \"DRIVER_NAME*,key=val,key2=val2,...\". Examples: \"eth_ring\",\n * \"eth_ring0\", \"eth_pmdAnything,arg=0:arg2=1\". The validity of the\n * driver name is not checked by this function, it is done when probing\n * the drivers.\n *\n * @param devtype\n * The type of the device.\n * @param devargs_str\n * The arguments as given by the user.\n *\n * @return\n * - 0 on success\n * - A negative value on error\n */\nint rte_eal_devargs_add(enum rte_devtype devtype, const char *devargs_str);\n\n/**\n * Count the number of user devices of a specified type\n *\n * @param devtype\n * The type of the devices to counted.\n *\n * @return\n * The number of devices.\n */\nunsigned int\nrte_eal_devargs_type_count(enum rte_devtype devtype);\n\n/**\n * This function dumps the list of user device and their arguments.\n *\n * @param f\n * A pointer to a file for output\n */\nvoid rte_eal_devargs_dump(FILE *f);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_DEVARGS_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_eal.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_EAL_H_\n#define _RTE_EAL_H_\n\n/**\n * @file\n *\n * EAL Configuration API\n */\n\n#include \n#include \n\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define RTE_MAGIC 19820526 /**< Magic number written by the main partition when ready. */\n\n/**\n * The lcore role (used in RTE or not).\n */\nenum rte_lcore_role_t {\n\tROLE_RTE,\n\tROLE_OFF,\n};\n\n/**\n * The type of process in a linuxapp, multi-process setup\n */\nenum rte_proc_type_t {\n\tRTE_PROC_AUTO = -1, /* allow auto-detection of primary/secondary */\n\tRTE_PROC_PRIMARY = 0, /* set to zero, so primary is the default */\n\tRTE_PROC_SECONDARY,\n\n\tRTE_PROC_INVALID\n};\n\n/**\n * The global RTE configuration structure.\n */\nstruct rte_config {\n\tuint32_t master_lcore; /**< Id of the master lcore */\n\tuint32_t lcore_count; /**< Number of available logical cores. */\n\tenum rte_lcore_role_t lcore_role[RTE_MAX_LCORE]; /**< State of cores. */\n\n\t/** Primary or secondary configuration */\n\tenum rte_proc_type_t process_type;\n\n\t/**\n\t * Pointer to memory configuration, which may be shared across multiple\n\t * Intel DPDK instances\n\t */\n\tstruct rte_mem_config *mem_config;\n} __attribute__((__packed__));\n\n/**\n * Get the global configuration structure.\n *\n * @return\n * A pointer to the global configuration structure.\n */\nstruct rte_config *rte_eal_get_configuration(void);\n\n/**\n * Get a lcore's role.\n *\n * @param lcore_id\n * The identifier of the lcore.\n * @return\n * The role of the lcore.\n */\nenum rte_lcore_role_t rte_eal_lcore_role(unsigned lcore_id);\n\n\n/**\n * Get the process type in a multi-process setup\n *\n * @return\n * The process type\n */\nenum rte_proc_type_t rte_eal_process_type(void);\n\n/**\n * Request iopl privilege for all RPL.\n *\n * This function should be called by pmds which need access to ioports.\n\n * @return\n * - On success, returns 0.\n * - On failure, returns -1.\n */\nint rte_eal_iopl_init(void);\n\n/**\n * Initialize the Environment Abstraction Layer (EAL).\n *\n * This function is to be executed on the MASTER lcore only, as soon\n * as possible in the application's main() function.\n *\n * The function finishes the initialization process before main() is called.\n * It puts the SLAVE lcores in the WAIT state.\n *\n * When the multi-partition feature is supported, depending on the\n * configuration (if CONFIG_RTE_EAL_MAIN_PARTITION is disabled), this\n * function waits to ensure that the magic number is set before\n * returning. See also the rte_eal_get_configuration() function. Note:\n * This behavior may change in the future.\n *\n * @param argc\n * The argc argument that was given to the main() function.\n * @param argv\n * The argv argument that was given to the main() function.\n * @return\n * - On success, the number of parsed arguments, which is greater or\n * equal to zero. After the call to rte_eal_init(),\n * all arguments argv[x] with x < ret may be modified and should\n * not be accessed by the application.\n * - On failure, a negative error value.\n */\nint rte_eal_init(int argc, char **argv);\n/**\n * Usage function typedef used by the application usage function.\n *\n * Use this function typedef to define and call rte_set_applcation_usage_hook()\n * routine.\n */\ntypedef void\t(*rte_usage_hook_t)(const char * prgname);\n\n/**\n * Add application usage routine callout from the eal_usage() routine.\n *\n * This function allows the application to include its usage message\n * in the EAL system usage message. The routine rte_set_application_usage_hook()\n * needs to be called before the rte_eal_init() routine in the application.\n *\n * This routine is optional for the application and will behave as if the set\n * routine was never called as the default behavior.\n *\n * @param usage_func\n * The func argument is a function pointer to the application usage routine.\n * Called function is defined using rte_usage_hook_t typedef, which is of\n * the form void rte_usage_func(const char * prgname).\n *\n * Calling this routine with a NULL value will reset the usage hook routine and\n * return the current value, which could be NULL.\n * @return\n * - Returns the current value of the rte_application_usage pointer to allow\n * the caller to daisy chain the usage routines if needing more then one.\n */\nrte_usage_hook_t\nrte_set_application_usage_hook(rte_usage_hook_t usage_func);\n\n/**\n * macro to get the lock of tailq in mem_config\n */\n#define RTE_EAL_TAILQ_RWLOCK (&rte_eal_get_configuration()->mem_config->qlock)\n\n/**\n * macro to get the multiple lock of mempool shared by mutiple-instance\n */\n#define RTE_EAL_MEMPOOL_RWLOCK (&rte_eal_get_configuration()->mem_config->mplock)\n\n/**\n * Whether EAL is using huge pages (disabled by --no-huge option).\n * The no-huge mode cannot be used with UIO poll-mode drivers like igb/ixgbe.\n * It is useful for NIC drivers (e.g. librte_pmd_mlx4, librte_pmd_vmxnet3) or\n * crypto drivers (e.g. librte_crypto_nitrox) provided by third-parties such\n * as 6WIND.\n *\n * @return\n * Nonzero if hugepages are enabled.\n */\nint rte_eal_has_hugepages(void);\n\n/**\n * A wrap API for syscall gettid.\n *\n * @return\n * On success, returns the thread ID of calling process.\n * It is always successful.\n */\nint rte_sys_gettid(void);\n\n/**\n * Get system unique thread id.\n *\n * @return\n * On success, returns the thread ID of calling process.\n * It is always successful.\n */\nstatic inline int rte_gettid(void)\n{\n\tstatic RTE_DEFINE_PER_LCORE(int, _thread_id) = -1;\n\tif (RTE_PER_LCORE(_thread_id) == -1)\n\t\tRTE_PER_LCORE(_thread_id) = rte_sys_gettid();\n\treturn RTE_PER_LCORE(_thread_id);\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_EAL_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_eal_memconfig.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_EAL_MEMCONFIG_H_\n#define _RTE_EAL_MEMCONFIG_H_\n\n#include \n#include \n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * the structure for the memory configuration for the RTE.\n * Used by the rte_config structure. It is separated out, as for multi-process\n * support, the memory details should be shared across instances\n */\nstruct rte_mem_config {\n\tvolatile uint32_t magic; /**< Magic number - Sanity check. */\n\n\t/* memory topology */\n\tuint32_t nchannel; /**< Number of channels (0 if unknown). */\n\tuint32_t nrank; /**< Number of ranks (0 if unknown). */\n\n\t/**\n\t * current lock nest order\n\t * - qlock->mlock (ring/hash/lpm)\n\t * - mplock->qlock->mlock (mempool)\n\t * Notice:\n\t * *ALWAYS* obtain qlock first if having to obtain both qlock and mlock\n\t */\n\trte_rwlock_t mlock; /**< only used by memzone LIB for thread-safe. */\n\trte_rwlock_t qlock; /**< used for tailq operation for thread safe. */\n\trte_rwlock_t mplock; /**< only used by mempool LIB for thread-safe. */\n\n\tuint32_t memzone_cnt; /**< Number of allocated memzones */\n\n\t/* memory segments and zones */\n\tstruct rte_memseg memseg[RTE_MAX_MEMSEG]; /**< Physmem descriptors. */\n\tstruct rte_memzone memzone[RTE_MAX_MEMZONE]; /**< Memzone descriptors. */\n\n\tstruct rte_tailq_head tailq_head[RTE_MAX_TAILQ]; /**< Tailqs for objects */\n\n\t/* Heaps of Malloc per socket */\n\tstruct malloc_heap malloc_heaps[RTE_MAX_NUMA_NODES];\n\n\t/* address of mem_config in primary process. used to map shared config into\n\t * exact same address the primary process maps it.\n\t */\n\tuint64_t mem_cfg_addr;\n} __attribute__((__packed__));\n\n\ninline static void\nrte_eal_mcfg_wait_complete(struct rte_mem_config* mcfg)\n{\n\t/* wait until shared mem_config finish initialising */\n\twhile(mcfg->magic != RTE_MAGIC)\n\t\trte_pause();\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__RTE_EAL_MEMCONFIG_H_*/\n" }, { "path": "lib/librte_eal/common/include/rte_errno.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/**\n * @file\n *\n * API for error cause tracking\n */\n\n#ifndef _RTE_ERRNO_H_\n#define _RTE_ERRNO_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\nRTE_DECLARE_PER_LCORE(int, _rte_errno); /**< Per core error number. */\n\n/**\n * Error number value, stored per-thread, which can be queried after\n * calls to certain functions to determine why those functions failed.\n *\n * Uses standard values from errno.h wherever possible, with a small number\n * of additional possible values for RTE-specific conditions.\n */\n#define rte_errno RTE_PER_LCORE(_rte_errno)\n\n/**\n * Function which returns a printable string describing a particular\n * error code. For non-RTE-specific error codes, this function returns\n * the value from the libc strerror function.\n *\n * @param errnum\n * The error number to be looked up - generally the value of rte_errno\n * @return\n * A pointer to a thread-local string containing the text describing\n * the error.\n */\nconst char *rte_strerror(int errnum);\n\n#ifndef __ELASTERROR\n/**\n * Check if we have a defined value for the max system-defined errno values.\n * if no max defined, start from 1000 to prevent overlap with standard values\n */\n#define __ELASTERROR 1000\n#endif\n\n/** Error types */\nenum {\n\tRTE_MIN_ERRNO = __ELASTERROR, /**< Start numbering above std errno vals */\n\n\tE_RTE_SECONDARY, /**< Operation not allowed in secondary processes */\n\tE_RTE_NO_CONFIG, /**< Missing rte_config */\n\n\tRTE_MAX_ERRNO /**< Max RTE error number */\n};\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_ERRNO_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_hexdump.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_HEXDUMP_H_\n#define _RTE_HEXDUMP_H_\n\n/**\n * @file\n * Simple API to dump out memory in a special hex format.\n */\n\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n* Dump out memory in a special hex dump format.\n*\n* @param f\n*\t\tA pointer to a file for output\n* @param title\n*\t\tIf not NULL this string is printed as a header to the output.\n* @param buf\n*\t\tThis is the buffer address to print out.\n* @param len\n*\t\tThe number of bytes to dump out\n* @return\n*\t\tNone.\n*/\n\nextern void\nrte_hexdump(FILE *f, const char * title, const void * buf, unsigned int len);\n\n/**\n* Dump out memory in a hex format with colons between bytes.\n*\n* @param f\n*\t\tA pointer to a file for output\n* @param title\n*\t\tIf not NULL this string is printed as a header to the output.\n* @param buf\n*\t\tThis is the buffer address to print out.\n* @param len\n*\t\tThe number of bytes to dump out\n* @return\n*\t\tNone.\n*/\n\nvoid\nrte_memdump(FILE *f, const char * title, const void * buf, unsigned int len);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_HEXDUMP_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_interrupts.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_INTERRUPTS_H_\n#define _RTE_INTERRUPTS_H_\n\n/**\n * @file\n *\n * The RTE interrupt interface provides functions to register/unregister\n * callbacks for a specific interrupt.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/** Interrupt handle */\nstruct rte_intr_handle;\n\n/** Function to be registered for the specific interrupt */\ntypedef void (*rte_intr_callback_fn)(struct rte_intr_handle *intr_handle,\n\t\t\t\t\t\t\tvoid *cb_arg);\n\n#include \n\n/**\n * It registers the callback for the specific interrupt. Multiple\n * callbacks cal be registered at the same time.\n * @param intr_handle\n * Pointer to the interrupt handle.\n * @param cb\n * callback address.\n * @param cb_arg\n * address of parameter for callback.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nint rte_intr_callback_register(struct rte_intr_handle *intr_handle,\n\t\t\t\trte_intr_callback_fn cb, void *cb_arg);\n\n/**\n * It unregisters the callback according to the specified interrupt handle.\n *\n * @param intr_handle\n * pointer to the interrupt handle.\n * @param cb\n * callback address.\n * @param cb_arg\n * address of parameter for callback, (void *)-1 means to remove all\n * registered which has the same callback address.\n *\n * @return\n * - On success, return the number of callback entities removed.\n * - On failure, a negative value.\n */\nint rte_intr_callback_unregister(struct rte_intr_handle *intr_handle,\n\t\t\t\trte_intr_callback_fn cb, void *cb_arg);\n\n/**\n * It enables the interrupt for the specified handle.\n *\n * @param intr_handle\n * pointer to the interrupt handle.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nint rte_intr_enable(struct rte_intr_handle *intr_handle);\n\n/**\n * It disables the interrupt for the specified handle.\n *\n * @param intr_handle\n * pointer to the interrupt handle.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nint rte_intr_disable(struct rte_intr_handle *intr_handle);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_eal/common/include/rte_launch.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_LAUNCH_H_\n#define _RTE_LAUNCH_H_\n\n/**\n * @file\n *\n * Launch tasks on other lcores\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * State of an lcore.\n */\nenum rte_lcore_state_t {\n\tWAIT, /**< waiting a new command */\n\tRUNNING, /**< executing command */\n\tFINISHED, /**< command executed */\n};\n\n/**\n * Definition of a remote launch function.\n */\ntypedef int (lcore_function_t)(void *);\n\n/**\n * Launch a function on another lcore.\n *\n * To be executed on the MASTER lcore only.\n *\n * Sends a message to a slave lcore (identified by the slave_id) that\n * is in the WAIT state (this is true after the first call to\n * rte_eal_init()). This can be checked by first calling\n * rte_eal_wait_lcore(slave_id).\n *\n * When the remote lcore receives the message, it switches to\n * the RUNNING state, then calls the function f with argument arg. Once the\n * execution is done, the remote lcore switches to a FINISHED state and\n * the return value of f is stored in a local variable to be read using\n * rte_eal_wait_lcore().\n *\n * The MASTER lcore returns as soon as the message is sent and knows\n * nothing about the completion of f.\n *\n * Note: This function is not designed to offer optimum\n * performance. It is just a practical way to launch a function on\n * another lcore at initialization time.\n *\n * @param f\n * The function to be called.\n * @param arg\n * The argument for the function.\n * @param slave_id\n * The identifier of the lcore on which the function should be executed.\n * @return\n * - 0: Success. Execution of function f started on the remote lcore.\n * - (-EBUSY): The remote lcore is not in a WAIT state.\n */\nint rte_eal_remote_launch(lcore_function_t *f, void *arg, unsigned slave_id);\n\n/**\n * This enum indicates whether the master core must execute the handler\n * launched on all logical cores.\n */\nenum rte_rmt_call_master_t {\n\tSKIP_MASTER = 0, /**< lcore handler not executed by master core. */\n\tCALL_MASTER, /**< lcore handler executed by master core. */\n};\n\n/**\n * Launch a function on all lcores.\n *\n * Check that each SLAVE lcore is in a WAIT state, then call\n * rte_eal_remote_launch() for each lcore.\n *\n * @param f\n * The function to be called.\n * @param arg\n * The argument for the function.\n * @param call_master\n * If call_master set to SKIP_MASTER, the MASTER lcore does not call\n * the function. If call_master is set to CALL_MASTER, the function\n * is also called on master before returning. In any case, the master\n * lcore returns as soon as it finished its job and knows nothing\n * about the completion of f on the other lcores.\n * @return\n * - 0: Success. Execution of function f started on all remote lcores.\n * - (-EBUSY): At least one remote lcore is not in a WAIT state. In this\n * case, no message is sent to any of the lcores.\n */\nint rte_eal_mp_remote_launch(lcore_function_t *f, void *arg,\n\t\t\t enum rte_rmt_call_master_t call_master);\n\n/**\n * Get the state of the lcore identified by slave_id.\n *\n * To be executed on the MASTER lcore only.\n *\n * @param slave_id\n * The identifier of the lcore.\n * @return\n * The state of the lcore.\n */\nenum rte_lcore_state_t rte_eal_get_lcore_state(unsigned slave_id);\n\n/**\n * Wait until an lcore finishes its job.\n *\n * To be executed on the MASTER lcore only.\n *\n * If the slave lcore identified by the slave_id is in a FINISHED state,\n * switch to the WAIT state. If the lcore is in RUNNING state, wait until\n * the lcore finishes its job and moves to the FINISHED state.\n *\n * @param slave_id\n * The identifier of the lcore.\n * @return\n * - 0: If the lcore identified by the slave_id is in a WAIT state.\n * - The value that was returned by the previous remote launch\n * function call if the lcore identified by the slave_id was in a\n * FINISHED or RUNNING state. In this case, it changes the state\n * of the lcore to WAIT.\n */\nint rte_eal_wait_lcore(unsigned slave_id);\n\n/**\n * Wait until all lcores finish their jobs.\n *\n * To be executed on the MASTER lcore only. Issue an\n * rte_eal_wait_lcore() for every lcore. The return values are\n * ignored.\n *\n * After a call to rte_eal_mp_wait_lcore(), the caller can assume\n * that all slave lcores are in a WAIT state.\n */\nvoid rte_eal_mp_wait_lcore(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_LAUNCH_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_lcore.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_LCORE_H_\n#define _RTE_LCORE_H_\n\n/**\n * @file\n *\n * API for lcore and socket manipulation\n *\n */\n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define LCORE_ID_ANY UINT32_MAX /**< Any lcore. */\n\n#if defined(__linux__)\n\ttypedef\tcpu_set_t rte_cpuset_t;\n#elif defined(__FreeBSD__)\n#include \n\ttypedef cpuset_t rte_cpuset_t;\n#endif\n\n/**\n * Structure storing internal configuration (per-lcore)\n */\nstruct lcore_config {\n\tunsigned detected; /**< true if lcore was detected */\n\tpthread_t thread_id; /**< pthread identifier */\n\tint pipe_master2slave[2]; /**< communication pipe with master */\n\tint pipe_slave2master[2]; /**< communication pipe with master */\n\tlcore_function_t * volatile f; /**< function to call */\n\tvoid * volatile arg; /**< argument of function */\n\tvolatile int ret; /**< return value of function */\n\tvolatile enum rte_lcore_state_t state; /**< lcore state */\n\tunsigned socket_id; /**< physical socket id for this lcore */\n\tunsigned core_id; /**< core number on socket for this lcore */\n\tint core_index; /**< relative index, starting from 0 */\n\trte_cpuset_t cpuset; /**< cpu set which the lcore affinity to */\n};\n\n/**\n * Internal configuration (per-lcore)\n */\nextern struct lcore_config lcore_config[RTE_MAX_LCORE];\n\nRTE_DECLARE_PER_LCORE(unsigned, _lcore_id); /**< Per thread \"lcore id\". */\nRTE_DECLARE_PER_LCORE(rte_cpuset_t, _cpuset); /**< Per thread \"cpuset\". */\n\n/**\n * Return the ID of the execution unit we are running on.\n * @return\n * Logical core ID (in EAL thread) or LCORE_ID_ANY (in non-EAL thread)\n */\nstatic inline unsigned\nrte_lcore_id(void)\n{\n\treturn RTE_PER_LCORE(_lcore_id);\n}\n\n/**\n * Get the id of the master lcore\n *\n * @return\n * the id of the master lcore\n */\nstatic inline unsigned\nrte_get_master_lcore(void)\n{\n\treturn rte_eal_get_configuration()->master_lcore;\n}\n\n/**\n * Return the number of execution units (lcores) on the system.\n *\n * @return\n * the number of execution units (lcores) on the system.\n */\nstatic inline unsigned\nrte_lcore_count(void)\n{\n\tconst struct rte_config *cfg = rte_eal_get_configuration();\n\treturn cfg->lcore_count;\n}\n\n/**\n * Return the index of the lcore starting from zero.\n * The order is physical or given by command line (-l option).\n *\n * @param lcore_id\n * The targeted lcore, or -1 for the current one.\n * @return\n * The relative index, or -1 if not enabled.\n */\nstatic inline int\nrte_lcore_index(int lcore_id)\n{\n\tif (lcore_id >= RTE_MAX_LCORE)\n\t\treturn -1;\n\tif (lcore_id < 0)\n\t\tlcore_id = rte_lcore_id();\n\treturn lcore_config[lcore_id].core_index;\n}\n\n/**\n * Return the ID of the physical socket of the logical core we are\n * running on.\n * @return\n * the ID of current lcoreid's physical socket\n */\nunsigned rte_socket_id(void);\n\n/**\n * Get the ID of the physical socket of the specified lcore\n *\n * @param lcore_id\n * the targeted lcore, which MUST be between 0 and RTE_MAX_LCORE-1.\n * @return\n * the ID of lcoreid's physical socket\n */\nstatic inline unsigned\nrte_lcore_to_socket_id(unsigned lcore_id)\n{\n\treturn lcore_config[lcore_id].socket_id;\n}\n\n/**\n * Test if an lcore is enabled.\n *\n * @param lcore_id\n * The identifier of the lcore, which MUST be between 0 and\n * RTE_MAX_LCORE-1.\n * @return\n * True if the given lcore is enabled; false otherwise.\n */\nstatic inline int\nrte_lcore_is_enabled(unsigned lcore_id)\n{\n\tstruct rte_config *cfg = rte_eal_get_configuration();\n\tif (lcore_id >= RTE_MAX_LCORE)\n\t\treturn 0;\n\treturn (cfg->lcore_role[lcore_id] != ROLE_OFF);\n}\n\n/**\n * Get the next enabled lcore ID.\n *\n * @param i\n * The current lcore (reference).\n * @param skip_master\n * If true, do not return the ID of the master lcore.\n * @param wrap\n * If true, go back to 0 when RTE_MAX_LCORE is reached; otherwise,\n * return RTE_MAX_LCORE.\n * @return\n * The next lcore_id or RTE_MAX_LCORE if not found.\n */\nstatic inline unsigned\nrte_get_next_lcore(unsigned i, int skip_master, int wrap)\n{\n\ti++;\n\tif (wrap)\n\t\ti %= RTE_MAX_LCORE;\n\n\twhile (i < RTE_MAX_LCORE) {\n\t\tif (!rte_lcore_is_enabled(i) ||\n\t\t (skip_master && (i == rte_get_master_lcore()))) {\n\t\t\ti++;\n\t\t\tif (wrap)\n\t\t\t\ti %= RTE_MAX_LCORE;\n\t\t\tcontinue;\n\t\t}\n\t\tbreak;\n\t}\n\treturn i;\n}\n/**\n * Macro to browse all running lcores.\n */\n#define RTE_LCORE_FOREACH(i)\t\t\t\t\t\t\\\n\tfor (i = rte_get_next_lcore(-1, 0, 0);\t\t\t\t\\\n\t i\n#include \n#include \n\n/** The rte_log structure. */\nstruct rte_logs {\n\tuint32_t type; /**< Bitfield with enabled logs. */\n\tuint32_t level; /**< Log level. */\n\tFILE *file; /**< Pointer to current FILE* for logs. */\n};\n\n/** Global log informations */\nextern struct rte_logs rte_logs;\n\n/* SDK log type */\n#define RTE_LOGTYPE_EAL 0x00000001 /**< Log related to eal. */\n#define RTE_LOGTYPE_MALLOC 0x00000002 /**< Log related to malloc. */\n#define RTE_LOGTYPE_RING 0x00000004 /**< Log related to ring. */\n#define RTE_LOGTYPE_MEMPOOL 0x00000008 /**< Log related to mempool. */\n#define RTE_LOGTYPE_TIMER 0x00000010 /**< Log related to timers. */\n#define RTE_LOGTYPE_PMD 0x00000020 /**< Log related to poll mode driver. */\n#define RTE_LOGTYPE_HASH 0x00000040 /**< Log related to hash table. */\n#define RTE_LOGTYPE_LPM 0x00000080 /**< Log related to LPM. */\n#define RTE_LOGTYPE_KNI 0x00000100 /**< Log related to KNI. */\n#define RTE_LOGTYPE_ACL 0x00000200 /**< Log related to ACL. */\n#define RTE_LOGTYPE_POWER 0x00000400 /**< Log related to power. */\n#define RTE_LOGTYPE_METER 0x00000800 /**< Log related to QoS meter. */\n#define RTE_LOGTYPE_SCHED 0x00001000 /**< Log related to QoS port scheduler. */\n#define RTE_LOGTYPE_PORT 0x00002000 /**< Log related to port. */\n#define RTE_LOGTYPE_TABLE 0x00004000 /**< Log related to table. */\n#define RTE_LOGTYPE_PIPELINE 0x00008000 /**< Log related to pipeline. */\n#define RTE_LOGTYPE_MBUF 0x00010000 /**< Log related to mbuf. */\n\n/* these log types can be used in an application */\n#define RTE_LOGTYPE_USER1 0x01000000 /**< User-defined log type 1. */\n#define RTE_LOGTYPE_USER2 0x02000000 /**< User-defined log type 2. */\n#define RTE_LOGTYPE_USER3 0x04000000 /**< User-defined log type 3. */\n#define RTE_LOGTYPE_USER4 0x08000000 /**< User-defined log type 4. */\n#define RTE_LOGTYPE_USER5 0x10000000 /**< User-defined log type 5. */\n#define RTE_LOGTYPE_USER6 0x20000000 /**< User-defined log type 6. */\n#define RTE_LOGTYPE_USER7 0x40000000 /**< User-defined log type 7. */\n#define RTE_LOGTYPE_USER8 0x80000000 /**< User-defined log type 8. */\n\n/* Can't use 0, as it gives compiler warnings */\n#define RTE_LOG_EMERG 1U /**< System is unusable. */\n#define RTE_LOG_ALERT 2U /**< Action must be taken immediately. */\n#define RTE_LOG_CRIT 3U /**< Critical conditions. */\n#define RTE_LOG_ERR 4U /**< Error conditions. */\n#define RTE_LOG_WARNING 5U /**< Warning conditions. */\n#define RTE_LOG_NOTICE 6U /**< Normal but significant condition. */\n#define RTE_LOG_INFO 7U /**< Informational. */\n#define RTE_LOG_DEBUG 8U /**< Debug-level messages. */\n\n/** The default log stream. */\nextern FILE *eal_default_log_stream;\n\n/**\n * Change the stream that will be used by the logging system.\n *\n * This can be done at any time. The f argument represents the stream\n * to be used to send the logs. If f is NULL, the default output is\n * used (stderr).\n *\n * @param f\n * Pointer to the stream.\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint rte_openlog_stream(FILE *f);\n\n/**\n * Set the global log level.\n *\n * After this call, all logs that are lower or equal than level and\n * lower or equal than the RTE_LOG_LEVEL configuration option will be\n * displayed.\n *\n * @param level\n * Log level. A value between RTE_LOG_EMERG (1) and RTE_LOG_DEBUG (8).\n */\nvoid rte_set_log_level(uint32_t level);\n\n/**\n * Get the global log level.\n */\nuint32_t rte_get_log_level(void);\n\n/**\n * Enable or disable the log type.\n *\n * @param type\n * Log type, for example, RTE_LOGTYPE_EAL.\n * @param enable\n * True for enable; false for disable.\n */\nvoid rte_set_log_type(uint32_t type, int enable);\n\n/**\n * Get the global log type.\n */\nuint32_t rte_get_log_type(void);\n\n/**\n * Get the current loglevel for the message being processed.\n *\n * Before calling the user-defined stream for logging, the log\n * subsystem sets a per-lcore variable containing the loglevel and the\n * logtype of the message being processed. This information can be\n * accessed by the user-defined log output function through this\n * function.\n *\n * @return\n * The loglevel of the message being processed.\n */\nint rte_log_cur_msg_loglevel(void);\n\n/**\n * Get the current logtype for the message being processed.\n *\n * Before calling the user-defined stream for logging, the log\n * subsystem sets a per-lcore variable containing the loglevel and the\n * logtype of the message being processed. This information can be\n * accessed by the user-defined log output function through this\n * function.\n *\n * @return\n * The logtype of the message being processed.\n */\nint rte_log_cur_msg_logtype(void);\n\n/**\n * Enable or disable the history (enabled by default)\n *\n * @param enable\n * true to enable, or 0 to disable history.\n */\nvoid rte_log_set_history(int enable);\n\n/**\n * Dump the log history to a file\n *\n * @param f\n * A pointer to a file for output\n */\nvoid rte_log_dump_history(FILE *f);\n\n/**\n * Add a log message to the history.\n *\n * This function can be called from a user-defined log stream. It adds\n * the given message in the history that can be dumped using\n * rte_log_dump_history().\n *\n * @param buf\n * A data buffer containing the message to be saved in the history.\n * @param size\n * The length of the data buffer.\n * @return\n * - 0: Success.\n * - (-ENOBUFS) if there is no room to store the message.\n */\nint rte_log_add_in_history(const char *buf, size_t size);\n\n/**\n * Generates a log message.\n *\n * The message will be sent in the stream defined by the previous call\n * to rte_openlog_stream().\n *\n * The level argument determines if the log should be displayed or\n * not, depending on the global rte_logs variable.\n *\n * The preferred alternative is the RTE_LOG() function because debug logs may\n * be removed at compilation time if optimization is enabled. Moreover,\n * logs are automatically prefixed by type when using the macro.\n *\n * @param level\n * Log level. A value between RTE_LOG_EMERG (1) and RTE_LOG_DEBUG (8).\n * @param logtype\n * The log type, for example, RTE_LOGTYPE_EAL.\n * @param format\n * The format string, as in printf(3), followed by the variable arguments\n * required by the format.\n * @return\n * - 0: Success.\n * - Negative on error.\n */\nint rte_log(uint32_t level, uint32_t logtype, const char *format, ...)\n#ifdef __GNUC__\n#if (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 2))\n\t__attribute__((cold))\n#endif\n#endif\n\t__attribute__((format(printf, 3, 4)));\n\n/**\n * Generates a log message.\n *\n * The message will be sent in the stream defined by the previous call\n * to rte_openlog_stream().\n *\n * The level argument determines if the log should be displayed or\n * not, depending on the global rte_logs variable. A trailing\n * newline may be added if needed.\n *\n * The preferred alternative is the RTE_LOG() because debug logs may be\n * removed at compilation time.\n *\n * @param level\n * Log level. A value between RTE_LOG_EMERG (1) and RTE_LOG_DEBUG (8).\n * @param logtype\n * The log type, for example, RTE_LOGTYPE_EAL.\n * @param format\n * The format string, as in printf(3), followed by the variable arguments\n * required by the format.\n * @param ap\n * The va_list of the variable arguments required by the format.\n * @return\n * - 0: Success.\n * - Negative on error.\n */\nint rte_vlog(uint32_t level, uint32_t logtype, const char *format, va_list ap)\n\t__attribute__((format(printf,3,0)));\n\n/**\n * Generates a log message.\n *\n * The RTE_LOG() is equivalent to rte_log() with two differences:\n\n * - RTE_LOG() can be used to remove debug logs at compilation time,\n * depending on RTE_LOG_LEVEL configuration option, and compilation\n * optimization level. If optimization is enabled, the tests\n * involving constants only are pre-computed. If compilation is done\n * with -O0, these tests will be done at run time.\n * - The log level and log type names are smaller, for example:\n * RTE_LOG(INFO, EAL, \"this is a %s\", \"log\");\n *\n * @param l\n * Log level. A value between EMERG (1) and DEBUG (8). The short name is\n * expanded by the macro, so it cannot be an integer value.\n * @param t\n * The log type, for example, EAL. The short name is expanded by the\n * macro, so it cannot be an integer value.\n * @param ...\n * The fmt string, as in printf(3), followed by the variable arguments\n * required by the format.\n * @return\n * - 0: Success.\n * - Negative on error.\n */\n#define RTE_LOG(l, t, ...)\t\t\t\t\t\\\n\t(void)((RTE_LOG_ ## l <= RTE_LOG_LEVEL) ?\t\t\\\n\t rte_log(RTE_LOG_ ## l,\t\t\t\t\t\\\n\t\t RTE_LOGTYPE_ ## t, # t \": \" __VA_ARGS__) :\t\\\n\t 0)\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_LOG_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_malloc.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_MALLOC_H_\n#define _RTE_MALLOC_H_\n\n/**\n * @file\n * RTE Malloc. This library provides methods for dynamically allocating memory\n * from hugepages.\n */\n\n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Structure to hold heap statistics obtained from rte_malloc_get_socket_stats function.\n */\nstruct rte_malloc_socket_stats {\n\tsize_t heap_totalsz_bytes; /**< Total bytes on heap */\n\tsize_t heap_freesz_bytes; /**< Total free bytes on heap */\n\tsize_t greatest_free_size; /**< Size in bytes of largest free block */\n\tunsigned free_count; /**< Number of free elements on heap */\n\tunsigned alloc_count; /**< Number of allocated elements on heap */\n\tsize_t heap_allocsz_bytes; /**< Total allocated bytes on heap */\n};\n\n/**\n * This function allocates memory from the huge-page area of memory. The memory\n * is not cleared. In NUMA systems, the memory allocated resides on the same\n * NUMA socket as the core that calls this function.\n *\n * @param type\n * A string identifying the type of allocated objects (useful for debug\n * purposes, such as identifying the cause of a memory leak). Can be NULL.\n * @param size\n * Size (in bytes) to be allocated.\n * @param align\n * If 0, the return is a pointer that is suitably aligned for any kind of\n * variable (in the same manner as malloc()).\n * Otherwise, the return is a pointer that is a multiple of *align*. In\n * this case, it must be a power of two. (Minimum alignment is the\n * cacheline size, i.e. 64-bytes)\n * @return\n * - NULL on error. Not enough memory, or invalid arguments (size is 0,\n * align is not a power of two).\n * - Otherwise, the pointer to the allocated object.\n */\nvoid *\nrte_malloc(const char *type, size_t size, unsigned align);\n\n/**\n * Allocate zero'ed memory from the heap.\n *\n * Equivalent to rte_malloc() except that the memory zone is\n * initialised with zeros. In NUMA systems, the memory allocated resides on the\n * same NUMA socket as the core that calls this function.\n *\n * @param type\n * A string identifying the type of allocated objects (useful for debug\n * purposes, such as identifying the cause of a memory leak). Can be NULL.\n * @param size\n * Size (in bytes) to be allocated.\n * @param align\n * If 0, the return is a pointer that is suitably aligned for any kind of\n * variable (in the same manner as malloc()).\n * Otherwise, the return is a pointer that is a multiple of *align*. In\n * this case, it must obviously be a power of two. (Minimum alignment is the\n * cacheline size, i.e. 64-bytes)\n * @return\n * - NULL on error. Not enough memory, or invalid arguments (size is 0,\n * align is not a power of two).\n * - Otherwise, the pointer to the allocated object.\n */\nvoid *\nrte_zmalloc(const char *type, size_t size, unsigned align);\n\n/**\n * Replacement function for calloc(), using huge-page memory. Memory area is\n * initialised with zeros. In NUMA systems, the memory allocated resides on the\n * same NUMA socket as the core that calls this function.\n *\n * @param type\n * A string identifying the type of allocated objects (useful for debug\n * purposes, such as identifying the cause of a memory leak). Can be NULL.\n * @param num\n * Number of elements to be allocated.\n * @param size\n * Size (in bytes) of a single element.\n * @param align\n * If 0, the return is a pointer that is suitably aligned for any kind of\n * variable (in the same manner as malloc()).\n * Otherwise, the return is a pointer that is a multiple of *align*. In\n * this case, it must obviously be a power of two. (Minimum alignment is the\n * cacheline size, i.e. 64-bytes)\n * @return\n * - NULL on error. Not enough memory, or invalid arguments (size is 0,\n * align is not a power of two).\n * - Otherwise, the pointer to the allocated object.\n */\nvoid *\nrte_calloc(const char *type, size_t num, size_t size, unsigned align);\n\n/**\n * Replacement function for realloc(), using huge-page memory. Reserved area\n * memory is resized, preserving contents. In NUMA systems, the new area\n * resides on the same NUMA socket as the old area.\n *\n * @param ptr\n * Pointer to already allocated memory\n * @param size\n * Size (in bytes) of new area. If this is 0, memory is freed.\n * @param align\n * If 0, the return is a pointer that is suitably aligned for any kind of\n * variable (in the same manner as malloc()).\n * Otherwise, the return is a pointer that is a multiple of *align*. In\n * this case, it must obviously be a power of two. (Minimum alignment is the\n * cacheline size, i.e. 64-bytes)\n * @return\n * - NULL on error. Not enough memory, or invalid arguments (size is 0,\n * align is not a power of two).\n * - Otherwise, the pointer to the reallocated memory.\n */\nvoid *\nrte_realloc(void *ptr, size_t size, unsigned align);\n\n/**\n * This function allocates memory from the huge-page area of memory. The memory\n * is not cleared.\n *\n * @param type\n * A string identifying the type of allocated objects (useful for debug\n * purposes, such as identifying the cause of a memory leak). Can be NULL.\n * @param size\n * Size (in bytes) to be allocated.\n * @param align\n * If 0, the return is a pointer that is suitably aligned for any kind of\n * variable (in the same manner as malloc()).\n * Otherwise, the return is a pointer that is a multiple of *align*. In\n * this case, it must be a power of two. (Minimum alignment is the\n * cacheline size, i.e. 64-bytes)\n * @param socket\n * NUMA socket to allocate memory on. If SOCKET_ID_ANY is used, this function\n * will behave the same as rte_malloc().\n * @return\n * - NULL on error. Not enough memory, or invalid arguments (size is 0,\n * align is not a power of two).\n * - Otherwise, the pointer to the allocated object.\n */\nvoid *\nrte_malloc_socket(const char *type, size_t size, unsigned align, int socket);\n\n/**\n * Allocate zero'ed memory from the heap.\n *\n * Equivalent to rte_malloc() except that the memory zone is\n * initialised with zeros.\n *\n * @param type\n * A string identifying the type of allocated objects (useful for debug\n * purposes, such as identifying the cause of a memory leak). Can be NULL.\n * @param size\n * Size (in bytes) to be allocated.\n * @param align\n * If 0, the return is a pointer that is suitably aligned for any kind of\n * variable (in the same manner as malloc()).\n * Otherwise, the return is a pointer that is a multiple of *align*. In\n * this case, it must obviously be a power of two. (Minimum alignment is the\n * cacheline size, i.e. 64-bytes)\n * @param socket\n * NUMA socket to allocate memory on. If SOCKET_ID_ANY is used, this function\n * will behave the same as rte_zmalloc().\n * @return\n * - NULL on error. Not enough memory, or invalid arguments (size is 0,\n * align is not a power of two).\n * - Otherwise, the pointer to the allocated object.\n */\nvoid *\nrte_zmalloc_socket(const char *type, size_t size, unsigned align, int socket);\n\n/**\n * Replacement function for calloc(), using huge-page memory. Memory area is\n * initialised with zeros.\n *\n * @param type\n * A string identifying the type of allocated objects (useful for debug\n * purposes, such as identifying the cause of a memory leak). Can be NULL.\n * @param num\n * Number of elements to be allocated.\n * @param size\n * Size (in bytes) of a single element.\n * @param align\n * If 0, the return is a pointer that is suitably aligned for any kind of\n * variable (in the same manner as malloc()).\n * Otherwise, the return is a pointer that is a multiple of *align*. In\n * this case, it must obviously be a power of two. (Minimum alignment is the\n * cacheline size, i.e. 64-bytes)\n * @param socket\n * NUMA socket to allocate memory on. If SOCKET_ID_ANY is used, this function\n * will behave the same as rte_calloc().\n * @return\n * - NULL on error. Not enough memory, or invalid arguments (size is 0,\n * align is not a power of two).\n * - Otherwise, the pointer to the allocated object.\n */\nvoid *\nrte_calloc_socket(const char *type, size_t num, size_t size, unsigned align, int socket);\n\n/**\n * Frees the memory space pointed to by the provided pointer.\n *\n * This pointer must have been returned by a previous call to\n * rte_malloc(), rte_zmalloc(), rte_calloc() or rte_realloc(). The behaviour of\n * rte_free() is undefined if the pointer does not match this requirement.\n *\n * If the pointer is NULL, the function does nothing.\n *\n * @param ptr\n * The pointer to memory to be freed.\n */\nvoid\nrte_free(void *ptr);\n\n/**\n * If malloc debug is enabled, check a memory block for header\n * and trailer markers to indicate that all is well with the block.\n * If size is non-null, also return the size of the block.\n *\n * @param ptr\n * pointer to the start of a data block, must have been returned\n * by a previous call to rte_malloc(), rte_zmalloc(), rte_calloc()\n * or rte_realloc()\n * @param size\n * if non-null, and memory block pointer is valid, returns the size\n * of the memory block\n * @return\n * -1 on error, invalid pointer passed or header and trailer markers\n * are missing or corrupted\n * 0 on success\n */\nint\nrte_malloc_validate(const void *ptr, size_t *size);\n\n/**\n * Get heap statistics for the specified heap.\n *\n * @param socket\n * An unsigned integer specifying the socket to get heap statistics for\n * @param socket_stats\n * A structure which provides memory to store statistics\n * @return\n * Null on error\n * Pointer to structure storing statistics on success\n */\nint\nrte_malloc_get_socket_stats(int socket,\n\t\tstruct rte_malloc_socket_stats *socket_stats);\n\n/**\n * Dump statistics.\n *\n * Dump for the specified type to the console. If the type argument is\n * NULL, all memory types will be dumped.\n *\n * @param f\n * A pointer to a file for output\n * @param type\n * A string identifying the type of objects to dump, or NULL\n * to dump all objects.\n */\nvoid\nrte_malloc_dump_stats(FILE *f, const char *type);\n\n/**\n * Set the maximum amount of allocated memory for this type.\n *\n * This is not yet implemented\n *\n * @param type\n * A string identifying the type of allocated objects.\n * @param max\n * The maximum amount of allocated bytes for this type.\n * @return\n * - 0: Success.\n * - (-1): Error.\n */\nint\nrte_malloc_set_limit(const char *type, size_t max);\n\n/**\n * Return the physical address of a virtual address obtained through\n * rte_malloc\n *\n * @param addr\n * Adress obtained from a previous rte_malloc call\n * @return\n * NULL on error\n * otherwise return physical address of the buffer\n */\nphys_addr_t\nrte_malloc_virt2phy(const void *addr);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_MALLOC_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_malloc_heap.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_MALLOC_HEAP_H_\n#define _RTE_MALLOC_HEAP_H_\n\n#include \n#include \n#include \n#include \n\n/* Number of free lists per heap, grouped by size. */\n#define RTE_HEAP_NUM_FREELISTS 13\n\n/**\n * Structure to hold malloc heap\n */\nstruct malloc_heap {\n\trte_spinlock_t lock;\n\tLIST_HEAD(, malloc_elem) free_head[RTE_HEAP_NUM_FREELISTS];\n\tunsigned alloc_count;\n\tsize_t total_size;\n} __rte_cache_aligned;\n\n#endif /* _RTE_MALLOC_HEAP_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_memory.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_MEMORY_H_\n#define _RTE_MEMORY_H_\n\n/**\n * @file\n *\n * Memory-related RTE API.\n */\n\n#include \n#include \n#include \n\n#ifdef RTE_EXEC_ENV_LINUXAPP\n#include \n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nenum rte_page_sizes {\n\tRTE_PGSIZE_4K = 1ULL << 12,\n\tRTE_PGSIZE_64K = 1ULL << 16,\n\tRTE_PGSIZE_256K = 1ULL << 18,\n\tRTE_PGSIZE_2M = 1ULL << 21,\n\tRTE_PGSIZE_16M = 1ULL << 24,\n\tRTE_PGSIZE_256M = 1ULL << 28,\n\tRTE_PGSIZE_512M = 1ULL << 29,\n\tRTE_PGSIZE_1G = 1ULL << 30,\n\tRTE_PGSIZE_4G = 1ULL << 32,\n\tRTE_PGSIZE_16G = 1ULL << 34,\n};\n\n#define SOCKET_ID_ANY -1 /**< Any NUMA socket. */\n#ifndef RTE_CACHE_LINE_SIZE\n#define RTE_CACHE_LINE_SIZE 64 /**< Cache line size. */\n#endif\n#define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */\n\n#define RTE_CACHE_LINE_ROUNDUP(size) \\\n\t(RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))\n/**< Return the first cache-aligned value greater or equal to size. */\n\n/**\n * Force alignment to cache line.\n */\n#define __rte_cache_aligned __attribute__((__aligned__(RTE_CACHE_LINE_SIZE)))\n\ntypedef uint64_t phys_addr_t; /**< Physical address definition. */\n#define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1)\n\n/**\n * Physical memory segment descriptor.\n */\nstruct rte_memseg {\n\tphys_addr_t phys_addr; /**< Start physical address. */\n\tunion {\n\t\tvoid *addr; /**< Start virtual address. */\n\t\tuint64_t addr_64; /**< Makes sure addr is always 64 bits */\n\t};\n#ifdef RTE_LIBRTE_IVSHMEM\n\tphys_addr_t ioremap_addr; /**< Real physical address inside the VM */\n#endif\n\tsize_t len; /**< Length of the segment. */\n\tuint64_t hugepage_sz; /**< The pagesize of underlying memory */\n\tint32_t socket_id; /**< NUMA socket ID. */\n\tuint32_t nchannel; /**< Number of channels. */\n\tuint32_t nrank; /**< Number of ranks. */\n#ifdef RTE_LIBRTE_XEN_DOM0\n\t /**< store segment MFNs */\n\tuint64_t mfn[DOM0_NUM_MEMBLOCK];\n#endif\n} __attribute__((__packed__));\n\n/**\n * Lock page in physical memory and prevent from swapping.\n *\n * @param virt\n * The virtual address.\n * @return\n * 0 on success, negative on error.\n */\nint rte_mem_lock_page(const void *virt);\n\n/**\n * Get physical address of any mapped virtual address in the current process.\n * It is found by browsing the /proc/self/pagemap special file.\n * The page must be locked.\n *\n * @param virt\n * The virtual address.\n * @return\n * The physical address or RTE_BAD_PHYS_ADDR on error.\n */\nphys_addr_t rte_mem_virt2phy(const void *virt);\n\n/**\n * Get the layout of the available physical memory.\n *\n * It can be useful for an application to have the full physical\n * memory layout to decide the size of a memory zone to reserve. This\n * table is stored in rte_config (see rte_eal_get_configuration()).\n *\n * @return\n * - On success, return a pointer to a read-only table of struct\n * rte_physmem_desc elements, containing the layout of all\n * addressable physical memory. The last element of the table\n * contains a NULL address.\n * - On error, return NULL. This should not happen since it is a fatal\n * error that will probably cause the entire system to panic.\n */\nconst struct rte_memseg *rte_eal_get_physmem_layout(void);\n\n/**\n * Dump the physical memory layout to the console.\n *\n * @param f\n * A pointer to a file for output\n */\nvoid rte_dump_physmem_layout(FILE *f);\n\n/**\n * Get the total amount of available physical memory.\n *\n * @return\n * The total amount of available physical memory in bytes.\n */\nuint64_t rte_eal_get_physmem_size(void);\n\n/**\n * Get the number of memory channels.\n *\n * @return\n * The number of memory channels on the system. The value is 0 if unknown\n * or not the same on all devices.\n */\nunsigned rte_memory_get_nchannel(void);\n\n/**\n * Get the number of memory ranks.\n *\n * @return\n * The number of memory ranks on the system. The value is 0 if unknown or\n * not the same on all devices.\n */\nunsigned rte_memory_get_nrank(void);\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n/**\n * Return the physical address of elt, which is an element of the pool mp.\n *\n * @param memseg_id\n * The mempool is from which memory segment.\n * @param phy_addr\n * physical address of elt.\n *\n * @return\n * The physical address or error.\n */\nphys_addr_t rte_mem_phy2mch(uint32_t memseg_id, const phys_addr_t phy_addr);\n\n/**\n * Memory init for supporting application running on Xen domain0.\n *\n * @param void\n *\n * @return\n * 0: successfully\n *\t negative: error\n */\nint rte_xen_dom0_memory_init(void);\n\n/**\n * Attach to memory setments of primary process on Xen domain0.\n *\n * @param void\n *\n * @return\n * 0: successfully\n * negative: error\n */\nint rte_xen_dom0_memory_attach(void);\n#endif\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_MEMORY_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_memzone.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_MEMZONE_H_\n#define _RTE_MEMZONE_H_\n\n/**\n * @file\n * RTE Memzone\n *\n * The goal of the memzone allocator is to reserve contiguous\n * portions of physical memory. These zones are identified by a name.\n *\n * The memzone descriptors are shared by all partitions and are\n * located in a known place of physical memory. This zone is accessed\n * using rte_eal_get_configuration(). The lookup (by name) of a\n * memory zone can be done in any partition and returns the same\n * physical address.\n *\n * A reserved memory zone cannot be unreserved. The reservation shall\n * be done at initialization time only.\n */\n\n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define RTE_MEMZONE_2MB 0x00000001 /**< Use 2MB pages. */\n#define RTE_MEMZONE_1GB 0x00000002 /**< Use 1GB pages. */\n#define RTE_MEMZONE_16MB 0x00000100 /**< Use 16MB pages. */\n#define RTE_MEMZONE_16GB 0x00000200 /**< Use 16GB pages. */\n#define RTE_MEMZONE_256KB 0x00010000 /**< Use 256KB pages. */\n#define RTE_MEMZONE_256MB 0x00020000 /**< Use 256MB pages. */\n#define RTE_MEMZONE_512MB 0x00040000 /**< Use 512MB pages. */\n#define RTE_MEMZONE_4GB 0x00080000 /**< Use 4GB pages. */\n#define RTE_MEMZONE_SIZE_HINT_ONLY 0x00000004 /**< Use available page size */\n\n/**\n * A structure describing a memzone, which is a contiguous portion of\n * physical memory identified by a name.\n */\nstruct rte_memzone {\n\n#define RTE_MEMZONE_NAMESIZE 32 /**< Maximum length of memory zone name.*/\n\tchar name[RTE_MEMZONE_NAMESIZE]; /**< Name of the memory zone. */\n\n\tphys_addr_t phys_addr; /**< Start physical address. */\n\tunion {\n\t\tvoid *addr; /**< Start virtual address. */\n\t\tuint64_t addr_64; /**< Makes sure addr is always 64-bits */\n\t};\n#ifdef RTE_LIBRTE_IVSHMEM\n\tphys_addr_t ioremap_addr; /**< Real physical address inside the VM */\n#endif\n\tsize_t len; /**< Length of the memzone. */\n\n\tuint64_t hugepage_sz; /**< The page size of underlying memory */\n\n\tint32_t socket_id; /**< NUMA socket ID. */\n\n\tuint32_t flags; /**< Characteristics of this memzone. */\n\tuint32_t memseg_id; /** \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\nTAILQ_HEAD(pci_device_list, rte_pci_device); /**< PCI devices in D-linked Q. */\nTAILQ_HEAD(pci_driver_list, rte_pci_driver); /**< PCI drivers in D-linked Q. */\n\nextern struct pci_driver_list pci_driver_list; /**< Global list of PCI drivers. */\nextern struct pci_device_list pci_device_list; /**< Global list of PCI devices. */\n\n/** Pathname of PCI devices directory. */\n#define SYSFS_PCI_DEVICES \"/sys/bus/pci/devices\"\n\n/** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */\n#define PCI_PRI_FMT \"%.4\" PRIx16 \":%.2\" PRIx8 \":%.2\" PRIx8 \".%\" PRIx8\n\n/** Short formatting string, without domain, for PCI device: Ex: 00:01.0 */\n#define PCI_SHORT_PRI_FMT \"%.2\" PRIx8 \":%.2\" PRIx8 \".%\" PRIx8\n\n/** Nb. of values in PCI device identifier format string. */\n#define PCI_FMT_NVAL 4\n\n/** Nb. of values in PCI resource format. */\n#define PCI_RESOURCE_FMT_NVAL 3\n\n/** IO resource type: memory address space */\n#define IORESOURCE_MEM 0x00000200\n\n/**\n * A structure describing a PCI resource.\n */\nstruct rte_pci_resource {\n\tuint64_t phys_addr; /**< Physical address, 0 if no resource. */\n\tuint64_t len; /**< Length of the resource. */\n\tvoid *addr; /**< Virtual address, NULL when not mapped. */\n};\n\n/** Maximum number of PCI resources. */\n#define PCI_MAX_RESOURCE 6\n\n/**\n * A structure describing an ID for a PCI driver. Each driver provides a\n * table of these IDs for each device that it supports.\n */\nstruct rte_pci_id {\n\tuint16_t vendor_id; /**< Vendor ID or PCI_ANY_ID. */\n\tuint16_t device_id; /**< Device ID or PCI_ANY_ID. */\n\tuint16_t subsystem_vendor_id; /**< Subsystem vendor ID or PCI_ANY_ID. */\n\tuint16_t subsystem_device_id; /**< Subsystem device ID or PCI_ANY_ID. */\n};\n\n/**\n * A structure describing the location of a PCI device.\n */\nstruct rte_pci_addr {\n\tuint16_t domain; /**< Device domain */\n\tuint8_t bus; /**< Device bus */\n\tuint8_t devid; /**< Device ID */\n\tuint8_t function; /**< Device function. */\n};\n\nstruct rte_devargs;\n\nenum rte_kernel_driver {\n\tRTE_KDRV_UNKNOWN = 0,\n\tRTE_KDRV_IGB_UIO,\n\tRTE_KDRV_VFIO,\n\tRTE_KDRV_UIO_GENERIC,\n\tRTE_KDRV_NIC_UIO,\n};\n\n/**\n * A structure describing a PCI device.\n */\nstruct rte_pci_device {\n\tTAILQ_ENTRY(rte_pci_device) next; /**< Next probed PCI device. */\n\tstruct rte_pci_addr addr; /**< PCI location. */\n\tstruct rte_pci_id id; /**< PCI ID. */\n\tstruct rte_pci_resource mem_resource[PCI_MAX_RESOURCE]; /**< PCI Memory Resource */\n\tstruct rte_intr_handle intr_handle; /**< Interrupt handle */\n\tstruct rte_pci_driver *driver; /**< Associated driver */\n\tuint16_t max_vfs; /**< sriov enable if not zero */\n\tint numa_node; /**< NUMA node connection */\n\tstruct rte_devargs *devargs; /**< Device user arguments */\n\tenum rte_kernel_driver kdrv; /**< Kernel driver passthrough */\n};\n\n/** Any PCI device identifier (vendor, device, ...) */\n#define PCI_ANY_ID (0xffff)\n\n#ifdef __cplusplus\n/** C++ macro used to help building up tables of device IDs */\n#define RTE_PCI_DEVICE(vend, dev) \\\n\t(vend), \\\n\t(dev), \\\n\tPCI_ANY_ID, \\\n\tPCI_ANY_ID\n#else\n/** Macro used to help building up tables of device IDs */\n#define RTE_PCI_DEVICE(vend, dev) \\\n\t.vendor_id = (vend), \\\n\t.device_id = (dev), \\\n\t.subsystem_vendor_id = PCI_ANY_ID, \\\n\t.subsystem_device_id = PCI_ANY_ID\n#endif\n\nstruct rte_pci_driver;\n\n/**\n * Initialisation function for the driver called during PCI probing.\n */\ntypedef int (pci_devinit_t)(struct rte_pci_driver *, struct rte_pci_device *);\n\n/**\n * Uninitialisation function for the driver called during hotplugging.\n */\ntypedef int (pci_devuninit_t)(struct rte_pci_device *);\n\n/**\n * A structure describing a PCI driver.\n */\nstruct rte_pci_driver {\n\tTAILQ_ENTRY(rte_pci_driver) next; /**< Next in list. */\n\tconst char *name; /**< Driver name. */\n\tpci_devinit_t *devinit; /**< Device init. function. */\n\tpci_devuninit_t *devuninit; /**< Device uninit function. */\n\tconst struct rte_pci_id *id_table;\t/**< ID table, NULL terminated. */\n\tuint32_t drv_flags; /**< Flags contolling handling of device. */\n};\n\n/** Device needs PCI BAR mapping (done with either IGB_UIO or VFIO) */\n#define RTE_PCI_DRV_NEED_MAPPING 0x0001\n/** Device driver must be registered several times until failure - deprecated */\n#pragma GCC poison RTE_PCI_DRV_MULTIPLE\n/** Device needs to be unbound even if no module is provided */\n#define RTE_PCI_DRV_FORCE_UNBIND 0x0004\n/** Device driver supports link state interrupt */\n#define RTE_PCI_DRV_INTR_LSC\t0x0008\n/** Device driver supports detaching capability */\n#define RTE_PCI_DRV_DETACHABLE\t0x0010\n\n/**\n * A structure describing a PCI mapping.\n */\nstruct pci_map {\n\tvoid *addr;\n\tchar *path;\n\tuint64_t offset;\n\tuint64_t size;\n\tuint64_t phaddr;\n};\n\n/**\n * A structure describing a mapped PCI resource.\n * For multi-process we need to reproduce all PCI mappings in secondary\n * processes, so save them in a tailq.\n */\nstruct mapped_pci_resource {\n\tTAILQ_ENTRY(mapped_pci_resource) next;\n\n\tstruct rte_pci_addr pci_addr;\n\tchar path[PATH_MAX];\n\tint nb_maps;\n\tstruct pci_map maps[PCI_MAX_RESOURCE];\n};\n\n/** mapped pci device list */\nTAILQ_HEAD(mapped_pci_res_list, mapped_pci_resource);\n\n/**< Internal use only - Macro used by pci addr parsing functions **/\n#define GET_PCIADDR_FIELD(in, fd, lim, dlm) \\\ndo { \\\n\tunsigned long val; \\\n\tchar *end; \\\n\terrno = 0; \\\n\tval = strtoul((in), &end, 16); \\\n\tif (errno != 0 || end[0] != (dlm) || val > (lim)) \\\n\t\treturn -EINVAL; \\\n\t(fd) = (typeof (fd))val; \\\n\t(in) = end + 1; \\\n} while(0)\n\n/**\n * Utility function to produce a PCI Bus-Device-Function value\n * given a string representation. Assumes that the BDF is provided without\n * a domain prefix (i.e. domain returned is always 0)\n *\n * @param input\n *\tThe input string to be parsed. Should have the format XX:XX.X\n * @param dev_addr\n *\tThe PCI Bus-Device-Function address to be returned. Domain will always be\n *\treturned as 0\n * @return\n * 0 on success, negative on error.\n */\nstatic inline int\neal_parse_pci_BDF(const char *input, struct rte_pci_addr *dev_addr)\n{\n\tdev_addr->domain = 0;\n\tGET_PCIADDR_FIELD(input, dev_addr->bus, UINT8_MAX, ':');\n\tGET_PCIADDR_FIELD(input, dev_addr->devid, UINT8_MAX, '.');\n\tGET_PCIADDR_FIELD(input, dev_addr->function, UINT8_MAX, 0);\n\treturn 0;\n}\n\n/**\n * Utility function to produce a PCI Bus-Device-Function value\n * given a string representation. Assumes that the BDF is provided including\n * a domain prefix.\n *\n * @param input\n *\tThe input string to be parsed. Should have the format XXXX:XX:XX.X\n * @param dev_addr\n *\tThe PCI Bus-Device-Function address to be returned\n * @return\n * 0 on success, negative on error.\n */\nstatic inline int\neal_parse_pci_DomBDF(const char *input, struct rte_pci_addr *dev_addr)\n{\n\tGET_PCIADDR_FIELD(input, dev_addr->domain, UINT16_MAX, ':');\n\tGET_PCIADDR_FIELD(input, dev_addr->bus, UINT8_MAX, ':');\n\tGET_PCIADDR_FIELD(input, dev_addr->devid, UINT8_MAX, '.');\n\tGET_PCIADDR_FIELD(input, dev_addr->function, UINT8_MAX, 0);\n\treturn 0;\n}\n#undef GET_PCIADDR_FIELD\n\n/* Compare two PCI device addresses. */\n/**\n * Utility function to compare two PCI device addresses.\n *\n * @param addr\n *\tThe PCI Bus-Device-Function address to compare\n * @param addr2\n *\tThe PCI Bus-Device-Function address to compare\n * @return\n *\t0 on equal PCI address.\n *\tPositive on addr is greater than addr2.\n *\tNegative on addr is less than addr2, or error.\n */\nstatic inline int\nrte_eal_compare_pci_addr(const struct rte_pci_addr *addr,\n\t\t\t const struct rte_pci_addr *addr2)\n{\n\tuint64_t dev_addr, dev_addr2;\n\n\tif ((addr == NULL) || (addr2 == NULL))\n\t\treturn -1;\n\n\tdev_addr = (addr->domain << 24) | (addr->bus << 16) |\n\t\t\t\t(addr->devid << 8) | addr->function;\n\tdev_addr2 = (addr2->domain << 24) | (addr2->bus << 16) |\n\t\t\t\t(addr2->devid << 8) | addr2->function;\n\n\tif (dev_addr > dev_addr2)\n\t\treturn 1;\n\telse if (dev_addr < dev_addr2)\n\t\treturn -1;\n\telse\n\t\treturn 0;\n}\n\n/**\n * Scan the content of the PCI bus, and the devices in the devices\n * list\n *\n * @return\n * 0 on success, negative on error\n */\nint rte_eal_pci_scan(void);\n\n/**\n * Probe the PCI bus for registered drivers.\n *\n * Scan the content of the PCI bus, and call the probe() function for\n * all registered drivers that have a matching entry in its id_table\n * for discovered devices.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint rte_eal_pci_probe(void);\n\n/**\n * @internal\n * Map a particular resource from a file.\n *\n * @param requested_addr\n * The starting address for the new mapping range.\n * @param fd\n * The file descriptor.\n * @param offset\n * The offset for the mapping range.\n * @param size\n * The size for the mapping range.\n * @param additional_flags\n * The additional flags for the mapping range.\n * @return\n * - On success, the function returns a pointer to the mapped area.\n * - On error, the value MAP_FAILED is returned.\n */\nvoid *pci_map_resource(void *requested_addr, int fd, off_t offset,\n\t\tsize_t size, int additional_flags);\n\n/**\n * @internal\n * Unmap a particular resource.\n *\n * @param requested_addr\n * The address for the unmapping range.\n * @param size\n * The size for the unmapping range.\n */\nvoid pci_unmap_resource(void *requested_addr, size_t size);\n\n/**\n * Probe the single PCI device.\n *\n * Scan the content of the PCI bus, and find the pci device specified by pci\n * address, then call the probe() function for registered driver that has a\n * matching entry in its id_table for discovered device.\n *\n * @param addr\n *\tThe PCI Bus-Device-Function address to probe.\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint rte_eal_pci_probe_one(const struct rte_pci_addr *addr);\n\n/**\n * Close the single PCI device.\n *\n * Scan the content of the PCI bus, and find the pci device specified by pci\n * address, then call the devuninit() function for registered driver that has a\n * matching entry in its id_table for discovered device.\n *\n * @param addr\n *\tThe PCI Bus-Device-Function address to close.\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint rte_eal_pci_detach(const struct rte_pci_addr *addr);\nint __attribute__ ((deprecated))\nrte_eal_pci_close_one(const struct rte_pci_addr *addr);\n\n/**\n * Dump the content of the PCI bus.\n *\n * @param f\n * A pointer to a file for output\n */\nvoid rte_eal_pci_dump(FILE *f);\n\n/**\n * Register a PCI driver.\n *\n * @param driver\n * A pointer to a rte_pci_driver structure describing the driver\n * to be registered.\n */\nvoid rte_eal_pci_register(struct rte_pci_driver *driver);\n\n/**\n * Unregister a PCI driver.\n *\n * @param driver\n * A pointer to a rte_pci_driver structure describing the driver\n * to be unregistered.\n */\nvoid rte_eal_pci_unregister(struct rte_pci_driver *driver);\n\n/**\n * Read PCI config space.\n *\n * @param device\n * A pointer to a rte_pci_device structure describing the device\n * to use\n * @param buf\n * A data buffer where the bytes should be read into\n * @param len\n * The length of the data buffer.\n * @param offset\n * The offset into PCI config space\n */\nint rte_eal_pci_read_config(const struct rte_pci_device *device,\n\t\t\t void *buf, size_t len, off_t offset);\n\n/**\n * Write PCI config space.\n *\n * @param device\n * A pointer to a rte_pci_device structure describing the device\n * to use\n * @param buf\n * A data buffer containing the bytes should be written\n * @param len\n * The length of the data buffer.\n * @param offset\n * The offset into PCI config space\n */\nint rte_eal_pci_write_config(const struct rte_pci_device *device,\n\t\t\t const void *buf, size_t len, off_t offset);\n\n#ifdef RTE_PCI_CONFIG\n/**\n * Set special config space registers for performance purpose.\n *\n * @param dev\n * A pointer to a rte_pci_device structure describing the device\n * to use\n */\nvoid pci_config_space_set(struct rte_pci_device *dev);\n#endif /* RTE_PCI_CONFIG */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_PCI_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_pci_dev_feature_defs.h", "content": "/*-\n * This file is provided under a dual BSD/GPLv2 license. When using or\n * redistributing this file, you may do so under either license.\n *\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n *\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_PCI_DEV_DEFS_H_\n#define _RTE_PCI_DEV_DEFS_H_\n\n/* interrupt mode */\nenum rte_intr_mode {\n\tRTE_INTR_MODE_NONE = 0,\n\tRTE_INTR_MODE_LEGACY,\n\tRTE_INTR_MODE_MSI,\n\tRTE_INTR_MODE_MSIX\n};\n\n#endif /* _RTE_PCI_DEV_DEFS_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_pci_dev_features.h", "content": "/*-\n * This file is provided under a dual BSD/GPLv2 license. When using or\n * redistributing this file, you may do so under either license.\n *\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n *\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_PCI_DEV_FEATURES_H\n#define _RTE_PCI_DEV_FEATURES_H\n\n#include \n\n#define RTE_INTR_MODE_NONE_NAME \"none\"\n#define RTE_INTR_MODE_LEGACY_NAME \"legacy\"\n#define RTE_INTR_MODE_MSI_NAME \"msi\"\n#define RTE_INTR_MODE_MSIX_NAME \"msix\"\n\n#endif\n" }, { "path": "lib/librte_eal/common/include/rte_pci_dev_ids.h", "content": "/*-\n * This file is provided under a dual BSD/GPLv2 license. When using or\n * redistributing this file, you may do so under either license.\n *\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n *\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n */\n\n/**\n * @file\n *\n * This file contains a list of the PCI device IDs recognised by DPDK, which\n * can be used to fill out an array of structures describing the devices.\n *\n * Currently four families of devices are recognised: those supported by the\n * IGB driver, by EM driver, those supported by the IXGBE driver, and by virtio\n * driver which is a para virtualization driver running in guest virtual machine.\n * The inclusion of these in an array built using this file depends on the\n * definition of\n * RTE_PCI_DEV_ID_DECL_EM\n * RTE_PCI_DEV_ID_DECL_IGB\n * RTE_PCI_DEV_ID_DECL_IGBVF\n * RTE_PCI_DEV_ID_DECL_IXGBE\n * RTE_PCI_DEV_ID_DECL_IXGBEVF\n * RTE_PCI_DEV_ID_DECL_I40E\n * RTE_PCI_DEV_ID_DECL_I40EVF\n * RTE_PCI_DEV_ID_DECL_VIRTIO\n * at the time when this file is included.\n *\n * In order to populate an array, the user of this file must define this macro:\n * RTE_PCI_DEV_ID_DECL_IXGBE(vendorID, deviceID). For example:\n *\n * @code\n * struct device {\n * int vend;\n * int dev;\n * };\n *\n * struct device devices[] = {\n * #define RTE_PCI_DEV_ID_DECL_IXGBE(vendorID, deviceID) {vend, dev},\n * #include \n * };\n * @endcode\n *\n * Note that this file can be included multiple times within the same file.\n */\n\n#ifndef RTE_PCI_DEV_ID_DECL_EM\n#define RTE_PCI_DEV_ID_DECL_EM(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_IGB\n#define RTE_PCI_DEV_ID_DECL_IGB(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_IGBVF\n#define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_IXGBE\n#define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_IXGBEVF\n#define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_I40E\n#define RTE_PCI_DEV_ID_DECL_I40E(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_I40EVF\n#define RTE_PCI_DEV_ID_DECL_I40EVF(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_VIRTIO\n#define RTE_PCI_DEV_ID_DECL_VIRTIO(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_VMXNET3\n#define RTE_PCI_DEV_ID_DECL_VMXNET3(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_FM10K\n#define RTE_PCI_DEV_ID_DECL_FM10K(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_FM10KVF\n#define RTE_PCI_DEV_ID_DECL_FM10KVF(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_ENIC\n#define RTE_PCI_DEV_ID_DECL_ENIC(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_BNX2X\n#define RTE_PCI_DEV_ID_DECL_BNX2X(vend, dev)\n#endif\n\n#ifndef RTE_PCI_DEV_ID_DECL_BNX2XVF\n#define RTE_PCI_DEV_ID_DECL_BNX2XVF(vend, dev)\n#endif\n\n#ifndef PCI_VENDOR_ID_INTEL\n/** Vendor ID used by Intel devices */\n#define PCI_VENDOR_ID_INTEL 0x8086\n#endif\n\n#ifndef PCI_VENDOR_ID_QUMRANET\n/** Vendor ID used by virtio devices */\n#define PCI_VENDOR_ID_QUMRANET 0x1AF4\n#endif\n\n#ifndef PCI_VENDOR_ID_VMWARE\n/** Vendor ID used by VMware devices */\n#define PCI_VENDOR_ID_VMWARE 0x15AD\n#endif\n\n#ifndef PCI_VENDOR_ID_CISCO\n/** Vendor ID used by Cisco VIC devices */\n#define PCI_VENDOR_ID_CISCO 0x1137\n#endif\n\n#ifndef PCI_VENDOR_ID_BROADCOM\n/** Vendor ID used by Broadcom devices */\n#define PCI_VENDOR_ID_BROADCOM 0x14E4\n#endif\n\n/******************** Physical EM devices from e1000_hw.h ********************/\n\n#define E1000_DEV_ID_82542 0x1000\n#define E1000_DEV_ID_82543GC_FIBER 0x1001\n#define E1000_DEV_ID_82543GC_COPPER 0x1004\n#define E1000_DEV_ID_82544EI_COPPER 0x1008\n#define E1000_DEV_ID_82544EI_FIBER 0x1009\n#define E1000_DEV_ID_82544GC_COPPER 0x100C\n#define E1000_DEV_ID_82544GC_LOM 0x100D\n#define E1000_DEV_ID_82540EM 0x100E\n#define E1000_DEV_ID_82540EM_LOM 0x1015\n#define E1000_DEV_ID_82540EP_LOM 0x1016\n#define E1000_DEV_ID_82540EP 0x1017\n#define E1000_DEV_ID_82540EP_LP 0x101E\n#define E1000_DEV_ID_82545EM_COPPER 0x100F\n#define E1000_DEV_ID_82545EM_FIBER 0x1011\n#define E1000_DEV_ID_82545GM_COPPER 0x1026\n#define E1000_DEV_ID_82545GM_FIBER 0x1027\n#define E1000_DEV_ID_82545GM_SERDES 0x1028\n#define E1000_DEV_ID_82546EB_COPPER 0x1010\n#define E1000_DEV_ID_82546EB_FIBER 0x1012\n#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D\n#define E1000_DEV_ID_82546GB_COPPER 0x1079\n#define E1000_DEV_ID_82546GB_FIBER 0x107A\n#define E1000_DEV_ID_82546GB_SERDES 0x107B\n#define E1000_DEV_ID_82546GB_PCIE 0x108A\n#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099\n#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5\n#define E1000_DEV_ID_82541EI 0x1013\n#define E1000_DEV_ID_82541EI_MOBILE 0x1018\n#define E1000_DEV_ID_82541ER_LOM 0x1014\n#define E1000_DEV_ID_82541ER 0x1078\n#define E1000_DEV_ID_82541GI 0x1076\n#define E1000_DEV_ID_82541GI_LF 0x107C\n#define E1000_DEV_ID_82541GI_MOBILE 0x1077\n#define E1000_DEV_ID_82547EI 0x1019\n#define E1000_DEV_ID_82547EI_MOBILE 0x101A\n#define E1000_DEV_ID_82547GI 0x1075\n#define E1000_DEV_ID_82571EB_COPPER 0x105E\n#define E1000_DEV_ID_82571EB_FIBER 0x105F\n#define E1000_DEV_ID_82571EB_SERDES 0x1060\n#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9\n#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA\n#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4\n#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5\n#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5\n#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC\n#define E1000_DEV_ID_82572EI_COPPER 0x107D\n#define E1000_DEV_ID_82572EI_FIBER 0x107E\n#define E1000_DEV_ID_82572EI_SERDES 0x107F\n#define E1000_DEV_ID_82572EI 0x10B9\n#define E1000_DEV_ID_82573E 0x108B\n#define E1000_DEV_ID_82573E_IAMT 0x108C\n#define E1000_DEV_ID_82573L 0x109A\n#define E1000_DEV_ID_82574L 0x10D3\n#define E1000_DEV_ID_82574LA 0x10F6\n#define E1000_DEV_ID_82583V 0x150C\n#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096\n#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098\n#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA\n#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB\n#define E1000_DEV_ID_ICH8_82567V_3 0x1501\n#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049\n#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A\n#define E1000_DEV_ID_ICH8_IGP_C 0x104B\n#define E1000_DEV_ID_ICH8_IFE 0x104C\n#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4\n#define E1000_DEV_ID_ICH8_IFE_G 0x10C5\n#define E1000_DEV_ID_ICH8_IGP_M 0x104D\n#define E1000_DEV_ID_ICH9_IGP_M 0x10BF\n#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5\n#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB\n#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD\n#define E1000_DEV_ID_ICH9_BM 0x10E5\n#define E1000_DEV_ID_ICH9_IGP_C 0x294C\n#define E1000_DEV_ID_ICH9_IFE 0x10C0\n#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3\n#define E1000_DEV_ID_ICH9_IFE_G 0x10C2\n#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC\n#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD\n#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE\n#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE\n#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF\n#define E1000_DEV_ID_ICH10_D_BM_V 0x1525\n\n#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA\n#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB\n#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF\n#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0\n#define E1000_DEV_ID_PCH2_LV_LM 0x1502\n#define E1000_DEV_ID_PCH2_LV_V 0x1503\n#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A\n#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B\n#define E1000_DEV_ID_PCH_LPTLP_I218_LM\t 0x155A\n#define E1000_DEV_ID_PCH_LPTLP_I218_V\t 0x1559\n\n/*\n * Tested (supported) on VM emulated HW.\n */\n\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82540EM)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82545EM_COPPER)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82545EM_FIBER)\n\n/*\n * Tested (supported) on real HW.\n */\n\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82546EB_COPPER)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82546EB_FIBER)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82546EB_QUAD_COPPER)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82571EB_COPPER)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82571EB_FIBER)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82571EB_SERDES)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82572EI_COPPER)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82572EI_FIBER)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82572EI_SERDES)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82572EI)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82573L)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82574L)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82574LA)\nRTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82583V)\n\n/******************** Physical IGB devices from e1000_hw.h ********************/\n\n#define E1000_DEV_ID_82576 0x10C9\n#define E1000_DEV_ID_82576_FIBER 0x10E6\n#define E1000_DEV_ID_82576_SERDES 0x10E7\n#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8\n#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526\n#define E1000_DEV_ID_82576_NS 0x150A\n#define E1000_DEV_ID_82576_NS_SERDES 0x1518\n#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D\n#define E1000_DEV_ID_82575EB_COPPER 0x10A7\n#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9\n#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6\n#define E1000_DEV_ID_82580_COPPER 0x150E\n#define E1000_DEV_ID_82580_FIBER 0x150F\n#define E1000_DEV_ID_82580_SERDES 0x1510\n#define E1000_DEV_ID_82580_SGMII 0x1511\n#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516\n#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527\n#define E1000_DEV_ID_I350_COPPER 0x1521\n#define E1000_DEV_ID_I350_FIBER 0x1522\n#define E1000_DEV_ID_I350_SERDES 0x1523\n#define E1000_DEV_ID_I350_SGMII 0x1524\n#define E1000_DEV_ID_I350_DA4 0x1546\n#define E1000_DEV_ID_I210_COPPER 0x1533\n#define E1000_DEV_ID_I210_COPPER_OEM1 0x1534\n#define E1000_DEV_ID_I210_COPPER_IT 0x1535\n#define E1000_DEV_ID_I210_FIBER 0x1536\n#define E1000_DEV_ID_I210_SERDES 0x1537\n#define E1000_DEV_ID_I210_SGMII 0x1538\n#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B\n#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C\n#define E1000_DEV_ID_I211_COPPER 0x1539\n#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40\n#define E1000_DEV_ID_I354_SGMII 0x1F41\n#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45\n#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438\n#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A\n#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C\n#define E1000_DEV_ID_DH89XXCC_SFP 0x0440\n\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82576)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82576_FIBER)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82576_SERDES)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82576_QUAD_COPPER)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82576_NS)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82576_NS_SERDES)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82576_SERDES_QUAD)\n\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82575EB_COPPER)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER)\n\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82580_COPPER)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82580_FIBER)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82580_SERDES)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82580_SGMII)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82580_COPPER_DUAL)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82580_QUAD_FIBER)\n\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I350_COPPER)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I350_FIBER)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I350_SERDES)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I350_SGMII)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I350_DA4)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I210_COPPER)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I210_COPPER_OEM1)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I210_COPPER_IT)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I210_FIBER)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I210_SERDES)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I210_SGMII)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I211_COPPER)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I354_SGMII)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_DH89XXCC_SGMII)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_DH89XXCC_SERDES)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE)\nRTE_PCI_DEV_ID_DECL_IGB(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_DH89XXCC_SFP)\n\n/****************** Physical IXGBE devices from ixgbe_type.h ******************/\n\n#define IXGBE_DEV_ID_82598 0x10B6\n#define IXGBE_DEV_ID_82598_BX 0x1508\n#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6\n#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7\n#define IXGBE_DEV_ID_82598AT 0x10C8\n#define IXGBE_DEV_ID_82598AT2 0x150B\n#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB\n#define IXGBE_DEV_ID_82598EB_CX4 0x10DD\n#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC\n#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1\n#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1\n#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4\n#define IXGBE_DEV_ID_82599_KX4 0x10F7\n#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514\n#define IXGBE_DEV_ID_82599_KR 0x1517\n#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8\n#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C\n#define IXGBE_DEV_ID_82599_CX4 0x10F9\n#define IXGBE_DEV_ID_82599_SFP 0x10FB\n#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9\n#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72\n#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0\n#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470\n#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A\n#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529\n#define IXGBE_DEV_ID_82599_SFP_EM 0x1507\n#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D\n#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A\n#define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558\n#define IXGBE_DEV_ID_82599EN_SFP 0x1557\n#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC\n#define IXGBE_DEV_ID_82599_T3_LOM 0x151C\n#define IXGBE_DEV_ID_82599_LS 0x154F\n#define IXGBE_DEV_ID_X540T 0x1528\n#define IXGBE_DEV_ID_X540T1 0x1560\n#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC\n#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD\n#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE\n#define IXGBE_DEV_ID_X550T 0x1563\n#define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA\n#define IXGBE_DEV_ID_X550EM_X_KR 0x15AB\n\n#ifdef RTE_NIC_BYPASS\n#define IXGBE_DEV_ID_82599_BYPASS 0x155D\n#endif\n\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598_BX)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, \\\n\tIXGBE_DEV_ID_82598AF_SINGLE_PORT)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598AT)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598AT2)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598EB_CX4)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, \\\n\tIXGBE_DEV_ID_82598_SR_DUAL_PORT_EM)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82598EB_XF_LR)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_KX4)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_KR)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, \\\n\tIXGBE_DEV_ID_82599_COMBO_BACKPLANE)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, \\\n\tIXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_CX4)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_SFP)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_SUBDEV_ID_82599_SFP)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_SUBDEV_ID_82599_RNDC)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_SUBDEV_ID_82599_560FLR)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_SUBDEV_ID_82599_ECNA_DP)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_SFP_FCOE)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_SFP_EM)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_SFP_SF2)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599EN_SFP)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_XAUI_LOM)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_T3_LOM)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_LS)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X540T)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X540T1)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550EM_X_SFP)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550EM_X_10G_T)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550EM_X_1G_T)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550T)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550EM_X_KX4)\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550EM_X_KR)\n\n#ifdef RTE_NIC_BYPASS\nRTE_PCI_DEV_ID_DECL_IXGBE(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_BYPASS)\n#endif\n\n/*************** Physical I40E devices from i40e_type.h *****************/\n\n#define I40E_DEV_ID_SFP_XL710 0x1572\n#define I40E_DEV_ID_QEMU 0x1574\n#define I40E_DEV_ID_KX_A 0x157F\n#define I40E_DEV_ID_KX_B 0x1580\n#define I40E_DEV_ID_KX_C 0x1581\n#define I40E_DEV_ID_QSFP_A 0x1583\n#define I40E_DEV_ID_QSFP_B 0x1584\n#define I40E_DEV_ID_QSFP_C 0x1585\n#define I40E_DEV_ID_10G_BASE_T 0x1586\n\nRTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_SFP_XL710)\nRTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QEMU)\nRTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_KX_A)\nRTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_KX_B)\nRTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_KX_C)\nRTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QSFP_A)\nRTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QSFP_B)\nRTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_QSFP_C)\nRTE_PCI_DEV_ID_DECL_I40E(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_10G_BASE_T)\n\n/*************** Physical FM10K devices from fm10k_type.h ***************/\n\n#define FM10K_DEV_ID_PF 0x15A4\n\nRTE_PCI_DEV_ID_DECL_FM10K(PCI_VENDOR_ID_INTEL, FM10K_DEV_ID_PF)\n\n/****************** Virtual IGB devices from e1000_hw.h ******************/\n\n#define E1000_DEV_ID_82576_VF 0x10CA\n#define E1000_DEV_ID_82576_VF_HV 0x152D\n#define E1000_DEV_ID_I350_VF 0x1520\n#define E1000_DEV_ID_I350_VF_HV 0x152F\n\nRTE_PCI_DEV_ID_DECL_IGBVF(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82576_VF)\nRTE_PCI_DEV_ID_DECL_IGBVF(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82576_VF_HV)\nRTE_PCI_DEV_ID_DECL_IGBVF(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I350_VF)\nRTE_PCI_DEV_ID_DECL_IGBVF(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_I350_VF_HV)\n\n/****************** Virtual IXGBE devices from ixgbe_type.h ******************/\n\n#define IXGBE_DEV_ID_82599_VF 0x10ED\n#define IXGBE_DEV_ID_82599_VF_HV 0x152E\n#define IXGBE_DEV_ID_X540_VF 0x1515\n#define IXGBE_DEV_ID_X540_VF_HV 0x1530\n#define IXGBE_DEV_ID_X550_VF_HV 0x1564\n#define IXGBE_DEV_ID_X550_VF 0x1565\n#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8\n#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9\n\nRTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_VF)\nRTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_82599_VF_HV)\nRTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X540_VF)\nRTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X540_VF_HV)\nRTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550_VF_HV)\nRTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550_VF)\nRTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550EM_X_VF)\nRTE_PCI_DEV_ID_DECL_IXGBEVF(PCI_VENDOR_ID_INTEL, IXGBE_DEV_ID_X550EM_X_VF_HV)\n\n/****************** Virtual I40E devices from i40e_type.h ********************/\n\n#define I40E_DEV_ID_VF 0x154C\n#define I40E_DEV_ID_VF_HV 0x1571\n\nRTE_PCI_DEV_ID_DECL_I40EVF(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_VF)\nRTE_PCI_DEV_ID_DECL_I40EVF(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_VF_HV)\n\n/****************** Virtio devices from virtio.h ******************/\n\n#define QUMRANET_DEV_ID_VIRTIO 0x1000\n\nRTE_PCI_DEV_ID_DECL_VIRTIO(PCI_VENDOR_ID_QUMRANET, QUMRANET_DEV_ID_VIRTIO)\n\n/****************** VMware VMXNET3 devices ******************/\n\n#define VMWARE_DEV_ID_VMXNET3 0x07B0\n\nRTE_PCI_DEV_ID_DECL_VMXNET3(PCI_VENDOR_ID_VMWARE, VMWARE_DEV_ID_VMXNET3)\n\n/*************** Virtual FM10K devices from fm10k_type.h ***************/\n\n#define FM10K_DEV_ID_VF 0x15A5\n\nRTE_PCI_DEV_ID_DECL_FM10KVF(PCI_VENDOR_ID_INTEL, FM10K_DEV_ID_VF)\n\n/****************** Cisco VIC devices ******************/\n\n#define PCI_DEVICE_ID_CISCO_VIC_ENET 0x0043 /* ethernet vnic */\n#define PCI_DEVICE_ID_CISCO_VIC_ENET_VF 0x0071 /* enet SRIOV VF */\n\nRTE_PCI_DEV_ID_DECL_ENIC(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET)\nRTE_PCI_DEV_ID_DECL_ENIC(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF)\n\n/****************** QLogic devices ******************/\n\n/* Broadcom/QLogic BNX2X */\n#define BNX2X_DEV_ID_57710\t0x164e\n#define BNX2X_DEV_ID_57711\t0x164f\n#define BNX2X_DEV_ID_57711E\t0x1650\n#define BNX2X_DEV_ID_57712\t0x1662\n#define BNX2X_DEV_ID_57712_MF\t0x1663\n#define BNX2X_DEV_ID_57712_VF\t0x166f\n#define BNX2X_DEV_ID_57713\t0x1651\n#define BNX2X_DEV_ID_57713E\t0x1652\n#define BNX2X_DEV_ID_57800\t0x168a\n#define BNX2X_DEV_ID_57800_MF\t0x16a5\n#define BNX2X_DEV_ID_57800_VF\t0x16a9\n#define BNX2X_DEV_ID_57810\t0x168e\n#define BNX2X_DEV_ID_57810_MF\t0x16ae\n#define BNX2X_DEV_ID_57810_VF\t0x16af\n#define BNX2X_DEV_ID_57811\t0x163d\n#define BNX2X_DEV_ID_57811_MF\t0x163e\n#define BNX2X_DEV_ID_57811_VF\t0x163f\n\n#define BNX2X_DEV_ID_57840_OBS\t\t0x168d\n#define BNX2X_DEV_ID_57840_OBS_MF\t0x16ab\n#define BNX2X_DEV_ID_57840_4_10\t\t0x16a1\n#define BNX2X_DEV_ID_57840_2_20\t\t0x16a2\n#define BNX2X_DEV_ID_57840_MF\t\t0x16a4\n#define BNX2X_DEV_ID_57840_VF\t\t0x16ad\n\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57800)\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57800_VF)\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57711)\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57810)\nRTE_PCI_DEV_ID_DECL_BNX2XVF(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57810_VF)\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57811)\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57811_VF)\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57840_OBS)\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57840_4_10)\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57840_2_20)\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57840_VF)\n#ifdef RTE_LIBRTE_BNX2X_MF_SUPPORT\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57810_MF)\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57811_MF)\nRTE_PCI_DEV_ID_DECL_BNX2X(PCI_VENDOR_ID_BROADCOM, BNX2X_DEV_ID_57840_MF)\n#endif\n\n/*\n * Undef all RTE_PCI_DEV_ID_DECL_* here.\n */\n#undef RTE_PCI_DEV_ID_DECL_BNX2X\n#undef RTE_PCI_DEV_ID_DECL_BNX2XVF\n#undef RTE_PCI_DEV_ID_DECL_EM\n#undef RTE_PCI_DEV_ID_DECL_IGB\n#undef RTE_PCI_DEV_ID_DECL_IGBVF\n#undef RTE_PCI_DEV_ID_DECL_IXGBE\n#undef RTE_PCI_DEV_ID_DECL_IXGBEVF\n#undef RTE_PCI_DEV_ID_DECL_I40E\n#undef RTE_PCI_DEV_ID_DECL_I40EVF\n#undef RTE_PCI_DEV_ID_DECL_VIRTIO\n#undef RTE_PCI_DEV_ID_DECL_VMXNET3\n#undef RTE_PCI_DEV_ID_DECL_FM10K\n#undef RTE_PCI_DEV_ID_DECL_FM10KVF\n" }, { "path": "lib/librte_eal/common/include/rte_per_lcore.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_PER_LCORE_H_\n#define _RTE_PER_LCORE_H_\n\n/**\n * @file\n *\n * Per-lcore variables in RTE\n *\n * This file defines an API for instantiating per-lcore \"global\n * variables\" that are environment-specific. Note that in all\n * environments, a \"shared variable\" is the default when you use a\n * global variable.\n *\n * Parts of this are execution environment specific.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n/**\n * Macro to define a per lcore variable \"var\" of type \"type\", don't\n * use keywords like \"static\" or \"volatile\" in type, just prefix the\n * whole macro.\n */\n#define RTE_DEFINE_PER_LCORE(type, name)\t\t\t\\\n\t__thread __typeof__(type) per_lcore_##name\n\n/**\n * Macro to declare an extern per lcore variable \"var\" of type \"type\"\n */\n#define RTE_DECLARE_PER_LCORE(type, name)\t\t\t\\\n\textern __thread __typeof__(type) per_lcore_##name\n\n/**\n * Read/write the per-lcore variable value\n */\n#define RTE_PER_LCORE(name) (per_lcore_##name)\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_PER_LCORE_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_random.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_RANDOM_H_\n#define _RTE_RANDOM_H_\n\n/**\n * @file\n *\n * Pseudo-random Generators in RTE\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n\n/**\n * Seed the pseudo-random generator.\n *\n * The generator is automatically seeded by the EAL init with a timer\n * value. It may need to be re-seeded by the user with a real random\n * value.\n *\n * @param seedval\n * The value of the seed.\n */\nstatic inline void\nrte_srand(uint64_t seedval)\n{\n\tsrand48((long unsigned int)seedval);\n}\n\n/**\n * Get a pseudo-random value.\n *\n * This function generates pseudo-random numbers using the linear\n * congruential algorithm and 48-bit integer arithmetic, called twice\n * to generate a 64-bit value.\n *\n * @return\n * A pseudo-random value between 0 and (1<<64)-1.\n */\nstatic inline uint64_t\nrte_rand(void)\n{\n\tuint64_t val;\n\tval = lrand48();\n\tval <<= 32;\n\tval += lrand48();\n\treturn val;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* _RTE_PER_LCORE_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_string_fns.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/**\n * @file\n *\n * String-related functions as replacement for libc equivalents\n */\n\n#ifndef _RTE_STRING_FNS_H_\n#define _RTE_STRING_FNS_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Takes string \"string\" parameter and splits it at character \"delim\"\n * up to maxtokens-1 times - to give \"maxtokens\" resulting tokens. Like\n * strtok or strsep functions, this modifies its input string, by replacing\n * instances of \"delim\" with '\\\\0'. All resultant tokens are returned in the\n * \"tokens\" array which must have enough entries to hold \"maxtokens\".\n *\n * @param string\n * The input string to be split into tokens\n *\n * @param stringlen\n * The max length of the input buffer\n *\n * @param tokens\n * The array to hold the pointers to the tokens in the string\n *\n * @param maxtokens\n * The number of elements in the tokens array. At most, maxtokens-1 splits\n * of the string will be done.\n *\n * @param delim\n * The character on which the split of the data will be done\n *\n * @return\n * The number of tokens in the tokens array.\n */\nint\nrte_strsplit(char *string, int stringlen,\n char **tokens, int maxtokens, char delim);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* RTE_STRING_FNS_H */\n" }, { "path": "lib/librte_eal/common/include/rte_tailq.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_TAILQ_H_\n#define _RTE_TAILQ_H_\n\n/**\n * @file\n * Here defines rte_tailq APIs for only internal use\n *\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n#include \n\n/** dummy structure type used by the rte_tailq APIs */\nstruct rte_tailq_entry {\n\tTAILQ_ENTRY(rte_tailq_entry) next; /**< Pointer entries for a tailq list */\n\tvoid *data; /**< Pointer to the data referenced by this tailq entry */\n};\n/** dummy */\nTAILQ_HEAD(rte_tailq_entry_head, rte_tailq_entry);\n\n#define RTE_TAILQ_NAMESIZE 32\n\n/**\n * The structure defining a tailq header entry for storing\n * in the rte_config structure in shared memory. Each tailq\n * is identified by name.\n * Any library storing a set of objects e.g. rings, mempools, hash-tables,\n * is recommended to use an entry here, so as to make it easy for\n * a multi-process app to find already-created elements in shared memory.\n */\nstruct rte_tailq_head {\n\tstruct rte_tailq_entry_head tailq_head; /**< NOTE: must be first element */\n\tchar name[RTE_TAILQ_NAMESIZE];\n};\n\nstruct rte_tailq_elem {\n\t/**\n\t * Reference to head in shared mem, updated at init time by\n\t * rte_eal_tailqs_init()\n\t */\n\tstruct rte_tailq_head *head;\n\tTAILQ_ENTRY(rte_tailq_elem) next;\n\tconst char name[RTE_TAILQ_NAMESIZE];\n};\n\n/**\n * Return the first tailq entry casted to the right struct.\n */\n#define RTE_TAILQ_CAST(tailq_entry, struct_name) \\\n\t(struct struct_name *)&(tailq_entry)->tailq_head\n\n/**\n * Utility macro to make looking up a tailqueue for a particular struct easier.\n *\n * @param name\n * The name of tailq\n *\n * @param struct_name\n * The name of the list type we are using. (Generally this is the same as the\n * first parameter passed to TAILQ_HEAD macro)\n *\n * @return\n * The return value from rte_eal_tailq_lookup, typecast to the appropriate\n * structure pointer type.\n * NULL on error, since the tailq_head is the first\n * element in the rte_tailq_head structure.\n */\n#define RTE_TAILQ_LOOKUP(name, struct_name) \\\n\tRTE_TAILQ_CAST(rte_eal_tailq_lookup(name), struct_name)\n\n/**\n * Dump tail queues to the console.\n *\n * @param f\n * A pointer to a file for output\n */\nvoid rte_dump_tailq(FILE *f);\n\n/**\n * Lookup for a tail queue.\n *\n * Get a pointer to a tail queue header of a tail\n * queue identified by the name given as an argument.\n * Note: this function is not multi-thread safe, and should only be called from\n * a single thread at a time\n *\n * @param name\n * The name of the queue.\n * @return\n * A pointer to the tail queue head structure.\n */\nstruct rte_tailq_head *rte_eal_tailq_lookup(const char *name);\n\n/**\n * Register a tail queue.\n *\n * Register a tail queue from shared memory.\n * This function is mainly used by EAL_REGISTER_TAILQ macro which is used to\n * register tailq from the different dpdk libraries. Since this macro is a\n * constructor, the function has no access to dpdk shared memory, so the\n * registered tailq can not be used before call to rte_eal_init() which calls\n * rte_eal_tailqs_init().\n *\n * @param t\n * The tailq element which contains the name of the tailq you want to\n * create (/retrieve when in secondary process).\n * @return\n * 0 on success or -1 in case of an error.\n */\nint rte_eal_tailq_register(struct rte_tailq_elem *t);\n\n#define EAL_REGISTER_TAILQ(t) \\\nvoid tailqinitfn_ ##t(void); \\\nvoid __attribute__((constructor, used)) tailqinitfn_ ##t(void) \\\n{ \\\n\tif (rte_eal_tailq_register(&t) < 0) \\\n\t\trte_panic(\"Cannot initialize tailq: %s\\n\", t.name); \\\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_TAILQ_H_ */\n" }, { "path": "lib/librte_eal/common/include/rte_version.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/**\n * @file\n * Definitions of Intel(R) DPDK version numbers\n */\n\n#ifndef _RTE_VERSION_H_\n#define _RTE_VERSION_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n#include \n\n/**\n * String that appears before the version number\n */\n#define RTE_VER_PREFIX \"RTE\"\n\n/**\n * Major version number i.e. the x in x.y.z\n */\n#define RTE_VER_MAJOR 2\n\n/**\n * Minor version number i.e. the y in x.y.z\n */\n#define RTE_VER_MINOR 1\n\n/**\n * Patch level number i.e. the z in x.y.z\n */\n#define RTE_VER_PATCH_LEVEL 0\n\n/**\n * Extra string to be appended to version number\n */\n#define RTE_VER_SUFFIX \"\"\n\n/**\n * Patch release number\n * 0-15 = release candidates\n * 16 = release\n */\n#define RTE_VER_PATCH_RELEASE 16\n\n/**\n * Macro to compute a version number usable for comparisons\n */\n#define RTE_VERSION_NUM(a,b,c,d) ((a) << 24 | (b) << 16 | (c) << 8 | (d))\n\n/**\n * All version numbers in one to compare with RTE_VERSION_NUM()\n */\n#define RTE_VERSION RTE_VERSION_NUM( \\\n\t\t\tRTE_VER_MAJOR, \\\n\t\t\tRTE_VER_MINOR, \\\n\t\t\tRTE_VER_PATCH_LEVEL, \\\n\t\t\tRTE_VER_PATCH_RELEASE)\n\n/**\n * Function returning version string\n * @return\n * string\n */\nstatic inline const char *\nrte_version(void)\n{\n\tstatic char version[32];\n\tif (version[0] != 0)\n\t\treturn version;\n\tif (strlen(RTE_VER_SUFFIX) == 0)\n\t\tsnprintf(version, sizeof(version), \"%s %d.%d.%d\",\n\t\t\tRTE_VER_PREFIX,\n\t\t\tRTE_VER_MAJOR,\n\t\t\tRTE_VER_MINOR,\n\t\t\tRTE_VER_PATCH_LEVEL);\n\telse\n\t\tsnprintf(version, sizeof(version), \"%s %d.%d.%d%s%d\",\n\t\t\tRTE_VER_PREFIX,\n\t\t\tRTE_VER_MAJOR,\n\t\t\tRTE_VER_MINOR,\n\t\t\tRTE_VER_PATCH_LEVEL,\n\t\t\tRTE_VER_SUFFIX,\n\t\t\tRTE_VER_PATCH_RELEASE < 16 ?\n\t\t\t\tRTE_VER_PATCH_RELEASE :\n\t\t\t\tRTE_VER_PATCH_RELEASE - 16);\n\treturn version;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* RTE_VERSION_H */\n" }, { "path": "lib/librte_eal/common/include/rte_warnings.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/**\n * @file\n * Definitions of warnings for use of various insecure functions\n */\n\n#ifndef _RTE_WARNINGS_H_\n#define _RTE_WARNINGS_H_\n\n#ifdef RTE_INSECURE_FUNCTION_WARNING\n\n/* we need to include all used standard header files so that they appear\n * _before_ we poison the function names.\n */\n\n#include \n#include \n#include \n#include \n#include \n#ifdef RTE_LIBRTE_EAL_LINUXAPP\n#include \n#endif\n\n/* the following function are deemed not fully secure for use e.g. they\n * do not always null-terminate arguments */\n#pragma GCC poison sprintf strtok snprintf vsnprintf\n#pragma GCC poison strlen strcpy strcat\n#pragma GCC poison sscanf\n\n/* other unsafe functions may be implemented as macros so just undef them */\n#ifdef strsep\n#undef strsep\n#else\n#pragma GCC poison strsep\n#endif\n\n#ifdef strncpy\n#undef strncpy\n#else\n#pragma GCC poison strncpy\n#endif\n\n#ifdef strncat\n#undef strncat\n#else\n#pragma GCC poison strncat\n#endif\n\n#endif\n\n#endif /* RTE_WARNINGS_H */\n" }, { "path": "lib/librte_eal/common/malloc_elem.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"malloc_elem.h\"\n#include \"malloc_heap.h\"\n\n#define MIN_DATA_SIZE (RTE_CACHE_LINE_SIZE)\n\n/*\n * initialise a general malloc_elem header structure\n */\nvoid\nmalloc_elem_init(struct malloc_elem *elem,\n\t\tstruct malloc_heap *heap, const struct rte_memseg *ms, size_t size)\n{\n\telem->heap = heap;\n\telem->ms = ms;\n\telem->prev = NULL;\n\tmemset(&elem->free_list, 0, sizeof(elem->free_list));\n\telem->state = ELEM_FREE;\n\telem->size = size;\n\telem->pad = 0;\n\tset_header(elem);\n\tset_trailer(elem);\n}\n\n/*\n * initialise a dummy malloc_elem header for the end-of-memseg marker\n */\nvoid\nmalloc_elem_mkend(struct malloc_elem *elem, struct malloc_elem *prev)\n{\n\tmalloc_elem_init(elem, prev->heap, prev->ms, 0);\n\telem->prev = prev;\n\telem->state = ELEM_BUSY; /* mark busy so its never merged */\n}\n\n/*\n * calculate the starting point of where data of the requested size\n * and alignment would fit in the current element. If the data doesn't\n * fit, return NULL.\n */\nstatic void *\nelem_start_pt(struct malloc_elem *elem, size_t size, unsigned align,\n\t\tsize_t bound)\n{\n\tconst size_t bmask = ~(bound - 1);\n\tuintptr_t end_pt = (uintptr_t)elem +\n\t\t\telem->size - MALLOC_ELEM_TRAILER_LEN;\n\tuintptr_t new_data_start = RTE_ALIGN_FLOOR((end_pt - size), align);\n\tuintptr_t new_elem_start;\n\n\t/* check boundary */\n\tif ((new_data_start & bmask) != ((end_pt - 1) & bmask)) {\n\t\tend_pt = RTE_ALIGN_FLOOR(end_pt, bound);\n\t\tnew_data_start = RTE_ALIGN_FLOOR((end_pt - size), align);\n\t\tif (((end_pt - 1) & bmask) != (new_data_start & bmask))\n\t\t\treturn NULL;\n\t}\n\n\tnew_elem_start = new_data_start - MALLOC_ELEM_HEADER_LEN;\n\n\t/* if the new start point is before the exist start, it won't fit */\n\treturn (new_elem_start < (uintptr_t)elem) ? NULL : (void *)new_elem_start;\n}\n\n/*\n * use elem_start_pt to determine if we get meet the size and\n * alignment request from the current element\n */\nint\nmalloc_elem_can_hold(struct malloc_elem *elem, size_t size,\tunsigned align,\n\t\tsize_t bound)\n{\n\treturn elem_start_pt(elem, size, align, bound) != NULL;\n}\n\n/*\n * split an existing element into two smaller elements at the given\n * split_pt parameter.\n */\nstatic void\nsplit_elem(struct malloc_elem *elem, struct malloc_elem *split_pt)\n{\n\tstruct malloc_elem *next_elem = RTE_PTR_ADD(elem, elem->size);\n\tconst size_t old_elem_size = (uintptr_t)split_pt - (uintptr_t)elem;\n\tconst size_t new_elem_size = elem->size - old_elem_size;\n\n\tmalloc_elem_init(split_pt, elem->heap, elem->ms, new_elem_size);\n\tsplit_pt->prev = elem;\n\tnext_elem->prev = split_pt;\n\telem->size = old_elem_size;\n\tset_trailer(elem);\n}\n\n/*\n * Given an element size, compute its freelist index.\n * We free an element into the freelist containing similarly-sized elements.\n * We try to allocate elements starting with the freelist containing\n * similarly-sized elements, and if necessary, we search freelists\n * containing larger elements.\n *\n * Example element size ranges for a heap with five free lists:\n * heap->free_head[0] - (0 , 2^8]\n * heap->free_head[1] - (2^8 , 2^10]\n * heap->free_head[2] - (2^10 ,2^12]\n * heap->free_head[3] - (2^12, 2^14]\n * heap->free_head[4] - (2^14, MAX_SIZE]\n */\nsize_t\nmalloc_elem_free_list_index(size_t size)\n{\n#define MALLOC_MINSIZE_LOG2 8\n#define MALLOC_LOG2_INCREMENT 2\n\n\tsize_t log2;\n\tsize_t index;\n\n\tif (size <= (1UL << MALLOC_MINSIZE_LOG2))\n\t\treturn 0;\n\n\t/* Find next power of 2 >= size. */\n\tlog2 = sizeof(size) * 8 - __builtin_clzl(size-1);\n\n\t/* Compute freelist index, based on log2(size). */\n\tindex = (log2 - MALLOC_MINSIZE_LOG2 + MALLOC_LOG2_INCREMENT - 1) /\n\t MALLOC_LOG2_INCREMENT;\n\n\treturn (index <= RTE_HEAP_NUM_FREELISTS-1?\n\t index: RTE_HEAP_NUM_FREELISTS-1);\n}\n\n/*\n * Add the specified element to its heap's free list.\n */\nvoid\nmalloc_elem_free_list_insert(struct malloc_elem *elem)\n{\n\tsize_t idx;\n\n\tidx = malloc_elem_free_list_index(elem->size - MALLOC_ELEM_HEADER_LEN);\n\telem->state = ELEM_FREE;\n\tLIST_INSERT_HEAD(&elem->heap->free_head[idx], elem, free_list);\n}\n\n/*\n * Remove the specified element from its heap's free list.\n */\nstatic void\nelem_free_list_remove(struct malloc_elem *elem)\n{\n\tLIST_REMOVE(elem, free_list);\n}\n\n/*\n * reserve a block of data in an existing malloc_elem. If the malloc_elem\n * is much larger than the data block requested, we split the element in two.\n * This function is only called from malloc_heap_alloc so parameter checking\n * is not done here, as it's done there previously.\n */\nstruct malloc_elem *\nmalloc_elem_alloc(struct malloc_elem *elem, size_t size, unsigned align,\n\t\tsize_t bound)\n{\n\tstruct malloc_elem *new_elem = elem_start_pt(elem, size, align, bound);\n\tconst size_t old_elem_size = (uintptr_t)new_elem - (uintptr_t)elem;\n\tconst size_t trailer_size = elem->size - old_elem_size - size -\n\t\tMALLOC_ELEM_OVERHEAD;\n\n\telem_free_list_remove(elem);\n\n\tif (trailer_size > MALLOC_ELEM_OVERHEAD + MIN_DATA_SIZE) {\n\t\t/* split it, too much free space after elem */\n\t\tstruct malloc_elem *new_free_elem =\n\t\t\t\tRTE_PTR_ADD(new_elem, size + MALLOC_ELEM_OVERHEAD);\n\n\t\tsplit_elem(elem, new_free_elem);\n\t\tmalloc_elem_free_list_insert(new_free_elem);\n\t}\n\n\tif (old_elem_size < MALLOC_ELEM_OVERHEAD + MIN_DATA_SIZE) {\n\t\t/* don't split it, pad the element instead */\n\t\telem->state = ELEM_BUSY;\n\t\telem->pad = old_elem_size;\n\n\t\t/* put a dummy header in padding, to point to real element header */\n\t\tif (elem->pad > 0){ /* pad will be at least 64-bytes, as everything\n\t\t * is cache-line aligned */\n\t\t\tnew_elem->pad = elem->pad;\n\t\t\tnew_elem->state = ELEM_PAD;\n\t\t\tnew_elem->size = elem->size - elem->pad;\n\t\t\tset_header(new_elem);\n\t\t}\n\n\t\treturn new_elem;\n\t}\n\n\t/* we are going to split the element in two. The original element\n\t * remains free, and the new element is the one allocated.\n\t * Re-insert original element, in case its new size makes it\n\t * belong on a different list.\n\t */\n\tsplit_elem(elem, new_elem);\n\tnew_elem->state = ELEM_BUSY;\n\tmalloc_elem_free_list_insert(elem);\n\n\treturn new_elem;\n}\n\n/*\n * joing two struct malloc_elem together. elem1 and elem2 must\n * be contiguous in memory.\n */\nstatic inline void\njoin_elem(struct malloc_elem *elem1, struct malloc_elem *elem2)\n{\n\tstruct malloc_elem *next = RTE_PTR_ADD(elem2, elem2->size);\n\telem1->size += elem2->size;\n\tnext->prev = elem1;\n}\n\n/*\n * free a malloc_elem block by adding it to the free list. If the\n * blocks either immediately before or immediately after newly freed block\n * are also free, the blocks are merged together.\n */\nint\nmalloc_elem_free(struct malloc_elem *elem)\n{\n\tif (!malloc_elem_cookies_ok(elem) || elem->state != ELEM_BUSY)\n\t\treturn -1;\n\n\trte_spinlock_lock(&(elem->heap->lock));\n\tstruct malloc_elem *next = RTE_PTR_ADD(elem, elem->size);\n\tif (next->state == ELEM_FREE){\n\t\t/* remove from free list, join to this one */\n\t\telem_free_list_remove(next);\n\t\tjoin_elem(elem, next);\n\t}\n\n\t/* check if previous element is free, if so join with it and return,\n\t * need to re-insert in free list, as that element's size is changing\n\t */\n\tif (elem->prev != NULL && elem->prev->state == ELEM_FREE) {\n\t\telem_free_list_remove(elem->prev);\n\t\tjoin_elem(elem->prev, elem);\n\t\tmalloc_elem_free_list_insert(elem->prev);\n\t}\n\t/* otherwise add ourselves to the free list */\n\telse {\n\t\tmalloc_elem_free_list_insert(elem);\n\t\telem->pad = 0;\n\t}\n\t/* decrease heap's count of allocated elements */\n\telem->heap->alloc_count--;\n\trte_spinlock_unlock(&(elem->heap->lock));\n\n\treturn 0;\n}\n\n/*\n * attempt to resize a malloc_elem by expanding into any free space\n * immediately after it in memory.\n */\nint\nmalloc_elem_resize(struct malloc_elem *elem, size_t size)\n{\n\tconst size_t new_size = size + MALLOC_ELEM_OVERHEAD;\n\t/* if we request a smaller size, then always return ok */\n\tconst size_t current_size = elem->size - elem->pad;\n\tif (current_size >= new_size)\n\t\treturn 0;\n\n\tstruct malloc_elem *next = RTE_PTR_ADD(elem, elem->size);\n\trte_spinlock_lock(&elem->heap->lock);\n\tif (next ->state != ELEM_FREE)\n\t\tgoto err_return;\n\tif (current_size + next->size < new_size)\n\t\tgoto err_return;\n\n\t/* we now know the element fits, so remove from free list,\n\t * join the two\n\t */\n\telem_free_list_remove(next);\n\tjoin_elem(elem, next);\n\n\tif (elem->size - new_size >= MIN_DATA_SIZE + MALLOC_ELEM_OVERHEAD){\n\t\t/* now we have a big block together. Lets cut it down a bit, by splitting */\n\t\tstruct malloc_elem *split_pt = RTE_PTR_ADD(elem, new_size);\n\t\tsplit_pt = RTE_PTR_ALIGN_CEIL(split_pt, RTE_CACHE_LINE_SIZE);\n\t\tsplit_elem(elem, split_pt);\n\t\tmalloc_elem_free_list_insert(split_pt);\n\t}\n\trte_spinlock_unlock(&elem->heap->lock);\n\treturn 0;\n\nerr_return:\n\trte_spinlock_unlock(&elem->heap->lock);\n\treturn -1;\n}\n" }, { "path": "lib/librte_eal/common/malloc_elem.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef MALLOC_ELEM_H_\n#define MALLOC_ELEM_H_\n\n#include \n\n/* dummy definition of struct so we can use pointers to it in malloc_elem struct */\nstruct malloc_heap;\n\nenum elem_state {\n\tELEM_FREE = 0,\n\tELEM_BUSY,\n\tELEM_PAD /* element is a padding-only header */\n};\n\nstruct malloc_elem {\n\tstruct malloc_heap *heap;\n\tstruct malloc_elem *volatile prev; /* points to prev elem in memseg */\n\tLIST_ENTRY(malloc_elem) free_list; /* list of free elements in heap */\n\tconst struct rte_memseg *ms;\n\tvolatile enum elem_state state;\n\tuint32_t pad;\n\tsize_t size;\n#ifdef RTE_LIBRTE_MALLOC_DEBUG\n\tuint64_t header_cookie; /* Cookie marking start of data */\n\t /* trailer cookie at start + size */\n#endif\n} __rte_cache_aligned;\n\n#ifndef RTE_LIBRTE_MALLOC_DEBUG\nstatic const unsigned MALLOC_ELEM_TRAILER_LEN = 0;\n\n/* dummy function - just check if pointer is non-null */\nstatic inline int\nmalloc_elem_cookies_ok(const struct malloc_elem *elem){ return elem != NULL; }\n\n/* dummy function - no header if malloc_debug is not enabled */\nstatic inline void\nset_header(struct malloc_elem *elem __rte_unused){ }\n\n/* dummy function - no trailer if malloc_debug is not enabled */\nstatic inline void\nset_trailer(struct malloc_elem *elem __rte_unused){ }\n\n\n#else\nstatic const unsigned MALLOC_ELEM_TRAILER_LEN = RTE_CACHE_LINE_SIZE;\n\n#define MALLOC_HEADER_COOKIE 0xbadbadbadadd2e55ULL /**< Header cookie. */\n#define MALLOC_TRAILER_COOKIE 0xadd2e55badbadbadULL /**< Trailer cookie.*/\n\n/* define macros to make referencing the header and trailer cookies easier */\n#define MALLOC_ELEM_TRAILER(elem) (*((uint64_t*)RTE_PTR_ADD(elem, \\\n\t\telem->size - MALLOC_ELEM_TRAILER_LEN)))\n#define MALLOC_ELEM_HEADER(elem) (elem->header_cookie)\n\nstatic inline void\nset_header(struct malloc_elem *elem)\n{\n\tif (elem != NULL)\n\t\tMALLOC_ELEM_HEADER(elem) = MALLOC_HEADER_COOKIE;\n}\n\nstatic inline void\nset_trailer(struct malloc_elem *elem)\n{\n\tif (elem != NULL)\n\t\tMALLOC_ELEM_TRAILER(elem) = MALLOC_TRAILER_COOKIE;\n}\n\n/* check that the header and trailer cookies are set correctly */\nstatic inline int\nmalloc_elem_cookies_ok(const struct malloc_elem *elem)\n{\n\treturn (elem != NULL &&\n\t\t\tMALLOC_ELEM_HEADER(elem) == MALLOC_HEADER_COOKIE &&\n\t\t\tMALLOC_ELEM_TRAILER(elem) == MALLOC_TRAILER_COOKIE);\n}\n\n#endif\n\nstatic const unsigned MALLOC_ELEM_HEADER_LEN = sizeof(struct malloc_elem);\n#define MALLOC_ELEM_OVERHEAD (MALLOC_ELEM_HEADER_LEN + MALLOC_ELEM_TRAILER_LEN)\n\n/*\n * Given a pointer to the start of a memory block returned by malloc, get\n * the actual malloc_elem header for that block.\n */\nstatic inline struct malloc_elem *\nmalloc_elem_from_data(const void *data)\n{\n\tif (data == NULL)\n\t\treturn NULL;\n\n\tstruct malloc_elem *elem = RTE_PTR_SUB(data, MALLOC_ELEM_HEADER_LEN);\n\tif (!malloc_elem_cookies_ok(elem))\n\t\treturn NULL;\n\treturn elem->state != ELEM_PAD ? elem: RTE_PTR_SUB(elem, elem->pad);\n}\n\n/*\n * initialise a malloc_elem header\n */\nvoid\nmalloc_elem_init(struct malloc_elem *elem,\n\t\tstruct malloc_heap *heap,\n\t\tconst struct rte_memseg *ms,\n\t\tsize_t size);\n\n/*\n * initialise a dummy malloc_elem header for the end-of-memseg marker\n */\nvoid\nmalloc_elem_mkend(struct malloc_elem *elem,\n\t\tstruct malloc_elem *prev_free);\n\n/*\n * return true if the current malloc_elem can hold a block of data\n * of the requested size and with the requested alignment\n */\nint\nmalloc_elem_can_hold(struct malloc_elem *elem, size_t size,\n\t\tunsigned align, size_t bound);\n\n/*\n * reserve a block of data in an existing malloc_elem. If the malloc_elem\n * is much larger than the data block requested, we split the element in two.\n */\nstruct malloc_elem *\nmalloc_elem_alloc(struct malloc_elem *elem, size_t size,\n\t\tunsigned align, size_t bound);\n\n/*\n * free a malloc_elem block by adding it to the free list. If the\n * blocks either immediately before or immediately after newly freed block\n * are also free, the blocks are merged together.\n */\nint\nmalloc_elem_free(struct malloc_elem *elem);\n\n/*\n * attempt to resize a malloc_elem by expanding into any free space\n * immediately after it in memory.\n */\nint\nmalloc_elem_resize(struct malloc_elem *elem, size_t size);\n\n/*\n * Given an element size, compute its freelist index.\n */\nsize_t\nmalloc_elem_free_list_index(size_t size);\n\n/*\n * Add element to its heap's free list.\n */\nvoid\nmalloc_elem_free_list_insert(struct malloc_elem *elem);\n\n#endif /* MALLOC_ELEM_H_ */\n" }, { "path": "lib/librte_eal/common/malloc_heap.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"malloc_elem.h\"\n#include \"malloc_heap.h\"\n\nstatic unsigned\ncheck_hugepage_sz(unsigned flags, uint64_t hugepage_sz)\n{\n\tunsigned check_flag = 0;\n\n\tif (!(flags & ~RTE_MEMZONE_SIZE_HINT_ONLY))\n\t\treturn 1;\n\n\tswitch (hugepage_sz) {\n\tcase RTE_PGSIZE_256K:\n\t\tcheck_flag = RTE_MEMZONE_256KB;\n\t\tbreak;\n\tcase RTE_PGSIZE_2M:\n\t\tcheck_flag = RTE_MEMZONE_2MB;\n\t\tbreak;\n\tcase RTE_PGSIZE_16M:\n\t\tcheck_flag = RTE_MEMZONE_16MB;\n\t\tbreak;\n\tcase RTE_PGSIZE_256M:\n\t\tcheck_flag = RTE_MEMZONE_256MB;\n\t\tbreak;\n\tcase RTE_PGSIZE_512M:\n\t\tcheck_flag = RTE_MEMZONE_512MB;\n\t\tbreak;\n\tcase RTE_PGSIZE_1G:\n\t\tcheck_flag = RTE_MEMZONE_1GB;\n\t\tbreak;\n\tcase RTE_PGSIZE_4G:\n\t\tcheck_flag = RTE_MEMZONE_4GB;\n\t\tbreak;\n\tcase RTE_PGSIZE_16G:\n\t\tcheck_flag = RTE_MEMZONE_16GB;\n\t}\n\n\treturn (check_flag & flags);\n}\n\n/*\n * Expand the heap with a memseg.\n * This reserves the zone and sets a dummy malloc_elem header at the end\n * to prevent overflow. The rest of the zone is added to free list as a single\n * large free block\n */\nstatic void\nmalloc_heap_add_memseg(struct malloc_heap *heap, struct rte_memseg *ms)\n{\n\t/* allocate the memory block headers, one at end, one at start */\n\tstruct malloc_elem *start_elem = (struct malloc_elem *)ms->addr;\n\tstruct malloc_elem *end_elem = RTE_PTR_ADD(ms->addr,\n\t\t\tms->len - MALLOC_ELEM_OVERHEAD);\n\tend_elem = RTE_PTR_ALIGN_FLOOR(end_elem, RTE_CACHE_LINE_SIZE);\n\tconst size_t elem_size = (uintptr_t)end_elem - (uintptr_t)start_elem;\n\n\tmalloc_elem_init(start_elem, heap, ms, elem_size);\n\tmalloc_elem_mkend(end_elem, start_elem);\n\tmalloc_elem_free_list_insert(start_elem);\n\n\theap->total_size += elem_size;\n}\n\n/*\n * Iterates through the freelist for a heap to find a free element\n * which can store data of the required size and with the requested alignment.\n * If size is 0, find the biggest available elem.\n * Returns null on failure, or pointer to element on success.\n */\nstatic struct malloc_elem *\nfind_suitable_element(struct malloc_heap *heap, size_t size,\n\t\tunsigned flags, size_t align, size_t bound)\n{\n\tsize_t idx;\n\tstruct malloc_elem *elem, *alt_elem = NULL;\n\n\tfor (idx = malloc_elem_free_list_index(size);\n\t\t\tidx < RTE_HEAP_NUM_FREELISTS; idx++) {\n\t\tfor (elem = LIST_FIRST(&heap->free_head[idx]);\n\t\t\t\t!!elem; elem = LIST_NEXT(elem, free_list)) {\n\t\t\tif (malloc_elem_can_hold(elem, size, align, bound)) {\n\t\t\t\tif (check_hugepage_sz(flags, elem->ms->hugepage_sz))\n\t\t\t\t\treturn elem;\n\t\t\t\tif (alt_elem == NULL)\n\t\t\t\t\talt_elem = elem;\n\t\t\t}\n\t\t}\n\t}\n\n\tif ((alt_elem != NULL) && (flags & RTE_MEMZONE_SIZE_HINT_ONLY))\n\t\treturn alt_elem;\n\n\treturn NULL;\n}\n\n/*\n * Main function to allocate a block of memory from the heap.\n * It locks the free list, scans it, and adds a new memseg if the\n * scan fails. Once the new memseg is added, it re-scans and should return\n * the new element after releasing the lock.\n */\nvoid *\nmalloc_heap_alloc(struct malloc_heap *heap,\n\t\tconst char *type __attribute__((unused)), size_t size, unsigned flags,\n\t\tsize_t align, size_t bound)\n{\n\tstruct malloc_elem *elem;\n\n\tsize = RTE_CACHE_LINE_ROUNDUP(size);\n\talign = RTE_CACHE_LINE_ROUNDUP(align);\n\n\trte_spinlock_lock(&heap->lock);\n\n\telem = find_suitable_element(heap, size, flags, align, bound);\n\tif (elem != NULL) {\n\t\telem = malloc_elem_alloc(elem, size, align, bound);\n\t\t/* increase heap's count of allocated elements */\n\t\theap->alloc_count++;\n\t}\n\trte_spinlock_unlock(&heap->lock);\n\n\treturn elem == NULL ? NULL : (void *)(&elem[1]);\n}\n\n/*\n * Function to retrieve data for heap on given socket\n */\nint\nmalloc_heap_get_stats(const struct malloc_heap *heap,\n\t\tstruct rte_malloc_socket_stats *socket_stats)\n{\n\tsize_t idx;\n\tstruct malloc_elem *elem;\n\n\t/* Initialise variables for heap */\n\tsocket_stats->free_count = 0;\n\tsocket_stats->heap_freesz_bytes = 0;\n\tsocket_stats->greatest_free_size = 0;\n\n\t/* Iterate through free list */\n\tfor (idx = 0; idx < RTE_HEAP_NUM_FREELISTS; idx++) {\n\t\tfor (elem = LIST_FIRST(&heap->free_head[idx]);\n\t\t\t!!elem; elem = LIST_NEXT(elem, free_list))\n\t\t{\n\t\t\tsocket_stats->free_count++;\n\t\t\tsocket_stats->heap_freesz_bytes += elem->size;\n\t\t\tif (elem->size > socket_stats->greatest_free_size)\n\t\t\t\tsocket_stats->greatest_free_size = elem->size;\n\t\t}\n\t}\n\t/* Get stats on overall heap and allocated memory on this heap */\n\tsocket_stats->heap_totalsz_bytes = heap->total_size;\n\tsocket_stats->heap_allocsz_bytes = (socket_stats->heap_totalsz_bytes -\n\t\t\tsocket_stats->heap_freesz_bytes);\n\tsocket_stats->alloc_count = heap->alloc_count;\n\treturn 0;\n}\n\nint\nrte_eal_malloc_heap_init(void)\n{\n\tstruct rte_mem_config *mcfg = rte_eal_get_configuration()->mem_config;\n\tunsigned ms_cnt;\n\tstruct rte_memseg *ms;\n\n\tif (mcfg == NULL)\n\t\treturn -1;\n\n\tfor (ms = &mcfg->memseg[0], ms_cnt = 0;\n\t\t\t(ms_cnt < RTE_MAX_MEMSEG) && (ms->len > 0);\n\t\t\tms_cnt++, ms++) {\n#ifdef RTE_LIBRTE_IVSHMEM\n\t\t/*\n\t\t * if segment has ioremap address set, it's an IVSHMEM segment and\n\t\t * it is not memory to allocate from.\n\t\t */\n\t\tif (ms->ioremap_addr != 0)\n\t\t\tcontinue;\n#endif\n\t\tmalloc_heap_add_memseg(&mcfg->malloc_heaps[ms->socket_id], ms);\n\t}\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/common/malloc_heap.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef MALLOC_HEAP_H_\n#define MALLOC_HEAP_H_\n\n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstatic inline unsigned\nmalloc_get_numa_socket(void)\n{\n\tunsigned socket_id = rte_socket_id();\n\n\tif (socket_id == (unsigned)SOCKET_ID_ANY)\n\t\treturn 0;\n\n\treturn socket_id;\n}\n\nvoid *\nmalloc_heap_alloc(struct malloc_heap *heap,\tconst char *type, size_t size,\n\t\tunsigned flags, size_t align, size_t bound);\n\nint\nmalloc_heap_get_stats(const struct malloc_heap *heap,\n\t\tstruct rte_malloc_socket_stats *socket_stats);\n\nint\nrte_eal_malloc_heap_init(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* MALLOC_HEAP_H_ */\n" }, { "path": "lib/librte_eal/common/rte_malloc.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \"malloc_elem.h\"\n#include \"malloc_heap.h\"\n\n\n/* Free the memory space back to heap */\nvoid rte_free(void *addr)\n{\n\tif (addr == NULL) return;\n\tif (malloc_elem_free(malloc_elem_from_data(addr)) < 0)\n\t\trte_panic(\"Fatal error: Invalid memory\\n\");\n}\n\n/*\n * Allocate memory on specified heap.\n */\nvoid *\nrte_malloc_socket(const char *type, size_t size, unsigned align, int socket_arg)\n{\n\tstruct rte_mem_config *mcfg = rte_eal_get_configuration()->mem_config;\n\tint socket, i;\n\tvoid *ret;\n\n\t/* return NULL if size is 0 or alignment is not power-of-2 */\n\tif (size == 0 || (align && !rte_is_power_of_2(align)))\n\t\treturn NULL;\n\n\tif (!rte_eal_has_hugepages())\n\t\tsocket_arg = SOCKET_ID_ANY;\n\n\tif (socket_arg == SOCKET_ID_ANY)\n\t\tsocket = malloc_get_numa_socket();\n\telse\n\t\tsocket = socket_arg;\n\n\t/* Check socket parameter */\n\tif (socket >= RTE_MAX_NUMA_NODES)\n\t\treturn NULL;\n\n\tret = malloc_heap_alloc(&mcfg->malloc_heaps[socket], type,\n\t\t\t\tsize, 0, align == 0 ? 1 : align, 0);\n\tif (ret != NULL || socket_arg != SOCKET_ID_ANY)\n\t\treturn ret;\n\n\t/* try other heaps */\n\tfor (i = 0; i < RTE_MAX_NUMA_NODES; i++) {\n\t\t/* we already tried this one */\n\t\tif (i == socket)\n\t\t\tcontinue;\n\n\t\tret = malloc_heap_alloc(&mcfg->malloc_heaps[i], type,\n\t\t\t\t\tsize, 0, align == 0 ? 1 : align, 0);\n\t\tif (ret != NULL)\n\t\t\treturn ret;\n\t}\n\n\treturn NULL;\n}\n\n/*\n * Allocate memory on default heap.\n */\nvoid *\nrte_malloc(const char *type, size_t size, unsigned align)\n{\n\treturn rte_malloc_socket(type, size, align, SOCKET_ID_ANY);\n}\n\n/*\n * Allocate zero'd memory on specified heap.\n */\nvoid *\nrte_zmalloc_socket(const char *type, size_t size, unsigned align, int socket)\n{\n\tvoid *ptr = rte_malloc_socket(type, size, align, socket);\n\n\tif (ptr != NULL)\n\t\tmemset(ptr, 0, size);\n\treturn ptr;\n}\n\n/*\n * Allocate zero'd memory on default heap.\n */\nvoid *\nrte_zmalloc(const char *type, size_t size, unsigned align)\n{\n\treturn rte_zmalloc_socket(type, size, align, SOCKET_ID_ANY);\n}\n\n/*\n * Allocate zero'd memory on specified heap.\n */\nvoid *\nrte_calloc_socket(const char *type, size_t num, size_t size, unsigned align, int socket)\n{\n\treturn rte_zmalloc_socket(type, num * size, align, socket);\n}\n\n/*\n * Allocate zero'd memory on default heap.\n */\nvoid *\nrte_calloc(const char *type, size_t num, size_t size, unsigned align)\n{\n\treturn rte_zmalloc(type, num * size, align);\n}\n\n/*\n * Resize allocated memory.\n */\nvoid *\nrte_realloc(void *ptr, size_t size, unsigned align)\n{\n\tif (ptr == NULL)\n\t\treturn rte_malloc(NULL, size, align);\n\n\tstruct malloc_elem *elem = malloc_elem_from_data(ptr);\n\tif (elem == NULL)\n\t\trte_panic(\"Fatal error: memory corruption detected\\n\");\n\n\tsize = RTE_CACHE_LINE_ROUNDUP(size), align = RTE_CACHE_LINE_ROUNDUP(align);\n\t/* check alignment matches first, and if ok, see if we can resize block */\n\tif (RTE_PTR_ALIGN(ptr,align) == ptr &&\n\t\t\tmalloc_elem_resize(elem, size) == 0)\n\t\treturn ptr;\n\n\t/* either alignment is off, or we have no room to expand,\n\t * so move data. */\n\tvoid *new_ptr = rte_malloc(NULL, size, align);\n\tif (new_ptr == NULL)\n\t\treturn NULL;\n\tconst unsigned old_size = elem->size - MALLOC_ELEM_OVERHEAD;\n\trte_memcpy(new_ptr, ptr, old_size < size ? old_size : size);\n\trte_free(ptr);\n\n\treturn new_ptr;\n}\n\nint\nrte_malloc_validate(const void *ptr, size_t *size)\n{\n\tconst struct malloc_elem *elem = malloc_elem_from_data(ptr);\n\tif (!malloc_elem_cookies_ok(elem))\n\t\treturn -1;\n\tif (size != NULL)\n\t\t*size = elem->size - elem->pad - MALLOC_ELEM_OVERHEAD;\n\treturn 0;\n}\n\n/*\n * Function to retrieve data for heap on given socket\n */\nint\nrte_malloc_get_socket_stats(int socket,\n\t\tstruct rte_malloc_socket_stats *socket_stats)\n{\n\tstruct rte_mem_config *mcfg = rte_eal_get_configuration()->mem_config;\n\n\tif (socket >= RTE_MAX_NUMA_NODES || socket < 0)\n\t\treturn -1;\n\n\treturn malloc_heap_get_stats(&mcfg->malloc_heaps[socket], socket_stats);\n}\n\n/*\n * Print stats on memory type. If type is NULL, info on all types is printed\n */\nvoid\nrte_malloc_dump_stats(FILE *f, __rte_unused const char *type)\n{\n\tunsigned int socket;\n\tstruct rte_malloc_socket_stats sock_stats;\n\t/* Iterate through all initialised heaps */\n\tfor (socket=0; socket< RTE_MAX_NUMA_NODES; socket++) {\n\t\tif ((rte_malloc_get_socket_stats(socket, &sock_stats) < 0))\n\t\t\tcontinue;\n\n\t\tfprintf(f, \"Socket:%u\\n\", socket);\n\t\tfprintf(f, \"\\tHeap_size:%zu,\\n\", sock_stats.heap_totalsz_bytes);\n\t\tfprintf(f, \"\\tFree_size:%zu,\\n\", sock_stats.heap_freesz_bytes);\n\t\tfprintf(f, \"\\tAlloc_size:%zu,\\n\", sock_stats.heap_allocsz_bytes);\n\t\tfprintf(f, \"\\tGreatest_free_size:%zu,\\n\",\n\t\t\t\tsock_stats.greatest_free_size);\n\t\tfprintf(f, \"\\tAlloc_count:%u,\\n\",sock_stats.alloc_count);\n\t\tfprintf(f, \"\\tFree_count:%u,\\n\", sock_stats.free_count);\n\t}\n\treturn;\n}\n\n/*\n * TODO: Set limit to memory that can be allocated to memory type\n */\nint\nrte_malloc_set_limit(__rte_unused const char *type,\n\t\t__rte_unused size_t max)\n{\n\treturn 0;\n}\n\n/*\n * Return the physical address of a virtual address obtained through rte_malloc\n */\nphys_addr_t\nrte_malloc_virt2phy(const void *addr)\n{\n\tconst struct malloc_elem *elem = malloc_elem_from_data(addr);\n\tif (elem == NULL)\n\t\treturn 0;\n\treturn elem->ms->phys_addr + ((uintptr_t)addr - (uintptr_t)elem->ms->addr);\n}\n" }, { "path": "lib/librte_eal/linuxapp/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nifeq ($(CONFIG_RTE_EAL_IGB_UIO),y)\nDIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += igb_uio\nendif\nDIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal\nifeq ($(CONFIG_RTE_KNI_KMOD),y)\nDIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += kni\nendif\nifeq ($(CONFIG_RTE_LIBRTE_XEN_DOM0),y)\nDIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += xen_dom0\nendif\n\ninclude $(RTE_SDK)/mk/rte.subdir.mk\n" }, { "path": "lib/librte_eal/linuxapp/eal/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nLIB = librte_eal.a\n\nEXPORT_MAP := rte_eal_version.map\n\nLIBABIVER := 1\n\nVPATH += $(RTE_SDK)/lib/librte_eal/common\n\nCFLAGS += -I$(SRCDIR)/include\nCFLAGS += -I$(RTE_SDK)/lib/librte_eal/common\nCFLAGS += -I$(RTE_SDK)/lib/librte_eal/common/include\nCFLAGS += -I$(RTE_SDK)/lib/librte_ring\nCFLAGS += -I$(RTE_SDK)/lib/librte_mempool\nCFLAGS += -I$(RTE_SDK)/lib/librte_ivshmem\nCFLAGS += $(WERROR_FLAGS) -O3\n\n# specific to linuxapp exec-env\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) := eal.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_hugepage_info.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_memory.c\nifeq ($(CONFIG_RTE_LIBRTE_XEN_DOM0),y)\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_xen_memory.c\nendif\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_thread.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_log.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_pci.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_pci_uio.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_pci_vfio.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_pci_vfio_mp_sync.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_debug.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_lcore.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_timer.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_interrupts.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_alarm.c\nifeq ($(CONFIG_RTE_LIBRTE_IVSHMEM),y)\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_ivshmem.c\nendif\n\n# from common dir\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_lcore.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_timer.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_memzone.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_log.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_launch.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_pci.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_pci_uio.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_memory.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_tailqs.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_errno.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_cpuflags.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_string_fns.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_hexdump.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_devargs.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_dev.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_options.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += eal_common_thread.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += rte_malloc.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += malloc_elem.c\nSRCS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += malloc_heap.c\n\nCFLAGS_eal.o := -D_GNU_SOURCE\nCFLAGS_eal_interrupts.o := -D_GNU_SOURCE\nCFLAGS_eal_lcore.o := -D_GNU_SOURCE\nCFLAGS_eal_thread.o := -D_GNU_SOURCE\nCFLAGS_eal_log.o := -D_GNU_SOURCE\nCFLAGS_eal_common_log.o := -D_GNU_SOURCE\nCFLAGS_eal_hugepage_info.o := -D_GNU_SOURCE\nCFLAGS_eal_pci.o := -D_GNU_SOURCE\nCFLAGS_eal_pci_uio.o := -D_GNU_SOURCE\nCFLAGS_eal_pci_vfio.o := -D_GNU_SOURCE\nCFLAGS_eal_common_whitelist.o := -D_GNU_SOURCE\nCFLAGS_eal_common_options.o := -D_GNU_SOURCE\nCFLAGS_eal_common_thread.o := -D_GNU_SOURCE\nCFLAGS_eal_common_lcore.o := -D_GNU_SOURCE\n\n# workaround for a gcc bug with noreturn attribute\n# http://gcc.gnu.org/bugzilla/show_bug.cgi?id=12603\nifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y)\nCFLAGS_eal_thread.o += -Wno-return-type\nendif\n\nINC := rte_interrupts.h rte_kni_common.h rte_dom0_common.h\n\nSYMLINK-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP)-include/exec-env := \\\n\t$(addprefix include/exec-env/,$(INC))\n\nDEPDIRS-$(CONFIG_RTE_LIBRTE_EAL_LINUXAPP) += lib/librte_eal/common\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2012-2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686)\n#include \n#endif\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_thread.h\"\n#include \"eal_internal_cfg.h\"\n#include \"eal_filesystem.h\"\n#include \"eal_hugepages.h\"\n#include \"eal_options.h\"\n\n#define MEMSIZE_IF_NO_HUGE_PAGE (64ULL * 1024ULL * 1024ULL)\n\n#define SOCKET_MEM_STRLEN (RTE_MAX_NUMA_NODES * 10)\n\n/* Allow the application to print its usage message too if set */\nstatic rte_usage_hook_t\trte_application_usage_hook = NULL;\n\nTAILQ_HEAD(shared_driver_list, shared_driver);\n\n/* Definition for shared object drivers. */\nstruct shared_driver {\n\tTAILQ_ENTRY(shared_driver) next;\n\n\tchar name[PATH_MAX];\n\tvoid* lib_handle;\n};\n\n/* List of external loadable drivers */\nstatic struct shared_driver_list solib_list =\nTAILQ_HEAD_INITIALIZER(solib_list);\n\n/* early configuration structure, when memory config is not mmapped */\nstatic struct rte_mem_config early_mem_config;\n\n/* define fd variable here, because file needs to be kept open for the\n * duration of the program, as we hold a write lock on it in the primary proc */\nstatic int mem_cfg_fd = -1;\n\nstatic struct flock wr_lock = {\n\t\t.l_type = F_WRLCK,\n\t\t.l_whence = SEEK_SET,\n\t\t.l_start = offsetof(struct rte_mem_config, memseg),\n\t\t.l_len = sizeof(early_mem_config.memseg),\n};\n\n/* Address of global and public configuration */\nstatic struct rte_config rte_config = {\n\t\t.mem_config = &early_mem_config,\n};\n\n/* internal configuration (per-core) */\nstruct lcore_config lcore_config[RTE_MAX_LCORE];\n\n/* internal configuration */\nstruct internal_config internal_config;\n\n/* used by rte_rdtsc() */\nint rte_cycles_vmware_tsc_map;\n\n/* Return a pointer to the configuration structure */\nstruct rte_config *\nrte_eal_get_configuration(void)\n{\n\treturn &rte_config;\n}\n\n/* parse a sysfs (or other) file containing one integer value */\nint\neal_parse_sysfs_value(const char *filename, unsigned long *val)\n{\n\tFILE *f;\n\tchar buf[BUFSIZ];\n\tchar *end = NULL;\n\n\tif ((f = fopen(filename, \"r\")) == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot open sysfs value %s\\n\",\n\t\t\t__func__, filename);\n\t\treturn -1;\n\t}\n\n\tif (fgets(buf, sizeof(buf), f) == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot read sysfs value %s\\n\",\n\t\t\t__func__, filename);\n\t\tfclose(f);\n\t\treturn -1;\n\t}\n\t*val = strtoul(buf, &end, 0);\n\tif ((buf[0] == '\\0') || (end == NULL) || (*end != '\\n')) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot parse sysfs value %s\\n\",\n\t\t\t\t__func__, filename);\n\t\tfclose(f);\n\t\treturn -1;\n\t}\n\tfclose(f);\n\treturn 0;\n}\n\n\n/* create memory configuration in shared/mmap memory. Take out\n * a write lock on the memsegs, so we can auto-detect primary/secondary.\n * This means we never close the file while running (auto-close on exit).\n * We also don't lock the whole file, so that in future we can use read-locks\n * on other parts, e.g. memzones, to detect if there are running secondary\n * processes. */\nstatic void\nrte_eal_config_create(void)\n{\n\tvoid *rte_mem_cfg_addr;\n\tint retval;\n\n\tconst char *pathname = eal_runtime_config_path();\n\n\tif (internal_config.no_shconf)\n\t\treturn;\n\n\t/* map the config before hugepage address so that we don't waste a page */\n\tif (internal_config.base_virtaddr != 0)\n\t\trte_mem_cfg_addr = (void *)\n\t\t\tRTE_ALIGN_FLOOR(internal_config.base_virtaddr -\n\t\t\tsizeof(struct rte_mem_config), sysconf(_SC_PAGE_SIZE));\n\telse\n\t\trte_mem_cfg_addr = NULL;\n\n\tif (mem_cfg_fd < 0){\n\t\tmem_cfg_fd = open(pathname, O_RDWR | O_CREAT, 0660);\n\t\tif (mem_cfg_fd < 0)\n\t\t\trte_panic(\"Cannot open '%s' for rte_mem_config\\n\", pathname);\n\t}\n\n\tretval = ftruncate(mem_cfg_fd, sizeof(*rte_config.mem_config));\n\tif (retval < 0){\n\t\tclose(mem_cfg_fd);\n\t\trte_panic(\"Cannot resize '%s' for rte_mem_config\\n\", pathname);\n\t}\n\n\tretval = fcntl(mem_cfg_fd, F_SETLK, &wr_lock);\n\tif (retval < 0){\n\t\tclose(mem_cfg_fd);\n\t\trte_exit(EXIT_FAILURE, \"Cannot create lock on '%s'. Is another primary \"\n\t\t\t\t\"process running?\\n\", pathname);\n\t}\n\n\trte_mem_cfg_addr = mmap(rte_mem_cfg_addr, sizeof(*rte_config.mem_config),\n\t\t\t\tPROT_READ | PROT_WRITE, MAP_SHARED, mem_cfg_fd, 0);\n\n\tif (rte_mem_cfg_addr == MAP_FAILED){\n\t\trte_panic(\"Cannot mmap memory for rte_config\\n\");\n\t}\n\tmemcpy(rte_mem_cfg_addr, &early_mem_config, sizeof(early_mem_config));\n\trte_config.mem_config = (struct rte_mem_config *) rte_mem_cfg_addr;\n\n\t/* store address of the config in the config itself so that secondary\n\t * processes could later map the config into this exact location */\n\trte_config.mem_config->mem_cfg_addr = (uintptr_t) rte_mem_cfg_addr;\n\n}\n\n/* attach to an existing shared memory config */\nstatic void\nrte_eal_config_attach(void)\n{\n\tstruct rte_mem_config *mem_config;\n\n\tconst char *pathname = eal_runtime_config_path();\n\n\tif (internal_config.no_shconf)\n\t\treturn;\n\n\tif (mem_cfg_fd < 0){\n\t\tmem_cfg_fd = open(pathname, O_RDWR);\n\t\tif (mem_cfg_fd < 0)\n\t\t\trte_panic(\"Cannot open '%s' for rte_mem_config\\n\", pathname);\n\t}\n\n\t/* map it as read-only first */\n\tmem_config = (struct rte_mem_config *) mmap(NULL, sizeof(*mem_config),\n\t\t\tPROT_READ, MAP_SHARED, mem_cfg_fd, 0);\n\tif (mem_config == MAP_FAILED)\n\t\trte_panic(\"Cannot mmap memory for rte_config\\n\");\n\n\trte_config.mem_config = mem_config;\n}\n\n/* reattach the shared config at exact memory location primary process has it */\nstatic void\nrte_eal_config_reattach(void)\n{\n\tstruct rte_mem_config *mem_config;\n\tvoid *rte_mem_cfg_addr;\n\n\tif (internal_config.no_shconf)\n\t\treturn;\n\n\t/* save the address primary process has mapped shared config to */\n\trte_mem_cfg_addr = (void *) (uintptr_t) rte_config.mem_config->mem_cfg_addr;\n\n\t/* unmap original config */\n\tmunmap(rte_config.mem_config, sizeof(struct rte_mem_config));\n\n\t/* remap the config at proper address */\n\tmem_config = (struct rte_mem_config *) mmap(rte_mem_cfg_addr,\n\t\t\tsizeof(*mem_config), PROT_READ | PROT_WRITE, MAP_SHARED,\n\t\t\tmem_cfg_fd, 0);\n\tclose(mem_cfg_fd);\n\tif (mem_config == MAP_FAILED || mem_config != rte_mem_cfg_addr)\n\t\trte_panic(\"Cannot mmap memory for rte_config\\n\");\n\n\trte_config.mem_config = mem_config;\n}\n\n/* Detect if we are a primary or a secondary process */\nenum rte_proc_type_t\neal_proc_type_detect(void)\n{\n\tenum rte_proc_type_t ptype = RTE_PROC_PRIMARY;\n\tconst char *pathname = eal_runtime_config_path();\n\n\t/* if we can open the file but not get a write-lock we are a secondary\n\t * process. NOTE: if we get a file handle back, we keep that open\n\t * and don't close it to prevent a race condition between multiple opens */\n\tif (((mem_cfg_fd = open(pathname, O_RDWR)) >= 0) &&\n\t\t\t(fcntl(mem_cfg_fd, F_SETLK, &wr_lock) < 0))\n\t\tptype = RTE_PROC_SECONDARY;\n\n\tRTE_LOG(INFO, EAL, \"Auto-detected process type: %s\\n\",\n\t\t\tptype == RTE_PROC_PRIMARY ? \"PRIMARY\" : \"SECONDARY\");\n\n\treturn ptype;\n}\n\n/* Sets up rte_config structure with the pointer to shared memory config.*/\nstatic void\nrte_config_init(void)\n{\n\trte_config.process_type = internal_config.process_type;\n\n\tswitch (rte_config.process_type){\n\tcase RTE_PROC_PRIMARY:\n\t\trte_eal_config_create();\n\t\tbreak;\n\tcase RTE_PROC_SECONDARY:\n\t\trte_eal_config_attach();\n\t\trte_eal_mcfg_wait_complete(rte_config.mem_config);\n\t\trte_eal_config_reattach();\n\t\tbreak;\n\tcase RTE_PROC_AUTO:\n\tcase RTE_PROC_INVALID:\n\t\trte_panic(\"Invalid process type\\n\");\n\t}\n}\n\n/* Unlocks hugepage directories that were locked by eal_hugepage_info_init */\nstatic void\neal_hugedirs_unlock(void)\n{\n\tint i;\n\n\tfor (i = 0; i < MAX_HUGEPAGE_SIZES; i++)\n\t{\n\t\t/* skip uninitialized */\n\t\tif (internal_config.hugepage_info[i].lock_descriptor < 0)\n\t\t\tcontinue;\n\t\t/* unlock hugepage file */\n\t\tflock(internal_config.hugepage_info[i].lock_descriptor, LOCK_UN);\n\t\tclose(internal_config.hugepage_info[i].lock_descriptor);\n\t\t/* reset the field */\n\t\tinternal_config.hugepage_info[i].lock_descriptor = -1;\n\t}\n}\n\n/* display usage */\nstatic void\neal_usage(const char *prgname)\n{\n\tprintf(\"\\nUsage: %s \", prgname);\n\teal_common_usage();\n\tprintf(\"EAL Linux options:\\n\"\n\t \" -d LIB.so Add driver (can be used multiple times)\\n\"\n\t \" --\"OPT_SOCKET_MEM\" Memory to allocate on sockets (comma separated values)\\n\"\n\t \" --\"OPT_HUGE_DIR\" Directory where hugetlbfs is mounted\\n\"\n\t \" --\"OPT_FILE_PREFIX\" Prefix for hugepage filenames\\n\"\n\t \" --\"OPT_BASE_VIRTADDR\" Base virtual address\\n\"\n\t \" --\"OPT_CREATE_UIO_DEV\" Create /dev/uioX (usually done by hotplug)\\n\"\n\t \" --\"OPT_VFIO_INTR\" Interrupt mode for VFIO (legacy|msi|msix)\\n\"\n\t \" --\"OPT_XEN_DOM0\" Support running on Xen dom0 without hugetlbfs\\n\"\n\t \"\\n\");\n\t/* Allow the application to print its usage message too if hook is set */\n\tif ( rte_application_usage_hook ) {\n\t\tprintf(\"===== Application Usage =====\\n\\n\");\n\t\trte_application_usage_hook(prgname);\n\t}\n}\n\n/* Set a per-application usage message */\nrte_usage_hook_t\nrte_set_application_usage_hook( rte_usage_hook_t usage_func )\n{\n\trte_usage_hook_t\told_func;\n\n\t/* Will be NULL on the first call to denote the last usage routine. */\n\told_func\t\t\t\t\t= rte_application_usage_hook;\n\trte_application_usage_hook\t= usage_func;\n\n\treturn old_func;\n}\n\nstatic int\neal_parse_socket_mem(char *socket_mem)\n{\n\tchar * arg[RTE_MAX_NUMA_NODES];\n\tchar *end;\n\tint arg_num, i, len;\n\tuint64_t total_mem = 0;\n\n\tlen = strnlen(socket_mem, SOCKET_MEM_STRLEN);\n\tif (len == SOCKET_MEM_STRLEN) {\n\t\tRTE_LOG(ERR, EAL, \"--socket-mem is too long\\n\");\n\t\treturn -1;\n\t}\n\n\t/* all other error cases will be caught later */\n\tif (!isdigit(socket_mem[len-1]))\n\t\treturn -1;\n\n\t/* split the optarg into separate socket values */\n\targ_num = rte_strsplit(socket_mem, len,\n\t\t\targ, RTE_MAX_NUMA_NODES, ',');\n\n\t/* if split failed, or 0 arguments */\n\tif (arg_num <= 0)\n\t\treturn -1;\n\n\tinternal_config.force_sockets = 1;\n\n\t/* parse each defined socket option */\n\terrno = 0;\n\tfor (i = 0; i < arg_num; i++) {\n\t\tend = NULL;\n\t\tinternal_config.socket_mem[i] = strtoull(arg[i], &end, 10);\n\n\t\t/* check for invalid input */\n\t\tif ((errno != 0) ||\n\t\t\t\t(arg[i][0] == '\\0') || (end == NULL) || (*end != '\\0'))\n\t\t\treturn -1;\n\t\tinternal_config.socket_mem[i] *= 1024ULL;\n\t\tinternal_config.socket_mem[i] *= 1024ULL;\n\t\ttotal_mem += internal_config.socket_mem[i];\n\t}\n\n\t/* check if we have a positive amount of total memory */\n\tif (total_mem == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic int\neal_parse_base_virtaddr(const char *arg)\n{\n\tchar *end;\n\tuint64_t addr;\n\n\terrno = 0;\n\taddr = strtoull(arg, &end, 16);\n\n\t/* check for errors */\n\tif ((errno != 0) || (arg[0] == '\\0') || end == NULL || (*end != '\\0'))\n\t\treturn -1;\n\n\t/* make sure we don't exceed 32-bit boundary on 32-bit target */\n#ifndef RTE_ARCH_64\n\tif (addr >= UINTPTR_MAX)\n\t\treturn -1;\n#endif\n\n\t/* align the addr on 16M boundary, 16MB is the minimum huge page\n\t * size on IBM Power architecture. If the addr is aligned to 16MB,\n\t * it can align to 2MB for x86. So this alignment can also be used\n\t * on x86 */\n\tinternal_config.base_virtaddr =\n\t\tRTE_PTR_ALIGN_CEIL((uintptr_t)addr, (size_t)RTE_PGSIZE_16M);\n\n\treturn 0;\n}\n\nstatic int\neal_parse_vfio_intr(const char *mode)\n{\n\tunsigned i;\n\tstatic struct {\n\t\tconst char *name;\n\t\tenum rte_intr_mode value;\n\t} map[] = {\n\t\t{ \"legacy\", RTE_INTR_MODE_LEGACY },\n\t\t{ \"msi\", RTE_INTR_MODE_MSI },\n\t\t{ \"msix\", RTE_INTR_MODE_MSIX },\n\t};\n\n\tfor (i = 0; i < RTE_DIM(map); i++) {\n\t\tif (!strcmp(mode, map[i].name)) {\n\t\t\tinternal_config.vfio_intr_mode = map[i].value;\n\t\t\treturn 0;\n\t\t}\n\t}\n\treturn -1;\n}\n\nstatic inline size_t\neal_get_hugepage_mem_size(void)\n{\n\tuint64_t size = 0;\n\tunsigned i, j;\n\n\tfor (i = 0; i < internal_config.num_hugepage_sizes; i++) {\n\t\tstruct hugepage_info *hpi = &internal_config.hugepage_info[i];\n\t\tif (hpi->hugedir != NULL) {\n\t\t\tfor (j = 0; j < RTE_MAX_NUMA_NODES; j++) {\n\t\t\t\tsize += hpi->hugepage_sz * hpi->num_pages[j];\n\t\t\t}\n\t\t}\n\t}\n\n\treturn (size < SIZE_MAX) ? (size_t)(size) : SIZE_MAX;\n}\n\n/* Parse the arguments for --log-level only */\nstatic void\neal_log_level_parse(int argc, char **argv)\n{\n\tint opt;\n\tchar **argvopt;\n\tint option_index;\n\n\targvopt = argv;\n\n\teal_reset_internal_config(&internal_config);\n\n\twhile ((opt = getopt_long(argc, argvopt, eal_short_options,\n\t\t\t\t eal_long_options, &option_index)) != EOF) {\n\n\t\tint ret;\n\n\t\t/* getopt is not happy, stop right now */\n\t\tif (opt == '?')\n\t\t\tbreak;\n\n\t\tret = (opt == OPT_LOG_LEVEL_NUM) ?\n\t\t\teal_parse_common_option(opt, optarg, &internal_config) : 0;\n\n\t\t/* common parser is not happy */\n\t\tif (ret < 0)\n\t\t\tbreak;\n\t}\n\n\toptind = 0; /* reset getopt lib */\n}\n\n/* Parse the argument given in the command line of the application */\nstatic int\neal_parse_args(int argc, char **argv)\n{\n\tint opt, ret;\n\tchar **argvopt;\n\tint option_index;\n\tchar *prgname = argv[0];\n\tstruct shared_driver *solib;\n\n\targvopt = argv;\n\n\twhile ((opt = getopt_long(argc, argvopt, eal_short_options,\n\t\t\t\t eal_long_options, &option_index)) != EOF) {\n\n\t\tint ret;\n\n\t\t/* getopt is not happy, stop right now */\n\t\tif (opt == '?') {\n\t\t\teal_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\n\t\tret = eal_parse_common_option(opt, optarg, &internal_config);\n\t\t/* common parser is not happy */\n\t\tif (ret < 0) {\n\t\t\teal_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t\t/* common parser handled this option */\n\t\tif (ret == 0)\n\t\t\tcontinue;\n\n\t\tswitch (opt) {\n\t\tcase 'h':\n\t\t\teal_usage(prgname);\n\t\t\texit(EXIT_SUCCESS);\n\n\t\t/* force loading of external driver */\n\t\tcase 'd':\n\t\t\tsolib = malloc(sizeof(*solib));\n\t\t\tif (solib == NULL) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"malloc(solib) failed\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tmemset(solib, 0, sizeof(*solib));\n\t\t\tstrncpy(solib->name, optarg, PATH_MAX-1);\n\t\t\tsolib->name[PATH_MAX-1] = 0;\n\t\t\tTAILQ_INSERT_TAIL(&solib_list, solib, next);\n\t\t\tbreak;\n\n\t\t/* long options */\n\t\tcase OPT_XEN_DOM0_NUM:\n#ifdef RTE_LIBRTE_XEN_DOM0\n\t\t\tinternal_config.xen_dom0_support = 1;\n#else\n\t\t\tRTE_LOG(ERR, EAL, \"Can't support DPDK app \"\n\t\t\t\t\"running on Dom0, please configure\"\n\t\t\t\t\" RTE_LIBRTE_XEN_DOM0=y\\n\");\n\t\t\treturn -1;\n#endif\n\t\t\tbreak;\n\n\t\tcase OPT_HUGE_DIR_NUM:\n\t\t\tinternal_config.hugepage_dir = optarg;\n\t\t\tbreak;\n\n\t\tcase OPT_FILE_PREFIX_NUM:\n\t\t\tinternal_config.hugefile_prefix = optarg;\n\t\t\tbreak;\n\n\t\tcase OPT_SOCKET_MEM_NUM:\n\t\t\tif (eal_parse_socket_mem(optarg) < 0) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"invalid parameters for --\"\n\t\t\t\t\t\tOPT_SOCKET_MEM \"\\n\");\n\t\t\t\teal_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase OPT_BASE_VIRTADDR_NUM:\n\t\t\tif (eal_parse_base_virtaddr(optarg) < 0) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"invalid parameter for --\"\n\t\t\t\t\t\tOPT_BASE_VIRTADDR \"\\n\");\n\t\t\t\teal_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase OPT_VFIO_INTR_NUM:\n\t\t\tif (eal_parse_vfio_intr(optarg) < 0) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"invalid parameters for --\"\n\t\t\t\t\t\tOPT_VFIO_INTR \"\\n\");\n\t\t\t\teal_usage(prgname);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tbreak;\n\n\t\tcase OPT_CREATE_UIO_DEV_NUM:\n\t\t\tinternal_config.create_uio_dev = 1;\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tif (opt < OPT_LONG_MIN_NUM && isprint(opt)) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Option %c is not supported \"\n\t\t\t\t\t\"on Linux\\n\", opt);\n\t\t\t} else if (opt >= OPT_LONG_MIN_NUM &&\n\t\t\t\t opt < OPT_LONG_MAX_NUM) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Option %s is not supported \"\n\t\t\t\t\t\"on Linux\\n\",\n\t\t\t\t\teal_long_options[option_index].name);\n\t\t\t} else {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Option %d is not supported \"\n\t\t\t\t\t\"on Linux\\n\", opt);\n\t\t\t}\n\t\t\teal_usage(prgname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tif (eal_adjust_config(&internal_config) != 0)\n\t\treturn -1;\n\n\t/* sanity checks */\n\tif (eal_check_common_options(&internal_config) != 0) {\n\t\teal_usage(prgname);\n\t\treturn -1;\n\t}\n\n\t/* --xen-dom0 doesn't make sense with --socket-mem */\n\tif (internal_config.xen_dom0_support && internal_config.force_sockets == 1) {\n\t\tRTE_LOG(ERR, EAL, \"Options --\"OPT_SOCKET_MEM\" cannot be specified \"\n\t\t\t\"together with --\"OPT_XEN_DOM0\"\\n\");\n\t\teal_usage(prgname);\n\t\treturn -1;\n\t}\n\n\tif (optind >= 0)\n\t\targv[optind-1] = prgname;\n\tret = optind-1;\n\toptind = 0; /* reset getopt lib */\n\treturn ret;\n}\n\nstatic void\neal_check_mem_on_local_socket(void)\n{\n\tconst struct rte_memseg *ms;\n\tint i, socket_id;\n\n\tsocket_id = rte_lcore_to_socket_id(rte_config.master_lcore);\n\n\tms = rte_eal_get_physmem_layout();\n\n\tfor (i = 0; i < RTE_MAX_MEMSEG; i++)\n\t\tif (ms[i].socket_id == socket_id &&\n\t\t\t\tms[i].len > 0)\n\t\t\treturn;\n\n\tRTE_LOG(WARNING, EAL, \"WARNING: Master core has no \"\n\t\t\t\"memory on local socket!\\n\");\n}\n\nstatic int\nsync_func(__attribute__((unused)) void *arg)\n{\n\treturn 0;\n}\n\ninline static void\nrte_eal_mcfg_complete(void)\n{\n\t/* ALL shared mem_config related INIT DONE */\n\tif (rte_config.process_type == RTE_PROC_PRIMARY)\n\t\trte_config.mem_config->magic = RTE_MAGIC;\n}\n\n/*\n * Request iopl privilege for all RPL, returns 0 on success\n * iopl() call is mostly for the i386 architecture. For other architectures,\n * return -1 to indicate IO privilege can't be changed in this way.\n */\nint\nrte_eal_iopl_init(void)\n{\n#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686)\n\tif (iopl(3) != 0)\n\t\treturn -1;\n\treturn 0;\n#else\n\treturn -1;\n#endif\n}\n\n/* Launch threads, called at application init(). */\nint\nrte_eal_init(int argc, char **argv)\n{\n\tint i, fctret, ret;\n\tpthread_t thread_id;\n\tstatic rte_atomic32_t run_once = RTE_ATOMIC32_INIT(0);\n\tstruct shared_driver *solib = NULL;\n\tconst char *logid;\n\tchar cpuset[RTE_CPU_AFFINITY_STR_LEN];\n\n\tif (!rte_atomic32_test_and_set(&run_once))\n\t\treturn -1;\n\n\tlogid = strrchr(argv[0], '/');\n\tlogid = strdup(logid ? logid + 1: argv[0]);\n\n\tthread_id = pthread_self();\n\n\tif (rte_eal_log_early_init() < 0)\n\t\trte_panic(\"Cannot init early logs\\n\");\n\n\teal_log_level_parse(argc, argv);\n\n\t/* set log level as early as possible */\n\trte_set_log_level(internal_config.log_level);\n\n\tif (rte_eal_cpu_init() < 0)\n\t\trte_panic(\"Cannot detect lcores\\n\");\n\n\tfctret = eal_parse_args(argc, argv);\n\tif (fctret < 0)\n\t\texit(1);\n\n\tif (internal_config.no_hugetlbfs == 0 &&\n\t\t\tinternal_config.process_type != RTE_PROC_SECONDARY &&\n\t\t\tinternal_config.xen_dom0_support == 0 &&\n\t\t\teal_hugepage_info_init() < 0)\n\t\trte_panic(\"Cannot get hugepage information\\n\");\n\n\tif (internal_config.memory == 0 && internal_config.force_sockets == 0) {\n\t\tif (internal_config.no_hugetlbfs)\n\t\t\tinternal_config.memory = MEMSIZE_IF_NO_HUGE_PAGE;\n\t\telse\n\t\t\tinternal_config.memory = eal_get_hugepage_mem_size();\n\t}\n\n\tif (internal_config.vmware_tsc_map == 1) {\n#ifdef RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT\n\t\trte_cycles_vmware_tsc_map = 1;\n\t\tRTE_LOG (DEBUG, EAL, \"Using VMWARE TSC MAP, \"\n\t\t\t\t\"you must have monitor_control.pseudo_perfctr = TRUE\\n\");\n#else\n\t\tRTE_LOG (WARNING, EAL, \"Ignoring --vmware-tsc-map because \"\n\t\t\t\t\"RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT is not set\\n\");\n#endif\n\t}\n\n\trte_srand(rte_rdtsc());\n\n\trte_config_init();\n\n\tif (rte_eal_pci_init() < 0)\n\t\trte_panic(\"Cannot init PCI\\n\");\n\n#ifdef RTE_LIBRTE_IVSHMEM\n\tif (rte_eal_ivshmem_init() < 0)\n\t\trte_panic(\"Cannot init IVSHMEM\\n\");\n#endif\n\n\tif (rte_eal_memory_init() < 0)\n\t\trte_panic(\"Cannot init memory\\n\");\n\n\t/* the directories are locked during eal_hugepage_info_init */\n\teal_hugedirs_unlock();\n\n\tif (rte_eal_memzone_init() < 0)\n\t\trte_panic(\"Cannot init memzone\\n\");\n\n\tif (rte_eal_tailqs_init() < 0)\n\t\trte_panic(\"Cannot init tail queues for objects\\n\");\n\n#ifdef RTE_LIBRTE_IVSHMEM\n\tif (rte_eal_ivshmem_obj_init() < 0)\n\t\trte_panic(\"Cannot init IVSHMEM objects\\n\");\n#endif\n\n\tif (rte_eal_log_init(logid, internal_config.syslog_facility) < 0)\n\t\trte_panic(\"Cannot init logs\\n\");\n\n\tif (rte_eal_alarm_init() < 0)\n\t\trte_panic(\"Cannot init interrupt-handling thread\\n\");\n\n\tif (rte_eal_intr_init() < 0)\n\t\trte_panic(\"Cannot init interrupt-handling thread\\n\");\n\n\tif (rte_eal_timer_init() < 0)\n\t\trte_panic(\"Cannot init HPET or TSC timers\\n\");\n\n\teal_check_mem_on_local_socket();\n\n\trte_eal_mcfg_complete();\n\n\tTAILQ_FOREACH(solib, &solib_list, next) {\n\t\tRTE_LOG(DEBUG, EAL, \"open shared lib %s\\n\", solib->name);\n\t\tsolib->lib_handle = dlopen(solib->name, RTLD_NOW);\n\t\tif (solib->lib_handle == NULL)\n\t\t\tRTE_LOG(WARNING, EAL, \"%s\\n\", dlerror());\n\t}\n\n\teal_thread_init_master(rte_config.master_lcore);\n\n\tret = eal_thread_dump_affinity(cpuset, RTE_CPU_AFFINITY_STR_LEN);\n\n\tRTE_LOG(DEBUG, EAL, \"Master lcore %u is ready (tid=%x;cpuset=[%s%s])\\n\",\n\t\trte_config.master_lcore, (int)thread_id, cpuset,\n\t\tret == 0 ? \"\" : \"...\");\n\n\tif (rte_eal_dev_init() < 0)\n\t\trte_panic(\"Cannot init pmd devices\\n\");\n\n\tRTE_LCORE_FOREACH_SLAVE(i) {\n\n\t\t/*\n\t\t * create communication pipes between master thread\n\t\t * and children\n\t\t */\n\t\tif (pipe(lcore_config[i].pipe_master2slave) < 0)\n\t\t\trte_panic(\"Cannot create pipe\\n\");\n\t\tif (pipe(lcore_config[i].pipe_slave2master) < 0)\n\t\t\trte_panic(\"Cannot create pipe\\n\");\n\n\t\tlcore_config[i].state = WAIT;\n\n\t\t/* create a thread for each lcore */\n\t\tret = pthread_create(&lcore_config[i].thread_id, NULL,\n\t\t\t\t eal_thread_loop, NULL);\n\t\tif (ret != 0)\n\t\t\trte_panic(\"Cannot create thread\\n\");\n\t}\n\n\t/*\n\t * Launch a dummy function on all slave lcores, so that master lcore\n\t * knows they are all ready when this function returns.\n\t */\n\trte_eal_mp_remote_launch(sync_func, NULL, SKIP_MASTER);\n\trte_eal_mp_wait_lcore();\n\n\t/* Probe & Initialize PCI devices */\n\tif (rte_eal_pci_probe())\n\t\trte_panic(\"Cannot probe PCI\\n\");\n\n\treturn fctret;\n}\n\n/* get core role */\nenum rte_lcore_role_t\nrte_eal_lcore_role(unsigned lcore_id)\n{\n\treturn rte_config.lcore_role[lcore_id];\n}\n\nenum rte_proc_type_t\nrte_eal_process_type(void)\n{\n\treturn rte_config.process_type;\n}\n\nint rte_eal_has_hugepages(void)\n{\n\treturn ! internal_config.no_hugetlbfs;\n}\n\nint\nrte_eal_check_module(const char *module_name)\n{\n\tchar mod_name[30]; /* Any module names can be longer than 30 bytes? */\n\tint ret = 0;\n\tint n;\n\n\tif (NULL == module_name)\n\t\treturn -1;\n\n\tFILE *fd = fopen(\"/proc/modules\", \"r\");\n\tif (NULL == fd) {\n\t\tRTE_LOG(ERR, EAL, \"Open /proc/modules failed!\"\n\t\t\t\" error %i (%s)\\n\", errno, strerror(errno));\n\t\treturn -1;\n\t}\n\twhile (!feof(fd)) {\n\t\tn = fscanf(fd, \"%29s %*[^\\n]\", mod_name);\n\t\tif ((n == 1) && !strcmp(mod_name, module_name)) {\n\t\t\tret = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\tfclose(fd);\n\n\treturn ret;\n}\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_alarm.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#ifndef\tTFD_NONBLOCK\n#include \n#define\tTFD_NONBLOCK\tO_NONBLOCK\n#endif\n\n#define NS_PER_US 1000\n#define US_PER_MS 1000\n#define MS_PER_S 1000\n#define US_PER_S (US_PER_MS * MS_PER_S)\n\nstruct alarm_entry {\n\tLIST_ENTRY(alarm_entry) next;\n\tstruct timeval time;\n\trte_eal_alarm_callback cb_fn;\n\tvoid *cb_arg;\n\tvolatile uint8_t executing;\n\tvolatile pthread_t executing_id;\n};\n\nstatic LIST_HEAD(alarm_list, alarm_entry) alarm_list = LIST_HEAD_INITIALIZER();\nstatic rte_spinlock_t alarm_list_lk = RTE_SPINLOCK_INITIALIZER;\n\nstatic struct rte_intr_handle intr_handle = {.fd = -1 };\nstatic int handler_registered = 0;\nstatic void eal_alarm_callback(struct rte_intr_handle *hdl, void *arg);\n\nint\nrte_eal_alarm_init(void)\n{\n\tintr_handle.type = RTE_INTR_HANDLE_ALARM;\n\t/* create a timerfd file descriptor */\n\tintr_handle.fd = timerfd_create(CLOCK_MONOTONIC, TFD_NONBLOCK);\n\tif (intr_handle.fd == -1)\n\t\tgoto error;\n\n\treturn 0;\n\nerror:\n\trte_errno = errno;\n\treturn -1;\n}\n\nstatic void\neal_alarm_callback(struct rte_intr_handle *hdl __rte_unused,\n\t\tvoid *arg __rte_unused)\n{\n\tstruct timeval now;\n\tstruct alarm_entry *ap;\n\n\trte_spinlock_lock(&alarm_list_lk);\n\twhile ((ap = LIST_FIRST(&alarm_list)) !=NULL &&\n\t\t\tgettimeofday(&now, NULL) == 0 &&\n\t\t\t(ap->time.tv_sec < now.tv_sec || (ap->time.tv_sec == now.tv_sec &&\n\t\t\t\t\t\tap->time.tv_usec <= now.tv_usec))){\n\t\tap->executing = 1;\n\t\tap->executing_id = pthread_self();\n\t\trte_spinlock_unlock(&alarm_list_lk);\n\n\t\tap->cb_fn(ap->cb_arg);\n\n\t\trte_spinlock_lock(&alarm_list_lk);\n\n\t\tLIST_REMOVE(ap, next);\n\t\trte_free(ap);\n\t}\n\n\tif (!LIST_EMPTY(&alarm_list)) {\n\t\tstruct itimerspec atime = { .it_interval = { 0, 0 } };\n\n\t\tap = LIST_FIRST(&alarm_list);\n\t\tatime.it_value.tv_sec = ap->time.tv_sec;\n\t\tatime.it_value.tv_nsec = ap->time.tv_usec * NS_PER_US;\n\t\t/* perform borrow for subtraction if necessary */\n\t\tif (now.tv_usec > ap->time.tv_usec)\n\t\t\tatime.it_value.tv_sec--, atime.it_value.tv_nsec += US_PER_S * NS_PER_US;\n\n\t\tatime.it_value.tv_sec -= now.tv_sec;\n\t\tatime.it_value.tv_nsec -= now.tv_usec * NS_PER_US;\n\t\ttimerfd_settime(intr_handle.fd, 0, &atime, NULL);\n\t}\n\trte_spinlock_unlock(&alarm_list_lk);\n}\n\nint\nrte_eal_alarm_set(uint64_t us, rte_eal_alarm_callback cb_fn, void *cb_arg)\n{\n\tstruct timeval now;\n\tint ret = 0;\n\tstruct alarm_entry *ap, *new_alarm;\n\n\t/* Check parameters, including that us won't cause a uint64_t overflow */\n\tif (us < 1 || us > (UINT64_MAX - US_PER_S) || cb_fn == NULL)\n\t\treturn -EINVAL;\n\n\tnew_alarm = rte_zmalloc(NULL, sizeof(*new_alarm), 0);\n\tif (new_alarm == NULL)\n\t\treturn -ENOMEM;\n\n\t/* use current time to calculate absolute time of alarm */\n\tgettimeofday(&now, NULL);\n\n\tnew_alarm->cb_fn = cb_fn;\n\tnew_alarm->cb_arg = cb_arg;\n\tnew_alarm->time.tv_usec = (now.tv_usec + us) % US_PER_S;\n\tnew_alarm->time.tv_sec = now.tv_sec + ((now.tv_usec + us) / US_PER_S);\n\n\trte_spinlock_lock(&alarm_list_lk);\n\tif (!handler_registered) {\n\t\tret |= rte_intr_callback_register(&intr_handle,\n\t\t\t\teal_alarm_callback, NULL);\n\t\thandler_registered = (ret == 0) ? 1 : 0;\n\t}\n\n\tif (LIST_EMPTY(&alarm_list))\n\t\tLIST_INSERT_HEAD(&alarm_list, new_alarm, next);\n\telse {\n\t\tLIST_FOREACH(ap, &alarm_list, next) {\n\t\t\tif (ap->time.tv_sec > new_alarm->time.tv_sec ||\n\t\t\t\t\t(ap->time.tv_sec == new_alarm->time.tv_sec &&\n\t\t\t\t\t\t\tap->time.tv_usec > new_alarm->time.tv_usec)){\n\t\t\t\tLIST_INSERT_BEFORE(ap, new_alarm, next);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tif (LIST_NEXT(ap, next) == NULL) {\n\t\t\t\tLIST_INSERT_AFTER(ap, new_alarm, next);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (LIST_FIRST(&alarm_list) == new_alarm) {\n\t\tstruct itimerspec alarm_time = {\n\t\t\t.it_interval = {0, 0},\n\t\t\t.it_value = {\n\t\t\t\t.tv_sec = us / US_PER_S,\n\t\t\t\t.tv_nsec = (us % US_PER_S) * NS_PER_US,\n\t\t\t},\n\t\t};\n\t\tret |= timerfd_settime(intr_handle.fd, 0, &alarm_time, NULL);\n\t}\n\trte_spinlock_unlock(&alarm_list_lk);\n\n\treturn ret;\n}\n\nint\nrte_eal_alarm_cancel(rte_eal_alarm_callback cb_fn, void *cb_arg)\n{\n\tstruct alarm_entry *ap, *ap_prev;\n\tint count = 0;\n\tint err = 0;\n\tint executing;\n\n\tif (!cb_fn) {\n\t\trte_errno = EINVAL;\n\t\treturn -1;\n\t}\n\n\tdo {\n\t\texecuting = 0;\n\t\trte_spinlock_lock(&alarm_list_lk);\n\t\t/* remove any matches at the start of the list */\n\t\twhile ((ap = LIST_FIRST(&alarm_list)) != NULL &&\n\t\t\t\tcb_fn == ap->cb_fn &&\n\t\t\t\t(cb_arg == (void *)-1 || cb_arg == ap->cb_arg)) {\n\n\t\t\tif (ap->executing == 0) {\n\t\t\t\tLIST_REMOVE(ap, next);\n\t\t\t\trte_free(ap);\n\t\t\t\tcount++;\n\t\t\t} else {\n\t\t\t\t/* If calling from other context, mark that alarm is executing\n\t\t\t\t * so loop can spin till it finish. Otherwise we are trying to\n\t\t\t\t * cancel our self - mark it by EINPROGRESS */\n\t\t\t\tif (pthread_equal(ap->executing_id, pthread_self()) == 0)\n\t\t\t\t\texecuting++;\n\t\t\t\telse\n\t\t\t\t\terr = EINPROGRESS;\n\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tap_prev = ap;\n\n\t\t/* now go through list, removing entries not at start */\n\t\tLIST_FOREACH(ap, &alarm_list, next) {\n\t\t\t/* this won't be true first time through */\n\t\t\tif (cb_fn == ap->cb_fn &&\n\t\t\t\t\t(cb_arg == (void *)-1 || cb_arg == ap->cb_arg)) {\n\n\t\t\t\tif (ap->executing == 0) {\n\t\t\t\t\tLIST_REMOVE(ap, next);\n\t\t\t\t\trte_free(ap);\n\t\t\t\t\tcount++;\n\t\t\t\t\tap = ap_prev;\n\t\t\t\t} else if (pthread_equal(ap->executing_id, pthread_self()) == 0)\n\t\t\t\t\texecuting++;\n\t\t\t\telse\n\t\t\t\t\terr = EINPROGRESS;\n\t\t\t}\n\t\t\tap_prev = ap;\n\t\t}\n\t\trte_spinlock_unlock(&alarm_list_lk);\n\t} while (executing != 0);\n\n\tif (count == 0 && err == 0)\n\t\trte_errno = ENOENT;\n\telse if (err)\n\t\trte_errno = err;\n\n\treturn count;\n}\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_debug.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#define BACKTRACE_SIZE 256\n\n/* dump the stack of the calling core */\nvoid rte_dump_stack(void)\n{\n\tvoid *func[BACKTRACE_SIZE];\n\tchar **symb = NULL;\n\tint size;\n\n\tsize = backtrace(func, BACKTRACE_SIZE);\n\tsymb = backtrace_symbols(func, size);\n\twhile (size > 0) {\n\t\trte_log(RTE_LOG_ERR, RTE_LOGTYPE_EAL,\n\t\t\t\"%d: [%s]\\n\", size, symb[size - 1]);\n\t\tsize --;\n\t}\n}\n\n/* not implemented in this environment */\nvoid rte_dump_registers(void)\n{\n\treturn;\n}\n\n/* call abort(), it will generate a coredump if enabled */\nvoid __rte_panic(const char *funcname, const char *format, ...)\n{\n\tva_list ap;\n\n\t/* disable history */\n\trte_log_set_history(0);\n\n\trte_log(RTE_LOG_CRIT, RTE_LOGTYPE_EAL, \"PANIC in %s():\\n\", funcname);\n\tva_start(ap, format);\n\trte_vlog(RTE_LOG_CRIT, RTE_LOGTYPE_EAL, format, ap);\n\tva_end(ap);\n\trte_dump_stack();\n\trte_dump_registers();\n\tabort();\n}\n\n/*\n * Like rte_panic this terminates the application. However, no traceback is\n * provided and no core-dump is generated.\n */\nvoid\nrte_exit(int exit_code, const char *format, ...)\n{\n\tva_list ap;\n\n\t/* disable history */\n\trte_log_set_history(0);\n\n\tif (exit_code != 0)\n\t\tRTE_LOG(CRIT, EAL, \"Error - exiting with code: %d\\n\"\n\t\t\t\t\" Cause: \", exit_code);\n\n\tva_start(ap, format);\n\trte_vlog(RTE_LOG_CRIT, RTE_LOGTYPE_EAL, format, ap);\n\tva_end(ap);\n\n#ifndef RTE_EAL_ALWAYS_PANIC_ON_ERROR\n\texit(exit_code);\n#else\n\trte_dump_stack();\n\trte_dump_registers();\n\tabort();\n#endif\n}\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_hugepage_info.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \"rte_string_fns.h\"\n#include \"eal_internal_cfg.h\"\n#include \"eal_hugepages.h\"\n#include \"eal_filesystem.h\"\n\nstatic const char sys_dir_path[] = \"/sys/kernel/mm/hugepages\";\n\n/* this function is only called from eal_hugepage_info_init which itself\n * is only called from a primary process */\nstatic uint32_t\nget_num_hugepages(const char *subdir)\n{\n\tchar path[PATH_MAX];\n\tlong unsigned resv_pages, num_pages = 0;\n\tconst char *nr_hp_file = \"free_hugepages\";\n\tconst char *nr_rsvd_file = \"resv_hugepages\";\n\n\t/* first, check how many reserved pages kernel reports */\n\tsnprintf(path, sizeof(path), \"%s/%s/%s\",\n\t\t\tsys_dir_path, subdir, nr_rsvd_file);\n\tif (eal_parse_sysfs_value(path, &resv_pages) < 0)\n\t\treturn 0;\n\n\tsnprintf(path, sizeof(path), \"%s/%s/%s\",\n\t\t\tsys_dir_path, subdir, nr_hp_file);\n\tif (eal_parse_sysfs_value(path, &num_pages) < 0)\n\t\treturn 0;\n\n\tif (num_pages == 0)\n\t\tRTE_LOG(WARNING, EAL, \"No free hugepages reported in %s\\n\",\n\t\t\t\tsubdir);\n\n\t/* adjust num_pages */\n\tif (num_pages >= resv_pages)\n\t\tnum_pages -= resv_pages;\n\telse if (resv_pages)\n\t\tnum_pages = 0;\n\n\t/* we want to return a uint32_t and more than this looks suspicious\n\t * anyway ... */\n\tif (num_pages > UINT32_MAX)\n\t\tnum_pages = UINT32_MAX;\n\n\treturn num_pages;\n}\n\nstatic uint64_t\nget_default_hp_size(void)\n{\n\tconst char proc_meminfo[] = \"/proc/meminfo\";\n\tconst char str_hugepagesz[] = \"Hugepagesize:\";\n\tunsigned hugepagesz_len = sizeof(str_hugepagesz) - 1;\n\tchar buffer[256];\n\tunsigned long long size = 0;\n\n\tFILE *fd = fopen(proc_meminfo, \"r\");\n\tif (fd == NULL)\n\t\trte_panic(\"Cannot open %s\\n\", proc_meminfo);\n\twhile(fgets(buffer, sizeof(buffer), fd)){\n\t\tif (strncmp(buffer, str_hugepagesz, hugepagesz_len) == 0){\n\t\t\tsize = rte_str_to_size(&buffer[hugepagesz_len]);\n\t\t\tbreak;\n\t\t}\n\t}\n\tfclose(fd);\n\tif (size == 0)\n\t\trte_panic(\"Cannot get default hugepage size from %s\\n\", proc_meminfo);\n\treturn size;\n}\n\nstatic const char *\nget_hugepage_dir(uint64_t hugepage_sz)\n{\n\tenum proc_mount_fieldnames {\n\t\tDEVICE = 0,\n\t\tMOUNTPT,\n\t\tFSTYPE,\n\t\tOPTIONS,\n\t\t_FIELDNAME_MAX\n\t};\n\tstatic uint64_t default_size = 0;\n\tconst char proc_mounts[] = \"/proc/mounts\";\n\tconst char hugetlbfs_str[] = \"hugetlbfs\";\n\tconst size_t htlbfs_str_len = sizeof(hugetlbfs_str) - 1;\n\tconst char pagesize_opt[] = \"pagesize=\";\n\tconst size_t pagesize_opt_len = sizeof(pagesize_opt) - 1;\n\tconst char split_tok = ' ';\n\tchar *splitstr[_FIELDNAME_MAX];\n\tchar buf[BUFSIZ];\n\tchar *retval = NULL;\n\n\tFILE *fd = fopen(proc_mounts, \"r\");\n\tif (fd == NULL)\n\t\trte_panic(\"Cannot open %s\\n\", proc_mounts);\n\n\tif (default_size == 0)\n\t\tdefault_size = get_default_hp_size();\n\n\twhile (fgets(buf, sizeof(buf), fd)){\n\t\tif (rte_strsplit(buf, sizeof(buf), splitstr, _FIELDNAME_MAX,\n\t\t\t\tsplit_tok) != _FIELDNAME_MAX) {\n\t\t\tRTE_LOG(ERR, EAL, \"Error parsing %s\\n\", proc_mounts);\n\t\t\tbreak; /* return NULL */\n\t\t}\n\n\t\t/* we have a specified --huge-dir option, only examine that dir */\n\t\tif (internal_config.hugepage_dir != NULL &&\n\t\t\t\tstrcmp(splitstr[MOUNTPT], internal_config.hugepage_dir) != 0)\n\t\t\tcontinue;\n\n\t\tif (strncmp(splitstr[FSTYPE], hugetlbfs_str, htlbfs_str_len) == 0){\n\t\t\tconst char *pagesz_str = strstr(splitstr[OPTIONS], pagesize_opt);\n\n\t\t\t/* if no explicit page size, the default page size is compared */\n\t\t\tif (pagesz_str == NULL){\n\t\t\t\tif (hugepage_sz == default_size){\n\t\t\t\t\tretval = strdup(splitstr[MOUNTPT]);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\t/* there is an explicit page size, so check it */\n\t\t\telse {\n\t\t\t\tuint64_t pagesz = rte_str_to_size(&pagesz_str[pagesize_opt_len]);\n\t\t\t\tif (pagesz == hugepage_sz) {\n\t\t\t\t\tretval = strdup(splitstr[MOUNTPT]);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t} /* end if strncmp hugetlbfs */\n\t} /* end while fgets */\n\n\tfclose(fd);\n\treturn retval;\n}\n\n/*\n * Clear the hugepage directory of whatever hugepage files\n * there are. Checks if the file is locked (i.e.\n * if it's in use by another DPDK process).\n */\nstatic int\nclear_hugedir(const char * hugedir)\n{\n\tDIR *dir;\n\tstruct dirent *dirent;\n\tint dir_fd, fd, lck_result;\n\tconst char filter[] = \"*map_*\"; /* matches hugepage files */\n\n\t/* open directory */\n\tdir = opendir(hugedir);\n\tif (!dir) {\n\t\tRTE_LOG(ERR, EAL, \"Unable to open hugepage directory %s\\n\",\n\t\t\t\thugedir);\n\t\tgoto error;\n\t}\n\tdir_fd = dirfd(dir);\n\n\tdirent = readdir(dir);\n\tif (!dirent) {\n\t\tRTE_LOG(ERR, EAL, \"Unable to read hugepage directory %s\\n\",\n\t\t\t\thugedir);\n\t\tgoto error;\n\t}\n\n\twhile(dirent != NULL){\n\t\t/* skip files that don't match the hugepage pattern */\n\t\tif (fnmatch(filter, dirent->d_name, 0) > 0) {\n\t\t\tdirent = readdir(dir);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* try and lock the file */\n\t\tfd = openat(dir_fd, dirent->d_name, O_RDONLY);\n\n\t\t/* skip to next file */\n\t\tif (fd == -1) {\n\t\t\tdirent = readdir(dir);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* non-blocking lock */\n\t\tlck_result = flock(fd, LOCK_EX | LOCK_NB);\n\n\t\t/* if lock succeeds, unlock and remove the file */\n\t\tif (lck_result != -1) {\n\t\t\tflock(fd, LOCK_UN);\n\t\t\tunlinkat(dir_fd, dirent->d_name, 0);\n\t\t}\n\t\tclose (fd);\n\t\tdirent = readdir(dir);\n\t}\n\n\tclosedir(dir);\n\treturn 0;\n\nerror:\n\tif (dir)\n\t\tclosedir(dir);\n\n\tRTE_LOG(ERR, EAL, \"Error while clearing hugepage dir: %s\\n\",\n\t\tstrerror(errno));\n\n\treturn -1;\n}\n\nstatic int\ncompare_hpi(const void *a, const void *b)\n{\n\tconst struct hugepage_info *hpi_a = a;\n\tconst struct hugepage_info *hpi_b = b;\n\n\treturn hpi_b->hugepage_sz - hpi_a->hugepage_sz;\n}\n\n/*\n * when we initialize the hugepage info, everything goes\n * to socket 0 by default. it will later get sorted by memory\n * initialization procedure.\n */\nint\neal_hugepage_info_init(void)\n{\n\tconst char dirent_start_text[] = \"hugepages-\";\n\tconst size_t dirent_start_len = sizeof(dirent_start_text) - 1;\n\tunsigned i, num_sizes = 0;\n\tDIR *dir;\n\tstruct dirent *dirent;\n\n\tdir = opendir(sys_dir_path);\n\tif (dir == NULL)\n\t\trte_panic(\"Cannot open directory %s to read system hugepage \"\n\t\t\t \"info\\n\", sys_dir_path);\n\n\tfor (dirent = readdir(dir); dirent != NULL; dirent = readdir(dir)) {\n\t\tstruct hugepage_info *hpi;\n\n\t\tif (strncmp(dirent->d_name, dirent_start_text,\n\t\t\t dirent_start_len) != 0)\n\t\t\tcontinue;\n\n\t\tif (num_sizes >= MAX_HUGEPAGE_SIZES)\n\t\t\tbreak;\n\n\t\thpi = &internal_config.hugepage_info[num_sizes];\n\t\thpi->hugepage_sz =\n\t\t\trte_str_to_size(&dirent->d_name[dirent_start_len]);\n\t\thpi->hugedir = get_hugepage_dir(hpi->hugepage_sz);\n\n\t\t/* first, check if we have a mountpoint */\n\t\tif (hpi->hugedir == NULL) {\n\t\t\tuint32_t num_pages;\n\n\t\t\tnum_pages = get_num_hugepages(dirent->d_name);\n\t\t\tif (num_pages > 0)\n\t\t\t\tRTE_LOG(NOTICE, EAL,\n\t\t\t\t\t\"%\" PRIu32 \" hugepages of size \"\n\t\t\t\t\t\"%\" PRIu64 \" reserved, but no mounted \"\n\t\t\t\t\t\"hugetlbfs found for that size\\n\",\n\t\t\t\t\tnum_pages, hpi->hugepage_sz);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* try to obtain a writelock */\n\t\thpi->lock_descriptor = open(hpi->hugedir, O_RDONLY);\n\n\t\t/* if blocking lock failed */\n\t\tif (flock(hpi->lock_descriptor, LOCK_EX) == -1) {\n\t\t\tRTE_LOG(CRIT, EAL,\n\t\t\t\t\"Failed to lock hugepage directory!\\n\");\n\t\t\tbreak;\n\t\t}\n\t\t/* clear out the hugepages dir from unused pages */\n\t\tif (clear_hugedir(hpi->hugedir) == -1)\n\t\t\tbreak;\n\n\t\t/* for now, put all pages into socket 0,\n\t\t * later they will be sorted */\n\t\thpi->num_pages[0] = get_num_hugepages(dirent->d_name);\n\n#ifndef RTE_ARCH_64\n\t\t/* for 32-bit systems, limit number of hugepages to\n\t\t * 1GB per page size */\n\t\thpi->num_pages[0] = RTE_MIN(hpi->num_pages[0],\n\t\t\t\t\t RTE_PGSIZE_1G / hpi->hugepage_sz);\n#endif\n\n\t\tnum_sizes++;\n\t}\n\tclosedir(dir);\n\n\t/* something went wrong, and we broke from the for loop above */\n\tif (dirent != NULL)\n\t\treturn -1;\n\n\tinternal_config.num_hugepage_sizes = num_sizes;\n\n\t/* sort the page directory entries by size, largest to smallest */\n\tqsort(&internal_config.hugepage_info[0], num_sizes,\n\t sizeof(internal_config.hugepage_info[0]), compare_hpi);\n\n\t/* now we have all info, check we have at least one valid size */\n\tfor (i = 0; i < num_sizes; i++)\n\t\tif (internal_config.hugepage_info[i].hugedir != NULL &&\n\t\t internal_config.hugepage_info[i].num_pages[0] > 0)\n\t\t\treturn 0;\n\n\t/* no valid hugepage mounts available, return error */\n\treturn -1;\n}\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_interrupts.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_vfio.h\"\n\n#define EAL_INTR_EPOLL_WAIT_FOREVER (-1)\n#define NB_OTHER_INTR 1\n\nstatic RTE_DEFINE_PER_LCORE(int, _epfd) = -1; /**< epoll fd per thread */\n\n/**\n * union for pipe fds.\n */\nunion intr_pipefds{\n\tstruct {\n\t\tint pipefd[2];\n\t};\n\tstruct {\n\t\tint readfd;\n\t\tint writefd;\n\t};\n};\n\n/**\n * union buffer for reading on different devices\n */\nunion rte_intr_read_buffer {\n\tint uio_intr_count; /* for uio device */\n#ifdef VFIO_PRESENT\n\tuint64_t vfio_intr_count; /* for vfio device */\n#endif\n\tuint64_t timerfd_num; /* for timerfd */\n\tchar charbuf[16]; /* for others */\n};\n\nTAILQ_HEAD(rte_intr_cb_list, rte_intr_callback);\nTAILQ_HEAD(rte_intr_source_list, rte_intr_source);\n\nstruct rte_intr_callback {\n\tTAILQ_ENTRY(rte_intr_callback) next;\n\trte_intr_callback_fn cb_fn; /**< callback address */\n\tvoid *cb_arg; /**< parameter for callback */\n};\n\nstruct rte_intr_source {\n\tTAILQ_ENTRY(rte_intr_source) next;\n\tstruct rte_intr_handle intr_handle; /**< interrupt handle */\n\tstruct rte_intr_cb_list callbacks; /**< user callbacks */\n\tuint32_t active;\n};\n\n/* global spinlock for interrupt data operation */\nstatic rte_spinlock_t intr_lock = RTE_SPINLOCK_INITIALIZER;\n\n/* union buffer for pipe read/write */\nstatic union intr_pipefds intr_pipe;\n\n/* interrupt sources list */\nstatic struct rte_intr_source_list intr_sources;\n\n/* interrupt handling thread */\nstatic pthread_t intr_thread;\n\n/* VFIO interrupts */\n#ifdef VFIO_PRESENT\n\n#define IRQ_SET_BUF_LEN (sizeof(struct vfio_irq_set) + sizeof(int))\n/* irq set buffer length for queue interrupts and LSC interrupt */\n#define MSIX_IRQ_SET_BUF_LEN (sizeof(struct vfio_irq_set) + \\\n\t\t\t sizeof(int) * (RTE_MAX_RXTX_INTR_VEC_ID + 1))\n\n/* enable legacy (INTx) interrupts */\nstatic int\nvfio_enable_intx(struct rte_intr_handle *intr_handle) {\n\tstruct vfio_irq_set *irq_set;\n\tchar irq_set_buf[IRQ_SET_BUF_LEN];\n\tint len, ret;\n\tint *fd_ptr;\n\n\tlen = sizeof(irq_set_buf);\n\n\t/* enable INTx */\n\tirq_set = (struct vfio_irq_set *) irq_set_buf;\n\tirq_set->argsz = len;\n\tirq_set->count = 1;\n\tirq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;\n\tirq_set->index = VFIO_PCI_INTX_IRQ_INDEX;\n\tirq_set->start = 0;\n\tfd_ptr = (int *) &irq_set->data;\n\t*fd_ptr = intr_handle->fd;\n\n\tret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL, \"Error enabling INTx interrupts for fd %d\\n\",\n\t\t\t\t\t\tintr_handle->fd);\n\t\treturn -1;\n\t}\n\n\t/* unmask INTx after enabling */\n\tmemset(irq_set, 0, len);\n\tlen = sizeof(struct vfio_irq_set);\n\tirq_set->argsz = len;\n\tirq_set->count = 1;\n\tirq_set->flags = VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_ACTION_UNMASK;\n\tirq_set->index = VFIO_PCI_INTX_IRQ_INDEX;\n\tirq_set->start = 0;\n\n\tret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL, \"Error unmasking INTx interrupts for fd %d\\n\",\n\t\t\t\t\t\tintr_handle->fd);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/* disable legacy (INTx) interrupts */\nstatic int\nvfio_disable_intx(struct rte_intr_handle *intr_handle) {\n\tstruct vfio_irq_set *irq_set;\n\tchar irq_set_buf[IRQ_SET_BUF_LEN];\n\tint len, ret;\n\n\tlen = sizeof(struct vfio_irq_set);\n\n\t/* mask interrupts before disabling */\n\tirq_set = (struct vfio_irq_set *) irq_set_buf;\n\tirq_set->argsz = len;\n\tirq_set->count = 1;\n\tirq_set->flags = VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_ACTION_UNMASK;\n\tirq_set->index = VFIO_PCI_INTX_IRQ_INDEX;\n\tirq_set->start = 0;\n\n\tret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL, \"Error unmasking INTx interrupts for fd %d\\n\",\n\t\t\t\t\t\tintr_handle->fd);\n\t\treturn -1;\n\t}\n\n\t/* disable INTx*/\n\tmemset(irq_set, 0, len);\n\tirq_set->argsz = len;\n\tirq_set->count = 0;\n\tirq_set->flags = VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_ACTION_TRIGGER;\n\tirq_set->index = VFIO_PCI_INTX_IRQ_INDEX;\n\tirq_set->start = 0;\n\n\tret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Error disabling INTx interrupts for fd %d\\n\", intr_handle->fd);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/* enable MSI interrupts */\nstatic int\nvfio_enable_msi(struct rte_intr_handle *intr_handle) {\n\tint len, ret;\n\tchar irq_set_buf[IRQ_SET_BUF_LEN];\n\tstruct vfio_irq_set *irq_set;\n\tint *fd_ptr;\n\n\tlen = sizeof(irq_set_buf);\n\n\tirq_set = (struct vfio_irq_set *) irq_set_buf;\n\tirq_set->argsz = len;\n\tirq_set->count = 1;\n\tirq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;\n\tirq_set->index = VFIO_PCI_MSI_IRQ_INDEX;\n\tirq_set->start = 0;\n\tfd_ptr = (int *) &irq_set->data;\n\t*fd_ptr = intr_handle->fd;\n\n\tret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL, \"Error enabling MSI interrupts for fd %d\\n\",\n\t\t\t\t\t\tintr_handle->fd);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n/* disable MSI interrupts */\nstatic int\nvfio_disable_msi(struct rte_intr_handle *intr_handle) {\n\tstruct vfio_irq_set *irq_set;\n\tchar irq_set_buf[IRQ_SET_BUF_LEN];\n\tint len, ret;\n\n\tlen = sizeof(struct vfio_irq_set);\n\n\tirq_set = (struct vfio_irq_set *) irq_set_buf;\n\tirq_set->argsz = len;\n\tirq_set->count = 0;\n\tirq_set->flags = VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_ACTION_TRIGGER;\n\tirq_set->index = VFIO_PCI_MSI_IRQ_INDEX;\n\tirq_set->start = 0;\n\n\tret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n\n\tif (ret)\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Error disabling MSI interrupts for fd %d\\n\", intr_handle->fd);\n\n\treturn ret;\n}\n\n/* enable MSI-X interrupts */\nstatic int\nvfio_enable_msix(struct rte_intr_handle *intr_handle) {\n\tint len, ret;\n\tchar irq_set_buf[MSIX_IRQ_SET_BUF_LEN];\n\tstruct vfio_irq_set *irq_set;\n\tint *fd_ptr;\n\n\tlen = sizeof(irq_set_buf);\n\n\tirq_set = (struct vfio_irq_set *) irq_set_buf;\n\tirq_set->argsz = len;\n#ifdef RTE_NEXT_ABI\n\tif (!intr_handle->max_intr)\n\t\tintr_handle->max_intr = 1;\n\telse if (intr_handle->max_intr > RTE_MAX_RXTX_INTR_VEC_ID)\n\t\tintr_handle->max_intr = RTE_MAX_RXTX_INTR_VEC_ID + 1;\n\n\tirq_set->count = intr_handle->max_intr;\n#else\n\tirq_set->count = 1;\n#endif\n\tirq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;\n\tirq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;\n\tirq_set->start = 0;\n\tfd_ptr = (int *) &irq_set->data;\n#ifdef RTE_NEXT_ABI\n\tmemcpy(fd_ptr, intr_handle->efds, sizeof(intr_handle->efds));\n\tfd_ptr[intr_handle->max_intr - 1] = intr_handle->fd;\n#else\n\tfd_ptr[0] = intr_handle->fd;\n#endif\n\n\tret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL, \"Error enabling MSI-X interrupts for fd %d\\n\",\n\t\t\t\t\t\tintr_handle->fd);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* disable MSI-X interrupts */\nstatic int\nvfio_disable_msix(struct rte_intr_handle *intr_handle) {\n\tstruct vfio_irq_set *irq_set;\n\tchar irq_set_buf[MSIX_IRQ_SET_BUF_LEN];\n\tint len, ret;\n\n\tlen = sizeof(struct vfio_irq_set);\n\n\tirq_set = (struct vfio_irq_set *) irq_set_buf;\n\tirq_set->argsz = len;\n\tirq_set->count = 0;\n\tirq_set->flags = VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_ACTION_TRIGGER;\n\tirq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;\n\tirq_set->start = 0;\n\n\tret = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n\n\tif (ret)\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Error disabling MSI-X interrupts for fd %d\\n\", intr_handle->fd);\n\n\treturn ret;\n}\n#endif\n\nstatic int\nuio_intx_intr_disable(struct rte_intr_handle *intr_handle)\n{\n\tunsigned char command_high;\n\n\t/* use UIO config file descriptor for uio_pci_generic */\n\tif (pread(intr_handle->uio_cfg_fd, &command_high, 1, 5) != 1) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Error reading interrupts status for fd %d\\n\",\n\t\t\tintr_handle->uio_cfg_fd);\n\t\treturn -1;\n\t}\n\t/* disable interrupts */\n\tcommand_high |= 0x4;\n\tif (pwrite(intr_handle->uio_cfg_fd, &command_high, 1, 5) != 1) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Error disabling interrupts for fd %d\\n\",\n\t\t\tintr_handle->uio_cfg_fd);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nuio_intx_intr_enable(struct rte_intr_handle *intr_handle)\n{\n\tunsigned char command_high;\n\n\t/* use UIO config file descriptor for uio_pci_generic */\n\tif (pread(intr_handle->uio_cfg_fd, &command_high, 1, 5) != 1) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Error reading interrupts status for fd %d\\n\",\n\t\t\tintr_handle->uio_cfg_fd);\n\t\treturn -1;\n\t}\n\t/* enable interrupts */\n\tcommand_high &= ~0x4;\n\tif (pwrite(intr_handle->uio_cfg_fd, &command_high, 1, 5) != 1) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Error enabling interrupts for fd %d\\n\",\n\t\t\tintr_handle->uio_cfg_fd);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nuio_intr_disable(struct rte_intr_handle *intr_handle)\n{\n\tconst int value = 0;\n\n\tif (write(intr_handle->fd, &value, sizeof(value)) < 0) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Error disabling interrupts for fd %d (%s)\\n\",\n\t\t\tintr_handle->fd, strerror(errno));\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nstatic int\nuio_intr_enable(struct rte_intr_handle *intr_handle)\n{\n\tconst int value = 1;\n\n\tif (write(intr_handle->fd, &value, sizeof(value)) < 0) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Error enabling interrupts for fd %d (%s)\\n\",\n\t\t\tintr_handle->fd, strerror(errno));\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nint\nrte_intr_callback_register(struct rte_intr_handle *intr_handle,\n\t\t\trte_intr_callback_fn cb, void *cb_arg)\n{\n\tint ret, wake_thread;\n\tstruct rte_intr_source *src;\n\tstruct rte_intr_callback *callback;\n\n\twake_thread = 0;\n\n\t/* first do parameter checking */\n\tif (intr_handle == NULL || intr_handle->fd < 0 || cb == NULL) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Registering with invalid input parameter\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* allocate a new interrupt callback entity */\n\tcallback = rte_zmalloc(\"interrupt callback list\",\n\t\t\t\tsizeof(*callback), 0);\n\tif (callback == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Can not allocate memory\\n\");\n\t\treturn -ENOMEM;\n\t}\n\tcallback->cb_fn = cb;\n\tcallback->cb_arg = cb_arg;\n\n\trte_spinlock_lock(&intr_lock);\n\n\t/* check if there is at least one callback registered for the fd */\n\tTAILQ_FOREACH(src, &intr_sources, next) {\n\t\tif (src->intr_handle.fd == intr_handle->fd) {\n\t\t\t/* we had no interrupts for this */\n\t\t\tif TAILQ_EMPTY(&src->callbacks)\n\t\t\t\twake_thread = 1;\n\n\t\t\tTAILQ_INSERT_TAIL(&(src->callbacks), callback, next);\n\t\t\tret = 0;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* no existing callbacks for this - add new source */\n\tif (src == NULL) {\n\t\tif ((src = rte_zmalloc(\"interrupt source list\",\n\t\t\t\tsizeof(*src), 0)) == NULL) {\n\t\t\tRTE_LOG(ERR, EAL, \"Can not allocate memory\\n\");\n\t\t\trte_free(callback);\n\t\t\tret = -ENOMEM;\n\t\t} else {\n\t\t\tsrc->intr_handle = *intr_handle;\n\t\t\tTAILQ_INIT(&src->callbacks);\n\t\t\tTAILQ_INSERT_TAIL(&(src->callbacks), callback, next);\n\t\t\tTAILQ_INSERT_TAIL(&intr_sources, src, next);\n\t\t\twake_thread = 1;\n\t\t\tret = 0;\n\t\t}\n\t}\n\n\trte_spinlock_unlock(&intr_lock);\n\n\t/**\n\t * check if need to notify the pipe fd waited by epoll_wait to\n\t * rebuild the wait list.\n\t */\n\tif (wake_thread)\n\t\tif (write(intr_pipe.writefd, \"1\", 1) < 0)\n\t\t\treturn -EPIPE;\n\n\treturn ret;\n}\n\nint\nrte_intr_callback_unregister(struct rte_intr_handle *intr_handle,\n\t\t\trte_intr_callback_fn cb_fn, void *cb_arg)\n{\n\tint ret;\n\tstruct rte_intr_source *src;\n\tstruct rte_intr_callback *cb, *next;\n\n\t/* do parameter checking first */\n\tif (intr_handle == NULL || intr_handle->fd < 0) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\"Unregistering with invalid input parameter\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\trte_spinlock_lock(&intr_lock);\n\n\t/* check if the insterrupt source for the fd is existent */\n\tTAILQ_FOREACH(src, &intr_sources, next)\n\t\tif (src->intr_handle.fd == intr_handle->fd)\n\t\t\tbreak;\n\n\t/* No interrupt source registered for the fd */\n\tif (src == NULL) {\n\t\tret = -ENOENT;\n\n\t/* interrupt source has some active callbacks right now. */\n\t} else if (src->active != 0) {\n\t\tret = -EAGAIN;\n\n\t/* ok to remove. */\n\t} else {\n\t\tret = 0;\n\n\t\t/*walk through the callbacks and remove all that match. */\n\t\tfor (cb = TAILQ_FIRST(&src->callbacks); cb != NULL; cb = next) {\n\n\t\t\tnext = TAILQ_NEXT(cb, next);\n\n\t\t\tif (cb->cb_fn == cb_fn && (cb_arg == (void *)-1 ||\n\t\t\t\t\tcb->cb_arg == cb_arg)) {\n\t\t\t\tTAILQ_REMOVE(&src->callbacks, cb, next);\n\t\t\t\trte_free(cb);\n\t\t\t\tret++;\n\t\t\t}\n\t\t}\n\n\t\t/* all callbacks for that source are removed. */\n\t\tif (TAILQ_EMPTY(&src->callbacks)) {\n\t\t\tTAILQ_REMOVE(&intr_sources, src, next);\n\t\t\trte_free(src);\n\t\t}\n\t}\n\n\trte_spinlock_unlock(&intr_lock);\n\n\t/* notify the pipe fd waited by epoll_wait to rebuild the wait list */\n\tif (ret >= 0 && write(intr_pipe.writefd, \"1\", 1) < 0) {\n\t\tret = -EPIPE;\n\t}\n\n\treturn ret;\n}\n\nint\nrte_intr_enable(struct rte_intr_handle *intr_handle)\n{\n\tif (!intr_handle || intr_handle->fd < 0 || intr_handle->uio_cfg_fd < 0)\n\t\treturn -1;\n\n\tswitch (intr_handle->type){\n\t/* write to the uio fd to enable the interrupt */\n\tcase RTE_INTR_HANDLE_UIO:\n\t\tif (uio_intr_enable(intr_handle))\n\t\t\treturn -1;\n\t\tbreak;\n\tcase RTE_INTR_HANDLE_UIO_INTX:\n\t\tif (uio_intx_intr_enable(intr_handle))\n\t\t\treturn -1;\n\t\tbreak;\n\t/* not used at this moment */\n\tcase RTE_INTR_HANDLE_ALARM:\n\t\treturn -1;\n#ifdef VFIO_PRESENT\n\tcase RTE_INTR_HANDLE_VFIO_MSIX:\n\t\tif (vfio_enable_msix(intr_handle))\n\t\t\treturn -1;\n\t\tbreak;\n\tcase RTE_INTR_HANDLE_VFIO_MSI:\n\t\tif (vfio_enable_msi(intr_handle))\n\t\t\treturn -1;\n\t\tbreak;\n\tcase RTE_INTR_HANDLE_VFIO_LEGACY:\n\t\tif (vfio_enable_intx(intr_handle))\n\t\t\treturn -1;\n\t\tbreak;\n#endif\n\t/* unknown handle type */\n\tdefault:\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Unknown handle type of fd %d\\n\",\n\t\t\t\t\tintr_handle->fd);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nint\nrte_intr_disable(struct rte_intr_handle *intr_handle)\n{\n\tif (!intr_handle || intr_handle->fd < 0 || intr_handle->uio_cfg_fd < 0)\n\t\treturn -1;\n\n\tswitch (intr_handle->type){\n\t/* write to the uio fd to disable the interrupt */\n\tcase RTE_INTR_HANDLE_UIO:\n\t\tif (uio_intr_disable(intr_handle))\n\t\t\treturn -1;\n\t\tbreak;\n\tcase RTE_INTR_HANDLE_UIO_INTX:\n\t\tif (uio_intx_intr_disable(intr_handle))\n\t\t\treturn -1;\n\t\tbreak;\n\t/* not used at this moment */\n\tcase RTE_INTR_HANDLE_ALARM:\n\t\treturn -1;\n#ifdef VFIO_PRESENT\n\tcase RTE_INTR_HANDLE_VFIO_MSIX:\n\t\tif (vfio_disable_msix(intr_handle))\n\t\t\treturn -1;\n\t\tbreak;\n\tcase RTE_INTR_HANDLE_VFIO_MSI:\n\t\tif (vfio_disable_msi(intr_handle))\n\t\t\treturn -1;\n\t\tbreak;\n\tcase RTE_INTR_HANDLE_VFIO_LEGACY:\n\t\tif (vfio_disable_intx(intr_handle))\n\t\t\treturn -1;\n\t\tbreak;\n#endif\n\t/* unknown handle type */\n\tdefault:\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Unknown handle type of fd %d\\n\",\n\t\t\t\t\tintr_handle->fd);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\neal_intr_process_interrupts(struct epoll_event *events, int nfds)\n{\n\tint n, bytes_read;\n\tstruct rte_intr_source *src;\n\tstruct rte_intr_callback *cb;\n\tunion rte_intr_read_buffer buf;\n\tstruct rte_intr_callback active_cb;\n\n\tfor (n = 0; n < nfds; n++) {\n\n\t\t/**\n\t\t * if the pipe fd is ready to read, return out to\n\t\t * rebuild the wait list.\n\t\t */\n\t\tif (events[n].data.fd == intr_pipe.readfd){\n\t\t\tint r = read(intr_pipe.readfd, buf.charbuf,\n\t\t\t\t\tsizeof(buf.charbuf));\n\t\t\tRTE_SET_USED(r);\n\t\t\treturn -1;\n\t\t}\n\t\trte_spinlock_lock(&intr_lock);\n\t\tTAILQ_FOREACH(src, &intr_sources, next)\n\t\t\tif (src->intr_handle.fd ==\n\t\t\t\t\tevents[n].data.fd)\n\t\t\t\tbreak;\n\t\tif (src == NULL){\n\t\t\trte_spinlock_unlock(&intr_lock);\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* mark this interrupt source as active and release the lock. */\n\t\tsrc->active = 1;\n\t\trte_spinlock_unlock(&intr_lock);\n\n\t\t/* set the length to be read dor different handle type */\n\t\tswitch (src->intr_handle.type) {\n\t\tcase RTE_INTR_HANDLE_UIO:\n\t\tcase RTE_INTR_HANDLE_UIO_INTX:\n\t\t\tbytes_read = sizeof(buf.uio_intr_count);\n\t\t\tbreak;\n\t\tcase RTE_INTR_HANDLE_ALARM:\n\t\t\tbytes_read = sizeof(buf.timerfd_num);\n\t\t\tbreak;\n#ifdef VFIO_PRESENT\n\t\tcase RTE_INTR_HANDLE_VFIO_MSIX:\n\t\tcase RTE_INTR_HANDLE_VFIO_MSI:\n\t\tcase RTE_INTR_HANDLE_VFIO_LEGACY:\n\t\t\tbytes_read = sizeof(buf.vfio_intr_count);\n\t\t\tbreak;\n#endif\n\t\tdefault:\n\t\t\tbytes_read = 1;\n\t\t\tbreak;\n\t\t}\n\n\t\t/**\n\t\t * read out to clear the ready-to-be-read flag\n\t\t * for epoll_wait.\n\t\t */\n\t\tbytes_read = read(events[n].data.fd, &buf, bytes_read);\n\t\tif (bytes_read < 0) {\n\t\t\tif (errno == EINTR || errno == EWOULDBLOCK)\n\t\t\t\tcontinue;\n\n\t\t\tRTE_LOG(ERR, EAL, \"Error reading from file \"\n\t\t\t\t\"descriptor %d: %s\\n\", events[n].data.fd,\n\t\t\t\t\t\t\tstrerror(errno));\n\t\t} else if (bytes_read == 0)\n\t\t\tRTE_LOG(ERR, EAL, \"Read nothing from file \"\n\t\t\t\t\"descriptor %d\\n\", events[n].data.fd);\n\n\t\t/* grab a lock, again to call callbacks and update status. */\n\t\trte_spinlock_lock(&intr_lock);\n\n\t\tif (bytes_read > 0) {\n\n\t\t\t/* Finally, call all callbacks. */\n\t\t\tTAILQ_FOREACH(cb, &src->callbacks, next) {\n\n\t\t\t\t/* make a copy and unlock. */\n\t\t\t\tactive_cb = *cb;\n\t\t\t\trte_spinlock_unlock(&intr_lock);\n\n\t\t\t\t/* call the actual callback */\n\t\t\t\tactive_cb.cb_fn(&src->intr_handle,\n\t\t\t\t\tactive_cb.cb_arg);\n\n\t\t\t\t/*get the lock back. */\n\t\t\t\trte_spinlock_lock(&intr_lock);\n\t\t\t}\n\t\t}\n\n\t\t/* we done with that interrupt source, release it. */\n\t\tsrc->active = 0;\n\t\trte_spinlock_unlock(&intr_lock);\n\t}\n\n\treturn 0;\n}\n\n/**\n * It handles all the interrupts.\n *\n * @param pfd\n * epoll file descriptor.\n * @param totalfds\n * The number of file descriptors added in epoll.\n *\n * @return\n * void\n */\nstatic void\neal_intr_handle_interrupts(int pfd, unsigned totalfds)\n{\n\tstruct epoll_event events[totalfds];\n\tint nfds = 0;\n\n\tfor(;;) {\n\t\tnfds = epoll_wait(pfd, events, totalfds,\n\t\t\tEAL_INTR_EPOLL_WAIT_FOREVER);\n\t\t/* epoll_wait fail */\n\t\tif (nfds < 0) {\n\t\t\tif (errno == EINTR)\n\t\t\t\tcontinue;\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\"epoll_wait returns with fail\\n\");\n\t\t\treturn;\n\t\t}\n\t\t/* epoll_wait timeout, will never happens here */\n\t\telse if (nfds == 0)\n\t\t\tcontinue;\n\t\t/* epoll_wait has at least one fd ready to read */\n\t\tif (eal_intr_process_interrupts(events, nfds) < 0)\n\t\t\treturn;\n\t}\n}\n\n/**\n * It builds/rebuilds up the epoll file descriptor with all the\n * file descriptors being waited on. Then handles the interrupts.\n *\n * @param arg\n * pointer. (unused)\n *\n * @return\n * never return;\n */\nstatic __attribute__((noreturn)) void *\neal_intr_thread_main(__rte_unused void *arg)\n{\n\tstruct epoll_event ev;\n\n\t/* host thread, never break out */\n\tfor (;;) {\n\t\t/* build up the epoll fd with all descriptors we are to\n\t\t * wait on then pass it to the handle_interrupts function\n\t\t */\n\t\tstatic struct epoll_event pipe_event = {\n\t\t\t.events = EPOLLIN | EPOLLPRI,\n\t\t};\n\t\tstruct rte_intr_source *src;\n\t\tunsigned numfds = 0;\n\n\t\t/* create epoll fd */\n\t\tint pfd = epoll_create(1);\n\t\tif (pfd < 0)\n\t\t\trte_panic(\"Cannot create epoll instance\\n\");\n\n\t\tpipe_event.data.fd = intr_pipe.readfd;\n\t\t/**\n\t\t * add pipe fd into wait list, this pipe is used to\n\t\t * rebuild the wait list.\n\t\t */\n\t\tif (epoll_ctl(pfd, EPOLL_CTL_ADD, intr_pipe.readfd,\n\t\t\t\t\t\t&pipe_event) < 0) {\n\t\t\trte_panic(\"Error adding fd to %d epoll_ctl, %s\\n\",\n\t\t\t\t\tintr_pipe.readfd, strerror(errno));\n\t\t}\n\t\tnumfds++;\n\n\t\trte_spinlock_lock(&intr_lock);\n\n\t\tTAILQ_FOREACH(src, &intr_sources, next) {\n\t\t\tif (src->callbacks.tqh_first == NULL)\n\t\t\t\tcontinue; /* skip those with no callbacks */\n\t\t\tev.events = EPOLLIN | EPOLLPRI;\n\t\t\tev.data.fd = src->intr_handle.fd;\n\n\t\t\t/**\n\t\t\t * add all the uio device file descriptor\n\t\t\t * into wait list.\n\t\t\t */\n\t\t\tif (epoll_ctl(pfd, EPOLL_CTL_ADD,\n\t\t\t\t\tsrc->intr_handle.fd, &ev) < 0){\n\t\t\t\trte_panic(\"Error adding fd %d epoll_ctl, %s\\n\",\n\t\t\t\t\tsrc->intr_handle.fd, strerror(errno));\n\t\t\t}\n\t\t\telse\n\t\t\t\tnumfds++;\n\t\t}\n\t\trte_spinlock_unlock(&intr_lock);\n\t\t/* serve the interrupt */\n\t\teal_intr_handle_interrupts(pfd, numfds);\n\n\t\t/**\n\t\t * when we return, we need to rebuild the\n\t\t * list of fds to monitor.\n\t\t */\n\t\tclose(pfd);\n\t}\n}\n\nint\nrte_eal_intr_init(void)\n{\n\tint ret = 0;\n\n\t/* init the global interrupt source head */\n\tTAILQ_INIT(&intr_sources);\n\n\t/**\n\t * create a pipe which will be waited by epoll and notified to\n\t * rebuild the wait list of epoll.\n\t */\n\tif (pipe(intr_pipe.pipefd) < 0)\n\t\treturn -1;\n\n\t/* create the host thread to wait/handle the interrupt */\n\tret = pthread_create(&intr_thread, NULL,\n\t\t\teal_intr_thread_main, NULL);\n\tif (ret != 0)\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Failed to create thread for interrupt handling\\n\");\n\n\treturn -ret;\n}\n\n#ifdef RTE_NEXT_ABI\nstatic void\neal_intr_proc_rxtx_intr(int fd, const struct rte_intr_handle *intr_handle)\n{\n\tunion rte_intr_read_buffer buf;\n\tint bytes_read = 1;\n\n\tswitch (intr_handle->type) {\n\tcase RTE_INTR_HANDLE_UIO:\n\tcase RTE_INTR_HANDLE_UIO_INTX:\n\t\tbytes_read = sizeof(buf.uio_intr_count);\n\t\tbreak;\n#ifdef VFIO_PRESENT\n\tcase RTE_INTR_HANDLE_VFIO_MSIX:\n\tcase RTE_INTR_HANDLE_VFIO_MSI:\n\tcase RTE_INTR_HANDLE_VFIO_LEGACY:\n\t\tbytes_read = sizeof(buf.vfio_intr_count);\n\t\tbreak;\n#endif\n\tdefault:\n\t\tbytes_read = 1;\n\t\tRTE_LOG(INFO, EAL, \"unexpected intr type\\n\");\n\t\tbreak;\n\t}\n\n\t/**\n\t * read out to clear the ready-to-be-read flag\n\t * for epoll_wait.\n\t */\n\tdo {\n\t\tbytes_read = read(fd, &buf, bytes_read);\n\t\tif (bytes_read < 0) {\n\t\t\tif (errno == EINTR || errno == EWOULDBLOCK ||\n\t\t\t errno == EAGAIN)\n\t\t\t\tcontinue;\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\"Error reading from fd %d: %s\\n\",\n\t\t\t\tfd, strerror(errno));\n\t\t} else if (bytes_read == 0)\n\t\t\tRTE_LOG(ERR, EAL, \"Read nothing from fd %d\\n\", fd);\n\t\treturn;\n\t} while (1);\n}\n#endif\n\nstatic int\neal_epoll_process_event(struct epoll_event *evs, unsigned int n,\n\t\t\tstruct rte_epoll_event *events)\n{\n\tunsigned int i, count = 0;\n\tstruct rte_epoll_event *rev;\n\n\tfor (i = 0; i < n; i++) {\n\t\trev = evs[i].data.ptr;\n\t\tif (!rev || !rte_atomic32_cmpset(&rev->status, RTE_EPOLL_VALID,\n\t\t\t\t\t\t RTE_EPOLL_EXEC))\n\t\t\tcontinue;\n\n\t\tevents[count].status = RTE_EPOLL_VALID;\n\t\tevents[count].fd = rev->fd;\n\t\tevents[count].epfd = rev->epfd;\n\t\tevents[count].epdata.event = rev->epdata.event;\n\t\tevents[count].epdata.data = rev->epdata.data;\n\t\tif (rev->epdata.cb_fun)\n\t\t\trev->epdata.cb_fun(rev->fd,\n\t\t\t\t\t rev->epdata.cb_arg);\n\n\t\trte_compiler_barrier();\n\t\trev->status = RTE_EPOLL_VALID;\n\t\tcount++;\n\t}\n\treturn count;\n}\n\nstatic inline int\neal_init_tls_epfd(void)\n{\n\tint pfd = epoll_create(255);\n\n\tif (pfd < 0) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Cannot create epoll instance\\n\");\n\t\treturn -1;\n\t}\n\treturn pfd;\n}\n\nint\nrte_intr_tls_epfd(void)\n{\n\tif (RTE_PER_LCORE(_epfd) == -1)\n\t\tRTE_PER_LCORE(_epfd) = eal_init_tls_epfd();\n\n\treturn RTE_PER_LCORE(_epfd);\n}\n\nint\nrte_epoll_wait(int epfd, struct rte_epoll_event *events,\n\t int maxevents, int timeout)\n{\n\tstruct epoll_event evs[maxevents];\n\tint rc;\n\n\tif (!events) {\n\t\tRTE_LOG(ERR, EAL, \"rte_epoll_event can't be NULL\\n\");\n\t\treturn -1;\n\t}\n\n\t/* using per thread epoll fd */\n\tif (epfd == RTE_EPOLL_PER_THREAD)\n\t\tepfd = rte_intr_tls_epfd();\n\n\twhile (1) {\n\t\trc = epoll_wait(epfd, evs, maxevents, timeout);\n\t\tif (likely(rc > 0)) {\n\t\t\t/* epoll_wait has at least one fd ready to read */\n\t\t\trc = eal_epoll_process_event(evs, rc, events);\n\t\t\tbreak;\n\t\t} else if (rc < 0) {\n\t\t\tif (errno == EINTR)\n\t\t\t\tcontinue;\n\t\t\t/* epoll_wait fail */\n\t\t\tRTE_LOG(ERR, EAL, \"epoll_wait returns with fail %s\\n\",\n\t\t\t\tstrerror(errno));\n\t\t\trc = -1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn rc;\n}\n\nstatic inline void\neal_epoll_data_safe_free(struct rte_epoll_event *ev)\n{\n\twhile (!rte_atomic32_cmpset(&ev->status, RTE_EPOLL_VALID,\n\t\t\t\t RTE_EPOLL_INVALID))\n\t\twhile (ev->status != RTE_EPOLL_VALID)\n\t\t\trte_pause();\n\tmemset(&ev->epdata, 0, sizeof(ev->epdata));\n\tev->fd = -1;\n\tev->epfd = -1;\n}\n\nint\nrte_epoll_ctl(int epfd, int op, int fd,\n\t struct rte_epoll_event *event)\n{\n\tstruct epoll_event ev;\n\n\tif (!event) {\n\t\tRTE_LOG(ERR, EAL, \"rte_epoll_event can't be NULL\\n\");\n\t\treturn -1;\n\t}\n\n\t/* using per thread epoll fd */\n\tif (epfd == RTE_EPOLL_PER_THREAD)\n\t\tepfd = rte_intr_tls_epfd();\n\n\tif (op == EPOLL_CTL_ADD) {\n\t\tevent->status = RTE_EPOLL_VALID;\n\t\tevent->fd = fd; /* ignore fd in event */\n\t\tevent->epfd = epfd;\n\t\tev.data.ptr = (void *)event;\n\t}\n\n\tev.events = event->epdata.event;\n\tif (epoll_ctl(epfd, op, fd, &ev) < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Error op %d fd %d epoll_ctl, %s\\n\",\n\t\t\top, fd, strerror(errno));\n\t\tif (op == EPOLL_CTL_ADD)\n\t\t\t/* rollback status when CTL_ADD fail */\n\t\t\tevent->status = RTE_EPOLL_INVALID;\n\t\treturn -1;\n\t}\n\n\tif (op == EPOLL_CTL_DEL && event->status != RTE_EPOLL_INVALID)\n\t\teal_epoll_data_safe_free(event);\n\n\treturn 0;\n}\n\n#ifdef RTE_NEXT_ABI\nint\nrte_intr_rx_ctl(struct rte_intr_handle *intr_handle, int epfd,\n\t\tint op, unsigned int vec, void *data)\n{\n\tstruct rte_epoll_event *rev;\n\tstruct rte_epoll_data *epdata;\n\tint epfd_op;\n\tint rc = 0;\n\n\tif (!intr_handle || intr_handle->nb_efd == 0 ||\n\t vec >= intr_handle->nb_efd) {\n\t\tRTE_LOG(ERR, EAL, \"Wrong intr vector number.\\n\");\n\t\treturn -EPERM;\n\t}\n\n\tswitch (op) {\n\tcase RTE_INTR_EVENT_ADD:\n\t\tepfd_op = EPOLL_CTL_ADD;\n\t\trev = &intr_handle->elist[vec];\n\t\tif (rev->status != RTE_EPOLL_INVALID) {\n\t\t\tRTE_LOG(INFO, EAL, \"Event already been added.\\n\");\n\t\t\treturn -EEXIST;\n\t\t}\n\n\t\t/* attach to intr vector fd */\n\t\tepdata = &rev->epdata;\n\t\tepdata->event = EPOLLIN | EPOLLPRI | EPOLLET;\n\t\tepdata->data = data;\n\t\tepdata->cb_fun = (rte_intr_event_cb_t)eal_intr_proc_rxtx_intr;\n\t\tepdata->cb_arg = (void *)intr_handle;\n\t\trc = rte_epoll_ctl(epfd, epfd_op, intr_handle->efds[vec], rev);\n\t\tif (!rc)\n\t\t\tRTE_LOG(DEBUG, EAL,\n\t\t\t\t\"efd %d associated with vec %d added on epfd %d\"\n\t\t\t\t\"\\n\", rev->fd, vec, epfd);\n\t\telse\n\t\t\trc = -EPERM;\n\t\tbreak;\n\tcase RTE_INTR_EVENT_DEL:\n\t\tepfd_op = EPOLL_CTL_DEL;\n\t\trev = &intr_handle->elist[vec];\n\t\tif (rev->status == RTE_EPOLL_INVALID) {\n\t\t\tRTE_LOG(INFO, EAL, \"Event does not exist.\\n\");\n\t\t\treturn -EPERM;\n\t\t}\n\n\t\trc = rte_epoll_ctl(rev->epfd, epfd_op, rev->fd, rev);\n\t\tif (rc)\n\t\t\trc = -EPERM;\n\t\tbreak;\n\tdefault:\n\t\tRTE_LOG(ERR, EAL, \"event op type mismatch\\n\");\n\t\trc = -EPERM;\n\t}\n\n\treturn rc;\n}\n\nint\nrte_intr_efd_enable(struct rte_intr_handle *intr_handle, uint32_t nb_efd)\n{\n\tuint32_t i;\n\tint fd;\n\tuint32_t n = RTE_MIN(nb_efd, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);\n\n\tif (intr_handle->type == RTE_INTR_HANDLE_VFIO_MSIX) {\n\t\tfor (i = 0; i < n; i++) {\n\t\t\tfd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);\n\t\t\tif (fd < 0) {\n\t\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\t\"can't setup eventfd, error %i (%s)\\n\",\n\t\t\t\t\terrno, strerror(errno));\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tintr_handle->efds[i] = fd;\n\t\t}\n\t\tintr_handle->nb_efd = n;\n\t\tintr_handle->max_intr = NB_OTHER_INTR + n;\n\t} else {\n\t\tintr_handle->efds[0] = intr_handle->fd;\n\t\tintr_handle->nb_efd = RTE_MIN(nb_efd, 1U);\n\t\tintr_handle->max_intr = NB_OTHER_INTR;\n\t}\n\n\treturn 0;\n}\n\nvoid\nrte_intr_efd_disable(struct rte_intr_handle *intr_handle)\n{\n\tuint32_t i;\n\tstruct rte_epoll_event *rev;\n\n\tfor (i = 0; i < intr_handle->nb_efd; i++) {\n\t\trev = &intr_handle->elist[i];\n\t\tif (rev->status == RTE_EPOLL_INVALID)\n\t\t\tcontinue;\n\t\tif (rte_epoll_ctl(rev->epfd, EPOLL_CTL_DEL, rev->fd, rev)) {\n\t\t\t/* force free if the entry valid */\n\t\t\teal_epoll_data_safe_free(rev);\n\t\t\trev->status = RTE_EPOLL_INVALID;\n\t\t}\n\t}\n\n\tif (intr_handle->max_intr > intr_handle->nb_efd) {\n\t\tfor (i = 0; i < intr_handle->nb_efd; i++)\n\t\t\tclose(intr_handle->efds[i]);\n\t}\n\tintr_handle->nb_efd = 0;\n\tintr_handle->max_intr = 0;\n}\n\nint\nrte_intr_dp_is_en(struct rte_intr_handle *intr_handle)\n{\n\treturn !(!intr_handle->nb_efd);\n}\n\nint\nrte_intr_allow_others(struct rte_intr_handle *intr_handle)\n{\n\treturn !!(intr_handle->max_intr - intr_handle->nb_efd);\n}\n\n#else\nint\nrte_intr_rx_ctl(struct rte_intr_handle *intr_handle,\n\t\tint epfd, int op, unsigned int vec, void *data)\n{\n\tRTE_SET_USED(intr_handle);\n\tRTE_SET_USED(epfd);\n\tRTE_SET_USED(op);\n\tRTE_SET_USED(vec);\n\tRTE_SET_USED(data);\n\treturn -ENOTSUP;\n}\n\nint\nrte_intr_efd_enable(struct rte_intr_handle *intr_handle, uint32_t nb_efd)\n{\n\tRTE_SET_USED(intr_handle);\n\tRTE_SET_USED(nb_efd);\n\treturn 0;\n}\n\nvoid\nrte_intr_efd_disable(struct rte_intr_handle *intr_handle)\n{\n\tRTE_SET_USED(intr_handle);\n}\n\nint\nrte_intr_dp_is_en(struct rte_intr_handle *intr_handle)\n{\n\tRTE_SET_USED(intr_handle);\n\treturn 0;\n}\n\nint\nrte_intr_allow_others(struct rte_intr_handle *intr_handle)\n{\n\tRTE_SET_USED(intr_handle);\n\treturn 1;\n}\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_ivshmem.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifdef RTE_LIBRTE_IVSHMEM /* hide it from coverage */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_internal_cfg.h\"\n#include \"eal_private.h\"\n\n#define PCI_VENDOR_ID_IVSHMEM 0x1Af4\n#define PCI_DEVICE_ID_IVSHMEM 0x1110\n\n#define IVSHMEM_MAGIC 0x0BADC0DE\n\n#define IVSHMEM_RESOURCE_PATH \"/sys/bus/pci/devices/%04x:%02x:%02x.%x/resource2\"\n#define IVSHMEM_CONFIG_PATH \"/var/run/.%s_ivshmem_config\"\n\n#define PHYS 0x1\n#define VIRT 0x2\n#define IOREMAP 0x4\n#define FULL (PHYS|VIRT|IOREMAP)\n\n#define METADATA_SIZE_ALIGNED \\\n\t(RTE_ALIGN_CEIL(sizeof(struct rte_ivshmem_metadata),pagesz))\n\n#define CONTAINS(x,y)\\\n\t(((y).addr_64 >= (x).addr_64) && ((y).addr_64 < (x).addr_64 + (x).len))\n\n#define DIM(x) (sizeof(x)/sizeof(x[0]))\n\nstruct ivshmem_pci_device {\n\tchar path[PATH_MAX];\n\tphys_addr_t ioremap_addr;\n};\n\n/* data type to store in config */\nstruct ivshmem_segment {\n\tstruct rte_ivshmem_metadata_entry entry;\n\tuint64_t align;\n\tchar path[PATH_MAX];\n};\nstruct ivshmem_shared_config {\n\tstruct ivshmem_segment segment[RTE_MAX_MEMSEG];\n\tuint32_t segment_idx;\n\tstruct ivshmem_pci_device pci_devs[RTE_LIBRTE_IVSHMEM_MAX_PCI_DEVS];\n\tuint32_t pci_devs_idx;\n};\nstatic struct ivshmem_shared_config * ivshmem_config;\nstatic int memseg_idx;\nstatic int pagesz;\n\n/* Tailq heads to add rings to */\nTAILQ_HEAD(rte_ring_list, rte_tailq_entry);\n\n/*\n * Utility functions\n */\n\nstatic int\nis_ivshmem_device(struct rte_pci_device * dev)\n{\n\treturn (dev->id.vendor_id == PCI_VENDOR_ID_IVSHMEM\n\t\t\t&& dev->id.device_id == PCI_DEVICE_ID_IVSHMEM);\n}\n\nstatic void *\nmap_metadata(int fd, uint64_t len)\n{\n\tsize_t metadata_len = sizeof(struct rte_ivshmem_metadata);\n\tsize_t aligned_len = METADATA_SIZE_ALIGNED;\n\n\treturn mmap(NULL, metadata_len, PROT_READ | PROT_WRITE,\n\t\t\tMAP_SHARED, fd, len - aligned_len);\n}\n\nstatic void\nunmap_metadata(void * ptr)\n{\n\tmunmap(ptr, sizeof(struct rte_ivshmem_metadata));\n}\n\nstatic int\nhas_ivshmem_metadata(int fd, uint64_t len)\n{\n\tstruct rte_ivshmem_metadata metadata;\n\tvoid * ptr;\n\n\tptr = map_metadata(fd, len);\n\n\tif (ptr == MAP_FAILED)\n\t\treturn -1;\n\n\tmetadata = *(struct rte_ivshmem_metadata*) (ptr);\n\n\tunmap_metadata(ptr);\n\n\treturn metadata.magic_number == IVSHMEM_MAGIC;\n}\n\nstatic void\nremove_segment(struct ivshmem_segment * ms, int len, int idx)\n{\n\tint i;\n\n\tfor (i = idx; i < len - 1; i++)\n\t\tmemcpy(&ms[i], &ms[i+1], sizeof(struct ivshmem_segment));\n\tmemset(&ms[len-1], 0, sizeof(struct ivshmem_segment));\n}\n\nstatic int\noverlap(const struct rte_memzone * mz1, const struct rte_memzone * mz2)\n{\n\tuint64_t start1, end1, start2, end2;\n\tuint64_t p_start1, p_end1, p_start2, p_end2;\n\tuint64_t i_start1, i_end1, i_start2, i_end2;\n\tint result = 0;\n\n\t/* gather virtual addresses */\n\tstart1 = mz1->addr_64;\n\tend1 = mz1->addr_64 + mz1->len;\n\tstart2 = mz2->addr_64;\n\tend2 = mz2->addr_64 + mz2->len;\n\n\t/* gather physical addresses */\n\tp_start1 = mz1->phys_addr;\n\tp_end1 = mz1->phys_addr + mz1->len;\n\tp_start2 = mz2->phys_addr;\n\tp_end2 = mz2->phys_addr + mz2->len;\n\n\t/* gather ioremap addresses */\n\ti_start1 = mz1->ioremap_addr;\n\ti_end1 = mz1->ioremap_addr + mz1->len;\n\ti_start2 = mz2->ioremap_addr;\n\ti_end2 = mz2->ioremap_addr + mz2->len;\n\n\t/* check for overlap in virtual addresses */\n\tif (start1 >= start2 && start1 < end2)\n\t\tresult |= VIRT;\n\tif (start2 >= start1 && start2 < end1)\n\t\tresult |= VIRT;\n\n\t/* check for overlap in physical addresses */\n\tif (p_start1 >= p_start2 && p_start1 < p_end2)\n\t\tresult |= PHYS;\n\tif (p_start2 >= p_start1 && p_start2 < p_end1)\n\t\tresult |= PHYS;\n\n\t/* check for overlap in ioremap addresses */\n\tif (i_start1 >= i_start2 && i_start1 < i_end2)\n\t\tresult |= IOREMAP;\n\tif (i_start2 >= i_start1 && i_start2 < i_end1)\n\t\tresult |= IOREMAP;\n\n\treturn result;\n}\n\nstatic int\nadjacent(const struct rte_memzone * mz1, const struct rte_memzone * mz2)\n{\n\tuint64_t start1, end1, start2, end2;\n\tuint64_t p_start1, p_end1, p_start2, p_end2;\n\tuint64_t i_start1, i_end1, i_start2, i_end2;\n\tint result = 0;\n\n\t/* gather virtual addresses */\n\tstart1 = mz1->addr_64;\n\tend1 = mz1->addr_64 + mz1->len;\n\tstart2 = mz2->addr_64;\n\tend2 = mz2->addr_64 + mz2->len;\n\n\t/* gather physical addresses */\n\tp_start1 = mz1->phys_addr;\n\tp_end1 = mz1->phys_addr + mz1->len;\n\tp_start2 = mz2->phys_addr;\n\tp_end2 = mz2->phys_addr + mz2->len;\n\n\t/* gather ioremap addresses */\n\ti_start1 = mz1->ioremap_addr;\n\ti_end1 = mz1->ioremap_addr + mz1->len;\n\ti_start2 = mz2->ioremap_addr;\n\ti_end2 = mz2->ioremap_addr + mz2->len;\n\n\t/* check if segments are virtually adjacent */\n\tif (start1 == end2)\n\t\tresult |= VIRT;\n\tif (start2 == end1)\n\t\tresult |= VIRT;\n\n\t/* check if segments are physically adjacent */\n\tif (p_start1 == p_end2)\n\t\tresult |= PHYS;\n\tif (p_start2 == p_end1)\n\t\tresult |= PHYS;\n\n\t/* check if segments are ioremap-adjacent */\n\tif (i_start1 == i_end2)\n\t\tresult |= IOREMAP;\n\tif (i_start2 == i_end1)\n\t\tresult |= IOREMAP;\n\n\treturn result;\n}\n\nstatic int\nhas_adjacent_segments(struct ivshmem_segment * ms, int len)\n{\n\tint i, j, a;\n\n\tfor (i = 0; i < len; i++)\n\t\tfor (j = i + 1; j < len; j++) {\n\t\t\ta = adjacent(&ms[i].entry.mz, &ms[j].entry.mz);\n\n\t\t\t/* check if segments are adjacent virtually and/or physically but\n\t\t\t * not ioremap (since that would indicate that they are from\n\t\t\t * different PCI devices and thus don't need to be concatenated.\n\t\t\t */\n\t\t\tif ((a & (VIRT|PHYS)) > 0 && (a & IOREMAP) == 0)\n\t\t\t\treturn 1;\n\t\t}\n\treturn 0;\n}\n\nstatic int\nhas_overlapping_segments(struct ivshmem_segment * ms, int len)\n{\n\tint i, j;\n\n\tfor (i = 0; i < len; i++)\n\t\tfor (j = i + 1; j < len; j++)\n\t\t\tif (overlap(&ms[i].entry.mz, &ms[j].entry.mz))\n\t\t\t\treturn 1;\n\treturn 0;\n}\n\nstatic int\nseg_compare(const void * a, const void * b)\n{\n\tconst struct ivshmem_segment * s1 = (const struct ivshmem_segment*) a;\n\tconst struct ivshmem_segment * s2 = (const struct ivshmem_segment*) b;\n\n\t/* move unallocated zones to the end */\n\tif (s1->entry.mz.addr == NULL && s2->entry.mz.addr == NULL)\n\t\treturn 0;\n\tif (s1->entry.mz.addr == 0)\n\t\treturn 1;\n\tif (s2->entry.mz.addr == 0)\n\t\treturn -1;\n\n\treturn s1->entry.mz.phys_addr > s2->entry.mz.phys_addr;\n}\n\n#ifdef RTE_LIBRTE_IVSHMEM_DEBUG\nstatic void\nentry_dump(struct rte_ivshmem_metadata_entry *e)\n{\n\tRTE_LOG(DEBUG, EAL, \"\\tvirt: %p-%p\\n\", e->mz.addr,\n\t\t\tRTE_PTR_ADD(e->mz.addr, e->mz.len));\n\tRTE_LOG(DEBUG, EAL, \"\\tphys: 0x%\" PRIx64 \"-0x%\" PRIx64 \"\\n\",\n\t\t\te->mz.phys_addr,\n\t\t\te->mz.phys_addr + e->mz.len);\n\tRTE_LOG(DEBUG, EAL, \"\\tio: 0x%\" PRIx64 \"-0x%\" PRIx64 \"\\n\",\n\t\t\te->mz.ioremap_addr,\n\t\t\te->mz.ioremap_addr + e->mz.len);\n\tRTE_LOG(DEBUG, EAL, \"\\tlen: 0x%\" PRIx64 \"\\n\", e->mz.len);\n\tRTE_LOG(DEBUG, EAL, \"\\toff: 0x%\" PRIx64 \"\\n\", e->offset);\n}\n#endif\n\n\n\n/*\n * Actual useful code\n */\n\n/* read through metadata mapped from the IVSHMEM device */\nstatic int\nread_metadata(char * path, int path_len, int fd, uint64_t flen)\n{\n\tstruct rte_ivshmem_metadata metadata;\n\tstruct rte_ivshmem_metadata_entry * entry;\n\tint idx, i;\n\tvoid * ptr;\n\n\tptr = map_metadata(fd, flen);\n\n\tif (ptr == MAP_FAILED)\n\t\treturn -1;\n\n\tmetadata = *(struct rte_ivshmem_metadata*) (ptr);\n\n\tunmap_metadata(ptr);\n\n\tRTE_LOG(DEBUG, EAL, \"Parsing metadata for \\\"%s\\\"\\n\", metadata.name);\n\n\tidx = ivshmem_config->segment_idx;\n\n\tfor (i = 0; i < RTE_LIBRTE_IVSHMEM_MAX_ENTRIES &&\n\t\tidx <= RTE_MAX_MEMSEG; i++) {\n\n\t\tif (idx == RTE_MAX_MEMSEG) {\n\t\t\tRTE_LOG(ERR, EAL, \"Not enough memory segments!\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tentry = &metadata.entry[i];\n\n\t\t/* stop on uninitialized memzone */\n\t\tif (entry->mz.len == 0)\n\t\t\tbreak;\n\n\t\t/* copy metadata entry */\n\t\tmemcpy(&ivshmem_config->segment[idx].entry, entry,\n\t\t\t\tsizeof(struct rte_ivshmem_metadata_entry));\n\n\t\t/* copy path */\n\t\tsnprintf(ivshmem_config->segment[idx].path, path_len, \"%s\", path);\n\n\t\tidx++;\n\t}\n\tivshmem_config->segment_idx = idx;\n\n\treturn 0;\n}\n\n/* check through each segment and look for adjacent or overlapping ones. */\nstatic int\ncleanup_segments(struct ivshmem_segment * ms, int tbl_len)\n{\n\tstruct ivshmem_segment * s, * tmp;\n\tint i, j, concat, seg_adjacent, seg_overlapping;\n\tuint64_t start1, start2, end1, end2, p_start1, p_start2, i_start1, i_start2;\n\n\tqsort(ms, tbl_len, sizeof(struct ivshmem_segment),\n\t\t\t\tseg_compare);\n\n\twhile (has_overlapping_segments(ms, tbl_len) ||\n\t\t\thas_adjacent_segments(ms, tbl_len)) {\n\n\t\tfor (i = 0; i < tbl_len; i++) {\n\t\t\ts = &ms[i];\n\n\t\t\tconcat = 0;\n\n\t\t\tfor (j = i + 1; j < tbl_len; j++) {\n\t\t\t\ttmp = &ms[j];\n\n\t\t\t\t/* check if this segment is overlapping with existing segment,\n\t\t\t\t * or is adjacent to existing segment */\n\t\t\t\tseg_overlapping = overlap(&s->entry.mz, &tmp->entry.mz);\n\t\t\t\tseg_adjacent = adjacent(&s->entry.mz, &tmp->entry.mz);\n\n\t\t\t\t/* check if segments fully overlap or are fully adjacent */\n\t\t\t\tif ((seg_adjacent == FULL) || (seg_overlapping == FULL)) {\n\n#ifdef RTE_LIBRTE_IVSHMEM_DEBUG\n\t\t\t\t\tRTE_LOG(DEBUG, EAL, \"Concatenating segments\\n\");\n\t\t\t\t\tRTE_LOG(DEBUG, EAL, \"Segment %i:\\n\", i);\n\t\t\t\t\tentry_dump(&s->entry);\n\t\t\t\t\tRTE_LOG(DEBUG, EAL, \"Segment %i:\\n\", j);\n\t\t\t\t\tentry_dump(&tmp->entry);\n#endif\n\n\t\t\t\t\tstart1 = s->entry.mz.addr_64;\n\t\t\t\t\tstart2 = tmp->entry.mz.addr_64;\n\t\t\t\t\tp_start1 = s->entry.mz.phys_addr;\n\t\t\t\t\tp_start2 = tmp->entry.mz.phys_addr;\n\t\t\t\t\ti_start1 = s->entry.mz.ioremap_addr;\n\t\t\t\t\ti_start2 = tmp->entry.mz.ioremap_addr;\n\t\t\t\t\tend1 = s->entry.mz.addr_64 + s->entry.mz.len;\n\t\t\t\t\tend2 = tmp->entry.mz.addr_64 + tmp->entry.mz.len;\n\n\t\t\t\t\t/* settle for minimum start address and maximum length */\n\t\t\t\t\ts->entry.mz.addr_64 = RTE_MIN(start1, start2);\n\t\t\t\t\ts->entry.mz.phys_addr = RTE_MIN(p_start1, p_start2);\n\t\t\t\t\ts->entry.mz.ioremap_addr = RTE_MIN(i_start1, i_start2);\n\t\t\t\t\ts->entry.offset = RTE_MIN(s->entry.offset, tmp->entry.offset);\n\t\t\t\t\ts->entry.mz.len = RTE_MAX(end1, end2) - s->entry.mz.addr_64;\n\t\t\t\t\tconcat = 1;\n\n#ifdef RTE_LIBRTE_IVSHMEM_DEBUG\n\t\t\t\t\tRTE_LOG(DEBUG, EAL, \"Resulting segment:\\n\");\n\t\t\t\t\tentry_dump(&s->entry);\n\n#endif\n\t\t\t\t}\n\t\t\t\t/* if segments not fully overlap, we have an error condition.\n\t\t\t\t * adjacent segments can coexist.\n\t\t\t\t */\n\t\t\t\telse if (seg_overlapping > 0) {\n\t\t\t\t\tRTE_LOG(ERR, EAL, \"Segments %i and %i overlap!\\n\", i, j);\n#ifdef RTE_LIBRTE_IVSHMEM_DEBUG\n\t\t\t\t\tRTE_LOG(DEBUG, EAL, \"Segment %i:\\n\", i);\n\t\t\t\t\tentry_dump(&s->entry);\n\t\t\t\t\tRTE_LOG(DEBUG, EAL, \"Segment %i:\\n\", j);\n\t\t\t\t\tentry_dump(&tmp->entry);\n#endif\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t\tif (concat)\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t\t/* if we concatenated, remove segment at j */\n\t\t\tif (concat) {\n\t\t\t\tremove_segment(ms, tbl_len, j);\n\t\t\t\ttbl_len--;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn tbl_len;\n}\n\nstatic int\ncreate_shared_config(void)\n{\n\tchar path[PATH_MAX];\n\tint fd;\n\n\t/* build ivshmem config file path */\n\tsnprintf(path, sizeof(path), IVSHMEM_CONFIG_PATH,\n\t\t\tinternal_config.hugefile_prefix);\n\n\tfd = open(path, O_CREAT | O_RDWR, 0600);\n\n\tif (fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Could not open %s: %s\\n\", path, strerror(errno));\n\t\treturn -1;\n\t}\n\n\t/* try ex-locking first - if the file is locked, we have a problem */\n\tif (flock(fd, LOCK_EX | LOCK_NB) == -1) {\n\t\tRTE_LOG(ERR, EAL, \"Locking %s failed: %s\\n\", path, strerror(errno));\n\t\tclose(fd);\n\t\treturn -1;\n\t}\n\n\tif (ftruncate(fd, sizeof(struct ivshmem_shared_config)) < 0) {\n\t\tRTE_LOG(ERR, EAL, \"ftruncate failed: %s\\n\", strerror(errno));\n\t\treturn -1;\n\t}\n\n\tivshmem_config = mmap(NULL, sizeof(struct ivshmem_shared_config),\n\t\t\tPROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);\n\n\tif (ivshmem_config == MAP_FAILED)\n\t\treturn -1;\n\n\tmemset(ivshmem_config, 0, sizeof(struct ivshmem_shared_config));\n\n\t/* change the exclusive lock we got earlier to a shared lock */\n\tif (flock(fd, LOCK_SH | LOCK_NB) == -1) {\n\t\tRTE_LOG(ERR, EAL, \"Locking %s failed: %s \\n\", path, strerror(errno));\n\t\treturn -1;\n\t}\n\n\tclose(fd);\n\n\treturn 0;\n}\n\n/* open shared config file and, if present, map the config.\n * having no config file is not an error condition, as we later check if\n * ivshmem_config is NULL (if it is, that means nothing was mapped). */\nstatic int\nopen_shared_config(void)\n{\n\tchar path[PATH_MAX];\n\tint fd;\n\n\t/* build ivshmem config file path */\n\tsnprintf(path, sizeof(path), IVSHMEM_CONFIG_PATH,\n\t\t\tinternal_config.hugefile_prefix);\n\n\tfd = open(path, O_RDONLY);\n\n\t/* if the file doesn't exist, just return success */\n\tif (fd < 0 && errno == ENOENT)\n\t\treturn 0;\n\t/* else we have an error condition */\n\telse if (fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Could not open %s: %s\\n\",\n\t\t\t\tpath, strerror(errno));\n\t\treturn -1;\n\t}\n\n\t/* try ex-locking first - if the lock *does* succeed, this means it's a\n\t * stray config file, so it should be deleted.\n\t */\n\tif (flock(fd, LOCK_EX | LOCK_NB) != -1) {\n\n\t\t/* if we can't remove the file, something is wrong */\n\t\tif (unlink(path) < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"Could not remove %s: %s\\n\", path,\n\t\t\t\t\tstrerror(errno));\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* release the lock */\n\t\tflock(fd, LOCK_UN);\n\t\tclose(fd);\n\n\t\t/* return success as having a stray config file is equivalent to not\n\t\t * having config file at all.\n\t\t */\n\t\treturn 0;\n\t}\n\n\tivshmem_config = mmap(NULL, sizeof(struct ivshmem_shared_config),\n\t\t\tPROT_READ, MAP_SHARED, fd, 0);\n\n\tif (ivshmem_config == MAP_FAILED)\n\t\treturn -1;\n\n\t/* place a shared lock on config file */\n\tif (flock(fd, LOCK_SH | LOCK_NB) == -1) {\n\t\tRTE_LOG(ERR, EAL, \"Locking %s failed: %s \\n\", path, strerror(errno));\n\t\treturn -1;\n\t}\n\n\tclose(fd);\n\n\treturn 0;\n}\n\n/*\n * This function does the following:\n *\n * 1) Builds a table of ivshmem_segments with proper offset alignment\n * 2) Cleans up that table so that we don't have any overlapping or adjacent\n * memory segments\n * 3) Creates memsegs from this table and maps them into memory.\n */\nstatic inline int\nmap_all_segments(void)\n{\n\tstruct ivshmem_segment ms_tbl[RTE_MAX_MEMSEG];\n\tstruct ivshmem_pci_device * pci_dev;\n\tstruct rte_mem_config * mcfg;\n\tstruct ivshmem_segment * seg;\n\tint fd, fd_zero;\n\tunsigned i, j;\n\tstruct rte_memzone mz;\n\tstruct rte_memseg ms;\n\tvoid * base_addr;\n\tuint64_t align, len;\n\tphys_addr_t ioremap_addr;\n\n\tioremap_addr = 0;\n\n\tmemset(ms_tbl, 0, sizeof(ms_tbl));\n\tmemset(&mz, 0, sizeof(struct rte_memzone));\n\tmemset(&ms, 0, sizeof(struct rte_memseg));\n\n\t/* first, build a table of memsegs to map, to avoid failed mmaps due to\n\t * overlaps\n\t */\n\tfor (i = 0; i < ivshmem_config->segment_idx && i <= RTE_MAX_MEMSEG; i++) {\n\t\tif (i == RTE_MAX_MEMSEG) {\n\t\t\tRTE_LOG(ERR, EAL, \"Too many segments requested!\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tseg = &ivshmem_config->segment[i];\n\n\t\t/* copy segment to table */\n\t\tmemcpy(&ms_tbl[i], seg, sizeof(struct ivshmem_segment));\n\n\t\t/* find ioremap addr */\n\t\tfor (j = 0; j < DIM(ivshmem_config->pci_devs); j++) {\n\t\t\tpci_dev = &ivshmem_config->pci_devs[j];\n\t\t\tif (!strncmp(pci_dev->path, seg->path, sizeof(pci_dev->path))) {\n\t\t\t\tioremap_addr = pci_dev->ioremap_addr;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (ioremap_addr == 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"Cannot find ioremap addr!\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* work out alignments */\n\t\talign = seg->entry.mz.addr_64 -\n\t\t\t\tRTE_ALIGN_FLOOR(seg->entry.mz.addr_64, 0x1000);\n\t\tlen = RTE_ALIGN_CEIL(seg->entry.mz.len + align, 0x1000);\n\n\t\t/* save original alignments */\n\t\tms_tbl[i].align = align;\n\n\t\t/* create a memory zone */\n\t\tmz.addr_64 = seg->entry.mz.addr_64 - align;\n\t\tmz.len = len;\n\t\tmz.hugepage_sz = seg->entry.mz.hugepage_sz;\n\t\tmz.phys_addr = seg->entry.mz.phys_addr - align;\n\n\t\t/* find true physical address */\n\t\tmz.ioremap_addr = ioremap_addr + seg->entry.offset - align;\n\n\t\tms_tbl[i].entry.offset = seg->entry.offset - align;\n\n\t\tmemcpy(&ms_tbl[i].entry.mz, &mz, sizeof(struct rte_memzone));\n\t}\n\n\t/* clean up the segments */\n\tmemseg_idx = cleanup_segments(ms_tbl, ivshmem_config->segment_idx);\n\n\tif (memseg_idx < 0)\n\t\treturn -1;\n\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\tfd_zero = open(\"/dev/zero\", O_RDWR);\n\n\tif (fd_zero < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot open /dev/zero: %s\\n\", strerror(errno));\n\t\treturn -1;\n\t}\n\n\t/* create memsegs and put them into DPDK memory */\n\tfor (i = 0; i < (unsigned) memseg_idx; i++) {\n\n\t\tseg = &ms_tbl[i];\n\n\t\tms.addr_64 = seg->entry.mz.addr_64;\n\t\tms.hugepage_sz = seg->entry.mz.hugepage_sz;\n\t\tms.len = seg->entry.mz.len;\n\t\tms.nchannel = rte_memory_get_nchannel();\n\t\tms.nrank = rte_memory_get_nrank();\n\t\tms.phys_addr = seg->entry.mz.phys_addr;\n\t\tms.ioremap_addr = seg->entry.mz.ioremap_addr;\n\t\tms.socket_id = seg->entry.mz.socket_id;\n\n\t\tbase_addr = mmap(ms.addr, ms.len,\n\t\t\t\tPROT_READ | PROT_WRITE, MAP_PRIVATE, fd_zero, 0);\n\n\t\tif (base_addr == MAP_FAILED || base_addr != ms.addr) {\n\t\t\tRTE_LOG(ERR, EAL, \"Cannot map /dev/zero!\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tfd = open(seg->path, O_RDWR);\n\n\t\tif (fd < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"Cannot open %s: %s\\n\", seg->path,\n\t\t\t\t\tstrerror(errno));\n\t\t\treturn -1;\n\t\t}\n\n\t\tmunmap(ms.addr, ms.len);\n\n\t\tbase_addr = mmap(ms.addr, ms.len,\n\t\t\t\tPROT_READ | PROT_WRITE, MAP_SHARED, fd,\n\t\t\t\tseg->entry.offset);\n\n\n\t\tif (base_addr == MAP_FAILED || base_addr != ms.addr) {\n\t\t\tRTE_LOG(ERR, EAL, \"Cannot map segment into memory: \"\n\t\t\t\t\t\"expected %p got %p (%s)\\n\", ms.addr, base_addr,\n\t\t\t\t\tstrerror(errno));\n\t\t\treturn -1;\n\t\t}\n\n\t\tRTE_LOG(DEBUG, EAL, \"Memory segment mapped: %p (len %\" PRIx64 \") at \"\n\t\t\t\t\"offset 0x%\" PRIx64 \"\\n\",\n\t\t\t\tms.addr, ms.len, seg->entry.offset);\n\n\t\t/* put the pointers back into their real positions using original\n\t\t * alignment */\n\t\tms.addr_64 += seg->align;\n\t\tms.phys_addr += seg->align;\n\t\tms.ioremap_addr += seg->align;\n\t\tms.len -= seg->align;\n\n\t\t/* at this point, the rest of DPDK memory is not initialized, so we\n\t\t * expect memsegs to be empty */\n\t\tmemcpy(&mcfg->memseg[i], &ms,\n\t\t\t\tsizeof(struct rte_memseg));\n\n\t\tclose(fd);\n\n\t\tRTE_LOG(DEBUG, EAL, \"IVSHMEM segment found, size: 0x%lx\\n\",\n\t\t\t\tms.len);\n\t}\n\n\treturn 0;\n}\n\n/* this happens at a later stage, after general EAL memory initialization */\nint\nrte_eal_ivshmem_obj_init(void)\n{\n\tstruct rte_ring_list* ring_list = NULL;\n\tstruct rte_mem_config * mcfg;\n\tstruct ivshmem_segment * seg;\n\tstruct rte_memzone * mz;\n\tstruct rte_ring * r;\n\tstruct rte_tailq_entry *te;\n\tunsigned i, ms, idx;\n\tuint64_t offset;\n\n\t/* secondary process would not need any object discovery - it'll all\n\t * already be in shared config */\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY || ivshmem_config == NULL)\n\t\treturn 0;\n\n\t/* check that we have an initialised ring tail queue */\n\tring_list = RTE_TAILQ_LOOKUP(RTE_TAILQ_RING_NAME, rte_ring_list);\n\tif (ring_list == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"No rte_ring tailq found!\\n\");\n\t\treturn -1;\n\t}\n\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\t/* create memzones */\n\tfor (i = 0; i < ivshmem_config->segment_idx && i <= RTE_MAX_MEMZONE; i++) {\n\n\t\tseg = &ivshmem_config->segment[i];\n\n\t\t/* add memzone */\n\t\tif (mcfg->memzone_cnt == RTE_MAX_MEMZONE) {\n\t\t\tRTE_LOG(ERR, EAL, \"No more memory zones available!\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tidx = mcfg->memzone_cnt;\n\n\t\tRTE_LOG(DEBUG, EAL, \"Found memzone: '%s' at %p (len 0x%\" PRIx64 \")\\n\",\n\t\t\t\tseg->entry.mz.name, seg->entry.mz.addr, seg->entry.mz.len);\n\n\t\tmemcpy(&mcfg->memzone[idx], &seg->entry.mz,\n\t\t\t\tsizeof(struct rte_memzone));\n\n\t\t/* find ioremap address */\n\t\tfor (ms = 0; ms <= RTE_MAX_MEMSEG; ms++) {\n\t\t\tif (ms == RTE_MAX_MEMSEG) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Physical address of segment not found!\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tif (CONTAINS(mcfg->memseg[ms], mcfg->memzone[idx])) {\n\t\t\t\toffset = mcfg->memzone[idx].addr_64 -\n\t\t\t\t\t\t\t\tmcfg->memseg[ms].addr_64;\n\t\t\t\tmcfg->memzone[idx].ioremap_addr = mcfg->memseg[ms].ioremap_addr +\n\t\t\t\t\t\toffset;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tmcfg->memzone_cnt++;\n\t}\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* find rings */\n\tfor (i = 0; i < mcfg->memzone_cnt; i++) {\n\t\tmz = &mcfg->memzone[i];\n\n\t\t/* check if memzone has a ring prefix */\n\t\tif (strncmp(mz->name, RTE_RING_MZ_PREFIX,\n\t\t\t\tsizeof(RTE_RING_MZ_PREFIX) - 1) != 0)\n\t\t\tcontinue;\n\n\t\tr = (struct rte_ring*) (mz->addr_64);\n\n\t\tte = rte_zmalloc(\"RING_TAILQ_ENTRY\", sizeof(*te), 0);\n\t\tif (te == NULL) {\n\t\t\tRTE_LOG(ERR, EAL, \"Cannot allocate ring tailq entry!\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tte->data = (void *) r;\n\n\t\tTAILQ_INSERT_TAIL(ring_list, te, next);\n\n\t\tRTE_LOG(DEBUG, EAL, \"Found ring: '%s' at %p\\n\", r->name, mz->addr);\n\t}\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n#ifdef RTE_LIBRTE_IVSHMEM_DEBUG\n\trte_memzone_dump(stdout);\n\trte_ring_list_dump(stdout);\n#endif\n\n\treturn 0;\n}\n\n/* initialize ivshmem structures */\nint rte_eal_ivshmem_init(void)\n{\n\tstruct rte_pci_device * dev;\n\tstruct rte_pci_resource * res;\n\tint fd, ret;\n\tchar path[PATH_MAX];\n\n\t/* initialize everything to 0 */\n\tmemset(path, 0, sizeof(path));\n\tivshmem_config = NULL;\n\n\tpagesz = getpagesize();\n\n\tRTE_LOG(DEBUG, EAL, \"Searching for IVSHMEM devices...\\n\");\n\n\tif (rte_eal_process_type() == RTE_PROC_SECONDARY) {\n\n\t\tif (open_shared_config() < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"Could not open IVSHMEM config!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\telse {\n\n\t\tTAILQ_FOREACH(dev, &pci_device_list, next) {\n\n\t\t\tif (is_ivshmem_device(dev)) {\n\n\t\t\t\t/* IVSHMEM memory is always on BAR2 */\n\t\t\t\tres = &dev->mem_resource[2];\n\n\t\t\t\t/* if we don't have a BAR2 */\n\t\t\t\tif (res->len == 0)\n\t\t\t\t\tcontinue;\n\n\t\t\t\t/* construct pci device path */\n\t\t\t\tsnprintf(path, sizeof(path), IVSHMEM_RESOURCE_PATH,\n\t\t\t\t\t\tdev->addr.domain, dev->addr.bus, dev->addr.devid,\n\t\t\t\t\t\tdev->addr.function);\n\n\t\t\t\t/* try to find memseg */\n\t\t\t\tfd = open(path, O_RDWR);\n\t\t\t\tif (fd < 0) {\n\t\t\t\t\tRTE_LOG(ERR, EAL, \"Could not open %s\\n\", path);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\n\t\t\t\t/* check if it's a DPDK IVSHMEM device */\n\t\t\t\tret = has_ivshmem_metadata(fd, res->len);\n\n\t\t\t\t/* is DPDK device */\n\t\t\t\tif (ret == 1) {\n\n\t\t\t\t\t/* config file creation is deferred until the first\n\t\t\t\t\t * DPDK device is found. then, it has to be created\n\t\t\t\t\t * only once. */\n\t\t\t\t\tif (ivshmem_config == NULL &&\n\t\t\t\t\t\t\tcreate_shared_config() < 0) {\n\t\t\t\t\t\tRTE_LOG(ERR, EAL, \"Could not create IVSHMEM config!\\n\");\n\t\t\t\t\t\tclose(fd);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\n\t\t\t\t\tif (read_metadata(path, sizeof(path), fd, res->len) < 0) {\n\t\t\t\t\t\tRTE_LOG(ERR, EAL, \"Could not read metadata from\"\n\t\t\t\t\t\t\t\t\" device %02x:%02x.%x!\\n\", dev->addr.bus,\n\t\t\t\t\t\t\t\tdev->addr.devid, dev->addr.function);\n\t\t\t\t\t\tclose(fd);\n\t\t\t\t\t\treturn -1;\n\t\t\t\t\t}\n\n\t\t\t\t\tif (ivshmem_config->pci_devs_idx == RTE_LIBRTE_IVSHMEM_MAX_PCI_DEVS) {\n\t\t\t\t\t\tRTE_LOG(WARNING, EAL,\n\t\t\t\t\t\t\t\t\"IVSHMEM PCI device limit exceeded. Increase \"\n\t\t\t\t\t\t\t\t\"CONFIG_RTE_LIBRTE_IVSHMEM_MAX_PCI_DEVS in \"\n\t\t\t\t\t\t\t\t\"your config file.\\n\");\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\n\t\t\t\t\tRTE_LOG(INFO, EAL, \"Found IVSHMEM device %02x:%02x.%x\\n\",\n\t\t\t\t\t\t\tdev->addr.bus, dev->addr.devid, dev->addr.function);\n\n\t\t\t\t\tivshmem_config->pci_devs[ivshmem_config->pci_devs_idx].ioremap_addr = res->phys_addr;\n\t\t\t\t\tsnprintf(ivshmem_config->pci_devs[ivshmem_config->pci_devs_idx].path,\n\t\t\t\t\t\t\tsizeof(ivshmem_config->pci_devs[ivshmem_config->pci_devs_idx].path),\n\t\t\t\t\t\t\t\"%s\", path);\n\n\t\t\t\t\tivshmem_config->pci_devs_idx++;\n\t\t\t\t}\n\t\t\t\t/* failed to read */\n\t\t\t\telse if (ret < 0) {\n\t\t\t\t\tRTE_LOG(ERR, EAL, \"Could not read IVSHMEM device: %s\\n\",\n\t\t\t\t\t\t\tstrerror(errno));\n\t\t\t\t\tclose(fd);\n\t\t\t\t\treturn -1;\n\t\t\t\t}\n\t\t\t\t/* not a DPDK device */\n\t\t\t\telse\n\t\t\t\t\tRTE_LOG(DEBUG, EAL, \"Skipping non-DPDK IVSHMEM device\\n\");\n\n\t\t\t\t/* close the BAR fd */\n\t\t\t\tclose(fd);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* ivshmem_config is not NULL only if config was created and/or mapped */\n\tif (ivshmem_config) {\n\t\tif (map_all_segments() < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"Mapping IVSHMEM segments failed!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\telse {\n\t\tRTE_LOG(DEBUG, EAL, \"No IVSHMEM configuration found! \\n\");\n\t}\n\n\treturn 0;\n}\n\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_lcore.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_filesystem.h\"\n#include \"eal_thread.h\"\n\n#define SYS_CPU_DIR \"/sys/devices/system/cpu/cpu%u\"\n#define CORE_ID_FILE \"topology/core_id\"\n#define NUMA_NODE_PATH \"/sys/devices/system/node\"\n\n/* Check if a cpu is present by the presence of the cpu information for it */\nint\neal_cpu_detected(unsigned lcore_id)\n{\n\tchar path[PATH_MAX];\n\tint len = snprintf(path, sizeof(path), SYS_CPU_DIR\n\t\t\"/\"CORE_ID_FILE, lcore_id);\n\tif (len <= 0 || (unsigned)len >= sizeof(path))\n\t\treturn 0;\n\tif (access(path, F_OK) != 0)\n\t\treturn 0;\n\n\treturn 1;\n}\n\n/*\n * Get CPU socket id (NUMA node) for a logical core.\n *\n * This searches each nodeX directories in /sys for the symlink for the given\n * lcore_id and returns the numa node where the lcore is found. If lcore is not\n * found on any numa node, returns zero.\n */\nunsigned\neal_cpu_socket_id(unsigned lcore_id)\n{\n\tunsigned socket;\n\n\tfor (socket = 0; socket < RTE_MAX_NUMA_NODES; socket++) {\n\t\tchar path[PATH_MAX];\n\n\t\tsnprintf(path, sizeof(path), \"%s/node%u/cpu%u\", NUMA_NODE_PATH,\n\t\t\t\tsocket, lcore_id);\n\t\tif (access(path, F_OK) == 0)\n\t\t\treturn socket;\n\t}\n\treturn 0;\n}\n\n/* Get the cpu core id value from the /sys/.../cpuX core_id value */\nunsigned\neal_cpu_core_id(unsigned lcore_id)\n{\n\tchar path[PATH_MAX];\n\tunsigned long id;\n\n\tint len = snprintf(path, sizeof(path), SYS_CPU_DIR \"/%s\", lcore_id, CORE_ID_FILE);\n\tif (len <= 0 || (unsigned)len >= sizeof(path))\n\t\tgoto err;\n\tif (eal_parse_sysfs_value(path, &id) != 0)\n\t\tgoto err;\n\treturn (unsigned)id;\n\nerr:\n\tRTE_LOG(ERR, EAL, \"Error reading core id value from %s \"\n\t\t\t\"for lcore %u - assuming core 0\\n\", SYS_CPU_DIR, lcore_id);\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_log.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n\n/*\n * default log function, used once mempool (hence log history) is\n * available\n */\nstatic ssize_t\nconsole_log_write(__attribute__((unused)) void *c, const char *buf, size_t size)\n{\n\tchar copybuf[BUFSIZ + 1];\n\tssize_t ret;\n\tuint32_t loglevel;\n\n\t/* add this log in history */\n\trte_log_add_in_history(buf, size);\n\n\t/* write on stdout */\n\tret = fwrite(buf, 1, size, stdout);\n\tfflush(stdout);\n\n\t/* truncate message if too big (should not happen) */\n\tif (size > BUFSIZ)\n\t\tsize = BUFSIZ;\n\n\t/* Syslog error levels are from 0 to 7, so subtract 1 to convert */\n\tloglevel = rte_log_cur_msg_loglevel() - 1;\n\tmemcpy(copybuf, buf, size);\n\tcopybuf[size] = '\\0';\n\n\t/* write on syslog too */\n\tsyslog(loglevel, \"%s\", copybuf);\n\n\treturn ret;\n}\n\nstatic cookie_io_functions_t console_log_func = {\n\t.write = console_log_write,\n};\n\n/*\n * set the log to default function, called during eal init process,\n * once memzones are available.\n */\nint\nrte_eal_log_init(const char *id, int facility)\n{\n\tFILE *log_stream;\n\n\tlog_stream = fopencookie(NULL, \"w+\", console_log_func);\n\tif (log_stream == NULL)\n\t\treturn -1;\n\n\topenlog(id, LOG_NDELAY | LOG_PID, facility);\n\n\tif (rte_eal_common_log_init(log_stream) < 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/* early logs */\n\n/*\n * early log function, used during boot when mempool (hence log\n * history) is not available\n */\nstatic ssize_t\nearly_log_write(__attribute__((unused)) void *c, const char *buf, size_t size)\n{\n\tssize_t ret;\n\tret = fwrite(buf, size, 1, stdout);\n\tfflush(stdout);\n\tif (ret == 0)\n\t\treturn -1;\n\treturn ret;\n}\n\nstatic cookie_io_functions_t early_log_func = {\n\t.write = early_log_write,\n};\nstatic FILE *early_log_stream;\n\n/*\n * init the log library, called by rte_eal_init() to enable early\n * logs\n */\nint\nrte_eal_log_early_init(void)\n{\n\tearly_log_stream = fopencookie(NULL, \"w+\", early_log_func);\n\tif (early_log_stream == NULL) {\n\t\tprintf(\"Cannot configure early_log_stream\\n\");\n\t\treturn -1;\n\t}\n\trte_openlog_stream(early_log_stream);\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_memory.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n/* BSD LICENSE\n *\n * Copyright(c) 2013 6WIND.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#define _FILE_OFFSET_BITS 64\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_internal_cfg.h\"\n#include \"eal_filesystem.h\"\n#include \"eal_hugepages.h\"\n\n/**\n * @file\n * Huge page mapping under linux\n *\n * To reserve a big contiguous amount of memory, we use the hugepage\n * feature of linux. For that, we need to have hugetlbfs mounted. This\n * code will create many files in this directory (one per page) and\n * map them in virtual memory. For each page, we will retrieve its\n * physical address and remap it in order to have a virtual contiguous\n * zone as well as a physical contiguous zone.\n */\n\nstatic uint64_t baseaddr_offset;\n\nstatic unsigned proc_pagemap_readable;\n\n#define RANDOMIZE_VA_SPACE_FILE \"/proc/sys/kernel/randomize_va_space\"\n\nstatic void\ntest_proc_pagemap_readable(void)\n{\n\tint fd = open(\"/proc/self/pagemap\", O_RDONLY);\n\n\tif (fd < 0) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Cannot open /proc/self/pagemap: %s. \"\n\t\t\t\"virt2phys address translation will not work\\n\",\n\t\t\tstrerror(errno));\n\t\treturn;\n\t}\n\n\t/* Is readable */\n\tclose(fd);\n\tproc_pagemap_readable = 1;\n}\n\n/* Lock page in physical memory and prevent from swapping. */\nint\nrte_mem_lock_page(const void *virt)\n{\n\tunsigned long virtual = (unsigned long)virt;\n\tint page_size = getpagesize();\n\tunsigned long aligned = (virtual & ~ (page_size - 1));\n\treturn mlock((void*)aligned, page_size);\n}\n\n/*\n * Get physical address of any mapped virtual address in the current process.\n */\nphys_addr_t\nrte_mem_virt2phy(const void *virtaddr)\n{\n\tint fd;\n\tuint64_t page, physaddr;\n\tunsigned long virt_pfn;\n\tint page_size;\n\toff_t offset;\n\n\t/* Cannot parse /proc/self/pagemap, no need to log errors everywhere */\n\tif (!proc_pagemap_readable)\n\t\treturn RTE_BAD_PHYS_ADDR;\n\n\t/* standard page size */\n\tpage_size = getpagesize();\n\n\tfd = open(\"/proc/self/pagemap\", O_RDONLY);\n\tif (fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot open /proc/self/pagemap: %s\\n\",\n\t\t\t__func__, strerror(errno));\n\t\treturn RTE_BAD_PHYS_ADDR;\n\t}\n\n\tvirt_pfn = (unsigned long)virtaddr / page_size;\n\toffset = sizeof(uint64_t) * virt_pfn;\n\tif (lseek(fd, offset, SEEK_SET) == (off_t) -1) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): seek error in /proc/self/pagemap: %s\\n\",\n\t\t\t\t__func__, strerror(errno));\n\t\tclose(fd);\n\t\treturn RTE_BAD_PHYS_ADDR;\n\t}\n\tif (read(fd, &page, sizeof(uint64_t)) < 0) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot read /proc/self/pagemap: %s\\n\",\n\t\t\t\t__func__, strerror(errno));\n\t\tclose(fd);\n\t\treturn RTE_BAD_PHYS_ADDR;\n\t}\n\n\t/*\n\t * the pfn (page frame number) are bits 0-54 (see\n\t * pagemap.txt in linux Documentation)\n\t */\n\tphysaddr = ((page & 0x7fffffffffffffULL) * page_size)\n\t\t+ ((unsigned long)virtaddr % page_size);\n\tclose(fd);\n\treturn physaddr;\n}\n\n/*\n * For each hugepage in hugepg_tbl, fill the physaddr value. We find\n * it by browsing the /proc/self/pagemap special file.\n */\nstatic int\nfind_physaddrs(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi)\n{\n\tunsigned i;\n\tphys_addr_t addr;\n\n\tfor (i = 0; i < hpi->num_pages[0]; i++) {\n\t\taddr = rte_mem_virt2phy(hugepg_tbl[i].orig_va);\n\t\tif (addr == RTE_BAD_PHYS_ADDR)\n\t\t\treturn -1;\n\t\thugepg_tbl[i].physaddr = addr;\n\t}\n\treturn 0;\n}\n\n/*\n * Check whether address-space layout randomization is enabled in\n * the kernel. This is important for multi-process as it can prevent\n * two processes mapping data to the same virtual address\n * Returns:\n * 0 - address space randomization disabled\n * 1/2 - address space randomization enabled\n * negative error code on error\n */\nstatic int\naslr_enabled(void)\n{\n\tchar c;\n\tint retval, fd = open(RANDOMIZE_VA_SPACE_FILE, O_RDONLY);\n\tif (fd < 0)\n\t\treturn -errno;\n\tretval = read(fd, &c, 1);\n\tclose(fd);\n\tif (retval < 0)\n\t\treturn -errno;\n\tif (retval == 0)\n\t\treturn -EIO;\n\tswitch (c) {\n\t\tcase '0' : return 0;\n\t\tcase '1' : return 1;\n\t\tcase '2' : return 2;\n\t\tdefault: return -EINVAL;\n\t}\n}\n\n/*\n * Try to mmap *size bytes in /dev/zero. If it is successful, return the\n * pointer to the mmap'd area and keep *size unmodified. Else, retry\n * with a smaller zone: decrease *size by hugepage_sz until it reaches\n * 0. In this case, return NULL. Note: this function returns an address\n * which is a multiple of hugepage size.\n */\nstatic void *\nget_virtual_area(size_t *size, size_t hugepage_sz)\n{\n\tvoid *addr;\n\tint fd;\n\tlong aligned_addr;\n\n\tif (internal_config.base_virtaddr != 0) {\n\t\taddr = (void*) (uintptr_t) (internal_config.base_virtaddr +\n\t\t\t\tbaseaddr_offset);\n\t}\n\telse addr = NULL;\n\n\tRTE_LOG(DEBUG, EAL, \"Ask a virtual area of 0x%zx bytes\\n\", *size);\n\n\tfd = open(\"/dev/zero\", O_RDONLY);\n\tif (fd < 0){\n\t\tRTE_LOG(ERR, EAL, \"Cannot open /dev/zero\\n\");\n\t\treturn NULL;\n\t}\n\tdo {\n\t\taddr = mmap(addr,\n\t\t\t\t(*size) + hugepage_sz, PROT_READ, MAP_PRIVATE, fd, 0);\n\t\tif (addr == MAP_FAILED)\n\t\t\t*size -= hugepage_sz;\n\t} while (addr == MAP_FAILED && *size > 0);\n\n\tif (addr == MAP_FAILED) {\n\t\tclose(fd);\n\t\tRTE_LOG(ERR, EAL, \"Cannot get a virtual area: %s\\n\",\n\t\t\tstrerror(errno));\n\t\treturn NULL;\n\t}\n\n\tmunmap(addr, (*size) + hugepage_sz);\n\tclose(fd);\n\n\t/* align addr to a huge page size boundary */\n\taligned_addr = (long)addr;\n\taligned_addr += (hugepage_sz - 1);\n\taligned_addr &= (~(hugepage_sz - 1));\n\taddr = (void *)(aligned_addr);\n\n\tRTE_LOG(DEBUG, EAL, \"Virtual area found at %p (size = 0x%zx)\\n\",\n\t\taddr, *size);\n\n\t/* increment offset */\n\tbaseaddr_offset += *size;\n\n\treturn addr;\n}\n\n/*\n * Mmap all hugepages of hugepage table: it first open a file in\n * hugetlbfs, then mmap() hugepage_sz data in it. If orig is set, the\n * virtual address is stored in hugepg_tbl[i].orig_va, else it is stored\n * in hugepg_tbl[i].final_va. The second mapping (when orig is 0) tries to\n * map continguous physical blocks in contiguous virtual blocks.\n */\nstatic int\nmap_all_hugepages(struct hugepage_file *hugepg_tbl,\n\t\tstruct hugepage_info *hpi, int orig)\n{\n\tint fd;\n\tunsigned i;\n\tvoid *virtaddr;\n\tvoid *vma_addr = NULL;\n\tsize_t vma_len = 0;\n\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\tRTE_SET_USED(vma_len);\n#endif\n\n\tfor (i = 0; i < hpi->num_pages[0]; i++) {\n\t\tuint64_t hugepage_sz = hpi->hugepage_sz;\n\n\t\tif (orig) {\n\t\t\thugepg_tbl[i].file_id = i;\n\t\t\thugepg_tbl[i].size = hugepage_sz;\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\t\t\teal_get_hugefile_temp_path(hugepg_tbl[i].filepath,\n\t\t\t\t\tsizeof(hugepg_tbl[i].filepath), hpi->hugedir,\n\t\t\t\t\thugepg_tbl[i].file_id);\n#else\n\t\t\teal_get_hugefile_path(hugepg_tbl[i].filepath,\n\t\t\t\t\tsizeof(hugepg_tbl[i].filepath), hpi->hugedir,\n\t\t\t\t\thugepg_tbl[i].file_id);\n#endif\n\t\t\thugepg_tbl[i].filepath[sizeof(hugepg_tbl[i].filepath) - 1] = '\\0';\n\t\t}\n#ifndef RTE_ARCH_64\n\t\t/* for 32-bit systems, don't remap 1G and 16G pages, just reuse\n\t\t * original map address as final map address.\n\t\t */\n\t\telse if ((hugepage_sz == RTE_PGSIZE_1G)\n\t\t\t|| (hugepage_sz == RTE_PGSIZE_16G)) {\n\t\t\thugepg_tbl[i].final_va = hugepg_tbl[i].orig_va;\n\t\t\thugepg_tbl[i].orig_va = NULL;\n\t\t\tcontinue;\n\t\t}\n#endif\n\n#ifndef RTE_EAL_SINGLE_FILE_SEGMENTS\n\t\telse if (vma_len == 0) {\n\t\t\tunsigned j, num_pages;\n\n\t\t\t/* reserve a virtual area for next contiguous\n\t\t\t * physical block: count the number of\n\t\t\t * contiguous physical pages. */\n\t\t\tfor (j = i+1; j < hpi->num_pages[0] ; j++) {\n#ifdef RTE_ARCH_PPC_64\n\t\t\t\t/* The physical addresses are sorted in\n\t\t\t\t * descending order on PPC64 */\n\t\t\t\tif (hugepg_tbl[j].physaddr !=\n\t\t\t\t hugepg_tbl[j-1].physaddr - hugepage_sz)\n\t\t\t\t\tbreak;\n#else\n\t\t\t\tif (hugepg_tbl[j].physaddr !=\n\t\t\t\t hugepg_tbl[j-1].physaddr + hugepage_sz)\n\t\t\t\t\tbreak;\n#endif\n\t\t\t}\n\t\t\tnum_pages = j - i;\n\t\t\tvma_len = num_pages * hugepage_sz;\n\n\t\t\t/* get the biggest virtual memory area up to\n\t\t\t * vma_len. If it fails, vma_addr is NULL, so\n\t\t\t * let the kernel provide the address. */\n\t\t\tvma_addr = get_virtual_area(&vma_len, hpi->hugepage_sz);\n\t\t\tif (vma_addr == NULL)\n\t\t\t\tvma_len = hugepage_sz;\n\t\t}\n#endif\n\n\t\t/* try to create hugepage file */\n\t\tfd = open(hugepg_tbl[i].filepath, O_CREAT | O_RDWR, 0755);\n\t\tif (fd < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"%s(): open failed: %s\\n\", __func__,\n\t\t\t\t\tstrerror(errno));\n\t\t\treturn -1;\n\t\t}\n\n\t\tvirtaddr = mmap(vma_addr, hugepage_sz, PROT_READ | PROT_WRITE,\n\t\t\t\tMAP_SHARED, fd, 0);\n\t\tif (virtaddr == MAP_FAILED) {\n\t\t\tRTE_LOG(ERR, EAL, \"%s(): mmap failed: %s\\n\", __func__,\n\t\t\t\t\tstrerror(errno));\n\t\t\tclose(fd);\n\t\t\treturn -1;\n\t\t}\n\n\t\tif (orig) {\n\t\t\thugepg_tbl[i].orig_va = virtaddr;\n\t\t\tmemset(virtaddr, 0, hugepage_sz);\n\t\t}\n\t\telse {\n\t\t\thugepg_tbl[i].final_va = virtaddr;\n\t\t}\n\n\t\t/* set shared flock on the file. */\n\t\tif (flock(fd, LOCK_SH | LOCK_NB) == -1) {\n\t\t\tRTE_LOG(ERR, EAL, \"%s(): Locking file failed:%s \\n\",\n\t\t\t\t__func__, strerror(errno));\n\t\t\tclose(fd);\n\t\t\treturn -1;\n\t\t}\n\n\t\tclose(fd);\n\n\t\tvma_addr = (char *)vma_addr + hugepage_sz;\n\t\tvma_len -= hugepage_sz;\n\t}\n\treturn 0;\n}\n\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\n/*\n * Remaps all hugepages into single file segments\n */\nstatic int\nremap_all_hugepages(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi)\n{\n\tint fd;\n\tunsigned i = 0, j, num_pages, page_idx = 0;\n\tvoid *vma_addr = NULL, *old_addr = NULL, *page_addr = NULL;\n\tsize_t vma_len = 0;\n\tsize_t hugepage_sz = hpi->hugepage_sz;\n\tsize_t total_size, offset;\n\tchar filepath[MAX_HUGEPAGE_PATH];\n\tphys_addr_t physaddr;\n\tint socket;\n\n\twhile (i < hpi->num_pages[0]) {\n\n#ifndef RTE_ARCH_64\n\t\t/* for 32-bit systems, don't remap 1G pages and 16G pages,\n\t\t * just reuse original map address as final map address.\n\t\t */\n\t\tif ((hugepage_sz == RTE_PGSIZE_1G)\n\t\t\t|| (hugepage_sz == RTE_PGSIZE_16G)) {\n\t\t\thugepg_tbl[i].final_va = hugepg_tbl[i].orig_va;\n\t\t\thugepg_tbl[i].orig_va = NULL;\n\t\t\ti++;\n\t\t\tcontinue;\n\t\t}\n#endif\n\n\t\t/* reserve a virtual area for next contiguous\n\t\t * physical block: count the number of\n\t\t * contiguous physical pages. */\n\t\tfor (j = i+1; j < hpi->num_pages[0] ; j++) {\n#ifdef RTE_ARCH_PPC_64\n\t\t\t/* The physical addresses are sorted in descending\n\t\t\t * order on PPC64 */\n\t\t\tif (hugepg_tbl[j].physaddr !=\n\t\t\t\thugepg_tbl[j-1].physaddr - hugepage_sz)\n\t\t\t\tbreak;\n#else\n\t\t\tif (hugepg_tbl[j].physaddr !=\n\t\t\t\thugepg_tbl[j-1].physaddr + hugepage_sz)\n\t\t\t\tbreak;\n#endif\n\t\t}\n\t\tnum_pages = j - i;\n\t\tvma_len = num_pages * hugepage_sz;\n\n\t\tsocket = hugepg_tbl[i].socket_id;\n\n\t\t/* get the biggest virtual memory area up to\n\t\t * vma_len. If it fails, vma_addr is NULL, so\n\t\t * let the kernel provide the address. */\n\t\tvma_addr = get_virtual_area(&vma_len, hpi->hugepage_sz);\n\n\t\t/* If we can't find a big enough virtual area, work out how many pages\n\t\t * we are going to get */\n\t\tif (vma_addr == NULL)\n\t\t\tj = i + 1;\n\t\telse if (vma_len != num_pages * hugepage_sz) {\n\t\t\tnum_pages = vma_len / hugepage_sz;\n\t\t\tj = i + num_pages;\n\n\t\t}\n\n\t\thugepg_tbl[page_idx].file_id = page_idx;\n\t\teal_get_hugefile_path(filepath,\n\t\t\t\tsizeof(filepath),\n\t\t\t\thpi->hugedir,\n\t\t\t\thugepg_tbl[page_idx].file_id);\n\n\t\t/* try to create hugepage file */\n\t\tfd = open(filepath, O_CREAT | O_RDWR, 0755);\n\t\tif (fd < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"%s(): open failed: %s\\n\", __func__, strerror(errno));\n\t\t\treturn -1;\n\t\t}\n\n\t\ttotal_size = 0;\n\t\tfor (;i < j; i++) {\n\n\t\t\t/* unmap current segment */\n\t\t\tif (total_size > 0)\n\t\t\t\tmunmap(vma_addr, total_size);\n\n\t\t\t/* unmap original page */\n\t\t\tmunmap(hugepg_tbl[i].orig_va, hugepage_sz);\n\t\t\tunlink(hugepg_tbl[i].filepath);\n\n\t\t\ttotal_size += hugepage_sz;\n\n\t\t\told_addr = vma_addr;\n\n\t\t\t/* map new, bigger segment */\n\t\t\tvma_addr = mmap(vma_addr, total_size,\n\t\t\t\t\tPROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);\n\n\t\t\tif (vma_addr == MAP_FAILED || vma_addr != old_addr) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"%s(): mmap failed: %s\\n\", __func__, strerror(errno));\n\t\t\t\tclose(fd);\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\t/* touch the page. this is needed because kernel postpones mapping\n\t\t\t * creation until the first page fault. with this, we pin down\n\t\t\t * the page and it is marked as used and gets into process' pagemap.\n\t\t\t */\n\t\t\tfor (offset = 0; offset < total_size; offset += hugepage_sz)\n\t\t\t\t*((volatile uint8_t*) RTE_PTR_ADD(vma_addr, offset));\n\t\t}\n\n\t\t/* set shared flock on the file. */\n\t\tif (flock(fd, LOCK_SH | LOCK_NB) == -1) {\n\t\t\tRTE_LOG(ERR, EAL, \"%s(): Locking file failed:%s \\n\",\n\t\t\t\t__func__, strerror(errno));\n\t\t\tclose(fd);\n\t\t\treturn -1;\n\t\t}\n\n\t\tsnprintf(hugepg_tbl[page_idx].filepath, MAX_HUGEPAGE_PATH, \"%s\",\n\t\t\t\tfilepath);\n\n\t\tphysaddr = rte_mem_virt2phy(vma_addr);\n\n\t\tif (physaddr == RTE_BAD_PHYS_ADDR)\n\t\t\treturn -1;\n\n\t\thugepg_tbl[page_idx].final_va = vma_addr;\n\n\t\thugepg_tbl[page_idx].physaddr = physaddr;\n\n\t\thugepg_tbl[page_idx].repeated = num_pages;\n\n\t\thugepg_tbl[page_idx].socket_id = socket;\n\n\t\tclose(fd);\n\n\t\t/* verify the memory segment - that is, check that every VA corresponds\n\t\t * to the physical address we expect to see\n\t\t */\n\t\tfor (offset = 0; offset < vma_len; offset += hugepage_sz) {\n\t\t\tuint64_t expected_physaddr;\n\n\t\t\texpected_physaddr = hugepg_tbl[page_idx].physaddr + offset;\n\t\t\tpage_addr = RTE_PTR_ADD(vma_addr, offset);\n\t\t\tphysaddr = rte_mem_virt2phy(page_addr);\n\n\t\t\tif (physaddr != expected_physaddr) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Segment sanity check failed: wrong physaddr \"\n\t\t\t\t\t\t\"at %p (offset 0x%\" PRIx64 \": 0x%\" PRIx64\n\t\t\t\t\t\t\" (expected 0x%\" PRIx64 \")\\n\",\n\t\t\t\t\t\tpage_addr, offset, physaddr, expected_physaddr);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t}\n\n\t\t/* zero out the whole segment */\n\t\tmemset(hugepg_tbl[page_idx].final_va, 0, total_size);\n\n\t\tpage_idx++;\n\t}\n\n\t/* zero out the rest */\n\tmemset(&hugepg_tbl[page_idx], 0, (hpi->num_pages[0] - page_idx) * sizeof(struct hugepage_file));\n\treturn page_idx;\n}\n#else/* RTE_EAL_SINGLE_FILE_SEGMENTS=n */\n\n/* Unmap all hugepages from original mapping */\nstatic int\nunmap_all_hugepages_orig(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi)\n{\n unsigned i;\n for (i = 0; i < hpi->num_pages[0]; i++) {\n if (hugepg_tbl[i].orig_va) {\n munmap(hugepg_tbl[i].orig_va, hpi->hugepage_sz);\n hugepg_tbl[i].orig_va = NULL;\n }\n }\n return 0;\n}\n#endif /* RTE_EAL_SINGLE_FILE_SEGMENTS */\n\n/*\n * Parse /proc/self/numa_maps to get the NUMA socket ID for each huge\n * page.\n */\nstatic int\nfind_numasocket(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi)\n{\n\tint socket_id;\n\tchar *end, *nodestr;\n\tunsigned i, hp_count = 0;\n\tuint64_t virt_addr;\n\tchar buf[BUFSIZ];\n\tchar hugedir_str[PATH_MAX];\n\tFILE *f;\n\n\tf = fopen(\"/proc/self/numa_maps\", \"r\");\n\tif (f == NULL) {\n\t\tRTE_LOG(NOTICE, EAL, \"cannot open /proc/self/numa_maps,\"\n\t\t\t\t\" consider that all memory is in socket_id 0\\n\");\n\t\treturn 0;\n\t}\n\n\tsnprintf(hugedir_str, sizeof(hugedir_str),\n\t\t\t\"%s/%s\", hpi->hugedir, internal_config.hugefile_prefix);\n\n\t/* parse numa map */\n\twhile (fgets(buf, sizeof(buf), f) != NULL) {\n\n\t\t/* ignore non huge page */\n\t\tif (strstr(buf, \" huge \") == NULL &&\n\t\t\t\tstrstr(buf, hugedir_str) == NULL)\n\t\t\tcontinue;\n\n\t\t/* get zone addr */\n\t\tvirt_addr = strtoull(buf, &end, 16);\n\t\tif (virt_addr == 0 || end == buf) {\n\t\t\tRTE_LOG(ERR, EAL, \"%s(): error in numa_maps parsing\\n\", __func__);\n\t\t\tgoto error;\n\t\t}\n\n\t\t/* get node id (socket id) */\n\t\tnodestr = strstr(buf, \" N\");\n\t\tif (nodestr == NULL) {\n\t\t\tRTE_LOG(ERR, EAL, \"%s(): error in numa_maps parsing\\n\", __func__);\n\t\t\tgoto error;\n\t\t}\n\t\tnodestr += 2;\n\t\tend = strstr(nodestr, \"=\");\n\t\tif (end == NULL) {\n\t\t\tRTE_LOG(ERR, EAL, \"%s(): error in numa_maps parsing\\n\", __func__);\n\t\t\tgoto error;\n\t\t}\n\t\tend[0] = '\\0';\n\t\tend = NULL;\n\n\t\tsocket_id = strtoul(nodestr, &end, 0);\n\t\tif ((nodestr[0] == '\\0') || (end == NULL) || (*end != '\\0')) {\n\t\t\tRTE_LOG(ERR, EAL, \"%s(): error in numa_maps parsing\\n\", __func__);\n\t\t\tgoto error;\n\t\t}\n\n\t\t/* if we find this page in our mappings, set socket_id */\n\t\tfor (i = 0; i < hpi->num_pages[0]; i++) {\n\t\t\tvoid *va = (void *)(unsigned long)virt_addr;\n\t\t\tif (hugepg_tbl[i].orig_va == va) {\n\t\t\t\thugepg_tbl[i].socket_id = socket_id;\n\t\t\t\thp_count++;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (hp_count < hpi->num_pages[0])\n\t\tgoto error;\n\n\tfclose(f);\n\treturn 0;\n\nerror:\n\tfclose(f);\n\treturn -1;\n}\n\n/*\n * Sort the hugepg_tbl by physical address (lower addresses first on x86,\n * higher address first on powerpc). We use a slow algorithm, but we won't\n * have millions of pages, and this is only done at init time.\n */\nstatic int\nsort_by_physaddr(struct hugepage_file *hugepg_tbl, struct hugepage_info *hpi)\n{\n\tunsigned i, j;\n\tint compare_idx;\n\tuint64_t compare_addr;\n\tstruct hugepage_file tmp;\n\n\tfor (i = 0; i < hpi->num_pages[0]; i++) {\n\t\tcompare_addr = 0;\n\t\tcompare_idx = -1;\n\n\t\t/*\n\t\t * browse all entries starting at 'i', and find the\n\t\t * entry with the smallest addr\n\t\t */\n\t\tfor (j=i; j< hpi->num_pages[0]; j++) {\n\n\t\t\tif (compare_addr == 0 ||\n#ifdef RTE_ARCH_PPC_64\n\t\t\t\thugepg_tbl[j].physaddr > compare_addr) {\n#else\n\t\t\t\thugepg_tbl[j].physaddr < compare_addr) {\n#endif\n\t\t\t\tcompare_addr = hugepg_tbl[j].physaddr;\n\t\t\t\tcompare_idx = j;\n\t\t\t}\n\t\t}\n\n\t\t/* should not happen */\n\t\tif (compare_idx == -1) {\n\t\t\tRTE_LOG(ERR, EAL, \"%s(): error in physaddr sorting\\n\", __func__);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* swap the 2 entries in the table */\n\t\tmemcpy(&tmp, &hugepg_tbl[compare_idx],\n\t\t\tsizeof(struct hugepage_file));\n\t\tmemcpy(&hugepg_tbl[compare_idx], &hugepg_tbl[i],\n\t\t\tsizeof(struct hugepage_file));\n\t\tmemcpy(&hugepg_tbl[i], &tmp, sizeof(struct hugepage_file));\n\t}\n\treturn 0;\n}\n\n/*\n * Uses mmap to create a shared memory area for storage of data\n * Used in this file to store the hugepage file map on disk\n */\nstatic void *\ncreate_shared_memory(const char *filename, const size_t mem_size)\n{\n\tvoid *retval;\n\tint fd = open(filename, O_CREAT | O_RDWR, 0666);\n\tif (fd < 0)\n\t\treturn NULL;\n\tif (ftruncate(fd, mem_size) < 0) {\n\t\tclose(fd);\n\t\treturn NULL;\n\t}\n\tretval = mmap(NULL, mem_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);\n\tclose(fd);\n\treturn retval;\n}\n\n/*\n * this copies *active* hugepages from one hugepage table to another.\n * destination is typically the shared memory.\n */\nstatic int\ncopy_hugepages_to_shared_mem(struct hugepage_file * dst, int dest_size,\n\t\tconst struct hugepage_file * src, int src_size)\n{\n\tint src_pos, dst_pos = 0;\n\n\tfor (src_pos = 0; src_pos < src_size; src_pos++) {\n\t\tif (src[src_pos].final_va != NULL) {\n\t\t\t/* error on overflow attempt */\n\t\t\tif (dst_pos == dest_size)\n\t\t\t\treturn -1;\n\t\t\tmemcpy(&dst[dst_pos], &src[src_pos], sizeof(struct hugepage_file));\n\t\t\tdst_pos++;\n\t\t}\n\t}\n\treturn 0;\n}\n\n/*\n * unmaps hugepages that are not going to be used. since we originally allocate\n * ALL hugepages (not just those we need), additional unmapping needs to be done.\n */\nstatic int\nunmap_unneeded_hugepages(struct hugepage_file *hugepg_tbl,\n\t\tstruct hugepage_info *hpi,\n\t\tunsigned num_hp_info)\n{\n\tunsigned socket, size;\n\tint page, nrpages = 0;\n\n\t/* get total number of hugepages */\n\tfor (size = 0; size < num_hp_info; size++)\n\t\tfor (socket = 0; socket < RTE_MAX_NUMA_NODES; socket++)\n\t\t\tnrpages += internal_config.hugepage_info[size].num_pages[socket];\n\n\tfor (size = 0; size < num_hp_info; size++) {\n\t\tfor (socket = 0; socket < RTE_MAX_NUMA_NODES; socket++) {\n\t\t\tunsigned pages_found = 0;\n\n\t\t\t/* traverse until we have unmapped all the unused pages */\n\t\t\tfor (page = 0; page < nrpages; page++) {\n\t\t\t\tstruct hugepage_file *hp = &hugepg_tbl[page];\n\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\t\t\t\t/* if this page was already cleared */\n\t\t\t\tif (hp->final_va == NULL)\n\t\t\t\t\tcontinue;\n#endif\n\n\t\t\t\t/* find a page that matches the criteria */\n\t\t\t\tif ((hp->size == hpi[size].hugepage_sz) &&\n\t\t\t\t\t\t(hp->socket_id == (int) socket)) {\n\n\t\t\t\t\t/* if we skipped enough pages, unmap the rest */\n\t\t\t\t\tif (pages_found == hpi[size].num_pages[socket]) {\n\t\t\t\t\t\tuint64_t unmap_len;\n\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\t\t\t\t\t\tunmap_len = hp->size * hp->repeated;\n#else\n\t\t\t\t\t\tunmap_len = hp->size;\n#endif\n\n\t\t\t\t\t\t/* get start addr and len of the remaining segment */\n\t\t\t\t\t\tmunmap(hp->final_va, (size_t) unmap_len);\n\n\t\t\t\t\t\thp->final_va = NULL;\n\t\t\t\t\t\tif (unlink(hp->filepath) == -1) {\n\t\t\t\t\t\t\tRTE_LOG(ERR, EAL, \"%s(): Removing %s failed: %s\\n\",\n\t\t\t\t\t\t\t\t\t__func__, hp->filepath, strerror(errno));\n\t\t\t\t\t\t\treturn -1;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\t\t\t\t\t/* else, check how much do we need to map */\n\t\t\t\t\telse {\n\t\t\t\t\t\tint nr_pg_left =\n\t\t\t\t\t\t\t\thpi[size].num_pages[socket] - pages_found;\n\n\t\t\t\t\t\t/* if we need enough memory to fit into the segment */\n\t\t\t\t\t\tif (hp->repeated <= nr_pg_left) {\n\t\t\t\t\t\t\tpages_found += hp->repeated;\n\t\t\t\t\t\t}\n\t\t\t\t\t\t/* truncate the segment */\n\t\t\t\t\t\telse {\n\t\t\t\t\t\t\tuint64_t final_size = nr_pg_left * hp->size;\n\t\t\t\t\t\t\tuint64_t seg_size = hp->repeated * hp->size;\n\n\t\t\t\t\t\t\tvoid * unmap_va = RTE_PTR_ADD(hp->final_va,\n\t\t\t\t\t\t\t\t\tfinal_size);\n\t\t\t\t\t\t\tint fd;\n\n\t\t\t\t\t\t\tmunmap(unmap_va, seg_size - final_size);\n\n\t\t\t\t\t\t\tfd = open(hp->filepath, O_RDWR);\n\t\t\t\t\t\t\tif (fd < 0) {\n\t\t\t\t\t\t\t\tRTE_LOG(ERR, EAL, \"Cannot open %s: %s\\n\",\n\t\t\t\t\t\t\t\t\t\thp->filepath, strerror(errno));\n\t\t\t\t\t\t\t\treturn -1;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tif (ftruncate(fd, final_size) < 0) {\n\t\t\t\t\t\t\t\tRTE_LOG(ERR, EAL, \"Cannot truncate %s: %s\\n\",\n\t\t\t\t\t\t\t\t\t\thp->filepath, strerror(errno));\n\t\t\t\t\t\t\t\treturn -1;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\tclose(fd);\n\n\t\t\t\t\t\t\tpages_found += nr_pg_left;\n\t\t\t\t\t\t\thp->repeated = nr_pg_left;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n#else\n\t\t\t\t\t/* else, lock the page and skip */\n\t\t\t\t\telse\n\t\t\t\t\t\tpages_found++;\n#endif\n\n\t\t\t\t} /* match page */\n\t\t\t} /* foreach page */\n\t\t} /* foreach socket */\n\t} /* foreach pagesize */\n\n\treturn 0;\n}\n\nstatic inline uint64_t\nget_socket_mem_size(int socket)\n{\n\tuint64_t size = 0;\n\tunsigned i;\n\n\tfor (i = 0; i < internal_config.num_hugepage_sizes; i++){\n\t\tstruct hugepage_info *hpi = &internal_config.hugepage_info[i];\n\t\tif (hpi->hugedir != NULL)\n\t\t\tsize += hpi->hugepage_sz * hpi->num_pages[socket];\n\t}\n\n\treturn size;\n}\n\n/*\n * This function is a NUMA-aware equivalent of calc_num_pages.\n * It takes in the list of hugepage sizes and the\n * number of pages thereof, and calculates the best number of\n * pages of each size to fulfill the request for ram\n */\nstatic int\ncalc_num_pages_per_socket(uint64_t * memory,\n\t\tstruct hugepage_info *hp_info,\n\t\tstruct hugepage_info *hp_used,\n\t\tunsigned num_hp_info)\n{\n\tunsigned socket, j, i = 0;\n\tunsigned requested, available;\n\tint total_num_pages = 0;\n\tuint64_t remaining_mem, cur_mem;\n\tuint64_t total_mem = internal_config.memory;\n\n\tif (num_hp_info == 0)\n\t\treturn -1;\n\n\t/* if specific memory amounts per socket weren't requested */\n\tif (internal_config.force_sockets == 0) {\n\t\tint cpu_per_socket[RTE_MAX_NUMA_NODES];\n\t\tsize_t default_size, total_size;\n\t\tunsigned lcore_id;\n\n\t\t/* Compute number of cores per socket */\n\t\tmemset(cpu_per_socket, 0, sizeof(cpu_per_socket));\n\t\tRTE_LCORE_FOREACH(lcore_id) {\n\t\t\tcpu_per_socket[rte_lcore_to_socket_id(lcore_id)]++;\n\t\t}\n\n\t\t/*\n\t\t * Automatically spread requested memory amongst detected sockets according\n\t\t * to number of cores from cpu mask present on each socket\n\t\t */\n\t\ttotal_size = internal_config.memory;\n\t\tfor (socket = 0; socket < RTE_MAX_NUMA_NODES && total_size != 0; socket++) {\n\n\t\t\t/* Set memory amount per socket */\n\t\t\tdefault_size = (internal_config.memory * cpu_per_socket[socket])\n\t\t\t / rte_lcore_count();\n\n\t\t\t/* Limit to maximum available memory on socket */\n\t\t\tdefault_size = RTE_MIN(default_size, get_socket_mem_size(socket));\n\n\t\t\t/* Update sizes */\n\t\t\tmemory[socket] = default_size;\n\t\t\ttotal_size -= default_size;\n\t\t}\n\n\t\t/*\n\t\t * If some memory is remaining, try to allocate it by getting all\n\t\t * available memory from sockets, one after the other\n\t\t */\n\t\tfor (socket = 0; socket < RTE_MAX_NUMA_NODES && total_size != 0; socket++) {\n\t\t\t/* take whatever is available */\n\t\t\tdefault_size = RTE_MIN(get_socket_mem_size(socket) - memory[socket],\n\t\t\t total_size);\n\n\t\t\t/* Update sizes */\n\t\t\tmemory[socket] += default_size;\n\t\t\ttotal_size -= default_size;\n\t\t}\n\t}\n\n\tfor (socket = 0; socket < RTE_MAX_NUMA_NODES && total_mem != 0; socket++) {\n\t\t/* skips if the memory on specific socket wasn't requested */\n\t\tfor (i = 0; i < num_hp_info && memory[socket] != 0; i++){\n\t\t\thp_used[i].hugedir = hp_info[i].hugedir;\n\t\t\thp_used[i].num_pages[socket] = RTE_MIN(\n\t\t\t\t\tmemory[socket] / hp_info[i].hugepage_sz,\n\t\t\t\t\thp_info[i].num_pages[socket]);\n\n\t\t\tcur_mem = hp_used[i].num_pages[socket] *\n\t\t\t\t\thp_used[i].hugepage_sz;\n\n\t\t\tmemory[socket] -= cur_mem;\n\t\t\ttotal_mem -= cur_mem;\n\n\t\t\ttotal_num_pages += hp_used[i].num_pages[socket];\n\n\t\t\t/* check if we have met all memory requests */\n\t\t\tif (memory[socket] == 0)\n\t\t\t\tbreak;\n\n\t\t\t/* check if we have any more pages left at this size, if so\n\t\t\t * move on to next size */\n\t\t\tif (hp_used[i].num_pages[socket] == hp_info[i].num_pages[socket])\n\t\t\t\tcontinue;\n\t\t\t/* At this point we know that there are more pages available that are\n\t\t\t * bigger than the memory we want, so lets see if we can get enough\n\t\t\t * from other page sizes.\n\t\t\t */\n\t\t\tremaining_mem = 0;\n\t\t\tfor (j = i+1; j < num_hp_info; j++)\n\t\t\t\tremaining_mem += hp_info[j].hugepage_sz *\n\t\t\t\thp_info[j].num_pages[socket];\n\n\t\t\t/* is there enough other memory, if not allocate another page and quit */\n\t\t\tif (remaining_mem < memory[socket]){\n\t\t\t\tcur_mem = RTE_MIN(memory[socket],\n\t\t\t\t\t\thp_info[i].hugepage_sz);\n\t\t\t\tmemory[socket] -= cur_mem;\n\t\t\t\ttotal_mem -= cur_mem;\n\t\t\t\thp_used[i].num_pages[socket]++;\n\t\t\t\ttotal_num_pages++;\n\t\t\t\tbreak; /* we are done with this socket*/\n\t\t\t}\n\t\t}\n\t\t/* if we didn't satisfy all memory requirements per socket */\n\t\tif (memory[socket] > 0) {\n\t\t\t/* to prevent icc errors */\n\t\t\trequested = (unsigned) (internal_config.socket_mem[socket] /\n\t\t\t\t\t0x100000);\n\t\t\tavailable = requested -\n\t\t\t\t\t((unsigned) (memory[socket] / 0x100000));\n\t\t\tRTE_LOG(ERR, EAL, \"Not enough memory available on socket %u! \"\n\t\t\t\t\t\"Requested: %uMB, available: %uMB\\n\", socket,\n\t\t\t\t\trequested, available);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* if we didn't satisfy total memory requirements */\n\tif (total_mem > 0) {\n\t\trequested = (unsigned) (internal_config.memory / 0x100000);\n\t\tavailable = requested - (unsigned) (total_mem / 0x100000);\n\t\tRTE_LOG(ERR, EAL, \"Not enough memory available! Requested: %uMB,\"\n\t\t\t\t\" available: %uMB\\n\", requested, available);\n\t\treturn -1;\n\t}\n\treturn total_num_pages;\n}\n\n/*\n * Prepare physical memory mapping: fill configuration structure with\n * these infos, return 0 on success.\n * 1. map N huge pages in separate files in hugetlbfs\n * 2. find associated physical addr\n * 3. find associated NUMA socket ID\n * 4. sort all huge pages by physical address\n * 5. remap these N huge pages in the correct order\n * 6. unmap the first mapping\n * 7. fill memsegs in configuration with contiguous zones\n */\nint\nrte_eal_hugepage_init(void)\n{\n\tstruct rte_mem_config *mcfg;\n\tstruct hugepage_file *hugepage, *tmp_hp = NULL;\n\tstruct hugepage_info used_hp[MAX_HUGEPAGE_SIZES];\n\n\tuint64_t memory[RTE_MAX_NUMA_NODES];\n\n\tunsigned hp_offset;\n\tint i, j, new_memseg;\n\tint nr_hugefiles, nr_hugepages = 0;\n\tvoid *addr;\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\tint new_pages_count[MAX_HUGEPAGE_SIZES];\n#endif\n\n\ttest_proc_pagemap_readable();\n\n\tmemset(used_hp, 0, sizeof(used_hp));\n\n\t/* get pointer to global configuration */\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\t/* hugetlbfs can be disabled */\n\tif (internal_config.no_hugetlbfs) {\n\t\taddr = mmap(NULL, internal_config.memory, PROT_READ | PROT_WRITE,\n\t\t\t\tMAP_PRIVATE | MAP_ANONYMOUS, 0, 0);\n\t\tif (addr == MAP_FAILED) {\n\t\t\tRTE_LOG(ERR, EAL, \"%s: mmap() failed: %s\\n\", __func__,\n\t\t\t\t\tstrerror(errno));\n\t\t\treturn -1;\n\t\t}\n\t\tmcfg->memseg[0].phys_addr = (phys_addr_t)(uintptr_t)addr;\n\t\tmcfg->memseg[0].addr = addr;\n\t\tmcfg->memseg[0].hugepage_sz = RTE_PGSIZE_4K;\n\t\tmcfg->memseg[0].len = internal_config.memory;\n\t\tmcfg->memseg[0].socket_id = 0;\n\t\treturn 0;\n\t}\n\n/* check if app runs on Xen Dom0 */\n\tif (internal_config.xen_dom0_support) {\n#ifdef RTE_LIBRTE_XEN_DOM0\n\t\t/* use dom0_mm kernel driver to init memory */\n\t\tif (rte_xen_dom0_memory_init() < 0)\n\t\t\treturn -1;\n\t\telse\n\t\t\treturn 0;\n#endif\n\t}\n\n\t/* calculate total number of hugepages available. at this point we haven't\n\t * yet started sorting them so they all are on socket 0 */\n\tfor (i = 0; i < (int) internal_config.num_hugepage_sizes; i++) {\n\t\t/* meanwhile, also initialize used_hp hugepage sizes in used_hp */\n\t\tused_hp[i].hugepage_sz = internal_config.hugepage_info[i].hugepage_sz;\n\n\t\tnr_hugepages += internal_config.hugepage_info[i].num_pages[0];\n\t}\n\n\t/*\n\t * allocate a memory area for hugepage table.\n\t * this isn't shared memory yet. due to the fact that we need some\n\t * processing done on these pages, shared memory will be created\n\t * at a later stage.\n\t */\n\ttmp_hp = malloc(nr_hugepages * sizeof(struct hugepage_file));\n\tif (tmp_hp == NULL)\n\t\tgoto fail;\n\n\tmemset(tmp_hp, 0, nr_hugepages * sizeof(struct hugepage_file));\n\n\thp_offset = 0; /* where we start the current page size entries */\n\n\t/* map all hugepages and sort them */\n\tfor (i = 0; i < (int)internal_config.num_hugepage_sizes; i ++){\n\t\tstruct hugepage_info *hpi;\n\n\t\t/*\n\t\t * we don't yet mark hugepages as used at this stage, so\n\t\t * we just map all hugepages available to the system\n\t\t * all hugepages are still located on socket 0\n\t\t */\n\t\thpi = &internal_config.hugepage_info[i];\n\n\t\tif (hpi->num_pages[0] == 0)\n\t\t\tcontinue;\n\n\t\t/* map all hugepages available */\n\t\tif (map_all_hugepages(&tmp_hp[hp_offset], hpi, 1) < 0){\n\t\t\tRTE_LOG(DEBUG, EAL, \"Failed to mmap %u MB hugepages\\n\",\n\t\t\t\t\t(unsigned)(hpi->hugepage_sz / 0x100000));\n\t\t\tgoto fail;\n\t\t}\n\n\t\t/* find physical addresses and sockets for each hugepage */\n\t\tif (find_physaddrs(&tmp_hp[hp_offset], hpi) < 0){\n\t\t\tRTE_LOG(DEBUG, EAL, \"Failed to find phys addr for %u MB pages\\n\",\n\t\t\t\t\t(unsigned)(hpi->hugepage_sz / 0x100000));\n\t\t\tgoto fail;\n\t\t}\n\n\t\tif (find_numasocket(&tmp_hp[hp_offset], hpi) < 0){\n\t\t\tRTE_LOG(DEBUG, EAL, \"Failed to find NUMA socket for %u MB pages\\n\",\n\t\t\t\t\t(unsigned)(hpi->hugepage_sz / 0x100000));\n\t\t\tgoto fail;\n\t\t}\n\n\t\tif (sort_by_physaddr(&tmp_hp[hp_offset], hpi) < 0)\n\t\t\tgoto fail;\n\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\t\t/* remap all hugepages into single file segments */\n\t\tnew_pages_count[i] = remap_all_hugepages(&tmp_hp[hp_offset], hpi);\n\t\tif (new_pages_count[i] < 0){\n\t\t\tRTE_LOG(DEBUG, EAL, \"Failed to remap %u MB pages\\n\",\n\t\t\t\t\t(unsigned)(hpi->hugepage_sz / 0x100000));\n\t\t\tgoto fail;\n\t\t}\n\n\t\t/* we have processed a num of hugepages of this size, so inc offset */\n\t\thp_offset += new_pages_count[i];\n#else\n\t\t/* remap all hugepages */\n\t\tif (map_all_hugepages(&tmp_hp[hp_offset], hpi, 0) < 0){\n\t\t\tRTE_LOG(DEBUG, EAL, \"Failed to remap %u MB pages\\n\",\n\t\t\t\t\t(unsigned)(hpi->hugepage_sz / 0x100000));\n\t\t\tgoto fail;\n\t\t}\n\n\t\t/* unmap original mappings */\n\t\tif (unmap_all_hugepages_orig(&tmp_hp[hp_offset], hpi) < 0)\n\t\t\tgoto fail;\n\n\t\t/* we have processed a num of hugepages of this size, so inc offset */\n\t\thp_offset += hpi->num_pages[0];\n#endif\n\t}\n\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\tnr_hugefiles = 0;\n\tfor (i = 0; i < (int) internal_config.num_hugepage_sizes; i++) {\n\t\tnr_hugefiles += new_pages_count[i];\n\t}\n#else\n\tnr_hugefiles = nr_hugepages;\n#endif\n\n\n\t/* clean out the numbers of pages */\n\tfor (i = 0; i < (int) internal_config.num_hugepage_sizes; i++)\n\t\tfor (j = 0; j < RTE_MAX_NUMA_NODES; j++)\n\t\t\tinternal_config.hugepage_info[i].num_pages[j] = 0;\n\n\t/* get hugepages for each socket */\n\tfor (i = 0; i < nr_hugefiles; i++) {\n\t\tint socket = tmp_hp[i].socket_id;\n\n\t\t/* find a hugepage info with right size and increment num_pages */\n\t\tconst int nb_hpsizes = RTE_MIN(MAX_HUGEPAGE_SIZES,\n\t\t\t\t(int)internal_config.num_hugepage_sizes);\n\t\tfor (j = 0; j < nb_hpsizes; j++) {\n\t\t\tif (tmp_hp[i].size ==\n\t\t\t\t\tinternal_config.hugepage_info[j].hugepage_sz) {\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\t\t\t\t\tinternal_config.hugepage_info[j].num_pages[socket] +=\n\t\t\t\t\t\ttmp_hp[i].repeated;\n#else\n\t\t\t\tinternal_config.hugepage_info[j].num_pages[socket]++;\n#endif\n\t\t\t}\n\t\t}\n\t}\n\n\t/* make a copy of socket_mem, needed for number of pages calculation */\n\tfor (i = 0; i < RTE_MAX_NUMA_NODES; i++)\n\t\tmemory[i] = internal_config.socket_mem[i];\n\n\t/* calculate final number of pages */\n\tnr_hugepages = calc_num_pages_per_socket(memory,\n\t\t\tinternal_config.hugepage_info, used_hp,\n\t\t\tinternal_config.num_hugepage_sizes);\n\n\t/* error if not enough memory available */\n\tif (nr_hugepages < 0)\n\t\tgoto fail;\n\n\t/* reporting in! */\n\tfor (i = 0; i < (int) internal_config.num_hugepage_sizes; i++) {\n\t\tfor (j = 0; j < RTE_MAX_NUMA_NODES; j++) {\n\t\t\tif (used_hp[i].num_pages[j] > 0) {\n\t\t\t\tRTE_LOG(DEBUG, EAL,\n\t\t\t\t\t\"Requesting %u pages of size %uMB\"\n\t\t\t\t\t\" from socket %i\\n\",\n\t\t\t\t\tused_hp[i].num_pages[j],\n\t\t\t\t\t(unsigned)\n\t\t\t\t\t(used_hp[i].hugepage_sz / 0x100000),\n\t\t\t\t\tj);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* create shared memory */\n\thugepage = create_shared_memory(eal_hugepage_info_path(),\n\t\t\tnr_hugefiles * sizeof(struct hugepage_file));\n\n\tif (hugepage == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Failed to create shared memory!\\n\");\n\t\tgoto fail;\n\t}\n\tmemset(hugepage, 0, nr_hugefiles * sizeof(struct hugepage_file));\n\n\t/*\n\t * unmap pages that we won't need (looks at used_hp).\n\t * also, sets final_va to NULL on pages that were unmapped.\n\t */\n\tif (unmap_unneeded_hugepages(tmp_hp, used_hp,\n\t\t\tinternal_config.num_hugepage_sizes) < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Unmapping and locking hugepages failed!\\n\");\n\t\tgoto fail;\n\t}\n\n\t/*\n\t * copy stuff from malloc'd hugepage* to the actual shared memory.\n\t * this procedure only copies those hugepages that have final_va\n\t * not NULL. has overflow protection.\n\t */\n\tif (copy_hugepages_to_shared_mem(hugepage, nr_hugefiles,\n\t\t\ttmp_hp, nr_hugefiles) < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Copying tables to shared memory failed!\\n\");\n\t\tgoto fail;\n\t}\n\n\t/* free the temporary hugepage table */\n\tfree(tmp_hp);\n\ttmp_hp = NULL;\n\n\t/* find earliest free memseg - this is needed because in case of IVSHMEM,\n\t * segments might have already been initialized */\n\tfor (j = 0; j < RTE_MAX_MEMSEG; j++)\n\t\tif (mcfg->memseg[j].addr == NULL) {\n\t\t\t/* move to previous segment and exit loop */\n\t\t\tj--;\n\t\t\tbreak;\n\t\t}\n\n\tfor (i = 0; i < nr_hugefiles; i++) {\n\t\tnew_memseg = 0;\n\n\t\t/* if this is a new section, create a new memseg */\n\t\tif (i == 0)\n\t\t\tnew_memseg = 1;\n\t\telse if (hugepage[i].socket_id != hugepage[i-1].socket_id)\n\t\t\tnew_memseg = 1;\n\t\telse if (hugepage[i].size != hugepage[i-1].size)\n\t\t\tnew_memseg = 1;\n\n#ifdef RTE_ARCH_PPC_64\n\t\t/* On PPC64 architecture, the mmap always start from higher\n\t\t * virtual address to lower address. Here, both the physical\n\t\t * address and virtual address are in descending order */\n\t\telse if ((hugepage[i-1].physaddr - hugepage[i].physaddr) !=\n\t\t hugepage[i].size)\n\t\t\tnew_memseg = 1;\n\t\telse if (((unsigned long)hugepage[i-1].final_va -\n\t\t (unsigned long)hugepage[i].final_va) != hugepage[i].size)\n\t\t\tnew_memseg = 1;\n#else\n\t\telse if ((hugepage[i].physaddr - hugepage[i-1].physaddr) !=\n\t\t hugepage[i].size)\n\t\t\tnew_memseg = 1;\n\t\telse if (((unsigned long)hugepage[i].final_va -\n\t\t (unsigned long)hugepage[i-1].final_va) != hugepage[i].size)\n\t\t\tnew_memseg = 1;\n#endif\n\n\t\tif (new_memseg) {\n\t\t\tj += 1;\n\t\t\tif (j == RTE_MAX_MEMSEG)\n\t\t\t\tbreak;\n\n\t\t\tmcfg->memseg[j].phys_addr = hugepage[i].physaddr;\n\t\t\tmcfg->memseg[j].addr = hugepage[i].final_va;\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\t\t\tmcfg->memseg[j].len = hugepage[i].size * hugepage[i].repeated;\n#else\n\t\t\tmcfg->memseg[j].len = hugepage[i].size;\n#endif\n\t\t\tmcfg->memseg[j].socket_id = hugepage[i].socket_id;\n\t\t\tmcfg->memseg[j].hugepage_sz = hugepage[i].size;\n\t\t}\n\t\t/* continuation of previous memseg */\n\t\telse {\n#ifdef RTE_ARCH_PPC_64\n\t\t/* Use the phy and virt address of the last page as segment\n\t\t * address for IBM Power architecture */\n\t\t\tmcfg->memseg[j].phys_addr = hugepage[i].physaddr;\n\t\t\tmcfg->memseg[j].addr = hugepage[i].final_va;\n#endif\n\t\t\tmcfg->memseg[j].len += mcfg->memseg[j].hugepage_sz;\n\t\t}\n\t\thugepage[i].memseg_id = j;\n\t}\n\n\tif (i < nr_hugefiles) {\n\t\tRTE_LOG(ERR, EAL, \"Can only reserve %d pages \"\n\t\t\t\"from %d requested\\n\"\n\t\t\t\"Current %s=%d is not enough\\n\"\n\t\t\t\"Please either increase it or request less amount \"\n\t\t\t\"of memory.\\n\",\n\t\t\ti, nr_hugefiles, RTE_STR(CONFIG_RTE_MAX_MEMSEG),\n\t\t\tRTE_MAX_MEMSEG);\n\t\treturn -ENOMEM;\n\t}\n\n\treturn 0;\n\nfail:\n\tif (tmp_hp)\n\t\tfree(tmp_hp);\n\treturn -1;\n}\n\n/*\n * uses fstat to report the size of a file on disk\n */\nstatic off_t\ngetFileSize(int fd)\n{\n\tstruct stat st;\n\tif (fstat(fd, &st) < 0)\n\t\treturn 0;\n\treturn st.st_size;\n}\n\n/*\n * This creates the memory mappings in the secondary process to match that of\n * the server process. It goes through each memory segment in the DPDK runtime\n * configuration and finds the hugepages which form that segment, mapping them\n * in order to form a contiguous block in the virtual memory space\n */\nint\nrte_eal_hugepage_attach(void)\n{\n\tconst struct rte_mem_config *mcfg = rte_eal_get_configuration()->mem_config;\n\tconst struct hugepage_file *hp = NULL;\n\tunsigned num_hp = 0;\n\tunsigned i, s = 0; /* s used to track the segment number */\n\toff_t size;\n\tint fd, fd_zero = -1, fd_hugepage = -1;\n\n\tif (aslr_enabled() > 0) {\n\t\tRTE_LOG(WARNING, EAL, \"WARNING: Address Space Layout Randomization \"\n\t\t\t\t\"(ASLR) is enabled in the kernel.\\n\");\n\t\tRTE_LOG(WARNING, EAL, \" This may cause issues with mapping memory \"\n\t\t\t\t\"into secondary processes\\n\");\n\t}\n\n\ttest_proc_pagemap_readable();\n\n\tif (internal_config.xen_dom0_support) {\n#ifdef RTE_LIBRTE_XEN_DOM0\n\t\tif (rte_xen_dom0_memory_attach() < 0) {\n\t\t\tRTE_LOG(ERR, EAL,\"Failed to attach memory setments of primay \"\n\t\t\t\t\t\"process\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\treturn 0;\n#endif\n\t}\n\n\tfd_zero = open(\"/dev/zero\", O_RDONLY);\n\tif (fd_zero < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Could not open /dev/zero\\n\");\n\t\tgoto error;\n\t}\n\tfd_hugepage = open(eal_hugepage_info_path(), O_RDONLY);\n\tif (fd_hugepage < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Could not open %s\\n\", eal_hugepage_info_path());\n\t\tgoto error;\n\t}\n\n\t/* map all segments into memory to make sure we get the addrs */\n\tfor (s = 0; s < RTE_MAX_MEMSEG; ++s) {\n\t\tvoid *base_addr;\n\n\t\t/*\n\t\t * the first memory segment with len==0 is the one that\n\t\t * follows the last valid segment.\n\t\t */\n\t\tif (mcfg->memseg[s].len == 0)\n\t\t\tbreak;\n\n#ifdef RTE_LIBRTE_IVSHMEM\n\t\t/*\n\t\t * if segment has ioremap address set, it's an IVSHMEM segment and\n\t\t * doesn't need mapping as it was already mapped earlier\n\t\t */\n\t\tif (mcfg->memseg[s].ioremap_addr != 0)\n\t\t\tcontinue;\n#endif\n\n\t\t/*\n\t\t * fdzero is mmapped to get a contiguous block of virtual\n\t\t * addresses of the appropriate memseg size.\n\t\t * use mmap to get identical addresses as the primary process.\n\t\t */\n\t\tbase_addr = mmap(mcfg->memseg[s].addr, mcfg->memseg[s].len,\n\t\t\t\t PROT_READ, MAP_PRIVATE, fd_zero, 0);\n\t\tif (base_addr == MAP_FAILED ||\n\t\t base_addr != mcfg->memseg[s].addr) {\n\t\t\tRTE_LOG(ERR, EAL, \"Could not mmap %llu bytes \"\n\t\t\t\t\"in /dev/zero to requested address [%p]: '%s'\\n\",\n\t\t\t\t(unsigned long long)mcfg->memseg[s].len,\n\t\t\t\tmcfg->memseg[s].addr, strerror(errno));\n\t\t\tif (aslr_enabled() > 0) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"It is recommended to \"\n\t\t\t\t\t\"disable ASLR in the kernel \"\n\t\t\t\t\t\"and retry running both primary \"\n\t\t\t\t\t\"and secondary processes\\n\");\n\t\t\t}\n\t\t\tgoto error;\n\t\t}\n\t}\n\n\tsize = getFileSize(fd_hugepage);\n\thp = mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd_hugepage, 0);\n\tif (hp == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Could not mmap %s\\n\", eal_hugepage_info_path());\n\t\tgoto error;\n\t}\n\n\tnum_hp = size / sizeof(struct hugepage_file);\n\tRTE_LOG(DEBUG, EAL, \"Analysing %u files\\n\", num_hp);\n\n\ts = 0;\n\twhile (s < RTE_MAX_MEMSEG && mcfg->memseg[s].len > 0){\n\t\tvoid *addr, *base_addr;\n\t\tuintptr_t offset = 0;\n\t\tsize_t mapping_size;\n#ifdef RTE_LIBRTE_IVSHMEM\n\t\t/*\n\t\t * if segment has ioremap address set, it's an IVSHMEM segment and\n\t\t * doesn't need mapping as it was already mapped earlier\n\t\t */\n\t\tif (mcfg->memseg[s].ioremap_addr != 0) {\n\t\t\ts++;\n\t\t\tcontinue;\n\t\t}\n#endif\n\t\t/*\n\t\t * free previously mapped memory so we can map the\n\t\t * hugepages into the space\n\t\t */\n\t\tbase_addr = mcfg->memseg[s].addr;\n\t\tmunmap(base_addr, mcfg->memseg[s].len);\n\n\t\t/* find the hugepages for this segment and map them\n\t\t * we don't need to worry about order, as the server sorted the\n\t\t * entries before it did the second mmap of them */\n\t\tfor (i = 0; i < num_hp && offset < mcfg->memseg[s].len; i++){\n\t\t\tif (hp[i].memseg_id == (int)s){\n\t\t\t\tfd = open(hp[i].filepath, O_RDWR);\n\t\t\t\tif (fd < 0) {\n\t\t\t\t\tRTE_LOG(ERR, EAL, \"Could not open %s\\n\",\n\t\t\t\t\t\thp[i].filepath);\n\t\t\t\t\tgoto error;\n\t\t\t\t}\n#ifdef RTE_EAL_SINGLE_FILE_SEGMENTS\n\t\t\t\tmapping_size = hp[i].size * hp[i].repeated;\n#else\n\t\t\t\tmapping_size = hp[i].size;\n#endif\n\t\t\t\taddr = mmap(RTE_PTR_ADD(base_addr, offset),\n\t\t\t\t\t\tmapping_size, PROT_READ | PROT_WRITE,\n\t\t\t\t\t\tMAP_SHARED, fd, 0);\n\t\t\t\tclose(fd); /* close file both on success and on failure */\n\t\t\t\tif (addr == MAP_FAILED ||\n\t\t\t\t\t\taddr != RTE_PTR_ADD(base_addr, offset)) {\n\t\t\t\t\tRTE_LOG(ERR, EAL, \"Could not mmap %s\\n\",\n\t\t\t\t\t\thp[i].filepath);\n\t\t\t\t\tgoto error;\n\t\t\t\t}\n\t\t\t\toffset+=mapping_size;\n\t\t\t}\n\t\t}\n\t\tRTE_LOG(DEBUG, EAL, \"Mapped segment %u of size 0x%llx\\n\", s,\n\t\t\t\t(unsigned long long)mcfg->memseg[s].len);\n\t\ts++;\n\t}\n\t/* unmap the hugepage config file, since we are done using it */\n\tmunmap((void *)(uintptr_t)hp, size);\n\tclose(fd_zero);\n\tclose(fd_hugepage);\n\treturn 0;\n\nerror:\n\tif (fd_zero >= 0)\n\t\tclose(fd_zero);\n\tif (fd_hugepage >= 0)\n\t\tclose(fd_hugepage);\n\treturn -1;\n}\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_pci.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_filesystem.h\"\n#include \"eal_private.h\"\n#include \"eal_pci_init.h\"\n\n/**\n * @file\n * PCI probing under linux\n *\n * This code is used to simulate a PCI probe by parsing information in sysfs.\n * When a registered device matches a driver, it is then initialized with\n * IGB_UIO driver (or doesn't initialize, if the device wasn't bound to it).\n */\n\n/* unbind kernel driver for this device */\nint\npci_unbind_kernel_driver(struct rte_pci_device *dev)\n{\n\tint n;\n\tFILE *f;\n\tchar filename[PATH_MAX];\n\tchar buf[BUFSIZ];\n\tstruct rte_pci_addr *loc = &dev->addr;\n\n\t/* open /sys/bus/pci/devices/AAAA:BB:CC.D/driver */\n\tsnprintf(filename, sizeof(filename),\n\t SYSFS_PCI_DEVICES \"/\" PCI_PRI_FMT \"/driver/unbind\",\n\t loc->domain, loc->bus, loc->devid, loc->function);\n\n\tf = fopen(filename, \"w\");\n\tif (f == NULL) /* device was not bound */\n\t\treturn 0;\n\n\tn = snprintf(buf, sizeof(buf), PCI_PRI_FMT \"\\n\",\n\t loc->domain, loc->bus, loc->devid, loc->function);\n\tif ((n < 0) || (n >= (int)sizeof(buf))) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): snprintf failed\\n\", __func__);\n\t\tgoto error;\n\t}\n\tif (fwrite(buf, n, 1, f) == 0) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): could not write to %s\\n\", __func__,\n\t\t\t\tfilename);\n\t\tgoto error;\n\t}\n\n\tfclose(f);\n\treturn 0;\n\nerror:\n\tfclose(f);\n\treturn -1;\n}\n\nstatic int\npci_get_kernel_driver_by_path(const char *filename, char *dri_name)\n{\n\tint count;\n\tchar path[PATH_MAX];\n\tchar *name;\n\n\tif (!filename || !dri_name)\n\t\treturn -1;\n\n\tcount = readlink(filename, path, PATH_MAX);\n\tif (count >= PATH_MAX)\n\t\treturn -1;\n\n\t/* For device does not have a driver */\n\tif (count < 0)\n\t\treturn 1;\n\n\tpath[count] = '\\0';\n\n\tname = strrchr(path, '/');\n\tif (name) {\n\t\tstrncpy(dri_name, name + 1, strlen(name + 1) + 1);\n\t\treturn 0;\n\t}\n\n\treturn -1;\n}\n\n/* Map pci device */\nint\npci_map_device(struct rte_pci_device *dev)\n{\n\tint ret = -1;\n\n\t/* try mapping the NIC resources using VFIO if it exists */\n\tswitch (dev->kdrv) {\n\tcase RTE_KDRV_VFIO:\n#ifdef VFIO_PRESENT\n\t\tif (pci_vfio_is_enabled())\n\t\t\tret = pci_vfio_map_resource(dev);\n#endif\n\t\tbreak;\n\tcase RTE_KDRV_IGB_UIO:\n\tcase RTE_KDRV_UIO_GENERIC:\n\t\t/* map resources for devices that use uio */\n\t\tret = pci_uio_map_resource(dev);\n\t\tbreak;\n\tdefault:\n\t\tRTE_LOG(DEBUG, EAL,\n\t\t\t\" Not managed by a supported kernel driver, skipped\\n\");\n\t\tret = 1;\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n/* Unmap pci device */\nvoid\npci_unmap_device(struct rte_pci_device *dev)\n{\n\t/* try unmapping the NIC resources using VFIO if it exists */\n\tswitch (dev->kdrv) {\n\tcase RTE_KDRV_VFIO:\n\t\tRTE_LOG(ERR, EAL, \"Hotplug doesn't support vfio yet\\n\");\n\t\tbreak;\n\tcase RTE_KDRV_IGB_UIO:\n\tcase RTE_KDRV_UIO_GENERIC:\n\t\t/* unmap resources for devices that use uio */\n\t\tpci_uio_unmap_resource(dev);\n\t\tbreak;\n\tdefault:\n\t\tRTE_LOG(DEBUG, EAL,\n\t\t\t\" Not managed by a supported kernel driver, skipped\\n\");\n\t\tbreak;\n\t}\n}\n\nvoid *\npci_find_max_end_va(void)\n{\n\tconst struct rte_memseg *seg = rte_eal_get_physmem_layout();\n\tconst struct rte_memseg *last = seg;\n\tunsigned i = 0;\n\n\tfor (i = 0; i < RTE_MAX_MEMSEG; i++, seg++) {\n\t\tif (seg->addr == NULL)\n\t\t\tbreak;\n\n\t\tif (seg->addr > last->addr)\n\t\t\tlast = seg;\n\n\t}\n\treturn RTE_PTR_ADD(last->addr, last->len);\n}\n\n/* parse the \"resource\" sysfs file */\nstatic int\npci_parse_sysfs_resource(const char *filename, struct rte_pci_device *dev)\n{\n\tFILE *f;\n\tchar buf[BUFSIZ];\n\tunion pci_resource_info {\n\t\tstruct {\n\t\t\tchar *phys_addr;\n\t\t\tchar *end_addr;\n\t\t\tchar *flags;\n\t\t};\n\t\tchar *ptrs[PCI_RESOURCE_FMT_NVAL];\n\t} res_info;\n\tint i;\n\tuint64_t phys_addr, end_addr, flags;\n\n\tf = fopen(filename, \"r\");\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot open sysfs resource\\n\");\n\t\treturn -1;\n\t}\n\n\tfor (i = 0; imem_resource[i].phys_addr = phys_addr;\n\t\t\tdev->mem_resource[i].len = end_addr - phys_addr + 1;\n\t\t\t/* not mapped for now */\n\t\t\tdev->mem_resource[i].addr = NULL;\n\t\t}\n\t}\n\tfclose(f);\n\treturn 0;\n\nerror:\n\tfclose(f);\n\treturn -1;\n}\n\n/* Scan one pci sysfs entry, and fill the devices list from it. */\nstatic int\npci_scan_one(const char *dirname, uint16_t domain, uint8_t bus,\n\t uint8_t devid, uint8_t function)\n{\n\tchar filename[PATH_MAX];\n\tunsigned long tmp;\n\tstruct rte_pci_device *dev;\n\tchar driver[PATH_MAX];\n\tint ret;\n\n\tdev = malloc(sizeof(*dev));\n\tif (dev == NULL)\n\t\treturn -1;\n\n\tmemset(dev, 0, sizeof(*dev));\n\tdev->addr.domain = domain;\n\tdev->addr.bus = bus;\n\tdev->addr.devid = devid;\n\tdev->addr.function = function;\n\n\t/* get vendor id */\n\tsnprintf(filename, sizeof(filename), \"%s/vendor\", dirname);\n\tif (eal_parse_sysfs_value(filename, &tmp) < 0) {\n\t\tfree(dev);\n\t\treturn -1;\n\t}\n\tdev->id.vendor_id = (uint16_t)tmp;\n\n\t/* get device id */\n\tsnprintf(filename, sizeof(filename), \"%s/device\", dirname);\n\tif (eal_parse_sysfs_value(filename, &tmp) < 0) {\n\t\tfree(dev);\n\t\treturn -1;\n\t}\n\tdev->id.device_id = (uint16_t)tmp;\n\n\t/* get subsystem_vendor id */\n\tsnprintf(filename, sizeof(filename), \"%s/subsystem_vendor\",\n\t\t dirname);\n\tif (eal_parse_sysfs_value(filename, &tmp) < 0) {\n\t\tfree(dev);\n\t\treturn -1;\n\t}\n\tdev->id.subsystem_vendor_id = (uint16_t)tmp;\n\n\t/* get subsystem_device id */\n\tsnprintf(filename, sizeof(filename), \"%s/subsystem_device\",\n\t\t dirname);\n\tif (eal_parse_sysfs_value(filename, &tmp) < 0) {\n\t\tfree(dev);\n\t\treturn -1;\n\t}\n\tdev->id.subsystem_device_id = (uint16_t)tmp;\n\n\t/* get max_vfs */\n\tdev->max_vfs = 0;\n\tsnprintf(filename, sizeof(filename), \"%s/max_vfs\", dirname);\n\tif (!access(filename, F_OK) &&\n\t eal_parse_sysfs_value(filename, &tmp) == 0)\n\t\tdev->max_vfs = (uint16_t)tmp;\n\telse {\n\t\t/* for non igb_uio driver, need kernel version >= 3.8 */\n\t\tsnprintf(filename, sizeof(filename),\n\t\t\t \"%s/sriov_numvfs\", dirname);\n\t\tif (!access(filename, F_OK) &&\n\t\t eal_parse_sysfs_value(filename, &tmp) == 0)\n\t\t\tdev->max_vfs = (uint16_t)tmp;\n\t}\n\n\t/* get numa node */\n\tsnprintf(filename, sizeof(filename), \"%s/numa_node\",\n\t\t dirname);\n\tif (access(filename, R_OK) != 0) {\n\t\t/* if no NUMA support, set default to 0 */\n\t\tdev->numa_node = 0;\n\t} else {\n\t\tif (eal_parse_sysfs_value(filename, &tmp) < 0) {\n\t\t\tfree(dev);\n\t\t\treturn -1;\n\t\t}\n\t\tdev->numa_node = tmp;\n\t}\n\n\t/* parse resources */\n\tsnprintf(filename, sizeof(filename), \"%s/resource\", dirname);\n\tif (pci_parse_sysfs_resource(filename, dev) < 0) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot parse resource\\n\", __func__);\n\t\tfree(dev);\n\t\treturn -1;\n\t}\n\n\t/* parse driver */\n\tsnprintf(filename, sizeof(filename), \"%s/driver\", dirname);\n\tret = pci_get_kernel_driver_by_path(filename, driver);\n\tif (ret < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Fail to get kernel driver\\n\");\n\t\tfree(dev);\n\t\treturn -1;\n\t}\n\n\tif (!ret) {\n\t\tif (!strcmp(driver, \"vfio-pci\"))\n\t\t\tdev->kdrv = RTE_KDRV_VFIO;\n\t\telse if (!strcmp(driver, \"igb_uio\"))\n\t\t\tdev->kdrv = RTE_KDRV_IGB_UIO;\n\t\telse if (!strcmp(driver, \"uio_pci_generic\"))\n\t\t\tdev->kdrv = RTE_KDRV_UIO_GENERIC;\n\t\telse\n\t\t\tdev->kdrv = RTE_KDRV_UNKNOWN;\n\t} else\n\t\tdev->kdrv = RTE_KDRV_UNKNOWN;\n\n\t/* device is valid, add in list (sorted) */\n\tif (TAILQ_EMPTY(&pci_device_list)) {\n\t\tTAILQ_INSERT_TAIL(&pci_device_list, dev, next);\n\t} else {\n\t\tstruct rte_pci_device *dev2;\n\t\tint ret;\n\n\t\tTAILQ_FOREACH(dev2, &pci_device_list, next) {\n\t\t\tret = rte_eal_compare_pci_addr(&dev->addr, &dev2->addr);\n\t\t\tif (ret > 0)\n\t\t\t\tcontinue;\n\n\t\t\tif (ret < 0) {\n\t\t\t\tTAILQ_INSERT_BEFORE(dev2, dev, next);\n\t\t\t} else { /* already registered */\n\t\t\t\tdev2->kdrv = dev->kdrv;\n\t\t\t\tdev2->max_vfs = dev->max_vfs;\n\t\t\t\tmemmove(dev2->mem_resource, dev->mem_resource,\n\t\t\t\t\tsizeof(dev->mem_resource));\n\t\t\t\tfree(dev);\n\t\t\t}\n\t\t\treturn 0;\n\t\t}\n\t\tTAILQ_INSERT_TAIL(&pci_device_list, dev, next);\n\t}\n\n\treturn 0;\n}\n\n/*\n * split up a pci address into its constituent parts.\n */\nstatic int\nparse_pci_addr_format(const char *buf, int bufsize, uint16_t *domain,\n\t\tuint8_t *bus, uint8_t *devid, uint8_t *function)\n{\n\t/* first split on ':' */\n\tunion splitaddr {\n\t\tstruct {\n\t\t\tchar *domain;\n\t\t\tchar *bus;\n\t\t\tchar *devid;\n\t\t\tchar *function;\n\t\t};\n\t\tchar *str[PCI_FMT_NVAL]; /* last element-separator is \".\" not \":\" */\n\t} splitaddr;\n\n\tchar *buf_copy = strndup(buf, bufsize);\n\tif (buf_copy == NULL)\n\t\treturn -1;\n\n\tif (rte_strsplit(buf_copy, bufsize, splitaddr.str, PCI_FMT_NVAL, ':')\n\t\t\t!= PCI_FMT_NVAL - 1)\n\t\tgoto error;\n\t/* final split is on '.' between devid and function */\n\tsplitaddr.function = strchr(splitaddr.devid,'.');\n\tif (splitaddr.function == NULL)\n\t\tgoto error;\n\t*splitaddr.function++ = '\\0';\n\n\t/* now convert to int values */\n\terrno = 0;\n\t*domain = (uint16_t)strtoul(splitaddr.domain, NULL, 16);\n\t*bus = (uint8_t)strtoul(splitaddr.bus, NULL, 16);\n\t*devid = (uint8_t)strtoul(splitaddr.devid, NULL, 16);\n\t*function = (uint8_t)strtoul(splitaddr.function, NULL, 10);\n\tif (errno != 0)\n\t\tgoto error;\n\n\tfree(buf_copy); /* free the copy made with strdup */\n\treturn 0;\nerror:\n\tfree(buf_copy);\n\treturn -1;\n}\n\n/*\n * Scan the content of the PCI bus, and the devices in the devices\n * list\n */\nint\nrte_eal_pci_scan(void)\n{\n\tstruct dirent *e;\n\tDIR *dir;\n\tchar dirname[PATH_MAX];\n\tuint16_t domain;\n\tuint8_t bus, devid, function;\n\n\tdir = opendir(SYSFS_PCI_DEVICES);\n\tif (dir == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): opendir failed: %s\\n\",\n\t\t\t__func__, strerror(errno));\n\t\treturn -1;\n\t}\n\n\twhile ((e = readdir(dir)) != NULL) {\n\t\tif (e->d_name[0] == '.')\n\t\t\tcontinue;\n\n\t\tif (parse_pci_addr_format(e->d_name, sizeof(e->d_name), &domain,\n\t\t\t\t&bus, &devid, &function) != 0)\n\t\t\tcontinue;\n\n\t\tsnprintf(dirname, sizeof(dirname), \"%s/%s\", SYSFS_PCI_DEVICES,\n\t\t\t e->d_name);\n\t\tif (pci_scan_one(dirname, domain, bus, devid, function) < 0)\n\t\t\tgoto error;\n\t}\n\tclosedir(dir);\n\treturn 0;\n\nerror:\n\tclosedir(dir);\n\treturn -1;\n}\n\n#ifdef RTE_PCI_CONFIG\nstatic int\npci_config_extended_tag(struct rte_pci_device *dev)\n{\n\tstruct rte_pci_addr *loc = &dev->addr;\n\tchar filename[PATH_MAX];\n\tchar buf[BUFSIZ];\n\tFILE *f;\n\n\t/* not configured, let it as is */\n\tif (strncmp(RTE_PCI_EXTENDED_TAG, \"on\", 2) != 0 &&\n\t\tstrncmp(RTE_PCI_EXTENDED_TAG, \"off\", 3) != 0)\n\t\treturn 0;\n\n\tsnprintf(filename, sizeof(filename),\n\t\tSYSFS_PCI_DEVICES \"/\" PCI_PRI_FMT \"/\" \"extended_tag\",\n\t\tloc->domain, loc->bus, loc->devid, loc->function);\n\tf = fopen(filename, \"rw+\");\n\tif (!f)\n\t\treturn -1;\n\n\tfgets(buf, sizeof(buf), f);\n\tif (strncmp(RTE_PCI_EXTENDED_TAG, \"on\", 2) == 0) {\n\t\t/* enable Extended Tag*/\n\t\tif (strncmp(buf, \"on\", 2) != 0) {\n\t\t\tfseek(f, 0, SEEK_SET);\n\t\t\tfputs(\"on\", f);\n\t\t}\n\t} else {\n\t\t/* disable Extended Tag */\n\t\tif (strncmp(buf, \"off\", 3) != 0) {\n\t\t\tfseek(f, 0, SEEK_SET);\n\t\t\tfputs(\"off\", f);\n\t\t}\n\t}\n\tfclose(f);\n\n\treturn 0;\n}\n\nstatic int\npci_config_max_read_request_size(struct rte_pci_device *dev)\n{\n\tstruct rte_pci_addr *loc = &dev->addr;\n\tchar filename[PATH_MAX];\n\tchar buf[BUFSIZ], param[BUFSIZ];\n\tFILE *f;\n\t/* size can be 128, 256, 512, 1024, 2048, 4096 */\n\tuint32_t max_size = RTE_PCI_MAX_READ_REQUEST_SIZE;\n\n\t/* not configured, let it as is */\n\tif (!max_size)\n\t\treturn 0;\n\n\tsnprintf(filename, sizeof(filename),\n\t\tSYSFS_PCI_DEVICES \"/\" PCI_PRI_FMT \"/\" \"max_read_request_size\",\n\t\t\tloc->domain, loc->bus, loc->devid, loc->function);\n\tf = fopen(filename, \"rw+\");\n\tif (!f)\n\t\treturn -1;\n\n\tfgets(buf, sizeof(buf), f);\n\tsnprintf(param, sizeof(param), \"%d\", max_size);\n\n\t/* check if the size to be set is the same as current */\n\tif (strcmp(buf, param) == 0) {\n\t\tfclose(f);\n\t\treturn 0;\n\t}\n\tfseek(f, 0, SEEK_SET);\n\tfputs(param, f);\n\tfclose(f);\n\n\treturn 0;\n}\n\nvoid\npci_config_space_set(struct rte_pci_device *dev)\n{\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n\t\treturn;\n\n\t/* configure extended tag */\n\tpci_config_extended_tag(dev);\n\n\t/* configure max read request size */\n\tpci_config_max_read_request_size(dev);\n}\n#endif\n\n/* Read PCI config space. */\nint rte_eal_pci_read_config(const struct rte_pci_device *device,\n\t\t\t void *buf, size_t len, off_t offset)\n{\n\tconst struct rte_intr_handle *intr_handle = &device->intr_handle;\n\n\tswitch (intr_handle->type) {\n\tcase RTE_INTR_HANDLE_UIO:\n\tcase RTE_INTR_HANDLE_UIO_INTX:\n\t\treturn pci_uio_read_config(intr_handle, buf, len, offset);\n\n#ifdef VFIO_PRESENT\n\tcase RTE_INTR_HANDLE_VFIO_MSIX:\n\tcase RTE_INTR_HANDLE_VFIO_MSI:\n\tcase RTE_INTR_HANDLE_VFIO_LEGACY:\n\t\treturn pci_vfio_read_config(intr_handle, buf, len, offset);\n#endif\n\tdefault:\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Unknown handle type of fd %d\\n\",\n\t\t\t\t\tintr_handle->fd);\n\t\treturn -1;\n\t}\n}\n\n/* Write PCI config space. */\nint rte_eal_pci_write_config(const struct rte_pci_device *device,\n\t\t\t const void *buf, size_t len, off_t offset)\n{\n\tconst struct rte_intr_handle *intr_handle = &device->intr_handle;\n\n\tswitch (intr_handle->type) {\n\tcase RTE_INTR_HANDLE_UIO:\n\tcase RTE_INTR_HANDLE_UIO_INTX:\n\t\treturn pci_uio_write_config(intr_handle, buf, len, offset);\n\n#ifdef VFIO_PRESENT\n\tcase RTE_INTR_HANDLE_VFIO_MSIX:\n\tcase RTE_INTR_HANDLE_VFIO_MSI:\n\tcase RTE_INTR_HANDLE_VFIO_LEGACY:\n\t\treturn pci_vfio_write_config(intr_handle, buf, len, offset);\n#endif\n\tdefault:\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Unknown handle type of fd %d\\n\",\n\t\t\t\t\tintr_handle->fd);\n\t\treturn -1;\n\t}\n}\n\n/* Init the PCI EAL subsystem */\nint\nrte_eal_pci_init(void)\n{\n\tTAILQ_INIT(&pci_driver_list);\n\tTAILQ_INIT(&pci_device_list);\n\n\t/* for debug purposes, PCI can be disabled */\n\tif (internal_config.no_pci)\n\t\treturn 0;\n\n\tif (rte_eal_pci_scan() < 0) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): Cannot scan PCI bus\\n\", __func__);\n\t\treturn -1;\n\t}\n#ifdef VFIO_PRESENT\n\tpci_vfio_enable();\n\n\tif (pci_vfio_is_enabled()) {\n\n\t\t/* if we are primary process, create a thread to communicate with\n\t\t * secondary processes. the thread will use a socket to wait for\n\t\t * requests from secondary process to send open file descriptors,\n\t\t * because VFIO does not allow multiple open descriptors on a group or\n\t\t * VFIO container.\n\t\t */\n\t\tif (internal_config.process_type == RTE_PROC_PRIMARY &&\n\t\t\t\tpci_vfio_mp_sync_setup() < 0)\n\t\t\treturn -1;\n\t}\n#endif\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_pci_init.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef EAL_PCI_INIT_H_\n#define EAL_PCI_INIT_H_\n\n#include \"eal_vfio.h\"\n\n/*\n * Helper function to map PCI resources right after hugepages in virtual memory\n */\nextern void *pci_map_addr;\nvoid *pci_find_max_end_va(void);\n\nint pci_uio_alloc_resource(struct rte_pci_device *dev,\n\t\tstruct mapped_pci_resource **uio_res);\nvoid pci_uio_free_resource(struct rte_pci_device *dev,\n\t\tstruct mapped_pci_resource *uio_res);\nint pci_uio_map_resource_by_index(struct rte_pci_device *dev, int res_idx,\n\t\tstruct mapped_pci_resource *uio_res, int map_idx);\n\nint pci_uio_read_config(const struct rte_intr_handle *intr_handle,\n\t\t\tvoid *buf, size_t len, off_t offs);\nint pci_uio_write_config(const struct rte_intr_handle *intr_handle,\n\t\t\t const void *buf, size_t len, off_t offs);\n\n#ifdef VFIO_PRESENT\n\n#define VFIO_MAX_GROUPS 64\n\nint pci_vfio_enable(void);\nint pci_vfio_is_enabled(void);\nint pci_vfio_mp_sync_setup(void);\n\n/* access config space */\nint pci_vfio_read_config(const struct rte_intr_handle *intr_handle,\n\t\t\t void *buf, size_t len, off_t offs);\nint pci_vfio_write_config(const struct rte_intr_handle *intr_handle,\n\t\t\t const void *buf, size_t len, off_t offs);\n\n/* map VFIO resource prototype */\nint pci_vfio_map_resource(struct rte_pci_device *dev);\nint pci_vfio_get_group_fd(int iommu_group_fd);\nint pci_vfio_get_container_fd(void);\n\n/*\n * Function prototypes for VFIO multiprocess sync functions\n */\nint vfio_mp_sync_send_request(int socket, int req);\nint vfio_mp_sync_receive_request(int socket);\nint vfio_mp_sync_send_fd(int socket, int fd);\nint vfio_mp_sync_receive_fd(int socket);\nint vfio_mp_sync_connect_to_primary(void);\n\n/* socket comm protocol definitions */\n#define SOCKET_REQ_CONTAINER 0x100\n#define SOCKET_REQ_GROUP 0x200\n#define SOCKET_OK 0x0\n#define SOCKET_NO_FD 0x1\n#define SOCKET_ERR 0xFF\n\n/*\n * we don't need to store device fd's anywhere since they can be obtained from\n * the group fd via an ioctl() call.\n */\nstruct vfio_group {\n\tint group_no;\n\tint fd;\n};\n\nstruct vfio_config {\n\tint vfio_enabled;\n\tint vfio_container_fd;\n\tint vfio_container_has_dma;\n\tint vfio_group_idx;\n\tstruct vfio_group vfio_groups[VFIO_MAX_GROUPS];\n};\n\n#endif\n\n#endif /* EAL_PCI_INIT_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_pci_uio.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_filesystem.h\"\n#include \"eal_pci_init.h\"\n\nvoid *pci_map_addr = NULL;\n\n#define OFF_MAX ((uint64_t)(off_t)-1)\n\nint\npci_uio_read_config(const struct rte_intr_handle *intr_handle,\n\t\t void *buf, size_t len, off_t offset)\n{\n\treturn pread(intr_handle->uio_cfg_fd, buf, len, offset);\n}\n\nint\npci_uio_write_config(const struct rte_intr_handle *intr_handle,\n\t\t const void *buf, size_t len, off_t offset)\n{\n\treturn pwrite(intr_handle->uio_cfg_fd, buf, len, offset);\n}\n\nstatic int\npci_uio_set_bus_master(int dev_fd)\n{\n\tuint16_t reg;\n\tint ret;\n\n\tret = pread(dev_fd, ®, sizeof(reg), PCI_COMMAND);\n\tif (ret != sizeof(reg)) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Cannot read command from PCI config space!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* return if bus mastering is already on */\n\tif (reg & PCI_COMMAND_MASTER)\n\t\treturn 0;\n\n\treg |= PCI_COMMAND_MASTER;\n\n\tret = pwrite(dev_fd, ®, sizeof(reg), PCI_COMMAND);\n\tif (ret != sizeof(reg)) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"Cannot write command to PCI config space!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\npci_mknod_uio_dev(const char *sysfs_uio_path, unsigned uio_num)\n{\n\tFILE *f;\n\tchar filename[PATH_MAX];\n\tint ret;\n\tunsigned major, minor;\n\tdev_t dev;\n\n\t/* get the name of the sysfs file that contains the major and minor\n\t * of the uio device and read its content */\n\tsnprintf(filename, sizeof(filename), \"%s/dev\", sysfs_uio_path);\n\n\tf = fopen(filename, \"r\");\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot open sysfs to get major:minor\\n\",\n\t\t\t__func__);\n\t\treturn -1;\n\t}\n\n\tret = fscanf(f, \"%u:%u\", &major, &minor);\n\tif (ret != 2) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): cannot parse sysfs to get major:minor\\n\",\n\t\t\t__func__);\n\t\tfclose(f);\n\t\treturn -1;\n\t}\n\tfclose(f);\n\n\t/* create the char device \"mknod /dev/uioX c major minor\" */\n\tsnprintf(filename, sizeof(filename), \"/dev/uio%u\", uio_num);\n\tdev = makedev(major, minor);\n\tret = mknod(filename, S_IFCHR | S_IRUSR | S_IWUSR, dev);\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"%s(): mknod() failed %s\\n\",\n\t\t\t__func__, strerror(errno));\n\t\treturn -1;\n\t}\n\n\treturn ret;\n}\n\n/*\n * Return the uioX char device used for a pci device. On success, return\n * the UIO number and fill dstbuf string with the path of the device in\n * sysfs. On error, return a negative value. In this case dstbuf is\n * invalid.\n */\nstatic int\npci_get_uio_dev(struct rte_pci_device *dev, char *dstbuf,\n\t\t\t unsigned int buflen)\n{\n\tstruct rte_pci_addr *loc = &dev->addr;\n\tunsigned int uio_num;\n\tstruct dirent *e;\n\tDIR *dir;\n\tchar dirname[PATH_MAX];\n\n\t/* depending on kernel version, uio can be located in uio/uioX\n\t * or uio:uioX */\n\n\tsnprintf(dirname, sizeof(dirname),\n\t\t\tSYSFS_PCI_DEVICES \"/\" PCI_PRI_FMT \"/uio\",\n\t\t\tloc->domain, loc->bus, loc->devid, loc->function);\n\n\tdir = opendir(dirname);\n\tif (dir == NULL) {\n\t\t/* retry with the parent directory */\n\t\tsnprintf(dirname, sizeof(dirname),\n\t\t\t\tSYSFS_PCI_DEVICES \"/\" PCI_PRI_FMT,\n\t\t\t\tloc->domain, loc->bus, loc->devid, loc->function);\n\t\tdir = opendir(dirname);\n\n\t\tif (dir == NULL) {\n\t\t\tRTE_LOG(ERR, EAL, \"Cannot opendir %s\\n\", dirname);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* take the first file starting with \"uio\" */\n\twhile ((e = readdir(dir)) != NULL) {\n\t\t/* format could be uio%d ...*/\n\t\tint shortprefix_len = sizeof(\"uio\") - 1;\n\t\t/* ... or uio:uio%d */\n\t\tint longprefix_len = sizeof(\"uio:uio\") - 1;\n\t\tchar *endptr;\n\n\t\tif (strncmp(e->d_name, \"uio\", 3) != 0)\n\t\t\tcontinue;\n\n\t\t/* first try uio%d */\n\t\terrno = 0;\n\t\tuio_num = strtoull(e->d_name + shortprefix_len, &endptr, 10);\n\t\tif (errno == 0 && endptr != (e->d_name + shortprefix_len)) {\n\t\t\tsnprintf(dstbuf, buflen, \"%s/uio%u\", dirname, uio_num);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* then try uio:uio%d */\n\t\terrno = 0;\n\t\tuio_num = strtoull(e->d_name + longprefix_len, &endptr, 10);\n\t\tif (errno == 0 && endptr != (e->d_name + longprefix_len)) {\n\t\t\tsnprintf(dstbuf, buflen, \"%s/uio:uio%u\", dirname, uio_num);\n\t\t\tbreak;\n\t\t}\n\t}\n\tclosedir(dir);\n\n\t/* No uio resource found */\n\tif (e == NULL)\n\t\treturn -1;\n\n\t/* create uio device if we've been asked to */\n\tif (internal_config.create_uio_dev &&\n\t\t\tpci_mknod_uio_dev(dstbuf, uio_num) < 0)\n\t\tRTE_LOG(WARNING, EAL, \"Cannot create /dev/uio%u\\n\", uio_num);\n\n\treturn uio_num;\n}\n\nvoid\npci_uio_free_resource(struct rte_pci_device *dev,\n\t\tstruct mapped_pci_resource *uio_res)\n{\n\trte_free(uio_res);\n\n\tif (dev->intr_handle.uio_cfg_fd >= 0) {\n\t\tclose(dev->intr_handle.uio_cfg_fd);\n\t\tdev->intr_handle.uio_cfg_fd = -1;\n\t}\n\tif (dev->intr_handle.fd) {\n\t\tclose(dev->intr_handle.fd);\n\t\tdev->intr_handle.fd = -1;\n\t\tdev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;\n\t}\n}\n\nint\npci_uio_alloc_resource(struct rte_pci_device *dev,\n\t\tstruct mapped_pci_resource **uio_res)\n{\n\tchar dirname[PATH_MAX];\n\tchar cfgname[PATH_MAX];\n\tchar devname[PATH_MAX]; /* contains the /dev/uioX */\n\tint uio_num;\n\tstruct rte_pci_addr *loc;\n\n\tloc = &dev->addr;\n\n\t/* find uio resource */\n\tuio_num = pci_get_uio_dev(dev, dirname, sizeof(dirname));\n\tif (uio_num < 0) {\n\t\tRTE_LOG(WARNING, EAL, \" \"PCI_PRI_FMT\" not managed by UIO driver, \"\n\t\t\t\t\"skipping\\n\", loc->domain, loc->bus, loc->devid, loc->function);\n\t\treturn 1;\n\t}\n\tsnprintf(devname, sizeof(devname), \"/dev/uio%u\", uio_num);\n\n\t/* save fd if in primary process */\n\tdev->intr_handle.fd = open(devname, O_RDWR);\n\tif (dev->intr_handle.fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot open %s: %s\\n\",\n\t\t\tdevname, strerror(errno));\n\t\tgoto error;\n\t}\n\n\tsnprintf(cfgname, sizeof(cfgname),\n\t\t\t\"/sys/class/uio/uio%u/device/config\", uio_num);\n\tdev->intr_handle.uio_cfg_fd = open(cfgname, O_RDWR);\n\tif (dev->intr_handle.uio_cfg_fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot open %s: %s\\n\",\n\t\t\tcfgname, strerror(errno));\n\t\tgoto error;\n\t}\n\n\tif (dev->kdrv == RTE_KDRV_IGB_UIO)\n\t\tdev->intr_handle.type = RTE_INTR_HANDLE_UIO;\n\telse {\n\t\tdev->intr_handle.type = RTE_INTR_HANDLE_UIO_INTX;\n\n\t\t/* set bus master that is not done by uio_pci_generic */\n\t\tif (pci_uio_set_bus_master(dev->intr_handle.uio_cfg_fd)) {\n\t\t\tRTE_LOG(ERR, EAL, \"Cannot set up bus mastering!\\n\");\n\t\t\tgoto error;\n\t\t}\n\t}\n\n\t/* allocate the mapping details for secondary processes*/\n\t*uio_res = rte_zmalloc(\"UIO_RES\", sizeof(**uio_res), 0);\n\tif (*uio_res == NULL) {\n\t\tRTE_LOG(ERR, EAL,\n\t\t\t\"%s(): cannot store uio mmap details\\n\", __func__);\n\t\tgoto error;\n\t}\n\n\tsnprintf((*uio_res)->path, sizeof((*uio_res)->path), \"%s\", devname);\n\tmemcpy(&(*uio_res)->pci_addr, &dev->addr, sizeof((*uio_res)->pci_addr));\n\n\treturn 0;\n\nerror:\n\tpci_uio_free_resource(dev, *uio_res);\n\treturn -1;\n}\n\nint\npci_uio_map_resource_by_index(struct rte_pci_device *dev, int res_idx,\n\t\tstruct mapped_pci_resource *uio_res, int map_idx)\n{\n\tint fd;\n\tchar devname[PATH_MAX]; /* contains the /dev/uioX */\n\tvoid *mapaddr;\n\tstruct rte_pci_addr *loc;\n\tstruct pci_map *maps;\n\n\tloc = &dev->addr;\n\tmaps = uio_res->maps;\n\n\t/* update devname for mmap */\n\tsnprintf(devname, sizeof(devname),\n\t\t\tSYSFS_PCI_DEVICES \"/\" PCI_PRI_FMT \"/resource%d\",\n\t\t\tloc->domain, loc->bus, loc->devid,\n\t\t\tloc->function, res_idx);\n\n\t/* allocate memory to keep path */\n\tmaps[map_idx].path = rte_malloc(NULL, strlen(devname) + 1, 0);\n\tif (maps[map_idx].path == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot allocate memory for path: %s\\n\",\n\t\t\t\tstrerror(errno));\n\t\treturn -1;\n\t}\n\n\t/*\n\t * open resource file, to mmap it\n\t */\n\tfd = open(devname, O_RDWR);\n\tif (fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot open %s: %s\\n\",\n\t\t\t\tdevname, strerror(errno));\n\t\tgoto error;\n\t}\n\n\t/* try mapping somewhere close to the end of hugepages */\n\tif (pci_map_addr == NULL)\n\t\tpci_map_addr = pci_find_max_end_va();\n\n\tmapaddr = pci_map_resource(pci_map_addr, fd, 0,\n\t\t\t(size_t)dev->mem_resource[res_idx].len, 0);\n\tclose(fd);\n\tif (mapaddr == MAP_FAILED)\n\t\tgoto error;\n\n\tpci_map_addr = RTE_PTR_ADD(mapaddr,\n\t\t\t(size_t)dev->mem_resource[res_idx].len);\n\n\tmaps[map_idx].phaddr = dev->mem_resource[res_idx].phys_addr;\n\tmaps[map_idx].size = dev->mem_resource[res_idx].len;\n\tmaps[map_idx].addr = mapaddr;\n\tmaps[map_idx].offset = 0;\n\tstrcpy(maps[map_idx].path, devname);\n\tdev->mem_resource[res_idx].addr = mapaddr;\n\n\treturn 0;\n\nerror:\n\trte_free(maps[map_idx].path);\n\treturn -1;\n}\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_pci_vfio.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_filesystem.h\"\n#include \"eal_pci_init.h\"\n#include \"eal_vfio.h\"\n\n/**\n * @file\n * PCI probing under linux (VFIO version)\n *\n * This code tries to determine if the PCI device is bound to VFIO driver,\n * and initialize it (map BARs, set up interrupts) if that's the case.\n *\n * This file is only compiled if CONFIG_RTE_EAL_VFIO is set to \"y\".\n */\n\n#ifdef VFIO_PRESENT\n\n#define PAGE_SIZE (sysconf(_SC_PAGESIZE))\n#define PAGE_MASK (~(PAGE_SIZE - 1))\n\nstatic struct rte_tailq_elem rte_vfio_tailq = {\n\t.name = \"VFIO_RESOURCE_LIST\",\n};\nEAL_REGISTER_TAILQ(rte_vfio_tailq)\n\n#define VFIO_DIR \"/dev/vfio\"\n#define VFIO_CONTAINER_PATH \"/dev/vfio/vfio\"\n#define VFIO_GROUP_FMT \"/dev/vfio/%u\"\n#define VFIO_GET_REGION_ADDR(x) ((uint64_t) x << 40ULL)\n\n/* per-process VFIO config */\nstatic struct vfio_config vfio_cfg;\n\nint\npci_vfio_read_config(const struct rte_intr_handle *intr_handle,\n\t\t void *buf, size_t len, off_t offs)\n{\n\treturn pread64(intr_handle->vfio_dev_fd, buf, len,\n\t VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);\n}\n\nint\npci_vfio_write_config(const struct rte_intr_handle *intr_handle,\n\t\t const void *buf, size_t len, off_t offs)\n{\n\treturn pwrite64(intr_handle->vfio_dev_fd, buf, len,\n\t VFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) + offs);\n}\n\n/* get PCI BAR number where MSI-X interrupts are */\nstatic int\npci_vfio_get_msix_bar(int fd, int *msix_bar, uint32_t *msix_table_offset,\n\t\t uint32_t *msix_table_size)\n{\n\tint ret;\n\tuint32_t reg;\n\tuint16_t flags;\n\tuint8_t cap_id, cap_offset;\n\n\t/* read PCI capability pointer from config space */\n\tret = pread64(fd, ®, sizeof(reg),\n\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n\t\t\tPCI_CAPABILITY_LIST);\n\tif (ret != sizeof(reg)) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot read capability pointer from PCI \"\n\t\t\t\t\"config space!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* we need first byte */\n\tcap_offset = reg & 0xFF;\n\n\twhile (cap_offset) {\n\n\t\t/* read PCI capability ID */\n\t\tret = pread64(fd, ®, sizeof(reg),\n\t\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n\t\t\t\tcap_offset);\n\t\tif (ret != sizeof(reg)) {\n\t\t\tRTE_LOG(ERR, EAL, \"Cannot read capability ID from PCI \"\n\t\t\t\t\t\"config space!\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* we need first byte */\n\t\tcap_id = reg & 0xFF;\n\n\t\t/* if we haven't reached MSI-X, check next capability */\n\t\tif (cap_id != PCI_CAP_ID_MSIX) {\n\t\t\tret = pread64(fd, ®, sizeof(reg),\n\t\t\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n\t\t\t\t\tcap_offset);\n\t\t\tif (ret != sizeof(reg)) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Cannot read capability pointer from PCI \"\n\t\t\t\t\t\t\"config space!\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\t/* we need second byte */\n\t\t\tcap_offset = (reg & 0xFF00) >> 8;\n\n\t\t\tcontinue;\n\t\t}\n\t\t/* else, read table offset */\n\t\telse {\n\t\t\t/* table offset resides in the next 4 bytes */\n\t\t\tret = pread64(fd, ®, sizeof(reg),\n\t\t\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n\t\t\t\t\tcap_offset + 4);\n\t\t\tif (ret != sizeof(reg)) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Cannot read table offset from PCI config \"\n\t\t\t\t\t\t\"space!\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tret = pread64(fd, &flags, sizeof(flags),\n\t\t\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n\t\t\t\t\tcap_offset + 2);\n\t\t\tif (ret != sizeof(flags)) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Cannot read table flags from PCI config \"\n\t\t\t\t\t\t\"space!\\n\");\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\t*msix_bar = reg & RTE_PCI_MSIX_TABLE_BIR;\n\t\t\t*msix_table_offset = reg & RTE_PCI_MSIX_TABLE_OFFSET;\n\t\t\t*msix_table_size = 16 * (1 + (flags & RTE_PCI_MSIX_FLAGS_QSIZE));\n\n\t\t\treturn 0;\n\t\t}\n\t}\n\treturn 0;\n}\n\n/* set PCI bus mastering */\nstatic int\npci_vfio_set_bus_master(int dev_fd)\n{\n\tuint16_t reg;\n\tint ret;\n\n\tret = pread64(dev_fd, ®, sizeof(reg),\n\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n\t\t\tPCI_COMMAND);\n\tif (ret != sizeof(reg)) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot read command from PCI config space!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* set the master bit */\n\treg |= PCI_COMMAND_MASTER;\n\n\tret = pwrite64(dev_fd, ®, sizeof(reg),\n\t\t\tVFIO_GET_REGION_ADDR(VFIO_PCI_CONFIG_REGION_INDEX) +\n\t\t\tPCI_COMMAND);\n\n\tif (ret != sizeof(reg)) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot write command to PCI config space!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/* set up DMA mappings */\nstatic int\npci_vfio_setup_dma_maps(int vfio_container_fd)\n{\n\tconst struct rte_memseg *ms = rte_eal_get_physmem_layout();\n\tint i, ret;\n\n\tret = ioctl(vfio_container_fd, VFIO_SET_IOMMU,\n\t\t\tVFIO_TYPE1_IOMMU);\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL, \" cannot set IOMMU type, \"\n\t\t\t\t\"error %i (%s)\\n\", errno, strerror(errno));\n\t\treturn -1;\n\t}\n\n\t/* map all DPDK segments for DMA. use 1:1 PA to IOVA mapping */\n\tfor (i = 0; i < RTE_MAX_MEMSEG; i++) {\n\t\tstruct vfio_iommu_type1_dma_map dma_map;\n\n\t\tif (ms[i].addr == NULL)\n\t\t\tbreak;\n\n\t\tmemset(&dma_map, 0, sizeof(dma_map));\n\t\tdma_map.argsz = sizeof(struct vfio_iommu_type1_dma_map);\n\t\tdma_map.vaddr = ms[i].addr_64;\n\t\tdma_map.size = ms[i].len;\n\t\tdma_map.iova = ms[i].phys_addr;\n\t\tdma_map.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE;\n\n\t\tret = ioctl(vfio_container_fd, VFIO_IOMMU_MAP_DMA, &dma_map);\n\n\t\tif (ret) {\n\t\t\tRTE_LOG(ERR, EAL, \" cannot set up DMA remapping, \"\n\t\t\t\t\t\"error %i (%s)\\n\", errno, strerror(errno));\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/* set up interrupt support (but not enable interrupts) */\nstatic int\npci_vfio_setup_interrupts(struct rte_pci_device *dev, int vfio_dev_fd)\n{\n\tint i, ret, intr_idx;\n\n\t/* default to invalid index */\n\tintr_idx = VFIO_PCI_NUM_IRQS;\n\n\t/* get interrupt type from internal config (MSI-X by default, can be\n\t * overriden from the command line\n\t */\n\tswitch (internal_config.vfio_intr_mode) {\n\tcase RTE_INTR_MODE_MSIX:\n\t\tintr_idx = VFIO_PCI_MSIX_IRQ_INDEX;\n\t\tbreak;\n\tcase RTE_INTR_MODE_MSI:\n\t\tintr_idx = VFIO_PCI_MSI_IRQ_INDEX;\n\t\tbreak;\n\tcase RTE_INTR_MODE_LEGACY:\n\t\tintr_idx = VFIO_PCI_INTX_IRQ_INDEX;\n\t\tbreak;\n\t/* don't do anything if we want to automatically determine interrupt type */\n\tcase RTE_INTR_MODE_NONE:\n\t\tbreak;\n\tdefault:\n\t\tRTE_LOG(ERR, EAL, \" unknown default interrupt type!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* start from MSI-X interrupt type */\n\tfor (i = VFIO_PCI_MSIX_IRQ_INDEX; i >= 0; i--) {\n\t\tstruct vfio_irq_info irq = { .argsz = sizeof(irq) };\n\t\tint fd = -1;\n\n\t\t/* skip interrupt modes we don't want */\n\t\tif (internal_config.vfio_intr_mode != RTE_INTR_MODE_NONE &&\n\t\t\t\ti != intr_idx)\n\t\t\tcontinue;\n\n\t\tirq.index = i;\n\n\t\tret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);\n\t\tif (ret < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \" cannot get IRQ info, \"\n\t\t\t\t\t\"error %i (%s)\\n\", errno, strerror(errno));\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* if this vector cannot be used with eventfd, fail if we explicitly\n\t\t * specified interrupt type, otherwise continue */\n\t\tif ((irq.flags & VFIO_IRQ_INFO_EVENTFD) == 0) {\n\t\t\tif (internal_config.vfio_intr_mode != RTE_INTR_MODE_NONE) {\n\t\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\t\t\" interrupt vector does not support eventfd!\\n\");\n\t\t\t\treturn -1;\n\t\t\t} else\n\t\t\t\tcontinue;\n\t\t}\n\n\t\t/* set up an eventfd for interrupts */\n\t\tfd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);\n\t\tif (fd < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \" cannot set up eventfd, \"\n\t\t\t\t\t\"error %i (%s)\\n\", errno, strerror(errno));\n\t\t\treturn -1;\n\t\t}\n\n\t\tdev->intr_handle.fd = fd;\n\t\tdev->intr_handle.vfio_dev_fd = vfio_dev_fd;\n\n\t\tswitch (i) {\n\t\tcase VFIO_PCI_MSIX_IRQ_INDEX:\n\t\t\tinternal_config.vfio_intr_mode = RTE_INTR_MODE_MSIX;\n\t\t\tdev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;\n\t\t\tbreak;\n\t\tcase VFIO_PCI_MSI_IRQ_INDEX:\n\t\t\tinternal_config.vfio_intr_mode = RTE_INTR_MODE_MSI;\n\t\t\tdev->intr_handle.type = RTE_INTR_HANDLE_VFIO_MSI;\n\t\t\tbreak;\n\t\tcase VFIO_PCI_INTX_IRQ_INDEX:\n\t\t\tinternal_config.vfio_intr_mode = RTE_INTR_MODE_LEGACY;\n\t\t\tdev->intr_handle.type = RTE_INTR_HANDLE_VFIO_LEGACY;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tRTE_LOG(ERR, EAL, \" unknown interrupt type!\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\treturn 0;\n\t}\n\n\t/* if we're here, we haven't found a suitable interrupt vector */\n\treturn -1;\n}\n\n/* open container fd or get an existing one */\nint\npci_vfio_get_container_fd(void)\n{\n\tint ret, vfio_container_fd;\n\n\t/* if we're in a primary process, try to open the container */\n\tif (internal_config.process_type == RTE_PROC_PRIMARY) {\n\t\tvfio_container_fd = open(VFIO_CONTAINER_PATH, O_RDWR);\n\t\tif (vfio_container_fd < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \" cannot open VFIO container, \"\n\t\t\t\t\t\"error %i (%s)\\n\", errno, strerror(errno));\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* check VFIO API version */\n\t\tret = ioctl(vfio_container_fd, VFIO_GET_API_VERSION);\n\t\tif (ret != VFIO_API_VERSION) {\n\t\t\tif (ret < 0)\n\t\t\t\tRTE_LOG(ERR, EAL, \" could not get VFIO API version, \"\n\t\t\t\t\t\t\"error %i (%s)\\n\", errno, strerror(errno));\n\t\t\telse\n\t\t\t\tRTE_LOG(ERR, EAL, \" unsupported VFIO API version!\\n\");\n\t\t\tclose(vfio_container_fd);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* check if we support IOMMU type 1 */\n\t\tret = ioctl(vfio_container_fd, VFIO_CHECK_EXTENSION, VFIO_TYPE1_IOMMU);\n\t\tif (ret != 1) {\n\t\t\tif (ret < 0)\n\t\t\t\tRTE_LOG(ERR, EAL, \" could not get IOMMU type, \"\n\t\t\t\t\t\"error %i (%s)\\n\", errno,\n\t\t\t\t\tstrerror(errno));\n\t\t\telse\n\t\t\t\tRTE_LOG(ERR, EAL, \" unsupported IOMMU type \"\n\t\t\t\t\t\"detected in VFIO\\n\");\n\t\t\tclose(vfio_container_fd);\n\t\t\treturn -1;\n\t\t}\n\n\t\treturn vfio_container_fd;\n\t} else {\n\t\t/*\n\t\t * if we're in a secondary process, request container fd from the\n\t\t * primary process via our socket\n\t\t */\n\t\tint socket_fd;\n\n\t\tsocket_fd = vfio_mp_sync_connect_to_primary();\n\t\tif (socket_fd < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \" cannot connect to primary process!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tif (vfio_mp_sync_send_request(socket_fd, SOCKET_REQ_CONTAINER) < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \" cannot request container fd!\\n\");\n\t\t\tclose(socket_fd);\n\t\t\treturn -1;\n\t\t}\n\t\tvfio_container_fd = vfio_mp_sync_receive_fd(socket_fd);\n\t\tif (vfio_container_fd < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \" cannot get container fd!\\n\");\n\t\t\tclose(socket_fd);\n\t\t\treturn -1;\n\t\t}\n\t\tclose(socket_fd);\n\t\treturn vfio_container_fd;\n\t}\n\n\treturn -1;\n}\n\n/* open group fd or get an existing one */\nint\npci_vfio_get_group_fd(int iommu_group_no)\n{\n\tint i;\n\tint vfio_group_fd;\n\tchar filename[PATH_MAX];\n\n\t/* check if we already have the group descriptor open */\n\tfor (i = 0; i < vfio_cfg.vfio_group_idx; i++)\n\t\tif (vfio_cfg.vfio_groups[i].group_no == iommu_group_no)\n\t\t\treturn vfio_cfg.vfio_groups[i].fd;\n\n\t/* if primary, try to open the group */\n\tif (internal_config.process_type == RTE_PROC_PRIMARY) {\n\t\tsnprintf(filename, sizeof(filename),\n\t\t\t\t VFIO_GROUP_FMT, iommu_group_no);\n\t\tvfio_group_fd = open(filename, O_RDWR);\n\t\tif (vfio_group_fd < 0) {\n\t\t\t/* if file not found, it's not an error */\n\t\t\tif (errno != ENOENT) {\n\t\t\t\tRTE_LOG(ERR, EAL, \"Cannot open %s: %s\\n\", filename,\n\t\t\t\t\t\tstrerror(errno));\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\treturn 0;\n\t\t}\n\n\t\t/* if the fd is valid, create a new group for it */\n\t\tif (vfio_cfg.vfio_group_idx == VFIO_MAX_GROUPS) {\n\t\t\tRTE_LOG(ERR, EAL, \"Maximum number of VFIO groups reached!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tvfio_cfg.vfio_groups[vfio_cfg.vfio_group_idx].group_no = iommu_group_no;\n\t\tvfio_cfg.vfio_groups[vfio_cfg.vfio_group_idx].fd = vfio_group_fd;\n\t\treturn vfio_group_fd;\n\t}\n\t/* if we're in a secondary process, request group fd from the primary\n\t * process via our socket\n\t */\n\telse {\n\t\tint socket_fd, ret;\n\n\t\tsocket_fd = vfio_mp_sync_connect_to_primary();\n\n\t\tif (socket_fd < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \" cannot connect to primary process!\\n\");\n\t\t\treturn -1;\n\t\t}\n\t\tif (vfio_mp_sync_send_request(socket_fd, SOCKET_REQ_GROUP) < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \" cannot request container fd!\\n\");\n\t\t\tclose(socket_fd);\n\t\t\treturn -1;\n\t\t}\n\t\tif (vfio_mp_sync_send_request(socket_fd, iommu_group_no) < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \" cannot send group number!\\n\");\n\t\t\tclose(socket_fd);\n\t\t\treturn -1;\n\t\t}\n\t\tret = vfio_mp_sync_receive_request(socket_fd);\n\t\tswitch (ret) {\n\t\tcase SOCKET_NO_FD:\n\t\t\tclose(socket_fd);\n\t\t\treturn 0;\n\t\tcase SOCKET_OK:\n\t\t\tvfio_group_fd = vfio_mp_sync_receive_fd(socket_fd);\n\t\t\t/* if we got the fd, return it */\n\t\t\tif (vfio_group_fd > 0) {\n\t\t\t\tclose(socket_fd);\n\t\t\t\treturn vfio_group_fd;\n\t\t\t}\n\t\t\t/* fall-through on error */\n\t\tdefault:\n\t\t\tRTE_LOG(ERR, EAL, \" cannot get container fd!\\n\");\n\t\t\tclose(socket_fd);\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn -1;\n}\n\n/* parse IOMMU group number for a PCI device\n * returns -1 for errors, 0 for non-existent group */\nstatic int\npci_vfio_get_group_no(const char *pci_addr)\n{\n\tchar linkname[PATH_MAX];\n\tchar filename[PATH_MAX];\n\tchar *tok[16], *group_tok, *end;\n\tint ret, iommu_group_no;\n\n\tmemset(linkname, 0, sizeof(linkname));\n\tmemset(filename, 0, sizeof(filename));\n\n\t/* try to find out IOMMU group for this device */\n\tsnprintf(linkname, sizeof(linkname),\n\t\t\t SYSFS_PCI_DEVICES \"/%s/iommu_group\", pci_addr);\n\n\tret = readlink(linkname, filename, sizeof(filename));\n\n\t/* if the link doesn't exist, no VFIO for us */\n\tif (ret < 0)\n\t\treturn 0;\n\n\tret = rte_strsplit(filename, sizeof(filename),\n\t\t\ttok, RTE_DIM(tok), '/');\n\n\tif (ret <= 0) {\n\t\tRTE_LOG(ERR, EAL, \" %s cannot get IOMMU group\\n\", pci_addr);\n\t\treturn -1;\n\t}\n\n\t/* IOMMU group is always the last token */\n\terrno = 0;\n\tgroup_tok = tok[ret - 1];\n\tend = group_tok;\n\tiommu_group_no = strtol(group_tok, &end, 10);\n\tif ((end != group_tok && *end != '\\0') || errno != 0) {\n\t\tRTE_LOG(ERR, EAL, \" %s error parsing IOMMU number!\\n\", pci_addr);\n\t\treturn -1;\n\t}\n\n\treturn iommu_group_no;\n}\n\nstatic void\nclear_current_group(void)\n{\n\tvfio_cfg.vfio_groups[vfio_cfg.vfio_group_idx].group_no = 0;\n\tvfio_cfg.vfio_groups[vfio_cfg.vfio_group_idx].fd = -1;\n}\n\n\n/*\n * map the PCI resources of a PCI device in virtual memory (VFIO version).\n * primary and secondary processes follow almost exactly the same path\n */\nint\npci_vfio_map_resource(struct rte_pci_device *dev)\n{\n\tstruct vfio_group_status group_status = {\n\t\t\t.argsz = sizeof(group_status)\n\t};\n\tstruct vfio_device_info device_info = { .argsz = sizeof(device_info) };\n\tint vfio_group_fd, vfio_dev_fd;\n\tint iommu_group_no;\n\tchar pci_addr[PATH_MAX] = {0};\n\tstruct rte_pci_addr *loc = &dev->addr;\n\tint i, ret, msix_bar;\n\tstruct mapped_pci_resource *vfio_res = NULL;\n\tstruct mapped_pci_res_list *vfio_res_list = RTE_TAILQ_CAST(rte_vfio_tailq.head, mapped_pci_res_list);\n\n\tstruct pci_map *maps;\n\tuint32_t msix_table_offset = 0;\n\tuint32_t msix_table_size = 0;\n\n\tdev->intr_handle.fd = -1;\n\tdev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;\n\n\t/* store PCI address string */\n\tsnprintf(pci_addr, sizeof(pci_addr), PCI_PRI_FMT,\n\t\t\tloc->domain, loc->bus, loc->devid, loc->function);\n\n\t/* get group number */\n\tiommu_group_no = pci_vfio_get_group_no(pci_addr);\n\n\t/* if 0, group doesn't exist */\n\tif (iommu_group_no == 0) {\n\t\tRTE_LOG(WARNING, EAL, \" %s not managed by VFIO driver, skipping\\n\",\n\t\t\t\tpci_addr);\n\t\treturn 1;\n\t}\n\t/* if negative, something failed */\n\telse if (iommu_group_no < 0)\n\t\treturn -1;\n\n\t/* get the actual group fd */\n\tvfio_group_fd = pci_vfio_get_group_fd(iommu_group_no);\n\tif (vfio_group_fd < 0)\n\t\treturn -1;\n\n\t/* store group fd */\n\tvfio_cfg.vfio_groups[vfio_cfg.vfio_group_idx].group_no = iommu_group_no;\n\tvfio_cfg.vfio_groups[vfio_cfg.vfio_group_idx].fd = vfio_group_fd;\n\n\t/* if group_fd == 0, that means the device isn't managed by VFIO */\n\tif (vfio_group_fd == 0) {\n\t\tRTE_LOG(WARNING, EAL, \" %s not managed by VFIO driver, skipping\\n\",\n\t\t\t\tpci_addr);\n\t\t/* we store 0 as group fd to distinguish between existing but\n\t\t * unbound VFIO groups, and groups that don't exist at all.\n\t\t */\n\t\tvfio_cfg.vfio_group_idx++;\n\t\treturn 1;\n\t}\n\n\t/*\n\t * at this point, we know at least one port on this device is bound to VFIO,\n\t * so we can proceed to try and set this particular port up\n\t */\n\n\t/* check if the group is viable */\n\tret = ioctl(vfio_group_fd, VFIO_GROUP_GET_STATUS, &group_status);\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL, \" %s cannot get group status, \"\n\t\t\t\t\"error %i (%s)\\n\", pci_addr, errno, strerror(errno));\n\t\tclose(vfio_group_fd);\n\t\tclear_current_group();\n\t\treturn -1;\n\t} else if (!(group_status.flags & VFIO_GROUP_FLAGS_VIABLE)) {\n\t\tRTE_LOG(ERR, EAL, \" %s VFIO group is not viable!\\n\", pci_addr);\n\t\tclose(vfio_group_fd);\n\t\tclear_current_group();\n\t\treturn -1;\n\t}\n\n\t/*\n\t * at this point, we know that this group is viable (meaning, all devices\n\t * are either bound to VFIO or not bound to anything)\n\t */\n\n\t/* check if group does not have a container yet */\n\tif (!(group_status.flags & VFIO_GROUP_FLAGS_CONTAINER_SET)) {\n\n\t\t/* add group to a container */\n\t\tret = ioctl(vfio_group_fd, VFIO_GROUP_SET_CONTAINER,\n\t\t\t\t&vfio_cfg.vfio_container_fd);\n\t\tif (ret) {\n\t\t\tRTE_LOG(ERR, EAL, \" %s cannot add VFIO group to container, \"\n\t\t\t\t\t\"error %i (%s)\\n\", pci_addr, errno, strerror(errno));\n\t\t\tclose(vfio_group_fd);\n\t\t\tclear_current_group();\n\t\t\treturn -1;\n\t\t}\n\t\t/*\n\t\t * at this point we know that this group has been successfully\n\t\t * initialized, so we increment vfio_group_idx to indicate that we can\n\t\t * add new groups.\n\t\t */\n\t\tvfio_cfg.vfio_group_idx++;\n\t}\n\n\t/*\n\t * set up DMA mappings for container\n\t *\n\t * needs to be done only once, only when at least one group is assigned to\n\t * a container and only in primary process\n\t */\n\tif (internal_config.process_type == RTE_PROC_PRIMARY &&\n\t\t\tvfio_cfg.vfio_container_has_dma == 0) {\n\t\tret = pci_vfio_setup_dma_maps(vfio_cfg.vfio_container_fd);\n\t\tif (ret) {\n\t\t\tRTE_LOG(ERR, EAL, \" %s DMA remapping failed, \"\n\t\t\t\t\t\"error %i (%s)\\n\", pci_addr, errno, strerror(errno));\n\t\t\treturn -1;\n\t\t}\n\t\tvfio_cfg.vfio_container_has_dma = 1;\n\t}\n\n\t/* get a file descriptor for the device */\n\tvfio_dev_fd = ioctl(vfio_group_fd, VFIO_GROUP_GET_DEVICE_FD, pci_addr);\n\tif (vfio_dev_fd < 0) {\n\t\t/* if we cannot get a device fd, this simply means that this\n\t\t * particular port is not bound to VFIO\n\t\t */\n\t\tRTE_LOG(WARNING, EAL, \" %s not managed by VFIO driver, skipping\\n\",\n\t\t\t\tpci_addr);\n\t\treturn 1;\n\t}\n\n\t/* test and setup the device */\n\tret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_INFO, &device_info);\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL, \" %s cannot get device info, \"\n\t\t\t\t\"error %i (%s)\\n\", pci_addr, errno, strerror(errno));\n\t\tclose(vfio_dev_fd);\n\t\treturn -1;\n\t}\n\n\t/* get MSI-X BAR, if any (we have to know where it is because we can't\n\t * easily mmap it when using VFIO) */\n\tmsix_bar = -1;\n\tret = pci_vfio_get_msix_bar(vfio_dev_fd, &msix_bar,\n\t\t\t\t &msix_table_offset, &msix_table_size);\n\tif (ret < 0) {\n\t\tRTE_LOG(ERR, EAL, \" %s cannot get MSI-X BAR number!\\n\", pci_addr);\n\t\tclose(vfio_dev_fd);\n\t\treturn -1;\n\t}\n\n\t/* if we're in a primary process, allocate vfio_res and get region info */\n\tif (internal_config.process_type == RTE_PROC_PRIMARY) {\n\t\tvfio_res = rte_zmalloc(\"VFIO_RES\", sizeof(*vfio_res), 0);\n\t\tif (vfio_res == NULL) {\n\t\t\tRTE_LOG(ERR, EAL,\n\t\t\t\t\"%s(): cannot store uio mmap details\\n\", __func__);\n\t\t\tclose(vfio_dev_fd);\n\t\t\treturn -1;\n\t\t}\n\t\tmemcpy(&vfio_res->pci_addr, &dev->addr, sizeof(vfio_res->pci_addr));\n\n\t\t/* get number of registers (up to BAR5) */\n\t\tvfio_res->nb_maps = RTE_MIN((int) device_info.num_regions,\n\t\t\t\tVFIO_PCI_BAR5_REGION_INDEX + 1);\n\t} else {\n\t\t/* if we're in a secondary process, just find our tailq entry */\n\t\tTAILQ_FOREACH(vfio_res, vfio_res_list, next) {\n\t\t\tif (memcmp(&vfio_res->pci_addr, &dev->addr, sizeof(dev->addr)))\n\t\t\t\tcontinue;\n\t\t\tbreak;\n\t\t}\n\t\t/* if we haven't found our tailq entry, something's wrong */\n\t\tif (vfio_res == NULL) {\n\t\t\tRTE_LOG(ERR, EAL, \" %s cannot find TAILQ entry for PCI device!\\n\",\n\t\t\t\t\tpci_addr);\n\t\t\tclose(vfio_dev_fd);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\t/* map BARs */\n\tmaps = vfio_res->maps;\n\n\tfor (i = 0; i < (int) vfio_res->nb_maps; i++) {\n\t\tstruct vfio_region_info reg = { .argsz = sizeof(reg) };\n\t\tvoid *bar_addr;\n\t\tstruct memreg {\n\t\t\tunsigned long offset, size;\n\t\t} memreg[2] = {};\n\n\t\treg.index = i;\n\n\t\tret = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_REGION_INFO, ®);\n\n\t\tif (ret) {\n\t\t\tRTE_LOG(ERR, EAL, \" %s cannot get device region info \"\n\t\t\t\t\t\"error %i (%s)\\n\", pci_addr, errno, strerror(errno));\n\t\t\tclose(vfio_dev_fd);\n\t\t\tif (internal_config.process_type == RTE_PROC_PRIMARY)\n\t\t\t\trte_free(vfio_res);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* skip non-mmapable BARs */\n\t\tif ((reg.flags & VFIO_REGION_INFO_FLAG_MMAP) == 0)\n\t\t\tcontinue;\n\n\t\tif (i == msix_bar) {\n\t\t\t/*\n\t\t\t * VFIO will not let us map the MSI-X table,\n\t\t\t * but we can map around it.\n\t\t\t */\n\t\t\tuint32_t table_start = msix_table_offset;\n\t\t\tuint32_t table_end = table_start + msix_table_size;\n\t\t\ttable_end = (table_end + ~PAGE_MASK) & PAGE_MASK;\n\t\t\ttable_start &= PAGE_MASK;\n\n\t\t\tif (table_start == 0 && table_end >= reg.size) {\n\t\t\t\t/* Cannot map this BAR */\n\t\t\t\tRTE_LOG(DEBUG, EAL, \"Skipping BAR %d\\n\", i);\n\t\t\t\tcontinue;\n\t\t\t} else {\n\t\t\t\tmemreg[0].offset = reg.offset;\n\t\t\t\tmemreg[0].size = table_start;\n\t\t\t\tmemreg[1].offset = table_end;\n\t\t\t\tmemreg[1].size = reg.size - table_end;\n\n\t\t\t\tRTE_LOG(DEBUG, EAL,\n\t\t\t\t\t\"Trying to map BAR %d that contains the MSI-X \"\n\t\t\t\t\t\"table. Trying offsets: \"\n\t\t\t\t\t\"0x%04lx:0x%04lx, 0x%04lx:0x%04lx\\n\", i,\n\t\t\t\t\tmemreg[0].offset, memreg[0].size,\n\t\t\t\t\tmemreg[1].offset, memreg[1].size);\n\t\t\t}\n\t\t} else {\n\t\t\tmemreg[0].offset = reg.offset;\n\t\t\tmemreg[0].size = reg.size;\n\t\t}\n\n\t\t/* try to figure out an address */\n\t\tif (internal_config.process_type == RTE_PROC_PRIMARY) {\n\t\t\t/* try mapping somewhere close to the end of hugepages */\n\t\t\tif (pci_map_addr == NULL)\n\t\t\t\tpci_map_addr = pci_find_max_end_va();\n\n\t\t\tbar_addr = pci_map_addr;\n\t\t\tpci_map_addr = RTE_PTR_ADD(bar_addr, (size_t) reg.size);\n\t\t} else {\n\t\t\tbar_addr = maps[i].addr;\n\t\t}\n\n\t\t/* reserve the address using an inaccessible mapping */\n\t\tbar_addr = mmap(bar_addr, reg.size, 0, MAP_PRIVATE |\n\t\t\t\tMAP_ANONYMOUS, -1, 0);\n\t\tif (bar_addr != MAP_FAILED) {\n\t\t\tvoid *map_addr = NULL;\n\t\t\tif (memreg[0].size) {\n\t\t\t\t/* actual map of first part */\n\t\t\t\tmap_addr = pci_map_resource(bar_addr, vfio_dev_fd,\n\t\t\t\t\t\t\t memreg[0].offset,\n\t\t\t\t\t\t\t memreg[0].size,\n\t\t\t\t\t\t\t MAP_FIXED);\n\t\t\t}\n\n\t\t\t/* if there's a second part, try to map it */\n\t\t\tif (map_addr != MAP_FAILED\n\t\t\t && memreg[1].offset && memreg[1].size) {\n\t\t\t\tvoid *second_addr = RTE_PTR_ADD(bar_addr, memreg[1].offset);\n\t\t\t\tmap_addr = pci_map_resource(second_addr,\n\t\t\t\t\t\t\t vfio_dev_fd, memreg[1].offset,\n\t\t\t\t\t\t\t memreg[1].size,\n\t\t\t\t\t\t\t MAP_FIXED);\n\t\t\t}\n\n\t\t\tif (map_addr == MAP_FAILED || !map_addr) {\n\t\t\t\tmunmap(bar_addr, reg.size);\n\t\t\t\tbar_addr = MAP_FAILED;\n\t\t\t}\n\t\t}\n\n\t\tif (bar_addr == MAP_FAILED ||\n\t\t\t\t(internal_config.process_type == RTE_PROC_SECONDARY &&\n\t\t\t\t\t\tbar_addr != maps[i].addr)) {\n\t\t\tRTE_LOG(ERR, EAL, \" %s mapping BAR%i failed: %s\\n\", pci_addr, i,\n\t\t\t\t\tstrerror(errno));\n\t\t\tclose(vfio_dev_fd);\n\t\t\tif (internal_config.process_type == RTE_PROC_PRIMARY)\n\t\t\t\trte_free(vfio_res);\n\t\t\treturn -1;\n\t\t}\n\n\t\tmaps[i].addr = bar_addr;\n\t\tmaps[i].offset = reg.offset;\n\t\tmaps[i].size = reg.size;\n\t\tmaps[i].path = NULL; /* vfio doesn't have per-resource paths */\n\t\tdev->mem_resource[i].addr = bar_addr;\n\t}\n\n\t/* if secondary process, do not set up interrupts */\n\tif (internal_config.process_type == RTE_PROC_PRIMARY) {\n\t\tif (pci_vfio_setup_interrupts(dev, vfio_dev_fd) != 0) {\n\t\t\tRTE_LOG(ERR, EAL, \" %s error setting up interrupts!\\n\", pci_addr);\n\t\t\tclose(vfio_dev_fd);\n\t\t\trte_free(vfio_res);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* set bus mastering for the device */\n\t\tif (pci_vfio_set_bus_master(vfio_dev_fd)) {\n\t\t\tRTE_LOG(ERR, EAL, \" %s cannot set up bus mastering!\\n\", pci_addr);\n\t\t\tclose(vfio_dev_fd);\n\t\t\trte_free(vfio_res);\n\t\t\treturn -1;\n\t\t}\n\n\t\t/* Reset the device */\n\t\tioctl(vfio_dev_fd, VFIO_DEVICE_RESET);\n\t}\n\n\tif (internal_config.process_type == RTE_PROC_PRIMARY)\n\t\tTAILQ_INSERT_TAIL(vfio_res_list, vfio_res, next);\n\n\treturn 0;\n}\n\nint\npci_vfio_enable(void)\n{\n\t/* initialize group list */\n\tint i;\n\tint module_vfio_type1;\n\n\tfor (i = 0; i < VFIO_MAX_GROUPS; i++) {\n\t\tvfio_cfg.vfio_groups[i].fd = -1;\n\t\tvfio_cfg.vfio_groups[i].group_no = -1;\n\t}\n\n\tmodule_vfio_type1 = rte_eal_check_module(\"vfio_iommu_type1\");\n\n\t/* return error directly */\n\tif (module_vfio_type1 == -1) {\n\t\tRTE_LOG(INFO, EAL, \"Could not get loaded module details!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* return 0 if VFIO modules not loaded */\n\tif (module_vfio_type1 == 0) {\n\t\tRTE_LOG(INFO, EAL, \"VFIO modules not all loaded, \"\n\t\t\t\"skip VFIO support...\\n\");\n\t\treturn 0;\n\t}\n\n\tvfio_cfg.vfio_container_fd = pci_vfio_get_container_fd();\n\n\t/* check if we have VFIO driver enabled */\n\tif (vfio_cfg.vfio_container_fd != -1)\n\t\tvfio_cfg.vfio_enabled = 1;\n\telse\n\t\tRTE_LOG(NOTICE, EAL, \"VFIO support could not be initialized\\n\");\n\n\treturn 0;\n}\n\nint\npci_vfio_is_enabled(void)\n{\n\treturn vfio_cfg.vfio_enabled;\n}\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_pci_vfio_mp_sync.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n/* sys/un.h with __USE_MISC uses strlen, which is unsafe */\n#ifdef __USE_MISC\n#define REMOVED_USE_MISC\n#undef __USE_MISC\n#endif\n#include \n/* make sure we redefine __USE_MISC only if it was previously undefined */\n#ifdef REMOVED_USE_MISC\n#define __USE_MISC\n#undef REMOVED_USE_MISC\n#endif\n\n#include \n#include \n#include \n#include \n\n#include \"eal_filesystem.h\"\n#include \"eal_pci_init.h\"\n\n/**\n * @file\n * VFIO socket for communication between primary and secondary processes.\n *\n * This file is only compiled if CONFIG_RTE_EAL_VFIO is set to \"y\".\n */\n\n#ifdef VFIO_PRESENT\n\n#define SOCKET_PATH_FMT \"%s/.%s_mp_socket\"\n#define CMSGLEN (CMSG_LEN(sizeof(int)))\n#define FD_TO_CMSGHDR(fd, chdr) \\\n\t\tdo {\\\n\t\t\t(chdr).cmsg_len = CMSGLEN;\\\n\t\t\t(chdr).cmsg_level = SOL_SOCKET;\\\n\t\t\t(chdr).cmsg_type = SCM_RIGHTS;\\\n\t\t\tmemcpy((chdr).__cmsg_data, &(fd), sizeof(fd));\\\n\t\t} while (0)\n#define CMSGHDR_TO_FD(chdr, fd) \\\n\t\t\tmemcpy(&(fd), (chdr).__cmsg_data, sizeof(fd))\n\nstatic pthread_t socket_thread;\nstatic int mp_socket_fd;\n\n\n/* get socket path (/var/run if root, $HOME otherwise) */\nstatic void\nget_socket_path(char *buffer, int bufsz)\n{\n\tconst char *dir = \"/var/run\";\n\tconst char *home_dir = getenv(\"HOME\");\n\n\tif (getuid() != 0 && home_dir != NULL)\n\t\tdir = home_dir;\n\n\t/* use current prefix as file path */\n\tsnprintf(buffer, bufsz, SOCKET_PATH_FMT, dir,\n\t\t\tinternal_config.hugefile_prefix);\n}\n\n\n\n/*\n * data flow for socket comm protocol:\n * 1. client sends SOCKET_REQ_CONTAINER or SOCKET_REQ_GROUP\n * 1a. in case of SOCKET_REQ_GROUP, client also then sends group number\n * 2. server receives message\n * 2a. in case of invalid group, SOCKET_ERR is sent back to client\n * 2b. in case of unbound group, SOCKET_NO_FD is sent back to client\n * 2c. in case of valid group, SOCKET_OK is sent and immediately followed by fd\n *\n * in case of any error, socket is closed.\n */\n\n/* send a request, return -1 on error */\nint\nvfio_mp_sync_send_request(int socket, int req)\n{\n\tstruct msghdr hdr;\n\tstruct iovec iov;\n\tint buf;\n\tint ret;\n\n\tmemset(&hdr, 0, sizeof(hdr));\n\n\tbuf = req;\n\n\thdr.msg_iov = &iov;\n\thdr.msg_iovlen = 1;\n\tiov.iov_base = (char *) &buf;\n\tiov.iov_len = sizeof(buf);\n\n\tret = sendmsg(socket, &hdr, 0);\n\tif (ret < 0)\n\t\treturn -1;\n\treturn 0;\n}\n\n/* receive a request and return it */\nint\nvfio_mp_sync_receive_request(int socket)\n{\n\tint buf;\n\tstruct msghdr hdr;\n\tstruct iovec iov;\n\tint ret, req;\n\n\tmemset(&hdr, 0, sizeof(hdr));\n\n\tbuf = SOCKET_ERR;\n\n\thdr.msg_iov = &iov;\n\thdr.msg_iovlen = 1;\n\tiov.iov_base = (char *) &buf;\n\tiov.iov_len = sizeof(buf);\n\n\tret = recvmsg(socket, &hdr, 0);\n\tif (ret < 0)\n\t\treturn -1;\n\n\treq = buf;\n\n\treturn req;\n}\n\n/* send OK in message, fd in control message */\nint\nvfio_mp_sync_send_fd(int socket, int fd)\n{\n\tint buf;\n\tstruct msghdr hdr;\n\tstruct cmsghdr *chdr;\n\tchar chdr_buf[CMSGLEN];\n\tstruct iovec iov;\n\tint ret;\n\n\tchdr = (struct cmsghdr *) chdr_buf;\n\tmemset(chdr, 0, sizeof(chdr_buf));\n\tmemset(&hdr, 0, sizeof(hdr));\n\n\thdr.msg_iov = &iov;\n\thdr.msg_iovlen = 1;\n\tiov.iov_base = (char *) &buf;\n\tiov.iov_len = sizeof(buf);\n\thdr.msg_control = chdr;\n\thdr.msg_controllen = CMSGLEN;\n\n\tbuf = SOCKET_OK;\n\tFD_TO_CMSGHDR(fd, *chdr);\n\n\tret = sendmsg(socket, &hdr, 0);\n\tif (ret < 0)\n\t\treturn -1;\n\treturn 0;\n}\n\n/* receive OK in message, fd in control message */\nint\nvfio_mp_sync_receive_fd(int socket)\n{\n\tint buf;\n\tstruct msghdr hdr;\n\tstruct cmsghdr *chdr;\n\tchar chdr_buf[CMSGLEN];\n\tstruct iovec iov;\n\tint ret, req, fd;\n\n\tbuf = SOCKET_ERR;\n\n\tchdr = (struct cmsghdr *) chdr_buf;\n\tmemset(chdr, 0, sizeof(chdr_buf));\n\tmemset(&hdr, 0, sizeof(hdr));\n\n\thdr.msg_iov = &iov;\n\thdr.msg_iovlen = 1;\n\tiov.iov_base = (char *) &buf;\n\tiov.iov_len = sizeof(buf);\n\thdr.msg_control = chdr;\n\thdr.msg_controllen = CMSGLEN;\n\n\tret = recvmsg(socket, &hdr, 0);\n\tif (ret < 0)\n\t\treturn -1;\n\n\treq = buf;\n\n\tif (req != SOCKET_OK)\n\t\treturn -1;\n\n\tCMSGHDR_TO_FD(*chdr, fd);\n\n\treturn fd;\n}\n\n/* connect socket_fd in secondary process to the primary process's socket */\nint\nvfio_mp_sync_connect_to_primary(void)\n{\n\tstruct sockaddr_un addr;\n\tsocklen_t sockaddr_len;\n\tint socket_fd;\n\n\t/* set up a socket */\n\tsocket_fd = socket(AF_UNIX, SOCK_SEQPACKET, 0);\n\tif (socket_fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Failed to create socket!\\n\");\n\t\treturn -1;\n\t}\n\n\tget_socket_path(addr.sun_path, sizeof(addr.sun_path));\n\taddr.sun_family = AF_UNIX;\n\n\tsockaddr_len = sizeof(struct sockaddr_un);\n\n\tif (connect(socket_fd, (struct sockaddr *) &addr, sockaddr_len) == 0)\n\t\treturn socket_fd;\n\n\t/* if connect failed */\n\tclose(socket_fd);\n\treturn -1;\n}\n\n\n\n/*\n * socket listening thread for primary process\n */\nstatic __attribute__((noreturn)) void *\npci_vfio_mp_sync_thread(void __rte_unused * arg)\n{\n\tint ret, fd, vfio_group_no;\n\n\t/* wait for requests on the socket */\n\tfor (;;) {\n\t\tint conn_sock;\n\t\tstruct sockaddr_un addr;\n\t\tsocklen_t sockaddr_len = sizeof(addr);\n\n\t\t/* this is a blocking call */\n\t\tconn_sock = accept(mp_socket_fd, (struct sockaddr *) &addr,\n\t\t\t\t&sockaddr_len);\n\n\t\t/* just restart on error */\n\t\tif (conn_sock == -1)\n\t\t\tcontinue;\n\n\t\t/* set socket to linger after close */\n\t\tstruct linger l;\n\t\tl.l_onoff = 1;\n\t\tl.l_linger = 60;\n\t\tsetsockopt(conn_sock, SOL_SOCKET, SO_LINGER, &l, sizeof(l));\n\n\t\tret = vfio_mp_sync_receive_request(conn_sock);\n\n\t\tswitch (ret) {\n\t\tcase SOCKET_REQ_CONTAINER:\n\t\t\tfd = pci_vfio_get_container_fd();\n\t\t\tif (fd < 0)\n\t\t\t\tvfio_mp_sync_send_request(conn_sock, SOCKET_ERR);\n\t\t\telse\n\t\t\t\tvfio_mp_sync_send_fd(conn_sock, fd);\n\t\t\tbreak;\n\t\tcase SOCKET_REQ_GROUP:\n\t\t\t/* wait for group number */\n\t\t\tvfio_group_no = vfio_mp_sync_receive_request(conn_sock);\n\t\t\tif (vfio_group_no < 0) {\n\t\t\t\tclose(conn_sock);\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tfd = pci_vfio_get_group_fd(vfio_group_no);\n\n\t\t\tif (fd < 0)\n\t\t\t\tvfio_mp_sync_send_request(conn_sock, SOCKET_ERR);\n\t\t\t/* if VFIO group exists but isn't bound to VFIO driver */\n\t\t\telse if (fd == 0)\n\t\t\t\tvfio_mp_sync_send_request(conn_sock, SOCKET_NO_FD);\n\t\t\t/* if group exists and is bound to VFIO driver */\n\t\t\telse {\n\t\t\t\tvfio_mp_sync_send_request(conn_sock, SOCKET_OK);\n\t\t\t\tvfio_mp_sync_send_fd(conn_sock, fd);\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tvfio_mp_sync_send_request(conn_sock, SOCKET_ERR);\n\t\t\tbreak;\n\t\t}\n\t\tclose(conn_sock);\n\t}\n}\n\nstatic int\nvfio_mp_sync_socket_setup(void)\n{\n\tint ret, socket_fd;\n\tstruct sockaddr_un addr;\n\tsocklen_t sockaddr_len;\n\n\t/* set up a socket */\n\tsocket_fd = socket(AF_UNIX, SOCK_SEQPACKET, 0);\n\tif (socket_fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Failed to create socket!\\n\");\n\t\treturn -1;\n\t}\n\n\tget_socket_path(addr.sun_path, sizeof(addr.sun_path));\n\taddr.sun_family = AF_UNIX;\n\n\tsockaddr_len = sizeof(struct sockaddr_un);\n\n\tunlink(addr.sun_path);\n\n\tret = bind(socket_fd, (struct sockaddr *) &addr, sockaddr_len);\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL, \"Failed to bind socket: %s!\\n\", strerror(errno));\n\t\tclose(socket_fd);\n\t\treturn -1;\n\t}\n\n\tret = listen(socket_fd, 50);\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL, \"Failed to listen: %s!\\n\", strerror(errno));\n\t\tclose(socket_fd);\n\t\treturn -1;\n\t}\n\n\t/* save the socket in local configuration */\n\tmp_socket_fd = socket_fd;\n\n\treturn 0;\n}\n\n/*\n * set up a local socket and tell it to listen for incoming connections\n */\nint\npci_vfio_mp_sync_setup(void)\n{\n\tint ret;\n\n\tif (vfio_mp_sync_socket_setup() < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Failed to set up local socket!\\n\");\n\t\treturn -1;\n\t}\n\n\tret = pthread_create(&socket_thread, NULL,\n\t\t\tpci_vfio_mp_sync_thread, NULL);\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL, \"Failed to create thread for communication with \"\n\t\t\t\t\"secondary processes!\\n\");\n\t\tclose(mp_socket_fd);\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_thread.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_thread.h\"\n\nRTE_DEFINE_PER_LCORE(unsigned, _lcore_id) = LCORE_ID_ANY;\nRTE_DEFINE_PER_LCORE(unsigned, _socket_id) = (unsigned)SOCKET_ID_ANY;\nRTE_DEFINE_PER_LCORE(rte_cpuset_t, _cpuset);\n\n/*\n * Send a message to a slave lcore identified by slave_id to call a\n * function f with argument arg. Once the execution is done, the\n * remote lcore switch in FINISHED state.\n */\nint\nrte_eal_remote_launch(int (*f)(void *), void *arg, unsigned slave_id)\n{\n\tint n;\n\tchar c = 0;\n\tint m2s = lcore_config[slave_id].pipe_master2slave[1];\n\tint s2m = lcore_config[slave_id].pipe_slave2master[0];\n\n\tif (lcore_config[slave_id].state != WAIT)\n\t\treturn -EBUSY;\n\n\tlcore_config[slave_id].f = f;\n\tlcore_config[slave_id].arg = arg;\n\n\t/* send message */\n\tn = 0;\n\twhile (n == 0 || (n < 0 && errno == EINTR))\n\t\tn = write(m2s, &c, 1);\n\tif (n < 0)\n\t\trte_panic(\"cannot write on configuration pipe\\n\");\n\n\t/* wait ack */\n\tdo {\n\t\tn = read(s2m, &c, 1);\n\t} while (n < 0 && errno == EINTR);\n\n\tif (n <= 0)\n\t\trte_panic(\"cannot read on configuration pipe\\n\");\n\n\treturn 0;\n}\n\n/* set affinity for current EAL thread */\nstatic int\neal_thread_set_affinity(void)\n{\n\tunsigned lcore_id = rte_lcore_id();\n\n\t/* acquire system unique id */\n\trte_gettid();\n\n\t/* update EAL thread core affinity */\n\treturn rte_thread_set_affinity(&lcore_config[lcore_id].cpuset);\n}\n\nvoid eal_thread_init_master(unsigned lcore_id)\n{\n\t/* set the lcore ID in per-lcore memory area */\n\tRTE_PER_LCORE(_lcore_id) = lcore_id;\n\n\t/* set CPU affinity */\n\tif (eal_thread_set_affinity() < 0)\n\t\trte_panic(\"cannot set affinity\\n\");\n}\n\n/* main loop of threads */\n__attribute__((noreturn)) void *\neal_thread_loop(__attribute__((unused)) void *arg)\n{\n\tchar c;\n\tint n, ret;\n\tunsigned lcore_id;\n\tpthread_t thread_id;\n\tint m2s, s2m;\n\tchar cpuset[RTE_CPU_AFFINITY_STR_LEN];\n\n\tthread_id = pthread_self();\n\n\t/* retrieve our lcore_id from the configuration structure */\n\tRTE_LCORE_FOREACH_SLAVE(lcore_id) {\n\t\tif (thread_id == lcore_config[lcore_id].thread_id)\n\t\t\tbreak;\n\t}\n\tif (lcore_id == RTE_MAX_LCORE)\n\t\trte_panic(\"cannot retrieve lcore id\\n\");\n\n\tm2s = lcore_config[lcore_id].pipe_master2slave[0];\n\ts2m = lcore_config[lcore_id].pipe_slave2master[1];\n\n\t/* set the lcore ID in per-lcore memory area */\n\tRTE_PER_LCORE(_lcore_id) = lcore_id;\n\n\t/* set CPU affinity */\n\tif (eal_thread_set_affinity() < 0)\n\t\trte_panic(\"cannot set affinity\\n\");\n\n\tret = eal_thread_dump_affinity(cpuset, RTE_CPU_AFFINITY_STR_LEN);\n\n\tRTE_LOG(DEBUG, EAL, \"lcore %u is ready (tid=%x;cpuset=[%s%s])\\n\",\n\t\tlcore_id, (int)thread_id, cpuset, ret == 0 ? \"\" : \"...\");\n\n\t/* read on our pipe to get commands */\n\twhile (1) {\n\t\tvoid *fct_arg;\n\n\t\t/* wait command */\n\t\tdo {\n\t\t\tn = read(m2s, &c, 1);\n\t\t} while (n < 0 && errno == EINTR);\n\n\t\tif (n <= 0)\n\t\t\trte_panic(\"cannot read on configuration pipe\\n\");\n\n\t\tlcore_config[lcore_id].state = RUNNING;\n\n\t\t/* send ack */\n\t\tn = 0;\n\t\twhile (n == 0 || (n < 0 && errno == EINTR))\n\t\t\tn = write(s2m, &c, 1);\n\t\tif (n < 0)\n\t\t\trte_panic(\"cannot write on configuration pipe\\n\");\n\n\t\tif (lcore_config[lcore_id].f == NULL)\n\t\t\trte_panic(\"NULL function pointer\\n\");\n\n\t\t/* call the function and store the return value */\n\t\tfct_arg = lcore_config[lcore_id].arg;\n\t\tret = lcore_config[lcore_id].f(fct_arg);\n\t\tlcore_config[lcore_id].ret = ret;\n\t\trte_wmb();\n\t\tlcore_config[lcore_id].state = FINISHED;\n\t}\n\n\t/* never reached */\n\t/* pthread_exit(NULL); */\n\t/* return NULL; */\n}\n\n/* require calling thread tid by gettid() */\nint rte_sys_gettid(void)\n{\n\treturn (int)syscall(SYS_gettid);\n}\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_timer.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright(c) 2012-2013 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_internal_cfg.h\"\n\nenum timer_source eal_timer_source = EAL_TIMER_HPET;\n\n#ifdef RTE_LIBEAL_USE_HPET\n\n#define DEV_HPET \"/dev/hpet\"\n\n/* Maximum number of counters. */\n#define HPET_TIMER_NUM 3\n\n/* General capabilities register */\n#define CLK_PERIOD_SHIFT 32 /* Clock period shift. */\n#define CLK_PERIOD_MASK 0xffffffff00000000ULL /* Clock period mask. */\n\n/**\n * HPET timer registers. From the Intel IA-PC HPET (High Precision Event\n * Timers) Specification.\n */\nstruct eal_hpet_regs {\n\t/* Memory-mapped, software visible registers */\n\tuint64_t capabilities; /**< RO General Capabilities Register. */\n\tuint64_t reserved0; /**< Reserved for future use. */\n\tuint64_t config; /**< RW General Configuration Register. */\n\tuint64_t reserved1; /**< Reserved for future use. */\n\tuint64_t isr; /**< RW Clear General Interrupt Status. */\n\tuint64_t reserved2[25]; /**< Reserved for future use. */\n\tunion {\n\t\tuint64_t counter; /**< RW Main Counter Value Register. */\n\t\tstruct {\n\t\t\tuint32_t counter_l; /**< RW Main Counter Low. */\n\t\t\tuint32_t counter_h; /**< RW Main Counter High. */\n\t\t};\n\t};\n\tuint64_t reserved3; /**< Reserved for future use. */\n\tstruct {\n\t\tuint64_t config; /**< RW Timer Config and Capability Reg. */\n\t\tuint64_t comp; /**< RW Timer Comparator Value Register. */\n\t\tuint64_t fsb; /**< RW FSB Interrupt Route Register. */\n\t\tuint64_t reserved4; /**< Reserved for future use. */\n\t} timers[HPET_TIMER_NUM]; /**< Set of HPET timers. */\n};\n\n/* Mmap'd hpet registers */\nstatic volatile struct eal_hpet_regs *eal_hpet = NULL;\n\n/* Period at which the HPET counter increments in\n * femtoseconds (10^-15 seconds). */\nstatic uint32_t eal_hpet_resolution_fs = 0;\n\n/* Frequency of the HPET counter in Hz */\nstatic uint64_t eal_hpet_resolution_hz = 0;\n\n/* Incremented 4 times during one 32bits hpet full count */\nstatic uint32_t eal_hpet_msb;\n\nstatic pthread_t msb_inc_thread_id;\n\n/*\n * This function runs on a specific thread to update a global variable\n * containing used to process MSB of the HPET (unfortunatelly, we need\n * this because hpet is 32 bits by default under linux).\n */\nstatic void\nhpet_msb_inc(__attribute__((unused)) void *arg)\n{\n\tuint32_t t;\n\n\twhile (1) {\n\t\tt = (eal_hpet->counter_l >> 30);\n\t\tif (t != (eal_hpet_msb & 3))\n\t\t\teal_hpet_msb ++;\n\t\tsleep(10);\n\t}\n}\n\nuint64_t\nrte_get_hpet_hz(void)\n{\n\tif(internal_config.no_hpet)\n\t\trte_panic(\"Error, HPET called, but no HPET present\\n\");\n\n\treturn eal_hpet_resolution_hz;\n}\n\nuint64_t\nrte_get_hpet_cycles(void)\n{\n\tuint32_t t, msb;\n\tuint64_t ret;\n\n\tif(internal_config.no_hpet)\n\t\trte_panic(\"Error, HPET called, but no HPET present\\n\");\n\n\tt = eal_hpet->counter_l;\n\tmsb = eal_hpet_msb;\n\tret = (msb + 2 - (t >> 30)) / 4;\n\tret <<= 32;\n\tret += t;\n\treturn ret;\n}\n\n#endif\n\n#ifdef RTE_LIBEAL_USE_HPET\n/*\n * Open and mmap /dev/hpet (high precision event timer) that will\n * provide our time reference.\n */\nint\nrte_eal_hpet_init(int make_default)\n{\n\tint fd, ret;\n\n\tif (internal_config.no_hpet) {\n\t\tRTE_LOG(NOTICE, EAL, \"HPET is disabled\\n\");\n\t\treturn -1;\n\t}\n\n\tfd = open(DEV_HPET, O_RDONLY);\n\tif (fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"ERROR: Cannot open \"DEV_HPET\": %s!\\n\",\n\t\t\tstrerror(errno));\n\t\tinternal_config.no_hpet = 1;\n\t\treturn -1;\n\t}\n\teal_hpet = mmap(NULL, 1024, PROT_READ, MAP_SHARED, fd, 0);\n\tif (eal_hpet == MAP_FAILED) {\n\t\tRTE_LOG(ERR, EAL, \"ERROR: Cannot mmap \"DEV_HPET\"!\\n\"\n\t\t\t\t\"Please enable CONFIG_HPET_MMAP in your kernel configuration \"\n\t\t\t\t\"to allow HPET support.\\n\"\n\t\t\t\t\"To run without using HPET, set CONFIG_RTE_LIBEAL_USE_HPET=n \"\n\t\t\t\t\"in your build configuration or use '--no-hpet' EAL flag.\\n\");\n\t\tclose(fd);\n\t\tinternal_config.no_hpet = 1;\n\t\treturn -1;\n\t}\n\tclose(fd);\n\n\teal_hpet_resolution_fs = (uint32_t)((eal_hpet->capabilities &\n\t\t\t\t\tCLK_PERIOD_MASK) >>\n\t\t\t\t\tCLK_PERIOD_SHIFT);\n\n\teal_hpet_resolution_hz = (1000ULL*1000ULL*1000ULL*1000ULL*1000ULL) /\n\t\t(uint64_t)eal_hpet_resolution_fs;\n\n\tRTE_LOG(INFO, EAL, \"HPET frequency is ~%\"PRIu64\" kHz\\n\",\n\t\t\teal_hpet_resolution_hz/1000);\n\n\teal_hpet_msb = (eal_hpet->counter_l >> 30);\n\n\t/* create a thread that will increment a global variable for\n\t * msb (hpet is 32 bits by default under linux) */\n\tret = pthread_create(&msb_inc_thread_id, NULL,\n\t\t\t(void *(*)(void *))hpet_msb_inc, NULL);\n\tif (ret < 0) {\n\t\tRTE_LOG(ERR, EAL, \"ERROR: Cannot create HPET timer thread!\\n\");\n\t\tinternal_config.no_hpet = 1;\n\t\treturn -1;\n\t}\n\n\tif (make_default)\n\t\teal_timer_source = EAL_TIMER_HPET;\n\treturn 0;\n}\n#endif\n\nstatic void\ncheck_tsc_flags(void)\n{\n\tchar line[512];\n\tFILE *stream;\n\n\tstream = fopen(\"/proc/cpuinfo\", \"r\");\n\tif (!stream) {\n\t\tRTE_LOG(WARNING, EAL, \"WARNING: Unable to open /proc/cpuinfo\\n\");\n\t\treturn;\n\t}\n\n\twhile (fgets(line, sizeof line, stream)) {\n\t\tchar *constant_tsc;\n\t\tchar *nonstop_tsc;\n\n\t\tif (strncmp(line, \"flags\", 5) != 0)\n\t\t\tcontinue;\n\n\t\tconstant_tsc = strstr(line, \"constant_tsc\");\n\t\tnonstop_tsc = strstr(line, \"nonstop_tsc\");\n\t\tif (!constant_tsc || !nonstop_tsc)\n\t\t\tRTE_LOG(WARNING, EAL,\n\t\t\t\t\"WARNING: cpu flags \"\n\t\t\t\t\"constant_tsc=%s \"\n\t\t\t\t\"nonstop_tsc=%s \"\n\t\t\t\t\"-> using unreliable clock cycles !\\n\",\n\t\t\t\tconstant_tsc ? \"yes\":\"no\",\n\t\t\t\tnonstop_tsc ? \"yes\":\"no\");\n\t\tbreak;\n\t}\n\n\tfclose(stream);\n}\n\nuint64_t\nget_tsc_freq(void)\n{\n#ifdef CLOCK_MONOTONIC_RAW\n#define NS_PER_SEC 1E9\n\n\tstruct timespec sleeptime = {.tv_nsec = 5E8 }; /* 1/2 second */\n\n\tstruct timespec t_start, t_end;\n\tuint64_t tsc_hz;\n\n\tif (clock_gettime(CLOCK_MONOTONIC_RAW, &t_start) == 0) {\n\t\tuint64_t ns, end, start = rte_rdtsc();\n\t\tnanosleep(&sleeptime,NULL);\n\t\tclock_gettime(CLOCK_MONOTONIC_RAW, &t_end);\n\t\tend = rte_rdtsc();\n\t\tns = ((t_end.tv_sec - t_start.tv_sec) * NS_PER_SEC);\n\t\tns += (t_end.tv_nsec - t_start.tv_nsec);\n\n\t\tdouble secs = (double)ns/NS_PER_SEC;\n\t\ttsc_hz = (uint64_t)((end - start)/secs);\n\t\treturn tsc_hz;\n\t}\n#endif\n\treturn 0;\n}\n\nint\nrte_eal_timer_init(void)\n{\n\n\teal_timer_source = EAL_TIMER_TSC;\n\n\tset_tsc_freq();\n\tcheck_tsc_flags();\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_vfio.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef EAL_VFIO_H_\n#define EAL_VFIO_H_\n\n/*\n * determine if VFIO is present on the system\n */\n#ifdef RTE_EAL_VFIO\n#include \n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)\n#include \n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)\n#define RTE_PCI_MSIX_TABLE_BIR 0x7\n#define RTE_PCI_MSIX_TABLE_OFFSET 0xfffffff8\n#define RTE_PCI_MSIX_FLAGS_QSIZE 0x07ff\n#else\n#define RTE_PCI_MSIX_TABLE_BIR PCI_MSIX_TABLE_BIR\n#define RTE_PCI_MSIX_TABLE_OFFSET PCI_MSIX_TABLE_OFFSET\n#define RTE_PCI_MSIX_FLAGS_QSIZE PCI_MSIX_FLAGS_QSIZE\n#endif\n\n#define VFIO_PRESENT\n#endif /* kernel version */\n#endif /* RTE_EAL_VFIO */\n\n#endif /* EAL_VFIO_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/eal/eal_xen_memory.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eal_private.h\"\n#include \"eal_internal_cfg.h\"\n#include \"eal_filesystem.h\"\n#include \n\n#define PAGE_SIZE RTE_PGSIZE_4K\n#define DEFAUL_DOM0_NAME \"dom0-mem\"\n\nstatic int xen_fd = -1;\nstatic const char sys_dir_path[] = \"/sys/kernel/mm/dom0-mm/memsize-mB\";\n\n/*\n * Try to mmap *size bytes in /dev/zero. If it is successful, return the\n * pointer to the mmap'd area and keep *size unmodified. Else, retry\n * with a smaller zone: decrease *size by mem_size until it reaches\n * 0. In this case, return NULL. Note: this function returns an address\n * which is a multiple of mem_size size.\n */\nstatic void *\nxen_get_virtual_area(size_t *size, size_t mem_size)\n{\n\tvoid *addr;\n\tint fd;\n\tlong aligned_addr;\n\n\tRTE_LOG(DEBUG, EAL, \"Ask a virtual area of 0x%zu bytes\\n\", *size);\n\n\tfd = open(\"/dev/zero\", O_RDONLY);\n\tif (fd < 0){\n\t\tRTE_LOG(ERR, EAL, \"Cannot open /dev/zero\\n\");\n\t\treturn NULL;\n\t}\n\tdo {\n\t\taddr = mmap(NULL, (*size) + mem_size, PROT_READ,\n\t\t\tMAP_PRIVATE, fd, 0);\n\t\tif (addr == MAP_FAILED)\n\t\t\t*size -= mem_size;\n\t} while (addr == MAP_FAILED && *size > 0);\n\n\tif (addr == MAP_FAILED) {\n\t\tclose(fd);\n\t\tRTE_LOG(ERR, EAL, \"Cannot get a virtual area\\n\");\n\t\treturn NULL;\n\t}\n\n\tmunmap(addr, (*size) + mem_size);\n\tclose(fd);\n\n\t/* align addr to a mem_size boundary */\n\taligned_addr = (uintptr_t)addr;\n\taligned_addr = RTE_ALIGN_CEIL(aligned_addr, mem_size);\n addr = (void *)(aligned_addr);\n\n\tRTE_LOG(DEBUG, EAL, \"Virtual area found at %p (size = 0x%zx)\\n\",\n\t\taddr, *size);\n\n\treturn addr;\n}\n\n/**\n * Get memory size configuration from /sys/devices/virtual/misc/dom0_mm\n * /memsize-mB/memsize file, and the size unit is mB.\n */\nstatic int\nget_xen_memory_size(void)\n{\n\tchar path[PATH_MAX];\n\tunsigned long mem_size = 0;\n\tstatic const char *file_name;\n\n\tfile_name = \"memsize\";\n\tsnprintf(path, sizeof(path), \"%s/%s\",\n\t\t\tsys_dir_path, file_name);\n\n\tif (eal_parse_sysfs_value(path, &mem_size) < 0)\n\t\treturn -1;\n\n\tif (mem_size == 0)\n\t\trte_exit(EXIT_FAILURE,\"XEN-DOM0:the %s/%s was not\"\n\t\t\t\" configured.\\n\",sys_dir_path, file_name);\n\tif (mem_size % 2)\n\t\trte_exit(EXIT_FAILURE,\"XEN-DOM0:the %s/%s must be\"\n\t\t\t\" even number.\\n\",sys_dir_path, file_name);\n\n\tif (mem_size > DOM0_CONFIG_MEMSIZE)\n\t\trte_exit(EXIT_FAILURE,\"XEN-DOM0:the %s/%s should not be larger\"\n\t\t\t\" than %d mB\\n\",sys_dir_path, file_name, DOM0_CONFIG_MEMSIZE);\n\n\treturn mem_size;\n}\n\n/**\n * Based on physical address to caculate MFN in Xen Dom0.\n */\nphys_addr_t\nrte_mem_phy2mch(uint32_t memseg_id, const phys_addr_t phy_addr)\n{\n\tint mfn_id;\n\tuint64_t mfn, mfn_offset;\n\tstruct rte_mem_config *mcfg = rte_eal_get_configuration()->mem_config;\n\tstruct rte_memseg *memseg = mcfg->memseg;\n\n\tmfn_id = (phy_addr - memseg[memseg_id].phys_addr) / RTE_PGSIZE_2M;\n\n\t/*the MFN is contiguous in 2M */\n\tmfn_offset = (phy_addr - memseg[memseg_id].phys_addr) %\n\t\t\t\t\tRTE_PGSIZE_2M / PAGE_SIZE;\n\tmfn = mfn_offset + memseg[memseg_id].mfn[mfn_id];\n\n\t/** return mechine address */\n\treturn (mfn * PAGE_SIZE + phy_addr % PAGE_SIZE);\n}\n\nint\nrte_xen_dom0_memory_init(void)\n{\n\tvoid *vir_addr, *vma_addr = NULL;\n\tint err, ret = 0;\n\tuint32_t i, requested, mem_size, memseg_idx, num_memseg = 0;\n\tsize_t vma_len = 0;\n\tstruct memory_info meminfo;\n\tstruct memseg_info seginfo[RTE_MAX_MEMSEG];\n\tint flags, page_size = getpagesize();\n\tstruct rte_mem_config *mcfg = rte_eal_get_configuration()->mem_config;\n\tstruct rte_memseg *memseg = mcfg->memseg;\n\tuint64_t total_mem = internal_config.memory;\n\n\tmemset(seginfo, 0, sizeof(seginfo));\n\tmemset(&meminfo, 0, sizeof(struct memory_info));\n\n\tmem_size = get_xen_memory_size();\n\trequested = (unsigned) (total_mem / 0x100000);\n\tif (requested > mem_size)\n\t\t/* if we didn't satisfy total memory requirements */\n\t\trte_exit(EXIT_FAILURE,\"Not enough memory available! Requested: %uMB,\"\n\t\t\t\t\" available: %uMB\\n\", requested, mem_size);\n\telse if (total_mem != 0)\n\t\tmem_size = requested;\n\n\t/* Check FD and open once */\n\tif (xen_fd < 0) {\n\t\txen_fd = open(DOM0_MM_DEV, O_RDWR);\n\t\tif (xen_fd < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"Can not open %s\\n\",DOM0_MM_DEV);\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\tmeminfo.size = mem_size;\n\n\t/* construct memory mangement name for Dom0 */\n\tsnprintf(meminfo.name, DOM0_NAME_MAX, \"%s-%s\",\n\t\tinternal_config.hugefile_prefix, DEFAUL_DOM0_NAME);\n\n\t/* Notify kernel driver to allocate memory */\n\tret = ioctl(xen_fd, RTE_DOM0_IOCTL_PREPARE_MEMSEG, &meminfo);\n\tif (ret < 0) {\n\t\tRTE_LOG(ERR, EAL, \"XEN DOM0:failed to get memory\\n\");\n\t\terr = -EIO;\n\t\tgoto fail;\n\t}\n\n\t/* Get number of memory segment from driver */\n\tret = ioctl(xen_fd, RTE_DOM0_IOCTL_GET_NUM_MEMSEG, &num_memseg);\n\tif (ret < 0) {\n\t\tRTE_LOG(ERR, EAL, \"XEN DOM0:failed to get memseg count.\\n\");\n\t\terr = -EIO;\n\t\tgoto fail;\n\t}\n\n\tif(num_memseg > RTE_MAX_MEMSEG){\n\t\tRTE_LOG(ERR, EAL, \"XEN DOM0: the memseg count %d is greater\"\n\t\t\t\" than max memseg %d.\\n\",num_memseg, RTE_MAX_MEMSEG);\n\t\terr = -EIO;\n\t\tgoto fail;\n\t}\n\n\t/* get all memory segements information */\n\tret = ioctl(xen_fd, RTE_DOM0_IOCTL_GET_MEMSEG_INFO, seginfo);\n\tif (ret < 0) {\n\t\tRTE_LOG(ERR, EAL, \"XEN DOM0:failed to get memseg info.\\n\");\n\t\terr = -EIO;\n\t\tgoto fail;\n\t}\n\n\t/* map all memory segments to contiguous user space */\n\tfor (memseg_idx = 0; memseg_idx < num_memseg; memseg_idx++)\n\t{\n\t\tvma_len = seginfo[memseg_idx].size;\n\n\t\t/**\n\t\t * get the biggest virtual memory area up to vma_len. If it fails,\n\t\t * vma_addr is NULL, so let the kernel provide the address.\n\t\t */\n\t\tvma_addr = xen_get_virtual_area(&vma_len, RTE_PGSIZE_2M);\n\t\tif (vma_addr == NULL) {\n\t\t\tflags = MAP_SHARED;\n\t\t\tvma_len = RTE_PGSIZE_2M;\n\t\t} else\n\t\t\tflags = MAP_SHARED | MAP_FIXED;\n\n\t\tseginfo[memseg_idx].size = vma_len;\n\t\tvir_addr = mmap(vma_addr, seginfo[memseg_idx].size,\n\t\t\tPROT_READ|PROT_WRITE, flags, xen_fd,\n\t\t\tmemseg_idx * page_size);\n\t\tif (vir_addr == MAP_FAILED) {\n\t\t\tRTE_LOG(ERR, EAL, \"XEN DOM0:Could not mmap %s\\n\",\n\t\t\t\tDOM0_MM_DEV);\n\t\t\terr = -EIO;\n\t\t\tgoto fail;\n\t\t}\n\n\t\tmemseg[memseg_idx].addr = vir_addr;\n\t\tmemseg[memseg_idx].phys_addr = page_size *\n\t\t\tseginfo[memseg_idx].pfn ;\n\t\tmemseg[memseg_idx].len = seginfo[memseg_idx].size;\n\t\tfor ( i = 0; i < seginfo[memseg_idx].size / RTE_PGSIZE_2M; i++)\n\t\t\tmemseg[memseg_idx].mfn[i] = seginfo[memseg_idx].mfn[i];\n\n\t\t/* MFNs are continuous in 2M, so assume that page size is 2M */\n\t\tmemseg[memseg_idx].hugepage_sz = RTE_PGSIZE_2M;\n\n\t\tmemseg[memseg_idx].nchannel = mcfg->nchannel;\n\t\tmemseg[memseg_idx].nrank = mcfg->nrank;\n\n\t\t/* NUMA is not suppoted in Xen Dom0, so only set socket 0*/\n\t\tmemseg[memseg_idx].socket_id = 0;\n\t}\n\n\treturn 0;\nfail:\n\tif (xen_fd > 0) {\n\t\tclose(xen_fd);\n\t\txen_fd = -1;\n\t}\n\treturn err;\n}\n\n/*\n * This creates the memory mappings in the secondary process to match that of\n * the server process. It goes through each memory segment in the DPDK runtime\n * configuration, mapping them in order to form a contiguous block in the\n * virtual memory space\n */\nint\nrte_xen_dom0_memory_attach(void)\n{\n\tconst struct rte_mem_config *mcfg;\n\tunsigned s = 0; /* s used to track the segment number */\n\tint xen_fd = -1;\n\tint ret = -1;\n\tvoid *vir_addr;\n\tchar name[DOM0_NAME_MAX] = {0};\n\tint page_size = getpagesize();\n\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\t/* Check FD and open once */\n\tif (xen_fd < 0) {\n\t\txen_fd = open(DOM0_MM_DEV, O_RDWR);\n\t\tif (xen_fd < 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"Can not open %s\\n\",DOM0_MM_DEV);\n\t\t\tgoto error;\n\t\t}\n\t}\n\n\t/* construct memory mangement name for Dom0 */\n\tsnprintf(name, DOM0_NAME_MAX, \"%s-%s\",\n\t\tinternal_config.hugefile_prefix, DEFAUL_DOM0_NAME);\n\t/* attach to memory segments of primary process */\n\tret = ioctl(xen_fd, RTE_DOM0_IOCTL_ATTACH_TO_MEMSEG, name);\n\tif (ret) {\n\t\tRTE_LOG(ERR, EAL,\"attach memory segments fail.\\n\");\n\t\tgoto error;\n\t}\n\n\t/* map all segments into memory to make sure we get the addrs */\n\tfor (s = 0; s < RTE_MAX_MEMSEG; ++s) {\n\n\t\t/*\n\t\t * the first memory segment with len==0 is the one that\n\t\t * follows the last valid segment.\n\t\t */\n\t\tif (mcfg->memseg[s].len == 0)\n\t\t\tbreak;\n\n\t\tvir_addr = mmap(mcfg->memseg[s].addr, mcfg->memseg[s].len,\n\t\t\t\tPROT_READ|PROT_WRITE, MAP_SHARED|MAP_FIXED, xen_fd,\n\t\t\t\ts * page_size);\n\t\tif (vir_addr == MAP_FAILED) {\n\t\t\tRTE_LOG(ERR, EAL, \"Could not mmap %llu bytes \"\n\t\t\t\t\"in %s to requested address [%p]\\n\",\n\t\t\t\t(unsigned long long)mcfg->memseg[s].len, DOM0_MM_DEV,\n\t\t\t\tmcfg->memseg[s].addr);\n\t\t\tgoto error;\n\t\t}\n\t}\n\treturn 0;\n\nerror:\n\tif (xen_fd >= 0) {\n\t\tclose(xen_fd);\n\t\txen_fd = -1;\n\t}\n\treturn -1;\n}\n" }, { "path": "lib/librte_eal/linuxapp/eal/include/exec-env/rte_dom0_common.h", "content": "/*-\n * This file is provided under a dual BSD/LGPLv2 license. When using or\n * redistributing this file, you may do so under either license.\n *\n * GNU LESSER GENERAL PUBLIC LICENSE\n *\n * Copyright(c) 2007-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2.1 of the GNU Lesser General Public License\n * as published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * Lesser General Public License for more details.\n *\n * You should have received a copy of the GNU Lesser General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n *\n * Contact Information:\n * Intel Corporation\n *\n *\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n */\n\n#ifndef _RTE_DOM0_COMMON_H_\n#define _RTE_DOM0_COMMON_H_\n\n#ifdef __KERNEL__\n#include \n#endif\n\n#define DOM0_NAME_MAX 256\n#define DOM0_MM_DEV \"/dev/dom0_mm\"\n\n#define DOM0_CONTIG_NUM_ORDER 9 /**< order of 2M */\n#define DOM0_NUM_MEMSEG 512 /**< Maximum nb. of memory segment. */\n#define DOM0_MEMBLOCK_SIZE 0x200000 /**< size of memory block(2M). */\n#define DOM0_CONFIG_MEMSIZE 4096 /**< Maximum config memory size(4G). */\n#define DOM0_NUM_MEMBLOCK (DOM0_CONFIG_MEMSIZE / 2) /**< Maximum nb. of 2M memory block. */\n\n#define RTE_DOM0_IOCTL_PREPARE_MEMSEG _IOWR(0, 1 , struct memory_info)\n#define RTE_DOM0_IOCTL_ATTACH_TO_MEMSEG _IOWR(0, 2 , char *)\n#define RTE_DOM0_IOCTL_GET_NUM_MEMSEG _IOWR(0, 3, int)\n#define RTE_DOM0_IOCTL_GET_MEMSEG_INFO _IOWR(0, 4, void *)\n\n/**\n * A structure used to store memory information.\n */\nstruct memory_info {\n\tchar name[DOM0_NAME_MAX];\n\tuint64_t size;\n};\n\n/**\n * A structure used to store memory segment information.\n */\nstruct memseg_info {\n\tuint32_t idx;\n\tuint64_t pfn;\n\tuint64_t size;\n\tuint64_t mfn[DOM0_NUM_MEMBLOCK];\n};\n\n/**\n * A structure used to store memory block information.\n */\nstruct memblock_info {\n\tuint8_t exchange_flag;\n\tuint8_t used;\n\tuint64_t vir_addr;\n\tuint64_t pfn;\n\tuint64_t mfn;\n};\n#endif /* _RTE_DOM0_COMMON_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/eal/include/exec-env/rte_interrupts.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_INTERRUPTS_H_\n#error \"don't include this file directly, please include generic \"\n#endif\n\n#ifndef _RTE_LINUXAPP_INTERRUPTS_H_\n#define _RTE_LINUXAPP_INTERRUPTS_H_\n\n#define RTE_MAX_RXTX_INTR_VEC_ID 32\n\nenum rte_intr_handle_type {\n\tRTE_INTR_HANDLE_UNKNOWN = 0,\n\tRTE_INTR_HANDLE_UIO, /**< uio device handle */\n\tRTE_INTR_HANDLE_UIO_INTX, /**< uio generic handle */\n\tRTE_INTR_HANDLE_VFIO_LEGACY, /**< vfio device handle (legacy) */\n\tRTE_INTR_HANDLE_VFIO_MSI, /**< vfio device handle (MSI) */\n\tRTE_INTR_HANDLE_VFIO_MSIX, /**< vfio device handle (MSIX) */\n\tRTE_INTR_HANDLE_ALARM, /**< alarm handle */\n\tRTE_INTR_HANDLE_MAX\n};\n\n#define RTE_INTR_EVENT_ADD 1UL\n#define RTE_INTR_EVENT_DEL 2UL\n\ntypedef void (*rte_intr_event_cb_t)(int fd, void *arg);\n\nstruct rte_epoll_data {\n\tuint32_t event; /**< event type */\n\tvoid *data; /**< User data */\n\trte_intr_event_cb_t cb_fun; /**< IN: callback fun */\n\tvoid *cb_arg;\t /**< IN: callback arg */\n};\n\nenum {\n\tRTE_EPOLL_INVALID = 0,\n\tRTE_EPOLL_VALID,\n\tRTE_EPOLL_EXEC,\n};\n\n/** interrupt epoll event obj, taken by epoll_event.ptr */\nstruct rte_epoll_event {\n\tvolatile uint32_t status; /**< OUT: event status */\n\tint fd; /**< OUT: event fd */\n\tint epfd; /**< OUT: epoll instance the ev associated with */\n\tstruct rte_epoll_data epdata;\n};\n\n/** Handle for interrupts. */\nstruct rte_intr_handle {\n\tunion {\n\t\tint vfio_dev_fd; /**< VFIO device file descriptor */\n\t\tint uio_cfg_fd; /**< UIO config file descriptor\n\t\t\t\t\tfor uio_pci_generic */\n\t};\n\tint fd;\t /**< interrupt event file descriptor */\n\tenum rte_intr_handle_type type; /**< handle type */\n#ifdef RTE_NEXT_ABI\n\tuint32_t max_intr; /**< max interrupt requested */\n\tuint32_t nb_efd; /**< number of available efd(event fd) */\n\tint efds[RTE_MAX_RXTX_INTR_VEC_ID]; /**< intr vectors/efds mapping */\n\tstruct rte_epoll_event elist[RTE_MAX_RXTX_INTR_VEC_ID];\n\t\t\t\t /**< intr vector epoll event */\n\tint *intr_vec; /**< intr vector number array */\n#endif\n};\n\n#define RTE_EPOLL_PER_THREAD -1 /**< to hint using per thread epfd */\n\n/**\n * It waits for events on the epoll instance.\n *\n * @param epfd\n * Epoll instance fd on which the caller wait for events.\n * @param events\n * Memory area contains the events that will be available for the caller.\n * @param maxevents\n * Up to maxevents are returned, must greater than zero.\n * @param timeout\n * Specifying a timeout of -1 causes a block indefinitely.\n * Specifying a timeout equal to zero cause to return immediately.\n * @return\n * - On success, returns the number of available event.\n * - On failure, a negative value.\n */\nint\nrte_epoll_wait(int epfd, struct rte_epoll_event *events,\n\t int maxevents, int timeout);\n\n/**\n * It performs control operations on epoll instance referred by the epfd.\n * It requests that the operation op be performed for the target fd.\n *\n * @param epfd\n * Epoll instance fd on which the caller perform control operations.\n * @param op\n * The operation be performed for the target fd.\n * @param fd\n * The target fd on which the control ops perform.\n * @param event\n * Describes the object linked to the fd.\n * Note: The caller must take care the object deletion after CTL_DEL.\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nint\nrte_epoll_ctl(int epfd, int op, int fd,\n\t struct rte_epoll_event *event);\n\n/**\n * The function returns the per thread epoll instance.\n *\n * @return\n * epfd the epoll instance referred to.\n */\nint\nrte_intr_tls_epfd(void);\n\n/**\n * @param intr_handle\n * Pointer to the interrupt handle.\n * @param epfd\n * Epoll instance fd which the intr vector associated to.\n * @param op\n * The operation be performed for the vector.\n * Operation type of {ADD, DEL}.\n * @param vec\n * RX intr vector number added to the epoll instance wait list.\n * @param data\n * User raw data.\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nint\nrte_intr_rx_ctl(struct rte_intr_handle *intr_handle,\n\t\tint epfd, int op, unsigned int vec, void *data);\n\n/**\n * It enables the packet I/O interrupt event if it's necessary.\n * It creates event fd for each interrupt vector when MSIX is used,\n * otherwise it multiplexes a single event fd.\n *\n * @param intr_handle\n * Pointer to the interrupt handle.\n * @param nb_vec\n * Number of interrupt vector trying to enable.\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nint\nrte_intr_efd_enable(struct rte_intr_handle *intr_handle, uint32_t nb_efd);\n\n/**\n * It disables the packet I/O interrupt event.\n * It deletes registered eventfds and closes the open fds.\n *\n * @param intr_handle\n * Pointer to the interrupt handle.\n */\nvoid\nrte_intr_efd_disable(struct rte_intr_handle *intr_handle);\n\n/**\n * The packet I/O interrupt on datapath is enabled or not.\n *\n * @param intr_handle\n * Pointer to the interrupt handle.\n */\nint\nrte_intr_dp_is_en(struct rte_intr_handle *intr_handle);\n\n/**\n * The interrupt handle instance allows other causes or not.\n * Other causes stand for any none packet I/O interrupts.\n *\n * @param intr_handle\n * Pointer to the interrupt handle.\n */\nint\nrte_intr_allow_others(struct rte_intr_handle *intr_handle);\n\n#endif /* _RTE_LINUXAPP_INTERRUPTS_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/eal/include/exec-env/rte_kni_common.h", "content": "/*-\n * This file is provided under a dual BSD/LGPLv2 license. When using or\n * redistributing this file, you may do so under either license.\n *\n * GNU LESSER GENERAL PUBLIC LICENSE\n *\n * Copyright(c) 2007-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2.1 of the GNU Lesser General Public License\n * as published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * Lesser General Public License for more details.\n *\n * You should have received a copy of the GNU Lesser General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n *\n * Contact Information:\n * Intel Corporation\n *\n *\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n */\n\n#ifndef _RTE_KNI_COMMON_H_\n#define _RTE_KNI_COMMON_H_\n\n#ifdef __KERNEL__\n#include \n#endif\n\n/**\n * KNI name is part of memzone name.\n */\n#define RTE_KNI_NAMESIZE 32\n\n#ifndef RTE_CACHE_LINE_SIZE\n#define RTE_CACHE_LINE_SIZE 64 /**< Cache line size. */\n#endif\n\n/*\n * Request id.\n */\nenum rte_kni_req_id {\n\tRTE_KNI_REQ_UNKNOWN = 0,\n\tRTE_KNI_REQ_CHANGE_MTU,\n\tRTE_KNI_REQ_CFG_NETWORK_IF,\n\tRTE_KNI_REQ_MAX,\n};\n\n/*\n * Structure for KNI request.\n */\nstruct rte_kni_request {\n\tuint32_t req_id; /**< Request id */\n\tunion {\n\t\tuint32_t new_mtu; /**< New MTU */\n\t\tuint8_t if_up; /**< 1: interface up, 0: interface down */\n\t};\n\tint32_t result; /**< Result for processing request */\n} __attribute__((__packed__));\n\n/*\n * Fifo struct mapped in a shared memory. It describes a circular buffer FIFO\n * Write and read should wrap around. Fifo is empty when write == read\n * Writing should never overwrite the read position\n */\nstruct rte_kni_fifo {\n\tvolatile unsigned write; /**< Next position to be written*/\n\tvolatile unsigned read; /**< Next position to be read */\n\tunsigned len; /**< Circular buffer length */\n\tunsigned elem_size; /**< Pointer size - for 32/64 bit OS */\n\tvoid * volatile buffer[0]; /**< The buffer contains mbuf pointers */\n};\n\n/*\n * The kernel image of the rte_mbuf struct, with only the relevant fields.\n * Padding is necessary to assure the offsets of these fields\n */\nstruct rte_kni_mbuf {\n\tvoid *buf_addr __attribute__((__aligned__(RTE_CACHE_LINE_SIZE)));\n\tchar pad0[10];\n\tuint16_t data_off; /**< Start address of data in segment buffer. */\n\tchar pad1[4];\n\tuint64_t ol_flags; /**< Offload features. */\n#ifdef RTE_NEXT_ABI\n\tchar pad2[4];\n\tuint32_t pkt_len; /**< Total pkt len: sum of all segment data_len. */\n\tuint16_t data_len; /**< Amount of data in segment buffer. */\n#else\n\tchar pad2[2];\n\tuint16_t data_len; /**< Amount of data in segment buffer. */\n\tuint32_t pkt_len; /**< Total pkt len: sum of all segment data_len. */\n#endif\n\n\t/* fields on second cache line */\n\tchar pad3[8] __attribute__((__aligned__(RTE_CACHE_LINE_SIZE)));\n\tvoid *pool;\n\tvoid *next;\n};\n\n/*\n * Struct used to create a KNI device. Passed to the kernel in IOCTL call\n */\n\nstruct rte_kni_device_info {\n\tchar name[RTE_KNI_NAMESIZE]; /**< Network device name for KNI */\n\n\tphys_addr_t tx_phys;\n\tphys_addr_t rx_phys;\n\tphys_addr_t alloc_phys;\n\tphys_addr_t free_phys;\n\n\t/* Used by Ethtool */\n\tphys_addr_t req_phys;\n\tphys_addr_t resp_phys;\n\tphys_addr_t sync_phys;\n\tvoid * sync_va;\n\n\t/* mbuf mempool */\n\tvoid * mbuf_va;\n\tphys_addr_t mbuf_phys;\n\n\t/* PCI info */\n\tuint16_t vendor_id; /**< Vendor ID or PCI_ANY_ID. */\n\tuint16_t device_id; /**< Device ID or PCI_ANY_ID. */\n\tuint8_t bus; /**< Device bus */\n\tuint8_t devid; /**< Device ID */\n\tuint8_t function; /**< Device function. */\n\n\tuint16_t group_id; /**< Group ID */\n\tuint32_t core_id; /**< core ID to bind for kernel thread */\n\n\tuint8_t force_bind : 1; /**< Flag for kernel thread binding */\n\n\t/* mbuf size */\n\tunsigned mbuf_size;\n};\n\n#define KNI_DEVICE \"kni\"\n\n#define RTE_KNI_IOCTL_TEST _IOWR(0, 1, int)\n#define RTE_KNI_IOCTL_CREATE _IOWR(0, 2, struct rte_kni_device_info)\n#define RTE_KNI_IOCTL_RELEASE _IOWR(0, 3, struct rte_kni_device_info)\n\n#endif /* _RTE_KNI_COMMON_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/igb_uio/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# module name and path\n#\nMODULE = igb_uio\nMODULE_PATH = drivers/net/igb_uio\n\n#\n# CFLAGS\n#\nMODULE_CFLAGS += -I$(SRCDIR) --param max-inline-insns-single=100\nMODULE_CFLAGS += -I$(RTE_OUTPUT)/include\nMODULE_CFLAGS += -Winline -Wall -Werror\nMODULE_CFLAGS += -include $(RTE_OUTPUT)/include/rte_config.h\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-y := igb_uio.c\n\ninclude $(RTE_SDK)/mk/rte.module.mk\n" }, { "path": "lib/librte_eal/linuxapp/igb_uio/compat.h", "content": "/*\n * Minimal wrappers to allow compiling igb_uio on older kernels.\n */\n\n#ifndef RHEL_RELEASE_VERSION\n#define RHEL_RELEASE_VERSION(a, b) (((a) << 8) + (b))\n#endif\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)\n#define pci_cfg_access_lock pci_block_user_cfg_access\n#define pci_cfg_access_unlock pci_unblock_user_cfg_access\n#endif\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)\n#define HAVE_PTE_MASK_PAGE_IOMAP\n#endif\n\n#ifndef PCI_MSIX_ENTRY_SIZE\n#define PCI_MSIX_ENTRY_SIZE 16\n#define PCI_MSIX_ENTRY_LOWER_ADDR 0\n#define PCI_MSIX_ENTRY_UPPER_ADDR 4\n#define PCI_MSIX_ENTRY_DATA 8\n#define PCI_MSIX_ENTRY_VECTOR_CTRL 12\n#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1\n#endif\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34) && \\\n\t(!(defined(RHEL_RELEASE_CODE) && \\\n\t RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5, 9)))\n\nstatic int pci_num_vf(struct pci_dev *dev)\n{\n\tstruct iov {\n\t\tint pos;\n\t\tint nres;\n\t\tu32 cap;\n\t\tu16 ctrl;\n\t\tu16 total;\n\t\tu16 initial;\n\t\tu16 nr_virtfn;\n\t} *iov = (struct iov *)dev->sriov;\n\n\tif (!dev->is_physfn)\n\t\treturn 0;\n\n\treturn iov->nr_virtfn;\n}\n\n#endif /* < 2.6.34 */\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39) && \\\n\t(!(defined(RHEL_RELEASE_CODE) && \\\n\t RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4)))\n\n#define kstrtoul strict_strtoul\n\n#endif /* < 2.6.39 */\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0) && \\\n\t(!(defined(RHEL_RELEASE_CODE) && \\\n\t RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 3)))\n\n/* Check if INTX works to control irq's.\n * Set's INTX_DISABLE flag and reads it back\n */\nstatic bool pci_intx_mask_supported(struct pci_dev *pdev)\n{\n\tbool mask_supported = false;\n\tuint16_t orig, new;\n\n\tpci_block_user_cfg_access(pdev);\n\tpci_read_config_word(pdev, PCI_COMMAND, &orig);\n\tpci_write_config_word(pdev, PCI_COMMAND,\n\t\t\t orig ^ PCI_COMMAND_INTX_DISABLE);\n\tpci_read_config_word(pdev, PCI_COMMAND, &new);\n\n\tif ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {\n\t\tdev_err(&pdev->dev, \"Command register changed from \"\n\t\t\t\"0x%x to 0x%x: driver or hardware bug?\\n\", orig, new);\n\t} else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {\n\t\tmask_supported = true;\n\t\tpci_write_config_word(pdev, PCI_COMMAND, orig);\n\t}\n\tpci_unblock_user_cfg_access(pdev);\n\n\treturn mask_supported;\n}\n\nstatic bool pci_check_and_mask_intx(struct pci_dev *pdev)\n{\n\tbool pending;\n\tuint32_t status;\n\n\tpci_block_user_cfg_access(pdev);\n\tpci_read_config_dword(pdev, PCI_COMMAND, &status);\n\n\t/* interrupt is not ours, goes to out */\n\tpending = (((status >> 16) & PCI_STATUS_INTERRUPT) != 0);\n\tif (pending) {\n\t\tuint16_t old, new;\n\n\t\told = status;\n\t\tif (status != 0)\n\t\t\tnew = old & (~PCI_COMMAND_INTX_DISABLE);\n\t\telse\n\t\t\tnew = old | PCI_COMMAND_INTX_DISABLE;\n\n\t\tif (old != new)\n\t\t\tpci_write_config_word(pdev, PCI_COMMAND, new);\n\t}\n\tpci_unblock_user_cfg_access(pdev);\n\n\treturn pending;\n}\n\n#endif /* < 3.3.0 */\n" }, { "path": "lib/librte_eal/linuxapp/igb_uio/igb_uio.c", "content": "/*-\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n */\n\n#define pr_fmt(fmt) KBUILD_MODNAME \": \" fmt\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#ifdef CONFIG_XEN_DOM0\n#include \n#endif\n#include \n\n#include \"compat.h\"\n\n#ifdef RTE_PCI_CONFIG\n#define PCI_SYS_FILE_BUF_SIZE 10\n#define PCI_DEV_CAP_REG 0xA4\n#define PCI_DEV_CTRL_REG 0xA8\n#define PCI_DEV_CAP_EXT_TAG_MASK 0x20\n#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8\n#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)\n#endif\n\n/**\n * A structure describing the private information for a uio device.\n */\nstruct rte_uio_pci_dev {\n\tstruct uio_info info;\n\tstruct pci_dev *pdev;\n\tenum rte_intr_mode mode;\n};\n\nstatic char *intr_mode = NULL;\nstatic enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;\n\nstatic inline struct rte_uio_pci_dev *\nigbuio_get_uio_pci_dev(struct uio_info *info)\n{\n\treturn container_of(info, struct rte_uio_pci_dev, info);\n}\n\n/* sriov sysfs */\nstatic ssize_t\nshow_max_vfs(struct device *dev, struct device_attribute *attr,\n\t char *buf)\n{\n\treturn snprintf(buf, 10, \"%u\\n\",\n\t\t\tpci_num_vf(container_of(dev, struct pci_dev, dev)));\n}\n\nstatic ssize_t\nstore_max_vfs(struct device *dev, struct device_attribute *attr,\n\t const char *buf, size_t count)\n{\n\tint err = 0;\n\tunsigned long max_vfs;\n\tstruct pci_dev *pdev = container_of(dev, struct pci_dev, dev);\n\n\tif (0 != kstrtoul(buf, 0, &max_vfs))\n\t\treturn -EINVAL;\n\n\tif (0 == max_vfs)\n\t\tpci_disable_sriov(pdev);\n\telse if (0 == pci_num_vf(pdev))\n\t\terr = pci_enable_sriov(pdev, max_vfs);\n\telse /* do nothing if change max_vfs number */\n\t\terr = -EINVAL;\n\n\treturn err ? err : count;\n}\n\n#ifdef RTE_PCI_CONFIG\nstatic ssize_t\nshow_extended_tag(struct device *dev, struct device_attribute *attr, char *buf)\n{\n\tstruct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);\n\tuint32_t val = 0;\n\n\tpci_read_config_dword(pci_dev, PCI_DEV_CAP_REG, &val);\n\tif (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */\n\t\treturn snprintf(buf, PCI_SYS_FILE_BUF_SIZE, \"%s\\n\", \"invalid\");\n\n\tval = 0;\n\tpci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,\n\t\t\t\t\tPCI_DEV_CTRL_REG, &val);\n\n\treturn snprintf(buf, PCI_SYS_FILE_BUF_SIZE, \"%s\\n\",\n\t\t(val & PCI_DEV_CTRL_EXT_TAG_MASK) ? \"on\" : \"off\");\n}\n\nstatic ssize_t\nstore_extended_tag(struct device *dev,\n\t\t struct device_attribute *attr,\n\t\t const char *buf,\n\t\t size_t count)\n{\n\tstruct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);\n\tuint32_t val = 0, enable;\n\n\tif (strncmp(buf, \"on\", 2) == 0)\n\t\tenable = 1;\n\telse if (strncmp(buf, \"off\", 3) == 0)\n\t\tenable = 0;\n\telse\n\t\treturn -EINVAL;\n\n\tpci_cfg_access_lock(pci_dev);\n\tpci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,\n\t\t\t\t\tPCI_DEV_CAP_REG, &val);\n\tif (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */\n\t\tpci_cfg_access_unlock(pci_dev);\n\t\treturn -EPERM;\n\t}\n\n\tval = 0;\n\tpci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,\n\t\t\t\t\tPCI_DEV_CTRL_REG, &val);\n\tif (enable)\n\t\tval |= PCI_DEV_CTRL_EXT_TAG_MASK;\n\telse\n\t\tval &= ~PCI_DEV_CTRL_EXT_TAG_MASK;\n\tpci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,\n\t\t\t\t\tPCI_DEV_CTRL_REG, val);\n\tpci_cfg_access_unlock(pci_dev);\n\n\treturn count;\n}\n\nstatic ssize_t\nshow_max_read_request_size(struct device *dev,\n\t\t\t struct device_attribute *attr,\n\t\t\t char *buf)\n{\n\tstruct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);\n\tint val = pcie_get_readrq(pci_dev);\n\n\treturn snprintf(buf, PCI_SYS_FILE_BUF_SIZE, \"%d\\n\", val);\n}\n\nstatic ssize_t\nstore_max_read_request_size(struct device *dev,\n\t\t\t struct device_attribute *attr,\n\t\t\t const char *buf,\n\t\t\t size_t count)\n{\n\tstruct pci_dev *pci_dev = container_of(dev, struct pci_dev, dev);\n\tunsigned long size = 0;\n\tint ret;\n\n\tif (0 != kstrtoul(buf, 0, &size))\n\t\treturn -EINVAL;\n\n\tret = pcie_set_readrq(pci_dev, (int)size);\n\tif (ret < 0)\n\t\treturn ret;\n\n\treturn count;\n}\n#endif\n\nstatic DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);\n#ifdef RTE_PCI_CONFIG\nstatic DEVICE_ATTR(extended_tag, S_IRUGO | S_IWUSR, show_extended_tag,\n\tstore_extended_tag);\nstatic DEVICE_ATTR(max_read_request_size, S_IRUGO | S_IWUSR,\n\tshow_max_read_request_size, store_max_read_request_size);\n#endif\n\nstatic struct attribute *dev_attrs[] = {\n\t&dev_attr_max_vfs.attr,\n#ifdef RTE_PCI_CONFIG\n\t&dev_attr_extended_tag.attr,\n\t&dev_attr_max_read_request_size.attr,\n#endif\n\tNULL,\n};\n\nstatic const struct attribute_group dev_attr_grp = {\n\t.attrs = dev_attrs,\n};\n/*\n * It masks the msix on/off of generating MSI-X messages.\n */\nstatic void\nigbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)\n{\n\tu32 mask_bits = desc->masked;\n\tunsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +\n\t\t\t\t\t\tPCI_MSIX_ENTRY_VECTOR_CTRL;\n\n\tif (state != 0)\n\t\tmask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;\n\telse\n\t\tmask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;\n\n\tif (mask_bits != desc->masked) {\n\t\twritel(mask_bits, desc->mask_base + offset);\n\t\treadl(desc->mask_base);\n\t\tdesc->masked = mask_bits;\n\t}\n}\n\n/**\n * This is the irqcontrol callback to be registered to uio_info.\n * It can be used to disable/enable interrupt from user space processes.\n *\n * @param info\n * pointer to uio_info.\n * @param irq_state\n * state value. 1 to enable interrupt, 0 to disable interrupt.\n *\n * @return\n * - On success, 0.\n * - On failure, a negative value.\n */\nstatic int\nigbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)\n{\n\tstruct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);\n\tstruct pci_dev *pdev = udev->pdev;\n\n\tpci_cfg_access_lock(pdev);\n\tif (udev->mode == RTE_INTR_MODE_LEGACY)\n\t\tpci_intx(pdev, !!irq_state);\n\n\telse if (udev->mode == RTE_INTR_MODE_MSIX) {\n\t\tstruct msi_desc *desc;\n\n\t\tlist_for_each_entry(desc, &pdev->msi_list, list)\n\t\t\tigbuio_msix_mask_irq(desc, irq_state);\n\t}\n\tpci_cfg_access_unlock(pdev);\n\n\treturn 0;\n}\n\n/**\n * This is interrupt handler which will check if the interrupt is for the right device.\n * If yes, disable it here and will be enable later.\n */\nstatic irqreturn_t\nigbuio_pci_irqhandler(int irq, struct uio_info *info)\n{\n\tstruct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);\n\n\t/* Legacy mode need to mask in hardware */\n\tif (udev->mode == RTE_INTR_MODE_LEGACY &&\n\t !pci_check_and_mask_intx(udev->pdev))\n\t\treturn IRQ_NONE;\n\n\t/* Message signal mode, no share IRQ and automasked */\n\treturn IRQ_HANDLED;\n}\n\n#ifdef CONFIG_XEN_DOM0\nstatic int\nigbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)\n{\n\tint idx;\n\n\tidx = (int)vma->vm_pgoff;\n\tvma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);\n#ifdef HAVE_PTE_MASK_PAGE_IOMAP\n\tvma->vm_page_prot.pgprot |= _PAGE_IOMAP;\n#endif\n\n\treturn remap_pfn_range(vma,\n\t\t\tvma->vm_start,\n\t\t\tinfo->mem[idx].addr >> PAGE_SHIFT,\n\t\t\tvma->vm_end - vma->vm_start,\n\t\t\tvma->vm_page_prot);\n}\n\n/**\n * This is uio device mmap method which will use igbuio mmap for Xen\n * Dom0 environment.\n */\nstatic int\nigbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)\n{\n\tint idx;\n\n\tif (vma->vm_pgoff >= MAX_UIO_MAPS)\n\t\treturn -EINVAL;\n\n\tif (info->mem[vma->vm_pgoff].size == 0)\n\t\treturn -EINVAL;\n\n\tidx = (int)vma->vm_pgoff;\n\tswitch (info->mem[idx].memtype) {\n\tcase UIO_MEM_PHYS:\n\t\treturn igbuio_dom0_mmap_phys(info, vma);\n\tcase UIO_MEM_LOGICAL:\n\tcase UIO_MEM_VIRTUAL:\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n}\n#endif\n\n/* Remap pci resources described by bar #pci_bar in uio resource n. */\nstatic int\nigbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,\n\t\t int n, int pci_bar, const char *name)\n{\n\tunsigned long addr, len;\n\tvoid *internal_addr;\n\n\tif (sizeof(info->mem) / sizeof(info->mem[0]) <= n)\n\t\treturn -EINVAL;\n\n\taddr = pci_resource_start(dev, pci_bar);\n\tlen = pci_resource_len(dev, pci_bar);\n\tif (addr == 0 || len == 0)\n\t\treturn -1;\n\tinternal_addr = ioremap(addr, len);\n\tif (internal_addr == NULL)\n\t\treturn -1;\n\tinfo->mem[n].name = name;\n\tinfo->mem[n].addr = addr;\n\tinfo->mem[n].internal_addr = internal_addr;\n\tinfo->mem[n].size = len;\n\tinfo->mem[n].memtype = UIO_MEM_PHYS;\n\treturn 0;\n}\n\n/* Get pci port io resources described by bar #pci_bar in uio resource n. */\nstatic int\nigbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,\n\t\tint n, int pci_bar, const char *name)\n{\n\tunsigned long addr, len;\n\n\tif (sizeof(info->port) / sizeof(info->port[0]) <= n)\n\t\treturn -EINVAL;\n\n\taddr = pci_resource_start(dev, pci_bar);\n\tlen = pci_resource_len(dev, pci_bar);\n\tif (addr == 0 || len == 0)\n\t\treturn -EINVAL;\n\n\tinfo->port[n].name = name;\n\tinfo->port[n].start = addr;\n\tinfo->port[n].size = len;\n\tinfo->port[n].porttype = UIO_PORT_X86;\n\n\treturn 0;\n}\n\n/* Unmap previously ioremap'd resources */\nstatic void\nigbuio_pci_release_iomem(struct uio_info *info)\n{\n\tint i;\n\n\tfor (i = 0; i < MAX_UIO_MAPS; i++) {\n\t\tif (info->mem[i].internal_addr)\n\t\t\tiounmap(info->mem[i].internal_addr);\n\t}\n}\n\nstatic int\nigbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)\n{\n\tint i, iom, iop, ret;\n\tunsigned long flags;\n\tstatic const char *bar_names[PCI_STD_RESOURCE_END + 1] = {\n\t\t\"BAR0\",\n\t\t\"BAR1\",\n\t\t\"BAR2\",\n\t\t\"BAR3\",\n\t\t\"BAR4\",\n\t\t\"BAR5\",\n\t};\n\n\tiom = 0;\n\tiop = 0;\n\n\tfor (i = 0; i != sizeof(bar_names) / sizeof(bar_names[0]); i++) {\n\t\tif (pci_resource_len(dev, i) != 0 &&\n\t\t\t\tpci_resource_start(dev, i) != 0) {\n\t\t\tflags = pci_resource_flags(dev, i);\n\t\t\tif (flags & IORESOURCE_MEM) {\n\t\t\t\tret = igbuio_pci_setup_iomem(dev, info, iom,\n\t\t\t\t\t\t\t i, bar_names[i]);\n\t\t\t\tif (ret != 0)\n\t\t\t\t\treturn ret;\n\t\t\t\tiom++;\n\t\t\t} else if (flags & IORESOURCE_IO) {\n\t\t\t\tret = igbuio_pci_setup_ioport(dev, info, iop,\n\t\t\t\t\t\t\t i, bar_names[i]);\n\t\t\t\tif (ret != 0)\n\t\t\t\t\treturn ret;\n\t\t\t\tiop++;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn (iom != 0) ? ret : -ENOENT;\n}\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)\nstatic int __devinit\n#else\nstatic int\n#endif\nigbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)\n{\n\tstruct rte_uio_pci_dev *udev;\n\tstruct msix_entry msix_entry;\n\tint err;\n\n\tudev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);\n\tif (!udev)\n\t\treturn -ENOMEM;\n\n\t/*\n\t * enable device: ask low-level code to enable I/O and\n\t * memory\n\t */\n\terr = pci_enable_device(dev);\n\tif (err != 0) {\n\t\tdev_err(&dev->dev, \"Cannot enable PCI device\\n\");\n\t\tgoto fail_free;\n\t}\n\n\t/*\n\t * reserve device's PCI memory regions for use by this\n\t * module\n\t */\n\terr = pci_request_regions(dev, \"igb_uio\");\n\tif (err != 0) {\n\t\tdev_err(&dev->dev, \"Cannot request regions\\n\");\n\t\tgoto fail_disable;\n\t}\n\n\t/* enable bus mastering on the device */\n\tpci_set_master(dev);\n\n\t/* remap IO memory */\n\terr = igbuio_setup_bars(dev, &udev->info);\n\tif (err != 0)\n\t\tgoto fail_release_iomem;\n\n\t/* set 64-bit DMA mask */\n\terr = pci_set_dma_mask(dev, DMA_BIT_MASK(64));\n\tif (err != 0) {\n\t\tdev_err(&dev->dev, \"Cannot set DMA mask\\n\");\n\t\tgoto fail_release_iomem;\n\t}\n\n\terr = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));\n\tif (err != 0) {\n\t\tdev_err(&dev->dev, \"Cannot set consistent DMA mask\\n\");\n\t\tgoto fail_release_iomem;\n\t}\n\n\t/* fill uio infos */\n\tudev->info.name = \"igb_uio\";\n\tudev->info.version = \"0.1\";\n\tudev->info.handler = igbuio_pci_irqhandler;\n\tudev->info.irqcontrol = igbuio_pci_irqcontrol;\n#ifdef CONFIG_XEN_DOM0\n\t/* check if the driver run on Xen Dom0 */\n\tif (xen_initial_domain())\n\t\tudev->info.mmap = igbuio_dom0_pci_mmap;\n#endif\n\tudev->info.priv = udev;\n\tudev->pdev = dev;\n\n\tswitch (igbuio_intr_mode_preferred) {\n\tcase RTE_INTR_MODE_MSIX:\n\t\t/* Only 1 msi-x vector needed */\n\t\tmsix_entry.entry = 0;\n\t\tif (pci_enable_msix(dev, &msix_entry, 1) == 0) {\n\t\t\tdev_dbg(&dev->dev, \"using MSI-X\");\n\t\t\tudev->info.irq = msix_entry.vector;\n\t\t\tudev->mode = RTE_INTR_MODE_MSIX;\n\t\t\tbreak;\n\t\t}\n\t\t/* fall back to INTX */\n\tcase RTE_INTR_MODE_LEGACY:\n\t\tif (pci_intx_mask_supported(dev)) {\n\t\t\tdev_dbg(&dev->dev, \"using INTX\");\n\t\t\tudev->info.irq_flags = IRQF_SHARED;\n\t\t\tudev->info.irq = dev->irq;\n\t\t\tudev->mode = RTE_INTR_MODE_LEGACY;\n\t\t\tbreak;\n\t\t}\n\t\tdev_notice(&dev->dev, \"PCI INTX mask not supported\\n\");\n\t\t/* fall back to no IRQ */\n\tcase RTE_INTR_MODE_NONE:\n\t\tudev->mode = RTE_INTR_MODE_NONE;\n\t\tudev->info.irq = 0;\n\t\tbreak;\n\n\tdefault:\n\t\tdev_err(&dev->dev, \"invalid IRQ mode %u\",\n\t\t\tigbuio_intr_mode_preferred);\n\t\terr = -EINVAL;\n\t\tgoto fail_release_iomem;\n\t}\n\n\terr = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);\n\tif (err != 0)\n\t\tgoto fail_release_iomem;\n\n\t/* register uio driver */\n\terr = uio_register_device(&dev->dev, &udev->info);\n\tif (err != 0)\n\t\tgoto fail_remove_group;\n\n\tpci_set_drvdata(dev, udev);\n\n\tdev_info(&dev->dev, \"uio device registered with irq %lx\\n\",\n\t\t udev->info.irq);\n\n\treturn 0;\n\nfail_remove_group:\n\tsysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);\nfail_release_iomem:\n\tigbuio_pci_release_iomem(&udev->info);\n\tif (udev->mode == RTE_INTR_MODE_MSIX)\n\t\tpci_disable_msix(udev->pdev);\n\tpci_release_regions(dev);\nfail_disable:\n\tpci_disable_device(dev);\nfail_free:\n\tkfree(udev);\n\n\treturn err;\n}\n\nstatic void\nigbuio_pci_remove(struct pci_dev *dev)\n{\n\tstruct uio_info *info = pci_get_drvdata(dev);\n\tstruct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);\n\n\tif (info->priv == NULL) {\n\t\tpr_notice(\"Not igbuio device\\n\");\n\t\treturn;\n\t}\n\n\tsysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);\n\tuio_unregister_device(info);\n\tigbuio_pci_release_iomem(info);\n\tif (udev->mode == RTE_INTR_MODE_MSIX)\n\t\tpci_disable_msix(dev);\n\tpci_release_regions(dev);\n\tpci_disable_device(dev);\n\tpci_set_drvdata(dev, NULL);\n\tkfree(info);\n}\n\nstatic int\nigbuio_config_intr_mode(char *intr_str)\n{\n\tif (!intr_str) {\n\t\tpr_info(\"Use MSIX interrupt by default\\n\");\n\t\treturn 0;\n\t}\n\n\tif (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {\n\t\tigbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;\n\t\tpr_info(\"Use MSIX interrupt\\n\");\n\t} else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {\n\t\tigbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;\n\t\tpr_info(\"Use legacy interrupt\\n\");\n\t} else {\n\t\tpr_info(\"Error: bad parameter - %s\\n\", intr_str);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic struct pci_driver igbuio_pci_driver = {\n\t.name = \"igb_uio\",\n\t.id_table = NULL,\n\t.probe = igbuio_pci_probe,\n\t.remove = igbuio_pci_remove,\n};\n\nstatic int __init\nigbuio_pci_init_module(void)\n{\n\tint ret;\n\n\tret = igbuio_config_intr_mode(intr_mode);\n\tif (ret < 0)\n\t\treturn ret;\n\n\treturn pci_register_driver(&igbuio_pci_driver);\n}\n\nstatic void __exit\nigbuio_pci_exit_module(void)\n{\n\tpci_unregister_driver(&igbuio_pci_driver);\n}\n\nmodule_init(igbuio_pci_init_module);\nmodule_exit(igbuio_pci_exit_module);\n\nmodule_param(intr_mode, charp, S_IRUGO);\nMODULE_PARM_DESC(intr_mode,\n\"igb_uio interrupt mode (default=msix):\\n\"\n\" \" RTE_INTR_MODE_MSIX_NAME \" Use MSIX interrupt\\n\"\n\" \" RTE_INTR_MODE_LEGACY_NAME \" Use Legacy interrupt\\n\"\n\"\\n\");\n\nMODULE_DESCRIPTION(\"UIO driver for Intel IGB PCI cards\");\nMODULE_LICENSE(\"GPL\");\nMODULE_AUTHOR(\"Intel Corporation\");\n" }, { "path": "lib/librte_eal/linuxapp/kni/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# module name and path\n#\nMODULE = rte_kni\n\n#\n# CFLAGS\n#\nMODULE_CFLAGS += -I$(SRCDIR) --param max-inline-insns-single=50\nMODULE_CFLAGS += -I$(RTE_OUTPUT)/include -I$(SRCDIR)/ethtool/ixgbe -I$(SRCDIR)/ethtool/igb\nMODULE_CFLAGS += -include $(RTE_OUTPUT)/include/rte_config.h\nMODULE_CFLAGS += -Wall -Werror\n\nifeq ($(shell test -f /proc/version_signature && lsb_release -si 2>/dev/null),Ubuntu)\nMODULE_CFLAGS += -DUBUNTU_RELEASE_CODE=$(shell lsb_release -sr | tr -d .)\nUBUNTU_KERNEL_CODE := $(shell cut -d' ' -f2 /proc/version_signature | \\\n cut -d'~' -f1 | cut -d- -f1,2 | tr .- $(comma))\nMODULE_CFLAGS += -D\"UBUNTU_KERNEL_CODE=UBUNTU_KERNEL_VERSION($(UBUNTU_KERNEL_CODE))\"\nendif\n\n# this lib needs main eal\nDEPDIRS-y += lib/librte_eal/linuxapp/eal\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-y := ethtool/ixgbe/ixgbe_main.c\nSRCS-y += ethtool/ixgbe/ixgbe_api.c\nSRCS-y += ethtool/ixgbe/ixgbe_common.c\nSRCS-y += ethtool/ixgbe/ixgbe_ethtool.c\nSRCS-y += ethtool/ixgbe/ixgbe_82599.c\nSRCS-y += ethtool/ixgbe/ixgbe_82598.c\nSRCS-y += ethtool/ixgbe/ixgbe_x540.c\nSRCS-y += ethtool/ixgbe/ixgbe_phy.c\nSRCS-y += ethtool/ixgbe/kcompat.c\n\nSRCS-y += ethtool/igb/e1000_82575.c\nSRCS-y += ethtool/igb/e1000_i210.c\nSRCS-y += ethtool/igb/e1000_api.c\nSRCS-y += ethtool/igb/e1000_mac.c\nSRCS-y += ethtool/igb/e1000_manage.c\nSRCS-y += ethtool/igb/e1000_mbx.c\nSRCS-y += ethtool/igb/e1000_nvm.c\nSRCS-y += ethtool/igb/e1000_phy.c\nSRCS-y += ethtool/igb/igb_ethtool.c\nSRCS-y += ethtool/igb/igb_hwmon.c\nSRCS-y += ethtool/igb/igb_main.c\nSRCS-y += ethtool/igb/igb_debugfs.c\nSRCS-y += ethtool/igb/igb_param.c\nSRCS-y += ethtool/igb/igb_procfs.c\nSRCS-y += ethtool/igb/igb_vmdq.c\n#SRCS-y += ethtool/igb/igb_ptp.c\n#SRCS-y += ethtool/igb/kcompat.c\n\nSRCS-y += kni_misc.c\nSRCS-y += kni_net.c\nSRCS-y += kni_ethtool.c\nSRCS-$(CONFIG_RTE_KNI_VHOST) += kni_vhost.c\n\ninclude $(RTE_SDK)/mk/rte.module.mk\n" }, { "path": "lib/librte_eal/linuxapp/kni/compat.h", "content": "/*\n * Minimal wrappers to allow compiling kni on older kernels.\n */\n\n#ifndef RHEL_RELEASE_VERSION\n#define RHEL_RELEASE_VERSION(a, b) (((a) << 8) + (b))\n#endif\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39) && \\\n\t(!(defined(RHEL_RELEASE_CODE) && \\\n\t RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4)))\n\n#define kstrtoul strict_strtoul\n\n#endif /* < 2.6.39 */\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)\n\n#define sk_sleep(s) (s)->sk_sleep\n\n#endif /* < 2.6.35 */\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,19,0)\n#define HAVE_IOV_ITER_MSGHDR\n#endif\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(4,1,0) )\n#define HAVE_KIOCB_MSG_PARAM\n#endif /* < 4.1.0 */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/README", "content": "..\n BSD LICENSE\n \n Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n All rights reserved.\n \n Redistribution and use in source and binary forms, with or without\n modification, are permitted provided that the following conditions\n are met:\n \n * Redistributions of source code must retain the above copyright\n notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in\n the documentation and/or other materials provided with the\n distribution.\n * Neither the name of Intel Corporation nor the names of its\n contributors may be used to endorse or promote products derived\n from this software without specific prior written permission.\n \n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nDescription\n\nIn order to support ethtool in Kernel NIC Interface, the standard Linux kernel\ndrivers of ixgbe/igb are needed to be reused here. ixgbe-3.9.17 is the version\nmodified from in kernel NIC interface kernel module to support ixgbe NIC, and\nigb-3.4.8 is the version modified from in kernel NIC interface kernel module to\nsupport igb NIC.\n\nThe source code package of ixgbe can be downloaded from sourceforge.net as below.\nhttp://sourceforge.net/projects/e1000/files/ixgbe%20stable/\nBelow source files are copied or modified from ixgbe.\n\nixgbe_82598.h\nixgbe_82599.c\nixgbe_82599.h\nixgbe_api.c\nixgbe_api.h\nixgbe_common.c\nixgbe_common.h\nixgbe_dcb.h\nixgbe_ethtool.c\nixgbe_fcoe.h\nixgbe.h\nixgbe_main.c\nixgbe_mbx.h\nixgbe_osdep.h\nixgbe_phy.c\nixgbe_phy.h\nixgbe_sriov.h\nixgbe_type.h\nkcompat.c\nkcompat.h\n\nThe source code package of igb can be downloaded from sourceforge.net as below.\nhttp://sourceforge.net/projects/e1000/files/igb%20stable/\nBelow source files are copied or modified from igb.\n\ne1000_82575.c\ne1000_82575.h\ne1000_api.c\ne1000_api.h\ne1000_defines.h\ne1000_hw.h\ne1000_mac.c\ne1000_mac.h\ne1000_manage.c\ne1000_manage.h\ne1000_mbx.c\ne1000_mbx.h\ne1000_nvm.c\ne1000_nvm.h\ne1000_osdep.h\ne1000_phy.c\ne1000_phy.h\ne1000_regs.h\nigb_ethtool.c\nigb.h\nigb_main.c\nigb_param.c\nigb_procfs.c\nigb_regtest.h\nigb_sysfs.c\nigb_vmdq.c\nigb_vmdq.h\nkcompat.c\nkcompat_ethtool.c\nkcompat.h\n\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/COPYING", "content": "\n\"This software program is licensed subject to the GNU General Public License \n(GPL). Version 2, June 1991, available at \n\"\n\nGNU General Public License \n\nVersion 2, June 1991\n\nCopyright (C) 1989, 1991 Free Software Foundation, Inc. \n59 Temple Place - Suite 330, Boston, MA 02111-1307, USA\n\nEveryone is permitted to copy and distribute verbatim copies of this license\ndocument, but changing it is not allowed.\n\nPreamble\n\nThe licenses for most software are designed to take away your freedom to \nshare and change it. By contrast, the GNU General Public License is intended\nto guarantee your freedom to share and change free software--to make sure \nthe software is free for all its users. This General Public License applies \nto most of the Free Software Foundation's software and to any other program \nwhose authors commit to using it. (Some other Free Software Foundation \nsoftware is covered by the GNU Library General Public License instead.) You \ncan apply it to your programs, too.\n\nWhen we speak of free software, we are referring to freedom, not price. Our\nGeneral Public Licenses are designed to make sure that you have the freedom \nto distribute copies of free software (and charge for this service if you \nwish), that you receive source code or can get it if you want it, that you \ncan change the software or use pieces of it in new free programs; and that \nyou know you can do these things.\n\nTo protect your rights, we need to make restrictions that forbid anyone to \ndeny you these rights or to ask you to surrender the rights. These \nrestrictions translate to certain responsibilities for you if you distribute\ncopies of the software, or if you modify it.\n\nFor example, if you distribute copies of such a program, whether gratis or \nfor a fee, you must give the recipients all the rights that you have. You \nmust make sure that they, too, receive or can get the source code. And you \nmust show them these terms so they know their rights.\n \nWe protect your rights with two steps: (1) copyright the software, and (2) \noffer you this license which gives you legal permission to copy, distribute \nand/or modify the software. \n\nAlso, for each author's protection and ours, we want to make certain that \neveryone understands that there is no warranty for this free software. If \nthe software is modified by someone else and passed on, we want its \nrecipients to know that what they have is not the original, so that any \nproblems introduced by others will not reflect on the original authors' \nreputations. \n\nFinally, any free program is threatened constantly by software patents. We \nwish to avoid the danger that redistributors of a free program will \nindividually obtain patent licenses, in effect making the program \nproprietary. To prevent this, we have made it clear that any patent must be \nlicensed for everyone's free use or not licensed at all. \n\nThe precise terms and conditions for copying, distribution and modification \nfollow. \n\nTERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION\n\n0. This License applies to any program or other work which contains a notice\n placed by the copyright holder saying it may be distributed under the \n terms of this General Public License. The \"Program\", below, refers to any\n such program or work, and a \"work based on the Program\" means either the \n Program or any derivative work under copyright law: that is to say, a \n work containing the Program or a portion of it, either verbatim or with \n modifications and/or translated into another language. (Hereinafter, \n translation is included without limitation in the term \"modification\".) \n Each licensee is addressed as \"you\". \n\n Activities other than copying, distribution and modification are not \n covered by this License; they are outside its scope. The act of running \n the Program is not restricted, and the output from the Program is covered \n only if its contents constitute a work based on the Program (independent \n of having been made by running the Program). Whether that is true depends\n on what the Program does. \n\n1. You may copy and distribute verbatim copies of the Program's source code \n as you receive it, in any medium, provided that you conspicuously and \n appropriately publish on each copy an appropriate copyright notice and \n disclaimer of warranty; keep intact all the notices that refer to this \n License and to the absence of any warranty; and give any other recipients \n of the Program a copy of this License along with the Program. \n\n You may charge a fee for the physical act of transferring a copy, and you \n may at your option offer warranty protection in exchange for a fee. \n\n2. You may modify your copy or copies of the Program or any portion of it, \n thus forming a work based on the Program, and copy and distribute such \n modifications or work under the terms of Section 1 above, provided that \n you also meet all of these conditions: \n\n * a) You must cause the modified files to carry prominent notices stating \n that you changed the files and the date of any change. \n\n * b) You must cause any work that you distribute or publish, that in \n whole or in part contains or is derived from the Program or any part \n thereof, to be licensed as a whole at no charge to all third parties\n under the terms of this License. \n\n * c) If the modified program normally reads commands interactively when \n run, you must cause it, when started running for such interactive \n use in the most ordinary way, to print or display an announcement \n including an appropriate copyright notice and a notice that there is\n no warranty (or else, saying that you provide a warranty) and that \n users may redistribute the program under these conditions, and \n telling the user how to view a copy of this License. (Exception: if \n the Program itself is interactive but does not normally print such \n an announcement, your work based on the Program is not required to \n print an announcement.) \n\n These requirements apply to the modified work as a whole. If identifiable \n sections of that work are not derived from the Program, and can be \n reasonably considered independent and separate works in themselves, then \n this License, and its terms, do not apply to those sections when you \n distribute them as separate works. But when you distribute the same \n sections as part of a whole which is a work based on the Program, the \n distribution of the whole must be on the terms of this License, whose \n permissions for other licensees extend to the entire whole, and thus to \n each and every part regardless of who wrote it. \n\n Thus, it is not the intent of this section to claim rights or contest \n your rights to work written entirely by you; rather, the intent is to \n exercise the right to control the distribution of derivative or \n collective works based on the Program. \n\n In addition, mere aggregation of another work not based on the Program \n with the Program (or with a work based on the Program) on a volume of a \n storage or distribution medium does not bring the other work under the \n scope of this License. \n\n3. You may copy and distribute the Program (or a work based on it, under \n Section 2) in object code or executable form under the terms of Sections \n 1 and 2 above provided that you also do one of the following: \n\n * a) Accompany it with the complete corresponding machine-readable source \n code, which must be distributed under the terms of Sections 1 and 2 \n above on a medium customarily used for software interchange; or, \n\n * b) Accompany it with a written offer, valid for at least three years, \n to give any third party, for a charge no more than your cost of \n physically performing source distribution, a complete machine-\n readable copy of the corresponding source code, to be distributed \n under the terms of Sections 1 and 2 above on a medium customarily \n used for software interchange; or, \n\n * c) Accompany it with the information you received as to the offer to \n distribute corresponding source code. (This alternative is allowed \n only for noncommercial distribution and only if you received the \n program in object code or executable form with such an offer, in \n accord with Subsection b above.) \n\n The source code for a work means the preferred form of the work for \n making modifications to it. For an executable work, complete source code \n means all the source code for all modules it contains, plus any \n associated interface definition files, plus the scripts used to control \n compilation and installation of the executable. However, as a special \n exception, the source code distributed need not include anything that is \n normally distributed (in either source or binary form) with the major \n components (compiler, kernel, and so on) of the operating system on which\n the executable runs, unless that component itself accompanies the \n executable. \n\n If distribution of executable or object code is made by offering access \n to copy from a designated place, then offering equivalent access to copy \n the source code from the same place counts as distribution of the source \n code, even though third parties are not compelled to copy the source \n along with the object code. \n\n4. You may not copy, modify, sublicense, or distribute the Program except as\n expressly provided under this License. Any attempt otherwise to copy, \n modify, sublicense or distribute the Program is void, and will \n automatically terminate your rights under this License. However, parties \n who have received copies, or rights, from you under this License will not\n have their licenses terminated so long as such parties remain in full \n compliance. \n\n5. You are not required to accept this License, since you have not signed \n it. However, nothing else grants you permission to modify or distribute \n the Program or its derivative works. These actions are prohibited by law \n if you do not accept this License. Therefore, by modifying or \n distributing the Program (or any work based on the Program), you \n indicate your acceptance of this License to do so, and all its terms and\n conditions for copying, distributing or modifying the Program or works \n based on it. \n\n6. Each time you redistribute the Program (or any work based on the \n Program), the recipient automatically receives a license from the \n original licensor to copy, distribute or modify the Program subject to \n these terms and conditions. You may not impose any further restrictions \n on the recipients' exercise of the rights granted herein. You are not \n responsible for enforcing compliance by third parties to this License. \n\n7. If, as a consequence of a court judgment or allegation of patent \n infringement or for any other reason (not limited to patent issues), \n conditions are imposed on you (whether by court order, agreement or \n otherwise) that contradict the conditions of this License, they do not \n excuse you from the conditions of this License. If you cannot distribute \n so as to satisfy simultaneously your obligations under this License and \n any other pertinent obligations, then as a consequence you may not \n distribute the Program at all. For example, if a patent license would \n not permit royalty-free redistribution of the Program by all those who \n receive copies directly or indirectly through you, then the only way you \n could satisfy both it and this License would be to refrain entirely from \n distribution of the Program. \n\n If any portion of this section is held invalid or unenforceable under any\n particular circumstance, the balance of the section is intended to apply\n and the section as a whole is intended to apply in other circumstances. \n\n It is not the purpose of this section to induce you to infringe any \n patents or other property right claims or to contest validity of any \n such claims; this section has the sole purpose of protecting the \n integrity of the free software distribution system, which is implemented \n by public license practices. Many people have made generous contributions\n to the wide range of software distributed through that system in \n reliance on consistent application of that system; it is up to the \n author/donor to decide if he or she is willing to distribute software \n through any other system and a licensee cannot impose that choice. \n\n This section is intended to make thoroughly clear what is believed to be \n a consequence of the rest of this License. \n\n8. If the distribution and/or use of the Program is restricted in certain \n countries either by patents or by copyrighted interfaces, the original \n copyright holder who places the Program under this License may add an \n explicit geographical distribution limitation excluding those countries, \n so that distribution is permitted only in or among countries not thus \n excluded. In such case, this License incorporates the limitation as if \n written in the body of this License. \n\n9. The Free Software Foundation may publish revised and/or new versions of \n the General Public License from time to time. Such new versions will be \n similar in spirit to the present version, but may differ in detail to \n address new problems or concerns. \n\n Each version is given a distinguishing version number. If the Program \n specifies a version number of this License which applies to it and \"any \n later version\", you have the option of following the terms and \n conditions either of that version or of any later version published by \n the Free Software Foundation. If the Program does not specify a version \n number of this License, you may choose any version ever published by the \n Free Software Foundation. \n\n10. If you wish to incorporate parts of the Program into other free programs\n whose distribution conditions are different, write to the author to ask \n for permission. For software which is copyrighted by the Free Software \n Foundation, write to the Free Software Foundation; we sometimes make \n exceptions for this. Our decision will be guided by the two goals of \n preserving the free status of all derivatives of our free software and \n of promoting the sharing and reuse of software generally. \n\n NO WARRANTY\n\n11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY \n FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN \n OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES \n PROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER \n EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED \n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE \n ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH \n YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL \n NECESSARY SERVICING, REPAIR OR CORRECTION. \n\n12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING \n WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR \n REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR \n DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL \n DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM \n (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED \n INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF \n THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR \n OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. \n\nEND OF TERMS AND CONDITIONS\n\nHow to Apply These Terms to Your New Programs\n\nIf you develop a new program, and you want it to be of the greatest \npossible use to the public, the best way to achieve this is to make it free \nsoftware which everyone can redistribute and change under these terms. \n\nTo do so, attach the following notices to the program. It is safest to \nattach them to the start of each source file to most effectively convey the\nexclusion of warranty; and each file should have at least the \"copyright\" \nline and a pointer to where the full notice is found. \n\none line to give the program's name and an idea of what it does.\nCopyright (C) yyyy name of author\n\nThis program is free software; you can redistribute it and/or modify it \nunder the terms of the GNU General Public License as published by the Free \nSoftware Foundation; either version 2 of the License, or (at your option) \nany later version.\n\nThis program is distributed in the hope that it will be useful, but WITHOUT \nANY WARRANTY; without even the implied warranty of MERCHANTABILITY or \nFITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for \nmore details.\n\nYou should have received a copy of the GNU General Public License along with\nthis program; if not, write to the Free Software Foundation, Inc., 59 \nTemple Place - Suite 330, Boston, MA 02111-1307, USA.\n\nAlso add information on how to contact you by electronic and paper mail. \n\nIf the program is interactive, make it output a short notice like this when \nit starts in an interactive mode: \n\nGnomovision version 69, Copyright (C) year name of author Gnomovision comes \nwith ABSOLUTELY NO WARRANTY; for details type 'show w'. This is free \nsoftware, and you are welcome to redistribute it under certain conditions; \ntype 'show c' for details.\n\nThe hypothetical commands 'show w' and 'show c' should show the appropriate \nparts of the General Public License. Of course, the commands you use may be \ncalled something other than 'show w' and 'show c'; they could even be \nmouse-clicks or menu items--whatever suits your program. \n\nYou should also get your employer (if you work as a programmer) or your \nschool, if any, to sign a \"copyright disclaimer\" for the program, if \nnecessary. Here is a sample; alter the names: \n\nYoyodyne, Inc., hereby disclaims all copyright interest in the program \n'Gnomovision' (which makes passes at compilers) written by James Hacker.\n\nsignature of Ty Coon, 1 April 1989\nTy Coon, President of Vice\n\nThis General Public License does not permit incorporating your program into \nproprietary programs. If your program is a subroutine library, you may \nconsider it more useful to permit linking proprietary applications with the \nlibrary. If this is what you want to do, use the GNU Library General Public \nLicense instead of this License.\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_82575.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n/*\n * 82575EB Gigabit Network Connection\n * 82575EB Gigabit Backplane Connection\n * 82575GB Gigabit Network Connection\n * 82576 Gigabit Network Connection\n * 82576 Quad Port Gigabit Mezzanine Adapter\n * 82580 Gigabit Network Connection\n * I350 Gigabit Network Connection\n */\n\n#include \"e1000_api.h\"\n#include \"e1000_i210.h\"\n\nstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw);\nstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw);\nstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw);\nstatic void e1000_release_phy_82575(struct e1000_hw *hw);\nstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);\nstatic void e1000_release_nvm_82575(struct e1000_hw *hw);\nstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw);\nstatic s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);\nstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);\nstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\t u16 *duplex);\nstatic s32 e1000_init_hw_82575(struct e1000_hw *hw);\nstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);\nstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 *data);\nstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw);\nstatic s32 e1000_reset_hw_82580(struct e1000_hw *hw);\nstatic s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,\n\t\t\t\t u32 offset, u16 *data);\nstatic s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,\n\t\t\t\t u32 offset, u16 data);\nstatic s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,\n\t\t\t\t\t bool active);\nstatic s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,\n\t\t\t\t\t bool active);\nstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,\n\t\t\t\t\t bool active);\nstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);\nstatic s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);\nstatic s32 e1000_get_media_type_82575(struct e1000_hw *hw);\nstatic s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);\nstatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);\nstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,\n\t\t\t\t\t u32 offset, u16 data);\nstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);\nstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);\nstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,\n\t\t\t\t\t\t u16 *speed, u16 *duplex);\nstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw);\nstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);\nstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw);\nstatic s32 e1000_reset_init_script_82575(struct e1000_hw *hw);\nstatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);\nstatic void e1000_config_collision_dist_82575(struct e1000_hw *hw);\nstatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);\nstatic void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);\nstatic void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);\nstatic s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);\nstatic s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);\nstatic s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);\nstatic s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);\nstatic s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,\n\t\t\t\t\t\t u16 offset);\nstatic s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,\n\t\t\t\t\t\t u16 offset);\nstatic s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);\nstatic s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);\nstatic void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);\nstatic void e1000_clear_vfta_i350(struct e1000_hw *hw);\n\nstatic void e1000_i2c_start(struct e1000_hw *hw);\nstatic void e1000_i2c_stop(struct e1000_hw *hw);\nstatic s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);\nstatic s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);\nstatic s32 e1000_get_i2c_ack(struct e1000_hw *hw);\nstatic s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);\nstatic s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);\nstatic void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);\nstatic void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);\nstatic s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);\nstatic bool e1000_get_i2c_data(u32 *i2cctl);\n\nstatic const u16 e1000_82580_rxpbs_table[] = {\n\t36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };\n#define E1000_82580_RXPBS_TABLE_SIZE \\\n\t(sizeof(e1000_82580_rxpbs_table)/sizeof(u16))\n\n\n/**\n * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO\n * @hw: pointer to the HW structure\n *\n * Called to determine if the I2C pins are being used for I2C or as an\n * external MDIO interface since the two options are mutually exclusive.\n **/\nstatic bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)\n{\n\tu32 reg = 0;\n\tbool ext_mdio = false;\n\n\tDEBUGFUNC(\"e1000_sgmii_uses_mdio_82575\");\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82575:\n\tcase e1000_82576:\n\t\treg = E1000_READ_REG(hw, E1000_MDIC);\n\t\text_mdio = !!(reg & E1000_MDIC_DEST);\n\t\tbreak;\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\treg = E1000_READ_REG(hw, E1000_MDICNFG);\n\t\text_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\treturn ext_mdio;\n}\n\n/**\n * e1000_init_phy_params_82575 - Init PHY func ptrs.\n * @hw: pointer to the HW structure\n **/\nstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 ctrl_ext;\n\n\tDEBUGFUNC(\"e1000_init_phy_params_82575\");\n\n\tphy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;\n\tphy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;\n\n\tif (hw->phy.media_type != e1000_media_type_copper) {\n\t\tphy->type = e1000_phy_none;\n\t\tgoto out;\n\t}\n\n\tphy->ops.power_up = e1000_power_up_phy_copper;\n\tphy->ops.power_down = e1000_power_down_phy_copper_82575;\n\n\tphy->autoneg_mask\t= AUTONEG_ADVERTISE_SPEED_DEFAULT;\n\tphy->reset_delay_us\t= 100;\n\n\tphy->ops.acquire\t= e1000_acquire_phy_82575;\n\tphy->ops.check_reset_block = e1000_check_reset_block_generic;\n\tphy->ops.commit\t\t= e1000_phy_sw_reset_generic;\n\tphy->ops.get_cfg_done\t= e1000_get_cfg_done_82575;\n\tphy->ops.release\t= e1000_release_phy_82575;\n\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\n\tif (e1000_sgmii_active_82575(hw)) {\n\t\tphy->ops.reset = e1000_phy_hw_reset_sgmii_82575;\n\t\tctrl_ext |= E1000_CTRL_I2C_ENA;\n\t} else {\n\t\tphy->ops.reset = e1000_phy_hw_reset_generic;\n\t\tctrl_ext &= ~E1000_CTRL_I2C_ENA;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\te1000_reset_mdicnfg_82580(hw);\n\n\tif (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {\n\t\tphy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;\n\t\tphy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;\n\t} else {\n\t\tswitch (hw->mac.type) {\n\t\tcase e1000_82580:\n\t\tcase e1000_i350:\n\t\tcase e1000_i354:\n\t\t\tphy->ops.read_reg = e1000_read_phy_reg_82580;\n\t\t\tphy->ops.write_reg = e1000_write_phy_reg_82580;\n\t\t\tbreak;\n\t\tcase e1000_i210:\n\t\tcase e1000_i211:\n\t\t\tphy->ops.read_reg = e1000_read_phy_reg_gs40g;\n\t\t\tphy->ops.write_reg = e1000_write_phy_reg_gs40g;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tphy->ops.read_reg = e1000_read_phy_reg_igp;\n\t\t\tphy->ops.write_reg = e1000_write_phy_reg_igp;\n\t\t}\n\t}\n\n\t/* Set phy->phy_addr and phy->id. */\n\tret_val = e1000_get_phy_id_82575(hw);\n\n\t/* Verify phy id and set remaining function pointers */\n\tswitch (phy->id) {\n\tcase M88E1543_E_PHY_ID:\n\tcase I347AT4_E_PHY_ID:\n\tcase M88E1112_E_PHY_ID:\n\tcase M88E1340M_E_PHY_ID:\n\tcase M88E1111_I_PHY_ID:\n\t\tphy->type\t\t= e1000_phy_m88;\n\t\tphy->ops.check_polarity\t= e1000_check_polarity_m88;\n\t\tphy->ops.get_info\t= e1000_get_phy_info_m88;\n\t\tif (phy->id == I347AT4_E_PHY_ID ||\n\t\t phy->id == M88E1112_E_PHY_ID ||\n\t\t phy->id == M88E1340M_E_PHY_ID)\n\t\t\tphy->ops.get_cable_length =\n\t\t\t\t\t e1000_get_cable_length_m88_gen2;\n\t\telse if (phy->id == M88E1543_E_PHY_ID)\n\t\t\tphy->ops.get_cable_length =\n\t\t\t\t\t e1000_get_cable_length_m88_gen2;\n\t\telse\n\t\t\tphy->ops.get_cable_length = e1000_get_cable_length_m88;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;\n\t\t/* Check if this PHY is confgured for media swap. */\n\t\tif (phy->id == M88E1112_E_PHY_ID) {\n\t\t\tu16 data;\n\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t E1000_M88E1112_PAGE_ADDR,\n\t\t\t\t\t\t 2);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t E1000_M88E1112_MAC_CTRL_1,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tdata = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>\n\t\t\t E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;\n\t\t\tif (data == E1000_M88E1112_AUTO_COPPER_SGMII ||\n\t\t\t data == E1000_M88E1112_AUTO_COPPER_BASEX)\n\t\t\t\thw->mac.ops.check_for_link =\n\t\t\t\t\t\te1000_check_for_link_media_swap;\n\t\t}\n\t\tbreak;\n\tcase IGP03E1000_E_PHY_ID:\n\tcase IGP04E1000_E_PHY_ID:\n\t\tphy->type = e1000_phy_igp_3;\n\t\tphy->ops.check_polarity = e1000_check_polarity_igp;\n\t\tphy->ops.get_info = e1000_get_phy_info_igp;\n\t\tphy->ops.get_cable_length = e1000_get_cable_length_igp_2;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;\n\t\tphy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;\n\t\tphy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;\n\t\tbreak;\n\tcase I82580_I_PHY_ID:\n\tcase I350_I_PHY_ID:\n\t\tphy->type = e1000_phy_82580;\n\t\tphy->ops.check_polarity = e1000_check_polarity_82577;\n\t\tphy->ops.force_speed_duplex =\n\t\t\t\t\t e1000_phy_force_speed_duplex_82577;\n\t\tphy->ops.get_cable_length = e1000_get_cable_length_82577;\n\t\tphy->ops.get_info = e1000_get_phy_info_82577;\n\t\tphy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;\n\t\tphy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;\n\t\tbreak;\n\tcase I210_I_PHY_ID:\n\t\tphy->type\t\t= e1000_phy_i210;\n\t\tphy->ops.check_polarity\t= e1000_check_polarity_m88;\n\t\tphy->ops.get_info\t= e1000_get_phy_info_m88;\n\t\tphy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;\n\t\tphy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;\n\t\tphy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;\n\t\tphy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;\n\t\tbreak;\n\tdefault:\n\t\tret_val = -E1000_ERR_PHY;\n\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_nvm_params_82575 - Init NVM func ptrs.\n * @hw: pointer to the HW structure\n **/\ns32 e1000_init_nvm_params_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\tu16 size;\n\n\tDEBUGFUNC(\"e1000_init_nvm_params_82575\");\n\n\tsize = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>\n\t\t E1000_EECD_SIZE_EX_SHIFT);\n\t/*\n\t * Added to a constant, \"size\" becomes the left-shift value\n\t * for setting word_size.\n\t */\n\tsize += NVM_WORD_SIZE_BASE_SHIFT;\n\n\t/* Just in case size is out of range, cap it to the largest\n\t * EEPROM size supported\n\t */\n\tif (size > 15)\n\t\tsize = 15;\n\n\tnvm->word_size = 1 << size;\n\tif (hw->mac.type < e1000_i210) {\n\t\tnvm->opcode_bits = 8;\n\t\tnvm->delay_usec = 1;\n\n\t\tswitch (nvm->override) {\n\t\tcase e1000_nvm_override_spi_large:\n\t\t\tnvm->page_size = 32;\n\t\t\tnvm->address_bits = 16;\n\t\t\tbreak;\n\t\tcase e1000_nvm_override_spi_small:\n\t\t\tnvm->page_size = 8;\n\t\t\tnvm->address_bits = 8;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tnvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;\n\t\t\tnvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?\n\t\t\t\t\t 16 : 8;\n\t\t\tbreak;\n\t\t}\n\t\tif (nvm->word_size == (1 << 15))\n\t\t\tnvm->page_size = 128;\n\n\t\tnvm->type = e1000_nvm_eeprom_spi;\n\t} else {\n\t\tnvm->type = e1000_nvm_flash_hw;\n\t}\n\n\t/* Function Pointers */\n\tnvm->ops.acquire = e1000_acquire_nvm_82575;\n\tnvm->ops.release = e1000_release_nvm_82575;\n\tif (nvm->word_size < (1 << 15))\n\t\tnvm->ops.read = e1000_read_nvm_eerd;\n\telse\n\t\tnvm->ops.read = e1000_read_nvm_spi;\n\n\tnvm->ops.write = e1000_write_nvm_spi;\n\tnvm->ops.validate = e1000_validate_nvm_checksum_generic;\n\tnvm->ops.update = e1000_update_nvm_checksum_generic;\n\tnvm->ops.valid_led_default = e1000_valid_led_default_82575;\n\n\t/* override generic family function pointers for specific descendants */\n\tswitch (hw->mac.type) {\n\tcase e1000_82580:\n\t\tnvm->ops.validate = e1000_validate_nvm_checksum_82580;\n\t\tnvm->ops.update = e1000_update_nvm_checksum_82580;\n\t\tbreak;\n\tcase e1000_i350:\n\t//case e1000_i354:\n\t\tnvm->ops.validate = e1000_validate_nvm_checksum_i350;\n\t\tnvm->ops.update = e1000_update_nvm_checksum_i350;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_mac_params_82575 - Init MAC func ptrs.\n * @hw: pointer to the HW structure\n **/\nstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tstruct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;\n\n\tDEBUGFUNC(\"e1000_init_mac_params_82575\");\n\n\t/* Derives media type */\n\te1000_get_media_type_82575(hw);\n\t/* Set mta register count */\n\tmac->mta_reg_count = 128;\n\t/* Set uta register count */\n\tmac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;\n\t/* Set rar entry count */\n\tmac->rar_entry_count = E1000_RAR_ENTRIES_82575;\n\tif (mac->type == e1000_82576)\n\t\tmac->rar_entry_count = E1000_RAR_ENTRIES_82576;\n\tif (mac->type == e1000_82580)\n\t\tmac->rar_entry_count = E1000_RAR_ENTRIES_82580;\n\tif (mac->type == e1000_i350 || mac->type == e1000_i354)\n\t\tmac->rar_entry_count = E1000_RAR_ENTRIES_I350;\n\n\t/* Enable EEE default settings for EEE supported devices */\n\tif (mac->type >= e1000_i350)\n\t\tdev_spec->eee_disable = false;\n\n\t/* Allow a single clear of the SW semaphore on I210 and newer */\n\tif (mac->type >= e1000_i210)\n\t\tdev_spec->clear_semaphore_once = true;\n\n\t/* Set if part includes ASF firmware */\n\tmac->asf_firmware_present = true;\n\t/* FWSM register */\n\tmac->has_fwsm = true;\n\t/* ARC supported; valid only if manageability features are enabled. */\n\tmac->arc_subsystem_valid =\n\t\t!!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);\n\n\t/* Function pointers */\n\n\t/* bus type/speed/width */\n\tmac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;\n\t/* reset */\n\tif (mac->type >= e1000_82580)\n\t\tmac->ops.reset_hw = e1000_reset_hw_82580;\n\telse\n\tmac->ops.reset_hw = e1000_reset_hw_82575;\n\t/* hw initialization */\n\tmac->ops.init_hw = e1000_init_hw_82575;\n\t/* link setup */\n\tmac->ops.setup_link = e1000_setup_link_generic;\n\t/* physical interface link setup */\n\tmac->ops.setup_physical_interface =\n\t\t(hw->phy.media_type == e1000_media_type_copper)\n\t\t? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;\n\t/* physical interface shutdown */\n\tmac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;\n\t/* physical interface power up */\n\tmac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;\n\t/* check for link */\n\tmac->ops.check_for_link = e1000_check_for_link_82575;\n\t/* read mac address */\n\tmac->ops.read_mac_addr = e1000_read_mac_addr_82575;\n\t/* configure collision distance */\n\tmac->ops.config_collision_dist = e1000_config_collision_dist_82575;\n\t/* multicast address update */\n\tmac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;\n\tif (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {\n\t\t/* writing VFTA */\n\t\tmac->ops.write_vfta = e1000_write_vfta_i350;\n\t\t/* clearing VFTA */\n\t\tmac->ops.clear_vfta = e1000_clear_vfta_i350;\n\t} else {\n\t\t/* writing VFTA */\n\t\tmac->ops.write_vfta = e1000_write_vfta_generic;\n\t\t/* clearing VFTA */\n\t\tmac->ops.clear_vfta = e1000_clear_vfta_generic;\n\t}\n\tif (hw->mac.type >= e1000_82580)\n\t\tmac->ops.validate_mdi_setting =\n\t\t\t\te1000_validate_mdi_setting_crossover_generic;\n\t/* ID LED init */\n\tmac->ops.id_led_init = e1000_id_led_init_generic;\n\t/* blink LED */\n\tmac->ops.blink_led = e1000_blink_led_generic;\n\t/* setup LED */\n\tmac->ops.setup_led = e1000_setup_led_generic;\n\t/* cleanup LED */\n\tmac->ops.cleanup_led = e1000_cleanup_led_generic;\n\t/* turn on/off LED */\n\tmac->ops.led_on = e1000_led_on_generic;\n\tmac->ops.led_off = e1000_led_off_generic;\n\t/* clear hardware counters */\n\tmac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;\n\t/* link info */\n\tmac->ops.get_link_up_info = e1000_get_link_up_info_82575;\n\t/* get thermal sensor data */\n\tmac->ops.get_thermal_sensor_data =\n\t\t\t\te1000_get_thermal_sensor_data_generic;\n\tmac->ops.init_thermal_sensor_thresh =\n\t\t\t\te1000_init_thermal_sensor_thresh_generic;\n\t/* acquire SW_FW sync */\n\tmac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;\n\tmac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;\n\tif (mac->type >= e1000_i210) {\n\t\tmac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;\n\t\tmac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;\n\t}\n\n\t/* set lan id for port to determine which phy lock to use */\n\thw->mac.ops.set_lan_id(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_function_pointers_82575 - Init func ptrs.\n * @hw: pointer to the HW structure\n *\n * Called to initialize all function pointers and parameters.\n **/\nvoid e1000_init_function_pointers_82575(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_init_function_pointers_82575\");\n\n\thw->mac.ops.init_params = e1000_init_mac_params_82575;\n\thw->nvm.ops.init_params = e1000_init_nvm_params_82575;\n\thw->phy.ops.init_params = e1000_init_phy_params_82575;\n\thw->mbx.ops.init_params = e1000_init_mbx_params_pf;\n}\n\n/**\n * e1000_acquire_phy_82575 - Acquire rights to access PHY\n * @hw: pointer to the HW structure\n *\n * Acquire access rights to the correct PHY.\n **/\nstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw)\n{\n\tu16 mask = E1000_SWFW_PHY0_SM;\n\n\tDEBUGFUNC(\"e1000_acquire_phy_82575\");\n\n\tif (hw->bus.func == E1000_FUNC_1)\n\t\tmask = E1000_SWFW_PHY1_SM;\n\telse if (hw->bus.func == E1000_FUNC_2)\n\t\tmask = E1000_SWFW_PHY2_SM;\n\telse if (hw->bus.func == E1000_FUNC_3)\n\t\tmask = E1000_SWFW_PHY3_SM;\n\n\treturn hw->mac.ops.acquire_swfw_sync(hw, mask);\n}\n\n/**\n * e1000_release_phy_82575 - Release rights to access PHY\n * @hw: pointer to the HW structure\n *\n * A wrapper to release access rights to the correct PHY.\n **/\nstatic void e1000_release_phy_82575(struct e1000_hw *hw)\n{\n\tu16 mask = E1000_SWFW_PHY0_SM;\n\n\tDEBUGFUNC(\"e1000_release_phy_82575\");\n\n\tif (hw->bus.func == E1000_FUNC_1)\n\t\tmask = E1000_SWFW_PHY1_SM;\n\telse if (hw->bus.func == E1000_FUNC_2)\n\t\tmask = E1000_SWFW_PHY2_SM;\n\telse if (hw->bus.func == E1000_FUNC_3)\n\t\tmask = E1000_SWFW_PHY3_SM;\n\n\thw->mac.ops.release_swfw_sync(hw, mask);\n}\n\n/**\n * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the PHY register at offset using the serial gigabit media independent\n * interface and stores the retrieved information in data.\n **/\nstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 *data)\n{\n\ts32 ret_val = -E1000_ERR_PARAM;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_sgmii_82575\");\n\n\tif (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {\n\t\tDEBUGOUT1(\"PHY Address %u is out of range\\n\", offset);\n\t\tgoto out;\n\t}\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_read_phy_reg_i2c(hw, offset, data);\n\n\thw->phy.ops.release(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Writes the data to PHY register at the offset using the serial gigabit\n * media independent interface.\n **/\nstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,\n\t\t\t\t\t u16 data)\n{\n\ts32 ret_val = -E1000_ERR_PARAM;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_sgmii_82575\");\n\n\tif (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {\n\t\tDEBUGOUT1(\"PHY Address %d is out of range\\n\", offset);\n\t\tgoto out;\n\t}\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_write_phy_reg_i2c(hw, offset, data);\n\n\thw->phy.ops.release(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_get_phy_id_82575 - Retrieve PHY addr and id\n * @hw: pointer to the HW structure\n *\n * Retrieves the PHY address and ID for both PHY's which do and do not use\n * sgmi interface.\n **/\nstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 phy_id;\n\tu32 ctrl_ext;\n\tu32 mdic;\n\n\tDEBUGFUNC(\"e1000_get_phy_id_82575\");\n\n\t/* i354 devices can have a PHY that needs an extra read for id */\n\tif (hw->mac.type == e1000_i354)\n\t\te1000_get_phy_id(hw);\n\n\n\t/*\n\t * For SGMII PHYs, we try the list of possible addresses until\n\t * we find one that works. For non-SGMII PHYs\n\t * (e.g. integrated copper PHYs), an address of 1 should\n\t * work. The result of this function should mean phy->phy_addr\n\t * and phy->id are set correctly.\n\t */\n\tif (!e1000_sgmii_active_82575(hw)) {\n\t\tphy->addr = 1;\n\t\tret_val = e1000_get_phy_id(hw);\n\t\tgoto out;\n\t}\n\n\tif (e1000_sgmii_uses_mdio_82575(hw)) {\n\t\tswitch (hw->mac.type) {\n\t\tcase e1000_82575:\n\t\tcase e1000_82576:\n\t\t\tmdic = E1000_READ_REG(hw, E1000_MDIC);\n\t\t\tmdic &= E1000_MDIC_PHY_MASK;\n\t\t\tphy->addr = mdic >> E1000_MDIC_PHY_SHIFT;\n\t\t\tbreak;\n\t\tcase e1000_82580:\n\t\tcase e1000_i350:\n\t\tcase e1000_i354:\n\t\tcase e1000_i210:\n\t\tcase e1000_i211:\n\t\t\tmdic = E1000_READ_REG(hw, E1000_MDICNFG);\n\t\t\tmdic &= E1000_MDICNFG_PHY_MASK;\n\t\t\tphy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tret_val = -E1000_ERR_PHY;\n\t\t\tgoto out;\n\t\t\tbreak;\n\t\t}\n\t\tret_val = e1000_get_phy_id(hw);\n\t\tgoto out;\n\t}\n\n\t/* Power on sgmii phy if it is disabled */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT,\n\t\t\tctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);\n\tE1000_WRITE_FLUSH(hw);\n\tmsec_delay(300);\n\n\t/*\n\t * The address field in the I2CCMD register is 3 bits and 0 is invalid.\n\t * Therefore, we need to test 1-7\n\t */\n\tfor (phy->addr = 1; phy->addr < 8; phy->addr++) {\n\t\tret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);\n\t\tif (ret_val == E1000_SUCCESS) {\n\t\t\tDEBUGOUT2(\"Vendor ID 0x%08X read at address %u\\n\",\n\t\t\t\t phy_id, phy->addr);\n\t\t\t/*\n\t\t\t * At the time of this writing, The M88 part is\n\t\t\t * the only supported SGMII PHY product.\n\t\t\t */\n\t\t\tif (phy_id == M88_VENDOR)\n\t\t\t\tbreak;\n\t\t} else {\n\t\t\tDEBUGOUT1(\"PHY address %u was unreadable\\n\",\n\t\t\t\t phy->addr);\n\t\t}\n\t}\n\n\t/* A valid PHY type couldn't be found. */\n\tif (phy->addr == 8) {\n\t\tphy->addr = 0;\n\t\tret_val = -E1000_ERR_PHY;\n\t} else {\n\t\tret_val = e1000_get_phy_id(hw);\n\t}\n\n\t/* restore previous sfp cage power state */\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset\n * @hw: pointer to the HW structure\n *\n * Resets the PHY using the serial gigabit media independent interface.\n **/\nstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_phy_hw_reset_sgmii_82575\");\n\n\t/*\n\t * This isn't a true \"hard\" reset, but is the only reset\n\t * available to us at this time.\n\t */\n\n\tDEBUGOUT(\"Soft resetting SGMII attached PHY...\\n\");\n\n\tif (!(hw->phy.ops.write_reg))\n\t\tgoto out;\n\n\t/*\n\t * SFP documentation requires the following to configure the SPF module\n\t * to work on SGMII. No further documentation is given.\n\t */\n\tret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = hw->phy.ops.commit(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state\n * @hw: pointer to the HW structure\n * @active: true to enable LPLU, false to disable\n *\n * Sets the LPLU D0 state according to the active flag. When\n * activating LPLU this function also disables smart speed\n * and vice versa. LPLU will not be activated unless the\n * device autonegotiation advertisement meets standards of\n * either 10 or 10/100 or 10/100/1000 at all duplexes.\n * This is a function pointer entry point only called by\n * PHY setup routines.\n **/\nstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_set_d0_lplu_state_82575\");\n\n\tif (!(hw->phy.ops.read_reg))\n\t\tgoto out;\n\n\tret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (active) {\n\t\tdata |= IGP02E1000_PM_D0_LPLU;\n\t\tret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,\n\t\t\t\t\t data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n\t\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t &data);\n\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\tret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t} else {\n\t\tdata &= ~IGP02E1000_PM_D0_LPLU;\n\t\tret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,\n\t\t\t\t\t data);\n\t\t/*\n\t\t * LPLU and SmartSpeed are mutually exclusive. LPLU is used\n\t\t * during Dx states where the power conservation is most\n\t\t * important. During driver activity we should enable\n\t\t * SmartSpeed, so performance is maintained.\n\t\t */\n\t\tif (phy->smart_speed == e1000_smart_speed_on) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tdata |= IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t} else if (phy->smart_speed == e1000_smart_speed_off) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\n\t\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state\n * @hw: pointer to the HW structure\n * @active: true to enable LPLU, false to disable\n *\n * Sets the LPLU D0 state according to the active flag. When\n * activating LPLU this function also disables smart speed\n * and vice versa. LPLU will not be activated unless the\n * device autonegotiation advertisement meets standards of\n * either 10 or 10/100 or 10/100/1000 at all duplexes.\n * This is a function pointer entry point only called by\n * PHY setup routines.\n **/\nstatic s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 data;\n\n\tDEBUGFUNC(\"e1000_set_d0_lplu_state_82580\");\n\n\tdata = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);\n\n\tif (active) {\n\t\tdata |= E1000_82580_PM_D0_LPLU;\n\n\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n\t\tdata &= ~E1000_82580_PM_SPD;\n\t} else {\n\t\tdata &= ~E1000_82580_PM_D0_LPLU;\n\n\t\t/*\n\t\t * LPLU and SmartSpeed are mutually exclusive. LPLU is used\n\t\t * during Dx states where the power conservation is most\n\t\t * important. During driver activity we should enable\n\t\t * SmartSpeed, so performance is maintained.\n\t\t */\n\t\tif (phy->smart_speed == e1000_smart_speed_on)\n\t\t\tdata |= E1000_82580_PM_SPD;\n\t\telse if (phy->smart_speed == e1000_smart_speed_off)\n\t\t\tdata &= ~E1000_82580_PM_SPD;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);\n\treturn ret_val;\n}\n\n/**\n * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3\n * @hw: pointer to the HW structure\n * @active: boolean used to enable/disable lplu\n *\n * Success returns 0, Failure returns 1\n *\n * The low power link up (lplu) state is set to the power management level D3\n * and SmartSpeed is disabled when active is true, else clear lplu for D3\n * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU\n * is used during Dx states where the power conservation is most important.\n * During driver activity, SmartSpeed should be enabled so performance is\n * maintained.\n **/\ns32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 data;\n\n\tDEBUGFUNC(\"e1000_set_d3_lplu_state_82580\");\n\n\tdata = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);\n\n\tif (!active) {\n\t\tdata &= ~E1000_82580_PM_D3_LPLU;\n\t\t/*\n\t\t * LPLU and SmartSpeed are mutually exclusive. LPLU is used\n\t\t * during Dx states where the power conservation is most\n\t\t * important. During driver activity we should enable\n\t\t * SmartSpeed, so performance is maintained.\n\t\t */\n\t\tif (phy->smart_speed == e1000_smart_speed_on)\n\t\t\tdata |= E1000_82580_PM_SPD;\n\t\telse if (phy->smart_speed == e1000_smart_speed_off)\n\t\t\tdata &= ~E1000_82580_PM_SPD;\n\t} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||\n\t\t (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||\n\t\t (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {\n\t\tdata |= E1000_82580_PM_D3_LPLU;\n\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n\t\tdata &= ~E1000_82580_PM_SPD;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);\n\treturn ret_val;\n}\n\n/**\n * e1000_acquire_nvm_82575 - Request for access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Acquire the necessary semaphores for exclusive access to the EEPROM.\n * Set the EEPROM access request bit and wait for EEPROM access grant bit.\n * Return successful if access grant bit set, else clear the request for\n * EEPROM access and return -E1000_ERR_NVM (-1).\n **/\nstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_acquire_nvm_82575\");\n\n\tret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);\n\tif (ret_val)\n\t\tgoto out;\n\n\t/*\n\t * Check if there is some access\n\t * error this access may hook on\n\t */\n\tif (hw->mac.type == e1000_i350) {\n\t\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\t\tif (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |\n\t\t E1000_EECD_TIMEOUT)) {\n\t\t\t/* Clear all access error flags */\n\t\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd |\n\t\t\t\t\tE1000_EECD_ERROR_CLR);\n\t\t\tDEBUGOUT(\"Nvm bit banging access error detected and cleared.\\n\");\n\t\t}\n\t}\n\tif (hw->mac.type == e1000_82580) {\n\t\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\t\tif (eecd & E1000_EECD_BLOCKED) {\n\t\t\t/* Clear access error flag */\n\t\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd |\n\t\t\t\t\tE1000_EECD_BLOCKED);\n\t\t\tDEBUGOUT(\"Nvm bit banging access error detected and cleared.\\n\");\n\t\t}\n\t}\n\n\n\tret_val = e1000_acquire_nvm_generic(hw);\n\tif (ret_val)\n\t\te1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_release_nvm_82575 - Release exclusive access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Stop any current commands to the EEPROM and clear the EEPROM request bit,\n * then release the semaphores acquired.\n **/\nstatic void e1000_release_nvm_82575(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_release_nvm_82575\");\n\n\te1000_release_nvm_generic(hw);\n\n\te1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);\n}\n\n/**\n * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore\n * @hw: pointer to the HW structure\n * @mask: specifies which semaphore to acquire\n *\n * Acquire the SW/FW semaphore to access the PHY or NVM. The mask\n * will also specify which port we're acquiring the lock for.\n **/\nstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)\n{\n\tu32 swfw_sync;\n\tu32 swmask = mask;\n\tu32 fwmask = mask << 16;\n\ts32 ret_val = E1000_SUCCESS;\n\ts32 i = 0, timeout = 200; /* FIXME: find real value to use here */\n\n\tDEBUGFUNC(\"e1000_acquire_swfw_sync_82575\");\n\n\twhile (i < timeout) {\n\t\tif (e1000_get_hw_semaphore_generic(hw)) {\n\t\t\tret_val = -E1000_ERR_SWFW_SYNC;\n\t\t\tgoto out;\n\t\t}\n\n\t\tswfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);\n\t\tif (!(swfw_sync & (fwmask | swmask)))\n\t\t\tbreak;\n\n\t\t/*\n\t\t * Firmware currently using resource (fwmask)\n\t\t * or other software thread using resource (swmask)\n\t\t */\n\t\te1000_put_hw_semaphore_generic(hw);\n\t\tmsec_delay_irq(5);\n\t\ti++;\n\t}\n\n\tif (i == timeout) {\n\t\tDEBUGOUT(\"Driver can't access resource, SW_FW_SYNC timeout.\\n\");\n\t\tret_val = -E1000_ERR_SWFW_SYNC;\n\t\tgoto out;\n\t}\n\n\tswfw_sync |= swmask;\n\tE1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);\n\n\te1000_put_hw_semaphore_generic(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_release_swfw_sync_82575 - Release SW/FW semaphore\n * @hw: pointer to the HW structure\n * @mask: specifies which semaphore to acquire\n *\n * Release the SW/FW semaphore used to access the PHY or NVM. The mask\n * will also specify which port we're releasing the lock for.\n **/\nstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)\n{\n\tu32 swfw_sync;\n\n\tDEBUGFUNC(\"e1000_release_swfw_sync_82575\");\n\n\twhile (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)\n\t\t; /* Empty */\n\n\tswfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);\n\tswfw_sync &= ~mask;\n\tE1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);\n\n\te1000_put_hw_semaphore_generic(hw);\n}\n\n/**\n * e1000_get_cfg_done_82575 - Read config done bit\n * @hw: pointer to the HW structure\n *\n * Read the management control register for the config done bit for\n * completion status. NOTE: silicon which is EEPROM-less will fail trying\n * to read the config done bit, so an error is *ONLY* logged and returns\n * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon\n * would not be able to be reset or change link.\n **/\nstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)\n{\n\ts32 timeout = PHY_CFG_TIMEOUT;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 mask = E1000_NVM_CFG_DONE_PORT_0;\n\n\tDEBUGFUNC(\"e1000_get_cfg_done_82575\");\n\n\tif (hw->bus.func == E1000_FUNC_1)\n\t\tmask = E1000_NVM_CFG_DONE_PORT_1;\n\telse if (hw->bus.func == E1000_FUNC_2)\n\t\tmask = E1000_NVM_CFG_DONE_PORT_2;\n\telse if (hw->bus.func == E1000_FUNC_3)\n\t\tmask = E1000_NVM_CFG_DONE_PORT_3;\n\twhile (timeout) {\n\t\tif (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t\ttimeout--;\n\t}\n\tif (!timeout)\n\t\tDEBUGOUT(\"MNG configuration cycle has not completed.\\n\");\n\n\t/* If EEPROM is not marked present, init the PHY manually */\n\tif (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&\n\t (hw->phy.type == e1000_phy_igp_3))\n\t\te1000_phy_init_script_igp3(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_link_up_info_82575 - Get link speed/duplex info\n * @hw: pointer to the HW structure\n * @speed: stores the current speed\n * @duplex: stores the current duplex\n *\n * This is a wrapper function, if using the serial gigabit media independent\n * interface, use PCS to retrieve the link speed and duplex information.\n * Otherwise, use the generic function to get the link speed and duplex info.\n **/\nstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\tu16 *duplex)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_get_link_up_info_82575\");\n\n\tif (hw->phy.media_type != e1000_media_type_copper)\n\t\tret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,\n\t\t\t\t\t\t\t duplex);\n\telse\n\t\tret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,\n\t\t\t\t\t\t\t\t duplex);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_link_82575 - Check for link\n * @hw: pointer to the HW structure\n *\n * If sgmii is enabled, then use the pcs register to determine link, otherwise\n * use the generic interface for determining link.\n **/\nstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 speed, duplex;\n\n\tDEBUGFUNC(\"e1000_check_for_link_82575\");\n\n\tif (hw->phy.media_type != e1000_media_type_copper) {\n\t\tret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,\n\t\t\t\t\t\t\t &duplex);\n\t\t/*\n\t\t * Use this flag to determine if link needs to be checked or\n\t\t * not. If we have link clear the flag so that we do not\n\t\t * continue to check for link.\n\t\t */\n\t\thw->mac.get_link_status = !hw->mac.serdes_has_link;\n\n\t\t/*\n\t\t * Configure Flow Control now that Auto-Neg has completed.\n\t\t * First, we need to restore the desired flow control\n\t\t * settings because we may have had to re-autoneg with a\n\t\t * different link partner.\n\t\t */\n\t\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\t\tif (ret_val)\n\t\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n\t} else {\n\t\tret_val = e1000_check_for_copper_link_generic(hw);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_link_media_swap - Check which M88E1112 interface linked\n * @hw: pointer to the HW structure\n *\n * Poll the M88E1112 interfaces to see which interface achieved link.\n */\nstatic s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\tu8 port = 0;\n\n\tDEBUGFUNC(\"e1000_check_for_link_media_swap\");\n\n\t/* Check the copper medium. */\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (data & E1000_M88E1112_STATUS_LINK)\n\t\tport = E1000_MEDIA_PORT_COPPER;\n\n\t/* Check the other medium. */\n\tret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (data & E1000_M88E1112_STATUS_LINK)\n\t\tport = E1000_MEDIA_PORT_OTHER;\n\n\t/* Determine if a swap needs to happen. */\n\tif (port && (hw->dev_spec._82575.media_port != port)) {\n\t\thw->dev_spec._82575.media_port = port;\n\t\thw->dev_spec._82575.media_changed = true;\n\t} else {\n\t\tret_val = e1000_check_for_link_82575(hw);\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown\n * @hw: pointer to the HW structure\n **/\nstatic void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)\n{\n\tu32 reg;\n\n\tDEBUGFUNC(\"e1000_power_up_serdes_link_82575\");\n\n\tif ((hw->phy.media_type != e1000_media_type_internal_serdes) &&\n\t !e1000_sgmii_active_82575(hw))\n\t\treturn;\n\n\t/* Enable PCS to turn on link */\n\treg = E1000_READ_REG(hw, E1000_PCS_CFG0);\n\treg |= E1000_PCS_CFG_PCS_EN;\n\tE1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);\n\n\t/* Power up the laser */\n\treg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\treg &= ~E1000_CTRL_EXT_SDP3_DATA;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);\n\n\t/* flush the write to verify completion */\n\tE1000_WRITE_FLUSH(hw);\n\tmsec_delay(1);\n}\n\n/**\n * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex\n * @hw: pointer to the HW structure\n * @speed: stores the current speed\n * @duplex: stores the current duplex\n *\n * Using the physical coding sub-layer (PCS), retrieve the current speed and\n * duplex, then store the values in the pointers provided.\n **/\nstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,\n\t\t\t\t\t\tu16 *speed, u16 *duplex)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 pcs;\n\tu32 status;\n\n\tDEBUGFUNC(\"e1000_get_pcs_speed_and_duplex_82575\");\n\n\t/*\n\t * Read the PCS Status register for link state. For non-copper mode,\n\t * the status register is not accurate. The PCS status register is\n\t * used instead.\n\t */\n\tpcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);\n\n\t/*\n\t * The link up bit determines when link is up on autoneg.\n\t */\n\tif (pcs & E1000_PCS_LSTS_LINK_OK) {\n\t\tmac->serdes_has_link = true;\n\n\t\t/* Detect and store PCS speed */\n\t\tif (pcs & E1000_PCS_LSTS_SPEED_1000)\n\t\t\t*speed = SPEED_1000;\n\t\telse if (pcs & E1000_PCS_LSTS_SPEED_100)\n\t\t\t*speed = SPEED_100;\n\t\telse\n\t\t\t*speed = SPEED_10;\n\n\t\t/* Detect and store PCS duplex */\n\t\tif (pcs & E1000_PCS_LSTS_DUPLEX_FULL)\n\t\t\t*duplex = FULL_DUPLEX;\n\t\telse\n\t\t\t*duplex = HALF_DUPLEX;\n\n\t\t/* Check if it is an I354 2.5Gb backplane connection. */\n\t\tif (mac->type == e1000_i354) {\n\t\t\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\t\t\tif ((status & E1000_STATUS_2P5_SKU) &&\n\t\t\t !(status & E1000_STATUS_2P5_SKU_OVER)) {\n\t\t\t\t*speed = SPEED_2500;\n\t\t\t\t*duplex = FULL_DUPLEX;\n\t\t\t\tDEBUGOUT(\"2500 Mbs, \");\n\t\t\t\tDEBUGOUT(\"Full Duplex\\n\");\n\t\t\t}\n\t\t}\n\n\t} else {\n\t\tmac->serdes_has_link = false;\n\t\t*speed = 0;\n\t\t*duplex = 0;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_shutdown_serdes_link_82575 - Remove link during power down\n * @hw: pointer to the HW structure\n *\n * In the case of serdes shut down sfp and PCS on driver unload\n * when management pass thru is not enabled.\n **/\nvoid e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)\n{\n\tu32 reg;\n\n\tDEBUGFUNC(\"e1000_shutdown_serdes_link_82575\");\n\n\tif ((hw->phy.media_type != e1000_media_type_internal_serdes) &&\n\t !e1000_sgmii_active_82575(hw))\n\t\treturn;\n\n\tif (!e1000_enable_mng_pass_thru(hw)) {\n\t\t/* Disable PCS to turn off link */\n\t\treg = E1000_READ_REG(hw, E1000_PCS_CFG0);\n\t\treg &= ~E1000_PCS_CFG_PCS_EN;\n\t\tE1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);\n\n\t\t/* shutdown the laser */\n\t\treg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\treg |= E1000_CTRL_EXT_SDP3_DATA;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);\n\n\t\t/* flush the write to verify completion */\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tmsec_delay(1);\n\t}\n\n\treturn;\n}\n\n/**\n * e1000_reset_hw_82575 - Reset hardware\n * @hw: pointer to the HW structure\n *\n * This resets the hardware into a known state.\n **/\nstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_reset_hw_82575\");\n\n\t/*\n\t * Prevent the PCI-E bus from sticking if there is no TLP connection\n\t * on the last TLP read/write transaction when MAC is reset.\n\t */\n\tret_val = e1000_disable_pcie_master_generic(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"PCI-E Master disable polling has failed.\\n\");\n\n\t/* set the completion timeout for interface */\n\tret_val = e1000_set_pcie_completion_timeout(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"PCI-E Set completion timeout has failed.\\n\");\n\n\tDEBUGOUT(\"Masking off all interrupts\\n\");\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\n\tE1000_WRITE_REG(hw, E1000_RCTL, 0);\n\tE1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);\n\tE1000_WRITE_FLUSH(hw);\n\n\tmsec_delay(10);\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\tDEBUGOUT(\"Issuing a global reset to MAC\\n\");\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);\n\n\tret_val = e1000_get_auto_rd_done_generic(hw);\n\tif (ret_val) {\n\t\t/*\n\t\t * When auto config read does not complete, do not\n\t\t * return with an error. This can happen in situations\n\t\t * where there is no eeprom and prevents getting link.\n\t\t */\n\t\tDEBUGOUT(\"Auto Read Done did not complete\\n\");\n\t}\n\n\t/* If EEPROM is not present, run manual init scripts */\n\tif (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))\n\t\te1000_reset_init_script_82575(hw);\n\n\t/* Clear any pending interrupt events. */\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\tE1000_READ_REG(hw, E1000_ICR);\n\n\t/* Install any alternate MAC address into RAR0 */\n\tret_val = e1000_check_alt_mac_addr_generic(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_hw_82575 - Initialize hardware\n * @hw: pointer to the HW structure\n *\n * This inits the hardware readying it for operation.\n **/\nstatic s32 e1000_init_hw_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val;\n\tu16 i, rar_count = mac->rar_entry_count;\n\n\tDEBUGFUNC(\"e1000_init_hw_82575\");\n\n\t/* Initialize identification LED */\n\tret_val = mac->ops.id_led_init(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error initializing identification LED\\n\");\n\t\t/* This is not fatal and we should not stop init due to this */\n\t}\n\n\t/* Disabling VLAN filtering */\n\tDEBUGOUT(\"Initializing the IEEE VLAN\\n\");\n\tmac->ops.clear_vfta(hw);\n\n\t/* Setup the receive address */\n\te1000_init_rx_addrs_generic(hw, rar_count);\n\n\t/* Zero out the Multicast HASH table */\n\tDEBUGOUT(\"Zeroing the MTA\\n\");\n\tfor (i = 0; i < mac->mta_reg_count; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);\n\n\t/* Zero out the Unicast HASH table */\n\tDEBUGOUT(\"Zeroing the UTA\\n\");\n\tfor (i = 0; i < mac->uta_reg_count; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);\n\n\t/* Setup link and flow control */\n\tret_val = mac->ops.setup_link(hw);\n\n\t/* Set the default MTU size */\n\thw->dev_spec._82575.mtu = 1500;\n\n\t/*\n\t * Clear all of the statistics registers (clear on read). It is\n\t * important that we do this after we have tried to establish link\n\t * because the symbol error count will increment wildly if there\n\t * is no link.\n\t */\n\te1000_clear_hw_cntrs_82575(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_copper_link_82575 - Configure copper link settings\n * @hw: pointer to the HW structure\n *\n * Configures the link for auto-neg or forced speed and duplex. Then we check\n * for link, once link is established calls to configure collision distance\n * and flow control are called.\n **/\nstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\tu32 phpm_reg;\n\n\tDEBUGFUNC(\"e1000_setup_copper_link_82575\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= E1000_CTRL_SLU;\n\tctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\t/* Clear Go Link Disconnect bit on supported devices */\n\tswitch (hw->mac.type) {\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\tphpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);\n\t\tphpm_reg &= ~E1000_82580_PM_GO_LINKD;\n\t\tE1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tret_val = e1000_setup_serdes_link_82575(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tif (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) {\n\t\t/* allow time for SFP cage time to power up phy */\n\t\tmsec_delay(300);\n\n\t\tret_val = hw->phy.ops.reset(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error resetting the PHY.\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\tswitch (hw->phy.type) {\n\tcase e1000_phy_i210:\n\tcase e1000_phy_m88:\n\t\tswitch (hw->phy.id) {\n\t\tcase I347AT4_E_PHY_ID:\n\t\tcase M88E1112_E_PHY_ID:\n\t\tcase M88E1340M_E_PHY_ID:\n\t\tcase M88E1543_E_PHY_ID:\n\t\tcase I210_I_PHY_ID:\n\t\t\tret_val = e1000_copper_link_setup_m88_gen2(hw);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tret_val = e1000_copper_link_setup_m88(hw);\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase e1000_phy_igp_3:\n\t\tret_val = e1000_copper_link_setup_igp(hw);\n\t\tbreak;\n\tcase e1000_phy_82580:\n\t\tret_val = e1000_copper_link_setup_82577(hw);\n\t\tbreak;\n\tdefault:\n\t\tret_val = -E1000_ERR_PHY;\n\t\tbreak;\n\t}\n\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_setup_copper_link_generic(hw);\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_serdes_link_82575 - Setup link for serdes\n * @hw: pointer to the HW structure\n *\n * Configure the physical coding sub-layer (PCS) link. The PCS link is\n * used on copper connections where the serialized gigabit media independent\n * interface (sgmii), or serdes fiber is being used. Configures the link\n * for auto-negotiation or forces speed/duplex.\n **/\nstatic s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)\n{\n\tu32 ctrl_ext, ctrl_reg, reg, anadv_reg;\n\tbool pcs_autoneg;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_setup_serdes_link_82575\");\n\n\tif ((hw->phy.media_type != e1000_media_type_internal_serdes) &&\n\t !e1000_sgmii_active_82575(hw))\n\t\treturn ret_val;\n\n\t/*\n\t * On the 82575, SerDes loopback mode persists until it is\n\t * explicitly turned off or a power cycle is performed. A read to\n\t * the register does not indicate its status. Therefore, we ensure\n\t * loopback mode is disabled during initialization.\n\t */\n\tE1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);\n\n\t/* power on the sfp cage if present */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\n\tctrl_reg = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl_reg |= E1000_CTRL_SLU;\n\n\t/* set both sw defined pins on 82575/82576*/\n\tif (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)\n\t\tctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;\n\n\treg = E1000_READ_REG(hw, E1000_PCS_LCTL);\n\n\t/* default pcs_autoneg to the same setting as mac autoneg */\n\tpcs_autoneg = hw->mac.autoneg;\n\n\tswitch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {\n\tcase E1000_CTRL_EXT_LINK_MODE_SGMII:\n\t\t/* sgmii mode lets the phy handle forcing speed/duplex */\n\t\tpcs_autoneg = true;\n\t\t/* autoneg time out should be disabled for SGMII mode */\n\t\treg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);\n\t\tbreak;\n\tcase E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:\n\t\t/* disable PCS autoneg and support parallel detect only */\n\t\tpcs_autoneg = false;\n\t\t/* fall through to default case */\n\tdefault:\n\t\tif (hw->mac.type == e1000_82575 ||\n\t\t hw->mac.type == e1000_82576) {\n\t\t\tret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);\n\t\t\tif (ret_val) {\n\t\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\t\treturn ret_val;\n\t\t\t}\n\n\t\t\tif (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)\n\t\t\t\tpcs_autoneg = false;\n\t\t}\n\n\t\t/*\n\t\t * non-SGMII modes only supports a speed of 1000/Full for the\n\t\t * link so it is best to just force the MAC and let the pcs\n\t\t * link either autoneg or be forced to 1000/Full\n\t\t */\n\t\tctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |\n\t\t\t E1000_CTRL_FD | E1000_CTRL_FRCDPX;\n\n\t\t/* set speed of 1000/Full if speed/duplex is forced */\n\t\treg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;\n\t\tbreak;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);\n\n\t/*\n\t * New SerDes mode allows for forcing speed or autonegotiating speed\n\t * at 1gb. Autoneg should be default set by most drivers. This is the\n\t * mode that will be compatible with older link partners and switches.\n\t * However, both are supported by the hardware and some drivers/tools.\n\t */\n\treg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |\n\t\t E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);\n\n\tif (pcs_autoneg) {\n\t\t/* Set PCS register for autoneg */\n\t\treg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */\n\t\t E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */\n\n\t\t/* Disable force flow control for autoneg */\n\t\treg &= ~E1000_PCS_LCTL_FORCE_FCTRL;\n\n\t\t/* Configure flow control advertisement for autoneg */\n\t\tanadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);\n\t\tanadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);\n\n\t\tswitch (hw->fc.requested_mode) {\n\t\tcase e1000_fc_full:\n\t\tcase e1000_fc_rx_pause:\n\t\t\tanadv_reg |= E1000_TXCW_ASM_DIR;\n\t\t\tanadv_reg |= E1000_TXCW_PAUSE;\n\t\t\tbreak;\n\t\tcase e1000_fc_tx_pause:\n\t\t\tanadv_reg |= E1000_TXCW_ASM_DIR;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tE1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);\n\n\t\tDEBUGOUT1(\"Configuring Autoneg:PCS_LCTL=0x%08X\\n\", reg);\n\t} else {\n\t\t/* Set PCS register for forced link */\n\t\treg |= E1000_PCS_LCTL_FSD;\t/* Force Speed */\n\n\t\t/* Force flow control for forced link */\n\t\treg |= E1000_PCS_LCTL_FORCE_FCTRL;\n\n\t\tDEBUGOUT1(\"Configuring Forced Link:PCS_LCTL=0x%08X\\n\", reg);\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);\n\n\tif (!pcs_autoneg && !e1000_sgmii_active_82575(hw))\n\t\te1000_force_mac_fc_generic(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_media_type_82575 - derives current media type.\n * @hw: pointer to the HW structure\n *\n * The media type is chosen reflecting few settings.\n * The following are taken into account:\n * - link mode set in the current port Init Control Word #3\n * - current link mode settings in CSR register\n * - MDIO vs. I2C PHY control interface chosen\n * - SFP module media type\n **/\nstatic s32 e1000_get_media_type_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 ctrl_ext = 0;\n\tu32 link_mode = 0;\n\n\t/* Set internal phy as default */\n\tdev_spec->sgmii_active = false;\n\tdev_spec->module_plugged = false;\n\n\t/* Get CSR setting */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\n\t/* extract link mode setting */\n\tlink_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;\n\n\tswitch (link_mode) {\n\tcase E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:\n\t\thw->phy.media_type = e1000_media_type_internal_serdes;\n\t\tbreak;\n\tcase E1000_CTRL_EXT_LINK_MODE_GMII:\n\t\thw->phy.media_type = e1000_media_type_copper;\n\t\tbreak;\n\tcase E1000_CTRL_EXT_LINK_MODE_SGMII:\n\t\t/* Get phy control interface type set (MDIO vs. I2C)*/\n\t\tif (e1000_sgmii_uses_mdio_82575(hw)) {\n\t\t\thw->phy.media_type = e1000_media_type_copper;\n\t\t\tdev_spec->sgmii_active = true;\n\t\t\tbreak;\n\t\t}\n\t\t/* fall through for I2C based SGMII */\n\tcase E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:\n\t\t/* read media type from SFP EEPROM */\n\t\tret_val = e1000_set_sfp_media_type_82575(hw);\n\t\tif ((ret_val != E1000_SUCCESS) ||\n\t\t (hw->phy.media_type == e1000_media_type_unknown)) {\n\t\t\t/*\n\t\t\t * If media type was not identified then return media\n\t\t\t * type defined by the CTRL_EXT settings.\n\t\t\t */\n\t\t\thw->phy.media_type = e1000_media_type_internal_serdes;\n\n\t\t\tif (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {\n\t\t\t\thw->phy.media_type = e1000_media_type_copper;\n\t\t\t\tdev_spec->sgmii_active = true;\n\t\t\t}\n\n\t\t\tbreak;\n\t\t}\n\n\t\t/* do not change link mode for 100BaseFX */\n\t\tif (dev_spec->eth_flags.e100_base_fx)\n\t\t\tbreak;\n\n\t\t/* change current link mode setting */\n\t\tctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;\n\n\t\tif (hw->phy.media_type == e1000_media_type_copper)\n\t\t\tctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;\n\t\telse\n\t\t\tctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;\n\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\n\t\tbreak;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_set_sfp_media_type_82575 - derives SFP module media type.\n * @hw: pointer to the HW structure\n *\n * The media type is chosen based on SFP module.\n * compatibility flags retrieved from SFP ID EEPROM.\n **/\nstatic s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_ERR_CONFIG;\n\tu32 ctrl_ext = 0;\n\tstruct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;\n\tstruct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;\n\tu8 tranceiver_type = 0;\n\ts32 timeout = 3;\n\n\t/* Turn I2C interface ON and power on sfp cage */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);\n\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* Read SFP module data */\n\twhile (timeout) {\n\t\tret_val = e1000_read_sfp_data_byte(hw,\n\t\t\tE1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),\n\t\t\t&tranceiver_type);\n\t\tif (ret_val == E1000_SUCCESS)\n\t\t\tbreak;\n\t\tmsec_delay(100);\n\t\ttimeout--;\n\t}\n\tif (ret_val != E1000_SUCCESS)\n\t\tgoto out;\n\n\tret_val = e1000_read_sfp_data_byte(hw,\n\t\t\tE1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),\n\t\t\t(u8 *)eth_flags);\n\tif (ret_val != E1000_SUCCESS)\n\t\tgoto out;\n\n\t/* Check if there is some SFP module plugged and powered */\n\tif ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||\n\t (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {\n\t\tdev_spec->module_plugged = true;\n\t\tif (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {\n\t\t\thw->phy.media_type = e1000_media_type_internal_serdes;\n\t\t} else if (eth_flags->e100_base_fx) {\n\t\t\tdev_spec->sgmii_active = true;\n\t\t\thw->phy.media_type = e1000_media_type_internal_serdes;\n\t\t} else if (eth_flags->e1000_base_t) {\n\t\t\tdev_spec->sgmii_active = true;\n\t\t\thw->phy.media_type = e1000_media_type_copper;\n\t\t} else {\n\t\t\thw->phy.media_type = e1000_media_type_unknown;\n\t\t\tDEBUGOUT(\"PHY module has not been recognized\\n\");\n\t\t\tgoto out;\n\t\t}\n\t} else {\n\t\thw->phy.media_type = e1000_media_type_unknown;\n\t}\n\tret_val = E1000_SUCCESS;\nout:\n\t/* Restore I2C interface setting */\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\treturn ret_val;\n}\n\n/**\n * e1000_valid_led_default_82575 - Verify a valid default LED config\n * @hw: pointer to the HW structure\n * @data: pointer to the NVM (EEPROM)\n *\n * Read the EEPROM for the current default LED configuration. If the\n * LED configuration is not valid, set to a valid LED configuration.\n **/\nstatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_valid_led_default_82575\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\tgoto out;\n\t}\n\n\tif (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {\n\t\tswitch (hw->phy.media_type) {\n\t\tcase e1000_media_type_internal_serdes:\n\t\t\t*data = ID_LED_DEFAULT_82575_SERDES;\n\t\t\tbreak;\n\t\tcase e1000_media_type_copper:\n\t\tdefault:\n\t\t\t*data = ID_LED_DEFAULT;\n\t\t\tbreak;\n\t\t}\n\t}\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_sgmii_active_82575 - Return sgmii state\n * @hw: pointer to the HW structure\n *\n * 82575 silicon has a serialized gigabit media independent interface (sgmii)\n * which can be enabled for use in the embedded applications. Simply\n * return the current state of the sgmii interface.\n **/\nstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;\n\treturn dev_spec->sgmii_active;\n}\n\n/**\n * e1000_reset_init_script_82575 - Inits HW defaults after reset\n * @hw: pointer to the HW structure\n *\n * Inits recommended HW defaults after a reset when there is no EEPROM\n * detected. This is only for the 82575.\n **/\nstatic s32 e1000_reset_init_script_82575(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_reset_init_script_82575\");\n\n\tif (hw->mac.type == e1000_82575) {\n\t\tDEBUGOUT(\"Running reset init script for 82575\\n\");\n\t\t/* SerDes configuration via SERDESCTRL */\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);\n\n\t\t/* CCM configuration via CCMCTL register */\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);\n\n\t\t/* PCIe lanes configuration */\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);\n\n\t\t/* PCIe PLL Configuration */\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);\n\t\te1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_mac_addr_82575 - Read device MAC address\n * @hw: pointer to the HW structure\n **/\nstatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_read_mac_addr_82575\");\n\n\t/*\n\t * If there's an alternate MAC address place it in RAR0\n\t * so that it will override the Si installed default perm\n\t * address.\n\t */\n\tret_val = e1000_check_alt_mac_addr_generic(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_read_mac_addr_generic(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_config_collision_dist_82575 - Configure collision distance\n * @hw: pointer to the HW structure\n *\n * Configures the collision distance to the default value and is used\n * during link setup.\n **/\nstatic void e1000_config_collision_dist_82575(struct e1000_hw *hw)\n{\n\tu32 tctl_ext;\n\n\tDEBUGFUNC(\"e1000_config_collision_dist_82575\");\n\n\ttctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);\n\n\ttctl_ext &= ~E1000_TCTL_EXT_COLD;\n\ttctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;\n\n\tE1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * e1000_power_down_phy_copper_82575 - Remove link during PHY power down\n * @hw: pointer to the HW structure\n *\n * In the case of a PHY power down to save power, or to turn off link during a\n * driver unload, or wake on lan is not enabled, remove the link.\n **/\nstatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\n\tif (!(phy->ops.check_reset_block))\n\t\treturn;\n\n\t/* If the management interface is not enabled, then power down */\n\tif (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))\n\t\te1000_power_down_phy_copper(hw);\n\n\treturn;\n}\n\n/**\n * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters\n * @hw: pointer to the HW structure\n *\n * Clears the hardware counters by reading the counter registers.\n **/\nstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_clear_hw_cntrs_82575\");\n\n\te1000_clear_hw_cntrs_base_generic(hw);\n\n\tE1000_READ_REG(hw, E1000_PRC64);\n\tE1000_READ_REG(hw, E1000_PRC127);\n\tE1000_READ_REG(hw, E1000_PRC255);\n\tE1000_READ_REG(hw, E1000_PRC511);\n\tE1000_READ_REG(hw, E1000_PRC1023);\n\tE1000_READ_REG(hw, E1000_PRC1522);\n\tE1000_READ_REG(hw, E1000_PTC64);\n\tE1000_READ_REG(hw, E1000_PTC127);\n\tE1000_READ_REG(hw, E1000_PTC255);\n\tE1000_READ_REG(hw, E1000_PTC511);\n\tE1000_READ_REG(hw, E1000_PTC1023);\n\tE1000_READ_REG(hw, E1000_PTC1522);\n\n\tE1000_READ_REG(hw, E1000_ALGNERRC);\n\tE1000_READ_REG(hw, E1000_RXERRC);\n\tE1000_READ_REG(hw, E1000_TNCRS);\n\tE1000_READ_REG(hw, E1000_CEXTERR);\n\tE1000_READ_REG(hw, E1000_TSCTC);\n\tE1000_READ_REG(hw, E1000_TSCTFC);\n\n\tE1000_READ_REG(hw, E1000_MGTPRC);\n\tE1000_READ_REG(hw, E1000_MGTPDC);\n\tE1000_READ_REG(hw, E1000_MGTPTC);\n\n\tE1000_READ_REG(hw, E1000_IAC);\n\tE1000_READ_REG(hw, E1000_ICRXOC);\n\n\tE1000_READ_REG(hw, E1000_ICRXPTC);\n\tE1000_READ_REG(hw, E1000_ICRXATC);\n\tE1000_READ_REG(hw, E1000_ICTXPTC);\n\tE1000_READ_REG(hw, E1000_ICTXATC);\n\tE1000_READ_REG(hw, E1000_ICTXQEC);\n\tE1000_READ_REG(hw, E1000_ICTXQMTC);\n\tE1000_READ_REG(hw, E1000_ICRXDMTC);\n\n\tE1000_READ_REG(hw, E1000_CBTMPC);\n\tE1000_READ_REG(hw, E1000_HTDPMC);\n\tE1000_READ_REG(hw, E1000_CBRMPC);\n\tE1000_READ_REG(hw, E1000_RPTHC);\n\tE1000_READ_REG(hw, E1000_HGPTC);\n\tE1000_READ_REG(hw, E1000_HTCBDPC);\n\tE1000_READ_REG(hw, E1000_HGORCL);\n\tE1000_READ_REG(hw, E1000_HGORCH);\n\tE1000_READ_REG(hw, E1000_HGOTCL);\n\tE1000_READ_REG(hw, E1000_HGOTCH);\n\tE1000_READ_REG(hw, E1000_LENERRS);\n\n\t/* This register should not be read in copper configurations */\n\tif ((hw->phy.media_type == e1000_media_type_internal_serdes) ||\n\t e1000_sgmii_active_82575(hw))\n\t\tE1000_READ_REG(hw, E1000_SCVPC);\n}\n\n/**\n * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable\n * @hw: pointer to the HW structure\n *\n * After rx enable if managability is enabled then there is likely some\n * bad data at the start of the fifo and possibly in the DMA fifo. This\n * function clears the fifos and flushes any packets that came in as rx was\n * being enabled.\n **/\nvoid e1000_rx_fifo_flush_82575(struct e1000_hw *hw)\n{\n\tu32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;\n\tint i, ms_wait;\n\n\tDEBUGFUNC(\"e1000_rx_fifo_workaround_82575\");\n\tif (hw->mac.type != e1000_82575 ||\n\t !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))\n\t\treturn;\n\n\t/* Disable all Rx queues */\n\tfor (i = 0; i < 4; i++) {\n\t\trxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));\n\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(i),\n\t\t\t\trxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);\n\t}\n\t/* Poll all queues to verify they have shut down */\n\tfor (ms_wait = 0; ms_wait < 10; ms_wait++) {\n\t\tmsec_delay(1);\n\t\trx_enabled = 0;\n\t\tfor (i = 0; i < 4; i++)\n\t\t\trx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));\n\t\tif (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))\n\t\t\tbreak;\n\t}\n\n\tif (ms_wait == 10)\n\t\tDEBUGOUT(\"Queue disable timed out after 10ms\\n\");\n\n\t/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all\n\t * incoming packets are rejected. Set enable and wait 2ms so that\n\t * any packet that was coming in as RCTL.EN was set is flushed\n\t */\n\trfctl = E1000_READ_REG(hw, E1000_RFCTL);\n\tE1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);\n\n\trlpml = E1000_READ_REG(hw, E1000_RLPML);\n\tE1000_WRITE_REG(hw, E1000_RLPML, 0);\n\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\ttemp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);\n\ttemp_rctl |= E1000_RCTL_LPE;\n\n\tE1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);\n\tE1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);\n\tE1000_WRITE_FLUSH(hw);\n\tmsec_delay(2);\n\n\t/* Enable Rx queues that were previously enabled and restore our\n\t * previous state\n\t */\n\tfor (i = 0; i < 4; i++)\n\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\tE1000_WRITE_FLUSH(hw);\n\n\tE1000_WRITE_REG(hw, E1000_RLPML, rlpml);\n\tE1000_WRITE_REG(hw, E1000_RFCTL, rfctl);\n\n\t/* Flush receive errors generated by workaround */\n\tE1000_READ_REG(hw, E1000_ROC);\n\tE1000_READ_REG(hw, E1000_RNBC);\n\tE1000_READ_REG(hw, E1000_MPC);\n}\n\n/**\n * e1000_set_pcie_completion_timeout - set pci-e completion timeout\n * @hw: pointer to the HW structure\n *\n * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,\n * however the hardware default for these parts is 500us to 1ms which is less\n * than the 10ms recommended by the pci-e spec. To address this we need to\n * increase the value to either 10ms to 200ms for capability version 1 config,\n * or 16ms to 55ms for version 2.\n **/\nstatic s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)\n{\n\tu32 gcr = E1000_READ_REG(hw, E1000_GCR);\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 pcie_devctl2;\n\n\t/* only take action if timeout value is defaulted to 0 */\n\tif (gcr & E1000_GCR_CMPL_TMOUT_MASK)\n\t\tgoto out;\n\n\t/*\n\t * if capababilities version is type 1 we can write the\n\t * timeout of 10ms to 200ms through the GCR register\n\t */\n\tif (!(gcr & E1000_GCR_CAP_VER2)) {\n\t\tgcr |= E1000_GCR_CMPL_TMOUT_10ms;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * for version 2 capabilities we need to write the config space\n\t * directly in order to set the completion timeout value for\n\t * 16ms to 55ms\n\t */\n\tret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,\n\t\t\t\t\t &pcie_devctl2);\n\tif (ret_val)\n\t\tgoto out;\n\n\tpcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;\n\n\tret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,\n\t\t\t\t\t &pcie_devctl2);\nout:\n\t/* disable completion timeout resend */\n\tgcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;\n\n\tE1000_WRITE_REG(hw, E1000_GCR, gcr);\n\treturn ret_val;\n}\n\n/**\n * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing\n * @hw: pointer to the hardware struct\n * @enable: state to enter, either enabled or disabled\n * @pf: Physical Function pool - do not set anti-spoofing for the PF\n *\n * enables/disables L2 switch anti-spoofing functionality.\n **/\nvoid e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)\n{\n\tu32 reg_val, reg_offset;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82576:\n\t\treg_offset = E1000_DTXSWC;\n\t\tbreak;\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\treg_offset = E1000_TXSWC;\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\treg_val = E1000_READ_REG(hw, reg_offset);\n\tif (enable) {\n\t\treg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |\n\t\t\t E1000_DTXSWC_VLAN_SPOOF_MASK);\n\t\t/* The PF can spoof - it has to in order to\n\t\t * support emulation mode NICs\n\t\t */\n\t\treg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));\n\t} else {\n\t\treg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |\n\t\t\t E1000_DTXSWC_VLAN_SPOOF_MASK);\n\t}\n\tE1000_WRITE_REG(hw, reg_offset, reg_val);\n}\n\n/**\n * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback\n * @hw: pointer to the hardware struct\n * @enable: state to enter, either enabled or disabled\n *\n * enables/disables L2 switch loopback functionality.\n **/\nvoid e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)\n{\n\tu32 dtxswc;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82576:\n\t\tdtxswc = E1000_READ_REG(hw, E1000_DTXSWC);\n\t\tif (enable)\n\t\t\tdtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;\n\t\telse\n\t\t\tdtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;\n\t\tE1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);\n\t\tbreak;\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\tdtxswc = E1000_READ_REG(hw, E1000_TXSWC);\n\t\tif (enable)\n\t\t\tdtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;\n\t\telse\n\t\t\tdtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;\n\t\tE1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);\n\t\tbreak;\n\tdefault:\n\t\t/* Currently no other hardware supports loopback */\n\t\tbreak;\n\t}\n\n\n}\n\n/**\n * e1000_vmdq_set_replication_pf - enable or disable vmdq replication\n * @hw: pointer to the hardware struct\n * @enable: state to enter, either enabled or disabled\n *\n * enables/disables replication of packets across multiple pools.\n **/\nvoid e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)\n{\n\tu32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);\n\n\tif (enable)\n\t\tvt_ctl |= E1000_VT_CTL_VM_REPL_EN;\n\telse\n\t\tvt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;\n\n\tE1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);\n}\n\n/**\n * e1000_read_phy_reg_82580 - Read 82580 MDI control register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the MDI control register in the PHY at offset and stores the\n * information read to data.\n **/\nstatic s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_82580\");\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_read_phy_reg_mdic(hw, offset, data);\n\n\thw->phy.ops.release(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_write_phy_reg_82580 - Write 82580 MDI control register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write to register at offset\n *\n * Writes data to MDI control register in the PHY at offset.\n **/\nstatic s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_82580\");\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\tgoto out;\n\n\tret_val = e1000_write_phy_reg_mdic(hw, offset, data);\n\n\thw->phy.ops.release(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits\n * @hw: pointer to the HW structure\n *\n * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on\n * the values found in the EEPROM. This addresses an issue in which these\n * bits are not restored from EEPROM after reset.\n **/\nstatic s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 mdicnfg;\n\tu16 nvm_data = 0;\n\n\tDEBUGFUNC(\"e1000_reset_mdicnfg_82580\");\n\n\tif (hw->mac.type != e1000_82580)\n\t\tgoto out;\n\tif (!e1000_sgmii_active_82575(hw))\n\t\tgoto out;\n\n\tret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +\n\t\t\t\t NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,\n\t\t\t\t &nvm_data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\tgoto out;\n\t}\n\n\tmdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);\n\tif (nvm_data & NVM_WORD24_EXT_MDIO)\n\t\tmdicnfg |= E1000_MDICNFG_EXT_MDIO;\n\tif (nvm_data & NVM_WORD24_COM_MDIO)\n\t\tmdicnfg |= E1000_MDICNFG_COM_MDIO;\n\tE1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_reset_hw_82580 - Reset hardware\n * @hw: pointer to the HW structure\n *\n * This resets function or entire device (all ports, etc.)\n * to a known state.\n **/\nstatic s32 e1000_reset_hw_82580(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\t/* BH SW mailbox bit in SW_FW_SYNC */\n\tu16 swmbsw_mask = E1000_SW_SYNCH_MB;\n\tu32 ctrl;\n\tbool global_device_reset = hw->dev_spec._82575.global_device_reset;\n\n\tDEBUGFUNC(\"e1000_reset_hw_82580\");\n\n\thw->dev_spec._82575.global_device_reset = false;\n\n\t/* 82580 does not reliably do global_device_reset due to hw errata */\n\tif (hw->mac.type == e1000_82580)\n\t\tglobal_device_reset = false;\n\n\t/* Get current control state. */\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\t/*\n\t * Prevent the PCI-E bus from sticking if there is no TLP connection\n\t * on the last TLP read/write transaction when MAC is reset.\n\t */\n\tret_val = e1000_disable_pcie_master_generic(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"PCI-E Master disable polling has failed.\\n\");\n\n\tDEBUGOUT(\"Masking off all interrupts\\n\");\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\tE1000_WRITE_REG(hw, E1000_RCTL, 0);\n\tE1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);\n\tE1000_WRITE_FLUSH(hw);\n\n\tmsec_delay(10);\n\n\t/* Determine whether or not a global dev reset is requested */\n\tif (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,\n\t swmbsw_mask))\n\t\t\tglobal_device_reset = false;\n\n\tif (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &\n\t E1000_STAT_DEV_RST_SET))\n\t\tctrl |= E1000_CTRL_DEV_RST;\n\telse\n\t\tctrl |= E1000_CTRL_RST;\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* Add delay to insure DEV_RST has time to complete */\n\tif (global_device_reset)\n\t\tmsec_delay(5);\n\n\tret_val = e1000_get_auto_rd_done_generic(hw);\n\tif (ret_val) {\n\t\t/*\n\t\t * When auto config read does not complete, do not\n\t\t * return with an error. This can happen in situations\n\t\t * where there is no eeprom and prevents getting link.\n\t\t */\n\t\tDEBUGOUT(\"Auto Read Done did not complete\\n\");\n\t}\n\n\t/* clear global device reset status bit */\n\tE1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);\n\n\t/* Clear any pending interrupt events. */\n\tE1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);\n\tE1000_READ_REG(hw, E1000_ICR);\n\n\tret_val = e1000_reset_mdicnfg_82580(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"Could not reset MDICNFG based on EEPROM\\n\");\n\n\t/* Install any alternate MAC address into RAR0 */\n\tret_val = e1000_check_alt_mac_addr_generic(hw);\n\n\t/* Release semaphore */\n\tif (global_device_reset)\n\t\thw->mac.ops.release_swfw_sync(hw, swmbsw_mask);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size\n * @data: data received by reading RXPBS register\n *\n * The 82580 uses a table based approach for packet buffer allocation sizes.\n * This function converts the retrieved value into the correct table value\n * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7\n * 0x0 36 72 144 1 2 4 8 16\n * 0x8 35 70 140 rsv rsv rsv rsv rsv\n */\nu16 e1000_rxpbs_adjust_82580(u32 data)\n{\n\tu16 ret_val = 0;\n\n\tif (data < E1000_82580_RXPBS_TABLE_SIZE)\n\t\tret_val = e1000_82580_rxpbs_table[data];\n\n\treturn ret_val;\n}\n\n/**\n * e1000_validate_nvm_checksum_with_offset - Validate EEPROM\n * checksum\n * @hw: pointer to the HW structure\n * @offset: offset in words of the checksum protected region\n *\n * Calculates the EEPROM checksum by reading/adding each word of the EEPROM\n * and then verifies that the sum of the EEPROM is equal to 0xBABA.\n **/\ns32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 checksum = 0;\n\tu16 i, nvm_data;\n\n\tDEBUGFUNC(\"e1000_validate_nvm_checksum_with_offset\");\n\n\tfor (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {\n\t\tret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\tgoto out;\n\t\t}\n\t\tchecksum += nvm_data;\n\t}\n\n\tif (checksum != (u16) NVM_SUM) {\n\t\tDEBUGOUT(\"NVM Checksum Invalid\\n\");\n\t\tret_val = -E1000_ERR_NVM;\n\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_update_nvm_checksum_with_offset - Update EEPROM\n * checksum\n * @hw: pointer to the HW structure\n * @offset: offset in words of the checksum protected region\n *\n * Updates the EEPROM checksum by reading/adding each word of the EEPROM\n * up to the checksum. Then calculates the EEPROM checksum and writes the\n * value to the EEPROM.\n **/\ns32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)\n{\n\ts32 ret_val;\n\tu16 checksum = 0;\n\tu16 i, nvm_data;\n\n\tDEBUGFUNC(\"e1000_update_nvm_checksum_with_offset\");\n\n\tfor (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {\n\t\tret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error while updating checksum.\\n\");\n\t\t\tgoto out;\n\t\t}\n\t\tchecksum += nvm_data;\n\t}\n\tchecksum = (u16) NVM_SUM - checksum;\n\tret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,\n\t\t\t\t &checksum);\n\tif (ret_val)\n\t\tDEBUGOUT(\"NVM Write Error while updating checksum.\\n\");\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Calculates the EEPROM section checksum by reading/adding each word of\n * the EEPROM and then verifies that the sum of the EEPROM is\n * equal to 0xBABA.\n **/\nstatic s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 eeprom_regions_count = 1;\n\tu16 j, nvm_data;\n\tu16 nvm_offset;\n\n\tDEBUGFUNC(\"e1000_validate_nvm_checksum_82580\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\tgoto out;\n\t}\n\n\tif (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {\n\t\t/* if chekcsums compatibility bit is set validate checksums\n\t\t * for all 4 ports. */\n\t\teeprom_regions_count = 4;\n\t}\n\n\tfor (j = 0; j < eeprom_regions_count; j++) {\n\t\tnvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);\n\t\tret_val = e1000_validate_nvm_checksum_with_offset(hw,\n\t\t\t\t\t\t\t\t nvm_offset);\n\t\tif (ret_val != E1000_SUCCESS)\n\t\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_update_nvm_checksum_82580 - Update EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Updates the EEPROM section checksums for all 4 ports by reading/adding\n * each word of the EEPROM up to the checksum. Then calculates the EEPROM\n * checksum and writes the value to the EEPROM.\n **/\nstatic s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 j, nvm_data;\n\tu16 nvm_offset;\n\n\tDEBUGFUNC(\"e1000_update_nvm_checksum_82580\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error while updating checksum compatibility bit.\\n\");\n\t\tgoto out;\n\t}\n\n\tif (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {\n\t\t/* set compatibility bit to validate checksums appropriately */\n\t\tnvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;\n\t\tret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,\n\t\t\t\t\t &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Write Error while updating checksum compatibility bit.\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\n\tfor (j = 0; j < 4; j++) {\n\t\tnvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);\n\t\tret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Calculates the EEPROM section checksum by reading/adding each word of\n * the EEPROM and then verifies that the sum of the EEPROM is\n * equal to 0xBABA.\n **/\nstatic s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 j;\n\tu16 nvm_offset;\n\n\tDEBUGFUNC(\"e1000_validate_nvm_checksum_i350\");\n\n\tfor (j = 0; j < 4; j++) {\n\t\tnvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);\n\t\tret_val = e1000_validate_nvm_checksum_with_offset(hw,\n\t\t\t\t\t\t\t\t nvm_offset);\n\t\tif (ret_val != E1000_SUCCESS)\n\t\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_update_nvm_checksum_i350 - Update EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Updates the EEPROM section checksums for all 4 ports by reading/adding\n * each word of the EEPROM up to the checksum. Then calculates the EEPROM\n * checksum and writes the value to the EEPROM.\n **/\nstatic s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 j;\n\tu16 nvm_offset;\n\n\tDEBUGFUNC(\"e1000_update_nvm_checksum_i350\");\n\n\tfor (j = 0; j < 4; j++) {\n\t\tnvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);\n\t\tret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);\n\t\tif (ret_val != E1000_SUCCESS)\n\t\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * __e1000_access_emi_reg - Read/write EMI register\n * @hw: pointer to the HW structure\n * @addr: EMI address to program\n * @data: pointer to value to read/write from/to the EMI address\n * @read: boolean flag to indicate read or write\n **/\nstatic s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,\n\t\t\t\t u16 *data, bool read)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"__e1000_access_emi_reg\");\n\n\tret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (read)\n\t\tret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);\n\telse\n\t\tret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_emi_reg - Read Extended Management Interface register\n * @hw: pointer to the HW structure\n * @addr: EMI address to program\n * @data: value to be read from the EMI address\n **/\ns32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)\n{\n\tDEBUGFUNC(\"e1000_read_emi_reg\");\n\n\treturn __e1000_access_emi_reg(hw, addr, data, true);\n}\n\n/**\n * e1000_set_eee_i350 - Enable/disable EEE support\n * @hw: pointer to the HW structure\n *\n * Enable/disable EEE based on setting in dev_spec structure.\n *\n **/\ns32 e1000_set_eee_i350(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 ipcnfg, eeer;\n\n\tDEBUGFUNC(\"e1000_set_eee_i350\");\n\n\tif ((hw->mac.type < e1000_i350) ||\n\t (hw->phy.media_type != e1000_media_type_copper))\n\t\tgoto out;\n\tipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);\n\teeer = E1000_READ_REG(hw, E1000_EEER);\n\n\t/* enable or disable per user setting */\n\tif (!(hw->dev_spec._82575.eee_disable)) {\n\t\tu32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);\n\n\t\tipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);\n\t\teeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |\n\t\t\t E1000_EEER_LPI_FC);\n\n\t\t/* This bit should not be set in normal operation. */\n\t\tif (eee_su & E1000_EEE_SU_LPI_CLK_STP)\n\t\t\tDEBUGOUT(\"LPI Clock Stop Bit should not be set!\\n\");\n\t} else {\n\t\tipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);\n\t\teeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |\n\t\t\t E1000_EEER_LPI_FC);\n\t}\n\tE1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);\n\tE1000_WRITE_REG(hw, E1000_EEER, eeer);\n\tE1000_READ_REG(hw, E1000_IPCNFG);\n\tE1000_READ_REG(hw, E1000_EEER);\nout:\n\n\treturn ret_val;\n}\n\n/**\n * e1000_set_eee_i354 - Enable/disable EEE support\n * @hw: pointer to the HW structure\n *\n * Enable/disable EEE legacy mode based on setting in dev_spec structure.\n *\n **/\ns32 e1000_set_eee_i354(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_set_eee_i354\");\n\n\tif ((hw->phy.media_type != e1000_media_type_copper) ||\n\t ((phy->id != M88E1543_E_PHY_ID)))\n\t\tgoto out;\n\n\tif (!hw->dev_spec._82575.eee_disable) {\n\t\t/* Switch to PHY page 18. */\n\t\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tphy_data |= E1000_M88E1543_EEE_CTRL_1_MS;\n\t\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,\n\t\t\t\t\t phy_data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\t/* Return the PHY to page 0. */\n\t\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\t/* Turn on EEE advertisement. */\n\t\tret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,\n\t\t\t\t\t E1000_EEE_ADV_DEV_I354,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tphy_data |= E1000_EEE_ADV_100_SUPPORTED |\n\t\t\t E1000_EEE_ADV_1000_SUPPORTED;\n\t\tret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,\n\t\t\t\t\t\tE1000_EEE_ADV_DEV_I354,\n\t\t\t\t\t\tphy_data);\n\t} else {\n\t\t/* Turn off EEE advertisement. */\n\t\tret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,\n\t\t\t\t\t E1000_EEE_ADV_DEV_I354,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tphy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |\n\t\t\t E1000_EEE_ADV_1000_SUPPORTED);\n\t\tret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,\n\t\t\t\t\t\tE1000_EEE_ADV_DEV_I354,\n\t\t\t\t\t\tphy_data);\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_get_eee_status_i354 - Get EEE status\n * @hw: pointer to the HW structure\n * @status: EEE status\n *\n * Get EEE status by guessing based on whether Tx or Rx LPI indications have\n * been received.\n **/\ns32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_get_eee_status_i354\");\n\n\t/* Check if EEE is supported on this device. */\n\tif ((hw->phy.media_type != e1000_media_type_copper) ||\n\t ((phy->id != M88E1543_E_PHY_ID)))\n\t\tgoto out;\n\n\tret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,\n\t\t\t\t E1000_PCS_STATUS_DEV_I354,\n\t\t\t\t &phy_data);\n\tif (ret_val)\n\t\tgoto out;\n\n\t*status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |\n\t\t\t E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;\n\nout:\n\treturn ret_val;\n}\n\n/* Due to a hw errata, if the host tries to configure the VFTA register\n * while performing queries from the BMC or DMA, then the VFTA in some\n * cases won't be written.\n */\n\n/**\n * e1000_clear_vfta_i350 - Clear VLAN filter table\n * @hw: pointer to the HW structure\n *\n * Clears the register array which contains the VLAN filter table by\n * setting all the values to 0.\n **/\nvoid e1000_clear_vfta_i350(struct e1000_hw *hw)\n{\n\tu32 offset;\n\tint i;\n\n\tDEBUGFUNC(\"e1000_clear_vfta_350\");\n\n\tfor (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {\n\t\tfor (i = 0; i < 10; i++)\n\t\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);\n\n\t\tE1000_WRITE_FLUSH(hw);\n\t}\n}\n\n/**\n * e1000_write_vfta_i350 - Write value to VLAN filter table\n * @hw: pointer to the HW structure\n * @offset: register offset in VLAN filter table\n * @value: register value written to VLAN filter table\n *\n * Writes value at the given offset in the register array which stores\n * the VLAN filter table.\n **/\nvoid e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)\n{\n\tint i;\n\n\tDEBUGFUNC(\"e1000_write_vfta_350\");\n\n\tfor (i = 0; i < 10; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);\n\n\tE1000_WRITE_FLUSH(hw);\n}\n\n\n/**\n * e1000_set_i2c_bb - Enable I2C bit-bang\n * @hw: pointer to the HW structure\n *\n * Enable I2C bit-bang interface\n *\n **/\ns32 e1000_set_i2c_bb(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 ctrl_ext, i2cparams;\n\n\tDEBUGFUNC(\"e1000_set_i2c_bb\");\n\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tctrl_ext |= E1000_CTRL_I2C_ENA;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\tE1000_WRITE_FLUSH(hw);\n\n\ti2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\ti2cparams |= E1000_I2CBB_EN;\n\ti2cparams |= E1000_I2C_DATA_OE_N;\n\ti2cparams |= E1000_I2C_CLK_OE_N;\n\tE1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);\n\tE1000_WRITE_FLUSH(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to read\n * @dev_addr: device address\n * @data: value read\n *\n * Performs byte read operation over I2C interface at\n * a specified device address.\n **/\ns32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t\tu8 dev_addr, u8 *data)\n{\n\ts32 status = E1000_SUCCESS;\n\tu32 max_retry = 10;\n\tu32 retry = 1;\n\tu16 swfw_mask = 0;\n\n\tbool nack = true;\n\n\tDEBUGFUNC(\"e1000_read_i2c_byte_generic\");\n\n\tswfw_mask = E1000_SWFW_PHY0_SM;\n\n\tdo {\n\t\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)\n\t\t != E1000_SUCCESS) {\n\t\t\tstatus = E1000_ERR_SWFW_SYNC;\n\t\t\tgoto read_byte_out;\n\t\t}\n\n\t\te1000_i2c_start(hw);\n\n\t\t/* Device Address and write indication */\n\t\tstatus = e1000_clock_out_i2c_byte(hw, dev_addr);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_get_i2c_ack(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_clock_out_i2c_byte(hw, byte_offset);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_get_i2c_ack(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\te1000_i2c_start(hw);\n\n\t\t/* Device Address and read indication */\n\t\tstatus = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_get_i2c_ack(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_clock_in_i2c_byte(hw, data);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_clock_out_i2c_bit(hw, nack);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\te1000_i2c_stop(hw);\n\t\tbreak;\n\nfail:\n\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\t\tmsec_delay(100);\n\t\te1000_i2c_bus_clear(hw);\n\t\tretry++;\n\t\tif (retry < max_retry)\n\t\t\tDEBUGOUT(\"I2C byte read error - Retrying.\\n\");\n\t\telse\n\t\t\tDEBUGOUT(\"I2C byte read error.\\n\");\n\n\t} while (retry < max_retry);\n\n\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\nread_byte_out:\n\n\treturn status;\n}\n\n/**\n * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @dev_addr: device address\n * @data: value to write\n *\n * Performs byte write operation over I2C interface at\n * a specified device address.\n **/\ns32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data)\n{\n\ts32 status = E1000_SUCCESS;\n\tu32 max_retry = 1;\n\tu32 retry = 0;\n\tu16 swfw_mask = 0;\n\n\tDEBUGFUNC(\"e1000_write_i2c_byte_generic\");\n\n\tswfw_mask = E1000_SWFW_PHY0_SM;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {\n\t\tstatus = E1000_ERR_SWFW_SYNC;\n\t\tgoto write_byte_out;\n\t}\n\n\tdo {\n\t\te1000_i2c_start(hw);\n\n\t\tstatus = e1000_clock_out_i2c_byte(hw, dev_addr);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_get_i2c_ack(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_clock_out_i2c_byte(hw, byte_offset);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_get_i2c_ack(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_clock_out_i2c_byte(hw, data);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\tstatus = e1000_get_i2c_ack(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\tgoto fail;\n\n\t\te1000_i2c_stop(hw);\n\t\tbreak;\n\nfail:\n\t\te1000_i2c_bus_clear(hw);\n\t\tretry++;\n\t\tif (retry < max_retry)\n\t\t\tDEBUGOUT(\"I2C byte write error - Retrying.\\n\");\n\t\telse\n\t\t\tDEBUGOUT(\"I2C byte write error.\\n\");\n\t} while (retry < max_retry);\n\n\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\nwrite_byte_out:\n\n\treturn status;\n}\n\n/**\n * e1000_i2c_start - Sets I2C start condition\n * @hw: pointer to hardware structure\n *\n * Sets I2C start condition (High -> Low on SDA while SCL is High)\n **/\nstatic void e1000_i2c_start(struct e1000_hw *hw)\n{\n\tu32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\tDEBUGFUNC(\"e1000_i2c_start\");\n\n\t/* Start condition must begin with data and clock high */\n\te1000_set_i2c_data(hw, &i2cctl, 1);\n\te1000_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Setup time for start condition (4.7us) */\n\tusec_delay(E1000_I2C_T_SU_STA);\n\n\te1000_set_i2c_data(hw, &i2cctl, 0);\n\n\t/* Hold time for start condition (4us) */\n\tusec_delay(E1000_I2C_T_HD_STA);\n\n\te1000_lower_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum low period of clock is 4.7 us */\n\tusec_delay(E1000_I2C_T_LOW);\n\n}\n\n/**\n * e1000_i2c_stop - Sets I2C stop condition\n * @hw: pointer to hardware structure\n *\n * Sets I2C stop condition (Low -> High on SDA while SCL is High)\n **/\nstatic void e1000_i2c_stop(struct e1000_hw *hw)\n{\n\tu32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\tDEBUGFUNC(\"e1000_i2c_stop\");\n\n\t/* Stop condition must begin with data low and clock high */\n\te1000_set_i2c_data(hw, &i2cctl, 0);\n\te1000_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Setup time for stop condition (4us) */\n\tusec_delay(E1000_I2C_T_SU_STO);\n\n\te1000_set_i2c_data(hw, &i2cctl, 1);\n\n\t/* bus free time between stop and start (4.7us)*/\n\tusec_delay(E1000_I2C_T_BUF);\n}\n\n/**\n * e1000_clock_in_i2c_byte - Clocks in one byte via I2C\n * @hw: pointer to hardware structure\n * @data: data byte to clock in\n *\n * Clocks in one byte data via I2C data/clock\n **/\nstatic s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)\n{\n\ts32 i;\n\tbool bit = 0;\n\n\tDEBUGFUNC(\"e1000_clock_in_i2c_byte\");\n\n\t*data = 0;\n\tfor (i = 7; i >= 0; i--) {\n\t\te1000_clock_in_i2c_bit(hw, &bit);\n\t\t*data |= bit << i;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_clock_out_i2c_byte - Clocks out one byte via I2C\n * @hw: pointer to hardware structure\n * @data: data byte clocked out\n *\n * Clocks out one byte data via I2C data/clock\n **/\nstatic s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)\n{\n\ts32 status = E1000_SUCCESS;\n\ts32 i;\n\tu32 i2cctl;\n\tbool bit = 0;\n\n\tDEBUGFUNC(\"e1000_clock_out_i2c_byte\");\n\n\tfor (i = 7; i >= 0; i--) {\n\t\tbit = (data >> i) & 0x1;\n\t\tstatus = e1000_clock_out_i2c_bit(hw, bit);\n\n\t\tif (status != E1000_SUCCESS)\n\t\t\tbreak;\n\t}\n\n\t/* Release SDA line (set high) */\n\ti2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\ti2cctl |= E1000_I2C_DATA_OE_N;\n\tE1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);\n\tE1000_WRITE_FLUSH(hw);\n\n\treturn status;\n}\n\n/**\n * e1000_get_i2c_ack - Polls for I2C ACK\n * @hw: pointer to hardware structure\n *\n * Clocks in/out one bit via I2C data/clock\n **/\nstatic s32 e1000_get_i2c_ack(struct e1000_hw *hw)\n{\n\ts32 status = E1000_SUCCESS;\n\tu32 i = 0;\n\tu32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\tu32 timeout = 10;\n\tbool ack = true;\n\n\tDEBUGFUNC(\"e1000_get_i2c_ack\");\n\n\te1000_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum high period of clock is 4us */\n\tusec_delay(E1000_I2C_T_HIGH);\n\n\t/* Wait until SCL returns high */\n\tfor (i = 0; i < timeout; i++) {\n\t\tusec_delay(1);\n\t\ti2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\t\tif (i2cctl & E1000_I2C_CLK_IN)\n\t\t\tbreak;\n\t}\n\tif (!(i2cctl & E1000_I2C_CLK_IN))\n\t\treturn E1000_ERR_I2C;\n\n\tack = e1000_get_i2c_data(&i2cctl);\n\tif (ack) {\n\t\tDEBUGOUT(\"I2C ack was not received.\\n\");\n\t\tstatus = E1000_ERR_I2C;\n\t}\n\n\te1000_lower_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum low period of clock is 4.7 us */\n\tusec_delay(E1000_I2C_T_LOW);\n\n\treturn status;\n}\n\n/**\n * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock\n * @hw: pointer to hardware structure\n * @data: read data value\n *\n * Clocks in one bit via I2C data/clock\n **/\nstatic s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)\n{\n\tu32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\tDEBUGFUNC(\"e1000_clock_in_i2c_bit\");\n\n\te1000_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum high period of clock is 4us */\n\tusec_delay(E1000_I2C_T_HIGH);\n\n\ti2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\t*data = e1000_get_i2c_data(&i2cctl);\n\n\te1000_lower_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum low period of clock is 4.7 us */\n\tusec_delay(E1000_I2C_T_LOW);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock\n * @hw: pointer to hardware structure\n * @data: data value to write\n *\n * Clocks out one bit via I2C data/clock\n **/\nstatic s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)\n{\n\ts32 status;\n\tu32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\tDEBUGFUNC(\"e1000_clock_out_i2c_bit\");\n\n\tstatus = e1000_set_i2c_data(hw, &i2cctl, data);\n\tif (status == E1000_SUCCESS) {\n\t\te1000_raise_i2c_clk(hw, &i2cctl);\n\n\t\t/* Minimum high period of clock is 4us */\n\t\tusec_delay(E1000_I2C_T_HIGH);\n\n\t\te1000_lower_i2c_clk(hw, &i2cctl);\n\n\t\t/* Minimum low period of clock is 4.7 us.\n\t\t * This also takes care of the data hold time.\n\t\t */\n\t\tusec_delay(E1000_I2C_T_LOW);\n\t} else {\n\t\tstatus = E1000_ERR_I2C;\n\t\tDEBUGOUT1(\"I2C data was not set to %X\\n\", data);\n\t}\n\n\treturn status;\n}\n/**\n * e1000_raise_i2c_clk - Raises the I2C SCL clock\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Raises the I2C clock line '0'->'1'\n **/\nstatic void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)\n{\n\tDEBUGFUNC(\"e1000_raise_i2c_clk\");\n\n\t*i2cctl |= E1000_I2C_CLK_OUT;\n\t*i2cctl &= ~E1000_I2C_CLK_OE_N;\n\tE1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* SCL rise time (1000ns) */\n\tusec_delay(E1000_I2C_T_RISE);\n}\n\n/**\n * e1000_lower_i2c_clk - Lowers the I2C SCL clock\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Lowers the I2C clock line '1'->'0'\n **/\nstatic void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)\n{\n\n\tDEBUGFUNC(\"e1000_lower_i2c_clk\");\n\n\t*i2cctl &= ~E1000_I2C_CLK_OUT;\n\t*i2cctl &= ~E1000_I2C_CLK_OE_N;\n\tE1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* SCL fall time (300ns) */\n\tusec_delay(E1000_I2C_T_FALL);\n}\n\n/**\n * e1000_set_i2c_data - Sets the I2C data bit\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n * @data: I2C data value (0 or 1) to set\n *\n * Sets the I2C data bit\n **/\nstatic s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)\n{\n\ts32 status = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_set_i2c_data\");\n\n\tif (data)\n\t\t*i2cctl |= E1000_I2C_DATA_OUT;\n\telse\n\t\t*i2cctl &= ~E1000_I2C_DATA_OUT;\n\n\t*i2cctl &= ~E1000_I2C_DATA_OE_N;\n\t*i2cctl |= E1000_I2C_CLK_OE_N;\n\tE1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */\n\tusec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);\n\n\t*i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\tif (data != e1000_get_i2c_data(i2cctl)) {\n\t\tstatus = E1000_ERR_I2C;\n\t\tDEBUGOUT1(\"Error - I2C data was not set to %X.\\n\", data);\n\t}\n\n\treturn status;\n}\n\n/**\n * e1000_get_i2c_data - Reads the I2C SDA data bit\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Returns the I2C data bit value\n **/\nstatic bool e1000_get_i2c_data(u32 *i2cctl)\n{\n\tbool data;\n\n\tDEBUGFUNC(\"e1000_get_i2c_data\");\n\n\tif (*i2cctl & E1000_I2C_DATA_IN)\n\t\tdata = 1;\n\telse\n\t\tdata = 0;\n\n\treturn data;\n}\n\n/**\n * e1000_i2c_bus_clear - Clears the I2C bus\n * @hw: pointer to hardware structure\n *\n * Clears the I2C bus by sending nine clock pulses.\n * Used when data line is stuck low.\n **/\nvoid e1000_i2c_bus_clear(struct e1000_hw *hw)\n{\n\tu32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\tu32 i;\n\n\tDEBUGFUNC(\"e1000_i2c_bus_clear\");\n\n\te1000_i2c_start(hw);\n\n\te1000_set_i2c_data(hw, &i2cctl, 1);\n\n\tfor (i = 0; i < 9; i++) {\n\t\te1000_raise_i2c_clk(hw, &i2cctl);\n\n\t\t/* Min high period of clock is 4us */\n\t\tusec_delay(E1000_I2C_T_HIGH);\n\n\t\te1000_lower_i2c_clk(hw, &i2cctl);\n\n\t\t/* Min low period of clock is 4.7us*/\n\t\tusec_delay(E1000_I2C_T_LOW);\n\t}\n\n\te1000_i2c_start(hw);\n\n\t/* Put the i2c bus back to default state */\n\te1000_i2c_stop(hw);\n}\n\nstatic const u8 e1000_emc_temp_data[4] = {\n\tE1000_EMC_INTERNAL_DATA,\n\tE1000_EMC_DIODE1_DATA,\n\tE1000_EMC_DIODE2_DATA,\n\tE1000_EMC_DIODE3_DATA\n};\nstatic const u8 e1000_emc_therm_limit[4] = {\n\tE1000_EMC_INTERNAL_THERM_LIMIT,\n\tE1000_EMC_DIODE1_THERM_LIMIT,\n\tE1000_EMC_DIODE2_THERM_LIMIT,\n\tE1000_EMC_DIODE3_THERM_LIMIT\n};\n\n/**\n * e1000_get_thermal_sensor_data_generic - Gathers thermal sensor data\n * @hw: pointer to hardware structure\n *\n * Updates the temperatures in mac.thermal_sensor_data\n **/\ns32 e1000_get_thermal_sensor_data_generic(struct e1000_hw *hw)\n{\n\ts32 status = E1000_SUCCESS;\n\tu16 ets_offset;\n\tu16 ets_cfg;\n\tu16 ets_sensor;\n\tu8 num_sensors;\n\tu8 sensor_index;\n\tu8 sensor_location;\n\tu8 i;\n\tstruct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;\n\n\tDEBUGFUNC(\"e1000_get_thermal_sensor_data_generic\");\n\n\tif ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))\n\t\treturn E1000_NOT_IMPLEMENTED;\n\n\tdata->sensor[0].temp = (E1000_READ_REG(hw, E1000_THMJT) & 0xFF);\n\n\t/* Return the internal sensor only if ETS is unsupported */\n\te1000_read_nvm(hw, NVM_ETS_CFG, 1, &ets_offset);\n\tif ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))\n\t\treturn status;\n\n\te1000_read_nvm(hw, ets_offset, 1, &ets_cfg);\n\tif (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)\n\t != NVM_ETS_TYPE_EMC)\n\t\treturn E1000_NOT_IMPLEMENTED;\n\n\tnum_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);\n\tif (num_sensors > E1000_MAX_SENSORS)\n\t\tnum_sensors = E1000_MAX_SENSORS;\n\n\tfor (i = 1; i < num_sensors; i++) {\n\t\te1000_read_nvm(hw, (ets_offset + i), 1, &ets_sensor);\n\t\tsensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>\n\t\t\t\tNVM_ETS_DATA_INDEX_SHIFT);\n\t\tsensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>\n\t\t\t\t NVM_ETS_DATA_LOC_SHIFT);\n\n\t\tif (sensor_location != 0)\n\t\t\thw->phy.ops.read_i2c_byte(hw,\n\t\t\t\t\te1000_emc_temp_data[sensor_index],\n\t\t\t\t\tE1000_I2C_THERMAL_SENSOR_ADDR,\n\t\t\t\t\t&data->sensor[i].temp);\n\t}\n\treturn status;\n}\n\n/**\n * e1000_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds\n * @hw: pointer to hardware structure\n *\n * Sets the thermal sensor thresholds according to the NVM map\n * and save off the threshold and location values into mac.thermal_sensor_data\n **/\ns32 e1000_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)\n{\n\ts32 status = E1000_SUCCESS;\n\tu16 ets_offset;\n\tu16 ets_cfg;\n\tu16 ets_sensor;\n\tu8 low_thresh_delta;\n\tu8 num_sensors;\n\tu8 sensor_index;\n\tu8 sensor_location;\n\tu8 therm_limit;\n\tu8 i;\n\tstruct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;\n\n\tDEBUGFUNC(\"e1000_init_thermal_sensor_thresh_generic\");\n\n\tif ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))\n\t\treturn E1000_NOT_IMPLEMENTED;\n\n\tmemset(data, 0, sizeof(struct e1000_thermal_sensor_data));\n\n\tdata->sensor[0].location = 0x1;\n\tdata->sensor[0].caution_thresh =\n\t\t(E1000_READ_REG(hw, E1000_THHIGHTC) & 0xFF);\n\tdata->sensor[0].max_op_thresh =\n\t\t(E1000_READ_REG(hw, E1000_THLOWTC) & 0xFF);\n\n\t/* Return the internal sensor only if ETS is unsupported */\n\te1000_read_nvm(hw, NVM_ETS_CFG, 1, &ets_offset);\n\tif ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))\n\t\treturn status;\n\n\te1000_read_nvm(hw, ets_offset, 1, &ets_cfg);\n\tif (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)\n\t != NVM_ETS_TYPE_EMC)\n\t\treturn E1000_NOT_IMPLEMENTED;\n\n\tlow_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>\n\t\t\t NVM_ETS_LTHRES_DELTA_SHIFT);\n\tnum_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);\n\n\tfor (i = 1; i <= num_sensors; i++) {\n\t\te1000_read_nvm(hw, (ets_offset + i), 1, &ets_sensor);\n\t\tsensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>\n\t\t\t\tNVM_ETS_DATA_INDEX_SHIFT);\n\t\tsensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>\n\t\t\t\t NVM_ETS_DATA_LOC_SHIFT);\n\t\ttherm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;\n\n\t\thw->phy.ops.write_i2c_byte(hw,\n\t\t\te1000_emc_therm_limit[sensor_index],\n\t\t\tE1000_I2C_THERMAL_SENSOR_ADDR,\n\t\t\ttherm_limit);\n\n\t\tif ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {\n\t\t\tdata->sensor[i].location = sensor_location;\n\t\t\tdata->sensor[i].caution_thresh = therm_limit;\n\t\t\tdata->sensor[i].max_op_thresh = therm_limit -\n\t\t\t\t\t\t\tlow_thresh_delta;\n\t\t}\n\t}\n\treturn status;\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_82575.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _E1000_82575_H_\n#define _E1000_82575_H_\n\n#define ID_LED_DEFAULT_82575_SERDES\t((ID_LED_DEF1_DEF2 << 12) | \\\n\t\t\t\t\t (ID_LED_DEF1_DEF2 << 8) | \\\n\t\t\t\t\t (ID_LED_DEF1_DEF2 << 4) | \\\n\t\t\t\t\t (ID_LED_OFF1_ON2))\n/*\n * Receive Address Register Count\n * Number of high/low register pairs in the RAR. The RAR (Receive Address\n * Registers) holds the directed and multicast addresses that we monitor.\n * These entries are also used for MAC-based filtering.\n */\n/*\n * For 82576, there are an additional set of RARs that begin at an offset\n * separate from the first set of RARs.\n */\n#define E1000_RAR_ENTRIES_82575\t16\n#define E1000_RAR_ENTRIES_82576\t24\n#define E1000_RAR_ENTRIES_82580\t24\n#define E1000_RAR_ENTRIES_I350\t32\n#define E1000_SW_SYNCH_MB\t0x00000100\n#define E1000_STAT_DEV_RST_SET\t0x00100000\n#define E1000_CTRL_DEV_RST\t0x20000000\n\nstruct e1000_adv_data_desc {\n\t__le64 buffer_addr; /* Address of the descriptor's data buffer */\n\tunion {\n\t\tu32 data;\n\t\tstruct {\n\t\t\tu32 datalen:16; /* Data buffer length */\n\t\t\tu32 rsvd:4;\n\t\t\tu32 dtyp:4; /* Descriptor type */\n\t\t\tu32 dcmd:8; /* Descriptor command */\n\t\t} config;\n\t} lower;\n\tunion {\n\t\tu32 data;\n\t\tstruct {\n\t\t\tu32 status:4; /* Descriptor status */\n\t\t\tu32 idx:4;\n\t\t\tu32 popts:6; /* Packet Options */\n\t\t\tu32 paylen:18; /* Payload length */\n\t\t} options;\n\t} upper;\n};\n\n#define E1000_TXD_DTYP_ADV_C\t0x2 /* Advanced Context Descriptor */\n#define E1000_TXD_DTYP_ADV_D\t0x3 /* Advanced Data Descriptor */\n#define E1000_ADV_TXD_CMD_DEXT\t0x20 /* Descriptor extension (0 = legacy) */\n#define E1000_ADV_TUCMD_IPV4\t0x2 /* IP Packet Type: 1=IPv4 */\n#define E1000_ADV_TUCMD_IPV6\t0x0 /* IP Packet Type: 0=IPv6 */\n#define E1000_ADV_TUCMD_L4T_UDP\t0x0 /* L4 Packet TYPE of UDP */\n#define E1000_ADV_TUCMD_L4T_TCP\t0x4 /* L4 Packet TYPE of TCP */\n#define E1000_ADV_TUCMD_MKRREQ\t0x10 /* Indicates markers are required */\n#define E1000_ADV_DCMD_EOP\t0x1 /* End of Packet */\n#define E1000_ADV_DCMD_IFCS\t0x2 /* Insert FCS (Ethernet CRC) */\n#define E1000_ADV_DCMD_RS\t0x8 /* Report Status */\n#define E1000_ADV_DCMD_VLE\t0x40 /* Add VLAN tag */\n#define E1000_ADV_DCMD_TSE\t0x80 /* TCP Seg enable */\n/* Extended Device Control */\n#define E1000_CTRL_EXT_NSICR\t0x00000001 /* Disable Intr Clear all on read */\n\nstruct e1000_adv_context_desc {\n\tunion {\n\t\tu32 ip_config;\n\t\tstruct {\n\t\t\tu32 iplen:9;\n\t\t\tu32 maclen:7;\n\t\t\tu32 vlan_tag:16;\n\t\t} fields;\n\t} ip_setup;\n\tu32 seq_num;\n\tunion {\n\t\tu64 l4_config;\n\t\tstruct {\n\t\t\tu32 mkrloc:9;\n\t\t\tu32 tucmd:11;\n\t\t\tu32 dtyp:4;\n\t\t\tu32 adv:8;\n\t\t\tu32 rsvd:4;\n\t\t\tu32 idx:4;\n\t\t\tu32 l4len:8;\n\t\t\tu32 mss:16;\n\t\t} fields;\n\t} l4_setup;\n};\n\n/* SRRCTL bit definitions */\n#define E1000_SRRCTL_BSIZEPKT_SHIFT\t\t10 /* Shift _right_ */\n#define E1000_SRRCTL_BSIZEHDRSIZE_MASK\t\t0x00000F00\n#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT\t\t2 /* Shift _left_ */\n#define E1000_SRRCTL_DESCTYPE_LEGACY\t\t0x00000000\n#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF\t0x02000000\n#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT\t\t0x04000000\n#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS\t0x0A000000\n#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION\t0x06000000\n#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000\n#define E1000_SRRCTL_DESCTYPE_MASK\t\t0x0E000000\n#define E1000_SRRCTL_TIMESTAMP\t\t\t0x40000000\n#define E1000_SRRCTL_DROP_EN\t\t\t0x80000000\n\n#define E1000_SRRCTL_BSIZEPKT_MASK\t\t0x0000007F\n#define E1000_SRRCTL_BSIZEHDR_MASK\t\t0x00003F00\n\n#define E1000_TX_HEAD_WB_ENABLE\t\t0x1\n#define E1000_TX_SEQNUM_WB_ENABLE\t0x2\n\n#define E1000_MRQC_ENABLE_RSS_4Q\t\t0x00000002\n#define E1000_MRQC_ENABLE_VMDQ\t\t\t0x00000003\n#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q\t\t0x00000005\n#define E1000_MRQC_RSS_FIELD_IPV4_UDP\t\t0x00400000\n#define E1000_MRQC_RSS_FIELD_IPV6_UDP\t\t0x00800000\n#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX\t0x01000000\n#define E1000_MRQC_ENABLE_RSS_8Q\t\t0x00000002\n\n#define E1000_VMRCTL_MIRROR_PORT_SHIFT\t\t8\n#define E1000_VMRCTL_MIRROR_DSTPORT_MASK\t(7 << \\\n\t\t\t\t\t\t E1000_VMRCTL_MIRROR_PORT_SHIFT)\n#define E1000_VMRCTL_POOL_MIRROR_ENABLE\t\t(1 << 0)\n#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE\t(1 << 1)\n#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE\t(1 << 2)\n\n#define E1000_EICR_TX_QUEUE ( \\\n\tE1000_EICR_TX_QUEUE0 | \\\n\tE1000_EICR_TX_QUEUE1 | \\\n\tE1000_EICR_TX_QUEUE2 | \\\n\tE1000_EICR_TX_QUEUE3)\n\n#define E1000_EICR_RX_QUEUE ( \\\n\tE1000_EICR_RX_QUEUE0 | \\\n\tE1000_EICR_RX_QUEUE1 | \\\n\tE1000_EICR_RX_QUEUE2 | \\\n\tE1000_EICR_RX_QUEUE3)\n\n#define E1000_EIMS_RX_QUEUE\tE1000_EICR_RX_QUEUE\n#define E1000_EIMS_TX_QUEUE\tE1000_EICR_TX_QUEUE\n\n#define EIMS_ENABLE_MASK ( \\\n\tE1000_EIMS_RX_QUEUE | \\\n\tE1000_EIMS_TX_QUEUE | \\\n\tE1000_EIMS_TCP_TIMER | \\\n\tE1000_EIMS_OTHER)\n\n/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */\n#define E1000_IMIR_PORT_IM_EN\t0x00010000 /* TCP port enable */\n#define E1000_IMIR_PORT_BP\t0x00020000 /* TCP port check bypass */\n#define E1000_IMIREXT_SIZE_BP\t0x00001000 /* Packet size bypass */\n#define E1000_IMIREXT_CTRL_URG\t0x00002000 /* Check URG bit in header */\n#define E1000_IMIREXT_CTRL_ACK\t0x00004000 /* Check ACK bit in header */\n#define E1000_IMIREXT_CTRL_PSH\t0x00008000 /* Check PSH bit in header */\n#define E1000_IMIREXT_CTRL_RST\t0x00010000 /* Check RST bit in header */\n#define E1000_IMIREXT_CTRL_SYN\t0x00020000 /* Check SYN bit in header */\n#define E1000_IMIREXT_CTRL_FIN\t0x00040000 /* Check FIN bit in header */\n#define E1000_IMIREXT_CTRL_BP\t0x00080000 /* Bypass check of ctrl bits */\n\n/* Receive Descriptor - Advanced */\nunion e1000_adv_rx_desc {\n\tstruct {\n\t\t__le64 pkt_addr; /* Packet buffer address */\n\t\t__le64 hdr_addr; /* Header buffer address */\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\t__le32 data;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 pkt_info; /*RSS type, Pkt type*/\n\t\t\t\t\t/* Split Header, header buffer len */\n\t\t\t\t\t__le16 hdr_info;\n\t\t\t\t} hs_rss;\n\t\t\t} lo_dword;\n\t\t\tunion {\n\t\t\t\t__le32 rss; /* RSS Hash */\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id; /* IP id */\n\t\t\t\t\t__le16 csum; /* Packet Checksum */\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error; /* ext status/error */\n\t\t\t__le16 length; /* Packet length */\n\t\t\t__le16 vlan; /* VLAN tag */\n\t\t} upper;\n\t} wb; /* writeback */\n};\n\n#define E1000_RXDADV_RSSTYPE_MASK\t0x0000000F\n#define E1000_RXDADV_RSSTYPE_SHIFT\t12\n#define E1000_RXDADV_HDRBUFLEN_MASK\t0x7FE0\n#define E1000_RXDADV_HDRBUFLEN_SHIFT\t5\n#define E1000_RXDADV_SPLITHEADER_EN\t0x00001000\n#define E1000_RXDADV_SPH\t\t0x8000\n#define E1000_RXDADV_STAT_TS\t\t0x10000 /* Pkt was time stamped */\n#define E1000_RXDADV_STAT_TSIP\t\t0x08000 /* timestamp in packet */\n#define E1000_RXDADV_ERR_HBO\t\t0x00800000\n\n/* RSS Hash results */\n#define E1000_RXDADV_RSSTYPE_NONE\t0x00000000\n#define E1000_RXDADV_RSSTYPE_IPV4_TCP\t0x00000001\n#define E1000_RXDADV_RSSTYPE_IPV4\t0x00000002\n#define E1000_RXDADV_RSSTYPE_IPV6_TCP\t0x00000003\n#define E1000_RXDADV_RSSTYPE_IPV6_EX\t0x00000004\n#define E1000_RXDADV_RSSTYPE_IPV6\t0x00000005\n#define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006\n#define E1000_RXDADV_RSSTYPE_IPV4_UDP\t0x00000007\n#define E1000_RXDADV_RSSTYPE_IPV6_UDP\t0x00000008\n#define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009\n\n/* RSS Packet Types as indicated in the receive descriptor */\n#define E1000_RXDADV_PKTTYPE_NONE\t0x00000000\n#define E1000_RXDADV_PKTTYPE_IPV4\t0x00000010 /* IPV4 hdr present */\n#define E1000_RXDADV_PKTTYPE_IPV4_EX\t0x00000020 /* IPV4 hdr + extensions */\n#define E1000_RXDADV_PKTTYPE_IPV6\t0x00000040 /* IPV6 hdr present */\n#define E1000_RXDADV_PKTTYPE_IPV6_EX\t0x00000080 /* IPV6 hdr + extensions */\n#define E1000_RXDADV_PKTTYPE_TCP\t0x00000100 /* TCP hdr present */\n#define E1000_RXDADV_PKTTYPE_UDP\t0x00000200 /* UDP hdr present */\n#define E1000_RXDADV_PKTTYPE_SCTP\t0x00000400 /* SCTP hdr present */\n#define E1000_RXDADV_PKTTYPE_NFS\t0x00000800 /* NFS hdr present */\n\n#define E1000_RXDADV_PKTTYPE_IPSEC_ESP\t0x00001000 /* IPSec ESP */\n#define E1000_RXDADV_PKTTYPE_IPSEC_AH\t0x00002000 /* IPSec AH */\n#define E1000_RXDADV_PKTTYPE_LINKSEC\t0x00004000 /* LinkSec Encap */\n#define E1000_RXDADV_PKTTYPE_ETQF\t0x00008000 /* PKTTYPE is ETQF index */\n#define E1000_RXDADV_PKTTYPE_ETQF_MASK\t0x00000070 /* ETQF has 8 indices */\n#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT\t4 /* Right-shift 4 bits */\n\n/* LinkSec results */\n/* Security Processing bit Indication */\n#define E1000_RXDADV_LNKSEC_STATUS_SECP\t\t0x00020000\n#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK\t0x18000000\n#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH\t0x08000000\n#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR\t0x10000000\n#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG\t0x18000000\n\n#define E1000_RXDADV_IPSEC_STATUS_SECP\t\t\t0x00020000\n#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK\t\t0x18000000\n#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL\t0x08000000\n#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH\t\t0x10000000\n#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED\t0x18000000\n\n/* Transmit Descriptor - Advanced */\nunion e1000_adv_tx_desc {\n\tstruct {\n\t\t__le64 buffer_addr; /* Address of descriptor's data buf */\n\t\t__le32 cmd_type_len;\n\t\t__le32 olinfo_status;\n\t} read;\n\tstruct {\n\t\t__le64 rsvd; /* Reserved */\n\t\t__le32 nxtseq_seed;\n\t\t__le32 status;\n\t} wb;\n};\n\n/* Adv Transmit Descriptor Config Masks */\n#define E1000_ADVTXD_DTYP_CTXT\t0x00200000 /* Advanced Context Descriptor */\n#define E1000_ADVTXD_DTYP_DATA\t0x00300000 /* Advanced Data Descriptor */\n#define E1000_ADVTXD_DCMD_EOP\t0x01000000 /* End of Packet */\n#define E1000_ADVTXD_DCMD_IFCS\t0x02000000 /* Insert FCS (Ethernet CRC) */\n#define E1000_ADVTXD_DCMD_RS\t0x08000000 /* Report Status */\n#define E1000_ADVTXD_DCMD_DDTYP_ISCSI\t0x10000000 /* DDP hdr type or iSCSI */\n#define E1000_ADVTXD_DCMD_DEXT\t0x20000000 /* Descriptor extension (1=Adv) */\n#define E1000_ADVTXD_DCMD_VLE\t0x40000000 /* VLAN pkt enable */\n#define E1000_ADVTXD_DCMD_TSE\t0x80000000 /* TCP Seg enable */\n#define E1000_ADVTXD_MAC_LINKSEC\t0x00040000 /* Apply LinkSec on pkt */\n#define E1000_ADVTXD_MAC_TSTAMP\t\t0x00080000 /* IEEE1588 Timestamp pkt */\n#define E1000_ADVTXD_STAT_SN_CRC\t0x00000002 /* NXTSEQ/SEED prsnt in WB */\n#define E1000_ADVTXD_IDX_SHIFT\t\t4 /* Adv desc Index shift */\n#define E1000_ADVTXD_POPTS_ISCO_1ST\t0x00000000 /* 1st TSO of iSCSI PDU */\n#define E1000_ADVTXD_POPTS_ISCO_MDL\t0x00000800 /* Middle TSO of iSCSI PDU */\n#define E1000_ADVTXD_POPTS_ISCO_LAST\t0x00001000 /* Last TSO of iSCSI PDU */\n/* 1st & Last TSO-full iSCSI PDU*/\n#define E1000_ADVTXD_POPTS_ISCO_FULL\t0x00001800\n#define E1000_ADVTXD_POPTS_IPSEC\t0x00000400 /* IPSec offload request */\n#define E1000_ADVTXD_PAYLEN_SHIFT\t14 /* Adv desc PAYLEN shift */\n\n/* Context descriptors */\nstruct e1000_adv_tx_context_desc {\n\t__le32 vlan_macip_lens;\n\t__le32 seqnum_seed;\n\t__le32 type_tucmd_mlhl;\n\t__le32 mss_l4len_idx;\n};\n\n#define E1000_ADVTXD_MACLEN_SHIFT\t9 /* Adv ctxt desc mac len shift */\n#define E1000_ADVTXD_VLAN_SHIFT\t\t16 /* Adv ctxt vlan tag shift */\n#define E1000_ADVTXD_TUCMD_IPV4\t\t0x00000400 /* IP Packet Type: 1=IPv4 */\n#define E1000_ADVTXD_TUCMD_IPV6\t\t0x00000000 /* IP Packet Type: 0=IPv6 */\n#define E1000_ADVTXD_TUCMD_L4T_UDP\t0x00000000 /* L4 Packet TYPE of UDP */\n#define E1000_ADVTXD_TUCMD_L4T_TCP\t0x00000800 /* L4 Packet TYPE of TCP */\n#define E1000_ADVTXD_TUCMD_L4T_SCTP\t0x00001000 /* L4 Packet TYPE of SCTP */\n#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP\t0x00002000 /* IPSec Type ESP */\n/* IPSec Encrypt Enable for ESP */\n#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN\t0x00004000\n/* Req requires Markers and CRC */\n#define E1000_ADVTXD_TUCMD_MKRREQ\t0x00002000\n#define E1000_ADVTXD_L4LEN_SHIFT\t8 /* Adv ctxt L4LEN shift */\n#define E1000_ADVTXD_MSS_SHIFT\t\t16 /* Adv ctxt MSS shift */\n/* Adv ctxt IPSec SA IDX mask */\n#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK\t0x000000FF\n/* Adv ctxt IPSec ESP len mask */\n#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK\t\t0x000000FF\n\n/* Additional Transmit Descriptor Control definitions */\n#define E1000_TXDCTL_QUEUE_ENABLE\t0x02000000 /* Ena specific Tx Queue */\n#define E1000_TXDCTL_SWFLSH\t\t0x04000000 /* Tx Desc. wbk flushing */\n/* Tx Queue Arbitration Priority 0=low, 1=high */\n#define E1000_TXDCTL_PRIORITY\t\t0x08000000\n\n/* Additional Receive Descriptor Control definitions */\n#define E1000_RXDCTL_QUEUE_ENABLE\t0x02000000 /* Ena specific Rx Queue */\n#define E1000_RXDCTL_SWFLSH\t\t0x04000000 /* Rx Desc. wbk flushing */\n\n/* Direct Cache Access (DCA) definitions */\n#define E1000_DCA_CTRL_DCA_ENABLE\t0x00000000 /* DCA Enable */\n#define E1000_DCA_CTRL_DCA_DISABLE\t0x00000001 /* DCA Disable */\n\n#define E1000_DCA_CTRL_DCA_MODE_CB1\t0x00 /* DCA Mode CB1 */\n#define E1000_DCA_CTRL_DCA_MODE_CB2\t0x02 /* DCA Mode CB2 */\n\n#define E1000_DCA_RXCTRL_CPUID_MASK\t0x0000001F /* Rx CPUID Mask */\n#define E1000_DCA_RXCTRL_DESC_DCA_EN\t(1 << 5) /* DCA Rx Desc enable */\n#define E1000_DCA_RXCTRL_HEAD_DCA_EN\t(1 << 6) /* DCA Rx Desc header ena */\n#define E1000_DCA_RXCTRL_DATA_DCA_EN\t(1 << 7) /* DCA Rx Desc payload ena */\n#define E1000_DCA_RXCTRL_DESC_RRO_EN\t(1 << 9) /* DCA Rx Desc Relax Order */\n\n#define E1000_DCA_TXCTRL_CPUID_MASK\t0x0000001F /* Tx CPUID Mask */\n#define E1000_DCA_TXCTRL_DESC_DCA_EN\t(1 << 5) /* DCA Tx Desc enable */\n#define E1000_DCA_TXCTRL_DESC_RRO_EN\t(1 << 9) /* Tx rd Desc Relax Order */\n#define E1000_DCA_TXCTRL_TX_WB_RO_EN\t(1 << 11) /* Tx Desc writeback RO bit */\n#define E1000_DCA_TXCTRL_DATA_RRO_EN\t(1 << 13) /* Tx rd data Relax Order */\n\n#define E1000_DCA_TXCTRL_CPUID_MASK_82576\t0xFF000000 /* Tx CPUID Mask */\n#define E1000_DCA_RXCTRL_CPUID_MASK_82576\t0xFF000000 /* Rx CPUID Mask */\n#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576\t24 /* Tx CPUID */\n#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576\t24 /* Rx CPUID */\n\n/* Additional interrupt register bit definitions */\n#define E1000_ICR_LSECPNS\t0x00000020 /* PN threshold - server */\n#define E1000_IMS_LSECPNS\tE1000_ICR_LSECPNS /* PN threshold - server */\n#define E1000_ICS_LSECPNS\tE1000_ICR_LSECPNS /* PN threshold - server */\n\n/* ETQF register bit definitions */\n#define E1000_ETQF_FILTER_ENABLE\t(1 << 26)\n#define E1000_ETQF_IMM_INT\t\t(1 << 29)\n#define E1000_ETQF_1588\t\t\t(1 << 30)\n#define E1000_ETQF_QUEUE_ENABLE\t\t(1 << 31)\n/*\n * ETQF filter list: one static filter per filter consumer. This is\n * to avoid filter collisions later. Add new filters\n * here!!\n *\n * Current filters:\n * EAPOL 802.1x (0x888e): Filter 0\n */\n#define E1000_ETQF_FILTER_EAPOL\t\t0\n\n#define E1000_FTQF_VF_BP\t\t0x00008000\n#define E1000_FTQF_1588_TIME_STAMP\t0x08000000\n#define E1000_FTQF_MASK\t\t\t0xF0000000\n#define E1000_FTQF_MASK_PROTO_BP\t0x10000000\n#define E1000_FTQF_MASK_SOURCE_ADDR_BP\t0x20000000\n#define E1000_FTQF_MASK_DEST_ADDR_BP\t0x40000000\n#define E1000_FTQF_MASK_SOURCE_PORT_BP\t0x80000000\n\n#define E1000_NVM_APME_82575\t\t0x0400\n#define MAX_NUM_VFS\t\t\t7\n\n#define E1000_DTXSWC_MAC_SPOOF_MASK\t0x000000FF /* Per VF MAC spoof cntrl */\n#define E1000_DTXSWC_VLAN_SPOOF_MASK\t0x0000FF00 /* Per VF VLAN spoof cntrl */\n#define E1000_DTXSWC_LLE_MASK\t\t0x00FF0000 /* Per VF Local LB enables */\n#define E1000_DTXSWC_VLAN_SPOOF_SHIFT\t8\n#define E1000_DTXSWC_LLE_SHIFT\t\t16\n#define E1000_DTXSWC_VMDQ_LOOPBACK_EN\t(1 << 31) /* global VF LB enable */\n\n/* Easy defines for setting default pool, would normally be left a zero */\n#define E1000_VT_CTL_DEFAULT_POOL_SHIFT\t7\n#define E1000_VT_CTL_DEFAULT_POOL_MASK\t(0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)\n\n/* Other useful VMD_CTL register defines */\n#define E1000_VT_CTL_IGNORE_MAC\t\t(1 << 28)\n#define E1000_VT_CTL_DISABLE_DEF_POOL\t(1 << 29)\n#define E1000_VT_CTL_VM_REPL_EN\t\t(1 << 30)\n\n/* Per VM Offload register setup */\n#define E1000_VMOLR_RLPML_MASK\t0x00003FFF /* Long Packet Maximum Length mask */\n#define E1000_VMOLR_LPE\t\t0x00010000 /* Accept Long packet */\n#define E1000_VMOLR_RSSE\t0x00020000 /* Enable RSS */\n#define E1000_VMOLR_AUPE\t0x01000000 /* Accept untagged packets */\n#define E1000_VMOLR_ROMPE\t0x02000000 /* Accept overflow multicast */\n#define E1000_VMOLR_ROPE\t0x04000000 /* Accept overflow unicast */\n#define E1000_VMOLR_BAM\t\t0x08000000 /* Accept Broadcast packets */\n#define E1000_VMOLR_MPME\t0x10000000 /* Multicast promiscuous mode */\n#define E1000_VMOLR_STRVLAN\t0x40000000 /* Vlan stripping enable */\n#define E1000_VMOLR_STRCRC\t0x80000000 /* CRC stripping enable */\n\n#define E1000_VMOLR_VPE\t\t0x00800000 /* VLAN promiscuous enable */\n#define E1000_VMOLR_UPE\t\t0x20000000 /* Unicast promisuous enable */\n#define E1000_DVMOLR_HIDVLAN\t0x20000000 /* Vlan hiding enable */\n#define E1000_DVMOLR_STRVLAN\t0x40000000 /* Vlan stripping enable */\n#define E1000_DVMOLR_STRCRC\t0x80000000 /* CRC stripping enable */\n\n#define E1000_PBRWAC_WALPB\t0x00000007 /* Wrap around event on LAN Rx PB */\n#define E1000_PBRWAC_PBE\t0x00000008 /* Rx packet buffer empty */\n\n#define E1000_VLVF_ARRAY_SIZE\t\t32\n#define E1000_VLVF_VLANID_MASK\t\t0x00000FFF\n#define E1000_VLVF_POOLSEL_SHIFT\t12\n#define E1000_VLVF_POOLSEL_MASK\t\t(0xFF << E1000_VLVF_POOLSEL_SHIFT)\n#define E1000_VLVF_LVLAN\t\t0x00100000\n#define E1000_VLVF_VLANID_ENABLE\t0x80000000\n\n#define E1000_VMVIR_VLANA_DEFAULT\t0x40000000 /* Always use default VLAN */\n#define E1000_VMVIR_VLANA_NEVER\t\t0x80000000 /* Never insert VLAN tag */\n\n#define E1000_VF_INIT_TIMEOUT\t200 /* Number of retries to clear RSTI */\n\n#define E1000_IOVCTL\t\t0x05BBC\n#define E1000_IOVCTL_REUSE_VFQ\t0x00000001\n\n#define E1000_RPLOLR_STRVLAN\t0x40000000\n#define E1000_RPLOLR_STRCRC\t0x80000000\n\n#define E1000_TCTL_EXT_COLD\t0x000FFC00\n#define E1000_TCTL_EXT_COLD_SHIFT\t10\n\n#define E1000_DTXCTL_8023LL\t0x0004\n#define E1000_DTXCTL_VLAN_ADDED\t0x0008\n#define E1000_DTXCTL_OOS_ENABLE\t0x0010\n#define E1000_DTXCTL_MDP_EN\t0x0020\n#define E1000_DTXCTL_SPOOF_INT\t0x0040\n\n#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT\t(1 << 14)\n\n#define ALL_QUEUES\t\t0xFFFF\n\n/* Rx packet buffer size defines */\n#define E1000_RXPBS_SIZE_MASK_82576\t0x0000007F\nvoid e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);\nvoid e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf);\nvoid e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);\ns32 e1000_init_nvm_params_82575(struct e1000_hw *hw);\n\nu16 e1000_rxpbs_adjust_82580(u32 data);\ns32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data);\ns32 e1000_set_eee_i350(struct e1000_hw *);\ns32 e1000_set_eee_i354(struct e1000_hw *);\ns32 e1000_get_eee_status_i354(struct e1000_hw *, bool *);\n#define E1000_I2C_THERMAL_SENSOR_ADDR\t0xF8\n#define E1000_EMC_INTERNAL_DATA\t\t0x00\n#define E1000_EMC_INTERNAL_THERM_LIMIT\t0x20\n#define E1000_EMC_DIODE1_DATA\t\t0x01\n#define E1000_EMC_DIODE1_THERM_LIMIT\t0x19\n#define E1000_EMC_DIODE2_DATA\t\t0x23\n#define E1000_EMC_DIODE2_THERM_LIMIT\t0x1A\n#define E1000_EMC_DIODE3_DATA\t\t0x2A\n#define E1000_EMC_DIODE3_THERM_LIMIT\t0x30\n\ns32 e1000_get_thermal_sensor_data_generic(struct e1000_hw *hw);\ns32 e1000_init_thermal_sensor_thresh_generic(struct e1000_hw *hw);\n\n/* I2C SDA and SCL timing parameters for standard mode */\n#define E1000_I2C_T_HD_STA\t4\n#define E1000_I2C_T_LOW\t\t5\n#define E1000_I2C_T_HIGH\t4\n#define E1000_I2C_T_SU_STA\t5\n#define E1000_I2C_T_HD_DATA\t5\n#define E1000_I2C_T_SU_DATA\t1\n#define E1000_I2C_T_RISE\t1\n#define E1000_I2C_T_FALL\t1\n#define E1000_I2C_T_SU_STO\t4\n#define E1000_I2C_T_BUF\t\t5\n\ns32 e1000_set_i2c_bb(struct e1000_hw *hw);\ns32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t\tu8 dev_addr, u8 *data);\ns32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data);\nvoid e1000_i2c_bus_clear(struct e1000_hw *hw);\n#endif /* _E1000_82575_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_api.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"e1000_api.h\"\n\n/**\n * e1000_init_mac_params - Initialize MAC function pointers\n * @hw: pointer to the HW structure\n *\n * This function initializes the function pointers for the MAC\n * set of functions. Called by drivers or by e1000_setup_init_funcs.\n **/\ns32 e1000_init_mac_params(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tif (hw->mac.ops.init_params) {\n\t\tret_val = hw->mac.ops.init_params(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"MAC Initialization Error\\n\");\n\t\t\tgoto out;\n\t\t}\n\t} else {\n\t\tDEBUGOUT(\"mac.init_mac_params was NULL\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_nvm_params - Initialize NVM function pointers\n * @hw: pointer to the HW structure\n *\n * This function initializes the function pointers for the NVM\n * set of functions. Called by drivers or by e1000_setup_init_funcs.\n **/\ns32 e1000_init_nvm_params(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tif (hw->nvm.ops.init_params) {\n\t\tret_val = hw->nvm.ops.init_params(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Initialization Error\\n\");\n\t\t\tgoto out;\n\t\t}\n\t} else {\n\t\tDEBUGOUT(\"nvm.init_nvm_params was NULL\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_phy_params - Initialize PHY function pointers\n * @hw: pointer to the HW structure\n *\n * This function initializes the function pointers for the PHY\n * set of functions. Called by drivers or by e1000_setup_init_funcs.\n **/\ns32 e1000_init_phy_params(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tif (hw->phy.ops.init_params) {\n\t\tret_val = hw->phy.ops.init_params(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"PHY Initialization Error\\n\");\n\t\t\tgoto out;\n\t\t}\n\t} else {\n\t\tDEBUGOUT(\"phy.init_phy_params was NULL\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_mbx_params - Initialize mailbox function pointers\n * @hw: pointer to the HW structure\n *\n * This function initializes the function pointers for the PHY\n * set of functions. Called by drivers or by e1000_setup_init_funcs.\n **/\ns32 e1000_init_mbx_params(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tif (hw->mbx.ops.init_params) {\n\t\tret_val = hw->mbx.ops.init_params(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Mailbox Initialization Error\\n\");\n\t\t\tgoto out;\n\t\t}\n\t} else {\n\t\tDEBUGOUT(\"mbx.init_mbx_params was NULL\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_set_mac_type - Sets MAC type\n * @hw: pointer to the HW structure\n *\n * This function sets the mac type of the adapter based on the\n * device ID stored in the hw structure.\n * MUST BE FIRST FUNCTION CALLED (explicitly or through\n * e1000_setup_init_funcs()).\n **/\ns32 e1000_set_mac_type(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_set_mac_type\");\n\n\tswitch (hw->device_id) {\n\tcase E1000_DEV_ID_82575EB_COPPER:\n\tcase E1000_DEV_ID_82575EB_FIBER_SERDES:\n\tcase E1000_DEV_ID_82575GB_QUAD_COPPER:\n\t\tmac->type = e1000_82575;\n\t\tbreak;\n\tcase E1000_DEV_ID_82576:\n\tcase E1000_DEV_ID_82576_FIBER:\n\tcase E1000_DEV_ID_82576_SERDES:\n\tcase E1000_DEV_ID_82576_QUAD_COPPER:\n\tcase E1000_DEV_ID_82576_QUAD_COPPER_ET2:\n\tcase E1000_DEV_ID_82576_NS:\n\tcase E1000_DEV_ID_82576_NS_SERDES:\n\tcase E1000_DEV_ID_82576_SERDES_QUAD:\n\t\tmac->type = e1000_82576;\n\t\tbreak;\n\tcase E1000_DEV_ID_82580_COPPER:\n\tcase E1000_DEV_ID_82580_FIBER:\n\tcase E1000_DEV_ID_82580_SERDES:\n\tcase E1000_DEV_ID_82580_SGMII:\n\tcase E1000_DEV_ID_82580_COPPER_DUAL:\n\tcase E1000_DEV_ID_82580_QUAD_FIBER:\n\tcase E1000_DEV_ID_DH89XXCC_SGMII:\n\tcase E1000_DEV_ID_DH89XXCC_SERDES:\n\tcase E1000_DEV_ID_DH89XXCC_BACKPLANE:\n\tcase E1000_DEV_ID_DH89XXCC_SFP:\n\t\tmac->type = e1000_82580;\n\t\tbreak;\n\tcase E1000_DEV_ID_I350_COPPER:\n\tcase E1000_DEV_ID_I350_FIBER:\n\tcase E1000_DEV_ID_I350_SERDES:\n\tcase E1000_DEV_ID_I350_SGMII:\n\tcase E1000_DEV_ID_I350_DA4:\n\t\tmac->type = e1000_i350;\n\t\tbreak;\n\tcase E1000_DEV_ID_I210_COPPER_FLASHLESS:\n\tcase E1000_DEV_ID_I210_SERDES_FLASHLESS:\n\tcase E1000_DEV_ID_I210_COPPER:\n\tcase E1000_DEV_ID_I210_COPPER_OEM1:\n\tcase E1000_DEV_ID_I210_COPPER_IT:\n\tcase E1000_DEV_ID_I210_FIBER:\n\tcase E1000_DEV_ID_I210_SERDES:\n\tcase E1000_DEV_ID_I210_SGMII:\n\t\tmac->type = e1000_i210;\n\t\tbreak;\n\tcase E1000_DEV_ID_I211_COPPER:\n\t\tmac->type = e1000_i211;\n\t\tbreak;\n\n\tcase E1000_DEV_ID_I354_BACKPLANE_1GBPS:\n\tcase E1000_DEV_ID_I354_SGMII:\n\tcase E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:\n\t\tmac->type = e1000_i354;\n\t\tbreak;\n\tdefault:\n\t\t/* Should never have loaded on this device */\n\t\tret_val = -E1000_ERR_MAC_INIT;\n\t\tbreak;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_init_funcs - Initializes function pointers\n * @hw: pointer to the HW structure\n * @init_device: true will initialize the rest of the function pointers\n *\t\t getting the device ready for use. false will only set\n *\t\t MAC type and the function pointers for the other init\n *\t\t functions. Passing false will not generate any hardware\n *\t\t reads or writes.\n *\n * This function must be called by a driver in order to use the rest\n * of the 'shared' code files. Called by drivers only.\n **/\ns32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)\n{\n\ts32 ret_val;\n\n\t/* Can't do much good without knowing the MAC type. */\n\tret_val = e1000_set_mac_type(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"ERROR: MAC type could not be set properly.\\n\");\n\t\tgoto out;\n\t}\n\n\tif (!hw->hw_addr) {\n\t\tDEBUGOUT(\"ERROR: Registers not mapped\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * Init function pointers to generic implementations. We do this first\n\t * allowing a driver module to override it afterward.\n\t */\n\te1000_init_mac_ops_generic(hw);\n\te1000_init_phy_ops_generic(hw);\n\te1000_init_nvm_ops_generic(hw);\n\te1000_init_mbx_ops_generic(hw);\n\n\t/*\n\t * Set up the init function pointers. These are functions within the\n\t * adapter family file that sets up function pointers for the rest of\n\t * the functions in that family.\n\t */\n\tswitch (hw->mac.type) {\n\tcase e1000_82575:\n\tcase e1000_82576:\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\te1000_init_function_pointers_82575(hw);\n\t\tbreak;\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\te1000_init_function_pointers_i210(hw);\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\"Hardware not supported\\n\");\n\t\tret_val = -E1000_ERR_CONFIG;\n\t\tbreak;\n\t}\n\n\t/*\n\t * Initialize the rest of the function pointers. These require some\n\t * register reads/writes in some cases.\n\t */\n\tif (!(ret_val) && init_device) {\n\t\tret_val = e1000_init_mac_params(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tret_val = e1000_init_nvm_params(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tret_val = e1000_init_phy_params(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\n\t\tret_val = e1000_init_mbx_params(hw);\n\t\tif (ret_val)\n\t\t\tgoto out;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_get_bus_info - Obtain bus information for adapter\n * @hw: pointer to the HW structure\n *\n * This will obtain information about the HW bus for which the\n * adapter is attached and stores it in the hw structure. This is a\n * function pointer entry point called by drivers.\n **/\ns32 e1000_get_bus_info(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.get_bus_info)\n\t\treturn hw->mac.ops.get_bus_info(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_clear_vfta - Clear VLAN filter table\n * @hw: pointer to the HW structure\n *\n * This clears the VLAN filter table on the adapter. This is a function\n * pointer entry point called by drivers.\n **/\nvoid e1000_clear_vfta(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.clear_vfta)\n\t\thw->mac.ops.clear_vfta(hw);\n}\n\n/**\n * e1000_write_vfta - Write value to VLAN filter table\n * @hw: pointer to the HW structure\n * @offset: the 32-bit offset in which to write the value to.\n * @value: the 32-bit value to write at location offset.\n *\n * This writes a 32-bit value to a 32-bit offset in the VLAN filter\n * table. This is a function pointer entry point called by drivers.\n **/\nvoid e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)\n{\n\tif (hw->mac.ops.write_vfta)\n\t\thw->mac.ops.write_vfta(hw, offset, value);\n}\n\n/**\n * e1000_update_mc_addr_list - Update Multicast addresses\n * @hw: pointer to the HW structure\n * @mc_addr_list: array of multicast addresses to program\n * @mc_addr_count: number of multicast addresses to program\n *\n * Updates the Multicast Table Array.\n * The caller must have a packed mc_addr_list of multicast addresses.\n **/\nvoid e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,\n\t\t\t u32 mc_addr_count)\n{\n\tif (hw->mac.ops.update_mc_addr_list)\n\t\thw->mac.ops.update_mc_addr_list(hw, mc_addr_list,\n\t\t\t\t\t\tmc_addr_count);\n}\n\n/**\n * e1000_force_mac_fc - Force MAC flow control\n * @hw: pointer to the HW structure\n *\n * Force the MAC's flow control settings. Currently no func pointer exists\n * and all implementations are handled in the generic version of this\n * function.\n **/\ns32 e1000_force_mac_fc(struct e1000_hw *hw)\n{\n\treturn e1000_force_mac_fc_generic(hw);\n}\n\n/**\n * e1000_check_for_link - Check/Store link connection\n * @hw: pointer to the HW structure\n *\n * This checks the link condition of the adapter and stores the\n * results in the hw->mac structure. This is a function pointer entry\n * point called by drivers.\n **/\ns32 e1000_check_for_link(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.check_for_link)\n\t\treturn hw->mac.ops.check_for_link(hw);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_check_mng_mode - Check management mode\n * @hw: pointer to the HW structure\n *\n * This checks if the adapter has manageability enabled.\n * This is a function pointer entry point called by drivers.\n **/\nbool e1000_check_mng_mode(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.check_mng_mode)\n\t\treturn hw->mac.ops.check_mng_mode(hw);\n\n\treturn false;\n}\n\n/**\n * e1000_mng_write_dhcp_info - Writes DHCP info to host interface\n * @hw: pointer to the HW structure\n * @buffer: pointer to the host interface\n * @length: size of the buffer\n *\n * Writes the DHCP information to the host interface.\n **/\ns32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)\n{\n\treturn e1000_mng_write_dhcp_info_generic(hw, buffer, length);\n}\n\n/**\n * e1000_reset_hw - Reset hardware\n * @hw: pointer to the HW structure\n *\n * This resets the hardware into a known state. This is a function pointer\n * entry point called by drivers.\n **/\ns32 e1000_reset_hw(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.reset_hw)\n\t\treturn hw->mac.ops.reset_hw(hw);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_init_hw - Initialize hardware\n * @hw: pointer to the HW structure\n *\n * This inits the hardware readying it for operation. This is a function\n * pointer entry point called by drivers.\n **/\ns32 e1000_init_hw(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.init_hw)\n\t\treturn hw->mac.ops.init_hw(hw);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_setup_link - Configures link and flow control\n * @hw: pointer to the HW structure\n *\n * This configures link and flow control settings for the adapter. This\n * is a function pointer entry point called by drivers. While modules can\n * also call this, they probably call their own version of this function.\n **/\ns32 e1000_setup_link(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.setup_link)\n\t\treturn hw->mac.ops.setup_link(hw);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_get_speed_and_duplex - Returns current speed and duplex\n * @hw: pointer to the HW structure\n * @speed: pointer to a 16-bit value to store the speed\n * @duplex: pointer to a 16-bit value to store the duplex.\n *\n * This returns the speed and duplex of the adapter in the two 'out'\n * variables passed in. This is a function pointer entry point called\n * by drivers.\n **/\ns32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)\n{\n\tif (hw->mac.ops.get_link_up_info)\n\t\treturn hw->mac.ops.get_link_up_info(hw, speed, duplex);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_setup_led - Configures SW controllable LED\n * @hw: pointer to the HW structure\n *\n * This prepares the SW controllable LED for use and saves the current state\n * of the LED so it can be later restored. This is a function pointer entry\n * point called by drivers.\n **/\ns32 e1000_setup_led(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.setup_led)\n\t\treturn hw->mac.ops.setup_led(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_cleanup_led - Restores SW controllable LED\n * @hw: pointer to the HW structure\n *\n * This restores the SW controllable LED to the value saved off by\n * e1000_setup_led. This is a function pointer entry point called by drivers.\n **/\ns32 e1000_cleanup_led(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.cleanup_led)\n\t\treturn hw->mac.ops.cleanup_led(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_blink_led - Blink SW controllable LED\n * @hw: pointer to the HW structure\n *\n * This starts the adapter LED blinking. Request the LED to be setup first\n * and cleaned up after. This is a function pointer entry point called by\n * drivers.\n **/\ns32 e1000_blink_led(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.blink_led)\n\t\treturn hw->mac.ops.blink_led(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_id_led_init - store LED configurations in SW\n * @hw: pointer to the HW structure\n *\n * Initializes the LED config in SW. This is a function pointer entry point\n * called by drivers.\n **/\ns32 e1000_id_led_init(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.id_led_init)\n\t\treturn hw->mac.ops.id_led_init(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_led_on - Turn on SW controllable LED\n * @hw: pointer to the HW structure\n *\n * Turns the SW defined LED on. This is a function pointer entry point\n * called by drivers.\n **/\ns32 e1000_led_on(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.led_on)\n\t\treturn hw->mac.ops.led_on(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_led_off - Turn off SW controllable LED\n * @hw: pointer to the HW structure\n *\n * Turns the SW defined LED off. This is a function pointer entry point\n * called by drivers.\n **/\ns32 e1000_led_off(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.led_off)\n\t\treturn hw->mac.ops.led_off(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_reset_adaptive - Reset adaptive IFS\n * @hw: pointer to the HW structure\n *\n * Resets the adaptive IFS. Currently no func pointer exists and all\n * implementations are handled in the generic version of this function.\n **/\nvoid e1000_reset_adaptive(struct e1000_hw *hw)\n{\n\te1000_reset_adaptive_generic(hw);\n}\n\n/**\n * e1000_update_adaptive - Update adaptive IFS\n * @hw: pointer to the HW structure\n *\n * Updates adapter IFS. Currently no func pointer exists and all\n * implementations are handled in the generic version of this function.\n **/\nvoid e1000_update_adaptive(struct e1000_hw *hw)\n{\n\te1000_update_adaptive_generic(hw);\n}\n\n/**\n * e1000_disable_pcie_master - Disable PCI-Express master access\n * @hw: pointer to the HW structure\n *\n * Disables PCI-Express master access and verifies there are no pending\n * requests. Currently no func pointer exists and all implementations are\n * handled in the generic version of this function.\n **/\ns32 e1000_disable_pcie_master(struct e1000_hw *hw)\n{\n\treturn e1000_disable_pcie_master_generic(hw);\n}\n\n/**\n * e1000_config_collision_dist - Configure collision distance\n * @hw: pointer to the HW structure\n *\n * Configures the collision distance to the default value and is used\n * during link setup.\n **/\nvoid e1000_config_collision_dist(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.config_collision_dist)\n\t\thw->mac.ops.config_collision_dist(hw);\n}\n\n/**\n * e1000_rar_set - Sets a receive address register\n * @hw: pointer to the HW structure\n * @addr: address to set the RAR to\n * @index: the RAR to set\n *\n * Sets a Receive Address Register (RAR) to the specified address.\n **/\nvoid e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)\n{\n\tif (hw->mac.ops.rar_set)\n\t\thw->mac.ops.rar_set(hw, addr, index);\n}\n\n/**\n * e1000_validate_mdi_setting - Ensures valid MDI/MDIX SW state\n * @hw: pointer to the HW structure\n *\n * Ensures that the MDI/MDIX SW state is valid.\n **/\ns32 e1000_validate_mdi_setting(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.validate_mdi_setting)\n\t\treturn hw->mac.ops.validate_mdi_setting(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_hash_mc_addr - Determines address location in multicast table\n * @hw: pointer to the HW structure\n * @mc_addr: Multicast address to hash.\n *\n * This hashes an address to determine its location in the multicast\n * table. Currently no func pointer exists and all implementations\n * are handled in the generic version of this function.\n **/\nu32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)\n{\n\treturn e1000_hash_mc_addr_generic(hw, mc_addr);\n}\n\n/**\n * e1000_enable_tx_pkt_filtering - Enable packet filtering on TX\n * @hw: pointer to the HW structure\n *\n * Enables packet filtering on transmit packets if manageability is enabled\n * and host interface is enabled.\n * Currently no func pointer exists and all implementations are handled in the\n * generic version of this function.\n **/\nbool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)\n{\n\treturn e1000_enable_tx_pkt_filtering_generic(hw);\n}\n\n/**\n * e1000_mng_host_if_write - Writes to the manageability host interface\n * @hw: pointer to the HW structure\n * @buffer: pointer to the host interface buffer\n * @length: size of the buffer\n * @offset: location in the buffer to write to\n * @sum: sum of the data (not checksum)\n *\n * This function writes the buffer content at the offset given on the host if.\n * It also does alignment considerations to do the writes in most efficient\n * way. Also fills up the sum of the buffer in *buffer parameter.\n **/\ns32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,\n\t\t\t u16 offset, u8 *sum)\n{\n\treturn e1000_mng_host_if_write_generic(hw, buffer, length, offset, sum);\n}\n\n/**\n * e1000_mng_write_cmd_header - Writes manageability command header\n * @hw: pointer to the HW structure\n * @hdr: pointer to the host interface command header\n *\n * Writes the command header after does the checksum calculation.\n **/\ns32 e1000_mng_write_cmd_header(struct e1000_hw *hw,\n\t\t\t struct e1000_host_mng_command_header *hdr)\n{\n\treturn e1000_mng_write_cmd_header_generic(hw, hdr);\n}\n\n/**\n * e1000_mng_enable_host_if - Checks host interface is enabled\n * @hw: pointer to the HW structure\n *\n * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND\n *\n * This function checks whether the HOST IF is enabled for command operation\n * and also checks whether the previous command is completed. It busy waits\n * in case of previous command is not completed.\n **/\ns32 e1000_mng_enable_host_if(struct e1000_hw *hw)\n{\n\treturn e1000_mng_enable_host_if_generic(hw);\n}\n\n/**\n * e1000_check_reset_block - Verifies PHY can be reset\n * @hw: pointer to the HW structure\n *\n * Checks if the PHY is in a state that can be reset or if manageability\n * has it tied up. This is a function pointer entry point called by drivers.\n **/\ns32 e1000_check_reset_block(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.check_reset_block)\n\t\treturn hw->phy.ops.check_reset_block(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_phy_reg - Reads PHY register\n * @hw: pointer to the HW structure\n * @offset: the register to read\n * @data: the buffer to store the 16-bit read.\n *\n * Reads the PHY register and returns the value in data.\n * This is a function pointer entry point called by drivers.\n **/\ns32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\tif (hw->phy.ops.read_reg)\n\t\treturn hw->phy.ops.read_reg(hw, offset, data);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_phy_reg - Writes PHY register\n * @hw: pointer to the HW structure\n * @offset: the register to write\n * @data: the value to write.\n *\n * Writes the PHY register at offset with the value in data.\n * This is a function pointer entry point called by drivers.\n **/\ns32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\tif (hw->phy.ops.write_reg)\n\t\treturn hw->phy.ops.write_reg(hw, offset, data);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_release_phy - Generic release PHY\n * @hw: pointer to the HW structure\n *\n * Return if silicon family does not require a semaphore when accessing the\n * PHY.\n **/\nvoid e1000_release_phy(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.release)\n\t\thw->phy.ops.release(hw);\n}\n\n/**\n * e1000_acquire_phy - Generic acquire PHY\n * @hw: pointer to the HW structure\n *\n * Return success if silicon family does not require a semaphore when\n * accessing the PHY.\n **/\ns32 e1000_acquire_phy(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.acquire)\n\t\treturn hw->phy.ops.acquire(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_kmrn_reg - Reads register using Kumeran interface\n * @hw: pointer to the HW structure\n * @offset: the register to read\n * @data: the location to store the 16-bit value read.\n *\n * Reads a register out of the Kumeran interface. Currently no func pointer\n * exists and all implementations are handled in the generic version of\n * this function.\n **/\ns32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn e1000_read_kmrn_reg_generic(hw, offset, data);\n}\n\n/**\n * e1000_write_kmrn_reg - Writes register using Kumeran interface\n * @hw: pointer to the HW structure\n * @offset: the register to write\n * @data: the value to write.\n *\n * Writes a register to the Kumeran interface. Currently no func pointer\n * exists and all implementations are handled in the generic version of\n * this function.\n **/\ns32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn e1000_write_kmrn_reg_generic(hw, offset, data);\n}\n\n/**\n * e1000_get_cable_length - Retrieves cable length estimation\n * @hw: pointer to the HW structure\n *\n * This function estimates the cable length and stores them in\n * hw->phy.min_length and hw->phy.max_length. This is a function pointer\n * entry point called by drivers.\n **/\ns32 e1000_get_cable_length(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.get_cable_length)\n\t\treturn hw->phy.ops.get_cable_length(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_phy_info - Retrieves PHY information from registers\n * @hw: pointer to the HW structure\n *\n * This function gets some information from various PHY registers and\n * populates hw->phy values with it. This is a function pointer entry\n * point called by drivers.\n **/\ns32 e1000_get_phy_info(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.get_info)\n\t\treturn hw->phy.ops.get_info(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_hw_reset - Hard PHY reset\n * @hw: pointer to the HW structure\n *\n * Performs a hard PHY reset. This is a function pointer entry point called\n * by drivers.\n **/\ns32 e1000_phy_hw_reset(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.reset)\n\t\treturn hw->phy.ops.reset(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_commit - Soft PHY reset\n * @hw: pointer to the HW structure\n *\n * Performs a soft PHY reset on those that apply. This is a function pointer\n * entry point called by drivers.\n **/\ns32 e1000_phy_commit(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.commit)\n\t\treturn hw->phy.ops.commit(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_d0_lplu_state - Sets low power link up state for D0\n * @hw: pointer to the HW structure\n * @active: boolean used to enable/disable lplu\n *\n * Success returns 0, Failure returns 1\n *\n * The low power link up (lplu) state is set to the power management level D0\n * and SmartSpeed is disabled when active is true, else clear lplu for D0\n * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU\n * is used during Dx states where the power conservation is most important.\n * During driver activity, SmartSpeed should be enabled so performance is\n * maintained. This is a function pointer entry point called by drivers.\n **/\ns32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)\n{\n\tif (hw->phy.ops.set_d0_lplu_state)\n\t\treturn hw->phy.ops.set_d0_lplu_state(hw, active);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_d3_lplu_state - Sets low power link up state for D3\n * @hw: pointer to the HW structure\n * @active: boolean used to enable/disable lplu\n *\n * Success returns 0, Failure returns 1\n *\n * The low power link up (lplu) state is set to the power management level D3\n * and SmartSpeed is disabled when active is true, else clear lplu for D3\n * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU\n * is used during Dx states where the power conservation is most important.\n * During driver activity, SmartSpeed should be enabled so performance is\n * maintained. This is a function pointer entry point called by drivers.\n **/\ns32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)\n{\n\tif (hw->phy.ops.set_d3_lplu_state)\n\t\treturn hw->phy.ops.set_d3_lplu_state(hw, active);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_mac_addr - Reads MAC address\n * @hw: pointer to the HW structure\n *\n * Reads the MAC address out of the adapter and stores it in the HW structure.\n * Currently no func pointer exists and all implementations are handled in the\n * generic version of this function.\n **/\ns32 e1000_read_mac_addr(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.read_mac_addr)\n\t\treturn hw->mac.ops.read_mac_addr(hw);\n\n\treturn e1000_read_mac_addr_generic(hw);\n}\n\n/**\n * e1000_read_pba_string - Read device part number string\n * @hw: pointer to the HW structure\n * @pba_num: pointer to device part number\n * @pba_num_size: size of part number buffer\n *\n * Reads the product board assembly (PBA) number from the EEPROM and stores\n * the value in pba_num.\n * Currently no func pointer exists and all implementations are handled in the\n * generic version of this function.\n **/\ns32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size)\n{\n\treturn e1000_read_pba_string_generic(hw, pba_num, pba_num_size);\n}\n\n/**\n * e1000_read_pba_length - Read device part number string length\n * @hw: pointer to the HW structure\n * @pba_num_size: size of part number buffer\n *\n * Reads the product board assembly (PBA) number length from the EEPROM and\n * stores the value in pba_num.\n * Currently no func pointer exists and all implementations are handled in the\n * generic version of this function.\n **/\ns32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size)\n{\n\treturn e1000_read_pba_length_generic(hw, pba_num_size);\n}\n\n/**\n * e1000_validate_nvm_checksum - Verifies NVM (EEPROM) checksum\n * @hw: pointer to the HW structure\n *\n * Validates the NVM checksum is correct. This is a function pointer entry\n * point called by drivers.\n **/\ns32 e1000_validate_nvm_checksum(struct e1000_hw *hw)\n{\n\tif (hw->nvm.ops.validate)\n\t\treturn hw->nvm.ops.validate(hw);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_update_nvm_checksum - Updates NVM (EEPROM) checksum\n * @hw: pointer to the HW structure\n *\n * Updates the NVM checksum. Currently no func pointer exists and all\n * implementations are handled in the generic version of this function.\n **/\ns32 e1000_update_nvm_checksum(struct e1000_hw *hw)\n{\n\tif (hw->nvm.ops.update)\n\t\treturn hw->nvm.ops.update(hw);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_reload_nvm - Reloads EEPROM\n * @hw: pointer to the HW structure\n *\n * Reloads the EEPROM by setting the \"Reinitialize from EEPROM\" bit in the\n * extended control register.\n **/\nvoid e1000_reload_nvm(struct e1000_hw *hw)\n{\n\tif (hw->nvm.ops.reload)\n\t\thw->nvm.ops.reload(hw);\n}\n\n/**\n * e1000_read_nvm - Reads NVM (EEPROM)\n * @hw: pointer to the HW structure\n * @offset: the word offset to read\n * @words: number of 16-bit words to read\n * @data: pointer to the properly sized buffer for the data.\n *\n * Reads 16-bit chunks of data from the NVM (EEPROM). This is a function\n * pointer entry point called by drivers.\n **/\ns32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)\n{\n\tif (hw->nvm.ops.read)\n\t\treturn hw->nvm.ops.read(hw, offset, words, data);\n\n\treturn -E1000_ERR_CONFIG;\n}\n\n/**\n * e1000_write_nvm - Writes to NVM (EEPROM)\n * @hw: pointer to the HW structure\n * @offset: the word offset to read\n * @words: number of 16-bit words to write\n * @data: pointer to the properly sized buffer for the data.\n *\n * Writes 16-bit chunks of data to the NVM (EEPROM). This is a function\n * pointer entry point called by drivers.\n **/\ns32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)\n{\n\tif (hw->nvm.ops.write)\n\t\treturn hw->nvm.ops.write(hw, offset, words, data);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_8bit_ctrl_reg - Writes 8bit Control register\n * @hw: pointer to the HW structure\n * @reg: 32bit register offset\n * @offset: the register to write\n * @data: the value to write.\n *\n * Writes the PHY register at offset with the value in data.\n * This is a function pointer entry point called by drivers.\n **/\ns32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,\n\t\t\t u8 data)\n{\n\treturn e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data);\n}\n\n/**\n * e1000_power_up_phy - Restores link in case of PHY power down\n * @hw: pointer to the HW structure\n *\n * The phy may be powered down to save power, to turn off link when the\n * driver is unloaded, or wake on lan is not enabled (among others).\n **/\nvoid e1000_power_up_phy(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.power_up)\n\t\thw->phy.ops.power_up(hw);\n\n\te1000_setup_link(hw);\n}\n\n/**\n * e1000_power_down_phy - Power down PHY\n * @hw: pointer to the HW structure\n *\n * The phy may be powered down to save power, to turn off link when the\n * driver is unloaded, or wake on lan is not enabled (among others).\n **/\nvoid e1000_power_down_phy(struct e1000_hw *hw)\n{\n\tif (hw->phy.ops.power_down)\n\t\thw->phy.ops.power_down(hw);\n}\n\n/**\n * e1000_power_up_fiber_serdes_link - Power up serdes link\n * @hw: pointer to the HW structure\n *\n * Power on the optics and PCS.\n **/\nvoid e1000_power_up_fiber_serdes_link(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.power_up_serdes)\n\t\thw->mac.ops.power_up_serdes(hw);\n}\n\n/**\n * e1000_shutdown_fiber_serdes_link - Remove link during power down\n * @hw: pointer to the HW structure\n *\n * Shutdown the optics and PCS on driver unload.\n **/\nvoid e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.shutdown_serdes)\n\t\thw->mac.ops.shutdown_serdes(hw);\n}\n\n/**\n * e1000_get_thermal_sensor_data - Gathers thermal sensor data\n * @hw: pointer to hardware structure\n *\n * Updates the temperatures in mac.thermal_sensor_data\n **/\ns32 e1000_get_thermal_sensor_data(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.get_thermal_sensor_data)\n\t\treturn hw->mac.ops.get_thermal_sensor_data(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_init_thermal_sensor_thresh - Sets thermal sensor thresholds\n * @hw: pointer to hardware structure\n *\n * Sets the thermal sensor thresholds according to the NVM map\n **/\ns32 e1000_init_thermal_sensor_thresh(struct e1000_hw *hw)\n{\n\tif (hw->mac.ops.init_thermal_sensor_thresh)\n\t\treturn hw->mac.ops.init_thermal_sensor_thresh(hw);\n\n\treturn E1000_SUCCESS;\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_api.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _E1000_API_H_\n#define _E1000_API_H_\n\n#include \"e1000_hw.h\"\n\nextern void e1000_init_function_pointers_82575(struct e1000_hw *hw);\nextern void e1000_rx_fifo_flush_82575(struct e1000_hw *hw);\nextern void e1000_init_function_pointers_vf(struct e1000_hw *hw);\nextern void e1000_power_up_fiber_serdes_link(struct e1000_hw *hw);\nextern void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw);\nextern void e1000_init_function_pointers_i210(struct e1000_hw *hw);\n\ns32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr);\ns32 e1000_set_mac_type(struct e1000_hw *hw);\ns32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device);\ns32 e1000_init_mac_params(struct e1000_hw *hw);\ns32 e1000_init_nvm_params(struct e1000_hw *hw);\ns32 e1000_init_phy_params(struct e1000_hw *hw);\ns32 e1000_init_mbx_params(struct e1000_hw *hw);\ns32 e1000_get_bus_info(struct e1000_hw *hw);\nvoid e1000_clear_vfta(struct e1000_hw *hw);\nvoid e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);\ns32 e1000_force_mac_fc(struct e1000_hw *hw);\ns32 e1000_check_for_link(struct e1000_hw *hw);\ns32 e1000_reset_hw(struct e1000_hw *hw);\ns32 e1000_init_hw(struct e1000_hw *hw);\ns32 e1000_setup_link(struct e1000_hw *hw);\ns32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex);\ns32 e1000_disable_pcie_master(struct e1000_hw *hw);\nvoid e1000_config_collision_dist(struct e1000_hw *hw);\nvoid e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);\nu32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);\nvoid e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,\n\t\t\t u32 mc_addr_count);\ns32 e1000_setup_led(struct e1000_hw *hw);\ns32 e1000_cleanup_led(struct e1000_hw *hw);\ns32 e1000_check_reset_block(struct e1000_hw *hw);\ns32 e1000_blink_led(struct e1000_hw *hw);\ns32 e1000_led_on(struct e1000_hw *hw);\ns32 e1000_led_off(struct e1000_hw *hw);\ns32 e1000_id_led_init(struct e1000_hw *hw);\nvoid e1000_reset_adaptive(struct e1000_hw *hw);\nvoid e1000_update_adaptive(struct e1000_hw *hw);\ns32 e1000_get_cable_length(struct e1000_hw *hw);\ns32 e1000_validate_mdi_setting(struct e1000_hw *hw);\ns32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,\n\t\t\t u8 data);\ns32 e1000_get_phy_info(struct e1000_hw *hw);\nvoid e1000_release_phy(struct e1000_hw *hw);\ns32 e1000_acquire_phy(struct e1000_hw *hw);\ns32 e1000_phy_hw_reset(struct e1000_hw *hw);\ns32 e1000_phy_commit(struct e1000_hw *hw);\nvoid e1000_power_up_phy(struct e1000_hw *hw);\nvoid e1000_power_down_phy(struct e1000_hw *hw);\ns32 e1000_read_mac_addr(struct e1000_hw *hw);\ns32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size);\ns32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size);\nvoid e1000_reload_nvm(struct e1000_hw *hw);\ns32 e1000_update_nvm_checksum(struct e1000_hw *hw);\ns32 e1000_validate_nvm_checksum(struct e1000_hw *hw);\ns32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);\ns32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);\ns32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);\ns32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);\nbool e1000_check_mng_mode(struct e1000_hw *hw);\nbool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);\ns32 e1000_mng_enable_host_if(struct e1000_hw *hw);\ns32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,\n\t\t\t u16 offset, u8 *sum);\ns32 e1000_mng_write_cmd_header(struct e1000_hw *hw,\n\t\t\t struct e1000_host_mng_command_header *hdr);\ns32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);\ns32 e1000_get_thermal_sensor_data(struct e1000_hw *hw);\ns32 e1000_init_thermal_sensor_thresh(struct e1000_hw *hw);\n\n\n\n/*\n * TBI_ACCEPT macro definition:\n *\n * This macro requires:\n * adapter = a pointer to struct e1000_hw\n * status = the 8 bit status field of the Rx descriptor with EOP set\n * error = the 8 bit error field of the Rx descriptor with EOP set\n * length = the sum of all the length fields of the Rx descriptors that\n * make up the current frame\n * last_byte = the last byte of the frame DMAed by the hardware\n * max_frame_length = the maximum frame length we want to accept.\n * min_frame_length = the minimum frame length we want to accept.\n *\n * This macro is a conditional that should be used in the interrupt\n * handler's Rx processing routine when RxErrors have been detected.\n *\n * Typical use:\n * ...\n * if (TBI_ACCEPT) {\n * accept_frame = true;\n * e1000_tbi_adjust_stats(adapter, MacAddress);\n * frame_length--;\n * } else {\n * accept_frame = false;\n * }\n * ...\n */\n\n/* The carrier extension symbol, as received by the NIC. */\n#define CARRIER_EXTENSION 0x0F\n\n#define TBI_ACCEPT(a, status, errors, length, last_byte, \\\n\t\t min_frame_size, max_frame_size) \\\n\t(e1000_tbi_sbp_enabled_82543(a) && \\\n\t (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \\\n\t ((last_byte) == CARRIER_EXTENSION) && \\\n\t (((status) & E1000_RXD_STAT_VP) ? \\\n\t (((length) > (min_frame_size - VLAN_TAG_SIZE)) && \\\n\t ((length) <= (max_frame_size + 1))) : \\\n\t (((length) > min_frame_size) && \\\n\t ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1)))))\n\n#ifndef E1000_MAX\n#define E1000_MAX(a, b) ((a) > (b) ? (a) : (b))\n#endif\n#ifndef E1000_DIVIDE_ROUND_UP\n#define E1000_DIVIDE_ROUND_UP(a, b)\t(((a) + (b) - 1) / (b)) /* ceil(a/b) */\n#endif\n#endif /* _E1000_API_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_defines.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _E1000_DEFINES_H_\n#define _E1000_DEFINES_H_\n\n/* Number of Transmit and Receive Descriptors must be a multiple of 8 */\n#define REQ_TX_DESCRIPTOR_MULTIPLE 8\n#define REQ_RX_DESCRIPTOR_MULTIPLE 8\n\n/* Definitions for power management and wakeup registers */\n/* Wake Up Control */\n#define E1000_WUC_APME\t\t0x00000001 /* APM Enable */\n#define E1000_WUC_PME_EN\t0x00000002 /* PME Enable */\n#define E1000_WUC_PME_STATUS\t0x00000004 /* PME Status */\n#define E1000_WUC_APMPME\t0x00000008 /* Assert PME on APM Wakeup */\n#define E1000_WUC_PHY_WAKE\t0x00000100 /* if PHY supports wakeup */\n\n/* Wake Up Filter Control */\n#define E1000_WUFC_LNKC\t0x00000001 /* Link Status Change Wakeup Enable */\n#define E1000_WUFC_MAG\t0x00000002 /* Magic Packet Wakeup Enable */\n#define E1000_WUFC_EX\t0x00000004 /* Directed Exact Wakeup Enable */\n#define E1000_WUFC_MC\t0x00000008 /* Directed Multicast Wakeup Enable */\n#define E1000_WUFC_BC\t0x00000010 /* Broadcast Wakeup Enable */\n#define E1000_WUFC_ARP\t0x00000020 /* ARP Request Packet Wakeup Enable */\n#define E1000_WUFC_IPV4\t0x00000040 /* Directed IPv4 Packet Wakeup Enable */\n#define E1000_WUFC_FLX0\t\t0x00010000 /* Flexible Filter 0 Enable */\n\n/* Wake Up Status */\n#define E1000_WUS_LNKC\t\tE1000_WUFC_LNKC\n#define E1000_WUS_MAG\t\tE1000_WUFC_MAG\n#define E1000_WUS_EX\t\tE1000_WUFC_EX\n#define E1000_WUS_MC\t\tE1000_WUFC_MC\n#define E1000_WUS_BC\t\tE1000_WUFC_BC\n\n/* Extended Device Control */\n#define E1000_CTRL_EXT_SDP4_DATA\t0x00000010 /* SW Definable Pin 4 data */\n#define E1000_CTRL_EXT_SDP6_DATA\t0x00000040 /* SW Definable Pin 6 data */\n#define E1000_CTRL_EXT_SDP3_DATA\t0x00000080 /* SW Definable Pin 3 data */\n#define E1000_CTRL_EXT_SDP6_DIR\t0x00000400 /* Direction of SDP6 0=in 1=out */\n#define E1000_CTRL_EXT_SDP3_DIR\t0x00000800 /* Direction of SDP3 0=in 1=out */\n#define E1000_CTRL_EXT_EE_RST\t0x00002000 /* Reinitialize from EEPROM */\n/* Physical Func Reset Done Indication */\n#define E1000_CTRL_EXT_PFRSTD\t0x00004000\n#define E1000_CTRL_EXT_SPD_BYPS\t0x00008000 /* Speed Select Bypass */\n#define E1000_CTRL_EXT_RO_DIS\t0x00020000 /* Relaxed Ordering disable */\n#define E1000_CTRL_EXT_DMA_DYN_CLK_EN\t0x00080000 /* DMA Dynamic Clk Gating */\n#define E1000_CTRL_EXT_LINK_MODE_MASK\t0x00C00000\n/* Offset of the link mode field in Ctrl Ext register */\n#define E1000_CTRL_EXT_LINK_MODE_OFFSET\t22\n#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX\t0x00400000\n#define E1000_CTRL_EXT_LINK_MODE_GMII\t0x00000000\n#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES\t0x00C00000\n#define E1000_CTRL_EXT_LINK_MODE_SGMII\t0x00800000\n#define E1000_CTRL_EXT_EIAME\t\t0x01000000\n#define E1000_CTRL_EXT_IRCA\t\t0x00000001\n#define E1000_CTRL_EXT_DRV_LOAD\t\t0x10000000 /* Drv loaded bit for FW */\n#define E1000_CTRL_EXT_IAME\t\t0x08000000 /* Int ACK Auto-mask */\n#define E1000_CTRL_EXT_PBA_CLR\t\t0x80000000 /* PBA Clear */\n#define E1000_I2CCMD_REG_ADDR_SHIFT\t16\n#define E1000_I2CCMD_PHY_ADDR_SHIFT\t24\n#define E1000_I2CCMD_OPCODE_READ\t0x08000000\n#define E1000_I2CCMD_OPCODE_WRITE\t0x00000000\n#define E1000_I2CCMD_READY\t\t0x20000000\n#define E1000_I2CCMD_ERROR\t\t0x80000000\n#define E1000_I2CCMD_SFP_DATA_ADDR(a)\t(0x0000 + (a))\n#define E1000_I2CCMD_SFP_DIAG_ADDR(a)\t(0x0100 + (a))\n#define E1000_MAX_SGMII_PHY_REG_ADDR\t255\n#define E1000_I2CCMD_PHY_TIMEOUT\t200\n#define E1000_IVAR_VALID\t0x80\n#define E1000_GPIE_NSICR\t0x00000001\n#define E1000_GPIE_MSIX_MODE\t0x00000010\n#define E1000_GPIE_EIAME\t0x40000000\n#define E1000_GPIE_PBA\t\t0x80000000\n\n/* Receive Descriptor bit definitions */\n#define E1000_RXD_STAT_DD\t0x01 /* Descriptor Done */\n#define E1000_RXD_STAT_EOP\t0x02 /* End of Packet */\n#define E1000_RXD_STAT_IXSM\t0x04 /* Ignore checksum */\n#define E1000_RXD_STAT_VP\t0x08 /* IEEE VLAN Packet */\n#define E1000_RXD_STAT_UDPCS\t0x10 /* UDP xsum calculated */\n#define E1000_RXD_STAT_TCPCS\t0x20 /* TCP xsum calculated */\n#define E1000_RXD_STAT_IPCS\t0x40 /* IP xsum calculated */\n#define E1000_RXD_STAT_PIF\t0x80 /* passed in-exact filter */\n#define E1000_RXD_STAT_IPIDV\t0x200 /* IP identification valid */\n#define E1000_RXD_STAT_UDPV\t0x400 /* Valid UDP checksum */\n#define E1000_RXD_STAT_DYNINT\t0x800 /* Pkt caused INT via DYNINT */\n#define E1000_RXD_ERR_CE\t0x01 /* CRC Error */\n#define E1000_RXD_ERR_SE\t0x02 /* Symbol Error */\n#define E1000_RXD_ERR_SEQ\t0x04 /* Sequence Error */\n#define E1000_RXD_ERR_CXE\t0x10 /* Carrier Extension Error */\n#define E1000_RXD_ERR_TCPE\t0x20 /* TCP/UDP Checksum Error */\n#define E1000_RXD_ERR_IPE\t0x40 /* IP Checksum Error */\n#define E1000_RXD_ERR_RXE\t0x80 /* Rx Data Error */\n#define E1000_RXD_SPC_VLAN_MASK\t0x0FFF /* VLAN ID is in lower 12 bits */\n\n#define E1000_RXDEXT_STATERR_TST\t0x00000100 /* Time Stamp taken */\n#define E1000_RXDEXT_STATERR_LB\t\t0x00040000\n#define E1000_RXDEXT_STATERR_CE\t\t0x01000000\n#define E1000_RXDEXT_STATERR_SE\t\t0x02000000\n#define E1000_RXDEXT_STATERR_SEQ\t0x04000000\n#define E1000_RXDEXT_STATERR_CXE\t0x10000000\n#define E1000_RXDEXT_STATERR_TCPE\t0x20000000\n#define E1000_RXDEXT_STATERR_IPE\t0x40000000\n#define E1000_RXDEXT_STATERR_RXE\t0x80000000\n\n/* mask to determine if packets should be dropped due to frame errors */\n#define E1000_RXD_ERR_FRAME_ERR_MASK ( \\\n\tE1000_RXD_ERR_CE |\t\t\\\n\tE1000_RXD_ERR_SE |\t\t\\\n\tE1000_RXD_ERR_SEQ |\t\t\\\n\tE1000_RXD_ERR_CXE |\t\t\\\n\tE1000_RXD_ERR_RXE)\n\n/* Same mask, but for extended and packet split descriptors */\n#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \\\n\tE1000_RXDEXT_STATERR_CE |\t\\\n\tE1000_RXDEXT_STATERR_SE |\t\\\n\tE1000_RXDEXT_STATERR_SEQ |\t\\\n\tE1000_RXDEXT_STATERR_CXE |\t\\\n\tE1000_RXDEXT_STATERR_RXE)\n\n#define E1000_MRQC_RSS_FIELD_MASK\t\t0xFFFF0000\n#define E1000_MRQC_RSS_FIELD_IPV4_TCP\t\t0x00010000\n#define E1000_MRQC_RSS_FIELD_IPV4\t\t0x00020000\n#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX\t0x00040000\n#define E1000_MRQC_RSS_FIELD_IPV6\t\t0x00100000\n#define E1000_MRQC_RSS_FIELD_IPV6_TCP\t\t0x00200000\n\n#define E1000_RXDPS_HDRSTAT_HDRSP\t\t0x00008000\n\n/* Management Control */\n#define E1000_MANC_SMBUS_EN\t0x00000001 /* SMBus Enabled - RO */\n#define E1000_MANC_ASF_EN\t0x00000002 /* ASF Enabled - RO */\n#define E1000_MANC_ARP_EN\t0x00002000 /* Enable ARP Request Filtering */\n#define E1000_MANC_RCV_TCO_EN\t0x00020000 /* Receive TCO Packets Enabled */\n#define E1000_MANC_BLK_PHY_RST_ON_IDE\t0x00040000 /* Block phy resets */\n/* Enable MAC address filtering */\n#define E1000_MANC_EN_MAC_ADDR_FILTER\t0x00100000\n/* Enable MNG packets to host memory */\n#define E1000_MANC_EN_MNG2HOST\t\t0x00200000\n\n#define E1000_MANC2H_PORT_623\t\t0x00000020 /* Port 0x26f */\n#define E1000_MANC2H_PORT_664\t\t0x00000040 /* Port 0x298 */\n#define E1000_MDEF_PORT_623\t\t0x00000800 /* Port 0x26f */\n#define E1000_MDEF_PORT_664\t\t0x00000400 /* Port 0x298 */\n\n/* Receive Control */\n#define E1000_RCTL_RST\t\t0x00000001 /* Software reset */\n#define E1000_RCTL_EN\t\t0x00000002 /* enable */\n#define E1000_RCTL_SBP\t\t0x00000004 /* store bad packet */\n#define E1000_RCTL_UPE\t\t0x00000008 /* unicast promisc enable */\n#define E1000_RCTL_MPE\t\t0x00000010 /* multicast promisc enable */\n#define E1000_RCTL_LPE\t\t0x00000020 /* long packet enable */\n#define E1000_RCTL_LBM_NO\t0x00000000 /* no loopback mode */\n#define E1000_RCTL_LBM_MAC\t0x00000040 /* MAC loopback mode */\n#define E1000_RCTL_LBM_TCVR\t0x000000C0 /* tcvr loopback mode */\n#define E1000_RCTL_DTYP_PS\t0x00000400 /* Packet Split descriptor */\n#define E1000_RCTL_RDMTS_HALF\t0x00000000 /* Rx desc min thresh size */\n#define E1000_RCTL_MO_SHIFT\t12 /* multicast offset shift */\n#define E1000_RCTL_MO_3\t\t0x00003000 /* multicast offset 15:4 */\n#define E1000_RCTL_BAM\t\t0x00008000 /* broadcast enable */\n/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */\n#define E1000_RCTL_SZ_2048\t0x00000000 /* Rx buffer size 2048 */\n#define E1000_RCTL_SZ_1024\t0x00010000 /* Rx buffer size 1024 */\n#define E1000_RCTL_SZ_512\t0x00020000 /* Rx buffer size 512 */\n#define E1000_RCTL_SZ_256\t0x00030000 /* Rx buffer size 256 */\n/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */\n#define E1000_RCTL_SZ_16384\t0x00010000 /* Rx buffer size 16384 */\n#define E1000_RCTL_SZ_8192\t0x00020000 /* Rx buffer size 8192 */\n#define E1000_RCTL_SZ_4096\t0x00030000 /* Rx buffer size 4096 */\n#define E1000_RCTL_VFE\t\t0x00040000 /* vlan filter enable */\n#define E1000_RCTL_CFIEN\t0x00080000 /* canonical form enable */\n#define E1000_RCTL_CFI\t\t0x00100000 /* canonical form indicator */\n#define E1000_RCTL_DPF\t\t0x00400000 /* discard pause frames */\n#define E1000_RCTL_PMCF\t\t0x00800000 /* pass MAC control frames */\n#define E1000_RCTL_BSEX\t\t0x02000000 /* Buffer size extension */\n#define E1000_RCTL_SECRC\t0x04000000 /* Strip Ethernet CRC */\n\n/* Use byte values for the following shift parameters\n * Usage:\n * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &\n *\t\t E1000_PSRCTL_BSIZE0_MASK) |\n *\t\t((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &\n *\t\t E1000_PSRCTL_BSIZE1_MASK) |\n *\t\t((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &\n *\t\t E1000_PSRCTL_BSIZE2_MASK) |\n *\t\t((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;\n *\t\t E1000_PSRCTL_BSIZE3_MASK))\n * where value0 = [128..16256], default=256\n * value1 = [1024..64512], default=4096\n * value2 = [0..64512], default=4096\n * value3 = [0..64512], default=0\n */\n\n#define E1000_PSRCTL_BSIZE0_MASK\t0x0000007F\n#define E1000_PSRCTL_BSIZE1_MASK\t0x00003F00\n#define E1000_PSRCTL_BSIZE2_MASK\t0x003F0000\n#define E1000_PSRCTL_BSIZE3_MASK\t0x3F000000\n\n#define E1000_PSRCTL_BSIZE0_SHIFT\t7 /* Shift _right_ 7 */\n#define E1000_PSRCTL_BSIZE1_SHIFT\t2 /* Shift _right_ 2 */\n#define E1000_PSRCTL_BSIZE2_SHIFT\t6 /* Shift _left_ 6 */\n#define E1000_PSRCTL_BSIZE3_SHIFT\t14 /* Shift _left_ 14 */\n\n/* SWFW_SYNC Definitions */\n#define E1000_SWFW_EEP_SM\t0x01\n#define E1000_SWFW_PHY0_SM\t0x02\n#define E1000_SWFW_PHY1_SM\t0x04\n#define E1000_SWFW_CSR_SM\t0x08\n#define E1000_SWFW_PHY2_SM\t0x20\n#define E1000_SWFW_PHY3_SM\t0x40\n#define E1000_SWFW_SW_MNG_SM\t0x400\n\n/* Device Control */\n#define E1000_CTRL_FD\t\t0x00000001 /* Full duplex.0=half; 1=full */\n#define E1000_CTRL_PRIOR\t0x00000004 /* Priority on PCI. 0=rx,1=fair */\n#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */\n#define E1000_CTRL_LRST\t\t0x00000008 /* Link reset. 0=normal,1=reset */\n#define E1000_CTRL_ASDE\t\t0x00000020 /* Auto-speed detect enable */\n#define E1000_CTRL_SLU\t\t0x00000040 /* Set link up (Force Link) */\n#define E1000_CTRL_ILOS\t\t0x00000080 /* Invert Loss-Of Signal */\n#define E1000_CTRL_SPD_SEL\t0x00000300 /* Speed Select Mask */\n#define E1000_CTRL_SPD_10\t0x00000000 /* Force 10Mb */\n#define E1000_CTRL_SPD_100\t0x00000100 /* Force 100Mb */\n#define E1000_CTRL_SPD_1000\t0x00000200 /* Force 1Gb */\n#define E1000_CTRL_FRCSPD\t0x00000800 /* Force Speed */\n#define E1000_CTRL_FRCDPX\t0x00001000 /* Force Duplex */\n#define E1000_CTRL_SWDPIN0\t0x00040000 /* SWDPIN 0 value */\n#define E1000_CTRL_SWDPIN1\t0x00080000 /* SWDPIN 1 value */\n#define E1000_CTRL_SWDPIN2\t0x00100000 /* SWDPIN 2 value */\n#define E1000_CTRL_ADVD3WUC\t0x00100000 /* D3 WUC */\n#define E1000_CTRL_SWDPIN3\t0x00200000 /* SWDPIN 3 value */\n#define E1000_CTRL_SWDPIO0\t0x00400000 /* SWDPIN 0 Input or output */\n#define E1000_CTRL_RST\t\t0x04000000 /* Global reset */\n#define E1000_CTRL_RFCE\t\t0x08000000 /* Receive Flow Control enable */\n#define E1000_CTRL_TFCE\t\t0x10000000 /* Transmit flow control enable */\n#define E1000_CTRL_VME\t\t0x40000000 /* IEEE VLAN mode enable */\n#define E1000_CTRL_PHY_RST\t0x80000000 /* PHY Reset */\n#define E1000_CTRL_I2C_ENA\t0x02000000 /* I2C enable */\n\n\n#define E1000_CONNSW_ENRGSRC\t\t0x4\n#define E1000_CONNSW_PHYSD\t\t0x400\n#define E1000_CONNSW_PHY_PDN\t\t0x800\n#define E1000_CONNSW_SERDESD\t\t0x200\n#define E1000_CONNSW_AUTOSENSE_CONF\t0x2\n#define E1000_CONNSW_AUTOSENSE_EN\t0x1\n#define E1000_PCS_CFG_PCS_EN\t\t8\n#define E1000_PCS_LCTL_FLV_LINK_UP\t1\n#define E1000_PCS_LCTL_FSV_10\t\t0\n#define E1000_PCS_LCTL_FSV_100\t\t2\n#define E1000_PCS_LCTL_FSV_1000\t\t4\n#define E1000_PCS_LCTL_FDV_FULL\t\t8\n#define E1000_PCS_LCTL_FSD\t\t0x10\n#define E1000_PCS_LCTL_FORCE_LINK\t0x20\n#define E1000_PCS_LCTL_FORCE_FCTRL\t0x80\n#define E1000_PCS_LCTL_AN_ENABLE\t0x10000\n#define E1000_PCS_LCTL_AN_RESTART\t0x20000\n#define E1000_PCS_LCTL_AN_TIMEOUT\t0x40000\n#define E1000_ENABLE_SERDES_LOOPBACK\t0x0410\n\n#define E1000_PCS_LSTS_LINK_OK\t\t1\n#define E1000_PCS_LSTS_SPEED_100\t2\n#define E1000_PCS_LSTS_SPEED_1000\t4\n#define E1000_PCS_LSTS_DUPLEX_FULL\t8\n#define E1000_PCS_LSTS_SYNK_OK\t\t0x10\n#define E1000_PCS_LSTS_AN_COMPLETE\t0x10000\n\n/* Device Status */\n#define E1000_STATUS_FD\t\t\t0x00000001 /* Duplex 0=half 1=full */\n#define E1000_STATUS_LU\t\t\t0x00000002 /* Link up.0=no,1=link */\n#define E1000_STATUS_FUNC_MASK\t\t0x0000000C /* PCI Function Mask */\n#define E1000_STATUS_FUNC_SHIFT\t\t2\n#define E1000_STATUS_FUNC_1\t\t0x00000004 /* Function 1 */\n#define E1000_STATUS_TXOFF\t\t0x00000010 /* transmission paused */\n#define E1000_STATUS_SPEED_MASK\t0x000000C0\n#define E1000_STATUS_SPEED_10\t\t0x00000000 /* Speed 10Mb/s */\n#define E1000_STATUS_SPEED_100\t\t0x00000040 /* Speed 100Mb/s */\n#define E1000_STATUS_SPEED_1000\t\t0x00000080 /* Speed 1000Mb/s */\n#define E1000_STATUS_LAN_INIT_DONE\t0x00000200 /* Lan Init Compltn by NVM */\n#define E1000_STATUS_PHYRA\t\t0x00000400 /* PHY Reset Asserted */\n#define E1000_STATUS_GIO_MASTER_ENABLE\t0x00080000 /* Master request status */\n#define E1000_STATUS_2P5_SKU\t\t0x00001000 /* Val of 2.5GBE SKU strap */\n#define E1000_STATUS_2P5_SKU_OVER\t0x00002000 /* Val of 2.5GBE SKU Over */\n\n#define SPEED_10\t10\n#define SPEED_100\t100\n#define SPEED_1000\t1000\n#define SPEED_2500\t2500\n#define HALF_DUPLEX\t1\n#define FULL_DUPLEX\t2\n\n\n#define ADVERTISE_10_HALF\t\t0x0001\n#define ADVERTISE_10_FULL\t\t0x0002\n#define ADVERTISE_100_HALF\t\t0x0004\n#define ADVERTISE_100_FULL\t\t0x0008\n#define ADVERTISE_1000_HALF\t\t0x0010 /* Not used, just FYI */\n#define ADVERTISE_1000_FULL\t\t0x0020\n\n/* 1000/H is not supported, nor spec-compliant. */\n#define E1000_ALL_SPEED_DUPLEX\t( \\\n\tADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \\\n\tADVERTISE_100_FULL | ADVERTISE_1000_FULL)\n#define E1000_ALL_NOT_GIG\t( \\\n\tADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \\\n\tADVERTISE_100_FULL)\n#define E1000_ALL_100_SPEED\t(ADVERTISE_100_HALF | ADVERTISE_100_FULL)\n#define E1000_ALL_10_SPEED\t(ADVERTISE_10_HALF | ADVERTISE_10_FULL)\n#define E1000_ALL_HALF_DUPLEX\t(ADVERTISE_10_HALF | ADVERTISE_100_HALF)\n\n#define AUTONEG_ADVERTISE_SPEED_DEFAULT\t\tE1000_ALL_SPEED_DUPLEX\n\n/* LED Control */\n#define E1000_LEDCTL_LED0_MODE_MASK\t0x0000000F\n#define E1000_LEDCTL_LED0_MODE_SHIFT\t0\n#define E1000_LEDCTL_LED0_IVRT\t\t0x00000040\n#define E1000_LEDCTL_LED0_BLINK\t\t0x00000080\n\n#define E1000_LEDCTL_MODE_LED_ON\t0xE\n#define E1000_LEDCTL_MODE_LED_OFF\t0xF\n\n/* Transmit Descriptor bit definitions */\n#define E1000_TXD_DTYP_D\t0x00100000 /* Data Descriptor */\n#define E1000_TXD_DTYP_C\t0x00000000 /* Context Descriptor */\n#define E1000_TXD_POPTS_IXSM\t0x01 /* Insert IP checksum */\n#define E1000_TXD_POPTS_TXSM\t0x02 /* Insert TCP/UDP checksum */\n#define E1000_TXD_CMD_EOP\t0x01000000 /* End of Packet */\n#define E1000_TXD_CMD_IFCS\t0x02000000 /* Insert FCS (Ethernet CRC) */\n#define E1000_TXD_CMD_IC\t0x04000000 /* Insert Checksum */\n#define E1000_TXD_CMD_RS\t0x08000000 /* Report Status */\n#define E1000_TXD_CMD_RPS\t0x10000000 /* Report Packet Sent */\n#define E1000_TXD_CMD_DEXT\t0x20000000 /* Desc extension (0 = legacy) */\n#define E1000_TXD_CMD_VLE\t0x40000000 /* Add VLAN tag */\n#define E1000_TXD_CMD_IDE\t0x80000000 /* Enable Tidv register */\n#define E1000_TXD_STAT_DD\t0x00000001 /* Descriptor Done */\n#define E1000_TXD_STAT_EC\t0x00000002 /* Excess Collisions */\n#define E1000_TXD_STAT_LC\t0x00000004 /* Late Collisions */\n#define E1000_TXD_STAT_TU\t0x00000008 /* Transmit underrun */\n#define E1000_TXD_CMD_TCP\t0x01000000 /* TCP packet */\n#define E1000_TXD_CMD_IP\t0x02000000 /* IP packet */\n#define E1000_TXD_CMD_TSE\t0x04000000 /* TCP Seg enable */\n#define E1000_TXD_STAT_TC\t0x00000004 /* Tx Underrun */\n#define E1000_TXD_EXTCMD_TSTAMP\t0x00000010 /* IEEE1588 Timestamp packet */\n\n/* Transmit Control */\n#define E1000_TCTL_EN\t\t0x00000002 /* enable Tx */\n#define E1000_TCTL_PSP\t\t0x00000008 /* pad short packets */\n#define E1000_TCTL_CT\t\t0x00000ff0 /* collision threshold */\n#define E1000_TCTL_COLD\t\t0x003ff000 /* collision distance */\n#define E1000_TCTL_RTLC\t\t0x01000000 /* Re-transmit on late collision */\n#define E1000_TCTL_MULR\t\t0x10000000 /* Multiple request support */\n\n/* Transmit Arbitration Count */\n#define E1000_TARC0_ENABLE\t0x00000400 /* Enable Tx Queue 0 */\n\n/* SerDes Control */\n#define E1000_SCTL_DISABLE_SERDES_LOOPBACK\t0x0400\n#define E1000_SCTL_ENABLE_SERDES_LOOPBACK\t0x0410\n\n/* Receive Checksum Control */\n#define E1000_RXCSUM_IPOFL\t0x00000100 /* IPv4 checksum offload */\n#define E1000_RXCSUM_TUOFL\t0x00000200 /* TCP / UDP checksum offload */\n#define E1000_RXCSUM_CRCOFL\t0x00000800 /* CRC32 offload enable */\n#define E1000_RXCSUM_IPPCSE\t0x00001000 /* IP payload checksum enable */\n#define E1000_RXCSUM_PCSD\t0x00002000 /* packet checksum disabled */\n\n/* Header split receive */\n#define E1000_RFCTL_NFSW_DIS\t\t0x00000040\n#define E1000_RFCTL_NFSR_DIS\t\t0x00000080\n#define E1000_RFCTL_ACK_DIS\t\t0x00001000\n#define E1000_RFCTL_EXTEN\t\t0x00008000\n#define E1000_RFCTL_IPV6_EX_DIS\t\t0x00010000\n#define E1000_RFCTL_NEW_IPV6_EXT_DIS\t0x00020000\n#define E1000_RFCTL_LEF\t\t\t0x00040000\n\n/* Collision related configuration parameters */\n#define E1000_COLLISION_THRESHOLD\t15\n#define E1000_CT_SHIFT\t\t\t4\n#define E1000_COLLISION_DISTANCE\t63\n#define E1000_COLD_SHIFT\t\t12\n\n/* Default values for the transmit IPG register */\n#define DEFAULT_82543_TIPG_IPGT_FIBER\t9\n#define DEFAULT_82543_TIPG_IPGT_COPPER\t8\n\n#define E1000_TIPG_IPGT_MASK\t\t0x000003FF\n\n#define DEFAULT_82543_TIPG_IPGR1\t8\n#define E1000_TIPG_IPGR1_SHIFT\t\t10\n\n#define DEFAULT_82543_TIPG_IPGR2\t6\n#define DEFAULT_80003ES2LAN_TIPG_IPGR2\t7\n#define E1000_TIPG_IPGR2_SHIFT\t\t20\n\n/* Ethertype field values */\n#define ETHERNET_IEEE_VLAN_TYPE\t\t0x8100 /* 802.3ac packet */\n\n#define ETHERNET_FCS_SIZE\t\t4\n#define MAX_JUMBO_FRAME_SIZE\t\t0x3F00\n\n/* Extended Configuration Control and Size */\n#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP\t0x00000020\n#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE\t0x00000001\n#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE\t0x00000008\n#define E1000_EXTCNF_CTRL_SWFLAG\t\t0x00000020\n#define E1000_EXTCNF_CTRL_GATE_PHY_CFG\t\t0x00000080\n#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK\t0x00FF0000\n#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT\t16\n#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK\t0x0FFF0000\n#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT\t16\n\n#define E1000_PHY_CTRL_D0A_LPLU\t\t\t0x00000002\n#define E1000_PHY_CTRL_NOND0A_LPLU\t\t0x00000004\n#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE\t0x00000008\n#define E1000_PHY_CTRL_GBE_DISABLE\t\t0x00000040\n\n#define E1000_KABGTXD_BGSQLBIAS\t\t\t0x00050000\n\n/* PBA constants */\n#define E1000_PBA_8K\t\t0x0008 /* 8KB */\n#define E1000_PBA_10K\t\t0x000A /* 10KB */\n#define E1000_PBA_12K\t\t0x000C /* 12KB */\n#define E1000_PBA_14K\t\t0x000E /* 14KB */\n#define E1000_PBA_16K\t\t0x0010 /* 16KB */\n#define E1000_PBA_18K\t\t0x0012\n#define E1000_PBA_20K\t\t0x0014\n#define E1000_PBA_22K\t\t0x0016\n#define E1000_PBA_24K\t\t0x0018\n#define E1000_PBA_26K\t\t0x001A\n#define E1000_PBA_30K\t\t0x001E\n#define E1000_PBA_32K\t\t0x0020\n#define E1000_PBA_34K\t\t0x0022\n#define E1000_PBA_35K\t\t0x0023\n#define E1000_PBA_38K\t\t0x0026\n#define E1000_PBA_40K\t\t0x0028\n#define E1000_PBA_48K\t\t0x0030 /* 48KB */\n#define E1000_PBA_64K\t\t0x0040 /* 64KB */\n\n#define E1000_PBA_RXA_MASK\t0xFFFF\n\n#define E1000_PBS_16K\t\tE1000_PBA_16K\n\n#define IFS_MAX\t\t\t80\n#define IFS_MIN\t\t\t40\n#define IFS_RATIO\t\t4\n#define IFS_STEP\t\t10\n#define MIN_NUM_XMITS\t\t1000\n\n/* SW Semaphore Register */\n#define E1000_SWSM_SMBI\t\t0x00000001 /* Driver Semaphore bit */\n#define E1000_SWSM_SWESMBI\t0x00000002 /* FW Semaphore bit */\n#define E1000_SWSM_DRV_LOAD\t0x00000008 /* Driver Loaded Bit */\n\n#define E1000_SWSM2_LOCK\t0x00000002 /* Secondary driver semaphore bit */\n\n/* Interrupt Cause Read */\n#define E1000_ICR_TXDW\t\t0x00000001 /* Transmit desc written back */\n#define E1000_ICR_TXQE\t\t0x00000002 /* Transmit Queue empty */\n#define E1000_ICR_LSC\t\t0x00000004 /* Link Status Change */\n#define E1000_ICR_RXSEQ\t\t0x00000008 /* Rx sequence error */\n#define E1000_ICR_RXDMT0\t0x00000010 /* Rx desc min. threshold (0) */\n#define E1000_ICR_RXO\t\t0x00000040 /* Rx overrun */\n#define E1000_ICR_RXT0\t\t0x00000080 /* Rx timer intr (ring 0) */\n#define E1000_ICR_VMMB\t\t0x00000100 /* VM MB event */\n#define E1000_ICR_RXCFG\t\t0x00000400 /* Rx /c/ ordered set */\n#define E1000_ICR_GPI_EN0\t0x00000800 /* GP Int 0 */\n#define E1000_ICR_GPI_EN1\t0x00001000 /* GP Int 1 */\n#define E1000_ICR_GPI_EN2\t0x00002000 /* GP Int 2 */\n#define E1000_ICR_GPI_EN3\t0x00004000 /* GP Int 3 */\n#define E1000_ICR_TXD_LOW\t0x00008000\n#define E1000_ICR_MNG\t\t0x00040000 /* Manageability event */\n#define E1000_ICR_TS\t\t0x00080000 /* Time Sync Interrupt */\n#define E1000_ICR_DRSTA\t\t0x40000000 /* Device Reset Asserted */\n/* If this bit asserted, the driver should claim the interrupt */\n#define E1000_ICR_INT_ASSERTED\t0x80000000\n#define E1000_ICR_DOUTSYNC\t0x10000000 /* NIC DMA out of sync */\n#define E1000_ICR_FER\t\t0x00400000 /* Fatal Error */\n\n#define E1000_ICR_THS\t\t0x00800000 /* ICR.THS: Thermal Sensor Event*/\n#define E1000_ICR_MDDET\t\t0x10000000 /* Malicious Driver Detect */\n\n\n/* Extended Interrupt Cause Read */\n#define E1000_EICR_RX_QUEUE0\t0x00000001 /* Rx Queue 0 Interrupt */\n#define E1000_EICR_RX_QUEUE1\t0x00000002 /* Rx Queue 1 Interrupt */\n#define E1000_EICR_RX_QUEUE2\t0x00000004 /* Rx Queue 2 Interrupt */\n#define E1000_EICR_RX_QUEUE3\t0x00000008 /* Rx Queue 3 Interrupt */\n#define E1000_EICR_TX_QUEUE0\t0x00000100 /* Tx Queue 0 Interrupt */\n#define E1000_EICR_TX_QUEUE1\t0x00000200 /* Tx Queue 1 Interrupt */\n#define E1000_EICR_TX_QUEUE2\t0x00000400 /* Tx Queue 2 Interrupt */\n#define E1000_EICR_TX_QUEUE3\t0x00000800 /* Tx Queue 3 Interrupt */\n#define E1000_EICR_TCP_TIMER\t0x40000000 /* TCP Timer */\n#define E1000_EICR_OTHER\t0x80000000 /* Interrupt Cause Active */\n/* TCP Timer */\n#define E1000_TCPTIMER_KS\t0x00000100 /* KickStart */\n#define E1000_TCPTIMER_COUNT_ENABLE\t0x00000200 /* Count Enable */\n#define E1000_TCPTIMER_COUNT_FINISH\t0x00000400 /* Count finish */\n#define E1000_TCPTIMER_LOOP\t0x00000800 /* Loop */\n\n/* This defines the bits that are set in the Interrupt Mask\n * Set/Read Register. Each bit is documented below:\n * o RXT0 = Receiver Timer Interrupt (ring 0)\n * o TXDW = Transmit Descriptor Written Back\n * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)\n * o RXSEQ = Receive Sequence Error\n * o LSC = Link Status Change\n */\n#define IMS_ENABLE_MASK ( \\\n\tE1000_IMS_RXT0 | \\\n\tE1000_IMS_TXDW | \\\n\tE1000_IMS_RXDMT0 | \\\n\tE1000_IMS_RXSEQ | \\\n\tE1000_IMS_LSC)\n\n/* Interrupt Mask Set */\n#define E1000_IMS_TXDW\t\tE1000_ICR_TXDW /* Tx desc written back */\n#define E1000_IMS_TXQE\t\tE1000_ICR_TXQE /* Transmit Queue empty */\n#define E1000_IMS_LSC\t\tE1000_ICR_LSC /* Link Status Change */\n#define E1000_IMS_VMMB\t\tE1000_ICR_VMMB /* Mail box activity */\n#define E1000_IMS_RXSEQ\t\tE1000_ICR_RXSEQ /* Rx sequence error */\n#define E1000_IMS_RXDMT0\tE1000_ICR_RXDMT0 /* Rx desc min. threshold */\n#define E1000_IMS_RXO\t\tE1000_ICR_RXO /* Rx overrun */\n#define E1000_IMS_RXT0\t\tE1000_ICR_RXT0 /* Rx timer intr */\n#define E1000_IMS_TXD_LOW\tE1000_ICR_TXD_LOW\n#define E1000_IMS_TS\t\tE1000_ICR_TS /* Time Sync Interrupt */\n#define E1000_IMS_DRSTA\t\tE1000_ICR_DRSTA /* Device Reset Asserted */\n#define E1000_IMS_DOUTSYNC\tE1000_ICR_DOUTSYNC /* NIC DMA out of sync */\n#define E1000_IMS_FER\t\tE1000_ICR_FER /* Fatal Error */\n\n#define E1000_IMS_THS\t\tE1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/\n#define E1000_IMS_MDDET\t\tE1000_ICR_MDDET /* Malicious Driver Detect */\n/* Extended Interrupt Mask Set */\n#define E1000_EIMS_RX_QUEUE0\tE1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */\n#define E1000_EIMS_RX_QUEUE1\tE1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */\n#define E1000_EIMS_RX_QUEUE2\tE1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */\n#define E1000_EIMS_RX_QUEUE3\tE1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */\n#define E1000_EIMS_TX_QUEUE0\tE1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */\n#define E1000_EIMS_TX_QUEUE1\tE1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */\n#define E1000_EIMS_TX_QUEUE2\tE1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */\n#define E1000_EIMS_TX_QUEUE3\tE1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */\n#define E1000_EIMS_TCP_TIMER\tE1000_EICR_TCP_TIMER /* TCP Timer */\n#define E1000_EIMS_OTHER\tE1000_EICR_OTHER /* Interrupt Cause Active */\n\n/* Interrupt Cause Set */\n#define E1000_ICS_LSC\t\tE1000_ICR_LSC /* Link Status Change */\n#define E1000_ICS_RXSEQ\t\tE1000_ICR_RXSEQ /* Rx sequence error */\n#define E1000_ICS_RXDMT0\tE1000_ICR_RXDMT0 /* Rx desc min. threshold */\n\n/* Extended Interrupt Cause Set */\n#define E1000_EICS_RX_QUEUE0\tE1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */\n#define E1000_EICS_RX_QUEUE1\tE1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */\n#define E1000_EICS_RX_QUEUE2\tE1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */\n#define E1000_EICS_RX_QUEUE3\tE1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */\n#define E1000_EICS_TX_QUEUE0\tE1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */\n#define E1000_EICS_TX_QUEUE1\tE1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */\n#define E1000_EICS_TX_QUEUE2\tE1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */\n#define E1000_EICS_TX_QUEUE3\tE1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */\n#define E1000_EICS_TCP_TIMER\tE1000_EICR_TCP_TIMER /* TCP Timer */\n#define E1000_EICS_OTHER\tE1000_EICR_OTHER /* Interrupt Cause Active */\n\n#define E1000_EITR_ITR_INT_MASK\t0x0000FFFF\n/* E1000_EITR_CNT_IGNR is only for 82576 and newer */\n#define E1000_EITR_CNT_IGNR\t0x80000000 /* Don't reset counters on write */\n#define E1000_EITR_INTERVAL 0x00007FFC\n\n/* Transmit Descriptor Control */\n#define E1000_TXDCTL_PTHRESH\t0x0000003F /* TXDCTL Prefetch Threshold */\n#define E1000_TXDCTL_HTHRESH\t0x00003F00 /* TXDCTL Host Threshold */\n#define E1000_TXDCTL_WTHRESH\t0x003F0000 /* TXDCTL Writeback Threshold */\n#define E1000_TXDCTL_GRAN\t0x01000000 /* TXDCTL Granularity */\n#define E1000_TXDCTL_FULL_TX_DESC_WB\t0x01010000 /* GRAN=1, WTHRESH=1 */\n#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */\n/* Enable the counting of descriptors still to be processed. */\n#define E1000_TXDCTL_COUNT_DESC\t0x00400000\n\n/* Flow Control Constants */\n#define FLOW_CONTROL_ADDRESS_LOW\t0x00C28001\n#define FLOW_CONTROL_ADDRESS_HIGH\t0x00000100\n#define FLOW_CONTROL_TYPE\t\t0x8808\n\n/* 802.1q VLAN Packet Size */\n#define VLAN_TAG_SIZE\t\t\t4 /* 802.3ac tag (not DMA'd) */\n#define E1000_VLAN_FILTER_TBL_SIZE\t128 /* VLAN Filter Table (4096 bits) */\n\n/* Receive Address\n * Number of high/low register pairs in the RAR. The RAR (Receive Address\n * Registers) holds the directed and multicast addresses that we monitor.\n * Technically, we have 16 spots. However, we reserve one of these spots\n * (RAR[15]) for our directed address used by controllers with\n * manageability enabled, allowing us room for 15 multicast addresses.\n */\n#define E1000_RAR_ENTRIES\t15\n#define E1000_RAH_AV\t\t0x80000000 /* Receive descriptor valid */\n#define E1000_RAL_MAC_ADDR_LEN\t4\n#define E1000_RAH_MAC_ADDR_LEN\t2\n#define E1000_RAH_QUEUE_MASK_82575\t0x000C0000\n#define E1000_RAH_POOL_1\t0x00040000\n\n/* Error Codes */\n#define E1000_SUCCESS\t\t\t0\n#define E1000_ERR_NVM\t\t\t1\n#define E1000_ERR_PHY\t\t\t2\n#define E1000_ERR_CONFIG\t\t3\n#define E1000_ERR_PARAM\t\t\t4\n#define E1000_ERR_MAC_INIT\t\t5\n#define E1000_ERR_PHY_TYPE\t\t6\n#define E1000_ERR_RESET\t\t\t9\n#define E1000_ERR_MASTER_REQUESTS_PENDING\t10\n#define E1000_ERR_HOST_INTERFACE_COMMAND\t11\n#define E1000_BLK_PHY_RESET\t\t12\n#define E1000_ERR_SWFW_SYNC\t\t13\n#define E1000_NOT_IMPLEMENTED\t\t14\n#define E1000_ERR_MBX\t\t\t15\n#define E1000_ERR_INVALID_ARGUMENT\t16\n#define E1000_ERR_NO_SPACE\t\t17\n#define E1000_ERR_NVM_PBA_SECTION\t18\n#define E1000_ERR_I2C\t\t\t19\n#define E1000_ERR_INVM_VALUE_NOT_FOUND\t20\n\n/* Loop limit on how long we wait for auto-negotiation to complete */\n#define FIBER_LINK_UP_LIMIT\t\t50\n#define COPPER_LINK_UP_LIMIT\t\t10\n#define PHY_AUTO_NEG_LIMIT\t\t45\n#define PHY_FORCE_LIMIT\t\t\t20\n/* Number of 100 microseconds we wait for PCI Express master disable */\n#define MASTER_DISABLE_TIMEOUT\t\t800\n/* Number of milliseconds we wait for PHY configuration done after MAC reset */\n#define PHY_CFG_TIMEOUT\t\t\t100\n/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */\n#define MDIO_OWNERSHIP_TIMEOUT\t\t10\n/* Number of milliseconds for NVM auto read done after MAC reset. */\n#define AUTO_READ_DONE_TIMEOUT\t\t10\n\n/* Flow Control */\n#define E1000_FCRTH_RTH\t\t0x0000FFF8 /* Mask Bits[15:3] for RTH */\n#define E1000_FCRTL_RTL\t\t0x0000FFF8 /* Mask Bits[15:3] for RTL */\n#define E1000_FCRTL_XONE\t0x80000000 /* Enable XON frame transmission */\n\n/* Transmit Configuration Word */\n#define E1000_TXCW_FD\t\t0x00000020 /* TXCW full duplex */\n#define E1000_TXCW_PAUSE\t0x00000080 /* TXCW sym pause request */\n#define E1000_TXCW_ASM_DIR\t0x00000100 /* TXCW astm pause direction */\n#define E1000_TXCW_PAUSE_MASK\t0x00000180 /* TXCW pause request mask */\n#define E1000_TXCW_ANE\t\t0x80000000 /* Auto-neg enable */\n\n/* Receive Configuration Word */\n#define E1000_RXCW_CW\t\t0x0000ffff /* RxConfigWord mask */\n#define E1000_RXCW_IV\t\t0x08000000 /* Receive config invalid */\n#define E1000_RXCW_C\t\t0x20000000 /* Receive config */\n#define E1000_RXCW_SYNCH\t0x40000000 /* Receive config synch */\n\n#define E1000_TSYNCTXCTL_VALID\t\t0x00000001 /* Tx timestamp valid */\n#define E1000_TSYNCTXCTL_ENABLED\t0x00000010 /* enable Tx timestamping */\n\n#define E1000_TSYNCRXCTL_VALID\t\t0x00000001 /* Rx timestamp valid */\n#define E1000_TSYNCRXCTL_TYPE_MASK\t0x0000000E /* Rx type mask */\n#define E1000_TSYNCRXCTL_TYPE_L2_V2\t0x00\n#define E1000_TSYNCRXCTL_TYPE_L4_V1\t0x02\n#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2\t0x04\n#define E1000_TSYNCRXCTL_TYPE_ALL\t0x08\n#define E1000_TSYNCRXCTL_TYPE_EVENT_V2\t0x0A\n#define E1000_TSYNCRXCTL_ENABLED\t0x00000010 /* enable Rx timestamping */\n#define E1000_TSYNCRXCTL_SYSCFI\t\t0x00000020 /* Sys clock frequency */\n\n#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK\t\t0x000000FF\n#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE\t\t0x00\n#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE\t0x01\n#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE\t0x02\n#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE\t0x03\n#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE\t0x04\n\n#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK\t\t0x00000F00\n#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE\t\t0x0000\n#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE\t0x0100\n#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE\t0x0200\n#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE\t0x0300\n#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE\t0x0800\n#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE\t0x0900\n#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00\n#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE\t0x0B00\n#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE\t0x0C00\n#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE\t0x0D00\n\n#define E1000_TIMINCA_16NS_SHIFT\t24\n#define E1000_TIMINCA_INCPERIOD_SHIFT\t24\n#define E1000_TIMINCA_INCVALUE_MASK\t0x00FFFFFF\n\n#define E1000_TSICR_TXTS\t\t0x00000002\n#define E1000_TSIM_TXTS\t\t\t0x00000002\n/* TUPLE Filtering Configuration */\n#define E1000_TTQF_DISABLE_MASK\t\t0xF0008000 /* TTQF Disable Mask */\n#define E1000_TTQF_QUEUE_ENABLE\t\t0x100 /* TTQF Queue Enable Bit */\n#define E1000_TTQF_PROTOCOL_MASK\t0xFF /* TTQF Protocol Mask */\n/* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */\n#define E1000_TTQF_PROTOCOL_TCP\t\t0x0\n/* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */\n#define E1000_TTQF_PROTOCOL_UDP\t\t0x1\n/* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */\n#define E1000_TTQF_PROTOCOL_SCTP\t0x2\n#define E1000_TTQF_PROTOCOL_SHIFT\t5 /* TTQF Protocol Shift */\n#define E1000_TTQF_QUEUE_SHIFT\t\t16 /* TTQF Queue Shfit */\n#define E1000_TTQF_RX_QUEUE_MASK\t0x70000 /* TTQF Queue Mask */\n#define E1000_TTQF_MASK_ENABLE\t\t0x10000000 /* TTQF Mask Enable Bit */\n#define E1000_IMIR_CLEAR_MASK\t\t0xF001FFFF /* IMIR Reg Clear Mask */\n#define E1000_IMIR_PORT_BYPASS\t\t0x20000 /* IMIR Port Bypass Bit */\n#define E1000_IMIR_PRIORITY_SHIFT\t29 /* IMIR Priority Shift */\n#define E1000_IMIREXT_CLEAR_MASK\t0x7FFFF /* IMIREXT Reg Clear Mask */\n\n#define E1000_MDICNFG_EXT_MDIO\t\t0x80000000 /* MDI ext/int destination */\n#define E1000_MDICNFG_COM_MDIO\t\t0x40000000 /* MDI shared w/ lan 0 */\n#define E1000_MDICNFG_PHY_MASK\t\t0x03E00000\n#define E1000_MDICNFG_PHY_SHIFT\t\t21\n\n#define E1000_MEDIA_PORT_COPPER\t\t\t1\n#define E1000_MEDIA_PORT_OTHER\t\t\t2\n#define E1000_M88E1112_AUTO_COPPER_SGMII\t0x2\n#define E1000_M88E1112_AUTO_COPPER_BASEX\t0x3\n#define E1000_M88E1112_STATUS_LINK\t\t0x0004 /* Interface Link Bit */\n#define E1000_M88E1112_MAC_CTRL_1\t\t0x10\n#define E1000_M88E1112_MAC_CTRL_1_MODE_MASK\t0x0380 /* Mode Select */\n#define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT\t7\n#define E1000_M88E1112_PAGE_ADDR\t\t0x16\n#define E1000_M88E1112_STATUS\t\t\t0x01\n\n#define E1000_THSTAT_LOW_EVENT\t\t0x20000000 /* Low thermal threshold */\n#define E1000_THSTAT_MID_EVENT\t\t0x00200000 /* Mid thermal threshold */\n#define E1000_THSTAT_HIGH_EVENT\t\t0x00002000 /* High thermal threshold */\n#define E1000_THSTAT_PWR_DOWN\t\t0x00000001 /* Power Down Event */\n#define E1000_THSTAT_LINK_THROTTLE\t0x00000002 /* Link Spd Throttle Event */\n\n/* I350 EEE defines */\n#define E1000_IPCNFG_EEE_1G_AN\t\t0x00000008 /* IPCNFG EEE Ena 1G AN */\n#define E1000_IPCNFG_EEE_100M_AN\t0x00000004 /* IPCNFG EEE Ena 100M AN */\n#define E1000_EEER_TX_LPI_EN\t\t0x00010000 /* EEER Tx LPI Enable */\n#define E1000_EEER_RX_LPI_EN\t\t0x00020000 /* EEER Rx LPI Enable */\n#define E1000_EEER_LPI_FC\t\t0x00040000 /* EEER Ena on Flow Cntrl */\n/* EEE status */\n#define E1000_EEER_EEE_NEG\t\t0x20000000 /* EEE capability nego */\n#define E1000_EEER_RX_LPI_STATUS\t0x40000000 /* Rx in LPI state */\n#define E1000_EEER_TX_LPI_STATUS\t0x80000000 /* Tx in LPI state */\n#define E1000_EEE_LP_ADV_ADDR_I350\t0x040F /* EEE LP Advertisement */\n#define E1000_M88E1543_PAGE_ADDR\t0x16 /* Page Offset Register */\n#define E1000_M88E1543_EEE_CTRL_1\t0x0\n#define E1000_M88E1543_EEE_CTRL_1_MS\t0x0001 /* EEE Master/Slave */\n#define E1000_EEE_ADV_DEV_I354\t\t7\n#define E1000_EEE_ADV_ADDR_I354\t\t60\n#define E1000_EEE_ADV_100_SUPPORTED\t(1 << 1) /* 100BaseTx EEE Supported */\n#define E1000_EEE_ADV_1000_SUPPORTED\t(1 << 2) /* 1000BaseT EEE Supported */\n#define E1000_PCS_STATUS_DEV_I354\t3\n#define E1000_PCS_STATUS_ADDR_I354\t1\n#define E1000_PCS_STATUS_RX_LPI_RCVD\t0x0400\n#define E1000_PCS_STATUS_TX_LPI_RCVD\t0x0800\n#define E1000_EEE_SU_LPI_CLK_STP\t0x00800000 /* EEE LPI Clock Stop */\n#define E1000_EEE_LP_ADV_DEV_I210\t7 /* EEE LP Adv Device */\n#define E1000_EEE_LP_ADV_ADDR_I210\t61 /* EEE LP Adv Register */\n/* PCI Express Control */\n#define E1000_GCR_RXD_NO_SNOOP\t\t0x00000001\n#define E1000_GCR_RXDSCW_NO_SNOOP\t0x00000002\n#define E1000_GCR_RXDSCR_NO_SNOOP\t0x00000004\n#define E1000_GCR_TXD_NO_SNOOP\t\t0x00000008\n#define E1000_GCR_TXDSCW_NO_SNOOP\t0x00000010\n#define E1000_GCR_TXDSCR_NO_SNOOP\t0x00000020\n#define E1000_GCR_CMPL_TMOUT_MASK\t0x0000F000\n#define E1000_GCR_CMPL_TMOUT_10ms\t0x00001000\n#define E1000_GCR_CMPL_TMOUT_RESEND\t0x00010000\n#define E1000_GCR_CAP_VER2\t\t0x00040000\n\n#define PCIE_NO_SNOOP_ALL\t(E1000_GCR_RXD_NO_SNOOP | \\\n\t\t\t\t E1000_GCR_RXDSCW_NO_SNOOP | \\\n\t\t\t\t E1000_GCR_RXDSCR_NO_SNOOP | \\\n\t\t\t\t E1000_GCR_TXD_NO_SNOOP | \\\n\t\t\t\t E1000_GCR_TXDSCW_NO_SNOOP | \\\n\t\t\t\t E1000_GCR_TXDSCR_NO_SNOOP)\n\n#define E1000_MMDAC_FUNC_DATA\t0x4000 /* Data, no post increment */\n\n/* mPHY address control and data registers */\n#define E1000_MPHY_ADDR_CTL\t\t0x0024 /* Address Control Reg */\n#define E1000_MPHY_ADDR_CTL_OFFSET_MASK\t0xFFFF0000\n#define E1000_MPHY_DATA\t\t\t0x0E10 /* Data Register */\n\n/* AFE CSR Offset for PCS CLK */\n#define E1000_MPHY_PCS_CLK_REG_OFFSET\t0x0004\n/* Override for near end digital loopback. */\n#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN\t0x10\n\n/* PHY Control Register */\n#define MII_CR_SPEED_SELECT_MSB\t0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */\n#define MII_CR_COLL_TEST_ENABLE\t0x0080 /* Collision test enable */\n#define MII_CR_FULL_DUPLEX\t0x0100 /* FDX =1, half duplex =0 */\n#define MII_CR_RESTART_AUTO_NEG\t0x0200 /* Restart auto negotiation */\n#define MII_CR_ISOLATE\t\t0x0400 /* Isolate PHY from MII */\n#define MII_CR_POWER_DOWN\t0x0800 /* Power down */\n#define MII_CR_AUTO_NEG_EN\t0x1000 /* Auto Neg Enable */\n#define MII_CR_SPEED_SELECT_LSB\t0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */\n#define MII_CR_LOOPBACK\t\t0x4000 /* 0 = normal, 1 = loopback */\n#define MII_CR_RESET\t\t0x8000 /* 0 = normal, 1 = PHY reset */\n#define MII_CR_SPEED_1000\t0x0040\n#define MII_CR_SPEED_100\t0x2000\n#define MII_CR_SPEED_10\t\t0x0000\n\n/* PHY Status Register */\n#define MII_SR_EXTENDED_CAPS\t0x0001 /* Extended register capabilities */\n#define MII_SR_JABBER_DETECT\t0x0002 /* Jabber Detected */\n#define MII_SR_LINK_STATUS\t0x0004 /* Link Status 1 = link */\n#define MII_SR_AUTONEG_CAPS\t0x0008 /* Auto Neg Capable */\n#define MII_SR_REMOTE_FAULT\t0x0010 /* Remote Fault Detect */\n#define MII_SR_AUTONEG_COMPLETE\t0x0020 /* Auto Neg Complete */\n#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */\n#define MII_SR_EXTENDED_STATUS\t0x0100 /* Ext. status info in Reg 0x0F */\n#define MII_SR_100T2_HD_CAPS\t0x0200 /* 100T2 Half Duplex Capable */\n#define MII_SR_100T2_FD_CAPS\t0x0400 /* 100T2 Full Duplex Capable */\n#define MII_SR_10T_HD_CAPS\t0x0800 /* 10T Half Duplex Capable */\n#define MII_SR_10T_FD_CAPS\t0x1000 /* 10T Full Duplex Capable */\n#define MII_SR_100X_HD_CAPS\t0x2000 /* 100X Half Duplex Capable */\n#define MII_SR_100X_FD_CAPS\t0x4000 /* 100X Full Duplex Capable */\n#define MII_SR_100T4_CAPS\t0x8000 /* 100T4 Capable */\n\n/* Autoneg Advertisement Register */\n#define NWAY_AR_SELECTOR_FIELD\t0x0001 /* indicates IEEE 802.3 CSMA/CD */\n#define NWAY_AR_10T_HD_CAPS\t0x0020 /* 10T Half Duplex Capable */\n#define NWAY_AR_10T_FD_CAPS\t0x0040 /* 10T Full Duplex Capable */\n#define NWAY_AR_100TX_HD_CAPS\t0x0080 /* 100TX Half Duplex Capable */\n#define NWAY_AR_100TX_FD_CAPS\t0x0100 /* 100TX Full Duplex Capable */\n#define NWAY_AR_100T4_CAPS\t0x0200 /* 100T4 Capable */\n#define NWAY_AR_PAUSE\t\t0x0400 /* Pause operation desired */\n#define NWAY_AR_ASM_DIR\t\t0x0800 /* Asymmetric Pause Direction bit */\n#define NWAY_AR_REMOTE_FAULT\t0x2000 /* Remote Fault detected */\n#define NWAY_AR_NEXT_PAGE\t0x8000 /* Next Page ability supported */\n\n/* Link Partner Ability Register (Base Page) */\n#define NWAY_LPAR_SELECTOR_FIELD\t0x0000 /* LP protocol selector field */\n#define NWAY_LPAR_10T_HD_CAPS\t\t0x0020 /* LP 10T Half Dplx Capable */\n#define NWAY_LPAR_10T_FD_CAPS\t\t0x0040 /* LP 10T Full Dplx Capable */\n#define NWAY_LPAR_100TX_HD_CAPS\t\t0x0080 /* LP 100TX Half Dplx Capable */\n#define NWAY_LPAR_100TX_FD_CAPS\t\t0x0100 /* LP 100TX Full Dplx Capable */\n#define NWAY_LPAR_100T4_CAPS\t\t0x0200 /* LP is 100T4 Capable */\n#define NWAY_LPAR_PAUSE\t\t\t0x0400 /* LP Pause operation desired */\n#define NWAY_LPAR_ASM_DIR\t\t0x0800 /* LP Asym Pause Direction bit */\n#define NWAY_LPAR_REMOTE_FAULT\t\t0x2000 /* LP detected Remote Fault */\n#define NWAY_LPAR_ACKNOWLEDGE\t\t0x4000 /* LP rx'd link code word */\n#define NWAY_LPAR_NEXT_PAGE\t\t0x8000 /* Next Page ability supported */\n\n/* Autoneg Expansion Register */\n#define NWAY_ER_LP_NWAY_CAPS\t\t0x0001 /* LP has Auto Neg Capability */\n#define NWAY_ER_PAGE_RXD\t\t0x0002 /* LP 10T Half Dplx Capable */\n#define NWAY_ER_NEXT_PAGE_CAPS\t\t0x0004 /* LP 10T Full Dplx Capable */\n#define NWAY_ER_LP_NEXT_PAGE_CAPS\t0x0008 /* LP 100TX Half Dplx Capable */\n#define NWAY_ER_PAR_DETECT_FAULT\t0x0010 /* LP 100TX Full Dplx Capable */\n\n/* 1000BASE-T Control Register */\n#define CR_1000T_ASYM_PAUSE\t0x0080 /* Advertise asymmetric pause bit */\n#define CR_1000T_HD_CAPS\t0x0100 /* Advertise 1000T HD capability */\n#define CR_1000T_FD_CAPS\t0x0200 /* Advertise 1000T FD capability */\n/* 1=Repeater/switch device port 0=DTE device */\n#define CR_1000T_REPEATER_DTE\t0x0400\n/* 1=Configure PHY as Master 0=Configure PHY as Slave */\n#define CR_1000T_MS_VALUE\t0x0800\n/* 1=Master/Slave manual config value 0=Automatic Master/Slave config */\n#define CR_1000T_MS_ENABLE\t0x1000\n#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */\n#define CR_1000T_TEST_MODE_1\t0x2000 /* Transmit Waveform test */\n#define CR_1000T_TEST_MODE_2\t0x4000 /* Master Transmit Jitter test */\n#define CR_1000T_TEST_MODE_3\t0x6000 /* Slave Transmit Jitter test */\n#define CR_1000T_TEST_MODE_4\t0x8000 /* Transmitter Distortion test */\n\n/* 1000BASE-T Status Register */\n#define SR_1000T_IDLE_ERROR_CNT\t\t0x00FF /* Num idle err since last rd */\n#define SR_1000T_ASYM_PAUSE_DIR\t\t0x0100 /* LP asym pause direction bit */\n#define SR_1000T_LP_HD_CAPS\t\t0x0400 /* LP is 1000T HD capable */\n#define SR_1000T_LP_FD_CAPS\t\t0x0800 /* LP is 1000T FD capable */\n#define SR_1000T_REMOTE_RX_STATUS\t0x1000 /* Remote receiver OK */\n#define SR_1000T_LOCAL_RX_STATUS\t0x2000 /* Local receiver OK */\n#define SR_1000T_MS_CONFIG_RES\t\t0x4000 /* 1=Local Tx Master, 0=Slave */\n#define SR_1000T_MS_CONFIG_FAULT\t0x8000 /* Master/Slave config fault */\n\n#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT\t5\n\n/* PHY 1000 MII Register/Bit Definitions */\n/* PHY Registers defined by IEEE */\n#define PHY_CONTROL\t\t0x00 /* Control Register */\n#define PHY_STATUS\t\t0x01 /* Status Register */\n#define PHY_ID1\t\t\t0x02 /* Phy Id Reg (word 1) */\n#define PHY_ID2\t\t\t0x03 /* Phy Id Reg (word 2) */\n#define PHY_AUTONEG_ADV\t\t0x04 /* Autoneg Advertisement */\n#define PHY_LP_ABILITY\t\t0x05 /* Link Partner Ability (Base Page) */\n#define PHY_AUTONEG_EXP\t\t0x06 /* Autoneg Expansion Reg */\n#define PHY_NEXT_PAGE_TX\t0x07 /* Next Page Tx */\n#define PHY_LP_NEXT_PAGE\t0x08 /* Link Partner Next Page */\n#define PHY_1000T_CTRL\t\t0x09 /* 1000Base-T Control Reg */\n#define PHY_1000T_STATUS\t0x0A /* 1000Base-T Status Reg */\n#define PHY_EXT_STATUS\t\t0x0F /* Extended Status Reg */\n\n#define PHY_CONTROL_LB\t\t0x4000 /* PHY Loopback bit */\n\n/* NVM Control */\n#define E1000_EECD_SK\t\t0x00000001 /* NVM Clock */\n#define E1000_EECD_CS\t\t0x00000002 /* NVM Chip Select */\n#define E1000_EECD_DI\t\t0x00000004 /* NVM Data In */\n#define E1000_EECD_DO\t\t0x00000008 /* NVM Data Out */\n#define E1000_EECD_REQ\t\t0x00000040 /* NVM Access Request */\n#define E1000_EECD_GNT\t\t0x00000080 /* NVM Access Grant */\n#define E1000_EECD_PRES\t\t0x00000100 /* NVM Present */\n#define E1000_EECD_SIZE\t\t0x00000200 /* NVM Size (0=64 word 1=256 word) */\n#define E1000_EECD_BLOCKED\t0x00008000 /* Bit banging access blocked flag */\n#define E1000_EECD_ABORT\t0x00010000 /* NVM operation aborted flag */\n#define E1000_EECD_TIMEOUT\t0x00020000 /* NVM read operation timeout flag */\n#define E1000_EECD_ERROR_CLR\t0x00040000 /* NVM error status clear bit */\n/* NVM Addressing bits based on type 0=small, 1=large */\n#define E1000_EECD_ADDR_BITS\t0x00000400\n#define E1000_NVM_GRANT_ATTEMPTS\t1000 /* NVM # attempts to gain grant */\n#define E1000_EECD_AUTO_RD\t\t0x00000200 /* NVM Auto Read done */\n#define E1000_EECD_SIZE_EX_MASK\t\t0x00007800 /* NVM Size */\n#define E1000_EECD_SIZE_EX_SHIFT\t11\n#define E1000_EECD_FLUPD\t\t0x00080000 /* Update FLASH */\n#define E1000_EECD_AUPDEN\t\t0x00100000 /* Ena Auto FLASH update */\n#define E1000_EECD_SEC1VAL\t\t0x00400000 /* Sector One Valid */\n#define E1000_EECD_SEC1VAL_VALID_MASK\t(E1000_EECD_AUTO_RD | E1000_EECD_PRES)\n#define E1000_EECD_FLUPD_I210\t\t0x00800000 /* Update FLASH */\n#define E1000_EECD_FLUDONE_I210\t\t0x04000000 /* Update FLASH done */\n#define E1000_EECD_FLASH_DETECTED_I210\t0x00080000 /* FLASH detected */\n#define E1000_EECD_SEC1VAL_I210\t\t0x02000000 /* Sector One Valid */\n#define E1000_FLUDONE_ATTEMPTS\t\t20000\n#define E1000_EERD_EEWR_MAX_COUNT\t512 /* buffered EEPROM words rw */\n#define E1000_I210_FIFO_SEL_RX\t\t0x00\n#define E1000_I210_FIFO_SEL_TX_QAV(_i)\t(0x02 + (_i))\n#define E1000_I210_FIFO_SEL_TX_LEGACY\tE1000_I210_FIFO_SEL_TX_QAV(0)\n#define E1000_I210_FIFO_SEL_BMC2OS_TX\t0x06\n#define E1000_I210_FIFO_SEL_BMC2OS_RX\t0x01\n\n#define E1000_I210_FLASH_SECTOR_SIZE\t0x1000 /* 4KB FLASH sector unit size */\n/* Secure FLASH mode requires removing MSb */\n#define E1000_I210_FW_PTR_MASK\t\t0x7FFF\n/* Firmware code revision field word offset*/\n#define E1000_I210_FW_VER_OFFSET\t328\n\n#define E1000_NVM_RW_REG_DATA\t16 /* Offset to data in NVM read/write regs */\n#define E1000_NVM_RW_REG_DONE\t2 /* Offset to READ/WRITE done bit */\n#define E1000_NVM_RW_REG_START\t1 /* Start operation */\n#define E1000_NVM_RW_ADDR_SHIFT\t2 /* Shift to the address bits */\n#define E1000_NVM_POLL_WRITE\t1 /* Flag for polling for write complete */\n#define E1000_NVM_POLL_READ\t0 /* Flag for polling for read complete */\n#define E1000_FLASH_UPDATES\t2000\n\n/* NVM Word Offsets */\n#define NVM_COMPAT\t\t\t0x0003\n#define NVM_ID_LED_SETTINGS\t\t0x0004\n#define NVM_VERSION\t\t\t0x0005\n#define E1000_I210_NVM_FW_MODULE_PTR\t0x0010\n#define E1000_I350_NVM_FW_MODULE_PTR\t0x0051\n#define NVM_FUTURE_INIT_WORD1\t\t0x0019\n#define NVM_ETRACK_WORD\t\t\t0x0042\n#define NVM_ETRACK_HIWORD\t\t0x0043\n#define NVM_COMB_VER_OFF\t\t0x0083\n#define NVM_COMB_VER_PTR\t\t0x003d\n\n/* NVM version defines */\n#define NVM_MAJOR_MASK\t\t\t0xF000\n#define NVM_MINOR_MASK\t\t\t0x0FF0\n#define NVM_IMAGE_ID_MASK\t\t0x000F\n#define NVM_COMB_VER_MASK\t\t0x00FF\n#define NVM_MAJOR_SHIFT\t\t\t12\n#define NVM_MINOR_SHIFT\t\t\t4\n#define NVM_COMB_VER_SHFT\t\t8\n#define NVM_VER_INVALID\t\t\t0xFFFF\n#define NVM_ETRACK_SHIFT\t\t16\n#define NVM_ETRACK_VALID\t\t0x8000\n#define NVM_NEW_DEC_MASK\t\t0x0F00\n#define NVM_HEX_CONV\t\t\t16\n#define NVM_HEX_TENS\t\t\t10\n\n/* FW version defines */\n/* Offset of \"Loader patch ptr\" in Firmware Header */\n#define E1000_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET\t0x01\n/* Patch generation hour & minutes */\n#define E1000_I350_NVM_FW_VER_WORD1_OFFSET\t\t0x04\n/* Patch generation month & day */\n#define E1000_I350_NVM_FW_VER_WORD2_OFFSET\t\t0x05\n/* Patch generation year */\n#define E1000_I350_NVM_FW_VER_WORD3_OFFSET\t\t0x06\n/* Patch major & minor numbers */\n#define E1000_I350_NVM_FW_VER_WORD4_OFFSET\t\t0x07\n\n#define NVM_MAC_ADDR\t\t\t0x0000\n#define NVM_SUB_DEV_ID\t\t\t0x000B\n#define NVM_SUB_VEN_ID\t\t\t0x000C\n#define NVM_DEV_ID\t\t\t0x000D\n#define NVM_VEN_ID\t\t\t0x000E\n#define NVM_INIT_CTRL_2\t\t\t0x000F\n#define NVM_INIT_CTRL_4\t\t\t0x0013\n#define NVM_LED_1_CFG\t\t\t0x001C\n#define NVM_LED_0_2_CFG\t\t\t0x001F\n\n#define NVM_COMPAT_VALID_CSUM\t\t0x0001\n#define NVM_FUTURE_INIT_WORD1_VALID_CSUM\t0x0040\n\n#define NVM_ETS_CFG\t\t\t0x003E\n#define NVM_ETS_LTHRES_DELTA_MASK\t0x07C0\n#define NVM_ETS_LTHRES_DELTA_SHIFT\t6\n#define NVM_ETS_TYPE_MASK\t\t0x0038\n#define NVM_ETS_TYPE_SHIFT\t\t3\n#define NVM_ETS_TYPE_EMC\t\t0x000\n#define NVM_ETS_NUM_SENSORS_MASK\t0x0007\n#define NVM_ETS_DATA_LOC_MASK\t\t0x3C00\n#define NVM_ETS_DATA_LOC_SHIFT\t\t10\n#define NVM_ETS_DATA_INDEX_MASK\t\t0x0300\n#define NVM_ETS_DATA_INDEX_SHIFT\t8\n#define NVM_ETS_DATA_HTHRESH_MASK\t0x00FF\n#define NVM_INIT_CONTROL2_REG\t\t0x000F\n#define NVM_INIT_CONTROL3_PORT_B\t0x0014\n#define NVM_INIT_3GIO_3\t\t\t0x001A\n#define NVM_SWDEF_PINS_CTRL_PORT_0\t0x0020\n#define NVM_INIT_CONTROL3_PORT_A\t0x0024\n#define NVM_CFG\t\t\t\t0x0012\n#define NVM_ALT_MAC_ADDR_PTR\t\t0x0037\n#define NVM_CHECKSUM_REG\t\t0x003F\n#define NVM_COMPATIBILITY_REG_3\t\t0x0003\n#define NVM_COMPATIBILITY_BIT_MASK\t0x8000\n\n#define E1000_NVM_CFG_DONE_PORT_0\t0x040000 /* MNG config cycle done */\n#define E1000_NVM_CFG_DONE_PORT_1\t0x080000 /* ...for second port */\n#define E1000_NVM_CFG_DONE_PORT_2\t0x100000 /* ...for third port */\n#define E1000_NVM_CFG_DONE_PORT_3\t0x200000 /* ...for fourth port */\n\n#define NVM_82580_LAN_FUNC_OFFSET(a)\t((a) ? (0x40 + (0x40 * (a))) : 0)\n\n/* Mask bits for fields in Word 0x24 of the NVM */\n#define NVM_WORD24_COM_MDIO\t\t0x0008 /* MDIO interface shared */\n#define NVM_WORD24_EXT_MDIO\t\t0x0004 /* MDIO accesses routed extrnl */\n/* Offset of Link Mode bits for 82575/82576 */\n#define NVM_WORD24_LNK_MODE_OFFSET\t8\n/* Offset of Link Mode bits for 82580 up */\n#define NVM_WORD24_82580_LNK_MODE_OFFSET\t4\n\n\n/* Mask bits for fields in Word 0x0f of the NVM */\n#define NVM_WORD0F_PAUSE_MASK\t\t0x3000\n#define NVM_WORD0F_PAUSE\t\t0x1000\n#define NVM_WORD0F_ASM_DIR\t\t0x2000\n\n/* Mask bits for fields in Word 0x1a of the NVM */\n#define NVM_WORD1A_ASPM_MASK\t\t0x000C\n\n/* Mask bits for fields in Word 0x03 of the EEPROM */\n#define NVM_COMPAT_LOM\t\t\t0x0800\n\n/* length of string needed to store PBA number */\n#define E1000_PBANUM_LENGTH\t\t11\n\n/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */\n#define NVM_SUM\t\t\t\t0xBABA\n\n/* PBA (printed board assembly) number words */\n#define NVM_PBA_OFFSET_0\t\t8\n#define NVM_PBA_OFFSET_1\t\t9\n#define NVM_PBA_PTR_GUARD\t\t0xFAFA\n#define NVM_RESERVED_WORD\t\t0xFFFF\n#define NVM_WORD_SIZE_BASE_SHIFT\t6\n\n/* NVM Commands - SPI */\n#define NVM_MAX_RETRY_SPI\t5000 /* Max wait of 5ms, for RDY signal */\n#define NVM_READ_OPCODE_SPI\t0x03 /* NVM read opcode */\n#define NVM_WRITE_OPCODE_SPI\t0x02 /* NVM write opcode */\n#define NVM_A8_OPCODE_SPI\t0x08 /* opcode bit-3 = address bit-8 */\n#define NVM_WREN_OPCODE_SPI\t0x06 /* NVM set Write Enable latch */\n#define NVM_RDSR_OPCODE_SPI\t0x05 /* NVM read Status register */\n\n/* SPI NVM Status Register */\n#define NVM_STATUS_RDY_SPI\t0x01\n\n/* Word definitions for ID LED Settings */\n#define ID_LED_RESERVED_0000\t0x0000\n#define ID_LED_RESERVED_FFFF\t0xFFFF\n#define ID_LED_DEFAULT\t\t((ID_LED_OFF1_ON2 << 12) | \\\n\t\t\t\t (ID_LED_OFF1_OFF2 << 8) | \\\n\t\t\t\t (ID_LED_DEF1_DEF2 << 4) | \\\n\t\t\t\t (ID_LED_DEF1_DEF2))\n#define ID_LED_DEF1_DEF2\t0x1\n#define ID_LED_DEF1_ON2\t\t0x2\n#define ID_LED_DEF1_OFF2\t0x3\n#define ID_LED_ON1_DEF2\t\t0x4\n#define ID_LED_ON1_ON2\t\t0x5\n#define ID_LED_ON1_OFF2\t\t0x6\n#define ID_LED_OFF1_DEF2\t0x7\n#define ID_LED_OFF1_ON2\t\t0x8\n#define ID_LED_OFF1_OFF2\t0x9\n\n#define IGP_ACTIVITY_LED_MASK\t0xFFFFF0FF\n#define IGP_ACTIVITY_LED_ENABLE\t0x0300\n#define IGP_LED3_MODE\t\t0x07000000\n\n/* PCI/PCI-X/PCI-EX Config space */\n#define PCI_HEADER_TYPE_REGISTER\t0x0E\n#define PCIE_LINK_STATUS\t\t0x12\n#define PCIE_DEVICE_CONTROL2\t\t0x28\n\n#define PCI_HEADER_TYPE_MULTIFUNC\t0x80\n#define PCIE_LINK_WIDTH_MASK\t\t0x3F0\n#define PCIE_LINK_WIDTH_SHIFT\t\t4\n#define PCIE_LINK_SPEED_MASK\t\t0x0F\n#define PCIE_LINK_SPEED_2500\t\t0x01\n#define PCIE_LINK_SPEED_5000\t\t0x02\n#define PCIE_DEVICE_CONTROL2_16ms\t0x0005\n\n#ifndef ETH_ADDR_LEN\n#define ETH_ADDR_LEN\t\t\t6\n#endif\n\n#define PHY_REVISION_MASK\t\t0xFFFFFFF0\n#define MAX_PHY_REG_ADDRESS\t\t0x1F /* 5 bit address bus (0-0x1F) */\n#define MAX_PHY_MULTI_PAGE_REG\t\t0xF\n\n/* Bit definitions for valid PHY IDs.\n * I = Integrated\n * E = External\n */\n#define M88E1000_E_PHY_ID\t0x01410C50\n#define M88E1000_I_PHY_ID\t0x01410C30\n#define M88E1011_I_PHY_ID\t0x01410C20\n#define IGP01E1000_I_PHY_ID\t0x02A80380\n#define M88E1111_I_PHY_ID\t0x01410CC0\n#define M88E1543_E_PHY_ID\t0x01410EA0\n#define M88E1112_E_PHY_ID\t0x01410C90\n#define I347AT4_E_PHY_ID\t0x01410DC0\n#define M88E1340M_E_PHY_ID\t0x01410DF0\n#define GG82563_E_PHY_ID\t0x01410CA0\n#define IGP03E1000_E_PHY_ID\t0x02A80390\n#define IFE_E_PHY_ID\t\t0x02A80330\n#define IFE_PLUS_E_PHY_ID\t0x02A80320\n#define IFE_C_E_PHY_ID\t\t0x02A80310\n#define I82580_I_PHY_ID\t\t0x015403A0\n#define I350_I_PHY_ID\t\t0x015403B0\n#define I210_I_PHY_ID\t\t0x01410C00\n#define IGP04E1000_E_PHY_ID\t0x02A80391\n#define M88_VENDOR\t\t0x0141\n\n/* M88E1000 Specific Registers */\n#define M88E1000_PHY_SPEC_CTRL\t\t0x10 /* PHY Specific Control Reg */\n#define M88E1000_PHY_SPEC_STATUS\t0x11 /* PHY Specific Status Reg */\n#define M88E1000_EXT_PHY_SPEC_CTRL\t0x14 /* Extended PHY Specific Cntrl */\n#define M88E1000_RX_ERR_CNTR\t\t0x15 /* Receive Error Counter */\n\n#define M88E1000_PHY_PAGE_SELECT\t0x1D /* Reg 29 for pg number setting */\n#define M88E1000_PHY_GEN_CONTROL\t0x1E /* meaning depends on reg 29 */\n\n/* M88E1000 PHY Specific Control Register */\n#define M88E1000_PSCR_POLARITY_REVERSAL\t0x0002 /* 1=Polarity Reverse enabled */\n/* MDI Crossover Mode bits 6:5 Manual MDI configuration */\n#define M88E1000_PSCR_MDI_MANUAL_MODE\t0x0000\n#define M88E1000_PSCR_MDIX_MANUAL_MODE\t0x0020 /* Manual MDIX configuration */\n/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */\n#define M88E1000_PSCR_AUTO_X_1000T\t0x0040\n/* Auto crossover enabled all speeds */\n#define M88E1000_PSCR_AUTO_X_MODE\t0x0060\n#define M88E1000_PSCR_ASSERT_CRS_ON_TX\t0x0800 /* 1=Assert CRS on Tx */\n\n/* M88E1000 PHY Specific Status Register */\n#define M88E1000_PSSR_REV_POLARITY\t0x0002 /* 1=Polarity reversed */\n#define M88E1000_PSSR_DOWNSHIFT\t\t0x0020 /* 1=Downshifted */\n#define M88E1000_PSSR_MDIX\t\t0x0040 /* 1=MDIX; 0=MDI */\n/* 0 = <50M\n * 1 = 50-80M\n * 2 = 80-110M\n * 3 = 110-140M\n * 4 = >140M\n */\n#define M88E1000_PSSR_CABLE_LENGTH\t0x0380\n#define M88E1000_PSSR_LINK\t\t0x0400 /* 1=Link up, 0=Link down */\n#define M88E1000_PSSR_SPD_DPLX_RESOLVED\t0x0800 /* 1=Speed & Duplex resolved */\n#define M88E1000_PSSR_SPEED\t\t0xC000 /* Speed, bits 14:15 */\n#define M88E1000_PSSR_1000MBS\t\t0x8000 /* 10=1000Mbs */\n\n#define M88E1000_PSSR_CABLE_LENGTH_SHIFT\t7\n\n/* Number of times we will attempt to autonegotiate before downshifting if we\n * are the master\n */\n#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK\t0x0C00\n#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X\t0x0000\n/* Number of times we will attempt to autonegotiate before downshifting if we\n * are the slave\n */\n#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK\t0x0300\n#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X\t0x0100\n#define M88E1000_EPSCR_TX_CLK_25\t0x0070 /* 25 MHz TX_CLK */\n\n/* Intel I347AT4 Registers */\n#define I347AT4_PCDL\t\t0x10 /* PHY Cable Diagnostics Length */\n#define I347AT4_PCDC\t\t0x15 /* PHY Cable Diagnostics Control */\n#define I347AT4_PAGE_SELECT\t0x16\n\n/* I347AT4 Extended PHY Specific Control Register */\n\n/* Number of times we will attempt to autonegotiate before downshifting if we\n * are the master\n */\n#define I347AT4_PSCR_DOWNSHIFT_ENABLE\t0x0800\n#define I347AT4_PSCR_DOWNSHIFT_MASK\t0x7000\n#define I347AT4_PSCR_DOWNSHIFT_1X\t0x0000\n#define I347AT4_PSCR_DOWNSHIFT_2X\t0x1000\n#define I347AT4_PSCR_DOWNSHIFT_3X\t0x2000\n#define I347AT4_PSCR_DOWNSHIFT_4X\t0x3000\n#define I347AT4_PSCR_DOWNSHIFT_5X\t0x4000\n#define I347AT4_PSCR_DOWNSHIFT_6X\t0x5000\n#define I347AT4_PSCR_DOWNSHIFT_7X\t0x6000\n#define I347AT4_PSCR_DOWNSHIFT_8X\t0x7000\n\n/* I347AT4 PHY Cable Diagnostics Control */\n#define I347AT4_PCDC_CABLE_LENGTH_UNIT\t0x0400 /* 0=cm 1=meters */\n\n/* M88E1112 only registers */\n#define M88E1112_VCT_DSP_DISTANCE\t0x001A\n\n/* M88EC018 Rev 2 specific DownShift settings */\n#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK\t0x0E00\n#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X\t0x0800\n\n/* Bits...\n * 15-5: page\n * 4-0: register offset\n */\n#define GG82563_PAGE_SHIFT\t5\n#define GG82563_REG(page, reg)\t\\\n\t(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))\n#define GG82563_MIN_ALT_REG\t30\n\n/* GG82563 Specific Registers */\n#define GG82563_PHY_SPEC_CTRL\t\tGG82563_REG(0, 16) /* PHY Spec Cntrl */\n#define GG82563_PHY_PAGE_SELECT\t\tGG82563_REG(0, 22) /* Page Select */\n#define GG82563_PHY_SPEC_CTRL_2\t\tGG82563_REG(0, 26) /* PHY Spec Cntrl2 */\n#define GG82563_PHY_PAGE_SELECT_ALT\tGG82563_REG(0, 29) /* Alt Page Select */\n\n/* MAC Specific Control Register */\n#define GG82563_PHY_MAC_SPEC_CTRL\tGG82563_REG(2, 21)\n\n#define GG82563_PHY_DSP_DISTANCE\tGG82563_REG(5, 26) /* DSP Distance */\n\n/* Page 193 - Port Control Registers */\n/* Kumeran Mode Control */\n#define GG82563_PHY_KMRN_MODE_CTRL\tGG82563_REG(193, 16)\n#define GG82563_PHY_PWR_MGMT_CTRL\tGG82563_REG(193, 20) /* Pwr Mgt Ctrl */\n\n/* Page 194 - KMRN Registers */\n#define GG82563_PHY_INBAND_CTRL\t\tGG82563_REG(194, 18) /* Inband Ctrl */\n\n/* MDI Control */\n#define E1000_MDIC_REG_MASK\t0x001F0000\n#define E1000_MDIC_REG_SHIFT\t16\n#define E1000_MDIC_PHY_MASK\t0x03E00000\n#define E1000_MDIC_PHY_SHIFT\t21\n#define E1000_MDIC_OP_WRITE\t0x04000000\n#define E1000_MDIC_OP_READ\t0x08000000\n#define E1000_MDIC_READY\t0x10000000\n#define E1000_MDIC_ERROR\t0x40000000\n#define E1000_MDIC_DEST\t\t0x80000000\n\n/* SerDes Control */\n#define E1000_GEN_CTL_READY\t\t0x80000000\n#define E1000_GEN_CTL_ADDRESS_SHIFT\t8\n#define E1000_GEN_POLL_TIMEOUT\t\t640\n\n/* LinkSec register fields */\n#define E1000_LSECTXCAP_SUM_MASK\t0x00FF0000\n#define E1000_LSECTXCAP_SUM_SHIFT\t16\n#define E1000_LSECRXCAP_SUM_MASK\t0x00FF0000\n#define E1000_LSECRXCAP_SUM_SHIFT\t16\n\n#define E1000_LSECTXCTRL_EN_MASK\t0x00000003\n#define E1000_LSECTXCTRL_DISABLE\t0x0\n#define E1000_LSECTXCTRL_AUTH\t\t0x1\n#define E1000_LSECTXCTRL_AUTH_ENCRYPT\t0x2\n#define E1000_LSECTXCTRL_AISCI\t\t0x00000020\n#define E1000_LSECTXCTRL_PNTHRSH_MASK\t0xFFFFFF00\n#define E1000_LSECTXCTRL_RSV_MASK\t0x000000D8\n\n#define E1000_LSECRXCTRL_EN_MASK\t0x0000000C\n#define E1000_LSECRXCTRL_EN_SHIFT\t2\n#define E1000_LSECRXCTRL_DISABLE\t0x0\n#define E1000_LSECRXCTRL_CHECK\t\t0x1\n#define E1000_LSECRXCTRL_STRICT\t\t0x2\n#define E1000_LSECRXCTRL_DROP\t\t0x3\n#define E1000_LSECRXCTRL_PLSH\t\t0x00000040\n#define E1000_LSECRXCTRL_RP\t\t0x00000080\n#define E1000_LSECRXCTRL_RSV_MASK\t0xFFFFFF33\n\n/* Tx Rate-Scheduler Config fields */\n#define E1000_RTTBCNRC_RS_ENA\t\t0x80000000\n#define E1000_RTTBCNRC_RF_DEC_MASK\t0x00003FFF\n#define E1000_RTTBCNRC_RF_INT_SHIFT\t14\n#define E1000_RTTBCNRC_RF_INT_MASK\t\\\n\t(E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)\n\n/* DMA Coalescing register fields */\n/* DMA Coalescing Watchdog Timer */\n#define E1000_DMACR_DMACWT_MASK\t\t0x00003FFF\n/* DMA Coalescing Rx Threshold */\n#define E1000_DMACR_DMACTHR_MASK\t0x00FF0000\n#define E1000_DMACR_DMACTHR_SHIFT\t16\n/* Lx when no PCIe transactions */\n#define E1000_DMACR_DMAC_LX_MASK\t0x30000000\n#define E1000_DMACR_DMAC_LX_SHIFT\t28\n#define E1000_DMACR_DMAC_EN\t\t0x80000000 /* Enable DMA Coalescing */\n/* DMA Coalescing BMC-to-OS Watchdog Enable */\n#define E1000_DMACR_DC_BMC2OSW_EN\t0x00008000\n\n/* DMA Coalescing Transmit Threshold */\n#define E1000_DMCTXTH_DMCTTHR_MASK\t0x00000FFF\n\n#define E1000_DMCTLX_TTLX_MASK\t\t0x00000FFF /* Time to LX request */\n\n/* Rx Traffic Rate Threshold */\n#define E1000_DMCRTRH_UTRESH_MASK\t0x0007FFFF\n/* Rx packet rate in current window */\n#define E1000_DMCRTRH_LRPRCW\t\t0x80000000\n\n/* DMA Coal Rx Traffic Current Count */\n#define E1000_DMCCNT_CCOUNT_MASK\t0x01FFFFFF\n\n/* Flow ctrl Rx Threshold High val */\n#define E1000_FCRTC_RTH_COAL_MASK\t0x0003FFF0\n#define E1000_FCRTC_RTH_COAL_SHIFT\t4\n/* Lx power decision based on DMA coal */\n#define E1000_PCIEMISC_LX_DECISION\t0x00000080\n\n#define E1000_RXPBS_CFG_TS_EN\t\t0x80000000 /* Timestamp in Rx buffer */\n#define E1000_RXPBS_SIZE_I210_MASK\t0x0000003F /* Rx packet buffer size */\n#define E1000_TXPB0S_SIZE_I210_MASK\t0x0000003F /* Tx packet buffer 0 size */\n\n/* Proxy Filter Control */\n#define E1000_PROXYFC_D0\t\t0x00000001 /* Enable offload in D0 */\n#define E1000_PROXYFC_EX\t\t0x00000004 /* Directed exact proxy */\n#define E1000_PROXYFC_MC\t\t0x00000008 /* Directed MC Proxy */\n#define E1000_PROXYFC_BC\t\t0x00000010 /* Broadcast Proxy Enable */\n#define E1000_PROXYFC_ARP_DIRECTED\t0x00000020 /* Directed ARP Proxy Ena */\n#define E1000_PROXYFC_IPV4\t\t0x00000040 /* Directed IPv4 Enable */\n#define E1000_PROXYFC_IPV6\t\t0x00000080 /* Directed IPv6 Enable */\n#define E1000_PROXYFC_NS\t\t0x00000200 /* IPv6 Neighbor Solicitation */\n#define E1000_PROXYFC_ARP\t\t0x00000800 /* ARP Request Proxy Ena */\n/* Proxy Status */\n#define E1000_PROXYS_CLEAR\t\t0xFFFFFFFF /* Clear */\n\n/* Firmware Status */\n#define E1000_FWSTS_FWRI\t\t0x80000000 /* FW Reset Indication */\n/* VF Control */\n#define E1000_VTCTRL_RST\t\t0x04000000 /* Reset VF */\n\n#define E1000_STATUS_LAN_ID_MASK\t0x00000000C /* Mask for Lan ID field */\n/* Lan ID bit field offset in status register */\n#define E1000_STATUS_LAN_ID_OFFSET\t2\n#define E1000_VFTA_ENTRIES\t\t128\n#ifndef E1000_UNUSEDARG\n#define E1000_UNUSEDARG\n#endif /* E1000_UNUSEDARG */\n#endif /* _E1000_DEFINES_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_hw.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _E1000_HW_H_\n#define _E1000_HW_H_\n\n#include \"e1000_osdep.h\"\n#include \"e1000_regs.h\"\n#include \"e1000_defines.h\"\n\nstruct e1000_hw;\n\n#define E1000_DEV_ID_82576\t\t\t0x10C9\n#define E1000_DEV_ID_82576_FIBER\t\t0x10E6\n#define E1000_DEV_ID_82576_SERDES\t\t0x10E7\n#define E1000_DEV_ID_82576_QUAD_COPPER\t\t0x10E8\n#define E1000_DEV_ID_82576_QUAD_COPPER_ET2\t0x1526\n#define E1000_DEV_ID_82576_NS\t\t\t0x150A\n#define E1000_DEV_ID_82576_NS_SERDES\t\t0x1518\n#define E1000_DEV_ID_82576_SERDES_QUAD\t\t0x150D\n#define E1000_DEV_ID_82575EB_COPPER\t\t0x10A7\n#define E1000_DEV_ID_82575EB_FIBER_SERDES\t0x10A9\n#define E1000_DEV_ID_82575GB_QUAD_COPPER\t0x10D6\n#define E1000_DEV_ID_82580_COPPER\t\t0x150E\n#define E1000_DEV_ID_82580_FIBER\t\t0x150F\n#define E1000_DEV_ID_82580_SERDES\t\t0x1510\n#define E1000_DEV_ID_82580_SGMII\t\t0x1511\n#define E1000_DEV_ID_82580_COPPER_DUAL\t\t0x1516\n#define E1000_DEV_ID_82580_QUAD_FIBER\t\t0x1527\n#define E1000_DEV_ID_I350_COPPER\t\t0x1521\n#define E1000_DEV_ID_I350_FIBER\t\t\t0x1522\n#define E1000_DEV_ID_I350_SERDES\t\t0x1523\n#define E1000_DEV_ID_I350_SGMII\t\t\t0x1524\n#define E1000_DEV_ID_I350_DA4\t\t\t0x1546\n#define E1000_DEV_ID_I210_COPPER\t\t0x1533\n#define E1000_DEV_ID_I210_COPPER_OEM1\t\t0x1534\n#define E1000_DEV_ID_I210_COPPER_IT\t\t0x1535\n#define E1000_DEV_ID_I210_FIBER\t\t\t0x1536\n#define E1000_DEV_ID_I210_SERDES\t\t0x1537\n#define E1000_DEV_ID_I210_SGMII\t\t\t0x1538\n#define E1000_DEV_ID_I210_COPPER_FLASHLESS\t0x157B\n#define E1000_DEV_ID_I210_SERDES_FLASHLESS\t0x157C\n#define E1000_DEV_ID_I211_COPPER\t\t0x1539\n#define E1000_DEV_ID_I354_BACKPLANE_1GBPS\t0x1F40\n#define E1000_DEV_ID_I354_SGMII\t\t\t0x1F41\n#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS\t0x1F45\n#define E1000_DEV_ID_DH89XXCC_SGMII\t\t0x0438\n#define E1000_DEV_ID_DH89XXCC_SERDES\t\t0x043A\n#define E1000_DEV_ID_DH89XXCC_BACKPLANE\t\t0x043C\n#define E1000_DEV_ID_DH89XXCC_SFP\t\t0x0440\n\n#define E1000_REVISION_0\t0\n#define E1000_REVISION_1\t1\n#define E1000_REVISION_2\t2\n#define E1000_REVISION_3\t3\n#define E1000_REVISION_4\t4\n\n#define E1000_FUNC_0\t\t0\n#define E1000_FUNC_1\t\t1\n#define E1000_FUNC_2\t\t2\n#define E1000_FUNC_3\t\t3\n\n#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0\t0\n#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1\t3\n#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2\t6\n#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3\t9\n\nenum e1000_mac_type {\n\te1000_undefined = 0,\n\te1000_82575,\n\te1000_82576,\n\te1000_82580,\n\te1000_i350,\n\te1000_i354,\n\te1000_i210,\n\te1000_i211,\n\te1000_num_macs /* List is 1-based, so subtract 1 for true count. */\n};\n\nenum e1000_media_type {\n\te1000_media_type_unknown = 0,\n\te1000_media_type_copper = 1,\n\te1000_media_type_fiber = 2,\n\te1000_media_type_internal_serdes = 3,\n\te1000_num_media_types\n};\n\nenum e1000_nvm_type {\n\te1000_nvm_unknown = 0,\n\te1000_nvm_none,\n\te1000_nvm_eeprom_spi,\n\te1000_nvm_flash_hw,\n\te1000_nvm_invm,\n\te1000_nvm_flash_sw\n};\n\nenum e1000_nvm_override {\n\te1000_nvm_override_none = 0,\n\te1000_nvm_override_spi_small,\n\te1000_nvm_override_spi_large,\n};\n\nenum e1000_phy_type {\n\te1000_phy_unknown = 0,\n\te1000_phy_none,\n\te1000_phy_m88,\n\te1000_phy_igp,\n\te1000_phy_igp_2,\n\te1000_phy_gg82563,\n\te1000_phy_igp_3,\n\te1000_phy_ife,\n\te1000_phy_82580,\n\te1000_phy_vf,\n\te1000_phy_i210,\n};\n\nenum e1000_bus_type {\n\te1000_bus_type_unknown = 0,\n\te1000_bus_type_pci,\n\te1000_bus_type_pcix,\n\te1000_bus_type_pci_express,\n\te1000_bus_type_reserved\n};\n\nenum e1000_bus_speed {\n\te1000_bus_speed_unknown = 0,\n\te1000_bus_speed_33,\n\te1000_bus_speed_66,\n\te1000_bus_speed_100,\n\te1000_bus_speed_120,\n\te1000_bus_speed_133,\n\te1000_bus_speed_2500,\n\te1000_bus_speed_5000,\n\te1000_bus_speed_reserved\n};\n\nenum e1000_bus_width {\n\te1000_bus_width_unknown = 0,\n\te1000_bus_width_pcie_x1,\n\te1000_bus_width_pcie_x2,\n\te1000_bus_width_pcie_x4 = 4,\n\te1000_bus_width_pcie_x8 = 8,\n\te1000_bus_width_32,\n\te1000_bus_width_64,\n\te1000_bus_width_reserved\n};\n\nenum e1000_1000t_rx_status {\n\te1000_1000t_rx_status_not_ok = 0,\n\te1000_1000t_rx_status_ok,\n\te1000_1000t_rx_status_undefined = 0xFF\n};\n\nenum e1000_rev_polarity {\n\te1000_rev_polarity_normal = 0,\n\te1000_rev_polarity_reversed,\n\te1000_rev_polarity_undefined = 0xFF\n};\n\nenum e1000_fc_mode {\n\te1000_fc_none = 0,\n\te1000_fc_rx_pause,\n\te1000_fc_tx_pause,\n\te1000_fc_full,\n\te1000_fc_default = 0xFF\n};\n\nenum e1000_ms_type {\n\te1000_ms_hw_default = 0,\n\te1000_ms_force_master,\n\te1000_ms_force_slave,\n\te1000_ms_auto\n};\n\nenum e1000_smart_speed {\n\te1000_smart_speed_default = 0,\n\te1000_smart_speed_on,\n\te1000_smart_speed_off\n};\n\nenum e1000_serdes_link_state {\n\te1000_serdes_link_down = 0,\n\te1000_serdes_link_autoneg_progress,\n\te1000_serdes_link_autoneg_complete,\n\te1000_serdes_link_forced_up\n};\n\n#ifndef __le16\n#define __le16 u16\n#endif\n#ifndef __le32\n#define __le32 u32\n#endif\n#ifndef __le64\n#define __le64 u64\n#endif\n/* Receive Descriptor */\nstruct e1000_rx_desc {\n\t__le64 buffer_addr; /* Address of the descriptor's data buffer */\n\t__le16 length; /* Length of data DMAed into data buffer */\n\t__le16 csum; /* Packet checksum */\n\tu8 status; /* Descriptor status */\n\tu8 errors; /* Descriptor Errors */\n\t__le16 special;\n};\n\n/* Receive Descriptor - Extended */\nunion e1000_rx_desc_extended {\n\tstruct {\n\t\t__le64 buffer_addr;\n\t\t__le64 reserved;\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq; /* Multiple Rx Queues */\n\t\t\tunion {\n\t\t\t\t__le32 rss; /* RSS Hash */\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id; /* IP id */\n\t\t\t\t\t__le16 csum; /* Packet Checksum */\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error; /* ext status/error */\n\t\t\t__le16 length;\n\t\t\t__le16 vlan; /* VLAN tag */\n\t\t} upper;\n\t} wb; /* writeback */\n};\n\n#define MAX_PS_BUFFERS 4\n\n/* Number of packet split data buffers (not including the header buffer) */\n#define PS_PAGE_BUFFERS\t(MAX_PS_BUFFERS - 1)\n\n/* Receive Descriptor - Packet Split */\nunion e1000_rx_desc_packet_split {\n\tstruct {\n\t\t/* one buffer for protocol header(s), three data buffers */\n\t\t__le64 buffer_addr[MAX_PS_BUFFERS];\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\t__le32 mrq; /* Multiple Rx Queues */\n\t\t\tunion {\n\t\t\t\t__le32 rss; /* RSS Hash */\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id; /* IP id */\n\t\t\t\t\t__le16 csum; /* Packet Checksum */\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error; /* ext status/error */\n\t\t\t__le16 length0; /* length of buffer 0 */\n\t\t\t__le16 vlan; /* VLAN tag */\n\t\t} middle;\n\t\tstruct {\n\t\t\t__le16 header_status;\n\t\t\t/* length of buffers 1-3 */\n\t\t\t__le16 length[PS_PAGE_BUFFERS];\n\t\t} upper;\n\t\t__le64 reserved;\n\t} wb; /* writeback */\n};\n\n/* Transmit Descriptor */\nstruct e1000_tx_desc {\n\t__le64 buffer_addr; /* Address of the descriptor's data buffer */\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\t__le16 length; /* Data buffer length */\n\t\t\tu8 cso; /* Checksum offset */\n\t\t\tu8 cmd; /* Descriptor control */\n\t\t} flags;\n\t} lower;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status; /* Descriptor status */\n\t\t\tu8 css; /* Checksum start */\n\t\t\t__le16 special;\n\t\t} fields;\n\t} upper;\n};\n\n/* Offload Context Descriptor */\nstruct e1000_context_desc {\n\tunion {\n\t\t__le32 ip_config;\n\t\tstruct {\n\t\t\tu8 ipcss; /* IP checksum start */\n\t\t\tu8 ipcso; /* IP checksum offset */\n\t\t\t__le16 ipcse; /* IP checksum end */\n\t\t} ip_fields;\n\t} lower_setup;\n\tunion {\n\t\t__le32 tcp_config;\n\t\tstruct {\n\t\t\tu8 tucss; /* TCP checksum start */\n\t\t\tu8 tucso; /* TCP checksum offset */\n\t\t\t__le16 tucse; /* TCP checksum end */\n\t\t} tcp_fields;\n\t} upper_setup;\n\t__le32 cmd_and_length;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status; /* Descriptor status */\n\t\t\tu8 hdr_len; /* Header length */\n\t\t\t__le16 mss; /* Maximum segment size */\n\t\t} fields;\n\t} tcp_seg_setup;\n};\n\n/* Offload data descriptor */\nstruct e1000_data_desc {\n\t__le64 buffer_addr; /* Address of the descriptor's buffer address */\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\t__le16 length; /* Data buffer length */\n\t\t\tu8 typ_len_ext;\n\t\t\tu8 cmd;\n\t\t} flags;\n\t} lower;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status; /* Descriptor status */\n\t\t\tu8 popts; /* Packet Options */\n\t\t\t__le16 special;\n\t\t} fields;\n\t} upper;\n};\n\n/* Statistics counters collected by the MAC */\nstruct e1000_hw_stats {\n\tu64 crcerrs;\n\tu64 algnerrc;\n\tu64 symerrs;\n\tu64 rxerrc;\n\tu64 mpc;\n\tu64 scc;\n\tu64 ecol;\n\tu64 mcc;\n\tu64 latecol;\n\tu64 colc;\n\tu64 dc;\n\tu64 tncrs;\n\tu64 sec;\n\tu64 cexterr;\n\tu64 rlec;\n\tu64 xonrxc;\n\tu64 xontxc;\n\tu64 xoffrxc;\n\tu64 xofftxc;\n\tu64 fcruc;\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 rnbc;\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rjc;\n\tu64 mgprc;\n\tu64 mgpdc;\n\tu64 mgptc;\n\tu64 tor;\n\tu64 tot;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 tsctc;\n\tu64 tsctfc;\n\tu64 iac;\n\tu64 icrxptc;\n\tu64 icrxatc;\n\tu64 ictxptc;\n\tu64 ictxatc;\n\tu64 ictxqec;\n\tu64 ictxqmtc;\n\tu64 icrxdmtc;\n\tu64 icrxoc;\n\tu64 cbtmpc;\n\tu64 htdpmc;\n\tu64 cbrdpc;\n\tu64 cbrmpc;\n\tu64 rpthc;\n\tu64 hgptc;\n\tu64 htcbdpc;\n\tu64 hgorc;\n\tu64 hgotc;\n\tu64 lenerrs;\n\tu64 scvpc;\n\tu64 hrmpc;\n\tu64 doosync;\n\tu64 o2bgptc;\n\tu64 o2bspc;\n\tu64 b2ospc;\n\tu64 b2ogprc;\n};\n\n\nstruct e1000_phy_stats {\n\tu32 idle_errors;\n\tu32 receive_errors;\n};\n\nstruct e1000_host_mng_dhcp_cookie {\n\tu32 signature;\n\tu8 status;\n\tu8 reserved0;\n\tu16 vlan_id;\n\tu32 reserved1;\n\tu16 reserved2;\n\tu8 reserved3;\n\tu8 checksum;\n};\n\n/* Host Interface \"Rev 1\" */\nstruct e1000_host_command_header {\n\tu8 command_id;\n\tu8 command_length;\n\tu8 command_options;\n\tu8 checksum;\n};\n\n#define E1000_HI_MAX_DATA_LENGTH\t252\nstruct e1000_host_command_info {\n\tstruct e1000_host_command_header command_header;\n\tu8 command_data[E1000_HI_MAX_DATA_LENGTH];\n};\n\n/* Host Interface \"Rev 2\" */\nstruct e1000_host_mng_command_header {\n\tu8 command_id;\n\tu8 checksum;\n\tu16 reserved1;\n\tu16 reserved2;\n\tu16 command_length;\n};\n\n#define E1000_HI_MAX_MNG_DATA_LENGTH\t0x6F8\nstruct e1000_host_mng_command_info {\n\tstruct e1000_host_mng_command_header command_header;\n\tu8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];\n};\n\n#include \"e1000_mac.h\"\n#include \"e1000_phy.h\"\n#include \"e1000_nvm.h\"\n#include \"e1000_manage.h\"\n#include \"e1000_mbx.h\"\n\n/* Function pointers for the MAC. */\nstruct e1000_mac_operations {\n\ts32 (*init_params)(struct e1000_hw *);\n\ts32 (*id_led_init)(struct e1000_hw *);\n\ts32 (*blink_led)(struct e1000_hw *);\n\tbool (*check_mng_mode)(struct e1000_hw *);\n\ts32 (*check_for_link)(struct e1000_hw *);\n\ts32 (*cleanup_led)(struct e1000_hw *);\n\tvoid (*clear_hw_cntrs)(struct e1000_hw *);\n\tvoid (*clear_vfta)(struct e1000_hw *);\n\ts32 (*get_bus_info)(struct e1000_hw *);\n\tvoid (*set_lan_id)(struct e1000_hw *);\n\ts32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);\n\ts32 (*led_on)(struct e1000_hw *);\n\ts32 (*led_off)(struct e1000_hw *);\n\tvoid (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);\n\ts32 (*reset_hw)(struct e1000_hw *);\n\ts32 (*init_hw)(struct e1000_hw *);\n\tvoid (*shutdown_serdes)(struct e1000_hw *);\n\tvoid (*power_up_serdes)(struct e1000_hw *);\n\ts32 (*setup_link)(struct e1000_hw *);\n\ts32 (*setup_physical_interface)(struct e1000_hw *);\n\ts32 (*setup_led)(struct e1000_hw *);\n\tvoid (*write_vfta)(struct e1000_hw *, u32, u32);\n\tvoid (*config_collision_dist)(struct e1000_hw *);\n\tvoid (*rar_set)(struct e1000_hw *, u8*, u32);\n\ts32 (*read_mac_addr)(struct e1000_hw *);\n\ts32 (*validate_mdi_setting)(struct e1000_hw *);\n\ts32 (*get_thermal_sensor_data)(struct e1000_hw *);\n\ts32 (*init_thermal_sensor_thresh)(struct e1000_hw *);\n\ts32 (*acquire_swfw_sync)(struct e1000_hw *, u16);\n\tvoid (*release_swfw_sync)(struct e1000_hw *, u16);\n};\n\n/* When to use various PHY register access functions:\n *\n * Func Caller\n * Function Does Does When to use\n * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n * X_reg L,P,A n/a for simple PHY reg accesses\n * X_reg_locked P,A L for multiple accesses of different regs\n * on different pages\n * X_reg_page A L,P for multiple accesses of different regs\n * on the same page\n *\n * Where X=[read|write], L=locking, P=sets page, A=register access\n *\n */\nstruct e1000_phy_operations {\n\ts32 (*init_params)(struct e1000_hw *);\n\ts32 (*acquire)(struct e1000_hw *);\n\ts32 (*check_polarity)(struct e1000_hw *);\n\ts32 (*check_reset_block)(struct e1000_hw *);\n\ts32 (*commit)(struct e1000_hw *);\n\ts32 (*force_speed_duplex)(struct e1000_hw *);\n\ts32 (*get_cfg_done)(struct e1000_hw *hw);\n\ts32 (*get_cable_length)(struct e1000_hw *);\n\ts32 (*get_info)(struct e1000_hw *);\n\ts32 (*set_page)(struct e1000_hw *, u16);\n\ts32 (*read_reg)(struct e1000_hw *, u32, u16 *);\n\ts32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);\n\ts32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);\n\tvoid (*release)(struct e1000_hw *);\n\ts32 (*reset)(struct e1000_hw *);\n\ts32 (*set_d0_lplu_state)(struct e1000_hw *, bool);\n\ts32 (*set_d3_lplu_state)(struct e1000_hw *, bool);\n\ts32 (*write_reg)(struct e1000_hw *, u32, u16);\n\ts32 (*write_reg_locked)(struct e1000_hw *, u32, u16);\n\ts32 (*write_reg_page)(struct e1000_hw *, u32, u16);\n\tvoid (*power_up)(struct e1000_hw *);\n\tvoid (*power_down)(struct e1000_hw *);\n\ts32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);\n\ts32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);\n};\n\n/* Function pointers for the NVM. */\nstruct e1000_nvm_operations {\n\ts32 (*init_params)(struct e1000_hw *);\n\ts32 (*acquire)(struct e1000_hw *);\n\ts32 (*read)(struct e1000_hw *, u16, u16, u16 *);\n\tvoid (*release)(struct e1000_hw *);\n\tvoid (*reload)(struct e1000_hw *);\n\ts32 (*update)(struct e1000_hw *);\n\ts32 (*valid_led_default)(struct e1000_hw *, u16 *);\n\ts32 (*validate)(struct e1000_hw *);\n\ts32 (*write)(struct e1000_hw *, u16, u16, u16 *);\n};\n\n#define E1000_MAX_SENSORS\t\t3\n\nstruct e1000_thermal_diode_data {\n\tu8 location;\n\tu8 temp;\n\tu8 caution_thresh;\n\tu8 max_op_thresh;\n};\n\nstruct e1000_thermal_sensor_data {\n\tstruct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];\n};\n\nstruct e1000_mac_info {\n\tstruct e1000_mac_operations ops;\n\tu8 addr[ETH_ADDR_LEN];\n\tu8 perm_addr[ETH_ADDR_LEN];\n\n\tenum e1000_mac_type type;\n\n\tu32 collision_delta;\n\tu32 ledctl_default;\n\tu32 ledctl_mode1;\n\tu32 ledctl_mode2;\n\tu32 mc_filter_type;\n\tu32 tx_packet_delta;\n\tu32 txcw;\n\n\tu16 current_ifs_val;\n\tu16 ifs_max_val;\n\tu16 ifs_min_val;\n\tu16 ifs_ratio;\n\tu16 ifs_step_size;\n\tu16 mta_reg_count;\n\tu16 uta_reg_count;\n\n\t/* Maximum size of the MTA register table in all supported adapters */\n\t#define MAX_MTA_REG 128\n\tu32 mta_shadow[MAX_MTA_REG];\n\tu16 rar_entry_count;\n\n\tu8 forced_speed_duplex;\n\n\tbool adaptive_ifs;\n\tbool has_fwsm;\n\tbool arc_subsystem_valid;\n\tbool asf_firmware_present;\n\tbool autoneg;\n\tbool autoneg_failed;\n\tbool get_link_status;\n\tbool in_ifs_mode;\n\tenum e1000_serdes_link_state serdes_link_state;\n\tbool serdes_has_link;\n\tbool tx_pkt_filtering;\n\tstruct e1000_thermal_sensor_data thermal_sensor_data;\n};\n\nstruct e1000_phy_info {\n\tstruct e1000_phy_operations ops;\n\tenum e1000_phy_type type;\n\n\tenum e1000_1000t_rx_status local_rx;\n\tenum e1000_1000t_rx_status remote_rx;\n\tenum e1000_ms_type ms_type;\n\tenum e1000_ms_type original_ms_type;\n\tenum e1000_rev_polarity cable_polarity;\n\tenum e1000_smart_speed smart_speed;\n\n\tu32 addr;\n\tu32 id;\n\tu32 reset_delay_us; /* in usec */\n\tu32 revision;\n\n\tenum e1000_media_type media_type;\n\n\tu16 autoneg_advertised;\n\tu16 autoneg_mask;\n\tu16 cable_length;\n\tu16 max_cable_length;\n\tu16 min_cable_length;\n\n\tu8 mdix;\n\n\tbool disable_polarity_correction;\n\tbool is_mdix;\n\tbool polarity_correction;\n\tbool reset_disable;\n\tbool speed_downgraded;\n\tbool autoneg_wait_to_complete;\n};\n\nstruct e1000_nvm_info {\n\tstruct e1000_nvm_operations ops;\n\tenum e1000_nvm_type type;\n\tenum e1000_nvm_override override;\n\n\tu32 flash_bank_size;\n\tu32 flash_base_addr;\n\n\tu16 word_size;\n\tu16 delay_usec;\n\tu16 address_bits;\n\tu16 opcode_bits;\n\tu16 page_size;\n};\n\nstruct e1000_bus_info {\n\tenum e1000_bus_type type;\n\tenum e1000_bus_speed speed;\n\tenum e1000_bus_width width;\n\n\tu16 func;\n\tu16 pci_cmd_word;\n};\n\nstruct e1000_fc_info {\n\tu32 high_water; /* Flow control high-water mark */\n\tu32 low_water; /* Flow control low-water mark */\n\tu16 pause_time; /* Flow control pause timer */\n\tu16 refresh_time; /* Flow control refresh timer */\n\tbool send_xon; /* Flow control send XON */\n\tbool strict_ieee; /* Strict IEEE mode */\n\tenum e1000_fc_mode current_mode; /* FC mode in effect */\n\tenum e1000_fc_mode requested_mode; /* FC mode requested by caller */\n};\n\nstruct e1000_mbx_operations {\n\ts32 (*init_params)(struct e1000_hw *hw);\n\ts32 (*read)(struct e1000_hw *, u32 *, u16, u16);\n\ts32 (*write)(struct e1000_hw *, u32 *, u16, u16);\n\ts32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);\n\ts32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);\n\ts32 (*check_for_msg)(struct e1000_hw *, u16);\n\ts32 (*check_for_ack)(struct e1000_hw *, u16);\n\ts32 (*check_for_rst)(struct e1000_hw *, u16);\n};\n\nstruct e1000_mbx_stats {\n\tu32 msgs_tx;\n\tu32 msgs_rx;\n\n\tu32 acks;\n\tu32 reqs;\n\tu32 rsts;\n};\n\nstruct e1000_mbx_info {\n\tstruct e1000_mbx_operations ops;\n\tstruct e1000_mbx_stats stats;\n\tu32 timeout;\n\tu32 usec_delay;\n\tu16 size;\n};\n\nstruct e1000_dev_spec_82575 {\n\tbool sgmii_active;\n\tbool global_device_reset;\n\tbool eee_disable;\n\tbool module_plugged;\n\tbool clear_semaphore_once;\n\tu32 mtu;\n\tstruct sfp_e1000_flags eth_flags;\n\tu8 media_port;\n\tbool media_changed;\n};\n\nstruct e1000_dev_spec_vf {\n\tu32 vf_number;\n\tu32 v2p_mailbox;\n};\n\nstruct e1000_hw {\n\tvoid *back;\n\n\tu8 __iomem *hw_addr;\n\tu8 __iomem *flash_address;\n\tunsigned long io_base;\n\n\tstruct e1000_mac_info mac;\n\tstruct e1000_fc_info fc;\n\tstruct e1000_phy_info phy;\n\tstruct e1000_nvm_info nvm;\n\tstruct e1000_bus_info bus;\n\tstruct e1000_mbx_info mbx;\n\tstruct e1000_host_mng_dhcp_cookie mng_cookie;\n\n\tunion {\n\t\tstruct e1000_dev_spec_82575 _82575;\n\t\tstruct e1000_dev_spec_vf vf;\n\t} dev_spec;\n\n\tu16 device_id;\n\tu16 subsystem_vendor_id;\n\tu16 subsystem_device_id;\n\tu16 vendor_id;\n\n\tu8 revision_id;\n};\n\n#include \"e1000_82575.h\"\n#include \"e1000_i210.h\"\n\n/* These functions must be implemented by drivers */\ns32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);\ns32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);\n\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_i210.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"e1000_api.h\"\n\n\nstatic s32 e1000_acquire_nvm_i210(struct e1000_hw *hw);\nstatic void e1000_release_nvm_i210(struct e1000_hw *hw);\nstatic s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw);\nstatic s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t\tu16 *data);\nstatic s32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw);\nstatic s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data);\n\n/**\n * e1000_acquire_nvm_i210 - Request for access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Acquire the necessary semaphores for exclusive access to the EEPROM.\n * Set the EEPROM access request bit and wait for EEPROM access grant bit.\n * Return successful if access grant bit set, else clear the request for\n * EEPROM access and return -E1000_ERR_NVM (-1).\n **/\nstatic s32 e1000_acquire_nvm_i210(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_acquire_nvm_i210\");\n\n\tret_val = e1000_acquire_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_release_nvm_i210 - Release exclusive access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Stop any current commands to the EEPROM and clear the EEPROM request bit,\n * then release the semaphores acquired.\n **/\nstatic void e1000_release_nvm_i210(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_release_nvm_i210\");\n\n\te1000_release_swfw_sync_i210(hw, E1000_SWFW_EEP_SM);\n}\n\n/**\n * e1000_acquire_swfw_sync_i210 - Acquire SW/FW semaphore\n * @hw: pointer to the HW structure\n * @mask: specifies which semaphore to acquire\n *\n * Acquire the SW/FW semaphore to access the PHY or NVM. The mask\n * will also specify which port we're acquiring the lock for.\n **/\ns32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask)\n{\n\tu32 swfw_sync;\n\tu32 swmask = mask;\n\tu32 fwmask = mask << 16;\n\ts32 ret_val = E1000_SUCCESS;\n\ts32 i = 0, timeout = 200; /* FIXME: find real value to use here */\n\n\tDEBUGFUNC(\"e1000_acquire_swfw_sync_i210\");\n\n\twhile (i < timeout) {\n\t\tif (e1000_get_hw_semaphore_i210(hw)) {\n\t\t\tret_val = -E1000_ERR_SWFW_SYNC;\n\t\t\tgoto out;\n\t\t}\n\n\t\tswfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);\n\t\tif (!(swfw_sync & (fwmask | swmask)))\n\t\t\tbreak;\n\n\t\t/*\n\t\t * Firmware currently using resource (fwmask)\n\t\t * or other software thread using resource (swmask)\n\t\t */\n\t\te1000_put_hw_semaphore_generic(hw);\n\t\tmsec_delay_irq(5);\n\t\ti++;\n\t}\n\n\tif (i == timeout) {\n\t\tDEBUGOUT(\"Driver can't access resource, SW_FW_SYNC timeout.\\n\");\n\t\tret_val = -E1000_ERR_SWFW_SYNC;\n\t\tgoto out;\n\t}\n\n\tswfw_sync |= swmask;\n\tE1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);\n\n\te1000_put_hw_semaphore_generic(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_release_swfw_sync_i210 - Release SW/FW semaphore\n * @hw: pointer to the HW structure\n * @mask: specifies which semaphore to acquire\n *\n * Release the SW/FW semaphore used to access the PHY or NVM. The mask\n * will also specify which port we're releasing the lock for.\n **/\nvoid e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask)\n{\n\tu32 swfw_sync;\n\n\tDEBUGFUNC(\"e1000_release_swfw_sync_i210\");\n\n\twhile (e1000_get_hw_semaphore_i210(hw) != E1000_SUCCESS)\n\t\t; /* Empty */\n\n\tswfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);\n\tswfw_sync &= ~mask;\n\tE1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);\n\n\te1000_put_hw_semaphore_generic(hw);\n}\n\n/**\n * e1000_get_hw_semaphore_i210 - Acquire hardware semaphore\n * @hw: pointer to the HW structure\n *\n * Acquire the HW semaphore to access the PHY or NVM\n **/\nstatic s32 e1000_get_hw_semaphore_i210(struct e1000_hw *hw)\n{\n\tu32 swsm;\n\ts32 timeout = hw->nvm.word_size + 1;\n\ts32 i = 0;\n\n\tDEBUGFUNC(\"e1000_get_hw_semaphore_i210\");\n\n\t/* Get the SW semaphore */\n\twhile (i < timeout) {\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tif (!(swsm & E1000_SWSM_SMBI))\n\t\t\tbreak;\n\n\t\tusec_delay(50);\n\t\ti++;\n\t}\n\n\tif (i == timeout) {\n\t\t/* In rare circumstances, the SW semaphore may already be held\n\t\t * unintentionally. Clear the semaphore once before giving up.\n\t\t */\n\t\tif (hw->dev_spec._82575.clear_semaphore_once) {\n\t\t\thw->dev_spec._82575.clear_semaphore_once = false;\n\t\t\te1000_put_hw_semaphore_generic(hw);\n\t\t\tfor (i = 0; i < timeout; i++) {\n\t\t\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\t\t\tif (!(swsm & E1000_SWSM_SMBI))\n\t\t\t\t\tbreak;\n\n\t\t\t\tusec_delay(50);\n\t\t\t}\n\t\t}\n\n\t\t/* If we do not have the semaphore here, we have to give up. */\n\t\tif (i == timeout) {\n\t\t\tDEBUGOUT(\"Driver can't access device - SMBI bit is set.\\n\");\n\t\t\treturn -E1000_ERR_NVM;\n\t\t}\n\t}\n\n\t/* Get the FW semaphore. */\n\tfor (i = 0; i < timeout; i++) {\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tE1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);\n\n\t\t/* Semaphore acquired if bit latched */\n\t\tif (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)\n\t\t\tbreak;\n\n\t\tusec_delay(50);\n\t}\n\n\tif (i == timeout) {\n\t\t/* Release semaphores */\n\t\te1000_put_hw_semaphore_generic(hw);\n\t\tDEBUGOUT(\"Driver can't access the NVM\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register\n * @hw: pointer to the HW structure\n * @offset: offset of word in the Shadow Ram to read\n * @words: number of words to read\n * @data: word read from the Shadow Ram\n *\n * Reads a 16 bit word from the Shadow Ram using the EERD register.\n * Uses necessary synchronization semaphores.\n **/\ns32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t u16 *data)\n{\n\ts32 status = E1000_SUCCESS;\n\tu16 i, count;\n\n\tDEBUGFUNC(\"e1000_read_nvm_srrd_i210\");\n\n\t/* We cannot hold synchronization semaphores for too long,\n\t * because of forceful takeover procedure. However it is more efficient\n\t * to read in bursts than synchronizing access for each word. */\n\tfor (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {\n\t\tcount = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?\n\t\t\tE1000_EERD_EEWR_MAX_COUNT : (words - i);\n\t\tif (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {\n\t\t\tstatus = e1000_read_nvm_eerd(hw, offset, count,\n\t\t\t\t\t\t data + i);\n\t\t\thw->nvm.ops.release(hw);\n\t\t} else {\n\t\t\tstatus = E1000_ERR_SWFW_SYNC;\n\t\t}\n\n\t\tif (status != E1000_SUCCESS)\n\t\t\tbreak;\n\t}\n\n\treturn status;\n}\n\n/**\n * e1000_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR\n * @hw: pointer to the HW structure\n * @offset: offset within the Shadow RAM to be written to\n * @words: number of words to write\n * @data: 16 bit word(s) to be written to the Shadow RAM\n *\n * Writes data to Shadow RAM at offset using EEWR register.\n *\n * If e1000_update_nvm_checksum is not called after this function , the\n * data will not be committed to FLASH and also Shadow RAM will most likely\n * contain an invalid checksum.\n *\n * If error code is returned, data and Shadow RAM may be inconsistent - buffer\n * partially written.\n **/\ns32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t u16 *data)\n{\n\ts32 status = E1000_SUCCESS;\n\tu16 i, count;\n\n\tDEBUGFUNC(\"e1000_write_nvm_srwr_i210\");\n\n\t/* We cannot hold synchronization semaphores for too long,\n\t * because of forceful takeover procedure. However it is more efficient\n\t * to write in bursts than synchronizing access for each word. */\n\tfor (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {\n\t\tcount = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?\n\t\t\tE1000_EERD_EEWR_MAX_COUNT : (words - i);\n\t\tif (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {\n\t\t\tstatus = e1000_write_nvm_srwr(hw, offset, count,\n\t\t\t\t\t\t data + i);\n\t\t\thw->nvm.ops.release(hw);\n\t\t} else {\n\t\t\tstatus = E1000_ERR_SWFW_SYNC;\n\t\t}\n\n\t\tif (status != E1000_SUCCESS)\n\t\t\tbreak;\n\t}\n\n\treturn status;\n}\n\n/**\n * e1000_write_nvm_srwr - Write to Shadow Ram using EEWR\n * @hw: pointer to the HW structure\n * @offset: offset within the Shadow Ram to be written to\n * @words: number of words to write\n * @data: 16 bit word(s) to be written to the Shadow Ram\n *\n * Writes data to Shadow Ram at offset using EEWR register.\n *\n * If e1000_update_nvm_checksum is not called after this function , the\n * Shadow Ram will most likely contain an invalid checksum.\n **/\nstatic s32 e1000_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t\tu16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 i, k, eewr = 0;\n\tu32 attempts = 100000;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_write_nvm_srwr\");\n\n\t/*\n\t * A check for invalid values: offset too large, too many words,\n\t * too many words for the offset, and not enough words.\n\t */\n\tif ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\tret_val = -E1000_ERR_NVM;\n\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < words; i++) {\n\t\teewr = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |\n\t\t\t(data[i] << E1000_NVM_RW_REG_DATA) |\n\t\t\tE1000_NVM_RW_REG_START;\n\n\t\tE1000_WRITE_REG(hw, E1000_SRWR, eewr);\n\n\t\tfor (k = 0; k < attempts; k++) {\n\t\t\tif (E1000_NVM_RW_REG_DONE &\n\t\t\t E1000_READ_REG(hw, E1000_SRWR)) {\n\t\t\t\tret_val = E1000_SUCCESS;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tusec_delay(5);\n\t\t}\n\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\tDEBUGOUT(\"Shadow RAM write EEWR timed out\\n\");\n\t\t\tbreak;\n\t\t}\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/** e1000_read_invm_word_i210 - Reads OTP\n * @hw: pointer to the HW structure\n * @address: the word address (aka eeprom offset) to read\n * @data: pointer to the data read\n *\n * Reads 16-bit words from the OTP. Return error when the word is not\n * stored in OTP.\n **/\nstatic s32 e1000_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data)\n{\n\ts32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;\n\tu32 invm_dword;\n\tu16 i;\n\tu8 record_type, word_address;\n\n\tDEBUGFUNC(\"e1000_read_invm_word_i210\");\n\n\tfor (i = 0; i < E1000_INVM_SIZE; i++) {\n\t\tinvm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));\n\t\t/* Get record type */\n\t\trecord_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword);\n\t\tif (record_type == E1000_INVM_UNINITIALIZED_STRUCTURE)\n\t\t\tbreak;\n\t\tif (record_type == E1000_INVM_CSR_AUTOLOAD_STRUCTURE)\n\t\t\ti += E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS;\n\t\tif (record_type == E1000_INVM_RSA_KEY_SHA256_STRUCTURE)\n\t\t\ti += E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS;\n\t\tif (record_type == E1000_INVM_WORD_AUTOLOAD_STRUCTURE) {\n\t\t\tword_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword);\n\t\t\tif (word_address == address) {\n\t\t\t\t*data = INVM_DWORD_TO_WORD_DATA(invm_dword);\n\t\t\t\tDEBUGOUT2(\"Read INVM Word 0x%02x = %x\",\n\t\t\t\t\t address, *data);\n\t\t\t\tstatus = E1000_SUCCESS;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tif (status != E1000_SUCCESS)\n\t\tDEBUGOUT1(\"Requested word 0x%02x not found in OTP\\n\", address);\n\treturn status;\n}\n\n/** e1000_read_invm_i210 - Read invm wrapper function for I210/I211\n * @hw: pointer to the HW structure\n * @address: the word address (aka eeprom offset) to read\n * @data: pointer to the data read\n *\n * Wrapper function to return data formerly found in the NVM.\n **/\nstatic s32 e1000_read_invm_i210(struct e1000_hw *hw, u16 offset,\n\t\t\t\tu16 E1000_UNUSEDARG words, u16 *data)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_read_invm_i210\");\n\n\t/* Only the MAC addr is required to be present in the iNVM */\n\tswitch (offset) {\n\tcase NVM_MAC_ADDR:\n\t\tret_val = e1000_read_invm_word_i210(hw, (u8)offset, &data[0]);\n\t\tret_val |= e1000_read_invm_word_i210(hw, (u8)offset+1,\n\t\t\t\t\t\t &data[1]);\n\t\tret_val |= e1000_read_invm_word_i210(hw, (u8)offset+2,\n\t\t\t\t\t\t &data[2]);\n\t\tif (ret_val != E1000_SUCCESS)\n\t\t\tDEBUGOUT(\"MAC Addr not found in iNVM\\n\");\n\t\tbreak;\n\tcase NVM_INIT_CTRL_2:\n\t\tret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\t*data = NVM_INIT_CTRL_2_DEFAULT_I211;\n\t\t\tret_val = E1000_SUCCESS;\n\t\t}\n\t\tbreak;\n\tcase NVM_INIT_CTRL_4:\n\t\tret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\t*data = NVM_INIT_CTRL_4_DEFAULT_I211;\n\t\t\tret_val = E1000_SUCCESS;\n\t\t}\n\t\tbreak;\n\tcase NVM_LED_1_CFG:\n\t\tret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\t*data = NVM_LED_1_CFG_DEFAULT_I211;\n\t\t\tret_val = E1000_SUCCESS;\n\t\t}\n\t\tbreak;\n\tcase NVM_LED_0_2_CFG:\n\t\tret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\t*data = NVM_LED_0_2_CFG_DEFAULT_I211;\n\t\t\tret_val = E1000_SUCCESS;\n\t\t}\n\t\tbreak;\n\tcase NVM_ID_LED_SETTINGS:\n\t\tret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\t*data = ID_LED_RESERVED_FFFF;\n\t\t\tret_val = E1000_SUCCESS;\n\t\t}\n\t\tbreak;\n\tcase NVM_SUB_DEV_ID:\n\t\t*data = hw->subsystem_device_id;\n\t\tbreak;\n\tcase NVM_SUB_VEN_ID:\n\t\t*data = hw->subsystem_vendor_id;\n\t\tbreak;\n\tcase NVM_DEV_ID:\n\t\t*data = hw->device_id;\n\t\tbreak;\n\tcase NVM_VEN_ID:\n\t\t*data = hw->vendor_id;\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT1(\"NVM word 0x%02x is not mapped.\\n\", offset);\n\t\t*data = NVM_RESERVED_WORD;\n\t\tbreak;\n\t}\n\treturn ret_val;\n}\n\n/**\n * e1000_read_invm_version - Reads iNVM version and image type\n * @hw: pointer to the HW structure\n * @invm_ver: version structure for the version read\n *\n * Reads iNVM version and image type.\n **/\ns32 e1000_read_invm_version(struct e1000_hw *hw,\n\t\t\t struct e1000_fw_version *invm_ver)\n{\n\tu32 *record = NULL;\n\tu32 *next_record = NULL;\n\tu32 i = 0;\n\tu32 invm_dword = 0;\n\tu32 invm_blocks = E1000_INVM_SIZE - (E1000_INVM_ULT_BYTES_SIZE /\n\t\t\t\t\t E1000_INVM_RECORD_SIZE_IN_BYTES);\n\tu32 buffer[E1000_INVM_SIZE];\n\ts32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;\n\tu16 version = 0;\n\n\tDEBUGFUNC(\"e1000_read_invm_version\");\n\n\t/* Read iNVM memory */\n\tfor (i = 0; i < E1000_INVM_SIZE; i++) {\n\t\tinvm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));\n\t\tbuffer[i] = invm_dword;\n\t}\n\n\t/* Read version number */\n\tfor (i = 1; i < invm_blocks; i++) {\n\t\trecord = &buffer[invm_blocks - i];\n\t\tnext_record = &buffer[invm_blocks - i + 1];\n\n\t\t/* Check if we have first version location used */\n\t\tif ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) {\n\t\t\tversion = 0;\n\t\t\tstatus = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\t/* Check if we have second version location used */\n\t\telse if ((i == 1) &&\n\t\t\t ((*record & E1000_INVM_VER_FIELD_TWO) == 0)) {\n\t\t\tversion = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;\n\t\t\tstatus = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\t/*\n\t\t * Check if we have odd version location\n\t\t * used and it is the last one used\n\t\t */\n\t\telse if ((((*record & E1000_INVM_VER_FIELD_ONE) == 0) &&\n\t\t\t ((*record & 0x3) == 0)) || (((*record & 0x3) != 0) &&\n\t\t\t (i != 1))) {\n\t\t\tversion = (*next_record & E1000_INVM_VER_FIELD_TWO)\n\t\t\t\t >> 13;\n\t\t\tstatus = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\t/*\n\t\t * Check if we have even version location\n\t\t * used and it is the last one used\n\t\t */\n\t\telse if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) &&\n\t\t\t ((*record & 0x3) == 0)) {\n\t\t\tversion = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;\n\t\t\tstatus = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (status == E1000_SUCCESS) {\n\t\tinvm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK)\n\t\t\t\t\t>> E1000_INVM_MAJOR_SHIFT;\n\t\tinvm_ver->invm_minor = version & E1000_INVM_MINOR_MASK;\n\t}\n\t/* Read Image Type */\n\tfor (i = 1; i < invm_blocks; i++) {\n\t\trecord = &buffer[invm_blocks - i];\n\t\tnext_record = &buffer[invm_blocks - i + 1];\n\n\t\t/* Check if we have image type in first location used */\n\t\tif ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) {\n\t\t\tinvm_ver->invm_img_type = 0;\n\t\t\tstatus = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\t/* Check if we have image type in first location used */\n\t\telse if ((((*record & 0x3) == 0) &&\n\t\t\t ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) ||\n\t\t\t ((((*record & 0x3) != 0) && (i != 1)))) {\n\t\t\tinvm_ver->invm_img_type =\n\t\t\t\t(*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23;\n\t\t\tstatus = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn status;\n}\n\n/**\n * e1000_validate_nvm_checksum_i210 - Validate EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Calculates the EEPROM checksum by reading/adding each word of the EEPROM\n * and then verifies that the sum of the EEPROM is equal to 0xBABA.\n **/\ns32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw)\n{\n\ts32 status = E1000_SUCCESS;\n\ts32 (*read_op_ptr)(struct e1000_hw *, u16, u16, u16 *);\n\n\tDEBUGFUNC(\"e1000_validate_nvm_checksum_i210\");\n\n\tif (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {\n\n\t\t/*\n\t\t * Replace the read function with semaphore grabbing with\n\t\t * the one that skips this for a while.\n\t\t * We have semaphore taken already here.\n\t\t */\n\t\tread_op_ptr = hw->nvm.ops.read;\n\t\thw->nvm.ops.read = e1000_read_nvm_eerd;\n\n\t\tstatus = e1000_validate_nvm_checksum_generic(hw);\n\n\t\t/* Revert original read operation. */\n\t\thw->nvm.ops.read = read_op_ptr;\n\n\t\thw->nvm.ops.release(hw);\n\t} else {\n\t\tstatus = E1000_ERR_SWFW_SYNC;\n\t}\n\n\treturn status;\n}\n\n\n/**\n * e1000_update_nvm_checksum_i210 - Update EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Updates the EEPROM checksum by reading/adding each word of the EEPROM\n * up to the checksum. Then calculates the EEPROM checksum and writes the\n * value to the EEPROM. Next commit EEPROM data onto the Flash.\n **/\ns32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 checksum = 0;\n\tu16 i, nvm_data;\n\n\tDEBUGFUNC(\"e1000_update_nvm_checksum_i210\");\n\n\t/*\n\t * Read the first word from the EEPROM. If this times out or fails, do\n\t * not continue or we could be in for a very long wait while every\n\t * EEPROM read fails\n\t */\n\tret_val = e1000_read_nvm_eerd(hw, 0, 1, &nvm_data);\n\tif (ret_val != E1000_SUCCESS) {\n\t\tDEBUGOUT(\"EEPROM read failed\\n\");\n\t\tgoto out;\n\t}\n\n\tif (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {\n\t\t/*\n\t\t * Do not use hw->nvm.ops.write, hw->nvm.ops.read\n\t\t * because we do not want to take the synchronization\n\t\t * semaphores twice here.\n\t\t */\n\n\t\tfor (i = 0; i < NVM_CHECKSUM_REG; i++) {\n\t\t\tret_val = e1000_read_nvm_eerd(hw, i, 1, &nvm_data);\n\t\t\tif (ret_val) {\n\t\t\t\thw->nvm.ops.release(hw);\n\t\t\t\tDEBUGOUT(\"NVM Read Error while updating checksum.\\n\");\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t\tchecksum += nvm_data;\n\t\t}\n\t\tchecksum = (u16) NVM_SUM - checksum;\n\t\tret_val = e1000_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,\n\t\t\t\t\t\t&checksum);\n\t\tif (ret_val != E1000_SUCCESS) {\n\t\t\thw->nvm.ops.release(hw);\n\t\t\tDEBUGOUT(\"NVM Write Error while updating checksum.\\n\");\n\t\t\tgoto out;\n\t\t}\n\n\t\thw->nvm.ops.release(hw);\n\n\t\tret_val = e1000_update_flash_i210(hw);\n\t} else {\n\t\tret_val = E1000_ERR_SWFW_SYNC;\n\t}\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_get_flash_presence_i210 - Check if flash device is detected.\n * @hw: pointer to the HW structure\n *\n **/\nbool e1000_get_flash_presence_i210(struct e1000_hw *hw)\n{\n\tu32 eec = 0;\n\tbool ret_val = false;\n\n\tDEBUGFUNC(\"e1000_get_flash_presence_i210\");\n\n\teec = E1000_READ_REG(hw, E1000_EECD);\n\n\tif (eec & E1000_EECD_FLASH_DETECTED_I210)\n\t\tret_val = true;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_update_flash_i210 - Commit EEPROM to the flash\n * @hw: pointer to the HW structure\n *\n **/\ns32 e1000_update_flash_i210(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 flup;\n\n\tDEBUGFUNC(\"e1000_update_flash_i210\");\n\n\tret_val = e1000_pool_flash_update_done_i210(hw);\n\tif (ret_val == -E1000_ERR_NVM) {\n\t\tDEBUGOUT(\"Flash update time out\\n\");\n\t\tgoto out;\n\t}\n\n\tflup = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD_I210;\n\tE1000_WRITE_REG(hw, E1000_EECD, flup);\n\n\tret_val = e1000_pool_flash_update_done_i210(hw);\n\tif (ret_val == E1000_SUCCESS)\n\t\tDEBUGOUT(\"Flash update complete\\n\");\n\telse\n\t\tDEBUGOUT(\"Flash update time out\\n\");\n\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.\n * @hw: pointer to the HW structure\n *\n **/\ns32 e1000_pool_flash_update_done_i210(struct e1000_hw *hw)\n{\n\ts32 ret_val = -E1000_ERR_NVM;\n\tu32 i, reg;\n\n\tDEBUGFUNC(\"e1000_pool_flash_update_done_i210\");\n\n\tfor (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {\n\t\treg = E1000_READ_REG(hw, E1000_EECD);\n\t\tif (reg & E1000_EECD_FLUDONE_I210) {\n\t\t\tret_val = E1000_SUCCESS;\n\t\t\tbreak;\n\t\t}\n\t\tusec_delay(5);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_init_nvm_params_i210 - Initialize i210 NVM function pointers\n * @hw: pointer to the HW structure\n *\n * Initialize the i210/i211 NVM parameters and function pointers.\n **/\nstatic s32 e1000_init_nvm_params_i210(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\n\tDEBUGFUNC(\"e1000_init_nvm_params_i210\");\n\n\tret_val = e1000_init_nvm_params_82575(hw);\n\tnvm->ops.acquire = e1000_acquire_nvm_i210;\n\tnvm->ops.release = e1000_release_nvm_i210;\n\tnvm->ops.valid_led_default = e1000_valid_led_default_i210;\n\tif (e1000_get_flash_presence_i210(hw)) {\n\t\thw->nvm.type = e1000_nvm_flash_hw;\n\t\tnvm->ops.read = e1000_read_nvm_srrd_i210;\n\t\tnvm->ops.write = e1000_write_nvm_srwr_i210;\n\t\tnvm->ops.validate = e1000_validate_nvm_checksum_i210;\n\t\tnvm->ops.update = e1000_update_nvm_checksum_i210;\n\t} else {\n\t\thw->nvm.type = e1000_nvm_invm;\n\t\tnvm->ops.read = e1000_read_invm_i210;\n\t\tnvm->ops.write = e1000_null_write_nvm;\n\t\tnvm->ops.validate = e1000_null_ops_generic;\n\t\tnvm->ops.update = e1000_null_ops_generic;\n\t}\n\treturn ret_val;\n}\n\n/**\n * e1000_init_function_pointers_i210 - Init func ptrs.\n * @hw: pointer to the HW structure\n *\n * Called to initialize all function pointers and parameters.\n **/\nvoid e1000_init_function_pointers_i210(struct e1000_hw *hw)\n{\n\te1000_init_function_pointers_82575(hw);\n\thw->nvm.ops.init_params = e1000_init_nvm_params_i210;\n\n\treturn;\n}\n\n/**\n * e1000_valid_led_default_i210 - Verify a valid default LED config\n * @hw: pointer to the HW structure\n * @data: pointer to the NVM (EEPROM)\n *\n * Read the EEPROM for the current default LED configuration. If the\n * LED configuration is not valid, set to a valid LED configuration.\n **/\nstatic s32 e1000_valid_led_default_i210(struct e1000_hw *hw, u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_valid_led_default_i210\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\tgoto out;\n\t}\n\n\tif (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {\n\t\tswitch (hw->phy.media_type) {\n\t\tcase e1000_media_type_internal_serdes:\n\t\t\t*data = ID_LED_DEFAULT_I210_SERDES;\n\t\t\tbreak;\n\t\tcase e1000_media_type_copper:\n\t\tdefault:\n\t\t\t*data = ID_LED_DEFAULT_I210;\n\t\t\tbreak;\n\t\t}\n\t}\nout:\n\treturn ret_val;\n}\n\n/**\n * __e1000_access_xmdio_reg - Read/write XMDIO register\n * @hw: pointer to the HW structure\n * @address: XMDIO address to program\n * @dev_addr: device address to program\n * @data: pointer to value to read/write from/to the XMDIO address\n * @read: boolean flag to indicate read or write\n **/\nstatic s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,\n\t\t\t\t u8 dev_addr, u16 *data, bool read)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"__e1000_access_xmdio_reg\");\n\n\tret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |\n\t\t\t\t\t\t\t dev_addr);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (read)\n\t\tret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);\n\telse\n\t\tret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Recalibrate the device back to 0 */\n\tret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_xmdio_reg - Read XMDIO register\n * @hw: pointer to the HW structure\n * @addr: XMDIO address to program\n * @dev_addr: device address to program\n * @data: value to be read from the EMI address\n **/\ns32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)\n{\n\tDEBUGFUNC(\"e1000_read_xmdio_reg\");\n\n\treturn __e1000_access_xmdio_reg(hw, addr, dev_addr, data, true);\n}\n\n/**\n * e1000_write_xmdio_reg - Write XMDIO register\n * @hw: pointer to the HW structure\n * @addr: XMDIO address to program\n * @dev_addr: device address to program\n * @data: value to be written to the XMDIO address\n **/\ns32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)\n{\n\tDEBUGFUNC(\"e1000_read_xmdio_reg\");\n\n\treturn __e1000_access_xmdio_reg(hw, addr, dev_addr, &data, false);\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_i210.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _E1000_I210_H_\n#define _E1000_I210_H_\n\nbool e1000_get_flash_presence_i210(struct e1000_hw *hw);\ns32 e1000_update_flash_i210(struct e1000_hw *hw);\ns32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw);\ns32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw);\ns32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset,\n\t\t\t u16 words, u16 *data);\ns32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset,\n\t\t\t u16 words, u16 *data);\ns32 e1000_read_invm_version(struct e1000_hw *hw,\n\t\t\t struct e1000_fw_version *invm_ver);\ns32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);\nvoid e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);\ns32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,\n\t\t\t u16 *data);\ns32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,\n\t\t\t u16 data);\n\n#define E1000_STM_OPCODE\t\t0xDB00\n#define E1000_EEPROM_FLASH_SIZE_WORD\t0x11\n\n#define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \\\n\t(u8)((invm_dword) & 0x7)\n#define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \\\n\t(u8)(((invm_dword) & 0x0000FE00) >> 9)\n#define INVM_DWORD_TO_WORD_DATA(invm_dword) \\\n\t(u16)(((invm_dword) & 0xFFFF0000) >> 16)\n\nenum E1000_INVM_STRUCTURE_TYPE {\n\tE1000_INVM_UNINITIALIZED_STRUCTURE\t\t= 0x00,\n\tE1000_INVM_WORD_AUTOLOAD_STRUCTURE\t\t= 0x01,\n\tE1000_INVM_CSR_AUTOLOAD_STRUCTURE\t\t= 0x02,\n\tE1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE\t= 0x03,\n\tE1000_INVM_RSA_KEY_SHA256_STRUCTURE\t\t= 0x04,\n\tE1000_INVM_INVALIDATED_STRUCTURE\t\t= 0x0F,\n};\n\n#define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS\t8\n#define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS\t1\n#define E1000_INVM_ULT_BYTES_SIZE\t8\n#define E1000_INVM_RECORD_SIZE_IN_BYTES\t4\n#define E1000_INVM_VER_FIELD_ONE\t0x1FF8\n#define E1000_INVM_VER_FIELD_TWO\t0x7FE000\n#define E1000_INVM_IMGTYPE_FIELD\t0x1F800000\n\n#define E1000_INVM_MAJOR_MASK\t0x3F0\n#define E1000_INVM_MINOR_MASK\t0xF\n#define E1000_INVM_MAJOR_SHIFT\t4\n\n#define ID_LED_DEFAULT_I210\t\t((ID_LED_OFF1_ON2 << 8) | \\\n\t\t\t\t\t (ID_LED_DEF1_DEF2 << 4) | \\\n\t\t\t\t\t (ID_LED_OFF1_OFF2))\n#define ID_LED_DEFAULT_I210_SERDES\t((ID_LED_DEF1_DEF2 << 8) | \\\n\t\t\t\t\t (ID_LED_DEF1_DEF2 << 4) | \\\n\t\t\t\t\t (ID_LED_OFF1_ON2))\n\n/* NVM offset defaults for I211 devices */\n#define NVM_INIT_CTRL_2_DEFAULT_I211\t0X7243\n#define NVM_INIT_CTRL_4_DEFAULT_I211\t0x00C1\n#define NVM_LED_1_CFG_DEFAULT_I211\t0x0184\n#define NVM_LED_0_2_CFG_DEFAULT_I211\t0x200C\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_mac.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"e1000_api.h\"\n\nstatic s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);\nstatic void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);\nstatic void e1000_config_collision_dist_generic(struct e1000_hw *hw);\nstatic void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);\n\n/**\n * e1000_init_mac_ops_generic - Initialize MAC function pointers\n * @hw: pointer to the HW structure\n *\n * Setups up the function pointers to no-op functions\n **/\nvoid e1000_init_mac_ops_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tDEBUGFUNC(\"e1000_init_mac_ops_generic\");\n\n\t/* General Setup */\n\tmac->ops.init_params = e1000_null_ops_generic;\n\tmac->ops.init_hw = e1000_null_ops_generic;\n\tmac->ops.reset_hw = e1000_null_ops_generic;\n\tmac->ops.setup_physical_interface = e1000_null_ops_generic;\n\tmac->ops.get_bus_info = e1000_null_ops_generic;\n\tmac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;\n\tmac->ops.read_mac_addr = e1000_read_mac_addr_generic;\n\tmac->ops.config_collision_dist = e1000_config_collision_dist_generic;\n\tmac->ops.clear_hw_cntrs = e1000_null_mac_generic;\n\t/* LED */\n\tmac->ops.cleanup_led = e1000_null_ops_generic;\n\tmac->ops.setup_led = e1000_null_ops_generic;\n\tmac->ops.blink_led = e1000_null_ops_generic;\n\tmac->ops.led_on = e1000_null_ops_generic;\n\tmac->ops.led_off = e1000_null_ops_generic;\n\t/* LINK */\n\tmac->ops.setup_link = e1000_null_ops_generic;\n\tmac->ops.get_link_up_info = e1000_null_link_info;\n\tmac->ops.check_for_link = e1000_null_ops_generic;\n\t/* Management */\n\tmac->ops.check_mng_mode = e1000_null_mng_mode;\n\t/* VLAN, MC, etc. */\n\tmac->ops.update_mc_addr_list = e1000_null_update_mc;\n\tmac->ops.clear_vfta = e1000_null_mac_generic;\n\tmac->ops.write_vfta = e1000_null_write_vfta;\n\tmac->ops.rar_set = e1000_rar_set_generic;\n\tmac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;\n}\n\n/**\n * e1000_null_ops_generic - No-op function, returns 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_ops_generic(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_null_ops_generic\");\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_mac_generic - No-op function, return void\n * @hw: pointer to the HW structure\n **/\nvoid e1000_null_mac_generic(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_null_mac_generic\");\n\treturn;\n}\n\n/**\n * e1000_null_link_info - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_link_info(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u16 E1000_UNUSEDARG *s, u16 E1000_UNUSEDARG *d)\n{\n\tDEBUGFUNC(\"e1000_null_link_info\");\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_mng_mode - No-op function, return false\n * @hw: pointer to the HW structure\n **/\nbool e1000_null_mng_mode(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_null_mng_mode\");\n\treturn false;\n}\n\n/**\n * e1000_null_update_mc - No-op function, return void\n * @hw: pointer to the HW structure\n **/\nvoid e1000_null_update_mc(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)\n{\n\tDEBUGFUNC(\"e1000_null_update_mc\");\n\treturn;\n}\n\n/**\n * e1000_null_write_vfta - No-op function, return void\n * @hw: pointer to the HW structure\n **/\nvoid e1000_null_write_vfta(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u32 E1000_UNUSEDARG a, u32 E1000_UNUSEDARG b)\n{\n\tDEBUGFUNC(\"e1000_null_write_vfta\");\n\treturn;\n}\n\n/**\n * e1000_null_rar_set - No-op function, return void\n * @hw: pointer to the HW structure\n **/\nvoid e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\tu8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)\n{\n\tDEBUGFUNC(\"e1000_null_rar_set\");\n\treturn;\n}\n\n/**\n * e1000_get_bus_info_pcie_generic - Get PCIe bus information\n * @hw: pointer to the HW structure\n *\n * Determines and stores the system bus information for a particular\n * network interface. The following bus information is determined and stored:\n * bus speed, bus width, type (PCIe), and PCIe function.\n **/\ns32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tstruct e1000_bus_info *bus = &hw->bus;\n\ts32 ret_val;\n\tu16 pcie_link_status;\n\n\tDEBUGFUNC(\"e1000_get_bus_info_pcie_generic\");\n\n\tbus->type = e1000_bus_type_pci_express;\n\n\tret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,\n\t\t\t\t\t &pcie_link_status);\n\tif (ret_val) {\n\t\tbus->width = e1000_bus_width_unknown;\n\t\tbus->speed = e1000_bus_speed_unknown;\n\t} else {\n\t\tswitch (pcie_link_status & PCIE_LINK_SPEED_MASK) {\n\t\tcase PCIE_LINK_SPEED_2500:\n\t\t\tbus->speed = e1000_bus_speed_2500;\n\t\t\tbreak;\n\t\tcase PCIE_LINK_SPEED_5000:\n\t\t\tbus->speed = e1000_bus_speed_5000;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbus->speed = e1000_bus_speed_unknown;\n\t\t\tbreak;\n\t\t}\n\n\t\tbus->width = (enum e1000_bus_width)((pcie_link_status &\n\t\t\t PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);\n\t}\n\n\tmac->ops.set_lan_id(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices\n *\n * @hw: pointer to the HW structure\n *\n * Determines the LAN function id by reading memory-mapped registers\n * and swaps the port value if requested.\n **/\nstatic void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)\n{\n\tstruct e1000_bus_info *bus = &hw->bus;\n\tu32 reg;\n\n\t/* The status register reports the correct function number\n\t * for the device regardless of function swap state.\n\t */\n\treg = E1000_READ_REG(hw, E1000_STATUS);\n\tbus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;\n}\n\n/**\n * e1000_set_lan_id_single_port - Set LAN id for a single port device\n * @hw: pointer to the HW structure\n *\n * Sets the LAN function id to zero for a single port device.\n **/\nvoid e1000_set_lan_id_single_port(struct e1000_hw *hw)\n{\n\tstruct e1000_bus_info *bus = &hw->bus;\n\n\tbus->func = 0;\n}\n\n/**\n * e1000_clear_vfta_generic - Clear VLAN filter table\n * @hw: pointer to the HW structure\n *\n * Clears the register array which contains the VLAN filter table by\n * setting all the values to 0.\n **/\nvoid e1000_clear_vfta_generic(struct e1000_hw *hw)\n{\n\tu32 offset;\n\n\tDEBUGFUNC(\"e1000_clear_vfta_generic\");\n\n\tfor (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);\n\t\tE1000_WRITE_FLUSH(hw);\n\t}\n}\n\n/**\n * e1000_write_vfta_generic - Write value to VLAN filter table\n * @hw: pointer to the HW structure\n * @offset: register offset in VLAN filter table\n * @value: register value written to VLAN filter table\n *\n * Writes value at the given offset in the register array which stores\n * the VLAN filter table.\n **/\nvoid e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)\n{\n\tDEBUGFUNC(\"e1000_write_vfta_generic\");\n\n\tE1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * e1000_init_rx_addrs_generic - Initialize receive address's\n * @hw: pointer to the HW structure\n * @rar_count: receive address registers\n *\n * Setup the receive address registers by setting the base receive address\n * register to the devices MAC address and clearing all the other receive\n * address registers to 0.\n **/\nvoid e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)\n{\n\tu32 i;\n\tu8 mac_addr[ETH_ADDR_LEN] = {0};\n\n\tDEBUGFUNC(\"e1000_init_rx_addrs_generic\");\n\n\t/* Setup the receive address */\n\tDEBUGOUT(\"Programming MAC Address into RAR[0]\\n\");\n\n\thw->mac.ops.rar_set(hw, hw->mac.addr, 0);\n\n\t/* Zero out the other (rar_entry_count - 1) receive addresses */\n\tDEBUGOUT1(\"Clearing RAR[1-%u]\\n\", rar_count-1);\n\tfor (i = 1; i < rar_count; i++)\n\t\thw->mac.ops.rar_set(hw, mac_addr, i);\n}\n\n/**\n * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr\n * @hw: pointer to the HW structure\n *\n * Checks the nvm for an alternate MAC address. An alternate MAC address\n * can be setup by pre-boot software and must be treated like a permanent\n * address and must override the actual permanent MAC address. If an\n * alternate MAC address is found it is programmed into RAR0, replacing\n * the permanent address that was installed into RAR0 by the Si on reset.\n * This function will return SUCCESS unless it encounters an error while\n * reading the EEPROM.\n **/\ns32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)\n{\n\tu32 i;\n\ts32 ret_val;\n\tu16 offset, nvm_alt_mac_addr_offset, nvm_data;\n\tu8 alt_mac_addr[ETH_ADDR_LEN];\n\n\tDEBUGFUNC(\"e1000_check_alt_mac_addr_generic\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\n\t/* Alternate MAC address is handled by the option ROM for 82580\n\t * and newer. SW support not required.\n\t */\n\tif (hw->mac.type >= e1000_82580)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,\n\t\t\t\t &nvm_alt_mac_addr_offset);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif ((nvm_alt_mac_addr_offset == 0xFFFF) ||\n\t (nvm_alt_mac_addr_offset == 0x0000))\n\t\t/* There is no Alternate MAC Address */\n\t\treturn E1000_SUCCESS;\n\n\tif (hw->bus.func == E1000_FUNC_1)\n\t\tnvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;\n\tif (hw->bus.func == E1000_FUNC_2)\n\t\tnvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;\n\n\tif (hw->bus.func == E1000_FUNC_3)\n\t\tnvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;\n\tfor (i = 0; i < ETH_ADDR_LEN; i += 2) {\n\t\toffset = nvm_alt_mac_addr_offset + (i >> 1);\n\t\tret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\n\t\talt_mac_addr[i] = (u8)(nvm_data & 0xFF);\n\t\talt_mac_addr[i + 1] = (u8)(nvm_data >> 8);\n\t}\n\n\t/* if multicast bit is set, the alternate address will not be used */\n\tif (alt_mac_addr[0] & 0x01) {\n\t\tDEBUGOUT(\"Ignoring Alternate Mac Address with MC bit set\\n\");\n\t\treturn E1000_SUCCESS;\n\t}\n\n\t/* We have a valid alternate MAC address, and we want to treat it the\n\t * same as the normal permanent MAC address stored by the HW into the\n\t * RAR. Do this by mapping this address into RAR0.\n\t */\n\thw->mac.ops.rar_set(hw, alt_mac_addr, 0);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_rar_set_generic - Set receive address register\n * @hw: pointer to the HW structure\n * @addr: pointer to the receive address\n * @index: receive address array register\n *\n * Sets the receive address array register at index to the address passed\n * in by addr.\n **/\nstatic void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)\n{\n\tu32 rar_low, rar_high;\n\n\tDEBUGFUNC(\"e1000_rar_set_generic\");\n\n\t/* HW expects these in little endian so we reverse the byte order\n\t * from network order (big endian) to little endian\n\t */\n\trar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |\n\t\t ((u32) addr[2] << 16) | ((u32) addr[3] << 24));\n\n\trar_high = ((u32) addr[4] | ((u32) addr[5] << 8));\n\n\t/* If MAC address zero, no need to set the AV bit */\n\tif (rar_low || rar_high)\n\t\trar_high |= E1000_RAH_AV;\n\n\t/* Some bridges will combine consecutive 32-bit writes into\n\t * a single burst write, which will malfunction on some parts.\n\t * The flushes avoid this.\n\t */\n\tE1000_WRITE_REG(hw, E1000_RAL(index), rar_low);\n\tE1000_WRITE_FLUSH(hw);\n\tE1000_WRITE_REG(hw, E1000_RAH(index), rar_high);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * e1000_hash_mc_addr_generic - Generate a multicast hash value\n * @hw: pointer to the HW structure\n * @mc_addr: pointer to a multicast address\n *\n * Generates a multicast address hash value which is used to determine\n * the multicast filter table array address and new table value.\n **/\nu32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)\n{\n\tu32 hash_value, hash_mask;\n\tu8 bit_shift = 0;\n\n\tDEBUGFUNC(\"e1000_hash_mc_addr_generic\");\n\n\t/* Register count multiplied by bits per register */\n\thash_mask = (hw->mac.mta_reg_count * 32) - 1;\n\n\t/* For a mc_filter_type of 0, bit_shift is the number of left-shifts\n\t * where 0xFF would still fall within the hash mask.\n\t */\n\twhile (hash_mask >> bit_shift != 0xFF)\n\t\tbit_shift++;\n\n\t/* The portion of the address that is used for the hash table\n\t * is determined by the mc_filter_type setting.\n\t * The algorithm is such that there is a total of 8 bits of shifting.\n\t * The bit_shift for a mc_filter_type of 0 represents the number of\n\t * left-shifts where the MSB of mc_addr[5] would still fall within\n\t * the hash_mask. Case 0 does this exactly. Since there are a total\n\t * of 8 bits of shifting, then mc_addr[4] will shift right the\n\t * remaining number of bits. Thus 8 - bit_shift. The rest of the\n\t * cases are a variation of this algorithm...essentially raising the\n\t * number of bits to shift mc_addr[5] left, while still keeping the\n\t * 8-bit shifting total.\n\t *\n\t * For example, given the following Destination MAC Address and an\n\t * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),\n\t * we can see that the bit_shift for case 0 is 4. These are the hash\n\t * values resulting from each mc_filter_type...\n\t * [0] [1] [2] [3] [4] [5]\n\t * 01 AA 00 12 34 56\n\t * LSB\t\t MSB\n\t *\n\t * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563\n\t * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6\n\t * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163\n\t * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634\n\t */\n\tswitch (hw->mac.mc_filter_type) {\n\tdefault:\n\tcase 0:\n\t\tbreak;\n\tcase 1:\n\t\tbit_shift += 1;\n\t\tbreak;\n\tcase 2:\n\t\tbit_shift += 2;\n\t\tbreak;\n\tcase 3:\n\t\tbit_shift += 4;\n\t\tbreak;\n\t}\n\n\thash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |\n\t\t\t\t (((u16) mc_addr[5]) << bit_shift)));\n\n\treturn hash_value;\n}\n\n/**\n * e1000_update_mc_addr_list_generic - Update Multicast addresses\n * @hw: pointer to the HW structure\n * @mc_addr_list: array of multicast addresses to program\n * @mc_addr_count: number of multicast addresses to program\n *\n * Updates entire Multicast Table Array.\n * The caller must have a packed mc_addr_list of multicast addresses.\n **/\nvoid e1000_update_mc_addr_list_generic(struct e1000_hw *hw,\n\t\t\t\t u8 *mc_addr_list, u32 mc_addr_count)\n{\n\tu32 hash_value, hash_bit, hash_reg;\n\tint i;\n\n\tDEBUGFUNC(\"e1000_update_mc_addr_list_generic\");\n\n\t/* clear mta_shadow */\n\tmemset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));\n\n\t/* update mta_shadow from mc_addr_list */\n\tfor (i = 0; (u32) i < mc_addr_count; i++) {\n\t\thash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);\n\n\t\thash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);\n\t\thash_bit = hash_value & 0x1F;\n\n\t\thw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);\n\t\tmc_addr_list += (ETH_ADDR_LEN);\n\t}\n\n\t/* replace the entire MTA table */\n\tfor (i = hw->mac.mta_reg_count - 1; i >= 0; i--)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters\n * @hw: pointer to the HW structure\n *\n * Clears the base hardware counters by reading the counter registers.\n **/\nvoid e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_clear_hw_cntrs_base_generic\");\n\n\tE1000_READ_REG(hw, E1000_CRCERRS);\n\tE1000_READ_REG(hw, E1000_SYMERRS);\n\tE1000_READ_REG(hw, E1000_MPC);\n\tE1000_READ_REG(hw, E1000_SCC);\n\tE1000_READ_REG(hw, E1000_ECOL);\n\tE1000_READ_REG(hw, E1000_MCC);\n\tE1000_READ_REG(hw, E1000_LATECOL);\n\tE1000_READ_REG(hw, E1000_COLC);\n\tE1000_READ_REG(hw, E1000_DC);\n\tE1000_READ_REG(hw, E1000_SEC);\n\tE1000_READ_REG(hw, E1000_RLEC);\n\tE1000_READ_REG(hw, E1000_XONRXC);\n\tE1000_READ_REG(hw, E1000_XONTXC);\n\tE1000_READ_REG(hw, E1000_XOFFRXC);\n\tE1000_READ_REG(hw, E1000_XOFFTXC);\n\tE1000_READ_REG(hw, E1000_FCRUC);\n\tE1000_READ_REG(hw, E1000_GPRC);\n\tE1000_READ_REG(hw, E1000_BPRC);\n\tE1000_READ_REG(hw, E1000_MPRC);\n\tE1000_READ_REG(hw, E1000_GPTC);\n\tE1000_READ_REG(hw, E1000_GORCL);\n\tE1000_READ_REG(hw, E1000_GORCH);\n\tE1000_READ_REG(hw, E1000_GOTCL);\n\tE1000_READ_REG(hw, E1000_GOTCH);\n\tE1000_READ_REG(hw, E1000_RNBC);\n\tE1000_READ_REG(hw, E1000_RUC);\n\tE1000_READ_REG(hw, E1000_RFC);\n\tE1000_READ_REG(hw, E1000_ROC);\n\tE1000_READ_REG(hw, E1000_RJC);\n\tE1000_READ_REG(hw, E1000_TORL);\n\tE1000_READ_REG(hw, E1000_TORH);\n\tE1000_READ_REG(hw, E1000_TOTL);\n\tE1000_READ_REG(hw, E1000_TOTH);\n\tE1000_READ_REG(hw, E1000_TPR);\n\tE1000_READ_REG(hw, E1000_TPT);\n\tE1000_READ_REG(hw, E1000_MPTC);\n\tE1000_READ_REG(hw, E1000_BPTC);\n}\n\n/**\n * e1000_check_for_copper_link_generic - Check for link (Copper)\n * @hw: pointer to the HW structure\n *\n * Checks to see of the link status of the hardware has changed. If a\n * change in link status has been detected, then we read the PHY registers\n * to get the current speed/duplex if link exists.\n **/\ns32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_check_for_copper_link\");\n\n\t/* We only want to go out to the PHY registers to see if Auto-Neg\n\t * has completed and/or if our link status has changed. The\n\t * get_link_status flag is set upon receiving a Link Status\n\t * Change or Rx Sequence Error interrupt.\n\t */\n\tif (!mac->get_link_status)\n\t\treturn E1000_SUCCESS;\n\n\t/* First we want to see if the MII Status Register reports\n\t * link. If so, then we want to get the current speed/duplex\n\t * of the PHY.\n\t */\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!link)\n\t\treturn E1000_SUCCESS; /* No link detected */\n\n\tmac->get_link_status = false;\n\n\t/* Check if there was DownShift, must be checked\n\t * immediately after link-up\n\t */\n\te1000_check_downshift_generic(hw);\n\n\t/* If we are forcing speed/duplex, then we simply return since\n\t * we have already determined whether we have link or not.\n\t */\n\tif (!mac->autoneg)\n\t\treturn -E1000_ERR_CONFIG;\n\n\t/* Auto-Neg is enabled. Auto Speed Detection takes care\n\t * of MAC speed/duplex configuration. So we only need to\n\t * configure Collision Distance in the MAC.\n\t */\n\tmac->ops.config_collision_dist(hw);\n\n\t/* Configure Flow Control now that Auto-Neg has completed.\n\t * First, we need to restore the desired flow control\n\t * settings because we may have had to re-autoneg with a\n\t * different link partner.\n\t */\n\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\tif (ret_val)\n\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_fiber_link_generic - Check for link (Fiber)\n * @hw: pointer to the HW structure\n *\n * Checks for link up on the hardware. If link is not up and we have\n * a signal, then we need to force link up.\n **/\ns32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 rxcw;\n\tu32 ctrl;\n\tu32 status;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_check_for_fiber_link_generic\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\trxcw = E1000_READ_REG(hw, E1000_RXCW);\n\n\t/* If we don't have link (auto-negotiation failed or link partner\n\t * cannot auto-negotiate), the cable is plugged in (we have signal),\n\t * and our link partner is not trying to auto-negotiate with us (we\n\t * are receiving idles or data), we need to force link up. We also\n\t * need to give auto-negotiation time to complete, in case the cable\n\t * was just plugged in. The autoneg_failed flag does this.\n\t */\n\t/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */\n\tif ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) &&\n\t !(rxcw & E1000_RXCW_C)) {\n\t\tif (!mac->autoneg_failed) {\n\t\t\tmac->autoneg_failed = true;\n\t\t\treturn E1000_SUCCESS;\n\t\t}\n\t\tDEBUGOUT(\"NOT Rx'ing /C/, disable AutoNeg and force link.\\n\");\n\n\t\t/* Disable auto-negotiation in the TXCW register */\n\t\tE1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));\n\n\t\t/* Force link-up and also force full-duplex. */\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\t\t/* Configure Flow Control after forcing link up. */\n\t\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {\n\t\t/* If we are forcing link and we are receiving /C/ ordered\n\t\t * sets, re-enable auto-negotiation in the TXCW register\n\t\t * and disable forced link in the Device Control register\n\t\t * in an attempt to auto-negotiate with our link partner.\n\t\t */\n\t\tDEBUGOUT(\"Rx'ing /C/, enable AutoNeg and stop forcing link.\\n\");\n\t\tE1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));\n\n\t\tmac->serdes_has_link = true;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_check_for_serdes_link_generic - Check for link (Serdes)\n * @hw: pointer to the HW structure\n *\n * Checks for link up on the hardware. If link is not up and we have\n * a signal, then we need to force link up.\n **/\ns32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 rxcw;\n\tu32 ctrl;\n\tu32 status;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_check_for_serdes_link_generic\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\trxcw = E1000_READ_REG(hw, E1000_RXCW);\n\n\t/* If we don't have link (auto-negotiation failed or link partner\n\t * cannot auto-negotiate), and our link partner is not trying to\n\t * auto-negotiate with us (we are receiving idles or data),\n\t * we need to force link up. We also need to give auto-negotiation\n\t * time to complete.\n\t */\n\t/* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */\n\tif (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) {\n\t\tif (!mac->autoneg_failed) {\n\t\t\tmac->autoneg_failed = true;\n\t\t\treturn E1000_SUCCESS;\n\t\t}\n\t\tDEBUGOUT(\"NOT Rx'ing /C/, disable AutoNeg and force link.\\n\");\n\n\t\t/* Disable auto-negotiation in the TXCW register */\n\t\tE1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));\n\n\t\t/* Force link-up and also force full-duplex. */\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\t\t/* Configure Flow Control after forcing link up. */\n\t\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error configuring flow control\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t} else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {\n\t\t/* If we are forcing link and we are receiving /C/ ordered\n\t\t * sets, re-enable auto-negotiation in the TXCW register\n\t\t * and disable forced link in the Device Control register\n\t\t * in an attempt to auto-negotiate with our link partner.\n\t\t */\n\t\tDEBUGOUT(\"Rx'ing /C/, enable AutoNeg and stop forcing link.\\n\");\n\t\tE1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));\n\n\t\tmac->serdes_has_link = true;\n\t} else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {\n\t\t/* If we force link for non-auto-negotiation switch, check\n\t\t * link status based on MAC synchronization for internal\n\t\t * serdes media type.\n\t\t */\n\t\t/* SYNCH bit and IV bit are sticky. */\n\t\tusec_delay(10);\n\t\trxcw = E1000_READ_REG(hw, E1000_RXCW);\n\t\tif (rxcw & E1000_RXCW_SYNCH) {\n\t\t\tif (!(rxcw & E1000_RXCW_IV)) {\n\t\t\t\tmac->serdes_has_link = true;\n\t\t\t\tDEBUGOUT(\"SERDES: Link up - forced.\\n\");\n\t\t\t}\n\t\t} else {\n\t\t\tmac->serdes_has_link = false;\n\t\t\tDEBUGOUT(\"SERDES: Link down - force failed.\\n\");\n\t\t}\n\t}\n\n\tif (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {\n\t\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\t\tif (status & E1000_STATUS_LU) {\n\t\t\t/* SYNCH bit and IV bit are sticky, so reread rxcw. */\n\t\t\tusec_delay(10);\n\t\t\trxcw = E1000_READ_REG(hw, E1000_RXCW);\n\t\t\tif (rxcw & E1000_RXCW_SYNCH) {\n\t\t\t\tif (!(rxcw & E1000_RXCW_IV)) {\n\t\t\t\t\tmac->serdes_has_link = true;\n\t\t\t\t\tDEBUGOUT(\"SERDES: Link up - autoneg completed successfully.\\n\");\n\t\t\t\t} else {\n\t\t\t\t\tmac->serdes_has_link = false;\n\t\t\t\t\tDEBUGOUT(\"SERDES: Link down - invalid codewords detected in autoneg.\\n\");\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tmac->serdes_has_link = false;\n\t\t\t\tDEBUGOUT(\"SERDES: Link down - no sync.\\n\");\n\t\t\t}\n\t\t} else {\n\t\t\tmac->serdes_has_link = false;\n\t\t\tDEBUGOUT(\"SERDES: Link down - autoneg failed\\n\");\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_default_fc_generic - Set flow control default values\n * @hw: pointer to the HW structure\n *\n * Read the EEPROM for the default values for flow control and store the\n * values.\n **/\nstatic s32 e1000_set_default_fc_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 nvm_data;\n\n\tDEBUGFUNC(\"e1000_set_default_fc_generic\");\n\n\t/* Read and store word 0x0F of the EEPROM. This word contains bits\n\t * that determine the hardware's default PAUSE (flow control) mode,\n\t * a bit that determines whether the HW defaults to enabling or\n\t * disabling auto-negotiation, and the direction of the\n\t * SW defined pins. If there is no SW over-ride of the flow\n\t * control setting, then the variable hw->fc will\n\t * be initialized based on a value in the EEPROM.\n\t */\n\tret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);\n\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif (!(nvm_data & NVM_WORD0F_PAUSE_MASK))\n\t\thw->fc.requested_mode = e1000_fc_none;\n\telse if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==\n\t\t NVM_WORD0F_ASM_DIR)\n\t\thw->fc.requested_mode = e1000_fc_tx_pause;\n\telse\n\t\thw->fc.requested_mode = e1000_fc_full;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_setup_link_generic - Setup flow control and link settings\n * @hw: pointer to the HW structure\n *\n * Determines which flow control settings to use, then configures flow\n * control. Calls the appropriate media-specific link configuration\n * function. Assuming the adapter has a valid link partner, a valid link\n * should be established. Assumes the hardware has previously been reset\n * and the transmitter and receiver are not enabled.\n **/\ns32 e1000_setup_link_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_setup_link_generic\");\n\n\t/* In the case of the phy reset being blocked, we already have a link.\n\t * We do not need to set it up again.\n\t */\n\tif (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))\n\t\treturn E1000_SUCCESS;\n\n\t/* If requested flow control is set to default, set flow control\n\t * based on the EEPROM flow control settings.\n\t */\n\tif (hw->fc.requested_mode == e1000_fc_default) {\n\t\tret_val = e1000_set_default_fc_generic(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* Save off the requested flow control mode for use later. Depending\n\t * on the link partner's capabilities, we may or may not use this mode.\n\t */\n\thw->fc.current_mode = hw->fc.requested_mode;\n\n\tDEBUGOUT1(\"After fix-ups FlowControl is now = %x\\n\",\n\t\thw->fc.current_mode);\n\n\t/* Call the necessary media_type subroutine to configure the link. */\n\tret_val = hw->mac.ops.setup_physical_interface(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Initialize the flow control address, type, and PAUSE timer\n\t * registers to their default values. This is done even if flow\n\t * control is disabled, because it does not hurt anything to\n\t * initialize these registers.\n\t */\n\tDEBUGOUT(\"Initializing the Flow Control address, type and timer regs\\n\");\n\tE1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);\n\tE1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);\n\tE1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);\n\n\tE1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);\n\n\treturn e1000_set_fc_watermarks_generic(hw);\n}\n\n/**\n * e1000_commit_fc_settings_generic - Configure flow control\n * @hw: pointer to the HW structure\n *\n * Write the flow control settings to the Transmit Config Word Register (TXCW)\n * base on the flow control settings in e1000_mac_info.\n **/\nstatic s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 txcw;\n\n\tDEBUGFUNC(\"e1000_commit_fc_settings_generic\");\n\n\t/* Check for a software override of the flow control settings, and\n\t * setup the device accordingly. If auto-negotiation is enabled, then\n\t * software will have to set the \"PAUSE\" bits to the correct value in\n\t * the Transmit Config Word Register (TXCW) and re-start auto-\n\t * negotiation. However, if auto-negotiation is disabled, then\n\t * software will have to manually configure the two flow control enable\n\t * bits in the CTRL register.\n\t *\n\t * The possible values of the \"fc\" parameter are:\n\t * 0: Flow control is completely disabled\n\t * 1: Rx flow control is enabled (we can receive pause frames,\n\t * but not send pause frames).\n\t * 2: Tx flow control is enabled (we can send pause frames but we\n\t * do not support receiving pause frames).\n\t * 3: Both Rx and Tx flow control (symmetric) are enabled.\n\t */\n\tswitch (hw->fc.current_mode) {\n\tcase e1000_fc_none:\n\t\t/* Flow control completely disabled by a software over-ride. */\n\t\ttxcw = (E1000_TXCW_ANE | E1000_TXCW_FD);\n\t\tbreak;\n\tcase e1000_fc_rx_pause:\n\t\t/* Rx Flow control is enabled and Tx Flow control is disabled\n\t\t * by a software over-ride. Since there really isn't a way to\n\t\t * advertise that we are capable of Rx Pause ONLY, we will\n\t\t * advertise that we support both symmetric and asymmetric Rx\n\t\t * PAUSE. Later, we will disable the adapter's ability to send\n\t\t * PAUSE frames.\n\t\t */\n\t\ttxcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);\n\t\tbreak;\n\tcase e1000_fc_tx_pause:\n\t\t/* Tx Flow control is enabled, and Rx Flow control is disabled,\n\t\t * by a software over-ride.\n\t\t */\n\t\ttxcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);\n\t\tbreak;\n\tcase e1000_fc_full:\n\t\t/* Flow control (both Rx and Tx) is enabled by a software\n\t\t * over-ride.\n\t\t */\n\t\ttxcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\"Flow control param set incorrectly\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t\tbreak;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_TXCW, txcw);\n\tmac->txcw = txcw;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_poll_fiber_serdes_link_generic - Poll for link up\n * @hw: pointer to the HW structure\n *\n * Polls for link up by reading the status register, if link fails to come\n * up with auto-negotiation, then the link is forced if a signal is detected.\n **/\nstatic s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 i, status;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_poll_fiber_serdes_link_generic\");\n\n\t/* If we have a signal (the cable is plugged in, or assumed true for\n\t * serdes media) then poll for a \"Link-Up\" indication in the Device\n\t * Status Register. Time-out if a link isn't seen in 500 milliseconds\n\t * seconds (Auto-negotiation should complete in less than 500\n\t * milliseconds even if the other end is doing it in SW).\n\t */\n\tfor (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {\n\t\tmsec_delay(10);\n\t\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\t\tif (status & E1000_STATUS_LU)\n\t\t\tbreak;\n\t}\n\tif (i == FIBER_LINK_UP_LIMIT) {\n\t\tDEBUGOUT(\"Never got a valid link from auto-neg!!!\\n\");\n\t\tmac->autoneg_failed = true;\n\t\t/* AutoNeg failed to achieve a link, so we'll call\n\t\t * mac->check_for_link. This routine will force the\n\t\t * link up if we detect a signal. This will allow us to\n\t\t * communicate with non-autonegotiating link partners.\n\t\t */\n\t\tret_val = mac->ops.check_for_link(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error while checking for link\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t\tmac->autoneg_failed = false;\n\t} else {\n\t\tmac->autoneg_failed = false;\n\t\tDEBUGOUT(\"Valid Link Found\\n\");\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes\n * @hw: pointer to the HW structure\n *\n * Configures collision distance and flow control for fiber and serdes\n * links. Upon successful setup, poll for link.\n **/\ns32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_setup_fiber_serdes_link_generic\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\t/* Take the link out of reset */\n\tctrl &= ~E1000_CTRL_LRST;\n\n\thw->mac.ops.config_collision_dist(hw);\n\n\tret_val = e1000_commit_fc_settings_generic(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Since auto-negotiation is enabled, take the link out of reset (the\n\t * link will be in reset, because we previously reset the chip). This\n\t * will restart auto-negotiation. If auto-negotiation is successful\n\t * then the link-up status bit will be set and the flow control enable\n\t * bits (RFCE and TFCE) will be set according to their negotiated value.\n\t */\n\tDEBUGOUT(\"Auto-negotiation enabled\\n\");\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\tE1000_WRITE_FLUSH(hw);\n\tmsec_delay(1);\n\n\t/* For these adapters, the SW definable pin 1 is set when the optics\n\t * detect a signal. If we have a signal, then poll for a \"Link-Up\"\n\t * indication.\n\t */\n\tif (hw->phy.media_type == e1000_media_type_internal_serdes ||\n\t (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {\n\t\tret_val = e1000_poll_fiber_serdes_link_generic(hw);\n\t} else {\n\t\tDEBUGOUT(\"No signal detected\\n\");\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_config_collision_dist_generic - Configure collision distance\n * @hw: pointer to the HW structure\n *\n * Configures the collision distance to the default value and is used\n * during link setup.\n **/\nstatic void e1000_config_collision_dist_generic(struct e1000_hw *hw)\n{\n\tu32 tctl;\n\n\tDEBUGFUNC(\"e1000_config_collision_dist_generic\");\n\n\ttctl = E1000_READ_REG(hw, E1000_TCTL);\n\n\ttctl &= ~E1000_TCTL_COLD;\n\ttctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;\n\n\tE1000_WRITE_REG(hw, E1000_TCTL, tctl);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks\n * @hw: pointer to the HW structure\n *\n * Sets the flow control high/low threshold (watermark) registers. If\n * flow control XON frame transmission is enabled, then set XON frame\n * transmission as well.\n **/\ns32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)\n{\n\tu32 fcrtl = 0, fcrth = 0;\n\n\tDEBUGFUNC(\"e1000_set_fc_watermarks_generic\");\n\n\t/* Set the flow control receive threshold registers. Normally,\n\t * these registers will be set to a default threshold that may be\n\t * adjusted later by the driver's runtime code. However, if the\n\t * ability to transmit pause frames is not enabled, then these\n\t * registers will be set to 0.\n\t */\n\tif (hw->fc.current_mode & e1000_fc_tx_pause) {\n\t\t/* We need to set up the Receive Threshold high and low water\n\t\t * marks as well as (optionally) enabling the transmission of\n\t\t * XON frames.\n\t\t */\n\t\tfcrtl = hw->fc.low_water;\n\t\tif (hw->fc.send_xon)\n\t\t\tfcrtl |= E1000_FCRTL_XONE;\n\n\t\tfcrth = hw->fc.high_water;\n\t}\n\tE1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);\n\tE1000_WRITE_REG(hw, E1000_FCRTH, fcrth);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_force_mac_fc_generic - Force the MAC's flow control settings\n * @hw: pointer to the HW structure\n *\n * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the\n * device control register to reflect the adapter settings. TFCE and RFCE\n * need to be explicitly set by software when a copper PHY is used because\n * autonegotiation is managed by the PHY rather than the MAC. Software must\n * also configure these bits when link is forced on a fiber connection.\n **/\ns32 e1000_force_mac_fc_generic(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\n\tDEBUGFUNC(\"e1000_force_mac_fc_generic\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\n\t/* Because we didn't get link via the internal auto-negotiation\n\t * mechanism (we either forced link or we got link via PHY\n\t * auto-neg), we have to manually enable/disable transmit an\n\t * receive flow control.\n\t *\n\t * The \"Case\" statement below enables/disable flow control\n\t * according to the \"hw->fc.current_mode\" parameter.\n\t *\n\t * The possible values of the \"fc\" parameter are:\n\t * 0: Flow control is completely disabled\n\t * 1: Rx flow control is enabled (we can receive pause\n\t * frames but not send pause frames).\n\t * 2: Tx flow control is enabled (we can send pause frames\n\t * frames but we do not receive pause frames).\n\t * 3: Both Rx and Tx flow control (symmetric) is enabled.\n\t * other: No other values should be possible at this point.\n\t */\n\tDEBUGOUT1(\"hw->fc.current_mode = %u\\n\", hw->fc.current_mode);\n\n\tswitch (hw->fc.current_mode) {\n\tcase e1000_fc_none:\n\t\tctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));\n\t\tbreak;\n\tcase e1000_fc_rx_pause:\n\t\tctrl &= (~E1000_CTRL_TFCE);\n\t\tctrl |= E1000_CTRL_RFCE;\n\t\tbreak;\n\tcase e1000_fc_tx_pause:\n\t\tctrl &= (~E1000_CTRL_RFCE);\n\t\tctrl |= E1000_CTRL_TFCE;\n\t\tbreak;\n\tcase e1000_fc_full:\n\t\tctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\"Flow control param set incorrectly\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_config_fc_after_link_up_generic - Configures flow control after link\n * @hw: pointer to the HW structure\n *\n * Checks the status of auto-negotiation after link up to ensure that the\n * speed and duplex were not forced. If the link needed to be forced, then\n * flow control needs to be forced also. If auto-negotiation is enabled\n * and did not fail, then we configure flow control based on our link\n * partner.\n **/\ns32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val = E1000_SUCCESS;\n\tu32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;\n\tu16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;\n\tu16 speed, duplex;\n\n\tDEBUGFUNC(\"e1000_config_fc_after_link_up_generic\");\n\n\t/* Check for the case where we have fiber media and auto-neg failed\n\t * so we had to force link. In this case, we need to force the\n\t * configuration of the MAC to match the \"fc\" parameter.\n\t */\n\tif (mac->autoneg_failed) {\n\t\tif (hw->phy.media_type == e1000_media_type_fiber ||\n\t\t hw->phy.media_type == e1000_media_type_internal_serdes)\n\t\t\tret_val = e1000_force_mac_fc_generic(hw);\n\t} else {\n\t\tif (hw->phy.media_type == e1000_media_type_copper)\n\t\t\tret_val = e1000_force_mac_fc_generic(hw);\n\t}\n\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error forcing flow control settings\\n\");\n\t\treturn ret_val;\n\t}\n\n\t/* Check for the case where we have copper media and auto-neg is\n\t * enabled. In this case, we need to check and see if Auto-Neg\n\t * has completed, and if so, how the PHY and link partner has\n\t * flow control configured.\n\t */\n\tif ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {\n\t\t/* Read the MII Status Register and check to see if AutoNeg\n\t\t * has completed. We read this twice because this reg has\n\t\t * some \"sticky\" (latched) bits.\n\t\t */\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {\n\t\t\tDEBUGOUT(\"Copper PHY and Auto Neg has not completed.\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\n\t\t/* The AutoNeg process has completed, so we now need to\n\t\t * read both the Auto Negotiation Advertisement\n\t\t * Register (Address 4) and the Auto_Negotiation Base\n\t\t * Page Ability Register (Address 5) to determine how\n\t\t * flow control was negotiated.\n\t\t */\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,\n\t\t\t\t\t &mii_nway_adv_reg);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,\n\t\t\t\t\t &mii_nway_lp_ability_reg);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Two bits in the Auto Negotiation Advertisement Register\n\t\t * (Address 4) and two bits in the Auto Negotiation Base\n\t\t * Page Ability Register (Address 5) determine flow control\n\t\t * for both the PHY and the link partner. The following\n\t\t * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,\n\t\t * 1999, describes these PAUSE resolution bits and how flow\n\t\t * control is determined based upon these settings.\n\t\t * NOTE: DC = Don't Care\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 0 | 0 | DC | DC | e1000_fc_none\n\t\t * 0 | 1 | 0 | DC | e1000_fc_none\n\t\t * 0 | 1 | 1 | 0 | e1000_fc_none\n\t\t * 0 | 1 | 1 | 1 | e1000_fc_tx_pause\n\t\t * 1 | 0 | 0 | DC | e1000_fc_none\n\t\t * 1 | DC | 1 | DC | e1000_fc_full\n\t\t * 1 | 1 | 0 | 0 | e1000_fc_none\n\t\t * 1 | 1 | 0 | 1 | e1000_fc_rx_pause\n\t\t *\n\t\t * Are both PAUSE bits set to 1? If so, this implies\n\t\t * Symmetric Flow Control is enabled at both ends. The\n\t\t * ASM_DIR bits are irrelevant per the spec.\n\t\t *\n\t\t * For Symmetric Flow Control:\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 1 | DC | 1 | DC | E1000_fc_full\n\t\t *\n\t\t */\n\t\tif ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&\n\t\t (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {\n\t\t\t/* Now we need to check if the user selected Rx ONLY\n\t\t\t * of pause frames. In this case, we had to advertise\n\t\t\t * FULL flow control because we could not advertise Rx\n\t\t\t * ONLY. Hence, we must now check to see if we need to\n\t\t\t * turn OFF the TRANSMISSION of PAUSE frames.\n\t\t\t */\n\t\t\tif (hw->fc.requested_mode == e1000_fc_full) {\n\t\t\t\thw->fc.current_mode = e1000_fc_full;\n\t\t\t\tDEBUGOUT(\"Flow Control = FULL.\\n\");\n\t\t\t} else {\n\t\t\t\thw->fc.current_mode = e1000_fc_rx_pause;\n\t\t\t\tDEBUGOUT(\"Flow Control = Rx PAUSE frames only.\\n\");\n\t\t\t}\n\t\t}\n\t\t/* For receiving PAUSE frames ONLY.\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 0 | 1 | 1 | 1 | e1000_fc_tx_pause\n\t\t */\n\t\telse if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&\n\t\t\t (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&\n\t\t\t (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&\n\t\t\t (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {\n\t\t\thw->fc.current_mode = e1000_fc_tx_pause;\n\t\t\tDEBUGOUT(\"Flow Control = Tx PAUSE frames only.\\n\");\n\t\t}\n\t\t/* For transmitting PAUSE frames ONLY.\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 1 | 1 | 0 | 1 | e1000_fc_rx_pause\n\t\t */\n\t\telse if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&\n\t\t\t (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&\n\t\t\t !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&\n\t\t\t (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {\n\t\t\thw->fc.current_mode = e1000_fc_rx_pause;\n\t\t\tDEBUGOUT(\"Flow Control = Rx PAUSE frames only.\\n\");\n\t\t} else {\n\t\t\t/* Per the IEEE spec, at this point flow control\n\t\t\t * should be disabled.\n\t\t\t */\n\t\t\thw->fc.current_mode = e1000_fc_none;\n\t\t\tDEBUGOUT(\"Flow Control = NONE.\\n\");\n\t\t}\n\n\t\t/* Now we need to do one last check... If we auto-\n\t\t * negotiated to HALF DUPLEX, flow control should not be\n\t\t * enabled per IEEE 802.3 spec.\n\t\t */\n\t\tret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error getting link speed and duplex\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\n\t\tif (duplex == HALF_DUPLEX)\n\t\t\thw->fc.current_mode = e1000_fc_none;\n\n\t\t/* Now we call a subroutine to actually force the MAC\n\t\t * controller to use the correct flow control settings.\n\t\t */\n\t\tret_val = e1000_force_mac_fc_generic(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error forcing flow control settings\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\t/* Check for the case where we have SerDes media and auto-neg is\n\t * enabled. In this case, we need to check and see if Auto-Neg\n\t * has completed, and if so, how the PHY and link partner has\n\t * flow control configured.\n\t */\n\tif ((hw->phy.media_type == e1000_media_type_internal_serdes) &&\n\t mac->autoneg) {\n\t\t/* Read the PCS_LSTS and check to see if AutoNeg\n\t\t * has completed.\n\t\t */\n\t\tpcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);\n\n\t\tif (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {\n\t\t\tDEBUGOUT(\"PCS Auto Neg has not completed.\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\n\t\t/* The AutoNeg process has completed, so we now need to\n\t\t * read both the Auto Negotiation Advertisement\n\t\t * Register (PCS_ANADV) and the Auto_Negotiation Base\n\t\t * Page Ability Register (PCS_LPAB) to determine how\n\t\t * flow control was negotiated.\n\t\t */\n\t\tpcs_adv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);\n\t\tpcs_lp_ability_reg = E1000_READ_REG(hw, E1000_PCS_LPAB);\n\n\t\t/* Two bits in the Auto Negotiation Advertisement Register\n\t\t * (PCS_ANADV) and two bits in the Auto Negotiation Base\n\t\t * Page Ability Register (PCS_LPAB) determine flow control\n\t\t * for both the PHY and the link partner. The following\n\t\t * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,\n\t\t * 1999, describes these PAUSE resolution bits and how flow\n\t\t * control is determined based upon these settings.\n\t\t * NOTE: DC = Don't Care\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 0 | 0 | DC | DC | e1000_fc_none\n\t\t * 0 | 1 | 0 | DC | e1000_fc_none\n\t\t * 0 | 1 | 1 | 0 | e1000_fc_none\n\t\t * 0 | 1 | 1 | 1 | e1000_fc_tx_pause\n\t\t * 1 | 0 | 0 | DC | e1000_fc_none\n\t\t * 1 | DC | 1 | DC | e1000_fc_full\n\t\t * 1 | 1 | 0 | 0 | e1000_fc_none\n\t\t * 1 | 1 | 0 | 1 | e1000_fc_rx_pause\n\t\t *\n\t\t * Are both PAUSE bits set to 1? If so, this implies\n\t\t * Symmetric Flow Control is enabled at both ends. The\n\t\t * ASM_DIR bits are irrelevant per the spec.\n\t\t *\n\t\t * For Symmetric Flow Control:\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 1 | DC | 1 | DC | e1000_fc_full\n\t\t *\n\t\t */\n\t\tif ((pcs_adv_reg & E1000_TXCW_PAUSE) &&\n\t\t (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {\n\t\t\t/* Now we need to check if the user selected Rx ONLY\n\t\t\t * of pause frames. In this case, we had to advertise\n\t\t\t * FULL flow control because we could not advertise Rx\n\t\t\t * ONLY. Hence, we must now check to see if we need to\n\t\t\t * turn OFF the TRANSMISSION of PAUSE frames.\n\t\t\t */\n\t\t\tif (hw->fc.requested_mode == e1000_fc_full) {\n\t\t\t\thw->fc.current_mode = e1000_fc_full;\n\t\t\t\tDEBUGOUT(\"Flow Control = FULL.\\n\");\n\t\t\t} else {\n\t\t\t\thw->fc.current_mode = e1000_fc_rx_pause;\n\t\t\t\tDEBUGOUT(\"Flow Control = Rx PAUSE frames only.\\n\");\n\t\t\t}\n\t\t}\n\t\t/* For receiving PAUSE frames ONLY.\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 0 | 1 | 1 | 1 | e1000_fc_tx_pause\n\t\t */\n\t\telse if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&\n\t\t\t (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&\n\t\t\t (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&\n\t\t\t (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {\n\t\t\thw->fc.current_mode = e1000_fc_tx_pause;\n\t\t\tDEBUGOUT(\"Flow Control = Tx PAUSE frames only.\\n\");\n\t\t}\n\t\t/* For transmitting PAUSE frames ONLY.\n\t\t *\n\t\t * LOCAL DEVICE | LINK PARTNER\n\t\t * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result\n\t\t *-------|---------|-------|---------|--------------------\n\t\t * 1 | 1 | 0 | 1 | e1000_fc_rx_pause\n\t\t */\n\t\telse if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&\n\t\t\t (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&\n\t\t\t !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&\n\t\t\t (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {\n\t\t\thw->fc.current_mode = e1000_fc_rx_pause;\n\t\t\tDEBUGOUT(\"Flow Control = Rx PAUSE frames only.\\n\");\n\t\t} else {\n\t\t\t/* Per the IEEE spec, at this point flow control\n\t\t\t * should be disabled.\n\t\t\t */\n\t\t\thw->fc.current_mode = e1000_fc_none;\n\t\t\tDEBUGOUT(\"Flow Control = NONE.\\n\");\n\t\t}\n\n\t\t/* Now we call a subroutine to actually force the MAC\n\t\t * controller to use the correct flow control settings.\n\t\t */\n\t\tpcs_ctrl_reg = E1000_READ_REG(hw, E1000_PCS_LCTL);\n\t\tpcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;\n\t\tE1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_ctrl_reg);\n\n\t\tret_val = e1000_force_mac_fc_generic(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error forcing flow control settings\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex\n * @hw: pointer to the HW structure\n * @speed: stores the current speed\n * @duplex: stores the current duplex\n *\n * Read the status register for the current speed/duplex and store the current\n * speed and duplex for copper connections.\n **/\ns32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\t u16 *duplex)\n{\n\tu32 status;\n\n\tDEBUGFUNC(\"e1000_get_speed_and_duplex_copper_generic\");\n\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\tif (status & E1000_STATUS_SPEED_1000) {\n\t\t*speed = SPEED_1000;\n\t\tDEBUGOUT(\"1000 Mbs, \");\n\t} else if (status & E1000_STATUS_SPEED_100) {\n\t\t*speed = SPEED_100;\n\t\tDEBUGOUT(\"100 Mbs, \");\n\t} else {\n\t\t*speed = SPEED_10;\n\t\tDEBUGOUT(\"10 Mbs, \");\n\t}\n\n\tif (status & E1000_STATUS_FD) {\n\t\t*duplex = FULL_DUPLEX;\n\t\tDEBUGOUT(\"Full Duplex\\n\");\n\t} else {\n\t\t*duplex = HALF_DUPLEX;\n\t\tDEBUGOUT(\"Half Duplex\\n\");\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex\n * @hw: pointer to the HW structure\n * @speed: stores the current speed\n * @duplex: stores the current duplex\n *\n * Sets the speed and duplex to gigabit full duplex (the only possible option)\n * for fiber/serdes links.\n **/\ns32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t\t\t\t u16 *speed, u16 *duplex)\n{\n\tDEBUGFUNC(\"e1000_get_speed_and_duplex_fiber_serdes_generic\");\n\n\t*speed = SPEED_1000;\n\t*duplex = FULL_DUPLEX;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_hw_semaphore_generic - Acquire hardware semaphore\n * @hw: pointer to the HW structure\n *\n * Acquire the HW semaphore to access the PHY or NVM\n **/\ns32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)\n{\n\tu32 swsm;\n\ts32 timeout = hw->nvm.word_size + 1;\n\ts32 i = 0;\n\n\tDEBUGFUNC(\"e1000_get_hw_semaphore_generic\");\n\n\t/* Get the SW semaphore */\n\twhile (i < timeout) {\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tif (!(swsm & E1000_SWSM_SMBI))\n\t\t\tbreak;\n\n\t\tusec_delay(50);\n\t\ti++;\n\t}\n\n\tif (i == timeout) {\n\t\tDEBUGOUT(\"Driver can't access device - SMBI bit is set.\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\t/* Get the FW semaphore. */\n\tfor (i = 0; i < timeout; i++) {\n\t\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\t\tE1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);\n\n\t\t/* Semaphore acquired if bit latched */\n\t\tif (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)\n\t\t\tbreak;\n\n\t\tusec_delay(50);\n\t}\n\n\tif (i == timeout) {\n\t\t/* Release semaphores */\n\t\te1000_put_hw_semaphore_generic(hw);\n\t\tDEBUGOUT(\"Driver can't access the NVM\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_put_hw_semaphore_generic - Release hardware semaphore\n * @hw: pointer to the HW structure\n *\n * Release hardware semaphore used to access the PHY or NVM\n **/\nvoid e1000_put_hw_semaphore_generic(struct e1000_hw *hw)\n{\n\tu32 swsm;\n\n\tDEBUGFUNC(\"e1000_put_hw_semaphore_generic\");\n\n\tswsm = E1000_READ_REG(hw, E1000_SWSM);\n\n\tswsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);\n\n\tE1000_WRITE_REG(hw, E1000_SWSM, swsm);\n}\n\n/**\n * e1000_get_auto_rd_done_generic - Check for auto read completion\n * @hw: pointer to the HW structure\n *\n * Check EEPROM for Auto Read done bit.\n **/\ns32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)\n{\n\ts32 i = 0;\n\n\tDEBUGFUNC(\"e1000_get_auto_rd_done_generic\");\n\n\twhile (i < AUTO_READ_DONE_TIMEOUT) {\n\t\tif (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t\ti++;\n\t}\n\n\tif (i == AUTO_READ_DONE_TIMEOUT) {\n\t\tDEBUGOUT(\"Auto read by HW from NVM has not completed.\\n\");\n\t\treturn -E1000_ERR_RESET;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_valid_led_default_generic - Verify a valid default LED config\n * @hw: pointer to the HW structure\n * @data: pointer to the NVM (EEPROM)\n *\n * Read the EEPROM for the current default LED configuration. If the\n * LED configuration is not valid, set to a valid LED configuration.\n **/\ns32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_valid_led_default_generic\");\n\n\tret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)\n\t\t*data = ID_LED_DEFAULT;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_id_led_init_generic -\n * @hw: pointer to the HW structure\n *\n **/\ns32 e1000_id_led_init_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\ts32 ret_val;\n\tconst u32 ledctl_mask = 0x000000FF;\n\tconst u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;\n\tconst u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;\n\tu16 data, i, temp;\n\tconst u16 led_mask = 0x0F;\n\n\tDEBUGFUNC(\"e1000_id_led_init_generic\");\n\n\tret_val = hw->nvm.ops.valid_led_default(hw, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tmac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);\n\tmac->ledctl_mode1 = mac->ledctl_default;\n\tmac->ledctl_mode2 = mac->ledctl_default;\n\n\tfor (i = 0; i < 4; i++) {\n\t\ttemp = (data >> (i << 2)) & led_mask;\n\t\tswitch (temp) {\n\t\tcase ID_LED_ON1_DEF2:\n\t\tcase ID_LED_ON1_ON2:\n\t\tcase ID_LED_ON1_OFF2:\n\t\t\tmac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));\n\t\t\tmac->ledctl_mode1 |= ledctl_on << (i << 3);\n\t\t\tbreak;\n\t\tcase ID_LED_OFF1_DEF2:\n\t\tcase ID_LED_OFF1_ON2:\n\t\tcase ID_LED_OFF1_OFF2:\n\t\t\tmac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));\n\t\t\tmac->ledctl_mode1 |= ledctl_off << (i << 3);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* Do nothing */\n\t\t\tbreak;\n\t\t}\n\t\tswitch (temp) {\n\t\tcase ID_LED_DEF1_ON2:\n\t\tcase ID_LED_ON1_ON2:\n\t\tcase ID_LED_OFF1_ON2:\n\t\t\tmac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));\n\t\t\tmac->ledctl_mode2 |= ledctl_on << (i << 3);\n\t\t\tbreak;\n\t\tcase ID_LED_DEF1_OFF2:\n\t\tcase ID_LED_ON1_OFF2:\n\t\tcase ID_LED_OFF1_OFF2:\n\t\t\tmac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));\n\t\t\tmac->ledctl_mode2 |= ledctl_off << (i << 3);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* Do nothing */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_setup_led_generic - Configures SW controllable LED\n * @hw: pointer to the HW structure\n *\n * This prepares the SW controllable LED for use and saves the current state\n * of the LED so it can be later restored.\n **/\ns32 e1000_setup_led_generic(struct e1000_hw *hw)\n{\n\tu32 ledctl;\n\n\tDEBUGFUNC(\"e1000_setup_led_generic\");\n\n\tif (hw->mac.ops.setup_led != e1000_setup_led_generic)\n\t\treturn -E1000_ERR_CONFIG;\n\n\tif (hw->phy.media_type == e1000_media_type_fiber) {\n\t\tledctl = E1000_READ_REG(hw, E1000_LEDCTL);\n\t\thw->mac.ledctl_default = ledctl;\n\t\t/* Turn off LED0 */\n\t\tledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |\n\t\t\t E1000_LEDCTL_LED0_MODE_MASK);\n\t\tledctl |= (E1000_LEDCTL_MODE_LED_OFF <<\n\t\t\t E1000_LEDCTL_LED0_MODE_SHIFT);\n\t\tE1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);\n\t} else if (hw->phy.media_type == e1000_media_type_copper) {\n\t\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_cleanup_led_generic - Set LED config to default operation\n * @hw: pointer to the HW structure\n *\n * Remove the current LED configuration and set the LED configuration\n * to the default value, saved from the EEPROM.\n **/\ns32 e1000_cleanup_led_generic(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_cleanup_led_generic\");\n\n\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_blink_led_generic - Blink LED\n * @hw: pointer to the HW structure\n *\n * Blink the LEDs which are set to be on.\n **/\ns32 e1000_blink_led_generic(struct e1000_hw *hw)\n{\n\tu32 ledctl_blink = 0;\n\tu32 i;\n\n\tDEBUGFUNC(\"e1000_blink_led_generic\");\n\n\tif (hw->phy.media_type == e1000_media_type_fiber) {\n\t\t/* always blink LED0 for PCI-E fiber */\n\t\tledctl_blink = E1000_LEDCTL_LED0_BLINK |\n\t\t (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);\n\t} else {\n\t\t/* Set the blink bit for each LED that's \"on\" (0x0E)\n\t\t * (or \"off\" if inverted) in ledctl_mode2. The blink\n\t\t * logic in hardware only works when mode is set to \"on\"\n\t\t * so it must be changed accordingly when the mode is\n\t\t * \"off\" and inverted.\n\t\t */\n\t\tledctl_blink = hw->mac.ledctl_mode2;\n\t\tfor (i = 0; i < 32; i += 8) {\n\t\t\tu32 mode = (hw->mac.ledctl_mode2 >> i) &\n\t\t\t E1000_LEDCTL_LED0_MODE_MASK;\n\t\t\tu32 led_default = hw->mac.ledctl_default >> i;\n\n\t\t\tif ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&\n\t\t\t (mode == E1000_LEDCTL_MODE_LED_ON)) ||\n\t\t\t ((led_default & E1000_LEDCTL_LED0_IVRT) &&\n\t\t\t (mode == E1000_LEDCTL_MODE_LED_OFF))) {\n\t\t\t\tledctl_blink &=\n\t\t\t\t ~(E1000_LEDCTL_LED0_MODE_MASK << i);\n\t\t\t\tledctl_blink |= (E1000_LEDCTL_LED0_BLINK |\n\t\t\t\t\t\t E1000_LEDCTL_MODE_LED_ON) << i;\n\t\t\t}\n\t\t}\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_led_on_generic - Turn LED on\n * @hw: pointer to the HW structure\n *\n * Turn LED on.\n **/\ns32 e1000_led_on_generic(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\n\tDEBUGFUNC(\"e1000_led_on_generic\");\n\n\tswitch (hw->phy.media_type) {\n\tcase e1000_media_type_fiber:\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tctrl &= ~E1000_CTRL_SWDPIN0;\n\t\tctrl |= E1000_CTRL_SWDPIO0;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\t\tbreak;\n\tcase e1000_media_type_copper:\n\t\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_led_off_generic - Turn LED off\n * @hw: pointer to the HW structure\n *\n * Turn LED off.\n **/\ns32 e1000_led_off_generic(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\n\tDEBUGFUNC(\"e1000_led_off_generic\");\n\n\tswitch (hw->phy.media_type) {\n\tcase e1000_media_type_fiber:\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tctrl |= E1000_CTRL_SWDPIN0;\n\t\tctrl |= E1000_CTRL_SWDPIO0;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\t\tbreak;\n\tcase e1000_media_type_copper:\n\t\tE1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities\n * @hw: pointer to the HW structure\n * @no_snoop: bitmap of snoop events\n *\n * Set the PCI-express register to snoop for events enabled in 'no_snoop'.\n **/\nvoid e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)\n{\n\tu32 gcr;\n\n\tDEBUGFUNC(\"e1000_set_pcie_no_snoop_generic\");\n\n\tif (no_snoop) {\n\t\tgcr = E1000_READ_REG(hw, E1000_GCR);\n\t\tgcr &= ~(PCIE_NO_SNOOP_ALL);\n\t\tgcr |= no_snoop;\n\t\tE1000_WRITE_REG(hw, E1000_GCR, gcr);\n\t}\n}\n\n/**\n * e1000_disable_pcie_master_generic - Disables PCI-express master access\n * @hw: pointer to the HW structure\n *\n * Returns E1000_SUCCESS if successful, else returns -10\n * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused\n * the master requests to be disabled.\n *\n * Disables PCI-Express master access and verifies there are no pending\n * requests.\n **/\ns32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)\n{\n\tu32 ctrl;\n\ts32 timeout = MASTER_DISABLE_TIMEOUT;\n\n\tDEBUGFUNC(\"e1000_disable_pcie_master_generic\");\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= E1000_CTRL_GIO_MASTER_DISABLE;\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\twhile (timeout) {\n\t\tif (!(E1000_READ_REG(hw, E1000_STATUS) &\n\t\t E1000_STATUS_GIO_MASTER_ENABLE))\n\t\t\tbreak;\n\t\tusec_delay(100);\n\t\ttimeout--;\n\t}\n\n\tif (!timeout) {\n\t\tDEBUGOUT(\"Master requests are pending.\\n\");\n\t\treturn -E1000_ERR_MASTER_REQUESTS_PENDING;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing\n * @hw: pointer to the HW structure\n *\n * Reset the Adaptive Interframe Spacing throttle to default values.\n **/\nvoid e1000_reset_adaptive_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"e1000_reset_adaptive_generic\");\n\n\tif (!mac->adaptive_ifs) {\n\t\tDEBUGOUT(\"Not in Adaptive IFS mode!\\n\");\n\t\treturn;\n\t}\n\n\tmac->current_ifs_val = 0;\n\tmac->ifs_min_val = IFS_MIN;\n\tmac->ifs_max_val = IFS_MAX;\n\tmac->ifs_step_size = IFS_STEP;\n\tmac->ifs_ratio = IFS_RATIO;\n\n\tmac->in_ifs_mode = false;\n\tE1000_WRITE_REG(hw, E1000_AIT, 0);\n}\n\n/**\n * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing\n * @hw: pointer to the HW structure\n *\n * Update the Adaptive Interframe Spacing Throttle value based on the\n * time between transmitted packets and time between collisions.\n **/\nvoid e1000_update_adaptive_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\n\tDEBUGFUNC(\"e1000_update_adaptive_generic\");\n\n\tif (!mac->adaptive_ifs) {\n\t\tDEBUGOUT(\"Not in Adaptive IFS mode!\\n\");\n\t\treturn;\n\t}\n\n\tif ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {\n\t\tif (mac->tx_packet_delta > MIN_NUM_XMITS) {\n\t\t\tmac->in_ifs_mode = true;\n\t\t\tif (mac->current_ifs_val < mac->ifs_max_val) {\n\t\t\t\tif (!mac->current_ifs_val)\n\t\t\t\t\tmac->current_ifs_val = mac->ifs_min_val;\n\t\t\t\telse\n\t\t\t\t\tmac->current_ifs_val +=\n\t\t\t\t\t\tmac->ifs_step_size;\n\t\t\t\tE1000_WRITE_REG(hw, E1000_AIT,\n\t\t\t\t\t\tmac->current_ifs_val);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tif (mac->in_ifs_mode &&\n\t\t (mac->tx_packet_delta <= MIN_NUM_XMITS)) {\n\t\t\tmac->current_ifs_val = 0;\n\t\t\tmac->in_ifs_mode = false;\n\t\t\tE1000_WRITE_REG(hw, E1000_AIT, 0);\n\t\t}\n\t}\n}\n\n/**\n * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings\n * @hw: pointer to the HW structure\n *\n * Verify that when not using auto-negotiation that MDI/MDIx is correctly\n * set, which is forced to MDI mode only.\n **/\nstatic s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)\n{\n\tDEBUGFUNC(\"e1000_validate_mdi_setting_generic\");\n\n\tif (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {\n\t\tDEBUGOUT(\"Invalid MDI setting detected\\n\");\n\t\thw->phy.mdix = 1;\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings\n * @hw: pointer to the HW structure\n *\n * Validate the MDI/MDIx setting, allowing for auto-crossover during forced\n * operation.\n **/\ns32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_validate_mdi_setting_crossover_generic\");\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register\n * @hw: pointer to the HW structure\n * @reg: 32bit register offset such as E1000_SCTL\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Writes an address/data control type register. There are several of these\n * and they all have the format address << 8 | data and bit 31 is polled for\n * completion.\n **/\ns32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,\n\t\t\t\t u32 offset, u8 data)\n{\n\tu32 i, regvalue = 0;\n\n\tDEBUGFUNC(\"e1000_write_8bit_ctrl_reg_generic\");\n\n\t/* Set up the address and data */\n\tregvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);\n\tE1000_WRITE_REG(hw, reg, regvalue);\n\n\t/* Poll the ready bit to see if the MDI read completed */\n\tfor (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {\n\t\tusec_delay(5);\n\t\tregvalue = E1000_READ_REG(hw, reg);\n\t\tif (regvalue & E1000_GEN_CTL_READY)\n\t\t\tbreak;\n\t}\n\tif (!(regvalue & E1000_GEN_CTL_READY)) {\n\t\tDEBUGOUT1(\"Reg %08x did not indicate ready\\n\", reg);\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_mac.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _E1000_MAC_H_\n#define _E1000_MAC_H_\n\nvoid e1000_init_mac_ops_generic(struct e1000_hw *hw);\nvoid e1000_null_mac_generic(struct e1000_hw *hw);\ns32 e1000_null_ops_generic(struct e1000_hw *hw);\ns32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d);\nbool e1000_null_mng_mode(struct e1000_hw *hw);\nvoid e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a);\nvoid e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b);\nvoid e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a);\ns32 e1000_blink_led_generic(struct e1000_hw *hw);\ns32 e1000_check_for_copper_link_generic(struct e1000_hw *hw);\ns32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw);\ns32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw);\ns32 e1000_cleanup_led_generic(struct e1000_hw *hw);\ns32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw);\ns32 e1000_disable_pcie_master_generic(struct e1000_hw *hw);\ns32 e1000_force_mac_fc_generic(struct e1000_hw *hw);\ns32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw);\ns32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw);\nvoid e1000_set_lan_id_single_port(struct e1000_hw *hw);\ns32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw);\ns32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,\n\t\t\t\t\t u16 *duplex);\ns32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,\n\t\t\t\t\t\t u16 *speed, u16 *duplex);\ns32 e1000_id_led_init_generic(struct e1000_hw *hw);\ns32 e1000_led_on_generic(struct e1000_hw *hw);\ns32 e1000_led_off_generic(struct e1000_hw *hw);\nvoid e1000_update_mc_addr_list_generic(struct e1000_hw *hw,\n\t\t\t\t u8 *mc_addr_list, u32 mc_addr_count);\ns32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw);\ns32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw);\ns32 e1000_setup_led_generic(struct e1000_hw *hw);\ns32 e1000_setup_link_generic(struct e1000_hw *hw);\ns32 e1000_validate_mdi_setting_crossover_generic(struct e1000_hw *hw);\ns32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,\n\t\t\t\t u32 offset, u8 data);\n\nu32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr);\n\nvoid e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw);\nvoid e1000_clear_vfta_generic(struct e1000_hw *hw);\nvoid e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count);\nvoid e1000_put_hw_semaphore_generic(struct e1000_hw *hw);\ns32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);\nvoid e1000_reset_adaptive_generic(struct e1000_hw *hw);\nvoid e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop);\nvoid e1000_update_adaptive_generic(struct e1000_hw *hw);\nvoid e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);\n\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_manage.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"e1000_api.h\"\n\n/**\n * e1000_calculate_checksum - Calculate checksum for buffer\n * @buffer: pointer to EEPROM\n * @length: size of EEPROM to calculate a checksum for\n *\n * Calculates the checksum for some buffer on a specified length. The\n * checksum calculated is returned.\n **/\nu8 e1000_calculate_checksum(u8 *buffer, u32 length)\n{\n\tu32 i;\n\tu8 sum = 0;\n\n\tDEBUGFUNC(\"e1000_calculate_checksum\");\n\n\tif (!buffer)\n\t\treturn 0;\n\n\tfor (i = 0; i < length; i++)\n\t\tsum += buffer[i];\n\n\treturn (u8) (0 - sum);\n}\n\n/**\n * e1000_mng_enable_host_if_generic - Checks host interface is enabled\n * @hw: pointer to the HW structure\n *\n * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND\n *\n * This function checks whether the HOST IF is enabled for command operation\n * and also checks whether the previous command is completed. It busy waits\n * in case of previous command is not completed.\n **/\ns32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)\n{\n\tu32 hicr;\n\tu8 i;\n\n\tDEBUGFUNC(\"e1000_mng_enable_host_if_generic\");\n\n\tif (!hw->mac.arc_subsystem_valid) {\n\t\tDEBUGOUT(\"ARC subsystem not valid.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\t/* Check that the host interface is enabled. */\n\thicr = E1000_READ_REG(hw, E1000_HICR);\n\tif (!(hicr & E1000_HICR_EN)) {\n\t\tDEBUGOUT(\"E1000_HOST_EN bit disabled.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\t/* check the previous command is completed */\n\tfor (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {\n\t\thicr = E1000_READ_REG(hw, E1000_HICR);\n\t\tif (!(hicr & E1000_HICR_C))\n\t\t\tbreak;\n\t\tmsec_delay_irq(1);\n\t}\n\n\tif (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {\n\t\tDEBUGOUT(\"Previous command timeout failed .\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_check_mng_mode_generic - Generic check management mode\n * @hw: pointer to the HW structure\n *\n * Reads the firmware semaphore register and returns true (>0) if\n * manageability is enabled, else false (0).\n **/\nbool e1000_check_mng_mode_generic(struct e1000_hw *hw)\n{\n\tu32 fwsm = E1000_READ_REG(hw, E1000_FWSM);\n\n\tDEBUGFUNC(\"e1000_check_mng_mode_generic\");\n\n\n\treturn (fwsm & E1000_FWSM_MODE_MASK) ==\n\t\t(E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);\n}\n\n/**\n * e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx\n * @hw: pointer to the HW structure\n *\n * Enables packet filtering on transmit packets if manageability is enabled\n * and host interface is enabled.\n **/\nbool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;\n\tu32 *buffer = (u32 *)&hw->mng_cookie;\n\tu32 offset;\n\ts32 ret_val, hdr_csum, csum;\n\tu8 i, len;\n\n\tDEBUGFUNC(\"e1000_enable_tx_pkt_filtering_generic\");\n\n\thw->mac.tx_pkt_filtering = true;\n\n\t/* No manageability, no filtering */\n\tif (!hw->mac.ops.check_mng_mode(hw)) {\n\t\thw->mac.tx_pkt_filtering = false;\n\t\treturn hw->mac.tx_pkt_filtering;\n\t}\n\n\t/* If we can't read from the host interface for whatever\n\t * reason, disable filtering.\n\t */\n\tret_val = e1000_mng_enable_host_if_generic(hw);\n\tif (ret_val != E1000_SUCCESS) {\n\t\thw->mac.tx_pkt_filtering = false;\n\t\treturn hw->mac.tx_pkt_filtering;\n\t}\n\n\t/* Read in the header. Length and offset are in dwords. */\n\tlen = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;\n\toffset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;\n\tfor (i = 0; i < len; i++)\n\t\t*(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,\n\t\t\t\t\t\t\t offset + i);\n\thdr_csum = hdr->checksum;\n\thdr->checksum = 0;\n\tcsum = e1000_calculate_checksum((u8 *)hdr,\n\t\t\t\t\tE1000_MNG_DHCP_COOKIE_LENGTH);\n\t/* If either the checksums or signature don't match, then\n\t * the cookie area isn't considered valid, in which case we\n\t * take the safe route of assuming Tx filtering is enabled.\n\t */\n\tif ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {\n\t\thw->mac.tx_pkt_filtering = true;\n\t\treturn hw->mac.tx_pkt_filtering;\n\t}\n\n\t/* Cookie area is valid, make the final check for filtering. */\n\tif (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))\n\t\thw->mac.tx_pkt_filtering = false;\n\n\treturn hw->mac.tx_pkt_filtering;\n}\n\n/**\n * e1000_mng_write_cmd_header_generic - Writes manageability command header\n * @hw: pointer to the HW structure\n * @hdr: pointer to the host interface command header\n *\n * Writes the command header after does the checksum calculation.\n **/\ns32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,\n\t\t\t\t struct e1000_host_mng_command_header *hdr)\n{\n\tu16 i, length = sizeof(struct e1000_host_mng_command_header);\n\n\tDEBUGFUNC(\"e1000_mng_write_cmd_header_generic\");\n\n\t/* Write the whole command header structure with new checksum. */\n\n\thdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);\n\n\tlength >>= 2;\n\t/* Write the relevant command block into the ram area. */\n\tfor (i = 0; i < length; i++) {\n\t\tE1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,\n\t\t\t\t\t *((u32 *) hdr + i));\n\t\tE1000_WRITE_FLUSH(hw);\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_mng_host_if_write_generic - Write to the manageability host interface\n * @hw: pointer to the HW structure\n * @buffer: pointer to the host interface buffer\n * @length: size of the buffer\n * @offset: location in the buffer to write to\n * @sum: sum of the data (not checksum)\n *\n * This function writes the buffer content at the offset given on the host if.\n * It also does alignment considerations to do the writes in most efficient\n * way. Also fills up the sum of the buffer in *buffer parameter.\n **/\ns32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,\n\t\t\t\t u16 length, u16 offset, u8 *sum)\n{\n\tu8 *tmp;\n\tu8 *bufptr = buffer;\n\tu32 data = 0;\n\tu16 remaining, i, j, prev_bytes;\n\n\tDEBUGFUNC(\"e1000_mng_host_if_write_generic\");\n\n\t/* sum = only sum of the data and it is not checksum */\n\n\tif (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)\n\t\treturn -E1000_ERR_PARAM;\n\n\ttmp = (u8 *)&data;\n\tprev_bytes = offset & 0x3;\n\toffset >>= 2;\n\n\tif (prev_bytes) {\n\t\tdata = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);\n\t\tfor (j = prev_bytes; j < sizeof(u32); j++) {\n\t\t\t*(tmp + j) = *bufptr++;\n\t\t\t*sum += *(tmp + j);\n\t\t}\n\t\tE1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);\n\t\tlength -= j - prev_bytes;\n\t\toffset++;\n\t}\n\n\tremaining = length & 0x3;\n\tlength -= remaining;\n\n\t/* Calculate length in DWORDs */\n\tlength >>= 2;\n\n\t/* The device driver writes the relevant command block into the\n\t * ram area.\n\t */\n\tfor (i = 0; i < length; i++) {\n\t\tfor (j = 0; j < sizeof(u32); j++) {\n\t\t\t*(tmp + j) = *bufptr++;\n\t\t\t*sum += *(tmp + j);\n\t\t}\n\n\t\tE1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,\n\t\t\t\t\t data);\n\t}\n\tif (remaining) {\n\t\tfor (j = 0; j < sizeof(u32); j++) {\n\t\t\tif (j < remaining)\n\t\t\t\t*(tmp + j) = *bufptr++;\n\t\t\telse\n\t\t\t\t*(tmp + j) = 0;\n\n\t\t\t*sum += *(tmp + j);\n\t\t}\n\t\tE1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,\n\t\t\t\t\t data);\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface\n * @hw: pointer to the HW structure\n * @buffer: pointer to the host interface\n * @length: size of the buffer\n *\n * Writes the DHCP information to the host interface.\n **/\ns32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,\n\t\t\t\t u16 length)\n{\n\tstruct e1000_host_mng_command_header hdr;\n\ts32 ret_val;\n\tu32 hicr;\n\n\tDEBUGFUNC(\"e1000_mng_write_dhcp_info_generic\");\n\n\thdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;\n\thdr.command_length = length;\n\thdr.reserved1 = 0;\n\thdr.reserved2 = 0;\n\thdr.checksum = 0;\n\n\t/* Enable the host interface */\n\tret_val = e1000_mng_enable_host_if_generic(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Populate the host interface with the contents of \"buffer\". */\n\tret_val = e1000_mng_host_if_write_generic(hw, buffer, length,\n\t\t\t\t\t\t sizeof(hdr), &(hdr.checksum));\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Write the manageability command header */\n\tret_val = e1000_mng_write_cmd_header_generic(hw, &hdr);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Tell the ARC a new command is pending. */\n\thicr = E1000_READ_REG(hw, E1000_HICR);\n\tE1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_enable_mng_pass_thru - Check if management passthrough is needed\n * @hw: pointer to the HW structure\n *\n * Verifies the hardware needs to leave interface enabled so that frames can\n * be directed to and from the management interface.\n **/\nbool e1000_enable_mng_pass_thru(struct e1000_hw *hw)\n{\n\tu32 manc;\n\tu32 fwsm, factps;\n\n\tDEBUGFUNC(\"e1000_enable_mng_pass_thru\");\n\n\tif (!hw->mac.asf_firmware_present)\n\t\treturn false;\n\n\tmanc = E1000_READ_REG(hw, E1000_MANC);\n\n\tif (!(manc & E1000_MANC_RCV_TCO_EN))\n\t\treturn false;\n\n\tif (hw->mac.has_fwsm) {\n\t\tfwsm = E1000_READ_REG(hw, E1000_FWSM);\n\t\tfactps = E1000_READ_REG(hw, E1000_FACTPS);\n\n\t\tif (!(factps & E1000_FACTPS_MNGCG) &&\n\t\t ((fwsm & E1000_FWSM_MODE_MASK) ==\n\t\t (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))\n\t\t\treturn true;\n\t} else if ((manc & E1000_MANC_SMBUS_EN) &&\n\t\t !(manc & E1000_MANC_ASF_EN)) {\n\t\treturn true;\n\t}\n\n\treturn false;\n}\n\n/**\n * e1000_host_interface_command - Writes buffer to host interface\n * @hw: pointer to the HW structure\n * @buffer: contains a command to write\n * @length: the byte length of the buffer, must be multiple of 4 bytes\n *\n * Writes a buffer to the Host Interface. Upon success, returns E1000_SUCCESS\n * else returns E1000_ERR_HOST_INTERFACE_COMMAND.\n **/\ns32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)\n{\n\tu32 hicr, i;\n\n\tDEBUGFUNC(\"e1000_host_interface_command\");\n\n\tif (!(hw->mac.arc_subsystem_valid)) {\n\t\tDEBUGOUT(\"Hardware doesn't support host interface command.\\n\");\n\t\treturn E1000_SUCCESS;\n\t}\n\n\tif (!hw->mac.asf_firmware_present) {\n\t\tDEBUGOUT(\"Firmware is not present.\\n\");\n\t\treturn E1000_SUCCESS;\n\t}\n\n\tif (length == 0 || length & 0x3 ||\n\t length > E1000_HI_MAX_BLOCK_BYTE_LENGTH) {\n\t\tDEBUGOUT(\"Buffer length failure.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\t/* Check that the host interface is enabled. */\n\thicr = E1000_READ_REG(hw, E1000_HICR);\n\tif (!(hicr & E1000_HICR_EN)) {\n\t\tDEBUGOUT(\"E1000_HOST_EN bit disabled.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\t/* Calculate length in DWORDs */\n\tlength >>= 2;\n\n\t/* The device driver writes the relevant command block\n\t * into the ram area.\n\t */\n\tfor (i = 0; i < length; i++)\n\t\tE1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,\n\t\t\t\t\t *((u32 *)buffer + i));\n\n\t/* Setting this bit tells the ARC that a new command is pending. */\n\tE1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);\n\n\tfor (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {\n\t\thicr = E1000_READ_REG(hw, E1000_HICR);\n\t\tif (!(hicr & E1000_HICR_C))\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t}\n\n\t/* Check command successful completion. */\n\tif (i == E1000_HI_COMMAND_TIMEOUT ||\n\t (!(E1000_READ_REG(hw, E1000_HICR) & E1000_HICR_SV))) {\n\t\tDEBUGOUT(\"Command has failed with no status valid.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\tfor (i = 0; i < length; i++)\n\t\t*((u32 *)buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,\n\t\t\t\t\t\t\t\t E1000_HOST_IF,\n\t\t\t\t\t\t\t\t i);\n\n\treturn E1000_SUCCESS;\n}\n/**\n * e1000_load_firmware - Writes proxy FW code buffer to host interface\n * and execute.\n * @hw: pointer to the HW structure\n * @buffer: contains a firmware to write\n * @length: the byte length of the buffer, must be multiple of 4 bytes\n *\n * Upon success returns E1000_SUCCESS, returns E1000_ERR_CONFIG if not enabled\n * in HW else returns E1000_ERR_HOST_INTERFACE_COMMAND.\n **/\ns32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)\n{\n\tu32 hicr, hibba, fwsm, icr, i;\n\n\tDEBUGFUNC(\"e1000_load_firmware\");\n\n\tif (hw->mac.type < e1000_i210) {\n\t\tDEBUGOUT(\"Hardware doesn't support loading FW by the driver\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\t/* Check that the host interface is enabled. */\n\thicr = E1000_READ_REG(hw, E1000_HICR);\n\tif (!(hicr & E1000_HICR_EN)) {\n\t\tDEBUGOUT(\"E1000_HOST_EN bit disabled.\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\tif (!(hicr & E1000_HICR_MEMORY_BASE_EN)) {\n\t\tDEBUGOUT(\"E1000_HICR_MEMORY_BASE_EN bit disabled.\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tif (length == 0 || length & 0x3 || length > E1000_HI_FW_MAX_LENGTH) {\n\t\tDEBUGOUT(\"Buffer length failure.\\n\");\n\t\treturn -E1000_ERR_INVALID_ARGUMENT;\n\t}\n\n\t/* Clear notification from ROM-FW by reading ICR register */\n\ticr = E1000_READ_REG(hw, E1000_ICR_V2);\n\n\t/* Reset ROM-FW */\n\thicr = E1000_READ_REG(hw, E1000_HICR);\n\thicr |= E1000_HICR_FW_RESET_ENABLE;\n\tE1000_WRITE_REG(hw, E1000_HICR, hicr);\n\thicr |= E1000_HICR_FW_RESET;\n\tE1000_WRITE_REG(hw, E1000_HICR, hicr);\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* Wait till MAC notifies about its readiness after ROM-FW reset */\n\tfor (i = 0; i < (E1000_HI_COMMAND_TIMEOUT * 2); i++) {\n\t\ticr = E1000_READ_REG(hw, E1000_ICR_V2);\n\t\tif (icr & E1000_ICR_MNG)\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t}\n\n\t/* Check for timeout */\n\tif (i == E1000_HI_COMMAND_TIMEOUT) {\n\t\tDEBUGOUT(\"FW reset failed.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\t/* Wait till MAC is ready to accept new FW code */\n\tfor (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {\n\t\tfwsm = E1000_READ_REG(hw, E1000_FWSM);\n\t\tif ((fwsm & E1000_FWSM_FW_VALID) &&\n\t\t ((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT ==\n\t\t E1000_FWSM_HI_EN_ONLY_MODE))\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t}\n\n\t/* Check for timeout */\n\tif (i == E1000_HI_COMMAND_TIMEOUT) {\n\t\tDEBUGOUT(\"FW reset failed.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\t/* Calculate length in DWORDs */\n\tlength >>= 2;\n\n\t/* The device driver writes the relevant FW code block\n\t * into the ram area in DWORDs via 1kB ram addressing window.\n\t */\n\tfor (i = 0; i < length; i++) {\n\t\tif (!(i % E1000_HI_FW_BLOCK_DWORD_LENGTH)) {\n\t\t\t/* Point to correct 1kB ram window */\n\t\t\thibba = E1000_HI_FW_BASE_ADDRESS +\n\t\t\t\t((E1000_HI_FW_BLOCK_DWORD_LENGTH << 2) *\n\t\t\t\t(i / E1000_HI_FW_BLOCK_DWORD_LENGTH));\n\n\t\t\tE1000_WRITE_REG(hw, E1000_HIBBA, hibba);\n\t\t}\n\n\t\tE1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF,\n\t\t\t\t\t i % E1000_HI_FW_BLOCK_DWORD_LENGTH,\n\t\t\t\t\t *((u32 *)buffer + i));\n\t}\n\n\t/* Setting this bit tells the ARC that a new FW is ready to execute. */\n\thicr = E1000_READ_REG(hw, E1000_HICR);\n\tE1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);\n\n\tfor (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {\n\t\thicr = E1000_READ_REG(hw, E1000_HICR);\n\t\tif (!(hicr & E1000_HICR_C))\n\t\t\tbreak;\n\t\tmsec_delay(1);\n\t}\n\n\t/* Check for successful FW start. */\n\tif (i == E1000_HI_COMMAND_TIMEOUT) {\n\t\tDEBUGOUT(\"New FW did not start within timeout period.\\n\");\n\t\treturn -E1000_ERR_HOST_INTERFACE_COMMAND;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_manage.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _E1000_MANAGE_H_\n#define _E1000_MANAGE_H_\n\nbool e1000_check_mng_mode_generic(struct e1000_hw *hw);\nbool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);\ns32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw);\ns32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,\n\t\t\t\t u16 length, u16 offset, u8 *sum);\ns32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,\n\t\t\t\t struct e1000_host_mng_command_header *hdr);\ns32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,\n\t\t\t\t u8 *buffer, u16 length);\nbool e1000_enable_mng_pass_thru(struct e1000_hw *hw);\nu8 e1000_calculate_checksum(u8 *buffer, u32 length);\ns32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length);\ns32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length);\n\nenum e1000_mng_mode {\n\te1000_mng_mode_none = 0,\n\te1000_mng_mode_asf,\n\te1000_mng_mode_pt,\n\te1000_mng_mode_ipmi,\n\te1000_mng_mode_host_if_only\n};\n\n#define E1000_FACTPS_MNGCG\t\t\t0x20000000\n\n#define E1000_FWSM_MODE_MASK\t\t\t0xE\n#define E1000_FWSM_MODE_SHIFT\t\t\t1\n#define E1000_FWSM_FW_VALID\t\t\t0x00008000\n#define E1000_FWSM_HI_EN_ONLY_MODE\t\t0x4\n\n#define E1000_MNG_IAMT_MODE\t\t\t0x3\n#define E1000_MNG_DHCP_COOKIE_LENGTH\t\t0x10\n#define E1000_MNG_DHCP_COOKIE_OFFSET\t\t0x6F0\n#define E1000_MNG_DHCP_COMMAND_TIMEOUT\t\t10\n#define E1000_MNG_DHCP_TX_PAYLOAD_CMD\t\t64\n#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING\t0x1\n#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN\t0x2\n\n#define E1000_VFTA_ENTRY_SHIFT\t\t\t5\n#define E1000_VFTA_ENTRY_MASK\t\t\t0x7F\n#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK\t\t0x1F\n\n#define E1000_HI_MAX_BLOCK_BYTE_LENGTH\t\t1792 /* Num of bytes in range */\n#define E1000_HI_MAX_BLOCK_DWORD_LENGTH\t\t448 /* Num of dwords in range */\n#define E1000_HI_COMMAND_TIMEOUT\t\t500 /* Process HI cmd limit */\n#define E1000_HI_FW_BASE_ADDRESS\t\t0x10000\n#define E1000_HI_FW_MAX_LENGTH\t\t\t(64 * 1024) /* Num of bytes */\n#define E1000_HI_FW_BLOCK_DWORD_LENGTH\t\t256 /* Num of DWORDs per page */\n#define E1000_HICR_MEMORY_BASE_EN\t\t0x200 /* MB Enable bit - RO */\n#define E1000_HICR_EN\t\t\t0x01 /* Enable bit - RO */\n/* Driver sets this bit when done to put command in RAM */\n#define E1000_HICR_C\t\t\t0x02\n#define E1000_HICR_SV\t\t\t0x04 /* Status Validity */\n#define E1000_HICR_FW_RESET_ENABLE\t0x40\n#define E1000_HICR_FW_RESET\t\t0x80\n\n/* Intel(R) Active Management Technology signature */\n#define E1000_IAMT_SIGNATURE\t\t0x544D4149\n\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_mbx.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"e1000_mbx.h\"\n\n/**\n * e1000_null_mbx_check_for_flag - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\nstatic s32 e1000_null_mbx_check_for_flag(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t\t\t u16 E1000_UNUSEDARG mbx_id)\n{\n\tDEBUGFUNC(\"e1000_null_mbx_check_flag\");\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_mbx_transact - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\nstatic s32 e1000_null_mbx_transact(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t\t u32 E1000_UNUSEDARG *msg,\n\t\t\t\t u16 E1000_UNUSEDARG size,\n\t\t\t\t u16 E1000_UNUSEDARG mbx_id)\n{\n\tDEBUGFUNC(\"e1000_null_mbx_rw_msg\");\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_mbx - Reads a message from the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to read\n *\n * returns SUCCESS if it successfully read message from buffer\n **/\ns32 e1000_read_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_read_mbx\");\n\n\t/* limit read to size of mailbox */\n\tif (size > mbx->size)\n\t\tsize = mbx->size;\n\n\tif (mbx->ops.read)\n\t\tret_val = mbx->ops.read(hw, msg, size, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_mbx - Write a message to the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully copied message into the buffer\n **/\ns32 e1000_write_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_write_mbx\");\n\n\tif (size > mbx->size)\n\t\tret_val = -E1000_ERR_MBX;\n\n\telse if (mbx->ops.write)\n\t\tret_val = mbx->ops.write(hw, msg, size, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_msg - checks to see if someone sent us mail\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the Status bit was found or else ERR_MBX\n **/\ns32 e1000_check_for_msg(struct e1000_hw *hw, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_check_for_msg\");\n\n\tif (mbx->ops.check_for_msg)\n\t\tret_val = mbx->ops.check_for_msg(hw, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_ack - checks to see if someone sent us ACK\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the Status bit was found or else ERR_MBX\n **/\ns32 e1000_check_for_ack(struct e1000_hw *hw, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_check_for_ack\");\n\n\tif (mbx->ops.check_for_ack)\n\t\tret_val = mbx->ops.check_for_ack(hw, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_rst - checks to see if other side has reset\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to check\n *\n * returns SUCCESS if the Status bit was found or else ERR_MBX\n **/\ns32 e1000_check_for_rst(struct e1000_hw *hw, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_check_for_rst\");\n\n\tif (mbx->ops.check_for_rst)\n\t\tret_val = mbx->ops.check_for_rst(hw, mbx_id);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_poll_for_msg - Wait for message notification\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully received a message notification\n **/\nstatic s32 e1000_poll_for_msg(struct e1000_hw *hw, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tint countdown = mbx->timeout;\n\n\tDEBUGFUNC(\"e1000_poll_for_msg\");\n\n\tif (!countdown || !mbx->ops.check_for_msg)\n\t\tgoto out;\n\n\twhile (countdown && mbx->ops.check_for_msg(hw, mbx_id)) {\n\t\tcountdown--;\n\t\tif (!countdown)\n\t\t\tbreak;\n\t\tusec_delay(mbx->usec_delay);\n\t}\n\n\t/* if we failed, all future posted messages fail until reset */\n\tif (!countdown)\n\t\tmbx->timeout = 0;\nout:\n\treturn countdown ? E1000_SUCCESS : -E1000_ERR_MBX;\n}\n\n/**\n * e1000_poll_for_ack - Wait for message acknowledgement\n * @hw: pointer to the HW structure\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully received a message acknowledgement\n **/\nstatic s32 e1000_poll_for_ack(struct e1000_hw *hw, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tint countdown = mbx->timeout;\n\n\tDEBUGFUNC(\"e1000_poll_for_ack\");\n\n\tif (!countdown || !mbx->ops.check_for_ack)\n\t\tgoto out;\n\n\twhile (countdown && mbx->ops.check_for_ack(hw, mbx_id)) {\n\t\tcountdown--;\n\t\tif (!countdown)\n\t\t\tbreak;\n\t\tusec_delay(mbx->usec_delay);\n\t}\n\n\t/* if we failed, all future posted messages fail until reset */\n\tif (!countdown)\n\t\tmbx->timeout = 0;\nout:\n\treturn countdown ? E1000_SUCCESS : -E1000_ERR_MBX;\n}\n\n/**\n * e1000_read_posted_mbx - Wait for message notification and receive message\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully received a message notification and\n * copied it into the receive buffer.\n **/\ns32 e1000_read_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_read_posted_mbx\");\n\n\tif (!mbx->ops.read)\n\t\tgoto out;\n\n\tret_val = e1000_poll_for_msg(hw, mbx_id);\n\n\t/* if ack received read message, otherwise we timed out */\n\tif (!ret_val)\n\t\tret_val = mbx->ops.read(hw, msg, size, mbx_id);\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_write_posted_mbx - Write a message to the mailbox, wait for ack\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @mbx_id: id of mailbox to write\n *\n * returns SUCCESS if it successfully copied message into the buffer and\n * received an ack to that message within delay * timeout period\n **/\ns32 e1000_write_posted_mbx(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_write_posted_mbx\");\n\n\t/* exit if either we can't write or there isn't a defined timeout */\n\tif (!mbx->ops.write || !mbx->timeout)\n\t\tgoto out;\n\n\t/* send msg */\n\tret_val = mbx->ops.write(hw, msg, size, mbx_id);\n\n\t/* if msg sent wait until we receive an ack */\n\tif (!ret_val)\n\t\tret_val = e1000_poll_for_ack(hw, mbx_id);\nout:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_mbx_ops_generic - Initialize mbx function pointers\n * @hw: pointer to the HW structure\n *\n * Sets the function pointers to no-op functions\n **/\nvoid e1000_init_mbx_ops_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\tmbx->ops.init_params = e1000_null_ops_generic;\n\tmbx->ops.read = e1000_null_mbx_transact;\n\tmbx->ops.write = e1000_null_mbx_transact;\n\tmbx->ops.check_for_msg = e1000_null_mbx_check_for_flag;\n\tmbx->ops.check_for_ack = e1000_null_mbx_check_for_flag;\n\tmbx->ops.check_for_rst = e1000_null_mbx_check_for_flag;\n\tmbx->ops.read_posted = e1000_read_posted_mbx;\n\tmbx->ops.write_posted = e1000_write_posted_mbx;\n}\n\nstatic s32 e1000_check_for_bit_pf(struct e1000_hw *hw, u32 mask)\n{\n\tu32 mbvficr = E1000_READ_REG(hw, E1000_MBVFICR);\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tif (mbvficr & mask) {\n\t\tret_val = E1000_SUCCESS;\n\t\tE1000_WRITE_REG(hw, E1000_MBVFICR, mask);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_msg_pf - checks to see if the VF has sent mail\n * @hw: pointer to the HW structure\n * @vf_number: the VF index\n *\n * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n **/\nstatic s32 e1000_check_for_msg_pf(struct e1000_hw *hw, u16 vf_number)\n{\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_check_for_msg_pf\");\n\n\tif (!e1000_check_for_bit_pf(hw, E1000_MBVFICR_VFREQ_VF1 << vf_number)) {\n\t\tret_val = E1000_SUCCESS;\n\t\thw->mbx.stats.reqs++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_ack_pf - checks to see if the VF has ACKed\n * @hw: pointer to the HW structure\n * @vf_number: the VF index\n *\n * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n **/\nstatic s32 e1000_check_for_ack_pf(struct e1000_hw *hw, u16 vf_number)\n{\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_check_for_ack_pf\");\n\n\tif (!e1000_check_for_bit_pf(hw, E1000_MBVFICR_VFACK_VF1 << vf_number)) {\n\t\tret_val = E1000_SUCCESS;\n\t\thw->mbx.stats.acks++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_for_rst_pf - checks to see if the VF has reset\n * @hw: pointer to the HW structure\n * @vf_number: the VF index\n *\n * returns SUCCESS if the VF has set the Status bit or else ERR_MBX\n **/\nstatic s32 e1000_check_for_rst_pf(struct e1000_hw *hw, u16 vf_number)\n{\n\tu32 vflre = E1000_READ_REG(hw, E1000_VFLRE);\n\ts32 ret_val = -E1000_ERR_MBX;\n\n\tDEBUGFUNC(\"e1000_check_for_rst_pf\");\n\n\tif (vflre & (1 << vf_number)) {\n\t\tret_val = E1000_SUCCESS;\n\t\tE1000_WRITE_REG(hw, E1000_VFLRE, (1 << vf_number));\n\t\thw->mbx.stats.rsts++;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_obtain_mbx_lock_pf - obtain mailbox lock\n * @hw: pointer to the HW structure\n * @vf_number: the VF index\n *\n * return SUCCESS if we obtained the mailbox lock\n **/\nstatic s32 e1000_obtain_mbx_lock_pf(struct e1000_hw *hw, u16 vf_number)\n{\n\ts32 ret_val = -E1000_ERR_MBX;\n\tu32 p2v_mailbox;\n\n\tDEBUGFUNC(\"e1000_obtain_mbx_lock_pf\");\n\n\t/* Take ownership of the buffer */\n\tE1000_WRITE_REG(hw, E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_PFU);\n\n\t/* reserve mailbox for vf use */\n\tp2v_mailbox = E1000_READ_REG(hw, E1000_P2VMAILBOX(vf_number));\n\tif (p2v_mailbox & E1000_P2VMAILBOX_PFU)\n\t\tret_val = E1000_SUCCESS;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_mbx_pf - Places a message in the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @vf_number: the VF index\n *\n * returns SUCCESS if it successfully copied message into the buffer\n **/\nstatic s32 e1000_write_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size,\n\t\t\t u16 vf_number)\n{\n\ts32 ret_val;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_write_mbx_pf\");\n\n\t/* lock the mailbox to prevent pf/vf race condition */\n\tret_val = e1000_obtain_mbx_lock_pf(hw, vf_number);\n\tif (ret_val)\n\t\tgoto out_no_write;\n\n\t/* flush msg and acks as we are overwriting the message buffer */\n\te1000_check_for_msg_pf(hw, vf_number);\n\te1000_check_for_ack_pf(hw, vf_number);\n\n\t/* copy the caller specified message to the mailbox memory buffer */\n\tfor (i = 0; i < size; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_VMBMEM(vf_number), i, msg[i]);\n\n\t/* Interrupt VF to tell it a message has been sent and release buffer*/\n\tE1000_WRITE_REG(hw, E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_STS);\n\n\t/* update stats */\n\thw->mbx.stats.msgs_tx++;\n\nout_no_write:\n\treturn ret_val;\n\n}\n\n/**\n * e1000_read_mbx_pf - Read a message from the mailbox\n * @hw: pointer to the HW structure\n * @msg: The message buffer\n * @size: Length of buffer\n * @vf_number: the VF index\n *\n * This function copies a message from the mailbox buffer to the caller's\n * memory buffer. The presumption is that the caller knows that there was\n * a message due to a VF request so no polling for message is needed.\n **/\nstatic s32 e1000_read_mbx_pf(struct e1000_hw *hw, u32 *msg, u16 size,\n\t\t\t u16 vf_number)\n{\n\ts32 ret_val;\n\tu16 i;\n\n\tDEBUGFUNC(\"e1000_read_mbx_pf\");\n\n\t/* lock the mailbox to prevent pf/vf race condition */\n\tret_val = e1000_obtain_mbx_lock_pf(hw, vf_number);\n\tif (ret_val)\n\t\tgoto out_no_read;\n\n\t/* copy the message to the mailbox memory buffer */\n\tfor (i = 0; i < size; i++)\n\t\tmsg[i] = E1000_READ_REG_ARRAY(hw, E1000_VMBMEM(vf_number), i);\n\n\t/* Acknowledge the message and release buffer */\n\tE1000_WRITE_REG(hw, E1000_P2VMAILBOX(vf_number), E1000_P2VMAILBOX_ACK);\n\n\t/* update stats */\n\thw->mbx.stats.msgs_rx++;\n\nout_no_read:\n\treturn ret_val;\n}\n\n/**\n * e1000_init_mbx_params_pf - set initial values for pf mailbox\n * @hw: pointer to the HW structure\n *\n * Initializes the hw->mbx struct to correct values for pf mailbox\n */\ns32 e1000_init_mbx_params_pf(struct e1000_hw *hw)\n{\n\tstruct e1000_mbx_info *mbx = &hw->mbx;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82576:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\tmbx->timeout = 0;\n\t\tmbx->usec_delay = 0;\n\n\t\tmbx->size = E1000_VFMAILBOX_SIZE;\n\n\t\tmbx->ops.read = e1000_read_mbx_pf;\n\t\tmbx->ops.write = e1000_write_mbx_pf;\n\t\tmbx->ops.read_posted = e1000_read_posted_mbx;\n\t\tmbx->ops.write_posted = e1000_write_posted_mbx;\n\t\tmbx->ops.check_for_msg = e1000_check_for_msg_pf;\n\t\tmbx->ops.check_for_ack = e1000_check_for_ack_pf;\n\t\tmbx->ops.check_for_rst = e1000_check_for_rst_pf;\n\n\t\tmbx->stats.msgs_tx = 0;\n\t\tmbx->stats.msgs_rx = 0;\n\t\tmbx->stats.reqs = 0;\n\t\tmbx->stats.acks = 0;\n\t\tmbx->stats.rsts = 0;\n\tdefault:\n\t\treturn E1000_SUCCESS;\n\t}\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_mbx.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _E1000_MBX_H_\n#define _E1000_MBX_H_\n\n#include \"e1000_api.h\"\n\n#define E1000_P2VMAILBOX_STS\t0x00000001 /* Initiate message send to VF */\n#define E1000_P2VMAILBOX_ACK\t0x00000002 /* Ack message recv'd from VF */\n#define E1000_P2VMAILBOX_VFU\t0x00000004 /* VF owns the mailbox buffer */\n#define E1000_P2VMAILBOX_PFU\t0x00000008 /* PF owns the mailbox buffer */\n#define E1000_P2VMAILBOX_RVFU\t0x00000010 /* Reset VFU - used when VF stuck */\n\n#define E1000_MBVFICR_VFREQ_MASK 0x000000FF /* bits for VF messages */\n#define E1000_MBVFICR_VFREQ_VF1\t0x00000001 /* bit for VF 1 message */\n#define E1000_MBVFICR_VFACK_MASK 0x00FF0000 /* bits for VF acks */\n#define E1000_MBVFICR_VFACK_VF1\t0x00010000 /* bit for VF 1 ack */\n\n#define E1000_VFMAILBOX_SIZE\t16 /* 16 32 bit words - 64 bytes */\n\n/* If it's a E1000_VF_* msg then it originates in the VF and is sent to the\n * PF. The reverse is true if it is E1000_PF_*.\n * Message ACK's are the value or'd with 0xF0000000\n */\n/* Msgs below or'd with this are the ACK */\n#define E1000_VT_MSGTYPE_ACK\t0x80000000\n/* Msgs below or'd with this are the NACK */\n#define E1000_VT_MSGTYPE_NACK\t0x40000000\n/* Indicates that VF is still clear to send requests */\n#define E1000_VT_MSGTYPE_CTS\t0x20000000\n#define E1000_VT_MSGINFO_SHIFT\t16\n/* bits 23:16 are used for extra info for certain messages */\n#define E1000_VT_MSGINFO_MASK\t(0xFF << E1000_VT_MSGINFO_SHIFT)\n\n#define E1000_VF_RESET\t\t\t0x01 /* VF requests reset */\n#define E1000_VF_SET_MAC_ADDR\t\t0x02 /* VF requests to set MAC addr */\n#define E1000_VF_SET_MULTICAST\t\t0x03 /* VF requests to set MC addr */\n#define E1000_VF_SET_MULTICAST_COUNT_MASK (0x1F << E1000_VT_MSGINFO_SHIFT)\n#define E1000_VF_SET_MULTICAST_OVERFLOW\t(0x80 << E1000_VT_MSGINFO_SHIFT)\n#define E1000_VF_SET_VLAN\t\t0x04 /* VF requests to set VLAN */\n#define E1000_VF_SET_VLAN_ADD\t\t(0x01 << E1000_VT_MSGINFO_SHIFT)\n#define E1000_VF_SET_LPE\t\t0x05 /* reqs to set VMOLR.LPE */\n#define E1000_VF_SET_PROMISC\t\t0x06 /* reqs to clear VMOLR.ROPE/MPME*/\n#define E1000_VF_SET_PROMISC_UNICAST\t(0x01 << E1000_VT_MSGINFO_SHIFT)\n#define E1000_VF_SET_PROMISC_MULTICAST\t(0x02 << E1000_VT_MSGINFO_SHIFT)\n\n#define E1000_PF_CONTROL_MSG\t\t0x0100 /* PF control message */\n\n#define E1000_VF_MBX_INIT_TIMEOUT\t2000 /* number of retries on mailbox */\n#define E1000_VF_MBX_INIT_DELAY\t\t500 /* microseconds between retries */\n\ns32 e1000_read_mbx(struct e1000_hw *, u32 *, u16, u16);\ns32 e1000_write_mbx(struct e1000_hw *, u32 *, u16, u16);\ns32 e1000_read_posted_mbx(struct e1000_hw *, u32 *, u16, u16);\ns32 e1000_write_posted_mbx(struct e1000_hw *, u32 *, u16, u16);\ns32 e1000_check_for_msg(struct e1000_hw *, u16);\ns32 e1000_check_for_ack(struct e1000_hw *, u16);\ns32 e1000_check_for_rst(struct e1000_hw *, u16);\nvoid e1000_init_mbx_ops_generic(struct e1000_hw *hw);\ns32 e1000_init_mbx_params_pf(struct e1000_hw *);\n\n#endif /* _E1000_MBX_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_nvm.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"e1000_api.h\"\n\nstatic void e1000_reload_nvm_generic(struct e1000_hw *hw);\n\n/**\n * e1000_init_nvm_ops_generic - Initialize NVM function pointers\n * @hw: pointer to the HW structure\n *\n * Setups up the function pointers to no-op functions\n **/\nvoid e1000_init_nvm_ops_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tDEBUGFUNC(\"e1000_init_nvm_ops_generic\");\n\n\t/* Initialize function pointers */\n\tnvm->ops.init_params = e1000_null_ops_generic;\n\tnvm->ops.acquire = e1000_null_ops_generic;\n\tnvm->ops.read = e1000_null_read_nvm;\n\tnvm->ops.release = e1000_null_nvm_generic;\n\tnvm->ops.reload = e1000_reload_nvm_generic;\n\tnvm->ops.update = e1000_null_ops_generic;\n\tnvm->ops.valid_led_default = e1000_null_led_default;\n\tnvm->ops.validate = e1000_null_ops_generic;\n\tnvm->ops.write = e1000_null_write_nvm;\n}\n\n/**\n * e1000_null_nvm_read - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_read_nvm(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\tu16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,\n\t\t\tu16 E1000_UNUSEDARG *c)\n{\n\tDEBUGFUNC(\"e1000_null_read_nvm\");\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_nvm_generic - No-op function, return void\n * @hw: pointer to the HW structure\n **/\nvoid e1000_null_nvm_generic(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_null_nvm_generic\");\n\treturn;\n}\n\n/**\n * e1000_null_led_default - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_led_default(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u16 E1000_UNUSEDARG *data)\n{\n\tDEBUGFUNC(\"e1000_null_led_default\");\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_write_nvm - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_write_nvm(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u16 E1000_UNUSEDARG a, u16 E1000_UNUSEDARG b,\n\t\t\t u16 E1000_UNUSEDARG *c)\n{\n\tDEBUGFUNC(\"e1000_null_write_nvm\");\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_raise_eec_clk - Raise EEPROM clock\n * @hw: pointer to the HW structure\n * @eecd: pointer to the EEPROM\n *\n * Enable/Raise the EEPROM clock bit.\n **/\nstatic void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)\n{\n\t*eecd = *eecd | E1000_EECD_SK;\n\tE1000_WRITE_REG(hw, E1000_EECD, *eecd);\n\tE1000_WRITE_FLUSH(hw);\n\tusec_delay(hw->nvm.delay_usec);\n}\n\n/**\n * e1000_lower_eec_clk - Lower EEPROM clock\n * @hw: pointer to the HW structure\n * @eecd: pointer to the EEPROM\n *\n * Clear/Lower the EEPROM clock bit.\n **/\nstatic void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)\n{\n\t*eecd = *eecd & ~E1000_EECD_SK;\n\tE1000_WRITE_REG(hw, E1000_EECD, *eecd);\n\tE1000_WRITE_FLUSH(hw);\n\tusec_delay(hw->nvm.delay_usec);\n}\n\n/**\n * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM\n * @hw: pointer to the HW structure\n * @data: data to send to the EEPROM\n * @count: number of bits to shift out\n *\n * We need to shift 'count' bits out to the EEPROM. So, the value in the\n * \"data\" parameter will be shifted out to the EEPROM one bit at a time.\n * In order to do this, \"data\" must be broken down into bits.\n **/\nstatic void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\tu32 mask;\n\n\tDEBUGFUNC(\"e1000_shift_out_eec_bits\");\n\n\tmask = 0x01 << (count - 1);\n\tif (nvm->type == e1000_nvm_eeprom_spi)\n\t\teecd |= E1000_EECD_DO;\n\n\tdo {\n\t\teecd &= ~E1000_EECD_DI;\n\n\t\tif (data & mask)\n\t\t\teecd |= E1000_EECD_DI;\n\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tE1000_WRITE_FLUSH(hw);\n\n\t\tusec_delay(nvm->delay_usec);\n\n\t\te1000_raise_eec_clk(hw, &eecd);\n\t\te1000_lower_eec_clk(hw, &eecd);\n\n\t\tmask >>= 1;\n\t} while (mask);\n\n\teecd &= ~E1000_EECD_DI;\n\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n}\n\n/**\n * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM\n * @hw: pointer to the HW structure\n * @count: number of bits to shift in\n *\n * In order to read a register from the EEPROM, we need to shift 'count' bits\n * in from the EEPROM. Bits are \"shifted in\" by raising the clock input to\n * the EEPROM (setting the SK bit), and then reading the value of the data out\n * \"DO\" bit. During this \"shifting in\" process the data in \"DI\" bit should\n * always be clear.\n **/\nstatic u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)\n{\n\tu32 eecd;\n\tu32 i;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_shift_in_eec_bits\");\n\n\teecd = E1000_READ_REG(hw, E1000_EECD);\n\n\teecd &= ~(E1000_EECD_DO | E1000_EECD_DI);\n\tdata = 0;\n\n\tfor (i = 0; i < count; i++) {\n\t\tdata <<= 1;\n\t\te1000_raise_eec_clk(hw, &eecd);\n\n\t\teecd = E1000_READ_REG(hw, E1000_EECD);\n\n\t\teecd &= ~E1000_EECD_DI;\n\t\tif (eecd & E1000_EECD_DO)\n\t\t\tdata |= 1;\n\n\t\te1000_lower_eec_clk(hw, &eecd);\n\t}\n\n\treturn data;\n}\n\n/**\n * e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion\n * @hw: pointer to the HW structure\n * @ee_reg: EEPROM flag for polling\n *\n * Polls the EEPROM status bit for either read or write completion based\n * upon the value of 'ee_reg'.\n **/\ns32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)\n{\n\tu32 attempts = 100000;\n\tu32 i, reg = 0;\n\n\tDEBUGFUNC(\"e1000_poll_eerd_eewr_done\");\n\n\tfor (i = 0; i < attempts; i++) {\n\t\tif (ee_reg == E1000_NVM_POLL_READ)\n\t\t\treg = E1000_READ_REG(hw, E1000_EERD);\n\t\telse\n\t\t\treg = E1000_READ_REG(hw, E1000_EEWR);\n\n\t\tif (reg & E1000_NVM_RW_REG_DONE)\n\t\t\treturn E1000_SUCCESS;\n\n\t\tusec_delay(5);\n\t}\n\n\treturn -E1000_ERR_NVM;\n}\n\n/**\n * e1000_acquire_nvm_generic - Generic request for access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Set the EEPROM access request bit and wait for EEPROM access grant bit.\n * Return successful if access grant bit set, else clear the request for\n * EEPROM access and return -E1000_ERR_NVM (-1).\n **/\ns32 e1000_acquire_nvm_generic(struct e1000_hw *hw)\n{\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\ts32 timeout = E1000_NVM_GRANT_ATTEMPTS;\n\n\tDEBUGFUNC(\"e1000_acquire_nvm_generic\");\n\n\tE1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);\n\teecd = E1000_READ_REG(hw, E1000_EECD);\n\n\twhile (timeout) {\n\t\tif (eecd & E1000_EECD_GNT)\n\t\t\tbreak;\n\t\tusec_delay(5);\n\t\teecd = E1000_READ_REG(hw, E1000_EECD);\n\t\ttimeout--;\n\t}\n\n\tif (!timeout) {\n\t\teecd &= ~E1000_EECD_REQ;\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tDEBUGOUT(\"Could not acquire NVM grant\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_standby_nvm - Return EEPROM to standby state\n * @hw: pointer to the HW structure\n *\n * Return the EEPROM to a standby state.\n **/\nstatic void e1000_standby_nvm(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\n\tDEBUGFUNC(\"e1000_standby_nvm\");\n\n\tif (nvm->type == e1000_nvm_eeprom_spi) {\n\t\t/* Toggle CS to flush commands */\n\t\teecd |= E1000_EECD_CS;\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tusec_delay(nvm->delay_usec);\n\t\teecd &= ~E1000_EECD_CS;\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tusec_delay(nvm->delay_usec);\n\t}\n}\n\n/**\n * e1000_stop_nvm - Terminate EEPROM command\n * @hw: pointer to the HW structure\n *\n * Terminates the current command by inverting the EEPROM's chip select pin.\n **/\nstatic void e1000_stop_nvm(struct e1000_hw *hw)\n{\n\tu32 eecd;\n\n\tDEBUGFUNC(\"e1000_stop_nvm\");\n\n\teecd = E1000_READ_REG(hw, E1000_EECD);\n\tif (hw->nvm.type == e1000_nvm_eeprom_spi) {\n\t\t/* Pull CS high */\n\t\teecd |= E1000_EECD_CS;\n\t\te1000_lower_eec_clk(hw, &eecd);\n\t}\n}\n\n/**\n * e1000_release_nvm_generic - Release exclusive access to EEPROM\n * @hw: pointer to the HW structure\n *\n * Stop any current commands to the EEPROM and clear the EEPROM request bit.\n **/\nvoid e1000_release_nvm_generic(struct e1000_hw *hw)\n{\n\tu32 eecd;\n\n\tDEBUGFUNC(\"e1000_release_nvm_generic\");\n\n\te1000_stop_nvm(hw);\n\n\teecd = E1000_READ_REG(hw, E1000_EECD);\n\teecd &= ~E1000_EECD_REQ;\n\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n}\n\n/**\n * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write\n * @hw: pointer to the HW structure\n *\n * Setups the EEPROM for reading and writing.\n **/\nstatic s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 eecd = E1000_READ_REG(hw, E1000_EECD);\n\tu8 spi_stat_reg;\n\n\tDEBUGFUNC(\"e1000_ready_nvm_eeprom\");\n\n\tif (nvm->type == e1000_nvm_eeprom_spi) {\n\t\tu16 timeout = NVM_MAX_RETRY_SPI;\n\n\t\t/* Clear SK and CS */\n\t\teecd &= ~(E1000_EECD_CS | E1000_EECD_SK);\n\t\tE1000_WRITE_REG(hw, E1000_EECD, eecd);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tusec_delay(1);\n\n\t\t/* Read \"Status Register\" repeatedly until the LSB is cleared.\n\t\t * The EEPROM will signal that the command has been completed\n\t\t * by clearing bit 0 of the internal status register. If it's\n\t\t * not cleared within 'timeout', then error out.\n\t\t */\n\t\twhile (timeout) {\n\t\t\te1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,\n\t\t\t\t\t\t hw->nvm.opcode_bits);\n\t\t\tspi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);\n\t\t\tif (!(spi_stat_reg & NVM_STATUS_RDY_SPI))\n\t\t\t\tbreak;\n\n\t\t\tusec_delay(5);\n\t\t\te1000_standby_nvm(hw);\n\t\t\ttimeout--;\n\t\t}\n\n\t\tif (!timeout) {\n\t\t\tDEBUGOUT(\"SPI NVM Status error\\n\");\n\t\t\treturn -E1000_ERR_NVM;\n\t\t}\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_nvm_spi - Read EEPROM's using SPI\n * @hw: pointer to the HW structure\n * @offset: offset of word in the EEPROM to read\n * @words: number of words to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM.\n **/\ns32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 i = 0;\n\ts32 ret_val;\n\tu16 word_in;\n\tu8 read_opcode = NVM_READ_OPCODE_SPI;\n\n\tDEBUGFUNC(\"e1000_read_nvm_spi\");\n\n\t/* A check for invalid values: offset too large, too many words,\n\t * and not enough words.\n\t */\n\tif ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\tret_val = nvm->ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_ready_nvm_eeprom(hw);\n\tif (ret_val)\n\t\tgoto release;\n\n\te1000_standby_nvm(hw);\n\n\tif ((nvm->address_bits == 8) && (offset >= 128))\n\t\tread_opcode |= NVM_A8_OPCODE_SPI;\n\n\t/* Send the READ command (opcode + addr) */\n\te1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);\n\te1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);\n\n\t/* Read the data. SPI NVMs increment the address with each byte\n\t * read and will roll over if reading beyond the end. This allows\n\t * us to read the whole NVM from any offset\n\t */\n\tfor (i = 0; i < words; i++) {\n\t\tword_in = e1000_shift_in_eec_bits(hw, 16);\n\t\tdata[i] = (word_in >> 8) | (word_in << 8);\n\t}\n\nrelease:\n\tnvm->ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_nvm_eerd - Reads EEPROM using EERD register\n * @hw: pointer to the HW structure\n * @offset: offset of word in the EEPROM to read\n * @words: number of words to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM using the EERD register.\n **/\ns32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\tu32 i, eerd = 0;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_read_nvm_eerd\");\n\n\t/* A check for invalid values: offset too large, too many words,\n\t * too many words for the offset, and not enough words.\n\t */\n\tif ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\tfor (i = 0; i < words; i++) {\n\t\teerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +\n\t\t E1000_NVM_RW_REG_START;\n\n\t\tE1000_WRITE_REG(hw, E1000_EERD, eerd);\n\t\tret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);\n\t\tif (ret_val)\n\t\t\tbreak;\n\n\t\tdata[i] = (E1000_READ_REG(hw, E1000_EERD) >>\n\t\t\t E1000_NVM_RW_REG_DATA);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_nvm_spi - Write to EEPROM using SPI\n * @hw: pointer to the HW structure\n * @offset: offset within the EEPROM to be written to\n * @words: number of words to write\n * @data: 16 bit word(s) to be written to the EEPROM\n *\n * Writes data to EEPROM at offset using SPI interface.\n *\n * If e1000_update_nvm_checksum is not called after this function , the\n * EEPROM will most likely contain an invalid checksum.\n **/\ns32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)\n{\n\tstruct e1000_nvm_info *nvm = &hw->nvm;\n\ts32 ret_val = -E1000_ERR_NVM;\n\tu16 widx = 0;\n\n\tDEBUGFUNC(\"e1000_write_nvm_spi\");\n\n\t/* A check for invalid values: offset too large, too many words,\n\t * and not enough words.\n\t */\n\tif ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||\n\t (words == 0)) {\n\t\tDEBUGOUT(\"nvm parameter(s) out of bounds\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\twhile (widx < words) {\n\t\tu8 write_opcode = NVM_WRITE_OPCODE_SPI;\n\n\t\tret_val = nvm->ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = e1000_ready_nvm_eeprom(hw);\n\t\tif (ret_val) {\n\t\t\tnvm->ops.release(hw);\n\t\t\treturn ret_val;\n\t\t}\n\n\t\te1000_standby_nvm(hw);\n\n\t\t/* Send the WRITE ENABLE command (8 bit opcode) */\n\t\te1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,\n\t\t\t\t\t nvm->opcode_bits);\n\n\t\te1000_standby_nvm(hw);\n\n\t\t/* Some SPI eeproms use the 8th address bit embedded in the\n\t\t * opcode\n\t\t */\n\t\tif ((nvm->address_bits == 8) && (offset >= 128))\n\t\t\twrite_opcode |= NVM_A8_OPCODE_SPI;\n\n\t\t/* Send the Write command (8-bit opcode + addr) */\n\t\te1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);\n\t\te1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),\n\t\t\t\t\t nvm->address_bits);\n\n\t\t/* Loop to allow for up to whole page write of eeprom */\n\t\twhile (widx < words) {\n\t\t\tu16 word_out = data[widx];\n\t\t\tword_out = (word_out >> 8) | (word_out << 8);\n\t\t\te1000_shift_out_eec_bits(hw, word_out, 16);\n\t\t\twidx++;\n\n\t\t\tif ((((offset + widx) * 2) % nvm->page_size) == 0) {\n\t\t\t\te1000_standby_nvm(hw);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tmsec_delay(10);\n\t\tnvm->ops.release(hw);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_pba_string_generic - Read device part number\n * @hw: pointer to the HW structure\n * @pba_num: pointer to device part number\n * @pba_num_size: size of part number buffer\n *\n * Reads the product board assembly (PBA) number from the EEPROM and stores\n * the value in pba_num.\n **/\ns32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,\n\t\t\t\t u32 pba_num_size)\n{\n\ts32 ret_val;\n\tu16 nvm_data;\n\tu16 pba_ptr;\n\tu16 offset;\n\tu16 length;\n\n\tDEBUGFUNC(\"e1000_read_pba_string_generic\");\n\n\tif (pba_num == NULL) {\n\t\tDEBUGOUT(\"PBA string buffer was null\\n\");\n\t\treturn -E1000_ERR_INVALID_ARGUMENT;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\t/* if nvm_data is not ptr guard the PBA must be in legacy format which\n\t * means pba_ptr is actually our second data word for the PBA number\n\t * and we can decode it into an ascii string\n\t */\n\tif (nvm_data != NVM_PBA_PTR_GUARD) {\n\t\tDEBUGOUT(\"NVM PBA number is not stored as string\\n\");\n\n\t\t/* make sure callers buffer is big enough to store the PBA */\n\t\tif (pba_num_size < E1000_PBANUM_LENGTH) {\n\t\t\tDEBUGOUT(\"PBA string buffer too small\\n\");\n\t\t\treturn E1000_ERR_NO_SPACE;\n\t\t}\n\n\t\t/* extract hex string from data and pba_ptr */\n\t\tpba_num[0] = (nvm_data >> 12) & 0xF;\n\t\tpba_num[1] = (nvm_data >> 8) & 0xF;\n\t\tpba_num[2] = (nvm_data >> 4) & 0xF;\n\t\tpba_num[3] = nvm_data & 0xF;\n\t\tpba_num[4] = (pba_ptr >> 12) & 0xF;\n\t\tpba_num[5] = (pba_ptr >> 8) & 0xF;\n\t\tpba_num[6] = '-';\n\t\tpba_num[7] = 0;\n\t\tpba_num[8] = (pba_ptr >> 4) & 0xF;\n\t\tpba_num[9] = pba_ptr & 0xF;\n\n\t\t/* put a null character on the end of our string */\n\t\tpba_num[10] = '\\0';\n\n\t\t/* switch all the data but the '-' to hex char */\n\t\tfor (offset = 0; offset < 10; offset++) {\n\t\t\tif (pba_num[offset] < 0xA)\n\t\t\t\tpba_num[offset] += '0';\n\t\t\telse if (pba_num[offset] < 0x10)\n\t\t\t\tpba_num[offset] += 'A' - 0xA;\n\t\t}\n\n\t\treturn E1000_SUCCESS;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif (length == 0xFFFF || length == 0) {\n\t\tDEBUGOUT(\"NVM PBA number section invalid length\\n\");\n\t\treturn -E1000_ERR_NVM_PBA_SECTION;\n\t}\n\t/* check if pba_num buffer is big enough */\n\tif (pba_num_size < (((u32)length * 2) - 1)) {\n\t\tDEBUGOUT(\"PBA string buffer too small\\n\");\n\t\treturn -E1000_ERR_NO_SPACE;\n\t}\n\n\t/* trim pba length from start of string */\n\tpba_ptr++;\n\tlength--;\n\n\tfor (offset = 0; offset < length; offset++) {\n\t\tret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t\tpba_num[offset * 2] = (u8)(nvm_data >> 8);\n\t\tpba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);\n\t}\n\tpba_num[offset * 2] = '\\0';\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_pba_length_generic - Read device part number length\n * @hw: pointer to the HW structure\n * @pba_num_size: size of part number buffer\n *\n * Reads the product board assembly (PBA) number length from the EEPROM and\n * stores the value in pba_num_size.\n **/\ns32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)\n{\n\ts32 ret_val;\n\tu16 nvm_data;\n\tu16 pba_ptr;\n\tu16 length;\n\n\tDEBUGFUNC(\"e1000_read_pba_length_generic\");\n\n\tif (pba_num_size == NULL) {\n\t\tDEBUGOUT(\"PBA buffer size was null\\n\");\n\t\treturn -E1000_ERR_INVALID_ARGUMENT;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\t /* if data is not ptr guard the PBA must be in legacy format */\n\tif (nvm_data != NVM_PBA_PTR_GUARD) {\n\t\t*pba_num_size = E1000_PBANUM_LENGTH;\n\t\treturn E1000_SUCCESS;\n\t}\n\n\tret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif (length == 0xFFFF || length == 0) {\n\t\tDEBUGOUT(\"NVM PBA number section invalid length\\n\");\n\t\treturn -E1000_ERR_NVM_PBA_SECTION;\n\t}\n\n\t/* Convert from length in u16 values to u8 chars, add 1 for NULL,\n\t * and subtract 2 because length field is included in length.\n\t */\n\t*pba_num_size = ((u32)length * 2) - 1;\n\n\treturn E1000_SUCCESS;\n}\n\n\n\n\n\n/**\n * e1000_read_mac_addr_generic - Read device MAC address\n * @hw: pointer to the HW structure\n *\n * Reads the device MAC address from the EEPROM and stores the value.\n * Since devices with two ports use the same EEPROM, we increment the\n * last bit in the MAC address for the second port.\n **/\ns32 e1000_read_mac_addr_generic(struct e1000_hw *hw)\n{\n\tu32 rar_high;\n\tu32 rar_low;\n\tu16 i;\n\n\trar_high = E1000_READ_REG(hw, E1000_RAH(0));\n\trar_low = E1000_READ_REG(hw, E1000_RAL(0));\n\n\tfor (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)\n\t\thw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));\n\n\tfor (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)\n\t\thw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));\n\n\tfor (i = 0; i < ETH_ADDR_LEN; i++)\n\t\thw->mac.addr[i] = hw->mac.perm_addr[i];\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_validate_nvm_checksum_generic - Validate EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Calculates the EEPROM checksum by reading/adding each word of the EEPROM\n * and then verifies that the sum of the EEPROM is equal to 0xBABA.\n **/\ns32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 checksum = 0;\n\tu16 i, nvm_data;\n\n\tDEBUGFUNC(\"e1000_validate_nvm_checksum_generic\");\n\n\tfor (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {\n\t\tret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t\tchecksum += nvm_data;\n\t}\n\n\tif (checksum != (u16) NVM_SUM) {\n\t\tDEBUGOUT(\"NVM Checksum Invalid\\n\");\n\t\treturn -E1000_ERR_NVM;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_update_nvm_checksum_generic - Update EEPROM checksum\n * @hw: pointer to the HW structure\n *\n * Updates the EEPROM checksum by reading/adding each word of the EEPROM\n * up to the checksum. Then calculates the EEPROM checksum and writes the\n * value to the EEPROM.\n **/\ns32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 checksum = 0;\n\tu16 i, nvm_data;\n\n\tDEBUGFUNC(\"e1000_update_nvm_checksum\");\n\n\tfor (i = 0; i < NVM_CHECKSUM_REG; i++) {\n\t\tret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"NVM Read Error while updating checksum.\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t\tchecksum += nvm_data;\n\t}\n\tchecksum = (u16) NVM_SUM - checksum;\n\tret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);\n\tif (ret_val)\n\t\tDEBUGOUT(\"NVM Write Error while updating checksum.\\n\");\n\n\treturn ret_val;\n}\n\n/**\n * e1000_reload_nvm_generic - Reloads EEPROM\n * @hw: pointer to the HW structure\n *\n * Reloads the EEPROM by setting the \"Reinitialize from EEPROM\" bit in the\n * extended control register.\n **/\nstatic void e1000_reload_nvm_generic(struct e1000_hw *hw)\n{\n\tu32 ctrl_ext;\n\n\tDEBUGFUNC(\"e1000_reload_nvm_generic\");\n\n\tusec_delay(10);\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tctrl_ext |= E1000_CTRL_EXT_EE_RST;\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * e1000_get_fw_version - Get firmware version information\n * @hw: pointer to the HW structure\n * @fw_vers: pointer to output version structure\n *\n * unsupported/not present features return 0 in version structure\n **/\nvoid e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)\n{\n\tu16 eeprom_verh, eeprom_verl, etrack_test, fw_version;\n\tu8 q, hval, rem, result;\n\tu16 comb_verh, comb_verl, comb_offset;\n\n\tmemset(fw_vers, 0, sizeof(struct e1000_fw_version));\n\n\t/* basic eeprom version numbers, bits used vary by part and by tool\n\t * used to create the nvm images */\n\t/* Check which data format we have */\n\thw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);\n\tswitch (hw->mac.type) {\n\tcase e1000_i211:\n\t\te1000_read_invm_version(hw, fw_vers);\n\t\treturn;\n\tcase e1000_82575:\n\tcase e1000_82576:\n\tcase e1000_82580:\n\t\t/* Use this format, unless EETRACK ID exists,\n\t\t * then use alternate format\n\t\t */\n\t\tif ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {\n\t\t\thw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);\n\t\t\tfw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)\n\t\t\t\t\t >> NVM_MAJOR_SHIFT;\n\t\t\tfw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)\n\t\t\t\t\t >> NVM_MINOR_SHIFT;\n\t\t\tfw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);\n\t\t\tgoto etrack_id;\n\t\t}\n\t\tbreak;\n\tcase e1000_i210:\n\t\tif (!(e1000_get_flash_presence_i210(hw))) {\n\t\t\te1000_read_invm_version(hw, fw_vers);\n\t\t\treturn;\n\t\t}\n\t\t/* fall through */\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\t/* find combo image version */\n\t\thw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);\n\t\tif ((comb_offset != 0x0) &&\n\t\t (comb_offset != NVM_VER_INVALID)) {\n\n\t\t\thw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset\n\t\t\t\t\t + 1), 1, &comb_verh);\n\t\t\thw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),\n\t\t\t\t\t 1, &comb_verl);\n\n\t\t\t/* get Option Rom version if it exists and is valid */\n\t\t\tif ((comb_verh && comb_verl) &&\n\t\t\t ((comb_verh != NVM_VER_INVALID) &&\n\t\t\t (comb_verl != NVM_VER_INVALID))) {\n\n\t\t\t\tfw_vers->or_valid = true;\n\t\t\t\tfw_vers->or_major =\n\t\t\t\t\tcomb_verl >> NVM_COMB_VER_SHFT;\n\t\t\t\tfw_vers->or_build =\n\t\t\t\t\t(comb_verl << NVM_COMB_VER_SHFT)\n\t\t\t\t\t| (comb_verh >> NVM_COMB_VER_SHFT);\n\t\t\t\tfw_vers->or_patch =\n\t\t\t\t\tcomb_verh & NVM_COMB_VER_MASK;\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\thw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);\n\tfw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)\n\t\t\t >> NVM_MAJOR_SHIFT;\n\n\t/* check for old style version format in newer images*/\n\tif ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {\n\t\teeprom_verl = (fw_version & NVM_COMB_VER_MASK);\n\t} else {\n\t\teeprom_verl = (fw_version & NVM_MINOR_MASK)\n\t\t\t\t>> NVM_MINOR_SHIFT;\n\t}\n\t/* Convert minor value to hex before assigning to output struct\n\t * Val to be converted will not be higher than 99, per tool output\n\t */\n\tq = eeprom_verl / NVM_HEX_CONV;\n\thval = q * NVM_HEX_TENS;\n\trem = eeprom_verl % NVM_HEX_CONV;\n\tresult = hval + rem;\n\tfw_vers->eep_minor = result;\n\netrack_id:\n\tif ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {\n\t\thw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);\n\t\thw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);\n\t\tfw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)\n\t\t\t| eeprom_verl;\n\t}\n\treturn;\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_nvm.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _E1000_NVM_H_\n#define _E1000_NVM_H_\n\n\nstruct e1000_fw_version {\n\tu32 etrack_id;\n\tu16 eep_major;\n\tu16 eep_minor;\n\tu16 eep_build;\n\n\tu8 invm_major;\n\tu8 invm_minor;\n\tu8 invm_img_type;\n\n\tbool or_valid;\n\tu16 or_major;\n\tu16 or_build;\n\tu16 or_patch;\n};\n\n\nvoid e1000_init_nvm_ops_generic(struct e1000_hw *hw);\ns32 e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c);\nvoid e1000_null_nvm_generic(struct e1000_hw *hw);\ns32 e1000_null_led_default(struct e1000_hw *hw, u16 *data);\ns32 e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c);\ns32 e1000_acquire_nvm_generic(struct e1000_hw *hw);\n\ns32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);\ns32 e1000_read_mac_addr_generic(struct e1000_hw *hw);\ns32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,\n\t\t\t\t u32 pba_num_size);\ns32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size);\ns32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);\ns32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t u16 *data);\ns32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data);\ns32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw);\ns32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,\n\t\t\t u16 *data);\ns32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw);\nvoid e1000_release_nvm_generic(struct e1000_hw *hw);\nvoid e1000_get_fw_version(struct e1000_hw *hw,\n\t\t\t struct e1000_fw_version *fw_vers);\n\n#define E1000_STM_OPCODE\t0xDB00\n\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_osdep.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n\n/* glue for the OS independent part of e1000\n * includes register access macros\n */\n\n#ifndef _E1000_OSDEP_H_\n#define _E1000_OSDEP_H_\n\n#include \n#include \n#include \n#include \n#include \n#include \"kcompat.h\"\n\n#ifndef __INTEL_COMPILER\n#pragma GCC diagnostic ignored \"-Wunused-function\"\n#endif\n\n#define usec_delay(x) udelay(x)\n#define usec_delay_irq(x) udelay(x)\n#ifndef msec_delay\n#define msec_delay(x) do { \\\n\t/* Don't mdelay in interrupt context! */ \\\n\tif (in_interrupt()) \\\n\t\tBUG(); \\\n\telse \\\n\t\tmsleep(x); \\\n} while (0)\n\n/* Some workarounds require millisecond delays and are run during interrupt\n * context. Most notably, when establishing link, the phy may need tweaking\n * but cannot process phy register reads/writes faster than millisecond\n * intervals...and we establish link due to a \"link status change\" interrupt.\n */\n#define msec_delay_irq(x) mdelay(x)\n#endif\n\n#define PCI_COMMAND_REGISTER PCI_COMMAND\n#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE\n#define ETH_ADDR_LEN ETH_ALEN\n\n#ifdef __BIG_ENDIAN\n#define E1000_BIG_ENDIAN __BIG_ENDIAN\n#endif\n\n\n#ifdef DEBUG\n#define DEBUGOUT(S) printk(KERN_DEBUG S)\n#define DEBUGOUT1(S, A...) printk(KERN_DEBUG S, ## A)\n#else\n#define DEBUGOUT(S)\n#define DEBUGOUT1(S, A...)\n#endif\n\n#ifdef DEBUG_FUNC\n#define DEBUGFUNC(F) DEBUGOUT(F \"\\n\")\n#else\n#define DEBUGFUNC(F)\n#endif\n#define DEBUGOUT2 DEBUGOUT1\n#define DEBUGOUT3 DEBUGOUT2\n#define DEBUGOUT7 DEBUGOUT3\n\n#define E1000_REGISTER(a, reg) reg\n\n#define E1000_WRITE_REG(a, reg, value) ( \\\n writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg))))\n\n#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_REGISTER(a, reg)))\n\n#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \\\n writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2))))\n\n#define E1000_READ_REG_ARRAY(a, reg, offset) ( \\\n readl((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))\n\n#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY\n#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY\n\n#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \\\n writew((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1))))\n\n#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \\\n readw((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1)))\n\n#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \\\n writeb((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + (offset))))\n\n#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \\\n readb((a)->hw_addr + E1000_REGISTER(a, reg) + (offset)))\n\n#define E1000_WRITE_REG_IO(a, reg, offset) do { \\\n outl(reg, ((a)->io_base)); \\\n outl(offset, ((a)->io_base + 4)); } while (0)\n\n#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)\n\n#define E1000_WRITE_FLASH_REG(a, reg, value) ( \\\n writel((value), ((a)->flash_address + reg)))\n\n#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \\\n writew((value), ((a)->flash_address + reg)))\n\n#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))\n\n#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))\n\n#endif /* _E1000_OSDEP_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_phy.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"e1000_api.h\"\n\nstatic s32 e1000_wait_autoneg(struct e1000_hw *hw);\n/* Cable length tables */\nstatic const u16 e1000_m88_cable_length_table[] = {\n\t0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };\n#define M88E1000_CABLE_LENGTH_TABLE_SIZE \\\n\t\t(sizeof(e1000_m88_cable_length_table) / \\\n\t\t sizeof(e1000_m88_cable_length_table[0]))\n\nstatic const u16 e1000_igp_2_cable_length_table[] = {\n\t0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,\n\t6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,\n\t26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,\n\t44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,\n\t66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,\n\t87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,\n\t100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,\n\t124};\n#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \\\n\t\t(sizeof(e1000_igp_2_cable_length_table) / \\\n\t\t sizeof(e1000_igp_2_cable_length_table[0]))\n\n/**\n * e1000_init_phy_ops_generic - Initialize PHY function pointers\n * @hw: pointer to the HW structure\n *\n * Setups up the function pointers to no-op functions\n **/\nvoid e1000_init_phy_ops_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tDEBUGFUNC(\"e1000_init_phy_ops_generic\");\n\n\t/* Initialize function pointers */\n\tphy->ops.init_params = e1000_null_ops_generic;\n\tphy->ops.acquire = e1000_null_ops_generic;\n\tphy->ops.check_polarity = e1000_null_ops_generic;\n\tphy->ops.check_reset_block = e1000_null_ops_generic;\n\tphy->ops.commit = e1000_null_ops_generic;\n\tphy->ops.force_speed_duplex = e1000_null_ops_generic;\n\tphy->ops.get_cfg_done = e1000_null_ops_generic;\n\tphy->ops.get_cable_length = e1000_null_ops_generic;\n\tphy->ops.get_info = e1000_null_ops_generic;\n\tphy->ops.set_page = e1000_null_set_page;\n\tphy->ops.read_reg = e1000_null_read_reg;\n\tphy->ops.read_reg_locked = e1000_null_read_reg;\n\tphy->ops.read_reg_page = e1000_null_read_reg;\n\tphy->ops.release = e1000_null_phy_generic;\n\tphy->ops.reset = e1000_null_ops_generic;\n\tphy->ops.set_d0_lplu_state = e1000_null_lplu_state;\n\tphy->ops.set_d3_lplu_state = e1000_null_lplu_state;\n\tphy->ops.write_reg = e1000_null_write_reg;\n\tphy->ops.write_reg_locked = e1000_null_write_reg;\n\tphy->ops.write_reg_page = e1000_null_write_reg;\n\tphy->ops.power_up = e1000_null_phy_generic;\n\tphy->ops.power_down = e1000_null_phy_generic;\n\tphy->ops.read_i2c_byte = e1000_read_i2c_byte_null;\n\tphy->ops.write_i2c_byte = e1000_write_i2c_byte_null;\n}\n\n/**\n * e1000_null_set_page - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\tu16 E1000_UNUSEDARG data)\n{\n\tDEBUGFUNC(\"e1000_null_set_page\");\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_read_reg - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\tu32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)\n{\n\tDEBUGFUNC(\"e1000_null_read_reg\");\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_phy_generic - No-op function, return void\n * @hw: pointer to the HW structure\n **/\nvoid e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_null_phy_generic\");\n\treturn;\n}\n\n/**\n * e1000_null_lplu_state - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t bool E1000_UNUSEDARG active)\n{\n\tDEBUGFUNC(\"e1000_null_lplu_state\");\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_null_write_reg - No-op function, return 0\n * @hw: pointer to the HW structure\n **/\ns32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)\n{\n\tDEBUGFUNC(\"e1000_null_write_reg\");\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_i2c_byte_null - No-op function, return 0\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @dev_addr: device address\n * @data: data value read\n *\n **/\ns32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u8 E1000_UNUSEDARG byte_offset,\n\t\t\t u8 E1000_UNUSEDARG dev_addr,\n\t\t\t u8 E1000_UNUSEDARG *data)\n{\n\tDEBUGFUNC(\"e1000_read_i2c_byte_null\");\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_i2c_byte_null - No-op function, return 0\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @dev_addr: device address\n * @data: data value to write\n *\n **/\ns32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,\n\t\t\t u8 E1000_UNUSEDARG byte_offset,\n\t\t\t u8 E1000_UNUSEDARG dev_addr,\n\t\t\t u8 E1000_UNUSEDARG data)\n{\n\tDEBUGFUNC(\"e1000_write_i2c_byte_null\");\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_check_reset_block_generic - Check if PHY reset is blocked\n * @hw: pointer to the HW structure\n *\n * Read the PHY management control register and check whether a PHY reset\n * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise\n * return E1000_BLK_PHY_RESET (12).\n **/\ns32 e1000_check_reset_block_generic(struct e1000_hw *hw)\n{\n\tu32 manc;\n\n\tDEBUGFUNC(\"e1000_check_reset_block\");\n\n\tmanc = E1000_READ_REG(hw, E1000_MANC);\n\n\treturn (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?\n\t E1000_BLK_PHY_RESET : E1000_SUCCESS;\n}\n\n/**\n * e1000_get_phy_id - Retrieve the PHY ID and revision\n * @hw: pointer to the HW structure\n *\n * Reads the PHY registers and stores the PHY ID and possibly the PHY\n * revision in the hardware structure.\n **/\ns32 e1000_get_phy_id(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 phy_id;\n\n\tDEBUGFUNC(\"e1000_get_phy_id\");\n\n\tif (!phy->ops.read_reg)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy->id = (u32)(phy_id << 16);\n\tusec_delay(20);\n\tret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy->id |= (u32)(phy_id & PHY_REVISION_MASK);\n\tphy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);\n\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_reset_dsp_generic - Reset PHY DSP\n * @hw: pointer to the HW structure\n *\n * Reset the digital signal processor.\n **/\ns32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_phy_reset_dsp_generic\");\n\n\tif (!hw->phy.ops.write_reg)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);\n}\n\n/**\n * e1000_read_phy_reg_mdic - Read MDI control register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the MDI control register in the PHY at offset and stores the\n * information read to data.\n **/\ns32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tu32 i, mdic = 0;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_mdic\");\n\n\tif (offset > MAX_PHY_REG_ADDRESS) {\n\t\tDEBUGOUT1(\"PHY Address %d is out of range\\n\", offset);\n\t\treturn -E1000_ERR_PARAM;\n\t}\n\n\t/* Set up Op-code, Phy Address, and register offset in the MDI\n\t * Control register. The MAC will take care of interfacing with the\n\t * PHY to retrieve the desired data.\n\t */\n\tmdic = ((offset << E1000_MDIC_REG_SHIFT) |\n\t\t(phy->addr << E1000_MDIC_PHY_SHIFT) |\n\t\t(E1000_MDIC_OP_READ));\n\n\tE1000_WRITE_REG(hw, E1000_MDIC, mdic);\n\n\t/* Poll the ready bit to see if the MDI read completed\n\t * Increasing the time out as testing showed failures with\n\t * the lower time out\n\t */\n\tfor (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {\n\t\tusec_delay_irq(50);\n\t\tmdic = E1000_READ_REG(hw, E1000_MDIC);\n\t\tif (mdic & E1000_MDIC_READY)\n\t\t\tbreak;\n\t}\n\tif (!(mdic & E1000_MDIC_READY)) {\n\t\tDEBUGOUT(\"MDI Read did not complete\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (mdic & E1000_MDIC_ERROR) {\n\t\tDEBUGOUT(\"MDI Error\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {\n\t\tDEBUGOUT2(\"MDI Read offset error - requested %d, returned %d\\n\",\n\t\t\t offset,\n\t\t\t (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);\n\t\treturn -E1000_ERR_PHY;\n\t}\n\t*data = (u16) mdic;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_phy_reg_mdic - Write MDI control register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write to register at offset\n *\n * Writes data to MDI control register in the PHY at offset.\n **/\ns32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tu32 i, mdic = 0;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_mdic\");\n\n\tif (offset > MAX_PHY_REG_ADDRESS) {\n\t\tDEBUGOUT1(\"PHY Address %d is out of range\\n\", offset);\n\t\treturn -E1000_ERR_PARAM;\n\t}\n\n\t/* Set up Op-code, Phy Address, and register offset in the MDI\n\t * Control register. The MAC will take care of interfacing with the\n\t * PHY to retrieve the desired data.\n\t */\n\tmdic = (((u32)data) |\n\t\t(offset << E1000_MDIC_REG_SHIFT) |\n\t\t(phy->addr << E1000_MDIC_PHY_SHIFT) |\n\t\t(E1000_MDIC_OP_WRITE));\n\n\tE1000_WRITE_REG(hw, E1000_MDIC, mdic);\n\n\t/* Poll the ready bit to see if the MDI read completed\n\t * Increasing the time out as testing showed failures with\n\t * the lower time out\n\t */\n\tfor (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {\n\t\tusec_delay_irq(50);\n\t\tmdic = E1000_READ_REG(hw, E1000_MDIC);\n\t\tif (mdic & E1000_MDIC_READY)\n\t\t\tbreak;\n\t}\n\tif (!(mdic & E1000_MDIC_READY)) {\n\t\tDEBUGOUT(\"MDI Write did not complete\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (mdic & E1000_MDIC_ERROR) {\n\t\tDEBUGOUT(\"MDI Error\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {\n\t\tDEBUGOUT2(\"MDI Write offset error - requested %d, returned %d\\n\",\n\t\t\t offset,\n\t\t\t (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_phy_reg_i2c - Read PHY register using i2c\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the PHY register at offset using the i2c interface and stores the\n * retrieved information in data.\n **/\ns32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tu32 i, i2ccmd = 0;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_i2c\");\n\n\t/* Set up Op-code, Phy Address, and register address in the I2CCMD\n\t * register. The MAC will take care of interfacing with the\n\t * PHY to retrieve the desired data.\n\t */\n\ti2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |\n\t\t (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |\n\t\t (E1000_I2CCMD_OPCODE_READ));\n\n\tE1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);\n\n\t/* Poll the ready bit to see if the I2C read completed */\n\tfor (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {\n\t\tusec_delay(50);\n\t\ti2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);\n\t\tif (i2ccmd & E1000_I2CCMD_READY)\n\t\t\tbreak;\n\t}\n\tif (!(i2ccmd & E1000_I2CCMD_READY)) {\n\t\tDEBUGOUT(\"I2CCMD Read did not complete\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (i2ccmd & E1000_I2CCMD_ERROR) {\n\t\tDEBUGOUT(\"I2CCMD Error bit set\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\t/* Need to byte-swap the 16-bit value. */\n\t*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_phy_reg_i2c - Write PHY register using i2c\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Writes the data to PHY register at the offset using the i2c interface.\n **/\ns32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\tu32 i, i2ccmd = 0;\n\tu16 phy_data_swapped;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_i2c\");\n\n\t/* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/\n\tif ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {\n\t\tDEBUGOUT1(\"PHY I2C Address %d is out of range.\\n\",\n\t\t\t hw->phy.addr);\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\t/* Swap the data bytes for the I2C interface */\n\tphy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);\n\n\t/* Set up Op-code, Phy Address, and register address in the I2CCMD\n\t * register. The MAC will take care of interfacing with the\n\t * PHY to retrieve the desired data.\n\t */\n\ti2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |\n\t\t (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |\n\t\t E1000_I2CCMD_OPCODE_WRITE |\n\t\t phy_data_swapped);\n\n\tE1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);\n\n\t/* Poll the ready bit to see if the I2C read completed */\n\tfor (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {\n\t\tusec_delay(50);\n\t\ti2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);\n\t\tif (i2ccmd & E1000_I2CCMD_READY)\n\t\t\tbreak;\n\t}\n\tif (!(i2ccmd & E1000_I2CCMD_READY)) {\n\t\tDEBUGOUT(\"I2CCMD Write did not complete\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (i2ccmd & E1000_I2CCMD_ERROR) {\n\t\tDEBUGOUT(\"I2CCMD Error bit set\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_sfp_data_byte - Reads SFP module data.\n * @hw: pointer to the HW structure\n * @offset: byte location offset to be read\n * @data: read data buffer pointer\n *\n * Reads one byte from SFP module data stored\n * in SFP resided EEPROM memory or SFP diagnostic area.\n * Function should be called with\n * E1000_I2CCMD_SFP_DATA_ADDR() for SFP module database access\n * E1000_I2CCMD_SFP_DIAG_ADDR() for SFP diagnostics parameters\n * access\n **/\ns32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)\n{\n\tu32 i = 0;\n\tu32 i2ccmd = 0;\n\tu32 data_local = 0;\n\n\tDEBUGFUNC(\"e1000_read_sfp_data_byte\");\n\n\tif (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {\n\t\tDEBUGOUT(\"I2CCMD command address exceeds upper limit\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\t/* Set up Op-code, EEPROM Address,in the I2CCMD\n\t * register. The MAC will take care of interfacing with the\n\t * EEPROM to retrieve the desired data.\n\t */\n\ti2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |\n\t\t E1000_I2CCMD_OPCODE_READ);\n\n\tE1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);\n\n\t/* Poll the ready bit to see if the I2C read completed */\n\tfor (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {\n\t\tusec_delay(50);\n\t\tdata_local = E1000_READ_REG(hw, E1000_I2CCMD);\n\t\tif (data_local & E1000_I2CCMD_READY)\n\t\t\tbreak;\n\t}\n\tif (!(data_local & E1000_I2CCMD_READY)) {\n\t\tDEBUGOUT(\"I2CCMD Read did not complete\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (data_local & E1000_I2CCMD_ERROR) {\n\t\tDEBUGOUT(\"I2CCMD Error bit set\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\t*data = (u8) data_local & 0xFF;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_sfp_data_byte - Writes SFP module data.\n * @hw: pointer to the HW structure\n * @offset: byte location offset to write to\n * @data: data to write\n *\n * Writes one byte to SFP module data stored\n * in SFP resided EEPROM memory or SFP diagnostic area.\n * Function should be called with\n * E1000_I2CCMD_SFP_DATA_ADDR() for SFP module database access\n * E1000_I2CCMD_SFP_DIAG_ADDR() for SFP diagnostics parameters\n * access\n **/\ns32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)\n{\n\tu32 i = 0;\n\tu32 i2ccmd = 0;\n\tu32 data_local = 0;\n\n\tDEBUGFUNC(\"e1000_write_sfp_data_byte\");\n\n\tif (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {\n\t\tDEBUGOUT(\"I2CCMD command address exceeds upper limit\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\t/* The programming interface is 16 bits wide\n\t * so we need to read the whole word first\n\t * then update appropriate byte lane and write\n\t * the updated word back.\n\t */\n\t/* Set up Op-code, EEPROM Address,in the I2CCMD\n\t * register. The MAC will take care of interfacing\n\t * with an EEPROM to write the data given.\n\t */\n\ti2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |\n\t\t E1000_I2CCMD_OPCODE_READ);\n\t/* Set a command to read single word */\n\tE1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);\n\tfor (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {\n\t\tusec_delay(50);\n\t\t/* Poll the ready bit to see if lastly\n\t\t * launched I2C operation completed\n\t\t */\n\t\ti2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);\n\t\tif (i2ccmd & E1000_I2CCMD_READY) {\n\t\t\t/* Check if this is READ or WRITE phase */\n\t\t\tif ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==\n\t\t\t E1000_I2CCMD_OPCODE_READ) {\n\t\t\t\t/* Write the selected byte\n\t\t\t\t * lane and update whole word\n\t\t\t\t */\n\t\t\t\tdata_local = i2ccmd & 0xFF00;\n\t\t\t\tdata_local |= data;\n\t\t\t\ti2ccmd = ((offset <<\n\t\t\t\t\tE1000_I2CCMD_REG_ADDR_SHIFT) |\n\t\t\t\t\tE1000_I2CCMD_OPCODE_WRITE | data_local);\n\t\t\t\tE1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);\n\t\t\t} else {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\tif (!(i2ccmd & E1000_I2CCMD_READY)) {\n\t\tDEBUGOUT(\"I2CCMD Write did not complete\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\tif (i2ccmd & E1000_I2CCMD_ERROR) {\n\t\tDEBUGOUT(\"I2CCMD Error bit set\\n\");\n\t\treturn -E1000_ERR_PHY;\n\t}\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_phy_reg_m88 - Read m88 PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Acquires semaphore, if necessary, then reads the PHY register at offset\n * and storing the retrieved information in data. Release any acquired\n * semaphores before exiting.\n **/\ns32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_m88\");\n\n\tif (!hw->phy.ops.acquire)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t data);\n\n\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_phy_reg_m88 - Write m88 PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Acquires semaphore, if necessary, then writes the data to PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\ns32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\ts32 ret_val;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_m88\");\n\n\tif (!hw->phy.ops.acquire)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t data);\n\n\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_set_page_igp - Set page as on IGP-like PHY(s)\n * @hw: pointer to the HW structure\n * @page: page to set (shifted left when necessary)\n *\n * Sets PHY page required for PHY register access. Assumes semaphore is\n * already acquired. Note, this function sets phy.addr to 1 so the caller\n * must set it appropriately (if necessary) after this function returns.\n **/\ns32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)\n{\n\tDEBUGFUNC(\"e1000_set_page_igp\");\n\n\tDEBUGOUT1(\"Setting page 0x%x\\n\", page);\n\n\thw->phy.addr = 1;\n\n\treturn e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);\n}\n\n/**\n * __e1000_read_phy_reg_igp - Read igp PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n * @locked: semaphore has already been acquired or not\n *\n * Acquires semaphore, if necessary, then reads the PHY register at offset\n * and stores the retrieved information in data. Release any acquired\n * semaphores before exiting.\n **/\nstatic s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,\n\t\t\t\t bool locked)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"__e1000_read_phy_reg_igp\");\n\n\tif (!locked) {\n\t\tif (!hw->phy.ops.acquire)\n\t\t\treturn E1000_SUCCESS;\n\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tif (offset > MAX_PHY_MULTI_PAGE_REG)\n\t\tret_val = e1000_write_phy_reg_mdic(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PAGE_SELECT,\n\t\t\t\t\t\t (u16)offset);\n\tif (!ret_val)\n\t\tret_val = e1000_read_phy_reg_mdic(hw,\n\t\t\t\t\t\t MAX_PHY_REG_ADDRESS & offset,\n\t\t\t\t\t\t data);\n\tif (!locked)\n\t\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_read_phy_reg_igp - Read igp PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Acquires semaphore then reads the PHY register at offset and stores the\n * retrieved information in data.\n * Release the acquired semaphore before exiting.\n **/\ns32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn __e1000_read_phy_reg_igp(hw, offset, data, false);\n}\n\n/**\n * e1000_read_phy_reg_igp_locked - Read igp PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the PHY register at offset and stores the retrieved information\n * in data. Assumes semaphore already acquired.\n **/\ns32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn __e1000_read_phy_reg_igp(hw, offset, data, true);\n}\n\n/**\n * e1000_write_phy_reg_igp - Write igp PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n * @locked: semaphore has already been acquired or not\n *\n * Acquires semaphore, if necessary, then writes the data to PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\nstatic s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,\n\t\t\t\t bool locked)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_igp\");\n\n\tif (!locked) {\n\t\tif (!hw->phy.ops.acquire)\n\t\t\treturn E1000_SUCCESS;\n\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tif (offset > MAX_PHY_MULTI_PAGE_REG)\n\t\tret_val = e1000_write_phy_reg_mdic(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PAGE_SELECT,\n\t\t\t\t\t\t (u16)offset);\n\tif (!ret_val)\n\t\tret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &\n\t\t\t\t\t\t offset,\n\t\t\t\t\t\t data);\n\tif (!locked)\n\t\thw->phy.ops.release(hw);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_write_phy_reg_igp - Write igp PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Acquires semaphore then writes the data to PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\ns32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn __e1000_write_phy_reg_igp(hw, offset, data, false);\n}\n\n/**\n * e1000_write_phy_reg_igp_locked - Write igp PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Writes the data to PHY register at the offset.\n * Assumes semaphore already acquired.\n **/\ns32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn __e1000_write_phy_reg_igp(hw, offset, data, true);\n}\n\n/**\n * __e1000_read_kmrn_reg - Read kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n * @locked: semaphore has already been acquired or not\n *\n * Acquires semaphore, if necessary. Then reads the PHY register at offset\n * using the kumeran interface. The information retrieved is stored in data.\n * Release any acquired semaphores before exiting.\n **/\nstatic s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,\n\t\t\t\t bool locked)\n{\n\tu32 kmrnctrlsta;\n\n\tDEBUGFUNC(\"__e1000_read_kmrn_reg\");\n\n\tif (!locked) {\n\t\ts32 ret_val = E1000_SUCCESS;\n\n\t\tif (!hw->phy.ops.acquire)\n\t\t\treturn E1000_SUCCESS;\n\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tkmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &\n\t\t E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;\n\tE1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);\n\tE1000_WRITE_FLUSH(hw);\n\n\tusec_delay(2);\n\n\tkmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);\n\t*data = (u16)kmrnctrlsta;\n\n\tif (!locked)\n\t\thw->phy.ops.release(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_read_kmrn_reg_generic - Read kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Acquires semaphore then reads the PHY register at offset using the\n * kumeran interface. The information retrieved is stored in data.\n * Release the acquired semaphore before exiting.\n **/\ns32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn __e1000_read_kmrn_reg(hw, offset, data, false);\n}\n\n/**\n * e1000_read_kmrn_reg_locked - Read kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to be read\n * @data: pointer to the read data\n *\n * Reads the PHY register at offset using the kumeran interface. The\n * information retrieved is stored in data.\n * Assumes semaphore already acquired.\n **/\ns32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\treturn __e1000_read_kmrn_reg(hw, offset, data, true);\n}\n\n/**\n * __e1000_write_kmrn_reg - Write kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n * @locked: semaphore has already been acquired or not\n *\n * Acquires semaphore, if necessary. Then write the data to PHY register\n * at the offset using the kumeran interface. Release any acquired semaphores\n * before exiting.\n **/\nstatic s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,\n\t\t\t\t bool locked)\n{\n\tu32 kmrnctrlsta;\n\n\tDEBUGFUNC(\"e1000_write_kmrn_reg_generic\");\n\n\tif (!locked) {\n\t\ts32 ret_val = E1000_SUCCESS;\n\n\t\tif (!hw->phy.ops.acquire)\n\t\t\treturn E1000_SUCCESS;\n\n\t\tret_val = hw->phy.ops.acquire(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tkmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &\n\t\t E1000_KMRNCTRLSTA_OFFSET) | data;\n\tE1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);\n\tE1000_WRITE_FLUSH(hw);\n\n\tusec_delay(2);\n\n\tif (!locked)\n\t\thw->phy.ops.release(hw);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_kmrn_reg_generic - Write kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Acquires semaphore then writes the data to the PHY register at the offset\n * using the kumeran interface. Release the acquired semaphore before exiting.\n **/\ns32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn __e1000_write_kmrn_reg(hw, offset, data, false);\n}\n\n/**\n * e1000_write_kmrn_reg_locked - Write kumeran register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Write the data to PHY register at the offset using the kumeran interface.\n * Assumes semaphore already acquired.\n **/\ns32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\treturn __e1000_write_kmrn_reg(hw, offset, data, true);\n}\n\n/**\n * e1000_set_master_slave_mode - Setup PHY for Master/slave mode\n * @hw: pointer to the HW structure\n *\n * Sets up Master/slave mode\n **/\nstatic s32 e1000_set_master_slave_mode(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 phy_data;\n\n\t/* Resolve Master/Slave mode */\n\tret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* load defaults for future use */\n\thw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?\n\t\t\t\t ((phy_data & CR_1000T_MS_VALUE) ?\n\t\t\t\t e1000_ms_force_master :\n\t\t\t\t e1000_ms_force_slave) : e1000_ms_auto;\n\n\tswitch (hw->phy.ms_type) {\n\tcase e1000_ms_force_master:\n\t\tphy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);\n\t\tbreak;\n\tcase e1000_ms_force_slave:\n\t\tphy_data |= CR_1000T_MS_ENABLE;\n\t\tphy_data &= ~(CR_1000T_MS_VALUE);\n\t\tbreak;\n\tcase e1000_ms_auto:\n\t\tphy_data &= ~CR_1000T_MS_ENABLE;\n\t\t/* fall-through */\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);\n}\n\n/**\n * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link\n * @hw: pointer to the HW structure\n *\n * Sets up Carrier-sense on Transmit and downshift values.\n **/\ns32 e1000_copper_link_setup_82577(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_copper_link_setup_82577\");\n\n\tif (hw->phy.reset_disable)\n\t\treturn E1000_SUCCESS;\n\n\tif (hw->phy.type == e1000_phy_82580) {\n\t\tret_val = hw->phy.ops.reset(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error resetting the PHY.\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\t/* Enable CRS on Tx. This must be set for half-duplex operation. */\n\tret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_data |= I82577_CFG_ASSERT_CRS_ON_TX;\n\n\t/* Enable downshift */\n\tphy_data |= I82577_CFG_ENABLE_DOWNSHIFT;\n\n\tret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Set MDI/MDIX mode */\n\tret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\tphy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;\n\t/* Options:\n\t * 0 - Auto (default)\n\t * 1 - MDI mode\n\t * 2 - MDI-X mode\n\t */\n\tswitch (hw->phy.mdix) {\n\tcase 1:\n\t\tbreak;\n\tcase 2:\n\t\tphy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;\n\t\tbreak;\n\tcase 0:\n\tdefault:\n\t\tphy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;\n\t\tbreak;\n\t}\n\tret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn e1000_set_master_slave_mode(hw);\n}\n\n/**\n * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link\n * @hw: pointer to the HW structure\n *\n * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock\n * and downshift values are set also.\n **/\ns32 e1000_copper_link_setup_m88(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_copper_link_setup_m88\");\n\n\tif (phy->reset_disable)\n\t\treturn E1000_SUCCESS;\n\n\t/* Enable CRS on Tx. This must be set for half-duplex operation. */\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;\n\n\t/* Options:\n\t * MDI/MDI-X = 0 (default)\n\t * 0 - Auto for all speeds\n\t * 1 - MDI mode\n\t * 2 - MDI-X mode\n\t * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)\n\t */\n\tphy_data &= ~M88E1000_PSCR_AUTO_X_MODE;\n\n\tswitch (phy->mdix) {\n\tcase 1:\n\t\tphy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;\n\t\tbreak;\n\tcase 2:\n\t\tphy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;\n\t\tbreak;\n\tcase 3:\n\t\tphy_data |= M88E1000_PSCR_AUTO_X_1000T;\n\t\tbreak;\n\tcase 0:\n\tdefault:\n\t\tphy_data |= M88E1000_PSCR_AUTO_X_MODE;\n\t\tbreak;\n\t}\n\n\t/* Options:\n\t * disable_polarity_correction = 0 (default)\n\t * Automatic Correction for Reversed Cable Polarity\n\t * 0 - Disabled\n\t * 1 - Enabled\n\t */\n\tphy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;\n\tif (phy->disable_polarity_correction)\n\t\tphy_data |= M88E1000_PSCR_POLARITY_REVERSAL;\n\n\tret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (phy->revision < E1000_REVISION_4) {\n\t\t/* Force TX_CLK in the Extended PHY Specific Control Register\n\t\t * to 25MHz clock.\n\t\t */\n\t\tret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy_data |= M88E1000_EPSCR_TX_CLK_25;\n\n\t\tif ((phy->revision == E1000_REVISION_2) &&\n\t\t (phy->id == M88E1111_I_PHY_ID)) {\n\t\t\t/* 82573L PHY - set the downshift counter to 5x. */\n\t\t\tphy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;\n\t\t\tphy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;\n\t\t} else {\n\t\t\t/* Configure Master and Slave downshift values */\n\t\t\tphy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |\n\t\t\t\t M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);\n\t\t\tphy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |\n\t\t\t\t M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);\n\t\t}\n\t\tret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,\n\t\t\t\t\t phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* Commit the changes. */\n\tret_val = phy->ops.commit(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error committing the PHY changes\\n\");\n\t\treturn ret_val;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link\n * @hw: pointer to the HW structure\n *\n * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.\n * Also enables and sets the downshift parameters.\n **/\ns32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data;\n\n\tDEBUGFUNC(\"e1000_copper_link_setup_m88_gen2\");\n\n\tif (phy->reset_disable)\n\t\treturn E1000_SUCCESS;\n\n\t/* Enable CRS on Tx. This must be set for half-duplex operation. */\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Options:\n\t * MDI/MDI-X = 0 (default)\n\t * 0 - Auto for all speeds\n\t * 1 - MDI mode\n\t * 2 - MDI-X mode\n\t * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)\n\t */\n\tphy_data &= ~M88E1000_PSCR_AUTO_X_MODE;\n\n\tswitch (phy->mdix) {\n\tcase 1:\n\t\tphy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;\n\t\tbreak;\n\tcase 2:\n\t\tphy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;\n\t\tbreak;\n\tcase 3:\n\t\t/* M88E1112 does not support this mode) */\n\t\tif (phy->id != M88E1112_E_PHY_ID) {\n\t\t\tphy_data |= M88E1000_PSCR_AUTO_X_1000T;\n\t\t\tbreak;\n\t\t}\n\tcase 0:\n\tdefault:\n\t\tphy_data |= M88E1000_PSCR_AUTO_X_MODE;\n\t\tbreak;\n\t}\n\n\t/* Options:\n\t * disable_polarity_correction = 0 (default)\n\t * Automatic Correction for Reversed Cable Polarity\n\t * 0 - Disabled\n\t * 1 - Enabled\n\t */\n\tphy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;\n\tif (phy->disable_polarity_correction)\n\t\tphy_data |= M88E1000_PSCR_POLARITY_REVERSAL;\n\n\t/* Enable downshift and setting it to X6 */\n\tif (phy->id == M88E1543_E_PHY_ID) {\n\t\tphy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;\n\t\tret_val =\n\t\t phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.commit(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error committing the PHY changes\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\tphy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;\n\tphy_data |= I347AT4_PSCR_DOWNSHIFT_6X;\n\tphy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;\n\n\tret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Commit the changes. */\n\tret_val = phy->ops.commit(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error committing the PHY changes\\n\");\n\t\treturn ret_val;\n\t}\n\n\tret_val = e1000_set_master_slave_mode(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_copper_link_setup_igp - Setup igp PHY's for copper link\n * @hw: pointer to the HW structure\n *\n * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for\n * igp PHY's.\n **/\ns32 e1000_copper_link_setup_igp(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_copper_link_setup_igp\");\n\n\tif (phy->reset_disable)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->phy.ops.reset(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error resetting the PHY.\\n\");\n\t\treturn ret_val;\n\t}\n\n\t/* Wait 100ms for MAC to configure PHY from NVM settings, to avoid\n\t * timeout issues when LFS is enabled.\n\t */\n\tmsec_delay(100);\n\n\t/* disable lplu d0 during driver init */\n\tif (hw->phy.ops.set_d0_lplu_state) {\n\t\tret_val = hw->phy.ops.set_d0_lplu_state(hw, false);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error Disabling LPLU D0\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\t/* Configure mdi-mdix settings */\n\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tdata &= ~IGP01E1000_PSCR_AUTO_MDIX;\n\n\tswitch (phy->mdix) {\n\tcase 1:\n\t\tdata &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;\n\t\tbreak;\n\tcase 2:\n\t\tdata |= IGP01E1000_PSCR_FORCE_MDI_MDIX;\n\t\tbreak;\n\tcase 0:\n\tdefault:\n\t\tdata |= IGP01E1000_PSCR_AUTO_MDIX;\n\t\tbreak;\n\t}\n\tret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* set auto-master slave resolution settings */\n\tif (hw->mac.autoneg) {\n\t\t/* when autonegotiation advertisement is only 1000Mbps then we\n\t\t * should disable SmartSpeed and enable Auto MasterSlave\n\t\t * resolution as hardware default.\n\t\t */\n\t\tif (phy->autoneg_advertised == ADVERTISE_1000_FULL) {\n\t\t\t/* Disable SmartSpeed */\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\t/* Set auto Master/Slave resolution process */\n\t\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata &= ~CR_1000T_MS_ENABLE;\n\t\t\tret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t}\n\n\t\tret_val = e1000_set_master_slave_mode(hw);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation\n * @hw: pointer to the HW structure\n *\n * Reads the MII auto-neg advertisement register and/or the 1000T control\n * register and if the PHY is already setup for auto-negotiation, then\n * return successful. Otherwise, setup advertisement and flow control to\n * the appropriate values for the wanted auto-negotiation.\n **/\nstatic s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 mii_autoneg_adv_reg;\n\tu16 mii_1000t_ctrl_reg = 0;\n\n\tDEBUGFUNC(\"e1000_phy_setup_autoneg\");\n\n\tphy->autoneg_advertised &= phy->autoneg_mask;\n\n\t/* Read the MII Auto-Neg Advertisement Register (Address 4). */\n\tret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (phy->autoneg_mask & ADVERTISE_1000_FULL) {\n\t\t/* Read the MII 1000Base-T Control Register (Address 9). */\n\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,\n\t\t\t\t\t &mii_1000t_ctrl_reg);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\t/* Need to parse both autoneg_advertised and fc and set up\n\t * the appropriate PHY registers. First we will parse for\n\t * autoneg_advertised software override. Since we can advertise\n\t * a plethora of combinations, we need to check each bit\n\t * individually.\n\t */\n\n\t/* First we clear all the 10/100 mb speed bits in the Auto-Neg\n\t * Advertisement Register (Address 4) and the 1000 mb speed bits in\n\t * the 1000Base-T Control Register (Address 9).\n\t */\n\tmii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |\n\t\t\t\t NWAY_AR_100TX_HD_CAPS |\n\t\t\t\t NWAY_AR_10T_FD_CAPS |\n\t\t\t\t NWAY_AR_10T_HD_CAPS);\n\tmii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);\n\n\tDEBUGOUT1(\"autoneg_advertised %x\\n\", phy->autoneg_advertised);\n\n\t/* Do we want to advertise 10 Mb Half Duplex? */\n\tif (phy->autoneg_advertised & ADVERTISE_10_HALF) {\n\t\tDEBUGOUT(\"Advertise 10mb Half duplex\\n\");\n\t\tmii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;\n\t}\n\n\t/* Do we want to advertise 10 Mb Full Duplex? */\n\tif (phy->autoneg_advertised & ADVERTISE_10_FULL) {\n\t\tDEBUGOUT(\"Advertise 10mb Full duplex\\n\");\n\t\tmii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;\n\t}\n\n\t/* Do we want to advertise 100 Mb Half Duplex? */\n\tif (phy->autoneg_advertised & ADVERTISE_100_HALF) {\n\t\tDEBUGOUT(\"Advertise 100mb Half duplex\\n\");\n\t\tmii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;\n\t}\n\n\t/* Do we want to advertise 100 Mb Full Duplex? */\n\tif (phy->autoneg_advertised & ADVERTISE_100_FULL) {\n\t\tDEBUGOUT(\"Advertise 100mb Full duplex\\n\");\n\t\tmii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;\n\t}\n\n\t/* We do not allow the Phy to advertise 1000 Mb Half Duplex */\n\tif (phy->autoneg_advertised & ADVERTISE_1000_HALF)\n\t\tDEBUGOUT(\"Advertise 1000mb Half duplex request denied!\\n\");\n\n\t/* Do we want to advertise 1000 Mb Full Duplex? */\n\tif (phy->autoneg_advertised & ADVERTISE_1000_FULL) {\n\t\tDEBUGOUT(\"Advertise 1000mb Full duplex\\n\");\n\t\tmii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;\n\t}\n\n\t/* Check for a software override of the flow control settings, and\n\t * setup the PHY advertisement registers accordingly. If\n\t * auto-negotiation is enabled, then software will have to set the\n\t * \"PAUSE\" bits to the correct value in the Auto-Negotiation\n\t * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-\n\t * negotiation.\n\t *\n\t * The possible values of the \"fc\" parameter are:\n\t * 0: Flow control is completely disabled\n\t * 1: Rx flow control is enabled (we can receive pause frames\n\t * but not send pause frames).\n\t * 2: Tx flow control is enabled (we can send pause frames\n\t * but we do not support receiving pause frames).\n\t * 3: Both Rx and Tx flow control (symmetric) are enabled.\n\t * other: No software override. The flow control configuration\n\t * in the EEPROM is used.\n\t */\n\tswitch (hw->fc.current_mode) {\n\tcase e1000_fc_none:\n\t\t/* Flow control (Rx & Tx) is completely disabled by a\n\t\t * software over-ride.\n\t\t */\n\t\tmii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);\n\t\tbreak;\n\tcase e1000_fc_rx_pause:\n\t\t/* Rx Flow control is enabled, and Tx Flow control is\n\t\t * disabled, by a software over-ride.\n\t\t *\n\t\t * Since there really isn't a way to advertise that we are\n\t\t * capable of Rx Pause ONLY, we will advertise that we\n\t\t * support both symmetric and asymmetric Rx PAUSE. Later\n\t\t * (in e1000_config_fc_after_link_up) we will disable the\n\t\t * hw's ability to send PAUSE frames.\n\t\t */\n\t\tmii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);\n\t\tbreak;\n\tcase e1000_fc_tx_pause:\n\t\t/* Tx Flow control is enabled, and Rx Flow control is\n\t\t * disabled, by a software over-ride.\n\t\t */\n\t\tmii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;\n\t\tmii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;\n\t\tbreak;\n\tcase e1000_fc_full:\n\t\t/* Flow control (both Rx and Tx) is enabled by a software\n\t\t * over-ride.\n\t\t */\n\t\tmii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);\n\t\tbreak;\n\tdefault:\n\t\tDEBUGOUT(\"Flow control param set incorrectly\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tDEBUGOUT1(\"Auto-Neg Advertising %x\\n\", mii_autoneg_adv_reg);\n\n\tif (phy->autoneg_mask & ADVERTISE_1000_FULL)\n\t\tret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,\n\t\t\t\t\t mii_1000t_ctrl_reg);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link\n * @hw: pointer to the HW structure\n *\n * Performs initial bounds checking on autoneg advertisement parameter, then\n * configure to advertise the full capability. Setup the PHY to autoneg\n * and restart the negotiation process between the link partner. If\n * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.\n **/\nstatic s32 e1000_copper_link_autoneg(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_ctrl;\n\n\tDEBUGFUNC(\"e1000_copper_link_autoneg\");\n\n\t/* Perform some bounds checking on the autoneg advertisement\n\t * parameter.\n\t */\n\tphy->autoneg_advertised &= phy->autoneg_mask;\n\n\t/* If autoneg_advertised is zero, we assume it was not defaulted\n\t * by the calling code so we set to advertise full capability.\n\t */\n\tif (!phy->autoneg_advertised)\n\t\tphy->autoneg_advertised = phy->autoneg_mask;\n\n\tDEBUGOUT(\"Reconfiguring auto-neg advertisement params\\n\");\n\tret_val = e1000_phy_setup_autoneg(hw);\n\tif (ret_val) {\n\t\tDEBUGOUT(\"Error Setting up Auto-Negotiation\\n\");\n\t\treturn ret_val;\n\t}\n\tDEBUGOUT(\"Restarting Auto-Neg\\n\");\n\n\t/* Restart auto-negotiation by setting the Auto Neg Enable bit and\n\t * the Auto Neg Restart bit in the PHY control register.\n\t */\n\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);\n\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Does the user want to wait for Auto-Neg to complete here, or\n\t * check at a later time (for example, callback routine).\n\t */\n\tif (phy->autoneg_wait_to_complete) {\n\t\tret_val = e1000_wait_autoneg(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error while waiting for autoneg to complete\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\thw->mac.get_link_status = true;\n\n\treturn ret_val;\n}\n\n/**\n * e1000_setup_copper_link_generic - Configure copper link settings\n * @hw: pointer to the HW structure\n *\n * Calls the appropriate function to configure the link for auto-neg or forced\n * speed and duplex. Then we check for link, once link is established calls\n * to configure collision distance and flow control are called. If link is\n * not established, we return -E1000_ERR_PHY (-2).\n **/\ns32 e1000_setup_copper_link_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_setup_copper_link_generic\");\n\n\tif (hw->mac.autoneg) {\n\t\t/* Setup autoneg and flow control advertisement and perform\n\t\t * autonegotiation.\n\t\t */\n\t\tret_val = e1000_copper_link_autoneg(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\t/* PHY will be set to 10H, 10F, 100H or 100F\n\t\t * depending on user settings.\n\t\t */\n\t\tDEBUGOUT(\"Forcing Speed and Duplex\\n\");\n\t\tret_val = hw->phy.ops.force_speed_duplex(hw);\n\t\tif (ret_val) {\n\t\t\tDEBUGOUT(\"Error Forcing Speed and Duplex\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t}\n\n\t/* Check link status. Wait up to 100 microseconds for link to become\n\t * valid.\n\t */\n\tret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,\n\t\t\t\t\t &link);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (link) {\n\t\tDEBUGOUT(\"Valid link established!!!\\n\");\n\t\thw->mac.ops.config_collision_dist(hw);\n\t\tret_val = e1000_config_fc_after_link_up_generic(hw);\n\t} else {\n\t\tDEBUGOUT(\"Unable to establish link!!!\\n\");\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY\n * @hw: pointer to the HW structure\n *\n * Calls the PHY setup function to force speed and duplex. Clears the\n * auto-crossover to force MDI manually. Waits for link and returns\n * successful if link up is successful, else -E1000_ERR_PHY (-2).\n **/\ns32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_phy_force_speed_duplex_igp\");\n\n\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\te1000_phy_force_speed_duplex_setup(hw, &phy_data);\n\n\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Clear Auto-Crossover to force MDI manually. IGP requires MDI\n\t * forced whenever speed and duplex are forced.\n\t */\n\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;\n\tphy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;\n\n\tret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tDEBUGOUT1(\"IGP PSCR: %X\\n\", phy_data);\n\n\tusec_delay(1);\n\n\tif (phy->autoneg_wait_to_complete) {\n\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on IGP phy.\\n\");\n\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (!link)\n\t\t\tDEBUGOUT(\"Link taking longer than expected.\\n\");\n\n\t\t/* Try once more */\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY\n * @hw: pointer to the HW structure\n *\n * Calls the PHY setup function to force speed and duplex. Clears the\n * auto-crossover to force MDI manually. Resets the PHY to commit the\n * changes. If time expires while waiting for link up, we reset the DSP.\n * After reset, TX_CLK and CRS on Tx must be set. Return successful upon\n * successful completion, else return corresponding error code.\n **/\ns32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_phy_force_speed_duplex_m88\");\n\n\t/* I210 and I211 devices support Auto-Crossover in forced operation. */\n\tif (phy->type != e1000_phy_i210) {\n\t\t/* Clear Auto-Crossover to force MDI manually. M88E1000\n\t\t * requires MDI forced whenever speed and duplex are forced.\n\t\t */\n\t\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy_data &= ~M88E1000_PSCR_AUTO_X_MODE;\n\t\tret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,\n\t\t\t\t\t phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tDEBUGOUT1(\"M88E1000 PSCR: %X\\n\", phy_data);\n\n\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\te1000_phy_force_speed_duplex_setup(hw, &phy_data);\n\n\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Reset the phy to commit changes. */\n\tret_val = hw->phy.ops.commit(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (phy->autoneg_wait_to_complete) {\n\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on M88 phy.\\n\");\n\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (!link) {\n\t\t\tbool reset_dsp = true;\n\n\t\t\tswitch (hw->phy.id) {\n\t\t\tcase I347AT4_E_PHY_ID:\n\t\t\tcase M88E1340M_E_PHY_ID:\n\t\t\tcase M88E1112_E_PHY_ID:\n\t\t\tcase M88E1543_E_PHY_ID:\n\t\t\tcase I210_I_PHY_ID:\n\t\t\t\treset_dsp = false;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tif (hw->phy.type != e1000_phy_m88)\n\t\t\t\t\treset_dsp = false;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif (!reset_dsp) {\n\t\t\t\tDEBUGOUT(\"Link taking longer than expected.\\n\");\n\t\t\t} else {\n\t\t\t\t/* We didn't get link.\n\t\t\t\t * Reset the DSP and cross our fingers.\n\t\t\t\t */\n\t\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\tM88E1000_PHY_PAGE_SELECT,\n\t\t\t\t\t\t0x001d);\n\t\t\t\tif (ret_val)\n\t\t\t\t\treturn ret_val;\n\t\t\t\tret_val = e1000_phy_reset_dsp_generic(hw);\n\t\t\t\tif (ret_val)\n\t\t\t\t\treturn ret_val;\n\t\t\t}\n\t\t}\n\n\t\t/* Try once more */\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\tif (hw->phy.type != e1000_phy_m88)\n\t\treturn E1000_SUCCESS;\n\n\tif (hw->phy.id == I347AT4_E_PHY_ID ||\n\t\thw->phy.id == M88E1340M_E_PHY_ID ||\n\t\thw->phy.id == M88E1112_E_PHY_ID)\n\t\treturn E1000_SUCCESS;\n\tif (hw->phy.id == I210_I_PHY_ID)\n\t\treturn E1000_SUCCESS;\n\tif ((hw->phy.id == M88E1543_E_PHY_ID))\n\t\treturn E1000_SUCCESS;\n\tret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Resetting the phy means we need to re-force TX_CLK in the\n\t * Extended PHY Specific Control Register to 25MHz clock from\n\t * the reset value of 2.5MHz.\n\t */\n\tphy_data |= M88E1000_EPSCR_TX_CLK_25;\n\tret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* In addition, we must re-enable CRS on Tx for both half and full\n\t * duplex.\n\t */\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;\n\tret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex\n * @hw: pointer to the HW structure\n *\n * Forces the speed and duplex settings of the PHY.\n * This is a function pointer entry point only called by\n * PHY setup routines.\n **/\ns32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_phy_force_speed_duplex_ife\");\n\n\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\te1000_phy_force_speed_duplex_setup(hw, &data);\n\n\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\t/* Disable MDI-X support for 10/100 */\n\tret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tdata &= ~IFE_PMC_AUTO_MDIX;\n\tdata &= ~IFE_PMC_FORCE_MDIX;\n\n\tret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tDEBUGOUT1(\"IFE PMC: %X\\n\", data);\n\n\tusec_delay(1);\n\n\tif (phy->autoneg_wait_to_complete) {\n\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on IFE phy.\\n\");\n\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (!link)\n\t\t\tDEBUGOUT(\"Link taking longer than expected.\\n\");\n\n\t\t/* Try once more */\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex\n * @hw: pointer to the HW structure\n * @phy_ctrl: pointer to current value of PHY_CONTROL\n *\n * Forces speed and duplex on the PHY by doing the following: disable flow\n * control, force speed/duplex on the MAC, disable auto speed detection,\n * disable auto-negotiation, configure duplex, configure speed, configure\n * the collision distance, write configuration to CTRL register. The\n * caller must write to the PHY_CONTROL register for these settings to\n * take affect.\n **/\nvoid e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)\n{\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tu32 ctrl;\n\n\tDEBUGFUNC(\"e1000_phy_force_speed_duplex_setup\");\n\n\t/* Turn off flow control when forcing speed/duplex */\n\thw->fc.current_mode = e1000_fc_none;\n\n\t/* Force speed/duplex on the mac */\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);\n\tctrl &= ~E1000_CTRL_SPD_SEL;\n\n\t/* Disable Auto Speed Detection */\n\tctrl &= ~E1000_CTRL_ASDE;\n\n\t/* Disable autoneg on the phy */\n\t*phy_ctrl &= ~MII_CR_AUTO_NEG_EN;\n\n\t/* Forcing Full or Half Duplex? */\n\tif (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {\n\t\tctrl &= ~E1000_CTRL_FD;\n\t\t*phy_ctrl &= ~MII_CR_FULL_DUPLEX;\n\t\tDEBUGOUT(\"Half Duplex\\n\");\n\t} else {\n\t\tctrl |= E1000_CTRL_FD;\n\t\t*phy_ctrl |= MII_CR_FULL_DUPLEX;\n\t\tDEBUGOUT(\"Full Duplex\\n\");\n\t}\n\n\t/* Forcing 10mb or 100mb? */\n\tif (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {\n\t\tctrl |= E1000_CTRL_SPD_100;\n\t\t*phy_ctrl |= MII_CR_SPEED_100;\n\t\t*phy_ctrl &= ~MII_CR_SPEED_1000;\n\t\tDEBUGOUT(\"Forcing 100mb\\n\");\n\t} else {\n\t\tctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);\n\t\t*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);\n\t\tDEBUGOUT(\"Forcing 10mb\\n\");\n\t}\n\n\thw->mac.ops.config_collision_dist(hw);\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n}\n\n/**\n * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3\n * @hw: pointer to the HW structure\n * @active: boolean used to enable/disable lplu\n *\n * Success returns 0, Failure returns 1\n *\n * The low power link up (lplu) state is set to the power management level D3\n * and SmartSpeed is disabled when active is true, else clear lplu for D3\n * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU\n * is used during Dx states where the power conservation is most important.\n * During driver activity, SmartSpeed should be enabled so performance is\n * maintained.\n **/\ns32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_set_d3_lplu_state_generic\");\n\n\tif (!hw->phy.ops.read_reg)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!active) {\n\t\tdata &= ~IGP02E1000_PM_D3_LPLU;\n\t\tret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,\n\t\t\t\t\t data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\t/* LPLU and SmartSpeed are mutually exclusive. LPLU is used\n\t\t * during Dx states where the power conservation is most\n\t\t * important. During driver activity we should enable\n\t\t * SmartSpeed, so performance is maintained.\n\t\t */\n\t\tif (phy->smart_speed == e1000_smart_speed_on) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata |= IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t} else if (phy->smart_speed == e1000_smart_speed_off) {\n\t\t\tret_val = phy->ops.read_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t &data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\n\t\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\t\tret_val = phy->ops.write_reg(hw,\n\t\t\t\t\t\t IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t\t data);\n\t\t\tif (ret_val)\n\t\t\t\treturn ret_val;\n\t\t}\n\t} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||\n\t\t (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||\n\t\t (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {\n\t\tdata |= IGP02E1000_PM_D3_LPLU;\n\t\tret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,\n\t\t\t\t\t data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* When LPLU is enabled, we should disable SmartSpeed */\n\t\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tdata &= ~IGP01E1000_PSCFR_SMART_SPEED;\n\t\tret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,\n\t\t\t\t\t data);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_downshift_generic - Checks whether a downshift in speed occurred\n * @hw: pointer to the HW structure\n *\n * Success returns 0, Failure returns 1\n *\n * A downshift is detected by querying the PHY link health.\n **/\ns32 e1000_check_downshift_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, offset, mask;\n\n\tDEBUGFUNC(\"e1000_check_downshift_generic\");\n\n\tswitch (phy->type) {\n\tcase e1000_phy_i210:\n\tcase e1000_phy_m88:\n\tcase e1000_phy_gg82563:\n\t\toffset = M88E1000_PHY_SPEC_STATUS;\n\t\tmask = M88E1000_PSSR_DOWNSHIFT;\n\t\tbreak;\n\tcase e1000_phy_igp_2:\n\tcase e1000_phy_igp_3:\n\t\toffset = IGP01E1000_PHY_LINK_HEALTH;\n\t\tmask = IGP01E1000_PLHR_SS_DOWNGRADE;\n\t\tbreak;\n\tdefault:\n\t\t/* speed downshift not supported */\n\t\tphy->speed_downgraded = false;\n\t\treturn E1000_SUCCESS;\n\t}\n\n\tret_val = phy->ops.read_reg(hw, offset, &phy_data);\n\n\tif (!ret_val)\n\t\tphy->speed_downgraded = !!(phy_data & mask);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_polarity_m88 - Checks the polarity.\n * @hw: pointer to the HW structure\n *\n * Success returns 0, Failure returns -E1000_ERR_PHY (-2)\n *\n * Polarity is determined based on the PHY specific status register.\n **/\ns32 e1000_check_polarity_m88(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_check_polarity_m88\");\n\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);\n\n\tif (!ret_val)\n\t\tphy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)\n\t\t\t\t ? e1000_rev_polarity_reversed\n\t\t\t\t : e1000_rev_polarity_normal);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_polarity_igp - Checks the polarity.\n * @hw: pointer to the HW structure\n *\n * Success returns 0, Failure returns -E1000_ERR_PHY (-2)\n *\n * Polarity is determined based on the PHY port status register, and the\n * current speed (since there is no polarity at 100Mbps).\n **/\ns32 e1000_check_polarity_igp(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data, offset, mask;\n\n\tDEBUGFUNC(\"e1000_check_polarity_igp\");\n\n\t/* Polarity is determined based on the speed of\n\t * our connection.\n\t */\n\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif ((data & IGP01E1000_PSSR_SPEED_MASK) ==\n\t IGP01E1000_PSSR_SPEED_1000MBPS) {\n\t\toffset = IGP01E1000_PHY_PCS_INIT_REG;\n\t\tmask = IGP01E1000_PHY_POLARITY_MASK;\n\t} else {\n\t\t/* This really only applies to 10Mbps since\n\t\t * there is no polarity for 100Mbps (always 0).\n\t\t */\n\t\toffset = IGP01E1000_PHY_PORT_STATUS;\n\t\tmask = IGP01E1000_PSSR_POLARITY_REVERSED;\n\t}\n\n\tret_val = phy->ops.read_reg(hw, offset, &data);\n\n\tif (!ret_val)\n\t\tphy->cable_polarity = ((data & mask)\n\t\t\t\t ? e1000_rev_polarity_reversed\n\t\t\t\t : e1000_rev_polarity_normal);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_check_polarity_ife - Check cable polarity for IFE PHY\n * @hw: pointer to the HW structure\n *\n * Polarity is determined on the polarity reversal feature being enabled.\n **/\ns32 e1000_check_polarity_ife(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, offset, mask;\n\n\tDEBUGFUNC(\"e1000_check_polarity_ife\");\n\n\t/* Polarity is determined based on the reversal feature being enabled.\n\t */\n\tif (phy->polarity_correction) {\n\t\toffset = IFE_PHY_EXTENDED_STATUS_CONTROL;\n\t\tmask = IFE_PESC_POLARITY_REVERSED;\n\t} else {\n\t\toffset = IFE_PHY_SPECIAL_CONTROL;\n\t\tmask = IFE_PSC_FORCE_POLARITY;\n\t}\n\n\tret_val = phy->ops.read_reg(hw, offset, &phy_data);\n\n\tif (!ret_val)\n\t\tphy->cable_polarity = ((phy_data & mask)\n\t\t\t\t ? e1000_rev_polarity_reversed\n\t\t\t\t : e1000_rev_polarity_normal);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_wait_autoneg - Wait for auto-neg completion\n * @hw: pointer to the HW structure\n *\n * Waits for auto-negotiation to complete or for the auto-negotiation time\n * limit to expire, which ever happens first.\n **/\nstatic s32 e1000_wait_autoneg(struct e1000_hw *hw)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 i, phy_status;\n\n\tDEBUGFUNC(\"e1000_wait_autoneg\");\n\n\tif (!hw->phy.ops.read_reg)\n\t\treturn E1000_SUCCESS;\n\n\t/* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */\n\tfor (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);\n\t\tif (ret_val)\n\t\t\tbreak;\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);\n\t\tif (ret_val)\n\t\t\tbreak;\n\t\tif (phy_status & MII_SR_AUTONEG_COMPLETE)\n\t\t\tbreak;\n\t\tmsec_delay(100);\n\t}\n\n\t/* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation\n\t * has completed.\n\t */\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_has_link_generic - Polls PHY for link\n * @hw: pointer to the HW structure\n * @iterations: number of times to poll for link\n * @usec_interval: delay between polling attempts\n * @success: pointer to whether polling was successful or not\n *\n * Polls the PHY status register for link, 'iterations' number of times.\n **/\ns32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,\n\t\t\t u32 usec_interval, bool *success)\n{\n\ts32 ret_val = E1000_SUCCESS;\n\tu16 i, phy_status;\n\n\tDEBUGFUNC(\"e1000_phy_has_link_generic\");\n\n\tif (!hw->phy.ops.read_reg)\n\t\treturn E1000_SUCCESS;\n\n\tfor (i = 0; i < iterations; i++) {\n\t\t/* Some PHYs require the PHY_STATUS register to be read\n\t\t * twice due to the link bit being sticky. No harm doing\n\t\t * it across the board.\n\t\t */\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);\n\t\tif (ret_val)\n\t\t\t/* If the first read fails, another entity may have\n\t\t\t * ownership of the resources, wait and try again to\n\t\t\t * see if they have relinquished the resources yet.\n\t\t\t */\n\t\t\tusec_delay(usec_interval);\n\t\tret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);\n\t\tif (ret_val)\n\t\t\tbreak;\n\t\tif (phy_status & MII_SR_LINK_STATUS)\n\t\t\tbreak;\n\t\tif (usec_interval >= 1000)\n\t\t\tmsec_delay_irq(usec_interval/1000);\n\t\telse\n\t\t\tusec_delay(usec_interval);\n\t}\n\n\t*success = (i < iterations);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_cable_length_m88 - Determine cable length for m88 PHY\n * @hw: pointer to the HW structure\n *\n * Reads the PHY specific status register to retrieve the cable length\n * information. The cable length is determined by averaging the minimum and\n * maximum values to get the \"average\" cable length. The m88 PHY has four\n * possible cable length values, which are:\n *\tRegister Value\t\tCable Length\n *\t0\t\t\t< 50 meters\n *\t1\t\t\t50 - 80 meters\n *\t2\t\t\t80 - 110 meters\n *\t3\t\t\t110 - 140 meters\n *\t4\t\t\t> 140 meters\n **/\ns32 e1000_get_cable_length_m88(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, index;\n\n\tDEBUGFUNC(\"e1000_get_cable_length_m88\");\n\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tindex = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>\n\t\t M88E1000_PSSR_CABLE_LENGTH_SHIFT);\n\n\tif (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)\n\t\treturn -E1000_ERR_PHY;\n\n\tphy->min_cable_length = e1000_m88_cable_length_table[index];\n\tphy->max_cable_length = e1000_m88_cable_length_table[index + 1];\n\n\tphy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;\n\n\treturn E1000_SUCCESS;\n}\n\ns32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, phy_data2, is_cm;\n\tu16 index, default_page;\n\n\tDEBUGFUNC(\"e1000_get_cable_length_m88_gen2\");\n\n\tswitch (hw->phy.id) {\n\tcase I210_I_PHY_ID:\n\t\t/* Get cable length from PHY Cable Diagnostics Control Reg */\n\t\tret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +\n\t\t\t\t\t (I347AT4_PCDL + phy->addr),\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Check if the unit of cable length is meters or cm */\n\t\tret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +\n\t\t\t\t\t I347AT4_PCDC, &phy_data2);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tis_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);\n\n\t\t/* Populate the phy structure with cable length in meters */\n\t\tphy->min_cable_length = phy_data / (is_cm ? 100 : 1);\n\t\tphy->max_cable_length = phy_data / (is_cm ? 100 : 1);\n\t\tphy->cable_length = phy_data / (is_cm ? 100 : 1);\n\t\tbreak;\n\tcase M88E1543_E_PHY_ID:\n\tcase M88E1340M_E_PHY_ID:\n\tcase I347AT4_E_PHY_ID:\n\t\t/* Remember the original page select and set it to 7 */\n\t\tret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,\n\t\t\t\t\t &default_page);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Get cable length from PHY Cable Diagnostics Control Reg */\n\t\tret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Check if the unit of cable length is meters or cm */\n\t\tret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tis_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);\n\n\t\t/* Populate the phy structure with cable length in meters */\n\t\tphy->min_cable_length = phy_data / (is_cm ? 100 : 1);\n\t\tphy->max_cable_length = phy_data / (is_cm ? 100 : 1);\n\t\tphy->cable_length = phy_data / (is_cm ? 100 : 1);\n\n\t\t/* Reset the page select to its original value */\n\t\tret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,\n\t\t\t\t\t default_page);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t\tbreak;\n\n\tcase M88E1112_E_PHY_ID:\n\t\t/* Remember the original page select and set it to 5 */\n\t\tret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,\n\t\t\t\t\t &default_page);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tindex = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>\n\t\t\tM88E1000_PSSR_CABLE_LENGTH_SHIFT;\n\n\t\tif (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)\n\t\t\treturn -E1000_ERR_PHY;\n\n\t\tphy->min_cable_length = e1000_m88_cable_length_table[index];\n\t\tphy->max_cable_length = e1000_m88_cable_length_table[index + 1];\n\n\t\tphy->cable_length = (phy->min_cable_length +\n\t\t\t\t phy->max_cable_length) / 2;\n\n\t\t/* Reset the page select to its original value */\n\t\tret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,\n\t\t\t\t\t default_page);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tbreak;\n\tdefault:\n\t\treturn -E1000_ERR_PHY;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY\n * @hw: pointer to the HW structure\n *\n * The automatic gain control (agc) normalizes the amplitude of the\n * received signal, adjusting for the attenuation produced by the\n * cable. By reading the AGC registers, which represent the\n * combination of coarse and fine gain value, the value can be put\n * into a lookup table to obtain the approximate cable length\n * for each channel.\n **/\ns32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, i, agc_value = 0;\n\tu16 cur_agc_index, max_agc_index = 0;\n\tu16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;\n\tstatic const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {\n\t\tIGP02E1000_PHY_AGC_A,\n\t\tIGP02E1000_PHY_AGC_B,\n\t\tIGP02E1000_PHY_AGC_C,\n\t\tIGP02E1000_PHY_AGC_D\n\t};\n\n\tDEBUGFUNC(\"e1000_get_cable_length_igp_2\");\n\n\t/* Read the AGC registers for all channels */\n\tfor (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {\n\t\tret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\t/* Getting bits 15:9, which represent the combination of\n\t\t * coarse and fine gain values. The result is a number\n\t\t * that can be put into the lookup table to obtain the\n\t\t * approximate cable length.\n\t\t */\n\t\tcur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &\n\t\t\t\t IGP02E1000_AGC_LENGTH_MASK);\n\n\t\t/* Array index bound check. */\n\t\tif ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||\n\t\t (cur_agc_index == 0))\n\t\t\treturn -E1000_ERR_PHY;\n\n\t\t/* Remove min & max AGC values from calculation. */\n\t\tif (e1000_igp_2_cable_length_table[min_agc_index] >\n\t\t e1000_igp_2_cable_length_table[cur_agc_index])\n\t\t\tmin_agc_index = cur_agc_index;\n\t\tif (e1000_igp_2_cable_length_table[max_agc_index] <\n\t\t e1000_igp_2_cable_length_table[cur_agc_index])\n\t\t\tmax_agc_index = cur_agc_index;\n\n\t\tagc_value += e1000_igp_2_cable_length_table[cur_agc_index];\n\t}\n\n\tagc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +\n\t\t e1000_igp_2_cable_length_table[max_agc_index]);\n\tagc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);\n\n\t/* Calculate cable length with the error range of +/- 10 meters. */\n\tphy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?\n\t\t\t\t (agc_value - IGP02E1000_AGC_RANGE) : 0);\n\tphy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;\n\n\tphy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_phy_info_m88 - Retrieve PHY information\n * @hw: pointer to the HW structure\n *\n * Valid for only copper links. Read the PHY status register (sticky read)\n * to verify that link is up. Read the PHY special control register to\n * determine the polarity and 10base-T extended distance. Read the PHY\n * special status register to determine MDI/MDIx and current speed. If\n * speed is 1000, then determine cable length, local and remote receiver.\n **/\ns32 e1000_get_phy_info_m88(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_get_phy_info_m88\");\n\n\tif (phy->media_type != e1000_media_type_copper) {\n\t\tDEBUGOUT(\"Phy info is only valid for copper media\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!link) {\n\t\tDEBUGOUT(\"Phy info is only valid if link is up\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy->polarity_correction = !!(phy_data &\n\t\t\t\t M88E1000_PSCR_POLARITY_REVERSAL);\n\n\tret_val = e1000_check_polarity_m88(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);\n\n\tif ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {\n\t\tret_val = hw->phy.ops.get_cable_length(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)\n\t\t\t\t? e1000_1000t_rx_status_ok\n\t\t\t\t: e1000_1000t_rx_status_not_ok;\n\n\t\tphy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)\n\t\t\t\t ? e1000_1000t_rx_status_ok\n\t\t\t\t : e1000_1000t_rx_status_not_ok;\n\t} else {\n\t\t/* Set values to \"undefined\" */\n\t\tphy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;\n\t\tphy->local_rx = e1000_1000t_rx_status_undefined;\n\t\tphy->remote_rx = e1000_1000t_rx_status_undefined;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_phy_info_igp - Retrieve igp PHY information\n * @hw: pointer to the HW structure\n *\n * Read PHY status to determine if link is up. If link is up, then\n * set/determine 10base-T extended distance and polarity correction. Read\n * PHY port status to determine MDI/MDIx and speed. Based on the speed,\n * determine on the cable length, local and remote receiver.\n **/\ns32 e1000_get_phy_info_igp(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_get_phy_info_igp\");\n\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!link) {\n\t\tDEBUGOUT(\"Phy info is only valid if link is up\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tphy->polarity_correction = true;\n\n\tret_val = e1000_check_polarity_igp(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);\n\n\tif ((data & IGP01E1000_PSSR_SPEED_MASK) ==\n\t IGP01E1000_PSSR_SPEED_1000MBPS) {\n\t\tret_val = phy->ops.get_cable_length(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)\n\t\t\t\t? e1000_1000t_rx_status_ok\n\t\t\t\t: e1000_1000t_rx_status_not_ok;\n\n\t\tphy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)\n\t\t\t\t ? e1000_1000t_rx_status_ok\n\t\t\t\t : e1000_1000t_rx_status_not_ok;\n\t} else {\n\t\tphy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;\n\t\tphy->local_rx = e1000_1000t_rx_status_undefined;\n\t\tphy->remote_rx = e1000_1000t_rx_status_undefined;\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_phy_info_ife - Retrieves various IFE PHY states\n * @hw: pointer to the HW structure\n *\n * Populates \"phy\" structure with various feature states.\n **/\ns32 e1000_get_phy_info_ife(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_get_phy_info_ife\");\n\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!link) {\n\t\tDEBUGOUT(\"Phy info is only valid if link is up\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\tphy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);\n\n\tif (phy->polarity_correction) {\n\t\tret_val = e1000_check_polarity_ife(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\t} else {\n\t\t/* Polarity is forced */\n\t\tphy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)\n\t\t\t\t ? e1000_rev_polarity_reversed\n\t\t\t\t : e1000_rev_polarity_normal);\n\t}\n\n\tret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);\n\n\t/* The following parameters are undefined for 10/100 operation. */\n\tphy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;\n\tphy->local_rx = e1000_1000t_rx_status_undefined;\n\tphy->remote_rx = e1000_1000t_rx_status_undefined;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_sw_reset_generic - PHY software reset\n * @hw: pointer to the HW structure\n *\n * Does a software reset of the PHY by reading the PHY control register and\n * setting/write the control register reset bit to the PHY.\n **/\ns32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)\n{\n\ts32 ret_val;\n\tu16 phy_ctrl;\n\n\tDEBUGFUNC(\"e1000_phy_sw_reset_generic\");\n\n\tif (!hw->phy.ops.read_reg)\n\t\treturn E1000_SUCCESS;\n\n\tret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy_ctrl |= MII_CR_RESET;\n\tret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tusec_delay(1);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_hw_reset_generic - PHY hardware reset\n * @hw: pointer to the HW structure\n *\n * Verify the reset block is not blocking us from resetting. Acquire\n * semaphore (if necessary) and read/set/write the device control reset\n * bit in the PHY. Wait the appropriate delay time for the device to\n * reset and release the semaphore (if necessary).\n **/\ns32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu32 ctrl;\n\n\tDEBUGFUNC(\"e1000_phy_hw_reset_generic\");\n\n\tif (phy->ops.check_reset_block) {\n\t\tret_val = phy->ops.check_reset_block(hw);\n\t\tif (ret_val)\n\t\t\treturn E1000_SUCCESS;\n\t}\n\n\tret_val = phy->ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);\n\tE1000_WRITE_FLUSH(hw);\n\n\tusec_delay(phy->reset_delay_us);\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\tE1000_WRITE_FLUSH(hw);\n\n\tusec_delay(150);\n\n\tphy->ops.release(hw);\n\n\treturn phy->ops.get_cfg_done(hw);\n}\n\n/**\n * e1000_get_cfg_done_generic - Generic configuration done\n * @hw: pointer to the HW structure\n *\n * Generic function to wait 10 milli-seconds for configuration to complete\n * and return success.\n **/\ns32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)\n{\n\tDEBUGFUNC(\"e1000_get_cfg_done_generic\");\n\n\tmsec_delay_irq(10);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_phy_init_script_igp3 - Inits the IGP3 PHY\n * @hw: pointer to the HW structure\n *\n * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.\n **/\ns32 e1000_phy_init_script_igp3(struct e1000_hw *hw)\n{\n\tDEBUGOUT(\"Running IGP 3 PHY init script\\n\");\n\n\t/* PHY init IGP 3 */\n\t/* Enable rise/fall, 10-mode work in class-A */\n\thw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);\n\t/* Remove all caps from Replica path filter */\n\thw->phy.ops.write_reg(hw, 0x2F52, 0x0000);\n\t/* Bias trimming for ADC, AFE and Driver (Default) */\n\thw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);\n\t/* Increase Hybrid poly bias */\n\thw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);\n\t/* Add 4% to Tx amplitude in Gig mode */\n\thw->phy.ops.write_reg(hw, 0x2010, 0x10B0);\n\t/* Disable trimming (TTT) */\n\thw->phy.ops.write_reg(hw, 0x2011, 0x0000);\n\t/* Poly DC correction to 94.6% + 2% for all channels */\n\thw->phy.ops.write_reg(hw, 0x20DD, 0x249A);\n\t/* ABS DC correction to 95.9% */\n\thw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);\n\t/* BG temp curve trim */\n\thw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);\n\t/* Increasing ADC OPAMP stage 1 currents to max */\n\thw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);\n\t/* Force 1000 ( required for enabling PHY regs configuration) */\n\thw->phy.ops.write_reg(hw, 0x0000, 0x0140);\n\t/* Set upd_freq to 6 */\n\thw->phy.ops.write_reg(hw, 0x1F30, 0x1606);\n\t/* Disable NPDFE */\n\thw->phy.ops.write_reg(hw, 0x1F31, 0xB814);\n\t/* Disable adaptive fixed FFE (Default) */\n\thw->phy.ops.write_reg(hw, 0x1F35, 0x002A);\n\t/* Enable FFE hysteresis */\n\thw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);\n\t/* Fixed FFE for short cable lengths */\n\thw->phy.ops.write_reg(hw, 0x1F54, 0x0065);\n\t/* Fixed FFE for medium cable lengths */\n\thw->phy.ops.write_reg(hw, 0x1F55, 0x002A);\n\t/* Fixed FFE for long cable lengths */\n\thw->phy.ops.write_reg(hw, 0x1F56, 0x002A);\n\t/* Enable Adaptive Clip Threshold */\n\thw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);\n\t/* AHT reset limit to 1 */\n\thw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);\n\t/* Set AHT master delay to 127 msec */\n\thw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);\n\t/* Set scan bits for AHT */\n\thw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);\n\t/* Set AHT Preset bits */\n\thw->phy.ops.write_reg(hw, 0x1F79, 0x0210);\n\t/* Change integ_factor of channel A to 3 */\n\thw->phy.ops.write_reg(hw, 0x1895, 0x0003);\n\t/* Change prop_factor of channels BCD to 8 */\n\thw->phy.ops.write_reg(hw, 0x1796, 0x0008);\n\t/* Change cg_icount + enable integbp for channels BCD */\n\thw->phy.ops.write_reg(hw, 0x1798, 0xD008);\n\t/* Change cg_icount + enable integbp + change prop_factor_master\n\t * to 8 for channel A\n\t */\n\thw->phy.ops.write_reg(hw, 0x1898, 0xD918);\n\t/* Disable AHT in Slave mode on channel A */\n\thw->phy.ops.write_reg(hw, 0x187A, 0x0800);\n\t/* Enable LPLU and disable AN to 1000 in non-D0a states,\n\t * Enable SPD+B2B\n\t */\n\thw->phy.ops.write_reg(hw, 0x0019, 0x008D);\n\t/* Enable restart AN on an1000_dis change */\n\thw->phy.ops.write_reg(hw, 0x001B, 0x2080);\n\t/* Enable wh_fifo read clock in 10/100 modes */\n\thw->phy.ops.write_reg(hw, 0x0014, 0x0045);\n\t/* Restart AN, Speed selection is 1000 */\n\thw->phy.ops.write_reg(hw, 0x0000, 0x1340);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_phy_type_from_id - Get PHY type from id\n * @phy_id: phy_id read from the phy\n *\n * Returns the phy type from the id.\n **/\nenum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)\n{\n\tenum e1000_phy_type phy_type = e1000_phy_unknown;\n\n\tswitch (phy_id) {\n\tcase M88E1000_I_PHY_ID:\n\tcase M88E1000_E_PHY_ID:\n\tcase M88E1111_I_PHY_ID:\n\tcase M88E1011_I_PHY_ID:\n\tcase M88E1543_E_PHY_ID:\n\tcase I347AT4_E_PHY_ID:\n\tcase M88E1112_E_PHY_ID:\n\tcase M88E1340M_E_PHY_ID:\n\t\tphy_type = e1000_phy_m88;\n\t\tbreak;\n\tcase IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */\n\t\tphy_type = e1000_phy_igp_2;\n\t\tbreak;\n\tcase GG82563_E_PHY_ID:\n\t\tphy_type = e1000_phy_gg82563;\n\t\tbreak;\n\tcase IGP03E1000_E_PHY_ID:\n\t\tphy_type = e1000_phy_igp_3;\n\t\tbreak;\n\tcase IFE_E_PHY_ID:\n\tcase IFE_PLUS_E_PHY_ID:\n\tcase IFE_C_E_PHY_ID:\n\t\tphy_type = e1000_phy_ife;\n\t\tbreak;\n\tcase I82580_I_PHY_ID:\n\t\tphy_type = e1000_phy_82580;\n\t\tbreak;\n\tcase I210_I_PHY_ID:\n\t\tphy_type = e1000_phy_i210;\n\t\tbreak;\n\tdefault:\n\t\tphy_type = e1000_phy_unknown;\n\t\tbreak;\n\t}\n\treturn phy_type;\n}\n\n/**\n * e1000_determine_phy_address - Determines PHY address.\n * @hw: pointer to the HW structure\n *\n * This uses a trial and error method to loop through possible PHY\n * addresses. It tests each by reading the PHY ID registers and\n * checking for a match.\n **/\ns32 e1000_determine_phy_address(struct e1000_hw *hw)\n{\n\tu32 phy_addr = 0;\n\tu32 i;\n\tenum e1000_phy_type phy_type = e1000_phy_unknown;\n\n\thw->phy.id = phy_type;\n\n\tfor (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {\n\t\thw->phy.addr = phy_addr;\n\t\ti = 0;\n\n\t\tdo {\n\t\t\te1000_get_phy_id(hw);\n\t\t\tphy_type = e1000_get_phy_type_from_id(hw->phy.id);\n\n\t\t\t/* If phy_type is valid, break - we found our\n\t\t\t * PHY address\n\t\t\t */\n\t\t\tif (phy_type != e1000_phy_unknown)\n\t\t\t\treturn E1000_SUCCESS;\n\n\t\t\tmsec_delay(1);\n\t\t\ti++;\n\t\t} while (i < 10);\n\t}\n\n\treturn -E1000_ERR_PHY_TYPE;\n}\n\n/**\n * e1000_power_up_phy_copper - Restore copper link in case of PHY power down\n * @hw: pointer to the HW structure\n *\n * In the case of a PHY power down to save power, or to turn off link during a\n * driver unload, or wake on lan is not enabled, restore the link to previous\n * settings.\n **/\nvoid e1000_power_up_phy_copper(struct e1000_hw *hw)\n{\n\tu16 mii_reg = 0;\n\tu16 power_reg = 0;\n\n\t/* The PHY will retain its settings across a power down/up cycle */\n\thw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);\n\tmii_reg &= ~MII_CR_POWER_DOWN;\n\tif (hw->phy.type == e1000_phy_i210) {\n\t\thw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);\n\t\tpower_reg &= ~GS40G_CS_POWER_DOWN;\n\t\thw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);\n\t}\n\thw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);\n}\n\n/**\n * e1000_power_down_phy_copper - Restore copper link in case of PHY power down\n * @hw: pointer to the HW structure\n *\n * In the case of a PHY power down to save power, or to turn off link during a\n * driver unload, or wake on lan is not enabled, restore the link to previous\n * settings.\n **/\nvoid e1000_power_down_phy_copper(struct e1000_hw *hw)\n{\n\tu16 mii_reg = 0;\n\tu16 power_reg = 0;\n\n\t/* The PHY will retain its settings across a power down/up cycle */\n\thw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);\n\tmii_reg |= MII_CR_POWER_DOWN;\n\t/* i210 Phy requires an additional bit for power up/down */\n\tif (hw->phy.type == e1000_phy_i210) {\n\t\thw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);\n\t\tpower_reg |= GS40G_CS_POWER_DOWN;\n\t\thw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);\n\t}\n\thw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);\n\tmsec_delay(1);\n}\n\n/**\n * e1000_check_polarity_82577 - Checks the polarity.\n * @hw: pointer to the HW structure\n *\n * Success returns 0, Failure returns -E1000_ERR_PHY (-2)\n *\n * Polarity is determined based on the PHY specific status register.\n **/\ns32 e1000_check_polarity_82577(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\n\tDEBUGFUNC(\"e1000_check_polarity_82577\");\n\n\tret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);\n\n\tif (!ret_val)\n\t\tphy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)\n\t\t\t\t ? e1000_rev_polarity_reversed\n\t\t\t\t : e1000_rev_polarity_normal);\n\n\treturn ret_val;\n}\n\n/**\n * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY\n * @hw: pointer to the HW structure\n *\n * Calls the PHY setup function to force speed and duplex.\n **/\ns32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_phy_force_speed_duplex_82577\");\n\n\tret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\te1000_phy_force_speed_duplex_setup(hw, &phy_data);\n\n\tret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tusec_delay(1);\n\n\tif (phy->autoneg_wait_to_complete) {\n\t\tDEBUGOUT(\"Waiting for forced speed/duplex link on 82577 phy\\n\");\n\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tif (!link)\n\t\t\tDEBUGOUT(\"Link taking longer than expected.\\n\");\n\n\t\t/* Try once more */\n\t\tret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,\n\t\t\t\t\t\t 100000, &link);\n\t}\n\n\treturn ret_val;\n}\n\n/**\n * e1000_get_phy_info_82577 - Retrieve I82577 PHY information\n * @hw: pointer to the HW structure\n *\n * Read PHY status to determine if link is up. If link is up, then\n * set/determine 10base-T extended distance and polarity correction. Read\n * PHY port status to determine MDI/MDIx and speed. Based on the speed,\n * determine on the cable length, local and remote receiver.\n **/\ns32 e1000_get_phy_info_82577(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 data;\n\tbool link;\n\n\tDEBUGFUNC(\"e1000_get_phy_info_82577\");\n\n\tret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (!link) {\n\t\tDEBUGOUT(\"Phy info is only valid if link is up\\n\");\n\t\treturn -E1000_ERR_CONFIG;\n\t}\n\n\tphy->polarity_correction = true;\n\n\tret_val = e1000_check_polarity_82577(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tphy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);\n\n\tif ((data & I82577_PHY_STATUS2_SPEED_MASK) ==\n\t I82577_PHY_STATUS2_SPEED_1000MBPS) {\n\t\tret_val = hw->phy.ops.get_cable_length(hw);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);\n\t\tif (ret_val)\n\t\t\treturn ret_val;\n\n\t\tphy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)\n\t\t\t\t? e1000_1000t_rx_status_ok\n\t\t\t\t: e1000_1000t_rx_status_not_ok;\n\n\t\tphy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)\n\t\t\t\t ? e1000_1000t_rx_status_ok\n\t\t\t\t : e1000_1000t_rx_status_not_ok;\n\t} else {\n\t\tphy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;\n\t\tphy->local_rx = e1000_1000t_rx_status_undefined;\n\t\tphy->remote_rx = e1000_1000t_rx_status_undefined;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY\n * @hw: pointer to the HW structure\n *\n * Reads the diagnostic status register and verifies result is valid before\n * placing it in the phy_cable_length field.\n **/\ns32 e1000_get_cable_length_82577(struct e1000_hw *hw)\n{\n\tstruct e1000_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\tu16 phy_data, length;\n\n\tDEBUGFUNC(\"e1000_get_cable_length_82577\");\n\n\tret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tlength = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>\n\t\t I82577_DSTATUS_CABLE_LENGTH_SHIFT);\n\n\tif (length == E1000_CABLE_LENGTH_UNDEFINED)\n\t\treturn -E1000_ERR_PHY;\n\n\tphy->cable_length = length;\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_phy_reg_gs40g - Write GS40G PHY register\n * @hw: pointer to the HW structure\n * @offset: register offset to write to\n * @data: data to write at register offset\n *\n * Acquires semaphore, if necessary, then writes the data to PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\ns32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)\n{\n\ts32 ret_val;\n\tu16 page = offset >> GS40G_PAGE_SHIFT;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_gs40g\");\n\n\toffset = offset & GS40G_OFFSET_MASK;\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);\n\tif (ret_val)\n\t\tgoto release;\n\tret_val = e1000_write_phy_reg_mdic(hw, offset, data);\n\nrelease:\n\thw->phy.ops.release(hw);\n\treturn ret_val;\n}\n\n/**\n * e1000_read_phy_reg_gs40g - Read GS40G PHY register\n * @hw: pointer to the HW structure\n * @offset: lower half is register offset to read to\n * upper half is page to use.\n * @data: data to read at register offset\n *\n * Acquires semaphore, if necessary, then reads the data in the PHY register\n * at the offset. Release any acquired semaphores before exiting.\n **/\ns32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)\n{\n\ts32 ret_val;\n\tu16 page = offset >> GS40G_PAGE_SHIFT;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_gs40g\");\n\n\toffset = offset & GS40G_OFFSET_MASK;\n\tret_val = hw->phy.ops.acquire(hw);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);\n\tif (ret_val)\n\t\tgoto release;\n\tret_val = e1000_read_phy_reg_mdic(hw, offset, data);\n\nrelease:\n\thw->phy.ops.release(hw);\n\treturn ret_val;\n}\n\n/**\n * e1000_read_phy_reg_mphy - Read mPHY control register\n * @hw: pointer to the HW structure\n * @address: address to be read\n * @data: pointer to the read data\n *\n * Reads the mPHY control register in the PHY at offset and stores the\n * information read to data.\n **/\ns32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)\n{\n\tu32 mphy_ctrl = 0;\n\tbool locked = false;\n\tbool ready = false;\n\n\tDEBUGFUNC(\"e1000_read_phy_reg_mphy\");\n\n\t/* Check if mPHY is ready to read/write operations */\n\tready = e1000_is_mphy_ready(hw);\n\tif (!ready)\n\t\treturn -E1000_ERR_PHY;\n\n\t/* Check if mPHY access is disabled and enable it if so */\n\tmphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);\n\tif (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {\n\t\tlocked = true;\n\t\tready = e1000_is_mphy_ready(hw);\n\t\tif (!ready)\n\t\t\treturn -E1000_ERR_PHY;\n\t\tmphy_ctrl |= E1000_MPHY_ENA_ACCESS;\n\t\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);\n\t}\n\n\t/* Set the address that we want to read */\n\tready = e1000_is_mphy_ready(hw);\n\tif (!ready)\n\t\treturn -E1000_ERR_PHY;\n\n\t/* We mask address, because we want to use only current lane */\n\tmphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &\n\t\t~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |\n\t\t(address & E1000_MPHY_ADDRESS_MASK);\n\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);\n\n\t/* Read data from the address */\n\tready = e1000_is_mphy_ready(hw);\n\tif (!ready)\n\t\treturn -E1000_ERR_PHY;\n\t*data = E1000_READ_REG(hw, E1000_MPHY_DATA);\n\n\t/* Disable access to mPHY if it was originally disabled */\n\tif (locked)\n\t\tready = e1000_is_mphy_ready(hw);\n\t\tif (!ready)\n\t\t\treturn -E1000_ERR_PHY;\n\t\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,\n\t\t\t\tE1000_MPHY_DIS_ACCESS);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_write_phy_reg_mphy - Write mPHY control register\n * @hw: pointer to the HW structure\n * @address: address to write to\n * @data: data to write to register at offset\n * @line_override: used when we want to use different line than default one\n *\n * Writes data to mPHY control register.\n **/\ns32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,\n\t\t\t bool line_override)\n{\n\tu32 mphy_ctrl = 0;\n\tbool locked = false;\n\tbool ready = false;\n\n\tDEBUGFUNC(\"e1000_write_phy_reg_mphy\");\n\n\t/* Check if mPHY is ready to read/write operations */\n\tready = e1000_is_mphy_ready(hw);\n\tif (!ready)\n\t\treturn -E1000_ERR_PHY;\n\n\t/* Check if mPHY access is disabled and enable it if so */\n\tmphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);\n\tif (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {\n\t\tlocked = true;\n\t\tready = e1000_is_mphy_ready(hw);\n\t\tif (!ready)\n\t\t\treturn -E1000_ERR_PHY;\n\t\tmphy_ctrl |= E1000_MPHY_ENA_ACCESS;\n\t\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);\n\t}\n\n\t/* Set the address that we want to read */\n\tready = e1000_is_mphy_ready(hw);\n\tif (!ready)\n\t\treturn -E1000_ERR_PHY;\n\n\t/* We mask address, because we want to use only current lane */\n\tif (line_override)\n\t\tmphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;\n\telse\n\t\tmphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;\n\tmphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |\n\t\t(address & E1000_MPHY_ADDRESS_MASK);\n\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);\n\n\t/* Read data from the address */\n\tready = e1000_is_mphy_ready(hw);\n\tif (!ready)\n\t\treturn -E1000_ERR_PHY;\n\tE1000_WRITE_REG(hw, E1000_MPHY_DATA, data);\n\n\t/* Disable access to mPHY if it was originally disabled */\n\tif (locked)\n\t\tready = e1000_is_mphy_ready(hw);\n\t\tif (!ready)\n\t\t\treturn -E1000_ERR_PHY;\n\t\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,\n\t\t\t\tE1000_MPHY_DIS_ACCESS);\n\n\treturn E1000_SUCCESS;\n}\n\n/**\n * e1000_is_mphy_ready - Check if mPHY control register is not busy\n * @hw: pointer to the HW structure\n *\n * Returns mPHY control register status.\n **/\nbool e1000_is_mphy_ready(struct e1000_hw *hw)\n{\n\tu16 retry_count = 0;\n\tu32 mphy_ctrl = 0;\n\tbool ready = false;\n\n\twhile (retry_count < 2) {\n\t\tmphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);\n\t\tif (mphy_ctrl & E1000_MPHY_BUSY) {\n\t\t\tusec_delay(20);\n\t\t\tretry_count++;\n\t\t\tcontinue;\n\t\t}\n\t\tready = true;\n\t\tbreak;\n\t}\n\n\tif (!ready)\n\t\tDEBUGOUT(\"ERROR READING mPHY control register, phy is busy.\\n\");\n\n\treturn ready;\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_phy.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _E1000_PHY_H_\n#define _E1000_PHY_H_\n\nvoid e1000_init_phy_ops_generic(struct e1000_hw *hw);\ns32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);\nvoid e1000_null_phy_generic(struct e1000_hw *hw);\ns32 e1000_null_lplu_state(struct e1000_hw *hw, bool active);\ns32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_null_set_page(struct e1000_hw *hw, u16 data);\ns32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t u8 dev_addr, u8 *data);\ns32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t u8 dev_addr, u8 data);\ns32 e1000_check_downshift_generic(struct e1000_hw *hw);\ns32 e1000_check_polarity_m88(struct e1000_hw *hw);\ns32 e1000_check_polarity_igp(struct e1000_hw *hw);\ns32 e1000_check_polarity_ife(struct e1000_hw *hw);\ns32 e1000_check_reset_block_generic(struct e1000_hw *hw);\ns32 e1000_copper_link_setup_igp(struct e1000_hw *hw);\ns32 e1000_copper_link_setup_m88(struct e1000_hw *hw);\ns32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw);\ns32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);\ns32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);\ns32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);\ns32 e1000_get_cable_length_m88(struct e1000_hw *hw);\ns32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw);\ns32 e1000_get_cable_length_igp_2(struct e1000_hw *hw);\ns32 e1000_get_cfg_done_generic(struct e1000_hw *hw);\ns32 e1000_get_phy_id(struct e1000_hw *hw);\ns32 e1000_get_phy_info_igp(struct e1000_hw *hw);\ns32 e1000_get_phy_info_m88(struct e1000_hw *hw);\ns32 e1000_get_phy_info_ife(struct e1000_hw *hw);\ns32 e1000_phy_sw_reset_generic(struct e1000_hw *hw);\nvoid e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);\ns32 e1000_phy_hw_reset_generic(struct e1000_hw *hw);\ns32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw);\ns32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);\ns32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);\ns32 e1000_setup_copper_link_generic(struct e1000_hw *hw);\ns32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,\n\t\t\t\tu32 usec_interval, bool *success);\ns32 e1000_phy_init_script_igp3(struct e1000_hw *hw);\nenum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);\ns32 e1000_determine_phy_address(struct e1000_hw *hw);\ns32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);\ns32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);\nvoid e1000_power_up_phy_copper(struct e1000_hw *hw);\nvoid e1000_power_down_phy_copper(struct e1000_hw *hw);\ns32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);\ns32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data);\ns32 e1000_copper_link_setup_82577(struct e1000_hw *hw);\ns32 e1000_check_polarity_82577(struct e1000_hw *hw);\ns32 e1000_get_phy_info_82577(struct e1000_hw *hw);\ns32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);\ns32 e1000_get_cable_length_82577(struct e1000_hw *hw);\ns32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);\ns32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);\ns32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data);\ns32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,\n\t\t\t bool line_override);\nbool e1000_is_mphy_ready(struct e1000_hw *hw);\n\n#define E1000_MAX_PHY_ADDR\t\t8\n\n/* IGP01E1000 Specific Registers */\n#define IGP01E1000_PHY_PORT_CONFIG\t0x10 /* Port Config */\n#define IGP01E1000_PHY_PORT_STATUS\t0x11 /* Status */\n#define IGP01E1000_PHY_PORT_CTRL\t0x12 /* Control */\n#define IGP01E1000_PHY_LINK_HEALTH\t0x13 /* PHY Link Health */\n#define IGP02E1000_PHY_POWER_MGMT\t0x19 /* Power Management */\n#define IGP01E1000_PHY_PAGE_SELECT\t0x1F /* Page Select */\n#define BM_PHY_PAGE_SELECT\t\t22 /* Page Select for BM */\n#define IGP_PAGE_SHIFT\t\t\t5\n#define PHY_REG_MASK\t\t\t0x1F\n\n/* GS40G - I210 PHY defines */\n#define GS40G_PAGE_SELECT\t\t0x16\n#define GS40G_PAGE_SHIFT\t\t16\n#define GS40G_OFFSET_MASK\t\t0xFFFF\n#define GS40G_PAGE_2\t\t\t0x20000\n#define GS40G_MAC_REG2\t\t\t0x15\n#define GS40G_MAC_LB\t\t\t0x4140\n#define GS40G_MAC_SPEED_1G\t\t0X0006\n#define GS40G_COPPER_SPEC\t\t0x0010\n#define GS40G_CS_POWER_DOWN\t\t0x0002\n\n#define HV_INTC_FC_PAGE_START\t\t768\n#define I82578_ADDR_REG\t\t\t29\n#define I82577_ADDR_REG\t\t\t16\n#define I82577_CFG_REG\t\t\t22\n#define I82577_CFG_ASSERT_CRS_ON_TX\t(1 << 15)\n#define I82577_CFG_ENABLE_DOWNSHIFT\t(3 << 10) /* auto downshift */\n#define I82577_CTRL_REG\t\t\t23\n\n/* 82577 specific PHY registers */\n#define I82577_PHY_CTRL_2\t\t18\n#define I82577_PHY_LBK_CTRL\t\t19\n#define I82577_PHY_STATUS_2\t\t26\n#define I82577_PHY_DIAG_STATUS\t\t31\n\n/* I82577 PHY Status 2 */\n#define I82577_PHY_STATUS2_REV_POLARITY\t\t0x0400\n#define I82577_PHY_STATUS2_MDIX\t\t\t0x0800\n#define I82577_PHY_STATUS2_SPEED_MASK\t\t0x0300\n#define I82577_PHY_STATUS2_SPEED_1000MBPS\t0x0200\n\n/* I82577 PHY Control 2 */\n#define I82577_PHY_CTRL2_MANUAL_MDIX\t\t0x0200\n#define I82577_PHY_CTRL2_AUTO_MDI_MDIX\t\t0x0400\n#define I82577_PHY_CTRL2_MDIX_CFG_MASK\t\t0x0600\n\n/* I82577 PHY Diagnostics Status */\n#define I82577_DSTATUS_CABLE_LENGTH\t\t0x03FC\n#define I82577_DSTATUS_CABLE_LENGTH_SHIFT\t2\n\n/* 82580 PHY Power Management */\n#define E1000_82580_PHY_POWER_MGMT\t0xE14\n#define E1000_82580_PM_SPD\t\t0x0001 /* Smart Power Down */\n#define E1000_82580_PM_D0_LPLU\t\t0x0002 /* For D0a states */\n#define E1000_82580_PM_D3_LPLU\t\t0x0004 /* For all other states */\n#define E1000_82580_PM_GO_LINKD\t\t0x0020 /* Go Link Disconnect */\n\n#define E1000_MPHY_DIS_ACCESS\t\t0x80000000 /* disable_access bit */\n#define E1000_MPHY_ENA_ACCESS\t\t0x40000000 /* enable_access bit */\n#define E1000_MPHY_BUSY\t\t\t0x00010000 /* busy bit */\n#define E1000_MPHY_ADDRESS_FNC_OVERRIDE\t0x20000000 /* fnc_override bit */\n#define E1000_MPHY_ADDRESS_MASK\t\t0x0000FFFF /* address mask */\n\n#define IGP01E1000_PHY_PCS_INIT_REG\t0x00B4\n#define IGP01E1000_PHY_POLARITY_MASK\t0x0078\n\n#define IGP01E1000_PSCR_AUTO_MDIX\t0x1000\n#define IGP01E1000_PSCR_FORCE_MDI_MDIX\t0x2000 /* 0=MDI, 1=MDIX */\n\n#define IGP01E1000_PSCFR_SMART_SPEED\t0x0080\n\n#define IGP02E1000_PM_SPD\t\t0x0001 /* Smart Power Down */\n#define IGP02E1000_PM_D0_LPLU\t\t0x0002 /* For D0a states */\n#define IGP02E1000_PM_D3_LPLU\t\t0x0004 /* For all other states */\n\n#define IGP01E1000_PLHR_SS_DOWNGRADE\t0x8000\n\n#define IGP01E1000_PSSR_POLARITY_REVERSED\t0x0002\n#define IGP01E1000_PSSR_MDIX\t\t0x0800\n#define IGP01E1000_PSSR_SPEED_MASK\t0xC000\n#define IGP01E1000_PSSR_SPEED_1000MBPS\t0xC000\n\n#define IGP02E1000_PHY_CHANNEL_NUM\t4\n#define IGP02E1000_PHY_AGC_A\t\t0x11B1\n#define IGP02E1000_PHY_AGC_B\t\t0x12B1\n#define IGP02E1000_PHY_AGC_C\t\t0x14B1\n#define IGP02E1000_PHY_AGC_D\t\t0x18B1\n\n#define IGP02E1000_AGC_LENGTH_SHIFT\t9 /* Course=15:13, Fine=12:9 */\n#define IGP02E1000_AGC_LENGTH_MASK\t0x7F\n#define IGP02E1000_AGC_RANGE\t\t15\n\n#define E1000_CABLE_LENGTH_UNDEFINED\t0xFF\n\n#define E1000_KMRNCTRLSTA_OFFSET\t0x001F0000\n#define E1000_KMRNCTRLSTA_OFFSET_SHIFT\t16\n#define E1000_KMRNCTRLSTA_REN\t\t0x00200000\n#define E1000_KMRNCTRLSTA_DIAG_OFFSET\t0x3 /* Kumeran Diagnostic */\n#define E1000_KMRNCTRLSTA_TIMEOUTS\t0x4 /* Kumeran Timeouts */\n#define E1000_KMRNCTRLSTA_INBAND_PARAM\t0x9 /* Kumeran InBand Parameters */\n#define E1000_KMRNCTRLSTA_IBIST_DISABLE\t0x0200 /* Kumeran IBIST Disable */\n#define E1000_KMRNCTRLSTA_DIAG_NELPBK\t0x1000 /* Nearend Loopback mode */\n\n#define IFE_PHY_EXTENDED_STATUS_CONTROL\t0x10\n#define IFE_PHY_SPECIAL_CONTROL\t\t0x11 /* 100BaseTx PHY Special Ctrl */\n#define IFE_PHY_SPECIAL_CONTROL_LED\t0x1B /* PHY Special and LED Ctrl */\n#define IFE_PHY_MDIX_CONTROL\t\t0x1C /* MDI/MDI-X Control */\n\n/* IFE PHY Extended Status Control */\n#define IFE_PESC_POLARITY_REVERSED\t0x0100\n\n/* IFE PHY Special Control */\n#define IFE_PSC_AUTO_POLARITY_DISABLE\t0x0010\n#define IFE_PSC_FORCE_POLARITY\t\t0x0020\n\n/* IFE PHY Special Control and LED Control */\n#define IFE_PSCL_PROBE_MODE\t\t0x0020\n#define IFE_PSCL_PROBE_LEDS_OFF\t\t0x0006 /* Force LEDs 0 and 2 off */\n#define IFE_PSCL_PROBE_LEDS_ON\t\t0x0007 /* Force LEDs 0 and 2 on */\n\n/* IFE PHY MDIX Control */\n#define IFE_PMC_MDIX_STATUS\t\t0x0020 /* 1=MDI-X, 0=MDI */\n#define IFE_PMC_FORCE_MDIX\t\t0x0040 /* 1=force MDI-X, 0=force MDI */\n#define IFE_PMC_AUTO_MDIX\t\t0x0080 /* 1=enable auto, 0=disable */\n\n/* SFP modules ID memory locations */\n#define E1000_SFF_IDENTIFIER_OFFSET\t0x00\n#define E1000_SFF_IDENTIFIER_SFF\t0x02\n#define E1000_SFF_IDENTIFIER_SFP\t0x03\n\n#define E1000_SFF_ETH_FLAGS_OFFSET\t0x06\n/* Flags for SFP modules compatible with ETH up to 1Gb */\nstruct sfp_e1000_flags {\n\tu8 e1000_base_sx:1;\n\tu8 e1000_base_lx:1;\n\tu8 e1000_base_cx:1;\n\tu8 e1000_base_t:1;\n\tu8 e100_base_lx:1;\n\tu8 e100_base_fx:1;\n\tu8 e10_base_bx10:1;\n\tu8 e10_base_px:1;\n};\n\n/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */\n#define E1000_SFF_VENDOR_OUI_TYCO\t0x00407600\n#define E1000_SFF_VENDOR_OUI_FTL\t0x00906500\n#define E1000_SFF_VENDOR_OUI_AVAGO\t0x00176A00\n#define E1000_SFF_VENDOR_OUI_INTEL\t0x001B2100\n\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_regs.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _E1000_REGS_H_\n#define _E1000_REGS_H_\n\n#define E1000_CTRL\t0x00000 /* Device Control - RW */\n#define E1000_STATUS\t0x00008 /* Device Status - RO */\n#define E1000_EECD\t0x00010 /* EEPROM/Flash Control - RW */\n#define E1000_EERD\t0x00014 /* EEPROM Read - RW */\n#define E1000_CTRL_EXT\t0x00018 /* Extended Device Control - RW */\n#define E1000_FLA\t0x0001C /* Flash Access - RW */\n#define E1000_MDIC\t0x00020 /* MDI Control - RW */\n#define E1000_MDICNFG\t0x00E04 /* MDI Config - RW */\n#define E1000_REGISTER_SET_SIZE\t\t0x20000 /* CSR Size */\n#define E1000_EEPROM_INIT_CTRL_WORD_2\t0x0F /* EEPROM Init Ctrl Word 2 */\n#define E1000_EEPROM_PCIE_CTRL_WORD_2\t0x28 /* EEPROM PCIe Ctrl Word 2 */\n#define E1000_BARCTRL\t\t\t0x5BBC /* BAR ctrl reg */\n#define E1000_BARCTRL_FLSIZE\t\t0x0700 /* BAR ctrl Flsize */\n#define E1000_BARCTRL_CSRSIZE\t\t0x2000 /* BAR ctrl CSR size */\n#define E1000_MPHY_ADDR_CTRL\t0x0024 /* GbE MPHY Address Control */\n#define E1000_MPHY_DATA\t\t0x0E10 /* GBE MPHY Data */\n#define E1000_MPHY_STAT\t\t0x0E0C /* GBE MPHY Statistics */\n#define E1000_PPHY_CTRL\t\t0x5b48 /* PCIe PHY Control */\n#define E1000_I350_BARCTRL\t\t0x5BFC /* BAR ctrl reg */\n#define E1000_I350_DTXMXPKTSZ\t\t0x355C /* Maximum sent packet size reg*/\n#define E1000_SCTL\t0x00024 /* SerDes Control - RW */\n#define E1000_FCAL\t0x00028 /* Flow Control Address Low - RW */\n#define E1000_FCAH\t0x0002C /* Flow Control Address High -RW */\n#define E1000_FCT\t0x00030 /* Flow Control Type - RW */\n#define E1000_CONNSW\t0x00034 /* Copper/Fiber switch control - RW */\n#define E1000_VET\t0x00038 /* VLAN Ether Type - RW */\n#define E1000_ICR\t0x000C0 /* Interrupt Cause Read - R/clr */\n#define E1000_ITR\t0x000C4 /* Interrupt Throttling Rate - RW */\n#define E1000_ICS\t0x000C8 /* Interrupt Cause Set - WO */\n#define E1000_IMS\t0x000D0 /* Interrupt Mask Set - RW */\n#define E1000_IMC\t0x000D8 /* Interrupt Mask Clear - WO */\n#define E1000_IAM\t0x000E0 /* Interrupt Acknowledge Auto Mask */\n#define E1000_RCTL\t0x00100 /* Rx Control - RW */\n#define E1000_FCTTV\t0x00170 /* Flow Control Transmit Timer Value - RW */\n#define E1000_TXCW\t0x00178 /* Tx Configuration Word - RW */\n#define E1000_RXCW\t0x00180 /* Rx Configuration Word - RO */\n#define E1000_EICR\t0x01580 /* Ext. Interrupt Cause Read - R/clr */\n#define E1000_EITR(_n)\t(0x01680 + (0x4 * (_n)))\n#define E1000_EICS\t0x01520 /* Ext. Interrupt Cause Set - W0 */\n#define E1000_EIMS\t0x01524 /* Ext. Interrupt Mask Set/Read - RW */\n#define E1000_EIMC\t0x01528 /* Ext. Interrupt Mask Clear - WO */\n#define E1000_EIAC\t0x0152C /* Ext. Interrupt Auto Clear - RW */\n#define E1000_EIAM\t0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */\n#define E1000_GPIE\t0x01514 /* General Purpose Interrupt Enable - RW */\n#define E1000_IVAR0\t0x01700 /* Interrupt Vector Allocation (array) - RW */\n#define E1000_IVAR_MISC\t0x01740 /* IVAR for \"other\" causes - RW */\n#define E1000_TCTL\t0x00400 /* Tx Control - RW */\n#define E1000_TCTL_EXT\t0x00404 /* Extended Tx Control - RW */\n#define E1000_TIPG\t0x00410 /* Tx Inter-packet gap -RW */\n#define E1000_AIT\t0x00458 /* Adaptive Interframe Spacing Throttle - RW */\n#define E1000_LEDCTL\t0x00E00 /* LED Control - RW */\n#define E1000_LEDMUX\t0x08130 /* LED MUX Control */\n#define E1000_EXTCNF_CTRL\t0x00F00 /* Extended Configuration Control */\n#define E1000_EXTCNF_SIZE\t0x00F08 /* Extended Configuration Size */\n#define E1000_PHY_CTRL\t0x00F10 /* PHY Control Register in CSR */\n#define E1000_PBA\t0x01000 /* Packet Buffer Allocation - RW */\n#define E1000_PBS\t0x01008 /* Packet Buffer Size */\n#define E1000_EEMNGCTL\t0x01010 /* MNG EEprom Control */\n#define E1000_EEARBC\t0x01024 /* EEPROM Auto Read Bus Control */\n#define E1000_EEWR\t0x0102C /* EEPROM Write Register - RW */\n#define E1000_FLOP\t0x0103C /* FLASH Opcode Register */\n#define E1000_I2CCMD\t0x01028 /* SFPI2C Command Register - RW */\n#define E1000_I2CPARAMS\t0x0102C /* SFPI2C Parameters Register - RW */\n#define E1000_I2CBB_EN\t0x00000100 /* I2C - Bit Bang Enable */\n#define E1000_I2C_CLK_OUT\t0x00000200 /* I2C- Clock */\n#define E1000_I2C_DATA_OUT\t0x00000400 /* I2C- Data Out */\n#define E1000_I2C_DATA_OE_N\t0x00000800 /* I2C- Data Output Enable */\n#define E1000_I2C_DATA_IN\t0x00001000 /* I2C- Data In */\n#define E1000_I2C_CLK_OE_N\t0x00002000 /* I2C- Clock Output Enable */\n#define E1000_I2C_CLK_IN\t0x00004000 /* I2C- Clock In */\n#define E1000_I2C_CLK_STRETCH_DIS\t0x00008000 /* I2C- Dis Clk Stretching */\n#define E1000_WDSTP\t0x01040 /* Watchdog Setup - RW */\n#define E1000_SWDSTS\t0x01044 /* SW Device Status - RW */\n#define E1000_FRTIMER\t0x01048 /* Free Running Timer - RW */\n#define E1000_TCPTIMER\t0x0104C /* TCP Timer - RW */\n#define E1000_VPDDIAG\t0x01060 /* VPD Diagnostic - RO */\n#define E1000_ICR_V2\t0x01500 /* Intr Cause - new location - RC */\n#define E1000_ICS_V2\t0x01504 /* Intr Cause Set - new location - WO */\n#define E1000_IMS_V2\t0x01508 /* Intr Mask Set/Read - new location - RW */\n#define E1000_IMC_V2\t0x0150C /* Intr Mask Clear - new location - WO */\n#define E1000_IAM_V2\t0x01510 /* Intr Ack Auto Mask - new location - RW */\n#define E1000_ERT\t0x02008 /* Early Rx Threshold - RW */\n#define E1000_FCRTL\t0x02160 /* Flow Control Receive Threshold Low - RW */\n#define E1000_FCRTH\t0x02168 /* Flow Control Receive Threshold High - RW */\n#define E1000_PSRCTL\t0x02170 /* Packet Split Receive Control - RW */\n#define E1000_RDFH\t0x02410 /* Rx Data FIFO Head - RW */\n#define E1000_RDFT\t0x02418 /* Rx Data FIFO Tail - RW */\n#define E1000_RDFHS\t0x02420 /* Rx Data FIFO Head Saved - RW */\n#define E1000_RDFTS\t0x02428 /* Rx Data FIFO Tail Saved - RW */\n#define E1000_RDFPC\t0x02430 /* Rx Data FIFO Packet Count - RW */\n#define E1000_PBRTH\t0x02458 /* PB Rx Arbitration Threshold - RW */\n#define E1000_FCRTV\t0x02460 /* Flow Control Refresh Timer Value - RW */\n/* Split and Replication Rx Control - RW */\n#define E1000_RDPUMB\t0x025CC /* DMA Rx Descriptor uC Mailbox - RW */\n#define E1000_RDPUAD\t0x025D0 /* DMA Rx Descriptor uC Addr Command - RW */\n#define E1000_RDPUWD\t0x025D4 /* DMA Rx Descriptor uC Data Write - RW */\n#define E1000_RDPURD\t0x025D8 /* DMA Rx Descriptor uC Data Read - RW */\n#define E1000_RDPUCTL\t0x025DC /* DMA Rx Descriptor uC Control - RW */\n#define E1000_PBDIAG\t0x02458 /* Packet Buffer Diagnostic - RW */\n#define E1000_RXPBS\t0x02404 /* Rx Packet Buffer Size - RW */\n#define E1000_IRPBS\t0x02404 /* Same as RXPBS, renamed for newer Si - RW */\n#define E1000_PBRWAC\t0x024E8 /* Rx packet buffer wrap around counter - RO */\n#define E1000_RDTR\t0x02820 /* Rx Delay Timer - RW */\n#define E1000_RADV\t0x0282C /* Rx Interrupt Absolute Delay Timer - RW */\n#define E1000_EMIADD\t0x10 /* Extended Memory Indirect Address */\n#define E1000_EMIDATA\t0x11 /* Extended Memory Indirect Data */\n#define E1000_SRWR\t\t0x12018 /* Shadow Ram Write Register - RW */\n#define E1000_I210_FLMNGCTL\t0x12038\n#define E1000_I210_FLMNGDATA\t0x1203C\n#define E1000_I210_FLMNGCNT\t0x12040\n\n#define E1000_I210_FLSWCTL\t0x12048\n#define E1000_I210_FLSWDATA\t0x1204C\n#define E1000_I210_FLSWCNT\t0x12050\n\n#define E1000_I210_FLA\t\t0x1201C\n\n#define E1000_INVM_DATA_REG(_n)\t(0x12120 + 4*(_n))\n#define E1000_INVM_SIZE\t\t64 /* Number of INVM Data Registers */\n\n/* QAV Tx mode control register */\n#define E1000_I210_TQAVCTRL\t0x3570\n\n/* QAV Tx mode control register bitfields masks */\n/* QAV enable */\n#define E1000_TQAVCTRL_MODE\t\t\t(1 << 0)\n/* Fetching arbitration type */\n#define E1000_TQAVCTRL_FETCH_ARB\t\t(1 << 4)\n/* Fetching timer enable */\n#define E1000_TQAVCTRL_FETCH_TIMER_ENABLE\t(1 << 5)\n/* Launch arbitration type */\n#define E1000_TQAVCTRL_LAUNCH_ARB\t\t(1 << 8)\n/* Launch timer enable */\n#define E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE\t(1 << 9)\n/* SP waits for SR enable */\n#define E1000_TQAVCTRL_SP_WAIT_SR\t\t(1 << 10)\n/* Fetching timer correction */\n#define E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET\t16\n#define E1000_TQAVCTRL_FETCH_TIMER_DELTA\t\\\n\t\t\t(0xFFFF << E1000_TQAVCTRL_FETCH_TIMER_DELTA_OFFSET)\n\n/* High credit registers where _n can be 0 or 1. */\n#define E1000_I210_TQAVHC(_n)\t\t\t(0x300C + 0x40 * (_n))\n\n/* Queues fetch arbitration priority control register */\n#define E1000_I210_TQAVARBCTRL\t\t\t0x3574\n/* Queues priority masks where _n and _p can be 0-3. */\n#define E1000_TQAVARBCTRL_QUEUE_PRI(_n, _p)\t((_p) << (2 * _n))\n/* QAV Tx mode control registers where _n can be 0 or 1. */\n#define E1000_I210_TQAVCC(_n)\t\t\t(0x3004 + 0x40 * (_n))\n\n/* QAV Tx mode control register bitfields masks */\n#define E1000_TQAVCC_IDLE_SLOPE\t\t0xFFFF /* Idle slope */\n#define E1000_TQAVCC_KEEP_CREDITS\t(1 << 30) /* Keep credits opt enable */\n#define E1000_TQAVCC_QUEUE_MODE\t\t(1 << 31) /* SP vs. SR Tx mode */\n\n/* Good transmitted packets counter registers */\n#define E1000_PQGPTC(_n)\t\t(0x010014 + (0x100 * (_n)))\n\n/* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */\n#define E1000_I210_TXPBS_SIZE(_n, _s)\t((_s) << (6 * _n))\n\n#define E1000_MMDAC\t\t\t13 /* MMD Access Control */\n#define E1000_MMDAAD\t\t\t14 /* MMD Access Address/Data */\n\n/* Convenience macros\n *\n * Note: \"_n\" is the queue number of the register to be written to.\n *\n * Example usage:\n * E1000_RDBAL_REG(current_rx_queue)\n */\n#define E1000_RDBAL(_n)\t((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C000 + ((_n) * 0x40)))\n#define E1000_RDBAH(_n)\t((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C004 + ((_n) * 0x40)))\n#define E1000_RDLEN(_n)\t((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C008 + ((_n) * 0x40)))\n#define E1000_SRRCTL(_n)\t((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \\\n\t\t\t\t (0x0C00C + ((_n) * 0x40)))\n#define E1000_RDH(_n)\t((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C010 + ((_n) * 0x40)))\n#define E1000_RXCTL(_n)\t((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C014 + ((_n) * 0x40)))\n#define E1000_DCA_RXCTRL(_n)\tE1000_RXCTL(_n)\n#define E1000_RDT(_n)\t((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C018 + ((_n) * 0x40)))\n#define E1000_RXDCTL(_n)\t((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \\\n\t\t\t\t (0x0C028 + ((_n) * 0x40)))\n#define E1000_RQDPC(_n)\t((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \\\n\t\t\t (0x0C030 + ((_n) * 0x40)))\n#define E1000_TDBAL(_n)\t((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \\\n\t\t\t (0x0E000 + ((_n) * 0x40)))\n#define E1000_TDBAH(_n)\t((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \\\n\t\t\t (0x0E004 + ((_n) * 0x40)))\n#define E1000_TDLEN(_n)\t((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \\\n\t\t\t (0x0E008 + ((_n) * 0x40)))\n#define E1000_TDH(_n)\t((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \\\n\t\t\t (0x0E010 + ((_n) * 0x40)))\n#define E1000_TXCTL(_n)\t((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \\\n\t\t\t (0x0E014 + ((_n) * 0x40)))\n#define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)\n#define E1000_TDT(_n)\t((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \\\n\t\t\t (0x0E018 + ((_n) * 0x40)))\n#define E1000_TXDCTL(_n)\t((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \\\n\t\t\t\t (0x0E028 + ((_n) * 0x40)))\n#define E1000_TDWBAL(_n)\t((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \\\n\t\t\t\t (0x0E038 + ((_n) * 0x40)))\n#define E1000_TDWBAH(_n)\t((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \\\n\t\t\t\t (0x0E03C + ((_n) * 0x40)))\n#define E1000_TARC(_n)\t\t(0x03840 + ((_n) * 0x100))\n#define E1000_RSRPD\t\t0x02C00 /* Rx Small Packet Detect - RW */\n#define E1000_RAID\t\t0x02C08 /* Receive Ack Interrupt Delay - RW */\n#define E1000_KABGTXD\t\t0x03004 /* AFE Band Gap Transmit Ref Data */\n#define E1000_PSRTYPE(_i)\t(0x05480 + ((_i) * 4))\n#define E1000_RAL(_i)\t\t(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \\\n\t\t\t\t (0x054E0 + ((_i - 16) * 8)))\n#define E1000_RAH(_i)\t\t(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \\\n\t\t\t\t (0x054E4 + ((_i - 16) * 8)))\n#define E1000_SHRAL(_i)\t\t(0x05438 + ((_i) * 8))\n#define E1000_SHRAH(_i)\t\t(0x0543C + ((_i) * 8))\n#define E1000_IP4AT_REG(_i)\t(0x05840 + ((_i) * 8))\n#define E1000_IP6AT_REG(_i)\t(0x05880 + ((_i) * 4))\n#define E1000_WUPM_REG(_i)\t(0x05A00 + ((_i) * 4))\n#define E1000_FFMT_REG(_i)\t(0x09000 + ((_i) * 8))\n#define E1000_FFVT_REG(_i)\t(0x09800 + ((_i) * 8))\n#define E1000_FFLT_REG(_i)\t(0x05F00 + ((_i) * 8))\n#define E1000_PBSLAC\t\t0x03100 /* Pkt Buffer Slave Access Control */\n#define E1000_PBSLAD(_n)\t(0x03110 + (0x4 * (_n))) /* Pkt Buffer DWORD */\n#define E1000_TXPBS\t\t0x03404 /* Tx Packet Buffer Size - RW */\n/* Same as TXPBS, renamed for newer Si - RW */\n#define E1000_ITPBS\t\t0x03404\n#define E1000_TDFH\t\t0x03410 /* Tx Data FIFO Head - RW */\n#define E1000_TDFT\t\t0x03418 /* Tx Data FIFO Tail - RW */\n#define E1000_TDFHS\t\t0x03420 /* Tx Data FIFO Head Saved - RW */\n#define E1000_TDFTS\t\t0x03428 /* Tx Data FIFO Tail Saved - RW */\n#define E1000_TDFPC\t\t0x03430 /* Tx Data FIFO Packet Count - RW */\n#define E1000_TDPUMB\t\t0x0357C /* DMA Tx Desc uC Mail Box - RW */\n#define E1000_TDPUAD\t\t0x03580 /* DMA Tx Desc uC Addr Command - RW */\n#define E1000_TDPUWD\t\t0x03584 /* DMA Tx Desc uC Data Write - RW */\n#define E1000_TDPURD\t\t0x03588 /* DMA Tx Desc uC Data Read - RW */\n#define E1000_TDPUCTL\t\t0x0358C /* DMA Tx Desc uC Control - RW */\n#define E1000_DTXCTL\t\t0x03590 /* DMA Tx Control - RW */\n#define E1000_DTXTCPFLGL\t0x0359C /* DMA Tx Control flag low - RW */\n#define E1000_DTXTCPFLGH\t0x035A0 /* DMA Tx Control flag high - RW */\n/* DMA Tx Max Total Allow Size Reqs - RW */\n#define E1000_DTXMXSZRQ\t\t0x03540\n#define E1000_TIDV\t0x03820 /* Tx Interrupt Delay Value - RW */\n#define E1000_TADV\t0x0382C /* Tx Interrupt Absolute Delay Val - RW */\n#define E1000_CRCERRS\t0x04000 /* CRC Error Count - R/clr */\n#define E1000_ALGNERRC\t0x04004 /* Alignment Error Count - R/clr */\n#define E1000_SYMERRS\t0x04008 /* Symbol Error Count - R/clr */\n#define E1000_RXERRC\t0x0400C /* Receive Error Count - R/clr */\n#define E1000_MPC\t0x04010 /* Missed Packet Count - R/clr */\n#define E1000_SCC\t0x04014 /* Single Collision Count - R/clr */\n#define E1000_ECOL\t0x04018 /* Excessive Collision Count - R/clr */\n#define E1000_MCC\t0x0401C /* Multiple Collision Count - R/clr */\n#define E1000_LATECOL\t0x04020 /* Late Collision Count - R/clr */\n#define E1000_COLC\t0x04028 /* Collision Count - R/clr */\n#define E1000_DC\t0x04030 /* Defer Count - R/clr */\n#define E1000_TNCRS\t0x04034 /* Tx-No CRS - R/clr */\n#define E1000_SEC\t0x04038 /* Sequence Error Count - R/clr */\n#define E1000_CEXTERR\t0x0403C /* Carrier Extension Error Count - R/clr */\n#define E1000_RLEC\t0x04040 /* Receive Length Error Count - R/clr */\n#define E1000_XONRXC\t0x04048 /* XON Rx Count - R/clr */\n#define E1000_XONTXC\t0x0404C /* XON Tx Count - R/clr */\n#define E1000_XOFFRXC\t0x04050 /* XOFF Rx Count - R/clr */\n#define E1000_XOFFTXC\t0x04054 /* XOFF Tx Count - R/clr */\n#define E1000_FCRUC\t0x04058 /* Flow Control Rx Unsupported Count- R/clr */\n#define E1000_PRC64\t0x0405C /* Packets Rx (64 bytes) - R/clr */\n#define E1000_PRC127\t0x04060 /* Packets Rx (65-127 bytes) - R/clr */\n#define E1000_PRC255\t0x04064 /* Packets Rx (128-255 bytes) - R/clr */\n#define E1000_PRC511\t0x04068 /* Packets Rx (255-511 bytes) - R/clr */\n#define E1000_PRC1023\t0x0406C /* Packets Rx (512-1023 bytes) - R/clr */\n#define E1000_PRC1522\t0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */\n#define E1000_GPRC\t0x04074 /* Good Packets Rx Count - R/clr */\n#define E1000_BPRC\t0x04078 /* Broadcast Packets Rx Count - R/clr */\n#define E1000_MPRC\t0x0407C /* Multicast Packets Rx Count - R/clr */\n#define E1000_GPTC\t0x04080 /* Good Packets Tx Count - R/clr */\n#define E1000_GORCL\t0x04088 /* Good Octets Rx Count Low - R/clr */\n#define E1000_GORCH\t0x0408C /* Good Octets Rx Count High - R/clr */\n#define E1000_GOTCL\t0x04090 /* Good Octets Tx Count Low - R/clr */\n#define E1000_GOTCH\t0x04094 /* Good Octets Tx Count High - R/clr */\n#define E1000_RNBC\t0x040A0 /* Rx No Buffers Count - R/clr */\n#define E1000_RUC\t0x040A4 /* Rx Undersize Count - R/clr */\n#define E1000_RFC\t0x040A8 /* Rx Fragment Count - R/clr */\n#define E1000_ROC\t0x040AC /* Rx Oversize Count - R/clr */\n#define E1000_RJC\t0x040B0 /* Rx Jabber Count - R/clr */\n#define E1000_MGTPRC\t0x040B4 /* Management Packets Rx Count - R/clr */\n#define E1000_MGTPDC\t0x040B8 /* Management Packets Dropped Count - R/clr */\n#define E1000_MGTPTC\t0x040BC /* Management Packets Tx Count - R/clr */\n#define E1000_TORL\t0x040C0 /* Total Octets Rx Low - R/clr */\n#define E1000_TORH\t0x040C4 /* Total Octets Rx High - R/clr */\n#define E1000_TOTL\t0x040C8 /* Total Octets Tx Low - R/clr */\n#define E1000_TOTH\t0x040CC /* Total Octets Tx High - R/clr */\n#define E1000_TPR\t0x040D0 /* Total Packets Rx - R/clr */\n#define E1000_TPT\t0x040D4 /* Total Packets Tx - R/clr */\n#define E1000_PTC64\t0x040D8 /* Packets Tx (64 bytes) - R/clr */\n#define E1000_PTC127\t0x040DC /* Packets Tx (65-127 bytes) - R/clr */\n#define E1000_PTC255\t0x040E0 /* Packets Tx (128-255 bytes) - R/clr */\n#define E1000_PTC511\t0x040E4 /* Packets Tx (256-511 bytes) - R/clr */\n#define E1000_PTC1023\t0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */\n#define E1000_PTC1522\t0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */\n#define E1000_MPTC\t0x040F0 /* Multicast Packets Tx Count - R/clr */\n#define E1000_BPTC\t0x040F4 /* Broadcast Packets Tx Count - R/clr */\n#define E1000_TSCTC\t0x040F8 /* TCP Segmentation Context Tx - R/clr */\n#define E1000_TSCTFC\t0x040FC /* TCP Segmentation Context Tx Fail - R/clr */\n#define E1000_IAC\t0x04100 /* Interrupt Assertion Count */\n#define E1000_ICRXPTC\t0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */\n#define E1000_ICRXATC\t0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */\n#define E1000_ICTXPTC\t0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */\n#define E1000_ICTXATC\t0x04110 /* Interrupt Cause Tx Abs Timer Expire Count */\n#define E1000_ICTXQEC\t0x04118 /* Interrupt Cause Tx Queue Empty Count */\n#define E1000_ICTXQMTC\t0x0411C /* Interrupt Cause Tx Queue Min Thresh Count */\n#define E1000_ICRXDMTC\t0x04120 /* Interrupt Cause Rx Desc Min Thresh Count */\n#define E1000_ICRXOC\t0x04124 /* Interrupt Cause Receiver Overrun Count */\n\n/* Virtualization statistical counters */\n#define E1000_PFVFGPRC(_n)\t(0x010010 + (0x100 * (_n)))\n#define E1000_PFVFGPTC(_n)\t(0x010014 + (0x100 * (_n)))\n#define E1000_PFVFGORC(_n)\t(0x010018 + (0x100 * (_n)))\n#define E1000_PFVFGOTC(_n)\t(0x010034 + (0x100 * (_n)))\n#define E1000_PFVFMPRC(_n)\t(0x010038 + (0x100 * (_n)))\n#define E1000_PFVFGPRLBC(_n)\t(0x010040 + (0x100 * (_n)))\n#define E1000_PFVFGPTLBC(_n)\t(0x010044 + (0x100 * (_n)))\n#define E1000_PFVFGORLBC(_n)\t(0x010048 + (0x100 * (_n)))\n#define E1000_PFVFGOTLBC(_n)\t(0x010050 + (0x100 * (_n)))\n\n/* LinkSec */\n#define E1000_LSECTXUT\t\t0x04300 /* Tx Untagged Pkt Cnt */\n#define E1000_LSECTXPKTE\t0x04304 /* Encrypted Tx Pkts Cnt */\n#define E1000_LSECTXPKTP\t0x04308 /* Protected Tx Pkt Cnt */\n#define E1000_LSECTXOCTE\t0x0430C /* Encrypted Tx Octets Cnt */\n#define E1000_LSECTXOCTP\t0x04310 /* Protected Tx Octets Cnt */\n#define E1000_LSECRXUT\t\t0x04314 /* Untagged non-Strict Rx Pkt Cnt */\n#define E1000_LSECRXOCTD\t0x0431C /* Rx Octets Decrypted Count */\n#define E1000_LSECRXOCTV\t0x04320 /* Rx Octets Validated */\n#define E1000_LSECRXBAD\t\t0x04324 /* Rx Bad Tag */\n#define E1000_LSECRXNOSCI\t0x04328 /* Rx Packet No SCI Count */\n#define E1000_LSECRXUNSCI\t0x0432C /* Rx Packet Unknown SCI Count */\n#define E1000_LSECRXUNCH\t0x04330 /* Rx Unchecked Packets Count */\n#define E1000_LSECRXDELAY\t0x04340 /* Rx Delayed Packet Count */\n#define E1000_LSECRXLATE\t0x04350 /* Rx Late Packets Count */\n#define E1000_LSECRXOK(_n)\t(0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */\n#define E1000_LSECRXINV(_n)\t(0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */\n#define E1000_LSECRXNV(_n)\t(0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */\n#define E1000_LSECRXUNSA\t0x043C0 /* Rx Unused SA Count */\n#define E1000_LSECRXNUSA\t0x043D0 /* Rx Not Using SA Count */\n#define E1000_LSECTXCAP\t\t0x0B000 /* Tx Capabilities Register - RO */\n#define E1000_LSECRXCAP\t\t0x0B300 /* Rx Capabilities Register - RO */\n#define E1000_LSECTXCTRL\t0x0B004 /* Tx Control - RW */\n#define E1000_LSECRXCTRL\t0x0B304 /* Rx Control - RW */\n#define E1000_LSECTXSCL\t\t0x0B008 /* Tx SCI Low - RW */\n#define E1000_LSECTXSCH\t\t0x0B00C /* Tx SCI High - RW */\n#define E1000_LSECTXSA\t\t0x0B010 /* Tx SA0 - RW */\n#define E1000_LSECTXPN0\t\t0x0B018 /* Tx SA PN 0 - RW */\n#define E1000_LSECTXPN1\t\t0x0B01C /* Tx SA PN 1 - RW */\n#define E1000_LSECRXSCL\t\t0x0B3D0 /* Rx SCI Low - RW */\n#define E1000_LSECRXSCH\t\t0x0B3E0 /* Rx SCI High - RW */\n/* LinkSec Tx 128-bit Key 0 - WO */\n#define E1000_LSECTXKEY0(_n)\t(0x0B020 + (0x04 * (_n)))\n/* LinkSec Tx 128-bit Key 1 - WO */\n#define E1000_LSECTXKEY1(_n)\t(0x0B030 + (0x04 * (_n)))\n#define E1000_LSECRXSA(_n)\t(0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */\n#define E1000_LSECRXPN(_n)\t(0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */\n/* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit\n * key - RW.\n */\n#define E1000_LSECRXKEY(_n, _m)\t(0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))\n\n#define E1000_SSVPC\t\t0x041A0 /* Switch Security Violation Pkt Cnt */\n#define E1000_IPSCTRL\t\t0xB430 /* IpSec Control Register */\n#define E1000_IPSRXCMD\t\t0x0B408 /* IPSec Rx Command Register - RW */\n#define E1000_IPSRXIDX\t\t0x0B400 /* IPSec Rx Index - RW */\n/* IPSec Rx IPv4/v6 Address - RW */\n#define E1000_IPSRXIPADDR(_n)\t(0x0B420 + (0x04 * (_n)))\n/* IPSec Rx 128-bit Key - RW */\n#define E1000_IPSRXKEY(_n)\t(0x0B410 + (0x04 * (_n)))\n#define E1000_IPSRXSALT\t\t0x0B404 /* IPSec Rx Salt - RW */\n#define E1000_IPSRXSPI\t\t0x0B40C /* IPSec Rx SPI - RW */\n/* IPSec Tx 128-bit Key - RW */\n#define E1000_IPSTXKEY(_n)\t(0x0B460 + (0x04 * (_n)))\n#define E1000_IPSTXSALT\t\t0x0B454 /* IPSec Tx Salt - RW */\n#define E1000_IPSTXIDX\t\t0x0B450 /* IPSec Tx SA IDX - RW */\n#define E1000_PCS_CFG0\t0x04200 /* PCS Configuration 0 - RW */\n#define E1000_PCS_LCTL\t0x04208 /* PCS Link Control - RW */\n#define E1000_PCS_LSTAT\t0x0420C /* PCS Link Status - RO */\n#define E1000_CBTMPC\t0x0402C /* Circuit Breaker Tx Packet Count */\n#define E1000_HTDPMC\t0x0403C /* Host Transmit Discarded Packets */\n#define E1000_CBRDPC\t0x04044 /* Circuit Breaker Rx Dropped Count */\n#define E1000_CBRMPC\t0x040FC /* Circuit Breaker Rx Packet Count */\n#define E1000_RPTHC\t0x04104 /* Rx Packets To Host */\n#define E1000_HGPTC\t0x04118 /* Host Good Packets Tx Count */\n#define E1000_HTCBDPC\t0x04124 /* Host Tx Circuit Breaker Dropped Count */\n#define E1000_HGORCL\t0x04128 /* Host Good Octets Received Count Low */\n#define E1000_HGORCH\t0x0412C /* Host Good Octets Received Count High */\n#define E1000_HGOTCL\t0x04130 /* Host Good Octets Transmit Count Low */\n#define E1000_HGOTCH\t0x04134 /* Host Good Octets Transmit Count High */\n#define E1000_LENERRS\t0x04138 /* Length Errors Count */\n#define E1000_SCVPC\t0x04228 /* SerDes/SGMII Code Violation Pkt Count */\n#define E1000_HRMPC\t0x0A018 /* Header Redirection Missed Packet Count */\n#define E1000_PCS_ANADV\t0x04218 /* AN advertisement - RW */\n#define E1000_PCS_LPAB\t0x0421C /* Link Partner Ability - RW */\n#define E1000_PCS_NPTX\t0x04220 /* AN Next Page Transmit - RW */\n#define E1000_PCS_LPABNP\t0x04224 /* Link Partner Ability Next Pg - RW */\n#define E1000_RXCSUM\t0x05000 /* Rx Checksum Control - RW */\n#define E1000_RLPML\t0x05004 /* Rx Long Packet Max Length */\n#define E1000_RFCTL\t0x05008 /* Receive Filter Control*/\n#define E1000_MTA\t0x05200 /* Multicast Table Array - RW Array */\n#define E1000_RA\t0x05400 /* Receive Address - RW Array */\n#define E1000_RA2\t0x054E0 /* 2nd half of Rx address array - RW Array */\n#define E1000_VFTA\t0x05600 /* VLAN Filter Table Array - RW Array */\n#define E1000_VT_CTL\t0x0581C /* VMDq Control - RW */\n#define E1000_CIAA\t0x05B88 /* Config Indirect Access Address - RW */\n#define E1000_CIAD\t0x05B8C /* Config Indirect Access Data - RW */\n#define E1000_VFQA0\t0x0B000 /* VLAN Filter Queue Array 0 - RW Array */\n#define E1000_VFQA1\t0x0B200 /* VLAN Filter Queue Array 1 - RW Array */\n#define E1000_WUC\t0x05800 /* Wakeup Control - RW */\n#define E1000_WUFC\t0x05808 /* Wakeup Filter Control - RW */\n#define E1000_WUS\t0x05810 /* Wakeup Status - RO */\n#define E1000_MANC\t0x05820 /* Management Control - RW */\n#define E1000_IPAV\t0x05838 /* IP Address Valid - RW */\n#define E1000_IP4AT\t0x05840 /* IPv4 Address Table - RW Array */\n#define E1000_IP6AT\t0x05880 /* IPv6 Address Table - RW Array */\n#define E1000_WUPL\t0x05900 /* Wakeup Packet Length - RW */\n#define E1000_WUPM\t0x05A00 /* Wakeup Packet Memory - RO A */\n#define E1000_PBACL\t0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */\n#define E1000_FFLT\t0x05F00 /* Flexible Filter Length Table - RW Array */\n#define E1000_HOST_IF\t0x08800 /* Host Interface */\n#define E1000_FFMT\t0x09000 /* Flexible Filter Mask Table - RW Array */\n#define E1000_FFVT\t0x09800 /* Flexible Filter Value Table - RW Array */\n#define E1000_HIBBA\t0x8F40 /* Host Interface Buffer Base Address */\n/* Flexible Host Filter Table */\n#define E1000_FHFT(_n)\t(0x09000 + ((_n) * 0x100))\n/* Ext Flexible Host Filter Table */\n#define E1000_FHFT_EXT(_n)\t(0x09A00 + ((_n) * 0x100))\n\n\n#define E1000_KMRNCTRLSTA\t0x00034 /* MAC-PHY interface - RW */\n#define E1000_MANC2H\t\t0x05860 /* Management Control To Host - RW */\n/* Management Decision Filters */\n#define E1000_MDEF(_n)\t\t(0x05890 + (4 * (_n)))\n#define E1000_SW_FW_SYNC\t0x05B5C /* SW-FW Synchronization - RW */\n#define E1000_CCMCTL\t0x05B48 /* CCM Control Register */\n#define E1000_GIOCTL\t0x05B44 /* GIO Analog Control Register */\n#define E1000_SCCTL\t0x05B4C /* PCIc PLL Configuration Register */\n#define E1000_GCR\t0x05B00 /* PCI-Ex Control */\n#define E1000_GCR2\t0x05B64 /* PCI-Ex Control #2 */\n#define E1000_GSCL_1\t0x05B10 /* PCI-Ex Statistic Control #1 */\n#define E1000_GSCL_2\t0x05B14 /* PCI-Ex Statistic Control #2 */\n#define E1000_GSCL_3\t0x05B18 /* PCI-Ex Statistic Control #3 */\n#define E1000_GSCL_4\t0x05B1C /* PCI-Ex Statistic Control #4 */\n#define E1000_FACTPS\t0x05B30 /* Function Active and Power State to MNG */\n#define E1000_SWSM\t0x05B50 /* SW Semaphore */\n#define E1000_FWSM\t0x05B54 /* FW Semaphore */\n/* Driver-only SW semaphore (not used by BOOT agents) */\n#define E1000_SWSM2\t0x05B58\n#define E1000_DCA_ID\t0x05B70 /* DCA Requester ID Information - RO */\n#define E1000_DCA_CTRL\t0x05B74 /* DCA Control - RW */\n#define E1000_UFUSE\t0x05B78 /* UFUSE - RO */\n#define E1000_FFLT_DBG\t0x05F04 /* Debug Register */\n#define E1000_HICR\t0x08F00 /* Host Interface Control */\n#define E1000_FWSTS\t0x08F0C /* FW Status */\n\n/* RSS registers */\n#define E1000_CPUVEC\t0x02C10 /* CPU Vector Register - RW */\n#define E1000_MRQC\t0x05818 /* Multiple Receive Control - RW */\n#define E1000_IMIR(_i)\t(0x05A80 + ((_i) * 4)) /* Immediate Interrupt */\n#define E1000_IMIREXT(_i)\t(0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/\n#define E1000_IMIRVP\t\t0x05AC0 /* Immediate INT Rx VLAN Priority -RW */\n#define E1000_MSIXBM(_i)\t(0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */\n#define E1000_RETA(_i)\t(0x05C00 + ((_i) * 4)) /* Redirection Table - RW */\n#define E1000_RSSRK(_i)\t(0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */\n#define E1000_RSSIM\t0x05864 /* RSS Interrupt Mask */\n#define E1000_RSSIR\t0x05868 /* RSS Interrupt Request */\n/* VT Registers */\n#define E1000_SWPBS\t0x03004 /* Switch Packet Buffer Size - RW */\n#define E1000_MBVFICR\t0x00C80 /* Mailbox VF Cause - RWC */\n#define E1000_MBVFIMR\t0x00C84 /* Mailbox VF int Mask - RW */\n#define E1000_VFLRE\t0x00C88 /* VF Register Events - RWC */\n#define E1000_VFRE\t0x00C8C /* VF Receive Enables */\n#define E1000_VFTE\t0x00C90 /* VF Transmit Enables */\n#define E1000_QDE\t0x02408 /* Queue Drop Enable - RW */\n#define E1000_DTXSWC\t0x03500 /* DMA Tx Switch Control - RW */\n#define E1000_WVBR\t0x03554 /* VM Wrong Behavior - RWS */\n#define E1000_RPLOLR\t0x05AF0 /* Replication Offload - RW */\n#define E1000_UTA\t0x0A000 /* Unicast Table Array - RW */\n#define E1000_IOVTCL\t0x05BBC /* IOV Control Register */\n#define E1000_VMRCTL\t0X05D80 /* Virtual Mirror Rule Control */\n#define E1000_VMRVLAN\t0x05D90 /* Virtual Mirror Rule VLAN */\n#define E1000_VMRVM\t0x05DA0 /* Virtual Mirror Rule VM */\n#define E1000_MDFB\t0x03558 /* Malicious Driver free block */\n#define E1000_LVMMC\t0x03548 /* Last VM Misbehavior cause */\n#define E1000_TXSWC\t0x05ACC /* Tx Switch Control */\n#define E1000_SCCRL\t0x05DB0 /* Storm Control Control */\n#define E1000_BSCTRH\t0x05DB8 /* Broadcast Storm Control Threshold */\n#define E1000_MSCTRH\t0x05DBC /* Multicast Storm Control Threshold */\n/* These act per VF so an array friendly macro is used */\n#define E1000_V2PMAILBOX(_n)\t(0x00C40 + (4 * (_n)))\n#define E1000_P2VMAILBOX(_n)\t(0x00C00 + (4 * (_n)))\n#define E1000_VMBMEM(_n)\t(0x00800 + (64 * (_n)))\n#define E1000_VFVMBMEM(_n)\t(0x00800 + (_n))\n#define E1000_VMOLR(_n)\t\t(0x05AD0 + (4 * (_n)))\n/* VLAN Virtual Machine Filter - RW */\n#define E1000_VLVF(_n)\t\t(0x05D00 + (4 * (_n)))\n#define E1000_VMVIR(_n)\t\t(0x03700 + (4 * (_n)))\n#define E1000_DVMOLR(_n)\t(0x0C038 + (0x40 * (_n))) /* DMA VM offload */\n#define E1000_VTCTRL(_n)\t(0x10000 + (0x100 * (_n))) /* VT Control */\n#define E1000_TSYNCRXCTL\t0x0B620 /* Rx Time Sync Control register - RW */\n#define E1000_TSYNCTXCTL\t0x0B614 /* Tx Time Sync Control register - RW */\n#define E1000_TSYNCRXCFG\t0x05F50 /* Time Sync Rx Configuration - RW */\n#define E1000_RXSTMPL\t0x0B624 /* Rx timestamp Low - RO */\n#define E1000_RXSTMPH\t0x0B628 /* Rx timestamp High - RO */\n#define E1000_RXSATRL\t0x0B62C /* Rx timestamp attribute low - RO */\n#define E1000_RXSATRH\t0x0B630 /* Rx timestamp attribute high - RO */\n#define E1000_TXSTMPL\t0x0B618 /* Tx timestamp value Low - RO */\n#define E1000_TXSTMPH\t0x0B61C /* Tx timestamp value High - RO */\n#define E1000_SYSTIML\t0x0B600 /* System time register Low - RO */\n#define E1000_SYSTIMH\t0x0B604 /* System time register High - RO */\n#define E1000_TIMINCA\t0x0B608 /* Increment attributes register - RW */\n#define E1000_TIMADJL\t0x0B60C /* Time sync time adjustment offset Low - RW */\n#define E1000_TIMADJH\t0x0B610 /* Time sync time adjustment offset High - RW */\n#define E1000_TSAUXC\t0x0B640 /* Timesync Auxiliary Control register */\n#define E1000_SYSTIMR\t0x0B6F8 /* System time register Residue */\n#define E1000_TSICR\t0x0B66C /* Interrupt Cause Register */\n#define E1000_TSIM\t0x0B674 /* Interrupt Mask Register */\n\n/* Filtering Registers */\n#define E1000_SAQF(_n)\t(0x05980 + (4 * (_n))) /* Source Address Queue Fltr */\n#define E1000_DAQF(_n)\t(0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */\n#define E1000_SPQF(_n)\t(0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */\n#define E1000_FTQF(_n)\t(0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */\n#define E1000_TTQF(_n)\t(0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */\n#define E1000_SYNQF(_n)\t(0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */\n#define E1000_ETQF(_n)\t(0x05CB0 + (4 * (_n))) /* EType Queue Fltr */\n\n#define E1000_RTTDCS\t0x3600 /* Reedtown Tx Desc plane control and status */\n#define E1000_RTTPCS\t0x3474 /* Reedtown Tx Packet Plane control and status */\n#define E1000_RTRPCS\t0x2474 /* Rx packet plane control and status */\n#define E1000_RTRUP2TC\t0x05AC4 /* Rx User Priority to Traffic Class */\n#define E1000_RTTUP2TC\t0x0418 /* Transmit User Priority to Traffic Class */\n/* Tx Desc plane TC Rate-scheduler config */\n#define E1000_RTTDTCRC(_n)\t(0x3610 + ((_n) * 4))\n/* Tx Packet plane TC Rate-Scheduler Config */\n#define E1000_RTTPTCRC(_n)\t(0x3480 + ((_n) * 4))\n/* Rx Packet plane TC Rate-Scheduler Config */\n#define E1000_RTRPTCRC(_n)\t(0x2480 + ((_n) * 4))\n/* Tx Desc Plane TC Rate-Scheduler Status */\n#define E1000_RTTDTCRS(_n)\t(0x3630 + ((_n) * 4))\n/* Tx Desc Plane TC Rate-Scheduler MMW */\n#define E1000_RTTDTCRM(_n)\t(0x3650 + ((_n) * 4))\n/* Tx Packet plane TC Rate-Scheduler Status */\n#define E1000_RTTPTCRS(_n)\t(0x34A0 + ((_n) * 4))\n/* Tx Packet plane TC Rate-scheduler MMW */\n#define E1000_RTTPTCRM(_n)\t(0x34C0 + ((_n) * 4))\n/* Rx Packet plane TC Rate-Scheduler Status */\n#define E1000_RTRPTCRS(_n)\t(0x24A0 + ((_n) * 4))\n/* Rx Packet plane TC Rate-Scheduler MMW */\n#define E1000_RTRPTCRM(_n)\t(0x24C0 + ((_n) * 4))\n/* Tx Desc plane VM Rate-Scheduler MMW*/\n#define E1000_RTTDVMRM(_n)\t(0x3670 + ((_n) * 4))\n/* Tx BCN Rate-Scheduler MMW */\n#define E1000_RTTBCNRM(_n)\t(0x3690 + ((_n) * 4))\n#define E1000_RTTDQSEL\t0x3604 /* Tx Desc Plane Queue Select */\n#define E1000_RTTDVMRC\t0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */\n#define E1000_RTTDVMRS\t0x360C /* Tx Desc Plane VM Rate-Scheduler Status */\n#define E1000_RTTBCNRC\t0x36B0 /* Tx BCN Rate-Scheduler Config */\n#define E1000_RTTBCNRS\t0x36B4 /* Tx BCN Rate-Scheduler Status */\n#define E1000_RTTBCNCR\t0xB200 /* Tx BCN Control Register */\n#define E1000_RTTBCNTG\t0x35A4 /* Tx BCN Tagging */\n#define E1000_RTTBCNCP\t0xB208 /* Tx BCN Congestion point */\n#define E1000_RTRBCNCR\t0xB20C /* Rx BCN Control Register */\n#define E1000_RTTBCNRD\t0x36B8 /* Tx BCN Rate Drift */\n#define E1000_PFCTOP\t0x1080 /* Priority Flow Control Type and Opcode */\n#define E1000_RTTBCNIDX\t0xB204 /* Tx BCN Congestion Point */\n#define E1000_RTTBCNACH\t0x0B214 /* Tx BCN Control High */\n#define E1000_RTTBCNACL\t0x0B210 /* Tx BCN Control Low */\n\n/* DMA Coalescing registers */\n#define E1000_DMACR\t0x02508 /* Control Register */\n#define E1000_DMCTXTH\t0x03550 /* Transmit Threshold */\n#define E1000_DMCTLX\t0x02514 /* Time to Lx Request */\n#define E1000_DMCRTRH\t0x05DD0 /* Receive Packet Rate Threshold */\n#define E1000_DMCCNT\t0x05DD4 /* Current Rx Count */\n#define E1000_FCRTC\t0x02170 /* Flow Control Rx high watermark */\n#define E1000_PCIEMISC\t0x05BB8 /* PCIE misc config register */\n\n/* PCIe Parity Status Register */\n#define E1000_PCIEERRSTS\t0x05BA8\n\n#define E1000_PROXYS\t0x5F64 /* Proxying Status */\n#define E1000_PROXYFC\t0x5F60 /* Proxying Filter Control */\n/* Thermal sensor configuration and status registers */\n#define E1000_THMJT\t0x08100 /* Junction Temperature */\n#define E1000_THLOWTC\t0x08104 /* Low Threshold Control */\n#define E1000_THMIDTC\t0x08108 /* Mid Threshold Control */\n#define E1000_THHIGHTC\t0x0810C /* High Threshold Control */\n#define E1000_THSTAT\t0x08110 /* Thermal Sensor Status */\n\n/* Energy Efficient Ethernet \"EEE\" registers */\n#define E1000_IPCNFG\t0x0E38 /* Internal PHY Configuration */\n#define E1000_LTRC\t0x01A0 /* Latency Tolerance Reporting Control */\n#define E1000_EEER\t0x0E30 /* Energy Efficient Ethernet \"EEE\"*/\n#define E1000_EEE_SU\t0x0E34 /* EEE Setup */\n#define E1000_TLPIC\t0x4148 /* EEE Tx LPI Count - TLPIC */\n#define E1000_RLPIC\t0x414C /* EEE Rx LPI Count - RLPIC */\n\n/* OS2BMC Registers */\n#define E1000_B2OSPC\t0x08FE0 /* BMC2OS packets sent by BMC */\n#define E1000_B2OGPRC\t0x04158 /* BMC2OS packets received by host */\n#define E1000_O2BGPTC\t0x08FE4 /* OS2BMC packets received by BMC */\n#define E1000_O2BSPC\t0x0415C /* OS2BMC packets transmitted by host */\n\n\n\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/igb.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n/* Linux PRO/1000 Ethernet Driver main header file */\n\n#ifndef _IGB_H_\n#define _IGB_H_\n\n#include \n\n#ifndef IGB_NO_LRO\n#include \n#endif\n\n#undef HAVE_HW_TIME_STAMP\n#ifdef HAVE_HW_TIME_STAMP\n#include \n#include \n#include \n\n#endif\n#ifdef SIOCETHTOOL\n#include \n#endif\n\nstruct igb_adapter;\n\n#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)\n//#define IGB_DCA\n#endif\n#ifdef IGB_DCA\n#include \n#endif\n\n#include \"kcompat.h\"\n\n#ifdef HAVE_SCTP\n#include \n#endif\n\n#include \"e1000_api.h\"\n#include \"e1000_82575.h\"\n#include \"e1000_manage.h\"\n#include \"e1000_mbx.h\"\n\n#define IGB_ERR(args...) printk(KERN_ERR \"igb: \" args)\n\n#define PFX \"igb: \"\n#define DPRINTK(nlevel, klevel, fmt, args...) \\\n\t(void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \\\n\tprintk(KERN_##klevel PFX \"%s: %s: \" fmt, adapter->netdev->name, \\\n\t\t__FUNCTION__ , ## args))\n\n#ifdef HAVE_PTP_1588_CLOCK\n#include \n#include \n#include \n#endif /* HAVE_PTP_1588_CLOCK */\n\n#ifdef HAVE_I2C_SUPPORT\n#include \n#include \n#endif /* HAVE_I2C_SUPPORT */\n\n/* Interrupt defines */\n#define IGB_START_ITR 648 /* ~6000 ints/sec */\n#define IGB_4K_ITR 980\n#define IGB_20K_ITR 196\n#define IGB_70K_ITR 56\n\n/* Interrupt modes, as used by the IntMode parameter */\n#define IGB_INT_MODE_LEGACY 0\n#define IGB_INT_MODE_MSI 1\n#define IGB_INT_MODE_MSIX 2\n\n/* TX/RX descriptor defines */\n#define IGB_DEFAULT_TXD 256\n#define IGB_DEFAULT_TX_WORK\t\t 128\n#define IGB_MIN_TXD 80\n#define IGB_MAX_TXD 4096\n\n#define IGB_DEFAULT_RXD 256\n#define IGB_MIN_RXD 80\n#define IGB_MAX_RXD 4096\n\n#define IGB_MIN_ITR_USECS 10 /* 100k irq/sec */\n#define IGB_MAX_ITR_USECS 8191 /* 120 irq/sec */\n\n#define NON_Q_VECTORS 1\n#define MAX_Q_VECTORS 10\n\n/* Transmit and receive queues */\n#define IGB_MAX_RX_QUEUES 16\n#define IGB_MAX_TX_QUEUES 16\n\n#define IGB_MAX_VF_MC_ENTRIES 30\n#define IGB_MAX_VF_FUNCTIONS 8\n#define IGB_82576_VF_DEV_ID 0x10CA\n#define IGB_I350_VF_DEV_ID 0x1520\n#define IGB_MAX_UTA_ENTRIES 128\n#define MAX_EMULATION_MAC_ADDRS 16\n#define OUI_LEN 3\n#define IGB_MAX_VMDQ_QUEUES 8\n\n\nstruct vf_data_storage {\n\tunsigned char vf_mac_addresses[ETH_ALEN];\n\tu16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];\n\tu16 num_vf_mc_hashes;\n\tu16 default_vf_vlan_id;\n\tu16 vlans_enabled;\n\tunsigned char em_mac_addresses[MAX_EMULATION_MAC_ADDRS * ETH_ALEN];\n\tu32 uta_table_copy[IGB_MAX_UTA_ENTRIES];\n\tu32 flags;\n\tunsigned long last_nack;\n#ifdef IFLA_VF_MAX\n\tu16 pf_vlan; /* When set, guest VLAN config not allowed. */\n\tu16 pf_qos;\n\tu16 tx_rate;\n#ifdef HAVE_VF_SPOOFCHK_CONFIGURE\n\tbool spoofchk_enabled;\n#endif\n#endif\n};\n\n#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */\n#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */\n#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */\n#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */\n\n/* RX descriptor control thresholds.\n * PTHRESH - MAC will consider prefetch if it has fewer than this number of\n * descriptors available in its onboard memory.\n * Setting this to 0 disables RX descriptor prefetch.\n * HTHRESH - MAC will only prefetch if there are at least this many descriptors\n * available in host memory.\n * If PTHRESH is 0, this should also be 0.\n * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back\n * descriptors until either it has this many to write back, or the\n * ITR timer expires.\n */\n#define IGB_RX_PTHRESH\t((hw->mac.type == e1000_i354) ? 12 : 8)\n#define IGB_RX_HTHRESH\t8\n#define IGB_TX_PTHRESH\t((hw->mac.type == e1000_i354) ? 20 : 8)\n#define IGB_TX_HTHRESH\t1\n#define IGB_RX_WTHRESH\t((hw->mac.type == e1000_82576 && \\\n\t\t\t adapter->msix_entries) ? 1 : 4)\n\n/* this is the size past which hardware will drop packets when setting LPE=0 */\n#define MAXIMUM_ETHERNET_VLAN_SIZE 1522\n\n/* NOTE: netdev_alloc_skb reserves 16 bytes, NET_IP_ALIGN means we\n * reserve 2 more, and skb_shared_info adds an additional 384 more,\n * this adds roughly 448 bytes of extra data meaning the smallest\n * allocation we could have is 1K.\n * i.e. RXBUFFER_512 --> size-1024 slab\n */\n/* Supported Rx Buffer Sizes */\n#define IGB_RXBUFFER_256 256\n#define IGB_RXBUFFER_2048 2048\n#define IGB_RXBUFFER_16384 16384\n#define IGB_RX_HDR_LEN\t IGB_RXBUFFER_256\n#if MAX_SKB_FRAGS < 8\n#define IGB_RX_BUFSZ\t ALIGN(MAX_JUMBO_FRAME_SIZE / MAX_SKB_FRAGS, 1024)\n#else\n#define IGB_RX_BUFSZ\t IGB_RXBUFFER_2048\n#endif\n\n\n/* Packet Buffer allocations */\n#define IGB_PBA_BYTES_SHIFT 0xA\n#define IGB_TX_HEAD_ADDR_SHIFT 7\n#define IGB_PBA_TX_MASK 0xFFFF0000\n\n#define IGB_FC_PAUSE_TIME 0x0680 /* 858 usec */\n\n/* How many Rx Buffers do we bundle into one write to the hardware ? */\n#define IGB_RX_BUFFER_WRITE\t16\t/* Must be power of 2 */\n\n#define IGB_EEPROM_APME 0x0400\n#define AUTO_ALL_MODES 0\n\n#ifndef IGB_MASTER_SLAVE\n/* Switch to override PHY master/slave setting */\n#define IGB_MASTER_SLAVE\te1000_ms_hw_default\n#endif\n\n#define IGB_MNG_VLAN_NONE -1\n\n#ifndef IGB_NO_LRO\n#define IGB_LRO_MAX 32 /*Maximum number of LRO descriptors*/\nstruct igb_lro_stats {\n\tu32 flushed;\n\tu32 coal;\n};\n\n/*\n * igb_lro_header - header format to be aggregated by LRO\n * @iph: IP header without options\n * @tcp: TCP header\n * @ts: Optional TCP timestamp data in TCP options\n *\n * This structure relies on the check above that verifies that the header\n * is IPv4 and does not contain any options.\n */\nstruct igb_lrohdr {\n\tstruct iphdr iph;\n\tstruct tcphdr th;\n\t__be32 ts[0];\n};\n\nstruct igb_lro_list {\n\tstruct sk_buff_head active;\n\tstruct igb_lro_stats stats;\n};\n\n#endif /* IGB_NO_LRO */\nstruct igb_cb {\n#ifndef IGB_NO_LRO\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\tunion {\t\t\t\t/* Union defining head/tail partner */\n\t\tstruct sk_buff *head;\n\t\tstruct sk_buff *tail;\n\t};\n#endif\n\t__be32\ttsecr;\t\t\t/* timestamp echo response */\n\tu32\ttsval;\t\t\t/* timestamp value in host order */\n\tu32\tnext_seq;\t\t/* next expected sequence number */\n\tu16\tfree;\t\t\t/* 65521 minus total size */\n\tu16\tmss;\t\t\t/* size of data portion of packet */\n\tu16\tappend_cnt;\t\t/* number of skb's appended */\n#endif /* IGB_NO_LRO */\n#ifdef HAVE_VLAN_RX_REGISTER\n\tu16\tvid;\t\t\t/* VLAN tag */\n#endif\n};\n#define IGB_CB(skb) ((struct igb_cb *)(skb)->cb)\n\nenum igb_tx_flags {\n\t/* cmd_type flags */\n\tIGB_TX_FLAGS_VLAN\t= 0x01,\n\tIGB_TX_FLAGS_TSO\t= 0x02,\n\tIGB_TX_FLAGS_TSTAMP\t= 0x04,\n\n\t/* olinfo flags */\n\tIGB_TX_FLAGS_IPV4\t= 0x10,\n\tIGB_TX_FLAGS_CSUM\t= 0x20,\n};\n\n/* VLAN info */\n#define IGB_TX_FLAGS_VLAN_MASK\t\t0xffff0000\n#define IGB_TX_FLAGS_VLAN_SHIFT\t\t 16\n\n/*\n * The largest size we can write to the descriptor is 65535. In order to\n * maintain a power of two alignment we have to limit ourselves to 32K.\n */\n#define IGB_MAX_TXD_PWR\t\t15\n#define IGB_MAX_DATA_PER_TXD\t(1 << IGB_MAX_TXD_PWR)\n\n/* Tx Descriptors needed, worst case */\n#define TXD_USE_COUNT(S)\tDIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)\n#ifndef MAX_SKB_FRAGS\n#define DESC_NEEDED\t4\n#elif (MAX_SKB_FRAGS < 16)\n#define DESC_NEEDED\t((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)\n#else\n#define DESC_NEEDED\t(MAX_SKB_FRAGS + 4)\n#endif\n\n/* wrapper around a pointer to a socket buffer,\n * so a DMA handle can be stored along with the buffer */\nstruct igb_tx_buffer {\n\tunion e1000_adv_tx_desc *next_to_watch;\n\tunsigned long time_stamp;\n\tstruct sk_buff *skb;\n\tunsigned int bytecount;\n\tu16 gso_segs;\n\t__be16 protocol;\n\tDEFINE_DMA_UNMAP_ADDR(dma);\n\tDEFINE_DMA_UNMAP_LEN(len);\n\tu32 tx_flags;\n};\n\nstruct igb_rx_buffer {\n\tdma_addr_t dma;\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\tstruct sk_buff *skb;\n#else\n\tstruct page *page;\n\tu32 page_offset;\n#endif\n};\n\nstruct igb_tx_queue_stats {\n\tu64 packets;\n\tu64 bytes;\n\tu64 restart_queue;\n};\n\nstruct igb_rx_queue_stats {\n\tu64 packets;\n\tu64 bytes;\n\tu64 drops;\n\tu64 csum_err;\n\tu64 alloc_failed;\n\tu64 ipv4_packets; /* IPv4 headers processed */\n\tu64 ipv4e_packets; /* IPv4E headers with extensions processed */\n\tu64 ipv6_packets; /* IPv6 headers processed */\n\tu64 ipv6e_packets; /* IPv6E headers with extensions processed */\n\tu64 tcp_packets; /* TCP headers processed */\n\tu64 udp_packets; /* UDP headers processed */\n\tu64 sctp_packets; /* SCTP headers processed */\n\tu64 nfs_packets; /* NFS headers processe */\n};\n\nstruct igb_ring_container {\n\tstruct igb_ring *ring;\t\t/* pointer to linked list of rings */\n\tunsigned int total_bytes;\t/* total bytes processed this int */\n\tunsigned int total_packets;\t/* total packets processed this int */\n\tu16 work_limit;\t\t\t/* total work allowed per interrupt */\n\tu8 count;\t\t\t/* total number of rings in vector */\n\tu8 itr;\t\t\t\t/* current ITR setting for ring */\n};\n\nstruct igb_ring {\n\tstruct igb_q_vector *q_vector; /* backlink to q_vector */\n\tstruct net_device *netdev; /* back pointer to net_device */\n\tstruct device *dev; /* device for dma mapping */\n\tunion {\t\t\t\t/* array of buffer info structs */\n\t\tstruct igb_tx_buffer *tx_buffer_info;\n\t\tstruct igb_rx_buffer *rx_buffer_info;\n\t};\n#ifdef HAVE_PTP_1588_CLOCK\n\tunsigned long last_rx_timestamp;\n#endif /* HAVE_PTP_1588_CLOCK */\n\tvoid *desc; /* descriptor ring memory */\n\tunsigned long flags; /* ring specific flags */\n\tvoid __iomem *tail; /* pointer to ring tail register */\n\tdma_addr_t dma;\t\t\t/* phys address of the ring */\n\tunsigned int size;\t\t/* length of desc. ring in bytes */\n\n\tu16 count; /* number of desc. in the ring */\n\tu8 queue_index; /* logical index of the ring*/\n\tu8 reg_idx; /* physical index of the ring */\n\n\t/* everything past this point are written often */\n\tu16 next_to_clean;\n\tu16 next_to_use;\n\tu16 next_to_alloc;\n\n\tunion {\n\t\t/* TX */\n\t\tstruct {\n\t\t\tstruct igb_tx_queue_stats tx_stats;\n\t\t};\n\t\t/* RX */\n\t\tstruct {\n\t\t\tstruct igb_rx_queue_stats rx_stats;\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\t\t\tu16 rx_buffer_len;\n#else\n\t\t\tstruct sk_buff *skb;\n#endif\n\t\t};\n\t};\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n\tstruct net_device *vmdq_netdev;\n\tint vqueue_index;\t\t/* queue index for virtual netdev */\n#endif\n} ____cacheline_internodealigned_in_smp;\n\nstruct igb_q_vector {\n\tstruct igb_adapter *adapter;\t/* backlink */\n\tint cpu;\t\t\t/* CPU for DCA */\n\tu32 eims_value;\t\t\t/* EIMS mask value */\n\n\tu16 itr_val;\n\tu8 set_itr;\n\tvoid __iomem *itr_register;\n\n\tstruct igb_ring_container rx, tx;\n\n\tstruct napi_struct napi;\n#ifndef IGB_NO_LRO\n\tstruct igb_lro_list lrolist; /* LRO list for queue vector*/\n#endif\n\tchar name[IFNAMSIZ + 9];\n#ifndef HAVE_NETDEV_NAPI_LIST\n\tstruct net_device poll_dev;\n#endif\n\n\t/* for dynamic allocation of rings associated with this q_vector */\n\tstruct igb_ring ring[0] ____cacheline_internodealigned_in_smp;\n};\n\nenum e1000_ring_flags_t {\n#ifndef HAVE_NDO_SET_FEATURES\n\tIGB_RING_FLAG_RX_CSUM,\n#endif\n\tIGB_RING_FLAG_RX_SCTP_CSUM,\n\tIGB_RING_FLAG_RX_LB_VLAN_BSWAP,\n\tIGB_RING_FLAG_TX_CTX_IDX,\n\tIGB_RING_FLAG_TX_DETECT_HANG,\n};\n\nstruct igb_mac_addr {\n\tu8 addr[ETH_ALEN];\n\tu16 queue;\n\tu16 state; /* bitmask */\n};\n#define IGB_MAC_STATE_DEFAULT\t0x1\n#define IGB_MAC_STATE_MODIFIED\t0x2\n#define IGB_MAC_STATE_IN_USE\t0x4\n\n#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)\n\n#define IGB_RX_DESC(R, i)\t \\\n\t(&(((union e1000_adv_rx_desc *)((R)->desc))[i]))\n#define IGB_TX_DESC(R, i)\t \\\n\t(&(((union e1000_adv_tx_desc *)((R)->desc))[i]))\n#define IGB_TX_CTXTDESC(R, i)\t \\\n\t(&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))\n\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n#define netdev_ring(ring) \\\n\t((ring->vmdq_netdev ? ring->vmdq_netdev : ring->netdev))\n#define ring_queue_index(ring) \\\n\t((ring->vmdq_netdev ? ring->vqueue_index : ring->queue_index))\n#else\n#define netdev_ring(ring) (ring->netdev)\n#define ring_queue_index(ring) (ring->queue_index)\n#endif /* CONFIG_IGB_VMDQ_NETDEV */\n\n/* igb_test_staterr - tests bits within Rx descriptor status and error fields */\nstatic inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,\n\t\t\t\t const u32 stat_err_bits)\n{\n\treturn rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);\n}\n\n/* igb_desc_unused - calculate if we have unused descriptors */\nstatic inline u16 igb_desc_unused(const struct igb_ring *ring)\n{\n\tu16 ntc = ring->next_to_clean;\n\tu16 ntu = ring->next_to_use;\n\n\treturn ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;\n}\n\n#ifdef CONFIG_BQL\nstatic inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)\n{\n\treturn netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);\n}\n#endif /* CONFIG_BQL */\n\n// #ifdef EXT_THERMAL_SENSOR_SUPPORT\n// #ifdef IGB_PROCFS\nstruct igb_therm_proc_data\n{\n\tstruct e1000_hw *hw;\n\tstruct e1000_thermal_diode_data *sensor_data;\n};\n\n// #endif /* IGB_PROCFS */\n// #endif /* EXT_THERMAL_SENSOR_SUPPORT */\n\n#ifdef IGB_HWMON\n#define IGB_HWMON_TYPE_LOC\t0\n#define IGB_HWMON_TYPE_TEMP\t1\n#define IGB_HWMON_TYPE_CAUTION\t2\n#define IGB_HWMON_TYPE_MAX\t3\n\nstruct hwmon_attr {\n\tstruct device_attribute dev_attr;\n\tstruct e1000_hw *hw;\n\tstruct e1000_thermal_diode_data *sensor;\n\tchar name[12];\n\t};\n\nstruct hwmon_buff {\n\tstruct device *device;\n\tstruct hwmon_attr *hwmon_list;\n\tunsigned int n_hwmon;\n\t};\n#endif /* IGB_HWMON */\n\n/* board specific private data structure */\nstruct igb_adapter {\n#ifdef HAVE_VLAN_RX_REGISTER\n\t/* vlgrp must be first member of structure */\n\tstruct vlan_group *vlgrp;\n#else\n\tunsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];\n#endif\n\tstruct net_device *netdev;\n\n\tunsigned long state;\n\tunsigned int flags;\n\n\tunsigned int num_q_vectors;\n\tstruct msix_entry *msix_entries;\n\n\n\t/* TX */\n\tu16 tx_work_limit;\n\tu32 tx_timeout_count;\n\tint num_tx_queues;\n\tstruct igb_ring *tx_ring[IGB_MAX_TX_QUEUES];\n\n\t/* RX */\n\tint num_rx_queues;\n\tstruct igb_ring *rx_ring[IGB_MAX_RX_QUEUES];\n\n\tstruct timer_list watchdog_timer;\n\tstruct timer_list dma_err_timer;\n\tstruct timer_list phy_info_timer;\n\tu16 mng_vlan_id;\n\tu32 bd_number;\n\tu32 wol;\n\tu32 en_mng_pt;\n\tu16 link_speed;\n\tu16 link_duplex;\n\tu8 port_num;\n\n\t/* Interrupt Throttle Rate */\n\tu32 rx_itr_setting;\n\tu32 tx_itr_setting;\n\n\tstruct work_struct reset_task;\n\tstruct work_struct watchdog_task;\n\tstruct work_struct dma_err_task;\n\tbool fc_autoneg;\n\tu8 tx_timeout_factor;\n\n#ifdef DEBUG\n\tbool tx_hang_detected;\n\tbool disable_hw_reset;\n#endif\n\tu32 max_frame_size;\n\n\t/* OS defined structs */\n\tstruct pci_dev *pdev;\n#ifndef HAVE_NETDEV_STATS_IN_NETDEV\n\tstruct net_device_stats net_stats;\n#endif\n#ifndef IGB_NO_LRO\n\tstruct igb_lro_stats lro_stats;\n#endif\n\n\t/* structs defined in e1000_hw.h */\n\tstruct e1000_hw hw;\n\tstruct e1000_hw_stats stats;\n\tstruct e1000_phy_info phy_info;\n\tstruct e1000_phy_stats phy_stats;\n\n#ifdef ETHTOOL_TEST\n\tu32 test_icr;\n\tstruct igb_ring test_tx_ring;\n\tstruct igb_ring test_rx_ring;\n#endif\n\n\tint msg_enable;\n\n\tstruct igb_q_vector *q_vector[MAX_Q_VECTORS];\n\tu32 eims_enable_mask;\n\tu32 eims_other;\n\n\t/* to not mess up cache alignment, always add to the bottom */\n\tu32 *config_space;\n\tu16 tx_ring_count;\n\tu16 rx_ring_count;\n\tstruct vf_data_storage *vf_data;\n#ifdef IFLA_VF_MAX\n\tint vf_rate_link_speed;\n#endif\n\tu32 lli_port;\n\tu32 lli_size;\n\tunsigned int vfs_allocated_count;\n\t/* Malicious Driver Detection flag. Valid only when SR-IOV is enabled */\n\tbool mdd;\n\tint int_mode;\n\tu32 rss_queues;\n\tu32 vmdq_pools;\n\tchar fw_version[32];\n\tu32 wvbr;\n\tstruct igb_mac_addr *mac_table;\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n\tstruct net_device *vmdq_netdev[IGB_MAX_VMDQ_QUEUES];\n#endif\n\tint vferr_refcount;\n\tint dmac;\n\tu32 *shadow_vfta;\n\n\t/* External Thermal Sensor support flag */\n\tbool ets;\n#ifdef IGB_HWMON\n\tstruct hwmon_buff igb_hwmon_buff;\n#else /* IGB_HWMON */\n#ifdef IGB_PROCFS\n\tstruct proc_dir_entry *eth_dir;\n\tstruct proc_dir_entry *info_dir;\n\tstruct proc_dir_entry *therm_dir[E1000_MAX_SENSORS];\n\tstruct igb_therm_proc_data therm_data[E1000_MAX_SENSORS];\n\tbool old_lsc;\n#endif /* IGB_PROCFS */\n#endif /* IGB_HWMON */\n\tu32 etrack_id;\n\n#ifdef HAVE_PTP_1588_CLOCK\n\tstruct ptp_clock *ptp_clock;\n\tstruct ptp_clock_info ptp_caps;\n\tstruct delayed_work ptp_overflow_work;\n\tstruct work_struct ptp_tx_work;\n\tstruct sk_buff *ptp_tx_skb;\n\tunsigned long ptp_tx_start;\n\tunsigned long last_rx_ptp_check;\n\tspinlock_t tmreg_lock;\n\tstruct cyclecounter cc;\n\tstruct timecounter tc;\n\tu32 tx_hwtstamp_timeouts;\n\tu32 rx_hwtstamp_cleared;\n#endif /* HAVE_PTP_1588_CLOCK */\n\n#ifdef HAVE_I2C_SUPPORT\n\tstruct i2c_algo_bit_data i2c_algo;\n\tstruct i2c_adapter i2c_adap;\n\tstruct i2c_client *i2c_client;\n#endif /* HAVE_I2C_SUPPORT */\n\tunsigned long link_check_timeout;\n\n\n\tint devrc;\n\n\tint copper_tries;\n\tu16 eee_advert;\n};\n\n#ifdef CONFIG_IGB_VMDQ_NETDEV\nstruct igb_vmdq_adapter {\n#ifdef HAVE_VLAN_RX_REGISTER\n\t/* vlgrp must be first member of structure */\n\tstruct vlan_group *vlgrp;\n#else\n\tunsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];\n#endif\n\tstruct igb_adapter *real_adapter;\n\tstruct net_device *vnetdev;\n\tstruct net_device_stats net_stats;\n\tstruct igb_ring *tx_ring;\n\tstruct igb_ring *rx_ring;\n};\n#endif\n\n#define IGB_FLAG_HAS_MSI\t\t(1 << 0)\n#define IGB_FLAG_DCA_ENABLED\t\t(1 << 1)\n#define IGB_FLAG_LLI_PUSH\t\t(1 << 2)\n#define IGB_FLAG_QUAD_PORT_A\t\t(1 << 3)\n#define IGB_FLAG_QUEUE_PAIRS\t\t(1 << 4)\n#define IGB_FLAG_EEE\t\t\t(1 << 5)\n#define IGB_FLAG_DMAC\t\t\t(1 << 6)\n#define IGB_FLAG_DETECT_BAD_DMA\t\t(1 << 7)\n#define IGB_FLAG_PTP\t\t\t(1 << 8)\n#define IGB_FLAG_RSS_FIELD_IPV4_UDP\t(1 << 9)\n#define IGB_FLAG_RSS_FIELD_IPV6_UDP\t(1 << 10)\n#define IGB_FLAG_WOL_SUPPORTED\t\t(1 << 11)\n#define IGB_FLAG_NEED_LINK_UPDATE\t(1 << 12)\n#define IGB_FLAG_LOOPBACK_ENABLE\t(1 << 13)\n#define IGB_FLAG_MEDIA_RESET\t\t(1 << 14)\n#define IGB_FLAG_MAS_ENABLE\t\t(1 << 15)\n\n/* Media Auto Sense */\n#define IGB_MAS_ENABLE_0\t\t0X0001\n#define IGB_MAS_ENABLE_1\t\t0X0002\n#define IGB_MAS_ENABLE_2\t\t0X0004\n#define IGB_MAS_ENABLE_3\t\t0X0008\n\n#define IGB_MIN_TXPBSIZE 20408\n#define IGB_TX_BUF_4096 4096\n\n#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */\n\n/* DMA Coalescing defines */\n#define IGB_DMAC_DISABLE 0\n#define IGB_DMAC_MIN 250\n#define IGB_DMAC_500 500\n#define IGB_DMAC_EN_DEFAULT 1000\n#define IGB_DMAC_2000 2000\n#define IGB_DMAC_3000 3000\n#define IGB_DMAC_4000 4000\n#define IGB_DMAC_5000 5000\n#define IGB_DMAC_6000 6000\n#define IGB_DMAC_7000 7000\n#define IGB_DMAC_8000 8000\n#define IGB_DMAC_9000 9000\n#define IGB_DMAC_MAX 10000\n\n#define IGB_82576_TSYNC_SHIFT 19\n#define IGB_82580_TSYNC_SHIFT 24\n#define IGB_TS_HDR_LEN 16\n\n/* CEM Support */\n#define FW_HDR_LEN 0x4\n#define FW_CMD_DRV_INFO 0xDD\n#define FW_CMD_DRV_INFO_LEN 0x5\n#define FW_CMD_RESERVED 0X0\n#define FW_RESP_SUCCESS 0x1\n#define FW_UNUSED_VER 0x0\n#define FW_MAX_RETRIES 3\n#define FW_STATUS_SUCCESS 0x1\n#define FW_FAMILY_DRV_VER 0Xffffffff\n\n#define IGB_MAX_LINK_TRIES 20\n\nstruct e1000_fw_hdr {\n\tu8 cmd;\n\tu8 buf_len;\n\tunion\n\t{\n\t\tu8 cmd_resv;\n\t\tu8 ret_status;\n\t} cmd_or_resp;\n\tu8 checksum;\n};\n\n#pragma pack(push,1)\nstruct e1000_fw_drv_info {\n\tstruct e1000_fw_hdr hdr;\n\tu8 port_num;\n\tu32 drv_version;\n\tu16 pad; /* end spacing to ensure length is mult. of dword */\n\tu8 pad2; /* end spacing to ensure length is mult. of dword2 */\n};\n#pragma pack(pop)\n\nenum e1000_state_t {\n\t__IGB_TESTING,\n\t__IGB_RESETTING,\n\t__IGB_DOWN\n};\n\nextern char igb_driver_name[];\nextern char igb_driver_version[];\n\nextern int igb_up(struct igb_adapter *);\nextern void igb_down(struct igb_adapter *);\nextern void igb_reinit_locked(struct igb_adapter *);\nextern void igb_reset(struct igb_adapter *);\nextern int igb_set_spd_dplx(struct igb_adapter *, u16);\nextern int igb_setup_tx_resources(struct igb_ring *);\nextern int igb_setup_rx_resources(struct igb_ring *);\nextern void igb_free_tx_resources(struct igb_ring *);\nextern void igb_free_rx_resources(struct igb_ring *);\nextern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);\nextern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);\nextern void igb_setup_tctl(struct igb_adapter *);\nextern void igb_setup_rctl(struct igb_adapter *);\nextern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);\nextern void igb_unmap_and_free_tx_resource(struct igb_ring *,\n struct igb_tx_buffer *);\nextern void igb_alloc_rx_buffers(struct igb_ring *, u16);\nextern void igb_clean_rx_ring(struct igb_ring *);\nextern void igb_update_stats(struct igb_adapter *);\nextern bool igb_has_link(struct igb_adapter *adapter);\nextern void igb_set_ethtool_ops(struct net_device *);\nextern void igb_check_options(struct igb_adapter *);\nextern void igb_power_up_link(struct igb_adapter *);\n#ifdef HAVE_PTP_1588_CLOCK\nextern void igb_ptp_init(struct igb_adapter *adapter);\nextern void igb_ptp_stop(struct igb_adapter *adapter);\nextern void igb_ptp_reset(struct igb_adapter *adapter);\nextern void igb_ptp_tx_work(struct work_struct *work);\nextern void igb_ptp_rx_hang(struct igb_adapter *adapter);\nextern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);\nextern void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,\n\t\t\t\tstruct sk_buff *skb);\nextern void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,\n\t\t\t\tunsigned char *va,\n\t\t\t\tstruct sk_buff *skb);\nstatic inline void igb_ptp_rx_hwtstamp(struct igb_ring *rx_ring,\n\t\t\t\t union e1000_adv_rx_desc *rx_desc,\n\t\t\t\t struct sk_buff *skb)\n{\n\tif (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\t\tigb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb);\n\t\tskb_pull(skb, IGB_TS_HDR_LEN);\n#endif\n\t\treturn;\n\t}\n\n\tif (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS))\n\t\tigb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);\n\n\t/* Update the last_rx_timestamp timer in order to enable watchdog check\n\t * for error case of latched timestamp on a dropped packet.\n\t */\n\trx_ring->last_rx_timestamp = jiffies;\n}\n\nextern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev,\n\t\t\t\t struct ifreq *ifr, int cmd);\n#endif /* HAVE_PTP_1588_CLOCK */\n#ifdef ETHTOOL_OPS_COMPAT\nextern int ethtool_ioctl(struct ifreq *);\n#endif\nextern int igb_write_mc_addr_list(struct net_device *netdev);\nextern int igb_add_mac_filter(struct igb_adapter *adapter, u8 *addr, u16 queue);\nextern int igb_del_mac_filter(struct igb_adapter *adapter, u8* addr, u16 queue);\nextern int igb_available_rars(struct igb_adapter *adapter);\nextern s32 igb_vlvf_set(struct igb_adapter *, u32, bool, u32);\nextern void igb_configure_vt_default_pool(struct igb_adapter *adapter);\nextern void igb_enable_vlan_tags(struct igb_adapter *adapter);\n#ifndef HAVE_VLAN_RX_REGISTER\nextern void igb_vlan_mode(struct net_device *, u32);\n#endif\n\n#define E1000_PCS_CFG_IGN_SD\t1\n\n#ifdef IGB_HWMON\nvoid igb_sysfs_exit(struct igb_adapter *adapter);\nint igb_sysfs_init(struct igb_adapter *adapter);\n#else\n#ifdef IGB_PROCFS\nint igb_procfs_init(struct igb_adapter* adapter);\nvoid igb_procfs_exit(struct igb_adapter* adapter);\nint igb_procfs_topdir_init(void);\nvoid igb_procfs_topdir_exit(void);\n#endif /* IGB_PROCFS */\n#endif /* IGB_HWMON */\n\n\n\n#endif /* _IGB_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/igb_debugfs.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"igb.h\"\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/igb_ethtool.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n/* ethtool support for igb */\n\n#include \n#include \n\n#ifdef SIOCETHTOOL\n#include \n#ifdef CONFIG_PM_RUNTIME\n#include \n#endif /* CONFIG_PM_RUNTIME */\n#include \n\n#include \"igb.h\"\n#include \"igb_regtest.h\"\n#include \n#ifdef ETHTOOL_GEEE\n#include \n#endif\n\n#ifdef ETHTOOL_OPS_COMPAT\n#include \"kcompat_ethtool.c\"\n#endif\n#ifdef ETHTOOL_GSTATS\nstruct igb_stats {\n\tchar stat_string[ETH_GSTRING_LEN];\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\n#define IGB_STAT(_name, _stat) { \\\n\t.stat_string = _name, \\\n\t.sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \\\n\t.stat_offset = offsetof(struct igb_adapter, _stat) \\\n}\nstatic const struct igb_stats igb_gstrings_stats[] = {\n\tIGB_STAT(\"rx_packets\", stats.gprc),\n\tIGB_STAT(\"tx_packets\", stats.gptc),\n\tIGB_STAT(\"rx_bytes\", stats.gorc),\n\tIGB_STAT(\"tx_bytes\", stats.gotc),\n\tIGB_STAT(\"rx_broadcast\", stats.bprc),\n\tIGB_STAT(\"tx_broadcast\", stats.bptc),\n\tIGB_STAT(\"rx_multicast\", stats.mprc),\n\tIGB_STAT(\"tx_multicast\", stats.mptc),\n\tIGB_STAT(\"multicast\", stats.mprc),\n\tIGB_STAT(\"collisions\", stats.colc),\n\tIGB_STAT(\"rx_crc_errors\", stats.crcerrs),\n\tIGB_STAT(\"rx_no_buffer_count\", stats.rnbc),\n\tIGB_STAT(\"rx_missed_errors\", stats.mpc),\n\tIGB_STAT(\"tx_aborted_errors\", stats.ecol),\n\tIGB_STAT(\"tx_carrier_errors\", stats.tncrs),\n\tIGB_STAT(\"tx_window_errors\", stats.latecol),\n\tIGB_STAT(\"tx_abort_late_coll\", stats.latecol),\n\tIGB_STAT(\"tx_deferred_ok\", stats.dc),\n\tIGB_STAT(\"tx_single_coll_ok\", stats.scc),\n\tIGB_STAT(\"tx_multi_coll_ok\", stats.mcc),\n\tIGB_STAT(\"tx_timeout_count\", tx_timeout_count),\n\tIGB_STAT(\"rx_long_length_errors\", stats.roc),\n\tIGB_STAT(\"rx_short_length_errors\", stats.ruc),\n\tIGB_STAT(\"rx_align_errors\", stats.algnerrc),\n\tIGB_STAT(\"tx_tcp_seg_good\", stats.tsctc),\n\tIGB_STAT(\"tx_tcp_seg_failed\", stats.tsctfc),\n\tIGB_STAT(\"rx_flow_control_xon\", stats.xonrxc),\n\tIGB_STAT(\"rx_flow_control_xoff\", stats.xoffrxc),\n\tIGB_STAT(\"tx_flow_control_xon\", stats.xontxc),\n\tIGB_STAT(\"tx_flow_control_xoff\", stats.xofftxc),\n\tIGB_STAT(\"rx_long_byte_count\", stats.gorc),\n\tIGB_STAT(\"tx_dma_out_of_sync\", stats.doosync),\n#ifndef IGB_NO_LRO\n\tIGB_STAT(\"lro_aggregated\", lro_stats.coal),\n\tIGB_STAT(\"lro_flushed\", lro_stats.flushed),\n#endif /* IGB_LRO */\n\tIGB_STAT(\"tx_smbus\", stats.mgptc),\n\tIGB_STAT(\"rx_smbus\", stats.mgprc),\n\tIGB_STAT(\"dropped_smbus\", stats.mgpdc),\n\tIGB_STAT(\"os2bmc_rx_by_bmc\", stats.o2bgptc),\n\tIGB_STAT(\"os2bmc_tx_by_bmc\", stats.b2ospc),\n\tIGB_STAT(\"os2bmc_tx_by_host\", stats.o2bspc),\n\tIGB_STAT(\"os2bmc_rx_by_host\", stats.b2ogprc),\n#ifdef HAVE_PTP_1588_CLOCK\n\tIGB_STAT(\"tx_hwtstamp_timeouts\", tx_hwtstamp_timeouts),\n\tIGB_STAT(\"rx_hwtstamp_cleared\", rx_hwtstamp_cleared),\n#endif /* HAVE_PTP_1588_CLOCK */\n};\n\n#define IGB_NETDEV_STAT(_net_stat) { \\\n\t.stat_string = #_net_stat, \\\n\t.sizeof_stat = FIELD_SIZEOF(struct net_device_stats, _net_stat), \\\n\t.stat_offset = offsetof(struct net_device_stats, _net_stat) \\\n}\nstatic const struct igb_stats igb_gstrings_net_stats[] = {\n\tIGB_NETDEV_STAT(rx_errors),\n\tIGB_NETDEV_STAT(tx_errors),\n\tIGB_NETDEV_STAT(tx_dropped),\n\tIGB_NETDEV_STAT(rx_length_errors),\n\tIGB_NETDEV_STAT(rx_over_errors),\n\tIGB_NETDEV_STAT(rx_frame_errors),\n\tIGB_NETDEV_STAT(rx_fifo_errors),\n\tIGB_NETDEV_STAT(tx_fifo_errors),\n\tIGB_NETDEV_STAT(tx_heartbeat_errors)\n};\n\n#define IGB_GLOBAL_STATS_LEN ARRAY_SIZE(igb_gstrings_stats)\n#define IGB_NETDEV_STATS_LEN ARRAY_SIZE(igb_gstrings_net_stats)\n#define IGB_RX_QUEUE_STATS_LEN \\\n\t(sizeof(struct igb_rx_queue_stats) / sizeof(u64))\n#define IGB_TX_QUEUE_STATS_LEN \\\n\t(sizeof(struct igb_tx_queue_stats) / sizeof(u64))\n#define IGB_QUEUE_STATS_LEN \\\n\t((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \\\n\t IGB_RX_QUEUE_STATS_LEN) + \\\n\t (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \\\n\t IGB_TX_QUEUE_STATS_LEN))\n#define IGB_STATS_LEN \\\n\t(IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)\n\n#endif /* ETHTOOL_GSTATS */\n#ifdef ETHTOOL_TEST\nstatic const char igb_gstrings_test[][ETH_GSTRING_LEN] = {\n\t\"Register test (offline)\", \"Eeprom test (offline)\",\n\t\"Interrupt test (offline)\", \"Loopback test (offline)\",\n\t\"Link test (on/offline)\"\n};\n#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)\n#endif /* ETHTOOL_TEST */\n\nstatic int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 status;\n\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\n\t\tecmd->supported = (SUPPORTED_10baseT_Half |\n\t\t\t\t SUPPORTED_10baseT_Full |\n\t\t\t\t SUPPORTED_100baseT_Half |\n\t\t\t\t SUPPORTED_100baseT_Full |\n\t\t\t\t SUPPORTED_1000baseT_Full|\n\t\t\t\t SUPPORTED_Autoneg |\n\t\t\t\t SUPPORTED_TP |\n\t\t\t\t SUPPORTED_Pause);\n\t\tecmd->advertising = ADVERTISED_TP;\n\n\t\tif (hw->mac.autoneg == 1) {\n\t\t\tecmd->advertising |= ADVERTISED_Autoneg;\n\t\t\t/* the e1000 autoneg seems to match ethtool nicely */\n\t\t\tecmd->advertising |= hw->phy.autoneg_advertised;\n\t\t}\n\n\t\tecmd->port = PORT_TP;\n\t\tecmd->phy_address = hw->phy.addr;\n\t\tecmd->transceiver = XCVR_INTERNAL;\n\n\t} else {\n\t\tecmd->supported = (SUPPORTED_1000baseT_Full |\n\t\t\t\t SUPPORTED_100baseT_Full |\n\t\t\t\t SUPPORTED_FIBRE |\n\t\t\t\t SUPPORTED_Autoneg |\n\t\t\t\t SUPPORTED_Pause);\n\t\tif (hw->mac.type == e1000_i354)\n\t\t\tecmd->supported |= (SUPPORTED_2500baseX_Full);\n\n\t\tecmd->advertising = ADVERTISED_FIBRE;\n\n\t\tswitch (adapter->link_speed) {\n\t\tcase SPEED_2500:\n\t\t\tecmd->advertising = ADVERTISED_2500baseX_Full;\n\t\t\tbreak;\n\t\tcase SPEED_1000:\n\t\t\tecmd->advertising = ADVERTISED_1000baseT_Full;\n\t\t\tbreak;\n\t\tcase SPEED_100:\n\t\t\tecmd->advertising = ADVERTISED_100baseT_Full;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tif (hw->mac.autoneg == 1)\n\t\t\tecmd->advertising |= ADVERTISED_Autoneg;\n\n\t\tecmd->port = PORT_FIBRE;\n\t\tecmd->transceiver = XCVR_EXTERNAL;\n\t}\n\n\tif (hw->mac.autoneg != 1)\n\t\tecmd->advertising &= ~(ADVERTISED_Pause |\n\t\t\t\t ADVERTISED_Asym_Pause);\n\n\tif (hw->fc.requested_mode == e1000_fc_full)\n\t\tecmd->advertising |= ADVERTISED_Pause;\n\telse if (hw->fc.requested_mode == e1000_fc_rx_pause)\n\t\tecmd->advertising |= (ADVERTISED_Pause |\n\t\t\t\t ADVERTISED_Asym_Pause);\n\telse if (hw->fc.requested_mode == e1000_fc_tx_pause)\n\t\tecmd->advertising |= ADVERTISED_Asym_Pause;\n\telse\n\t\tecmd->advertising &= ~(ADVERTISED_Pause |\n\t\t\t\t ADVERTISED_Asym_Pause);\n\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\n\tif (status & E1000_STATUS_LU) {\n\t\tif ((hw->mac.type == e1000_i354) &&\n\t\t (status & E1000_STATUS_2P5_SKU) &&\n\t\t !(status & E1000_STATUS_2P5_SKU_OVER))\n\t\t\tecmd->speed = SPEED_2500;\n\t\telse if (status & E1000_STATUS_SPEED_1000)\n\t\t\tecmd->speed = SPEED_1000;\n\t\telse if (status & E1000_STATUS_SPEED_100)\n\t\t\tecmd->speed = SPEED_100;\n\t\telse\n\t\t\tecmd->speed = SPEED_10;\n\n\t\tif ((status & E1000_STATUS_FD) ||\n\t\t hw->phy.media_type != e1000_media_type_copper)\n\t\t\tecmd->duplex = DUPLEX_FULL;\n\t\telse\n\t\t\tecmd->duplex = DUPLEX_HALF;\n\n\t} else {\n\t\tecmd->speed = -1;\n\t\tecmd->duplex = -1;\n\t}\n\n\tif ((hw->phy.media_type == e1000_media_type_fiber) ||\n\t hw->mac.autoneg)\n\t\tecmd->autoneg = AUTONEG_ENABLE;\n\telse\n\t\tecmd->autoneg = AUTONEG_DISABLE;\n#ifdef ETH_TP_MDI_X\n\n\t/* MDI-X => 2; MDI =>1; Invalid =>0 */\n\tif (hw->phy.media_type == e1000_media_type_copper)\n\t\tecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :\n\t\t\t\t\t\t ETH_TP_MDI;\n\telse\n\t\tecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;\n\n#ifdef ETH_TP_MDI_AUTO\n\tif (hw->phy.mdix == AUTO_ALL_MODES)\n\t\tecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;\n\telse\n\t\tecmd->eth_tp_mdix_ctrl = hw->phy.mdix;\n\n#endif\n#endif /* ETH_TP_MDI_X */\n\treturn 0;\n}\n\nstatic int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\tif (ecmd->duplex == DUPLEX_HALF) {\n\t\tif (!hw->dev_spec._82575.eee_disable)\n\t\t\tdev_info(pci_dev_to_dev(adapter->pdev), \"EEE disabled: not supported with half duplex\\n\");\n\t\thw->dev_spec._82575.eee_disable = true;\n\t} else {\n\t\tif (hw->dev_spec._82575.eee_disable)\n\t\t\tdev_info(pci_dev_to_dev(adapter->pdev), \"EEE enabled\\n\");\n\t\thw->dev_spec._82575.eee_disable = false;\n\t}\n\n\t/* When SoL/IDER sessions are active, autoneg/speed/duplex\n\t * cannot be changed */\n\tif (e1000_check_reset_block(hw)) {\n\t\tdev_err(pci_dev_to_dev(adapter->pdev), \"Cannot change link \"\n\t\t\t\"characteristics when SoL/IDER is active.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n#ifdef ETH_TP_MDI_AUTO\n\t/*\n\t * MDI setting is only allowed when autoneg enabled because\n\t * some hardware doesn't allow MDI setting when speed or\n\t * duplex is forced.\n\t */\n\tif (ecmd->eth_tp_mdix_ctrl) {\n\t\tif (hw->phy.media_type != e1000_media_type_copper)\n\t\t\treturn -EOPNOTSUPP;\n\n\t\tif ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&\n\t\t (ecmd->autoneg != AUTONEG_ENABLE)) {\n\t\t\tdev_err(&adapter->pdev->dev, \"forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n#endif /* ETH_TP_MDI_AUTO */\n\twhile (test_and_set_bit(__IGB_RESETTING, &adapter->state))\n\t\tusleep_range(1000, 2000);\n\n\tif (ecmd->autoneg == AUTONEG_ENABLE) {\n\t\thw->mac.autoneg = 1;\n\t\tif (hw->phy.media_type == e1000_media_type_fiber) {\n\t\t\thw->phy.autoneg_advertised = ecmd->advertising |\n\t\t\t\t\t\t ADVERTISED_FIBRE |\n\t\t\t\t\t\t ADVERTISED_Autoneg;\n\t\t\tswitch (adapter->link_speed) {\n\t\t\tcase SPEED_2500:\n\t\t\t\thw->phy.autoneg_advertised =\n\t\t\t\t\tADVERTISED_2500baseX_Full;\n\t\t\t\tbreak;\n\t\t\tcase SPEED_1000:\n\t\t\t\thw->phy.autoneg_advertised =\n\t\t\t\t\tADVERTISED_1000baseT_Full;\n\t\t\t\tbreak;\n\t\t\tcase SPEED_100:\n\t\t\t\thw->phy.autoneg_advertised =\n\t\t\t\t\tADVERTISED_100baseT_Full;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else {\n\t\t\thw->phy.autoneg_advertised = ecmd->advertising |\n\t\t\t\t\t\t ADVERTISED_TP |\n\t\t\t\t\t\t ADVERTISED_Autoneg;\n\t\t}\n\t\tecmd->advertising = hw->phy.autoneg_advertised;\n\t\tif (adapter->fc_autoneg)\n\t\t\thw->fc.requested_mode = e1000_fc_default;\n\t} else {\n\t\tif (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {\n\t\t\tclear_bit(__IGB_RESETTING, &adapter->state);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n#ifdef ETH_TP_MDI_AUTO\n\t/* MDI-X => 2; MDI => 1; Auto => 3 */\n\tif (ecmd->eth_tp_mdix_ctrl) {\n\t\t/* fix up the value for auto (3 => 0) as zero is mapped\n\t\t * internally to auto\n\t\t */\n\t\tif (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)\n\t\t\thw->phy.mdix = AUTO_ALL_MODES;\n\t\telse\n\t\t\thw->phy.mdix = ecmd->eth_tp_mdix_ctrl;\n\t}\n\n#endif /* ETH_TP_MDI_AUTO */\n\t/* reset the link */\n\tif (netif_running(adapter->netdev)) {\n\t\tigb_down(adapter);\n\t\tigb_up(adapter);\n\t} else\n\t\tigb_reset(adapter);\n\n\tclear_bit(__IGB_RESETTING, &adapter->state);\n\treturn 0;\n}\n\nstatic u32 igb_get_link(struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_mac_info *mac = &adapter->hw.mac;\n\n\t/*\n\t * If the link is not reported up to netdev, interrupts are disabled,\n\t * and so the physical link state may have changed since we last\n\t * looked. Set get_link_status to make sure that the true link\n\t * state is interrogated, rather than pulling a cached and possibly\n\t * stale link state from the driver.\n\t */\n\tif (!netif_carrier_ok(netdev))\n\t\tmac->get_link_status = 1;\n\n\treturn igb_has_link(adapter);\n}\n\nstatic void igb_get_pauseparam(struct net_device *netdev,\n\t\t\t struct ethtool_pauseparam *pause)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\tpause->autoneg =\n\t\t(adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);\n\n\tif (hw->fc.current_mode == e1000_fc_rx_pause)\n\t\tpause->rx_pause = 1;\n\telse if (hw->fc.current_mode == e1000_fc_tx_pause)\n\t\tpause->tx_pause = 1;\n\telse if (hw->fc.current_mode == e1000_fc_full) {\n\t\tpause->rx_pause = 1;\n\t\tpause->tx_pause = 1;\n\t}\n}\n\nstatic int igb_set_pauseparam(struct net_device *netdev,\n\t\t\t struct ethtool_pauseparam *pause)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint retval = 0;\n\n\tadapter->fc_autoneg = pause->autoneg;\n\n\twhile (test_and_set_bit(__IGB_RESETTING, &adapter->state))\n\t\tusleep_range(1000, 2000);\n\n\tif (adapter->fc_autoneg == AUTONEG_ENABLE) {\n\t\thw->fc.requested_mode = e1000_fc_default;\n\t\tif (netif_running(adapter->netdev)) {\n\t\t\tigb_down(adapter);\n\t\t\tigb_up(adapter);\n\t\t} else {\n\t\t\tigb_reset(adapter);\n\t\t}\n\t} else {\n\t\tif (pause->rx_pause && pause->tx_pause)\n\t\t\thw->fc.requested_mode = e1000_fc_full;\n\t\telse if (pause->rx_pause && !pause->tx_pause)\n\t\t\thw->fc.requested_mode = e1000_fc_rx_pause;\n\t\telse if (!pause->rx_pause && pause->tx_pause)\n\t\t\thw->fc.requested_mode = e1000_fc_tx_pause;\n\t\telse if (!pause->rx_pause && !pause->tx_pause)\n\t\t\thw->fc.requested_mode = e1000_fc_none;\n\n\t\thw->fc.current_mode = hw->fc.requested_mode;\n\n\t\tif (hw->phy.media_type == e1000_media_type_fiber) {\n\t\t\tretval = hw->mac.ops.setup_link(hw);\n\t\t\t/* implicit goto out */\n\t\t} else {\n\t\t\tretval = e1000_force_mac_fc(hw);\n\t\t\tif (retval)\n\t\t\t\tgoto out;\n\t\t\te1000_set_fc_watermarks_generic(hw);\n\t\t}\n\t}\n\nout:\n\tclear_bit(__IGB_RESETTING, &adapter->state);\n\treturn retval;\n}\n\nstatic u32 igb_get_msglevel(struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\treturn adapter->msg_enable;\n}\n\nstatic void igb_set_msglevel(struct net_device *netdev, u32 data)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tadapter->msg_enable = data;\n}\n\nstatic int igb_get_regs_len(struct net_device *netdev)\n{\n#define IGB_REGS_LEN 555\n\treturn IGB_REGS_LEN * sizeof(u32);\n}\n\nstatic void igb_get_regs(struct net_device *netdev,\n\t\t\t struct ethtool_regs *regs, void *p)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 *regs_buff = p;\n\tu8 i;\n\n\tmemset(p, 0, IGB_REGS_LEN * sizeof(u32));\n\n\tregs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;\n\n\t/* General Registers */\n\tregs_buff[0] = E1000_READ_REG(hw, E1000_CTRL);\n\tregs_buff[1] = E1000_READ_REG(hw, E1000_STATUS);\n\tregs_buff[2] = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tregs_buff[3] = E1000_READ_REG(hw, E1000_MDIC);\n\tregs_buff[4] = E1000_READ_REG(hw, E1000_SCTL);\n\tregs_buff[5] = E1000_READ_REG(hw, E1000_CONNSW);\n\tregs_buff[6] = E1000_READ_REG(hw, E1000_VET);\n\tregs_buff[7] = E1000_READ_REG(hw, E1000_LEDCTL);\n\tregs_buff[8] = E1000_READ_REG(hw, E1000_PBA);\n\tregs_buff[9] = E1000_READ_REG(hw, E1000_PBS);\n\tregs_buff[10] = E1000_READ_REG(hw, E1000_FRTIMER);\n\tregs_buff[11] = E1000_READ_REG(hw, E1000_TCPTIMER);\n\n\t/* NVM Register */\n\tregs_buff[12] = E1000_READ_REG(hw, E1000_EECD);\n\n\t/* Interrupt */\n\t/* Reading EICS for EICR because they read the\n\t * same but EICS does not clear on read */\n\tregs_buff[13] = E1000_READ_REG(hw, E1000_EICS);\n\tregs_buff[14] = E1000_READ_REG(hw, E1000_EICS);\n\tregs_buff[15] = E1000_READ_REG(hw, E1000_EIMS);\n\tregs_buff[16] = E1000_READ_REG(hw, E1000_EIMC);\n\tregs_buff[17] = E1000_READ_REG(hw, E1000_EIAC);\n\tregs_buff[18] = E1000_READ_REG(hw, E1000_EIAM);\n\t/* Reading ICS for ICR because they read the\n\t * same but ICS does not clear on read */\n\tregs_buff[19] = E1000_READ_REG(hw, E1000_ICS);\n\tregs_buff[20] = E1000_READ_REG(hw, E1000_ICS);\n\tregs_buff[21] = E1000_READ_REG(hw, E1000_IMS);\n\tregs_buff[22] = E1000_READ_REG(hw, E1000_IMC);\n\tregs_buff[23] = E1000_READ_REG(hw, E1000_IAC);\n\tregs_buff[24] = E1000_READ_REG(hw, E1000_IAM);\n\tregs_buff[25] = E1000_READ_REG(hw, E1000_IMIRVP);\n\n\t/* Flow Control */\n\tregs_buff[26] = E1000_READ_REG(hw, E1000_FCAL);\n\tregs_buff[27] = E1000_READ_REG(hw, E1000_FCAH);\n\tregs_buff[28] = E1000_READ_REG(hw, E1000_FCTTV);\n\tregs_buff[29] = E1000_READ_REG(hw, E1000_FCRTL);\n\tregs_buff[30] = E1000_READ_REG(hw, E1000_FCRTH);\n\tregs_buff[31] = E1000_READ_REG(hw, E1000_FCRTV);\n\n\t/* Receive */\n\tregs_buff[32] = E1000_READ_REG(hw, E1000_RCTL);\n\tregs_buff[33] = E1000_READ_REG(hw, E1000_RXCSUM);\n\tregs_buff[34] = E1000_READ_REG(hw, E1000_RLPML);\n\tregs_buff[35] = E1000_READ_REG(hw, E1000_RFCTL);\n\tregs_buff[36] = E1000_READ_REG(hw, E1000_MRQC);\n\tregs_buff[37] = E1000_READ_REG(hw, E1000_VT_CTL);\n\n\t/* Transmit */\n\tregs_buff[38] = E1000_READ_REG(hw, E1000_TCTL);\n\tregs_buff[39] = E1000_READ_REG(hw, E1000_TCTL_EXT);\n\tregs_buff[40] = E1000_READ_REG(hw, E1000_TIPG);\n\tregs_buff[41] = E1000_READ_REG(hw, E1000_DTXCTL);\n\n\t/* Wake Up */\n\tregs_buff[42] = E1000_READ_REG(hw, E1000_WUC);\n\tregs_buff[43] = E1000_READ_REG(hw, E1000_WUFC);\n\tregs_buff[44] = E1000_READ_REG(hw, E1000_WUS);\n\tregs_buff[45] = E1000_READ_REG(hw, E1000_IPAV);\n\tregs_buff[46] = E1000_READ_REG(hw, E1000_WUPL);\n\n\t/* MAC */\n\tregs_buff[47] = E1000_READ_REG(hw, E1000_PCS_CFG0);\n\tregs_buff[48] = E1000_READ_REG(hw, E1000_PCS_LCTL);\n\tregs_buff[49] = E1000_READ_REG(hw, E1000_PCS_LSTAT);\n\tregs_buff[50] = E1000_READ_REG(hw, E1000_PCS_ANADV);\n\tregs_buff[51] = E1000_READ_REG(hw, E1000_PCS_LPAB);\n\tregs_buff[52] = E1000_READ_REG(hw, E1000_PCS_NPTX);\n\tregs_buff[53] = E1000_READ_REG(hw, E1000_PCS_LPABNP);\n\n\t/* Statistics */\n\tregs_buff[54] = adapter->stats.crcerrs;\n\tregs_buff[55] = adapter->stats.algnerrc;\n\tregs_buff[56] = adapter->stats.symerrs;\n\tregs_buff[57] = adapter->stats.rxerrc;\n\tregs_buff[58] = adapter->stats.mpc;\n\tregs_buff[59] = adapter->stats.scc;\n\tregs_buff[60] = adapter->stats.ecol;\n\tregs_buff[61] = adapter->stats.mcc;\n\tregs_buff[62] = adapter->stats.latecol;\n\tregs_buff[63] = adapter->stats.colc;\n\tregs_buff[64] = adapter->stats.dc;\n\tregs_buff[65] = adapter->stats.tncrs;\n\tregs_buff[66] = adapter->stats.sec;\n\tregs_buff[67] = adapter->stats.htdpmc;\n\tregs_buff[68] = adapter->stats.rlec;\n\tregs_buff[69] = adapter->stats.xonrxc;\n\tregs_buff[70] = adapter->stats.xontxc;\n\tregs_buff[71] = adapter->stats.xoffrxc;\n\tregs_buff[72] = adapter->stats.xofftxc;\n\tregs_buff[73] = adapter->stats.fcruc;\n\tregs_buff[74] = adapter->stats.prc64;\n\tregs_buff[75] = adapter->stats.prc127;\n\tregs_buff[76] = adapter->stats.prc255;\n\tregs_buff[77] = adapter->stats.prc511;\n\tregs_buff[78] = adapter->stats.prc1023;\n\tregs_buff[79] = adapter->stats.prc1522;\n\tregs_buff[80] = adapter->stats.gprc;\n\tregs_buff[81] = adapter->stats.bprc;\n\tregs_buff[82] = adapter->stats.mprc;\n\tregs_buff[83] = adapter->stats.gptc;\n\tregs_buff[84] = adapter->stats.gorc;\n\tregs_buff[86] = adapter->stats.gotc;\n\tregs_buff[88] = adapter->stats.rnbc;\n\tregs_buff[89] = adapter->stats.ruc;\n\tregs_buff[90] = adapter->stats.rfc;\n\tregs_buff[91] = adapter->stats.roc;\n\tregs_buff[92] = adapter->stats.rjc;\n\tregs_buff[93] = adapter->stats.mgprc;\n\tregs_buff[94] = adapter->stats.mgpdc;\n\tregs_buff[95] = adapter->stats.mgptc;\n\tregs_buff[96] = adapter->stats.tor;\n\tregs_buff[98] = adapter->stats.tot;\n\tregs_buff[100] = adapter->stats.tpr;\n\tregs_buff[101] = adapter->stats.tpt;\n\tregs_buff[102] = adapter->stats.ptc64;\n\tregs_buff[103] = adapter->stats.ptc127;\n\tregs_buff[104] = adapter->stats.ptc255;\n\tregs_buff[105] = adapter->stats.ptc511;\n\tregs_buff[106] = adapter->stats.ptc1023;\n\tregs_buff[107] = adapter->stats.ptc1522;\n\tregs_buff[108] = adapter->stats.mptc;\n\tregs_buff[109] = adapter->stats.bptc;\n\tregs_buff[110] = adapter->stats.tsctc;\n\tregs_buff[111] = adapter->stats.iac;\n\tregs_buff[112] = adapter->stats.rpthc;\n\tregs_buff[113] = adapter->stats.hgptc;\n\tregs_buff[114] = adapter->stats.hgorc;\n\tregs_buff[116] = adapter->stats.hgotc;\n\tregs_buff[118] = adapter->stats.lenerrs;\n\tregs_buff[119] = adapter->stats.scvpc;\n\tregs_buff[120] = adapter->stats.hrmpc;\n\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[121 + i] = E1000_READ_REG(hw, E1000_SRRCTL(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[125 + i] = E1000_READ_REG(hw, E1000_PSRTYPE(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[129 + i] = E1000_READ_REG(hw, E1000_RDBAL(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[133 + i] = E1000_READ_REG(hw, E1000_RDBAH(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[137 + i] = E1000_READ_REG(hw, E1000_RDLEN(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[141 + i] = E1000_READ_REG(hw, E1000_RDH(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[145 + i] = E1000_READ_REG(hw, E1000_RDT(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[149 + i] = E1000_READ_REG(hw, E1000_RXDCTL(i));\n\n\tfor (i = 0; i < 10; i++)\n\t\tregs_buff[153 + i] = E1000_READ_REG(hw, E1000_EITR(i));\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[163 + i] = E1000_READ_REG(hw, E1000_IMIR(i));\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[171 + i] = E1000_READ_REG(hw, E1000_IMIREXT(i));\n\tfor (i = 0; i < 16; i++)\n\t\tregs_buff[179 + i] = E1000_READ_REG(hw, E1000_RAL(i));\n\tfor (i = 0; i < 16; i++)\n\t\tregs_buff[195 + i] = E1000_READ_REG(hw, E1000_RAH(i));\n\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[211 + i] = E1000_READ_REG(hw, E1000_TDBAL(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[215 + i] = E1000_READ_REG(hw, E1000_TDBAH(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[219 + i] = E1000_READ_REG(hw, E1000_TDLEN(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[223 + i] = E1000_READ_REG(hw, E1000_TDH(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[227 + i] = E1000_READ_REG(hw, E1000_TDT(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[231 + i] = E1000_READ_REG(hw, E1000_TXDCTL(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[235 + i] = E1000_READ_REG(hw, E1000_TDWBAL(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[239 + i] = E1000_READ_REG(hw, E1000_TDWBAH(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[243 + i] = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));\n\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[247 + i] = E1000_READ_REG(hw, E1000_IP4AT_REG(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[251 + i] = E1000_READ_REG(hw, E1000_IP6AT_REG(i));\n\tfor (i = 0; i < 32; i++)\n\t\tregs_buff[255 + i] = E1000_READ_REG(hw, E1000_WUPM_REG(i));\n\tfor (i = 0; i < 128; i++)\n\t\tregs_buff[287 + i] = E1000_READ_REG(hw, E1000_FFMT_REG(i));\n\tfor (i = 0; i < 128; i++)\n\t\tregs_buff[415 + i] = E1000_READ_REG(hw, E1000_FFVT_REG(i));\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[543 + i] = E1000_READ_REG(hw, E1000_FFLT_REG(i));\n\n\tregs_buff[547] = E1000_READ_REG(hw, E1000_TDFH);\n\tregs_buff[548] = E1000_READ_REG(hw, E1000_TDFT);\n\tregs_buff[549] = E1000_READ_REG(hw, E1000_TDFHS);\n\tregs_buff[550] = E1000_READ_REG(hw, E1000_TDFPC);\n\tif (hw->mac.type > e1000_82580) {\n\t\tregs_buff[551] = adapter->stats.o2bgptc;\n\t\tregs_buff[552] = adapter->stats.b2ospc;\n\t\tregs_buff[553] = adapter->stats.o2bspc;\n\t\tregs_buff[554] = adapter->stats.b2ogprc;\n\t}\n}\n\nstatic int igb_get_eeprom_len(struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\treturn adapter->hw.nvm.word_size * 2;\n}\n\nstatic int igb_get_eeprom(struct net_device *netdev,\n\t\t\t struct ethtool_eeprom *eeprom, u8 *bytes)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu16 *eeprom_buff;\n\tint first_word, last_word;\n\tint ret_val = 0;\n\tu16 i;\n\n\tif (eeprom->len == 0)\n\t\treturn -EINVAL;\n\n\teeprom->magic = hw->vendor_id | (hw->device_id << 16);\n\n\tfirst_word = eeprom->offset >> 1;\n\tlast_word = (eeprom->offset + eeprom->len - 1) >> 1;\n\n\teeprom_buff = kmalloc(sizeof(u16) *\n\t\t\t(last_word - first_word + 1), GFP_KERNEL);\n\tif (!eeprom_buff)\n\t\treturn -ENOMEM;\n\n\tif (hw->nvm.type == e1000_nvm_eeprom_spi)\n\t\tret_val = e1000_read_nvm(hw, first_word,\n\t\t\t\t\t last_word - first_word + 1,\n\t\t\t\t\t eeprom_buff);\n\telse {\n\t\tfor (i = 0; i < last_word - first_word + 1; i++) {\n\t\t\tret_val = e1000_read_nvm(hw, first_word + i, 1,\n\t\t\t\t\t\t &eeprom_buff[i]);\n\t\t\tif (ret_val)\n\t\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Device's eeprom is always little-endian, word addressable */\n\tfor (i = 0; i < last_word - first_word + 1; i++)\n\t\teeprom_buff[i] = le16_to_cpu(eeprom_buff[i]);\n\n\tmemcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),\n\t\t\teeprom->len);\n\tkfree(eeprom_buff);\n\n\treturn ret_val;\n}\n\nstatic int igb_set_eeprom(struct net_device *netdev,\n\t\t\t struct ethtool_eeprom *eeprom, u8 *bytes)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu16 *eeprom_buff;\n\tvoid *ptr;\n\tint max_len, first_word, last_word, ret_val = 0;\n\tu16 i;\n\n\tif (eeprom->len == 0)\n\t\treturn -EOPNOTSUPP;\n\n\tif (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))\n\t\treturn -EFAULT;\n\n\tmax_len = hw->nvm.word_size * 2;\n\n\tfirst_word = eeprom->offset >> 1;\n\tlast_word = (eeprom->offset + eeprom->len - 1) >> 1;\n\teeprom_buff = kmalloc(max_len, GFP_KERNEL);\n\tif (!eeprom_buff)\n\t\treturn -ENOMEM;\n\n\tptr = (void *)eeprom_buff;\n\n\tif (eeprom->offset & 1) {\n\t\t/* need read/modify/write of first changed EEPROM word */\n\t\t/* only the second byte of the word is being modified */\n\t\tret_val = e1000_read_nvm(hw, first_word, 1,\n\t\t\t\t\t &eeprom_buff[0]);\n\t\tptr++;\n\t}\n\tif (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {\n\t\t/* need read/modify/write of last changed EEPROM word */\n\t\t/* only the first byte of the word is being modified */\n\t\tret_val = e1000_read_nvm(hw, last_word, 1,\n\t\t\t &eeprom_buff[last_word - first_word]);\n\t}\n\n\t/* Device's eeprom is always little-endian, word addressable */\n\tfor (i = 0; i < last_word - first_word + 1; i++)\n\t\tle16_to_cpus(&eeprom_buff[i]);\n\n\tmemcpy(ptr, bytes, eeprom->len);\n\n\tfor (i = 0; i < last_word - first_word + 1; i++)\n\t\tcpu_to_le16s(&eeprom_buff[i]);\n\n\tret_val = e1000_write_nvm(hw, first_word,\n\t\t\t\t last_word - first_word + 1, eeprom_buff);\n\n\t/* Update the checksum if write succeeded.\n\t * and flush shadow RAM for 82573 controllers */\n\tif (ret_val == 0)\n\t\te1000_update_nvm_checksum(hw);\n\n\tkfree(eeprom_buff);\n\treturn ret_val;\n}\n\nstatic void igb_get_drvinfo(struct net_device *netdev,\n\t\t\t struct ethtool_drvinfo *drvinfo)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\tstrncpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver) - 1);\n\tstrncpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version) - 1);\n\n\tstrncpy(drvinfo->fw_version, adapter->fw_version,\n\t\tsizeof(drvinfo->fw_version) - 1);\n\tstrncpy(drvinfo->bus_info, pci_name(adapter->pdev), sizeof(drvinfo->bus_info) -1);\n\tdrvinfo->n_stats = IGB_STATS_LEN;\n\tdrvinfo->testinfo_len = IGB_TEST_LEN;\n\tdrvinfo->regdump_len = igb_get_regs_len(netdev);\n\tdrvinfo->eedump_len = igb_get_eeprom_len(netdev);\n}\n\nstatic void igb_get_ringparam(struct net_device *netdev,\n\t\t\t struct ethtool_ringparam *ring)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\tring->rx_max_pending = IGB_MAX_RXD;\n\tring->tx_max_pending = IGB_MAX_TXD;\n\tring->rx_mini_max_pending = 0;\n\tring->rx_jumbo_max_pending = 0;\n\tring->rx_pending = adapter->rx_ring_count;\n\tring->tx_pending = adapter->tx_ring_count;\n\tring->rx_mini_pending = 0;\n\tring->rx_jumbo_pending = 0;\n}\n\nstatic int igb_set_ringparam(struct net_device *netdev,\n\t\t\t struct ethtool_ringparam *ring)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct igb_ring *temp_ring;\n\tint i, err = 0;\n\tu16 new_rx_count, new_tx_count;\n\n\tif ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))\n\t\treturn -EINVAL;\n\n\tnew_rx_count = min(ring->rx_pending, (u32)IGB_MAX_RXD);\n\tnew_rx_count = max(new_rx_count, (u16)IGB_MIN_RXD);\n\tnew_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);\n\n\tnew_tx_count = min(ring->tx_pending, (u32)IGB_MAX_TXD);\n\tnew_tx_count = max(new_tx_count, (u16)IGB_MIN_TXD);\n\tnew_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);\n\n\tif ((new_tx_count == adapter->tx_ring_count) &&\n\t (new_rx_count == adapter->rx_ring_count)) {\n\t\t/* nothing to do */\n\t\treturn 0;\n\t}\n\n\twhile (test_and_set_bit(__IGB_RESETTING, &adapter->state))\n\t\tusleep_range(1000, 2000);\n\n\tif (!netif_running(adapter->netdev)) {\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\t\tadapter->tx_ring[i]->count = new_tx_count;\n\t\tfor (i = 0; i < adapter->num_rx_queues; i++)\n\t\t\tadapter->rx_ring[i]->count = new_rx_count;\n\t\tadapter->tx_ring_count = new_tx_count;\n\t\tadapter->rx_ring_count = new_rx_count;\n\t\tgoto clear_reset;\n\t}\n\n\tif (adapter->num_tx_queues > adapter->num_rx_queues)\n\t\ttemp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));\n\telse\n\t\ttemp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));\n\n\tif (!temp_ring) {\n\t\terr = -ENOMEM;\n\t\tgoto clear_reset;\n\t}\n\n\tigb_down(adapter);\n\n\t/*\n\t * We can't just free everything and then setup again,\n\t * because the ISRs in MSI-X mode get passed pointers\n\t * to the tx and rx ring structs.\n\t */\n\tif (new_tx_count != adapter->tx_ring_count) {\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\t\tmemcpy(&temp_ring[i], adapter->tx_ring[i],\n\t\t\t sizeof(struct igb_ring));\n\n\t\t\ttemp_ring[i].count = new_tx_count;\n\t\t\terr = igb_setup_tx_resources(&temp_ring[i]);\n\t\t\tif (err) {\n\t\t\t\twhile (i) {\n\t\t\t\t\ti--;\n\t\t\t\t\tigb_free_tx_resources(&temp_ring[i]);\n\t\t\t\t}\n\t\t\t\tgoto err_setup;\n\t\t\t}\n\t\t}\n\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\t\tigb_free_tx_resources(adapter->tx_ring[i]);\n\n\t\t\tmemcpy(adapter->tx_ring[i], &temp_ring[i],\n\t\t\t sizeof(struct igb_ring));\n\t\t}\n\n\t\tadapter->tx_ring_count = new_tx_count;\n\t}\n\n\tif (new_rx_count != adapter->rx_ring_count) {\n\t\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\t\tmemcpy(&temp_ring[i], adapter->rx_ring[i],\n\t\t\t sizeof(struct igb_ring));\n\n\t\t\ttemp_ring[i].count = new_rx_count;\n\t\t\terr = igb_setup_rx_resources(&temp_ring[i]);\n\t\t\tif (err) {\n\t\t\t\twhile (i) {\n\t\t\t\t\ti--;\n\t\t\t\t\tigb_free_rx_resources(&temp_ring[i]);\n\t\t\t\t}\n\t\t\t\tgoto err_setup;\n\t\t\t}\n\n\t\t}\n\n\t\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\t\tigb_free_rx_resources(adapter->rx_ring[i]);\n\n\t\t\tmemcpy(adapter->rx_ring[i], &temp_ring[i],\n\t\t\t sizeof(struct igb_ring));\n\t\t}\n\n\t\tadapter->rx_ring_count = new_rx_count;\n\t}\nerr_setup:\n\tigb_up(adapter);\n\tvfree(temp_ring);\nclear_reset:\n\tclear_bit(__IGB_RESETTING, &adapter->state);\n\treturn err;\n}\nstatic bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,\n\t\t\t int reg, u32 mask, u32 write)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 pat, val;\n\tstatic const u32 _test[] =\n\t\t{0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};\n\tfor (pat = 0; pat < ARRAY_SIZE(_test); pat++) {\n\t\tE1000_WRITE_REG(hw, reg, (_test[pat] & write));\n\t\tval = E1000_READ_REG(hw, reg) & mask;\n\t\tif (val != (_test[pat] & write & mask)) {\n\t\t\tdev_err(pci_dev_to_dev(adapter->pdev), \"pattern test reg %04X \"\n\t\t\t\t\"failed: got 0x%08X expected 0x%08X\\n\",\n\t\t\t E1000_REGISTER(hw, reg), val, (_test[pat] & write & mask));\n\t\t\t*data = E1000_REGISTER(hw, reg);\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,\n\t\t\t int reg, u32 mask, u32 write)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 val;\n\tE1000_WRITE_REG(hw, reg, write & mask);\n\tval = E1000_READ_REG(hw, reg);\n\tif ((write & mask) != (val & mask)) {\n\t\tdev_err(pci_dev_to_dev(adapter->pdev), \"set/check reg %04X test failed:\"\n\t\t\t\" got 0x%08X expected 0x%08X\\n\", reg,\n\t\t\t(val & mask), (write & mask));\n\t\t*data = E1000_REGISTER(hw, reg);\n\t\treturn 1;\n\t}\n\n\treturn 0;\n}\n\n#define REG_PATTERN_TEST(reg, mask, write) \\\n\tdo { \\\n\t\tif (reg_pattern_test(adapter, data, reg, mask, write)) \\\n\t\t\treturn 1; \\\n\t} while (0)\n\n#define REG_SET_AND_CHECK(reg, mask, write) \\\n\tdo { \\\n\t\tif (reg_set_and_check(adapter, data, reg, mask, write)) \\\n\t\t\treturn 1; \\\n\t} while (0)\n\nstatic int igb_reg_test(struct igb_adapter *adapter, u64 *data)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct igb_reg_test *test;\n\tu32 value, before, after;\n\tu32 i, toggle;\n\n\tswitch (adapter->hw.mac.type) {\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\ttest = reg_test_i350;\n\t\ttoggle = 0x7FEFF3FF;\n\t\tbreak;\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\ttest = reg_test_i210;\n\t\ttoggle = 0x7FEFF3FF;\n\t\tbreak;\n\tcase e1000_82580:\n\t\ttest = reg_test_82580;\n\t\ttoggle = 0x7FEFF3FF;\n\t\tbreak;\n\tcase e1000_82576:\n\t\ttest = reg_test_82576;\n\t\ttoggle = 0x7FFFF3FF;\n\t\tbreak;\n\tdefault:\n\t\ttest = reg_test_82575;\n\t\ttoggle = 0x7FFFF3FF;\n\t\tbreak;\n\t}\n\n\t/* Because the status register is such a special case,\n\t * we handle it separately from the rest of the register\n\t * tests. Some bits are read-only, some toggle, and some\n\t * are writable on newer MACs.\n\t */\n\tbefore = E1000_READ_REG(hw, E1000_STATUS);\n\tvalue = (E1000_READ_REG(hw, E1000_STATUS) & toggle);\n\tE1000_WRITE_REG(hw, E1000_STATUS, toggle);\n\tafter = E1000_READ_REG(hw, E1000_STATUS) & toggle;\n\tif (value != after) {\n\t\tdev_err(pci_dev_to_dev(adapter->pdev), \"failed STATUS register test \"\n\t\t\t\"got: 0x%08X expected: 0x%08X\\n\", after, value);\n\t\t*data = 1;\n\t\treturn 1;\n\t}\n\t/* restore previous status */\n\tE1000_WRITE_REG(hw, E1000_STATUS, before);\n\n\t/* Perform the remainder of the register test, looping through\n\t * the test table until we either fail or reach the null entry.\n\t */\n\twhile (test->reg) {\n\t\tfor (i = 0; i < test->array_len; i++) {\n\t\t\tswitch (test->test_type) {\n\t\t\tcase PATTERN_TEST:\n\t\t\t\tREG_PATTERN_TEST(test->reg +\n\t\t\t\t\t\t(i * test->reg_offset),\n\t\t\t\t\t\ttest->mask,\n\t\t\t\t\t\ttest->write);\n\t\t\t\tbreak;\n\t\t\tcase SET_READ_TEST:\n\t\t\t\tREG_SET_AND_CHECK(test->reg +\n\t\t\t\t\t\t(i * test->reg_offset),\n\t\t\t\t\t\ttest->mask,\n\t\t\t\t\t\ttest->write);\n\t\t\t\tbreak;\n\t\t\tcase WRITE_NO_TEST:\n\t\t\t\twritel(test->write,\n\t\t\t\t (adapter->hw.hw_addr + test->reg)\n\t\t\t\t\t+ (i * test->reg_offset));\n\t\t\t\tbreak;\n\t\t\tcase TABLE32_TEST:\n\t\t\t\tREG_PATTERN_TEST(test->reg + (i * 4),\n\t\t\t\t\t\ttest->mask,\n\t\t\t\t\t\ttest->write);\n\t\t\t\tbreak;\n\t\t\tcase TABLE64_TEST_LO:\n\t\t\t\tREG_PATTERN_TEST(test->reg + (i * 8),\n\t\t\t\t\t\ttest->mask,\n\t\t\t\t\t\ttest->write);\n\t\t\t\tbreak;\n\t\t\tcase TABLE64_TEST_HI:\n\t\t\t\tREG_PATTERN_TEST((test->reg + 4) + (i * 8),\n\t\t\t\t\t\ttest->mask,\n\t\t\t\t\t\ttest->write);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\ttest++;\n\t}\n\n\t*data = 0;\n\treturn 0;\n}\n\nstatic int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)\n{\n\t*data = 0;\n\n\t/* Validate NVM checksum */\n\tif (e1000_validate_nvm_checksum(&adapter->hw) < 0)\n\t\t*data = 2;\n\n\treturn *data;\n}\n\nstatic irqreturn_t igb_test_intr(int irq, void *data)\n{\n\tstruct igb_adapter *adapter = (struct igb_adapter *) data;\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\tadapter->test_icr |= E1000_READ_REG(hw, E1000_ICR);\n\n\treturn IRQ_HANDLED;\n}\n\nstatic int igb_intr_test(struct igb_adapter *adapter, u64 *data)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct net_device *netdev = adapter->netdev;\n\tu32 mask, ics_mask, i = 0, shared_int = TRUE;\n\tu32 irq = adapter->pdev->irq;\n\n\t*data = 0;\n\n\t/* Hook up test interrupt handler just for this test */\n\tif (adapter->msix_entries) {\n\t\tif (request_irq(adapter->msix_entries[0].vector,\n\t\t &igb_test_intr, 0, netdev->name, adapter)) {\n\t\t\t*data = 1;\n\t\t\treturn -1;\n\t\t}\n\t} else if (adapter->flags & IGB_FLAG_HAS_MSI) {\n\t\tshared_int = FALSE;\n\t\tif (request_irq(irq,\n\t\t igb_test_intr, 0, netdev->name, adapter)) {\n\t\t\t*data = 1;\n\t\t\treturn -1;\n\t\t}\n\t} else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,\n\t\t\t\tnetdev->name, adapter)) {\n\t\tshared_int = FALSE;\n\t} else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,\n\t\t netdev->name, adapter)) {\n\t\t*data = 1;\n\t\treturn -1;\n\t}\n\tdev_info(pci_dev_to_dev(adapter->pdev), \"testing %s interrupt\\n\",\n\t\t (shared_int ? \"shared\" : \"unshared\"));\n\n\t/* Disable all the interrupts */\n\tE1000_WRITE_REG(hw, E1000_IMC, ~0);\n\tE1000_WRITE_FLUSH(hw);\n\tusleep_range(10000, 20000);\n\n\t/* Define all writable bits for ICS */\n\tswitch (hw->mac.type) {\n\tcase e1000_82575:\n\t\tics_mask = 0x37F47EDD;\n\t\tbreak;\n\tcase e1000_82576:\n\t\tics_mask = 0x77D4FBFD;\n\t\tbreak;\n\tcase e1000_82580:\n\t\tics_mask = 0x77DCFED5;\n\t\tbreak;\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\tics_mask = 0x77DCFED5;\n\t\tbreak;\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\tics_mask = 0x774CFED5;\n\t\tbreak;\n\tdefault:\n\t\tics_mask = 0x7FFFFFFF;\n\t\tbreak;\n\t}\n\n\t/* Test each interrupt */\n\tfor (; i < 31; i++) {\n\t\t/* Interrupt to test */\n\t\tmask = 1 << i;\n\n\t\tif (!(mask & ics_mask))\n\t\t\tcontinue;\n\n\t\tif (!shared_int) {\n\t\t\t/* Disable the interrupt to be reported in\n\t\t\t * the cause register and then force the same\n\t\t\t * interrupt and see if one gets posted. If\n\t\t\t * an interrupt was posted to the bus, the\n\t\t\t * test failed.\n\t\t\t */\n\t\t\tadapter->test_icr = 0;\n\n\t\t\t/* Flush any pending interrupts */\n\t\t\tE1000_WRITE_REG(hw, E1000_ICR, ~0);\n\n\t\t\tE1000_WRITE_REG(hw, E1000_IMC, mask);\n\t\t\tE1000_WRITE_REG(hw, E1000_ICS, mask);\n\t\t\tE1000_WRITE_FLUSH(hw);\n\t\t\tusleep_range(10000, 20000);\n\n\t\t\tif (adapter->test_icr & mask) {\n\t\t\t\t*data = 3;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/* Enable the interrupt to be reported in\n\t\t * the cause register and then force the same\n\t\t * interrupt and see if one gets posted. If\n\t\t * an interrupt was not posted to the bus, the\n\t\t * test failed.\n\t\t */\n\t\tadapter->test_icr = 0;\n\n\t\t/* Flush any pending interrupts */\n\t\tE1000_WRITE_REG(hw, E1000_ICR, ~0);\n\n\t\tE1000_WRITE_REG(hw, E1000_IMS, mask);\n\t\tE1000_WRITE_REG(hw, E1000_ICS, mask);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tusleep_range(10000, 20000);\n\n\t\tif (!(adapter->test_icr & mask)) {\n\t\t\t*data = 4;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (!shared_int) {\n\t\t\t/* Disable the other interrupts to be reported in\n\t\t\t * the cause register and then force the other\n\t\t\t * interrupts and see if any get posted. If\n\t\t\t * an interrupt was posted to the bus, the\n\t\t\t * test failed.\n\t\t\t */\n\t\t\tadapter->test_icr = 0;\n\n\t\t\t/* Flush any pending interrupts */\n\t\t\tE1000_WRITE_REG(hw, E1000_ICR, ~0);\n\n\t\t\tE1000_WRITE_REG(hw, E1000_IMC, ~mask);\n\t\t\tE1000_WRITE_REG(hw, E1000_ICS, ~mask);\n\t\t\tE1000_WRITE_FLUSH(hw);\n\t\t\tusleep_range(10000, 20000);\n\n\t\t\tif (adapter->test_icr & mask) {\n\t\t\t\t*data = 5;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Disable all the interrupts */\n\tE1000_WRITE_REG(hw, E1000_IMC, ~0);\n\tE1000_WRITE_FLUSH(hw);\n\tusleep_range(10000, 20000);\n\n\t/* Unhook test interrupt handler */\n\tif (adapter->msix_entries)\n\t\tfree_irq(adapter->msix_entries[0].vector, adapter);\n\telse\n\t\tfree_irq(irq, adapter);\n\n\treturn *data;\n}\n\nstatic void igb_free_desc_rings(struct igb_adapter *adapter)\n{\n\tigb_free_tx_resources(&adapter->test_tx_ring);\n\tigb_free_rx_resources(&adapter->test_rx_ring);\n}\n\nstatic int igb_setup_desc_rings(struct igb_adapter *adapter)\n{\n\tstruct igb_ring *tx_ring = &adapter->test_tx_ring;\n\tstruct igb_ring *rx_ring = &adapter->test_rx_ring;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint ret_val;\n\n\t/* Setup Tx descriptor ring and Tx buffers */\n\ttx_ring->count = IGB_DEFAULT_TXD;\n\ttx_ring->dev = pci_dev_to_dev(adapter->pdev);\n\ttx_ring->netdev = adapter->netdev;\n\ttx_ring->reg_idx = adapter->vfs_allocated_count;\n\n\tif (igb_setup_tx_resources(tx_ring)) {\n\t\tret_val = 1;\n\t\tgoto err_nomem;\n\t}\n\n\tigb_setup_tctl(adapter);\n\tigb_configure_tx_ring(adapter, tx_ring);\n\n\t/* Setup Rx descriptor ring and Rx buffers */\n\trx_ring->count = IGB_DEFAULT_RXD;\n\trx_ring->dev = pci_dev_to_dev(adapter->pdev);\n\trx_ring->netdev = adapter->netdev;\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\trx_ring->rx_buffer_len = IGB_RX_HDR_LEN;\n#endif\n\trx_ring->reg_idx = adapter->vfs_allocated_count;\n\n\tif (igb_setup_rx_resources(rx_ring)) {\n\t\tret_val = 2;\n\t\tgoto err_nomem;\n\t}\n\n\t/* set the default queue to queue 0 of PF */\n\tE1000_WRITE_REG(hw, E1000_MRQC, adapter->vfs_allocated_count << 3);\n\n\t/* enable receive ring */\n\tigb_setup_rctl(adapter);\n\tigb_configure_rx_ring(adapter, rx_ring);\n\n\tigb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));\n\n\treturn 0;\n\nerr_nomem:\n\tigb_free_desc_rings(adapter);\n\treturn ret_val;\n}\n\nstatic void igb_phy_disable_receiver(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\t/* Write out to PHY registers 29 and 30 to disable the Receiver. */\n\te1000_write_phy_reg(hw, 29, 0x001F);\n\te1000_write_phy_reg(hw, 30, 0x8FFC);\n\te1000_write_phy_reg(hw, 29, 0x001A);\n\te1000_write_phy_reg(hw, 30, 0x8FF0);\n}\n\nstatic int igb_integrated_phy_loopback(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 ctrl_reg = 0;\n\n\thw->mac.autoneg = FALSE;\n\n\tif (hw->phy.type == e1000_phy_m88) {\n\t\tif (hw->phy.id != I210_I_PHY_ID) {\n\t\t\t/* Auto-MDI/MDIX Off */\n\t\t\te1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);\n\t\t\t/* reset to update Auto-MDI/MDIX */\n\t\t\te1000_write_phy_reg(hw, PHY_CONTROL, 0x9140);\n\t\t\t/* autoneg off */\n\t\t\te1000_write_phy_reg(hw, PHY_CONTROL, 0x8140);\n\t\t} else {\n\t\t\t/* force 1000, set loopback */\n\t\t\te1000_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);\n\t\t\te1000_write_phy_reg(hw, PHY_CONTROL, 0x4140);\n\t\t}\n\t} else {\n\t\t/* enable MII loopback */\n\t\tif (hw->phy.type == e1000_phy_82580)\n\t\t\te1000_write_phy_reg(hw, I82577_PHY_LBK_CTRL, 0x8041);\n\t}\n\n\t/* force 1000, set loopback */\n\te1000_write_phy_reg(hw, PHY_CONTROL, 0x4140);\n\n\t/* Now set up the MAC to the same speed/duplex as the PHY. */\n\tctrl_reg = E1000_READ_REG(hw, E1000_CTRL);\n\tctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */\n\tctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */\n\t\t E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */\n\t\t E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */\n\t\t E1000_CTRL_FD |\t /* Force Duplex to FULL */\n\t\t E1000_CTRL_SLU);\t /* Set link up enable bit */\n\n\tif (hw->phy.type == e1000_phy_m88)\n\t\tctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */\n\n\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);\n\n\t/* Disable the receiver on the PHY so when a cable is plugged in, the\n\t * PHY does not begin to autoneg when a cable is reconnected to the NIC.\n\t */\n\tif (hw->phy.type == e1000_phy_m88)\n\t\tigb_phy_disable_receiver(adapter);\n\n\tmdelay(500);\n\treturn 0;\n}\n\nstatic int igb_set_phy_loopback(struct igb_adapter *adapter)\n{\n\treturn igb_integrated_phy_loopback(adapter);\n}\n\nstatic int igb_setup_loopback_test(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 reg;\n\n\treg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\n\t/* use CTRL_EXT to identify link type as SGMII can appear as copper */\n\tif (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {\n if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||\n (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||\n (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||\n (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {\n\n /* Enable DH89xxCC MPHY for near end loopback */\n reg = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTL);\n reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |\n E1000_MPHY_PCS_CLK_REG_OFFSET;\n E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTL, reg);\n\n reg = E1000_READ_REG(hw, E1000_MPHY_DATA);\n reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;\n E1000_WRITE_REG(hw, E1000_MPHY_DATA, reg);\n }\n\n\t\treg = E1000_READ_REG(hw, E1000_RCTL);\n\t\treg |= E1000_RCTL_LBM_TCVR;\n\t\tE1000_WRITE_REG(hw, E1000_RCTL, reg);\n\n\t\tE1000_WRITE_REG(hw, E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);\n\n\t\treg = E1000_READ_REG(hw, E1000_CTRL);\n\t\treg &= ~(E1000_CTRL_RFCE |\n\t\t\t E1000_CTRL_TFCE |\n\t\t\t E1000_CTRL_LRST);\n\t\treg |= E1000_CTRL_SLU |\n\t\t E1000_CTRL_FD;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, reg);\n\n\t\t/* Unset switch control to serdes energy detect */\n\t\treg = E1000_READ_REG(hw, E1000_CONNSW);\n\t\treg &= ~E1000_CONNSW_ENRGSRC;\n\t\tE1000_WRITE_REG(hw, E1000_CONNSW, reg);\n\n\t\t/* Unset sigdetect for SERDES loopback on\n\t\t * 82580 and newer devices\n\t\t */\n\t\tif (hw->mac.type >= e1000_82580) {\n\t\t\treg = E1000_READ_REG(hw, E1000_PCS_CFG0);\n\t\t\treg |= E1000_PCS_CFG_IGN_SD;\n\t\t\tE1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);\n\t\t}\n\n\t\t/* Set PCS register for forced speed */\n\t\treg = E1000_READ_REG(hw, E1000_PCS_LCTL);\n\t\treg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/\n\t\treg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */\n\t\t E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */\n\t\t E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */\n\t\t E1000_PCS_LCTL_FSD | /* Force Speed */\n\t\t E1000_PCS_LCTL_FORCE_LINK; /* Force Link */\n\t\tE1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);\n\n\t\treturn 0;\n\t}\n\n\treturn igb_set_phy_loopback(adapter);\n}\n\nstatic void igb_loopback_cleanup(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 rctl;\n\tu16 phy_reg;\n\n if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||\n\t (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||\n\t (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||\n (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {\n\t\tu32 reg;\n\n\t\t/* Disable near end loopback on DH89xxCC */\n\t\treg = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTL);\n reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK ) |\n E1000_MPHY_PCS_CLK_REG_OFFSET;\n\tE1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTL, reg);\n\n\t\treg = E1000_READ_REG(hw, E1000_MPHY_DATA);\n\treg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;\n\tE1000_WRITE_REG(hw, E1000_MPHY_DATA, reg);\n\t}\n\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\trctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\n\thw->mac.autoneg = TRUE;\n\te1000_read_phy_reg(hw, PHY_CONTROL, &phy_reg);\n\tif (phy_reg & MII_CR_LOOPBACK) {\n\t\tphy_reg &= ~MII_CR_LOOPBACK;\n\t\tif (hw->phy.type == I210_I_PHY_ID)\n\t\t\te1000_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);\n\t\te1000_write_phy_reg(hw, PHY_CONTROL, phy_reg);\n\t\te1000_phy_commit(hw);\n\t}\n}\nstatic void igb_create_lbtest_frame(struct sk_buff *skb,\n\t\t\t\t unsigned int frame_size)\n{\n\tmemset(skb->data, 0xFF, frame_size);\n\tframe_size /= 2;\n\tmemset(&skb->data[frame_size], 0xAA, frame_size - 1);\n\tmemset(&skb->data[frame_size + 10], 0xBE, 1);\n\tmemset(&skb->data[frame_size + 12], 0xAF, 1);\n}\n\nstatic int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,\n\t\t\t\t unsigned int frame_size)\n{\n\tunsigned char *data;\n\tbool match = true;\n\n\tframe_size >>= 1;\n\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\tdata = rx_buffer->skb->data;\n#else\n\tdata = kmap(rx_buffer->page);\n#endif\n\n\tif (data[3] != 0xFF ||\n\t data[frame_size + 10] != 0xBE ||\n\t data[frame_size + 12] != 0xAF)\n\t\tmatch = false;\n\n#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\tkunmap(rx_buffer->page);\n\n#endif\n\treturn match;\n}\n\nstatic u16 igb_clean_test_rings(struct igb_ring *rx_ring,\n struct igb_ring *tx_ring,\n unsigned int size)\n{\n\tunion e1000_adv_rx_desc *rx_desc;\n\tstruct igb_rx_buffer *rx_buffer_info;\n\tstruct igb_tx_buffer *tx_buffer_info;\n\tu16 rx_ntc, tx_ntc, count = 0;\n\n\t/* initialize next to clean and descriptor values */\n\trx_ntc = rx_ring->next_to_clean;\n\ttx_ntc = tx_ring->next_to_clean;\n\trx_desc = IGB_RX_DESC(rx_ring, rx_ntc);\n\n\twhile (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {\n\t\t/* check rx buffer */\n\t\trx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];\n\n\t\t/* sync Rx buffer for CPU read */\n\t\tdma_sync_single_for_cpu(rx_ring->dev,\n\t\t\t\t\trx_buffer_info->dma,\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\t\t\t\t\tIGB_RX_HDR_LEN,\n#else\n\t\t\t\t\tIGB_RX_BUFSZ,\n#endif\n\t\t\t\t\tDMA_FROM_DEVICE);\n\n\t\t/* verify contents of skb */\n\t\tif (igb_check_lbtest_frame(rx_buffer_info, size))\n\t\t\tcount++;\n\n\t\t/* sync Rx buffer for device write */\n\t\tdma_sync_single_for_device(rx_ring->dev,\n\t\t\t\t\t rx_buffer_info->dma,\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\t\t\t\t\t IGB_RX_HDR_LEN,\n#else\n\t\t\t\t\t IGB_RX_BUFSZ,\n#endif\n\t\t\t\t\t DMA_FROM_DEVICE);\n\n\t\t/* unmap buffer on tx side */\n\t\ttx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];\n\t\tigb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);\n\n\t\t/* increment rx/tx next to clean counters */\n\t\trx_ntc++;\n\t\tif (rx_ntc == rx_ring->count)\n\t\t\trx_ntc = 0;\n\t\ttx_ntc++;\n\t\tif (tx_ntc == tx_ring->count)\n\t\t\ttx_ntc = 0;\n\n\t\t/* fetch next descriptor */\n\t\trx_desc = IGB_RX_DESC(rx_ring, rx_ntc);\n\t}\n\n\t/* re-map buffers to ring, store next to clean values */\n\tigb_alloc_rx_buffers(rx_ring, count);\n\trx_ring->next_to_clean = rx_ntc;\n\ttx_ring->next_to_clean = tx_ntc;\n\n\treturn count;\n}\n\nstatic int igb_run_loopback_test(struct igb_adapter *adapter)\n{\n\tstruct igb_ring *tx_ring = &adapter->test_tx_ring;\n\tstruct igb_ring *rx_ring = &adapter->test_rx_ring;\n\tu16 i, j, lc, good_cnt;\n\tint ret_val = 0;\n\tunsigned int size = IGB_RX_HDR_LEN;\n\tnetdev_tx_t tx_ret_val;\n\tstruct sk_buff *skb;\n\n\t/* allocate test skb */\n\tskb = alloc_skb(size, GFP_KERNEL);\n\tif (!skb)\n\t\treturn 11;\n\n\t/* place data into test skb */\n\tigb_create_lbtest_frame(skb, size);\n\tskb_put(skb, size);\n\n\t/*\n\t * Calculate the loop count based on the largest descriptor ring\n\t * The idea is to wrap the largest ring a number of times using 64\n\t * send/receive pairs during each loop\n\t */\n\n\tif (rx_ring->count <= tx_ring->count)\n\t\tlc = ((tx_ring->count / 64) * 2) + 1;\n\telse\n\t\tlc = ((rx_ring->count / 64) * 2) + 1;\n\n\tfor (j = 0; j <= lc; j++) { /* loop count loop */\n\t\t/* reset count of good packets */\n\t\tgood_cnt = 0;\n\n\t\t/* place 64 packets on the transmit queue*/\n\t\tfor (i = 0; i < 64; i++) {\n\t\t\tskb_get(skb);\n\t\t\ttx_ret_val = igb_xmit_frame_ring(skb, tx_ring);\n\t\t\tif (tx_ret_val == NETDEV_TX_OK)\n\t\t\t\tgood_cnt++;\n\t\t}\n\n\t\tif (good_cnt != 64) {\n\t\t\tret_val = 12;\n\t\t\tbreak;\n\t\t}\n\n\t\t/* allow 200 milliseconds for packets to go from tx to rx */\n\t\tmsleep(200);\n\n\t\tgood_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);\n\t\tif (good_cnt != 64) {\n\t\t\tret_val = 13;\n\t\t\tbreak;\n\t\t}\n\t} /* end loop count loop */\n\n\t/* free the original skb */\n\tkfree_skb(skb);\n\n\treturn ret_val;\n}\n\nstatic int igb_loopback_test(struct igb_adapter *adapter, u64 *data)\n{\n\t/* PHY loopback cannot be performed if SoL/IDER\n\t * sessions are active */\n\tif (e1000_check_reset_block(&adapter->hw)) {\n\t\tdev_err(pci_dev_to_dev(adapter->pdev),\n\t\t\t\"Cannot do PHY loopback test \"\n\t\t\t\"when SoL/IDER is active.\\n\");\n\t\t*data = 0;\n\t\tgoto out;\n\t}\n\tif (adapter->hw.mac.type == e1000_i354) {\n\t\tdev_info(&adapter->pdev->dev,\n\t\t\t\"Loopback test not supported on i354.\\n\");\n\t\t*data = 0;\n\t\tgoto out;\n\t}\n\t*data = igb_setup_desc_rings(adapter);\n\tif (*data)\n\t\tgoto out;\n\t*data = igb_setup_loopback_test(adapter);\n\tif (*data)\n\t\tgoto err_loopback;\n\t*data = igb_run_loopback_test(adapter);\n\n\tigb_loopback_cleanup(adapter);\n\nerr_loopback:\n\tigb_free_desc_rings(adapter);\nout:\n\treturn *data;\n}\n\nstatic int igb_link_test(struct igb_adapter *adapter, u64 *data)\n{\n\tu32 link;\n\tint i, time;\n\n\t*data = 0;\n\ttime = 0;\n\tif (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {\n\t\tint i = 0;\n\t\tadapter->hw.mac.serdes_has_link = FALSE;\n\n\t\t/* On some blade server designs, link establishment\n\t\t * could take as long as 2-3 minutes */\n\t\tdo {\n\t\t\te1000_check_for_link(&adapter->hw);\n\t\t\tif (adapter->hw.mac.serdes_has_link)\n\t\t\t\tgoto out;\n\t\t\tmsleep(20);\n\t\t} while (i++ < 3750);\n\n\t\t*data = 1;\n\t} else {\n\t\tfor (i=0; i < IGB_MAX_LINK_TRIES; i++) {\n\t\tlink = igb_has_link(adapter);\n\t\t\tif (link)\n\t\t\t\tgoto out;\n\t\t\telse {\n\t\t\t\ttime++;\n\t\t\t\tmsleep(1000);\n\t\t\t}\n\t\t}\n\t\tif (!link)\n\t\t\t*data = 1;\n\t}\n\tout:\n\t\treturn *data;\n}\n\nstatic void igb_diag_test(struct net_device *netdev,\n\t\t\t struct ethtool_test *eth_test, u64 *data)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tu16 autoneg_advertised;\n\tu8 forced_speed_duplex, autoneg;\n\tbool if_running = netif_running(netdev);\n\n\tset_bit(__IGB_TESTING, &adapter->state);\n\tif (eth_test->flags == ETH_TEST_FL_OFFLINE) {\n\t\t/* Offline tests */\n\n\t\t/* save speed, duplex, autoneg settings */\n\t\tautoneg_advertised = adapter->hw.phy.autoneg_advertised;\n\t\tforced_speed_duplex = adapter->hw.mac.forced_speed_duplex;\n\t\tautoneg = adapter->hw.mac.autoneg;\n\n\t\tdev_info(pci_dev_to_dev(adapter->pdev), \"offline testing starting\\n\");\n\n\t\t/* power up link for link test */\n\t\tigb_power_up_link(adapter);\n\n\t\t/* Link test performed before hardware reset so autoneg doesn't\n\t\t * interfere with test result */\n\t\tif (igb_link_test(adapter, &data[4]))\n\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\n\t\tif (if_running)\n\t\t\t/* indicate we're in test mode */\n\t\t\tdev_close(netdev);\n\t\telse\n\t\t\tigb_reset(adapter);\n\n\t\tif (igb_reg_test(adapter, &data[0]))\n\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\n\t\tigb_reset(adapter);\n\t\tif (igb_eeprom_test(adapter, &data[1]))\n\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\n\t\tigb_reset(adapter);\n\t\tif (igb_intr_test(adapter, &data[2]))\n\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\n\t\tigb_reset(adapter);\n\n\t\t/* power up link for loopback test */\n\t\tigb_power_up_link(adapter);\n\n\t\tif (igb_loopback_test(adapter, &data[3]))\n\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\n\t\t/* restore speed, duplex, autoneg settings */\n\t\tadapter->hw.phy.autoneg_advertised = autoneg_advertised;\n\t\tadapter->hw.mac.forced_speed_duplex = forced_speed_duplex;\n\t\tadapter->hw.mac.autoneg = autoneg;\n\n\t\t/* force this routine to wait until autoneg complete/timeout */\n\t\tadapter->hw.phy.autoneg_wait_to_complete = TRUE;\n\t\tigb_reset(adapter);\n\t\tadapter->hw.phy.autoneg_wait_to_complete = FALSE;\n\n\t\tclear_bit(__IGB_TESTING, &adapter->state);\n\t\tif (if_running)\n\t\t\tdev_open(netdev);\n\t} else {\n\t\tdev_info(pci_dev_to_dev(adapter->pdev), \"online testing starting\\n\");\n\n\t\t/* PHY is powered down when interface is down */\n\t\tif (if_running && igb_link_test(adapter, &data[4]))\n\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\t\telse\n\t\t\tdata[4] = 0;\n\n\t\t/* Online tests aren't run; pass by default */\n\t\tdata[0] = 0;\n\t\tdata[1] = 0;\n\t\tdata[2] = 0;\n\t\tdata[3] = 0;\n\n\t\tclear_bit(__IGB_TESTING, &adapter->state);\n\t}\n\tmsleep_interruptible(4 * 1000);\n}\n\nstatic void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\twol->supported = WAKE_UCAST | WAKE_MCAST |\n\t WAKE_BCAST | WAKE_MAGIC |\n\t WAKE_PHY;\n\twol->wolopts = 0;\n\n\tif (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))\n\t\treturn;\n\n\t/* apply any specific unsupported masks here */\n\tswitch (adapter->hw.device_id) {\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (adapter->wol & E1000_WUFC_EX)\n\t\twol->wolopts |= WAKE_UCAST;\n\tif (adapter->wol & E1000_WUFC_MC)\n\t\twol->wolopts |= WAKE_MCAST;\n\tif (adapter->wol & E1000_WUFC_BC)\n\t\twol->wolopts |= WAKE_BCAST;\n\tif (adapter->wol & E1000_WUFC_MAG)\n\t\twol->wolopts |= WAKE_MAGIC;\n\tif (adapter->wol & E1000_WUFC_LNKC)\n\t\twol->wolopts |= WAKE_PHY;\n}\n\nstatic int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\tif (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))\n\t\treturn -EOPNOTSUPP;\n\n\tif (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))\n\t\treturn wol->wolopts ? -EOPNOTSUPP : 0;\n\n\t/* these settings will always override what we currently have */\n\tadapter->wol = 0;\n\n\tif (wol->wolopts & WAKE_UCAST)\n\t\tadapter->wol |= E1000_WUFC_EX;\n\tif (wol->wolopts & WAKE_MCAST)\n\t\tadapter->wol |= E1000_WUFC_MC;\n\tif (wol->wolopts & WAKE_BCAST)\n\t\tadapter->wol |= E1000_WUFC_BC;\n\tif (wol->wolopts & WAKE_MAGIC)\n\t\tadapter->wol |= E1000_WUFC_MAG;\n\tif (wol->wolopts & WAKE_PHY)\n\t\tadapter->wol |= E1000_WUFC_LNKC;\n\tdevice_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);\n\n\treturn 0;\n}\n\n/* bit defines for adapter->led_status */\n#ifdef HAVE_ETHTOOL_SET_PHYS_ID\nstatic int igb_set_phys_id(struct net_device *netdev,\n enum ethtool_phys_id_state state)\n{\n struct igb_adapter *adapter = netdev_priv(netdev);\n struct e1000_hw *hw = &adapter->hw;\n\n switch (state) {\n case ETHTOOL_ID_ACTIVE:\n\t\te1000_blink_led(hw);\n return 2;\n case ETHTOOL_ID_ON:\n e1000_led_on(hw);\n break;\n case ETHTOOL_ID_OFF:\n e1000_led_off(hw);\n break;\n case ETHTOOL_ID_INACTIVE:\n\t\te1000_led_off(hw);\n\t\te1000_cleanup_led(hw);\n break;\n }\n\n return 0;\n}\n#else\nstatic int igb_phys_id(struct net_device *netdev, u32 data)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tunsigned long timeout;\n\n\ttimeout = data * 1000;\n\n\t/*\n\t * msleep_interruptable only accepts unsigned int so we are limited\n\t * in how long a duration we can wait\n\t */\n\tif (!timeout || timeout > UINT_MAX)\n\t\ttimeout = UINT_MAX;\n\n\te1000_blink_led(hw);\n\tmsleep_interruptible(timeout);\n\n\te1000_led_off(hw);\n\te1000_cleanup_led(hw);\n\n\treturn 0;\n}\n#endif /* HAVE_ETHTOOL_SET_PHYS_ID */\n\nstatic int igb_set_coalesce(struct net_device *netdev,\n\t\t\t struct ethtool_coalesce *ec)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tint i;\n\n\tif ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||\n\t ((ec->rx_coalesce_usecs > 3) &&\n\t (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||\n\t (ec->rx_coalesce_usecs == 2))\n\t {\n\t \tprintk(\"set_coalesce:invalid parameter..\");\n\t\treturn -EINVAL;\n\t}\n\n\tif ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||\n\t ((ec->tx_coalesce_usecs > 3) &&\n\t (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||\n\t (ec->tx_coalesce_usecs == 2))\n\t\treturn -EINVAL;\n\n\tif ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)\n\t\treturn -EINVAL;\n\n\tif (ec->tx_max_coalesced_frames_irq)\n\t\tadapter->tx_work_limit = ec->tx_max_coalesced_frames_irq;\n\n\t/* If ITR is disabled, disable DMAC */\n\tif (ec->rx_coalesce_usecs == 0) {\n\t\tadapter->dmac = IGB_DMAC_DISABLE;\n\t}\n\n\t/* convert to rate of irq's per second */\n\tif (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)\n\t\tadapter->rx_itr_setting = ec->rx_coalesce_usecs;\n\telse\n\t\tadapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;\n\n\t/* convert to rate of irq's per second */\n\tif (adapter->flags & IGB_FLAG_QUEUE_PAIRS)\n\t\tadapter->tx_itr_setting = adapter->rx_itr_setting;\n\telse if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)\n\t\tadapter->tx_itr_setting = ec->tx_coalesce_usecs;\n\telse\n\t\tadapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;\n\n\tfor (i = 0; i < adapter->num_q_vectors; i++) {\n\t\tstruct igb_q_vector *q_vector = adapter->q_vector[i];\n\t\tq_vector->tx.work_limit = adapter->tx_work_limit;\n\t\tif (q_vector->rx.ring)\n\t\t\tq_vector->itr_val = adapter->rx_itr_setting;\n\t\telse\n\t\t\tq_vector->itr_val = adapter->tx_itr_setting;\n\t\tif (q_vector->itr_val && q_vector->itr_val <= 3)\n\t\t\tq_vector->itr_val = IGB_START_ITR;\n\t\tq_vector->set_itr = 1;\n\t}\n\n\treturn 0;\n}\n\nstatic int igb_get_coalesce(struct net_device *netdev,\n\t\t\t struct ethtool_coalesce *ec)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\tif (adapter->rx_itr_setting <= 3)\n\t\tec->rx_coalesce_usecs = adapter->rx_itr_setting;\n\telse\n\t\tec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;\n\n\tec->tx_max_coalesced_frames_irq = adapter->tx_work_limit;\n\n\tif (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {\n\t\tif (adapter->tx_itr_setting <= 3)\n\t\t\tec->tx_coalesce_usecs = adapter->tx_itr_setting;\n\t\telse\n\t\t\tec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;\n\t}\n\n\treturn 0;\n}\n\nstatic int igb_nway_reset(struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tif (netif_running(netdev))\n\t\tigb_reinit_locked(adapter);\n\treturn 0;\n}\n\n#ifdef HAVE_ETHTOOL_GET_SSET_COUNT\nstatic int igb_get_sset_count(struct net_device *netdev, int sset)\n{\n\tswitch (sset) {\n\tcase ETH_SS_STATS:\n\t\treturn IGB_STATS_LEN;\n\tcase ETH_SS_TEST:\n\t\treturn IGB_TEST_LEN;\n\tdefault:\n\t\treturn -ENOTSUPP;\n\t}\n}\n#else\nstatic int igb_get_stats_count(struct net_device *netdev)\n{\n\treturn IGB_STATS_LEN;\n}\n\nstatic int igb_diag_test_count(struct net_device *netdev)\n{\n\treturn IGB_TEST_LEN;\n}\n#endif\n\nstatic void igb_get_ethtool_stats(struct net_device *netdev,\n\t\t\t\t struct ethtool_stats *stats, u64 *data)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n#ifdef HAVE_NETDEV_STATS_IN_NETDEV\n\tstruct net_device_stats *net_stats = &netdev->stats;\n#else\n\tstruct net_device_stats *net_stats = &adapter->net_stats;\n#endif\n\tu64 *queue_stat;\n\tint i, j, k;\n\tchar *p;\n\n\tigb_update_stats(adapter);\n\n\tfor (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {\n\t\tp = (char *)adapter + igb_gstrings_stats[i].stat_offset;\n\t\tdata[i] = (igb_gstrings_stats[i].sizeof_stat ==\n\t\t\tsizeof(u64)) ? *(u64 *)p : *(u32 *)p;\n\t}\n\tfor (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {\n\t\tp = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;\n\t\tdata[i] = (igb_gstrings_net_stats[j].sizeof_stat ==\n\t\t\tsizeof(u64)) ? *(u64 *)p : *(u32 *)p;\n\t}\n\tfor (j = 0; j < adapter->num_tx_queues; j++) {\n\t\tqueue_stat = (u64 *)&adapter->tx_ring[j]->tx_stats;\n\t\tfor (k = 0; k < IGB_TX_QUEUE_STATS_LEN; k++, i++)\n\t\t\tdata[i] = queue_stat[k];\n\t}\n\tfor (j = 0; j < adapter->num_rx_queues; j++) {\n\t\tqueue_stat = (u64 *)&adapter->rx_ring[j]->rx_stats;\n\t\tfor (k = 0; k < IGB_RX_QUEUE_STATS_LEN; k++, i++)\n\t\t\tdata[i] = queue_stat[k];\n\t}\n}\n\nstatic void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tu8 *p = data;\n\tint i;\n\n\tswitch (stringset) {\n\tcase ETH_SS_TEST:\n\t\tmemcpy(data, *igb_gstrings_test,\n\t\t\tIGB_TEST_LEN*ETH_GSTRING_LEN);\n\t\tbreak;\n\tcase ETH_SS_STATS:\n\t\tfor (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {\n\t\t\tmemcpy(p, igb_gstrings_stats[i].stat_string,\n\t\t\t ETH_GSTRING_LEN);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t}\n\t\tfor (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {\n\t\t\tmemcpy(p, igb_gstrings_net_stats[i].stat_string,\n\t\t\t ETH_GSTRING_LEN);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t}\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\t\tsprintf(p, \"tx_queue_%u_packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"tx_queue_%u_bytes\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"tx_queue_%u_restart\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t}\n\t\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\t\tsprintf(p, \"rx_queue_%u_packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_bytes\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_drops\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_csum_err\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_alloc_failed\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_ipv4_packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_ipv4e_packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_ipv6_packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_ipv6e_packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_tcp_packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_udp_packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_sctp_packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_nfs_packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t}\n/*\t\tBUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */\n\t\tbreak;\n\t}\n}\n\n#ifdef HAVE_ETHTOOL_GET_TS_INFO\nstatic int igb_get_ts_info(struct net_device *dev,\n\t\t\t struct ethtool_ts_info *info)\n{\n\tstruct igb_adapter *adapter = netdev_priv(dev);\n\n\tswitch (adapter->hw.mac.type) {\n#ifdef HAVE_PTP_1588_CLOCK\n\tcase e1000_82575:\n\t\tinfo->so_timestamping =\n\t\t\tSOF_TIMESTAMPING_TX_SOFTWARE |\n\t\t\tSOF_TIMESTAMPING_RX_SOFTWARE |\n\t\t\tSOF_TIMESTAMPING_SOFTWARE;\n\t\treturn 0;\n\tcase e1000_82576:\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\tinfo->so_timestamping =\n\t\t\tSOF_TIMESTAMPING_TX_SOFTWARE |\n\t\t\tSOF_TIMESTAMPING_RX_SOFTWARE |\n\t\t\tSOF_TIMESTAMPING_SOFTWARE |\n\t\t\tSOF_TIMESTAMPING_TX_HARDWARE |\n\t\t\tSOF_TIMESTAMPING_RX_HARDWARE |\n\t\t\tSOF_TIMESTAMPING_RAW_HARDWARE;\n\n\t\tif (adapter->ptp_clock)\n\t\t\tinfo->phc_index = ptp_clock_index(adapter->ptp_clock);\n\t\telse\n\t\t\tinfo->phc_index = -1;\n\n\t\tinfo->tx_types =\n\t\t\t(1 << HWTSTAMP_TX_OFF) |\n\t\t\t(1 << HWTSTAMP_TX_ON);\n\n\t\tinfo->rx_filters = 1 << HWTSTAMP_FILTER_NONE;\n\n\t\t/* 82576 does not support timestamping all packets. */\n\t\tif (adapter->hw.mac.type >= e1000_82580)\n\t\t\tinfo->rx_filters |= 1 << HWTSTAMP_FILTER_ALL;\n\t\telse\n\t\t\tinfo->rx_filters |=\n\t\t\t\t(1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |\n\t\t\t\t(1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |\n\t\t\t\t(1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |\n\t\t\t\t(1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |\n\t\t\t\t(1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |\n\t\t\t\t(1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |\n\t\t\t\t(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);\n\n\t\treturn 0;\n#endif /* HAVE_PTP_1588_CLOCK */\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n}\n#endif /* HAVE_ETHTOOL_GET_TS_INFO */\n\n#ifdef CONFIG_PM_RUNTIME\nstatic int igb_ethtool_begin(struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\tpm_runtime_get_sync(&adapter->pdev->dev);\n\n\treturn 0;\n}\n\nstatic void igb_ethtool_complete(struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\tpm_runtime_put(&adapter->pdev->dev);\n}\n#endif /* CONFIG_PM_RUNTIME */\n\n#ifndef HAVE_NDO_SET_FEATURES\nstatic u32 igb_get_rx_csum(struct net_device *netdev)\n{\n\treturn !!(netdev->features & NETIF_F_RXCSUM);\n}\n\nstatic int igb_set_rx_csum(struct net_device *netdev, u32 data)\n{\n\tconst u32 feature_list = NETIF_F_RXCSUM;\n\n\tif (data)\n\t\tnetdev->features |= feature_list;\n\telse\n\t\tnetdev->features &= ~feature_list;\n\n\treturn 0;\n}\n\nstatic int igb_set_tx_csum(struct net_device *netdev, u32 data)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n#ifdef NETIF_F_IPV6_CSUM\n\tu32 feature_list = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;\n#else\n\tu32 feature_list = NETIF_F_IP_CSUM;\n#endif\n\n\tif (adapter->hw.mac.type >= e1000_82576)\n\t\tfeature_list |= NETIF_F_SCTP_CSUM;\n\n\tif (data)\n\t\tnetdev->features |= feature_list;\n\telse\n\t\tnetdev->features &= ~feature_list;\n\n\treturn 0;\n}\n\n#ifdef NETIF_F_TSO\nstatic int igb_set_tso(struct net_device *netdev, u32 data)\n{\n#ifdef NETIF_F_TSO6\n\tconst u32 feature_list = NETIF_F_TSO | NETIF_F_TSO6;\n#else\n\tconst u32 feature_list = NETIF_F_TSO;\n#endif\n\n\tif (data)\n\t\tnetdev->features |= feature_list;\n\telse\n\t\tnetdev->features &= ~feature_list;\n\n#ifndef HAVE_NETDEV_VLAN_FEATURES\n\tif (!data) {\n\t\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\t\tstruct net_device *v_netdev;\n\t\tint i;\n\n\t\t/* disable TSO on all VLANs if they're present */\n\t\tif (!adapter->vlgrp)\n\t\t\tgoto tso_out;\n\n\t\tfor (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {\n\t\t\tv_netdev = vlan_group_get_device(adapter->vlgrp, i);\n\t\t\tif (!v_netdev)\n\t\t\t\tcontinue;\n\n\t\t\tv_netdev->features &= ~feature_list;\n\t\t\tvlan_group_set_device(adapter->vlgrp, i, v_netdev);\n\t\t}\n\t}\n\ntso_out:\n\n#endif /* HAVE_NETDEV_VLAN_FEATURES */\n\treturn 0;\n}\n\n#endif /* NETIF_F_TSO */\n#ifdef ETHTOOL_GFLAGS\nstatic int igb_set_flags(struct net_device *netdev, u32 data)\n{\n\tu32 supported_flags = ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN |\n\t\t\t ETH_FLAG_RXHASH;\n#ifndef HAVE_VLAN_RX_REGISTER\n\tu32 changed = netdev->features ^ data;\n#endif\n\tint rc;\n#ifndef IGB_NO_LRO\n\n\tsupported_flags |= ETH_FLAG_LRO;\n#endif\n\t/*\n\t * Since there is no support for separate tx vlan accel\n\t * enabled make sure tx flag is cleared if rx is.\n\t */\n\tif (!(data & ETH_FLAG_RXVLAN))\n\t\tdata &= ~ETH_FLAG_TXVLAN;\n\n\trc = ethtool_op_set_flags(netdev, data, supported_flags);\n\tif (rc)\n\t\treturn rc;\n#ifndef HAVE_VLAN_RX_REGISTER\n\n\tif (changed & ETH_FLAG_RXVLAN)\n\t\tigb_vlan_mode(netdev, data);\n#endif\n\n\treturn 0;\n}\n\n#endif /* ETHTOOL_GFLAGS */\n#endif /* HAVE_NDO_SET_FEATURES */\n#ifdef ETHTOOL_SADV_COAL\nstatic int igb_set_adv_coal(struct net_device *netdev, struct ethtool_value *edata)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\tswitch (edata->data) {\n\tcase IGB_DMAC_DISABLE:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tcase IGB_DMAC_MIN:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tcase IGB_DMAC_500:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tcase IGB_DMAC_EN_DEFAULT:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tcase IGB_DMAC_2000:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tcase IGB_DMAC_3000:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tcase IGB_DMAC_4000:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tcase IGB_DMAC_5000:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tcase IGB_DMAC_6000:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tcase IGB_DMAC_7000:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tcase IGB_DMAC_8000:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tcase IGB_DMAC_9000:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tcase IGB_DMAC_MAX:\n\t\tadapter->dmac = edata->data;\n\t\tbreak;\n\tdefault:\n\t\tadapter->dmac = IGB_DMAC_DISABLE;\n\t\tprintk(\"set_dmac: invalid setting, setting DMAC to %d\\n\",\n\t\t\tadapter->dmac);\n\t}\n\tprintk(\"%s: setting DMAC to %d\\n\", netdev->name, adapter->dmac);\n\treturn 0;\n}\n#endif /* ETHTOOL_SADV_COAL */\n#ifdef ETHTOOL_GADV_COAL\nstatic void igb_get_dmac(struct net_device *netdev,\n\t\t\t struct ethtool_value *edata)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tedata->data = adapter->dmac;\n\n\treturn;\n}\n#endif\n\n#ifdef ETHTOOL_GEEE\nstatic int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 ret_val;\n\tu16 phy_data;\n\n\tif ((hw->mac.type < e1000_i350) ||\n\t (hw->phy.media_type != e1000_media_type_copper))\n\t\treturn -EOPNOTSUPP;\n\n\tedata->supported = (SUPPORTED_1000baseT_Full |\n\t\t\t SUPPORTED_100baseT_Full);\n\n\tif (!hw->dev_spec._82575.eee_disable)\n\t\tedata->advertised =\n\t\t\tmmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert);\n\n\t/* The IPCNFG and EEER registers are not supported on I354. */\n\tif (hw->mac.type == e1000_i354) {\n\t\te1000_get_eee_status_i354(hw, (bool *)&edata->eee_active);\n\t} else {\n\t\tu32 eeer;\n\n\t\teeer = E1000_READ_REG(hw, E1000_EEER);\n\n\t\t/* EEE status on negotiated link */\n\t\tif (eeer & E1000_EEER_EEE_NEG)\n\t\t\tedata->eee_active = true;\n\n\t\tif (eeer & E1000_EEER_TX_LPI_EN)\n\t\t\tedata->tx_lpi_enabled = true;\n\t}\n\n\t/* EEE Link Partner Advertised */\n\tswitch (hw->mac.type) {\n\tcase e1000_i350:\n\t\tret_val = e1000_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn -ENODATA;\n\n\t\tedata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);\n\n\t\tbreak;\n\tcase e1000_i354:\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\tret_val = e1000_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,\n\t\t\t\t\t E1000_EEE_LP_ADV_DEV_I210,\n\t\t\t\t\t &phy_data);\n\t\tif (ret_val)\n\t\t\treturn -ENODATA;\n\n\t\tedata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);\n\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tedata->eee_enabled = !hw->dev_spec._82575.eee_disable;\n\n\tif ((hw->mac.type == e1000_i354) &&\n\t (edata->eee_enabled))\n\t\tedata->tx_lpi_enabled = true;\n\n\t/*\n\t * report correct negotiated EEE status for devices that\n\t * wrongly report EEE at half-duplex\n\t */\n\tif (adapter->link_duplex == HALF_DUPLEX) {\n\t\tedata->eee_enabled = false;\n\t\tedata->eee_active = false;\n\t\tedata->tx_lpi_enabled = false;\n\t\tedata->advertised &= ~edata->advertised;\n\t}\n\n\treturn 0;\n}\n#endif\n\n#ifdef ETHTOOL_SEEE\nstatic int igb_set_eee(struct net_device *netdev,\n\t\t struct ethtool_eee *edata)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct ethtool_eee eee_curr;\n\ts32 ret_val;\n\n\tif ((hw->mac.type < e1000_i350) ||\n\t (hw->phy.media_type != e1000_media_type_copper))\n\t\treturn -EOPNOTSUPP;\n\n\tret_val = igb_get_eee(netdev, &eee_curr);\n\tif (ret_val)\n\t\treturn ret_val;\n\n\tif (eee_curr.eee_enabled) {\n\t\tif (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {\n\t\t\tdev_err(pci_dev_to_dev(adapter->pdev),\n\t\t\t\t\"Setting EEE tx-lpi is not supported\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\t/* Tx LPI time is not implemented currently */\n\t\tif (edata->tx_lpi_timer) {\n\t\t\tdev_err(pci_dev_to_dev(adapter->pdev),\n\t\t\t\t\"Setting EEE Tx LPI timer is not supported\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tif (edata->advertised &\n\t\t ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL)) {\n\t\t\tdev_err(pci_dev_to_dev(adapter->pdev),\n\t\t\t\t\"EEE Advertisement supports only 100Tx and or 100T full duplex\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t} else if (!edata->eee_enabled) {\n\t\tdev_err(pci_dev_to_dev(adapter->pdev),\n\t\t\t\"Setting EEE options is not supported with EEE disabled\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\tadapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised);\n\n\tif (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {\n\t\thw->dev_spec._82575.eee_disable = !edata->eee_enabled;\n\n\t\t/* reset link */\n\t\tif (netif_running(netdev))\n\t\t\tigb_reinit_locked(adapter);\n\t\telse\n\t\t\tigb_reset(adapter);\n\t}\n\n\treturn 0;\n}\n#endif /* ETHTOOL_SEEE */\n\n#ifdef ETHTOOL_GRXRINGS\nstatic int igb_get_rss_hash_opts(struct igb_adapter *adapter,\n\t\t\t\t struct ethtool_rxnfc *cmd)\n{\n\tcmd->data = 0;\n\n\t/* Report default options for RSS on igb */\n\tswitch (cmd->flow_type) {\n\tcase TCP_V4_FLOW:\n\t\tcmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;\n\tcase UDP_V4_FLOW:\n\t\tif (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)\n\t\t\tcmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;\n\tcase SCTP_V4_FLOW:\n\tcase AH_ESP_V4_FLOW:\n\tcase AH_V4_FLOW:\n\tcase ESP_V4_FLOW:\n\tcase IPV4_FLOW:\n\t\tcmd->data |= RXH_IP_SRC | RXH_IP_DST;\n\t\tbreak;\n\tcase TCP_V6_FLOW:\n\t\tcmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;\n\tcase UDP_V6_FLOW:\n\t\tif (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)\n\t\t\tcmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;\n\tcase SCTP_V6_FLOW:\n\tcase AH_ESP_V6_FLOW:\n\tcase AH_V6_FLOW:\n\tcase ESP_V6_FLOW:\n\tcase IPV6_FLOW:\n\t\tcmd->data |= RXH_IP_SRC | RXH_IP_DST;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,\n#ifdef HAVE_ETHTOOL_GET_RXNFC_VOID_RULE_LOCS\n\t\t\t void *rule_locs)\n#else\n\t\t\t u32 *rule_locs)\n#endif\n{\n\tstruct igb_adapter *adapter = netdev_priv(dev);\n\tint ret = -EOPNOTSUPP;\n\n\tswitch (cmd->cmd) {\n\tcase ETHTOOL_GRXRINGS:\n\t\tcmd->data = adapter->num_rx_queues;\n\t\tret = 0;\n\t\tbreak;\n\tcase ETHTOOL_GRXFH:\n\t\tret = igb_get_rss_hash_opts(adapter, cmd);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n#define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \\\n\t\t IGB_FLAG_RSS_FIELD_IPV6_UDP)\nstatic int igb_set_rss_hash_opt(struct igb_adapter *adapter,\n\t\t\t\tstruct ethtool_rxnfc *nfc)\n{\n\tu32 flags = adapter->flags;\n\n\t/*\n\t * RSS does not support anything other than hashing\n\t * to queues on src and dst IPs and ports\n\t */\n\tif (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |\n\t\t\t RXH_L4_B_0_1 | RXH_L4_B_2_3))\n\t\treturn -EINVAL;\n\n\tswitch (nfc->flow_type) {\n\tcase TCP_V4_FLOW:\n\tcase TCP_V6_FLOW:\n\t\tif (!(nfc->data & RXH_IP_SRC) ||\n\t\t !(nfc->data & RXH_IP_DST) ||\n\t\t !(nfc->data & RXH_L4_B_0_1) ||\n\t\t !(nfc->data & RXH_L4_B_2_3))\n\t\t\treturn -EINVAL;\n\t\tbreak;\n\tcase UDP_V4_FLOW:\n\t\tif (!(nfc->data & RXH_IP_SRC) ||\n\t\t !(nfc->data & RXH_IP_DST))\n\t\t\treturn -EINVAL;\n\t\tswitch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {\n\t\tcase 0:\n\t\t\tflags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;\n\t\t\tbreak;\n\t\tcase (RXH_L4_B_0_1 | RXH_L4_B_2_3):\n\t\t\tflags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tbreak;\n\tcase UDP_V6_FLOW:\n\t\tif (!(nfc->data & RXH_IP_SRC) ||\n\t\t !(nfc->data & RXH_IP_DST))\n\t\t\treturn -EINVAL;\n\t\tswitch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {\n\t\tcase 0:\n\t\t\tflags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;\n\t\t\tbreak;\n\t\tcase (RXH_L4_B_0_1 | RXH_L4_B_2_3):\n\t\t\tflags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tbreak;\n\tcase AH_ESP_V4_FLOW:\n\tcase AH_V4_FLOW:\n\tcase ESP_V4_FLOW:\n\tcase SCTP_V4_FLOW:\n\tcase AH_ESP_V6_FLOW:\n\tcase AH_V6_FLOW:\n\tcase ESP_V6_FLOW:\n\tcase SCTP_V6_FLOW:\n\t\tif (!(nfc->data & RXH_IP_SRC) ||\n\t\t !(nfc->data & RXH_IP_DST) ||\n\t\t (nfc->data & RXH_L4_B_0_1) ||\n\t\t (nfc->data & RXH_L4_B_2_3))\n\t\t\treturn -EINVAL;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\t/* if we changed something we need to update flags */\n\tif (flags != adapter->flags) {\n\t\tstruct e1000_hw *hw = &adapter->hw;\n\t\tu32 mrqc = E1000_READ_REG(hw, E1000_MRQC);\n\n\t\tif ((flags & UDP_RSS_FLAGS) &&\n\t\t !(adapter->flags & UDP_RSS_FLAGS))\n\t\t\tDPRINTK(DRV, WARNING,\n\t\t\t\t\"enabling UDP RSS: fragmented packets may arrive out of order to the stack above\\n\");\n\n\t\tadapter->flags = flags;\n\n\t\t/* Perform hash on these packet types */\n\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV4 |\n\t\t\tE1000_MRQC_RSS_FIELD_IPV4_TCP |\n\t\t\tE1000_MRQC_RSS_FIELD_IPV6 |\n\t\t\tE1000_MRQC_RSS_FIELD_IPV6_TCP;\n\n\t\tmrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |\n\t\t\t E1000_MRQC_RSS_FIELD_IPV6_UDP);\n\n\t\tif (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)\n\t\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;\n\n\t\tif (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)\n\t\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;\n\n\t\tE1000_WRITE_REG(hw, E1000_MRQC, mrqc);\n\t}\n\n\treturn 0;\n}\n\nstatic int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)\n{\n\tstruct igb_adapter *adapter = netdev_priv(dev);\n\tint ret = -EOPNOTSUPP;\n\n\tswitch (cmd->cmd) {\n\tcase ETHTOOL_SRXFH:\n\t\tret = igb_set_rss_hash_opt(adapter, cmd);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n#endif /* ETHTOOL_GRXRINGS */\n\nstatic const struct ethtool_ops igb_ethtool_ops = {\n\t.get_settings = igb_get_settings,\n\t.set_settings = igb_set_settings,\n\t.get_drvinfo = igb_get_drvinfo,\n\t.get_regs_len = igb_get_regs_len,\n\t.get_regs = igb_get_regs,\n\t.get_wol = igb_get_wol,\n\t.set_wol = igb_set_wol,\n\t.get_msglevel = igb_get_msglevel,\n\t.set_msglevel = igb_set_msglevel,\n\t.nway_reset = igb_nway_reset,\n\t.get_link = igb_get_link,\n\t.get_eeprom_len = igb_get_eeprom_len,\n\t.get_eeprom = igb_get_eeprom,\n\t.set_eeprom = igb_set_eeprom,\n\t.get_ringparam = igb_get_ringparam,\n\t.set_ringparam = igb_set_ringparam,\n\t.get_pauseparam = igb_get_pauseparam,\n\t.set_pauseparam = igb_set_pauseparam,\n\t.self_test = igb_diag_test,\n\t.get_strings = igb_get_strings,\n#ifndef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT\n#ifdef HAVE_ETHTOOL_SET_PHYS_ID\n\t.set_phys_id = igb_set_phys_id,\n#else\n\t.phys_id = igb_phys_id,\n#endif /* HAVE_ETHTOOL_SET_PHYS_ID */\n#endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */\n#ifdef HAVE_ETHTOOL_GET_SSET_COUNT\n\t.get_sset_count = igb_get_sset_count,\n#else\n\t.get_stats_count = igb_get_stats_count,\n\t.self_test_count = igb_diag_test_count,\n#endif\n\t.get_ethtool_stats = igb_get_ethtool_stats,\n#ifdef HAVE_ETHTOOL_GET_PERM_ADDR\n\t.get_perm_addr = ethtool_op_get_perm_addr,\n#endif\n\t.get_coalesce = igb_get_coalesce,\n\t.set_coalesce = igb_set_coalesce,\n#ifndef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT\n#ifdef HAVE_ETHTOOL_GET_TS_INFO\n\t.get_ts_info = igb_get_ts_info,\n#endif /* HAVE_ETHTOOL_GET_TS_INFO */\n#endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */\n#ifdef CONFIG_PM_RUNTIME\n\t.begin\t\t\t= igb_ethtool_begin,\n\t.complete\t\t= igb_ethtool_complete,\n#endif /* CONFIG_PM_RUNTIME */\n#ifndef HAVE_NDO_SET_FEATURES\n\t.get_rx_csum = igb_get_rx_csum,\n\t.set_rx_csum = igb_set_rx_csum,\n\t.get_tx_csum = ethtool_op_get_tx_csum,\n\t.set_tx_csum = igb_set_tx_csum,\n\t.get_sg = ethtool_op_get_sg,\n\t.set_sg = ethtool_op_set_sg,\n#ifdef NETIF_F_TSO\n\t.get_tso = ethtool_op_get_tso,\n\t.set_tso = igb_set_tso,\n#endif\n#ifdef ETHTOOL_GFLAGS\n\t.get_flags = ethtool_op_get_flags,\n\t.set_flags = igb_set_flags,\n#endif /* ETHTOOL_GFLAGS */\n#endif /* HAVE_NDO_SET_FEATURES */\n#ifdef ETHTOOL_GADV_COAL\n\t.get_advcoal\t\t= igb_get_adv_coal,\n\t.set_advcoal\t\t= igb_set_dmac_coal,\n#endif /* ETHTOOL_GADV_COAL */\n#ifndef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT\n#ifdef ETHTOOL_GEEE\n\t.get_eee\t\t= igb_get_eee,\n#endif\n#ifdef ETHTOOL_SEEE\n\t.set_eee\t\t= igb_set_eee,\n#endif\n#endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */\n#ifdef ETHTOOL_GRXRINGS\n\t.get_rxnfc\t\t= igb_get_rxnfc,\n\t.set_rxnfc\t\t= igb_set_rxnfc,\n#endif\n};\n\n#ifdef HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT\nstatic const struct ethtool_ops_ext igb_ethtool_ops_ext = {\n\t.size\t\t= sizeof(struct ethtool_ops_ext),\n\t.get_ts_info\t= igb_get_ts_info,\n\t.set_phys_id\t= igb_set_phys_id,\n\t.get_eee\t= igb_get_eee,\n\t.set_eee\t= igb_set_eee,\n};\n\nvoid igb_set_ethtool_ops(struct net_device *netdev)\n{\n\tSET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);\n\tset_ethtool_ops_ext(netdev, &igb_ethtool_ops_ext);\n}\n#else\nvoid igb_set_ethtool_ops(struct net_device *netdev)\n{\n\t/* have to \"undeclare\" const on this struct to remove warnings */\n\tSET_ETHTOOL_OPS(netdev, (struct ethtool_ops *)&igb_ethtool_ops);\n}\n#endif /* HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT */\n#endif\t/* SIOCETHTOOL */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/igb_hwmon.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"igb.h\"\n#include \"e1000_82575.h\"\n#include \"e1000_hw.h\"\n#ifdef IGB_HWMON\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#ifdef HAVE_I2C_SUPPORT\nstatic struct i2c_board_info i350_sensor_info = {\n\tI2C_BOARD_INFO(\"i350bb\", (0Xf8 >> 1)),\n};\n#endif /* HAVE_I2C_SUPPORT */\n\n/* hwmon callback functions */\nstatic ssize_t igb_hwmon_show_location(struct device *dev,\n\t\t\t\t\t struct device_attribute *attr,\n\t\t\t\t\t char *buf)\n{\n\tstruct hwmon_attr *igb_attr = container_of(attr, struct hwmon_attr,\n\t\t\t\t\t\t dev_attr);\n\treturn sprintf(buf, \"loc%u\\n\",\n\t\t igb_attr->sensor->location);\n}\n\nstatic ssize_t igb_hwmon_show_temp(struct device *dev,\n\t\t\t\t struct device_attribute *attr,\n\t\t\t\t char *buf)\n{\n\tstruct hwmon_attr *igb_attr = container_of(attr, struct hwmon_attr,\n\t\t\t\t\t\t dev_attr);\n\tunsigned int value;\n\n\t/* reset the temp field */\n\tigb_attr->hw->mac.ops.get_thermal_sensor_data(igb_attr->hw);\n\n\tvalue = igb_attr->sensor->temp;\n\n\t/* display millidegree */\n\tvalue *= 1000;\n\n\treturn sprintf(buf, \"%u\\n\", value);\n}\n\nstatic ssize_t igb_hwmon_show_cautionthresh(struct device *dev,\n\t\t\t\t struct device_attribute *attr,\n\t\t\t\t char *buf)\n{\n\tstruct hwmon_attr *igb_attr = container_of(attr, struct hwmon_attr,\n\t\t\t\t\t\t dev_attr);\n\tunsigned int value = igb_attr->sensor->caution_thresh;\n\n\t/* display millidegree */\n\tvalue *= 1000;\n\n\treturn sprintf(buf, \"%u\\n\", value);\n}\n\nstatic ssize_t igb_hwmon_show_maxopthresh(struct device *dev,\n\t\t\t\t struct device_attribute *attr,\n\t\t\t\t char *buf)\n{\n\tstruct hwmon_attr *igb_attr = container_of(attr, struct hwmon_attr,\n\t\t\t\t\t\t dev_attr);\n\tunsigned int value = igb_attr->sensor->max_op_thresh;\n\n\t/* display millidegree */\n\tvalue *= 1000;\n\n\treturn sprintf(buf, \"%u\\n\", value);\n}\n\n/* igb_add_hwmon_attr - Create hwmon attr table for a hwmon sysfs file.\n * @ adapter: pointer to the adapter structure\n * @ offset: offset in the eeprom sensor data table\n * @ type: type of sensor data to display\n *\n * For each file we want in hwmon's sysfs interface we need a device_attribute\n * This is included in our hwmon_attr struct that contains the references to\n * the data structures we need to get the data to display.\n */\nstatic int igb_add_hwmon_attr(struct igb_adapter *adapter,\n\t\t\t\tunsigned int offset, int type) {\n\tint rc;\n\tunsigned int n_attr;\n\tstruct hwmon_attr *igb_attr;\n\n\tn_attr = adapter->igb_hwmon_buff.n_hwmon;\n\tigb_attr = &adapter->igb_hwmon_buff.hwmon_list[n_attr];\n\n\tswitch (type) {\n\tcase IGB_HWMON_TYPE_LOC:\n\t\tigb_attr->dev_attr.show = igb_hwmon_show_location;\n\t\tsnprintf(igb_attr->name, sizeof(igb_attr->name),\n\t\t\t \"temp%u_label\", offset);\n\t\tbreak;\n\tcase IGB_HWMON_TYPE_TEMP:\n\t\tigb_attr->dev_attr.show = igb_hwmon_show_temp;\n\t\tsnprintf(igb_attr->name, sizeof(igb_attr->name),\n\t\t\t \"temp%u_input\", offset);\n\t\tbreak;\n\tcase IGB_HWMON_TYPE_CAUTION:\n\t\tigb_attr->dev_attr.show = igb_hwmon_show_cautionthresh;\n\t\tsnprintf(igb_attr->name, sizeof(igb_attr->name),\n\t\t\t \"temp%u_max\", offset);\n\t\tbreak;\n\tcase IGB_HWMON_TYPE_MAX:\n\t\tigb_attr->dev_attr.show = igb_hwmon_show_maxopthresh;\n\t\tsnprintf(igb_attr->name, sizeof(igb_attr->name),\n\t\t\t \"temp%u_crit\", offset);\n\t\tbreak;\n\tdefault:\n\t\trc = -EPERM;\n\t\treturn rc;\n\t}\n\n\t/* These always the same regardless of type */\n\tigb_attr->sensor =\n\t\t&adapter->hw.mac.thermal_sensor_data.sensor[offset];\n\tigb_attr->hw = &adapter->hw;\n\tigb_attr->dev_attr.store = NULL;\n\tigb_attr->dev_attr.attr.mode = S_IRUGO;\n\tigb_attr->dev_attr.attr.name = igb_attr->name;\n\tsysfs_attr_init(&igb_attr->dev_attr.attr);\n\trc = device_create_file(&adapter->pdev->dev,\n\t\t\t\t&igb_attr->dev_attr);\n\tif (rc == 0)\n\t\t++adapter->igb_hwmon_buff.n_hwmon;\n\n\treturn rc;\n}\n\nstatic void igb_sysfs_del_adapter(struct igb_adapter *adapter)\n{\n\tint i;\n\n\tif (adapter == NULL)\n\t\treturn;\n\n\tfor (i = 0; i < adapter->igb_hwmon_buff.n_hwmon; i++) {\n\t\tdevice_remove_file(&adapter->pdev->dev,\n\t\t\t &adapter->igb_hwmon_buff.hwmon_list[i].dev_attr);\n\t}\n\n\tkfree(adapter->igb_hwmon_buff.hwmon_list);\n\n\tif (adapter->igb_hwmon_buff.device)\n\t\thwmon_device_unregister(adapter->igb_hwmon_buff.device);\n}\n\n/* called from igb_main.c */\nvoid igb_sysfs_exit(struct igb_adapter *adapter)\n{\n\tigb_sysfs_del_adapter(adapter);\n}\n\n/* called from igb_main.c */\nint igb_sysfs_init(struct igb_adapter *adapter)\n{\n\tstruct hwmon_buff *igb_hwmon = &adapter->igb_hwmon_buff;\n\tunsigned int i;\n\tint n_attrs;\n\tint rc = 0;\n#ifdef HAVE_I2C_SUPPORT\n\tstruct i2c_client *client = NULL;\n#endif /* HAVE_I2C_SUPPORT */\n\n\t/* If this method isn't defined we don't support thermals */\n\tif (adapter->hw.mac.ops.init_thermal_sensor_thresh == NULL)\n\t\tgoto exit;\n\n\t/* Don't create thermal hwmon interface if no sensors present */\n\trc = (adapter->hw.mac.ops.init_thermal_sensor_thresh(&adapter->hw));\n\t\tif (rc)\n\t\t\tgoto exit;\n#ifdef HAVE_I2C_SUPPORT\n\t/* init i2c_client */\n\tclient = i2c_new_device(&adapter->i2c_adap, &i350_sensor_info);\n\tif (client == NULL) {\n\t\tdev_info(&adapter->pdev->dev,\n\t\t\t\"Failed to create new i2c device..\\n\");\n\t\tgoto exit;\n\t}\n\tadapter->i2c_client = client;\n#endif /* HAVE_I2C_SUPPORT */\n\n\t/* Allocation space for max attributes\n\t * max num sensors * values (loc, temp, max, caution)\n\t */\n\tn_attrs = E1000_MAX_SENSORS * 4;\n\tigb_hwmon->hwmon_list = kcalloc(n_attrs, sizeof(struct hwmon_attr),\n\t\t\t\t\t GFP_KERNEL);\n\tif (!igb_hwmon->hwmon_list) {\n\t\trc = -ENOMEM;\n\t\tgoto err;\n\t}\n\n\tigb_hwmon->device = hwmon_device_register(&adapter->pdev->dev);\n\tif (IS_ERR(igb_hwmon->device)) {\n\t\trc = PTR_ERR(igb_hwmon->device);\n\t\tgoto err;\n\t}\n\n\tfor (i = 0; i < E1000_MAX_SENSORS; i++) {\n\n\t\t/* Only create hwmon sysfs entries for sensors that have\n\t\t * meaningful data.\n\t\t */\n\t\tif (adapter->hw.mac.thermal_sensor_data.sensor[i].location == 0)\n\t\t\tcontinue;\n\n\t\t/* Bail if any hwmon attr struct fails to initialize */\n\t\trc = igb_add_hwmon_attr(adapter, i, IGB_HWMON_TYPE_CAUTION);\n\t\trc |= igb_add_hwmon_attr(adapter, i, IGB_HWMON_TYPE_LOC);\n\t\trc |= igb_add_hwmon_attr(adapter, i, IGB_HWMON_TYPE_TEMP);\n\t\trc |= igb_add_hwmon_attr(adapter, i, IGB_HWMON_TYPE_MAX);\n\t\tif (rc)\n\t\t\tgoto err;\n\t}\n\n\tgoto exit;\n\nerr:\n\tigb_sysfs_del_adapter(adapter);\nexit:\n\treturn rc;\n}\n#endif /* IGB_HWMON */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/igb_main.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#ifdef NETIF_F_TSO\n#include \n#ifdef NETIF_F_TSO6\n#include \n#include \n#endif\n#endif\n#ifdef SIOCGMIIPHY\n#include \n#endif\n#ifdef SIOCETHTOOL\n#include \n#endif\n#include \n#ifdef CONFIG_PM_RUNTIME\n#include \n#endif /* CONFIG_PM_RUNTIME */\n\n#include \n#include \"igb.h\"\n#include \"igb_vmdq.h\"\n\n#include \n\n#if defined(DEBUG) || defined (DEBUG_DUMP) || defined (DEBUG_ICR) || defined(DEBUG_ITR)\n#define DRV_DEBUG \"_debug\"\n#else\n#define DRV_DEBUG\n#endif\n#define DRV_HW_PERF\n#define VERSION_SUFFIX\n\n#define MAJ 5\n#define MIN 0\n#define BUILD 6\n#define DRV_VERSION __stringify(MAJ) \".\" __stringify(MIN) \".\" __stringify(BUILD) VERSION_SUFFIX DRV_DEBUG DRV_HW_PERF\n\nchar igb_driver_name[] = \"igb\";\nchar igb_driver_version[] = DRV_VERSION;\nstatic const char igb_driver_string[] =\n \"Intel(R) Gigabit Ethernet Network Driver\";\nstatic const char igb_copyright[] =\n\t\t\t\t\"Copyright (c) 2007-2013 Intel Corporation.\";\n\nstatic DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES) },\n\t{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER) },\n\t/* required last entry */\n\t{0, }\n};\n\n//MODULE_DEVICE_TABLE(pci, igb_pci_tbl);\nstatic void igb_set_sriov_capability(struct igb_adapter *adapter) __attribute__((__unused__));\nvoid igb_reset(struct igb_adapter *);\nstatic int igb_setup_all_tx_resources(struct igb_adapter *);\nstatic int igb_setup_all_rx_resources(struct igb_adapter *);\nstatic void igb_free_all_tx_resources(struct igb_adapter *);\nstatic void igb_free_all_rx_resources(struct igb_adapter *);\nstatic void igb_setup_mrqc(struct igb_adapter *);\nvoid igb_update_stats(struct igb_adapter *);\nstatic int igb_probe(struct pci_dev *, const struct pci_device_id *);\nstatic void __devexit igb_remove(struct pci_dev *pdev);\nstatic int igb_sw_init(struct igb_adapter *);\nstatic int igb_open(struct net_device *);\nstatic int igb_close(struct net_device *);\nstatic void igb_configure(struct igb_adapter *);\nstatic void igb_configure_tx(struct igb_adapter *);\nstatic void igb_configure_rx(struct igb_adapter *);\nstatic void igb_clean_all_tx_rings(struct igb_adapter *);\nstatic void igb_clean_all_rx_rings(struct igb_adapter *);\nstatic void igb_clean_tx_ring(struct igb_ring *);\nstatic void igb_set_rx_mode(struct net_device *);\nstatic void igb_update_phy_info(unsigned long);\nstatic void igb_watchdog(unsigned long);\nstatic void igb_watchdog_task(struct work_struct *);\nstatic void igb_dma_err_task(struct work_struct *);\nstatic void igb_dma_err_timer(unsigned long data);\nstatic netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);\nstatic struct net_device_stats *igb_get_stats(struct net_device *);\nstatic int igb_change_mtu(struct net_device *, int);\nvoid igb_full_sync_mac_table(struct igb_adapter *adapter);\nstatic int igb_set_mac(struct net_device *, void *);\nstatic void igb_set_uta(struct igb_adapter *adapter);\nstatic irqreturn_t igb_intr(int irq, void *);\nstatic irqreturn_t igb_intr_msi(int irq, void *);\nstatic irqreturn_t igb_msix_other(int irq, void *);\nstatic irqreturn_t igb_msix_ring(int irq, void *);\n#ifdef IGB_DCA\nstatic void igb_update_dca(struct igb_q_vector *);\nstatic void igb_setup_dca(struct igb_adapter *);\n#endif /* IGB_DCA */\nstatic int igb_poll(struct napi_struct *, int);\nstatic bool igb_clean_tx_irq(struct igb_q_vector *);\nstatic bool igb_clean_rx_irq(struct igb_q_vector *, int);\nstatic int igb_ioctl(struct net_device *, struct ifreq *, int cmd);\nstatic void igb_tx_timeout(struct net_device *);\nstatic void igb_reset_task(struct work_struct *);\n#ifdef HAVE_VLAN_RX_REGISTER\nstatic void igb_vlan_mode(struct net_device *, struct vlan_group *);\n#endif\n#ifdef HAVE_VLAN_PROTOCOL\nstatic int igb_vlan_rx_add_vid(struct net_device *,\n __be16 proto, u16);\nstatic int igb_vlan_rx_kill_vid(struct net_device *,\n __be16 proto, u16);\n#elif defined HAVE_INT_NDO_VLAN_RX_ADD_VID\n#ifdef NETIF_F_HW_VLAN_CTAG_RX\nstatic int igb_vlan_rx_add_vid(struct net_device *,\n\t\t\t __always_unused __be16 proto, u16);\nstatic int igb_vlan_rx_kill_vid(struct net_device *,\n\t\t\t __always_unused __be16 proto, u16);\n#else\nstatic int igb_vlan_rx_add_vid(struct net_device *, u16);\nstatic int igb_vlan_rx_kill_vid(struct net_device *, u16);\n#endif\n#else\nstatic void igb_vlan_rx_add_vid(struct net_device *, u16);\nstatic void igb_vlan_rx_kill_vid(struct net_device *, u16);\n#endif\nstatic void igb_restore_vlan(struct igb_adapter *);\nvoid igb_rar_set(struct igb_adapter *adapter, u32 index);\nstatic void igb_ping_all_vfs(struct igb_adapter *);\nstatic void igb_msg_task(struct igb_adapter *);\nstatic void igb_vmm_control(struct igb_adapter *);\nstatic int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);\nstatic void igb_restore_vf_multicasts(struct igb_adapter *adapter);\nstatic void igb_process_mdd_event(struct igb_adapter *);\n#ifdef IFLA_VF_MAX\nstatic int igb_ndo_set_vf_mac( struct net_device *netdev, int vf, u8 *mac);\nstatic int igb_ndo_set_vf_vlan(struct net_device *netdev,\n\t\t\t\tint vf, u16 vlan, u8 qos);\n#ifdef HAVE_VF_SPOOFCHK_CONFIGURE\nstatic int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,\n\t\t\t\tbool setting);\n#endif\n#ifdef HAVE_VF_MIN_MAX_TXRATE\nstatic int igb_ndo_set_vf_bw(struct net_device *, int, int, int);\n#else /* HAVE_VF_MIN_MAX_TXRATE */\nstatic int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);\n#endif /* HAVE_VF_MIN_MAX_TXRATE */\nstatic int igb_ndo_get_vf_config(struct net_device *netdev, int vf,\n\t\t\t\t struct ifla_vf_info *ivi);\nstatic void igb_check_vf_rate_limit(struct igb_adapter *);\n#endif\nstatic int igb_vf_configure(struct igb_adapter *adapter, int vf);\n#ifdef CONFIG_PM\n#ifdef HAVE_SYSTEM_SLEEP_PM_OPS\nstatic int igb_suspend(struct device *dev);\nstatic int igb_resume(struct device *dev);\n#ifdef CONFIG_PM_RUNTIME\nstatic int igb_runtime_suspend(struct device *dev);\nstatic int igb_runtime_resume(struct device *dev);\nstatic int igb_runtime_idle(struct device *dev);\n#endif /* CONFIG_PM_RUNTIME */\nstatic const struct dev_pm_ops igb_pm_ops = {\n#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)\n .suspend = igb_suspend,\n .resume = igb_resume,\n .freeze = igb_suspend,\n .thaw = igb_resume,\n .poweroff = igb_suspend,\n .restore = igb_resume,\n#ifdef CONFIG_PM_RUNTIME\n .runtime_suspend = igb_runtime_suspend,\n .runtime_resume = igb_runtime_resume,\n .runtime_idle = igb_runtime_idle,\n#endif\n#else /* Linux >= 2.6.34 */\n\tSET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)\n#ifdef CONFIG_PM_RUNTIME\n\tSET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,\n\t\t\tigb_runtime_idle)\n#endif /* CONFIG_PM_RUNTIME */\n#endif /* Linux version */\n};\n#else\nstatic int igb_suspend(struct pci_dev *pdev, pm_message_t state);\nstatic int igb_resume(struct pci_dev *pdev);\n#endif /* HAVE_SYSTEM_SLEEP_PM_OPS */\n#endif /* CONFIG_PM */\n#ifndef USE_REBOOT_NOTIFIER\nstatic void igb_shutdown(struct pci_dev *);\n#else\nstatic int igb_notify_reboot(struct notifier_block *, unsigned long, void *);\nstatic struct notifier_block igb_notifier_reboot = {\n\t.notifier_call\t= igb_notify_reboot,\n\t.next\t\t= NULL,\n\t.priority\t= 0\n};\n#endif\n#ifdef IGB_DCA\nstatic int igb_notify_dca(struct notifier_block *, unsigned long, void *);\nstatic struct notifier_block dca_notifier = {\n\t.notifier_call\t= igb_notify_dca,\n\t.next\t\t= NULL,\n\t.priority\t= 0\n};\n#endif\n#ifdef CONFIG_NET_POLL_CONTROLLER\n/* for netdump / net console */\nstatic void igb_netpoll(struct net_device *);\n#endif\n\n#ifdef HAVE_PCI_ERS\nstatic pci_ers_result_t igb_io_error_detected(struct pci_dev *,\n\t\t pci_channel_state_t);\nstatic pci_ers_result_t igb_io_slot_reset(struct pci_dev *);\nstatic void igb_io_resume(struct pci_dev *);\n\nstatic struct pci_error_handlers igb_err_handler = {\n\t.error_detected = igb_io_error_detected,\n\t.slot_reset = igb_io_slot_reset,\n\t.resume = igb_io_resume,\n};\n#endif\n\nstatic void igb_init_fw(struct igb_adapter *adapter);\nstatic void igb_init_dmac(struct igb_adapter *adapter, u32 pba);\n\nstatic struct pci_driver igb_driver = {\n\t.name = igb_driver_name,\n\t.id_table = igb_pci_tbl,\n\t.probe = igb_probe,\n\t.remove = __devexit_p(igb_remove),\n#ifdef CONFIG_PM\n#ifdef HAVE_SYSTEM_SLEEP_PM_OPS\n\t.driver.pm = &igb_pm_ops,\n#else\n\t.suspend = igb_suspend,\n\t.resume = igb_resume,\n#endif /* HAVE_SYSTEM_SLEEP_PM_OPS */\n#endif /* CONFIG_PM */\n#ifndef USE_REBOOT_NOTIFIER\n\t.shutdown = igb_shutdown,\n#endif\n#ifdef HAVE_PCI_ERS\n\t.err_handler = &igb_err_handler\n#endif\n};\n\n//MODULE_AUTHOR(\"Intel Corporation, \");\n//MODULE_DESCRIPTION(\"Intel(R) Gigabit Ethernet Network Driver\");\n//MODULE_LICENSE(\"GPL\");\n//MODULE_VERSION(DRV_VERSION);\n\nstatic void igb_vfta_set(struct igb_adapter *adapter, u32 vid, bool add)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct e1000_host_mng_dhcp_cookie *mng_cookie = &hw->mng_cookie;\n\tu32 index = (vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;\n\tu32 mask = 1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK);\n\tu32 vfta;\n\n\t/*\n\t * if this is the management vlan the only option is to add it in so\n\t * that the management pass through will continue to work\n\t */\n\tif ((mng_cookie->status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&\n\t (vid == mng_cookie->vlan_id))\n\t\tadd = TRUE;\n\n\tvfta = adapter->shadow_vfta[index];\n\n\tif (add)\n\t\tvfta |= mask;\n\telse\n\t\tvfta &= ~mask;\n\n\te1000_write_vfta(hw, index, vfta);\n\tadapter->shadow_vfta[index] = vfta;\n}\n\nstatic int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;\n//module_param(debug, int, 0);\n//MODULE_PARM_DESC(debug, \"Debug level (0=none, ..., 16=all)\");\n\n/**\n * igb_init_module - Driver Registration Routine\n *\n * igb_init_module is the first routine called when the driver is\n * loaded. All it does is register with the PCI subsystem.\n **/\nstatic int __init igb_init_module(void)\n{\n\tint ret;\n\n\tprintk(KERN_INFO \"%s - version %s\\n\",\n\t igb_driver_string, igb_driver_version);\n\n\tprintk(KERN_INFO \"%s\\n\", igb_copyright);\n#ifdef IGB_HWMON\n/* only use IGB_PROCFS if IGB_HWMON is not defined */\n#else\n#ifdef IGB_PROCFS\n\tif (igb_procfs_topdir_init())\n\t\tprintk(KERN_INFO \"Procfs failed to initialize topdir\\n\");\n#endif /* IGB_PROCFS */\n#endif /* IGB_HWMON */\n\n#ifdef IGB_DCA\n\tdca_register_notify(&dca_notifier);\n#endif\n\tret = pci_register_driver(&igb_driver);\n#ifdef USE_REBOOT_NOTIFIER\n\tif (ret >= 0) {\n\t\tregister_reboot_notifier(&igb_notifier_reboot);\n\t}\n#endif\n\treturn ret;\n}\n\n#undef module_init\n#define module_init(x) static int x(void) __attribute__((__unused__));\nmodule_init(igb_init_module);\n\n/**\n * igb_exit_module - Driver Exit Cleanup Routine\n *\n * igb_exit_module is called just before the driver is removed\n * from memory.\n **/\nstatic void __exit igb_exit_module(void)\n{\n#ifdef IGB_DCA\n\tdca_unregister_notify(&dca_notifier);\n#endif\n#ifdef USE_REBOOT_NOTIFIER\n\tunregister_reboot_notifier(&igb_notifier_reboot);\n#endif\n\tpci_unregister_driver(&igb_driver);\n\n#ifdef IGB_HWMON\n/* only compile IGB_PROCFS if IGB_HWMON is not defined */\n#else\n#ifdef IGB_PROCFS\n\tigb_procfs_topdir_exit();\n#endif /* IGB_PROCFS */\n#endif /* IGB_HWMON */\n}\n\n#undef module_exit\n#define module_exit(x) static void x(void) __attribute__((__unused__));\nmodule_exit(igb_exit_module);\n\n#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))\n/**\n * igb_cache_ring_register - Descriptor ring to register mapping\n * @adapter: board private structure to initialize\n *\n * Once we know the feature-set enabled for the device, we'll cache\n * the register offset the descriptor ring is assigned to.\n **/\nstatic void igb_cache_ring_register(struct igb_adapter *adapter)\n{\n\tint i = 0, j = 0;\n\tu32 rbase_offset = adapter->vfs_allocated_count;\n\n\tswitch (adapter->hw.mac.type) {\n\tcase e1000_82576:\n\t\t/* The queues are allocated for virtualization such that VF 0\n\t\t * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.\n\t\t * In order to avoid collision we start at the first free queue\n\t\t * and continue consuming queues in the same sequence\n\t\t */\n\t\tif ((adapter->rss_queues > 1) && adapter->vmdq_pools) {\n\t\t\tfor (; i < adapter->rss_queues; i++)\n\t\t\t\tadapter->rx_ring[i]->reg_idx = rbase_offset +\n\t\t\t\t Q_IDX_82576(i);\n\t\t}\n\tcase e1000_82575:\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\tcase e1000_i210:\n\tcase e1000_i211:\n\tdefault:\n\t\tfor (; i < adapter->num_rx_queues; i++)\n\t\t\tadapter->rx_ring[i]->reg_idx = rbase_offset + i;\n\t\tfor (; j < adapter->num_tx_queues; j++)\n\t\t\tadapter->tx_ring[j]->reg_idx = rbase_offset + j;\n\t\tbreak;\n\t}\n}\n\nstatic void igb_configure_lli(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu16 port;\n\n\t/* LLI should only be enabled for MSI-X or MSI interrupts */\n\tif (!adapter->msix_entries && !(adapter->flags & IGB_FLAG_HAS_MSI))\n\t\treturn;\n\n\tif (adapter->lli_port) {\n\t\t/* use filter 0 for port */\n\t\tport = htons((u16)adapter->lli_port);\n\t\tE1000_WRITE_REG(hw, E1000_IMIR(0),\n\t\t\t(port | E1000_IMIR_PORT_IM_EN));\n\t\tE1000_WRITE_REG(hw, E1000_IMIREXT(0),\n\t\t\t(E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));\n\t}\n\n\tif (adapter->flags & IGB_FLAG_LLI_PUSH) {\n\t\t/* use filter 1 for push flag */\n\t\tE1000_WRITE_REG(hw, E1000_IMIR(1),\n\t\t\t(E1000_IMIR_PORT_BP | E1000_IMIR_PORT_IM_EN));\n\t\tE1000_WRITE_REG(hw, E1000_IMIREXT(1),\n\t\t\t(E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_PSH));\n\t}\n\n\tif (adapter->lli_size) {\n\t\t/* use filter 2 for size */\n\t\tE1000_WRITE_REG(hw, E1000_IMIR(2),\n\t\t\t(E1000_IMIR_PORT_BP | E1000_IMIR_PORT_IM_EN));\n\t\tE1000_WRITE_REG(hw, E1000_IMIREXT(2),\n\t\t\t(adapter->lli_size | E1000_IMIREXT_CTRL_BP));\n\t}\n\n}\n\n/**\n * igb_write_ivar - configure ivar for given MSI-X vector\n * @hw: pointer to the HW structure\n * @msix_vector: vector number we are allocating to a given ring\n * @index: row index of IVAR register to write within IVAR table\n * @offset: column offset of in IVAR, should be multiple of 8\n *\n * This function is intended to handle the writing of the IVAR register\n * for adapters 82576 and newer. The IVAR table consists of 2 columns,\n * each containing an cause allocation for an Rx and Tx ring, and a\n * variable number of rows depending on the number of queues supported.\n **/\nstatic void igb_write_ivar(struct e1000_hw *hw, int msix_vector,\n\t\t\t int index, int offset)\n{\n\tu32 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);\n\n\t/* clear any bits that are currently set */\n\tivar &= ~((u32)0xFF << offset);\n\n\t/* write vector and valid bit */\n\tivar |= (msix_vector | E1000_IVAR_VALID) << offset;\n\n\tE1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);\n}\n\n#define IGB_N0_QUEUE -1\nstatic void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)\n{\n\tstruct igb_adapter *adapter = q_vector->adapter;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint rx_queue = IGB_N0_QUEUE;\n\tint tx_queue = IGB_N0_QUEUE;\n\tu32 msixbm = 0;\n\n\tif (q_vector->rx.ring)\n\t\trx_queue = q_vector->rx.ring->reg_idx;\n\tif (q_vector->tx.ring)\n\t\ttx_queue = q_vector->tx.ring->reg_idx;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82575:\n\t\t/* The 82575 assigns vectors using a bitmask, which matches the\n\t\t bitmask for the EICR/EIMS/EIMC registers. To assign one\n\t\t or more queues to a vector, we write the appropriate bits\n\t\t into the MSIXBM register for that vector. */\n\t\tif (rx_queue > IGB_N0_QUEUE)\n\t\t\tmsixbm = E1000_EICR_RX_QUEUE0 << rx_queue;\n\t\tif (tx_queue > IGB_N0_QUEUE)\n\t\t\tmsixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;\n\t\tif (!adapter->msix_entries && msix_vector == 0)\n\t\t\tmsixbm |= E1000_EIMS_OTHER;\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), msix_vector, msixbm);\n\t\tq_vector->eims_value = msixbm;\n\t\tbreak;\n\tcase e1000_82576:\n\t\t/*\n\t\t * 82576 uses a table that essentially consists of 2 columns\n\t\t * with 8 rows. The ordering is column-major so we use the\n\t\t * lower 3 bits as the row index, and the 4th bit as the\n\t\t * column offset.\n\t\t */\n\t\tif (rx_queue > IGB_N0_QUEUE)\n\t\t\tigb_write_ivar(hw, msix_vector,\n\t\t\t\t rx_queue & 0x7,\n\t\t\t\t (rx_queue & 0x8) << 1);\n\t\tif (tx_queue > IGB_N0_QUEUE)\n\t\t\tigb_write_ivar(hw, msix_vector,\n\t\t\t\t tx_queue & 0x7,\n\t\t\t\t ((tx_queue & 0x8) << 1) + 8);\n\t\tq_vector->eims_value = 1 << msix_vector;\n\t\tbreak;\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\t/*\n\t\t * On 82580 and newer adapters the scheme is similar to 82576\n\t\t * however instead of ordering column-major we have things\n\t\t * ordered row-major. So we traverse the table by using\n\t\t * bit 0 as the column offset, and the remaining bits as the\n\t\t * row index.\n\t\t */\n\t\tif (rx_queue > IGB_N0_QUEUE)\n\t\t\tigb_write_ivar(hw, msix_vector,\n\t\t\t\t rx_queue >> 1,\n\t\t\t\t (rx_queue & 0x1) << 4);\n\t\tif (tx_queue > IGB_N0_QUEUE)\n\t\t\tigb_write_ivar(hw, msix_vector,\n\t\t\t\t tx_queue >> 1,\n\t\t\t\t ((tx_queue & 0x1) << 4) + 8);\n\t\tq_vector->eims_value = 1 << msix_vector;\n\t\tbreak;\n\tdefault:\n\t\tBUG();\n\t\tbreak;\n\t}\n\n\t/* add q_vector eims value to global eims_enable_mask */\n\tadapter->eims_enable_mask |= q_vector->eims_value;\n\n\t/* configure q_vector to set itr on first interrupt */\n\tq_vector->set_itr = 1;\n}\n\n/**\n * igb_configure_msix - Configure MSI-X hardware\n *\n * igb_configure_msix sets up the hardware to properly\n * generate MSI-X interrupts.\n **/\nstatic void igb_configure_msix(struct igb_adapter *adapter)\n{\n\tu32 tmp;\n\tint i, vector = 0;\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\tadapter->eims_enable_mask = 0;\n\n\t/* set vector for other causes, i.e. link changes */\n\tswitch (hw->mac.type) {\n\tcase e1000_82575:\n\t\ttmp = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\t/* enable MSI-X PBA support*/\n\t\ttmp |= E1000_CTRL_EXT_PBA_CLR;\n\n\t\t/* Auto-Mask interrupts upon ICR read. */\n\t\ttmp |= E1000_CTRL_EXT_EIAME;\n\t\ttmp |= E1000_CTRL_EXT_IRCA;\n\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);\n\n\t\t/* enable msix_other interrupt */\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), vector++,\n\t\t E1000_EIMS_OTHER);\n\t\tadapter->eims_other = E1000_EIMS_OTHER;\n\n\t\tbreak;\n\n\tcase e1000_82576:\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\t/* Turn on MSI-X capability first, or our settings\n\t\t * won't stick. And it will take days to debug. */\n\t\tE1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_MSIX_MODE |\n\t\t E1000_GPIE_PBA | E1000_GPIE_EIAME |\n\t\t E1000_GPIE_NSICR);\n\n\t\t/* enable msix_other interrupt */\n\t\tadapter->eims_other = 1 << vector;\n\t\ttmp = (vector++ | E1000_IVAR_VALID) << 8;\n\n\t\tE1000_WRITE_REG(hw, E1000_IVAR_MISC, tmp);\n\t\tbreak;\n\tdefault:\n\t\t/* do nothing, since nothing else supports MSI-X */\n\t\tbreak;\n\t} /* switch (hw->mac.type) */\n\n\tadapter->eims_enable_mask |= adapter->eims_other;\n\n\tfor (i = 0; i < adapter->num_q_vectors; i++)\n\t\tigb_assign_vector(adapter->q_vector[i], vector++);\n\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/**\n * igb_request_msix - Initialize MSI-X interrupts\n *\n * igb_request_msix allocates MSI-X vectors and requests interrupts from the\n * kernel.\n **/\nstatic int igb_request_msix(struct igb_adapter *adapter)\n{\n\tstruct net_device *netdev = adapter->netdev;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint i, err = 0, vector = 0, free_vector = 0;\n\n\terr = request_irq(adapter->msix_entries[vector].vector,\n\t &igb_msix_other, 0, netdev->name, adapter);\n\tif (err)\n\t\tgoto err_out;\n\n\tfor (i = 0; i < adapter->num_q_vectors; i++) {\n\t\tstruct igb_q_vector *q_vector = adapter->q_vector[i];\n\n\t\tvector++;\n\n\t\tq_vector->itr_register = hw->hw_addr + E1000_EITR(vector);\n\n\t\tif (q_vector->rx.ring && q_vector->tx.ring)\n\t\t\tsprintf(q_vector->name, \"%s-TxRx-%u\", netdev->name,\n\t\t\t q_vector->rx.ring->queue_index);\n\t\telse if (q_vector->tx.ring)\n\t\t\tsprintf(q_vector->name, \"%s-tx-%u\", netdev->name,\n\t\t\t q_vector->tx.ring->queue_index);\n\t\telse if (q_vector->rx.ring)\n\t\t\tsprintf(q_vector->name, \"%s-rx-%u\", netdev->name,\n\t\t\t q_vector->rx.ring->queue_index);\n\t\telse\n\t\t\tsprintf(q_vector->name, \"%s-unused\", netdev->name);\n\n\t\terr = request_irq(adapter->msix_entries[vector].vector,\n\t\t igb_msix_ring, 0, q_vector->name,\n\t\t q_vector);\n\t\tif (err)\n\t\t\tgoto err_free;\n\t}\n\n\tigb_configure_msix(adapter);\n\treturn 0;\n\nerr_free:\n\t/* free already assigned IRQs */\n\tfree_irq(adapter->msix_entries[free_vector++].vector, adapter);\n\n\tvector--;\n\tfor (i = 0; i < vector; i++) {\n\t\tfree_irq(adapter->msix_entries[free_vector++].vector,\n\t\t\t adapter->q_vector[i]);\n\t}\nerr_out:\n\treturn err;\n}\n\nstatic void igb_reset_interrupt_capability(struct igb_adapter *adapter)\n{\n\tif (adapter->msix_entries) {\n\t\tpci_disable_msix(adapter->pdev);\n\t\tkfree(adapter->msix_entries);\n\t\tadapter->msix_entries = NULL;\n\t} else if (adapter->flags & IGB_FLAG_HAS_MSI) {\n\t\tpci_disable_msi(adapter->pdev);\n\t}\n}\n\n/**\n * igb_free_q_vector - Free memory allocated for specific interrupt vector\n * @adapter: board private structure to initialize\n * @v_idx: Index of vector to be freed\n *\n * This function frees the memory allocated to the q_vector. In addition if\n * NAPI is enabled it will delete any references to the NAPI struct prior\n * to freeing the q_vector.\n **/\nstatic void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)\n{\n\tstruct igb_q_vector *q_vector = adapter->q_vector[v_idx];\n\n\tif (q_vector->tx.ring)\n\t\tadapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;\n\n\tif (q_vector->rx.ring)\n\t\tadapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;\n\n\tadapter->q_vector[v_idx] = NULL;\n\tnetif_napi_del(&q_vector->napi);\n#ifndef IGB_NO_LRO\n\t__skb_queue_purge(&q_vector->lrolist.active);\n#endif\n\tkfree(q_vector);\n}\n\n/**\n * igb_free_q_vectors - Free memory allocated for interrupt vectors\n * @adapter: board private structure to initialize\n *\n * This function frees the memory allocated to the q_vectors. In addition if\n * NAPI is enabled it will delete any references to the NAPI struct prior\n * to freeing the q_vector.\n **/\nstatic void igb_free_q_vectors(struct igb_adapter *adapter)\n{\n\tint v_idx = adapter->num_q_vectors;\n\n\tadapter->num_tx_queues = 0;\n\tadapter->num_rx_queues = 0;\n\tadapter->num_q_vectors = 0;\n\n\twhile (v_idx--)\n\t\tigb_free_q_vector(adapter, v_idx);\n}\n\n/**\n * igb_clear_interrupt_scheme - reset the device to a state of no interrupts\n *\n * This function resets the device so that it has 0 rx queues, tx queues, and\n * MSI-X interrupts allocated.\n */\nstatic void igb_clear_interrupt_scheme(struct igb_adapter *adapter)\n{\n\tigb_free_q_vectors(adapter);\n\tigb_reset_interrupt_capability(adapter);\n}\n\n/**\n * igb_process_mdd_event\n * @adapter - board private structure\n *\n * Identify a malicious VF, disable the VF TX/RX queues and log a message.\n */\nstatic void igb_process_mdd_event(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 lvmmc, vfte, vfre, mdfb;\n\tu8 vf_queue;\n\n\tlvmmc = E1000_READ_REG(hw, E1000_LVMMC);\n\tvf_queue = lvmmc >> 29;\n\n\t/* VF index cannot be bigger or equal to VFs allocated */\n\tif (vf_queue >= adapter->vfs_allocated_count)\n\t\treturn;\n\n\tnetdev_info(adapter->netdev,\n\t \"VF %d misbehaved. VF queues are disabled. \"\n\t \"VM misbehavior code is 0x%x\\n\", vf_queue, lvmmc);\n\n\t/* Disable VFTE and VFRE related bits */\n\tvfte = E1000_READ_REG(hw, E1000_VFTE);\n\tvfte &= ~(1 << vf_queue);\n\tE1000_WRITE_REG(hw, E1000_VFTE, vfte);\n\n\tvfre = E1000_READ_REG(hw, E1000_VFRE);\n\tvfre &= ~(1 << vf_queue);\n\tE1000_WRITE_REG(hw, E1000_VFRE, vfre);\n\n\t/* Disable MDFB related bit. Clear on write */\n\tmdfb = E1000_READ_REG(hw, E1000_MDFB);\n\tmdfb |= (1 << vf_queue);\n\tE1000_WRITE_REG(hw, E1000_MDFB, mdfb);\n\n\t/* Reset the specific VF */\n\tE1000_WRITE_REG(hw, E1000_VTCTRL(vf_queue), E1000_VTCTRL_RST);\n}\n\n/**\n * igb_disable_mdd\n * @adapter - board private structure\n *\n * Disable MDD behavior in the HW\n **/\nstatic void igb_disable_mdd(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 reg;\n\n\tif ((hw->mac.type != e1000_i350) ||\n\t (hw->mac.type != e1000_i354))\n\t\treturn;\n\n\treg = E1000_READ_REG(hw, E1000_DTXCTL);\n\treg &= (~E1000_DTXCTL_MDP_EN);\n\tE1000_WRITE_REG(hw, E1000_DTXCTL, reg);\n}\n\n/**\n * igb_enable_mdd\n * @adapter - board private structure\n *\n * Enable the HW to detect malicious driver and sends an interrupt to\n * the driver.\n **/\nstatic void igb_enable_mdd(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 reg;\n\n\t/* Only available on i350 device */\n\tif (hw->mac.type != e1000_i350)\n\t\treturn;\n\n\treg = E1000_READ_REG(hw, E1000_DTXCTL);\n\treg |= E1000_DTXCTL_MDP_EN;\n\tE1000_WRITE_REG(hw, E1000_DTXCTL, reg);\n}\n\n/**\n * igb_reset_sriov_capability - disable SR-IOV if enabled\n *\n * Attempt to disable single root IO virtualization capabilites present in the\n * kernel.\n **/\nstatic void igb_reset_sriov_capability(struct igb_adapter *adapter)\n{\n\tstruct pci_dev *pdev = adapter->pdev;\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\t/* reclaim resources allocated to VFs */\n\tif (adapter->vf_data) {\n\t\tif (!pci_vfs_assigned(pdev)) {\n\t\t\t/*\n\t\t\t * disable iov and allow time for transactions to\n\t\t\t * clear\n\t\t\t */\n\t\t\tpci_disable_sriov(pdev);\n\t\t\tmsleep(500);\n\n\t\t\tdev_info(pci_dev_to_dev(pdev), \"IOV Disabled\\n\");\n\t\t} else {\n\t\t\tdev_info(pci_dev_to_dev(pdev), \"IOV Not Disabled\\n \"\n\t\t\t\t\t\"VF(s) are assigned to guests!\\n\");\n\t\t}\n\t\t/* Disable Malicious Driver Detection */\n\t\tigb_disable_mdd(adapter);\n\n\t\t/* free vf data storage */\n\t\tkfree(adapter->vf_data);\n\t\tadapter->vf_data = NULL;\n\n\t\t/* switch rings back to PF ownership */\n\t\tE1000_WRITE_REG(hw, E1000_IOVCTL,\n\t\t\t\tE1000_IOVCTL_REUSE_VFQ);\n\t\tE1000_WRITE_FLUSH(hw);\n\t\tmsleep(100);\n\t}\n\n\tadapter->vfs_allocated_count = 0;\n}\n\n/**\n * igb_set_sriov_capability - setup SR-IOV if supported\n *\n * Attempt to enable single root IO virtualization capabilites present in the\n * kernel.\n **/\nstatic void igb_set_sriov_capability(struct igb_adapter *adapter)\n{\n\tstruct pci_dev *pdev = adapter->pdev;\n\tint old_vfs = 0;\n\tint i;\n\n\told_vfs = pci_num_vf(pdev);\n\tif (old_vfs) {\n\t\tdev_info(pci_dev_to_dev(pdev),\n\t\t\t\t\"%d pre-allocated VFs found - override \"\n\t\t\t\t\"max_vfs setting of %d\\n\", old_vfs,\n\t\t\t\tadapter->vfs_allocated_count);\n\t\tadapter->vfs_allocated_count = old_vfs;\n\t}\n\t/* no VFs requested, do nothing */\n\tif (!adapter->vfs_allocated_count)\n\t\treturn;\n\n\t/* allocate vf data storage */\n\tadapter->vf_data = kcalloc(adapter->vfs_allocated_count,\n\t sizeof(struct vf_data_storage),\n\t GFP_KERNEL);\n\n\tif (adapter->vf_data) {\n\t\tif (!old_vfs) {\n\t\t\tif (pci_enable_sriov(pdev,\n\t\t\t\t\tadapter->vfs_allocated_count))\n\t\t\t\tgoto err_out;\n\t\t}\n\t\tfor (i = 0; i < adapter->vfs_allocated_count; i++)\n\t\t\tigb_vf_configure(adapter, i);\n\n\t\tswitch (adapter->hw.mac.type) {\n\t\tcase e1000_82576:\n\t\tcase e1000_i350:\n\t\t\t/* Enable VM to VM loopback by default */\n\t\t\tadapter->flags |= IGB_FLAG_LOOPBACK_ENABLE;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* Currently no other hardware supports loopback */\n\t\t\tbreak;\n\t\t}\n\n\t\t/* DMA Coalescing is not supported in IOV mode. */\n\t\tif (adapter->hw.mac.type >= e1000_i350)\n\t\tadapter->dmac = IGB_DMAC_DISABLE;\n\t\tif (adapter->hw.mac.type < e1000_i350)\n\t\tadapter->flags |= IGB_FLAG_DETECT_BAD_DMA;\n\t\treturn;\n\n\t}\n\nerr_out:\n\tkfree(adapter->vf_data);\n\tadapter->vf_data = NULL;\n\tadapter->vfs_allocated_count = 0;\n\tdev_warn(pci_dev_to_dev(pdev),\n\t\t\t\"Failed to initialize SR-IOV virtualization\\n\");\n}\n\n/**\n * igb_set_interrupt_capability - set MSI or MSI-X if supported\n *\n * Attempt to configure interrupts using the best available\n * capabilities of the hardware and kernel.\n **/\nstatic void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)\n{\n\tstruct pci_dev *pdev = adapter->pdev;\n\tint err;\n\tint numvecs, i;\n\n\tif (!msix)\n\t\tadapter->int_mode = IGB_INT_MODE_MSI;\n\n\t/* Number of supported queues. */\n\tadapter->num_rx_queues = adapter->rss_queues;\n\n\tif (adapter->vmdq_pools > 1)\n\t\tadapter->num_rx_queues += adapter->vmdq_pools - 1;\n\n#ifdef HAVE_TX_MQ\n\tif (adapter->vmdq_pools)\n\t\tadapter->num_tx_queues = adapter->vmdq_pools;\n\telse\n\t\tadapter->num_tx_queues = adapter->num_rx_queues;\n#else\n\tadapter->num_tx_queues = max_t(u32, 1, adapter->vmdq_pools);\n#endif\n\n\tswitch (adapter->int_mode) {\n\tcase IGB_INT_MODE_MSIX:\n\t\t/* start with one vector for every rx queue */\n\t\tnumvecs = adapter->num_rx_queues;\n\n\t\t/* if tx handler is separate add 1 for every tx queue */\n\t\tif (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))\n\t\t\tnumvecs += adapter->num_tx_queues;\n\n\t\t/* store the number of vectors reserved for queues */\n\t\tadapter->num_q_vectors = numvecs;\n\n\t\t/* add 1 vector for link status interrupts */\n\t\tnumvecs++;\n\t\tadapter->msix_entries = kcalloc(numvecs,\n\t\t sizeof(struct msix_entry),\n\t\t GFP_KERNEL);\n\t\tif (adapter->msix_entries) {\n\t\t\tfor (i = 0; i < numvecs; i++)\n\t\t\t\tadapter->msix_entries[i].entry = i;\n\n\t\t\terr = pci_enable_msix(pdev,\n\t\t\t adapter->msix_entries, numvecs);\n\t\t\tif (err == 0)\n\t\t\t\tbreak;\n\t\t}\n\t\t/* MSI-X failed, so fall through and try MSI */\n\t\tdev_warn(pci_dev_to_dev(pdev), \"Failed to initialize MSI-X interrupts. \"\n\t\t \"Falling back to MSI interrupts.\\n\");\n\t\tigb_reset_interrupt_capability(adapter);\n\tcase IGB_INT_MODE_MSI:\n\t\tif (!pci_enable_msi(pdev))\n\t\t\tadapter->flags |= IGB_FLAG_HAS_MSI;\n\t\telse\n\t\t\tdev_warn(pci_dev_to_dev(pdev), \"Failed to initialize MSI \"\n\t\t\t \"interrupts. Falling back to legacy \"\n\t\t\t \"interrupts.\\n\");\n\t\t/* Fall through */\n\tcase IGB_INT_MODE_LEGACY:\n\t\t/* disable advanced features and set number of queues to 1 */\n\t\tigb_reset_sriov_capability(adapter);\n\t\tadapter->vmdq_pools = 0;\n\t\tadapter->rss_queues = 1;\n\t\tadapter->flags |= IGB_FLAG_QUEUE_PAIRS;\n\t\tadapter->num_rx_queues = 1;\n\t\tadapter->num_tx_queues = 1;\n\t\tadapter->num_q_vectors = 1;\n\t\t/* Don't do anything; this is system default */\n\t\tbreak;\n\t}\n}\n\nstatic void igb_add_ring(struct igb_ring *ring,\n\t\t\t struct igb_ring_container *head)\n{\n\thead->ring = ring;\n\thead->count++;\n}\n\n/**\n * igb_alloc_q_vector - Allocate memory for a single interrupt vector\n * @adapter: board private structure to initialize\n * @v_count: q_vectors allocated on adapter, used for ring interleaving\n * @v_idx: index of vector in adapter struct\n * @txr_count: total number of Tx rings to allocate\n * @txr_idx: index of first Tx ring to allocate\n * @rxr_count: total number of Rx rings to allocate\n * @rxr_idx: index of first Rx ring to allocate\n *\n * We allocate one q_vector. If allocation fails we return -ENOMEM.\n **/\nstatic int igb_alloc_q_vector(struct igb_adapter *adapter,\n\t\t\t unsigned int v_count, unsigned int v_idx,\n\t\t\t unsigned int txr_count, unsigned int txr_idx,\n\t\t\t unsigned int rxr_count, unsigned int rxr_idx)\n{\n\tstruct igb_q_vector *q_vector;\n\tstruct igb_ring *ring;\n\tint ring_count, size;\n\n\t/* igb only supports 1 Tx and/or 1 Rx queue per vector */\n\tif (txr_count > 1 || rxr_count > 1)\n\t\treturn -ENOMEM;\n\n\tring_count = txr_count + rxr_count;\n\tsize = sizeof(struct igb_q_vector) +\n\t (sizeof(struct igb_ring) * ring_count);\n\n\t/* allocate q_vector and rings */\n\tq_vector = kzalloc(size, GFP_KERNEL);\n\tif (!q_vector)\n\t\treturn -ENOMEM;\n\n#ifndef IGB_NO_LRO\n\t/* initialize LRO */\n\t__skb_queue_head_init(&q_vector->lrolist.active);\n\n#endif\n\t/* initialize NAPI */\n\tnetif_napi_add(adapter->netdev, &q_vector->napi,\n\t\t igb_poll, 64);\n\n\t/* tie q_vector and adapter together */\n\tadapter->q_vector[v_idx] = q_vector;\n\tq_vector->adapter = adapter;\n\n\t/* initialize work limits */\n\tq_vector->tx.work_limit = adapter->tx_work_limit;\n\n\t/* initialize ITR configuration */\n\tq_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);\n\tq_vector->itr_val = IGB_START_ITR;\n\n\t/* initialize pointer to rings */\n\tring = q_vector->ring;\n\n\t/* intialize ITR */\n\tif (rxr_count) {\n\t\t/* rx or rx/tx vector */\n\t\tif (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)\n\t\t\tq_vector->itr_val = adapter->rx_itr_setting;\n\t} else {\n\t\t/* tx only vector */\n\t\tif (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)\n\t\t\tq_vector->itr_val = adapter->tx_itr_setting;\n\t}\n\n\tif (txr_count) {\n\t\t/* assign generic ring traits */\n\t\tring->dev = &adapter->pdev->dev;\n\t\tring->netdev = adapter->netdev;\n\n\t\t/* configure backlink on ring */\n\t\tring->q_vector = q_vector;\n\n\t\t/* update q_vector Tx values */\n\t\tigb_add_ring(ring, &q_vector->tx);\n\n\t\t/* For 82575, context index must be unique per ring. */\n\t\tif (adapter->hw.mac.type == e1000_82575)\n\t\t\tset_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);\n\n\t\t/* apply Tx specific ring traits */\n\t\tring->count = adapter->tx_ring_count;\n\t\tring->queue_index = txr_idx;\n\n\t\t/* assign ring to adapter */\n\t\tadapter->tx_ring[txr_idx] = ring;\n\n\t\t/* push pointer to next ring */\n\t\tring++;\n\t}\n\n\tif (rxr_count) {\n\t\t/* assign generic ring traits */\n\t\tring->dev = &adapter->pdev->dev;\n\t\tring->netdev = adapter->netdev;\n\n\t\t/* configure backlink on ring */\n\t\tring->q_vector = q_vector;\n\n\t\t/* update q_vector Rx values */\n\t\tigb_add_ring(ring, &q_vector->rx);\n\n#ifndef HAVE_NDO_SET_FEATURES\n\t\t/* enable rx checksum */\n\t\tset_bit(IGB_RING_FLAG_RX_CSUM, &ring->flags);\n\n#endif\n\t\t/* set flag indicating ring supports SCTP checksum offload */\n\t\tif (adapter->hw.mac.type >= e1000_82576)\n\t\t\tset_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);\n\n\t\tif ((adapter->hw.mac.type == e1000_i350) ||\n\t\t (adapter->hw.mac.type == e1000_i354))\n\t\t\tset_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);\n\n\t\t/* apply Rx specific ring traits */\n\t\tring->count = adapter->rx_ring_count;\n\t\tring->queue_index = rxr_idx;\n\n\t\t/* assign ring to adapter */\n\t\tadapter->rx_ring[rxr_idx] = ring;\n\t}\n\n\treturn 0;\n}\n\n/**\n * igb_alloc_q_vectors - Allocate memory for interrupt vectors\n * @adapter: board private structure to initialize\n *\n * We allocate one q_vector per queue interrupt. If allocation fails we\n * return -ENOMEM.\n **/\nstatic int igb_alloc_q_vectors(struct igb_adapter *adapter)\n{\n\tint q_vectors = adapter->num_q_vectors;\n\tint rxr_remaining = adapter->num_rx_queues;\n\tint txr_remaining = adapter->num_tx_queues;\n\tint rxr_idx = 0, txr_idx = 0, v_idx = 0;\n\tint err;\n\n\tif (q_vectors >= (rxr_remaining + txr_remaining)) {\n\t\tfor (; rxr_remaining; v_idx++) {\n\t\t\terr = igb_alloc_q_vector(adapter, q_vectors, v_idx,\n\t\t\t\t\t\t 0, 0, 1, rxr_idx);\n\n\t\t\tif (err)\n\t\t\t\tgoto err_out;\n\n\t\t\t/* update counts and index */\n\t\t\trxr_remaining--;\n\t\t\trxr_idx++;\n\t\t}\n\t}\n\n\tfor (; v_idx < q_vectors; v_idx++) {\n\t\tint rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);\n\t\tint tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);\n\t\terr = igb_alloc_q_vector(adapter, q_vectors, v_idx,\n\t\t\t\t\t tqpv, txr_idx, rqpv, rxr_idx);\n\n\t\tif (err)\n\t\t\tgoto err_out;\n\n\t\t/* update counts and index */\n\t\trxr_remaining -= rqpv;\n\t\ttxr_remaining -= tqpv;\n\t\trxr_idx++;\n\t\ttxr_idx++;\n\t}\n\n\treturn 0;\n\nerr_out:\n\tadapter->num_tx_queues = 0;\n\tadapter->num_rx_queues = 0;\n\tadapter->num_q_vectors = 0;\n\n\twhile (v_idx--)\n\t\tigb_free_q_vector(adapter, v_idx);\n\n\treturn -ENOMEM;\n}\n\n/**\n * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors\n *\n * This function initializes the interrupts and allocates all of the queues.\n **/\nstatic int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)\n{\n\tstruct pci_dev *pdev = adapter->pdev;\n\tint err;\n\n\tigb_set_interrupt_capability(adapter, msix);\n\n\terr = igb_alloc_q_vectors(adapter);\n\tif (err) {\n\t\tdev_err(pci_dev_to_dev(pdev), \"Unable to allocate memory for vectors\\n\");\n\t\tgoto err_alloc_q_vectors;\n\t}\n\n\tigb_cache_ring_register(adapter);\n\n\treturn 0;\n\nerr_alloc_q_vectors:\n\tigb_reset_interrupt_capability(adapter);\n\treturn err;\n}\n\n/**\n * igb_request_irq - initialize interrupts\n *\n * Attempts to configure interrupts using the best available\n * capabilities of the hardware and kernel.\n **/\nstatic int igb_request_irq(struct igb_adapter *adapter)\n{\n\tstruct net_device *netdev = adapter->netdev;\n\tstruct pci_dev *pdev = adapter->pdev;\n\tint err = 0;\n\n\tif (adapter->msix_entries) {\n\t\terr = igb_request_msix(adapter);\n\t\tif (!err)\n\t\t\tgoto request_done;\n\t\t/* fall back to MSI */\n\t\tigb_free_all_tx_resources(adapter);\n\t\tigb_free_all_rx_resources(adapter);\n\n\t\tigb_clear_interrupt_scheme(adapter);\n\t\tigb_reset_sriov_capability(adapter);\n\t\terr = igb_init_interrupt_scheme(adapter, false);\n\t\tif (err)\n\t\t\tgoto request_done;\n\t\tigb_setup_all_tx_resources(adapter);\n\t\tigb_setup_all_rx_resources(adapter);\n\t\tigb_configure(adapter);\n\t}\n\n\tigb_assign_vector(adapter->q_vector[0], 0);\n\n\tif (adapter->flags & IGB_FLAG_HAS_MSI) {\n\t\terr = request_irq(pdev->irq, &igb_intr_msi, 0,\n\t\t\t\t netdev->name, adapter);\n\t\tif (!err)\n\t\t\tgoto request_done;\n\n\t\t/* fall back to legacy interrupts */\n\t\tigb_reset_interrupt_capability(adapter);\n\t\tadapter->flags &= ~IGB_FLAG_HAS_MSI;\n\t}\n\n\terr = request_irq(pdev->irq, &igb_intr, IRQF_SHARED,\n\t\t\t netdev->name, adapter);\n\n\tif (err)\n\t\tdev_err(pci_dev_to_dev(pdev), \"Error %d getting interrupt\\n\",\n\t\t\terr);\n\nrequest_done:\n\treturn err;\n}\n\nstatic void igb_free_irq(struct igb_adapter *adapter)\n{\n\tif (adapter->msix_entries) {\n\t\tint vector = 0, i;\n\n\t\tfree_irq(adapter->msix_entries[vector++].vector, adapter);\n\n\t\tfor (i = 0; i < adapter->num_q_vectors; i++)\n\t\t\tfree_irq(adapter->msix_entries[vector++].vector,\n\t\t\t adapter->q_vector[i]);\n\t} else {\n\t\tfree_irq(adapter->pdev->irq, adapter);\n\t}\n}\n\n/**\n * igb_irq_disable - Mask off interrupt generation on the NIC\n * @adapter: board private structure\n **/\nstatic void igb_irq_disable(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\t/*\n\t * we need to be careful when disabling interrupts. The VFs are also\n\t * mapped into these registers and so clearing the bits can cause\n\t * issues on the VF drivers so we only need to clear what we set\n\t */\n\tif (adapter->msix_entries) {\n\t\tu32 regval = E1000_READ_REG(hw, E1000_EIAM);\n\t\tE1000_WRITE_REG(hw, E1000_EIAM, regval & ~adapter->eims_enable_mask);\n\t\tE1000_WRITE_REG(hw, E1000_EIMC, adapter->eims_enable_mask);\n\t\tregval = E1000_READ_REG(hw, E1000_EIAC);\n\t\tE1000_WRITE_REG(hw, E1000_EIAC, regval & ~adapter->eims_enable_mask);\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_IAM, 0);\n\tE1000_WRITE_REG(hw, E1000_IMC, ~0);\n\tE1000_WRITE_FLUSH(hw);\n\n\tif (adapter->msix_entries) {\n\t\tint vector = 0, i;\n\n\t\tsynchronize_irq(adapter->msix_entries[vector++].vector);\n\n\t\tfor (i = 0; i < adapter->num_q_vectors; i++)\n\t\t\tsynchronize_irq(adapter->msix_entries[vector++].vector);\n\t} else {\n\t\tsynchronize_irq(adapter->pdev->irq);\n\t}\n}\n\n/**\n * igb_irq_enable - Enable default interrupt generation settings\n * @adapter: board private structure\n **/\nstatic void igb_irq_enable(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\tif (adapter->msix_entries) {\n\t\tu32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;\n\t\tu32 regval = E1000_READ_REG(hw, E1000_EIAC);\n\t\tE1000_WRITE_REG(hw, E1000_EIAC, regval | adapter->eims_enable_mask);\n\t\tregval = E1000_READ_REG(hw, E1000_EIAM);\n\t\tE1000_WRITE_REG(hw, E1000_EIAM, regval | adapter->eims_enable_mask);\n\t\tE1000_WRITE_REG(hw, E1000_EIMS, adapter->eims_enable_mask);\n\t\tif (adapter->vfs_allocated_count) {\n\t\t\tE1000_WRITE_REG(hw, E1000_MBVFIMR, 0xFF);\n\t\t\tims |= E1000_IMS_VMMB;\n\t\t\tif (adapter->mdd)\n\t\t\t\tif ((adapter->hw.mac.type == e1000_i350) ||\n\t\t\t\t (adapter->hw.mac.type == e1000_i354))\n\t\t\t\tims |= E1000_IMS_MDDET;\n\t\t}\n\t\tE1000_WRITE_REG(hw, E1000_IMS, ims);\n\t} else {\n\t\tE1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK |\n\t\t\t\tE1000_IMS_DRSTA);\n\t\tE1000_WRITE_REG(hw, E1000_IAM, IMS_ENABLE_MASK |\n\t\t\t\tE1000_IMS_DRSTA);\n\t}\n}\n\nstatic void igb_update_mng_vlan(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu16 vid = adapter->hw.mng_cookie.vlan_id;\n\tu16 old_vid = adapter->mng_vlan_id;\n\n\tif (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {\n\t\t/* add VID to filter table */\n\t\tigb_vfta_set(adapter, vid, TRUE);\n\t\tadapter->mng_vlan_id = vid;\n\t} else {\n\t\tadapter->mng_vlan_id = IGB_MNG_VLAN_NONE;\n\t}\n\n\tif ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&\n\t (vid != old_vid) &&\n#ifdef HAVE_VLAN_RX_REGISTER\n\t !vlan_group_get_device(adapter->vlgrp, old_vid)) {\n#else\n\t !test_bit(old_vid, adapter->active_vlans)) {\n#endif\n\t\t/* remove VID from filter table */\n\t\tigb_vfta_set(adapter, old_vid, FALSE);\n\t}\n}\n\n/**\n * igb_release_hw_control - release control of the h/w to f/w\n * @adapter: address of board private structure\n *\n * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.\n * For ASF and Pass Through versions of f/w this means that the\n * driver is no longer loaded.\n *\n **/\nstatic void igb_release_hw_control(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 ctrl_ext;\n\n\t/* Let firmware take over control of h/w */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT,\n\t\t\tctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);\n}\n\n/**\n * igb_get_hw_control - get control of the h/w from f/w\n * @adapter: address of board private structure\n *\n * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.\n * For ASF and Pass Through versions of f/w this means that\n * the driver is loaded.\n *\n **/\nstatic void igb_get_hw_control(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 ctrl_ext;\n\n\t/* Let firmware know the driver has taken over */\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tE1000_WRITE_REG(hw, E1000_CTRL_EXT,\n\t\t\tctrl_ext | E1000_CTRL_EXT_DRV_LOAD);\n}\n\n/**\n * igb_configure - configure the hardware for RX and TX\n * @adapter: private board structure\n **/\nstatic void igb_configure(struct igb_adapter *adapter)\n{\n\tstruct net_device *netdev = adapter->netdev;\n\tint i;\n\n\tigb_get_hw_control(adapter);\n\tigb_set_rx_mode(netdev);\n\n\tigb_restore_vlan(adapter);\n\n\tigb_setup_tctl(adapter);\n\tigb_setup_mrqc(adapter);\n\tigb_setup_rctl(adapter);\n\n\tigb_configure_tx(adapter);\n\tigb_configure_rx(adapter);\n\n\te1000_rx_fifo_flush_82575(&adapter->hw);\n#ifdef CONFIG_NETDEVICES_MULTIQUEUE\n\tif (adapter->num_tx_queues > 1)\n\t\tnetdev->features |= NETIF_F_MULTI_QUEUE;\n\telse\n\t\tnetdev->features &= ~NETIF_F_MULTI_QUEUE;\n#endif\n\n\t/* call igb_desc_unused which always leaves\n\t * at least 1 descriptor unused to make sure\n\t * next_to_use != next_to_clean */\n\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\tstruct igb_ring *ring = adapter->rx_ring[i];\n\t\tigb_alloc_rx_buffers(ring, igb_desc_unused(ring));\n\t}\n}\n\n/**\n * igb_power_up_link - Power up the phy/serdes link\n * @adapter: address of board private structure\n **/\nvoid igb_power_up_link(struct igb_adapter *adapter)\n{\n\te1000_phy_hw_reset(&adapter->hw);\n\n\tif (adapter->hw.phy.media_type == e1000_media_type_copper)\n\t\te1000_power_up_phy(&adapter->hw);\n\telse\n\t\te1000_power_up_fiber_serdes_link(&adapter->hw);\n}\n\n/**\n * igb_power_down_link - Power down the phy/serdes link\n * @adapter: address of board private structure\n */\nstatic void igb_power_down_link(struct igb_adapter *adapter)\n{\n\tif (adapter->hw.phy.media_type == e1000_media_type_copper)\n\t\te1000_power_down_phy(&adapter->hw);\n\telse\n\t\te1000_shutdown_fiber_serdes_link(&adapter->hw);\n}\n\n/* Detect and switch function for Media Auto Sense */\nstatic void igb_check_swap_media(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 ctrl_ext, connsw;\n\tbool swap_now = false;\n\tbool link;\n\n\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tconnsw = E1000_READ_REG(hw, E1000_CONNSW);\n\tlink = igb_has_link(adapter);\n\n\t/* need to live swap if current media is copper and we have fiber/serdes\n\t * to go to.\n\t */\n\n\tif ((hw->phy.media_type == e1000_media_type_copper) &&\n\t (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {\n\t\tswap_now = true;\n\t} else if (!(connsw & E1000_CONNSW_SERDESD)) {\n\t\t/* copper signal takes time to appear */\n\t\tif (adapter->copper_tries < 2) {\n\t\t\tadapter->copper_tries++;\n\t\t\tconnsw |= E1000_CONNSW_AUTOSENSE_CONF;\n\t\t\tE1000_WRITE_REG(hw, E1000_CONNSW, connsw);\n\t\t\treturn;\n\t\t} else {\n\t\t\tadapter->copper_tries = 0;\n\t\t\tif ((connsw & E1000_CONNSW_PHYSD) &&\n\t\t\t (!(connsw & E1000_CONNSW_PHY_PDN))) {\n\t\t\t\tswap_now = true;\n\t\t\t\tconnsw &= ~E1000_CONNSW_AUTOSENSE_CONF;\n\t\t\t\tE1000_WRITE_REG(hw, E1000_CONNSW, connsw);\n\t\t\t}\n\t\t}\n\t}\n\n\tif (swap_now) {\n\t\tswitch (hw->phy.media_type) {\n\t\tcase e1000_media_type_copper:\n\t\t\tdev_info(pci_dev_to_dev(adapter->pdev),\n\t\t\t\t \"%s:MAS: changing media to fiber/serdes\\n\",\n\t\t\tadapter->netdev->name);\n\t\t\tctrl_ext |=\n\t\t\t\tE1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;\n\t\t\tadapter->flags |= IGB_FLAG_MEDIA_RESET;\n\t\t\tadapter->copper_tries = 0;\n\t\t\tbreak;\n\t\tcase e1000_media_type_internal_serdes:\n\t\tcase e1000_media_type_fiber:\n\t\t\tdev_info(pci_dev_to_dev(adapter->pdev),\n\t\t\t\t \"%s:MAS: changing media to copper\\n\",\n\t\t\t\t adapter->netdev->name);\n\t\t\tctrl_ext &=\n\t\t\t\t~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;\n\t\t\tadapter->flags |= IGB_FLAG_MEDIA_RESET;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* shouldn't get here during regular operation */\n\t\t\tdev_err(pci_dev_to_dev(adapter->pdev),\n\t\t\t\t\"%s:AMS: Invalid media type found, returning\\n\",\n\t\t\t\tadapter->netdev->name);\n\t\t\tbreak;\n\t\t}\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);\n\t}\n}\n\n#ifdef HAVE_I2C_SUPPORT\n/* igb_get_i2c_data - Reads the I2C SDA data bit\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Returns the I2C data bit value\n */\nstatic int igb_get_i2c_data(void *data)\n{\n\tstruct igb_adapter *adapter = (struct igb_adapter *)data;\n\tstruct e1000_hw *hw = &adapter->hw;\n\ts32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\treturn ((i2cctl & E1000_I2C_DATA_IN) != 0);\n}\n\n/* igb_set_i2c_data - Sets the I2C data bit\n * @data: pointer to hardware structure\n * @state: I2C data value (0 or 1) to set\n *\n * Sets the I2C data bit\n */\nstatic void igb_set_i2c_data(void *data, int state)\n{\n\tstruct igb_adapter *adapter = (struct igb_adapter *)data;\n\tstruct e1000_hw *hw = &adapter->hw;\n\ts32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\tif (state)\n\t\ti2cctl |= E1000_I2C_DATA_OUT;\n\telse\n\t\ti2cctl &= ~E1000_I2C_DATA_OUT;\n\n\ti2cctl &= ~E1000_I2C_DATA_OE_N;\n\ti2cctl |= E1000_I2C_CLK_OE_N;\n\n\tE1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);\n\tE1000_WRITE_FLUSH(hw);\n\n}\n\n/* igb_set_i2c_clk - Sets the I2C SCL clock\n * @data: pointer to hardware structure\n * @state: state to set clock\n *\n * Sets the I2C clock line to state\n */\nstatic void igb_set_i2c_clk(void *data, int state)\n{\n\tstruct igb_adapter *adapter = (struct igb_adapter *)data;\n\tstruct e1000_hw *hw = &adapter->hw;\n\ts32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\tif (state) {\n\t\ti2cctl |= E1000_I2C_CLK_OUT;\n\t\ti2cctl &= ~E1000_I2C_CLK_OE_N;\n\t} else {\n\t\ti2cctl &= ~E1000_I2C_CLK_OUT;\n\t\ti2cctl &= ~E1000_I2C_CLK_OE_N;\n\t}\n\tE1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);\n\tE1000_WRITE_FLUSH(hw);\n}\n\n/* igb_get_i2c_clk - Gets the I2C SCL clock state\n * @data: pointer to hardware structure\n *\n * Gets the I2C clock state\n */\nstatic int igb_get_i2c_clk(void *data)\n{\n\tstruct igb_adapter *adapter = (struct igb_adapter *)data;\n\tstruct e1000_hw *hw = &adapter->hw;\n\ts32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);\n\n\treturn ((i2cctl & E1000_I2C_CLK_IN) != 0);\n}\n\nstatic const struct i2c_algo_bit_data igb_i2c_algo = {\n\t.setsda\t\t= igb_set_i2c_data,\n\t.setscl\t\t= igb_set_i2c_clk,\n\t.getsda\t\t= igb_get_i2c_data,\n\t.getscl\t\t= igb_get_i2c_clk,\n\t.udelay\t\t= 5,\n\t.timeout\t= 20,\n};\n\n/* igb_init_i2c - Init I2C interface\n * @adapter: pointer to adapter structure\n *\n */\nstatic s32 igb_init_i2c(struct igb_adapter *adapter)\n{\n\ts32 status = E1000_SUCCESS;\n\n\t/* I2C interface supported on i350 devices */\n\tif (adapter->hw.mac.type != e1000_i350)\n\t\treturn E1000_SUCCESS;\n\n\t/* Initialize the i2c bus which is controlled by the registers.\n\t * This bus will use the i2c_algo_bit structue that implements\n\t * the protocol through toggling of the 4 bits in the register.\n\t */\n\tadapter->i2c_adap.owner = THIS_MODULE;\n\tadapter->i2c_algo = igb_i2c_algo;\n\tadapter->i2c_algo.data = adapter;\n\tadapter->i2c_adap.algo_data = &adapter->i2c_algo;\n\tadapter->i2c_adap.dev.parent = &adapter->pdev->dev;\n\tstrlcpy(adapter->i2c_adap.name, \"igb BB\",\n\t\tsizeof(adapter->i2c_adap.name));\n\tstatus = i2c_bit_add_bus(&adapter->i2c_adap);\n\treturn status;\n}\n\n#endif /* HAVE_I2C_SUPPORT */\n/**\n * igb_up - Open the interface and prepare it to handle traffic\n * @adapter: board private structure\n **/\nint igb_up(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint i;\n\n\t/* hardware has been reset, we need to reload some things */\n\tigb_configure(adapter);\n\n\tclear_bit(__IGB_DOWN, &adapter->state);\n\n\tfor (i = 0; i < adapter->num_q_vectors; i++)\n\t\tnapi_enable(&(adapter->q_vector[i]->napi));\n\n\tif (adapter->msix_entries)\n\t\tigb_configure_msix(adapter);\n\telse\n\t\tigb_assign_vector(adapter->q_vector[0], 0);\n\n\tigb_configure_lli(adapter);\n\n\t/* Clear any pending interrupts. */\n\tE1000_READ_REG(hw, E1000_ICR);\n\tigb_irq_enable(adapter);\n\n\t/* notify VFs that reset has been completed */\n\tif (adapter->vfs_allocated_count) {\n\t\tu32 reg_data = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\treg_data |= E1000_CTRL_EXT_PFRSTD;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, reg_data);\n\t}\n\n\tnetif_tx_start_all_queues(adapter->netdev);\n\n\tif (adapter->flags & IGB_FLAG_DETECT_BAD_DMA)\n\t\tschedule_work(&adapter->dma_err_task);\n\t/* start the watchdog. */\n\thw->mac.get_link_status = 1;\n\tschedule_work(&adapter->watchdog_task);\n\n\tif ((adapter->flags & IGB_FLAG_EEE) &&\n\t (!hw->dev_spec._82575.eee_disable))\n\t\tadapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;\n\n\treturn 0;\n}\n\nvoid igb_down(struct igb_adapter *adapter)\n{\n\tstruct net_device *netdev = adapter->netdev;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 tctl, rctl;\n\tint i;\n\n\t/* signal that we're down so the interrupt handler does not\n\t * reschedule our watchdog timer */\n\tset_bit(__IGB_DOWN, &adapter->state);\n\n\t/* disable receives in the hardware */\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);\n\t/* flush and sleep below */\n\n\tnetif_tx_stop_all_queues(netdev);\n\n\t/* disable transmits in the hardware */\n\ttctl = E1000_READ_REG(hw, E1000_TCTL);\n\ttctl &= ~E1000_TCTL_EN;\n\tE1000_WRITE_REG(hw, E1000_TCTL, tctl);\n\t/* flush both disables and wait for them to finish */\n\tE1000_WRITE_FLUSH(hw);\n\tusleep_range(10000, 20000);\n\n\tfor (i = 0; i < adapter->num_q_vectors; i++)\n\t\tnapi_disable(&(adapter->q_vector[i]->napi));\n\n\tigb_irq_disable(adapter);\n\n\tadapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;\n\n\tdel_timer_sync(&adapter->watchdog_timer);\n\tif (adapter->flags & IGB_FLAG_DETECT_BAD_DMA)\n\t\tdel_timer_sync(&adapter->dma_err_timer);\n\tdel_timer_sync(&adapter->phy_info_timer);\n\n\tnetif_carrier_off(netdev);\n\n\t/* record the stats before reset*/\n\tigb_update_stats(adapter);\n\n\tadapter->link_speed = 0;\n\tadapter->link_duplex = 0;\n\n#ifdef HAVE_PCI_ERS\n\tif (!pci_channel_offline(adapter->pdev))\n\t\tigb_reset(adapter);\n#else\n\tigb_reset(adapter);\n#endif\n\tigb_clean_all_tx_rings(adapter);\n\tigb_clean_all_rx_rings(adapter);\n#ifdef IGB_DCA\n\t/* since we reset the hardware DCA settings were cleared */\n\tigb_setup_dca(adapter);\n#endif\n}\n\nvoid igb_reinit_locked(struct igb_adapter *adapter)\n{\n\tWARN_ON(in_interrupt());\n\twhile (test_and_set_bit(__IGB_RESETTING, &adapter->state))\n\t\tusleep_range(1000, 2000);\n\tigb_down(adapter);\n\tigb_up(adapter);\n\tclear_bit(__IGB_RESETTING, &adapter->state);\n}\n\n/**\n * igb_enable_mas - Media Autosense re-enable after swap\n *\n * @adapter: adapter struct\n **/\nstatic s32 igb_enable_mas(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 connsw;\n\ts32 ret_val = E1000_SUCCESS;\n\n\tconnsw = E1000_READ_REG(hw, E1000_CONNSW);\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\t\t/* configure for SerDes media detect */\n\t\tif (!(connsw & E1000_CONNSW_SERDESD)) {\n\t\t\tconnsw |= E1000_CONNSW_ENRGSRC;\n\t\t\tconnsw |= E1000_CONNSW_AUTOSENSE_EN;\n\t\t\tE1000_WRITE_REG(hw, E1000_CONNSW, connsw);\n\t\t\tE1000_WRITE_FLUSH(hw);\n\t\t} else if (connsw & E1000_CONNSW_SERDESD) {\n\t\t\t/* already SerDes, no need to enable anything */\n\t\t\treturn ret_val;\n\t\t} else {\n\t\t\tdev_info(pci_dev_to_dev(adapter->pdev),\n\t\t\t\"%s:MAS: Unable to configure feature, disabling..\\n\",\n\t\t\tadapter->netdev->name);\n\t\t\tadapter->flags &= ~IGB_FLAG_MAS_ENABLE;\n\t\t}\n\t}\n\treturn ret_val;\n}\n\nvoid igb_reset(struct igb_adapter *adapter)\n{\n\tstruct pci_dev *pdev = adapter->pdev;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct e1000_mac_info *mac = &hw->mac;\n\tstruct e1000_fc_info *fc = &hw->fc;\n\tu32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;\n\n\t/* Repartition Pba for greater than 9k mtu\n\t * To take effect CTRL.RST is required.\n\t */\n\tswitch (mac->type) {\n\tcase e1000_i350:\n\tcase e1000_82580:\n\tcase e1000_i354:\n\t\tpba = E1000_READ_REG(hw, E1000_RXPBS);\n\t\tpba = e1000_rxpbs_adjust_82580(pba);\n\t\tbreak;\n\tcase e1000_82576:\n\t\tpba = E1000_READ_REG(hw, E1000_RXPBS);\n\t\tpba &= E1000_RXPBS_SIZE_MASK_82576;\n\t\tbreak;\n\tcase e1000_82575:\n\tcase e1000_i210:\n\tcase e1000_i211:\n\tdefault:\n\t\tpba = E1000_PBA_34K;\n\t\tbreak;\n\t}\n\n\tif ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&\n\t (mac->type < e1000_82576)) {\n\t\t/* adjust PBA for jumbo frames */\n\t\tE1000_WRITE_REG(hw, E1000_PBA, pba);\n\n\t\t/* To maintain wire speed transmits, the Tx FIFO should be\n\t\t * large enough to accommodate two full transmit packets,\n\t\t * rounded up to the next 1KB and expressed in KB. Likewise,\n\t\t * the Rx FIFO should be large enough to accommodate at least\n\t\t * one full receive packet and is similarly rounded up and\n\t\t * expressed in KB. */\n\t\tpba = E1000_READ_REG(hw, E1000_PBA);\n\t\t/* upper 16 bits has Tx packet buffer allocation size in KB */\n\t\ttx_space = pba >> 16;\n\t\t/* lower 16 bits has Rx packet buffer allocation size in KB */\n\t\tpba &= 0xffff;\n\t\t/* the tx fifo also stores 16 bytes of information about the tx\n\t\t * but don't include ethernet FCS because hardware appends it */\n\t\tmin_tx_space = (adapter->max_frame_size +\n\t\t\t\tsizeof(union e1000_adv_tx_desc) -\n\t\t\t\tETH_FCS_LEN) * 2;\n\t\tmin_tx_space = ALIGN(min_tx_space, 1024);\n\t\tmin_tx_space >>= 10;\n\t\t/* software strips receive CRC, so leave room for it */\n\t\tmin_rx_space = adapter->max_frame_size;\n\t\tmin_rx_space = ALIGN(min_rx_space, 1024);\n\t\tmin_rx_space >>= 10;\n\n\t\t/* If current Tx allocation is less than the min Tx FIFO size,\n\t\t * and the min Tx FIFO size is less than the current Rx FIFO\n\t\t * allocation, take space away from current Rx allocation */\n\t\tif (tx_space < min_tx_space &&\n\t\t ((min_tx_space - tx_space) < pba)) {\n\t\t\tpba = pba - (min_tx_space - tx_space);\n\n\t\t\t/* if short on rx space, rx wins and must trump tx\n\t\t\t * adjustment */\n\t\t\tif (pba < min_rx_space)\n\t\t\t\tpba = min_rx_space;\n\t\t}\n\t\tE1000_WRITE_REG(hw, E1000_PBA, pba);\n\t}\n\n\t/* flow control settings */\n\t/* The high water mark must be low enough to fit one full frame\n\t * (or the size used for early receive) above it in the Rx FIFO.\n\t * Set it to the lower of:\n\t * - 90% of the Rx FIFO size, or\n\t * - the full Rx FIFO size minus one full frame */\n\thwm = min(((pba << 10) * 9 / 10),\n\t\t\t((pba << 10) - 2 * adapter->max_frame_size));\n\n\tfc->high_water = hwm & 0xFFFFFFF0;\t/* 16-byte granularity */\n\tfc->low_water = fc->high_water - 16;\n\tfc->pause_time = 0xFFFF;\n\tfc->send_xon = 1;\n\tfc->current_mode = fc->requested_mode;\n\n\t/* disable receive for all VFs and wait one second */\n\tif (adapter->vfs_allocated_count) {\n\t\tint i;\n\t\t/*\n\t\t * Clear all flags except indication that the PF has set\n\t\t * the VF MAC addresses administratively\n\t\t */\n\t\tfor (i = 0 ; i < adapter->vfs_allocated_count; i++)\n\t\t\tadapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;\n\n\t\t/* ping all the active vfs to let them know we are going down */\n\t\tigb_ping_all_vfs(adapter);\n\n\t\t/* disable transmits and receives */\n\t\tE1000_WRITE_REG(hw, E1000_VFRE, 0);\n\t\tE1000_WRITE_REG(hw, E1000_VFTE, 0);\n\t}\n\n\t/* Allow time for pending master requests to run */\n\te1000_reset_hw(hw);\n\tE1000_WRITE_REG(hw, E1000_WUC, 0);\n\n\tif (adapter->flags & IGB_FLAG_MEDIA_RESET) {\n\t\te1000_setup_init_funcs(hw, TRUE);\n\t\tigb_check_options(adapter);\n\t\te1000_get_bus_info(hw);\n\t\tadapter->flags &= ~IGB_FLAG_MEDIA_RESET;\n\t}\n\tif (adapter->flags & IGB_FLAG_MAS_ENABLE) {\n\t\tif (igb_enable_mas(adapter))\n\t\t\tdev_err(pci_dev_to_dev(pdev),\n\t\t\t\t\"Error enabling Media Auto Sense\\n\");\n\t}\n\tif (e1000_init_hw(hw))\n\t\tdev_err(pci_dev_to_dev(pdev), \"Hardware Error\\n\");\n\n\t/*\n\t * Flow control settings reset on hardware reset, so guarantee flow\n\t * control is off when forcing speed.\n\t */\n\tif (!hw->mac.autoneg)\n\t\te1000_force_mac_fc(hw);\n\n\tigb_init_dmac(adapter, pba);\n\t/* Re-initialize the thermal sensor on i350 devices. */\n\tif (mac->type == e1000_i350 && hw->bus.func == 0) {\n\t\t/*\n\t\t * If present, re-initialize the external thermal sensor\n\t\t * interface.\n\t\t */\n\t\tif (adapter->ets)\n\t\t\te1000_set_i2c_bb(hw);\n\t\te1000_init_thermal_sensor_thresh(hw);\n\t}\n\n\t/*Re-establish EEE setting */\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\t\tswitch (mac->type) {\n\t\tcase e1000_i350:\n\t\tcase e1000_i210:\n\t\tcase e1000_i211:\n\t\t\te1000_set_eee_i350(hw);\n\t\t\tbreak;\n\t\tcase e1000_i354:\n\t\t\te1000_set_eee_i354(hw);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (!netif_running(adapter->netdev))\n\t\tigb_power_down_link(adapter);\n\n\tigb_update_mng_vlan(adapter);\n\n\t/* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */\n\tE1000_WRITE_REG(hw, E1000_VET, ETHERNET_IEEE_VLAN_TYPE);\n\n\n#ifdef HAVE_PTP_1588_CLOCK\n\t/* Re-enable PTP, where applicable. */\n\tigb_ptp_reset(adapter);\n#endif /* HAVE_PTP_1588_CLOCK */\n\n\te1000_get_phy_info(hw);\n\n\tadapter->devrc++;\n}\n\n#ifdef HAVE_NDO_SET_FEATURES\nstatic kni_netdev_features_t igb_fix_features(struct net_device *netdev,\n\t\t\t\t\t kni_netdev_features_t features)\n{\n\t/*\n\t * Since there is no support for separate tx vlan accel\n\t * enabled make sure tx flag is cleared if rx is.\n\t */\n#ifdef NETIF_F_HW_VLAN_CTAG_RX\n\tif (!(features & NETIF_F_HW_VLAN_CTAG_RX))\n\t\tfeatures &= ~NETIF_F_HW_VLAN_CTAG_TX;\n#else\n\tif (!(features & NETIF_F_HW_VLAN_RX))\n\t\tfeatures &= ~NETIF_F_HW_VLAN_TX;\n#endif\n\n\t/* If Rx checksum is disabled, then LRO should also be disabled */\n\tif (!(features & NETIF_F_RXCSUM))\n\t\tfeatures &= ~NETIF_F_LRO;\n\n\treturn features;\n}\n\nstatic int igb_set_features(struct net_device *netdev,\n\t\t\t kni_netdev_features_t features)\n{\n\tu32 changed = netdev->features ^ features;\n\n#ifdef NETIF_F_HW_VLAN_CTAG_RX\n\tif (changed & NETIF_F_HW_VLAN_CTAG_RX)\n#else\n\tif (changed & NETIF_F_HW_VLAN_RX)\n#endif\n\t\tigb_vlan_mode(netdev, features);\n\n\treturn 0;\n}\n\n#ifdef NTF_SELF\n#ifdef USE_CONST_DEV_UC_CHAR\nstatic int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],\n\t\t\t struct net_device *dev,\n\t\t\t const unsigned char *addr,\n#ifdef HAVE_NDO_FDB_ADD_VID\n\t\t\t u16 vid,\n#endif\n\t\t\t u16 flags)\n#else\nstatic int igb_ndo_fdb_add(struct ndmsg *ndm,\n\t\t\t struct net_device *dev,\n\t\t\t unsigned char *addr,\n\t\t\t u16 flags)\n#endif\n{\n\tstruct igb_adapter *adapter = netdev_priv(dev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint err;\n\n\tif (!(adapter->vfs_allocated_count))\n\t\treturn -EOPNOTSUPP;\n\n\t/* Hardware does not support aging addresses so if a\n\t * ndm_state is given only allow permanent addresses\n\t */\n\tif (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {\n\t\tpr_info(\"%s: FDB only supports static addresses\\n\",\n\t\t\tigb_driver_name);\n\t\treturn -EINVAL;\n\t}\n\n\tif (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {\n\t\tu32 rar_uc_entries = hw->mac.rar_entry_count -\n\t\t\t\t\t(adapter->vfs_allocated_count + 1);\n\n\t\tif (netdev_uc_count(dev) < rar_uc_entries)\n\t\t\terr = dev_uc_add_excl(dev, addr);\n\t\telse\n\t\t\terr = -ENOMEM;\n\t} else if (is_multicast_ether_addr(addr)) {\n\t\terr = dev_mc_add_excl(dev, addr);\n\t} else {\n\t\terr = -EINVAL;\n\t}\n\n\t/* Only return duplicate errors if NLM_F_EXCL is set */\n\tif (err == -EEXIST && !(flags & NLM_F_EXCL))\n\t\terr = 0;\n\n\treturn err;\n}\n\n#ifndef USE_DEFAULT_FDB_DEL_DUMP\n#ifdef USE_CONST_DEV_UC_CHAR\nstatic int igb_ndo_fdb_del(struct ndmsg *ndm,\n\t\t\t struct net_device *dev,\n\t\t\t const unsigned char *addr)\n#else\nstatic int igb_ndo_fdb_del(struct ndmsg *ndm,\n\t\t\t struct net_device *dev,\n\t\t\t unsigned char *addr)\n#endif\n{\n\tstruct igb_adapter *adapter = netdev_priv(dev);\n\tint err = -EOPNOTSUPP;\n\n\tif (ndm->ndm_state & NUD_PERMANENT) {\n\t\tpr_info(\"%s: FDB only supports static addresses\\n\",\n\t\t\tigb_driver_name);\n\t\treturn -EINVAL;\n\t}\n\n\tif (adapter->vfs_allocated_count) {\n\t\tif (is_unicast_ether_addr(addr))\n\t\t\terr = dev_uc_del(dev, addr);\n\t\telse if (is_multicast_ether_addr(addr))\n\t\t\terr = dev_mc_del(dev, addr);\n\t\telse\n\t\t\terr = -EINVAL;\n\t}\n\n\treturn err;\n}\n\nstatic int igb_ndo_fdb_dump(struct sk_buff *skb,\n\t\t\t struct netlink_callback *cb,\n\t\t\t struct net_device *dev,\n\t\t\t int idx)\n{\n\tstruct igb_adapter *adapter = netdev_priv(dev);\n\n\tif (adapter->vfs_allocated_count)\n\t\tidx = ndo_dflt_fdb_dump(skb, cb, dev, idx);\n\n\treturn idx;\n}\n#endif /* USE_DEFAULT_FDB_DEL_DUMP */\n\n#ifdef HAVE_BRIDGE_ATTRIBS\n#ifdef HAVE_NDO_BRIDGE_SET_DEL_LINK_FLAGS\nstatic int igb_ndo_bridge_setlink(struct net_device *dev,\n\t\t\t\t struct nlmsghdr *nlh,\n\t\t\t\t u16 flags)\n#else\nstatic int igb_ndo_bridge_setlink(struct net_device *dev,\n\t\t\t\t struct nlmsghdr *nlh)\n#endif /* HAVE_NDO_BRIDGE_SET_DEL_LINK_FLAGS */\n{\n\tstruct igb_adapter *adapter = netdev_priv(dev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct nlattr *attr, *br_spec;\n\tint rem;\n\n\tif (!(adapter->vfs_allocated_count))\n\t\treturn -EOPNOTSUPP;\n\n\tswitch (adapter->hw.mac.type) {\n\tcase e1000_82576:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\tbreak;\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n\n\tbr_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);\n\n\tnla_for_each_nested(attr, br_spec, rem) {\n\t\t__u16 mode;\n\n\t\tif (nla_type(attr) != IFLA_BRIDGE_MODE)\n\t\t\tcontinue;\n\n\t\tmode = nla_get_u16(attr);\n\t\tif (mode == BRIDGE_MODE_VEPA) {\n\t\t\te1000_vmdq_set_loopback_pf(hw, 0);\n\t\t\tadapter->flags &= ~IGB_FLAG_LOOPBACK_ENABLE;\n\t\t} else if (mode == BRIDGE_MODE_VEB) {\n\t\t\te1000_vmdq_set_loopback_pf(hw, 1);\n\t\t\tadapter->flags |= IGB_FLAG_LOOPBACK_ENABLE;\n\t\t} else\n\t\t\treturn -EINVAL;\n\n\t\tnetdev_info(adapter->netdev, \"enabling bridge mode: %s\\n\",\n\t\t\t mode == BRIDGE_MODE_VEPA ? \"VEPA\" : \"VEB\");\n\t}\n\n\treturn 0;\n}\n\n#ifdef HAVE_BRIDGE_FILTER\n#ifdef HAVE_NDO_BRIDGE_GETLINK_FILTER_MASK\nstatic int igb_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,\n\t\t\t\t struct net_device *dev, u32 filter_mask,\n\t\t\t\t int nlflags)\n#else\nstatic int igb_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,\n\t\t\t\t struct net_device *dev, u32 filter_mask)\n#endif /* HAVE_NDO_BRIDGE_GETLINK_FILTER_MASK */\n#else\nstatic int igb_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,\n\t\t\t\t struct net_device *dev)\n#endif\n{\n\tstruct igb_adapter *adapter = netdev_priv(dev);\n\tu16 mode;\n\n\tif (!(adapter->vfs_allocated_count))\n\t\treturn -EOPNOTSUPP;\n\n\tif (adapter->flags & IGB_FLAG_LOOPBACK_ENABLE)\n\t\tmode = BRIDGE_MODE_VEB;\n\telse\n\t\tmode = BRIDGE_MODE_VEPA;\n\n#ifdef HAVE_NDO_FDB_ADD_VID\n#ifdef HAVE_NDO_BRIDGE_GETLINK_FILTER_MASK\n\treturn ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode, 0, 0, nlflags);\n#else\n\treturn ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode, 0, 0);\n#endif /* HAVE_NDO_BRIDGE_GETLINK_FILTER_MASK */\n#else\n\treturn ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);\n#endif /* HAVE_NDO_FDB_ADD_VID */\n}\n#endif /* HAVE_BRIDGE_ATTRIBS */\n#endif /* NTF_SELF */\n\n#endif /* HAVE_NDO_SET_FEATURES */\n#ifdef HAVE_NET_DEVICE_OPS\nstatic const struct net_device_ops igb_netdev_ops = {\n\t.ndo_open\t\t= igb_open,\n\t.ndo_stop\t\t= igb_close,\n\t.ndo_start_xmit\t\t= igb_xmit_frame,\n\t.ndo_get_stats\t\t= igb_get_stats,\n\t.ndo_set_rx_mode\t= igb_set_rx_mode,\n\t.ndo_set_mac_address\t= igb_set_mac,\n\t.ndo_change_mtu\t\t= igb_change_mtu,\n\t.ndo_do_ioctl\t\t= igb_ioctl,\n\t.ndo_tx_timeout\t\t= igb_tx_timeout,\n\t.ndo_validate_addr\t= eth_validate_addr,\n\t.ndo_vlan_rx_add_vid\t= igb_vlan_rx_add_vid,\n\t.ndo_vlan_rx_kill_vid\t= igb_vlan_rx_kill_vid,\n#ifdef IFLA_VF_MAX\n\t.ndo_set_vf_mac\t\t= igb_ndo_set_vf_mac,\n\t.ndo_set_vf_vlan\t= igb_ndo_set_vf_vlan,\n#ifdef HAVE_VF_MIN_MAX_TXRATE\n\t.ndo_set_vf_rate\t= igb_ndo_set_vf_bw,\n#else /* HAVE_VF_MIN_MAX_TXRATE */\n\t.ndo_set_vf_tx_rate\t= igb_ndo_set_vf_bw,\n#endif /* HAVE_VF_MIN_MAX_TXRATE */\n\t.ndo_get_vf_config\t= igb_ndo_get_vf_config,\n#ifdef HAVE_VF_SPOOFCHK_CONFIGURE\n\t.ndo_set_vf_spoofchk\t= igb_ndo_set_vf_spoofchk,\n#endif /* HAVE_VF_SPOOFCHK_CONFIGURE */\n#endif /* IFLA_VF_MAX */\n#ifdef CONFIG_NET_POLL_CONTROLLER\n\t.ndo_poll_controller\t= igb_netpoll,\n#endif\n#ifdef HAVE_NDO_SET_FEATURES\n\t.ndo_fix_features\t= igb_fix_features,\n\t.ndo_set_features\t= igb_set_features,\n#endif\n#ifdef HAVE_VLAN_RX_REGISTER\n\t.ndo_vlan_rx_register\t= igb_vlan_mode,\n#endif\n#ifndef HAVE_RHEL6_NETDEV_OPS_EXT_FDB\n#ifdef NTF_SELF\n\t.ndo_fdb_add\t\t= igb_ndo_fdb_add,\n#ifndef USE_DEFAULT_FDB_DEL_DUMP\n\t.ndo_fdb_del\t\t= igb_ndo_fdb_del,\n\t.ndo_fdb_dump\t\t= igb_ndo_fdb_dump,\n#endif\n#endif /* ! HAVE_RHEL6_NETDEV_OPS_EXT_FDB */\n#ifdef HAVE_BRIDGE_ATTRIBS\n\t.ndo_bridge_setlink\t= igb_ndo_bridge_setlink,\n\t.ndo_bridge_getlink\t= igb_ndo_bridge_getlink,\n#endif /* HAVE_BRIDGE_ATTRIBS */\n#endif\n};\n\n#ifdef CONFIG_IGB_VMDQ_NETDEV\nstatic const struct net_device_ops igb_vmdq_ops = {\n\t.ndo_open\t\t= &igb_vmdq_open,\n\t.ndo_stop\t\t= &igb_vmdq_close,\n\t.ndo_start_xmit\t\t= &igb_vmdq_xmit_frame,\n\t.ndo_get_stats\t\t= &igb_vmdq_get_stats,\n\t.ndo_set_rx_mode\t= &igb_vmdq_set_rx_mode,\n\t.ndo_validate_addr\t= eth_validate_addr,\n\t.ndo_set_mac_address\t= &igb_vmdq_set_mac,\n\t.ndo_change_mtu\t\t= &igb_vmdq_change_mtu,\n\t.ndo_tx_timeout\t\t= &igb_vmdq_tx_timeout,\n\t.ndo_vlan_rx_register\t= &igb_vmdq_vlan_rx_register,\n\t.ndo_vlan_rx_add_vid\t= &igb_vmdq_vlan_rx_add_vid,\n\t.ndo_vlan_rx_kill_vid\t= &igb_vmdq_vlan_rx_kill_vid,\n};\n\n#endif /* CONFIG_IGB_VMDQ_NETDEV */\n#endif /* HAVE_NET_DEVICE_OPS */\n#ifdef CONFIG_IGB_VMDQ_NETDEV\nvoid igb_assign_vmdq_netdev_ops(struct net_device *vnetdev)\n{\n#ifdef HAVE_NET_DEVICE_OPS\n\tvnetdev->netdev_ops = &igb_vmdq_ops;\n#else\n\tdev->open = &igb_vmdq_open;\n\tdev->stop = &igb_vmdq_close;\n\tdev->hard_start_xmit = &igb_vmdq_xmit_frame;\n\tdev->get_stats = &igb_vmdq_get_stats;\n#ifdef HAVE_SET_RX_MODE\n\tdev->set_rx_mode = &igb_vmdq_set_rx_mode;\n#endif\n\tdev->set_multicast_list = &igb_vmdq_set_rx_mode;\n\tdev->set_mac_address = &igb_vmdq_set_mac;\n\tdev->change_mtu = &igb_vmdq_change_mtu;\n#ifdef HAVE_TX_TIMEOUT\n\tdev->tx_timeout = &igb_vmdq_tx_timeout;\n#endif\n#if defined(NETIF_F_HW_VLAN_TX) || defined(NETIF_F_HW_VLAN_CTAG_TX)\n\tdev->vlan_rx_register = &igb_vmdq_vlan_rx_register;\n\tdev->vlan_rx_add_vid = &igb_vmdq_vlan_rx_add_vid;\n\tdev->vlan_rx_kill_vid = &igb_vmdq_vlan_rx_kill_vid;\n#endif\n#endif\n\tigb_vmdq_set_ethtool_ops(vnetdev);\n\tvnetdev->watchdog_timeo = 5 * HZ;\n\n}\n\nint igb_init_vmdq_netdevs(struct igb_adapter *adapter)\n{\n\tint pool, err = 0, base_queue;\n\tstruct net_device *vnetdev;\n\tstruct igb_vmdq_adapter *vmdq_adapter;\n\n\tfor (pool = 1; pool < adapter->vmdq_pools; pool++) {\n\t\tint qpp = (!adapter->rss_queues ? 1 : adapter->rss_queues);\n\t\tbase_queue = pool * qpp;\n\t\tvnetdev = alloc_etherdev(sizeof(struct igb_vmdq_adapter));\n\t\tif (!vnetdev) {\n\t\t\terr = -ENOMEM;\n\t\t\tbreak;\n\t\t}\n\t\tvmdq_adapter = netdev_priv(vnetdev);\n\t\tvmdq_adapter->vnetdev = vnetdev;\n\t\tvmdq_adapter->real_adapter = adapter;\n\t\tvmdq_adapter->rx_ring = adapter->rx_ring[base_queue];\n\t\tvmdq_adapter->tx_ring = adapter->tx_ring[base_queue];\n\t\tigb_assign_vmdq_netdev_ops(vnetdev);\n\t\tsnprintf(vnetdev->name, IFNAMSIZ, \"%sv%d\",\n\t\t\t adapter->netdev->name, pool);\n\t\tvnetdev->features = adapter->netdev->features;\n#ifdef HAVE_NETDEV_VLAN_FEATURES\n\t\tvnetdev->vlan_features = adapter->netdev->vlan_features;\n#endif\n\t\tadapter->vmdq_netdev[pool-1] = vnetdev;\n\t\terr = register_netdev(vnetdev);\n\t\tif (err)\n\t\t\tbreak;\n\t}\n\treturn err;\n}\n\nint igb_remove_vmdq_netdevs(struct igb_adapter *adapter)\n{\n\tint pool, err = 0;\n\n\tfor (pool = 1; pool < adapter->vmdq_pools; pool++) {\n\t\tunregister_netdev(adapter->vmdq_netdev[pool-1]);\n\t\tfree_netdev(adapter->vmdq_netdev[pool-1]);\n\t\tadapter->vmdq_netdev[pool-1] = NULL;\n\t}\n\treturn err;\n}\n#endif /* CONFIG_IGB_VMDQ_NETDEV */\n\n/**\n * igb_set_fw_version - Configure version string for ethtool\n * @adapter: adapter struct\n *\n **/\nstatic void igb_set_fw_version(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct e1000_fw_version fw;\n\n\te1000_get_fw_version(hw, &fw);\n\n\tswitch (hw->mac.type) {\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\tif (!(e1000_get_flash_presence_i210(hw))) {\n\t\t\tsnprintf(adapter->fw_version,\n\t\t\t sizeof(adapter->fw_version),\n\t\t\t \"%2d.%2d-%d\",\n\t\t\t fw.invm_major, fw.invm_minor, fw.invm_img_type);\n\t\t\tbreak;\n\t\t}\n\t\t/* fall through */\n\tdefault:\n\t\t/* if option rom is valid, display its version too*/\n\t\tif (fw.or_valid) {\n\t\t\tsnprintf(adapter->fw_version,\n\t\t\t sizeof(adapter->fw_version),\n\t\t\t \"%d.%d, 0x%08x, %d.%d.%d\",\n\t\t\t fw.eep_major, fw.eep_minor, fw.etrack_id,\n\t\t\t fw.or_major, fw.or_build, fw.or_patch);\n\t\t/* no option rom */\n\t\t} else {\n\t\t\tif (fw.etrack_id != 0X0000) {\n\t\t\tsnprintf(adapter->fw_version,\n\t\t\t sizeof(adapter->fw_version),\n\t\t\t \"%d.%d, 0x%08x\",\n\t\t\t fw.eep_major, fw.eep_minor, fw.etrack_id);\n\t\t\t} else {\n\t\t\tsnprintf(adapter->fw_version,\n\t\t\t sizeof(adapter->fw_version),\n\t\t\t \"%d.%d.%d\",\n\t\t\t fw.eep_major, fw.eep_minor, fw.eep_build);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\t}\n\n\treturn;\n}\n\n/**\n * igb_init_mas - init Media Autosense feature if enabled in the NVM\n *\n * @adapter: adapter struct\n **/\nstatic void igb_init_mas(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu16 eeprom_data;\n\n\te1000_read_nvm(hw, NVM_COMPAT, 1, &eeprom_data);\n\tswitch (hw->bus.func) {\n\tcase E1000_FUNC_0:\n\t\tif (eeprom_data & IGB_MAS_ENABLE_0)\n\t\t\tadapter->flags |= IGB_FLAG_MAS_ENABLE;\n\t\tbreak;\n\tcase E1000_FUNC_1:\n\t\tif (eeprom_data & IGB_MAS_ENABLE_1)\n\t\t\tadapter->flags |= IGB_FLAG_MAS_ENABLE;\n\t\tbreak;\n\tcase E1000_FUNC_2:\n\t\tif (eeprom_data & IGB_MAS_ENABLE_2)\n\t\t\tadapter->flags |= IGB_FLAG_MAS_ENABLE;\n\t\tbreak;\n\tcase E1000_FUNC_3:\n\t\tif (eeprom_data & IGB_MAS_ENABLE_3)\n\t\t\tadapter->flags |= IGB_FLAG_MAS_ENABLE;\n\t\tbreak;\n\tdefault:\n\t\t/* Shouldn't get here */\n\t\tdev_err(pci_dev_to_dev(adapter->pdev),\n\t\t\t\"%s:AMS: Invalid port configuration, returning\\n\",\n\t\t\tadapter->netdev->name);\n\t\tbreak;\n\t}\n}\n\n/**\n * igb_probe - Device Initialization Routine\n * @pdev: PCI device information struct\n * @ent: entry in igb_pci_tbl\n *\n * Returns 0 on success, negative on failure\n *\n * igb_probe initializes an adapter identified by a pci_dev structure.\n * The OS initialization, configuring of the adapter private structure,\n * and a hardware reset occur.\n **/\nstatic int __devinit igb_probe(struct pci_dev *pdev,\n\t\t\t const struct pci_device_id *ent)\n{\n\tstruct net_device *netdev;\n\tstruct igb_adapter *adapter;\n\tstruct e1000_hw *hw;\n\tu16 eeprom_data = 0;\n\tu8 pba_str[E1000_PBANUM_LENGTH];\n\ts32 ret_val;\n\tstatic int global_quad_port_a; /* global quad port a indication */\n\tint i, err, pci_using_dac;\n\tstatic int cards_found;\n\n\terr = pci_enable_device_mem(pdev);\n\tif (err)\n\t\treturn err;\n\n\tpci_using_dac = 0;\n\terr = dma_set_mask(pci_dev_to_dev(pdev), DMA_BIT_MASK(64));\n\tif (!err) {\n\t\terr = dma_set_coherent_mask(pci_dev_to_dev(pdev), DMA_BIT_MASK(64));\n\t\tif (!err)\n\t\t\tpci_using_dac = 1;\n\t} else {\n\t\terr = dma_set_mask(pci_dev_to_dev(pdev), DMA_BIT_MASK(32));\n\t\tif (err) {\n\t\t\terr = dma_set_coherent_mask(pci_dev_to_dev(pdev), DMA_BIT_MASK(32));\n\t\t\tif (err) {\n\t\t\t\tIGB_ERR(\"No usable DMA configuration, \"\n\t\t\t\t \"aborting\\n\");\n\t\t\t\tgoto err_dma;\n\t\t\t}\n\t\t}\n\t}\n\n#ifndef HAVE_ASPM_QUIRKS\n\t/* 82575 requires that the pci-e link partner disable the L0s state */\n\tswitch (pdev->device) {\n\tcase E1000_DEV_ID_82575EB_COPPER:\n\tcase E1000_DEV_ID_82575EB_FIBER_SERDES:\n\tcase E1000_DEV_ID_82575GB_QUAD_COPPER:\n\t\tpci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);\n\tdefault:\n\t\tbreak;\n\t}\n\n#endif /* HAVE_ASPM_QUIRKS */\n\terr = pci_request_selected_regions(pdev,\n\t pci_select_bars(pdev,\n IORESOURCE_MEM),\n\t igb_driver_name);\n\tif (err)\n\t\tgoto err_pci_reg;\n\n\tpci_enable_pcie_error_reporting(pdev);\n\n\tpci_set_master(pdev);\n\n\terr = -ENOMEM;\n#ifdef HAVE_TX_MQ\n\tnetdev = alloc_etherdev_mq(sizeof(struct igb_adapter),\n\t IGB_MAX_TX_QUEUES);\n#else\n\tnetdev = alloc_etherdev(sizeof(struct igb_adapter));\n#endif /* HAVE_TX_MQ */\n\tif (!netdev)\n\t\tgoto err_alloc_etherdev;\n\n\tSET_MODULE_OWNER(netdev);\n\tSET_NETDEV_DEV(netdev, &pdev->dev);\n\n\tpci_set_drvdata(pdev, netdev);\n\tadapter = netdev_priv(netdev);\n\tadapter->netdev = netdev;\n\tadapter->pdev = pdev;\n\thw = &adapter->hw;\n\thw->back = adapter;\n\tadapter->port_num = hw->bus.func;\n\tadapter->msg_enable = (1 << debug) - 1;\n\n#ifdef HAVE_PCI_ERS\n\terr = pci_save_state(pdev);\n\tif (err)\n\t\tgoto err_ioremap;\n#endif\n\terr = -EIO;\n\thw->hw_addr = ioremap(pci_resource_start(pdev, 0),\n\t pci_resource_len(pdev, 0));\n\tif (!hw->hw_addr)\n\t\tgoto err_ioremap;\n\n#ifdef HAVE_NET_DEVICE_OPS\n\tnetdev->netdev_ops = &igb_netdev_ops;\n#else /* HAVE_NET_DEVICE_OPS */\n\tnetdev->open = &igb_open;\n\tnetdev->stop = &igb_close;\n\tnetdev->get_stats = &igb_get_stats;\n#ifdef HAVE_SET_RX_MODE\n\tnetdev->set_rx_mode = &igb_set_rx_mode;\n#endif\n\tnetdev->set_multicast_list = &igb_set_rx_mode;\n\tnetdev->set_mac_address = &igb_set_mac;\n\tnetdev->change_mtu = &igb_change_mtu;\n\tnetdev->do_ioctl = &igb_ioctl;\n#ifdef HAVE_TX_TIMEOUT\n\tnetdev->tx_timeout = &igb_tx_timeout;\n#endif\n\tnetdev->vlan_rx_register = igb_vlan_mode;\n\tnetdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;\n\tnetdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;\n#ifdef CONFIG_NET_POLL_CONTROLLER\n\tnetdev->poll_controller = igb_netpoll;\n#endif\n\tnetdev->hard_start_xmit = &igb_xmit_frame;\n#endif /* HAVE_NET_DEVICE_OPS */\n\tigb_set_ethtool_ops(netdev);\n#ifdef HAVE_TX_TIMEOUT\n\tnetdev->watchdog_timeo = 5 * HZ;\n#endif\n\n\tstrncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);\n\n\tadapter->bd_number = cards_found;\n\n\t/* setup the private structure */\n\terr = igb_sw_init(adapter);\n\tif (err)\n\t\tgoto err_sw_init;\n\n\te1000_get_bus_info(hw);\n\n\thw->phy.autoneg_wait_to_complete = FALSE;\n\thw->mac.adaptive_ifs = FALSE;\n\n\t/* Copper options */\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\t\thw->phy.mdix = AUTO_ALL_MODES;\n\t\thw->phy.disable_polarity_correction = FALSE;\n\t\thw->phy.ms_type = e1000_ms_hw_default;\n\t}\n\n\tif (e1000_check_reset_block(hw))\n\t\tdev_info(pci_dev_to_dev(pdev),\n\t\t\t\"PHY reset is blocked due to SOL/IDER session.\\n\");\n\n\t/*\n\t * features is initialized to 0 in allocation, it might have bits\n\t * set by igb_sw_init so we should use an or instead of an\n\t * assignment.\n\t */\n\tnetdev->features |= NETIF_F_SG |\n\t\t\t NETIF_F_IP_CSUM |\n#ifdef NETIF_F_IPV6_CSUM\n\t\t\t NETIF_F_IPV6_CSUM |\n#endif\n#ifdef NETIF_F_TSO\n\t\t\t NETIF_F_TSO |\n#ifdef NETIF_F_TSO6\n\t\t\t NETIF_F_TSO6 |\n#endif\n#endif /* NETIF_F_TSO */\n#ifdef NETIF_F_RXHASH\n\t\t\t NETIF_F_RXHASH |\n#endif\n\t\t\t NETIF_F_RXCSUM |\n#ifdef NETIF_F_HW_VLAN_CTAG_RX\n\t\t\t NETIF_F_HW_VLAN_CTAG_RX |\n\t\t\t NETIF_F_HW_VLAN_CTAG_TX;\n#else\n\t\t\t NETIF_F_HW_VLAN_RX |\n\t\t\t NETIF_F_HW_VLAN_TX;\n#endif\n\n\tif (hw->mac.type >= e1000_82576)\n\t\tnetdev->features |= NETIF_F_SCTP_CSUM;\n\n#ifdef HAVE_NDO_SET_FEATURES\n\t/* copy netdev features into list of user selectable features */\n\tnetdev->hw_features |= netdev->features;\n#ifndef IGB_NO_LRO\n\n\t/* give us the option of enabling LRO later */\n\tnetdev->hw_features |= NETIF_F_LRO;\n#endif\n#else\n#ifdef NETIF_F_GRO\n\n\t/* this is only needed on kernels prior to 2.6.39 */\n\tnetdev->features |= NETIF_F_GRO;\n#endif\n#endif\n\n\t/* set this bit last since it cannot be part of hw_features */\n#ifdef NETIF_F_HW_VLAN_CTAG_FILTER\n\tnetdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;\n#else\n\tnetdev->features |= NETIF_F_HW_VLAN_FILTER;\n#endif\n\n#ifdef HAVE_NETDEV_VLAN_FEATURES\n\tnetdev->vlan_features |= NETIF_F_TSO |\n\t\t\t\t NETIF_F_TSO6 |\n\t\t\t\t NETIF_F_IP_CSUM |\n\t\t\t\t NETIF_F_IPV6_CSUM |\n\t\t\t\t NETIF_F_SG;\n\n#endif\n\tif (pci_using_dac)\n\t\tnetdev->features |= NETIF_F_HIGHDMA;\n\n\tadapter->en_mng_pt = e1000_enable_mng_pass_thru(hw);\n#ifdef DEBUG\n\tif (adapter->dmac != IGB_DMAC_DISABLE)\n\t\tprintk(\"%s: DMA Coalescing is enabled..\\n\", netdev->name);\n#endif\n\n\t/* before reading the NVM, reset the controller to put the device in a\n\t * known good starting state */\n\te1000_reset_hw(hw);\n\n\t/* make sure the NVM is good */\n\tif (e1000_validate_nvm_checksum(hw) < 0) {\n\t\tdev_err(pci_dev_to_dev(pdev), \"The NVM Checksum Is Not\"\n\t\t \" Valid\\n\");\n\t\terr = -EIO;\n\t\tgoto err_eeprom;\n\t}\n\n\t/* copy the MAC address out of the NVM */\n\tif (e1000_read_mac_addr(hw))\n\t\tdev_err(pci_dev_to_dev(pdev), \"NVM Read Error\\n\");\n\tmemcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);\n#ifdef ETHTOOL_GPERMADDR\n\tmemcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);\n\n\tif (!is_valid_ether_addr(netdev->perm_addr)) {\n#else\n\tif (!is_valid_ether_addr(netdev->dev_addr)) {\n#endif\n\t\tdev_err(pci_dev_to_dev(pdev), \"Invalid MAC Address\\n\");\n\t\terr = -EIO;\n\t\tgoto err_eeprom;\n\t}\n\n\tmemcpy(&adapter->mac_table[0].addr, hw->mac.addr, netdev->addr_len);\n\tadapter->mac_table[0].queue = adapter->vfs_allocated_count;\n\tadapter->mac_table[0].state = (IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE);\n\tigb_rar_set(adapter, 0);\n\n\t/* get firmware version for ethtool -i */\n\tigb_set_fw_version(adapter);\n\n\t/* Check if Media Autosense is enabled */\n\tif (hw->mac.type == e1000_82580)\n\t\tigb_init_mas(adapter);\n\tsetup_timer(&adapter->watchdog_timer, &igb_watchdog,\n\t (unsigned long) adapter);\n\tif (adapter->flags & IGB_FLAG_DETECT_BAD_DMA)\n\t\tsetup_timer(&adapter->dma_err_timer, &igb_dma_err_timer,\n\t\t\t (unsigned long) adapter);\n\tsetup_timer(&adapter->phy_info_timer, &igb_update_phy_info,\n\t (unsigned long) adapter);\n\n\tINIT_WORK(&adapter->reset_task, igb_reset_task);\n\tINIT_WORK(&adapter->watchdog_task, igb_watchdog_task);\n\tif (adapter->flags & IGB_FLAG_DETECT_BAD_DMA)\n\t\tINIT_WORK(&adapter->dma_err_task, igb_dma_err_task);\n\n\t/* Initialize link properties that are user-changeable */\n\tadapter->fc_autoneg = true;\n\thw->mac.autoneg = true;\n\thw->phy.autoneg_advertised = 0x2f;\n\n\thw->fc.requested_mode = e1000_fc_default;\n\thw->fc.current_mode = e1000_fc_default;\n\n\te1000_validate_mdi_setting(hw);\n\n\t/* By default, support wake on port A */\n\tif (hw->bus.func == 0)\n\t\tadapter->flags |= IGB_FLAG_WOL_SUPPORTED;\n\n\t/* Check the NVM for wake support for non-port A ports */\n\tif (hw->mac.type >= e1000_82580)\n\t\thw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +\n\t\t NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,\n\t\t &eeprom_data);\n\telse if (hw->bus.func == 1)\n\t\te1000_read_nvm(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);\n\n\tif (eeprom_data & IGB_EEPROM_APME)\n\t\tadapter->flags |= IGB_FLAG_WOL_SUPPORTED;\n\n\t/* now that we have the eeprom settings, apply the special cases where\n\t * the eeprom may be wrong or the board simply won't support wake on\n\t * lan on a particular port */\n\tswitch (pdev->device) {\n\tcase E1000_DEV_ID_82575GB_QUAD_COPPER:\n\t\tadapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;\n\t\tbreak;\n\tcase E1000_DEV_ID_82575EB_FIBER_SERDES:\n\tcase E1000_DEV_ID_82576_FIBER:\n\tcase E1000_DEV_ID_82576_SERDES:\n\t\t/* Wake events only supported on port A for dual fiber\n\t\t * regardless of eeprom setting */\n\t\tif (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FUNC_1)\n\t\t\tadapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;\n\t\tbreak;\n\tcase E1000_DEV_ID_82576_QUAD_COPPER:\n\tcase E1000_DEV_ID_82576_QUAD_COPPER_ET2:\n\t\t/* if quad port adapter, disable WoL on all but port A */\n\t\tif (global_quad_port_a != 0)\n\t\t\tadapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;\n\t\telse\n\t\t\tadapter->flags |= IGB_FLAG_QUAD_PORT_A;\n\t\t/* Reset for multiple quad port adapters */\n\t\tif (++global_quad_port_a == 4)\n\t\t\tglobal_quad_port_a = 0;\n\t\tbreak;\n\tdefault:\n\t\t/* If the device can't wake, don't set software support */\n\t\tif (!device_can_wakeup(&adapter->pdev->dev))\n\t\t\tadapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;\n\t\tbreak;\n\t}\n\n\t/* initialize the wol settings based on the eeprom settings */\n\tif (adapter->flags & IGB_FLAG_WOL_SUPPORTED)\n\t\tadapter->wol |= E1000_WUFC_MAG;\n\n\t/* Some vendors want WoL disabled by default, but still supported */\n\tif ((hw->mac.type == e1000_i350) &&\n\t (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {\n\t\tadapter->flags |= IGB_FLAG_WOL_SUPPORTED;\n\t\tadapter->wol = 0;\n\t}\n\n\tdevice_set_wakeup_enable(pci_dev_to_dev(adapter->pdev),\n\t\t\t\t adapter->flags & IGB_FLAG_WOL_SUPPORTED);\n\n\t/* reset the hardware with the new settings */\n\tigb_reset(adapter);\n\tadapter->devrc = 0;\n\n#ifdef HAVE_I2C_SUPPORT\n\t/* Init the I2C interface */\n\terr = igb_init_i2c(adapter);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to init i2c interface\\n\");\n\t\tgoto err_eeprom;\n\t}\n#endif /* HAVE_I2C_SUPPORT */\n\n\t/* let the f/w know that the h/w is now under the control of the\n\t * driver. */\n\tigb_get_hw_control(adapter);\n\n\tstrncpy(netdev->name, \"eth%d\", IFNAMSIZ);\n\terr = register_netdev(netdev);\n\tif (err)\n\t\tgoto err_register;\n\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n\terr = igb_init_vmdq_netdevs(adapter);\n\tif (err)\n\t\tgoto err_register;\n#endif\n\t/* carrier off reporting is important to ethtool even BEFORE open */\n\tnetif_carrier_off(netdev);\n\n#ifdef IGB_DCA\n\tif (dca_add_requester(&pdev->dev) == E1000_SUCCESS) {\n\t\tadapter->flags |= IGB_FLAG_DCA_ENABLED;\n\t\tdev_info(pci_dev_to_dev(pdev), \"DCA enabled\\n\");\n\t\tigb_setup_dca(adapter);\n\t}\n\n#endif\n#ifdef HAVE_PTP_1588_CLOCK\n\t/* do hw tstamp init after resetting */\n\tigb_ptp_init(adapter);\n#endif /* HAVE_PTP_1588_CLOCK */\n\n\tdev_info(pci_dev_to_dev(pdev), \"Intel(R) Gigabit Ethernet Network Connection\\n\");\n\t/* print bus type/speed/width info */\n\tdev_info(pci_dev_to_dev(pdev), \"%s: (PCIe:%s:%s) \",\n\t netdev->name,\n\t ((hw->bus.speed == e1000_bus_speed_2500) ? \"2.5GT/s\" :\n\t (hw->bus.speed == e1000_bus_speed_5000) ? \"5.0GT/s\" :\n\t\t (hw->mac.type == e1000_i354) ? \"integrated\" :\n\t \"unknown\"),\n\t ((hw->bus.width == e1000_bus_width_pcie_x4) ? \"Width x4\" :\n\t (hw->bus.width == e1000_bus_width_pcie_x2) ? \"Width x2\" :\n\t (hw->bus.width == e1000_bus_width_pcie_x1) ? \"Width x1\" :\n\t\t (hw->mac.type == e1000_i354) ? \"integrated\" :\n\t \"unknown\"));\n\tdev_info(pci_dev_to_dev(pdev), \"%s: MAC: \", netdev->name);\n\tfor (i = 0; i < 6; i++)\n\t\tprintk(\"%2.2x%c\", netdev->dev_addr[i], i == 5 ? '\\n' : ':');\n\n\tret_val = e1000_read_pba_string(hw, pba_str, E1000_PBANUM_LENGTH);\n\tif (ret_val)\n\t\tstrncpy(pba_str, \"Unknown\", sizeof(pba_str) - 1);\n\tdev_info(pci_dev_to_dev(pdev), \"%s: PBA No: %s\\n\", netdev->name,\n\t\t pba_str);\n\n\n\t/* Initialize the thermal sensor on i350 devices. */\n\tif (hw->mac.type == e1000_i350) {\n\t\tif (hw->bus.func == 0) {\n\t\t\tu16 ets_word;\n\n\t\t\t/*\n\t\t\t * Read the NVM to determine if this i350 device\n\t\t\t * supports an external thermal sensor.\n\t\t\t */\n\t\t\te1000_read_nvm(hw, NVM_ETS_CFG, 1, &ets_word);\n\t\t\tif (ets_word != 0x0000 && ets_word != 0xFFFF)\n\t\t\t\tadapter->ets = true;\n\t\t\telse\n\t\t\t\tadapter->ets = false;\n\t\t}\n#ifdef IGB_HWMON\n\n\t\tigb_sysfs_init(adapter);\n#else\n#ifdef IGB_PROCFS\n\n\t\tigb_procfs_init(adapter);\n#endif /* IGB_PROCFS */\n#endif /* IGB_HWMON */\n\t} else {\n\t\tadapter->ets = false;\n\t}\n\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\t\tswitch (hw->mac.type) {\n\t\tcase e1000_i350:\n\t\tcase e1000_i210:\n\t\tcase e1000_i211:\n\t\t\t/* Enable EEE for internal copper PHY devices */\n\t\t\terr = e1000_set_eee_i350(hw);\n\t\t\tif ((!err) &&\n\t\t\t (adapter->flags & IGB_FLAG_EEE))\n\t\t\t\tadapter->eee_advert =\n\t\t\t\t\tMDIO_EEE_100TX | MDIO_EEE_1000T;\n\t\t\tbreak;\n\t\tcase e1000_i354:\n\t\t\tif ((E1000_READ_REG(hw, E1000_CTRL_EXT)) &\n\t\t\t (E1000_CTRL_EXT_LINK_MODE_SGMII)) {\n\t\t\t\terr = e1000_set_eee_i354(hw);\n\t\t\t\tif ((!err) &&\n\t\t\t\t (adapter->flags & IGB_FLAG_EEE))\n\t\t\t\t\tadapter->eee_advert =\n\t\t\t\t\t MDIO_EEE_100TX | MDIO_EEE_1000T;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* send driver version info to firmware */\n\tif (hw->mac.type >= e1000_i350)\n\t\tigb_init_fw(adapter);\n\n#ifndef IGB_NO_LRO\n\tif (netdev->features & NETIF_F_LRO)\n\t\tdev_info(pci_dev_to_dev(pdev), \"Internal LRO is enabled \\n\");\n\telse\n\t\tdev_info(pci_dev_to_dev(pdev), \"LRO is disabled \\n\");\n#endif\n\tdev_info(pci_dev_to_dev(pdev),\n\t \"Using %s interrupts. %d rx queue(s), %d tx queue(s)\\n\",\n\t adapter->msix_entries ? \"MSI-X\" :\n\t (adapter->flags & IGB_FLAG_HAS_MSI) ? \"MSI\" : \"legacy\",\n\t adapter->num_rx_queues, adapter->num_tx_queues);\n\n\tcards_found++;\n\n\tpm_runtime_put_noidle(&pdev->dev);\n\treturn 0;\n\nerr_register:\n\tigb_release_hw_control(adapter);\n#ifdef HAVE_I2C_SUPPORT\n\tmemset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));\n#endif /* HAVE_I2C_SUPPORT */\nerr_eeprom:\n\tif (!e1000_check_reset_block(hw))\n\t\te1000_phy_hw_reset(hw);\n\n\tif (hw->flash_address)\n\t\tiounmap(hw->flash_address);\nerr_sw_init:\n\tigb_clear_interrupt_scheme(adapter);\n\tigb_reset_sriov_capability(adapter);\n\tiounmap(hw->hw_addr);\nerr_ioremap:\n\tfree_netdev(netdev);\nerr_alloc_etherdev:\n\tpci_release_selected_regions(pdev,\n\t pci_select_bars(pdev, IORESOURCE_MEM));\nerr_pci_reg:\nerr_dma:\n\tpci_disable_device(pdev);\n\treturn err;\n}\n#ifdef HAVE_I2C_SUPPORT\n/*\n * igb_remove_i2c - Cleanup I2C interface\n * @adapter: pointer to adapter structure\n *\n */\nstatic void igb_remove_i2c(struct igb_adapter *adapter)\n{\n\n\t/* free the adapter bus structure */\n\ti2c_del_adapter(&adapter->i2c_adap);\n}\n#endif /* HAVE_I2C_SUPPORT */\n\n/**\n * igb_remove - Device Removal Routine\n * @pdev: PCI device information struct\n *\n * igb_remove is called by the PCI subsystem to alert the driver\n * that it should release a PCI device. The could be caused by a\n * Hot-Plug event, or because the driver is going to be removed from\n * memory.\n **/\nstatic void __devexit igb_remove(struct pci_dev *pdev)\n{\n\tstruct net_device *netdev = pci_get_drvdata(pdev);\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\tpm_runtime_get_noresume(&pdev->dev);\n#ifdef HAVE_I2C_SUPPORT\n\tigb_remove_i2c(adapter);\n#endif /* HAVE_I2C_SUPPORT */\n#ifdef HAVE_PTP_1588_CLOCK\n\tigb_ptp_stop(adapter);\n#endif /* HAVE_PTP_1588_CLOCK */\n\n\t/* flush_scheduled work may reschedule our watchdog task, so\n\t * explicitly disable watchdog tasks from being rescheduled */\n\tset_bit(__IGB_DOWN, &adapter->state);\n\tdel_timer_sync(&adapter->watchdog_timer);\n\tif (adapter->flags & IGB_FLAG_DETECT_BAD_DMA)\n\t\tdel_timer_sync(&adapter->dma_err_timer);\n\tdel_timer_sync(&adapter->phy_info_timer);\n\n\tflush_scheduled_work();\n\n#ifdef IGB_DCA\n\tif (adapter->flags & IGB_FLAG_DCA_ENABLED) {\n\t\tdev_info(pci_dev_to_dev(pdev), \"DCA disabled\\n\");\n\t\tdca_remove_requester(&pdev->dev);\n\t\tadapter->flags &= ~IGB_FLAG_DCA_ENABLED;\n\t\tE1000_WRITE_REG(hw, E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_DISABLE);\n\t}\n#endif\n\n\t/* Release control of h/w to f/w. If f/w is AMT enabled, this\n\t * would have already happened in close and is redundant. */\n\tigb_release_hw_control(adapter);\n\n\tunregister_netdev(netdev);\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n\tigb_remove_vmdq_netdevs(adapter);\n#endif\n\n\tigb_clear_interrupt_scheme(adapter);\n\tigb_reset_sriov_capability(adapter);\n\n\tiounmap(hw->hw_addr);\n\tif (hw->flash_address)\n\t\tiounmap(hw->flash_address);\n\tpci_release_selected_regions(pdev,\n\t pci_select_bars(pdev, IORESOURCE_MEM));\n\n#ifdef IGB_HWMON\n\tigb_sysfs_exit(adapter);\n#else\n#ifdef IGB_PROCFS\n\tigb_procfs_exit(adapter);\n#endif /* IGB_PROCFS */\n#endif /* IGB_HWMON */\n\tkfree(adapter->mac_table);\n\tkfree(adapter->shadow_vfta);\n\tfree_netdev(netdev);\n\n\tpci_disable_pcie_error_reporting(pdev);\n\n\tpci_disable_device(pdev);\n}\n\n/**\n * igb_sw_init - Initialize general software structures (struct igb_adapter)\n * @adapter: board private structure to initialize\n *\n * igb_sw_init initializes the Adapter private data structure.\n * Fields are initialized based on PCI device information and\n * OS network device settings (MTU size).\n **/\nstatic int igb_sw_init(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct net_device *netdev = adapter->netdev;\n\tstruct pci_dev *pdev = adapter->pdev;\n\n\t/* PCI config space info */\n\n\thw->vendor_id = pdev->vendor;\n\thw->device_id = pdev->device;\n\thw->subsystem_vendor_id = pdev->subsystem_vendor;\n\thw->subsystem_device_id = pdev->subsystem_device;\n\n\tpci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);\n\n\tpci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);\n\n\t/* set default ring sizes */\n\tadapter->tx_ring_count = IGB_DEFAULT_TXD;\n\tadapter->rx_ring_count = IGB_DEFAULT_RXD;\n\n\t/* set default work limits */\n\tadapter->tx_work_limit = IGB_DEFAULT_TX_WORK;\n\n\tadapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +\n\t\t\t\t\t VLAN_HLEN;\n\n\t/* Initialize the hardware-specific values */\n\tif (e1000_setup_init_funcs(hw, TRUE)) {\n\t\tdev_err(pci_dev_to_dev(pdev), \"Hardware Initialization Failure\\n\");\n\t\treturn -EIO;\n\t}\n\n\tadapter->mac_table = kzalloc(sizeof(struct igb_mac_addr) *\n\t\t\t\t hw->mac.rar_entry_count,\n\t\t\t\t GFP_ATOMIC);\n\n\t/* Setup and initialize a copy of the hw vlan table array */\n\tadapter->shadow_vfta = kzalloc(sizeof(u32) * E1000_VFTA_ENTRIES,\n\t\t\t\t GFP_ATOMIC);\n#ifdef NO_KNI\n\t/* These calls may decrease the number of queues */\n\tif (hw->mac.type < e1000_i210) {\n\t\tigb_set_sriov_capability(adapter);\n\t}\n\n\tif (igb_init_interrupt_scheme(adapter, true)) {\n\t\tdev_err(pci_dev_to_dev(pdev), \"Unable to allocate memory for queues\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\t/* Explicitly disable IRQ since the NIC can be in any state. */\n\tigb_irq_disable(adapter);\n\n\tset_bit(__IGB_DOWN, &adapter->state);\n#endif\n\treturn 0;\n}\n\n/**\n * igb_open - Called when a network interface is made active\n * @netdev: network interface device structure\n *\n * Returns 0 on success, negative value on failure\n *\n * The open entry point is called when a network interface is made\n * active by the system (IFF_UP). At this point all resources needed\n * for transmit and receive operations are allocated, the interrupt\n * handler is registered with the OS, the watchdog timer is started,\n * and the stack is notified that the interface is ready.\n **/\nstatic int __igb_open(struct net_device *netdev, bool resuming)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n#ifdef CONFIG_PM_RUNTIME\n\tstruct pci_dev *pdev = adapter->pdev;\n#endif /* CONFIG_PM_RUNTIME */\n\tint err;\n\tint i;\n\n\t/* disallow open during test */\n\tif (test_bit(__IGB_TESTING, &adapter->state)) {\n\t\tWARN_ON(resuming);\n\t\treturn -EBUSY;\n\t}\n\n#ifdef CONFIG_PM_RUNTIME\n\tif (!resuming)\n\t\tpm_runtime_get_sync(&pdev->dev);\n#endif /* CONFIG_PM_RUNTIME */\n\n\tnetif_carrier_off(netdev);\n\n\t/* allocate transmit descriptors */\n\terr = igb_setup_all_tx_resources(adapter);\n\tif (err)\n\t\tgoto err_setup_tx;\n\n\t/* allocate receive descriptors */\n\terr = igb_setup_all_rx_resources(adapter);\n\tif (err)\n\t\tgoto err_setup_rx;\n\n\tigb_power_up_link(adapter);\n\n\t/* before we allocate an interrupt, we must be ready to handle it.\n\t * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt\n\t * as soon as we call pci_request_irq, so we have to setup our\n\t * clean_rx handler before we do so. */\n\tigb_configure(adapter);\n\n\terr = igb_request_irq(adapter);\n\tif (err)\n\t\tgoto err_req_irq;\n\n\t/* Notify the stack of the actual queue counts. */\n\tnetif_set_real_num_tx_queues(netdev,\n\t\t\t\t adapter->vmdq_pools ? 1 :\n\t\t\t\t adapter->num_tx_queues);\n\n\terr = netif_set_real_num_rx_queues(netdev,\n\t\t\t\t\t adapter->vmdq_pools ? 1 :\n\t\t\t\t\t adapter->num_rx_queues);\n\tif (err)\n\t\tgoto err_set_queues;\n\n\t/* From here on the code is the same as igb_up() */\n\tclear_bit(__IGB_DOWN, &adapter->state);\n\n\tfor (i = 0; i < adapter->num_q_vectors; i++)\n\t\tnapi_enable(&(adapter->q_vector[i]->napi));\n\tigb_configure_lli(adapter);\n\n\t/* Clear any pending interrupts. */\n\tE1000_READ_REG(hw, E1000_ICR);\n\n\tigb_irq_enable(adapter);\n\n\t/* notify VFs that reset has been completed */\n\tif (adapter->vfs_allocated_count) {\n\t\tu32 reg_data = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\treg_data |= E1000_CTRL_EXT_PFRSTD;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL_EXT, reg_data);\n\t}\n\n\tnetif_tx_start_all_queues(netdev);\n\n\tif (adapter->flags & IGB_FLAG_DETECT_BAD_DMA)\n\t\tschedule_work(&adapter->dma_err_task);\n\n\t/* start the watchdog. */\n\thw->mac.get_link_status = 1;\n\tschedule_work(&adapter->watchdog_task);\n\n\treturn E1000_SUCCESS;\n\nerr_set_queues:\n\tigb_free_irq(adapter);\nerr_req_irq:\n\tigb_release_hw_control(adapter);\n\tigb_power_down_link(adapter);\n\tigb_free_all_rx_resources(adapter);\nerr_setup_rx:\n\tigb_free_all_tx_resources(adapter);\nerr_setup_tx:\n\tigb_reset(adapter);\n\n#ifdef CONFIG_PM_RUNTIME\n\tif (!resuming)\n\t\tpm_runtime_put(&pdev->dev);\n#endif /* CONFIG_PM_RUNTIME */\n\n\treturn err;\n}\n\nstatic int igb_open(struct net_device *netdev)\n{\n\treturn __igb_open(netdev, false);\n}\n\n/**\n * igb_close - Disables a network interface\n * @netdev: network interface device structure\n *\n * Returns 0, this is not allowed to fail\n *\n * The close entry point is called when an interface is de-activated\n * by the OS. The hardware is still under the driver's control, but\n * needs to be disabled. A global MAC reset is issued to stop the\n * hardware, and all transmit and receive resources are freed.\n **/\nstatic int __igb_close(struct net_device *netdev, bool suspending)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n#ifdef CONFIG_PM_RUNTIME\n\tstruct pci_dev *pdev = adapter->pdev;\n#endif /* CONFIG_PM_RUNTIME */\n\n\tWARN_ON(test_bit(__IGB_RESETTING, &adapter->state));\n\n#ifdef CONFIG_PM_RUNTIME\n\tif (!suspending)\n\t\tpm_runtime_get_sync(&pdev->dev);\n#endif /* CONFIG_PM_RUNTIME */\n\n\tigb_down(adapter);\n\n\tigb_release_hw_control(adapter);\n\n\tigb_free_irq(adapter);\n\n\tigb_free_all_tx_resources(adapter);\n\tigb_free_all_rx_resources(adapter);\n\n#ifdef CONFIG_PM_RUNTIME\n\tif (!suspending)\n\t\tpm_runtime_put_sync(&pdev->dev);\n#endif /* CONFIG_PM_RUNTIME */\n\n\treturn 0;\n}\n\nstatic int igb_close(struct net_device *netdev)\n{\n\treturn __igb_close(netdev, false);\n}\n\n/**\n * igb_setup_tx_resources - allocate Tx resources (Descriptors)\n * @tx_ring: tx descriptor ring (for a specific queue) to setup\n *\n * Return 0 on success, negative on failure\n **/\nint igb_setup_tx_resources(struct igb_ring *tx_ring)\n{\n\tstruct device *dev = tx_ring->dev;\n\tint size;\n\n\tsize = sizeof(struct igb_tx_buffer) * tx_ring->count;\n\ttx_ring->tx_buffer_info = vzalloc(size);\n\tif (!tx_ring->tx_buffer_info)\n\t\tgoto err;\n\n\t/* round up to nearest 4K */\n\ttx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);\n\ttx_ring->size = ALIGN(tx_ring->size, 4096);\n\n\ttx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,\n\t\t\t\t\t &tx_ring->dma, GFP_KERNEL);\n\n\tif (!tx_ring->desc)\n\t\tgoto err;\n\n\ttx_ring->next_to_use = 0;\n\ttx_ring->next_to_clean = 0;\n\n\treturn 0;\n\nerr:\n\tvfree(tx_ring->tx_buffer_info);\n\tdev_err(dev,\n\t\t\"Unable to allocate memory for the transmit descriptor ring\\n\");\n\treturn -ENOMEM;\n}\n\n/**\n * igb_setup_all_tx_resources - wrapper to allocate Tx resources\n *\t\t\t\t (Descriptors) for all queues\n * @adapter: board private structure\n *\n * Return 0 on success, negative on failure\n **/\nstatic int igb_setup_all_tx_resources(struct igb_adapter *adapter)\n{\n\tstruct pci_dev *pdev = adapter->pdev;\n\tint i, err = 0;\n\n\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\terr = igb_setup_tx_resources(adapter->tx_ring[i]);\n\t\tif (err) {\n\t\t\tdev_err(pci_dev_to_dev(pdev),\n\t\t\t\t\"Allocation for Tx Queue %u failed\\n\", i);\n\t\t\tfor (i--; i >= 0; i--)\n\t\t\t\tigb_free_tx_resources(adapter->tx_ring[i]);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn err;\n}\n\n/**\n * igb_setup_tctl - configure the transmit control registers\n * @adapter: Board private structure\n **/\nvoid igb_setup_tctl(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 tctl;\n\n\t/* disable queue 0 which is enabled by default on 82575 and 82576 */\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(0), 0);\n\n\t/* Program the Transmit Control Register */\n\ttctl = E1000_READ_REG(hw, E1000_TCTL);\n\ttctl &= ~E1000_TCTL_CT;\n\ttctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |\n\t\t(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);\n\n\te1000_config_collision_dist(hw);\n\n\t/* Enable transmits */\n\ttctl |= E1000_TCTL_EN;\n\n\tE1000_WRITE_REG(hw, E1000_TCTL, tctl);\n}\n\nstatic u32 igb_tx_wthresh(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tswitch (hw->mac.type) {\n\tcase e1000_i354:\n\t\treturn 4;\n\tcase e1000_82576:\n\t\tif (adapter->msix_entries)\n\t\t\treturn 1;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn 16;\n}\n\n/**\n * igb_configure_tx_ring - Configure transmit ring after Reset\n * @adapter: board private structure\n * @ring: tx ring to configure\n *\n * Configure a transmit ring after a reset.\n **/\nvoid igb_configure_tx_ring(struct igb_adapter *adapter,\n struct igb_ring *ring)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 txdctl = 0;\n\tu64 tdba = ring->dma;\n\tint reg_idx = ring->reg_idx;\n\n\t/* disable the queue */\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(reg_idx), 0);\n\tE1000_WRITE_FLUSH(hw);\n\tmdelay(10);\n\n\tE1000_WRITE_REG(hw, E1000_TDLEN(reg_idx),\n\t ring->count * sizeof(union e1000_adv_tx_desc));\n\tE1000_WRITE_REG(hw, E1000_TDBAL(reg_idx),\n\t tdba & 0x00000000ffffffffULL);\n\tE1000_WRITE_REG(hw, E1000_TDBAH(reg_idx), tdba >> 32);\n\n\tring->tail = hw->hw_addr + E1000_TDT(reg_idx);\n\tE1000_WRITE_REG(hw, E1000_TDH(reg_idx), 0);\n\twritel(0, ring->tail);\n\n\ttxdctl |= IGB_TX_PTHRESH;\n\ttxdctl |= IGB_TX_HTHRESH << 8;\n\ttxdctl |= igb_tx_wthresh(adapter) << 16;\n\n\ttxdctl |= E1000_TXDCTL_QUEUE_ENABLE;\n\tE1000_WRITE_REG(hw, E1000_TXDCTL(reg_idx), txdctl);\n}\n\n/**\n * igb_configure_tx - Configure transmit Unit after Reset\n * @adapter: board private structure\n *\n * Configure the Tx unit of the MAC after a reset.\n **/\nstatic void igb_configure_tx(struct igb_adapter *adapter)\n{\n\tint i;\n\n\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\tigb_configure_tx_ring(adapter, adapter->tx_ring[i]);\n}\n\n/**\n * igb_setup_rx_resources - allocate Rx resources (Descriptors)\n * @rx_ring: rx descriptor ring (for a specific queue) to setup\n *\n * Returns 0 on success, negative on failure\n **/\nint igb_setup_rx_resources(struct igb_ring *rx_ring)\n{\n\tstruct device *dev = rx_ring->dev;\n\tint size, desc_len;\n\n\tsize = sizeof(struct igb_rx_buffer) * rx_ring->count;\n\trx_ring->rx_buffer_info = vzalloc(size);\n\tif (!rx_ring->rx_buffer_info)\n\t\tgoto err;\n\n\tdesc_len = sizeof(union e1000_adv_rx_desc);\n\n\t/* Round up to nearest 4K */\n\trx_ring->size = rx_ring->count * desc_len;\n\trx_ring->size = ALIGN(rx_ring->size, 4096);\n\n\trx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,\n\t\t\t\t\t &rx_ring->dma, GFP_KERNEL);\n\n\tif (!rx_ring->desc)\n\t\tgoto err;\n\n\trx_ring->next_to_alloc = 0;\n\trx_ring->next_to_clean = 0;\n\trx_ring->next_to_use = 0;\n\n\treturn 0;\n\nerr:\n\tvfree(rx_ring->rx_buffer_info);\n\trx_ring->rx_buffer_info = NULL;\n\tdev_err(dev, \"Unable to allocate memory for the receive descriptor\"\n\t\t\" ring\\n\");\n\treturn -ENOMEM;\n}\n\n/**\n * igb_setup_all_rx_resources - wrapper to allocate Rx resources\n *\t\t\t\t (Descriptors) for all queues\n * @adapter: board private structure\n *\n * Return 0 on success, negative on failure\n **/\nstatic int igb_setup_all_rx_resources(struct igb_adapter *adapter)\n{\n\tstruct pci_dev *pdev = adapter->pdev;\n\tint i, err = 0;\n\n\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\terr = igb_setup_rx_resources(adapter->rx_ring[i]);\n\t\tif (err) {\n\t\t\tdev_err(pci_dev_to_dev(pdev),\n\t\t\t\t\"Allocation for Rx Queue %u failed\\n\", i);\n\t\t\tfor (i--; i >= 0; i--)\n\t\t\t\tigb_free_rx_resources(adapter->rx_ring[i]);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn err;\n}\n\n/**\n * igb_setup_mrqc - configure the multiple receive queue control registers\n * @adapter: Board private structure\n **/\nstatic void igb_setup_mrqc(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 mrqc, rxcsum;\n\tu32 j, num_rx_queues, shift = 0, shift2 = 0;\n\tstatic const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,\n\t\t\t\t\t0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,\n\t\t\t\t\t0xA32DCB77, 0x0CF23080, 0x3BB7426A,\n\t\t\t\t\t0xFA01ACBE };\n\n\t/* Fill out hash function seeds */\n\tfor (j = 0; j < 10; j++)\n\t\tE1000_WRITE_REG(hw, E1000_RSSRK(j), rsskey[j]);\n\n\tnum_rx_queues = adapter->rss_queues;\n\n\t/* 82575 and 82576 supports 2 RSS queues for VMDq */\n\tswitch (hw->mac.type) {\n\tcase e1000_82575:\n\t\tif (adapter->vmdq_pools) {\n\t\t\tshift = 2;\n\t\t\tshift2 = 6;\n\t\t\tbreak;\n\t\t}\n\t\tshift = 6;\n\t\tbreak;\n\tcase e1000_82576:\n\t\t/* 82576 supports 2 RSS queues for SR-IOV */\n\t\tif (adapter->vfs_allocated_count || adapter->vmdq_pools) {\n\t\t\tshift = 3;\n\t\t\tnum_rx_queues = 2;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/*\n\t * Populate the redirection table 4 entries at a time. To do this\n\t * we are generating the results for n and n+2 and then interleaving\n\t * those with the results with n+1 and n+3.\n\t */\n\tfor (j = 0; j < 32; j++) {\n\t\t/* first pass generates n and n+2 */\n\t\tu32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;\n\t\tu32 reta = (base & 0x07800780) >> (7 - shift);\n\n\t\t/* second pass generates n+1 and n+3 */\n\t\tbase += 0x00010001 * num_rx_queues;\n\t\treta |= (base & 0x07800780) << (1 + shift);\n\n\t\t/* generate 2nd table for 82575 based parts */\n\t\tif (shift2)\n\t\t\treta |= (0x01010101 * num_rx_queues) << shift2;\n\n\t\tE1000_WRITE_REG(hw, E1000_RETA(j), reta);\n\t}\n\n\t/*\n\t * Disable raw packet checksumming so that RSS hash is placed in\n\t * descriptor on writeback. No need to enable TCP/UDP/IP checksum\n\t * offloads as they are enabled by default\n\t */\n\trxcsum = E1000_READ_REG(hw, E1000_RXCSUM);\n\trxcsum |= E1000_RXCSUM_PCSD;\n\n\tif (adapter->hw.mac.type >= e1000_82576)\n\t\t/* Enable Receive Checksum Offload for SCTP */\n\t\trxcsum |= E1000_RXCSUM_CRCOFL;\n\n\t/* Don't need to set TUOFL or IPOFL, they default to 1 */\n\tE1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);\n\n\t/* Generate RSS hash based on packet types, TCP/UDP\n\t * port numbers and/or IPv4/v6 src and dst addresses\n\t */\n\tmrqc = E1000_MRQC_RSS_FIELD_IPV4 |\n\t E1000_MRQC_RSS_FIELD_IPV4_TCP |\n\t E1000_MRQC_RSS_FIELD_IPV6 |\n\t E1000_MRQC_RSS_FIELD_IPV6_TCP |\n\t E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;\n\n\tif (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)\n\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;\n\tif (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)\n\t\tmrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;\n\n\t/* If VMDq is enabled then we set the appropriate mode for that, else\n\t * we default to RSS so that an RSS hash is calculated per packet even\n\t * if we are only using one queue */\n\tif (adapter->vfs_allocated_count || adapter->vmdq_pools) {\n\t\tif (hw->mac.type > e1000_82575) {\n\t\t\t/* Set the default pool for the PF's first queue */\n\t\t\tu32 vtctl = E1000_READ_REG(hw, E1000_VT_CTL);\n\t\t\tvtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |\n\t\t\t\t E1000_VT_CTL_DISABLE_DEF_POOL);\n\t\t\tvtctl |= adapter->vfs_allocated_count <<\n\t\t\t\tE1000_VT_CTL_DEFAULT_POOL_SHIFT;\n\t\t\tE1000_WRITE_REG(hw, E1000_VT_CTL, vtctl);\n\t\t} else if (adapter->rss_queues > 1) {\n\t\t\t/* set default queue for pool 1 to queue 2 */\n\t\t\tE1000_WRITE_REG(hw, E1000_VT_CTL,\n\t\t\t\t adapter->rss_queues << 7);\n\t\t}\n\t\tif (adapter->rss_queues > 1)\n\t\t\tmrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;\n\t\telse\n\t\t\tmrqc |= E1000_MRQC_ENABLE_VMDQ;\n\t} else {\n\t\tmrqc |= E1000_MRQC_ENABLE_RSS_4Q;\n\t}\n\tigb_vmm_control(adapter);\n\n\tE1000_WRITE_REG(hw, E1000_MRQC, mrqc);\n}\n\n/**\n * igb_setup_rctl - configure the receive control registers\n * @adapter: Board private structure\n **/\nvoid igb_setup_rctl(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 rctl;\n\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\n\trctl &= ~(3 << E1000_RCTL_MO_SHIFT);\n\trctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);\n\n\trctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |\n\t\t(hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);\n\n\t/*\n\t * enable stripping of CRC. It's unlikely this will break BMC\n\t * redirection as it did with e1000. Newer features require\n\t * that the HW strips the CRC.\n\t */\n\trctl |= E1000_RCTL_SECRC;\n\n\t/* disable store bad packets and clear size bits. */\n\trctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);\n\n\t/* enable LPE to prevent packets larger than max_frame_size */\n\trctl |= E1000_RCTL_LPE;\n\n\t/* disable queue 0 to prevent tail write w/o re-config */\n\tE1000_WRITE_REG(hw, E1000_RXDCTL(0), 0);\n\n\t/* Attention!!! For SR-IOV PF driver operations you must enable\n\t * queue drop for all VF and PF queues to prevent head of line blocking\n\t * if an un-trusted VF does not provide descriptors to hardware.\n\t */\n\tif (adapter->vfs_allocated_count) {\n\t\t/* set all queue drop enable bits */\n\t\tE1000_WRITE_REG(hw, E1000_QDE, ALL_QUEUES);\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n}\n\nstatic inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,\n int vfn)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 vmolr;\n\n\t/* if it isn't the PF check to see if VFs are enabled and\n\t * increase the size to support vlan tags */\n\tif (vfn < adapter->vfs_allocated_count &&\n\t adapter->vf_data[vfn].vlans_enabled)\n\t\tsize += VLAN_HLEN;\n\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n\tif (vfn >= adapter->vfs_allocated_count) {\n\t\tint queue = vfn - adapter->vfs_allocated_count;\n\t\tstruct igb_vmdq_adapter *vadapter;\n\n\t\tvadapter = netdev_priv(adapter->vmdq_netdev[queue-1]);\n\t\tif (vadapter->vlgrp)\n\t\t\tsize += VLAN_HLEN;\n\t}\n#endif\n\tvmolr = E1000_READ_REG(hw, E1000_VMOLR(vfn));\n\tvmolr &= ~E1000_VMOLR_RLPML_MASK;\n\tvmolr |= size | E1000_VMOLR_LPE;\n\tE1000_WRITE_REG(hw, E1000_VMOLR(vfn), vmolr);\n\n\treturn 0;\n}\n\n/**\n * igb_rlpml_set - set maximum receive packet size\n * @adapter: board private structure\n *\n * Configure maximum receivable packet size.\n **/\nstatic void igb_rlpml_set(struct igb_adapter *adapter)\n{\n\tu32 max_frame_size = adapter->max_frame_size;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu16 pf_id = adapter->vfs_allocated_count;\n\n\tif (adapter->vmdq_pools && hw->mac.type != e1000_82575) {\n\t\tint i;\n\t\tfor (i = 0; i < adapter->vmdq_pools; i++)\n\t\t\tigb_set_vf_rlpml(adapter, max_frame_size, pf_id + i);\n\t\t/*\n\t\t * If we're in VMDQ or SR-IOV mode, then set global RLPML\n\t\t * to our max jumbo frame size, in case we need to enable\n\t\t * jumbo frames on one of the rings later.\n\t\t * This will not pass over-length frames into the default\n\t\t * queue because it's gated by the VMOLR.RLPML.\n\t\t */\n\t\tmax_frame_size = MAX_JUMBO_FRAME_SIZE;\n\t}\n\t/* Set VF RLPML for the PF device. */\n\tif (adapter->vfs_allocated_count)\n\t\tigb_set_vf_rlpml(adapter, max_frame_size, pf_id);\n\n\tE1000_WRITE_REG(hw, E1000_RLPML, max_frame_size);\n}\n\nstatic inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,\n\t\t\t\t\tint vfn, bool enable)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 val;\n\tvoid __iomem *reg;\n\n\tif (hw->mac.type < e1000_82576)\n\t\treturn;\n\n\tif (hw->mac.type == e1000_i350)\n\t\treg = hw->hw_addr + E1000_DVMOLR(vfn);\n\telse\n\t\treg = hw->hw_addr + E1000_VMOLR(vfn);\n\n\tval = readl(reg);\n\tif (enable)\n\t\tval |= E1000_VMOLR_STRVLAN;\n\telse\n\t\tval &= ~(E1000_VMOLR_STRVLAN);\n\twritel(val, reg);\n}\nstatic inline void igb_set_vmolr(struct igb_adapter *adapter,\n\t\t\t\t int vfn, bool aupe)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 vmolr;\n\n\t/*\n\t * This register exists only on 82576 and newer so if we are older then\n\t * we should exit and do nothing\n\t */\n\tif (hw->mac.type < e1000_82576)\n\t\treturn;\n\n\tvmolr = E1000_READ_REG(hw, E1000_VMOLR(vfn));\n\n\tif (aupe)\n\t\tvmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */\n\telse\n\t\tvmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */\n\n\t/* clear all bits that might not be set */\n\tvmolr &= ~E1000_VMOLR_RSSE;\n\n\tif (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)\n\t\tvmolr |= E1000_VMOLR_RSSE; /* enable RSS */\n\n\tvmolr |= E1000_VMOLR_BAM;\t /* Accept broadcast */\n\tvmolr |= E1000_VMOLR_LPE;\t /* Accept long packets */\n\n\tE1000_WRITE_REG(hw, E1000_VMOLR(vfn), vmolr);\n}\n\n/**\n * igb_configure_rx_ring - Configure a receive ring after Reset\n * @adapter: board private structure\n * @ring: receive ring to be configured\n *\n * Configure the Rx unit of the MAC after a reset.\n **/\nvoid igb_configure_rx_ring(struct igb_adapter *adapter,\n struct igb_ring *ring)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu64 rdba = ring->dma;\n\tint reg_idx = ring->reg_idx;\n\tu32 srrctl = 0, rxdctl = 0;\n\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\t/*\n\t * RLPML prevents us from receiving a frame larger than max_frame so\n\t * it is safe to just set the rx_buffer_len to max_frame without the\n\t * risk of an skb over panic.\n\t */\n\tring->rx_buffer_len = max_t(u32, adapter->max_frame_size,\n\t\t\t\t MAXIMUM_ETHERNET_VLAN_SIZE);\n\n#endif\n\t/* disable the queue */\n\tE1000_WRITE_REG(hw, E1000_RXDCTL(reg_idx), 0);\n\n\t/* Set DMA base address registers */\n\tE1000_WRITE_REG(hw, E1000_RDBAL(reg_idx),\n\t rdba & 0x00000000ffffffffULL);\n\tE1000_WRITE_REG(hw, E1000_RDBAH(reg_idx), rdba >> 32);\n\tE1000_WRITE_REG(hw, E1000_RDLEN(reg_idx),\n\t ring->count * sizeof(union e1000_adv_rx_desc));\n\n\t/* initialize head and tail */\n\tring->tail = hw->hw_addr + E1000_RDT(reg_idx);\n\tE1000_WRITE_REG(hw, E1000_RDH(reg_idx), 0);\n\twritel(0, ring->tail);\n\n\t/* reset next-to- use/clean to place SW in sync with hardwdare */\n\tring->next_to_clean = 0;\n\tring->next_to_use = 0;\n#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\tring->next_to_alloc = 0;\n\n#endif\n\t/* set descriptor configuration */\n#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\tsrrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;\n\tsrrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;\n#else /* CONFIG_IGB_DISABLE_PACKET_SPLIT */\n\tsrrctl = ALIGN(ring->rx_buffer_len, 1024) >>\n\t E1000_SRRCTL_BSIZEPKT_SHIFT;\n#endif /* CONFIG_IGB_DISABLE_PACKET_SPLIT */\n\tsrrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;\n#ifdef HAVE_PTP_1588_CLOCK\n\tif (hw->mac.type >= e1000_82580)\n\t\tsrrctl |= E1000_SRRCTL_TIMESTAMP;\n#endif /* HAVE_PTP_1588_CLOCK */\n\t/*\n\t * We should set the drop enable bit if:\n\t * SR-IOV is enabled\n\t * or\n\t * Flow Control is disabled and number of RX queues > 1\n\t *\n\t * This allows us to avoid head of line blocking for security\n\t * and performance reasons.\n\t */\n\tif (adapter->vfs_allocated_count ||\n\t (adapter->num_rx_queues > 1 &&\n\t (hw->fc.requested_mode == e1000_fc_none ||\n\t hw->fc.requested_mode == e1000_fc_rx_pause)))\n\t\tsrrctl |= E1000_SRRCTL_DROP_EN;\n\n\tE1000_WRITE_REG(hw, E1000_SRRCTL(reg_idx), srrctl);\n\n\t/* set filtering for VMDQ pools */\n\tigb_set_vmolr(adapter, reg_idx & 0x7, true);\n\n\trxdctl |= IGB_RX_PTHRESH;\n\trxdctl |= IGB_RX_HTHRESH << 8;\n\trxdctl |= IGB_RX_WTHRESH << 16;\n\n\t/* enable receive descriptor fetching */\n\trxdctl |= E1000_RXDCTL_QUEUE_ENABLE;\n\tE1000_WRITE_REG(hw, E1000_RXDCTL(reg_idx), rxdctl);\n}\n\n/**\n * igb_configure_rx - Configure receive Unit after Reset\n * @adapter: board private structure\n *\n * Configure the Rx unit of the MAC after a reset.\n **/\nstatic void igb_configure_rx(struct igb_adapter *adapter)\n{\n\tint i;\n\n\t/* set UTA to appropriate mode */\n\tigb_set_uta(adapter);\n\n\tigb_full_sync_mac_table(adapter);\n\t/* Setup the HW Rx Head and Tail Descriptor Pointers and\n\t * the Base and Length of the Rx Descriptor Ring */\n\tfor (i = 0; i < adapter->num_rx_queues; i++)\n\t\tigb_configure_rx_ring(adapter, adapter->rx_ring[i]);\n}\n\n/**\n * igb_free_tx_resources - Free Tx Resources per Queue\n * @tx_ring: Tx descriptor ring for a specific queue\n *\n * Free all transmit software resources\n **/\nvoid igb_free_tx_resources(struct igb_ring *tx_ring)\n{\n\tigb_clean_tx_ring(tx_ring);\n\n\tvfree(tx_ring->tx_buffer_info);\n\ttx_ring->tx_buffer_info = NULL;\n\n\t/* if not set, then don't free */\n\tif (!tx_ring->desc)\n\t\treturn;\n\n\tdma_free_coherent(tx_ring->dev, tx_ring->size,\n\t\t\t tx_ring->desc, tx_ring->dma);\n\n\ttx_ring->desc = NULL;\n}\n\n/**\n * igb_free_all_tx_resources - Free Tx Resources for All Queues\n * @adapter: board private structure\n *\n * Free all transmit software resources\n **/\nstatic void igb_free_all_tx_resources(struct igb_adapter *adapter)\n{\n\tint i;\n\n\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\tigb_free_tx_resources(adapter->tx_ring[i]);\n}\n\nvoid igb_unmap_and_free_tx_resource(struct igb_ring *ring,\n\t\t\t\t struct igb_tx_buffer *tx_buffer)\n{\n\tif (tx_buffer->skb) {\n\t\tdev_kfree_skb_any(tx_buffer->skb);\n\t\tif (dma_unmap_len(tx_buffer, len))\n\t\t\tdma_unmap_single(ring->dev,\n\t\t\t dma_unmap_addr(tx_buffer, dma),\n\t\t\t dma_unmap_len(tx_buffer, len),\n\t\t\t DMA_TO_DEVICE);\n\t} else if (dma_unmap_len(tx_buffer, len)) {\n\t\tdma_unmap_page(ring->dev,\n\t\t dma_unmap_addr(tx_buffer, dma),\n\t\t dma_unmap_len(tx_buffer, len),\n\t\t DMA_TO_DEVICE);\n\t}\n\ttx_buffer->next_to_watch = NULL;\n\ttx_buffer->skb = NULL;\n\tdma_unmap_len_set(tx_buffer, len, 0);\n\t/* buffer_info must be completely set up in the transmit path */\n}\n\n/**\n * igb_clean_tx_ring - Free Tx Buffers\n * @tx_ring: ring to be cleaned\n **/\nstatic void igb_clean_tx_ring(struct igb_ring *tx_ring)\n{\n\tstruct igb_tx_buffer *buffer_info;\n\tunsigned long size;\n\tu16 i;\n\n\tif (!tx_ring->tx_buffer_info)\n\t\treturn;\n\t/* Free all the Tx ring sk_buffs */\n\n\tfor (i = 0; i < tx_ring->count; i++) {\n\t\tbuffer_info = &tx_ring->tx_buffer_info[i];\n\t\tigb_unmap_and_free_tx_resource(tx_ring, buffer_info);\n\t}\n\n\tnetdev_tx_reset_queue(txring_txq(tx_ring));\n\n\tsize = sizeof(struct igb_tx_buffer) * tx_ring->count;\n\tmemset(tx_ring->tx_buffer_info, 0, size);\n\n\t/* Zero out the descriptor ring */\n\tmemset(tx_ring->desc, 0, tx_ring->size);\n\n\ttx_ring->next_to_use = 0;\n\ttx_ring->next_to_clean = 0;\n}\n\n/**\n * igb_clean_all_tx_rings - Free Tx Buffers for all queues\n * @adapter: board private structure\n **/\nstatic void igb_clean_all_tx_rings(struct igb_adapter *adapter)\n{\n\tint i;\n\n\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\tigb_clean_tx_ring(adapter->tx_ring[i]);\n}\n\n/**\n * igb_free_rx_resources - Free Rx Resources\n * @rx_ring: ring to clean the resources from\n *\n * Free all receive software resources\n **/\nvoid igb_free_rx_resources(struct igb_ring *rx_ring)\n{\n\tigb_clean_rx_ring(rx_ring);\n\n\tvfree(rx_ring->rx_buffer_info);\n\trx_ring->rx_buffer_info = NULL;\n\n\t/* if not set, then don't free */\n\tif (!rx_ring->desc)\n\t\treturn;\n\n\tdma_free_coherent(rx_ring->dev, rx_ring->size,\n\t\t\t rx_ring->desc, rx_ring->dma);\n\n\trx_ring->desc = NULL;\n}\n\n/**\n * igb_free_all_rx_resources - Free Rx Resources for All Queues\n * @adapter: board private structure\n *\n * Free all receive software resources\n **/\nstatic void igb_free_all_rx_resources(struct igb_adapter *adapter)\n{\n\tint i;\n\n\tfor (i = 0; i < adapter->num_rx_queues; i++)\n\t\tigb_free_rx_resources(adapter->rx_ring[i]);\n}\n\n/**\n * igb_clean_rx_ring - Free Rx Buffers per Queue\n * @rx_ring: ring to free buffers from\n **/\nvoid igb_clean_rx_ring(struct igb_ring *rx_ring)\n{\n\tunsigned long size;\n\tu16 i;\n\n\tif (!rx_ring->rx_buffer_info)\n\t\treturn;\n\n#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\tif (rx_ring->skb)\n\t\tdev_kfree_skb(rx_ring->skb);\n\trx_ring->skb = NULL;\n\n#endif\n\t/* Free all the Rx ring sk_buffs */\n\tfor (i = 0; i < rx_ring->count; i++) {\n\t\tstruct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\t\tif (buffer_info->dma) {\n\t\t\tdma_unmap_single(rx_ring->dev,\n\t\t\t buffer_info->dma,\n\t\t\t\t\t rx_ring->rx_buffer_len,\n\t\t\t\t\t DMA_FROM_DEVICE);\n\t\t\tbuffer_info->dma = 0;\n\t\t}\n\n\t\tif (buffer_info->skb) {\n\t\t\tdev_kfree_skb(buffer_info->skb);\n\t\t\tbuffer_info->skb = NULL;\n\t\t}\n#else\n\t\tif (!buffer_info->page)\n\t\t\tcontinue;\n\n\t\tdma_unmap_page(rx_ring->dev,\n\t\t\t buffer_info->dma,\n\t\t\t PAGE_SIZE,\n\t\t\t DMA_FROM_DEVICE);\n\t\t__free_page(buffer_info->page);\n\n\t\tbuffer_info->page = NULL;\n#endif\n\t}\n\n\tsize = sizeof(struct igb_rx_buffer) * rx_ring->count;\n\tmemset(rx_ring->rx_buffer_info, 0, size);\n\n\t/* Zero out the descriptor ring */\n\tmemset(rx_ring->desc, 0, rx_ring->size);\n\n\trx_ring->next_to_alloc = 0;\n\trx_ring->next_to_clean = 0;\n\trx_ring->next_to_use = 0;\n}\n\n/**\n * igb_clean_all_rx_rings - Free Rx Buffers for all queues\n * @adapter: board private structure\n **/\nstatic void igb_clean_all_rx_rings(struct igb_adapter *adapter)\n{\n\tint i;\n\n\tfor (i = 0; i < adapter->num_rx_queues; i++)\n\t\tigb_clean_rx_ring(adapter->rx_ring[i]);\n}\n\n/**\n * igb_set_mac - Change the Ethernet Address of the NIC\n * @netdev: network interface device structure\n * @p: pointer to an address structure\n *\n * Returns 0 on success, negative on failure\n **/\nstatic int igb_set_mac(struct net_device *netdev, void *p)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct sockaddr *addr = p;\n\n\tif (!is_valid_ether_addr(addr->sa_data))\n\t\treturn -EADDRNOTAVAIL;\n\n\tigb_del_mac_filter(adapter, hw->mac.addr,\n\t\t\t adapter->vfs_allocated_count);\n\tmemcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);\n\tmemcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);\n\n\t/* set the correct pool for the new PF MAC address in entry 0 */\n\treturn igb_add_mac_filter(adapter, hw->mac.addr,\n\t adapter->vfs_allocated_count);\n}\n\n/**\n * igb_write_mc_addr_list - write multicast addresses to MTA\n * @netdev: network interface device structure\n *\n * Writes multicast address list to the MTA hash table.\n * Returns: -ENOMEM on failure\n * 0 on no addresses written\n * X on writing X addresses to MTA\n **/\nint igb_write_mc_addr_list(struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n#ifdef NETDEV_HW_ADDR_T_MULTICAST\n\tstruct netdev_hw_addr *ha;\n#else\n\tstruct dev_mc_list *ha;\n#endif\n\tu8 *mta_list;\n\tint i, count;\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n\tint vm;\n#endif\n\tcount = netdev_mc_count(netdev);\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n\tfor (vm = 1; vm < adapter->vmdq_pools; vm++) {\n\t\tif (!adapter->vmdq_netdev[vm])\n\t\t\tbreak;\n\t\tif (!netif_running(adapter->vmdq_netdev[vm]))\n\t\t\tcontinue;\n\t\tcount += netdev_mc_count(adapter->vmdq_netdev[vm]);\n\t}\n#endif\n\n\tif (!count) {\n\t\te1000_update_mc_addr_list(hw, NULL, 0);\n\t\treturn 0;\n\t}\n\tmta_list = kzalloc(count * 6, GFP_ATOMIC);\n\tif (!mta_list)\n\t\treturn -ENOMEM;\n\n\t/* The shared function expects a packed array of only addresses. */\n\ti = 0;\n\tnetdev_for_each_mc_addr(ha, netdev)\n#ifdef NETDEV_HW_ADDR_T_MULTICAST\n\t\tmemcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);\n#else\n\t\tmemcpy(mta_list + (i++ * ETH_ALEN), ha->dmi_addr, ETH_ALEN);\n#endif\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n\tfor (vm = 1; vm < adapter->vmdq_pools; vm++) {\n\t\tif (!adapter->vmdq_netdev[vm])\n\t\t\tbreak;\n\t\tif (!netif_running(adapter->vmdq_netdev[vm]) ||\n\t\t !netdev_mc_count(adapter->vmdq_netdev[vm]))\n\t\t\tcontinue;\n\t\tnetdev_for_each_mc_addr(ha, adapter->vmdq_netdev[vm])\n#ifdef NETDEV_HW_ADDR_T_MULTICAST\n\t\t\tmemcpy(mta_list + (i++ * ETH_ALEN),\n\t\t\t ha->addr, ETH_ALEN);\n#else\n\t\t\tmemcpy(mta_list + (i++ * ETH_ALEN),\n\t\t\t ha->dmi_addr, ETH_ALEN);\n#endif\n\t}\n#endif\n\te1000_update_mc_addr_list(hw, mta_list, i);\n\tkfree(mta_list);\n\n\treturn count;\n}\n\nvoid igb_rar_set(struct igb_adapter *adapter, u32 index)\n{\n\tu32 rar_low, rar_high;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu8 *addr = adapter->mac_table[index].addr;\n\t/* HW expects these in little endian so we reverse the byte order\n\t * from network order (big endian) to little endian\n\t */\n\trar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |\n\t ((u32) addr[2] << 16) | ((u32) addr[3] << 24));\n\trar_high = ((u32) addr[4] | ((u32) addr[5] << 8));\n\n\t/* Indicate to hardware the Address is Valid. */\n\tif (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE)\n\t\trar_high |= E1000_RAH_AV;\n\n\tif (hw->mac.type == e1000_82575)\n\t\trar_high |= E1000_RAH_POOL_1 * adapter->mac_table[index].queue;\n\telse\n\t\trar_high |= E1000_RAH_POOL_1 << adapter->mac_table[index].queue;\n\n\tE1000_WRITE_REG(hw, E1000_RAL(index), rar_low);\n\tE1000_WRITE_FLUSH(hw);\n\tE1000_WRITE_REG(hw, E1000_RAH(index), rar_high);\n\tE1000_WRITE_FLUSH(hw);\n}\n\nvoid igb_full_sync_mac_table(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint i;\n\tfor (i = 0; i < hw->mac.rar_entry_count; i++) {\n\t\t\tigb_rar_set(adapter, i);\n\t}\n}\n\nvoid igb_sync_mac_table(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint i;\n\tfor (i = 0; i < hw->mac.rar_entry_count; i++) {\n\t\tif (adapter->mac_table[i].state & IGB_MAC_STATE_MODIFIED)\n\t\t\tigb_rar_set(adapter, i);\n\t\tadapter->mac_table[i].state &= ~(IGB_MAC_STATE_MODIFIED);\n\t}\n}\n\nint igb_available_rars(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint i, count = 0;\n\n\tfor (i = 0; i < hw->mac.rar_entry_count; i++) {\n\t\tif (adapter->mac_table[i].state == 0)\n\t\t\tcount++;\n\t}\n\treturn count;\n}\n\n#ifdef HAVE_SET_RX_MODE\n/**\n * igb_write_uc_addr_list - write unicast addresses to RAR table\n * @netdev: network interface device structure\n *\n * Writes unicast address list to the RAR table.\n * Returns: -ENOMEM on failure/insufficient address space\n * 0 on no addresses written\n * X on writing X addresses to the RAR table\n **/\nstatic int igb_write_uc_addr_list(struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tunsigned int vfn = adapter->vfs_allocated_count;\n\tint count = 0;\n\n\t/* return ENOMEM indicating insufficient memory for addresses */\n\tif (netdev_uc_count(netdev) > igb_available_rars(adapter))\n\t\treturn -ENOMEM;\n\tif (!netdev_uc_empty(netdev)) {\n#ifdef NETDEV_HW_ADDR_T_UNICAST\n\t\tstruct netdev_hw_addr *ha;\n#else\n\t\tstruct dev_mc_list *ha;\n#endif\n\t\tnetdev_for_each_uc_addr(ha, netdev) {\n#ifdef NETDEV_HW_ADDR_T_UNICAST\n\t\t\tigb_del_mac_filter(adapter, ha->addr, vfn);\n\t\t\tigb_add_mac_filter(adapter, ha->addr, vfn);\n#else\n\t\t\tigb_del_mac_filter(adapter, ha->da_addr, vfn);\n\t\t\tigb_add_mac_filter(adapter, ha->da_addr, vfn);\n#endif\n\t\t\tcount++;\n\t\t}\n\t}\n\treturn count;\n}\n\n#endif /* HAVE_SET_RX_MODE */\n/**\n * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set\n * @netdev: network interface device structure\n *\n * The set_rx_mode entry point is called whenever the unicast or multicast\n * address lists or the network interface flags are updated. This routine is\n * responsible for configuring the hardware for proper unicast, multicast,\n * promiscuous mode, and all-multi behavior.\n **/\nstatic void igb_set_rx_mode(struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tunsigned int vfn = adapter->vfs_allocated_count;\n\tu32 rctl, vmolr = 0;\n\tint count;\n\n\t/* Check for Promiscuous and All Multicast modes */\n\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\n\t/* clear the effected bits */\n\trctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);\n\n\tif (netdev->flags & IFF_PROMISC) {\n\t\trctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);\n\t\tvmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);\n\t\t/* retain VLAN HW filtering if in VT mode */\n\t\tif (adapter->vfs_allocated_count || adapter->vmdq_pools)\n\t\t\trctl |= E1000_RCTL_VFE;\n\t} else {\n\t\tif (netdev->flags & IFF_ALLMULTI) {\n\t\t\trctl |= E1000_RCTL_MPE;\n\t\t\tvmolr |= E1000_VMOLR_MPME;\n\t\t} else {\n\t\t\t/*\n\t\t\t * Write addresses to the MTA, if the attempt fails\n\t\t\t * then we should just turn on promiscuous mode so\n\t\t\t * that we can at least receive multicast traffic\n\t\t\t */\n\t\t\tcount = igb_write_mc_addr_list(netdev);\n\t\t\tif (count < 0) {\n\t\t\t\trctl |= E1000_RCTL_MPE;\n\t\t\t\tvmolr |= E1000_VMOLR_MPME;\n\t\t\t} else if (count) {\n\t\t\t\tvmolr |= E1000_VMOLR_ROMPE;\n\t\t\t}\n\t\t}\n#ifdef HAVE_SET_RX_MODE\n\t\t/*\n\t\t * Write addresses to available RAR registers, if there is not\n\t\t * sufficient space to store all the addresses then enable\n\t\t * unicast promiscuous mode\n\t\t */\n\t\tcount = igb_write_uc_addr_list(netdev);\n\t\tif (count < 0) {\n\t\t\trctl |= E1000_RCTL_UPE;\n\t\t\tvmolr |= E1000_VMOLR_ROPE;\n\t\t}\n#endif /* HAVE_SET_RX_MODE */\n\t\trctl |= E1000_RCTL_VFE;\n\t}\n\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\n\t/*\n\t * In order to support SR-IOV and eventually VMDq it is necessary to set\n\t * the VMOLR to enable the appropriate modes. Without this workaround\n\t * we will have issues with VLAN tag stripping not being done for frames\n\t * that are only arriving because we are the default pool\n\t */\n\tif (hw->mac.type < e1000_82576)\n\t\treturn;\n\n\tvmolr |= E1000_READ_REG(hw, E1000_VMOLR(vfn)) &\n\t ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);\n\tE1000_WRITE_REG(hw, E1000_VMOLR(vfn), vmolr);\n\tigb_restore_vf_multicasts(adapter);\n}\n\nstatic void igb_check_wvbr(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 wvbr = 0;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82576:\n\tcase e1000_i350:\n\t\tif (!(wvbr = E1000_READ_REG(hw, E1000_WVBR)))\n\t\t\treturn;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tadapter->wvbr |= wvbr;\n}\n\n#define IGB_STAGGERED_QUEUE_OFFSET 8\n\nstatic void igb_spoof_check(struct igb_adapter *adapter)\n{\n\tint j;\n\n\tif (!adapter->wvbr)\n\t\treturn;\n\n\tswitch (adapter->hw.mac.type) {\n\tcase e1000_82576:\n\t\tfor (j = 0; j < adapter->vfs_allocated_count; j++) {\n\t\t\tif (adapter->wvbr & (1 << j) ||\n\t\t\t adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {\n\t\t\t\tDPRINTK(DRV, WARNING,\n\t\t\t\t\t\"Spoof event(s) detected on VF %d\\n\", j);\n\t\t\t\tadapter->wvbr &=\n\t\t\t\t\t~((1 << j) |\n\t\t\t\t\t (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tcase e1000_i350:\n\t\tfor (j = 0; j < adapter->vfs_allocated_count; j++) {\n\t\t\tif (adapter->wvbr & (1 << j)) {\n\t\t\t\tDPRINTK(DRV, WARNING,\n\t\t\t\t\t\"Spoof event(s) detected on VF %d\\n\", j);\n\t\t\t\tadapter->wvbr &= ~(1 << j);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n/* Need to wait a few seconds after link up to get diagnostic information from\n * the phy */\nstatic void igb_update_phy_info(unsigned long data)\n{\n\tstruct igb_adapter *adapter = (struct igb_adapter *) data;\n\te1000_get_phy_info(&adapter->hw);\n}\n\n/**\n * igb_has_link - check shared code for link and determine up/down\n * @adapter: pointer to driver private info\n **/\nbool igb_has_link(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tbool link_active = FALSE;\n\n\t/* get_link_status is set on LSC (link status) interrupt or\n\t * rx sequence error interrupt. get_link_status will stay\n\t * false until the e1000_check_for_link establishes link\n\t * for copper adapters ONLY\n\t */\n\tswitch (hw->phy.media_type) {\n\tcase e1000_media_type_copper:\n\t\tif (!hw->mac.get_link_status)\n\t\t\treturn true;\n\tcase e1000_media_type_internal_serdes:\n\t\te1000_check_for_link(hw);\n\t\tlink_active = !hw->mac.get_link_status;\n\t\tbreak;\n\tcase e1000_media_type_unknown:\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (((hw->mac.type == e1000_i210) ||\n\t (hw->mac.type == e1000_i211)) &&\n\t (hw->phy.id == I210_I_PHY_ID)) {\n\t\tif (!netif_carrier_ok(adapter->netdev)) {\n\t\t\tadapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;\n\t\t} else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {\n\t\t\tadapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;\n\t\t\tadapter->link_check_timeout = jiffies;\n\t\t}\n\t}\n\n\treturn link_active;\n}\n\n/**\n * igb_watchdog - Timer Call-back\n * @data: pointer to adapter cast into an unsigned long\n **/\nstatic void igb_watchdog(unsigned long data)\n{\n\tstruct igb_adapter *adapter = (struct igb_adapter *)data;\n\t/* Do the rest outside of interrupt context */\n\tschedule_work(&adapter->watchdog_task);\n}\n\nstatic void igb_watchdog_task(struct work_struct *work)\n{\n\tstruct igb_adapter *adapter = container_of(work,\n\t struct igb_adapter,\n watchdog_task);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct net_device *netdev = adapter->netdev;\n\tu32 link;\n\tint i;\n\tu32 thstat, ctrl_ext;\n\tu32 connsw;\n\n\tlink = igb_has_link(adapter);\n\t/* Force link down if we have fiber to swap to */\n\tif (adapter->flags & IGB_FLAG_MAS_ENABLE) {\n\t\tif (hw->phy.media_type == e1000_media_type_copper) {\n\t\t\tconnsw = E1000_READ_REG(hw, E1000_CONNSW);\n\t\t\tif (!(connsw & E1000_CONNSW_AUTOSENSE_EN))\n\t\t\t\tlink = 0;\n\t\t}\n\t}\n\n\tif (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {\n\t\tif (time_after(jiffies, (adapter->link_check_timeout + HZ)))\n\t\t\tadapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;\n\t\telse\n\t\t\tlink = FALSE;\n\t}\n\n\tif (link) {\n\t\t/* Perform a reset if the media type changed. */\n\t\tif (hw->dev_spec._82575.media_changed) {\n\t\t\thw->dev_spec._82575.media_changed = false;\n\t\t\tadapter->flags |= IGB_FLAG_MEDIA_RESET;\n\t\t\tigb_reset(adapter);\n\t\t}\n\n\t\t/* Cancel scheduled suspend requests. */\n\t\tpm_runtime_resume(netdev->dev.parent);\n\n\t\tif (!netif_carrier_ok(netdev)) {\n\t\t\tu32 ctrl;\n\t\t\te1000_get_speed_and_duplex(hw,\n\t\t\t &adapter->link_speed,\n\t\t\t &adapter->link_duplex);\n\n\t\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\t\t/* Links status message must follow this format */\n\t\t\tprintk(KERN_INFO \"igb: %s NIC Link is Up %d Mbps %s, \"\n\t\t\t\t \"Flow Control: %s\\n\",\n\t\t\t netdev->name,\n\t\t\t adapter->link_speed,\n\t\t\t adapter->link_duplex == FULL_DUPLEX ?\n\t\t\t\t \"Full Duplex\" : \"Half Duplex\",\n\t\t\t ((ctrl & E1000_CTRL_TFCE) &&\n\t\t\t (ctrl & E1000_CTRL_RFCE)) ? \"RX/TX\":\n\t\t\t ((ctrl & E1000_CTRL_RFCE) ? \"RX\" :\n\t\t\t ((ctrl & E1000_CTRL_TFCE) ? \"TX\" : \"None\")));\n\t\t\t/* adjust timeout factor according to speed/duplex */\n\t\t\tadapter->tx_timeout_factor = 1;\n\t\t\tswitch (adapter->link_speed) {\n\t\t\tcase SPEED_10:\n\t\t\t\tadapter->tx_timeout_factor = 14;\n\t\t\t\tbreak;\n\t\t\tcase SPEED_100:\n\t\t\t\t/* maybe add some timeout factor ? */\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tnetif_carrier_on(netdev);\n\t\t\tnetif_tx_wake_all_queues(netdev);\n\n\t\t\tigb_ping_all_vfs(adapter);\n#ifdef IFLA_VF_MAX\n\t\t\tigb_check_vf_rate_limit(adapter);\n#endif /* IFLA_VF_MAX */\n\n\t\t\t/* link state has changed, schedule phy info update */\n\t\t\tif (!test_bit(__IGB_DOWN, &adapter->state))\n\t\t\t\tmod_timer(&adapter->phy_info_timer,\n\t\t\t\t\t round_jiffies(jiffies + 2 * HZ));\n\t\t}\n\t} else {\n\t\tif (netif_carrier_ok(netdev)) {\n\t\t\tadapter->link_speed = 0;\n\t\t\tadapter->link_duplex = 0;\n\t\t\t/* check for thermal sensor event on i350 */\n\t\t\tif (hw->mac.type == e1000_i350) {\n\t\t\t\tthstat = E1000_READ_REG(hw, E1000_THSTAT);\n\t\t\t\tctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\t\t\t\tif ((hw->phy.media_type ==\n\t\t\t\t\te1000_media_type_copper) &&\n\t\t\t\t\t!(ctrl_ext &\n\t\t\t\t\tE1000_CTRL_EXT_LINK_MODE_SGMII)) {\n\t\t\t\t\tif (thstat & E1000_THSTAT_PWR_DOWN) {\n\t\t\t\t\t\tprintk(KERN_ERR \"igb: %s The \"\n\t\t\t\t\t\t\"network adapter was stopped \"\n\t\t\t\t\t\t\"because it overheated.\\n\",\n\t\t\t\t\t\tnetdev->name);\n\t\t\t\t\t}\n\t\t\t\t\tif (thstat & E1000_THSTAT_LINK_THROTTLE) {\n\t\t\t\t\t\tprintk(KERN_INFO\n\t\t\t\t\t\t\t\"igb: %s The network \"\n\t\t\t\t\t\t\t\"adapter supported \"\n\t\t\t\t\t\t\t\"link speed \"\n\t\t\t\t\t\t\t\"was downshifted \"\n\t\t\t\t\t\t\t\"because it \"\n\t\t\t\t\t\t\t\"overheated.\\n\",\n\t\t\t\t\t\t\tnetdev->name);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Links status message must follow this format */\n\t\t\tprintk(KERN_INFO \"igb: %s NIC Link is Down\\n\",\n\t\t\t netdev->name);\n\t\t\tnetif_carrier_off(netdev);\n\t\t\tnetif_tx_stop_all_queues(netdev);\n\n\t\t\tigb_ping_all_vfs(adapter);\n\n\t\t\t/* link state has changed, schedule phy info update */\n\t\t\tif (!test_bit(__IGB_DOWN, &adapter->state))\n\t\t\t\tmod_timer(&adapter->phy_info_timer,\n\t\t\t\t\t round_jiffies(jiffies + 2 * HZ));\n\t\t\t/* link is down, time to check for alternate media */\n\t\t\tif (adapter->flags & IGB_FLAG_MAS_ENABLE) {\n\t\t\t\tigb_check_swap_media(adapter);\n\t\t\t\tif (adapter->flags & IGB_FLAG_MEDIA_RESET) {\n\t\t\t\t\tschedule_work(&adapter->reset_task);\n\t\t\t\t\t/* return immediately */\n\t\t\t\t\treturn;\n\t\t\t\t}\n\t\t\t}\n\t\t\tpm_schedule_suspend(netdev->dev.parent,\n\t\t\t\t\t MSEC_PER_SEC * 5);\n\n\t\t/* also check for alternate media here */\n\t\t} else if (!netif_carrier_ok(netdev) &&\n\t\t\t (adapter->flags & IGB_FLAG_MAS_ENABLE)) {\n\t\t\thw->mac.ops.power_up_serdes(hw);\n\t\t\tigb_check_swap_media(adapter);\n\t\t\tif (adapter->flags & IGB_FLAG_MEDIA_RESET) {\n\t\t\t\tschedule_work(&adapter->reset_task);\n\t\t\t\t/* return immediately */\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\t}\n\n\tigb_update_stats(adapter);\n\n\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\tstruct igb_ring *tx_ring = adapter->tx_ring[i];\n\t\tif (!netif_carrier_ok(netdev)) {\n\t\t\t/* We've lost link, so the controller stops DMA,\n\t\t\t * but we've got queued Tx work that's never going\n\t\t\t * to get done, so reset controller to flush Tx.\n\t\t\t * (Do the reset outside of interrupt context). */\n\t\t\tif (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {\n\t\t\t\tadapter->tx_timeout_count++;\n\t\t\t\tschedule_work(&adapter->reset_task);\n\t\t\t\t/* return immediately since reset is imminent */\n\t\t\t\treturn;\n\t\t\t}\n\t\t}\n\n\t\t/* Force detection of hung controller every watchdog period */\n\t\tset_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);\n\t}\n\n\t/* Cause software interrupt to ensure rx ring is cleaned */\n\tif (adapter->msix_entries) {\n\t\tu32 eics = 0;\n\t\tfor (i = 0; i < adapter->num_q_vectors; i++)\n\t\t\teics |= adapter->q_vector[i]->eims_value;\n\t\tE1000_WRITE_REG(hw, E1000_EICS, eics);\n\t} else {\n\t\tE1000_WRITE_REG(hw, E1000_ICS, E1000_ICS_RXDMT0);\n\t}\n\n\tigb_spoof_check(adapter);\n\n\t/* Reset the timer */\n\tif (!test_bit(__IGB_DOWN, &adapter->state)) {\n\t\tif (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)\n\t\t\tmod_timer(&adapter->watchdog_timer,\n\t\t\t\t round_jiffies(jiffies + HZ));\n\t\telse\n\t\t\tmod_timer(&adapter->watchdog_timer,\n\t\t\t\t round_jiffies(jiffies + 2 * HZ));\n\t}\n}\n\nstatic void igb_dma_err_task(struct work_struct *work)\n{\n\tstruct igb_adapter *adapter = container_of(work,\n\t struct igb_adapter,\n dma_err_task);\n\tint vf;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct net_device *netdev = adapter->netdev;\n\tu32 hgptc;\n\tu32 ciaa, ciad;\n\n\thgptc = E1000_READ_REG(hw, E1000_HGPTC);\n\tif (hgptc) /* If incrementing then no need for the check below */\n\t\tgoto dma_timer_reset;\n\t/*\n\t * Check to see if a bad DMA write target from an errant or\n\t * malicious VF has caused a PCIe error. If so then we can\n\t * issue a VFLR to the offending VF(s) and then resume without\n\t * requesting a full slot reset.\n\t */\n\n\tfor (vf = 0; vf < adapter->vfs_allocated_count; vf++) {\n\t\tciaa = (vf << 16) | 0x80000000;\n\t\t/* 32 bit read so align, we really want status at offset 6 */\n\t\tciaa |= PCI_COMMAND;\n\t\tE1000_WRITE_REG(hw, E1000_CIAA, ciaa);\n\t\tciad = E1000_READ_REG(hw, E1000_CIAD);\n\t\tciaa &= 0x7FFFFFFF;\n\t\t/* disable debug mode asap after reading data */\n\t\tE1000_WRITE_REG(hw, E1000_CIAA, ciaa);\n\t\t/* Get the upper 16 bits which will be the PCI status reg */\n\t\tciad >>= 16;\n\t\tif (ciad & (PCI_STATUS_REC_MASTER_ABORT |\n\t\t\t PCI_STATUS_REC_TARGET_ABORT |\n\t\t\t PCI_STATUS_SIG_SYSTEM_ERROR)) {\n\t\t\tnetdev_err(netdev, \"VF %d suffered error\\n\", vf);\n\t\t\t/* Issue VFLR */\n\t\t\tciaa = (vf << 16) | 0x80000000;\n\t\t\tciaa |= 0xA8;\n\t\t\tE1000_WRITE_REG(hw, E1000_CIAA, ciaa);\n\t\t\tciad = 0x00008000; /* VFLR */\n\t\t\tE1000_WRITE_REG(hw, E1000_CIAD, ciad);\n\t\t\tciaa &= 0x7FFFFFFF;\n\t\t\tE1000_WRITE_REG(hw, E1000_CIAA, ciaa);\n\t\t}\n\t}\ndma_timer_reset:\n\t/* Reset the timer */\n\tif (!test_bit(__IGB_DOWN, &adapter->state))\n\t\tmod_timer(&adapter->dma_err_timer,\n\t\t\t round_jiffies(jiffies + HZ / 10));\n}\n\n/**\n * igb_dma_err_timer - Timer Call-back\n * @data: pointer to adapter cast into an unsigned long\n **/\nstatic void igb_dma_err_timer(unsigned long data)\n{\n\tstruct igb_adapter *adapter = (struct igb_adapter *)data;\n\t/* Do the rest outside of interrupt context */\n\tschedule_work(&adapter->dma_err_task);\n}\n\nenum latency_range {\n\tlowest_latency = 0,\n\tlow_latency = 1,\n\tbulk_latency = 2,\n\tlatency_invalid = 255\n};\n\n/**\n * igb_update_ring_itr - update the dynamic ITR value based on packet size\n *\n * Stores a new ITR value based on strictly on packet size. This\n * algorithm is less sophisticated than that used in igb_update_itr,\n * due to the difficulty of synchronizing statistics across multiple\n * receive rings. The divisors and thresholds used by this function\n * were determined based on theoretical maximum wire speed and testing\n * data, in order to minimize response time while increasing bulk\n * throughput.\n * This functionality is controlled by the InterruptThrottleRate module\n * parameter (see igb_param.c)\n * NOTE: This function is called only when operating in a multiqueue\n * receive environment.\n * @q_vector: pointer to q_vector\n **/\nstatic void igb_update_ring_itr(struct igb_q_vector *q_vector)\n{\n\tint new_val = q_vector->itr_val;\n\tint avg_wire_size = 0;\n\tstruct igb_adapter *adapter = q_vector->adapter;\n\tunsigned int packets;\n\n\t/* For non-gigabit speeds, just fix the interrupt rate at 4000\n\t * ints/sec - ITR timer value of 120 ticks.\n\t */\n\tswitch (adapter->link_speed) {\n\tcase SPEED_10:\n\tcase SPEED_100:\n\t\tnew_val = IGB_4K_ITR;\n\t\tgoto set_itr_val;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tpackets = q_vector->rx.total_packets;\n\tif (packets)\n\t\tavg_wire_size = q_vector->rx.total_bytes / packets;\n\n\tpackets = q_vector->tx.total_packets;\n\tif (packets)\n\t\tavg_wire_size = max_t(u32, avg_wire_size,\n\t\t q_vector->tx.total_bytes / packets);\n\n\t/* if avg_wire_size isn't set no work was done */\n\tif (!avg_wire_size)\n\t\tgoto clear_counts;\n\n\t/* Add 24 bytes to size to account for CRC, preamble, and gap */\n\tavg_wire_size += 24;\n\n\t/* Don't starve jumbo frames */\n\tavg_wire_size = min(avg_wire_size, 3000);\n\n\t/* Give a little boost to mid-size frames */\n\tif ((avg_wire_size > 300) && (avg_wire_size < 1200))\n\t\tnew_val = avg_wire_size / 3;\n\telse\n\t\tnew_val = avg_wire_size / 2;\n\n\t/* conservative mode (itr 3) eliminates the lowest_latency setting */\n\tif (new_val < IGB_20K_ITR &&\n\t ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||\n\t (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))\n\t\tnew_val = IGB_20K_ITR;\n\nset_itr_val:\n\tif (new_val != q_vector->itr_val) {\n\t\tq_vector->itr_val = new_val;\n\t\tq_vector->set_itr = 1;\n\t}\nclear_counts:\n\tq_vector->rx.total_bytes = 0;\n\tq_vector->rx.total_packets = 0;\n\tq_vector->tx.total_bytes = 0;\n\tq_vector->tx.total_packets = 0;\n}\n\n/**\n * igb_update_itr - update the dynamic ITR value based on statistics\n * Stores a new ITR value based on packets and byte\n * counts during the last interrupt. The advantage of per interrupt\n * computation is faster updates and more accurate ITR for the current\n * traffic pattern. Constants in this function were computed\n * based on theoretical maximum wire speed and thresholds were set based\n * on testing data as well as attempting to minimize response time\n * while increasing bulk throughput.\n * this functionality is controlled by the InterruptThrottleRate module\n * parameter (see igb_param.c)\n * NOTE: These calculations are only valid when operating in a single-\n * queue environment.\n * @q_vector: pointer to q_vector\n * @ring_container: ring info to update the itr for\n **/\nstatic void igb_update_itr(struct igb_q_vector *q_vector,\n\t\t\t struct igb_ring_container *ring_container)\n{\n\tunsigned int packets = ring_container->total_packets;\n\tunsigned int bytes = ring_container->total_bytes;\n\tu8 itrval = ring_container->itr;\n\n\t/* no packets, exit with status unchanged */\n\tif (packets == 0)\n\t\treturn;\n\n\tswitch (itrval) {\n\tcase lowest_latency:\n\t\t/* handle TSO and jumbo frames */\n\t\tif (bytes/packets > 8000)\n\t\t\titrval = bulk_latency;\n\t\telse if ((packets < 5) && (bytes > 512))\n\t\t\titrval = low_latency;\n\t\tbreak;\n\tcase low_latency: /* 50 usec aka 20000 ints/s */\n\t\tif (bytes > 10000) {\n\t\t\t/* this if handles the TSO accounting */\n\t\t\tif (bytes/packets > 8000) {\n\t\t\t\titrval = bulk_latency;\n\t\t\t} else if ((packets < 10) || ((bytes/packets) > 1200)) {\n\t\t\t\titrval = bulk_latency;\n\t\t\t} else if ((packets > 35)) {\n\t\t\t\titrval = lowest_latency;\n\t\t\t}\n\t\t} else if (bytes/packets > 2000) {\n\t\t\titrval = bulk_latency;\n\t\t} else if (packets <= 2 && bytes < 512) {\n\t\t\titrval = lowest_latency;\n\t\t}\n\t\tbreak;\n\tcase bulk_latency: /* 250 usec aka 4000 ints/s */\n\t\tif (bytes > 25000) {\n\t\t\tif (packets > 35)\n\t\t\t\titrval = low_latency;\n\t\t} else if (bytes < 1500) {\n\t\t\titrval = low_latency;\n\t\t}\n\t\tbreak;\n\t}\n\n\t/* clear work counters since we have the values we need */\n\tring_container->total_bytes = 0;\n\tring_container->total_packets = 0;\n\n\t/* write updated itr to ring container */\n\tring_container->itr = itrval;\n}\n\nstatic void igb_set_itr(struct igb_q_vector *q_vector)\n{\n\tstruct igb_adapter *adapter = q_vector->adapter;\n\tu32 new_itr = q_vector->itr_val;\n\tu8 current_itr = 0;\n\n\t/* for non-gigabit speeds, just fix the interrupt rate at 4000 */\n\tswitch (adapter->link_speed) {\n\tcase SPEED_10:\n\tcase SPEED_100:\n\t\tcurrent_itr = 0;\n\t\tnew_itr = IGB_4K_ITR;\n\t\tgoto set_itr_now;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tigb_update_itr(q_vector, &q_vector->tx);\n\tigb_update_itr(q_vector, &q_vector->rx);\n\n\tcurrent_itr = max(q_vector->rx.itr, q_vector->tx.itr);\n\n\t/* conservative mode (itr 3) eliminates the lowest_latency setting */\n\tif (current_itr == lowest_latency &&\n\t ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||\n\t (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))\n\t\tcurrent_itr = low_latency;\n\n\tswitch (current_itr) {\n\t/* counts and packets in update_itr are dependent on these numbers */\n\tcase lowest_latency:\n\t\tnew_itr = IGB_70K_ITR; /* 70,000 ints/sec */\n\t\tbreak;\n\tcase low_latency:\n\t\tnew_itr = IGB_20K_ITR; /* 20,000 ints/sec */\n\t\tbreak;\n\tcase bulk_latency:\n\t\tnew_itr = IGB_4K_ITR; /* 4,000 ints/sec */\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\nset_itr_now:\n\tif (new_itr != q_vector->itr_val) {\n\t\t/* this attempts to bias the interrupt rate towards Bulk\n\t\t * by adding intermediate steps when interrupt rate is\n\t\t * increasing */\n\t\tnew_itr = new_itr > q_vector->itr_val ?\n\t\t max((new_itr * q_vector->itr_val) /\n\t\t (new_itr + (q_vector->itr_val >> 2)),\n\t\t\t\t new_itr) :\n\t\t\t new_itr;\n\t\t/* Don't write the value here; it resets the adapter's\n\t\t * internal timer, and causes us to delay far longer than\n\t\t * we should between interrupts. Instead, we write the ITR\n\t\t * value at the beginning of the next interrupt so the timing\n\t\t * ends up being correct.\n\t\t */\n\t\tq_vector->itr_val = new_itr;\n\t\tq_vector->set_itr = 1;\n\t}\n}\n\nvoid igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,\n\t\t u32 type_tucmd, u32 mss_l4len_idx)\n{\n\tstruct e1000_adv_tx_context_desc *context_desc;\n\tu16 i = tx_ring->next_to_use;\n\n\tcontext_desc = IGB_TX_CTXTDESC(tx_ring, i);\n\n\ti++;\n\ttx_ring->next_to_use = (i < tx_ring->count) ? i : 0;\n\n\t/* set bits to identify this as an advanced context descriptor */\n\ttype_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;\n\n\t/* For 82575, context index must be unique per ring. */\n\tif (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))\n\t\tmss_l4len_idx |= tx_ring->reg_idx << 4;\n\n\tcontext_desc->vlan_macip_lens\t= cpu_to_le32(vlan_macip_lens);\n\tcontext_desc->seqnum_seed\t= 0;\n\tcontext_desc->type_tucmd_mlhl\t= cpu_to_le32(type_tucmd);\n\tcontext_desc->mss_l4len_idx\t= cpu_to_le32(mss_l4len_idx);\n}\n\nstatic int igb_tso(struct igb_ring *tx_ring,\n\t\t struct igb_tx_buffer *first,\n\t\t u8 *hdr_len)\n{\n#ifdef NETIF_F_TSO\n\tstruct sk_buff *skb = first->skb;\n\tu32 vlan_macip_lens, type_tucmd;\n\tu32 mss_l4len_idx, l4len;\n\n\tif (skb->ip_summed != CHECKSUM_PARTIAL)\n\t\treturn 0;\n\n\tif (!skb_is_gso(skb))\n#endif /* NETIF_F_TSO */\n\t\treturn 0;\n#ifdef NETIF_F_TSO\n\n\tif (skb_header_cloned(skb)) {\n\t\tint err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\t/* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */\n\ttype_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;\n\n\tif (first->protocol == __constant_htons(ETH_P_IP)) {\n\t\tstruct iphdr *iph = ip_hdr(skb);\n\t\tiph->tot_len = 0;\n\t\tiph->check = 0;\n\t\ttcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,\n\t\t\t\t\t\t\t iph->daddr, 0,\n\t\t\t\t\t\t\t IPPROTO_TCP,\n\t\t\t\t\t\t\t 0);\n\t\ttype_tucmd |= E1000_ADVTXD_TUCMD_IPV4;\n\t\tfirst->tx_flags |= IGB_TX_FLAGS_TSO |\n\t\t\t\t IGB_TX_FLAGS_CSUM |\n\t\t\t\t IGB_TX_FLAGS_IPV4;\n#ifdef NETIF_F_TSO6\n\t} else if (skb_is_gso_v6(skb)) {\n\t\tipv6_hdr(skb)->payload_len = 0;\n\t\ttcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,\n\t\t\t\t\t\t &ipv6_hdr(skb)->daddr,\n\t\t\t\t\t\t 0, IPPROTO_TCP, 0);\n\t\tfirst->tx_flags |= IGB_TX_FLAGS_TSO |\n\t\t\t\t IGB_TX_FLAGS_CSUM;\n#endif\n\t}\n\n\t/* compute header lengths */\n\tl4len = tcp_hdrlen(skb);\n\t*hdr_len = skb_transport_offset(skb) + l4len;\n\n\t/* update gso size and bytecount with header size */\n\tfirst->gso_segs = skb_shinfo(skb)->gso_segs;\n\tfirst->bytecount += (first->gso_segs - 1) * *hdr_len;\n\n\t/* MSS L4LEN IDX */\n\tmss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;\n\tmss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;\n\n\t/* VLAN MACLEN IPLEN */\n\tvlan_macip_lens = skb_network_header_len(skb);\n\tvlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;\n\tvlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;\n\n\tigb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);\n\n\treturn 1;\n#endif /* NETIF_F_TSO */\n}\n\nstatic void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)\n{\n\tstruct sk_buff *skb = first->skb;\n\tu32 vlan_macip_lens = 0;\n\tu32 mss_l4len_idx = 0;\n\tu32 type_tucmd = 0;\n\n\tif (skb->ip_summed != CHECKSUM_PARTIAL) {\n\t\tif (!(first->tx_flags & IGB_TX_FLAGS_VLAN))\n\t\t\treturn;\n\t} else {\n\t\tu8 nexthdr = 0;\n\t\tswitch (first->protocol) {\n\t\tcase __constant_htons(ETH_P_IP):\n\t\t\tvlan_macip_lens |= skb_network_header_len(skb);\n\t\t\ttype_tucmd |= E1000_ADVTXD_TUCMD_IPV4;\n\t\t\tnexthdr = ip_hdr(skb)->protocol;\n\t\t\tbreak;\n#ifdef NETIF_F_IPV6_CSUM\n\t\tcase __constant_htons(ETH_P_IPV6):\n\t\t\tvlan_macip_lens |= skb_network_header_len(skb);\n\t\t\tnexthdr = ipv6_hdr(skb)->nexthdr;\n\t\t\tbreak;\n#endif\n\t\tdefault:\n\t\t\tif (unlikely(net_ratelimit())) {\n\t\t\t\tdev_warn(tx_ring->dev,\n\t\t\t\t \"partial checksum but proto=%x!\\n\",\n\t\t\t\t first->protocol);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\n\t\tswitch (nexthdr) {\n\t\tcase IPPROTO_TCP:\n\t\t\ttype_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;\n\t\t\tmss_l4len_idx = tcp_hdrlen(skb) <<\n\t\t\t\t\tE1000_ADVTXD_L4LEN_SHIFT;\n\t\t\tbreak;\n#ifdef HAVE_SCTP\n\t\tcase IPPROTO_SCTP:\n\t\t\ttype_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;\n\t\t\tmss_l4len_idx = sizeof(struct sctphdr) <<\n\t\t\t\t\tE1000_ADVTXD_L4LEN_SHIFT;\n\t\t\tbreak;\n#endif\n\t\tcase IPPROTO_UDP:\n\t\t\tmss_l4len_idx = sizeof(struct udphdr) <<\n\t\t\t\t\tE1000_ADVTXD_L4LEN_SHIFT;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tif (unlikely(net_ratelimit())) {\n\t\t\t\tdev_warn(tx_ring->dev,\n\t\t\t\t \"partial checksum but l4 proto=%x!\\n\",\n\t\t\t\t nexthdr);\n\t\t\t}\n\t\t\tbreak;\n\t\t}\n\n\t\t/* update TX checksum flag */\n\t\tfirst->tx_flags |= IGB_TX_FLAGS_CSUM;\n\t}\n\n\tvlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;\n\tvlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;\n\n\tigb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);\n}\n\n#define IGB_SET_FLAG(_input, _flag, _result) \\\n\t((_flag <= _result) ? \\\n\t ((u32)(_input & _flag) * (_result / _flag)) : \\\n\t ((u32)(_input & _flag) / (_flag / _result)))\n\nstatic u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)\n{\n\t/* set type for advanced descriptor with frame checksum insertion */\n\tu32 cmd_type = E1000_ADVTXD_DTYP_DATA |\n\t\t E1000_ADVTXD_DCMD_DEXT |\n\t\t E1000_ADVTXD_DCMD_IFCS;\n\n\t/* set HW vlan bit if vlan is present */\n\tcmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,\n\t\t\t\t (E1000_ADVTXD_DCMD_VLE));\n\n\t/* set segmentation bits for TSO */\n\tcmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,\n\t\t\t\t (E1000_ADVTXD_DCMD_TSE));\n\n\t/* set timestamp bit if present */\n\tcmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,\n\t\t\t\t (E1000_ADVTXD_MAC_TSTAMP));\n\n\treturn cmd_type;\n}\n\nstatic void igb_tx_olinfo_status(struct igb_ring *tx_ring,\n\t\t\t\t union e1000_adv_tx_desc *tx_desc,\n\t\t\t\t u32 tx_flags, unsigned int paylen)\n{\n\tu32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;\n\n\t/* 82575 requires a unique index per ring */\n\tif (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))\n\t\tolinfo_status |= tx_ring->reg_idx << 4;\n\n\t/* insert L4 checksum */\n\tolinfo_status |= IGB_SET_FLAG(tx_flags,\n\t\t\t\t IGB_TX_FLAGS_CSUM,\n\t\t\t\t (E1000_TXD_POPTS_TXSM << 8));\n\n\t/* insert IPv4 checksum */\n\tolinfo_status |= IGB_SET_FLAG(tx_flags,\n\t\t\t\t IGB_TX_FLAGS_IPV4,\n\t\t\t\t (E1000_TXD_POPTS_IXSM << 8));\n\n\ttx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);\n}\n\nstatic void igb_tx_map(struct igb_ring *tx_ring,\n\t\t struct igb_tx_buffer *first,\n\t\t const u8 hdr_len)\n{\n\tstruct sk_buff *skb = first->skb;\n\tstruct igb_tx_buffer *tx_buffer;\n\tunion e1000_adv_tx_desc *tx_desc;\n\tstruct skb_frag_struct *frag;\n\tdma_addr_t dma;\n\tunsigned int data_len, size;\n\tu32 tx_flags = first->tx_flags;\n\tu32 cmd_type = igb_tx_cmd_type(skb, tx_flags);\n\tu16 i = tx_ring->next_to_use;\n\n\ttx_desc = IGB_TX_DESC(tx_ring, i);\n\n\tigb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);\n\n\tsize = skb_headlen(skb);\n\tdata_len = skb->data_len;\n\n\tdma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);\n\n\ttx_buffer = first;\n\n\tfor (frag = &skb_shinfo(skb)->frags[0];; frag++) {\n\t\tif (dma_mapping_error(tx_ring->dev, dma))\n\t\t\tgoto dma_error;\n\n\t\t/* record length, and DMA address */\n\t\tdma_unmap_len_set(tx_buffer, len, size);\n\t\tdma_unmap_addr_set(tx_buffer, dma, dma);\n\n\t\ttx_desc->read.buffer_addr = cpu_to_le64(dma);\n\n\t\twhile (unlikely(size > IGB_MAX_DATA_PER_TXD)) {\n\t\t\ttx_desc->read.cmd_type_len =\n\t\t\t\tcpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);\n\n\t\t\ti++;\n\t\t\ttx_desc++;\n\t\t\tif (i == tx_ring->count) {\n\t\t\t\ttx_desc = IGB_TX_DESC(tx_ring, 0);\n\t\t\t\ti = 0;\n\t\t\t}\n\t\t\ttx_desc->read.olinfo_status = 0;\n\n\t\t\tdma += IGB_MAX_DATA_PER_TXD;\n\t\t\tsize -= IGB_MAX_DATA_PER_TXD;\n\n\t\t\ttx_desc->read.buffer_addr = cpu_to_le64(dma);\n\t\t}\n\n\t\tif (likely(!data_len))\n\t\t\tbreak;\n\n\t\ttx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);\n\n\t\ti++;\n\t\ttx_desc++;\n\t\tif (i == tx_ring->count) {\n\t\t\ttx_desc = IGB_TX_DESC(tx_ring, 0);\n\t\t\ti = 0;\n\t\t}\n\t\ttx_desc->read.olinfo_status = 0;\n\n\t\tsize = skb_frag_size(frag);\n\t\tdata_len -= size;\n\n\t\tdma = skb_frag_dma_map(tx_ring->dev, frag, 0,\n\t\t\t\t size, DMA_TO_DEVICE);\n\n\t\ttx_buffer = &tx_ring->tx_buffer_info[i];\n\t}\n\n\t/* write last descriptor with RS and EOP bits */\n\tcmd_type |= size | IGB_TXD_DCMD;\n\ttx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);\n\n\tnetdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);\n\t/* set the timestamp */\n\tfirst->time_stamp = jiffies;\n\n\t/*\n\t * Force memory writes to complete before letting h/w know there\n\t * are new descriptors to fetch. (Only applicable for weak-ordered\n\t * memory model archs, such as IA-64).\n\t *\n\t * We also need this memory barrier to make certain all of the\n\t * status bits have been updated before next_to_watch is written.\n\t */\n\twmb();\n\n\t/* set next_to_watch value indicating a packet is present */\n\tfirst->next_to_watch = tx_desc;\n\n\ti++;\n\tif (i == tx_ring->count)\n\t\ti = 0;\n\n\ttx_ring->next_to_use = i;\n\n\twritel(i, tx_ring->tail);\n\n\t/* we need this if more than one processor can write to our tail\n\t * at a time, it syncronizes IO on IA64/Altix systems */\n\tmmiowb();\n\n\treturn;\n\ndma_error:\n\tdev_err(tx_ring->dev, \"TX DMA map failed\\n\");\n\n\t/* clear dma mappings for failed tx_buffer_info map */\n\tfor (;;) {\n\t\ttx_buffer = &tx_ring->tx_buffer_info[i];\n\t\tigb_unmap_and_free_tx_resource(tx_ring, tx_buffer);\n\t\tif (tx_buffer == first)\n\t\t\tbreak;\n\t\tif (i == 0)\n\t\t\ti = tx_ring->count;\n\t\ti--;\n\t}\n\n\ttx_ring->next_to_use = i;\n}\n\nstatic int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)\n{\n\tstruct net_device *netdev = netdev_ring(tx_ring);\n\n\tif (netif_is_multiqueue(netdev))\n\t\tnetif_stop_subqueue(netdev, ring_queue_index(tx_ring));\n\telse\n\t\tnetif_stop_queue(netdev);\n\n\t/* Herbert's original patch had:\n\t * smp_mb__after_netif_stop_queue();\n\t * but since that doesn't exist yet, just open code it. */\n\tsmp_mb();\n\n\t/* We need to check again in a case another CPU has just\n\t * made room available. */\n\tif (igb_desc_unused(tx_ring) < size)\n\t\treturn -EBUSY;\n\n\t/* A reprieve! */\n\tif (netif_is_multiqueue(netdev))\n\t\tnetif_wake_subqueue(netdev, ring_queue_index(tx_ring));\n\telse\n\t\tnetif_wake_queue(netdev);\n\n\ttx_ring->tx_stats.restart_queue++;\n\n\treturn 0;\n}\n\nstatic inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)\n{\n\tif (igb_desc_unused(tx_ring) >= size)\n\t\treturn 0;\n\treturn __igb_maybe_stop_tx(tx_ring, size);\n}\n\nnetdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,\n\t\t\t\tstruct igb_ring *tx_ring)\n{\n\tstruct igb_tx_buffer *first;\n\tint tso;\n\tu32 tx_flags = 0;\n#if PAGE_SIZE > IGB_MAX_DATA_PER_TXD\n\tunsigned short f;\n#endif\n\tu16 count = TXD_USE_COUNT(skb_headlen(skb));\n\t__be16 protocol = vlan_get_protocol(skb);\n\tu8 hdr_len = 0;\n\n\t/*\n\t * need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,\n\t * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,\n\t * + 2 desc gap to keep tail from touching head,\n\t * + 1 desc for context descriptor,\n\t * otherwise try next time\n\t */\n#if PAGE_SIZE > IGB_MAX_DATA_PER_TXD\n\tfor (f = 0; f < skb_shinfo(skb)->nr_frags; f++)\n\t\tcount += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);\n#else\n\tcount += skb_shinfo(skb)->nr_frags;\n#endif\n\tif (igb_maybe_stop_tx(tx_ring, count + 3)) {\n\t\t/* this is a hard error */\n\t\treturn NETDEV_TX_BUSY;\n\t}\n\n\t/* record the location of the first descriptor for this packet */\n\tfirst = &tx_ring->tx_buffer_info[tx_ring->next_to_use];\n\tfirst->skb = skb;\n\tfirst->bytecount = skb->len;\n\tfirst->gso_segs = 1;\n\n\tskb_tx_timestamp(skb);\n\n#ifdef HAVE_PTP_1588_CLOCK\n\tif (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {\n\t\tstruct igb_adapter *adapter = netdev_priv(tx_ring->netdev);\n\t\tif (!adapter->ptp_tx_skb) {\n\t\t\tskb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;\n\t\t\ttx_flags |= IGB_TX_FLAGS_TSTAMP;\n\n\t\t\tadapter->ptp_tx_skb = skb_get(skb);\n\t\t\tadapter->ptp_tx_start = jiffies;\n\t\t\tif (adapter->hw.mac.type == e1000_82576)\n\t\t\t\tschedule_work(&adapter->ptp_tx_work);\n\t\t}\n\t}\n#endif /* HAVE_PTP_1588_CLOCK */\n\n\tif (vlan_tx_tag_present(skb)) {\n\t\ttx_flags |= IGB_TX_FLAGS_VLAN;\n\t\ttx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);\n\t}\n\n\t/* record initial flags and protocol */\n\tfirst->tx_flags = tx_flags;\n\tfirst->protocol = protocol;\n\n\ttso = igb_tso(tx_ring, first, &hdr_len);\n\tif (tso < 0)\n\t\tgoto out_drop;\n\telse if (!tso)\n\t\tigb_tx_csum(tx_ring, first);\n\n\tigb_tx_map(tx_ring, first, hdr_len);\n\n#ifndef HAVE_TRANS_START_IN_QUEUE\n\tnetdev_ring(tx_ring)->trans_start = jiffies;\n\n#endif\n\t/* Make sure there is space in the ring for the next send. */\n\tigb_maybe_stop_tx(tx_ring, DESC_NEEDED);\n\n\treturn NETDEV_TX_OK;\n\nout_drop:\n\tigb_unmap_and_free_tx_resource(tx_ring, first);\n\n\treturn NETDEV_TX_OK;\n}\n\n#ifdef HAVE_TX_MQ\nstatic inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,\n struct sk_buff *skb)\n{\n\tunsigned int r_idx = skb->queue_mapping;\n\n\tif (r_idx >= adapter->num_tx_queues)\n\t\tr_idx = r_idx % adapter->num_tx_queues;\n\n\treturn adapter->tx_ring[r_idx];\n}\n#else\n#define igb_tx_queue_mapping(_adapter, _skb) (_adapter)->tx_ring[0]\n#endif\n\nstatic netdev_tx_t igb_xmit_frame(struct sk_buff *skb,\n struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\tif (test_bit(__IGB_DOWN, &adapter->state)) {\n\t\tdev_kfree_skb_any(skb);\n\t\treturn NETDEV_TX_OK;\n\t}\n\n\tif (skb->len <= 0) {\n\t\tdev_kfree_skb_any(skb);\n\t\treturn NETDEV_TX_OK;\n\t}\n\n\t/*\n\t * The minimum packet size with TCTL.PSP set is 17 so pad the skb\n\t * in order to meet this minimum size requirement.\n\t */\n\tif (skb->len < 17) {\n\t\tif (skb_padto(skb, 17))\n\t\t\treturn NETDEV_TX_OK;\n\t\tskb->len = 17;\n\t}\n\n\treturn igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));\n}\n\n/**\n * igb_tx_timeout - Respond to a Tx Hang\n * @netdev: network interface device structure\n **/\nstatic void igb_tx_timeout(struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\t/* Do the reset outside of interrupt context */\n\tadapter->tx_timeout_count++;\n\n\tif (hw->mac.type >= e1000_82580)\n\t\thw->dev_spec._82575.global_device_reset = true;\n\n\tschedule_work(&adapter->reset_task);\n\tE1000_WRITE_REG(hw, E1000_EICS,\n\t\t\t(adapter->eims_enable_mask & ~adapter->eims_other));\n}\n\nstatic void igb_reset_task(struct work_struct *work)\n{\n\tstruct igb_adapter *adapter;\n\tadapter = container_of(work, struct igb_adapter, reset_task);\n\n\tigb_reinit_locked(adapter);\n}\n\n/**\n * igb_get_stats - Get System Network Statistics\n * @netdev: network interface device structure\n *\n * Returns the address of the device statistics structure.\n * The statistics are updated here and also from the timer callback.\n **/\nstatic struct net_device_stats *igb_get_stats(struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\tif (!test_bit(__IGB_RESETTING, &adapter->state))\n\t\tigb_update_stats(adapter);\n\n#ifdef HAVE_NETDEV_STATS_IN_NETDEV\n\t/* only return the current stats */\n\treturn &netdev->stats;\n#else\n\t/* only return the current stats */\n\treturn &adapter->net_stats;\n#endif /* HAVE_NETDEV_STATS_IN_NETDEV */\n}\n\n/**\n * igb_change_mtu - Change the Maximum Transfer Unit\n * @netdev: network interface device structure\n * @new_mtu: new value for maximum frame size\n *\n * Returns 0 on success, negative on failure\n **/\nstatic int igb_change_mtu(struct net_device *netdev, int new_mtu)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct pci_dev *pdev = adapter->pdev;\n\tint max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;\n\n\tif ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {\n\t\tdev_err(pci_dev_to_dev(pdev), \"Invalid MTU setting\\n\");\n\t\treturn -EINVAL;\n\t}\n\n#define MAX_STD_JUMBO_FRAME_SIZE 9238\n\tif (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {\n\t\tdev_err(pci_dev_to_dev(pdev), \"MTU > 9216 not supported.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* adjust max frame to be at least the size of a standard frame */\n\tif (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))\n\t\tmax_frame = ETH_FRAME_LEN + ETH_FCS_LEN;\n\n\twhile (test_and_set_bit(__IGB_RESETTING, &adapter->state))\n\t\tusleep_range(1000, 2000);\n\n\t/* igb_down has a dependency on max_frame_size */\n\tadapter->max_frame_size = max_frame;\n\n\tif (netif_running(netdev))\n\t\tigb_down(adapter);\n\n\tdev_info(pci_dev_to_dev(pdev), \"changing MTU from %d to %d\\n\",\n\t netdev->mtu, new_mtu);\n\tnetdev->mtu = new_mtu;\n\thw->dev_spec._82575.mtu = new_mtu;\n\n\tif (netif_running(netdev))\n\t\tigb_up(adapter);\n\telse\n\t\tigb_reset(adapter);\n\n\tclear_bit(__IGB_RESETTING, &adapter->state);\n\n\treturn 0;\n}\n\n/**\n * igb_update_stats - Update the board statistics counters\n * @adapter: board private structure\n **/\n\nvoid igb_update_stats(struct igb_adapter *adapter)\n{\n#ifdef HAVE_NETDEV_STATS_IN_NETDEV\n\tstruct net_device_stats *net_stats = &adapter->netdev->stats;\n#else\n\tstruct net_device_stats *net_stats = &adapter->net_stats;\n#endif /* HAVE_NETDEV_STATS_IN_NETDEV */\n\tstruct e1000_hw *hw = &adapter->hw;\n#ifdef HAVE_PCI_ERS\n\tstruct pci_dev *pdev = adapter->pdev;\n#endif\n\tu32 reg, mpc;\n\tu16 phy_tmp;\n\tint i;\n\tu64 bytes, packets;\n#ifndef IGB_NO_LRO\n\tu32 flushed = 0, coal = 0;\n\tstruct igb_q_vector *q_vector;\n#endif\n\n#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF\n\n\t/*\n\t * Prevent stats update while adapter is being reset, or if the pci\n\t * connection is down.\n\t */\n\tif (adapter->link_speed == 0)\n\t\treturn;\n#ifdef HAVE_PCI_ERS\n\tif (pci_channel_offline(pdev))\n\t\treturn;\n\n#endif\n#ifndef IGB_NO_LRO\n\tfor (i = 0; i < adapter->num_q_vectors; i++) {\n\t\tq_vector = adapter->q_vector[i];\n\t\tif (!q_vector)\n\t\t\tcontinue;\n\t\tflushed += q_vector->lrolist.stats.flushed;\n\t\tcoal += q_vector->lrolist.stats.coal;\n\t}\n\tadapter->lro_stats.flushed = flushed;\n\tadapter->lro_stats.coal = coal;\n\n#endif\n\tbytes = 0;\n\tpackets = 0;\n\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\tu32 rqdpc_tmp = E1000_READ_REG(hw, E1000_RQDPC(i)) & 0x0FFF;\n\t\tstruct igb_ring *ring = adapter->rx_ring[i];\n\t\tring->rx_stats.drops += rqdpc_tmp;\n\t\tnet_stats->rx_fifo_errors += rqdpc_tmp;\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n\t\tif (!ring->vmdq_netdev) {\n\t\t\tbytes += ring->rx_stats.bytes;\n\t\t\tpackets += ring->rx_stats.packets;\n\t\t}\n#else\n\t\tbytes += ring->rx_stats.bytes;\n\t\tpackets += ring->rx_stats.packets;\n#endif\n\t}\n\n\tnet_stats->rx_bytes = bytes;\n\tnet_stats->rx_packets = packets;\n\n\tbytes = 0;\n\tpackets = 0;\n\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\tstruct igb_ring *ring = adapter->tx_ring[i];\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n\t\tif (!ring->vmdq_netdev) {\n\t\t\tbytes += ring->tx_stats.bytes;\n\t\t\tpackets += ring->tx_stats.packets;\n\t\t}\n#else\n\t\tbytes += ring->tx_stats.bytes;\n\t\tpackets += ring->tx_stats.packets;\n#endif\n\t}\n\tnet_stats->tx_bytes = bytes;\n\tnet_stats->tx_packets = packets;\n\n\t/* read stats registers */\n\tadapter->stats.crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);\n\tadapter->stats.gprc += E1000_READ_REG(hw, E1000_GPRC);\n\tadapter->stats.gorc += E1000_READ_REG(hw, E1000_GORCL);\n\tE1000_READ_REG(hw, E1000_GORCH); /* clear GORCL */\n\tadapter->stats.bprc += E1000_READ_REG(hw, E1000_BPRC);\n\tadapter->stats.mprc += E1000_READ_REG(hw, E1000_MPRC);\n\tadapter->stats.roc += E1000_READ_REG(hw, E1000_ROC);\n\n\tadapter->stats.prc64 += E1000_READ_REG(hw, E1000_PRC64);\n\tadapter->stats.prc127 += E1000_READ_REG(hw, E1000_PRC127);\n\tadapter->stats.prc255 += E1000_READ_REG(hw, E1000_PRC255);\n\tadapter->stats.prc511 += E1000_READ_REG(hw, E1000_PRC511);\n\tadapter->stats.prc1023 += E1000_READ_REG(hw, E1000_PRC1023);\n\tadapter->stats.prc1522 += E1000_READ_REG(hw, E1000_PRC1522);\n\tadapter->stats.symerrs += E1000_READ_REG(hw, E1000_SYMERRS);\n\tadapter->stats.sec += E1000_READ_REG(hw, E1000_SEC);\n\n\tmpc = E1000_READ_REG(hw, E1000_MPC);\n\tadapter->stats.mpc += mpc;\n\tnet_stats->rx_fifo_errors += mpc;\n\tadapter->stats.scc += E1000_READ_REG(hw, E1000_SCC);\n\tadapter->stats.ecol += E1000_READ_REG(hw, E1000_ECOL);\n\tadapter->stats.mcc += E1000_READ_REG(hw, E1000_MCC);\n\tadapter->stats.latecol += E1000_READ_REG(hw, E1000_LATECOL);\n\tadapter->stats.dc += E1000_READ_REG(hw, E1000_DC);\n\tadapter->stats.rlec += E1000_READ_REG(hw, E1000_RLEC);\n\tadapter->stats.xonrxc += E1000_READ_REG(hw, E1000_XONRXC);\n\tadapter->stats.xontxc += E1000_READ_REG(hw, E1000_XONTXC);\n\tadapter->stats.xoffrxc += E1000_READ_REG(hw, E1000_XOFFRXC);\n\tadapter->stats.xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);\n\tadapter->stats.fcruc += E1000_READ_REG(hw, E1000_FCRUC);\n\tadapter->stats.gptc += E1000_READ_REG(hw, E1000_GPTC);\n\tadapter->stats.gotc += E1000_READ_REG(hw, E1000_GOTCL);\n\tE1000_READ_REG(hw, E1000_GOTCH); /* clear GOTCL */\n\tadapter->stats.rnbc += E1000_READ_REG(hw, E1000_RNBC);\n\tadapter->stats.ruc += E1000_READ_REG(hw, E1000_RUC);\n\tadapter->stats.rfc += E1000_READ_REG(hw, E1000_RFC);\n\tadapter->stats.rjc += E1000_READ_REG(hw, E1000_RJC);\n\tadapter->stats.tor += E1000_READ_REG(hw, E1000_TORH);\n\tadapter->stats.tot += E1000_READ_REG(hw, E1000_TOTH);\n\tadapter->stats.tpr += E1000_READ_REG(hw, E1000_TPR);\n\n\tadapter->stats.ptc64 += E1000_READ_REG(hw, E1000_PTC64);\n\tadapter->stats.ptc127 += E1000_READ_REG(hw, E1000_PTC127);\n\tadapter->stats.ptc255 += E1000_READ_REG(hw, E1000_PTC255);\n\tadapter->stats.ptc511 += E1000_READ_REG(hw, E1000_PTC511);\n\tadapter->stats.ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);\n\tadapter->stats.ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);\n\n\tadapter->stats.mptc += E1000_READ_REG(hw, E1000_MPTC);\n\tadapter->stats.bptc += E1000_READ_REG(hw, E1000_BPTC);\n\n\tadapter->stats.tpt += E1000_READ_REG(hw, E1000_TPT);\n\tadapter->stats.colc += E1000_READ_REG(hw, E1000_COLC);\n\n\tadapter->stats.algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);\n\t/* read internal phy sepecific stats */\n\treg = E1000_READ_REG(hw, E1000_CTRL_EXT);\n\tif (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {\n\t\tadapter->stats.rxerrc += E1000_READ_REG(hw, E1000_RXERRC);\n\n\t\t/* this stat has invalid values on i210/i211 */\n\t\tif ((hw->mac.type != e1000_i210) &&\n\t\t (hw->mac.type != e1000_i211))\n\t\t\tadapter->stats.tncrs += E1000_READ_REG(hw, E1000_TNCRS);\n\t}\n\tadapter->stats.tsctc += E1000_READ_REG(hw, E1000_TSCTC);\n\tadapter->stats.tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);\n\n\tadapter->stats.iac += E1000_READ_REG(hw, E1000_IAC);\n\tadapter->stats.icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);\n\tadapter->stats.icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);\n\tadapter->stats.icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);\n\tadapter->stats.ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);\n\tadapter->stats.ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);\n\tadapter->stats.ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);\n\tadapter->stats.ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);\n\tadapter->stats.icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);\n\n\t/* Fill out the OS statistics structure */\n\tnet_stats->multicast = adapter->stats.mprc;\n\tnet_stats->collisions = adapter->stats.colc;\n\n\t/* Rx Errors */\n\n\t/* RLEC on some newer hardware can be incorrect so build\n\t * our own version based on RUC and ROC */\n\tnet_stats->rx_errors = adapter->stats.rxerrc +\n\t\tadapter->stats.crcerrs + adapter->stats.algnerrc +\n\t\tadapter->stats.ruc + adapter->stats.roc +\n\t\tadapter->stats.cexterr;\n\tnet_stats->rx_length_errors = adapter->stats.ruc +\n\t\t\t\t adapter->stats.roc;\n\tnet_stats->rx_crc_errors = adapter->stats.crcerrs;\n\tnet_stats->rx_frame_errors = adapter->stats.algnerrc;\n\tnet_stats->rx_missed_errors = adapter->stats.mpc;\n\n\t/* Tx Errors */\n\tnet_stats->tx_errors = adapter->stats.ecol +\n\t\t\t adapter->stats.latecol;\n\tnet_stats->tx_aborted_errors = adapter->stats.ecol;\n\tnet_stats->tx_window_errors = adapter->stats.latecol;\n\tnet_stats->tx_carrier_errors = adapter->stats.tncrs;\n\n\t/* Tx Dropped needs to be maintained elsewhere */\n\n\t/* Phy Stats */\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\t\tif ((adapter->link_speed == SPEED_1000) &&\n\t\t (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {\n\t\t\tphy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;\n\t\t\tadapter->phy_stats.idle_errors += phy_tmp;\n\t\t}\n\t}\n\n\t/* Management Stats */\n\tadapter->stats.mgptc += E1000_READ_REG(hw, E1000_MGTPTC);\n\tadapter->stats.mgprc += E1000_READ_REG(hw, E1000_MGTPRC);\n\tif (hw->mac.type > e1000_82580) {\n\t\tadapter->stats.o2bgptc += E1000_READ_REG(hw, E1000_O2BGPTC);\n\t\tadapter->stats.o2bspc += E1000_READ_REG(hw, E1000_O2BSPC);\n\t\tadapter->stats.b2ospc += E1000_READ_REG(hw, E1000_B2OSPC);\n\t\tadapter->stats.b2ogprc += E1000_READ_REG(hw, E1000_B2OGPRC);\n\t}\n}\n\nstatic irqreturn_t igb_msix_other(int irq, void *data)\n{\n\tstruct igb_adapter *adapter = data;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 icr = E1000_READ_REG(hw, E1000_ICR);\n\t/* reading ICR causes bit 31 of EICR to be cleared */\n\n\tif (icr & E1000_ICR_DRSTA)\n\t\tschedule_work(&adapter->reset_task);\n\n\tif (icr & E1000_ICR_DOUTSYNC) {\n\t\t/* HW is reporting DMA is out of sync */\n\t\tadapter->stats.doosync++;\n\t\t/* The DMA Out of Sync is also indication of a spoof event\n\t\t * in IOV mode. Check the Wrong VM Behavior register to\n\t\t * see if it is really a spoof event. */\n\t\tigb_check_wvbr(adapter);\n\t}\n\n\t/* Check for a mailbox event */\n\tif (icr & E1000_ICR_VMMB)\n\t\tigb_msg_task(adapter);\n\n\tif (icr & E1000_ICR_LSC) {\n\t\thw->mac.get_link_status = 1;\n\t\t/* guard against interrupt when we're going down */\n\t\tif (!test_bit(__IGB_DOWN, &adapter->state))\n\t\t\tmod_timer(&adapter->watchdog_timer, jiffies + 1);\n\t}\n\n#ifdef HAVE_PTP_1588_CLOCK\n\tif (icr & E1000_ICR_TS) {\n\t\tu32 tsicr = E1000_READ_REG(hw, E1000_TSICR);\n\n\t\tif (tsicr & E1000_TSICR_TXTS) {\n\t\t\t/* acknowledge the interrupt */\n\t\t\tE1000_WRITE_REG(hw, E1000_TSICR, E1000_TSICR_TXTS);\n\t\t\t/* retrieve hardware timestamp */\n\t\t\tschedule_work(&adapter->ptp_tx_work);\n\t\t}\n\t}\n#endif /* HAVE_PTP_1588_CLOCK */\n\n\t/* Check for MDD event */\n\tif (icr & E1000_ICR_MDDET)\n\t\tigb_process_mdd_event(adapter);\n\n\tE1000_WRITE_REG(hw, E1000_EIMS, adapter->eims_other);\n\n\treturn IRQ_HANDLED;\n}\n\nstatic void igb_write_itr(struct igb_q_vector *q_vector)\n{\n\tstruct igb_adapter *adapter = q_vector->adapter;\n\tu32 itr_val = q_vector->itr_val & 0x7FFC;\n\n\tif (!q_vector->set_itr)\n\t\treturn;\n\n\tif (!itr_val)\n\t\titr_val = 0x4;\n\n\tif (adapter->hw.mac.type == e1000_82575)\n\t\titr_val |= itr_val << 16;\n\telse\n\t\titr_val |= E1000_EITR_CNT_IGNR;\n\n\twritel(itr_val, q_vector->itr_register);\n\tq_vector->set_itr = 0;\n}\n\nstatic irqreturn_t igb_msix_ring(int irq, void *data)\n{\n\tstruct igb_q_vector *q_vector = data;\n\n\t/* Write the ITR value calculated from the previous interrupt. */\n\tigb_write_itr(q_vector);\n\n\tnapi_schedule(&q_vector->napi);\n\n\treturn IRQ_HANDLED;\n}\n\n#ifdef IGB_DCA\nstatic void igb_update_tx_dca(struct igb_adapter *adapter,\n\t\t\t struct igb_ring *tx_ring,\n\t\t\t int cpu)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 txctrl = dca3_get_tag(tx_ring->dev, cpu);\n\n\tif (hw->mac.type != e1000_82575)\n\t\ttxctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT_82576;\n\n\t/*\n\t * We can enable relaxed ordering for reads, but not writes when\n\t * DCA is enabled. This is due to a known issue in some chipsets\n\t * which will cause the DCA tag to be cleared.\n\t */\n\ttxctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |\n\t\t E1000_DCA_TXCTRL_DATA_RRO_EN |\n\t\t E1000_DCA_TXCTRL_DESC_DCA_EN;\n\n\tE1000_WRITE_REG(hw, E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);\n}\n\nstatic void igb_update_rx_dca(struct igb_adapter *adapter,\n\t\t\t struct igb_ring *rx_ring,\n\t\t\t int cpu)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);\n\n\tif (hw->mac.type != e1000_82575)\n\t\trxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT_82576;\n\n\t/*\n\t * We can enable relaxed ordering for reads, but not writes when\n\t * DCA is enabled. This is due to a known issue in some chipsets\n\t * which will cause the DCA tag to be cleared.\n\t */\n\trxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |\n\t\t E1000_DCA_RXCTRL_DESC_DCA_EN;\n\n\tE1000_WRITE_REG(hw, E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);\n}\n\nstatic void igb_update_dca(struct igb_q_vector *q_vector)\n{\n\tstruct igb_adapter *adapter = q_vector->adapter;\n\tint cpu = get_cpu();\n\n\tif (q_vector->cpu == cpu)\n\t\tgoto out_no_update;\n\n\tif (q_vector->tx.ring)\n\t\tigb_update_tx_dca(adapter, q_vector->tx.ring, cpu);\n\n\tif (q_vector->rx.ring)\n\t\tigb_update_rx_dca(adapter, q_vector->rx.ring, cpu);\n\n\tq_vector->cpu = cpu;\nout_no_update:\n\tput_cpu();\n}\n\nstatic void igb_setup_dca(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint i;\n\n\tif (!(adapter->flags & IGB_FLAG_DCA_ENABLED))\n\t\treturn;\n\n\t/* Always use CB2 mode, difference is masked in the CB driver. */\n\tE1000_WRITE_REG(hw, E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);\n\n\tfor (i = 0; i < adapter->num_q_vectors; i++) {\n\t\tadapter->q_vector[i]->cpu = -1;\n\t\tigb_update_dca(adapter->q_vector[i]);\n\t}\n}\n\nstatic int __igb_notify_dca(struct device *dev, void *data)\n{\n\tstruct net_device *netdev = dev_get_drvdata(dev);\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct pci_dev *pdev = adapter->pdev;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tunsigned long event = *(unsigned long *)data;\n\n\tswitch (event) {\n\tcase DCA_PROVIDER_ADD:\n\t\t/* if already enabled, don't do it again */\n\t\tif (adapter->flags & IGB_FLAG_DCA_ENABLED)\n\t\t\tbreak;\n\t\tif (dca_add_requester(dev) == E1000_SUCCESS) {\n\t\t\tadapter->flags |= IGB_FLAG_DCA_ENABLED;\n\t\t\tdev_info(pci_dev_to_dev(pdev), \"DCA enabled\\n\");\n\t\t\tigb_setup_dca(adapter);\n\t\t\tbreak;\n\t\t}\n\t\t/* Fall Through since DCA is disabled. */\n\tcase DCA_PROVIDER_REMOVE:\n\t\tif (adapter->flags & IGB_FLAG_DCA_ENABLED) {\n\t\t\t/* without this a class_device is left\n\t\t\t * hanging around in the sysfs model */\n\t\t\tdca_remove_requester(dev);\n\t\t\tdev_info(pci_dev_to_dev(pdev), \"DCA disabled\\n\");\n\t\t\tadapter->flags &= ~IGB_FLAG_DCA_ENABLED;\n\t\t\tE1000_WRITE_REG(hw, E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_DISABLE);\n\t\t}\n\t\tbreak;\n\t}\n\n\treturn E1000_SUCCESS;\n}\n\nstatic int igb_notify_dca(struct notifier_block *nb, unsigned long event,\n void *p)\n{\n\tint ret_val;\n\n\tret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,\n\t __igb_notify_dca);\n\n\treturn ret_val ? NOTIFY_BAD : NOTIFY_DONE;\n}\n#endif /* IGB_DCA */\n\nstatic int igb_vf_configure(struct igb_adapter *adapter, int vf)\n{\n\tunsigned char mac_addr[ETH_ALEN];\n\n\trandom_ether_addr(mac_addr);\n\tigb_set_vf_mac(adapter, vf, mac_addr);\n\n#ifdef IFLA_VF_MAX\n#ifdef HAVE_VF_SPOOFCHK_CONFIGURE\n\t/* By default spoof check is enabled for all VFs */\n\tadapter->vf_data[vf].spoofchk_enabled = true;\n#endif\n#endif\n\n\treturn true;\n}\n\nstatic void igb_ping_all_vfs(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 ping;\n\tint i;\n\n\tfor (i = 0 ; i < adapter->vfs_allocated_count; i++) {\n\t\tping = E1000_PF_CONTROL_MSG;\n\t\tif (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)\n\t\t\tping |= E1000_VT_MSGTYPE_CTS;\n\t\te1000_write_mbx(hw, &ping, 1, i);\n\t}\n}\n\n/**\n * igb_mta_set_ - Set multicast filter table address\n * @adapter: pointer to the adapter structure\n * @hash_value: determines the MTA register and bit to set\n *\n * The multicast table address is a register array of 32-bit registers.\n * The hash_value is used to determine what register the bit is in, the\n * current value is read, the new bit is OR'd in and the new value is\n * written back into the register.\n **/\nvoid igb_mta_set(struct igb_adapter *adapter, u32 hash_value)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 hash_bit, hash_reg, mta;\n\n\t/*\n\t * The MTA is a register array of 32-bit registers. It is\n\t * treated like an array of (32*mta_reg_count) bits. We want to\n\t * set bit BitArray[hash_value]. So we figure out what register\n\t * the bit is in, read it, OR in the new bit, then write\n\t * back the new value. The (hw->mac.mta_reg_count - 1) serves as a\n\t * mask to bits 31:5 of the hash value which gives us the\n\t * register we're modifying. The hash bit within that register\n\t * is determined by the lower 5 bits of the hash value.\n\t */\n\thash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);\n\thash_bit = hash_value & 0x1F;\n\n\tmta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);\n\n\tmta |= (1 << hash_bit);\n\n\tE1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);\n\tE1000_WRITE_FLUSH(hw);\n}\n\nstatic int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)\n{\n\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 vmolr = E1000_READ_REG(hw, E1000_VMOLR(vf));\n\tstruct vf_data_storage *vf_data = &adapter->vf_data[vf];\n\n\tvf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |\n\t IGB_VF_FLAG_MULTI_PROMISC);\n\tvmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);\n\n#ifdef IGB_ENABLE_VF_PROMISC\n\tif (*msgbuf & E1000_VF_SET_PROMISC_UNICAST) {\n\t\tvmolr |= E1000_VMOLR_ROPE;\n\t\tvf_data->flags |= IGB_VF_FLAG_UNI_PROMISC;\n\t\t*msgbuf &= ~E1000_VF_SET_PROMISC_UNICAST;\n\t}\n#endif\n\tif (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {\n\t\tvmolr |= E1000_VMOLR_MPME;\n\t\tvf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;\n\t\t*msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;\n\t} else {\n\t\t/*\n\t\t * if we have hashes and we are clearing a multicast promisc\n\t\t * flag we need to write the hashes to the MTA as this step\n\t\t * was previously skipped\n\t\t */\n\t\tif (vf_data->num_vf_mc_hashes > 30) {\n\t\t\tvmolr |= E1000_VMOLR_MPME;\n\t\t} else if (vf_data->num_vf_mc_hashes) {\n\t\t\tint j;\n\t\t\tvmolr |= E1000_VMOLR_ROMPE;\n\t\t\tfor (j = 0; j < vf_data->num_vf_mc_hashes; j++)\n\t\t\t\tigb_mta_set(adapter, vf_data->vf_mc_hashes[j]);\n\t\t}\n\t}\n\n\tE1000_WRITE_REG(hw, E1000_VMOLR(vf), vmolr);\n\n\t/* there are flags left unprocessed, likely not supported */\n\tif (*msgbuf & E1000_VT_MSGINFO_MASK)\n\t\treturn -EINVAL;\n\n\treturn 0;\n\n}\n\nstatic int igb_set_vf_multicasts(struct igb_adapter *adapter,\n\t\t\t\t u32 *msgbuf, u32 vf)\n{\n\tint n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;\n\tu16 *hash_list = (u16 *)&msgbuf[1];\n\tstruct vf_data_storage *vf_data = &adapter->vf_data[vf];\n\tint i;\n\n\t/* salt away the number of multicast addresses assigned\n\t * to this VF for later use to restore when the PF multi cast\n\t * list changes\n\t */\n\tvf_data->num_vf_mc_hashes = n;\n\n\t/* only up to 30 hash values supported */\n\tif (n > 30)\n\t\tn = 30;\n\n\t/* store the hashes for later use */\n\tfor (i = 0; i < n; i++)\n\t\tvf_data->vf_mc_hashes[i] = hash_list[i];\n\n\t/* Flush and reset the mta with the new values */\n\tigb_set_rx_mode(adapter->netdev);\n\n\treturn 0;\n}\n\nstatic void igb_restore_vf_multicasts(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct vf_data_storage *vf_data;\n\tint i, j;\n\n\tfor (i = 0; i < adapter->vfs_allocated_count; i++) {\n\t\tu32 vmolr = E1000_READ_REG(hw, E1000_VMOLR(i));\n\t\tvmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);\n\n\t\tvf_data = &adapter->vf_data[i];\n\n\t\tif ((vf_data->num_vf_mc_hashes > 30) ||\n\t\t (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {\n\t\t\tvmolr |= E1000_VMOLR_MPME;\n\t\t} else if (vf_data->num_vf_mc_hashes) {\n\t\t\tvmolr |= E1000_VMOLR_ROMPE;\n\t\t\tfor (j = 0; j < vf_data->num_vf_mc_hashes; j++)\n\t\t\t\tigb_mta_set(adapter, vf_data->vf_mc_hashes[j]);\n\t\t}\n\t\tE1000_WRITE_REG(hw, E1000_VMOLR(i), vmolr);\n\t}\n}\n\nstatic void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 pool_mask, reg, vid;\n\tu16 vlan_default;\n\tint i;\n\n\tpool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);\n\n\t/* Find the vlan filter for this id */\n\tfor (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {\n\t\treg = E1000_READ_REG(hw, E1000_VLVF(i));\n\n\t\t/* remove the vf from the pool */\n\t\treg &= ~pool_mask;\n\n\t\t/* if pool is empty then remove entry from vfta */\n\t\tif (!(reg & E1000_VLVF_POOLSEL_MASK) &&\n\t\t (reg & E1000_VLVF_VLANID_ENABLE)) {\n\t\t\treg = 0;\n\t\t\tvid = reg & E1000_VLVF_VLANID_MASK;\n\t\t\tigb_vfta_set(adapter, vid, FALSE);\n\t\t}\n\n\t\tE1000_WRITE_REG(hw, E1000_VLVF(i), reg);\n\t}\n\n\tadapter->vf_data[vf].vlans_enabled = 0;\n\n\tvlan_default = adapter->vf_data[vf].default_vf_vlan_id;\n\tif (vlan_default)\n\t\tigb_vlvf_set(adapter, vlan_default, true, vf);\n}\n\ns32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 reg, i;\n\n\t/* The vlvf table only exists on 82576 hardware and newer */\n\tif (hw->mac.type < e1000_82576)\n\t\treturn -1;\n\n\t/* we only need to do this if VMDq is enabled */\n\tif (!adapter->vmdq_pools)\n\t\treturn -1;\n\n\t/* Find the vlan filter for this id */\n\tfor (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {\n\t\treg = E1000_READ_REG(hw, E1000_VLVF(i));\n\t\tif ((reg & E1000_VLVF_VLANID_ENABLE) &&\n\t\t vid == (reg & E1000_VLVF_VLANID_MASK))\n\t\t\tbreak;\n\t}\n\n\tif (add) {\n\t\tif (i == E1000_VLVF_ARRAY_SIZE) {\n\t\t\t/* Did not find a matching VLAN ID entry that was\n\t\t\t * enabled. Search for a free filter entry, i.e.\n\t\t\t * one without the enable bit set\n\t\t\t */\n\t\t\tfor (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {\n\t\t\t\treg = E1000_READ_REG(hw, E1000_VLVF(i));\n\t\t\t\tif (!(reg & E1000_VLVF_VLANID_ENABLE))\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (i < E1000_VLVF_ARRAY_SIZE) {\n\t\t\t/* Found an enabled/available entry */\n\t\t\treg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);\n\n\t\t\t/* if !enabled we need to set this up in vfta */\n\t\t\tif (!(reg & E1000_VLVF_VLANID_ENABLE)) {\n\t\t\t\t/* add VID to filter table */\n\t\t\t\tigb_vfta_set(adapter, vid, TRUE);\n\t\t\t\treg |= E1000_VLVF_VLANID_ENABLE;\n\t\t\t}\n\t\t\treg &= ~E1000_VLVF_VLANID_MASK;\n\t\t\treg |= vid;\n\t\t\tE1000_WRITE_REG(hw, E1000_VLVF(i), reg);\n\n\t\t\t/* do not modify RLPML for PF devices */\n\t\t\tif (vf >= adapter->vfs_allocated_count)\n\t\t\t\treturn E1000_SUCCESS;\n\n\t\t\tif (!adapter->vf_data[vf].vlans_enabled) {\n\t\t\t\tu32 size;\n\t\t\t\treg = E1000_READ_REG(hw, E1000_VMOLR(vf));\n\t\t\t\tsize = reg & E1000_VMOLR_RLPML_MASK;\n\t\t\t\tsize += 4;\n\t\t\t\treg &= ~E1000_VMOLR_RLPML_MASK;\n\t\t\t\treg |= size;\n\t\t\t\tE1000_WRITE_REG(hw, E1000_VMOLR(vf), reg);\n\t\t\t}\n\n\t\t\tadapter->vf_data[vf].vlans_enabled++;\n\t\t}\n\t} else {\n\t\tif (i < E1000_VLVF_ARRAY_SIZE) {\n\t\t\t/* remove vf from the pool */\n\t\t\treg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));\n\t\t\t/* if pool is empty then remove entry from vfta */\n\t\t\tif (!(reg & E1000_VLVF_POOLSEL_MASK)) {\n\t\t\t\treg = 0;\n\t\t\t\tigb_vfta_set(adapter, vid, FALSE);\n\t\t\t}\n\t\t\tE1000_WRITE_REG(hw, E1000_VLVF(i), reg);\n\n\t\t\t/* do not modify RLPML for PF devices */\n\t\t\tif (vf >= adapter->vfs_allocated_count)\n\t\t\t\treturn E1000_SUCCESS;\n\n\t\t\tadapter->vf_data[vf].vlans_enabled--;\n\t\t\tif (!adapter->vf_data[vf].vlans_enabled) {\n\t\t\t\tu32 size;\n\t\t\t\treg = E1000_READ_REG(hw, E1000_VMOLR(vf));\n\t\t\t\tsize = reg & E1000_VMOLR_RLPML_MASK;\n\t\t\t\tsize -= 4;\n\t\t\t\treg &= ~E1000_VMOLR_RLPML_MASK;\n\t\t\t\treg |= size;\n\t\t\t\tE1000_WRITE_REG(hw, E1000_VMOLR(vf), reg);\n\t\t\t}\n\t\t}\n\t}\n\treturn E1000_SUCCESS;\n}\n\n#ifdef IFLA_VF_MAX\nstatic void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\tif (vid)\n\t\tE1000_WRITE_REG(hw, E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));\n\telse\n\t\tE1000_WRITE_REG(hw, E1000_VMVIR(vf), 0);\n}\n\nstatic int igb_ndo_set_vf_vlan(struct net_device *netdev,\n\t\t\t int vf, u16 vlan, u8 qos)\n{\n\tint err = 0;\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\t/* VLAN IDs accepted range 0-4094 */\n\tif ((vf >= adapter->vfs_allocated_count) || (vlan > VLAN_VID_MASK-1) || (qos > 7))\n\t\treturn -EINVAL;\n\tif (vlan || qos) {\n\t\terr = igb_vlvf_set(adapter, vlan, !!vlan, vf);\n\t\tif (err)\n\t\t\tgoto out;\n\t\tigb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);\n\t\tigb_set_vmolr(adapter, vf, !vlan);\n\t\tadapter->vf_data[vf].pf_vlan = vlan;\n\t\tadapter->vf_data[vf].pf_qos = qos;\n\t\tigb_set_vf_vlan_strip(adapter, vf, true);\n\t\tdev_info(&adapter->pdev->dev,\n\t\t\t \"Setting VLAN %d, QOS 0x%x on VF %d\\n\", vlan, qos, vf);\n\t\tif (test_bit(__IGB_DOWN, &adapter->state)) {\n\t\t\tdev_warn(&adapter->pdev->dev,\n\t\t\t\t \"The VF VLAN has been set,\"\n\t\t\t\t \" but the PF device is not up.\\n\");\n\t\t\tdev_warn(&adapter->pdev->dev,\n\t\t\t\t \"Bring the PF device up before\"\n\t\t\t\t \" attempting to use the VF device.\\n\");\n\t\t}\n\t} else {\n\t\tif (adapter->vf_data[vf].pf_vlan)\n\t\t\tdev_info(&adapter->pdev->dev,\n\t\t\t\t \"Clearing VLAN on VF %d\\n\", vf);\n\t\tigb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,\n\t\t\t\t false, vf);\n\t\tigb_set_vmvir(adapter, vlan, vf);\n\t\tigb_set_vmolr(adapter, vf, true);\n\t\tigb_set_vf_vlan_strip(adapter, vf, false);\n\t\tadapter->vf_data[vf].pf_vlan = 0;\n\t\tadapter->vf_data[vf].pf_qos = 0;\n }\nout:\n return err;\n}\n\n#ifdef HAVE_VF_SPOOFCHK_CONFIGURE\nstatic int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,\n\t\t\t\tbool setting)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 dtxswc, reg_offset;\n\n\tif (!adapter->vfs_allocated_count)\n\t\treturn -EOPNOTSUPP;\n\n\tif (vf >= adapter->vfs_allocated_count)\n\t\treturn -EINVAL;\n\n\treg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;\n\tdtxswc = E1000_READ_REG(hw, reg_offset);\n\tif (setting)\n\t\tdtxswc |= ((1 << vf) |\n\t\t\t (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));\n\telse\n\t\tdtxswc &= ~((1 << vf) |\n\t\t\t (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));\n\tE1000_WRITE_REG(hw, reg_offset, dtxswc);\n\n\tadapter->vf_data[vf].spoofchk_enabled = setting;\n\treturn E1000_SUCCESS;\n}\n#endif /* HAVE_VF_SPOOFCHK_CONFIGURE */\n#endif /* IFLA_VF_MAX */\n\nstatic int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint i;\n\tu32 reg;\n\n\t/* Find the vlan filter for this id */\n\tfor (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {\n\t\treg = E1000_READ_REG(hw, E1000_VLVF(i));\n\t\tif ((reg & E1000_VLVF_VLANID_ENABLE) &&\n\t\t vid == (reg & E1000_VLVF_VLANID_MASK))\n\t\t\tbreak;\n\t}\n\n\tif (i >= E1000_VLVF_ARRAY_SIZE)\n\t\ti = -1;\n\n\treturn i;\n}\n\nstatic int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;\n\tint vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);\n\tint err = 0;\n\n\tif (vid)\n\t\tigb_set_vf_vlan_strip(adapter, vf, true);\n\telse\n\t\tigb_set_vf_vlan_strip(adapter, vf, false);\n\n\t/* If in promiscuous mode we need to make sure the PF also has\n\t * the VLAN filter set.\n\t */\n\tif (add && (adapter->netdev->flags & IFF_PROMISC))\n\t\terr = igb_vlvf_set(adapter, vid, add,\n\t\t\t\t adapter->vfs_allocated_count);\n\tif (err)\n\t\tgoto out;\n\n\terr = igb_vlvf_set(adapter, vid, add, vf);\n\n\tif (err)\n\t\tgoto out;\n\n\t/* Go through all the checks to see if the VLAN filter should\n\t * be wiped completely.\n\t */\n\tif (!add && (adapter->netdev->flags & IFF_PROMISC)) {\n\t\tu32 vlvf, bits;\n\n\t\tint regndx = igb_find_vlvf_entry(adapter, vid);\n\t\tif (regndx < 0)\n\t\t\tgoto out;\n\t\t/* See if any other pools are set for this VLAN filter\n\t\t * entry other than the PF.\n\t\t */\n\t\tvlvf = bits = E1000_READ_REG(hw, E1000_VLVF(regndx));\n\t\tbits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +\n\t\t\t adapter->vfs_allocated_count);\n\t\t/* If the filter was removed then ensure PF pool bit\n\t\t * is cleared if the PF only added itself to the pool\n\t\t * because the PF is in promiscuous mode.\n\t\t */\n\t\tif ((vlvf & VLAN_VID_MASK) == vid &&\n#ifndef HAVE_VLAN_RX_REGISTER\n\t\t !test_bit(vid, adapter->active_vlans) &&\n#endif\n\t\t !bits)\n\t\t\tigb_vlvf_set(adapter, vid, add,\n\t\t\t\t adapter->vfs_allocated_count);\n\t}\n\nout:\n\treturn err;\n}\n\nstatic inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\t/* clear flags except flag that the PF has set the MAC */\n\tadapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;\n\tadapter->vf_data[vf].last_nack = jiffies;\n\n\t/* reset offloads to defaults */\n\tigb_set_vmolr(adapter, vf, true);\n\n\t/* reset vlans for device */\n\tigb_clear_vf_vfta(adapter, vf);\n#ifdef IFLA_VF_MAX\n\tif (adapter->vf_data[vf].pf_vlan)\n\t\tigb_ndo_set_vf_vlan(adapter->netdev, vf,\n\t\t\t\t adapter->vf_data[vf].pf_vlan,\n\t\t\t\t adapter->vf_data[vf].pf_qos);\n\telse\n\t\tigb_clear_vf_vfta(adapter, vf);\n#endif\n\n\t/* reset multicast table array for vf */\n\tadapter->vf_data[vf].num_vf_mc_hashes = 0;\n\n\t/* Flush and reset the mta with the new values */\n\tigb_set_rx_mode(adapter->netdev);\n\n\t/*\n\t * Reset the VFs TDWBAL and TDWBAH registers which are not\n\t * cleared by a VFLR\n\t */\n\tE1000_WRITE_REG(hw, E1000_TDWBAH(vf), 0);\n\tE1000_WRITE_REG(hw, E1000_TDWBAL(vf), 0);\n\tif (hw->mac.type == e1000_82576) {\n\t\tE1000_WRITE_REG(hw, E1000_TDWBAH(IGB_MAX_VF_FUNCTIONS + vf), 0);\n\t\tE1000_WRITE_REG(hw, E1000_TDWBAL(IGB_MAX_VF_FUNCTIONS + vf), 0);\n\t}\n}\n\nstatic void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)\n{\n\tunsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;\n\n\t/* generate a new mac address as we were hotplug removed/added */\n\tif (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))\n\t\trandom_ether_addr(vf_mac);\n\n\t/* process remaining reset events */\n\tigb_vf_reset(adapter, vf);\n}\n\nstatic void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tunsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;\n\tu32 reg, msgbuf[3];\n\tu8 *addr = (u8 *)(&msgbuf[1]);\n\n\t/* process all the same items cleared in a function level reset */\n\tigb_vf_reset(adapter, vf);\n\n\t/* set vf mac address */\n\tigb_del_mac_filter(adapter, vf_mac, vf);\n\tigb_add_mac_filter(adapter, vf_mac, vf);\n\n\t/* enable transmit and receive for vf */\n\treg = E1000_READ_REG(hw, E1000_VFTE);\n\tE1000_WRITE_REG(hw, E1000_VFTE, reg | (1 << vf));\n\treg = E1000_READ_REG(hw, E1000_VFRE);\n\tE1000_WRITE_REG(hw, E1000_VFRE, reg | (1 << vf));\n\n\tadapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;\n\n\t/* reply to reset with ack and vf mac address */\n\tmsgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;\n\tmemcpy(addr, vf_mac, 6);\n\te1000_write_mbx(hw, msgbuf, 3, vf);\n}\n\nstatic int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)\n{\n\t/*\n\t * The VF MAC Address is stored in a packed array of bytes\n\t * starting at the second 32 bit word of the msg array\n\t */\n\tunsigned char *addr = (unsigned char *)&msg[1];\n\tint err = -1;\n\n\tif (is_valid_ether_addr(addr))\n\t\terr = igb_set_vf_mac(adapter, vf, addr);\n\n\treturn err;\n}\n\nstatic void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct vf_data_storage *vf_data = &adapter->vf_data[vf];\n\tu32 msg = E1000_VT_MSGTYPE_NACK;\n\n\t/* if device isn't clear to send it shouldn't be reading either */\n\tif (!(vf_data->flags & IGB_VF_FLAG_CTS) &&\n\t time_after(jiffies, vf_data->last_nack + (2 * HZ))) {\n\t\te1000_write_mbx(hw, &msg, 1, vf);\n\t\tvf_data->last_nack = jiffies;\n\t}\n}\n\nstatic void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)\n{\n\tstruct pci_dev *pdev = adapter->pdev;\n\tu32 msgbuf[E1000_VFMAILBOX_SIZE];\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct vf_data_storage *vf_data = &adapter->vf_data[vf];\n\ts32 retval;\n\n\tretval = e1000_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);\n\n\tif (retval) {\n\t\tdev_err(pci_dev_to_dev(pdev), \"Error receiving message from VF\\n\");\n\t\treturn;\n\t}\n\n\t/* this is a message we already processed, do nothing */\n\tif (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))\n\t\treturn;\n\n\t/*\n\t * until the vf completes a reset it should not be\n\t * allowed to start any configuration.\n\t */\n\n\tif (msgbuf[0] == E1000_VF_RESET) {\n\t\tigb_vf_reset_msg(adapter, vf);\n\t\treturn;\n\t}\n\n\tif (!(vf_data->flags & IGB_VF_FLAG_CTS)) {\n\t\tmsgbuf[0] = E1000_VT_MSGTYPE_NACK;\n\t\tif (time_after(jiffies, vf_data->last_nack + (2 * HZ))) {\n\t\t\te1000_write_mbx(hw, msgbuf, 1, vf);\n\t\t\tvf_data->last_nack = jiffies;\n\t\t}\n\t\treturn;\n\t}\n\n\tswitch ((msgbuf[0] & 0xFFFF)) {\n\tcase E1000_VF_SET_MAC_ADDR:\n\t\tretval = -EINVAL;\n#ifndef IGB_DISABLE_VF_MAC_SET\n\t\tif (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))\n\t\t\tretval = igb_set_vf_mac_addr(adapter, msgbuf, vf);\n\t\telse\n\t\t\tDPRINTK(DRV, INFO,\n\t\t\t\t\"VF %d attempted to override administratively \"\n\t\t\t\t\"set MAC address\\nReload the VF driver to \"\n\t\t\t\t\"resume operations\\n\", vf);\n#endif\n\t\tbreak;\n\tcase E1000_VF_SET_PROMISC:\n\t\tretval = igb_set_vf_promisc(adapter, msgbuf, vf);\n\t\tbreak;\n\tcase E1000_VF_SET_MULTICAST:\n\t\tretval = igb_set_vf_multicasts(adapter, msgbuf, vf);\n\t\tbreak;\n\tcase E1000_VF_SET_LPE:\n\t\tretval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);\n\t\tbreak;\n\tcase E1000_VF_SET_VLAN:\n\t\tretval = -1;\n#ifdef IFLA_VF_MAX\n\t\tif (vf_data->pf_vlan)\n\t\t\tDPRINTK(DRV, INFO,\n\t\t\t\t\"VF %d attempted to override administratively \"\n\t\t\t\t\"set VLAN tag\\nReload the VF driver to \"\n\t\t\t\t\"resume operations\\n\", vf);\n\t\telse\n#endif\n\t\t\tretval = igb_set_vf_vlan(adapter, msgbuf, vf);\n\t\tbreak;\n\tdefault:\n\t\tdev_err(pci_dev_to_dev(pdev), \"Unhandled Msg %08x\\n\", msgbuf[0]);\n\t\tretval = -E1000_ERR_MBX;\n\t\tbreak;\n\t}\n\n\t/* notify the VF of the results of what it sent us */\n\tif (retval)\n\t\tmsgbuf[0] |= E1000_VT_MSGTYPE_NACK;\n\telse\n\t\tmsgbuf[0] |= E1000_VT_MSGTYPE_ACK;\n\n\tmsgbuf[0] |= E1000_VT_MSGTYPE_CTS;\n\n\te1000_write_mbx(hw, msgbuf, 1, vf);\n}\n\nstatic void igb_msg_task(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 vf;\n\n\tfor (vf = 0; vf < adapter->vfs_allocated_count; vf++) {\n\t\t/* process any reset requests */\n\t\tif (!e1000_check_for_rst(hw, vf))\n\t\t\tigb_vf_reset_event(adapter, vf);\n\n\t\t/* process any messages pending */\n\t\tif (!e1000_check_for_msg(hw, vf))\n\t\t\tigb_rcv_msg_from_vf(adapter, vf);\n\n\t\t/* process any acks */\n\t\tif (!e1000_check_for_ack(hw, vf))\n\t\t\tigb_rcv_ack_from_vf(adapter, vf);\n\t}\n}\n\n/**\n * igb_set_uta - Set unicast filter table address\n * @adapter: board private structure\n *\n * The unicast table address is a register array of 32-bit registers.\n * The table is meant to be used in a way similar to how the MTA is used\n * however due to certain limitations in the hardware it is necessary to\n * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous\n * enable bit to allow vlan tag stripping when promiscuous mode is enabled\n **/\nstatic void igb_set_uta(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint i;\n\n\t/* The UTA table only exists on 82576 hardware and newer */\n\tif (hw->mac.type < e1000_82576)\n\t\treturn;\n\n\t/* we only need to do this if VMDq is enabled */\n\tif (!adapter->vmdq_pools)\n\t\treturn;\n\n\tfor (i = 0; i < hw->mac.uta_reg_count; i++)\n\t\tE1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, ~0);\n}\n\n/**\n * igb_intr_msi - Interrupt Handler\n * @irq: interrupt number\n * @data: pointer to a network interface device structure\n **/\nstatic irqreturn_t igb_intr_msi(int irq, void *data)\n{\n\tstruct igb_adapter *adapter = data;\n\tstruct igb_q_vector *q_vector = adapter->q_vector[0];\n\tstruct e1000_hw *hw = &adapter->hw;\n\t/* read ICR disables interrupts using IAM */\n\tu32 icr = E1000_READ_REG(hw, E1000_ICR);\n\n\tigb_write_itr(q_vector);\n\n\tif (icr & E1000_ICR_DRSTA)\n\t\tschedule_work(&adapter->reset_task);\n\n\tif (icr & E1000_ICR_DOUTSYNC) {\n\t\t/* HW is reporting DMA is out of sync */\n\t\tadapter->stats.doosync++;\n\t}\n\n\tif (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {\n\t\thw->mac.get_link_status = 1;\n\t\tif (!test_bit(__IGB_DOWN, &adapter->state))\n\t\t\tmod_timer(&adapter->watchdog_timer, jiffies + 1);\n\t}\n\n#ifdef HAVE_PTP_1588_CLOCK\n\tif (icr & E1000_ICR_TS) {\n\t\tu32 tsicr = E1000_READ_REG(hw, E1000_TSICR);\n\n\t\tif (tsicr & E1000_TSICR_TXTS) {\n\t\t\t/* acknowledge the interrupt */\n\t\t\tE1000_WRITE_REG(hw, E1000_TSICR, E1000_TSICR_TXTS);\n\t\t\t/* retrieve hardware timestamp */\n\t\t\tschedule_work(&adapter->ptp_tx_work);\n\t\t}\n\t}\n#endif /* HAVE_PTP_1588_CLOCK */\n\n\tnapi_schedule(&q_vector->napi);\n\n\treturn IRQ_HANDLED;\n}\n\n/**\n * igb_intr - Legacy Interrupt Handler\n * @irq: interrupt number\n * @data: pointer to a network interface device structure\n **/\nstatic irqreturn_t igb_intr(int irq, void *data)\n{\n\tstruct igb_adapter *adapter = data;\n\tstruct igb_q_vector *q_vector = adapter->q_vector[0];\n\tstruct e1000_hw *hw = &adapter->hw;\n\t/* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No\n\t * need for the IMC write */\n\tu32 icr = E1000_READ_REG(hw, E1000_ICR);\n\n\t/* IMS will not auto-mask if INT_ASSERTED is not set, and if it is\n\t * not set, then the adapter didn't send an interrupt */\n\tif (!(icr & E1000_ICR_INT_ASSERTED))\n\t\treturn IRQ_NONE;\n\n\tigb_write_itr(q_vector);\n\n\tif (icr & E1000_ICR_DRSTA)\n\t\tschedule_work(&adapter->reset_task);\n\n\tif (icr & E1000_ICR_DOUTSYNC) {\n\t\t/* HW is reporting DMA is out of sync */\n\t\tadapter->stats.doosync++;\n\t}\n\n\tif (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {\n\t\thw->mac.get_link_status = 1;\n\t\t/* guard against interrupt when we're going down */\n\t\tif (!test_bit(__IGB_DOWN, &adapter->state))\n\t\t\tmod_timer(&adapter->watchdog_timer, jiffies + 1);\n\t}\n\n#ifdef HAVE_PTP_1588_CLOCK\n\tif (icr & E1000_ICR_TS) {\n\t\tu32 tsicr = E1000_READ_REG(hw, E1000_TSICR);\n\n\t\tif (tsicr & E1000_TSICR_TXTS) {\n\t\t\t/* acknowledge the interrupt */\n\t\t\tE1000_WRITE_REG(hw, E1000_TSICR, E1000_TSICR_TXTS);\n\t\t\t/* retrieve hardware timestamp */\n\t\t\tschedule_work(&adapter->ptp_tx_work);\n\t\t}\n\t}\n#endif /* HAVE_PTP_1588_CLOCK */\n\n\tnapi_schedule(&q_vector->napi);\n\n\treturn IRQ_HANDLED;\n}\n\nvoid igb_ring_irq_enable(struct igb_q_vector *q_vector)\n{\n\tstruct igb_adapter *adapter = q_vector->adapter;\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\tif ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||\n\t (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {\n\t\tif ((adapter->num_q_vectors == 1) && !adapter->vf_data)\n\t\t\tigb_set_itr(q_vector);\n\t\telse\n\t\t\tigb_update_ring_itr(q_vector);\n\t}\n\n\tif (!test_bit(__IGB_DOWN, &adapter->state)) {\n\t\tif (adapter->msix_entries)\n\t\t\tE1000_WRITE_REG(hw, E1000_EIMS, q_vector->eims_value);\n\t\telse\n\t\t\tigb_irq_enable(adapter);\n\t}\n}\n\n/**\n * igb_poll - NAPI Rx polling callback\n * @napi: napi polling structure\n * @budget: count of how many packets we should handle\n **/\nstatic int igb_poll(struct napi_struct *napi, int budget)\n{\n\tstruct igb_q_vector *q_vector = container_of(napi, struct igb_q_vector, napi);\n\tbool clean_complete = true;\n\n#ifdef IGB_DCA\n\tif (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)\n\t\tigb_update_dca(q_vector);\n#endif\n\tif (q_vector->tx.ring)\n\t\tclean_complete = igb_clean_tx_irq(q_vector);\n\n\tif (q_vector->rx.ring)\n\t\tclean_complete &= igb_clean_rx_irq(q_vector, budget);\n\n#ifndef HAVE_NETDEV_NAPI_LIST\n\t/* if netdev is disabled we need to stop polling */\n\tif (!netif_running(q_vector->adapter->netdev))\n\t\tclean_complete = true;\n\n#endif\n\t/* If all work not completed, return budget and keep polling */\n\tif (!clean_complete)\n\t\treturn budget;\n\n\t/* If not enough Rx work done, exit the polling mode */\n\tnapi_complete(napi);\n\tigb_ring_irq_enable(q_vector);\n\n\treturn 0;\n}\n\n/**\n * igb_clean_tx_irq - Reclaim resources after transmit completes\n * @q_vector: pointer to q_vector containing needed info\n * returns TRUE if ring is completely cleaned\n **/\nstatic bool igb_clean_tx_irq(struct igb_q_vector *q_vector)\n{\n\tstruct igb_adapter *adapter = q_vector->adapter;\n\tstruct igb_ring *tx_ring = q_vector->tx.ring;\n\tstruct igb_tx_buffer *tx_buffer;\n\tunion e1000_adv_tx_desc *tx_desc;\n\tunsigned int total_bytes = 0, total_packets = 0;\n\tunsigned int budget = q_vector->tx.work_limit;\n\tunsigned int i = tx_ring->next_to_clean;\n\n\tif (test_bit(__IGB_DOWN, &adapter->state))\n\t\treturn true;\n\n\ttx_buffer = &tx_ring->tx_buffer_info[i];\n\ttx_desc = IGB_TX_DESC(tx_ring, i);\n\ti -= tx_ring->count;\n\n\tdo {\n\t\tunion e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;\n\n\t\t/* if next_to_watch is not set then there is no work pending */\n\t\tif (!eop_desc)\n\t\t\tbreak;\n\n\t\t/* prevent any other reads prior to eop_desc */\n\t\tread_barrier_depends();\n\n\t\t/* if DD is not set pending work has not been completed */\n\t\tif (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))\n\t\t\tbreak;\n\n\t\t/* clear next_to_watch to prevent false hangs */\n\t\ttx_buffer->next_to_watch = NULL;\n\n\t\t/* update the statistics for this packet */\n\t\ttotal_bytes += tx_buffer->bytecount;\n\t\ttotal_packets += tx_buffer->gso_segs;\n\n\t\t/* free the skb */\n\t\tdev_kfree_skb_any(tx_buffer->skb);\n\n\t\t/* unmap skb header data */\n\t\tdma_unmap_single(tx_ring->dev,\n\t\t dma_unmap_addr(tx_buffer, dma),\n\t\t dma_unmap_len(tx_buffer, len),\n\t\t DMA_TO_DEVICE);\n\n\t\t/* clear tx_buffer data */\n\t\ttx_buffer->skb = NULL;\n\t\tdma_unmap_len_set(tx_buffer, len, 0);\n\n\t\t/* clear last DMA location and unmap remaining buffers */\n\t\twhile (tx_desc != eop_desc) {\n\t\t\ttx_buffer++;\n\t\t\ttx_desc++;\n\t\t\ti++;\n\t\t\tif (unlikely(!i)) {\n\t\t\t\ti -= tx_ring->count;\n\t\t\t\ttx_buffer = tx_ring->tx_buffer_info;\n\t\t\t\ttx_desc = IGB_TX_DESC(tx_ring, 0);\n\t\t\t}\n\n\t\t\t/* unmap any remaining paged data */\n\t\t\tif (dma_unmap_len(tx_buffer, len)) {\n\t\t\t\tdma_unmap_page(tx_ring->dev,\n\t\t\t\t dma_unmap_addr(tx_buffer, dma),\n\t\t\t\t dma_unmap_len(tx_buffer, len),\n\t\t\t\t DMA_TO_DEVICE);\n\t\t\t\tdma_unmap_len_set(tx_buffer, len, 0);\n\t\t\t}\n\t\t}\n\n\t\t/* move us one more past the eop_desc for start of next pkt */\n\t\ttx_buffer++;\n\t\ttx_desc++;\n\t\ti++;\n\t\tif (unlikely(!i)) {\n\t\t\ti -= tx_ring->count;\n\t\t\ttx_buffer = tx_ring->tx_buffer_info;\n\t\t\ttx_desc = IGB_TX_DESC(tx_ring, 0);\n\t\t}\n\n\t\t/* issue prefetch for next Tx descriptor */\n\t\tprefetch(tx_desc);\n\n\t\t/* update budget accounting */\n\t\tbudget--;\n\t} while (likely(budget));\n\n\tnetdev_tx_completed_queue(txring_txq(tx_ring),\n\t\t\t\t total_packets, total_bytes);\n\n\ti += tx_ring->count;\n\ttx_ring->next_to_clean = i;\n\ttx_ring->tx_stats.bytes += total_bytes;\n\ttx_ring->tx_stats.packets += total_packets;\n\tq_vector->tx.total_bytes += total_bytes;\n\tq_vector->tx.total_packets += total_packets;\n\n#ifdef DEBUG\n\tif (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags) &&\n\t !(adapter->disable_hw_reset && adapter->tx_hang_detected)) {\n#else\n\tif (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {\n#endif\n\t\tstruct e1000_hw *hw = &adapter->hw;\n\n\t\t/* Detect a transmit hang in hardware, this serializes the\n\t\t * check with the clearing of time_stamp and movement of i */\n\t\tclear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);\n\t\tif (tx_buffer->next_to_watch &&\n\t\t time_after(jiffies, tx_buffer->time_stamp +\n\t\t (adapter->tx_timeout_factor * HZ))\n\t\t && !(E1000_READ_REG(hw, E1000_STATUS) &\n\t\t E1000_STATUS_TXOFF)) {\n\n\t\t\t/* detected Tx unit hang */\n#ifdef DEBUG\n\t\t\tadapter->tx_hang_detected = TRUE;\n\t\t\tif (adapter->disable_hw_reset) {\n\t\t\t\tDPRINTK(DRV, WARNING,\n\t\t\t\t\t\"Deactivating netdev watchdog timer\\n\");\n\t\t\t\tif (del_timer(&netdev_ring(tx_ring)->watchdog_timer))\n\t\t\t\t\tdev_put(netdev_ring(tx_ring));\n#ifndef HAVE_NET_DEVICE_OPS\n\t\t\t\tnetdev_ring(tx_ring)->tx_timeout = NULL;\n#endif\n\t\t\t}\n#endif /* DEBUG */\n\t\t\tdev_err(tx_ring->dev,\n\t\t\t\t\"Detected Tx Unit Hang\\n\"\n\t\t\t\t\" Tx Queue <%d>\\n\"\n\t\t\t\t\" TDH <%x>\\n\"\n\t\t\t\t\" TDT <%x>\\n\"\n\t\t\t\t\" next_to_use <%x>\\n\"\n\t\t\t\t\" next_to_clean <%x>\\n\"\n\t\t\t\t\"buffer_info[next_to_clean]\\n\"\n\t\t\t\t\" time_stamp <%lx>\\n\"\n\t\t\t\t\" next_to_watch <%p>\\n\"\n\t\t\t\t\" jiffies <%lx>\\n\"\n\t\t\t\t\" desc.status <%x>\\n\",\n\t\t\t\ttx_ring->queue_index,\n\t\t\t\tE1000_READ_REG(hw, E1000_TDH(tx_ring->reg_idx)),\n\t\t\t\treadl(tx_ring->tail),\n\t\t\t\ttx_ring->next_to_use,\n\t\t\t\ttx_ring->next_to_clean,\n\t\t\t\ttx_buffer->time_stamp,\n\t\t\t\ttx_buffer->next_to_watch,\n\t\t\t\tjiffies,\n\t\t\t\ttx_buffer->next_to_watch->wb.status);\n\t\t\tif (netif_is_multiqueue(netdev_ring(tx_ring)))\n\t\t\t\tnetif_stop_subqueue(netdev_ring(tx_ring),\n\t\t\t\t\t\t ring_queue_index(tx_ring));\n\t\t\telse\n\t\t\t\tnetif_stop_queue(netdev_ring(tx_ring));\n\n\t\t\t/* we are about to reset, no point in enabling stuff */\n\t\t\treturn true;\n\t\t}\n\t}\n\n#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)\n\tif (unlikely(total_packets &&\n\t\t netif_carrier_ok(netdev_ring(tx_ring)) &&\n\t\t igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {\n\t\t/* Make sure that anybody stopping the queue after this\n\t\t * sees the new next_to_clean.\n\t\t */\n\t\tsmp_mb();\n\t\tif (netif_is_multiqueue(netdev_ring(tx_ring))) {\n\t\t\tif (__netif_subqueue_stopped(netdev_ring(tx_ring),\n\t\t\t\t\t\t ring_queue_index(tx_ring)) &&\n\t\t\t !(test_bit(__IGB_DOWN, &adapter->state))) {\n\t\t\t\tnetif_wake_subqueue(netdev_ring(tx_ring),\n\t\t\t\t\t\t ring_queue_index(tx_ring));\n\t\t\t\ttx_ring->tx_stats.restart_queue++;\n\t\t\t}\n\t\t} else {\n\t\t\tif (netif_queue_stopped(netdev_ring(tx_ring)) &&\n\t\t\t !(test_bit(__IGB_DOWN, &adapter->state))) {\n\t\t\t\tnetif_wake_queue(netdev_ring(tx_ring));\n\t\t\t\ttx_ring->tx_stats.restart_queue++;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn !!budget;\n}\n\n#ifdef HAVE_VLAN_RX_REGISTER\n/**\n * igb_receive_skb - helper function to handle rx indications\n * @q_vector: structure containing interrupt and ring information\n * @skb: packet to send up\n **/\nstatic void igb_receive_skb(struct igb_q_vector *q_vector,\n struct sk_buff *skb)\n{\n\tstruct vlan_group **vlgrp = netdev_priv(skb->dev);\n\n\tif (IGB_CB(skb)->vid) {\n\t\tif (*vlgrp) {\n\t\t\tvlan_gro_receive(&q_vector->napi, *vlgrp,\n\t\t\t\t\t IGB_CB(skb)->vid, skb);\n\t\t} else {\n\t\t\tdev_kfree_skb_any(skb);\n\t\t}\n\t} else {\n\t\tnapi_gro_receive(&q_vector->napi, skb);\n\t}\n}\n\n#endif /* HAVE_VLAN_RX_REGISTER */\n#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT\n/**\n * igb_reuse_rx_page - page flip buffer and store it back on the ring\n * @rx_ring: rx descriptor ring to store buffers on\n * @old_buff: donor buffer to have page reused\n *\n * Synchronizes page for reuse by the adapter\n **/\nstatic void igb_reuse_rx_page(struct igb_ring *rx_ring,\n\t\t\t struct igb_rx_buffer *old_buff)\n{\n\tstruct igb_rx_buffer *new_buff;\n\tu16 nta = rx_ring->next_to_alloc;\n\n\tnew_buff = &rx_ring->rx_buffer_info[nta];\n\n\t/* update, and store next to alloc */\n\tnta++;\n\trx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;\n\n\t/* transfer page from old buffer to new buffer */\n\tmemcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));\n\n\t/* sync the buffer for use by the device */\n\tdma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,\n\t\t\t\t\t old_buff->page_offset,\n\t\t\t\t\t IGB_RX_BUFSZ,\n\t\t\t\t\t DMA_FROM_DEVICE);\n}\n\nstatic bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,\n\t\t\t\t struct page *page,\n\t\t\t\t unsigned int truesize)\n{\n\t/* avoid re-using remote pages */\n\tif (unlikely(page_to_nid(page) != numa_node_id()))\n\t\treturn false;\n\n#if (PAGE_SIZE < 8192)\n\t/* if we are only owner of page we can reuse it */\n\tif (unlikely(page_count(page) != 1))\n\t\treturn false;\n\n\t/* flip page offset to other buffer */\n\trx_buffer->page_offset ^= IGB_RX_BUFSZ;\n\n#else\n\t/* move offset up to the next cache line */\n\trx_buffer->page_offset += truesize;\n\n\tif (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))\n\t\treturn false;\n#endif\n\n\t/* bump ref count on page before it is given to the stack */\n\tget_page(page);\n\n\treturn true;\n}\n\n/**\n * igb_add_rx_frag - Add contents of Rx buffer to sk_buff\n * @rx_ring: rx descriptor ring to transact packets on\n * @rx_buffer: buffer containing page to add\n * @rx_desc: descriptor containing length of buffer written by hardware\n * @skb: sk_buff to place the data into\n *\n * This function will add the data contained in rx_buffer->page to the skb.\n * This is done either through a direct copy if the data in the buffer is\n * less than the skb header size, otherwise it will just attach the page as\n * a frag to the skb.\n *\n * The function will then update the page offset if necessary and return\n * true if the buffer can be reused by the adapter.\n **/\nstatic bool igb_add_rx_frag(struct igb_ring *rx_ring,\n\t\t\t struct igb_rx_buffer *rx_buffer,\n\t\t\t union e1000_adv_rx_desc *rx_desc,\n\t\t\t struct sk_buff *skb)\n{\n\tstruct page *page = rx_buffer->page;\n\tunsigned int size = le16_to_cpu(rx_desc->wb.upper.length);\n#if (PAGE_SIZE < 8192)\n\tunsigned int truesize = IGB_RX_BUFSZ;\n#else\n\tunsigned int truesize = ALIGN(size, L1_CACHE_BYTES);\n#endif\n\n\tif ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {\n\t\tunsigned char *va = page_address(page) + rx_buffer->page_offset;\n\n#ifdef HAVE_PTP_1588_CLOCK\n\t\tif (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {\n\t\t\tigb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);\n\t\t\tva += IGB_TS_HDR_LEN;\n\t\t\tsize -= IGB_TS_HDR_LEN;\n\t\t}\n#endif /* HAVE_PTP_1588_CLOCK */\n\n\t\tmemcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));\n\n\t\t/* we can reuse buffer as-is, just make sure it is local */\n\t\tif (likely(page_to_nid(page) == numa_node_id()))\n\t\t\treturn true;\n\n\t\t/* this page cannot be reused so discard it */\n\t\tput_page(page);\n\t\treturn false;\n\t}\n\n\tskb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,\n\t\t\trx_buffer->page_offset, size, truesize);\n\n\treturn igb_can_reuse_rx_page(rx_buffer, page, truesize);\n}\n\nstatic struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,\n\t\t\t\t\t union e1000_adv_rx_desc *rx_desc,\n\t\t\t\t\t struct sk_buff *skb)\n{\n\tstruct igb_rx_buffer *rx_buffer;\n\tstruct page *page;\n\n\trx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];\n\n\tpage = rx_buffer->page;\n\tprefetchw(page);\n\n\tif (likely(!skb)) {\n\t\tvoid *page_addr = page_address(page) +\n\t\t\t\t rx_buffer->page_offset;\n\n\t\t/* prefetch first cache line of first page */\n\t\tprefetch(page_addr);\n#if L1_CACHE_BYTES < 128\n\t\tprefetch(page_addr + L1_CACHE_BYTES);\n#endif\n\n\t\t/* allocate a skb to store the frags */\n\t\tskb = netdev_alloc_skb_ip_align(rx_ring->netdev,\n\t\t\t\t\t\tIGB_RX_HDR_LEN);\n\t\tif (unlikely(!skb)) {\n\t\t\trx_ring->rx_stats.alloc_failed++;\n\t\t\treturn NULL;\n\t\t}\n\n\t\t/*\n\t\t * we will be copying header into skb->data in\n\t\t * pskb_may_pull so it is in our interest to prefetch\n\t\t * it now to avoid a possible cache miss\n\t\t */\n\t\tprefetchw(skb->data);\n\t}\n\n\t/* we are reusing so sync this buffer for CPU use */\n\tdma_sync_single_range_for_cpu(rx_ring->dev,\n\t\t\t\t rx_buffer->dma,\n\t\t\t\t rx_buffer->page_offset,\n\t\t\t\t IGB_RX_BUFSZ,\n\t\t\t\t DMA_FROM_DEVICE);\n\n\t/* pull page into skb */\n\tif (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {\n\t\t/* hand second half of page back to the ring */\n\t\tigb_reuse_rx_page(rx_ring, rx_buffer);\n\t} else {\n\t\t/* we are not reusing the buffer so unmap it */\n\t\tdma_unmap_page(rx_ring->dev, rx_buffer->dma,\n\t\t\t PAGE_SIZE, DMA_FROM_DEVICE);\n\t}\n\n\t/* clear contents of rx_buffer */\n\trx_buffer->page = NULL;\n\n\treturn skb;\n}\n\n#endif\nstatic inline void igb_rx_checksum(struct igb_ring *ring,\n\t\t\t\t union e1000_adv_rx_desc *rx_desc,\n\t\t\t\t struct sk_buff *skb)\n{\n\tskb_checksum_none_assert(skb);\n\n\t/* Ignore Checksum bit is set */\n\tif (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))\n\t\treturn;\n\n\t/* Rx checksum disabled via ethtool */\n\tif (!(netdev_ring(ring)->features & NETIF_F_RXCSUM))\n\t\treturn;\n\n\t/* TCP/UDP checksum error bit is set */\n\tif (igb_test_staterr(rx_desc,\n\t\t\t E1000_RXDEXT_STATERR_TCPE |\n\t\t\t E1000_RXDEXT_STATERR_IPE)) {\n\t\t/*\n\t\t * work around errata with sctp packets where the TCPE aka\n\t\t * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)\n\t\t * packets, (aka let the stack check the crc32c)\n\t\t */\n\t\tif (!((skb->len == 60) &&\n\t\t test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags)))\n\t\t\tring->rx_stats.csum_err++;\n\n\t\t/* let the stack verify checksum errors */\n\t\treturn;\n\t}\n\t/* It must be a TCP or UDP packet with a valid checksum */\n\tif (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |\n\t\t\t\t E1000_RXD_STAT_UDPCS))\n\t\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n}\n\n#ifdef NETIF_F_RXHASH\nstatic inline void igb_rx_hash(struct igb_ring *ring,\n\t\t\t union e1000_adv_rx_desc *rx_desc,\n\t\t\t struct sk_buff *skb)\n{\n\tif (netdev_ring(ring)->features & NETIF_F_RXHASH)\n\t\tskb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),\n\t\t\t PKT_HASH_TYPE_L3);\n}\n\n#endif\n#ifndef IGB_NO_LRO\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n/**\n * igb_merge_active_tail - merge active tail into lro skb\n * @tail: pointer to active tail in frag_list\n *\n * This function merges the length and data of an active tail into the\n * skb containing the frag_list. It resets the tail's pointer to the head,\n * but it leaves the heads pointer to tail intact.\n **/\nstatic inline struct sk_buff *igb_merge_active_tail(struct sk_buff *tail)\n{\n\tstruct sk_buff *head = IGB_CB(tail)->head;\n\n\tif (!head)\n\t\treturn tail;\n\n\thead->len += tail->len;\n\thead->data_len += tail->len;\n\thead->truesize += tail->len;\n\n\tIGB_CB(tail)->head = NULL;\n\n\treturn head;\n}\n\n/**\n * igb_add_active_tail - adds an active tail into the skb frag_list\n * @head: pointer to the start of the skb\n * @tail: pointer to active tail to add to frag_list\n *\n * This function adds an active tail to the end of the frag list. This tail\n * will still be receiving data so we cannot yet ad it's stats to the main\n * skb. That is done via igb_merge_active_tail.\n **/\nstatic inline void igb_add_active_tail(struct sk_buff *head, struct sk_buff *tail)\n{\n\tstruct sk_buff *old_tail = IGB_CB(head)->tail;\n\n\tif (old_tail) {\n\t\tigb_merge_active_tail(old_tail);\n\t\told_tail->next = tail;\n\t} else {\n\t\tskb_shinfo(head)->frag_list = tail;\n\t}\n\n\tIGB_CB(tail)->head = head;\n\tIGB_CB(head)->tail = tail;\n\n\tIGB_CB(head)->append_cnt++;\n}\n\n/**\n * igb_close_active_frag_list - cleanup pointers on a frag_list skb\n * @head: pointer to head of an active frag list\n *\n * This function will clear the frag_tail_tracker pointer on an active\n * frag_list and returns true if the pointer was actually set\n **/\nstatic inline bool igb_close_active_frag_list(struct sk_buff *head)\n{\n\tstruct sk_buff *tail = IGB_CB(head)->tail;\n\n\tif (!tail)\n\t\treturn false;\n\n\tigb_merge_active_tail(tail);\n\n\tIGB_CB(head)->tail = NULL;\n\n\treturn true;\n}\n\n#endif /* CONFIG_IGB_DISABLE_PACKET_SPLIT */\n/**\n * igb_can_lro - returns true if packet is TCP/IPV4 and LRO is enabled\n * @adapter: board private structure\n * @rx_desc: pointer to the rx descriptor\n * @skb: pointer to the skb to be merged\n *\n **/\nstatic inline bool igb_can_lro(struct igb_ring *rx_ring,\n\t\t\t union e1000_adv_rx_desc *rx_desc,\n\t\t\t struct sk_buff *skb)\n{\n\tstruct iphdr *iph = (struct iphdr *)skb->data;\n\t__le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;\n\n\t/* verify hardware indicates this is IPv4/TCP */\n\tif((!(pkt_info & cpu_to_le16(E1000_RXDADV_PKTTYPE_TCP)) ||\n\t !(pkt_info & cpu_to_le16(E1000_RXDADV_PKTTYPE_IPV4))))\n\t\treturn false;\n\n\t/* .. and LRO is enabled */\n\tif (!(netdev_ring(rx_ring)->features & NETIF_F_LRO))\n\t\treturn false;\n\n\t/* .. and we are not in promiscuous mode */\n\tif (netdev_ring(rx_ring)->flags & IFF_PROMISC)\n\t\treturn false;\n\n\t/* .. and the header is large enough for us to read IP/TCP fields */\n\tif (!pskb_may_pull(skb, sizeof(struct igb_lrohdr)))\n\t\treturn false;\n\n\t/* .. and there are no VLANs on packet */\n\tif (skb->protocol != __constant_htons(ETH_P_IP))\n\t\treturn false;\n\n\t/* .. and we are version 4 with no options */\n\tif (*(u8 *)iph != 0x45)\n\t\treturn false;\n\n\t/* .. and the packet is not fragmented */\n\tif (iph->frag_off & htons(IP_MF | IP_OFFSET))\n\t\treturn false;\n\n\t/* .. and that next header is TCP */\n\tif (iph->protocol != IPPROTO_TCP)\n\t\treturn false;\n\n\treturn true;\n}\n\nstatic inline struct igb_lrohdr *igb_lro_hdr(struct sk_buff *skb)\n{\n\treturn (struct igb_lrohdr *)skb->data;\n}\n\n/**\n * igb_lro_flush - Indicate packets to upper layer.\n *\n * Update IP and TCP header part of head skb if more than one\n * skb's chained and indicate packets to upper layer.\n **/\nstatic void igb_lro_flush(struct igb_q_vector *q_vector,\n\t\t\t struct sk_buff *skb)\n{\n\tstruct igb_lro_list *lrolist = &q_vector->lrolist;\n\n\t__skb_unlink(skb, &lrolist->active);\n\n\tif (IGB_CB(skb)->append_cnt) {\n\t\tstruct igb_lrohdr *lroh = igb_lro_hdr(skb);\n\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\t\t/* close any active lro contexts */\n\t\tigb_close_active_frag_list(skb);\n\n#endif\n\t\t/* incorporate ip header and re-calculate checksum */\n\t\tlroh->iph.tot_len = ntohs(skb->len);\n\t\tlroh->iph.check = 0;\n\n\t\t/* header length is 5 since we know no options exist */\n\t\tlroh->iph.check = ip_fast_csum((u8 *)lroh, 5);\n\n\t\t/* clear TCP checksum to indicate we are an LRO frame */\n\t\tlroh->th.check = 0;\n\n\t\t/* incorporate latest timestamp into the tcp header */\n\t\tif (IGB_CB(skb)->tsecr) {\n\t\t\tlroh->ts[2] = IGB_CB(skb)->tsecr;\n\t\t\tlroh->ts[1] = htonl(IGB_CB(skb)->tsval);\n\t\t}\n#ifdef NETIF_F_GSO\n\n\t\tskb_shinfo(skb)->gso_size = IGB_CB(skb)->mss;\n\t\tskb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;\n#endif\n\t}\n\n#ifdef HAVE_VLAN_RX_REGISTER\n\tigb_receive_skb(q_vector, skb);\n#else\n\tnapi_gro_receive(&q_vector->napi, skb);\n#endif\n\tlrolist->stats.flushed++;\n}\n\nstatic void igb_lro_flush_all(struct igb_q_vector *q_vector)\n{\n\tstruct igb_lro_list *lrolist = &q_vector->lrolist;\n\tstruct sk_buff *skb, *tmp;\n\n\tskb_queue_reverse_walk_safe(&lrolist->active, skb, tmp)\n\t\tigb_lro_flush(q_vector, skb);\n}\n\n/*\n * igb_lro_header_ok - Main LRO function.\n **/\nstatic void igb_lro_header_ok(struct sk_buff *skb)\n{\n\tstruct igb_lrohdr *lroh = igb_lro_hdr(skb);\n\tu16 opt_bytes, data_len;\n\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\tIGB_CB(skb)->tail = NULL;\n#endif\n\tIGB_CB(skb)->tsecr = 0;\n\tIGB_CB(skb)->append_cnt = 0;\n\tIGB_CB(skb)->mss = 0;\n\n\t/* ensure that the checksum is valid */\n\tif (skb->ip_summed != CHECKSUM_UNNECESSARY)\n\t\treturn;\n\n\t/* If we see CE codepoint in IP header, packet is not mergeable */\n\tif (INET_ECN_is_ce(ipv4_get_dsfield(&lroh->iph)))\n\t\treturn;\n\n\t/* ensure no bits set besides ack or psh */\n\tif (lroh->th.fin || lroh->th.syn || lroh->th.rst ||\n\t lroh->th.urg || lroh->th.ece || lroh->th.cwr ||\n\t !lroh->th.ack)\n\t\treturn;\n\n\t/* store the total packet length */\n\tdata_len = ntohs(lroh->iph.tot_len);\n\n\t/* remove any padding from the end of the skb */\n\t__pskb_trim(skb, data_len);\n\n\t/* remove header length from data length */\n\tdata_len -= sizeof(struct igb_lrohdr);\n\n\t/*\n\t * check for timestamps. Since the only option we handle are timestamps,\n\t * we only have to handle the simple case of aligned timestamps\n\t */\n\topt_bytes = (lroh->th.doff << 2) - sizeof(struct tcphdr);\n\tif (opt_bytes != 0) {\n\t\tif ((opt_bytes != TCPOLEN_TSTAMP_ALIGNED) ||\n\t\t !pskb_may_pull(skb, sizeof(struct igb_lrohdr) +\n\t\t\t\t\tTCPOLEN_TSTAMP_ALIGNED) ||\n\t\t (lroh->ts[0] != htonl((TCPOPT_NOP << 24) |\n\t\t\t\t\t (TCPOPT_NOP << 16) |\n\t\t\t\t\t (TCPOPT_TIMESTAMP << 8) |\n\t\t\t\t\t TCPOLEN_TIMESTAMP)) ||\n\t\t (lroh->ts[2] == 0)) {\n\t\t\treturn;\n\t\t}\n\n\t\tIGB_CB(skb)->tsval = ntohl(lroh->ts[1]);\n\t\tIGB_CB(skb)->tsecr = lroh->ts[2];\n\n\t\tdata_len -= TCPOLEN_TSTAMP_ALIGNED;\n\t}\n\n\t/* record data_len as mss for the packet */\n\tIGB_CB(skb)->mss = data_len;\n\tIGB_CB(skb)->next_seq = ntohl(lroh->th.seq);\n}\n\n#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT\nstatic void igb_merge_frags(struct sk_buff *lro_skb, struct sk_buff *new_skb)\n{\n\tstruct skb_shared_info *sh_info;\n\tstruct skb_shared_info *new_skb_info;\n\tunsigned int data_len;\n\n\tsh_info = skb_shinfo(lro_skb);\n\tnew_skb_info = skb_shinfo(new_skb);\n\n\t/* copy frags into the last skb */\n\tmemcpy(sh_info->frags + sh_info->nr_frags,\n\t new_skb_info->frags,\n\t new_skb_info->nr_frags * sizeof(skb_frag_t));\n\n\t/* copy size data over */\n\tsh_info->nr_frags += new_skb_info->nr_frags;\n\tdata_len = IGB_CB(new_skb)->mss;\n\tlro_skb->len += data_len;\n\tlro_skb->data_len += data_len;\n\tlro_skb->truesize += data_len;\n\n\t/* wipe record of data from new_skb */\n\tnew_skb_info->nr_frags = 0;\n\tnew_skb->len = new_skb->data_len = 0;\n\tdev_kfree_skb_any(new_skb);\n}\n\n#endif /* CONFIG_IGB_DISABLE_PACKET_SPLIT */\n/**\n * igb_lro_receive - if able, queue skb into lro chain\n * @q_vector: structure containing interrupt and ring information\n * @new_skb: pointer to current skb being checked\n *\n * Checks whether the skb given is eligible for LRO and if that's\n * fine chains it to the existing lro_skb based on flowid. If an LRO for\n * the flow doesn't exist create one.\n **/\nstatic void igb_lro_receive(struct igb_q_vector *q_vector,\n\t\t\t struct sk_buff *new_skb)\n{\n\tstruct sk_buff *lro_skb;\n\tstruct igb_lro_list *lrolist = &q_vector->lrolist;\n\tstruct igb_lrohdr *lroh = igb_lro_hdr(new_skb);\n\t__be32 saddr = lroh->iph.saddr;\n\t__be32 daddr = lroh->iph.daddr;\n\t__be32 tcp_ports = *(__be32 *)&lroh->th;\n\tu16 data_len;\n#ifdef HAVE_VLAN_RX_REGISTER\n\tu16 vid = IGB_CB(new_skb)->vid;\n#else\n\tu16 vid = new_skb->vlan_tci;\n#endif\n\n\tigb_lro_header_ok(new_skb);\n\n\t/*\n\t * we have a packet that might be eligible for LRO,\n\t * so see if it matches anything we might expect\n\t */\n\tskb_queue_walk(&lrolist->active, lro_skb) {\n\t\tif (*(__be32 *)&igb_lro_hdr(lro_skb)->th != tcp_ports ||\n\t\t igb_lro_hdr(lro_skb)->iph.saddr != saddr ||\n\t\t igb_lro_hdr(lro_skb)->iph.daddr != daddr)\n\t\t\tcontinue;\n\n#ifdef HAVE_VLAN_RX_REGISTER\n\t\tif (IGB_CB(lro_skb)->vid != vid)\n#else\n\t\tif (lro_skb->vlan_tci != vid)\n#endif\n\t\t\tcontinue;\n\n\t\t/* out of order packet */\n\t\tif (IGB_CB(lro_skb)->next_seq != IGB_CB(new_skb)->next_seq) {\n\t\t\tigb_lro_flush(q_vector, lro_skb);\n\t\t\tIGB_CB(new_skb)->mss = 0;\n\t\t\tbreak;\n\t\t}\n\n\t\t/* TCP timestamp options have changed */\n\t\tif (!IGB_CB(lro_skb)->tsecr != !IGB_CB(new_skb)->tsecr) {\n\t\t\tigb_lro_flush(q_vector, lro_skb);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* make sure timestamp values are increasing */\n\t\tif (IGB_CB(lro_skb)->tsecr &&\n\t\t IGB_CB(lro_skb)->tsval > IGB_CB(new_skb)->tsval) {\n\t\t\tigb_lro_flush(q_vector, lro_skb);\n\t\t\tIGB_CB(new_skb)->mss = 0;\n\t\t\tbreak;\n\t\t}\n\n\t\tdata_len = IGB_CB(new_skb)->mss;\n\n\t\t/* Check for all of the above below\n\t\t * malformed header\n\t\t * no tcp data\n\t\t * resultant packet would be too large\n\t\t * new skb is larger than our current mss\n\t\t * data would remain in header\n\t\t * we would consume more frags then the sk_buff contains\n\t\t * ack sequence numbers changed\n\t\t * window size has changed\n\t\t */\n\t\tif (data_len == 0 ||\n\t\t data_len > IGB_CB(lro_skb)->mss ||\n\t\t data_len > IGB_CB(lro_skb)->free ||\n#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\t\t data_len != new_skb->data_len ||\n\t\t skb_shinfo(new_skb)->nr_frags >=\n\t\t (MAX_SKB_FRAGS - skb_shinfo(lro_skb)->nr_frags) ||\n#endif\n\t\t igb_lro_hdr(lro_skb)->th.ack_seq != lroh->th.ack_seq ||\n\t\t igb_lro_hdr(lro_skb)->th.window != lroh->th.window) {\n\t\t\tigb_lro_flush(q_vector, lro_skb);\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Remove IP and TCP header*/\n\t\tskb_pull(new_skb, new_skb->len - data_len);\n\n\t\t/* update timestamp and timestamp echo response */\n\t\tIGB_CB(lro_skb)->tsval = IGB_CB(new_skb)->tsval;\n\t\tIGB_CB(lro_skb)->tsecr = IGB_CB(new_skb)->tsecr;\n\n\t\t/* update sequence and free space */\n\t\tIGB_CB(lro_skb)->next_seq += data_len;\n\t\tIGB_CB(lro_skb)->free -= data_len;\n\n\t\t/* update append_cnt */\n\t\tIGB_CB(lro_skb)->append_cnt++;\n\n#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\t\t/* if header is empty pull pages into current skb */\n\t\tigb_merge_frags(lro_skb, new_skb);\n#else\n\t\t/* chain this new skb in frag_list */\n\t\tigb_add_active_tail(lro_skb, new_skb);\n#endif\n\n\t\tif ((data_len < IGB_CB(lro_skb)->mss) || lroh->th.psh ||\n\t\t skb_shinfo(lro_skb)->nr_frags == MAX_SKB_FRAGS) {\n\t\t\tigb_lro_hdr(lro_skb)->th.psh |= lroh->th.psh;\n\t\t\tigb_lro_flush(q_vector, lro_skb);\n\t\t}\n\n\t\tlrolist->stats.coal++;\n\t\treturn;\n\t}\n\n\tif (IGB_CB(new_skb)->mss && !lroh->th.psh) {\n\t\t/* if we are at capacity flush the tail */\n\t\tif (skb_queue_len(&lrolist->active) >= IGB_LRO_MAX) {\n\t\t\tlro_skb = skb_peek_tail(&lrolist->active);\n\t\t\tif (lro_skb)\n\t\t\t\tigb_lro_flush(q_vector, lro_skb);\n\t\t}\n\n\t\t/* update sequence and free space */\n\t\tIGB_CB(new_skb)->next_seq += IGB_CB(new_skb)->mss;\n\t\tIGB_CB(new_skb)->free = 65521 - new_skb->len;\n\n\t\t/* .. and insert at the front of the active list */\n\t\t__skb_queue_head(&lrolist->active, new_skb);\n\n\t\tlrolist->stats.coal++;\n\t\treturn;\n\t}\n\n\t/* packet not handled by any of the above, pass it to the stack */\n#ifdef HAVE_VLAN_RX_REGISTER\n\tigb_receive_skb(q_vector, new_skb);\n#else\n\tnapi_gro_receive(&q_vector->napi, new_skb);\n#endif\n}\n\n#endif /* IGB_NO_LRO */\n/**\n * igb_process_skb_fields - Populate skb header fields from Rx descriptor\n * @rx_ring: rx descriptor ring packet is being transacted on\n * @rx_desc: pointer to the EOP Rx descriptor\n * @skb: pointer to current skb being populated\n *\n * This function checks the ring, descriptor, and packet information in\n * order to populate the hash, checksum, VLAN, timestamp, protocol, and\n * other fields within the skb.\n **/\nstatic void igb_process_skb_fields(struct igb_ring *rx_ring,\n\t\t\t\t union e1000_adv_rx_desc *rx_desc,\n\t\t\t\t struct sk_buff *skb)\n{\n\tstruct net_device *dev = rx_ring->netdev;\n\t__le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;\n\n#ifdef NETIF_F_RXHASH\n\tigb_rx_hash(rx_ring, rx_desc, skb);\n\n#endif\n\tigb_rx_checksum(rx_ring, rx_desc, skb);\n\n /* update packet type stats */\n\tif (pkt_info & cpu_to_le16(E1000_RXDADV_PKTTYPE_IPV4))\n\t\trx_ring->rx_stats.ipv4_packets++;\n\telse if (pkt_info & cpu_to_le16(E1000_RXDADV_PKTTYPE_IPV4_EX))\n\t\trx_ring->rx_stats.ipv4e_packets++;\n\telse if (pkt_info & cpu_to_le16(E1000_RXDADV_PKTTYPE_IPV6))\n\t\trx_ring->rx_stats.ipv6_packets++;\n\telse if (pkt_info & cpu_to_le16(E1000_RXDADV_PKTTYPE_IPV6_EX))\n\t\trx_ring->rx_stats.ipv6e_packets++;\n\telse if (pkt_info & cpu_to_le16(E1000_RXDADV_PKTTYPE_TCP))\n\t\trx_ring->rx_stats.tcp_packets++;\n\telse if (pkt_info & cpu_to_le16(E1000_RXDADV_PKTTYPE_UDP))\n\t\trx_ring->rx_stats.udp_packets++;\n\telse if (pkt_info & cpu_to_le16(E1000_RXDADV_PKTTYPE_SCTP))\n\t\trx_ring->rx_stats.sctp_packets++;\n\telse if (pkt_info & cpu_to_le16(E1000_RXDADV_PKTTYPE_NFS))\n\t\trx_ring->rx_stats.nfs_packets++;\n\n#ifdef HAVE_PTP_1588_CLOCK\n\tigb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);\n#endif /* HAVE_PTP_1588_CLOCK */\n\n#ifdef NETIF_F_HW_VLAN_CTAG_RX\n\tif ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&\n#else\n\tif ((dev->features & NETIF_F_HW_VLAN_RX) &&\n#endif\n\t igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {\n\t\tu16 vid = 0;\n\t\tif (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&\n\t\t test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))\n\t\t\tvid = be16_to_cpu(rx_desc->wb.upper.vlan);\n\t\telse\n\t\t\tvid = le16_to_cpu(rx_desc->wb.upper.vlan);\n#ifdef HAVE_VLAN_RX_REGISTER\n\t\tIGB_CB(skb)->vid = vid;\n\t} else {\n\t\tIGB_CB(skb)->vid = 0;\n#else\n\n#ifdef HAVE_VLAN_PROTOCOL\n\t\t__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);\n#else\n\t\t__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);\n#endif\n\n\n#endif\n\t}\n\n\tskb_record_rx_queue(skb, rx_ring->queue_index);\n\n\tskb->protocol = eth_type_trans(skb, dev);\n}\n\n/**\n * igb_is_non_eop - process handling of non-EOP buffers\n * @rx_ring: Rx ring being processed\n * @rx_desc: Rx descriptor for current buffer\n *\n * This function updates next to clean. If the buffer is an EOP buffer\n * this function exits returning false, otherwise it will place the\n * sk_buff in the next buffer to be chained and return true indicating\n * that this is in fact a non-EOP buffer.\n **/\nstatic bool igb_is_non_eop(struct igb_ring *rx_ring,\n\t\t\t union e1000_adv_rx_desc *rx_desc)\n{\n\tu32 ntc = rx_ring->next_to_clean + 1;\n\n\t/* fetch, update, and store next to clean */\n\tntc = (ntc < rx_ring->count) ? ntc : 0;\n\trx_ring->next_to_clean = ntc;\n\n\tprefetch(IGB_RX_DESC(rx_ring, ntc));\n\n\tif (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))\n\t\treturn false;\n\n\treturn true;\n}\n\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n/* igb_clean_rx_irq -- * legacy */\nstatic bool igb_clean_rx_irq(struct igb_q_vector *q_vector, int budget)\n{\n\tstruct igb_ring *rx_ring = q_vector->rx.ring;\n\tunsigned int total_bytes = 0, total_packets = 0;\n\tu16 cleaned_count = igb_desc_unused(rx_ring);\n\n\tdo {\n\t\tstruct igb_rx_buffer *rx_buffer;\n\t\tunion e1000_adv_rx_desc *rx_desc;\n\t\tstruct sk_buff *skb;\n\t\tu16 ntc;\n\n\t\t/* return some buffers to hardware, one at a time is too slow */\n\t\tif (cleaned_count >= IGB_RX_BUFFER_WRITE) {\n\t\t\tigb_alloc_rx_buffers(rx_ring, cleaned_count);\n\t\t\tcleaned_count = 0;\n\t\t}\n\n\t\tntc = rx_ring->next_to_clean;\n\t\trx_desc = IGB_RX_DESC(rx_ring, ntc);\n\t\trx_buffer = &rx_ring->rx_buffer_info[ntc];\n\n\t\tif (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))\n\t\t\tbreak;\n\n\t\t/*\n\t\t * This memory barrier is needed to keep us from reading\n\t\t * any other fields out of the rx_desc until we know the\n\t\t * RXD_STAT_DD bit is set\n\t\t */\n\t\trmb();\n\n\t\tskb = rx_buffer->skb;\n\n\t\tprefetch(skb->data);\n\n\t\t/* pull the header of the skb in */\n\t\t__skb_put(skb, le16_to_cpu(rx_desc->wb.upper.length));\n\n\t\t/* clear skb reference in buffer info structure */\n\t\trx_buffer->skb = NULL;\n\n\t\tcleaned_count++;\n\n\t\tBUG_ON(igb_is_non_eop(rx_ring, rx_desc));\n\n\t\tdma_unmap_single(rx_ring->dev, rx_buffer->dma,\n\t\t\t\t rx_ring->rx_buffer_len,\n\t\t\t\t DMA_FROM_DEVICE);\n\t\trx_buffer->dma = 0;\n\n\t\tif (igb_test_staterr(rx_desc,\n\t\t\t\t E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {\n\t\t\tdev_kfree_skb_any(skb);\n\t\t\tcontinue;\n\t\t}\n\n\t\ttotal_bytes += skb->len;\n\n\t\t/* populate checksum, timestamp, VLAN, and protocol */\n\t\tigb_process_skb_fields(rx_ring, rx_desc, skb);\n\n#ifndef IGB_NO_LRO\n\t\tif (igb_can_lro(rx_ring, rx_desc, skb))\n\t\t\tigb_lro_receive(q_vector, skb);\n\t\telse\n#endif\n#ifdef HAVE_VLAN_RX_REGISTER\n\t\t\tigb_receive_skb(q_vector, skb);\n#else\n\t\t\tnapi_gro_receive(&q_vector->napi, skb);\n#endif\n\n#ifndef NETIF_F_GRO\n\t\tnetdev_ring(rx_ring)->last_rx = jiffies;\n\n#endif\n\t\t/* update budget accounting */\n\t\ttotal_packets++;\n\t} while (likely(total_packets < budget));\n\n\trx_ring->rx_stats.packets += total_packets;\n\trx_ring->rx_stats.bytes += total_bytes;\n\tq_vector->rx.total_packets += total_packets;\n\tq_vector->rx.total_bytes += total_bytes;\n\n\tif (cleaned_count)\n\t\tigb_alloc_rx_buffers(rx_ring, cleaned_count);\n\n#ifndef IGB_NO_LRO\n\tigb_lro_flush_all(q_vector);\n\n#endif /* IGB_NO_LRO */\n\treturn (total_packets < budget);\n}\n#else /* CONFIG_IGB_DISABLE_PACKET_SPLIT */\n/**\n * igb_get_headlen - determine size of header for LRO/GRO\n * @data: pointer to the start of the headers\n * @max_len: total length of section to find headers in\n *\n * This function is meant to determine the length of headers that will\n * be recognized by hardware for LRO, and GRO offloads. The main\n * motivation of doing this is to only perform one pull for IPv4 TCP\n * packets so that we can do basic things like calculating the gso_size\n * based on the average data per packet.\n **/\nstatic unsigned int igb_get_headlen(unsigned char *data,\n\t\t\t\t unsigned int max_len)\n{\n\tunion {\n\t\tunsigned char *network;\n\t\t/* l2 headers */\n\t\tstruct ethhdr *eth;\n\t\tstruct vlan_hdr *vlan;\n\t\t/* l3 headers */\n\t\tstruct iphdr *ipv4;\n\t\tstruct ipv6hdr *ipv6;\n\t} hdr;\n\t__be16 protocol;\n\tu8 nexthdr = 0;\t/* default to not TCP */\n\tu8 hlen;\n\n\t/* this should never happen, but better safe than sorry */\n\tif (max_len < ETH_HLEN)\n\t\treturn max_len;\n\n\t/* initialize network frame pointer */\n\thdr.network = data;\n\n\t/* set first protocol and move network header forward */\n\tprotocol = hdr.eth->h_proto;\n\thdr.network += ETH_HLEN;\n\n\t/* handle any vlan tag if present */\n\tif (protocol == __constant_htons(ETH_P_8021Q)) {\n\t\tif ((hdr.network - data) > (max_len - VLAN_HLEN))\n\t\t\treturn max_len;\n\n\t\tprotocol = hdr.vlan->h_vlan_encapsulated_proto;\n\t\thdr.network += VLAN_HLEN;\n\t}\n\n\t/* handle L3 protocols */\n\tif (protocol == __constant_htons(ETH_P_IP)) {\n\t\tif ((hdr.network - data) > (max_len - sizeof(struct iphdr)))\n\t\t\treturn max_len;\n\n\t\t/* access ihl as a u8 to avoid unaligned access on ia64 */\n\t\thlen = (hdr.network[0] & 0x0F) << 2;\n\n\t\t/* verify hlen meets minimum size requirements */\n\t\tif (hlen < sizeof(struct iphdr))\n\t\t\treturn hdr.network - data;\n\n\t\t/* record next protocol if header is present */\n\t\tif (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))\n\t\t\tnexthdr = hdr.ipv4->protocol;\n#ifdef NETIF_F_TSO6\n\t} else if (protocol == __constant_htons(ETH_P_IPV6)) {\n\t\tif ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))\n\t\t\treturn max_len;\n\n\t\t/* record next protocol */\n\t\tnexthdr = hdr.ipv6->nexthdr;\n\t\thlen = sizeof(struct ipv6hdr);\n#endif /* NETIF_F_TSO6 */\n\t} else {\n\t\treturn hdr.network - data;\n\t}\n\n\t/* relocate pointer to start of L4 header */\n\thdr.network += hlen;\n\n\t/* finally sort out TCP */\n\tif (nexthdr == IPPROTO_TCP) {\n\t\tif ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))\n\t\t\treturn max_len;\n\n\t\t/* access doff as a u8 to avoid unaligned access on ia64 */\n\t\thlen = (hdr.network[12] & 0xF0) >> 2;\n\n\t\t/* verify hlen meets minimum size requirements */\n\t\tif (hlen < sizeof(struct tcphdr))\n\t\t\treturn hdr.network - data;\n\n\t\thdr.network += hlen;\n\t} else if (nexthdr == IPPROTO_UDP) {\n\t\tif ((hdr.network - data) > (max_len - sizeof(struct udphdr)))\n\t\t\treturn max_len;\n\n\t\thdr.network += sizeof(struct udphdr);\n\t}\n\n\t/*\n\t * If everything has gone correctly hdr.network should be the\n\t * data section of the packet and will be the end of the header.\n\t * If not then it probably represents the end of the last recognized\n\t * header.\n\t */\n\tif ((hdr.network - data) < max_len)\n\t\treturn hdr.network - data;\n\telse\n\t\treturn max_len;\n}\n\n/**\n * igb_pull_tail - igb specific version of skb_pull_tail\n * @rx_ring: rx descriptor ring packet is being transacted on\n * @rx_desc: pointer to the EOP Rx descriptor\n * @skb: pointer to current skb being adjusted\n *\n * This function is an igb specific version of __pskb_pull_tail. The\n * main difference between this version and the original function is that\n * this function can make several assumptions about the state of things\n * that allow for significant optimizations versus the standard function.\n * As a result we can do things like drop a frag and maintain an accurate\n * truesize for the skb.\n */\nstatic void igb_pull_tail(struct igb_ring *rx_ring,\n\t\t\t union e1000_adv_rx_desc *rx_desc,\n\t\t\t struct sk_buff *skb)\n{\n\tstruct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];\n\tunsigned char *va;\n\tunsigned int pull_len;\n\n\t/*\n\t * it is valid to use page_address instead of kmap since we are\n\t * working with pages allocated out of the lomem pool per\n\t * alloc_page(GFP_ATOMIC)\n\t */\n\tva = skb_frag_address(frag);\n\n#ifdef HAVE_PTP_1588_CLOCK\n\tif (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {\n\t\t/* retrieve timestamp from buffer */\n\t\tigb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);\n\n\t\t/* update pointers to remove timestamp header */\n\t\tskb_frag_size_sub(frag, IGB_TS_HDR_LEN);\n\t\tfrag->page_offset += IGB_TS_HDR_LEN;\n\t\tskb->data_len -= IGB_TS_HDR_LEN;\n\t\tskb->len -= IGB_TS_HDR_LEN;\n\n\t\t/* move va to start of packet data */\n\t\tva += IGB_TS_HDR_LEN;\n\t}\n#endif /* HAVE_PTP_1588_CLOCK */\n\n\t/*\n\t * we need the header to contain the greater of either ETH_HLEN or\n\t * 60 bytes if the skb->len is less than 60 for skb_pad.\n\t */\n\tpull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);\n\n\t/* align pull length to size of long to optimize memcpy performance */\n\tskb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));\n\n\t/* update all of the pointers */\n\tskb_frag_size_sub(frag, pull_len);\n\tfrag->page_offset += pull_len;\n\tskb->data_len -= pull_len;\n\tskb->tail += pull_len;\n}\n\n/**\n * igb_cleanup_headers - Correct corrupted or empty headers\n * @rx_ring: rx descriptor ring packet is being transacted on\n * @rx_desc: pointer to the EOP Rx descriptor\n * @skb: pointer to current skb being fixed\n *\n * Address the case where we are pulling data in on pages only\n * and as such no data is present in the skb header.\n *\n * In addition if skb is not at least 60 bytes we need to pad it so that\n * it is large enough to qualify as a valid Ethernet frame.\n *\n * Returns true if an error was encountered and skb was freed.\n **/\nstatic bool igb_cleanup_headers(struct igb_ring *rx_ring,\n\t\t\t\tunion e1000_adv_rx_desc *rx_desc,\n\t\t\t\tstruct sk_buff *skb)\n{\n\n\tif (unlikely((igb_test_staterr(rx_desc,\n\t\t\t\t E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {\n\t\tstruct net_device *netdev = rx_ring->netdev;\n\t\tif (!(netdev->features & NETIF_F_RXALL)) {\n\t\t\tdev_kfree_skb_any(skb);\n\t\t\treturn true;\n\t\t}\n\t}\n\n\t/* place header in linear portion of buffer */\n\tif (skb_is_nonlinear(skb))\n\t\tigb_pull_tail(rx_ring, rx_desc, skb);\n\n\t/* if skb_pad returns an error the skb was freed */\n\tif (unlikely(skb->len < 60)) {\n\t\tint pad_len = 60 - skb->len;\n\n\t\tif (skb_pad(skb, pad_len))\n\t\t\treturn true;\n\t\t__skb_put(skb, pad_len);\n\t}\n\n\treturn false;\n}\n\n/* igb_clean_rx_irq -- * packet split */\nstatic bool igb_clean_rx_irq(struct igb_q_vector *q_vector, int budget)\n{\n\tstruct igb_ring *rx_ring = q_vector->rx.ring;\n\tstruct sk_buff *skb = rx_ring->skb;\n\tunsigned int total_bytes = 0, total_packets = 0;\n\tu16 cleaned_count = igb_desc_unused(rx_ring);\n\n\tdo {\n\t\tunion e1000_adv_rx_desc *rx_desc;\n\n\t\t/* return some buffers to hardware, one at a time is too slow */\n\t\tif (cleaned_count >= IGB_RX_BUFFER_WRITE) {\n\t\t\tigb_alloc_rx_buffers(rx_ring, cleaned_count);\n\t\t\tcleaned_count = 0;\n\t\t}\n\n\t\trx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);\n\n\t\tif (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))\n\t\t\tbreak;\n\n\t\t/*\n\t\t * This memory barrier is needed to keep us from reading\n\t\t * any other fields out of the rx_desc until we know the\n\t\t * RXD_STAT_DD bit is set\n\t\t */\n\t\trmb();\n\n\t\t/* retrieve a buffer from the ring */\n\t\tskb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);\n\n\t\t/* exit if we failed to retrieve a buffer */\n\t\tif (!skb)\n\t\t\tbreak;\n\n\t\tcleaned_count++;\n\n\t\t/* fetch next buffer in frame if non-eop */\n\t\tif (igb_is_non_eop(rx_ring, rx_desc))\n\t\t\tcontinue;\n\n\t\t/* verify the packet layout is correct */\n\t\tif (igb_cleanup_headers(rx_ring, rx_desc, skb)) {\n\t\t\tskb = NULL;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* probably a little skewed due to removing CRC */\n\t\ttotal_bytes += skb->len;\n\n\t\t/* populate checksum, timestamp, VLAN, and protocol */\n\t\tigb_process_skb_fields(rx_ring, rx_desc, skb);\n\n#ifndef IGB_NO_LRO\n\t\tif (igb_can_lro(rx_ring, rx_desc, skb))\n\t\t\tigb_lro_receive(q_vector, skb);\n\t\telse\n#endif\n#ifdef HAVE_VLAN_RX_REGISTER\n\t\t\tigb_receive_skb(q_vector, skb);\n#else\n\t\t\tnapi_gro_receive(&q_vector->napi, skb);\n#endif\n#ifndef NETIF_F_GRO\n\n\t\tnetdev_ring(rx_ring)->last_rx = jiffies;\n#endif\n\n\t\t/* reset skb pointer */\n\t\tskb = NULL;\n\n\t\t/* update budget accounting */\n\t\ttotal_packets++;\n\t} while (likely(total_packets < budget));\n\n\t/* place incomplete frames back on ring for completion */\n\trx_ring->skb = skb;\n\n\trx_ring->rx_stats.packets += total_packets;\n\trx_ring->rx_stats.bytes += total_bytes;\n\tq_vector->rx.total_packets += total_packets;\n\tq_vector->rx.total_bytes += total_bytes;\n\n\tif (cleaned_count)\n\t\tigb_alloc_rx_buffers(rx_ring, cleaned_count);\n\n#ifndef IGB_NO_LRO\n\tigb_lro_flush_all(q_vector);\n\n#endif /* IGB_NO_LRO */\n\treturn (total_packets < budget);\n}\n#endif /* CONFIG_IGB_DISABLE_PACKET_SPLIT */\n\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\nstatic bool igb_alloc_mapped_skb(struct igb_ring *rx_ring,\n\t\t\t\t struct igb_rx_buffer *bi)\n{\n\tstruct sk_buff *skb = bi->skb;\n\tdma_addr_t dma = bi->dma;\n\n\tif (dma)\n\t\treturn true;\n\n\tif (likely(!skb)) {\n\t\tskb = netdev_alloc_skb_ip_align(netdev_ring(rx_ring),\n\t\t\t\t\t\trx_ring->rx_buffer_len);\n\t\tbi->skb = skb;\n\t\tif (!skb) {\n\t\t\trx_ring->rx_stats.alloc_failed++;\n\t\t\treturn false;\n\t\t}\n\n\t\t/* initialize skb for ring */\n\t\tskb_record_rx_queue(skb, ring_queue_index(rx_ring));\n\t}\n\n\tdma = dma_map_single(rx_ring->dev, skb->data,\n\t\t\t rx_ring->rx_buffer_len, DMA_FROM_DEVICE);\n\n\t/* if mapping failed free memory back to system since\n\t * there isn't much point in holding memory we can't use\n\t */\n\tif (dma_mapping_error(rx_ring->dev, dma)) {\n\t\tdev_kfree_skb_any(skb);\n\t\tbi->skb = NULL;\n\n\t\trx_ring->rx_stats.alloc_failed++;\n\t\treturn false;\n\t}\n\n\tbi->dma = dma;\n\treturn true;\n}\n\n#else /* CONFIG_IGB_DISABLE_PACKET_SPLIT */\nstatic bool igb_alloc_mapped_page(struct igb_ring *rx_ring,\n\t\t\t\t struct igb_rx_buffer *bi)\n{\n\tstruct page *page = bi->page;\n\tdma_addr_t dma;\n\n\t/* since we are recycling buffers we should seldom need to alloc */\n\tif (likely(page))\n\t\treturn true;\n\n\t/* alloc new page for storage */\n\tpage = alloc_page(GFP_ATOMIC | __GFP_COLD);\n\tif (unlikely(!page)) {\n\t\trx_ring->rx_stats.alloc_failed++;\n\t\treturn false;\n\t}\n\n\t/* map page for use */\n\tdma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);\n\n\t/*\n\t * if mapping failed free memory back to system since\n\t * there isn't much point in holding memory we can't use\n\t */\n\tif (dma_mapping_error(rx_ring->dev, dma)) {\n\t\t__free_page(page);\n\n\t\trx_ring->rx_stats.alloc_failed++;\n\t\treturn false;\n\t}\n\n\tbi->dma = dma;\n\tbi->page = page;\n\tbi->page_offset = 0;\n\n\treturn true;\n}\n\n#endif /* CONFIG_IGB_DISABLE_PACKET_SPLIT */\n/**\n * igb_alloc_rx_buffers - Replace used receive buffers; packet split\n * @adapter: address of board private structure\n **/\nvoid igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)\n{\n\tunion e1000_adv_rx_desc *rx_desc;\n\tstruct igb_rx_buffer *bi;\n\tu16 i = rx_ring->next_to_use;\n\n\t/* nothing to do */\n\tif (!cleaned_count)\n\t\treturn;\n\n\trx_desc = IGB_RX_DESC(rx_ring, i);\n\tbi = &rx_ring->rx_buffer_info[i];\n\ti -= rx_ring->count;\n\n\tdo {\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\t\tif (!igb_alloc_mapped_skb(rx_ring, bi))\n#else\n\t\tif (!igb_alloc_mapped_page(rx_ring, bi))\n#endif /* CONFIG_IGB_DISABLE_PACKET_SPLIT */\n\t\t\tbreak;\n\n\t\t/*\n\t\t * Refresh the desc even if buffer_addrs didn't change\n\t\t * because each write-back erases this info.\n\t\t */\n#ifdef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\t\trx_desc->read.pkt_addr = cpu_to_le64(bi->dma);\n#else\n\t\trx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);\n#endif\n\n\t\trx_desc++;\n\t\tbi++;\n\t\ti++;\n\t\tif (unlikely(!i)) {\n\t\t\trx_desc = IGB_RX_DESC(rx_ring, 0);\n\t\t\tbi = rx_ring->rx_buffer_info;\n\t\t\ti -= rx_ring->count;\n\t\t}\n\n\t\t/* clear the hdr_addr for the next_to_use descriptor */\n\t\trx_desc->read.hdr_addr = 0;\n\n\t\tcleaned_count--;\n\t} while (cleaned_count);\n\n\ti += rx_ring->count;\n\n\tif (rx_ring->next_to_use != i) {\n\t\t/* record the next descriptor to use */\n\t\trx_ring->next_to_use = i;\n\n#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT\n\t\t/* update next to alloc since we have filled the ring */\n\t\trx_ring->next_to_alloc = i;\n\n#endif\n\t\t/*\n\t\t * Force memory writes to complete before letting h/w\n\t\t * know there are new descriptors to fetch. (Only\n\t\t * applicable for weak-ordered memory model archs,\n\t\t * such as IA-64).\n\t\t */\n\t\twmb();\n\t\twritel(i, rx_ring->tail);\n\t}\n}\n\n#ifdef SIOCGMIIPHY\n/**\n * igb_mii_ioctl -\n * @netdev:\n * @ifreq:\n * @cmd:\n **/\nstatic int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct mii_ioctl_data *data = if_mii(ifr);\n\n\tif (adapter->hw.phy.media_type != e1000_media_type_copper)\n\t\treturn -EOPNOTSUPP;\n\n\tswitch (cmd) {\n\tcase SIOCGMIIPHY:\n\t\tdata->phy_id = adapter->hw.phy.addr;\n\t\tbreak;\n\tcase SIOCGMIIREG:\n\t\tif (!capable(CAP_NET_ADMIN))\n\t\t\treturn -EPERM;\n\t\tif (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,\n\t\t\t\t &data->val_out))\n\t\t\treturn -EIO;\n\t\tbreak;\n\tcase SIOCSMIIREG:\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n\treturn E1000_SUCCESS;\n}\n\n#endif\n/**\n * igb_ioctl -\n * @netdev:\n * @ifreq:\n * @cmd:\n **/\nstatic int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)\n{\n\tswitch (cmd) {\n#ifdef SIOCGMIIPHY\n\tcase SIOCGMIIPHY:\n\tcase SIOCGMIIREG:\n\tcase SIOCSMIIREG:\n\t\treturn igb_mii_ioctl(netdev, ifr, cmd);\n#endif\n#ifdef HAVE_PTP_1588_CLOCK\n\tcase SIOCSHWTSTAMP:\n\t\treturn igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);\n#endif /* HAVE_PTP_1588_CLOCK */\n#ifdef ETHTOOL_OPS_COMPAT\n\tcase SIOCETHTOOL:\n\t\treturn ethtool_ioctl(ifr);\n#endif\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n}\n\ns32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)\n{\n\tstruct igb_adapter *adapter = hw->back;\n\tu16 cap_offset;\n\n\tcap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);\n\tif (!cap_offset)\n\t\treturn -E1000_ERR_CONFIG;\n\n\tpci_read_config_word(adapter->pdev, cap_offset + reg, value);\n\n\treturn E1000_SUCCESS;\n}\n\ns32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)\n{\n\tstruct igb_adapter *adapter = hw->back;\n\tu16 cap_offset;\n\n\tcap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);\n\tif (!cap_offset)\n\t\treturn -E1000_ERR_CONFIG;\n\n\tpci_write_config_word(adapter->pdev, cap_offset + reg, *value);\n\n\treturn E1000_SUCCESS;\n}\n\n#ifdef HAVE_VLAN_RX_REGISTER\nstatic void igb_vlan_mode(struct net_device *netdev, struct vlan_group *vlgrp)\n#else\nvoid igb_vlan_mode(struct net_device *netdev, u32 features)\n#endif\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 ctrl, rctl;\n\tint i;\n#ifdef HAVE_VLAN_RX_REGISTER\n\tbool enable = !!vlgrp;\n\n\tigb_irq_disable(adapter);\n\n\tadapter->vlgrp = vlgrp;\n\n\tif (!test_bit(__IGB_DOWN, &adapter->state))\n\t\tigb_irq_enable(adapter);\n#else\n#ifdef NETIF_F_HW_VLAN_CTAG_RX\n\tbool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);\n#else\n\tbool enable = !!(features & NETIF_F_HW_VLAN_RX);\n#endif\n#endif\n\n\tif (enable) {\n\t\t/* enable VLAN tag insert/strip */\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tctrl |= E1000_CTRL_VME;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\t\t/* Disable CFI check */\n\t\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\t\trctl &= ~E1000_RCTL_CFIEN;\n\t\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\t} else {\n\t\t/* disable VLAN tag insert/strip */\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\tctrl &= ~E1000_CTRL_VME;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\t}\n\n#ifndef CONFIG_IGB_VMDQ_NETDEV\n\tfor (i = 0; i < adapter->vmdq_pools; i++) {\n\t\tigb_set_vf_vlan_strip(adapter,\n\t\t\t\t adapter->vfs_allocated_count + i,\n\t\t\t\t enable);\n\t}\n\n#else\n\tigb_set_vf_vlan_strip(adapter,\n\t\t\t adapter->vfs_allocated_count,\n\t\t\t enable);\n\n\tfor (i = 1; i < adapter->vmdq_pools; i++) {\n#ifdef HAVE_VLAN_RX_REGISTER\n\t\tstruct igb_vmdq_adapter *vadapter;\n\t\tvadapter = netdev_priv(adapter->vmdq_netdev[i-1]);\n\t\tenable = !!vadapter->vlgrp;\n#else\n\t\tstruct net_device *vnetdev;\n\t\tvnetdev = adapter->vmdq_netdev[i-1];\n#ifdef NETIF_F_HW_VLAN_CTAG_RX\n\t\tenable = !!(vnetdev->features & NETIF_F_HW_VLAN_CTAG_RX);\n#else\n\t\tenable = !!(vnetdev->features & NETIF_F_HW_VLAN_RX);\n#endif\n#endif\n\t\tigb_set_vf_vlan_strip(adapter,\n\t\t\t\t adapter->vfs_allocated_count + i,\n\t\t\t\t enable);\n\t}\n\n#endif\n\tigb_rlpml_set(adapter);\n}\n\n#ifdef HAVE_VLAN_PROTOCOL\nstatic int igb_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)\n#elif defined HAVE_INT_NDO_VLAN_RX_ADD_VID\n#ifdef NETIF_F_HW_VLAN_CTAG_RX\nstatic int igb_vlan_rx_add_vid(struct net_device *netdev,\n\t\t\t __always_unused __be16 proto, u16 vid)\n#else\nstatic int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)\n#endif\n#else\nstatic void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)\n#endif\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tint pf_id = adapter->vfs_allocated_count;\n\n\t/* attempt to add filter to vlvf array */\n\tigb_vlvf_set(adapter, vid, TRUE, pf_id);\n\n\t/* add the filter since PF can receive vlans w/o entry in vlvf */\n\tigb_vfta_set(adapter, vid, TRUE);\n#ifndef HAVE_NETDEV_VLAN_FEATURES\n\n\t/* Copy feature flags from netdev to the vlan netdev for this vid.\n\t * This allows things like TSO to bubble down to our vlan device.\n\t * There is no need to update netdev for vlan 0 (DCB), since it\n\t * wouldn't has v_netdev.\n\t */\n\tif (adapter->vlgrp) {\n\t\tstruct vlan_group *vlgrp = adapter->vlgrp;\n\t\tstruct net_device *v_netdev = vlan_group_get_device(vlgrp, vid);\n\t\tif (v_netdev) {\n\t\t\tv_netdev->features |= netdev->features;\n\t\t\tvlan_group_set_device(vlgrp, vid, v_netdev);\n\t\t}\n\t}\n#endif\n#ifndef HAVE_VLAN_RX_REGISTER\n\n\tset_bit(vid, adapter->active_vlans);\n#endif\n#ifdef HAVE_INT_NDO_VLAN_RX_ADD_VID\n\treturn 0;\n#endif\n}\n\n#ifdef HAVE_VLAN_PROTOCOL\nstatic int igb_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)\n#elif defined HAVE_INT_NDO_VLAN_RX_ADD_VID\n#ifdef NETIF_F_HW_VLAN_CTAG_RX\nstatic int igb_vlan_rx_kill_vid(struct net_device *netdev,\n\t\t\t\t__always_unused __be16 proto, u16 vid)\n#else\nstatic int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)\n#endif\n#else\nstatic void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)\n#endif\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tint pf_id = adapter->vfs_allocated_count;\n\ts32 err;\n\n#ifdef HAVE_VLAN_RX_REGISTER\n\tigb_irq_disable(adapter);\n\n\tvlan_group_set_device(adapter->vlgrp, vid, NULL);\n\n\tif (!test_bit(__IGB_DOWN, &adapter->state))\n\t\tigb_irq_enable(adapter);\n\n#endif /* HAVE_VLAN_RX_REGISTER */\n\t/* remove vlan from VLVF table array */\n\terr = igb_vlvf_set(adapter, vid, FALSE, pf_id);\n\n\t/* if vid was not present in VLVF just remove it from table */\n\tif (err)\n\t\tigb_vfta_set(adapter, vid, FALSE);\n#ifndef HAVE_VLAN_RX_REGISTER\n\n\tclear_bit(vid, adapter->active_vlans);\n#endif\n#ifdef HAVE_INT_NDO_VLAN_RX_ADD_VID\n\treturn 0;\n#endif\n}\n\nstatic void igb_restore_vlan(struct igb_adapter *adapter)\n{\n#ifdef HAVE_VLAN_RX_REGISTER\n\tigb_vlan_mode(adapter->netdev, adapter->vlgrp);\n\n\tif (adapter->vlgrp) {\n\t\tu16 vid;\n\t\tfor (vid = 0; vid < VLAN_N_VID; vid++) {\n\t\t\tif (!vlan_group_get_device(adapter->vlgrp, vid))\n\t\t\t\tcontinue;\n#ifdef NETIF_F_HW_VLAN_CTAG_RX\n\t\t\tigb_vlan_rx_add_vid(adapter->netdev,\n\t\t\t\t\t htons(ETH_P_8021Q), vid);\n#else\n\t\t\tigb_vlan_rx_add_vid(adapter->netdev, vid);\n#endif\n\t\t}\n\t}\n#else\n\tu16 vid;\n\n\tigb_vlan_mode(adapter->netdev, adapter->netdev->features);\n\n\tfor_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)\n#ifdef NETIF_F_HW_VLAN_CTAG_RX\n\t\tigb_vlan_rx_add_vid(adapter->netdev,\n\t\t\t\t htons(ETH_P_8021Q), vid);\n#else\n\t\tigb_vlan_rx_add_vid(adapter->netdev, vid);\n#endif\n#endif\n}\n\nint igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)\n{\n\tstruct pci_dev *pdev = adapter->pdev;\n\tstruct e1000_mac_info *mac = &adapter->hw.mac;\n\n\tmac->autoneg = 0;\n\n\t/* SerDes device's does not support 10Mbps Full/duplex\n\t * and 100Mbps Half duplex\n\t */\n\tif (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {\n\t\tswitch (spddplx) {\n\t\tcase SPEED_10 + DUPLEX_HALF:\n\t\tcase SPEED_10 + DUPLEX_FULL:\n\t\tcase SPEED_100 + DUPLEX_HALF:\n\t\t\tdev_err(pci_dev_to_dev(pdev),\n\t\t\t\t\"Unsupported Speed/Duplex configuration\\n\");\n\t\t\treturn -EINVAL;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tswitch (spddplx) {\n\tcase SPEED_10 + DUPLEX_HALF:\n\t\tmac->forced_speed_duplex = ADVERTISE_10_HALF;\n\t\tbreak;\n\tcase SPEED_10 + DUPLEX_FULL:\n\t\tmac->forced_speed_duplex = ADVERTISE_10_FULL;\n\t\tbreak;\n\tcase SPEED_100 + DUPLEX_HALF:\n\t\tmac->forced_speed_duplex = ADVERTISE_100_HALF;\n\t\tbreak;\n\tcase SPEED_100 + DUPLEX_FULL:\n\t\tmac->forced_speed_duplex = ADVERTISE_100_FULL;\n\t\tbreak;\n\tcase SPEED_1000 + DUPLEX_FULL:\n\t\tmac->autoneg = 1;\n\t\tadapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;\n\t\tbreak;\n\tcase SPEED_1000 + DUPLEX_HALF: /* not supported */\n\tdefault:\n\t\tdev_err(pci_dev_to_dev(pdev), \"Unsupported Speed/Duplex configuration\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* clear MDI, MDI(-X) override is only allowed when autoneg enabled */\n\tadapter->hw.phy.mdix = AUTO_ALL_MODES;\n\n\treturn 0;\n}\n\nstatic int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,\n\t\t\t bool runtime)\n{\n\tstruct net_device *netdev = pci_get_drvdata(pdev);\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 ctrl, rctl, status;\n\tu32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;\n#ifdef CONFIG_PM\n\tint retval = 0;\n#endif\n\n\tnetif_device_detach(netdev);\n\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\tif (status & E1000_STATUS_LU)\n\t\twufc &= ~E1000_WUFC_LNKC;\n\n\tif (netif_running(netdev))\n\t\t__igb_close(netdev, true);\n\n\tigb_clear_interrupt_scheme(adapter);\n\n#ifdef CONFIG_PM\n\tretval = pci_save_state(pdev);\n\tif (retval)\n\t\treturn retval;\n#endif\n\n\tif (wufc) {\n\t\tigb_setup_rctl(adapter);\n\t\tigb_set_rx_mode(netdev);\n\n\t\t/* turn on all-multi mode if wake on multicast is enabled */\n\t\tif (wufc & E1000_WUFC_MC) {\n\t\t\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\t\t\trctl |= E1000_RCTL_MPE;\n\t\t\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\t\t}\n\n\t\tctrl = E1000_READ_REG(hw, E1000_CTRL);\n\t\t/* phy power management enable */\n\t\t#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000\n\t\tctrl |= E1000_CTRL_ADVD3WUC;\n\t\tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n\n\t\t/* Allow time for pending master requests to run */\n\t\te1000_disable_pcie_master(hw);\n\n\t\tE1000_WRITE_REG(hw, E1000_WUC, E1000_WUC_PME_EN);\n\t\tE1000_WRITE_REG(hw, E1000_WUFC, wufc);\n\t} else {\n\t\tE1000_WRITE_REG(hw, E1000_WUC, 0);\n\t\tE1000_WRITE_REG(hw, E1000_WUFC, 0);\n\t}\n\n\t*enable_wake = wufc || adapter->en_mng_pt;\n\tif (!*enable_wake)\n\t\tigb_power_down_link(adapter);\n\telse\n\t\tigb_power_up_link(adapter);\n\n\t/* Release control of h/w to f/w. If f/w is AMT enabled, this\n\t * would have already happened in close and is redundant. */\n\tigb_release_hw_control(adapter);\n\n\tpci_disable_device(pdev);\n\n\treturn 0;\n}\n\n#ifdef CONFIG_PM\n#ifdef HAVE_SYSTEM_SLEEP_PM_OPS\nstatic int igb_suspend(struct device *dev)\n#else\nstatic int igb_suspend(struct pci_dev *pdev, pm_message_t state)\n#endif /* HAVE_SYSTEM_SLEEP_PM_OPS */\n{\n#ifdef HAVE_SYSTEM_SLEEP_PM_OPS\n\tstruct pci_dev *pdev = to_pci_dev(dev);\n#endif /* HAVE_SYSTEM_SLEEP_PM_OPS */\n\tint retval;\n\tbool wake;\n\n\tretval = __igb_shutdown(pdev, &wake, 0);\n\tif (retval)\n\t\treturn retval;\n\n\tif (wake) {\n\t\tpci_prepare_to_sleep(pdev);\n\t} else {\n\t\tpci_wake_from_d3(pdev, false);\n\t\tpci_set_power_state(pdev, PCI_D3hot);\n\t}\n\n\treturn 0;\n}\n\n#ifdef HAVE_SYSTEM_SLEEP_PM_OPS\nstatic int igb_resume(struct device *dev)\n#else\nstatic int igb_resume(struct pci_dev *pdev)\n#endif /* HAVE_SYSTEM_SLEEP_PM_OPS */\n{\n#ifdef HAVE_SYSTEM_SLEEP_PM_OPS\n\tstruct pci_dev *pdev = to_pci_dev(dev);\n#endif /* HAVE_SYSTEM_SLEEP_PM_OPS */\n\tstruct net_device *netdev = pci_get_drvdata(pdev);\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 err;\n\n\tpci_set_power_state(pdev, PCI_D0);\n\tpci_restore_state(pdev);\n\tpci_save_state(pdev);\n\n\terr = pci_enable_device_mem(pdev);\n\tif (err) {\n\t\tdev_err(pci_dev_to_dev(pdev),\n\t\t\t\"igb: Cannot enable PCI device from suspend\\n\");\n\t\treturn err;\n\t}\n\tpci_set_master(pdev);\n\n\tpci_enable_wake(pdev, PCI_D3hot, 0);\n\tpci_enable_wake(pdev, PCI_D3cold, 0);\n\n\tif (igb_init_interrupt_scheme(adapter, true)) {\n\t\tdev_err(pci_dev_to_dev(pdev), \"Unable to allocate memory for queues\\n\");\n\t\treturn -ENOMEM;\n\t}\n\n\tigb_reset(adapter);\n\n\t/* let the f/w know that the h/w is now under the control of the\n\t * driver. */\n\tigb_get_hw_control(adapter);\n\n\tE1000_WRITE_REG(hw, E1000_WUS, ~0);\n\n\tif (netdev->flags & IFF_UP) {\n\t\trtnl_lock();\n\t\terr = __igb_open(netdev, true);\n\t\trtnl_unlock();\n\t\tif (err)\n\t\t\treturn err;\n\t}\n\n\tnetif_device_attach(netdev);\n\n\treturn 0;\n}\n\n#ifdef CONFIG_PM_RUNTIME\n#ifdef HAVE_SYSTEM_SLEEP_PM_OPS\nstatic int igb_runtime_idle(struct device *dev)\n{\n\tstruct pci_dev *pdev = to_pci_dev(dev);\n\tstruct net_device *netdev = pci_get_drvdata(pdev);\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\tif (!igb_has_link(adapter))\n\t\tpm_schedule_suspend(dev, MSEC_PER_SEC * 5);\n\n\treturn -EBUSY;\n}\n\nstatic int igb_runtime_suspend(struct device *dev)\n{\n\tstruct pci_dev *pdev = to_pci_dev(dev);\n\tint retval;\n\tbool wake;\n\n\tretval = __igb_shutdown(pdev, &wake, 1);\n\tif (retval)\n\t\treturn retval;\n\n\tif (wake) {\n\t\tpci_prepare_to_sleep(pdev);\n\t} else {\n\t\tpci_wake_from_d3(pdev, false);\n\t\tpci_set_power_state(pdev, PCI_D3hot);\n\t}\n\n\treturn 0;\n}\n\nstatic int igb_runtime_resume(struct device *dev)\n{\n\treturn igb_resume(dev);\n}\n#endif /* HAVE_SYSTEM_SLEEP_PM_OPS */\n#endif /* CONFIG_PM_RUNTIME */\n#endif /* CONFIG_PM */\n\n#ifdef USE_REBOOT_NOTIFIER\n/* only want to do this for 2.4 kernels? */\nstatic int igb_notify_reboot(struct notifier_block *nb, unsigned long event,\n void *p)\n{\n\tstruct pci_dev *pdev = NULL;\n\tbool wake;\n\n\tswitch (event) {\n\tcase SYS_DOWN:\n\tcase SYS_HALT:\n\tcase SYS_POWER_OFF:\n\t\twhile ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))) {\n\t\t\tif (pci_dev_driver(pdev) == &igb_driver) {\n\t\t\t\t__igb_shutdown(pdev, &wake, 0);\n\t\t\t\tif (event == SYS_POWER_OFF) {\n\t\t\t\t\tpci_wake_from_d3(pdev, wake);\n\t\t\t\t\tpci_set_power_state(pdev, PCI_D3hot);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\treturn NOTIFY_DONE;\n}\n#else\nstatic void igb_shutdown(struct pci_dev *pdev)\n{\n\tbool wake = false;\n\n\t__igb_shutdown(pdev, &wake, 0);\n\n\tif (system_state == SYSTEM_POWER_OFF) {\n\t\tpci_wake_from_d3(pdev, wake);\n\t\tpci_set_power_state(pdev, PCI_D3hot);\n\t}\n}\n#endif /* USE_REBOOT_NOTIFIER */\n\n#ifdef CONFIG_NET_POLL_CONTROLLER\n/*\n * Polling 'interrupt' - used by things like netconsole to send skbs\n * without having to re-enable interrupts. It's not called while\n * the interrupt routine is executing.\n */\nstatic void igb_netpoll(struct net_device *netdev)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct igb_q_vector *q_vector;\n\tint i;\n\n\tfor (i = 0; i < adapter->num_q_vectors; i++) {\n\t\tq_vector = adapter->q_vector[i];\n\t\tif (adapter->msix_entries)\n\t\t\tE1000_WRITE_REG(hw, E1000_EIMC, q_vector->eims_value);\n\t\telse\n\t\t\tigb_irq_disable(adapter);\n\t\tnapi_schedule(&q_vector->napi);\n\t}\n}\n#endif /* CONFIG_NET_POLL_CONTROLLER */\n\n#ifdef HAVE_PCI_ERS\n#define E1000_DEV_ID_82576_VF 0x10CA\n/**\n * igb_io_error_detected - called when PCI error is detected\n * @pdev: Pointer to PCI device\n * @state: The current pci connection state\n *\n * This function is called after a PCI bus error affecting\n * this device has been detected.\n */\nstatic pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,\n\t\t\t\t\t pci_channel_state_t state)\n{\n\tstruct net_device *netdev = pci_get_drvdata(pdev);\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n#ifdef CONFIG_PCI_IOV__UNUSED\n\tstruct pci_dev *bdev, *vfdev;\n\tu32 dw0, dw1, dw2, dw3;\n\tint vf, pos;\n\tu16 req_id, pf_func;\n\n\tif (!(adapter->flags & IGB_FLAG_DETECT_BAD_DMA))\n\t\tgoto skip_bad_vf_detection;\n\n\tbdev = pdev->bus->self;\n\twhile (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))\n\t\tbdev = bdev->bus->self;\n\n\tif (!bdev)\n\t\tgoto skip_bad_vf_detection;\n\n\tpos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);\n\tif (!pos)\n\t\tgoto skip_bad_vf_detection;\n\n\tpci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);\n\tpci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);\n\tpci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);\n\tpci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);\n\n\treq_id = dw1 >> 16;\n\t/* On the 82576 if bit 7 of the requestor ID is set then it's a VF */\n\tif (!(req_id & 0x0080))\n\t\tgoto skip_bad_vf_detection;\n\n\tpf_func = req_id & 0x01;\n\tif ((pf_func & 1) == (pdev->devfn & 1)) {\n\n\t\tvf = (req_id & 0x7F) >> 1;\n\t\tdev_err(pci_dev_to_dev(pdev),\n\t\t\t\"VF %d has caused a PCIe error\\n\", vf);\n\t\tdev_err(pci_dev_to_dev(pdev),\n\t\t\t\"TLP: dw0: %8.8x\\tdw1: %8.8x\\tdw2: \"\n\t\t\t\"%8.8x\\tdw3: %8.8x\\n\",\n\t\t\tdw0, dw1, dw2, dw3);\n\n\t\t/* Find the pci device of the offending VF */\n\t\tvfdev = pci_get_device(PCI_VENDOR_ID_INTEL,\n\t\t\t\t E1000_DEV_ID_82576_VF, NULL);\n\t\twhile (vfdev) {\n\t\t\tif (vfdev->devfn == (req_id & 0xFF))\n\t\t\t\tbreak;\n\t\t\tvfdev = pci_get_device(PCI_VENDOR_ID_INTEL,\n\t\t\t\t\t E1000_DEV_ID_82576_VF, vfdev);\n\t\t}\n\t\t/*\n\t\t * There's a slim chance the VF could have been hot plugged,\n\t\t * so if it is no longer present we don't need to issue the\n\t\t * VFLR. Just clean up the AER in that case.\n\t\t */\n\t\tif (vfdev) {\n\t\t\tdev_err(pci_dev_to_dev(pdev),\n\t\t\t\t\"Issuing VFLR to VF %d\\n\", vf);\n\t\t\tpci_write_config_dword(vfdev, 0xA8, 0x00008000);\n\t\t}\n\n\t\tpci_cleanup_aer_uncorrect_error_status(pdev);\n\t}\n\n\t/*\n\t * Even though the error may have occurred on the other port\n\t * we still need to increment the vf error reference count for\n\t * both ports because the I/O resume function will be called\n\t * for both of them.\n\t */\n\tadapter->vferr_refcount++;\n\n\treturn PCI_ERS_RESULT_RECOVERED;\n\nskip_bad_vf_detection:\n#endif /* CONFIG_PCI_IOV */\n\n\tnetif_device_detach(netdev);\n\n\tif (state == pci_channel_io_perm_failure)\n\t\treturn PCI_ERS_RESULT_DISCONNECT;\n\n\tif (netif_running(netdev))\n\t\tigb_down(adapter);\n\tpci_disable_device(pdev);\n\n\t/* Request a slot slot reset. */\n\treturn PCI_ERS_RESULT_NEED_RESET;\n}\n\n/**\n * igb_io_slot_reset - called after the pci bus has been reset.\n * @pdev: Pointer to PCI device\n *\n * Restart the card from scratch, as if from a cold-boot. Implementation\n * resembles the first-half of the igb_resume routine.\n */\nstatic pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)\n{\n\tstruct net_device *netdev = pci_get_drvdata(pdev);\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tpci_ers_result_t result;\n\n\tif (pci_enable_device_mem(pdev)) {\n\t\tdev_err(pci_dev_to_dev(pdev),\n\t\t\t\"Cannot re-enable PCI device after reset.\\n\");\n\t\tresult = PCI_ERS_RESULT_DISCONNECT;\n\t} else {\n\t\tpci_set_master(pdev);\n\t\tpci_restore_state(pdev);\n\t\tpci_save_state(pdev);\n\n\t\tpci_enable_wake(pdev, PCI_D3hot, 0);\n\t\tpci_enable_wake(pdev, PCI_D3cold, 0);\n\n\t\tschedule_work(&adapter->reset_task);\n\t\tE1000_WRITE_REG(hw, E1000_WUS, ~0);\n\t\tresult = PCI_ERS_RESULT_RECOVERED;\n\t}\n\n\tpci_cleanup_aer_uncorrect_error_status(pdev);\n\n\treturn result;\n}\n\n/**\n * igb_io_resume - called when traffic can start flowing again.\n * @pdev: Pointer to PCI device\n *\n * This callback is called when the error recovery driver tells us that\n * its OK to resume normal operation. Implementation resembles the\n * second-half of the igb_resume routine.\n */\nstatic void igb_io_resume(struct pci_dev *pdev)\n{\n\tstruct net_device *netdev = pci_get_drvdata(pdev);\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\n\tif (adapter->vferr_refcount) {\n\t\tdev_info(pci_dev_to_dev(pdev), \"Resuming after VF err\\n\");\n\t\tadapter->vferr_refcount--;\n\t\treturn;\n\t}\n\n\tif (netif_running(netdev)) {\n\t\tif (igb_up(adapter)) {\n\t\t\tdev_err(pci_dev_to_dev(pdev), \"igb_up failed after reset\\n\");\n\t\t\treturn;\n\t\t}\n\t}\n\n\tnetif_device_attach(netdev);\n\n\t/* let the f/w know that the h/w is now under the control of the\n\t * driver. */\n\tigb_get_hw_control(adapter);\n}\n\n#endif /* HAVE_PCI_ERS */\n\nint igb_add_mac_filter(struct igb_adapter *adapter, u8 *addr, u16 queue)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint i;\n\n\tif (is_zero_ether_addr(addr))\n\t\treturn 0;\n\n\tfor (i = 0; i < hw->mac.rar_entry_count; i++) {\n\t\tif (adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE)\n\t\t\tcontinue;\n\t\tadapter->mac_table[i].state = (IGB_MAC_STATE_MODIFIED |\n\t\t\t\t\t\t IGB_MAC_STATE_IN_USE);\n\t\tmemcpy(adapter->mac_table[i].addr, addr, ETH_ALEN);\n\t\tadapter->mac_table[i].queue = queue;\n\t\tigb_sync_mac_table(adapter);\n\t\treturn 0;\n\t}\n\treturn -ENOMEM;\n}\nint igb_del_mac_filter(struct igb_adapter *adapter, u8* addr, u16 queue)\n{\n\t/* search table for addr, if found, set to 0 and sync */\n\tint i;\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\tif (is_zero_ether_addr(addr))\n\t\treturn 0;\n\tfor (i = 0; i < hw->mac.rar_entry_count; i++) {\n\t\tif (ether_addr_equal(addr, adapter->mac_table[i].addr) &&\n\t\t adapter->mac_table[i].queue == queue) {\n\t\t\tadapter->mac_table[i].state = IGB_MAC_STATE_MODIFIED;\n\t\t\tmemset(adapter->mac_table[i].addr, 0, ETH_ALEN);\n\t\t\tadapter->mac_table[i].queue = 0;\n\t\t\tigb_sync_mac_table(adapter);\n\t\t\treturn 0;\n\t\t}\n\t}\n\treturn -ENOMEM;\n}\nstatic int igb_set_vf_mac(struct igb_adapter *adapter,\n int vf, unsigned char *mac_addr)\n{\n\tigb_del_mac_filter(adapter, adapter->vf_data[vf].vf_mac_addresses, vf);\n\tmemcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);\n\n\tigb_add_mac_filter(adapter, mac_addr, vf);\n\n\treturn 0;\n}\n\n#ifdef IFLA_VF_MAX\nstatic int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tif (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))\n\t\treturn -EINVAL;\n\tadapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;\n\tdev_info(&adapter->pdev->dev, \"setting MAC %pM on VF %d\\n\", mac, vf);\n\tdev_info(&adapter->pdev->dev, \"Reload the VF driver to make this\"\n\t\t\t\t \" change effective.\\n\");\n\tif (test_bit(__IGB_DOWN, &adapter->state)) {\n\t\tdev_warn(&adapter->pdev->dev, \"The VF MAC address has been set,\"\n\t\t\t \" but the PF device is not up.\\n\");\n\t\tdev_warn(&adapter->pdev->dev, \"Bring the PF device up before\"\n\t\t\t \" attempting to use the VF device.\\n\");\n\t}\n\treturn igb_set_vf_mac(adapter, vf, mac);\n}\n\nstatic int igb_link_mbps(int internal_link_speed)\n{\n\tswitch (internal_link_speed) {\n\tcase SPEED_100:\n\t\treturn 100;\n\tcase SPEED_1000:\n\t\treturn 1000;\n\tcase SPEED_2500:\n\t\treturn 2500;\n\tdefault:\n\t\treturn 0;\n\t}\n}\n\nstatic void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,\n\t\t\tint link_speed)\n{\n\tint rf_dec, rf_int;\n\tu32 bcnrc_val;\n\n\tif (tx_rate != 0) {\n\t\t/* Calculate the rate factor values to set */\n\t\trf_int = link_speed / tx_rate;\n\t\trf_dec = (link_speed - (rf_int * tx_rate));\n\t\trf_dec = (rf_dec * (1<vf_rate_link_speed == 0) ||\n\t\t(adapter->hw.mac.type != e1000_82576))\n\t\treturn;\n\n\tactual_link_speed = igb_link_mbps(adapter->link_speed);\n\tif (actual_link_speed != adapter->vf_rate_link_speed) {\n\t\treset_rate = true;\n\t\tadapter->vf_rate_link_speed = 0;\n\t\tdev_info(&adapter->pdev->dev,\n\t\t\"Link speed has been changed. VF Transmit rate is disabled\\n\");\n\t}\n\n\tfor (i = 0; i < adapter->vfs_allocated_count; i++) {\n\t\tif (reset_rate)\n\t\t\tadapter->vf_data[i].tx_rate = 0;\n\n\t\tigb_set_vf_rate_limit(&adapter->hw, i,\n\t\t\tadapter->vf_data[i].tx_rate, actual_link_speed);\n\t}\n}\n\n#ifdef HAVE_VF_MIN_MAX_TXRATE\nstatic int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int min_tx_rate,\n\t\t\t int tx_rate)\n#else /* HAVE_VF_MIN_MAX_TXRATE */\nstatic int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)\n#endif /* HAVE_VF_MIN_MAX_TXRATE */\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint actual_link_speed;\n\n\tif (hw->mac.type != e1000_82576)\n\t\treturn -EOPNOTSUPP;\n\n#ifdef HAVE_VF_MIN_MAX_TXRATE\n\tif (min_tx_rate)\n\t\treturn -EINVAL;\n#endif /* HAVE_VF_MIN_MAX_TXRATE */\n\n\tactual_link_speed = igb_link_mbps(adapter->link_speed);\n\tif ((vf >= adapter->vfs_allocated_count) ||\n\t\t(!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) ||\n\t\t(tx_rate < 0) || (tx_rate > actual_link_speed))\n\t\treturn -EINVAL;\n\n\tadapter->vf_rate_link_speed = actual_link_speed;\n\tadapter->vf_data[vf].tx_rate = (u16)tx_rate;\n\tigb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);\n\n\treturn 0;\n}\n\nstatic int igb_ndo_get_vf_config(struct net_device *netdev,\n\t\t\t\t int vf, struct ifla_vf_info *ivi)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tif (vf >= adapter->vfs_allocated_count)\n\t\treturn -EINVAL;\n\tivi->vf = vf;\n\tmemcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);\n#ifdef HAVE_VF_MIN_MAX_TXRATE\n\tivi->max_tx_rate = adapter->vf_data[vf].tx_rate;\n\tivi->min_tx_rate = 0;\n#else /* HAVE_VF_MIN_MAX_TXRATE */\n\tivi->tx_rate = adapter->vf_data[vf].tx_rate;\n#endif /* HAVE_VF_MIN_MAX_TXRATE */\n\tivi->vlan = adapter->vf_data[vf].pf_vlan;\n\tivi->qos = adapter->vf_data[vf].pf_qos;\n#ifdef HAVE_VF_SPOOFCHK_CONFIGURE\n\tivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;\n#endif\n\treturn 0;\n}\n#endif\nstatic void igb_vmm_control(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint count;\n\tu32 reg;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82575:\n\tdefault:\n\t\t/* replication is not supported for 82575 */\n\t\treturn;\n\tcase e1000_82576:\n\t\t/* notify HW that the MAC is adding vlan tags */\n\t\treg = E1000_READ_REG(hw, E1000_DTXCTL);\n\t\treg |= (E1000_DTXCTL_VLAN_ADDED |\n\t\t\tE1000_DTXCTL_SPOOF_INT);\n\t\tE1000_WRITE_REG(hw, E1000_DTXCTL, reg);\n\tcase e1000_82580:\n\t\t/* enable replication vlan tag stripping */\n\t\treg = E1000_READ_REG(hw, E1000_RPLOLR);\n\t\treg |= E1000_RPLOLR_STRVLAN;\n\t\tE1000_WRITE_REG(hw, E1000_RPLOLR, reg);\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\t/* none of the above registers are supported by i350 */\n\t\tbreak;\n\t}\n\n\t/* Enable Malicious Driver Detection */\n\tif ((adapter->vfs_allocated_count) &&\n\t (adapter->mdd)) {\n\t\tif (hw->mac.type == e1000_i350)\n\t\t\tigb_enable_mdd(adapter);\n\t}\n\n\t\t/* enable replication and loopback support */\n\t\tcount = adapter->vfs_allocated_count || adapter->vmdq_pools;\n\t\tif (adapter->flags & IGB_FLAG_LOOPBACK_ENABLE && count)\n\t\t\te1000_vmdq_set_loopback_pf(hw, 1);\n\t\te1000_vmdq_set_anti_spoofing_pf(hw,\n\t\t\tadapter->vfs_allocated_count || adapter->vmdq_pools,\n\t\t\tadapter->vfs_allocated_count);\n\te1000_vmdq_set_replication_pf(hw, adapter->vfs_allocated_count ||\n\t\t\t\t adapter->vmdq_pools);\n}\n\nstatic void igb_init_fw(struct igb_adapter *adapter)\n{\n\tstruct e1000_fw_drv_info fw_cmd;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint i;\n\tu16 mask;\n\n\tif (hw->mac.type == e1000_i210)\n\t\tmask = E1000_SWFW_EEP_SM;\n\telse\n\t\tmask = E1000_SWFW_PHY0_SM;\n\t/* i211 parts do not support this feature */\n\tif (hw->mac.type == e1000_i211)\n\t\thw->mac.arc_subsystem_valid = false;\n\n\tif (!hw->mac.ops.acquire_swfw_sync(hw, mask)) {\n\t\tfor (i = 0; i <= FW_MAX_RETRIES; i++) {\n\t\t\tE1000_WRITE_REG(hw, E1000_FWSTS, E1000_FWSTS_FWRI);\n\t\t\tfw_cmd.hdr.cmd = FW_CMD_DRV_INFO;\n\t\t\tfw_cmd.hdr.buf_len = FW_CMD_DRV_INFO_LEN;\n\t\t\tfw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CMD_RESERVED;\n\t\t\tfw_cmd.port_num = hw->bus.func;\n\t\t\tfw_cmd.drv_version = FW_FAMILY_DRV_VER;\n\t\t\tfw_cmd.hdr.checksum = 0;\n\t\t\tfw_cmd.hdr.checksum = e1000_calculate_checksum((u8 *)&fw_cmd,\n\t\t\t (FW_HDR_LEN +\n\t\t\t fw_cmd.hdr.buf_len));\n\t\t\t e1000_host_interface_command(hw, (u8*)&fw_cmd,\n\t\t\t sizeof(fw_cmd));\n\t\t\tif (fw_cmd.hdr.cmd_or_resp.ret_status == FW_STATUS_SUCCESS)\n\t\t\t\tbreak;\n\t\t}\n\t} else\n\t\tdev_warn(pci_dev_to_dev(adapter->pdev),\n\t\t\t \"Unable to get semaphore, firmware init failed.\\n\");\n\thw->mac.ops.release_swfw_sync(hw, mask);\n}\n\nstatic void igb_init_dmac(struct igb_adapter *adapter, u32 pba)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 dmac_thr;\n\tu16 hwm;\n\tu32 status;\n\n\tif (hw->mac.type == e1000_i211)\n\t\treturn;\n\n\tif (hw->mac.type > e1000_82580) {\n\t\tif (adapter->dmac != IGB_DMAC_DISABLE) {\n\t\t\tu32 reg;\n\n\t\t\t/* force threshold to 0. */\n\t\t\tE1000_WRITE_REG(hw, E1000_DMCTXTH, 0);\n\n\t\t\t/*\n\t\t\t * DMA Coalescing high water mark needs to be greater\n\t\t\t * than the Rx threshold. Set hwm to PBA - max frame\n\t\t\t * size in 16B units, capping it at PBA - 6KB.\n\t\t\t */\n\t\t\thwm = 64 * pba - adapter->max_frame_size / 16;\n\t\t\tif (hwm < 64 * (pba - 6))\n\t\t\t\thwm = 64 * (pba - 6);\n\t\t\treg = E1000_READ_REG(hw, E1000_FCRTC);\n\t\t\treg &= ~E1000_FCRTC_RTH_COAL_MASK;\n\t\t\treg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)\n\t\t\t\t& E1000_FCRTC_RTH_COAL_MASK);\n\t\t\tE1000_WRITE_REG(hw, E1000_FCRTC, reg);\n\n\t\t\t/*\n\t\t\t * Set the DMA Coalescing Rx threshold to PBA - 2 * max\n\t\t\t * frame size, capping it at PBA - 10KB.\n\t\t\t */\n\t\t\tdmac_thr = pba - adapter->max_frame_size / 512;\n\t\t\tif (dmac_thr < pba - 10)\n\t\t\t\tdmac_thr = pba - 10;\n\t\t\treg = E1000_READ_REG(hw, E1000_DMACR);\n\t\t\treg &= ~E1000_DMACR_DMACTHR_MASK;\n\t\t\treg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)\n\t\t\t\t& E1000_DMACR_DMACTHR_MASK);\n\n\t\t\t/* transition to L0x or L1 if available..*/\n\t\t\treg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);\n\n\t\t\t/* Check if status is 2.5Gb backplane connection\n\t\t\t * before configuration of watchdog timer, which is\n\t\t\t * in msec values in 12.8usec intervals\n\t\t\t * watchdog timer= msec values in 32usec intervals\n\t\t\t * for non 2.5Gb connection\n\t\t\t */\n\t\t\tif (hw->mac.type == e1000_i354) {\n\t\t\t\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\t\t\t\tif ((status & E1000_STATUS_2P5_SKU) &&\n\t\t\t\t (!(status & E1000_STATUS_2P5_SKU_OVER)))\n\t\t\t\t\treg |= ((adapter->dmac * 5) >> 6);\n\t\t\t\telse\n\t\t\t\t\treg |= ((adapter->dmac) >> 5);\n\t\t\t} else {\n\t\t\t\treg |= ((adapter->dmac) >> 5);\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Disable BMC-to-OS Watchdog enable\n\t\t\t * on devices that support OS-to-BMC\n\t\t\t */\n\t\t\tif (hw->mac.type != e1000_i354)\n\t\t\t\treg &= ~E1000_DMACR_DC_BMC2OSW_EN;\n\t\t\tE1000_WRITE_REG(hw, E1000_DMACR, reg);\n\n\t\t\t/* no lower threshold to disable coalescing(smart fifb)-UTRESH=0*/\n\t\t\tE1000_WRITE_REG(hw, E1000_DMCRTRH, 0);\n\n\t\t\t/* This sets the time to wait before requesting\n\t\t\t * transition to low power state to number of usecs\n\t\t\t * needed to receive 1 512 byte frame at gigabit\n\t\t\t * line rate. On i350 device, time to make transition\n\t\t\t * to Lx state is delayed by 4 usec with flush disable\n\t\t\t * bit set to avoid losing mailbox interrupts\n\t\t\t */\n\t\t\treg = E1000_READ_REG(hw, E1000_DMCTLX);\n\t\t\tif (hw->mac.type == e1000_i350)\n\t\t\t\treg |= IGB_DMCTLX_DCFLUSH_DIS;\n\n\t\t\t/* in 2.5Gb connection, TTLX unit is 0.4 usec\n\t\t\t * which is 0x4*2 = 0xA. But delay is still 4 usec\n\t\t\t */\n\t\t\tif (hw->mac.type == e1000_i354) {\n\t\t\t\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\t\t\t\tif ((status & E1000_STATUS_2P5_SKU) &&\n\t\t\t\t (!(status & E1000_STATUS_2P5_SKU_OVER)))\n\t\t\t\t\treg |= 0xA;\n\t\t\t\telse\n\t\t\t\t\treg |= 0x4;\n\t\t\t} else {\n\t\t\t\treg |= 0x4;\n\t\t\t}\n\t\t\tE1000_WRITE_REG(hw, E1000_DMCTLX, reg);\n\n\t\t\t/* free space in tx packet buffer to wake from DMA coal */\n\t\t\tE1000_WRITE_REG(hw, E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -\n\t\t\t\t(IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);\n\n\t\t\t/* make low power state decision controlled by DMA coal */\n\t\t\treg = E1000_READ_REG(hw, E1000_PCIEMISC);\n\t\t\treg &= ~E1000_PCIEMISC_LX_DECISION;\n\t\t\tE1000_WRITE_REG(hw, E1000_PCIEMISC, reg);\n\t\t} /* endif adapter->dmac is not disabled */\n\t} else if (hw->mac.type == e1000_82580) {\n\t\tu32 reg = E1000_READ_REG(hw, E1000_PCIEMISC);\n\t\tE1000_WRITE_REG(hw, E1000_PCIEMISC,\n\t\t reg & ~E1000_PCIEMISC_LX_DECISION);\n\t\tE1000_WRITE_REG(hw, E1000_DMACR, 0);\n\t}\n}\n\n#ifdef HAVE_I2C_SUPPORT\n/* igb_read_i2c_byte - Reads 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to read\n * @dev_addr: device address\n * @data: value read\n *\n * Performs byte read operation over I2C interface at\n * a specified device address.\n */\ns32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t\tu8 dev_addr, u8 *data)\n{\n\tstruct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);\n\tstruct i2c_client *this_client = adapter->i2c_client;\n\ts32 status;\n\tu16 swfw_mask = 0;\n\n\tif (!this_client)\n\t\treturn E1000_ERR_I2C;\n\n\tswfw_mask = E1000_SWFW_PHY0_SM;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)\n\t != E1000_SUCCESS)\n\t\treturn E1000_ERR_SWFW_SYNC;\n\n\tstatus = i2c_smbus_read_byte_data(this_client, byte_offset);\n\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\n\tif (status < 0)\n\t\treturn E1000_ERR_I2C;\n\telse {\n\t\t*data = status;\n\t\treturn E1000_SUCCESS;\n\t}\n}\n\n/* igb_write_i2c_byte - Writes 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @dev_addr: device address\n * @data: value to write\n *\n * Performs byte write operation over I2C interface at\n * a specified device address.\n */\ns32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data)\n{\n\tstruct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);\n\tstruct i2c_client *this_client = adapter->i2c_client;\n\ts32 status;\n\tu16 swfw_mask = E1000_SWFW_PHY0_SM;\n\n\tif (!this_client)\n\t\treturn E1000_ERR_I2C;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)\n\t\treturn E1000_ERR_SWFW_SYNC;\n\tstatus = i2c_smbus_write_byte_data(this_client, byte_offset, data);\n\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\n\tif (status)\n\t\treturn E1000_ERR_I2C;\n\telse\n\t\treturn E1000_SUCCESS;\n}\n#endif /* HAVE_I2C_SUPPORT */\n/* igb_main.c */\n\n\n/**\n * igb_probe - Device Initialization Routine\n * @pdev: PCI device information struct\n * @ent: entry in igb_pci_tbl\n *\n * Returns 0 on success, negative on failure\n *\n * igb_probe initializes an adapter identified by a pci_dev structure.\n * The OS initialization, configuring of the adapter private structure,\n * and a hardware reset occur.\n **/\nint igb_kni_probe(struct pci_dev *pdev,\n\t\t\t struct net_device **lad_dev)\n{\n\tstruct net_device *netdev;\n\tstruct igb_adapter *adapter;\n\tstruct e1000_hw *hw;\n\tu16 eeprom_data = 0;\n\tu8 pba_str[E1000_PBANUM_LENGTH];\n\ts32 ret_val;\n\tstatic int global_quad_port_a; /* global quad port a indication */\n\tint i, err, pci_using_dac = 0;\n\tstatic int cards_found;\n\n\terr = pci_enable_device_mem(pdev);\n\tif (err)\n\t\treturn err;\n\n#ifdef NO_KNI\n\tpci_using_dac = 0;\n\terr = dma_set_mask(pci_dev_to_dev(pdev), DMA_BIT_MASK(64));\n\tif (!err) {\n\t\terr = dma_set_coherent_mask(pci_dev_to_dev(pdev), DMA_BIT_MASK(64));\n\t\tif (!err)\n\t\t\tpci_using_dac = 1;\n\t} else {\n\t\terr = dma_set_mask(pci_dev_to_dev(pdev), DMA_BIT_MASK(32));\n\t\tif (err) {\n\t\t\terr = dma_set_coherent_mask(pci_dev_to_dev(pdev), DMA_BIT_MASK(32));\n\t\t\tif (err) {\n\t\t\t\tIGB_ERR(\"No usable DMA configuration, \"\n\t\t\t\t \"aborting\\n\");\n\t\t\t\tgoto err_dma;\n\t\t\t}\n\t\t}\n\t}\n\n#ifndef HAVE_ASPM_QUIRKS\n\t/* 82575 requires that the pci-e link partner disable the L0s state */\n\tswitch (pdev->device) {\n\tcase E1000_DEV_ID_82575EB_COPPER:\n\tcase E1000_DEV_ID_82575EB_FIBER_SERDES:\n\tcase E1000_DEV_ID_82575GB_QUAD_COPPER:\n\t\tpci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);\n\tdefault:\n\t\tbreak;\n\t}\n\n#endif /* HAVE_ASPM_QUIRKS */\n\terr = pci_request_selected_regions(pdev,\n\t pci_select_bars(pdev,\n IORESOURCE_MEM),\n\t igb_driver_name);\n\tif (err)\n\t\tgoto err_pci_reg;\n\n\tpci_enable_pcie_error_reporting(pdev);\n\n\tpci_set_master(pdev);\n\n\terr = -ENOMEM;\n#endif /* NO_KNI */\n#ifdef HAVE_TX_MQ\n\tnetdev = alloc_etherdev_mq(sizeof(struct igb_adapter),\n\t IGB_MAX_TX_QUEUES);\n#else\n\tnetdev = alloc_etherdev(sizeof(struct igb_adapter));\n#endif /* HAVE_TX_MQ */\n\tif (!netdev)\n\t\tgoto err_alloc_etherdev;\n\n\tSET_MODULE_OWNER(netdev);\n\tSET_NETDEV_DEV(netdev, &pdev->dev);\n\n\t//pci_set_drvdata(pdev, netdev);\n\tadapter = netdev_priv(netdev);\n\tadapter->netdev = netdev;\n\tadapter->pdev = pdev;\n\thw = &adapter->hw;\n\thw->back = adapter;\n\tadapter->port_num = hw->bus.func;\n\tadapter->msg_enable = (1 << debug) - 1;\n\n#ifdef HAVE_PCI_ERS\n\terr = pci_save_state(pdev);\n\tif (err)\n\t\tgoto err_ioremap;\n#endif\n\terr = -EIO;\n\thw->hw_addr = ioremap(pci_resource_start(pdev, 0),\n\t pci_resource_len(pdev, 0));\n\tif (!hw->hw_addr)\n\t\tgoto err_ioremap;\n\n#ifdef HAVE_NET_DEVICE_OPS\n\tnetdev->netdev_ops = &igb_netdev_ops;\n#else /* HAVE_NET_DEVICE_OPS */\n\tnetdev->open = &igb_open;\n\tnetdev->stop = &igb_close;\n\tnetdev->get_stats = &igb_get_stats;\n#ifdef HAVE_SET_RX_MODE\n\tnetdev->set_rx_mode = &igb_set_rx_mode;\n#endif\n\tnetdev->set_multicast_list = &igb_set_rx_mode;\n\tnetdev->set_mac_address = &igb_set_mac;\n\tnetdev->change_mtu = &igb_change_mtu;\n\tnetdev->do_ioctl = &igb_ioctl;\n#ifdef HAVE_TX_TIMEOUT\n\tnetdev->tx_timeout = &igb_tx_timeout;\n#endif\n\tnetdev->vlan_rx_register = igb_vlan_mode;\n\tnetdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;\n\tnetdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;\n#ifdef CONFIG_NET_POLL_CONTROLLER\n\tnetdev->poll_controller = igb_netpoll;\n#endif\n\tnetdev->hard_start_xmit = &igb_xmit_frame;\n#endif /* HAVE_NET_DEVICE_OPS */\n\tigb_set_ethtool_ops(netdev);\n#ifdef HAVE_TX_TIMEOUT\n\tnetdev->watchdog_timeo = 5 * HZ;\n#endif\n\n\tstrncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);\n\n\tadapter->bd_number = cards_found;\n\n\t/* setup the private structure */\n\terr = igb_sw_init(adapter);\n\tif (err)\n\t\tgoto err_sw_init;\n\n\te1000_get_bus_info(hw);\n\n\thw->phy.autoneg_wait_to_complete = FALSE;\n\thw->mac.adaptive_ifs = FALSE;\n\n\t/* Copper options */\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\t\thw->phy.mdix = AUTO_ALL_MODES;\n\t\thw->phy.disable_polarity_correction = FALSE;\n\t\thw->phy.ms_type = e1000_ms_hw_default;\n\t}\n\n\tif (e1000_check_reset_block(hw))\n\t\tdev_info(pci_dev_to_dev(pdev),\n\t\t\t\"PHY reset is blocked due to SOL/IDER session.\\n\");\n\n\t/*\n\t * features is initialized to 0 in allocation, it might have bits\n\t * set by igb_sw_init so we should use an or instead of an\n\t * assignment.\n\t */\n\tnetdev->features |= NETIF_F_SG |\n\t\t\t NETIF_F_IP_CSUM |\n#ifdef NETIF_F_IPV6_CSUM\n\t\t\t NETIF_F_IPV6_CSUM |\n#endif\n#ifdef NETIF_F_TSO\n\t\t\t NETIF_F_TSO |\n#ifdef NETIF_F_TSO6\n\t\t\t NETIF_F_TSO6 |\n#endif\n#endif /* NETIF_F_TSO */\n#ifdef NETIF_F_RXHASH\n\t\t\t NETIF_F_RXHASH |\n#endif\n\t\t\t NETIF_F_RXCSUM |\n#ifdef NETIF_F_HW_VLAN_CTAG_RX\n\t\t\t NETIF_F_HW_VLAN_CTAG_RX |\n\t\t\t NETIF_F_HW_VLAN_CTAG_TX;\n#else\n\t\t\t NETIF_F_HW_VLAN_RX |\n\t\t\t NETIF_F_HW_VLAN_TX;\n#endif\n\n\tif (hw->mac.type >= e1000_82576)\n\t\tnetdev->features |= NETIF_F_SCTP_CSUM;\n\n#ifdef HAVE_NDO_SET_FEATURES\n\t/* copy netdev features into list of user selectable features */\n\tnetdev->hw_features |= netdev->features;\n#ifndef IGB_NO_LRO\n\n\t/* give us the option of enabling LRO later */\n\tnetdev->hw_features |= NETIF_F_LRO;\n#endif\n#else\n#ifdef NETIF_F_GRO\n\n\t/* this is only needed on kernels prior to 2.6.39 */\n\tnetdev->features |= NETIF_F_GRO;\n#endif\n#endif\n\n\t/* set this bit last since it cannot be part of hw_features */\n#ifdef NETIF_F_HW_VLAN_CTAG_FILTER\n\tnetdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;\n#else\n\tnetdev->features |= NETIF_F_HW_VLAN_FILTER;\n#endif\n\n#ifdef HAVE_NETDEV_VLAN_FEATURES\n\tnetdev->vlan_features |= NETIF_F_TSO |\n\t\t\t\t NETIF_F_TSO6 |\n\t\t\t\t NETIF_F_IP_CSUM |\n\t\t\t\t NETIF_F_IPV6_CSUM |\n\t\t\t\t NETIF_F_SG;\n\n#endif\n\tif (pci_using_dac)\n\t\tnetdev->features |= NETIF_F_HIGHDMA;\n\n#ifdef NO_KNI\n\tadapter->en_mng_pt = e1000_enable_mng_pass_thru(hw);\n#ifdef DEBUG\n\tif (adapter->dmac != IGB_DMAC_DISABLE)\n\t\tprintk(\"%s: DMA Coalescing is enabled..\\n\", netdev->name);\n#endif\n\n\t/* before reading the NVM, reset the controller to put the device in a\n\t * known good starting state */\n\te1000_reset_hw(hw);\n#endif /* NO_KNI */\n\n\t/* make sure the NVM is good */\n\tif (e1000_validate_nvm_checksum(hw) < 0) {\n\t\tdev_err(pci_dev_to_dev(pdev), \"The NVM Checksum Is Not\"\n\t\t \" Valid\\n\");\n\t\terr = -EIO;\n\t\tgoto err_eeprom;\n\t}\n\n\t/* copy the MAC address out of the NVM */\n\tif (e1000_read_mac_addr(hw))\n\t\tdev_err(pci_dev_to_dev(pdev), \"NVM Read Error\\n\");\n\tmemcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);\n#ifdef ETHTOOL_GPERMADDR\n\tmemcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);\n\n\tif (!is_valid_ether_addr(netdev->perm_addr)) {\n#else\n\tif (!is_valid_ether_addr(netdev->dev_addr)) {\n#endif\n\t\tdev_err(pci_dev_to_dev(pdev), \"Invalid MAC Address\\n\");\n\t\terr = -EIO;\n\t\tgoto err_eeprom;\n\t}\n\n\tmemcpy(&adapter->mac_table[0].addr, hw->mac.addr, netdev->addr_len);\n\tadapter->mac_table[0].queue = adapter->vfs_allocated_count;\n\tadapter->mac_table[0].state = (IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE);\n\tigb_rar_set(adapter, 0);\n\n\t/* get firmware version for ethtool -i */\n\tigb_set_fw_version(adapter);\n\n\t/* Check if Media Autosense is enabled */\n\tif (hw->mac.type == e1000_82580)\n\t\tigb_init_mas(adapter);\n\n#ifdef NO_KNI\n\tsetup_timer(&adapter->watchdog_timer, &igb_watchdog,\n\t (unsigned long) adapter);\n\tif (adapter->flags & IGB_FLAG_DETECT_BAD_DMA)\n\t\tsetup_timer(&adapter->dma_err_timer, &igb_dma_err_timer,\n\t\t\t (unsigned long) adapter);\n\tsetup_timer(&adapter->phy_info_timer, &igb_update_phy_info,\n\t (unsigned long) adapter);\n\n\tINIT_WORK(&adapter->reset_task, igb_reset_task);\n\tINIT_WORK(&adapter->watchdog_task, igb_watchdog_task);\n\tif (adapter->flags & IGB_FLAG_DETECT_BAD_DMA)\n\t\tINIT_WORK(&adapter->dma_err_task, igb_dma_err_task);\n#endif\n\n\t/* Initialize link properties that are user-changeable */\n\tadapter->fc_autoneg = true;\n\thw->mac.autoneg = true;\n\thw->phy.autoneg_advertised = 0x2f;\n\n\thw->fc.requested_mode = e1000_fc_default;\n\thw->fc.current_mode = e1000_fc_default;\n\n\te1000_validate_mdi_setting(hw);\n\n\t/* By default, support wake on port A */\n\tif (hw->bus.func == 0)\n\t\tadapter->flags |= IGB_FLAG_WOL_SUPPORTED;\n\n\t/* Check the NVM for wake support for non-port A ports */\n\tif (hw->mac.type >= e1000_82580)\n\t\thw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +\n\t\t NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,\n\t\t &eeprom_data);\n\telse if (hw->bus.func == 1)\n\t\te1000_read_nvm(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);\n\n\tif (eeprom_data & IGB_EEPROM_APME)\n\t\tadapter->flags |= IGB_FLAG_WOL_SUPPORTED;\n\n\t/* now that we have the eeprom settings, apply the special cases where\n\t * the eeprom may be wrong or the board simply won't support wake on\n\t * lan on a particular port */\n\tswitch (pdev->device) {\n\tcase E1000_DEV_ID_82575GB_QUAD_COPPER:\n\t\tadapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;\n\t\tbreak;\n\tcase E1000_DEV_ID_82575EB_FIBER_SERDES:\n\tcase E1000_DEV_ID_82576_FIBER:\n\tcase E1000_DEV_ID_82576_SERDES:\n\t\t/* Wake events only supported on port A for dual fiber\n\t\t * regardless of eeprom setting */\n\t\tif (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FUNC_1)\n\t\t\tadapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;\n\t\tbreak;\n\tcase E1000_DEV_ID_82576_QUAD_COPPER:\n\tcase E1000_DEV_ID_82576_QUAD_COPPER_ET2:\n\t\t/* if quad port adapter, disable WoL on all but port A */\n\t\tif (global_quad_port_a != 0)\n\t\t\tadapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;\n\t\telse\n\t\t\tadapter->flags |= IGB_FLAG_QUAD_PORT_A;\n\t\t/* Reset for multiple quad port adapters */\n\t\tif (++global_quad_port_a == 4)\n\t\t\tglobal_quad_port_a = 0;\n\t\tbreak;\n\tdefault:\n\t\t/* If the device can't wake, don't set software support */\n\t\tif (!device_can_wakeup(&adapter->pdev->dev))\n\t\t\tadapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;\n\t\tbreak;\n\t}\n\n\t/* initialize the wol settings based on the eeprom settings */\n\tif (adapter->flags & IGB_FLAG_WOL_SUPPORTED)\n\t\tadapter->wol |= E1000_WUFC_MAG;\n\n\t/* Some vendors want WoL disabled by default, but still supported */\n\tif ((hw->mac.type == e1000_i350) &&\n\t (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {\n\t\tadapter->flags |= IGB_FLAG_WOL_SUPPORTED;\n\t\tadapter->wol = 0;\n\t}\n\n#ifdef NO_KNI\n\tdevice_set_wakeup_enable(pci_dev_to_dev(adapter->pdev),\n\t\t\t\t adapter->flags & IGB_FLAG_WOL_SUPPORTED);\n\n\t/* reset the hardware with the new settings */\n\tigb_reset(adapter);\n\tadapter->devrc = 0;\n\n#ifdef HAVE_I2C_SUPPORT\n\t/* Init the I2C interface */\n\terr = igb_init_i2c(adapter);\n\tif (err) {\n\t\tdev_err(&pdev->dev, \"failed to init i2c interface\\n\");\n\t\tgoto err_eeprom;\n\t}\n#endif /* HAVE_I2C_SUPPORT */\n\n\t/* let the f/w know that the h/w is now under the control of the\n\t * driver. */\n\tigb_get_hw_control(adapter);\n\n\tstrncpy(netdev->name, \"eth%d\", IFNAMSIZ);\n\terr = register_netdev(netdev);\n\tif (err)\n\t\tgoto err_register;\n\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n\terr = igb_init_vmdq_netdevs(adapter);\n\tif (err)\n\t\tgoto err_register;\n#endif\n\t/* carrier off reporting is important to ethtool even BEFORE open */\n\tnetif_carrier_off(netdev);\n\n#ifdef IGB_DCA\n\tif (dca_add_requester(&pdev->dev) == E1000_SUCCESS) {\n\t\tadapter->flags |= IGB_FLAG_DCA_ENABLED;\n\t\tdev_info(pci_dev_to_dev(pdev), \"DCA enabled\\n\");\n\t\tigb_setup_dca(adapter);\n\t}\n\n#endif\n#ifdef HAVE_PTP_1588_CLOCK\n\t/* do hw tstamp init after resetting */\n\tigb_ptp_init(adapter);\n#endif /* HAVE_PTP_1588_CLOCK */\n\n#endif /* NO_KNI */\n\tdev_info(pci_dev_to_dev(pdev), \"Intel(R) Gigabit Ethernet Network Connection\\n\");\n\t/* print bus type/speed/width info */\n\tdev_info(pci_dev_to_dev(pdev), \"%s: (PCIe:%s:%s) \",\n\t netdev->name,\n\t ((hw->bus.speed == e1000_bus_speed_2500) ? \"2.5GT/s\" :\n\t (hw->bus.speed == e1000_bus_speed_5000) ? \"5.0GT/s\" :\n\t\t (hw->mac.type == e1000_i354) ? \"integrated\" :\n\t \"unknown\"),\n\t ((hw->bus.width == e1000_bus_width_pcie_x4) ? \"Width x4\" :\n\t (hw->bus.width == e1000_bus_width_pcie_x2) ? \"Width x2\" :\n\t (hw->bus.width == e1000_bus_width_pcie_x1) ? \"Width x1\" :\n\t\t (hw->mac.type == e1000_i354) ? \"integrated\" :\n\t \"unknown\"));\n\tdev_info(pci_dev_to_dev(pdev), \"%s: MAC: \", netdev->name);\n\tfor (i = 0; i < 6; i++)\n\t\tprintk(\"%2.2x%c\", netdev->dev_addr[i], i == 5 ? '\\n' : ':');\n\n\tret_val = e1000_read_pba_string(hw, pba_str, E1000_PBANUM_LENGTH);\n\tif (ret_val)\n\t\tstrncpy(pba_str, \"Unknown\", sizeof(pba_str) - 1);\n\tdev_info(pci_dev_to_dev(pdev), \"%s: PBA No: %s\\n\", netdev->name,\n\t\t pba_str);\n\n\n\t/* Initialize the thermal sensor on i350 devices. */\n\tif (hw->mac.type == e1000_i350) {\n\t\tif (hw->bus.func == 0) {\n\t\t\tu16 ets_word;\n\n\t\t\t/*\n\t\t\t * Read the NVM to determine if this i350 device\n\t\t\t * supports an external thermal sensor.\n\t\t\t */\n\t\t\te1000_read_nvm(hw, NVM_ETS_CFG, 1, &ets_word);\n\t\t\tif (ets_word != 0x0000 && ets_word != 0xFFFF)\n\t\t\t\tadapter->ets = true;\n\t\t\telse\n\t\t\t\tadapter->ets = false;\n\t\t}\n#ifdef NO_KNI\n#ifdef IGB_HWMON\n\n\t\tigb_sysfs_init(adapter);\n#else\n#ifdef IGB_PROCFS\n\n\t\tigb_procfs_init(adapter);\n#endif /* IGB_PROCFS */\n#endif /* IGB_HWMON */\n#endif /* NO_KNI */\n\t} else {\n\t\tadapter->ets = false;\n\t}\n\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\t\tswitch (hw->mac.type) {\n\t\tcase e1000_i350:\n\t\tcase e1000_i210:\n\t\tcase e1000_i211:\n\t\t\t/* Enable EEE for internal copper PHY devices */\n\t\t\terr = e1000_set_eee_i350(hw);\n\t\t\tif ((!err) &&\n\t\t\t (adapter->flags & IGB_FLAG_EEE))\n\t\t\t\tadapter->eee_advert =\n\t\t\t\t\tMDIO_EEE_100TX | MDIO_EEE_1000T;\n\t\t\tbreak;\n\t\tcase e1000_i354:\n\t\t\tif ((E1000_READ_REG(hw, E1000_CTRL_EXT)) &\n\t\t\t (E1000_CTRL_EXT_LINK_MODE_SGMII)) {\n\t\t\t\terr = e1000_set_eee_i354(hw);\n\t\t\t\tif ((!err) &&\n\t\t\t\t (adapter->flags & IGB_FLAG_EEE))\n\t\t\t\t\tadapter->eee_advert =\n\t\t\t\t\t MDIO_EEE_100TX | MDIO_EEE_1000T;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* send driver version info to firmware */\n\tif (hw->mac.type >= e1000_i350)\n\t\tigb_init_fw(adapter);\n\n#ifndef IGB_NO_LRO\n\tif (netdev->features & NETIF_F_LRO)\n\t\tdev_info(pci_dev_to_dev(pdev), \"Internal LRO is enabled \\n\");\n\telse\n\t\tdev_info(pci_dev_to_dev(pdev), \"LRO is disabled \\n\");\n#endif\n\tdev_info(pci_dev_to_dev(pdev),\n\t \"Using %s interrupts. %d rx queue(s), %d tx queue(s)\\n\",\n\t adapter->msix_entries ? \"MSI-X\" :\n\t (adapter->flags & IGB_FLAG_HAS_MSI) ? \"MSI\" : \"legacy\",\n\t adapter->num_rx_queues, adapter->num_tx_queues);\n\n\tcards_found++;\n\t*lad_dev = netdev;\n\n\tpm_runtime_put_noidle(&pdev->dev);\n\treturn 0;\n\n//err_register:\n//\tigb_release_hw_control(adapter);\n#ifdef HAVE_I2C_SUPPORT\n\tmemset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));\n#endif /* HAVE_I2C_SUPPORT */\nerr_eeprom:\n//\tif (!e1000_check_reset_block(hw))\n//\t\te1000_phy_hw_reset(hw);\n\n\tif (hw->flash_address)\n\t\tiounmap(hw->flash_address);\nerr_sw_init:\n//\tigb_clear_interrupt_scheme(adapter);\n//\tigb_reset_sriov_capability(adapter);\n\tiounmap(hw->hw_addr);\nerr_ioremap:\n\tfree_netdev(netdev);\nerr_alloc_etherdev:\n//\tpci_release_selected_regions(pdev,\n//\t pci_select_bars(pdev, IORESOURCE_MEM));\n//err_pci_reg:\n//err_dma:\n\tpci_disable_device(pdev);\n\treturn err;\n}\n\n\nvoid igb_kni_remove(struct pci_dev *pdev)\n{\n\tpci_disable_device(pdev);\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/igb_param.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n\n#include \n\n#include \"igb.h\"\n\n/* This is the only thing that needs to be changed to adjust the\n * maximum number of ports that the driver can manage.\n */\n\n#define IGB_MAX_NIC 32\n\n#define OPTION_UNSET -1\n#define OPTION_DISABLED 0\n#define OPTION_ENABLED 1\n#define MAX_NUM_LIST_OPTS 15\n\n/* All parameters are treated the same, as an integer array of values.\n * This macro just reduces the need to repeat the same declaration code\n * over and over (plus this helps to avoid typo bugs).\n */\n\n#define IGB_PARAM_INIT { [0 ... IGB_MAX_NIC] = OPTION_UNSET }\n#ifndef module_param_array\n/* Module Parameters are always initialized to -1, so that the driver\n * can tell the difference between no user specified value or the\n * user asking for the default value.\n * The true default values are loaded in when igb_check_options is called.\n *\n * This is a GCC extension to ANSI C.\n * See the item \"Labeled Elements in Initializers\" in the section\n * \"Extensions to the C Language Family\" of the GCC documentation.\n */\n\n#define IGB_PARAM(X, desc) \\\n\tstatic const int X[IGB_MAX_NIC+1] = IGB_PARAM_INIT; \\\n\tMODULE_PARM(X, \"1-\" __MODULE_STRING(IGB_MAX_NIC) \"i\"); \\\n\tMODULE_PARM_DESC(X, desc);\n#else\n#define IGB_PARAM(X, desc) \\\n\tstatic int X[IGB_MAX_NIC+1] = IGB_PARAM_INIT; \\\n\tstatic unsigned int num_##X; \\\n\tmodule_param_array_named(X, X, int, &num_##X, 0); \\\n\tMODULE_PARM_DESC(X, desc);\n#endif\n\n/* Interrupt Throttle Rate (interrupts/sec)\n *\n * Valid Range: 100-100000 (0=off, 1=dynamic, 3=dynamic conservative)\n */\nIGB_PARAM(InterruptThrottleRate,\n\t \"Maximum interrupts per second, per vector, (max 100000), default 3=adaptive\");\n#define DEFAULT_ITR 3\n#define MAX_ITR 100000\n/* #define MIN_ITR 120 */\n#define MIN_ITR 0\n/* IntMode (Interrupt Mode)\n *\n * Valid Range: 0 - 2\n *\n * Default Value: 2 (MSI-X)\n */\nIGB_PARAM(IntMode, \"Change Interrupt Mode (0=Legacy, 1=MSI, 2=MSI-X), default 2\");\n#define MAX_INTMODE IGB_INT_MODE_MSIX\n#define MIN_INTMODE IGB_INT_MODE_LEGACY\n\nIGB_PARAM(Node, \"set the starting node to allocate memory on, default -1\");\n\n/* LLIPort (Low Latency Interrupt TCP Port)\n *\n * Valid Range: 0 - 65535\n *\n * Default Value: 0 (disabled)\n */\nIGB_PARAM(LLIPort, \"Low Latency Interrupt TCP Port (0-65535), default 0=off\");\n\n#define DEFAULT_LLIPORT 0\n#define MAX_LLIPORT 0xFFFF\n#define MIN_LLIPORT 0\n\n/* LLIPush (Low Latency Interrupt on TCP Push flag)\n *\n * Valid Range: 0, 1\n *\n * Default Value: 0 (disabled)\n */\nIGB_PARAM(LLIPush, \"Low Latency Interrupt on TCP Push flag (0,1), default 0=off\");\n\n#define DEFAULT_LLIPUSH 0\n#define MAX_LLIPUSH 1\n#define MIN_LLIPUSH 0\n\n/* LLISize (Low Latency Interrupt on Packet Size)\n *\n * Valid Range: 0 - 1500\n *\n * Default Value: 0 (disabled)\n */\nIGB_PARAM(LLISize, \"Low Latency Interrupt on Packet Size (0-1500), default 0=off\");\n\n#define DEFAULT_LLISIZE 0\n#define MAX_LLISIZE 1500\n#define MIN_LLISIZE 0\n\n/* RSS (Enable RSS multiqueue receive)\n *\n * Valid Range: 0 - 8\n *\n * Default Value: 1\n */\nIGB_PARAM(RSS, \"Number of Receive-Side Scaling Descriptor Queues (0-8), default 1, 0=number of cpus\");\n\n#define DEFAULT_RSS 1\n#define MAX_RSS 8\n#define MIN_RSS 0\n\n/* VMDQ (Enable VMDq multiqueue receive)\n *\n * Valid Range: 0 - 8\n *\n * Default Value: 0\n */\nIGB_PARAM(VMDQ, \"Number of Virtual Machine Device Queues: 0-1 = disable, 2-8 enable, default 0\");\n\n#define DEFAULT_VMDQ 0\n#define MAX_VMDQ MAX_RSS\n#define MIN_VMDQ 0\n\n/* max_vfs (Enable SR-IOV VF devices)\n *\n * Valid Range: 0 - 7\n *\n * Default Value: 0\n */\nIGB_PARAM(max_vfs, \"Number of Virtual Functions: 0 = disable, 1-7 enable, default 0\");\n\n#define DEFAULT_SRIOV 0\n#define MAX_SRIOV 7\n#define MIN_SRIOV 0\n\n/* MDD (Enable Malicious Driver Detection)\n *\n * Only available when SR-IOV is enabled - max_vfs is greater than 0\n *\n * Valid Range: 0, 1\n *\n * Default Value: 1\n */\nIGB_PARAM(MDD, \"Malicious Driver Detection (0/1), default 1 = enabled. \"\n\t \"Only available when max_vfs is greater than 0\");\n\n#ifdef DEBUG\n\n/* Disable Hardware Reset on Tx Hang\n *\n * Valid Range: 0, 1\n *\n * Default Value: 0 (disabled, i.e. h/w will reset)\n */\nIGB_PARAM(DisableHwReset, \"Disable reset of hardware on Tx hang\");\n\n/* Dump Transmit and Receive buffers\n *\n * Valid Range: 0, 1\n *\n * Default Value: 0\n */\nIGB_PARAM(DumpBuffers, \"Dump Tx/Rx buffers on Tx hang or by request\");\n\n#endif /* DEBUG */\n\n/* QueuePairs (Enable TX/RX queue pairs for interrupt handling)\n *\n * Valid Range: 0 - 1\n *\n * Default Value: 1\n */\nIGB_PARAM(QueuePairs, \"Enable Tx/Rx queue pairs for interrupt handling (0,1), default 1=on\");\n\n#define DEFAULT_QUEUE_PAIRS 1\n#define MAX_QUEUE_PAIRS 1\n#define MIN_QUEUE_PAIRS 0\n\n/* Enable/disable EEE (a.k.a. IEEE802.3az)\n *\n * Valid Range: 0, 1\n *\n * Default Value: 1\n */\n IGB_PARAM(EEE, \"Enable/disable on parts that support the feature\");\n\n/* Enable/disable DMA Coalescing\n *\n * Valid Values: 0(off), 1000, 2000, 3000, 4000, 5000, 6000, 7000, 8000,\n * 9000, 10000(msec), 250(usec), 500(usec)\n *\n * Default Value: 0\n */\n IGB_PARAM(DMAC, \"Disable or set latency for DMA Coalescing ((0=off, 1000-10000(msec), 250, 500 (usec))\");\n\n#ifndef IGB_NO_LRO\n/* Enable/disable Large Receive Offload\n *\n * Valid Values: 0(off), 1(on)\n *\n * Default Value: 0\n */\n IGB_PARAM(LRO, \"Large Receive Offload (0,1), default 0=off\");\n\n#endif\nstruct igb_opt_list {\n\tint i;\n\tchar *str;\n};\nstruct igb_option {\n\tenum { enable_option, range_option, list_option } type;\n\tconst char *name;\n\tconst char *err;\n\tint def;\n\tunion {\n\t\tstruct { /* range_option info */\n\t\t\tint min;\n\t\t\tint max;\n\t\t} r;\n\t\tstruct { /* list_option info */\n\t\t\tint nr;\n\t\t\tstruct igb_opt_list *p;\n\t\t} l;\n\t} arg;\n};\n\nstatic int igb_validate_option(unsigned int *value,\n\t\t\t struct igb_option *opt,\n\t\t\t struct igb_adapter *adapter)\n{\n\tif (*value == OPTION_UNSET) {\n\t\t*value = opt->def;\n\t\treturn 0;\n\t}\n\n\tswitch (opt->type) {\n\tcase enable_option:\n\t\tswitch (*value) {\n\t\tcase OPTION_ENABLED:\n\t\t\tDPRINTK(PROBE, INFO, \"%s Enabled\\n\", opt->name);\n\t\t\treturn 0;\n\t\tcase OPTION_DISABLED:\n\t\t\tDPRINTK(PROBE, INFO, \"%s Disabled\\n\", opt->name);\n\t\t\treturn 0;\n\t\t}\n\t\tbreak;\n\tcase range_option:\n\t\tif (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {\n\t\t\tDPRINTK(PROBE, INFO,\n\t\t\t\t\t\"%s set to %d\\n\", opt->name, *value);\n\t\t\treturn 0;\n\t\t}\n\t\tbreak;\n\tcase list_option: {\n\t\tint i;\n\t\tstruct igb_opt_list *ent;\n\n\t\tfor (i = 0; i < opt->arg.l.nr; i++) {\n\t\t\tent = &opt->arg.l.p[i];\n\t\t\tif (*value == ent->i) {\n\t\t\t\tif (ent->str[0] != '\\0')\n\t\t\t\t\tDPRINTK(PROBE, INFO, \"%s\\n\", ent->str);\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\n\t\tbreak;\n\tdefault:\n\t\tBUG();\n\t}\n\n\tDPRINTK(PROBE, INFO, \"Invalid %s value specified (%d) %s\\n\",\n\t opt->name, *value, opt->err);\n\t*value = opt->def;\n\treturn -1;\n}\n\n/**\n * igb_check_options - Range Checking for Command Line Parameters\n * @adapter: board private structure\n *\n * This routine checks all command line parameters for valid user\n * input. If an invalid value is given, or if no user specified\n * value exists, a default value is used. The final value is stored\n * in a variable in the adapter structure.\n **/\n\nvoid igb_check_options(struct igb_adapter *adapter)\n{\n\tint bd = adapter->bd_number;\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\tif (bd >= IGB_MAX_NIC) {\n\t\tDPRINTK(PROBE, NOTICE,\n\t\t \"Warning: no configuration for board #%d\\n\", bd);\n\t\tDPRINTK(PROBE, NOTICE, \"Using defaults for all values\\n\");\n#ifndef module_param_array\n\t\tbd = IGB_MAX_NIC;\n#endif\n\t}\n\n\t{ /* Interrupt Throttling Rate */\n\t\tstruct igb_option opt = {\n\t\t\t.type = range_option,\n\t\t\t.name = \"Interrupt Throttling Rate (ints/sec)\",\n\t\t\t.err = \"using default of \" __MODULE_STRING(DEFAULT_ITR),\n\t\t\t.def = DEFAULT_ITR,\n\t\t\t.arg = { .r = { .min = MIN_ITR,\n\t\t\t\t\t .max = MAX_ITR } }\n\t\t};\n\n#ifdef module_param_array\n\t\tif (num_InterruptThrottleRate > bd) {\n#endif\n\t\t\tunsigned int itr = InterruptThrottleRate[bd];\n\n\t\t\tswitch (itr) {\n\t\t\tcase 0:\n\t\t\t\tDPRINTK(PROBE, INFO, \"%s turned off\\n\",\n\t\t\t\t opt.name);\n\t\t\t\tif (hw->mac.type >= e1000_i350)\n\t\t\t\t\tadapter->dmac = IGB_DMAC_DISABLE;\n\t\t\t\tadapter->rx_itr_setting = itr;\n\t\t\t\tbreak;\n\t\t\tcase 1:\n\t\t\t\tDPRINTK(PROBE, INFO, \"%s set to dynamic mode\\n\",\n\t\t\t\t\topt.name);\n\t\t\t\tadapter->rx_itr_setting = itr;\n\t\t\t\tbreak;\n\t\t\tcase 3:\n\t\t\t\tDPRINTK(PROBE, INFO,\n\t\t\t\t \"%s set to dynamic conservative mode\\n\",\n\t\t\t\t\topt.name);\n\t\t\t\tadapter->rx_itr_setting = itr;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tigb_validate_option(&itr, &opt, adapter);\n\t\t\t\t/* Save the setting, because the dynamic bits\n\t\t\t\t * change itr. In case of invalid user value,\n\t\t\t\t * default to conservative mode, else need to\n\t\t\t\t * clear the lower two bits because they are\n\t\t\t\t * used as control */\n\t\t\t\tif (itr == 3) {\n\t\t\t\t\tadapter->rx_itr_setting = itr;\n\t\t\t\t} else {\n\t\t\t\t\tadapter->rx_itr_setting = 1000000000 /\n\t\t\t\t\t (itr * 256);\n\t\t\t\t\tadapter->rx_itr_setting &= ~3;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n#ifdef module_param_array\n\t\t} else {\n\t\t\tadapter->rx_itr_setting = opt.def;\n\t\t}\n#endif\n\t\tadapter->tx_itr_setting = adapter->rx_itr_setting;\n\t}\n\t{ /* Interrupt Mode */\n\t\tstruct igb_option opt = {\n\t\t\t.type = range_option,\n\t\t\t.name = \"Interrupt Mode\",\n\t\t\t.err = \"defaulting to 2 (MSI-X)\",\n\t\t\t.def = IGB_INT_MODE_MSIX,\n\t\t\t.arg = { .r = { .min = MIN_INTMODE,\n\t\t\t\t\t .max = MAX_INTMODE } }\n\t\t};\n\n#ifdef module_param_array\n\t\tif (num_IntMode > bd) {\n#endif\n\t\t\tunsigned int int_mode = IntMode[bd];\n\t\t\tigb_validate_option(&int_mode, &opt, adapter);\n\t\t\tadapter->int_mode = int_mode;\n#ifdef module_param_array\n\t\t} else {\n\t\t\tadapter->int_mode = opt.def;\n\t\t}\n#endif\n\t}\n\t{ /* Low Latency Interrupt TCP Port */\n\t\tstruct igb_option opt = {\n\t\t\t.type = range_option,\n\t\t\t.name = \"Low Latency Interrupt TCP Port\",\n\t\t\t.err = \"using default of \" __MODULE_STRING(DEFAULT_LLIPORT),\n\t\t\t.def = DEFAULT_LLIPORT,\n\t\t\t.arg = { .r = { .min = MIN_LLIPORT,\n\t\t\t\t\t .max = MAX_LLIPORT } }\n\t\t};\n\n#ifdef module_param_array\n\t\tif (num_LLIPort > bd) {\n#endif\n\t\t\tadapter->lli_port = LLIPort[bd];\n\t\t\tif (adapter->lli_port) {\n\t\t\t\tigb_validate_option(&adapter->lli_port, &opt,\n\t\t\t\t adapter);\n\t\t\t} else {\n\t\t\t\tDPRINTK(PROBE, INFO, \"%s turned off\\n\",\n\t\t\t\t\topt.name);\n\t\t\t}\n#ifdef module_param_array\n\t\t} else {\n\t\t\tadapter->lli_port = opt.def;\n\t\t}\n#endif\n\t}\n\t{ /* Low Latency Interrupt on Packet Size */\n\t\tstruct igb_option opt = {\n\t\t\t.type = range_option,\n\t\t\t.name = \"Low Latency Interrupt on Packet Size\",\n\t\t\t.err = \"using default of \" __MODULE_STRING(DEFAULT_LLISIZE),\n\t\t\t.def = DEFAULT_LLISIZE,\n\t\t\t.arg = { .r = { .min = MIN_LLISIZE,\n\t\t\t\t\t .max = MAX_LLISIZE } }\n\t\t};\n\n#ifdef module_param_array\n\t\tif (num_LLISize > bd) {\n#endif\n\t\t\tadapter->lli_size = LLISize[bd];\n\t\t\tif (adapter->lli_size) {\n\t\t\t\tigb_validate_option(&adapter->lli_size, &opt,\n\t\t\t\t adapter);\n\t\t\t} else {\n\t\t\t\tDPRINTK(PROBE, INFO, \"%s turned off\\n\",\n\t\t\t\t\topt.name);\n\t\t\t}\n#ifdef module_param_array\n\t\t} else {\n\t\t\tadapter->lli_size = opt.def;\n\t\t}\n#endif\n\t}\n\t{ /* Low Latency Interrupt on TCP Push flag */\n\t\tstruct igb_option opt = {\n\t\t\t.type = enable_option,\n\t\t\t.name = \"Low Latency Interrupt on TCP Push flag\",\n\t\t\t.err = \"defaulting to Disabled\",\n\t\t\t.def = OPTION_DISABLED\n\t\t};\n\n#ifdef module_param_array\n\t\tif (num_LLIPush > bd) {\n#endif\n\t\t\tunsigned int lli_push = LLIPush[bd];\n\t\t\tigb_validate_option(&lli_push, &opt, adapter);\n\t\t\tadapter->flags |= lli_push ? IGB_FLAG_LLI_PUSH : 0;\n#ifdef module_param_array\n\t\t} else {\n\t\t\tadapter->flags |= opt.def ? IGB_FLAG_LLI_PUSH : 0;\n\t\t}\n#endif\n\t}\n\t{ /* SRIOV - Enable SR-IOV VF devices */\n\t\tstruct igb_option opt = {\n\t\t\t.type = range_option,\n\t\t\t.name = \"max_vfs - SR-IOV VF devices\",\n\t\t\t.err = \"using default of \" __MODULE_STRING(DEFAULT_SRIOV),\n\t\t\t.def = DEFAULT_SRIOV,\n\t\t\t.arg = { .r = { .min = MIN_SRIOV,\n\t\t\t\t\t .max = MAX_SRIOV } }\n\t\t};\n\n#ifdef module_param_array\n\t\tif (num_max_vfs > bd) {\n#endif\n\t\t\tadapter->vfs_allocated_count = max_vfs[bd];\n\t\t\tigb_validate_option(&adapter->vfs_allocated_count, &opt, adapter);\n\n#ifdef module_param_array\n\t\t} else {\n\t\t\tadapter->vfs_allocated_count = opt.def;\n\t\t}\n#endif\n\t\tif (adapter->vfs_allocated_count) {\n\t\t\tswitch (hw->mac.type) {\n\t\t\tcase e1000_82575:\n\t\t\tcase e1000_82580:\n\t\t\tcase e1000_i210:\n\t\t\tcase e1000_i211:\n\t\t\tcase e1000_i354:\n\t\t\t\tadapter->vfs_allocated_count = 0;\n\t\t\t\tDPRINTK(PROBE, INFO, \"SR-IOV option max_vfs not supported.\\n\");\n\t\t\tdefault:\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\t{ /* VMDQ - Enable VMDq multiqueue receive */\n\t\tstruct igb_option opt = {\n\t\t\t.type = range_option,\n\t\t\t.name = \"VMDQ - VMDq multiqueue queue count\",\n\t\t\t.err = \"using default of \" __MODULE_STRING(DEFAULT_VMDQ),\n\t\t\t.def = DEFAULT_VMDQ,\n\t\t\t.arg = { .r = { .min = MIN_VMDQ,\n\t\t\t\t\t .max = (MAX_VMDQ - adapter->vfs_allocated_count) } }\n\t\t};\n\t\tif ((hw->mac.type != e1000_i210) ||\n\t\t (hw->mac.type != e1000_i211)) {\n#ifdef module_param_array\n\t\tif (num_VMDQ > bd) {\n#endif\n\t\t\tadapter->vmdq_pools = (VMDQ[bd] == 1 ? 0 : VMDQ[bd]);\n\t\t\tif (adapter->vfs_allocated_count && !adapter->vmdq_pools) {\n\t\t\t\tDPRINTK(PROBE, INFO, \"Enabling SR-IOV requires VMDq be set to at least 1\\n\");\n\t\t\t\tadapter->vmdq_pools = 1;\n\t\t\t}\n\t\t\tigb_validate_option(&adapter->vmdq_pools, &opt, adapter);\n\n#ifdef module_param_array\n\t\t} else {\n\t\t\tif (!adapter->vfs_allocated_count)\n\t\t\t\tadapter->vmdq_pools = (opt.def == 1 ? 0 : opt.def);\n\t\t\telse\n\t\t\t\tadapter->vmdq_pools = 1;\n\t\t}\n#endif\n#ifdef CONFIG_IGB_VMDQ_NETDEV\n\t\tif (hw->mac.type == e1000_82575 && adapter->vmdq_pools) {\n\t\t\tDPRINTK(PROBE, INFO, \"VMDq not supported on this part.\\n\");\n\t\t\tadapter->vmdq_pools = 0;\n\t\t}\n#endif\n\n\t} else {\n\t\tDPRINTK(PROBE, INFO, \"VMDq option is not supported.\\n\");\n\t\tadapter->vmdq_pools = opt.def;\n\t}\n\t}\n\t{ /* RSS - Enable RSS multiqueue receives */\n\t\tstruct igb_option opt = {\n\t\t\t.type = range_option,\n\t\t\t.name = \"RSS - RSS multiqueue receive count\",\n\t\t\t.err = \"using default of \" __MODULE_STRING(DEFAULT_RSS),\n\t\t\t.def = DEFAULT_RSS,\n\t\t\t.arg = { .r = { .min = MIN_RSS,\n\t\t\t\t\t .max = MAX_RSS } }\n\t\t};\n\n\t\tswitch (hw->mac.type) {\n\t\tcase e1000_82575:\n#ifndef CONFIG_IGB_VMDQ_NETDEV\n\t\t\tif (!!adapter->vmdq_pools) {\n\t\t\t\tif (adapter->vmdq_pools <= 2) {\n\t\t\t\t\tif (adapter->vmdq_pools == 2)\n\t\t\t\t\t\topt.arg.r.max = 3;\n\t\t\t\t} else {\n\t\t\t\t\topt.arg.r.max = 1;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\topt.arg.r.max = 4;\n\t\t\t}\n#else\n\t\t\topt.arg.r.max = !!adapter->vmdq_pools ? 1 : 4;\n#endif /* CONFIG_IGB_VMDQ_NETDEV */\n\t\t\tbreak;\n\t\tcase e1000_i210:\n\t\t\topt.arg.r.max = 4;\n\t\t\tbreak;\n\t\tcase e1000_i211:\n\t\t\topt.arg.r.max = 2;\n\t\t\tbreak;\n\t\tcase e1000_82576:\n#ifndef CONFIG_IGB_VMDQ_NETDEV\n\t\t\tif (!!adapter->vmdq_pools)\n\t\t\t\topt.arg.r.max = 2;\n\t\t\tbreak;\n#endif /* CONFIG_IGB_VMDQ_NETDEV */\n\t\tcase e1000_82580:\n\t\tcase e1000_i350:\n\t\tcase e1000_i354:\n\t\tdefault:\n\t\t\tif (!!adapter->vmdq_pools)\n\t\t\t\topt.arg.r.max = 1;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (adapter->int_mode != IGB_INT_MODE_MSIX) {\n\t\t\tDPRINTK(PROBE, INFO, \"RSS is not supported when in MSI/Legacy Interrupt mode, %s\\n\",\n\t\t\t\topt.err);\n\t\t\topt.arg.r.max = 1;\n\t\t}\n\n#ifdef module_param_array\n\t\tif (num_RSS > bd) {\n#endif\n\t\t\tadapter->rss_queues = RSS[bd];\n\t\t\tswitch (adapter->rss_queues) {\n\t\t\tcase 1:\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tigb_validate_option(&adapter->rss_queues, &opt, adapter);\n\t\t\t\tif (adapter->rss_queues)\n\t\t\t\t\tbreak;\n\t\t\tcase 0:\n\t\t\t\tadapter->rss_queues = min_t(u32, opt.arg.r.max, num_online_cpus());\n\t\t\t\tbreak;\n\t\t\t}\n#ifdef module_param_array\n\t\t} else {\n\t\t\tadapter->rss_queues = opt.def;\n\t\t}\n#endif\n\t}\n\t{ /* QueuePairs - Enable Tx/Rx queue pairs for interrupt handling */\n\t\tstruct igb_option opt = {\n\t\t\t.type = enable_option,\n\t\t\t.name = \"QueuePairs - Tx/Rx queue pairs for interrupt handling\",\n\t\t\t.err = \"defaulting to Enabled\",\n\t\t\t.def = OPTION_ENABLED\n\t\t};\n#ifdef module_param_array\n\t\tif (num_QueuePairs > bd) {\n#endif\n\t\t\tunsigned int qp = QueuePairs[bd];\n\t\t\t/*\n\t\t\t * We must enable queue pairs if the number of queues\n\t\t\t * exceeds the number of available interrupts. We are\n\t\t\t * limited to 10, or 3 per unallocated vf. On I210 and\n\t\t\t * I211 devices, we are limited to 5 interrupts.\n\t\t\t * However, since I211 only supports 2 queues, we do not\n\t\t\t * need to check and override the user option.\n\t\t\t */\n\t\t\tif (qp == OPTION_DISABLED) {\n\t\t\t\tif (adapter->rss_queues > 4)\n\t\t\t\t\tqp = OPTION_ENABLED;\n\n\t\t\t\tif (adapter->vmdq_pools > 4)\n\t\t\t\t\tqp = OPTION_ENABLED;\n\n\t\t\t\tif (adapter->rss_queues > 1 &&\n\t\t\t\t (adapter->vmdq_pools > 3 ||\n\t\t\t\t adapter->vfs_allocated_count > 6))\n\t\t\t\t\tqp = OPTION_ENABLED;\n\n\t\t\t\tif (hw->mac.type == e1000_i210 &&\n\t\t\t\t adapter->rss_queues > 2)\n\t\t\t\t\tqp = OPTION_ENABLED;\n\n\t\t\t\tif (qp == OPTION_ENABLED)\n\t\t\t\t\tDPRINTK(PROBE, INFO, \"Number of queues exceeds available interrupts, %s\\n\",\n\t\t\t\t\t\topt.err);\n\t\t\t}\n\t\t\tigb_validate_option(&qp, &opt, adapter);\n\t\t\tadapter->flags |= qp ? IGB_FLAG_QUEUE_PAIRS : 0;\n#ifdef module_param_array\n\t\t} else {\n\t\t\tadapter->flags |= opt.def ? IGB_FLAG_QUEUE_PAIRS : 0;\n\t\t}\n#endif\n\t}\n\t{ /* EEE - Enable EEE for capable adapters */\n\n\t\tif (hw->mac.type >= e1000_i350) {\n\t\t\tstruct igb_option opt = {\n\t\t\t\t.type = enable_option,\n\t\t\t\t.name = \"EEE Support\",\n\t\t\t\t.err = \"defaulting to Enabled\",\n\t\t\t\t.def = OPTION_ENABLED\n\t\t\t};\n#ifdef module_param_array\n\t\t\tif (num_EEE > bd) {\n#endif\n\t\t\t\tunsigned int eee = EEE[bd];\n\t\t\t\tigb_validate_option(&eee, &opt, adapter);\n\t\t\t\tadapter->flags |= eee ? IGB_FLAG_EEE : 0;\n\t\t\t\tif (eee)\n\t\t\t\t\thw->dev_spec._82575.eee_disable = false;\n\t\t\t\telse\n\t\t\t\t\thw->dev_spec._82575.eee_disable = true;\n\n#ifdef module_param_array\n\t\t\t} else {\n\t\t\t\tadapter->flags |= opt.def ? IGB_FLAG_EEE : 0;\n\t\t\t\tif (adapter->flags & IGB_FLAG_EEE)\n\t\t\t\t\thw->dev_spec._82575.eee_disable = false;\n\t\t\t\telse\n\t\t\t\t\thw->dev_spec._82575.eee_disable = true;\n\t\t\t}\n#endif\n\t\t}\n\t}\n\t{ /* DMAC - Enable DMA Coalescing for capable adapters */\n\n\t\tif (hw->mac.type >= e1000_i350) {\n\t\t\tstruct igb_opt_list list [] = {\n\t\t\t\t{ IGB_DMAC_DISABLE, \"DMAC Disable\"},\n\t\t\t\t{ IGB_DMAC_MIN, \"DMAC 250 usec\"},\n\t\t\t\t{ IGB_DMAC_500, \"DMAC 500 usec\"},\n\t\t\t\t{ IGB_DMAC_EN_DEFAULT, \"DMAC 1000 usec\"},\n\t\t\t\t{ IGB_DMAC_2000, \"DMAC 2000 usec\"},\n\t\t\t\t{ IGB_DMAC_3000, \"DMAC 3000 usec\"},\n\t\t\t\t{ IGB_DMAC_4000, \"DMAC 4000 usec\"},\n\t\t\t\t{ IGB_DMAC_5000, \"DMAC 5000 usec\"},\n\t\t\t\t{ IGB_DMAC_6000, \"DMAC 6000 usec\"},\n\t\t\t\t{ IGB_DMAC_7000, \"DMAC 7000 usec\"},\n\t\t\t\t{ IGB_DMAC_8000, \"DMAC 8000 usec\"},\n\t\t\t\t{ IGB_DMAC_9000, \"DMAC 9000 usec\"},\n\t\t\t\t{ IGB_DMAC_MAX, \"DMAC 10000 usec\"}\n\t\t\t};\n\t\t\tstruct igb_option opt = {\n\t\t\t\t.type = list_option,\n\t\t\t\t.name = \"DMA Coalescing\",\n\t\t\t\t.err = \"using default of \"__MODULE_STRING(IGB_DMAC_DISABLE),\n\t\t\t\t.def = IGB_DMAC_DISABLE,\n\t\t\t\t.arg = { .l = { .nr = 13,\n\t\t\t\t\t \t.p = list\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t};\n#ifdef module_param_array\n\t\t\tif (num_DMAC > bd) {\n#endif\n\t\t\t\tunsigned int dmac = DMAC[bd];\n\t\t\t\tif (adapter->rx_itr_setting == IGB_DMAC_DISABLE)\n\t\t\t\t\tdmac = IGB_DMAC_DISABLE;\n\t\t\t\tigb_validate_option(&dmac, &opt, adapter);\n\t\t\t\tswitch (dmac) {\n\t\t\t\tcase IGB_DMAC_DISABLE:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tcase IGB_DMAC_MIN:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tcase IGB_DMAC_500:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tcase IGB_DMAC_EN_DEFAULT:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tcase IGB_DMAC_2000:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tcase IGB_DMAC_3000:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tcase IGB_DMAC_4000:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tcase IGB_DMAC_5000:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tcase IGB_DMAC_6000:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tcase IGB_DMAC_7000:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tcase IGB_DMAC_8000:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tcase IGB_DMAC_9000:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tcase IGB_DMAC_MAX:\n\t\t\t\t\tadapter->dmac = dmac;\n\t\t\t\t\tbreak;\n\t\t\t\tdefault:\n\t\t\t\t\tadapter->dmac = opt.def;\n\t\t\t\t\tDPRINTK(PROBE, INFO,\n\t\t\t\t\t\"Invalid DMAC setting, \"\n\t\t\t\t\t\"resetting DMAC to %d\\n\", opt.def);\n\t\t\t\t}\n#ifdef module_param_array\n\t\t\t} else\n\t\t\t\tadapter->dmac = opt.def;\n#endif\n\t\t}\n\t}\n#ifndef IGB_NO_LRO\n\t{ /* LRO - Enable Large Receive Offload */\n\t\tstruct igb_option opt = {\n\t\t\t.type = enable_option,\n\t\t\t.name = \"LRO - Large Receive Offload\",\n\t\t\t.err = \"defaulting to Disabled\",\n\t\t\t.def = OPTION_DISABLED\n\t\t};\n\t\tstruct net_device *netdev = adapter->netdev;\n#ifdef module_param_array\n\t\tif (num_LRO > bd) {\n#endif\n\t\t\tunsigned int lro = LRO[bd];\n\t\t\tigb_validate_option(&lro, &opt, adapter);\n\t\t\tnetdev->features |= lro ? NETIF_F_LRO : 0;\n#ifdef module_param_array\n\t\t} else if (opt.def == OPTION_ENABLED) {\n\t\t\tnetdev->features |= NETIF_F_LRO;\n\t\t}\n#endif\n\t}\n#endif /* IGB_NO_LRO */\n\t{ /* MDD - Enable Malicious Driver Detection. Only available when\n\t SR-IOV is enabled. */\n\t\tstruct igb_option opt = {\n\t\t\t.type = enable_option,\n\t\t\t.name = \"Malicious Driver Detection\",\n\t\t\t.err = \"defaulting to 1\",\n\t\t\t.def = OPTION_ENABLED,\n\t\t\t.arg = { .r = { .min = OPTION_DISABLED,\n\t\t\t\t\t .max = OPTION_ENABLED } }\n\t\t};\n\n#ifdef module_param_array\n\t\tif (num_MDD > bd) {\n#endif\n\t\t\tadapter->mdd = MDD[bd];\n\t\t\tigb_validate_option((uint *)&adapter->mdd, &opt,\n\t\t\t\t\t adapter);\n#ifdef module_param_array\n\t\t} else {\n\t\t\tadapter->mdd = opt.def;\n\t\t}\n#endif\n\t}\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/igb_procfs.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"igb.h\"\n#include \"e1000_82575.h\"\n#include \"e1000_hw.h\"\n\n#ifdef IGB_PROCFS\n#ifndef IGB_HWMON\n\n#include \n#include \n#include \n#include \n#include \n\nstatic struct proc_dir_entry *igb_top_dir = NULL;\n\n\nbool igb_thermal_present(struct igb_adapter *adapter)\n{\n\ts32 status;\n\tstruct e1000_hw *hw;\n\n\tif (adapter == NULL)\n\t\treturn false;\n\thw = &adapter->hw;\n\n\t/*\n\t * Only set I2C bit-bang mode if an external thermal sensor is\n\t * supported on this device.\n\t */\n\tif (adapter->ets) {\n\t\tstatus = e1000_set_i2c_bb(hw);\n\t\tif (status != E1000_SUCCESS)\n\t\t\treturn false;\n\t}\n\n\tstatus = hw->mac.ops.init_thermal_sensor_thresh(hw);\n\tif (status != E1000_SUCCESS)\n\t\treturn false;\n\n\treturn true;\n}\n\n\nstatic int igb_macburn(char *page, char **start, off_t off, int count,\n\t\t\tint *eof, void *data)\n{\n\tstruct e1000_hw *hw;\n\tstruct igb_adapter *adapter = (struct igb_adapter *)data;\n\tif (adapter == NULL)\n\t\treturn snprintf(page, count, \"error: no adapter\\n\");\n\n\thw = &adapter->hw;\n\tif (hw == NULL)\n\t\treturn snprintf(page, count, \"error: no hw data\\n\");\n\n\treturn snprintf(page, count, \"0x%02X%02X%02X%02X%02X%02X\\n\",\n\t\t (unsigned int)hw->mac.perm_addr[0],\n\t\t (unsigned int)hw->mac.perm_addr[1],\n\t\t (unsigned int)hw->mac.perm_addr[2],\n\t\t (unsigned int)hw->mac.perm_addr[3],\n\t\t (unsigned int)hw->mac.perm_addr[4],\n\t\t (unsigned int)hw->mac.perm_addr[5]);\n}\n\nstatic int igb_macadmn(char *page, char **start, off_t off,\n\t\t int count, int *eof, void *data)\n{\n\tstruct e1000_hw *hw;\n\tstruct igb_adapter *adapter = (struct igb_adapter *)data;\n\tif (adapter == NULL)\n\t\treturn snprintf(page, count, \"error: no adapter\\n\");\n\n\thw = &adapter->hw;\n\tif (hw == NULL)\n\t\treturn snprintf(page, count, \"error: no hw data\\n\");\n\n\treturn snprintf(page, count, \"0x%02X%02X%02X%02X%02X%02X\\n\",\n\t\t (unsigned int)hw->mac.addr[0],\n\t\t (unsigned int)hw->mac.addr[1],\n\t\t (unsigned int)hw->mac.addr[2],\n\t\t (unsigned int)hw->mac.addr[3],\n\t\t (unsigned int)hw->mac.addr[4],\n\t\t (unsigned int)hw->mac.addr[5]);\n}\n\nstatic int igb_numeports(char *page, char **start, off_t off, int count,\n\t\t\t int *eof, void *data)\n{\n\tstruct e1000_hw *hw;\n\tint ports;\n\tstruct igb_adapter *adapter = (struct igb_adapter *)data;\n\tif (adapter == NULL)\n\t\treturn snprintf(page, count, \"error: no adapter\\n\");\n\n\thw = &adapter->hw;\n\tif (hw == NULL)\n\t\treturn snprintf(page, count, \"error: no hw data\\n\");\n\n\tports = 4;\n\n\treturn snprintf(page, count, \"%d\\n\", ports);\n}\n\nstatic int igb_porttype(char *page, char **start, off_t off, int count,\n\t\t\tint *eof, void *data)\n{\n\tstruct igb_adapter *adapter = (struct igb_adapter *)data;\n\tif (adapter == NULL)\n\t\treturn snprintf(page, count, \"error: no adapter\\n\");\n\n\treturn snprintf(page, count, \"%d\\n\",\n\t\t\ttest_bit(__IGB_DOWN, &adapter->state));\n}\n\nstatic int igb_therm_location(char *page, char **start, off_t off,\n\t\t\t\t int count, int *eof, void *data)\n{\n\tstruct igb_therm_proc_data *therm_data =\n\t\t(struct igb_therm_proc_data *)data;\n\n\tif (therm_data == NULL)\n\t\treturn snprintf(page, count, \"error: no therm_data\\n\");\n\n\treturn snprintf(page, count, \"%d\\n\", therm_data->sensor_data->location);\n}\n\nstatic int igb_therm_maxopthresh(char *page, char **start, off_t off,\n\t\t\t\t int count, int *eof, void *data)\n{\n\tstruct igb_therm_proc_data *therm_data =\n\t\t(struct igb_therm_proc_data *)data;\n\n\tif (therm_data == NULL)\n\t\treturn snprintf(page, count, \"error: no therm_data\\n\");\n\n\treturn snprintf(page, count, \"%d\\n\",\n\t\t\ttherm_data->sensor_data->max_op_thresh);\n}\n\nstatic int igb_therm_cautionthresh(char *page, char **start, off_t off,\n\t\t\t\t int count, int *eof, void *data)\n{\n\tstruct igb_therm_proc_data *therm_data =\n\t\t(struct igb_therm_proc_data *)data;\n\n\tif (therm_data == NULL)\n\t\treturn snprintf(page, count, \"error: no therm_data\\n\");\n\n\treturn snprintf(page, count, \"%d\\n\",\n\t\t\ttherm_data->sensor_data->caution_thresh);\n}\n\nstatic int igb_therm_temp(char *page, char **start, off_t off,\n\t\t\t int count, int *eof, void *data)\n{\n\ts32 status;\n\tstruct igb_therm_proc_data *therm_data =\n\t\t(struct igb_therm_proc_data *)data;\n\n\tif (therm_data == NULL)\n\t\treturn snprintf(page, count, \"error: no therm_data\\n\");\n\n\tstatus = e1000_get_thermal_sensor_data(therm_data->hw);\n\tif (status != E1000_SUCCESS)\n\t\tsnprintf(page, count, \"error: status %d returned\\n\", status);\n\n\treturn snprintf(page, count, \"%d\\n\", therm_data->sensor_data->temp);\n}\n\nstruct igb_proc_type{\n\tchar name[32];\n\tint (*read)(char*, char**, off_t, int, int*, void*);\n};\n\nstruct igb_proc_type igb_proc_entries[] = {\n\t{\"numeports\", &igb_numeports},\n\t{\"porttype\", &igb_porttype},\n\t{\"macburn\", &igb_macburn},\n\t{\"macadmn\", &igb_macadmn},\n\t{\"\", NULL}\n};\n\nstruct igb_proc_type igb_internal_entries[] = {\n\t{\"location\", &igb_therm_location},\n\t{\"temp\", &igb_therm_temp},\n\t{\"cautionthresh\", &igb_therm_cautionthresh},\n\t{\"maxopthresh\", &igb_therm_maxopthresh},\n\t{\"\", NULL}\n};\n\nvoid igb_del_proc_entries(struct igb_adapter *adapter)\n{\n\tint index, i;\n\tchar buf[16];\t/* much larger than the sensor number will ever be */\n\n\tif (igb_top_dir == NULL)\n\t\treturn;\n\n\tfor (i = 0; i < E1000_MAX_SENSORS; i++) {\n\t\tif (adapter->therm_dir[i] == NULL)\n\t\t\tcontinue;\n\n\t\tfor (index = 0; ; index++) {\n\t\t\tif (igb_internal_entries[index].read == NULL)\n\t\t\t\tbreak;\n\n\t\t\t remove_proc_entry(igb_internal_entries[index].name,\n\t\t\t\t\t adapter->therm_dir[i]);\n\t\t}\n\t\tsnprintf(buf, sizeof(buf), \"sensor_%d\", i);\n\t\tremove_proc_entry(buf, adapter->info_dir);\n\t}\n\n\tif (adapter->info_dir != NULL) {\n\t\tfor (index = 0; ; index++) {\n\t\t\tif (igb_proc_entries[index].read == NULL)\n\t\t\t\tbreak;\n\t\t remove_proc_entry(igb_proc_entries[index].name,\n\t\t\t\t\t adapter->info_dir);\n\t\t}\n\t\tremove_proc_entry(\"info\", adapter->eth_dir);\n\t}\n\n\tif (adapter->eth_dir != NULL)\n\t\tremove_proc_entry(pci_name(adapter->pdev), igb_top_dir);\n}\n\n/* called from igb_main.c */\nvoid igb_procfs_exit(struct igb_adapter *adapter)\n{\n\tigb_del_proc_entries(adapter);\n}\n\nint igb_procfs_topdir_init(void)\n{\n\tigb_top_dir = proc_mkdir(\"driver/igb\", NULL);\n\tif (igb_top_dir == NULL)\n\t\treturn -ENOMEM;\n\n\treturn 0;\n}\n\nvoid igb_procfs_topdir_exit(void)\n{\n\tremove_proc_entry(\"driver/igb\", NULL);\n}\n\n/* called from igb_main.c */\nint igb_procfs_init(struct igb_adapter *adapter)\n{\n\tint rc = 0;\n\tint i;\n\tint index;\n\tchar buf[16];\t/* much larger than the sensor number will ever be */\n\n\tadapter->eth_dir = NULL;\n\tadapter->info_dir = NULL;\n\tfor (i = 0; i < E1000_MAX_SENSORS; i++)\n\t\tadapter->therm_dir[i] = NULL;\n\n\tif ( igb_top_dir == NULL ) {\n\t\trc = -ENOMEM;\n\t\tgoto fail;\n\t}\n\n\tadapter->eth_dir = proc_mkdir(pci_name(adapter->pdev), igb_top_dir);\n\tif (adapter->eth_dir == NULL) {\n\t\trc = -ENOMEM;\n\t\tgoto fail;\n\t}\n\n\tadapter->info_dir = proc_mkdir(\"info\", adapter->eth_dir);\n\tif (adapter->info_dir == NULL) {\n\t\trc = -ENOMEM;\n\t\tgoto fail;\n\t}\n\tfor (index = 0; ; index++) {\n\t\tif (igb_proc_entries[index].read == NULL) {\n\t\t\tbreak;\n\t\t}\n\t\tif (!(create_proc_read_entry(igb_proc_entries[index].name,\n\t\t\t\t\t 0444,\n\t\t\t\t\t adapter->info_dir,\n\t\t\t\t\t igb_proc_entries[index].read,\n\t\t\t\t\t adapter))) {\n\n\t\t\trc = -ENOMEM;\n\t\t\tgoto fail;\n\t\t}\n\t}\n\tif (igb_thermal_present(adapter) == false)\n\t\tgoto exit;\n\n\tfor (i = 0; i < E1000_MAX_SENSORS; i++) {\n\n\t\t if (adapter->hw.mac.thermal_sensor_data.sensor[i].location== 0)\n\t\t\tcontinue;\n\n\t\tsnprintf(buf, sizeof(buf), \"sensor_%d\", i);\n\t\tadapter->therm_dir[i] = proc_mkdir(buf, adapter->info_dir);\n\t\tif (adapter->therm_dir[i] == NULL) {\n\t\t\trc = -ENOMEM;\n\t\t\tgoto fail;\n\t\t}\n\t\tfor (index = 0; ; index++) {\n\t\t\tif (igb_internal_entries[index].read == NULL)\n\t\t\t\tbreak;\n\t\t\t/*\n\t\t\t * therm_data struct contains pointer the read func\n\t\t\t * will be needing\n\t\t\t */\n\t\t\tadapter->therm_data[i].hw = &adapter->hw;\n\t\t\tadapter->therm_data[i].sensor_data =\n\t\t\t\t&adapter->hw.mac.thermal_sensor_data.sensor[i];\n\n\t\t\tif (!(create_proc_read_entry(\n\t\t\t\t\t igb_internal_entries[index].name,\n\t\t\t\t\t 0444,\n\t\t\t\t\t adapter->therm_dir[i],\n\t\t\t\t\t igb_internal_entries[index].read,\n\t\t\t\t\t &adapter->therm_data[i]))) {\n\t\t\t\trc = -ENOMEM;\n\t\t\t\tgoto fail;\n\t\t\t}\n\t\t}\n\t}\n\tgoto exit;\n\nfail:\n\tigb_del_proc_entries(adapter);\nexit:\n\treturn rc;\n}\n\n#endif /* !IGB_HWMON */\n#endif /* IGB_PROCFS */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/igb_ptp.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n/******************************************************************************\n Copyright(c) 2011 Richard Cochran for some of the\n 82576 and 82580 code\n******************************************************************************/\n\n#include \"igb.h\"\n\n#include \n#include \n#include \n#include \n\n#define INCVALUE_MASK\t\t0x7fffffff\n#define ISGN\t\t\t0x80000000\n\n/*\n * The 82580 timesync updates the system timer every 8ns by 8ns,\n * and this update value cannot be reprogrammed.\n *\n * Neither the 82576 nor the 82580 offer registers wide enough to hold\n * nanoseconds time values for very long. For the 82580, SYSTIM always\n * counts nanoseconds, but the upper 24 bits are not available. The\n * frequency is adjusted by changing the 32 bit fractional nanoseconds\n * register, TIMINCA.\n *\n * For the 82576, the SYSTIM register time unit is affect by the\n * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this\n * field are needed to provide the nominal 16 nanosecond period,\n * leaving 19 bits for fractional nanoseconds.\n *\n * We scale the NIC clock cycle by a large factor so that relatively\n * small clock corrections can be added or subtracted at each clock\n * tick. The drawbacks of a large factor are a) that the clock\n * register overflows more quickly (not such a big deal) and b) that\n * the increment per tick has to fit into 24 bits. As a result we\n * need to use a shift of 19 so we can fit a value of 16 into the\n * TIMINCA register.\n *\n *\n * SYSTIMH SYSTIML\n * +--------------+ +---+---+------+\n * 82576 | 32 | | 8 | 5 | 19 |\n * +--------------+ +---+---+------+\n * \\________ 45 bits _______/ fract\n *\n * +----------+---+ +--------------+\n * 82580 | 24 | 8 | | 32 |\n * +----------+---+ +--------------+\n * reserved \\______ 40 bits _____/\n *\n *\n * The 45 bit 82576 SYSTIM overflows every\n * 2^45 * 10^-9 / 3600 = 9.77 hours.\n *\n * The 40 bit 82580 SYSTIM overflows every\n * 2^40 * 10^-9 / 60 = 18.3 minutes.\n */\n\n#define IGB_SYSTIM_OVERFLOW_PERIOD\t(HZ * 60 * 9)\n#define IGB_PTP_TX_TIMEOUT\t\t(HZ * 15)\n#define INCPERIOD_82576\t\t\t(1 << E1000_TIMINCA_16NS_SHIFT)\n#define INCVALUE_82576_MASK\t\t((1 << E1000_TIMINCA_16NS_SHIFT) - 1)\n#define INCVALUE_82576\t\t\t(16 << IGB_82576_TSYNC_SHIFT)\n#define IGB_NBITS_82580\t\t\t40\n\n/*\n * SYSTIM read access for the 82576\n */\n\nstatic cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)\n{\n\tstruct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);\n\tstruct e1000_hw *hw = &igb->hw;\n\tu64 val;\n\tu32 lo, hi;\n\n\tlo = E1000_READ_REG(hw, E1000_SYSTIML);\n\thi = E1000_READ_REG(hw, E1000_SYSTIMH);\n\n\tval = ((u64) hi) << 32;\n\tval |= lo;\n\n\treturn val;\n}\n\n/*\n * SYSTIM read access for the 82580\n */\n\nstatic cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)\n{\n\tstruct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);\n\tstruct e1000_hw *hw = &igb->hw;\n\tu64 val;\n\tu32 lo, hi;\n\n\t/* The timestamp latches on lowest register read. For the 82580\n\t * the lowest register is SYSTIMR instead of SYSTIML. However we only\n\t * need to provide nanosecond resolution, so we just ignore it.\n\t */\n\tE1000_READ_REG(hw, E1000_SYSTIMR);\n\tlo = E1000_READ_REG(hw, E1000_SYSTIML);\n\thi = E1000_READ_REG(hw, E1000_SYSTIMH);\n\n\tval = ((u64) hi) << 32;\n\tval |= lo;\n\n\treturn val;\n}\n\n/*\n * SYSTIM read access for I210/I211\n */\n\nstatic void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 sec, nsec;\n\n\t/* The timestamp latches on lowest register read. For I210/I211, the\n\t * lowest register is SYSTIMR. Since we only need to provide nanosecond\n\t * resolution, we can ignore it.\n\t */\n\tE1000_READ_REG(hw, E1000_SYSTIMR);\n\tnsec = E1000_READ_REG(hw, E1000_SYSTIML);\n\tsec = E1000_READ_REG(hw, E1000_SYSTIMH);\n\n\tts->tv_sec = sec;\n\tts->tv_nsec = nsec;\n}\n\nstatic void igb_ptp_write_i210(struct igb_adapter *adapter,\n\t\t\t const struct timespec *ts)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\t/*\n\t * Writing the SYSTIMR register is not necessary as it only provides\n\t * sub-nanosecond resolution.\n\t */\n\tE1000_WRITE_REG(hw, E1000_SYSTIML, ts->tv_nsec);\n\tE1000_WRITE_REG(hw, E1000_SYSTIMH, ts->tv_sec);\n}\n\n/**\n * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp\n * @adapter: board private structure\n * @hwtstamps: timestamp structure to update\n * @systim: unsigned 64bit system time value.\n *\n * We need to convert the system time value stored in the RX/TXSTMP registers\n * into a hwtstamp which can be used by the upper level timestamping functions.\n *\n * The 'tmreg_lock' spinlock is used to protect the consistency of the\n * system time value. This is needed because reading the 64 bit time\n * value involves reading two (or three) 32 bit registers. The first\n * read latches the value. Ditto for writing.\n *\n * In addition, here have extended the system time with an overflow\n * counter in software.\n **/\nstatic void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,\n\t\t\t\t struct skb_shared_hwtstamps *hwtstamps,\n\t\t\t\t u64 systim)\n{\n\tunsigned long flags;\n\tu64 ns;\n\n\tswitch (adapter->hw.mac.type) {\n\tcase e1000_82576:\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\tspin_lock_irqsave(&adapter->tmreg_lock, flags);\n\n\t\tns = timecounter_cyc2time(&adapter->tc, systim);\n\n\t\tspin_unlock_irqrestore(&adapter->tmreg_lock, flags);\n\n\t\tmemset(hwtstamps, 0, sizeof(*hwtstamps));\n\t\thwtstamps->hwtstamp = ns_to_ktime(ns);\n\t\tbreak;\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\tmemset(hwtstamps, 0, sizeof(*hwtstamps));\n\t\t/* Upper 32 bits contain s, lower 32 bits contain ns. */\n\t\thwtstamps->hwtstamp = ktime_set(systim >> 32,\n\t\t\t\t\t\tsystim & 0xFFFFFFFF);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n/*\n * PTP clock operations\n */\n\nstatic int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)\n{\n\tstruct igb_adapter *igb = container_of(ptp, struct igb_adapter,\n\t\t\t\t\t ptp_caps);\n\tstruct e1000_hw *hw = &igb->hw;\n\tint neg_adj = 0;\n\tu64 rate;\n\tu32 incvalue;\n\n\tif (ppb < 0) {\n\t\tneg_adj = 1;\n\t\tppb = -ppb;\n\t}\n\trate = ppb;\n\trate <<= 14;\n\trate = div_u64(rate, 1953125);\n\n\tincvalue = 16 << IGB_82576_TSYNC_SHIFT;\n\n\tif (neg_adj)\n\t\tincvalue -= rate;\n\telse\n\t\tincvalue += rate;\n\n\tE1000_WRITE_REG(hw, E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));\n\n\treturn 0;\n}\n\nstatic int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)\n{\n\tstruct igb_adapter *igb = container_of(ptp, struct igb_adapter,\n\t\t\t\t\t ptp_caps);\n\tstruct e1000_hw *hw = &igb->hw;\n\tint neg_adj = 0;\n\tu64 rate;\n\tu32 inca;\n\n\tif (ppb < 0) {\n\t\tneg_adj = 1;\n\t\tppb = -ppb;\n\t}\n\trate = ppb;\n\trate <<= 26;\n\trate = div_u64(rate, 1953125);\n\n\t/* At 2.5G speeds, the TIMINCA register on I354 updates the clock 2.5x\n\t * as quickly. Account for this by dividing the adjustment by 2.5.\n\t */\n\tif (hw->mac.type == e1000_i354) {\n\t\tu32 status = E1000_READ_REG(hw, E1000_STATUS);\n\n\t\tif ((status & E1000_STATUS_2P5_SKU) &&\n\t\t !(status & E1000_STATUS_2P5_SKU_OVER)) {\n\t\t\trate <<= 1;\n\t\t\trate = div_u64(rate, 5);\n\t\t}\n\t}\n\n\tinca = rate & INCVALUE_MASK;\n\tif (neg_adj)\n\t\tinca |= ISGN;\n\n\tE1000_WRITE_REG(hw, E1000_TIMINCA, inca);\n\n\treturn 0;\n}\n\nstatic int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)\n{\n\tstruct igb_adapter *igb = container_of(ptp, struct igb_adapter,\n\t\t\t\t\t ptp_caps);\n\tunsigned long flags;\n\ts64 now;\n\n\tspin_lock_irqsave(&igb->tmreg_lock, flags);\n\n\tnow = timecounter_read(&igb->tc);\n\tnow += delta;\n\ttimecounter_init(&igb->tc, &igb->cc, now);\n\n\tspin_unlock_irqrestore(&igb->tmreg_lock, flags);\n\n\treturn 0;\n}\n\nstatic int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)\n{\n\tstruct igb_adapter *igb = container_of(ptp, struct igb_adapter,\n\t\t\t\t\t ptp_caps);\n\tunsigned long flags;\n\tstruct timespec now, then = ns_to_timespec(delta);\n\n\tspin_lock_irqsave(&igb->tmreg_lock, flags);\n\n\tigb_ptp_read_i210(igb, &now);\n\tnow = timespec_add(now, then);\n\tigb_ptp_write_i210(igb, (const struct timespec *)&now);\n\n\tspin_unlock_irqrestore(&igb->tmreg_lock, flags);\n\n\treturn 0;\n}\n\nstatic int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,\n\t\t\t\t struct timespec *ts)\n{\n\tstruct igb_adapter *igb = container_of(ptp, struct igb_adapter,\n\t\t\t\t\t ptp_caps);\n\tunsigned long flags;\n\tu64 ns;\n\tu32 remainder;\n\n\tspin_lock_irqsave(&igb->tmreg_lock, flags);\n\n\tns = timecounter_read(&igb->tc);\n\n\tspin_unlock_irqrestore(&igb->tmreg_lock, flags);\n\n\tts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);\n\tts->tv_nsec = remainder;\n\n\treturn 0;\n}\n\nstatic int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,\n\t\t\t\tstruct timespec *ts)\n{\n\tstruct igb_adapter *igb = container_of(ptp, struct igb_adapter,\n\t\t\t\t\t ptp_caps);\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&igb->tmreg_lock, flags);\n\n\tigb_ptp_read_i210(igb, ts);\n\n\tspin_unlock_irqrestore(&igb->tmreg_lock, flags);\n\n\treturn 0;\n}\n\nstatic int igb_ptp_settime_82576(struct ptp_clock_info *ptp,\n\t\t\t\t const struct timespec *ts)\n{\n\tstruct igb_adapter *igb = container_of(ptp, struct igb_adapter,\n\t\t\t\t\t ptp_caps);\n\tunsigned long flags;\n\tu64 ns;\n\n\tns = ts->tv_sec * 1000000000ULL;\n\tns += ts->tv_nsec;\n\n\tspin_lock_irqsave(&igb->tmreg_lock, flags);\n\n\ttimecounter_init(&igb->tc, &igb->cc, ns);\n\n\tspin_unlock_irqrestore(&igb->tmreg_lock, flags);\n\n\treturn 0;\n}\n\nstatic int igb_ptp_settime_i210(struct ptp_clock_info *ptp,\n\t\t\t\tconst struct timespec *ts)\n{\n\tstruct igb_adapter *igb = container_of(ptp, struct igb_adapter,\n\t\t\t\t\t ptp_caps);\n\tunsigned long flags;\n\n\tspin_lock_irqsave(&igb->tmreg_lock, flags);\n\n\tigb_ptp_write_i210(igb, ts);\n\n\tspin_unlock_irqrestore(&igb->tmreg_lock, flags);\n\n\treturn 0;\n}\n\nstatic int igb_ptp_enable(struct ptp_clock_info *ptp,\n\t\t\t struct ptp_clock_request *rq, int on)\n{\n\treturn -EOPNOTSUPP;\n}\n\n/**\n * igb_ptp_tx_work\n * @work: pointer to work struct\n *\n * This work function polls the TSYNCTXCTL valid bit to determine when a\n * timestamp has been taken for the current stored skb.\n */\nvoid igb_ptp_tx_work(struct work_struct *work)\n{\n\tstruct igb_adapter *adapter = container_of(work, struct igb_adapter,\n\t\t\t\t\t\t ptp_tx_work);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 tsynctxctl;\n\n\tif (!adapter->ptp_tx_skb)\n\t\treturn;\n\n\tif (time_is_before_jiffies(adapter->ptp_tx_start +\n\t\t\t\t IGB_PTP_TX_TIMEOUT)) {\n\t\tdev_kfree_skb_any(adapter->ptp_tx_skb);\n\t\tadapter->ptp_tx_skb = NULL;\n\t\tadapter->tx_hwtstamp_timeouts++;\n\t\tdev_warn(&adapter->pdev->dev, \"clearing Tx timestamp hang\");\n\t\treturn;\n\t}\n\n\ttsynctxctl = E1000_READ_REG(hw, E1000_TSYNCTXCTL);\n\tif (tsynctxctl & E1000_TSYNCTXCTL_VALID)\n\t\tigb_ptp_tx_hwtstamp(adapter);\n\telse\n\t\t/* reschedule to check later */\n\t\tschedule_work(&adapter->ptp_tx_work);\n}\n\nstatic void igb_ptp_overflow_check(struct work_struct *work)\n{\n\tstruct igb_adapter *igb =\n\t\tcontainer_of(work, struct igb_adapter, ptp_overflow_work.work);\n\tstruct timespec ts;\n\n\tigb->ptp_caps.gettime(&igb->ptp_caps, &ts);\n\n\tpr_debug(\"igb overflow check at %ld.%09lu\\n\", ts.tv_sec, ts.tv_nsec);\n\n\tschedule_delayed_work(&igb->ptp_overflow_work,\n\t\t\t IGB_SYSTIM_OVERFLOW_PERIOD);\n}\n\n/**\n * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched\n * @adapter: private network adapter structure\n *\n * This watchdog task is scheduled to detect error case where hardware has\n * dropped an Rx packet that was timestamped when the ring is full. The\n * particular error is rare but leaves the device in a state unable to timestamp\n * any future packets.\n */\nvoid igb_ptp_rx_hang(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct igb_ring *rx_ring;\n\tu32 tsyncrxctl = E1000_READ_REG(hw, E1000_TSYNCRXCTL);\n\tunsigned long rx_event;\n\tint n;\n\n\tif (hw->mac.type != e1000_82576)\n\t\treturn;\n\n\t/* If we don't have a valid timestamp in the registers, just update the\n\t * timeout counter and exit\n\t */\n\tif (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {\n\t\tadapter->last_rx_ptp_check = jiffies;\n\t\treturn;\n\t}\n\n\t/* Determine the most recent watchdog or rx_timestamp event */\n\trx_event = adapter->last_rx_ptp_check;\n\tfor (n = 0; n < adapter->num_rx_queues; n++) {\n\t\trx_ring = adapter->rx_ring[n];\n\t\tif (time_after(rx_ring->last_rx_timestamp, rx_event))\n\t\t\trx_event = rx_ring->last_rx_timestamp;\n\t}\n\n\t/* Only need to read the high RXSTMP register to clear the lock */\n\tif (time_is_before_jiffies(rx_event + 5 * HZ)) {\n\t\tE1000_READ_REG(hw, E1000_RXSTMPH);\n\t\tadapter->last_rx_ptp_check = jiffies;\n\t\tadapter->rx_hwtstamp_cleared++;\n\t\tdev_warn(&adapter->pdev->dev, \"clearing Rx timestamp hang\");\n\t}\n}\n\n/**\n * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp\n * @adapter: Board private structure.\n *\n * If we were asked to do hardware stamping and such a time stamp is\n * available, then it must have been for this skb here because we only\n * allow only one such packet into the queue.\n */\nvoid igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct skb_shared_hwtstamps shhwtstamps;\n\tu64 regval;\n\n\tregval = E1000_READ_REG(hw, E1000_TXSTMPL);\n\tregval |= (u64)E1000_READ_REG(hw, E1000_TXSTMPH) << 32;\n\n\tigb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);\n\tskb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);\n\tdev_kfree_skb_any(adapter->ptp_tx_skb);\n\tadapter->ptp_tx_skb = NULL;\n}\n\n/**\n * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp\n * @q_vector: Pointer to interrupt specific structure\n * @va: Pointer to address containing Rx buffer\n * @skb: Buffer containing timestamp and packet\n *\n * This function is meant to retrieve a timestamp from the first buffer of an\n * incoming frame. The value is stored in little endian format starting on\n * byte 8.\n */\nvoid igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,\n\t\t\t unsigned char *va,\n\t\t\t struct sk_buff *skb)\n{\n\t__le64 *regval = (__le64 *)va;\n\n\t/*\n\t * The timestamp is recorded in little endian format.\n\t * DWORD: 0 1 2 3\n\t * Field: Reserved Reserved SYSTIML SYSTIMH\n\t */\n\tigb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),\n\t\t\t\t le64_to_cpu(regval[1]));\n}\n\n/**\n * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register\n * @q_vector: Pointer to interrupt specific structure\n * @skb: Buffer containing timestamp and packet\n *\n * This function is meant to retrieve a timestamp from the internal registers\n * of the adapter and store it in the skb.\n */\nvoid igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,\n\t\t\t struct sk_buff *skb)\n{\n\tstruct igb_adapter *adapter = q_vector->adapter;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu64 regval;\n\n\t/*\n\t * If this bit is set, then the RX registers contain the time stamp. No\n\t * other packet will be time stamped until we read these registers, so\n\t * read the registers to make them available again. Because only one\n\t * packet can be time stamped at a time, we know that the register\n\t * values must belong to this one here and therefore we don't need to\n\t * compare any of the additional attributes stored for it.\n\t *\n\t * If nothing went wrong, then it should have a shared tx_flags that we\n\t * can turn into a skb_shared_hwtstamps.\n\t */\n\tif (!(E1000_READ_REG(hw, E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))\n\t\treturn;\n\n\tregval = E1000_READ_REG(hw, E1000_RXSTMPL);\n\tregval |= (u64)E1000_READ_REG(hw, E1000_RXSTMPH) << 32;\n\n\tigb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);\n}\n\n/**\n * igb_ptp_hwtstamp_ioctl - control hardware time stamping\n * @netdev:\n * @ifreq:\n * @cmd:\n *\n * Outgoing time stamping can be enabled and disabled. Play nice and\n * disable it when requested, although it shouldn't case any overhead\n * when no packet needs it. At most one packet in the queue may be\n * marked for time stamping, otherwise it would be impossible to tell\n * for sure to which packet the hardware time stamp belongs.\n *\n * Incoming time stamping has to be configured via the hardware\n * filters. Not all combinations are supported, in particular event\n * type has to be specified. Matching the kind of event packet is\n * not supported, with the exception of \"all V2 events regardless of\n * level 2 or 4\".\n *\n **/\nint igb_ptp_hwtstamp_ioctl(struct net_device *netdev,\n\t\t\t struct ifreq *ifr, int cmd)\n{\n\tstruct igb_adapter *adapter = netdev_priv(netdev);\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct hwtstamp_config config;\n\tu32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;\n\tu32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;\n\tu32 tsync_rx_cfg = 0;\n\tbool is_l4 = false;\n\tbool is_l2 = false;\n\tu32 regval;\n\n\tif (copy_from_user(&config, ifr->ifr_data, sizeof(config)))\n\t\treturn -EFAULT;\n\n\t/* reserved for future extensions */\n\tif (config.flags)\n\t\treturn -EINVAL;\n\n\tswitch (config.tx_type) {\n\tcase HWTSTAMP_TX_OFF:\n\t\ttsync_tx_ctl = 0;\n\tcase HWTSTAMP_TX_ON:\n\t\tbreak;\n\tdefault:\n\t\treturn -ERANGE;\n\t}\n\n\tswitch (config.rx_filter) {\n\tcase HWTSTAMP_FILTER_NONE:\n\t\ttsync_rx_ctl = 0;\n\t\tbreak;\n\tcase HWTSTAMP_FILTER_PTP_V1_L4_SYNC:\n\t\ttsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;\n\t\ttsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;\n\t\tis_l4 = true;\n\t\tbreak;\n\tcase HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:\n\t\ttsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;\n\t\ttsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;\n\t\tis_l4 = true;\n\t\tbreak;\n\tcase HWTSTAMP_FILTER_PTP_V2_EVENT:\n\tcase HWTSTAMP_FILTER_PTP_V2_L2_EVENT:\n\tcase HWTSTAMP_FILTER_PTP_V2_L4_EVENT:\n\tcase HWTSTAMP_FILTER_PTP_V2_SYNC:\n\tcase HWTSTAMP_FILTER_PTP_V2_L2_SYNC:\n\tcase HWTSTAMP_FILTER_PTP_V2_L4_SYNC:\n\tcase HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:\n\tcase HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:\n\tcase HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:\n\t\ttsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;\n\t\tconfig.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;\n\t\tis_l2 = true;\n\t\tis_l4 = true;\n\t\tbreak;\n\tcase HWTSTAMP_FILTER_PTP_V1_L4_EVENT:\n\tcase HWTSTAMP_FILTER_ALL:\n\t\t/*\n\t\t * 82576 cannot timestamp all packets, which it needs to do to\n\t\t * support both V1 Sync and Delay_Req messages\n\t\t */\n\t\tif (hw->mac.type != e1000_82576) {\n\t\t\ttsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;\n\t\t\tconfig.rx_filter = HWTSTAMP_FILTER_ALL;\n\t\t\tbreak;\n\t\t}\n\t\t/* fall through */\n\tdefault:\n\t\tconfig.rx_filter = HWTSTAMP_FILTER_NONE;\n\t\treturn -ERANGE;\n\t}\n\n\tif (hw->mac.type == e1000_82575) {\n\t\tif (tsync_rx_ctl | tsync_tx_ctl)\n\t\t\treturn -EINVAL;\n\t\treturn 0;\n\t}\n\n\t/*\n\t * Per-packet timestamping only works if all packets are\n\t * timestamped, so enable timestamping in all packets as\n\t * long as one rx filter was configured.\n\t */\n\tif ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {\n\t\ttsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;\n\t\ttsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;\n\t\tconfig.rx_filter = HWTSTAMP_FILTER_ALL;\n\t\tis_l2 = true;\n\t\tis_l4 = true;\n\n\t\tif ((hw->mac.type == e1000_i210) ||\n\t\t (hw->mac.type == e1000_i211)) {\n\t\t\tregval = E1000_READ_REG(hw, E1000_RXPBS);\n\t\t\tregval |= E1000_RXPBS_CFG_TS_EN;\n\t\t\tE1000_WRITE_REG(hw, E1000_RXPBS, regval);\n\t\t}\n\t}\n\n\t/* enable/disable TX */\n\tregval = E1000_READ_REG(hw, E1000_TSYNCTXCTL);\n\tregval &= ~E1000_TSYNCTXCTL_ENABLED;\n\tregval |= tsync_tx_ctl;\n\tE1000_WRITE_REG(hw, E1000_TSYNCTXCTL, regval);\n\n\t/* enable/disable RX */\n\tregval = E1000_READ_REG(hw, E1000_TSYNCRXCTL);\n\tregval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);\n\tregval |= tsync_rx_ctl;\n\tE1000_WRITE_REG(hw, E1000_TSYNCRXCTL, regval);\n\n\t/* define which PTP packets are time stamped */\n\tE1000_WRITE_REG(hw, E1000_TSYNCRXCFG, tsync_rx_cfg);\n\n\t/* define ethertype filter for timestamped packets */\n\tif (is_l2)\n\t\tE1000_WRITE_REG(hw, E1000_ETQF(3),\n\t\t (E1000_ETQF_FILTER_ENABLE | /* enable filter */\n\t\t E1000_ETQF_1588 | /* enable timestamping */\n\t\t ETH_P_1588)); /* 1588 eth protocol type */\n\telse\n\t\tE1000_WRITE_REG(hw, E1000_ETQF(3), 0);\n\n\t/* L4 Queue Filter[3]: filter by destination port and protocol */\n\tif (is_l4) {\n\t\tu32 ftqf = (IPPROTO_UDP /* UDP */\n\t\t\t| E1000_FTQF_VF_BP /* VF not compared */\n\t\t\t| E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */\n\t\t\t| E1000_FTQF_MASK); /* mask all inputs */\n\t\tftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */\n\n\t\tE1000_WRITE_REG(hw, E1000_IMIR(3), htons(PTP_EV_PORT));\n\t\tE1000_WRITE_REG(hw, E1000_IMIREXT(3),\n\t\t (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));\n\t\tif (hw->mac.type == e1000_82576) {\n\t\t\t/* enable source port check */\n\t\t\tE1000_WRITE_REG(hw, E1000_SPQF(3), htons(PTP_EV_PORT));\n\t\t\tftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;\n\t\t}\n\t\tE1000_WRITE_REG(hw, E1000_FTQF(3), ftqf);\n\t} else {\n\t\tE1000_WRITE_REG(hw, E1000_FTQF(3), E1000_FTQF_MASK);\n\t}\n\tE1000_WRITE_FLUSH(hw);\n\n\t/* clear TX/RX time stamp registers, just to be sure */\n\tregval = E1000_READ_REG(hw, E1000_TXSTMPL);\n\tregval = E1000_READ_REG(hw, E1000_TXSTMPH);\n\tregval = E1000_READ_REG(hw, E1000_RXSTMPL);\n\tregval = E1000_READ_REG(hw, E1000_RXSTMPH);\n\n\treturn copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?\n\t\t-EFAULT : 0;\n}\n\nvoid igb_ptp_init(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\tstruct net_device *netdev = adapter->netdev;\n\n\tswitch (hw->mac.type) {\n\tcase e1000_82576:\n\t\tsnprintf(adapter->ptp_caps.name, 16, \"%pm\", netdev->dev_addr);\n\t\tadapter->ptp_caps.owner = THIS_MODULE;\n\t\tadapter->ptp_caps.max_adj = 999999881;\n\t\tadapter->ptp_caps.n_ext_ts = 0;\n\t\tadapter->ptp_caps.pps = 0;\n\t\tadapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;\n\t\tadapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;\n\t\tadapter->ptp_caps.gettime = igb_ptp_gettime_82576;\n\t\tadapter->ptp_caps.settime = igb_ptp_settime_82576;\n\t\tadapter->ptp_caps.enable = igb_ptp_enable;\n\t\tadapter->cc.read = igb_ptp_read_82576;\n\t\tadapter->cc.mask = CLOCKSOURCE_MASK(64);\n\t\tadapter->cc.mult = 1;\n\t\tadapter->cc.shift = IGB_82576_TSYNC_SHIFT;\n\t\t/* Dial the nominal frequency. */\n\t\tE1000_WRITE_REG(hw, E1000_TIMINCA, INCPERIOD_82576 |\n\t\t\t\t\t\t INCVALUE_82576);\n\t\tbreak;\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\tsnprintf(adapter->ptp_caps.name, 16, \"%pm\", netdev->dev_addr);\n\t\tadapter->ptp_caps.owner = THIS_MODULE;\n\t\tadapter->ptp_caps.max_adj = 62499999;\n\t\tadapter->ptp_caps.n_ext_ts = 0;\n\t\tadapter->ptp_caps.pps = 0;\n\t\tadapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;\n\t\tadapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;\n\t\tadapter->ptp_caps.gettime = igb_ptp_gettime_82576;\n\t\tadapter->ptp_caps.settime = igb_ptp_settime_82576;\n\t\tadapter->ptp_caps.enable = igb_ptp_enable;\n\t\tadapter->cc.read = igb_ptp_read_82580;\n\t\tadapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580);\n\t\tadapter->cc.mult = 1;\n\t\tadapter->cc.shift = 0;\n\t\t/* Enable the timer functions by clearing bit 31. */\n\t\tE1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);\n\t\tbreak;\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\tsnprintf(adapter->ptp_caps.name, 16, \"%pm\", netdev->dev_addr);\n\t\tadapter->ptp_caps.owner = THIS_MODULE;\n\t\tadapter->ptp_caps.max_adj = 62499999;\n\t\tadapter->ptp_caps.n_ext_ts = 0;\n\t\tadapter->ptp_caps.pps = 0;\n\t\tadapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;\n\t\tadapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;\n\t\tadapter->ptp_caps.gettime = igb_ptp_gettime_i210;\n\t\tadapter->ptp_caps.settime = igb_ptp_settime_i210;\n\t\tadapter->ptp_caps.enable = igb_ptp_enable;\n\t\t/* Enable the timer functions by clearing bit 31. */\n\t\tE1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);\n\t\tbreak;\n\tdefault:\n\t\tadapter->ptp_clock = NULL;\n\t\treturn;\n\t}\n\n\tE1000_WRITE_FLUSH(hw);\n\n\tspin_lock_init(&adapter->tmreg_lock);\n\tINIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);\n\n\t/* Initialize the clock and overflow work for devices that need it. */\n\tif ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {\n\t\tstruct timespec ts = ktime_to_timespec(ktime_get_real());\n\n\t\tigb_ptp_settime_i210(&adapter->ptp_caps, &ts);\n\t} else {\n\t\ttimecounter_init(&adapter->tc, &adapter->cc,\n\t\t\t\t ktime_to_ns(ktime_get_real()));\n\n\t\tINIT_DELAYED_WORK(&adapter->ptp_overflow_work,\n\t\t\t\t igb_ptp_overflow_check);\n\n\t\tschedule_delayed_work(&adapter->ptp_overflow_work,\n\t\t\t\t IGB_SYSTIM_OVERFLOW_PERIOD);\n\t}\n\n\t/* Initialize the time sync interrupts for devices that support it. */\n\tif (hw->mac.type >= e1000_82580) {\n\t\tE1000_WRITE_REG(hw, E1000_TSIM, E1000_TSIM_TXTS);\n\t\tE1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_TS);\n\t}\n\n\tadapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,\n\t\t\t\t\t\t&adapter->pdev->dev);\n\tif (IS_ERR(adapter->ptp_clock)) {\n\t\tadapter->ptp_clock = NULL;\n\t\tdev_err(&adapter->pdev->dev, \"ptp_clock_register failed\\n\");\n\t} else {\n\t\tdev_info(&adapter->pdev->dev, \"added PHC on %s\\n\",\n\t\t\t adapter->netdev->name);\n\t\tadapter->flags |= IGB_FLAG_PTP;\n\t}\n}\n\n/**\n * igb_ptp_stop - Disable PTP device and stop the overflow check.\n * @adapter: Board private structure.\n *\n * This function stops the PTP support and cancels the delayed work.\n **/\nvoid igb_ptp_stop(struct igb_adapter *adapter)\n{\n\tswitch (adapter->hw.mac.type) {\n\tcase e1000_82576:\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\t\tcancel_delayed_work_sync(&adapter->ptp_overflow_work);\n\t\tbreak;\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\t/* No delayed work to cancel. */\n\t\tbreak;\n\tdefault:\n\t\treturn;\n\t}\n\n\tcancel_work_sync(&adapter->ptp_tx_work);\n\tif (adapter->ptp_tx_skb) {\n\t\tdev_kfree_skb_any(adapter->ptp_tx_skb);\n\t\tadapter->ptp_tx_skb = NULL;\n\t}\n\n\tif (adapter->ptp_clock) {\n\t\tptp_clock_unregister(adapter->ptp_clock);\n\t\tdev_info(&adapter->pdev->dev, \"removed PHC on %s\\n\",\n\t\t\t adapter->netdev->name);\n\t\tadapter->flags &= ~IGB_FLAG_PTP;\n\t}\n}\n\n/**\n * igb_ptp_reset - Re-enable the adapter for PTP following a reset.\n * @adapter: Board private structure.\n *\n * This function handles the reset work required to re-enable the PTP device.\n **/\nvoid igb_ptp_reset(struct igb_adapter *adapter)\n{\n\tstruct e1000_hw *hw = &adapter->hw;\n\n\tif (!(adapter->flags & IGB_FLAG_PTP))\n\t\treturn;\n\n\tswitch (adapter->hw.mac.type) {\n\tcase e1000_82576:\n\t\t/* Dial the nominal frequency. */\n\t\tE1000_WRITE_REG(hw, E1000_TIMINCA, INCPERIOD_82576 |\n\t\t\t\t\t\t INCVALUE_82576);\n\t\tbreak;\n\tcase e1000_82580:\n\tcase e1000_i350:\n\tcase e1000_i354:\n\tcase e1000_i210:\n\tcase e1000_i211:\n\t\t/* Enable the timer functions and interrupts. */\n\t\tE1000_WRITE_REG(hw, E1000_TSAUXC, 0x0);\n\t\tE1000_WRITE_REG(hw, E1000_TSIM, E1000_TSIM_TXTS);\n\t\tE1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_TS);\n\t\tbreak;\n\tdefault:\n\t\t/* No work to do. */\n\t\treturn;\n\t}\n\n\t/* Re-initialize the timer. */\n\tif ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {\n\t\tstruct timespec ts = ktime_to_timespec(ktime_get_real());\n\n\t\tigb_ptp_settime_i210(&adapter->ptp_caps, &ts);\n\t} else {\n\t\ttimecounter_init(&adapter->tc, &adapter->cc,\n\t\t\t\t ktime_to_ns(ktime_get_real()));\n\t}\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/igb_regtest.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n/* ethtool register test data */\nstruct igb_reg_test {\n\tu16 reg;\n\tu16 reg_offset;\n\tu16 array_len;\n\tu16 test_type;\n\tu32 mask;\n\tu32 write;\n};\n\n/* In the hardware, registers are laid out either singly, in arrays\n * spaced 0x100 bytes apart, or in contiguous tables. We assume\n * most tests take place on arrays or single registers (handled\n * as a single-element array) and special-case the tables.\n * Table tests are always pattern tests.\n *\n * We also make provision for some required setup steps by specifying\n * registers to be written without any read-back testing.\n */\n\n#define PATTERN_TEST\t1\n#define SET_READ_TEST\t2\n#define WRITE_NO_TEST\t3\n#define TABLE32_TEST\t4\n#define TABLE64_TEST_LO\t5\n#define TABLE64_TEST_HI\t6\n\n/* i210 reg test */\nstatic struct igb_reg_test reg_test_i210[] = {\n\t{ E1000_FCAL,\t 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_FCAH,\t 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },\n\t{ E1000_FCT,\t 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },\n\t{ E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },\n\t/* RDH is read-only for i210, only test RDT. */\n\t{ E1000_RDT(0),\t 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_FCRTH,\t 0x100, 1, PATTERN_TEST, 0x0003FFF0, 0x0003FFF0 },\n\t{ E1000_FCTTV,\t 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_TIPG,\t 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },\n\t{ E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },\n\t{ E1000_TDT(0),\t 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_RCTL,\t 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },\n\t{ E1000_RCTL, \t 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },\n\t{ E1000_RCTL, \t 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },\n\t{ E1000_TCTL,\t 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },\n\t{ E1000_RA,\t 0, 16, TABLE64_TEST_LO,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RA,\t 0, 16, TABLE64_TEST_HI,\n\t\t\t\t\t\t0x900FFFFF, 0xFFFFFFFF },\n\t{ E1000_MTA,\t 0, 128, TABLE32_TEST,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ 0, 0, 0, 0 }\n};\n\n/* i350 reg test */\nstatic struct igb_reg_test reg_test_i350[] = {\n\t{ E1000_FCAL,\t 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_FCAH,\t 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },\n\t{ E1000_FCT,\t 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },\n\t/* VET is readonly on i350 */\n\t{ E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },\n\t{ E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },\n\t/* RDH is read-only for i350, only test RDT. */\n\t{ E1000_RDT(0),\t 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_RDT(4),\t 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_FCRTH,\t 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },\n\t{ E1000_FCTTV,\t 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_TIPG,\t 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },\n\t{ E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },\n\t{ E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },\n\t{ E1000_TDT(0),\t 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_TDT(4),\t 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_RCTL,\t 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },\n\t{ E1000_RCTL, \t 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },\n\t{ E1000_RCTL, \t 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },\n\t{ E1000_TCTL,\t 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },\n\t{ E1000_RA,\t 0, 16, TABLE64_TEST_LO,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RA,\t 0, 16, TABLE64_TEST_HI,\n\t\t\t\t\t\t0xC3FFFFFF, 0xFFFFFFFF },\n\t{ E1000_RA2,\t 0, 16, TABLE64_TEST_LO,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RA2,\t 0, 16, TABLE64_TEST_HI,\n\t\t\t\t\t\t0xC3FFFFFF, 0xFFFFFFFF },\n\t{ E1000_MTA,\t 0, 128, TABLE32_TEST,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ 0, 0, 0, 0 }\n};\n\n/* 82580 reg test */\nstatic struct igb_reg_test reg_test_82580[] = {\n\t{ E1000_FCAL,\t 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_FCAH,\t 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },\n\t{ E1000_FCT,\t 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },\n\t{ E1000_VET,\t 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },\n\t{ E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },\n\t/* RDH is read-only for 82580, only test RDT. */\n\t{ E1000_RDT(0),\t 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_RDT(4),\t 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_FCRTH,\t 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },\n\t{ E1000_FCTTV,\t 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_TIPG,\t 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },\n\t{ E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },\n\t{ E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },\n\t{ E1000_TDT(0),\t 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_TDT(4),\t 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_RCTL,\t 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },\n\t{ E1000_RCTL, \t 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },\n\t{ E1000_RCTL, \t 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },\n\t{ E1000_TCTL,\t 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },\n\t{ E1000_RA,\t 0, 16, TABLE64_TEST_LO,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RA,\t 0, 16, TABLE64_TEST_HI,\n\t\t\t\t\t\t0x83FFFFFF, 0xFFFFFFFF },\n\t{ E1000_RA2,\t 0, 8, TABLE64_TEST_LO,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RA2,\t 0, 8, TABLE64_TEST_HI,\n\t\t\t\t\t\t0x83FFFFFF, 0xFFFFFFFF },\n\t{ E1000_MTA,\t 0, 128, TABLE32_TEST,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ 0, 0, 0, 0 }\n};\n\n/* 82576 reg test */\nstatic struct igb_reg_test reg_test_82576[] = {\n\t{ E1000_FCAL,\t 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_FCAH,\t 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },\n\t{ E1000_FCT,\t 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },\n\t{ E1000_VET,\t 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },\n\t{ E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },\n\t/* Enable all queues before testing. */\n\t{ E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },\n\t{ E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },\n\t/* RDH is read-only for 82576, only test RDT. */\n\t{ E1000_RDT(0),\t 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_RDT(4),\t 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },\n\t{ E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },\n\t{ E1000_FCRTH,\t 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },\n\t{ E1000_FCTTV,\t 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_TIPG,\t 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },\n\t{ E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },\n\t{ E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },\n\t{ E1000_RCTL,\t 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },\n\t{ E1000_RCTL, \t 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },\n\t{ E1000_RCTL, \t 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },\n\t{ E1000_TCTL,\t 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },\n\t{ E1000_RA,\t 0, 16, TABLE64_TEST_LO,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RA,\t 0, 16, TABLE64_TEST_HI,\n\t\t\t\t\t\t0x83FFFFFF, 0xFFFFFFFF },\n\t{ E1000_RA2,\t 0, 8, TABLE64_TEST_LO,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RA2,\t 0, 8, TABLE64_TEST_HI,\n\t\t\t\t\t\t0x83FFFFFF, 0xFFFFFFFF },\n\t{ E1000_MTA,\t 0, 128, TABLE32_TEST,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ 0, 0, 0, 0 }\n};\n\n/* 82575 register test */\nstatic struct igb_reg_test reg_test_82575[] = {\n\t{ E1000_FCAL,\t0x100,\t1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_FCAH,\t0x100,\t1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },\n\t{ E1000_FCT,\t0x100,\t1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },\n\t{ E1000_VET,\t0x100,\t1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RDBAL(0),\t0x100,\t4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_RDBAH(0),\t0x100,\t4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RDLEN(0),\t0x100,\t4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },\n\t/* Enable all four RX queues before testing. */\n\t{ E1000_RXDCTL(0),\t0x100,\t4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },\n\t/* RDH is read-only for 82575, only test RDT. */\n\t{ E1000_RDT(0),\t0x100,\t4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_RXDCTL(0),\t0x100,\t4, WRITE_NO_TEST, 0, 0 },\n\t{ E1000_FCRTH,\t0x100,\t1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },\n\t{ E1000_FCTTV,\t0x100,\t1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ E1000_TIPG,\t0x100,\t1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },\n\t{ E1000_TDBAL(0),\t0x100,\t4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ E1000_TDBAH(0),\t0x100,\t4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_TDLEN(0),\t0x100,\t4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },\n\t{ E1000_RCTL,\t0x100,\t1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },\n\t{ E1000_RCTL, \t0x100,\t1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },\n\t{ E1000_RCTL, \t0x100,\t1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },\n\t{ E1000_TCTL,\t0x100,\t1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },\n\t{ E1000_TXCW,\t0x100,\t1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },\n\t{ E1000_RA,\t0,\t16, TABLE64_TEST_LO,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ E1000_RA,\t0,\t16, TABLE64_TEST_HI,\n\t\t\t\t\t\t0x800FFFFF, 0xFFFFFFFF },\n\t{ E1000_MTA,\t0,\t128, TABLE32_TEST,\n\t\t\t\t\t\t0xFFFFFFFF, 0xFFFFFFFF },\n\t{ 0, 0, 0, 0 }\n};\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/igb_vmdq.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n\n#include \n\n#include \"igb.h\"\n#include \"igb_vmdq.h\"\n#include \n\n#ifdef CONFIG_IGB_VMDQ_NETDEV\nint igb_vmdq_open(struct net_device *dev)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(dev);\n\tstruct igb_adapter *adapter = vadapter->real_adapter;\n\tstruct net_device *main_netdev = adapter->netdev;\n\tint hw_queue = vadapter->rx_ring->queue_index +\n\t\t adapter->vfs_allocated_count;\n\n\tif (test_bit(__IGB_DOWN, &adapter->state)) {\n\t\tDPRINTK(DRV, WARNING,\n\t\t\t\"Open %s before opening this device.\\n\",\n\t\t\tmain_netdev->name);\n\t\treturn -EAGAIN;\n\t}\n\tnetif_carrier_off(dev);\n\tvadapter->tx_ring->vmdq_netdev = dev;\n\tvadapter->rx_ring->vmdq_netdev = dev;\n\tif (is_valid_ether_addr(dev->dev_addr)) {\n\t\tigb_del_mac_filter(adapter, dev->dev_addr, hw_queue);\n\t\tigb_add_mac_filter(adapter, dev->dev_addr, hw_queue);\n\t}\n\tnetif_carrier_on(dev);\n\treturn 0;\n}\n\nint igb_vmdq_close(struct net_device *dev)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(dev);\n\tstruct igb_adapter *adapter = vadapter->real_adapter;\n\tint hw_queue = vadapter->rx_ring->queue_index +\n\t\t adapter->vfs_allocated_count;\n\n\tnetif_carrier_off(dev);\n\tigb_del_mac_filter(adapter, dev->dev_addr, hw_queue);\n\n\tvadapter->tx_ring->vmdq_netdev = NULL;\n\tvadapter->rx_ring->vmdq_netdev = NULL;\n\treturn 0;\n}\n\nnetdev_tx_t igb_vmdq_xmit_frame(struct sk_buff *skb, struct net_device *dev)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(dev);\n\n\treturn igb_xmit_frame_ring(skb, vadapter->tx_ring);\n}\n\nstruct net_device_stats *igb_vmdq_get_stats(struct net_device *dev)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(dev);\n struct igb_adapter *adapter = vadapter->real_adapter;\n struct e1000_hw *hw = &adapter->hw;\n\tint hw_queue = vadapter->rx_ring->queue_index +\n\t\t adapter->vfs_allocated_count;\n\n\tvadapter->net_stats.rx_packets +=\n\t\t\tE1000_READ_REG(hw, E1000_PFVFGPRC(hw_queue));\n\tE1000_WRITE_REG(hw, E1000_PFVFGPRC(hw_queue), 0);\n vadapter->net_stats.tx_packets +=\n\t\t\tE1000_READ_REG(hw, E1000_PFVFGPTC(hw_queue));\n E1000_WRITE_REG(hw, E1000_PFVFGPTC(hw_queue), 0);\n vadapter->net_stats.rx_bytes +=\n\t\t\tE1000_READ_REG(hw, E1000_PFVFGORC(hw_queue));\n E1000_WRITE_REG(hw, E1000_PFVFGORC(hw_queue), 0);\n vadapter->net_stats.tx_bytes +=\n\t\t\tE1000_READ_REG(hw, E1000_PFVFGOTC(hw_queue));\n E1000_WRITE_REG(hw, E1000_PFVFGOTC(hw_queue), 0);\n vadapter->net_stats.multicast +=\n\t\t\tE1000_READ_REG(hw, E1000_PFVFMPRC(hw_queue));\n E1000_WRITE_REG(hw, E1000_PFVFMPRC(hw_queue), 0);\n\t/* only return the current stats */\n\treturn &vadapter->net_stats;\n}\n\n/**\n * igb_write_vm_addr_list - write unicast addresses to RAR table\n * @netdev: network interface device structure\n *\n * Writes unicast address list to the RAR table.\n * Returns: -ENOMEM on failure/insufficient address space\n * 0 on no addresses written\n * X on writing X addresses to the RAR table\n **/\nstatic int igb_write_vm_addr_list(struct net_device *netdev)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(netdev);\n struct igb_adapter *adapter = vadapter->real_adapter;\n\tint count = 0;\n\tint hw_queue = vadapter->rx_ring->queue_index +\n\t\t adapter->vfs_allocated_count;\n\n\t/* return ENOMEM indicating insufficient memory for addresses */\n\tif (netdev_uc_count(netdev) > igb_available_rars(adapter))\n\t\treturn -ENOMEM;\n\n\tif (!netdev_uc_empty(netdev)) {\n#ifdef NETDEV_HW_ADDR_T_UNICAST\n\t\tstruct netdev_hw_addr *ha;\n#else\n\t\tstruct dev_mc_list *ha;\n#endif\n\t\tnetdev_for_each_uc_addr(ha, netdev) {\n#ifdef NETDEV_HW_ADDR_T_UNICAST\n\t\t\tigb_del_mac_filter(adapter, ha->addr, hw_queue);\n\t\t\tigb_add_mac_filter(adapter, ha->addr, hw_queue);\n#else\n\t\t\tigb_del_mac_filter(adapter, ha->da_addr, hw_queue);\n\t\t\tigb_add_mac_filter(adapter, ha->da_addr, hw_queue);\n#endif\n\t\t\tcount++;\n\t\t}\n\t}\n\treturn count;\n}\n\n\n#define E1000_VMOLR_UPE\t\t0x20000000 /* Unicast promiscuous mode */\nvoid igb_vmdq_set_rx_mode(struct net_device *dev)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(dev);\n struct igb_adapter *adapter = vadapter->real_adapter;\n struct e1000_hw *hw = &adapter->hw;\n\tu32 vmolr, rctl;\n\tint hw_queue = vadapter->rx_ring->queue_index +\n\t\t adapter->vfs_allocated_count;\n\n\t/* Check for Promiscuous and All Multicast modes */\n\tvmolr = E1000_READ_REG(hw, E1000_VMOLR(hw_queue));\n\n\t/* clear the affected bits */\n\tvmolr &= ~(E1000_VMOLR_UPE | E1000_VMOLR_MPME |\n\t\t E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE);\n\n\tif (dev->flags & IFF_PROMISC) {\n\t\tvmolr |= E1000_VMOLR_UPE;\n\t\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\t\trctl |= E1000_RCTL_UPE;\n\t\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\t} else {\n\t\trctl = E1000_READ_REG(hw, E1000_RCTL);\n\t\trctl &= ~E1000_RCTL_UPE;\n\t\tE1000_WRITE_REG(hw, E1000_RCTL, rctl);\n\t\tif (dev->flags & IFF_ALLMULTI) {\n\t\t\tvmolr |= E1000_VMOLR_MPME;\n\t\t} else {\n\t\t\t/*\n\t\t\t * Write addresses to the MTA, if the attempt fails\n\t\t\t * then we should just turn on promiscuous mode so\n\t\t\t * that we can at least receive multicast traffic\n\t\t\t */\n\t\t\tif (igb_write_mc_addr_list(adapter->netdev) != 0)\n\t\t\t\tvmolr |= E1000_VMOLR_ROMPE;\n\t\t}\n#ifdef HAVE_SET_RX_MODE\n\t\t/*\n\t\t * Write addresses to available RAR registers, if there is not\n\t\t * sufficient space to store all the addresses then enable\n\t\t * unicast promiscuous mode\n\t\t */\n\t\tif (igb_write_vm_addr_list(dev) < 0)\n\t\t\tvmolr |= E1000_VMOLR_UPE;\n#endif\n\t}\n\tE1000_WRITE_REG(hw, E1000_VMOLR(hw_queue), vmolr);\n\n\treturn;\n}\n\nint igb_vmdq_set_mac(struct net_device *dev, void *p)\n{\n\tstruct sockaddr *addr = p;\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(dev);\n struct igb_adapter *adapter = vadapter->real_adapter;\n\tint hw_queue = vadapter->rx_ring->queue_index +\n\t\t adapter->vfs_allocated_count;\n\n\tigb_del_mac_filter(adapter, dev->dev_addr, hw_queue);\n\tmemcpy(dev->dev_addr, addr->sa_data, dev->addr_len);\n\treturn igb_add_mac_filter(adapter, dev->dev_addr, hw_queue);\n}\n\nint igb_vmdq_change_mtu(struct net_device *dev, int new_mtu)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(dev);\n\tstruct igb_adapter *adapter = vadapter->real_adapter;\n\n\tif (adapter->netdev->mtu < new_mtu) {\n\t\tDPRINTK(PROBE, INFO,\n\t\t\t\"Set MTU on %s to >= %d \"\n\t\t\t\"before changing MTU on %s\\n\",\n\t\t\tadapter->netdev->name, new_mtu, dev->name);\n\t\treturn -EINVAL;\n\t}\n\tdev->mtu = new_mtu;\n\treturn 0;\n}\n\nvoid igb_vmdq_tx_timeout(struct net_device *dev)\n{\n\treturn;\n}\n\nvoid igb_vmdq_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(dev);\n\tstruct igb_adapter *adapter = vadapter->real_adapter;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tint hw_queue = vadapter->rx_ring->queue_index +\n\t\t adapter->vfs_allocated_count;\n\n\tvadapter->vlgrp = grp;\n\n\tigb_enable_vlan_tags(adapter);\n\tE1000_WRITE_REG(hw, E1000_VMVIR(hw_queue), 0);\n\n\treturn;\n}\nvoid igb_vmdq_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(dev);\n\tstruct igb_adapter *adapter = vadapter->real_adapter;\n#ifndef HAVE_NETDEV_VLAN_FEATURES\n\tstruct net_device *v_netdev;\n#endif\n\tint hw_queue = vadapter->rx_ring->queue_index +\n\t\t adapter->vfs_allocated_count;\n\n\t/* attempt to add filter to vlvf array */\n\tigb_vlvf_set(adapter, vid, TRUE, hw_queue);\n\n#ifndef HAVE_NETDEV_VLAN_FEATURES\n\n\t/* Copy feature flags from netdev to the vlan netdev for this vid.\n\t * This allows things like TSO to bubble down to our vlan device.\n\t */\n\tv_netdev = vlan_group_get_device(vadapter->vlgrp, vid);\n\tv_netdev->features |= adapter->netdev->features;\n\tvlan_group_set_device(vadapter->vlgrp, vid, v_netdev);\n#endif\n\n\treturn;\n}\nvoid igb_vmdq_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(dev);\n\tstruct igb_adapter *adapter = vadapter->real_adapter;\n\tint hw_queue = vadapter->rx_ring->queue_index +\n\t\t adapter->vfs_allocated_count;\n\n\tvlan_group_set_device(vadapter->vlgrp, vid, NULL);\n\t/* remove vlan from VLVF table array */\n\tigb_vlvf_set(adapter, vid, FALSE, hw_queue);\n\n\n\treturn;\n}\n\nstatic int igb_vmdq_get_settings(struct net_device *netdev,\n\t\t\t\t struct ethtool_cmd *ecmd)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(netdev);\n\tstruct igb_adapter *adapter = vadapter->real_adapter;\n\tstruct e1000_hw *hw = &adapter->hw;\n\tu32 status;\n\n\tif (hw->phy.media_type == e1000_media_type_copper) {\n\n\t\tecmd->supported = (SUPPORTED_10baseT_Half |\n\t\t\t\t SUPPORTED_10baseT_Full |\n\t\t\t\t SUPPORTED_100baseT_Half |\n\t\t\t\t SUPPORTED_100baseT_Full |\n\t\t\t\t SUPPORTED_1000baseT_Full|\n\t\t\t\t SUPPORTED_Autoneg |\n\t\t\t\t SUPPORTED_TP);\n\t\tecmd->advertising = ADVERTISED_TP;\n\n\t\tif (hw->mac.autoneg == 1) {\n\t\t\tecmd->advertising |= ADVERTISED_Autoneg;\n\t\t\t/* the e1000 autoneg seems to match ethtool nicely */\n\t\t\tecmd->advertising |= hw->phy.autoneg_advertised;\n\t\t}\n\n\t\tecmd->port = PORT_TP;\n\t\tecmd->phy_address = hw->phy.addr;\n\t} else {\n\t\tecmd->supported = (SUPPORTED_1000baseT_Full |\n\t\t\t\t SUPPORTED_FIBRE |\n\t\t\t\t SUPPORTED_Autoneg);\n\n\t\tecmd->advertising = (ADVERTISED_1000baseT_Full |\n\t\t\t\t ADVERTISED_FIBRE |\n\t\t\t\t ADVERTISED_Autoneg);\n\n\t\tecmd->port = PORT_FIBRE;\n\t}\n\n\tecmd->transceiver = XCVR_INTERNAL;\n\n\tstatus = E1000_READ_REG(hw, E1000_STATUS);\n\n\tif (status & E1000_STATUS_LU) {\n\n\t\tif ((status & E1000_STATUS_SPEED_1000) ||\n\t\t hw->phy.media_type != e1000_media_type_copper)\n\t\t\tecmd->speed = SPEED_1000;\n\t\telse if (status & E1000_STATUS_SPEED_100)\n\t\t\tecmd->speed = SPEED_100;\n\t\telse\n\t\t\tecmd->speed = SPEED_10;\n\n\t\tif ((status & E1000_STATUS_FD) ||\n\t\t hw->phy.media_type != e1000_media_type_copper)\n\t\t\tecmd->duplex = DUPLEX_FULL;\n\t\telse\n\t\t\tecmd->duplex = DUPLEX_HALF;\n\t} else {\n\t\tecmd->speed = -1;\n\t\tecmd->duplex = -1;\n\t}\n\n\tecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;\n\treturn 0;\n}\n\n\nstatic u32 igb_vmdq_get_msglevel(struct net_device *netdev)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(netdev);\n\tstruct igb_adapter *adapter = vadapter->real_adapter;\n\treturn adapter->msg_enable;\n}\n\nstatic void igb_vmdq_get_drvinfo(struct net_device *netdev,\n\t\t\t\t struct ethtool_drvinfo *drvinfo)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(netdev);\n\tstruct igb_adapter *adapter = vadapter->real_adapter;\n\tstruct net_device *main_netdev = adapter->netdev;\n\n\tstrncpy(drvinfo->driver, igb_driver_name, 32);\n\tstrncpy(drvinfo->version, igb_driver_version, 32);\n\n\tstrncpy(drvinfo->fw_version, \"N/A\", 4);\n\tsnprintf(drvinfo->bus_info, 32, \"%s VMDQ %d\", main_netdev->name,\n\t\t vadapter->rx_ring->queue_index);\n\tdrvinfo->n_stats = 0;\n\tdrvinfo->testinfo_len = 0;\n\tdrvinfo->regdump_len = 0;\n}\n\nstatic void igb_vmdq_get_ringparam(struct net_device *netdev,\n\t\t\t\t struct ethtool_ringparam *ring)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(netdev);\n\n\tstruct igb_ring *tx_ring = vadapter->tx_ring;\n\tstruct igb_ring *rx_ring = vadapter->rx_ring;\n\n\tring->rx_max_pending = IGB_MAX_RXD;\n\tring->tx_max_pending = IGB_MAX_TXD;\n\tring->rx_mini_max_pending = 0;\n\tring->rx_jumbo_max_pending = 0;\n\tring->rx_pending = rx_ring->count;\n\tring->tx_pending = tx_ring->count;\n\tring->rx_mini_pending = 0;\n\tring->rx_jumbo_pending = 0;\n}\nstatic u32 igb_vmdq_get_rx_csum(struct net_device *netdev)\n{\n\tstruct igb_vmdq_adapter *vadapter = netdev_priv(netdev);\n\tstruct igb_adapter *adapter = vadapter->real_adapter;\n\n\treturn test_bit(IGB_RING_FLAG_RX_CSUM, &adapter->rx_ring[0]->flags);\n}\n\n\nstatic struct ethtool_ops igb_vmdq_ethtool_ops = {\n\t.get_settings = igb_vmdq_get_settings,\n\t.get_drvinfo = igb_vmdq_get_drvinfo,\n\t.get_link = ethtool_op_get_link,\n\t.get_ringparam = igb_vmdq_get_ringparam,\n\t.get_rx_csum = igb_vmdq_get_rx_csum,\n\t.get_tx_csum = ethtool_op_get_tx_csum,\n\t.get_sg = ethtool_op_get_sg,\n\t.set_sg = ethtool_op_set_sg,\n\t.get_msglevel = igb_vmdq_get_msglevel,\n#ifdef NETIF_F_TSO\n\t.get_tso = ethtool_op_get_tso,\n#endif\n#ifdef HAVE_ETHTOOL_GET_PERM_ADDR\n\t.get_perm_addr = ethtool_op_get_perm_addr,\n#endif\n};\n\nvoid igb_vmdq_set_ethtool_ops(struct net_device *netdev)\n{\n\tSET_ETHTOOL_OPS(netdev, &igb_vmdq_ethtool_ops);\n}\n\n\n#endif /* CONFIG_IGB_VMDQ_NETDEV */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/igb_vmdq.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _IGB_VMDQ_H_\n#define _IGB_VMDQ_H_\n\n#ifdef CONFIG_IGB_VMDQ_NETDEV\nint igb_vmdq_open(struct net_device *dev);\nint igb_vmdq_close(struct net_device *dev);\nnetdev_tx_t igb_vmdq_xmit_frame(struct sk_buff *skb, struct net_device *dev);\nstruct net_device_stats *igb_vmdq_get_stats(struct net_device *dev);\nvoid igb_vmdq_set_rx_mode(struct net_device *dev);\nint igb_vmdq_set_mac(struct net_device *dev, void *addr);\nint igb_vmdq_change_mtu(struct net_device *dev, int new_mtu);\nvoid igb_vmdq_tx_timeout(struct net_device *dev);\nvoid igb_vmdq_vlan_rx_register(struct net_device *dev,\n\t\t\t\t struct vlan_group *grp);\nvoid igb_vmdq_vlan_rx_add_vid(struct net_device *dev, unsigned short vid);\nvoid igb_vmdq_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);\nvoid igb_vmdq_set_ethtool_ops(struct net_device *netdev);\n#endif /* CONFIG_IGB_VMDQ_NETDEV */\n#endif /* _IGB_VMDQ_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/kcompat.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"igb.h\"\n#include \"kcompat.h\"\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,8) )\n/* From lib/vsprintf.c */\n#include \n\nstatic int skip_atoi(const char **s)\n{\n\tint i=0;\n\n\twhile (isdigit(**s))\n\t\ti = i*10 + *((*s)++) - '0';\n\treturn i;\n}\n\n#define _kc_ZEROPAD\t1\t\t/* pad with zero */\n#define _kc_SIGN\t2\t\t/* unsigned/signed long */\n#define _kc_PLUS\t4\t\t/* show plus */\n#define _kc_SPACE\t8\t\t/* space if plus */\n#define _kc_LEFT\t16\t\t/* left justified */\n#define _kc_SPECIAL\t32\t\t/* 0x */\n#define _kc_LARGE\t64\t\t/* use 'ABCDEF' instead of 'abcdef' */\n\nstatic char * number(char * buf, char * end, long long num, int base, int size, int precision, int type)\n{\n\tchar c,sign,tmp[66];\n\tconst char *digits;\n\tconst char small_digits[] = \"0123456789abcdefghijklmnopqrstuvwxyz\";\n\tconst char large_digits[] = \"0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ\";\n\tint i;\n\n\tdigits = (type & _kc_LARGE) ? large_digits : small_digits;\n\tif (type & _kc_LEFT)\n\t\ttype &= ~_kc_ZEROPAD;\n\tif (base < 2 || base > 36)\n\t\treturn 0;\n\tc = (type & _kc_ZEROPAD) ? '0' : ' ';\n\tsign = 0;\n\tif (type & _kc_SIGN) {\n\t\tif (num < 0) {\n\t\t\tsign = '-';\n\t\t\tnum = -num;\n\t\t\tsize--;\n\t\t} else if (type & _kc_PLUS) {\n\t\t\tsign = '+';\n\t\t\tsize--;\n\t\t} else if (type & _kc_SPACE) {\n\t\t\tsign = ' ';\n\t\t\tsize--;\n\t\t}\n\t}\n\tif (type & _kc_SPECIAL) {\n\t\tif (base == 16)\n\t\t\tsize -= 2;\n\t\telse if (base == 8)\n\t\t\tsize--;\n\t}\n\ti = 0;\n\tif (num == 0)\n\t\ttmp[i++]='0';\n\telse while (num != 0)\n\t\ttmp[i++] = digits[do_div(num,base)];\n\tif (i > precision)\n\t\tprecision = i;\n\tsize -= precision;\n\tif (!(type&(_kc_ZEROPAD+_kc_LEFT))) {\n\t\twhile(size-->0) {\n\t\t\tif (buf <= end)\n\t\t\t\t*buf = ' ';\n\t\t\t++buf;\n\t\t}\n\t}\n\tif (sign) {\n\t\tif (buf <= end)\n\t\t\t*buf = sign;\n\t\t++buf;\n\t}\n\tif (type & _kc_SPECIAL) {\n\t\tif (base==8) {\n\t\t\tif (buf <= end)\n\t\t\t\t*buf = '0';\n\t\t\t++buf;\n\t\t} else if (base==16) {\n\t\t\tif (buf <= end)\n\t\t\t\t*buf = '0';\n\t\t\t++buf;\n\t\t\tif (buf <= end)\n\t\t\t\t*buf = digits[33];\n\t\t\t++buf;\n\t\t}\n\t}\n\tif (!(type & _kc_LEFT)) {\n\t\twhile (size-- > 0) {\n\t\t\tif (buf <= end)\n\t\t\t\t*buf = c;\n\t\t\t++buf;\n\t\t}\n\t}\n\twhile (i < precision--) {\n\t\tif (buf <= end)\n\t\t\t*buf = '0';\n\t\t++buf;\n\t}\n\twhile (i-- > 0) {\n\t\tif (buf <= end)\n\t\t\t*buf = tmp[i];\n\t\t++buf;\n\t}\n\twhile (size-- > 0) {\n\t\tif (buf <= end)\n\t\t\t*buf = ' ';\n\t\t++buf;\n\t}\n\treturn buf;\n}\n\nint _kc_vsnprintf(char *buf, size_t size, const char *fmt, va_list args)\n{\n\tint len;\n\tunsigned long long num;\n\tint i, base;\n\tchar *str, *end, c;\n\tconst char *s;\n\n\tint flags;\t\t/* flags to number() */\n\n\tint field_width;\t/* width of output field */\n\tint precision;\t\t/* min. # of digits for integers; max\n\t\t\t\t number of chars for from string */\n\tint qualifier;\t\t/* 'h', 'l', or 'L' for integer fields */\n\t\t\t\t/* 'z' support added 23/7/1999 S.H. */\n\t\t\t\t/* 'z' changed to 'Z' --davidm 1/25/99 */\n\n\tstr = buf;\n\tend = buf + size - 1;\n\n\tif (end < buf - 1) {\n\t\tend = ((void *) -1);\n\t\tsize = end - buf + 1;\n\t}\n\n\tfor (; *fmt ; ++fmt) {\n\t\tif (*fmt != '%') {\n\t\t\tif (str <= end)\n\t\t\t\t*str = *fmt;\n\t\t\t++str;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* process flags */\n\t\tflags = 0;\n\t\trepeat:\n\t\t\t++fmt;\t\t/* this also skips first '%' */\n\t\t\tswitch (*fmt) {\n\t\t\t\tcase '-': flags |= _kc_LEFT; goto repeat;\n\t\t\t\tcase '+': flags |= _kc_PLUS; goto repeat;\n\t\t\t\tcase ' ': flags |= _kc_SPACE; goto repeat;\n\t\t\t\tcase '#': flags |= _kc_SPECIAL; goto repeat;\n\t\t\t\tcase '0': flags |= _kc_ZEROPAD; goto repeat;\n\t\t\t}\n\n\t\t/* get field width */\n\t\tfield_width = -1;\n\t\tif (isdigit(*fmt))\n\t\t\tfield_width = skip_atoi(&fmt);\n\t\telse if (*fmt == '*') {\n\t\t\t++fmt;\n\t\t\t/* it's the next argument */\n\t\t\tfield_width = va_arg(args, int);\n\t\t\tif (field_width < 0) {\n\t\t\t\tfield_width = -field_width;\n\t\t\t\tflags |= _kc_LEFT;\n\t\t\t}\n\t\t}\n\n\t\t/* get the precision */\n\t\tprecision = -1;\n\t\tif (*fmt == '.') {\n\t\t\t++fmt;\n\t\t\tif (isdigit(*fmt))\n\t\t\t\tprecision = skip_atoi(&fmt);\n\t\t\telse if (*fmt == '*') {\n\t\t\t\t++fmt;\n\t\t\t\t/* it's the next argument */\n\t\t\t\tprecision = va_arg(args, int);\n\t\t\t}\n\t\t\tif (precision < 0)\n\t\t\t\tprecision = 0;\n\t\t}\n\n\t\t/* get the conversion qualifier */\n\t\tqualifier = -1;\n\t\tif (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt =='Z') {\n\t\t\tqualifier = *fmt;\n\t\t\t++fmt;\n\t\t}\n\n\t\t/* default base */\n\t\tbase = 10;\n\n\t\tswitch (*fmt) {\n\t\t\tcase 'c':\n\t\t\t\tif (!(flags & _kc_LEFT)) {\n\t\t\t\t\twhile (--field_width > 0) {\n\t\t\t\t\t\tif (str <= end)\n\t\t\t\t\t\t\t*str = ' ';\n\t\t\t\t\t\t++str;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tc = (unsigned char) va_arg(args, int);\n\t\t\t\tif (str <= end)\n\t\t\t\t\t*str = c;\n\t\t\t\t++str;\n\t\t\t\twhile (--field_width > 0) {\n\t\t\t\t\tif (str <= end)\n\t\t\t\t\t\t*str = ' ';\n\t\t\t\t\t++str;\n\t\t\t\t}\n\t\t\t\tcontinue;\n\n\t\t\tcase 's':\n\t\t\t\ts = va_arg(args, char *);\n\t\t\t\tif (!s)\n\t\t\t\t\ts = \"\";\n\n\t\t\t\tlen = strnlen(s, precision);\n\n\t\t\t\tif (!(flags & _kc_LEFT)) {\n\t\t\t\t\twhile (len < field_width--) {\n\t\t\t\t\t\tif (str <= end)\n\t\t\t\t\t\t\t*str = ' ';\n\t\t\t\t\t\t++str;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tfor (i = 0; i < len; ++i) {\n\t\t\t\t\tif (str <= end)\n\t\t\t\t\t\t*str = *s;\n\t\t\t\t\t++str; ++s;\n\t\t\t\t}\n\t\t\t\twhile (len < field_width--) {\n\t\t\t\t\tif (str <= end)\n\t\t\t\t\t\t*str = ' ';\n\t\t\t\t\t++str;\n\t\t\t\t}\n\t\t\t\tcontinue;\n\n\t\t\tcase 'p':\n\t\t\t\tif (field_width == -1) {\n\t\t\t\t\tfield_width = 2*sizeof(void *);\n\t\t\t\t\tflags |= _kc_ZEROPAD;\n\t\t\t\t}\n\t\t\t\tstr = number(str, end,\n\t\t\t\t\t\t(unsigned long) va_arg(args, void *),\n\t\t\t\t\t\t16, field_width, precision, flags);\n\t\t\t\tcontinue;\n\n\n\t\t\tcase 'n':\n\t\t\t\t/* FIXME:\n\t\t\t\t* What does C99 say about the overflow case here? */\n\t\t\t\tif (qualifier == 'l') {\n\t\t\t\t\tlong * ip = va_arg(args, long *);\n\t\t\t\t\t*ip = (str - buf);\n\t\t\t\t} else if (qualifier == 'Z') {\n\t\t\t\t\tsize_t * ip = va_arg(args, size_t *);\n\t\t\t\t\t*ip = (str - buf);\n\t\t\t\t} else {\n\t\t\t\t\tint * ip = va_arg(args, int *);\n\t\t\t\t\t*ip = (str - buf);\n\t\t\t\t}\n\t\t\t\tcontinue;\n\n\t\t\tcase '%':\n\t\t\t\tif (str <= end)\n\t\t\t\t\t*str = '%';\n\t\t\t\t++str;\n\t\t\t\tcontinue;\n\n\t\t\t\t/* integer number formats - set up the flags and \"break\" */\n\t\t\tcase 'o':\n\t\t\t\tbase = 8;\n\t\t\t\tbreak;\n\n\t\t\tcase 'X':\n\t\t\t\tflags |= _kc_LARGE;\n\t\t\tcase 'x':\n\t\t\t\tbase = 16;\n\t\t\t\tbreak;\n\n\t\t\tcase 'd':\n\t\t\tcase 'i':\n\t\t\t\tflags |= _kc_SIGN;\n\t\t\tcase 'u':\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\tif (str <= end)\n\t\t\t\t\t*str = '%';\n\t\t\t\t++str;\n\t\t\t\tif (*fmt) {\n\t\t\t\t\tif (str <= end)\n\t\t\t\t\t\t*str = *fmt;\n\t\t\t\t\t++str;\n\t\t\t\t} else {\n\t\t\t\t\t--fmt;\n\t\t\t\t}\n\t\t\t\tcontinue;\n\t\t}\n\t\tif (qualifier == 'L')\n\t\t\tnum = va_arg(args, long long);\n\t\telse if (qualifier == 'l') {\n\t\t\tnum = va_arg(args, unsigned long);\n\t\t\tif (flags & _kc_SIGN)\n\t\t\t\tnum = (signed long) num;\n\t\t} else if (qualifier == 'Z') {\n\t\t\tnum = va_arg(args, size_t);\n\t\t} else if (qualifier == 'h') {\n\t\t\tnum = (unsigned short) va_arg(args, int);\n\t\t\tif (flags & _kc_SIGN)\n\t\t\t\tnum = (signed short) num;\n\t\t} else {\n\t\t\tnum = va_arg(args, unsigned int);\n\t\t\tif (flags & _kc_SIGN)\n\t\t\t\tnum = (signed int) num;\n\t\t}\n\t\tstr = number(str, end, num, base,\n\t\t\t\tfield_width, precision, flags);\n\t}\n\tif (str <= end)\n\t\t*str = '\\0';\n\telse if (size > 0)\n\t\t/* don't write out a null byte if the buf size is zero */\n\t\t*end = '\\0';\n\t/* the trailing null byte doesn't count towards the total\n\t* ++str;\n\t*/\n\treturn str-buf;\n}\n\nint _kc_snprintf(char * buf, size_t size, const char *fmt, ...)\n{\n\tva_list args;\n\tint i;\n\n\tva_start(args, fmt);\n\ti = _kc_vsnprintf(buf,size,fmt,args);\n\tva_end(args);\n\treturn i;\n}\n#endif /* < 2.4.8 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) )\n\n/**************************************/\n/* PCI DMA MAPPING */\n\n#if defined(CONFIG_HIGHMEM)\n\n#ifndef PCI_DRAM_OFFSET\n#define PCI_DRAM_OFFSET 0\n#endif\n\nu64\n_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset,\n size_t size, int direction)\n{\n\treturn (((u64) (page - mem_map) << PAGE_SHIFT) + offset +\n\t\tPCI_DRAM_OFFSET);\n}\n\n#else /* CONFIG_HIGHMEM */\n\nu64\n_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset,\n size_t size, int direction)\n{\n\treturn pci_map_single(dev, (void *)page_address(page) + offset, size,\n\t\t\t direction);\n}\n\n#endif /* CONFIG_HIGHMEM */\n\nvoid\n_kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size,\n int direction)\n{\n\treturn pci_unmap_single(dev, dma_addr, size, direction);\n}\n\n#endif /* 2.4.13 => 2.4.3 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) )\n\n/**************************************/\n/* PCI DRIVER API */\n\nint\n_kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask)\n{\n\tif (!pci_dma_supported(dev, mask))\n\t\treturn -EIO;\n\tdev->dma_mask = mask;\n\treturn 0;\n}\n\nint\n_kc_pci_request_regions(struct pci_dev *dev, char *res_name)\n{\n\tint i;\n\n\tfor (i = 0; i < 6; i++) {\n\t\tif (pci_resource_len(dev, i) == 0)\n\t\t\tcontinue;\n\n\t\tif (pci_resource_flags(dev, i) & IORESOURCE_IO) {\n\t\t\tif (!request_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) {\n\t\t\t\tpci_release_regions(dev);\n\t\t\t\treturn -EBUSY;\n\t\t\t}\n\t\t} else if (pci_resource_flags(dev, i) & IORESOURCE_MEM) {\n\t\t\tif (!request_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) {\n\t\t\t\tpci_release_regions(dev);\n\t\t\t\treturn -EBUSY;\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\nvoid\n_kc_pci_release_regions(struct pci_dev *dev)\n{\n\tint i;\n\n\tfor (i = 0; i < 6; i++) {\n\t\tif (pci_resource_len(dev, i) == 0)\n\t\t\tcontinue;\n\n\t\tif (pci_resource_flags(dev, i) & IORESOURCE_IO)\n\t\t\trelease_region(pci_resource_start(dev, i), pci_resource_len(dev, i));\n\n\t\telse if (pci_resource_flags(dev, i) & IORESOURCE_MEM)\n\t\t\trelease_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i));\n\t}\n}\n\n/**************************************/\n/* NETWORK DRIVER API */\n\nstruct net_device *\n_kc_alloc_etherdev(int sizeof_priv)\n{\n\tstruct net_device *dev;\n\tint alloc_size;\n\n\talloc_size = sizeof(*dev) + sizeof_priv + IFNAMSIZ + 31;\n\tdev = kzalloc(alloc_size, GFP_KERNEL);\n\tif (!dev)\n\t\treturn NULL;\n\n\tif (sizeof_priv)\n\t\tdev->priv = (void *) (((unsigned long)(dev + 1) + 31) & ~31);\n\tdev->name[0] = '\\0';\n\tether_setup(dev);\n\n\treturn dev;\n}\n\nint\n_kc_is_valid_ether_addr(u8 *addr)\n{\n\tconst char zaddr[6] = { 0, };\n\n\treturn !(addr[0] & 1) && memcmp(addr, zaddr, 6);\n}\n\n#endif /* 2.4.3 => 2.4.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) )\n\nint\n_kc_pci_set_power_state(struct pci_dev *dev, int state)\n{\n\treturn 0;\n}\n\nint\n_kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable)\n{\n\treturn 0;\n}\n\n#endif /* 2.4.6 => 2.4.3 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )\nvoid _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page,\n int off, int size)\n{\n\tskb_frag_t *frag = &skb_shinfo(skb)->frags[i];\n\tfrag->page = page;\n\tfrag->page_offset = off;\n\tfrag->size = size;\n\tskb_shinfo(skb)->nr_frags = i + 1;\n}\n\n/*\n * Original Copyright:\n * find_next_bit.c: fallback find next bit implementation\n *\n * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.\n * Written by David Howells (dhowells@redhat.com)\n */\n\n/**\n * find_next_bit - find the next set bit in a memory region\n * @addr: The address to base the search on\n * @offset: The bitnumber to start searching at\n * @size: The maximum size to search\n */\nunsigned long find_next_bit(const unsigned long *addr, unsigned long size,\n unsigned long offset)\n{\n\tconst unsigned long *p = addr + BITOP_WORD(offset);\n\tunsigned long result = offset & ~(BITS_PER_LONG-1);\n\tunsigned long tmp;\n\n\tif (offset >= size)\n\t\treturn size;\n\tsize -= result;\n\toffset %= BITS_PER_LONG;\n\tif (offset) {\n\t\ttmp = *(p++);\n\t\ttmp &= (~0UL << offset);\n\t\tif (size < BITS_PER_LONG)\n\t\t\tgoto found_first;\n\t\tif (tmp)\n\t\t\tgoto found_middle;\n\t\tsize -= BITS_PER_LONG;\n\t\tresult += BITS_PER_LONG;\n\t}\n\twhile (size & ~(BITS_PER_LONG-1)) {\n\t\tif ((tmp = *(p++)))\n\t\t\tgoto found_middle;\n\t\tresult += BITS_PER_LONG;\n\t\tsize -= BITS_PER_LONG;\n\t}\n\tif (!size)\n\t\treturn result;\n\ttmp = *p;\n\nfound_first:\n\ttmp &= (~0UL >> (BITS_PER_LONG - size));\n\tif (tmp == 0UL)\t\t/* Are any bits set? */\n\t\treturn result + size;\t/* Nope. */\nfound_middle:\n\treturn result + ffs(tmp);\n}\n\nsize_t _kc_strlcpy(char *dest, const char *src, size_t size)\n{\n\tsize_t ret = strlen(src);\n\n\tif (size) {\n\t\tsize_t len = (ret >= size) ? size - 1 : ret;\n\t\tmemcpy(dest, src, len);\n\t\tdest[len] = '\\0';\n\t}\n\treturn ret;\n}\n\n#ifndef do_div\n#if BITS_PER_LONG == 32\nuint32_t __attribute__((weak)) _kc__div64_32(uint64_t *n, uint32_t base)\n{\n\tuint64_t rem = *n;\n\tuint64_t b = base;\n\tuint64_t res, d = 1;\n\tuint32_t high = rem >> 32;\n\n\t/* Reduce the thing a bit first */\n\tres = 0;\n\tif (high >= base) {\n\t\thigh /= base;\n\t\tres = (uint64_t) high << 32;\n\t\trem -= (uint64_t) (high*base) << 32;\n\t}\n\n\twhile ((int64_t)b > 0 && b < rem) {\n\t\tb = b+b;\n\t\td = d+d;\n\t}\n\n\tdo {\n\t\tif (rem >= b) {\n\t\t\trem -= b;\n\t\t\tres += d;\n\t\t}\n\t\tb >>= 1;\n\t\td >>= 1;\n\t} while (d);\n\n\t*n = res;\n\treturn rem;\n}\n#endif /* BITS_PER_LONG == 32 */\n#endif /* do_div */\n#endif /* 2.6.0 => 2.4.6 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) )\nint _kc_scnprintf(char * buf, size_t size, const char *fmt, ...)\n{\n\tva_list args;\n\tint i;\n\n\tva_start(args, fmt);\n\ti = vsnprintf(buf, size, fmt, args);\n\tva_end(args);\n\treturn (i >= size) ? (size - 1) : i;\n}\n#endif /* < 2.6.4 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) )\nDECLARE_BITMAP(_kcompat_node_online_map, MAX_NUMNODES) = {1};\n#endif /* < 2.6.10 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) )\nchar *_kc_kstrdup(const char *s, unsigned int gfp)\n{\n\tsize_t len;\n\tchar *buf;\n\n\tif (!s)\n\t\treturn NULL;\n\n\tlen = strlen(s) + 1;\n\tbuf = kmalloc(len, gfp);\n\tif (buf)\n\t\tmemcpy(buf, s, len);\n\treturn buf;\n}\n#endif /* < 2.6.13 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) )\nvoid *_kc_kzalloc(size_t size, int flags)\n{\n\tvoid *ret = kmalloc(size, flags);\n\tif (ret)\n\t\tmemset(ret, 0, size);\n\treturn ret;\n}\n#endif /* <= 2.6.13 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) )\nint _kc_skb_pad(struct sk_buff *skb, int pad)\n{\n\tint ntail;\n\n /* If the skbuff is non linear tailroom is always zero.. */\n if(!skb_cloned(skb) && skb_tailroom(skb) >= pad) {\n\t\tmemset(skb->data+skb->len, 0, pad);\n\t\treturn 0;\n }\n\n\tntail = skb->data_len + pad - (skb->end - skb->tail);\n\tif (likely(skb_cloned(skb) || ntail > 0)) {\n\t\tif (pskb_expand_head(skb, 0, ntail, GFP_ATOMIC));\n\t\t\tgoto free_skb;\n\t}\n\n#ifdef MAX_SKB_FRAGS\n\tif (skb_is_nonlinear(skb) &&\n\t !__pskb_pull_tail(skb, skb->data_len))\n\t\tgoto free_skb;\n\n#endif\n\tmemset(skb->data + skb->len, 0, pad);\n return 0;\n\nfree_skb:\n\tkfree_skb(skb);\n\treturn -ENOMEM;\n}\n\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,4)))\nint _kc_pci_save_state(struct pci_dev *pdev)\n{\n\tstruct net_device *netdev = pci_get_drvdata(pdev);\n\tstruct adapter_struct *adapter = netdev_priv(netdev);\n\tint size = PCI_CONFIG_SPACE_LEN, i;\n\tu16 pcie_cap_offset, pcie_link_status;\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) )\n\t/* no ->dev for 2.4 kernels */\n\tWARN_ON(pdev->dev.driver_data == NULL);\n#endif\n\tpcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP);\n\tif (pcie_cap_offset) {\n\t\tif (!pci_read_config_word(pdev,\n\t\t pcie_cap_offset + PCIE_LINK_STATUS,\n\t\t &pcie_link_status))\n\t\tsize = PCIE_CONFIG_SPACE_LEN;\n\t}\n\tpci_config_space_ich8lan();\n#ifdef HAVE_PCI_ERS\n\tif (adapter->config_space == NULL)\n#else\n\tWARN_ON(adapter->config_space != NULL);\n#endif\n\t\tadapter->config_space = kmalloc(size, GFP_KERNEL);\n\tif (!adapter->config_space) {\n\t\tprintk(KERN_ERR \"Out of memory in pci_save_state\\n\");\n\t\treturn -ENOMEM;\n\t}\n\tfor (i = 0; i < (size / 4); i++)\n\t\tpci_read_config_dword(pdev, i * 4, &adapter->config_space[i]);\n\treturn 0;\n}\n\nvoid _kc_pci_restore_state(struct pci_dev *pdev)\n{\n\tstruct net_device *netdev = pci_get_drvdata(pdev);\n\tstruct adapter_struct *adapter = netdev_priv(netdev);\n\tint size = PCI_CONFIG_SPACE_LEN, i;\n\tu16 pcie_cap_offset;\n\tu16 pcie_link_status;\n\n\tif (adapter->config_space != NULL) {\n\t\tpcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP);\n\t\tif (pcie_cap_offset &&\n\t\t !pci_read_config_word(pdev,\n\t\t pcie_cap_offset + PCIE_LINK_STATUS,\n\t\t &pcie_link_status))\n\t\t\tsize = PCIE_CONFIG_SPACE_LEN;\n\n\t\tpci_config_space_ich8lan();\n\t\tfor (i = 0; i < (size / 4); i++)\n\t\tpci_write_config_dword(pdev, i * 4, adapter->config_space[i]);\n#ifndef HAVE_PCI_ERS\n\t\tkfree(adapter->config_space);\n\t\tadapter->config_space = NULL;\n#endif\n\t}\n}\n#endif /* !(RHEL_RELEASE_CODE >= RHEL 5.4) */\n\n#ifdef HAVE_PCI_ERS\nvoid _kc_free_netdev(struct net_device *netdev)\n{\n\tstruct adapter_struct *adapter = netdev_priv(netdev);\n\n\tif (adapter->config_space != NULL)\n\t\tkfree(adapter->config_space);\n#ifdef CONFIG_SYSFS\n\tif (netdev->reg_state == NETREG_UNINITIALIZED) {\n\t\tkfree((char *)netdev - netdev->padded);\n\t} else {\n\t\tBUG_ON(netdev->reg_state != NETREG_UNREGISTERED);\n\t\tnetdev->reg_state = NETREG_RELEASED;\n\t\tclass_device_put(&netdev->class_dev);\n\t}\n#else\n\tkfree((char *)netdev - netdev->padded);\n#endif\n}\n#endif\n\nvoid *_kc_kmemdup(const void *src, size_t len, unsigned gfp)\n{\n\tvoid *p;\n\n\tp = kzalloc(len, gfp);\n\tif (p)\n\t\tmemcpy(p, src, len);\n\treturn p;\n}\n#endif /* <= 2.6.19 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) )\nstruct pci_dev *_kc_netdev_to_pdev(struct net_device *netdev)\n{\n\treturn ((struct adapter_struct *)netdev_priv(netdev))->pdev;\n}\n#endif /* < 2.6.21 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) )\n/* hexdump code taken from lib/hexdump.c */\nstatic void _kc_hex_dump_to_buffer(const void *buf, size_t len, int rowsize,\n\t\t\tint groupsize, unsigned char *linebuf,\n\t\t\tsize_t linebuflen, bool ascii)\n{\n\tconst u8 *ptr = buf;\n\tu8 ch;\n\tint j, lx = 0;\n\tint ascii_column;\n\n\tif (rowsize != 16 && rowsize != 32)\n\t\trowsize = 16;\n\n\tif (!len)\n\t\tgoto nil;\n\tif (len > rowsize)\t\t/* limit to one line at a time */\n\t\tlen = rowsize;\n\tif ((len % groupsize) != 0)\t/* no mixed size output */\n\t\tgroupsize = 1;\n\n\tswitch (groupsize) {\n\tcase 8: {\n\t\tconst u64 *ptr8 = buf;\n\t\tint ngroups = len / groupsize;\n\n\t\tfor (j = 0; j < ngroups; j++)\n\t\t\tlx += scnprintf((char *)(linebuf + lx), linebuflen - lx,\n\t\t\t\t\"%s%16.16llx\", j ? \" \" : \"\",\n\t\t\t\t(unsigned long long)*(ptr8 + j));\n\t\tascii_column = 17 * ngroups + 2;\n\t\tbreak;\n\t}\n\n\tcase 4: {\n\t\tconst u32 *ptr4 = buf;\n\t\tint ngroups = len / groupsize;\n\n\t\tfor (j = 0; j < ngroups; j++)\n\t\t\tlx += scnprintf((char *)(linebuf + lx), linebuflen - lx,\n\t\t\t\t\"%s%8.8x\", j ? \" \" : \"\", *(ptr4 + j));\n\t\tascii_column = 9 * ngroups + 2;\n\t\tbreak;\n\t}\n\n\tcase 2: {\n\t\tconst u16 *ptr2 = buf;\n\t\tint ngroups = len / groupsize;\n\n\t\tfor (j = 0; j < ngroups; j++)\n\t\t\tlx += scnprintf((char *)(linebuf + lx), linebuflen - lx,\n\t\t\t\t\"%s%4.4x\", j ? \" \" : \"\", *(ptr2 + j));\n\t\tascii_column = 5 * ngroups + 2;\n\t\tbreak;\n\t}\n\n\tdefault:\n\t\tfor (j = 0; (j < len) && (lx + 3) <= linebuflen; j++) {\n\t\t\tch = ptr[j];\n\t\t\tlinebuf[lx++] = hex_asc(ch >> 4);\n\t\t\tlinebuf[lx++] = hex_asc(ch & 0x0f);\n\t\t\tlinebuf[lx++] = ' ';\n\t\t}\n\t\tif (j)\n\t\t\tlx--;\n\n\t\tascii_column = 3 * rowsize + 2;\n\t\tbreak;\n\t}\n\tif (!ascii)\n\t\tgoto nil;\n\n\twhile (lx < (linebuflen - 1) && lx < (ascii_column - 1))\n\t\tlinebuf[lx++] = ' ';\n\tfor (j = 0; (j < len) && (lx + 2) < linebuflen; j++)\n\t\tlinebuf[lx++] = (isascii(ptr[j]) && isprint(ptr[j])) ? ptr[j]\n\t\t\t\t: '.';\nnil:\n\tlinebuf[lx++] = '\\0';\n}\n\nvoid _kc_print_hex_dump(const char *level,\n\t\t\tconst char *prefix_str, int prefix_type,\n\t\t\tint rowsize, int groupsize,\n\t\t\tconst void *buf, size_t len, bool ascii)\n{\n\tconst u8 *ptr = buf;\n\tint i, linelen, remaining = len;\n\tunsigned char linebuf[200];\n\n\tif (rowsize != 16 && rowsize != 32)\n\t\trowsize = 16;\n\n\tfor (i = 0; i < len; i += rowsize) {\n\t\tlinelen = min(remaining, rowsize);\n\t\tremaining -= rowsize;\n\t\t_kc_hex_dump_to_buffer(ptr + i, linelen, rowsize, groupsize,\n\t\t\t\tlinebuf, sizeof(linebuf), ascii);\n\n\t\tswitch (prefix_type) {\n\t\tcase DUMP_PREFIX_ADDRESS:\n\t\t\tprintk(\"%s%s%*p: %s\\n\", level, prefix_str,\n\t\t\t\t(int)(2 * sizeof(void *)), ptr + i, linebuf);\n\t\t\tbreak;\n\t\tcase DUMP_PREFIX_OFFSET:\n\t\t\tprintk(\"%s%s%.8x: %s\\n\", level, prefix_str, i, linebuf);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintk(\"%s%s%s\\n\", level, prefix_str, linebuf);\n\t\t\tbreak;\n\t\t}\n\t}\n}\n\n#ifdef HAVE_I2C_SUPPORT\nstruct i2c_client *\n_kc_i2c_new_device(struct i2c_adapter *adap, struct i2c_board_info const *info)\n{\n\tstruct i2c_client\t*client;\n\tint\t\t\tstatus;\n\n\tclient = kzalloc(sizeof *client, GFP_KERNEL);\n\tif (!client)\n\t\treturn NULL;\n\n\tclient->adapter = adap;\n\n\tclient->dev.platform_data = info->platform_data;\n\n\tclient->flags = info->flags;\n\tclient->addr = info->addr;\n\n\tstrlcpy(client->name, info->type, sizeof(client->name));\n\n\t/* Check for address business */\n\tstatus = i2c_check_addr(adap, client->addr);\n\tif (status)\n\t\tgoto out_err;\n\n\tclient->dev.parent = &client->adapter->dev;\n\tclient->dev.bus = &i2c_bus_type;\n\n\tstatus = i2c_attach_client(client);\n\tif (status)\n\t\tgoto out_err;\n\n\tdev_dbg(&adap->dev, \"client [%s] registered with bus id %s\\n\",\n\t\tclient->name, dev_name(&client->dev));\n\n\treturn client;\n\nout_err:\n\tdev_err(&adap->dev, \"Failed to register i2c client %s at 0x%02x \"\n\t\t\"(%d)\\n\", client->name, client->addr, status);\n\tkfree(client);\n\treturn NULL;\n}\n#endif /* HAVE_I2C_SUPPORT */\n#endif /* < 2.6.22 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) )\n#ifdef NAPI\nstruct net_device *napi_to_poll_dev(const struct napi_struct *napi)\n{\n\tstruct adapter_q_vector *q_vector = container_of(napi,\n\t struct adapter_q_vector,\n\t napi);\n\treturn &q_vector->poll_dev;\n}\n\nint __kc_adapter_clean(struct net_device *netdev, int *budget)\n{\n\tint work_done;\n\tint work_to_do = min(*budget, netdev->quota);\n\t/* kcompat.h netif_napi_add puts napi struct in \"fake netdev->priv\" */\n\tstruct napi_struct *napi = netdev->priv;\n\twork_done = napi->poll(napi, work_to_do);\n\t*budget -= work_done;\n\tnetdev->quota -= work_done;\n\treturn (work_done >= work_to_do) ? 1 : 0;\n}\n#endif /* NAPI */\n#endif /* <= 2.6.24 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) )\nvoid _kc_pci_disable_link_state(struct pci_dev *pdev, int state)\n{\n\tstruct pci_dev *parent = pdev->bus->self;\n\tu16 link_state;\n\tint pos;\n\n\tif (!parent)\n\t\treturn;\n\n\tpos = pci_find_capability(parent, PCI_CAP_ID_EXP);\n\tif (pos) {\n\t\tpci_read_config_word(parent, pos + PCI_EXP_LNKCTL, &link_state);\n\t\tlink_state &= ~state;\n\t\tpci_write_config_word(parent, pos + PCI_EXP_LNKCTL, link_state);\n\t}\n}\n#endif /* < 2.6.26 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) )\n#ifdef HAVE_TX_MQ\nvoid _kc_netif_tx_stop_all_queues(struct net_device *netdev)\n{\n\tstruct adapter_struct *adapter = netdev_priv(netdev);\n\tint i;\n\n\tnetif_stop_queue(netdev);\n\tif (netif_is_multiqueue(netdev))\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\t\tnetif_stop_subqueue(netdev, i);\n}\nvoid _kc_netif_tx_wake_all_queues(struct net_device *netdev)\n{\n\tstruct adapter_struct *adapter = netdev_priv(netdev);\n\tint i;\n\n\tnetif_wake_queue(netdev);\n\tif (netif_is_multiqueue(netdev))\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\t\tnetif_wake_subqueue(netdev, i);\n}\nvoid _kc_netif_tx_start_all_queues(struct net_device *netdev)\n{\n\tstruct adapter_struct *adapter = netdev_priv(netdev);\n\tint i;\n\n\tnetif_start_queue(netdev);\n\tif (netif_is_multiqueue(netdev))\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\t\tnetif_start_subqueue(netdev, i);\n}\n#endif /* HAVE_TX_MQ */\n\n#ifndef __WARN_printf\nvoid __kc_warn_slowpath(const char *file, int line, const char *fmt, ...)\n{\n\tva_list args;\n\n\tprintk(KERN_WARNING \"------------[ cut here ]------------\\n\");\n\tprintk(KERN_WARNING \"WARNING: at %s:%d %s()\\n\", file, line);\n\tva_start(args, fmt);\n\tvprintk(fmt, args);\n\tva_end(args);\n\n\tdump_stack();\n}\n#endif /* __WARN_printf */\n#endif /* < 2.6.27 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) )\n\nint\n_kc_pci_prepare_to_sleep(struct pci_dev *dev)\n{\n\tpci_power_t target_state;\n\tint error;\n\n\ttarget_state = pci_choose_state(dev, PMSG_SUSPEND);\n\n\tpci_enable_wake(dev, target_state, true);\n\n\terror = pci_set_power_state(dev, target_state);\n\n\tif (error)\n\t\tpci_enable_wake(dev, target_state, false);\n\n\treturn error;\n}\n\nint\n_kc_pci_wake_from_d3(struct pci_dev *dev, bool enable)\n{\n\tint err;\n\n\terr = pci_enable_wake(dev, PCI_D3cold, enable);\n\tif (err)\n\t\tgoto out;\n\n\terr = pci_enable_wake(dev, PCI_D3hot, enable);\n\nout:\n\treturn err;\n}\n#endif /* < 2.6.28 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) )\nstatic void __kc_pci_set_master(struct pci_dev *pdev, bool enable)\n{\n\tu16 old_cmd, cmd;\n\n\tpci_read_config_word(pdev, PCI_COMMAND, &old_cmd);\n\tif (enable)\n\t\tcmd = old_cmd | PCI_COMMAND_MASTER;\n\telse\n\t\tcmd = old_cmd & ~PCI_COMMAND_MASTER;\n\tif (cmd != old_cmd) {\n\t\tdev_dbg(pci_dev_to_dev(pdev), \"%s bus mastering\\n\",\n\t\t\tenable ? \"enabling\" : \"disabling\");\n\t\tpci_write_config_word(pdev, PCI_COMMAND, cmd);\n\t}\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,7) )\n\tpdev->is_busmaster = enable;\n#endif\n}\n\nvoid _kc_pci_clear_master(struct pci_dev *dev)\n{\n\t__kc_pci_set_master(dev, false);\n}\n#endif /* < 2.6.29 */\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34) )\n#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0))\nint _kc_pci_num_vf(struct pci_dev *dev)\n{\n\tint num_vf = 0;\n#ifdef CONFIG_PCI_IOV\n\tstruct pci_dev *vfdev;\n\n\t/* loop through all ethernet devices starting at PF dev */\n\tvfdev = pci_get_class(PCI_CLASS_NETWORK_ETHERNET << 8, NULL);\n\twhile (vfdev) {\n\t\tif (vfdev->is_virtfn && vfdev->physfn == dev)\n\t\t\tnum_vf++;\n\n\t\tvfdev = pci_get_class(PCI_CLASS_NETWORK_ETHERNET << 8, vfdev);\n\t}\n\n#endif\n\treturn num_vf;\n}\n#endif /* RHEL_RELEASE_CODE */\n#endif /* < 2.6.34 */\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) )\n#ifdef HAVE_TX_MQ\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0)))\n#ifndef CONFIG_NETDEVICES_MULTIQUEUE\nvoid _kc_netif_set_real_num_tx_queues(struct net_device *dev, unsigned int txq)\n{\n\tunsigned int real_num = dev->real_num_tx_queues;\n\tstruct Qdisc *qdisc;\n\tint i;\n\n\tif (unlikely(txq > dev->num_tx_queues))\n\t\t;\n\telse if (txq > real_num)\n\t\tdev->real_num_tx_queues = txq;\n\telse if ( txq < real_num) {\n\t\tdev->real_num_tx_queues = txq;\n\t\tfor (i = txq; i < dev->num_tx_queues; i++) {\n\t\t\tqdisc = netdev_get_tx_queue(dev, i)->qdisc;\n\t\t\tif (qdisc) {\n\t\t\t\tspin_lock_bh(qdisc_lock(qdisc));\n\t\t\t\tqdisc_reset(qdisc);\n\t\t\t\tspin_unlock_bh(qdisc_lock(qdisc));\n\t\t\t}\n\t\t}\n\t}\n}\n#endif /* CONFIG_NETDEVICES_MULTIQUEUE */\n#endif /* !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0)) */\n#endif /* HAVE_TX_MQ */\n\nssize_t _kc_simple_write_to_buffer(void *to, size_t available, loff_t *ppos,\n\t\t\t\t const void __user *from, size_t count)\n{\n loff_t pos = *ppos;\n size_t res;\n\n if (pos < 0)\n return -EINVAL;\n if (pos >= available || !count)\n return 0;\n if (count > available - pos)\n count = available - pos;\n res = copy_from_user(to + pos, from, count);\n if (res == count)\n return -EFAULT;\n count -= res;\n *ppos = pos + count;\n return count;\n}\n\n#endif /* < 2.6.35 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) )\nstatic const u32 _kc_flags_dup_features =\n\t(ETH_FLAG_LRO | ETH_FLAG_NTUPLE | ETH_FLAG_RXHASH);\n\nu32 _kc_ethtool_op_get_flags(struct net_device *dev)\n{\n\treturn dev->features & _kc_flags_dup_features;\n}\n\nint _kc_ethtool_op_set_flags(struct net_device *dev, u32 data, u32 supported)\n{\n\tif (data & ~supported)\n\t\treturn -EINVAL;\n\n\tdev->features = ((dev->features & ~_kc_flags_dup_features) |\n\t\t\t (data & _kc_flags_dup_features));\n\treturn 0;\n}\n#endif /* < 2.6.36 */\n\n/******************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39) )\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,0)))\n\n\n\n#endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,0)) */\n#endif /* < 2.6.39 */\n\n/******************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0) )\nvoid _kc_skb_add_rx_frag(struct sk_buff *skb, int i, struct page *page,\n\t\t\t int off, int size, unsigned int truesize)\n{\n\tskb_fill_page_desc(skb, i, page, off, size);\n\tskb->len += size;\n\tskb->data_len += size;\n\tskb->truesize += truesize;\n}\n\nint _kc_simple_open(struct inode *inode, struct file *file)\n{\n if (inode->i_private)\n file->private_data = inode->i_private;\n\n return 0;\n}\n\n#endif /* < 3.4.0 */\n\n/******************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0) )\n#if !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0)) && \\\n !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,5))\nstatic inline int __kc_pcie_cap_version(struct pci_dev *dev)\n{\n\tint pos;\n\tu16 reg16;\n\n\tpos = pci_find_capability(dev, PCI_CAP_ID_EXP);\n\tif (!pos)\n\t\treturn 0;\n\tpci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);\n\treturn reg16 & PCI_EXP_FLAGS_VERS;\n}\n\nstatic inline bool __kc_pcie_cap_has_devctl(const struct pci_dev __always_unused *dev)\n{\n\treturn true;\n}\n\nstatic inline bool __kc_pcie_cap_has_lnkctl(struct pci_dev *dev)\n{\n\tint type = pci_pcie_type(dev);\n\n\treturn __kc_pcie_cap_version(dev) > 1 ||\n\t type == PCI_EXP_TYPE_ROOT_PORT ||\n\t type == PCI_EXP_TYPE_ENDPOINT ||\n\t type == PCI_EXP_TYPE_LEG_END;\n}\n\nstatic inline bool __kc_pcie_cap_has_sltctl(struct pci_dev *dev)\n{\n\tint type = pci_pcie_type(dev);\n\tint pos;\n\tu16 pcie_flags_reg;\n\n\tpos = pci_find_capability(dev, PCI_CAP_ID_EXP);\n\tif (!pos)\n\t\treturn 0;\n\tpci_read_config_word(dev, pos + PCI_EXP_FLAGS, &pcie_flags_reg);\n\n\treturn __kc_pcie_cap_version(dev) > 1 ||\n\t type == PCI_EXP_TYPE_ROOT_PORT ||\n\t (type == PCI_EXP_TYPE_DOWNSTREAM &&\n\t\tpcie_flags_reg & PCI_EXP_FLAGS_SLOT);\n}\n\nstatic inline bool __kc_pcie_cap_has_rtctl(struct pci_dev *dev)\n{\n\tint type = pci_pcie_type(dev);\n\n\treturn __kc_pcie_cap_version(dev) > 1 ||\n\t type == PCI_EXP_TYPE_ROOT_PORT ||\n\t type == PCI_EXP_TYPE_RC_EC;\n}\n\nstatic bool __kc_pcie_capability_reg_implemented(struct pci_dev *dev, int pos)\n{\n\tif (!pci_is_pcie(dev))\n\t\treturn false;\n\n\tswitch (pos) {\n\tcase PCI_EXP_FLAGS_TYPE:\n\t\treturn true;\n\tcase PCI_EXP_DEVCAP:\n\tcase PCI_EXP_DEVCTL:\n\tcase PCI_EXP_DEVSTA:\n\t\treturn __kc_pcie_cap_has_devctl(dev);\n\tcase PCI_EXP_LNKCAP:\n\tcase PCI_EXP_LNKCTL:\n\tcase PCI_EXP_LNKSTA:\n\t\treturn __kc_pcie_cap_has_lnkctl(dev);\n\tcase PCI_EXP_SLTCAP:\n\tcase PCI_EXP_SLTCTL:\n\tcase PCI_EXP_SLTSTA:\n\t\treturn __kc_pcie_cap_has_sltctl(dev);\n\tcase PCI_EXP_RTCTL:\n\tcase PCI_EXP_RTCAP:\n\tcase PCI_EXP_RTSTA:\n\t\treturn __kc_pcie_cap_has_rtctl(dev);\n\tcase PCI_EXP_DEVCAP2:\n\tcase PCI_EXP_DEVCTL2:\n\tcase PCI_EXP_LNKCAP2:\n\tcase PCI_EXP_LNKCTL2:\n\tcase PCI_EXP_LNKSTA2:\n\t\treturn __kc_pcie_cap_version(dev) > 1;\n\tdefault:\n\t\treturn false;\n\t}\n}\n\n/*\n * Note that these accessor functions are only for the \"PCI Express\n * Capability\" (see PCIe spec r3.0, sec 7.8). They do not apply to the\n * other \"PCI Express Extended Capabilities\" (AER, VC, ACS, MFVC, etc.)\n */\nint __kc_pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)\n{\n\tint ret;\n\n\t*val = 0;\n\tif (pos & 1)\n\t\treturn -EINVAL;\n\n\tif (__kc_pcie_capability_reg_implemented(dev, pos)) {\n\t\tret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);\n\t\t/*\n\t\t * Reset *val to 0 if pci_read_config_word() fails, it may\n\t\t * have been written as 0xFFFF if hardware error happens\n\t\t * during pci_read_config_word().\n\t\t */\n\t\tif (ret)\n\t\t\t*val = 0;\n\t\treturn ret;\n\t}\n\n\t/*\n\t * For Functions that do not implement the Slot Capabilities,\n\t * Slot Status, and Slot Control registers, these spaces must\n\t * be hardwired to 0b, with the exception of the Presence Detect\n\t * State bit in the Slot Status register of Downstream Ports,\n\t * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)\n\t */\n\tif (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&\n\t pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {\n\t\t*val = PCI_EXP_SLTSTA_PDS;\n\t}\n\n\treturn 0;\n}\n\nint __kc_pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)\n{\n\tif (pos & 1)\n\t\treturn -EINVAL;\n\n\tif (!__kc_pcie_capability_reg_implemented(dev, pos))\n\t\treturn 0;\n\n\treturn pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);\n}\n\nint __kc_pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,\n\t\t\t\t\t u16 clear, u16 set)\n{\n\tint ret;\n\tu16 val;\n\n\tret = __kc_pcie_capability_read_word(dev, pos, &val);\n\tif (!ret) {\n\t\tval &= ~clear;\n\t\tval |= set;\n\t\tret = __kc_pcie_capability_write_word(dev, pos, val);\n\t}\n\n\treturn ret;\n}\n#endif /* !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0)) && \\\n !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,5)) */\n#endif /* < 3.7.0 */\n\n/******************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0) )\n#endif /* 3.9.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) )\n#ifdef CONFIG_PCI_IOV\nint __kc_pci_vfs_assigned(struct pci_dev *dev)\n{\n\tunsigned int vfs_assigned = 0;\n#ifdef HAVE_PCI_DEV_FLAGS_ASSIGNED\n\tint pos;\n\tstruct pci_dev *vfdev;\n\tunsigned short dev_id;\n\n\t/* only search if we are a PF */\n\tif (!dev->is_physfn)\n\t\treturn 0;\n\n\t/* find SR-IOV capability */\n\tpos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);\n\tif (!pos)\n\t\treturn 0;\n\n\t/*\n\t * determine the device ID for the VFs, the vendor ID will be the\n\t * same as the PF so there is no need to check for that one\n\t */\n\tpci_read_config_word(dev, pos + PCI_SRIOV_VF_DID, &dev_id);\n\n\t/* loop through all the VFs to see if we own any that are assigned */\n\tvfdev = pci_get_device(dev->vendor, dev_id, NULL);\n\twhile (vfdev) {\n\t\t/*\n\t\t * It is considered assigned if it is a virtual function with\n\t\t * our dev as the physical function and the assigned bit is set\n\t\t */\n\t\tif (vfdev->is_virtfn && (vfdev->physfn == dev) &&\n\t\t (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED))\n\t\t\tvfs_assigned++;\n\n\t\tvfdev = pci_get_device(dev->vendor, dev_id, vfdev);\n\t}\n\n#endif /* HAVE_PCI_DEV_FLAGS_ASSIGNED */\n\treturn vfs_assigned;\n}\n\n#endif /* CONFIG_PCI_IOV */\n#endif /* 3.10.0 */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/kcompat.h", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _KCOMPAT_H_\n#define _KCOMPAT_H_\n\n#ifndef LINUX_VERSION_CODE\n#include \n#else\n#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))\n#endif\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/* NAPI enable/disable flags here */\n#define NAPI\n\n#define adapter_struct igb_adapter\n#define adapter_q_vector igb_q_vector\n#define NAPI\n\n/* and finally set defines so that the code sees the changes */\n#ifdef NAPI\n#else\n#endif /* NAPI */\n\n/* packet split disable/enable */\n#ifdef DISABLE_PACKET_SPLIT\n#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT\n#define CONFIG_IGB_DISABLE_PACKET_SPLIT\n#endif\n#endif /* DISABLE_PACKET_SPLIT */\n\n/* MSI compatibility code for all kernels and drivers */\n#ifdef DISABLE_PCI_MSI\n#undef CONFIG_PCI_MSI\n#endif\n#ifndef CONFIG_PCI_MSI\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) )\nstruct msix_entry {\n\tu16 vector; /* kernel uses to write allocated vector */\n\tu16 entry; /* driver uses to specify entry, OS writes */\n};\n#endif\n#undef pci_enable_msi\n#define pci_enable_msi(a) -ENOTSUPP\n#undef pci_disable_msi\n#define pci_disable_msi(a) do {} while (0)\n#undef pci_enable_msix\n#define pci_enable_msix(a, b, c) -ENOTSUPP\n#undef pci_disable_msix\n#define pci_disable_msix(a) do {} while (0)\n#define msi_remove_pci_irq_vectors(a) do {} while (0)\n#endif /* CONFIG_PCI_MSI */\n#ifdef DISABLE_PM\n#undef CONFIG_PM\n#endif\n\n#ifdef DISABLE_NET_POLL_CONTROLLER\n#undef CONFIG_NET_POLL_CONTROLLER\n#endif\n\n#ifndef PMSG_SUSPEND\n#define PMSG_SUSPEND 3\n#endif\n\n/* generic boolean compatibility */\n#undef TRUE\n#undef FALSE\n#define TRUE true\n#define FALSE false\n#ifdef GCC_VERSION\n#if ( GCC_VERSION < 3000 )\n#define _Bool char\n#endif\n#else\n#define _Bool char\n#endif\n\n/* kernels less than 2.4.14 don't have this */\n#ifndef ETH_P_8021Q\n#define ETH_P_8021Q 0x8100\n#endif\n\n#ifndef module_param\n#define module_param(v,t,p) MODULE_PARM(v, \"i\");\n#endif\n\n#ifndef DMA_64BIT_MASK\n#define DMA_64BIT_MASK 0xffffffffffffffffULL\n#endif\n\n#ifndef DMA_32BIT_MASK\n#define DMA_32BIT_MASK 0x00000000ffffffffULL\n#endif\n\n#ifndef PCI_CAP_ID_EXP\n#define PCI_CAP_ID_EXP 0x10\n#endif\n\n#ifndef PCIE_LINK_STATE_L0S\n#define PCIE_LINK_STATE_L0S 1\n#endif\n#ifndef PCIE_LINK_STATE_L1\n#define PCIE_LINK_STATE_L1 2\n#endif\n\n#ifndef mmiowb\n#ifdef CONFIG_IA64\n#define mmiowb() asm volatile (\"mf.a\" ::: \"memory\")\n#else\n#define mmiowb()\n#endif\n#endif\n\n#ifndef SET_NETDEV_DEV\n#define SET_NETDEV_DEV(net, pdev)\n#endif\n\n#if !defined(HAVE_FREE_NETDEV) && ( LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) )\n#define free_netdev(x)\tkfree(x)\n#endif\n\n#ifdef HAVE_POLL_CONTROLLER\n#define CONFIG_NET_POLL_CONTROLLER\n#endif\n\n#ifndef SKB_DATAREF_SHIFT\n/* if we do not have the infrastructure to detect if skb_header is cloned\n just return false in all cases */\n#define skb_header_cloned(x) 0\n#endif\n\n#ifndef NETIF_F_GSO\n#define gso_size tso_size\n#define gso_segs tso_segs\n#endif\n\n#ifndef NETIF_F_GRO\n#define vlan_gro_receive(_napi, _vlgrp, _vlan, _skb) \\\n\t\tvlan_hwaccel_receive_skb(_skb, _vlgrp, _vlan)\n#define napi_gro_receive(_napi, _skb) netif_receive_skb(_skb)\n#endif\n\n#ifndef NETIF_F_SCTP_CSUM\n#define NETIF_F_SCTP_CSUM 0\n#endif\n\n#ifndef NETIF_F_LRO\n#define NETIF_F_LRO (1 << 15)\n#endif\n\n#ifndef NETIF_F_NTUPLE\n#define NETIF_F_NTUPLE (1 << 27)\n#endif\n\n#ifndef IPPROTO_SCTP\n#define IPPROTO_SCTP 132\n#endif\n\n#ifndef CHECKSUM_PARTIAL\n#define CHECKSUM_PARTIAL CHECKSUM_HW\n#define CHECKSUM_COMPLETE CHECKSUM_HW\n#endif\n\n#ifndef __read_mostly\n#define __read_mostly\n#endif\n\n#ifndef MII_RESV1\n#define MII_RESV1\t\t0x17\t\t/* Reserved...\t\t*/\n#endif\n\n#ifndef unlikely\n#define unlikely(_x) _x\n#define likely(_x) _x\n#endif\n\n#ifndef WARN_ON\n#define WARN_ON(x)\n#endif\n\n#ifndef PCI_DEVICE\n#define PCI_DEVICE(vend,dev) \\\n\t.vendor = (vend), .device = (dev), \\\n\t.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID\n#endif\n\n#ifndef node_online\n#define node_online(node) ((node) == 0)\n#endif\n\n#ifndef num_online_cpus\n#define num_online_cpus() smp_num_cpus\n#endif\n\n#ifndef cpu_online\n#define cpu_online(cpuid) test_bit((cpuid), &cpu_online_map)\n#endif\n\n#ifndef _LINUX_RANDOM_H\n#include \n#endif\n\n#ifndef DECLARE_BITMAP\n#ifndef BITS_TO_LONGS\n#define BITS_TO_LONGS(bits) (((bits)+BITS_PER_LONG-1)/BITS_PER_LONG)\n#endif\n#define DECLARE_BITMAP(name,bits) long name[BITS_TO_LONGS(bits)]\n#endif\n\n#ifndef VLAN_HLEN\n#define VLAN_HLEN 4\n#endif\n\n#ifndef VLAN_ETH_HLEN\n#define VLAN_ETH_HLEN 18\n#endif\n\n#ifndef VLAN_ETH_FRAME_LEN\n#define VLAN_ETH_FRAME_LEN 1518\n#endif\n\n#if !defined(IXGBE_DCA) && !defined(IGB_DCA)\n#define dca_get_tag(b) 0\n#define dca_add_requester(a) -1\n#define dca_remove_requester(b) do { } while(0)\n#define DCA_PROVIDER_ADD 0x0001\n#define DCA_PROVIDER_REMOVE 0x0002\n#endif\n\n#ifndef DCA_GET_TAG_TWO_ARGS\n#define dca3_get_tag(a,b) dca_get_tag(b)\n#endif\n\n#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS\n#if defined(__i386__) || defined(__x86_64__)\n#define CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS\n#endif\n#endif\n\n/* taken from 2.6.24 definition in linux/kernel.h */\n#ifndef IS_ALIGNED\n#define IS_ALIGNED(x,a) (((x) % ((typeof(x))(a))) == 0)\n#endif\n\n#ifdef IS_ENABLED\n#undef IS_ENABLED\n#undef __ARG_PLACEHOLDER_1\n#undef config_enabled\n#undef _config_enabled\n#undef __config_enabled\n#undef ___config_enabled\n#endif\n\n#define __ARG_PLACEHOLDER_1 0,\n#define config_enabled(cfg) _config_enabled(cfg)\n#define _config_enabled(value) __config_enabled(__ARG_PLACEHOLDER_##value)\n#define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0)\n#define ___config_enabled(__ignored, val, ...) val\n\n#define IS_ENABLED(option) \\\n\t(config_enabled(option) || config_enabled(option##_MODULE))\n\n#if !defined(NETIF_F_HW_VLAN_TX) && !defined(NETIF_F_HW_VLAN_CTAG_TX)\nstruct _kc_vlan_ethhdr {\n\tunsigned char\th_dest[ETH_ALEN];\n\tunsigned char\th_source[ETH_ALEN];\n\t__be16\t\th_vlan_proto;\n\t__be16\t\th_vlan_TCI;\n\t__be16\t\th_vlan_encapsulated_proto;\n};\n#define vlan_ethhdr _kc_vlan_ethhdr\nstruct _kc_vlan_hdr {\n\t__be16\t\th_vlan_TCI;\n\t__be16\t\th_vlan_encapsulated_proto;\n};\n#define vlan_hdr _kc_vlan_hdr\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) )\n#define vlan_tx_tag_present(_skb) 0\n#define vlan_tx_tag_get(_skb) 0\n#endif\n#endif /* NETIF_F_HW_VLAN_TX && NETIF_F_HW_VLAN_CTAG_TX */\n\n#ifndef VLAN_PRIO_SHIFT\n#define VLAN_PRIO_SHIFT 13\n#endif\n\n\n#ifndef __GFP_COLD\n#define __GFP_COLD 0\n#endif\n\n#ifndef __GFP_COMP\n#define __GFP_COMP 0\n#endif\n\n/*****************************************************************************/\n/* Installations with ethtool version without eeprom, adapter id, or statistics\n * support */\n\n#ifndef ETH_GSTRING_LEN\n#define ETH_GSTRING_LEN 32\n#endif\n\n#ifndef ETHTOOL_GSTATS\n#define ETHTOOL_GSTATS 0x1d\n#undef ethtool_drvinfo\n#define ethtool_drvinfo k_ethtool_drvinfo\nstruct k_ethtool_drvinfo {\n\tu32 cmd;\n\tchar driver[32];\n\tchar version[32];\n\tchar fw_version[32];\n\tchar bus_info[32];\n\tchar reserved1[32];\n\tchar reserved2[16];\n\tu32 n_stats;\n\tu32 testinfo_len;\n\tu32 eedump_len;\n\tu32 regdump_len;\n};\n\nstruct ethtool_stats {\n\tu32 cmd;\n\tu32 n_stats;\n\tu64 data[0];\n};\n#endif /* ETHTOOL_GSTATS */\n\n#ifndef ETHTOOL_PHYS_ID\n#define ETHTOOL_PHYS_ID 0x1c\n#endif /* ETHTOOL_PHYS_ID */\n\n#ifndef ETHTOOL_GSTRINGS\n#define ETHTOOL_GSTRINGS 0x1b\nenum ethtool_stringset {\n\tETH_SS_TEST = 0,\n\tETH_SS_STATS,\n};\nstruct ethtool_gstrings {\n\tu32 cmd; /* ETHTOOL_GSTRINGS */\n\tu32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/\n\tu32 len; /* number of strings in the string set */\n\tu8 data[0];\n};\n#endif /* ETHTOOL_GSTRINGS */\n\n#ifndef ETHTOOL_TEST\n#define ETHTOOL_TEST 0x1a\nenum ethtool_test_flags {\n\tETH_TEST_FL_OFFLINE\t= (1 << 0),\n\tETH_TEST_FL_FAILED\t= (1 << 1),\n};\nstruct ethtool_test {\n\tu32 cmd;\n\tu32 flags;\n\tu32 reserved;\n\tu32 len;\n\tu64 data[0];\n};\n#endif /* ETHTOOL_TEST */\n\n#ifndef ETHTOOL_GEEPROM\n#define ETHTOOL_GEEPROM 0xb\n#undef ETHTOOL_GREGS\nstruct ethtool_eeprom {\n\tu32 cmd;\n\tu32 magic;\n\tu32 offset;\n\tu32 len;\n\tu8 data[0];\n};\n\nstruct ethtool_value {\n\tu32 cmd;\n\tu32 data;\n};\n#endif /* ETHTOOL_GEEPROM */\n\n#ifndef ETHTOOL_GLINK\n#define ETHTOOL_GLINK 0xa\n#endif /* ETHTOOL_GLINK */\n\n#ifndef ETHTOOL_GWOL\n#define ETHTOOL_GWOL 0x5\n#define ETHTOOL_SWOL 0x6\n#define SOPASS_MAX 6\nstruct ethtool_wolinfo {\n\tu32 cmd;\n\tu32 supported;\n\tu32 wolopts;\n\tu8 sopass[SOPASS_MAX]; /* SecureOn(tm) password */\n};\n#endif /* ETHTOOL_GWOL */\n\n#ifndef ETHTOOL_GREGS\n#define ETHTOOL_GREGS\t\t0x00000004 /* Get NIC registers */\n#define ethtool_regs _kc_ethtool_regs\n/* for passing big chunks of data */\nstruct _kc_ethtool_regs {\n\tu32 cmd;\n\tu32 version; /* driver-specific, indicates different chips/revs */\n\tu32 len; /* bytes */\n\tu8 data[0];\n};\n#endif /* ETHTOOL_GREGS */\n\n#ifndef ETHTOOL_GMSGLVL\n#define ETHTOOL_GMSGLVL\t\t0x00000007 /* Get driver message level */\n#endif\n#ifndef ETHTOOL_SMSGLVL\n#define ETHTOOL_SMSGLVL\t\t0x00000008 /* Set driver msg level, priv. */\n#endif\n#ifndef ETHTOOL_NWAY_RST\n#define ETHTOOL_NWAY_RST\t0x00000009 /* Restart autonegotiation, priv */\n#endif\n#ifndef ETHTOOL_GLINK\n#define ETHTOOL_GLINK\t\t0x0000000a /* Get link status */\n#endif\n#ifndef ETHTOOL_GEEPROM\n#define ETHTOOL_GEEPROM\t\t0x0000000b /* Get EEPROM data */\n#endif\n#ifndef ETHTOOL_SEEPROM\n#define ETHTOOL_SEEPROM\t\t0x0000000c /* Set EEPROM data */\n#endif\n#ifndef ETHTOOL_GCOALESCE\n#define ETHTOOL_GCOALESCE\t0x0000000e /* Get coalesce config */\n/* for configuring coalescing parameters of chip */\n#define ethtool_coalesce _kc_ethtool_coalesce\nstruct _kc_ethtool_coalesce {\n\tu32\tcmd;\t/* ETHTOOL_{G,S}COALESCE */\n\n\t/* How many usecs to delay an RX interrupt after\n\t * a packet arrives. If 0, only rx_max_coalesced_frames\n\t * is used.\n\t */\n\tu32\trx_coalesce_usecs;\n\n\t/* How many packets to delay an RX interrupt after\n\t * a packet arrives. If 0, only rx_coalesce_usecs is\n\t * used. It is illegal to set both usecs and max frames\n\t * to zero as this would cause RX interrupts to never be\n\t * generated.\n\t */\n\tu32\trx_max_coalesced_frames;\n\n\t/* Same as above two parameters, except that these values\n\t * apply while an IRQ is being serviced by the host. Not\n\t * all cards support this feature and the values are ignored\n\t * in that case.\n\t */\n\tu32\trx_coalesce_usecs_irq;\n\tu32\trx_max_coalesced_frames_irq;\n\n\t/* How many usecs to delay a TX interrupt after\n\t * a packet is sent. If 0, only tx_max_coalesced_frames\n\t * is used.\n\t */\n\tu32\ttx_coalesce_usecs;\n\n\t/* How many packets to delay a TX interrupt after\n\t * a packet is sent. If 0, only tx_coalesce_usecs is\n\t * used. It is illegal to set both usecs and max frames\n\t * to zero as this would cause TX interrupts to never be\n\t * generated.\n\t */\n\tu32\ttx_max_coalesced_frames;\n\n\t/* Same as above two parameters, except that these values\n\t * apply while an IRQ is being serviced by the host. Not\n\t * all cards support this feature and the values are ignored\n\t * in that case.\n\t */\n\tu32\ttx_coalesce_usecs_irq;\n\tu32\ttx_max_coalesced_frames_irq;\n\n\t/* How many usecs to delay in-memory statistics\n\t * block updates. Some drivers do not have an in-memory\n\t * statistic block, and in such cases this value is ignored.\n\t * This value must not be zero.\n\t */\n\tu32\tstats_block_coalesce_usecs;\n\n\t/* Adaptive RX/TX coalescing is an algorithm implemented by\n\t * some drivers to improve latency under low packet rates and\n\t * improve throughput under high packet rates. Some drivers\n\t * only implement one of RX or TX adaptive coalescing. Anything\n\t * not implemented by the driver causes these values to be\n\t * silently ignored.\n\t */\n\tu32\tuse_adaptive_rx_coalesce;\n\tu32\tuse_adaptive_tx_coalesce;\n\n\t/* When the packet rate (measured in packets per second)\n\t * is below pkt_rate_low, the {rx,tx}_*_low parameters are\n\t * used.\n\t */\n\tu32\tpkt_rate_low;\n\tu32\trx_coalesce_usecs_low;\n\tu32\trx_max_coalesced_frames_low;\n\tu32\ttx_coalesce_usecs_low;\n\tu32\ttx_max_coalesced_frames_low;\n\n\t/* When the packet rate is below pkt_rate_high but above\n\t * pkt_rate_low (both measured in packets per second) the\n\t * normal {rx,tx}_* coalescing parameters are used.\n\t */\n\n\t/* When the packet rate is (measured in packets per second)\n\t * is above pkt_rate_high, the {rx,tx}_*_high parameters are\n\t * used.\n\t */\n\tu32\tpkt_rate_high;\n\tu32\trx_coalesce_usecs_high;\n\tu32\trx_max_coalesced_frames_high;\n\tu32\ttx_coalesce_usecs_high;\n\tu32\ttx_max_coalesced_frames_high;\n\n\t/* How often to do adaptive coalescing packet rate sampling,\n\t * measured in seconds. Must not be zero.\n\t */\n\tu32\trate_sample_interval;\n};\n#endif /* ETHTOOL_GCOALESCE */\n\n#ifndef ETHTOOL_SCOALESCE\n#define ETHTOOL_SCOALESCE\t0x0000000f /* Set coalesce config. */\n#endif\n#ifndef ETHTOOL_GRINGPARAM\n#define ETHTOOL_GRINGPARAM\t0x00000010 /* Get ring parameters */\n/* for configuring RX/TX ring parameters */\n#define ethtool_ringparam _kc_ethtool_ringparam\nstruct _kc_ethtool_ringparam {\n\tu32\tcmd;\t/* ETHTOOL_{G,S}RINGPARAM */\n\n\t/* Read only attributes. These indicate the maximum number\n\t * of pending RX/TX ring entries the driver will allow the\n\t * user to set.\n\t */\n\tu32\trx_max_pending;\n\tu32\trx_mini_max_pending;\n\tu32\trx_jumbo_max_pending;\n\tu32\ttx_max_pending;\n\n\t/* Values changeable by the user. The valid values are\n\t * in the range 1 to the \"*_max_pending\" counterpart above.\n\t */\n\tu32\trx_pending;\n\tu32\trx_mini_pending;\n\tu32\trx_jumbo_pending;\n\tu32\ttx_pending;\n};\n#endif /* ETHTOOL_GRINGPARAM */\n\n#ifndef ETHTOOL_SRINGPARAM\n#define ETHTOOL_SRINGPARAM\t0x00000011 /* Set ring parameters, priv. */\n#endif\n#ifndef ETHTOOL_GPAUSEPARAM\n#define ETHTOOL_GPAUSEPARAM\t0x00000012 /* Get pause parameters */\n/* for configuring link flow control parameters */\n#define ethtool_pauseparam _kc_ethtool_pauseparam\nstruct _kc_ethtool_pauseparam {\n\tu32\tcmd;\t/* ETHTOOL_{G,S}PAUSEPARAM */\n\n\t/* If the link is being auto-negotiated (via ethtool_cmd.autoneg\n\t * being true) the user may set 'autoneg' here non-zero to have the\n\t * pause parameters be auto-negotiated too. In such a case, the\n\t * {rx,tx}_pause values below determine what capabilities are\n\t * advertised.\n\t *\n\t * If 'autoneg' is zero or the link is not being auto-negotiated,\n\t * then {rx,tx}_pause force the driver to use/not-use pause\n\t * flow control.\n\t */\n\tu32\tautoneg;\n\tu32\trx_pause;\n\tu32\ttx_pause;\n};\n#endif /* ETHTOOL_GPAUSEPARAM */\n\n#ifndef ETHTOOL_SPAUSEPARAM\n#define ETHTOOL_SPAUSEPARAM\t0x00000013 /* Set pause parameters. */\n#endif\n#ifndef ETHTOOL_GRXCSUM\n#define ETHTOOL_GRXCSUM\t\t0x00000014 /* Get RX hw csum enable (ethtool_value) */\n#endif\n#ifndef ETHTOOL_SRXCSUM\n#define ETHTOOL_SRXCSUM\t\t0x00000015 /* Set RX hw csum enable (ethtool_value) */\n#endif\n#ifndef ETHTOOL_GTXCSUM\n#define ETHTOOL_GTXCSUM\t\t0x00000016 /* Get TX hw csum enable (ethtool_value) */\n#endif\n#ifndef ETHTOOL_STXCSUM\n#define ETHTOOL_STXCSUM\t\t0x00000017 /* Set TX hw csum enable (ethtool_value) */\n#endif\n#ifndef ETHTOOL_GSG\n#define ETHTOOL_GSG\t\t0x00000018 /* Get scatter-gather enable\n\t\t\t\t\t * (ethtool_value) */\n#endif\n#ifndef ETHTOOL_SSG\n#define ETHTOOL_SSG\t\t0x00000019 /* Set scatter-gather enable\n\t\t\t\t\t * (ethtool_value). */\n#endif\n#ifndef ETHTOOL_TEST\n#define ETHTOOL_TEST\t\t0x0000001a /* execute NIC self-test, priv. */\n#endif\n#ifndef ETHTOOL_GSTRINGS\n#define ETHTOOL_GSTRINGS\t0x0000001b /* get specified string set */\n#endif\n#ifndef ETHTOOL_PHYS_ID\n#define ETHTOOL_PHYS_ID\t\t0x0000001c /* identify the NIC */\n#endif\n#ifndef ETHTOOL_GSTATS\n#define ETHTOOL_GSTATS\t\t0x0000001d /* get NIC-specific statistics */\n#endif\n#ifndef ETHTOOL_GTSO\n#define ETHTOOL_GTSO\t\t0x0000001e /* Get TSO enable (ethtool_value) */\n#endif\n#ifndef ETHTOOL_STSO\n#define ETHTOOL_STSO\t\t0x0000001f /* Set TSO enable (ethtool_value) */\n#endif\n\n#ifndef ETHTOOL_BUSINFO_LEN\n#define ETHTOOL_BUSINFO_LEN\t32\n#endif\n\n#ifndef RHEL_RELEASE_VERSION\n#define RHEL_RELEASE_VERSION(a,b) (((a) << 8) + (b))\n#endif\n#ifndef AX_RELEASE_VERSION\n#define AX_RELEASE_VERSION(a,b) (((a) << 8) + (b))\n#endif\n\n#ifndef AX_RELEASE_CODE\n#define AX_RELEASE_CODE 0\n#endif\n\n#if (AX_RELEASE_CODE && AX_RELEASE_CODE == AX_RELEASE_VERSION(3,0))\n#define RHEL_RELEASE_CODE RHEL_RELEASE_VERSION(5,0)\n#elif (AX_RELEASE_CODE && AX_RELEASE_CODE == AX_RELEASE_VERSION(3,1))\n#define RHEL_RELEASE_CODE RHEL_RELEASE_VERSION(5,1)\n#elif (AX_RELEASE_CODE && AX_RELEASE_CODE == AX_RELEASE_VERSION(3,2))\n#define RHEL_RELEASE_CODE RHEL_RELEASE_VERSION(5,3)\n#endif\n\n#ifndef RHEL_RELEASE_CODE\n/* NOTE: RHEL_RELEASE_* introduced in RHEL4.5 */\n#define RHEL_RELEASE_CODE 0\n#endif\n\n/* SuSE version macro is the same as Linux kernel version */\n#ifndef SLE_VERSION\n#define SLE_VERSION(a,b,c) KERNEL_VERSION(a,b,c)\n#endif\n#ifdef CONFIG_SUSE_KERNEL\n#if ( LINUX_VERSION_CODE == KERNEL_VERSION(2,6,27) )\n/* SLES11 GA is 2.6.27 based */\n#define SLE_VERSION_CODE SLE_VERSION(11,0,0)\n#elif ( LINUX_VERSION_CODE == KERNEL_VERSION(2,6,32) )\n/* SLES11 SP1 is 2.6.32 based */\n#define SLE_VERSION_CODE SLE_VERSION(11,1,0)\n#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,61)) && \\\n (LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0)))\n/* SLES11 SP3 is at least 3.0.61+ based */\n#define SLE_VERSION_CODE SLE_VERSION(11,3,0)\n#elif ( LINUX_VERSION_CODE >= KERNEL_VERSION(3,12,28) )\n/* SLES12 is at least 3.12.28+ based */\n#define SLE_VERSION_CODE SLE_VERSION(12,0,0)\n#endif /* LINUX_VERSION_CODE == KERNEL_VERSION(x,y,z) */\n#endif /* CONFIG_SUSE_KERNEL */\n#ifndef SLE_VERSION_CODE\n#define SLE_VERSION_CODE 0\n#endif /* SLE_VERSION_CODE */\n\n/* Ubuntu release and kernel codes must be specified from Makefile */\n#ifndef UBUNTU_RELEASE_VERSION\n#define UBUNTU_RELEASE_VERSION(a,b) (((a) * 100) + (b))\n#endif\n#ifndef UBUNTU_KERNEL_VERSION\n#define UBUNTU_KERNEL_VERSION(a,b,c,abi,upload) (((a) << 40) + ((b) << 32) + ((c) << 24) + ((abi) << 8) + (upload))\n#endif\n#ifndef UBUNTU_RELEASE_CODE\n#define UBUNTU_RELEASE_CODE 0\n#endif\n#ifndef UBUNTU_KERNEL_CODE\n#define UBUNTU_KERNEL_CODE 0\n#endif\n\n#ifdef __KLOCWORK__\n#ifdef ARRAY_SIZE\n#undef ARRAY_SIZE\n#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))\n#endif\n#endif /* __KLOCWORK__ */\n\n/*****************************************************************************/\n/* 2.4.3 => 2.4.0 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) )\n\n/**************************************/\n/* PCI DRIVER API */\n\n#ifndef pci_set_dma_mask\n#define pci_set_dma_mask _kc_pci_set_dma_mask\nextern int _kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask);\n#endif\n\n#ifndef pci_request_regions\n#define pci_request_regions _kc_pci_request_regions\nextern int _kc_pci_request_regions(struct pci_dev *pdev, char *res_name);\n#endif\n\n#ifndef pci_release_regions\n#define pci_release_regions _kc_pci_release_regions\nextern void _kc_pci_release_regions(struct pci_dev *pdev);\n#endif\n\n/**************************************/\n/* NETWORK DRIVER API */\n\n#ifndef alloc_etherdev\n#define alloc_etherdev _kc_alloc_etherdev\nextern struct net_device * _kc_alloc_etherdev(int sizeof_priv);\n#endif\n\n#ifndef is_valid_ether_addr\n#define is_valid_ether_addr _kc_is_valid_ether_addr\nextern int _kc_is_valid_ether_addr(u8 *addr);\n#endif\n\n/**************************************/\n/* MISCELLANEOUS */\n\n#ifndef INIT_TQUEUE\n#define INIT_TQUEUE(_tq, _routine, _data)\t\t\\\n\tdo {\t\t\t\t\t\t\\\n\t\tINIT_LIST_HEAD(&(_tq)->list);\t\t\\\n\t\t(_tq)->sync = 0;\t\t\t\\\n\t\t(_tq)->routine = _routine;\t\t\\\n\t\t(_tq)->data = _data;\t\t\t\\\n\t} while (0)\n#endif\n\n#endif /* 2.4.3 => 2.4.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,5) )\n/* Generic MII registers. */\n#define MII_BMCR 0x00 /* Basic mode control register */\n#define MII_BMSR 0x01 /* Basic mode status register */\n#define MII_PHYSID1 0x02 /* PHYS ID 1 */\n#define MII_PHYSID2 0x03 /* PHYS ID 2 */\n#define MII_ADVERTISE 0x04 /* Advertisement control reg */\n#define MII_LPA 0x05 /* Link partner ability reg */\n#define MII_EXPANSION 0x06 /* Expansion register */\n/* Basic mode control register. */\n#define BMCR_FULLDPLX 0x0100 /* Full duplex */\n#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */\n/* Basic mode status register. */\n#define BMSR_ERCAP 0x0001 /* Ext-reg capability */\n#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */\n#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */\n#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */\n#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */\n#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */\n/* Advertisement control register. */\n#define ADVERTISE_CSMA 0x0001 /* Only selector supported */\n#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */\n#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */\n#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */\n#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */\n#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \\\n ADVERTISE_100HALF | ADVERTISE_100FULL)\n/* Expansion register for auto-negotiation. */\n#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */\n#endif\n\n/*****************************************************************************/\n/* 2.4.6 => 2.4.3 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) )\n\n#ifndef pci_set_power_state\n#define pci_set_power_state _kc_pci_set_power_state\nextern int _kc_pci_set_power_state(struct pci_dev *dev, int state);\n#endif\n\n#ifndef pci_enable_wake\n#define pci_enable_wake _kc_pci_enable_wake\nextern int _kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable);\n#endif\n\n#ifndef pci_disable_device\n#define pci_disable_device _kc_pci_disable_device\nextern void _kc_pci_disable_device(struct pci_dev *pdev);\n#endif\n\n/* PCI PM entry point syntax changed, so don't support suspend/resume */\n#undef CONFIG_PM\n\n#endif /* 2.4.6 => 2.4.3 */\n\n#ifndef HAVE_PCI_SET_MWI\n#define pci_set_mwi(X) pci_write_config_word(X, \\\n\t\t\t PCI_COMMAND, adapter->hw.bus.pci_cmd_word | \\\n\t\t\t PCI_COMMAND_INVALIDATE);\n#define pci_clear_mwi(X) pci_write_config_word(X, \\\n\t\t\t PCI_COMMAND, adapter->hw.bus.pci_cmd_word & \\\n\t\t\t ~PCI_COMMAND_INVALIDATE);\n#endif\n\n/*****************************************************************************/\n/* 2.4.10 => 2.4.9 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) )\n\n/**************************************/\n/* MODULE API */\n\n#ifndef MODULE_LICENSE\n\t#define MODULE_LICENSE(X)\n#endif\n\n/**************************************/\n/* OTHER */\n\n#undef min\n#define min(x,y) ({ \\\n\tconst typeof(x) _x = (x);\t\\\n\tconst typeof(y) _y = (y);\t\\\n\t(void) (&_x == &_y);\t\t\\\n\t_x < _y ? _x : _y; })\n\n#undef max\n#define max(x,y) ({ \\\n\tconst typeof(x) _x = (x);\t\\\n\tconst typeof(y) _y = (y);\t\\\n\t(void) (&_x == &_y);\t\t\\\n\t_x > _y ? _x : _y; })\n\n#define min_t(type,x,y) ({ \\\n\ttype _x = (x); \\\n\ttype _y = (y); \\\n\t_x < _y ? _x : _y; })\n\n#define max_t(type,x,y) ({ \\\n\ttype _x = (x); \\\n\ttype _y = (y); \\\n\t_x > _y ? _x : _y; })\n\n#ifndef list_for_each_safe\n#define list_for_each_safe(pos, n, head) \\\n\tfor (pos = (head)->next, n = pos->next; pos != (head); \\\n\t\tpos = n, n = pos->next)\n#endif\n\n#ifndef ____cacheline_aligned_in_smp\n#ifdef CONFIG_SMP\n#define ____cacheline_aligned_in_smp ____cacheline_aligned\n#else\n#define ____cacheline_aligned_in_smp\n#endif /* CONFIG_SMP */\n#endif\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,8) )\nextern int _kc_snprintf(char * buf, size_t size, const char *fmt, ...);\n#define snprintf(buf, size, fmt, args...) _kc_snprintf(buf, size, fmt, ##args)\nextern int _kc_vsnprintf(char *buf, size_t size, const char *fmt, va_list args);\n#define vsnprintf(buf, size, fmt, args) _kc_vsnprintf(buf, size, fmt, args)\n#else /* 2.4.8 => 2.4.9 */\nextern int snprintf(char * buf, size_t size, const char *fmt, ...);\nextern int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);\n#endif\n#endif /* 2.4.10 -> 2.4.6 */\n\n\n/*****************************************************************************/\n/* 2.4.12 => 2.4.10 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,12) )\n#ifndef HAVE_NETIF_MSG\n#define HAVE_NETIF_MSG 1\nenum {\n\tNETIF_MSG_DRV\t\t= 0x0001,\n\tNETIF_MSG_PROBE\t\t= 0x0002,\n\tNETIF_MSG_LINK\t\t= 0x0004,\n\tNETIF_MSG_TIMER\t\t= 0x0008,\n\tNETIF_MSG_IFDOWN\t= 0x0010,\n\tNETIF_MSG_IFUP\t\t= 0x0020,\n\tNETIF_MSG_RX_ERR\t= 0x0040,\n\tNETIF_MSG_TX_ERR\t= 0x0080,\n\tNETIF_MSG_TX_QUEUED\t= 0x0100,\n\tNETIF_MSG_INTR\t\t= 0x0200,\n\tNETIF_MSG_TX_DONE\t= 0x0400,\n\tNETIF_MSG_RX_STATUS\t= 0x0800,\n\tNETIF_MSG_PKTDATA\t= 0x1000,\n\tNETIF_MSG_HW\t\t= 0x2000,\n\tNETIF_MSG_WOL\t\t= 0x4000,\n};\n\n#define netif_msg_drv(p)\t((p)->msg_enable & NETIF_MSG_DRV)\n#define netif_msg_probe(p)\t((p)->msg_enable & NETIF_MSG_PROBE)\n#define netif_msg_link(p)\t((p)->msg_enable & NETIF_MSG_LINK)\n#define netif_msg_timer(p)\t((p)->msg_enable & NETIF_MSG_TIMER)\n#define netif_msg_ifdown(p)\t((p)->msg_enable & NETIF_MSG_IFDOWN)\n#define netif_msg_ifup(p)\t((p)->msg_enable & NETIF_MSG_IFUP)\n#define netif_msg_rx_err(p)\t((p)->msg_enable & NETIF_MSG_RX_ERR)\n#define netif_msg_tx_err(p)\t((p)->msg_enable & NETIF_MSG_TX_ERR)\n#define netif_msg_tx_queued(p)\t((p)->msg_enable & NETIF_MSG_TX_QUEUED)\n#define netif_msg_intr(p)\t((p)->msg_enable & NETIF_MSG_INTR)\n#define netif_msg_tx_done(p)\t((p)->msg_enable & NETIF_MSG_TX_DONE)\n#define netif_msg_rx_status(p)\t((p)->msg_enable & NETIF_MSG_RX_STATUS)\n#define netif_msg_pktdata(p)\t((p)->msg_enable & NETIF_MSG_PKTDATA)\n#endif /* !HAVE_NETIF_MSG */\n#endif /* 2.4.12 => 2.4.10 */\n\n/*****************************************************************************/\n/* 2.4.13 => 2.4.12 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) )\n\n/**************************************/\n/* PCI DMA MAPPING */\n\n#ifndef virt_to_page\n\t#define virt_to_page(v) (mem_map + (virt_to_phys(v) >> PAGE_SHIFT))\n#endif\n\n#ifndef pci_map_page\n#define pci_map_page _kc_pci_map_page\nextern u64 _kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, size_t size, int direction);\n#endif\n\n#ifndef pci_unmap_page\n#define pci_unmap_page _kc_pci_unmap_page\nextern void _kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, int direction);\n#endif\n\n/* pci_set_dma_mask takes dma_addr_t, which is only 32-bits prior to 2.4.13 */\n\n#undef DMA_32BIT_MASK\n#define DMA_32BIT_MASK\t0xffffffff\n#undef DMA_64BIT_MASK\n#define DMA_64BIT_MASK\t0xffffffff\n\n/**************************************/\n/* OTHER */\n\n#ifndef cpu_relax\n#define cpu_relax()\trep_nop()\n#endif\n\nstruct vlan_ethhdr {\n\tunsigned char h_dest[ETH_ALEN];\n\tunsigned char h_source[ETH_ALEN];\n\tunsigned short h_vlan_proto;\n\tunsigned short h_vlan_TCI;\n\tunsigned short h_vlan_encapsulated_proto;\n};\n#endif /* 2.4.13 => 2.4.12 */\n\n/*****************************************************************************/\n/* 2.4.17 => 2.4.12 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17) )\n\n#ifndef __devexit_p\n\t#define __devexit_p(x) &(x)\n#endif\n\n#else\n /* For Kernel 3.8 these are not defined - so undefine all */\n #undef __devexit_p\n #undef __devexit\n #undef __devinit\n #undef __devinitdata\n #define __devexit_p(x) &(x)\n #define __devexit\n #define __devinit\n #define __devinitdata\n\n#endif /* 2.4.17 => 2.4.13 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,18) )\n#define NETIF_MSG_HW\t0x2000\n#define NETIF_MSG_WOL\t0x4000\n\n#ifndef netif_msg_hw\n#define netif_msg_hw(p)\t\t((p)->msg_enable & NETIF_MSG_HW)\n#endif\n#ifndef netif_msg_wol\n#define netif_msg_wol(p)\t((p)->msg_enable & NETIF_MSG_WOL)\n#endif\n#endif /* 2.4.18 */\n\n/*****************************************************************************/\n\n/*****************************************************************************/\n/* 2.4.20 => 2.4.19 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20) )\n\n/* we won't support NAPI on less than 2.4.20 */\n#ifdef NAPI\n#undef NAPI\n#endif\n\n#endif /* 2.4.20 => 2.4.19 */\n\n/*****************************************************************************/\n/* 2.4.22 => 2.4.17 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) )\n#define pci_name(x)\t((x)->slot_name)\n\n#ifndef SUPPORTED_10000baseT_Full\n#define SUPPORTED_10000baseT_Full\t(1 << 12)\n#endif\n#ifndef ADVERTISED_10000baseT_Full\n#define ADVERTISED_10000baseT_Full\t(1 << 12)\n#endif\n#endif\n\n/*****************************************************************************/\n/* 2.4.22 => 2.4.17 */\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) )\n#ifndef IGB_NO_LRO\n#define IGB_NO_LRO\n#endif\n#endif\n\n/*****************************************************************************/\n/*****************************************************************************/\n/* 2.4.23 => 2.4.22 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23) )\n/*****************************************************************************/\n#ifdef NAPI\n#ifndef netif_poll_disable\n#define netif_poll_disable(x) _kc_netif_poll_disable(x)\nstatic inline void _kc_netif_poll_disable(struct net_device *netdev)\n{\n\twhile (test_and_set_bit(__LINK_STATE_RX_SCHED, &netdev->state)) {\n\t\t/* No hurry */\n\t\tcurrent->state = TASK_INTERRUPTIBLE;\n\t\tschedule_timeout(1);\n\t}\n}\n#endif\n#ifndef netif_poll_enable\n#define netif_poll_enable(x) _kc_netif_poll_enable(x)\nstatic inline void _kc_netif_poll_enable(struct net_device *netdev)\n{\n\tclear_bit(__LINK_STATE_RX_SCHED, &netdev->state);\n}\n#endif\n#endif /* NAPI */\n#ifndef netif_tx_disable\n#define netif_tx_disable(x) _kc_netif_tx_disable(x)\nstatic inline void _kc_netif_tx_disable(struct net_device *dev)\n{\n\tspin_lock_bh(&dev->xmit_lock);\n\tnetif_stop_queue(dev);\n\tspin_unlock_bh(&dev->xmit_lock);\n}\n#endif\n#else /* 2.4.23 => 2.4.22 */\n#define HAVE_SCTP\n#endif /* 2.4.23 => 2.4.22 */\n\n/*****************************************************************************/\n/* 2.6.4 => 2.6.0 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) || \\\n ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \\\n LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) )\n#define ETHTOOL_OPS_COMPAT\n#endif /* 2.6.4 => 2.6.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) )\n#define __user\n#endif /* < 2.4.27 */\n\n/*****************************************************************************/\n/* 2.5.71 => 2.4.x */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,71) )\n#define sk_protocol protocol\n#define pci_get_device pci_find_device\n#endif /* 2.5.70 => 2.4.x */\n\n/*****************************************************************************/\n/* < 2.4.27 or 2.6.0 <= 2.6.5 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) || \\\n ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \\\n LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) )\n\n#ifndef netif_msg_init\n#define netif_msg_init _kc_netif_msg_init\nstatic inline u32 _kc_netif_msg_init(int debug_value, int default_msg_enable_bits)\n{\n\t/* use default */\n\tif (debug_value < 0 || debug_value >= (sizeof(u32) * 8))\n\t\treturn default_msg_enable_bits;\n\tif (debug_value == 0) /* no output */\n\t\treturn 0;\n\t/* set low N bits */\n\treturn (1 << debug_value) -1;\n}\n#endif\n\n#endif /* < 2.4.27 or 2.6.0 <= 2.6.5 */\n/*****************************************************************************/\n#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \\\n (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \\\n ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) )))\n#define netdev_priv(x) x->priv\n#endif\n\n/*****************************************************************************/\n/* <= 2.5.0 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) )\n#include \n#undef pci_register_driver\n#define pci_register_driver pci_module_init\n\n/*\n * Most of the dma compat code is copied/modifed from the 2.4.37\n * /include/linux/libata-compat.h header file\n */\n/* These definitions mirror those in pci.h, so they can be used\n * interchangeably with their PCI_ counterparts */\nenum dma_data_direction {\n\tDMA_BIDIRECTIONAL = 0,\n\tDMA_TO_DEVICE = 1,\n\tDMA_FROM_DEVICE = 2,\n\tDMA_NONE = 3,\n};\n\nstruct device {\n\tstruct pci_dev pdev;\n};\n\nstatic inline struct pci_dev *to_pci_dev (struct device *dev)\n{\n\treturn (struct pci_dev *) dev;\n}\nstatic inline struct device *pci_dev_to_dev(struct pci_dev *pdev)\n{\n\treturn (struct device *) pdev;\n}\n\n#define pdev_printk(lvl, pdev, fmt, args...)\t\\\n\tprintk(\"%s %s: \" fmt, lvl, pci_name(pdev), ## args)\n#define dev_err(dev, fmt, args...) \\\n\tpdev_printk(KERN_ERR, to_pci_dev(dev), fmt, ## args)\n#define dev_info(dev, fmt, args...) \\\n\tpdev_printk(KERN_INFO, to_pci_dev(dev), fmt, ## args)\n#define dev_warn(dev, fmt, args...) \\\n\tpdev_printk(KERN_WARNING, to_pci_dev(dev), fmt, ## args)\n#define dev_notice(dev, fmt, args...) \\\n\tpdev_printk(KERN_NOTICE, to_pci_dev(dev), fmt, ## args)\n#define dev_dbg(dev, fmt, args...) \\\n\tpdev_printk(KERN_DEBUG, to_pci_dev(dev), fmt, ## args)\n\n/* NOTE: dangerous! we ignore the 'gfp' argument */\n#define dma_alloc_coherent(dev,sz,dma,gfp) \\\n\tpci_alloc_consistent(to_pci_dev(dev),(sz),(dma))\n#define dma_free_coherent(dev,sz,addr,dma_addr) \\\n\tpci_free_consistent(to_pci_dev(dev),(sz),(addr),(dma_addr))\n\n#define dma_map_page(dev,a,b,c,d) \\\n\tpci_map_page(to_pci_dev(dev),(a),(b),(c),(d))\n#define dma_unmap_page(dev,a,b,c) \\\n\tpci_unmap_page(to_pci_dev(dev),(a),(b),(c))\n\n#define dma_map_single(dev,a,b,c) \\\n\tpci_map_single(to_pci_dev(dev),(a),(b),(c))\n#define dma_unmap_single(dev,a,b,c) \\\n\tpci_unmap_single(to_pci_dev(dev),(a),(b),(c))\n\n#define dma_map_sg(dev, sg, nents, dir) \\\n\tpci_map_sg(to_pci_dev(dev), (sg), (nents), (dir)\n#define dma_unmap_sg(dev, sg, nents, dir) \\\n\tpci_unmap_sg(to_pci_dev(dev), (sg), (nents), (dir)\n\n#define dma_sync_single(dev,a,b,c) \\\n\tpci_dma_sync_single(to_pci_dev(dev),(a),(b),(c))\n\n/* for range just sync everything, that's all the pci API can do */\n#define dma_sync_single_range(dev,addr,off,sz,dir) \\\n\tpci_dma_sync_single(to_pci_dev(dev),(addr),(off)+(sz),(dir))\n\n#define dma_set_mask(dev,mask) \\\n\tpci_set_dma_mask(to_pci_dev(dev),(mask))\n\n/* hlist_* code - double linked lists */\nstruct hlist_head {\n\tstruct hlist_node *first;\n};\n\nstruct hlist_node {\n\tstruct hlist_node *next, **pprev;\n};\n\nstatic inline void __hlist_del(struct hlist_node *n)\n{\n\tstruct hlist_node *next = n->next;\n\tstruct hlist_node **pprev = n->pprev;\n\t*pprev = next;\n\tif (next)\n\tnext->pprev = pprev;\n}\n\nstatic inline void hlist_del(struct hlist_node *n)\n{\n\t__hlist_del(n);\n\tn->next = NULL;\n\tn->pprev = NULL;\n}\n\nstatic inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h)\n{\n\tstruct hlist_node *first = h->first;\n\tn->next = first;\n\tif (first)\n\t\tfirst->pprev = &n->next;\n\th->first = n;\n\tn->pprev = &h->first;\n}\n\nstatic inline int hlist_empty(const struct hlist_head *h)\n{\n\treturn !h->first;\n}\n#define HLIST_HEAD_INIT { .first = NULL }\n#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL }\n#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL)\nstatic inline void INIT_HLIST_NODE(struct hlist_node *h)\n{\n\th->next = NULL;\n\th->pprev = NULL;\n}\n\n#ifndef might_sleep\n#define might_sleep()\n#endif\n#else\nstatic inline struct device *pci_dev_to_dev(struct pci_dev *pdev)\n{\n\treturn &pdev->dev;\n}\n#endif /* <= 2.5.0 */\n\n/*****************************************************************************/\n/* 2.5.28 => 2.4.23 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) )\n\n#include \n#define work_struct tq_struct\n#undef INIT_WORK\n#define INIT_WORK(a,b) INIT_TQUEUE(a,(void (*)(void *))b,a)\n#undef container_of\n#define container_of list_entry\n#define schedule_work schedule_task\n#define flush_scheduled_work flush_scheduled_tasks\n#define cancel_work_sync(x) flush_scheduled_work()\n\n#endif /* 2.5.28 => 2.4.17 */\n\n/*****************************************************************************/\n/* 2.6.0 => 2.5.28 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )\n#ifndef read_barrier_depends\n#define read_barrier_depends() rmb()\n#endif\n\n#undef get_cpu\n#define get_cpu() smp_processor_id()\n#undef put_cpu\n#define put_cpu() do { } while(0)\n#define MODULE_INFO(version, _version)\n#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT\n#define CONFIG_E1000_DISABLE_PACKET_SPLIT 1\n#endif\n#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT\n#define CONFIG_IGB_DISABLE_PACKET_SPLIT 1\n#endif\n\n#define dma_set_coherent_mask(dev,mask) 1\n\n#undef dev_put\n#define dev_put(dev) __dev_put(dev)\n\n#ifndef skb_fill_page_desc\n#define skb_fill_page_desc _kc_skb_fill_page_desc\nextern void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size);\n#endif\n\n#undef ALIGN\n#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1))\n\n#ifndef page_count\n#define page_count(p) atomic_read(&(p)->count)\n#endif\n\n#ifdef MAX_NUMNODES\n#undef MAX_NUMNODES\n#endif\n#define MAX_NUMNODES 1\n\n/* find_first_bit and find_next bit are not defined for most\n * 2.4 kernels (except for the redhat 2.4.21 kernels\n */\n#include \n#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)\n#undef find_next_bit\n#define find_next_bit _kc_find_next_bit\nextern unsigned long _kc_find_next_bit(const unsigned long *addr,\n unsigned long size,\n unsigned long offset);\n#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)\n\n\n#ifndef netdev_name\nstatic inline const char *_kc_netdev_name(const struct net_device *dev)\n{\n\tif (strchr(dev->name, '%'))\n\t\treturn \"(unregistered net_device)\";\n\treturn dev->name;\n}\n#define netdev_name(netdev)\t_kc_netdev_name(netdev)\n#endif /* netdev_name */\n\n#ifndef strlcpy\n#define strlcpy _kc_strlcpy\nextern size_t _kc_strlcpy(char *dest, const char *src, size_t size);\n#endif /* strlcpy */\n\n#ifndef do_div\n#if BITS_PER_LONG == 64\n# define do_div(n,base) ({\t\t\t\t\t\\\n\tuint32_t __base = (base);\t\t\t\t\\\n\tuint32_t __rem;\t\t\t\t\t\t\\\n\t__rem = ((uint64_t)(n)) % __base;\t\t\t\\\n\t(n) = ((uint64_t)(n)) / __base;\t\t\t\t\\\n\t__rem;\t\t\t\t\t\t\t\\\n })\n#elif BITS_PER_LONG == 32\nextern uint32_t _kc__div64_32(uint64_t *dividend, uint32_t divisor);\n# define do_div(n,base) ({\t\t\t\t\\\n\tuint32_t __base = (base);\t\t\t\\\n\tuint32_t __rem;\t\t\t\t\t\\\n\tif (likely(((n) >> 32) == 0)) {\t\t\t\\\n\t\t__rem = (uint32_t)(n) % __base;\t\t\\\n\t\t(n) = (uint32_t)(n) / __base;\t\t\\\n\t} else \t\t\t\t\t\t\\\n\t\t__rem = _kc__div64_32(&(n), __base);\t\\\n\t__rem;\t\t\t\t\t\t\\\n })\n#else /* BITS_PER_LONG == ?? */\n# error do_div() does not yet support the C64\n#endif /* BITS_PER_LONG */\n#endif /* do_div */\n\n#ifndef NSEC_PER_SEC\n#define NSEC_PER_SEC\t1000000000L\n#endif\n\n#undef HAVE_I2C_SUPPORT\n#else /* 2.6.0 */\n#if IS_ENABLED(CONFIG_I2C_ALGOBIT) && \\\n\t(RHEL_RELEASE_CODE && (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,9)))\n#define HAVE_I2C_SUPPORT\n#endif /* IS_ENABLED(CONFIG_I2C_ALGOBIT) */\n\n#endif /* 2.6.0 => 2.5.28 */\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) )\n#define dma_pool pci_pool\n#define dma_pool_destroy pci_pool_destroy\n#define dma_pool_alloc pci_pool_alloc\n#define dma_pool_free pci_pool_free\n\n#define dma_pool_create(name,dev,size,align,allocation) \\\n pci_pool_create((name),to_pci_dev(dev),(size),(align),(allocation))\n#endif /* < 2.6.3 */\n\n/*****************************************************************************/\n/* 2.6.4 => 2.6.0 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) )\n#define MODULE_VERSION(_version) MODULE_INFO(version, _version)\n#endif /* 2.6.4 => 2.6.0 */\n\n/*****************************************************************************/\n/* 2.6.5 => 2.6.0 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) )\n#define dma_sync_single_for_cpu\t\tdma_sync_single\n#define dma_sync_single_for_device\tdma_sync_single\n#define dma_sync_single_range_for_cpu\t\tdma_sync_single_range\n#define dma_sync_single_range_for_device\tdma_sync_single_range\n#ifndef pci_dma_mapping_error\n#define pci_dma_mapping_error _kc_pci_dma_mapping_error\nstatic inline int _kc_pci_dma_mapping_error(dma_addr_t dma_addr)\n{\n\treturn dma_addr == 0;\n}\n#endif\n#endif /* 2.6.5 => 2.6.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) )\nextern int _kc_scnprintf(char * buf, size_t size, const char *fmt, ...);\n#define scnprintf(buf, size, fmt, args...) _kc_scnprintf(buf, size, fmt, ##args)\n#endif /* < 2.6.4 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,6) )\n/* taken from 2.6 include/linux/bitmap.h */\n#undef bitmap_zero\n#define bitmap_zero _kc_bitmap_zero\nstatic inline void _kc_bitmap_zero(unsigned long *dst, int nbits)\n{\n if (nbits <= BITS_PER_LONG)\n *dst = 0UL;\n else {\n int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);\n memset(dst, 0, len);\n }\n}\n#define random_ether_addr _kc_random_ether_addr\nstatic inline void _kc_random_ether_addr(u8 *addr)\n{\n get_random_bytes(addr, ETH_ALEN);\n addr[0] &= 0xfe; /* clear multicast */\n addr[0] |= 0x02; /* set local assignment */\n}\n#define page_to_nid(x) 0\n\n#endif /* < 2.6.6 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) )\n#undef if_mii\n#define if_mii _kc_if_mii\nstatic inline struct mii_ioctl_data *_kc_if_mii(struct ifreq *rq)\n{\n\treturn (struct mii_ioctl_data *) &rq->ifr_ifru;\n}\n\n#ifndef __force\n#define __force\n#endif\n#endif /* < 2.6.7 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) )\n#ifndef PCI_EXP_DEVCTL\n#define PCI_EXP_DEVCTL 8\n#endif\n#ifndef PCI_EXP_DEVCTL_CERE\n#define PCI_EXP_DEVCTL_CERE 0x0001\n#endif\n#define PCI_EXP_FLAGS\t\t2\t/* Capabilities register */\n#define PCI_EXP_FLAGS_VERS\t0x000f\t/* Capability version */\n#define PCI_EXP_FLAGS_TYPE\t0x00f0\t/* Device/Port type */\n#define PCI_EXP_TYPE_ENDPOINT\t0x0\t/* Express Endpoint */\n#define PCI_EXP_TYPE_LEG_END\t0x1\t/* Legacy Endpoint */\n#define PCI_EXP_TYPE_ROOT_PORT 0x4\t/* Root Port */\n#define PCI_EXP_TYPE_DOWNSTREAM 0x6\t/* Downstream Port */\n#define PCI_EXP_FLAGS_SLOT\t0x0100\t/* Slot implemented */\n#define PCI_EXP_DEVCAP\t\t4\t/* Device capabilities */\n#define PCI_EXP_DEVSTA\t\t10\t/* Device Status */\n#define msleep(x)\tdo { set_current_state(TASK_UNINTERRUPTIBLE); \\\n\t\t\t\tschedule_timeout((x * HZ)/1000 + 2); \\\n\t\t\t} while (0)\n\n#endif /* < 2.6.8 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))\n#include \n#define __iomem\n\n#ifndef kcalloc\n#define kcalloc(n, size, flags) _kc_kzalloc(((n) * (size)), flags)\nextern void *_kc_kzalloc(size_t size, int flags);\n#endif\n#define MSEC_PER_SEC 1000L\nstatic inline unsigned int _kc_jiffies_to_msecs(const unsigned long j)\n{\n#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)\n\treturn (MSEC_PER_SEC / HZ) * j;\n#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)\n\treturn (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC);\n#else\n\treturn (j * MSEC_PER_SEC) / HZ;\n#endif\n}\nstatic inline unsigned long _kc_msecs_to_jiffies(const unsigned int m)\n{\n\tif (m > _kc_jiffies_to_msecs(MAX_JIFFY_OFFSET))\n\t\treturn MAX_JIFFY_OFFSET;\n#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)\n\treturn (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ);\n#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)\n\treturn m * (HZ / MSEC_PER_SEC);\n#else\n\treturn (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC;\n#endif\n}\n\n#define msleep_interruptible _kc_msleep_interruptible\nstatic inline unsigned long _kc_msleep_interruptible(unsigned int msecs)\n{\n\tunsigned long timeout = _kc_msecs_to_jiffies(msecs) + 1;\n\n\twhile (timeout && !signal_pending(current)) {\n\t\t__set_current_state(TASK_INTERRUPTIBLE);\n\t\ttimeout = schedule_timeout(timeout);\n\t}\n\treturn _kc_jiffies_to_msecs(timeout);\n}\n\n/* Basic mode control register. */\n#define BMCR_SPEED1000\t\t0x0040 /* MSB of Speed (1000) */\n\n#ifndef __le16\n#define __le16 u16\n#endif\n#ifndef __le32\n#define __le32 u32\n#endif\n#ifndef __le64\n#define __le64 u64\n#endif\n#ifndef __be16\n#define __be16 u16\n#endif\n#ifndef __be32\n#define __be32 u32\n#endif\n#ifndef __be64\n#define __be64 u64\n#endif\n\nstatic inline struct vlan_ethhdr *vlan_eth_hdr(const struct sk_buff *skb)\n{\n\treturn (struct vlan_ethhdr *)skb->mac.raw;\n}\n\n/* Wake-On-Lan options. */\n#define WAKE_PHY\t\t(1 << 0)\n#define WAKE_UCAST\t\t(1 << 1)\n#define WAKE_MCAST\t\t(1 << 2)\n#define WAKE_BCAST\t\t(1 << 3)\n#define WAKE_ARP\t\t(1 << 4)\n#define WAKE_MAGIC\t\t(1 << 5)\n#define WAKE_MAGICSECURE\t(1 << 6) /* only meaningful if WAKE_MAGIC */\n\n#define skb_header_pointer _kc_skb_header_pointer\nstatic inline void *_kc_skb_header_pointer(const struct sk_buff *skb,\n\t\t\t\t\t int offset, int len, void *buffer)\n{\n\tint hlen = skb_headlen(skb);\n\n\tif (hlen - offset >= len)\n\t\treturn skb->data + offset;\n\n#ifdef MAX_SKB_FRAGS\n\tif (skb_copy_bits(skb, offset, buffer, len) < 0)\n\t\treturn NULL;\n\n\treturn buffer;\n#else\n\treturn NULL;\n#endif\n\n#ifndef NETDEV_TX_OK\n#define NETDEV_TX_OK 0\n#endif\n#ifndef NETDEV_TX_BUSY\n#define NETDEV_TX_BUSY 1\n#endif\n#ifndef NETDEV_TX_LOCKED\n#define NETDEV_TX_LOCKED -1\n#endif\n}\n\n#ifndef __bitwise\n#define __bitwise\n#endif\n#endif /* < 2.6.9 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) )\n#ifdef module_param_array_named\n#undef module_param_array_named\n#define module_param_array_named(name, array, type, nump, perm) \\\n\tstatic struct kparam_array __param_arr_##name \\\n\t= { ARRAY_SIZE(array), nump, param_set_##type, param_get_##type, \\\n\t sizeof(array[0]), array }; \\\n\tmodule_param_call(name, param_array_set, param_array_get, \\\n\t\t\t &__param_arr_##name, perm)\n#endif /* module_param_array_named */\n/*\n * num_online is broken for all < 2.6.10 kernels. This is needed to support\n * Node module parameter of ixgbe.\n */\n#undef num_online_nodes\n#define num_online_nodes(n) 1\nextern DECLARE_BITMAP(_kcompat_node_online_map, MAX_NUMNODES);\n#undef node_online_map\n#define node_online_map _kcompat_node_online_map\n#define pci_get_class pci_find_class\n#endif /* < 2.6.10 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) )\n#define PCI_D0 0\n#define PCI_D1 1\n#define PCI_D2 2\n#define PCI_D3hot 3\n#define PCI_D3cold 4\ntypedef int pci_power_t;\n#define pci_choose_state(pdev,state) state\n#define PMSG_SUSPEND 3\n#define PCI_EXP_LNKCTL\t16\n\n#undef NETIF_F_LLTX\n\n#ifndef ARCH_HAS_PREFETCH\n#define prefetch(X)\n#endif\n\n#ifndef NET_IP_ALIGN\n#define NET_IP_ALIGN 2\n#endif\n\n#define KC_USEC_PER_SEC\t1000000L\n#define usecs_to_jiffies _kc_usecs_to_jiffies\nstatic inline unsigned int _kc_jiffies_to_usecs(const unsigned long j)\n{\n#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ)\n\treturn (KC_USEC_PER_SEC / HZ) * j;\n#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC)\n\treturn (j + (HZ / KC_USEC_PER_SEC) - 1)/(HZ / KC_USEC_PER_SEC);\n#else\n\treturn (j * KC_USEC_PER_SEC) / HZ;\n#endif\n}\nstatic inline unsigned long _kc_usecs_to_jiffies(const unsigned int m)\n{\n\tif (m > _kc_jiffies_to_usecs(MAX_JIFFY_OFFSET))\n\t\treturn MAX_JIFFY_OFFSET;\n#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ)\n\treturn (m + (KC_USEC_PER_SEC / HZ) - 1) / (KC_USEC_PER_SEC / HZ);\n#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC)\n\treturn m * (HZ / KC_USEC_PER_SEC);\n#else\n\treturn (m * HZ + KC_USEC_PER_SEC - 1) / KC_USEC_PER_SEC;\n#endif\n}\n\n#define PCI_EXP_LNKCAP\t\t12\t/* Link Capabilities */\n#define PCI_EXP_LNKSTA\t\t18\t/* Link Status */\n#define PCI_EXP_SLTCAP\t\t20\t/* Slot Capabilities */\n#define PCI_EXP_SLTCTL\t\t24\t/* Slot Control */\n#define PCI_EXP_SLTSTA\t\t26\t/* Slot Status */\n#define PCI_EXP_RTCTL\t\t28\t/* Root Control */\n#define PCI_EXP_RTCAP\t\t30\t/* Root Capabilities */\n#define PCI_EXP_RTSTA\t\t32\t/* Root Status */\n#endif /* < 2.6.11 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,12) )\n#include \n#define USE_REBOOT_NOTIFIER\n\n/* Generic MII registers. */\n#define MII_CTRL1000 0x09 /* 1000BASE-T control */\n#define MII_STAT1000 0x0a /* 1000BASE-T status */\n/* Advertisement control register. */\n#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */\n#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymmetric pause */\n/* Link partner ability register. */\n#define LPA_PAUSE_CAP\t\t0x0400\t/* Can pause */\n#define LPA_PAUSE_ASYM\t\t0x0800\t/* Can pause asymetrically */\n/* 1000BASE-T Control register */\n#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */\n#define ADVERTISE_1000HALF\t0x0100 /* Advertise 1000BASE-T half duplex */\n/* 1000BASE-T Status register */\n#define LPA_1000LOCALRXOK\t0x2000\t/* Link partner local receiver status */\n#define LPA_1000REMRXOK\t\t0x1000\t/* Link partner remote receiver status */\n\n#ifndef is_zero_ether_addr\n#define is_zero_ether_addr _kc_is_zero_ether_addr\nstatic inline int _kc_is_zero_ether_addr(const u8 *addr)\n{\n\treturn !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);\n}\n#endif /* is_zero_ether_addr */\n#ifndef is_multicast_ether_addr\n#define is_multicast_ether_addr _kc_is_multicast_ether_addr\nstatic inline int _kc_is_multicast_ether_addr(const u8 *addr)\n{\n\treturn addr[0] & 0x01;\n}\n#endif /* is_multicast_ether_addr */\n#endif /* < 2.6.12 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) )\n#ifndef kstrdup\n#define kstrdup _kc_kstrdup\nextern char *_kc_kstrdup(const char *s, unsigned int gfp);\n#endif\n#endif /* < 2.6.13 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) )\n#define pm_message_t u32\n#ifndef kzalloc\n#define kzalloc _kc_kzalloc\nextern void *_kc_kzalloc(size_t size, int flags);\n#endif\n\n/* Generic MII registers. */\n#define MII_ESTATUS\t 0x0f\t/* Extended Status */\n/* Basic mode status register. */\n#define BMSR_ESTATEN\t\t0x0100\t/* Extended Status in R15 */\n/* Extended status register. */\n#define ESTATUS_1000_TFULL\t0x2000\t/* Can do 1000BT Full */\n#define ESTATUS_1000_THALF\t0x1000\t/* Can do 1000BT Half */\n\n#define SUPPORTED_Pause\t (1 << 13)\n#define SUPPORTED_Asym_Pause\t(1 << 14)\n#define ADVERTISED_Pause\t(1 << 13)\n#define ADVERTISED_Asym_Pause\t(1 << 14)\n\n#if (!(RHEL_RELEASE_CODE && \\\n (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,3)) && \\\n (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0))))\n#if ((LINUX_VERSION_CODE == KERNEL_VERSION(2,6,9)) && !defined(gfp_t))\n#define gfp_t unsigned\n#else\ntypedef unsigned gfp_t;\n#endif\n#endif /* !RHEL4.3->RHEL5.0 */\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,9) )\n#ifdef CONFIG_X86_64\n#define dma_sync_single_range_for_cpu(dev, addr, off, sz, dir) \\\n\tdma_sync_single_for_cpu((dev), (addr), (off) + (sz), (dir))\n#define dma_sync_single_range_for_device(dev, addr, off, sz, dir) \\\n\tdma_sync_single_for_device((dev), (addr), (off) + (sz), (dir))\n#endif\n#endif\n#endif /* < 2.6.14 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) )\n#ifndef vmalloc_node\n#define vmalloc_node(a,b) vmalloc(a)\n#endif /* vmalloc_node*/\n\n#define setup_timer(_timer, _function, _data) \\\ndo { \\\n\t(_timer)->function = _function; \\\n\t(_timer)->data = _data; \\\n\tinit_timer(_timer); \\\n} while (0)\n#ifndef device_can_wakeup\n#define device_can_wakeup(dev)\t(1)\n#endif\n#ifndef device_set_wakeup_enable\n#define device_set_wakeup_enable(dev, val)\tdo{}while(0)\n#endif\n#ifndef device_init_wakeup\n#define device_init_wakeup(dev,val) do {} while (0)\n#endif\nstatic inline unsigned _kc_compare_ether_addr(const u8 *addr1, const u8 *addr2)\n{\n\tconst u16 *a = (const u16 *) addr1;\n\tconst u16 *b = (const u16 *) addr2;\n\n\treturn ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0;\n}\n#undef compare_ether_addr\n#define compare_ether_addr(addr1, addr2) _kc_compare_ether_addr(addr1, addr2)\n#endif /* < 2.6.15 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) )\n#undef DEFINE_MUTEX\n#define DEFINE_MUTEX(x)\tDECLARE_MUTEX(x)\n#define mutex_lock(x)\tdown_interruptible(x)\n#define mutex_unlock(x)\tup(x)\n\n#ifndef ____cacheline_internodealigned_in_smp\n#ifdef CONFIG_SMP\n#define ____cacheline_internodealigned_in_smp ____cacheline_aligned_in_smp\n#else\n#define ____cacheline_internodealigned_in_smp\n#endif /* CONFIG_SMP */\n#endif /* ____cacheline_internodealigned_in_smp */\n#undef HAVE_PCI_ERS\n#else /* 2.6.16 and above */\n#undef HAVE_PCI_ERS\n#define HAVE_PCI_ERS\n#if ( SLE_VERSION_CODE && SLE_VERSION_CODE == SLE_VERSION(10,4,0) )\n#ifdef device_can_wakeup\n#undef device_can_wakeup\n#endif /* device_can_wakeup */\n#define device_can_wakeup(dev) 1\n#endif /* SLE_VERSION(10,4,0) */\n#endif /* < 2.6.16 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17) )\n#ifndef dev_notice\n#define dev_notice(dev, fmt, args...) \\\n\tdev_printk(KERN_NOTICE, dev, fmt, ## args)\n#endif\n\n#ifndef first_online_node\n#define first_online_node 0\n#endif\n#ifndef NET_SKB_PAD\n#define NET_SKB_PAD 16\n#endif\n#endif /* < 2.6.17 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) )\n\n#ifndef IRQ_HANDLED\n#define irqreturn_t void\n#define IRQ_HANDLED\n#define IRQ_NONE\n#endif\n\n#ifndef IRQF_PROBE_SHARED\n#ifdef SA_PROBEIRQ\n#define IRQF_PROBE_SHARED SA_PROBEIRQ\n#else\n#define IRQF_PROBE_SHARED 0\n#endif\n#endif\n\n#ifndef IRQF_SHARED\n#define IRQF_SHARED SA_SHIRQ\n#endif\n\n#ifndef ARRAY_SIZE\n#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))\n#endif\n\n#ifndef FIELD_SIZEOF\n#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))\n#endif\n\n#ifndef skb_is_gso\n#ifdef NETIF_F_TSO\n#define skb_is_gso _kc_skb_is_gso\nstatic inline int _kc_skb_is_gso(const struct sk_buff *skb)\n{\n\treturn skb_shinfo(skb)->gso_size;\n}\n#else\n#define skb_is_gso(a) 0\n#endif\n#endif\n\n#ifndef resource_size_t\n#define resource_size_t unsigned long\n#endif\n\n#ifdef skb_pad\n#undef skb_pad\n#endif\n#define skb_pad(x,y) _kc_skb_pad(x, y)\nint _kc_skb_pad(struct sk_buff *skb, int pad);\n#ifdef skb_padto\n#undef skb_padto\n#endif\n#define skb_padto(x,y) _kc_skb_padto(x, y)\nstatic inline int _kc_skb_padto(struct sk_buff *skb, unsigned int len)\n{\n\tunsigned int size = skb->len;\n\tif(likely(size >= len))\n\t\treturn 0;\n\treturn _kc_skb_pad(skb, len - size);\n}\n\n#ifndef DECLARE_PCI_UNMAP_ADDR\n#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \\\n\tdma_addr_t ADDR_NAME\n#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \\\n\tu32 LEN_NAME\n#define pci_unmap_addr(PTR, ADDR_NAME) \\\n\t((PTR)->ADDR_NAME)\n#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \\\n\t(((PTR)->ADDR_NAME) = (VAL))\n#define pci_unmap_len(PTR, LEN_NAME) \\\n\t((PTR)->LEN_NAME)\n#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \\\n\t(((PTR)->LEN_NAME) = (VAL))\n#endif /* DECLARE_PCI_UNMAP_ADDR */\n#endif /* < 2.6.18 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) )\n\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,0)))\n#define i_private u.generic_ip\n#endif /* >= RHEL 5.0 */\n\n#ifndef DIV_ROUND_UP\n#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))\n#endif\n#ifndef __ALIGN_MASK\n#define __ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))\n#endif\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) )\n#if (!((RHEL_RELEASE_CODE && \\\n ((RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,4) && \\\n RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0)) || \\\n (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,0))))))\ntypedef irqreturn_t (*irq_handler_t)(int, void*, struct pt_regs *);\n#endif\n#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0))\n#undef CONFIG_INET_LRO\n#undef CONFIG_INET_LRO_MODULE\n#ifdef IXGBE_FCOE\n#undef CONFIG_FCOE\n#undef CONFIG_FCOE_MODULE\n#endif /* IXGBE_FCOE */\n#endif\ntypedef irqreturn_t (*new_handler_t)(int, void*);\nstatic inline irqreturn_t _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id)\n#else /* 2.4.x */\ntypedef void (*irq_handler_t)(int, void*, struct pt_regs *);\ntypedef void (*new_handler_t)(int, void*);\nstatic inline int _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id)\n#endif /* >= 2.5.x */\n{\n\tirq_handler_t new_handler = (irq_handler_t) handler;\n\treturn request_irq(irq, new_handler, flags, devname, dev_id);\n}\n\n#undef request_irq\n#define request_irq(irq, handler, flags, devname, dev_id) _kc_request_irq((irq), (handler), (flags), (devname), (dev_id))\n\n#define irq_handler_t new_handler_t\n/* pci_restore_state and pci_save_state handles MSI/PCIE from 2.6.19 */\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,4)))\n#define PCIE_CONFIG_SPACE_LEN 256\n#define PCI_CONFIG_SPACE_LEN 64\n#define PCIE_LINK_STATUS 0x12\n#define pci_config_space_ich8lan() do {} while(0)\n#undef pci_save_state\nextern int _kc_pci_save_state(struct pci_dev *);\n#define pci_save_state(pdev) _kc_pci_save_state(pdev)\n#undef pci_restore_state\nextern void _kc_pci_restore_state(struct pci_dev *);\n#define pci_restore_state(pdev) _kc_pci_restore_state(pdev)\n#endif /* !(RHEL_RELEASE_CODE >= RHEL 5.4) */\n\n#ifdef HAVE_PCI_ERS\n#undef free_netdev\nextern void _kc_free_netdev(struct net_device *);\n#define free_netdev(netdev) _kc_free_netdev(netdev)\n#endif\nstatic inline int pci_enable_pcie_error_reporting(struct pci_dev *dev)\n{\n\treturn 0;\n}\n#define pci_disable_pcie_error_reporting(dev) do {} while (0)\n#define pci_cleanup_aer_uncorrect_error_status(dev) do {} while (0)\n\nextern void *_kc_kmemdup(const void *src, size_t len, unsigned gfp);\n#define kmemdup(src, len, gfp) _kc_kmemdup(src, len, gfp)\n#ifndef bool\n#define bool _Bool\n#define true 1\n#define false 0\n#endif\n#else /* 2.6.19 */\n#include \n#include \n#endif /* < 2.6.19 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) )\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) )\n#undef INIT_WORK\n#define INIT_WORK(_work, _func) \\\ndo { \\\n\tINIT_LIST_HEAD(&(_work)->entry); \\\n\t(_work)->pending = 0; \\\n\t(_work)->func = (void (*)(void *))_func; \\\n\t(_work)->data = _work; \\\n\tinit_timer(&(_work)->timer); \\\n} while (0)\n#endif\n\n#ifndef PCI_VDEVICE\n#define PCI_VDEVICE(ven, dev) \\\n\tPCI_VENDOR_ID_##ven, (dev), \\\n\tPCI_ANY_ID, PCI_ANY_ID, 0, 0\n#endif\n\n#ifndef PCI_VENDOR_ID_INTEL\n#define PCI_VENDOR_ID_INTEL 0x8086\n#endif\n\n#ifndef round_jiffies\n#define round_jiffies(x) x\n#endif\n\n#define csum_offset csum\n\n#define HAVE_EARLY_VMALLOC_NODE\n#define dev_to_node(dev) -1\n#undef set_dev_node\n/* remove compiler warning with b=b, for unused variable */\n#define set_dev_node(a, b) do { (b) = (b); } while(0)\n\n#if (!(RHEL_RELEASE_CODE && \\\n (((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(4,7)) && \\\n (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0))) || \\\n (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,6)))) && \\\n !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10,2,0)))\ntypedef __u16 __bitwise __sum16;\ntypedef __u32 __bitwise __wsum;\n#endif\n\n#if (!(RHEL_RELEASE_CODE && \\\n (((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(4,7)) && \\\n (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0))) || \\\n (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,4)))) && \\\n !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10,2,0)))\nstatic inline __wsum csum_unfold(__sum16 n)\n{\n\treturn (__force __wsum)n;\n}\n#endif\n\n#else /* < 2.6.20 */\n#define HAVE_DEVICE_NUMA_NODE\n#endif /* < 2.6.20 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) )\n#define to_net_dev(class) container_of(class, struct net_device, class_dev)\n#define NETDEV_CLASS_DEV\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,5)))\n#define vlan_group_get_device(vg, id) (vg->vlan_devices[id])\n#define vlan_group_set_device(vg, id, dev)\t\t\\\n\tdo {\t\t\t\t\t\t\\\n\t\tif (vg) vg->vlan_devices[id] = dev;\t\\\n\t} while (0)\n#endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,5)) */\n#define pci_channel_offline(pdev) (pdev->error_state && \\\n\tpdev->error_state != pci_channel_io_normal)\n#define pci_request_selected_regions(pdev, bars, name) \\\n pci_request_regions(pdev, name)\n#define pci_release_selected_regions(pdev, bars) pci_release_regions(pdev);\n\n#ifndef __aligned\n#define __aligned(x)\t\t\t__attribute__((aligned(x)))\n#endif\n\nextern struct pci_dev *_kc_netdev_to_pdev(struct net_device *netdev);\n#define netdev_to_dev(netdev)\t\\\n\tpci_dev_to_dev(_kc_netdev_to_pdev(netdev))\n#else\nstatic inline struct device *netdev_to_dev(struct net_device *netdev)\n{\n\treturn &netdev->dev;\n}\n\n#endif /* < 2.6.21 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) )\n#define tcp_hdr(skb) (skb->h.th)\n#define tcp_hdrlen(skb) (skb->h.th->doff << 2)\n#define skb_transport_offset(skb) (skb->h.raw - skb->data)\n#define skb_transport_header(skb) (skb->h.raw)\n#define ipv6_hdr(skb) (skb->nh.ipv6h)\n#define ip_hdr(skb) (skb->nh.iph)\n#define skb_network_offset(skb) (skb->nh.raw - skb->data)\n#define skb_network_header(skb) (skb->nh.raw)\n#define skb_tail_pointer(skb) skb->tail\n#define skb_reset_tail_pointer(skb) \\\n\tdo { \\\n\t\tskb->tail = skb->data; \\\n\t} while (0)\n#define skb_set_tail_pointer(skb, offset) \\\n\tdo { \\\n\t\tskb->tail = skb->data + offset; \\\n\t} while (0)\n#define skb_copy_to_linear_data(skb, from, len) \\\n\t\t\t\tmemcpy(skb->data, from, len)\n#define skb_copy_to_linear_data_offset(skb, offset, from, len) \\\n\t\t\t\tmemcpy(skb->data + offset, from, len)\n#define skb_network_header_len(skb) (skb->h.raw - skb->nh.raw)\n#define pci_register_driver pci_module_init\n#define skb_mac_header(skb) skb->mac.raw\n\n#ifdef NETIF_F_MULTI_QUEUE\n#ifndef alloc_etherdev_mq\n#define alloc_etherdev_mq(_a, _b) alloc_etherdev(_a)\n#endif\n#endif /* NETIF_F_MULTI_QUEUE */\n\n#ifndef ETH_FCS_LEN\n#define ETH_FCS_LEN 4\n#endif\n#define cancel_work_sync(x) flush_scheduled_work()\n#ifndef udp_hdr\n#define udp_hdr _udp_hdr\nstatic inline struct udphdr *_udp_hdr(const struct sk_buff *skb)\n{\n\treturn (struct udphdr *)skb_transport_header(skb);\n}\n#endif\n\n#ifdef cpu_to_be16\n#undef cpu_to_be16\n#endif\n#define cpu_to_be16(x) __constant_htons(x)\n\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,1)))\nenum {\n\tDUMP_PREFIX_NONE,\n\tDUMP_PREFIX_ADDRESS,\n\tDUMP_PREFIX_OFFSET\n};\n#endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,1)) */\n#ifndef hex_asc\n#define hex_asc(x)\t\"0123456789abcdef\"[x]\n#endif\n#include \nextern void _kc_print_hex_dump(const char *level, const char *prefix_str,\n\t\t\t int prefix_type, int rowsize, int groupsize,\n\t\t\t const void *buf, size_t len, bool ascii);\n#define print_hex_dump(lvl, s, t, r, g, b, l, a) \\\n\t\t_kc_print_hex_dump(lvl, s, t, r, g, b, l, a)\n#ifndef ADVERTISED_2500baseX_Full\n#define ADVERTISED_2500baseX_Full (1 << 15)\n#endif\n#ifndef SUPPORTED_2500baseX_Full\n#define SUPPORTED_2500baseX_Full (1 << 15)\n#endif\n\n#ifdef HAVE_I2C_SUPPORT\n#include \n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,5)))\nstruct i2c_board_info {\n\tchar\tdriver_name[KOBJ_NAME_LEN];\n\tchar\ttype[I2C_NAME_SIZE];\n\tunsigned short\tflags;\n\tunsigned short\taddr;\n\tvoid\t\t*platform_data;\n};\n#define I2C_BOARD_INFO(driver, dev_addr) .driver_name = (driver),\\\n\t\t\t.addr = (dev_addr)\n#endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,5)) */\n#define i2c_new_device(adap, info) _kc_i2c_new_device(adap, info)\nextern struct i2c_client *\n_kc_i2c_new_device(struct i2c_adapter *adap, struct i2c_board_info const *info);\n#endif /* HAVE_I2C_SUPPORT */\n\n#else /* 2.6.22 */\n#define ETH_TYPE_TRANS_SETS_DEV\n#define HAVE_NETDEV_STATS_IN_NETDEV\n#endif /* < 2.6.22 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) )\n#undef SET_MODULE_OWNER\n#define SET_MODULE_OWNER(dev) do { } while (0)\n#endif /* > 2.6.22 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) )\n#define netif_subqueue_stopped(_a, _b) 0\n#ifndef PTR_ALIGN\n#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))\n#endif\n\n#ifndef CONFIG_PM_SLEEP\n#define CONFIG_PM_SLEEP\tCONFIG_PM\n#endif\n\n#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) )\n#define HAVE_ETHTOOL_GET_PERM_ADDR\n#endif /* 2.6.14 through 2.6.22 */\n#endif /* < 2.6.23 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) )\n#ifndef ETH_FLAG_LRO\n#define ETH_FLAG_LRO NETIF_F_LRO\n#endif\n\n/* if GRO is supported then the napi struct must already exist */\n#ifndef NETIF_F_GRO\n/* NAPI API changes in 2.6.24 break everything */\nstruct napi_struct {\n\t/* used to look up the real NAPI polling routine */\n\tint (*poll)(struct napi_struct *, int);\n\tstruct net_device *dev;\n\tint weight;\n};\n#endif\n\n#ifdef NAPI\nextern int __kc_adapter_clean(struct net_device *, int *);\nextern struct net_device *napi_to_poll_dev(const struct napi_struct *napi);\n#define netif_napi_add(_netdev, _napi, _poll, _weight) \\\n\tdo { \\\n\t\tstruct napi_struct *__napi = (_napi); \\\n\t\tstruct net_device *poll_dev = napi_to_poll_dev(__napi); \\\n\t\tpoll_dev->poll = &(__kc_adapter_clean); \\\n\t\tpoll_dev->priv = (_napi); \\\n\t\tpoll_dev->weight = (_weight); \\\n\t\tset_bit(__LINK_STATE_RX_SCHED, &poll_dev->state); \\\n\t\tset_bit(__LINK_STATE_START, &poll_dev->state);\\\n\t\tdev_hold(poll_dev); \\\n\t\t__napi->poll = &(_poll); \\\n\t\t__napi->weight = (_weight); \\\n\t\t__napi->dev = (_netdev); \\\n\t} while (0)\n#define netif_napi_del(_napi) \\\n\tdo { \\\n\t\tstruct net_device *poll_dev = napi_to_poll_dev(_napi); \\\n\t\tWARN_ON(!test_bit(__LINK_STATE_RX_SCHED, &poll_dev->state)); \\\n\t\tdev_put(poll_dev); \\\n\t\tmemset(poll_dev, 0, sizeof(struct net_device));\\\n\t} while (0)\n#define napi_schedule_prep(_napi) \\\n\t(netif_running((_napi)->dev) && netif_rx_schedule_prep(napi_to_poll_dev(_napi)))\n#define napi_schedule(_napi) \\\n\tdo { \\\n\t\tif (napi_schedule_prep(_napi)) \\\n\t\t\t__netif_rx_schedule(napi_to_poll_dev(_napi)); \\\n\t} while (0)\n#define napi_enable(_napi) netif_poll_enable(napi_to_poll_dev(_napi))\n#define napi_disable(_napi) netif_poll_disable(napi_to_poll_dev(_napi))\n#ifdef CONFIG_SMP\nstatic inline void napi_synchronize(const struct napi_struct *n)\n{\n\tstruct net_device *dev = napi_to_poll_dev(n);\n\n\twhile (test_bit(__LINK_STATE_RX_SCHED, &dev->state)) {\n\t\t/* No hurry. */\n\t\tmsleep(1);\n\t}\n}\n#else\n#define napi_synchronize(n)\tbarrier()\n#endif /* CONFIG_SMP */\n#define __napi_schedule(_napi) __netif_rx_schedule(napi_to_poll_dev(_napi))\n#ifndef NETIF_F_GRO\n#define napi_complete(_napi) netif_rx_complete(napi_to_poll_dev(_napi))\n#else\n#define napi_complete(_napi) \\\n\tdo { \\\n\t\tnapi_gro_flush(_napi); \\\n\t\tnetif_rx_complete(napi_to_poll_dev(_napi)); \\\n\t} while (0)\n#endif /* NETIF_F_GRO */\n#else /* NAPI */\n#define netif_napi_add(_netdev, _napi, _poll, _weight) \\\n\tdo { \\\n\t\tstruct napi_struct *__napi = _napi; \\\n\t\t_netdev->poll = &(_poll); \\\n\t\t_netdev->weight = (_weight); \\\n\t\t__napi->poll = &(_poll); \\\n\t\t__napi->weight = (_weight); \\\n\t\t__napi->dev = (_netdev); \\\n\t} while (0)\n#define netif_napi_del(_a) do {} while (0)\n#endif /* NAPI */\n\n#undef dev_get_by_name\n#define dev_get_by_name(_a, _b) dev_get_by_name(_b)\n#define __netif_subqueue_stopped(_a, _b) netif_subqueue_stopped(_a, _b)\n#ifndef DMA_BIT_MASK\n#define DMA_BIT_MASK(n)\t(((n) == 64) ? DMA_64BIT_MASK : ((1ULL<<(n))-1))\n#endif\n\n#ifdef NETIF_F_TSO6\n#define skb_is_gso_v6 _kc_skb_is_gso_v6\nstatic inline int _kc_skb_is_gso_v6(const struct sk_buff *skb)\n{\n\treturn skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6;\n}\n#endif /* NETIF_F_TSO6 */\n\n#ifndef KERN_CONT\n#define KERN_CONT\t\"\"\n#endif\n#ifndef pr_err\n#define pr_err(fmt, arg...) \\\n\tprintk(KERN_ERR fmt, ##arg)\n#endif\n#else /* < 2.6.24 */\n#define HAVE_ETHTOOL_GET_SSET_COUNT\n#define HAVE_NETDEV_NAPI_LIST\n#endif /* < 2.6.24 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,24) )\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) )\n#include \n#else /* >= 3.2.0 */\n#include \n#endif /* else >= 3.2.0 */\n#endif /* > 2.6.24 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) )\n#define PM_QOS_CPU_DMA_LATENCY\t1\n\n#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18) )\n#include \n#define PM_QOS_DEFAULT_VALUE\tINFINITE_LATENCY\n#define pm_qos_add_requirement(pm_qos_class, name, value) \\\n\t\tset_acceptable_latency(name, value)\n#define pm_qos_remove_requirement(pm_qos_class, name) \\\n\t\tremove_acceptable_latency(name)\n#define pm_qos_update_requirement(pm_qos_class, name, value) \\\n\t\tmodify_acceptable_latency(name, value)\n#else\n#define PM_QOS_DEFAULT_VALUE\t-1\n#define pm_qos_add_requirement(pm_qos_class, name, value)\n#define pm_qos_remove_requirement(pm_qos_class, name)\n#define pm_qos_update_requirement(pm_qos_class, name, value) { \\\n\tif (value != PM_QOS_DEFAULT_VALUE) { \\\n\t\tprintk(KERN_WARNING \"%s: unable to set PM QoS requirement\\n\", \\\n\t\t\tpci_name(adapter->pdev)); \\\n\t} \\\n}\n\n#endif /* > 2.6.18 */\n\n#define pci_enable_device_mem(pdev) pci_enable_device(pdev)\n\n#ifndef DEFINE_PCI_DEVICE_TABLE\n#define DEFINE_PCI_DEVICE_TABLE(_table) struct pci_device_id _table[]\n#endif /* DEFINE_PCI_DEVICE_TABLE */\n\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) )\n#ifndef IGB_PROCFS\n#define IGB_PROCFS\n#endif /* IGB_PROCFS */\n#endif /* >= 2.6.0 */\n\n#else /* < 2.6.25 */\n\n\n#if IS_ENABLED(CONFIG_HWMON)\n#ifndef IGB_HWMON\n#define IGB_HWMON\n#endif /* IGB_HWMON */\n#endif /* CONFIG_HWMON */\n\n#endif /* < 2.6.25 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) )\n#ifndef clamp_t\n#define clamp_t(type, val, min, max) ({\t\t\\\n\ttype __val = (val);\t\t\t\\\n\ttype __min = (min);\t\t\t\\\n\ttype __max = (max);\t\t\t\\\n\t__val = __val < __min ? __min : __val;\t\\\n\t__val > __max ? __max : __val; })\n#endif /* clamp_t */\n#undef kzalloc_node\n#define kzalloc_node(_size, _flags, _node) kzalloc(_size, _flags)\n\nextern void _kc_pci_disable_link_state(struct pci_dev *dev, int state);\n#define pci_disable_link_state(p, s) _kc_pci_disable_link_state(p, s)\n#else /* < 2.6.26 */\n#include \n#define HAVE_NETDEV_VLAN_FEATURES\n#ifndef PCI_EXP_LNKCAP_ASPMS\n#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */\n#endif /* PCI_EXP_LNKCAP_ASPMS */\n#endif /* < 2.6.26 */\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) )\nstatic inline void _kc_ethtool_cmd_speed_set(struct ethtool_cmd *ep,\n\t\t\t\t\t __u32 speed)\n{\n\tep->speed = (__u16)speed;\n\t/* ep->speed_hi = (__u16)(speed >> 16); */\n}\n#define ethtool_cmd_speed_set _kc_ethtool_cmd_speed_set\n\nstatic inline __u32 _kc_ethtool_cmd_speed(struct ethtool_cmd *ep)\n{\n\t/* no speed_hi before 2.6.27, and probably no need for it yet */\n\treturn (__u32)ep->speed;\n}\n#define ethtool_cmd_speed _kc_ethtool_cmd_speed\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) )\n#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) && defined(CONFIG_PM))\n#define ANCIENT_PM 1\n#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23)) && \\\n (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) && \\\n defined(CONFIG_PM_SLEEP))\n#define NEWER_PM 1\n#endif\n#if defined(ANCIENT_PM) || defined(NEWER_PM)\n#undef device_set_wakeup_enable\n#define device_set_wakeup_enable(dev, val) \\\n\tdo { \\\n\t\tu16 pmc = 0; \\\n\t\tint pm = pci_find_capability(adapter->pdev, PCI_CAP_ID_PM); \\\n\t\tif (pm) { \\\n\t\t\tpci_read_config_word(adapter->pdev, pm + PCI_PM_PMC, \\\n\t\t\t\t&pmc); \\\n\t\t} \\\n\t\t(dev)->power.can_wakeup = !!(pmc >> 11); \\\n\t\t(dev)->power.should_wakeup = (val && (pmc >> 11)); \\\n\t} while (0)\n#endif /* 2.6.15-2.6.22 and CONFIG_PM or 2.6.23-2.6.25 and CONFIG_PM_SLEEP */\n#endif /* 2.6.15 through 2.6.27 */\n#ifndef netif_napi_del\n#define netif_napi_del(_a) do {} while (0)\n#ifdef NAPI\n#ifdef CONFIG_NETPOLL\n#undef netif_napi_del\n#define netif_napi_del(_a) list_del(&(_a)->dev_list);\n#endif\n#endif\n#endif /* netif_napi_del */\n#ifdef dma_mapping_error\n#undef dma_mapping_error\n#endif\n#define dma_mapping_error(dev, dma_addr) pci_dma_mapping_error(dma_addr)\n\n#ifdef CONFIG_NETDEVICES_MULTIQUEUE\n#define HAVE_TX_MQ\n#endif\n\n#ifdef HAVE_TX_MQ\nextern void _kc_netif_tx_stop_all_queues(struct net_device *);\nextern void _kc_netif_tx_wake_all_queues(struct net_device *);\nextern void _kc_netif_tx_start_all_queues(struct net_device *);\n#define netif_tx_stop_all_queues(a) _kc_netif_tx_stop_all_queues(a)\n#define netif_tx_wake_all_queues(a) _kc_netif_tx_wake_all_queues(a)\n#define netif_tx_start_all_queues(a) _kc_netif_tx_start_all_queues(a)\n#undef netif_stop_subqueue\n#define netif_stop_subqueue(_ndev,_qi) do { \\\n\tif (netif_is_multiqueue((_ndev))) \\\n\t\tnetif_stop_subqueue((_ndev), (_qi)); \\\n\telse \\\n\t\tnetif_stop_queue((_ndev)); \\\n\t} while (0)\n#undef netif_start_subqueue\n#define netif_start_subqueue(_ndev,_qi) do { \\\n\tif (netif_is_multiqueue((_ndev))) \\\n\t\tnetif_start_subqueue((_ndev), (_qi)); \\\n\telse \\\n\t\tnetif_start_queue((_ndev)); \\\n\t} while (0)\n#else /* HAVE_TX_MQ */\n#define netif_tx_stop_all_queues(a) netif_stop_queue(a)\n#define netif_tx_wake_all_queues(a) netif_wake_queue(a)\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12) )\n#define netif_tx_start_all_queues(a) netif_start_queue(a)\n#else\n#define netif_tx_start_all_queues(a) do {} while (0)\n#endif\n#define netif_stop_subqueue(_ndev,_qi) netif_stop_queue((_ndev))\n#define netif_start_subqueue(_ndev,_qi) netif_start_queue((_ndev))\n#endif /* HAVE_TX_MQ */\n#ifndef NETIF_F_MULTI_QUEUE\n#define NETIF_F_MULTI_QUEUE 0\n#define netif_is_multiqueue(a) 0\n#define netif_wake_subqueue(a, b)\n#endif /* NETIF_F_MULTI_QUEUE */\n\n#ifndef __WARN_printf\nextern void __kc_warn_slowpath(const char *file, const int line,\n\t\tconst char *fmt, ...) __attribute__((format(printf, 3, 4)));\n#define __WARN_printf(arg...) __kc_warn_slowpath(__FILE__, __LINE__, arg)\n#endif /* __WARN_printf */\n\n#ifndef WARN\n#define WARN(condition, format...) ({\t\t\t\t\t\t\\\n\tint __ret_warn_on = !!(condition);\t\t\t\t\\\n\tif (unlikely(__ret_warn_on))\t\t\t\t\t\\\n\t\t__WARN_printf(format);\t\t\t\t\t\\\n\tunlikely(__ret_warn_on);\t\t\t\t\t\\\n})\n#endif /* WARN */\n#undef HAVE_IXGBE_DEBUG_FS\n#undef HAVE_IGB_DEBUG_FS\n#else /* < 2.6.27 */\n#define HAVE_TX_MQ\n#define HAVE_NETDEV_SELECT_QUEUE\n#ifdef CONFIG_DEBUG_FS\n#define HAVE_IXGBE_DEBUG_FS\n#define HAVE_IGB_DEBUG_FS\n#endif /* CONFIG_DEBUG_FS */\n#endif /* < 2.6.27 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) )\n#define pci_ioremap_bar(pdev, bar)\tioremap(pci_resource_start(pdev, bar), \\\n\t\t\t\t\t pci_resource_len(pdev, bar))\n#define pci_wake_from_d3 _kc_pci_wake_from_d3\n#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep\nextern int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable);\nextern int _kc_pci_prepare_to_sleep(struct pci_dev *dev);\n#define netdev_alloc_page(a) alloc_page(GFP_ATOMIC)\n#ifndef __skb_queue_head_init\nstatic inline void __kc_skb_queue_head_init(struct sk_buff_head *list)\n{\n\tlist->prev = list->next = (struct sk_buff *)list;\n\tlist->qlen = 0;\n}\n#define __skb_queue_head_init(_q) __kc_skb_queue_head_init(_q)\n#endif\n\n#define PCI_EXP_DEVCAP2\t\t36\t/* Device Capabilities 2 */\n#define PCI_EXP_DEVCTL2\t\t40\t/* Device Control 2 */\n\n#endif /* < 2.6.28 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) )\n#ifndef swap\n#define swap(a, b) \\\n\tdo { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)\n#endif\n#define pci_request_selected_regions_exclusive(pdev, bars, name) \\\n\t\tpci_request_selected_regions(pdev, bars, name)\n#ifndef CONFIG_NR_CPUS\n#define CONFIG_NR_CPUS 1\n#endif /* CONFIG_NR_CPUS */\n#ifndef pcie_aspm_enabled\n#define pcie_aspm_enabled() (1)\n#endif /* pcie_aspm_enabled */\n\n#define PCI_EXP_SLTSTA_PDS\t0x0040\t/* Presence Detect State */\n\n#ifndef pci_clear_master\nextern void _kc_pci_clear_master(struct pci_dev *dev);\n#define pci_clear_master(dev)\t_kc_pci_clear_master(dev)\n#endif\n\n#ifndef PCI_EXP_LNKCTL_ASPMC\n#define PCI_EXP_LNKCTL_ASPMC\t0x0003\t/* ASPM Control */\n#endif\n#else /* < 2.6.29 */\n#ifndef HAVE_NET_DEVICE_OPS\n#define HAVE_NET_DEVICE_OPS\n#endif\n#ifdef CONFIG_DCB\n#define HAVE_PFC_MODE_ENABLE\n#endif /* CONFIG_DCB */\n#endif /* < 2.6.29 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) )\n#define skb_rx_queue_recorded(a) false\n#define skb_get_rx_queue(a) 0\n#define skb_record_rx_queue(a, b) do {} while (0)\n#define skb_tx_hash(n, s) ___kc_skb_tx_hash((n), (s), (n)->real_num_tx_queues)\n#ifndef CONFIG_PCI_IOV\n#undef pci_enable_sriov\n#define pci_enable_sriov(a, b) -ENOTSUPP\n#undef pci_disable_sriov\n#define pci_disable_sriov(a) do {} while (0)\n#endif /* CONFIG_PCI_IOV */\n#ifndef pr_cont\n#define pr_cont(fmt, ...) \\\n\tprintk(KERN_CONT fmt, ##__VA_ARGS__)\n#endif /* pr_cont */\nstatic inline void _kc_synchronize_irq(unsigned int a)\n{\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) )\n\tsynchronize_irq();\n#else /* < 2.5.28 */\n\tsynchronize_irq(a);\n#endif /* < 2.5.28 */\n}\n#undef synchronize_irq\n#define synchronize_irq(a) _kc_synchronize_irq(a)\n\n#define PCI_EXP_LNKCTL2\t\t48\t/* Link Control 2 */\n\n#else /* < 2.6.30 */\n#define HAVE_ASPM_QUIRKS\n#endif /* < 2.6.30 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31) )\n#define ETH_P_1588 0x88F7\n#define ETH_P_FIP 0x8914\n#ifndef netdev_uc_count\n#define netdev_uc_count(dev) ((dev)->uc_count)\n#endif\n#ifndef netdev_for_each_uc_addr\n#define netdev_for_each_uc_addr(uclist, dev) \\\n\tfor (uclist = dev->uc_list; uclist; uclist = uclist->next)\n#endif\n#ifndef PORT_OTHER\n#define PORT_OTHER 0xff\n#endif\n#ifndef MDIO_PHY_ID_PRTAD\n#define MDIO_PHY_ID_PRTAD 0x03e0\n#endif\n#ifndef MDIO_PHY_ID_DEVAD\n#define MDIO_PHY_ID_DEVAD 0x001f\n#endif\n#ifndef skb_dst\n#define skb_dst(s) ((s)->dst)\n#endif\n\n#ifndef SUPPORTED_1000baseKX_Full\n#define SUPPORTED_1000baseKX_Full\t(1 << 17)\n#endif\n#ifndef SUPPORTED_10000baseKX4_Full\n#define SUPPORTED_10000baseKX4_Full\t(1 << 18)\n#endif\n#ifndef SUPPORTED_10000baseKR_Full\n#define SUPPORTED_10000baseKR_Full\t(1 << 19)\n#endif\n\n#ifndef ADVERTISED_1000baseKX_Full\n#define ADVERTISED_1000baseKX_Full\t(1 << 17)\n#endif\n#ifndef ADVERTISED_10000baseKX4_Full\n#define ADVERTISED_10000baseKX4_Full\t(1 << 18)\n#endif\n#ifndef ADVERTISED_10000baseKR_Full\n#define ADVERTISED_10000baseKR_Full\t(1 << 19)\n#endif\n\n#else /* < 2.6.31 */\n#ifndef HAVE_NETDEV_STORAGE_ADDRESS\n#define HAVE_NETDEV_STORAGE_ADDRESS\n#endif\n#ifndef HAVE_NETDEV_HW_ADDR\n#define HAVE_NETDEV_HW_ADDR\n#endif\n#ifndef HAVE_TRANS_START_IN_QUEUE\n#define HAVE_TRANS_START_IN_QUEUE\n#endif\n#ifndef HAVE_INCLUDE_LINUX_MDIO_H\n#define HAVE_INCLUDE_LINUX_MDIO_H\n#endif\n#endif /* < 2.6.31 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) )\n#undef netdev_tx_t\n#define netdev_tx_t int\n#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)\n#ifndef NETIF_F_FCOE_MTU\n#define NETIF_F_FCOE_MTU (1 << 26)\n#endif\n#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )\nstatic inline int _kc_pm_runtime_get_sync()\n{\n\treturn 1;\n}\n#define pm_runtime_get_sync(dev)\t_kc_pm_runtime_get_sync()\n#else /* 2.6.0 => 2.6.32 */\nstatic inline int _kc_pm_runtime_get_sync(struct device *dev)\n{\n\treturn 1;\n}\n#ifndef pm_runtime_get_sync\n#define pm_runtime_get_sync(dev)\t_kc_pm_runtime_get_sync(dev)\n#endif\n#endif /* 2.6.0 => 2.6.32 */\n#ifndef pm_runtime_put\n#define pm_runtime_put(dev)\t\tdo {} while (0)\n#endif\n#ifndef pm_runtime_put_sync\n#define pm_runtime_put_sync(dev)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_resume\n#define pm_runtime_resume(dev)\t\tdo {} while (0)\n#endif\n#ifndef pm_schedule_suspend\n#define pm_schedule_suspend(dev, t)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_set_suspended\n#define pm_runtime_set_suspended(dev)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_disable\n#define pm_runtime_disable(dev)\t\tdo {} while (0)\n#endif\n#ifndef pm_runtime_put_noidle\n#define pm_runtime_put_noidle(dev)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_set_active\n#define pm_runtime_set_active(dev)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_enable\n#define pm_runtime_enable(dev)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_get_noresume\n#define pm_runtime_get_noresume(dev)\tdo {} while (0)\n#endif\n#else /* < 2.6.32 */\n#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)\n#ifndef HAVE_NETDEV_OPS_FCOE_ENABLE\n#define HAVE_NETDEV_OPS_FCOE_ENABLE\n#endif\n#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */\n#ifdef CONFIG_DCB\n#ifndef HAVE_DCBNL_OPS_GETAPP\n#define HAVE_DCBNL_OPS_GETAPP\n#endif\n#endif /* CONFIG_DCB */\n#include \n/* IOV bad DMA target work arounds require at least this kernel rev support */\n#define HAVE_PCIE_TYPE\n#endif /* < 2.6.32 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33) )\n#ifndef pci_pcie_cap\n#define pci_pcie_cap(pdev) pci_find_capability(pdev, PCI_CAP_ID_EXP)\n#endif\n#ifndef IPV4_FLOW\n#define IPV4_FLOW 0x10\n#endif /* IPV4_FLOW */\n#ifndef IPV6_FLOW\n#define IPV6_FLOW 0x11\n#endif /* IPV6_FLOW */\n/* Features back-ported to RHEL6 or SLES11 SP1 after 2.6.32 */\n#if ( (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0)) || \\\n (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,1,0)) )\n#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)\n#ifndef HAVE_NETDEV_OPS_FCOE_GETWWN\n#define HAVE_NETDEV_OPS_FCOE_GETWWN\n#endif\n#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */\n#endif /* RHEL6 or SLES11 SP1 */\n#ifndef __percpu\n#define __percpu\n#endif /* __percpu */\n#ifndef PORT_DA\n#define PORT_DA PORT_OTHER\n#endif\n#ifndef PORT_NONE\n#define PORT_NONE PORT_OTHER\n#endif\n\n#if ((RHEL_RELEASE_CODE && \\\n (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,3)) && \\\n (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0))))\n#if !defined(CONFIG_X86_32) && !defined(CONFIG_NEED_DMA_MAP_STATE)\n#undef DEFINE_DMA_UNMAP_ADDR\n#define DEFINE_DMA_UNMAP_ADDR(ADDR_NAME)\tdma_addr_t ADDR_NAME\n#undef DEFINE_DMA_UNMAP_LEN\n#define DEFINE_DMA_UNMAP_LEN(LEN_NAME)\t\t__u32 LEN_NAME\n#undef dma_unmap_addr\n#define dma_unmap_addr(PTR, ADDR_NAME)\t\t((PTR)->ADDR_NAME)\n#undef dma_unmap_addr_set\n#define dma_unmap_addr_set(PTR, ADDR_NAME, VAL)\t(((PTR)->ADDR_NAME) = (VAL))\n#undef dma_unmap_len\n#define dma_unmap_len(PTR, LEN_NAME)\t\t((PTR)->LEN_NAME)\n#undef dma_unmap_len_set\n#define dma_unmap_len_set(PTR, LEN_NAME, VAL)\t(((PTR)->LEN_NAME) = (VAL))\n#endif /* CONFIG_X86_64 && !CONFIG_NEED_DMA_MAP_STATE */\n#endif /* RHEL_RELEASE_CODE */\n\n#if (!(RHEL_RELEASE_CODE && \\\n (((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,8)) && \\\n (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0))) || \\\n ((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,1)) && \\\n (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0))))))\nstatic inline bool pci_is_pcie(struct pci_dev *dev)\n{\n\treturn !!pci_pcie_cap(dev);\n}\n#endif /* RHEL_RELEASE_CODE */\n\n#ifndef __always_unused\n#define __always_unused __attribute__((__unused__))\n#endif\n#ifndef __maybe_unused\n#define __maybe_unused __attribute__((__unused__))\n#endif\n\n#if (!(RHEL_RELEASE_CODE && \\\n (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,2))))\n#define sk_tx_queue_get(_sk) (-1)\n#define sk_tx_queue_set(_sk, _tx_queue) do {} while(0)\n#endif /* !(RHEL >= 6.2) */\n\n#if (RHEL_RELEASE_CODE && \\\n (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,4)) && \\\n (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)))\n#define HAVE_RHEL6_ETHTOOL_OPS_EXT_STRUCT\n#define HAVE_ETHTOOL_SET_PHYS_ID\n#define HAVE_ETHTOOL_GET_TS_INFO\n#endif /* RHEL >= 6.4 && RHEL < 7.0 */\n\n#if (RHEL_RELEASE_CODE && \\\n (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,5)) && \\\n (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)))\n#define HAVE_RHEL6_NETDEV_OPS_EXT_FDB\n#endif /* RHEL >= 6.5 && RHEL < 7.0 */\n\n#else /* < 2.6.33 */\n#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)\n#ifndef HAVE_NETDEV_OPS_FCOE_GETWWN\n#define HAVE_NETDEV_OPS_FCOE_GETWWN\n#endif\n#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */\n#endif /* < 2.6.33 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34) )\n#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0))\n#ifndef pci_num_vf\n#define pci_num_vf(pdev) _kc_pci_num_vf(pdev)\nextern int _kc_pci_num_vf(struct pci_dev *dev);\n#endif\n#endif /* RHEL_RELEASE_CODE */\n\n#ifndef ETH_FLAG_NTUPLE\n#define ETH_FLAG_NTUPLE NETIF_F_NTUPLE\n#endif\n\n#ifndef netdev_mc_count\n#define netdev_mc_count(dev) ((dev)->mc_count)\n#endif\n#ifndef netdev_mc_empty\n#define netdev_mc_empty(dev) (netdev_mc_count(dev) == 0)\n#endif\n#ifndef netdev_for_each_mc_addr\n#define netdev_for_each_mc_addr(mclist, dev) \\\n\tfor (mclist = dev->mc_list; mclist; mclist = mclist->next)\n#endif\n#ifndef netdev_uc_count\n#define netdev_uc_count(dev) ((dev)->uc.count)\n#endif\n#ifndef netdev_uc_empty\n#define netdev_uc_empty(dev) (netdev_uc_count(dev) == 0)\n#endif\n#ifndef netdev_for_each_uc_addr\n#define netdev_for_each_uc_addr(ha, dev) \\\n\tlist_for_each_entry(ha, &dev->uc.list, list)\n#endif\n#ifndef dma_set_coherent_mask\n#define dma_set_coherent_mask(dev,mask) \\\n\tpci_set_consistent_dma_mask(to_pci_dev(dev),(mask))\n#endif\n#ifndef pci_dev_run_wake\n#define pci_dev_run_wake(pdev)\t(0)\n#endif\n\n/* netdev logging taken from include/linux/netdevice.h */\n#ifndef netdev_name\nstatic inline const char *_kc_netdev_name(const struct net_device *dev)\n{\n\tif (dev->reg_state != NETREG_REGISTERED)\n\t\treturn \"(unregistered net_device)\";\n\treturn dev->name;\n}\n#define netdev_name(netdev)\t_kc_netdev_name(netdev)\n#endif /* netdev_name */\n\n#undef netdev_printk\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )\n#define netdev_printk(level, netdev, format, args...)\t\t\\\ndo {\t\t\t\t\t\t\t\t\\\n\tstruct pci_dev *pdev = _kc_netdev_to_pdev(netdev);\t\\\n\tprintk(level \"%s: \" format, pci_name(pdev), ##args);\t\\\n} while(0)\n#elif ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) )\n#define netdev_printk(level, netdev, format, args...)\t\t\\\ndo {\t\t\t\t\t\t\t\t\\\n\tstruct pci_dev *pdev = _kc_netdev_to_pdev(netdev);\t\\\n\tstruct device *dev = pci_dev_to_dev(pdev);\t\t\\\n\tdev_printk(level, dev, \"%s: \" format,\t\t\t\\\n\t\t netdev_name(netdev), ##args);\t\t\\\n} while(0)\n#else /* 2.6.21 => 2.6.34 */\n#define netdev_printk(level, netdev, format, args...)\t\t\\\n\tdev_printk(level, (netdev)->dev.parent,\t\t\t\\\n\t\t \"%s: \" format,\t\t\t\t\\\n\t\t netdev_name(netdev), ##args)\n#endif /* <2.6.0 <2.6.21 <2.6.34 */\n#undef netdev_emerg\n#define netdev_emerg(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_EMERG, dev, format, ##args)\n#undef netdev_alert\n#define netdev_alert(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_ALERT, dev, format, ##args)\n#undef netdev_crit\n#define netdev_crit(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_CRIT, dev, format, ##args)\n#undef netdev_err\n#define netdev_err(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_ERR, dev, format, ##args)\n#undef netdev_warn\n#define netdev_warn(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_WARNING, dev, format, ##args)\n#undef netdev_notice\n#define netdev_notice(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_NOTICE, dev, format, ##args)\n#undef netdev_info\n#define netdev_info(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_INFO, dev, format, ##args)\n#undef netdev_dbg\n#if defined(DEBUG)\n#define netdev_dbg(__dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_DEBUG, __dev, format, ##args)\n#elif defined(CONFIG_DYNAMIC_DEBUG)\n#define netdev_dbg(__dev, format, args...)\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\\\n\tdynamic_dev_dbg((__dev)->dev.parent, \"%s: \" format,\t\\\n\t\t\tnetdev_name(__dev), ##args);\t\t\\\n} while (0)\n#else /* DEBUG */\n#define netdev_dbg(__dev, format, args...)\t\t\t\\\n({\t\t\t\t\t\t\t\t\\\n\tif (0)\t\t\t\t\t\t\t\\\n\t\tnetdev_printk(KERN_DEBUG, __dev, format, ##args); \\\n\t0;\t\t\t\t\t\t\t\\\n})\n#endif /* DEBUG */\n\n#undef netif_printk\n#define netif_printk(priv, type, level, dev, fmt, args...)\t\\\ndo {\t\t\t\t\t\t\t\t\\\n\tif (netif_msg_##type(priv))\t\t\t\t\\\n\t\tnetdev_printk(level, (dev), fmt, ##args);\t\\\n} while (0)\n\n#undef netif_emerg\n#define netif_emerg(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(emerg, priv, type, dev, fmt, ##args)\n#undef netif_alert\n#define netif_alert(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(alert, priv, type, dev, fmt, ##args)\n#undef netif_crit\n#define netif_crit(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(crit, priv, type, dev, fmt, ##args)\n#undef netif_err\n#define netif_err(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(err, priv, type, dev, fmt, ##args)\n#undef netif_warn\n#define netif_warn(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(warn, priv, type, dev, fmt, ##args)\n#undef netif_notice\n#define netif_notice(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(notice, priv, type, dev, fmt, ##args)\n#undef netif_info\n#define netif_info(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(info, priv, type, dev, fmt, ##args)\n#undef netif_dbg\n#define netif_dbg(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(dbg, priv, type, dev, fmt, ##args)\n\n#ifdef SET_SYSTEM_SLEEP_PM_OPS\n#define HAVE_SYSTEM_SLEEP_PM_OPS\n#endif\n\n#ifndef for_each_set_bit\n#define for_each_set_bit(bit, addr, size) \\\n\tfor ((bit) = find_first_bit((addr), (size)); \\\n\t\t(bit) < (size); \\\n\t\t(bit) = find_next_bit((addr), (size), (bit) + 1))\n#endif /* for_each_set_bit */\n\n#ifndef DEFINE_DMA_UNMAP_ADDR\n#define DEFINE_DMA_UNMAP_ADDR DECLARE_PCI_UNMAP_ADDR\n#define DEFINE_DMA_UNMAP_LEN DECLARE_PCI_UNMAP_LEN\n#define dma_unmap_addr pci_unmap_addr\n#define dma_unmap_addr_set pci_unmap_addr_set\n#define dma_unmap_len pci_unmap_len\n#define dma_unmap_len_set pci_unmap_len_set\n#endif /* DEFINE_DMA_UNMAP_ADDR */\n\n#if (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,3))\n#ifdef IGB_HWMON\n#ifdef CONFIG_DEBUG_LOCK_ALLOC\n#define sysfs_attr_init(attr)\t\t\t\t\\\n\tdo {\t\t\t\t\t\t\\\n\t\tstatic struct lock_class_key __key;\t\\\n\t\t(attr)->key = &__key;\t\t\t\\\n\t} while (0)\n#else\n#define sysfs_attr_init(attr) do {} while (0)\n#endif /* CONFIG_DEBUG_LOCK_ALLOC */\n#endif /* IGB_HWMON */\n#endif /* RHEL_RELEASE_CODE */\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )\nstatic inline bool _kc_pm_runtime_suspended()\n{\n\treturn false;\n}\n#define pm_runtime_suspended(dev)\t_kc_pm_runtime_suspended()\n#else /* 2.6.0 => 2.6.34 */\nstatic inline bool _kc_pm_runtime_suspended(struct device *dev)\n{\n\treturn false;\n}\n#ifndef pm_runtime_suspended\n#define pm_runtime_suspended(dev)\t_kc_pm_runtime_suspended(dev)\n#endif\n#endif /* 2.6.0 => 2.6.34 */\n\n#else /* < 2.6.34 */\n#define HAVE_SYSTEM_SLEEP_PM_OPS\n#ifndef HAVE_SET_RX_MODE\n#define HAVE_SET_RX_MODE\n#endif\n\n#endif /* < 2.6.34 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) )\n\nssize_t _kc_simple_write_to_buffer(void *to, size_t available, loff_t *ppos,\n\t\t\t\t const void __user *from, size_t count);\n#define simple_write_to_buffer _kc_simple_write_to_buffer\n\n#ifndef numa_node_id\n#define numa_node_id() 0\n#endif\n#ifdef HAVE_TX_MQ\n#include \n#ifndef CONFIG_NETDEVICES_MULTIQUEUE\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0)))\nvoid _kc_netif_set_real_num_tx_queues(struct net_device *, unsigned int);\n#define netif_set_real_num_tx_queues _kc_netif_set_real_num_tx_queues\n#endif /* !(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0)) */\n#else /* CONFIG_NETDEVICES_MULTI_QUEUE */\n#define netif_set_real_num_tx_queues(_netdev, _count) \\\n\tdo { \\\n\t\t(_netdev)->egress_subqueue_count = _count; \\\n\t} while (0)\n#endif /* CONFIG_NETDEVICES_MULTI_QUEUE */\n#else /* HAVE_TX_MQ */\n#define netif_set_real_num_tx_queues(_netdev, _count) do {} while(0)\n#endif /* HAVE_TX_MQ */\n#ifndef ETH_FLAG_RXHASH\n#define ETH_FLAG_RXHASH (1<<28)\n#endif /* ETH_FLAG_RXHASH */\n#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0))\n#define HAVE_IRQ_AFFINITY_HINT\n#endif\n#else /* < 2.6.35 */\n#define HAVE_PM_QOS_REQUEST_LIST\n#define HAVE_IRQ_AFFINITY_HINT\n#endif /* < 2.6.35 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) )\nextern int _kc_ethtool_op_set_flags(struct net_device *, u32, u32);\n#define ethtool_op_set_flags _kc_ethtool_op_set_flags\nextern u32 _kc_ethtool_op_get_flags(struct net_device *);\n#define ethtool_op_get_flags _kc_ethtool_op_get_flags\n\n#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS\n#ifdef NET_IP_ALIGN\n#undef NET_IP_ALIGN\n#endif\n#define NET_IP_ALIGN 0\n#endif /* CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS */\n\n#ifdef NET_SKB_PAD\n#undef NET_SKB_PAD\n#endif\n\n#if (L1_CACHE_BYTES > 32)\n#define NET_SKB_PAD L1_CACHE_BYTES\n#else\n#define NET_SKB_PAD 32\n#endif\n\nstatic inline struct sk_buff *_kc_netdev_alloc_skb_ip_align(struct net_device *dev,\n\t\t\t\t\t\t\t unsigned int length)\n{\n\tstruct sk_buff *skb;\n\n\tskb = alloc_skb(length + NET_SKB_PAD + NET_IP_ALIGN, GFP_ATOMIC);\n\tif (skb) {\n#if (NET_IP_ALIGN + NET_SKB_PAD)\n\t\tskb_reserve(skb, NET_IP_ALIGN + NET_SKB_PAD);\n#endif\n\t\tskb->dev = dev;\n\t}\n\treturn skb;\n}\n\n#ifdef netdev_alloc_skb_ip_align\n#undef netdev_alloc_skb_ip_align\n#endif\n#define netdev_alloc_skb_ip_align(n, l) _kc_netdev_alloc_skb_ip_align(n, l)\n\n#undef netif_level\n#define netif_level(level, priv, type, dev, fmt, args...)\t\\\ndo {\t\t\t\t\t\t\t\t\\\n\tif (netif_msg_##type(priv))\t\t\t\t\\\n\t\tnetdev_##level(dev, fmt, ##args);\t\t\\\n} while (0)\n\n#undef usleep_range\n#define usleep_range(min, max)\tmsleep(DIV_ROUND_UP(min, 1000))\n\n#define u64_stats_update_begin(a) do { } while(0)\n#define u64_stats_update_end(a) do { } while(0)\n#define u64_stats_fetch_begin(a) do { } while(0)\n#define u64_stats_fetch_retry_bh(a) (0)\n#define u64_stats_fetch_begin_bh(a) (0)\n\n#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,1))\n#define HAVE_8021P_SUPPORT\n#endif\n\n#else /* < 2.6.36 */\n\n\n#define HAVE_PM_QOS_REQUEST_ACTIVE\n#define HAVE_8021P_SUPPORT\n#define HAVE_NDO_GET_STATS64\n#endif /* < 2.6.36 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37) )\n#ifndef netif_set_real_num_rx_queues\nstatic inline int __kc_netif_set_real_num_rx_queues(struct net_device *dev,\n\t\t\t\t\t\t unsigned int rxq)\n{\n\treturn 0;\n}\n#define netif_set_real_num_rx_queues(dev, rxq) \\\n\t__kc_netif_set_real_num_rx_queues((dev), (rxq))\n#endif\n#ifndef ETHTOOL_RXNTUPLE_ACTION_CLEAR\n#define ETHTOOL_RXNTUPLE_ACTION_CLEAR (-2)\n#endif\n#ifndef VLAN_N_VID\n#define VLAN_N_VID\tVLAN_GROUP_ARRAY_LEN\n#endif /* VLAN_N_VID */\n#ifndef ETH_FLAG_TXVLAN\n#define ETH_FLAG_TXVLAN (1 << 7)\n#endif /* ETH_FLAG_TXVLAN */\n#ifndef ETH_FLAG_RXVLAN\n#define ETH_FLAG_RXVLAN (1 << 8)\n#endif /* ETH_FLAG_RXVLAN */\n\nstatic inline void _kc_skb_checksum_none_assert(struct sk_buff *skb)\n{\n\tWARN_ON(skb->ip_summed != CHECKSUM_NONE);\n}\n#define skb_checksum_none_assert(skb) _kc_skb_checksum_none_assert(skb)\n\nstatic inline void *_kc_vzalloc_node(unsigned long size, int node)\n{\n\tvoid *addr = vmalloc_node(size, node);\n\tif (addr)\n\t\tmemset(addr, 0, size);\n\treturn addr;\n}\n#define vzalloc_node(_size, _node) _kc_vzalloc_node(_size, _node)\n\nstatic inline void *_kc_vzalloc(unsigned long size)\n{\n\tvoid *addr = vmalloc(size);\n\tif (addr)\n\t\tmemset(addr, 0, size);\n\treturn addr;\n}\n#define vzalloc(_size) _kc_vzalloc(_size)\n\n#ifndef vlan_get_protocol\nstatic inline __be16 __kc_vlan_get_protocol(const struct sk_buff *skb)\n{\n\tif (vlan_tx_tag_present(skb) ||\n\t skb->protocol != cpu_to_be16(ETH_P_8021Q))\n\t\treturn skb->protocol;\n\n\tif (skb_headlen(skb) < sizeof(struct vlan_ethhdr))\n\t\treturn 0;\n\n\treturn ((struct vlan_ethhdr*)skb->data)->h_vlan_encapsulated_proto;\n}\n#define vlan_get_protocol(_skb) __kc_vlan_get_protocol(_skb)\n#endif\n#ifdef HAVE_HW_TIME_STAMP\n#define SKBTX_HW_TSTAMP (1 << 0)\n#define SKBTX_IN_PROGRESS (1 << 2)\n#define SKB_SHARED_TX_IS_UNION\n#endif\n\n#ifndef device_wakeup_enable\n#define device_wakeup_enable(dev)\tdevice_set_wakeup_enable(dev, true)\n#endif\n\n#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,4,18) )\n#ifndef HAVE_VLAN_RX_REGISTER\n#define HAVE_VLAN_RX_REGISTER\n#endif\n#endif /* > 2.4.18 */\n#endif /* < 2.6.37 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) )\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) )\n#define skb_checksum_start_offset(skb) skb_transport_offset(skb)\n#else /* 2.6.22 -> 2.6.37 */\nstatic inline int _kc_skb_checksum_start_offset(const struct sk_buff *skb)\n{\n return skb->csum_start - skb_headroom(skb);\n}\n#define skb_checksum_start_offset(skb) _kc_skb_checksum_start_offset(skb)\n#endif /* 2.6.22 -> 2.6.37 */\n#ifdef CONFIG_DCB\n#ifndef IEEE_8021QAZ_MAX_TCS\n#define IEEE_8021QAZ_MAX_TCS 8\n#endif\n#ifndef DCB_CAP_DCBX_HOST\n#define DCB_CAP_DCBX_HOST\t\t0x01\n#endif\n#ifndef DCB_CAP_DCBX_LLD_MANAGED\n#define DCB_CAP_DCBX_LLD_MANAGED\t0x02\n#endif\n#ifndef DCB_CAP_DCBX_VER_CEE\n#define DCB_CAP_DCBX_VER_CEE\t\t0x04\n#endif\n#ifndef DCB_CAP_DCBX_VER_IEEE\n#define DCB_CAP_DCBX_VER_IEEE\t\t0x08\n#endif\n#ifndef DCB_CAP_DCBX_STATIC\n#define DCB_CAP_DCBX_STATIC\t\t0x10\n#endif\n#endif /* CONFIG_DCB */\n#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,2))\n#define CONFIG_XPS\n#endif /* RHEL_RELEASE_VERSION(6,2) */\n#endif /* < 2.6.38 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39) )\n#ifndef NETIF_F_RXCSUM\n#define NETIF_F_RXCSUM\t\t(1 << 29)\n#endif\n#ifndef skb_queue_reverse_walk_safe\n#define skb_queue_reverse_walk_safe(queue, skb, tmp)\t\t\t\t\\\n\t\tfor (skb = (queue)->prev, tmp = skb->prev;\t\t\t\\\n\t\t skb != (struct sk_buff *)(queue);\t\t\t\t\\\n\t\t skb = tmp, tmp = skb->prev)\n#endif\n#else /* < 2.6.39 */\n#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)\n#ifndef HAVE_NETDEV_OPS_FCOE_DDP_TARGET\n#define HAVE_NETDEV_OPS_FCOE_DDP_TARGET\n#endif\n#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */\n#ifndef HAVE_MQPRIO\n#define HAVE_MQPRIO\n#endif\n#ifndef HAVE_SETUP_TC\n#define HAVE_SETUP_TC\n#endif\n#ifdef CONFIG_DCB\n#ifndef HAVE_DCBNL_IEEE\n#define HAVE_DCBNL_IEEE\n#endif\n#endif /* CONFIG_DCB */\n#ifndef HAVE_NDO_SET_FEATURES\n#define HAVE_NDO_SET_FEATURES\n#endif\n#endif /* < 2.6.39 */\n\n/*****************************************************************************/\n/* use < 2.6.40 because of a Fedora 15 kernel update where they\n * updated the kernel version to 2.6.40.x and they back-ported 3.0 features\n * like set_phys_id for ethtool.\n */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,40) )\n#ifdef ETHTOOL_GRXRINGS\n#ifndef FLOW_EXT\n#define\tFLOW_EXT\t0x80000000\nunion _kc_ethtool_flow_union {\n\tstruct ethtool_tcpip4_spec\t\ttcp_ip4_spec;\n\tstruct ethtool_usrip4_spec\t\tusr_ip4_spec;\n\t__u8\t\t\t\t\thdata[60];\n};\nstruct _kc_ethtool_flow_ext {\n\t__be16\tvlan_etype;\n\t__be16\tvlan_tci;\n\t__be32\tdata[2];\n};\nstruct _kc_ethtool_rx_flow_spec {\n\t__u32\t\tflow_type;\n\tunion _kc_ethtool_flow_union h_u;\n\tstruct _kc_ethtool_flow_ext h_ext;\n\tunion _kc_ethtool_flow_union m_u;\n\tstruct _kc_ethtool_flow_ext m_ext;\n\t__u64\t\tring_cookie;\n\t__u32\t\tlocation;\n};\n#define ethtool_rx_flow_spec _kc_ethtool_rx_flow_spec\n#endif /* FLOW_EXT */\n#endif\n\n#define pci_disable_link_state_locked pci_disable_link_state\n\n#ifndef PCI_LTR_VALUE_MASK\n#define PCI_LTR_VALUE_MASK\t0x000003ff\n#endif\n#ifndef PCI_LTR_SCALE_MASK\n#define PCI_LTR_SCALE_MASK\t0x00001c00\n#endif\n#ifndef PCI_LTR_SCALE_SHIFT\n#define PCI_LTR_SCALE_SHIFT\t10\n#endif\n\n#else /* < 2.6.40 */\n#define HAVE_ETHTOOL_SET_PHYS_ID\n#endif /* < 2.6.40 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0) )\n#define USE_LEGACY_PM_SUPPORT\n#endif /* < 3.0.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) )\n#ifndef __netdev_alloc_skb_ip_align\n#define __netdev_alloc_skb_ip_align(d,l,_g) netdev_alloc_skb_ip_align(d,l)\n#endif /* __netdev_alloc_skb_ip_align */\n#define dcb_ieee_setapp(dev, app) dcb_setapp(dev, app)\n#define dcb_ieee_delapp(dev, app) 0\n#define dcb_ieee_getapp_mask(dev, app) (1 << app->priority)\n\n/* 1000BASE-T Control register */\n#define CTL1000_AS_MASTER\t0x0800\n#define CTL1000_ENABLE_MASTER\t0x1000\n\n#else /* < 3.1.0 */\n#ifndef HAVE_DCBNL_IEEE_DELAPP\n#define HAVE_DCBNL_IEEE_DELAPP\n#endif\n#endif /* < 3.1.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) )\n#ifdef ETHTOOL_GRXRINGS\n#define HAVE_ETHTOOL_GET_RXNFC_VOID_RULE_LOCS\n#endif /* ETHTOOL_GRXRINGS */\n\n#ifndef skb_frag_size\n#define skb_frag_size(frag)\t_kc_skb_frag_size(frag)\nstatic inline unsigned int _kc_skb_frag_size(const skb_frag_t *frag)\n{\n\treturn frag->size;\n}\n#endif /* skb_frag_size */\n\n#ifndef skb_frag_size_sub\n#define skb_frag_size_sub(frag, delta)\t_kc_skb_frag_size_sub(frag, delta)\nstatic inline void _kc_skb_frag_size_sub(skb_frag_t *frag, int delta)\n{\n\tfrag->size -= delta;\n}\n#endif /* skb_frag_size_sub */\n\n#ifndef skb_frag_page\n#define skb_frag_page(frag)\t_kc_skb_frag_page(frag)\nstatic inline struct page *_kc_skb_frag_page(const skb_frag_t *frag)\n{\n\treturn frag->page;\n}\n#endif /* skb_frag_page */\n\n#ifndef skb_frag_address\n#define skb_frag_address(frag)\t_kc_skb_frag_address(frag)\nstatic inline void *_kc_skb_frag_address(const skb_frag_t *frag)\n{\n\treturn page_address(skb_frag_page(frag)) + frag->page_offset;\n}\n#endif /* skb_frag_address */\n\n#ifndef skb_frag_dma_map\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) )\n#include \n#endif\n#define skb_frag_dma_map(dev,frag,offset,size,dir) \\\n\t\t_kc_skb_frag_dma_map(dev,frag,offset,size,dir)\nstatic inline dma_addr_t _kc_skb_frag_dma_map(struct device *dev,\n\t\t\t\t\t const skb_frag_t *frag,\n\t\t\t\t\t size_t offset, size_t size,\n\t\t\t\t\t enum dma_data_direction dir)\n{\n\treturn dma_map_page(dev, skb_frag_page(frag),\n\t\t\t frag->page_offset + offset, size, dir);\n}\n#endif /* skb_frag_dma_map */\n\n#ifndef __skb_frag_unref\n#define __skb_frag_unref(frag) __kc_skb_frag_unref(frag)\nstatic inline void __kc_skb_frag_unref(skb_frag_t *frag)\n{\n\tput_page(skb_frag_page(frag));\n}\n#endif /* __skb_frag_unref */\n\n#ifndef SPEED_UNKNOWN\n#define SPEED_UNKNOWN\t-1\n#endif\n#ifndef DUPLEX_UNKNOWN\n#define DUPLEX_UNKNOWN\t0xff\n#endif\n#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,3))\n#ifndef HAVE_PCI_DEV_FLAGS_ASSIGNED\n#define HAVE_PCI_DEV_FLAGS_ASSIGNED\n#endif\n#endif\n#else /* < 3.2.0 */\n#ifndef HAVE_PCI_DEV_FLAGS_ASSIGNED\n#define HAVE_PCI_DEV_FLAGS_ASSIGNED\n#define HAVE_VF_SPOOFCHK_CONFIGURE\n#endif\n#endif /* < 3.2.0 */\n\n#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(6,2))\n#undef ixgbe_get_netdev_tc_txq\n#define ixgbe_get_netdev_tc_txq(dev, tc) (&netdev_extended(dev)->qos_data.tc_to_txq[tc])\n#endif\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) )\ntypedef u32 kni_netdev_features_t;\n#undef PCI_EXP_TYPE_RC_EC\n#define PCI_EXP_TYPE_RC_EC\t0xa\t/* Root Complex Event Collector */\n#ifndef CONFIG_BQL\n#define netdev_tx_completed_queue(_q, _p, _b) do {} while (0)\n#define netdev_completed_queue(_n, _p, _b) do {} while (0)\n#define netdev_tx_sent_queue(_q, _b) do {} while (0)\n#define netdev_sent_queue(_n, _b) do {} while (0)\n#define netdev_tx_reset_queue(_q) do {} while (0)\n#define netdev_reset_queue(_n) do {} while (0)\n#endif\n#else /* ! < 3.3.0 */\ntypedef netdev_features_t kni_netdev_features_t;\n#define HAVE_INT_NDO_VLAN_RX_ADD_VID\n#ifdef ETHTOOL_SRXNTUPLE\n#undef ETHTOOL_SRXNTUPLE\n#endif\n#endif /* < 3.3.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0) )\n#ifndef NETIF_F_RXFCS\n#define NETIF_F_RXFCS\t0\n#endif /* NETIF_F_RXFCS */\n#ifndef NETIF_F_RXALL\n#define NETIF_F_RXALL\t0\n#endif /* NETIF_F_RXALL */\n\n#if !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0))\n#define NUMTCS_RETURNS_U8\n\nint _kc_simple_open(struct inode *inode, struct file *file);\n#define simple_open _kc_simple_open\n#endif /* !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0)) */\n\n\n#ifndef skb_add_rx_frag\n#define skb_add_rx_frag _kc_skb_add_rx_frag\nextern void _kc_skb_add_rx_frag(struct sk_buff *, int, struct page *,\n\t\t\t\tint, int, unsigned int);\n#endif\n#ifdef NET_ADDR_RANDOM\n#define eth_hw_addr_random(N) do { \\\n\trandom_ether_addr(N->dev_addr); \\\n\tN->addr_assign_type |= NET_ADDR_RANDOM; \\\n\t} while (0)\n#else /* NET_ADDR_RANDOM */\n#define eth_hw_addr_random(N) random_ether_addr(N->dev_addr)\n#endif /* NET_ADDR_RANDOM */\n#else /* < 3.4.0 */\n#include \n#endif /* >= 3.4.0 */\n\n/*****************************************************************************/\n#if defined(E1000E_PTP) || defined(IGB_PTP) || defined(IXGBE_PTP) || defined(I40E_PTP)\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) ) && IS_ENABLED(CONFIG_PTP_1588_CLOCK)\n#define HAVE_PTP_1588_CLOCK\n#else\n#error Cannot enable PTP Hardware Clock support due to a pre-3.0 kernel version or CONFIG_PTP_1588_CLOCK not enabled in the kernel\n#endif /* > 3.0.0 && IS_ENABLED(CONFIG_PTP_1588_CLOCK) */\n#endif /* E1000E_PTP || IGB_PTP || IXGBE_PTP || I40E_PTP */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) )\n#define skb_tx_timestamp(skb) do {} while (0)\nstatic inline bool __kc_ether_addr_equal(const u8 *addr1, const u8 *addr2)\n{\n\treturn !compare_ether_addr(addr1, addr2);\n}\n#define ether_addr_equal(_addr1, _addr2) __kc_ether_addr_equal((_addr1),(_addr2))\n#else\n#define HAVE_FDB_OPS\n#define HAVE_ETHTOOL_GET_TS_INFO\n#endif /* < 3.5.0 */\n\n/*****************************************************************************/\n#include \n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0) )\n#define PCI_EXP_LNKCAP2\t\t44\t/* Link Capability 2 */\n\n#ifndef MDIO_EEE_100TX\n#define MDIO_EEE_100TX\t\t0x0002\t/* 100TX EEE cap */\n#endif\n#ifndef MDIO_EEE_1000T\n#define MDIO_EEE_1000T\t\t0x0004\t/* 1000T EEE cap */\n#endif\n#ifndef MDIO_EEE_10GT\n#define MDIO_EEE_10GT\t\t0x0008\t/* 10GT EEE cap */\n#endif\n#ifndef MDIO_EEE_1000KX\n#define MDIO_EEE_1000KX\t\t0x0010\t/* 1000KX EEE cap */\n#endif\n#ifndef MDIO_EEE_10GKX4\n#define MDIO_EEE_10GKX4\t\t0x0020\t/* 10G KX4 EEE cap */\n#endif\n#ifndef MDIO_EEE_10GKR\n#define MDIO_EEE_10GKR\t\t0x0040\t/* 10G KR EEE cap */\n#endif\n#endif /* < 3.6.0 */\n\n/******************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0) )\n#ifndef ADVERTISED_40000baseKR4_Full\n/* these defines were all added in one commit, so should be safe\n * to trigger activiation on one define\n */\n#define SUPPORTED_40000baseKR4_Full\t(1 << 23)\n#define SUPPORTED_40000baseCR4_Full\t(1 << 24)\n#define SUPPORTED_40000baseSR4_Full\t(1 << 25)\n#define SUPPORTED_40000baseLR4_Full\t(1 << 26)\n#define ADVERTISED_40000baseKR4_Full\t(1 << 23)\n#define ADVERTISED_40000baseCR4_Full\t(1 << 24)\n#define ADVERTISED_40000baseSR4_Full\t(1 << 25)\n#define ADVERTISED_40000baseLR4_Full\t(1 << 26)\n#endif\n\n/**\n * mmd_eee_cap_to_ethtool_sup_t\n * @eee_cap: value of the MMD EEE Capability register\n *\n * A small helper function that translates MMD EEE Capability (3.20) bits\n * to ethtool supported settings.\n */\nstatic inline u32 __kc_mmd_eee_cap_to_ethtool_sup_t(u16 eee_cap)\n{\n\tu32 supported = 0;\n\n\tif (eee_cap & MDIO_EEE_100TX)\n\t\tsupported |= SUPPORTED_100baseT_Full;\n\tif (eee_cap & MDIO_EEE_1000T)\n\t\tsupported |= SUPPORTED_1000baseT_Full;\n\tif (eee_cap & MDIO_EEE_10GT)\n\t\tsupported |= SUPPORTED_10000baseT_Full;\n\tif (eee_cap & MDIO_EEE_1000KX)\n\t\tsupported |= SUPPORTED_1000baseKX_Full;\n\tif (eee_cap & MDIO_EEE_10GKX4)\n\t\tsupported |= SUPPORTED_10000baseKX4_Full;\n\tif (eee_cap & MDIO_EEE_10GKR)\n\t\tsupported |= SUPPORTED_10000baseKR_Full;\n\n\treturn supported;\n}\n#define mmd_eee_cap_to_ethtool_sup_t(eee_cap) \\\n\t__kc_mmd_eee_cap_to_ethtool_sup_t(eee_cap)\n\n/**\n * mmd_eee_adv_to_ethtool_adv_t\n * @eee_adv: value of the MMD EEE Advertisement/Link Partner Ability registers\n *\n * A small helper function that translates the MMD EEE Advertisement (7.60)\n * and MMD EEE Link Partner Ability (7.61) bits to ethtool advertisement\n * settings.\n */\nstatic inline u32 __kc_mmd_eee_adv_to_ethtool_adv_t(u16 eee_adv)\n{\n\tu32 adv = 0;\n\n\tif (eee_adv & MDIO_EEE_100TX)\n\t\tadv |= ADVERTISED_100baseT_Full;\n\tif (eee_adv & MDIO_EEE_1000T)\n\t\tadv |= ADVERTISED_1000baseT_Full;\n\tif (eee_adv & MDIO_EEE_10GT)\n\t\tadv |= ADVERTISED_10000baseT_Full;\n\tif (eee_adv & MDIO_EEE_1000KX)\n\t\tadv |= ADVERTISED_1000baseKX_Full;\n\tif (eee_adv & MDIO_EEE_10GKX4)\n\t\tadv |= ADVERTISED_10000baseKX4_Full;\n\tif (eee_adv & MDIO_EEE_10GKR)\n\t\tadv |= ADVERTISED_10000baseKR_Full;\n\n\treturn adv;\n}\n#define mmd_eee_adv_to_ethtool_adv_t(eee_adv) \\\n\t__kc_mmd_eee_adv_to_ethtool_adv_t(eee_adv)\n\n/**\n * ethtool_adv_to_mmd_eee_adv_t\n * @adv: the ethtool advertisement settings\n *\n * A small helper function that translates ethtool advertisement settings\n * to EEE advertisements for the MMD EEE Advertisement (7.60) and\n * MMD EEE Link Partner Ability (7.61) registers.\n */\nstatic inline u16 __kc_ethtool_adv_to_mmd_eee_adv_t(u32 adv)\n{\n\tu16 reg = 0;\n\n\tif (adv & ADVERTISED_100baseT_Full)\n\t\treg |= MDIO_EEE_100TX;\n\tif (adv & ADVERTISED_1000baseT_Full)\n\t\treg |= MDIO_EEE_1000T;\n\tif (adv & ADVERTISED_10000baseT_Full)\n\t\treg |= MDIO_EEE_10GT;\n\tif (adv & ADVERTISED_1000baseKX_Full)\n\t\treg |= MDIO_EEE_1000KX;\n\tif (adv & ADVERTISED_10000baseKX4_Full)\n\t\treg |= MDIO_EEE_10GKX4;\n\tif (adv & ADVERTISED_10000baseKR_Full)\n\t\treg |= MDIO_EEE_10GKR;\n\n\treturn reg;\n}\n#define ethtool_adv_to_mmd_eee_adv_t(adv) \\\n\t__kc_ethtool_adv_to_mmd_eee_adv_t(adv)\n\n#ifndef pci_pcie_type\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) )\nstatic inline u8 pci_pcie_type(struct pci_dev *pdev)\n{\n\tint pos;\n\tu16 reg16;\n\n\tpos = pci_find_capability(pdev, PCI_CAP_ID_EXP);\n\tif (!pos)\n\t\tBUG();\n\tpci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);\n\treturn (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;\n}\n#else /* < 2.6.24 */\n#define pci_pcie_type(x)\t(x)->pcie_type\n#endif /* < 2.6.24 */\n#endif /* pci_pcie_type */\n\n#define ptp_clock_register(caps, args...) ptp_clock_register(caps)\n\n#ifndef PCI_EXP_LNKSTA2\nint __kc_pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);\n#define pcie_capability_read_word(d,p,v) __kc_pcie_capability_read_word(d,p,v)\nint __kc_pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);\n#define pcie_capability_write_word(d,p,v) __kc_pcie_capability_write_word(d,p,v)\nint __kc_pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,\n\t\t\t\t\t u16 clear, u16 set);\n#define pcie_capability_clear_and_set_word(d,p,c,s) \\\n\t__kc_pcie_capability_clear_and_set_word(d,p,c,s)\n\n#define PCI_EXP_LNKSTA2\t\t50\t/* Link Status 2 */\n\nstatic inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,\n\t\t\t\t\t u16 clear)\n{\n\treturn __kc_pcie_capability_clear_and_set_word(dev, pos, clear, 0);\n}\n#endif /* !PCI_EXP_LNKSTA2 */\n\n#if (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0))\n#define USE_CONST_DEV_UC_CHAR\n#endif\n\n#else /* >= 3.7.0 */\n#define HAVE_CONST_STRUCT_PCI_ERROR_HANDLERS\n#define USE_CONST_DEV_UC_CHAR\n#endif /* >= 3.7.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0) )\n#ifndef PCI_EXP_LNKCTL_ASPM_L0S\n#define PCI_EXP_LNKCTL_ASPM_L0S 0x01\t/* L0s Enable */\n#endif\n#ifndef PCI_EXP_LNKCTL_ASPM_L1\n#define PCI_EXP_LNKCTL_ASPM_L1 0x02\t/* L1 Enable */\n#endif\n#define HAVE_CONFIG_HOTPLUG\n/* Reserved Ethernet Addresses per IEEE 802.1Q */\nstatic const u8 eth_reserved_addr_base[ETH_ALEN] __aligned(2) = {\n\t0x01, 0x80, 0xc2, 0x00, 0x00, 0x00 };\n#if !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0)) &&\\\n !(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,5))\nstatic inline bool is_link_local_ether_addr(const u8 *addr)\n{\n\t__be16 *a = (__be16 *)addr;\n\tstatic const __be16 *b = (const __be16 *)eth_reserved_addr_base;\n\tstatic const __be16 m = cpu_to_be16(0xfff0);\n\n\treturn ((a[0] ^ b[0]) | (a[1] ^ b[1]) | ((a[2] ^ b[2]) & m)) == 0;\n}\n#endif /* !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,3,0)) */\n#else /* >= 3.8.0 */\n#ifndef __devinit\n#define __devinit\n#define HAVE_ENCAP_CSUM_OFFLOAD\n#endif\n\n#ifndef __devinitdata\n#define __devinitdata\n#endif\n\n#ifndef __devexit\n#define __devexit\n#endif\n\n#ifndef __devexit_p\n#define __devexit_p\n#endif\n\n#ifndef HAVE_SRIOV_CONFIGURE\n#define HAVE_SRIOV_CONFIGURE\n#endif\n\n#define HAVE_BRIDGE_ATTRIBS\n#ifndef BRIDGE_MODE_VEB\n#define BRIDGE_MODE_VEB\t\t0\t/* Default loopback mode */\n#endif /* BRIDGE_MODE_VEB */\n#ifndef BRIDGE_MODE_VEPA\n#define BRIDGE_MODE_VEPA\t1\t/* 802.1Qbg defined VEPA mode */\n#endif /* BRIDGE_MODE_VEPA */\n#endif /* >= 3.8.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0) )\n\n#undef hlist_entry\n#define hlist_entry(ptr, type, member) container_of(ptr,type,member)\n\n#undef hlist_entry_safe\n#define hlist_entry_safe(ptr, type, member) \\\n\t(ptr) ? hlist_entry(ptr, type, member) : NULL\n\n#undef hlist_for_each_entry\n#define hlist_for_each_entry(pos, head, member) \\\n\tfor (pos = hlist_entry_safe((head)->first, typeof(*(pos)), member); \\\n\t pos; \\\n\t pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))\n\n#undef hlist_for_each_entry_safe\n#define hlist_for_each_entry_safe(pos, n, head, member)\t\t \\\n\tfor (pos = hlist_entry_safe((head)->first, typeof(*pos), member); \\\n\t pos && ({ n = pos->member.next; 1; });\t\t\t \\\n\t pos = hlist_entry_safe(n, typeof(*pos), member))\n\n#ifdef CONFIG_XPS\nextern int __kc_netif_set_xps_queue(struct net_device *, struct cpumask *, u16);\n#define netif_set_xps_queue(_dev, _mask, _idx) __kc_netif_set_xps_queue((_dev), (_mask), (_idx))\n#else /* CONFIG_XPS */\n#define netif_set_xps_queue(_dev, _mask, _idx) do {} while (0)\n#endif /* CONFIG_XPS */\n\n#ifdef HAVE_NETDEV_SELECT_QUEUE\n#define _kc_hashrnd 0xd631614b /* not so random hash salt */\nextern u16 __kc_netdev_pick_tx(struct net_device *dev, struct sk_buff *skb);\n#define __netdev_pick_tx __kc_netdev_pick_tx\n#endif /* HAVE_NETDEV_SELECT_QUEUE */\n#else\n#define HAVE_BRIDGE_FILTER\n#define USE_DEFAULT_FDB_DEL_DUMP\n#endif /* < 3.9.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) )\n#ifdef CONFIG_PCI_IOV\nextern int __kc_pci_vfs_assigned(struct pci_dev *dev);\n#else\nstatic inline int __kc_pci_vfs_assigned(struct pci_dev *dev)\n{\n\treturn 0;\n}\n#endif\n#define pci_vfs_assigned(dev) __kc_pci_vfs_assigned(dev)\n\n#ifndef VLAN_TX_COOKIE_MAGIC\nstatic inline struct sk_buff *__kc__vlan_hwaccel_put_tag(struct sk_buff *skb,\n\t\t\t\t\t\t\t u16 vlan_tci)\n{\n#ifdef VLAN_TAG_PRESENT\n\tvlan_tci |= VLAN_TAG_PRESENT;\n#endif\n\tskb->vlan_tci = vlan_tci;\n return skb;\n}\n#define __vlan_hwaccel_put_tag(skb, vlan_proto, vlan_tci) \\\n\t__kc__vlan_hwaccel_put_tag(skb, vlan_tci)\n#endif\n\n#else /* >= 3.10.0 */\n#define HAVE_ENCAP_TSO_OFFLOAD\n#endif /* >= 3.10.0 */\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0) )\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,6)))\n#if (!(UBUNTU_KERNEL_CODE >= UBUNTU_KERNEL_VERSION(3,13,0,30,54) \\\n && (UBUNTU_RELEASE_CODE == UBUNTU_RELEASE_VERSION(12,4) \\\n || UBUNTU_RELEASE_CODE == UBUNTU_RELEASE_VERSION(14,4))))\n#if (!(SLE_VERSION_CODE == SLE_VERSION(12,0,0)))\n#ifdef NETIF_F_RXHASH\n#define PKT_HASH_TYPE_L3 0\nstatic inline void\nskb_set_hash(struct sk_buff *skb, __u32 hash, __always_unused int type)\n{\n\tskb->rxhash = hash;\n}\n#endif /* NETIF_F_RXHASH */\n#endif /* < SLES12 */\n#endif /* < 3.13.0-30.54 (Ubuntu 14.04) */\n#endif /* < RHEL7 */\n#endif /* < 3.14.0 */\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0) )\n#define SET_ETHTOOL_OPS(netdev, ops) ((netdev)->ethtool_ops = (ops))\n#define HAVE_VF_MIN_MAX_TXRATE 1\n#endif /* >= 3.16.0 */\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(3,19,0) )\n#define HAVE_NDO_FDB_ADD_VID\n#endif /* >= 3.19.0 */\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(4,0,0) )\n/* vlan_tx_xx functions got renamed to skb_vlan */\n#define vlan_tx_tag_get skb_vlan_tag_get\n#define vlan_tx_tag_present skb_vlan_tag_present\n#define HAVE_NDO_BRIDGE_SET_DEL_LINK_FLAGS\n#endif /* 4.0.0 */\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0) )\n/* ndo_bridge_getlink adds new nlflags parameter */\n#define HAVE_NDO_BRIDGE_GETLINK_FILTER_MASK\n#endif /* >= 4.1.0 */\n#endif /* _KCOMPAT_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/igb/kcompat_ethtool.c", "content": "/*******************************************************************************\n\n Intel(R) Gigabit Ethernet Linux driver\n Copyright(c) 2007-2013 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n/*\n * net/core/ethtool.c - Ethtool ioctl handler\n * Copyright (c) 2003 Matthew Wilcox \n *\n * This file is where we call all the ethtool_ops commands to get\n * the information ethtool needs. We fall back to calling do_ioctl()\n * for drivers which haven't been converted to ethtool_ops yet.\n *\n * It's GPL, stupid.\n *\n * Modification by sfeldma@pobox.com to work as backward compat\n * solution for pre-ethtool_ops kernels.\n *\t- copied struct ethtool_ops from ethtool.h\n *\t- defined SET_ETHTOOL_OPS\n *\t- put in some #ifndef NETIF_F_xxx wrappers\n *\t- changes refs to dev->ethtool_ops to ethtool_ops\n *\t- changed dev_ethtool to ethtool_ioctl\n * - remove EXPORT_SYMBOL()s\n * - added _kc_ prefix in built-in ethtool_op_xxx ops.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"kcompat.h\"\n\n#undef SUPPORTED_10000baseT_Full\n#define SUPPORTED_10000baseT_Full\t(1 << 12)\n#undef ADVERTISED_10000baseT_Full\n#define ADVERTISED_10000baseT_Full\t(1 << 12)\n#undef SPEED_10000\n#define SPEED_10000\t\t10000\n\n#undef ethtool_ops\n#define ethtool_ops _kc_ethtool_ops\n\nstruct _kc_ethtool_ops {\n\tint (*get_settings)(struct net_device *, struct ethtool_cmd *);\n\tint (*set_settings)(struct net_device *, struct ethtool_cmd *);\n\tvoid (*get_drvinfo)(struct net_device *, struct ethtool_drvinfo *);\n\tint (*get_regs_len)(struct net_device *);\n\tvoid (*get_regs)(struct net_device *, struct ethtool_regs *, void *);\n\tvoid (*get_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tint (*set_wol)(struct net_device *, struct ethtool_wolinfo *);\n\tu32 (*get_msglevel)(struct net_device *);\n\tvoid (*set_msglevel)(struct net_device *, u32);\n\tint (*nway_reset)(struct net_device *);\n\tu32 (*get_link)(struct net_device *);\n\tint (*get_eeprom_len)(struct net_device *);\n\tint (*get_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*set_eeprom)(struct net_device *, struct ethtool_eeprom *, u8 *);\n\tint (*get_coalesce)(struct net_device *, struct ethtool_coalesce *);\n\tint (*set_coalesce)(struct net_device *, struct ethtool_coalesce *);\n\tvoid (*get_ringparam)(struct net_device *, struct ethtool_ringparam *);\n\tint (*set_ringparam)(struct net_device *, struct ethtool_ringparam *);\n\tvoid (*get_pauseparam)(struct net_device *,\n\t struct ethtool_pauseparam*);\n\tint (*set_pauseparam)(struct net_device *,\n\t struct ethtool_pauseparam*);\n\tu32 (*get_rx_csum)(struct net_device *);\n\tint (*set_rx_csum)(struct net_device *, u32);\n\tu32 (*get_tx_csum)(struct net_device *);\n\tint (*set_tx_csum)(struct net_device *, u32);\n\tu32 (*get_sg)(struct net_device *);\n\tint (*set_sg)(struct net_device *, u32);\n\tu32 (*get_tso)(struct net_device *);\n\tint (*set_tso)(struct net_device *, u32);\n\tint (*self_test_count)(struct net_device *);\n\tvoid (*self_test)(struct net_device *, struct ethtool_test *, u64 *);\n\tvoid (*get_strings)(struct net_device *, u32 stringset, u8 *);\n\tint (*phys_id)(struct net_device *, u32);\n\tint (*get_stats_count)(struct net_device *);\n\tvoid (*get_ethtool_stats)(struct net_device *, struct ethtool_stats *,\n\t u64 *);\n} *ethtool_ops = NULL;\n\n#undef SET_ETHTOOL_OPS\n#define SET_ETHTOOL_OPS(netdev, ops) (ethtool_ops = (ops))\n\n/*\n * Some useful ethtool_ops methods that are device independent. If we find that\n * all drivers want to do the same thing here, we can turn these into dev_()\n * function calls.\n */\n\n#undef ethtool_op_get_link\n#define ethtool_op_get_link _kc_ethtool_op_get_link\nu32 _kc_ethtool_op_get_link(struct net_device *dev)\n{\n\treturn netif_carrier_ok(dev) ? 1 : 0;\n}\n\n#undef ethtool_op_get_tx_csum\n#define ethtool_op_get_tx_csum _kc_ethtool_op_get_tx_csum\nu32 _kc_ethtool_op_get_tx_csum(struct net_device *dev)\n{\n#ifdef NETIF_F_IP_CSUM\n\treturn (dev->features & NETIF_F_IP_CSUM) != 0;\n#else\n\treturn 0;\n#endif\n}\n\n#undef ethtool_op_set_tx_csum\n#define ethtool_op_set_tx_csum _kc_ethtool_op_set_tx_csum\nint _kc_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)\n{\n#ifdef NETIF_F_IP_CSUM\n\tif (data)\n#ifdef NETIF_F_IPV6_CSUM\n\t\tdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);\n\telse\n\t\tdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);\n#else\n\t\tdev->features |= NETIF_F_IP_CSUM;\n\telse\n\t\tdev->features &= ~NETIF_F_IP_CSUM;\n#endif\n#endif\n\n\treturn 0;\n}\n\n#undef ethtool_op_get_sg\n#define ethtool_op_get_sg _kc_ethtool_op_get_sg\nu32 _kc_ethtool_op_get_sg(struct net_device *dev)\n{\n#ifdef NETIF_F_SG\n\treturn (dev->features & NETIF_F_SG) != 0;\n#else\n\treturn 0;\n#endif\n}\n\n#undef ethtool_op_set_sg\n#define ethtool_op_set_sg _kc_ethtool_op_set_sg\nint _kc_ethtool_op_set_sg(struct net_device *dev, u32 data)\n{\n#ifdef NETIF_F_SG\n\tif (data)\n\t\tdev->features |= NETIF_F_SG;\n\telse\n\t\tdev->features &= ~NETIF_F_SG;\n#endif\n\n\treturn 0;\n}\n\n#undef ethtool_op_get_tso\n#define ethtool_op_get_tso _kc_ethtool_op_get_tso\nu32 _kc_ethtool_op_get_tso(struct net_device *dev)\n{\n#ifdef NETIF_F_TSO\n\treturn (dev->features & NETIF_F_TSO) != 0;\n#else\n\treturn 0;\n#endif\n}\n\n#undef ethtool_op_set_tso\n#define ethtool_op_set_tso _kc_ethtool_op_set_tso\nint _kc_ethtool_op_set_tso(struct net_device *dev, u32 data)\n{\n#ifdef NETIF_F_TSO\n\tif (data)\n\t\tdev->features |= NETIF_F_TSO;\n\telse\n\t\tdev->features &= ~NETIF_F_TSO;\n#endif\n\n\treturn 0;\n}\n\n/* Handlers for each ethtool command */\n\nstatic int ethtool_get_settings(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_cmd cmd = { ETHTOOL_GSET };\n\tint err;\n\n\tif (!ethtool_ops->get_settings)\n\t\treturn -EOPNOTSUPP;\n\n\terr = ethtool_ops->get_settings(dev, &cmd);\n\tif (err < 0)\n\t\treturn err;\n\n\tif (copy_to_user(useraddr, &cmd, sizeof(cmd)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nstatic int ethtool_set_settings(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_cmd cmd;\n\n\tif (!ethtool_ops->set_settings)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&cmd, useraddr, sizeof(cmd)))\n\t\treturn -EFAULT;\n\n\treturn ethtool_ops->set_settings(dev, &cmd);\n}\n\nstatic int ethtool_get_drvinfo(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_drvinfo info;\n\tstruct ethtool_ops *ops = ethtool_ops;\n\n\tif (!ops->get_drvinfo)\n\t\treturn -EOPNOTSUPP;\n\n\tmemset(&info, 0, sizeof(info));\n\tinfo.cmd = ETHTOOL_GDRVINFO;\n\tops->get_drvinfo(dev, &info);\n\n\tif (ops->self_test_count)\n\t\tinfo.testinfo_len = ops->self_test_count(dev);\n\tif (ops->get_stats_count)\n\t\tinfo.n_stats = ops->get_stats_count(dev);\n\tif (ops->get_regs_len)\n\t\tinfo.regdump_len = ops->get_regs_len(dev);\n\tif (ops->get_eeprom_len)\n\t\tinfo.eedump_len = ops->get_eeprom_len(dev);\n\n\tif (copy_to_user(useraddr, &info, sizeof(info)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nstatic int ethtool_get_regs(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_regs regs;\n\tstruct ethtool_ops *ops = ethtool_ops;\n\tvoid *regbuf;\n\tint reglen, ret;\n\n\tif (!ops->get_regs || !ops->get_regs_len)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(®s, useraddr, sizeof(regs)))\n\t\treturn -EFAULT;\n\n\treglen = ops->get_regs_len(dev);\n\tif (regs.len > reglen)\n\t\tregs.len = reglen;\n\n\tregbuf = kmalloc(reglen, GFP_USER);\n\tif (!regbuf)\n\t\treturn -ENOMEM;\n\n\tops->get_regs(dev, ®s, regbuf);\n\n\tret = -EFAULT;\n\tif (copy_to_user(useraddr, ®s, sizeof(regs)))\n\t\tgoto out;\n\tuseraddr += offsetof(struct ethtool_regs, data);\n\tif (copy_to_user(useraddr, regbuf, reglen))\n\t\tgoto out;\n\tret = 0;\n\nout:\n\tkfree(regbuf);\n\treturn ret;\n}\n\nstatic int ethtool_get_wol(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_wolinfo wol = { ETHTOOL_GWOL };\n\n\tif (!ethtool_ops->get_wol)\n\t\treturn -EOPNOTSUPP;\n\n\tethtool_ops->get_wol(dev, &wol);\n\n\tif (copy_to_user(useraddr, &wol, sizeof(wol)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nstatic int ethtool_set_wol(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_wolinfo wol;\n\n\tif (!ethtool_ops->set_wol)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&wol, useraddr, sizeof(wol)))\n\t\treturn -EFAULT;\n\n\treturn ethtool_ops->set_wol(dev, &wol);\n}\n\nstatic int ethtool_get_msglevel(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_value edata = { ETHTOOL_GMSGLVL };\n\n\tif (!ethtool_ops->get_msglevel)\n\t\treturn -EOPNOTSUPP;\n\n\tedata.data = ethtool_ops->get_msglevel(dev);\n\n\tif (copy_to_user(useraddr, &edata, sizeof(edata)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nstatic int ethtool_set_msglevel(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_value edata;\n\n\tif (!ethtool_ops->set_msglevel)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&edata, useraddr, sizeof(edata)))\n\t\treturn -EFAULT;\n\n\tethtool_ops->set_msglevel(dev, edata.data);\n\treturn 0;\n}\n\nstatic int ethtool_nway_reset(struct net_device *dev)\n{\n\tif (!ethtool_ops->nway_reset)\n\t\treturn -EOPNOTSUPP;\n\n\treturn ethtool_ops->nway_reset(dev);\n}\n\nstatic int ethtool_get_link(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_value edata = { ETHTOOL_GLINK };\n\n\tif (!ethtool_ops->get_link)\n\t\treturn -EOPNOTSUPP;\n\n\tedata.data = ethtool_ops->get_link(dev);\n\n\tif (copy_to_user(useraddr, &edata, sizeof(edata)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nstatic int ethtool_get_eeprom(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_eeprom eeprom;\n\tstruct ethtool_ops *ops = ethtool_ops;\n\tu8 *data;\n\tint ret;\n\n\tif (!ops->get_eeprom || !ops->get_eeprom_len)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&eeprom, useraddr, sizeof(eeprom)))\n\t\treturn -EFAULT;\n\n\t/* Check for wrap and zero */\n\tif (eeprom.offset + eeprom.len <= eeprom.offset)\n\t\treturn -EINVAL;\n\n\t/* Check for exceeding total eeprom len */\n\tif (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev))\n\t\treturn -EINVAL;\n\n\tdata = kmalloc(eeprom.len, GFP_USER);\n\tif (!data)\n\t\treturn -ENOMEM;\n\n\tret = -EFAULT;\n\tif (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len))\n\t\tgoto out;\n\n\tret = ops->get_eeprom(dev, &eeprom, data);\n\tif (ret)\n\t\tgoto out;\n\n\tret = -EFAULT;\n\tif (copy_to_user(useraddr, &eeprom, sizeof(eeprom)))\n\t\tgoto out;\n\tif (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len))\n\t\tgoto out;\n\tret = 0;\n\nout:\n\tkfree(data);\n\treturn ret;\n}\n\nstatic int ethtool_set_eeprom(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_eeprom eeprom;\n\tstruct ethtool_ops *ops = ethtool_ops;\n\tu8 *data;\n\tint ret;\n\n\tif (!ops->set_eeprom || !ops->get_eeprom_len)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&eeprom, useraddr, sizeof(eeprom)))\n\t\treturn -EFAULT;\n\n\t/* Check for wrap and zero */\n\tif (eeprom.offset + eeprom.len <= eeprom.offset)\n\t\treturn -EINVAL;\n\n\t/* Check for exceeding total eeprom len */\n\tif (eeprom.offset + eeprom.len > ops->get_eeprom_len(dev))\n\t\treturn -EINVAL;\n\n\tdata = kmalloc(eeprom.len, GFP_USER);\n\tif (!data)\n\t\treturn -ENOMEM;\n\n\tret = -EFAULT;\n\tif (copy_from_user(data, useraddr + sizeof(eeprom), eeprom.len))\n\t\tgoto out;\n\n\tret = ops->set_eeprom(dev, &eeprom, data);\n\tif (ret)\n\t\tgoto out;\n\n\tif (copy_to_user(useraddr + sizeof(eeprom), data, eeprom.len))\n\t\tret = -EFAULT;\n\nout:\n\tkfree(data);\n\treturn ret;\n}\n\nstatic int ethtool_get_coalesce(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_coalesce coalesce = { ETHTOOL_GCOALESCE };\n\n\tif (!ethtool_ops->get_coalesce)\n\t\treturn -EOPNOTSUPP;\n\n\tethtool_ops->get_coalesce(dev, &coalesce);\n\n\tif (copy_to_user(useraddr, &coalesce, sizeof(coalesce)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nstatic int ethtool_set_coalesce(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_coalesce coalesce;\n\n\tif (!ethtool_ops->get_coalesce)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&coalesce, useraddr, sizeof(coalesce)))\n\t\treturn -EFAULT;\n\n\treturn ethtool_ops->set_coalesce(dev, &coalesce);\n}\n\nstatic int ethtool_get_ringparam(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_ringparam ringparam = { ETHTOOL_GRINGPARAM };\n\n\tif (!ethtool_ops->get_ringparam)\n\t\treturn -EOPNOTSUPP;\n\n\tethtool_ops->get_ringparam(dev, &ringparam);\n\n\tif (copy_to_user(useraddr, &ringparam, sizeof(ringparam)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nstatic int ethtool_set_ringparam(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_ringparam ringparam;\n\n\tif (!ethtool_ops->get_ringparam)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&ringparam, useraddr, sizeof(ringparam)))\n\t\treturn -EFAULT;\n\n\treturn ethtool_ops->set_ringparam(dev, &ringparam);\n}\n\nstatic int ethtool_get_pauseparam(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_pauseparam pauseparam = { ETHTOOL_GPAUSEPARAM };\n\n\tif (!ethtool_ops->get_pauseparam)\n\t\treturn -EOPNOTSUPP;\n\n\tethtool_ops->get_pauseparam(dev, &pauseparam);\n\n\tif (copy_to_user(useraddr, &pauseparam, sizeof(pauseparam)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nstatic int ethtool_set_pauseparam(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_pauseparam pauseparam;\n\n\tif (!ethtool_ops->get_pauseparam)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&pauseparam, useraddr, sizeof(pauseparam)))\n\t\treturn -EFAULT;\n\n\treturn ethtool_ops->set_pauseparam(dev, &pauseparam);\n}\n\nstatic int ethtool_get_rx_csum(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_value edata = { ETHTOOL_GRXCSUM };\n\n\tif (!ethtool_ops->get_rx_csum)\n\t\treturn -EOPNOTSUPP;\n\n\tedata.data = ethtool_ops->get_rx_csum(dev);\n\n\tif (copy_to_user(useraddr, &edata, sizeof(edata)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nstatic int ethtool_set_rx_csum(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_value edata;\n\n\tif (!ethtool_ops->set_rx_csum)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&edata, useraddr, sizeof(edata)))\n\t\treturn -EFAULT;\n\n\tethtool_ops->set_rx_csum(dev, edata.data);\n\treturn 0;\n}\n\nstatic int ethtool_get_tx_csum(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_value edata = { ETHTOOL_GTXCSUM };\n\n\tif (!ethtool_ops->get_tx_csum)\n\t\treturn -EOPNOTSUPP;\n\n\tedata.data = ethtool_ops->get_tx_csum(dev);\n\n\tif (copy_to_user(useraddr, &edata, sizeof(edata)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nstatic int ethtool_set_tx_csum(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_value edata;\n\n\tif (!ethtool_ops->set_tx_csum)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&edata, useraddr, sizeof(edata)))\n\t\treturn -EFAULT;\n\n\treturn ethtool_ops->set_tx_csum(dev, edata.data);\n}\n\nstatic int ethtool_get_sg(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_value edata = { ETHTOOL_GSG };\n\n\tif (!ethtool_ops->get_sg)\n\t\treturn -EOPNOTSUPP;\n\n\tedata.data = ethtool_ops->get_sg(dev);\n\n\tif (copy_to_user(useraddr, &edata, sizeof(edata)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nstatic int ethtool_set_sg(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_value edata;\n\n\tif (!ethtool_ops->set_sg)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&edata, useraddr, sizeof(edata)))\n\t\treturn -EFAULT;\n\n\treturn ethtool_ops->set_sg(dev, edata.data);\n}\n\nstatic int ethtool_get_tso(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_value edata = { ETHTOOL_GTSO };\n\n\tif (!ethtool_ops->get_tso)\n\t\treturn -EOPNOTSUPP;\n\n\tedata.data = ethtool_ops->get_tso(dev);\n\n\tif (copy_to_user(useraddr, &edata, sizeof(edata)))\n\t\treturn -EFAULT;\n\treturn 0;\n}\n\nstatic int ethtool_set_tso(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_value edata;\n\n\tif (!ethtool_ops->set_tso)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&edata, useraddr, sizeof(edata)))\n\t\treturn -EFAULT;\n\n\treturn ethtool_ops->set_tso(dev, edata.data);\n}\n\nstatic int ethtool_self_test(struct net_device *dev, char *useraddr)\n{\n\tstruct ethtool_test test;\n\tstruct ethtool_ops *ops = ethtool_ops;\n\tu64 *data;\n\tint ret;\n\n\tif (!ops->self_test || !ops->self_test_count)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&test, useraddr, sizeof(test)))\n\t\treturn -EFAULT;\n\n\ttest.len = ops->self_test_count(dev);\n\tdata = kmalloc(test.len * sizeof(u64), GFP_USER);\n\tif (!data)\n\t\treturn -ENOMEM;\n\n\tops->self_test(dev, &test, data);\n\n\tret = -EFAULT;\n\tif (copy_to_user(useraddr, &test, sizeof(test)))\n\t\tgoto out;\n\tuseraddr += sizeof(test);\n\tif (copy_to_user(useraddr, data, test.len * sizeof(u64)))\n\t\tgoto out;\n\tret = 0;\n\nout:\n\tkfree(data);\n\treturn ret;\n}\n\nstatic int ethtool_get_strings(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_gstrings gstrings;\n\tstruct ethtool_ops *ops = ethtool_ops;\n\tu8 *data;\n\tint ret;\n\n\tif (!ops->get_strings)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&gstrings, useraddr, sizeof(gstrings)))\n\t\treturn -EFAULT;\n\n\tswitch (gstrings.string_set) {\n\tcase ETH_SS_TEST:\n\t\tif (!ops->self_test_count)\n\t\t\treturn -EOPNOTSUPP;\n\t\tgstrings.len = ops->self_test_count(dev);\n\t\tbreak;\n\tcase ETH_SS_STATS:\n\t\tif (!ops->get_stats_count)\n\t\t\treturn -EOPNOTSUPP;\n\t\tgstrings.len = ops->get_stats_count(dev);\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tdata = kmalloc(gstrings.len * ETH_GSTRING_LEN, GFP_USER);\n\tif (!data)\n\t\treturn -ENOMEM;\n\n\tops->get_strings(dev, gstrings.string_set, data);\n\n\tret = -EFAULT;\n\tif (copy_to_user(useraddr, &gstrings, sizeof(gstrings)))\n\t\tgoto out;\n\tuseraddr += sizeof(gstrings);\n\tif (copy_to_user(useraddr, data, gstrings.len * ETH_GSTRING_LEN))\n\t\tgoto out;\n\tret = 0;\n\nout:\n\tkfree(data);\n\treturn ret;\n}\n\nstatic int ethtool_phys_id(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_value id;\n\n\tif (!ethtool_ops->phys_id)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&id, useraddr, sizeof(id)))\n\t\treturn -EFAULT;\n\n\treturn ethtool_ops->phys_id(dev, id.data);\n}\n\nstatic int ethtool_get_stats(struct net_device *dev, void *useraddr)\n{\n\tstruct ethtool_stats stats;\n\tstruct ethtool_ops *ops = ethtool_ops;\n\tu64 *data;\n\tint ret;\n\n\tif (!ops->get_ethtool_stats || !ops->get_stats_count)\n\t\treturn -EOPNOTSUPP;\n\n\tif (copy_from_user(&stats, useraddr, sizeof(stats)))\n\t\treturn -EFAULT;\n\n\tstats.n_stats = ops->get_stats_count(dev);\n\tdata = kmalloc(stats.n_stats * sizeof(u64), GFP_USER);\n\tif (!data)\n\t\treturn -ENOMEM;\n\n\tops->get_ethtool_stats(dev, &stats, data);\n\n\tret = -EFAULT;\n\tif (copy_to_user(useraddr, &stats, sizeof(stats)))\n\t\tgoto out;\n\tuseraddr += sizeof(stats);\n\tif (copy_to_user(useraddr, data, stats.n_stats * sizeof(u64)))\n\t\tgoto out;\n\tret = 0;\n\nout:\n\tkfree(data);\n\treturn ret;\n}\n\n/* The main entry point in this file. Called from net/core/dev.c */\n\n#define ETHTOOL_OPS_COMPAT\nint ethtool_ioctl(struct ifreq *ifr)\n{\n\tstruct net_device *dev = __dev_get_by_name(ifr->ifr_name);\n\tvoid *useraddr = (void *) ifr->ifr_data;\n\tu32 ethcmd;\n\n\t/*\n\t * XXX: This can be pushed down into the ethtool_* handlers that\n\t * need it. Keep existing behavior for the moment.\n\t */\n\tif (!capable(CAP_NET_ADMIN))\n\t\treturn -EPERM;\n\n\tif (!dev || !netif_device_present(dev))\n\t\treturn -ENODEV;\n\n\tif (copy_from_user(ðcmd, useraddr, sizeof (ethcmd)))\n\t\treturn -EFAULT;\n\n\tswitch (ethcmd) {\n\tcase ETHTOOL_GSET:\n\t\treturn ethtool_get_settings(dev, useraddr);\n\tcase ETHTOOL_SSET:\n\t\treturn ethtool_set_settings(dev, useraddr);\n\tcase ETHTOOL_GDRVINFO:\n\t\treturn ethtool_get_drvinfo(dev, useraddr);\n\tcase ETHTOOL_GREGS:\n\t\treturn ethtool_get_regs(dev, useraddr);\n\tcase ETHTOOL_GWOL:\n\t\treturn ethtool_get_wol(dev, useraddr);\n\tcase ETHTOOL_SWOL:\n\t\treturn ethtool_set_wol(dev, useraddr);\n\tcase ETHTOOL_GMSGLVL:\n\t\treturn ethtool_get_msglevel(dev, useraddr);\n\tcase ETHTOOL_SMSGLVL:\n\t\treturn ethtool_set_msglevel(dev, useraddr);\n\tcase ETHTOOL_NWAY_RST:\n\t\treturn ethtool_nway_reset(dev);\n\tcase ETHTOOL_GLINK:\n\t\treturn ethtool_get_link(dev, useraddr);\n\tcase ETHTOOL_GEEPROM:\n\t\treturn ethtool_get_eeprom(dev, useraddr);\n\tcase ETHTOOL_SEEPROM:\n\t\treturn ethtool_set_eeprom(dev, useraddr);\n\tcase ETHTOOL_GCOALESCE:\n\t\treturn ethtool_get_coalesce(dev, useraddr);\n\tcase ETHTOOL_SCOALESCE:\n\t\treturn ethtool_set_coalesce(dev, useraddr);\n\tcase ETHTOOL_GRINGPARAM:\n\t\treturn ethtool_get_ringparam(dev, useraddr);\n\tcase ETHTOOL_SRINGPARAM:\n\t\treturn ethtool_set_ringparam(dev, useraddr);\n\tcase ETHTOOL_GPAUSEPARAM:\n\t\treturn ethtool_get_pauseparam(dev, useraddr);\n\tcase ETHTOOL_SPAUSEPARAM:\n\t\treturn ethtool_set_pauseparam(dev, useraddr);\n\tcase ETHTOOL_GRXCSUM:\n\t\treturn ethtool_get_rx_csum(dev, useraddr);\n\tcase ETHTOOL_SRXCSUM:\n\t\treturn ethtool_set_rx_csum(dev, useraddr);\n\tcase ETHTOOL_GTXCSUM:\n\t\treturn ethtool_get_tx_csum(dev, useraddr);\n\tcase ETHTOOL_STXCSUM:\n\t\treturn ethtool_set_tx_csum(dev, useraddr);\n\tcase ETHTOOL_GSG:\n\t\treturn ethtool_get_sg(dev, useraddr);\n\tcase ETHTOOL_SSG:\n\t\treturn ethtool_set_sg(dev, useraddr);\n\tcase ETHTOOL_GTSO:\n\t\treturn ethtool_get_tso(dev, useraddr);\n\tcase ETHTOOL_STSO:\n\t\treturn ethtool_set_tso(dev, useraddr);\n\tcase ETHTOOL_TEST:\n\t\treturn ethtool_self_test(dev, useraddr);\n\tcase ETHTOOL_GSTRINGS:\n\t\treturn ethtool_get_strings(dev, useraddr);\n\tcase ETHTOOL_PHYS_ID:\n\t\treturn ethtool_phys_id(dev, useraddr);\n\tcase ETHTOOL_GSTATS:\n\t\treturn ethtool_get_stats(dev, useraddr);\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n\n\treturn -EOPNOTSUPP;\n}\n\n#define mii_if_info _kc_mii_if_info\nstruct _kc_mii_if_info {\n\tint phy_id;\n\tint advertising;\n\tint phy_id_mask;\n\tint reg_num_mask;\n\n\tunsigned int full_duplex : 1;\t/* is full duplex? */\n\tunsigned int force_media : 1;\t/* is autoneg. disabled? */\n\n\tstruct net_device *dev;\n\tint (*mdio_read) (struct net_device *dev, int phy_id, int location);\n\tvoid (*mdio_write) (struct net_device *dev, int phy_id, int location, int val);\n};\n\nstruct ethtool_cmd;\nstruct mii_ioctl_data;\n\n#undef mii_link_ok\n#define mii_link_ok _kc_mii_link_ok\n#undef mii_nway_restart\n#define mii_nway_restart _kc_mii_nway_restart\n#undef mii_ethtool_gset\n#define mii_ethtool_gset _kc_mii_ethtool_gset\n#undef mii_ethtool_sset\n#define mii_ethtool_sset _kc_mii_ethtool_sset\n#undef mii_check_link\n#define mii_check_link _kc_mii_check_link\nextern int _kc_mii_link_ok (struct mii_if_info *mii);\nextern int _kc_mii_nway_restart (struct mii_if_info *mii);\nextern int _kc_mii_ethtool_gset(struct mii_if_info *mii,\n struct ethtool_cmd *ecmd);\nextern int _kc_mii_ethtool_sset(struct mii_if_info *mii,\n struct ethtool_cmd *ecmd);\nextern void _kc_mii_check_link (struct mii_if_info *mii);\n#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,4,6) )\n#undef generic_mii_ioctl\n#define generic_mii_ioctl _kc_generic_mii_ioctl\nextern int _kc_generic_mii_ioctl(struct mii_if_info *mii_if,\n struct mii_ioctl_data *mii_data, int cmd,\n unsigned int *duplex_changed);\n#endif /* > 2.4.6 */\n\n\nstruct _kc_pci_dev_ext {\n\tstruct pci_dev *dev;\n\tvoid *pci_drvdata;\n\tstruct pci_driver *driver;\n};\n\nstruct _kc_net_dev_ext {\n\tstruct net_device *dev;\n\tunsigned int carrier;\n};\n\n\n/**************************************/\n/* mii support */\n\nint _kc_mii_ethtool_gset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)\n{\n\tstruct net_device *dev = mii->dev;\n\tu32 advert, bmcr, lpa, nego;\n\n\tecmd->supported =\n\t (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |\n\t SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |\n\t SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);\n\n\t/* only supports twisted-pair */\n\tecmd->port = PORT_MII;\n\n\t/* only supports internal transceiver */\n\tecmd->transceiver = XCVR_INTERNAL;\n\n\t/* this isn't fully supported at higher layers */\n\tecmd->phy_address = mii->phy_id;\n\n\tecmd->advertising = ADVERTISED_TP | ADVERTISED_MII;\n\tadvert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE);\n\tif (advert & ADVERTISE_10HALF)\n\t\tecmd->advertising |= ADVERTISED_10baseT_Half;\n\tif (advert & ADVERTISE_10FULL)\n\t\tecmd->advertising |= ADVERTISED_10baseT_Full;\n\tif (advert & ADVERTISE_100HALF)\n\t\tecmd->advertising |= ADVERTISED_100baseT_Half;\n\tif (advert & ADVERTISE_100FULL)\n\t\tecmd->advertising |= ADVERTISED_100baseT_Full;\n\n\tbmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);\n\tlpa = mii->mdio_read(dev, mii->phy_id, MII_LPA);\n\tif (bmcr & BMCR_ANENABLE) {\n\t\tecmd->advertising |= ADVERTISED_Autoneg;\n\t\tecmd->autoneg = AUTONEG_ENABLE;\n\n\t\tnego = mii_nway_result(advert & lpa);\n\t\tif (nego == LPA_100FULL || nego == LPA_100HALF)\n\t\t\tecmd->speed = SPEED_100;\n\t\telse\n\t\t\tecmd->speed = SPEED_10;\n\t\tif (nego == LPA_100FULL || nego == LPA_10FULL) {\n\t\t\tecmd->duplex = DUPLEX_FULL;\n\t\t\tmii->full_duplex = 1;\n\t\t} else {\n\t\t\tecmd->duplex = DUPLEX_HALF;\n\t\t\tmii->full_duplex = 0;\n\t\t}\n\t} else {\n\t\tecmd->autoneg = AUTONEG_DISABLE;\n\n\t\tecmd->speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;\n\t\tecmd->duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;\n\t}\n\n\t/* ignore maxtxpkt, maxrxpkt for now */\n\n\treturn 0;\n}\n\nint _kc_mii_ethtool_sset(struct mii_if_info *mii, struct ethtool_cmd *ecmd)\n{\n\tstruct net_device *dev = mii->dev;\n\n\tif (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)\n\t\treturn -EINVAL;\n\tif (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)\n\t\treturn -EINVAL;\n\tif (ecmd->port != PORT_MII)\n\t\treturn -EINVAL;\n\tif (ecmd->transceiver != XCVR_INTERNAL)\n\t\treturn -EINVAL;\n\tif (ecmd->phy_address != mii->phy_id)\n\t\treturn -EINVAL;\n\tif (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)\n\t\treturn -EINVAL;\n\n\t/* ignore supported, maxtxpkt, maxrxpkt */\n\n\tif (ecmd->autoneg == AUTONEG_ENABLE) {\n\t\tu32 bmcr, advert, tmp;\n\n\t\tif ((ecmd->advertising & (ADVERTISED_10baseT_Half |\n\t\t\t\t\t ADVERTISED_10baseT_Full |\n\t\t\t\t\t ADVERTISED_100baseT_Half |\n\t\t\t\t\t ADVERTISED_100baseT_Full)) == 0)\n\t\t\treturn -EINVAL;\n\n\t\t/* advertise only what has been requested */\n\t\tadvert = mii->mdio_read(dev, mii->phy_id, MII_ADVERTISE);\n\t\ttmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);\n\t\tif (ADVERTISED_10baseT_Half)\n\t\t\ttmp |= ADVERTISE_10HALF;\n\t\tif (ADVERTISED_10baseT_Full)\n\t\t\ttmp |= ADVERTISE_10FULL;\n\t\tif (ADVERTISED_100baseT_Half)\n\t\t\ttmp |= ADVERTISE_100HALF;\n\t\tif (ADVERTISED_100baseT_Full)\n\t\t\ttmp |= ADVERTISE_100FULL;\n\t\tif (advert != tmp) {\n\t\t\tmii->mdio_write(dev, mii->phy_id, MII_ADVERTISE, tmp);\n\t\t\tmii->advertising = tmp;\n\t\t}\n\n\t\t/* turn on autonegotiation, and force a renegotiate */\n\t\tbmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);\n\t\tbmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);\n\t\tmii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr);\n\n\t\tmii->force_media = 0;\n\t} else {\n\t\tu32 bmcr, tmp;\n\n\t\t/* turn off auto negotiation, set speed and duplexity */\n\t\tbmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);\n\t\ttmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);\n\t\tif (ecmd->speed == SPEED_100)\n\t\t\ttmp |= BMCR_SPEED100;\n\t\tif (ecmd->duplex == DUPLEX_FULL) {\n\t\t\ttmp |= BMCR_FULLDPLX;\n\t\t\tmii->full_duplex = 1;\n\t\t} else\n\t\t\tmii->full_duplex = 0;\n\t\tif (bmcr != tmp)\n\t\t\tmii->mdio_write(dev, mii->phy_id, MII_BMCR, tmp);\n\n\t\tmii->force_media = 1;\n\t}\n\treturn 0;\n}\n\nint _kc_mii_link_ok (struct mii_if_info *mii)\n{\n\t/* first, a dummy read, needed to latch some MII phys */\n\tmii->mdio_read(mii->dev, mii->phy_id, MII_BMSR);\n\tif (mii->mdio_read(mii->dev, mii->phy_id, MII_BMSR) & BMSR_LSTATUS)\n\t\treturn 1;\n\treturn 0;\n}\n\nint _kc_mii_nway_restart (struct mii_if_info *mii)\n{\n\tint bmcr;\n\tint r = -EINVAL;\n\n\t/* if autoneg is off, it's an error */\n\tbmcr = mii->mdio_read(mii->dev, mii->phy_id, MII_BMCR);\n\n\tif (bmcr & BMCR_ANENABLE) {\n\t\tbmcr |= BMCR_ANRESTART;\n\t\tmii->mdio_write(mii->dev, mii->phy_id, MII_BMCR, bmcr);\n\t\tr = 0;\n\t}\n\n\treturn r;\n}\n\nvoid _kc_mii_check_link (struct mii_if_info *mii)\n{\n\tint cur_link = mii_link_ok(mii);\n\tint prev_link = netif_carrier_ok(mii->dev);\n\n\tif (cur_link && !prev_link)\n\t\tnetif_carrier_on(mii->dev);\n\telse if (prev_link && !cur_link)\n\t\tnetif_carrier_off(mii->dev);\n}\n\n#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,4,6) )\nint _kc_generic_mii_ioctl(struct mii_if_info *mii_if,\n struct mii_ioctl_data *mii_data, int cmd,\n unsigned int *duplex_chg_out)\n{\n\tint rc = 0;\n\tunsigned int duplex_changed = 0;\n\n\tif (duplex_chg_out)\n\t\t*duplex_chg_out = 0;\n\n\tmii_data->phy_id &= mii_if->phy_id_mask;\n\tmii_data->reg_num &= mii_if->reg_num_mask;\n\n\tswitch(cmd) {\n\tcase SIOCDEVPRIVATE:\t/* binary compat, remove in 2.5 */\n\tcase SIOCGMIIPHY:\n\t\tmii_data->phy_id = mii_if->phy_id;\n\t\t/* fall through */\n\n\tcase SIOCDEVPRIVATE + 1:/* binary compat, remove in 2.5 */\n\tcase SIOCGMIIREG:\n\t\tmii_data->val_out =\n\t\t\tmii_if->mdio_read(mii_if->dev, mii_data->phy_id,\n\t\t\t\t\t mii_data->reg_num);\n\t\tbreak;\n\n\tcase SIOCDEVPRIVATE + 2:/* binary compat, remove in 2.5 */\n\tcase SIOCSMIIREG: {\n\t\tu16 val = mii_data->val_in;\n\n\t\tif (!capable(CAP_NET_ADMIN))\n\t\t\treturn -EPERM;\n\n\t\tif (mii_data->phy_id == mii_if->phy_id) {\n\t\t\tswitch(mii_data->reg_num) {\n\t\t\tcase MII_BMCR: {\n\t\t\t\tunsigned int new_duplex = 0;\n\t\t\t\tif (val & (BMCR_RESET|BMCR_ANENABLE))\n\t\t\t\t\tmii_if->force_media = 0;\n\t\t\t\telse\n\t\t\t\t\tmii_if->force_media = 1;\n\t\t\t\tif (mii_if->force_media &&\n\t\t\t\t (val & BMCR_FULLDPLX))\n\t\t\t\t\tnew_duplex = 1;\n\t\t\t\tif (mii_if->full_duplex != new_duplex) {\n\t\t\t\t\tduplex_changed = 1;\n\t\t\t\t\tmii_if->full_duplex = new_duplex;\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tcase MII_ADVERTISE:\n\t\t\t\tmii_if->advertising = val;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\t/* do nothing */\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tmii_if->mdio_write(mii_if->dev, mii_data->phy_id,\n\t\t\t\t mii_data->reg_num, val);\n\t\tbreak;\n\t}\n\n\tdefault:\n\t\trc = -EOPNOTSUPP;\n\t\tbreak;\n\t}\n\n\tif ((rc == 0) && (duplex_chg_out) && (duplex_changed))\n\t\t*duplex_chg_out = 1;\n\n\treturn rc;\n}\n#endif /* > 2.4.6 */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/COPYING", "content": "\n\"This software program is licensed subject to the GNU General Public License \n(GPL). Version 2, June 1991, available at \n\"\n\nGNU General Public License \n\nVersion 2, June 1991\n\nCopyright (C) 1989, 1991 Free Software Foundation, Inc. \n59 Temple Place - Suite 330, Boston, MA 02111-1307, USA\n\nEveryone is permitted to copy and distribute verbatim copies of this license\ndocument, but changing it is not allowed.\n\nPreamble\n\nThe licenses for most software are designed to take away your freedom to \nshare and change it. By contrast, the GNU General Public License is intended\nto guarantee your freedom to share and change free software--to make sure \nthe software is free for all its users. This General Public License applies \nto most of the Free Software Foundation's software and to any other program \nwhose authors commit to using it. (Some other Free Software Foundation \nsoftware is covered by the GNU Library General Public License instead.) You \ncan apply it to your programs, too.\n\nWhen we speak of free software, we are referring to freedom, not price. Our\nGeneral Public Licenses are designed to make sure that you have the freedom \nto distribute copies of free software (and charge for this service if you \nwish), that you receive source code or can get it if you want it, that you \ncan change the software or use pieces of it in new free programs; and that \nyou know you can do these things.\n\nTo protect your rights, we need to make restrictions that forbid anyone to \ndeny you these rights or to ask you to surrender the rights. These \nrestrictions translate to certain responsibilities for you if you distribute\ncopies of the software, or if you modify it.\n\nFor example, if you distribute copies of such a program, whether gratis or \nfor a fee, you must give the recipients all the rights that you have. You \nmust make sure that they, too, receive or can get the source code. And you \nmust show them these terms so they know their rights.\n \nWe protect your rights with two steps: (1) copyright the software, and (2) \noffer you this license which gives you legal permission to copy, distribute \nand/or modify the software. \n\nAlso, for each author's protection and ours, we want to make certain that \neveryone understands that there is no warranty for this free software. If \nthe software is modified by someone else and passed on, we want its \nrecipients to know that what they have is not the original, so that any \nproblems introduced by others will not reflect on the original authors' \nreputations. \n\nFinally, any free program is threatened constantly by software patents. We \nwish to avoid the danger that redistributors of a free program will \nindividually obtain patent licenses, in effect making the program \nproprietary. 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Many people have made generous contributions\n to the wide range of software distributed through that system in \n reliance on consistent application of that system; it is up to the \n author/donor to decide if he or she is willing to distribute software \n through any other system and a licensee cannot impose that choice. \n\n This section is intended to make thoroughly clear what is believed to be \n a consequence of the rest of this License. \n\n8. If the distribution and/or use of the Program is restricted in certain \n countries either by patents or by copyrighted interfaces, the original \n copyright holder who places the Program under this License may add an \n explicit geographical distribution limitation excluding those countries, \n so that distribution is permitted only in or among countries not thus \n excluded. In such case, this License incorporates the limitation as if \n written in the body of this License. \n\n9. The Free Software Foundation may publish revised and/or new versions of \n the General Public License from time to time. Such new versions will be \n similar in spirit to the present version, but may differ in detail to \n address new problems or concerns. \n\n Each version is given a distinguishing version number. If the Program \n specifies a version number of this License which applies to it and \"any \n later version\", you have the option of following the terms and \n conditions either of that version or of any later version published by \n the Free Software Foundation. If the Program does not specify a version \n number of this License, you may choose any version ever published by the \n Free Software Foundation. \n\n10. If you wish to incorporate parts of the Program into other free programs\n whose distribution conditions are different, write to the author to ask \n for permission. For software which is copyrighted by the Free Software \n Foundation, write to the Free Software Foundation; we sometimes make \n exceptions for this. Our decision will be guided by the two goals of \n preserving the free status of all derivatives of our free software and \n of promoting the sharing and reuse of software generally. \n\n NO WARRANTY\n\n11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY \n FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN \n OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES \n PROVIDE THE PROGRAM \"AS IS\" WITHOUT WARRANTY OF ANY KIND, EITHER \n EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED \n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE \n ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH \n YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL \n NECESSARY SERVICING, REPAIR OR CORRECTION. \n\n12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING \n WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR \n REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR \n DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL \n DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM \n (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED \n INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF \n THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR \n OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. \n\nEND OF TERMS AND CONDITIONS\n\nHow to Apply These Terms to Your New Programs\n\nIf you develop a new program, and you want it to be of the greatest \npossible use to the public, the best way to achieve this is to make it free \nsoftware which everyone can redistribute and change under these terms. \n\nTo do so, attach the following notices to the program. It is safest to \nattach them to the start of each source file to most effectively convey the\nexclusion of warranty; and each file should have at least the \"copyright\" \nline and a pointer to where the full notice is found. \n\none line to give the program's name and an idea of what it does.\nCopyright (C) yyyy name of author\n\nThis program is free software; you can redistribute it and/or modify it \nunder the terms of the GNU General Public License as published by the Free \nSoftware Foundation; either version 2 of the License, or (at your option) \nany later version.\n\nThis program is distributed in the hope that it will be useful, but WITHOUT \nANY WARRANTY; without even the implied warranty of MERCHANTABILITY or \nFITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for \nmore details.\n\nYou should have received a copy of the GNU General Public License along with\nthis program; if not, write to the Free Software Foundation, Inc., 59 \nTemple Place - Suite 330, Boston, MA 02111-1307, USA.\n\nAlso add information on how to contact you by electronic and paper mail. \n\nIf the program is interactive, make it output a short notice like this when \nit starts in an interactive mode: \n\nGnomovision version 69, Copyright (C) year name of author Gnomovision comes \nwith ABSOLUTELY NO WARRANTY; for details type 'show w'. This is free \nsoftware, and you are welcome to redistribute it under certain conditions; \ntype 'show c' for details.\n\nThe hypothetical commands 'show w' and 'show c' should show the appropriate \nparts of the General Public License. Of course, the commands you use may be \ncalled something other than 'show w' and 'show c'; they could even be \nmouse-clicks or menu items--whatever suits your program. \n\nYou should also get your employer (if you work as a programmer) or your \nschool, if any, to sign a \"copyright disclaimer\" for the program, if \nnecessary. Here is a sample; alter the names: \n\nYoyodyne, Inc., hereby disclaims all copyright interest in the program \n'Gnomovision' (which makes passes at compilers) written by James Hacker.\n\nsignature of Ty Coon, 1 April 1989\nTy Coon, President of Vice\n\nThis General Public License does not permit incorporating your program into \nproprietary programs. If your program is a subroutine library, you may \nconsider it more useful to permit linking proprietary applications with the \nlibrary. If this is what you want to do, use the GNU Library General Public \nLicense instead of this License.\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _IXGBE_H_\n#define _IXGBE_H_\n\n#ifndef IXGBE_NO_LRO\n#include \n#endif\n\n#include \n#include \n#ifdef HAVE_IRQ_AFFINITY_HINT\n#include \n#endif /* HAVE_IRQ_AFFINITY_HINT */\n#include \n\n#ifdef SIOCETHTOOL\n#include \n#endif\n#ifdef NETIF_F_HW_VLAN_TX\n#include \n#endif\n#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)\n#define IXGBE_DCA\n#include \n#endif\n#include \"ixgbe_dcb.h\"\n\n#include \"kcompat.h\"\n\n#ifdef HAVE_SCTP\n#include \n#endif\n\n#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)\n#define IXGBE_FCOE\n#include \"ixgbe_fcoe.h\"\n#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */\n\n#if defined(CONFIG_PTP_1588_CLOCK) || defined(CONFIG_PTP_1588_CLOCK_MODULE)\n#define HAVE_IXGBE_PTP\n#endif\n\n#include \"ixgbe_api.h\"\n\n#define PFX \"ixgbe: \"\n#define DPRINTK(nlevel, klevel, fmt, args...) \\\n\t((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \\\n\tprintk(KERN_##klevel PFX \"%s: %s: \" fmt, adapter->netdev->name, \\\n\t\t__func__ , ## args)))\n\n/* TX/RX descriptor defines */\n#define IXGBE_DEFAULT_TXD\t\t512\n#define IXGBE_DEFAULT_TX_WORK\t\t256\n#define IXGBE_MAX_TXD\t\t\t4096\n#define IXGBE_MIN_TXD\t\t\t64\n\n#define IXGBE_DEFAULT_RXD\t\t512\n#define IXGBE_DEFAULT_RX_WORK\t\t256\n#define IXGBE_MAX_RXD\t\t\t4096\n#define IXGBE_MIN_RXD\t\t\t64\n\n\n/* flow control */\n#define IXGBE_MIN_FCRTL\t\t\t0x40\n#define IXGBE_MAX_FCRTL\t\t\t0x7FF80\n#define IXGBE_MIN_FCRTH\t\t\t0x600\n#define IXGBE_MAX_FCRTH\t\t\t0x7FFF0\n#define IXGBE_DEFAULT_FCPAUSE\t\t0xFFFF\n#define IXGBE_MIN_FCPAUSE\t\t0\n#define IXGBE_MAX_FCPAUSE\t\t0xFFFF\n\n/* Supported Rx Buffer Sizes */\n#define IXGBE_RXBUFFER_512\t512 /* Used for packet split */\n#ifdef CONFIG_IXGBE_DISABLE_PACKET_SPLIT\n#define IXGBE_RXBUFFER_1536\t1536\n#define IXGBE_RXBUFFER_2K\t2048\n#define IXGBE_RXBUFFER_3K\t3072\n#define IXGBE_RXBUFFER_4K\t4096\n#define IXGBE_RXBUFFER_7K\t7168\n#define IXGBE_RXBUFFER_8K\t8192\n#define IXGBE_RXBUFFER_15K\t15360\n#endif /* CONFIG_IXGBE_DISABLE_PACKET_SPLIT */\n#define IXGBE_MAX_RXBUFFER\t16384 /* largest size for single descriptor */\n\n/*\n * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we\n * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,\n * this adds up to 512 bytes of extra data meaning the smallest allocation\n * we could have is 1K.\n * i.e. RXBUFFER_512 --> size-1024 slab\n */\n#define IXGBE_RX_HDR_SIZE\tIXGBE_RXBUFFER_512\n\n#define MAXIMUM_ETHERNET_VLAN_SIZE\t(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)\n\n/* How many Rx Buffers do we bundle into one write to the hardware ? */\n#define IXGBE_RX_BUFFER_WRITE\t16\t/* Must be power of 2 */\n\n#define IXGBE_TX_FLAGS_CSUM\t\t(u32)(1)\n#define IXGBE_TX_FLAGS_HW_VLAN\t\t(u32)(1 << 1)\n#define IXGBE_TX_FLAGS_SW_VLAN\t\t(u32)(1 << 2)\n#define IXGBE_TX_FLAGS_TSO\t\t(u32)(1 << 3)\n#define IXGBE_TX_FLAGS_IPV4\t\t(u32)(1 << 4)\n#define IXGBE_TX_FLAGS_FCOE\t\t(u32)(1 << 5)\n#define IXGBE_TX_FLAGS_FSO\t\t(u32)(1 << 6)\n#define IXGBE_TX_FLAGS_TXSW\t\t(u32)(1 << 7)\n#define IXGBE_TX_FLAGS_TSTAMP\t\t(u32)(1 << 8)\n#define IXGBE_TX_FLAGS_VLAN_MASK\t0xffff0000\n#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK\t0xe0000000\n#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT\t29\n#define IXGBE_TX_FLAGS_VLAN_SHIFT\t16\n\n#define IXGBE_MAX_RX_DESC_POLL\t\t10\n\n#define IXGBE_MAX_VF_MC_ENTRIES\t\t30\n#define IXGBE_MAX_VF_FUNCTIONS\t\t64\n#define IXGBE_MAX_VFTA_ENTRIES\t\t128\n#define MAX_EMULATION_MAC_ADDRS\t\t16\n#define IXGBE_MAX_PF_MACVLANS\t\t15\n#define IXGBE_82599_VF_DEVICE_ID\t0x10ED\n#define IXGBE_X540_VF_DEVICE_ID\t\t0x1515\n\n#ifdef CONFIG_PCI_IOV\n#define VMDQ_P(p)\t((p) + adapter->num_vfs)\n#else\n#define VMDQ_P(p)\t(p)\n#endif\n\n#define UPDATE_VF_COUNTER_32bit(reg, last_counter, counter)\t\\\n\t{\t\t\t\t\t\t\t\\\n\t\tu32 current_counter = IXGBE_READ_REG(hw, reg);\t\\\n\t\tif (current_counter < last_counter)\t\t\\\n\t\t\tcounter += 0x100000000LL;\t\t\\\n\t\tlast_counter = current_counter;\t\t\t\\\n\t\tcounter &= 0xFFFFFFFF00000000LL;\t\t\\\n\t\tcounter |= current_counter;\t\t\t\\\n\t}\n\n#define UPDATE_VF_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \\\n\t{\t\t\t\t\t\t\t\t \\\n\t\tu64 current_counter_lsb = IXGBE_READ_REG(hw, reg_lsb);\t \\\n\t\tu64 current_counter_msb = IXGBE_READ_REG(hw, reg_msb);\t \\\n\t\tu64 current_counter = (current_counter_msb << 32) |\t \\\n\t\t\tcurrent_counter_lsb;\t\t\t\t \\\n\t\tif (current_counter < last_counter)\t\t\t \\\n\t\t\tcounter += 0x1000000000LL;\t\t\t \\\n\t\tlast_counter = current_counter;\t\t\t\t \\\n\t\tcounter &= 0xFFFFFFF000000000LL;\t\t\t \\\n\t\tcounter |= current_counter;\t\t\t\t \\\n\t}\n\nstruct vf_stats {\n\tu64 gprc;\n\tu64 gorc;\n\tu64 gptc;\n\tu64 gotc;\n\tu64 mprc;\n};\n\nstruct vf_data_storage {\n\tunsigned char vf_mac_addresses[ETH_ALEN];\n\tu16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];\n\tu16 num_vf_mc_hashes;\n\tu16 default_vf_vlan_id;\n\tu16 vlans_enabled;\n\tbool clear_to_send;\n\tstruct vf_stats vfstats;\n\tstruct vf_stats last_vfstats;\n\tstruct vf_stats saved_rst_vfstats;\n\tbool pf_set_mac;\n\tu16 pf_vlan; /* When set, guest VLAN config not allowed. */\n\tu16 pf_qos;\n\tu16 tx_rate;\n\tu16 vlan_count;\n\tu8 spoofchk_enabled;\n\tstruct pci_dev *vfdev;\n};\n\nstruct vf_macvlans {\n\tstruct list_head l;\n\tint vf;\n\tbool free;\n\tbool is_macvlan;\n\tu8 vf_macvlan[ETH_ALEN];\n};\n\n#ifndef IXGBE_NO_LRO\n#define IXGBE_LRO_MAX\t\t32\t/*Maximum number of LRO descriptors*/\n#define IXGBE_LRO_GLOBAL\t10\n\nstruct ixgbe_lro_stats {\n\tu32 flushed;\n\tu32 coal;\n};\n\n/*\n * ixgbe_lro_header - header format to be aggregated by LRO\n * @iph: IP header without options\n * @tcp: TCP header\n * @ts: Optional TCP timestamp data in TCP options\n *\n * This structure relies on the check above that verifies that the header\n * is IPv4 and does not contain any options.\n */\nstruct ixgbe_lrohdr {\n\tstruct iphdr iph;\n\tstruct tcphdr th;\n\t__be32 ts[0];\n};\n\nstruct ixgbe_lro_list {\n\tstruct sk_buff_head active;\n\tstruct ixgbe_lro_stats stats;\n};\n\n#endif /* IXGBE_NO_LRO */\n#define IXGBE_MAX_TXD_PWR\t14\n#define IXGBE_MAX_DATA_PER_TXD\t(1 << IXGBE_MAX_TXD_PWR)\n\n/* Tx Descriptors needed, worst case */\n#define TXD_USE_COUNT(S)\tDIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)\n#ifdef MAX_SKB_FRAGS\n#define DESC_NEEDED\t((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)\n#else\n#define DESC_NEEDED\t4\n#endif\n\n/* wrapper around a pointer to a socket buffer,\n * so a DMA handle can be stored along with the buffer */\nstruct ixgbe_tx_buffer {\n\tunion ixgbe_adv_tx_desc *next_to_watch;\n\tunsigned long time_stamp;\n\tstruct sk_buff *skb;\n\tunsigned int bytecount;\n\tunsigned short gso_segs;\n\t__be16 protocol;\n\tDEFINE_DMA_UNMAP_ADDR(dma);\n\tDEFINE_DMA_UNMAP_LEN(len);\n\tu32 tx_flags;\n};\n\nstruct ixgbe_rx_buffer {\n\tstruct sk_buff *skb;\n\tdma_addr_t dma;\n#ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT\n\tstruct page *page;\n\tunsigned int page_offset;\n#endif\n};\n\nstruct ixgbe_queue_stats {\n\tu64 packets;\n\tu64 bytes;\n};\n\nstruct ixgbe_tx_queue_stats {\n\tu64 restart_queue;\n\tu64 tx_busy;\n\tu64 tx_done_old;\n};\n\nstruct ixgbe_rx_queue_stats {\n\tu64 rsc_count;\n\tu64 rsc_flush;\n\tu64 non_eop_descs;\n\tu64 alloc_rx_page_failed;\n\tu64 alloc_rx_buff_failed;\n\tu64 csum_err;\n};\n\nenum ixgbe_ring_state_t {\n\t__IXGBE_TX_FDIR_INIT_DONE,\n\t__IXGBE_TX_DETECT_HANG,\n\t__IXGBE_HANG_CHECK_ARMED,\n\t__IXGBE_RX_RSC_ENABLED,\n#ifndef HAVE_NDO_SET_FEATURES\n\t__IXGBE_RX_CSUM_ENABLED,\n#endif\n\t__IXGBE_RX_CSUM_UDP_ZERO_ERR,\n#ifdef IXGBE_FCOE\n\t__IXGBE_RX_FCOE_BUFSZ,\n#endif\n};\n\n#define check_for_tx_hang(ring) \\\n\ttest_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)\n#define set_check_for_tx_hang(ring) \\\n\tset_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)\n#define clear_check_for_tx_hang(ring) \\\n\tclear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)\n#ifndef IXGBE_NO_HW_RSC\n#define ring_is_rsc_enabled(ring) \\\n\ttest_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)\n#else\n#define ring_is_rsc_enabled(ring)\tfalse\n#endif\n#define set_ring_rsc_enabled(ring) \\\n\tset_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)\n#define clear_ring_rsc_enabled(ring) \\\n\tclear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)\n#define netdev_ring(ring) (ring->netdev)\n#define ring_queue_index(ring) (ring->queue_index)\n\n\nstruct ixgbe_ring {\n\tstruct ixgbe_ring *next;\t/* pointer to next ring in q_vector */\n\tstruct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */\n\tstruct net_device *netdev;\t/* netdev ring belongs to */\n\tstruct device *dev;\t\t/* device for DMA mapping */\n\tvoid *desc;\t\t\t/* descriptor ring memory */\n\tunion {\n\t\tstruct ixgbe_tx_buffer *tx_buffer_info;\n\t\tstruct ixgbe_rx_buffer *rx_buffer_info;\n\t};\n\tunsigned long state;\n\tu8 __iomem *tail;\n\tdma_addr_t dma;\t\t\t/* phys. address of descriptor ring */\n\tunsigned int size;\t\t/* length in bytes */\n\n\tu16 count;\t\t\t/* amount of descriptors */\n\n\tu8 queue_index; /* needed for multiqueue queue management */\n\tu8 reg_idx;\t\t\t/* holds the special value that gets\n\t\t\t\t\t * the hardware register offset\n\t\t\t\t\t * associated with this ring, which is\n\t\t\t\t\t * different for DCB and RSS modes\n\t\t\t\t\t */\n\tu16 next_to_use;\n\tu16 next_to_clean;\n\n\tunion {\n#ifdef CONFIG_IXGBE_DISABLE_PACKET_SPLIT\n\t\tu16 rx_buf_len;\n#else\n\t\tu16 next_to_alloc;\n#endif\n\t\tstruct {\n\t\t\tu8 atr_sample_rate;\n\t\t\tu8 atr_count;\n\t\t};\n\t};\n\n\tu8 dcb_tc;\n\tstruct ixgbe_queue_stats stats;\n\tunion {\n\t\tstruct ixgbe_tx_queue_stats tx_stats;\n\t\tstruct ixgbe_rx_queue_stats rx_stats;\n\t};\n} ____cacheline_internodealigned_in_smp;\n\nenum ixgbe_ring_f_enum {\n\tRING_F_NONE = 0,\n\tRING_F_VMDQ, /* SR-IOV uses the same ring feature */\n\tRING_F_RSS,\n\tRING_F_FDIR,\n#ifdef IXGBE_FCOE\n\tRING_F_FCOE,\n#endif /* IXGBE_FCOE */\n\tRING_F_ARRAY_SIZE /* must be last in enum set */\n};\n\n#define IXGBE_MAX_DCB_INDICES\t8\n#define IXGBE_MAX_RSS_INDICES\t16\n#define IXGBE_MAX_VMDQ_INDICES\t64\n#define IXGBE_MAX_FDIR_INDICES\t64\n#ifdef IXGBE_FCOE\n#define IXGBE_MAX_FCOE_INDICES\t8\n#define MAX_RX_QUEUES\t(IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)\n#define MAX_TX_QUEUES\t(IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)\n#else\n#define MAX_RX_QUEUES\tIXGBE_MAX_FDIR_INDICES\n#define MAX_TX_QUEUES\tIXGBE_MAX_FDIR_INDICES\n#endif /* IXGBE_FCOE */\nstruct ixgbe_ring_feature {\n\tint indices;\n\tint mask;\n};\n\n#ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT\n/*\n * FCoE requires that all Rx buffers be over 2200 bytes in length. Since\n * this is twice the size of a half page we need to double the page order\n * for FCoE enabled Rx queues.\n */\n#if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)\nstatic inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)\n{\n\treturn test_bit(__IXGBE_RX_FCOE_BUFSZ, &ring->state) ? 1 : 0;\n}\n#else\n#define ixgbe_rx_pg_order(_ring) 0\n#endif\n#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))\n#define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring))\n\n#endif\nstruct ixgbe_ring_container {\n\tstruct ixgbe_ring *ring;\t/* pointer to linked list of rings */\n\tunsigned int total_bytes;\t/* total bytes processed this int */\n\tunsigned int total_packets;\t/* total packets processed this int */\n\tu16 work_limit;\t\t\t/* total work allowed per interrupt */\n\tu8 count;\t\t\t/* total number of rings in vector */\n\tu8 itr;\t\t\t\t/* current ITR setting for ring */\n};\n\n/* iterator for handling rings in ring container */\n#define ixgbe_for_each_ring(pos, head) \\\n\tfor (pos = (head).ring; pos != NULL; pos = pos->next)\n\n#define MAX_RX_PACKET_BUFFERS\t((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \\\n\t\t\t\t ? 8 : 1)\n#define MAX_TX_PACKET_BUFFERS\tMAX_RX_PACKET_BUFFERS\n\n/* MAX_MSIX_Q_VECTORS of these are allocated,\n * but we only use one per queue-specific vector.\n */\nstruct ixgbe_q_vector {\n\tstruct ixgbe_adapter *adapter;\n\tint cpu;\t/* CPU for DCA */\n\tu16 v_idx;\t/* index of q_vector within array, also used for\n\t\t\t * finding the bit in EICR and friends that\n\t\t\t * represents the vector for this ring */\n\tu16 itr;\t/* Interrupt throttle rate written to EITR */\n\tstruct ixgbe_ring_container rx, tx;\n\n#ifdef CONFIG_IXGBE_NAPI\n\tstruct napi_struct napi;\n#endif\n#ifndef HAVE_NETDEV_NAPI_LIST\n\tstruct net_device poll_dev;\n#endif\n#ifdef HAVE_IRQ_AFFINITY_HINT\n\tcpumask_t affinity_mask;\n#endif\n#ifndef IXGBE_NO_LRO\n\tstruct ixgbe_lro_list lrolist; /* LRO list for queue vector*/\n#endif\n\tint numa_node;\n\tchar name[IFNAMSIZ + 9];\n\n\t/* for dynamic allocation of rings associated with this q_vector */\n\tstruct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;\n};\n\n/*\n * microsecond values for various ITR rates shifted by 2 to fit itr register\n * with the first 3 bits reserved 0\n */\n#define IXGBE_MIN_RSC_ITR\t24\n#define IXGBE_100K_ITR\t\t40\n#define IXGBE_20K_ITR\t\t200\n#define IXGBE_16K_ITR\t\t248\n#define IXGBE_10K_ITR\t\t400\n#define IXGBE_8K_ITR\t\t500\n\n/* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */\nstatic inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,\n\t\t\t\t\tconst u32 stat_err_bits)\n{\n\treturn rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);\n}\n\n/* ixgbe_desc_unused - calculate if we have unused descriptors */\nstatic inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)\n{\n\tu16 ntc = ring->next_to_clean;\n\tu16 ntu = ring->next_to_use;\n\n\treturn ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;\n}\n\n#define IXGBE_RX_DESC(R, i)\t\\\n\t(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))\n#define IXGBE_TX_DESC(R, i)\t\\\n\t(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))\n#define IXGBE_TX_CTXTDESC(R, i)\t\\\n\t(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))\n\n#define IXGBE_MAX_JUMBO_FRAME_SIZE\t16128\n#ifdef IXGBE_FCOE\n/* use 3K as the baby jumbo frame size for FCoE */\n#define IXGBE_FCOE_JUMBO_FRAME_SIZE\t3072\n#endif /* IXGBE_FCOE */\n\n#define TCP_TIMER_VECTOR\t0\n#define OTHER_VECTOR\t1\n#define NON_Q_VECTORS\t(OTHER_VECTOR + TCP_TIMER_VECTOR)\n\n#define IXGBE_MAX_MSIX_Q_VECTORS_82599\t64\n#define IXGBE_MAX_MSIX_Q_VECTORS_82598\t16\n\nstruct ixgbe_mac_addr {\n\tu8 addr[ETH_ALEN];\n\tu16 queue;\n\tu16 state; /* bitmask */\n};\n#define IXGBE_MAC_STATE_DEFAULT\t\t0x1\n#define IXGBE_MAC_STATE_MODIFIED\t0x2\n#define IXGBE_MAC_STATE_IN_USE\t\t0x4\n\n#ifdef IXGBE_PROCFS\nstruct ixgbe_therm_proc_data {\n\tstruct ixgbe_hw *hw;\n\tstruct ixgbe_thermal_diode_data *sensor_data;\n};\n\n#endif /* IXGBE_PROCFS */\n\n/*\n * Only for array allocations in our adapter struct. On 82598, there will be\n * unused entries in the array, but that's not a big deal. Also, in 82599,\n * we can actually assign 64 queue vectors based on our extended-extended\n * interrupt registers. This is different than 82598, which is limited to 16.\n */\n#define MAX_MSIX_Q_VECTORS\tIXGBE_MAX_MSIX_Q_VECTORS_82599\n#define MAX_MSIX_COUNT\t\tIXGBE_MAX_MSIX_VECTORS_82599\n\n#define MIN_MSIX_Q_VECTORS\t1\n#define MIN_MSIX_COUNT\t\t(MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)\n\n/* default to trying for four seconds */\n#define IXGBE_TRY_LINK_TIMEOUT\t(4 * HZ)\n\n/* board specific private data structure */\nstruct ixgbe_adapter {\n#ifdef NETIF_F_HW_VLAN_TX\n#ifdef HAVE_VLAN_RX_REGISTER\n\tstruct vlan_group *vlgrp; /* must be first, see ixgbe_receive_skb */\n#else\n\tunsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];\n#endif\n#endif /* NETIF_F_HW_VLAN_TX */\n\t/* OS defined structs */\n\tstruct net_device *netdev;\n\tstruct pci_dev *pdev;\n\n\tunsigned long state;\n\n\t/* Some features need tri-state capability,\n\t * thus the additional *_CAPABLE flags.\n\t */\n\tu32 flags;\n#define IXGBE_FLAG_MSI_CAPABLE\t\t\t(u32)(1 << 0)\n#define IXGBE_FLAG_MSI_ENABLED\t\t\t(u32)(1 << 1)\n#define IXGBE_FLAG_MSIX_CAPABLE\t\t\t(u32)(1 << 2)\n#define IXGBE_FLAG_MSIX_ENABLED\t\t\t(u32)(1 << 3)\n#ifndef IXGBE_NO_LLI\n#define IXGBE_FLAG_LLI_PUSH\t\t\t(u32)(1 << 4)\n#endif\n#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 8)\n#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)\n#define IXGBE_FLAG_DCA_ENABLED\t\t\t(u32)(1 << 9)\n#define IXGBE_FLAG_DCA_CAPABLE\t\t\t(u32)(1 << 10)\n#define IXGBE_FLAG_DCA_ENABLED_DATA\t\t(u32)(1 << 11)\n#else\n#define IXGBE_FLAG_DCA_ENABLED\t\t\t(u32)0\n#define IXGBE_FLAG_DCA_CAPABLE\t\t\t(u32)0\n#define IXGBE_FLAG_DCA_ENABLED_DATA (u32)0\n#endif\n#define IXGBE_FLAG_MQ_CAPABLE\t\t\t(u32)(1 << 12)\n#define IXGBE_FLAG_DCB_ENABLED\t\t\t(u32)(1 << 13)\n#define IXGBE_FLAG_DCB_CAPABLE\t\t\t(u32)(1 << 14)\n#define IXGBE_FLAG_RSS_ENABLED\t\t\t(u32)(1 << 15)\n#define IXGBE_FLAG_RSS_CAPABLE\t\t\t(u32)(1 << 16)\n#define IXGBE_FLAG_VMDQ_ENABLED\t\t\t(u32)(1 << 18)\n#define IXGBE_FLAG_FAN_FAIL_CAPABLE\t\t(u32)(1 << 19)\n#define IXGBE_FLAG_NEED_LINK_UPDATE\t\t(u32)(1 << 20)\n#define IXGBE_FLAG_NEED_LINK_CONFIG\t\t(u32)(1 << 21)\n#define IXGBE_FLAG_FDIR_HASH_CAPABLE\t\t(u32)(1 << 22)\n#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE\t\t(u32)(1 << 23)\n#ifdef IXGBE_FCOE\n#define IXGBE_FLAG_FCOE_CAPABLE\t\t\t(u32)(1 << 24)\n#define IXGBE_FLAG_FCOE_ENABLED\t\t\t(u32)(1 << 25)\n#endif /* IXGBE_FCOE */\n#define IXGBE_FLAG_SRIOV_CAPABLE\t\t(u32)(1 << 26)\n#define IXGBE_FLAG_SRIOV_ENABLED\t\t(u32)(1 << 27)\n#define IXGBE_FLAG_SRIOV_REPLICATION_ENABLE\t(u32)(1 << 28)\n#define IXGBE_FLAG_SRIOV_L2SWITCH_ENABLE\t(u32)(1 << 29)\n#define IXGBE_FLAG_SRIOV_L2LOOPBACK_ENABLE\t(u32)(1 << 30)\n#define IXGBE_FLAG_RX_BB_CAPABLE\t\t(u32)(1 << 31)\n\n\tu32 flags2;\n#ifndef IXGBE_NO_HW_RSC\n#define IXGBE_FLAG2_RSC_CAPABLE\t\t\t(u32)(1)\n#define IXGBE_FLAG2_RSC_ENABLED\t\t\t(u32)(1 << 1)\n#else\n#define IXGBE_FLAG2_RSC_CAPABLE\t\t\t0\n#define IXGBE_FLAG2_RSC_ENABLED\t\t\t0\n#endif\n#define IXGBE_FLAG2_VMDQ_DEFAULT_OVERRIDE\t(u32)(1 << 2)\n#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE\t\t(u32)(1 << 4)\n#define IXGBE_FLAG2_TEMP_SENSOR_EVENT\t\t(u32)(1 << 5)\n#define IXGBE_FLAG2_SEARCH_FOR_SFP\t\t(u32)(1 << 6)\n#define IXGBE_FLAG2_SFP_NEEDS_RESET\t\t(u32)(1 << 7)\n#define IXGBE_FLAG2_RESET_REQUESTED\t\t(u32)(1 << 8)\n#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT\t(u32)(1 << 9)\n#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP\t\t(u32)(1 << 10)\n#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP\t\t(u32)(1 << 11)\n#define IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED (u32)(1 << 12)\n\n\t/* Tx fast path data */\n\tint num_tx_queues;\n\tu16 tx_itr_setting;\n\tu16 tx_work_limit;\n\n\t/* Rx fast path data */\n\tint num_rx_queues;\n\tu16 rx_itr_setting;\n\tu16 rx_work_limit;\n\n\t/* TX */\n\tstruct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;\n\n\tu64 restart_queue;\n\tu64 lsc_int;\n\tu32 tx_timeout_count;\n\n\t/* RX */\n\tstruct ixgbe_ring *rx_ring[MAX_RX_QUEUES];\n\tint num_rx_pools;\t\t/* == num_rx_queues in 82598 */\n\tint num_rx_queues_per_pool;\t/* 1 if 82598, can be many if 82599 */\n\tu64 hw_csum_rx_error;\n\tu64 hw_rx_no_dma_resources;\n\tu64 rsc_total_count;\n\tu64 rsc_total_flush;\n\tu64 non_eop_descs;\n#ifndef CONFIG_IXGBE_NAPI\n\tu64 rx_dropped_backlog;\t\t/* count drops from rx intr handler */\n#endif\n\tu32 alloc_rx_page_failed;\n\tu32 alloc_rx_buff_failed;\n\n\tstruct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];\n\n#ifdef HAVE_DCBNL_IEEE\n\tstruct ieee_pfc *ixgbe_ieee_pfc;\n\tstruct ieee_ets *ixgbe_ieee_ets;\n#endif\n\tstruct ixgbe_dcb_config dcb_cfg;\n\tstruct ixgbe_dcb_config temp_dcb_cfg;\n\tu8 dcb_set_bitmap;\n\tu8 dcbx_cap;\n#ifndef HAVE_MQPRIO\n\tu8 tc;\n#endif\n\tenum ixgbe_fc_mode last_lfc_mode;\n\n\tint num_msix_vectors;\n\tint max_msix_q_vectors; /* true count of q_vectors for device */\n\tstruct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];\n\tstruct msix_entry *msix_entries;\n\n#ifndef HAVE_NETDEV_STATS_IN_NETDEV\n\tstruct net_device_stats net_stats;\n#endif\n#ifndef IXGBE_NO_LRO\n\tstruct ixgbe_lro_stats lro_stats;\n#endif\n\n#ifdef ETHTOOL_TEST\n\tu32 test_icr;\n\tstruct ixgbe_ring test_tx_ring;\n\tstruct ixgbe_ring test_rx_ring;\n#endif\n\n\t/* structs defined in ixgbe_hw.h */\n\tstruct ixgbe_hw hw;\n\tu16 msg_enable;\n\tstruct ixgbe_hw_stats stats;\n#ifndef IXGBE_NO_LLI\n\tu32 lli_port;\n\tu32 lli_size;\n\tu32 lli_etype;\n\tu32 lli_vlan_pri;\n#endif /* IXGBE_NO_LLI */\n\n\tu32 *config_space;\n\tu64 tx_busy;\n\tunsigned int tx_ring_count;\n\tunsigned int rx_ring_count;\n\n\tu32 link_speed;\n\tbool link_up;\n\tunsigned long link_check_timeout;\n\n\tstruct timer_list service_timer;\n\tstruct work_struct service_task;\n\n\tstruct hlist_head fdir_filter_list;\n\tunsigned long fdir_overflow; /* number of times ATR was backed off */\n\tunion ixgbe_atr_input fdir_mask;\n\tint fdir_filter_count;\n\tu32 fdir_pballoc;\n\tu32 atr_sample_rate;\n\tspinlock_t fdir_perfect_lock;\n\n#ifdef IXGBE_FCOE\n\tstruct ixgbe_fcoe fcoe;\n#endif /* IXGBE_FCOE */\n\tu32 wol;\n\n\tu16 bd_number;\n\n\tchar eeprom_id[32];\n\tu16 eeprom_cap;\n\tbool netdev_registered;\n\tu32 interrupt_event;\n#ifdef HAVE_ETHTOOL_SET_PHYS_ID\n\tu32 led_reg;\n#endif\n\n\tDECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);\n\tunsigned int num_vfs;\n\tstruct vf_data_storage *vfinfo;\n\tint vf_rate_link_speed;\n\tstruct vf_macvlans vf_mvs;\n\tstruct vf_macvlans *mv_list;\n#ifdef CONFIG_PCI_IOV\n\tu32 timer_event_accumulator;\n\tu32 vferr_refcount;\n#endif\n\tstruct ixgbe_mac_addr *mac_table;\n#ifdef IXGBE_SYSFS\n\tstruct kobject *info_kobj;\n\tstruct kobject *therm_kobj[IXGBE_MAX_SENSORS];\n#else /* IXGBE_SYSFS */\n#ifdef IXGBE_PROCFS\n\tstruct proc_dir_entry *eth_dir;\n\tstruct proc_dir_entry *info_dir;\n\tstruct proc_dir_entry *therm_dir[IXGBE_MAX_SENSORS];\n\tstruct ixgbe_therm_proc_data therm_data[IXGBE_MAX_SENSORS];\n#endif /* IXGBE_PROCFS */\n#endif /* IXGBE_SYSFS */\n};\n\nstruct ixgbe_fdir_filter {\n\tstruct hlist_node fdir_node;\n\tunion ixgbe_atr_input filter;\n\tu16 sw_idx;\n\tu16 action;\n};\n\nenum ixgbe_state_t {\n\t__IXGBE_TESTING,\n\t__IXGBE_RESETTING,\n\t__IXGBE_DOWN,\n\t__IXGBE_SERVICE_SCHED,\n\t__IXGBE_IN_SFP_INIT,\n};\n\nstruct ixgbe_cb {\n#ifdef CONFIG_IXGBE_DISABLE_PACKET_SPLIT\n\tunion {\t\t\t\t/* Union defining head/tail partner */\n\t\tstruct sk_buff *head;\n\t\tstruct sk_buff *tail;\n\t};\n#endif\n\tdma_addr_t dma;\n#ifndef IXGBE_NO_LRO\n\t__be32\ttsecr;\t\t\t/* timestamp echo response */\n\tu32\ttsval;\t\t\t/* timestamp value in host order */\n\tu32\tnext_seq;\t\t/* next expected sequence number */\n\tu16\tfree;\t\t\t/* 65521 minus total size */\n\tu16\tmss;\t\t\t/* size of data portion of packet */\n#endif /* IXGBE_NO_LRO */\n#ifdef HAVE_VLAN_RX_REGISTER\n\tu16\tvid;\t\t\t/* VLAN tag */\n#endif\n\tu16\tappend_cnt;\t\t/* number of skb's appended */\n#ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT\n\tbool\tpage_released;\n#endif\n};\n#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)\n\n#ifdef IXGBE_SYSFS\nvoid ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);\nint ixgbe_sysfs_init(struct ixgbe_adapter *adapter);\n#endif /* IXGBE_SYSFS */\n#ifdef IXGBE_PROCFS\nvoid ixgbe_procfs_exit(struct ixgbe_adapter *adapter);\nint ixgbe_procfs_init(struct ixgbe_adapter *adapter);\nint ixgbe_procfs_topdir_init(void);\nvoid ixgbe_procfs_topdir_exit(void);\n#endif /* IXGBE_PROCFS */\n\nextern struct dcbnl_rtnl_ops dcbnl_ops;\nextern int ixgbe_copy_dcb_cfg(struct ixgbe_adapter *adapter, int tc_max);\n\nextern u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 index);\n\n/* needed by ixgbe_main.c */\nextern int ixgbe_validate_mac_addr(u8 *mc_addr);\nextern void ixgbe_check_options(struct ixgbe_adapter *adapter);\nextern void ixgbe_assign_netdev_ops(struct net_device *netdev);\n\n/* needed by ixgbe_ethtool.c */\nextern char ixgbe_driver_name[];\nextern const char ixgbe_driver_version[];\n\nextern void ixgbe_up(struct ixgbe_adapter *adapter);\nextern void ixgbe_down(struct ixgbe_adapter *adapter);\nextern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);\nextern void ixgbe_reset(struct ixgbe_adapter *adapter);\nextern void ixgbe_set_ethtool_ops(struct net_device *netdev);\nextern int ixgbe_setup_rx_resources(struct ixgbe_ring *);\nextern int ixgbe_setup_tx_resources(struct ixgbe_ring *);\nextern void ixgbe_free_rx_resources(struct ixgbe_ring *);\nextern void ixgbe_free_tx_resources(struct ixgbe_ring *);\nextern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,\n\t\t\t\t struct ixgbe_ring *);\nextern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,\n\t\t\t\t struct ixgbe_ring *);\nextern void ixgbe_update_stats(struct ixgbe_adapter *adapter);\nextern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);\nextern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);\nextern bool ixgbe_is_ixgbe(struct pci_dev *pcidev);\nextern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,\n\t\t\t\t\t struct ixgbe_adapter *,\n\t\t\t\t\t struct ixgbe_ring *);\nextern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,\n\t\t\t\t\t struct ixgbe_tx_buffer *);\nextern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);\nextern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,\n\t\t\t\t struct ixgbe_ring *);\nextern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,\n\t\t\t struct ixgbe_ring *);\nextern void ixgbe_set_rx_mode(struct net_device *netdev);\nextern int ixgbe_write_mc_addr_list(struct net_device *netdev);\nextern int ixgbe_setup_tc(struct net_device *dev, u8 tc);\n#ifdef IXGBE_FCOE\nextern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);\n#endif /* IXGBE_FCOE */\nextern void ixgbe_do_reset(struct net_device *netdev);\nextern void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector);\nextern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,\n\t\t\t\t struct ixgbe_ring *);\nextern void ixgbe_vlan_stripping_enable(struct ixgbe_adapter *adapter);\nextern void ixgbe_vlan_stripping_disable(struct ixgbe_adapter *adapter);\n#ifdef ETHTOOL_OPS_COMPAT\nextern int ethtool_ioctl(struct ifreq *ifr);\n#endif\n\n#ifdef IXGBE_FCOE\nextern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);\nextern int ixgbe_fso(struct ixgbe_ring *tx_ring,\n\t\t struct ixgbe_tx_buffer *first,\n\t\t u8 *hdr_len);\nextern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);\nextern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,\n\t\t\t union ixgbe_adv_rx_desc *rx_desc,\n\t\t\t struct sk_buff *skb);\nextern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,\n\t\t\t struct scatterlist *sgl, unsigned int sgc);\n#ifdef HAVE_NETDEV_OPS_FCOE_DDP_TARGET\nextern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,\n\t\t\t\t struct scatterlist *sgl, unsigned int sgc);\n#endif /* HAVE_NETDEV_OPS_FCOE_DDP_TARGET */\nextern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);\n#ifdef HAVE_NETDEV_OPS_FCOE_ENABLE\nextern int ixgbe_fcoe_enable(struct net_device *netdev);\nextern int ixgbe_fcoe_disable(struct net_device *netdev);\n#endif /* HAVE_NETDEV_OPS_FCOE_ENABLE */\n#ifdef CONFIG_DCB\n#ifdef HAVE_DCBNL_OPS_GETAPP\nextern u8 ixgbe_fcoe_getapp(struct net_device *netdev);\n#endif /* HAVE_DCBNL_OPS_GETAPP */\nextern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);\n#endif /* CONFIG_DCB */\n#ifdef HAVE_NETDEV_OPS_FCOE_GETWWN\nextern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);\n#endif\n#endif /* IXGBE_FCOE */\n\n#ifdef CONFIG_DCB\n#ifdef HAVE_DCBNL_IEEE\ns32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max_frame);\n#endif /* HAVE_DCBNL_IEEE */\n#endif /* CONFIG_DCB */\n\nextern void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring);\nextern int ixgbe_get_settings(struct net_device *netdev,\n\t\t\t struct ethtool_cmd *ecmd);\nextern int ixgbe_write_uc_addr_list(struct ixgbe_adapter *adapter,\n\t\t\t struct net_device *netdev, unsigned int vfn);\nextern void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter);\nextern int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,\n\t\t\t\tu8 *addr, u16 queue);\nextern int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,\n\t\t\t\tu8 *addr, u16 queue);\nextern int ixgbe_available_rars(struct ixgbe_adapter *adapter);\n#ifndef HAVE_VLAN_RX_REGISTER\nextern void ixgbe_vlan_mode(struct net_device *, u32);\n#endif\n#ifndef ixgbe_get_netdev_tc_txq\n#define ixgbe_get_netdev_tc_txq(dev, tc) (&dev->tc_to_txq[tc])\n#endif\nextern void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);\n#endif /* _IXGBE_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_82598.c", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"ixgbe_type.h\"\n#include \"ixgbe_82598.h\"\n#include \"ixgbe_api.h\"\n#include \"ixgbe_common.h\"\n#include \"ixgbe_phy.h\"\n\nstatic s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t\t bool *autoneg);\nstatic enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);\nstatic s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t bool autoneg_wait_to_complete);\nstatic s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed, bool *link_up,\n\t\t\t\t bool link_up_wait_to_complete);\nstatic s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg,\n\t\t\t\t bool autoneg_wait_to_complete);\nstatic s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t\t bool autoneg,\n\t\t\t\t\t bool autoneg_wait_to_complete);\nstatic s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);\nstatic s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);\nstatic s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);\nstatic void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,\n\t\t\t\t u32 headroom, int strategy);\n\n/**\n * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout\n * @hw: pointer to the HW structure\n *\n * The defaults for 82598 should be in the range of 50us to 50ms,\n * however the hardware default for these parts is 500us to 1ms which is less\n * than the 10ms recommended by the pci-e spec. To address this we need to\n * increase the value to either 10ms to 250ms for capability version 1 config,\n * or 16ms to 55ms for version 2.\n **/\nvoid ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)\n{\n\tu32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);\n\tu16 pcie_devctl2;\n\n\t/* only take action if timeout value is defaulted to 0 */\n\tif (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)\n\t\tgoto out;\n\n\t/*\n\t * if capababilities version is type 1 we can write the\n\t * timeout of 10ms to 250ms through the GCR register\n\t */\n\tif (!(gcr & IXGBE_GCR_CAP_VER2)) {\n\t\tgcr |= IXGBE_GCR_CMPL_TMOUT_10ms;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * for version 2 capabilities we need to write the config space\n\t * directly in order to set the completion timeout value for\n\t * 16ms to 55ms\n\t */\n\tpcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);\n\tpcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;\n\tIXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);\nout:\n\t/* disable completion timeout resend */\n\tgcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;\n\tIXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);\n}\n\n/**\n * ixgbe_init_ops_82598 - Inits func ptrs and MAC type\n * @hw: pointer to hardware structure\n *\n * Initialize the function pointers and assign the MAC type for 82598.\n * Does not touch the hardware.\n **/\ns32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\ts32 ret_val;\n\n\tret_val = ixgbe_init_phy_ops_generic(hw);\n\tret_val = ixgbe_init_ops_generic(hw);\n\n\t/* PHY */\n\tphy->ops.init = &ixgbe_init_phy_ops_82598;\n\n\t/* MAC */\n\tmac->ops.start_hw = &ixgbe_start_hw_82598;\n\tmac->ops.reset_hw = &ixgbe_reset_hw_82598;\n\tmac->ops.get_media_type = &ixgbe_get_media_type_82598;\n\tmac->ops.get_supported_physical_layer =\n\t\t\t\t&ixgbe_get_supported_physical_layer_82598;\n\tmac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;\n\tmac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;\n\tmac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;\n\n\t/* RAR, Multicast, VLAN */\n\tmac->ops.set_vmdq = &ixgbe_set_vmdq_82598;\n\tmac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;\n\tmac->ops.set_vfta = &ixgbe_set_vfta_82598;\n\tmac->ops.set_vlvf = NULL;\n\tmac->ops.clear_vfta = &ixgbe_clear_vfta_82598;\n\n\t/* Flow Control */\n\tmac->ops.fc_enable = &ixgbe_fc_enable_82598;\n\n\tmac->mcft_size\t\t= 128;\n\tmac->vft_size\t\t= 128;\n\tmac->num_rar_entries\t= 16;\n\tmac->rx_pb_size\t\t= 512;\n\tmac->max_tx_queues\t= 32;\n\tmac->max_rx_queues\t= 64;\n\tmac->max_msix_vectors\t= ixgbe_get_pcie_msix_count_generic(hw);\n\n\t/* SFP+ Module */\n\tphy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;\n\n\t/* Link */\n\tmac->ops.check_link = &ixgbe_check_mac_link_82598;\n\tmac->ops.setup_link = &ixgbe_setup_mac_link_82598;\n\tmac->ops.flap_tx_laser = NULL;\n\tmac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;\n\tmac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;\n\n\t/* Manageability interface */\n\tmac->ops.set_fw_drv_ver = NULL;\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_init_phy_ops_82598 - PHY/SFP specific init\n * @hw: pointer to hardware structure\n *\n * Initialize any function pointers that were not able to be\n * set during init_shared_code because the PHY/SFP type was\n * not known. Perform the SFP init if necessary.\n *\n **/\ns32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\ts32 ret_val = 0;\n\tu16 list_offset, data_offset;\n\n\t/* Identify the PHY */\n\tphy->ops.identify(hw);\n\n\t/* Overwrite the link function pointers if copper PHY */\n\tif (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {\n\t\tmac->ops.setup_link = &ixgbe_setup_copper_link_82598;\n\t\tmac->ops.get_link_capabilities =\n\t\t\t\t&ixgbe_get_copper_link_capabilities_generic;\n\t}\n\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_tn:\n\t\tphy->ops.setup_link = &ixgbe_setup_phy_link_tnx;\n\t\tphy->ops.check_link = &ixgbe_check_phy_link_tnx;\n\t\tphy->ops.get_firmware_version =\n\t\t\t\t\t&ixgbe_get_phy_firmware_version_tnx;\n\t\tbreak;\n\tcase ixgbe_phy_nl:\n\t\tphy->ops.reset = &ixgbe_reset_phy_nl;\n\n\t\t/* Call SFP+ identify routine to get the SFP+ module type */\n\t\tret_val = phy->ops.identify_sfp(hw);\n\t\tif (ret_val != 0)\n\t\t\tgoto out;\n\t\telse if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {\n\t\t\tret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/* Check to see if SFP+ module is supported */\n\t\tret_val = ixgbe_get_sfp_init_sequence_offsets(hw,\n\t\t\t\t\t\t\t &list_offset,\n\t\t\t\t\t\t\t &data_offset);\n\t\tif (ret_val != 0) {\n\t\t\tret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\t\tgoto out;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx\n * @hw: pointer to hardware structure\n *\n * Starts the hardware using the generic start_hw function.\n * Disables relaxed ordering Then set pcie completion timeout\n *\n **/\ns32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)\n{\n\tu32 regval;\n\tu32 i;\n\ts32 ret_val = 0;\n\n\tret_val = ixgbe_start_hw_generic(hw);\n\n\t/* Disable relaxed ordering */\n\tfor (i = 0; ((i < hw->mac.max_tx_queues) &&\n\t (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {\n\t\tregval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));\n\t\tregval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);\n\t}\n\n\tfor (i = 0; ((i < hw->mac.max_rx_queues) &&\n\t (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {\n\t\tregval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));\n\t\tregval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |\n\t\t\t IXGBE_DCA_RXCTRL_HEAD_WRO_EN);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);\n\t}\n\n\t/* set the completion timeout for interface */\n\tif (ret_val == 0)\n\t\tixgbe_set_pcie_completion_timeout(hw);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_get_link_capabilities_82598 - Determines link capabilities\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @autoneg: boolean auto-negotiation value\n *\n * Determines the link capabilities by reading the AUTOC register.\n **/\nstatic s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t\t bool *autoneg)\n{\n\ts32 status = 0;\n\tu32 autoc = 0;\n\n\t/*\n\t * Determine link capabilities based on the stored value of AUTOC,\n\t * which represents EEPROM defaults. If AUTOC value has not been\n\t * stored, use the current register value.\n\t */\n\tif (hw->mac.orig_link_settings_stored)\n\t\tautoc = hw->mac.orig_autoc;\n\telse\n\t\tautoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\n\tswitch (autoc & IXGBE_AUTOC_LMS_MASK) {\n\tcase IXGBE_AUTOC_LMS_1G_LINK_NO_AN:\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*autoneg = false;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_10G_LINK_NO_AN:\n\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\t\t*autoneg = false;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_1G_AN:\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*autoneg = true;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_KX4_AN:\n\tcase IXGBE_AUTOC_LMS_KX4_AN_1G_AN:\n\t\t*speed = IXGBE_LINK_SPEED_UNKNOWN;\n\t\tif (autoc & IXGBE_AUTOC_KX4_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (autoc & IXGBE_AUTOC_KX_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*autoneg = true;\n\t\tbreak;\n\n\tdefault:\n\t\tstatus = IXGBE_ERR_LINK_SETUP;\n\t\tbreak;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_media_type_82598 - Determines media type\n * @hw: pointer to hardware structure\n *\n * Returns the media type (fiber, copper, backplane)\n **/\nstatic enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)\n{\n\tenum ixgbe_media_type media_type;\n\n\t/* Detect if there is a copper PHY attached. */\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_cu_unknown:\n\tcase ixgbe_phy_tn:\n\t\tmedia_type = ixgbe_media_type_copper;\n\t\tgoto out;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Media type for I82598 is based on device ID */\n\tswitch (hw->device_id) {\n\tcase IXGBE_DEV_ID_82598:\n\tcase IXGBE_DEV_ID_82598_BX:\n\t\t/* Default device ID is mezzanine card KX/KX4 */\n\t\tmedia_type = ixgbe_media_type_backplane;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82598AF_DUAL_PORT:\n\tcase IXGBE_DEV_ID_82598AF_SINGLE_PORT:\n\tcase IXGBE_DEV_ID_82598_DA_DUAL_PORT:\n\tcase IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:\n\tcase IXGBE_DEV_ID_82598EB_XF_LR:\n\tcase IXGBE_DEV_ID_82598EB_SFP_LOM:\n\t\tmedia_type = ixgbe_media_type_fiber;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82598EB_CX4:\n\tcase IXGBE_DEV_ID_82598_CX4_DUAL_PORT:\n\t\tmedia_type = ixgbe_media_type_cx4;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82598AT:\n\tcase IXGBE_DEV_ID_82598AT2:\n\t\tmedia_type = ixgbe_media_type_copper;\n\t\tbreak;\n\tdefault:\n\t\tmedia_type = ixgbe_media_type_unknown;\n\t\tbreak;\n\t}\nout:\n\treturn media_type;\n}\n\n/**\n * ixgbe_fc_enable_82598 - Enable flow control\n * @hw: pointer to hardware structure\n *\n * Enable flow control according to the current settings.\n **/\ns32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = 0;\n\tu32 fctrl_reg;\n\tu32 rmcs_reg;\n\tu32 reg;\n\tu32 fcrtl, fcrth;\n\tu32 link_speed = 0;\n\tint i;\n\tbool link_up;\n\n\t/* Validate the water mark configuration */\n\tif (!hw->fc.pause_time) {\n\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\tgoto out;\n\t}\n\n\t/* Low water mark of zero causes XOFF floods */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tif ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&\n\t\t hw->fc.high_water[i]) {\n\t\t\tif (!hw->fc.low_water[i] ||\n\t\t\t hw->fc.low_water[i] >= hw->fc.high_water[i]) {\n\t\t\t\thw_dbg(hw, \"Invalid water mark configuration\\n\");\n\t\t\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\t}\n\n\t/*\n\t * On 82598 having Rx FC on causes resets while doing 1G\n\t * so if it's on turn it off once we know link_speed. For\n\t * more details see 82598 Specification update.\n\t */\n\thw->mac.ops.check_link(hw, &link_speed, &link_up, false);\n\tif (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {\n\t\tswitch (hw->fc.requested_mode) {\n\t\tcase ixgbe_fc_full:\n\t\t\thw->fc.requested_mode = ixgbe_fc_tx_pause;\n\t\t\tbreak;\n\t\tcase ixgbe_fc_rx_pause:\n\t\t\thw->fc.requested_mode = ixgbe_fc_none;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\t/* no change */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* Negotiate the fc mode to use */\n\tixgbe_fc_autoneg(hw);\n\n\t/* Disable any previous flow control settings */\n\tfctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\tfctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);\n\n\trmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);\n\trmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);\n\n\t/*\n\t * The possible values of fc.current_mode are:\n\t * 0: Flow control is completely disabled\n\t * 1: Rx flow control is enabled (we can receive pause frames,\n\t * but not send pause frames).\n\t * 2: Tx flow control is enabled (we can send pause frames but\n\t * we do not support receiving pause frames).\n\t * 3: Both Rx and Tx flow control (symmetric) are enabled.\n\t * other: Invalid.\n\t */\n\tswitch (hw->fc.current_mode) {\n\tcase ixgbe_fc_none:\n\t\t/*\n\t\t * Flow control is disabled by software override or autoneg.\n\t\t * The code below will actually disable it in the HW.\n\t\t */\n\t\tbreak;\n\tcase ixgbe_fc_rx_pause:\n\t\t/*\n\t\t * Rx Flow control is enabled and Tx Flow control is\n\t\t * disabled by software override. Since there really\n\t\t * isn't a way to advertise that we are capable of RX\n\t\t * Pause ONLY, we will advertise that we support both\n\t\t * symmetric and asymmetric Rx PAUSE. Later, we will\n\t\t * disable the adapter's ability to send PAUSE frames.\n\t\t */\n\t\tfctrl_reg |= IXGBE_FCTRL_RFCE;\n\t\tbreak;\n\tcase ixgbe_fc_tx_pause:\n\t\t/*\n\t\t * Tx Flow control is enabled, and Rx Flow control is\n\t\t * disabled by software override.\n\t\t */\n\t\trmcs_reg |= IXGBE_RMCS_TFCE_802_3X;\n\t\tbreak;\n\tcase ixgbe_fc_full:\n\t\t/* Flow control (both Rx and Tx) is enabled by SW override. */\n\t\tfctrl_reg |= IXGBE_FCTRL_RFCE;\n\t\trmcs_reg |= IXGBE_RMCS_TFCE_802_3X;\n\t\tbreak;\n\tdefault:\n\t\thw_dbg(hw, \"Flow control param set incorrectly\\n\");\n\t\tret_val = IXGBE_ERR_CONFIG;\n\t\tgoto out;\n\t\tbreak;\n\t}\n\n\t/* Set 802.3x based flow control settings. */\n\tfctrl_reg |= IXGBE_FCTRL_DPF;\n\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);\n\tIXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);\n\n\t/* Set up and enable Rx high/low water mark thresholds, enable XON. */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tif ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&\n\t\t hw->fc.high_water[i]) {\n\t\t\tfcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;\n\t\t\tfcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);\n\t\t} else {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);\n\t\t}\n\n\t}\n\n\t/* Configure pause time (2 TCs per register) */\n\treg = hw->fc.pause_time * 0x00010001;\n\tfor (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);\n\n\t/* Configure flow control refresh threshold value */\n\tIXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_start_mac_link_82598 - Configures MAC link settings\n * @hw: pointer to hardware structure\n *\n * Configures link settings based on values in the ixgbe_hw struct.\n * Restarts the link. Performs autonegotiation if needed.\n **/\nstatic s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t bool autoneg_wait_to_complete)\n{\n\tu32 autoc_reg;\n\tu32 links_reg;\n\tu32 i;\n\ts32 status = 0;\n\n\t/* Restart link */\n\tautoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tautoc_reg |= IXGBE_AUTOC_AN_RESTART;\n\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);\n\n\t/* Only poll for autoneg to complete if specified to do so */\n\tif (autoneg_wait_to_complete) {\n\t\tif ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==\n\t\t IXGBE_AUTOC_LMS_KX4_AN ||\n\t\t (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==\n\t\t IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {\n\t\t\tlinks_reg = 0; /* Just in case Autoneg time = 0 */\n\t\t\tfor (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {\n\t\t\t\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\t\t\t\tif (links_reg & IXGBE_LINKS_KX_AN_COMP)\n\t\t\t\t\tbreak;\n\t\t\t\tmsleep(100);\n\t\t\t}\n\t\t\tif (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {\n\t\t\t\tstatus = IXGBE_ERR_AUTONEG_NOT_COMPLETE;\n\t\t\t\thw_dbg(hw, \"Autonegotiation did not complete.\\n\");\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Add delay to filter out noises during initial link setup */\n\tmsleep(50);\n\n\treturn status;\n}\n\n/**\n * ixgbe_validate_link_ready - Function looks for phy link\n * @hw: pointer to hardware structure\n *\n * Function indicates success when phy link is available. If phy is not ready\n * within 5 seconds of MAC indicating link, the function returns error.\n **/\nstatic s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)\n{\n\tu32 timeout;\n\tu16 an_reg;\n\n\tif (hw->device_id != IXGBE_DEV_ID_82598AT2)\n\t\treturn 0;\n\n\tfor (timeout = 0;\n\t timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);\n\n\t\tif ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&\n\t\t (an_reg & IXGBE_MII_AUTONEG_LINK_UP))\n\t\t\tbreak;\n\n\t\tmsleep(100);\n\t}\n\n\tif (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {\n\t\thw_dbg(hw, \"Link was indicated but link is down\\n\");\n\t\treturn IXGBE_ERR_LINK_SETUP;\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_check_mac_link_82598 - Get link/speed status\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @link_up: true is link is up, false otherwise\n * @link_up_wait_to_complete: bool used to wait for link up or not\n *\n * Reads the links register to determine if link is up and the current speed\n **/\nstatic s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed, bool *link_up,\n\t\t\t\t bool link_up_wait_to_complete)\n{\n\tu32 links_reg;\n\tu32 i;\n\tu16 link_reg, adapt_comp_reg;\n\n\t/*\n\t * SERDES PHY requires us to read link status from undocumented\n\t * register 0xC79F. Bit 0 set indicates link is up/ready; clear\n\t * indicates link down. OxC00C is read to check that the XAUI lanes\n\t * are active. Bit 0 clear indicates active; set indicates inactive.\n\t */\n\tif (hw->phy.type == ixgbe_phy_nl) {\n\t\thw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);\n\t\thw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);\n\t\thw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,\n\t\t\t\t &adapt_comp_reg);\n\t\tif (link_up_wait_to_complete) {\n\t\t\tfor (i = 0; i < IXGBE_LINK_UP_TIME; i++) {\n\t\t\t\tif ((link_reg & 1) &&\n\t\t\t\t ((adapt_comp_reg & 1) == 0)) {\n\t\t\t\t\t*link_up = true;\n\t\t\t\t\tbreak;\n\t\t\t\t} else {\n\t\t\t\t\t*link_up = false;\n\t\t\t\t}\n\t\t\t\tmsleep(100);\n\t\t\t\thw->phy.ops.read_reg(hw, 0xC79F,\n\t\t\t\t\t\t IXGBE_TWINAX_DEV,\n\t\t\t\t\t\t &link_reg);\n\t\t\t\thw->phy.ops.read_reg(hw, 0xC00C,\n\t\t\t\t\t\t IXGBE_TWINAX_DEV,\n\t\t\t\t\t\t &adapt_comp_reg);\n\t\t\t}\n\t\t} else {\n\t\t\tif ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))\n\t\t\t\t*link_up = true;\n\t\t\telse\n\t\t\t\t*link_up = false;\n\t\t}\n\n\t\tif (*link_up == false)\n\t\t\tgoto out;\n\t}\n\n\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\tif (link_up_wait_to_complete) {\n\t\tfor (i = 0; i < IXGBE_LINK_UP_TIME; i++) {\n\t\t\tif (links_reg & IXGBE_LINKS_UP) {\n\t\t\t\t*link_up = true;\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\t*link_up = false;\n\t\t\t}\n\t\t\tmsleep(100);\n\t\t\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\t\t}\n\t} else {\n\t\tif (links_reg & IXGBE_LINKS_UP)\n\t\t\t*link_up = true;\n\t\telse\n\t\t\t*link_up = false;\n\t}\n\n\tif (links_reg & IXGBE_LINKS_SPEED)\n\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\telse\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\n\tif ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&\n\t (ixgbe_validate_link_ready(hw) != 0))\n\t\t*link_up = false;\n\nout:\n\treturn 0;\n}\n\n/**\n * ixgbe_setup_mac_link_82598 - Set MAC link speed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg: true if autonegotiation enabled\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Set the link speed in the AUTOC register and restarts link.\n **/\nstatic s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed, bool autoneg,\n\t\t\t\t bool autoneg_wait_to_complete)\n{\n\ts32 status = 0;\n\tixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;\n\tu32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tu32 autoc = curr_autoc;\n\tu32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;\n\n\t/* Check to see if speed passed in is supported. */\n\tixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);\n\tspeed &= link_capabilities;\n\n\tif (speed == IXGBE_LINK_SPEED_UNKNOWN)\n\t\tstatus = IXGBE_ERR_LINK_SETUP;\n\n\t/* Set KX4/KX support according to speed requested */\n\telse if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||\n\t\t link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {\n\t\tautoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;\n\t\tif (speed & IXGBE_LINK_SPEED_10GB_FULL)\n\t\t\tautoc |= IXGBE_AUTOC_KX4_SUPP;\n\t\tif (speed & IXGBE_LINK_SPEED_1GB_FULL)\n\t\t\tautoc |= IXGBE_AUTOC_KX_SUPP;\n\t\tif (autoc != curr_autoc)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);\n\t}\n\n\tif (status == 0) {\n\t\t/*\n\t\t * Setup and restart the link based on the new values in\n\t\t * ixgbe_hw This will write the AUTOC register based on the new\n\t\t * stored values\n\t\t */\n\t\tstatus = ixgbe_start_mac_link_82598(hw,\n\t\t\t\t\t\t autoneg_wait_to_complete);\n\t}\n\n\treturn status;\n}\n\n\n/**\n * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg: true if autonegotiation enabled\n * @autoneg_wait_to_complete: true if waiting is needed to complete\n *\n * Sets the link speed in the AUTOC register in the MAC and restarts link.\n **/\nstatic s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t\t bool autoneg,\n\t\t\t\t\t bool autoneg_wait_to_complete)\n{\n\ts32 status;\n\n\t/* Setup the PHY according to input speed */\n\tstatus = hw->phy.ops.setup_link_speed(hw, speed, autoneg,\n\t\t\t\t\t autoneg_wait_to_complete);\n\t/* Set up MAC */\n\tixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);\n\n\treturn status;\n}\n\n/**\n * ixgbe_reset_hw_82598 - Performs hardware reset\n * @hw: pointer to hardware structure\n *\n * Resets the hardware by resetting the transmit and receive units, masks and\n * clears all interrupts, performing a PHY reset, and performing a link (MAC)\n * reset.\n **/\nstatic s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\ts32 phy_status = 0;\n\tu32 ctrl;\n\tu32 gheccr;\n\tu32 i;\n\tu32 autoc;\n\tu8 analog_val;\n\n\t/* Call adapter stop to disable tx/rx and clear interrupts */\n\tstatus = hw->mac.ops.stop_adapter(hw);\n\tif (status != 0)\n\t\tgoto reset_hw_out;\n\n\t/*\n\t * Power up the Atlas Tx lanes if they are currently powered down.\n\t * Atlas Tx lanes are powered down for MAC loopback tests, but\n\t * they are not automatically restored on reset.\n\t */\n\thw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);\n\tif (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {\n\t\t/* Enable Tx Atlas so packets can be transmitted again */\n\t\thw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,\n\t\t\t\t\t &analog_val);\n\t\tanalog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;\n\t\thw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,\n\t\t\t\t\t analog_val);\n\n\t\thw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,\n\t\t\t\t\t &analog_val);\n\t\tanalog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;\n\t\thw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,\n\t\t\t\t\t analog_val);\n\n\t\thw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,\n\t\t\t\t\t &analog_val);\n\t\tanalog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;\n\t\thw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,\n\t\t\t\t\t analog_val);\n\n\t\thw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,\n\t\t\t\t\t &analog_val);\n\t\tanalog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;\n\t\thw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,\n\t\t\t\t\t analog_val);\n\t}\n\n\t/* Reset PHY */\n\tif (hw->phy.reset_disable == false) {\n\t\t/* PHY ops must be identified and initialized prior to reset */\n\n\t\t/* Init PHY and function pointers, perform SFP setup */\n\t\tphy_status = hw->phy.ops.init(hw);\n\t\tif (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)\n\t\t\tgoto reset_hw_out;\n\t\tif (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)\n\t\t\tgoto mac_reset_top;\n\n\t\thw->phy.ops.reset(hw);\n\t}\n\nmac_reset_top:\n\t/*\n\t * Issue global reset to the MAC. This needs to be a SW reset.\n\t * If link reset is used, it might reset the MAC when mng is using it\n\t */\n\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Poll for reset bit to self-clear indicating reset is complete */\n\tfor (i = 0; i < 10; i++) {\n\t\tudelay(1);\n\t\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);\n\t\tif (!(ctrl & IXGBE_CTRL_RST))\n\t\t\tbreak;\n\t}\n\tif (ctrl & IXGBE_CTRL_RST) {\n\t\tstatus = IXGBE_ERR_RESET_FAILED;\n\t\thw_dbg(hw, \"Reset polling failed to complete.\\n\");\n\t}\n\n\tmsleep(50);\n\n\t/*\n\t * Double resets are required for recovery from certain error\n\t * conditions. Between resets, it is necessary to stall to allow time\n\t * for any pending HW events to complete.\n\t */\n\tif (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {\n\t\thw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;\n\t\tgoto mac_reset_top;\n\t}\n\n\tgheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);\n\tgheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));\n\tIXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);\n\n\t/*\n\t * Store the original AUTOC value if it has not been\n\t * stored off yet. Otherwise restore the stored original\n\t * AUTOC value since the reset operation sets back to deaults.\n\t */\n\tautoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tif (hw->mac.orig_link_settings_stored == false) {\n\t\thw->mac.orig_autoc = autoc;\n\t\thw->mac.orig_link_settings_stored = true;\n\t} else if (autoc != hw->mac.orig_autoc) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);\n\t}\n\n\t/* Store the permanent mac address */\n\thw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);\n\n\t/*\n\t * Store MAC address from RAR0, clear receive address registers, and\n\t * clear the multicast table\n\t */\n\thw->mac.ops.init_rx_addrs(hw);\n\nreset_hw_out:\n\tif (phy_status != 0)\n\t\tstatus = phy_status;\n\n\treturn status;\n}\n\n/**\n * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address\n * @hw: pointer to hardware struct\n * @rar: receive address register index to associate with a VMDq index\n * @vmdq: VMDq set index\n **/\ns32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n{\n\tu32 rar_high;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\t/* Make sure we are using a valid rar index range */\n\tif (rar >= rar_entries) {\n\t\thw_dbg(hw, \"RAR index %d is out of range.\\n\", rar);\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));\n\trar_high &= ~IXGBE_RAH_VIND_MASK;\n\trar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);\n\tIXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);\n\treturn 0;\n}\n\n/**\n * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address\n * @hw: pointer to hardware struct\n * @rar: receive address register index to associate with a VMDq index\n * @vmdq: VMDq clear index (not used in 82598, but elsewhere)\n **/\nstatic s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n{\n\tu32 rar_high;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\n\t/* Make sure we are using a valid rar index range */\n\tif (rar >= rar_entries) {\n\t\thw_dbg(hw, \"RAR index %d is out of range.\\n\", rar);\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));\n\tif (rar_high & IXGBE_RAH_VIND_MASK) {\n\t\trar_high &= ~IXGBE_RAH_VIND_MASK;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_set_vfta_82598 - Set VLAN filter table\n * @hw: pointer to hardware structure\n * @vlan: VLAN id to write to VLAN filter\n * @vind: VMDq output index that maps queue to VLAN id in VFTA\n * @vlan_on: boolean flag to turn on/off VLAN in VFTA\n *\n * Turn on/off specified VLAN in the VLAN filter table.\n **/\ns32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n\t\t\t bool vlan_on)\n{\n\tu32 regindex;\n\tu32 bitindex;\n\tu32 bits;\n\tu32 vftabyte;\n\n\tif (vlan > 4095)\n\t\treturn IXGBE_ERR_PARAM;\n\n\t/* Determine 32-bit word position in array */\n\tregindex = (vlan >> 5) & 0x7F; /* upper seven bits */\n\n\t/* Determine the location of the (VMD) queue index */\n\tvftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */\n\tbitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */\n\n\t/* Set the nibble for VMD queue index */\n\tbits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));\n\tbits &= (~(0x0F << bitindex));\n\tbits |= (vind << bitindex);\n\tIXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);\n\n\t/* Determine the location of the bit for this VLAN id */\n\tbitindex = vlan & 0x1F; /* lower five bits */\n\n\tbits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));\n\tif (vlan_on)\n\t\t/* Turn on this VLAN id */\n\t\tbits |= (1 << bitindex);\n\telse\n\t\t/* Turn off this VLAN id */\n\t\tbits &= ~(1 << bitindex);\n\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_clear_vfta_82598 - Clear VLAN filter table\n * @hw: pointer to hardware structure\n *\n * Clears the VLAN filer table, and the VMDq index associated with the filter\n **/\nstatic s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)\n{\n\tu32 offset;\n\tu32 vlanbyte;\n\n\tfor (offset = 0; offset < hw->mac.vft_size; offset++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);\n\n\tfor (vlanbyte = 0; vlanbyte < 4; vlanbyte++)\n\t\tfor (offset = 0; offset < hw->mac.vft_size; offset++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),\n\t\t\t\t\t0);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register\n * @hw: pointer to hardware structure\n * @reg: analog register to read\n * @val: read value\n *\n * Performs read operation to Atlas analog register specified.\n **/\ns32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)\n{\n\tu32 atlas_ctl;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,\n\t\t\tIXGBE_ATLASCTL_WRITE_CMD | (reg << 8));\n\tIXGBE_WRITE_FLUSH(hw);\n\tudelay(10);\n\tatlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);\n\t*val = (u8)atlas_ctl;\n\n\treturn 0;\n}\n\n/**\n * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register\n * @hw: pointer to hardware structure\n * @reg: atlas register to write\n * @val: value to write\n *\n * Performs write operation to Atlas analog register specified.\n **/\ns32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)\n{\n\tu32 atlas_ctl;\n\n\tatlas_ctl = (reg << 8) | val;\n\tIXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);\n\tIXGBE_WRITE_FLUSH(hw);\n\tudelay(10);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.\n * @hw: pointer to hardware structure\n * @byte_offset: EEPROM byte offset to read\n * @eeprom_data: value read\n *\n * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\tu8 *eeprom_data)\n{\n\ts32 status = 0;\n\tu16 sfp_addr = 0;\n\tu16 sfp_data = 0;\n\tu16 sfp_stat = 0;\n\tu32 i;\n\n\tif (hw->phy.type == ixgbe_phy_nl) {\n\t\t/*\n\t\t * NetLogic phy SDA/SCL registers are at addresses 0xC30A to\n\t\t * 0xC30D. These registers are used to talk to the SFP+\n\t\t * module's EEPROM through the SDA/SCL (I2C) interface.\n\t\t */\n\t\tsfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;\n\t\tsfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);\n\t\thw->phy.ops.write_reg(hw,\n\t\t\t\t IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,\n\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t sfp_addr);\n\n\t\t/* Poll status */\n\t\tfor (i = 0; i < 100; i++) {\n\t\t\thw->phy.ops.read_reg(hw,\n\t\t\t\t\t IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,\n\t\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t\t &sfp_stat);\n\t\t\tsfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;\n\t\t\tif (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)\n\t\t\t\tbreak;\n\t\t\tmsleep(10);\n\t\t}\n\n\t\tif (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {\n\t\t\thw_dbg(hw, \"EEPROM read did not pass.\\n\");\n\t\t\tstatus = IXGBE_ERR_SFP_NOT_PRESENT;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/* Read data */\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,\n\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);\n\n\t\t*eeprom_data = (u8)(sfp_data >> 8);\n\t} else {\n\t\tstatus = IXGBE_ERR_PHY;\n\t\tgoto out;\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type\n * @hw: pointer to hardware structure\n *\n * Determines physical layer capabilities of the current configuration.\n **/\nu32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)\n{\n\tu32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n\tu32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tu32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;\n\tu32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;\n\tu16 ext_ability = 0;\n\n\thw->phy.ops.identify(hw);\n\n\t/* Copper PHY must be checked before AUTOC LMS to determine correct\n\t * physical layer because 10GBase-T PHYs use LMS = KX4/KX */\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_tn:\n\tcase ixgbe_phy_cu_unknown:\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,\n\t\tIXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);\n\t\tif (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;\n\t\tif (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;\n\t\tif (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;\n\t\tgoto out;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tswitch (autoc & IXGBE_AUTOC_LMS_MASK) {\n\tcase IXGBE_AUTOC_LMS_1G_AN:\n\tcase IXGBE_AUTOC_LMS_1G_LINK_NO_AN:\n\t\tif (pma_pmd_1g == IXGBE_AUTOC_1G_KX)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;\n\t\telse\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;\n\t\tbreak;\n\tcase IXGBE_AUTOC_LMS_10G_LINK_NO_AN:\n\t\tif (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;\n\t\telse if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;\n\t\telse /* XAUI */\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n\t\tbreak;\n\tcase IXGBE_AUTOC_LMS_KX4_AN:\n\tcase IXGBE_AUTOC_LMS_KX4_AN_1G_AN:\n\t\tif (autoc & IXGBE_AUTOC_KX_SUPP)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;\n\t\tif (autoc & IXGBE_AUTOC_KX4_SUPP)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (hw->phy.type == ixgbe_phy_nl) {\n\t\thw->phy.ops.identify_sfp(hw);\n\n\t\tswitch (hw->phy.sfp_type) {\n\t\tcase ixgbe_sfp_type_da_cu:\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;\n\t\t\tbreak;\n\t\tcase ixgbe_sfp_type_sr:\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;\n\t\t\tbreak;\n\t\tcase ixgbe_sfp_type_lr:\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tswitch (hw->device_id) {\n\tcase IXGBE_DEV_ID_82598_DA_DUAL_PORT:\n\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82598AF_DUAL_PORT:\n\tcase IXGBE_DEV_ID_82598AF_SINGLE_PORT:\n\tcase IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:\n\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82598EB_XF_LR:\n\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\nout:\n\treturn physical_layer;\n}\n\n/**\n * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple\n * port devices.\n * @hw: pointer to the HW structure\n *\n * Calls common function and corrects issue with some single port devices\n * that enable LAN1 but not LAN0.\n **/\nvoid ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_bus_info *bus = &hw->bus;\n\tu16 pci_gen = 0;\n\tu16 pci_ctrl2 = 0;\n\n\tixgbe_set_lan_id_multi_port_pcie(hw);\n\n\t/* check if LAN0 is disabled */\n\thw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);\n\tif ((pci_gen != 0) && (pci_gen != 0xFFFF)) {\n\n\t\thw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);\n\n\t\t/* if LAN0 is completely disabled force function to 0 */\n\t\tif ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&\n\t\t !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&\n\t\t !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {\n\n\t\t\tbus->func = 0;\n\t\t}\n\t}\n}\n\n/**\n * ixgbe_set_rxpba_82598 - Initialize RX packet buffer\n * @hw: pointer to hardware structure\n * @num_pb: number of packet buffers to allocate\n * @headroom: reserve n KB of headroom\n * @strategy: packet buffer allocation strategy\n **/\nstatic void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,\n\t\t\t\t u32 headroom, int strategy)\n{\n\tu32 rxpktsize = IXGBE_RXPBSIZE_64KB;\n\tu8 i = 0;\n\n\tif (!num_pb)\n\t\treturn;\n\n\t/* Setup Rx packet buffer sizes */\n\tswitch (strategy) {\n\tcase PBA_STRATEGY_WEIGHTED:\n\t\t/* Setup the first four at 80KB */\n\t\trxpktsize = IXGBE_RXPBSIZE_80KB;\n\t\tfor (; i < 4; i++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);\n\t\t/* Setup the last four at 48KB...don't re-init i */\n\t\trxpktsize = IXGBE_RXPBSIZE_48KB;\n\t\t/* Fall Through */\n\tcase PBA_STRATEGY_EQUAL:\n\tdefault:\n\t\t/* Divide the remaining Rx packet buffer evenly among the TCs */\n\t\tfor (; i < IXGBE_MAX_PACKET_BUFFERS; i++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);\n\t\tbreak;\n\t}\n\n\t/* Setup Tx packet buffer sizes */\n\tfor (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);\n\n\treturn;\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_82598.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _IXGBE_82598_H_\n#define _IXGBE_82598_H_\n\nu32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);\ns32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw);\ns32 ixgbe_start_hw_82598(struct ixgbe_hw *hw);\ns32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);\ns32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on);\ns32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);\ns32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);\ns32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\tu8 *eeprom_data);\nu32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);\ns32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);\nvoid ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);\nvoid ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);\n#endif /* _IXGBE_82598_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_82599.c", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"ixgbe_type.h\"\n#include \"ixgbe_82599.h\"\n#include \"ixgbe_api.h\"\n#include \"ixgbe_common.h\"\n#include \"ixgbe_phy.h\"\n\nstatic s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t\t bool autoneg,\n\t\t\t\t\t bool autoneg_wait_to_complete);\nstatic s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);\nstatic s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,\n\t\t\t\t u16 offset, u16 *data);\nstatic s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data);\nstatic s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\tu8 dev_addr, u8 *data);\nstatic s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t\tu8 dev_addr, u8 data);\n\nvoid ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\n\t/* enable the laser control functions for SFP+ fiber */\n\tif (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {\n\t\tmac->ops.disable_tx_laser =\n\t\t\t\t &ixgbe_disable_tx_laser_multispeed_fiber;\n\t\tmac->ops.enable_tx_laser =\n\t\t\t\t\t&ixgbe_enable_tx_laser_multispeed_fiber;\n\t\tmac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;\n\n\t} else {\n\t\tmac->ops.disable_tx_laser = NULL;\n\t\tmac->ops.enable_tx_laser = NULL;\n\t\tmac->ops.flap_tx_laser = NULL;\n\t}\n\n\tif (hw->phy.multispeed_fiber) {\n\t\t/* Set up dual speed SFP+ support */\n\t\tmac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;\n\t} else {\n\t\tif ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&\n\t\t (hw->phy.smart_speed == ixgbe_smart_speed_auto ||\n\t\t hw->phy.smart_speed == ixgbe_smart_speed_on) &&\n\t\t !ixgbe_verify_lesm_fw_enabled_82599(hw)) {\n\t\t\tmac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;\n\t\t} else {\n\t\t\tmac->ops.setup_link = &ixgbe_setup_mac_link_82599;\n\t\t}\n\t}\n}\n\n/**\n * ixgbe_init_phy_ops_82599 - PHY/SFP specific init\n * @hw: pointer to hardware structure\n *\n * Initialize any function pointers that were not able to be\n * set during init_shared_code because the PHY/SFP type was\n * not known. Perform the SFP init if necessary.\n *\n **/\ns32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\ts32 ret_val = 0;\n\tu32 esdp;\n\n\tif (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {\n\t\t/* Store flag indicating I2C bus access control unit. */\n\t\thw->phy.qsfp_shared_i2c_bus = TRUE;\n\n\t\t/* Initialize access to QSFP+ I2C bus */\n\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\tesdp |= IXGBE_ESDP_SDP0_DIR;\n\t\tesdp &= ~IXGBE_ESDP_SDP1_DIR;\n\t\tesdp &= ~IXGBE_ESDP_SDP0;\n\t\tesdp &= ~IXGBE_ESDP_SDP0_NATIVE;\n\t\tesdp &= ~IXGBE_ESDP_SDP1_NATIVE;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\n\t\tphy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;\n\t\tphy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;\n\t}\n\t/* Identify the PHY or SFP module */\n\tret_val = phy->ops.identify(hw);\n\tif (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)\n\t\tgoto init_phy_ops_out;\n\n\t/* Setup function pointers based on detected SFP module and speeds */\n\tixgbe_init_mac_link_ops_82599(hw);\n\tif (hw->phy.sfp_type != ixgbe_sfp_type_unknown)\n\t\thw->phy.ops.reset = NULL;\n\n\t/* If copper media, overwrite with copper function pointers */\n\tif (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {\n\t\tmac->ops.setup_link = &ixgbe_setup_copper_link_82599;\n\t\tmac->ops.get_link_capabilities =\n\t\t\t\t &ixgbe_get_copper_link_capabilities_generic;\n\t}\n\n\t/* Set necessary function pointers based on phy type */\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_tn:\n\t\tphy->ops.setup_link = &ixgbe_setup_phy_link_tnx;\n\t\tphy->ops.check_link = &ixgbe_check_phy_link_tnx;\n\t\tphy->ops.get_firmware_version =\n\t\t\t &ixgbe_get_phy_firmware_version_tnx;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\ninit_phy_ops_out:\n\treturn ret_val;\n}\n\ns32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = 0;\n\tu32 reg_anlp1 = 0;\n\tu32 i = 0;\n\tu16 list_offset, data_offset, data_value;\n\n\tif (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {\n\t\tixgbe_init_mac_link_ops_82599(hw);\n\n\t\thw->phy.ops.reset = NULL;\n\n\t\tret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,\n\t\t\t\t\t\t\t &data_offset);\n\t\tif (ret_val != 0)\n\t\t\tgoto setup_sfp_out;\n\n\t\t/* PHY config will finish before releasing the semaphore */\n\t\tret_val = hw->mac.ops.acquire_swfw_sync(hw,\n\t\t\t\t\t\t\tIXGBE_GSSR_MAC_CSR_SM);\n\t\tif (ret_val != 0) {\n\t\t\tret_val = IXGBE_ERR_SWFW_SYNC;\n\t\t\tgoto setup_sfp_out;\n\t\t}\n\n\t\thw->eeprom.ops.read(hw, ++data_offset, &data_value);\n\t\twhile (data_value != 0xffff) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);\n\t\t\tIXGBE_WRITE_FLUSH(hw);\n\t\t\thw->eeprom.ops.read(hw, ++data_offset, &data_value);\n\t\t}\n\n\t\t/* Release the semaphore */\n\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);\n\t\t/* Delay obtaining semaphore again to allow FW access */\n\t\tmsleep(hw->eeprom.semaphore_delay);\n\n\t\t/* Now restart DSP by setting Restart_AN and clearing LMS */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,\n\t\t\t\tIXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |\n\t\t\t\tIXGBE_AUTOC_AN_RESTART));\n\n\t\t/* Wait for AN to leave state 0 */\n\t\tfor (i = 0; i < 10; i++) {\n\t\t\tmsleep(4);\n\t\t\treg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);\n\t\t\tif (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)\n\t\t\t\tbreak;\n\t\t}\n\t\tif (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {\n\t\t\thw_dbg(hw, \"sfp module setup not complete\\n\");\n\t\t\tret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;\n\t\t\tgoto setup_sfp_out;\n\t\t}\n\n\t\t/* Restart DSP by setting Restart_AN and return to SFI mode */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,\n\t\t\t\tIXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |\n\t\t\t\tIXGBE_AUTOC_AN_RESTART));\n\t}\n\nsetup_sfp_out:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_init_ops_82599 - Inits func ptrs and MAC type\n * @hw: pointer to hardware structure\n *\n * Initialize the function pointers and assign the MAC type for 82599.\n * Does not touch the hardware.\n **/\n\ns32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\ts32 ret_val;\n\n\tixgbe_init_phy_ops_generic(hw);\n\tret_val = ixgbe_init_ops_generic(hw);\n\n\t/* PHY */\n\tphy->ops.identify = &ixgbe_identify_phy_82599;\n\tphy->ops.init = &ixgbe_init_phy_ops_82599;\n\n\t/* MAC */\n\tmac->ops.reset_hw = &ixgbe_reset_hw_82599;\n\tmac->ops.get_media_type = &ixgbe_get_media_type_82599;\n\tmac->ops.get_supported_physical_layer =\n\t\t\t\t &ixgbe_get_supported_physical_layer_82599;\n\tmac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;\n\tmac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;\n\tmac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;\n\tmac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;\n\tmac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;\n\tmac->ops.start_hw = &ixgbe_start_hw_82599;\n\tmac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;\n\tmac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;\n\tmac->ops.get_device_caps = &ixgbe_get_device_caps_generic;\n\tmac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;\n\tmac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;\n\n\t/* RAR, Multicast, VLAN */\n\tmac->ops.set_vmdq = &ixgbe_set_vmdq_generic;\n\tmac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;\n\tmac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;\n\tmac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;\n\tmac->rar_highwater = 1;\n\tmac->ops.set_vfta = &ixgbe_set_vfta_generic;\n\tmac->ops.set_vlvf = &ixgbe_set_vlvf_generic;\n\tmac->ops.clear_vfta = &ixgbe_clear_vfta_generic;\n\tmac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;\n\tmac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;\n\tmac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;\n\tmac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;\n\n\t/* Link */\n\tmac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;\n\tmac->ops.check_link = &ixgbe_check_mac_link_generic;\n\tmac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;\n\tixgbe_init_mac_link_ops_82599(hw);\n\n\tmac->mcft_size\t\t= 128;\n\tmac->vft_size\t\t= 128;\n\tmac->num_rar_entries\t= 128;\n\tmac->rx_pb_size\t\t= 512;\n\tmac->max_tx_queues\t= 128;\n\tmac->max_rx_queues\t= 128;\n\tmac->max_msix_vectors\t= ixgbe_get_pcie_msix_count_generic(hw);\n\n\tmac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &\n\t\t\t\t IXGBE_FWSM_MODE_MASK) ? true : false;\n\n\t//hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;\n\n\t/* EEPROM */\n\teeprom->ops.read = &ixgbe_read_eeprom_82599;\n\teeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;\n\n\t/* Manageability interface */\n\tmac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;\n\n\tmac->ops.get_thermal_sensor_data =\n\t\t\t\t\t &ixgbe_get_thermal_sensor_data_generic;\n\tmac->ops.init_thermal_sensor_thresh =\n\t\t\t\t &ixgbe_init_thermal_sensor_thresh_generic;\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_get_link_capabilities_82599 - Determines link capabilities\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @negotiation: true when autoneg or autotry is enabled\n *\n * Determines the link capabilities by reading the AUTOC register.\n **/\ns32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t bool *negotiation)\n{\n\ts32 status = 0;\n\tu32 autoc = 0;\n\n\t/* Check if 1G SFP module. */\n\tif (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||\n\t hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||\n\t hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||\n\t hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*negotiation = true;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * Determine link capabilities based on the stored value of AUTOC,\n\t * which represents EEPROM defaults. If AUTOC value has not\n\t * been stored, use the current register values.\n\t */\n\tif (hw->mac.orig_link_settings_stored)\n\t\tautoc = hw->mac.orig_autoc;\n\telse\n\t\tautoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\n\tswitch (autoc & IXGBE_AUTOC_LMS_MASK) {\n\tcase IXGBE_AUTOC_LMS_1G_LINK_NO_AN:\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*negotiation = false;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_10G_LINK_NO_AN:\n\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\t\t*negotiation = false;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_1G_AN:\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*negotiation = true;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_10G_SERIAL:\n\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\t\t*negotiation = false;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_KX4_KX_KR:\n\tcase IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:\n\t\t*speed = IXGBE_LINK_SPEED_UNKNOWN;\n\t\tif (autoc & IXGBE_AUTOC_KR_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (autoc & IXGBE_AUTOC_KX4_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (autoc & IXGBE_AUTOC_KX_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*negotiation = true;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:\n\t\t*speed = IXGBE_LINK_SPEED_100_FULL;\n\t\tif (autoc & IXGBE_AUTOC_KR_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (autoc & IXGBE_AUTOC_KX4_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (autoc & IXGBE_AUTOC_KX_SUPP)\n\t\t\t*speed |= IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*negotiation = true;\n\t\tbreak;\n\n\tcase IXGBE_AUTOC_LMS_SGMII_1G_100M:\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;\n\t\t*negotiation = false;\n\t\tbreak;\n\n\tdefault:\n\t\tstatus = IXGBE_ERR_LINK_SETUP;\n\t\tgoto out;\n\t\tbreak;\n\t}\n\n\tif (hw->phy.multispeed_fiber) {\n\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL |\n\t\t\t IXGBE_LINK_SPEED_1GB_FULL;\n\t\t*negotiation = true;\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_get_media_type_82599 - Get media type\n * @hw: pointer to hardware structure\n *\n * Returns the media type (fiber, copper, backplane)\n **/\nenum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)\n{\n\tenum ixgbe_media_type media_type;\n\n\t/* Detect if there is a copper PHY attached. */\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_cu_unknown:\n\tcase ixgbe_phy_tn:\n\t\tmedia_type = ixgbe_media_type_copper;\n\t\tgoto out;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tswitch (hw->device_id) {\n\tcase IXGBE_DEV_ID_82599_KX4:\n\tcase IXGBE_DEV_ID_82599_KX4_MEZZ:\n\tcase IXGBE_DEV_ID_82599_COMBO_BACKPLANE:\n\tcase IXGBE_DEV_ID_82599_KR:\n\tcase IXGBE_DEV_ID_82599_BACKPLANE_FCOE:\n\tcase IXGBE_DEV_ID_82599_XAUI_LOM:\n\t\t/* Default device ID is mezzanine card KX/KX4 */\n\t\tmedia_type = ixgbe_media_type_backplane;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_SFP:\n\tcase IXGBE_DEV_ID_82599_SFP_FCOE:\n\tcase IXGBE_DEV_ID_82599_SFP_EM:\n\tcase IXGBE_DEV_ID_82599_SFP_SF2:\n\tcase IXGBE_DEV_ID_82599EN_SFP:\n\t\tmedia_type = ixgbe_media_type_fiber;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_CX4:\n\t\tmedia_type = ixgbe_media_type_cx4;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_T3_LOM:\n\t\tmedia_type = ixgbe_media_type_copper;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_LS:\n\t\tmedia_type = ixgbe_media_type_fiber_lco;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_QSFP_SF_QP:\n\t\tmedia_type = ixgbe_media_type_fiber_qsfp;\n\t\tbreak;\n\tdefault:\n\t\tmedia_type = ixgbe_media_type_unknown;\n\t\tbreak;\n\t}\nout:\n\treturn media_type;\n}\n\n/**\n * ixgbe_start_mac_link_82599 - Setup MAC link settings\n * @hw: pointer to hardware structure\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Configures link settings based on values in the ixgbe_hw struct.\n * Restarts the link. Performs autonegotiation if needed.\n **/\ns32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,\n\t\t\t bool autoneg_wait_to_complete)\n{\n\tu32 autoc_reg;\n\tu32 links_reg = 0;\n\tu32 i;\n\ts32 status = 0;\n\n\t/* Restart link */\n\tautoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tautoc_reg |= IXGBE_AUTOC_AN_RESTART;\n\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);\n\n\t/* Only poll for autoneg to complete if specified to do so */\n\tif (autoneg_wait_to_complete) {\n\t\tif ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==\n\t\t IXGBE_AUTOC_LMS_KX4_KX_KR ||\n\t\t (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==\n\t\t IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||\n\t\t (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==\n\t\t IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {\n\t\t\tfor (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {\n\t\t\t\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\t\t\t\tif (links_reg & IXGBE_LINKS_KX_AN_COMP)\n\t\t\t\t\tbreak;\n\t\t\t\tmsleep(100);\n\t\t\t}\n\t\t\tif (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {\n\t\t\t\tstatus = IXGBE_ERR_AUTONEG_NOT_COMPLETE;\n\t\t\t\thw_dbg(hw, \"Autoneg did not complete.\\n\");\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Add delay to filter out noises during initial link setup */\n\tmsleep(50);\n\n\treturn status;\n}\n\n/**\n * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser\n * @hw: pointer to hardware structure\n *\n * The base drivers may require better control over SFP+ module\n * PHY states. This includes selectively shutting down the Tx\n * laser on the PHY, effectively halting physical link.\n **/\nvoid ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n{\n\tu32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\n\t/* Disable tx laser; allow 100us to go dark per spec */\n\tesdp_reg |= IXGBE_ESDP_SDP3;\n\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\tudelay(100);\n}\n\n/**\n * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser\n * @hw: pointer to hardware structure\n *\n * The base drivers may require better control over SFP+ module\n * PHY states. This includes selectively turning on the Tx\n * laser on the PHY, effectively starting physical link.\n **/\nvoid ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n{\n\tu32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\n\t/* Enable tx laser; allow 100ms to light up */\n\tesdp_reg &= ~IXGBE_ESDP_SDP3;\n\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\tmsleep(100);\n}\n\n/**\n * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser\n * @hw: pointer to hardware structure\n *\n * When the driver changes the link speeds that it can support,\n * it sets autotry_restart to true to indicate that we need to\n * initiate a new autotry session with the link partner. To do\n * so, we set the speed then disable and re-enable the tx laser, to\n * alert the link partner that it also needs to restart autotry on its\n * end. This is consistent with true clause 37 autoneg, which also\n * involves a loss of signal.\n **/\nvoid ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)\n{\n\tif (hw->mac.autotry_restart) {\n\t\tixgbe_disable_tx_laser_multispeed_fiber(hw);\n\t\tixgbe_enable_tx_laser_multispeed_fiber(hw);\n\t\thw->mac.autotry_restart = false;\n\t}\n}\n\n/**\n * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg: true if autonegotiation enabled\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Set the link speed in the AUTOC register and restarts link.\n **/\ns32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed, bool autoneg,\n\t\t\t\t bool autoneg_wait_to_complete)\n{\n\ts32 status = 0;\n\tixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;\n\tixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;\n\tu32 speedcnt = 0;\n\tu32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\tu32 i = 0;\n\tbool link_up = false;\n\tbool negotiation;\n\n\t/* Mask off requested but non-supported speeds */\n\tstatus = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);\n\tif (status != 0)\n\t\treturn status;\n\n\tspeed &= link_speed;\n\n\t/*\n\t * Try each speed one by one, highest priority first. We do this in\n\t * software because 10gb fiber doesn't support speed autonegotiation.\n\t */\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL) {\n\t\tspeedcnt++;\n\t\thighest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;\n\n\t\t/* If we already have link at this speed, just jump out */\n\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up, false);\n\t\tif (status != 0)\n\t\t\treturn status;\n\n\t\tif ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)\n\t\t\tgoto out;\n\n\t\t/* Set the module link speed */\n\t\tesdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\n\t\t/* Allow module to change analog characteristics (1G->10G) */\n\t\tmsleep(40);\n\n\t\tstatus = ixgbe_setup_mac_link_82599(hw,\n\t\t\t\t\t\t IXGBE_LINK_SPEED_10GB_FULL,\n\t\t\t\t\t\t autoneg,\n\t\t\t\t\t\t autoneg_wait_to_complete);\n\t\tif (status != 0)\n\t\t\treturn status;\n\n\t\t/* Flap the tx laser if it has not already been done */\n\t\tixgbe_flap_tx_laser(hw);\n\n\t\t/*\n\t\t * Wait for the controller to acquire link. Per IEEE 802.3ap,\n\t\t * Section 73.10.2, we may have to wait up to 500ms if KR is\n\t\t * attempted. 82599 uses the same timing for 10g SFI.\n\t\t */\n\t\tfor (i = 0; i < 5; i++) {\n\t\t\t/* Wait for the link partner to also set speed */\n\t\t\tmsleep(100);\n\n\t\t\t/* If we have link, just jump out */\n\t\t\tstatus = ixgbe_check_link(hw, &link_speed,\n\t\t\t\t\t\t &link_up, false);\n\t\t\tif (status != 0)\n\t\t\t\treturn status;\n\n\t\t\tif (link_up)\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL) {\n\t\tspeedcnt++;\n\t\tif (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)\n\t\t\thighest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;\n\n\t\t/* If we already have link at this speed, just jump out */\n\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up, false);\n\t\tif (status != 0)\n\t\t\treturn status;\n\n\t\tif ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)\n\t\t\tgoto out;\n\n\t\t/* Set the module link speed */\n\t\tesdp_reg &= ~IXGBE_ESDP_SDP5;\n\t\tesdp_reg |= IXGBE_ESDP_SDP5_DIR;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\n\t\t/* Allow module to change analog characteristics (10G->1G) */\n\t\tmsleep(40);\n\n\t\tstatus = ixgbe_setup_mac_link_82599(hw,\n\t\t\t\t\t\t IXGBE_LINK_SPEED_1GB_FULL,\n\t\t\t\t\t\t autoneg,\n\t\t\t\t\t\t autoneg_wait_to_complete);\n\t\tif (status != 0)\n\t\t\treturn status;\n\n\t\t/* Flap the tx laser if it has not already been done */\n\t\tixgbe_flap_tx_laser(hw);\n\n\t\t/* Wait for the link partner to also set speed */\n\t\tmsleep(100);\n\n\t\t/* If we have link, just jump out */\n\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up, false);\n\t\tif (status != 0)\n\t\t\treturn status;\n\n\t\tif (link_up)\n\t\t\tgoto out;\n\t}\n\n\t/*\n\t * We didn't get link. Configure back to the highest speed we tried,\n\t * (if there was more than one). We call ourselves back with just the\n\t * single highest speed that the user requested.\n\t */\n\tif (speedcnt > 1)\n\t\tstatus = ixgbe_setup_mac_link_multispeed_fiber(hw,\n\t\t\thighest_link_speed, autoneg, autoneg_wait_to_complete);\n\nout:\n\t/* Set autoneg_advertised value based on input link speed */\n\thw->phy.autoneg_advertised = 0;\n\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;\n\n\treturn status;\n}\n\n/**\n * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg: true if autonegotiation enabled\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Implements the Intel SmartSpeed algorithm.\n **/\ns32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed, bool autoneg,\n\t\t\t\t bool autoneg_wait_to_complete)\n{\n\ts32 status = 0;\n\tixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;\n\ts32 i, j;\n\tbool link_up = false;\n\tu32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\n\t /* Set autoneg_advertised value based on input link speed */\n\thw->phy.autoneg_advertised = 0;\n\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_100_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;\n\n\t/*\n\t * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the\n\t * autoneg advertisement if link is unable to be established at the\n\t * highest negotiated rate. This can sometimes happen due to integrity\n\t * issues with the physical media connection.\n\t */\n\n\t/* First, try to get link with full advertisement */\n\thw->phy.smart_speed_active = false;\n\tfor (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {\n\t\tstatus = ixgbe_setup_mac_link_82599(hw, speed, autoneg,\n\t\t\t\t\t\t autoneg_wait_to_complete);\n\t\tif (status != 0)\n\t\t\tgoto out;\n\n\t\t/*\n\t\t * Wait for the controller to acquire link. Per IEEE 802.3ap,\n\t\t * Section 73.10.2, we may have to wait up to 500ms if KR is\n\t\t * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per\n\t\t * Table 9 in the AN MAS.\n\t\t */\n\t\tfor (i = 0; i < 5; i++) {\n\t\t\tmsleep(100);\n\n\t\t\t/* If we have link, just jump out */\n\t\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up,\n\t\t\t\t\t\t false);\n\t\t\tif (status != 0)\n\t\t\t\tgoto out;\n\n\t\t\tif (link_up)\n\t\t\t\tgoto out;\n\t\t}\n\t}\n\n\t/*\n\t * We didn't get link. If we advertised KR plus one of KX4/KX\n\t * (or BX4/BX), then disable KR and try again.\n\t */\n\tif (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||\n\t ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))\n\t\tgoto out;\n\n\t/* Turn SmartSpeed on to disable KR support */\n\thw->phy.smart_speed_active = true;\n\tstatus = ixgbe_setup_mac_link_82599(hw, speed, autoneg,\n\t\t\t\t\t autoneg_wait_to_complete);\n\tif (status != 0)\n\t\tgoto out;\n\n\t/*\n\t * Wait for the controller to acquire link. 600ms will allow for\n\t * the AN link_fail_inhibit_timer as well for multiple cycles of\n\t * parallel detect, both 10g and 1g. This allows for the maximum\n\t * connect attempts as defined in the AN MAS table 73-7.\n\t */\n\tfor (i = 0; i < 6; i++) {\n\t\tmsleep(100);\n\n\t\t/* If we have link, just jump out */\n\t\tstatus = ixgbe_check_link(hw, &link_speed, &link_up, false);\n\t\tif (status != 0)\n\t\t\tgoto out;\n\n\t\tif (link_up)\n\t\t\tgoto out;\n\t}\n\n\t/* We didn't get link. Turn SmartSpeed back off. */\n\thw->phy.smart_speed_active = false;\n\tstatus = ixgbe_setup_mac_link_82599(hw, speed, autoneg,\n\t\t\t\t\t autoneg_wait_to_complete);\n\nout:\n\tif (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))\n\t\thw_dbg(hw, \"Smartspeed has downgraded the link speed \"\n\t\t\"from the maximum advertised\\n\");\n\treturn status;\n}\n\n/**\n * ixgbe_setup_mac_link_82599 - Set MAC link speed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg: true if autonegotiation enabled\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n *\n * Set the link speed in the AUTOC register and restarts link.\n **/\ns32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,\n\t\t\t ixgbe_link_speed speed, bool autoneg,\n\t\t\t bool autoneg_wait_to_complete)\n{\n\ts32 status = 0;\n\tu32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tu32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);\n\tu32 start_autoc = autoc;\n\tu32 orig_autoc = 0;\n\tu32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;\n\tu32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;\n\tu32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;\n\tu32 links_reg = 0;\n\tu32 i;\n\tixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;\n\n\t/* Check to see if speed passed in is supported. */\n\tstatus = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);\n\tif (status != 0)\n\t\tgoto out;\n\n\tspeed &= link_capabilities;\n\n\tif (speed == IXGBE_LINK_SPEED_UNKNOWN) {\n\t\tstatus = IXGBE_ERR_LINK_SETUP;\n\t\tgoto out;\n\t}\n\n\t/* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/\n\tif (hw->mac.orig_link_settings_stored)\n\t\torig_autoc = hw->mac.orig_autoc;\n\telse\n\t\torig_autoc = autoc;\n\n\tif (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||\n\t link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||\n\t link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {\n\t\t/* Set KX4/KX/KR support according to speed requested */\n\t\tautoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);\n\t\tif (speed & IXGBE_LINK_SPEED_10GB_FULL)\n\t\t\tif (orig_autoc & IXGBE_AUTOC_KX4_SUPP)\n\t\t\t\tautoc |= IXGBE_AUTOC_KX4_SUPP;\n\t\t\tif ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&\n\t\t\t (hw->phy.smart_speed_active == false))\n\t\t\t\tautoc |= IXGBE_AUTOC_KR_SUPP;\n\t\tif (speed & IXGBE_LINK_SPEED_1GB_FULL)\n\t\t\tautoc |= IXGBE_AUTOC_KX_SUPP;\n\t} else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&\n\t\t (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||\n\t\t link_mode == IXGBE_AUTOC_LMS_1G_AN)) {\n\t\t/* Switch from 1G SFI to 10G SFI if requested */\n\t\tif ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&\n\t\t (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {\n\t\t\tautoc &= ~IXGBE_AUTOC_LMS_MASK;\n\t\t\tautoc |= IXGBE_AUTOC_LMS_10G_SERIAL;\n\t\t}\n\t} else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&\n\t\t (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {\n\t\t/* Switch from 10G SFI to 1G SFI if requested */\n\t\tif ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&\n\t\t (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {\n\t\t\tautoc &= ~IXGBE_AUTOC_LMS_MASK;\n\t\t\tif (autoneg)\n\t\t\t\tautoc |= IXGBE_AUTOC_LMS_1G_AN;\n\t\t\telse\n\t\t\t\tautoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;\n\t\t}\n\t}\n\n\tif (autoc != start_autoc) {\n\t\t/* Restart link */\n\t\tautoc |= IXGBE_AUTOC_AN_RESTART;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);\n\n\t\t/* Only poll for autoneg to complete if specified to do so */\n\t\tif (autoneg_wait_to_complete) {\n\t\t\tif (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||\n\t\t\t link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||\n\t\t\t link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {\n\t\t\t\tfor (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {\n\t\t\t\t\tlinks_reg =\n\t\t\t\t\t IXGBE_READ_REG(hw, IXGBE_LINKS);\n\t\t\t\t\tif (links_reg & IXGBE_LINKS_KX_AN_COMP)\n\t\t\t\t\t\tbreak;\n\t\t\t\t\tmsleep(100);\n\t\t\t\t}\n\t\t\t\tif (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {\n\t\t\t\t\tstatus =\n\t\t\t\t\t\tIXGBE_ERR_AUTONEG_NOT_COMPLETE;\n\t\t\t\t\thw_dbg(hw, \"Autoneg did not complete.\\n\");\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* Add delay to filter out noises during initial link setup */\n\t\tmsleep(50);\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg: true if autonegotiation enabled\n * @autoneg_wait_to_complete: true if waiting is needed to complete\n *\n * Restarts link on PHY and MAC based on settings passed in.\n **/\nstatic s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t\t bool autoneg,\n\t\t\t\t\t bool autoneg_wait_to_complete)\n{\n\ts32 status;\n\n\t/* Setup the PHY according to input speed */\n\tstatus = hw->phy.ops.setup_link_speed(hw, speed, autoneg,\n\t\t\t\t\t autoneg_wait_to_complete);\n\t/* Set up MAC */\n\tixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);\n\n\treturn status;\n}\n\n/**\n * ixgbe_reset_hw_82599 - Perform hardware reset\n * @hw: pointer to hardware structure\n *\n * Resets the hardware by resetting the transmit and receive units, masks\n * and clears all interrupts, perform a PHY reset, and perform a link (MAC)\n * reset.\n **/\ns32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)\n{\n//\tixgbe_link_speed link_speed;\n\ts32 status = 0;\n//\tu32 ctrl, i, autoc, autoc2;\n//\tbool link_up = false;\n\n#if 0\n\t/* Call adapter stop to disable tx/rx and clear interrupts */\n\tstatus = hw->mac.ops.stop_adapter(hw);\n\tif (status != 0)\n\t\tgoto reset_hw_out;\n\n\t/* flush pending Tx transactions */\n\tixgbe_clear_tx_pending(hw);\n\n\t/* PHY ops must be identified and initialized prior to reset */\n\n\t/* Identify PHY and related function pointers */\n\tstatus = hw->phy.ops.init(hw);\n\n\tif (status == IXGBE_ERR_SFP_NOT_SUPPORTED)\n\t\tgoto reset_hw_out;\n\n\t/* Setup SFP module if there is one present. */\n\tif (hw->phy.sfp_setup_needed) {\n\t\tstatus = hw->mac.ops.setup_sfp(hw);\n\t\thw->phy.sfp_setup_needed = false;\n\t}\n\n\tif (status == IXGBE_ERR_SFP_NOT_SUPPORTED)\n\t\tgoto reset_hw_out;\n\n\t/* Reset PHY */\n\tif (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)\n\t\thw->phy.ops.reset(hw);\n\nmac_reset_top:\n\t/*\n\t * Issue global reset to the MAC. Needs to be SW reset if link is up.\n\t * If link reset is used when link is up, it might reset the PHY when\n\t * mng is using it. If link is down or the flag to force full link\n\t * reset is set, then perform link reset.\n\t */\n\tctrl = IXGBE_CTRL_LNK_RST;\n\tif (!hw->force_full_reset) {\n\t\thw->mac.ops.check_link(hw, &link_speed, &link_up, false);\n\t\tif (link_up)\n\t\t\tctrl = IXGBE_CTRL_RST;\n\t}\n\n\tctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Poll for reset bit to self-clear indicating reset is complete */\n\tfor (i = 0; i < 10; i++) {\n\t\tudelay(1);\n\t\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);\n\t\tif (!(ctrl & IXGBE_CTRL_RST_MASK))\n\t\t\tbreak;\n\t}\n\n\tif (ctrl & IXGBE_CTRL_RST_MASK) {\n\t\tstatus = IXGBE_ERR_RESET_FAILED;\n\t\thw_dbg(hw, \"Reset polling failed to complete.\\n\");\n\t}\n\n\tmsleep(50);\n\n\t/*\n\t * Double resets are required for recovery from certain error\n\t * conditions. Between resets, it is necessary to stall to allow time\n\t * for any pending HW events to complete.\n\t */\n\tif (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {\n\t\thw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;\n\t\tgoto mac_reset_top;\n\t}\n\n\t/*\n\t * Store the original AUTOC/AUTOC2 values if they have not been\n\t * stored off yet. Otherwise restore the stored original\n\t * values since the reset operation sets back to defaults.\n\t */\n\tautoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tautoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);\n\tif (hw->mac.orig_link_settings_stored == false) {\n\t\thw->mac.orig_autoc = autoc;\n\t\thw->mac.orig_autoc2 = autoc2;\n\t\thw->mac.orig_link_settings_stored = true;\n\t} else {\n\t\tif (autoc != hw->mac.orig_autoc)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |\n\t\t\t\t\tIXGBE_AUTOC_AN_RESTART));\n\n\t\tif ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=\n\t\t (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {\n\t\t\tautoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;\n\t\t\tautoc2 |= (hw->mac.orig_autoc2 &\n\t\t\t\t IXGBE_AUTOC2_UPPER_MASK);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);\n\t\t}\n\t}\n#endif\n\n\t/* Store the permanent mac address */\n\thw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);\n\n\t/*\n\t * Store MAC address from RAR0, clear receive address registers, and\n\t * clear the multicast table. Also reset num_rar_entries to 128,\n\t * since we modify this value when programming the SAN MAC address.\n\t */\n\thw->mac.num_rar_entries = 128;\n\thw->mac.ops.init_rx_addrs(hw);\n\n\t/* Store the permanent SAN mac address */\n\thw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);\n\n\t/* Add the SAN MAC address to the RAR only if it's a valid address */\n\tif (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {\n\t\thw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,\n\t\t\t\t hw->mac.san_addr, 0, IXGBE_RAH_AV);\n\n\t\t/* Save the SAN MAC RAR index */\n\t\thw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;\n\n\t\t/* Reserve the last RAR for the SAN MAC address */\n\t\thw->mac.num_rar_entries--;\n\t}\n\n\t/* Store the alternative WWNN/WWPN prefix */\n\thw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,\n\t\t\t\t &hw->mac.wwpn_prefix);\n\n//reset_hw_out:\n\treturn status;\n}\n\n/**\n * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)\n{\n\tint i;\n\tu32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);\n\tfdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;\n\n\t/*\n\t * Before starting reinitialization process,\n\t * FDIRCMD.CMD must be zero.\n\t */\n\tfor (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {\n\t\tif (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &\n\t\t IXGBE_FDIRCMD_CMD_MASK))\n\t\t\tbreak;\n\t\tudelay(10);\n\t}\n\tif (i >= IXGBE_FDIRCMD_CMD_POLL) {\n\t\thw_dbg(hw, \"Flow Director previous command isn't complete, \"\n\t\t\t \"aborting table re-initialization.\\n\");\n\t\treturn IXGBE_ERR_FDIR_REINIT_FAILED;\n\t}\n\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);\n\tIXGBE_WRITE_FLUSH(hw);\n\t/*\n\t * 82599 adapters flow director init flow cannot be restarted,\n\t * Workaround 82599 silicon errata by performing the following steps\n\t * before re-writing the FDIRCTRL control register with the same value.\n\t * - write 1 to bit 8 of FDIRCMD register &\n\t * - write 0 to bit 8 of FDIRCMD register\n\t */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,\n\t\t\t(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |\n\t\t\t IXGBE_FDIRCMD_CLEARHT));\n\tIXGBE_WRITE_FLUSH(hw);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,\n\t\t\t(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &\n\t\t\t ~IXGBE_FDIRCMD_CLEARHT));\n\tIXGBE_WRITE_FLUSH(hw);\n\t/*\n\t * Clear FDIR Hash register to clear any leftover hashes\n\t * waiting to be programmed.\n\t */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Poll init-done after we write FDIRCTRL register */\n\tfor (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {\n\t\tif (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &\n\t\t\t\t IXGBE_FDIRCTRL_INIT_DONE)\n\t\t\tbreak;\n\t\tudelay(10);\n\t}\n\tif (i >= IXGBE_FDIR_INIT_DONE_POLL) {\n\t\thw_dbg(hw, \"Flow Director Signature poll time exceeded!\\n\");\n\t\treturn IXGBE_ERR_FDIR_REINIT_FAILED;\n\t}\n\n\t/* Clear FDIR statistics registers (read to clear) */\n\tIXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);\n\tIXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);\n\tIXGBE_READ_REG(hw, IXGBE_FDIRMATCH);\n\tIXGBE_READ_REG(hw, IXGBE_FDIRMISS);\n\tIXGBE_READ_REG(hw, IXGBE_FDIRLEN);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers\n * @hw: pointer to hardware structure\n * @fdirctrl: value to write to flow director control register\n **/\nstatic void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)\n{\n\tint i;\n\n\t/* Prime the keys for hashing */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);\n\n\t/*\n\t * Poll init-done after we write the register. Estimated times:\n\t * 10G: PBALLOC = 11b, timing is 60us\n\t * 1G: PBALLOC = 11b, timing is 600us\n\t * 100M: PBALLOC = 11b, timing is 6ms\n\t *\n\t * Multiple these timings by 4 if under full Rx load\n\t *\n\t * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for\n\t * 1 msec per poll time. If we're at line rate and drop to 100M, then\n\t * this might not finish in our poll time, but we can live with that\n\t * for now.\n\t */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);\n\tIXGBE_WRITE_FLUSH(hw);\n\tfor (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {\n\t\tif (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &\n\t\t\t\t IXGBE_FDIRCTRL_INIT_DONE)\n\t\t\tbreak;\n\t\tmsleep(1);\n\t}\n\n\tif (i >= IXGBE_FDIR_INIT_DONE_POLL)\n\t\thw_dbg(hw, \"Flow Director poll time exceeded!\\n\");\n}\n\n/**\n * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters\n * @hw: pointer to hardware structure\n * @fdirctrl: value to write to flow director control register, initially\n *\t contains just the value of the Rx packet buffer allocation\n **/\ns32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)\n{\n\t/*\n\t * Continue setup of fdirctrl register bits:\n\t * Move the flexible bytes to use the ethertype - shift 6 words\n\t * Set the maximum length per hash bucket to 0xA filters\n\t * Send interrupt when 64 filters are left\n\t */\n\tfdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |\n\t\t (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |\n\t\t (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);\n\n\t/* write hashes and fdirctrl register, poll for completion */\n\tixgbe_fdir_enable_82599(hw, fdirctrl);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters\n * @hw: pointer to hardware structure\n * @fdirctrl: value to write to flow director control register, initially\n *\t contains just the value of the Rx packet buffer allocation\n **/\ns32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)\n{\n\t/*\n\t * Continue setup of fdirctrl register bits:\n\t * Turn perfect match filtering on\n\t * Report hash in RSS field of Rx wb descriptor\n\t * Initialize the drop queue\n\t * Move the flexible bytes to use the ethertype - shift 6 words\n\t * Set the maximum length per hash bucket to 0xA filters\n\t * Send interrupt when 64 (0x4 * 16) filters are left\n\t */\n\tfdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |\n\t\t IXGBE_FDIRCTRL_REPORT_STATUS |\n\t\t (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |\n\t\t (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |\n\t\t (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |\n\t\t (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);\n\n\t/* write hashes and fdirctrl register, poll for completion */\n\tixgbe_fdir_enable_82599(hw, fdirctrl);\n\n\treturn 0;\n}\n\n/*\n * These defines allow us to quickly generate all of the necessary instructions\n * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION\n * for values 0 through 15\n */\n#define IXGBE_ATR_COMMON_HASH_KEY \\\n\t\t(IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)\n#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \\\ndo { \\\n\tu32 n = (_n); \\\n\tif (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \\\n\t\tcommon_hash ^= lo_hash_dword >> n; \\\n\telse if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \\\n\t\tbucket_hash ^= lo_hash_dword >> n; \\\n\telse if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \\\n\t\tsig_hash ^= lo_hash_dword << (16 - n); \\\n\tif (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \\\n\t\tcommon_hash ^= hi_hash_dword >> n; \\\n\telse if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \\\n\t\tbucket_hash ^= hi_hash_dword >> n; \\\n\telse if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \\\n\t\tsig_hash ^= hi_hash_dword << (16 - n); \\\n} while (0);\n\n/**\n * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash\n * @stream: input bitstream to compute the hash on\n *\n * This function is almost identical to the function above but contains\n * several optomizations such as unwinding all of the loops, letting the\n * compiler work out all of the conditional ifs since the keys are static\n * defines, and computing two keys at once since the hashed dword stream\n * will be the same for both keys.\n **/\nu32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,\n\t\t\t\t union ixgbe_atr_hash_dword common)\n{\n\tu32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;\n\tu32 sig_hash = 0, bucket_hash = 0, common_hash = 0;\n\n\t/* record the flow_vm_vlan bits as they are a key part to the hash */\n\tflow_vm_vlan = IXGBE_NTOHL(input.dword);\n\n\t/* generate common hash dword */\n\thi_hash_dword = IXGBE_NTOHL(common.dword);\n\n\t/* low dword is word swapped version of common */\n\tlo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);\n\n\t/* apply flow ID/VM pool/VLAN ID bits to hash words */\n\thi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);\n\n\t/* Process bits 0 and 16 */\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(0);\n\n\t/*\n\t * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to\n\t * delay this because bit 0 of the stream should not be processed\n\t * so we do not add the vlan until after bit 0 was processed\n\t */\n\tlo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);\n\n\t/* Process remaining 30 bit of the key */\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(1);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(2);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(3);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(4);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(5);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(6);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(7);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(8);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(9);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(10);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(11);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(12);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(13);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(14);\n\tIXGBE_COMPUTE_SIG_HASH_ITERATION(15);\n\n\t/* combine common_hash result with signature and bucket hashes */\n\tbucket_hash ^= common_hash;\n\tbucket_hash &= IXGBE_ATR_HASH_MASK;\n\n\tsig_hash ^= common_hash << 16;\n\tsig_hash &= IXGBE_ATR_HASH_MASK << 16;\n\n\t/* return completed signature hash */\n\treturn sig_hash ^ bucket_hash;\n}\n\n/**\n * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter\n * @hw: pointer to hardware structure\n * @input: unique input dword\n * @common: compressed common input dword\n * @queue: queue index to direct traffic to\n **/\ns32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t union ixgbe_atr_hash_dword input,\n\t\t\t\t\t union ixgbe_atr_hash_dword common,\n\t\t\t\t\t u8 queue)\n{\n\tu64 fdirhashcmd;\n\tu32 fdircmd;\n\n\t/*\n\t * Get the flow_type in order to program FDIRCMD properly\n\t * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6\n\t */\n\tswitch (input.formatted.flow_type) {\n\tcase IXGBE_ATR_FLOW_TYPE_TCPV4:\n\tcase IXGBE_ATR_FLOW_TYPE_UDPV4:\n\tcase IXGBE_ATR_FLOW_TYPE_SCTPV4:\n\tcase IXGBE_ATR_FLOW_TYPE_TCPV6:\n\tcase IXGBE_ATR_FLOW_TYPE_UDPV6:\n\tcase IXGBE_ATR_FLOW_TYPE_SCTPV6:\n\t\tbreak;\n\tdefault:\n\t\thw_dbg(hw, \" Error on flow type input\\n\");\n\t\treturn IXGBE_ERR_CONFIG;\n\t}\n\n\t/* configure FDIRCMD register */\n\tfdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |\n\t\t IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;\n\tfdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;\n\tfdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;\n\n\t/*\n\t * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits\n\t * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.\n\t */\n\tfdirhashcmd = (u64)fdircmd << 32;\n\tfdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);\n\tIXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);\n\n\thw_dbg(hw, \"Tx Queue=%x hash=%x\\n\", queue, (u32)fdirhashcmd);\n\n\treturn 0;\n}\n\n#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \\\ndo { \\\n\tu32 n = (_n); \\\n\tif (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \\\n\t\tbucket_hash ^= lo_hash_dword >> n; \\\n\tif (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \\\n\t\tbucket_hash ^= hi_hash_dword >> n; \\\n} while (0);\n\n/**\n * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash\n * @atr_input: input bitstream to compute the hash on\n * @input_mask: mask for the input bitstream\n *\n * This function serves two main purposes. First it applys the input_mask\n * to the atr_input resulting in a cleaned up atr_input data stream.\n * Secondly it computes the hash and stores it in the bkt_hash field at\n * the end of the input byte stream. This way it will be available for\n * future use without needing to recompute the hash.\n **/\nvoid ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,\n\t\t\t\t\t union ixgbe_atr_input *input_mask)\n{\n\n\tu32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;\n\tu32 bucket_hash = 0;\n\n\t/* Apply masks to input data */\n\tinput->dword_stream[0] &= input_mask->dword_stream[0];\n\tinput->dword_stream[1] &= input_mask->dword_stream[1];\n\tinput->dword_stream[2] &= input_mask->dword_stream[2];\n\tinput->dword_stream[3] &= input_mask->dword_stream[3];\n\tinput->dword_stream[4] &= input_mask->dword_stream[4];\n\tinput->dword_stream[5] &= input_mask->dword_stream[5];\n\tinput->dword_stream[6] &= input_mask->dword_stream[6];\n\tinput->dword_stream[7] &= input_mask->dword_stream[7];\n\tinput->dword_stream[8] &= input_mask->dword_stream[8];\n\tinput->dword_stream[9] &= input_mask->dword_stream[9];\n\tinput->dword_stream[10] &= input_mask->dword_stream[10];\n\n\t/* record the flow_vm_vlan bits as they are a key part to the hash */\n\tflow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);\n\n\t/* generate common hash dword */\n\thi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^\n\t\t\t\t input->dword_stream[2] ^\n\t\t\t\t input->dword_stream[3] ^\n\t\t\t\t input->dword_stream[4] ^\n\t\t\t\t input->dword_stream[5] ^\n\t\t\t\t input->dword_stream[6] ^\n\t\t\t\t input->dword_stream[7] ^\n\t\t\t\t input->dword_stream[8] ^\n\t\t\t\t input->dword_stream[9] ^\n\t\t\t\t input->dword_stream[10]);\n\n\t/* low dword is word swapped version of common */\n\tlo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);\n\n\t/* apply flow ID/VM pool/VLAN ID bits to hash words */\n\thi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);\n\n\t/* Process bits 0 and 16 */\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(0);\n\n\t/*\n\t * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to\n\t * delay this because bit 0 of the stream should not be processed\n\t * so we do not add the vlan until after bit 0 was processed\n\t */\n\tlo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);\n\n\t/* Process remaining 30 bit of the key */\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(1);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(2);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(3);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(4);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(5);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(6);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(7);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(8);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(9);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(10);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(11);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(12);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(13);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(14);\n\tIXGBE_COMPUTE_BKT_HASH_ITERATION(15);\n\n\t/*\n\t * Limit hash to 13 bits since max bucket count is 8K.\n\t * Store result at the end of the input stream.\n\t */\n\tinput->formatted.bkt_hash = bucket_hash & 0x1FFF;\n}\n\n/**\n * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks\n * @input_mask: mask to be bit swapped\n *\n * The source and destination port masks for flow director are bit swapped\n * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to\n * generate a correctly swapped value we need to bit swap the mask and that\n * is what is accomplished by this function.\n **/\nstatic u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)\n{\n\tu32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);\n\tmask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;\n\tmask |= IXGBE_NTOHS(input_mask->formatted.src_port);\n\tmask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);\n\tmask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);\n\tmask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);\n\treturn ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);\n}\n\n/*\n * These two macros are meant to address the fact that we have registers\n * that are either all or in part big-endian. As a result on big-endian\n * systems we will end up byte swapping the value to little-endian before\n * it is byte swapped again and written to the hardware in the original\n * big-endian format.\n */\n#define IXGBE_STORE_AS_BE32(_value) \\\n\t(((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \\\n\t (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))\n\n#define IXGBE_WRITE_REG_BE32(a, reg, value) \\\n\tIXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))\n\n#define IXGBE_STORE_AS_BE16(_value) \\\n\tIXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))\n\ns32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,\n\t\t\t\t union ixgbe_atr_input *input_mask)\n{\n\t/* mask IPv6 since it is currently not supported */\n\tu32 fdirm = IXGBE_FDIRM_DIPv6;\n\tu32 fdirtcpm;\n\n\t/*\n\t * Program the relevant mask registers. If src/dst_port or src/dst_addr\n\t * are zero, then assume a full mask for that field. Also assume that\n\t * a VLAN of 0 is unspecified, so mask that out as well. L4type\n\t * cannot be masked out in this implementation.\n\t *\n\t * This also assumes IPv4 only. IPv6 masking isn't supported at this\n\t * point in time.\n\t */\n\n\t/* verify bucket hash is cleared on hash generation */\n\tif (input_mask->formatted.bkt_hash)\n\t\thw_dbg(hw, \" bucket hash should always be 0 in mask\\n\");\n\n\t/* Program FDIRM and verify partial masks */\n\tswitch (input_mask->formatted.vm_pool & 0x7F) {\n\tcase 0x0:\n\t\tfdirm |= IXGBE_FDIRM_POOL;\n\tcase 0x7F:\n\t\tbreak;\n\tdefault:\n\t\thw_dbg(hw, \" Error on vm pool mask\\n\");\n\t\treturn IXGBE_ERR_CONFIG;\n\t}\n\n\tswitch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {\n\tcase 0x0:\n\t\tfdirm |= IXGBE_FDIRM_L4P;\n\t\tif (input_mask->formatted.dst_port ||\n\t\t input_mask->formatted.src_port) {\n\t\t\thw_dbg(hw, \" Error on src/dst port mask\\n\");\n\t\t\treturn IXGBE_ERR_CONFIG;\n\t\t}\n\tcase IXGBE_ATR_L4TYPE_MASK:\n\t\tbreak;\n\tdefault:\n\t\thw_dbg(hw, \" Error on flow type mask\\n\");\n\t\treturn IXGBE_ERR_CONFIG;\n\t}\n\n\tswitch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {\n\tcase 0x0000:\n\t\t/* mask VLAN ID, fall through to mask VLAN priority */\n\t\tfdirm |= IXGBE_FDIRM_VLANID;\n\tcase 0x0FFF:\n\t\t/* mask VLAN priority */\n\t\tfdirm |= IXGBE_FDIRM_VLANP;\n\t\tbreak;\n\tcase 0xE000:\n\t\t/* mask VLAN ID only, fall through */\n\t\tfdirm |= IXGBE_FDIRM_VLANID;\n\tcase 0xEFFF:\n\t\t/* no VLAN fields masked */\n\t\tbreak;\n\tdefault:\n\t\thw_dbg(hw, \" Error on VLAN mask\\n\");\n\t\treturn IXGBE_ERR_CONFIG;\n\t}\n\n\tswitch (input_mask->formatted.flex_bytes & 0xFFFF) {\n\tcase 0x0000:\n\t\t/* Mask Flex Bytes, fall through */\n\t\tfdirm |= IXGBE_FDIRM_FLEX;\n\tcase 0xFFFF:\n\t\tbreak;\n\tdefault:\n\t\thw_dbg(hw, \" Error on flexible byte mask\\n\");\n\t\treturn IXGBE_ERR_CONFIG;\n\t}\n\n\t/* Now mask VM pool and destination IPv6 - bits 5 and 2 */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);\n\n\t/* store the TCP/UDP port masks, bit reversed from port layout */\n\tfdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);\n\n\t/* write both the same so that UDP and TCP use the same mask */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);\n\n\t/* store source and destination IP masks (big-enian) */\n\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,\n\t\t\t ~input_mask->formatted.src_ip[0]);\n\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,\n\t\t\t ~input_mask->formatted.dst_ip[0]);\n\n\treturn 0;\n}\n\ns32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t union ixgbe_atr_input *input,\n\t\t\t\t\t u16 soft_id, u8 queue)\n{\n\tu32 fdirport, fdirvlan, fdirhash, fdircmd;\n\n\t/* currently IPv6 is not supported, must be programmed with 0 */\n\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),\n\t\t\t input->formatted.src_ip[0]);\n\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),\n\t\t\t input->formatted.src_ip[1]);\n\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),\n\t\t\t input->formatted.src_ip[2]);\n\n\t/* record the source address (big-endian) */\n\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);\n\n\t/* record the first 32 bits of the destination address (big-endian) */\n\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);\n\n\t/* record source and destination port (little-endian)*/\n\tfdirport = IXGBE_NTOHS(input->formatted.dst_port);\n\tfdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;\n\tfdirport |= IXGBE_NTOHS(input->formatted.src_port);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);\n\n\t/* record vlan (little-endian) and flex_bytes(big-endian) */\n\tfdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);\n\tfdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;\n\tfdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);\n\n\t/* configure FDIRHASH register */\n\tfdirhash = input->formatted.bkt_hash;\n\tfdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);\n\n\t/*\n\t * flush all previous writes to make certain registers are\n\t * programmed prior to issuing the command\n\t */\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* configure FDIRCMD register */\n\tfdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |\n\t\t IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;\n\tif (queue == IXGBE_FDIR_DROP_QUEUE)\n\t\tfdircmd |= IXGBE_FDIRCMD_DROP;\n\tfdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;\n\tfdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;\n\tfdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);\n\n\treturn 0;\n}\n\ns32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t union ixgbe_atr_input *input,\n\t\t\t\t\t u16 soft_id)\n{\n\tu32 fdirhash;\n\tu32 fdircmd = 0;\n\tu32 retry_count;\n\ts32 err = 0;\n\n\t/* configure FDIRHASH register */\n\tfdirhash = input->formatted.bkt_hash;\n\tfdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);\n\n\t/* flush hash to HW */\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Query if filter is present */\n\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);\n\n\tfor (retry_count = 10; retry_count; retry_count--) {\n\t\t/* allow 10us for query to process */\n\t\tudelay(10);\n\t\t/* verify query completed successfully */\n\t\tfdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);\n\t\tif (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))\n\t\t\tbreak;\n\t}\n\n\tif (!retry_count)\n\t\terr = IXGBE_ERR_FDIR_REINIT_FAILED;\n\n\t/* if filter exists in hardware then remove it */\n\tif (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,\n\t\t\t\tIXGBE_FDIRCMD_CMD_REMOVE_FLOW);\n\t}\n\n\treturn err;\n}\n\n/**\n * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter\n * @hw: pointer to hardware structure\n * @input: input bitstream\n * @input_mask: mask for the input bitstream\n * @soft_id: software index for the filters\n * @queue: queue index to direct traffic to\n *\n * Note that the caller to this function must lock before calling, since the\n * hardware writes must be protected from one another.\n **/\ns32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\tunion ixgbe_atr_input *input,\n\t\t\t\t\tunion ixgbe_atr_input *input_mask,\n\t\t\t\t\tu16 soft_id, u8 queue)\n{\n\ts32 err = IXGBE_ERR_CONFIG;\n\n\t/*\n\t * Check flow_type formatting, and bail out before we touch the hardware\n\t * if there's a configuration issue\n\t */\n\tswitch (input->formatted.flow_type) {\n\tcase IXGBE_ATR_FLOW_TYPE_IPV4:\n\t\tinput_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;\n\t\tif (input->formatted.dst_port || input->formatted.src_port) {\n\t\t\thw_dbg(hw, \" Error on src/dst port\\n\");\n\t\t\treturn IXGBE_ERR_CONFIG;\n\t\t}\n\t\tbreak;\n\tcase IXGBE_ATR_FLOW_TYPE_SCTPV4:\n\t\tif (input->formatted.dst_port || input->formatted.src_port) {\n\t\t\thw_dbg(hw, \" Error on src/dst port\\n\");\n\t\t\treturn IXGBE_ERR_CONFIG;\n\t\t}\n\tcase IXGBE_ATR_FLOW_TYPE_TCPV4:\n\tcase IXGBE_ATR_FLOW_TYPE_UDPV4:\n\t\tinput_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |\n\t\t\t\t\t\t IXGBE_ATR_L4TYPE_MASK;\n\t\tbreak;\n\tdefault:\n\t\thw_dbg(hw, \" Error on flow type input\\n\");\n\t\treturn err;\n\t}\n\n\t/* program input mask into the HW */\n\terr = ixgbe_fdir_set_input_mask_82599(hw, input_mask);\n\tif (err)\n\t\treturn err;\n\n\t/* apply mask and compute/store hash */\n\tixgbe_atr_compute_perfect_hash_82599(input, input_mask);\n\n\t/* program filters to filter memory */\n\treturn ixgbe_fdir_write_perfect_filter_82599(hw, input,\n\t\t\t\t\t\t soft_id, queue);\n}\n\n/**\n * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register\n * @hw: pointer to hardware structure\n * @reg: analog register to read\n * @val: read value\n *\n * Performs read operation to Omer analog register specified.\n **/\ns32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)\n{\n\tu32 core_ctl;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |\n\t\t\t(reg << 8));\n\tIXGBE_WRITE_FLUSH(hw);\n\tudelay(10);\n\tcore_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);\n\t*val = (u8)core_ctl;\n\n\treturn 0;\n}\n\n/**\n * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register\n * @hw: pointer to hardware structure\n * @reg: atlas register to write\n * @val: value to write\n *\n * Performs write operation to Omer analog register specified.\n **/\ns32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)\n{\n\tu32 core_ctl;\n\n\tcore_ctl = (reg << 8) | val;\n\tIXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);\n\tIXGBE_WRITE_FLUSH(hw);\n\tudelay(10);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx\n * @hw: pointer to hardware structure\n *\n * Starts the hardware using the generic start_hw function\n * and the generation start_hw function.\n * Then performs revision-specific operations, if any.\n **/\ns32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = 0;\n\n\tret_val = ixgbe_start_hw_generic(hw);\n\tif (ret_val != 0)\n\t\tgoto out;\n\n\tret_val = ixgbe_start_hw_gen2(hw);\n\tif (ret_val != 0)\n\t\tgoto out;\n\n\t/* We need to run link autotry after the driver loads */\n\thw->mac.autotry_restart = true;\n\n\tif (ret_val == 0)\n\t\tret_val = ixgbe_verify_fw_version_82599(hw);\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_identify_phy_82599 - Get physical layer module\n * @hw: pointer to hardware structure\n *\n * Determines the physical layer module found on the current adapter.\n * If PHY already detected, maintains current PHY type in hw struct,\n * otherwise executes the PHY detection routine.\n **/\ns32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_PHY_ADDR_INVALID;\n\n\t/* Detect PHY if not unknown - returns success if already detected. */\n\tstatus = ixgbe_identify_phy_generic(hw);\n\tif (status != 0) {\n\t\t/* 82599 10GBASE-T requires an external PHY */\n\t\tif (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)\n\t\t\tgoto out;\n\t\telse\n\t\t\tstatus = ixgbe_identify_module_generic(hw);\n\t}\n\n\t/* Set PHY type none if no PHY detected */\n\tif (hw->phy.type == ixgbe_phy_unknown) {\n\t\thw->phy.type = ixgbe_phy_none;\n\t\tstatus = 0;\n\t}\n\n\t/* Return error if SFP module has been detected but is not supported */\n\tif (hw->phy.type == ixgbe_phy_sfp_unsupported)\n\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type\n * @hw: pointer to hardware structure\n *\n * Determines physical layer capabilities of the current configuration.\n **/\nu32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)\n{\n\tu32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n\tu32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tu32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);\n\tu32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;\n\tu32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;\n\tu32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;\n\tu16 ext_ability = 0;\n\tu8 comp_codes_10g = 0;\n\tu8 comp_codes_1g = 0;\n\n\thw->phy.ops.identify(hw);\n\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_tn:\n\tcase ixgbe_phy_cu_unknown:\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,\n\t\tIXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);\n\t\tif (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;\n\t\tif (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;\n\t\tif (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;\n\t\tgoto out;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tswitch (autoc & IXGBE_AUTOC_LMS_MASK) {\n\tcase IXGBE_AUTOC_LMS_1G_AN:\n\tcase IXGBE_AUTOC_LMS_1G_LINK_NO_AN:\n\t\tif (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |\n\t\t\t IXGBE_PHYSICAL_LAYER_1000BASE_BX;\n\t\t\tgoto out;\n\t\t} else\n\t\t\t/* SFI mode so read SFP module */\n\t\t\tgoto sfp_check;\n\t\tbreak;\n\tcase IXGBE_AUTOC_LMS_10G_LINK_NO_AN:\n\t\tif (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;\n\t\telse if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;\n\t\telse if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;\n\t\tgoto out;\n\t\tbreak;\n\tcase IXGBE_AUTOC_LMS_10G_SERIAL:\n\t\tif (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;\n\t\t\tgoto out;\n\t\t} else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)\n\t\t\tgoto sfp_check;\n\t\tbreak;\n\tcase IXGBE_AUTOC_LMS_KX4_KX_KR:\n\tcase IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:\n\t\tif (autoc & IXGBE_AUTOC_KX_SUPP)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;\n\t\tif (autoc & IXGBE_AUTOC_KX4_SUPP)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;\n\t\tif (autoc & IXGBE_AUTOC_KR_SUPP)\n\t\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;\n\t\tgoto out;\n\t\tbreak;\n\tdefault:\n\t\tgoto out;\n\t\tbreak;\n\t}\n\nsfp_check:\n\t/* SFP check must be done last since DA modules are sometimes used to\n\t * test KR mode - we need to id KR mode correctly before SFP module.\n\t * Call identify_sfp because the pluggable module may have changed */\n\thw->phy.ops.identify_sfp(hw);\n\tif (hw->phy.sfp_type == ixgbe_sfp_type_not_present)\n\t\tgoto out;\n\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_sfp_passive_tyco:\n\tcase ixgbe_phy_sfp_passive_unknown:\n\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;\n\t\tbreak;\n\tcase ixgbe_phy_sfp_ftl_active:\n\tcase ixgbe_phy_sfp_active_unknown:\n\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;\n\t\tbreak;\n\tcase ixgbe_phy_sfp_avago:\n\tcase ixgbe_phy_sfp_ftl:\n\tcase ixgbe_phy_sfp_intel:\n\tcase ixgbe_phy_sfp_unknown:\n\t\thw->phy.ops.read_i2c_eeprom(hw,\n\t\t IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);\n\t\thw->phy.ops.read_i2c_eeprom(hw,\n\t\t IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);\n\t\tif (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;\n\t\telse if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;\n\t\telse if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;\n\t\telse if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)\n\t\t\tphysical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\nout:\n\treturn physical_layer;\n}\n\n/**\n * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599\n * @hw: pointer to hardware structure\n * @regval: register value to write to RXCTRL\n *\n * Enables the Rx DMA unit for 82599\n **/\ns32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)\n{\n\n\t/*\n\t * Workaround for 82599 silicon errata when enabling the Rx datapath.\n\t * If traffic is incoming before we enable the Rx unit, it could hang\n\t * the Rx DMA unit. Therefore, make sure the security engine is\n\t * completely disabled prior to enabling the Rx unit.\n\t */\n\n\thw->mac.ops.disable_sec_rx_path(hw);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);\n\n\thw->mac.ops.enable_sec_rx_path(hw);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_verify_fw_version_82599 - verify fw version for 82599\n * @hw: pointer to hardware structure\n *\n * Verifies that installed the firmware version is 0.6 or higher\n * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.\n *\n * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or\n * if the FW version is not supported.\n **/\nstatic s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_EEPROM_VERSION;\n\tu16 fw_offset, fw_ptp_cfg_offset;\n\tu16 fw_version = 0;\n\n\t/* firmware check is only necessary for SFI devices */\n\tif (hw->phy.media_type != ixgbe_media_type_fiber) {\n\t\tstatus = 0;\n\t\tgoto fw_version_out;\n\t}\n\n\t/* get the offset to the Firmware Module block */\n\thw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);\n\n\tif ((fw_offset == 0) || (fw_offset == 0xFFFF))\n\t\tgoto fw_version_out;\n\n\t/* get the offset to the Pass Through Patch Configuration block */\n\thw->eeprom.ops.read(hw, (fw_offset +\n\t\t\t\t IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),\n\t\t\t\t &fw_ptp_cfg_offset);\n\n\tif ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))\n\t\tgoto fw_version_out;\n\n\t/* get the firmware version */\n\thw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +\n\t\t\t IXGBE_FW_PATCH_VERSION_4), &fw_version);\n\n\tif (fw_version > 0x5)\n\t\tstatus = 0;\n\nfw_version_out:\n\treturn status;\n}\n\n/**\n * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.\n * @hw: pointer to hardware structure\n *\n * Returns true if the LESM FW module is present and enabled. Otherwise\n * returns false. Smart Speed must be disabled if LESM FW module is enabled.\n **/\nbool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)\n{\n\tbool lesm_enabled = false;\n\tu16 fw_offset, fw_lesm_param_offset, fw_lesm_state;\n\ts32 status;\n\n\t/* get the offset to the Firmware Module block */\n\tstatus = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);\n\n\tif ((status != 0) ||\n\t (fw_offset == 0) || (fw_offset == 0xFFFF))\n\t\tgoto out;\n\n\t/* get the offset to the LESM Parameters block */\n\tstatus = hw->eeprom.ops.read(hw, (fw_offset +\n\t\t\t\t IXGBE_FW_LESM_PARAMETERS_PTR),\n\t\t\t\t &fw_lesm_param_offset);\n\n\tif ((status != 0) ||\n\t (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))\n\t\tgoto out;\n\n\t/* get the lesm state word */\n\tstatus = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +\n\t\t\t\t IXGBE_FW_LESM_STATE_1),\n\t\t\t\t &fw_lesm_state);\n\n\tif ((status == 0) &&\n\t (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))\n\t\tlesm_enabled = true;\n\nout:\n\treturn lesm_enabled;\n}\n\n/**\n * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using\n * fastest available method\n *\n * @hw: pointer to hardware structure\n * @offset: offset of word in EEPROM to read\n * @words: number of words\n * @data: word(s) read from the EEPROM\n *\n * Retrieves 16 bit word(s) read from EEPROM\n **/\nstatic s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data)\n{\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\ts32 ret_val = IXGBE_ERR_CONFIG;\n\n\t/*\n\t * If EEPROM is detected and can be addressed using 14 bits,\n\t * use EERD otherwise use bit bang\n\t */\n\tif ((eeprom->type == ixgbe_eeprom_spi) &&\n\t (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))\n\t\tret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,\n\t\t\t\t\t\t\t data);\n\telse\n\t\tret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,\n\t\t\t\t\t\t\t\t words,\n\t\t\t\t\t\t\t\t data);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_read_eeprom_82599 - Read EEPROM word using\n * fastest available method\n *\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM\n **/\nstatic s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,\n\t\t\t\t u16 offset, u16 *data)\n{\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\ts32 ret_val = IXGBE_ERR_CONFIG;\n\n\t/*\n\t * If EEPROM is detected and can be addressed using 14 bits,\n\t * use EERD otherwise use bit bang\n\t */\n\tif ((eeprom->type == ixgbe_eeprom_spi) &&\n\t (offset <= IXGBE_EERD_MAX_ADDR))\n\t\tret_val = ixgbe_read_eerd_generic(hw, offset, data);\n\telse\n\t\tret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to read\n * @data: value read\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface at\n * a specified device address.\n **/\nstatic s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\tu8 dev_addr, u8 *data)\n{\n\tu32 esdp;\n\ts32 status;\n\ts32 timeout = 200;\n\n\tif (hw->phy.qsfp_shared_i2c_bus == TRUE) {\n\t\t/* Acquire I2C bus ownership. */\n\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\tesdp |= IXGBE_ESDP_SDP0;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\n\t\twhile (timeout) {\n\t\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\t\tif (esdp & IXGBE_ESDP_SDP1)\n\t\t\t\tbreak;\n\n\t\t\tmsleep(5);\n\t\t\ttimeout--;\n\t\t}\n\n\t\tif (!timeout) {\n\t\t\thw_dbg(hw, \"Driver can't access resource,\"\n\t\t\t\t \" acquiring I2C bus timeout.\\n\");\n\t\t\tstatus = IXGBE_ERR_I2C;\n\t\t\tgoto release_i2c_access;\n\t\t}\n\t}\n\n\tstatus = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);\n\nrelease_i2c_access:\n\n\tif (hw->phy.qsfp_shared_i2c_bus == TRUE) {\n\t\t/* Release I2C bus ownership. */\n\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\tesdp &= ~IXGBE_ESDP_SDP0;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @data: value to write\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface at\n * a specified device address.\n **/\nstatic s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data)\n{\n\tu32 esdp;\n\ts32 status;\n\ts32 timeout = 200;\n\n\tif (hw->phy.qsfp_shared_i2c_bus == TRUE) {\n\t\t/* Acquire I2C bus ownership. */\n\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\tesdp |= IXGBE_ESDP_SDP0;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\n\t\twhile (timeout) {\n\t\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\t\tif (esdp & IXGBE_ESDP_SDP1)\n\t\t\t\tbreak;\n\n\t\t\tmsleep(5);\n\t\t\ttimeout--;\n\t\t}\n\n\t\tif (!timeout) {\n\t\t\thw_dbg(hw, \"Driver can't access resource,\"\n\t\t\t\t \" acquiring I2C bus timeout.\\n\");\n\t\t\tstatus = IXGBE_ERR_I2C;\n\t\t\tgoto release_i2c_access;\n\t\t}\n\t}\n\n\tstatus = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);\n\nrelease_i2c_access:\n\n\tif (hw->phy.qsfp_shared_i2c_bus == TRUE) {\n\t\t/* Release I2C bus ownership. */\n\t\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\t\tesdp &= ~IXGBE_ESDP_SDP0;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t}\n\n\treturn status;\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_82599.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _IXGBE_82599_H_\n#define _IXGBE_82599_H_\n\ns32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed, bool *autoneg);\nenum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);\nvoid ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);\nvoid ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);\nvoid ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);\ns32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed speed, bool autoneg,\n\t\t\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed, bool autoneg,\n\t\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,\n\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t\t bool autoneg, bool autoneg_wait_to_complete);\ns32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw);\nvoid ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw);\ns32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);\ns32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);\ns32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);\ns32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);\ns32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);\ns32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);\nu32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);\ns32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);\nbool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);\n#endif /* _IXGBE_82599_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_api.c", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"ixgbe_api.h\"\n#include \"ixgbe_common.h\"\n\n/**\n * ixgbe_init_shared_code - Initialize the shared code\n * @hw: pointer to hardware structure\n *\n * This will assign function pointers and assign the MAC type and PHY code.\n * Does not touch the hardware. This function must be called prior to any\n * other function in the shared code. The ixgbe_hw structure should be\n * memset to 0 prior to calling this function. The following fields in\n * hw structure should be filled in prior to calling this function:\n * hw_addr, back, device_id, vendor_id, subsystem_device_id,\n * subsystem_vendor_id, and revision_id\n **/\ns32 ixgbe_init_shared_code(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\n\t/*\n\t * Set the mac type\n\t */\n\tixgbe_set_mac_type(hw);\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tstatus = ixgbe_init_ops_82598(hw);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\t\tstatus = ixgbe_init_ops_82599(hw);\n\t\tbreak;\n\tcase ixgbe_mac_X540:\n\t\tstatus = ixgbe_init_ops_X540(hw);\n\t\tbreak;\n\tdefault:\n\t\tstatus = IXGBE_ERR_DEVICE_NOT_SUPPORTED;\n\t\tbreak;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_set_mac_type - Sets MAC type\n * @hw: pointer to the HW structure\n *\n * This function sets the mac type of the adapter based on the\n * vendor ID and device ID stored in the hw structure.\n **/\ns32 ixgbe_set_mac_type(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = 0;\n\n\tif (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {\n\t\tswitch (hw->device_id) {\n\t\tcase IXGBE_DEV_ID_82598:\n\t\tcase IXGBE_DEV_ID_82598_BX:\n\t\tcase IXGBE_DEV_ID_82598AF_SINGLE_PORT:\n\t\tcase IXGBE_DEV_ID_82598AF_DUAL_PORT:\n\t\tcase IXGBE_DEV_ID_82598AT:\n\t\tcase IXGBE_DEV_ID_82598AT2:\n\t\tcase IXGBE_DEV_ID_82598EB_CX4:\n\t\tcase IXGBE_DEV_ID_82598_CX4_DUAL_PORT:\n\t\tcase IXGBE_DEV_ID_82598_DA_DUAL_PORT:\n\t\tcase IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:\n\t\tcase IXGBE_DEV_ID_82598EB_XF_LR:\n\t\tcase IXGBE_DEV_ID_82598EB_SFP_LOM:\n\t\t\thw->mac.type = ixgbe_mac_82598EB;\n\t\t\tbreak;\n\t\tcase IXGBE_DEV_ID_82599_KX4:\n\t\tcase IXGBE_DEV_ID_82599_KX4_MEZZ:\n\t\tcase IXGBE_DEV_ID_82599_XAUI_LOM:\n\t\tcase IXGBE_DEV_ID_82599_COMBO_BACKPLANE:\n\t\tcase IXGBE_DEV_ID_82599_KR:\n\t\tcase IXGBE_DEV_ID_82599_SFP:\n\t\tcase IXGBE_DEV_ID_82599_BACKPLANE_FCOE:\n\t\tcase IXGBE_DEV_ID_82599_SFP_FCOE:\n\t\tcase IXGBE_DEV_ID_82599_SFP_EM:\n\t\tcase IXGBE_DEV_ID_82599_SFP_SF2:\n\t\tcase IXGBE_DEV_ID_82599_QSFP_SF_QP:\n\t\tcase IXGBE_DEV_ID_82599EN_SFP:\n\t\tcase IXGBE_DEV_ID_82599_CX4:\n\t\tcase IXGBE_DEV_ID_82599_LS:\n\t\tcase IXGBE_DEV_ID_82599_T3_LOM:\n\t\t\thw->mac.type = ixgbe_mac_82599EB;\n\t\t\tbreak;\n\t\tcase IXGBE_DEV_ID_X540T:\n\t\t\thw->mac.type = ixgbe_mac_X540;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;\n\t\t\tbreak;\n\t\t}\n\t} else {\n\t\tret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;\n\t}\n\n\thw_dbg(hw, \"ixgbe_set_mac_type found mac: %d, returns: %d\\n\",\n\t\t hw->mac.type, ret_val);\n\treturn ret_val;\n}\n\n/**\n * ixgbe_init_hw - Initialize the hardware\n * @hw: pointer to hardware structure\n *\n * Initialize the hardware by resetting and then starting the hardware\n **/\ns32 ixgbe_init_hw(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_reset_hw - Performs a hardware reset\n * @hw: pointer to hardware structure\n *\n * Resets the hardware by resetting the transmit and receive units, masks and\n * clears all interrupts, performs a PHY reset, and performs a MAC reset\n **/\ns32 ixgbe_reset_hw(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_start_hw - Prepares hardware for Rx/Tx\n * @hw: pointer to hardware structure\n *\n * Starts the hardware by filling the bus info structure and media type,\n * clears all on chip counters, initializes receive address registers,\n * multicast table, VLAN filter table, calls routine to setup link and\n * flow control settings, and leaves transmit and receive units disabled\n * and uninitialized.\n **/\ns32 ixgbe_start_hw(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_clear_hw_cntrs - Clear hardware counters\n * @hw: pointer to hardware structure\n *\n * Clears all hardware statistics counters by reading them from the hardware\n * Statistics counters are clear on read.\n **/\ns32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_media_type - Get media type\n * @hw: pointer to hardware structure\n *\n * Returns the media type (fiber, copper, backplane)\n **/\nenum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),\n\t\t\t ixgbe_media_type_unknown);\n}\n\n/**\n * ixgbe_get_mac_addr - Get MAC address\n * @hw: pointer to hardware structure\n * @mac_addr: Adapter MAC address\n *\n * Reads the adapter's MAC address from the first Receive Address Register\n * (RAR0) A reset of the adapter must have been performed prior to calling\n * this function in order for the MAC address to have been loaded from the\n * EEPROM into RAR0\n **/\ns32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,\n\t\t\t (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_san_mac_addr - Get SAN MAC address\n * @hw: pointer to hardware structure\n * @san_mac_addr: SAN MAC address\n *\n * Reads the SAN MAC address from the EEPROM, if it's available. This is\n * per-port, so set_lan_id() must be called before reading the addresses.\n **/\ns32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr,\n\t\t\t (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_san_mac_addr - Write a SAN MAC address\n * @hw: pointer to hardware structure\n * @san_mac_addr: SAN MAC address\n *\n * Writes A SAN MAC address to the EEPROM.\n **/\ns32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr,\n\t\t\t (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_device_caps - Get additional device capabilities\n * @hw: pointer to hardware structure\n * @device_caps: the EEPROM word for device capabilities\n *\n * Reads the extra device capabilities from the EEPROM\n **/\ns32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_device_caps,\n\t\t\t (hw, device_caps), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM\n * @hw: pointer to hardware structure\n * @wwnn_prefix: the alternative WWNN prefix\n * @wwpn_prefix: the alternative WWPN prefix\n *\n * This function will read the EEPROM from the alternative SAN MAC address\n * block to check the support for the alternative WWNN/WWPN prefix support.\n **/\ns32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n\t\t\t u16 *wwpn_prefix)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,\n\t\t\t (hw, wwnn_prefix, wwpn_prefix),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM\n * @hw: pointer to hardware structure\n * @bs: the fcoe boot status\n *\n * This function will read the FCOE boot status from the iSCSI FCOE block\n **/\ns32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status,\n\t\t\t (hw, bs),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_bus_info - Set PCI bus info\n * @hw: pointer to hardware structure\n *\n * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure\n **/\ns32 ixgbe_get_bus_info(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_num_of_tx_queues - Get Tx queues\n * @hw: pointer to hardware structure\n *\n * Returns the number of transmit queues for the given adapter.\n **/\nu32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)\n{\n\treturn hw->mac.max_tx_queues;\n}\n\n/**\n * ixgbe_get_num_of_rx_queues - Get Rx queues\n * @hw: pointer to hardware structure\n *\n * Returns the number of receive queues for the given adapter.\n **/\nu32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)\n{\n\treturn hw->mac.max_rx_queues;\n}\n\n/**\n * ixgbe_stop_adapter - Disable Rx/Tx units\n * @hw: pointer to hardware structure\n *\n * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,\n * disables transmit and receive units. The adapter_stopped flag is used by\n * the shared code and drivers to determine if the adapter is in a stopped\n * state and should not touch the hardware.\n **/\ns32 ixgbe_stop_adapter(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_pba_string - Reads part number string from EEPROM\n * @hw: pointer to hardware structure\n * @pba_num: stores the part number string from the EEPROM\n * @pba_num_size: part number string buffer length\n *\n * Reads the part number string from the EEPROM.\n **/\ns32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)\n{\n\treturn ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);\n}\n\n/**\n * ixgbe_identify_phy - Get PHY type\n * @hw: pointer to hardware structure\n *\n * Determines the physical layer module found on the current adapter.\n **/\ns32 ixgbe_identify_phy(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\n\tif (hw->phy.type == ixgbe_phy_unknown) {\n\t\tstatus = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),\n\t\t\t\t\t IXGBE_NOT_IMPLEMENTED);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_reset_phy - Perform a PHY reset\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_reset_phy(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\n\tif (hw->phy.type == ixgbe_phy_unknown) {\n\t\tif (ixgbe_identify_phy(hw) != 0)\n\t\t\tstatus = IXGBE_ERR_PHY;\n\t}\n\n\tif (status == 0) {\n\t\tstatus = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),\n\t\t\t\t\t IXGBE_NOT_IMPLEMENTED);\n\t}\n\treturn status;\n}\n\n/**\n * ixgbe_get_phy_firmware_version -\n * @hw: pointer to hardware structure\n * @firmware_version: pointer to firmware version\n **/\ns32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)\n{\n\ts32 status = 0;\n\n\tstatus = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,\n\t\t\t\t (hw, firmware_version),\n\t\t\t\t IXGBE_NOT_IMPLEMENTED);\n\treturn status;\n}\n\n/**\n * ixgbe_read_phy_reg - Read PHY register\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit address of PHY register to read\n * @phy_data: Pointer to read data from PHY register\n *\n * Reads a value from a specified PHY register\n **/\ns32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n\t\t u16 *phy_data)\n{\n\tif (hw->phy.id == 0)\n\t\tixgbe_identify_phy(hw);\n\n\treturn ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,\n\t\t\t device_type, phy_data), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_phy_reg - Write PHY register\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit PHY register to write\n * @phy_data: Data to write to the PHY register\n *\n * Writes a value to specified PHY register\n **/\ns32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n\t\t\tu16 phy_data)\n{\n\tif (hw->phy.id == 0)\n\t\tixgbe_identify_phy(hw);\n\n\treturn ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,\n\t\t\t device_type, phy_data), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_setup_phy_link - Restart PHY autoneg\n * @hw: pointer to hardware structure\n *\n * Restart autonegotiation and PHY and waits for completion.\n **/\ns32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_check_phy_link - Determine link and speed status\n * @hw: pointer to hardware structure\n *\n * Reads a PHY register to determine if link is up and the current speed for\n * the PHY.\n **/\ns32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t bool *link_up)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,\n\t\t\t link_up), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_setup_phy_link_speed - Set auto advertise\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg: true if autonegotiation enabled\n *\n * Sets the auto advertised capabilities\n **/\ns32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t\t bool autoneg,\n\t\t\t bool autoneg_wait_to_complete)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,\n\t\t\t autoneg, autoneg_wait_to_complete),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_check_link - Get link and speed status\n * @hw: pointer to hardware structure\n *\n * Reads the links register to determine if link is up and the current speed\n **/\ns32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t bool *link_up, bool link_up_wait_to_complete)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,\n\t\t\t link_up, link_up_wait_to_complete),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_disable_tx_laser - Disable Tx laser\n * @hw: pointer to hardware structure\n *\n * If the driver needs to disable the laser on SFI optics.\n **/\nvoid ixgbe_disable_tx_laser(struct ixgbe_hw *hw)\n{\n\tif (hw->mac.ops.disable_tx_laser)\n\t\thw->mac.ops.disable_tx_laser(hw);\n}\n\n/**\n * ixgbe_enable_tx_laser - Enable Tx laser\n * @hw: pointer to hardware structure\n *\n * If the driver needs to enable the laser on SFI optics.\n **/\nvoid ixgbe_enable_tx_laser(struct ixgbe_hw *hw)\n{\n\tif (hw->mac.ops.enable_tx_laser)\n\t\thw->mac.ops.enable_tx_laser(hw);\n}\n\n/**\n * ixgbe_flap_tx_laser - flap Tx laser to start autotry process\n * @hw: pointer to hardware structure\n *\n * When the driver changes the link speeds that it can support then\n * flap the tx laser to alert the link partner to start autotry\n * process on its end.\n **/\nvoid ixgbe_flap_tx_laser(struct ixgbe_hw *hw)\n{\n\tif (hw->mac.ops.flap_tx_laser)\n\t\thw->mac.ops.flap_tx_laser(hw);\n}\n\n/**\n * ixgbe_setup_link - Set link speed\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg: true if autonegotiation enabled\n *\n * Configures link settings. Restarts the link.\n * Performs autonegotiation if needed.\n **/\ns32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t bool autoneg,\n\t\t bool autoneg_wait_to_complete)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,\n\t\t\t autoneg, autoneg_wait_to_complete),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_link_capabilities - Returns link capabilities\n * @hw: pointer to hardware structure\n *\n * Determines the link capabilities of the current configuration.\n **/\ns32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t\tbool *autoneg)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,\n\t\t\t speed, autoneg), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_led_on - Turn on LEDs\n * @hw: pointer to hardware structure\n * @index: led number to turn on\n *\n * Turns on the software controllable LEDs.\n **/\ns32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_led_off - Turn off LEDs\n * @hw: pointer to hardware structure\n * @index: led number to turn off\n *\n * Turns off the software controllable LEDs.\n **/\ns32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_blink_led_start - Blink LEDs\n * @hw: pointer to hardware structure\n * @index: led number to blink\n *\n * Blink LED based on index.\n **/\ns32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_blink_led_stop - Stop blinking LEDs\n * @hw: pointer to hardware structure\n *\n * Stop blinking LED based on index.\n **/\ns32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_init_eeprom_params - Initialize EEPROM parameters\n * @hw: pointer to hardware structure\n *\n * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n * ixgbe_hw struct in order to set up EEPROM access.\n **/\ns32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n\n/**\n * ixgbe_write_eeprom - Write word to EEPROM\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be written to\n * @data: 16 bit word to be written to the EEPROM\n *\n * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not\n * called after this function, the EEPROM will most likely contain an\n * invalid checksum.\n **/\ns32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be written to\n * @data: 16 bit word(s) to be written to the EEPROM\n * @words: number of words\n *\n * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not\n * called after this function, the EEPROM will most likely contain an\n * invalid checksum.\n **/\ns32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,\n\t\t\t u16 *data)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.write_buffer,\n\t\t\t (hw, offset, words, data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_eeprom - Read word from EEPROM\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be read\n * @data: read 16 bit value from EEPROM\n *\n * Reads 16 bit value from EEPROM\n **/\ns32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be read\n * @data: read 16 bit word(s) from EEPROM\n * @words: number of words\n *\n * Reads 16 bit word(s) from EEPROM\n **/\ns32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,\n\t\t\t u16 words, u16 *data)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.read_buffer,\n\t\t\t (hw, offset, words, data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum\n * @hw: pointer to hardware structure\n * @checksum_val: calculated checksum\n *\n * Performs checksum calculation and validates the EEPROM checksum\n **/\ns32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,\n\t\t\t (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_insert_mac_addr - Find a RAR for this mac address\n * @hw: pointer to hardware structure\n * @addr: Address to put into receive address register\n * @vmdq: VMDq pool to assign\n *\n * Puts an ethernet address into a receive address register, or\n * finds the rar that it is aleady in; adds to the pool list\n **/\ns32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr,\n\t\t\t (hw, addr, vmdq),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_rar - Set Rx address register\n * @hw: pointer to hardware structure\n * @index: Receive address register to write\n * @addr: Address to put into receive address register\n * @vmdq: VMDq \"set\"\n * @enable_addr: set flag that address is active\n *\n * Puts an ethernet address into a receive address register.\n **/\ns32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n\t\t u32 enable_addr)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,\n\t\t\t enable_addr), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_clear_rar - Clear Rx address register\n * @hw: pointer to hardware structure\n * @index: Receive address register to write\n *\n * Puts an ethernet address into a receive address register.\n **/\ns32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_vmdq - Associate a VMDq index with a receive address\n * @hw: pointer to hardware structure\n * @rar: receive address register index to associate with VMDq index\n * @vmdq: VMDq set or pool index\n **/\ns32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n\n}\n\n/**\n * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address\n * @hw: pointer to hardware structure\n * @vmdq: VMDq default pool index\n **/\ns32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,\n\t\t\t (hw, vmdq), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address\n * @hw: pointer to hardware structure\n * @rar: receive address register index to disassociate with VMDq index\n * @vmdq: VMDq set or pool index\n **/\ns32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_init_rx_addrs - Initializes receive address filters.\n * @hw: pointer to hardware structure\n *\n * Places the MAC address in receive address register 0 and clears the rest\n * of the receive address registers. Clears the multicast table. Assumes\n * the receiver is in reset when the routine is called.\n **/\ns32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_num_rx_addrs - Returns the number of RAR entries.\n * @hw: pointer to hardware structure\n **/\nu32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)\n{\n\treturn hw->mac.num_rar_entries;\n}\n\n/**\n * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses\n * @hw: pointer to hardware structure\n * @addr_list: the list of new multicast addresses\n * @addr_count: number of addresses\n * @func: iterator function to walk the multicast address list\n *\n * The given list replaces any existing list. Clears the secondary addrs from\n * receive address registers. Uses unused receive address registers for the\n * first secondary addresses, and falls back to promiscuous mode as needed.\n **/\ns32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,\n\t\t\t u32 addr_count, ixgbe_mc_addr_itr func)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,\n\t\t\t addr_list, addr_count, func),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses\n * @hw: pointer to hardware structure\n * @mc_addr_list: the list of new multicast addresses\n * @mc_addr_count: number of addresses\n * @func: iterator function to walk the multicast address list\n *\n * The given list replaces any existing list. Clears the MC addrs from receive\n * address registers and the multicast table. Uses unused receive address\n * registers for the first multicast addresses, and hashes the rest into the\n * multicast table.\n **/\ns32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,\n\t\t\t u32 mc_addr_count, ixgbe_mc_addr_itr func,\n\t\t\t bool clear)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,\n\t\t\t mc_addr_list, mc_addr_count, func, clear),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_enable_mc - Enable multicast address in RAR\n * @hw: pointer to hardware structure\n *\n * Enables multicast address in RAR and the use of the multicast hash table.\n **/\ns32 ixgbe_enable_mc(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_disable_mc - Disable multicast address in RAR\n * @hw: pointer to hardware structure\n *\n * Disables multicast address in RAR and the use of the multicast hash table.\n **/\ns32 ixgbe_disable_mc(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_clear_vfta - Clear VLAN filter table\n * @hw: pointer to hardware structure\n *\n * Clears the VLAN filer table, and the VMDq index associated with the filter\n **/\ns32 ixgbe_clear_vfta(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_vfta - Set VLAN filter table\n * @hw: pointer to hardware structure\n * @vlan: VLAN id to write to VLAN filter\n * @vind: VMDq output index that maps queue to VLAN id in VFTA\n * @vlan_on: boolean flag to turn on/off VLAN in VFTA\n *\n * Turn on/off specified VLAN in the VLAN filter table.\n **/\ns32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,\n\t\t\t vlan_on), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_vlvf - Set VLAN Pool Filter\n * @hw: pointer to hardware structure\n * @vlan: VLAN id to write to VLAN filter\n * @vind: VMDq output index that maps queue to VLAN id in VFVFB\n * @vlan_on: boolean flag to turn on/off VLAN in VFVF\n * @vfta_changed: pointer to boolean flag which indicates whether VFTA\n * should be changed\n *\n * Turn on/off specified bit in VLVF table.\n **/\ns32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,\n\t\t bool *vfta_changed)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,\n\t\t\t vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_fc_enable - Enable flow control\n * @hw: pointer to hardware structure\n *\n * Configures the flow control settings based on SW configuration.\n **/\ns32 ixgbe_fc_enable(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_set_fw_drv_ver - Try to send the driver version number FW\n * @hw: pointer to hardware structure\n * @maj: driver major number to be sent to firmware\n * @min: driver minor number to be sent to firmware\n * @build: driver build number to be sent to firmware\n * @ver: driver version number to be sent to firmware\n **/\ns32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n\t\t\t u8 ver)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,\n\t\t\t build, ver), IXGBE_NOT_IMPLEMENTED);\n}\n\n\n/**\n * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data\n * @hw: pointer to hardware structure\n *\n * Updates the temperatures in mac.thermal_sensor_data\n **/\ns32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw),\n\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds\n * @hw: pointer to hardware structure\n *\n * Inits the thermal sensor thresholds according to the NVM map\n **/\ns32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw),\n\t\t\t\tIXGBE_NOT_IMPLEMENTED);\n}\n/**\n * ixgbe_read_analog_reg8 - Reads 8 bit analog register\n * @hw: pointer to hardware structure\n * @reg: analog register to read\n * @val: read value\n *\n * Performs write operation to analog register specified.\n **/\ns32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,\n\t\t\t val), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_analog_reg8 - Writes 8 bit analog register\n * @hw: pointer to hardware structure\n * @reg: analog register to write\n * @val: value to write\n *\n * Performs write operation to Atlas analog register specified.\n **/\ns32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,\n\t\t\t val), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.\n * @hw: pointer to hardware structure\n *\n * Initializes the Unicast Table Arrays to zero on device load. This\n * is part of the Rx init addr execution path.\n **/\ns32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to read\n * @data: value read\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,\n\t\t\tu8 *data)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,\n\t\t\t dev_addr, data), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_i2c_byte - Writes 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @data: value to write\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface\n * at a specified device address.\n **/\ns32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,\n\t\t\t u8 data)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,\n\t\t\t dev_addr, data), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface\n * @hw: pointer to hardware structure\n * @byte_offset: EEPROM byte offset to write\n * @eeprom_data: value to write\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,\n\t\t\t u8 byte_offset, u8 eeprom_data)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,\n\t\t\t (hw, byte_offset, eeprom_data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface\n * @hw: pointer to hardware structure\n * @byte_offset: EEPROM byte offset to read\n * @eeprom_data: value read\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)\n{\n\treturn ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,\n\t\t\t (hw, byte_offset, eeprom_data),\n\t\t\t IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_get_supported_physical_layer - Returns physical layer type\n * @hw: pointer to hardware structure\n *\n * Determines physical layer capabilities of the current configuration.\n **/\nu32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,\n\t\t\t (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);\n}\n\n/**\n * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics\n * @hw: pointer to hardware structure\n * @regval: bitfield to write to the Rx DMA register\n *\n * Enables the Rx DMA unit of the device.\n **/\ns32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,\n\t\t\t (hw, regval), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_disable_sec_rx_path - Stops the receive data path\n * @hw: pointer to hardware structure\n *\n * Stops the receive data path.\n **/\ns32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path,\n\t\t\t\t(hw), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_enable_sec_rx_path - Enables the receive data path\n * @hw: pointer to hardware structure\n *\n * Enables the receive data path.\n **/\ns32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,\n\t\t\t\t(hw), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to acquire\n *\n * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified\n * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\ns32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)\n{\n\treturn ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,\n\t\t\t (hw, mask), IXGBE_NOT_IMPLEMENTED);\n}\n\n/**\n * ixgbe_release_swfw_semaphore - Release SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to release\n *\n * Releases the SWFW semaphore through SW_FW_SYNC register for the specified\n * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\nvoid ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)\n{\n\tif (hw->mac.ops.release_swfw_sync)\n\t\thw->mac.ops.release_swfw_sync(hw, mask);\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_api.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _IXGBE_API_H_\n#define _IXGBE_API_H_\n\n#include \"ixgbe_type.h\"\n\ns32 ixgbe_init_shared_code(struct ixgbe_hw *hw);\n\nextern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);\nextern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);\nextern s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw);\n\ns32 ixgbe_set_mac_type(struct ixgbe_hw *hw);\ns32 ixgbe_init_hw(struct ixgbe_hw *hw);\ns32 ixgbe_reset_hw(struct ixgbe_hw *hw);\ns32 ixgbe_start_hw(struct ixgbe_hw *hw);\ns32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);\nenum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw);\ns32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);\ns32 ixgbe_get_bus_info(struct ixgbe_hw *hw);\nu32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);\nu32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);\ns32 ixgbe_stop_adapter(struct ixgbe_hw *hw);\ns32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);\n\ns32 ixgbe_identify_phy(struct ixgbe_hw *hw);\ns32 ixgbe_reset_phy(struct ixgbe_hw *hw);\ns32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n\t\t u16 *phy_data);\ns32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,\n\t\t\tu16 phy_data);\n\ns32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);\ns32 ixgbe_check_phy_link(struct ixgbe_hw *hw,\n\t\t\t ixgbe_link_speed *speed,\n\t\t\t bool *link_up);\ns32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,\n\t\t\t ixgbe_link_speed speed,\n\t\t\t bool autoneg,\n\t\t\t bool autoneg_wait_to_complete);\nvoid ixgbe_disable_tx_laser(struct ixgbe_hw *hw);\nvoid ixgbe_enable_tx_laser(struct ixgbe_hw *hw);\nvoid ixgbe_flap_tx_laser(struct ixgbe_hw *hw);\ns32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t bool autoneg, bool autoneg_wait_to_complete);\ns32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t bool *link_up, bool link_up_wait_to_complete);\ns32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t\tbool *autoneg);\ns32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);\n\ns32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);\ns32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);\ns32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,\n\t\t\t u16 words, u16 *data);\ns32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);\ns32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,\n\t\t\t u16 words, u16 *data);\n\ns32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);\ns32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);\n\ns32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);\ns32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n\t\t u32 enable_addr);\ns32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);\ns32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq);\ns32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);\ns32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);\nu32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);\ns32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,\n\t\t\t u32 addr_count, ixgbe_mc_addr_itr func);\ns32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,\n\t\t\t u32 mc_addr_count, ixgbe_mc_addr_itr func,\n\t\t\t bool clear);\nvoid ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);\ns32 ixgbe_enable_mc(struct ixgbe_hw *hw);\ns32 ixgbe_disable_mc(struct ixgbe_hw *hw);\ns32 ixgbe_clear_vfta(struct ixgbe_hw *hw);\ns32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,\n\t\t u32 vind, bool vlan_on);\ns32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n\t\t bool vlan_on, bool *vfta_changed);\ns32 ixgbe_fc_enable(struct ixgbe_hw *hw);\ns32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n\t\t\t u8 ver);\ns32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw);\ns32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw);\nvoid ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);\ns32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,\n\t\t\t\t u16 *firmware_version);\ns32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);\ns32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);\ns32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);\ns32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data);\nu32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw);\ns32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval);\ns32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw);\ns32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw);\ns32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);\ns32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);\ns32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);\ns32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t union ixgbe_atr_hash_dword input,\n\t\t\t\t\t union ixgbe_atr_hash_dword common,\n\t\t\t\t\t u8 queue);\ns32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,\n\t\t\t\t union ixgbe_atr_input *input_mask);\ns32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t union ixgbe_atr_input *input,\n\t\t\t\t\t u16 soft_id, u8 queue);\ns32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\t union ixgbe_atr_input *input,\n\t\t\t\t\t u16 soft_id);\ns32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,\n\t\t\t\t\tunion ixgbe_atr_input *input,\n\t\t\t\t\tunion ixgbe_atr_input *mask,\n\t\t\t\t\tu16 soft_id,\n\t\t\t\t\tu8 queue);\nvoid ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,\n\t\t\t\t\t union ixgbe_atr_input *mask);\nu32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,\n\t\t\t\t union ixgbe_atr_hash_dword common);\ns32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,\n\t\t\tu8 *data);\ns32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,\n\t\t\t u8 data);\ns32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);\ns32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);\ns32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);\ns32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);\ns32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);\nvoid ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);\ns32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n\t\t\t u16 *wwpn_prefix);\ns32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);\n\n#endif /* _IXGBE_API_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_common.c", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"ixgbe_common.h\"\n#include \"ixgbe_phy.h\"\n#include \"ixgbe_api.h\"\n\nstatic s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);\nstatic s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);\nstatic void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);\nstatic s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);\nstatic void ixgbe_standby_eeprom(struct ixgbe_hw *hw);\nstatic void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,\n\t\t\t\t\tu16 count);\nstatic u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);\nstatic void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);\nstatic void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);\nstatic void ixgbe_release_eeprom(struct ixgbe_hw *hw);\n\nstatic s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);\nstatic s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *san_mac_offset);\nstatic s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data);\nstatic s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data);\nstatic s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t\t u16 offset);\n\n/**\n * ixgbe_init_ops_generic - Inits function ptrs\n * @hw: pointer to the hardware structure\n *\n * Initialize the function pointers.\n **/\ns32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tu32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\t/* EEPROM */\n\teeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;\n\t/* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */\n\tif (eec & IXGBE_EEC_PRES) {\n\t\teeprom->ops.read = &ixgbe_read_eerd_generic;\n\t\teeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;\n\t} else {\n\t\teeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;\n\t\teeprom->ops.read_buffer =\n\t\t\t\t &ixgbe_read_eeprom_buffer_bit_bang_generic;\n\t}\n\teeprom->ops.write = &ixgbe_write_eeprom_generic;\n\teeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;\n\teeprom->ops.validate_checksum =\n\t\t\t\t &ixgbe_validate_eeprom_checksum_generic;\n\teeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;\n\teeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;\n\n\t/* MAC */\n\tmac->ops.init_hw = &ixgbe_init_hw_generic;\n\tmac->ops.reset_hw = NULL;\n\tmac->ops.start_hw = &ixgbe_start_hw_generic;\n\tmac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;\n\tmac->ops.get_media_type = NULL;\n\tmac->ops.get_supported_physical_layer = NULL;\n\tmac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;\n\tmac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;\n\tmac->ops.stop_adapter = &ixgbe_stop_adapter_generic;\n\tmac->ops.get_bus_info = &ixgbe_get_bus_info_generic;\n\tmac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;\n\tmac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;\n\tmac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;\n\n\t/* LEDs */\n\tmac->ops.led_on = &ixgbe_led_on_generic;\n\tmac->ops.led_off = &ixgbe_led_off_generic;\n\tmac->ops.blink_led_start = &ixgbe_blink_led_start_generic;\n\tmac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;\n\n\t/* RAR, Multicast, VLAN */\n\tmac->ops.set_rar = &ixgbe_set_rar_generic;\n\tmac->ops.clear_rar = &ixgbe_clear_rar_generic;\n\tmac->ops.insert_mac_addr = NULL;\n\tmac->ops.set_vmdq = NULL;\n\tmac->ops.clear_vmdq = NULL;\n\tmac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;\n\tmac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;\n\tmac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;\n\tmac->ops.enable_mc = &ixgbe_enable_mc_generic;\n\tmac->ops.disable_mc = &ixgbe_disable_mc_generic;\n\tmac->ops.clear_vfta = NULL;\n\tmac->ops.set_vfta = NULL;\n\tmac->ops.set_vlvf = NULL;\n\tmac->ops.init_uta_tables = NULL;\n\n\t/* Flow Control */\n\tmac->ops.fc_enable = &ixgbe_fc_enable_generic;\n\n\t/* Link */\n\tmac->ops.get_link_capabilities = NULL;\n\tmac->ops.setup_link = NULL;\n\tmac->ops.check_link = NULL;\n\n\treturn 0;\n}\n\n/**\n * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow\n * control\n * @hw: pointer to hardware structure\n *\n * There are several phys that do not support autoneg flow control. This\n * function check the device id to see if the associated phy supports\n * autoneg flow control.\n **/\nstatic s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)\n{\n\n\tswitch (hw->device_id) {\n\tcase IXGBE_DEV_ID_X540T:\n\t\treturn 0;\n\tcase IXGBE_DEV_ID_82599_T3_LOM:\n\t\treturn 0;\n\tdefault:\n\t\treturn IXGBE_ERR_FC_NOT_SUPPORTED;\n\t}\n}\n\n/**\n * ixgbe_setup_fc - Set up flow control\n * @hw: pointer to hardware structure\n *\n * Called at init time to set up flow control.\n **/\nstatic s32 ixgbe_setup_fc(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = 0;\n\tu32 reg = 0, reg_bp = 0;\n\tu16 reg_cu = 0;\n\n\t/*\n\t * Validate the requested mode. Strict IEEE mode does not allow\n\t * ixgbe_fc_rx_pause because it will cause us to fail at UNH.\n\t */\n\tif (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {\n\t\thw_dbg(hw, \"ixgbe_fc_rx_pause not valid in strict IEEE mode\\n\");\n\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * 10gig parts do not have a word in the EEPROM to determine the\n\t * default flow control setting, so we explicitly set it to full.\n\t */\n\tif (hw->fc.requested_mode == ixgbe_fc_default)\n\t\thw->fc.requested_mode = ixgbe_fc_full;\n\n\t/*\n\t * Set up the 1G and 10G flow control advertisement registers so the\n\t * HW will be able to do fc autoneg once the cable is plugged in. If\n\t * we link at 10G, the 1G advertisement is harmless and vice versa.\n\t */\n\tswitch (hw->phy.media_type) {\n\tcase ixgbe_media_type_fiber:\n\tcase ixgbe_media_type_backplane:\n\t\treg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);\n\t\treg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\t\tbreak;\n\tcase ixgbe_media_type_copper:\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/*\n\t * The possible values of fc.requested_mode are:\n\t * 0: Flow control is completely disabled\n\t * 1: Rx flow control is enabled (we can receive pause frames,\n\t * but not send pause frames).\n\t * 2: Tx flow control is enabled (we can send pause frames but\n\t * we do not support receiving pause frames).\n\t * 3: Both Rx and Tx flow control (symmetric) are enabled.\n\t * other: Invalid.\n\t */\n\tswitch (hw->fc.requested_mode) {\n\tcase ixgbe_fc_none:\n\t\t/* Flow control completely disabled by software override. */\n\t\treg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);\n\t\tif (hw->phy.media_type == ixgbe_media_type_backplane)\n\t\t\treg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |\n\t\t\t\t IXGBE_AUTOC_ASM_PAUSE);\n\t\telse if (hw->phy.media_type == ixgbe_media_type_copper)\n\t\t\treg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);\n\t\tbreak;\n\tcase ixgbe_fc_tx_pause:\n\t\t/*\n\t\t * Tx Flow control is enabled, and Rx Flow control is\n\t\t * disabled by software override.\n\t\t */\n\t\treg |= IXGBE_PCS1GANA_ASM_PAUSE;\n\t\treg &= ~IXGBE_PCS1GANA_SYM_PAUSE;\n\t\tif (hw->phy.media_type == ixgbe_media_type_backplane) {\n\t\t\treg_bp |= IXGBE_AUTOC_ASM_PAUSE;\n\t\t\treg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;\n\t\t} else if (hw->phy.media_type == ixgbe_media_type_copper) {\n\t\t\treg_cu |= IXGBE_TAF_ASM_PAUSE;\n\t\t\treg_cu &= ~IXGBE_TAF_SYM_PAUSE;\n\t\t}\n\t\tbreak;\n\tcase ixgbe_fc_rx_pause:\n\t\t/*\n\t\t * Rx Flow control is enabled and Tx Flow control is\n\t\t * disabled by software override. Since there really\n\t\t * isn't a way to advertise that we are capable of RX\n\t\t * Pause ONLY, we will advertise that we support both\n\t\t * symmetric and asymmetric Rx PAUSE, as such we fall\n\t\t * through to the fc_full statement. Later, we will\n\t\t * disable the adapter's ability to send PAUSE frames.\n\t\t */\n\tcase ixgbe_fc_full:\n\t\t/* Flow control (both Rx and Tx) is enabled by SW override. */\n\t\treg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;\n\t\tif (hw->phy.media_type == ixgbe_media_type_backplane)\n\t\t\treg_bp |= IXGBE_AUTOC_SYM_PAUSE |\n\t\t\t\t IXGBE_AUTOC_ASM_PAUSE;\n\t\telse if (hw->phy.media_type == ixgbe_media_type_copper)\n\t\t\treg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;\n\t\tbreak;\n\tdefault:\n\t\thw_dbg(hw, \"Flow control param set incorrectly\\n\");\n\t\tret_val = IXGBE_ERR_CONFIG;\n\t\tgoto out;\n\t\tbreak;\n\t}\n\n\tif (hw->mac.type != ixgbe_mac_X540) {\n\t\t/*\n\t\t * Enable auto-negotiation between the MAC & PHY;\n\t\t * the MAC will advertise clause 37 flow control.\n\t\t */\n\t\tIXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);\n\t\treg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);\n\n\t\t/* Disable AN timeout */\n\t\tif (hw->fc.strict_ieee)\n\t\t\treg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);\n\t\thw_dbg(hw, \"Set up FC; PCS1GLCTL = 0x%08X\\n\", reg);\n\t}\n\n\t/*\n\t * AUTOC restart handles negotiation of 1G and 10G on backplane\n\t * and copper. There is no need to set the PCS1GCTL register.\n\t *\n\t */\n\tif (hw->phy.media_type == ixgbe_media_type_backplane) {\n\t\treg_bp |= IXGBE_AUTOC_AN_RESTART;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);\n\t} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&\n\t\t (ixgbe_device_supports_autoneg_fc(hw) == 0)) {\n\t\thw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);\n\t}\n\n\thw_dbg(hw, \"Set up FC; IXGBE_AUTOC = 0x%08X\\n\", reg);\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx\n * @hw: pointer to hardware structure\n *\n * Starts the hardware by filling the bus info structure and media type, clears\n * all on chip counters, initializes receive address registers, multicast\n * table, VLAN filter table, calls routine to set up link and flow control\n * settings, and leaves transmit and receive units disabled and uninitialized\n **/\ns32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)\n{\n\ts32 ret_val;\n\tu32 ctrl_ext;\n\n\t/* Set the media type */\n\thw->phy.media_type = hw->mac.ops.get_media_type(hw);\n\n\t/* PHY ops initialization must be done in reset_hw() */\n\n\t/* Clear the VLAN filter table */\n\thw->mac.ops.clear_vfta(hw);\n\n\t/* Clear statistics registers */\n\thw->mac.ops.clear_hw_cntrs(hw);\n\n\t/* Set No Snoop Disable */\n\tctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);\n\tctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Setup flow control */\n\tret_val = ixgbe_setup_fc(hw);\n\tif (ret_val != 0)\n\t\tgoto out;\n\n\t/* Clear adapter stopped flag */\n\thw->adapter_stopped = false;\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_start_hw_gen2 - Init sequence for common device family\n * @hw: pointer to hw structure\n *\n * Performs the init sequence common to the second generation\n * of 10 GbE devices.\n * Devices in the second generation:\n * 82599\n * X540\n **/\ns32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)\n{\n\tu32 i;\n\tu32 regval;\n\n\t/* Clear the rate limiters */\n\tfor (i = 0; i < hw->mac.max_tx_queues; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);\n\t}\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Disable relaxed ordering */\n\tfor (i = 0; i < hw->mac.max_tx_queues; i++) {\n\t\tregval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));\n\t\tregval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);\n\t}\n\n\tfor (i = 0; i < hw->mac.max_rx_queues; i++) {\n\t\tregval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));\n\t\tregval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |\n\t\t\t IXGBE_DCA_RXCTRL_HEAD_WRO_EN);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_init_hw_generic - Generic hardware initialization\n * @hw: pointer to hardware structure\n *\n * Initialize the hardware by resetting the hardware, filling the bus info\n * structure and media type, clears all on chip counters, initializes receive\n * address registers, multicast table, VLAN filter table, calls routine to set\n * up link and flow control settings, and leaves transmit and receive units\n * disabled and uninitialized\n **/\ns32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\n\t/* Reset the hardware */\n\tstatus = hw->mac.ops.reset_hw(hw);\n\n\tif (status == 0) {\n\t\t/* Start the HW */\n\t\tstatus = hw->mac.ops.start_hw(hw);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters\n * @hw: pointer to hardware structure\n *\n * Clears all hardware statistics counters by reading them from the hardware\n * Statistics counters are clear on read.\n **/\ns32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)\n{\n\tu16 i = 0;\n\n\tIXGBE_READ_REG(hw, IXGBE_CRCERRS);\n\tIXGBE_READ_REG(hw, IXGBE_ILLERRC);\n\tIXGBE_READ_REG(hw, IXGBE_ERRBC);\n\tIXGBE_READ_REG(hw, IXGBE_MSPDC);\n\tfor (i = 0; i < 8; i++)\n\t\tIXGBE_READ_REG(hw, IXGBE_MPC(i));\n\n\tIXGBE_READ_REG(hw, IXGBE_MLFC);\n\tIXGBE_READ_REG(hw, IXGBE_MRFC);\n\tIXGBE_READ_REG(hw, IXGBE_RLEC);\n\tIXGBE_READ_REG(hw, IXGBE_LXONTXC);\n\tIXGBE_READ_REG(hw, IXGBE_LXOFFTXC);\n\tif (hw->mac.type >= ixgbe_mac_82599EB) {\n\t\tIXGBE_READ_REG(hw, IXGBE_LXONRXCNT);\n\t\tIXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);\n\t} else {\n\t\tIXGBE_READ_REG(hw, IXGBE_LXONRXC);\n\t\tIXGBE_READ_REG(hw, IXGBE_LXOFFRXC);\n\t}\n\n\tfor (i = 0; i < 8; i++) {\n\t\tIXGBE_READ_REG(hw, IXGBE_PXONTXC(i));\n\t\tIXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));\n\t\tif (hw->mac.type >= ixgbe_mac_82599EB) {\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));\n\t\t} else {\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PXONRXC(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));\n\t\t}\n\t}\n\tif (hw->mac.type >= ixgbe_mac_82599EB)\n\t\tfor (i = 0; i < 8; i++)\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));\n\tIXGBE_READ_REG(hw, IXGBE_PRC64);\n\tIXGBE_READ_REG(hw, IXGBE_PRC127);\n\tIXGBE_READ_REG(hw, IXGBE_PRC255);\n\tIXGBE_READ_REG(hw, IXGBE_PRC511);\n\tIXGBE_READ_REG(hw, IXGBE_PRC1023);\n\tIXGBE_READ_REG(hw, IXGBE_PRC1522);\n\tIXGBE_READ_REG(hw, IXGBE_GPRC);\n\tIXGBE_READ_REG(hw, IXGBE_BPRC);\n\tIXGBE_READ_REG(hw, IXGBE_MPRC);\n\tIXGBE_READ_REG(hw, IXGBE_GPTC);\n\tIXGBE_READ_REG(hw, IXGBE_GORCL);\n\tIXGBE_READ_REG(hw, IXGBE_GORCH);\n\tIXGBE_READ_REG(hw, IXGBE_GOTCL);\n\tIXGBE_READ_REG(hw, IXGBE_GOTCH);\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\tfor (i = 0; i < 8; i++)\n\t\t\tIXGBE_READ_REG(hw, IXGBE_RNBC(i));\n\tIXGBE_READ_REG(hw, IXGBE_RUC);\n\tIXGBE_READ_REG(hw, IXGBE_RFC);\n\tIXGBE_READ_REG(hw, IXGBE_ROC);\n\tIXGBE_READ_REG(hw, IXGBE_RJC);\n\tIXGBE_READ_REG(hw, IXGBE_MNGPRC);\n\tIXGBE_READ_REG(hw, IXGBE_MNGPDC);\n\tIXGBE_READ_REG(hw, IXGBE_MNGPTC);\n\tIXGBE_READ_REG(hw, IXGBE_TORL);\n\tIXGBE_READ_REG(hw, IXGBE_TORH);\n\tIXGBE_READ_REG(hw, IXGBE_TPR);\n\tIXGBE_READ_REG(hw, IXGBE_TPT);\n\tIXGBE_READ_REG(hw, IXGBE_PTC64);\n\tIXGBE_READ_REG(hw, IXGBE_PTC127);\n\tIXGBE_READ_REG(hw, IXGBE_PTC255);\n\tIXGBE_READ_REG(hw, IXGBE_PTC511);\n\tIXGBE_READ_REG(hw, IXGBE_PTC1023);\n\tIXGBE_READ_REG(hw, IXGBE_PTC1522);\n\tIXGBE_READ_REG(hw, IXGBE_MPTC);\n\tIXGBE_READ_REG(hw, IXGBE_BPTC);\n\tfor (i = 0; i < 16; i++) {\n\t\tIXGBE_READ_REG(hw, IXGBE_QPRC(i));\n\t\tIXGBE_READ_REG(hw, IXGBE_QPTC(i));\n\t\tif (hw->mac.type >= ixgbe_mac_82599EB) {\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBRC_L(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBRC_H(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBTC_L(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBTC_H(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QPRDC(i));\n\t\t} else {\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBRC(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBTC(i));\n\t\t}\n\t}\n\n\tif (hw->mac.type == ixgbe_mac_X540) {\n\t\tif (hw->phy.id == 0)\n\t\t\tixgbe_identify_phy(hw);\n\t\thw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,\n\t\t\t\t IXGBE_MDIO_PCS_DEV_TYPE, &i);\n\t\thw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,\n\t\t\t\t IXGBE_MDIO_PCS_DEV_TYPE, &i);\n\t\thw->phy.ops.read_reg(hw, IXGBE_LDPCECL,\n\t\t\t\t IXGBE_MDIO_PCS_DEV_TYPE, &i);\n\t\thw->phy.ops.read_reg(hw, IXGBE_LDPCECH,\n\t\t\t\t IXGBE_MDIO_PCS_DEV_TYPE, &i);\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_read_pba_string_generic - Reads part number string from EEPROM\n * @hw: pointer to hardware structure\n * @pba_num: stores the part number string from the EEPROM\n * @pba_num_size: part number string buffer length\n *\n * Reads the part number string from the EEPROM.\n **/\ns32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,\n\t\t\t\t u32 pba_num_size)\n{\n\ts32 ret_val;\n\tu16 data;\n\tu16 pba_ptr;\n\tu16 offset;\n\tu16 length;\n\n\tif (pba_num == NULL) {\n\t\thw_dbg(hw, \"PBA string buffer was null\\n\");\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\tret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);\n\tif (ret_val) {\n\t\thw_dbg(hw, \"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);\n\tif (ret_val) {\n\t\thw_dbg(hw, \"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\t/*\n\t * if data is not ptr guard the PBA must be in legacy format which\n\t * means pba_ptr is actually our second data word for the PBA number\n\t * and we can decode it into an ascii string\n\t */\n\tif (data != IXGBE_PBANUM_PTR_GUARD) {\n\t\thw_dbg(hw, \"NVM PBA number is not stored as string\\n\");\n\n\t\t/* we will need 11 characters to store the PBA */\n\t\tif (pba_num_size < 11) {\n\t\t\thw_dbg(hw, \"PBA string buffer too small\\n\");\n\t\t\treturn IXGBE_ERR_NO_SPACE;\n\t\t}\n\n\t\t/* extract hex string from data and pba_ptr */\n\t\tpba_num[0] = (data >> 12) & 0xF;\n\t\tpba_num[1] = (data >> 8) & 0xF;\n\t\tpba_num[2] = (data >> 4) & 0xF;\n\t\tpba_num[3] = data & 0xF;\n\t\tpba_num[4] = (pba_ptr >> 12) & 0xF;\n\t\tpba_num[5] = (pba_ptr >> 8) & 0xF;\n\t\tpba_num[6] = '-';\n\t\tpba_num[7] = 0;\n\t\tpba_num[8] = (pba_ptr >> 4) & 0xF;\n\t\tpba_num[9] = pba_ptr & 0xF;\n\n\t\t/* put a null character on the end of our string */\n\t\tpba_num[10] = '\\0';\n\n\t\t/* switch all the data but the '-' to hex char */\n\t\tfor (offset = 0; offset < 10; offset++) {\n\t\t\tif (pba_num[offset] < 0xA)\n\t\t\t\tpba_num[offset] += '0';\n\t\t\telse if (pba_num[offset] < 0x10)\n\t\t\t\tpba_num[offset] += 'A' - 0xA;\n\t\t}\n\n\t\treturn 0;\n\t}\n\n\tret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);\n\tif (ret_val) {\n\t\thw_dbg(hw, \"NVM Read Error\\n\");\n\t\treturn ret_val;\n\t}\n\n\tif (length == 0xFFFF || length == 0) {\n\t\thw_dbg(hw, \"NVM PBA number section invalid length\\n\");\n\t\treturn IXGBE_ERR_PBA_SECTION;\n\t}\n\n\t/* check if pba_num buffer is big enough */\n\tif (pba_num_size < (((u32)length * 2) - 1)) {\n\t\thw_dbg(hw, \"PBA string buffer too small\\n\");\n\t\treturn IXGBE_ERR_NO_SPACE;\n\t}\n\n\t/* trim pba length from start of string */\n\tpba_ptr++;\n\tlength--;\n\n\tfor (offset = 0; offset < length; offset++) {\n\t\tret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);\n\t\tif (ret_val) {\n\t\t\thw_dbg(hw, \"NVM Read Error\\n\");\n\t\t\treturn ret_val;\n\t\t}\n\t\tpba_num[offset * 2] = (u8)(data >> 8);\n\t\tpba_num[(offset * 2) + 1] = (u8)(data & 0xFF);\n\t}\n\tpba_num[offset * 2] = '\\0';\n\n\treturn 0;\n}\n\n/**\n * ixgbe_get_mac_addr_generic - Generic get MAC address\n * @hw: pointer to hardware structure\n * @mac_addr: Adapter MAC address\n *\n * Reads the adapter's MAC address from first Receive Address Register (RAR0)\n * A reset of the adapter must be performed prior to calling this function\n * in order for the MAC address to have been loaded from the EEPROM into RAR0\n **/\ns32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)\n{\n\tu32 rar_high;\n\tu32 rar_low;\n\tu16 i;\n\n\trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));\n\trar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));\n\n\tfor (i = 0; i < 4; i++)\n\t\tmac_addr[i] = (u8)(rar_low >> (i*8));\n\n\tfor (i = 0; i < 2; i++)\n\t\tmac_addr[i+4] = (u8)(rar_high >> (i*8));\n\n\treturn 0;\n}\n\n/**\n * ixgbe_get_bus_info_generic - Generic set PCI bus info\n * @hw: pointer to hardware structure\n *\n * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure\n **/\ns32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tu16 link_status;\n\n\thw->bus.type = ixgbe_bus_type_pci_express;\n\n\t/* Get the negotiated link width and speed from PCI config space */\n\tlink_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);\n\n\tswitch (link_status & IXGBE_PCI_LINK_WIDTH) {\n\tcase IXGBE_PCI_LINK_WIDTH_1:\n\t\thw->bus.width = ixgbe_bus_width_pcie_x1;\n\t\tbreak;\n\tcase IXGBE_PCI_LINK_WIDTH_2:\n\t\thw->bus.width = ixgbe_bus_width_pcie_x2;\n\t\tbreak;\n\tcase IXGBE_PCI_LINK_WIDTH_4:\n\t\thw->bus.width = ixgbe_bus_width_pcie_x4;\n\t\tbreak;\n\tcase IXGBE_PCI_LINK_WIDTH_8:\n\t\thw->bus.width = ixgbe_bus_width_pcie_x8;\n\t\tbreak;\n\tdefault:\n\t\thw->bus.width = ixgbe_bus_width_unknown;\n\t\tbreak;\n\t}\n\n\tswitch (link_status & IXGBE_PCI_LINK_SPEED) {\n\tcase IXGBE_PCI_LINK_SPEED_2500:\n\t\thw->bus.speed = ixgbe_bus_speed_2500;\n\t\tbreak;\n\tcase IXGBE_PCI_LINK_SPEED_5000:\n\t\thw->bus.speed = ixgbe_bus_speed_5000;\n\t\tbreak;\n\tcase IXGBE_PCI_LINK_SPEED_8000:\n\t\thw->bus.speed = ixgbe_bus_speed_8000;\n\t\tbreak;\n\tdefault:\n\t\thw->bus.speed = ixgbe_bus_speed_unknown;\n\t\tbreak;\n\t}\n\n\tmac->ops.set_lan_id(hw);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices\n * @hw: pointer to the HW structure\n *\n * Determines the LAN function id by reading memory-mapped registers\n * and swaps the port value if requested.\n **/\nvoid ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_bus_info *bus = &hw->bus;\n\tu32 reg;\n\n\treg = IXGBE_READ_REG(hw, IXGBE_STATUS);\n\tbus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;\n\tbus->lan_id = bus->func;\n\n\t/* check for a port swap */\n\treg = IXGBE_READ_REG(hw, IXGBE_FACTPS);\n\tif (reg & IXGBE_FACTPS_LFS)\n\t\tbus->func ^= 0x1;\n}\n\n/**\n * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units\n * @hw: pointer to hardware structure\n *\n * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,\n * disables transmit and receive units. The adapter_stopped flag is used by\n * the shared code and drivers to determine if the adapter is in a stopped\n * state and should not touch the hardware.\n **/\ns32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)\n{\n\tu32 reg_val;\n\tu16 i;\n\n\t/*\n\t * Set the adapter_stopped flag so other driver functions stop touching\n\t * the hardware\n\t */\n\thw->adapter_stopped = true;\n\n\t/* Disable the receive unit */\n\tIXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);\n\n\t/* Clear interrupt mask to stop interrupts from being generated */\n\tIXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);\n\n\t/* Clear any pending interrupts, flush previous writes */\n\tIXGBE_READ_REG(hw, IXGBE_EICR);\n\n\t/* Disable the transmit unit. Each queue must be disabled. */\n\tfor (i = 0; i < hw->mac.max_tx_queues; i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);\n\n\t/* Disable the receive unit by stopping each queue */\n\tfor (i = 0; i < hw->mac.max_rx_queues; i++) {\n\t\treg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));\n\t\treg_val &= ~IXGBE_RXDCTL_ENABLE;\n\t\treg_val |= IXGBE_RXDCTL_SWFLSH;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);\n\t}\n\n\t/* flush all queues disables */\n\tIXGBE_WRITE_FLUSH(hw);\n\tmsleep(2);\n\n\t/*\n\t * Prevent the PCI-E bus from from hanging by disabling PCI-E master\n\t * access and verify no pending requests\n\t */\n\treturn ixgbe_disable_pcie_master(hw);\n}\n\n/**\n * ixgbe_led_on_generic - Turns on the software controllable LEDs.\n * @hw: pointer to hardware structure\n * @index: led number to turn on\n **/\ns32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)\n{\n\tu32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\n\t/* To turn on the LED, set mode to ON. */\n\tled_reg &= ~IXGBE_LED_MODE_MASK(index);\n\tled_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_led_off_generic - Turns off the software controllable LEDs.\n * @hw: pointer to hardware structure\n * @index: led number to turn off\n **/\ns32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)\n{\n\tu32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\n\t/* To turn off the LED, set mode to OFF. */\n\tled_reg &= ~IXGBE_LED_MODE_MASK(index);\n\tled_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_init_eeprom_params_generic - Initialize EEPROM params\n * @hw: pointer to hardware structure\n *\n * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n * ixgbe_hw struct in order to set up EEPROM access.\n **/\ns32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\tu32 eec;\n\tu16 eeprom_size;\n\n\tif (eeprom->type == ixgbe_eeprom_uninitialized) {\n\t\teeprom->type = ixgbe_eeprom_none;\n\t\t/* Set default semaphore delay to 10ms which is a well\n\t\t * tested value */\n\t\teeprom->semaphore_delay = 10;\n\t\t/* Clear EEPROM page size, it will be initialized as needed */\n\t\teeprom->word_page_size = 0;\n\n\t\t/*\n\t\t * Check for EEPROM present first.\n\t\t * If not present leave as none\n\t\t */\n\t\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\t\tif (eec & IXGBE_EEC_PRES) {\n\t\t\teeprom->type = ixgbe_eeprom_spi;\n\n\t\t\t/*\n\t\t\t * SPI EEPROM is assumed here. This code would need to\n\t\t\t * change if a future EEPROM is not SPI.\n\t\t\t */\n\t\t\teeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>\n\t\t\t\t\t IXGBE_EEC_SIZE_SHIFT);\n\t\t\teeprom->word_size = 1 << (eeprom_size +\n\t\t\t\t\t IXGBE_EEPROM_WORD_SIZE_SHIFT);\n\t\t}\n\n\t\tif (eec & IXGBE_EEC_ADDR_SIZE)\n\t\t\teeprom->address_bits = 16;\n\t\telse\n\t\t\teeprom->address_bits = 8;\n\t\thw_dbg(hw, \"Eeprom params: type = %d, size = %d, address bits: \"\n\t\t\t \"%d\\n\", eeprom->type, eeprom->word_size,\n\t\t\t eeprom->address_bits);\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to write\n * @words: number of word(s)\n * @data: 16 bit word(s) to write to EEPROM\n *\n * Reads 16 bit word(s) from EEPROM through bit-bang method\n **/\ns32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data)\n{\n\ts32 status = 0;\n\tu16 i, count;\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (words == 0) {\n\t\tstatus = IXGBE_ERR_INVALID_ARGUMENT;\n\t\tgoto out;\n\t}\n\n\tif (offset + words > hw->eeprom.word_size) {\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * The EEPROM page size cannot be queried from the chip. We do lazy\n\t * initialization. It is worth to do that when we write large buffer.\n\t */\n\tif ((hw->eeprom.word_page_size == 0) &&\n\t (words > IXGBE_EEPROM_PAGE_SIZE_MAX))\n\t\tixgbe_detect_eeprom_page_size_generic(hw, offset);\n\n\t/*\n\t * We cannot hold synchronization semaphores for too long\n\t * to avoid other entity starvation. However it is more efficient\n\t * to read in bursts than synchronizing access for each word.\n\t */\n\tfor (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {\n\t\tcount = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?\n\t\t\tIXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);\n\t\tstatus = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,\n\t\t\t\t\t\t\t count, &data[i]);\n\n\t\tif (status != 0)\n\t\t\tbreak;\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be written to\n * @words: number of word(s)\n * @data: 16 bit word(s) to be written to the EEPROM\n *\n * If ixgbe_eeprom_update_checksum is not called after this function, the\n * EEPROM will most likely contain an invalid checksum.\n **/\nstatic s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data)\n{\n\ts32 status;\n\tu16 word;\n\tu16 page_size;\n\tu16 i;\n\tu8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;\n\n\t/* Prepare the EEPROM for writing */\n\tstatus = ixgbe_acquire_eeprom(hw);\n\n\tif (status == 0) {\n\t\tif (ixgbe_ready_eeprom(hw) != 0) {\n\t\t\tixgbe_release_eeprom(hw);\n\t\t\tstatus = IXGBE_ERR_EEPROM;\n\t\t}\n\t}\n\n\tif (status == 0) {\n\t\tfor (i = 0; i < words; i++) {\n\t\t\tixgbe_standby_eeprom(hw);\n\n\t\t\t/* Send the WRITE ENABLE command (8 bit opcode ) */\n\t\t\tixgbe_shift_out_eeprom_bits(hw,\n\t\t\t\t\t\t IXGBE_EEPROM_WREN_OPCODE_SPI,\n\t\t\t\t\t\t IXGBE_EEPROM_OPCODE_BITS);\n\n\t\t\tixgbe_standby_eeprom(hw);\n\n\t\t\t/*\n\t\t\t * Some SPI eeproms use the 8th address bit embedded\n\t\t\t * in the opcode\n\t\t\t */\n\t\t\tif ((hw->eeprom.address_bits == 8) &&\n\t\t\t ((offset + i) >= 128))\n\t\t\t\twrite_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;\n\n\t\t\t/* Send the Write command (8-bit opcode + addr) */\n\t\t\tixgbe_shift_out_eeprom_bits(hw, write_opcode,\n\t\t\t\t\t\t IXGBE_EEPROM_OPCODE_BITS);\n\t\t\tixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),\n\t\t\t\t\t\t hw->eeprom.address_bits);\n\n\t\t\tpage_size = hw->eeprom.word_page_size;\n\n\t\t\t/* Send the data in burst via SPI*/\n\t\t\tdo {\n\t\t\t\tword = data[i];\n\t\t\t\tword = (word >> 8) | (word << 8);\n\t\t\t\tixgbe_shift_out_eeprom_bits(hw, word, 16);\n\n\t\t\t\tif (page_size == 0)\n\t\t\t\t\tbreak;\n\n\t\t\t\t/* do not wrap around page */\n\t\t\t\tif (((offset + i) & (page_size - 1)) ==\n\t\t\t\t (page_size - 1))\n\t\t\t\t\tbreak;\n\t\t\t} while (++i < words);\n\n\t\t\tixgbe_standby_eeprom(hw);\n\t\t\tmsleep(10);\n\t\t}\n\t\t/* Done with writing - release the EEPROM */\n\t\tixgbe_release_eeprom(hw);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be written to\n * @data: 16 bit word to be written to the EEPROM\n *\n * If ixgbe_eeprom_update_checksum is not called after this function, the\n * EEPROM will most likely contain an invalid checksum.\n **/\ns32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)\n{\n\ts32 status;\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (offset >= hw->eeprom.word_size) {\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t\tgoto out;\n\t}\n\n\tstatus = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be read\n * @data: read 16 bit words(s) from EEPROM\n * @words: number of word(s)\n *\n * Reads 16 bit word(s) from EEPROM through bit-bang method\n **/\ns32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data)\n{\n\ts32 status = 0;\n\tu16 i, count;\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (words == 0) {\n\t\tstatus = IXGBE_ERR_INVALID_ARGUMENT;\n\t\tgoto out;\n\t}\n\n\tif (offset + words > hw->eeprom.word_size) {\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t\tgoto out;\n\t}\n\n\t/*\n\t * We cannot hold synchronization semaphores for too long\n\t * to avoid other entity starvation. However it is more efficient\n\t * to read in bursts than synchronizing access for each word.\n\t */\n\tfor (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {\n\t\tcount = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?\n\t\t\tIXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);\n\n\t\tstatus = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,\n\t\t\t\t\t\t\t count, &data[i]);\n\n\t\tif (status != 0)\n\t\t\tbreak;\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be read\n * @words: number of word(s)\n * @data: read 16 bit word(s) from EEPROM\n *\n * Reads 16 bit word(s) from EEPROM through bit-bang method\n **/\nstatic s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data)\n{\n\ts32 status;\n\tu16 word_in;\n\tu8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;\n\tu16 i;\n\n\t/* Prepare the EEPROM for reading */\n\tstatus = ixgbe_acquire_eeprom(hw);\n\n\tif (status == 0) {\n\t\tif (ixgbe_ready_eeprom(hw) != 0) {\n\t\t\tixgbe_release_eeprom(hw);\n\t\t\tstatus = IXGBE_ERR_EEPROM;\n\t\t}\n\t}\n\n\tif (status == 0) {\n\t\tfor (i = 0; i < words; i++) {\n\t\t\tixgbe_standby_eeprom(hw);\n\t\t\t/*\n\t\t\t * Some SPI eeproms use the 8th address bit embedded\n\t\t\t * in the opcode\n\t\t\t */\n\t\t\tif ((hw->eeprom.address_bits == 8) &&\n\t\t\t ((offset + i) >= 128))\n\t\t\t\tread_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;\n\n\t\t\t/* Send the READ command (opcode + addr) */\n\t\t\tixgbe_shift_out_eeprom_bits(hw, read_opcode,\n\t\t\t\t\t\t IXGBE_EEPROM_OPCODE_BITS);\n\t\t\tixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),\n\t\t\t\t\t\t hw->eeprom.address_bits);\n\n\t\t\t/* Read the data. */\n\t\t\tword_in = ixgbe_shift_in_eeprom_bits(hw, 16);\n\t\t\tdata[i] = (word_in >> 8) | (word_in << 8);\n\t\t}\n\n\t\t/* End this read operation */\n\t\tixgbe_release_eeprom(hw);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be read\n * @data: read 16 bit value from EEPROM\n *\n * Reads 16 bit value from EEPROM through bit-bang method\n **/\ns32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 *data)\n{\n\ts32 status;\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (offset >= hw->eeprom.word_size) {\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t\tgoto out;\n\t}\n\n\tstatus = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @words: number of word(s)\n * @data: 16 bit word(s) from the EEPROM\n *\n * Reads a 16 bit word(s) from the EEPROM using the EERD register.\n **/\ns32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data)\n{\n\tu32 eerd;\n\ts32 status = 0;\n\tu32 i;\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (words == 0) {\n\t\tstatus = IXGBE_ERR_INVALID_ARGUMENT;\n\t\tgoto out;\n\t}\n\n\tif (offset >= hw->eeprom.word_size) {\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < words; i++) {\n\t\teerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +\n\t\t IXGBE_EEPROM_RW_REG_START;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);\n\t\tstatus = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);\n\n\t\tif (status == 0) {\n\t\t\tdata[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>\n\t\t\t\t IXGBE_EEPROM_RW_REG_DATA);\n\t\t} else {\n\t\t\thw_dbg(hw, \"Eeprom read timed out\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size\n * @hw: pointer to hardware structure\n * @offset: offset within the EEPROM to be used as a scratch pad\n *\n * Discover EEPROM page size by writing marching data at given offset.\n * This function is called only when we are writing a new large buffer\n * at given offset so the data would be overwritten anyway.\n **/\nstatic s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t\t u16 offset)\n{\n\tu16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];\n\ts32 status = 0;\n\tu16 i;\n\n\tfor (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)\n\t\tdata[i] = i;\n\n\thw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;\n\tstatus = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,\n\t\t\t\t\t IXGBE_EEPROM_PAGE_SIZE_MAX, data);\n\thw->eeprom.word_page_size = 0;\n\tif (status != 0)\n\t\tgoto out;\n\n\tstatus = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);\n\tif (status != 0)\n\t\tgoto out;\n\n\t/*\n\t * When writing in burst more than the actual page size\n\t * EEPROM address wraps around current page.\n\t */\n\thw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];\n\n\thw_dbg(hw, \"Detected EEPROM page size = %d words.\",\n\t\t hw->eeprom.word_page_size);\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_read_eerd_generic - Read EEPROM word using EERD\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM using the EERD register.\n **/\ns32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)\n{\n\treturn ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);\n}\n\n/**\n * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to write\n * @words: number of word(s)\n * @data: word(s) write to the EEPROM\n *\n * Write a 16 bit word(s) to the EEPROM using the EEWR register.\n **/\ns32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data)\n{\n\tu32 eewr;\n\ts32 status = 0;\n\tu16 i;\n\n\thw->eeprom.ops.init_params(hw);\n\n\tif (words == 0) {\n\t\tstatus = IXGBE_ERR_INVALID_ARGUMENT;\n\t\tgoto out;\n\t}\n\n\tif (offset >= hw->eeprom.word_size) {\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t\tgoto out;\n\t}\n\n\tfor (i = 0; i < words; i++) {\n\t\teewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |\n\t\t\t(data[i] << IXGBE_EEPROM_RW_REG_DATA) |\n\t\t\tIXGBE_EEPROM_RW_REG_START;\n\n\t\tstatus = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);\n\t\tif (status != 0) {\n\t\t\thw_dbg(hw, \"Eeprom write EEWR timed out\\n\");\n\t\t\tgoto out;\n\t\t}\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);\n\n\t\tstatus = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);\n\t\tif (status != 0) {\n\t\t\thw_dbg(hw, \"Eeprom write EEWR timed out\\n\");\n\t\t\tgoto out;\n\t\t}\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_write_eewr_generic - Write EEPROM word using EEWR\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to write\n * @data: word write to the EEPROM\n *\n * Write a 16 bit word to the EEPROM using the EEWR register.\n **/\ns32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)\n{\n\treturn ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);\n}\n\n/**\n * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status\n * @hw: pointer to hardware structure\n * @ee_reg: EEPROM flag for polling\n *\n * Polls the status bit (bit 1) of the EERD or EEWR to determine when the\n * read or write is done respectively.\n **/\ns32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)\n{\n\tu32 i;\n\tu32 reg;\n\ts32 status = IXGBE_ERR_EEPROM;\n\n\tfor (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {\n\t\tif (ee_reg == IXGBE_NVM_POLL_READ)\n\t\t\treg = IXGBE_READ_REG(hw, IXGBE_EERD);\n\t\telse\n\t\t\treg = IXGBE_READ_REG(hw, IXGBE_EEWR);\n\n\t\tif (reg & IXGBE_EEPROM_RW_REG_DONE) {\n\t\t\tstatus = 0;\n\t\t\tbreak;\n\t\t}\n\t\tudelay(5);\n\t}\n\treturn status;\n}\n\n/**\n * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang\n * @hw: pointer to hardware structure\n *\n * Prepares EEPROM for access using bit-bang method. This function should\n * be called before issuing a command to the EEPROM.\n **/\nstatic s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\tu32 eec;\n\tu32 i;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)\n\t != 0)\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\n\tif (status == 0) {\n\t\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\t\t/* Request EEPROM Access */\n\t\teec |= IXGBE_EEC_REQ;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\n\t\tfor (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {\n\t\t\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\t\t\tif (eec & IXGBE_EEC_GNT)\n\t\t\t\tbreak;\n\t\t\tudelay(5);\n\t\t}\n\n\t\t/* Release if grant not acquired */\n\t\tif (!(eec & IXGBE_EEC_GNT)) {\n\t\t\teec &= ~IXGBE_EEC_REQ;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\t\t\thw_dbg(hw, \"Could not acquire EEPROM grant\\n\");\n\n\t\t\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\t\t\tstatus = IXGBE_ERR_EEPROM;\n\t\t}\n\n\t\t/* Setup EEPROM for Read/Write */\n\t\tif (status == 0) {\n\t\t\t/* Clear CS and SK */\n\t\t\teec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\t\t\tIXGBE_WRITE_FLUSH(hw);\n\t\t\tudelay(1);\n\t\t}\n\t}\n\treturn status;\n}\n\n/**\n * ixgbe_get_eeprom_semaphore - Get hardware semaphore\n * @hw: pointer to hardware structure\n *\n * Sets the hardware semaphores so EEPROM access can occur for bit-bang method\n **/\nstatic s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_EEPROM;\n\tu32 timeout = 2000;\n\tu32 i;\n\tu32 swsm;\n\n\t/* Get SMBI software semaphore between device drivers first */\n\tfor (i = 0; i < timeout; i++) {\n\t\t/*\n\t\t * If the SMBI bit is 0 when we read it, then the bit will be\n\t\t * set and we have the semaphore\n\t\t */\n\t\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\t\tif (!(swsm & IXGBE_SWSM_SMBI)) {\n\t\t\tstatus = 0;\n\t\t\tbreak;\n\t\t}\n\t\tudelay(50);\n\t}\n\n\tif (i == timeout) {\n\t\thw_dbg(hw, \"Driver can't access the Eeprom - SMBI Semaphore \"\n\t\t\t \"not granted.\\n\");\n\t\t/*\n\t\t * this release is particularly important because our attempts\n\t\t * above to get the semaphore may have succeeded, and if there\n\t\t * was a timeout, we should unconditionally clear the semaphore\n\t\t * bits to free the driver to make progress\n\t\t */\n\t\tixgbe_release_eeprom_semaphore(hw);\n\n\t\tudelay(50);\n\t\t/*\n\t\t * one last try\n\t\t * If the SMBI bit is 0 when we read it, then the bit will be\n\t\t * set and we have the semaphore\n\t\t */\n\t\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\t\tif (!(swsm & IXGBE_SWSM_SMBI))\n\t\t\tstatus = 0;\n\t}\n\n\t/* Now get the semaphore between SW/FW through the SWESMBI bit */\n\tif (status == 0) {\n\t\tfor (i = 0; i < timeout; i++) {\n\t\t\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\n\t\t\t/* Set the SW EEPROM semaphore bit to request access */\n\t\t\tswsm |= IXGBE_SWSM_SWESMBI;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);\n\n\t\t\t/*\n\t\t\t * If we set the bit successfully then we got the\n\t\t\t * semaphore.\n\t\t\t */\n\t\t\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\t\t\tif (swsm & IXGBE_SWSM_SWESMBI)\n\t\t\t\tbreak;\n\n\t\t\tudelay(50);\n\t\t}\n\n\t\t/*\n\t\t * Release semaphores and return error if SW EEPROM semaphore\n\t\t * was not granted because we don't have access to the EEPROM\n\t\t */\n\t\tif (i >= timeout) {\n\t\t\thw_dbg(hw, \"SWESMBI Software EEPROM semaphore \"\n\t\t\t\t \"not granted.\\n\");\n\t\t\tixgbe_release_eeprom_semaphore(hw);\n\t\t\tstatus = IXGBE_ERR_EEPROM;\n\t\t}\n\t} else {\n\t\thw_dbg(hw, \"Software semaphore SMBI between device drivers \"\n\t\t\t \"not granted.\\n\");\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_release_eeprom_semaphore - Release hardware semaphore\n * @hw: pointer to hardware structure\n *\n * This function clears hardware semaphore bits.\n **/\nstatic void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)\n{\n\tu32 swsm;\n\n\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\n\t/* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */\n\tswsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);\n\tIXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/**\n * ixgbe_ready_eeprom - Polls for EEPROM ready\n * @hw: pointer to hardware structure\n **/\nstatic s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\tu16 i;\n\tu8 spi_stat_reg;\n\n\t/*\n\t * Read \"Status Register\" repeatedly until the LSB is cleared. The\n\t * EEPROM will signal that the command has been completed by clearing\n\t * bit 0 of the internal status register. If it's not cleared within\n\t * 5 milliseconds, then error out.\n\t */\n\tfor (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {\n\t\tixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,\n\t\t\t\t\t IXGBE_EEPROM_OPCODE_BITS);\n\t\tspi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);\n\t\tif (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))\n\t\t\tbreak;\n\n\t\tudelay(5);\n\t\tixgbe_standby_eeprom(hw);\n\t};\n\n\t/*\n\t * On some parts, SPI write time could vary from 0-20mSec on 3.3V\n\t * devices (and only 0-5mSec on 5V devices)\n\t */\n\tif (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {\n\t\thw_dbg(hw, \"SPI EEPROM Status error\\n\");\n\t\tstatus = IXGBE_ERR_EEPROM;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_standby_eeprom - Returns EEPROM to a \"standby\" state\n * @hw: pointer to hardware structure\n **/\nstatic void ixgbe_standby_eeprom(struct ixgbe_hw *hw)\n{\n\tu32 eec;\n\n\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\t/* Toggle CS to flush commands */\n\teec |= IXGBE_EEC_CS;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\tIXGBE_WRITE_FLUSH(hw);\n\tudelay(1);\n\teec &= ~IXGBE_EEC_CS;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\tIXGBE_WRITE_FLUSH(hw);\n\tudelay(1);\n}\n\n/**\n * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.\n * @hw: pointer to hardware structure\n * @data: data to send to the EEPROM\n * @count: number of bits to shift out\n **/\nstatic void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,\n\t\t\t\t\tu16 count)\n{\n\tu32 eec;\n\tu32 mask;\n\tu32 i;\n\n\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\t/*\n\t * Mask is used to shift \"count\" bits of \"data\" out to the EEPROM\n\t * one bit at a time. Determine the starting bit based on count\n\t */\n\tmask = 0x01 << (count - 1);\n\n\tfor (i = 0; i < count; i++) {\n\t\t/*\n\t\t * A \"1\" is shifted out to the EEPROM by setting bit \"DI\" to a\n\t\t * \"1\", and then raising and then lowering the clock (the SK\n\t\t * bit controls the clock input to the EEPROM). A \"0\" is\n\t\t * shifted out to the EEPROM by setting \"DI\" to \"0\" and then\n\t\t * raising and then lowering the clock.\n\t\t */\n\t\tif (data & mask)\n\t\t\teec |= IXGBE_EEC_DI;\n\t\telse\n\t\t\teec &= ~IXGBE_EEC_DI;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\n\t\tudelay(1);\n\n\t\tixgbe_raise_eeprom_clk(hw, &eec);\n\t\tixgbe_lower_eeprom_clk(hw, &eec);\n\n\t\t/*\n\t\t * Shift mask to signify next bit of data to shift in to the\n\t\t * EEPROM\n\t\t */\n\t\tmask = mask >> 1;\n\t};\n\n\t/* We leave the \"DI\" bit set to \"0\" when we leave this routine. */\n\teec &= ~IXGBE_EEC_DI;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/**\n * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM\n * @hw: pointer to hardware structure\n **/\nstatic u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)\n{\n\tu32 eec;\n\tu32 i;\n\tu16 data = 0;\n\n\t/*\n\t * In order to read a register from the EEPROM, we need to shift\n\t * 'count' bits in from the EEPROM. Bits are \"shifted in\" by raising\n\t * the clock input to the EEPROM (setting the SK bit), and then reading\n\t * the value of the \"DO\" bit. During this \"shifting in\" process the\n\t * \"DI\" bit should always be clear.\n\t */\n\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\teec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);\n\n\tfor (i = 0; i < count; i++) {\n\t\tdata = data << 1;\n\t\tixgbe_raise_eeprom_clk(hw, &eec);\n\n\t\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\t\teec &= ~(IXGBE_EEC_DI);\n\t\tif (eec & IXGBE_EEC_DO)\n\t\t\tdata |= 1;\n\n\t\tixgbe_lower_eeprom_clk(hw, &eec);\n\t}\n\n\treturn data;\n}\n\n/**\n * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.\n * @hw: pointer to hardware structure\n * @eec: EEC register's current value\n **/\nstatic void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)\n{\n\t/*\n\t * Raise the clock input to the EEPROM\n\t * (setting the SK bit), then delay\n\t */\n\t*eec = *eec | IXGBE_EEC_SK;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);\n\tIXGBE_WRITE_FLUSH(hw);\n\tudelay(1);\n}\n\n/**\n * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.\n * @hw: pointer to hardware structure\n * @eecd: EECD's current value\n **/\nstatic void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)\n{\n\t/*\n\t * Lower the clock input to the EEPROM (clearing the SK bit), then\n\t * delay\n\t */\n\t*eec = *eec & ~IXGBE_EEC_SK;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);\n\tIXGBE_WRITE_FLUSH(hw);\n\tudelay(1);\n}\n\n/**\n * ixgbe_release_eeprom - Release EEPROM, release semaphores\n * @hw: pointer to hardware structure\n **/\nstatic void ixgbe_release_eeprom(struct ixgbe_hw *hw)\n{\n\tu32 eec;\n\n\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\teec |= IXGBE_EEC_CS; /* Pull CS high */\n\teec &= ~IXGBE_EEC_SK; /* Lower SCK */\n\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\tudelay(1);\n\n\t/* Stop requesting EEPROM access */\n\teec &= ~IXGBE_EEC_REQ;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, eec);\n\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\n\t/* Delay before attempt to obtain semaphore again to allow FW access */\n\tmsleep(hw->eeprom.semaphore_delay);\n}\n\n/**\n * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum\n * @hw: pointer to hardware structure\n **/\nu16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)\n{\n\tu16 i;\n\tu16 j;\n\tu16 checksum = 0;\n\tu16 length = 0;\n\tu16 pointer = 0;\n\tu16 word = 0;\n\n\t/* Include 0x0-0x3F in the checksum */\n\tfor (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {\n\t\tif (hw->eeprom.ops.read(hw, i, &word) != 0) {\n\t\t\thw_dbg(hw, \"EEPROM read failed\\n\");\n\t\t\tbreak;\n\t\t}\n\t\tchecksum += word;\n\t}\n\n\t/* Include all data from pointers except for the fw pointer */\n\tfor (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {\n\t\thw->eeprom.ops.read(hw, i, &pointer);\n\n\t\t/* Make sure the pointer seems valid */\n\t\tif (pointer != 0xFFFF && pointer != 0) {\n\t\t\thw->eeprom.ops.read(hw, pointer, &length);\n\n\t\t\tif (length != 0xFFFF && length != 0) {\n\t\t\t\tfor (j = pointer+1; j <= pointer+length; j++) {\n\t\t\t\t\thw->eeprom.ops.read(hw, j, &word);\n\t\t\t\t\tchecksum += word;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\tchecksum = (u16)IXGBE_EEPROM_SUM - checksum;\n\n\treturn checksum;\n}\n\n/**\n * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum\n * @hw: pointer to hardware structure\n * @checksum_val: calculated checksum\n *\n * Performs checksum calculation and validates the EEPROM checksum. If the\n * caller does not need checksum_val, the value can be NULL.\n **/\ns32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *checksum_val)\n{\n\ts32 status;\n\tu16 checksum;\n\tu16 read_checksum = 0;\n\n\t/*\n\t * Read the first word from the EEPROM. If this times out or fails, do\n\t * not continue or we could be in for a very long wait while every\n\t * EEPROM read fails\n\t */\n\tstatus = hw->eeprom.ops.read(hw, 0, &checksum);\n\n\tif (status == 0) {\n\t\tchecksum = hw->eeprom.ops.calc_checksum(hw);\n\n\t\thw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);\n\n\t\t/*\n\t\t * Verify read checksum from EEPROM is the same as\n\t\t * calculated checksum\n\t\t */\n\t\tif (read_checksum != checksum)\n\t\t\tstatus = IXGBE_ERR_EEPROM_CHECKSUM;\n\n\t\t/* If the user cares, return the calculated checksum */\n\t\tif (checksum_val)\n\t\t\t*checksum_val = checksum;\n\t} else {\n\t\thw_dbg(hw, \"EEPROM read failed\\n\");\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\tu16 checksum;\n\n\t/*\n\t * Read the first word from the EEPROM. If this times out or fails, do\n\t * not continue or we could be in for a very long wait while every\n\t * EEPROM read fails\n\t */\n\tstatus = hw->eeprom.ops.read(hw, 0, &checksum);\n\n\tif (status == 0) {\n\t\tchecksum = hw->eeprom.ops.calc_checksum(hw);\n\t\tstatus = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,\n\t\t\t\t\t checksum);\n\t} else {\n\t\thw_dbg(hw, \"EEPROM read failed\\n\");\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_validate_mac_addr - Validate MAC address\n * @mac_addr: pointer to MAC address.\n *\n * Tests a MAC address to ensure it is a valid Individual Address\n **/\ns32 ixgbe_validate_mac_addr(u8 *mac_addr)\n{\n\ts32 status = 0;\n\n\t/* Make sure it is not a multicast address */\n\tif (IXGBE_IS_MULTICAST(mac_addr)) {\n\t\thw_dbg(hw, \"MAC address is multicast\\n\");\n\t\tstatus = IXGBE_ERR_INVALID_MAC_ADDR;\n\t/* Not a broadcast address */\n\t} else if (IXGBE_IS_BROADCAST(mac_addr)) {\n\t\thw_dbg(hw, \"MAC address is broadcast\\n\");\n\t\tstatus = IXGBE_ERR_INVALID_MAC_ADDR;\n\t/* Reject the zero address */\n\t} else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&\n\t\t mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {\n\t\thw_dbg(hw, \"MAC address is all zeros\\n\");\n\t\tstatus = IXGBE_ERR_INVALID_MAC_ADDR;\n\t}\n\treturn status;\n}\n\n/**\n * ixgbe_set_rar_generic - Set Rx address register\n * @hw: pointer to hardware structure\n * @index: Receive address register to write\n * @addr: Address to put into receive address register\n * @vmdq: VMDq \"set\" or \"pool\" index\n * @enable_addr: set flag that address is active\n *\n * Puts an ethernet address into a receive address register.\n **/\ns32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n\t\t\t u32 enable_addr)\n{\n\tu32 rar_low, rar_high;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\t/* Make sure we are using a valid rar index range */\n\tif (index >= rar_entries) {\n\t\thw_dbg(hw, \"RAR index %d is out of range.\\n\", index);\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\t/* setup VMDq pool selection before this RAR gets enabled */\n\thw->mac.ops.set_vmdq(hw, index, vmdq);\n\n\t/*\n\t * HW expects these in little endian so we reverse the byte\n\t * order from network order (big endian) to little endian\n\t */\n\trar_low = ((u32)addr[0] |\n\t\t ((u32)addr[1] << 8) |\n\t\t ((u32)addr[2] << 16) |\n\t\t ((u32)addr[3] << 24));\n\t/*\n\t * Some parts put the VMDq setting in the extra RAH bits,\n\t * so save everything except the lower 16 bits that hold part\n\t * of the address and the address valid bit.\n\t */\n\trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));\n\trar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);\n\trar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));\n\n\tif (enable_addr != 0)\n\t\trar_high |= IXGBE_RAH_AV;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);\n\tIXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_clear_rar_generic - Remove Rx address register\n * @hw: pointer to hardware structure\n * @index: Receive address register to write\n *\n * Clears an ethernet address from a receive address register.\n **/\ns32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)\n{\n\tu32 rar_high;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\t/* Make sure we are using a valid rar index range */\n\tif (index >= rar_entries) {\n\t\thw_dbg(hw, \"RAR index %d is out of range.\\n\", index);\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\t/*\n\t * Some parts put the VMDq setting in the extra RAH bits,\n\t * so save everything except the lower 16 bits that hold part\n\t * of the address and the address valid bit.\n\t */\n\trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));\n\trar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);\n\n\tIXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);\n\tIXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);\n\n\t/* clear VMDq pool/queue selection for this RAR */\n\thw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_init_rx_addrs_generic - Initializes receive address filters.\n * @hw: pointer to hardware structure\n *\n * Places the MAC address in receive address register 0 and clears the rest\n * of the receive address registers. Clears the multicast table. Assumes\n * the receiver is in reset when the routine is called.\n **/\ns32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)\n{\n\tu32 i;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\t/*\n\t * If the current mac address is valid, assume it is a software override\n\t * to the permanent address.\n\t * Otherwise, use the permanent address from the eeprom.\n\t */\n\tif (ixgbe_validate_mac_addr(hw->mac.addr) ==\n\t IXGBE_ERR_INVALID_MAC_ADDR) {\n\t\t/* Get the MAC address from the RAR0 for later reference */\n\t\thw->mac.ops.get_mac_addr(hw, hw->mac.addr);\n\n\t\thw_dbg(hw, \" Keeping Current RAR0 Addr =%.2X %.2X %.2X \",\n\t\t\t hw->mac.addr[0], hw->mac.addr[1],\n\t\t\t hw->mac.addr[2]);\n\t\thw_dbg(hw, \"%.2X %.2X %.2X\\n\", hw->mac.addr[3],\n\t\t\t hw->mac.addr[4], hw->mac.addr[5]);\n\t} else {\n\t\t/* Setup the receive address. */\n\t\thw_dbg(hw, \"Overriding MAC Address in RAR[0]\\n\");\n\t\thw_dbg(hw, \" New MAC Addr =%.2X %.2X %.2X \",\n\t\t\t hw->mac.addr[0], hw->mac.addr[1],\n\t\t\t hw->mac.addr[2]);\n\t\thw_dbg(hw, \"%.2X %.2X %.2X\\n\", hw->mac.addr[3],\n\t\t\t hw->mac.addr[4], hw->mac.addr[5]);\n\n\t\thw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);\n\n\t\t/* clear VMDq pool/queue selection for RAR 0 */\n\t\thw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);\n\t}\n\thw->addr_ctrl.overflow_promisc = 0;\n\n\thw->addr_ctrl.rar_used_count = 1;\n\n\t/* Zero out the other receive addresses. */\n\thw_dbg(hw, \"Clearing RAR[1-%d]\\n\", rar_entries - 1);\n\tfor (i = 1; i < rar_entries; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);\n\t}\n\n\t/* Clear the MTA */\n\thw->addr_ctrl.mta_in_use = 0;\n\tIXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);\n\n\thw_dbg(hw, \" Clearing MTA\\n\");\n\tfor (i = 0; i < hw->mac.mcft_size; i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);\n\n\tixgbe_init_uta_tables(hw);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_add_uc_addr - Adds a secondary unicast address.\n * @hw: pointer to hardware structure\n * @addr: new address\n *\n * Adds it to unused receive address register or goes into promiscuous mode.\n **/\nvoid ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)\n{\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\tu32 rar;\n\n\thw_dbg(hw, \" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\\n\",\n\t\t addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);\n\n\t/*\n\t * Place this address in the RAR if there is room,\n\t * else put the controller into promiscuous mode\n\t */\n\tif (hw->addr_ctrl.rar_used_count < rar_entries) {\n\t\trar = hw->addr_ctrl.rar_used_count;\n\t\thw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);\n\t\thw_dbg(hw, \"Added a secondary address to RAR[%d]\\n\", rar);\n\t\thw->addr_ctrl.rar_used_count++;\n\t} else {\n\t\thw->addr_ctrl.overflow_promisc++;\n\t}\n\n\thw_dbg(hw, \"ixgbe_add_uc_addr Complete\\n\");\n}\n\n/**\n * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses\n * @hw: pointer to hardware structure\n * @addr_list: the list of new addresses\n * @addr_count: number of addresses\n * @next: iterator function to walk the address list\n *\n * The given list replaces any existing list. Clears the secondary addrs from\n * receive address registers. Uses unused receive address registers for the\n * first secondary addresses, and falls back to promiscuous mode as needed.\n *\n * Drivers using secondary unicast addresses must set user_set_promisc when\n * manually putting the device into promiscuous mode.\n **/\ns32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,\n\t\t\t\t u32 addr_count, ixgbe_mc_addr_itr next)\n{\n\tu8 *addr;\n\tu32 i;\n\tu32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;\n\tu32 uc_addr_in_use;\n\tu32 fctrl;\n\tu32 vmdq;\n\n\t/*\n\t * Clear accounting of old secondary address list,\n\t * don't count RAR[0]\n\t */\n\tuc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;\n\thw->addr_ctrl.rar_used_count -= uc_addr_in_use;\n\thw->addr_ctrl.overflow_promisc = 0;\n\n\t/* Zero out the other receive addresses */\n\thw_dbg(hw, \"Clearing RAR[1-%d]\\n\", uc_addr_in_use+1);\n\tfor (i = 0; i < uc_addr_in_use; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);\n\t}\n\n\t/* Add the new addresses */\n\tfor (i = 0; i < addr_count; i++) {\n\t\thw_dbg(hw, \" Adding the secondary addresses:\\n\");\n\t\taddr = next(hw, &addr_list, &vmdq);\n\t\tixgbe_add_uc_addr(hw, addr, vmdq);\n\t}\n\n\tif (hw->addr_ctrl.overflow_promisc) {\n\t\t/* enable promisc if not already in overflow or set by user */\n\t\tif (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {\n\t\t\thw_dbg(hw, \" Entering address overflow promisc mode\\n\");\n\t\t\tfctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\t\t\tfctrl |= IXGBE_FCTRL_UPE;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);\n\t\t}\n\t} else {\n\t\t/* only disable if set by overflow, not by user */\n\t\tif (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {\n\t\t\thw_dbg(hw, \" Leaving address overflow promisc mode\\n\");\n\t\t\tfctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\t\t\tfctrl &= ~IXGBE_FCTRL_UPE;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);\n\t\t}\n\t}\n\n\thw_dbg(hw, \"ixgbe_update_uc_addr_list_generic Complete\\n\");\n\treturn 0;\n}\n\n/**\n * ixgbe_mta_vector - Determines bit-vector in multicast table to set\n * @hw: pointer to hardware structure\n * @mc_addr: the multicast address\n *\n * Extracts the 12 bits, from a multicast address, to determine which\n * bit-vector to set in the multicast table. The hardware uses 12 bits, from\n * incoming rx multicast addresses, to determine the bit-vector to check in\n * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set\n * by the MO field of the MCSTCTRL. The MO field is set during initialization\n * to mc_filter_type.\n **/\nstatic s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)\n{\n\tu32 vector = 0;\n\n\tswitch (hw->mac.mc_filter_type) {\n\tcase 0: /* use bits [47:36] of the address */\n\t\tvector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));\n\t\tbreak;\n\tcase 1: /* use bits [46:35] of the address */\n\t\tvector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));\n\t\tbreak;\n\tcase 2: /* use bits [45:34] of the address */\n\t\tvector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));\n\t\tbreak;\n\tcase 3: /* use bits [43:32] of the address */\n\t\tvector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));\n\t\tbreak;\n\tdefault: /* Invalid mc_filter_type */\n\t\thw_dbg(hw, \"MC filter type param set incorrectly\\n\");\n\t\tbreak;\n\t}\n\n\t/* vector can only be 12-bits or boundary will be exceeded */\n\tvector &= 0xFFF;\n\treturn vector;\n}\n\n/**\n * ixgbe_set_mta - Set bit-vector in multicast table\n * @hw: pointer to hardware structure\n * @hash_value: Multicast address hash value\n *\n * Sets the bit-vector in the multicast table.\n **/\nvoid ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)\n{\n\tu32 vector;\n\tu32 vector_bit;\n\tu32 vector_reg;\n\n\thw->addr_ctrl.mta_in_use++;\n\n\tvector = ixgbe_mta_vector(hw, mc_addr);\n\thw_dbg(hw, \" bit-vector = 0x%03X\\n\", vector);\n\n\t/*\n\t * The MTA is a register array of 128 32-bit registers. It is treated\n\t * like an array of 4096 bits. We want to set bit\n\t * BitArray[vector_value]. So we figure out what register the bit is\n\t * in, read it, OR in the new bit, then write back the new value. The\n\t * register is determined by the upper 7 bits of the vector value and\n\t * the bit within that register are determined by the lower 5 bits of\n\t * the value.\n\t */\n\tvector_reg = (vector >> 5) & 0x7F;\n\tvector_bit = vector & 0x1F;\n\thw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);\n}\n\n/**\n * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses\n * @hw: pointer to hardware structure\n * @mc_addr_list: the list of new multicast addresses\n * @mc_addr_count: number of addresses\n * @next: iterator function to walk the multicast address list\n * @clear: flag, when set clears the table beforehand\n *\n * When the clear flag is set, the given list replaces any existing list.\n * Hashes the given addresses into the multicast table.\n **/\ns32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,\n\t\t\t\t u32 mc_addr_count, ixgbe_mc_addr_itr next,\n\t\t\t\t bool clear)\n{\n\tu32 i;\n\tu32 vmdq;\n\n\t/*\n\t * Set the new number of MC addresses that we are being requested to\n\t * use.\n\t */\n\thw->addr_ctrl.num_mc_addrs = mc_addr_count;\n\thw->addr_ctrl.mta_in_use = 0;\n\n\t/* Clear mta_shadow */\n\tif (clear) {\n\t\thw_dbg(hw, \" Clearing MTA\\n\");\n\t\tmemset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));\n\t}\n\n\t/* Update mta_shadow */\n\tfor (i = 0; i < mc_addr_count; i++) {\n\t\thw_dbg(hw, \" Adding the multicast addresses:\\n\");\n\t\tixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));\n\t}\n\n\t/* Enable mta */\n\tfor (i = 0; i < hw->mac.mcft_size; i++)\n\t\tIXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,\n\t\t\t\t hw->mac.mta_shadow[i]);\n\n\tif (hw->addr_ctrl.mta_in_use > 0)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,\n\t\t\t\tIXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);\n\n\thw_dbg(hw, \"ixgbe_update_mc_addr_list_generic Complete\\n\");\n\treturn 0;\n}\n\n/**\n * ixgbe_enable_mc_generic - Enable multicast address in RAR\n * @hw: pointer to hardware structure\n *\n * Enables multicast address in RAR and the use of the multicast hash table.\n **/\ns32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_addr_filter_info *a = &hw->addr_ctrl;\n\n\tif (a->mta_in_use > 0)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |\n\t\t\t\thw->mac.mc_filter_type);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_disable_mc_generic - Disable multicast address in RAR\n * @hw: pointer to hardware structure\n *\n * Disables multicast address in RAR and the use of the multicast hash table.\n **/\ns32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_addr_filter_info *a = &hw->addr_ctrl;\n\n\tif (a->mta_in_use > 0)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_fc_enable_generic - Enable flow control\n * @hw: pointer to hardware structure\n *\n * Enable flow control according to the current settings.\n **/\ns32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = 0;\n\tu32 mflcn_reg, fccfg_reg;\n\tu32 reg;\n\tu32 fcrtl, fcrth;\n\tint i;\n\n\t/* Validate the water mark configuration */\n\tif (!hw->fc.pause_time) {\n\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\tgoto out;\n\t}\n\n\t/* Low water mark of zero causes XOFF floods */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tif ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&\n\t\t hw->fc.high_water[i]) {\n\t\t\tif (!hw->fc.low_water[i] ||\n\t\t\t hw->fc.low_water[i] >= hw->fc.high_water[i]) {\n\t\t\t\thw_dbg(hw, \"Invalid water mark configuration\\n\");\n\t\t\t\tret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Negotiate the fc mode to use */\n\tixgbe_fc_autoneg(hw);\n\n\t/* Disable any previous flow control settings */\n\tmflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);\n\tmflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);\n\n\tfccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);\n\tfccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);\n\n\t/*\n\t * The possible values of fc.current_mode are:\n\t * 0: Flow control is completely disabled\n\t * 1: Rx flow control is enabled (we can receive pause frames,\n\t * but not send pause frames).\n\t * 2: Tx flow control is enabled (we can send pause frames but\n\t * we do not support receiving pause frames).\n\t * 3: Both Rx and Tx flow control (symmetric) are enabled.\n\t * other: Invalid.\n\t */\n\tswitch (hw->fc.current_mode) {\n\tcase ixgbe_fc_none:\n\t\t/*\n\t\t * Flow control is disabled by software override or autoneg.\n\t\t * The code below will actually disable it in the HW.\n\t\t */\n\t\tbreak;\n\tcase ixgbe_fc_rx_pause:\n\t\t/*\n\t\t * Rx Flow control is enabled and Tx Flow control is\n\t\t * disabled by software override. Since there really\n\t\t * isn't a way to advertise that we are capable of RX\n\t\t * Pause ONLY, we will advertise that we support both\n\t\t * symmetric and asymmetric Rx PAUSE. Later, we will\n\t\t * disable the adapter's ability to send PAUSE frames.\n\t\t */\n\t\tmflcn_reg |= IXGBE_MFLCN_RFCE;\n\t\tbreak;\n\tcase ixgbe_fc_tx_pause:\n\t\t/*\n\t\t * Tx Flow control is enabled, and Rx Flow control is\n\t\t * disabled by software override.\n\t\t */\n\t\tfccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;\n\t\tbreak;\n\tcase ixgbe_fc_full:\n\t\t/* Flow control (both Rx and Tx) is enabled by SW override. */\n\t\tmflcn_reg |= IXGBE_MFLCN_RFCE;\n\t\tfccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;\n\t\tbreak;\n\tdefault:\n\t\thw_dbg(hw, \"Flow control param set incorrectly\\n\");\n\t\tret_val = IXGBE_ERR_CONFIG;\n\t\tgoto out;\n\t\tbreak;\n\t}\n\n\t/* Set 802.3x based flow control settings. */\n\tmflcn_reg |= IXGBE_MFLCN_DPF;\n\tIXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);\n\tIXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);\n\n\n\t/* Set up and enable Rx high/low water mark thresholds, enable XON. */\n\tfor (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {\n\t\tif ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&\n\t\t hw->fc.high_water[i]) {\n\t\t\tfcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);\n\t\t\tfcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;\n\t\t} else {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);\n\t\t\t/*\n\t\t\t * In order to prevent Tx hangs when the internal Tx\n\t\t\t * switch is enabled we must set the high water mark\n\t\t\t * to the maximum FCRTH value. This allows the Tx\n\t\t\t * switch to function even under heavy Rx workloads.\n\t\t\t */\n\t\t\tfcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;\n\t\t}\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);\n\t}\n\n\t/* Configure pause time (2 TCs per register) */\n\treg = hw->fc.pause_time * 0x00010001;\n\tfor (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);\n\n\t/* Configure flow control refresh threshold value */\n\tIXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_negotiate_fc - Negotiate flow control\n * @hw: pointer to hardware structure\n * @adv_reg: flow control advertised settings\n * @lp_reg: link partner's flow control settings\n * @adv_sym: symmetric pause bit in advertisement\n * @adv_asm: asymmetric pause bit in advertisement\n * @lp_sym: symmetric pause bit in link partner advertisement\n * @lp_asm: asymmetric pause bit in link partner advertisement\n *\n * Find the intersection between advertised settings and link partner's\n * advertised settings\n **/\nstatic s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,\n\t\t\t u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)\n{\n\tif ((!(adv_reg)) || (!(lp_reg)))\n\t\treturn IXGBE_ERR_FC_NOT_NEGOTIATED;\n\n\tif ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {\n\t\t/*\n\t\t * Now we need to check if the user selected Rx ONLY\n\t\t * of pause frames. In this case, we had to advertise\n\t\t * FULL flow control because we could not advertise RX\n\t\t * ONLY. Hence, we must now check to see if we need to\n\t\t * turn OFF the TRANSMISSION of PAUSE frames.\n\t\t */\n\t\tif (hw->fc.requested_mode == ixgbe_fc_full) {\n\t\t\thw->fc.current_mode = ixgbe_fc_full;\n\t\t\thw_dbg(hw, \"Flow Control = FULL.\\n\");\n\t\t} else {\n\t\t\thw->fc.current_mode = ixgbe_fc_rx_pause;\n\t\t\thw_dbg(hw, \"Flow Control=RX PAUSE frames only\\n\");\n\t\t}\n\t} else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&\n\t\t (lp_reg & lp_sym) && (lp_reg & lp_asm)) {\n\t\thw->fc.current_mode = ixgbe_fc_tx_pause;\n\t\thw_dbg(hw, \"Flow Control = TX PAUSE frames only.\\n\");\n\t} else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&\n\t\t !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {\n\t\thw->fc.current_mode = ixgbe_fc_rx_pause;\n\t\thw_dbg(hw, \"Flow Control = RX PAUSE frames only.\\n\");\n\t} else {\n\t\thw->fc.current_mode = ixgbe_fc_none;\n\t\thw_dbg(hw, \"Flow Control = NONE.\\n\");\n\t}\n\treturn 0;\n}\n\n/**\n * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber\n * @hw: pointer to hardware structure\n *\n * Enable flow control according on 1 gig fiber.\n **/\nstatic s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)\n{\n\tu32 pcs_anadv_reg, pcs_lpab_reg, linkstat;\n\ts32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;\n\n\t/*\n\t * On multispeed fiber at 1g, bail out if\n\t * - link is up but AN did not complete, or if\n\t * - link is up and AN completed but timed out\n\t */\n\n\tlinkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);\n\tif ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||\n\t (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))\n\t\tgoto out;\n\n\tpcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);\n\tpcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);\n\n\tret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,\n\t\t\t\t pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,\n\t\t\t\t IXGBE_PCS1GANA_ASM_PAUSE,\n\t\t\t\t IXGBE_PCS1GANA_SYM_PAUSE,\n\t\t\t\t IXGBE_PCS1GANA_ASM_PAUSE);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37\n * @hw: pointer to hardware structure\n *\n * Enable flow control according to IEEE clause 37.\n **/\nstatic s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)\n{\n\tu32 links2, anlp1_reg, autoc_reg, links;\n\ts32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;\n\n\t/*\n\t * On backplane, bail out if\n\t * - backplane autoneg was not completed, or if\n\t * - we are 82599 and link partner is not AN enabled\n\t */\n\tlinks = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\tif ((links & IXGBE_LINKS_KX_AN_COMP) == 0)\n\t\tgoto out;\n\n\tif (hw->mac.type == ixgbe_mac_82599EB) {\n\t\tlinks2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);\n\t\tif ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)\n\t\t\tgoto out;\n\t}\n\t/*\n\t * Read the 10g AN autoc and LP ability registers and resolve\n\t * local flow control settings accordingly\n\t */\n\tautoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tanlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);\n\n\tret_val = ixgbe_negotiate_fc(hw, autoc_reg,\n\t\tanlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,\n\t\tIXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37\n * @hw: pointer to hardware structure\n *\n * Enable flow control according to IEEE clause 37.\n **/\nstatic s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)\n{\n\tu16 technology_ability_reg = 0;\n\tu16 lp_technology_ability_reg = 0;\n\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t &technology_ability_reg);\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t &lp_technology_ability_reg);\n\n\treturn ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,\n\t\t\t\t (u32)lp_technology_ability_reg,\n\t\t\t\t IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,\n\t\t\t\t IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);\n}\n\n/**\n * ixgbe_fc_autoneg - Configure flow control\n * @hw: pointer to hardware structure\n *\n * Compares our advertised flow control capabilities to those advertised by\n * our link partner, and determines the proper flow control mode to use.\n **/\nvoid ixgbe_fc_autoneg(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;\n\tixgbe_link_speed speed;\n\tbool link_up;\n\n\t/*\n\t * AN should have completed when the cable was plugged in.\n\t * Look for reasons to bail out. Bail out if:\n\t * - FC autoneg is disabled, or if\n\t * - link is not up.\n\t */\n\tif (hw->fc.disable_fc_autoneg)\n\t\tgoto out;\n\n\thw->mac.ops.check_link(hw, &speed, &link_up, false);\n\tif (!link_up)\n\t\tgoto out;\n\n\tswitch (hw->phy.media_type) {\n\t/* Autoneg flow control on fiber adapters */\n\tcase ixgbe_media_type_fiber:\n\t\tif (speed == IXGBE_LINK_SPEED_1GB_FULL)\n\t\t\tret_val = ixgbe_fc_autoneg_fiber(hw);\n\t\tbreak;\n\n\t/* Autoneg flow control on backplane adapters */\n\tcase ixgbe_media_type_backplane:\n\t\tret_val = ixgbe_fc_autoneg_backplane(hw);\n\t\tbreak;\n\n\t/* Autoneg flow control on copper adapters */\n\tcase ixgbe_media_type_copper:\n\t\tif (ixgbe_device_supports_autoneg_fc(hw) == 0)\n\t\t\tret_val = ixgbe_fc_autoneg_copper(hw);\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\t}\n\nout:\n\tif (ret_val == 0) {\n\t\thw->fc.fc_was_autonegged = true;\n\t} else {\n\t\thw->fc.fc_was_autonegged = false;\n\t\thw->fc.current_mode = hw->fc.requested_mode;\n\t}\n}\n\n/**\n * ixgbe_disable_pcie_master - Disable PCI-express master access\n * @hw: pointer to hardware structure\n *\n * Disables PCI-Express master access and verifies there are no pending\n * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable\n * bit hasn't caused the master requests to be disabled, else 0\n * is returned signifying master requests disabled.\n **/\ns32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\tu32 i;\n\n\t/* Always set this bit to ensure any future transactions are blocked */\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);\n\n\t/* Exit if master requets are blocked */\n\tif (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))\n\t\tgoto out;\n\n\t/* Poll for master request bit to clear */\n\tfor (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {\n\t\tudelay(100);\n\t\tif (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))\n\t\t\tgoto out;\n\t}\n\n\t/*\n\t * Two consecutive resets are required via CTRL.RST per datasheet\n\t * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine\n\t * of this need. The first reset prevents new master requests from\n\t * being issued by our device. We then must wait 1usec or more for any\n\t * remaining completions from the PCIe bus to trickle in, and then reset\n\t * again to clear out any effects they may have had on our device.\n\t */\n\thw_dbg(hw, \"GIO Master Disable bit didn't clear - requesting resets\\n\");\n\thw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;\n\n\t/*\n\t * Before proceeding, make sure that the PCIe block does not have\n\t * transactions pending.\n\t */\n\tfor (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {\n\t\tudelay(100);\n\t\tif (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &\n\t\t IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))\n\t\t\tgoto out;\n\t}\n\n\thw_dbg(hw, \"PCIe transaction pending bit also did not clear.\\n\");\n\tstatus = IXGBE_ERR_MASTER_REQUESTS_PENDING;\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to acquire\n *\n * Acquires the SWFW semaphore through the GSSR register for the specified\n * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\ns32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)\n{\n\tu32 gssr;\n\tu32 swmask = mask;\n\tu32 fwmask = mask << 5;\n\ts32 timeout = 200;\n\n\twhile (timeout) {\n\t\t/*\n\t\t * SW EEPROM semaphore bit is used for access to all\n\t\t * SW_FW_SYNC/GSSR bits (not just EEPROM)\n\t\t */\n\t\tif (ixgbe_get_eeprom_semaphore(hw))\n\t\t\treturn IXGBE_ERR_SWFW_SYNC;\n\n\t\tgssr = IXGBE_READ_REG(hw, IXGBE_GSSR);\n\t\tif (!(gssr & (fwmask | swmask)))\n\t\t\tbreak;\n\n\t\t/*\n\t\t * Firmware currently using resource (fwmask) or other software\n\t\t * thread currently using resource (swmask)\n\t\t */\n\t\tixgbe_release_eeprom_semaphore(hw);\n\t\tmsleep(5);\n\t\ttimeout--;\n\t}\n\n\tif (!timeout) {\n\t\thw_dbg(hw, \"Driver can't access resource, SW_FW_SYNC timeout.\\n\");\n\t\treturn IXGBE_ERR_SWFW_SYNC;\n\t}\n\n\tgssr |= swmask;\n\tIXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);\n\n\tixgbe_release_eeprom_semaphore(hw);\n\treturn 0;\n}\n\n/**\n * ixgbe_release_swfw_sync - Release SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to release\n *\n * Releases the SWFW semaphore through the GSSR register for the specified\n * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\nvoid ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)\n{\n\tu32 gssr;\n\tu32 swmask = mask;\n\n\tixgbe_get_eeprom_semaphore(hw);\n\n\tgssr = IXGBE_READ_REG(hw, IXGBE_GSSR);\n\tgssr &= ~swmask;\n\tIXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);\n\n\tixgbe_release_eeprom_semaphore(hw);\n}\n\n/**\n * ixgbe_disable_sec_rx_path_generic - Stops the receive data path\n * @hw: pointer to hardware structure\n *\n * Stops the receive data path and waits for the HW to internally empty\n * the Rx security block\n **/\ns32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)\n{\n#define IXGBE_MAX_SECRX_POLL 40\n\n\tint i;\n\tint secrxreg;\n\n\tsecrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);\n\tsecrxreg |= IXGBE_SECRXCTRL_RX_DIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);\n\tfor (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {\n\t\tsecrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);\n\t\tif (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)\n\t\t\tbreak;\n\t\telse\n\t\t\t/* Use interrupt-safe sleep just in case */\n\t\t\tudelay(1000);\n\t}\n\n\t/* For informational purposes only */\n\tif (i >= IXGBE_MAX_SECRX_POLL)\n\t\thw_dbg(hw, \"Rx unit being enabled before security \"\n\t\t\t \"path fully disabled. Continuing with init.\\n\");\n\n\treturn 0;\n}\n\n/**\n * ixgbe_enable_sec_rx_path_generic - Enables the receive data path\n * @hw: pointer to hardware structure\n *\n * Enables the receive data path.\n **/\ns32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)\n{\n\tint secrxreg;\n\n\tsecrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);\n\tsecrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;\n\tIXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit\n * @hw: pointer to hardware structure\n * @regval: register value to write to RXCTRL\n *\n * Enables the Rx DMA unit\n **/\ns32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)\n{\n\tIXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_blink_led_start_generic - Blink LED based on index.\n * @hw: pointer to hardware structure\n * @index: led number to blink\n **/\ns32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)\n{\n\tixgbe_link_speed speed = 0;\n\tbool link_up = 0;\n\tu32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tu32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\n\t/*\n\t * Link must be up to auto-blink the LEDs;\n\t * Force it if link is down.\n\t */\n\thw->mac.ops.check_link(hw, &speed, &link_up, false);\n\n\tif (!link_up) {\n\t\tautoc_reg |= IXGBE_AUTOC_AN_RESTART;\n\t\tautoc_reg |= IXGBE_AUTOC_FLU;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t\tmsleep(10);\n\t}\n\n\tled_reg &= ~IXGBE_LED_MODE_MASK(index);\n\tled_reg |= IXGBE_LED_BLINK(index);\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.\n * @hw: pointer to hardware structure\n * @index: led number to stop blinking\n **/\ns32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)\n{\n\tu32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tu32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\n\tautoc_reg &= ~IXGBE_AUTOC_FLU;\n\tautoc_reg |= IXGBE_AUTOC_AN_RESTART;\n\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);\n\n\tled_reg &= ~IXGBE_LED_MODE_MASK(index);\n\tled_reg &= ~IXGBE_LED_BLINK(index);\n\tled_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM\n * @hw: pointer to hardware structure\n * @san_mac_offset: SAN MAC address offset\n *\n * This function will read the EEPROM location for the SAN MAC address\n * pointer, and returns the value at that location. This is used in both\n * get and set mac_addr routines.\n **/\nstatic s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *san_mac_offset)\n{\n\t/*\n\t * First read the EEPROM pointer to see if the MAC addresses are\n\t * available.\n\t */\n\thw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM\n * @hw: pointer to hardware structure\n * @san_mac_addr: SAN MAC address\n *\n * Reads the SAN MAC address from the EEPROM, if it's available. This is\n * per-port, so set_lan_id() must be called before reading the addresses.\n * set_lan_id() is called by identify_sfp(), but this cannot be relied\n * upon for non-SFP connections, so we must call it here.\n **/\ns32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)\n{\n\tu16 san_mac_data, san_mac_offset;\n\tu8 i;\n\n\t/*\n\t * First read the EEPROM pointer to see if the MAC addresses are\n\t * available. If they're not, no point in calling set_lan_id() here.\n\t */\n\tixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);\n\n\tif ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {\n\t\t/*\n\t\t * No addresses available in this EEPROM. It's not an\n\t\t * error though, so just wipe the local address and return.\n\t\t */\n\t\tfor (i = 0; i < 6; i++)\n\t\t\tsan_mac_addr[i] = 0xFF;\n\n\t\tgoto san_mac_addr_out;\n\t}\n\n\t/* make sure we know which port we need to program */\n\thw->mac.ops.set_lan_id(hw);\n\t/* apply the port offset to the address offset */\n\t(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :\n\t\t\t (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);\n\tfor (i = 0; i < 3; i++) {\n\t\thw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);\n\t\tsan_mac_addr[i * 2] = (u8)(san_mac_data);\n\t\tsan_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);\n\t\tsan_mac_offset++;\n\t}\n\nsan_mac_addr_out:\n\treturn 0;\n}\n\n/**\n * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM\n * @hw: pointer to hardware structure\n * @san_mac_addr: SAN MAC address\n *\n * Write a SAN MAC address to the EEPROM.\n **/\ns32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)\n{\n\ts32 status = 0;\n\tu16 san_mac_data, san_mac_offset;\n\tu8 i;\n\n\t/* Look for SAN mac address pointer. If not defined, return */\n\tixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);\n\n\tif ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {\n\t\tstatus = IXGBE_ERR_NO_SAN_ADDR_PTR;\n\t\tgoto san_mac_addr_out;\n\t}\n\n\t/* Make sure we know which port we need to write */\n\thw->mac.ops.set_lan_id(hw);\n\t/* Apply the port offset to the address offset */\n\t(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :\n\t\t\t (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);\n\n\tfor (i = 0; i < 3; i++) {\n\t\tsan_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);\n\t\tsan_mac_data |= (u16)(san_mac_addr[i * 2]);\n\t\thw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);\n\t\tsan_mac_offset++;\n\t}\n\nsan_mac_addr_out:\n\treturn status;\n}\n\n/**\n * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count\n * @hw: pointer to hardware structure\n *\n * Read PCIe configuration space, and get the MSI-X vector count from\n * the capabilities table.\n **/\nu16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)\n{\n\tu16 msix_count = 1;\n\tu16 max_msix_count;\n\tu16 pcie_offset;\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tpcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;\n\t\tmax_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\t\tpcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;\n\t\tmax_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;\n\t\tbreak;\n\tdefault:\n\t\treturn msix_count;\n\t}\n\n\tmsix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);\n\tmsix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;\n\n\t/* MSI-X count is zero-based in HW */\n\tmsix_count++;\n\n\tif (msix_count > max_msix_count)\n\t\tmsix_count = max_msix_count;\n\n\treturn msix_count;\n}\n\n/**\n * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address\n * @hw: pointer to hardware structure\n * @addr: Address to put into receive address register\n * @vmdq: VMDq pool to assign\n *\n * Puts an ethernet address into a receive address register, or\n * finds the rar that it is aleady in; adds to the pool list\n **/\ns32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)\n{\n\tstatic const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;\n\tu32 first_empty_rar = NO_EMPTY_RAR_FOUND;\n\tu32 rar;\n\tu32 rar_low, rar_high;\n\tu32 addr_low, addr_high;\n\n\t/* swap bytes for HW little endian */\n\taddr_low = addr[0] | (addr[1] << 8)\n\t\t\t | (addr[2] << 16)\n\t\t\t | (addr[3] << 24);\n\taddr_high = addr[4] | (addr[5] << 8);\n\n\t/*\n\t * Either find the mac_id in rar or find the first empty space.\n\t * rar_highwater points to just after the highest currently used\n\t * rar in order to shorten the search. It grows when we add a new\n\t * rar to the top.\n\t */\n\tfor (rar = 0; rar < hw->mac.rar_highwater; rar++) {\n\t\trar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));\n\n\t\tif (((IXGBE_RAH_AV & rar_high) == 0)\n\t\t && first_empty_rar == NO_EMPTY_RAR_FOUND) {\n\t\t\tfirst_empty_rar = rar;\n\t\t} else if ((rar_high & 0xFFFF) == addr_high) {\n\t\t\trar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));\n\t\t\tif (rar_low == addr_low)\n\t\t\t\tbreak; /* found it already in the rars */\n\t\t}\n\t}\n\n\tif (rar < hw->mac.rar_highwater) {\n\t\t/* already there so just add to the pool bits */\n\t\tixgbe_set_vmdq(hw, rar, vmdq);\n\t} else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {\n\t\t/* stick it into first empty RAR slot we found */\n\t\trar = first_empty_rar;\n\t\tixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);\n\t} else if (rar == hw->mac.rar_highwater) {\n\t\t/* add it to the top of the list and inc the highwater mark */\n\t\tixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);\n\t\thw->mac.rar_highwater++;\n\t} else if (rar >= hw->mac.num_rar_entries) {\n\t\treturn IXGBE_ERR_INVALID_MAC_ADDR;\n\t}\n\n\t/*\n\t * If we found rar[0], make sure the default pool bit (we use pool 0)\n\t * remains cleared to be sure default pool packets will get delivered\n\t */\n\tif (rar == 0)\n\t\tixgbe_clear_vmdq(hw, rar, 0);\n\n\treturn rar;\n}\n\n/**\n * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address\n * @hw: pointer to hardware struct\n * @rar: receive address register index to disassociate\n * @vmdq: VMDq pool index to remove from the rar\n **/\ns32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n{\n\tu32 mpsar_lo, mpsar_hi;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\t/* Make sure we are using a valid rar index range */\n\tif (rar >= rar_entries) {\n\t\thw_dbg(hw, \"RAR index %d is out of range.\\n\", rar);\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\tmpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));\n\tmpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));\n\n\tif (!mpsar_lo && !mpsar_hi)\n\t\tgoto done;\n\n\tif (vmdq == IXGBE_CLEAR_VMDQ_ALL) {\n\t\tif (mpsar_lo) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);\n\t\t\tmpsar_lo = 0;\n\t\t}\n\t\tif (mpsar_hi) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);\n\t\t\tmpsar_hi = 0;\n\t\t}\n\t} else if (vmdq < 32) {\n\t\tmpsar_lo &= ~(1 << vmdq);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);\n\t} else {\n\t\tmpsar_hi &= ~(1 << (vmdq - 32));\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);\n\t}\n\n\t/* was that the last pool using this rar? */\n\tif (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)\n\t\thw->mac.ops.clear_rar(hw, rar);\ndone:\n\treturn 0;\n}\n\n/**\n * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address\n * @hw: pointer to hardware struct\n * @rar: receive address register index to associate with a VMDq index\n * @vmdq: VMDq pool index\n **/\ns32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)\n{\n\tu32 mpsar;\n\tu32 rar_entries = hw->mac.num_rar_entries;\n\n\t/* Make sure we are using a valid rar index range */\n\tif (rar >= rar_entries) {\n\t\thw_dbg(hw, \"RAR index %d is out of range.\\n\", rar);\n\t\treturn IXGBE_ERR_INVALID_ARGUMENT;\n\t}\n\n\tif (vmdq < 32) {\n\t\tmpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));\n\t\tmpsar |= 1 << vmdq;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);\n\t} else {\n\t\tmpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));\n\t\tmpsar |= 1 << (vmdq - 32);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);\n\t}\n\treturn 0;\n}\n\n/**\n * This function should only be involved in the IOV mode.\n * In IOV mode, Default pool is next pool after the number of\n * VFs advertized and not 0.\n * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]\n *\n * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address\n * @hw: pointer to hardware struct\n * @vmdq: VMDq pool index\n **/\ns32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)\n{\n\tu32 mpsar;\n\tu32 rar = hw->mac.san_mac_rar_index;\n\n\tif (vmdq < 32) {\n\t\tmpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));\n\t\tmpsar |= 1 << vmdq;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);\n\t} else {\n\t\tmpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));\n\t\tmpsar |= 1 << (vmdq - 32);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)\n{\n\tint i;\n\n\thw_dbg(hw, \" Clearing UTA\\n\");\n\n\tfor (i = 0; i < 128; i++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot\n * @hw: pointer to hardware structure\n * @vlan: VLAN id to write to VLAN filter\n *\n * return the VLVF index where this VLAN id should be placed\n *\n **/\ns32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)\n{\n\tu32 bits = 0;\n\tu32 first_empty_slot = 0;\n\ts32 regindex;\n\n\t/* short cut the special case */\n\tif (vlan == 0)\n\t\treturn 0;\n\n\t/*\n\t * Search for the vlan id in the VLVF entries. Save off the first empty\n\t * slot found along the way\n\t */\n\tfor (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {\n\t\tbits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));\n\t\tif (!bits && !(first_empty_slot))\n\t\t\tfirst_empty_slot = regindex;\n\t\telse if ((bits & 0x0FFF) == vlan)\n\t\t\tbreak;\n\t}\n\n\t/*\n\t * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan\n\t * in the VLVF. Else use the first empty VLVF register for this\n\t * vlan id.\n\t */\n\tif (regindex >= IXGBE_VLVF_ENTRIES) {\n\t\tif (first_empty_slot)\n\t\t\tregindex = first_empty_slot;\n\t\telse {\n\t\t\thw_dbg(hw, \"No space in VLVF.\\n\");\n\t\t\tregindex = IXGBE_ERR_NO_SPACE;\n\t\t}\n\t}\n\n\treturn regindex;\n}\n\n/**\n * ixgbe_set_vfta_generic - Set VLAN filter table\n * @hw: pointer to hardware structure\n * @vlan: VLAN id to write to VLAN filter\n * @vind: VMDq output index that maps queue to VLAN id in VFVFB\n * @vlan_on: boolean flag to turn on/off VLAN in VFVF\n *\n * Turn on/off specified VLAN in the VLAN filter table.\n **/\ns32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n\t\t\t bool vlan_on)\n{\n\ts32 regindex;\n\tu32 bitindex;\n\tu32 vfta;\n\tu32 targetbit;\n\ts32 ret_val = 0;\n\tbool vfta_changed = false;\n\n\tif (vlan > 4095)\n\t\treturn IXGBE_ERR_PARAM;\n\n\t/*\n\t * this is a 2 part operation - first the VFTA, then the\n\t * VLVF and VLVFB if VT Mode is set\n\t * We don't write the VFTA until we know the VLVF part succeeded.\n\t */\n\n\t/* Part 1\n\t * The VFTA is a bitstring made up of 128 32-bit registers\n\t * that enable the particular VLAN id, much like the MTA:\n\t * bits[11-5]: which register\n\t * bits[4-0]: which bit in the register\n\t */\n\tregindex = (vlan >> 5) & 0x7F;\n\tbitindex = vlan & 0x1F;\n\ttargetbit = (1 << bitindex);\n\tvfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));\n\n\tif (vlan_on) {\n\t\tif (!(vfta & targetbit)) {\n\t\t\tvfta |= targetbit;\n\t\t\tvfta_changed = true;\n\t\t}\n\t} else {\n\t\tif ((vfta & targetbit)) {\n\t\t\tvfta &= ~targetbit;\n\t\t\tvfta_changed = true;\n\t\t}\n\t}\n\n\t/* Part 2\n\t * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF\n\t */\n\tret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,\n\t\t\t\t\t &vfta_changed);\n\tif (ret_val != 0)\n\t\treturn ret_val;\n\n\tif (vfta_changed)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_set_vlvf_generic - Set VLAN Pool Filter\n * @hw: pointer to hardware structure\n * @vlan: VLAN id to write to VLAN filter\n * @vind: VMDq output index that maps queue to VLAN id in VFVFB\n * @vlan_on: boolean flag to turn on/off VLAN in VFVF\n * @vfta_changed: pointer to boolean flag which indicates whether VFTA\n * should be changed\n *\n * Turn on/off specified bit in VLVF table.\n **/\ns32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n\t\t\t bool vlan_on, bool *vfta_changed)\n{\n\tu32 vt;\n\n\tif (vlan > 4095)\n\t\treturn IXGBE_ERR_PARAM;\n\n\t/* If VT Mode is set\n\t * Either vlan_on\n\t * make sure the vlan is in VLVF\n\t * set the vind bit in the matching VLVFB\n\t * Or !vlan_on\n\t * clear the pool bit and possibly the vind\n\t */\n\tvt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);\n\tif (vt & IXGBE_VT_CTL_VT_ENABLE) {\n\t\ts32 vlvf_index;\n\t\tu32 bits;\n\n\t\tvlvf_index = ixgbe_find_vlvf_slot(hw, vlan);\n\t\tif (vlvf_index < 0)\n\t\t\treturn vlvf_index;\n\n\t\tif (vlan_on) {\n\t\t\t/* set the pool bit */\n\t\t\tif (vind < 32) {\n\t\t\t\tbits = IXGBE_READ_REG(hw,\n\t\t\t\t\t\tIXGBE_VLVFB(vlvf_index * 2));\n\t\t\t\tbits |= (1 << vind);\n\t\t\t\tIXGBE_WRITE_REG(hw,\n\t\t\t\t\t\tIXGBE_VLVFB(vlvf_index * 2),\n\t\t\t\t\t\tbits);\n\t\t\t} else {\n\t\t\t\tbits = IXGBE_READ_REG(hw,\n\t\t\t\t\tIXGBE_VLVFB((vlvf_index * 2) + 1));\n\t\t\t\tbits |= (1 << (vind - 32));\n\t\t\t\tIXGBE_WRITE_REG(hw,\n\t\t\t\t\tIXGBE_VLVFB((vlvf_index * 2) + 1),\n\t\t\t\t\tbits);\n\t\t\t}\n\t\t} else {\n\t\t\t/* clear the pool bit */\n\t\t\tif (vind < 32) {\n\t\t\t\tbits = IXGBE_READ_REG(hw,\n\t\t\t\t\t\tIXGBE_VLVFB(vlvf_index * 2));\n\t\t\t\tbits &= ~(1 << vind);\n\t\t\t\tIXGBE_WRITE_REG(hw,\n\t\t\t\t\t\tIXGBE_VLVFB(vlvf_index * 2),\n\t\t\t\t\t\tbits);\n\t\t\t\tbits |= IXGBE_READ_REG(hw,\n\t\t\t\t\tIXGBE_VLVFB((vlvf_index * 2) + 1));\n\t\t\t} else {\n\t\t\t\tbits = IXGBE_READ_REG(hw,\n\t\t\t\t\tIXGBE_VLVFB((vlvf_index * 2) + 1));\n\t\t\t\tbits &= ~(1 << (vind - 32));\n\t\t\t\tIXGBE_WRITE_REG(hw,\n\t\t\t\t\tIXGBE_VLVFB((vlvf_index * 2) + 1),\n\t\t\t\t\tbits);\n\t\t\t\tbits |= IXGBE_READ_REG(hw,\n\t\t\t\t\t\tIXGBE_VLVFB(vlvf_index * 2));\n\t\t\t}\n\t\t}\n\n\t\t/*\n\t\t * If there are still bits set in the VLVFB registers\n\t\t * for the VLAN ID indicated we need to see if the\n\t\t * caller is requesting that we clear the VFTA entry bit.\n\t\t * If the caller has requested that we clear the VFTA\n\t\t * entry bit but there are still pools/VFs using this VLAN\n\t\t * ID entry then ignore the request. We're not worried\n\t\t * about the case where we're turning the VFTA VLAN ID\n\t\t * entry bit on, only when requested to turn it off as\n\t\t * there may be multiple pools and/or VFs using the\n\t\t * VLAN ID entry. In that case we cannot clear the\n\t\t * VFTA bit until all pools/VFs using that VLAN ID have also\n\t\t * been cleared. This will be indicated by \"bits\" being\n\t\t * zero.\n\t\t */\n\t\tif (bits) {\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),\n\t\t\t\t\t(IXGBE_VLVF_VIEN | vlan));\n\t\t\tif ((!vlan_on) && (vfta_changed != NULL)) {\n\t\t\t\t/* someone wants to clear the vfta entry\n\t\t\t\t * but some pools/VFs are still using it.\n\t\t\t\t * Ignore it. */\n\t\t\t\t*vfta_changed = false;\n\t\t\t}\n\t\t} else\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_clear_vfta_generic - Clear VLAN filter table\n * @hw: pointer to hardware structure\n *\n * Clears the VLAN filer table, and the VMDq index associated with the filter\n **/\ns32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)\n{\n\tu32 offset;\n\n\tfor (offset = 0; offset < hw->mac.vft_size; offset++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);\n\n\tfor (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_check_mac_link_generic - Determine link and speed status\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @link_up: true when link is up\n * @link_up_wait_to_complete: bool used to wait for link up or not\n *\n * Reads the links register to determine if link is up and the current speed\n **/\ns32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t\t bool *link_up, bool link_up_wait_to_complete)\n{\n\tu32 links_reg, links_orig;\n\tu32 i;\n\n\t/* clear the old state */\n\tlinks_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\n\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\n\tif (links_orig != links_reg) {\n\t\thw_dbg(hw, \"LINKS changed from %08X to %08X\\n\",\n\t\t\t links_orig, links_reg);\n\t}\n\n\tif (link_up_wait_to_complete) {\n\t\tfor (i = 0; i < IXGBE_LINK_UP_TIME; i++) {\n\t\t\tif (links_reg & IXGBE_LINKS_UP) {\n\t\t\t\t*link_up = true;\n\t\t\t\tbreak;\n\t\t\t} else {\n\t\t\t\t*link_up = false;\n\t\t\t}\n\t\t\tmsleep(100);\n\t\t\tlinks_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\t\t}\n\t} else {\n\t\tif (links_reg & IXGBE_LINKS_UP)\n\t\t\t*link_up = true;\n\t\telse\n\t\t\t*link_up = false;\n\t}\n\n\tif ((links_reg & IXGBE_LINKS_SPEED_82599) ==\n\t IXGBE_LINKS_SPEED_10G_82599)\n\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\telse if ((links_reg & IXGBE_LINKS_SPEED_82599) ==\n\t\t IXGBE_LINKS_SPEED_1G_82599)\n\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\telse if ((links_reg & IXGBE_LINKS_SPEED_82599) ==\n\t\t IXGBE_LINKS_SPEED_100_82599)\n\t\t*speed = IXGBE_LINK_SPEED_100_FULL;\n\telse\n\t\t*speed = IXGBE_LINK_SPEED_UNKNOWN;\n\n\treturn 0;\n}\n\n/**\n * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from\n * the EEPROM\n * @hw: pointer to hardware structure\n * @wwnn_prefix: the alternative WWNN prefix\n * @wwpn_prefix: the alternative WWPN prefix\n *\n * This function will read the EEPROM from the alternative SAN MAC address\n * block to check the support for the alternative WWNN/WWPN prefix support.\n **/\ns32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n\t\t\t\t u16 *wwpn_prefix)\n{\n\tu16 offset, caps;\n\tu16 alt_san_mac_blk_offset;\n\n\t/* clear output first */\n\t*wwnn_prefix = 0xFFFF;\n\t*wwpn_prefix = 0xFFFF;\n\n\t/* check if alternative SAN MAC is supported */\n\thw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,\n\t\t\t &alt_san_mac_blk_offset);\n\n\tif ((alt_san_mac_blk_offset == 0) ||\n\t (alt_san_mac_blk_offset == 0xFFFF))\n\t\tgoto wwn_prefix_out;\n\n\t/* check capability in alternative san mac address block */\n\toffset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;\n\thw->eeprom.ops.read(hw, offset, &caps);\n\tif (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))\n\t\tgoto wwn_prefix_out;\n\n\t/* get the corresponding prefix for WWNN/WWPN */\n\toffset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;\n\thw->eeprom.ops.read(hw, offset, wwnn_prefix);\n\n\toffset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;\n\thw->eeprom.ops.read(hw, offset, wwpn_prefix);\n\nwwn_prefix_out:\n\treturn 0;\n}\n\n/**\n * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM\n * @hw: pointer to hardware structure\n * @bs: the fcoe boot status\n *\n * This function will read the FCOE boot status from the iSCSI FCOE block\n **/\ns32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)\n{\n\tu16 offset, caps, flags;\n\ts32 status;\n\n\t/* clear output first */\n\t*bs = ixgbe_fcoe_bootstatus_unavailable;\n\n\t/* check if FCOE IBA block is present */\n\toffset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;\n\tstatus = hw->eeprom.ops.read(hw, offset, &caps);\n\tif (status != 0)\n\t\tgoto out;\n\n\tif (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))\n\t\tgoto out;\n\n\t/* check if iSCSI FCOE block is populated */\n\tstatus = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);\n\tif (status != 0)\n\t\tgoto out;\n\n\tif ((offset == 0) || (offset == 0xFFFF))\n\t\tgoto out;\n\n\t/* read fcoe flags in iSCSI FCOE block */\n\toffset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;\n\tstatus = hw->eeprom.ops.read(hw, offset, &flags);\n\tif (status != 0)\n\t\tgoto out;\n\n\tif (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)\n\t\t*bs = ixgbe_fcoe_bootstatus_enabled;\n\telse\n\t\t*bs = ixgbe_fcoe_bootstatus_disabled;\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing\n * @hw: pointer to hardware structure\n * @enable: enable or disable switch for anti-spoofing\n * @pf: Physical Function pool - do not enable anti-spoofing for the PF\n *\n **/\nvoid ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)\n{\n\tint j;\n\tint pf_target_reg = pf >> 3;\n\tint pf_target_shift = pf % 8;\n\tu32 pfvfspoof = 0;\n\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\treturn;\n\n\tif (enable)\n\t\tpfvfspoof = IXGBE_SPOOF_MACAS_MASK;\n\n\t/*\n\t * PFVFSPOOF register array is size 8 with 8 bits assigned to\n\t * MAC anti-spoof enables in each register array element.\n\t */\n\tfor (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)\n\t\tIXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);\n\n\t/* If not enabling anti-spoofing then done */\n\tif (!enable)\n\t\treturn;\n\n\t/*\n\t * The PF should be allowed to spoof so that it can support\n\t * emulation mode NICs. Reset the bit assigned to the PF\n\t */\n\tpfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));\n\tpfvfspoof ^= (1 << pf_target_shift);\n\tIXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);\n}\n\n/**\n * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing\n * @hw: pointer to hardware structure\n * @enable: enable or disable switch for VLAN anti-spoofing\n * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing\n *\n **/\nvoid ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)\n{\n\tint vf_target_reg = vf >> 3;\n\tint vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;\n\tu32 pfvfspoof;\n\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\treturn;\n\n\tpfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));\n\tif (enable)\n\t\tpfvfspoof |= (1 << vf_target_shift);\n\telse\n\t\tpfvfspoof &= ~(1 << vf_target_shift);\n\tIXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);\n}\n\n/**\n * ixgbe_get_device_caps_generic - Get additional device capabilities\n * @hw: pointer to hardware structure\n * @device_caps: the EEPROM word with the extra device capabilities\n *\n * This function will read the EEPROM location for the device capabilities,\n * and return the word through device_caps.\n **/\ns32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)\n{\n\thw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_calculate_checksum - Calculate checksum for buffer\n * @buffer: pointer to EEPROM\n * @length: size of EEPROM to calculate a checksum for\n * Calculates the checksum for some buffer on a specified length. The\n * checksum calculated is returned.\n **/\nstatic u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)\n{\n\tu32 i;\n\tu8 sum = 0;\n\n\tif (!buffer)\n\t\treturn 0;\n\tfor (i = 0; i < length; i++)\n\t\tsum += buffer[i];\n\n\treturn (u8) (0 - sum);\n}\n\n/**\n * ixgbe_host_interface_command - Issue command to manageability block\n * @hw: pointer to the HW structure\n * @buffer: contains the command to write and where the return status will\n * be placed\n * @length: length of buffer, must be multiple of 4 bytes\n *\n * Communicates with the manageability block. On success return 0\n * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.\n **/\nstatic s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,\n\t\t\t\t\tu32 length)\n{\n\tu32 hicr, i, bi;\n\tu32 hdr_size = sizeof(struct ixgbe_hic_hdr);\n\tu8 buf_len, dword_len;\n\n\ts32 ret_val = 0;\n\n\tif (length == 0 || length & 0x3 ||\n\t length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {\n\t\thw_dbg(hw, \"Buffer length failure.\\n\");\n\t\tret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;\n\t\tgoto out;\n\t}\n\n\t/* Check that the host interface is enabled. */\n\thicr = IXGBE_READ_REG(hw, IXGBE_HICR);\n\tif ((hicr & IXGBE_HICR_EN) == 0) {\n\t\thw_dbg(hw, \"IXGBE_HOST_EN bit disabled.\\n\");\n\t\tret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;\n\t\tgoto out;\n\t}\n\n\t/* Calculate length in DWORDs */\n\tdword_len = length >> 2;\n\n\t/*\n\t * The device driver writes the relevant command block\n\t * into the ram area.\n\t */\n\tfor (i = 0; i < dword_len; i++)\n\t\tIXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,\n\t\t\t\t i, IXGBE_CPU_TO_LE32(buffer[i]));\n\n\t/* Setting this bit tells the ARC that a new command is pending. */\n\tIXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);\n\n\tfor (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {\n\t\thicr = IXGBE_READ_REG(hw, IXGBE_HICR);\n\t\tif (!(hicr & IXGBE_HICR_C))\n\t\t\tbreak;\n\t\tmsleep(1);\n\t}\n\n\t/* Check command successful completion. */\n\tif (i == IXGBE_HI_COMMAND_TIMEOUT ||\n\t (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {\n\t\thw_dbg(hw, \"Command has failed with no status valid.\\n\");\n\t\tret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;\n\t\tgoto out;\n\t}\n\n\t/* Calculate length in DWORDs */\n\tdword_len = hdr_size >> 2;\n\n\t/* first pull in the header so we know the buffer length */\n\tfor (bi = 0; bi < dword_len; bi++) {\n\t\tbuffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);\n\t\tIXGBE_LE32_TO_CPUS(&buffer[bi]);\n\t}\n\n\t/* If there is any thing in data position pull it in */\n\tbuf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;\n\tif (buf_len == 0)\n\t\tgoto out;\n\n\tif (length < (buf_len + hdr_size)) {\n\t\thw_dbg(hw, \"Buffer not large enough for reply message.\\n\");\n\t\tret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;\n\t\tgoto out;\n\t}\n\n\t/* Calculate length in DWORDs, add 3 for odd lengths */\n\tdword_len = (buf_len + 3) >> 2;\n\n\t/* Pull in the rest of the buffer (bi is where we left off)*/\n\tfor (; bi <= dword_len; bi++) {\n\t\tbuffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);\n\t\tIXGBE_LE32_TO_CPUS(&buffer[bi]);\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware\n * @hw: pointer to the HW structure\n * @maj: driver version major number\n * @min: driver version minor number\n * @build: driver version build number\n * @sub: driver version sub build number\n *\n * Sends driver version number to firmware through the manageability\n * block. On success return 0\n * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring\n * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.\n **/\ns32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,\n\t\t\t\t u8 build, u8 sub)\n{\n\tstruct ixgbe_hic_drv_info fw_cmd;\n\tint i;\n\ts32 ret_val = 0;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)\n\t != 0) {\n\t\tret_val = IXGBE_ERR_SWFW_SYNC;\n\t\tgoto out;\n\t}\n\n\tfw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;\n\tfw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;\n\tfw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;\n\tfw_cmd.port_num = (u8)hw->bus.func;\n\tfw_cmd.ver_maj = maj;\n\tfw_cmd.ver_min = min;\n\tfw_cmd.ver_build = build;\n\tfw_cmd.ver_sub = sub;\n\tfw_cmd.hdr.checksum = 0;\n\tfw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,\n\t\t\t\t(FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));\n\tfw_cmd.pad = 0;\n\tfw_cmd.pad2 = 0;\n\n\tfor (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {\n\t\tret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,\n\t\t\t\t\t\t sizeof(fw_cmd));\n\t\tif (ret_val != 0)\n\t\t\tcontinue;\n\n\t\tif (fw_cmd.hdr.cmd_or_resp.ret_status ==\n\t\t FW_CEM_RESP_STATUS_SUCCESS)\n\t\t\tret_val = 0;\n\t\telse\n\t\t\tret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;\n\n\t\tbreak;\n\t}\n\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_set_rxpba_generic - Initialize Rx packet buffer\n * @hw: pointer to hardware structure\n * @num_pb: number of packet buffers to allocate\n * @headroom: reserve n KB of headroom\n * @strategy: packet buffer allocation strategy\n **/\nvoid ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,\n\t\t\t int strategy)\n{\n\tu32 pbsize = hw->mac.rx_pb_size;\n\tint i = 0;\n\tu32 rxpktsize, txpktsize, txpbthresh;\n\n\t/* Reserve headroom */\n\tpbsize -= headroom;\n\n\tif (!num_pb)\n\t\tnum_pb = 1;\n\n\t/* Divide remaining packet buffer space amongst the number of packet\n\t * buffers requested using supplied strategy.\n\t */\n\tswitch (strategy) {\n\tcase PBA_STRATEGY_WEIGHTED:\n\t\t/* ixgbe_dcb_pba_80_48 strategy weight first half of packet\n\t\t * buffer with 5/8 of the packet buffer space.\n\t\t */\n\t\trxpktsize = (pbsize * 5) / (num_pb * 4);\n\t\tpbsize -= rxpktsize * (num_pb / 2);\n\t\trxpktsize <<= IXGBE_RXPBSIZE_SHIFT;\n\t\tfor (; i < (num_pb / 2); i++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);\n\t\t/* Fall through to configure remaining packet buffers */\n\tcase PBA_STRATEGY_EQUAL:\n\t\trxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;\n\t\tfor (; i < num_pb; i++)\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* Only support an equally distributed Tx packet buffer strategy. */\n\ttxpktsize = IXGBE_TXPBSIZE_MAX / num_pb;\n\ttxpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;\n\tfor (i = 0; i < num_pb; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);\n\t}\n\n\t/* Clear unused TCs, if any, to zero buffer size*/\n\tfor (; i < IXGBE_MAX_PB; i++) {\n\t\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);\n\t}\n}\n\n/**\n * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo\n * @hw: pointer to the hardware structure\n *\n * The 82599 and x540 MACs can experience issues if TX work is still pending\n * when a reset occurs. This function prevents this by flushing the PCIe\n * buffers on the system.\n **/\nvoid ixgbe_clear_tx_pending(struct ixgbe_hw *hw)\n{\n\tu32 gcr_ext, hlreg0;\n\n\t/*\n\t * If double reset is not requested then all transactions should\n\t * already be clear and as such there is no work to do\n\t */\n\tif (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))\n\t\treturn;\n\n\t/*\n\t * Set loopback enable to prevent any transmits from being sent\n\t * should the link come up. This assumes that the RXCTRL.RXEN bit\n\t * has already been cleared.\n\t */\n\thlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);\n\tIXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);\n\n\t/* initiate cleaning flow for buffers in the PCIe transaction layer */\n\tgcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);\n\tIXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,\n\t\t\tgcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);\n\n\t/* Flush all writes and allow 20usec for all transactions to clear */\n\tIXGBE_WRITE_FLUSH(hw);\n\tudelay(20);\n\n\t/* restore previous register values */\n\tIXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);\n\tIXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);\n}\n\nstatic const u8 ixgbe_emc_temp_data[4] = {\n\tIXGBE_EMC_INTERNAL_DATA,\n\tIXGBE_EMC_DIODE1_DATA,\n\tIXGBE_EMC_DIODE2_DATA,\n\tIXGBE_EMC_DIODE3_DATA\n};\nstatic const u8 ixgbe_emc_therm_limit[4] = {\n\tIXGBE_EMC_INTERNAL_THERM_LIMIT,\n\tIXGBE_EMC_DIODE1_THERM_LIMIT,\n\tIXGBE_EMC_DIODE2_THERM_LIMIT,\n\tIXGBE_EMC_DIODE3_THERM_LIMIT\n};\n\n/**\n * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data\n * @hw: pointer to hardware structure\n * @data: pointer to the thermal sensor data structure\n *\n * Returns the thermal sensor data structure\n **/\ns32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\tu16 ets_offset;\n\tu16 ets_cfg;\n\tu16 ets_sensor;\n\tu8 num_sensors;\n\tu8 sensor_index;\n\tu8 sensor_location;\n\tu8 i;\n\tstruct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;\n\n\t/* Only support thermal sensors attached to 82599 physical port 0 */\n\tif ((hw->mac.type != ixgbe_mac_82599EB) ||\n\t (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {\n\t\tstatus = IXGBE_NOT_IMPLEMENTED;\n\t\tgoto out;\n\t}\n\n\tstatus = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);\n\tif (status)\n\t\tgoto out;\n\n\tif ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {\n\t\tstatus = IXGBE_NOT_IMPLEMENTED;\n\t\tgoto out;\n\t}\n\n\tstatus = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);\n\tif (status)\n\t\tgoto out;\n\n\tif (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)\n\t\t!= IXGBE_ETS_TYPE_EMC) {\n\t\tstatus = IXGBE_NOT_IMPLEMENTED;\n\t\tgoto out;\n\t}\n\n\tnum_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);\n\tif (num_sensors > IXGBE_MAX_SENSORS)\n\t\tnum_sensors = IXGBE_MAX_SENSORS;\n\n\tfor (i = 0; i < num_sensors; i++) {\n\t\tstatus = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),\n\t\t\t\t\t &ets_sensor);\n\t\tif (status)\n\t\t\tgoto out;\n\n\t\tsensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>\n\t\t\t\tIXGBE_ETS_DATA_INDEX_SHIFT);\n\t\tsensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>\n\t\t\t\t IXGBE_ETS_DATA_LOC_SHIFT);\n\n\t\tif (sensor_location != 0) {\n\t\t\tstatus = hw->phy.ops.read_i2c_byte(hw,\n\t\t\t\t\tixgbe_emc_temp_data[sensor_index],\n\t\t\t\t\tIXGBE_I2C_THERMAL_SENSOR_ADDR,\n\t\t\t\t\t&data->sensor[i].temp);\n\t\t\tif (status)\n\t\t\t\tgoto out;\n\t\t}\n\t}\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds\n * @hw: pointer to hardware structure\n *\n * Inits the thermal sensor thresholds according to the NVM map\n * and save off the threshold and location values into mac.thermal_sensor_data\n **/\ns32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\tu16 ets_offset;\n\tu16 ets_cfg;\n\tu16 ets_sensor;\n\tu8 low_thresh_delta;\n\tu8 num_sensors;\n\tu8 sensor_index;\n\tu8 sensor_location;\n\tu8 therm_limit;\n\tu8 i;\n\tstruct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;\n\n\tmemset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));\n\n\t/* Only support thermal sensors attached to 82599 physical port 0 */\n\tif ((hw->mac.type != ixgbe_mac_82599EB) ||\n\t (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))\n\t\treturn IXGBE_NOT_IMPLEMENTED;\n\n\thw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);\n\tif ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))\n\t\treturn IXGBE_NOT_IMPLEMENTED;\n\n\thw->eeprom.ops.read(hw, ets_offset, &ets_cfg);\n\tif (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)\n\t\t!= IXGBE_ETS_TYPE_EMC)\n\t\treturn IXGBE_NOT_IMPLEMENTED;\n\n\tlow_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>\n\t\t\t IXGBE_ETS_LTHRES_DELTA_SHIFT);\n\tnum_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);\n\n\tfor (i = 0; i < num_sensors; i++) {\n\t\thw->eeprom.ops.read(hw, (ets_offset + 1 + i), &ets_sensor);\n\t\tsensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>\n\t\t\t\tIXGBE_ETS_DATA_INDEX_SHIFT);\n\t\tsensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>\n\t\t\t\t IXGBE_ETS_DATA_LOC_SHIFT);\n\t\ttherm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;\n\n\t\thw->phy.ops.write_i2c_byte(hw,\n\t\t\tixgbe_emc_therm_limit[sensor_index],\n\t\t\tIXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);\n\n\t\tif ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {\n\t\t\tdata->sensor[i].location = sensor_location;\n\t\t\tdata->sensor[i].caution_thresh = therm_limit;\n\t\t\tdata->sensor[i].max_op_thresh = therm_limit -\n\t\t\t\t\t\t\tlow_thresh_delta;\n\t\t}\n\t}\n\treturn status;\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_common.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _IXGBE_COMMON_H_\n#define _IXGBE_COMMON_H_\n\n#include \"ixgbe_type.h\"\n\nu16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);\n\ns32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);\ns32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);\ns32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);\ns32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);\ns32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);\ns32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,\n\t\t\t\t u32 pba_num_size);\ns32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);\ns32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);\nvoid ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);\ns32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);\n\ns32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);\n\ns32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);\ns32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);\ns32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data);\ns32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);\ns32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data);\ns32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);\ns32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 words, u16 *data);\ns32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t u16 *data);\ns32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n\t\t\t\t\t u16 words, u16 *data);\nu16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);\ns32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *checksum_val);\ns32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);\ns32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);\n\ns32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,\n\t\t\t u32 enable_addr);\ns32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);\ns32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,\n\t\t\t\t u32 mc_addr_count,\n\t\t\t\t ixgbe_mc_addr_itr func, bool clear);\ns32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,\n\t\t\t\t u32 addr_count, ixgbe_mc_addr_itr func);\ns32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);\ns32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);\ns32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);\ns32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw);\ns32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw);\n\ns32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);\nvoid ixgbe_fc_autoneg(struct ixgbe_hw *hw);\n\ns32 ixgbe_validate_mac_addr(u8 *mac_addr);\ns32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);\nvoid ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);\ns32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);\n\ns32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);\n\ns32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);\ns32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);\n\ns32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);\ns32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);\ns32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);\ns32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);\ns32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);\ns32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,\n\t\t\t u32 vind, bool vlan_on);\ns32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,\n\t\t\t bool vlan_on, bool *vfta_changed);\ns32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);\ns32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan);\n\ns32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,\n\t\t\t ixgbe_link_speed *speed,\n\t\t\t bool *link_up, bool link_up_wait_to_complete);\n\ns32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n\t\t\t\t u16 *wwpn_prefix);\n\ns32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs);\nvoid ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf);\nvoid ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);\ns32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);\nvoid ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,\n\t\t\t int strategy);\ns32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,\n\t\t\t\t u8 build, u8 ver);\nvoid ixgbe_clear_tx_pending(struct ixgbe_hw *hw);\n\n#define IXGBE_I2C_THERMAL_SENSOR_ADDR\t0xF8\n#define IXGBE_EMC_INTERNAL_DATA\t\t0x00\n#define IXGBE_EMC_INTERNAL_THERM_LIMIT\t0x20\n#define IXGBE_EMC_DIODE1_DATA\t\t0x01\n#define IXGBE_EMC_DIODE1_THERM_LIMIT\t0x19\n#define IXGBE_EMC_DIODE2_DATA\t\t0x23\n#define IXGBE_EMC_DIODE2_THERM_LIMIT\t0x1A\n#define IXGBE_EMC_DIODE3_DATA\t\t0x2A\n#define IXGBE_EMC_DIODE3_THERM_LIMIT\t0x30\n\ns32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);\ns32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);\n#endif /* IXGBE_COMMON */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_dcb.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _IXGBE_DCB_H_\n#define _IXGBE_DCB_H_\n\n\n#include \"ixgbe_type.h\"\n\n/* DCB defines */\n/* DCB credit calculation defines */\n#define IXGBE_DCB_CREDIT_QUANTUM\t64\n#define IXGBE_DCB_MAX_CREDIT_REFILL\t200 /* 200 * 64B = 12800B */\n#define IXGBE_DCB_MAX_TSO_SIZE\t\t(32 * 1024) /* Max TSO pkt size in DCB*/\n#define IXGBE_DCB_MAX_CREDIT\t\t(2 * IXGBE_DCB_MAX_CREDIT_REFILL)\n\n/* 513 for 32KB TSO packet */\n#define IXGBE_DCB_MIN_TSO_CREDIT\t\\\n\t((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1)\n\n/* DCB configuration defines */\n#define IXGBE_DCB_MAX_USER_PRIORITY\t8\n#define IXGBE_DCB_MAX_BW_GROUP\t\t8\n#define IXGBE_DCB_BW_PERCENT\t\t100\n\n#define IXGBE_DCB_TX_CONFIG\t\t0\n#define IXGBE_DCB_RX_CONFIG\t\t1\n\n/* DCB capability defines */\n#define IXGBE_DCB_PG_SUPPORT\t0x00000001\n#define IXGBE_DCB_PFC_SUPPORT\t0x00000002\n#define IXGBE_DCB_BCN_SUPPORT\t0x00000004\n#define IXGBE_DCB_UP2TC_SUPPORT\t0x00000008\n#define IXGBE_DCB_GSP_SUPPORT\t0x00000010\n\nstruct ixgbe_dcb_support {\n\tu32 capabilities; /* DCB capabilities */\n\n\t/* Each bit represents a number of TCs configurable in the hw.\n\t * If 8 traffic classes can be configured, the value is 0x80. */\n\tu8 traffic_classes;\n\tu8 pfc_traffic_classes;\n};\n\nenum ixgbe_dcb_tsa {\n\tixgbe_dcb_tsa_ets = 0,\n\tixgbe_dcb_tsa_group_strict_cee,\n\tixgbe_dcb_tsa_strict\n};\n\n/* Traffic class bandwidth allocation per direction */\nstruct ixgbe_dcb_tc_path {\n\tu8 bwg_id; /* Bandwidth Group (BWG) ID */\n\tu8 bwg_percent; /* % of BWG's bandwidth */\n\tu8 link_percent; /* % of link bandwidth */\n\tu8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */\n\tu16 data_credits_refill; /* Credit refill amount in 64B granularity */\n\tu16 data_credits_max; /* Max credits for a configured packet buffer\n\t\t\t * in 64B granularity.*/\n\tenum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */\n};\n\nenum ixgbe_dcb_pfc {\n\tixgbe_dcb_pfc_disabled = 0,\n\tixgbe_dcb_pfc_enabled,\n\tixgbe_dcb_pfc_enabled_txonly,\n\tixgbe_dcb_pfc_enabled_rxonly\n};\n\n/* Traffic class configuration */\nstruct ixgbe_dcb_tc_config {\n\tstruct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */\n\tenum ixgbe_dcb_pfc pfc; /* Class based flow control setting */\n\n\tu16 desc_credits_max; /* For Tx Descriptor arbitration */\n\tu8 tc; /* Traffic class (TC) */\n};\n\nenum ixgbe_dcb_pba {\n\t/* PBA[0-7] each use 64KB FIFO */\n\tixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL,\n\t/* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */\n\tixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED\n};\n\nstruct ixgbe_dcb_num_tcs {\n\tu8 pg_tcs;\n\tu8 pfc_tcs;\n};\n\nstruct ixgbe_dcb_config {\n\tstruct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS];\n\tstruct ixgbe_dcb_support support;\n\tstruct ixgbe_dcb_num_tcs num_tcs;\n\tu8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */\n\tbool pfc_mode_enable;\n\tbool round_robin_enable;\n\n\tenum ixgbe_dcb_pba rx_pba_cfg;\n\n\tu32 dcb_cfg_version; /* Not used...OS-specific? */\n\tu32 link_speed; /* For bandwidth allocation validation purpose */\n\tbool vt_mode;\n};\n\n/* DCB driver APIs */\n\n/* DCB rule checking */\ns32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *);\n\n/* DCB credits calculation */\ns32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int);\ns32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *,\n\t\t\t\t struct ixgbe_dcb_config *, u32, u8);\n\n/* DCB PFC */\ns32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *);\ns32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);\n\n/* DCB stats */\ns32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *);\ns32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);\ns32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);\n\n/* DCB config arbiters */\ns32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *,\n\t\t\t\t\t struct ixgbe_dcb_config *);\ns32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *,\n\t\t\t\t\t struct ixgbe_dcb_config *);\ns32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *,\n\t\t\t\t struct ixgbe_dcb_config *);\n\n/* DCB unpack routines */\nvoid ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *);\nvoid ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *);\nvoid ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *);\nvoid ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *);\nvoid ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *);\nvoid ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *);\n\n/* DCB initialization */\ns32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *);\ns32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *);\n#endif /* _IXGBE_DCB_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_ethtool.c", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n/* ethtool support for ixgbe */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#ifdef SIOCETHTOOL\n#include \n\n#include \"ixgbe.h\"\n\n#ifndef ETH_GSTRING_LEN\n#define ETH_GSTRING_LEN 32\n#endif\n\n#define IXGBE_ALL_RAR_ENTRIES 16\n\n#ifdef ETHTOOL_OPS_COMPAT\n#include \"kcompat_ethtool.c\"\n#endif\n#ifdef ETHTOOL_GSTATS\nstruct ixgbe_stats {\n\tchar stat_string[ETH_GSTRING_LEN];\n\tint sizeof_stat;\n\tint stat_offset;\n};\n\n#define IXGBE_NETDEV_STAT(_net_stat) { \\\n\t.stat_string = #_net_stat, \\\n\t.sizeof_stat = FIELD_SIZEOF(struct net_device_stats, _net_stat), \\\n\t.stat_offset = offsetof(struct net_device_stats, _net_stat) \\\n}\nstatic const struct ixgbe_stats ixgbe_gstrings_net_stats[] = {\n\tIXGBE_NETDEV_STAT(rx_packets),\n\tIXGBE_NETDEV_STAT(tx_packets),\n\tIXGBE_NETDEV_STAT(rx_bytes),\n\tIXGBE_NETDEV_STAT(tx_bytes),\n\tIXGBE_NETDEV_STAT(rx_errors),\n\tIXGBE_NETDEV_STAT(tx_errors),\n\tIXGBE_NETDEV_STAT(rx_dropped),\n\tIXGBE_NETDEV_STAT(tx_dropped),\n\tIXGBE_NETDEV_STAT(multicast),\n\tIXGBE_NETDEV_STAT(collisions),\n\tIXGBE_NETDEV_STAT(rx_over_errors),\n\tIXGBE_NETDEV_STAT(rx_crc_errors),\n\tIXGBE_NETDEV_STAT(rx_frame_errors),\n\tIXGBE_NETDEV_STAT(rx_fifo_errors),\n\tIXGBE_NETDEV_STAT(rx_missed_errors),\n\tIXGBE_NETDEV_STAT(tx_aborted_errors),\n\tIXGBE_NETDEV_STAT(tx_carrier_errors),\n\tIXGBE_NETDEV_STAT(tx_fifo_errors),\n\tIXGBE_NETDEV_STAT(tx_heartbeat_errors),\n};\n\n#define IXGBE_STAT(_name, _stat) { \\\n\t.stat_string = _name, \\\n\t.sizeof_stat = FIELD_SIZEOF(struct ixgbe_adapter, _stat), \\\n\t.stat_offset = offsetof(struct ixgbe_adapter, _stat) \\\n}\nstatic struct ixgbe_stats ixgbe_gstrings_stats[] = {\n\tIXGBE_STAT(\"rx_pkts_nic\", stats.gprc),\n\tIXGBE_STAT(\"tx_pkts_nic\", stats.gptc),\n\tIXGBE_STAT(\"rx_bytes_nic\", stats.gorc),\n\tIXGBE_STAT(\"tx_bytes_nic\", stats.gotc),\n\tIXGBE_STAT(\"lsc_int\", lsc_int),\n\tIXGBE_STAT(\"tx_busy\", tx_busy),\n\tIXGBE_STAT(\"non_eop_descs\", non_eop_descs),\n#ifndef CONFIG_IXGBE_NAPI\n\tIXGBE_STAT(\"rx_dropped_backlog\", rx_dropped_backlog),\n#endif\n\tIXGBE_STAT(\"broadcast\", stats.bprc),\n\tIXGBE_STAT(\"rx_no_buffer_count\", stats.rnbc[0]) ,\n\tIXGBE_STAT(\"tx_timeout_count\", tx_timeout_count),\n\tIXGBE_STAT(\"tx_restart_queue\", restart_queue),\n\tIXGBE_STAT(\"rx_long_length_errors\", stats.roc),\n\tIXGBE_STAT(\"rx_short_length_errors\", stats.ruc),\n\tIXGBE_STAT(\"tx_flow_control_xon\", stats.lxontxc),\n\tIXGBE_STAT(\"rx_flow_control_xon\", stats.lxonrxc),\n\tIXGBE_STAT(\"tx_flow_control_xoff\", stats.lxofftxc),\n\tIXGBE_STAT(\"rx_flow_control_xoff\", stats.lxoffrxc),\n\tIXGBE_STAT(\"rx_csum_offload_errors\", hw_csum_rx_error),\n\tIXGBE_STAT(\"alloc_rx_page_failed\", alloc_rx_page_failed),\n\tIXGBE_STAT(\"alloc_rx_buff_failed\", alloc_rx_buff_failed),\n#ifndef IXGBE_NO_LRO\n\tIXGBE_STAT(\"lro_aggregated\", lro_stats.coal),\n\tIXGBE_STAT(\"lro_flushed\", lro_stats.flushed),\n#endif /* IXGBE_NO_LRO */\n\tIXGBE_STAT(\"rx_no_dma_resources\", hw_rx_no_dma_resources),\n\tIXGBE_STAT(\"hw_rsc_aggregated\", rsc_total_count),\n\tIXGBE_STAT(\"hw_rsc_flushed\", rsc_total_flush),\n#ifdef HAVE_TX_MQ\n\tIXGBE_STAT(\"fdir_match\", stats.fdirmatch),\n\tIXGBE_STAT(\"fdir_miss\", stats.fdirmiss),\n\tIXGBE_STAT(\"fdir_overflow\", fdir_overflow),\n#endif /* HAVE_TX_MQ */\n#ifdef IXGBE_FCOE\n\tIXGBE_STAT(\"fcoe_bad_fccrc\", stats.fccrc),\n\tIXGBE_STAT(\"fcoe_last_errors\", stats.fclast),\n\tIXGBE_STAT(\"rx_fcoe_dropped\", stats.fcoerpdc),\n\tIXGBE_STAT(\"rx_fcoe_packets\", stats.fcoeprc),\n\tIXGBE_STAT(\"rx_fcoe_dwords\", stats.fcoedwrc),\n\tIXGBE_STAT(\"fcoe_noddp\", stats.fcoe_noddp),\n\tIXGBE_STAT(\"fcoe_noddp_ext_buff\", stats.fcoe_noddp_ext_buff),\n\tIXGBE_STAT(\"tx_fcoe_packets\", stats.fcoeptc),\n\tIXGBE_STAT(\"tx_fcoe_dwords\", stats.fcoedwtc),\n#endif /* IXGBE_FCOE */\n\tIXGBE_STAT(\"os2bmc_rx_by_bmc\", stats.o2bgptc),\n\tIXGBE_STAT(\"os2bmc_tx_by_bmc\", stats.b2ospc),\n\tIXGBE_STAT(\"os2bmc_tx_by_host\", stats.o2bspc),\n\tIXGBE_STAT(\"os2bmc_rx_by_host\", stats.b2ogprc),\n};\n\n#define IXGBE_QUEUE_STATS_LEN \\\n\t((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \\\n\t ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \\\n\t (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))\n#define IXGBE_GLOBAL_STATS_LEN\tARRAY_SIZE(ixgbe_gstrings_stats)\n#define IXGBE_NETDEV_STATS_LEN\tARRAY_SIZE(ixgbe_gstrings_net_stats)\n#define IXGBE_PB_STATS_LEN ( \\\n\t\t(((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \\\n\t\t IXGBE_FLAG_DCB_ENABLED) ? \\\n\t\t (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \\\n\t\t sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \\\n\t\t sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \\\n\t\t sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \\\n\t\t / sizeof(u64) : 0)\n#define IXGBE_VF_STATS_LEN \\\n\t((((struct ixgbe_adapter *)netdev_priv(netdev))->num_vfs) * \\\n\t (sizeof(struct vf_stats) / sizeof(u64)))\n#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \\\n\t\t\t IXGBE_NETDEV_STATS_LEN + \\\n\t\t\t IXGBE_PB_STATS_LEN + \\\n\t\t\t IXGBE_QUEUE_STATS_LEN + \\\n\t\t\t IXGBE_VF_STATS_LEN)\n\n#endif /* ETHTOOL_GSTATS */\n#ifdef ETHTOOL_TEST\nstatic const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {\n\t\"Register test (offline)\", \"Eeprom test (offline)\",\n\t\"Interrupt test (offline)\", \"Loopback test (offline)\",\n\t\"Link test (on/offline)\"\n};\n#define IXGBE_TEST_LEN\t(sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN)\n#endif /* ETHTOOL_TEST */\n\nint ixgbe_get_settings(struct net_device *netdev,\n\t\t struct ethtool_cmd *ecmd)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tu32 link_speed = 0;\n\tbool link_up;\n\n\tecmd->supported = SUPPORTED_10000baseT_Full;\n\tecmd->autoneg = AUTONEG_ENABLE;\n\tecmd->transceiver = XCVR_EXTERNAL;\n\tif ((hw->phy.media_type == ixgbe_media_type_copper) ||\n\t (hw->phy.multispeed_fiber)) {\n\t\tecmd->supported |= (SUPPORTED_1000baseT_Full |\n\t\t\t\t SUPPORTED_Autoneg);\n\t\tswitch (hw->mac.type) {\n\t\tcase ixgbe_mac_X540:\n\t\t\tecmd->supported |= SUPPORTED_100baseT_Full;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\n\t\tecmd->advertising = ADVERTISED_Autoneg;\n\t\tif (hw->phy.autoneg_advertised) {\n\t\t\tif (hw->phy.autoneg_advertised &\n\t\t\t IXGBE_LINK_SPEED_100_FULL)\n\t\t\t\tecmd->advertising |= ADVERTISED_100baseT_Full;\n\t\t\tif (hw->phy.autoneg_advertised &\n\t\t\t IXGBE_LINK_SPEED_10GB_FULL)\n\t\t\t\tecmd->advertising |= ADVERTISED_10000baseT_Full;\n\t\t\tif (hw->phy.autoneg_advertised &\n\t\t\t IXGBE_LINK_SPEED_1GB_FULL)\n\t\t\t\tecmd->advertising |= ADVERTISED_1000baseT_Full;\n\t\t} else {\n\t\t\t/*\n\t\t\t * Default advertised modes in case\n\t\t\t * phy.autoneg_advertised isn't set.\n\t\t\t */\n\t\t\tecmd->advertising |= (ADVERTISED_10000baseT_Full |\n\t\t\t\t\t ADVERTISED_1000baseT_Full);\n\t\t\tif (hw->mac.type == ixgbe_mac_X540)\n\t\t\t\tecmd->advertising |= ADVERTISED_100baseT_Full;\n\t\t}\n\n\t\tif (hw->phy.media_type == ixgbe_media_type_copper) {\n\t\t\tecmd->supported |= SUPPORTED_TP;\n\t\t\tecmd->advertising |= ADVERTISED_TP;\n\t\t\tecmd->port = PORT_TP;\n\t\t} else {\n\t\t\tecmd->supported |= SUPPORTED_FIBRE;\n\t\t\tecmd->advertising |= ADVERTISED_FIBRE;\n\t\t\tecmd->port = PORT_FIBRE;\n\t\t}\n\t} else if (hw->phy.media_type == ixgbe_media_type_backplane) {\n\t\t/* Set as FIBRE until SERDES defined in kernel */\n\t\tif (hw->device_id == IXGBE_DEV_ID_82598_BX) {\n\t\t\tecmd->supported = (SUPPORTED_1000baseT_Full |\n\t\t\t\t\t SUPPORTED_FIBRE);\n\t\t\tecmd->advertising = (ADVERTISED_1000baseT_Full |\n\t\t\t\t\t ADVERTISED_FIBRE);\n\t\t\tecmd->port = PORT_FIBRE;\n\t\t\tecmd->autoneg = AUTONEG_DISABLE;\n\t\t} else if ((hw->device_id == IXGBE_DEV_ID_82599_COMBO_BACKPLANE)\n\t\t\t || (hw->device_id == IXGBE_DEV_ID_82599_KX4_MEZZ)) {\n\t\t\tecmd->supported |= (SUPPORTED_1000baseT_Full |\n\t\t\t\t\t SUPPORTED_Autoneg |\n\t\t\t\t\t SUPPORTED_FIBRE);\n\t\t\tecmd->advertising = (ADVERTISED_10000baseT_Full |\n\t\t\t\t\t ADVERTISED_1000baseT_Full |\n\t\t\t\t\t ADVERTISED_Autoneg |\n\t\t\t\t\t ADVERTISED_FIBRE);\n\t\t\tecmd->port = PORT_FIBRE;\n\t\t} else {\n\t\t\tecmd->supported |= (SUPPORTED_1000baseT_Full |\n\t\t\t\t\t SUPPORTED_FIBRE);\n\t\t\tecmd->advertising = (ADVERTISED_10000baseT_Full |\n\t\t\t\t\t ADVERTISED_1000baseT_Full |\n\t\t\t\t\t ADVERTISED_FIBRE);\n\t\t\tecmd->port = PORT_FIBRE;\n\t\t}\n\t} else {\n\t\tecmd->supported |= SUPPORTED_FIBRE;\n\t\tecmd->advertising = (ADVERTISED_10000baseT_Full |\n\t\t\t\t ADVERTISED_FIBRE);\n\t\tecmd->port = PORT_FIBRE;\n\t\tecmd->autoneg = AUTONEG_DISABLE;\n\t}\n\n#ifdef HAVE_ETHTOOL_SFP_DISPLAY_PORT\n\t/* Get PHY type */\n\tswitch (adapter->hw.phy.type) {\n\tcase ixgbe_phy_tn:\n\tcase ixgbe_phy_aq:\n\tcase ixgbe_phy_cu_unknown:\n\t\t/* Copper 10G-BASET */\n\t\tecmd->port = PORT_TP;\n\t\tbreak;\n\tcase ixgbe_phy_qt:\n\t\tecmd->port = PORT_FIBRE;\n\t\tbreak;\n\tcase ixgbe_phy_nl:\n\tcase ixgbe_phy_sfp_passive_tyco:\n\tcase ixgbe_phy_sfp_passive_unknown:\n\tcase ixgbe_phy_sfp_ftl:\n\tcase ixgbe_phy_sfp_avago:\n\tcase ixgbe_phy_sfp_intel:\n\tcase ixgbe_phy_sfp_unknown:\n\t\tswitch (adapter->hw.phy.sfp_type) {\n\t\t/* SFP+ devices, further checking needed */\n\t\tcase ixgbe_sfp_type_da_cu:\n\t\tcase ixgbe_sfp_type_da_cu_core0:\n\t\tcase ixgbe_sfp_type_da_cu_core1:\n\t\t\tecmd->port = PORT_DA;\n\t\t\tbreak;\n\t\tcase ixgbe_sfp_type_sr:\n\t\tcase ixgbe_sfp_type_lr:\n\t\tcase ixgbe_sfp_type_srlr_core0:\n\t\tcase ixgbe_sfp_type_srlr_core1:\n\t\t\tecmd->port = PORT_FIBRE;\n\t\t\tbreak;\n\t\tcase ixgbe_sfp_type_not_present:\n\t\t\tecmd->port = PORT_NONE;\n\t\t\tbreak;\n\t\tcase ixgbe_sfp_type_1g_cu_core0:\n\t\tcase ixgbe_sfp_type_1g_cu_core1:\n\t\t\tecmd->port = PORT_TP;\n\t\t\tecmd->supported = SUPPORTED_TP;\n\t\t\tecmd->advertising = (ADVERTISED_1000baseT_Full |\n\t\t\t\tADVERTISED_TP);\n\t\t\tbreak;\n\t\tcase ixgbe_sfp_type_1g_sx_core0:\n\t\tcase ixgbe_sfp_type_1g_sx_core1:\n\t\t\tecmd->port = PORT_FIBRE;\n\t\t\tecmd->supported = SUPPORTED_FIBRE;\n\t\t\tecmd->advertising = (ADVERTISED_1000baseT_Full |\n\t\t\t\tADVERTISED_FIBRE);\n\t\t\tbreak;\n\t\tcase ixgbe_sfp_type_unknown:\n\t\tdefault:\n\t\t\tecmd->port = PORT_OTHER;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase ixgbe_phy_xaui:\n\t\tecmd->port = PORT_NONE;\n\t\tbreak;\n\tcase ixgbe_phy_unknown:\n\tcase ixgbe_phy_generic:\n\tcase ixgbe_phy_sfp_unsupported:\n\tdefault:\n\t\tecmd->port = PORT_OTHER;\n\t\tbreak;\n\t}\n#endif\n\n\tif (!in_interrupt()) {\n\t\thw->mac.ops.check_link(hw, &link_speed, &link_up, false);\n\t} else {\n\t\t/*\n\t\t * this case is a special workaround for RHEL5 bonding\n\t\t * that calls this routine from interrupt context\n\t\t */\n\t\tlink_speed = adapter->link_speed;\n\t\tlink_up = adapter->link_up;\n\t}\n\n\tif (link_up) {\n\t\tswitch (link_speed) {\n\t\tcase IXGBE_LINK_SPEED_10GB_FULL:\n\t\t\tecmd->speed = SPEED_10000;\n\t\t\tbreak;\n\t\tcase IXGBE_LINK_SPEED_1GB_FULL:\n\t\t\tecmd->speed = SPEED_1000;\n\t\t\tbreak;\n\t\tcase IXGBE_LINK_SPEED_100_FULL:\n\t\t\tecmd->speed = SPEED_100;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t\tecmd->duplex = DUPLEX_FULL;\n\t} else {\n\t\tecmd->speed = -1;\n\t\tecmd->duplex = -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int ixgbe_set_settings(struct net_device *netdev,\n\t\t\t struct ethtool_cmd *ecmd)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tu32 advertised, old;\n\ts32 err = 0;\n\n\tif ((hw->phy.media_type == ixgbe_media_type_copper) ||\n\t (hw->phy.multispeed_fiber)) {\n\t\t/*\n\t\t * this function does not support duplex forcing, but can\n\t\t * limit the advertising of the adapter to the specified speed\n\t\t */\n\t\tif (ecmd->autoneg == AUTONEG_DISABLE)\n\t\t\treturn -EINVAL;\n\n\t\tif (ecmd->advertising & ~ecmd->supported)\n\t\t\treturn -EINVAL;\n\n\t\told = hw->phy.autoneg_advertised;\n\t\tadvertised = 0;\n\t\tif (ecmd->advertising & ADVERTISED_10000baseT_Full)\n\t\t\tadvertised |= IXGBE_LINK_SPEED_10GB_FULL;\n\n\t\tif (ecmd->advertising & ADVERTISED_1000baseT_Full)\n\t\t\tadvertised |= IXGBE_LINK_SPEED_1GB_FULL;\n\n\t\tif (ecmd->advertising & ADVERTISED_100baseT_Full)\n\t\t\tadvertised |= IXGBE_LINK_SPEED_100_FULL;\n\n\t\tif (old == advertised)\n\t\t\treturn err;\n\t\t/* this sets the link speed and restarts auto-neg */\n\t\thw->mac.autotry_restart = true;\n\t\terr = hw->mac.ops.setup_link(hw, advertised, true, true);\n\t\tif (err) {\n\t\t\te_info(probe, \"setup link failed with code %d\\n\", err);\n\t\t\thw->mac.ops.setup_link(hw, old, true, true);\n\t\t}\n\t}\n\treturn err;\n}\n\nstatic void ixgbe_get_pauseparam(struct net_device *netdev,\n\t\t\t\t struct ethtool_pauseparam *pause)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\n\tif (hw->fc.disable_fc_autoneg)\n\t\tpause->autoneg = 0;\n\telse\n\t\tpause->autoneg = 1;\n\n\tif (hw->fc.current_mode == ixgbe_fc_rx_pause) {\n\t\tpause->rx_pause = 1;\n\t} else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {\n\t\tpause->tx_pause = 1;\n\t} else if (hw->fc.current_mode == ixgbe_fc_full) {\n\t\tpause->rx_pause = 1;\n\t\tpause->tx_pause = 1;\n\t}\n}\n\nstatic int ixgbe_set_pauseparam(struct net_device *netdev,\n\t\t\t\tstruct ethtool_pauseparam *pause)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct ixgbe_fc_info fc = hw->fc;\n\n\t/* 82598 does no support link flow control with DCB enabled */\n\tif ((hw->mac.type == ixgbe_mac_82598EB) &&\n\t (adapter->flags & IXGBE_FLAG_DCB_ENABLED))\n\t\treturn -EINVAL;\n\n\tfc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);\n\n\tif ((pause->rx_pause && pause->tx_pause) || pause->autoneg)\n\t\tfc.requested_mode = ixgbe_fc_full;\n\telse if (pause->rx_pause)\n\t\tfc.requested_mode = ixgbe_fc_rx_pause;\n\telse if (pause->tx_pause)\n\t\tfc.requested_mode = ixgbe_fc_tx_pause;\n\telse\n\t\tfc.requested_mode = ixgbe_fc_none;\n\n\t/* if the thing changed then we'll update and use new autoneg */\n\tif (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {\n\t\thw->fc = fc;\n\t\tif (netif_running(netdev))\n\t\t\tixgbe_reinit_locked(adapter);\n\t\telse\n\t\t\tixgbe_reset(adapter);\n\t}\n\n\treturn 0;\n}\n\nstatic u32 ixgbe_get_msglevel(struct net_device *netdev)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\treturn adapter->msg_enable;\n}\n\nstatic void ixgbe_set_msglevel(struct net_device *netdev, u32 data)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tadapter->msg_enable = data;\n}\n\nstatic int ixgbe_get_regs_len(struct net_device *netdev)\n{\n#define IXGBE_REGS_LEN 1129\n\treturn IXGBE_REGS_LEN * sizeof(u32);\n}\n\n#define IXGBE_GET_STAT(_A_, _R_)\t(_A_->stats._R_)\n\n\nstatic void ixgbe_get_regs(struct net_device *netdev, struct ethtool_regs *regs,\n\t\t\t void *p)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tu32 *regs_buff = p;\n\tu8 i;\n\n\tprintk(KERN_DEBUG \"ixgbe_get_regs_1\\n\");\n\tmemset(p, 0, IXGBE_REGS_LEN * sizeof(u32));\n\tprintk(KERN_DEBUG \"ixgbe_get_regs_2 0x%p\\n\", hw->hw_addr);\n\n\tregs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;\n\n\t/* General Registers */\n\tregs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);\n\tprintk(KERN_DEBUG \"ixgbe_get_regs_3\\n\");\n\tregs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);\n\tregs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);\n\tregs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);\n\tregs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);\n\tregs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\tregs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);\n\tregs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);\n\n\tprintk(KERN_DEBUG \"ixgbe_get_regs_4\\n\");\n\n\t/* NVM Register */\n\tregs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);\n\tregs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);\n\tregs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);\n\tregs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);\n\tregs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);\n\tregs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);\n\tregs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);\n\tregs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);\n\tregs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);\n\tregs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);\n\n\t/* Interrupt */\n\t/* don't read EICR because it can clear interrupt causes, instead\n\t * read EICS which is a shadow but doesn't clear EICR */\n\tregs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);\n\tregs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);\n\tregs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);\n\tregs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);\n\tregs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);\n\tregs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);\n\tregs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));\n\tregs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));\n\tregs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);\n\tregs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);\n\tregs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));\n\tregs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);\n\n\t/* Flow Control */\n\tregs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);\n\tregs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));\n\tregs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));\n\tregs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));\n\tregs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));\n\tfor (i = 0; i < 8; i++) {\n\t\tswitch (hw->mac.type) {\n\t\tcase ixgbe_mac_82598EB:\n\t\t\tregs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));\n\t\t\tregs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));\n\t\t\tbreak;\n\t\tcase ixgbe_mac_82599EB:\n\t\tcase ixgbe_mac_X540:\n\t\t\tregs_buff[35 + i] = IXGBE_READ_REG(hw,\n\t\t\t\t\t\t\t IXGBE_FCRTL_82599(i));\n\t\t\tregs_buff[43 + i] = IXGBE_READ_REG(hw,\n\t\t\t\t\t\t\t IXGBE_FCRTH_82599(i));\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\tregs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);\n\tregs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);\n\n\t/* Receive DMA */\n\tfor (i = 0; i < 64; i++)\n\t\tregs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));\n\tfor (i = 0; i < 64; i++)\n\t\tregs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));\n\tfor (i = 0; i < 64; i++)\n\t\tregs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));\n\tfor (i = 0; i < 64; i++)\n\t\tregs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));\n\tfor (i = 0; i < 64; i++)\n\t\tregs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));\n\tfor (i = 0; i < 64; i++)\n\t\tregs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));\n\tfor (i = 0; i < 16; i++)\n\t\tregs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));\n\tfor (i = 0; i < 16; i++)\n\t\tregs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));\n\tregs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));\n\tregs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n\tregs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);\n\n\t/* Receive */\n\tregs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);\n\tregs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);\n\tfor (i = 0; i < 16; i++)\n\t\tregs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));\n\tfor (i = 0; i < 16; i++)\n\t\tregs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));\n\tregs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));\n\tregs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\tregs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n\tregs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);\n\tregs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);\n\tregs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));\n\tregs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);\n\n\t/* Transmit */\n\tfor (i = 0; i < 32; i++)\n\t\tregs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));\n\tfor (i = 0; i < 32; i++)\n\t\tregs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));\n\tfor (i = 0; i < 32; i++)\n\t\tregs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));\n\tfor (i = 0; i < 32; i++)\n\t\tregs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));\n\tfor (i = 0; i < 32; i++)\n\t\tregs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));\n\tfor (i = 0; i < 32; i++)\n\t\tregs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));\n\tfor (i = 0; i < 32; i++)\n\t\tregs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));\n\tfor (i = 0; i < 32; i++)\n\t\tregs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));\n\tregs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);\n\tfor (i = 0; i < 16; i++)\n\t\tregs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));\n\tregs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));\n\tregs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);\n\n\t/* Wake Up */\n\tregs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);\n\tregs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);\n\tregs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);\n\tregs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);\n\tregs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);\n\tregs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);\n\tregs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);\n\tregs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);\n\tregs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));\n\n\t/* DCB */\n\tregs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);\n\tregs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);\n\tregs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);\n\tregs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));\n\n\t/* Statistics */\n\tregs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);\n\tregs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);\n\tregs_buff[883] = IXGBE_GET_STAT(adapter, errbc);\n\tregs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);\n\tregs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);\n\tregs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);\n\tregs_buff[895] = IXGBE_GET_STAT(adapter, rlec);\n\tregs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);\n\tregs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);\n\tregs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);\n\tregs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);\n\tregs_buff[932] = IXGBE_GET_STAT(adapter, prc64);\n\tregs_buff[933] = IXGBE_GET_STAT(adapter, prc127);\n\tregs_buff[934] = IXGBE_GET_STAT(adapter, prc255);\n\tregs_buff[935] = IXGBE_GET_STAT(adapter, prc511);\n\tregs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);\n\tregs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);\n\tregs_buff[938] = IXGBE_GET_STAT(adapter, gprc);\n\tregs_buff[939] = IXGBE_GET_STAT(adapter, bprc);\n\tregs_buff[940] = IXGBE_GET_STAT(adapter, mprc);\n\tregs_buff[941] = IXGBE_GET_STAT(adapter, gptc);\n\tregs_buff[942] = IXGBE_GET_STAT(adapter, gorc);\n\tregs_buff[944] = IXGBE_GET_STAT(adapter, gotc);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);\n\tregs_buff[954] = IXGBE_GET_STAT(adapter, ruc);\n\tregs_buff[955] = IXGBE_GET_STAT(adapter, rfc);\n\tregs_buff[956] = IXGBE_GET_STAT(adapter, roc);\n\tregs_buff[957] = IXGBE_GET_STAT(adapter, rjc);\n\tregs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);\n\tregs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);\n\tregs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);\n\tregs_buff[961] = IXGBE_GET_STAT(adapter, tor);\n\tregs_buff[963] = IXGBE_GET_STAT(adapter, tpr);\n\tregs_buff[964] = IXGBE_GET_STAT(adapter, tpt);\n\tregs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);\n\tregs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);\n\tregs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);\n\tregs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);\n\tregs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);\n\tregs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);\n\tregs_buff[971] = IXGBE_GET_STAT(adapter, mptc);\n\tregs_buff[972] = IXGBE_GET_STAT(adapter, bptc);\n\tregs_buff[973] = IXGBE_GET_STAT(adapter, xec);\n\tfor (i = 0; i < 16; i++)\n\t\tregs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);\n\tfor (i = 0; i < 16; i++)\n\t\tregs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);\n\tfor (i = 0; i < 16; i++)\n\t\tregs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);\n\tfor (i = 0; i < 16; i++)\n\t\tregs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);\n\n\t/* MAC */\n\tregs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);\n\tregs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);\n\tregs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);\n\tregs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);\n\tregs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);\n\tregs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);\n\tregs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);\n\tregs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);\n\tregs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);\n\tregs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);\n\tregs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);\n\tregs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);\n\tregs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);\n\tregs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);\n\tregs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);\n\tregs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);\n\tregs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);\n\tregs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);\n\tregs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);\n\tregs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);\n\tregs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);\n\tregs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);\n\tregs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);\n\tregs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);\n\tregs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);\n\tregs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);\n\tregs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\tregs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);\n\tregs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);\n\tregs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);\n\tregs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);\n\tregs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);\n\tregs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);\n\n\t/* Diagnostic */\n\tregs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));\n\tregs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));\n\tregs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);\n\tregs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));\n\tregs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);\n\tfor (i = 0; i < 4; i++)\n\t\tregs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));\n\tregs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);\n\tregs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);\n\tregs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);\n\tregs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);\n\tregs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);\n\tregs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);\n\tregs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);\n\tregs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);\n\tregs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);\n\tregs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);\n\tregs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);\n\tfor (i = 0; i < 8; i++)\n\t\tregs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));\n\tregs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);\n\tregs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);\n\tregs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);\n\tregs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);\n\tregs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);\n\tregs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);\n\tregs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);\n\tregs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);\n\tregs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);\n\n\t/* 82599 X540 specific registers */\n\tregs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);\n}\n\nstatic int ixgbe_get_eeprom_len(struct net_device *netdev)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\treturn adapter->hw.eeprom.word_size * 2;\n}\n\nstatic int ixgbe_get_eeprom(struct net_device *netdev,\n\t\t\t struct ethtool_eeprom *eeprom, u8 *bytes)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tu16 *eeprom_buff;\n\tint first_word, last_word, eeprom_len;\n\tint ret_val = 0;\n\tu16 i;\n\n\tif (eeprom->len == 0)\n\t\treturn -EINVAL;\n\n\teeprom->magic = hw->vendor_id | (hw->device_id << 16);\n\n\tfirst_word = eeprom->offset >> 1;\n\tlast_word = (eeprom->offset + eeprom->len - 1) >> 1;\n\teeprom_len = last_word - first_word + 1;\n\n\teeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);\n\tif (!eeprom_buff)\n\t\treturn -ENOMEM;\n\n\tret_val = ixgbe_read_eeprom_buffer(hw, first_word, eeprom_len,\n\t\t\t\t\t eeprom_buff);\n\n\t/* Device's eeprom is always little-endian, word addressable */\n\tfor (i = 0; i < eeprom_len; i++)\n\t\tle16_to_cpus(&eeprom_buff[i]);\n\n\tmemcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);\n\tkfree(eeprom_buff);\n\n\treturn ret_val;\n}\n\nstatic int ixgbe_set_eeprom(struct net_device *netdev,\n\t\t\t struct ethtool_eeprom *eeprom, u8 *bytes)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tu16 *eeprom_buff;\n\tvoid *ptr;\n\tint max_len, first_word, last_word, ret_val = 0;\n\tu16 i;\n\n\tif (eeprom->len == 0)\n\t\treturn -EINVAL;\n\n\tif (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))\n\t\treturn -EINVAL;\n\n\tmax_len = hw->eeprom.word_size * 2;\n\n\tfirst_word = eeprom->offset >> 1;\n\tlast_word = (eeprom->offset + eeprom->len - 1) >> 1;\n\teeprom_buff = kmalloc(max_len, GFP_KERNEL);\n\tif (!eeprom_buff)\n\t\treturn -ENOMEM;\n\n\tptr = eeprom_buff;\n\n\tif (eeprom->offset & 1) {\n\t\t/*\n\t\t * need read/modify/write of first changed EEPROM word\n\t\t * only the second byte of the word is being modified\n\t\t */\n\t\tret_val = ixgbe_read_eeprom(hw, first_word, &eeprom_buff[0]);\n\t\tif (ret_val)\n\t\t\tgoto err;\n\n\t\tptr++;\n\t}\n\tif (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {\n\t\t/*\n\t\t * need read/modify/write of last changed EEPROM word\n\t\t * only the first byte of the word is being modified\n\t\t */\n\t\tret_val = ixgbe_read_eeprom(hw, last_word,\n\t\t\t\t\t &eeprom_buff[last_word - first_word]);\n\t\tif (ret_val)\n\t\t\tgoto err;\n\t}\n\n\t/* Device's eeprom is always little-endian, word addressable */\n\tfor (i = 0; i < last_word - first_word + 1; i++)\n\t\tle16_to_cpus(&eeprom_buff[i]);\n\n\tmemcpy(ptr, bytes, eeprom->len);\n\n\tfor (i = 0; i < last_word - first_word + 1; i++)\n\t\tcpu_to_le16s(&eeprom_buff[i]);\n\n\tret_val = ixgbe_write_eeprom_buffer(hw, first_word,\n\t\t\t\t\t last_word - first_word + 1,\n\t\t\t\t\t eeprom_buff);\n\n\t/* Update the checksum */\n\tif (ret_val == 0)\n\t\tixgbe_update_eeprom_checksum(hw);\n\nerr:\n\tkfree(eeprom_buff);\n\treturn ret_val;\n}\n\nstatic void ixgbe_get_drvinfo(struct net_device *netdev,\n\t\t\t struct ethtool_drvinfo *drvinfo)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\n\tstrlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));\n\n\tstrlcpy(drvinfo->version, ixgbe_driver_version,\n\t\t\t\tsizeof(drvinfo->version));\n\n\tstrlcpy(drvinfo->fw_version, adapter->eeprom_id,\n\t\t\t\tsizeof(drvinfo->fw_version));\n\n\tstrlcpy(drvinfo->bus_info, pci_name(adapter->pdev),\n\t\t\t\tsizeof(drvinfo->bus_info));\n\n\tdrvinfo->n_stats = IXGBE_STATS_LEN;\n\tdrvinfo->testinfo_len = IXGBE_TEST_LEN;\n\tdrvinfo->regdump_len = ixgbe_get_regs_len(netdev);\n}\n\nstatic void ixgbe_get_ringparam(struct net_device *netdev,\n\t\t\t\tstruct ethtool_ringparam *ring)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\n\tring->rx_max_pending = IXGBE_MAX_RXD;\n\tring->tx_max_pending = IXGBE_MAX_TXD;\n\tring->rx_mini_max_pending = 0;\n\tring->rx_jumbo_max_pending = 0;\n\tring->rx_pending = adapter->rx_ring_count;\n\tring->tx_pending = adapter->tx_ring_count;\n\tring->rx_mini_pending = 0;\n\tring->rx_jumbo_pending = 0;\n}\n\nstatic int ixgbe_set_ringparam(struct net_device *netdev,\n\t\t\t struct ethtool_ringparam *ring)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_ring *tx_ring = NULL, *rx_ring = NULL;\n\tu32 new_rx_count, new_tx_count;\n\tint i, err = 0;\n\n\tif ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))\n\t\treturn -EINVAL;\n\n\tnew_tx_count = clamp_t(u32, ring->tx_pending,\n\t\t\t IXGBE_MIN_TXD, IXGBE_MAX_TXD);\n\tnew_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);\n\n\tnew_rx_count = clamp_t(u32, ring->rx_pending,\n\t\t\t IXGBE_MIN_RXD, IXGBE_MAX_RXD);\n\tnew_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);\n\n\t/* if nothing to do return success */\n\tif ((new_tx_count == adapter->tx_ring_count) &&\n\t (new_rx_count == adapter->rx_ring_count))\n\t\treturn 0;\n\n\twhile (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))\n\t\tusleep_range(1000, 2000);\n\n\tif (!netif_running(adapter->netdev)) {\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\t\tadapter->tx_ring[i]->count = new_tx_count;\n\t\tfor (i = 0; i < adapter->num_rx_queues; i++)\n\t\t\tadapter->rx_ring[i]->count = new_rx_count;\n\t\tadapter->tx_ring_count = new_tx_count;\n\t\tadapter->rx_ring_count = new_rx_count;\n\t\tgoto clear_reset;\n\t}\n\n\t/* alloc updated Tx resources */\n\tif (new_tx_count != adapter->tx_ring_count) {\n\t\ttx_ring = vmalloc(adapter->num_tx_queues * sizeof(*tx_ring));\n\t\tif (!tx_ring) {\n\t\t\terr = -ENOMEM;\n\t\t\tgoto clear_reset;\n\t\t}\n\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\t\t/* clone ring and setup updated count */\n\t\t\ttx_ring[i] = *adapter->tx_ring[i];\n\t\t\ttx_ring[i].count = new_tx_count;\n\t\t\terr = ixgbe_setup_tx_resources(&tx_ring[i]);\n\t\t\tif (err) {\n\t\t\t\twhile (i) {\n\t\t\t\t\ti--;\n\t\t\t\t\tixgbe_free_tx_resources(&tx_ring[i]);\n\t\t\t\t}\n\n\t\t\t\tvfree(tx_ring);\n\t\t\t\ttx_ring = NULL;\n\n\t\t\t\tgoto clear_reset;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* alloc updated Rx resources */\n\tif (new_rx_count != adapter->rx_ring_count) {\n\t\trx_ring = vmalloc(adapter->num_rx_queues * sizeof(*rx_ring));\n\t\tif (!rx_ring) {\n\t\t\terr = -ENOMEM;\n\t\t\tgoto clear_reset;\n\t\t}\n\n\t\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\t\t/* clone ring and setup updated count */\n\t\t\trx_ring[i] = *adapter->rx_ring[i];\n\t\t\trx_ring[i].count = new_rx_count;\n\t\t\terr = ixgbe_setup_rx_resources(&rx_ring[i]);\n\t\t\tif (err) {\n\t\t\t\twhile (i) {\n\t\t\t\t\ti--;\n\t\t\t\t\tixgbe_free_rx_resources(&rx_ring[i]);\n\t\t\t\t}\n\n\t\t\t\tvfree(rx_ring);\n\t\t\t\trx_ring = NULL;\n\n\t\t\t\tgoto clear_reset;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* bring interface down to prepare for update */\n\tixgbe_down(adapter);\n\n\t/* Tx */\n\tif (tx_ring) {\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\t\tixgbe_free_tx_resources(adapter->tx_ring[i]);\n\t\t\t*adapter->tx_ring[i] = tx_ring[i];\n\t\t}\n\t\tadapter->tx_ring_count = new_tx_count;\n\n\t\tvfree(tx_ring);\n\t\ttx_ring = NULL;\n\t}\n\n\t/* Rx */\n\tif (rx_ring) {\n\t\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\t\tixgbe_free_rx_resources(adapter->rx_ring[i]);\n\t\t\t*adapter->rx_ring[i] = rx_ring[i];\n\t\t}\n\t\tadapter->rx_ring_count = new_rx_count;\n\n\t\tvfree(rx_ring);\n\t\trx_ring = NULL;\n\t}\n\n\t/* restore interface using new values */\n\tixgbe_up(adapter);\n\nclear_reset:\n\t/* free Tx resources if Rx error is encountered */\n\tif (tx_ring) {\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\t\tixgbe_free_tx_resources(&tx_ring[i]);\n\t\tvfree(tx_ring);\n\t}\n\n\tclear_bit(__IXGBE_RESETTING, &adapter->state);\n\treturn err;\n}\n\n#ifndef HAVE_ETHTOOL_GET_SSET_COUNT\nstatic int ixgbe_get_stats_count(struct net_device *netdev)\n{\n\treturn IXGBE_STATS_LEN;\n}\n\n#else /* HAVE_ETHTOOL_GET_SSET_COUNT */\nstatic int ixgbe_get_sset_count(struct net_device *netdev, int sset)\n{\n\tswitch (sset) {\n\tcase ETH_SS_TEST:\n\t\treturn IXGBE_TEST_LEN;\n\tcase ETH_SS_STATS:\n\t\treturn IXGBE_STATS_LEN;\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n}\n\n#endif /* HAVE_ETHTOOL_GET_SSET_COUNT */\nstatic void ixgbe_get_ethtool_stats(struct net_device *netdev,\n\t\t\t\t struct ethtool_stats *stats, u64 *data)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n#ifdef HAVE_NETDEV_STATS_IN_NETDEV\n\tstruct net_device_stats *net_stats = &netdev->stats;\n#else\n\tstruct net_device_stats *net_stats = &adapter->net_stats;\n#endif\n\tu64 *queue_stat;\n\tint stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);\n\tint i, j, k;\n\tchar *p;\n\n\tprintk(KERN_DEBUG \"ixgbe_stats 0\\n\");\n\tixgbe_update_stats(adapter);\n\tprintk(KERN_DEBUG \"ixgbe_stats 1\\n\");\n\n\tfor (i = 0; i < IXGBE_NETDEV_STATS_LEN; i++) {\n\t\tp = (char *)net_stats + ixgbe_gstrings_net_stats[i].stat_offset;\n\t\tdata[i] = (ixgbe_gstrings_net_stats[i].sizeof_stat ==\n\t\t\tsizeof(u64)) ? *(u64 *)p : *(u32 *)p;\n\t}\n\tfor (j = 0; j < IXGBE_GLOBAL_STATS_LEN; j++, i++) {\n\t\tp = (char *)adapter + ixgbe_gstrings_stats[j].stat_offset;\n\t\tdata[i] = (ixgbe_gstrings_stats[j].sizeof_stat ==\n\t\t\t sizeof(u64)) ? *(u64 *)p : *(u32 *)p;\n\t}\n\tprintk(KERN_DEBUG \"ixgbe_stats 2\\n\");\n#ifdef NO_VNIC\n\tfor (j = 0; j < adapter->num_tx_queues; j++) {\n\t\tqueue_stat = (u64 *)&adapter->tx_ring[j]->stats;\n\t\tfor (k = 0; k < stat_count; k++)\n\t\t\tdata[i + k] = queue_stat[k];\n\t\ti += k;\n\t}\n\tfor (j = 0; j < adapter->num_rx_queues; j++) {\n\t\tqueue_stat = (u64 *)&adapter->rx_ring[j]->stats;\n\t\tfor (k = 0; k < stat_count; k++)\n\t\t\tdata[i + k] = queue_stat[k];\n\t\ti += k;\n\t}\n\tprintk(KERN_DEBUG \"ixgbe_stats 3\\n\");\n#endif\n\tif (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {\n\t\tfor (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {\n\t\t\tdata[i++] = adapter->stats.pxontxc[j];\n\t\t\tdata[i++] = adapter->stats.pxofftxc[j];\n\t\t}\n\t\tfor (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {\n\t\t\tdata[i++] = adapter->stats.pxonrxc[j];\n\t\t\tdata[i++] = adapter->stats.pxoffrxc[j];\n\t\t}\n\t}\n\tprintk(KERN_DEBUG \"ixgbe_stats 4\\n\");\n\tstat_count = sizeof(struct vf_stats) / sizeof(u64);\n\tfor (j = 0; j < adapter->num_vfs; j++) {\n\t\tqueue_stat = (u64 *)&adapter->vfinfo[j].vfstats;\n\t\tfor (k = 0; k < stat_count; k++)\n\t\t\tdata[i + k] = queue_stat[k];\n\t\tqueue_stat = (u64 *)&adapter->vfinfo[j].saved_rst_vfstats;\n\t\tfor (k = 0; k < stat_count; k++)\n\t\t\tdata[i + k] += queue_stat[k];\n\t\ti += k;\n\t}\n}\n\nstatic void ixgbe_get_strings(struct net_device *netdev, u32 stringset,\n\t\t\t u8 *data)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tchar *p = (char *)data;\n\tint i;\n\n\tswitch (stringset) {\n\tcase ETH_SS_TEST:\n\t\tmemcpy(data, *ixgbe_gstrings_test,\n\t\t\tIXGBE_TEST_LEN * ETH_GSTRING_LEN);\n\t\tbreak;\n\tcase ETH_SS_STATS:\n\t\tfor (i = 0; i < IXGBE_NETDEV_STATS_LEN; i++) {\n\t\t\tmemcpy(p, ixgbe_gstrings_net_stats[i].stat_string,\n\t\t\t ETH_GSTRING_LEN);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t}\n\t\tfor (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {\n\t\t\tmemcpy(p, ixgbe_gstrings_stats[i].stat_string,\n\t\t\t ETH_GSTRING_LEN);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t}\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\t\tsprintf(p, \"tx_queue_%u_packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"tx_queue_%u_bytes\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t}\n\t\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\t\tsprintf(p, \"rx_queue_%u_packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"rx_queue_%u_bytes\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t}\n\t\tif (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {\n\t\t\tfor (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {\n\t\t\t\tsprintf(p, \"tx_pb_%u_pxon\", i);\n\t\t\t\tp += ETH_GSTRING_LEN;\n\t\t\t\tsprintf(p, \"tx_pb_%u_pxoff\", i);\n\t\t\t\tp += ETH_GSTRING_LEN;\n\t\t\t}\n\t\t\tfor (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {\n\t\t\t\tsprintf(p, \"rx_pb_%u_pxon\", i);\n\t\t\t\tp += ETH_GSTRING_LEN;\n\t\t\t\tsprintf(p, \"rx_pb_%u_pxoff\", i);\n\t\t\t\tp += ETH_GSTRING_LEN;\n\t\t\t}\n\t\t}\n\t\tfor (i = 0; i < adapter->num_vfs; i++) {\n\t\t\tsprintf(p, \"VF %d Rx Packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"VF %d Rx Bytes\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"VF %d Tx Packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"VF %d Tx Bytes\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t\tsprintf(p, \"VF %d MC Packets\", i);\n\t\t\tp += ETH_GSTRING_LEN;\n\t\t}\n\t\t/* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */\n\t\tbreak;\n\t}\n}\n\nstatic int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tbool link_up;\n\tu32 link_speed = 0;\n\t*data = 0;\n\n\thw->mac.ops.check_link(hw, &link_speed, &link_up, true);\n\tif (link_up)\n\t\treturn *data;\n\telse\n\t\t*data = 1;\n\treturn *data;\n}\n\n/* ethtool register test data */\nstruct ixgbe_reg_test {\n\tu16 reg;\n\tu8 array_len;\n\tu8 test_type;\n\tu32 mask;\n\tu32 write;\n};\n\n/* In the hardware, registers are laid out either singly, in arrays\n * spaced 0x40 bytes apart, or in contiguous tables. We assume\n * most tests take place on arrays or single registers (handled\n * as a single-element array) and special-case the tables.\n * Table tests are always pattern tests.\n *\n * We also make provision for some required setup steps by specifying\n * registers to be written without any read-back testing.\n */\n\n#define PATTERN_TEST\t1\n#define SET_READ_TEST\t2\n#define WRITE_NO_TEST\t3\n#define TABLE32_TEST\t4\n#define TABLE64_TEST_LO\t5\n#define TABLE64_TEST_HI\t6\n\n/* default 82599 register test */\nstatic struct ixgbe_reg_test reg_test_82599[] = {\n\t{ IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },\n\t{ IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },\n\t{ IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },\n\t{ IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },\n\t{ IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },\n\t{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },\n\t{ IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },\n\t{ IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },\n\t{ IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },\n\t{ IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },\n\t{ IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },\n\t{ IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ 0, 0, 0, 0 }\n};\n\n/* default 82598 register test */\nstatic struct ixgbe_reg_test reg_test_82598[] = {\n\t{ IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },\n\t{ IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },\n\t{ IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },\n\t{ IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },\n\t/* Enable all four RX queues before testing. */\n\t{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },\n\t/* RDH is read-only for 82598, only test RDT. */\n\t{ IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },\n\t{ IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },\n\t{ IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },\n\t{ IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },\n\t{ IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },\n\t{ IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },\n\t{ IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },\n\t{ IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },\n\t{ IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },\n\t{ IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },\n\t{ 0, 0, 0, 0 }\n};\n\n#define REG_PATTERN_TEST(R, M, W)\t\t\t\t\t \\\n{\t\t\t\t\t\t\t\t\t \\\n\tu32 pat, val, before;\t\t\t\t\t\t \\\n\tconst u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \\\n\tfor (pat = 0; pat < ARRAY_SIZE(_test); pat++) {\t\t\t \\\n\t\tbefore = readl(adapter->hw.hw_addr + R);\t\t \\\n\t\twritel((_test[pat] & W), (adapter->hw.hw_addr + R));\t \\\n\t\tval = readl(adapter->hw.hw_addr + R);\t\t\t \\\n\t\tif (val != (_test[pat] & W & M)) {\t\t\t \\\n\t\t\te_err(drv, \"pattern test reg %04X failed: got \"\t \\\n\t\t\t \"0x%08X expected 0x%08X\\n\",\t\t \\\n\t\t\t\tR, val, (_test[pat] & W & M));\t\t \\\n\t\t\t*data = R;\t\t\t\t\t \\\n\t\t\twritel(before, adapter->hw.hw_addr + R);\t \\\n\t\t\treturn 1;\t\t\t\t\t \\\n\t\t}\t\t\t\t\t\t\t \\\n\t\twritel(before, adapter->hw.hw_addr + R);\t\t \\\n\t}\t\t\t\t\t\t\t\t \\\n}\n\n#define REG_SET_AND_CHECK(R, M, W)\t\t\t\t\t \\\n{\t\t\t\t\t\t\t\t\t \\\n\tu32 val, before;\t\t\t\t\t\t \\\n\tbefore = readl(adapter->hw.hw_addr + R);\t\t\t \\\n\twritel((W & M), (adapter->hw.hw_addr + R));\t\t\t \\\n\tval = readl(adapter->hw.hw_addr + R);\t\t\t\t \\\n\tif ((W & M) != (val & M)) {\t\t\t\t\t \\\n\t\te_err(drv, \"set/check reg %04X test failed: got 0x%08X \" \\\n\t\t \"expected 0x%08X\\n\", R, (val & M), (W & M));\t \\\n\t\t*data = R;\t\t\t\t\t\t \\\n\t\twritel(before, (adapter->hw.hw_addr + R));\t\t \\\n\t\treturn 1;\t\t\t\t\t\t \\\n\t}\t\t\t\t\t\t\t\t \\\n\twritel(before, (adapter->hw.hw_addr + R));\t\t\t \\\n}\n\nstatic int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)\n{\n\tstruct ixgbe_reg_test *test;\n\tu32 value, status_before, status_after;\n\tu32 i, toggle;\n\n\tswitch (adapter->hw.mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\ttoggle = 0x7FFFF3FF;\n\t\ttest = reg_test_82598;\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\t\ttoggle = 0x7FFFF30F;\n\t\ttest = reg_test_82599;\n\t\tbreak;\n\tdefault:\n\t\t*data = 1;\n\t\treturn 1;\n\t\tbreak;\n\t}\n\n\t/*\n\t * Because the status register is such a special case,\n\t * we handle it separately from the rest of the register\n\t * tests. Some bits are read-only, some toggle, and some\n\t * are writeable on newer MACs.\n\t */\n\tstatus_before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);\n\tvalue = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);\n\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);\n\tstatus_after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;\n\tif (value != status_after) {\n\t\te_err(drv, \"failed STATUS register test got: \"\n\t\t \"0x%08X expected: 0x%08X\\n\", status_after, value);\n\t\t*data = 1;\n\t\treturn 1;\n\t}\n\t/* restore previous status */\n\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, status_before);\n\n\t/*\n\t * Perform the remainder of the register test, looping through\n\t * the test table until we either fail or reach the null entry.\n\t */\n\twhile (test->reg) {\n\t\tfor (i = 0; i < test->array_len; i++) {\n\t\t\tswitch (test->test_type) {\n\t\t\tcase PATTERN_TEST:\n\t\t\t\tREG_PATTERN_TEST(test->reg + (i * 0x40),\n\t\t\t\t\t\ttest->mask,\n\t\t\t\t\t\ttest->write);\n\t\t\t\tbreak;\n\t\t\tcase SET_READ_TEST:\n\t\t\t\tREG_SET_AND_CHECK(test->reg + (i * 0x40),\n\t\t\t\t\t\ttest->mask,\n\t\t\t\t\t\ttest->write);\n\t\t\t\tbreak;\n\t\t\tcase WRITE_NO_TEST:\n\t\t\t\twritel(test->write,\n\t\t\t\t (adapter->hw.hw_addr + test->reg)\n\t\t\t\t + (i * 0x40));\n\t\t\t\tbreak;\n\t\t\tcase TABLE32_TEST:\n\t\t\t\tREG_PATTERN_TEST(test->reg + (i * 4),\n\t\t\t\t\t\ttest->mask,\n\t\t\t\t\t\ttest->write);\n\t\t\t\tbreak;\n\t\t\tcase TABLE64_TEST_LO:\n\t\t\t\tREG_PATTERN_TEST(test->reg + (i * 8),\n\t\t\t\t\t\ttest->mask,\n\t\t\t\t\t\ttest->write);\n\t\t\t\tbreak;\n\t\t\tcase TABLE64_TEST_HI:\n\t\t\t\tREG_PATTERN_TEST((test->reg + 4) + (i * 8),\n\t\t\t\t\t\ttest->mask,\n\t\t\t\t\t\ttest->write);\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\ttest++;\n\t}\n\n\t*data = 0;\n\treturn 0;\n}\n\nstatic int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)\n{\n\tif (ixgbe_validate_eeprom_checksum(&adapter->hw, NULL))\n\t\t*data = 1;\n\telse\n\t\t*data = 0;\n\treturn *data;\n}\n\nstatic irqreturn_t ixgbe_test_intr(int irq, void *data)\n{\n\tstruct net_device *netdev = (struct net_device *) data;\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\n\tadapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);\n\n\treturn IRQ_HANDLED;\n}\n\nstatic int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)\n{\n\tstruct net_device *netdev = adapter->netdev;\n\tu32 mask, i = 0, shared_int = true;\n\tu32 irq = adapter->pdev->irq;\n\n\t*data = 0;\n\n\t/* Hook up test interrupt handler just for this test */\n\tif (adapter->msix_entries) {\n\t\t/* NOTE: we don't test MSI-X interrupts here, yet */\n\t\treturn 0;\n\t} else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {\n\t\tshared_int = false;\n\t\tif (request_irq(irq, &ixgbe_test_intr, 0, netdev->name,\n\t\t\t\tnetdev)) {\n\t\t\t*data = 1;\n\t\t\treturn -1;\n\t\t}\n\t} else if (!request_irq(irq, &ixgbe_test_intr, IRQF_PROBE_SHARED,\n\t\t\t\tnetdev->name, netdev)) {\n\t\tshared_int = false;\n\t} else if (request_irq(irq, &ixgbe_test_intr, IRQF_SHARED,\n\t\t\t netdev->name, netdev)) {\n\t\t*data = 1;\n\t\treturn -1;\n\t}\n\te_info(hw, \"testing %s interrupt\\n\",\n\t (shared_int ? \"shared\" : \"unshared\"));\n\n\t/* Disable all the interrupts */\n\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);\n\tIXGBE_WRITE_FLUSH(&adapter->hw);\n\tusleep_range(10000, 20000);\n\n\t/* Test each interrupt */\n\tfor (; i < 10; i++) {\n\t\t/* Interrupt to test */\n\t\tmask = 1 << i;\n\n\t\tif (!shared_int) {\n\t\t\t/*\n\t\t\t * Disable the interrupts to be reported in\n\t\t\t * the cause register and then force the same\n\t\t\t * interrupt and see if one gets posted. If\n\t\t\t * an interrupt was posted to the bus, the\n\t\t\t * test failed.\n\t\t\t */\n\t\t\tadapter->test_icr = 0;\n\t\t\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,\n\t\t\t\t\t~mask & 0x00007FFF);\n\t\t\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,\n\t\t\t\t\t~mask & 0x00007FFF);\n\t\t\tIXGBE_WRITE_FLUSH(&adapter->hw);\n\t\t\tusleep_range(10000, 20000);\n\n\t\t\tif (adapter->test_icr & mask) {\n\t\t\t\t*data = 3;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/*\n\t\t * Enable the interrupt to be reported in the cause\n\t\t * register and then force the same interrupt and see\n\t\t * if one gets posted. If an interrupt was not posted\n\t\t * to the bus, the test failed.\n\t\t */\n\t\tadapter->test_icr = 0;\n\t\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);\n\t\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);\n\t\tIXGBE_WRITE_FLUSH(&adapter->hw);\n\t\tusleep_range(10000, 20000);\n\n\t\tif (!(adapter->test_icr & mask)) {\n\t\t\t*data = 4;\n\t\t\tbreak;\n\t\t}\n\n\t\tif (!shared_int) {\n\t\t\t/*\n\t\t\t * Disable the other interrupts to be reported in\n\t\t\t * the cause register and then force the other\n\t\t\t * interrupts and see if any get posted. If\n\t\t\t * an interrupt was posted to the bus, the\n\t\t\t * test failed.\n\t\t\t */\n\t\t\tadapter->test_icr = 0;\n\t\t\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,\n\t\t\t\t\t~mask & 0x00007FFF);\n\t\t\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,\n\t\t\t\t\t~mask & 0x00007FFF);\n\t\t\tIXGBE_WRITE_FLUSH(&adapter->hw);\n\t\t\tusleep_range(10000, 20000);\n\n\t\t\tif (adapter->test_icr) {\n\t\t\t\t*data = 5;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Disable all the interrupts */\n\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);\n\tIXGBE_WRITE_FLUSH(&adapter->hw);\n\tusleep_range(10000, 20000);\n\n\t/* Unhook test interrupt handler */\n\tfree_irq(irq, netdev);\n\n\treturn *data;\n}\n\n\n\nstatic int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tu32 reg_data;\n\n\t/* X540 needs to set the MACC.FLU bit to force link up */\n\tif (adapter->hw.mac.type == ixgbe_mac_X540) {\n\t\treg_data = IXGBE_READ_REG(hw, IXGBE_MACC);\n\t\treg_data |= IXGBE_MACC_FLU;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);\n\t}\n\n\t/* right now we only support MAC loopback in the driver */\n\treg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);\n\t/* Setup MAC loopback */\n\treg_data |= IXGBE_HLREG0_LPBK;\n\tIXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);\n\n\treg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\treg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;\n\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);\n\n\treg_data = IXGBE_READ_REG(hw, IXGBE_AUTOC);\n\treg_data &= ~IXGBE_AUTOC_LMS_MASK;\n\treg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;\n\tIXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);\n\tIXGBE_WRITE_FLUSH(hw);\n\tusleep_range(10000, 20000);\n\n\t/* Disable Atlas Tx lanes; re-enabled in reset path */\n\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\tu8 atlas;\n\n\t\tixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);\n\t\tatlas |= IXGBE_ATLAS_PDN_TX_REG_EN;\n\t\tixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);\n\n\t\tixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);\n\t\tatlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;\n\t\tixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);\n\n\t\tixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);\n\t\tatlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;\n\t\tixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);\n\n\t\tixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);\n\t\tatlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;\n\t\tixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);\n\t}\n\n\treturn 0;\n}\n\nstatic void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)\n{\n\tu32 reg_data;\n\n\treg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);\n\treg_data &= ~IXGBE_HLREG0_LPBK;\n\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);\n}\n\n\n\n\n\n\nstatic int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)\n{\n\n\t//*data = ixgbe_setup_desc_rings(adapter);\n\t//if (*data)\n\t//\tgoto out;\n\t*data = ixgbe_setup_loopback_test(adapter);\n\tif (*data)\n\t\tgoto err_loopback;\n\t//*data = ixgbe_run_loopback_test(adapter);\n\tixgbe_loopback_cleanup(adapter);\n\nerr_loopback:\n\t//ixgbe_free_desc_rings(adapter);\n//out:\n\treturn *data;\n\n}\n\n#ifndef HAVE_ETHTOOL_GET_SSET_COUNT\nstatic int ixgbe_diag_test_count(struct net_device *netdev)\n{\n\treturn IXGBE_TEST_LEN;\n}\n\n#endif /* HAVE_ETHTOOL_GET_SSET_COUNT */\nstatic void ixgbe_diag_test(struct net_device *netdev,\n\t\t\t struct ethtool_test *eth_test, u64 *data)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tbool if_running = netif_running(netdev);\n\n\tset_bit(__IXGBE_TESTING, &adapter->state);\n\tif (eth_test->flags == ETH_TEST_FL_OFFLINE) {\n\t\t/* Offline tests */\n\n\t\te_info(hw, \"offline testing starting\\n\");\n\n\t\t/* Link test performed before hardware reset so autoneg doesn't\n\t\t * interfere with test result */\n\t\tif (ixgbe_link_test(adapter, &data[4]))\n\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\n\t\tif (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {\n\t\t\tint i;\n\t\t\tfor (i = 0; i < adapter->num_vfs; i++) {\n\t\t\t\tif (adapter->vfinfo[i].clear_to_send) {\n\t\t\t\t\te_warn(drv, \"Please take active VFS \"\n\t\t\t\t\t \"offline and restart the \"\n\t\t\t\t\t \"adapter before running NIC \"\n\t\t\t\t\t \"diagnostics\\n\");\n\t\t\t\t\tdata[0] = 1;\n\t\t\t\t\tdata[1] = 1;\n\t\t\t\t\tdata[2] = 1;\n\t\t\t\t\tdata[3] = 1;\n\t\t\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\t\t\t\t\tclear_bit(__IXGBE_TESTING,\n\t\t\t\t\t\t &adapter->state);\n\t\t\t\t\tgoto skip_ol_tests;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\tif (if_running)\n\t\t\t/* indicate we're in test mode */\n\t\t\tdev_close(netdev);\n\t\telse\n\t\t\tixgbe_reset(adapter);\n\n\t\te_info(hw, \"register testing starting\\n\");\n\t\tif (ixgbe_reg_test(adapter, &data[0]))\n\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\n\t\tixgbe_reset(adapter);\n\t\te_info(hw, \"eeprom testing starting\\n\");\n\t\tif (ixgbe_eeprom_test(adapter, &data[1]))\n\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\n\t\tixgbe_reset(adapter);\n\t\te_info(hw, \"interrupt testing starting\\n\");\n\t\tif (ixgbe_intr_test(adapter, &data[2]))\n\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\n\t\t/* If SRIOV or VMDq is enabled then skip MAC\n\t\t * loopback diagnostic. */\n\t\tif (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |\n\t\t\t\t IXGBE_FLAG_VMDQ_ENABLED)) {\n\t\t\te_info(hw, \"skip MAC loopback diagnostic in VT mode\\n\");\n\t\t\tdata[3] = 0;\n\t\t\tgoto skip_loopback;\n\t\t}\n\n\t\tixgbe_reset(adapter);\n\t\te_info(hw, \"loopback testing starting\\n\");\n\t\tif (ixgbe_loopback_test(adapter, &data[3]))\n\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\nskip_loopback:\n\t\tixgbe_reset(adapter);\n\n\t\tclear_bit(__IXGBE_TESTING, &adapter->state);\n\t\tif (if_running)\n\t\t\tdev_open(netdev);\n\t} else {\n\t\te_info(hw, \"online testing starting\\n\");\n\t\t/* Online tests */\n\t\tif (ixgbe_link_test(adapter, &data[4]))\n\t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n\n\t\t/* Online tests aren't run; pass by default */\n\t\tdata[0] = 0;\n\t\tdata[1] = 0;\n\t\tdata[2] = 0;\n\t\tdata[3] = 0;\n\n\t\tclear_bit(__IXGBE_TESTING, &adapter->state);\n\t}\nskip_ol_tests:\n\tmsleep_interruptible(4 * 1000);\n}\n\nstatic int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,\n\t\t\t struct ethtool_wolinfo *wol)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tint retval = 1;\n\tu16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;\n\n\t/* WOL not supported except for the following */\n\tswitch (hw->device_id) {\n\tcase IXGBE_DEV_ID_82599_SFP:\n\t\t/* Only these subdevice could supports WOL */\n\t\tswitch (hw->subsystem_device_id) {\n\t\tcase IXGBE_SUBDEV_ID_82599_560FLR:\n\t\t\t/* only support first port */\n\t\t\tif (hw->bus.func != 0) {\n\t\t\t\twol->supported = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\tcase IXGBE_SUBDEV_ID_82599_SFP:\n\t\t\tretval = 0;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\twol->supported = 0;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_COMBO_BACKPLANE:\n\t\t/* All except this subdevice support WOL */\n\t\tif (hw->subsystem_device_id ==\n\t\t IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {\n\t\t\twol->supported = 0;\n\t\t\tbreak;\n\t\t}\n\t\tretval = 0;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_KX4:\n\t\tretval = 0;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X540T:\n\t\t/* check eeprom to see if enabled wol */\n\t\tif ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||\n\t\t ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&\n\t\t (hw->bus.func == 0))) {\n\t\t\tretval = 0;\n\t\t\tbreak;\n\t\t}\n\n\t\t/* All others not supported */\n\t\twol->supported = 0;\n\t\tbreak;\n\tdefault:\n\t\twol->supported = 0;\n\t}\n\treturn retval;\n}\n\nstatic void ixgbe_get_wol(struct net_device *netdev,\n\t\t\t struct ethtool_wolinfo *wol)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\n\twol->supported = WAKE_UCAST | WAKE_MCAST |\n\t\t\t WAKE_BCAST | WAKE_MAGIC;\n\twol->wolopts = 0;\n\n\tif (ixgbe_wol_exclusion(adapter, wol) ||\n\t !device_can_wakeup(&adapter->pdev->dev))\n\t\treturn;\n\n\tif (adapter->wol & IXGBE_WUFC_EX)\n\t\twol->wolopts |= WAKE_UCAST;\n\tif (adapter->wol & IXGBE_WUFC_MC)\n\t\twol->wolopts |= WAKE_MCAST;\n\tif (adapter->wol & IXGBE_WUFC_BC)\n\t\twol->wolopts |= WAKE_BCAST;\n\tif (adapter->wol & IXGBE_WUFC_MAG)\n\t\twol->wolopts |= WAKE_MAGIC;\n}\n\nstatic int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\n\tif (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))\n\t\treturn -EOPNOTSUPP;\n\n\tif (ixgbe_wol_exclusion(adapter, wol))\n\t\treturn wol->wolopts ? -EOPNOTSUPP : 0;\n\n\tadapter->wol = 0;\n\n\tif (wol->wolopts & WAKE_UCAST)\n\t\tadapter->wol |= IXGBE_WUFC_EX;\n\tif (wol->wolopts & WAKE_MCAST)\n\t\tadapter->wol |= IXGBE_WUFC_MC;\n\tif (wol->wolopts & WAKE_BCAST)\n\t\tadapter->wol |= IXGBE_WUFC_BC;\n\tif (wol->wolopts & WAKE_MAGIC)\n\t\tadapter->wol |= IXGBE_WUFC_MAG;\n\n\tdevice_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);\n\n\treturn 0;\n}\n\nstatic int ixgbe_nway_reset(struct net_device *netdev)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\n\tif (netif_running(netdev))\n\t\tixgbe_reinit_locked(adapter);\n\n\treturn 0;\n}\n\n#ifdef HAVE_ETHTOOL_SET_PHYS_ID\nstatic int ixgbe_set_phys_id(struct net_device *netdev,\n\t\t\t enum ethtool_phys_id_state state)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\n\tswitch (state) {\n\tcase ETHTOOL_ID_ACTIVE:\n\t\tadapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\t\treturn 2;\n\n\tcase ETHTOOL_ID_ON:\n\t\thw->mac.ops.led_on(hw, IXGBE_LED_ON);\n\t\tbreak;\n\n\tcase ETHTOOL_ID_OFF:\n\t\thw->mac.ops.led_off(hw, IXGBE_LED_ON);\n\t\tbreak;\n\n\tcase ETHTOOL_ID_INACTIVE:\n\t\t/* Restore LED settings */\n\t\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n#else\nstatic int ixgbe_phys_id(struct net_device *netdev, u32 data)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tu32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\tu32 i;\n\n\tif (!data || data > 300)\n\t\tdata = 300;\n\n\tfor (i = 0; i < (data * 1000); i += 400) {\n\t\tixgbe_led_on(hw, IXGBE_LED_ON);\n\t\tmsleep_interruptible(200);\n\t\tixgbe_led_off(hw, IXGBE_LED_ON);\n\t\tmsleep_interruptible(200);\n\t}\n\n\t/* Restore LED settings */\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);\n\n\treturn 0;\n}\n#endif /* HAVE_ETHTOOL_SET_PHYS_ID */\n\nstatic int ixgbe_get_coalesce(struct net_device *netdev,\n\t\t\t struct ethtool_coalesce *ec)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\n\tec->tx_max_coalesced_frames_irq = adapter->tx_work_limit;\n#ifndef CONFIG_IXGBE_NAPI\n\tec->rx_max_coalesced_frames_irq = adapter->rx_work_limit;\n#endif /* CONFIG_IXGBE_NAPI */\n\t/* only valid if in constant ITR mode */\n\tif (adapter->rx_itr_setting <= 1)\n\t\tec->rx_coalesce_usecs = adapter->rx_itr_setting;\n\telse\n\t\tec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;\n\n\t/* if in mixed tx/rx queues per vector mode, report only rx settings */\n\tif (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)\n\t\treturn 0;\n\n\t/* only valid if in constant ITR mode */\n\tif (adapter->tx_itr_setting <= 1)\n\t\tec->tx_coalesce_usecs = adapter->tx_itr_setting;\n\telse\n\t\tec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;\n\n\treturn 0;\n}\n\n/*\n * this function must be called before setting the new value of\n * rx_itr_setting\n */\n#ifdef NO_VNIC\nstatic bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)\n{\n\tstruct net_device *netdev = adapter->netdev;\n\n\t/* nothing to do if LRO or RSC are not enabled */\n\tif (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||\n\t !(netdev->features & NETIF_F_LRO))\n\t\treturn false;\n\n\t/* check the feature flag value and enable RSC if necessary */\n\tif (adapter->rx_itr_setting == 1 ||\n\t adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {\n\t\tif (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {\n\t\t\tadapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;\n\t\t\te_info(probe, \"rx-usecs value high enough \"\n\t\t\t\t \"to re-enable RSC\\n\");\n\t\t\treturn true;\n\t\t}\n\t/* if interrupt rate is too high then disable RSC */\n\t} else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {\n\t\tadapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;\n#ifdef IXGBE_NO_LRO\n\t\te_info(probe, \"rx-usecs set too low, disabling RSC\\n\");\n#else\n\t\te_info(probe, \"rx-usecs set too low, \"\n\t\t\t \"falling back to software LRO\\n\");\n#endif\n\t\treturn true;\n\t}\n\treturn false;\n}\n#endif\n\nstatic int ixgbe_set_coalesce(struct net_device *netdev,\n\t\t\t struct ethtool_coalesce *ec)\n{\n#ifdef NO_VNIC\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_q_vector *q_vector;\n\tint i;\n\tint num_vectors;\n\tu16 tx_itr_param, rx_itr_param;\n\tbool need_reset = false;\n\n\t/* don't accept tx specific changes if we've got mixed RxTx vectors */\n\tif (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count\n\t && ec->tx_coalesce_usecs)\n\t\treturn -EINVAL;\n\n\tif (ec->tx_max_coalesced_frames_irq)\n\t\tadapter->tx_work_limit = ec->tx_max_coalesced_frames_irq;\n\n#ifndef CONFIG_IXGBE_NAPI\n\tif (ec->rx_max_coalesced_frames_irq)\n\t\tadapter->rx_work_limit = ec->rx_max_coalesced_frames_irq;\n\n#endif\n\tif ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||\n\t (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))\n\t\treturn -EINVAL;\n\n\tif (ec->rx_coalesce_usecs > 1)\n\t\tadapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;\n\telse\n\t\tadapter->rx_itr_setting = ec->rx_coalesce_usecs;\n\n\tif (adapter->rx_itr_setting == 1)\n\t\trx_itr_param = IXGBE_20K_ITR;\n\telse\n\t\trx_itr_param = adapter->rx_itr_setting;\n\n\tif (ec->tx_coalesce_usecs > 1)\n\t\tadapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;\n\telse\n\t\tadapter->tx_itr_setting = ec->tx_coalesce_usecs;\n\n\tif (adapter->tx_itr_setting == 1)\n\t\ttx_itr_param = IXGBE_10K_ITR;\n\telse\n\t\ttx_itr_param = adapter->tx_itr_setting;\n\n\t/* check the old value and enable RSC if necessary */\n\tneed_reset = ixgbe_update_rsc(adapter);\n\n\tif (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)\n\t\tnum_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;\n\telse\n\t\tnum_vectors = 1;\n\n\tfor (i = 0; i < num_vectors; i++) {\n\t\tq_vector = adapter->q_vector[i];\n\t\tq_vector->tx.work_limit = adapter->tx_work_limit;\n\t\tq_vector->rx.work_limit = adapter->rx_work_limit;\n\t\tif (q_vector->tx.count && !q_vector->rx.count)\n\t\t\t/* tx only */\n\t\t\tq_vector->itr = tx_itr_param;\n\t\telse\n\t\t\t/* rx only or mixed */\n\t\t\tq_vector->itr = rx_itr_param;\n\t\tixgbe_write_eitr(q_vector);\n\t}\n\n\t/*\n\t * do reset here at the end to make sure EITR==0 case is handled\n\t * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings\n\t * also locks in RSC enable/disable which requires reset\n\t */\n\tif (need_reset)\n\t\tixgbe_do_reset(netdev);\n#endif\n\treturn 0;\n}\n\n#ifndef HAVE_NDO_SET_FEATURES\nstatic u32 ixgbe_get_rx_csum(struct net_device *netdev)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_ring *ring = adapter->rx_ring[0];\n\treturn test_bit(__IXGBE_RX_CSUM_ENABLED, &ring->state);\n}\n\nstatic int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tint i;\n\n\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\tstruct ixgbe_ring *ring = adapter->rx_ring[i];\n\t\tif (data)\n\t\t\tset_bit(__IXGBE_RX_CSUM_ENABLED, &ring->state);\n\t\telse\n\t\t\tclear_bit(__IXGBE_RX_CSUM_ENABLED, &ring->state);\n\t}\n\n\t/* LRO and RSC both depend on RX checksum to function */\n\tif (!data && (netdev->features & NETIF_F_LRO)) {\n\t\tnetdev->features &= ~NETIF_F_LRO;\n\n\t\tif (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {\n\t\t\tadapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;\n\t\t\tixgbe_do_reset(netdev);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic u32 ixgbe_get_tx_csum(struct net_device *netdev)\n{\n\treturn (netdev->features & NETIF_F_IP_CSUM) != 0;\n}\n\nstatic int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tu32 feature_list;\n\n#ifdef NETIF_F_IPV6_CSUM\n\tfeature_list = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;\n#else\n\tfeature_list = NETIF_F_IP_CSUM;\n#endif\n\tswitch (adapter->hw.mac.type) {\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\t\tfeature_list |= NETIF_F_SCTP_CSUM;\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\tif (data)\n\t\tnetdev->features |= feature_list;\n\telse\n\t\tnetdev->features &= ~feature_list;\n\n\treturn 0;\n}\n\n#ifdef NETIF_F_TSO\nstatic int ixgbe_set_tso(struct net_device *netdev, u32 data)\n{\n\tif (data) {\n\t\tnetdev->features |= NETIF_F_TSO;\n#ifdef NETIF_F_TSO6\n\t\tnetdev->features |= NETIF_F_TSO6;\n#endif\n\t} else {\n#ifndef HAVE_NETDEV_VLAN_FEATURES\n#ifdef NETIF_F_HW_VLAN_TX\n\t\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\t\t/* disable TSO on all VLANs if they're present */\n\t\tif (adapter->vlgrp) {\n\t\t\tint i;\n\t\t\tstruct net_device *v_netdev;\n\t\t\tfor (i = 0; i < VLAN_N_VID; i++) {\n\t\t\t\tv_netdev =\n\t\t\t\t vlan_group_get_device(adapter->vlgrp, i);\n\t\t\t\tif (v_netdev) {\n\t\t\t\t\tv_netdev->features &= ~NETIF_F_TSO;\n#ifdef NETIF_F_TSO6\n\t\t\t\t\tv_netdev->features &= ~NETIF_F_TSO6;\n#endif\n\t\t\t\t\tvlan_group_set_device(adapter->vlgrp, i,\n\t\t\t\t\t\t\t v_netdev);\n\t\t\t\t}\n\t\t\t}\n\t\t}\n#endif\n#endif /* HAVE_NETDEV_VLAN_FEATURES */\n\t\tnetdev->features &= ~NETIF_F_TSO;\n#ifdef NETIF_F_TSO6\n\t\tnetdev->features &= ~NETIF_F_TSO6;\n#endif\n\t}\n\treturn 0;\n}\n\n#endif /* NETIF_F_TSO */\n#ifdef ETHTOOL_GFLAGS\nstatic int ixgbe_set_flags(struct net_device *netdev, u32 data)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tu32 supported_flags = ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN;\n\tu32 changed = netdev->features ^ data;\n\tbool need_reset = false;\n\tint rc;\n\n#ifndef HAVE_VLAN_RX_REGISTER\n\tif ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&\n\t !(data & ETH_FLAG_RXVLAN))\n\t\treturn -EINVAL;\n\n#endif\n#ifdef NETIF_F_RXHASH\n\tif (adapter->flags & IXGBE_FLAG_RSS_ENABLED)\n\t\tsupported_flags |= ETH_FLAG_RXHASH;\n#endif\n#ifdef IXGBE_NO_LRO\n\tif (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)\n#endif\n\t\tsupported_flags |= ETH_FLAG_LRO;\n\n#ifdef ETHTOOL_GRXRINGS\n\tswitch (adapter->hw.mac.type) {\n\tcase ixgbe_mac_X540:\n\tcase ixgbe_mac_82599EB:\n\t\tsupported_flags |= ETH_FLAG_NTUPLE;\n\tdefault:\n\t\tbreak;\n\t}\n\n#endif\n\trc = ethtool_op_set_flags(netdev, data, supported_flags);\n\tif (rc)\n\t\treturn rc;\n\n#ifndef HAVE_VLAN_RX_REGISTER\n\tif (changed & ETH_FLAG_RXVLAN)\n\t\tixgbe_vlan_mode(netdev, netdev->features);\n\n#endif\n\t/* if state changes we need to update adapter->flags and reset */\n\tif (!(netdev->features & NETIF_F_LRO)) {\n\t\tif (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)\n\t\t\tneed_reset = true;\n\t\tadapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;\n\t} else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&\n\t\t !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {\n\t\tif (adapter->rx_itr_setting == 1 ||\n\t\t adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {\n\t\t\tadapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;\n\t\t\tneed_reset = true;\n\t\t} else if (changed & ETH_FLAG_LRO) {\n#ifdef IXGBE_NO_LRO\n\t\t\te_info(probe, \"rx-usecs set too low, \"\n\t\t\t \"disabling RSC\\n\");\n#else\n\t\t\te_info(probe, \"rx-usecs set too low, \"\n\t\t\t \"falling back to software LRO\\n\");\n#endif\n\t\t}\n\t}\n\n#ifdef ETHTOOL_GRXRINGS\n\t/*\n\t * Check if Flow Director n-tuple support was enabled or disabled. If\n\t * the state changed, we need to reset.\n\t */\n\tif (!(netdev->features & NETIF_F_NTUPLE)) {\n\t\tif (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {\n\t\t\t/* turn off Flow Director, set ATR and reset */\n\t\t\tif ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&\n\t\t\t !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))\n\t\t\t\tadapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;\n\t\t\tneed_reset = true;\n\t\t}\n\t\tadapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;\n\t} else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {\n\t\t/* turn off ATR, enable perfect filters and reset */\n\t\tadapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;\n\t\tadapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;\n\t\tneed_reset = true;\n\t}\n\n#endif /* ETHTOOL_GRXRINGS */\n\tif (need_reset)\n\t\tixgbe_do_reset(netdev);\n\n\treturn 0;\n}\n\n#endif /* ETHTOOL_GFLAGS */\n#endif /* HAVE_NDO_SET_FEATURES */\n#ifdef ETHTOOL_GRXRINGS\nstatic int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,\n\t\t\t\t\tstruct ethtool_rxnfc *cmd)\n{\n\tunion ixgbe_atr_input *mask = &adapter->fdir_mask;\n\tstruct ethtool_rx_flow_spec *fsp =\n\t\t(struct ethtool_rx_flow_spec *)&cmd->fs;\n\tstruct hlist_node *node, *node2;\n\tstruct ixgbe_fdir_filter *rule = NULL;\n\n\t/* report total rule count */\n\tcmd->data = (1024 << adapter->fdir_pballoc) - 2;\n\n\thlist_for_each_entry_safe(rule, node, node2,\n\t\t\t\t &adapter->fdir_filter_list, fdir_node) {\n\t\tif (fsp->location <= rule->sw_idx)\n\t\t\tbreak;\n\t}\n\n\tif (!rule || fsp->location != rule->sw_idx)\n\t\treturn -EINVAL;\n\n\t/* fill out the flow spec entry */\n\n\t/* set flow type field */\n\tswitch (rule->filter.formatted.flow_type) {\n\tcase IXGBE_ATR_FLOW_TYPE_TCPV4:\n\t\tfsp->flow_type = TCP_V4_FLOW;\n\t\tbreak;\n\tcase IXGBE_ATR_FLOW_TYPE_UDPV4:\n\t\tfsp->flow_type = UDP_V4_FLOW;\n\t\tbreak;\n\tcase IXGBE_ATR_FLOW_TYPE_SCTPV4:\n\t\tfsp->flow_type = SCTP_V4_FLOW;\n\t\tbreak;\n\tcase IXGBE_ATR_FLOW_TYPE_IPV4:\n\t\tfsp->flow_type = IP_USER_FLOW;\n\t\tfsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;\n\t\tfsp->h_u.usr_ip4_spec.proto = 0;\n\t\tfsp->m_u.usr_ip4_spec.proto = 0;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tfsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;\n\tfsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;\n\tfsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;\n\tfsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;\n\tfsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];\n\tfsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];\n\tfsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];\n\tfsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];\n\tfsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;\n\tfsp->m_ext.vlan_tci = mask->formatted.vlan_id;\n\tfsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;\n\tfsp->m_ext.vlan_etype = mask->formatted.flex_bytes;\n\tfsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);\n\tfsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);\n\tfsp->flow_type |= FLOW_EXT;\n\n\t/* record action */\n\tif (rule->action == IXGBE_FDIR_DROP_QUEUE)\n\t\tfsp->ring_cookie = RX_CLS_FLOW_DISC;\n\telse\n\t\tfsp->ring_cookie = rule->action;\n\n\treturn 0;\n}\n\nstatic int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,\n\t\t\t\t struct ethtool_rxnfc *cmd,\n\t\t\t\t u32 *rule_locs)\n{\n\tstruct hlist_node *node, *node2;\n\tstruct ixgbe_fdir_filter *rule;\n\tint cnt = 0;\n\n\t/* report total rule count */\n\tcmd->data = (1024 << adapter->fdir_pballoc) - 2;\n\n\thlist_for_each_entry_safe(rule, node, node2,\n\t\t\t\t &adapter->fdir_filter_list, fdir_node) {\n\t\tif (cnt == cmd->rule_cnt)\n\t\t\treturn -EMSGSIZE;\n\t\trule_locs[cnt] = rule->sw_idx;\n\t\tcnt++;\n\t}\n\n\tcmd->rule_cnt = cnt;\n\n\treturn 0;\n}\n\nstatic int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,\n\t\t\t\t struct ethtool_rxnfc *cmd)\n{\n\tcmd->data = 0;\n\n\t/* if RSS is disabled then report no hashing */\n\tif (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))\n\t\treturn 0;\n\n\t/* Report default options for RSS on ixgbe */\n\tswitch (cmd->flow_type) {\n\tcase TCP_V4_FLOW:\n\t\tcmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;\n\tcase UDP_V4_FLOW:\n\t\tif (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)\n\t\t\tcmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;\n\tcase SCTP_V4_FLOW:\n\tcase AH_ESP_V4_FLOW:\n\tcase AH_V4_FLOW:\n\tcase ESP_V4_FLOW:\n\tcase IPV4_FLOW:\n\t\tcmd->data |= RXH_IP_SRC | RXH_IP_DST;\n\t\tbreak;\n\tcase TCP_V6_FLOW:\n\t\tcmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;\n\tcase UDP_V6_FLOW:\n\t\tif (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)\n\t\t\tcmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;\n\tcase SCTP_V6_FLOW:\n\tcase AH_ESP_V6_FLOW:\n\tcase AH_V6_FLOW:\n\tcase ESP_V6_FLOW:\n\tcase IPV6_FLOW:\n\t\tcmd->data |= RXH_IP_SRC | RXH_IP_DST;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,\n#ifdef HAVE_ETHTOOL_GET_RXNFC_VOID_RULE_LOCS\n\t\t\t void *rule_locs)\n#else\n\t\t\t u32 *rule_locs)\n#endif\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(dev);\n\tint ret = -EOPNOTSUPP;\n\n\tswitch (cmd->cmd) {\n\tcase ETHTOOL_GRXRINGS:\n\t\tcmd->data = adapter->num_rx_queues;\n\t\tret = 0;\n\t\tbreak;\n\tcase ETHTOOL_GRXCLSRLCNT:\n\t\tcmd->rule_cnt = adapter->fdir_filter_count;\n\t\tret = 0;\n\t\tbreak;\n\tcase ETHTOOL_GRXCLSRULE:\n\t\tret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);\n\t\tbreak;\n\tcase ETHTOOL_GRXCLSRLALL:\n\t\tret = ixgbe_get_ethtool_fdir_all(adapter, cmd,\n\t\t\t\t\t\t (u32 *)rule_locs);\n\t\tbreak;\n\tcase ETHTOOL_GRXFH:\n\t\tret = ixgbe_get_rss_hash_opts(adapter, cmd);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,\n\t\t\t\t\t struct ixgbe_fdir_filter *input,\n\t\t\t\t\t u16 sw_idx)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct hlist_node *node, *node2, *parent;\n\tstruct ixgbe_fdir_filter *rule;\n\tint err = -EINVAL;\n\n\tparent = NULL;\n\trule = NULL;\n\n\thlist_for_each_entry_safe(rule, node, node2,\n\t\t\t\t &adapter->fdir_filter_list, fdir_node) {\n\t\t/* hash found, or no matching entry */\n\t\tif (rule->sw_idx >= sw_idx)\n\t\t\tbreak;\n\t\tparent = node;\n\t}\n\n\t/* if there is an old rule occupying our place remove it */\n\tif (rule && (rule->sw_idx == sw_idx)) {\n\t\tif (!input || (rule->filter.formatted.bkt_hash !=\n\t\t\t input->filter.formatted.bkt_hash)) {\n\t\t\terr = ixgbe_fdir_erase_perfect_filter_82599(hw,\n\t\t\t\t\t\t\t\t&rule->filter,\n\t\t\t\t\t\t\t\tsw_idx);\n\t\t}\n\n\t\thlist_del(&rule->fdir_node);\n\t\tkfree(rule);\n\t\tadapter->fdir_filter_count--;\n\t}\n\n\t/*\n\t * If no input this was a delete, err should be 0 if a rule was\n\t * successfully found and removed from the list else -EINVAL\n\t */\n\tif (!input)\n\t\treturn err;\n\n\t/* initialize node and set software index */\n\tINIT_HLIST_NODE(&input->fdir_node);\n\n\t/* add filter to the list */\n\tif (parent)\n\t\thlist_add_after(parent, &input->fdir_node);\n\telse\n\t\thlist_add_head(&input->fdir_node,\n\t\t\t &adapter->fdir_filter_list);\n\n\t/* update counts */\n\tadapter->fdir_filter_count++;\n\n\treturn 0;\n}\n\nstatic int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,\n\t\t\t\t u8 *flow_type)\n{\n\tswitch (fsp->flow_type & ~FLOW_EXT) {\n\tcase TCP_V4_FLOW:\n\t\t*flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;\n\t\tbreak;\n\tcase UDP_V4_FLOW:\n\t\t*flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;\n\t\tbreak;\n\tcase SCTP_V4_FLOW:\n\t\t*flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;\n\t\tbreak;\n\tcase IP_USER_FLOW:\n\t\tswitch (fsp->h_u.usr_ip4_spec.proto) {\n\t\tcase IPPROTO_TCP:\n\t\t\t*flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;\n\t\t\tbreak;\n\t\tcase IPPROTO_UDP:\n\t\t\t*flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;\n\t\t\tbreak;\n\t\tcase IPPROTO_SCTP:\n\t\t\t*flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;\n\t\t\tbreak;\n\t\tcase 0:\n\t\t\tif (!fsp->m_u.usr_ip4_spec.proto) {\n\t\t\t\t*flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;\n\t\t\t\tbreak;\n\t\t\t}\n\t\tdefault:\n\t\t\treturn 0;\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\treturn 0;\n\t}\n\n\treturn 1;\n}\n\nstatic int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,\n\t\t\t\t\tstruct ethtool_rxnfc *cmd)\n{\n\tstruct ethtool_rx_flow_spec *fsp =\n\t\t(struct ethtool_rx_flow_spec *)&cmd->fs;\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct ixgbe_fdir_filter *input;\n\tunion ixgbe_atr_input mask;\n\tint err;\n\n\tif (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))\n\t\treturn -EOPNOTSUPP;\n\n\t/*\n\t * Don't allow programming if the action is a queue greater than\n\t * the number of online Rx queues.\n\t */\n\tif ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&\n\t (fsp->ring_cookie >= adapter->num_rx_queues))\n\t\treturn -EINVAL;\n\n\t/* Don't allow indexes to exist outside of available space */\n\tif (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {\n\t\te_err(drv, \"Location out of range\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tinput = kzalloc(sizeof(*input), GFP_ATOMIC);\n\tif (!input)\n\t\treturn -ENOMEM;\n\n\tmemset(&mask, 0, sizeof(union ixgbe_atr_input));\n\n\t/* set SW index */\n\tinput->sw_idx = fsp->location;\n\n\t/* record flow type */\n\tif (!ixgbe_flowspec_to_flow_type(fsp,\n\t\t\t\t\t &input->filter.formatted.flow_type)) {\n\t\te_err(drv, \"Unrecognized flow type\\n\");\n\t\tgoto err_out;\n\t}\n\n\tmask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |\n\t\t\t\t IXGBE_ATR_L4TYPE_MASK;\n\n\tif (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)\n\t\tmask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;\n\n\t/* Copy input into formatted structures */\n\tinput->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;\n\tmask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;\n\tinput->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;\n\tmask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;\n\tinput->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;\n\tmask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;\n\tinput->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;\n\tmask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;\n\n\tif (fsp->flow_type & FLOW_EXT) {\n\t\tinput->filter.formatted.vm_pool =\n\t\t\t\t(unsigned char)ntohl(fsp->h_ext.data[1]);\n\t\tmask.formatted.vm_pool =\n\t\t\t\t(unsigned char)ntohl(fsp->m_ext.data[1]);\n\t\tinput->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;\n\t\tmask.formatted.vlan_id = fsp->m_ext.vlan_tci;\n\t\tinput->filter.formatted.flex_bytes =\n\t\t\t\t\t\tfsp->h_ext.vlan_etype;\n\t\tmask.formatted.flex_bytes = fsp->m_ext.vlan_etype;\n\t}\n\n\t/* determine if we need to drop or route the packet */\n\tif (fsp->ring_cookie == RX_CLS_FLOW_DISC)\n\t\tinput->action = IXGBE_FDIR_DROP_QUEUE;\n\telse\n\t\tinput->action = fsp->ring_cookie;\n\n\tspin_lock(&adapter->fdir_perfect_lock);\n\n\tif (hlist_empty(&adapter->fdir_filter_list)) {\n\t\t/* save mask and program input mask into HW */\n\t\tmemcpy(&adapter->fdir_mask, &mask, sizeof(mask));\n\t\terr = ixgbe_fdir_set_input_mask_82599(hw, &mask);\n\t\tif (err) {\n\t\t\te_err(drv, \"Error writing mask\\n\");\n\t\t\tgoto err_out_w_lock;\n\t\t}\n\t} else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {\n\t\te_err(drv, \"Only one mask supported per port\\n\");\n\t\tgoto err_out_w_lock;\n\t}\n\n\t/* apply mask and compute/store hash */\n\tixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);\n\n\t/* program filters to filter memory */\n\terr = ixgbe_fdir_write_perfect_filter_82599(hw,\n\t\t\t\t&input->filter, input->sw_idx,\n\t\t\t\t(input->action == IXGBE_FDIR_DROP_QUEUE) ?\n\t\t\t\tIXGBE_FDIR_DROP_QUEUE :\n\t\t\t\tadapter->rx_ring[input->action]->reg_idx);\n\tif (err)\n\t\tgoto err_out_w_lock;\n\n\tixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);\n\n\tspin_unlock(&adapter->fdir_perfect_lock);\n\n\tkfree(input);\n\treturn err;\nerr_out_w_lock:\n\tspin_unlock(&adapter->fdir_perfect_lock);\nerr_out:\n\tkfree(input);\n\treturn -EINVAL;\n}\n\nstatic int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,\n\t\t\t\t\tstruct ethtool_rxnfc *cmd)\n{\n\tstruct ethtool_rx_flow_spec *fsp =\n\t\t(struct ethtool_rx_flow_spec *)&cmd->fs;\n\tint err;\n\n\tspin_lock(&adapter->fdir_perfect_lock);\n\terr = ixgbe_update_ethtool_fdir_entry(adapter, NULL, (u16)(fsp->location));\n\tspin_unlock(&adapter->fdir_perfect_lock);\n\n\treturn err;\n}\n\n#ifdef ETHTOOL_SRXNTUPLE\n/*\n * We need to keep this around for kernels 2.6.33 - 2.6.39 in order to avoid\n * a null pointer dereference as it was assumend if the NETIF_F_NTUPLE flag\n * was defined that this function was present.\n */\nstatic int ixgbe_set_rx_ntuple(struct net_device *dev,\n\t\t\t struct ethtool_rx_ntuple *cmd)\n{\n\treturn -EOPNOTSUPP;\n}\n\n#endif\n#define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \\\n\t\t IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)\nstatic int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,\n\t\t\t\t struct ethtool_rxnfc *nfc)\n{\n\tu32 flags2 = adapter->flags2;\n\n\t/*\n\t * RSS does not support anything other than hashing\n\t * to queues on src and dst IPs and ports\n\t */\n\tif (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |\n\t\t\t RXH_L4_B_0_1 | RXH_L4_B_2_3))\n\t\treturn -EINVAL;\n\n\tswitch (nfc->flow_type) {\n\tcase TCP_V4_FLOW:\n\tcase TCP_V6_FLOW:\n\t\tif (!(nfc->data & RXH_IP_SRC) ||\n\t\t !(nfc->data & RXH_IP_DST) ||\n\t\t !(nfc->data & RXH_L4_B_0_1) ||\n\t\t !(nfc->data & RXH_L4_B_2_3))\n\t\t\treturn -EINVAL;\n\t\tbreak;\n\tcase UDP_V4_FLOW:\n\t\tif (!(nfc->data & RXH_IP_SRC) ||\n\t\t !(nfc->data & RXH_IP_DST))\n\t\t\treturn -EINVAL;\n\t\tswitch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {\n\t\tcase 0:\n\t\t\tflags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;\n\t\t\tbreak;\n\t\tcase (RXH_L4_B_0_1 | RXH_L4_B_2_3):\n\t\t\tflags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tbreak;\n\tcase UDP_V6_FLOW:\n\t\tif (!(nfc->data & RXH_IP_SRC) ||\n\t\t !(nfc->data & RXH_IP_DST))\n\t\t\treturn -EINVAL;\n\t\tswitch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {\n\t\tcase 0:\n\t\t\tflags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;\n\t\t\tbreak;\n\t\tcase (RXH_L4_B_0_1 | RXH_L4_B_2_3):\n\t\t\tflags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;\n\t\t\tbreak;\n\t\tdefault:\n\t\t\treturn -EINVAL;\n\t\t}\n\t\tbreak;\n\tcase AH_ESP_V4_FLOW:\n\tcase AH_V4_FLOW:\n\tcase ESP_V4_FLOW:\n\tcase SCTP_V4_FLOW:\n\tcase AH_ESP_V6_FLOW:\n\tcase AH_V6_FLOW:\n\tcase ESP_V6_FLOW:\n\tcase SCTP_V6_FLOW:\n\t\tif (!(nfc->data & RXH_IP_SRC) ||\n\t\t !(nfc->data & RXH_IP_DST) ||\n\t\t (nfc->data & RXH_L4_B_0_1) ||\n\t\t (nfc->data & RXH_L4_B_2_3))\n\t\t\treturn -EINVAL;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\t/* if we changed something we need to update flags */\n\tif (flags2 != adapter->flags2) {\n\t\tstruct ixgbe_hw *hw = &adapter->hw;\n\t\tu32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);\n\n\t\tif ((flags2 & UDP_RSS_FLAGS) &&\n\t\t !(adapter->flags2 & UDP_RSS_FLAGS))\n\t\t\te_warn(drv, \"enabling UDP RSS: fragmented packets\"\n\t\t\t \" may arrive out of order to the stack above\\n\");\n\n\t\tadapter->flags2 = flags2;\n\n\t\t/* Perform hash on these packet types */\n\t\tmrqc |= IXGBE_MRQC_RSS_FIELD_IPV4\n\t\t | IXGBE_MRQC_RSS_FIELD_IPV4_TCP\n\t\t | IXGBE_MRQC_RSS_FIELD_IPV6\n\t\t | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;\n\n\t\tmrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |\n\t\t\t IXGBE_MRQC_RSS_FIELD_IPV6_UDP);\n\n\t\tif (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)\n\t\t\tmrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;\n\n\t\tif (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)\n\t\t\tmrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);\n\t}\n\n\treturn 0;\n}\n\nstatic int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(dev);\n\tint ret = -EOPNOTSUPP;\n\n\tswitch (cmd->cmd) {\n\tcase ETHTOOL_SRXCLSRLINS:\n\t\tret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);\n\t\tbreak;\n\tcase ETHTOOL_SRXCLSRLDEL:\n\t\tret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);\n\t\tbreak;\n\tcase ETHTOOL_SRXFH:\n\t\tret = ixgbe_set_rss_hash_opt(adapter, cmd);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\n#endif /* ETHTOOL_GRXRINGS */\n//static\nstruct ethtool_ops ixgbe_ethtool_ops = {\n\t.get_settings\t\t= ixgbe_get_settings,\n\t.set_settings\t\t= ixgbe_set_settings,\n\t.get_drvinfo\t\t= ixgbe_get_drvinfo,\n\t.get_regs_len\t\t= ixgbe_get_regs_len,\n\t.get_regs\t\t= ixgbe_get_regs,\n\t.get_wol\t\t= ixgbe_get_wol,\n\t.set_wol\t\t= ixgbe_set_wol,\n\t.nway_reset\t\t= ixgbe_nway_reset,\n\t.get_link\t\t= ethtool_op_get_link,\n\t.get_eeprom_len\t\t= ixgbe_get_eeprom_len,\n\t.get_eeprom\t\t= ixgbe_get_eeprom,\n\t.set_eeprom\t\t= ixgbe_set_eeprom,\n\t.get_ringparam\t\t= ixgbe_get_ringparam,\n\t.set_ringparam\t\t= ixgbe_set_ringparam,\n\t.get_pauseparam\t\t= ixgbe_get_pauseparam,\n\t.set_pauseparam\t\t= ixgbe_set_pauseparam,\n\t.get_msglevel\t\t= ixgbe_get_msglevel,\n\t.set_msglevel\t\t= ixgbe_set_msglevel,\n#ifndef HAVE_ETHTOOL_GET_SSET_COUNT\n\t.self_test_count\t= ixgbe_diag_test_count,\n#endif /* HAVE_ETHTOOL_GET_SSET_COUNT */\n\t.self_test\t\t= ixgbe_diag_test,\n\t.get_strings\t\t= ixgbe_get_strings,\n#ifdef HAVE_ETHTOOL_SET_PHYS_ID\n\t.set_phys_id\t\t= ixgbe_set_phys_id,\n#else\n\t.phys_id\t\t= ixgbe_phys_id,\n#endif /* HAVE_ETHTOOL_SET_PHYS_ID */\n#ifndef HAVE_ETHTOOL_GET_SSET_COUNT\n\t.get_stats_count\t= ixgbe_get_stats_count,\n#else /* HAVE_ETHTOOL_GET_SSET_COUNT */\n\t.get_sset_count\t\t= ixgbe_get_sset_count,\n#endif /* HAVE_ETHTOOL_GET_SSET_COUNT */\n\t.get_ethtool_stats = ixgbe_get_ethtool_stats,\n#ifdef HAVE_ETHTOOL_GET_PERM_ADDR\n\t.get_perm_addr\t\t= ethtool_op_get_perm_addr,\n#endif\n\t.get_coalesce\t\t= ixgbe_get_coalesce,\n\t.set_coalesce\t\t= ixgbe_set_coalesce,\n#ifndef HAVE_NDO_SET_FEATURES\n\t.get_rx_csum\t\t= ixgbe_get_rx_csum,\n\t.set_rx_csum\t\t= ixgbe_set_rx_csum,\n\t.get_tx_csum\t\t= ixgbe_get_tx_csum,\n\t.set_tx_csum\t\t= ixgbe_set_tx_csum,\n\t.get_sg\t\t\t= ethtool_op_get_sg,\n\t.set_sg\t\t\t= ethtool_op_set_sg,\n#ifdef NETIF_F_TSO\n\t.get_tso\t\t= ethtool_op_get_tso,\n\t.set_tso\t\t= ixgbe_set_tso,\n#endif\n#ifdef ETHTOOL_GFLAGS\n\t.get_flags\t\t= ethtool_op_get_flags,\n\t.set_flags\t\t= ixgbe_set_flags,\n#endif\n#endif /* HAVE_NDO_SET_FEATURES */\n#ifdef ETHTOOL_GRXRINGS\n\t.get_rxnfc\t\t= ixgbe_get_rxnfc,\n\t.set_rxnfc\t\t= ixgbe_set_rxnfc,\n#ifdef ETHTOOL_SRXNTUPLE\n\t.set_rx_ntuple\t\t= ixgbe_set_rx_ntuple,\n#endif\n#endif\n};\n\nvoid ixgbe_set_ethtool_ops(struct net_device *netdev)\n{\n\tSET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);\n}\n#endif /* SIOCETHTOOL */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_fcoe.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _IXGBE_FCOE_H\n#define _IXGBE_FCOE_H\n\n#ifdef IXGBE_FCOE\n\n#include \n#include \n\n/* shift bits within STAT fo FCSTAT */\n#define IXGBE_RXDADV_FCSTAT_SHIFT\t4\n\n/* ddp user buffer */\n#define IXGBE_BUFFCNT_MAX\t256\t/* 8 bits bufcnt */\n#define IXGBE_FCPTR_ALIGN\t16\n#define IXGBE_FCPTR_MAX\t\t(IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t))\n#define IXGBE_FCBUFF_4KB\t0x0\n#define IXGBE_FCBUFF_8KB\t0x1\n#define IXGBE_FCBUFF_16KB\t0x2\n#define IXGBE_FCBUFF_64KB\t0x3\n#define IXGBE_FCBUFF_MAX\t65536\t/* 64KB max */\n#define IXGBE_FCBUFF_MIN\t4096\t/* 4KB min */\n#define IXGBE_FCOE_DDP_MAX\t512\t/* 9 bits xid */\n\n/* Default traffic class to use for FCoE */\n#define IXGBE_FCOE_DEFTC\t3\n\n/* fcerr */\n#define IXGBE_FCERR_BADCRC\t0x00100000\n#define IXGBE_FCERR_EOFSOF\t0x00200000\n#define IXGBE_FCERR_NOFIRST\t0x00300000\n#define IXGBE_FCERR_OOOSEQ\t0x00400000\n#define IXGBE_FCERR_NODMA\t0x00500000\n#define IXGBE_FCERR_PKTLOST\t0x00600000\n\n/* FCoE DDP for target mode */\n#define __IXGBE_FCOE_TARGET\t1\n\nstruct ixgbe_fcoe_ddp {\n\tint len;\n\tu32 err;\n\tunsigned int sgc;\n\tstruct scatterlist *sgl;\n\tdma_addr_t udp;\n\tu64 *udl;\n\tstruct pci_pool *pool;\n};\n\nstruct ixgbe_fcoe {\n\tstruct pci_pool **pool;\n\tatomic_t refcnt;\n\tspinlock_t lock;\n\tstruct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX];\n\tunsigned char *extra_ddp_buffer;\n\tdma_addr_t extra_ddp_buffer_dma;\n\tu64 __percpu *pcpu_noddp;\n\tu64 __percpu *pcpu_noddp_ext_buff;\n\tunsigned long mode;\n\tu8 tc;\n\tu8 up;\n\tu8 up_set;\n};\n#endif /* IXGBE_FCOE */\n\n#endif /* _IXGBE_FCOE_H */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_main.c", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n/******************************************************************************\n Copyright (c)2006 - 2007 Myricom, Inc. for some LRO specific code\n******************************************************************************/\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#ifdef HAVE_SCTP\n#include \n#endif\n#include \n#include \n#ifdef NETIF_F_TSO\n#include \n#ifdef NETIF_F_TSO6\n#include \n#endif\n#endif\n#ifdef SIOCETHTOOL\n#include \n#endif\n\n#include \"ixgbe.h\"\n\n#undef CONFIG_DCA\n#undef CONFIG_DCA_MODULE\n\nchar ixgbe_driver_name[] = \"ixgbe\";\nstatic const char ixgbe_driver_string[] =\n\t\t\t \"Intel(R) 10 Gigabit PCI Express Network Driver\";\n#define DRV_HW_PERF\n\n#ifndef CONFIG_IXGBE_NAPI\n#define DRIVERNAPI\n#else\n#define DRIVERNAPI \"-NAPI\"\n#endif\n\n#define FPGA\n\n#define VMDQ_TAG\n\n#define MAJ 3\n#define MIN 9\n#define BUILD 17\n#define DRV_VERSION\t__stringify(MAJ) \".\" __stringify(MIN) \".\" \\\n\t\t\t__stringify(BUILD) DRIVERNAPI DRV_HW_PERF FPGA VMDQ_TAG\nconst char ixgbe_driver_version[] = DRV_VERSION;\nstatic const char ixgbe_copyright[] =\n\t\t\t\t\"Copyright (c) 1999-2012 Intel Corporation.\";\n\n/* ixgbe_pci_tbl - PCI Device ID Table\n *\n * Wildcard entries (PCI_ANY_ID) should come last\n * Last entry must be all 0s\n *\n * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,\n * Class, Class Mask, private data (not used) }\n */\nDEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP)},\n\t{PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP)},\n\t/* required last entry */\n\t{0, }\n};\n\n#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)\nstatic int ixgbe_notify_dca(struct notifier_block *, unsigned long event,\n\t\t\t void *p);\nstatic struct notifier_block dca_notifier = {\n\t.notifier_call\t= ixgbe_notify_dca,\n\t.next\t\t= NULL,\n\t.priority\t= 0\n};\n\n#endif\nMODULE_AUTHOR(\"Intel Corporation, \");\nMODULE_DESCRIPTION(\"Intel(R) 10 Gigabit PCI Express Network Driver\");\nMODULE_LICENSE(\"GPL\");\nMODULE_VERSION(DRV_VERSION);\n\n#define DEFAULT_DEBUG_LEVEL_SHIFT 3\n\n\nstatic void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)\n{\n\tu32 ctrl_ext;\n\n\t/* Let firmware take over control of h/w */\n\tctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);\n\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,\n\t\t\tctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);\n}\n\n#ifdef NO_VNIC\nstatic void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)\n{\n\tu32 ctrl_ext;\n\n\t/* Let firmware know the driver has taken over */\n\tctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);\n\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,\n\t\t\tctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);\n}\n#endif\n\n\nstatic void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct ixgbe_hw_stats *hwstats = &adapter->stats;\n\tint i;\n\tu32 data;\n\n\tif ((hw->fc.current_mode != ixgbe_fc_full) &&\n\t (hw->fc.current_mode != ixgbe_fc_rx_pause))\n\t\treturn;\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tdata = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);\n\t\tbreak;\n\tdefault:\n\t\tdata = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);\n\t}\n\thwstats->lxoffrxc += data;\n\n\t/* refill credits (no tx hang) if we received xoff */\n\tif (!data)\n\t\treturn;\n\n\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\tclear_bit(__IXGBE_HANG_CHECK_ARMED,\n\t\t\t &adapter->tx_ring[i]->state);\n}\n\nstatic void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct ixgbe_hw_stats *hwstats = &adapter->stats;\n\tu32 xoff[8] = {0};\n\tint i;\n\tbool pfc_en = adapter->dcb_cfg.pfc_mode_enable;\n\n#ifdef HAVE_DCBNL_IEEE\n\tif (adapter->ixgbe_ieee_pfc)\n\t\tpfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);\n\n#endif\n\tif (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {\n\t\tixgbe_update_xoff_rx_lfc(adapter);\n\t\treturn;\n\t}\n\n\t/* update stats for each tc, only valid with PFC enabled */\n\tfor (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {\n\t\tswitch (hw->mac.type) {\n\t\tcase ixgbe_mac_82598EB:\n\t\t\txoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));\n\t\t\tbreak;\n\t\tdefault:\n\t\t\txoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));\n\t\t}\n\t\thwstats->pxoffrxc[i] += xoff[i];\n\t}\n\n\t/* disarm tx queues that have received xoff frames */\n\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\tstruct ixgbe_ring *tx_ring = adapter->tx_ring[i];\n\t\tu8 tc = tx_ring->dcb_tc;\n\n\t\tif ((tc <= 7) && (xoff[tc]))\n\t\t\tclear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);\n\t}\n}\n\n\n\n\n#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2\n\n\n\n\n#ifdef HAVE_8021P_SUPPORT\n/**\n * ixgbe_vlan_stripping_disable - helper to disable vlan tag stripping\n * @adapter: driver data\n */\nvoid ixgbe_vlan_stripping_disable(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tu32 vlnctrl;\n\tint i;\n\n\t/* leave vlan tag stripping enabled for DCB */\n\tif (adapter->flags & IXGBE_FLAG_DCB_ENABLED)\n\t\treturn;\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tvlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n\t\tvlnctrl &= ~IXGBE_VLNCTRL_VME;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\t\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\t\tu8 reg_idx = adapter->rx_ring[i]->reg_idx;\n\t\t\tvlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));\n\t\t\tvlnctrl &= ~IXGBE_RXDCTL_VME;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), vlnctrl);\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n#endif\n/**\n * ixgbe_vlan_stripping_enable - helper to enable vlan tag stripping\n * @adapter: driver data\n */\nvoid ixgbe_vlan_stripping_enable(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tu32 vlnctrl;\n\tint i;\n\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tvlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n\t\tvlnctrl |= IXGBE_VLNCTRL_VME;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);\n\t\tbreak;\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\t\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\t\tu8 reg_idx = adapter->rx_ring[i]->reg_idx;\n\t\t\tvlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));\n\t\t\tvlnctrl |= IXGBE_RXDCTL_VME;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), vlnctrl);\n\t\t}\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n#ifdef HAVE_VLAN_RX_REGISTER\nvoid ixgbe_vlan_mode(struct net_device *netdev, struct vlan_group *grp)\n#else\nvoid ixgbe_vlan_mode(struct net_device *netdev, u32 features)\n#endif\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n#ifdef HAVE_8021P_SUPPORT\n\tbool enable;\n#endif\n#ifdef HAVE_VLAN_RX_REGISTER\n\n\t//if (!test_bit(__IXGBE_DOWN, &adapter->state))\n\t//\tixgbe_irq_disable(adapter);\n\n\tadapter->vlgrp = grp;\n\n\t//if (!test_bit(__IXGBE_DOWN, &adapter->state))\n\t//\tixgbe_irq_enable(adapter, true, true);\n#endif\n#ifdef HAVE_8021P_SUPPORT\n#ifdef HAVE_VLAN_RX_REGISTER\n\tenable = (grp || (adapter->flags & IXGBE_FLAG_DCB_ENABLED));\n#else\n\tenable = !!(features & NETIF_F_HW_VLAN_RX);\n#endif\n\tif (enable)\n\t\t/* enable VLAN tag insert/strip */\n\t\tixgbe_vlan_stripping_enable(adapter);\n\telse\n\t\t/* disable VLAN tag insert/strip */\n\t\tixgbe_vlan_stripping_disable(adapter);\n\n#endif\n}\n\nstatic u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)\n{\n#ifdef NETDEV_HW_ADDR_T_MULTICAST\n\tstruct netdev_hw_addr *mc_ptr;\n#else\n\tstruct dev_mc_list *mc_ptr;\n#endif\n\tstruct ixgbe_adapter *adapter = hw->back;\n\tu8 *addr = *mc_addr_ptr;\n\n\t*vmdq = adapter->num_vfs;\n\n#ifdef NETDEV_HW_ADDR_T_MULTICAST\n\tmc_ptr = container_of(addr, struct netdev_hw_addr, addr[0]);\n\tif (mc_ptr->list.next) {\n\t\tstruct netdev_hw_addr *ha;\n\n\t\tha = list_entry(mc_ptr->list.next, struct netdev_hw_addr, list);\n\t\t*mc_addr_ptr = ha->addr;\n\t}\n#else\n\tmc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);\n\tif (mc_ptr->next)\n\t\t*mc_addr_ptr = mc_ptr->next->dmi_addr;\n#endif\n\telse\n\t\t*mc_addr_ptr = NULL;\n\n\treturn addr;\n}\n\n/**\n * ixgbe_write_mc_addr_list - write multicast addresses to MTA\n * @netdev: network interface device structure\n *\n * Writes multicast address list to the MTA hash table.\n * Returns: -ENOMEM on failure\n * 0 on no addresses written\n * X on writing X addresses to MTA\n **/\nint ixgbe_write_mc_addr_list(struct net_device *netdev)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_hw *hw = &adapter->hw;\n#ifdef NETDEV_HW_ADDR_T_MULTICAST\n\tstruct netdev_hw_addr *ha;\n#endif\n\tu8 *addr_list = NULL;\n\tint addr_count = 0;\n\n\tif (!hw->mac.ops.update_mc_addr_list)\n\t\treturn -ENOMEM;\n\n\tif (!netif_running(netdev))\n\t\treturn 0;\n\n\n\thw->mac.ops.update_mc_addr_list(hw, NULL, 0,\n\t\t\t\t\tixgbe_addr_list_itr, true);\n\n\tif (!netdev_mc_empty(netdev)) {\n#ifdef NETDEV_HW_ADDR_T_MULTICAST\n\t\tha = list_first_entry(&netdev->mc.list,\n\t\t\t\t struct netdev_hw_addr, list);\n\t\taddr_list = ha->addr;\n#else\n\t\taddr_list = netdev->mc_list->dmi_addr;\n#endif\n\t\taddr_count = netdev_mc_count(netdev);\n\n\t\thw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,\n\t\t\t\t\t\tixgbe_addr_list_itr, false);\n\t}\n\n#ifdef CONFIG_PCI_IOV\n\t//ixgbe_restore_vf_multicasts(adapter);\n#endif\n\treturn addr_count;\n}\n\n\nvoid ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tint i;\n\tfor (i = 0; i < hw->mac.num_rar_entries; i++) {\n\t\tif (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE) {\n\t\t\thw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,\n\t\t\t\t\t\tadapter->mac_table[i].queue,\n\t\t\t\t\t\tIXGBE_RAH_AV);\n\t\t} else {\n\t\t\thw->mac.ops.clear_rar(hw, i);\n\t\t}\n\t}\n}\n\nvoid ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tint i;\n\tfor (i = 0; i < hw->mac.num_rar_entries; i++) {\n\t\tif (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {\n\t\t\tif (adapter->mac_table[i].state &\n\t\t\t\t\tIXGBE_MAC_STATE_IN_USE) {\n\t\t\t\thw->mac.ops.set_rar(hw, i,\n\t\t\t\t\t\tadapter->mac_table[i].addr,\n\t\t\t\t\t\tadapter->mac_table[i].queue,\n\t\t\t\t\t\tIXGBE_RAH_AV);\n\t\t\t} else {\n\t\t\t\thw->mac.ops.clear_rar(hw, i);\n\t\t\t}\n\t\t\tadapter->mac_table[i].state &=\n\t\t\t\t~(IXGBE_MAC_STATE_MODIFIED);\n\t\t}\n\t}\n}\n\nint ixgbe_available_rars(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tint i, count = 0;\n\n\tfor (i = 0; i < hw->mac.num_rar_entries; i++) {\n\t\tif (adapter->mac_table[i].state == 0)\n\t\t\tcount++;\n\t}\n\treturn count;\n}\n\nint ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tint i;\n\n\tif (is_zero_ether_addr(addr))\n\t\treturn 0;\n\n\tfor (i = 0; i < hw->mac.num_rar_entries; i++) {\n\t\tif (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)\n\t\t\tcontinue;\n\t\tadapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |\n\t\t\t\t\t\tIXGBE_MAC_STATE_IN_USE);\n\t\tmemcpy(adapter->mac_table[i].addr, addr, ETH_ALEN);\n\t\tadapter->mac_table[i].queue = queue;\n\t\tixgbe_sync_mac_table(adapter);\n\t\treturn i;\n\t}\n\treturn -ENOMEM;\n}\n\nvoid ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)\n{\n\tint i;\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\n\tfor (i = 0; i < hw->mac.num_rar_entries; i++) {\n\t\tadapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;\n\t\tadapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;\n\t\tmemset(adapter->mac_table[i].addr, 0, ETH_ALEN);\n\t\tadapter->mac_table[i].queue = 0;\n\t}\n\tixgbe_sync_mac_table(adapter);\n}\n\nvoid ixgbe_del_mac_filter_by_index(struct ixgbe_adapter *adapter, int index)\n{\n\tadapter->mac_table[index].state |= IXGBE_MAC_STATE_MODIFIED;\n\tadapter->mac_table[index].state &= ~IXGBE_MAC_STATE_IN_USE;\n\tmemset(adapter->mac_table[index].addr, 0, ETH_ALEN);\n\tadapter->mac_table[index].queue = 0;\n\tixgbe_sync_mac_table(adapter);\n}\n\nint ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8* addr, u16 queue)\n{\n\t/* search table for addr, if found, set to 0 and sync */\n\tint i;\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\n\tif (is_zero_ether_addr(addr))\n\t\treturn 0;\n\tfor (i = 0; i < hw->mac.num_rar_entries; i++) {\n\t\tif (ether_addr_equal(addr, adapter->mac_table[i].addr) &&\n\t\t adapter->mac_table[i].queue == queue) {\n\t\t\tadapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;\n\t\t\tadapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;\n\t\t\tmemset(adapter->mac_table[i].addr, 0, ETH_ALEN);\n\t\t\tadapter->mac_table[i].queue = 0;\n\t\t\tixgbe_sync_mac_table(adapter);\n\t\t\treturn 0;\n\t\t}\n\t}\n\treturn -ENOMEM;\n}\n#ifdef HAVE_SET_RX_MODE\n/**\n * ixgbe_write_uc_addr_list - write unicast addresses to RAR table\n * @netdev: network interface device structure\n *\n * Writes unicast address list to the RAR table.\n * Returns: -ENOMEM on failure/insufficient address space\n * 0 on no addresses written\n * X on writing X addresses to the RAR table\n **/\nint ixgbe_write_uc_addr_list(struct ixgbe_adapter *adapter,\n\t\t\t struct net_device *netdev, unsigned int vfn)\n{\n\tint count = 0;\n\n\t/* return ENOMEM indicating insufficient memory for addresses */\n\tif (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))\n\t\treturn -ENOMEM;\n\n\tif (!netdev_uc_empty(netdev)) {\n#ifdef NETDEV_HW_ADDR_T_UNICAST\n\t\tstruct netdev_hw_addr *ha;\n#else\n\t\tstruct dev_mc_list *ha;\n#endif\n\t\tnetdev_for_each_uc_addr(ha, netdev) {\n#ifdef NETDEV_HW_ADDR_T_UNICAST\n\t\t\tixgbe_del_mac_filter(adapter, ha->addr, (u16)vfn);\n\t\t\tixgbe_add_mac_filter(adapter, ha->addr, (u16)vfn);\n#else\n\t\t\tixgbe_del_mac_filter(adapter, ha->da_addr, (u16)vfn);\n\t\t\tixgbe_add_mac_filter(adapter, ha->da_addr, (u16)vfn);\n#endif\n\t\t\tcount++;\n\t\t}\n\t}\n\treturn count;\n}\n\n#endif\n/**\n * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set\n * @netdev: network interface device structure\n *\n * The set_rx_method entry point is called whenever the unicast/multicast\n * address list or the network interface flags are updated. This routine is\n * responsible for configuring the hardware for proper unicast, multicast and\n * promiscuous mode.\n **/\nvoid ixgbe_set_rx_mode(struct net_device *netdev)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tu32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;\n\tu32 vlnctrl;\n\tint count;\n\n\t/* Check for Promiscuous and All Multicast modes */\n\tfctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);\n\tvlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);\n\n\t/* set all bits that we expect to always be set */\n\tfctrl |= IXGBE_FCTRL_BAM;\n\tfctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */\n\tfctrl |= IXGBE_FCTRL_PMCF;\n\n\t/* clear the bits we are changing the status of */\n\tfctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);\n\tvlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);\n\n\tif (netdev->flags & IFF_PROMISC) {\n\t\thw->addr_ctrl.user_set_promisc = true;\n\t\tfctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);\n\t\tvmolr |= IXGBE_VMOLR_MPE;\n\t} else {\n\t\tif (netdev->flags & IFF_ALLMULTI) {\n\t\t\tfctrl |= IXGBE_FCTRL_MPE;\n\t\t\tvmolr |= IXGBE_VMOLR_MPE;\n\t\t} else {\n\t\t\t/*\n\t\t\t * Write addresses to the MTA, if the attempt fails\n\t\t\t * then we should just turn on promiscuous mode so\n\t\t\t * that we can at least receive multicast traffic\n\t\t\t */\n\t\t\tcount = ixgbe_write_mc_addr_list(netdev);\n\t\t\tif (count < 0) {\n\t\t\t\tfctrl |= IXGBE_FCTRL_MPE;\n\t\t\t\tvmolr |= IXGBE_VMOLR_MPE;\n\t\t\t} else if (count) {\n\t\t\t\tvmolr |= IXGBE_VMOLR_ROMPE;\n\t\t\t}\n\t\t}\n#ifdef NETIF_F_HW_VLAN_TX\n\t\t/* enable hardware vlan filtering */\n\t\tvlnctrl |= IXGBE_VLNCTRL_VFE;\n#endif\n\t\thw->addr_ctrl.user_set_promisc = false;\n#ifdef HAVE_SET_RX_MODE\n\t\t/*\n\t\t * Write addresses to available RAR registers, if there is not\n\t\t * sufficient space to store all the addresses then enable\n\t\t * unicast promiscuous mode\n\t\t */\n\t\tcount = ixgbe_write_uc_addr_list(adapter, netdev,\n\t\t\t\t\t\t adapter->num_vfs);\n\t\tif (count < 0) {\n\t\t\tfctrl |= IXGBE_FCTRL_UPE;\n\t\t\tvmolr |= IXGBE_VMOLR_ROPE;\n\t\t}\n#endif\n\t}\n\n\tif (hw->mac.type != ixgbe_mac_82598EB) {\n\t\tvmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &\n\t\t\t ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |\n\t\t\t IXGBE_VMOLR_ROPE);\n\t\tIXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);\n\t}\n\n\tIXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);\n\tIXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);\n}\n\n\n\n\n\n\n\n\n/* Additional bittime to account for IXGBE framing */\n#define IXGBE_ETH_FRAMING 20\n\n/*\n * ixgbe_hpbthresh - calculate high water mark for flow control\n *\n * @adapter: board private structure to calculate for\n * @pb - packet buffer to calculate\n */\nstatic int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct net_device *dev = adapter->netdev;\n\tint link, tc, kb, marker;\n\tu32 dv_id, rx_pba;\n\n\t/* Calculate max LAN frame size */\n\ttc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;\n\n#ifdef IXGBE_FCOE\n\t/* FCoE traffic class uses FCOE jumbo frames */\n\tif (dev->features & NETIF_F_FCOE_MTU) {\n\t\tint fcoe_pb = 0;\n\n\t\tfcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);\n\n\t\tif (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)\n\t\t\ttc = IXGBE_FCOE_JUMBO_FRAME_SIZE;\n\t}\n#endif\n\n\t/* Calculate delay value for device */\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_X540:\n\t\tdv_id = IXGBE_DV_X540(link, tc);\n\t\tbreak;\n\tdefault:\n\t\tdv_id = IXGBE_DV(link, tc);\n\t\tbreak;\n\t}\n\n\t/* Loopback switch introduces additional latency */\n\tif (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)\n\t\tdv_id += IXGBE_B2BT(tc);\n\n\t/* Delay value is calculated in bit times convert to KB */\n\tkb = IXGBE_BT2KB(dv_id);\n\trx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;\n\n\tmarker = rx_pba - kb;\n\n\t/* It is possible that the packet buffer is not large enough\n\t * to provide required headroom. In this case throw an error\n\t * to user and a do the best we can.\n\t */\n\tif (marker < 0) {\n\t\te_warn(drv, \"Packet Buffer(%i) can not provide enough\"\n\t\t\t \"headroom to suppport flow control.\"\n\t\t\t \"Decrease MTU or number of traffic classes\\n\", pb);\n\t\tmarker = tc + 1;\n\t}\n\n\treturn marker;\n}\n\n/*\n * ixgbe_lpbthresh - calculate low water mark for for flow control\n *\n * @adapter: board private structure to calculate for\n * @pb - packet buffer to calculate\n */\nstatic int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct net_device *dev = adapter->netdev;\n\tint tc;\n\tu32 dv_id;\n\n\t/* Calculate max LAN frame size */\n\ttc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;\n\n#ifdef IXGBE_FCOE\n\t/* FCoE traffic class uses FCOE jumbo frames */\n\tif (dev->features & NETIF_F_FCOE_MTU) {\n\t\tint fcoe_pb = 0;\n\n\t\tfcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);\n\n\t\tif (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)\n\t\t\ttc = IXGBE_FCOE_JUMBO_FRAME_SIZE;\n\t}\n#endif\n\n\t/* Calculate delay value for device */\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_X540:\n\t\tdv_id = IXGBE_LOW_DV_X540(tc);\n\t\tbreak;\n\tdefault:\n\t\tdv_id = IXGBE_LOW_DV(tc);\n\t\tbreak;\n\t}\n\n\t/* Delay value is calculated in bit times convert to KB */\n\treturn IXGBE_BT2KB(dv_id);\n}\n\n/*\n * ixgbe_pbthresh_setup - calculate and setup high low water marks\n */\nstatic void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tint num_tc = netdev_get_num_tc(adapter->netdev);\n\tint i;\n\n\tif (!num_tc)\n\t\tnum_tc = 1;\n\tif (num_tc > IXGBE_DCB_MAX_TRAFFIC_CLASS)\n\t\tnum_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;\n\n\tfor (i = 0; i < num_tc; i++) {\n\t\thw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);\n\t\thw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);\n\n\t\t/* Low water marks must not be larger than high water marks */\n\t\tif (hw->fc.low_water[i] > hw->fc.high_water[i])\n\t\t\thw->fc.low_water[i] = 0;\n\t}\n\n\tfor (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++)\n\t\thw->fc.high_water[i] = 0;\n}\n\n\n\n#ifdef NO_VNIC\nstatic void ixgbe_configure(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\n\tixgbe_configure_pb(adapter);\n\tixgbe_configure_dcb(adapter);\n\n\tixgbe_set_rx_mode(adapter->netdev);\n#ifdef NETIF_F_HW_VLAN_TX\n\tixgbe_restore_vlan(adapter);\n#endif\n\n#ifdef IXGBE_FCOE\n\tif (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)\n\t\tixgbe_configure_fcoe(adapter);\n\n#endif /* IXGBE_FCOE */\n\n\tif (adapter->hw.mac.type != ixgbe_mac_82598EB)\n\t\thw->mac.ops.disable_sec_rx_path(hw);\n\n\tif (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {\n\t\tixgbe_init_fdir_signature_82599(&adapter->hw,\n\t\t\t\t\t\tadapter->fdir_pballoc);\n\t} else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {\n\t\tixgbe_init_fdir_perfect_82599(&adapter->hw,\n\t\t\t\t\t adapter->fdir_pballoc);\n\t\tixgbe_fdir_filter_restore(adapter);\n\t}\n\n\tif (adapter->hw.mac.type != ixgbe_mac_82598EB)\n\t\thw->mac.ops.enable_sec_rx_path(hw);\n\n\tixgbe_configure_virtualization(adapter);\n\n\tixgbe_configure_tx(adapter);\n\tixgbe_configure_rx(adapter);\n}\n#endif\n\nstatic bool ixgbe_is_sfp(struct ixgbe_hw *hw)\n{\n\tswitch (hw->phy.type) {\n\tcase ixgbe_phy_sfp_avago:\n\tcase ixgbe_phy_sfp_ftl:\n\tcase ixgbe_phy_sfp_intel:\n\tcase ixgbe_phy_sfp_unknown:\n\tcase ixgbe_phy_sfp_passive_tyco:\n\tcase ixgbe_phy_sfp_passive_unknown:\n\tcase ixgbe_phy_sfp_active_unknown:\n\tcase ixgbe_phy_sfp_ftl_active:\n\t\treturn true;\n\tcase ixgbe_phy_nl:\n\t\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\t\treturn true;\n\tdefault:\n\t\treturn false;\n\t}\n}\n\n\n/**\n * ixgbe_clear_vf_stats_counters - Clear out VF stats after reset\n * @adapter: board private structure\n *\n * On a reset we need to clear out the VF stats or accounting gets\n * messed up because they're not clear on read.\n **/\nvoid ixgbe_clear_vf_stats_counters(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tint i;\n\n\tfor (i = 0; i < adapter->num_vfs; i++) {\n\t\tadapter->vfinfo[i].last_vfstats.gprc =\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PVFGPRC(i));\n\t\tadapter->vfinfo[i].saved_rst_vfstats.gprc +=\n\t\t\tadapter->vfinfo[i].vfstats.gprc;\n\t\tadapter->vfinfo[i].vfstats.gprc = 0;\n\t\tadapter->vfinfo[i].last_vfstats.gptc =\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PVFGPTC(i));\n\t\tadapter->vfinfo[i].saved_rst_vfstats.gptc +=\n\t\t\tadapter->vfinfo[i].vfstats.gptc;\n\t\tadapter->vfinfo[i].vfstats.gptc = 0;\n\t\tadapter->vfinfo[i].last_vfstats.gorc =\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PVFGORC_LSB(i));\n\t\tadapter->vfinfo[i].saved_rst_vfstats.gorc +=\n\t\t\tadapter->vfinfo[i].vfstats.gorc;\n\t\tadapter->vfinfo[i].vfstats.gorc = 0;\n\t\tadapter->vfinfo[i].last_vfstats.gotc =\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PVFGOTC_LSB(i));\n\t\tadapter->vfinfo[i].saved_rst_vfstats.gotc +=\n\t\t\tadapter->vfinfo[i].vfstats.gotc;\n\t\tadapter->vfinfo[i].vfstats.gotc = 0;\n\t\tadapter->vfinfo[i].last_vfstats.mprc =\n\t\t\tIXGBE_READ_REG(hw, IXGBE_PVFMPRC(i));\n\t\tadapter->vfinfo[i].saved_rst_vfstats.mprc +=\n\t\t\tadapter->vfinfo[i].vfstats.mprc;\n\t\tadapter->vfinfo[i].vfstats.mprc = 0;\n\t}\n}\n\n\n\nvoid ixgbe_reinit_locked(struct ixgbe_adapter *adapter)\n{\n#ifdef NO_VNIC\n\tWARN_ON(in_interrupt());\n\t/* put off any impending NetWatchDogTimeout */\n\tadapter->netdev->trans_start = jiffies;\n\n\twhile (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))\n\t\tusleep_range(1000, 2000);\n\tixgbe_down(adapter);\n\t/*\n\t * If SR-IOV enabled then wait a bit before bringing the adapter\n\t * back up to give the VFs time to respond to the reset. The\n\t * two second wait is based upon the watchdog timer cycle in\n\t * the VF driver.\n\t */\n\tif (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)\n\t\tmsleep(2000);\n\tixgbe_up(adapter);\n\tclear_bit(__IXGBE_RESETTING, &adapter->state);\n#endif\n}\n\nvoid ixgbe_up(struct ixgbe_adapter *adapter)\n{\n\t/* hardware has been reset, we need to reload some things */\n\t//ixgbe_configure(adapter);\n\n\t//ixgbe_up_complete(adapter);\n}\n\nvoid ixgbe_reset(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct net_device *netdev = adapter->netdev;\n\tint err;\n\n\t/* lock SFP init bit to prevent race conditions with the watchdog */\n\twhile (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))\n\t\tusleep_range(1000, 2000);\n\n\t/* clear all SFP and link config related flags while holding SFP_INIT */\n\tadapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |\n\t\t\t IXGBE_FLAG2_SFP_NEEDS_RESET);\n\tadapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;\n\n\terr = hw->mac.ops.init_hw(hw);\n\tswitch (err) {\n\tcase 0:\n\tcase IXGBE_ERR_SFP_NOT_PRESENT:\n\tcase IXGBE_ERR_SFP_NOT_SUPPORTED:\n\t\tbreak;\n\tcase IXGBE_ERR_MASTER_REQUESTS_PENDING:\n\t\te_dev_err(\"master disable timed out\\n\");\n\t\tbreak;\n\tcase IXGBE_ERR_EEPROM_VERSION:\n\t\t/* We are running on a pre-production device, log a warning */\n\t\te_dev_warn(\"This device is a pre-production adapter/LOM. \"\n\t\t\t \"Please be aware there may be issues associated \"\n\t\t\t \"with your hardware. If you are experiencing \"\n\t\t\t \"problems please contact your Intel or hardware \"\n\t\t\t \"representative who provided you with this \"\n\t\t\t \"hardware.\\n\");\n\t\tbreak;\n\tdefault:\n\t\te_dev_err(\"Hardware Error: %d\\n\", err);\n\t}\n\n\tclear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);\n\n\tixgbe_flush_sw_mac_table(adapter);\n\tmemcpy(&adapter->mac_table[0].addr, hw->mac.perm_addr,\n\t netdev->addr_len);\n\tadapter->mac_table[0].queue = adapter->num_vfs;\n\tadapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |\n\t\t\t\t\tIXGBE_MAC_STATE_IN_USE);\n\thw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,\n\t\t\t\tadapter->mac_table[0].queue,\n\t\t\t\tIXGBE_RAH_AV);\n}\n\n\n\n\n\n\nvoid ixgbe_down(struct ixgbe_adapter *adapter)\n{\n#ifdef NO_VNIC\n\tstruct net_device *netdev = adapter->netdev;\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tu32 rxctrl;\n\tint i;\n\n\t/* signal that we are down to the interrupt handler */\n\tset_bit(__IXGBE_DOWN, &adapter->state);\n\n\t/* disable receives */\n\trxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n\tIXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);\n\n\t/* disable all enabled rx queues */\n\tfor (i = 0; i < adapter->num_rx_queues; i++)\n\t\t/* this call also flushes the previous write */\n\t\tixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);\n\n\tusleep_range(10000, 20000);\n\n\tnetif_tx_stop_all_queues(netdev);\n\n\t/* call carrier off first to avoid false dev_watchdog timeouts */\n\tnetif_carrier_off(netdev);\n\tnetif_tx_disable(netdev);\n\n\tixgbe_irq_disable(adapter);\n\n\tixgbe_napi_disable_all(adapter);\n\n\tadapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |\n\t\t\t IXGBE_FLAG2_RESET_REQUESTED);\n\tadapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;\n\n\tdel_timer_sync(&adapter->service_timer);\n\n\tif (adapter->num_vfs) {\n\t\t/* Clear EITR Select mapping */\n\t\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);\n\n\t\t/* Mark all the VFs as inactive */\n\t\tfor (i = 0 ; i < adapter->num_vfs; i++)\n\t\t\tadapter->vfinfo[i].clear_to_send = 0;\n\n\t\t/* ping all the active vfs to let them know we are going down */\n\t\tixgbe_ping_all_vfs(adapter);\n\n\t\t/* Disable all VFTE/VFRE TX/RX */\n\t\tixgbe_disable_tx_rx(adapter);\n\t}\n\n\t/* disable transmits in the hardware now that interrupts are off */\n\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\tu8 reg_idx = adapter->tx_ring[i]->reg_idx;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);\n\t}\n\n\t/* Disable the Tx DMA engine on 82599 and X540 */\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\t\tIXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,\n\t\t\t\t(IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &\n\t\t\t\t ~IXGBE_DMATXCTL_TE));\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n#ifdef HAVE_PCI_ERS\n\tif (!pci_channel_offline(adapter->pdev))\n#endif\n\t\tixgbe_reset(adapter);\n\t/* power down the optics */\n\tif ((hw->phy.multispeed_fiber) ||\n\t ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&\n\t (hw->mac.type == ixgbe_mac_82599EB)))\n\t\tixgbe_disable_tx_laser(hw);\n\n\tixgbe_clean_all_tx_rings(adapter);\n\tixgbe_clean_all_rx_rings(adapter);\n\n#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)\n\t/* since we reset the hardware DCA settings were cleared */\n\tixgbe_setup_dca(adapter);\n#endif\n\n#endif /* NO_VNIC */\n}\n\n#ifndef NO_VNIC\n\n#undef IXGBE_FCOE\n\n/* Artificial max queue cap per traffic class in DCB mode */\n#define DCB_QUEUE_CAP 8\n\n/**\n * ixgbe_set_dcb_queues: Allocate queues for a DCB-enabled device\n * @adapter: board private structure to initialize\n *\n * When DCB (Data Center Bridging) is enabled, allocate queues for\n * each traffic class. If multiqueue isn't available,then abort DCB\n * initialization.\n *\n * This function handles all combinations of DCB, RSS, and FCoE.\n *\n **/\nstatic bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)\n{\n int tcs;\n#ifdef HAVE_MQPRIO\n int rss_i, i, offset = 0;\n struct net_device *dev = adapter->netdev;\n\n /* Map queue offset and counts onto allocated tx queues */\n tcs = netdev_get_num_tc(dev);\n\n if (!tcs)\n return false;\n\n rss_i = min_t(int, dev->num_tx_queues / tcs, num_online_cpus());\n\n if (rss_i > DCB_QUEUE_CAP)\n rss_i = DCB_QUEUE_CAP;\n\n for (i = 0; i < tcs; i++) {\n netdev_set_tc_queue(dev, i, rss_i, offset);\n offset += rss_i;\n }\n\n adapter->num_tx_queues = rss_i * tcs;\n adapter->num_rx_queues = rss_i * tcs;\n\n#ifdef IXGBE_FCOE\n /* FCoE enabled queues require special configuration indexed\n * by feature specific indices and mask. Here we map FCoE\n * indices onto the DCB queue pairs allowing FCoE to own\n * configuration later.\n */\n\n if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {\n struct ixgbe_ring_feature *f;\n int tc;\n u8 prio_tc[IXGBE_DCB_MAX_USER_PRIORITY] = {0};\n\n ixgbe_dcb_unpack_map_cee(&adapter->dcb_cfg,\n IXGBE_DCB_TX_CONFIG,\n prio_tc);\n tc = prio_tc[adapter->fcoe.up];\n\n f = &adapter->ring_feature[RING_F_FCOE];\n f->indices = min_t(int, rss_i, f->indices);\n f->mask = rss_i * tc;\n }\n#endif /* IXGBE_FCOE */\n#else\n if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))\n return false;\n\n /* Enable one Queue per traffic class */\n tcs = adapter->tc;\n if (!tcs)\n return false;\n\n#ifdef IXGBE_FCOE\n if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {\n struct ixgbe_ring_feature *f;\n int tc = netdev_get_prio_tc_map(adapter->netdev,\n adapter->fcoe.up);\n\n f = &adapter->ring_feature[RING_F_FCOE];\n\n /*\n * We have max 8 queues for FCoE, where 8 the is\n * FCoE redirection table size. We must also share\n * ring resources with network traffic so if FCoE TC is\n * 4 or greater and we are in 8 TC mode we can only use\n * 7 queues.\n */\n if ((tcs > 4) && (tc >= 4) && (f->indices > 7))\n f->indices = 7;\n\n f->indices = min_t(int, num_online_cpus(), f->indices);\n f->mask = tcs;\n\n adapter->num_rx_queues = f->indices + tcs;\n adapter->num_tx_queues = f->indices + tcs;\n\n return true;\n }\n\n#endif /* IXGBE_FCOE */\n adapter->num_rx_queues = tcs;\n adapter->num_tx_queues = tcs;\n#endif /* HAVE_MQ */\n\n return true;\n}\n\n/**\n * ixgbe_set_vmdq_queues: Allocate queues for VMDq devices\n * @adapter: board private structure to initialize\n *\n * When VMDq (Virtual Machine Devices queue) is enabled, allocate queues\n * and VM pools where appropriate. If RSS is available, then also try and\n * enable RSS and map accordingly.\n *\n **/\nstatic bool ixgbe_set_vmdq_queues(struct ixgbe_adapter *adapter)\n{\n int vmdq_i = adapter->ring_feature[RING_F_VMDQ].indices;\n int vmdq_m = 0;\n int rss_i = adapter->ring_feature[RING_F_RSS].indices;\n unsigned long i;\n int rss_shift;\n bool ret = false;\n\n\n switch (adapter->flags & (IXGBE_FLAG_RSS_ENABLED\n | IXGBE_FLAG_DCB_ENABLED\n | IXGBE_FLAG_VMDQ_ENABLED)) {\n\n case (IXGBE_FLAG_RSS_ENABLED | IXGBE_FLAG_VMDQ_ENABLED):\n switch (adapter->hw.mac.type) {\n case ixgbe_mac_82599EB:\n case ixgbe_mac_X540:\n vmdq_i = min((int)IXGBE_MAX_VMDQ_INDICES, vmdq_i);\n if (vmdq_i > 32)\n rss_i = 2;\n else\n rss_i = 4;\n i = rss_i;\n rss_shift = find_first_bit(&i, sizeof(i) * 8);\n vmdq_m = ((IXGBE_MAX_VMDQ_INDICES - 1) <<\n rss_shift) & (MAX_RX_QUEUES - 1);\n break;\n default:\n break;\n }\n adapter->num_rx_queues = vmdq_i * rss_i;\n adapter->num_tx_queues = min((int)MAX_TX_QUEUES, vmdq_i * rss_i);\n ret = true;\n break;\n\n case (IXGBE_FLAG_VMDQ_ENABLED):\n switch (adapter->hw.mac.type) {\n case ixgbe_mac_82598EB:\n vmdq_m = (IXGBE_MAX_VMDQ_INDICES - 1);\n break;\n case ixgbe_mac_82599EB:\n case ixgbe_mac_X540:\n vmdq_m = (IXGBE_MAX_VMDQ_INDICES - 1) << 1;\n break;\n default:\n break;\n }\n adapter->num_rx_queues = vmdq_i;\n adapter->num_tx_queues = vmdq_i;\n ret = true;\n break;\n\n default:\n ret = false;\n goto vmdq_queues_out;\n }\n\n if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {\n adapter->num_rx_pools = vmdq_i;\n adapter->num_rx_queues_per_pool = adapter->num_rx_queues /\n vmdq_i;\n } else {\n adapter->num_rx_pools = adapter->num_rx_queues;\n adapter->num_rx_queues_per_pool = 1;\n }\n /* save the mask for later use */\n adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m;\nvmdq_queues_out:\n return ret;\n}\n\n/**\n * ixgbe_set_rss_queues: Allocate queues for RSS\n * @adapter: board private structure to initialize\n *\n * This is our \"base\" multiqueue mode. RSS (Receive Side Scaling) will try\n * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.\n *\n **/\nstatic bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)\n{\n struct ixgbe_ring_feature *f;\n\n if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {\n adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;\n return false;\n }\n\n /* set mask for 16 queue limit of RSS */\n f = &adapter->ring_feature[RING_F_RSS];\n f->mask = 0xF;\n\n /*\n * Use Flow Director in addition to RSS to ensure the best\n * distribution of flows across cores, even when an FDIR flow\n * isn't matched.\n */\n if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {\n f = &adapter->ring_feature[RING_F_FDIR];\n\n f->indices = min_t(int, num_online_cpus(), f->indices);\n f->mask = 0;\n }\n\n adapter->num_rx_queues = f->indices;\n#ifdef HAVE_TX_MQ\n adapter->num_tx_queues = f->indices;\n#endif\n\n return true;\n}\n\n#ifdef IXGBE_FCOE\n/**\n * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)\n * @adapter: board private structure to initialize\n *\n * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.\n * The ring feature mask is not used as a mask for FCoE, as it can take any 8\n * rx queues out of the max number of rx queues, instead, it is used as the\n * index of the first rx queue used by FCoE.\n *\n **/\nstatic bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)\n{\n struct ixgbe_ring_feature *f;\n\n if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))\n return false;\n\n ixgbe_set_rss_queues(adapter);\n\n f = &adapter->ring_feature[RING_F_FCOE];\n f->indices = min_t(int, num_online_cpus(), f->indices);\n\n /* adding FCoE queues */\n f->mask = adapter->num_rx_queues;\n adapter->num_rx_queues += f->indices;\n adapter->num_tx_queues += f->indices;\n\n return true;\n}\n\n#endif /* IXGBE_FCOE */\n/*\n * ixgbe_set_num_queues: Allocate queues for device, feature dependent\n * @adapter: board private structure to initialize\n *\n * This is the top level queue allocation routine. The order here is very\n * important, starting with the \"most\" number of features turned on at once,\n * and ending with the smallest set of features. This way large combinations\n * can be allocated if they're turned on, and smaller combinations are the\n * fallthrough conditions.\n *\n **/\nstatic void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)\n{\n /* Start with base case */\n adapter->num_rx_queues = 1;\n adapter->num_tx_queues = 1;\n adapter->num_rx_pools = adapter->num_rx_queues;\n adapter->num_rx_queues_per_pool = 1;\n\n if (ixgbe_set_vmdq_queues(adapter))\n return;\n\n if (ixgbe_set_dcb_queues(adapter))\n return;\n\n#ifdef IXGBE_FCOE\n if (ixgbe_set_fcoe_queues(adapter))\n return;\n\n#endif /* IXGBE_FCOE */\n ixgbe_set_rss_queues(adapter);\n}\n\n#endif\n\n\n/**\n * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)\n * @adapter: board private structure to initialize\n *\n * ixgbe_sw_init initializes the Adapter private data structure.\n * Fields are initialized based on PCI device information and\n * OS network device settings (MTU size).\n **/\nstatic int ixgbe_sw_init(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct pci_dev *pdev = adapter->pdev;\n\tint err;\n\n\t/* PCI config space info */\n\n\thw->vendor_id = pdev->vendor;\n\thw->device_id = pdev->device;\n\tpci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);\n\thw->subsystem_vendor_id = pdev->subsystem_vendor;\n\thw->subsystem_device_id = pdev->subsystem_device;\n\n\terr = ixgbe_init_shared_code(hw);\n\tif (err) {\n\t\te_err(probe, \"init_shared_code failed: %d\\n\", err);\n\t\tgoto out;\n\t}\n\tadapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *\n\t\t\t\t hw->mac.num_rar_entries,\n\t\t\t\t GFP_ATOMIC);\n\t/* Set capability flags */\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\tadapter->flags |= IXGBE_FLAG_MSI_CAPABLE |\n\t\t\t\t IXGBE_FLAG_MSIX_CAPABLE |\n\t\t\t\t IXGBE_FLAG_MQ_CAPABLE |\n\t\t\t\t IXGBE_FLAG_RSS_CAPABLE;\n\t\tadapter->flags |= IXGBE_FLAG_DCB_CAPABLE;\n#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)\n\t\tadapter->flags |= IXGBE_FLAG_DCA_CAPABLE;\n#endif\n\t\tadapter->flags &= ~IXGBE_FLAG_SRIOV_CAPABLE;\n\t\tadapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;\n\n\t\tif (hw->device_id == IXGBE_DEV_ID_82598AT)\n\t\t\tadapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;\n\n\t\tadapter->max_msix_q_vectors = IXGBE_MAX_MSIX_Q_VECTORS_82598;\n\t\tbreak;\n\tcase ixgbe_mac_X540:\n\t\tadapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;\n\tcase ixgbe_mac_82599EB:\n\t\tadapter->flags |= IXGBE_FLAG_MSI_CAPABLE |\n\t\t\t\t IXGBE_FLAG_MSIX_CAPABLE |\n\t\t\t\t IXGBE_FLAG_MQ_CAPABLE |\n\t\t\t\t IXGBE_FLAG_RSS_CAPABLE;\n\t\tadapter->flags |= IXGBE_FLAG_DCB_CAPABLE;\n#if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)\n\t\tadapter->flags |= IXGBE_FLAG_DCA_CAPABLE;\n#endif\n\t\tadapter->flags |= IXGBE_FLAG_SRIOV_CAPABLE;\n\t\tadapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;\n#ifdef IXGBE_FCOE\n\t\tadapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;\n\t\tadapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;\n\t\tadapter->ring_feature[RING_F_FCOE].indices = 0;\n#ifdef CONFIG_DCB\n\t\t/* Default traffic class to use for FCoE */\n\t\tadapter->fcoe.tc = IXGBE_FCOE_DEFTC;\n\t\tadapter->fcoe.up = IXGBE_FCOE_DEFTC;\n\t\tadapter->fcoe.up_set = IXGBE_FCOE_DEFTC;\n#endif\n#endif\n\t\tif (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)\n\t\t\tadapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;\n#ifndef IXGBE_NO_SMART_SPEED\n\t\thw->phy.smart_speed = ixgbe_smart_speed_on;\n#else\n\t\thw->phy.smart_speed = ixgbe_smart_speed_off;\n#endif\n\t\tadapter->max_msix_q_vectors = IXGBE_MAX_MSIX_Q_VECTORS_82599;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/* n-tuple support exists, always init our spinlock */\n\t//spin_lock_init(&adapter->fdir_perfect_lock);\n\n\tif (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) {\n\t\tint j;\n\t\tstruct ixgbe_dcb_tc_config *tc;\n\t\tint dcb_i = IXGBE_DCB_MAX_TRAFFIC_CLASS;\n\n\n\t\tadapter->dcb_cfg.num_tcs.pg_tcs = dcb_i;\n\t\tadapter->dcb_cfg.num_tcs.pfc_tcs = dcb_i;\n\t\tfor (j = 0; j < dcb_i; j++) {\n\t\t\ttc = &adapter->dcb_cfg.tc_config[j];\n\t\t\ttc->path[IXGBE_DCB_TX_CONFIG].bwg_id = 0;\n\t\t\ttc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 100 / dcb_i;\n\t\t\ttc->path[IXGBE_DCB_RX_CONFIG].bwg_id = 0;\n\t\t\ttc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 100 / dcb_i;\n\t\t\ttc->pfc = ixgbe_dcb_pfc_disabled;\n\t\t\tif (j == 0) {\n\t\t\t\t/* total of all TCs bandwidth needs to be 100 */\n\t\t\t\ttc->path[IXGBE_DCB_TX_CONFIG].bwg_percent +=\n\t\t\t\t\t\t\t\t 100 % dcb_i;\n\t\t\t\ttc->path[IXGBE_DCB_RX_CONFIG].bwg_percent +=\n\t\t\t\t\t\t\t\t 100 % dcb_i;\n\t\t\t}\n\t\t}\n\n\t\t/* Initialize default user to priority mapping, UPx->TC0 */\n\t\ttc = &adapter->dcb_cfg.tc_config[0];\n\t\ttc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;\n\t\ttc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;\n\n\t\tadapter->dcb_cfg.bw_percentage[IXGBE_DCB_TX_CONFIG][0] = 100;\n\t\tadapter->dcb_cfg.bw_percentage[IXGBE_DCB_RX_CONFIG][0] = 100;\n\t\tadapter->dcb_cfg.rx_pba_cfg = ixgbe_dcb_pba_equal;\n\t\tadapter->dcb_cfg.pfc_mode_enable = false;\n\t\tadapter->dcb_cfg.round_robin_enable = false;\n\t\tadapter->dcb_set_bitmap = 0x00;\n#ifdef CONFIG_DCB\n\t\tadapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;\n#endif /* CONFIG_DCB */\n\n\t\tif (hw->mac.type == ixgbe_mac_X540) {\n\t\t\tadapter->dcb_cfg.num_tcs.pg_tcs = 4;\n\t\t\tadapter->dcb_cfg.num_tcs.pfc_tcs = 4;\n\t\t}\n\t}\n#ifdef CONFIG_DCB\n\t/* XXX does this need to be initialized even w/o DCB? */\n\t//memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,\n\t// sizeof(adapter->temp_dcb_cfg));\n\n#endif\n\t//if (hw->mac.type == ixgbe_mac_82599EB ||\n\t// hw->mac.type == ixgbe_mac_X540)\n\t//\thw->mbx.ops.init_params(hw);\n\n\t/* default flow control settings */\n\thw->fc.requested_mode = ixgbe_fc_full;\n\thw->fc.current_mode = ixgbe_fc_full;\t/* init for ethtool output */\n\n\tadapter->last_lfc_mode = hw->fc.current_mode;\n\tixgbe_pbthresh_setup(adapter);\n\thw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;\n\thw->fc.send_xon = true;\n\thw->fc.disable_fc_autoneg = false;\n\n\t/* set default ring sizes */\n\tadapter->tx_ring_count = IXGBE_DEFAULT_TXD;\n\tadapter->rx_ring_count = IXGBE_DEFAULT_RXD;\n\n\t/* set default work limits */\n\tadapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;\n\tadapter->rx_work_limit = IXGBE_DEFAULT_RX_WORK;\n\n\tset_bit(__IXGBE_DOWN, &adapter->state);\nout:\n\treturn err;\n}\n\n/**\n * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)\n * @tx_ring: tx descriptor ring (for a specific queue) to setup\n *\n * Return 0 on success, negative on failure\n **/\nint ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)\n{\n\tstruct device *dev = tx_ring->dev;\n\t//int orig_node = dev_to_node(dev);\n\tint numa_node = -1;\n\tint size;\n\n\tsize = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;\n\n\tif (tx_ring->q_vector)\n\t\tnuma_node = tx_ring->q_vector->numa_node;\n\n\ttx_ring->tx_buffer_info = vzalloc_node(size, numa_node);\n\tif (!tx_ring->tx_buffer_info)\n\t\ttx_ring->tx_buffer_info = vzalloc(size);\n\tif (!tx_ring->tx_buffer_info)\n\t\tgoto err;\n\n\t/* round up to nearest 4K */\n\ttx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);\n\ttx_ring->size = ALIGN(tx_ring->size, 4096);\n\n\t//set_dev_node(dev, numa_node);\n\t//tx_ring->desc = dma_alloc_coherent(dev,\n\t//\t\t\t\t tx_ring->size,\n\t//\t\t\t\t &tx_ring->dma,\n\t//\t\t\t\t GFP_KERNEL);\n\t//set_dev_node(dev, orig_node);\n\t//if (!tx_ring->desc)\n\t//\ttx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,\n\t//\t\t\t\t\t &tx_ring->dma, GFP_KERNEL);\n\t//if (!tx_ring->desc)\n\t//\tgoto err;\n\n\treturn 0;\n\nerr:\n\tvfree(tx_ring->tx_buffer_info);\n\ttx_ring->tx_buffer_info = NULL;\n\tdev_err(dev, \"Unable to allocate memory for the Tx descriptor ring\\n\");\n\treturn -ENOMEM;\n}\n\n/**\n * ixgbe_setup_all_tx_resources - allocate all queues Tx resources\n * @adapter: board private structure\n *\n * If this function returns with an error, then it's possible one or\n * more of the rings is populated (while the rest are not). It is the\n * callers duty to clean those orphaned rings.\n *\n * Return 0 on success, negative on failure\n **/\nstatic int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)\n{\n\tint i, err = 0;\n\n\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\terr = ixgbe_setup_tx_resources(adapter->tx_ring[i]);\n\t\tif (!err)\n\t\t\tcontinue;\n\t\te_err(probe, \"Allocation for Tx Queue %u failed\\n\", i);\n\t\tbreak;\n\t}\n\n\treturn err;\n}\n\n/**\n * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)\n * @rx_ring: rx descriptor ring (for a specific queue) to setup\n *\n * Returns 0 on success, negative on failure\n **/\nint ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)\n{\n\tstruct device *dev = rx_ring->dev;\n\t//int orig_node = dev_to_node(dev);\n\tint numa_node = -1;\n\tint size;\n\n\tsize = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;\n\n\tif (rx_ring->q_vector)\n\t\tnuma_node = rx_ring->q_vector->numa_node;\n\n\trx_ring->rx_buffer_info = vzalloc_node(size, numa_node);\n\tif (!rx_ring->rx_buffer_info)\n\t\trx_ring->rx_buffer_info = vzalloc(size);\n\tif (!rx_ring->rx_buffer_info)\n\t\tgoto err;\n\n\t/* Round up to nearest 4K */\n\trx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);\n\trx_ring->size = ALIGN(rx_ring->size, 4096);\n\n#ifdef NO_VNIC\n\tset_dev_node(dev, numa_node);\n\trx_ring->desc = dma_alloc_coherent(dev,\n\t\t\t\t\t rx_ring->size,\n\t\t\t\t\t &rx_ring->dma,\n\t\t\t\t\t GFP_KERNEL);\n\tset_dev_node(dev, orig_node);\n\tif (!rx_ring->desc)\n\t\trx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,\n\t\t\t\t\t\t &rx_ring->dma, GFP_KERNEL);\n\tif (!rx_ring->desc)\n\t\tgoto err;\n\n#ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT\n\tixgbe_init_rx_page_offset(rx_ring);\n\n#endif\n\n#endif /* NO_VNIC */\n\treturn 0;\nerr:\n\tvfree(rx_ring->rx_buffer_info);\n\trx_ring->rx_buffer_info = NULL;\n\tdev_err(dev, \"Unable to allocate memory for the Rx descriptor ring\\n\");\n\treturn -ENOMEM;\n}\n\n/**\n * ixgbe_setup_all_rx_resources - allocate all queues Rx resources\n * @adapter: board private structure\n *\n * If this function returns with an error, then it's possible one or\n * more of the rings is populated (while the rest are not). It is the\n * callers duty to clean those orphaned rings.\n *\n * Return 0 on success, negative on failure\n **/\nstatic int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)\n{\n\tint i, err = 0;\n\n\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\terr = ixgbe_setup_rx_resources(adapter->rx_ring[i]);\n\t\tif (!err)\n\t\t\tcontinue;\n\t\te_err(probe, \"Allocation for Rx Queue %u failed\\n\", i);\n\t\tbreak;\n\t}\n\n\treturn err;\n}\n\n/**\n * ixgbe_free_tx_resources - Free Tx Resources per Queue\n * @tx_ring: Tx descriptor ring for a specific queue\n *\n * Free all transmit software resources\n **/\nvoid ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)\n{\n\t//ixgbe_clean_tx_ring(tx_ring);\n\n\tvfree(tx_ring->tx_buffer_info);\n\ttx_ring->tx_buffer_info = NULL;\n\n\t/* if not set, then don't free */\n\tif (!tx_ring->desc)\n\t\treturn;\n\n\t//dma_free_coherent(tx_ring->dev, tx_ring->size,\n\t//\t\t tx_ring->desc, tx_ring->dma);\n\n\ttx_ring->desc = NULL;\n}\n\n/**\n * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues\n * @adapter: board private structure\n *\n * Free all transmit software resources\n **/\nstatic void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)\n{\n\tint i;\n\n\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\tif (adapter->tx_ring[i]->desc)\n\t\t\tixgbe_free_tx_resources(adapter->tx_ring[i]);\n}\n\n/**\n * ixgbe_free_rx_resources - Free Rx Resources\n * @rx_ring: ring to clean the resources from\n *\n * Free all receive software resources\n **/\nvoid ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)\n{\n\t//ixgbe_clean_rx_ring(rx_ring);\n\n\tvfree(rx_ring->rx_buffer_info);\n\trx_ring->rx_buffer_info = NULL;\n\n\t/* if not set, then don't free */\n\tif (!rx_ring->desc)\n\t\treturn;\n\n\t//dma_free_coherent(rx_ring->dev, rx_ring->size,\n\t//\t\t rx_ring->desc, rx_ring->dma);\n\n\trx_ring->desc = NULL;\n}\n\n/**\n * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues\n * @adapter: board private structure\n *\n * Free all receive software resources\n **/\nstatic void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)\n{\n\tint i;\n\n\tfor (i = 0; i < adapter->num_rx_queues; i++)\n\t\tif (adapter->rx_ring[i]->desc)\n\t\t\tixgbe_free_rx_resources(adapter->rx_ring[i]);\n}\n\n\n/**\n * ixgbe_open - Called when a network interface is made active\n * @netdev: network interface device structure\n *\n * Returns 0 on success, negative value on failure\n *\n * The open entry point is called when a network interface is made\n * active by the system (IFF_UP). At this point all resources needed\n * for transmit and receive operations are allocated, the interrupt\n * handler is registered with the OS, the watchdog timer is started,\n * and the stack is notified that the interface is ready.\n **/\n//static\nint ixgbe_open(struct net_device *netdev)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tint err;\n\n\t/* disallow open during test */\n\tif (test_bit(__IXGBE_TESTING, &adapter->state))\n\t\treturn -EBUSY;\n\n\tnetif_carrier_off(netdev);\n\n\t/* allocate transmit descriptors */\n\terr = ixgbe_setup_all_tx_resources(adapter);\n\tif (err)\n\t\tgoto err_setup_tx;\n\n\t/* allocate receive descriptors */\n\terr = ixgbe_setup_all_rx_resources(adapter);\n\tif (err)\n\t\tgoto err_setup_rx;\n\n#ifdef NO_VNIC\n\tixgbe_configure(adapter);\n\n\terr = ixgbe_request_irq(adapter);\n\tif (err)\n\t\tgoto err_req_irq;\n\n\tixgbe_up_complete(adapter);\n\nerr_req_irq:\n#else\n\treturn 0;\n#endif\nerr_setup_rx:\n\tixgbe_free_all_rx_resources(adapter);\nerr_setup_tx:\n\tixgbe_free_all_tx_resources(adapter);\n\tixgbe_reset(adapter);\n\n\treturn err;\n}\n\n/**\n * ixgbe_close - Disables a network interface\n * @netdev: network interface device structure\n *\n * Returns 0, this is not allowed to fail\n *\n * The close entry point is called when an interface is de-activated\n * by the OS. The hardware is still under the drivers control, but\n * needs to be disabled. A global MAC reset is issued to stop the\n * hardware, and all transmit and receive resources are freed.\n **/\n//static\nint ixgbe_close(struct net_device *netdev)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\n\t//ixgbe_down(adapter);\n\t//ixgbe_free_irq(adapter);\n\n\t//ixgbe_fdir_filter_exit(adapter);\n\n\t//ixgbe_free_all_tx_resources(adapter);\n\t//ixgbe_free_all_rx_resources(adapter);\n\n\tixgbe_release_hw_control(adapter);\n\n\treturn 0;\n}\n\n\n\n\n\n/**\n * ixgbe_get_stats - Get System Network Statistics\n * @netdev: network interface device structure\n *\n * Returns the address of the device statistics structure.\n * The statistics are actually updated from the timer callback.\n **/\n//static\nstruct net_device_stats *ixgbe_get_stats(struct net_device *netdev)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\n\t/* update the stats data */\n\tixgbe_update_stats(adapter);\n\n#ifdef HAVE_NETDEV_STATS_IN_NETDEV\n\t/* only return the current stats */\n\treturn &netdev->stats;\n#else\n\t/* only return the current stats */\n\treturn &adapter->net_stats;\n#endif /* HAVE_NETDEV_STATS_IN_NETDEV */\n}\n\n/**\n * ixgbe_update_stats - Update the board statistics counters.\n * @adapter: board private structure\n **/\nvoid ixgbe_update_stats(struct ixgbe_adapter *adapter)\n{\n#ifdef HAVE_NETDEV_STATS_IN_NETDEV\n\tstruct net_device_stats *net_stats = &adapter->netdev->stats;\n#else\n\tstruct net_device_stats *net_stats = &adapter->net_stats;\n#endif /* HAVE_NETDEV_STATS_IN_NETDEV */\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct ixgbe_hw_stats *hwstats = &adapter->stats;\n\tu64 total_mpc = 0;\n\tu32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;\n\tu64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;\n\tu64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;\n\tu64 bytes = 0, packets = 0, hw_csum_rx_error = 0;\n#ifndef IXGBE_NO_LRO\n\tu32 flushed = 0, coal = 0;\n\tint num_q_vectors = 1;\n#endif\n#ifdef IXGBE_FCOE\n\tstruct ixgbe_fcoe *fcoe = &adapter->fcoe;\n\tunsigned int cpu;\n\tu64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;\n#endif /* IXGBE_FCOE */\n\n\tprintk(KERN_DEBUG \"ixgbe_update_stats, tx_queues=%d, rx_queues=%d\\n\",\n\t\t\tadapter->num_tx_queues, adapter->num_rx_queues);\n\n\tif (test_bit(__IXGBE_DOWN, &adapter->state) ||\n\t test_bit(__IXGBE_RESETTING, &adapter->state))\n\t\treturn;\n\n#ifndef IXGBE_NO_LRO\n\tif (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)\n\t\tnum_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;\n\n#endif\n\tif (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {\n\t\tu64 rsc_count = 0;\n\t\tu64 rsc_flush = 0;\n\t\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\t\trsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;\n\t\t\trsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;\n\t\t}\n\t\tadapter->rsc_total_count = rsc_count;\n\t\tadapter->rsc_total_flush = rsc_flush;\n\t}\n\n#ifndef IXGBE_NO_LRO\n\tfor (i = 0; i < num_q_vectors; i++) {\n\t\tstruct ixgbe_q_vector *q_vector = adapter->q_vector[i];\n\t\tif (!q_vector)\n\t\t\tcontinue;\n\t\tflushed += q_vector->lrolist.stats.flushed;\n\t\tcoal += q_vector->lrolist.stats.coal;\n\t}\n\tadapter->lro_stats.flushed = flushed;\n\tadapter->lro_stats.coal = coal;\n\n#endif\n\tfor (i = 0; i < adapter->num_rx_queues; i++) {\n\t\tstruct ixgbe_ring *rx_ring = adapter->rx_ring[i];\n\t\tnon_eop_descs += rx_ring->rx_stats.non_eop_descs;\n\t\talloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;\n\t\talloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;\n\t\thw_csum_rx_error += rx_ring->rx_stats.csum_err;\n\t\tbytes += rx_ring->stats.bytes;\n\t\tpackets += rx_ring->stats.packets;\n\n\t}\n\tadapter->non_eop_descs = non_eop_descs;\n\tadapter->alloc_rx_page_failed = alloc_rx_page_failed;\n\tadapter->alloc_rx_buff_failed = alloc_rx_buff_failed;\n\tadapter->hw_csum_rx_error = hw_csum_rx_error;\n\tnet_stats->rx_bytes = bytes;\n\tnet_stats->rx_packets = packets;\n\n\tbytes = 0;\n\tpackets = 0;\n\t/* gather some stats to the adapter struct that are per queue */\n\tfor (i = 0; i < adapter->num_tx_queues; i++) {\n\t\tstruct ixgbe_ring *tx_ring = adapter->tx_ring[i];\n\t\trestart_queue += tx_ring->tx_stats.restart_queue;\n\t\ttx_busy += tx_ring->tx_stats.tx_busy;\n\t\tbytes += tx_ring->stats.bytes;\n\t\tpackets += tx_ring->stats.packets;\n\t}\n\tadapter->restart_queue = restart_queue;\n\tadapter->tx_busy = tx_busy;\n\tnet_stats->tx_bytes = bytes;\n\tnet_stats->tx_packets = packets;\n\n\thwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);\n\n\t/* 8 register reads */\n\tfor (i = 0; i < 8; i++) {\n\t\t/* for packet buffers not used, the register should read 0 */\n\t\tmpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));\n\t\tmissed_rx += mpc;\n\t\thwstats->mpc[i] += mpc;\n\t\ttotal_mpc += hwstats->mpc[i];\n\t\thwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));\n\t\thwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));\n\t\tswitch (hw->mac.type) {\n\t\tcase ixgbe_mac_82598EB:\n\t\t\thwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));\n\t\t\thwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));\n\t\t\thwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));\n\t\t\thwstats->pxonrxc[i] +=\n\t\t\t\tIXGBE_READ_REG(hw, IXGBE_PXONRXC(i));\n\t\t\tbreak;\n\t\tcase ixgbe_mac_82599EB:\n\t\tcase ixgbe_mac_X540:\n\t\t\thwstats->pxonrxc[i] +=\n\t\t\t\tIXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/*16 register reads */\n\tfor (i = 0; i < 16; i++) {\n\t\thwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));\n\t\thwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));\n\t\tif ((hw->mac.type == ixgbe_mac_82599EB) ||\n\t\t (hw->mac.type == ixgbe_mac_X540)) {\n\t\t\thwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */\n\t\t\thwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));\n\t\t\tIXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */\n\t\t}\n\t}\n\n\thwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);\n\t/* work around hardware counting issue */\n\thwstats->gprc -= missed_rx;\n\n\tixgbe_update_xoff_received(adapter);\n\n\t/* 82598 hardware only has a 32 bit counter in the high register */\n\tswitch (hw->mac.type) {\n\tcase ixgbe_mac_82598EB:\n\t\thwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);\n\t\thwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);\n\t\thwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);\n\t\thwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);\n\t\tbreak;\n\tcase ixgbe_mac_X540:\n\t\t/* OS2BMC stats are X540 only*/\n\t\thwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);\n\t\thwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);\n\t\thwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);\n\t\thwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);\n\tcase ixgbe_mac_82599EB:\n\t\tfor (i = 0; i < 16; i++)\n\t\t\tadapter->hw_rx_no_dma_resources +=\n\t\t\t\t\t IXGBE_READ_REG(hw, IXGBE_QPRDC(i));\n\t\thwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);\n\t\tIXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */\n\t\thwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);\n\t\tIXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */\n\t\thwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);\n\t\tIXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */\n\t\thwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);\n#ifdef HAVE_TX_MQ\n\t\thwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);\n\t\thwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);\n#endif /* HAVE_TX_MQ */\n#ifdef IXGBE_FCOE\n\t\thwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);\n\t\thwstats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);\n\t\thwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);\n\t\thwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);\n\t\thwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);\n\t\thwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);\n\t\thwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);\n\t\t/* Add up per cpu counters for total ddp aloc fail */\n\t\tif (fcoe && fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {\n\t\t\tfor_each_possible_cpu(cpu) {\n\t\t\t\tfcoe_noddp_counts_sum +=\n\t\t\t\t\t*per_cpu_ptr(fcoe->pcpu_noddp, cpu);\n\t\t\t\tfcoe_noddp_ext_buff_counts_sum +=\n\t\t\t\t\t*per_cpu_ptr(fcoe->\n\t\t\t\t\t\tpcpu_noddp_ext_buff, cpu);\n\t\t\t}\n\t\t}\n\t\thwstats->fcoe_noddp = fcoe_noddp_counts_sum;\n\t\thwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;\n\n#endif /* IXGBE_FCOE */\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\tbprc = IXGBE_READ_REG(hw, IXGBE_BPRC);\n\thwstats->bprc += bprc;\n\thwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);\n\tif (hw->mac.type == ixgbe_mac_82598EB)\n\t\thwstats->mprc -= bprc;\n\thwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);\n\thwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);\n\thwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);\n\thwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);\n\thwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);\n\thwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);\n\thwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);\n\thwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);\n\tlxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);\n\thwstats->lxontxc += lxon;\n\tlxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);\n\thwstats->lxofftxc += lxoff;\n\thwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);\n\thwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);\n\t/*\n\t * 82598 errata - tx of flow control packets is included in tx counters\n\t */\n\txon_off_tot = lxon + lxoff;\n\thwstats->gptc -= xon_off_tot;\n\thwstats->mptc -= xon_off_tot;\n\thwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));\n\thwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);\n\thwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);\n\thwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);\n\thwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);\n\thwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);\n\thwstats->ptc64 -= xon_off_tot;\n\thwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);\n\thwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);\n\thwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);\n\thwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);\n\thwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);\n\thwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);\n\t/* Fill out the OS statistics structure */\n\tnet_stats->multicast = hwstats->mprc;\n\n\t/* Rx Errors */\n\tnet_stats->rx_errors = hwstats->crcerrs +\n\t\t\t\t hwstats->rlec;\n\tnet_stats->rx_dropped = 0;\n\tnet_stats->rx_length_errors = hwstats->rlec;\n\tnet_stats->rx_crc_errors = hwstats->crcerrs;\n\tnet_stats->rx_missed_errors = total_mpc;\n\n\t/*\n\t * VF Stats Collection - skip while resetting because these\n\t * are not clear on read and otherwise you'll sometimes get\n\t * crazy values.\n\t */\n\tif (!test_bit(__IXGBE_RESETTING, &adapter->state)) {\n\t\tfor (i = 0; i < adapter->num_vfs; i++) {\n\t\t\tUPDATE_VF_COUNTER_32bit(IXGBE_PVFGPRC(i),\t \\\n\t\t\t\t\tadapter->vfinfo[i].last_vfstats.gprc, \\\n\t\t\t\t\tadapter->vfinfo[i].vfstats.gprc);\n\t\t\tUPDATE_VF_COUNTER_32bit(IXGBE_PVFGPTC(i),\t \\\n\t\t\t\t\tadapter->vfinfo[i].last_vfstats.gptc, \\\n\t\t\t\t\tadapter->vfinfo[i].vfstats.gptc);\n\t\t\tUPDATE_VF_COUNTER_36bit(IXGBE_PVFGORC_LSB(i),\t \\\n\t\t\t\t\tIXGBE_PVFGORC_MSB(i),\t\t \\\n\t\t\t\t\tadapter->vfinfo[i].last_vfstats.gorc, \\\n\t\t\t\t\tadapter->vfinfo[i].vfstats.gorc);\n\t\t\tUPDATE_VF_COUNTER_36bit(IXGBE_PVFGOTC_LSB(i),\t \\\n\t\t\t\t\tIXGBE_PVFGOTC_MSB(i),\t\t \\\n\t\t\t\t\tadapter->vfinfo[i].last_vfstats.gotc, \\\n\t\t\t\t\tadapter->vfinfo[i].vfstats.gotc);\n\t\t\tUPDATE_VF_COUNTER_32bit(IXGBE_PVFMPRC(i),\t \\\n\t\t\t\t\tadapter->vfinfo[i].last_vfstats.mprc, \\\n\t\t\t\t\tadapter->vfinfo[i].vfstats.mprc);\n\t\t}\n\t}\n}\n\n\n#ifdef NO_VNIC\n\n/**\n * ixgbe_watchdog_update_link - update the link status\n * @adapter - pointer to the device adapter structure\n * @link_speed - pointer to a u32 to store the link_speed\n **/\nstatic void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)\n{\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tu32 link_speed = adapter->link_speed;\n\tbool link_up = adapter->link_up;\n\tbool pfc_en = adapter->dcb_cfg.pfc_mode_enable;\n\n\tif (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))\n\t\treturn;\n\n\tif (hw->mac.ops.check_link) {\n\t\thw->mac.ops.check_link(hw, &link_speed, &link_up, false);\n\t} else {\n\t\t/* always assume link is up, if no check link function */\n\t\tlink_speed = IXGBE_LINK_SPEED_10GB_FULL;\n\t\tlink_up = true;\n\t}\n\n#ifdef HAVE_DCBNL_IEEE\n\tif (adapter->ixgbe_ieee_pfc)\n\t\tpfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);\n\n#endif\n\tif (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {\n\t\thw->mac.ops.fc_enable(hw);\n\t\t//ixgbe_set_rx_drop_en(adapter);\n\t}\n\n\tif (link_up ||\n\t time_after(jiffies, (adapter->link_check_timeout +\n\t\t\t\t IXGBE_TRY_LINK_TIMEOUT))) {\n\t\tadapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t}\n\n\tadapter->link_up = link_up;\n\tadapter->link_speed = link_speed;\n}\n#endif\n\n\n\n#ifdef NO_VNIC\n\n/**\n * ixgbe_service_task - manages and runs subtasks\n * @work: pointer to work_struct containing our data\n **/\nstatic void ixgbe_service_task(struct work_struct *work)\n{\n\t//struct ixgbe_adapter *adapter = container_of(work,\n\t//\t\t\t\t\t struct ixgbe_adapter,\n\t//\t\t\t\t\t service_task);\n\n\t//ixgbe_reset_subtask(adapter);\n\t//ixgbe_sfp_detection_subtask(adapter);\n\t//ixgbe_sfp_link_config_subtask(adapter);\n\t//ixgbe_check_overtemp_subtask(adapter);\n\t//ixgbe_watchdog_subtask(adapter);\n#ifdef HAVE_TX_MQ\n\t//ixgbe_fdir_reinit_subtask(adapter);\n#endif\n\t//ixgbe_check_hang_subtask(adapter);\n\n\t//ixgbe_service_event_complete(adapter);\n}\n\n\n\n\n#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \\\n\t\t IXGBE_TXD_CMD_RS)\n\n\n/**\n * ixgbe_set_mac - Change the Ethernet Address of the NIC\n * @netdev: network interface device structure\n * @p: pointer to an address structure\n *\n * Returns 0 on success, negative on failure\n **/\nstatic int ixgbe_set_mac(struct net_device *netdev, void *p)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\tstruct ixgbe_hw *hw = &adapter->hw;\n\tstruct sockaddr *addr = p;\n\tint ret;\n\n\tif (!is_valid_ether_addr(addr->sa_data))\n\t\treturn -EADDRNOTAVAIL;\n\n\tixgbe_del_mac_filter(adapter, hw->mac.addr,\n\t\t\t adapter->num_vfs);\n\tmemcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);\n\tmemcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);\n\n\n\t/* set the correct pool for the new PF MAC address in entry 0 */\n\tret = ixgbe_add_mac_filter(adapter, hw->mac.addr,\n\t\t\t\t adapter->num_vfs);\n\treturn (ret > 0 ? 0 : ret);\n}\n\n\n/**\n * ixgbe_ioctl -\n * @netdev:\n * @ifreq:\n * @cmd:\n **/\nstatic int ixgbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)\n{\n\tswitch (cmd) {\n#ifdef ETHTOOL_OPS_COMPAT\n\tcase SIOCETHTOOL:\n\t\treturn ethtool_ioctl(ifr);\n#endif\n\tdefault:\n\t\treturn -EOPNOTSUPP;\n\t}\n}\n#endif /* NO_VNIC */\n\n\nvoid ixgbe_do_reset(struct net_device *netdev)\n{\n\tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n\n\tif (netif_running(netdev))\n\t\tixgbe_reinit_locked(adapter);\n\telse\n\t\tixgbe_reset(adapter);\n}\n\n\n\n\n\n\n/**\n * ixgbe_probe - Device Initialization Routine\n * @pdev: PCI device information struct\n * @ent: entry in ixgbe_pci_tbl\n *\n * Returns 0 on success, negative on failure\n *\n * ixgbe_probe initializes an adapter identified by a pci_dev structure.\n * The OS initialization, configuring of the adapter private structure,\n * and a hardware reset occur.\n **/\n//static\nint ixgbe_kni_probe(struct pci_dev *pdev,\n\t\t\t\t struct net_device **lad_dev)\n{\n\tsize_t count;\n\tstruct net_device *netdev;\n\tstruct ixgbe_adapter *adapter = NULL;\n\tstruct ixgbe_hw *hw = NULL;\n\tstatic int cards_found;\n\tint i, err;\n\tu16 offset;\n\tu16 eeprom_verh, eeprom_verl, eeprom_cfg_blkh, eeprom_cfg_blkl;\n\tu32 etrack_id;\n\tu16 build, major, patch;\n\tchar *info_string, *i_s_var;\n\tu8 part_str[IXGBE_PBANUM_LENGTH];\n\tenum ixgbe_mac_type mac_type = ixgbe_mac_unknown;\n#ifdef HAVE_TX_MQ\n\tunsigned int indices = num_possible_cpus();\n#endif /* HAVE_TX_MQ */\n#ifdef IXGBE_FCOE\n\tu16 device_caps;\n#endif\n\tu16 wol_cap;\n\n\terr = pci_enable_device_mem(pdev);\n\tif (err)\n\t\treturn err;\n\n\n#ifdef NO_VNIC\n\terr = pci_request_selected_regions(pdev, pci_select_bars(pdev,\n\t\t\t\t\t IORESOURCE_MEM), ixgbe_driver_name);\n\tif (err) {\n\t\tdev_err(pci_dev_to_dev(pdev),\n\t\t\t\"pci_request_selected_regions failed 0x%x\\n\", err);\n\t\tgoto err_pci_reg;\n\t}\n#endif\n\n\t/*\n\t * The mac_type is needed before we have the adapter is set up\n\t * so rather than maintain two devID -> MAC tables we dummy up\n\t * an ixgbe_hw stuct and use ixgbe_set_mac_type.\n\t */\n\thw = vmalloc(sizeof(struct ixgbe_hw));\n\tif (!hw) {\n\t\tpr_info(\"Unable to allocate memory for early mac \"\n\t\t\t\"check\\n\");\n\t} else {\n\t\thw->vendor_id = pdev->vendor;\n\t\thw->device_id = pdev->device;\n\t\tixgbe_set_mac_type(hw);\n\t\tmac_type = hw->mac.type;\n\t\tvfree(hw);\n\t}\n\n#ifdef NO_VNIC\n\t/*\n\t * Workaround of Silicon errata on 82598. Disable LOs in the PCI switch\n\t * port to which the 82598 is connected to prevent duplicate\n\t * completions caused by LOs. We need the mac type so that we only\n\t * do this on 82598 devices, ixgbe_set_mac_type does this for us if\n\t * we set it's device ID.\n\t */\n\tif (mac_type == ixgbe_mac_82598EB)\n\t\tpci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);\n\n\tpci_enable_pcie_error_reporting(pdev);\n\n\tpci_set_master(pdev);\n#endif\n\n#ifdef HAVE_TX_MQ\n#ifdef CONFIG_DCB\n#ifdef HAVE_MQPRIO\n\tindices *= IXGBE_DCB_MAX_TRAFFIC_CLASS;\n#else\n\tindices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);\n#endif /* HAVE_MQPRIO */\n#endif /* CONFIG_DCB */\n\n\tif (mac_type == ixgbe_mac_82598EB)\n\t\tindices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);\n\telse\n\t\tindices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);\n\n#ifdef IXGBE_FCOE\n\tindices += min_t(unsigned int, num_possible_cpus(),\n\t\t\t IXGBE_MAX_FCOE_INDICES);\n#endif\n\tnetdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);\n#else /* HAVE_TX_MQ */\n\tnetdev = alloc_etherdev(sizeof(struct ixgbe_adapter));\n#endif /* HAVE_TX_MQ */\n\tif (!netdev) {\n\t\terr = -ENOMEM;\n\t\tgoto err_alloc_etherdev;\n\t}\n\n\tSET_NETDEV_DEV(netdev, &pdev->dev);\n\n\tadapter = netdev_priv(netdev);\n\t//pci_set_drvdata(pdev, adapter);\n\n\tadapter->netdev = netdev;\n\tadapter->pdev = pdev;\n\thw = &adapter->hw;\n\thw->back = adapter;\n\tadapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;\n\n#ifdef HAVE_PCI_ERS\n\t/*\n\t * call save state here in standalone driver because it relies on\n\t * adapter struct to exist, and needs to call netdev_priv\n\t */\n\tpci_save_state(pdev);\n\n#endif\n\thw->hw_addr = ioremap(pci_resource_start(pdev, 0),\n\t\t\t pci_resource_len(pdev, 0));\n\tif (!hw->hw_addr) {\n\t\terr = -EIO;\n\t\tgoto err_ioremap;\n\t}\n\t//ixgbe_assign_netdev_ops(netdev);\n\tixgbe_set_ethtool_ops(netdev);\n\n\tstrlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));\n\n\tadapter->bd_number = cards_found;\n\n\t/* setup the private structure */\n\terr = ixgbe_sw_init(adapter);\n\tif (err)\n\t\tgoto err_sw_init;\n\n\t/* Make it possible the adapter to be woken up via WOL */\n\tswitch (adapter->hw.mac.type) {\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\t\tIXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\t/*\n\t * check_options must be called before setup_link to set up\n\t * hw->fc completely\n\t */\n\t//ixgbe_check_options(adapter);\n\n#ifndef NO_VNIC\n\t/* reset_hw fills in the perm_addr as well */\n\thw->phy.reset_if_overtemp = true;\n\terr = hw->mac.ops.reset_hw(hw);\n\thw->phy.reset_if_overtemp = false;\n\tif (err == IXGBE_ERR_SFP_NOT_PRESENT &&\n\t hw->mac.type == ixgbe_mac_82598EB) {\n\t\terr = 0;\n\t} else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {\n\t\te_dev_err(\"failed to load because an unsupported SFP+ \"\n\t\t\t \"module type was detected.\\n\");\n\t\te_dev_err(\"Reload the driver after installing a supported \"\n\t\t\t \"module.\\n\");\n\t\tgoto err_sw_init;\n\t} else if (err) {\n\t\te_dev_err(\"HW Init failed: %d\\n\", err);\n\t\tgoto err_sw_init;\n\t}\n#endif\n\n\t//if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)\n\t//\tixgbe_probe_vf(adapter);\n\n\n#ifdef MAX_SKB_FRAGS\n\tnetdev->features |= NETIF_F_SG |\n\t\t\t NETIF_F_IP_CSUM;\n\n#ifdef NETIF_F_IPV6_CSUM\n\tnetdev->features |= NETIF_F_IPV6_CSUM;\n#endif\n\n#ifdef NETIF_F_HW_VLAN_TX\n\tnetdev->features |= NETIF_F_HW_VLAN_TX |\n\t\t\t NETIF_F_HW_VLAN_RX;\n#endif\n#ifdef NETIF_F_TSO\n\tnetdev->features |= NETIF_F_TSO;\n#endif /* NETIF_F_TSO */\n#ifdef NETIF_F_TSO6\n\tnetdev->features |= NETIF_F_TSO6;\n#endif /* NETIF_F_TSO6 */\n#ifdef NETIF_F_RXHASH\n\tnetdev->features |= NETIF_F_RXHASH;\n#endif /* NETIF_F_RXHASH */\n\n#ifdef HAVE_NDO_SET_FEATURES\n\tnetdev->features |= NETIF_F_RXCSUM;\n\n\t/* copy netdev features into list of user selectable features */\n\tnetdev->hw_features |= netdev->features;\n\n\t/* give us the option of enabling RSC/LRO later */\n#ifdef IXGBE_NO_LRO\n\tif (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)\n#endif\n\t\tnetdev->hw_features |= NETIF_F_LRO;\n\n#else\n#ifdef NETIF_F_GRO\n\n\t/* this is only needed on kernels prior to 2.6.39 */\n\tnetdev->features |= NETIF_F_GRO;\n#endif /* NETIF_F_GRO */\n#endif\n\n#ifdef NETIF_F_HW_VLAN_TX\n\t/* set this bit last since it cannot be part of hw_features */\n\tnetdev->features |= NETIF_F_HW_VLAN_FILTER;\n#endif\n\tswitch (adapter->hw.mac.type) {\n\tcase ixgbe_mac_82599EB:\n\tcase ixgbe_mac_X540:\n\t\tnetdev->features |= NETIF_F_SCTP_CSUM;\n#ifdef HAVE_NDO_SET_FEATURES\n\t\tnetdev->hw_features |= NETIF_F_SCTP_CSUM |\n\t\t\t\t NETIF_F_NTUPLE;\n#endif\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n#ifdef HAVE_NETDEV_VLAN_FEATURES\n\tnetdev->vlan_features |= NETIF_F_SG |\n\t\t\t\t NETIF_F_IP_CSUM |\n\t\t\t\t NETIF_F_IPV6_CSUM |\n\t\t\t\t NETIF_F_TSO |\n\t\t\t\t NETIF_F_TSO6;\n\n#endif /* HAVE_NETDEV_VLAN_FEATURES */\n\t/*\n\t * If perfect filters were enabled in check_options(), enable them\n\t * on the netdevice too.\n\t */\n\tif (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)\n\t\tnetdev->features |= NETIF_F_NTUPLE;\n\tif (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)\n\t\tadapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;\n\tif (adapter->flags & IXGBE_FLAG_DCB_ENABLED)\n\t\tadapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;\n\tif (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {\n\t\tadapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;\n\t\t/* clear n-tuple support in the netdev unconditionally */\n\t\tnetdev->features &= ~NETIF_F_NTUPLE;\n\t}\n\n#ifdef NETIF_F_RXHASH\n\tif (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))\n\t\tnetdev->features &= ~NETIF_F_RXHASH;\n\n#endif /* NETIF_F_RXHASH */\n\tif (netdev->features & NETIF_F_LRO) {\n\t\tif ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&\n\t\t ((adapter->rx_itr_setting == 1) ||\n\t\t (adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR))) {\n\t\t\tadapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;\n\t\t} else if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) {\n#ifdef IXGBE_NO_LRO\n\t\t\te_info(probe, \"InterruptThrottleRate set too high, \"\n\t\t\t \"disabling RSC\\n\");\n#else\n\t\t\te_info(probe, \"InterruptThrottleRate set too high, \"\n\t\t\t \"falling back to software LRO\\n\");\n#endif\n\t\t}\n\t}\n#ifdef CONFIG_DCB\n\t//netdev->dcbnl_ops = &dcbnl_ops;\n#endif\n\n#ifdef IXGBE_FCOE\n#ifdef NETIF_F_FSO\n\tif (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {\n\t\tixgbe_get_device_caps(hw, &device_caps);\n\t\tif (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) {\n\t\t\tadapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;\n\t\t\tadapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;\n\t\t\te_info(probe, \"FCoE offload feature is not available. \"\n\t\t\t \"Disabling FCoE offload feature\\n\");\n\t\t}\n#ifndef HAVE_NETDEV_OPS_FCOE_ENABLE\n\t\telse {\n\t\t\tadapter->flags |= IXGBE_FLAG_FCOE_ENABLED;\n\t\t\tadapter->ring_feature[RING_F_FCOE].indices =\n\t\t\t\tIXGBE_FCRETA_SIZE;\n\t\t\tnetdev->features |= NETIF_F_FSO |\n\t\t\t\t\t NETIF_F_FCOE_CRC |\n\t\t\t\t\t NETIF_F_FCOE_MTU;\n\t\t\tnetdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;\n\t\t}\n#endif /* HAVE_NETDEV_OPS_FCOE_ENABLE */\n#ifdef HAVE_NETDEV_VLAN_FEATURES\n\t\tnetdev->vlan_features |= NETIF_F_FSO |\n\t\t\t\t\t NETIF_F_FCOE_CRC |\n\t\t\t\t\t NETIF_F_FCOE_MTU;\n#endif /* HAVE_NETDEV_VLAN_FEATURES */\n\t}\n#endif /* NETIF_F_FSO */\n#endif /* IXGBE_FCOE */\n\n#endif /* MAX_SKB_FRAGS */\n\t/* make sure the EEPROM is good */\n\tif (hw->eeprom.ops.validate_checksum &&\n\t (hw->eeprom.ops.validate_checksum(hw, NULL) < 0)) {\n\t\te_dev_err(\"The EEPROM Checksum Is Not Valid\\n\");\n\t\terr = -EIO;\n\t\tgoto err_sw_init;\n\t}\n\n\tmemcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);\n#ifdef ETHTOOL_GPERMADDR\n\tmemcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);\n\n\tif (ixgbe_validate_mac_addr(netdev->perm_addr)) {\n\t\te_dev_err(\"invalid MAC address\\n\");\n\t\terr = -EIO;\n\t\tgoto err_sw_init;\n\t}\n#else\n\tif (ixgbe_validate_mac_addr(netdev->dev_addr)) {\n\t\te_dev_err(\"invalid MAC address\\n\");\n\t\terr = -EIO;\n\t\tgoto err_sw_init;\n\t}\n#endif\n\tmemcpy(&adapter->mac_table[0].addr, hw->mac.perm_addr,\n\t netdev->addr_len);\n\tadapter->mac_table[0].queue = adapter->num_vfs;\n\tadapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |\n\t\t\t\t IXGBE_MAC_STATE_IN_USE);\n\thw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,\n\t\t\t adapter->mac_table[0].queue,\n\t\t\t IXGBE_RAH_AV);\n\n\t//setup_timer(&adapter->service_timer, &ixgbe_service_timer,\n\t//\t (unsigned long) adapter);\n\n\t//INIT_WORK(&adapter->service_task, ixgbe_service_task);\n\t//clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);\n\n\t//err = ixgbe_init_interrupt_scheme(adapter);\n\t//if (err)\n\t//\tgoto err_sw_init;\n\n\t//adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;\n\tixgbe_set_num_queues(adapter);\n\n\tadapter->wol = 0;\n\t/* WOL not supported for all but the following */\n\tswitch (pdev->device) {\n\tcase IXGBE_DEV_ID_82599_SFP:\n\t\t/* Only these subdevice supports WOL */\n\t\tswitch (pdev->subsystem_device) {\n\t\tcase IXGBE_SUBDEV_ID_82599_560FLR:\n\t\t\t/* only support first port */\n\t\t\tif (hw->bus.func != 0)\n\t\t\t\tbreak;\n\t\tcase IXGBE_SUBDEV_ID_82599_SFP:\n\t\t\tadapter->wol = IXGBE_WUFC_MAG;\n\t\t\tbreak;\n\t\t}\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_COMBO_BACKPLANE:\n\t\t/* All except this subdevice support WOL */\n\t\tif (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)\n\t\t\tadapter->wol = IXGBE_WUFC_MAG;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_82599_KX4:\n\t\tadapter->wol = IXGBE_WUFC_MAG;\n\t\tbreak;\n\tcase IXGBE_DEV_ID_X540T:\n\t\t/* Check eeprom to see if it is enabled */\n\t\tixgbe_read_eeprom(hw, 0x2c, &adapter->eeprom_cap);\n\t\twol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;\n\n\t\tif ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||\n\t\t ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&\n\t\t (hw->bus.func == 0)))\n\t\t\tadapter->wol = IXGBE_WUFC_MAG;\n\t\tbreak;\n\t}\n\t//device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);\n\n\n\t/*\n\t * Save off EEPROM version number and Option Rom version which\n\t * together make a unique identify for the eeprom\n\t */\n\tixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);\n\tixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);\n\n\tetrack_id = (eeprom_verh << 16) | eeprom_verl;\n\n\tixgbe_read_eeprom(hw, 0x17, &offset);\n\n\t/* Make sure offset to SCSI block is valid */\n\tif (!(offset == 0x0) && !(offset == 0xffff)) {\n\t\tixgbe_read_eeprom(hw, offset + 0x84, &eeprom_cfg_blkh);\n\t\tixgbe_read_eeprom(hw, offset + 0x83, &eeprom_cfg_blkl);\n\n\t\t/* Only display Option Rom if exist */\n\t\tif (eeprom_cfg_blkl && eeprom_cfg_blkh) {\n\t\t\tmajor = eeprom_cfg_blkl >> 8;\n\t\t\tbuild = (eeprom_cfg_blkl << 8) | (eeprom_cfg_blkh >> 8);\n\t\t\tpatch = eeprom_cfg_blkh & 0x00ff;\n\n\t\t\tsnprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),\n\t\t\t\t \"0x%08x, %d.%d.%d\", etrack_id, major, build,\n\t\t\t\t patch);\n\t\t} else {\n\t\t\tsnprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),\n\t\t\t\t \"0x%08x\", etrack_id);\n\t\t}\n\t} else {\n\t\tsnprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),\n\t\t\t \"0x%08x\", etrack_id);\n\t}\n\n\t/* reset the hardware with the new settings */\n\terr = hw->mac.ops.start_hw(hw);\n\tif (err == IXGBE_ERR_EEPROM_VERSION) {\n\t\t/* We are running on a pre-production device, log a warning */\n\t\te_dev_warn(\"This device is a pre-production adapter/LOM. \"\n\t\t\t \"Please be aware there may be issues associated \"\n\t\t\t \"with your hardware. If you are experiencing \"\n\t\t\t \"problems please contact your Intel or hardware \"\n\t\t\t \"representative who provided you with this \"\n\t\t\t \"hardware.\\n\");\n\t}\n\t/* pick up the PCI bus settings for reporting later */\n\tif (hw->mac.ops.get_bus_info)\n\t\thw->mac.ops.get_bus_info(hw);\n\n\tstrlcpy(netdev->name, \"eth%d\", sizeof(netdev->name));\n\t*lad_dev = netdev;\n\n\tadapter->netdev_registered = true;\n#ifdef NO_VNIC\n\t/* power down the optics */\n\tif ((hw->phy.multispeed_fiber) ||\n\t ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&\n\t (hw->mac.type == ixgbe_mac_82599EB)))\n\t\tixgbe_disable_tx_laser(hw);\n\n\t/* carrier off reporting is important to ethtool even BEFORE open */\n\tnetif_carrier_off(netdev);\n\t/* keep stopping all the transmit queues for older kernels */\n\tnetif_tx_stop_all_queues(netdev);\n#endif\n\n\t/* print all messages at the end so that we use our eth%d name */\n\t/* print bus type/speed/width info */\n\te_dev_info(\"(PCI Express:%s:%s) \",\n\t\t (hw->bus.speed == ixgbe_bus_speed_5000 ? \"5.0GT/s\" :\n\t\t hw->bus.speed == ixgbe_bus_speed_2500 ? \"2.5GT/s\" :\n\t\t \"Unknown\"),\n\t\t (hw->bus.width == ixgbe_bus_width_pcie_x8 ? \"Width x8\" :\n\t\t hw->bus.width == ixgbe_bus_width_pcie_x4 ? \"Width x4\" :\n\t\t hw->bus.width == ixgbe_bus_width_pcie_x1 ? \"Width x1\" :\n\t\t \"Unknown\"));\n\n\t/* print the MAC address */\n\tfor (i = 0; i < 6; i++)\n\t\tpr_cont(\"%2.2x%c\", netdev->dev_addr[i], i == 5 ? '\\n' : ':');\n\n\t/* First try to read PBA as a string */\n\terr = ixgbe_read_pba_string(hw, part_str, IXGBE_PBANUM_LENGTH);\n\tif (err)\n\t\tstrlcpy(part_str, \"Unknown\", sizeof(part_str));\n\tif (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)\n\t\te_info(probe, \"MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\\n\",\n\t\t hw->mac.type, hw->phy.type, hw->phy.sfp_type, part_str);\n\telse\n\t\te_info(probe, \"MAC: %d, PHY: %d, PBA No: %s\\n\",\n\t\t hw->mac.type, hw->phy.type, part_str);\n\n\tif (((hw->bus.speed == ixgbe_bus_speed_2500) &&\n\t (hw->bus.width <= ixgbe_bus_width_pcie_x4)) ||\n\t (hw->bus.width <= ixgbe_bus_width_pcie_x2)) {\n\t\te_dev_warn(\"PCI-Express bandwidth available for this \"\n\t\t\t \"card is not sufficient for optimal \"\n\t\t\t \"performance.\\n\");\n\t\te_dev_warn(\"For optimal performance a x8 PCI-Express \"\n\t\t\t \"slot is required.\\n\");\n\t}\n\n#define INFO_STRING_LEN 255\n\tinfo_string = kzalloc(INFO_STRING_LEN, GFP_KERNEL);\n\tif (!info_string) {\n\t\te_err(probe, \"allocation for info string failed\\n\");\n\t\tgoto no_info_string;\n\t}\n\tcount = 0;\n\ti_s_var = info_string;\n\tcount += snprintf(i_s_var, INFO_STRING_LEN, \"Enabled Features: \");\n\n\ti_s_var = info_string + count;\n\tcount += snprintf(i_s_var, (INFO_STRING_LEN - count),\n\t\t\t\"RxQ: %d TxQ: %d \", adapter->num_rx_queues,\n\t\t\t\t\tadapter->num_tx_queues);\n\ti_s_var = info_string + count;\n#ifdef IXGBE_FCOE\n\tif (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {\n\t\tcount += snprintf(i_s_var, INFO_STRING_LEN - count, \"FCoE \");\n\t\ti_s_var = info_string + count;\n\t}\n#endif\n\tif (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {\n\t\tcount += snprintf(i_s_var, INFO_STRING_LEN - count,\n\t\t\t\t\t\t\t\"FdirHash \");\n\t\ti_s_var = info_string + count;\n\t}\n\tif (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {\n\t\tcount += snprintf(i_s_var, INFO_STRING_LEN - count,\n\t\t\t\t\t\t\"FdirPerfect \");\n\t\ti_s_var = info_string + count;\n\t}\n\tif (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {\n\t\tcount += snprintf(i_s_var, INFO_STRING_LEN - count, \"DCB \");\n\t\ti_s_var = info_string + count;\n\t}\n\tif (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {\n\t\tcount += snprintf(i_s_var, INFO_STRING_LEN - count, \"RSS \");\n\t\ti_s_var = info_string + count;\n\t}\n\tif (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {\n\t\tcount += snprintf(i_s_var, INFO_STRING_LEN - count, \"DCA \");\n\t\ti_s_var = info_string + count;\n\t}\n\tif (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {\n\t\tcount += snprintf(i_s_var, INFO_STRING_LEN - count, \"RSC \");\n\t\ti_s_var = info_string + count;\n\t}\n#ifndef IXGBE_NO_LRO\n\telse if (netdev->features & NETIF_F_LRO) {\n\t\tcount += snprintf(i_s_var, INFO_STRING_LEN - count, \"LRO \");\n\t\ti_s_var = info_string + count;\n\t}\n#endif\n\n\tBUG_ON(i_s_var > (info_string + INFO_STRING_LEN));\n\t/* end features printing */\n\te_info(probe, \"%s\\n\", info_string);\n\tkfree(info_string);\nno_info_string:\n\n\t/* firmware requires blank driver version */\n\tixgbe_set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF);\n\n#if defined(HAVE_NETDEV_STORAGE_ADDRESS) && defined(NETDEV_HW_ADDR_T_SAN)\n\t/* add san mac addr to netdev */\n\t//ixgbe_add_sanmac_netdev(netdev);\n\n#endif /* (HAVE_NETDEV_STORAGE_ADDRESS) && (NETDEV_HW_ADDR_T_SAN) */\n\te_info(probe, \"Intel(R) 10 Gigabit Network Connection\\n\");\n\tcards_found++;\n\n#ifdef IXGBE_SYSFS\n\t//if (ixgbe_sysfs_init(adapter))\n\t//\te_err(probe, \"failed to allocate sysfs resources\\n\");\n#else\n#ifdef IXGBE_PROCFS\n\t//if (ixgbe_procfs_init(adapter))\n\t//\te_err(probe, \"failed to allocate procfs resources\\n\");\n#endif /* IXGBE_PROCFS */\n#endif /* IXGBE_SYSFS */\n\n\treturn 0;\n\n//err_register:\n\t//ixgbe_clear_interrupt_scheme(adapter);\n\t//ixgbe_release_hw_control(adapter);\nerr_sw_init:\n\tadapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;\n\tif (adapter->mac_table)\n\t\tkfree(adapter->mac_table);\n\tiounmap(hw->hw_addr);\nerr_ioremap:\n\tfree_netdev(netdev);\nerr_alloc_etherdev:\n\t//pci_release_selected_regions(pdev,\n\t//\t\t\t pci_select_bars(pdev, IORESOURCE_MEM));\n//err_pci_reg:\n//err_dma:\n\tpci_disable_device(pdev);\n\treturn err;\n}\n\n/**\n * ixgbe_remove - Device Removal Routine\n * @pdev: PCI device information struct\n *\n * ixgbe_remove is called by the PCI subsystem to alert the driver\n * that it should release a PCI device. The could be caused by a\n * Hot-Plug event, or because the driver is going to be removed from\n * memory.\n **/\nvoid ixgbe_kni_remove(struct pci_dev *pdev)\n{\n\tpci_disable_device(pdev);\n}\n\n\nu16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)\n{\n\tu16 value;\n\tstruct ixgbe_adapter *adapter = hw->back;\n\n\tpci_read_config_word(adapter->pdev, reg, &value);\n\treturn value;\n}\n\nvoid ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)\n{\n\tstruct ixgbe_adapter *adapter = hw->back;\n\n\tpci_write_config_word(adapter->pdev, reg, value);\n}\n\nvoid ewarn(struct ixgbe_hw *hw, const char *st, u32 status)\n{\n\tstruct ixgbe_adapter *adapter = hw->back;\n\n\tnetif_warn(adapter, drv, adapter->netdev, \"%s\", st);\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_mbx.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _IXGBE_MBX_H_\n#define _IXGBE_MBX_H_\n\n#include \"ixgbe_type.h\"\n\n#define IXGBE_VFMAILBOX_SIZE\t16 /* 16 32 bit words - 64 bytes */\n#define IXGBE_ERR_MBX\t\t-100\n\n#define IXGBE_VFMAILBOX\t\t0x002FC\n#define IXGBE_VFMBMEM\t\t0x00200\n\n/* Define mailbox register bits */\n#define IXGBE_VFMAILBOX_REQ\t0x00000001 /* Request for PF Ready bit */\n#define IXGBE_VFMAILBOX_ACK\t0x00000002 /* Ack PF message received */\n#define IXGBE_VFMAILBOX_VFU\t0x00000004 /* VF owns the mailbox buffer */\n#define IXGBE_VFMAILBOX_PFU\t0x00000008 /* PF owns the mailbox buffer */\n#define IXGBE_VFMAILBOX_PFSTS\t0x00000010 /* PF wrote a message in the MB */\n#define IXGBE_VFMAILBOX_PFACK\t0x00000020 /* PF ack the previous VF msg */\n#define IXGBE_VFMAILBOX_RSTI\t0x00000040 /* PF has reset indication */\n#define IXGBE_VFMAILBOX_RSTD\t0x00000080 /* PF has indicated reset done */\n#define IXGBE_VFMAILBOX_R2C_BITS\t0x000000B0 /* All read to clear bits */\n\n#define IXGBE_PFMAILBOX_STS\t0x00000001 /* Initiate message send to VF */\n#define IXGBE_PFMAILBOX_ACK\t0x00000002 /* Ack message recv'd from VF */\n#define IXGBE_PFMAILBOX_VFU\t0x00000004 /* VF owns the mailbox buffer */\n#define IXGBE_PFMAILBOX_PFU\t0x00000008 /* PF owns the mailbox buffer */\n#define IXGBE_PFMAILBOX_RVFU\t0x00000010 /* Reset VFU - used when VF stuck */\n\n#define IXGBE_MBVFICR_VFREQ_MASK\t0x0000FFFF /* bits for VF messages */\n#define IXGBE_MBVFICR_VFREQ_VF1\t\t0x00000001 /* bit for VF 1 message */\n#define IXGBE_MBVFICR_VFACK_MASK\t0xFFFF0000 /* bits for VF acks */\n#define IXGBE_MBVFICR_VFACK_VF1\t\t0x00010000 /* bit for VF 1 ack */\n\n\n/* If it's a IXGBE_VF_* msg then it originates in the VF and is sent to the\n * PF. The reverse is true if it is IXGBE_PF_*.\n * Message ACK's are the value or'd with 0xF0000000\n */\n#define IXGBE_VT_MSGTYPE_ACK\t0x80000000 /* Messages below or'd with\n\t\t\t\t\t * this are the ACK */\n#define IXGBE_VT_MSGTYPE_NACK\t0x40000000 /* Messages below or'd with\n\t\t\t\t\t * this are the NACK */\n#define IXGBE_VT_MSGTYPE_CTS\t0x20000000 /* Indicates that VF is still\n\t\t\t\t\t * clear to send requests */\n#define IXGBE_VT_MSGINFO_SHIFT\t16\n/* bits 23:16 are used for extra info for certain messages */\n#define IXGBE_VT_MSGINFO_MASK\t(0xFF << IXGBE_VT_MSGINFO_SHIFT)\n\n#define IXGBE_VF_RESET\t\t0x01 /* VF requests reset */\n#define IXGBE_VF_SET_MAC_ADDR\t0x02 /* VF requests PF to set MAC addr */\n#define IXGBE_VF_SET_MULTICAST\t0x03 /* VF requests PF to set MC addr */\n#define IXGBE_VF_SET_VLAN\t0x04 /* VF requests PF to set VLAN */\n#define IXGBE_VF_SET_LPE\t0x05 /* VF requests PF to set VMOLR.LPE */\n#define IXGBE_VF_SET_MACVLAN\t0x06 /* VF requests PF for unicast filter */\n\n/* length of permanent address message returned from PF */\n#define IXGBE_VF_PERMADDR_MSG_LEN\t4\n/* word in permanent address message with the current multicast type */\n#define IXGBE_VF_MC_TYPE_WORD\t\t3\n\n#define IXGBE_PF_CONTROL_MSG\t\t0x0100 /* PF control message */\n\n\n#define IXGBE_VF_MBX_INIT_TIMEOUT\t2000 /* number of retries on mailbox */\n#define IXGBE_VF_MBX_INIT_DELAY\t\t500 /* microseconds between retries */\n\ns32 ixgbe_read_mbx(struct ixgbe_hw *, u32 *, u16, u16);\ns32 ixgbe_write_mbx(struct ixgbe_hw *, u32 *, u16, u16);\ns32 ixgbe_read_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);\ns32 ixgbe_write_posted_mbx(struct ixgbe_hw *, u32 *, u16, u16);\ns32 ixgbe_check_for_msg(struct ixgbe_hw *, u16);\ns32 ixgbe_check_for_ack(struct ixgbe_hw *, u16);\ns32 ixgbe_check_for_rst(struct ixgbe_hw *, u16);\nvoid ixgbe_init_mbx_ops_generic(struct ixgbe_hw *hw);\nvoid ixgbe_init_mbx_params_vf(struct ixgbe_hw *);\nvoid ixgbe_init_mbx_params_pf(struct ixgbe_hw *);\n\n#endif /* _IXGBE_MBX_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n\n/* glue for the OS independent part of ixgbe\n * includes register access macros\n */\n\n#ifndef _IXGBE_OSDEP_H_\n#define _IXGBE_OSDEP_H_\n\n#include \n#include \n#include \n#include \n#include \n#include \"kcompat.h\"\n\n\n#ifndef msleep\n#define msleep(x)\tdo { if (in_interrupt()) { \\\n\t\t\t\t/* Don't mdelay in interrupt context! */ \\\n\t\t\t\tBUG(); \\\n\t\t\t} else { \\\n\t\t\t\tmsleep(x); \\\n\t\t\t} } while (0)\n\n#endif\n\n#undef ASSERT\n\n#ifdef DBG\n#define hw_dbg(hw, S, A...)\tprintk(KERN_DEBUG S, ## A)\n#else\n#define hw_dbg(hw, S, A...)\tdo {} while (0)\n#endif\n\n#define e_dev_info(format, arg...) \\\n\tdev_info(pci_dev_to_dev(adapter->pdev), format, ## arg)\n#define e_dev_warn(format, arg...) \\\n\tdev_warn(pci_dev_to_dev(adapter->pdev), format, ## arg)\n#define e_dev_err(format, arg...) \\\n\tdev_err(pci_dev_to_dev(adapter->pdev), format, ## arg)\n#define e_dev_notice(format, arg...) \\\n\tdev_notice(pci_dev_to_dev(adapter->pdev), format, ## arg)\n#define e_info(msglvl, format, arg...) \\\n\tnetif_info(adapter, msglvl, adapter->netdev, format, ## arg)\n#define e_err(msglvl, format, arg...) \\\n\tnetif_err(adapter, msglvl, adapter->netdev, format, ## arg)\n#define e_warn(msglvl, format, arg...) \\\n\tnetif_warn(adapter, msglvl, adapter->netdev, format, ## arg)\n#define e_crit(msglvl, format, arg...) \\\n\tnetif_crit(adapter, msglvl, adapter->netdev, format, ## arg)\n\n\n#ifdef DBG\n#define IXGBE_WRITE_REG(a, reg, value) do {\\\n\tswitch (reg) { \\\n\tcase IXGBE_EIMS: \\\n\tcase IXGBE_EIMC: \\\n\tcase IXGBE_EIAM: \\\n\tcase IXGBE_EIAC: \\\n\tcase IXGBE_EICR: \\\n\tcase IXGBE_EICS: \\\n\t\tprintk(\"%s: Reg - 0x%05X, value - 0x%08X\\n\", __func__, \\\n\t\t reg, (u32)(value)); \\\n\tdefault: \\\n\t\tbreak; \\\n\t} \\\n\twritel((value), ((a)->hw_addr + (reg))); \\\n} while (0)\n#else\n#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))\n#endif\n\n#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))\n\n#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \\\n\twritel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))\n\n#define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \\\n\treadl((a)->hw_addr + (reg) + ((offset) << 2)))\n\n#ifndef writeq\n#define writeq(val, addr)\tdo { writel((u32) (val), addr); \\\n\t\t\t\t writel((u32) (val >> 32), (addr + 4)); \\\n\t\t\t\t} while (0);\n#endif\n\n#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))\n\n#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)\nstruct ixgbe_hw;\nextern u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg);\nextern void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value);\nextern void ewarn(struct ixgbe_hw *hw, const char *str, u32 status);\n\n#define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg_word\n#define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg_word\n#define IXGBE_EEPROM_GRANT_ATTEMPS 100\n#define IXGBE_HTONL(_i) htonl(_i)\n#define IXGBE_NTOHL(_i) ntohl(_i)\n#define IXGBE_NTOHS(_i) ntohs(_i)\n#define IXGBE_CPU_TO_LE32(_i) cpu_to_le32(_i)\n#define IXGBE_LE32_TO_CPUS(_i) le32_to_cpus(_i)\n#define EWARN(H, W, S) ewarn(H, W, S)\n\n#endif /* _IXGBE_OSDEP_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_phy.c", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"ixgbe_api.h\"\n#include \"ixgbe_common.h\"\n#include \"ixgbe_phy.h\"\n\nstatic void ixgbe_i2c_start(struct ixgbe_hw *hw);\nstatic void ixgbe_i2c_stop(struct ixgbe_hw *hw);\nstatic s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);\nstatic s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);\nstatic s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);\nstatic s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);\nstatic s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);\nstatic void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);\nstatic void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);\nstatic s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);\nstatic bool ixgbe_get_i2c_data(u32 *i2cctl);\n\n/**\n * ixgbe_init_phy_ops_generic - Inits PHY function ptrs\n * @hw: pointer to the hardware structure\n *\n * Initialize the function pointers.\n **/\ns32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\n\t/* PHY */\n\tphy->ops.identify = &ixgbe_identify_phy_generic;\n\tphy->ops.reset = &ixgbe_reset_phy_generic;\n\tphy->ops.read_reg = &ixgbe_read_phy_reg_generic;\n\tphy->ops.write_reg = &ixgbe_write_phy_reg_generic;\n\tphy->ops.setup_link = &ixgbe_setup_phy_link_generic;\n\tphy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;\n\tphy->ops.check_link = NULL;\n\tphy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;\n\tphy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;\n\tphy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;\n\tphy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;\n\tphy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;\n\tphy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;\n\tphy->ops.identify_sfp = &ixgbe_identify_module_generic;\n\tphy->sfp_type = ixgbe_sfp_type_unknown;\n\tphy->ops.check_overtemp = &ixgbe_tn_check_overtemp;\n\treturn 0;\n}\n\n/**\n * ixgbe_identify_phy_generic - Get physical layer module\n * @hw: pointer to hardware structure\n *\n * Determines the physical layer module found on the current adapter.\n **/\ns32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_PHY_ADDR_INVALID;\n\tu32 phy_addr;\n\tu16 ext_ability = 0;\n\n\tif (hw->phy.type == ixgbe_phy_unknown) {\n\t\tfor (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {\n\t\t\tif (ixgbe_validate_phy_addr(hw, phy_addr)) {\n\t\t\t\thw->phy.addr = phy_addr;\n\t\t\t\tixgbe_get_phy_id(hw);\n\t\t\t\thw->phy.type =\n\t\t\t\t\tixgbe_get_phy_type_from_id(hw->phy.id);\n\n\t\t\t\tif (hw->phy.type == ixgbe_phy_unknown) {\n\t\t\t\t\thw->phy.ops.read_reg(hw,\n\t\t\t\t\t\t IXGBE_MDIO_PHY_EXT_ABILITY,\n\t\t\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t\t\t &ext_ability);\n\t\t\t\t\tif (ext_ability &\n\t\t\t\t\t (IXGBE_MDIO_PHY_10GBASET_ABILITY |\n\t\t\t\t\t IXGBE_MDIO_PHY_1000BASET_ABILITY))\n\t\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\t\t ixgbe_phy_cu_unknown;\n\t\t\t\t\telse\n\t\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\t\t ixgbe_phy_generic;\n\t\t\t\t}\n\n\t\t\t\tstatus = 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\t/* clear value if nothing found */\n\t\tif (status != 0)\n\t\t\thw->phy.addr = 0;\n\t} else {\n\t\tstatus = 0;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_validate_phy_addr - Determines phy address is valid\n * @hw: pointer to hardware structure\n *\n **/\nbool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)\n{\n\tu16 phy_id = 0;\n\tbool valid = false;\n\n\thw->phy.addr = phy_addr;\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,\n\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);\n\n\tif (phy_id != 0xFFFF && phy_id != 0x0)\n\t\tvalid = true;\n\n\treturn valid;\n}\n\n/**\n * ixgbe_get_phy_id - Get the phy type\n * @hw: pointer to hardware structure\n *\n **/\ns32 ixgbe_get_phy_id(struct ixgbe_hw *hw)\n{\n\tu32 status;\n\tu16 phy_id_high = 0;\n\tu16 phy_id_low = 0;\n\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,\n\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t &phy_id_high);\n\n\tif (status == 0) {\n\t\thw->phy.id = (u32)(phy_id_high << 16);\n\t\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,\n\t\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t\t &phy_id_low);\n\t\thw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);\n\t\thw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);\n\t}\n\treturn status;\n}\n\n/**\n * ixgbe_get_phy_type_from_id - Get the phy type\n * @hw: pointer to hardware structure\n *\n **/\nenum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)\n{\n\tenum ixgbe_phy_type phy_type;\n\n\tswitch (phy_id) {\n\tcase TN1010_PHY_ID:\n\t\tphy_type = ixgbe_phy_tn;\n\t\tbreak;\n\tcase X540_PHY_ID:\n\t\tphy_type = ixgbe_phy_aq;\n\t\tbreak;\n\tcase QT2022_PHY_ID:\n\t\tphy_type = ixgbe_phy_qt;\n\t\tbreak;\n\tcase ATH_PHY_ID:\n\t\tphy_type = ixgbe_phy_nl;\n\t\tbreak;\n\tdefault:\n\t\tphy_type = ixgbe_phy_unknown;\n\t\tbreak;\n\t}\n\n\thw_dbg(hw, \"phy type found is %d\\n\", phy_type);\n\treturn phy_type;\n}\n\n/**\n * ixgbe_reset_phy_generic - Performs a PHY reset\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)\n{\n\tu32 i;\n\tu16 ctrl = 0;\n\ts32 status = 0;\n\n\tif (hw->phy.type == ixgbe_phy_unknown)\n\t\tstatus = ixgbe_identify_phy_generic(hw);\n\n\tif (status != 0 || hw->phy.type == ixgbe_phy_none)\n\t\tgoto out;\n\n\t/* Don't reset PHY if it's shut down due to overtemp. */\n\tif (!hw->phy.reset_if_overtemp &&\n\t (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))\n\t\tgoto out;\n\n\t/*\n\t * Perform soft PHY reset to the PHY_XS.\n\t * This will cause a soft reset to the PHY\n\t */\n\thw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,\n\t\t\t IXGBE_MDIO_PHY_XS_DEV_TYPE,\n\t\t\t IXGBE_MDIO_PHY_XS_RESET);\n\n\t/*\n\t * Poll for reset bit to self-clear indicating reset is complete.\n\t * Some PHYs could take up to 3 seconds to complete and need about\n\t * 1.7 usec delay after the reset is complete.\n\t */\n\tfor (i = 0; i < 30; i++) {\n\t\tmsleep(100);\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,\n\t\t\t\t IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);\n\t\tif (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {\n\t\t\tudelay(2);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (ctrl & IXGBE_MDIO_PHY_XS_RESET) {\n\t\tstatus = IXGBE_ERR_RESET_FAILED;\n\t\thw_dbg(hw, \"PHY reset polling failed to complete.\\n\");\n\t}\n\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit address of PHY register to read\n * @phy_data: Pointer to read data from PHY register\n **/\ns32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t u32 device_type, u16 *phy_data)\n{\n\tu32 command;\n\tu32 i;\n\tu32 data;\n\ts32 status = 0;\n\tu16 gssr;\n\n\tif (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)\n\t\tgssr = IXGBE_GSSR_PHY1_SM;\n\telse\n\t\tgssr = IXGBE_GSSR_PHY0_SM;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\n\tif (status == 0) {\n\t\t/* Setup and write the address cycle command */\n\t\tcommand = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |\n\t\t\t (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |\n\t\t\t (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |\n\t\t\t (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MSCA, command);\n\n\t\t/*\n\t\t * Check every 10 usec to see if the address cycle completed.\n\t\t * The MDI Command bit will clear when the operation is\n\t\t * complete\n\t\t */\n\t\tfor (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {\n\t\t\tudelay(10);\n\n\t\t\tcommand = IXGBE_READ_REG(hw, IXGBE_MSCA);\n\n\t\t\tif ((command & IXGBE_MSCA_MDI_COMMAND) == 0)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tif ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {\n\t\t\thw_dbg(hw, \"PHY address command did not complete.\\n\");\n\t\t\tstatus = IXGBE_ERR_PHY;\n\t\t}\n\n\t\tif (status == 0) {\n\t\t\t/*\n\t\t\t * Address cycle complete, setup and write the read\n\t\t\t * command\n\t\t\t */\n\t\t\tcommand = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |\n\t\t\t\t (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |\n\t\t\t\t (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |\n\t\t\t\t (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));\n\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_MSCA, command);\n\n\t\t\t/*\n\t\t\t * Check every 10 usec to see if the address cycle\n\t\t\t * completed. The MDI Command bit will clear when the\n\t\t\t * operation is complete\n\t\t\t */\n\t\t\tfor (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {\n\t\t\t\tudelay(10);\n\n\t\t\t\tcommand = IXGBE_READ_REG(hw, IXGBE_MSCA);\n\n\t\t\t\tif ((command & IXGBE_MSCA_MDI_COMMAND) == 0)\n\t\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {\n\t\t\t\thw_dbg(hw, \"PHY read command didn't complete\\n\");\n\t\t\t\tstatus = IXGBE_ERR_PHY;\n\t\t\t} else {\n\t\t\t\t/*\n\t\t\t\t * Read operation is complete. Get the data\n\t\t\t\t * from MSRWD\n\t\t\t\t */\n\t\t\t\tdata = IXGBE_READ_REG(hw, IXGBE_MSRWD);\n\t\t\t\tdata >>= IXGBE_MSRWD_READ_DATA_SHIFT;\n\t\t\t\t*phy_data = (u16)(data);\n\t\t\t}\n\t\t}\n\n\t\thw->mac.ops.release_swfw_sync(hw, gssr);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register\n * @hw: pointer to hardware structure\n * @reg_addr: 32 bit PHY register to write\n * @device_type: 5 bit device type\n * @phy_data: Data to write to the PHY register\n **/\ns32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t\tu32 device_type, u16 phy_data)\n{\n\tu32 command;\n\tu32 i;\n\ts32 status = 0;\n\tu16 gssr;\n\n\tif (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)\n\t\tgssr = IXGBE_GSSR_PHY1_SM;\n\telse\n\t\tgssr = IXGBE_GSSR_PHY0_SM;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\n\tif (status == 0) {\n\t\t/* Put the data in the MDI single read and write data register*/\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);\n\n\t\t/* Setup and write the address cycle command */\n\t\tcommand = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |\n\t\t\t (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |\n\t\t\t (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |\n\t\t\t (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MSCA, command);\n\n\t\t/*\n\t\t * Check every 10 usec to see if the address cycle completed.\n\t\t * The MDI Command bit will clear when the operation is\n\t\t * complete\n\t\t */\n\t\tfor (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {\n\t\t\tudelay(10);\n\n\t\t\tcommand = IXGBE_READ_REG(hw, IXGBE_MSCA);\n\n\t\t\tif ((command & IXGBE_MSCA_MDI_COMMAND) == 0)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tif ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {\n\t\t\thw_dbg(hw, \"PHY address cmd didn't complete\\n\");\n\t\t\tstatus = IXGBE_ERR_PHY;\n\t\t}\n\n\t\tif (status == 0) {\n\t\t\t/*\n\t\t\t * Address cycle complete, setup and write the write\n\t\t\t * command\n\t\t\t */\n\t\t\tcommand = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |\n\t\t\t\t (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |\n\t\t\t\t (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |\n\t\t\t\t (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));\n\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_MSCA, command);\n\n\t\t\t/*\n\t\t\t * Check every 10 usec to see if the address cycle\n\t\t\t * completed. The MDI Command bit will clear when the\n\t\t\t * operation is complete\n\t\t\t */\n\t\t\tfor (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {\n\t\t\t\tudelay(10);\n\n\t\t\t\tcommand = IXGBE_READ_REG(hw, IXGBE_MSCA);\n\n\t\t\t\tif ((command & IXGBE_MSCA_MDI_COMMAND) == 0)\n\t\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tif ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {\n\t\t\t\thw_dbg(hw, \"PHY address cmd didn't complete\\n\");\n\t\t\t\tstatus = IXGBE_ERR_PHY;\n\t\t\t}\n\t\t}\n\n\t\thw->mac.ops.release_swfw_sync(hw, gssr);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_setup_phy_link_generic - Set and restart autoneg\n * @hw: pointer to hardware structure\n *\n * Restart autonegotiation and PHY and waits for completion.\n **/\ns32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\tu32 time_out;\n\tu32 max_time_out = 10;\n\tu16 autoneg_reg = IXGBE_MII_AUTONEG_REG;\n\tbool autoneg = false;\n\tixgbe_link_speed speed;\n\n\tixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);\n\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL) {\n\t\t/* Set or unset auto-negotiation 10G advertisement */\n\t\thw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;\n\t\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)\n\t\t\tautoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;\n\n\t\thw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t autoneg_reg);\n\t}\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL) {\n\t\t/* Set or unset auto-negotiation 1G advertisement */\n\t\thw->phy.ops.read_reg(hw,\n\t\t\t\t IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;\n\t\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)\n\t\t\tautoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;\n\n\t\thw->phy.ops.write_reg(hw,\n\t\t\t\t IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t autoneg_reg);\n\t}\n\n\tif (speed & IXGBE_LINK_SPEED_100_FULL) {\n\t\t/* Set or unset auto-negotiation 100M advertisement */\n\t\thw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |\n\t\t\t\t IXGBE_MII_100BASE_T_ADVERTISE_HALF);\n\t\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)\n\t\t\tautoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;\n\n\t\thw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t autoneg_reg);\n\t}\n\n\t/* Restart PHY autonegotiation and wait for completion */\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);\n\n\tautoneg_reg |= IXGBE_MII_RESTART;\n\n\thw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);\n\n\t/* Wait for autonegotiation to finish */\n\tfor (time_out = 0; time_out < max_time_out; time_out++) {\n\t\tudelay(10);\n\t\t/* Restart PHY autonegotiation and wait for completion */\n\t\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,\n\t\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;\n\t\tif (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)\n\t\t\tbreak;\n\t}\n\n\tif (time_out == max_time_out) {\n\t\tstatus = IXGBE_ERR_LINK_SETUP;\n\t\thw_dbg(hw, \"ixgbe_setup_phy_link_generic: time out\");\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg: true if autonegotiation enabled\n **/\ns32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg,\n\t\t\t\t bool autoneg_wait_to_complete)\n{\n\n\t/*\n\t * Clear autoneg_advertised and set new values based on input link\n\t * speed.\n\t */\n\thw->phy.autoneg_advertised = 0;\n\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;\n\n\tif (speed & IXGBE_LINK_SPEED_100_FULL)\n\t\thw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;\n\n\t/* Setup link based on the new speed settings */\n\thw->phy.ops.setup_link(hw);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @autoneg: boolean auto-negotiation value\n *\n * Determines the link capabilities by reading the AUTOC register.\n **/\ns32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t\t bool *autoneg)\n{\n\ts32 status = IXGBE_ERR_LINK_SETUP;\n\tu16 speed_ability;\n\n\t*speed = 0;\n\t*autoneg = true;\n\n\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,\n\t\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE,\n\t\t\t\t &speed_ability);\n\n\tif (status == 0) {\n\t\tif (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)\n\t\t\t*speed |= IXGBE_LINK_SPEED_10GB_FULL;\n\t\tif (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)\n\t\t\t*speed |= IXGBE_LINK_SPEED_1GB_FULL;\n\t\tif (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)\n\t\t\t*speed |= IXGBE_LINK_SPEED_100_FULL;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_check_phy_link_tnx - Determine link and speed status\n * @hw: pointer to hardware structure\n *\n * Reads the VS1 register to determine if link is up and the current speed for\n * the PHY.\n **/\ns32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n\t\t\t bool *link_up)\n{\n\ts32 status = 0;\n\tu32 time_out;\n\tu32 max_time_out = 10;\n\tu16 phy_link = 0;\n\tu16 phy_speed = 0;\n\tu16 phy_data = 0;\n\n\t/* Initialize speed and link to default case */\n\t*link_up = false;\n\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n\n\t/*\n\t * Check current speed and link status of the PHY register.\n\t * This is a vendor specific register and may have to\n\t * be changed for other copper PHYs.\n\t */\n\tfor (time_out = 0; time_out < max_time_out; time_out++) {\n\t\tudelay(10);\n\t\tstatus = hw->phy.ops.read_reg(hw,\n\t\t\t\t\tIXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,\n\t\t\t\t\tIXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t\t&phy_data);\n\t\tphy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;\n\t\tphy_speed = phy_data &\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;\n\t\tif (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {\n\t\t\t*link_up = true;\n\t\t\tif (phy_speed ==\n\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)\n\t\t\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn status;\n}\n\n/**\n *\tixgbe_setup_phy_link_tnx - Set and restart autoneg\n *\t@hw: pointer to hardware structure\n *\n *\tRestart autonegotiation and PHY and waits for completion.\n **/\ns32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\tu32 time_out;\n\tu32 max_time_out = 10;\n\tu16 autoneg_reg = IXGBE_MII_AUTONEG_REG;\n\tbool autoneg = false;\n\tixgbe_link_speed speed;\n\n\tixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);\n\n\tif (speed & IXGBE_LINK_SPEED_10GB_FULL) {\n\t\t/* Set or unset auto-negotiation 10G advertisement */\n\t\thw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;\n\t\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)\n\t\t\tautoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;\n\n\t\thw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t autoneg_reg);\n\t}\n\n\tif (speed & IXGBE_LINK_SPEED_1GB_FULL) {\n\t\t/* Set or unset auto-negotiation 1G advertisement */\n\t\thw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;\n\t\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)\n\t\t\tautoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;\n\n\t\thw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t autoneg_reg);\n\t}\n\n\tif (speed & IXGBE_LINK_SPEED_100_FULL) {\n\t\t/* Set or unset auto-negotiation 100M advertisement */\n\t\thw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;\n\t\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)\n\t\t\tautoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;\n\n\t\thw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,\n\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t autoneg_reg);\n\t}\n\n\t/* Restart PHY autonegotiation and wait for completion */\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);\n\n\tautoneg_reg |= IXGBE_MII_RESTART;\n\n\thw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,\n\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);\n\n\t/* Wait for autonegotiation to finish */\n\tfor (time_out = 0; time_out < max_time_out; time_out++) {\n\t\tudelay(10);\n\t\t/* Restart PHY autonegotiation and wait for completion */\n\t\tstatus = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,\n\t\t\t\t\t IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n\t\t\t\t\t &autoneg_reg);\n\n\t\tautoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;\n\t\tif (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)\n\t\t\tbreak;\n\t}\n\n\tif (time_out == max_time_out) {\n\t\tstatus = IXGBE_ERR_LINK_SETUP;\n\t\thw_dbg(hw, \"ixgbe_setup_phy_link_tnx: time out\");\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version\n * @hw: pointer to hardware structure\n * @firmware_version: pointer to the PHY Firmware Version\n **/\ns32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,\n\t\t\t\t u16 *firmware_version)\n{\n\ts32 status = 0;\n\n\tstatus = hw->phy.ops.read_reg(hw, TNX_FW_REV,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t firmware_version);\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version\n * @hw: pointer to hardware structure\n * @firmware_version: pointer to the PHY Firmware Version\n **/\ns32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *firmware_version)\n{\n\ts32 status = 0;\n\n\tstatus = hw->phy.ops.read_reg(hw, AQ_FW_REV,\n\t\t\t\t IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,\n\t\t\t\t firmware_version);\n\n\treturn status;\n}\n\n/**\n * ixgbe_reset_phy_nl - Performs a PHY reset\n * @hw: pointer to hardware structure\n **/\ns32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)\n{\n\tu16 phy_offset, control, eword, edata, block_crc;\n\tbool end_data = false;\n\tu16 list_offset, data_offset;\n\tu16 phy_data = 0;\n\ts32 ret_val = 0;\n\tu32 i;\n\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,\n\t\t\t IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);\n\n\t/* reset the PHY and poll for completion */\n\thw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,\n\t\t\t IXGBE_MDIO_PHY_XS_DEV_TYPE,\n\t\t\t (phy_data | IXGBE_MDIO_PHY_XS_RESET));\n\n\tfor (i = 0; i < 100; i++) {\n\t\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,\n\t\t\t\t IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);\n\t\tif ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)\n\t\t\tbreak;\n\t\tmsleep(10);\n\t}\n\n\tif ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {\n\t\thw_dbg(hw, \"PHY reset did not complete.\\n\");\n\t\tret_val = IXGBE_ERR_PHY;\n\t\tgoto out;\n\t}\n\n\t/* Get init offsets */\n\tret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,\n\t\t\t\t\t\t &data_offset);\n\tif (ret_val != 0)\n\t\tgoto out;\n\n\tret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);\n\tdata_offset++;\n\twhile (!end_data) {\n\t\t/*\n\t\t * Read control word from PHY init contents offset\n\t\t */\n\t\tret_val = hw->eeprom.ops.read(hw, data_offset, &eword);\n\t\tcontrol = (eword & IXGBE_CONTROL_MASK_NL) >>\n\t\t\t IXGBE_CONTROL_SHIFT_NL;\n\t\tedata = eword & IXGBE_DATA_MASK_NL;\n\t\tswitch (control) {\n\t\tcase IXGBE_DELAY_NL:\n\t\t\tdata_offset++;\n\t\t\thw_dbg(hw, \"DELAY: %d MS\\n\", edata);\n\t\t\tmsleep(edata);\n\t\t\tbreak;\n\t\tcase IXGBE_DATA_NL:\n\t\t\thw_dbg(hw, \"DATA:\\n\");\n\t\t\tdata_offset++;\n\t\t\thw->eeprom.ops.read(hw, data_offset++,\n\t\t\t\t\t &phy_offset);\n\t\t\tfor (i = 0; i < edata; i++) {\n\t\t\t\thw->eeprom.ops.read(hw, data_offset, &eword);\n\t\t\t\thw->phy.ops.write_reg(hw, phy_offset,\n\t\t\t\t\t\t IXGBE_TWINAX_DEV, eword);\n\t\t\t\thw_dbg(hw, \"Wrote %4.4x to %4.4x\\n\", eword,\n\t\t\t\t\t phy_offset);\n\t\t\t\tdata_offset++;\n\t\t\t\tphy_offset++;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase IXGBE_CONTROL_NL:\n\t\t\tdata_offset++;\n\t\t\thw_dbg(hw, \"CONTROL:\\n\");\n\t\t\tif (edata == IXGBE_CONTROL_EOL_NL) {\n\t\t\t\thw_dbg(hw, \"EOL\\n\");\n\t\t\t\tend_data = true;\n\t\t\t} else if (edata == IXGBE_CONTROL_SOL_NL) {\n\t\t\t\thw_dbg(hw, \"SOL\\n\");\n\t\t\t} else {\n\t\t\t\thw_dbg(hw, \"Bad control value\\n\");\n\t\t\t\tret_val = IXGBE_ERR_PHY;\n\t\t\t\tgoto out;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\thw_dbg(hw, \"Bad control type\\n\");\n\t\t\tret_val = IXGBE_ERR_PHY;\n\t\t\tgoto out;\n\t\t}\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_identify_module_generic - Identifies module type\n * @hw: pointer to hardware structure\n *\n * Determines HW type and calls appropriate function.\n **/\ns32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_SFP_NOT_PRESENT;\n\n\tswitch (hw->mac.ops.get_media_type(hw)) {\n\tcase ixgbe_media_type_fiber:\n\t\tstatus = ixgbe_identify_sfp_module_generic(hw);\n\t\tbreak;\n\n\tcase ixgbe_media_type_fiber_qsfp:\n\t\tstatus = ixgbe_identify_qsfp_module_generic(hw);\n\t\tbreak;\n\n\tdefault:\n\t\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n\t\tstatus = IXGBE_ERR_SFP_NOT_PRESENT;\n\t\tbreak;\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_identify_sfp_module_generic - Identifies SFP modules\n * @hw: pointer to hardware structure\n *\n * Searches for and identifies the SFP module and assigns appropriate PHY type.\n **/\ns32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_PHY_ADDR_INVALID;\n\tu32 vendor_oui = 0;\n\tenum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;\n\tu8 identifier = 0;\n\tu8 comp_codes_1g = 0;\n\tu8 comp_codes_10g = 0;\n\tu8 oui_bytes[3] = {0, 0, 0};\n\tu8 cable_tech = 0;\n\tu8 cable_spec = 0;\n\tu16 enforce_sfp = 0;\n\n\tif (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {\n\t\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n\t\tstatus = IXGBE_ERR_SFP_NOT_PRESENT;\n\t\tgoto out;\n\t}\n\n\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t IXGBE_SFF_IDENTIFIER,\n\t\t\t\t\t &identifier);\n\n\tif (status == IXGBE_ERR_SWFW_SYNC ||\n\t status == IXGBE_ERR_I2C ||\n\t status == IXGBE_ERR_SFP_NOT_PRESENT)\n\t\tgoto err_read_i2c_eeprom;\n\n\t/* LAN ID is needed for sfp_type determination */\n\thw->mac.ops.set_lan_id(hw);\n\n\tif (identifier != IXGBE_SFF_IDENTIFIER_SFP) {\n\t\thw->phy.type = ixgbe_phy_sfp_unsupported;\n\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t} else {\n\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t\t IXGBE_SFF_1GBE_COMP_CODES,\n\t\t\t\t\t\t &comp_codes_1g);\n\n\t\tif (status == IXGBE_ERR_SWFW_SYNC ||\n\t\t status == IXGBE_ERR_I2C ||\n\t\t status == IXGBE_ERR_SFP_NOT_PRESENT)\n\t\t\tgoto err_read_i2c_eeprom;\n\n\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t\t IXGBE_SFF_10GBE_COMP_CODES,\n\t\t\t\t\t\t &comp_codes_10g);\n\n\t\tif (status == IXGBE_ERR_SWFW_SYNC ||\n\t\t status == IXGBE_ERR_I2C ||\n\t\t status == IXGBE_ERR_SFP_NOT_PRESENT)\n\t\t\tgoto err_read_i2c_eeprom;\n\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t\t IXGBE_SFF_CABLE_TECHNOLOGY,\n\t\t\t\t\t\t &cable_tech);\n\n\t\tif (status == IXGBE_ERR_SWFW_SYNC ||\n\t\t status == IXGBE_ERR_I2C ||\n\t\t status == IXGBE_ERR_SFP_NOT_PRESENT)\n\t\t\tgoto err_read_i2c_eeprom;\n\n\t\t /* ID Module\n\t\t * =========\n\t\t * 0 SFP_DA_CU\n\t\t * 1 SFP_SR\n\t\t * 2 SFP_LR\n\t\t * 3 SFP_DA_CORE0 - 82599-specific\n\t\t * 4 SFP_DA_CORE1 - 82599-specific\n\t\t * 5 SFP_SR/LR_CORE0 - 82599-specific\n\t\t * 6 SFP_SR/LR_CORE1 - 82599-specific\n\t\t * 7 SFP_act_lmt_DA_CORE0 - 82599-specific\n\t\t * 8 SFP_act_lmt_DA_CORE1 - 82599-specific\n\t\t * 9 SFP_1g_cu_CORE0 - 82599-specific\n\t\t * 10 SFP_1g_cu_CORE1 - 82599-specific\n\t\t * 11 SFP_1g_sx_CORE0 - 82599-specific\n\t\t * 12 SFP_1g_sx_CORE1 - 82599-specific\n\t\t */\n\t\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\t\tif (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)\n\t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_da_cu;\n\t\t\telse if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)\n\t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_sr;\n\t\t\telse if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)\n\t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_lr;\n\t\t\telse\n\t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_unknown;\n\t\t} else if (hw->mac.type == ixgbe_mac_82599EB) {\n\t\t\tif (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {\n\t\t\t\tif (hw->bus.lan_id == 0)\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\t ixgbe_sfp_type_da_cu_core0;\n\t\t\t\telse\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\t ixgbe_sfp_type_da_cu_core1;\n\t\t\t} else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {\n\t\t\t\thw->phy.ops.read_i2c_eeprom(\n\t\t\t\t\t\thw, IXGBE_SFF_CABLE_SPEC_COMP,\n\t\t\t\t\t\t&cable_spec);\n\t\t\t\tif (cable_spec &\n\t\t\t\t IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {\n\t\t\t\t\tif (hw->bus.lan_id == 0)\n\t\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_da_act_lmt_core0;\n\t\t\t\t\telse\n\t\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_da_act_lmt_core1;\n\t\t\t\t} else {\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\t\tixgbe_sfp_type_unknown;\n\t\t\t\t}\n\t\t\t} else if (comp_codes_10g &\n\t\t\t\t (IXGBE_SFF_10GBASESR_CAPABLE |\n\t\t\t\t IXGBE_SFF_10GBASELR_CAPABLE)) {\n\t\t\t\tif (hw->bus.lan_id == 0)\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\t ixgbe_sfp_type_srlr_core0;\n\t\t\t\telse\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\t ixgbe_sfp_type_srlr_core1;\n\t\t\t} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {\n\t\t\t\tif (hw->bus.lan_id == 0)\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_1g_cu_core0;\n\t\t\t\telse\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_1g_cu_core1;\n\t\t\t} else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {\n\t\t\t\tif (hw->bus.lan_id == 0)\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_1g_sx_core0;\n\t\t\t\telse\n\t\t\t\t\thw->phy.sfp_type =\n\t\t\t\t\t\tixgbe_sfp_type_1g_sx_core1;\n\t\t\t} else {\n\t\t\t\thw->phy.sfp_type = ixgbe_sfp_type_unknown;\n\t\t\t}\n\t\t}\n\n\t\tif (hw->phy.sfp_type != stored_sfp_type)\n\t\t\thw->phy.sfp_setup_needed = true;\n\n\t\t/* Determine if the SFP+ PHY is dual speed or not. */\n\t\thw->phy.multispeed_fiber = false;\n\t\tif (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&\n\t\t (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||\n\t\t ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&\n\t\t (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))\n\t\t\thw->phy.multispeed_fiber = true;\n\n\t\t/* Determine PHY vendor */\n\t\tif (hw->phy.type != ixgbe_phy_nl) {\n\t\t\thw->phy.id = identifier;\n\t\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t\t IXGBE_SFF_VENDOR_OUI_BYTE0,\n\t\t\t\t\t\t &oui_bytes[0]);\n\n\t\t\tif (status == IXGBE_ERR_SWFW_SYNC ||\n\t\t\t status == IXGBE_ERR_I2C ||\n\t\t\t status == IXGBE_ERR_SFP_NOT_PRESENT)\n\t\t\t\tgoto err_read_i2c_eeprom;\n\n\t\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t\t IXGBE_SFF_VENDOR_OUI_BYTE1,\n\t\t\t\t\t\t &oui_bytes[1]);\n\n\t\t\tif (status == IXGBE_ERR_SWFW_SYNC ||\n\t\t\t status == IXGBE_ERR_I2C ||\n\t\t\t status == IXGBE_ERR_SFP_NOT_PRESENT)\n\t\t\t\tgoto err_read_i2c_eeprom;\n\n\t\t\tstatus = hw->phy.ops.read_i2c_eeprom(hw,\n\t\t\t\t\t\t IXGBE_SFF_VENDOR_OUI_BYTE2,\n\t\t\t\t\t\t &oui_bytes[2]);\n\n\t\t\tif (status == IXGBE_ERR_SWFW_SYNC ||\n\t\t\t status == IXGBE_ERR_I2C ||\n\t\t\t status == IXGBE_ERR_SFP_NOT_PRESENT)\n\t\t\t\tgoto err_read_i2c_eeprom;\n\n\t\t\tvendor_oui =\n\t\t\t ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |\n\t\t\t (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |\n\t\t\t (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));\n\n\t\t\tswitch (vendor_oui) {\n\t\t\tcase IXGBE_SFF_VENDOR_OUI_TYCO:\n\t\t\t\tif (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)\n\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\t ixgbe_phy_sfp_passive_tyco;\n\t\t\t\tbreak;\n\t\t\tcase IXGBE_SFF_VENDOR_OUI_FTL:\n\t\t\t\tif (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)\n\t\t\t\t\thw->phy.type = ixgbe_phy_sfp_ftl_active;\n\t\t\t\telse\n\t\t\t\t\thw->phy.type = ixgbe_phy_sfp_ftl;\n\t\t\t\tbreak;\n\t\t\tcase IXGBE_SFF_VENDOR_OUI_AVAGO:\n\t\t\t\thw->phy.type = ixgbe_phy_sfp_avago;\n\t\t\t\tbreak;\n\t\t\tcase IXGBE_SFF_VENDOR_OUI_INTEL:\n\t\t\t\thw->phy.type = ixgbe_phy_sfp_intel;\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tif (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)\n\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\t ixgbe_phy_sfp_passive_unknown;\n\t\t\t\telse if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)\n\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\tixgbe_phy_sfp_active_unknown;\n\t\t\t\telse\n\t\t\t\t\thw->phy.type = ixgbe_phy_sfp_unknown;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\t/* Allow any DA cable vendor */\n\t\tif (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |\n\t\t IXGBE_SFF_DA_ACTIVE_CABLE)) {\n\t\t\tstatus = 0;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/* Verify supported 1G SFP modules */\n\t\tif (comp_codes_10g == 0 &&\n\t\t !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||\n\t\t hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {\n\t\t\thw->phy.type = ixgbe_phy_sfp_unsupported;\n\t\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\t\tgoto out;\n\t\t}\n\n\t\t/* Anything else 82598-based is supported */\n\t\tif (hw->mac.type == ixgbe_mac_82598EB) {\n\t\t\tstatus = 0;\n\t\t\tgoto out;\n\t\t}\n\n\t\tixgbe_get_device_caps(hw, &enforce_sfp);\n\t\tif (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&\n\t\t !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||\n\t\t (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||\n\t\t (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||\n\t\t (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {\n\t\t\t/* Make sure we're a supported PHY type */\n\t\t\tif (hw->phy.type == ixgbe_phy_sfp_intel) {\n\t\t\t\tstatus = 0;\n\t\t\t} else {\n\t\t\t\tif (hw->allow_unsupported_sfp == true) {\n\t\t\t\t\tEWARN(hw, \"WARNING: Intel (R) Network \"\n\t\t\t\t\t \"Connections are quality tested \"\n\t\t\t\t\t \"using Intel (R) Ethernet Optics.\"\n\t\t\t\t\t \" Using untested modules is not \"\n\t\t\t\t\t \"supported and may cause unstable\"\n\t\t\t\t\t \" operation or damage to the \"\n\t\t\t\t\t \"module or the adapter. Intel \"\n\t\t\t\t\t \"Corporation is not responsible \"\n\t\t\t\t\t \"for any harm caused by using \"\n\t\t\t\t\t \"untested modules.\\n\", status);\n\t\t\t\t\tstatus = 0;\n\t\t\t\t} else {\n\t\t\t\t\thw_dbg(hw, \"SFP+ module not supported\\n\");\n\t\t\t\t\thw->phy.type =\n\t\t\t\t\t\tixgbe_phy_sfp_unsupported;\n\t\t\t\t\tstatus = IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\t\t\t}\n\t\t\t}\n\t\t} else {\n\t\t\tstatus = 0;\n\t\t}\n\t}\n\nout:\n\treturn status;\n\nerr_read_i2c_eeprom:\n\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n\tif (hw->phy.type != ixgbe_phy_nl) {\n\t\thw->phy.id = 0;\n\t\thw->phy.type = ixgbe_phy_unknown;\n\t}\n\treturn IXGBE_ERR_SFP_NOT_PRESENT;\n}\n\n/**\n * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules\n * @hw: pointer to hardware structure\n *\n * Searches for and identifies the QSFP module and assigns appropriate PHY type\n **/\ns32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\n\tif (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {\n\t\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n\t\tstatus = IXGBE_ERR_SFP_NOT_PRESENT;\n\t}\n\n\treturn status;\n}\n\n\n/**\n * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence\n * @hw: pointer to hardware structure\n * @list_offset: offset to the SFP ID list\n * @data_offset: offset to the SFP data block\n *\n * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if\n * so it returns the offsets to the phy init sequence block.\n **/\ns32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,\n\t\t\t\t\tu16 *list_offset,\n\t\t\t\t\tu16 *data_offset)\n{\n\tu16 sfp_id;\n\tu16 sfp_type = hw->phy.sfp_type;\n\n\tif (hw->phy.sfp_type == ixgbe_sfp_type_unknown)\n\t\treturn IXGBE_ERR_SFP_NOT_SUPPORTED;\n\n\tif (hw->phy.sfp_type == ixgbe_sfp_type_not_present)\n\t\treturn IXGBE_ERR_SFP_NOT_PRESENT;\n\n\tif ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&\n\t (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))\n\t\treturn IXGBE_ERR_SFP_NOT_SUPPORTED;\n\n\t/*\n\t * Limiting active cables and 1G Phys must be initialized as\n\t * SR modules\n\t */\n\tif (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||\n\t sfp_type == ixgbe_sfp_type_1g_cu_core0 ||\n\t sfp_type == ixgbe_sfp_type_1g_sx_core0)\n\t\tsfp_type = ixgbe_sfp_type_srlr_core0;\n\telse if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||\n\t\t sfp_type == ixgbe_sfp_type_1g_cu_core1 ||\n\t\t sfp_type == ixgbe_sfp_type_1g_sx_core1)\n\t\tsfp_type = ixgbe_sfp_type_srlr_core1;\n\n\t/* Read offset to PHY init contents */\n\thw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);\n\n\tif ((!*list_offset) || (*list_offset == 0xFFFF))\n\t\treturn IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;\n\n\t/* Shift offset to first ID word */\n\t(*list_offset)++;\n\n\t/*\n\t * Find the matching SFP ID in the EEPROM\n\t * and program the init sequence\n\t */\n\thw->eeprom.ops.read(hw, *list_offset, &sfp_id);\n\n\twhile (sfp_id != IXGBE_PHY_INIT_END_NL) {\n\t\tif (sfp_id == sfp_type) {\n\t\t\t(*list_offset)++;\n\t\t\thw->eeprom.ops.read(hw, *list_offset, data_offset);\n\t\t\tif ((!*data_offset) || (*data_offset == 0xFFFF)) {\n\t\t\t\thw_dbg(hw, \"SFP+ module not supported\\n\");\n\t\t\t\treturn IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t\t\t} else {\n\t\t\t\tbreak;\n\t\t\t}\n\t\t} else {\n\t\t\t(*list_offset) += 2;\n\t\t\tif (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))\n\t\t\t\treturn IXGBE_ERR_PHY;\n\t\t}\n\t}\n\n\tif (sfp_id == IXGBE_PHY_INIT_END_NL) {\n\t\thw_dbg(hw, \"No matching SFP+ module found\\n\");\n\t\treturn IXGBE_ERR_SFP_NOT_SUPPORTED;\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface\n * @hw: pointer to hardware structure\n * @byte_offset: EEPROM byte offset to read\n * @eeprom_data: value read\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 *eeprom_data)\n{\n\treturn hw->phy.ops.read_i2c_byte(hw, byte_offset,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR,\n\t\t\t\t\t eeprom_data);\n}\n\n/**\n * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface\n * @hw: pointer to hardware structure\n * @byte_offset: EEPROM byte offset to write\n * @eeprom_data: value to write\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface.\n **/\ns32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 eeprom_data)\n{\n\treturn hw->phy.ops.write_i2c_byte(hw, byte_offset,\n\t\t\t\t\t IXGBE_I2C_EEPROM_DEV_ADDR,\n\t\t\t\t\t eeprom_data);\n}\n\n/**\n * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to read\n * @data: value read\n *\n * Performs byte read operation to SFP module's EEPROM over I2C interface at\n * a specified device address.\n **/\ns32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\tu8 dev_addr, u8 *data)\n{\n\ts32 status = 0;\n\tu32 max_retry = 10;\n\tu32 retry = 0;\n\tu16 swfw_mask = 0;\n\tbool nack = 1;\n\t*data = 0;\n\n\tif (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)\n\t\tswfw_mask = IXGBE_GSSR_PHY1_SM;\n\telse\n\t\tswfw_mask = IXGBE_GSSR_PHY0_SM;\n\n\tdo {\n\t\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)\n\t\t != 0) {\n\t\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\t\t\tgoto read_byte_out;\n\t\t}\n\n\t\tixgbe_i2c_start(hw);\n\n\t\t/* Device Address and write indication */\n\t\tstatus = ixgbe_clock_out_i2c_byte(hw, dev_addr);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_get_i2c_ack(hw);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_clock_out_i2c_byte(hw, byte_offset);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_get_i2c_ack(hw);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tixgbe_i2c_start(hw);\n\n\t\t/* Device Address and read indication */\n\t\tstatus = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_get_i2c_ack(hw);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_clock_in_i2c_byte(hw, data);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_clock_out_i2c_bit(hw, nack);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tixgbe_i2c_stop(hw);\n\t\tbreak;\n\nfail:\n\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\t\tmsleep(100);\n\t\tixgbe_i2c_bus_clear(hw);\n\t\tretry++;\n\t\tif (retry < max_retry)\n\t\t\thw_dbg(hw, \"I2C byte read error - Retrying.\\n\");\n\t\telse\n\t\t\thw_dbg(hw, \"I2C byte read error.\\n\");\n\n\t} while (retry < max_retry);\n\n\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\nread_byte_out:\n\treturn status;\n}\n\n/**\n * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C\n * @hw: pointer to hardware structure\n * @byte_offset: byte offset to write\n * @data: value to write\n *\n * Performs byte write operation to SFP module's EEPROM over I2C interface at\n * a specified device address.\n **/\ns32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data)\n{\n\ts32 status = 0;\n\tu32 max_retry = 1;\n\tu32 retry = 0;\n\tu16 swfw_mask = 0;\n\n\tif (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)\n\t\tswfw_mask = IXGBE_GSSR_PHY1_SM;\n\telse\n\t\tswfw_mask = IXGBE_GSSR_PHY0_SM;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\t\tgoto write_byte_out;\n\t}\n\n\tdo {\n\t\tixgbe_i2c_start(hw);\n\n\t\tstatus = ixgbe_clock_out_i2c_byte(hw, dev_addr);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_get_i2c_ack(hw);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_clock_out_i2c_byte(hw, byte_offset);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_get_i2c_ack(hw);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_clock_out_i2c_byte(hw, data);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tstatus = ixgbe_get_i2c_ack(hw);\n\t\tif (status != 0)\n\t\t\tgoto fail;\n\n\t\tixgbe_i2c_stop(hw);\n\t\tbreak;\n\nfail:\n\t\tixgbe_i2c_bus_clear(hw);\n\t\tretry++;\n\t\tif (retry < max_retry)\n\t\t\thw_dbg(hw, \"I2C byte write error - Retrying.\\n\");\n\t\telse\n\t\t\thw_dbg(hw, \"I2C byte write error.\\n\");\n\t} while (retry < max_retry);\n\n\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n\nwrite_byte_out:\n\treturn status;\n}\n\n/**\n * ixgbe_i2c_start - Sets I2C start condition\n * @hw: pointer to hardware structure\n *\n * Sets I2C start condition (High -> Low on SDA while SCL is High)\n **/\nstatic void ixgbe_i2c_start(struct ixgbe_hw *hw)\n{\n\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n\n\t/* Start condition must begin with data and clock high */\n\tixgbe_set_i2c_data(hw, &i2cctl, 1);\n\tixgbe_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Setup time for start condition (4.7us) */\n\tudelay(IXGBE_I2C_T_SU_STA);\n\n\tixgbe_set_i2c_data(hw, &i2cctl, 0);\n\n\t/* Hold time for start condition (4us) */\n\tudelay(IXGBE_I2C_T_HD_STA);\n\n\tixgbe_lower_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum low period of clock is 4.7 us */\n\tudelay(IXGBE_I2C_T_LOW);\n\n}\n\n/**\n * ixgbe_i2c_stop - Sets I2C stop condition\n * @hw: pointer to hardware structure\n *\n * Sets I2C stop condition (Low -> High on SDA while SCL is High)\n **/\nstatic void ixgbe_i2c_stop(struct ixgbe_hw *hw)\n{\n\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n\n\t/* Stop condition must begin with data low and clock high */\n\tixgbe_set_i2c_data(hw, &i2cctl, 0);\n\tixgbe_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Setup time for stop condition (4us) */\n\tudelay(IXGBE_I2C_T_SU_STO);\n\n\tixgbe_set_i2c_data(hw, &i2cctl, 1);\n\n\t/* bus free time between stop and start (4.7us)*/\n\tudelay(IXGBE_I2C_T_BUF);\n}\n\n/**\n * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C\n * @hw: pointer to hardware structure\n * @data: data byte to clock in\n *\n * Clocks in one byte data via I2C data/clock\n **/\nstatic s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)\n{\n\ts32 i;\n\tbool bit = 0;\n\n\tfor (i = 7; i >= 0; i--) {\n\t\tixgbe_clock_in_i2c_bit(hw, &bit);\n\t\t*data |= bit << i;\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C\n * @hw: pointer to hardware structure\n * @data: data byte clocked out\n *\n * Clocks out one byte data via I2C data/clock\n **/\nstatic s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)\n{\n\ts32 status = 0;\n\ts32 i;\n\tu32 i2cctl;\n\tbool bit = 0;\n\n\tfor (i = 7; i >= 0; i--) {\n\t\tbit = (data >> i) & 0x1;\n\t\tstatus = ixgbe_clock_out_i2c_bit(hw, bit);\n\n\t\tif (status != 0)\n\t\t\tbreak;\n\t}\n\n\t/* Release SDA line (set high) */\n\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n\ti2cctl |= IXGBE_I2C_DATA_OUT;\n\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_i2c_ack - Polls for I2C ACK\n * @hw: pointer to hardware structure\n *\n * Clocks in/out one bit via I2C data/clock\n **/\nstatic s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\tu32 i = 0;\n\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n\tu32 timeout = 10;\n\tbool ack = 1;\n\n\tixgbe_raise_i2c_clk(hw, &i2cctl);\n\n\n\t/* Minimum high period of clock is 4us */\n\tudelay(IXGBE_I2C_T_HIGH);\n\n\t/* Poll for ACK. Note that ACK in I2C spec is\n\t * transition from 1 to 0 */\n\tfor (i = 0; i < timeout; i++) {\n\t\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n\t\tack = ixgbe_get_i2c_data(&i2cctl);\n\n\t\tudelay(1);\n\t\tif (ack == 0)\n\t\t\tbreak;\n\t}\n\n\tif (ack == 1) {\n\t\thw_dbg(hw, \"I2C ack was not received.\\n\");\n\t\tstatus = IXGBE_ERR_I2C;\n\t}\n\n\tixgbe_lower_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum low period of clock is 4.7 us */\n\tudelay(IXGBE_I2C_T_LOW);\n\n\treturn status;\n}\n\n/**\n * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock\n * @hw: pointer to hardware structure\n * @data: read data value\n *\n * Clocks in one bit via I2C data/clock\n **/\nstatic s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)\n{\n\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n\n\tixgbe_raise_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum high period of clock is 4us */\n\tudelay(IXGBE_I2C_T_HIGH);\n\n\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n\t*data = ixgbe_get_i2c_data(&i2cctl);\n\n\tixgbe_lower_i2c_clk(hw, &i2cctl);\n\n\t/* Minimum low period of clock is 4.7 us */\n\tudelay(IXGBE_I2C_T_LOW);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock\n * @hw: pointer to hardware structure\n * @data: data value to write\n *\n * Clocks out one bit via I2C data/clock\n **/\nstatic s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)\n{\n\ts32 status;\n\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n\n\tstatus = ixgbe_set_i2c_data(hw, &i2cctl, data);\n\tif (status == 0) {\n\t\tixgbe_raise_i2c_clk(hw, &i2cctl);\n\n\t\t/* Minimum high period of clock is 4us */\n\t\tudelay(IXGBE_I2C_T_HIGH);\n\n\t\tixgbe_lower_i2c_clk(hw, &i2cctl);\n\n\t\t/* Minimum low period of clock is 4.7 us.\n\t\t * This also takes care of the data hold time.\n\t\t */\n\t\tudelay(IXGBE_I2C_T_LOW);\n\t} else {\n\t\tstatus = IXGBE_ERR_I2C;\n\t\thw_dbg(hw, \"I2C data was not set to %X\\n\", data);\n\t}\n\n\treturn status;\n}\n/**\n * ixgbe_raise_i2c_clk - Raises the I2C SCL clock\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Raises the I2C clock line '0'->'1'\n **/\nstatic void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)\n{\n\tu32 i = 0;\n\tu32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;\n\tu32 i2cctl_r = 0;\n\n\tfor (i = 0; i < timeout; i++) {\n\t\t*i2cctl |= IXGBE_I2C_CLK_OUT;\n\n\t\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);\n\t\tIXGBE_WRITE_FLUSH(hw);\n\t\t/* SCL rise time (1000ns) */\n\t\tudelay(IXGBE_I2C_T_RISE);\n\n\t\ti2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n\t\tif (i2cctl_r & IXGBE_I2C_CLK_IN)\n\t\t\tbreak;\n\t}\n}\n\n/**\n * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Lowers the I2C clock line '1'->'0'\n **/\nstatic void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)\n{\n\n\t*i2cctl &= ~IXGBE_I2C_CLK_OUT;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* SCL fall time (300ns) */\n\tudelay(IXGBE_I2C_T_FALL);\n}\n\n/**\n * ixgbe_set_i2c_data - Sets the I2C data bit\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n * @data: I2C data value (0 or 1) to set\n *\n * Sets the I2C data bit\n **/\nstatic s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)\n{\n\ts32 status = 0;\n\n\tif (data)\n\t\t*i2cctl |= IXGBE_I2C_DATA_OUT;\n\telse\n\t\t*i2cctl &= ~IXGBE_I2C_DATA_OUT;\n\n\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */\n\tudelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);\n\n\t/* Verify data was set correctly */\n\t*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n\tif (data != ixgbe_get_i2c_data(i2cctl)) {\n\t\tstatus = IXGBE_ERR_I2C;\n\t\thw_dbg(hw, \"Error - I2C data was not set to %X.\\n\", data);\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_get_i2c_data - Reads the I2C SDA data bit\n * @hw: pointer to hardware structure\n * @i2cctl: Current value of I2CCTL register\n *\n * Returns the I2C data bit value\n **/\nstatic bool ixgbe_get_i2c_data(u32 *i2cctl)\n{\n\tbool data;\n\n\tif (*i2cctl & IXGBE_I2C_DATA_IN)\n\t\tdata = 1;\n\telse\n\t\tdata = 0;\n\n\treturn data;\n}\n\n/**\n * ixgbe_i2c_bus_clear - Clears the I2C bus\n * @hw: pointer to hardware structure\n *\n * Clears the I2C bus by sending nine clock pulses.\n * Used when data line is stuck low.\n **/\nvoid ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)\n{\n\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n\tu32 i;\n\n\tixgbe_i2c_start(hw);\n\n\tixgbe_set_i2c_data(hw, &i2cctl, 1);\n\n\tfor (i = 0; i < 9; i++) {\n\t\tixgbe_raise_i2c_clk(hw, &i2cctl);\n\n\t\t/* Min high period of clock is 4us */\n\t\tudelay(IXGBE_I2C_T_HIGH);\n\n\t\tixgbe_lower_i2c_clk(hw, &i2cctl);\n\n\t\t/* Min low period of clock is 4.7us*/\n\t\tudelay(IXGBE_I2C_T_LOW);\n\t}\n\n\tixgbe_i2c_start(hw);\n\n\t/* Put the i2c bus back to default state */\n\tixgbe_i2c_stop(hw);\n}\n\n/**\n * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.\n * @hw: pointer to hardware structure\n *\n * Checks if the LASI temp alarm status was triggered due to overtemp\n **/\ns32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\tu16 phy_data = 0;\n\n\tif (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)\n\t\tgoto out;\n\n\t/* Check that the LASI temp alarm status was triggered */\n\thw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,\n\t\t\t IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);\n\n\tif (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))\n\t\tgoto out;\n\n\tstatus = IXGBE_ERR_OVERTEMP;\nout:\n\treturn status;\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_phy.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _IXGBE_PHY_H_\n#define _IXGBE_PHY_H_\n\n#include \"ixgbe_type.h\"\n#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0\n\n/* EEPROM byte offsets */\n#define IXGBE_SFF_IDENTIFIER\t\t0x0\n#define IXGBE_SFF_IDENTIFIER_SFP\t0x3\n#define IXGBE_SFF_VENDOR_OUI_BYTE0\t0x25\n#define IXGBE_SFF_VENDOR_OUI_BYTE1\t0x26\n#define IXGBE_SFF_VENDOR_OUI_BYTE2\t0x27\n#define IXGBE_SFF_1GBE_COMP_CODES\t0x6\n#define IXGBE_SFF_10GBE_COMP_CODES\t0x3\n#define IXGBE_SFF_CABLE_TECHNOLOGY\t0x8\n#define IXGBE_SFF_CABLE_SPEC_COMP\t0x3C\n\n/* Bitmasks */\n#define IXGBE_SFF_DA_PASSIVE_CABLE\t0x4\n#define IXGBE_SFF_DA_ACTIVE_CABLE\t0x8\n#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING\t0x4\n#define IXGBE_SFF_1GBASESX_CAPABLE\t0x1\n#define IXGBE_SFF_1GBASELX_CAPABLE\t0x2\n#define IXGBE_SFF_1GBASET_CAPABLE\t0x8\n#define IXGBE_SFF_10GBASESR_CAPABLE\t0x10\n#define IXGBE_SFF_10GBASELR_CAPABLE\t0x20\n#define IXGBE_I2C_EEPROM_READ_MASK\t0x100\n#define IXGBE_I2C_EEPROM_STATUS_MASK\t0x3\n#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION\t0x0\n#define IXGBE_I2C_EEPROM_STATUS_PASS\t0x1\n#define IXGBE_I2C_EEPROM_STATUS_FAIL\t0x2\n#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS\t0x3\n\n/* Flow control defines */\n#define IXGBE_TAF_SYM_PAUSE\t\t0x400\n#define IXGBE_TAF_ASM_PAUSE\t\t0x800\n\n/* Bit-shift macros */\n#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT\t24\n#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT\t16\n#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT\t8\n\n/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */\n#define IXGBE_SFF_VENDOR_OUI_TYCO\t0x00407600\n#define IXGBE_SFF_VENDOR_OUI_FTL\t0x00906500\n#define IXGBE_SFF_VENDOR_OUI_AVAGO\t0x00176A00\n#define IXGBE_SFF_VENDOR_OUI_INTEL\t0x001B2100\n\n/* I2C SDA and SCL timing parameters for standard mode */\n#define IXGBE_I2C_T_HD_STA\t4\n#define IXGBE_I2C_T_LOW\t\t5\n#define IXGBE_I2C_T_HIGH\t4\n#define IXGBE_I2C_T_SU_STA\t5\n#define IXGBE_I2C_T_HD_DATA\t5\n#define IXGBE_I2C_T_SU_DATA\t1\n#define IXGBE_I2C_T_RISE\t1\n#define IXGBE_I2C_T_FALL\t1\n#define IXGBE_I2C_T_SU_STO\t4\n#define IXGBE_I2C_T_BUF\t\t5\n\n#define IXGBE_TN_LASI_STATUS_REG\t0x9005\n#define IXGBE_TN_LASI_STATUS_TEMP_ALARM\t0x0008\n\ns32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);\nbool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);\nenum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);\ns32 ixgbe_get_phy_id(struct ixgbe_hw *hw);\ns32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);\ns32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);\ns32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t u32 device_type, u16 *phy_data);\ns32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,\n\t\t\t\tu32 device_type, u16 phy_data);\ns32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);\ns32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed speed,\n\t\t\t\t bool autoneg,\n\t\t\t\t bool autoneg_wait_to_complete);\ns32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t\t bool *autoneg);\n\n/* PHY specific */\ns32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,\n\t\t\t ixgbe_link_speed *speed,\n\t\t\t bool *link_up);\ns32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);\ns32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,\n\t\t\t\t u16 *firmware_version);\ns32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,\n\t\t\t\t\t u16 *firmware_version);\n\ns32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);\ns32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);\ns32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);\ns32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);\ns32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,\n\t\t\t\t\tu16 *list_offset,\n\t\t\t\t\tu16 *data_offset);\ns32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);\ns32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\tu8 dev_addr, u8 *data);\ns32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 dev_addr, u8 data);\ns32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 *eeprom_data);\ns32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n\t\t\t\t u8 eeprom_data);\nvoid ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);\n#endif /* _IXGBE_PHY_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_sriov.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n\n#ifndef _IXGBE_SRIOV_H_\n#define _IXGBE_SRIOV_H_\n\nint ixgbe_set_vf_multicasts(struct ixgbe_adapter *adapter,\n\t\t\t int entries, u16 *hash_list, u32 vf);\nvoid ixgbe_restore_vf_multicasts(struct ixgbe_adapter *adapter);\nint ixgbe_set_vf_vlan(struct ixgbe_adapter *adapter, int add, int vid, u32 vf);\nvoid ixgbe_set_vmolr(struct ixgbe_hw *hw, u32 vf, bool aupe);\nvoid ixgbe_vf_reset_event(struct ixgbe_adapter *adapter, u32 vf);\nvoid ixgbe_vf_reset_msg(struct ixgbe_adapter *adapter, u32 vf);\nvoid ixgbe_msg_task(struct ixgbe_adapter *adapter);\nint ixgbe_set_vf_mac(struct ixgbe_adapter *adapter,\n\t\t int vf, unsigned char *mac_addr);\nvoid ixgbe_disable_tx_rx(struct ixgbe_adapter *adapter);\nvoid ixgbe_ping_all_vfs(struct ixgbe_adapter *adapter);\n#ifdef IFLA_VF_MAX\nint ixgbe_ndo_set_vf_mac(struct net_device *netdev, int queue, u8 *mac);\nint ixgbe_ndo_set_vf_vlan(struct net_device *netdev, int queue, u16 vlan,\n\t\t\t u8 qos);\nint ixgbe_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);\n#ifdef HAVE_VF_SPOOFCHK_CONFIGURE\nint ixgbe_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, bool setting);\n#endif\nint ixgbe_ndo_get_vf_config(struct net_device *netdev,\n\t\t\t int vf, struct ifla_vf_info *ivi);\n#endif\nvoid ixgbe_disable_sriov(struct ixgbe_adapter *adapter);\n#ifdef CONFIG_PCI_IOV\nint ixgbe_vf_configuration(struct pci_dev *pdev, unsigned int event_mask);\nvoid ixgbe_enable_sriov(struct ixgbe_adapter *adapter);\n#endif\nint ixgbe_check_vf_assignment(struct ixgbe_adapter *adapter);\n#ifdef IFLA_VF_MAX\nvoid ixgbe_check_vf_rate_limit(struct ixgbe_adapter *adapter);\n#endif /* IFLA_VF_MAX */\nvoid ixgbe_dump_registers(struct ixgbe_adapter *adapter);\n\n/*\n * These are defined in ixgbe_type.h on behalf of the VF driver\n * but we need them here unwrapped for the PF driver.\n */\n#define IXGBE_DEV_ID_82599_VF\t\t\t0x10ED\n#define IXGBE_DEV_ID_X540_VF\t\t\t0x1515\n\n#endif /* _IXGBE_SRIOV_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_type.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _IXGBE_TYPE_H_\n#define _IXGBE_TYPE_H_\n\n#include \"ixgbe_osdep.h\"\n\n\n/* Vendor ID */\n#define IXGBE_INTEL_VENDOR_ID\t\t\t0x8086\n\n/* Device IDs */\n#define IXGBE_DEV_ID_82598\t\t\t0x10B6\n#define IXGBE_DEV_ID_82598_BX\t\t\t0x1508\n#define IXGBE_DEV_ID_82598AF_DUAL_PORT\t\t0x10C6\n#define IXGBE_DEV_ID_82598AF_SINGLE_PORT\t0x10C7\n#define IXGBE_DEV_ID_82598AT\t\t\t0x10C8\n#define IXGBE_DEV_ID_82598AT2\t\t\t0x150B\n#define IXGBE_DEV_ID_82598EB_SFP_LOM\t\t0x10DB\n#define IXGBE_DEV_ID_82598EB_CX4\t\t0x10DD\n#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT\t0x10EC\n#define IXGBE_DEV_ID_82598_DA_DUAL_PORT\t\t0x10F1\n#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM\t0x10E1\n#define IXGBE_DEV_ID_82598EB_XF_LR\t\t0x10F4\n#define IXGBE_DEV_ID_82599_KX4\t\t\t0x10F7\n#define IXGBE_DEV_ID_82599_KX4_MEZZ\t\t0x1514\n#define IXGBE_DEV_ID_82599_KR\t\t\t0x1517\n#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE\t0x10F8\n#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ\t0x000C\n#define IXGBE_DEV_ID_82599_CX4\t\t\t0x10F9\n#define IXGBE_DEV_ID_82599_SFP\t\t\t0x10FB\n#define IXGBE_SUBDEV_ID_82599_SFP\t\t0x11A9\n#define IXGBE_SUBDEV_ID_82599_560FLR\t\t0x17D0\n#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE\t0x152A\n#define IXGBE_DEV_ID_82599_SFP_FCOE\t\t0x1529\n#define IXGBE_DEV_ID_82599_SFP_EM\t\t0x1507\n#define IXGBE_DEV_ID_82599_SFP_SF2\t\t0x154D\n#define IXGBE_DEV_ID_82599_QSFP_SF_QP\t\t0x1558\n#define IXGBE_DEV_ID_82599EN_SFP\t\t0x1557\n#define IXGBE_DEV_ID_82599_XAUI_LOM\t\t0x10FC\n#define IXGBE_DEV_ID_82599_T3_LOM\t\t0x151C\n#define IXGBE_DEV_ID_82599_LS\t\t\t0x154F\n#define IXGBE_DEV_ID_X540T\t\t\t0x1528\n\n/* General Registers */\n#define IXGBE_CTRL\t\t0x00000\n#define IXGBE_STATUS\t\t0x00008\n#define IXGBE_CTRL_EXT\t\t0x00018\n#define IXGBE_ESDP\t\t0x00020\n#define IXGBE_EODSDP\t\t0x00028\n#define IXGBE_I2CCTL\t\t0x00028\n#define IXGBE_PHY_GPIO\t\t0x00028\n#define IXGBE_MAC_GPIO\t\t0x00030\n#define IXGBE_PHYINT_STATUS0\t0x00100\n#define IXGBE_PHYINT_STATUS1\t0x00104\n#define IXGBE_PHYINT_STATUS2\t0x00108\n#define IXGBE_LEDCTL\t\t0x00200\n#define IXGBE_FRTIMER\t\t0x00048\n#define IXGBE_TCPTIMER\t\t0x0004C\n#define IXGBE_CORESPARE\t\t0x00600\n#define IXGBE_EXVET\t\t0x05078\n\n/* NVM Registers */\n#define IXGBE_EEC\t0x10010\n#define IXGBE_EERD\t0x10014\n#define IXGBE_EEWR\t0x10018\n#define IXGBE_FLA\t0x1001C\n#define IXGBE_EEMNGCTL\t0x10110\n#define IXGBE_EEMNGDATA\t0x10114\n#define IXGBE_FLMNGCTL\t0x10118\n#define IXGBE_FLMNGDATA\t0x1011C\n#define IXGBE_FLMNGCNT\t0x10120\n#define IXGBE_FLOP\t0x1013C\n#define IXGBE_GRC\t0x10200\n#define IXGBE_SRAMREL\t0x10210\n#define IXGBE_PHYDBG\t0x10218\n\n/* General Receive Control */\n#define IXGBE_GRC_MNG\t0x00000001 /* Manageability Enable */\n#define IXGBE_GRC_APME\t0x00000002 /* APM enabled in EEPROM */\n\n#define IXGBE_VPDDIAG0\t0x10204\n#define IXGBE_VPDDIAG1\t0x10208\n\n/* I2CCTL Bit Masks */\n#define IXGBE_I2C_CLK_IN\t0x00000001\n#define IXGBE_I2C_CLK_OUT\t0x00000002\n#define IXGBE_I2C_DATA_IN\t0x00000004\n#define IXGBE_I2C_DATA_OUT\t0x00000008\n#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT\t500\n\n#define IXGBE_I2C_THERMAL_SENSOR_ADDR\t0xF8\n#define IXGBE_EMC_INTERNAL_DATA\t\t0x00\n#define IXGBE_EMC_INTERNAL_THERM_LIMIT\t0x20\n#define IXGBE_EMC_DIODE1_DATA\t\t0x01\n#define IXGBE_EMC_DIODE1_THERM_LIMIT\t0x19\n#define IXGBE_EMC_DIODE2_DATA\t\t0x23\n#define IXGBE_EMC_DIODE2_THERM_LIMIT\t0x1A\n\n#define IXGBE_MAX_SENSORS\t\t3\n\nstruct ixgbe_thermal_diode_data {\n\tu8 location;\n\tu8 temp;\n\tu8 caution_thresh;\n\tu8 max_op_thresh;\n};\n\nstruct ixgbe_thermal_sensor_data {\n\tstruct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];\n};\n\n/* Interrupt Registers */\n#define IXGBE_EICR\t\t0x00800\n#define IXGBE_EICS\t\t0x00808\n#define IXGBE_EIMS\t\t0x00880\n#define IXGBE_EIMC\t\t0x00888\n#define IXGBE_EIAC\t\t0x00810\n#define IXGBE_EIAM\t\t0x00890\n#define IXGBE_EICS_EX(_i)\t(0x00A90 + (_i) * 4)\n#define IXGBE_EIMS_EX(_i)\t(0x00AA0 + (_i) * 4)\n#define IXGBE_EIMC_EX(_i)\t(0x00AB0 + (_i) * 4)\n#define IXGBE_EIAM_EX(_i)\t(0x00AD0 + (_i) * 4)\n/* 82599 EITR is only 12 bits, with the lower 3 always zero */\n/*\n * 82598 EITR is 16 bits but set the limits based on the max\n * supported by all ixgbe hardware\n */\n#define IXGBE_MAX_INT_RATE\t488281\n#define IXGBE_MIN_INT_RATE\t956\n#define IXGBE_MAX_EITR\t\t0x00000FF8\n#define IXGBE_MIN_EITR\t\t8\n#define IXGBE_EITR(_i)\t\t(((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \\\n\t\t\t\t (0x012300 + (((_i) - 24) * 4)))\n#define IXGBE_EITR_ITR_INT_MASK\t0x00000FF8\n#define IXGBE_EITR_LLI_MOD\t0x00008000\n#define IXGBE_EITR_CNT_WDIS\t0x80000000\n#define IXGBE_IVAR(_i)\t\t(0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */\n#define IXGBE_IVAR_MISC\t\t0x00A00 /* misc MSI-X interrupt causes */\n#define IXGBE_EITRSEL\t\t0x00894\n#define IXGBE_MSIXT\t\t0x00000 /* MSI-X Table. 0x0000 - 0x01C */\n#define IXGBE_MSIXPBA\t\t0x02000 /* MSI-X Pending bit array */\n#define IXGBE_PBACL(_i)\t(((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))\n#define IXGBE_GPIE\t\t0x00898\n\n/* Flow Control Registers */\n#define IXGBE_FCADBUL\t\t0x03210\n#define IXGBE_FCADBUH\t\t0x03214\n#define IXGBE_FCAMACL\t\t0x04328\n#define IXGBE_FCAMACH\t\t0x0432C\n#define IXGBE_FCRTH_82599(_i)\t(0x03260 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_FCRTL_82599(_i)\t(0x03220 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_PFCTOP\t\t0x03008\n#define IXGBE_FCTTV(_i)\t\t(0x03200 + ((_i) * 4)) /* 4 of these (0-3) */\n#define IXGBE_FCRTL(_i)\t\t(0x03220 + ((_i) * 8)) /* 8 of these (0-7) */\n#define IXGBE_FCRTH(_i)\t\t(0x03260 + ((_i) * 8)) /* 8 of these (0-7) */\n#define IXGBE_FCRTV\t\t0x032A0\n#define IXGBE_FCCFG\t\t0x03D00\n#define IXGBE_TFCS\t\t0x0CE00\n\n/* Receive DMA Registers */\n#define IXGBE_RDBAL(_i)\t(((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \\\n\t\t\t (0x0D000 + (((_i) - 64) * 0x40)))\n#define IXGBE_RDBAH(_i)\t(((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \\\n\t\t\t (0x0D004 + (((_i) - 64) * 0x40)))\n#define IXGBE_RDLEN(_i)\t(((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \\\n\t\t\t (0x0D008 + (((_i) - 64) * 0x40)))\n#define IXGBE_RDH(_i)\t(((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \\\n\t\t\t (0x0D010 + (((_i) - 64) * 0x40)))\n#define IXGBE_RDT(_i)\t(((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \\\n\t\t\t (0x0D018 + (((_i) - 64) * 0x40)))\n#define IXGBE_RXDCTL(_i)\t(((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \\\n\t\t\t\t (0x0D028 + (((_i) - 64) * 0x40)))\n#define IXGBE_RSCCTL(_i)\t(((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \\\n\t\t\t\t (0x0D02C + (((_i) - 64) * 0x40)))\n#define IXGBE_RSCDBU\t0x03028\n#define IXGBE_RDDCC\t0x02F20\n#define IXGBE_RXMEMWRAP\t0x03190\n#define IXGBE_STARCTRL\t0x03024\n/*\n * Split and Replication Receive Control Registers\n * 00-15 : 0x02100 + n*4\n * 16-64 : 0x01014 + n*0x40\n * 64-127: 0x0D014 + (n-64)*0x40\n */\n#define IXGBE_SRRCTL(_i)\t(((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \\\n\t\t\t\t (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \\\n\t\t\t\t (0x0D014 + (((_i) - 64) * 0x40))))\n/*\n * Rx DCA Control Register:\n * 00-15 : 0x02200 + n*4\n * 16-64 : 0x0100C + n*0x40\n * 64-127: 0x0D00C + (n-64)*0x40\n */\n#define IXGBE_DCA_RXCTRL(_i)\t(((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \\\n\t\t\t\t (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \\\n\t\t\t\t (0x0D00C + (((_i) - 64) * 0x40))))\n#define IXGBE_RDRXCTL\t\t0x02F00\n#define IXGBE_RDRXCTL_RSC_PUSH\t0x80\n/* 8 of these 0x03C00 - 0x03C1C */\n#define IXGBE_RXPBSIZE(_i)\t(0x03C00 + ((_i) * 4))\n#define IXGBE_RXCTRL\t\t0x03000\n#define IXGBE_DROPEN\t\t0x03D04\n#define IXGBE_RXPBSIZE_SHIFT\t10\n\n/* Receive Registers */\n#define IXGBE_RXCSUM\t\t0x05000\n#define IXGBE_RFCTL\t\t0x05008\n#define IXGBE_DRECCCTL\t\t0x02F08\n#define IXGBE_DRECCCTL_DISABLE\t0\n#define IXGBE_DRECCCTL2\t\t0x02F8C\n\n/* Multicast Table Array - 128 entries */\n#define IXGBE_MTA(_i)\t\t(0x05200 + ((_i) * 4))\n#define IXGBE_RAL(_i)\t\t(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \\\n\t\t\t\t (0x0A200 + ((_i) * 8)))\n#define IXGBE_RAH(_i)\t\t(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \\\n\t\t\t\t (0x0A204 + ((_i) * 8)))\n#define IXGBE_MPSAR_LO(_i)\t(0x0A600 + ((_i) * 8))\n#define IXGBE_MPSAR_HI(_i)\t(0x0A604 + ((_i) * 8))\n/* Packet split receive type */\n#define IXGBE_PSRTYPE(_i)\t(((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \\\n\t\t\t\t (0x0EA00 + ((_i) * 4)))\n/* array of 4096 1-bit vlan filters */\n#define IXGBE_VFTA(_i)\t\t(0x0A000 + ((_i) * 4))\n/*array of 4096 4-bit vlan vmdq indices */\n#define IXGBE_VFTAVIND(_j, _i)\t(0x0A200 + ((_j) * 0x200) + ((_i) * 4))\n#define IXGBE_FCTRL\t\t0x05080\n#define IXGBE_VLNCTRL\t\t0x05088\n#define IXGBE_MCSTCTRL\t\t0x05090\n#define IXGBE_MRQC\t\t0x05818\n#define IXGBE_SAQF(_i)\t(0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */\n#define IXGBE_DAQF(_i)\t(0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */\n#define IXGBE_SDPQF(_i)\t(0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */\n#define IXGBE_FTQF(_i)\t(0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */\n#define IXGBE_ETQF(_i)\t(0x05128 + ((_i) * 4)) /* EType Queue Filter */\n#define IXGBE_ETQS(_i)\t(0x0EC00 + ((_i) * 4)) /* EType Queue Select */\n#define IXGBE_SYNQF\t0x0EC30 /* SYN Packet Queue Filter */\n#define IXGBE_RQTC\t0x0EC70\n#define IXGBE_MTQC\t0x08120\n#define IXGBE_VLVF(_i)\t(0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */\n#define IXGBE_VLVFB(_i)\t(0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */\n#define IXGBE_VMVIR(_i)\t(0x08000 + ((_i) * 4)) /* 64 of these (0-63) */\n#define IXGBE_VT_CTL\t\t0x051B0\n#define IXGBE_PFMAILBOX(_i)\t(0x04B00 + (4 * (_i))) /* 64 total */\n/* 64 Mailboxes, 16 DW each */\n#define IXGBE_PFMBMEM(_i)\t(0x13000 + (64 * (_i)))\n#define IXGBE_PFMBICR(_i)\t(0x00710 + (4 * (_i))) /* 4 total */\n#define IXGBE_PFMBIMR(_i)\t(0x00720 + (4 * (_i))) /* 4 total */\n#define IXGBE_VFRE(_i)\t\t(0x051E0 + ((_i) * 4))\n#define IXGBE_VFTE(_i)\t\t(0x08110 + ((_i) * 4))\n#define IXGBE_VMECM(_i)\t\t(0x08790 + ((_i) * 4))\n#define IXGBE_QDE\t\t0x2F04\n#define IXGBE_VMTXSW(_i)\t(0x05180 + ((_i) * 4)) /* 2 total */\n#define IXGBE_VMOLR(_i)\t\t(0x0F000 + ((_i) * 4)) /* 64 total */\n#define IXGBE_UTA(_i)\t\t(0x0F400 + ((_i) * 4))\n#define IXGBE_MRCTL(_i)\t\t(0x0F600 + ((_i) * 4))\n#define IXGBE_VMRVLAN(_i)\t(0x0F610 + ((_i) * 4))\n#define IXGBE_VMRVM(_i)\t\t(0x0F630 + ((_i) * 4))\n#define IXGBE_L34T_IMIR(_i)\t(0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/\n#define IXGBE_RXFECCERR0\t0x051B8\n#define IXGBE_LLITHRESH\t\t0x0EC90\n#define IXGBE_IMIR(_i)\t\t(0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_IMIREXT(_i)\t(0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_IMIRVP\t\t0x05AC0\n#define IXGBE_VMD_CTL\t\t0x0581C\n#define IXGBE_RETA(_i)\t\t(0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */\n#define IXGBE_RSSRK(_i)\t\t(0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */\n\n/* Flow Director registers */\n#define IXGBE_FDIRCTRL\t0x0EE00\n#define IXGBE_FDIRHKEY\t0x0EE68\n#define IXGBE_FDIRSKEY\t0x0EE6C\n#define IXGBE_FDIRDIP4M\t0x0EE3C\n#define IXGBE_FDIRSIP4M\t0x0EE40\n#define IXGBE_FDIRTCPM\t0x0EE44\n#define IXGBE_FDIRUDPM\t0x0EE48\n#define IXGBE_FDIRIP6M\t0x0EE74\n#define IXGBE_FDIRM\t0x0EE70\n\n/* Flow Director Stats registers */\n#define IXGBE_FDIRFREE\t0x0EE38\n#define IXGBE_FDIRLEN\t0x0EE4C\n#define IXGBE_FDIRUSTAT\t0x0EE50\n#define IXGBE_FDIRFSTAT\t0x0EE54\n#define IXGBE_FDIRMATCH\t0x0EE58\n#define IXGBE_FDIRMISS\t0x0EE5C\n\n/* Flow Director Programming registers */\n#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */\n#define IXGBE_FDIRIPSA\t0x0EE18\n#define IXGBE_FDIRIPDA\t0x0EE1C\n#define IXGBE_FDIRPORT\t0x0EE20\n#define IXGBE_FDIRVLAN\t0x0EE24\n#define IXGBE_FDIRHASH\t0x0EE28\n#define IXGBE_FDIRCMD\t0x0EE2C\n\n/* Transmit DMA registers */\n#define IXGBE_TDBAL(_i)\t\t(0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/\n#define IXGBE_TDBAH(_i)\t\t(0x06004 + ((_i) * 0x40))\n#define IXGBE_TDLEN(_i)\t\t(0x06008 + ((_i) * 0x40))\n#define IXGBE_TDH(_i)\t\t(0x06010 + ((_i) * 0x40))\n#define IXGBE_TDT(_i)\t\t(0x06018 + ((_i) * 0x40))\n#define IXGBE_TXDCTL(_i)\t(0x06028 + ((_i) * 0x40))\n#define IXGBE_TDWBAL(_i)\t(0x06038 + ((_i) * 0x40))\n#define IXGBE_TDWBAH(_i)\t(0x0603C + ((_i) * 0x40))\n#define IXGBE_DTXCTL\t\t0x07E00\n\n#define IXGBE_DMATXCTL\t\t0x04A80\n#define IXGBE_PFVFSPOOF(_i)\t(0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */\n#define IXGBE_PFDTXGSWC\t\t0x08220\n#define IXGBE_DTXMXSZRQ\t\t0x08100\n#define IXGBE_DTXTCPFLGL\t0x04A88\n#define IXGBE_DTXTCPFLGH\t0x04A8C\n#define IXGBE_LBDRPEN\t\t0x0CA00\n#define IXGBE_TXPBTHRESH(_i)\t(0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */\n\n#define IXGBE_DMATXCTL_TE\t0x1 /* Transmit Enable */\n#define IXGBE_DMATXCTL_NS\t0x2 /* No Snoop LSO hdr buffer */\n#define IXGBE_DMATXCTL_GDV\t0x8 /* Global Double VLAN */\n#define IXGBE_DMATXCTL_VT_SHIFT\t16 /* VLAN EtherType */\n\n#define IXGBE_PFDTXGSWC_VT_LBEN\t0x1 /* Local L2 VT switch enable */\n\n/* Anti-spoofing defines */\n#define IXGBE_SPOOF_MACAS_MASK\t\t0xFF\n#define IXGBE_SPOOF_VLANAS_MASK\t\t0xFF00\n#define IXGBE_SPOOF_VLANAS_SHIFT\t8\n#define IXGBE_PFVFSPOOF_REG_COUNT\t8\n/* 16 of these (0-15) */\n#define IXGBE_DCA_TXCTRL(_i)\t\t(0x07200 + ((_i) * 4))\n/* Tx DCA Control register : 128 of these (0-127) */\n#define IXGBE_DCA_TXCTRL_82599(_i)\t(0x0600C + ((_i) * 0x40))\n#define IXGBE_TIPG\t\t\t0x0CB00\n#define IXGBE_TXPBSIZE(_i)\t\t(0x0CC00 + ((_i) * 4)) /* 8 of these */\n#define IXGBE_MNGTXMAP\t\t\t0x0CD10\n#define IXGBE_TIPG_FIBER_DEFAULT\t3\n#define IXGBE_TXPBSIZE_SHIFT\t\t10\n\n/* Wake up registers */\n#define IXGBE_WUC\t0x05800\n#define IXGBE_WUFC\t0x05808\n#define IXGBE_WUS\t0x05810\n#define IXGBE_IPAV\t0x05838\n#define IXGBE_IP4AT\t0x05840 /* IPv4 table 0x5840-0x5858 */\n#define IXGBE_IP6AT\t0x05880 /* IPv6 table 0x5880-0x588F */\n\n#define IXGBE_WUPL\t0x05900\n#define IXGBE_WUPM\t0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */\n#define IXGBE_FHFT(_n)\t(0x09000 + (_n * 0x100)) /* Flex host filter table */\n/* Ext Flexible Host Filter Table */\n#define IXGBE_FHFT_EXT(_n)\t(0x09800 + (_n * 0x100))\n\n#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX\t\t4\n#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX\t2\n\n/* Each Flexible Filter is at most 128 (0x80) bytes in length */\n#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX\t\t128\n#define IXGBE_FHFT_LENGTH_OFFSET\t\t0xFC /* Length byte in FHFT */\n#define IXGBE_FHFT_LENGTH_MASK\t\t\t0x0FF /* Length in lower byte */\n\n/* Definitions for power management and wakeup registers */\n/* Wake Up Control */\n#define IXGBE_WUC_PME_EN\t0x00000002 /* PME Enable */\n#define IXGBE_WUC_PME_STATUS\t0x00000004 /* PME Status */\n#define IXGBE_WUC_WKEN\t\t0x00000010 /* Enable PE_WAKE_N pin assertion */\n\n/* Wake Up Filter Control */\n#define IXGBE_WUFC_LNKC\t0x00000001 /* Link Status Change Wakeup Enable */\n#define IXGBE_WUFC_MAG\t0x00000002 /* Magic Packet Wakeup Enable */\n#define IXGBE_WUFC_EX\t0x00000004 /* Directed Exact Wakeup Enable */\n#define IXGBE_WUFC_MC\t0x00000008 /* Directed Multicast Wakeup Enable */\n#define IXGBE_WUFC_BC\t0x00000010 /* Broadcast Wakeup Enable */\n#define IXGBE_WUFC_ARP\t0x00000020 /* ARP Request Packet Wakeup Enable */\n#define IXGBE_WUFC_IPV4\t0x00000040 /* Directed IPv4 Packet Wakeup Enable */\n#define IXGBE_WUFC_IPV6\t0x00000080 /* Directed IPv6 Packet Wakeup Enable */\n#define IXGBE_WUFC_MNG\t0x00000100 /* Directed Mgmt Packet Wakeup Enable */\n\n#define IXGBE_WUFC_IGNORE_TCO\t0x00008000 /* Ignore WakeOn TCO packets */\n#define IXGBE_WUFC_FLX0\t0x00010000 /* Flexible Filter 0 Enable */\n#define IXGBE_WUFC_FLX1\t0x00020000 /* Flexible Filter 1 Enable */\n#define IXGBE_WUFC_FLX2\t0x00040000 /* Flexible Filter 2 Enable */\n#define IXGBE_WUFC_FLX3\t0x00080000 /* Flexible Filter 3 Enable */\n#define IXGBE_WUFC_FLX4\t0x00100000 /* Flexible Filter 4 Enable */\n#define IXGBE_WUFC_FLX5\t0x00200000 /* Flexible Filter 5 Enable */\n#define IXGBE_WUFC_FLX_FILTERS\t0x000F0000 /* Mask for 4 flex filters */\n/* Mask for Ext. flex filters */\n#define IXGBE_WUFC_EXT_FLX_FILTERS\t0x00300000\n#define IXGBE_WUFC_ALL_FILTERS\t0x003F00FF /* Mask for all wakeup filters */\n#define IXGBE_WUFC_FLX_OFFSET\t16 /* Offset to the Flexible Filters bits */\n\n/* Wake Up Status */\n#define IXGBE_WUS_LNKC\t\tIXGBE_WUFC_LNKC\n#define IXGBE_WUS_MAG\t\tIXGBE_WUFC_MAG\n#define IXGBE_WUS_EX\t\tIXGBE_WUFC_EX\n#define IXGBE_WUS_MC\t\tIXGBE_WUFC_MC\n#define IXGBE_WUS_BC\t\tIXGBE_WUFC_BC\n#define IXGBE_WUS_ARP\t\tIXGBE_WUFC_ARP\n#define IXGBE_WUS_IPV4\t\tIXGBE_WUFC_IPV4\n#define IXGBE_WUS_IPV6\t\tIXGBE_WUFC_IPV6\n#define IXGBE_WUS_MNG\t\tIXGBE_WUFC_MNG\n#define IXGBE_WUS_FLX0\t\tIXGBE_WUFC_FLX0\n#define IXGBE_WUS_FLX1\t\tIXGBE_WUFC_FLX1\n#define IXGBE_WUS_FLX2\t\tIXGBE_WUFC_FLX2\n#define IXGBE_WUS_FLX3\t\tIXGBE_WUFC_FLX3\n#define IXGBE_WUS_FLX4\t\tIXGBE_WUFC_FLX4\n#define IXGBE_WUS_FLX5\t\tIXGBE_WUFC_FLX5\n#define IXGBE_WUS_FLX_FILTERS\tIXGBE_WUFC_FLX_FILTERS\n\n/* Wake Up Packet Length */\n#define IXGBE_WUPL_LENGTH_MASK\t0xFFFF\n\n/* DCB registers */\n#define IXGBE_DCB_MAX_TRAFFIC_CLASS\t8\n#define IXGBE_RMCS\t\t0x03D00\n#define IXGBE_DPMCS\t\t0x07F40\n#define IXGBE_PDPMCS\t\t0x0CD00\n#define IXGBE_RUPPBMR\t\t0x050A0\n#define IXGBE_RT2CR(_i)\t\t(0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_RT2SR(_i)\t\t(0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_TDTQ2TCCR(_i)\t(0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */\n#define IXGBE_TDTQ2TCSR(_i)\t(0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */\n#define IXGBE_TDPT2TCCR(_i)\t(0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_TDPT2TCSR(_i)\t(0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */\n\n\n/* Security Control Registers */\n#define IXGBE_SECTXCTRL\t\t0x08800\n#define IXGBE_SECTXSTAT\t\t0x08804\n#define IXGBE_SECTXBUFFAF\t0x08808\n#define IXGBE_SECTXMINIFG\t0x08810\n#define IXGBE_SECRXCTRL\t\t0x08D00\n#define IXGBE_SECRXSTAT\t\t0x08D04\n\n/* Security Bit Fields and Masks */\n#define IXGBE_SECTXCTRL_SECTX_DIS\t0x00000001\n#define IXGBE_SECTXCTRL_TX_DIS\t\t0x00000002\n#define IXGBE_SECTXCTRL_STORE_FORWARD\t0x00000004\n\n#define IXGBE_SECTXSTAT_SECTX_RDY\t0x00000001\n#define IXGBE_SECTXSTAT_ECC_TXERR\t0x00000002\n\n#define IXGBE_SECRXCTRL_SECRX_DIS\t0x00000001\n#define IXGBE_SECRXCTRL_RX_DIS\t\t0x00000002\n\n#define IXGBE_SECRXSTAT_SECRX_RDY\t0x00000001\n#define IXGBE_SECRXSTAT_ECC_RXERR\t0x00000002\n\n/* LinkSec (MacSec) Registers */\n#define IXGBE_LSECTXCAP\t\t0x08A00\n#define IXGBE_LSECRXCAP\t\t0x08F00\n#define IXGBE_LSECTXCTRL\t0x08A04\n#define IXGBE_LSECTXSCL\t\t0x08A08 /* SCI Low */\n#define IXGBE_LSECTXSCH\t\t0x08A0C /* SCI High */\n#define IXGBE_LSECTXSA\t\t0x08A10\n#define IXGBE_LSECTXPN0\t\t0x08A14\n#define IXGBE_LSECTXPN1\t\t0x08A18\n#define IXGBE_LSECTXKEY0(_n)\t(0x08A1C + (4 * (_n))) /* 4 of these (0-3) */\n#define IXGBE_LSECTXKEY1(_n)\t(0x08A2C + (4 * (_n))) /* 4 of these (0-3) */\n#define IXGBE_LSECRXCTRL\t0x08F04\n#define IXGBE_LSECRXSCL\t\t0x08F08\n#define IXGBE_LSECRXSCH\t\t0x08F0C\n#define IXGBE_LSECRXSA(_i)\t(0x08F10 + (4 * (_i))) /* 2 of these (0-1) */\n#define IXGBE_LSECRXPN(_i)\t(0x08F18 + (4 * (_i))) /* 2 of these (0-1) */\n#define IXGBE_LSECRXKEY(_n, _m)\t(0x08F20 + ((0x10 * (_n)) + (4 * (_m))))\n#define IXGBE_LSECTXUT\t\t0x08A3C /* OutPktsUntagged */\n#define IXGBE_LSECTXPKTE\t0x08A40 /* OutPktsEncrypted */\n#define IXGBE_LSECTXPKTP\t0x08A44 /* OutPktsProtected */\n#define IXGBE_LSECTXOCTE\t0x08A48 /* OutOctetsEncrypted */\n#define IXGBE_LSECTXOCTP\t0x08A4C /* OutOctetsProtected */\n#define IXGBE_LSECRXUT\t\t0x08F40 /* InPktsUntagged/InPktsNoTag */\n#define IXGBE_LSECRXOCTD\t0x08F44 /* InOctetsDecrypted */\n#define IXGBE_LSECRXOCTV\t0x08F48 /* InOctetsValidated */\n#define IXGBE_LSECRXBAD\t\t0x08F4C /* InPktsBadTag */\n#define IXGBE_LSECRXNOSCI\t0x08F50 /* InPktsNoSci */\n#define IXGBE_LSECRXUNSCI\t0x08F54 /* InPktsUnknownSci */\n#define IXGBE_LSECRXUNCH\t0x08F58 /* InPktsUnchecked */\n#define IXGBE_LSECRXDELAY\t0x08F5C /* InPktsDelayed */\n#define IXGBE_LSECRXLATE\t0x08F60 /* InPktsLate */\n#define IXGBE_LSECRXOK(_n)\t(0x08F64 + (0x04 * (_n))) /* InPktsOk */\n#define IXGBE_LSECRXINV(_n)\t(0x08F6C + (0x04 * (_n))) /* InPktsInvalid */\n#define IXGBE_LSECRXNV(_n)\t(0x08F74 + (0x04 * (_n))) /* InPktsNotValid */\n#define IXGBE_LSECRXUNSA\t0x08F7C /* InPktsUnusedSa */\n#define IXGBE_LSECRXNUSA\t0x08F80 /* InPktsNotUsingSa */\n\n/* LinkSec (MacSec) Bit Fields and Masks */\n#define IXGBE_LSECTXCAP_SUM_MASK\t0x00FF0000\n#define IXGBE_LSECTXCAP_SUM_SHIFT\t16\n#define IXGBE_LSECRXCAP_SUM_MASK\t0x00FF0000\n#define IXGBE_LSECRXCAP_SUM_SHIFT\t16\n\n#define IXGBE_LSECTXCTRL_EN_MASK\t0x00000003\n#define IXGBE_LSECTXCTRL_DISABLE\t0x0\n#define IXGBE_LSECTXCTRL_AUTH\t\t0x1\n#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT\t0x2\n#define IXGBE_LSECTXCTRL_AISCI\t\t0x00000020\n#define IXGBE_LSECTXCTRL_PNTHRSH_MASK\t0xFFFFFF00\n#define IXGBE_LSECTXCTRL_RSV_MASK\t0x000000D8\n\n#define IXGBE_LSECRXCTRL_EN_MASK\t0x0000000C\n#define IXGBE_LSECRXCTRL_EN_SHIFT\t2\n#define IXGBE_LSECRXCTRL_DISABLE\t0x0\n#define IXGBE_LSECRXCTRL_CHECK\t\t0x1\n#define IXGBE_LSECRXCTRL_STRICT\t\t0x2\n#define IXGBE_LSECRXCTRL_DROP\t\t0x3\n#define IXGBE_LSECRXCTRL_PLSH\t\t0x00000040\n#define IXGBE_LSECRXCTRL_RP\t\t0x00000080\n#define IXGBE_LSECRXCTRL_RSV_MASK\t0xFFFFFF33\n\n/* IpSec Registers */\n#define IXGBE_IPSTXIDX\t\t0x08900\n#define IXGBE_IPSTXSALT\t\t0x08904\n#define IXGBE_IPSTXKEY(_i)\t(0x08908 + (4 * (_i))) /* 4 of these (0-3) */\n#define IXGBE_IPSRXIDX\t\t0x08E00\n#define IXGBE_IPSRXIPADDR(_i)\t(0x08E04 + (4 * (_i))) /* 4 of these (0-3) */\n#define IXGBE_IPSRXSPI\t\t0x08E14\n#define IXGBE_IPSRXIPIDX\t0x08E18\n#define IXGBE_IPSRXKEY(_i)\t(0x08E1C + (4 * (_i))) /* 4 of these (0-3) */\n#define IXGBE_IPSRXSALT\t\t0x08E2C\n#define IXGBE_IPSRXMOD\t\t0x08E30\n\n#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE\t0x4\n\n/* DCB registers */\n#define IXGBE_RTRPCS\t\t0x02430\n#define IXGBE_RTTDCS\t\t0x04900\n#define IXGBE_RTTDCS_ARBDIS\t0x00000040 /* DCB arbiter disable */\n#define IXGBE_RTTPCS\t\t0x0CD00\n#define IXGBE_RTRUP2TC\t\t0x03020\n#define IXGBE_RTTUP2TC\t\t0x0C800\n#define IXGBE_RTRPT4C(_i)\t(0x02140 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_TXLLQ(_i)\t\t(0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */\n#define IXGBE_RTRPT4S(_i)\t(0x02160 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_RTTDT2C(_i)\t(0x04910 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_RTTDT2S(_i)\t(0x04930 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_RTTPT2C(_i)\t(0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_RTTPT2S(_i)\t(0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_RTTDQSEL\t\t0x04904\n#define IXGBE_RTTDT1C\t\t0x04908\n#define IXGBE_RTTDT1S\t\t0x0490C\n#define IXGBE_RTTDTECC\t\t0x04990\n#define IXGBE_RTTDTECC_NO_BCN\t0x00000100\n\n#define IXGBE_RTTBCNRC\t\t\t0x04984\n#define IXGBE_RTTBCNRC_RS_ENA\t\t0x80000000\n#define IXGBE_RTTBCNRC_RF_DEC_MASK\t0x00003FFF\n#define IXGBE_RTTBCNRC_RF_INT_SHIFT\t14\n#define IXGBE_RTTBCNRC_RF_INT_MASK \\\n\t(IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)\n#define IXGBE_RTTBCNRM\t0x04980\n\n/* FCoE DMA Context Registers */\n#define IXGBE_FCPTRL\t\t0x02410 /* FC User Desc. PTR Low */\n#define IXGBE_FCPTRH\t\t0x02414 /* FC USer Desc. PTR High */\n#define IXGBE_FCBUFF\t\t0x02418 /* FC Buffer Control */\n#define IXGBE_FCDMARW\t\t0x02420 /* FC Receive DMA RW */\n#define IXGBE_FCINVST0\t\t0x03FC0 /* FC Invalid DMA Context Status Reg 0*/\n#define IXGBE_FCINVST(_i)\t(IXGBE_FCINVST0 + ((_i) * 4))\n#define IXGBE_FCBUFF_VALID\t(1 << 0) /* DMA Context Valid */\n#define IXGBE_FCBUFF_BUFFSIZE\t(3 << 3) /* User Buffer Size */\n#define IXGBE_FCBUFF_WRCONTX\t(1 << 7) /* 0: Initiator, 1: Target */\n#define IXGBE_FCBUFF_BUFFCNT\t0x0000ff00 /* Number of User Buffers */\n#define IXGBE_FCBUFF_OFFSET\t0xffff0000 /* User Buffer Offset */\n#define IXGBE_FCBUFF_BUFFSIZE_SHIFT\t3\n#define IXGBE_FCBUFF_BUFFCNT_SHIFT\t8\n#define IXGBE_FCBUFF_OFFSET_SHIFT\t16\n#define IXGBE_FCDMARW_WE\t\t(1 << 14) /* Write enable */\n#define IXGBE_FCDMARW_RE\t\t(1 << 15) /* Read enable */\n#define IXGBE_FCDMARW_FCOESEL\t\t0x000001ff /* FC X_ID: 11 bits */\n#define IXGBE_FCDMARW_LASTSIZE\t\t0xffff0000 /* Last User Buffer Size */\n#define IXGBE_FCDMARW_LASTSIZE_SHIFT\t16\n/* FCoE SOF/EOF */\n#define IXGBE_TEOFF\t\t0x04A94 /* Tx FC EOF */\n#define IXGBE_TSOFF\t\t0x04A98 /* Tx FC SOF */\n#define IXGBE_REOFF\t\t0x05158 /* Rx FC EOF */\n#define IXGBE_RSOFF\t\t0x051F8 /* Rx FC SOF */\n/* FCoE Filter Context Registers */\n#define IXGBE_FCFLT\t\t0x05108 /* FC FLT Context */\n#define IXGBE_FCFLTRW\t\t0x05110 /* FC Filter RW Control */\n#define IXGBE_FCPARAM\t\t0x051d8 /* FC Offset Parameter */\n#define IXGBE_FCFLT_VALID\t(1 << 0) /* Filter Context Valid */\n#define IXGBE_FCFLT_FIRST\t(1 << 1) /* Filter First */\n#define IXGBE_FCFLT_SEQID\t0x00ff0000 /* Sequence ID */\n#define IXGBE_FCFLT_SEQCNT\t0xff000000 /* Sequence Count */\n#define IXGBE_FCFLTRW_RVALDT\t(1 << 13) /* Fast Re-Validation */\n#define IXGBE_FCFLTRW_WE\t(1 << 14) /* Write Enable */\n#define IXGBE_FCFLTRW_RE\t(1 << 15) /* Read Enable */\n/* FCoE Receive Control */\n#define IXGBE_FCRXCTRL\t\t0x05100 /* FC Receive Control */\n#define IXGBE_FCRXCTRL_FCOELLI\t(1 << 0) /* Low latency interrupt */\n#define IXGBE_FCRXCTRL_SAVBAD\t(1 << 1) /* Save Bad Frames */\n#define IXGBE_FCRXCTRL_FRSTRDH\t(1 << 2) /* EN 1st Read Header */\n#define IXGBE_FCRXCTRL_LASTSEQH\t(1 << 3) /* EN Last Header in Seq */\n#define IXGBE_FCRXCTRL_ALLH\t(1 << 4) /* EN All Headers */\n#define IXGBE_FCRXCTRL_FRSTSEQH\t(1 << 5) /* EN 1st Seq. Header */\n#define IXGBE_FCRXCTRL_ICRC\t(1 << 6) /* Ignore Bad FC CRC */\n#define IXGBE_FCRXCTRL_FCCRCBO\t(1 << 7) /* FC CRC Byte Ordering */\n#define IXGBE_FCRXCTRL_FCOEVER\t0x00000f00 /* FCoE Version: 4 bits */\n#define IXGBE_FCRXCTRL_FCOEVER_SHIFT\t8\n/* FCoE Redirection */\n#define IXGBE_FCRECTL\t\t0x0ED00 /* FC Redirection Control */\n#define IXGBE_FCRETA0\t\t0x0ED10 /* FC Redirection Table 0 */\n#define IXGBE_FCRETA(_i)\t(IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */\n#define IXGBE_FCRECTL_ENA\t0x1 /* FCoE Redir Table Enable */\n#define IXGBE_FCRETASEL_ENA\t0x2 /* FCoE FCRETASEL bit */\n#define IXGBE_FCRETA_SIZE\t8 /* Max entries in FCRETA */\n#define IXGBE_FCRETA_ENTRY_MASK\t0x0000007f /* 7 bits for the queue index */\n\n/* Stats registers */\n#define IXGBE_CRCERRS\t0x04000\n#define IXGBE_ILLERRC\t0x04004\n#define IXGBE_ERRBC\t0x04008\n#define IXGBE_MSPDC\t0x04010\n#define IXGBE_MPC(_i)\t(0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/\n#define IXGBE_MLFC\t0x04034\n#define IXGBE_MRFC\t0x04038\n#define IXGBE_RLEC\t0x04040\n#define IXGBE_LXONTXC\t0x03F60\n#define IXGBE_LXONRXC\t0x0CF60\n#define IXGBE_LXOFFTXC\t0x03F68\n#define IXGBE_LXOFFRXC\t0x0CF68\n#define IXGBE_LXONRXCNT\t\t0x041A4\n#define IXGBE_LXOFFRXCNT\t0x041A8\n#define IXGBE_PXONRXCNT(_i)\t(0x04140 + ((_i) * 4)) /* 8 of these */\n#define IXGBE_PXOFFRXCNT(_i)\t(0x04160 + ((_i) * 4)) /* 8 of these */\n#define IXGBE_PXON2OFFCNT(_i)\t(0x03240 + ((_i) * 4)) /* 8 of these */\n#define IXGBE_PXONTXC(_i)\t(0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/\n#define IXGBE_PXONRXC(_i)\t(0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/\n#define IXGBE_PXOFFTXC(_i)\t(0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/\n#define IXGBE_PXOFFRXC(_i)\t(0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/\n#define IXGBE_PRC64\t\t0x0405C\n#define IXGBE_PRC127\t\t0x04060\n#define IXGBE_PRC255\t\t0x04064\n#define IXGBE_PRC511\t\t0x04068\n#define IXGBE_PRC1023\t\t0x0406C\n#define IXGBE_PRC1522\t\t0x04070\n#define IXGBE_GPRC\t\t0x04074\n#define IXGBE_BPRC\t\t0x04078\n#define IXGBE_MPRC\t\t0x0407C\n#define IXGBE_GPTC\t\t0x04080\n#define IXGBE_GORCL\t\t0x04088\n#define IXGBE_GORCH\t\t0x0408C\n#define IXGBE_GOTCL\t\t0x04090\n#define IXGBE_GOTCH\t\t0x04094\n#define IXGBE_RNBC(_i)\t\t(0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/\n#define IXGBE_RUC\t\t0x040A4\n#define IXGBE_RFC\t\t0x040A8\n#define IXGBE_ROC\t\t0x040AC\n#define IXGBE_RJC\t\t0x040B0\n#define IXGBE_MNGPRC\t\t0x040B4\n#define IXGBE_MNGPDC\t\t0x040B8\n#define IXGBE_MNGPTC\t\t0x0CF90\n#define IXGBE_TORL\t\t0x040C0\n#define IXGBE_TORH\t\t0x040C4\n#define IXGBE_TPR\t\t0x040D0\n#define IXGBE_TPT\t\t0x040D4\n#define IXGBE_PTC64\t\t0x040D8\n#define IXGBE_PTC127\t\t0x040DC\n#define IXGBE_PTC255\t\t0x040E0\n#define IXGBE_PTC511\t\t0x040E4\n#define IXGBE_PTC1023\t\t0x040E8\n#define IXGBE_PTC1522\t\t0x040EC\n#define IXGBE_MPTC\t\t0x040F0\n#define IXGBE_BPTC\t\t0x040F4\n#define IXGBE_XEC\t\t0x04120\n#define IXGBE_SSVPC\t\t0x08780\n\n#define IXGBE_RQSMR(_i)\t(0x02300 + ((_i) * 4))\n#define IXGBE_TQSMR(_i)\t(((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \\\n\t\t\t (0x08600 + ((_i) * 4)))\n#define IXGBE_TQSM(_i)\t(0x08600 + ((_i) * 4))\n\n#define IXGBE_QPRC(_i)\t(0x01030 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QPTC(_i)\t(0x06030 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QBRC(_i)\t(0x01034 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QBTC(_i)\t(0x06034 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QBRC_L(_i)\t(0x01034 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QBRC_H(_i)\t(0x01038 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QPRDC(_i)\t\t(0x01430 + ((_i) * 0x40)) /* 16 of these */\n#define IXGBE_QBTC_L(_i)\t(0x08700 + ((_i) * 0x8)) /* 16 of these */\n#define IXGBE_QBTC_H(_i)\t(0x08704 + ((_i) * 0x8)) /* 16 of these */\n#define IXGBE_FCCRC\t\t0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */\n#define IXGBE_FCOERPDC\t\t0x0241C /* FCoE Rx Packets Dropped Count */\n#define IXGBE_FCLAST\t\t0x02424 /* FCoE Last Error Count */\n#define IXGBE_FCOEPRC\t\t0x02428 /* Number of FCoE Packets Received */\n#define IXGBE_FCOEDWRC\t\t0x0242C /* Number of FCoE DWords Received */\n#define IXGBE_FCOEPTC\t\t0x08784 /* Number of FCoE Packets Transmitted */\n#define IXGBE_FCOEDWTC\t\t0x08788 /* Number of FCoE DWords Transmitted */\n#define IXGBE_FCCRC_CNT_MASK\t0x0000FFFF /* CRC_CNT: bit 0 - 15 */\n#define IXGBE_FCLAST_CNT_MASK\t0x0000FFFF /* Last_CNT: bit 0 - 15 */\n#define IXGBE_O2BGPTC\t\t0x041C4\n#define IXGBE_O2BSPC\t\t0x087B0\n#define IXGBE_B2OSPC\t\t0x041C0\n#define IXGBE_B2OGPRC\t\t0x02F90\n#define IXGBE_BUPRC\t\t0x04180\n#define IXGBE_BMPRC\t\t0x04184\n#define IXGBE_BBPRC\t\t0x04188\n#define IXGBE_BUPTC\t\t0x0418C\n#define IXGBE_BMPTC\t\t0x04190\n#define IXGBE_BBPTC\t\t0x04194\n#define IXGBE_BCRCERRS\t\t0x04198\n#define IXGBE_BXONRXC\t\t0x0419C\n#define IXGBE_BXOFFRXC\t\t0x041E0\n#define IXGBE_BXONTXC\t\t0x041E4\n#define IXGBE_BXOFFTXC\t\t0x041E8\n#define IXGBE_PCRC8ECL\t\t0x0E810\n#define IXGBE_PCRC8ECH\t\t0x0E811\n#define IXGBE_PCRC8ECH_MASK\t0x1F\n#define IXGBE_LDPCECL\t\t0x0E820\n#define IXGBE_LDPCECH\t\t0x0E821\n\n/* Management */\n#define IXGBE_MAVTV(_i)\t\t(0x05010 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_MFUTP(_i)\t\t(0x05030 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_MANC\t\t0x05820\n#define IXGBE_MFVAL\t\t0x05824\n#define IXGBE_MANC2H\t\t0x05860\n#define IXGBE_MDEF(_i)\t\t(0x05890 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_MIPAF\t\t0x058B0\n#define IXGBE_MMAL(_i)\t\t(0x05910 + ((_i) * 8)) /* 4 of these (0-3) */\n#define IXGBE_MMAH(_i)\t\t(0x05914 + ((_i) * 8)) /* 4 of these (0-3) */\n#define IXGBE_FTFT\t\t0x09400 /* 0x9400-0x97FC */\n#define IXGBE_METF(_i)\t\t(0x05190 + ((_i) * 4)) /* 4 of these (0-3) */\n#define IXGBE_MDEF_EXT(_i)\t(0x05160 + ((_i) * 4)) /* 8 of these (0-7) */\n#define IXGBE_LSWFW\t\t0x15014\n#define IXGBE_BMCIP(_i)\t\t(0x05050 + ((_i) * 4)) /* 0x5050-0x505C */\n#define IXGBE_BMCIPVAL\t\t0x05060\n#define IXGBE_BMCIP_IPADDR_TYPE\t0x00000001\n#define IXGBE_BMCIP_IPADDR_VALID\t0x00000002\n\n/* Management Bit Fields and Masks */\n#define IXGBE_MANC_EN_BMC2OS\t0x10000000 /* Ena BMC2OS and OS2BMC traffic */\n#define IXGBE_MANC_EN_BMC2OS_SHIFT\t28\n\n/* Firmware Semaphore Register */\n#define IXGBE_FWSM_MODE_MASK\t0xE\n\n/* ARC Subsystem registers */\n#define IXGBE_HICR\t\t0x15F00\n#define IXGBE_FWSTS\t\t0x15F0C\n#define IXGBE_HSMC0R\t\t0x15F04\n#define IXGBE_HSMC1R\t\t0x15F08\n#define IXGBE_SWSR\t\t0x15F10\n#define IXGBE_HFDR\t\t0x15FE8\n#define IXGBE_FLEX_MNG\t\t0x15800 /* 0x15800 - 0x15EFC */\n\n#define IXGBE_HICR_EN\t\t0x01 /* Enable bit - RO */\n/* Driver sets this bit when done to put command in RAM */\n#define IXGBE_HICR_C\t\t0x02\n#define IXGBE_HICR_SV\t\t0x04 /* Status Validity */\n#define IXGBE_HICR_FW_RESET_ENABLE\t0x40\n#define IXGBE_HICR_FW_RESET\t0x80\n\n/* PCI-E registers */\n#define IXGBE_GCR\t\t0x11000\n#define IXGBE_GTV\t\t0x11004\n#define IXGBE_FUNCTAG\t\t0x11008\n#define IXGBE_GLT\t\t0x1100C\n#define IXGBE_PCIEPIPEADR\t0x11004\n#define IXGBE_PCIEPIPEDAT\t0x11008\n#define IXGBE_GSCL_1\t\t0x11010\n#define IXGBE_GSCL_2\t\t0x11014\n#define IXGBE_GSCL_3\t\t0x11018\n#define IXGBE_GSCL_4\t\t0x1101C\n#define IXGBE_GSCN_0\t\t0x11020\n#define IXGBE_GSCN_1\t\t0x11024\n#define IXGBE_GSCN_2\t\t0x11028\n#define IXGBE_GSCN_3\t\t0x1102C\n#define IXGBE_FACTPS\t\t0x10150\n#define IXGBE_PCIEANACTL\t0x11040\n#define IXGBE_SWSM\t\t0x10140\n#define IXGBE_FWSM\t\t0x10148\n#define IXGBE_GSSR\t\t0x10160\n#define IXGBE_MREVID\t\t0x11064\n#define IXGBE_DCA_ID\t\t0x11070\n#define IXGBE_DCA_CTRL\t\t0x11074\n#define IXGBE_SWFW_SYNC\t\tIXGBE_GSSR\n\n/* PCI-E registers 82599-Specific */\n#define IXGBE_GCR_EXT\t\t0x11050\n#define IXGBE_GSCL_5_82599\t0x11030\n#define IXGBE_GSCL_6_82599\t0x11034\n#define IXGBE_GSCL_7_82599\t0x11038\n#define IXGBE_GSCL_8_82599\t0x1103C\n#define IXGBE_PHYADR_82599\t0x11040\n#define IXGBE_PHYDAT_82599\t0x11044\n#define IXGBE_PHYCTL_82599\t0x11048\n#define IXGBE_PBACLR_82599\t0x11068\n#define IXGBE_CIAA_82599\t0x11088\n#define IXGBE_CIAD_82599\t0x1108C\n#define IXGBE_PICAUSE\t\t0x110B0\n#define IXGBE_PIENA\t\t0x110B8\n#define IXGBE_CDQ_MBR_82599\t0x110B4\n#define IXGBE_PCIESPARE\t\t0x110BC\n#define IXGBE_MISC_REG_82599\t0x110F0\n#define IXGBE_ECC_CTRL_0_82599\t0x11100\n#define IXGBE_ECC_CTRL_1_82599\t0x11104\n#define IXGBE_ECC_STATUS_82599\t0x110E0\n#define IXGBE_BAR_CTRL_82599\t0x110F4\n\n/* PCI Express Control */\n#define IXGBE_GCR_CMPL_TMOUT_MASK\t0x0000F000\n#define IXGBE_GCR_CMPL_TMOUT_10ms\t0x00001000\n#define IXGBE_GCR_CMPL_TMOUT_RESEND\t0x00010000\n#define IXGBE_GCR_CAP_VER2\t\t0x00040000\n\n#define IXGBE_GCR_EXT_MSIX_EN\t\t0x80000000\n#define IXGBE_GCR_EXT_BUFFERS_CLEAR\t0x40000000\n#define IXGBE_GCR_EXT_VT_MODE_16\t0x00000001\n#define IXGBE_GCR_EXT_VT_MODE_32\t0x00000002\n#define IXGBE_GCR_EXT_VT_MODE_64\t0x00000003\n#define IXGBE_GCR_EXT_SRIOV\t\t(IXGBE_GCR_EXT_MSIX_EN | \\\n\t\t\t\t\t IXGBE_GCR_EXT_VT_MODE_64)\n/* Time Sync Registers */\n#define IXGBE_TSYNCRXCTL\t0x05188 /* Rx Time Sync Control register - RW */\n#define IXGBE_TSYNCTXCTL\t0x08C00 /* Tx Time Sync Control register - RW */\n#define IXGBE_RXSTMPL\t0x051E8 /* Rx timestamp Low - RO */\n#define IXGBE_RXSTMPH\t0x051A4 /* Rx timestamp High - RO */\n#define IXGBE_RXSATRL\t0x051A0 /* Rx timestamp attribute low - RO */\n#define IXGBE_RXSATRH\t0x051A8 /* Rx timestamp attribute high - RO */\n#define IXGBE_RXMTRL\t0x05120 /* RX message type register low - RW */\n#define IXGBE_TXSTMPL\t0x08C04 /* Tx timestamp value Low - RO */\n#define IXGBE_TXSTMPH\t0x08C08 /* Tx timestamp value High - RO */\n#define IXGBE_SYSTIML\t0x08C0C /* System time register Low - RO */\n#define IXGBE_SYSTIMH\t0x08C10 /* System time register High - RO */\n#define IXGBE_TIMINCA\t0x08C14 /* Increment attributes register - RW */\n#define IXGBE_TIMADJL\t0x08C18 /* Time Adjustment Offset register Low - RW */\n#define IXGBE_TIMADJH\t0x08C1C /* Time Adjustment Offset register High - RW */\n#define IXGBE_TSAUXC\t0x08C20 /* TimeSync Auxiliary Control register - RW */\n#define IXGBE_TRGTTIML0\t0x08C24 /* Target Time Register 0 Low - RW */\n#define IXGBE_TRGTTIMH0\t0x08C28 /* Target Time Register 0 High - RW */\n#define IXGBE_TRGTTIML1\t0x08C2C /* Target Time Register 1 Low - RW */\n#define IXGBE_TRGTTIMH1\t0x08C30 /* Target Time Register 1 High - RW */\n#define IXGBE_FREQOUT0\t0x08C34 /* Frequency Out 0 Control register - RW */\n#define IXGBE_FREQOUT1\t0x08C38 /* Frequency Out 1 Control register - RW */\n#define IXGBE_AUXSTMPL0\t0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */\n#define IXGBE_AUXSTMPH0\t0x08C40 /* Auxiliary Time Stamp 0 register High - RO */\n#define IXGBE_AUXSTMPL1\t0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */\n#define IXGBE_AUXSTMPH1\t0x08C48 /* Auxiliary Time Stamp 1 register High - RO */\n\n/* Diagnostic Registers */\n#define IXGBE_RDSTATCTL\t\t0x02C20\n#define IXGBE_RDSTAT(_i)\t(0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */\n#define IXGBE_RDHMPN\t\t0x02F08\n#define IXGBE_RIC_DW(_i)\t(0x02F10 + ((_i) * 4))\n#define IXGBE_RDPROBE\t\t0x02F20\n#define IXGBE_RDMAM\t\t0x02F30\n#define IXGBE_RDMAD\t\t0x02F34\n#define IXGBE_TDSTATCTL\t\t0x07C20\n#define IXGBE_TDSTAT(_i)\t(0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */\n#define IXGBE_TDHMPN\t\t0x07F08\n#define IXGBE_TDHMPN2\t\t0x082FC\n#define IXGBE_TXDESCIC\t\t0x082CC\n#define IXGBE_TIC_DW(_i)\t(0x07F10 + ((_i) * 4))\n#define IXGBE_TIC_DW2(_i)\t(0x082B0 + ((_i) * 4))\n#define IXGBE_TDPROBE\t\t0x07F20\n#define IXGBE_TXBUFCTRL\t\t0x0C600\n#define IXGBE_TXBUFDATA0\t0x0C610\n#define IXGBE_TXBUFDATA1\t0x0C614\n#define IXGBE_TXBUFDATA2\t0x0C618\n#define IXGBE_TXBUFDATA3\t0x0C61C\n#define IXGBE_RXBUFCTRL\t\t0x03600\n#define IXGBE_RXBUFDATA0\t0x03610\n#define IXGBE_RXBUFDATA1\t0x03614\n#define IXGBE_RXBUFDATA2\t0x03618\n#define IXGBE_RXBUFDATA3\t0x0361C\n#define IXGBE_PCIE_DIAG(_i)\t(0x11090 + ((_i) * 4)) /* 8 of these */\n#define IXGBE_RFVAL\t\t0x050A4\n#define IXGBE_MDFTC1\t\t0x042B8\n#define IXGBE_MDFTC2\t\t0x042C0\n#define IXGBE_MDFTFIFO1\t\t0x042C4\n#define IXGBE_MDFTFIFO2\t\t0x042C8\n#define IXGBE_MDFTS\t\t0x042CC\n#define IXGBE_RXDATAWRPTR(_i)\t(0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/\n#define IXGBE_RXDESCWRPTR(_i)\t(0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/\n#define IXGBE_RXDATARDPTR(_i)\t(0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/\n#define IXGBE_RXDESCRDPTR(_i)\t(0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/\n#define IXGBE_TXDATAWRPTR(_i)\t(0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/\n#define IXGBE_TXDESCWRPTR(_i)\t(0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/\n#define IXGBE_TXDATARDPTR(_i)\t(0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/\n#define IXGBE_TXDESCRDPTR(_i)\t(0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/\n#define IXGBE_PCIEECCCTL\t0x1106C\n#define IXGBE_RXWRPTR(_i)\t(0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/\n#define IXGBE_RXUSED(_i)\t(0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/\n#define IXGBE_RXRDPTR(_i)\t(0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/\n#define IXGBE_RXRDWRPTR(_i)\t(0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/\n#define IXGBE_TXWRPTR(_i)\t(0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/\n#define IXGBE_TXUSED(_i)\t(0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/\n#define IXGBE_TXRDPTR(_i)\t(0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/\n#define IXGBE_TXRDWRPTR(_i)\t(0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/\n#define IXGBE_PCIEECCCTL0\t0x11100\n#define IXGBE_PCIEECCCTL1\t0x11104\n#define IXGBE_RXDBUECC\t\t0x03F70\n#define IXGBE_TXDBUECC\t\t0x0CF70\n#define IXGBE_RXDBUEST\t\t0x03F74\n#define IXGBE_TXDBUEST\t\t0x0CF74\n#define IXGBE_PBTXECC\t\t0x0C300\n#define IXGBE_PBRXECC\t\t0x03300\n#define IXGBE_GHECCR\t\t0x110B0\n\n/* MAC Registers */\n#define IXGBE_PCS1GCFIG\t\t0x04200\n#define IXGBE_PCS1GLCTL\t\t0x04208\n#define IXGBE_PCS1GLSTA\t\t0x0420C\n#define IXGBE_PCS1GDBG0\t\t0x04210\n#define IXGBE_PCS1GDBG1\t\t0x04214\n#define IXGBE_PCS1GANA\t\t0x04218\n#define IXGBE_PCS1GANLP\t\t0x0421C\n#define IXGBE_PCS1GANNP\t\t0x04220\n#define IXGBE_PCS1GANLPNP\t0x04224\n#define IXGBE_HLREG0\t\t0x04240\n#define IXGBE_HLREG1\t\t0x04244\n#define IXGBE_PAP\t\t0x04248\n#define IXGBE_MACA\t\t0x0424C\n#define IXGBE_APAE\t\t0x04250\n#define IXGBE_ARD\t\t0x04254\n#define IXGBE_AIS\t\t0x04258\n#define IXGBE_MSCA\t\t0x0425C\n#define IXGBE_MSRWD\t\t0x04260\n#define IXGBE_MLADD\t\t0x04264\n#define IXGBE_MHADD\t\t0x04268\n#define IXGBE_MAXFRS\t\t0x04268\n#define IXGBE_TREG\t\t0x0426C\n#define IXGBE_PCSS1\t\t0x04288\n#define IXGBE_PCSS2\t\t0x0428C\n#define IXGBE_XPCSS\t\t0x04290\n#define IXGBE_MFLCN\t\t0x04294\n#define IXGBE_SERDESC\t\t0x04298\n#define IXGBE_MACS\t\t0x0429C\n#define IXGBE_AUTOC\t\t0x042A0\n#define IXGBE_LINKS\t\t0x042A4\n#define IXGBE_LINKS2\t\t0x04324\n#define IXGBE_AUTOC2\t\t0x042A8\n#define IXGBE_AUTOC3\t\t0x042AC\n#define IXGBE_ANLP1\t\t0x042B0\n#define IXGBE_ANLP2\t\t0x042B4\n#define IXGBE_MACC\t\t0x04330\n#define IXGBE_ATLASCTL\t\t0x04800\n#define IXGBE_MMNGC\t\t0x042D0\n#define IXGBE_ANLPNP1\t\t0x042D4\n#define IXGBE_ANLPNP2\t\t0x042D8\n#define IXGBE_KRPCSFC\t\t0x042E0\n#define IXGBE_KRPCSS\t\t0x042E4\n#define IXGBE_FECS1\t\t0x042E8\n#define IXGBE_FECS2\t\t0x042EC\n#define IXGBE_SMADARCTL\t\t0x14F10\n#define IXGBE_MPVC\t\t0x04318\n#define IXGBE_SGMIIC\t\t0x04314\n\n/* Statistics Registers */\n#define IXGBE_RXNFGPC\t\t0x041B0\n#define IXGBE_RXNFGBCL\t\t0x041B4\n#define IXGBE_RXNFGBCH\t\t0x041B8\n#define IXGBE_RXDGPC\t\t0x02F50\n#define IXGBE_RXDGBCL\t\t0x02F54\n#define IXGBE_RXDGBCH\t\t0x02F58\n#define IXGBE_RXDDGPC\t\t0x02F5C\n#define IXGBE_RXDDGBCL\t\t0x02F60\n#define IXGBE_RXDDGBCH\t\t0x02F64\n#define IXGBE_RXLPBKGPC\t\t0x02F68\n#define IXGBE_RXLPBKGBCL\t0x02F6C\n#define IXGBE_RXLPBKGBCH\t0x02F70\n#define IXGBE_RXDLPBKGPC\t0x02F74\n#define IXGBE_RXDLPBKGBCL\t0x02F78\n#define IXGBE_RXDLPBKGBCH\t0x02F7C\n#define IXGBE_TXDGPC\t\t0x087A0\n#define IXGBE_TXDGBCL\t\t0x087A4\n#define IXGBE_TXDGBCH\t\t0x087A8\n\n#define IXGBE_RXDSTATCTRL\t0x02F40\n\n/* Copper Pond 2 link timeout */\n#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50\n\n/* Omer CORECTL */\n#define IXGBE_CORECTL\t\t\t0x014F00\n/* BARCTRL */\n#define IXGBE_BARCTRL\t\t\t0x110F4\n#define IXGBE_BARCTRL_FLSIZE\t\t0x0700\n#define IXGBE_BARCTRL_FLSIZE_SHIFT\t8\n#define IXGBE_BARCTRL_CSRSIZE\t\t0x2000\n\n/* RSCCTL Bit Masks */\n#define IXGBE_RSCCTL_RSCEN\t0x01\n#define IXGBE_RSCCTL_MAXDESC_1\t0x00\n#define IXGBE_RSCCTL_MAXDESC_4\t0x04\n#define IXGBE_RSCCTL_MAXDESC_8\t0x08\n#define IXGBE_RSCCTL_MAXDESC_16\t0x0C\n\n/* RSCDBU Bit Masks */\n#define IXGBE_RSCDBU_RSCSMALDIS_MASK\t0x0000007F\n#define IXGBE_RSCDBU_RSCACKDIS\t\t0x00000080\n\n/* RDRXCTL Bit Masks */\n#define IXGBE_RDRXCTL_RDMTS_1_2\t\t0x00000000 /* Rx Desc Min THLD Size */\n#define IXGBE_RDRXCTL_CRCSTRIP\t\t0x00000002 /* CRC Strip */\n#define IXGBE_RDRXCTL_MVMEN\t\t0x00000020\n#define IXGBE_RDRXCTL_DMAIDONE\t\t0x00000008 /* DMA init cycle done */\n#define IXGBE_RDRXCTL_AGGDIS\t\t0x00010000 /* Aggregation disable */\n#define IXGBE_RDRXCTL_RSCFRSTSIZE\t0x003E0000 /* RSC First packet size */\n#define IXGBE_RDRXCTL_RSCLLIDIS\t\t0x00800000 /* Disabl RSC compl on LLI */\n#define IXGBE_RDRXCTL_RSCACKC\t\t0x02000000 /* must set 1 when RSC ena */\n#define IXGBE_RDRXCTL_FCOE_WRFIX\t0x04000000 /* must set 1 when RSC ena */\n\n/* RQTC Bit Masks and Shifts */\n#define IXGBE_RQTC_SHIFT_TC(_i)\t((_i) * 4)\n#define IXGBE_RQTC_TC0_MASK\t(0x7 << 0)\n#define IXGBE_RQTC_TC1_MASK\t(0x7 << 4)\n#define IXGBE_RQTC_TC2_MASK\t(0x7 << 8)\n#define IXGBE_RQTC_TC3_MASK\t(0x7 << 12)\n#define IXGBE_RQTC_TC4_MASK\t(0x7 << 16)\n#define IXGBE_RQTC_TC5_MASK\t(0x7 << 20)\n#define IXGBE_RQTC_TC6_MASK\t(0x7 << 24)\n#define IXGBE_RQTC_TC7_MASK\t(0x7 << 28)\n\n/* PSRTYPE.RQPL Bit masks and shift */\n#define IXGBE_PSRTYPE_RQPL_MASK\t\t0x7\n#define IXGBE_PSRTYPE_RQPL_SHIFT\t29\n\n/* CTRL Bit Masks */\n#define IXGBE_CTRL_GIO_DIS\t0x00000004 /* Global IO Master Disable bit */\n#define IXGBE_CTRL_LNK_RST\t0x00000008 /* Link Reset. Resets everything. */\n#define IXGBE_CTRL_RST\t\t0x04000000 /* Reset (SW) */\n#define IXGBE_CTRL_RST_MASK\t(IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)\n\n/* FACTPS */\n#define IXGBE_FACTPS_LFS\t0x40000000 /* LAN Function Select */\n\n/* MHADD Bit Masks */\n#define IXGBE_MHADD_MFS_MASK\t0xFFFF0000\n#define IXGBE_MHADD_MFS_SHIFT\t16\n\n/* Extended Device Control */\n#define IXGBE_CTRL_EXT_PFRSTD\t0x00004000 /* Physical Function Reset Done */\n#define IXGBE_CTRL_EXT_NS_DIS\t0x00010000 /* No Snoop disable */\n#define IXGBE_CTRL_EXT_RO_DIS\t0x00020000 /* Relaxed Ordering disable */\n#define IXGBE_CTRL_EXT_DRV_LOAD\t0x10000000 /* Driver loaded bit for FW */\n\n/* Direct Cache Access (DCA) definitions */\n#define IXGBE_DCA_CTRL_DCA_ENABLE\t0x00000000 /* DCA Enable */\n#define IXGBE_DCA_CTRL_DCA_DISABLE\t0x00000001 /* DCA Disable */\n\n#define IXGBE_DCA_CTRL_DCA_MODE_CB1\t0x00 /* DCA Mode CB1 */\n#define IXGBE_DCA_CTRL_DCA_MODE_CB2\t0x02 /* DCA Mode CB2 */\n\n#define IXGBE_DCA_RXCTRL_CPUID_MASK\t0x0000001F /* Rx CPUID Mask */\n#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599\t0xFF000000 /* Rx CPUID Mask */\n#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599\t24 /* Rx CPUID Shift */\n#define IXGBE_DCA_RXCTRL_DESC_DCA_EN\t(1 << 5) /* Rx Desc enable */\n#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN\t(1 << 6) /* Rx Desc header ena */\n#define IXGBE_DCA_RXCTRL_DATA_DCA_EN\t(1 << 7) /* Rx Desc payload ena */\n#define IXGBE_DCA_RXCTRL_DESC_RRO_EN\t(1 << 9) /* Rx rd Desc Relax Order */\n#define IXGBE_DCA_RXCTRL_DATA_WRO_EN\t(1 << 13) /* Rx wr data Relax Order */\n#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN\t(1 << 15) /* Rx wr header RO */\n\n#define IXGBE_DCA_TXCTRL_CPUID_MASK\t0x0000001F /* Tx CPUID Mask */\n#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599\t0xFF000000 /* Tx CPUID Mask */\n#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599\t24 /* Tx CPUID Shift */\n#define IXGBE_DCA_TXCTRL_DESC_DCA_EN\t(1 << 5) /* DCA Tx Desc enable */\n#define IXGBE_DCA_TXCTRL_DESC_RRO_EN\t(1 << 9) /* Tx rd Desc Relax Order */\n#define IXGBE_DCA_TXCTRL_DESC_WRO_EN\t(1 << 11) /* Tx Desc writeback RO bit */\n#define IXGBE_DCA_TXCTRL_DATA_RRO_EN\t(1 << 13) /* Tx rd data Relax Order */\n#define IXGBE_DCA_MAX_QUEUES_82598\t16 /* DCA regs only on 16 queues */\n\n/* MSCA Bit Masks */\n#define IXGBE_MSCA_NP_ADDR_MASK\t\t0x0000FFFF /* MDI Addr (new prot) */\n#define IXGBE_MSCA_NP_ADDR_SHIFT\t0\n#define IXGBE_MSCA_DEV_TYPE_MASK\t0x001F0000 /* Dev Type (new prot) */\n#define IXGBE_MSCA_DEV_TYPE_SHIFT\t16 /* Register Address (old prot */\n#define IXGBE_MSCA_PHY_ADDR_MASK\t0x03E00000 /* PHY Address mask */\n#define IXGBE_MSCA_PHY_ADDR_SHIFT\t21 /* PHY Address shift*/\n#define IXGBE_MSCA_OP_CODE_MASK\t\t0x0C000000 /* OP CODE mask */\n#define IXGBE_MSCA_OP_CODE_SHIFT\t26 /* OP CODE shift */\n#define IXGBE_MSCA_ADDR_CYCLE\t\t0x00000000 /* OP CODE 00 (addr cycle) */\n#define IXGBE_MSCA_WRITE\t\t0x04000000 /* OP CODE 01 (wr) */\n#define IXGBE_MSCA_READ\t\t\t0x0C000000 /* OP CODE 11 (rd) */\n#define IXGBE_MSCA_READ_AUTOINC\t\t0x08000000 /* OP CODE 10 (rd auto inc)*/\n#define IXGBE_MSCA_ST_CODE_MASK\t\t0x30000000 /* ST Code mask */\n#define IXGBE_MSCA_ST_CODE_SHIFT\t28 /* ST Code shift */\n#define IXGBE_MSCA_NEW_PROTOCOL\t\t0x00000000 /* ST CODE 00 (new prot) */\n#define IXGBE_MSCA_OLD_PROTOCOL\t\t0x10000000 /* ST CODE 01 (old prot) */\n#define IXGBE_MSCA_MDI_COMMAND\t\t0x40000000 /* Initiate MDI command */\n#define IXGBE_MSCA_MDI_IN_PROG_EN\t0x80000000 /* MDI in progress ena */\n\n/* MSRWD bit masks */\n#define IXGBE_MSRWD_WRITE_DATA_MASK\t0x0000FFFF\n#define IXGBE_MSRWD_WRITE_DATA_SHIFT\t0\n#define IXGBE_MSRWD_READ_DATA_MASK\t0xFFFF0000\n#define IXGBE_MSRWD_READ_DATA_SHIFT\t16\n\n/* Atlas registers */\n#define IXGBE_ATLAS_PDN_LPBK\t\t0x24\n#define IXGBE_ATLAS_PDN_10G\t\t0xB\n#define IXGBE_ATLAS_PDN_1G\t\t0xC\n#define IXGBE_ATLAS_PDN_AN\t\t0xD\n\n/* Atlas bit masks */\n#define IXGBE_ATLASCTL_WRITE_CMD\t0x00010000\n#define IXGBE_ATLAS_PDN_TX_REG_EN\t0x10\n#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL\t0xF0\n#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL\t0xF0\n#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL\t0xF0\n\n/* Omer bit masks */\n#define IXGBE_CORECTL_WRITE_CMD\t\t0x00010000\n\n/* Device Type definitions for new protocol MDIO commands */\n#define IXGBE_MDIO_PMA_PMD_DEV_TYPE\t\t0x1\n#define IXGBE_MDIO_PCS_DEV_TYPE\t\t\t0x3\n#define IXGBE_MDIO_PHY_XS_DEV_TYPE\t\t0x4\n#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE\t\t0x7\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE\t0x1E /* Device 30 */\n#define IXGBE_TWINAX_DEV\t\t\t1\n\n#define IXGBE_MDIO_COMMAND_TIMEOUT\t100 /* PHY Timeout for 1 GB mode */\n\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL\t\t0x0 /* VS1 Ctrl Reg */\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS\t\t0x1 /* VS1 Status Reg */\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS\t0x0008 /* 1 = Link Up */\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS\t0x0010 /* 0-10G, 1-1G */\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED\t\t0x0018\n#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED\t\t0x0010\n\n#define IXGBE_MDIO_AUTO_NEG_CONTROL\t0x0 /* AUTO_NEG Control Reg */\n#define IXGBE_MDIO_AUTO_NEG_STATUS\t0x1 /* AUTO_NEG Status Reg */\n#define IXGBE_MDIO_AUTO_NEG_ADVT\t0x10 /* AUTO_NEG Advt Reg */\n#define IXGBE_MDIO_AUTO_NEG_LP\t\t0x13 /* AUTO_NEG LP Status Reg */\n#define IXGBE_MDIO_PHY_XS_CONTROL\t0x0 /* PHY_XS Control Reg */\n#define IXGBE_MDIO_PHY_XS_RESET\t\t0x8000 /* PHY_XS Reset */\n#define IXGBE_MDIO_PHY_ID_HIGH\t\t0x2 /* PHY ID High Reg*/\n#define IXGBE_MDIO_PHY_ID_LOW\t\t0x3 /* PHY ID Low Reg*/\n#define IXGBE_MDIO_PHY_SPEED_ABILITY\t0x4 /* Speed Ability Reg */\n#define IXGBE_MDIO_PHY_SPEED_10G\t0x0001 /* 10G capable */\n#define IXGBE_MDIO_PHY_SPEED_1G\t\t0x0010 /* 1G capable */\n#define IXGBE_MDIO_PHY_SPEED_100M\t0x0020 /* 100M capable */\n#define IXGBE_MDIO_PHY_EXT_ABILITY\t0xB /* Ext Ability Reg */\n#define IXGBE_MDIO_PHY_10GBASET_ABILITY\t\t0x0004 /* 10GBaseT capable */\n#define IXGBE_MDIO_PHY_1000BASET_ABILITY\t0x0020 /* 1000BaseT capable */\n#define IXGBE_MDIO_PHY_100BASETX_ABILITY\t0x0080 /* 100BaseTX capable */\n#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE\t0x0800 /* Set low power mode */\n\n#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR\t0x0000 /* PMA/PMD Control Reg */\n#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR\t0xC30A /* PHY_XS SDA/SCL Addr Reg */\n#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA\t0xC30B /* PHY_XS SDA/SCL Data Reg */\n#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT\t0xC30C /* PHY_XS SDA/SCL Status Reg */\n\n/* MII clause 22/28 definitions */\n#define IXGBE_MDIO_PHY_LOW_POWER_MODE\t0x0800\n\n#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG\t0x20 /* 10G Control Reg */\n#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */\n#define IXGBE_MII_AUTONEG_XNP_TX_REG\t\t0x17 /* 1G XNP Transmit */\n#define IXGBE_MII_AUTONEG_ADVERTISE_REG\t\t0x10 /* 100M Advertisement */\n#define IXGBE_MII_10GBASE_T_ADVERTISE\t\t0x1000 /* full duplex, bit:12*/\n#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX\t0x4000 /* full duplex, bit:14*/\n#define IXGBE_MII_1GBASE_T_ADVERTISE\t\t0x8000 /* full duplex, bit:15*/\n#define IXGBE_MII_100BASE_T_ADVERTISE\t\t0x0100 /* full duplex, bit:8 */\n#define IXGBE_MII_100BASE_T_ADVERTISE_HALF\t0x0080 /* half duplex, bit:7 */\n#define IXGBE_MII_RESTART\t\t\t0x200\n#define IXGBE_MII_AUTONEG_COMPLETE\t\t0x20\n#define IXGBE_MII_AUTONEG_LINK_UP\t\t0x04\n#define IXGBE_MII_AUTONEG_REG\t\t\t0x0\n\n#define IXGBE_PHY_REVISION_MASK\t\t0xFFFFFFF0\n#define IXGBE_MAX_PHY_ADDR\t\t32\n\n/* PHY IDs*/\n#define TN1010_PHY_ID\t0x00A19410\n#define TNX_FW_REV\t0xB\n#define X540_PHY_ID\t0x01540200\n#define AQ_FW_REV\t0x20\n#define QT2022_PHY_ID\t0x0043A400\n#define ATH_PHY_ID\t0x03429050\n\n/* PHY Types */\n#define IXGBE_M88E1145_E_PHY_ID\t0x01410CD0\n\n/* Special PHY Init Routine */\n#define IXGBE_PHY_INIT_OFFSET_NL\t0x002B\n#define IXGBE_PHY_INIT_END_NL\t\t0xFFFF\n#define IXGBE_CONTROL_MASK_NL\t\t0xF000\n#define IXGBE_DATA_MASK_NL\t\t0x0FFF\n#define IXGBE_CONTROL_SHIFT_NL\t\t12\n#define IXGBE_DELAY_NL\t\t\t0\n#define IXGBE_DATA_NL\t\t\t1\n#define IXGBE_CONTROL_NL\t\t0x000F\n#define IXGBE_CONTROL_EOL_NL\t\t0x0FFF\n#define IXGBE_CONTROL_SOL_NL\t\t0x0000\n\n/* General purpose Interrupt Enable */\n#define IXGBE_SDP0_GPIEN\t0x00000001 /* SDP0 */\n#define IXGBE_SDP1_GPIEN\t0x00000002 /* SDP1 */\n#define IXGBE_SDP2_GPIEN\t0x00000004 /* SDP2 */\n#define IXGBE_GPIE_MSIX_MODE\t0x00000010 /* MSI-X mode */\n#define IXGBE_GPIE_OCD\t\t0x00000020 /* Other Clear Disable */\n#define IXGBE_GPIE_EIMEN\t0x00000040 /* Immediate Interrupt Enable */\n#define IXGBE_GPIE_EIAME\t0x40000000\n#define IXGBE_GPIE_PBA_SUPPORT\t0x80000000\n#define IXGBE_GPIE_RSC_DELAY_SHIFT\t11\n#define IXGBE_GPIE_VTMODE_MASK\t0x0000C000 /* VT Mode Mask */\n#define IXGBE_GPIE_VTMODE_16\t0x00004000 /* 16 VFs 8 queues per VF */\n#define IXGBE_GPIE_VTMODE_32\t0x00008000 /* 32 VFs 4 queues per VF */\n#define IXGBE_GPIE_VTMODE_64\t0x0000C000 /* 64 VFs 2 queues per VF */\n\n/* Packet Buffer Initialization */\n#define IXGBE_MAX_PACKET_BUFFERS\t8\n\n#define IXGBE_TXPBSIZE_20KB\t0x00005000 /* 20KB Packet Buffer */\n#define IXGBE_TXPBSIZE_40KB\t0x0000A000 /* 40KB Packet Buffer */\n#define IXGBE_RXPBSIZE_48KB\t0x0000C000 /* 48KB Packet Buffer */\n#define IXGBE_RXPBSIZE_64KB\t0x00010000 /* 64KB Packet Buffer */\n#define IXGBE_RXPBSIZE_80KB\t0x00014000 /* 80KB Packet Buffer */\n#define IXGBE_RXPBSIZE_128KB\t0x00020000 /* 128KB Packet Buffer */\n#define IXGBE_RXPBSIZE_MAX\t0x00080000 /* 512KB Packet Buffer */\n#define IXGBE_TXPBSIZE_MAX\t0x00028000 /* 160KB Packet Buffer */\n\n#define IXGBE_TXPKT_SIZE_MAX\t0xA /* Max Tx Packet size */\n#define IXGBE_MAX_PB\t\t8\n\n/* Packet buffer allocation strategies */\nenum {\n\tPBA_STRATEGY_EQUAL\t= 0, /* Distribute PB space equally */\n#define PBA_STRATEGY_EQUAL\tPBA_STRATEGY_EQUAL\n\tPBA_STRATEGY_WEIGHTED\t= 1, /* Weight front half of TCs */\n#define PBA_STRATEGY_WEIGHTED\tPBA_STRATEGY_WEIGHTED\n};\n\n/* Transmit Flow Control status */\n#define IXGBE_TFCS_TXOFF\t0x00000001\n#define IXGBE_TFCS_TXOFF0\t0x00000100\n#define IXGBE_TFCS_TXOFF1\t0x00000200\n#define IXGBE_TFCS_TXOFF2\t0x00000400\n#define IXGBE_TFCS_TXOFF3\t0x00000800\n#define IXGBE_TFCS_TXOFF4\t0x00001000\n#define IXGBE_TFCS_TXOFF5\t0x00002000\n#define IXGBE_TFCS_TXOFF6\t0x00004000\n#define IXGBE_TFCS_TXOFF7\t0x00008000\n\n/* TCP Timer */\n#define IXGBE_TCPTIMER_KS\t\t0x00000100\n#define IXGBE_TCPTIMER_COUNT_ENABLE\t0x00000200\n#define IXGBE_TCPTIMER_COUNT_FINISH\t0x00000400\n#define IXGBE_TCPTIMER_LOOP\t\t0x00000800\n#define IXGBE_TCPTIMER_DURATION_MASK\t0x000000FF\n\n/* HLREG0 Bit Masks */\n#define IXGBE_HLREG0_TXCRCEN\t\t0x00000001 /* bit 0 */\n#define IXGBE_HLREG0_RXCRCSTRP\t\t0x00000002 /* bit 1 */\n#define IXGBE_HLREG0_JUMBOEN\t\t0x00000004 /* bit 2 */\n#define IXGBE_HLREG0_TXPADEN\t\t0x00000400 /* bit 10 */\n#define IXGBE_HLREG0_TXPAUSEEN\t\t0x00001000 /* bit 12 */\n#define IXGBE_HLREG0_RXPAUSEEN\t\t0x00004000 /* bit 14 */\n#define IXGBE_HLREG0_LPBK\t\t0x00008000 /* bit 15 */\n#define IXGBE_HLREG0_MDCSPD\t\t0x00010000 /* bit 16 */\n#define IXGBE_HLREG0_CONTMDC\t\t0x00020000 /* bit 17 */\n#define IXGBE_HLREG0_CTRLFLTR\t\t0x00040000 /* bit 18 */\n#define IXGBE_HLREG0_PREPEND\t\t0x00F00000 /* bits 20-23 */\n#define IXGBE_HLREG0_PRIPAUSEEN\t\t0x01000000 /* bit 24 */\n#define IXGBE_HLREG0_RXPAUSERECDA\t0x06000000 /* bits 25-26 */\n#define IXGBE_HLREG0_RXLNGTHERREN\t0x08000000 /* bit 27 */\n#define IXGBE_HLREG0_RXPADSTRIPEN\t0x10000000 /* bit 28 */\n\n/* VMD_CTL bitmasks */\n#define IXGBE_VMD_CTL_VMDQ_EN\t\t0x00000001\n#define IXGBE_VMD_CTL_VMDQ_FILTER\t0x00000002\n\n/* VT_CTL bitmasks */\n#define IXGBE_VT_CTL_DIS_DEFPL\t\t0x20000000 /* disable default pool */\n#define IXGBE_VT_CTL_REPLEN\t\t0x40000000 /* replication enabled */\n#define IXGBE_VT_CTL_VT_ENABLE\t\t0x00000001 /* Enable VT Mode */\n#define IXGBE_VT_CTL_POOL_SHIFT\t\t7\n#define IXGBE_VT_CTL_POOL_MASK\t\t(0x3F << IXGBE_VT_CTL_POOL_SHIFT)\n\n/* VMOLR bitmasks */\n#define IXGBE_VMOLR_AUPE\t0x01000000 /* accept untagged packets */\n#define IXGBE_VMOLR_ROMPE\t0x02000000 /* accept packets in MTA tbl */\n#define IXGBE_VMOLR_ROPE\t0x04000000 /* accept packets in UC tbl */\n#define IXGBE_VMOLR_BAM\t\t0x08000000 /* accept broadcast packets */\n#define IXGBE_VMOLR_MPE\t\t0x10000000 /* multicast promiscuous */\n\n/* VFRE bitmask */\n#define IXGBE_VFRE_ENABLE_ALL\t0xFFFFFFFF\n\n#define IXGBE_VF_INIT_TIMEOUT\t200 /* Number of retries to clear RSTI */\n\n/* RDHMPN and TDHMPN bitmasks */\n#define IXGBE_RDHMPN_RDICADDR\t\t0x007FF800\n#define IXGBE_RDHMPN_RDICRDREQ\t\t0x00800000\n#define IXGBE_RDHMPN_RDICADDR_SHIFT\t11\n#define IXGBE_TDHMPN_TDICADDR\t\t0x003FF800\n#define IXGBE_TDHMPN_TDICRDREQ\t\t0x00800000\n#define IXGBE_TDHMPN_TDICADDR_SHIFT\t11\n\n#define IXGBE_RDMAM_MEM_SEL_SHIFT\t\t13\n#define IXGBE_RDMAM_DWORD_SHIFT\t\t\t9\n#define IXGBE_RDMAM_DESC_COMP_FIFO\t\t1\n#define IXGBE_RDMAM_DFC_CMD_FIFO\t\t2\n#define IXGBE_RDMAM_RSC_HEADER_ADDR\t\t3\n#define IXGBE_RDMAM_TCN_STATUS_RAM\t\t4\n#define IXGBE_RDMAM_WB_COLL_FIFO\t\t5\n#define IXGBE_RDMAM_QSC_CNT_RAM\t\t\t6\n#define IXGBE_RDMAM_QSC_FCOE_RAM\t\t7\n#define IXGBE_RDMAM_QSC_QUEUE_CNT\t\t8\n#define IXGBE_RDMAM_QSC_QUEUE_RAM\t\t0xA\n#define IXGBE_RDMAM_QSC_RSC_RAM\t\t\t0xB\n#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE\t\t135\n#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT\t\t4\n#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE\t\t48\n#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT\t\t7\n#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE\t32\n#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT\t4\n#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE\t256\n#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT\t9\n#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE\t\t8\n#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT\t\t4\n#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE\t\t64\n#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT\t\t4\n#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE\t\t512\n#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT\t\t5\n#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE\t\t32\n#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT\t\t4\n#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE\t\t128\n#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT\t\t8\n#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE\t\t32\n#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT\t\t8\n\n#define IXGBE_TXDESCIC_READY\t0x80000000\n\n/* Receive Checksum Control */\n#define IXGBE_RXCSUM_IPPCSE\t0x00001000 /* IP payload checksum enable */\n#define IXGBE_RXCSUM_PCSD\t0x00002000 /* packet checksum disabled */\n\n/* FCRTL Bit Masks */\n#define IXGBE_FCRTL_XONE\t0x80000000 /* XON enable */\n#define IXGBE_FCRTH_FCEN\t0x80000000 /* Packet buffer fc enable */\n\n/* PAP bit masks*/\n#define IXGBE_PAP_TXPAUSECNT_MASK\t0x0000FFFF /* Pause counter mask */\n\n/* RMCS Bit Masks */\n#define IXGBE_RMCS_RRM\t\t\t0x00000002 /* Rx Recycle Mode enable */\n/* Receive Arbitration Control: 0 Round Robin, 1 DFP */\n#define IXGBE_RMCS_RAC\t\t\t0x00000004\n/* Deficit Fixed Prio ena */\n#define IXGBE_RMCS_DFP\t\t\tIXGBE_RMCS_RAC\n#define IXGBE_RMCS_TFCE_802_3X\t\t0x00000008 /* Tx Priority FC ena */\n#define IXGBE_RMCS_TFCE_PRIORITY\t0x00000010 /* Tx Priority FC ena */\n#define IXGBE_RMCS_ARBDIS\t\t0x00000040 /* Arbitration disable bit */\n\n/* FCCFG Bit Masks */\n#define IXGBE_FCCFG_TFCE_802_3X\t\t0x00000008 /* Tx link FC enable */\n#define IXGBE_FCCFG_TFCE_PRIORITY\t0x00000010 /* Tx priority FC enable */\n\n/* Interrupt register bitmasks */\n\n/* Extended Interrupt Cause Read */\n#define IXGBE_EICR_RTX_QUEUE\t0x0000FFFF /* RTx Queue Interrupt */\n#define IXGBE_EICR_FLOW_DIR\t0x00010000 /* FDir Exception */\n#define IXGBE_EICR_RX_MISS\t0x00020000 /* Packet Buffer Overrun */\n#define IXGBE_EICR_PCI\t\t0x00040000 /* PCI Exception */\n#define IXGBE_EICR_MAILBOX\t0x00080000 /* VF to PF Mailbox Interrupt */\n#define IXGBE_EICR_LSC\t\t0x00100000 /* Link Status Change */\n#define IXGBE_EICR_LINKSEC\t0x00200000 /* PN Threshold */\n#define IXGBE_EICR_MNG\t\t0x00400000 /* Manageability Event Interrupt */\n#define IXGBE_EICR_TS\t\t0x00800000 /* Thermal Sensor Event */\n#define IXGBE_EICR_GPI_SDP0\t0x01000000 /* Gen Purpose Interrupt on SDP0 */\n#define IXGBE_EICR_GPI_SDP1\t0x02000000 /* Gen Purpose Interrupt on SDP1 */\n#define IXGBE_EICR_GPI_SDP2\t0x04000000 /* Gen Purpose Interrupt on SDP2 */\n#define IXGBE_EICR_ECC\t\t0x10000000 /* ECC Error */\n#define IXGBE_EICR_PBUR\t\t0x10000000 /* Packet Buffer Handler Error */\n#define IXGBE_EICR_DHER\t\t0x20000000 /* Descriptor Handler Error */\n#define IXGBE_EICR_TCP_TIMER\t0x40000000 /* TCP Timer */\n#define IXGBE_EICR_OTHER\t0x80000000 /* Interrupt Cause Active */\n\n/* Extended Interrupt Cause Set */\n#define IXGBE_EICS_RTX_QUEUE\tIXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */\n#define IXGBE_EICS_FLOW_DIR\tIXGBE_EICR_FLOW_DIR /* FDir Exception */\n#define IXGBE_EICS_RX_MISS\tIXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */\n#define IXGBE_EICS_PCI\t\tIXGBE_EICR_PCI /* PCI Exception */\n#define IXGBE_EICS_MAILBOX\tIXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */\n#define IXGBE_EICS_LSC\t\tIXGBE_EICR_LSC /* Link Status Change */\n#define IXGBE_EICS_MNG\t\tIXGBE_EICR_MNG /* MNG Event Interrupt */\n#define IXGBE_EICS_GPI_SDP0\tIXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */\n#define IXGBE_EICS_GPI_SDP1\tIXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */\n#define IXGBE_EICS_GPI_SDP2\tIXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */\n#define IXGBE_EICS_ECC\t\tIXGBE_EICR_ECC /* ECC Error */\n#define IXGBE_EICS_PBUR\t\tIXGBE_EICR_PBUR /* Pkt Buf Handler Err */\n#define IXGBE_EICS_DHER\t\tIXGBE_EICR_DHER /* Desc Handler Error */\n#define IXGBE_EICS_TCP_TIMER\tIXGBE_EICR_TCP_TIMER /* TCP Timer */\n#define IXGBE_EICS_OTHER\tIXGBE_EICR_OTHER /* INT Cause Active */\n\n/* Extended Interrupt Mask Set */\n#define IXGBE_EIMS_RTX_QUEUE\tIXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */\n#define IXGBE_EIMS_FLOW_DIR\tIXGBE_EICR_FLOW_DIR /* FDir Exception */\n#define IXGBE_EIMS_RX_MISS\tIXGBE_EICR_RX_MISS /* Packet Buffer Overrun */\n#define IXGBE_EIMS_PCI\t\tIXGBE_EICR_PCI /* PCI Exception */\n#define IXGBE_EIMS_MAILBOX\tIXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */\n#define IXGBE_EIMS_LSC\t\tIXGBE_EICR_LSC /* Link Status Change */\n#define IXGBE_EIMS_MNG\t\tIXGBE_EICR_MNG /* MNG Event Interrupt */\n#define IXGBE_EIMS_TS\t\tIXGBE_EICR_TS /* Thermal Sensor Event */\n#define IXGBE_EIMS_GPI_SDP0\tIXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */\n#define IXGBE_EIMS_GPI_SDP1\tIXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */\n#define IXGBE_EIMS_GPI_SDP2\tIXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */\n#define IXGBE_EIMS_ECC\t\tIXGBE_EICR_ECC /* ECC Error */\n#define IXGBE_EIMS_PBUR\t\tIXGBE_EICR_PBUR /* Pkt Buf Handler Err */\n#define IXGBE_EIMS_DHER\t\tIXGBE_EICR_DHER /* Descr Handler Error */\n#define IXGBE_EIMS_TCP_TIMER\tIXGBE_EICR_TCP_TIMER /* TCP Timer */\n#define IXGBE_EIMS_OTHER\tIXGBE_EICR_OTHER /* INT Cause Active */\n\n/* Extended Interrupt Mask Clear */\n#define IXGBE_EIMC_RTX_QUEUE\tIXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */\n#define IXGBE_EIMC_FLOW_DIR\tIXGBE_EICR_FLOW_DIR /* FDir Exception */\n#define IXGBE_EIMC_RX_MISS\tIXGBE_EICR_RX_MISS /* Packet Buffer Overrun */\n#define IXGBE_EIMC_PCI\t\tIXGBE_EICR_PCI /* PCI Exception */\n#define IXGBE_EIMC_MAILBOX\tIXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */\n#define IXGBE_EIMC_LSC\t\tIXGBE_EICR_LSC /* Link Status Change */\n#define IXGBE_EIMC_MNG\t\tIXGBE_EICR_MNG /* MNG Event Interrupt */\n#define IXGBE_EIMC_GPI_SDP0\tIXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */\n#define IXGBE_EIMC_GPI_SDP1\tIXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */\n#define IXGBE_EIMC_GPI_SDP2\tIXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */\n#define IXGBE_EIMC_ECC\t\tIXGBE_EICR_ECC /* ECC Error */\n#define IXGBE_EIMC_PBUR\t\tIXGBE_EICR_PBUR /* Pkt Buf Handler Err */\n#define IXGBE_EIMC_DHER\t\tIXGBE_EICR_DHER /* Desc Handler Err */\n#define IXGBE_EIMC_TCP_TIMER\tIXGBE_EICR_TCP_TIMER /* TCP Timer */\n#define IXGBE_EIMC_OTHER\tIXGBE_EICR_OTHER /* INT Cause Active */\n\n#define IXGBE_EIMS_ENABLE_MASK ( \\\n\t\t\t\tIXGBE_EIMS_RTX_QUEUE\t| \\\n\t\t\t\tIXGBE_EIMS_LSC\t\t| \\\n\t\t\t\tIXGBE_EIMS_TCP_TIMER\t| \\\n\t\t\t\tIXGBE_EIMS_OTHER)\n\n/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */\n#define IXGBE_IMIR_PORT_IM_EN\t0x00010000 /* TCP port enable */\n#define IXGBE_IMIR_PORT_BP\t0x00020000 /* TCP port check bypass */\n#define IXGBE_IMIREXT_SIZE_BP\t0x00001000 /* Packet size bypass */\n#define IXGBE_IMIREXT_CTRL_URG\t0x00002000 /* Check URG bit in header */\n#define IXGBE_IMIREXT_CTRL_ACK\t0x00004000 /* Check ACK bit in header */\n#define IXGBE_IMIREXT_CTRL_PSH\t0x00008000 /* Check PSH bit in header */\n#define IXGBE_IMIREXT_CTRL_RST\t0x00010000 /* Check RST bit in header */\n#define IXGBE_IMIREXT_CTRL_SYN\t0x00020000 /* Check SYN bit in header */\n#define IXGBE_IMIREXT_CTRL_FIN\t0x00040000 /* Check FIN bit in header */\n#define IXGBE_IMIREXT_CTRL_BP\t0x00080000 /* Bypass check of control bits */\n#define IXGBE_IMIR_SIZE_BP_82599\t0x00001000 /* Packet size bypass */\n#define IXGBE_IMIR_CTRL_URG_82599\t0x00002000 /* Check URG bit in header */\n#define IXGBE_IMIR_CTRL_ACK_82599\t0x00004000 /* Check ACK bit in header */\n#define IXGBE_IMIR_CTRL_PSH_82599\t0x00008000 /* Check PSH bit in header */\n#define IXGBE_IMIR_CTRL_RST_82599\t0x00010000 /* Check RST bit in header */\n#define IXGBE_IMIR_CTRL_SYN_82599\t0x00020000 /* Check SYN bit in header */\n#define IXGBE_IMIR_CTRL_FIN_82599\t0x00040000 /* Check FIN bit in header */\n#define IXGBE_IMIR_CTRL_BP_82599\t0x00080000 /* Bypass chk of ctrl bits */\n#define IXGBE_IMIR_LLI_EN_82599\t\t0x00100000 /* Enables low latency Int */\n#define IXGBE_IMIR_RX_QUEUE_MASK_82599\t0x0000007F /* Rx Queue Mask */\n#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599\t21 /* Rx Queue Shift */\n#define IXGBE_IMIRVP_PRIORITY_MASK\t0x00000007 /* VLAN priority mask */\n#define IXGBE_IMIRVP_PRIORITY_EN\t0x00000008 /* VLAN priority enable */\n\n#define IXGBE_MAX_FTQF_FILTERS\t\t128\n#define IXGBE_FTQF_PROTOCOL_MASK\t0x00000003\n#define IXGBE_FTQF_PROTOCOL_TCP\t\t0x00000000\n#define IXGBE_FTQF_PROTOCOL_UDP\t\t0x00000001\n#define IXGBE_FTQF_PROTOCOL_SCTP\t2\n#define IXGBE_FTQF_PRIORITY_MASK\t0x00000007\n#define IXGBE_FTQF_PRIORITY_SHIFT\t2\n#define IXGBE_FTQF_POOL_MASK\t\t0x0000003F\n#define IXGBE_FTQF_POOL_SHIFT\t\t8\n#define IXGBE_FTQF_5TUPLE_MASK_MASK\t0x0000001F\n#define IXGBE_FTQF_5TUPLE_MASK_SHIFT\t25\n#define IXGBE_FTQF_SOURCE_ADDR_MASK\t0x1E\n#define IXGBE_FTQF_DEST_ADDR_MASK\t0x1D\n#define IXGBE_FTQF_SOURCE_PORT_MASK\t0x1B\n#define IXGBE_FTQF_DEST_PORT_MASK\t0x17\n#define IXGBE_FTQF_PROTOCOL_COMP_MASK\t0x0F\n#define IXGBE_FTQF_POOL_MASK_EN\t\t0x40000000\n#define IXGBE_FTQF_QUEUE_ENABLE\t\t0x80000000\n\n/* Interrupt clear mask */\n#define IXGBE_IRQ_CLEAR_MASK\t0xFFFFFFFF\n\n/* Interrupt Vector Allocation Registers */\n#define IXGBE_IVAR_REG_NUM\t\t25\n#define IXGBE_IVAR_REG_NUM_82599\t64\n#define IXGBE_IVAR_TXRX_ENTRY\t\t96\n#define IXGBE_IVAR_RX_ENTRY\t\t64\n#define IXGBE_IVAR_RX_QUEUE(_i)\t\t(0 + (_i))\n#define IXGBE_IVAR_TX_QUEUE(_i)\t\t(64 + (_i))\n#define IXGBE_IVAR_TX_ENTRY\t\t32\n\n#define IXGBE_IVAR_TCP_TIMER_INDEX\t96 /* 0 based index */\n#define IXGBE_IVAR_OTHER_CAUSES_INDEX\t97 /* 0 based index */\n\n#define IXGBE_MSIX_VECTOR(_i)\t\t(0 + (_i))\n\n#define IXGBE_IVAR_ALLOC_VAL\t\t0x80 /* Interrupt Allocation valid */\n\n/* ETYPE Queue Filter/Select Bit Masks */\n#define IXGBE_MAX_ETQF_FILTERS\t\t8\n#define IXGBE_ETQF_FCOE\t\t\t0x08000000 /* bit 27 */\n#define IXGBE_ETQF_BCN\t\t\t0x10000000 /* bit 28 */\n#define IXGBE_ETQF_1588\t\t\t0x40000000 /* bit 30 */\n#define IXGBE_ETQF_FILTER_EN\t\t0x80000000 /* bit 31 */\n#define IXGBE_ETQF_POOL_ENABLE\t\t(1 << 26) /* bit 26 */\n\n#define IXGBE_ETQS_RX_QUEUE\t\t0x007F0000 /* bits 22:16 */\n#define IXGBE_ETQS_RX_QUEUE_SHIFT\t16\n#define IXGBE_ETQS_LLI\t\t\t0x20000000 /* bit 29 */\n#define IXGBE_ETQS_QUEUE_EN\t\t0x80000000 /* bit 31 */\n\n/*\n * ETQF filter list: one static filter per filter consumer. This is\n *\t\t to avoid filter collisions later. Add new filters\n *\t\t here!!\n *\n * Current filters:\n *\tEAPOL 802.1x (0x888e): Filter 0\n *\tFCoE (0x8906):\t Filter 2\n *\t1588 (0x88f7):\t Filter 3\n *\tFIP (0x8914):\t Filter 4\n */\n#define IXGBE_ETQF_FILTER_EAPOL\t\t0\n#define IXGBE_ETQF_FILTER_FCOE\t\t2\n#define IXGBE_ETQF_FILTER_1588\t\t3\n#define IXGBE_ETQF_FILTER_FIP\t\t4\n/* VLAN Control Bit Masks */\n#define IXGBE_VLNCTRL_VET\t\t0x0000FFFF /* bits 0-15 */\n#define IXGBE_VLNCTRL_CFI\t\t0x10000000 /* bit 28 */\n#define IXGBE_VLNCTRL_CFIEN\t\t0x20000000 /* bit 29 */\n#define IXGBE_VLNCTRL_VFE\t\t0x40000000 /* bit 30 */\n#define IXGBE_VLNCTRL_VME\t\t0x80000000 /* bit 31 */\n\n/* VLAN pool filtering masks */\n#define IXGBE_VLVF_VIEN\t\t\t0x80000000 /* filter is valid */\n#define IXGBE_VLVF_ENTRIES\t\t64\n#define IXGBE_VLVF_VLANID_MASK\t\t0x00000FFF\n/* Per VF Port VLAN insertion rules */\n#define IXGBE_VMVIR_VLANA_DEFAULT\t0x40000000 /* Always use default VLAN */\n#define IXGBE_VMVIR_VLANA_NEVER\t\t0x80000000 /* Never insert VLAN tag */\n\n#define IXGBE_ETHERNET_IEEE_VLAN_TYPE\t0x8100 /* 802.1q protocol */\n\n/* STATUS Bit Masks */\n#define IXGBE_STATUS_LAN_ID\t\t0x0000000C /* LAN ID */\n#define IXGBE_STATUS_LAN_ID_SHIFT\t2 /* LAN ID Shift*/\n#define IXGBE_STATUS_GIO\t\t0x00080000 /* GIO Master Ena Status */\n\n#define IXGBE_STATUS_LAN_ID_0\t0x00000000 /* LAN ID 0 */\n#define IXGBE_STATUS_LAN_ID_1\t0x00000004 /* LAN ID 1 */\n\n/* ESDP Bit Masks */\n#define IXGBE_ESDP_SDP0\t\t0x00000001 /* SDP0 Data Value */\n#define IXGBE_ESDP_SDP1\t\t0x00000002 /* SDP1 Data Value */\n#define IXGBE_ESDP_SDP2\t\t0x00000004 /* SDP2 Data Value */\n#define IXGBE_ESDP_SDP3\t\t0x00000008 /* SDP3 Data Value */\n#define IXGBE_ESDP_SDP4\t\t0x00000010 /* SDP4 Data Value */\n#define IXGBE_ESDP_SDP5\t\t0x00000020 /* SDP5 Data Value */\n#define IXGBE_ESDP_SDP6\t\t0x00000040 /* SDP6 Data Value */\n#define IXGBE_ESDP_SDP0_DIR\t0x00000100 /* SDP0 IO direction */\n#define IXGBE_ESDP_SDP1_DIR\t0x00000200 /* SDP1 IO direction */\n#define IXGBE_ESDP_SDP4_DIR\t0x00001000 /* SDP4 IO direction */\n#define IXGBE_ESDP_SDP5_DIR\t0x00002000 /* SDP5 IO direction */\n#define IXGBE_ESDP_SDP0_NATIVE\t0x00010000 /* SDP0 IO mode */\n#define IXGBE_ESDP_SDP1_NATIVE\t0x00020000 /* SDP1 IO mode */\n\n\n/* LEDCTL Bit Masks */\n#define IXGBE_LED_IVRT_BASE\t\t0x00000040\n#define IXGBE_LED_BLINK_BASE\t\t0x00000080\n#define IXGBE_LED_MODE_MASK_BASE\t0x0000000F\n#define IXGBE_LED_OFFSET(_base, _i)\t(_base << (8 * (_i)))\n#define IXGBE_LED_MODE_SHIFT(_i)\t(8*(_i))\n#define IXGBE_LED_IVRT(_i)\tIXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)\n#define IXGBE_LED_BLINK(_i)\tIXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)\n#define IXGBE_LED_MODE_MASK(_i)\tIXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)\n\n/* LED modes */\n#define IXGBE_LED_LINK_UP\t0x0\n#define IXGBE_LED_LINK_10G\t0x1\n#define IXGBE_LED_MAC\t\t0x2\n#define IXGBE_LED_FILTER\t0x3\n#define IXGBE_LED_LINK_ACTIVE\t0x4\n#define IXGBE_LED_LINK_1G\t0x5\n#define IXGBE_LED_ON\t\t0xE\n#define IXGBE_LED_OFF\t\t0xF\n\n/* AUTOC Bit Masks */\n#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000\n#define IXGBE_AUTOC_KX4_SUPP\t0x80000000\n#define IXGBE_AUTOC_KX_SUPP\t0x40000000\n#define IXGBE_AUTOC_PAUSE\t0x30000000\n#define IXGBE_AUTOC_ASM_PAUSE\t0x20000000\n#define IXGBE_AUTOC_SYM_PAUSE\t0x10000000\n#define IXGBE_AUTOC_RF\t\t0x08000000\n#define IXGBE_AUTOC_PD_TMR\t0x06000000\n#define IXGBE_AUTOC_AN_RX_LOOSE\t0x01000000\n#define IXGBE_AUTOC_AN_RX_DRIFT\t0x00800000\n#define IXGBE_AUTOC_AN_RX_ALIGN\t0x007C0000\n#define IXGBE_AUTOC_FECA\t0x00040000\n#define IXGBE_AUTOC_FECR\t0x00020000\n#define IXGBE_AUTOC_KR_SUPP\t0x00010000\n#define IXGBE_AUTOC_AN_RESTART\t0x00001000\n#define IXGBE_AUTOC_FLU\t\t0x00000001\n#define IXGBE_AUTOC_LMS_SHIFT\t13\n#define IXGBE_AUTOC_LMS_10G_SERIAL\t(0x3 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_KX4_KX_KR\t(0x4 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_SGMII_1G_100M\t(0x5 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN\t(0x6 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII\t(0x7 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_MASK\t\t(0x7 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN\t(0x0 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN\t(0x1 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_1G_AN\t\t(0x2 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_KX4_AN\t\t(0x4 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN\t(0x6 << IXGBE_AUTOC_LMS_SHIFT)\n#define IXGBE_AUTOC_LMS_ATTACH_TYPE\t(0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)\n\n#define IXGBE_AUTOC_1G_PMA_PMD_MASK\t0x00000200\n#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT\t9\n#define IXGBE_AUTOC_10G_PMA_PMD_MASK\t0x00000180\n#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT\t7\n#define IXGBE_AUTOC_10G_XAUI\t(0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC_10G_KX4\t(0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC_10G_CX4\t(0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC_1G_BX\t(0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC_1G_KX\t(0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC_1G_SFI\t(0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC_1G_KX_BX\t(0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)\n\n#define IXGBE_AUTOC2_UPPER_MASK\t0xFFFF0000\n#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK\t0x00030000\n#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT\t16\n#define IXGBE_AUTOC2_10G_KR\t(0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC2_10G_XFI\t(0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)\n#define IXGBE_AUTOC2_10G_SFI\t(0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)\n\n#define IXGBE_MACC_FLU\t\t0x00000001\n#define IXGBE_MACC_FSV_10G\t0x00030000\n#define IXGBE_MACC_FS\t\t0x00040000\n#define IXGBE_MAC_RX2TX_LPBK\t0x00000002\n\n/* LINKS Bit Masks */\n#define IXGBE_LINKS_KX_AN_COMP\t0x80000000\n#define IXGBE_LINKS_UP\t\t0x40000000\n#define IXGBE_LINKS_SPEED\t0x20000000\n#define IXGBE_LINKS_MODE\t0x18000000\n#define IXGBE_LINKS_RX_MODE\t0x06000000\n#define IXGBE_LINKS_TX_MODE\t0x01800000\n#define IXGBE_LINKS_XGXS_EN\t0x00400000\n#define IXGBE_LINKS_SGMII_EN\t0x02000000\n#define IXGBE_LINKS_PCS_1G_EN\t0x00200000\n#define IXGBE_LINKS_1G_AN_EN\t0x00100000\n#define IXGBE_LINKS_KX_AN_IDLE\t0x00080000\n#define IXGBE_LINKS_1G_SYNC\t0x00040000\n#define IXGBE_LINKS_10G_ALIGN\t0x00020000\n#define IXGBE_LINKS_10G_LANE_SYNC\t0x00017000\n#define IXGBE_LINKS_TL_FAULT\t\t0x00001000\n#define IXGBE_LINKS_SIGNAL\t\t0x00000F00\n\n#define IXGBE_LINKS_SPEED_82599\t\t0x30000000\n#define IXGBE_LINKS_SPEED_10G_82599\t0x30000000\n#define IXGBE_LINKS_SPEED_1G_82599\t0x20000000\n#define IXGBE_LINKS_SPEED_100_82599\t0x10000000\n#define IXGBE_LINK_UP_TIME\t\t90 /* 9.0 Seconds */\n#define IXGBE_AUTO_NEG_TIME\t\t45 /* 4.5 Seconds */\n\n#define IXGBE_LINKS2_AN_SUPPORTED\t0x00000040\n\n/* PCS1GLSTA Bit Masks */\n#define IXGBE_PCS1GLSTA_LINK_OK\t\t1\n#define IXGBE_PCS1GLSTA_SYNK_OK\t\t0x10\n#define IXGBE_PCS1GLSTA_AN_COMPLETE\t0x10000\n#define IXGBE_PCS1GLSTA_AN_PAGE_RX\t0x20000\n#define IXGBE_PCS1GLSTA_AN_TIMED_OUT\t0x40000\n#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT\t0x80000\n#define IXGBE_PCS1GLSTA_AN_ERROR_RWS\t0x100000\n\n#define IXGBE_PCS1GANA_SYM_PAUSE\t0x80\n#define IXGBE_PCS1GANA_ASM_PAUSE\t0x100\n\n/* PCS1GLCTL Bit Masks */\n#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */\n#define IXGBE_PCS1GLCTL_FLV_LINK_UP\t1\n#define IXGBE_PCS1GLCTL_FORCE_LINK\t0x20\n#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH\t0x40\n#define IXGBE_PCS1GLCTL_AN_ENABLE\t0x10000\n#define IXGBE_PCS1GLCTL_AN_RESTART\t0x20000\n\n/* ANLP1 Bit Masks */\n#define IXGBE_ANLP1_PAUSE\t\t0x0C00\n#define IXGBE_ANLP1_SYM_PAUSE\t\t0x0400\n#define IXGBE_ANLP1_ASM_PAUSE\t\t0x0800\n#define IXGBE_ANLP1_AN_STATE_MASK\t0x000f0000\n\n/* SW Semaphore Register bitmasks */\n#define IXGBE_SWSM_SMBI\t\t0x00000001 /* Driver Semaphore bit */\n#define IXGBE_SWSM_SWESMBI\t0x00000002 /* FW Semaphore bit */\n#define IXGBE_SWSM_WMNG\t\t0x00000004 /* Wake MNG Clock */\n#define IXGBE_SWFW_REGSMP\t0x80000000 /* Register Semaphore bit 31 */\n\n/* SW_FW_SYNC/GSSR definitions */\n#define IXGBE_GSSR_EEP_SM\t0x0001\n#define IXGBE_GSSR_PHY0_SM\t0x0002\n#define IXGBE_GSSR_PHY1_SM\t0x0004\n#define IXGBE_GSSR_MAC_CSR_SM\t0x0008\n#define IXGBE_GSSR_FLASH_SM\t0x0010\n#define IXGBE_GSSR_SW_MNG_SM\t0x0400\n\n/* FW Status register bitmask */\n#define IXGBE_FWSTS_FWRI\t0x00000200 /* Firmware Reset Indication */\n\n/* EEC Register */\n#define IXGBE_EEC_SK\t\t0x00000001 /* EEPROM Clock */\n#define IXGBE_EEC_CS\t\t0x00000002 /* EEPROM Chip Select */\n#define IXGBE_EEC_DI\t\t0x00000004 /* EEPROM Data In */\n#define IXGBE_EEC_DO\t\t0x00000008 /* EEPROM Data Out */\n#define IXGBE_EEC_FWE_MASK\t0x00000030 /* FLASH Write Enable */\n#define IXGBE_EEC_FWE_DIS\t0x00000010 /* Disable FLASH writes */\n#define IXGBE_EEC_FWE_EN\t0x00000020 /* Enable FLASH writes */\n#define IXGBE_EEC_FWE_SHIFT\t4\n#define IXGBE_EEC_REQ\t\t0x00000040 /* EEPROM Access Request */\n#define IXGBE_EEC_GNT\t\t0x00000080 /* EEPROM Access Grant */\n#define IXGBE_EEC_PRES\t\t0x00000100 /* EEPROM Present */\n#define IXGBE_EEC_ARD\t\t0x00000200 /* EEPROM Auto Read Done */\n#define IXGBE_EEC_FLUP\t\t0x00800000 /* Flash update command */\n#define IXGBE_EEC_SEC1VAL\t0x02000000 /* Sector 1 Valid */\n#define IXGBE_EEC_FLUDONE\t0x04000000 /* Flash update done */\n/* EEPROM Addressing bits based on type (0-small, 1-large) */\n#define IXGBE_EEC_ADDR_SIZE\t0x00000400\n#define IXGBE_EEC_SIZE\t\t0x00007800 /* EEPROM Size */\n#define IXGBE_EERD_MAX_ADDR\t0x00003FFF /* EERD alows 14 bits for addr. */\n\n#define IXGBE_EEC_SIZE_SHIFT\t\t11\n#define IXGBE_EEPROM_WORD_SIZE_SHIFT\t6\n#define IXGBE_EEPROM_OPCODE_BITS\t8\n\n/* Part Number String Length */\n#define IXGBE_PBANUM_LENGTH\t11\n\n/* Checksum and EEPROM pointers */\n#define IXGBE_PBANUM_PTR_GUARD\t0xFAFA\n#define IXGBE_EEPROM_CHECKSUM\t0x3F\n#define IXGBE_EEPROM_SUM\t0xBABA\n#define IXGBE_PCIE_ANALOG_PTR\t0x03\n#define IXGBE_ATLAS0_CONFIG_PTR\t0x04\n#define IXGBE_PHY_PTR\t\t0x04\n#define IXGBE_ATLAS1_CONFIG_PTR\t0x05\n#define IXGBE_OPTION_ROM_PTR\t0x05\n#define IXGBE_PCIE_GENERAL_PTR\t0x06\n#define IXGBE_PCIE_CONFIG0_PTR\t0x07\n#define IXGBE_PCIE_CONFIG1_PTR\t0x08\n#define IXGBE_CORE0_PTR\t\t0x09\n#define IXGBE_CORE1_PTR\t\t0x0A\n#define IXGBE_MAC0_PTR\t\t0x0B\n#define IXGBE_MAC1_PTR\t\t0x0C\n#define IXGBE_CSR0_CONFIG_PTR\t0x0D\n#define IXGBE_CSR1_CONFIG_PTR\t0x0E\n#define IXGBE_FW_PTR\t\t0x0F\n#define IXGBE_PBANUM0_PTR\t0x15\n#define IXGBE_PBANUM1_PTR\t0x16\n#define IXGBE_ALT_MAC_ADDR_PTR\t0x37\n#define IXGBE_FREE_SPACE_PTR\t0X3E\n\n/* External Thermal Sensor Config */\n#define IXGBE_ETS_CFG\t\t\t0x26\n#define IXGBE_ETS_LTHRES_DELTA_MASK\t0x07C0\n#define IXGBE_ETS_LTHRES_DELTA_SHIFT\t6\n#define IXGBE_ETS_TYPE_MASK\t\t0x0038\n#define IXGBE_ETS_TYPE_SHIFT\t\t3\n#define IXGBE_ETS_TYPE_EMC\t\t0x000\n#define IXGBE_ETS_NUM_SENSORS_MASK\t0x0007\n#define IXGBE_ETS_DATA_LOC_MASK\t\t0x3C00\n#define IXGBE_ETS_DATA_LOC_SHIFT\t10\n#define IXGBE_ETS_DATA_INDEX_MASK\t0x0300\n#define IXGBE_ETS_DATA_INDEX_SHIFT\t8\n#define IXGBE_ETS_DATA_HTHRESH_MASK\t0x00FF\n\n#define IXGBE_SAN_MAC_ADDR_PTR\t\t0x28\n#define IXGBE_DEVICE_CAPS\t\t0x2C\n#define IXGBE_SERIAL_NUMBER_MAC_ADDR\t0x11\n#define IXGBE_PCIE_MSIX_82599_CAPS\t0x72\n#define IXGBE_MAX_MSIX_VECTORS_82599\t0x40\n#define IXGBE_PCIE_MSIX_82598_CAPS\t0x62\n#define IXGBE_MAX_MSIX_VECTORS_82598\t0x13\n\n/* MSI-X capability fields masks */\n#define IXGBE_PCIE_MSIX_TBL_SZ_MASK\t0x7FF\n\n/* Legacy EEPROM word offsets */\n#define IXGBE_ISCSI_BOOT_CAPS\t\t0x0033\n#define IXGBE_ISCSI_SETUP_PORT_0\t0x0030\n#define IXGBE_ISCSI_SETUP_PORT_1\t0x0034\n\n/* EEPROM Commands - SPI */\n#define IXGBE_EEPROM_MAX_RETRY_SPI\t5000 /* Max wait 5ms for RDY signal */\n#define IXGBE_EEPROM_STATUS_RDY_SPI\t0x01\n#define IXGBE_EEPROM_READ_OPCODE_SPI\t0x03 /* EEPROM read opcode */\n#define IXGBE_EEPROM_WRITE_OPCODE_SPI\t0x02 /* EEPROM write opcode */\n#define IXGBE_EEPROM_A8_OPCODE_SPI\t0x08 /* opcode bit-3 = addr bit-8 */\n#define IXGBE_EEPROM_WREN_OPCODE_SPI\t0x06 /* EEPROM set Write Ena latch */\n/* EEPROM reset Write Enable latch */\n#define IXGBE_EEPROM_WRDI_OPCODE_SPI\t0x04\n#define IXGBE_EEPROM_RDSR_OPCODE_SPI\t0x05 /* EEPROM read Status reg */\n#define IXGBE_EEPROM_WRSR_OPCODE_SPI\t0x01 /* EEPROM write Status reg */\n#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI\t0x20 /* EEPROM ERASE 4KB */\n#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI\t0xD8 /* EEPROM ERASE 64KB */\n#define IXGBE_EEPROM_ERASE256_OPCODE_SPI\t0xDB /* EEPROM ERASE 256B */\n\n/* EEPROM Read Register */\n#define IXGBE_EEPROM_RW_REG_DATA\t16 /* data offset in EEPROM read reg */\n#define IXGBE_EEPROM_RW_REG_DONE\t2 /* Offset to READ done bit */\n#define IXGBE_EEPROM_RW_REG_START\t1 /* First bit to start operation */\n#define IXGBE_EEPROM_RW_ADDR_SHIFT\t2 /* Shift to the address bits */\n#define IXGBE_NVM_POLL_WRITE\t\t1 /* Flag for polling for wr complete */\n#define IXGBE_NVM_POLL_READ\t\t0 /* Flag for polling for rd complete */\n\n#define IXGBE_ETH_LENGTH_OF_ADDRESS\t6\n\n#define IXGBE_EEPROM_PAGE_SIZE_MAX\t128\n#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT\t512 /* words rd in burst */\n#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT\t256 /* words wr in burst */\n\n#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS\n#define IXGBE_EEPROM_GRANT_ATTEMPTS\t1000 /* EEPROM attempts to gain grant */\n#endif\n\n#ifndef IXGBE_EERD_EEWR_ATTEMPTS\n/* Number of 5 microseconds we wait for EERD read and\n * EERW write to complete */\n#define IXGBE_EERD_EEWR_ATTEMPTS\t100000\n#endif\n\n#ifndef IXGBE_FLUDONE_ATTEMPTS\n/* # attempts we wait for flush update to complete */\n#define IXGBE_FLUDONE_ATTEMPTS\t\t20000\n#endif\n\n#define IXGBE_PCIE_CTRL2\t\t0x5 /* PCIe Control 2 Offset */\n#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE\t0x8 /* Dummy Function Enable */\n#define IXGBE_PCIE_CTRL2_LAN_DISABLE\t0x2 /* LAN PCI Disable */\n#define IXGBE_PCIE_CTRL2_DISABLE_SELECT\t0x1 /* LAN Disable Select */\n\n#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET\t\t0x0\n#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET\t\t0x3\n#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP\t\t0x1\n#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS\t\t0x2\n#define IXGBE_FW_LESM_PARAMETERS_PTR\t\t0x2\n#define IXGBE_FW_LESM_STATE_1\t\t\t0x1\n#define IXGBE_FW_LESM_STATE_ENABLED\t\t0x8000 /* LESM Enable bit */\n#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR\t0x4\n#define IXGBE_FW_PATCH_VERSION_4\t\t0x7\n#define IXGBE_FCOE_IBA_CAPS_BLK_PTR\t\t0x33 /* iSCSI/FCOE block */\n#define IXGBE_FCOE_IBA_CAPS_FCOE\t\t0x20 /* FCOE flags */\n#define IXGBE_ISCSI_FCOE_BLK_PTR\t\t0x17 /* iSCSI/FCOE block */\n#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET\t\t0x0 /* FCOE flags */\n#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE\t\t0x1 /* FCOE flags enable bit */\n#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR\t\t0x27 /* Alt. SAN MAC block */\n#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET\t0x0 /* Alt SAN MAC capability */\n#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET\t0x1 /* Alt SAN MAC 0 offset */\n#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET\t0x4 /* Alt SAN MAC 1 offset */\n#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET\t0x7 /* Alt WWNN prefix offset */\n#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET\t0x8 /* Alt WWPN prefix offset */\n#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC\t0x0 /* Alt SAN MAC exists */\n#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN\t0x1 /* Alt WWN base exists */\n\n#define IXGBE_DEVICE_CAPS_WOL_PORT0_1\t0x4 /* WoL supported on ports 0 & 1 */\n#define IXGBE_DEVICE_CAPS_WOL_PORT0\t0x8 /* WoL supported on port 0 */\n#define IXGBE_DEVICE_CAPS_WOL_MASK\t0xC /* Mask for WoL capabilities */\n\n/* PCI Bus Info */\n#define IXGBE_PCI_DEVICE_STATUS\t\t0xAA\n#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING\t0x0020\n#define IXGBE_PCI_LINK_STATUS\t\t0xB2\n#define IXGBE_PCI_DEVICE_CONTROL2\t0xC8\n#define IXGBE_PCI_LINK_WIDTH\t\t0x3F0\n#define IXGBE_PCI_LINK_WIDTH_1\t\t0x10\n#define IXGBE_PCI_LINK_WIDTH_2\t\t0x20\n#define IXGBE_PCI_LINK_WIDTH_4\t\t0x40\n#define IXGBE_PCI_LINK_WIDTH_8\t\t0x80\n#define IXGBE_PCI_LINK_SPEED\t\t0xF\n#define IXGBE_PCI_LINK_SPEED_2500\t0x1\n#define IXGBE_PCI_LINK_SPEED_5000\t0x2\n#define IXGBE_PCI_LINK_SPEED_8000\t0x3\n#define IXGBE_PCI_HEADER_TYPE_REGISTER\t0x0E\n#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC\t0x80\n#define IXGBE_PCI_DEVICE_CONTROL2_16ms\t0x0005\n\n/* Number of 100 microseconds we wait for PCI Express master disable */\n#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT\t800\n\n/* Check whether address is multicast. This is little-endian specific check.*/\n#define IXGBE_IS_MULTICAST(Address) \\\n\t\t(bool)(((u8 *)(Address))[0] & ((u8)0x01))\n\n/* Check whether an address is broadcast. */\n#define IXGBE_IS_BROADCAST(Address) \\\n\t\t((((u8 *)(Address))[0] == ((u8)0xff)) && \\\n\t\t(((u8 *)(Address))[1] == ((u8)0xff)))\n\n/* RAH */\n#define IXGBE_RAH_VIND_MASK\t0x003C0000\n#define IXGBE_RAH_VIND_SHIFT\t18\n#define IXGBE_RAH_AV\t\t0x80000000\n#define IXGBE_CLEAR_VMDQ_ALL\t0xFFFFFFFF\n\n/* Header split receive */\n#define IXGBE_RFCTL_ISCSI_DIS\t\t0x00000001\n#define IXGBE_RFCTL_ISCSI_DWC_MASK\t0x0000003E\n#define IXGBE_RFCTL_ISCSI_DWC_SHIFT\t1\n#define IXGBE_RFCTL_RSC_DIS\t\t0x00000010\n#define IXGBE_RFCTL_NFSW_DIS\t\t0x00000040\n#define IXGBE_RFCTL_NFSR_DIS\t\t0x00000080\n#define IXGBE_RFCTL_NFS_VER_MASK\t0x00000300\n#define IXGBE_RFCTL_NFS_VER_SHIFT\t8\n#define IXGBE_RFCTL_NFS_VER_2\t\t0\n#define IXGBE_RFCTL_NFS_VER_3\t\t1\n#define IXGBE_RFCTL_NFS_VER_4\t\t2\n#define IXGBE_RFCTL_IPV6_DIS\t\t0x00000400\n#define IXGBE_RFCTL_IPV6_XSUM_DIS\t0x00000800\n#define IXGBE_RFCTL_IPFRSP_DIS\t\t0x00004000\n#define IXGBE_RFCTL_IPV6_EX_DIS\t\t0x00010000\n#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS\t0x00020000\n\n/* Transmit Config masks */\n#define IXGBE_TXDCTL_ENABLE\t\t0x02000000 /* Ena specific Tx Queue */\n#define IXGBE_TXDCTL_SWFLSH\t\t0x04000000 /* Tx Desc. wr-bk flushing */\n#define IXGBE_TXDCTL_WTHRESH_SHIFT\t16 /* shift to WTHRESH bits */\n/* Enable short packet padding to 64 bytes */\n#define IXGBE_TX_PAD_ENABLE\t\t0x00000400\n#define IXGBE_JUMBO_FRAME_ENABLE\t0x00000004 /* Allow jumbo frames */\n/* This allows for 16K packets + 4k for vlan */\n#define IXGBE_MAX_FRAME_SZ\t\t0x40040000\n\n#define IXGBE_TDWBAL_HEAD_WB_ENABLE\t0x1 /* Tx head write-back enable */\n#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE\t0x2 /* Tx seq# write-back enable */\n\n/* Receive Config masks */\n#define IXGBE_RXCTRL_RXEN\t\t0x00000001 /* Enable Receiver */\n#define IXGBE_RXCTRL_DMBYPS\t\t0x00000002 /* Desc Monitor Bypass */\n#define IXGBE_RXDCTL_ENABLE\t\t0x02000000 /* Ena specific Rx Queue */\n#define IXGBE_RXDCTL_SWFLSH\t\t0x04000000 /* Rx Desc wr-bk flushing */\n#define IXGBE_RXDCTL_RLPMLMASK\t\t0x00003FFF /* X540 supported only */\n#define IXGBE_RXDCTL_RLPML_EN\t\t0x00008000\n#define IXGBE_RXDCTL_VME\t\t0x40000000 /* VLAN mode enable */\n\n#define IXGBE_TSYNCTXCTL_VALID\t\t0x00000001 /* Tx timestamp valid */\n#define IXGBE_TSYNCTXCTL_ENABLED\t0x00000010 /* Tx timestamping enabled */\n\n#define IXGBE_TSYNCRXCTL_VALID\t\t0x00000001 /* Rx timestamp valid */\n#define IXGBE_TSYNCRXCTL_TYPE_MASK\t0x0000000E /* Rx type mask */\n#define IXGBE_TSYNCRXCTL_TYPE_L2_V2\t0x00\n#define IXGBE_TSYNCRXCTL_TYPE_L4_V1\t0x02\n#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2\t0x04\n#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2\t0x0A\n#define IXGBE_TSYNCRXCTL_ENABLED\t0x00000010 /* Rx Timestamping enabled */\n\n#define IXGBE_RXMTRL_V1_CTRLT_MASK\t0x000000FF\n#define IXGBE_RXMTRL_V1_SYNC_MSG\t0x00\n#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG\t0x01\n#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG\t0x02\n#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG\t0x03\n#define IXGBE_RXMTRL_V1_MGMT_MSG\t0x04\n\n#define IXGBE_RXMTRL_V2_MSGID_MASK\t0x0000FF00\n#define IXGBE_RXMTRL_V2_SYNC_MSG\t0x0000\n#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG\t0x0100\n#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG\t0x0200\n#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG\t0x0300\n#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG\t0x0800\n#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG\t0x0900\n#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00\n#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG\t0x0B00\n#define IXGBE_RXMTRL_V2_SIGNALLING_MSG\t0x0C00\n#define IXGBE_RXMTRL_V2_MGMT_MSG\t0x0D00\n\n#define IXGBE_FCTRL_SBP\t\t0x00000002 /* Store Bad Packet */\n#define IXGBE_FCTRL_MPE\t\t0x00000100 /* Multicast Promiscuous Ena*/\n#define IXGBE_FCTRL_UPE\t\t0x00000200 /* Unicast Promiscuous Ena */\n#define IXGBE_FCTRL_BAM\t\t0x00000400 /* Broadcast Accept Mode */\n#define IXGBE_FCTRL_PMCF\t0x00001000 /* Pass MAC Control Frames */\n#define IXGBE_FCTRL_DPF\t\t0x00002000 /* Discard Pause Frame */\n/* Receive Priority Flow Control Enable */\n#define IXGBE_FCTRL_RPFCE\t0x00004000\n#define IXGBE_FCTRL_RFCE\t0x00008000 /* Receive Flow Control Ena */\n#define IXGBE_MFLCN_PMCF\t0x00000001 /* Pass MAC Control Frames */\n#define IXGBE_MFLCN_DPF\t\t0x00000002 /* Discard Pause Frame */\n#define IXGBE_MFLCN_RPFCE\t0x00000004 /* Receive Priority FC Enable */\n#define IXGBE_MFLCN_RFCE\t0x00000008 /* Receive FC Enable */\n#define IXGBE_MFLCN_RPFCE_MASK\t0x00000FF4 /* Rx Priority FC bitmap mask */\n#define IXGBE_MFLCN_RPFCE_SHIFT\t4 /* Rx Priority FC bitmap shift */\n\n/* Multiple Receive Queue Control */\n#define IXGBE_MRQC_RSSEN\t0x00000001 /* RSS Enable */\n#define IXGBE_MRQC_MRQE_MASK\t0xF /* Bits 3:0 */\n#define IXGBE_MRQC_RT8TCEN\t0x00000002 /* 8 TC no RSS */\n#define IXGBE_MRQC_RT4TCEN\t0x00000003 /* 4 TC no RSS */\n#define IXGBE_MRQC_RTRSS8TCEN\t0x00000004 /* 8 TC w/ RSS */\n#define IXGBE_MRQC_RTRSS4TCEN\t0x00000005 /* 4 TC w/ RSS */\n#define IXGBE_MRQC_VMDQEN\t0x00000008 /* VMDq2 64 pools no RSS */\n#define IXGBE_MRQC_VMDQRSS32EN\t0x0000000A /* VMDq2 32 pools w/ RSS */\n#define IXGBE_MRQC_VMDQRSS64EN\t0x0000000B /* VMDq2 64 pools w/ RSS */\n#define IXGBE_MRQC_VMDQRT8TCEN\t0x0000000C /* VMDq2/RT 16 pool 8 TC */\n#define IXGBE_MRQC_VMDQRT4TCEN\t0x0000000D /* VMDq2/RT 32 pool 4 TC */\n#define IXGBE_MRQC_RSS_FIELD_MASK\t0xFFFF0000\n#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP\t0x00010000\n#define IXGBE_MRQC_RSS_FIELD_IPV4\t0x00020000\n#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000\n#define IXGBE_MRQC_RSS_FIELD_IPV6_EX\t0x00080000\n#define IXGBE_MRQC_RSS_FIELD_IPV6\t0x00100000\n#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP\t0x00200000\n#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP\t0x00400000\n#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP\t0x00800000\n#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000\n#define IXGBE_MRQC_L3L4TXSWEN\t\t0x00008000\n\n/* Queue Drop Enable */\n#define IXGBE_QDE_ENABLE\t0x00000001\n#define IXGBE_QDE_IDX_MASK\t0x00007F00\n#define IXGBE_QDE_IDX_SHIFT\t8\n#define IXGBE_QDE_WRITE\t\t0x00010000\n#define IXGBE_QDE_READ\t\t0x00020000\n\n#define IXGBE_TXD_POPTS_IXSM\t0x01 /* Insert IP checksum */\n#define IXGBE_TXD_POPTS_TXSM\t0x02 /* Insert TCP/UDP checksum */\n#define IXGBE_TXD_CMD_EOP\t0x01000000 /* End of Packet */\n#define IXGBE_TXD_CMD_IFCS\t0x02000000 /* Insert FCS (Ethernet CRC) */\n#define IXGBE_TXD_CMD_IC\t0x04000000 /* Insert Checksum */\n#define IXGBE_TXD_CMD_RS\t0x08000000 /* Report Status */\n#define IXGBE_TXD_CMD_DEXT\t0x20000000 /* Desc extension (0 = legacy) */\n#define IXGBE_TXD_CMD_VLE\t0x40000000 /* Add VLAN tag */\n#define IXGBE_TXD_STAT_DD\t0x00000001 /* Descriptor Done */\n\n#define IXGBE_RXDADV_IPSEC_STATUS_SECP\t\t0x00020000\n#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000\n#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH\t0x10000000\n#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED\t0x18000000\n#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK\t0x18000000\n/* Multiple Transmit Queue Command Register */\n#define IXGBE_MTQC_RT_ENA\t0x1 /* DCB Enable */\n#define IXGBE_MTQC_VT_ENA\t0x2 /* VMDQ2 Enable */\n#define IXGBE_MTQC_64Q_1PB\t0x0 /* 64 queues 1 pack buffer */\n#define IXGBE_MTQC_32VF\t\t0x8 /* 4 TX Queues per pool w/32VF's */\n#define IXGBE_MTQC_64VF\t\t0x4 /* 2 TX Queues per pool w/64VF's */\n#define IXGBE_MTQC_4TC_4TQ\t0x8 /* 4 TC if RT_ENA and VT_ENA */\n#define IXGBE_MTQC_8TC_8TQ\t0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */\n\n/* Receive Descriptor bit definitions */\n#define IXGBE_RXD_STAT_DD\t0x01 /* Descriptor Done */\n#define IXGBE_RXD_STAT_EOP\t0x02 /* End of Packet */\n#define IXGBE_RXD_STAT_FLM\t0x04 /* FDir Match */\n#define IXGBE_RXD_STAT_VP\t0x08 /* IEEE VLAN Packet */\n#define IXGBE_RXDADV_NEXTP_MASK\t0x000FFFF0 /* Next Descriptor Index */\n#define IXGBE_RXDADV_NEXTP_SHIFT\t0x00000004\n#define IXGBE_RXD_STAT_UDPCS\t0x10 /* UDP xsum calculated */\n#define IXGBE_RXD_STAT_L4CS\t0x20 /* L4 xsum calculated */\n#define IXGBE_RXD_STAT_IPCS\t0x40 /* IP xsum calculated */\n#define IXGBE_RXD_STAT_PIF\t0x80 /* passed in-exact filter */\n#define IXGBE_RXD_STAT_CRCV\t0x100 /* Speculative CRC Valid */\n#define IXGBE_RXD_STAT_VEXT\t0x200 /* 1st VLAN found */\n#define IXGBE_RXD_STAT_UDPV\t0x400 /* Valid UDP checksum */\n#define IXGBE_RXD_STAT_DYNINT\t0x800 /* Pkt caused INT via DYNINT */\n#define IXGBE_RXD_STAT_LLINT\t0x800 /* Pkt caused Low Latency Interrupt */\n#define IXGBE_RXD_STAT_TS\t0x10000 /* Time Stamp */\n#define IXGBE_RXD_STAT_SECP\t0x20000 /* Security Processing */\n#define IXGBE_RXD_STAT_LB\t0x40000 /* Loopback Status */\n#define IXGBE_RXD_STAT_ACK\t0x8000 /* ACK Packet indication */\n#define IXGBE_RXD_ERR_CE\t0x01 /* CRC Error */\n#define IXGBE_RXD_ERR_LE\t0x02 /* Length Error */\n#define IXGBE_RXD_ERR_PE\t0x08 /* Packet Error */\n#define IXGBE_RXD_ERR_OSE\t0x10 /* Oversize Error */\n#define IXGBE_RXD_ERR_USE\t0x20 /* Undersize Error */\n#define IXGBE_RXD_ERR_TCPE\t0x40 /* TCP/UDP Checksum Error */\n#define IXGBE_RXD_ERR_IPE\t0x80 /* IP Checksum Error */\n#define IXGBE_RXDADV_ERR_MASK\t\t0xfff00000 /* RDESC.ERRORS mask */\n#define IXGBE_RXDADV_ERR_SHIFT\t\t20 /* RDESC.ERRORS shift */\n#define IXGBE_RXDADV_ERR_RXE\t\t0x20000000 /* Any MAC Error */\n#define IXGBE_RXDADV_ERR_FCEOFE\t\t0x80000000 /* FCoEFe/IPE */\n#define IXGBE_RXDADV_ERR_FCERR\t\t0x00700000 /* FCERR/FDIRERR */\n#define IXGBE_RXDADV_ERR_FDIR_LEN\t0x00100000 /* FDIR Length error */\n#define IXGBE_RXDADV_ERR_FDIR_DROP\t0x00200000 /* FDIR Drop error */\n#define IXGBE_RXDADV_ERR_FDIR_COLL\t0x00400000 /* FDIR Collision error */\n#define IXGBE_RXDADV_ERR_HBO\t0x00800000 /*Header Buffer Overflow */\n#define IXGBE_RXDADV_ERR_CE\t0x01000000 /* CRC Error */\n#define IXGBE_RXDADV_ERR_LE\t0x02000000 /* Length Error */\n#define IXGBE_RXDADV_ERR_PE\t0x08000000 /* Packet Error */\n#define IXGBE_RXDADV_ERR_OSE\t0x10000000 /* Oversize Error */\n#define IXGBE_RXDADV_ERR_USE\t0x20000000 /* Undersize Error */\n#define IXGBE_RXDADV_ERR_TCPE\t0x40000000 /* TCP/UDP Checksum Error */\n#define IXGBE_RXDADV_ERR_IPE\t0x80000000 /* IP Checksum Error */\n#define IXGBE_RXD_VLAN_ID_MASK\t0x0FFF /* VLAN ID is in lower 12 bits */\n#define IXGBE_RXD_PRI_MASK\t0xE000 /* Priority is in upper 3 bits */\n#define IXGBE_RXD_PRI_SHIFT\t13\n#define IXGBE_RXD_CFI_MASK\t0x1000 /* CFI is bit 12 */\n#define IXGBE_RXD_CFI_SHIFT\t12\n\n#define IXGBE_RXDADV_STAT_DD\t\tIXGBE_RXD_STAT_DD /* Done */\n#define IXGBE_RXDADV_STAT_EOP\t\tIXGBE_RXD_STAT_EOP /* End of Packet */\n#define IXGBE_RXDADV_STAT_FLM\t\tIXGBE_RXD_STAT_FLM /* FDir Match */\n#define IXGBE_RXDADV_STAT_VP\t\tIXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */\n#define IXGBE_RXDADV_STAT_MASK\t\t0x000fffff /* Stat/NEXTP: bit 0-19 */\n#define IXGBE_RXDADV_STAT_FCEOFS\t0x00000040 /* FCoE EOF/SOF Stat */\n#define IXGBE_RXDADV_STAT_FCSTAT\t0x00000030 /* FCoE Pkt Stat */\n#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH\t0x00000000 /* 00: No Ctxt Match */\n#define IXGBE_RXDADV_STAT_FCSTAT_NODDP\t0x00000010 /* 01: Ctxt w/o DDP */\n#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP\t0x00000020 /* 10: Recv. FCP_RSP */\n#define IXGBE_RXDADV_STAT_FCSTAT_DDP\t0x00000030 /* 11: Ctxt w/ DDP */\n#define IXGBE_RXDADV_STAT_TS\t\t0x00010000 /* IEEE1588 Time Stamp */\n\n/* PSRTYPE bit definitions */\n#define IXGBE_PSRTYPE_TCPHDR\t0x00000010\n#define IXGBE_PSRTYPE_UDPHDR\t0x00000020\n#define IXGBE_PSRTYPE_IPV4HDR\t0x00000100\n#define IXGBE_PSRTYPE_IPV6HDR\t0x00000200\n#define IXGBE_PSRTYPE_L2HDR\t0x00001000\n\n/* SRRCTL bit definitions */\n#define IXGBE_SRRCTL_BSIZEPKT_SHIFT\t10 /* so many KBs */\n#define IXGBE_SRRCTL_RDMTS_SHIFT\t22\n#define IXGBE_SRRCTL_RDMTS_MASK\t\t0x01C00000\n#define IXGBE_SRRCTL_DROP_EN\t\t0x10000000\n#define IXGBE_SRRCTL_BSIZEPKT_MASK\t0x0000007F\n#define IXGBE_SRRCTL_BSIZEHDR_MASK\t0x00003F00\n#define IXGBE_SRRCTL_DESCTYPE_LEGACY\t0x00000000\n#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000\n#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT\t0x04000000\n#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000\n#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000\n#define IXGBE_SRRCTL_DESCTYPE_MASK\t0x0E000000\n\n#define IXGBE_RXDPS_HDRSTAT_HDRSP\t0x00008000\n#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK\t0x000003FF\n\n#define IXGBE_RXDADV_RSSTYPE_MASK\t0x0000000F\n#define IXGBE_RXDADV_PKTTYPE_MASK\t0x0000FFF0\n#define IXGBE_RXDADV_PKTTYPE_MASK_EX\t0x0001FFF0\n#define IXGBE_RXDADV_HDRBUFLEN_MASK\t0x00007FE0\n#define IXGBE_RXDADV_RSCCNT_MASK\t0x001E0000\n#define IXGBE_RXDADV_RSCCNT_SHIFT\t17\n#define IXGBE_RXDADV_HDRBUFLEN_SHIFT\t5\n#define IXGBE_RXDADV_SPLITHEADER_EN\t0x00001000\n#define IXGBE_RXDADV_SPH\t\t0x8000\n\n/* RSS Hash results */\n#define IXGBE_RXDADV_RSSTYPE_NONE\t0x00000000\n#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP\t0x00000001\n#define IXGBE_RXDADV_RSSTYPE_IPV4\t0x00000002\n#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP\t0x00000003\n#define IXGBE_RXDADV_RSSTYPE_IPV6_EX\t0x00000004\n#define IXGBE_RXDADV_RSSTYPE_IPV6\t0x00000005\n#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006\n#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP\t0x00000007\n#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP\t0x00000008\n#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009\n\n/* RSS Packet Types as indicated in the receive descriptor. */\n#define IXGBE_RXDADV_PKTTYPE_NONE\t0x00000000\n#define IXGBE_RXDADV_PKTTYPE_IPV4\t0x00000010 /* IPv4 hdr present */\n#define IXGBE_RXDADV_PKTTYPE_IPV4_EX\t0x00000020 /* IPv4 hdr + extensions */\n#define IXGBE_RXDADV_PKTTYPE_IPV6\t0x00000040 /* IPv6 hdr present */\n#define IXGBE_RXDADV_PKTTYPE_IPV6_EX\t0x00000080 /* IPv6 hdr + extensions */\n#define IXGBE_RXDADV_PKTTYPE_TCP\t0x00000100 /* TCP hdr present */\n#define IXGBE_RXDADV_PKTTYPE_UDP\t0x00000200 /* UDP hdr present */\n#define IXGBE_RXDADV_PKTTYPE_SCTP\t0x00000400 /* SCTP hdr present */\n#define IXGBE_RXDADV_PKTTYPE_NFS\t0x00000800 /* NFS hdr present */\n#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP\t0x00001000 /* IPSec ESP */\n#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH\t0x00002000 /* IPSec AH */\n#define IXGBE_RXDADV_PKTTYPE_LINKSEC\t0x00004000 /* LinkSec Encap */\n#define IXGBE_RXDADV_PKTTYPE_ETQF\t0x00008000 /* PKTTYPE is ETQF index */\n#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK\t0x00000070 /* ETQF has 8 indices */\n#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT\t4 /* Right-shift 4 bits */\n\n/* Security Processing bit Indication */\n#define IXGBE_RXDADV_LNKSEC_STATUS_SECP\t\t0x00020000\n#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH\t0x08000000\n#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR\t0x10000000\n#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK\t0x18000000\n#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG\t0x18000000\n\n/* Masks to determine if packets should be dropped due to frame errors */\n#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \\\n\t\t\t\tIXGBE_RXD_ERR_CE | \\\n\t\t\t\tIXGBE_RXD_ERR_LE | \\\n\t\t\t\tIXGBE_RXD_ERR_PE | \\\n\t\t\t\tIXGBE_RXD_ERR_OSE | \\\n\t\t\t\tIXGBE_RXD_ERR_USE)\n\n#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \\\n\t\t\t\tIXGBE_RXDADV_ERR_CE | \\\n\t\t\t\tIXGBE_RXDADV_ERR_LE | \\\n\t\t\t\tIXGBE_RXDADV_ERR_PE | \\\n\t\t\t\tIXGBE_RXDADV_ERR_OSE | \\\n\t\t\t\tIXGBE_RXDADV_ERR_USE)\n\n#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599\tIXGBE_RXDADV_ERR_RXE\n\n/* Multicast bit mask */\n#define IXGBE_MCSTCTRL_MFE\t0x4\n\n/* Number of Transmit and Receive Descriptors must be a multiple of 8 */\n#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE\t8\n#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE\t8\n#define IXGBE_REQ_TX_BUFFER_GRANULARITY\t\t1024\n\n/* Vlan-specific macros */\n#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK\t0x0FFF /* VLAN ID in lower 12 bits */\n#define IXGBE_RX_DESC_SPECIAL_PRI_MASK\t0xE000 /* Priority in upper 3 bits */\n#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT\t0x000D /* Priority in upper 3 of 16 */\n#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT\tIXGBE_RX_DESC_SPECIAL_PRI_SHIFT\n\n/* SR-IOV specific macros */\n#define IXGBE_MBVFICR_INDEX(vf_number)\t(vf_number >> 4)\n#define IXGBE_MBVFICR(_i)\t\t(0x00710 + ((_i) * 4))\n#define IXGBE_VFLRE(_i)\t\t\t(((_i & 1) ? 0x001C0 : 0x00600))\n#define IXGBE_VFLREC(_i)\t\t (0x00700 + ((_i) * 4))\n/* Translated register #defines */\n#define IXGBE_PVFCTRL(P)\t(0x00300 + (4 * (P)))\n#define IXGBE_PVFSTATUS(P)\t(0x00008 + (0 * (P)))\n#define IXGBE_PVFLINKS(P)\t(0x042A4 + (0 * (P)))\n#define IXGBE_PVFRTIMER(P)\t(0x00048 + (0 * (P)))\n#define IXGBE_PVFMAILBOX(P)\t(0x04C00 + (4 * (P)))\n#define IXGBE_PVFRXMEMWRAP(P)\t(0x03190 + (0 * (P)))\n#define IXGBE_PVTEICR(P)\t(0x00B00 + (4 * (P)))\n#define IXGBE_PVTEICS(P)\t(0x00C00 + (4 * (P)))\n#define IXGBE_PVTEIMS(P)\t(0x00D00 + (4 * (P)))\n#define IXGBE_PVTEIMC(P)\t(0x00E00 + (4 * (P)))\n#define IXGBE_PVTEIAC(P)\t(0x00F00 + (4 * (P)))\n#define IXGBE_PVTEIAM(P)\t(0x04D00 + (4 * (P)))\n#define IXGBE_PVTEITR(P)\t(((P) < 24) ? (0x00820 + ((P) * 4)) : \\\n\t\t\t\t (0x012300 + (((P) - 24) * 4)))\n#define IXGBE_PVTIVAR(P)\t(0x12500 + (4 * (P)))\n#define IXGBE_PVTIVAR_MISC(P)\t(0x04E00 + (4 * (P)))\n#define IXGBE_PVTRSCINT(P)\t(0x12000 + (4 * (P)))\n#define IXGBE_VFPBACL(P)\t(0x110C8 + (4 * (P)))\n#define IXGBE_PVFRDBAL(P)\t((P < 64) ? (0x01000 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D000 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFRDBAH(P)\t((P < 64) ? (0x01004 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D004 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFRDLEN(P)\t((P < 64) ? (0x01008 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D008 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFRDH(P)\t\t((P < 64) ? (0x01010 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D010 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFRDT(P)\t\t((P < 64) ? (0x01018 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D018 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFRXDCTL(P)\t((P < 64) ? (0x01028 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D028 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFSRRCTL(P)\t((P < 64) ? (0x01014 + (0x40 * (P))) \\\n\t\t\t\t : (0x0D014 + (0x40 * ((P) - 64))))\n#define IXGBE_PVFPSRTYPE(P)\t(0x0EA00 + (4 * (P)))\n#define IXGBE_PVFTDBAL(P)\t(0x06000 + (0x40 * (P)))\n#define IXGBE_PVFTDBAH(P)\t(0x06004 + (0x40 * (P)))\n#define IXGBE_PVFTTDLEN(P)\t(0x06008 + (0x40 * (P)))\n#define IXGBE_PVFTDH(P)\t\t(0x06010 + (0x40 * (P)))\n#define IXGBE_PVFTDT(P)\t\t(0x06018 + (0x40 * (P)))\n#define IXGBE_PVFTXDCTL(P)\t(0x06028 + (0x40 * (P)))\n#define IXGBE_PVFTDWBAL(P)\t(0x06038 + (0x40 * (P)))\n#define IXGBE_PVFTDWBAH(P)\t(0x0603C + (0x40 * (P)))\n#define IXGBE_PVFDCA_RXCTRL(P)\t(((P) < 64) ? (0x0100C + (0x40 * (P))) \\\n\t\t\t\t : (0x0D00C + (0x40 * ((P) - 64))))\n#define IXGBE_PVFDCA_TXCTRL(P)\t(0x0600C + (0x40 * (P)))\n#define IXGBE_PVFGPRC(x)\t(0x0101C + (0x40 * (x)))\n#define IXGBE_PVFGPTC(x)\t(0x08300 + (0x04 * (x)))\n#define IXGBE_PVFGORC_LSB(x)\t(0x01020 + (0x40 * (x)))\n#define IXGBE_PVFGORC_MSB(x)\t(0x0D020 + (0x40 * (x)))\n#define IXGBE_PVFGOTC_LSB(x)\t(0x08400 + (0x08 * (x)))\n#define IXGBE_PVFGOTC_MSB(x)\t(0x08404 + (0x08 * (x)))\n#define IXGBE_PVFMPRC(x)\t(0x0D01C + (0x40 * (x)))\n\n#define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \\\n\t\t(IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))\n#define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \\\n\t\t(IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))\n\n/* Little Endian defines */\n#ifndef __le16\n#define __le16 u16\n#endif\n#ifndef __le32\n#define __le32 u32\n#endif\n#ifndef __le64\n#define __le64 u64\n\n#endif\n#ifndef __be16\n/* Big Endian defines */\n#define __be16 u16\n#define __be32 u32\n#define __be64 u64\n\n#endif\nenum ixgbe_fdir_pballoc_type {\n\tIXGBE_FDIR_PBALLOC_NONE = 0,\n\tIXGBE_FDIR_PBALLOC_64K = 1,\n\tIXGBE_FDIR_PBALLOC_128K = 2,\n\tIXGBE_FDIR_PBALLOC_256K = 3,\n};\n\n/* Flow Director register values */\n#define IXGBE_FDIRCTRL_PBALLOC_64K\t\t0x00000001\n#define IXGBE_FDIRCTRL_PBALLOC_128K\t\t0x00000002\n#define IXGBE_FDIRCTRL_PBALLOC_256K\t\t0x00000003\n#define IXGBE_FDIRCTRL_INIT_DONE\t\t0x00000008\n#define IXGBE_FDIRCTRL_PERFECT_MATCH\t\t0x00000010\n#define IXGBE_FDIRCTRL_REPORT_STATUS\t\t0x00000020\n#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS\t0x00000080\n#define IXGBE_FDIRCTRL_DROP_Q_SHIFT\t\t8\n#define IXGBE_FDIRCTRL_FLEX_SHIFT\t\t16\n#define IXGBE_FDIRCTRL_SEARCHLIM\t\t0x00800000\n#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT\t\t24\n#define IXGBE_FDIRCTRL_FULL_THRESH_MASK\t\t0xF0000000\n#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT\t28\n\n#define IXGBE_FDIRTCPM_DPORTM_SHIFT\t\t16\n#define IXGBE_FDIRUDPM_DPORTM_SHIFT\t\t16\n#define IXGBE_FDIRIP6M_DIPM_SHIFT\t\t16\n#define IXGBE_FDIRM_VLANID\t\t\t0x00000001\n#define IXGBE_FDIRM_VLANP\t\t\t0x00000002\n#define IXGBE_FDIRM_POOL\t\t\t0x00000004\n#define IXGBE_FDIRM_L4P\t\t\t\t0x00000008\n#define IXGBE_FDIRM_FLEX\t\t\t0x00000010\n#define IXGBE_FDIRM_DIPv6\t\t\t0x00000020\n\n#define IXGBE_FDIRFREE_FREE_MASK\t\t0xFFFF\n#define IXGBE_FDIRFREE_FREE_SHIFT\t\t0\n#define IXGBE_FDIRFREE_COLL_MASK\t\t0x7FFF0000\n#define IXGBE_FDIRFREE_COLL_SHIFT\t\t16\n#define IXGBE_FDIRLEN_MAXLEN_MASK\t\t0x3F\n#define IXGBE_FDIRLEN_MAXLEN_SHIFT\t\t0\n#define IXGBE_FDIRLEN_MAXHASH_MASK\t\t0x7FFF0000\n#define IXGBE_FDIRLEN_MAXHASH_SHIFT\t\t16\n#define IXGBE_FDIRUSTAT_ADD_MASK\t\t0xFFFF\n#define IXGBE_FDIRUSTAT_ADD_SHIFT\t\t0\n#define IXGBE_FDIRUSTAT_REMOVE_MASK\t\t0xFFFF0000\n#define IXGBE_FDIRUSTAT_REMOVE_SHIFT\t\t16\n#define IXGBE_FDIRFSTAT_FADD_MASK\t\t0x00FF\n#define IXGBE_FDIRFSTAT_FADD_SHIFT\t\t0\n#define IXGBE_FDIRFSTAT_FREMOVE_MASK\t\t0xFF00\n#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT\t\t8\n#define IXGBE_FDIRPORT_DESTINATION_SHIFT\t16\n#define IXGBE_FDIRVLAN_FLEX_SHIFT\t\t16\n#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT\t15\n#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT\t16\n\n#define IXGBE_FDIRCMD_CMD_MASK\t\t\t0x00000003\n#define IXGBE_FDIRCMD_CMD_ADD_FLOW\t\t0x00000001\n#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW\t\t0x00000002\n#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT\t0x00000003\n#define IXGBE_FDIRCMD_FILTER_VALID\t\t0x00000004\n#define IXGBE_FDIRCMD_FILTER_UPDATE\t\t0x00000008\n#define IXGBE_FDIRCMD_IPv6DMATCH\t\t0x00000010\n#define IXGBE_FDIRCMD_L4TYPE_UDP\t\t0x00000020\n#define IXGBE_FDIRCMD_L4TYPE_TCP\t\t0x00000040\n#define IXGBE_FDIRCMD_L4TYPE_SCTP\t\t0x00000060\n#define IXGBE_FDIRCMD_IPV6\t\t\t0x00000080\n#define IXGBE_FDIRCMD_CLEARHT\t\t\t0x00000100\n#define IXGBE_FDIRCMD_DROP\t\t\t0x00000200\n#define IXGBE_FDIRCMD_INT\t\t\t0x00000400\n#define IXGBE_FDIRCMD_LAST\t\t\t0x00000800\n#define IXGBE_FDIRCMD_COLLISION\t\t\t0x00001000\n#define IXGBE_FDIRCMD_QUEUE_EN\t\t\t0x00008000\n#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT\t\t5\n#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT\t\t16\n#define IXGBE_FDIRCMD_VT_POOL_SHIFT\t\t24\n#define IXGBE_FDIR_INIT_DONE_POLL\t\t10\n#define IXGBE_FDIRCMD_CMD_POLL\t\t\t10\n\n#define IXGBE_FDIR_DROP_QUEUE\t\t\t127\n\n#define IXGBE_STATUS_OVERHEATING_BIT\t\t20 /* STATUS overtemp bit num */\n\n/* Manageablility Host Interface defines */\n#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH\t1792 /* Num of bytes in range */\n#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH\t448 /* Num of dwords in range */\n#define IXGBE_HI_COMMAND_TIMEOUT\t500 /* Process HI command limit */\n\n/* CEM Support */\n#define FW_CEM_HDR_LEN\t\t\t0x4\n#define FW_CEM_CMD_DRIVER_INFO\t\t0xDD\n#define FW_CEM_CMD_DRIVER_INFO_LEN\t0x5\n#define FW_CEM_CMD_RESERVED\t\t0X0\n#define FW_CEM_UNUSED_VER\t\t0x0\n#define FW_CEM_MAX_RETRIES\t\t3\n#define FW_CEM_RESP_STATUS_SUCCESS\t0x1\n\n/* Host Interface Command Structures */\n\nstruct ixgbe_hic_hdr {\n\tu8 cmd;\n\tu8 buf_len;\n\tunion {\n\t\tu8 cmd_resv;\n\t\tu8 ret_status;\n\t} cmd_or_resp;\n\tu8 checksum;\n};\n\nstruct ixgbe_hic_drv_info {\n\tstruct ixgbe_hic_hdr hdr;\n\tu8 port_num;\n\tu8 ver_sub;\n\tu8 ver_build;\n\tu8 ver_min;\n\tu8 ver_maj;\n\tu8 pad; /* end spacing to ensure length is mult. of dword */\n\tu16 pad2; /* end spacing to ensure length is mult. of dword2 */\n};\n\n/* Transmit Descriptor - Legacy */\nstruct ixgbe_legacy_tx_desc {\n\tu64 buffer_addr; /* Address of the descriptor's data buffer */\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\t__le16 length; /* Data buffer length */\n\t\t\tu8 cso; /* Checksum offset */\n\t\t\tu8 cmd; /* Descriptor control */\n\t\t} flags;\n\t} lower;\n\tunion {\n\t\t__le32 data;\n\t\tstruct {\n\t\t\tu8 status; /* Descriptor status */\n\t\t\tu8 css; /* Checksum start */\n\t\t\t__le16 vlan;\n\t\t} fields;\n\t} upper;\n};\n\n/* Transmit Descriptor - Advanced */\nunion ixgbe_adv_tx_desc {\n\tstruct {\n\t\t__le64 buffer_addr; /* Address of descriptor's data buf */\n\t\t__le32 cmd_type_len;\n\t\t__le32 olinfo_status;\n\t} read;\n\tstruct {\n\t\t__le64 rsvd; /* Reserved */\n\t\t__le32 nxtseq_seed;\n\t\t__le32 status;\n\t} wb;\n};\n\n/* Receive Descriptor - Legacy */\nstruct ixgbe_legacy_rx_desc {\n\t__le64 buffer_addr; /* Address of the descriptor's data buffer */\n\t__le16 length; /* Length of data DMAed into data buffer */\n\t__le16 csum; /* Packet checksum */\n\tu8 status; /* Descriptor status */\n\tu8 errors; /* Descriptor Errors */\n\t__le16 vlan;\n};\n\n/* Receive Descriptor - Advanced */\nunion ixgbe_adv_rx_desc {\n\tstruct {\n\t\t__le64 pkt_addr; /* Packet buffer address */\n\t\t__le64 hdr_addr; /* Header buffer address */\n\t} read;\n\tstruct {\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\t__le32 data;\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 pkt_info; /* RSS, Pkt type */\n\t\t\t\t\t__le16 hdr_info; /* Splithdr, hdrlen */\n\t\t\t\t} hs_rss;\n\t\t\t} lo_dword;\n\t\t\tunion {\n\t\t\t\t__le32 rss; /* RSS Hash */\n\t\t\t\tstruct {\n\t\t\t\t\t__le16 ip_id; /* IP id */\n\t\t\t\t\t__le16 csum; /* Packet Checksum */\n\t\t\t\t} csum_ip;\n\t\t\t} hi_dword;\n\t\t} lower;\n\t\tstruct {\n\t\t\t__le32 status_error; /* ext status/error */\n\t\t\t__le16 length; /* Packet length */\n\t\t\t__le16 vlan; /* VLAN tag */\n\t\t} upper;\n\t} wb; /* writeback */\n};\n\n/* Context descriptors */\nstruct ixgbe_adv_tx_context_desc {\n\t__le32 vlan_macip_lens;\n\t__le32 seqnum_seed;\n\t__le32 type_tucmd_mlhl;\n\t__le32 mss_l4len_idx;\n};\n\n/* Adv Transmit Descriptor Config Masks */\n#define IXGBE_ADVTXD_DTALEN_MASK\t0x0000FFFF /* Data buf length(bytes) */\n#define IXGBE_ADVTXD_MAC_LINKSEC\t0x00040000 /* Insert LinkSec */\n#define IXGBE_ADVTXD_MAC_TSTAMP\t\t0x00080000 /* IEEE1588 time stamp */\n#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */\n#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK\t0x000001FF /* IPSec ESP length */\n#define IXGBE_ADVTXD_DTYP_MASK\t\t0x00F00000 /* DTYP mask */\n#define IXGBE_ADVTXD_DTYP_CTXT\t\t0x00200000 /* Adv Context Desc */\n#define IXGBE_ADVTXD_DTYP_DATA\t\t0x00300000 /* Adv Data Descriptor */\n#define IXGBE_ADVTXD_DCMD_EOP\t\tIXGBE_TXD_CMD_EOP /* End of Packet */\n#define IXGBE_ADVTXD_DCMD_IFCS\t\tIXGBE_TXD_CMD_IFCS /* Insert FCS */\n#define IXGBE_ADVTXD_DCMD_RS\t\tIXGBE_TXD_CMD_RS /* Report Status */\n#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI\t0x10000000 /* DDP hdr type or iSCSI */\n#define IXGBE_ADVTXD_DCMD_DEXT\t\tIXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */\n#define IXGBE_ADVTXD_DCMD_VLE\t\tIXGBE_TXD_CMD_VLE /* VLAN pkt enable */\n#define IXGBE_ADVTXD_DCMD_TSE\t\t0x80000000 /* TCP Seg enable */\n#define IXGBE_ADVTXD_STAT_DD\t\tIXGBE_TXD_STAT_DD /* Descriptor Done */\n#define IXGBE_ADVTXD_STAT_SN_CRC\t0x00000002 /* NXTSEQ/SEED pres in WB */\n#define IXGBE_ADVTXD_STAT_RSV\t\t0x0000000C /* STA Reserved */\n#define IXGBE_ADVTXD_IDX_SHIFT\t\t4 /* Adv desc Index shift */\n#define IXGBE_ADVTXD_CC\t\t\t0x00000080 /* Check Context */\n#define IXGBE_ADVTXD_POPTS_SHIFT\t8 /* Adv desc POPTS shift */\n#define IXGBE_ADVTXD_POPTS_IXSM\t\t(IXGBE_TXD_POPTS_IXSM << \\\n\t\t\t\t\t IXGBE_ADVTXD_POPTS_SHIFT)\n#define IXGBE_ADVTXD_POPTS_TXSM\t\t(IXGBE_TXD_POPTS_TXSM << \\\n\t\t\t\t\t IXGBE_ADVTXD_POPTS_SHIFT)\n#define IXGBE_ADVTXD_POPTS_ISCO_1ST\t0x00000000 /* 1st TSO of iSCSI PDU */\n#define IXGBE_ADVTXD_POPTS_ISCO_MDL\t0x00000800 /* Middle TSO of iSCSI PDU */\n#define IXGBE_ADVTXD_POPTS_ISCO_LAST\t0x00001000 /* Last TSO of iSCSI PDU */\n/* 1st&Last TSO-full iSCSI PDU */\n#define IXGBE_ADVTXD_POPTS_ISCO_FULL\t0x00001800\n#define IXGBE_ADVTXD_POPTS_RSV\t\t0x00002000 /* POPTS Reserved */\n#define IXGBE_ADVTXD_PAYLEN_SHIFT\t14 /* Adv desc PAYLEN shift */\n#define IXGBE_ADVTXD_MACLEN_SHIFT\t9 /* Adv ctxt desc mac len shift */\n#define IXGBE_ADVTXD_VLAN_SHIFT\t\t16 /* Adv ctxt vlan tag shift */\n#define IXGBE_ADVTXD_TUCMD_IPV4\t\t0x00000400 /* IP Packet Type: 1=IPv4 */\n#define IXGBE_ADVTXD_TUCMD_IPV6\t\t0x00000000 /* IP Packet Type: 0=IPv6 */\n#define IXGBE_ADVTXD_TUCMD_L4T_UDP\t0x00000000 /* L4 Packet TYPE of UDP */\n#define IXGBE_ADVTXD_TUCMD_L4T_TCP\t0x00000800 /* L4 Packet TYPE of TCP */\n#define IXGBE_ADVTXD_TUCMD_L4T_SCTP\t0x00001000 /* L4 Packet TYPE of SCTP */\n#define IXGBE_ADVTXD_TUCMD_MKRREQ\t0x00002000 /* req Markers and CRC */\n#define IXGBE_ADVTXD_POPTS_IPSEC\t0x00000400 /* IPSec offload request */\n#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */\n#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */\n#define IXGBE_ADVTXT_TUCMD_FCOE\t\t0x00008000 /* FCoE Frame Type */\n#define IXGBE_ADVTXD_FCOEF_EOF_MASK\t(0x3 << 10) /* FC EOF index */\n#define IXGBE_ADVTXD_FCOEF_SOF\t\t((1 << 2) << 10) /* FC SOF index */\n#define IXGBE_ADVTXD_FCOEF_PARINC\t((1 << 3) << 10) /* Rel_Off in F_CTL */\n#define IXGBE_ADVTXD_FCOEF_ORIE\t\t((1 << 4) << 10) /* Orientation End */\n#define IXGBE_ADVTXD_FCOEF_ORIS\t\t((1 << 5) << 10) /* Orientation Start */\n#define IXGBE_ADVTXD_FCOEF_EOF_N\t(0x0 << 10) /* 00: EOFn */\n#define IXGBE_ADVTXD_FCOEF_EOF_T\t(0x1 << 10) /* 01: EOFt */\n#define IXGBE_ADVTXD_FCOEF_EOF_NI\t(0x2 << 10) /* 10: EOFni */\n#define IXGBE_ADVTXD_FCOEF_EOF_A\t(0x3 << 10) /* 11: EOFa */\n#define IXGBE_ADVTXD_L4LEN_SHIFT\t8 /* Adv ctxt L4LEN shift */\n#define IXGBE_ADVTXD_MSS_SHIFT\t\t16 /* Adv ctxt MSS shift */\n\n/* Autonegotiation advertised speeds */\ntypedef u32 ixgbe_autoneg_advertised;\n/* Link speed */\ntypedef u32 ixgbe_link_speed;\n#define IXGBE_LINK_SPEED_UNKNOWN\t0\n#define IXGBE_LINK_SPEED_100_FULL\t0x0008\n#define IXGBE_LINK_SPEED_1GB_FULL\t0x0020\n#define IXGBE_LINK_SPEED_10GB_FULL\t0x0080\n#define IXGBE_LINK_SPEED_82598_AUTONEG\t(IXGBE_LINK_SPEED_1GB_FULL | \\\n\t\t\t\t\t IXGBE_LINK_SPEED_10GB_FULL)\n#define IXGBE_LINK_SPEED_82599_AUTONEG\t(IXGBE_LINK_SPEED_100_FULL | \\\n\t\t\t\t\t IXGBE_LINK_SPEED_1GB_FULL | \\\n\t\t\t\t\t IXGBE_LINK_SPEED_10GB_FULL)\n\n\n/* Physical layer type */\ntypedef u32 ixgbe_physical_layer;\n#define IXGBE_PHYSICAL_LAYER_UNKNOWN\t\t0\n#define IXGBE_PHYSICAL_LAYER_10GBASE_T\t\t0x0001\n#define IXGBE_PHYSICAL_LAYER_1000BASE_T\t\t0x0002\n#define IXGBE_PHYSICAL_LAYER_100BASE_TX\t\t0x0004\n#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU\t0x0008\n#define IXGBE_PHYSICAL_LAYER_10GBASE_LR\t\t0x0010\n#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM\t0x0020\n#define IXGBE_PHYSICAL_LAYER_10GBASE_SR\t\t0x0040\n#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4\t0x0080\n#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4\t0x0100\n#define IXGBE_PHYSICAL_LAYER_1000BASE_KX\t0x0200\n#define IXGBE_PHYSICAL_LAYER_1000BASE_BX\t0x0400\n#define IXGBE_PHYSICAL_LAYER_10GBASE_KR\t\t0x0800\n#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI\t0x1000\n#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA\t0x2000\n#define IXGBE_PHYSICAL_LAYER_1000BASE_SX\t0x4000\n\n/* Flow Control Data Sheet defined values\n * Calculation and defines taken from 802.1bb Annex O\n */\n\n/* BitTimes (BT) conversion */\n#define IXGBE_BT2KB(BT)\t\t((BT + (8 * 1024 - 1)) / (8 * 1024))\n#define IXGBE_B2BT(BT)\t\t(BT * 8)\n\n/* Calculate Delay to respond to PFC */\n#define IXGBE_PFC_D\t672\n\n/* Calculate Cable Delay */\n#define IXGBE_CABLE_DC\t5556 /* Delay Copper */\n#define IXGBE_CABLE_DO\t5000 /* Delay Optical */\n\n/* Calculate Interface Delay X540 */\n#define IXGBE_PHY_DC\t25600 /* Delay 10G BASET */\n#define IXGBE_MAC_DC\t8192 /* Delay Copper XAUI interface */\n#define IXGBE_XAUI_DC\t(2 * 2048) /* Delay Copper Phy */\n\n#define IXGBE_ID_X540\t(IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)\n\n/* Calculate Interface Delay 82598, 82599 */\n#define IXGBE_PHY_D\t12800\n#define IXGBE_MAC_D\t4096\n#define IXGBE_XAUI_D\t(2 * 1024)\n\n#define IXGBE_ID\t(IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)\n\n/* Calculate Delay incurred from higher layer */\n#define IXGBE_HD\t6144\n\n/* Calculate PCI Bus delay for low thresholds */\n#define IXGBE_PCI_DELAY\t10000\n\n/* Calculate X540 delay value in bit times */\n#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \\\n\t\t\t((36 * \\\n\t\t\t (IXGBE_B2BT(_max_frame_link) + \\\n\t\t\t IXGBE_PFC_D + \\\n\t\t\t (2 * IXGBE_CABLE_DC) + \\\n\t\t\t (2 * IXGBE_ID_X540) + \\\n\t\t\t IXGBE_HD) / 25 + 1) + \\\n\t\t\t 2 * IXGBE_B2BT(_max_frame_tc))\n\n/* Calculate 82599, 82598 delay value in bit times */\n#define IXGBE_DV(_max_frame_link, _max_frame_tc) \\\n\t\t\t((36 * \\\n\t\t\t (IXGBE_B2BT(_max_frame_link) + \\\n\t\t\t IXGBE_PFC_D + \\\n\t\t\t (2 * IXGBE_CABLE_DC) + \\\n\t\t\t (2 * IXGBE_ID) + \\\n\t\t\t IXGBE_HD) / 25 + 1) + \\\n\t\t\t 2 * IXGBE_B2BT(_max_frame_tc))\n\n/* Calculate low threshold delay values */\n#define IXGBE_LOW_DV_X540(_max_frame_tc) \\\n\t\t\t(2 * IXGBE_B2BT(_max_frame_tc) + \\\n\t\t\t(36 * IXGBE_PCI_DELAY / 25) + 1)\n#define IXGBE_LOW_DV(_max_frame_tc) \\\n\t\t\t(2 * IXGBE_LOW_DV_X540(_max_frame_tc))\n\n/* Software ATR hash keys */\n#define IXGBE_ATR_BUCKET_HASH_KEY\t0x3DAD14E2\n#define IXGBE_ATR_SIGNATURE_HASH_KEY\t0x174D3614\n\n/* Software ATR input stream values and masks */\n#define IXGBE_ATR_HASH_MASK\t\t0x7fff\n#define IXGBE_ATR_L4TYPE_MASK\t\t0x3\n#define IXGBE_ATR_L4TYPE_UDP\t\t0x1\n#define IXGBE_ATR_L4TYPE_TCP\t\t0x2\n#define IXGBE_ATR_L4TYPE_SCTP\t\t0x3\n#define IXGBE_ATR_L4TYPE_IPV6_MASK\t0x4\nenum ixgbe_atr_flow_type {\n\tIXGBE_ATR_FLOW_TYPE_IPV4\t= 0x0,\n\tIXGBE_ATR_FLOW_TYPE_UDPV4\t= 0x1,\n\tIXGBE_ATR_FLOW_TYPE_TCPV4\t= 0x2,\n\tIXGBE_ATR_FLOW_TYPE_SCTPV4\t= 0x3,\n\tIXGBE_ATR_FLOW_TYPE_IPV6\t= 0x4,\n\tIXGBE_ATR_FLOW_TYPE_UDPV6\t= 0x5,\n\tIXGBE_ATR_FLOW_TYPE_TCPV6\t= 0x6,\n\tIXGBE_ATR_FLOW_TYPE_SCTPV6\t= 0x7,\n};\n\n/* Flow Director ATR input struct. */\nunion ixgbe_atr_input {\n\t/*\n\t * Byte layout in order, all values with MSB first:\n\t *\n\t * vm_pool\t- 1 byte\n\t * flow_type\t- 1 byte\n\t * vlan_id\t- 2 bytes\n\t * src_ip\t- 16 bytes\n\t * dst_ip\t- 16 bytes\n\t * src_port\t- 2 bytes\n\t * dst_port\t- 2 bytes\n\t * flex_bytes\t- 2 bytes\n\t * bkt_hash\t- 2 bytes\n\t */\n\tstruct {\n\t\tu8 vm_pool;\n\t\tu8 flow_type;\n\t\t__be16 vlan_id;\n\t\t__be32 dst_ip[4];\n\t\t__be32 src_ip[4];\n\t\t__be16 src_port;\n\t\t__be16 dst_port;\n\t\t__be16 flex_bytes;\n\t\t__be16 bkt_hash;\n\t} formatted;\n\t__be32 dword_stream[11];\n};\n\n/* Flow Director compressed ATR hash input struct */\nunion ixgbe_atr_hash_dword {\n\tstruct {\n\t\tu8 vm_pool;\n\t\tu8 flow_type;\n\t\t__be16 vlan_id;\n\t} formatted;\n\t__be32 ip;\n\tstruct {\n\t\t__be16 src;\n\t\t__be16 dst;\n\t} port;\n\t__be16 flex_bytes;\n\t__be32 dword;\n};\n\n\n/*\n * Unavailable: The FCoE Boot Option ROM is not present in the flash.\n * Disabled: Present; boot order is not set for any targets on the port.\n * Enabled: Present; boot order is set for at least one target on the port.\n */\nenum ixgbe_fcoe_boot_status {\n\tixgbe_fcoe_bootstatus_disabled = 0,\n\tixgbe_fcoe_bootstatus_enabled = 1,\n\tixgbe_fcoe_bootstatus_unavailable = 0xFFFF\n};\n\nenum ixgbe_eeprom_type {\n\tixgbe_eeprom_uninitialized = 0,\n\tixgbe_eeprom_spi,\n\tixgbe_flash,\n\tixgbe_eeprom_none /* No NVM support */\n};\n\nenum ixgbe_mac_type {\n\tixgbe_mac_unknown = 0,\n\tixgbe_mac_82598EB,\n\tixgbe_mac_82599EB,\n\tixgbe_mac_X540,\n\tixgbe_num_macs\n};\n\nenum ixgbe_phy_type {\n\tixgbe_phy_unknown = 0,\n\tixgbe_phy_none,\n\tixgbe_phy_tn,\n\tixgbe_phy_aq,\n\tixgbe_phy_cu_unknown,\n\tixgbe_phy_qt,\n\tixgbe_phy_xaui,\n\tixgbe_phy_nl,\n\tixgbe_phy_sfp_passive_tyco,\n\tixgbe_phy_sfp_passive_unknown,\n\tixgbe_phy_sfp_active_unknown,\n\tixgbe_phy_sfp_avago,\n\tixgbe_phy_sfp_ftl,\n\tixgbe_phy_sfp_ftl_active,\n\tixgbe_phy_sfp_unknown,\n\tixgbe_phy_sfp_intel,\n\tixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/\n\tixgbe_phy_generic\n};\n\n/*\n * SFP+ module type IDs:\n *\n * ID\tModule Type\n * =============\n * 0\tSFP_DA_CU\n * 1\tSFP_SR\n * 2\tSFP_LR\n * 3\tSFP_DA_CU_CORE0 - 82599-specific\n * 4\tSFP_DA_CU_CORE1 - 82599-specific\n * 5\tSFP_SR/LR_CORE0 - 82599-specific\n * 6\tSFP_SR/LR_CORE1 - 82599-specific\n */\nenum ixgbe_sfp_type {\n\tixgbe_sfp_type_da_cu = 0,\n\tixgbe_sfp_type_sr = 1,\n\tixgbe_sfp_type_lr = 2,\n\tixgbe_sfp_type_da_cu_core0 = 3,\n\tixgbe_sfp_type_da_cu_core1 = 4,\n\tixgbe_sfp_type_srlr_core0 = 5,\n\tixgbe_sfp_type_srlr_core1 = 6,\n\tixgbe_sfp_type_da_act_lmt_core0 = 7,\n\tixgbe_sfp_type_da_act_lmt_core1 = 8,\n\tixgbe_sfp_type_1g_cu_core0 = 9,\n\tixgbe_sfp_type_1g_cu_core1 = 10,\n\tixgbe_sfp_type_1g_sx_core0 = 11,\n\tixgbe_sfp_type_1g_sx_core1 = 12,\n\tixgbe_sfp_type_not_present = 0xFFFE,\n\tixgbe_sfp_type_unknown = 0xFFFF\n};\n\nenum ixgbe_media_type {\n\tixgbe_media_type_unknown = 0,\n\tixgbe_media_type_fiber,\n\tixgbe_media_type_fiber_qsfp,\n\tixgbe_media_type_fiber_lco,\n\tixgbe_media_type_copper,\n\tixgbe_media_type_backplane,\n\tixgbe_media_type_cx4,\n\tixgbe_media_type_virtual\n};\n\n/* Flow Control Settings */\nenum ixgbe_fc_mode {\n\tixgbe_fc_none = 0,\n\tixgbe_fc_rx_pause,\n\tixgbe_fc_tx_pause,\n\tixgbe_fc_full,\n\tixgbe_fc_default\n};\n\n/* Smart Speed Settings */\n#define IXGBE_SMARTSPEED_MAX_RETRIES\t3\nenum ixgbe_smart_speed {\n\tixgbe_smart_speed_auto = 0,\n\tixgbe_smart_speed_on,\n\tixgbe_smart_speed_off\n};\n\n/* PCI bus types */\nenum ixgbe_bus_type {\n\tixgbe_bus_type_unknown = 0,\n\tixgbe_bus_type_pci,\n\tixgbe_bus_type_pcix,\n\tixgbe_bus_type_pci_express,\n\tixgbe_bus_type_reserved\n};\n\n/* PCI bus speeds */\nenum ixgbe_bus_speed {\n\tixgbe_bus_speed_unknown\t= 0,\n\tixgbe_bus_speed_33\t= 33,\n\tixgbe_bus_speed_66\t= 66,\n\tixgbe_bus_speed_100\t= 100,\n\tixgbe_bus_speed_120\t= 120,\n\tixgbe_bus_speed_133\t= 133,\n\tixgbe_bus_speed_2500\t= 2500,\n\tixgbe_bus_speed_5000\t= 5000,\n\tixgbe_bus_speed_8000\t= 8000,\n\tixgbe_bus_speed_reserved\n};\n\n/* PCI bus widths */\nenum ixgbe_bus_width {\n\tixgbe_bus_width_unknown\t= 0,\n\tixgbe_bus_width_pcie_x1\t= 1,\n\tixgbe_bus_width_pcie_x2\t= 2,\n\tixgbe_bus_width_pcie_x4\t= 4,\n\tixgbe_bus_width_pcie_x8\t= 8,\n\tixgbe_bus_width_32\t= 32,\n\tixgbe_bus_width_64\t= 64,\n\tixgbe_bus_width_reserved\n};\n\nstruct ixgbe_addr_filter_info {\n\tu32 num_mc_addrs;\n\tu32 rar_used_count;\n\tu32 mta_in_use;\n\tu32 overflow_promisc;\n\tbool user_set_promisc;\n};\n\n/* Bus parameters */\nstruct ixgbe_bus_info {\n\tenum ixgbe_bus_speed speed;\n\tenum ixgbe_bus_width width;\n\tenum ixgbe_bus_type type;\n\n\tu16 func;\n\tu16 lan_id;\n};\n\n/* Flow control parameters */\nstruct ixgbe_fc_info {\n\tu32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */\n\tu32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */\n\tu16 pause_time; /* Flow Control Pause timer */\n\tbool send_xon; /* Flow control send XON */\n\tbool strict_ieee; /* Strict IEEE mode */\n\tbool disable_fc_autoneg; /* Do not autonegotiate FC */\n\tbool fc_was_autonegged; /* Is current_mode the result of autonegging? */\n\tenum ixgbe_fc_mode current_mode; /* FC mode in effect */\n\tenum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */\n};\n\n/* Statistics counters collected by the MAC */\nstruct ixgbe_hw_stats {\n\tu64 crcerrs;\n\tu64 illerrc;\n\tu64 errbc;\n\tu64 mspdc;\n\tu64 mpctotal;\n\tu64 mpc[8];\n\tu64 mlfc;\n\tu64 mrfc;\n\tu64 rlec;\n\tu64 lxontxc;\n\tu64 lxonrxc;\n\tu64 lxofftxc;\n\tu64 lxoffrxc;\n\tu64 pxontxc[8];\n\tu64 pxonrxc[8];\n\tu64 pxofftxc[8];\n\tu64 pxoffrxc[8];\n\tu64 prc64;\n\tu64 prc127;\n\tu64 prc255;\n\tu64 prc511;\n\tu64 prc1023;\n\tu64 prc1522;\n\tu64 gprc;\n\tu64 bprc;\n\tu64 mprc;\n\tu64 gptc;\n\tu64 gorc;\n\tu64 gotc;\n\tu64 rnbc[8];\n\tu64 ruc;\n\tu64 rfc;\n\tu64 roc;\n\tu64 rjc;\n\tu64 mngprc;\n\tu64 mngpdc;\n\tu64 mngptc;\n\tu64 tor;\n\tu64 tpr;\n\tu64 tpt;\n\tu64 ptc64;\n\tu64 ptc127;\n\tu64 ptc255;\n\tu64 ptc511;\n\tu64 ptc1023;\n\tu64 ptc1522;\n\tu64 mptc;\n\tu64 bptc;\n\tu64 xec;\n\tu64 qprc[16];\n\tu64 qptc[16];\n\tu64 qbrc[16];\n\tu64 qbtc[16];\n\tu64 qprdc[16];\n\tu64 pxon2offc[8];\n\tu64 fdirustat_add;\n\tu64 fdirustat_remove;\n\tu64 fdirfstat_fadd;\n\tu64 fdirfstat_fremove;\n\tu64 fdirmatch;\n\tu64 fdirmiss;\n\tu64 fccrc;\n\tu64 fclast;\n\tu64 fcoerpdc;\n\tu64 fcoeprc;\n\tu64 fcoeptc;\n\tu64 fcoedwrc;\n\tu64 fcoedwtc;\n\tu64 fcoe_noddp;\n\tu64 fcoe_noddp_ext_buff;\n\tu64 ldpcec;\n\tu64 pcrc8ec;\n\tu64 b2ospc;\n\tu64 b2ogprc;\n\tu64 o2bgptc;\n\tu64 o2bspc;\n};\n\n/* forward declaration */\nstruct ixgbe_hw;\n\n/* iterator type for walking multicast address lists */\ntypedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,\n\t\t\t\t u32 *vmdq);\n\n/* Function pointer table */\nstruct ixgbe_eeprom_operations {\n\ts32 (*init_params)(struct ixgbe_hw *);\n\ts32 (*read)(struct ixgbe_hw *, u16, u16 *);\n\ts32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);\n\ts32 (*write)(struct ixgbe_hw *, u16, u16);\n\ts32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);\n\ts32 (*validate_checksum)(struct ixgbe_hw *, u16 *);\n\ts32 (*update_checksum)(struct ixgbe_hw *);\n\tu16 (*calc_checksum)(struct ixgbe_hw *);\n};\n\nstruct ixgbe_mac_operations {\n\ts32 (*init_hw)(struct ixgbe_hw *);\n\ts32 (*reset_hw)(struct ixgbe_hw *);\n\ts32 (*start_hw)(struct ixgbe_hw *);\n\ts32 (*clear_hw_cntrs)(struct ixgbe_hw *);\n\tenum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);\n\tu32 (*get_supported_physical_layer)(struct ixgbe_hw *);\n\ts32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);\n\ts32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);\n\ts32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);\n\ts32 (*get_device_caps)(struct ixgbe_hw *, u16 *);\n\ts32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);\n\ts32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *);\n\ts32 (*stop_adapter)(struct ixgbe_hw *);\n\ts32 (*get_bus_info)(struct ixgbe_hw *);\n\tvoid (*set_lan_id)(struct ixgbe_hw *);\n\ts32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);\n\ts32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);\n\ts32 (*setup_sfp)(struct ixgbe_hw *);\n\ts32 (*enable_rx_dma)(struct ixgbe_hw *, u32);\n\ts32 (*disable_sec_rx_path)(struct ixgbe_hw *);\n\ts32 (*enable_sec_rx_path)(struct ixgbe_hw *);\n\ts32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);\n\tvoid (*release_swfw_sync)(struct ixgbe_hw *, u16);\n\n\t/* Link */\n\tvoid (*disable_tx_laser)(struct ixgbe_hw *);\n\tvoid (*enable_tx_laser)(struct ixgbe_hw *);\n\tvoid (*flap_tx_laser)(struct ixgbe_hw *);\n\ts32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);\n\ts32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);\n\ts32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,\n\t\t\t\t bool *);\n\n\t/* Packet Buffer manipulation */\n\tvoid (*setup_rxpba)(struct ixgbe_hw *, int, u32, int);\n\n\t/* LED */\n\ts32 (*led_on)(struct ixgbe_hw *, u32);\n\ts32 (*led_off)(struct ixgbe_hw *, u32);\n\ts32 (*blink_led_start)(struct ixgbe_hw *, u32);\n\ts32 (*blink_led_stop)(struct ixgbe_hw *, u32);\n\n\t/* RAR, Multicast, VLAN */\n\ts32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);\n\ts32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);\n\ts32 (*clear_rar)(struct ixgbe_hw *, u32);\n\ts32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);\n\ts32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);\n\ts32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);\n\ts32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);\n\ts32 (*init_rx_addrs)(struct ixgbe_hw *);\n\ts32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,\n\t\t\t\t ixgbe_mc_addr_itr);\n\ts32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,\n\t\t\t\t ixgbe_mc_addr_itr, bool clear);\n\ts32 (*enable_mc)(struct ixgbe_hw *);\n\ts32 (*disable_mc)(struct ixgbe_hw *);\n\ts32 (*clear_vfta)(struct ixgbe_hw *);\n\ts32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);\n\ts32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *);\n\ts32 (*init_uta_tables)(struct ixgbe_hw *);\n\tvoid (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);\n\tvoid (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);\n\n\t/* Flow Control */\n\ts32 (*fc_enable)(struct ixgbe_hw *);\n\n\t/* Manageability interface */\n\ts32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);\n\ts32 (*get_thermal_sensor_data)(struct ixgbe_hw *);\n\ts32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);\n};\n\nstruct ixgbe_phy_operations {\n\ts32 (*identify)(struct ixgbe_hw *);\n\ts32 (*identify_sfp)(struct ixgbe_hw *);\n\ts32 (*init)(struct ixgbe_hw *);\n\ts32 (*reset)(struct ixgbe_hw *);\n\ts32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);\n\ts32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);\n\ts32 (*setup_link)(struct ixgbe_hw *);\n\ts32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,\n\t\t\t\tbool);\n\ts32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);\n\ts32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);\n\ts32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);\n\ts32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);\n\ts32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);\n\ts32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);\n\tvoid (*i2c_bus_clear)(struct ixgbe_hw *);\n\ts32 (*check_overtemp)(struct ixgbe_hw *);\n};\n\nstruct ixgbe_eeprom_info {\n\tstruct ixgbe_eeprom_operations ops;\n\tenum ixgbe_eeprom_type type;\n\tu32 semaphore_delay;\n\tu16 word_size;\n\tu16 address_bits;\n\tu16 word_page_size;\n};\n\n#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED\t0x01\nstruct ixgbe_mac_info {\n\tstruct ixgbe_mac_operations ops;\n\tenum ixgbe_mac_type type;\n\tu8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];\n\tu8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];\n\tu8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];\n\t/* prefix for World Wide Node Name (WWNN) */\n\tu16 wwnn_prefix;\n\t/* prefix for World Wide Port Name (WWPN) */\n\tu16 wwpn_prefix;\n#define IXGBE_MAX_MTA\t\t\t128\n\tu32 mta_shadow[IXGBE_MAX_MTA];\n\ts32 mc_filter_type;\n\tu32 mcft_size;\n\tu32 vft_size;\n\tu32 num_rar_entries;\n\tu32 rar_highwater;\n\tu32 rx_pb_size;\n\tu32 max_tx_queues;\n\tu32 max_rx_queues;\n\tu32 orig_autoc;\n\tu8 san_mac_rar_index;\n\tu32 orig_autoc2;\n\tu16 max_msix_vectors;\n\tbool arc_subsystem_valid;\n\tbool orig_link_settings_stored;\n\tbool autotry_restart;\n\tu8 flags;\n\tstruct ixgbe_thermal_sensor_data thermal_sensor_data;\n};\n\nstruct ixgbe_phy_info {\n\tstruct ixgbe_phy_operations ops;\n\tenum ixgbe_phy_type type;\n\tu32 addr;\n\tu32 id;\n\tenum ixgbe_sfp_type sfp_type;\n\tbool sfp_setup_needed;\n\tu32 revision;\n\tenum ixgbe_media_type media_type;\n\tbool reset_disable;\n\tixgbe_autoneg_advertised autoneg_advertised;\n\tenum ixgbe_smart_speed smart_speed;\n\tbool smart_speed_active;\n\tbool multispeed_fiber;\n\tbool reset_if_overtemp;\n\tbool qsfp_shared_i2c_bus;\n};\n\n#include \"ixgbe_mbx.h\"\n\nstruct ixgbe_mbx_operations {\n\tvoid (*init_params)(struct ixgbe_hw *hw);\n\ts32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);\n\ts32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);\n\ts32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);\n\ts32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);\n\ts32 (*check_for_msg)(struct ixgbe_hw *, u16);\n\ts32 (*check_for_ack)(struct ixgbe_hw *, u16);\n\ts32 (*check_for_rst)(struct ixgbe_hw *, u16);\n};\n\nstruct ixgbe_mbx_stats {\n\tu32 msgs_tx;\n\tu32 msgs_rx;\n\n\tu32 acks;\n\tu32 reqs;\n\tu32 rsts;\n};\n\nstruct ixgbe_mbx_info {\n\tstruct ixgbe_mbx_operations ops;\n\tstruct ixgbe_mbx_stats stats;\n\tu32 timeout;\n\tu32 udelay;\n\tu32 v2p_mailbox;\n\tu16 size;\n};\n\nstruct ixgbe_hw {\n\tu8 __iomem *hw_addr;\n\tvoid *back;\n\tstruct ixgbe_mac_info mac;\n\tstruct ixgbe_addr_filter_info addr_ctrl;\n\tstruct ixgbe_fc_info fc;\n\tstruct ixgbe_phy_info phy;\n\tstruct ixgbe_eeprom_info eeprom;\n\tstruct ixgbe_bus_info bus;\n\tstruct ixgbe_mbx_info mbx;\n\tu16 device_id;\n\tu16 vendor_id;\n\tu16 subsystem_device_id;\n\tu16 subsystem_vendor_id;\n\tu8 revision_id;\n\tbool adapter_stopped;\n\tbool force_full_reset;\n\tbool allow_unsupported_sfp;\n};\n\n#define ixgbe_call_func(hw, func, params, error) \\\n\t\t(func != NULL) ? func params : error\n\n\n/* Error Codes */\n#define IXGBE_ERR_EEPROM\t\t\t-1\n#define IXGBE_ERR_EEPROM_CHECKSUM\t\t-2\n#define IXGBE_ERR_PHY\t\t\t\t-3\n#define IXGBE_ERR_CONFIG\t\t\t-4\n#define IXGBE_ERR_PARAM\t\t\t\t-5\n#define IXGBE_ERR_MAC_TYPE\t\t\t-6\n#define IXGBE_ERR_UNKNOWN_PHY\t\t\t-7\n#define IXGBE_ERR_LINK_SETUP\t\t\t-8\n#define IXGBE_ERR_ADAPTER_STOPPED\t\t-9\n#define IXGBE_ERR_INVALID_MAC_ADDR\t\t-10\n#define IXGBE_ERR_DEVICE_NOT_SUPPORTED\t\t-11\n#define IXGBE_ERR_MASTER_REQUESTS_PENDING\t-12\n#define IXGBE_ERR_INVALID_LINK_SETTINGS\t\t-13\n#define IXGBE_ERR_AUTONEG_NOT_COMPLETE\t\t-14\n#define IXGBE_ERR_RESET_FAILED\t\t\t-15\n#define IXGBE_ERR_SWFW_SYNC\t\t\t-16\n#define IXGBE_ERR_PHY_ADDR_INVALID\t\t-17\n#define IXGBE_ERR_I2C\t\t\t\t-18\n#define IXGBE_ERR_SFP_NOT_SUPPORTED\t\t-19\n#define IXGBE_ERR_SFP_NOT_PRESENT\t\t-20\n#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT\t-21\n#define IXGBE_ERR_NO_SAN_ADDR_PTR\t\t-22\n#define IXGBE_ERR_FDIR_REINIT_FAILED\t\t-23\n#define IXGBE_ERR_EEPROM_VERSION\t\t-24\n#define IXGBE_ERR_NO_SPACE\t\t\t-25\n#define IXGBE_ERR_OVERTEMP\t\t\t-26\n#define IXGBE_ERR_FC_NOT_NEGOTIATED\t\t-27\n#define IXGBE_ERR_FC_NOT_SUPPORTED\t\t-28\n#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE\t-30\n#define IXGBE_ERR_PBA_SECTION\t\t\t-31\n#define IXGBE_ERR_INVALID_ARGUMENT\t\t-32\n#define IXGBE_ERR_HOST_INTERFACE_COMMAND\t-33\n#define IXGBE_ERR_OUT_OF_MEM\t\t\t-34\n\n#define IXGBE_NOT_IMPLEMENTED\t\t\t0x7FFFFFFF\n\n#define UNREFERENCED_XPARAMETER\n\n#endif /* _IXGBE_TYPE_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_x540.c", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"ixgbe_x540.h\"\n#include \"ixgbe_type.h\"\n#include \"ixgbe_api.h\"\n#include \"ixgbe_common.h\"\n#include \"ixgbe_phy.h\"\n\nstatic s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);\nstatic s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);\nstatic s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);\nstatic void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);\n\n/**\n * ixgbe_init_ops_X540 - Inits func ptrs and MAC type\n * @hw: pointer to hardware structure\n *\n * Initialize the function pointers and assign the MAC type for X540.\n * Does not touch the hardware.\n **/\ns32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_mac_info *mac = &hw->mac;\n\tstruct ixgbe_phy_info *phy = &hw->phy;\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\ts32 ret_val;\n\n\tret_val = ixgbe_init_phy_ops_generic(hw);\n\tret_val = ixgbe_init_ops_generic(hw);\n\n\n\t/* EEPROM */\n\teeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;\n\teeprom->ops.read = &ixgbe_read_eerd_X540;\n\teeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;\n\teeprom->ops.write = &ixgbe_write_eewr_X540;\n\teeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;\n\teeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;\n\teeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;\n\teeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;\n\n\t/* PHY */\n\tphy->ops.init = &ixgbe_init_phy_ops_generic;\n\tphy->ops.reset = NULL;\n\n\t/* MAC */\n\tmac->ops.reset_hw = &ixgbe_reset_hw_X540;\n\tmac->ops.get_media_type = &ixgbe_get_media_type_X540;\n\tmac->ops.get_supported_physical_layer =\n\t\t\t\t &ixgbe_get_supported_physical_layer_X540;\n\tmac->ops.read_analog_reg8 = NULL;\n\tmac->ops.write_analog_reg8 = NULL;\n\tmac->ops.start_hw = &ixgbe_start_hw_X540;\n\tmac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;\n\tmac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;\n\tmac->ops.get_device_caps = &ixgbe_get_device_caps_generic;\n\tmac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;\n\tmac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;\n\tmac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;\n\tmac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;\n\tmac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;\n\tmac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;\n\n\t/* RAR, Multicast, VLAN */\n\tmac->ops.set_vmdq = &ixgbe_set_vmdq_generic;\n\tmac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;\n\tmac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;\n\tmac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;\n\tmac->rar_highwater = 1;\n\tmac->ops.set_vfta = &ixgbe_set_vfta_generic;\n\tmac->ops.set_vlvf = &ixgbe_set_vlvf_generic;\n\tmac->ops.clear_vfta = &ixgbe_clear_vfta_generic;\n\tmac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;\n\tmac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;\n\tmac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;\n\n\t/* Link */\n\tmac->ops.get_link_capabilities =\n\t\t\t\t&ixgbe_get_copper_link_capabilities_generic;\n\tmac->ops.setup_link = &ixgbe_setup_mac_link_X540;\n\tmac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;\n\tmac->ops.check_link = &ixgbe_check_mac_link_generic;\n\n\tmac->mcft_size\t\t= 128;\n\tmac->vft_size\t\t= 128;\n\tmac->num_rar_entries\t= 128;\n\tmac->rx_pb_size\t\t= 384;\n\tmac->max_tx_queues\t= 128;\n\tmac->max_rx_queues\t= 128;\n\tmac->max_msix_vectors\t= ixgbe_get_pcie_msix_count_generic(hw);\n\n\t/*\n\t * FWSM register\n\t * ARC supported; valid only if manageability features are\n\t * enabled.\n\t */\n\tmac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &\n\t\t\t\t IXGBE_FWSM_MODE_MASK) ? true : false;\n\n\t//hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;\n\n\t/* LEDs */\n\tmac->ops.blink_led_start = ixgbe_blink_led_start_X540;\n\tmac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;\n\n\t/* Manageability interface */\n\tmac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;\n\n\treturn ret_val;\n}\n\n/**\n * ixgbe_get_link_capabilities_X540 - Determines link capabilities\n * @hw: pointer to hardware structure\n * @speed: pointer to link speed\n * @autoneg: true when autoneg or autotry is enabled\n *\n * Determines the link capabilities by reading the AUTOC register.\n **/\ns32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed,\n\t\t\t\t bool *autoneg)\n{\n\tixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_get_media_type_X540 - Get media type\n * @hw: pointer to hardware structure\n *\n * Returns the media type (fiber, copper, backplane)\n **/\nenum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)\n{\n\treturn ixgbe_media_type_copper;\n}\n\n/**\n * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities\n * @hw: pointer to hardware structure\n * @speed: new link speed\n * @autoneg: true if autonegotiation enabled\n * @autoneg_wait_to_complete: true when waiting for completion is needed\n **/\ns32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,\n\t\t\t ixgbe_link_speed speed, bool autoneg,\n\t\t\t bool autoneg_wait_to_complete)\n{\n\treturn hw->phy.ops.setup_link_speed(hw, speed, autoneg,\n\t\t\t\t\t autoneg_wait_to_complete);\n}\n\n/**\n * ixgbe_reset_hw_X540 - Perform hardware reset\n * @hw: pointer to hardware structure\n *\n * Resets the hardware by resetting the transmit and receive units, masks\n * and clears all interrupts, and perform a reset.\n **/\ns32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)\n{\n\ts32 status = 0;\n\n\t/*\n\t * Userland DPDK takes the ownershiop of device\n\t * Kernel driver here used as the simple path for ethtool only\n\t * Won't real reset device anyway\n\t */\n#if 0\n\tu32 ctrl, i;\n\n\t/* Call adapter stop to disable tx/rx and clear interrupts */\n\tstatus = hw->mac.ops.stop_adapter(hw);\n\tif (status != 0)\n\t\tgoto reset_hw_out;\n\n\t/* flush pending Tx transactions */\n\tixgbe_clear_tx_pending(hw);\n\nmac_reset_top:\n\tctrl = IXGBE_CTRL_RST;\n\tctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);\n\tIXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\t/* Poll for reset bit to self-clear indicating reset is complete */\n\tfor (i = 0; i < 10; i++) {\n\t\tudelay(1);\n\t\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);\n\t\tif (!(ctrl & IXGBE_CTRL_RST_MASK))\n\t\t\tbreak;\n\t}\n\n\tif (ctrl & IXGBE_CTRL_RST_MASK) {\n\t\tstatus = IXGBE_ERR_RESET_FAILED;\n\t\thw_dbg(hw, \"Reset polling failed to complete.\\n\");\n\t}\n\tmsleep(100);\n\n\t/*\n\t * Double resets are required for recovery from certain error\n\t * conditions. Between resets, it is necessary to stall to allow time\n\t * for any pending HW events to complete.\n\t */\n\tif (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {\n\t\thw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;\n\t\tgoto mac_reset_top;\n\t}\n\n\t/* Set the Rx packet buffer size. */\n\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);\n\n#endif\n\n\t/* Store the permanent mac address */\n\thw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);\n\n\t/*\n\t * Store MAC address from RAR0, clear receive address registers, and\n\t * clear the multicast table. Also reset num_rar_entries to 128,\n\t * since we modify this value when programming the SAN MAC address.\n\t */\n\thw->mac.num_rar_entries = 128;\n\thw->mac.ops.init_rx_addrs(hw);\n\n\t/* Store the permanent SAN mac address */\n\thw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);\n\n\t/* Add the SAN MAC address to the RAR only if it's a valid address */\n\tif (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {\n\t\thw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,\n\t\t\t\t hw->mac.san_addr, 0, IXGBE_RAH_AV);\n\n\t\t/* Save the SAN MAC RAR index */\n\t\thw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;\n\n\t\t/* Reserve the last RAR for the SAN MAC address */\n\t\thw->mac.num_rar_entries--;\n\t}\n\n\t/* Store the alternative WWNN/WWPN prefix */\n\thw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,\n\t\t\t\t &hw->mac.wwpn_prefix);\n\n//reset_hw_out:\n\treturn status;\n}\n\n/**\n * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx\n * @hw: pointer to hardware structure\n *\n * Starts the hardware using the generic start_hw function\n * and the generation start_hw function.\n * Then performs revision-specific operations, if any.\n **/\ns32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)\n{\n\ts32 ret_val = 0;\n\n\tret_val = ixgbe_start_hw_generic(hw);\n\tif (ret_val != 0)\n\t\tgoto out;\n\n\tret_val = ixgbe_start_hw_gen2(hw);\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type\n * @hw: pointer to hardware structure\n *\n * Determines physical layer capabilities of the current configuration.\n **/\nu32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)\n{\n\tu32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n\tu16 ext_ability = 0;\n\n\thw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,\n\tIXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);\n\tif (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)\n\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;\n\tif (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)\n\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;\n\tif (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)\n\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;\n\n\treturn physical_layer;\n}\n\n/**\n * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params\n * @hw: pointer to hardware structure\n *\n * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n * ixgbe_hw struct in order to set up EEPROM access.\n **/\ns32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)\n{\n\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n\tu32 eec;\n\tu16 eeprom_size;\n\n\tif (eeprom->type == ixgbe_eeprom_uninitialized) {\n\t\teeprom->semaphore_delay = 10;\n\t\teeprom->type = ixgbe_flash;\n\n\t\teec = IXGBE_READ_REG(hw, IXGBE_EEC);\n\t\teeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>\n\t\t\t\t IXGBE_EEC_SIZE_SHIFT);\n\t\teeprom->word_size = 1 << (eeprom_size +\n\t\t\t\t\t IXGBE_EEPROM_WORD_SIZE_SHIFT);\n\n\t\thw_dbg(hw, \"Eeprom params: type = %d, size = %d\\n\",\n\t\t\t eeprom->type, eeprom->word_size);\n\t}\n\n\treturn 0;\n}\n\n/**\n * ixgbe_read_eerd_X540- Read EEPROM word using EERD\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @data: word read from the EEPROM\n *\n * Reads a 16 bit word from the EEPROM using the EERD register.\n **/\ns32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)\n{\n\ts32 status = 0;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n\t 0)\n\t\tstatus = ixgbe_read_eerd_generic(hw, offset, data);\n\telse\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\treturn status;\n}\n\n/**\n * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to read\n * @words: number of words\n * @data: word(s) read from the EEPROM\n *\n * Reads a 16 bit word(s) from the EEPROM using the EERD register.\n **/\ns32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,\n\t\t\t\tu16 offset, u16 words, u16 *data)\n{\n\ts32 status = 0;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n\t 0)\n\t\tstatus = ixgbe_read_eerd_buffer_generic(hw, offset,\n\t\t\t\t\t\t\twords, data);\n\telse\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\treturn status;\n}\n\n/**\n * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to write\n * @data: word write to the EEPROM\n *\n * Write a 16 bit word to the EEPROM using the EEWR register.\n **/\ns32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)\n{\n\ts32 status = 0;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n\t 0)\n\t\tstatus = ixgbe_write_eewr_generic(hw, offset, data);\n\telse\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\treturn status;\n}\n\n/**\n * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR\n * @hw: pointer to hardware structure\n * @offset: offset of word in the EEPROM to write\n * @words: number of words\n * @data: word(s) write to the EEPROM\n *\n * Write a 16 bit word(s) to the EEPROM using the EEWR register.\n **/\ns32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,\n\t\t\t\t u16 offset, u16 words, u16 *data)\n{\n\ts32 status = 0;\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n\t 0)\n\t\tstatus = ixgbe_write_eewr_buffer_generic(hw, offset,\n\t\t\t\t\t\t\t words, data);\n\telse\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\treturn status;\n}\n\n/**\n * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum\n *\n * This function does not use synchronization for EERD and EEWR. It can\n * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.\n *\n * @hw: pointer to hardware structure\n **/\nu16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)\n{\n\tu16 i;\n\tu16 j;\n\tu16 checksum = 0;\n\tu16 length = 0;\n\tu16 pointer = 0;\n\tu16 word = 0;\n\n\t/*\n\t * Do not use hw->eeprom.ops.read because we do not want to take\n\t * the synchronization semaphores here. Instead use\n\t * ixgbe_read_eerd_generic\n\t */\n\n\t/* Include 0x0-0x3F in the checksum */\n\tfor (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {\n\t\tif (ixgbe_read_eerd_generic(hw, i, &word) != 0) {\n\t\t\thw_dbg(hw, \"EEPROM read failed\\n\");\n\t\t\tbreak;\n\t\t}\n\t\tchecksum += word;\n\t}\n\n\t/*\n\t * Include all data from pointers 0x3, 0x6-0xE. This excludes the\n\t * FW, PHY module, and PCIe Expansion/Option ROM pointers.\n\t */\n\tfor (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {\n\t\tif (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)\n\t\t\tcontinue;\n\n\t\tif (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) {\n\t\t\thw_dbg(hw, \"EEPROM read failed\\n\");\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Skip pointer section if the pointer is invalid. */\n\t\tif (pointer == 0xFFFF || pointer == 0 ||\n\t\t pointer >= hw->eeprom.word_size)\n\t\t\tcontinue;\n\n\t\tif (ixgbe_read_eerd_generic(hw, pointer, &length) !=\n\t\t 0) {\n\t\t\thw_dbg(hw, \"EEPROM read failed\\n\");\n\t\t\tbreak;\n\t\t}\n\n\t\t/* Skip pointer section if length is invalid. */\n\t\tif (length == 0xFFFF || length == 0 ||\n\t\t (pointer + length) >= hw->eeprom.word_size)\n\t\t\tcontinue;\n\n\t\tfor (j = pointer+1; j <= pointer+length; j++) {\n\t\t\tif (ixgbe_read_eerd_generic(hw, j, &word) !=\n\t\t\t 0) {\n\t\t\t\thw_dbg(hw, \"EEPROM read failed\\n\");\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tchecksum += word;\n\t\t}\n\t}\n\n\tchecksum = (u16)IXGBE_EEPROM_SUM - checksum;\n\n\treturn checksum;\n}\n\n/**\n * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum\n * @hw: pointer to hardware structure\n * @checksum_val: calculated checksum\n *\n * Performs checksum calculation and validates the EEPROM checksum. If the\n * caller does not need checksum_val, the value can be NULL.\n **/\ns32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,\n\t\t\t\t\tu16 *checksum_val)\n{\n\ts32 status;\n\tu16 checksum;\n\tu16 read_checksum = 0;\n\n\t/*\n\t * Read the first word from the EEPROM. If this times out or fails, do\n\t * not continue or we could be in for a very long wait while every\n\t * EEPROM read fails\n\t */\n\tstatus = hw->eeprom.ops.read(hw, 0, &checksum);\n\n\tif (status != 0) {\n\t\thw_dbg(hw, \"EEPROM read failed\\n\");\n\t\tgoto out;\n\t}\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n\t 0) {\n\t\tchecksum = hw->eeprom.ops.calc_checksum(hw);\n\n\t\t/*\n\t\t * Do not use hw->eeprom.ops.read because we do not want to take\n\t\t * the synchronization semaphores twice here.\n\t\t*/\n\t\tixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,\n\t\t\t\t\t&read_checksum);\n\n\t\t/*\n\t\t * Verify read checksum from EEPROM is the same as\n\t\t * calculated checksum\n\t\t */\n\t\tif (read_checksum != checksum)\n\t\t\tstatus = IXGBE_ERR_EEPROM_CHECKSUM;\n\n\t\t/* If the user cares, return the calculated checksum */\n\t\tif (checksum_val)\n\t\t\t*checksum_val = checksum;\n\t} else {\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\t}\n\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash\n * @hw: pointer to hardware structure\n *\n * After writing EEPROM to shadow RAM using EEWR register, software calculates\n * checksum and updates the EEPROM and instructs the hardware to update\n * the flash.\n **/\ns32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)\n{\n\ts32 status;\n\tu16 checksum;\n\n\t/*\n\t * Read the first word from the EEPROM. If this times out or fails, do\n\t * not continue or we could be in for a very long wait while every\n\t * EEPROM read fails\n\t */\n\tstatus = hw->eeprom.ops.read(hw, 0, &checksum);\n\n\tif (status != 0)\n\t\thw_dbg(hw, \"EEPROM read failed\\n\");\n\n\tif (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==\n\t 0) {\n\t\tchecksum = hw->eeprom.ops.calc_checksum(hw);\n\n\t\t/*\n\t\t * Do not use hw->eeprom.ops.write because we do not want to\n\t\t * take the synchronization semaphores twice here.\n\t\t*/\n\t\tstatus = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,\n\t\t\t\t\t\t checksum);\n\n\tif (status == 0)\n\t\tstatus = ixgbe_update_flash_X540(hw);\n\telse\n\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n\t}\n\n\thw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);\n\n\treturn status;\n}\n\n/**\n * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device\n * @hw: pointer to hardware structure\n *\n * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy\n * EEPROM from shadow RAM to the flash device.\n **/\nstatic s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)\n{\n\tu32 flup;\n\ts32 status = IXGBE_ERR_EEPROM;\n\n\tstatus = ixgbe_poll_flash_update_done_X540(hw);\n\tif (status == IXGBE_ERR_EEPROM) {\n\t\thw_dbg(hw, \"Flash update time out\\n\");\n\t\tgoto out;\n\t}\n\n\tflup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;\n\tIXGBE_WRITE_REG(hw, IXGBE_EEC, flup);\n\n\tstatus = ixgbe_poll_flash_update_done_X540(hw);\n\tif (status == 0)\n\t\thw_dbg(hw, \"Flash update complete\\n\");\n\telse\n\t\thw_dbg(hw, \"Flash update time out\\n\");\n\n\tif (hw->revision_id == 0) {\n\t\tflup = IXGBE_READ_REG(hw, IXGBE_EEC);\n\n\t\tif (flup & IXGBE_EEC_SEC1VAL) {\n\t\t\tflup |= IXGBE_EEC_FLUP;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_EEC, flup);\n\t\t}\n\n\t\tstatus = ixgbe_poll_flash_update_done_X540(hw);\n\t\tif (status == 0)\n\t\t\thw_dbg(hw, \"Flash update complete\\n\");\n\t\telse\n\t\t\thw_dbg(hw, \"Flash update time out\\n\");\n\t}\nout:\n\treturn status;\n}\n\n/**\n * ixgbe_poll_flash_update_done_X540 - Poll flash update status\n * @hw: pointer to hardware structure\n *\n * Polls the FLUDONE (bit 26) of the EEC Register to determine when the\n * flash update is done.\n **/\nstatic s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)\n{\n\tu32 i;\n\tu32 reg;\n\ts32 status = IXGBE_ERR_EEPROM;\n\n\tfor (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {\n\t\treg = IXGBE_READ_REG(hw, IXGBE_EEC);\n\t\tif (reg & IXGBE_EEC_FLUDONE) {\n\t\t\tstatus = 0;\n\t\t\tbreak;\n\t\t}\n\t\tudelay(5);\n\t}\n\treturn status;\n}\n\n/**\n * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to acquire\n *\n * Acquires the SWFW semaphore thought the SW_FW_SYNC register for\n * the specified function (CSR, PHY0, PHY1, NVM, Flash)\n **/\ns32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)\n{\n\tu32 swfw_sync;\n\tu32 swmask = mask;\n\tu32 fwmask = mask << 5;\n\tu32 hwmask = 0;\n\tu32 timeout = 200;\n\tu32 i;\n\ts32 ret_val = 0;\n\n\tif (swmask == IXGBE_GSSR_EEP_SM)\n\t\thwmask = IXGBE_GSSR_FLASH_SM;\n\n\t/* SW only mask doesn't have FW bit pair */\n\tif (swmask == IXGBE_GSSR_SW_MNG_SM)\n\t\tfwmask = 0;\n\n\tfor (i = 0; i < timeout; i++) {\n\t\t/*\n\t\t * SW NVM semaphore bit is used for access to all\n\t\t * SW_FW_SYNC bits (not just NVM)\n\t\t */\n\t\tif (ixgbe_get_swfw_sync_semaphore(hw)) {\n\t\t\tret_val = IXGBE_ERR_SWFW_SYNC;\n\t\t\tgoto out;\n\t\t}\n\n\t\tswfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\n\t\tif (!(swfw_sync & (fwmask | swmask | hwmask))) {\n\t\t\tswfw_sync |= swmask;\n\t\t\tIXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);\n\t\t\tixgbe_release_swfw_sync_semaphore(hw);\n\t\t\tmsleep(5);\n\t\t\tgoto out;\n\t\t} else {\n\t\t\t/*\n\t\t\t * Firmware currently using resource (fwmask), hardware\n\t\t\t * currently using resource (hwmask), or other software\n\t\t\t * thread currently using resource (swmask)\n\t\t\t */\n\t\t\tixgbe_release_swfw_sync_semaphore(hw);\n\t\t\tmsleep(5);\n\t\t}\n\t}\n\n\t/* Failed to get SW only semaphore */\n\tif (swmask == IXGBE_GSSR_SW_MNG_SM) {\n\t\tret_val = IXGBE_ERR_SWFW_SYNC;\n\t\tgoto out;\n\t}\n\n\t/* If the resource is not released by the FW/HW the SW can assume that\n\t * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)\n\t * of the requested resource(s) while ignoring the corresponding FW/HW\n\t * bits in the SW_FW_SYNC register.\n\t */\n\tswfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\n\tif (swfw_sync & (fwmask | hwmask)) {\n\t\tif (ixgbe_get_swfw_sync_semaphore(hw)) {\n\t\t\tret_val = IXGBE_ERR_SWFW_SYNC;\n\t\t\tgoto out;\n\t\t}\n\n\t\tswfw_sync |= swmask;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);\n\t\tixgbe_release_swfw_sync_semaphore(hw);\n\t\tmsleep(5);\n\t}\n\nout:\n\treturn ret_val;\n}\n\n/**\n * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to release\n *\n * Releases the SWFW semaphore through the SW_FW_SYNC register\n * for the specified function (CSR, PHY0, PHY1, EVM, Flash)\n **/\nvoid ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)\n{\n\tu32 swfw_sync;\n\tu32 swmask = mask;\n\n\tixgbe_get_swfw_sync_semaphore(hw);\n\n\tswfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\n\tswfw_sync &= ~swmask;\n\tIXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);\n\n\tixgbe_release_swfw_sync_semaphore(hw);\n\tmsleep(5);\n}\n\n/**\n * ixgbe_get_nvm_semaphore - Get hardware semaphore\n * @hw: pointer to hardware structure\n *\n * Sets the hardware semaphores so SW/FW can gain control of shared resources\n **/\nstatic s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)\n{\n\ts32 status = IXGBE_ERR_EEPROM;\n\tu32 timeout = 2000;\n\tu32 i;\n\tu32 swsm;\n\n\t/* Get SMBI software semaphore between device drivers first */\n\tfor (i = 0; i < timeout; i++) {\n\t\t/*\n\t\t * If the SMBI bit is 0 when we read it, then the bit will be\n\t\t * set and we have the semaphore\n\t\t */\n\t\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\t\tif (!(swsm & IXGBE_SWSM_SMBI)) {\n\t\t\tstatus = 0;\n\t\t\tbreak;\n\t\t}\n\t\tudelay(50);\n\t}\n\n\t/* Now get the semaphore between SW/FW through the REGSMP bit */\n\tif (status == 0) {\n\t\tfor (i = 0; i < timeout; i++) {\n\t\t\tswsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\n\t\t\tif (!(swsm & IXGBE_SWFW_REGSMP))\n\t\t\t\tbreak;\n\n\t\t\tudelay(50);\n\t\t}\n\n\t\t/*\n\t\t * Release semaphores and return error if SW NVM semaphore\n\t\t * was not granted because we don't have access to the EEPROM\n\t\t */\n\t\tif (i >= timeout) {\n\t\t\thw_dbg(hw, \"REGSMP Software NVM semaphore not \"\n\t\t\t\t \"granted.\\n\");\n\t\t\tixgbe_release_swfw_sync_semaphore(hw);\n\t\t\tstatus = IXGBE_ERR_EEPROM;\n\t\t}\n\t} else {\n\t\thw_dbg(hw, \"Software semaphore SMBI between device drivers \"\n\t\t\t \"not granted.\\n\");\n\t}\n\n\treturn status;\n}\n\n/**\n * ixgbe_release_nvm_semaphore - Release hardware semaphore\n * @hw: pointer to hardware structure\n *\n * This function clears hardware semaphore bits.\n **/\nstatic void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)\n{\n\tu32 swsm;\n\n\t/* Release both semaphores by writing 0 to the bits REGSMP and SMBI */\n\n\tswsm = IXGBE_READ_REG(hw, IXGBE_SWSM);\n\tswsm &= ~IXGBE_SWSM_SMBI;\n\tIXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);\n\n\tswsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\n\tswsm &= ~IXGBE_SWFW_REGSMP;\n\tIXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);\n\n\tIXGBE_WRITE_FLUSH(hw);\n}\n\n/**\n * ixgbe_blink_led_start_X540 - Blink LED based on index.\n * @hw: pointer to hardware structure\n * @index: led number to blink\n *\n * Devices that implement the version 2 interface:\n * X540\n **/\ns32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)\n{\n\tu32 macc_reg;\n\tu32 ledctl_reg;\n\tixgbe_link_speed speed;\n\tbool link_up;\n\n\t/*\n\t * Link should be up in order for the blink bit in the LED control\n\t * register to work. Force link and speed in the MAC if link is down.\n\t * This will be reversed when we stop the blinking.\n\t */\n\thw->mac.ops.check_link(hw, &speed, &link_up, false);\n\tif (link_up == false) {\n\t\tmacc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);\n\t\tmacc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;\n\t\tIXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);\n\t}\n\t/* Set the LED to LINK_UP + BLINK. */\n\tledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\tledctl_reg &= ~IXGBE_LED_MODE_MASK(index);\n\tledctl_reg |= IXGBE_LED_BLINK(index);\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n\n/**\n * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.\n * @hw: pointer to hardware structure\n * @index: led number to stop blinking\n *\n * Devices that implement the version 2 interface:\n * X540\n **/\ns32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)\n{\n\tu32 macc_reg;\n\tu32 ledctl_reg;\n\n\t/* Restore the LED to its default value. */\n\tledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);\n\tledctl_reg &= ~IXGBE_LED_MODE_MASK(index);\n\tledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);\n\tledctl_reg &= ~IXGBE_LED_BLINK(index);\n\tIXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);\n\n\t/* Unforce link and speed in the MAC. */\n\tmacc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);\n\tmacc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);\n\tIXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);\n\tIXGBE_WRITE_FLUSH(hw);\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_x540.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _IXGBE_X540_H_\n#define _IXGBE_X540_H_\n\n#include \"ixgbe_type.h\"\n\ns32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,\n\t\t\t\t ixgbe_link_speed *speed, bool *autoneg);\nenum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw);\ns32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n\t\t\t bool autoneg, bool link_up_wait_to_complete);\ns32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw);\ns32 ixgbe_start_hw_X540(struct ixgbe_hw *hw);\nu32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw);\n\ns32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw);\ns32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data);\ns32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, u16 offset, u16 words,\n\t\t\t\tu16 *data);\ns32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data);\ns32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, u16 offset, u16 words,\n\t\t\t\t u16 *data);\ns32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw);\ns32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val);\nu16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);\n\ns32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);\nvoid ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);\n\ns32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index);\ns32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index);\n#endif /* _IXGBE_X540_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/kcompat.c", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#include \"ixgbe.h\"\n#include \"kcompat.h\"\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,8) )\n/* From lib/vsprintf.c */\n#include \n\nstatic int skip_atoi(const char **s)\n{\n\tint i=0;\n\n\twhile (isdigit(**s))\n\t\ti = i*10 + *((*s)++) - '0';\n\treturn i;\n}\n\n#define _kc_ZEROPAD\t1\t\t/* pad with zero */\n#define _kc_SIGN\t2\t\t/* unsigned/signed long */\n#define _kc_PLUS\t4\t\t/* show plus */\n#define _kc_SPACE\t8\t\t/* space if plus */\n#define _kc_LEFT\t16\t\t/* left justified */\n#define _kc_SPECIAL\t32\t\t/* 0x */\n#define _kc_LARGE\t64\t\t/* use 'ABCDEF' instead of 'abcdef' */\n\nstatic char * number(char * buf, char * end, long long num, int base, int size, int precision, int type)\n{\n\tchar c,sign,tmp[66];\n\tconst char *digits;\n\tconst char small_digits[] = \"0123456789abcdefghijklmnopqrstuvwxyz\";\n\tconst char large_digits[] = \"0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ\";\n\tint i;\n\n\tdigits = (type & _kc_LARGE) ? large_digits : small_digits;\n\tif (type & _kc_LEFT)\n\t\ttype &= ~_kc_ZEROPAD;\n\tif (base < 2 || base > 36)\n\t\treturn 0;\n\tc = (type & _kc_ZEROPAD) ? '0' : ' ';\n\tsign = 0;\n\tif (type & _kc_SIGN) {\n\t\tif (num < 0) {\n\t\t\tsign = '-';\n\t\t\tnum = -num;\n\t\t\tsize--;\n\t\t} else if (type & _kc_PLUS) {\n\t\t\tsign = '+';\n\t\t\tsize--;\n\t\t} else if (type & _kc_SPACE) {\n\t\t\tsign = ' ';\n\t\t\tsize--;\n\t\t}\n\t}\n\tif (type & _kc_SPECIAL) {\n\t\tif (base == 16)\n\t\t\tsize -= 2;\n\t\telse if (base == 8)\n\t\t\tsize--;\n\t}\n\ti = 0;\n\tif (num == 0)\n\t\ttmp[i++]='0';\n\telse while (num != 0)\n\t\ttmp[i++] = digits[do_div(num,base)];\n\tif (i > precision)\n\t\tprecision = i;\n\tsize -= precision;\n\tif (!(type&(_kc_ZEROPAD+_kc_LEFT))) {\n\t\twhile(size-->0) {\n\t\t\tif (buf <= end)\n\t\t\t\t*buf = ' ';\n\t\t\t++buf;\n\t\t}\n\t}\n\tif (sign) {\n\t\tif (buf <= end)\n\t\t\t*buf = sign;\n\t\t++buf;\n\t}\n\tif (type & _kc_SPECIAL) {\n\t\tif (base==8) {\n\t\t\tif (buf <= end)\n\t\t\t\t*buf = '0';\n\t\t\t++buf;\n\t\t} else if (base==16) {\n\t\t\tif (buf <= end)\n\t\t\t\t*buf = '0';\n\t\t\t++buf;\n\t\t\tif (buf <= end)\n\t\t\t\t*buf = digits[33];\n\t\t\t++buf;\n\t\t}\n\t}\n\tif (!(type & _kc_LEFT)) {\n\t\twhile (size-- > 0) {\n\t\t\tif (buf <= end)\n\t\t\t\t*buf = c;\n\t\t\t++buf;\n\t\t}\n\t}\n\twhile (i < precision--) {\n\t\tif (buf <= end)\n\t\t\t*buf = '0';\n\t\t++buf;\n\t}\n\twhile (i-- > 0) {\n\t\tif (buf <= end)\n\t\t\t*buf = tmp[i];\n\t\t++buf;\n\t}\n\twhile (size-- > 0) {\n\t\tif (buf <= end)\n\t\t\t*buf = ' ';\n\t\t++buf;\n\t}\n\treturn buf;\n}\n\nint _kc_vsnprintf(char *buf, size_t size, const char *fmt, va_list args)\n{\n\tint len;\n\tunsigned long long num;\n\tint i, base;\n\tchar *str, *end, c;\n\tconst char *s;\n\n\tint flags;\t\t/* flags to number() */\n\n\tint field_width;\t/* width of output field */\n\tint precision;\t\t/* min. # of digits for integers; max\n\t\t\t\t number of chars for from string */\n\tint qualifier;\t\t/* 'h', 'l', or 'L' for integer fields */\n\t\t\t\t/* 'z' support added 23/7/1999 S.H. */\n\t\t\t\t/* 'z' changed to 'Z' --davidm 1/25/99 */\n\n\tstr = buf;\n\tend = buf + size - 1;\n\n\tif (end < buf - 1) {\n\t\tend = ((void *) -1);\n\t\tsize = end - buf + 1;\n\t}\n\n\tfor (; *fmt ; ++fmt) {\n\t\tif (*fmt != '%') {\n\t\t\tif (str <= end)\n\t\t\t\t*str = *fmt;\n\t\t\t++str;\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* process flags */\n\t\tflags = 0;\n\t\trepeat:\n\t\t\t++fmt;\t\t/* this also skips first '%' */\n\t\t\tswitch (*fmt) {\n\t\t\t\tcase '-': flags |= _kc_LEFT; goto repeat;\n\t\t\t\tcase '+': flags |= _kc_PLUS; goto repeat;\n\t\t\t\tcase ' ': flags |= _kc_SPACE; goto repeat;\n\t\t\t\tcase '#': flags |= _kc_SPECIAL; goto repeat;\n\t\t\t\tcase '0': flags |= _kc_ZEROPAD; goto repeat;\n\t\t\t}\n\n\t\t/* get field width */\n\t\tfield_width = -1;\n\t\tif (isdigit(*fmt))\n\t\t\tfield_width = skip_atoi(&fmt);\n\t\telse if (*fmt == '*') {\n\t\t\t++fmt;\n\t\t\t/* it's the next argument */\n\t\t\tfield_width = va_arg(args, int);\n\t\t\tif (field_width < 0) {\n\t\t\t\tfield_width = -field_width;\n\t\t\t\tflags |= _kc_LEFT;\n\t\t\t}\n\t\t}\n\n\t\t/* get the precision */\n\t\tprecision = -1;\n\t\tif (*fmt == '.') {\n\t\t\t++fmt;\n\t\t\tif (isdigit(*fmt))\n\t\t\t\tprecision = skip_atoi(&fmt);\n\t\t\telse if (*fmt == '*') {\n\t\t\t\t++fmt;\n\t\t\t\t/* it's the next argument */\n\t\t\t\tprecision = va_arg(args, int);\n\t\t\t}\n\t\t\tif (precision < 0)\n\t\t\t\tprecision = 0;\n\t\t}\n\n\t\t/* get the conversion qualifier */\n\t\tqualifier = -1;\n\t\tif (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt =='Z') {\n\t\t\tqualifier = *fmt;\n\t\t\t++fmt;\n\t\t}\n\n\t\t/* default base */\n\t\tbase = 10;\n\n\t\tswitch (*fmt) {\n\t\t\tcase 'c':\n\t\t\t\tif (!(flags & _kc_LEFT)) {\n\t\t\t\t\twhile (--field_width > 0) {\n\t\t\t\t\t\tif (str <= end)\n\t\t\t\t\t\t\t*str = ' ';\n\t\t\t\t\t\t++str;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tc = (unsigned char) va_arg(args, int);\n\t\t\t\tif (str <= end)\n\t\t\t\t\t*str = c;\n\t\t\t\t++str;\n\t\t\t\twhile (--field_width > 0) {\n\t\t\t\t\tif (str <= end)\n\t\t\t\t\t\t*str = ' ';\n\t\t\t\t\t++str;\n\t\t\t\t}\n\t\t\t\tcontinue;\n\n\t\t\tcase 's':\n\t\t\t\ts = va_arg(args, char *);\n\t\t\t\tif (!s)\n\t\t\t\t\ts = \"\";\n\n\t\t\t\tlen = strnlen(s, precision);\n\n\t\t\t\tif (!(flags & _kc_LEFT)) {\n\t\t\t\t\twhile (len < field_width--) {\n\t\t\t\t\t\tif (str <= end)\n\t\t\t\t\t\t\t*str = ' ';\n\t\t\t\t\t\t++str;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\tfor (i = 0; i < len; ++i) {\n\t\t\t\t\tif (str <= end)\n\t\t\t\t\t\t*str = *s;\n\t\t\t\t\t++str; ++s;\n\t\t\t\t}\n\t\t\t\twhile (len < field_width--) {\n\t\t\t\t\tif (str <= end)\n\t\t\t\t\t\t*str = ' ';\n\t\t\t\t\t++str;\n\t\t\t\t}\n\t\t\t\tcontinue;\n\n\t\t\tcase 'p':\n\t\t\t\tif (field_width == -1) {\n\t\t\t\t\tfield_width = 2*sizeof(void *);\n\t\t\t\t\tflags |= _kc_ZEROPAD;\n\t\t\t\t}\n\t\t\t\tstr = number(str, end,\n\t\t\t\t\t\t(unsigned long) va_arg(args, void *),\n\t\t\t\t\t\t16, field_width, precision, flags);\n\t\t\t\tcontinue;\n\n\n\t\t\tcase 'n':\n\t\t\t\t/* FIXME:\n\t\t\t\t* What does C99 say about the overflow case here? */\n\t\t\t\tif (qualifier == 'l') {\n\t\t\t\t\tlong * ip = va_arg(args, long *);\n\t\t\t\t\t*ip = (str - buf);\n\t\t\t\t} else if (qualifier == 'Z') {\n\t\t\t\t\tsize_t * ip = va_arg(args, size_t *);\n\t\t\t\t\t*ip = (str - buf);\n\t\t\t\t} else {\n\t\t\t\t\tint * ip = va_arg(args, int *);\n\t\t\t\t\t*ip = (str - buf);\n\t\t\t\t}\n\t\t\t\tcontinue;\n\n\t\t\tcase '%':\n\t\t\t\tif (str <= end)\n\t\t\t\t\t*str = '%';\n\t\t\t\t++str;\n\t\t\t\tcontinue;\n\n\t\t\t\t/* integer number formats - set up the flags and \"break\" */\n\t\t\tcase 'o':\n\t\t\t\tbase = 8;\n\t\t\t\tbreak;\n\n\t\t\tcase 'X':\n\t\t\t\tflags |= _kc_LARGE;\n\t\t\tcase 'x':\n\t\t\t\tbase = 16;\n\t\t\t\tbreak;\n\n\t\t\tcase 'd':\n\t\t\tcase 'i':\n\t\t\t\tflags |= _kc_SIGN;\n\t\t\tcase 'u':\n\t\t\t\tbreak;\n\n\t\t\tdefault:\n\t\t\t\tif (str <= end)\n\t\t\t\t\t*str = '%';\n\t\t\t\t++str;\n\t\t\t\tif (*fmt) {\n\t\t\t\t\tif (str <= end)\n\t\t\t\t\t\t*str = *fmt;\n\t\t\t\t\t++str;\n\t\t\t\t} else {\n\t\t\t\t\t--fmt;\n\t\t\t\t}\n\t\t\t\tcontinue;\n\t\t}\n\t\tif (qualifier == 'L')\n\t\t\tnum = va_arg(args, long long);\n\t\telse if (qualifier == 'l') {\n\t\t\tnum = va_arg(args, unsigned long);\n\t\t\tif (flags & _kc_SIGN)\n\t\t\t\tnum = (signed long) num;\n\t\t} else if (qualifier == 'Z') {\n\t\t\tnum = va_arg(args, size_t);\n\t\t} else if (qualifier == 'h') {\n\t\t\tnum = (unsigned short) va_arg(args, int);\n\t\t\tif (flags & _kc_SIGN)\n\t\t\t\tnum = (signed short) num;\n\t\t} else {\n\t\t\tnum = va_arg(args, unsigned int);\n\t\t\tif (flags & _kc_SIGN)\n\t\t\t\tnum = (signed int) num;\n\t\t}\n\t\tstr = number(str, end, num, base,\n\t\t\t\tfield_width, precision, flags);\n\t}\n\tif (str <= end)\n\t\t*str = '\\0';\n\telse if (size > 0)\n\t\t/* don't write out a null byte if the buf size is zero */\n\t\t*end = '\\0';\n\t/* the trailing null byte doesn't count towards the total\n\t* ++str;\n\t*/\n\treturn str-buf;\n}\n\nint _kc_snprintf(char * buf, size_t size, const char *fmt, ...)\n{\n\tva_list args;\n\tint i;\n\n\tva_start(args, fmt);\n\ti = _kc_vsnprintf(buf,size,fmt,args);\n\tva_end(args);\n\treturn i;\n}\n#endif /* < 2.4.8 */\n\n\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) )\n#ifdef CONFIG_PCI_IOV\nint __kc_pci_vfs_assigned(struct pci_dev *dev)\n{\n unsigned int vfs_assigned = 0;\n#ifdef HAVE_PCI_DEV_FLAGS_ASSIGNED\n int pos;\n struct pci_dev *vfdev;\n unsigned short dev_id;\n\n /* only search if we are a PF */\n if (!dev->is_physfn)\n return 0;\n\n /* find SR-IOV capability */\n pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);\n if (!pos)\n return 0;\n\n /*\n * * determine the device ID for the VFs, the vendor ID will be the\n * * same as the PF so there is no need to check for that one\n * */\n pci_read_config_word(dev, pos + PCI_SRIOV_VF_DID, &dev_id);\n\n /* loop through all the VFs to see if we own any that are assigned */\n vfdev = pci_get_device(dev->vendor, dev_id, NULL);\n while (vfdev) {\n /*\n * * It is considered assigned if it is a virtual function with\n * * our dev as the physical function and the assigned bit is set\n * */\n if (vfdev->is_virtfn && (vfdev->physfn == dev) &&\n (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED))\n vfs_assigned++;\n\n vfdev = pci_get_device(dev->vendor, dev_id, vfdev);\n }\n\n#endif /* HAVE_PCI_DEV_FLAGS_ASSIGNED */\n return vfs_assigned;\n}\n\n#endif /* CONFIG_PCI_IOV */\n#endif /* 3.10.0 */\n\n\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) )\n\n/**************************************/\n/* PCI DMA MAPPING */\n\n#if defined(CONFIG_HIGHMEM)\n\n#ifndef PCI_DRAM_OFFSET\n#define PCI_DRAM_OFFSET 0\n#endif\n\nu64\n_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset,\n size_t size, int direction)\n{\n\treturn (((u64) (page - mem_map) << PAGE_SHIFT) + offset +\n\t\tPCI_DRAM_OFFSET);\n}\n\n#else /* CONFIG_HIGHMEM */\n\nu64\n_kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset,\n size_t size, int direction)\n{\n\treturn pci_map_single(dev, (void *)page_address(page) + offset, size,\n\t\t\t direction);\n}\n\n#endif /* CONFIG_HIGHMEM */\n\nvoid\n_kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size,\n int direction)\n{\n\treturn pci_unmap_single(dev, dma_addr, size, direction);\n}\n\n#endif /* 2.4.13 => 2.4.3 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) )\n\n/**************************************/\n/* PCI DRIVER API */\n\nint\n_kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask)\n{\n\tif (!pci_dma_supported(dev, mask))\n\t\treturn -EIO;\n\tdev->dma_mask = mask;\n\treturn 0;\n}\n\nint\n_kc_pci_request_regions(struct pci_dev *dev, char *res_name)\n{\n\tint i;\n\n\tfor (i = 0; i < 6; i++) {\n\t\tif (pci_resource_len(dev, i) == 0)\n\t\t\tcontinue;\n\n\t\tif (pci_resource_flags(dev, i) & IORESOURCE_IO) {\n\t\t\tif (!request_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) {\n\t\t\t\tpci_release_regions(dev);\n\t\t\t\treturn -EBUSY;\n\t\t\t}\n\t\t} else if (pci_resource_flags(dev, i) & IORESOURCE_MEM) {\n\t\t\tif (!request_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i), res_name)) {\n\t\t\t\tpci_release_regions(dev);\n\t\t\t\treturn -EBUSY;\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\nvoid\n_kc_pci_release_regions(struct pci_dev *dev)\n{\n\tint i;\n\n\tfor (i = 0; i < 6; i++) {\n\t\tif (pci_resource_len(dev, i) == 0)\n\t\t\tcontinue;\n\n\t\tif (pci_resource_flags(dev, i) & IORESOURCE_IO)\n\t\t\trelease_region(pci_resource_start(dev, i), pci_resource_len(dev, i));\n\n\t\telse if (pci_resource_flags(dev, i) & IORESOURCE_MEM)\n\t\t\trelease_mem_region(pci_resource_start(dev, i), pci_resource_len(dev, i));\n\t}\n}\n\n/**************************************/\n/* NETWORK DRIVER API */\n\nstruct net_device *\n_kc_alloc_etherdev(int sizeof_priv)\n{\n\tstruct net_device *dev;\n\tint alloc_size;\n\n\talloc_size = sizeof(*dev) + sizeof_priv + IFNAMSIZ + 31;\n\tdev = kzalloc(alloc_size, GFP_KERNEL);\n\tif (!dev)\n\t\treturn NULL;\n\n\tif (sizeof_priv)\n\t\tdev->priv = (void *) (((unsigned long)(dev + 1) + 31) & ~31);\n\tdev->name[0] = '\\0';\n\tether_setup(dev);\n\n\treturn dev;\n}\n\nint\n_kc_is_valid_ether_addr(u8 *addr)\n{\n\tconst char zaddr[6] = { 0, };\n\n\treturn !(addr[0] & 1) && memcmp(addr, zaddr, 6);\n}\n\n#endif /* 2.4.3 => 2.4.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) )\n\nint\n_kc_pci_set_power_state(struct pci_dev *dev, int state)\n{\n\treturn 0;\n}\n\nint\n_kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable)\n{\n\treturn 0;\n}\n\n#endif /* 2.4.6 => 2.4.3 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )\nvoid _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page,\n int off, int size)\n{\n\tskb_frag_t *frag = &skb_shinfo(skb)->frags[i];\n\tfrag->page = page;\n\tfrag->page_offset = off;\n\tfrag->size = size;\n\tskb_shinfo(skb)->nr_frags = i + 1;\n}\n\n/*\n * Original Copyright:\n * find_next_bit.c: fallback find next bit implementation\n *\n * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.\n * Written by David Howells (dhowells@redhat.com)\n */\n\n/**\n * find_next_bit - find the next set bit in a memory region\n * @addr: The address to base the search on\n * @offset: The bitnumber to start searching at\n * @size: The maximum size to search\n */\nunsigned long find_next_bit(const unsigned long *addr, unsigned long size,\n unsigned long offset)\n{\n\tconst unsigned long *p = addr + BITOP_WORD(offset);\n\tunsigned long result = offset & ~(BITS_PER_LONG-1);\n\tunsigned long tmp;\n\n\tif (offset >= size)\n\t\treturn size;\n\tsize -= result;\n\toffset %= BITS_PER_LONG;\n\tif (offset) {\n\t\ttmp = *(p++);\n\t\ttmp &= (~0UL << offset);\n\t\tif (size < BITS_PER_LONG)\n\t\t\tgoto found_first;\n\t\tif (tmp)\n\t\t\tgoto found_middle;\n\t\tsize -= BITS_PER_LONG;\n\t\tresult += BITS_PER_LONG;\n\t}\n\twhile (size & ~(BITS_PER_LONG-1)) {\n\t\tif ((tmp = *(p++)))\n\t\t\tgoto found_middle;\n\t\tresult += BITS_PER_LONG;\n\t\tsize -= BITS_PER_LONG;\n\t}\n\tif (!size)\n\t\treturn result;\n\ttmp = *p;\n\nfound_first:\n\ttmp &= (~0UL >> (BITS_PER_LONG - size));\n\tif (tmp == 0UL)\t\t/* Are any bits set? */\n\t\treturn result + size;\t/* Nope. */\nfound_middle:\n\treturn result + ffs(tmp);\n}\n\nsize_t _kc_strlcpy(char *dest, const char *src, size_t size)\n{\n\tsize_t ret = strlen(src);\n\n\tif (size) {\n\t\tsize_t len = (ret >= size) ? size - 1 : ret;\n\t\tmemcpy(dest, src, len);\n\t\tdest[len] = '\\0';\n\t}\n\treturn ret;\n}\n\n#endif /* 2.6.0 => 2.4.6 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) )\nint _kc_scnprintf(char * buf, size_t size, const char *fmt, ...)\n{\n\tva_list args;\n\tint i;\n\n\tva_start(args, fmt);\n\ti = vsnprintf(buf, size, fmt, args);\n\tva_end(args);\n\treturn (i >= size) ? (size - 1) : i;\n}\n#endif /* < 2.6.4 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) )\nDECLARE_BITMAP(_kcompat_node_online_map, MAX_NUMNODES) = {1};\n#endif /* < 2.6.10 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) )\nchar *_kc_kstrdup(const char *s, unsigned int gfp)\n{\n\tsize_t len;\n\tchar *buf;\n\n\tif (!s)\n\t\treturn NULL;\n\n\tlen = strlen(s) + 1;\n\tbuf = kmalloc(len, gfp);\n\tif (buf)\n\t\tmemcpy(buf, s, len);\n\treturn buf;\n}\n#endif /* < 2.6.13 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) )\nvoid *_kc_kzalloc(size_t size, int flags)\n{\n\tvoid *ret = kmalloc(size, flags);\n\tif (ret)\n\t\tmemset(ret, 0, size);\n\treturn ret;\n}\n#endif /* <= 2.6.13 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) )\nint _kc_skb_pad(struct sk_buff *skb, int pad)\n{\n\tint ntail;\n\n /* If the skbuff is non linear tailroom is always zero.. */\n if(!skb_cloned(skb) && skb_tailroom(skb) >= pad) {\n\t\tmemset(skb->data+skb->len, 0, pad);\n\t\treturn 0;\n }\n\n\tntail = skb->data_len + pad - (skb->end - skb->tail);\n\tif (likely(skb_cloned(skb) || ntail > 0)) {\n\t\tif (pskb_expand_head(skb, 0, ntail, GFP_ATOMIC));\n\t\t\tgoto free_skb;\n\t}\n\n#ifdef MAX_SKB_FRAGS\n\tif (skb_is_nonlinear(skb) &&\n\t !__pskb_pull_tail(skb, skb->data_len))\n\t\tgoto free_skb;\n\n#endif\n\tmemset(skb->data + skb->len, 0, pad);\n return 0;\n\nfree_skb:\n\tkfree_skb(skb);\n\treturn -ENOMEM;\n}\n\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,4)))\nint _kc_pci_save_state(struct pci_dev *pdev)\n{\n\tstruct adapter_struct *adapter = pci_get_drvdata(pdev);\n\tint size = PCI_CONFIG_SPACE_LEN, i;\n\tu16 pcie_cap_offset, pcie_link_status;\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) )\n\t/* no ->dev for 2.4 kernels */\n\tWARN_ON(pdev->dev.driver_data == NULL);\n#endif\n\tpcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP);\n\tif (pcie_cap_offset) {\n\t\tif (!pci_read_config_word(pdev,\n\t\t pcie_cap_offset + PCIE_LINK_STATUS,\n\t\t &pcie_link_status))\n\t\tsize = PCIE_CONFIG_SPACE_LEN;\n\t}\n\tpci_config_space_ich8lan();\n#ifdef HAVE_PCI_ERS\n\tif (adapter->config_space == NULL)\n#else\n\tWARN_ON(adapter->config_space != NULL);\n#endif\n\t\tadapter->config_space = kmalloc(size, GFP_KERNEL);\n\tif (!adapter->config_space) {\n\t\tprintk(KERN_ERR \"Out of memory in pci_save_state\\n\");\n\t\treturn -ENOMEM;\n\t}\n\tfor (i = 0; i < (size / 4); i++)\n\t\tpci_read_config_dword(pdev, i * 4, &adapter->config_space[i]);\n\treturn 0;\n}\n\nvoid _kc_pci_restore_state(struct pci_dev *pdev)\n{\n\tstruct adapter_struct *adapter = pci_get_drvdata(pdev);\n\tint size = PCI_CONFIG_SPACE_LEN, i;\n\tu16 pcie_cap_offset;\n\tu16 pcie_link_status;\n\n\tif (adapter->config_space != NULL) {\n\t\tpcie_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_EXP);\n\t\tif (pcie_cap_offset &&\n\t\t !pci_read_config_word(pdev,\n\t\t pcie_cap_offset + PCIE_LINK_STATUS,\n\t\t &pcie_link_status))\n\t\t\tsize = PCIE_CONFIG_SPACE_LEN;\n\n\t\tpci_config_space_ich8lan();\n\t\tfor (i = 0; i < (size / 4); i++)\n\t\tpci_write_config_dword(pdev, i * 4, adapter->config_space[i]);\n#ifndef HAVE_PCI_ERS\n\t\tkfree(adapter->config_space);\n\t\tadapter->config_space = NULL;\n#endif\n\t}\n}\n#endif /* !(RHEL_RELEASE_CODE >= RHEL 5.4) */\n\n#ifdef HAVE_PCI_ERS\nvoid _kc_free_netdev(struct net_device *netdev)\n{\n\tstruct adapter_struct *adapter = netdev_priv(netdev);\n\n\tif (adapter->config_space != NULL)\n\t\tkfree(adapter->config_space);\n#ifdef CONFIG_SYSFS\n\tif (netdev->reg_state == NETREG_UNINITIALIZED) {\n\t\tkfree((char *)netdev - netdev->padded);\n\t} else {\n\t\tBUG_ON(netdev->reg_state != NETREG_UNREGISTERED);\n\t\tnetdev->reg_state = NETREG_RELEASED;\n\t\tclass_device_put(&netdev->class_dev);\n\t}\n#else\n\tkfree((char *)netdev - netdev->padded);\n#endif\n}\n#endif\n\nvoid *_kc_kmemdup(const void *src, size_t len, unsigned gfp)\n{\n\tvoid *p;\n\n\tp = kzalloc(len, gfp);\n\tif (p)\n\t\tmemcpy(p, src, len);\n\treturn p;\n}\n#endif /* <= 2.6.19 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) )\n/* hexdump code taken from lib/hexdump.c */\nstatic void _kc_hex_dump_to_buffer(const void *buf, size_t len, int rowsize,\n\t\t\tint groupsize, unsigned char *linebuf,\n\t\t\tsize_t linebuflen, bool ascii)\n{\n\tconst u8 *ptr = buf;\n\tu8 ch;\n\tint j, lx = 0;\n\tint ascii_column;\n\n\tif (rowsize != 16 && rowsize != 32)\n\t\trowsize = 16;\n\n\tif (!len)\n\t\tgoto nil;\n\tif (len > rowsize)\t\t/* limit to one line at a time */\n\t\tlen = rowsize;\n\tif ((len % groupsize) != 0)\t/* no mixed size output */\n\t\tgroupsize = 1;\n\n\tswitch (groupsize) {\n\tcase 8: {\n\t\tconst u64 *ptr8 = buf;\n\t\tint ngroups = len / groupsize;\n\n\t\tfor (j = 0; j < ngroups; j++)\n\t\t\tlx += scnprintf((char *)(linebuf + lx), linebuflen - lx,\n\t\t\t\t\"%s%16.16llx\", j ? \" \" : \"\",\n\t\t\t\t(unsigned long long)*(ptr8 + j));\n\t\tascii_column = 17 * ngroups + 2;\n\t\tbreak;\n\t}\n\n\tcase 4: {\n\t\tconst u32 *ptr4 = buf;\n\t\tint ngroups = len / groupsize;\n\n\t\tfor (j = 0; j < ngroups; j++)\n\t\t\tlx += scnprintf((char *)(linebuf + lx), linebuflen - lx,\n\t\t\t\t\"%s%8.8x\", j ? \" \" : \"\", *(ptr4 + j));\n\t\tascii_column = 9 * ngroups + 2;\n\t\tbreak;\n\t}\n\n\tcase 2: {\n\t\tconst u16 *ptr2 = buf;\n\t\tint ngroups = len / groupsize;\n\n\t\tfor (j = 0; j < ngroups; j++)\n\t\t\tlx += scnprintf((char *)(linebuf + lx), linebuflen - lx,\n\t\t\t\t\"%s%4.4x\", j ? \" \" : \"\", *(ptr2 + j));\n\t\tascii_column = 5 * ngroups + 2;\n\t\tbreak;\n\t}\n\n\tdefault:\n\t\tfor (j = 0; (j < len) && (lx + 3) <= linebuflen; j++) {\n\t\t\tch = ptr[j];\n\t\t\tlinebuf[lx++] = hex_asc(ch >> 4);\n\t\t\tlinebuf[lx++] = hex_asc(ch & 0x0f);\n\t\t\tlinebuf[lx++] = ' ';\n\t\t}\n\t\tif (j)\n\t\t\tlx--;\n\n\t\tascii_column = 3 * rowsize + 2;\n\t\tbreak;\n\t}\n\tif (!ascii)\n\t\tgoto nil;\n\n\twhile (lx < (linebuflen - 1) && lx < (ascii_column - 1))\n\t\tlinebuf[lx++] = ' ';\n\tfor (j = 0; (j < len) && (lx + 2) < linebuflen; j++)\n\t\tlinebuf[lx++] = (isascii(ptr[j]) && isprint(ptr[j])) ? ptr[j]\n\t\t\t\t: '.';\nnil:\n\tlinebuf[lx++] = '\\0';\n}\n\nvoid _kc_print_hex_dump(const char *level,\n\t\t\tconst char *prefix_str, int prefix_type,\n\t\t\tint rowsize, int groupsize,\n\t\t\tconst void *buf, size_t len, bool ascii)\n{\n\tconst u8 *ptr = buf;\n\tint i, linelen, remaining = len;\n\tunsigned char linebuf[200];\n\n\tif (rowsize != 16 && rowsize != 32)\n\t\trowsize = 16;\n\n\tfor (i = 0; i < len; i += rowsize) {\n\t\tlinelen = min(remaining, rowsize);\n\t\tremaining -= rowsize;\n\t\t_kc_hex_dump_to_buffer(ptr + i, linelen, rowsize, groupsize,\n\t\t\t\tlinebuf, sizeof(linebuf), ascii);\n\n\t\tswitch (prefix_type) {\n\t\tcase DUMP_PREFIX_ADDRESS:\n\t\t\tprintk(\"%s%s%*p: %s\\n\", level, prefix_str,\n\t\t\t\t(int)(2 * sizeof(void *)), ptr + i, linebuf);\n\t\t\tbreak;\n\t\tcase DUMP_PREFIX_OFFSET:\n\t\t\tprintk(\"%s%s%.8x: %s\\n\", level, prefix_str, i, linebuf);\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tprintk(\"%s%s%s\\n\", level, prefix_str, linebuf);\n\t\t\tbreak;\n\t\t}\n\t}\n}\n#endif /* < 2.6.22 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) )\nint ixgbe_dcb_netlink_register(void)\n{\n\treturn 0;\n}\n\nint ixgbe_dcb_netlink_unregister(void)\n{\n\treturn 0;\n}\n\nint ixgbe_copy_dcb_cfg(struct ixgbe_adapter *adapter, int tc_max)\n{\n\treturn 0;\n}\n#endif /* < 2.6.23 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) )\n#ifdef NAPI\nstruct net_device *napi_to_poll_dev(struct napi_struct *napi)\n{\n\tstruct adapter_q_vector *q_vector = container_of(napi,\n\t struct adapter_q_vector,\n\t napi);\n\treturn &q_vector->poll_dev;\n}\n\nint __kc_adapter_clean(struct net_device *netdev, int *budget)\n{\n\tint work_done;\n\tint work_to_do = min(*budget, netdev->quota);\n\t/* kcompat.h netif_napi_add puts napi struct in \"fake netdev->priv\" */\n\tstruct napi_struct *napi = netdev->priv;\n\twork_done = napi->poll(napi, work_to_do);\n\t*budget -= work_done;\n\tnetdev->quota -= work_done;\n\treturn (work_done >= work_to_do) ? 1 : 0;\n}\n#endif /* NAPI */\n#endif /* <= 2.6.24 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) )\nvoid _kc_pci_disable_link_state(struct pci_dev *pdev, int state)\n{\n\tstruct pci_dev *parent = pdev->bus->self;\n\tu16 link_state;\n\tint pos;\n\n\tif (!parent)\n\t\treturn;\n\n\tpos = pci_find_capability(parent, PCI_CAP_ID_EXP);\n\tif (pos) {\n\t\tpci_read_config_word(parent, pos + PCI_EXP_LNKCTL, &link_state);\n\t\tlink_state &= ~state;\n\t\tpci_write_config_word(parent, pos + PCI_EXP_LNKCTL, link_state);\n\t}\n}\n#endif /* < 2.6.26 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) )\n#ifdef HAVE_TX_MQ\nvoid _kc_netif_tx_stop_all_queues(struct net_device *netdev)\n{\n\tstruct adapter_struct *adapter = netdev_priv(netdev);\n\tint i;\n\n\tnetif_stop_queue(netdev);\n\tif (netif_is_multiqueue(netdev))\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\t\tnetif_stop_subqueue(netdev, i);\n}\nvoid _kc_netif_tx_wake_all_queues(struct net_device *netdev)\n{\n\tstruct adapter_struct *adapter = netdev_priv(netdev);\n\tint i;\n\n\tnetif_wake_queue(netdev);\n\tif (netif_is_multiqueue(netdev))\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\t\tnetif_wake_subqueue(netdev, i);\n}\nvoid _kc_netif_tx_start_all_queues(struct net_device *netdev)\n{\n\tstruct adapter_struct *adapter = netdev_priv(netdev);\n\tint i;\n\n\tnetif_start_queue(netdev);\n\tif (netif_is_multiqueue(netdev))\n\t\tfor (i = 0; i < adapter->num_tx_queues; i++)\n\t\t\tnetif_start_subqueue(netdev, i);\n}\n#endif /* HAVE_TX_MQ */\n\n#ifndef __WARN_printf\nvoid __kc_warn_slowpath(const char *file, int line, const char *fmt, ...)\n{\n\tva_list args;\n\n\tprintk(KERN_WARNING \"------------[ cut here ]------------\\n\");\n\tprintk(KERN_WARNING \"WARNING: at %s:%d %s()\\n\", file, line);\n\tva_start(args, fmt);\n\tvprintk(fmt, args);\n\tva_end(args);\n\n\tdump_stack();\n}\n#endif /* __WARN_printf */\n#endif /* < 2.6.27 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) )\n\nint\n_kc_pci_prepare_to_sleep(struct pci_dev *dev)\n{\n\tpci_power_t target_state;\n\tint error;\n\n\ttarget_state = pci_choose_state(dev, PMSG_SUSPEND);\n\n\tpci_enable_wake(dev, target_state, true);\n\n\terror = pci_set_power_state(dev, target_state);\n\n\tif (error)\n\t\tpci_enable_wake(dev, target_state, false);\n\n\treturn error;\n}\n\nint\n_kc_pci_wake_from_d3(struct pci_dev *dev, bool enable)\n{\n\tint err;\n\n\terr = pci_enable_wake(dev, PCI_D3cold, enable);\n\tif (err)\n\t\tgoto out;\n\n\terr = pci_enable_wake(dev, PCI_D3hot, enable);\n\nout:\n\treturn err;\n}\n#endif /* < 2.6.28 */\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0) )\nvoid _kc_skb_add_rx_frag(struct sk_buff *skb, int i, struct page *page,\n\t\t\t int off, int size)\n{\n\tskb_fill_page_desc(skb, i, page, off, size);\n\tskb->len += size;\n\tskb->data_len += size;\n\tskb->truesize += size;\n}\n#endif /* < 3.4.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) )\n#ifdef HAVE_NETDEV_SELECT_QUEUE\n#include \nstatic u32 _kc_simple_tx_hashrnd;\nstatic u32 _kc_simple_tx_hashrnd_initialized;\n\nu16 _kc_skb_tx_hash(struct net_device *dev, struct sk_buff *skb)\n{\n\tu32 addr1, addr2, ports;\n\tu32 hash, ihl;\n\tu8 ip_proto = 0;\n\n\tif (unlikely(!_kc_simple_tx_hashrnd_initialized)) {\n\t\tget_random_bytes(&_kc_simple_tx_hashrnd, 4);\n\t\t_kc_simple_tx_hashrnd_initialized = 1;\n\t}\n\n\tswitch (skb->protocol) {\n\tcase htons(ETH_P_IP):\n\t\tif (!(ip_hdr(skb)->frag_off & htons(IP_MF | IP_OFFSET)))\n\t\t\tip_proto = ip_hdr(skb)->protocol;\n\t\taddr1 = ip_hdr(skb)->saddr;\n\t\taddr2 = ip_hdr(skb)->daddr;\n\t\tihl = ip_hdr(skb)->ihl;\n\t\tbreak;\n#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)\n\tcase htons(ETH_P_IPV6):\n\t\tip_proto = ipv6_hdr(skb)->nexthdr;\n\t\taddr1 = ipv6_hdr(skb)->saddr.s6_addr32[3];\n\t\taddr2 = ipv6_hdr(skb)->daddr.s6_addr32[3];\n\t\tihl = (40 >> 2);\n\t\tbreak;\n#endif\n\tdefault:\n\t\treturn 0;\n\t}\n\n\n\tswitch (ip_proto) {\n\tcase IPPROTO_TCP:\n\tcase IPPROTO_UDP:\n\tcase IPPROTO_DCCP:\n\tcase IPPROTO_ESP:\n\tcase IPPROTO_AH:\n\tcase IPPROTO_SCTP:\n\tcase IPPROTO_UDPLITE:\n\t\tports = *((u32 *) (skb_network_header(skb) + (ihl * 4)));\n\t\tbreak;\n\n\tdefault:\n\t\tports = 0;\n\t\tbreak;\n\t}\n\n\thash = jhash_3words(addr1, addr2, ports, _kc_simple_tx_hashrnd);\n\n\treturn (u16) (((u64) hash * dev->real_num_tx_queues) >> 32);\n}\n#endif /* HAVE_NETDEV_SELECT_QUEUE */\n#endif /* < 2.6.30 */\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) )\n#ifdef HAVE_TX_MQ\n#ifndef CONFIG_NETDEVICES_MULTIQUEUE\nvoid _kc_netif_set_real_num_tx_queues(struct net_device *dev, unsigned int txq)\n{\n\tunsigned int real_num = dev->real_num_tx_queues;\n\tstruct Qdisc *qdisc;\n\tint i;\n\n\tif (unlikely(txq > dev->num_tx_queues))\n\t\t;\n\telse if (txq > real_num)\n\t\tdev->real_num_tx_queues = txq;\n\telse if ( txq < real_num) {\n\t\tdev->real_num_tx_queues = txq;\n\t\tfor (i = txq; i < dev->num_tx_queues; i++) {\n\t\t\tqdisc = netdev_get_tx_queue(dev, i)->qdisc;\n\t\t\tif (qdisc) {\n\t\t\t\tspin_lock_bh(qdisc_lock(qdisc));\n\t\t\t\tqdisc_reset(qdisc);\n\t\t\t\tspin_unlock_bh(qdisc_lock(qdisc));\n\t\t\t}\n\t\t}\n\t}\n}\n#endif /* CONFIG_NETDEVICES_MULTIQUEUE */\n#endif /* HAVE_TX_MQ */\n#endif /* < 2.6.35 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) )\nstatic const u32 _kc_flags_dup_features =\n\t(ETH_FLAG_LRO | ETH_FLAG_NTUPLE | ETH_FLAG_RXHASH);\n\nu32 _kc_ethtool_op_get_flags(struct net_device *dev)\n{\n\treturn dev->features & _kc_flags_dup_features;\n}\n\nint _kc_ethtool_op_set_flags(struct net_device *dev, u32 data, u32 supported)\n{\n\tif (data & ~supported)\n\t\treturn -EINVAL;\n\n\tdev->features = ((dev->features & ~_kc_flags_dup_features) |\n\t\t\t (data & _kc_flags_dup_features));\n\treturn 0;\n}\n#endif /* < 2.6.36 */\n\n/******************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39) )\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,0)))\nu8 _kc_netdev_get_num_tc(struct net_device *dev)\n{\n\tstruct adapter_struct *kc_adapter = netdev_priv(dev);\n\tif (kc_adapter->flags & IXGBE_FLAG_DCB_ENABLED)\n\t\treturn kc_adapter->tc;\n\telse\n\t\treturn 0;\n}\n\nu8 _kc_netdev_get_prio_tc_map(struct net_device *dev, u8 up)\n{\n\tstruct adapter_struct *kc_adapter = netdev_priv(dev);\n\tint tc;\n\tu8 map;\n\n\tfor (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) {\n\t\tmap = kc_adapter->dcb_cfg.tc_config[tc].path[0].up_to_tc_bitmap;\n\n\t\tif (map & (1 << up))\n\t\t\treturn tc;\n\t}\n\n\treturn 0;\n}\n#endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,0)) */\n#endif /* < 2.6.39 */\n" }, { "path": "lib/librte_eal/linuxapp/kni/ethtool/ixgbe/kcompat.h", "content": "/*******************************************************************************\n\n Intel 10 Gigabit PCI Express Linux driver\n Copyright(c) 1999 - 2012 Intel Corporation.\n\n This program is free software; you can redistribute it and/or modify it\n under the terms and conditions of the GNU General Public License,\n version 2, as published by the Free Software Foundation.\n\n This program is distributed in the hope it will be useful, but WITHOUT\n ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n more details.\n\n You should have received a copy of the GNU General Public License along with\n this program; if not, write to the Free Software Foundation, Inc.,\n 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n\n The full GNU General Public License is included in this distribution in\n the file called \"COPYING\".\n\n Contact Information:\n e1000-devel Mailing List \n Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497\n\n*******************************************************************************/\n\n#ifndef _KCOMPAT_H_\n#define _KCOMPAT_H_\n\n#ifndef LINUX_VERSION_CODE\n#include \n#else\n#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))\n#endif\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/* NAPI enable/disable flags here */\n/* enable NAPI for ixgbe by default */\n#undef CONFIG_IXGBE_NAPI\n#define CONFIG_IXGBE_NAPI\n#define NAPI\n#ifdef CONFIG_IXGBE_NAPI\n#undef NAPI\n#define NAPI\n#endif /* CONFIG_IXGBE_NAPI */\n#ifdef IXGBE_NAPI\n#undef NAPI\n#define NAPI\n#endif /* IXGBE_NAPI */\n#ifdef IXGBE_NO_NAPI\n#undef NAPI\n#endif /* IXGBE_NO_NAPI */\n\n#define adapter_struct ixgbe_adapter\n#define adapter_q_vector ixgbe_q_vector\n\n/* and finally set defines so that the code sees the changes */\n#ifdef NAPI\n#ifndef CONFIG_IXGBE_NAPI\n#define CONFIG_IXGBE_NAPI\n#endif\n#else\n#undef CONFIG_IXGBE_NAPI\n#endif /* NAPI */\n\n/* packet split disable/enable */\n#ifdef DISABLE_PACKET_SPLIT\n#ifndef CONFIG_IXGBE_DISABLE_PACKET_SPLIT\n#define CONFIG_IXGBE_DISABLE_PACKET_SPLIT\n#endif\n#endif /* DISABLE_PACKET_SPLIT */\n\n/* MSI compatibility code for all kernels and drivers */\n#ifdef DISABLE_PCI_MSI\n#undef CONFIG_PCI_MSI\n#endif\n#ifndef CONFIG_PCI_MSI\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) )\nstruct msix_entry {\n\tu16 vector; /* kernel uses to write allocated vector */\n\tu16 entry; /* driver uses to specify entry, OS writes */\n};\n#endif\n#undef pci_enable_msi\n#define pci_enable_msi(a) -ENOTSUPP\n#undef pci_disable_msi\n#define pci_disable_msi(a) do {} while (0)\n#undef pci_enable_msix\n#define pci_enable_msix(a, b, c) -ENOTSUPP\n#undef pci_disable_msix\n#define pci_disable_msix(a) do {} while (0)\n#define msi_remove_pci_irq_vectors(a) do {} while (0)\n#endif /* CONFIG_PCI_MSI */\n#ifdef DISABLE_PM\n#undef CONFIG_PM\n#endif\n\n#ifdef DISABLE_NET_POLL_CONTROLLER\n#undef CONFIG_NET_POLL_CONTROLLER\n#endif\n\n#ifndef PMSG_SUSPEND\n#define PMSG_SUSPEND 3\n#endif\n\n/* generic boolean compatibility */\n#undef TRUE\n#undef FALSE\n#define TRUE true\n#define FALSE false\n#ifdef GCC_VERSION\n#if ( GCC_VERSION < 3000 )\n#define _Bool char\n#endif\n#else\n#define _Bool char\n#endif\n\n/* kernels less than 2.4.14 don't have this */\n#ifndef ETH_P_8021Q\n#define ETH_P_8021Q 0x8100\n#endif\n\n#ifndef module_param\n#define module_param(v,t,p) MODULE_PARM(v, \"i\");\n#endif\n\n#ifndef DMA_64BIT_MASK\n#define DMA_64BIT_MASK 0xffffffffffffffffULL\n#endif\n\n#ifndef DMA_32BIT_MASK\n#define DMA_32BIT_MASK 0x00000000ffffffffULL\n#endif\n\n#ifndef PCI_CAP_ID_EXP\n#define PCI_CAP_ID_EXP 0x10\n#endif\n\n#ifndef PCIE_LINK_STATE_L0S\n#define PCIE_LINK_STATE_L0S 1\n#endif\n#ifndef PCIE_LINK_STATE_L1\n#define PCIE_LINK_STATE_L1 2\n#endif\n\n#ifndef mmiowb\n#ifdef CONFIG_IA64\n#define mmiowb() asm volatile (\"mf.a\" ::: \"memory\")\n#else\n#define mmiowb()\n#endif\n#endif\n\n#ifndef SET_NETDEV_DEV\n#define SET_NETDEV_DEV(net, pdev)\n#endif\n\n#if !defined(HAVE_FREE_NETDEV) && ( LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) )\n#define free_netdev(x)\tkfree(x)\n#endif\n\n#ifdef HAVE_POLL_CONTROLLER\n#define CONFIG_NET_POLL_CONTROLLER\n#endif\n\n#ifndef SKB_DATAREF_SHIFT\n/* if we do not have the infrastructure to detect if skb_header is cloned\n just return false in all cases */\n#define skb_header_cloned(x) 0\n#endif\n\n#ifndef NETIF_F_GSO\n#define gso_size tso_size\n#define gso_segs tso_segs\n#endif\n\n#ifndef NETIF_F_GRO\n#define vlan_gro_receive(_napi, _vlgrp, _vlan, _skb) \\\n\t\tvlan_hwaccel_receive_skb(_skb, _vlgrp, _vlan)\n#define napi_gro_receive(_napi, _skb) netif_receive_skb(_skb)\n#endif\n\n#ifndef NETIF_F_SCTP_CSUM\n#define NETIF_F_SCTP_CSUM 0\n#endif\n\n#ifndef NETIF_F_LRO\n#define NETIF_F_LRO (1 << 15)\n#endif\n\n#ifndef NETIF_F_NTUPLE\n#define NETIF_F_NTUPLE (1 << 27)\n#endif\n\n#ifndef IPPROTO_SCTP\n#define IPPROTO_SCTP 132\n#endif\n\n#ifndef CHECKSUM_PARTIAL\n#define CHECKSUM_PARTIAL CHECKSUM_HW\n#define CHECKSUM_COMPLETE CHECKSUM_HW\n#endif\n\n#ifndef __read_mostly\n#define __read_mostly\n#endif\n\n#ifndef MII_RESV1\n#define MII_RESV1\t\t0x17\t\t/* Reserved...\t\t*/\n#endif\n\n#ifndef unlikely\n#define unlikely(_x) _x\n#define likely(_x) _x\n#endif\n\n#ifndef WARN_ON\n#define WARN_ON(x)\n#endif\n\n#ifndef PCI_DEVICE\n#define PCI_DEVICE(vend,dev) \\\n\t.vendor = (vend), .device = (dev), \\\n\t.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID\n#endif\n\n#ifndef node_online\n#define node_online(node) ((node) == 0)\n#endif\n\n#ifndef num_online_cpus\n#define num_online_cpus() smp_num_cpus\n#endif\n\n#ifndef cpu_online\n#define cpu_online(cpuid) test_bit((cpuid), &cpu_online_map)\n#endif\n\n#ifndef _LINUX_RANDOM_H\n#include \n#endif\n\n#ifndef DECLARE_BITMAP\n#ifndef BITS_TO_LONGS\n#define BITS_TO_LONGS(bits) (((bits)+BITS_PER_LONG-1)/BITS_PER_LONG)\n#endif\n#define DECLARE_BITMAP(name,bits) long name[BITS_TO_LONGS(bits)]\n#endif\n\n#ifndef VLAN_HLEN\n#define VLAN_HLEN 4\n#endif\n\n#ifndef VLAN_ETH_HLEN\n#define VLAN_ETH_HLEN 18\n#endif\n\n#ifndef VLAN_ETH_FRAME_LEN\n#define VLAN_ETH_FRAME_LEN 1518\n#endif\n\n#if !defined(IXGBE_DCA) && !defined(IGB_DCA)\n#define dca_get_tag(b) 0\n#define dca_add_requester(a) -1\n#define dca_remove_requester(b) do { } while(0)\n#define DCA_PROVIDER_ADD 0x0001\n#define DCA_PROVIDER_REMOVE 0x0002\n#endif\n\n#ifndef DCA_GET_TAG_TWO_ARGS\n#define dca3_get_tag(a,b) dca_get_tag(b)\n#endif\n\n#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS\n#if defined(__i386__) || defined(__x86_64__)\n#define CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS\n#endif\n#endif\n\n/* taken from 2.6.24 definition in linux/kernel.h */\n#ifndef IS_ALIGNED\n#define IS_ALIGNED(x,a) (((x) % ((typeof(x))(a))) == 0)\n#endif\n\n#ifndef NETIF_F_HW_VLAN_TX\nstruct _kc_vlan_ethhdr {\n\tunsigned char\th_dest[ETH_ALEN];\n\tunsigned char\th_source[ETH_ALEN];\n\t__be16\t\th_vlan_proto;\n\t__be16\t\th_vlan_TCI;\n\t__be16\t\th_vlan_encapsulated_proto;\n};\n#define vlan_ethhdr _kc_vlan_ethhdr\nstruct _kc_vlan_hdr {\n\t__be16\t\th_vlan_TCI;\n\t__be16\t\th_vlan_encapsulated_proto;\n};\n#define vlan_hdr _kc_vlan_hdr\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) )\n#define vlan_tx_tag_present(_skb) 0\n#define vlan_tx_tag_get(_skb) 0\n#endif\n#endif\n\n#ifndef VLAN_PRIO_SHIFT\n#define VLAN_PRIO_SHIFT 13\n#endif\n\n\n#ifndef __GFP_COLD\n#define __GFP_COLD 0\n#endif\n\n/*****************************************************************************/\n/* Installations with ethtool version without eeprom, adapter id, or statistics\n * support */\n\n#ifndef ETH_GSTRING_LEN\n#define ETH_GSTRING_LEN 32\n#endif\n\n#ifndef ETHTOOL_GSTATS\n#define ETHTOOL_GSTATS 0x1d\n#undef ethtool_drvinfo\n#define ethtool_drvinfo k_ethtool_drvinfo\nstruct k_ethtool_drvinfo {\n\tu32 cmd;\n\tchar driver[32];\n\tchar version[32];\n\tchar fw_version[32];\n\tchar bus_info[32];\n\tchar reserved1[32];\n\tchar reserved2[16];\n\tu32 n_stats;\n\tu32 testinfo_len;\n\tu32 eedump_len;\n\tu32 regdump_len;\n};\n\nstruct ethtool_stats {\n\tu32 cmd;\n\tu32 n_stats;\n\tu64 data[0];\n};\n#endif /* ETHTOOL_GSTATS */\n\n#ifndef ETHTOOL_PHYS_ID\n#define ETHTOOL_PHYS_ID 0x1c\n#endif /* ETHTOOL_PHYS_ID */\n\n#ifndef ETHTOOL_GSTRINGS\n#define ETHTOOL_GSTRINGS 0x1b\nenum ethtool_stringset {\n\tETH_SS_TEST = 0,\n\tETH_SS_STATS,\n};\nstruct ethtool_gstrings {\n\tu32 cmd; /* ETHTOOL_GSTRINGS */\n\tu32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/\n\tu32 len; /* number of strings in the string set */\n\tu8 data[0];\n};\n#endif /* ETHTOOL_GSTRINGS */\n\n#ifndef ETHTOOL_TEST\n#define ETHTOOL_TEST 0x1a\nenum ethtool_test_flags {\n\tETH_TEST_FL_OFFLINE\t= (1 << 0),\n\tETH_TEST_FL_FAILED\t= (1 << 1),\n};\nstruct ethtool_test {\n\tu32 cmd;\n\tu32 flags;\n\tu32 reserved;\n\tu32 len;\n\tu64 data[0];\n};\n#endif /* ETHTOOL_TEST */\n\n#ifndef ETHTOOL_GEEPROM\n#define ETHTOOL_GEEPROM 0xb\n#undef ETHTOOL_GREGS\nstruct ethtool_eeprom {\n\tu32 cmd;\n\tu32 magic;\n\tu32 offset;\n\tu32 len;\n\tu8 data[0];\n};\n\nstruct ethtool_value {\n\tu32 cmd;\n\tu32 data;\n};\n#endif /* ETHTOOL_GEEPROM */\n\n#ifndef ETHTOOL_GLINK\n#define ETHTOOL_GLINK 0xa\n#endif /* ETHTOOL_GLINK */\n\n#ifndef ETHTOOL_GWOL\n#define ETHTOOL_GWOL 0x5\n#define ETHTOOL_SWOL 0x6\n#define SOPASS_MAX 6\nstruct ethtool_wolinfo {\n\tu32 cmd;\n\tu32 supported;\n\tu32 wolopts;\n\tu8 sopass[SOPASS_MAX]; /* SecureOn(tm) password */\n};\n#endif /* ETHTOOL_GWOL */\n\n#ifndef ETHTOOL_GREGS\n#define ETHTOOL_GREGS\t\t0x00000004 /* Get NIC registers */\n#define ethtool_regs _kc_ethtool_regs\n/* for passing big chunks of data */\nstruct _kc_ethtool_regs {\n\tu32 cmd;\n\tu32 version; /* driver-specific, indicates different chips/revs */\n\tu32 len; /* bytes */\n\tu8 data[0];\n};\n#endif /* ETHTOOL_GREGS */\n\n#ifndef ETHTOOL_GMSGLVL\n#define ETHTOOL_GMSGLVL\t\t0x00000007 /* Get driver message level */\n#endif\n#ifndef ETHTOOL_SMSGLVL\n#define ETHTOOL_SMSGLVL\t\t0x00000008 /* Set driver msg level, priv. */\n#endif\n#ifndef ETHTOOL_NWAY_RST\n#define ETHTOOL_NWAY_RST\t0x00000009 /* Restart autonegotiation, priv */\n#endif\n#ifndef ETHTOOL_GLINK\n#define ETHTOOL_GLINK\t\t0x0000000a /* Get link status */\n#endif\n#ifndef ETHTOOL_GEEPROM\n#define ETHTOOL_GEEPROM\t\t0x0000000b /* Get EEPROM data */\n#endif\n#ifndef ETHTOOL_SEEPROM\n#define ETHTOOL_SEEPROM\t\t0x0000000c /* Set EEPROM data */\n#endif\n#ifndef ETHTOOL_GCOALESCE\n#define ETHTOOL_GCOALESCE\t0x0000000e /* Get coalesce config */\n/* for configuring coalescing parameters of chip */\n#define ethtool_coalesce _kc_ethtool_coalesce\nstruct _kc_ethtool_coalesce {\n\tu32\tcmd;\t/* ETHTOOL_{G,S}COALESCE */\n\n\t/* How many usecs to delay an RX interrupt after\n\t * a packet arrives. If 0, only rx_max_coalesced_frames\n\t * is used.\n\t */\n\tu32\trx_coalesce_usecs;\n\n\t/* How many packets to delay an RX interrupt after\n\t * a packet arrives. If 0, only rx_coalesce_usecs is\n\t * used. It is illegal to set both usecs and max frames\n\t * to zero as this would cause RX interrupts to never be\n\t * generated.\n\t */\n\tu32\trx_max_coalesced_frames;\n\n\t/* Same as above two parameters, except that these values\n\t * apply while an IRQ is being serviced by the host. Not\n\t * all cards support this feature and the values are ignored\n\t * in that case.\n\t */\n\tu32\trx_coalesce_usecs_irq;\n\tu32\trx_max_coalesced_frames_irq;\n\n\t/* How many usecs to delay a TX interrupt after\n\t * a packet is sent. If 0, only tx_max_coalesced_frames\n\t * is used.\n\t */\n\tu32\ttx_coalesce_usecs;\n\n\t/* How many packets to delay a TX interrupt after\n\t * a packet is sent. If 0, only tx_coalesce_usecs is\n\t * used. It is illegal to set both usecs and max frames\n\t * to zero as this would cause TX interrupts to never be\n\t * generated.\n\t */\n\tu32\ttx_max_coalesced_frames;\n\n\t/* Same as above two parameters, except that these values\n\t * apply while an IRQ is being serviced by the host. Not\n\t * all cards support this feature and the values are ignored\n\t * in that case.\n\t */\n\tu32\ttx_coalesce_usecs_irq;\n\tu32\ttx_max_coalesced_frames_irq;\n\n\t/* How many usecs to delay in-memory statistics\n\t * block updates. Some drivers do not have an in-memory\n\t * statistic block, and in such cases this value is ignored.\n\t * This value must not be zero.\n\t */\n\tu32\tstats_block_coalesce_usecs;\n\n\t/* Adaptive RX/TX coalescing is an algorithm implemented by\n\t * some drivers to improve latency under low packet rates and\n\t * improve throughput under high packet rates. Some drivers\n\t * only implement one of RX or TX adaptive coalescing. Anything\n\t * not implemented by the driver causes these values to be\n\t * silently ignored.\n\t */\n\tu32\tuse_adaptive_rx_coalesce;\n\tu32\tuse_adaptive_tx_coalesce;\n\n\t/* When the packet rate (measured in packets per second)\n\t * is below pkt_rate_low, the {rx,tx}_*_low parameters are\n\t * used.\n\t */\n\tu32\tpkt_rate_low;\n\tu32\trx_coalesce_usecs_low;\n\tu32\trx_max_coalesced_frames_low;\n\tu32\ttx_coalesce_usecs_low;\n\tu32\ttx_max_coalesced_frames_low;\n\n\t/* When the packet rate is below pkt_rate_high but above\n\t * pkt_rate_low (both measured in packets per second) the\n\t * normal {rx,tx}_* coalescing parameters are used.\n\t */\n\n\t/* When the packet rate is (measured in packets per second)\n\t * is above pkt_rate_high, the {rx,tx}_*_high parameters are\n\t * used.\n\t */\n\tu32\tpkt_rate_high;\n\tu32\trx_coalesce_usecs_high;\n\tu32\trx_max_coalesced_frames_high;\n\tu32\ttx_coalesce_usecs_high;\n\tu32\ttx_max_coalesced_frames_high;\n\n\t/* How often to do adaptive coalescing packet rate sampling,\n\t * measured in seconds. Must not be zero.\n\t */\n\tu32\trate_sample_interval;\n};\n#endif /* ETHTOOL_GCOALESCE */\n\n#ifndef ETHTOOL_SCOALESCE\n#define ETHTOOL_SCOALESCE\t0x0000000f /* Set coalesce config. */\n#endif\n#ifndef ETHTOOL_GRINGPARAM\n#define ETHTOOL_GRINGPARAM\t0x00000010 /* Get ring parameters */\n/* for configuring RX/TX ring parameters */\n#define ethtool_ringparam _kc_ethtool_ringparam\nstruct _kc_ethtool_ringparam {\n\tu32\tcmd;\t/* ETHTOOL_{G,S}RINGPARAM */\n\n\t/* Read only attributes. These indicate the maximum number\n\t * of pending RX/TX ring entries the driver will allow the\n\t * user to set.\n\t */\n\tu32\trx_max_pending;\n\tu32\trx_mini_max_pending;\n\tu32\trx_jumbo_max_pending;\n\tu32\ttx_max_pending;\n\n\t/* Values changeable by the user. The valid values are\n\t * in the range 1 to the \"*_max_pending\" counterpart above.\n\t */\n\tu32\trx_pending;\n\tu32\trx_mini_pending;\n\tu32\trx_jumbo_pending;\n\tu32\ttx_pending;\n};\n#endif /* ETHTOOL_GRINGPARAM */\n\n#ifndef ETHTOOL_SRINGPARAM\n#define ETHTOOL_SRINGPARAM\t0x00000011 /* Set ring parameters, priv. */\n#endif\n#ifndef ETHTOOL_GPAUSEPARAM\n#define ETHTOOL_GPAUSEPARAM\t0x00000012 /* Get pause parameters */\n/* for configuring link flow control parameters */\n#define ethtool_pauseparam _kc_ethtool_pauseparam\nstruct _kc_ethtool_pauseparam {\n\tu32\tcmd;\t/* ETHTOOL_{G,S}PAUSEPARAM */\n\n\t/* If the link is being auto-negotiated (via ethtool_cmd.autoneg\n\t * being true) the user may set 'autoneg' here non-zero to have the\n\t * pause parameters be auto-negotiated too. In such a case, the\n\t * {rx,tx}_pause values below determine what capabilities are\n\t * advertised.\n\t *\n\t * If 'autoneg' is zero or the link is not being auto-negotiated,\n\t * then {rx,tx}_pause force the driver to use/not-use pause\n\t * flow control.\n\t */\n\tu32\tautoneg;\n\tu32\trx_pause;\n\tu32\ttx_pause;\n};\n#endif /* ETHTOOL_GPAUSEPARAM */\n\n#ifndef ETHTOOL_SPAUSEPARAM\n#define ETHTOOL_SPAUSEPARAM\t0x00000013 /* Set pause parameters. */\n#endif\n#ifndef ETHTOOL_GRXCSUM\n#define ETHTOOL_GRXCSUM\t\t0x00000014 /* Get RX hw csum enable (ethtool_value) */\n#endif\n#ifndef ETHTOOL_SRXCSUM\n#define ETHTOOL_SRXCSUM\t\t0x00000015 /* Set RX hw csum enable (ethtool_value) */\n#endif\n#ifndef ETHTOOL_GTXCSUM\n#define ETHTOOL_GTXCSUM\t\t0x00000016 /* Get TX hw csum enable (ethtool_value) */\n#endif\n#ifndef ETHTOOL_STXCSUM\n#define ETHTOOL_STXCSUM\t\t0x00000017 /* Set TX hw csum enable (ethtool_value) */\n#endif\n#ifndef ETHTOOL_GSG\n#define ETHTOOL_GSG\t\t0x00000018 /* Get scatter-gather enable\n\t\t\t\t\t * (ethtool_value) */\n#endif\n#ifndef ETHTOOL_SSG\n#define ETHTOOL_SSG\t\t0x00000019 /* Set scatter-gather enable\n\t\t\t\t\t * (ethtool_value). */\n#endif\n#ifndef ETHTOOL_TEST\n#define ETHTOOL_TEST\t\t0x0000001a /* execute NIC self-test, priv. */\n#endif\n#ifndef ETHTOOL_GSTRINGS\n#define ETHTOOL_GSTRINGS\t0x0000001b /* get specified string set */\n#endif\n#ifndef ETHTOOL_PHYS_ID\n#define ETHTOOL_PHYS_ID\t\t0x0000001c /* identify the NIC */\n#endif\n#ifndef ETHTOOL_GSTATS\n#define ETHTOOL_GSTATS\t\t0x0000001d /* get NIC-specific statistics */\n#endif\n#ifndef ETHTOOL_GTSO\n#define ETHTOOL_GTSO\t\t0x0000001e /* Get TSO enable (ethtool_value) */\n#endif\n#ifndef ETHTOOL_STSO\n#define ETHTOOL_STSO\t\t0x0000001f /* Set TSO enable (ethtool_value) */\n#endif\n\n#ifndef ETHTOOL_BUSINFO_LEN\n#define ETHTOOL_BUSINFO_LEN\t32\n#endif\n\n#ifndef RHEL_RELEASE_CODE\n/* NOTE: RHEL_RELEASE_* introduced in RHEL4.5 */\n#define RHEL_RELEASE_CODE 0\n#endif\n#ifndef RHEL_RELEASE_VERSION\n#define RHEL_RELEASE_VERSION(a,b) (((a) << 8) + (b))\n#endif\n#ifndef AX_RELEASE_CODE\n#define AX_RELEASE_CODE 0\n#endif\n#ifndef AX_RELEASE_VERSION\n#define AX_RELEASE_VERSION(a,b) (((a) << 8) + (b))\n#endif\n\n/* SuSE version macro is the same as Linux kernel version */\n#ifndef SLE_VERSION\n#define SLE_VERSION(a,b,c) KERNEL_VERSION(a,b,c)\n#endif\n#ifndef SLE_VERSION_CODE\n#ifdef CONFIG_SUSE_KERNEL\n/* SLES11 GA is 2.6.27 based */\n#if ( LINUX_VERSION_CODE == KERNEL_VERSION(2,6,27) )\n#define SLE_VERSION_CODE SLE_VERSION(11,0,0)\n#elif ( LINUX_VERSION_CODE == KERNEL_VERSION(2,6,32) )\n/* SLES11 SP1 is 2.6.32 based */\n#define SLE_VERSION_CODE SLE_VERSION(11,1,0)\n#else\n#define SLE_VERSION_CODE 0\n#endif\n#else /* CONFIG_SUSE_KERNEL */\n#define SLE_VERSION_CODE 0\n#endif /* CONFIG_SUSE_KERNEL */\n#endif /* SLE_VERSION_CODE */\n\n#ifdef __KLOCWORK__\n#ifdef ARRAY_SIZE\n#undef ARRAY_SIZE\n#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))\n#endif\n#endif /* __KLOCWORK__ */\n\n/*****************************************************************************/\n/* 2.4.3 => 2.4.0 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3) )\n\n/**************************************/\n/* PCI DRIVER API */\n\n#ifndef pci_set_dma_mask\n#define pci_set_dma_mask _kc_pci_set_dma_mask\nextern int _kc_pci_set_dma_mask(struct pci_dev *dev, dma_addr_t mask);\n#endif\n\n#ifndef pci_request_regions\n#define pci_request_regions _kc_pci_request_regions\nextern int _kc_pci_request_regions(struct pci_dev *pdev, char *res_name);\n#endif\n\n#ifndef pci_release_regions\n#define pci_release_regions _kc_pci_release_regions\nextern void _kc_pci_release_regions(struct pci_dev *pdev);\n#endif\n\n/**************************************/\n/* NETWORK DRIVER API */\n\n#ifndef alloc_etherdev\n#define alloc_etherdev _kc_alloc_etherdev\nextern struct net_device * _kc_alloc_etherdev(int sizeof_priv);\n#endif\n\n#ifndef is_valid_ether_addr\n#define is_valid_ether_addr _kc_is_valid_ether_addr\nextern int _kc_is_valid_ether_addr(u8 *addr);\n#endif\n\n/**************************************/\n/* MISCELLANEOUS */\n\n#ifndef INIT_TQUEUE\n#define INIT_TQUEUE(_tq, _routine, _data)\t\t\\\n\tdo {\t\t\t\t\t\t\\\n\t\tINIT_LIST_HEAD(&(_tq)->list);\t\t\\\n\t\t(_tq)->sync = 0;\t\t\t\\\n\t\t(_tq)->routine = _routine;\t\t\\\n\t\t(_tq)->data = _data;\t\t\t\\\n\t} while (0)\n#endif\n\n#endif /* 2.4.3 => 2.4.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,5) )\n/* Generic MII registers. */\n#define MII_BMCR 0x00 /* Basic mode control register */\n#define MII_BMSR 0x01 /* Basic mode status register */\n#define MII_PHYSID1 0x02 /* PHYS ID 1 */\n#define MII_PHYSID2 0x03 /* PHYS ID 2 */\n#define MII_ADVERTISE 0x04 /* Advertisement control reg */\n#define MII_LPA 0x05 /* Link partner ability reg */\n#define MII_EXPANSION 0x06 /* Expansion register */\n/* Basic mode control register. */\n#define BMCR_FULLDPLX 0x0100 /* Full duplex */\n#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */\n/* Basic mode status register. */\n#define BMSR_ERCAP 0x0001 /* Ext-reg capability */\n#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */\n#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */\n#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */\n#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */\n#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */\n/* Advertisement control register. */\n#define ADVERTISE_CSMA 0x0001 /* Only selector supported */\n#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */\n#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */\n#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */\n#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */\n#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \\\n ADVERTISE_100HALF | ADVERTISE_100FULL)\n/* Expansion register for auto-negotiation. */\n#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */\n#endif\n\n/*****************************************************************************/\n/* 2.4.6 => 2.4.3 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6) )\n\n#ifndef pci_set_power_state\n#define pci_set_power_state _kc_pci_set_power_state\nextern int _kc_pci_set_power_state(struct pci_dev *dev, int state);\n#endif\n\n#ifndef pci_enable_wake\n#define pci_enable_wake _kc_pci_enable_wake\nextern int _kc_pci_enable_wake(struct pci_dev *pdev, u32 state, int enable);\n#endif\n\n#ifndef pci_disable_device\n#define pci_disable_device _kc_pci_disable_device\nextern void _kc_pci_disable_device(struct pci_dev *pdev);\n#endif\n\n/* PCI PM entry point syntax changed, so don't support suspend/resume */\n#undef CONFIG_PM\n\n#endif /* 2.4.6 => 2.4.3 */\n\n#ifndef HAVE_PCI_SET_MWI\n#define pci_set_mwi(X) pci_write_config_word(X, \\\n\t\t\t PCI_COMMAND, adapter->hw.bus.pci_cmd_word | \\\n\t\t\t PCI_COMMAND_INVALIDATE);\n#define pci_clear_mwi(X) pci_write_config_word(X, \\\n\t\t\t PCI_COMMAND, adapter->hw.bus.pci_cmd_word & \\\n\t\t\t ~PCI_COMMAND_INVALIDATE);\n#endif\n\n/*****************************************************************************/\n/* 2.4.10 => 2.4.9 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) )\n\n/**************************************/\n/* MODULE API */\n\n#ifndef MODULE_LICENSE\n\t#define MODULE_LICENSE(X)\n#endif\n\n/**************************************/\n/* OTHER */\n\n#undef min\n#define min(x,y) ({ \\\n\tconst typeof(x) _x = (x);\t\\\n\tconst typeof(y) _y = (y);\t\\\n\t(void) (&_x == &_y);\t\t\\\n\t_x < _y ? _x : _y; })\n\n#undef max\n#define max(x,y) ({ \\\n\tconst typeof(x) _x = (x);\t\\\n\tconst typeof(y) _y = (y);\t\\\n\t(void) (&_x == &_y);\t\t\\\n\t_x > _y ? _x : _y; })\n\n#define min_t(type,x,y) ({ \\\n\ttype _x = (x); \\\n\ttype _y = (y); \\\n\t_x < _y ? _x : _y; })\n\n#define max_t(type,x,y) ({ \\\n\ttype _x = (x); \\\n\ttype _y = (y); \\\n\t_x > _y ? _x : _y; })\n\n#ifndef list_for_each_safe\n#define list_for_each_safe(pos, n, head) \\\n\tfor (pos = (head)->next, n = pos->next; pos != (head); \\\n\t\tpos = n, n = pos->next)\n#endif\n\n#ifndef ____cacheline_aligned_in_smp\n#ifdef CONFIG_SMP\n#define ____cacheline_aligned_in_smp ____cacheline_aligned\n#else\n#define ____cacheline_aligned_in_smp\n#endif /* CONFIG_SMP */\n#endif\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,8) )\nextern int _kc_snprintf(char * buf, size_t size, const char *fmt, ...);\n#define snprintf(buf, size, fmt, args...) _kc_snprintf(buf, size, fmt, ##args)\nextern int _kc_vsnprintf(char *buf, size_t size, const char *fmt, va_list args);\n#define vsnprintf(buf, size, fmt, args) _kc_vsnprintf(buf, size, fmt, args)\n#else /* 2.4.8 => 2.4.9 */\nextern int snprintf(char * buf, size_t size, const char *fmt, ...);\nextern int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);\n#endif\n#endif /* 2.4.10 -> 2.4.6 */\n\n\n/*****************************************************************************/\n/* 2.4.12 => 2.4.10 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,12) )\n#ifndef HAVE_NETIF_MSG\n#define HAVE_NETIF_MSG 1\nenum {\n\tNETIF_MSG_DRV\t\t= 0x0001,\n\tNETIF_MSG_PROBE\t\t= 0x0002,\n\tNETIF_MSG_LINK\t\t= 0x0004,\n\tNETIF_MSG_TIMER\t\t= 0x0008,\n\tNETIF_MSG_IFDOWN\t= 0x0010,\n\tNETIF_MSG_IFUP\t\t= 0x0020,\n\tNETIF_MSG_RX_ERR\t= 0x0040,\n\tNETIF_MSG_TX_ERR\t= 0x0080,\n\tNETIF_MSG_TX_QUEUED\t= 0x0100,\n\tNETIF_MSG_INTR\t\t= 0x0200,\n\tNETIF_MSG_TX_DONE\t= 0x0400,\n\tNETIF_MSG_RX_STATUS\t= 0x0800,\n\tNETIF_MSG_PKTDATA\t= 0x1000,\n\tNETIF_MSG_HW\t\t= 0x2000,\n\tNETIF_MSG_WOL\t\t= 0x4000,\n};\n\n#define netif_msg_drv(p)\t((p)->msg_enable & NETIF_MSG_DRV)\n#define netif_msg_probe(p)\t((p)->msg_enable & NETIF_MSG_PROBE)\n#define netif_msg_link(p)\t((p)->msg_enable & NETIF_MSG_LINK)\n#define netif_msg_timer(p)\t((p)->msg_enable & NETIF_MSG_TIMER)\n#define netif_msg_ifdown(p)\t((p)->msg_enable & NETIF_MSG_IFDOWN)\n#define netif_msg_ifup(p)\t((p)->msg_enable & NETIF_MSG_IFUP)\n#define netif_msg_rx_err(p)\t((p)->msg_enable & NETIF_MSG_RX_ERR)\n#define netif_msg_tx_err(p)\t((p)->msg_enable & NETIF_MSG_TX_ERR)\n#define netif_msg_tx_queued(p)\t((p)->msg_enable & NETIF_MSG_TX_QUEUED)\n#define netif_msg_intr(p)\t((p)->msg_enable & NETIF_MSG_INTR)\n#define netif_msg_tx_done(p)\t((p)->msg_enable & NETIF_MSG_TX_DONE)\n#define netif_msg_rx_status(p)\t((p)->msg_enable & NETIF_MSG_RX_STATUS)\n#define netif_msg_pktdata(p)\t((p)->msg_enable & NETIF_MSG_PKTDATA)\n#endif /* !HAVE_NETIF_MSG */\n#endif /* 2.4.12 => 2.4.10 */\n\n/*****************************************************************************/\n/* 2.4.13 => 2.4.12 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,13) )\n\n/**************************************/\n/* PCI DMA MAPPING */\n\n#ifndef virt_to_page\n\t#define virt_to_page(v) (mem_map + (virt_to_phys(v) >> PAGE_SHIFT))\n#endif\n\n#ifndef pci_map_page\n#define pci_map_page _kc_pci_map_page\nextern u64 _kc_pci_map_page(struct pci_dev *dev, struct page *page, unsigned long offset, size_t size, int direction);\n#endif\n\n#ifndef pci_unmap_page\n#define pci_unmap_page _kc_pci_unmap_page\nextern void _kc_pci_unmap_page(struct pci_dev *dev, u64 dma_addr, size_t size, int direction);\n#endif\n\n/* pci_set_dma_mask takes dma_addr_t, which is only 32-bits prior to 2.4.13 */\n\n#undef DMA_32BIT_MASK\n#define DMA_32BIT_MASK\t0xffffffff\n#undef DMA_64BIT_MASK\n#define DMA_64BIT_MASK\t0xffffffff\n\n/**************************************/\n/* OTHER */\n\n#ifndef cpu_relax\n#define cpu_relax()\trep_nop()\n#endif\n\nstruct vlan_ethhdr {\n\tunsigned char h_dest[ETH_ALEN];\n\tunsigned char h_source[ETH_ALEN];\n\tunsigned short h_vlan_proto;\n\tunsigned short h_vlan_TCI;\n\tunsigned short h_vlan_encapsulated_proto;\n};\n#endif /* 2.4.13 => 2.4.12 */\n\n/*****************************************************************************/\n/* 2.4.17 => 2.4.12 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17) )\n\n#ifndef __devexit_p\n\t#define __devexit_p(x) &(x)\n#endif\n\n#endif /* 2.4.17 => 2.4.13 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,18) )\n#define NETIF_MSG_HW\t0x2000\n#define NETIF_MSG_WOL\t0x4000\n\n#ifndef netif_msg_hw\n#define netif_msg_hw(p)\t\t((p)->msg_enable & NETIF_MSG_HW)\n#endif\n#ifndef netif_msg_wol\n#define netif_msg_wol(p)\t((p)->msg_enable & NETIF_MSG_WOL)\n#endif\n#endif /* 2.4.18 */\n\n/*****************************************************************************/\n\n/*****************************************************************************/\n/* 2.4.20 => 2.4.19 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,20) )\n\n/* we won't support NAPI on less than 2.4.20 */\n#ifdef NAPI\n#undef NAPI\n#undef CONFIG_IXGBE_NAPI\n#endif\n\n#endif /* 2.4.20 => 2.4.19 */\n\n/*****************************************************************************/\n/* 2.4.22 => 2.4.17 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) )\n#define pci_name(x)\t((x)->slot_name)\n#endif\n\n/*****************************************************************************/\n/* 2.4.22 => 2.4.17 */\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) )\n#ifndef IXGBE_NO_LRO\n/* Don't enable LRO for these legacy kernels */\n#define IXGBE_NO_LRO\n#endif\n#endif\n\n/*****************************************************************************/\n/*****************************************************************************/\n/* 2.4.23 => 2.4.22 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,23) )\n/*****************************************************************************/\n#ifdef NAPI\n#ifndef netif_poll_disable\n#define netif_poll_disable(x) _kc_netif_poll_disable(x)\nstatic inline void _kc_netif_poll_disable(struct net_device *netdev)\n{\n\twhile (test_and_set_bit(__LINK_STATE_RX_SCHED, &netdev->state)) {\n\t\t/* No hurry */\n\t\tcurrent->state = TASK_INTERRUPTIBLE;\n\t\tschedule_timeout(1);\n\t}\n}\n#endif\n#ifndef netif_poll_enable\n#define netif_poll_enable(x) _kc_netif_poll_enable(x)\nstatic inline void _kc_netif_poll_enable(struct net_device *netdev)\n{\n\tclear_bit(__LINK_STATE_RX_SCHED, &netdev->state);\n}\n#endif\n#endif /* NAPI */\n#ifndef netif_tx_disable\n#define netif_tx_disable(x) _kc_netif_tx_disable(x)\nstatic inline void _kc_netif_tx_disable(struct net_device *dev)\n{\n\tspin_lock_bh(&dev->xmit_lock);\n\tnetif_stop_queue(dev);\n\tspin_unlock_bh(&dev->xmit_lock);\n}\n#endif\n#else /* 2.4.23 => 2.4.22 */\n#define HAVE_SCTP\n#endif /* 2.4.23 => 2.4.22 */\n\n/*****************************************************************************/\n/* 2.6.4 => 2.6.0 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,25) || \\\n ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \\\n LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) )\n#define ETHTOOL_OPS_COMPAT\n#endif /* 2.6.4 => 2.6.0 */\n\n/*****************************************************************************/\n/* 2.5.71 => 2.4.x */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,71) )\n#define sk_protocol protocol\n#define pci_get_device pci_find_device\n#endif /* 2.5.70 => 2.4.x */\n\n/*****************************************************************************/\n/* < 2.4.27 or 2.6.0 <= 2.6.5 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) || \\\n ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) && \\\n LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) )\n\n#ifndef netif_msg_init\n#define netif_msg_init _kc_netif_msg_init\nstatic inline u32 _kc_netif_msg_init(int debug_value, int default_msg_enable_bits)\n{\n\t/* use default */\n\tif (debug_value < 0 || debug_value >= (sizeof(u32) * 8))\n\t\treturn default_msg_enable_bits;\n\tif (debug_value == 0) /* no output */\n\t\treturn 0;\n\t/* set low N bits */\n\treturn (1 << debug_value) -1;\n}\n#endif\n\n#endif /* < 2.4.27 or 2.6.0 <= 2.6.5 */\n/*****************************************************************************/\n#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \\\n (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \\\n ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) )))\n#define netdev_priv(x) x->priv\n#endif\n\n/*****************************************************************************/\n/* <= 2.5.0 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) )\n#include \n#undef pci_register_driver\n#define pci_register_driver pci_module_init\n\n/*\n * Most of the dma compat code is copied/modifed from the 2.4.37\n * /include/linux/libata-compat.h header file\n */\n/* These definitions mirror those in pci.h, so they can be used\n * interchangeably with their PCI_ counterparts */\nenum dma_data_direction {\n\tDMA_BIDIRECTIONAL = 0,\n\tDMA_TO_DEVICE = 1,\n\tDMA_FROM_DEVICE = 2,\n\tDMA_NONE = 3,\n};\n\nstruct device {\n\tstruct pci_dev pdev;\n};\n\nstatic inline struct pci_dev *to_pci_dev (struct device *dev)\n{\n\treturn (struct pci_dev *) dev;\n}\nstatic inline struct device *pci_dev_to_dev(struct pci_dev *pdev)\n{\n\treturn (struct device *) pdev;\n}\n\n#define pdev_printk(lvl, pdev, fmt, args...)\t\\\n\tprintk(\"%s %s: \" fmt, lvl, pci_name(pdev), ## args)\n#define dev_err(dev, fmt, args...) \\\n\tpdev_printk(KERN_ERR, to_pci_dev(dev), fmt, ## args)\n#define dev_info(dev, fmt, args...) \\\n\tpdev_printk(KERN_INFO, to_pci_dev(dev), fmt, ## args)\n#define dev_warn(dev, fmt, args...) \\\n\tpdev_printk(KERN_WARNING, to_pci_dev(dev), fmt, ## args)\n\n/* NOTE: dangerous! we ignore the 'gfp' argument */\n#define dma_alloc_coherent(dev,sz,dma,gfp) \\\n\tpci_alloc_consistent(to_pci_dev(dev),(sz),(dma))\n#define dma_free_coherent(dev,sz,addr,dma_addr) \\\n\tpci_free_consistent(to_pci_dev(dev),(sz),(addr),(dma_addr))\n\n#define dma_map_page(dev,a,b,c,d) \\\n\tpci_map_page(to_pci_dev(dev),(a),(b),(c),(d))\n#define dma_unmap_page(dev,a,b,c) \\\n\tpci_unmap_page(to_pci_dev(dev),(a),(b),(c))\n\n#define dma_map_single(dev,a,b,c) \\\n\tpci_map_single(to_pci_dev(dev),(a),(b),(c))\n#define dma_unmap_single(dev,a,b,c) \\\n\tpci_unmap_single(to_pci_dev(dev),(a),(b),(c))\n\n#define dma_sync_single(dev,a,b,c) \\\n\tpci_dma_sync_single(to_pci_dev(dev),(a),(b),(c))\n\n/* for range just sync everything, that's all the pci API can do */\n#define dma_sync_single_range(dev,addr,off,sz,dir) \\\n\tpci_dma_sync_single(to_pci_dev(dev),(addr),(off)+(sz),(dir))\n\n#define dma_set_mask(dev,mask) \\\n\tpci_set_dma_mask(to_pci_dev(dev),(mask))\n\n/* hlist_* code - double linked lists */\nstruct hlist_head {\n\tstruct hlist_node *first;\n};\n\nstruct hlist_node {\n\tstruct hlist_node *next, **pprev;\n};\n\nstatic inline void __hlist_del(struct hlist_node *n)\n{\n\tstruct hlist_node *next = n->next;\n\tstruct hlist_node **pprev = n->pprev;\n\t*pprev = next;\n\tif (next)\n\tnext->pprev = pprev;\n}\n\nstatic inline void hlist_del(struct hlist_node *n)\n{\n\t__hlist_del(n);\n\tn->next = NULL;\n\tn->pprev = NULL;\n}\n\nstatic inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h)\n{\n\tstruct hlist_node *first = h->first;\n\tn->next = first;\n\tif (first)\n\t\tfirst->pprev = &n->next;\n\th->first = n;\n\tn->pprev = &h->first;\n}\n\nstatic inline int hlist_empty(const struct hlist_head *h)\n{\n\treturn !h->first;\n}\n#define HLIST_HEAD_INIT { .first = NULL }\n#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL }\n#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL)\nstatic inline void INIT_HLIST_NODE(struct hlist_node *h)\n{\n\th->next = NULL;\n\th->pprev = NULL;\n}\n#define hlist_entry(ptr, type, member) container_of(ptr,type,member)\n\n#define hlist_for_each_entry(tpos, pos, head, member) \\\n\tfor (pos = (head)->first; \\\n\t pos && ({ prefetch(pos->next); 1;}) && \\\n\t\t({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \\\n\t pos = pos->next)\n\n#define hlist_for_each_entry_safe(tpos, pos, n, head, member) \\\n\tfor (pos = (head)->first; \\\n\t pos && ({ n = pos->next; 1; }) && \\\n\t\t({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \\\n\t pos = n)\n\n#ifndef might_sleep\n#define might_sleep()\n#endif\n#else\nstatic inline struct device *pci_dev_to_dev(struct pci_dev *pdev)\n{\n\treturn &pdev->dev;\n}\n#endif /* <= 2.5.0 */\n\n/*****************************************************************************/\n/* 2.5.28 => 2.4.23 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) )\n\nstatic inline void _kc_synchronize_irq(void)\n{\n\tsynchronize_irq();\n}\n#undef synchronize_irq\n#define synchronize_irq(X) _kc_synchronize_irq()\n\n#include \n#define work_struct tq_struct\n#undef INIT_WORK\n#define INIT_WORK(a,b) INIT_TQUEUE(a,(void (*)(void *))b,a)\n#undef container_of\n#define container_of list_entry\n#define schedule_work schedule_task\n#define flush_scheduled_work flush_scheduled_tasks\n#define cancel_work_sync(x) flush_scheduled_work()\n\n#endif /* 2.5.28 => 2.4.17 */\n\n/*****************************************************************************/\n/* 2.6.0 => 2.5.28 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )\n#undef get_cpu\n#define get_cpu() smp_processor_id()\n#undef put_cpu\n#define put_cpu() do { } while(0)\n#define MODULE_INFO(version, _version)\n#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT\n#define CONFIG_E1000_DISABLE_PACKET_SPLIT 1\n#endif\n#define CONFIG_IGB_DISABLE_PACKET_SPLIT 1\n\n#define dma_set_coherent_mask(dev,mask) 1\n\n#undef dev_put\n#define dev_put(dev) __dev_put(dev)\n\n#ifndef skb_fill_page_desc\n#define skb_fill_page_desc _kc_skb_fill_page_desc\nextern void _kc_skb_fill_page_desc(struct sk_buff *skb, int i, struct page *page, int off, int size);\n#endif\n\n#undef ALIGN\n#define ALIGN(x,a) (((x)+(a)-1)&~((a)-1))\n\n#ifndef page_count\n#define page_count(p) atomic_read(&(p)->count)\n#endif\n\n#ifdef MAX_NUMNODES\n#undef MAX_NUMNODES\n#endif\n#define MAX_NUMNODES 1\n\n/* find_first_bit and find_next bit are not defined for most\n * 2.4 kernels (except for the redhat 2.4.21 kernels\n */\n#include \n#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)\n#undef find_next_bit\n#define find_next_bit _kc_find_next_bit\nextern unsigned long _kc_find_next_bit(const unsigned long *addr,\n unsigned long size,\n unsigned long offset);\n#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)\n\n\n#ifndef netdev_name\nstatic inline const char *_kc_netdev_name(const struct net_device *dev)\n{\n\tif (strchr(dev->name, '%'))\n\t\treturn \"(unregistered net_device)\";\n\treturn dev->name;\n}\n#define netdev_name(netdev)\t_kc_netdev_name(netdev)\n#endif /* netdev_name */\n\n#ifndef strlcpy\n#define strlcpy _kc_strlcpy\nextern size_t _kc_strlcpy(char *dest, const char *src, size_t size);\n#endif /* strlcpy */\n\n#endif /* 2.6.0 => 2.5.28 */\n\n/*****************************************************************************/\n/* 2.6.4 => 2.6.0 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) )\n#define MODULE_VERSION(_version) MODULE_INFO(version, _version)\n#endif /* 2.6.4 => 2.6.0 */\n\n/*****************************************************************************/\n/* 2.6.5 => 2.6.0 */\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) )\n#define dma_sync_single_for_cpu\t\tdma_sync_single\n#define dma_sync_single_for_device\tdma_sync_single\n#define dma_sync_single_range_for_cpu\t\tdma_sync_single_range\n#define dma_sync_single_range_for_device\tdma_sync_single_range\n#ifndef pci_dma_mapping_error\n#define pci_dma_mapping_error _kc_pci_dma_mapping_error\nstatic inline int _kc_pci_dma_mapping_error(dma_addr_t dma_addr)\n{\n\treturn dma_addr == 0;\n}\n#endif\n#endif /* 2.6.5 => 2.6.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) )\nextern int _kc_scnprintf(char * buf, size_t size, const char *fmt, ...);\n#define scnprintf(buf, size, fmt, args...) _kc_scnprintf(buf, size, fmt, ##args)\n#endif /* < 2.6.4 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,6) )\n/* taken from 2.6 include/linux/bitmap.h */\n#undef bitmap_zero\n#define bitmap_zero _kc_bitmap_zero\nstatic inline void _kc_bitmap_zero(unsigned long *dst, int nbits)\n{\n if (nbits <= BITS_PER_LONG)\n *dst = 0UL;\n else {\n int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);\n memset(dst, 0, len);\n }\n}\n#define random_ether_addr _kc_random_ether_addr\nstatic inline void _kc_random_ether_addr(u8 *addr)\n{\n get_random_bytes(addr, ETH_ALEN);\n addr[0] &= 0xfe; /* clear multicast */\n addr[0] |= 0x02; /* set local assignment */\n}\n#define page_to_nid(x) 0\n\n#endif /* < 2.6.6 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,7) )\n#undef if_mii\n#define if_mii _kc_if_mii\nstatic inline struct mii_ioctl_data *_kc_if_mii(struct ifreq *rq)\n{\n\treturn (struct mii_ioctl_data *) &rq->ifr_ifru;\n}\n\n#ifndef __force\n#define __force\n#endif\n#endif /* < 2.6.7 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8) )\n#ifndef PCI_EXP_DEVCTL\n#define PCI_EXP_DEVCTL 8\n#endif\n#ifndef PCI_EXP_DEVCTL_CERE\n#define PCI_EXP_DEVCTL_CERE 0x0001\n#endif\n#define msleep(x)\tdo { set_current_state(TASK_UNINTERRUPTIBLE); \\\n\t\t\t\tschedule_timeout((x * HZ)/1000 + 2); \\\n\t\t\t} while (0)\n\n#endif /* < 2.6.8 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))\n#include \n#define __iomem\n\n#ifndef kcalloc\n#define kcalloc(n, size, flags) _kc_kzalloc(((n) * (size)), flags)\nextern void *_kc_kzalloc(size_t size, int flags);\n#endif\n#define MSEC_PER_SEC 1000L\nstatic inline unsigned int _kc_jiffies_to_msecs(const unsigned long j)\n{\n#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)\n\treturn (MSEC_PER_SEC / HZ) * j;\n#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)\n\treturn (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC);\n#else\n\treturn (j * MSEC_PER_SEC) / HZ;\n#endif\n}\nstatic inline unsigned long _kc_msecs_to_jiffies(const unsigned int m)\n{\n\tif (m > _kc_jiffies_to_msecs(MAX_JIFFY_OFFSET))\n\t\treturn MAX_JIFFY_OFFSET;\n#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ)\n\treturn (m + (MSEC_PER_SEC / HZ) - 1) / (MSEC_PER_SEC / HZ);\n#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)\n\treturn m * (HZ / MSEC_PER_SEC);\n#else\n\treturn (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC;\n#endif\n}\n\n#define msleep_interruptible _kc_msleep_interruptible\nstatic inline unsigned long _kc_msleep_interruptible(unsigned int msecs)\n{\n\tunsigned long timeout = _kc_msecs_to_jiffies(msecs) + 1;\n\n\twhile (timeout && !signal_pending(current)) {\n\t\t__set_current_state(TASK_INTERRUPTIBLE);\n\t\ttimeout = schedule_timeout(timeout);\n\t}\n\treturn _kc_jiffies_to_msecs(timeout);\n}\n\n/* Basic mode control register. */\n#define BMCR_SPEED1000\t\t0x0040 /* MSB of Speed (1000) */\n\n#ifndef __le16\n#define __le16 u16\n#endif\n#ifndef __le32\n#define __le32 u32\n#endif\n#ifndef __le64\n#define __le64 u64\n#endif\n#ifndef __be16\n#define __be16 u16\n#endif\n#ifndef __be32\n#define __be32 u32\n#endif\n#ifndef __be64\n#define __be64 u64\n#endif\n\nstatic inline struct vlan_ethhdr *vlan_eth_hdr(const struct sk_buff *skb)\n{\n\treturn (struct vlan_ethhdr *)skb->mac.raw;\n}\n\n/* Wake-On-Lan options. */\n#define WAKE_PHY\t\t(1 << 0)\n#define WAKE_UCAST\t\t(1 << 1)\n#define WAKE_MCAST\t\t(1 << 2)\n#define WAKE_BCAST\t\t(1 << 3)\n#define WAKE_ARP\t\t(1 << 4)\n#define WAKE_MAGIC\t\t(1 << 5)\n#define WAKE_MAGICSECURE\t(1 << 6) /* only meaningful if WAKE_MAGIC */\n\n#define skb_header_pointer _kc_skb_header_pointer\nstatic inline void *_kc_skb_header_pointer(const struct sk_buff *skb,\n\t\t\t\t\t int offset, int len, void *buffer)\n{\n\tint hlen = skb_headlen(skb);\n\n\tif (hlen - offset >= len)\n\t\treturn skb->data + offset;\n\n#ifdef MAX_SKB_FRAGS\n\tif (skb_copy_bits(skb, offset, buffer, len) < 0)\n\t\treturn NULL;\n\n\treturn buffer;\n#else\n\treturn NULL;\n#endif\n\n#ifndef NETDEV_TX_OK\n#define NETDEV_TX_OK 0\n#endif\n#ifndef NETDEV_TX_BUSY\n#define NETDEV_TX_BUSY 1\n#endif\n#ifndef NETDEV_TX_LOCKED\n#define NETDEV_TX_LOCKED -1\n#endif\n}\n\n#ifndef __bitwise\n#define __bitwise\n#endif\n#endif /* < 2.6.9 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10) )\n#ifdef module_param_array_named\n#undef module_param_array_named\n#define module_param_array_named(name, array, type, nump, perm) \\\n\tstatic struct kparam_array __param_arr_##name \\\n\t= { ARRAY_SIZE(array), nump, param_set_##type, param_get_##type, \\\n\t sizeof(array[0]), array }; \\\n\tmodule_param_call(name, param_array_set, param_array_get, \\\n\t\t\t &__param_arr_##name, perm)\n#endif /* module_param_array_named */\n/*\n * num_online is broken for all < 2.6.10 kernels. This is needed to support\n * Node module parameter of ixgbe.\n */\n#undef num_online_nodes\n#define num_online_nodes(n) 1\nextern DECLARE_BITMAP(_kcompat_node_online_map, MAX_NUMNODES);\n#undef node_online_map\n#define node_online_map _kcompat_node_online_map\n#endif /* < 2.6.10 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11) )\n#define PCI_D0 0\n#define PCI_D1 1\n#define PCI_D2 2\n#define PCI_D3hot 3\n#define PCI_D3cold 4\ntypedef int pci_power_t;\n#define pci_choose_state(pdev,state) state\n#define PMSG_SUSPEND 3\n#define PCI_EXP_LNKCTL\t16\n\n#undef NETIF_F_LLTX\n\n#ifndef ARCH_HAS_PREFETCH\n#define prefetch(X)\n#endif\n\n#ifndef NET_IP_ALIGN\n#define NET_IP_ALIGN 2\n#endif\n\n#define KC_USEC_PER_SEC\t1000000L\n#define usecs_to_jiffies _kc_usecs_to_jiffies\nstatic inline unsigned int _kc_jiffies_to_usecs(const unsigned long j)\n{\n#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ)\n\treturn (KC_USEC_PER_SEC / HZ) * j;\n#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC)\n\treturn (j + (HZ / KC_USEC_PER_SEC) - 1)/(HZ / KC_USEC_PER_SEC);\n#else\n\treturn (j * KC_USEC_PER_SEC) / HZ;\n#endif\n}\nstatic inline unsigned long _kc_usecs_to_jiffies(const unsigned int m)\n{\n\tif (m > _kc_jiffies_to_usecs(MAX_JIFFY_OFFSET))\n\t\treturn MAX_JIFFY_OFFSET;\n#if HZ <= KC_USEC_PER_SEC && !(KC_USEC_PER_SEC % HZ)\n\treturn (m + (KC_USEC_PER_SEC / HZ) - 1) / (KC_USEC_PER_SEC / HZ);\n#elif HZ > KC_USEC_PER_SEC && !(HZ % KC_USEC_PER_SEC)\n\treturn m * (HZ / KC_USEC_PER_SEC);\n#else\n\treturn (m * HZ + KC_USEC_PER_SEC - 1) / KC_USEC_PER_SEC;\n#endif\n}\n#endif /* < 2.6.11 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,12) )\n#include \n#define USE_REBOOT_NOTIFIER\n\n/* Generic MII registers. */\n#define MII_CTRL1000 0x09 /* 1000BASE-T control */\n#define MII_STAT1000 0x0a /* 1000BASE-T status */\n/* Advertisement control register. */\n#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */\n#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymmetric pause */\n/* 1000BASE-T Control register */\n#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */\n#ifndef is_zero_ether_addr\n#define is_zero_ether_addr _kc_is_zero_ether_addr\nstatic inline int _kc_is_zero_ether_addr(const u8 *addr)\n{\n\treturn !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);\n}\n#endif /* is_zero_ether_addr */\n#ifndef is_multicast_ether_addr\n#define is_multicast_ether_addr _kc_is_multicast_ether_addr\nstatic inline int _kc_is_multicast_ether_addr(const u8 *addr)\n{\n\treturn addr[0] & 0x01;\n}\n#endif /* is_multicast_ether_addr */\n#endif /* < 2.6.12 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,13) )\n#ifndef kstrdup\n#define kstrdup _kc_kstrdup\nextern char *_kc_kstrdup(const char *s, unsigned int gfp);\n#endif\n#endif /* < 2.6.13 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) )\n#define pm_message_t u32\n#ifndef kzalloc\n#define kzalloc _kc_kzalloc\nextern void *_kc_kzalloc(size_t size, int flags);\n#endif\n\n/* Generic MII registers. */\n#define MII_ESTATUS\t 0x0f\t/* Extended Status */\n/* Basic mode status register. */\n#define BMSR_ESTATEN\t\t0x0100\t/* Extended Status in R15 */\n/* Extended status register. */\n#define ESTATUS_1000_TFULL\t0x2000\t/* Can do 1000BT Full */\n#define ESTATUS_1000_THALF\t0x1000\t/* Can do 1000BT Half */\n\n#define ADVERTISED_Pause\t(1 << 13)\n#define ADVERTISED_Asym_Pause\t(1 << 14)\n\n#if (!(RHEL_RELEASE_CODE && \\\n (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,3)) && \\\n (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0))))\n#if ((LINUX_VERSION_CODE == KERNEL_VERSION(2,6,9)) && !defined(gfp_t))\n#define gfp_t unsigned\n#else\ntypedef unsigned gfp_t;\n#endif\n#endif /* !RHEL4.3->RHEL5.0 */\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,9) )\n#ifdef CONFIG_X86_64\n#define dma_sync_single_range_for_cpu(dev, dma_handle, offset, size, dir) \\\n\tdma_sync_single_for_cpu(dev, dma_handle, size, dir)\n#define dma_sync_single_range_for_device(dev, dma_handle, offset, size, dir) \\\n\tdma_sync_single_for_device(dev, dma_handle, size, dir)\n#endif\n#endif\n#endif /* < 2.6.14 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15) )\n#ifndef vmalloc_node\n#define vmalloc_node(a,b) vmalloc(a)\n#endif /* vmalloc_node*/\n\n#define setup_timer(_timer, _function, _data) \\\ndo { \\\n\t(_timer)->function = _function; \\\n\t(_timer)->data = _data; \\\n\tinit_timer(_timer); \\\n} while (0)\n#ifndef device_can_wakeup\n#define device_can_wakeup(dev)\t(1)\n#endif\n#ifndef device_set_wakeup_enable\n#define device_set_wakeup_enable(dev, val)\tdo{}while(0)\n#endif\n#ifndef device_init_wakeup\n#define device_init_wakeup(dev,val) do {} while (0)\n#endif\nstatic inline unsigned _kc_compare_ether_addr(const u8 *addr1, const u8 *addr2)\n{\n\tconst u16 *a = (const u16 *) addr1;\n\tconst u16 *b = (const u16 *) addr2;\n\n\treturn ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) != 0;\n}\n#undef compare_ether_addr\n#define compare_ether_addr(addr1, addr2) _kc_compare_ether_addr(addr1, addr2)\n#endif /* < 2.6.15 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16) )\n#undef DEFINE_MUTEX\n#define DEFINE_MUTEX(x)\tDECLARE_MUTEX(x)\n#define mutex_lock(x)\tdown_interruptible(x)\n#define mutex_unlock(x)\tup(x)\n\n#ifndef ____cacheline_internodealigned_in_smp\n#ifdef CONFIG_SMP\n#define ____cacheline_internodealigned_in_smp ____cacheline_aligned_in_smp\n#else\n#define ____cacheline_internodealigned_in_smp\n#endif /* CONFIG_SMP */\n#endif /* ____cacheline_internodealigned_in_smp */\n#undef HAVE_PCI_ERS\n#else /* 2.6.16 and above */\n#undef HAVE_PCI_ERS\n#define HAVE_PCI_ERS\n#endif /* < 2.6.16 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,17) )\n#ifndef first_online_node\n#define first_online_node 0\n#endif\n#ifndef NET_SKB_PAD\n#define NET_SKB_PAD 16\n#endif\n#endif /* < 2.6.17 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) )\n\n#ifndef IRQ_HANDLED\n#define irqreturn_t void\n#define IRQ_HANDLED\n#define IRQ_NONE\n#endif\n\n#ifndef IRQF_PROBE_SHARED\n#ifdef SA_PROBEIRQ\n#define IRQF_PROBE_SHARED SA_PROBEIRQ\n#else\n#define IRQF_PROBE_SHARED 0\n#endif\n#endif\n\n#ifndef IRQF_SHARED\n#define IRQF_SHARED SA_SHIRQ\n#endif\n\n#ifndef ARRAY_SIZE\n#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))\n#endif\n\n#ifndef FIELD_SIZEOF\n#define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))\n#endif\n\n#ifndef skb_is_gso\n#ifdef NETIF_F_TSO\n#define skb_is_gso _kc_skb_is_gso\nstatic inline int _kc_skb_is_gso(const struct sk_buff *skb)\n{\n\treturn skb_shinfo(skb)->gso_size;\n}\n#else\n#define skb_is_gso(a) 0\n#endif\n#endif\n\n#ifndef resource_size_t\n#define resource_size_t unsigned long\n#endif\n\n#ifdef skb_pad\n#undef skb_pad\n#endif\n#define skb_pad(x,y) _kc_skb_pad(x, y)\nint _kc_skb_pad(struct sk_buff *skb, int pad);\n#ifdef skb_padto\n#undef skb_padto\n#endif\n#define skb_padto(x,y) _kc_skb_padto(x, y)\nstatic inline int _kc_skb_padto(struct sk_buff *skb, unsigned int len)\n{\n\tunsigned int size = skb->len;\n\tif(likely(size >= len))\n\t\treturn 0;\n\treturn _kc_skb_pad(skb, len - size);\n}\n\n#ifndef DECLARE_PCI_UNMAP_ADDR\n#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \\\n\tdma_addr_t ADDR_NAME\n#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \\\n\tu32 LEN_NAME\n#define pci_unmap_addr(PTR, ADDR_NAME) \\\n\t((PTR)->ADDR_NAME)\n#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \\\n\t(((PTR)->ADDR_NAME) = (VAL))\n#define pci_unmap_len(PTR, LEN_NAME) \\\n\t((PTR)->LEN_NAME)\n#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \\\n\t(((PTR)->LEN_NAME) = (VAL))\n#endif /* DECLARE_PCI_UNMAP_ADDR */\n#endif /* < 2.6.18 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) )\n\n#ifndef DIV_ROUND_UP\n#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))\n#endif\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0) )\n#if (!((RHEL_RELEASE_CODE && \\\n ((RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(4,4) && \\\n RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0)) || \\\n (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,0)))) || \\\n (AX_RELEASE_CODE && AX_RELEASE_CODE > AX_RELEASE_VERSION(3,0))))\ntypedef irqreturn_t (*irq_handler_t)(int, void*, struct pt_regs *);\n#endif\n#if (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(6,0))\n#undef CONFIG_INET_LRO\n#undef CONFIG_INET_LRO_MODULE\n#undef CONFIG_FCOE\n#undef CONFIG_FCOE_MODULE\n#endif\ntypedef irqreturn_t (*new_handler_t)(int, void*);\nstatic inline irqreturn_t _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id)\n#else /* 2.4.x */\ntypedef void (*irq_handler_t)(int, void*, struct pt_regs *);\ntypedef void (*new_handler_t)(int, void*);\nstatic inline int _kc_request_irq(unsigned int irq, new_handler_t handler, unsigned long flags, const char *devname, void *dev_id)\n#endif /* >= 2.5.x */\n{\n\tirq_handler_t new_handler = (irq_handler_t) handler;\n\treturn request_irq(irq, new_handler, flags, devname, dev_id);\n}\n\n#undef request_irq\n#define request_irq(irq, handler, flags, devname, dev_id) _kc_request_irq((irq), (handler), (flags), (devname), (dev_id))\n\n#define irq_handler_t new_handler_t\n/* pci_restore_state and pci_save_state handles MSI/PCIE from 2.6.19 */\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,4)))\n#define PCIE_CONFIG_SPACE_LEN 256\n#define PCI_CONFIG_SPACE_LEN 64\n#define PCIE_LINK_STATUS 0x12\n#define pci_config_space_ich8lan() do {} while(0)\n#undef pci_save_state\nextern int _kc_pci_save_state(struct pci_dev *);\n#define pci_save_state(pdev) _kc_pci_save_state(pdev)\n#undef pci_restore_state\nextern void _kc_pci_restore_state(struct pci_dev *);\n#define pci_restore_state(pdev) _kc_pci_restore_state(pdev)\n#endif /* !(RHEL_RELEASE_CODE >= RHEL 5.4) */\n\n#ifdef HAVE_PCI_ERS\n#undef free_netdev\nextern void _kc_free_netdev(struct net_device *);\n#define free_netdev(netdev) _kc_free_netdev(netdev)\n#endif\nstatic inline int pci_enable_pcie_error_reporting(struct pci_dev *dev)\n{\n\treturn 0;\n}\n#define pci_disable_pcie_error_reporting(dev) do {} while (0)\n#define pci_cleanup_aer_uncorrect_error_status(dev) do {} while (0)\n\nextern void *_kc_kmemdup(const void *src, size_t len, unsigned gfp);\n#define kmemdup(src, len, gfp) _kc_kmemdup(src, len, gfp)\n#ifndef bool\n#define bool _Bool\n#define true 1\n#define false 0\n#endif\n#else /* 2.6.19 */\n#include \n#include \n#endif /* < 2.6.19 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) )\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,28) )\n#undef INIT_WORK\n#define INIT_WORK(_work, _func) \\\ndo { \\\n\tINIT_LIST_HEAD(&(_work)->entry); \\\n\t(_work)->pending = 0; \\\n\t(_work)->func = (void (*)(void *))_func; \\\n\t(_work)->data = _work; \\\n\tinit_timer(&(_work)->timer); \\\n} while (0)\n#endif\n\n#ifndef PCI_VDEVICE\n#define PCI_VDEVICE(ven, dev) \\\n\tPCI_VENDOR_ID_##ven, (dev), \\\n\tPCI_ANY_ID, PCI_ANY_ID, 0, 0\n#endif\n\n#ifndef round_jiffies\n#define round_jiffies(x) x\n#endif\n\n#define csum_offset csum\n\n#define HAVE_EARLY_VMALLOC_NODE\n#define dev_to_node(dev) -1\n#undef set_dev_node\n/* remove compiler warning with b=b, for unused variable */\n#define set_dev_node(a, b) do { (b) = (b); } while(0)\n\n#if (!(RHEL_RELEASE_CODE && \\\n (((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(4,7)) && \\\n (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0))) || \\\n (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,6)))) && \\\n !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10,2,0)))\ntypedef __u16 __bitwise __sum16;\ntypedef __u32 __bitwise __wsum;\n#endif\n\n#if (!(RHEL_RELEASE_CODE && \\\n (((RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(4,7)) && \\\n (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,0))) || \\\n (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5,4)))) && \\\n !(SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(10,2,0)))\nstatic inline __wsum csum_unfold(__sum16 n)\n{\n\treturn (__force __wsum)n;\n}\n#endif\n\n#else /* < 2.6.20 */\n#define HAVE_DEVICE_NUMA_NODE\n#endif /* < 2.6.20 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) )\n#define to_net_dev(class) container_of(class, struct net_device, class_dev)\n#define NETDEV_CLASS_DEV\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,5)))\n#define vlan_group_get_device(vg, id) (vg->vlan_devices[id])\n#define vlan_group_set_device(vg, id, dev)\t\t\\\n\tdo {\t\t\t\t\t\t\\\n\t\tif (vg) vg->vlan_devices[id] = dev;\t\\\n\t} while (0)\n#endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,5)) */\n#define pci_channel_offline(pdev) (pdev->error_state && \\\n\tpdev->error_state != pci_channel_io_normal)\n#define pci_request_selected_regions(pdev, bars, name) \\\n pci_request_regions(pdev, name)\n#define pci_release_selected_regions(pdev, bars) pci_release_regions(pdev);\n#endif /* < 2.6.21 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) )\n#define tcp_hdr(skb) (skb->h.th)\n#define tcp_hdrlen(skb) (skb->h.th->doff << 2)\n#define skb_transport_offset(skb) (skb->h.raw - skb->data)\n#define skb_transport_header(skb) (skb->h.raw)\n#define ipv6_hdr(skb) (skb->nh.ipv6h)\n#define ip_hdr(skb) (skb->nh.iph)\n#define skb_network_offset(skb) (skb->nh.raw - skb->data)\n#define skb_network_header(skb) (skb->nh.raw)\n#define skb_tail_pointer(skb) skb->tail\n#define skb_reset_tail_pointer(skb) \\\n\tdo { \\\n\t\tskb->tail = skb->data; \\\n\t} while (0)\n#define skb_copy_to_linear_data(skb, from, len) \\\n\t\t\t\tmemcpy(skb->data, from, len)\n#define skb_copy_to_linear_data_offset(skb, offset, from, len) \\\n\t\t\t\tmemcpy(skb->data + offset, from, len)\n#define skb_network_header_len(skb) (skb->h.raw - skb->nh.raw)\n#define pci_register_driver pci_module_init\n#define skb_mac_header(skb) skb->mac.raw\n\n#ifdef NETIF_F_MULTI_QUEUE\n#ifndef alloc_etherdev_mq\n#define alloc_etherdev_mq(_a, _b) alloc_etherdev(_a)\n#endif\n#endif /* NETIF_F_MULTI_QUEUE */\n\n#ifndef ETH_FCS_LEN\n#define ETH_FCS_LEN 4\n#endif\n#define cancel_work_sync(x) flush_scheduled_work()\n#ifndef udp_hdr\n#define udp_hdr _udp_hdr\nstatic inline struct udphdr *_udp_hdr(const struct sk_buff *skb)\n{\n\treturn (struct udphdr *)skb_transport_header(skb);\n}\n#endif\n\n#ifdef cpu_to_be16\n#undef cpu_to_be16\n#endif\n#define cpu_to_be16(x) __constant_htons(x)\n\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,1)))\nenum {\n\tDUMP_PREFIX_NONE,\n\tDUMP_PREFIX_ADDRESS,\n\tDUMP_PREFIX_OFFSET\n};\n#endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(5,1)) */\n#ifndef hex_asc\n#define hex_asc(x)\t\"0123456789abcdef\"[x]\n#endif\n#include \nextern void _kc_print_hex_dump(const char *level, const char *prefix_str,\n\t\t\t int prefix_type, int rowsize, int groupsize,\n\t\t\t const void *buf, size_t len, bool ascii);\n#define print_hex_dump(lvl, s, t, r, g, b, l, a) \\\n\t\t_kc_print_hex_dump(lvl, s, t, r, g, b, l, a)\n#else /* 2.6.22 */\n#define ETH_TYPE_TRANS_SETS_DEV\n#define HAVE_NETDEV_STATS_IN_NETDEV\n#endif /* < 2.6.22 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22) )\n#endif /* > 2.6.22 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23) )\n#define netif_subqueue_stopped(_a, _b) 0\n#ifndef PTR_ALIGN\n#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))\n#endif\n\n#ifndef CONFIG_PM_SLEEP\n#define CONFIG_PM_SLEEP\tCONFIG_PM\n#endif\n\n#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) )\n#define HAVE_ETHTOOL_GET_PERM_ADDR\n#endif /* 2.6.14 through 2.6.22 */\n#endif /* < 2.6.23 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) )\n#ifndef ETH_FLAG_LRO\n#define ETH_FLAG_LRO NETIF_F_LRO\n#endif\n\n/* if GRO is supported then the napi struct must already exist */\n#ifndef NETIF_F_GRO\n/* NAPI API changes in 2.6.24 break everything */\nstruct napi_struct {\n\t/* used to look up the real NAPI polling routine */\n\tint (*poll)(struct napi_struct *, int);\n\tstruct net_device *dev;\n\tint weight;\n};\n#endif\n\n#ifdef NAPI\nextern int __kc_adapter_clean(struct net_device *, int *);\nextern struct net_device *napi_to_poll_dev(struct napi_struct *napi);\n#define netif_napi_add(_netdev, _napi, _poll, _weight) \\\n\tdo { \\\n\t\tstruct napi_struct *__napi = (_napi); \\\n\t\tstruct net_device *poll_dev = napi_to_poll_dev(__napi); \\\n\t\tpoll_dev->poll = &(__kc_adapter_clean); \\\n\t\tpoll_dev->priv = (_napi); \\\n\t\tpoll_dev->weight = (_weight); \\\n\t\tset_bit(__LINK_STATE_RX_SCHED, &poll_dev->state); \\\n\t\tset_bit(__LINK_STATE_START, &poll_dev->state);\\\n\t\tdev_hold(poll_dev); \\\n\t\t__napi->poll = &(_poll); \\\n\t\t__napi->weight = (_weight); \\\n\t\t__napi->dev = (_netdev); \\\n\t} while (0)\n#define netif_napi_del(_napi) \\\n\tdo { \\\n\t\tstruct net_device *poll_dev = napi_to_poll_dev(_napi); \\\n\t\tWARN_ON(!test_bit(__LINK_STATE_RX_SCHED, &poll_dev->state)); \\\n\t\tdev_put(poll_dev); \\\n\t\tmemset(poll_dev, 0, sizeof(struct net_device));\\\n\t} while (0)\n#define napi_schedule_prep(_napi) \\\n\t(netif_running((_napi)->dev) && netif_rx_schedule_prep(napi_to_poll_dev(_napi)))\n#define napi_schedule(_napi) \\\n\tdo { \\\n\t\tif (napi_schedule_prep(_napi)) \\\n\t\t\t__netif_rx_schedule(napi_to_poll_dev(_napi)); \\\n\t} while (0)\n#define napi_enable(_napi) netif_poll_enable(napi_to_poll_dev(_napi))\n#define napi_disable(_napi) netif_poll_disable(napi_to_poll_dev(_napi))\n#define __napi_schedule(_napi) __netif_rx_schedule(napi_to_poll_dev(_napi))\n#ifndef NETIF_F_GRO\n#define napi_complete(_napi) netif_rx_complete(napi_to_poll_dev(_napi))\n#else\n#define napi_complete(_napi) \\\n\tdo { \\\n\t\tnapi_gro_flush(_napi); \\\n\t\tnetif_rx_complete(napi_to_poll_dev(_napi)); \\\n\t} while (0)\n#endif /* NETIF_F_GRO */\n#else /* NAPI */\n#define netif_napi_add(_netdev, _napi, _poll, _weight) \\\n\tdo { \\\n\t\tstruct napi_struct *__napi = _napi; \\\n\t\t_netdev->poll = &(_poll); \\\n\t\t_netdev->weight = (_weight); \\\n\t\t__napi->poll = &(_poll); \\\n\t\t__napi->weight = (_weight); \\\n\t\t__napi->dev = (_netdev); \\\n\t} while (0)\n#define netif_napi_del(_a) do {} while (0)\n#endif /* NAPI */\n\n#undef dev_get_by_name\n#define dev_get_by_name(_a, _b) dev_get_by_name(_b)\n#define __netif_subqueue_stopped(_a, _b) netif_subqueue_stopped(_a, _b)\n#ifndef DMA_BIT_MASK\n#define DMA_BIT_MASK(n)\t(((n) == 64) ? DMA_64BIT_MASK : ((1ULL<<(n))-1))\n#endif\n\n#ifdef NETIF_F_TSO6\n#define skb_is_gso_v6 _kc_skb_is_gso_v6\nstatic inline int _kc_skb_is_gso_v6(const struct sk_buff *skb)\n{\n\treturn skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6;\n}\n#endif /* NETIF_F_TSO6 */\n\n#ifndef KERN_CONT\n#define KERN_CONT\t\"\"\n#endif\n#else /* < 2.6.24 */\n#define HAVE_ETHTOOL_GET_SSET_COUNT\n#define HAVE_NETDEV_NAPI_LIST\n#endif /* < 2.6.24 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,24) )\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) )\n#include \n#else /* >= 3.2.0 */\n#include \n#endif /* else >= 3.2.0 */\n#endif /* > 2.6.24 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) )\n#define PM_QOS_CPU_DMA_LATENCY\t1\n\n#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18) )\n#include \n#define PM_QOS_DEFAULT_VALUE\tINFINITE_LATENCY\n#define pm_qos_add_requirement(pm_qos_class, name, value) \\\n\t\tset_acceptable_latency(name, value)\n#define pm_qos_remove_requirement(pm_qos_class, name) \\\n\t\tremove_acceptable_latency(name)\n#define pm_qos_update_requirement(pm_qos_class, name, value) \\\n\t\tmodify_acceptable_latency(name, value)\n#else\n#define PM_QOS_DEFAULT_VALUE\t-1\n#define pm_qos_add_requirement(pm_qos_class, name, value)\n#define pm_qos_remove_requirement(pm_qos_class, name)\n#define pm_qos_update_requirement(pm_qos_class, name, value) { \\\n\tif (value != PM_QOS_DEFAULT_VALUE) { \\\n\t\tprintk(KERN_WARNING \"%s: unable to set PM QoS requirement\\n\", \\\n\t\t\tpci_name(adapter->pdev)); \\\n\t} \\\n}\n\n#endif /* > 2.6.18 */\n\n#define pci_enable_device_mem(pdev) pci_enable_device(pdev)\n\n#ifndef DEFINE_PCI_DEVICE_TABLE\n#define DEFINE_PCI_DEVICE_TABLE(_table) struct pci_device_id _table[]\n#endif /* DEFINE_PCI_DEVICE_TABLE */\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) )\n#ifndef IXGBE_PROCFS\n#define IXGBE_PROCFS\n#endif /* IXGBE_PROCFS */\n#endif /* >= 2.6.0 */\n\n\n#else /* < 2.6.25 */\n\n#ifndef IXGBE_SYSFS\n#define IXGBE_SYSFS\n#endif /* IXGBE_SYSFS */\n\n\n#endif /* < 2.6.25 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) )\n#ifndef clamp_t\n#define clamp_t(type, val, min, max) ({\t\t\\\n\ttype __val = (val);\t\t\t\\\n\ttype __min = (min);\t\t\t\\\n\ttype __max = (max);\t\t\t\\\n\t__val = __val < __min ? __min : __val;\t\\\n\t__val > __max ? __max : __val; })\n#endif /* clamp_t */\n#ifdef NETIF_F_TSO\n#ifdef NETIF_F_TSO6\n#define netif_set_gso_max_size(_netdev, size) \\\n\tdo { \\\n\t\tif (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { \\\n\t\t\t_netdev->features &= ~NETIF_F_TSO; \\\n\t\t\t_netdev->features &= ~NETIF_F_TSO6; \\\n\t\t} else { \\\n\t\t\t_netdev->features |= NETIF_F_TSO; \\\n\t\t\t_netdev->features |= NETIF_F_TSO6; \\\n\t\t} \\\n\t} while (0)\n#else /* NETIF_F_TSO6 */\n#define netif_set_gso_max_size(_netdev, size) \\\n\tdo { \\\n\t\tif (adapter->flags & IXGBE_FLAG_DCB_ENABLED) \\\n\t\t\t_netdev->features &= ~NETIF_F_TSO; \\\n\t\telse \\\n\t\t\t_netdev->features |= NETIF_F_TSO; \\\n\t} while (0)\n#endif /* NETIF_F_TSO6 */\n#else\n#define netif_set_gso_max_size(_netdev, size) do {} while (0)\n#endif /* NETIF_F_TSO */\n#undef kzalloc_node\n#define kzalloc_node(_size, _flags, _node) kzalloc(_size, _flags)\n\nextern void _kc_pci_disable_link_state(struct pci_dev *dev, int state);\n#define pci_disable_link_state(p, s) _kc_pci_disable_link_state(p, s)\n#else /* < 2.6.26 */\n#include \n#define HAVE_NETDEV_VLAN_FEATURES\n#endif /* < 2.6.26 */\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27) )\nstatic inline void _kc_ethtool_cmd_speed_set(struct ethtool_cmd *ep,\n\t\t\t\t\t __u32 speed)\n{\n\tep->speed = (__u16)speed;\n\t/* ep->speed_hi = (__u16)(speed >> 16); */\n}\n#define ethtool_cmd_speed_set _kc_ethtool_cmd_speed_set\n\nstatic inline __u32 _kc_ethtool_cmd_speed(struct ethtool_cmd *ep)\n{\n\t/* no speed_hi before 2.6.27, and probably no need for it yet */\n\treturn (__u32)ep->speed;\n}\n#define ethtool_cmd_speed _kc_ethtool_cmd_speed\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15) )\n#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) && defined(CONFIG_PM))\n#define ANCIENT_PM 1\n#elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23)) && \\\n (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) && \\\n defined(CONFIG_PM_SLEEP))\n#define NEWER_PM 1\n#endif\n#if defined(ANCIENT_PM) || defined(NEWER_PM)\n#undef device_set_wakeup_enable\n#define device_set_wakeup_enable(dev, val) \\\n\tdo { \\\n\t\tu16 pmc = 0; \\\n\t\tint pm = pci_find_capability(adapter->pdev, PCI_CAP_ID_PM); \\\n\t\tif (pm) { \\\n\t\t\tpci_read_config_word(adapter->pdev, pm + PCI_PM_PMC, \\\n\t\t\t\t&pmc); \\\n\t\t} \\\n\t\t(dev)->power.can_wakeup = !!(pmc >> 11); \\\n\t\t(dev)->power.should_wakeup = (val && (pmc >> 11)); \\\n\t} while (0)\n#endif /* 2.6.15-2.6.22 and CONFIG_PM or 2.6.23-2.6.25 and CONFIG_PM_SLEEP */\n#endif /* 2.6.15 through 2.6.27 */\n#ifndef netif_napi_del\n#define netif_napi_del(_a) do {} while (0)\n#ifdef NAPI\n#ifdef CONFIG_NETPOLL\n#undef netif_napi_del\n#define netif_napi_del(_a) list_del(&(_a)->dev_list);\n#endif\n#endif\n#endif /* netif_napi_del */\n#ifdef dma_mapping_error\n#undef dma_mapping_error\n#endif\n#define dma_mapping_error(dev, dma_addr) pci_dma_mapping_error(dma_addr)\n\n#ifdef CONFIG_NETDEVICES_MULTIQUEUE\n#define HAVE_TX_MQ\n#endif\n\n#ifdef HAVE_TX_MQ\nextern void _kc_netif_tx_stop_all_queues(struct net_device *);\nextern void _kc_netif_tx_wake_all_queues(struct net_device *);\nextern void _kc_netif_tx_start_all_queues(struct net_device *);\n#define netif_tx_stop_all_queues(a) _kc_netif_tx_stop_all_queues(a)\n#define netif_tx_wake_all_queues(a) _kc_netif_tx_wake_all_queues(a)\n#define netif_tx_start_all_queues(a) _kc_netif_tx_start_all_queues(a)\n#undef netif_stop_subqueue\n#define netif_stop_subqueue(_ndev,_qi) do { \\\n\tif (netif_is_multiqueue((_ndev))) \\\n\t\tnetif_stop_subqueue((_ndev), (_qi)); \\\n\telse \\\n\t\tnetif_stop_queue((_ndev)); \\\n\t} while (0)\n#undef netif_start_subqueue\n#define netif_start_subqueue(_ndev,_qi) do { \\\n\tif (netif_is_multiqueue((_ndev))) \\\n\t\tnetif_start_subqueue((_ndev), (_qi)); \\\n\telse \\\n\t\tnetif_start_queue((_ndev)); \\\n\t} while (0)\n#else /* HAVE_TX_MQ */\n#define netif_tx_stop_all_queues(a) netif_stop_queue(a)\n#define netif_tx_wake_all_queues(a) netif_wake_queue(a)\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12) )\n#define netif_tx_start_all_queues(a) netif_start_queue(a)\n#else\n#define netif_tx_start_all_queues(a) do {} while (0)\n#endif\n#define netif_stop_subqueue(_ndev,_qi) netif_stop_queue((_ndev))\n#define netif_start_subqueue(_ndev,_qi) netif_start_queue((_ndev))\n#endif /* HAVE_TX_MQ */\n#ifndef NETIF_F_MULTI_QUEUE\n#define NETIF_F_MULTI_QUEUE 0\n#define netif_is_multiqueue(a) 0\n#define netif_wake_subqueue(a, b)\n#endif /* NETIF_F_MULTI_QUEUE */\n\n#ifndef __WARN_printf\nextern void __kc_warn_slowpath(const char *file, const int line,\n\t\tconst char *fmt, ...) __attribute__((format(printf, 3, 4)));\n#define __WARN_printf(arg...) __kc_warn_slowpath(__FILE__, __LINE__, arg)\n#endif /* __WARN_printf */\n\n#ifndef WARN\n#define WARN(condition, format...) ({\t\t\t\t\t\t\\\n\tint __ret_warn_on = !!(condition);\t\t\t\t\\\n\tif (unlikely(__ret_warn_on))\t\t\t\t\t\\\n\t\t__WARN_printf(format);\t\t\t\t\t\\\n\tunlikely(__ret_warn_on);\t\t\t\t\t\\\n})\n#endif /* WARN */\n#else /* < 2.6.27 */\n#define HAVE_TX_MQ\n#define HAVE_NETDEV_SELECT_QUEUE\n#endif /* < 2.6.27 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) )\n#define pci_ioremap_bar(pdev, bar)\tioremap(pci_resource_start(pdev, bar), \\\n\t\t\t\t\t pci_resource_len(pdev, bar))\n#define pci_wake_from_d3 _kc_pci_wake_from_d3\n#define pci_prepare_to_sleep _kc_pci_prepare_to_sleep\nextern int _kc_pci_wake_from_d3(struct pci_dev *dev, bool enable);\nextern int _kc_pci_prepare_to_sleep(struct pci_dev *dev);\n#define netdev_alloc_page(a) alloc_page(GFP_ATOMIC)\n#ifndef __skb_queue_head_init\nstatic inline void __kc_skb_queue_head_init(struct sk_buff_head *list)\n{\n\tlist->prev = list->next = (struct sk_buff *)list;\n\tlist->qlen = 0;\n}\n#define __skb_queue_head_init(_q) __kc_skb_queue_head_init(_q)\n#endif\n#endif /* < 2.6.28 */\n\n#ifndef skb_add_rx_frag\n#define skb_add_rx_frag _kc_skb_add_rx_frag\nextern void _kc_skb_add_rx_frag(struct sk_buff *, int, struct page *, int, int);\n#endif\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) )\n#ifndef swap\n#define swap(a, b) \\\n\tdo { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)\n#endif\n#define pci_request_selected_regions_exclusive(pdev, bars, name) \\\n\t\tpci_request_selected_regions(pdev, bars, name)\n#ifndef CONFIG_NR_CPUS\n#define CONFIG_NR_CPUS 1\n#endif /* CONFIG_NR_CPUS */\n#ifndef pcie_aspm_enabled\n#define pcie_aspm_enabled() (1)\n#endif /* pcie_aspm_enabled */\n#else /* < 2.6.29 */\n#ifndef HAVE_NET_DEVICE_OPS\n#define HAVE_NET_DEVICE_OPS\n#endif\n#ifdef CONFIG_DCB\n#define HAVE_PFC_MODE_ENABLE\n#endif /* CONFIG_DCB */\n#endif /* < 2.6.29 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) )\n#define skb_rx_queue_recorded(a) false\n#define skb_get_rx_queue(a) 0\n#undef CONFIG_FCOE\n#undef CONFIG_FCOE_MODULE\nextern u16 _kc_skb_tx_hash(struct net_device *dev, struct sk_buff *skb);\n#define skb_tx_hash(n, s) _kc_skb_tx_hash(n, s)\n#define skb_record_rx_queue(a, b) do {} while (0)\n#ifndef CONFIG_PCI_IOV\n#undef pci_enable_sriov\n#define pci_enable_sriov(a, b) -ENOTSUPP\n#undef pci_disable_sriov\n#define pci_disable_sriov(a) do {} while (0)\n#endif /* CONFIG_PCI_IOV */\n#ifndef pr_cont\n#define pr_cont(fmt, ...) \\\n\tprintk(KERN_CONT fmt, ##__VA_ARGS__)\n#endif /* pr_cont */\n#else\n#define HAVE_ASPM_QUIRKS\n#endif /* < 2.6.30 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31) )\n#define ETH_P_1588 0x88F7\n#define ETH_P_FIP 0x8914\n#ifndef netdev_uc_count\n#define netdev_uc_count(dev) ((dev)->uc_count)\n#endif\n#ifndef netdev_for_each_uc_addr\n#define netdev_for_each_uc_addr(uclist, dev) \\\n\tfor (uclist = dev->uc_list; uclist; uclist = uclist->next)\n#endif\n#else\n#ifndef HAVE_NETDEV_STORAGE_ADDRESS\n#define HAVE_NETDEV_STORAGE_ADDRESS\n#endif\n#ifndef HAVE_NETDEV_HW_ADDR\n#define HAVE_NETDEV_HW_ADDR\n#endif\n#ifndef HAVE_TRANS_START_IN_QUEUE\n#define HAVE_TRANS_START_IN_QUEUE\n#endif\n#endif /* < 2.6.31 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) )\n#undef netdev_tx_t\n#define netdev_tx_t int\n#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)\n#ifndef NETIF_F_FCOE_MTU\n#define NETIF_F_FCOE_MTU (1 << 26)\n#endif\n#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */\n\n#ifndef pm_runtime_get_sync\n#define pm_runtime_get_sync(dev)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_put\n#define pm_runtime_put(dev)\t\tdo {} while (0)\n#endif\n#ifndef pm_runtime_put_sync\n#define pm_runtime_put_sync(dev)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_resume\n#define pm_runtime_resume(dev)\t\tdo {} while (0)\n#endif\n#ifndef pm_schedule_suspend\n#define pm_schedule_suspend(dev, t)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_set_suspended\n#define pm_runtime_set_suspended(dev)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_disable\n#define pm_runtime_disable(dev)\t\tdo {} while (0)\n#endif\n#ifndef pm_runtime_put_noidle\n#define pm_runtime_put_noidle(dev)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_set_active\n#define pm_runtime_set_active(dev)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_enable\n#define pm_runtime_enable(dev)\tdo {} while (0)\n#endif\n#ifndef pm_runtime_get_noresume\n#define pm_runtime_get_noresume(dev)\tdo {} while (0)\n#endif\n#else /* < 2.6.32 */\n#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)\n#ifndef HAVE_NETDEV_OPS_FCOE_ENABLE\n#define HAVE_NETDEV_OPS_FCOE_ENABLE\n#endif\n#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */\n#ifdef CONFIG_DCB\n#ifndef HAVE_DCBNL_OPS_GETAPP\n#define HAVE_DCBNL_OPS_GETAPP\n#endif\n#endif /* CONFIG_DCB */\n#include \n/* IOV bad DMA target work arounds require at least this kernel rev support */\n#define HAVE_PCIE_TYPE\n#endif /* < 2.6.32 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33) )\n#ifndef pci_pcie_cap\n#define pci_pcie_cap(pdev) pci_find_capability(pdev, PCI_CAP_ID_EXP)\n#endif\n#ifndef IPV4_FLOW\n#define IPV4_FLOW 0x10\n#endif /* IPV4_FLOW */\n#ifndef IPV6_FLOW\n#define IPV6_FLOW 0x11\n#endif /* IPV6_FLOW */\n/* Features back-ported to RHEL6 or SLES11 SP1 after 2.6.32 */\n#if ( (RHEL_RELEASE_CODE && RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,0)) || \\\n (SLE_VERSION_CODE && SLE_VERSION_CODE >= SLE_VERSION(11,1,0)) )\n#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)\n#ifndef HAVE_NETDEV_OPS_FCOE_GETWWN\n#define HAVE_NETDEV_OPS_FCOE_GETWWN\n#endif\n#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */\n#endif /* RHEL6 or SLES11 SP1 */\n#ifndef __percpu\n#define __percpu\n#endif /* __percpu */\n#else /* < 2.6.33 */\n#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)\n#ifndef HAVE_NETDEV_OPS_FCOE_GETWWN\n#define HAVE_NETDEV_OPS_FCOE_GETWWN\n#endif\n#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */\n#define HAVE_ETHTOOL_SFP_DISPLAY_PORT\n#endif /* < 2.6.33 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34) )\n#ifndef ETH_FLAG_NTUPLE\n#define ETH_FLAG_NTUPLE NETIF_F_NTUPLE\n#endif\n\n#ifndef netdev_mc_count\n#define netdev_mc_count(dev) ((dev)->mc_count)\n#endif\n#ifndef netdev_mc_empty\n#define netdev_mc_empty(dev) (netdev_mc_count(dev) == 0)\n#endif\n#ifndef netdev_for_each_mc_addr\n#define netdev_for_each_mc_addr(mclist, dev) \\\n\tfor (mclist = dev->mc_list; mclist; mclist = mclist->next)\n#endif\n#ifndef netdev_uc_count\n#define netdev_uc_count(dev) ((dev)->uc.count)\n#endif\n#ifndef netdev_uc_empty\n#define netdev_uc_empty(dev) (netdev_uc_count(dev) == 0)\n#endif\n#ifndef netdev_for_each_uc_addr\n#define netdev_for_each_uc_addr(ha, dev) \\\n\tlist_for_each_entry(ha, &dev->uc.list, list)\n#endif\n#ifndef dma_set_coherent_mask\n#define dma_set_coherent_mask(dev,mask) \\\n\tpci_set_consistent_dma_mask(to_pci_dev(dev),(mask))\n#endif\n#ifndef pci_dev_run_wake\n#define pci_dev_run_wake(pdev)\t(0)\n#endif\n\n/* netdev logging taken from include/linux/netdevice.h */\n#ifndef netdev_name\nstatic inline const char *_kc_netdev_name(const struct net_device *dev)\n{\n\tif (dev->reg_state != NETREG_REGISTERED)\n\t\treturn \"(unregistered net_device)\";\n\treturn dev->name;\n}\n#define netdev_name(netdev)\t_kc_netdev_name(netdev)\n#endif /* netdev_name */\n\n#undef netdev_printk\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) )\n#define netdev_printk(level, netdev, format, args...)\t\t\\\ndo {\t\t\t\t\t\t\t\t\\\n\tstruct adapter_struct *kc_adapter = netdev_priv(netdev);\\\n\tstruct pci_dev *pdev = kc_adapter->pdev;\t\t\\\n\tprintk(\"%s %s: \" format, level, pci_name(pdev),\t\t\\\n\t ##args);\t\t\t\t\t\t\\\n} while(0)\n#elif ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21) )\n#define netdev_printk(level, netdev, format, args...)\t\t\\\ndo {\t\t\t\t\t\t\t\t\\\n\tstruct adapter_struct *kc_adapter = netdev_priv(netdev);\\\n\tstruct pci_dev *pdev = kc_adapter->pdev;\t\t\\\n\tstruct device *dev = pci_dev_to_dev(pdev);\t\t\\\n\tdev_printk(level, dev, \"%s: \" format,\t\t\t\\\n\t\t netdev_name(netdev), ##args);\t\t\\\n} while(0)\n#else /* 2.6.21 => 2.6.34 */\n#define netdev_printk(level, netdev, format, args...)\t\t\\\n\tdev_printk(level, (netdev)->dev.parent,\t\t\t\\\n\t\t \"%s: \" format,\t\t\t\t\\\n\t\t netdev_name(netdev), ##args)\n#endif /* <2.6.0 <2.6.21 <2.6.34 */\n#undef netdev_emerg\n#define netdev_emerg(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_EMERG, dev, format, ##args)\n#undef netdev_alert\n#define netdev_alert(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_ALERT, dev, format, ##args)\n#undef netdev_crit\n#define netdev_crit(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_CRIT, dev, format, ##args)\n#undef netdev_err\n#define netdev_err(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_ERR, dev, format, ##args)\n#undef netdev_warn\n#define netdev_warn(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_WARNING, dev, format, ##args)\n#undef netdev_notice\n#define netdev_notice(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_NOTICE, dev, format, ##args)\n#undef netdev_info\n#define netdev_info(dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_INFO, dev, format, ##args)\n#undef netdev_dbg\n#if defined(DEBUG)\n#define netdev_dbg(__dev, format, args...)\t\t\t\\\n\tnetdev_printk(KERN_DEBUG, __dev, format, ##args)\n#elif defined(CONFIG_DYNAMIC_DEBUG)\n#define netdev_dbg(__dev, format, args...)\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\\\n\tdynamic_dev_dbg((__dev)->dev.parent, \"%s: \" format,\t\\\n\t\t\tnetdev_name(__dev), ##args);\t\t\\\n} while (0)\n#else /* DEBUG */\n#define netdev_dbg(__dev, format, args...)\t\t\t\\\n({\t\t\t\t\t\t\t\t\\\n\tif (0)\t\t\t\t\t\t\t\\\n\t\tnetdev_printk(KERN_DEBUG, __dev, format, ##args); \\\n\t0;\t\t\t\t\t\t\t\\\n})\n#endif /* DEBUG */\n\n#undef netif_printk\n#define netif_printk(priv, type, level, dev, fmt, args...)\t\\\ndo {\t\t\t\t\t\t\t\t\\\n\tif (netif_msg_##type(priv))\t\t\t\t\\\n\t\tnetdev_printk(level, (dev), fmt, ##args);\t\\\n} while (0)\n\n#undef netif_emerg\n#define netif_emerg(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(emerg, priv, type, dev, fmt, ##args)\n#undef netif_alert\n#define netif_alert(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(alert, priv, type, dev, fmt, ##args)\n#undef netif_crit\n#define netif_crit(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(crit, priv, type, dev, fmt, ##args)\n#undef netif_err\n#define netif_err(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(err, priv, type, dev, fmt, ##args)\n#undef netif_warn\n#define netif_warn(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(warn, priv, type, dev, fmt, ##args)\n#undef netif_notice\n#define netif_notice(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(notice, priv, type, dev, fmt, ##args)\n#undef netif_info\n#define netif_info(priv, type, dev, fmt, args...)\t\t\\\n\tnetif_level(info, priv, type, dev, fmt, ##args)\n\n#ifdef SET_SYSTEM_SLEEP_PM_OPS\n#define HAVE_SYSTEM_SLEEP_PM_OPS\n#endif\n\n#ifndef for_each_set_bit\n#define for_each_set_bit(bit, addr, size) \\\n\tfor ((bit) = find_first_bit((addr), (size)); \\\n\t\t(bit) < (size); \\\n\t\t(bit) = find_next_bit((addr), (size), (bit) + 1))\n#endif /* for_each_set_bit */\n\n#ifndef DEFINE_DMA_UNMAP_ADDR\n#define DEFINE_DMA_UNMAP_ADDR DECLARE_PCI_UNMAP_ADDR\n#define DEFINE_DMA_UNMAP_LEN DECLARE_PCI_UNMAP_LEN\n#define dma_unmap_addr pci_unmap_addr\n#define dma_unmap_addr_set pci_unmap_addr_set\n#define dma_unmap_len pci_unmap_len\n#define dma_unmap_len_set pci_unmap_len_set\n#endif /* DEFINE_DMA_UNMAP_ADDR */\n#else /* < 2.6.34 */\n#define HAVE_SYSTEM_SLEEP_PM_OPS\n#ifndef HAVE_SET_RX_MODE\n#define HAVE_SET_RX_MODE\n#endif\n\n#endif /* < 2.6.34 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) )\n#ifndef numa_node_id\n#define numa_node_id() 0\n#endif\n#ifdef HAVE_TX_MQ\n#include \n#ifndef CONFIG_NETDEVICES_MULTIQUEUE\nvoid _kc_netif_set_real_num_tx_queues(struct net_device *, unsigned int);\n#define netif_set_real_num_tx_queues _kc_netif_set_real_num_tx_queues\n#else /* CONFIG_NETDEVICES_MULTI_QUEUE */\n#define netif_set_real_num_tx_queues(_netdev, _count) \\\n\tdo { \\\n\t\t(_netdev)->egress_subqueue_count = _count; \\\n\t} while (0)\n#endif /* CONFIG_NETDEVICES_MULTI_QUEUE */\n#else\n#define netif_set_real_num_tx_queues(_netdev, _count) do {} while(0)\n#endif /* HAVE_TX_MQ */\n#ifndef ETH_FLAG_RXHASH\n#define ETH_FLAG_RXHASH (1<<28)\n#endif /* ETH_FLAG_RXHASH */\n#else /* < 2.6.35 */\n#define HAVE_PM_QOS_REQUEST_LIST\n#define HAVE_IRQ_AFFINITY_HINT\n#endif /* < 2.6.35 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36) )\nextern int _kc_ethtool_op_set_flags(struct net_device *, u32, u32);\n#define ethtool_op_set_flags _kc_ethtool_op_set_flags\nextern u32 _kc_ethtool_op_get_flags(struct net_device *);\n#define ethtool_op_get_flags _kc_ethtool_op_get_flags\n\n#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS\n#ifdef NET_IP_ALIGN\n#undef NET_IP_ALIGN\n#endif\n#define NET_IP_ALIGN 0\n#endif /* CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS */\n\n#ifdef NET_SKB_PAD\n#undef NET_SKB_PAD\n#endif\n\n#if (L1_CACHE_BYTES > 32)\n#define NET_SKB_PAD L1_CACHE_BYTES\n#else\n#define NET_SKB_PAD 32\n#endif\n\nstatic inline struct sk_buff *_kc_netdev_alloc_skb_ip_align(struct net_device *dev,\n\t\t\t\t\t\t\t unsigned int length)\n{\n\tstruct sk_buff *skb;\n\n\tskb = alloc_skb(length + NET_SKB_PAD + NET_IP_ALIGN, GFP_ATOMIC);\n\tif (skb) {\n#if (NET_IP_ALIGN + NET_SKB_PAD)\n\t\tskb_reserve(skb, NET_IP_ALIGN + NET_SKB_PAD);\n#endif\n\t\tskb->dev = dev;\n\t}\n\treturn skb;\n}\n\n#ifdef netdev_alloc_skb_ip_align\n#undef netdev_alloc_skb_ip_align\n#endif\n#define netdev_alloc_skb_ip_align(n, l) _kc_netdev_alloc_skb_ip_align(n, l)\n\n#undef netif_level\n#define netif_level(level, priv, type, dev, fmt, args...)\t\\\ndo {\t\t\t\t\t\t\t\t\\\n\tif (netif_msg_##type(priv))\t\t\t\t\\\n\t\tnetdev_##level(dev, fmt, ##args);\t\t\\\n} while (0)\n\n#undef usleep_range\n#define usleep_range(min, max)\tmsleep(DIV_ROUND_UP(min, 1000))\n\n#else /* < 2.6.36 */\n#define HAVE_PM_QOS_REQUEST_ACTIVE\n#define HAVE_8021P_SUPPORT\n#define HAVE_NDO_GET_STATS64\n#endif /* < 2.6.36 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37) )\n#ifndef ETHTOOL_RXNTUPLE_ACTION_CLEAR\n#define ETHTOOL_RXNTUPLE_ACTION_CLEAR (-2)\n#endif\n#ifndef VLAN_N_VID\n#define VLAN_N_VID\tVLAN_GROUP_ARRAY_LEN\n#endif /* VLAN_N_VID */\n#ifndef ETH_FLAG_TXVLAN\n#define ETH_FLAG_TXVLAN (1 << 7)\n#endif /* ETH_FLAG_TXVLAN */\n#ifndef ETH_FLAG_RXVLAN\n#define ETH_FLAG_RXVLAN (1 << 8)\n#endif /* ETH_FLAG_RXVLAN */\n\nstatic inline void _kc_skb_checksum_none_assert(struct sk_buff *skb)\n{\n\tWARN_ON(skb->ip_summed != CHECKSUM_NONE);\n}\n#define skb_checksum_none_assert(skb) _kc_skb_checksum_none_assert(skb)\n\nstatic inline void *_kc_vzalloc_node(unsigned long size, int node)\n{\n\tvoid *addr = vmalloc_node(size, node);\n\tif (addr)\n\t\tmemset(addr, 0, size);\n\treturn addr;\n}\n#define vzalloc_node(_size, _node) _kc_vzalloc_node(_size, _node)\n\nstatic inline void *_kc_vzalloc(unsigned long size)\n{\n\tvoid *addr = vmalloc(size);\n\tif (addr)\n\t\tmemset(addr, 0, size);\n\treturn addr;\n}\n#define vzalloc(_size) _kc_vzalloc(_size)\n\n#ifndef vlan_get_protocol\nstatic inline __be16 __kc_vlan_get_protocol(const struct sk_buff *skb)\n{\n\tif (vlan_tx_tag_present(skb) ||\n\t skb->protocol != cpu_to_be16(ETH_P_8021Q))\n\t\treturn skb->protocol;\n\n\tif (skb_headlen(skb) < sizeof(struct vlan_ethhdr))\n\t\treturn 0;\n\n\treturn ((struct vlan_ethhdr*)skb->data)->h_vlan_encapsulated_proto;\n}\n#define vlan_get_protocol(_skb) __kc_vlan_get_protocol(_skb)\n#endif\n#ifdef HAVE_HW_TIME_STAMP\n#define SKBTX_HW_TSTAMP (1 << 0)\n#define SKBTX_IN_PROGRESS (1 << 2)\n#define SKB_SHARED_TX_IS_UNION\n#endif\n#if ( LINUX_VERSION_CODE > KERNEL_VERSION(2,4,18) )\n#ifndef HAVE_VLAN_RX_REGISTER\n#define HAVE_VLAN_RX_REGISTER\n#endif\n#endif /* > 2.4.18 */\n#endif /* < 2.6.37 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) )\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22) )\n#define skb_checksum_start_offset(skb) skb_transport_offset(skb)\n#else /* 2.6.22 -> 2.6.37 */\nstatic inline int _kc_skb_checksum_start_offset(const struct sk_buff *skb)\n{\n return skb->csum_start - skb_headroom(skb);\n}\n#define skb_checksum_start_offset(skb) _kc_skb_checksum_start_offset(skb)\n#endif /* 2.6.22 -> 2.6.37 */\n#ifdef CONFIG_DCB\n#ifndef IEEE_8021QAZ_MAX_TCS\n#define IEEE_8021QAZ_MAX_TCS 8\n#endif\n#ifndef DCB_CAP_DCBX_HOST\n#define DCB_CAP_DCBX_HOST\t\t0x01\n#endif\n#ifndef DCB_CAP_DCBX_LLD_MANAGED\n#define DCB_CAP_DCBX_LLD_MANAGED\t0x02\n#endif\n#ifndef DCB_CAP_DCBX_VER_CEE\n#define DCB_CAP_DCBX_VER_CEE\t\t0x04\n#endif\n#ifndef DCB_CAP_DCBX_VER_IEEE\n#define DCB_CAP_DCBX_VER_IEEE\t\t0x08\n#endif\n#ifndef DCB_CAP_DCBX_STATIC\n#define DCB_CAP_DCBX_STATIC\t\t0x10\n#endif\n#endif /* CONFIG_DCB */\n#else /* < 2.6.38 */\n#endif /* < 2.6.38 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39) )\n#ifndef skb_queue_reverse_walk_safe\n#define skb_queue_reverse_walk_safe(queue, skb, tmp)\t\t\t\t\\\n\t\tfor (skb = (queue)->prev, tmp = skb->prev;\t\t\t\\\n\t\t skb != (struct sk_buff *)(queue);\t\t\t\t\\\n\t\t skb = tmp, tmp = skb->prev)\n#endif\n#if (!(RHEL_RELEASE_CODE && RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,0)))\nextern u8 _kc_netdev_get_num_tc(struct net_device *dev);\n#define netdev_get_num_tc(dev) _kc_netdev_get_num_tc(dev)\nextern u8 _kc_netdev_get_prio_tc_map(struct net_device *dev, u8 up);\n#define netdev_get_prio_tc_map(dev, up) _kc_netdev_get_prio_tc_map(dev, up)\n#define netdev_set_prio_tc_map(dev, up, tc) do {} while (0)\n#else /* RHEL6.1 or greater */\n#ifndef HAVE_MQPRIO\n#define HAVE_MQPRIO\n#endif /* HAVE_MQPRIO */\n#ifdef CONFIG_DCB\n#ifndef HAVE_DCBNL_IEEE\n#define HAVE_DCBNL_IEEE\n#ifndef IEEE_8021QAZ_TSA_STRICT\n#define IEEE_8021QAZ_TSA_STRICT\t\t0\n#endif\n#ifndef IEEE_8021QAZ_TSA_ETS\n#define IEEE_8021QAZ_TSA_ETS\t\t2\n#endif\n#ifndef IEEE_8021QAZ_APP_SEL_ETHERTYPE\n#define IEEE_8021QAZ_APP_SEL_ETHERTYPE\t1\n#endif\n#endif\n#endif /* CONFIG_DCB */\n#endif /* !(RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(6,0)) */\n#else /* < 2.6.39 */\n#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)\n#ifndef HAVE_NETDEV_OPS_FCOE_DDP_TARGET\n#define HAVE_NETDEV_OPS_FCOE_DDP_TARGET\n#endif\n#endif /* CONFIG_FCOE || CONFIG_FCOE_MODULE */\n#ifndef HAVE_MQPRIO\n#define HAVE_MQPRIO\n#endif\n#ifndef HAVE_SETUP_TC\n#define HAVE_SETUP_TC\n#endif\n#ifdef CONFIG_DCB\n#ifndef HAVE_DCBNL_IEEE\n#define HAVE_DCBNL_IEEE\n#endif\n#endif /* CONFIG_DCB */\n#ifndef HAVE_NDO_SET_FEATURES\n#define HAVE_NDO_SET_FEATURES\n#endif\n#endif /* < 2.6.39 */\n\n/*****************************************************************************/\n/* use < 2.6.40 because of a Fedora 15 kernel update where they\n * updated the kernel version to 2.6.40.x and they back-ported 3.0 features\n * like set_phys_id for ethtool.\n */\n#undef ETHTOOL_GRXRINGS\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,40) )\n#ifdef ETHTOOL_GRXRINGS\n#ifndef FLOW_EXT\n#define\tFLOW_EXT\t0x80000000\nunion _kc_ethtool_flow_union {\n\tstruct ethtool_tcpip4_spec\t\ttcp_ip4_spec;\n\tstruct ethtool_usrip4_spec\t\tusr_ip4_spec;\n\t__u8\t\t\t\t\thdata[60];\n};\nstruct _kc_ethtool_flow_ext {\n\t__be16\tvlan_etype;\n\t__be16\tvlan_tci;\n\t__be32\tdata[2];\n};\nstruct _kc_ethtool_rx_flow_spec {\n\t__u32\t\tflow_type;\n\tunion _kc_ethtool_flow_union h_u;\n\tstruct _kc_ethtool_flow_ext h_ext;\n\tunion _kc_ethtool_flow_union m_u;\n\tstruct _kc_ethtool_flow_ext m_ext;\n\t__u64\t\tring_cookie;\n\t__u32\t\tlocation;\n};\n#define ethtool_rx_flow_spec _kc_ethtool_rx_flow_spec\n#endif /* FLOW_EXT */\n#endif\n\n#define pci_disable_link_state_locked pci_disable_link_state\n\n#ifndef PCI_LTR_VALUE_MASK\n#define PCI_LTR_VALUE_MASK\t0x000003ff\n#endif\n#ifndef PCI_LTR_SCALE_MASK\n#define PCI_LTR_SCALE_MASK\t0x00001c00\n#endif\n#ifndef PCI_LTR_SCALE_SHIFT\n#define PCI_LTR_SCALE_SHIFT\t10\n#endif\n\n#else /* < 2.6.40 */\n#define HAVE_ETHTOOL_SET_PHYS_ID\n#endif /* < 2.6.40 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) )\n#ifndef __netdev_alloc_skb_ip_align\n#define __netdev_alloc_skb_ip_align(d,l,_g) netdev_alloc_skb_ip_align(d,l)\n#endif /* __netdev_alloc_skb_ip_align */\n#define dcb_ieee_setapp(dev, app) dcb_setapp(dev, app)\n#define dcb_ieee_delapp(dev, app) 0\n#define dcb_ieee_getapp_mask(dev, app) (1 << app->priority)\n#else /* < 3.1.0 */\n#ifndef HAVE_DCBNL_IEEE_DELAPP\n#define HAVE_DCBNL_IEEE_DELAPP\n#endif\n#endif /* < 3.1.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) )\n#ifdef ETHTOOL_GRXRINGS\n#define HAVE_ETHTOOL_GET_RXNFC_VOID_RULE_LOCS\n#endif /* ETHTOOL_GRXRINGS */\n\n#ifndef skb_frag_size\n#define skb_frag_size(frag)\t_kc_skb_frag_size(frag)\nstatic inline unsigned int _kc_skb_frag_size(const skb_frag_t *frag)\n{\n\treturn frag->size;\n}\n#endif /* skb_frag_size */\n\n#ifndef skb_frag_size_sub\n#define skb_frag_size_sub(frag, delta)\t_kc_skb_frag_size_sub(frag, delta)\nstatic inline void _kc_skb_frag_size_sub(skb_frag_t *frag, int delta)\n{\n\tfrag->size -= delta;\n}\n#endif /* skb_frag_size_sub */\n\n#ifndef skb_frag_page\n#define skb_frag_page(frag)\t_kc_skb_frag_page(frag)\nstatic inline struct page *_kc_skb_frag_page(const skb_frag_t *frag)\n{\n\treturn frag->page;\n}\n#endif /* skb_frag_page */\n\n#ifndef skb_frag_address\n#define skb_frag_address(frag)\t_kc_skb_frag_address(frag)\nstatic inline void *_kc_skb_frag_address(const skb_frag_t *frag)\n{\n\treturn page_address(skb_frag_page(frag)) + frag->page_offset;\n}\n#endif /* skb_frag_address */\n\n#ifndef skb_frag_dma_map\n#define skb_frag_dma_map(dev,frag,offset,size,dir) \\\n\t\t_kc_skb_frag_dma_map(dev,frag,offset,size,dir)\nstatic inline dma_addr_t _kc_skb_frag_dma_map(struct device *dev,\n\t\t\t\t\t const skb_frag_t *frag,\n\t\t\t\t\t size_t offset, size_t size,\n\t\t\t\t\t enum dma_data_direction dir)\n{\n\treturn dma_map_page(dev, skb_frag_page(frag),\n\t\t\t frag->page_offset + offset, size, dir);\n}\n#endif /* skb_frag_dma_map */\n\n#ifndef __skb_frag_unref\n#define __skb_frag_unref(frag) __kc_skb_frag_unref(frag)\nstatic inline void __kc_skb_frag_unref(skb_frag_t *frag)\n{\n\tput_page(skb_frag_page(frag));\n}\n#endif /* __skb_frag_unref */\n#else /* < 3.2.0 */\n#ifndef HAVE_PCI_DEV_FLAGS_ASSIGNED\n#define HAVE_PCI_DEV_FLAGS_ASSIGNED\n#define HAVE_VF_SPOOFCHK_CONFIGURE\n#endif\n#endif /* < 3.2.0 */\n\n#if (RHEL_RELEASE_CODE && \\\n\t(RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6,2)) && \\\n\t(RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(7,0)))\n#undef ixgbe_get_netdev_tc_txq\n#define ixgbe_get_netdev_tc_txq(dev, tc) (&netdev_extended(dev)->qos_data.tc_to_txq[tc])\n#endif\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) )\ntypedef u32 kni_netdev_features_t;\n#else /* ! < 3.3.0 */\ntypedef netdev_features_t kni_netdev_features_t;\n#define HAVE_INT_NDO_VLAN_RX_ADD_VID\n#ifdef ETHTOOL_SRXNTUPLE\n#undef ETHTOOL_SRXNTUPLE\n#endif\n#endif /* < 3.3.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0) )\n#ifndef NETIF_F_RXFCS\n#define NETIF_F_RXFCS\t0\n#endif /* NETIF_F_RXFCS */\n#ifndef NETIF_F_RXALL\n#define NETIF_F_RXALL\t0\n#endif /* NETIF_F_RXALL */\n\n#define NUMTCS_RETURNS_U8\n\n\n#endif /* < 3.4.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) )\nstatic inline bool __kc_ether_addr_equal(const u8 *addr1, const u8 *addr2)\n{\n\treturn !compare_ether_addr(addr1, addr2);\n}\n#define ether_addr_equal(_addr1, _addr2) __kc_ether_addr_equal((_addr1),(_addr2))\n#else\n#define HAVE_FDB_OPS\n#endif /* < 3.5.0 */\n\n/*****************************************************************************/\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) )\n#define NETIF_F_HW_VLAN_TX NETIF_F_HW_VLAN_CTAG_TX\n#define NETIF_F_HW_VLAN_RX NETIF_F_HW_VLAN_CTAG_RX\n#define NETIF_F_HW_VLAN_FILTER NETIF_F_HW_VLAN_CTAG_FILTER\n#endif /* >= 3.10.0 */\n\n#if ( LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) )\n#ifdef CONFIG_PCI_IOV\nextern int __kc_pci_vfs_assigned(struct pci_dev *dev);\n#else\nstatic inline int __kc_pci_vfs_assigned(struct pci_dev *dev)\n{\n return 0;\n}\n#endif\n#define pci_vfs_assigned(dev) __kc_pci_vfs_assigned(dev)\n\n#endif\n\n#if ( LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0) )\n#define SET_ETHTOOL_OPS(netdev, ops) ((netdev)->ethtool_ops = (ops))\n#endif /* >= 3.16.0 */\n\n#endif /* _KCOMPAT_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/kni_dev.h", "content": "/*-\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n */\n\n#ifndef _KNI_DEV_H_\n#define _KNI_DEV_H_\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#ifdef RTE_KNI_VHOST\n#include \n#endif\n\n#include \n#define KNI_KTHREAD_RESCHEDULE_INTERVAL 5 /* us */\n\n/**\n * A structure describing the private information for a kni device.\n */\n\nstruct kni_dev {\n\t/* kni list */\n\tstruct list_head list;\n\n\tstruct net_device_stats stats;\n\tint status;\n\tuint16_t group_id; /* Group ID of a group of KNI devices */\n\tunsigned core_id; /* Core ID to bind */\n\tchar name[RTE_KNI_NAMESIZE]; /* Network device name */\n\tstruct task_struct *pthread;\n\n\t/* wait queue for req/resp */\n\twait_queue_head_t wq;\n\tstruct mutex sync_lock;\n\n\t/* PCI device id */\n\tuint16_t device_id;\n\n\t/* kni device */\n\tstruct net_device *net_dev;\n\tstruct net_device *lad_dev;\n\tstruct pci_dev *pci_dev;\n\n\t/* queue for packets to be sent out */\n\tvoid *tx_q;\n\n\t/* queue for the packets received */\n\tvoid *rx_q;\n\n\t/* queue for the allocated mbufs those can be used to save sk buffs */\n\tvoid *alloc_q;\n\n\t/* free queue for the mbufs to be freed */\n\tvoid *free_q;\n\n\t/* request queue */\n\tvoid *req_q;\n\n\t/* response queue */\n\tvoid *resp_q;\n\n\tvoid * sync_kva;\n\tvoid *sync_va;\n\n\tvoid *mbuf_kva;\n\tvoid *mbuf_va;\n\n\t/* mbuf size */\n\tunsigned mbuf_size;\n\n\t/* synchro for request processing */\n\tunsigned long synchro;\n\n#ifdef RTE_KNI_VHOST\n\tstruct kni_vhost_queue* vhost_queue;\n\tvolatile enum {\n\t\tBE_STOP = 0x1,\n\t\tBE_START = 0x2,\n\t\tBE_FINISH = 0x4,\n\t}vq_status;\n#endif\n};\n\n#define KNI_ERR(args...) printk(KERN_DEBUG \"KNI: Error: \" args)\n#define KNI_PRINT(args...) printk(KERN_DEBUG \"KNI: \" args)\n#ifdef RTE_KNI_KO_DEBUG\n\t#define KNI_DBG(args...) printk(KERN_DEBUG \"KNI: \" args)\n#else\n\t#define KNI_DBG(args...)\n#endif\n\n#ifdef RTE_KNI_VHOST\nunsigned int\nkni_poll(struct file *file, struct socket *sock, poll_table * wait);\nint kni_chk_vhost_rx(struct kni_dev *kni);\nint kni_vhost_init(struct kni_dev *kni);\nint kni_vhost_backend_release(struct kni_dev *kni);\n\nstruct kni_vhost_queue {\n\tstruct sock sk;\n\tstruct socket *sock;\n\tint vnet_hdr_sz;\n\tstruct kni_dev *kni;\n\tint sockfd;\n\tunsigned int flags;\n\tstruct sk_buff* cache;\n\tstruct rte_kni_fifo* fifo;\n};\n\n#endif\n\n#ifdef RTE_KNI_VHOST_DEBUG_RX\n\t#define KNI_DBG_RX(args...) printk(KERN_DEBUG \"KNI RX: \" args)\n#else\n\t#define KNI_DBG_RX(args...)\n#endif\n\n#ifdef RTE_KNI_VHOST_DEBUG_TX\n\t#define KNI_DBG_TX(args...) printk(KERN_DEBUG \"KNI TX: \" args)\n#else\n\t#define KNI_DBG_TX(args...)\n#endif\n\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/kni/kni_ethtool.c", "content": "/*-\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n */\n\n#include \n#include \n#include \n#include \"kni_dev.h\"\n\nstatic int\nkni_check_if_running(struct net_device *dev)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\tif (priv->lad_dev)\n\t\treturn 0;\n\telse\n\t\treturn -EOPNOTSUPP;\n}\n\nstatic void\nkni_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\tpriv->lad_dev->ethtool_ops->get_drvinfo(priv->lad_dev, info);\n}\n\nstatic int\nkni_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\treturn priv->lad_dev->ethtool_ops->get_settings(priv->lad_dev, ecmd);\n}\n\nstatic int\nkni_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\treturn priv->lad_dev->ethtool_ops->set_settings(priv->lad_dev, ecmd);\n}\n\nstatic void\nkni_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\tpriv->lad_dev->ethtool_ops->get_wol(priv->lad_dev, wol);\n}\n\nstatic int\nkni_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\treturn priv->lad_dev->ethtool_ops->set_wol(priv->lad_dev, wol);\n}\n\nstatic int\nkni_nway_reset(struct net_device *dev)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\treturn priv->lad_dev->ethtool_ops->nway_reset(priv->lad_dev);\n}\n\nstatic int\nkni_get_eeprom_len(struct net_device *dev)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\treturn priv->lad_dev->ethtool_ops->get_eeprom_len(priv->lad_dev);\n}\n\nstatic int\nkni_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,\n\t\t\t\t\t\t\tu8 *bytes)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\treturn priv->lad_dev->ethtool_ops->get_eeprom(priv->lad_dev, eeprom,\n\t\t\t\t\t\t\t\tbytes);\n}\n\nstatic int\nkni_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,\n\t\t\t\t\t\t\tu8 *bytes)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\treturn priv->lad_dev->ethtool_ops->set_eeprom(priv->lad_dev, eeprom,\n\t\t\t\t\t\t\t\tbytes);\n}\n\nstatic void\nkni_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ring)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\tpriv->lad_dev->ethtool_ops->get_ringparam(priv->lad_dev, ring);\n}\n\nstatic int\nkni_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ring)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\treturn priv->lad_dev->ethtool_ops->set_ringparam(priv->lad_dev, ring);\n}\n\nstatic void\nkni_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\tpriv->lad_dev->ethtool_ops->get_pauseparam(priv->lad_dev, pause);\n}\n\nstatic int\nkni_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *pause)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\treturn priv->lad_dev->ethtool_ops->set_pauseparam(priv->lad_dev,\n\t\t\t\t\t\t\t\tpause);\n}\n\nstatic u32\nkni_get_msglevel(struct net_device *dev)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\treturn priv->lad_dev->ethtool_ops->get_msglevel(priv->lad_dev);\n}\n\nstatic void\nkni_set_msglevel(struct net_device *dev, u32 data)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\tpriv->lad_dev->ethtool_ops->set_msglevel(priv->lad_dev, data);\n}\n\nstatic int\nkni_get_regs_len(struct net_device *dev)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\treturn priv->lad_dev->ethtool_ops->get_regs_len(priv->lad_dev);\n}\n\nstatic void\nkni_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\tpriv->lad_dev->ethtool_ops->get_regs(priv->lad_dev, regs, p);\n}\n\nstatic void\nkni_get_strings(struct net_device *dev, u32 stringset, u8 *data)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\tpriv->lad_dev->ethtool_ops->get_strings(priv->lad_dev, stringset,\n\t\t\t\t\t\t\t\tdata);\n}\n\nstatic int\nkni_get_sset_count(struct net_device *dev, int sset)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\treturn priv->lad_dev->ethtool_ops->get_sset_count(priv->lad_dev, sset);\n}\n\nstatic void\nkni_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats,\n\t\t\t\t\t\t\t\tu64 *data)\n{\n\tstruct kni_dev *priv = netdev_priv(dev);\n\tpriv->lad_dev->ethtool_ops->get_ethtool_stats(priv->lad_dev, stats,\n\t\t\t\t\t\t\t\tdata);\n}\n\nstruct ethtool_ops kni_ethtool_ops = {\n\t.begin \t\t\t\t= kni_check_if_running,\n\t.get_drvinfo\t\t= kni_get_drvinfo,\n\t.get_settings\t\t= kni_get_settings,\n\t.set_settings\t\t= kni_set_settings,\n\t.get_regs_len\t\t= kni_get_regs_len,\n\t.get_regs\t\t\t= kni_get_regs,\n\t.get_wol\t\t\t= kni_get_wol,\n\t.set_wol\t\t\t= kni_set_wol,\n\t.nway_reset\t\t\t= kni_nway_reset,\n\t.get_link\t\t\t= ethtool_op_get_link,\n\t.get_eeprom_len\t\t= kni_get_eeprom_len,\n\t.get_eeprom\t\t\t= kni_get_eeprom,\n\t.set_eeprom\t\t\t= kni_set_eeprom,\n\t.get_ringparam\t\t= kni_get_ringparam,\n\t.set_ringparam\t\t= kni_set_ringparam,\n\t.get_pauseparam\t\t= kni_get_pauseparam,\n\t.set_pauseparam\t\t= kni_set_pauseparam,\n\t.get_msglevel\t\t= kni_get_msglevel,\n\t.set_msglevel\t\t= kni_set_msglevel,\n\t.get_strings\t\t= kni_get_strings,\n\t.get_sset_count\t\t= kni_get_sset_count,\n\t.get_ethtool_stats = kni_get_ethtool_stats,\n};\n\nvoid\nkni_set_ethtool_ops(struct net_device *netdev)\n{\n\tnetdev->ethtool_ops = &kni_ethtool_ops;\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/kni_fifo.h", "content": "/*-\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n */\n\n#ifndef _KNI_FIFO_H_\n#define _KNI_FIFO_H_\n\n#include \n\n/**\n * Adds num elements into the fifo. Return the number actually written\n */\nstatic inline unsigned\nkni_fifo_put(struct rte_kni_fifo *fifo, void **data, unsigned num)\n{\n\tunsigned i = 0;\n\tunsigned fifo_write = fifo->write;\n\tunsigned fifo_read = fifo->read;\n\tunsigned new_write = fifo_write;\n\n\tfor (i = 0; i < num; i++) {\n\t\tnew_write = (new_write + 1) & (fifo->len - 1);\n\n\t\tif (new_write == fifo_read)\n\t\t\tbreak;\n\t\tfifo->buffer[fifo_write] = data[i];\n\t\tfifo_write = new_write;\n\t}\n\tfifo->write = fifo_write;\n\n\treturn i;\n}\n\n/**\n * Get up to num elements from the fifo. Return the number actully read\n */\nstatic inline unsigned\nkni_fifo_get(struct rte_kni_fifo *fifo, void **data, unsigned num)\n{\n\tunsigned i = 0;\n\tunsigned new_read = fifo->read;\n\tunsigned fifo_write = fifo->write;\n\n\tfor (i = 0; i < num; i++) {\n\t\tif (new_read == fifo_write)\n\t\t\tbreak;\n\n\t\tdata[i] = fifo->buffer[new_read];\n\t\tnew_read = (new_read + 1) & (fifo->len - 1);\n\t}\n\tfifo->read = new_read;\n\n\treturn i;\n}\n\n/**\n * Get the num of elements in the fifo\n */\nstatic inline unsigned\nkni_fifo_count(struct rte_kni_fifo *fifo)\n{\n\treturn (fifo->len + fifo->write - fifo->read) & ( fifo->len - 1);\n}\n\n/**\n * Get the num of available elements in the fifo\n */\nstatic inline unsigned\nkni_fifo_free_count(struct rte_kni_fifo *fifo)\n{\n\treturn (fifo->read - fifo->write - 1) & (fifo->len - 1);\n}\n\n#ifdef RTE_KNI_VHOST\n/**\n * Initializes the kni fifo structure\n */\nstatic inline void\nkni_fifo_init(struct rte_kni_fifo *fifo, unsigned size)\n{\n\tfifo->write = 0;\n\tfifo->read = 0;\n\tfifo->len = size;\n\tfifo->elem_size = sizeof(void *);\n}\n#endif\n\n#endif /* _KNI_FIFO_H_ */\n" }, { "path": "lib/librte_eal/linuxapp/kni/kni_misc.c", "content": "/*-\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \"kni_dev.h\"\n#include \n\nMODULE_LICENSE(\"Dual BSD/GPL\");\nMODULE_AUTHOR(\"Intel Corporation\");\nMODULE_DESCRIPTION(\"Kernel Module for managing kni devices\");\n\n#define KNI_RX_LOOP_NUM 1000\n\n#define KNI_MAX_DEVICES 32\n\nextern void kni_net_rx(struct kni_dev *kni);\nextern void kni_net_init(struct net_device *dev);\nextern void kni_net_config_lo_mode(char *lo_str);\nextern void kni_net_poll_resp(struct kni_dev *kni);\nextern void kni_set_ethtool_ops(struct net_device *netdev);\n\nextern int ixgbe_kni_probe(struct pci_dev *pdev, struct net_device **lad_dev);\nextern void ixgbe_kni_remove(struct pci_dev *pdev);\nextern int igb_kni_probe(struct pci_dev *pdev, struct net_device **lad_dev);\nextern void igb_kni_remove(struct pci_dev *pdev);\n\nstatic int kni_open(struct inode *inode, struct file *file);\nstatic int kni_release(struct inode *inode, struct file *file);\nstatic int kni_ioctl(struct inode *inode, unsigned int ioctl_num,\n\t\t\t\t\tunsigned long ioctl_param);\nstatic int kni_compat_ioctl(struct inode *inode, unsigned int ioctl_num,\n\t\t\t\t\t\tunsigned long ioctl_param);\nstatic int kni_dev_remove(struct kni_dev *dev);\n\nstatic int __init kni_parse_kthread_mode(void);\n\n/* KNI processing for single kernel thread mode */\nstatic int kni_thread_single(void *unused);\n/* KNI processing for multiple kernel thread mode */\nstatic int kni_thread_multiple(void *param);\n\nstatic struct file_operations kni_fops = {\n\t.owner = THIS_MODULE,\n\t.open = kni_open,\n\t.release = kni_release,\n\t.unlocked_ioctl = (void *)kni_ioctl,\n\t.compat_ioctl = (void *)kni_compat_ioctl,\n};\n\nstatic struct miscdevice kni_misc = {\n\t.minor = MISC_DYNAMIC_MINOR,\n\t.name = KNI_DEVICE,\n\t.fops = &kni_fops,\n};\n\n/* loopback mode */\nstatic char *lo_mode = NULL;\n\n/* Kernel thread mode */\nstatic char *kthread_mode = NULL;\nstatic unsigned multiple_kthread_on = 0;\n\n#define KNI_DEV_IN_USE_BIT_NUM 0 /* Bit number for device in use */\n\nstatic volatile unsigned long device_in_use; /* device in use flag */\nstatic struct task_struct *kni_kthread;\n\n/* kni list lock */\nstatic DECLARE_RWSEM(kni_list_lock);\n\n/* kni list */\nstatic struct list_head kni_list_head = LIST_HEAD_INIT(kni_list_head);\n\nstatic int __init\nkni_init(void)\n{\n\tKNI_PRINT(\"######## DPDK kni module loading ########\\n\");\n\n\tif (kni_parse_kthread_mode() < 0) {\n\t\tKNI_ERR(\"Invalid parameter for kthread_mode\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (misc_register(&kni_misc) != 0) {\n\t\tKNI_ERR(\"Misc registration failed\\n\");\n\t\treturn -EPERM;\n\t}\n\n\t/* Clear the bit of device in use */\n\tclear_bit(KNI_DEV_IN_USE_BIT_NUM, &device_in_use);\n\n\t/* Configure the lo mode according to the input parameter */\n\tkni_net_config_lo_mode(lo_mode);\n\n\tKNI_PRINT(\"######## DPDK kni module loaded ########\\n\");\n\n\treturn 0;\n}\n\nstatic void __exit\nkni_exit(void)\n{\n\tmisc_deregister(&kni_misc);\n\tKNI_PRINT(\"####### DPDK kni module unloaded #######\\n\");\n}\n\nstatic int __init\nkni_parse_kthread_mode(void)\n{\n\tif (!kthread_mode)\n\t\treturn 0;\n\n\tif (strcmp(kthread_mode, \"single\") == 0)\n\t\treturn 0;\n\telse if (strcmp(kthread_mode, \"multiple\") == 0)\n\t\tmultiple_kthread_on = 1;\n\telse\n\t\treturn -1;\n\n\treturn 0;\n}\n\nstatic int\nkni_open(struct inode *inode, struct file *file)\n{\n\t/* kni device can be opened by one user only, test and set bit */\n\tif (test_and_set_bit(KNI_DEV_IN_USE_BIT_NUM, &device_in_use))\n\t\treturn -EBUSY;\n\n\t/* Create kernel thread for single mode */\n\tif (multiple_kthread_on == 0) {\n\t\tKNI_PRINT(\"Single kernel thread for all KNI devices\\n\");\n\t\t/* Create kernel thread for RX */\n\t\tkni_kthread = kthread_run(kni_thread_single, NULL,\n\t\t\t\t\t\t\"kni_single\");\n\t\tif (IS_ERR(kni_kthread)) {\n\t\t\tKNI_ERR(\"Unable to create kernel threaed\\n\");\n\t\t\treturn PTR_ERR(kni_kthread);\n\t\t}\n\t} else\n\t\tKNI_PRINT(\"Multiple kernel thread mode enabled\\n\");\n\n\tKNI_PRINT(\"/dev/kni opened\\n\");\n\n\treturn 0;\n}\n\nstatic int\nkni_release(struct inode *inode, struct file *file)\n{\n\tstruct kni_dev *dev, *n;\n\n\t/* Stop kernel thread for single mode */\n\tif (multiple_kthread_on == 0) {\n\t\t/* Stop kernel thread */\n\t\tkthread_stop(kni_kthread);\n\t\tkni_kthread = NULL;\n\t}\n\n\tdown_write(&kni_list_lock);\n\tlist_for_each_entry_safe(dev, n, &kni_list_head, list) {\n\t\t/* Stop kernel thread for multiple mode */\n\t\tif (multiple_kthread_on && dev->pthread != NULL) {\n\t\t\tkthread_stop(dev->pthread);\n\t\t\tdev->pthread = NULL;\n\t\t}\n\n#ifdef RTE_KNI_VHOST\n\t\tkni_vhost_backend_release(dev);\n#endif\n\t\tkni_dev_remove(dev);\n\t\tlist_del(&dev->list);\n\t}\n\tup_write(&kni_list_lock);\n\n\t/* Clear the bit of device in use */\n\tclear_bit(KNI_DEV_IN_USE_BIT_NUM, &device_in_use);\n\n\tKNI_PRINT(\"/dev/kni closed\\n\");\n\n\treturn 0;\n}\n\nstatic int\nkni_thread_single(void *unused)\n{\n\tint j;\n\tstruct kni_dev *dev;\n\n\twhile (!kthread_should_stop()) {\n\t\tdown_read(&kni_list_lock);\n\t\tfor (j = 0; j < KNI_RX_LOOP_NUM; j++) {\n\t\t\tlist_for_each_entry(dev, &kni_list_head, list) {\n#ifdef RTE_KNI_VHOST\n\t\t\t\tkni_chk_vhost_rx(dev);\n#else\n\t\t\t\tkni_net_rx(dev);\n#endif\n\t\t\t\tkni_net_poll_resp(dev);\n\t\t\t}\n\t\t}\n\t\tup_read(&kni_list_lock);\n#ifdef RTE_KNI_PREEMPT_DEFAULT\n\t\t/* reschedule out for a while */\n\t\tschedule_timeout_interruptible(usecs_to_jiffies( \\\n\t\t\t\tKNI_KTHREAD_RESCHEDULE_INTERVAL));\n#endif\n\t}\n\n\treturn 0;\n}\n\nstatic int\nkni_thread_multiple(void *param)\n{\n\tint j;\n\tstruct kni_dev *dev = (struct kni_dev *)param;\n\n\twhile (!kthread_should_stop()) {\n\t\tfor (j = 0; j < KNI_RX_LOOP_NUM; j++) {\n#ifdef RTE_KNI_VHOST\n\t\t\tkni_chk_vhost_rx(dev);\n#else\n\t\t\tkni_net_rx(dev);\n#endif\n\t\t\tkni_net_poll_resp(dev);\n\t\t}\n#ifdef RTE_KNI_PREEMPT_DEFAULT\n\t\tschedule_timeout_interruptible(usecs_to_jiffies( \\\n\t\t\t\tKNI_KTHREAD_RESCHEDULE_INTERVAL));\n#endif\n\t}\n\n\treturn 0;\n}\n\nstatic int\nkni_dev_remove(struct kni_dev *dev)\n{\n\tif (!dev)\n\t\treturn -ENODEV;\n\n\tswitch (dev->device_id) {\n\t#define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) case (dev):\n\t#include \n\t\tigb_kni_remove(dev->pci_dev);\n\t\tbreak;\n\t#define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) case (dev):\n\t#include \n\t\tixgbe_kni_remove(dev->pci_dev);\n\t\tbreak;\n\tdefault:\n\t\tbreak;\n\t}\n\n\tif (dev->net_dev) {\n\t\tunregister_netdev(dev->net_dev);\n\t\tfree_netdev(dev->net_dev);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nkni_check_param(struct kni_dev *kni, struct rte_kni_device_info *dev)\n{\n\tif (!kni || !dev)\n\t\treturn -1;\n\n\t/* Check if network name has been used */\n\tif (!strncmp(kni->name, dev->name, RTE_KNI_NAMESIZE)) {\n\t\tKNI_ERR(\"KNI name %s duplicated\\n\", dev->name);\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nkni_ioctl_create(unsigned int ioctl_num, unsigned long ioctl_param)\n{\n\tint ret;\n\tstruct rte_kni_device_info dev_info;\n\tstruct pci_dev *pci = NULL;\n\tstruct pci_dev *found_pci = NULL;\n\tstruct net_device *net_dev = NULL;\n\tstruct net_device *lad_dev = NULL;\n\tstruct kni_dev *kni, *dev, *n;\n\tstruct net *net;\n\n\tprintk(KERN_INFO \"KNI: Creating kni...\\n\");\n\t/* Check the buffer size, to avoid warning */\n\tif (_IOC_SIZE(ioctl_num) > sizeof(dev_info))\n\t\treturn -EINVAL;\n\n\t/* Copy kni info from user space */\n\tret = copy_from_user(&dev_info, (void *)ioctl_param, sizeof(dev_info));\n\tif (ret) {\n\t\tKNI_ERR(\"copy_from_user in kni_ioctl_create\");\n\t\treturn -EIO;\n\t}\n\n\t/**\n\t * Check if the cpu core id is valid for binding,\n\t * for multiple kernel thread mode.\n\t */\n\tif (multiple_kthread_on && dev_info.force_bind &&\n\t\t\t\t!cpu_online(dev_info.core_id)) {\n\t\tKNI_ERR(\"cpu %u is not online\\n\", dev_info.core_id);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Check if it has been created */\n\tdown_read(&kni_list_lock);\n\tlist_for_each_entry_safe(dev, n, &kni_list_head, list) {\n\t\tif (kni_check_param(dev, &dev_info) < 0) {\n\t\t\tup_read(&kni_list_lock);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\tup_read(&kni_list_lock);\n\n\tnet_dev = alloc_netdev(sizeof(struct kni_dev), dev_info.name,\n#ifdef NET_NAME_UNKNOWN\n\t\t\t\t\t\t\tNET_NAME_UNKNOWN,\n#endif\n\t\t\t\t\t\t\tkni_net_init);\n\tif (net_dev == NULL) {\n\t\tKNI_ERR(\"error allocating device \\\"%s\\\"\\n\", dev_info.name);\n\t\treturn -EBUSY;\n\t}\n\n\tnet = get_net_ns_by_pid(task_pid_vnr(current));\n\tif (IS_ERR(net)) {\n\t\tfree_netdev(net_dev);\n\t\treturn PTR_ERR(net);\n\t}\n\tdev_net_set(net_dev, net);\n\tput_net(net);\n\n\tkni = netdev_priv(net_dev);\n\n\tkni->net_dev = net_dev;\n\tkni->group_id = dev_info.group_id;\n\tkni->core_id = dev_info.core_id;\n\tstrncpy(kni->name, dev_info.name, RTE_KNI_NAMESIZE);\n\n\t/* Translate user space info into kernel space info */\n\tkni->tx_q = phys_to_virt(dev_info.tx_phys);\n\tkni->rx_q = phys_to_virt(dev_info.rx_phys);\n\tkni->alloc_q = phys_to_virt(dev_info.alloc_phys);\n\tkni->free_q = phys_to_virt(dev_info.free_phys);\n\n\tkni->req_q = phys_to_virt(dev_info.req_phys);\n\tkni->resp_q = phys_to_virt(dev_info.resp_phys);\n\tkni->sync_va = dev_info.sync_va;\n\tkni->sync_kva = phys_to_virt(dev_info.sync_phys);\n\n\tkni->mbuf_kva = phys_to_virt(dev_info.mbuf_phys);\n\tkni->mbuf_va = dev_info.mbuf_va;\n\n#ifdef RTE_KNI_VHOST\n\tkni->vhost_queue = NULL;\n\tkni->vq_status = BE_STOP;\n#endif\n\tkni->mbuf_size = dev_info.mbuf_size;\n\n\tKNI_PRINT(\"tx_phys: 0x%016llx, tx_q addr: 0x%p\\n\",\n\t\t(unsigned long long) dev_info.tx_phys, kni->tx_q);\n\tKNI_PRINT(\"rx_phys: 0x%016llx, rx_q addr: 0x%p\\n\",\n\t\t(unsigned long long) dev_info.rx_phys, kni->rx_q);\n\tKNI_PRINT(\"alloc_phys: 0x%016llx, alloc_q addr: 0x%p\\n\",\n\t\t(unsigned long long) dev_info.alloc_phys, kni->alloc_q);\n\tKNI_PRINT(\"free_phys: 0x%016llx, free_q addr: 0x%p\\n\",\n\t\t(unsigned long long) dev_info.free_phys, kni->free_q);\n\tKNI_PRINT(\"req_phys: 0x%016llx, req_q addr: 0x%p\\n\",\n\t\t(unsigned long long) dev_info.req_phys, kni->req_q);\n\tKNI_PRINT(\"resp_phys: 0x%016llx, resp_q addr: 0x%p\\n\",\n\t\t(unsigned long long) dev_info.resp_phys, kni->resp_q);\n\tKNI_PRINT(\"mbuf_phys: 0x%016llx, mbuf_kva: 0x%p\\n\",\n\t\t(unsigned long long) dev_info.mbuf_phys, kni->mbuf_kva);\n\tKNI_PRINT(\"mbuf_va: 0x%p\\n\", dev_info.mbuf_va);\n\tKNI_PRINT(\"mbuf_size: %u\\n\", kni->mbuf_size);\n\n\tKNI_DBG(\"PCI: %02x:%02x.%02x %04x:%04x\\n\",\n\t\t\t\t\tdev_info.bus,\n\t\t\t\t\tdev_info.devid,\n\t\t\t\t\tdev_info.function,\n\t\t\t\t\tdev_info.vendor_id,\n\t\t\t\t\tdev_info.device_id);\n\n\tpci = pci_get_device(dev_info.vendor_id, dev_info.device_id, NULL);\n\n\t/* Support Ethtool */\n\twhile (pci) {\n\t\tKNI_PRINT(\"pci_bus: %02x:%02x:%02x \\n\",\n\t\t\t\t\tpci->bus->number,\n\t\t\t\t\tPCI_SLOT(pci->devfn),\n\t\t\t\t\tPCI_FUNC(pci->devfn));\n\n\t\tif ((pci->bus->number == dev_info.bus) &&\n\t\t\t(PCI_SLOT(pci->devfn) == dev_info.devid) &&\n\t\t\t(PCI_FUNC(pci->devfn) == dev_info.function)) {\n\t\t\tfound_pci = pci;\n\t\t\tswitch (dev_info.device_id) {\n\t\t\t#define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) case (dev):\n\t\t\t#include \n\t\t\t\tret = igb_kni_probe(found_pci, &lad_dev);\n\t\t\t\tbreak;\n\t\t\t#define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) \\\n\t\t\t\t\t\t\tcase (dev):\n\t\t\t#include \n\t\t\t\tret = ixgbe_kni_probe(found_pci, &lad_dev);\n\t\t\t\tbreak;\n\t\t\tdefault:\n\t\t\t\tret = -1;\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tKNI_DBG(\"PCI found: pci=0x%p, lad_dev=0x%p\\n\",\n\t\t\t\t\t\t\tpci, lad_dev);\n\t\t\tif (ret == 0) {\n\t\t\t\tkni->lad_dev = lad_dev;\n\t\t\t\tkni_set_ethtool_ops(kni->net_dev);\n\t\t\t} else {\n\t\t\t\tKNI_ERR(\"Device not supported by ethtool\");\n\t\t\t\tkni->lad_dev = NULL;\n\t\t\t}\n\n\t\t\tkni->pci_dev = found_pci;\n\t\t\tkni->device_id = dev_info.device_id;\n\t\t\tbreak;\n\t\t}\n\t\tpci = pci_get_device(dev_info.vendor_id,\n\t\t\t\tdev_info.device_id, pci);\n\t}\n\tif (pci)\n\t\tpci_dev_put(pci);\n\n\tret = register_netdev(net_dev);\n\tif (ret) {\n\t\tKNI_ERR(\"error %i registering device \\\"%s\\\"\\n\",\n\t\t\t\t\tret, dev_info.name);\n\t\tkni_dev_remove(kni);\n\t\treturn -ENODEV;\n\t}\n\n#ifdef RTE_KNI_VHOST\n\tkni_vhost_init(kni);\n#endif\n\n\t/**\n\t * Create a new kernel thread for multiple mode, set its core affinity,\n\t * and finally wake it up.\n\t */\n\tif (multiple_kthread_on) {\n\t\tkni->pthread = kthread_create(kni_thread_multiple,\n\t\t\t\t\t (void *)kni,\n\t\t\t\t\t \"kni_%s\", kni->name);\n\t\tif (IS_ERR(kni->pthread)) {\n\t\t\tkni_dev_remove(kni);\n\t\t\treturn -ECANCELED;\n\t\t}\n\t\tif (dev_info.force_bind)\n\t\t\tkthread_bind(kni->pthread, kni->core_id);\n\t\twake_up_process(kni->pthread);\n\t}\n\n\tdown_write(&kni_list_lock);\n\tlist_add(&kni->list, &kni_list_head);\n\tup_write(&kni_list_lock);\n\n\treturn 0;\n}\n\nstatic int\nkni_ioctl_release(unsigned int ioctl_num, unsigned long ioctl_param)\n{\n\tint ret = -EINVAL;\n\tstruct kni_dev *dev, *n;\n\tstruct rte_kni_device_info dev_info;\n\n\tif (_IOC_SIZE(ioctl_num) > sizeof(dev_info))\n\t\t\treturn -EINVAL;\n\n\tret = copy_from_user(&dev_info, (void *)ioctl_param, sizeof(dev_info));\n\tif (ret) {\n\t\tKNI_ERR(\"copy_from_user in kni_ioctl_release\");\n\t\treturn -EIO;\n\t}\n\n\t/* Release the network device according to its name */\n\tif (strlen(dev_info.name) == 0)\n\t\treturn ret;\n\n\tdown_write(&kni_list_lock);\n\tlist_for_each_entry_safe(dev, n, &kni_list_head, list) {\n\t\tif (strncmp(dev->name, dev_info.name, RTE_KNI_NAMESIZE) != 0)\n\t\t\tcontinue;\n\n\t\tif (multiple_kthread_on && dev->pthread != NULL) {\n\t\t\tkthread_stop(dev->pthread);\n\t\t\tdev->pthread = NULL;\n\t\t}\n\n#ifdef RTE_KNI_VHOST\n\t\tkni_vhost_backend_release(dev);\n#endif\n\t\tkni_dev_remove(dev);\n\t\tlist_del(&dev->list);\n\t\tret = 0;\n\t\tbreak;\n\t}\n\tup_write(&kni_list_lock);\n\tprintk(KERN_INFO \"KNI: %s release kni named %s\\n\",\n\t\t(ret == 0 ? \"Successfully\" : \"Unsuccessfully\"), dev_info.name);\n\n\treturn ret;\n}\n\nstatic int\nkni_ioctl(struct inode *inode,\n\tunsigned int ioctl_num,\n\tunsigned long ioctl_param)\n{\n\tint ret = -EINVAL;\n\n\tKNI_DBG(\"IOCTL num=0x%0x param=0x%0lx \\n\", ioctl_num, ioctl_param);\n\n\t/*\n\t * Switch according to the ioctl called\n\t */\n\tswitch (_IOC_NR(ioctl_num)) {\n\tcase _IOC_NR(RTE_KNI_IOCTL_TEST):\n\t\t/* For test only, not used */\n\t\tbreak;\n\tcase _IOC_NR(RTE_KNI_IOCTL_CREATE):\n\t\tret = kni_ioctl_create(ioctl_num, ioctl_param);\n\t\tbreak;\n\tcase _IOC_NR(RTE_KNI_IOCTL_RELEASE):\n\t\tret = kni_ioctl_release(ioctl_num, ioctl_param);\n\t\tbreak;\n\tdefault:\n\t\tKNI_DBG(\"IOCTL default \\n\");\n\t\tbreak;\n\t}\n\n\treturn ret;\n}\n\nstatic int\nkni_compat_ioctl(struct inode *inode,\n\t\tunsigned int ioctl_num,\n\t\tunsigned long ioctl_param)\n{\n\t/* 32 bits app on 64 bits OS to be supported later */\n\tKNI_PRINT(\"Not implemented.\\n\");\n\n\treturn -EINVAL;\n}\n\nmodule_init(kni_init);\nmodule_exit(kni_exit);\n\nmodule_param(lo_mode, charp, S_IRUGO | S_IWUSR);\nMODULE_PARM_DESC(lo_mode,\n\"KNI loopback mode (default=lo_mode_none):\\n\"\n\" lo_mode_none Kernel loopback disabled\\n\"\n\" lo_mode_fifo Enable kernel loopback with fifo\\n\"\n\" lo_mode_fifo_skb Enable kernel loopback with fifo and skb buffer\\n\"\n\"\\n\"\n);\n\nmodule_param(kthread_mode, charp, S_IRUGO);\nMODULE_PARM_DESC(kthread_mode,\n\"Kernel thread mode (default=single):\\n\"\n\" single Single kernel thread mode enabled.\\n\"\n\" multiple Multiple kernel thread mode enabled.\\n\"\n\"\\n\"\n);\n" }, { "path": "lib/librte_eal/linuxapp/kni/kni_net.c", "content": "/*-\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n */\n\n/*\n * This code is inspired from the book \"Linux Device Drivers\" by\n * Alessandro Rubini and Jonathan Corbet, published by O'Reilly & Associates\n */\n\n#include \n#include \n#include \n#include \n#include /* eth_type_trans */\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \"kni_dev.h\"\n\n#define WD_TIMEOUT 5 /*jiffies */\n\n#define MBUF_BURST_SZ 32\n\n#define KNI_WAIT_RESPONSE_TIMEOUT 300 /* 3 seconds */\n\n/* typedef for rx function */\ntypedef void (*kni_net_rx_t)(struct kni_dev *kni);\n\nstatic int kni_net_tx(struct sk_buff *skb, struct net_device *dev);\nstatic void kni_net_rx_normal(struct kni_dev *kni);\nstatic void kni_net_rx_lo_fifo(struct kni_dev *kni);\nstatic void kni_net_rx_lo_fifo_skb(struct kni_dev *kni);\nstatic int kni_net_process_request(struct kni_dev *kni,\n\t\t\tstruct rte_kni_request *req);\n\n/* kni rx function pointer, with default to normal rx */\nstatic kni_net_rx_t kni_net_rx_func = kni_net_rx_normal;\n\n/*\n * Open and close\n */\nstatic int\nkni_net_open(struct net_device *dev)\n{\n\tint ret;\n\tstruct rte_kni_request req;\n\tstruct kni_dev *kni = netdev_priv(dev);\n\n\tif (kni->lad_dev)\n\t\tmemcpy(dev->dev_addr, kni->lad_dev->dev_addr, ETH_ALEN);\n\telse\n\t\t/*\n\t\t * Generate random mac address. eth_random_addr() is the newer\n\t\t * version of generating mac address in linux kernel.\n\t\t */\n\t\trandom_ether_addr(dev->dev_addr);\n\n\tnetif_start_queue(dev);\n\n\tmemset(&req, 0, sizeof(req));\n\treq.req_id = RTE_KNI_REQ_CFG_NETWORK_IF;\n\n\t/* Setting if_up to non-zero means up */\n\treq.if_up = 1;\n\tret = kni_net_process_request(kni, &req);\n\n\treturn (ret == 0) ? req.result : ret;\n}\n\nstatic int\nkni_net_release(struct net_device *dev)\n{\n\tint ret;\n\tstruct rte_kni_request req;\n\tstruct kni_dev *kni = netdev_priv(dev);\n\n\tnetif_stop_queue(dev); /* can't transmit any more */\n\n\tmemset(&req, 0, sizeof(req));\n\treq.req_id = RTE_KNI_REQ_CFG_NETWORK_IF;\n\n\t/* Setting if_up to 0 means down */\n\treq.if_up = 0;\n\tret = kni_net_process_request(kni, &req);\n\n\treturn (ret == 0) ? req.result : ret;\n}\n\n/*\n * Configuration changes (passed on by ifconfig)\n */\nstatic int\nkni_net_config(struct net_device *dev, struct ifmap *map)\n{\n\tif (dev->flags & IFF_UP) /* can't act on a running interface */\n\t\treturn -EBUSY;\n\n\t/* ignore other fields */\n\treturn 0;\n}\n\n/*\n * RX: normal working mode\n */\nstatic void\nkni_net_rx_normal(struct kni_dev *kni)\n{\n\tunsigned ret;\n\tuint32_t len;\n\tunsigned i, num_rx, num_fq;\n\tstruct rte_kni_mbuf *kva;\n\tstruct rte_kni_mbuf *va[MBUF_BURST_SZ];\n\tvoid * data_kva;\n\n\tstruct sk_buff *skb;\n\tstruct net_device *dev = kni->net_dev;\n\n\t/* Get the number of free entries in free_q */\n\tnum_fq = kni_fifo_free_count(kni->free_q);\n\tif (num_fq == 0) {\n\t\t/* No room on the free_q, bail out */\n\t\treturn;\n\t}\n\n\t/* Calculate the number of entries to dequeue from rx_q */\n\tnum_rx = min(num_fq, (unsigned)MBUF_BURST_SZ);\n\n\t/* Burst dequeue from rx_q */\n\tnum_rx = kni_fifo_get(kni->rx_q, (void **)va, num_rx);\n\tif (num_rx == 0)\n\t\treturn;\n\n\t/* Transfer received packets to netif */\n\tfor (i = 0; i < num_rx; i++) {\n\t\tkva = (void *)va[i] - kni->mbuf_va + kni->mbuf_kva;\n\t\tlen = kva->data_len;\n\t\tdata_kva = kva->buf_addr + kva->data_off - kni->mbuf_va\n\t\t\t\t+ kni->mbuf_kva;\n\n\t\tskb = dev_alloc_skb(len + 2);\n\t\tif (!skb) {\n\t\t\tKNI_ERR(\"Out of mem, dropping pkts\\n\");\n\t\t\t/* Update statistics */\n\t\t\tkni->stats.rx_dropped++;\n\t\t}\n\t\telse {\n\t\t\t/* Align IP on 16B boundary */\n\t\t\tskb_reserve(skb, 2);\n\t\t\tmemcpy(skb_put(skb, len), data_kva, len);\n\t\t\tskb->dev = dev;\n\t\t\tskb->protocol = eth_type_trans(skb, dev);\n\t\t\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n\n\t\t\t/* Call netif interface */\n\t\t\tnetif_rx(skb);\n\n\t\t\t/* Update statistics */\n\t\t\tkni->stats.rx_bytes += len;\n\t\t\tkni->stats.rx_packets++;\n\t\t}\n\t}\n\n\t/* Burst enqueue mbufs into free_q */\n\tret = kni_fifo_put(kni->free_q, (void **)va, num_rx);\n\tif (ret != num_rx)\n\t\t/* Failing should not happen */\n\t\tKNI_ERR(\"Fail to enqueue entries into free_q\\n\");\n}\n\n/*\n * RX: loopback with enqueue/dequeue fifos.\n */\nstatic void\nkni_net_rx_lo_fifo(struct kni_dev *kni)\n{\n\tunsigned ret;\n\tuint32_t len;\n\tunsigned i, num, num_rq, num_tq, num_aq, num_fq;\n\tstruct rte_kni_mbuf *kva;\n\tstruct rte_kni_mbuf *va[MBUF_BURST_SZ];\n\tvoid * data_kva;\n\n\tstruct rte_kni_mbuf *alloc_kva;\n\tstruct rte_kni_mbuf *alloc_va[MBUF_BURST_SZ];\n\tvoid *alloc_data_kva;\n\n\t/* Get the number of entries in rx_q */\n\tnum_rq = kni_fifo_count(kni->rx_q);\n\n\t/* Get the number of free entrie in tx_q */\n\tnum_tq = kni_fifo_free_count(kni->tx_q);\n\n\t/* Get the number of entries in alloc_q */\n\tnum_aq = kni_fifo_count(kni->alloc_q);\n\n\t/* Get the number of free entries in free_q */\n\tnum_fq = kni_fifo_free_count(kni->free_q);\n\n\t/* Calculate the number of entries to be dequeued from rx_q */\n\tnum = min(num_rq, num_tq);\n\tnum = min(num, num_aq);\n\tnum = min(num, num_fq);\n\tnum = min(num, (unsigned)MBUF_BURST_SZ);\n\n\t/* Return if no entry to dequeue from rx_q */\n\tif (num == 0)\n\t\treturn;\n\n\t/* Burst dequeue from rx_q */\n\tret = kni_fifo_get(kni->rx_q, (void **)va, num);\n\tif (ret == 0)\n\t\treturn; /* Failing should not happen */\n\n\t/* Dequeue entries from alloc_q */\n\tret = kni_fifo_get(kni->alloc_q, (void **)alloc_va, num);\n\tif (ret) {\n\t\tnum = ret;\n\t\t/* Copy mbufs */\n\t\tfor (i = 0; i < num; i++) {\n\t\t\tkva = (void *)va[i] - kni->mbuf_va + kni->mbuf_kva;\n\t\t\tlen = kva->pkt_len;\n\t\t\tdata_kva = kva->buf_addr + kva->data_off -\n\t\t\t\t\tkni->mbuf_va + kni->mbuf_kva;\n\n\t\t\talloc_kva = (void *)alloc_va[i] - kni->mbuf_va +\n\t\t\t\t\t\t\tkni->mbuf_kva;\n\t\t\talloc_data_kva = alloc_kva->buf_addr +\n\t\t\t\t\talloc_kva->data_off - kni->mbuf_va +\n\t\t\t\t\t\t\tkni->mbuf_kva;\n\t\t\tmemcpy(alloc_data_kva, data_kva, len);\n\t\t\talloc_kva->pkt_len = len;\n\t\t\talloc_kva->data_len = len;\n\n\t\t\tkni->stats.tx_bytes += len;\n\t\t\tkni->stats.rx_bytes += len;\n\t\t}\n\n\t\t/* Burst enqueue mbufs into tx_q */\n\t\tret = kni_fifo_put(kni->tx_q, (void **)alloc_va, num);\n\t\tif (ret != num)\n\t\t\t/* Failing should not happen */\n\t\t\tKNI_ERR(\"Fail to enqueue mbufs into tx_q\\n\");\n\t}\n\n\t/* Burst enqueue mbufs into free_q */\n\tret = kni_fifo_put(kni->free_q, (void **)va, num);\n\tif (ret != num)\n\t\t/* Failing should not happen */\n\t\tKNI_ERR(\"Fail to enqueue mbufs into free_q\\n\");\n\n\t/**\n\t * Update statistic, and enqueue/dequeue failure is impossible,\n\t * as all queues are checked at first.\n\t */\n\tkni->stats.tx_packets += num;\n\tkni->stats.rx_packets += num;\n}\n\n/*\n * RX: loopback with enqueue/dequeue fifos and sk buffer copies.\n */\nstatic void\nkni_net_rx_lo_fifo_skb(struct kni_dev *kni)\n{\n\tunsigned ret;\n\tuint32_t len;\n\tunsigned i, num_rq, num_fq, num;\n\tstruct rte_kni_mbuf *kva;\n\tstruct rte_kni_mbuf *va[MBUF_BURST_SZ];\n\tvoid * data_kva;\n\n\tstruct sk_buff *skb;\n\tstruct net_device *dev = kni->net_dev;\n\n\t/* Get the number of entries in rx_q */\n\tnum_rq = kni_fifo_count(kni->rx_q);\n\n\t/* Get the number of free entries in free_q */\n\tnum_fq = kni_fifo_free_count(kni->free_q);\n\n\t/* Calculate the number of entries to dequeue from rx_q */\n\tnum = min(num_rq, num_fq);\n\tnum = min(num, (unsigned)MBUF_BURST_SZ);\n\n\t/* Return if no entry to dequeue from rx_q */\n\tif (num == 0)\n\t\treturn;\n\n\t/* Burst dequeue mbufs from rx_q */\n\tret = kni_fifo_get(kni->rx_q, (void **)va, num);\n\tif (ret == 0)\n\t\treturn;\n\n\t/* Copy mbufs to sk buffer and then call tx interface */\n\tfor (i = 0; i < num; i++) {\n\t\tkva = (void *)va[i] - kni->mbuf_va + kni->mbuf_kva;\n\t\tlen = kva->data_len;\n\t\tdata_kva = kva->buf_addr + kva->data_off - kni->mbuf_va +\n\t\t\t\tkni->mbuf_kva;\n\n\t\tskb = dev_alloc_skb(len + 2);\n\t\tif (skb == NULL)\n\t\t\tKNI_ERR(\"Out of mem, dropping pkts\\n\");\n\t\telse {\n\t\t\t/* Align IP on 16B boundary */\n\t\t\tskb_reserve(skb, 2);\n\t\t\tmemcpy(skb_put(skb, len), data_kva, len);\n\t\t\tskb->dev = dev;\n\t\t\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n\t\t\tdev_kfree_skb(skb);\n\t\t}\n\n\t\t/* Simulate real usage, allocate/copy skb twice */\n\t\tskb = dev_alloc_skb(len + 2);\n\t\tif (skb == NULL) {\n\t\t\tKNI_ERR(\"Out of mem, dropping pkts\\n\");\n\t\t\tkni->stats.rx_dropped++;\n\t\t}\n\t\telse {\n\t\t\t/* Align IP on 16B boundary */\n\t\t\tskb_reserve(skb, 2);\n\t\t\tmemcpy(skb_put(skb, len), data_kva, len);\n\t\t\tskb->dev = dev;\n\t\t\tskb->ip_summed = CHECKSUM_UNNECESSARY;\n\n\t\t\tkni->stats.rx_bytes += len;\n\t\t\tkni->stats.rx_packets++;\n\n\t\t\t/* call tx interface */\n\t\t\tkni_net_tx(skb, dev);\n\t\t}\n\t}\n\n\t/* enqueue all the mbufs from rx_q into free_q */\n\tret = kni_fifo_put(kni->free_q, (void **)&va, num);\n\tif (ret != num)\n\t\t/* Failing should not happen */\n\t\tKNI_ERR(\"Fail to enqueue mbufs into free_q\\n\");\n}\n\n/* rx interface */\nvoid\nkni_net_rx(struct kni_dev *kni)\n{\n\t/**\n\t * It doesn't need to check if it is NULL pointer,\n\t * as it has a default value\n\t */\n\t(*kni_net_rx_func)(kni);\n}\n\n/*\n * Transmit a packet (called by the kernel)\n */\n#ifdef RTE_KNI_VHOST\nstatic int\nkni_net_tx(struct sk_buff *skb, struct net_device *dev)\n{\n\tstruct kni_dev *kni = netdev_priv(dev);\n\n\tdev_kfree_skb(skb);\n\tkni->stats.tx_dropped++;\n\n\treturn NETDEV_TX_OK;\n}\n#else\nstatic int\nkni_net_tx(struct sk_buff *skb, struct net_device *dev)\n{\n\tint len = 0;\n\tunsigned ret;\n\tstruct kni_dev *kni = netdev_priv(dev);\n\tstruct rte_kni_mbuf *pkt_kva = NULL;\n\tstruct rte_kni_mbuf *pkt_va = NULL;\n\n\tdev->trans_start = jiffies; /* save the timestamp */\n\n\t/* Check if the length of skb is less than mbuf size */\n\tif (skb->len > kni->mbuf_size)\n\t\tgoto drop;\n\n\t/**\n\t * Check if it has at least one free entry in tx_q and\n\t * one entry in alloc_q.\n\t */\n\tif (kni_fifo_free_count(kni->tx_q) == 0 ||\n\t\t\tkni_fifo_count(kni->alloc_q) == 0) {\n\t\t/**\n\t\t * If no free entry in tx_q or no entry in alloc_q,\n\t\t * drops skb and goes out.\n\t\t */\n\t\tgoto drop;\n\t}\n\n\t/* dequeue a mbuf from alloc_q */\n\tret = kni_fifo_get(kni->alloc_q, (void **)&pkt_va, 1);\n\tif (likely(ret == 1)) {\n\t\tvoid *data_kva;\n\n\t\tpkt_kva = (void *)pkt_va - kni->mbuf_va + kni->mbuf_kva;\n\t\tdata_kva = pkt_kva->buf_addr + pkt_kva->data_off - kni->mbuf_va\n\t\t\t\t+ kni->mbuf_kva;\n\n\t\tlen = skb->len;\n\t\tmemcpy(data_kva, skb->data, len);\n\t\tif (unlikely(len < ETH_ZLEN)) {\n\t\t\tmemset(data_kva + len, 0, ETH_ZLEN - len);\n\t\t\tlen = ETH_ZLEN;\n\t\t}\n\t\tpkt_kva->pkt_len = len;\n\t\tpkt_kva->data_len = len;\n\n\t\t/* enqueue mbuf into tx_q */\n\t\tret = kni_fifo_put(kni->tx_q, (void **)&pkt_va, 1);\n\t\tif (unlikely(ret != 1)) {\n\t\t\t/* Failing should not happen */\n\t\t\tKNI_ERR(\"Fail to enqueue mbuf into tx_q\\n\");\n\t\t\tgoto drop;\n\t\t}\n\t} else {\n\t\t/* Failing should not happen */\n\t\tKNI_ERR(\"Fail to dequeue mbuf from alloc_q\\n\");\n\t\tgoto drop;\n\t}\n\n\t/* Free skb and update statistics */\n\tdev_kfree_skb(skb);\n\tkni->stats.tx_bytes += len;\n\tkni->stats.tx_packets++;\n\n\treturn NETDEV_TX_OK;\n\ndrop:\n\t/* Free skb and update statistics */\n\tdev_kfree_skb(skb);\n\tkni->stats.tx_dropped++;\n\n\treturn NETDEV_TX_OK;\n}\n#endif\n\n/*\n * Deal with a transmit timeout.\n */\nstatic void\nkni_net_tx_timeout (struct net_device *dev)\n{\n\tstruct kni_dev *kni = netdev_priv(dev);\n\n\tKNI_DBG(\"Transmit timeout at %ld, latency %ld\\n\", jiffies,\n\t\t\tjiffies - dev->trans_start);\n\n\tkni->stats.tx_errors++;\n\tnetif_wake_queue(dev);\n\treturn;\n}\n\n/*\n * Ioctl commands\n */\nstatic int\nkni_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)\n{\n\tKNI_DBG(\"kni_net_ioctl %d\\n\",\n\t\t((struct kni_dev *)netdev_priv(dev))->group_id);\n\n\treturn 0;\n}\n\nstatic void\nkni_net_set_rx_mode(struct net_device *dev)\n{\n}\n\nstatic int\nkni_net_change_mtu(struct net_device *dev, int new_mtu)\n{\n\tint ret;\n\tstruct rte_kni_request req;\n\tstruct kni_dev *kni = netdev_priv(dev);\n\n\tKNI_DBG(\"kni_net_change_mtu new mtu %d to be set\\n\", new_mtu);\n\n\tmemset(&req, 0, sizeof(req));\n\treq.req_id = RTE_KNI_REQ_CHANGE_MTU;\n\treq.new_mtu = new_mtu;\n\tret = kni_net_process_request(kni, &req);\n\tif (ret == 0 && req.result == 0)\n\t\tdev->mtu = new_mtu;\n\n\treturn (ret == 0) ? req.result : ret;\n}\n\n/*\n * Checks if the user space application provided the resp message\n */\nvoid\nkni_net_poll_resp(struct kni_dev *kni)\n{\n\tif (kni_fifo_count(kni->resp_q))\n\t\twake_up_interruptible(&kni->wq);\n}\n\n/*\n * It can be called to process the request.\n */\nstatic int\nkni_net_process_request(struct kni_dev *kni, struct rte_kni_request *req)\n{\n\tint ret = -1;\n\tvoid *resp_va;\n\tunsigned num;\n\tint ret_val;\n\n\tif (!kni || !req) {\n\t\tKNI_ERR(\"No kni instance or request\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tmutex_lock(&kni->sync_lock);\n\n\t/* Construct data */\n\tmemcpy(kni->sync_kva, req, sizeof(struct rte_kni_request));\n\tnum = kni_fifo_put(kni->req_q, &kni->sync_va, 1);\n\tif (num < 1) {\n\t\tKNI_ERR(\"Cannot send to req_q\\n\");\n\t\tret = -EBUSY;\n\t\tgoto fail;\n\t}\n\n\tret_val = wait_event_interruptible_timeout(kni->wq,\n\t\t\tkni_fifo_count(kni->resp_q), 3 * HZ);\n\tif (signal_pending(current) || ret_val <= 0) {\n\t\tret = -ETIME;\n\t\tgoto fail;\n\t}\n\tnum = kni_fifo_get(kni->resp_q, (void **)&resp_va, 1);\n\tif (num != 1 || resp_va != kni->sync_va) {\n\t\t/* This should never happen */\n\t\tKNI_ERR(\"No data in resp_q\\n\");\n\t\tret = -ENODATA;\n\t\tgoto fail;\n\t}\n\n\tmemcpy(req, kni->sync_kva, sizeof(struct rte_kni_request));\n\tret = 0;\n\nfail:\n\tmutex_unlock(&kni->sync_lock);\n\treturn ret;\n}\n\n/*\n * Return statistics to the caller\n */\nstatic struct net_device_stats *\nkni_net_stats(struct net_device *dev)\n{\n\tstruct kni_dev *kni = netdev_priv(dev);\n\treturn &kni->stats;\n}\n\n/*\n * Fill the eth header\n */\nstatic int\nkni_net_header(struct sk_buff *skb, struct net_device *dev,\n\t\tunsigned short type, const void *daddr,\n\t\tconst void *saddr, unsigned int len)\n{\n\tstruct ethhdr *eth = (struct ethhdr *) skb_push(skb, ETH_HLEN);\n\n\tmemcpy(eth->h_source, saddr ? saddr : dev->dev_addr, dev->addr_len);\n\tmemcpy(eth->h_dest, daddr ? daddr : dev->dev_addr, dev->addr_len);\n\teth->h_proto = htons(type);\n\n\treturn dev->hard_header_len;\n}\n\n\n/*\n * Re-fill the eth header\n */\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))\nstatic int\nkni_net_rebuild_header(struct sk_buff *skb)\n{\n\tstruct net_device *dev = skb->dev;\n\tstruct ethhdr *eth = (struct ethhdr *) skb->data;\n\n\tmemcpy(eth->h_source, dev->dev_addr, dev->addr_len);\n\tmemcpy(eth->h_dest, dev->dev_addr, dev->addr_len);\n\n\treturn 0;\n}\n#endif /* < 4.1.0 */\n\n/**\n * kni_net_set_mac - Change the Ethernet Address of the KNI NIC\n * @netdev: network interface device structure\n * @p: pointer to an address structure\n *\n * Returns 0 on success, negative on failure\n **/\nstatic int kni_net_set_mac(struct net_device *netdev, void *p)\n{\n\tstruct sockaddr *addr = p;\n\tif (!is_valid_ether_addr((unsigned char *)(addr->sa_data)))\n\t\treturn -EADDRNOTAVAIL;\n\tmemcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);\n\treturn 0;\n}\n\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\nstatic int kni_net_change_carrier(struct net_device *dev, bool new_carrier)\n{\n\tif (new_carrier)\n\t\tnetif_carrier_on(dev);\n\telse\n\t\tnetif_carrier_off(dev);\n\treturn 0;\n}\n#endif\n\nstatic const struct header_ops kni_net_header_ops = {\n\t.create = kni_net_header,\n#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 1, 0))\n\t.rebuild = kni_net_rebuild_header,\n#endif /* < 4.1.0 */\n\t.cache = NULL, /* disable caching */\n};\n\nstatic const struct net_device_ops kni_net_netdev_ops = {\n\t.ndo_open = kni_net_open,\n\t.ndo_stop = kni_net_release,\n\t.ndo_set_config = kni_net_config,\n\t.ndo_start_xmit = kni_net_tx,\n\t.ndo_change_mtu = kni_net_change_mtu,\n\t.ndo_do_ioctl = kni_net_ioctl,\n\t.ndo_set_rx_mode = kni_net_set_rx_mode,\n\t.ndo_get_stats = kni_net_stats,\n\t.ndo_tx_timeout = kni_net_tx_timeout,\n\t.ndo_set_mac_address = kni_net_set_mac,\n#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0))\n\t.ndo_change_carrier = kni_net_change_carrier,\n#endif\n};\n\nvoid\nkni_net_init(struct net_device *dev)\n{\n\tstruct kni_dev *kni = netdev_priv(dev);\n\n\tKNI_DBG(\"kni_net_init\\n\");\n\n\tinit_waitqueue_head(&kni->wq);\n\tmutex_init(&kni->sync_lock);\n\n\tether_setup(dev); /* assign some of the fields */\n\tdev->netdev_ops = &kni_net_netdev_ops;\n\tdev->header_ops = &kni_net_header_ops;\n\tdev->watchdog_timeo = WD_TIMEOUT;\n}\n\nvoid\nkni_net_config_lo_mode(char *lo_str)\n{\n\tif (!lo_str) {\n\t\tKNI_PRINT(\"loopback disabled\");\n\t\treturn;\n\t}\n\n\tif (!strcmp(lo_str, \"lo_mode_none\"))\n\t\tKNI_PRINT(\"loopback disabled\");\n\telse if (!strcmp(lo_str, \"lo_mode_fifo\")) {\n\t\tKNI_PRINT(\"loopback mode=lo_mode_fifo enabled\");\n\t\tkni_net_rx_func = kni_net_rx_lo_fifo;\n\t} else if (!strcmp(lo_str, \"lo_mode_fifo_skb\")) {\n\t\tKNI_PRINT(\"loopback mode=lo_mode_fifo_skb enabled\");\n\t\tkni_net_rx_func = kni_net_rx_lo_fifo_skb;\n\t} else\n\t\tKNI_PRINT(\"Incognizant parameter, loopback disabled\");\n}\n" }, { "path": "lib/librte_eal/linuxapp/kni/kni_vhost.c", "content": "/*-\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"compat.h\"\n#include \"kni_dev.h\"\n#include \"kni_fifo.h\"\n\n#define RX_BURST_SZ 4\n\nextern void put_unused_fd(unsigned int fd);\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)\nextern struct file*\nsock_alloc_file(struct socket *sock,\n\t\tint flags, const char *dname);\n\nextern int get_unused_fd_flags(unsigned flags);\n\nextern void fd_install(unsigned int fd, struct file *file);\n\nstatic int kni_sock_map_fd(struct socket *sock)\n{\n\tstruct file *file;\n\tint fd = get_unused_fd_flags(0);\n\tif (fd < 0)\n\t\treturn fd;\n\n\tfile = sock_alloc_file(sock, 0, NULL);\n\tif (IS_ERR(file)) {\n\t\tput_unused_fd(fd);\n\t\treturn PTR_ERR(file);\n\t}\n\tfd_install(fd, file);\n\treturn fd;\n}\n#else\n#define kni_sock_map_fd(s) sock_map_fd(s, 0)\n#endif\n\nstatic struct proto kni_raw_proto = {\n\t.name = \"kni_vhost\",\n\t.owner = THIS_MODULE,\n\t.obj_size = sizeof(struct kni_vhost_queue),\n};\n\nstatic inline int\nkni_vhost_net_tx(struct kni_dev *kni, struct msghdr *m,\n\t\t unsigned offset, unsigned len)\n{\n\tstruct rte_kni_mbuf *pkt_kva = NULL;\n\tstruct rte_kni_mbuf *pkt_va = NULL;\n\tint ret;\n\n\tKNI_DBG_TX(\"tx offset=%d, len=%d, iovlen=%d\\n\",\n#ifdef HAVE_IOV_ITER_MSGHDR\n\t\t offset, len, (int)m->msg_iter.iov->iov_len);\n#else\n\t\t offset, len, (int)m->msg_iov->iov_len);\n#endif\n\n\t/**\n\t * Check if it has at least one free entry in tx_q and\n\t * one entry in alloc_q.\n\t */\n\tif (kni_fifo_free_count(kni->tx_q) == 0 ||\n\t kni_fifo_count(kni->alloc_q) == 0) {\n\t\t/**\n\t\t * If no free entry in tx_q or no entry in alloc_q,\n\t\t * drops skb and goes out.\n\t\t */\n\t\tgoto drop;\n\t}\n\n\t/* dequeue a mbuf from alloc_q */\n\tret = kni_fifo_get(kni->alloc_q, (void **)&pkt_va, 1);\n\tif (likely(ret == 1)) {\n\t\tvoid *data_kva;\n\n\t\tpkt_kva = (void *)pkt_va - kni->mbuf_va + kni->mbuf_kva;\n\t\tdata_kva = pkt_kva->buf_addr + pkt_kva->data_off\n\t\t - kni->mbuf_va + kni->mbuf_kva;\n\n#ifdef HAVE_IOV_ITER_MSGHDR\n\t\tcopy_from_iter(data_kva, len, &m->msg_iter);\n#else\n\t\tmemcpy_fromiovecend(data_kva, m->msg_iov, offset, len);\n#endif\n\n\t\tif (unlikely(len < ETH_ZLEN)) {\n\t\t\tmemset(data_kva + len, 0, ETH_ZLEN - len);\n\t\t\tlen = ETH_ZLEN;\n\t\t}\n\t\tpkt_kva->pkt_len = len;\n\t\tpkt_kva->data_len = len;\n\n\t\t/* enqueue mbuf into tx_q */\n\t\tret = kni_fifo_put(kni->tx_q, (void **)&pkt_va, 1);\n\t\tif (unlikely(ret != 1)) {\n\t\t\t/* Failing should not happen */\n\t\t\tKNI_ERR(\"Fail to enqueue mbuf into tx_q\\n\");\n\t\t\tgoto drop;\n\t\t}\n\t} else {\n\t\t/* Failing should not happen */\n\t\tKNI_ERR(\"Fail to dequeue mbuf from alloc_q\\n\");\n\t\tgoto drop;\n\t}\n\n\t/* update statistics */\n\tkni->stats.tx_bytes += len;\n\tkni->stats.tx_packets++;\n\n\treturn 0;\n\ndrop:\n\t/* update statistics */\n\tkni->stats.tx_dropped++;\n\n\treturn 0;\n}\n\nstatic inline int\nkni_vhost_net_rx(struct kni_dev *kni, struct msghdr *m,\n\t\t unsigned offset, unsigned len)\n{\n\tuint32_t pkt_len;\n\tstruct rte_kni_mbuf *kva;\n\tstruct rte_kni_mbuf *va;\n\tvoid * data_kva;\n\tstruct sk_buff *skb;\n\tstruct kni_vhost_queue *q = kni->vhost_queue;\n\n\tif (unlikely(q == NULL))\n\t\treturn 0;\n\n\t/* ensure at least one entry in free_q */\n\tif (unlikely(kni_fifo_free_count(kni->free_q) == 0))\n\t\treturn 0;\n\n\tskb = skb_dequeue(&q->sk.sk_receive_queue);\n\tif (unlikely(skb == NULL))\n\t\treturn 0;\n\n\tkva = (struct rte_kni_mbuf*)skb->data;\n\n\t/* free skb to cache */\n\tskb->data = NULL;\n\tif (unlikely(1 != kni_fifo_put(q->fifo, (void **)&skb, 1)))\n\t\t/* Failing should not happen */\n\t\tKNI_ERR(\"Fail to enqueue entries into rx cache fifo\\n\");\n\n\tpkt_len = kva->data_len;\n\tif (unlikely(pkt_len > len))\n\t\tgoto drop;\n\n\tKNI_DBG_RX(\"rx offset=%d, len=%d, pkt_len=%d, iovlen=%d\\n\",\n#ifdef HAVE_IOV_ITER_MSGHDR\n\t\t offset, len, pkt_len, (int)m->msg_iter.iov->iov_len);\n#else\n\t\t offset, len, pkt_len, (int)m->msg_iov->iov_len);\n#endif\n\n\tdata_kva = kva->buf_addr + kva->data_off - kni->mbuf_va + kni->mbuf_kva;\n#ifdef HAVE_IOV_ITER_MSGHDR\n\tif (unlikely(copy_to_iter(data_kva, pkt_len, &m->msg_iter)))\n#else\n\tif (unlikely(memcpy_toiovecend(m->msg_iov, data_kva, offset, pkt_len)))\n#endif\n\t\tgoto drop;\n\n\t/* Update statistics */\n\tkni->stats.rx_bytes += pkt_len;\n\tkni->stats.rx_packets++;\n\n\t/* enqueue mbufs into free_q */\n\tva = (void*)kva - kni->mbuf_kva + kni->mbuf_va;\n\tif (unlikely(1 != kni_fifo_put(kni->free_q, (void **)&va, 1)))\n\t\t/* Failing should not happen */\n\t\tKNI_ERR(\"Fail to enqueue entries into free_q\\n\");\n\n\tKNI_DBG_RX(\"receive done %d\\n\", pkt_len);\n\n\treturn pkt_len;\n\ndrop:\n\t/* Update drop statistics */\n\tkni->stats.rx_dropped++;\n\n\treturn 0;\n}\n\nstatic unsigned int\nkni_sock_poll(struct file *file, struct socket *sock, poll_table * wait)\n{\n\tstruct kni_vhost_queue *q =\n\t\tcontainer_of(sock->sk, struct kni_vhost_queue, sk);\n\tstruct kni_dev *kni;\n\tunsigned int mask = 0;\n\n\tif (unlikely(q == NULL || q->kni == NULL))\n\t\treturn POLLERR;\n\n\tkni = q->kni;\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)\n\tKNI_DBG(\"start kni_poll on group %d, wq 0x%16llx\\n\",\n\t\t kni->group_id, (uint64_t)sock->wq);\n#else\n\tKNI_DBG(\"start kni_poll on group %d, wait at 0x%16llx\\n\",\n\t\t kni->group_id, (uint64_t)&sock->wait);\n#endif\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)\n\tpoll_wait(file, &sock->wq->wait, wait);\n#else\n\tpoll_wait(file, &sock->wait, wait);\n#endif\n\n\tif (kni_fifo_count(kni->rx_q) > 0)\n\t\tmask |= POLLIN | POLLRDNORM;\n\n\tif (sock_writeable(&q->sk) ||\n\t (!test_and_set_bit(SOCK_ASYNC_NOSPACE, &q->sock->flags) &&\n\t sock_writeable(&q->sk)))\n\t\tmask |= POLLOUT | POLLWRNORM;\n\n\treturn mask;\n}\n\nstatic inline void\nkni_vhost_enqueue(struct kni_dev *kni, struct kni_vhost_queue *q,\n\t\t struct sk_buff *skb, struct rte_kni_mbuf *va)\n{\n\tstruct rte_kni_mbuf *kva;\n\n\tkva = (void *)(va) - kni->mbuf_va + kni->mbuf_kva;\n\t(skb)->data = (unsigned char*)kva;\n\t(skb)->len = kva->data_len;\n\tskb_queue_tail(&q->sk.sk_receive_queue, skb);\n}\n\nstatic inline void\nkni_vhost_enqueue_burst(struct kni_dev *kni, struct kni_vhost_queue *q,\n\t struct sk_buff **skb, struct rte_kni_mbuf **va)\n{\n\tint i;\n\tfor (i = 0; i < RX_BURST_SZ; skb++, va++, i++)\n\t\tkni_vhost_enqueue(kni, q, *skb, *va);\n}\n\nint\nkni_chk_vhost_rx(struct kni_dev *kni)\n{\n\tstruct kni_vhost_queue *q = kni->vhost_queue;\n\tunsigned nb_in, nb_mbuf, nb_skb;\n\tconst unsigned BURST_MASK = RX_BURST_SZ - 1;\n\tunsigned nb_burst, nb_backlog, i;\n\tstruct sk_buff *skb[RX_BURST_SZ];\n\tstruct rte_kni_mbuf *va[RX_BURST_SZ];\n\n\tif (unlikely(BE_STOP & kni->vq_status)) {\n\t\tkni->vq_status |= BE_FINISH;\n\t\treturn 0;\n\t}\n\n\tif (unlikely(q == NULL))\n\t\treturn 0;\n\n\tnb_skb = kni_fifo_count(q->fifo);\n\tnb_mbuf = kni_fifo_count(kni->rx_q);\n\n\tnb_in = min(nb_mbuf, nb_skb);\n\tnb_in = min(nb_in, (unsigned)RX_BURST_SZ);\n\tnb_burst = (nb_in & ~BURST_MASK);\n\tnb_backlog = (nb_in & BURST_MASK);\n\n\t/* enqueue skb_queue per BURST_SIZE bulk */\n\tif (0 != nb_burst) {\n\t\tif (unlikely(RX_BURST_SZ != kni_fifo_get(\n\t\t\t\t kni->rx_q, (void **)&va,\n\t\t\t\t RX_BURST_SZ)))\n\t\t\tgoto except;\n\n\t\tif (unlikely(RX_BURST_SZ != kni_fifo_get(\n\t\t\t\t q->fifo, (void **)&skb,\n\t\t\t\t RX_BURST_SZ)))\n\t\t\tgoto except;\n\n\t\tkni_vhost_enqueue_burst(kni, q, skb, va);\n\t}\n\n\t/* all leftover, do one by one */\n\tfor (i = 0; i < nb_backlog; ++i) {\n\t\tif (unlikely(1 != kni_fifo_get(\n\t\t\t\t kni->rx_q,(void **)&va, 1)))\n\t\t\tgoto except;\n\n\t\tif (unlikely(1 != kni_fifo_get(\n\t\t\t\t q->fifo, (void **)&skb, 1)))\n\t\t\tgoto except;\n\n\t\tkni_vhost_enqueue(kni, q, *skb, *va);\n\t}\n\n\t/* Ondemand wake up */\n\tif ((nb_in == RX_BURST_SZ) || (nb_skb == 0) ||\n\t ((nb_mbuf < RX_BURST_SZ) && (nb_mbuf != 0))) {\n\t\twake_up_interruptible_poll(sk_sleep(&q->sk),\n\t\t\t\t POLLIN | POLLRDNORM | POLLRDBAND);\n\t\tKNI_DBG_RX(\"RX CHK KICK nb_mbuf %d, nb_skb %d, nb_in %d\\n\",\n\t\t\t nb_mbuf, nb_skb, nb_in);\n\t}\n\n\treturn 0;\n\nexcept:\n\t/* Failing should not happen */\n\tKNI_ERR(\"Fail to enqueue fifo, it shouldn't happen \\n\");\n\tBUG_ON(1);\n\n\treturn 0;\n}\n\nstatic int\n#ifdef HAVE_KIOCB_MSG_PARAM\nkni_sock_sndmsg(struct kiocb *iocb, struct socket *sock,\n\t struct msghdr *m, size_t total_len)\n#else\nkni_sock_sndmsg(struct socket *sock,\n\t struct msghdr *m, size_t total_len)\n#endif /* HAVE_KIOCB_MSG_PARAM */\n{\n\tstruct kni_vhost_queue *q =\n\t\tcontainer_of(sock->sk, struct kni_vhost_queue, sk);\n\tint vnet_hdr_len = 0;\n\tunsigned long len = total_len;\n\n\tif (unlikely(q == NULL || q->kni == NULL))\n\t\treturn 0;\n\n\tKNI_DBG_TX(\"kni_sndmsg len %ld, flags 0x%08x, nb_iov %d\\n\",\n#ifdef HAVE_IOV_ITER_MSGHDR\n\t\t len, q->flags, (int)m->msg_iter.iov->iov_len);\n#else\n\t\t len, q->flags, (int)m->msg_iovlen);\n#endif\n\n#ifdef RTE_KNI_VHOST_VNET_HDR_EN\n\tif (likely(q->flags & IFF_VNET_HDR)) {\n\t\tvnet_hdr_len = q->vnet_hdr_sz;\n\t\tif (unlikely(len < vnet_hdr_len))\n\t\t\treturn -EINVAL;\n\t\tlen -= vnet_hdr_len;\n\t}\n#endif\n\n\tif (unlikely(len < ETH_HLEN + q->vnet_hdr_sz))\n\t\treturn -EINVAL;\n\n\treturn kni_vhost_net_tx(q->kni, m, vnet_hdr_len, len);\n}\n\nstatic int\n#ifdef HAVE_KIOCB_MSG_PARAM\nkni_sock_rcvmsg(struct kiocb *iocb, struct socket *sock,\n\t struct msghdr *m, size_t len, int flags)\n#else\nkni_sock_rcvmsg(struct socket *sock,\n\t struct msghdr *m, size_t len, int flags)\n#endif /* HAVE_KIOCB_MSG_PARAM */\n{\n\tint vnet_hdr_len = 0;\n\tint pkt_len = 0;\n\tstruct kni_vhost_queue *q =\n\t\tcontainer_of(sock->sk, struct kni_vhost_queue, sk);\n\tstatic struct virtio_net_hdr\n\t\t__attribute__ ((unused)) vnet_hdr = {\n\t\t.flags = 0,\n\t\t.gso_type = VIRTIO_NET_HDR_GSO_NONE\n\t};\n\n\tif (unlikely(q == NULL || q->kni == NULL))\n\t\treturn 0;\n\n#ifdef RTE_KNI_VHOST_VNET_HDR_EN\n\tif (likely(q->flags & IFF_VNET_HDR)) {\n\t\tvnet_hdr_len = q->vnet_hdr_sz;\n\t\tif ((len -= vnet_hdr_len) < 0)\n\t\t\treturn -EINVAL;\n\t}\n#endif\n\n\tif (unlikely(0 == (pkt_len = kni_vhost_net_rx(q->kni,\n\t\tm, vnet_hdr_len, len))))\n\t\treturn 0;\n\n#ifdef RTE_KNI_VHOST_VNET_HDR_EN\n\t/* no need to copy hdr when no pkt received */\n#ifdef HAVE_IOV_ITER_MSGHDR\n\tif (unlikely(copy_to_iter((void *)&vnet_hdr, vnet_hdr_len,\n\t\t&m->msg_iter)))\n#else\n\tif (unlikely(memcpy_toiovecend(m->msg_iov,\n\t\t(void *)&vnet_hdr, 0, vnet_hdr_len)))\n#endif /* HAVE_IOV_ITER_MSGHDR */\n\t\treturn -EFAULT;\n#endif /* RTE_KNI_VHOST_VNET_HDR_EN */\n\tKNI_DBG_RX(\"kni_rcvmsg expect_len %ld, flags 0x%08x, pkt_len %d\\n\",\n\t\t (unsigned long)len, q->flags, pkt_len);\n\n\treturn (pkt_len + vnet_hdr_len);\n}\n\n/* dummy tap like ioctl */\nstatic int\nkni_sock_ioctl(struct socket *sock, unsigned int cmd,\n\t unsigned long arg)\n{\n\tvoid __user *argp = (void __user *)arg;\n\tstruct ifreq __user *ifr = argp;\n\tunsigned int __user *up = argp;\n\tstruct kni_vhost_queue *q =\n\t\tcontainer_of(sock->sk, struct kni_vhost_queue, sk);\n\tstruct kni_dev *kni;\n\tunsigned int u;\n\tint __user *sp = argp;\n\tint s;\n\tint ret;\n\n\tKNI_DBG(\"tap ioctl cmd 0x%08x\\n\", cmd);\n\n\tswitch (cmd) {\n\tcase TUNSETIFF:\n\t\tKNI_DBG(\"TUNSETIFF\\n\");\n\t\t/* ignore the name, just look at flags */\n\t\tif (get_user(u, &ifr->ifr_flags))\n\t\t\treturn -EFAULT;\n\n\t\tret = 0;\n\t\tif ((u & ~IFF_VNET_HDR) != (IFF_NO_PI | IFF_TAP))\n\t\t\tret = -EINVAL;\n\t\telse\n\t\t\tq->flags = u;\n\n\t\treturn ret;\n\n\tcase TUNGETIFF:\n\t\tKNI_DBG(\"TUNGETIFF\\n\");\n\t\trcu_read_lock_bh();\n\t\tkni = rcu_dereference_bh(q->kni);\n\t\tif (kni)\n\t\t\tdev_hold(kni->net_dev);\n\t\trcu_read_unlock_bh();\n\n\t\tif (!kni)\n\t\t\treturn -ENOLINK;\n\n\t\tret = 0;\n\t\tif (copy_to_user(&ifr->ifr_name, kni->net_dev->name, IFNAMSIZ) ||\n\t\t put_user(q->flags, &ifr->ifr_flags))\n\t\t\tret = -EFAULT;\n\t\tdev_put(kni->net_dev);\n\t\treturn ret;\n\n\tcase TUNGETFEATURES:\n\t\tKNI_DBG(\"TUNGETFEATURES\\n\");\n\t\tu = IFF_TAP | IFF_NO_PI;\n#ifdef RTE_KNI_VHOST_VNET_HDR_EN\n\t\tu |= IFF_VNET_HDR;\n#endif\n\t\tif (put_user(u, up))\n\t\t\treturn -EFAULT;\n\t\treturn 0;\n\n\tcase TUNSETSNDBUF:\n\t\tKNI_DBG(\"TUNSETSNDBUF\\n\");\n\t\tif (get_user(u, up))\n\t\t\treturn -EFAULT;\n\n\t\tq->sk.sk_sndbuf = u;\n\t\treturn 0;\n\n\tcase TUNGETVNETHDRSZ:\n\t\ts = q->vnet_hdr_sz;\n\t\tif (put_user(s, sp))\n\t\t\treturn -EFAULT;\n\t\tKNI_DBG(\"TUNGETVNETHDRSZ %d\\n\", s);\n\t\treturn 0;\n\n\tcase TUNSETVNETHDRSZ:\n\t\tif (get_user(s, sp))\n\t\t\treturn -EFAULT;\n\t\tif (s < (int)sizeof(struct virtio_net_hdr))\n\t\t\treturn -EINVAL;\n\n\t\tKNI_DBG(\"TUNSETVNETHDRSZ %d\\n\", s);\n\t\tq->vnet_hdr_sz = s;\n\t\treturn 0;\n\n\tcase TUNSETOFFLOAD:\n\t\tKNI_DBG(\"TUNSETOFFLOAD %lx\\n\", arg);\n#ifdef RTE_KNI_VHOST_VNET_HDR_EN\n\t\t/* not support any offload yet */\n\t\tif (!(q->flags & IFF_VNET_HDR))\n\t\t\treturn -EINVAL;\n\n\t\treturn 0;\n#else\n\t\treturn -EINVAL;\n#endif\n\n\tdefault:\n\t\tKNI_DBG(\"NOT SUPPORT\\n\");\n\t\treturn -EINVAL;\n\t}\n}\n\nstatic int\nkni_sock_compat_ioctl(struct socket *sock, unsigned int cmd,\n\t\t unsigned long arg)\n{\n\t/* 32 bits app on 64 bits OS to be supported later */\n\tKNI_PRINT(\"Not implemented.\\n\");\n\n\treturn -EINVAL;\n}\n\n#define KNI_VHOST_WAIT_WQ_SAFE() \\\ndo {\t\t \t\\\n\twhile ((BE_FINISH | BE_STOP) == kni->vq_status) \\\n\t\tmsleep(1); \\\n}while(0) \\\n\n\nstatic int\nkni_sock_release(struct socket *sock)\n{\n\tstruct kni_vhost_queue *q =\n\t\tcontainer_of(sock->sk, struct kni_vhost_queue, sk);\n\tstruct kni_dev *kni;\n\n\tif (q == NULL)\n\t\treturn 0;\n\n\tif (NULL != (kni = q->kni)) {\n\t\tkni->vq_status = BE_STOP;\n\t\tKNI_VHOST_WAIT_WQ_SAFE();\n\t\tkni->vhost_queue = NULL;\n\t\tq->kni = NULL;\n\t}\n\n\tif (q->sockfd != -1)\n\t\tq->sockfd = -1;\n\n\tsk_set_socket(&q->sk, NULL);\n\tsock->sk = NULL;\n\n\tsock_put(&q->sk);\n\n\tKNI_DBG(\"dummy sock release done\\n\");\n\n\treturn 0;\n}\n\nint\nkni_sock_getname (struct socket *sock,\n\t\t struct sockaddr *addr,\n\t\t int *sockaddr_len, int peer)\n{\n\tKNI_DBG(\"dummy sock getname\\n\");\n\t((struct sockaddr_ll*)addr)->sll_family = AF_PACKET;\n\treturn 0;\n}\n\nstatic const struct proto_ops kni_socket_ops = {\n\t.getname = kni_sock_getname,\n\t.sendmsg = kni_sock_sndmsg,\n\t.recvmsg = kni_sock_rcvmsg,\n\t.release = kni_sock_release,\n\t.poll = kni_sock_poll,\n\t.ioctl = kni_sock_ioctl,\n\t.compat_ioctl = kni_sock_compat_ioctl,\n};\n\nstatic void\nkni_sk_write_space(struct sock *sk)\n{\n\twait_queue_head_t *wqueue;\n\n\tif (!sock_writeable(sk) ||\n\t !test_and_clear_bit(SOCK_ASYNC_NOSPACE,\n\t\t\t\t&sk->sk_socket->flags))\n\t\treturn;\n\twqueue = sk_sleep(sk);\n\tif (wqueue && waitqueue_active(wqueue))\n\t\twake_up_interruptible_poll(\n\t\t\twqueue, POLLOUT | POLLWRNORM | POLLWRBAND);\n}\n\nstatic void\nkni_sk_destruct(struct sock *sk)\n{\n\tstruct kni_vhost_queue *q =\n\t\tcontainer_of(sk, struct kni_vhost_queue, sk);\n\n\tif (!q)\n\t\treturn;\n\n\t/* make sure there's no packet in buffer */\n\twhile (skb_dequeue(&sk->sk_receive_queue) != NULL)\n\t ;\n\n\tmb();\n\n\tif (q->fifo != NULL) {\n\t\tkfree(q->fifo);\n\t\tq->fifo = NULL;\n\t}\n\n\tif (q->cache != NULL) {\n\t\tkfree(q->cache);\n\t\tq->cache = NULL;\n\t}\n}\n\nstatic int\nkni_vhost_backend_init(struct kni_dev *kni)\n{\n\tstruct kni_vhost_queue *q;\n\tstruct net *net = current->nsproxy->net_ns;\n\tint err, i, sockfd;\n\tstruct rte_kni_fifo *fifo;\n\tstruct sk_buff *elem;\n\n\tif (kni->vhost_queue != NULL)\n\t\treturn -1;\n\n\tif (!(q = (struct kni_vhost_queue *)sk_alloc(\n\t\t net, AF_UNSPEC, GFP_KERNEL, &kni_raw_proto)))\n\t\treturn -ENOMEM;\n\n\terr = sock_create_lite(AF_UNSPEC, SOCK_RAW, IPPROTO_RAW, &q->sock);\n\tif (err)\n\t\tgoto free_sk;\n\n\tsockfd = kni_sock_map_fd(q->sock);\n\tif (sockfd < 0) {\n\t\terr = sockfd;\n\t\tgoto free_sock;\n\t}\n\n\t/* cache init */\n\tq->cache = kzalloc(RTE_KNI_VHOST_MAX_CACHE_SIZE * sizeof(struct sk_buff),\n\t\t\t GFP_KERNEL);\n\tif (!q->cache)\n\t\tgoto free_fd;\n\n\tfifo = kzalloc(RTE_KNI_VHOST_MAX_CACHE_SIZE * sizeof(void *)\n\t\t\t+ sizeof(struct rte_kni_fifo), GFP_KERNEL);\n\tif (!fifo)\n\t\tgoto free_cache;\n\n\tkni_fifo_init(fifo, RTE_KNI_VHOST_MAX_CACHE_SIZE);\n\n\tfor (i = 0; i < RTE_KNI_VHOST_MAX_CACHE_SIZE; i++) {\n\t\telem = &q->cache[i];\n\t\tkni_fifo_put(fifo, (void**)&elem, 1);\n\t}\n\tq->fifo = fifo;\n\n\t/* store sockfd in vhost_queue */\n\tq->sockfd = sockfd;\n\n\t/* init socket */\n\tq->sock->type = SOCK_RAW;\n\tq->sock->state = SS_CONNECTED;\n\tq->sock->ops = &kni_socket_ops;\n\tsock_init_data(q->sock, &q->sk);\n\n\t/* init sock data */\n\tq->sk.sk_write_space = kni_sk_write_space;\n\tq->sk.sk_destruct = kni_sk_destruct;\n\tq->flags = IFF_NO_PI | IFF_TAP;\n\tq->vnet_hdr_sz = sizeof(struct virtio_net_hdr);\n#ifdef RTE_KNI_VHOST_VNET_HDR_EN\n\tq->flags |= IFF_VNET_HDR;\n#endif\n\n\t/* bind kni_dev with vhost_queue */\n\tq->kni = kni;\n\tkni->vhost_queue = q;\n\n\twmb();\n\n\tkni->vq_status = BE_START;\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)\n\tKNI_DBG(\"backend init sockfd=%d, sock->wq=0x%16llx,\"\n\t\t \"sk->sk_wq=0x%16llx\",\n\t\t q->sockfd, (uint64_t)q->sock->wq,\n\t\t (uint64_t)q->sk.sk_wq);\n#else\n\tKNI_DBG(\"backend init sockfd=%d, sock->wait at 0x%16llx,\"\n\t\t \"sk->sk_sleep=0x%16llx\",\n\t\t q->sockfd, (uint64_t)&q->sock->wait,\n\t\t (uint64_t)q->sk.sk_sleep);\n#endif\n\n\treturn 0;\n\nfree_cache:\n\tkfree(q->cache);\n\tq->cache = NULL;\n\nfree_fd:\n\tput_unused_fd(sockfd);\n\nfree_sock:\n\tq->kni = NULL;\n\tkni->vhost_queue = NULL;\n\tkni->vq_status |= BE_FINISH;\n\tsock_release(q->sock);\n\tq->sock->ops = NULL;\n\tq->sock = NULL;\n\nfree_sk:\n\tsk_free((struct sock*)q);\n\n\treturn err;\n}\n\n/* kni vhost sock sysfs */\nstatic ssize_t\nshow_sock_fd(struct device *dev, struct device_attribute *attr,\n\t char *buf)\n{\n\tstruct net_device *net_dev = container_of(dev, struct net_device, dev);\n\tstruct kni_dev *kni = netdev_priv(net_dev);\n\tint sockfd = -1;\n\tif (kni->vhost_queue != NULL)\n\t\tsockfd = kni->vhost_queue->sockfd;\n\treturn snprintf(buf, 10, \"%d\\n\", sockfd);\n}\n\nstatic ssize_t\nshow_sock_en(struct device *dev, struct device_attribute *attr,\n\t char *buf)\n{\n\tstruct net_device *net_dev = container_of(dev, struct net_device, dev);\n\tstruct kni_dev *kni = netdev_priv(net_dev);\n\treturn snprintf(buf, 10, \"%u\\n\", (kni->vhost_queue == NULL ? 0 : 1));\n}\n\nstatic ssize_t\nset_sock_en(struct device *dev, struct device_attribute *attr,\n\t const char *buf, size_t count)\n{\n\tstruct net_device *net_dev = container_of(dev, struct net_device, dev);\n\tstruct kni_dev *kni = netdev_priv(net_dev);\n\tunsigned long en;\n\tint err = 0;\n\n\tif (0 != kstrtoul(buf, 0, &en))\n\t\treturn -EINVAL;\n\n\tif (en)\n\t\terr = kni_vhost_backend_init(kni);\n\n\treturn err ? err : count;\n}\n\nstatic DEVICE_ATTR(sock_fd, S_IRUGO | S_IRUSR, show_sock_fd, NULL);\nstatic DEVICE_ATTR(sock_en, S_IRUGO | S_IWUSR, show_sock_en, set_sock_en);\nstatic struct attribute *dev_attrs[] = {\n\t&dev_attr_sock_fd.attr,\n\t&dev_attr_sock_en.attr,\n NULL,\n};\n\nstatic const struct attribute_group dev_attr_grp = {\n\t.attrs = dev_attrs,\n};\n\nint\nkni_vhost_backend_release(struct kni_dev *kni)\n{\n\tstruct kni_vhost_queue *q = kni->vhost_queue;\n\n\tif (q == NULL)\n\t\treturn 0;\n\n\t/* dettach from kni */\n\tq->kni = NULL;\n\n\tKNI_DBG(\"release backend done\\n\");\n\n\treturn 0;\n}\n\nint\nkni_vhost_init(struct kni_dev *kni)\n{\n\tstruct net_device *dev = kni->net_dev;\n\n\tif (sysfs_create_group(&dev->dev.kobj, &dev_attr_grp))\n\t\tsysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);\n\n\tkni->vq_status = BE_STOP;\n\n\tKNI_DBG(\"kni_vhost_init done\\n\");\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_eal/linuxapp/xen_dom0/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# module name and path\n#\nMODULE = rte_dom0_mm\n\n#\n# CFLAGS\n#\nMODULE_CFLAGS += -I$(SRCDIR) --param max-inline-insns-single=50\nMODULE_CFLAGS += -I$(RTE_OUTPUT)/include\nMODULE_CFLAGS += -include $(RTE_OUTPUT)/include/rte_config.h\nMODULE_CFLAGS += -Wall -Werror\n\n# this lib needs main eal\nDEPDIRS-y += lib/librte_eal/linuxapp/eal\n\n#\n# all source are stored in SRCS-y\n#\n\nSRCS-y += dom0_mm_misc.c\n\ninclude $(RTE_SDK)/mk/rte.module.mk\n" }, { "path": "lib/librte_eal/linuxapp/xen_dom0/compat.h", "content": "/*\n * Minimal wrappers to allow compiling xen_dom0 on older kernels.\n */\n\n#ifndef RHEL_RELEASE_VERSION\n#define RHEL_RELEASE_VERSION(a, b) (((a) << 8) + (b))\n#endif\n\n#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39) && \\\n\t(!(defined(RHEL_RELEASE_CODE) && \\\n\t RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4)))\n\n#define kstrtoul strict_strtoul\n\n#endif /* < 2.6.39 */\n" }, { "path": "lib/librte_eal/linuxapp/xen_dom0/dom0_mm_dev.h", "content": "/*-\n * This file is provided under a dual BSD/GPLv2 license. When using or\n * redistributing this file, you may do so under either license.\n *\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n *\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n */\n#ifndef _DOM0_MM_DEV_H_\n#define _DOM0_MM_DEV_H_\n\n#include \n#include \n#include \n#include \n#include \n\n#define NUM_MEM_CTX 256 /**< Maximum number of memory context*/\n#define MAX_EXCHANGE_FAIL_TIME 5 /**< Maximum times of allowing exchange fail .*/\n#define MAX_MEMBLOCK_SIZE (2 * DOM0_MEMBLOCK_SIZE)\n#define MAX_NUM_ORDER (DOM0_CONTIG_NUM_ORDER + 1)\n#define SIZE_PER_BLOCK 2 /** < size of per memory block(2MB)).*/\n\n/**\n * A structure describing the private information for a dom0 device.\n */\nstruct dom0_mm_dev {\n\tstruct miscdevice miscdev;\n\tuint8_t fail_times;\n\tuint32_t used_memsize;\n\tuint32_t num_mem_ctx;\n\tuint32_t config_memsize;\n\tuint32_t num_bigblock;\n\tstruct dom0_mm_data *mm_data[NUM_MEM_CTX];\n\tstruct mutex data_lock;\n};\n\nstruct dom0_mm_data{\n\tuint32_t refcnt;\n\tuint32_t num_memseg; /**< Number of memory segment. */\n\tuint32_t mem_size; /**< Size of requesting memory. */\n\n\tchar name[DOM0_NAME_MAX];\n\n\t/** Store global memory block IDs used by an instance */\n\tuint32_t block_num[DOM0_NUM_MEMBLOCK];\n\n\t/** Store memory block information.*/\n\tstruct memblock_info block_info[DOM0_NUM_MEMBLOCK];\n\n\t/** Store memory segment information.*/\n\tstruct memseg_info seg_info[DOM0_NUM_MEMSEG];\n};\n\n#define XEN_ERR(args...) printk(KERN_DEBUG \"XEN_DOM0: Error: \" args)\n#define XEN_PRINT(args...) printk(KERN_DEBUG \"XEN_DOM0: \" args)\n#endif\n" }, { "path": "lib/librte_eal/linuxapp/xen_dom0/dom0_mm_misc.c", "content": "/*-\n * This file is provided under a dual BSD/GPLv2 license. When using or\n * redistributing this file, you may do so under either license.\n *\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n *\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \"compat.h\"\n#include \"dom0_mm_dev.h\"\n\nMODULE_LICENSE(\"Dual BSD/GPL\");\nMODULE_AUTHOR(\"Intel Corporation\");\nMODULE_DESCRIPTION(\"Kernel Module for supporting DPDK running on Xen Dom0\");\n\nstatic struct dom0_mm_dev dom0_dev;\nstatic struct kobject *dom0_kobj = NULL;\n\nstatic struct memblock_info *rsv_mm_info;\n\n/* Default configuration for reserved memory size(2048 MB). */\nstatic uint32_t rsv_memsize = 2048;\n\nstatic int dom0_open(struct inode *inode, struct file *file);\nstatic int dom0_release(struct inode *inode, struct file *file);\nstatic int dom0_ioctl(struct file *file, unsigned int ioctl_num,\n\t\tunsigned long ioctl_param);\nstatic int dom0_mmap(struct file *file, struct vm_area_struct *vma);\nstatic int dom0_memory_free(uint32_t size);\nstatic int dom0_memory_release(struct dom0_mm_data *mm_data);\n\nstatic const struct file_operations data_fops = {\n\t.owner = THIS_MODULE,\n\t.open = dom0_open,\n\t.release = dom0_release,\n\t.mmap = dom0_mmap,\n\t.unlocked_ioctl = (void *)dom0_ioctl,\n};\n\nstatic ssize_t\nshow_memsize_rsvd(struct device *dev, struct device_attribute *attr, char *buf)\n{\n\treturn snprintf(buf, 10, \"%u\\n\", dom0_dev.used_memsize);\n}\n\nstatic ssize_t\nshow_memsize(struct device *dev, struct device_attribute *attr, char *buf)\n{\n\treturn snprintf(buf, 10, \"%u\\n\", dom0_dev.config_memsize);\n}\n\nstatic ssize_t\nstore_memsize(struct device *dev, struct device_attribute *attr,\n const char *buf, size_t count)\n{\n\tint err = 0;\n\tunsigned long mem_size;\n\n\tif (0 != kstrtoul(buf, 0, &mem_size))\n\t\treturn -EINVAL;\n\n\tmutex_lock(&dom0_dev.data_lock);\n\tif (0 == mem_size) {\n\t\terr = -EINVAL;\n\t\tgoto fail;\n\t} else if (mem_size > (rsv_memsize - dom0_dev.used_memsize)) {\n\t\tXEN_ERR(\"configure memory size fail\\n\");\n\t\terr = -EINVAL;\n\t\tgoto fail;\n\t} else\n\t\tdom0_dev.config_memsize = mem_size;\n\nfail:\n\tmutex_unlock(&dom0_dev.data_lock);\n\treturn err ? err : count;\n}\n\nstatic DEVICE_ATTR(memsize, S_IRUGO | S_IWUSR, show_memsize, store_memsize);\nstatic DEVICE_ATTR(memsize_rsvd, S_IRUGO, show_memsize_rsvd, NULL);\n\nstatic struct attribute *dev_attrs[] = {\n\t&dev_attr_memsize.attr,\n\t&dev_attr_memsize_rsvd.attr,\n\tNULL,\n};\n\n/* the memory size unit is MB */\nstatic const struct attribute_group dev_attr_grp = {\n\t.name = \"memsize-mB\",\n\t.attrs = dev_attrs,\n};\n\n\nstatic void\nsort_viraddr(struct memblock_info *mb, int cnt)\n{\n\tint i,j;\n\tuint64_t tmp_pfn;\n\tuint64_t tmp_viraddr;\n\n\t/*sort virtual address and pfn */\n\tfor(i = 0; i < cnt; i ++) {\n\t\tfor(j = cnt - 1; j > i; j--) {\n\t\t\tif(mb[j].pfn < mb[j - 1].pfn) {\n\t\t\t\ttmp_pfn = mb[j - 1].pfn;\n\t\t\t\tmb[j - 1].pfn = mb[j].pfn;\n\t\t\t\tmb[j].pfn = tmp_pfn;\n\n\t\t\t\ttmp_viraddr = mb[j - 1].vir_addr;\n\t\t\t\tmb[j - 1].vir_addr = mb[j].vir_addr;\n\t\t\t\tmb[j].vir_addr = tmp_viraddr;\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic int\ndom0_find_memdata(const char * mem_name)\n{\n\tunsigned i;\n\tint idx = -1;\n\tfor(i = 0; i< NUM_MEM_CTX; i++) {\n\t\tif(dom0_dev.mm_data[i] == NULL)\n\t\t\tcontinue;\n\t\tif (!strncmp(dom0_dev.mm_data[i]->name, mem_name,\n\t\t\tsizeof(char) * DOM0_NAME_MAX)) {\n\t\t\tidx = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn idx;\n}\n\nstatic int\ndom0_find_mempos(void)\n{\n\tunsigned i;\n\tint idx = -1;\n\n\tfor(i = 0; i< NUM_MEM_CTX; i++) {\n\t\tif(dom0_dev.mm_data[i] == NULL){\n\t\t\tidx = i;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn idx;\n}\n\nstatic int\ndom0_memory_release(struct dom0_mm_data *mm_data)\n{\n\tint idx;\n\tuint32_t num_block, block_id;\n\n\t/* each memory block is 2M */\n\tnum_block = mm_data->mem_size / SIZE_PER_BLOCK;\n\tif (num_block == 0)\n\t\treturn -EINVAL;\n\n\t/* reset global memory data */\n\tidx = dom0_find_memdata(mm_data->name);\n\tif (idx >= 0) {\n\t\tdom0_dev.used_memsize -= mm_data->mem_size;\n\t\tdom0_dev.mm_data[idx] = NULL;\n\t\tdom0_dev.num_mem_ctx--;\n\t}\n\n\t/* reset these memory blocks status as free */\n\tfor (idx = 0; idx < num_block; idx++) {\n\t\tblock_id = mm_data->block_num[idx];\n\t\trsv_mm_info[block_id].used = 0;\n\t}\n\n\tmemset(mm_data, 0, sizeof(struct dom0_mm_data));\n\tvfree(mm_data);\n\treturn 0;\n}\n\nstatic int\ndom0_memory_free(uint32_t rsv_size)\n{\n\tuint64_t vstart, vaddr;\n\tuint32_t i, num_block, size;\n\n\tif (!xen_pv_domain())\n\t\treturn -1;\n\n\t/* each memory block is 2M */\n\tnum_block = rsv_size / SIZE_PER_BLOCK;\n\tif (num_block == 0)\n\t\treturn -EINVAL;\n\n\t/* free all memory blocks of size of 4M and destroy contiguous region */\n\tfor (i = 0; i < dom0_dev.num_bigblock * 2; i += 2) {\n\t\tvstart = rsv_mm_info[i].vir_addr;\n\t\tif (vstart) {\n\t\t#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)\n\t\t\tif (rsv_mm_info[i].exchange_flag)\n\t\t\t\txen_destroy_contiguous_region(vstart,\n\t\t\t\t\t\tDOM0_CONTIG_NUM_ORDER);\n\t\t\tif (rsv_mm_info[i + 1].exchange_flag)\n\t\t\t\txen_destroy_contiguous_region(vstart +\n\t\t\t\t\t\tDOM0_MEMBLOCK_SIZE,\n\t\t\t\t\t\tDOM0_CONTIG_NUM_ORDER);\n\t\t#else\n\t\t\tif (rsv_mm_info[i].exchange_flag)\n\t\t\t\txen_destroy_contiguous_region(rsv_mm_info[i].pfn\n\t\t\t\t\t* PAGE_SIZE,\n\t\t\t\t\tDOM0_CONTIG_NUM_ORDER);\n\t\t\tif (rsv_mm_info[i + 1].exchange_flag)\n\t\t\t\txen_destroy_contiguous_region(rsv_mm_info[i].pfn\n\t\t\t\t\t* PAGE_SIZE + DOM0_MEMBLOCK_SIZE,\n\t\t\t\t\tDOM0_CONTIG_NUM_ORDER);\n\t\t#endif\n\n\t\t\tsize = DOM0_MEMBLOCK_SIZE * 2;\n\t\t\tvaddr = vstart;\n\t\t\twhile (size > 0) {\n\t\t\t\tClearPageReserved(virt_to_page(vaddr));\n\t\t\t\tvaddr += PAGE_SIZE;\n\t\t\t\tsize -= PAGE_SIZE;\n\t\t\t}\n\t\t\tfree_pages(vstart, MAX_NUM_ORDER);\n\t\t}\n\t}\n\n\t/* free all memory blocks size of 2M and destroy contiguous region */\n\tfor (; i < num_block; i++) {\n\t\tvstart = rsv_mm_info[i].vir_addr;\n\t\tif (vstart) {\n\t\t\tif (rsv_mm_info[i].exchange_flag)\n\t\t\t\txen_destroy_contiguous_region(vstart,\n\t\t\t\t\tDOM0_CONTIG_NUM_ORDER);\n\n\t\t\tsize = DOM0_MEMBLOCK_SIZE;\n\t\t\tvaddr = vstart;\n\t\t\twhile (size > 0) {\n\t\t\t\tClearPageReserved(virt_to_page(vaddr));\n\t\t\t\tvaddr += PAGE_SIZE;\n\t\t\t\tsize -= PAGE_SIZE;\n\t\t\t}\n\t\t\tfree_pages(vstart, DOM0_CONTIG_NUM_ORDER);\n\t\t}\n\t}\n\n\tmemset(rsv_mm_info, 0, sizeof(struct memblock_info) * num_block);\n\tvfree(rsv_mm_info);\n\trsv_mm_info = NULL;\n\n\treturn 0;\n}\n\nstatic void\nfind_free_memory(uint32_t count, struct dom0_mm_data *mm_data)\n{\n\tuint32_t i = 0;\n\tuint32_t j = 0;\n\n\twhile ((i < count) && (j < rsv_memsize / SIZE_PER_BLOCK)) {\n\t\tif (rsv_mm_info[j].used == 0) {\n\t\t\tmm_data->block_info[i].pfn = rsv_mm_info[j].pfn;\n\t\t\tmm_data->block_info[i].vir_addr =\n\t\t\t\trsv_mm_info[j].vir_addr;\n\t\t\tmm_data->block_info[i].mfn = rsv_mm_info[j].mfn;\n\t\t\tmm_data->block_info[i].exchange_flag =\n\t\t\t\trsv_mm_info[j].exchange_flag;\n\t\t\tmm_data->block_num[i] = j;\n\t\t\trsv_mm_info[j].used = 1;\n\t\t\ti++;\n\t\t}\n\t\tj++;\n\t}\n}\n\n/**\n * Find all memory segments in which physical addresses are contiguous.\n */\nstatic void\nfind_memseg(int count, struct dom0_mm_data * mm_data)\n{\n\tint i = 0;\n\tint j, k, idx = 0;\n\tuint64_t zone_len, pfn, num_block;\n\n\twhile(i < count) {\n\t\tif (mm_data->block_info[i].exchange_flag == 0) {\n\t\t\ti++;\n\t\t\tcontinue;\n\t\t}\n\t\tk = 0;\n\t\tpfn = mm_data->block_info[i].pfn;\n\t\tmm_data->seg_info[idx].pfn = pfn;\n\t\tmm_data->seg_info[idx].mfn[k] = mm_data->block_info[i].mfn;\n\n\t\tfor (j = i + 1; j < count; j++) {\n\n\t\t\t/* ignore exchange fail memory block */\n\t\t\tif (mm_data->block_info[j].exchange_flag == 0)\n\t\t\t\tbreak;\n\n\t\t\tif (mm_data->block_info[j].pfn !=\n\t\t\t\t(mm_data->block_info[j - 1].pfn +\n\t\t\t\t\t DOM0_MEMBLOCK_SIZE / PAGE_SIZE))\n\t\t\t break;\n\t\t\t++k;\n\t\t\tmm_data->seg_info[idx].mfn[k] = mm_data->block_info[j].mfn;\n\t\t}\n\n\t\tnum_block = j - i;\n\t\tzone_len = num_block * DOM0_MEMBLOCK_SIZE;\n\t\tmm_data->seg_info[idx].size = zone_len;\n\n\t\tXEN_PRINT(\"memseg id=%d, size=0x%llx\\n\", idx, zone_len);\n\t\ti = i+ num_block;\n\t\tidx++;\n\t\tif (idx == DOM0_NUM_MEMSEG)\n\t\t\tbreak;\n\t}\n\tmm_data->num_memseg = idx;\n}\n\nstatic int\ndom0_memory_reserve(uint32_t rsv_size)\n{\n\tuint64_t pfn, vstart, vaddr;\n\tuint32_t i, num_block, size, allocated_size = 0;\n\n#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0)\n\tdma_addr_t dma_handle;\n#endif\n\n\t/* 2M as memory block */\n\tnum_block = rsv_size / SIZE_PER_BLOCK;\n\n\trsv_mm_info = vmalloc(sizeof(struct memblock_info) * num_block);\n\tif (!rsv_mm_info) {\n\t\tXEN_ERR(\"Unable to allocate device memory information\\n\");\n\t\treturn -ENOMEM;\n\t}\n\tmemset(rsv_mm_info, 0, sizeof(struct memblock_info) * num_block);\n\n\t/* try alloc size of 4M once */\n\tfor (i = 0; i < num_block; i += 2) {\n\t\tvstart = (unsigned long)\n\t\t\t__get_free_pages(GFP_ATOMIC, MAX_NUM_ORDER);\n\t\tif (vstart == 0)\n\t\t\tbreak;\n\n\t\tdom0_dev.num_bigblock = i / 2 + 1;\n\t\tallocated_size = SIZE_PER_BLOCK * (i + 2);\n\n\t\t/* size of 4M */\n\t\tsize = DOM0_MEMBLOCK_SIZE * 2;\n\n\t\tvaddr = vstart;\n\t\twhile (size > 0) {\n\t\t\tSetPageReserved(virt_to_page(vaddr));\n\t\t\tvaddr += PAGE_SIZE;\n\t\t\tsize -= PAGE_SIZE;\n\t\t}\n\n\t\tpfn = virt_to_pfn(vstart);\n\t\trsv_mm_info[i].pfn = pfn;\n\t\trsv_mm_info[i].vir_addr = vstart;\n\t\trsv_mm_info[i + 1].pfn =\n\t\t\t\tpfn + DOM0_MEMBLOCK_SIZE / PAGE_SIZE;\n\t\trsv_mm_info[i + 1].vir_addr =\n\t\t\t\tvstart + DOM0_MEMBLOCK_SIZE;\n\t}\n\n\t/*if it failed to alloc 4M, and continue to alloc 2M once */\n\tfor (; i < num_block; i++) {\n\t\tvstart = (unsigned long)\n\t\t\t__get_free_pages(GFP_ATOMIC, DOM0_CONTIG_NUM_ORDER);\n\t\tif (vstart == 0) {\n\t\t\tXEN_ERR(\"allocate memory fail.\\n\");\n\t\t\tdom0_memory_free(allocated_size);\n\t\t\treturn -ENOMEM;\n\t\t}\n\n\t\tallocated_size += SIZE_PER_BLOCK;\n\n\t\tsize = DOM0_MEMBLOCK_SIZE;\n\t\tvaddr = vstart;\n\t\twhile (size > 0) {\n\t\t\tSetPageReserved(virt_to_page(vaddr));\n\t\t\tvaddr += PAGE_SIZE;\n\t\t\tsize -= PAGE_SIZE;\n\t\t}\n\t\tpfn = virt_to_pfn(vstart);\n\t\trsv_mm_info[i].pfn = pfn;\n\t\trsv_mm_info[i].vir_addr = vstart;\n\t}\n\n\tsort_viraddr(rsv_mm_info, num_block);\n\n\tfor (i = 0; i< num_block; i++) {\n\n\t\t/*\n\t\t * This API is used to exchage MFN for getting a block of\n\t\t * contiguous physical addresses, its maximum size is 2M.\n\t\t */\n\t#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)\n\t\tif (xen_create_contiguous_region(rsv_mm_info[i].vir_addr,\n\t\t\t\tDOM0_CONTIG_NUM_ORDER, 0) == 0) {\n\t#else\n\t\tif (xen_create_contiguous_region(rsv_mm_info[i].pfn * PAGE_SIZE,\n\t\t\t\tDOM0_CONTIG_NUM_ORDER, 0, &dma_handle) == 0) {\n\t#endif\n\t\t\trsv_mm_info[i].exchange_flag = 1;\n\t\t\trsv_mm_info[i].mfn =\n\t\t\t\tpfn_to_mfn(rsv_mm_info[i].pfn);\n\t\t\trsv_mm_info[i].used = 0;\n\t\t} else {\n\t\t\tXEN_ERR(\"exchange memeory fail\\n\");\n\t\t\trsv_mm_info[i].exchange_flag = 0;\n\t\t\tdom0_dev.fail_times++;\n\t\t\tif (dom0_dev.fail_times > MAX_EXCHANGE_FAIL_TIME) {\n\t\t\t\tdom0_memory_free(rsv_size);\n\t\t\t\treturn -EFAULT;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\ndom0_prepare_memsegs(struct memory_info *meminfo, struct dom0_mm_data *mm_data)\n{\n\tuint32_t num_block;\n\tint idx;\n\n\t/* check if there is a free name buffer */\n\tmemcpy(mm_data->name, meminfo->name, DOM0_NAME_MAX);\n\tmm_data->name[DOM0_NAME_MAX - 1] = '\\0';\n\tidx = dom0_find_mempos();\n\tif (idx < 0)\n\t\treturn -1;\n\n\tnum_block = meminfo->size / SIZE_PER_BLOCK;\n\t/* find free memory and new memory segments*/\n\tfind_free_memory(num_block, mm_data);\n\tfind_memseg(num_block, mm_data);\n\n\t/* update private memory data */\n\tmm_data->refcnt++;\n\tmm_data->mem_size = meminfo->size;\n\n\t/* update global memory data */\n\tdom0_dev.mm_data[idx] = mm_data;\n\tdom0_dev.num_mem_ctx++;\n\tdom0_dev.used_memsize += mm_data->mem_size;\n\n\treturn 0;\n}\n\nstatic int\ndom0_check_memory (struct memory_info *meminfo)\n{\n\tint idx;\n\tuint64_t mem_size;\n\n\t/* round memory size to the next even number. */\n\tif (meminfo->size % 2)\n\t\t++meminfo->size;\n\n\tmem_size = meminfo->size;\n\tif (dom0_dev.num_mem_ctx > NUM_MEM_CTX) {\n\t\tXEN_ERR(\"Memory data space is full in Dom0 driver\\n\");\n\t\treturn -1;\n\t}\n\tidx = dom0_find_memdata(meminfo->name);\n\tif (idx >= 0) {\n\t\tXEN_ERR(\"Memory data name %s has already exsited in Dom0 driver.\\n\",\n\t\t\tmeminfo->name);\n\t\treturn -1;\n\t}\n\tif ((dom0_dev.used_memsize + mem_size) > rsv_memsize) {\n\t\tXEN_ERR(\"Total size can't be larger than reserved size.\\n\");\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\nstatic int __init\ndom0_init(void)\n{\n\tif (!xen_domain())\n\t\treturn -ENODEV;\n\n\tif (rsv_memsize > DOM0_CONFIG_MEMSIZE) {\n\t\tXEN_ERR(\"The reserved memory size cannot be greater than %d\\n\",\n\t\t\tDOM0_CONFIG_MEMSIZE);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Setup the misc device */\n\tdom0_dev.miscdev.minor = MISC_DYNAMIC_MINOR;\n\tdom0_dev.miscdev.name = \"dom0_mm\";\n\tdom0_dev.miscdev.fops = &data_fops;\n\n\t/* register misc char device */\n\tif (misc_register(&dom0_dev.miscdev) != 0) {\n\t\tXEN_ERR(\"Misc device registration failed\\n\");\n\t\treturn -EPERM;\n\t}\n\n\tmutex_init(&dom0_dev.data_lock);\n\tdom0_kobj = kobject_create_and_add(\"dom0-mm\", mm_kobj);\n\n\tif (!dom0_kobj) {\n\t\tXEN_ERR(\"dom0-mm object creation failed\\n\");\n\t\tmisc_deregister(&dom0_dev.miscdev);\n\t\treturn -ENOMEM;\n\t}\n\n\tif (sysfs_create_group(dom0_kobj, &dev_attr_grp)) {\n\t\tkobject_put(dom0_kobj);\n\t\tmisc_deregister(&dom0_dev.miscdev);\n\t\treturn -EPERM;\n\t}\n\n\tif (dom0_memory_reserve(rsv_memsize) < 0) {\n\t\tsysfs_remove_group(dom0_kobj, &dev_attr_grp);\n\t\tkobject_put(dom0_kobj);\n\t\tmisc_deregister(&dom0_dev.miscdev);\n\t\treturn -ENOMEM;\n\t}\n\n\tXEN_PRINT(\"####### DPDK Xen Dom0 module loaded #######\\n\");\n\n\treturn 0;\n}\n\nstatic void __exit\ndom0_exit(void)\n{\n\tif (rsv_mm_info != NULL)\n\t\tdom0_memory_free(rsv_memsize);\n\n\tsysfs_remove_group(dom0_kobj, &dev_attr_grp);\n\tkobject_put(dom0_kobj);\n\tmisc_deregister(&dom0_dev.miscdev);\n\n\tXEN_PRINT(\"####### DPDK Xen Dom0 module unloaded #######\\n\");\n}\n\nstatic int\ndom0_open(struct inode *inode, struct file *file)\n{\n\tfile->private_data = NULL;\n\n\tXEN_PRINT(KERN_INFO \"/dev/dom0_mm opened\\n\");\n\treturn 0;\n}\n\nstatic int\ndom0_release(struct inode *inode, struct file *file)\n{\n\tint ret = 0;\n\tstruct dom0_mm_data *mm_data = file->private_data;\n\n\tif (mm_data == NULL)\n\t\treturn ret;\n\n\tmutex_lock(&dom0_dev.data_lock);\n\tif (--mm_data->refcnt == 0)\n\t\tret = dom0_memory_release(mm_data);\n\tmutex_unlock(&dom0_dev.data_lock);\n\n\tfile->private_data = NULL;\n\tXEN_PRINT(KERN_INFO \"/dev/dom0_mm closed\\n\");\n\treturn ret;\n}\n\nstatic int\ndom0_mmap(struct file *file, struct vm_area_struct *vm)\n{\n\tint status = 0;\n\tuint32_t idx = vm->vm_pgoff;\n\tuint64_t pfn, size = vm->vm_end - vm->vm_start;\n\tstruct dom0_mm_data *mm_data = file->private_data;\n\n\tif(mm_data == NULL)\n\t\treturn -EINVAL;\n\n\tmutex_lock(&dom0_dev.data_lock);\n\tif (idx >= mm_data->num_memseg) {\n\t\tmutex_unlock(&dom0_dev.data_lock);\n\t\treturn -EINVAL;\n\t}\n\n\tif (size > mm_data->seg_info[idx].size){\n\t\tmutex_unlock(&dom0_dev.data_lock);\n\t\treturn -EINVAL;\n\t}\n\n\tXEN_PRINT(\"mmap memseg idx =%d,size = 0x%llx\\n\", idx, size);\n\n\tpfn = mm_data->seg_info[idx].pfn;\n\tmutex_unlock(&dom0_dev.data_lock);\n\n\tstatus = remap_pfn_range(vm, vm->vm_start, pfn, size, PAGE_SHARED);\n\n\treturn status;\n}\nstatic int\ndom0_ioctl(struct file *file,\n\tunsigned int ioctl_num,\n\tunsigned long ioctl_param)\n{\n\tint idx, ret;\n\tchar name[DOM0_NAME_MAX] = {0};\n\tstruct memory_info meminfo;\n\tstruct dom0_mm_data *mm_data = file->private_data;\n\n\tXEN_PRINT(\"IOCTL num=0x%0x param=0x%0lx \\n\", ioctl_num, ioctl_param);\n\n\t/**\n\t * Switch according to the ioctl called\n\t */\n\tswitch _IOC_NR(ioctl_num) {\n\tcase _IOC_NR(RTE_DOM0_IOCTL_PREPARE_MEMSEG):\n\t\tret = copy_from_user(&meminfo, (void *)ioctl_param,\n\t\t\tsizeof(struct memory_info));\n\t\tif (ret)\n\t\t\treturn -EFAULT;\n\n\t\tif (mm_data != NULL) {\n\t\t\tXEN_ERR(\"Cannot create memory segment for the same\"\n\t\t\t\t\" file descriptor\\n\");\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\t/* Allocate private data */\n\t\tmm_data = vmalloc(sizeof(struct dom0_mm_data));\n\t\tif (!mm_data) {\n\t\t\tXEN_ERR(\"Unable to allocate device private data\\n\");\n\t\t\treturn -ENOMEM;\n\t\t}\n\t\tmemset(mm_data, 0, sizeof(struct dom0_mm_data));\n\n\t\tmutex_lock(&dom0_dev.data_lock);\n\t\t/* check if we can allocate memory*/\n\t\tif (dom0_check_memory(&meminfo) < 0) {\n\t\t\tmutex_unlock(&dom0_dev.data_lock);\n\t\t\tvfree(mm_data);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\t/* allocate memory and created memory segments*/\n\t\tif (dom0_prepare_memsegs(&meminfo, mm_data) < 0) {\n\t\t\tXEN_ERR(\"create memory segment fail.\\n\");\n\t\t\tmutex_unlock(&dom0_dev.data_lock);\n\t\t\treturn -EIO;\n\t\t}\n\n\t\tfile->private_data = mm_data;\n\t\tmutex_unlock(&dom0_dev.data_lock);\n\t\tbreak;\n\n\t/* support multiple process in term of memory mapping*/\n\tcase _IOC_NR(RTE_DOM0_IOCTL_ATTACH_TO_MEMSEG):\n\t\tret = copy_from_user(name, (void *)ioctl_param,\n\t\t\t\tsizeof(char) * DOM0_NAME_MAX);\n\t\tif (ret)\n\t\t\treturn -EFAULT;\n\n\t\tmutex_lock(&dom0_dev.data_lock);\n\t\tidx = dom0_find_memdata(name);\n\t\tif (idx < 0) {\n\t\t\tmutex_unlock(&dom0_dev.data_lock);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tmm_data = dom0_dev.mm_data[idx];\n\t\tmm_data->refcnt++;\n\t\tfile->private_data = mm_data;\n\t\tmutex_unlock(&dom0_dev.data_lock);\n\t\tbreak;\n\n\tcase _IOC_NR(RTE_DOM0_IOCTL_GET_NUM_MEMSEG):\n\t\tret = copy_to_user((void *)ioctl_param, &mm_data->num_memseg,\n\t\t\t\tsizeof(int));\n\t\tif (ret)\n\t\t\treturn -EFAULT;\n\t\tbreak;\n\n\tcase _IOC_NR(RTE_DOM0_IOCTL_GET_MEMSEG_INFO):\n\t\tret = copy_to_user((void *)ioctl_param,\n\t\t\t\t&mm_data->seg_info[0],\n\t\t\t\tsizeof(struct memseg_info) *\n\t\t\t\tmm_data->num_memseg);\n\t\tif (ret)\n\t\t\treturn -EFAULT;\n\t\tbreak;\n\tdefault:\n\t\tXEN_PRINT(\"IOCTL default \\n\");\n\t\tbreak;\n\t}\n\n\treturn 0;\n}\n\nmodule_init(dom0_init);\nmodule_exit(dom0_exit);\n\nmodule_param(rsv_memsize, uint, S_IRUGO | S_IWUSR);\nMODULE_PARM_DESC(rsv_memsize, \"Xen-dom0 reserved memory size(MB).\\n\");\n" }, { "path": "lib/librte_ether/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = libethdev.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_ether_version.map\n\nLIBABIVER := 1\n\nSRCS-y += rte_ethdev.c\n\n#\n# Export include files\n#\nSYMLINK-y-include += rte_ether.h\nSYMLINK-y-include += rte_ethdev.h\nSYMLINK-y-include += rte_eth_ctrl.h\nSYMLINK-y-include += rte_dev_info.h\n\n# this lib depends upon:\nDEPDIRS-y += lib/librte_eal lib/librte_mempool lib/librte_ring lib/librte_mbuf\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_ether/rte_dev_info.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_DEV_INFO_H_\n#define _RTE_DEV_INFO_H_\n\n/*\n * Placeholder for accessing device registers\n */\nstruct rte_dev_reg_info {\n\tvoid *data; /**< Buffer for return registers */\n\tuint32_t offset; /**< Start register table location for access */\n\tuint32_t length; /**< Number of registers to fetch */\n\tuint32_t version; /**< Device version */\n};\n\n/*\n * Placeholder for accessing device eeprom\n */\nstruct rte_dev_eeprom_info {\n\tvoid *data; /**< Buffer for return eeprom */\n\tuint32_t offset; /**< Start eeprom address for access*/\n\tuint32_t length; /**< Length of eeprom region to access */\n\tuint32_t magic; /**< Device-specific key, such as device-id */\n};\n\n#endif /* _RTE_DEV_INFO_H_ */\n" }, { "path": "lib/librte_ether/rte_eth_ctrl.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ETH_CTRL_H_\n#define _RTE_ETH_CTRL_H_\n\n/**\n * @file\n *\n * Ethernet device features and related data structures used\n * by control APIs should be defined in this file.\n *\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*\n * A packet can be identified by hardware as different flow types. Different\n * NIC hardwares may support different flow types.\n * Basically, the NIC hardware identifies the flow type as deep protocol as\n * possible, and exclusively. For example, if a packet is identified as\n * 'RTE_ETH_FLOW_NONFRAG_IPV4_TCP', it will not be any of other flow types,\n * though it is an actual IPV4 packet.\n * Note that the flow types are used to define RSS offload types in\n * rte_ethdev.h.\n */\n#define RTE_ETH_FLOW_UNKNOWN 0\n#define RTE_ETH_FLOW_RAW 1\n#define RTE_ETH_FLOW_IPV4 2\n#define RTE_ETH_FLOW_FRAG_IPV4 3\n#define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4\n#define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5\n#define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6\n#define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7\n#define RTE_ETH_FLOW_IPV6 8\n#define RTE_ETH_FLOW_FRAG_IPV6 9\n#define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10\n#define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11\n#define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12\n#define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13\n#define RTE_ETH_FLOW_L2_PAYLOAD 14\n#define RTE_ETH_FLOW_IPV6_EX 15\n#define RTE_ETH_FLOW_IPV6_TCP_EX 16\n#define RTE_ETH_FLOW_IPV6_UDP_EX 17\n#define RTE_ETH_FLOW_MAX 18\n\n/**\n * Feature filter types\n */\nenum rte_filter_type {\n\tRTE_ETH_FILTER_NONE = 0,\n\tRTE_ETH_FILTER_MACVLAN,\n\tRTE_ETH_FILTER_ETHERTYPE,\n\tRTE_ETH_FILTER_FLEXIBLE,\n\tRTE_ETH_FILTER_SYN,\n\tRTE_ETH_FILTER_NTUPLE,\n\tRTE_ETH_FILTER_TUNNEL,\n\tRTE_ETH_FILTER_FDIR,\n\tRTE_ETH_FILTER_HASH,\n\tRTE_ETH_FILTER_MAX\n};\n\n/**\n * Generic operations on filters\n */\nenum rte_filter_op {\n\t/** used to check whether the type filter is supported */\n\tRTE_ETH_FILTER_NOP = 0,\n\tRTE_ETH_FILTER_ADD, /**< add filter entry */\n\tRTE_ETH_FILTER_UPDATE, /**< update filter entry */\n\tRTE_ETH_FILTER_DELETE, /**< delete filter entry */\n\tRTE_ETH_FILTER_FLUSH, /**< flush all entries */\n\tRTE_ETH_FILTER_GET, /**< get filter entry */\n\tRTE_ETH_FILTER_SET, /**< configurations */\n\tRTE_ETH_FILTER_INFO, /**< retrieve information */\n\tRTE_ETH_FILTER_STATS, /**< retrieve statistics */\n\tRTE_ETH_FILTER_OP_MAX\n};\n\n/**\n * MAC filter type\n */\nenum rte_mac_filter_type {\n\tRTE_MAC_PERFECT_MATCH = 1, /**< exact match of MAC addr. */\n\tRTE_MACVLAN_PERFECT_MATCH, /**< exact match of MAC addr and VLAN ID. */\n\tRTE_MAC_HASH_MATCH, /**< hash match of MAC addr. */\n\t/** hash match of MAC addr and exact match of VLAN ID. */\n\tRTE_MACVLAN_HASH_MATCH,\n};\n\n/**\n * MAC filter info\n */\nstruct rte_eth_mac_filter {\n\tuint8_t is_vf; /**< 1 for VF, 0 for port dev */\n\tuint16_t dst_id; /**< VF ID, available when is_vf is 1*/\n\tenum rte_mac_filter_type filter_type; /**< MAC filter type */\n\tstruct ether_addr mac_addr;\n};\n\n/**\n * Define all structures for Ethertype Filter type.\n */\n\n#define RTE_ETHTYPE_FLAGS_MAC 0x0001 /**< If set, compare mac */\n#define RTE_ETHTYPE_FLAGS_DROP 0x0002 /**< If set, drop packet when match */\n\n/**\n * A structure used to define the ethertype filter entry\n * to support RTE_ETH_FILTER_ETHERTYPE with RTE_ETH_FILTER_ADD,\n * RTE_ETH_FILTER_DELETE and RTE_ETH_FILTER_GET operations.\n */\nstruct rte_eth_ethertype_filter {\n\tstruct ether_addr mac_addr; /**< Mac address to match. */\n\tuint16_t ether_type; /**< Ether type to match */\n\tuint16_t flags; /**< Flags from RTE_ETHTYPE_FLAGS_* */\n\tuint16_t queue; /**< Queue assigned to when match*/\n};\n\n#define RTE_FLEX_FILTER_MAXLEN\t128\t/**< bytes to use in flex filter. */\n#define RTE_FLEX_FILTER_MASK_SIZE\t\\\n\t(RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)\n\t\t\t\t\t/**< mask bytes in flex filter. */\n\n/**\n * A structure used to define the flex filter entry\n * to support RTE_ETH_FILTER_FLEXIBLE with RTE_ETH_FILTER_ADD,\n * RTE_ETH_FILTER_DELETE and RTE_ETH_FILTER_GET operations.\n */\nstruct rte_eth_flex_filter {\n\tuint16_t len;\n\tuint8_t bytes[RTE_FLEX_FILTER_MAXLEN]; /**< flex bytes in big endian.*/\n\tuint8_t mask[RTE_FLEX_FILTER_MASK_SIZE]; /**< if mask bit is 1b, do\n\t\t\t\t\tnot compare corresponding byte. */\n\tuint8_t priority;\n\tuint16_t queue; /**< Queue assigned to when match. */\n};\n\n/**\n * A structure used to define the TCP syn filter entry\n * to support RTE_ETH_FILTER_SYN with RTE_ETH_FILTER_ADD,\n * RTE_ETH_FILTER_DELETE and RTE_ETH_FILTER_GET operations.\n */\nstruct rte_eth_syn_filter {\n\tuint8_t hig_pri; /**< 1 - higher priority than other filters,\n\t\t\t\t 0 - lower priority. */\n\tuint16_t queue; /**< Queue assigned to when match */\n};\n\n/**\n * Define all structures for ntuple Filter type.\n */\n\n#define RTE_NTUPLE_FLAGS_DST_IP 0x0001 /**< If set, dst_ip is part of ntuple */\n#define RTE_NTUPLE_FLAGS_SRC_IP 0x0002 /**< If set, src_ip is part of ntuple */\n#define RTE_NTUPLE_FLAGS_DST_PORT 0x0004 /**< If set, dst_port is part of ntuple */\n#define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008 /**< If set, src_port is part of ntuple */\n#define RTE_NTUPLE_FLAGS_PROTO 0x0010 /**< If set, protocol is part of ntuple */\n#define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020 /**< If set, tcp flag is involved */\n\n#define RTE_5TUPLE_FLAGS ( \\\n\t\tRTE_NTUPLE_FLAGS_DST_IP | \\\n\t\tRTE_NTUPLE_FLAGS_SRC_IP | \\\n\t\tRTE_NTUPLE_FLAGS_DST_PORT | \\\n\t\tRTE_NTUPLE_FLAGS_SRC_PORT | \\\n\t\tRTE_NTUPLE_FLAGS_PROTO)\n\n#define RTE_2TUPLE_FLAGS ( \\\n\t\tRTE_NTUPLE_FLAGS_DST_PORT | \\\n\t\tRTE_NTUPLE_FLAGS_PROTO)\n\n#define TCP_URG_FLAG 0x20\n#define TCP_ACK_FLAG 0x10\n#define TCP_PSH_FLAG 0x08\n#define TCP_RST_FLAG 0x04\n#define TCP_SYN_FLAG 0x02\n#define TCP_FIN_FLAG 0x01\n#define TCP_FLAG_ALL 0x3F\n\n/**\n * A structure used to define the ntuple filter entry\n * to support RTE_ETH_FILTER_NTUPLE with RTE_ETH_FILTER_ADD,\n * RTE_ETH_FILTER_DELETE and RTE_ETH_FILTER_GET operations.\n */\nstruct rte_eth_ntuple_filter {\n\tuint16_t flags; /**< Flags from RTE_NTUPLE_FLAGS_* */\n\tuint32_t dst_ip; /**< Destination IP address in big endian. */\n\tuint32_t dst_ip_mask; /**< Mask of destination IP address. */\n\tuint32_t src_ip; /**< Source IP address in big endian. */\n\tuint32_t src_ip_mask; /**< Mask of destination IP address. */\n\tuint16_t dst_port; /**< Destination port in big endian. */\n\tuint16_t dst_port_mask; /**< Mask of destination port. */\n\tuint16_t src_port; /**< Source Port in big endian. */\n\tuint16_t src_port_mask; /**< Mask of source port. */\n\tuint8_t proto; /**< L4 protocol. */\n\tuint8_t proto_mask; /**< Mask of L4 protocol. */\n\t/** tcp_flags only meaningful when the proto is TCP.\n\t The packet matched above ntuple fields and contain\n\t any set bit in tcp_flags will hit this filter. */\n\tuint8_t tcp_flags;\n\tuint16_t priority; /**< seven levels (001b-111b), 111b is highest,\n\t\t\t\t used when more than one filter matches. */\n\tuint16_t queue; /**< Queue assigned to when match*/\n};\n\n/**\n * Tunneled type.\n */\nenum rte_eth_tunnel_type {\n\tRTE_TUNNEL_TYPE_NONE = 0,\n\tRTE_TUNNEL_TYPE_VXLAN,\n\tRTE_TUNNEL_TYPE_GENEVE,\n\tRTE_TUNNEL_TYPE_TEREDO,\n\tRTE_TUNNEL_TYPE_NVGRE,\n\tRTE_TUNNEL_TYPE_MAX,\n};\n\n/**\n * filter type of tunneling packet\n */\n#define ETH_TUNNEL_FILTER_OMAC 0x01 /**< filter by outer MAC addr */\n#define ETH_TUNNEL_FILTER_OIP 0x02 /**< filter by outer IP Addr */\n#define ETH_TUNNEL_FILTER_TENID 0x04 /**< filter by tenant ID */\n#define ETH_TUNNEL_FILTER_IMAC 0x08 /**< filter by inner MAC addr */\n#define ETH_TUNNEL_FILTER_IVLAN 0x10 /**< filter by inner VLAN ID */\n#define ETH_TUNNEL_FILTER_IIP 0x20 /**< filter by inner IP addr */\n\n#define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \\\n\t\t\t\t\tETH_TUNNEL_FILTER_IVLAN)\n#define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \\\n\t\t\t\t\tETH_TUNNEL_FILTER_IVLAN | \\\n\t\t\t\t\tETH_TUNNEL_FILTER_TENID)\n#define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \\\n\t\t\t\t\tETH_TUNNEL_FILTER_TENID)\n#define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \\\n\t\t\t\t\tETH_TUNNEL_FILTER_TENID | \\\n\t\t\t\t\tETH_TUNNEL_FILTER_IMAC)\n\n/**\n * Select IPv4 or IPv6 for tunnel filters.\n */\nenum rte_tunnel_iptype {\n\tRTE_TUNNEL_IPTYPE_IPV4 = 0, /**< IPv4. */\n\tRTE_TUNNEL_IPTYPE_IPV6, /**< IPv6. */\n};\n\n/**\n * Tunneling Packet filter configuration.\n */\nstruct rte_eth_tunnel_filter_conf {\n\tstruct ether_addr *outer_mac; /**< Outer MAC address filter. */\n\tstruct ether_addr *inner_mac; /**< Inner MAC address filter. */\n\tuint16_t inner_vlan; /**< Inner VLAN filter. */\n\tenum rte_tunnel_iptype ip_type; /**< IP address type. */\n\tunion {\n\t\tuint32_t ipv4_addr; /**< IPv4 source address to match. */\n\t\tuint32_t ipv6_addr[4]; /**< IPv6 source address to match. */\n\t} ip_addr; /**< IPv4/IPv6 source address to match (union of above). */\n\n\tuint16_t filter_type; /**< Filter type. */\n\tenum rte_eth_tunnel_type tunnel_type; /**< Tunnel Type. */\n\tuint32_t tenant_id; /** < Tenant number. */\n\tuint16_t queue_id; /** < queue number. */\n};\n\n#define RTE_ETH_FDIR_MAX_FLEXLEN 16 /** < Max length of flexbytes. */\n\n/**\n * A structure used to define the input for L2 flow\n */\nstruct rte_eth_l2_flow {\n\tuint16_t ether_type; /**< Ether type to match */\n};\n\n/**\n * A structure used to define the input for IPV4 flow\n */\nstruct rte_eth_ipv4_flow {\n\tuint32_t src_ip; /**< IPv4 source address to match. */\n\tuint32_t dst_ip; /**< IPv4 destination address to match. */\n};\n\n/**\n * A structure used to define the input for IPV4 UDP flow\n */\nstruct rte_eth_udpv4_flow {\n\tstruct rte_eth_ipv4_flow ip; /**< IPv4 fields to match. */\n\tuint16_t src_port; /**< UDP source port to match. */\n\tuint16_t dst_port; /**< UDP destination port to match. */\n};\n\n/**\n * A structure used to define the input for IPV4 TCP flow\n */\nstruct rte_eth_tcpv4_flow {\n\tstruct rte_eth_ipv4_flow ip; /**< IPv4 fields to match. */\n\tuint16_t src_port; /**< TCP source port to match. */\n\tuint16_t dst_port; /**< TCP destination port to match. */\n};\n\n/**\n * A structure used to define the input for IPV4 SCTP flow\n */\nstruct rte_eth_sctpv4_flow {\n\tstruct rte_eth_ipv4_flow ip; /**< IPv4 fields to match. */\n#ifdef RTE_NEXT_ABI\n\tuint16_t src_port; /**< SCTP source port to match. */\n\tuint16_t dst_port; /**< SCTP destination port to match. */\n#endif\n\tuint32_t verify_tag; /**< Verify tag to match */\n};\n\n/**\n * A structure used to define the input for IPV6 flow\n */\nstruct rte_eth_ipv6_flow {\n\tuint32_t src_ip[4]; /**< IPv6 source address to match. */\n\tuint32_t dst_ip[4]; /**< IPv6 destination address to match. */\n};\n\n/**\n * A structure used to define the input for IPV6 UDP flow\n */\nstruct rte_eth_udpv6_flow {\n\tstruct rte_eth_ipv6_flow ip; /**< IPv6 fields to match. */\n\tuint16_t src_port; /**< UDP source port to match. */\n\tuint16_t dst_port; /**< UDP destination port to match. */\n};\n\n/**\n * A structure used to define the input for IPV6 TCP flow\n */\nstruct rte_eth_tcpv6_flow {\n\tstruct rte_eth_ipv6_flow ip; /**< IPv6 fields to match. */\n\tuint16_t src_port; /**< TCP source port to match. */\n\tuint16_t dst_port; /**< TCP destination port to match. */\n};\n\n/**\n * A structure used to define the input for IPV6 SCTP flow\n */\nstruct rte_eth_sctpv6_flow {\n\tstruct rte_eth_ipv6_flow ip; /**< IPv6 fields to match. */\n#ifdef RTE_NEXT_ABI\n\tuint16_t src_port; /**< SCTP source port to match. */\n\tuint16_t dst_port; /**< SCTP destination port to match. */\n#endif\n\tuint32_t verify_tag; /**< Verify tag to match */\n};\n\n/**\n * An union contains the inputs for all types of flow\n */\nunion rte_eth_fdir_flow {\n\tstruct rte_eth_l2_flow l2_flow;\n\tstruct rte_eth_udpv4_flow udp4_flow;\n\tstruct rte_eth_tcpv4_flow tcp4_flow;\n\tstruct rte_eth_sctpv4_flow sctp4_flow;\n\tstruct rte_eth_ipv4_flow ip4_flow;\n\tstruct rte_eth_udpv6_flow udp6_flow;\n\tstruct rte_eth_tcpv6_flow tcp6_flow;\n\tstruct rte_eth_sctpv6_flow sctp6_flow;\n\tstruct rte_eth_ipv6_flow ipv6_flow;\n};\n\n/**\n * A structure used to contain extend input of flow\n */\nstruct rte_eth_fdir_flow_ext {\n\tuint16_t vlan_tci;\n\tuint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];\n\t/**< It is filled by the flexible payload to match. */\n};\n\n/**\n * A structure used to define the input for a flow director filter entry\n */\nstruct rte_eth_fdir_input {\n\tuint16_t flow_type;\n\tunion rte_eth_fdir_flow flow;\n\t/**< Flow fields to match, dependent on flow_type */\n\tstruct rte_eth_fdir_flow_ext flow_ext;\n\t/**< Additional fields to match */\n};\n\n/**\n * Behavior will be taken if FDIR match\n */\nenum rte_eth_fdir_behavior {\n\tRTE_ETH_FDIR_ACCEPT = 0,\n\tRTE_ETH_FDIR_REJECT,\n};\n\n/**\n * Flow director report status\n * It defines what will be reported if FDIR entry is matched.\n */\nenum rte_eth_fdir_status {\n\tRTE_ETH_FDIR_NO_REPORT_STATUS = 0, /**< Report nothing. */\n\tRTE_ETH_FDIR_REPORT_ID, /**< Only report FD ID. */\n\tRTE_ETH_FDIR_REPORT_ID_FLEX_4, /**< Report FD ID and 4 flex bytes. */\n\tRTE_ETH_FDIR_REPORT_FLEX_8, /**< Report 8 flex bytes. */\n};\n\n/**\n * A structure used to define an action when match FDIR packet filter.\n */\nstruct rte_eth_fdir_action {\n\tuint16_t rx_queue; /**< Queue assigned to if FDIR match. */\n\tenum rte_eth_fdir_behavior behavior; /**< Behavior will be taken */\n\tenum rte_eth_fdir_status report_status; /**< Status report option */\n\tuint8_t flex_off;\n\t/**< If report_status is RTE_ETH_FDIR_REPORT_ID_FLEX_4 or\n\t RTE_ETH_FDIR_REPORT_FLEX_8, flex_off specifies where the reported\n\t flex bytes start from in flexible payload. */\n};\n\n/**\n * A structure used to define the flow director filter entry by filter_ctrl API\n * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and\n * RTE_ETH_FILTER_DELETE operations.\n */\nstruct rte_eth_fdir_filter {\n\tuint32_t soft_id;\n\t/**< ID, an unique value is required when deal with FDIR entry */\n\tstruct rte_eth_fdir_input input; /**< Input set */\n\tstruct rte_eth_fdir_action action; /**< Action taken when match */\n};\n\n/**\n * A structure used to configure FDIR masks that are used by the device\n * to match the various fields of RX packet headers.\n */\nstruct rte_eth_fdir_masks {\n\tuint16_t vlan_tci_mask;\n\tstruct rte_eth_ipv4_flow ipv4_mask;\n\tstruct rte_eth_ipv6_flow ipv6_mask;\n\tuint16_t src_port_mask;\n\tuint16_t dst_port_mask;\n};\n\n/**\n * Payload type\n */\nenum rte_eth_payload_type {\n\tRTE_ETH_PAYLOAD_UNKNOWN = 0,\n\tRTE_ETH_RAW_PAYLOAD,\n\tRTE_ETH_L2_PAYLOAD,\n\tRTE_ETH_L3_PAYLOAD,\n\tRTE_ETH_L4_PAYLOAD,\n\tRTE_ETH_PAYLOAD_MAX = 8,\n};\n\n/**\n * A structure used to select bytes extracted from the protocol layers to\n * flexible payload for filter\n */\nstruct rte_eth_flex_payload_cfg {\n\tenum rte_eth_payload_type type; /**< Payload type */\n\tuint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN];\n\t/**< Offset in bytes from the beginning of packet's payload\n\t src_offset[i] indicates the flexbyte i's offset in original\n\t packet payload. This value should be less than\n\t flex_payload_limit in struct rte_eth_fdir_info.*/\n};\n\n/**\n * A structure used to define FDIR masks for flexible payload\n * for each flow type\n */\nstruct rte_eth_fdir_flex_mask {\n\tuint16_t flow_type;\n\tuint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN];\n\t/**< Mask for the whole flexible payload */\n};\n\n/**\n * A structure used to define all flexible payload related setting\n * include flexpay load and flex mask\n */\nstruct rte_eth_fdir_flex_conf {\n\tuint16_t nb_payloads; /**< The number of following payload cfg */\n\tuint16_t nb_flexmasks; /**< The number of following mask */\n\tstruct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX];\n\t/**< Flex payload configuration for each payload type */\n\tstruct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX];\n\t/**< Flex mask configuration for each flow type */\n};\n\n/**\n * Flow Director setting modes: none, signature or perfect.\n */\nenum rte_fdir_mode {\n\tRTE_FDIR_MODE_NONE = 0, /**< Disable FDIR support. */\n\tRTE_FDIR_MODE_SIGNATURE, /**< Enable FDIR signature filter mode. */\n\tRTE_FDIR_MODE_PERFECT, /**< Enable FDIR perfect filter mode. */\n};\n\n#define UINT32_BIT (CHAR_BIT * sizeof(uint32_t))\n#define RTE_FLOW_MASK_ARRAY_SIZE \\\n\t(RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT)\n\n/**\n * A structure used to get the information of flow director filter.\n * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_INFO operation.\n * It includes the mode, flexible payload configuration information,\n * capabilities and supported flow types, flexible payload characters.\n * It can be gotten to help taking specific configurations per device.\n */\nstruct rte_eth_fdir_info {\n\tenum rte_fdir_mode mode; /**< Flow director mode */\n\tstruct rte_eth_fdir_masks mask;\n\t/** Flex payload configuration information */\n\tstruct rte_eth_fdir_flex_conf flex_conf;\n\tuint32_t guarant_spc; /**< Guaranteed spaces.*/\n\tuint32_t best_spc; /**< Best effort spaces.*/\n\t/** Bit mask for every supported flow type. */\n\tuint32_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];\n\tuint32_t max_flexpayload; /**< Total flex payload in bytes. */\n\t/** Flexible payload unit in bytes. Size and alignments of all flex\n\t payload segments should be multiplies of this value. */\n\tuint32_t flex_payload_unit;\n\t/** Max number of flexible payload continuous segments.\n\t Each segment should be a multiple of flex_payload_unit.*/\n\tuint32_t max_flex_payload_segment_num;\n\t/** Maximum src_offset in bytes allowed. It indicates that\n\t src_offset[i] in struct rte_eth_flex_payload_cfg should be less\n\t than this value. */\n\tuint16_t flex_payload_limit;\n\t/** Flex bitmask unit in bytes. Size of flex bitmasks should be a\n\t multiply of this value. */\n\tuint32_t flex_bitmask_unit;\n\t/** Max supported size of flex bitmasks in flex_bitmask_unit */\n\tuint32_t max_flex_bitmask_num;\n};\n\n/**\n * A structure used to define the statistics of flow director.\n * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_STATS operation.\n */\nstruct rte_eth_fdir_stats {\n\tuint32_t collision; /**< Number of filters with collision. */\n\tuint32_t free; /**< Number of free filters. */\n\tuint32_t maxhash;\n\t/**< The lookup hash value of the added filter that updated the value\n\t of the MAXLEN field */\n\tuint32_t maxlen; /**< Longest linked list of filters. */\n\tuint64_t add; /**< Number of added filters. */\n\tuint64_t remove; /**< Number of removed filters. */\n\tuint64_t f_add; /**< Number of failed added filters. */\n\tuint64_t f_remove; /**< Number of failed removed filters. */\n\tuint32_t guarant_cnt; /**< Number of filters in guaranteed spaces. */\n\tuint32_t best_cnt; /**< Number of filters in best effort spaces. */\n};\n\n/**\n * Hash filter information types.\n * - RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT is for getting/setting the\n * information/configuration of 'symmetric hash enable' per port.\n * - RTE_ETH_HASH_FILTER_GLOBAL_CONFIG is for getting/setting the global\n * configurations of hash filters. Those global configurations are valid\n * for all ports of the same NIC.\n */\nenum rte_eth_hash_filter_info_type {\n\tRTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,\n\t/** Symmetric hash enable per port */\n\tRTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT,\n\t/** Configure globally for hash filter */\n\tRTE_ETH_HASH_FILTER_GLOBAL_CONFIG,\n\tRTE_ETH_HASH_FILTER_INFO_TYPE_MAX,\n};\n\n/**\n * Hash function types.\n */\nenum rte_eth_hash_function {\n\tRTE_ETH_HASH_FUNCTION_DEFAULT = 0,\n\tRTE_ETH_HASH_FUNCTION_TOEPLITZ, /**< Toeplitz */\n\tRTE_ETH_HASH_FUNCTION_SIMPLE_XOR, /**< Simple XOR */\n\tRTE_ETH_HASH_FUNCTION_MAX,\n};\n\n#define RTE_SYM_HASH_MASK_ARRAY_SIZE \\\n\t(RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT)\n/**\n * A structure used to set or get global hash function configurations which\n * include symmetric hash enable per flow type and hash function type.\n * Each bit in sym_hash_enable_mask[] indicates if the symmetric hash of the\n * coresponding flow type is enabled or not.\n * Each bit in valid_bit_mask[] indicates if the corresponding bit in\n * sym_hash_enable_mask[] is valid or not. For the configurations gotten, it\n * also means if the flow type is supported by hardware or not.\n */\nstruct rte_eth_hash_global_conf {\n\tenum rte_eth_hash_function hash_func; /**< Hash function type */\n\t/** Bit mask for symmetric hash enable per flow type */\n\tuint32_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];\n\t/** Bit mask indicates if the corresponding bit is valid */\n\tuint32_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];\n};\n\n/**\n * A structure used to set or get hash filter information, to support filter\n * type of 'RTE_ETH_FILTER_HASH' and its operations.\n */\nstruct rte_eth_hash_filter_info {\n\tenum rte_eth_hash_filter_info_type info_type; /**< Information type */\n\t/** Details of hash filter information */\n\tunion {\n\t\t/** For RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT */\n\t\tuint8_t enable;\n\t\t/** Global configurations of hash filter */\n\t\tstruct rte_eth_hash_global_conf global_conf;\n\t} info;\n};\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_ETH_CTRL_H_ */\n" }, { "path": "lib/librte_ether/rte_ethdev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_ether.h\"\n#include \"rte_ethdev.h\"\n\n#ifdef RTE_LIBRTE_ETHDEV_DEBUG\n#define PMD_DEBUG_TRACE(fmt, args...) do { \\\n\t\tRTE_LOG(ERR, PMD, \"%s: \" fmt, __func__, ## args); \\\n\t} while (0)\n#else\n#define PMD_DEBUG_TRACE(fmt, args...)\n#endif\n\n/* Macros for checking for restricting functions to primary instance only */\n#define PROC_PRIMARY_OR_ERR_RET(retval) do { \\\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) { \\\n\t\tPMD_DEBUG_TRACE(\"Cannot run in secondary processes\\n\"); \\\n\t\treturn (retval); \\\n\t} \\\n} while (0)\n\n#define PROC_PRIMARY_OR_RET() do { \\\n\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) { \\\n\t\tPMD_DEBUG_TRACE(\"Cannot run in secondary processes\\n\"); \\\n\t\treturn; \\\n\t} \\\n} while (0)\n\n/* Macros to check for invalid function pointers in dev_ops structure */\n#define FUNC_PTR_OR_ERR_RET(func, retval) do { \\\n\tif ((func) == NULL) { \\\n\t\tPMD_DEBUG_TRACE(\"Function not supported\\n\"); \\\n\t\treturn (retval); \\\n\t} \\\n} while (0)\n\n#define FUNC_PTR_OR_RET(func) do { \\\n\tif ((func) == NULL) { \\\n\t\tPMD_DEBUG_TRACE(\"Function not supported\\n\"); \\\n\t\treturn; \\\n\t} \\\n} while (0)\n\n/* Macros to check for valid port */\n#define VALID_PORTID_OR_ERR_RET(port_id, retval) do {\t\t\\\n\tif (!rte_eth_dev_is_valid_port(port_id)) {\t\t\\\n\t\tPMD_DEBUG_TRACE(\"Invalid port_id=%d\\n\", port_id); \\\n\t\treturn retval;\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\\\n} while (0)\n\n#define VALID_PORTID_OR_RET(port_id) do {\t\t\t\\\n\tif (!rte_eth_dev_is_valid_port(port_id)) {\t\t\\\n\t\tPMD_DEBUG_TRACE(\"Invalid port_id=%d\\n\", port_id); \\\n\t\treturn;\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\\\n} while (0)\n\nstatic const char *MZ_RTE_ETH_DEV_DATA = \"rte_eth_dev_data\";\nstruct rte_eth_dev rte_eth_devices[RTE_MAX_ETHPORTS];\nstatic struct rte_eth_dev_data *rte_eth_dev_data;\nstatic uint8_t nb_ports;\n\n/* spinlock for eth device callbacks */\nstatic rte_spinlock_t rte_eth_dev_cb_lock = RTE_SPINLOCK_INITIALIZER;\n\n/* store statistics names and its offset in stats structure */\nstruct rte_eth_xstats_name_off {\n\tchar name[RTE_ETH_XSTATS_NAME_SIZE];\n\tunsigned offset;\n};\n\nstatic const struct rte_eth_xstats_name_off rte_stats_strings[] = {\n\t{\"rx_packets\", offsetof(struct rte_eth_stats, ipackets)},\n\t{\"tx_packets\", offsetof(struct rte_eth_stats, opackets)},\n\t{\"rx_bytes\", offsetof(struct rte_eth_stats, ibytes)},\n\t{\"tx_bytes\", offsetof(struct rte_eth_stats, obytes)},\n\t{\"tx_errors\", offsetof(struct rte_eth_stats, oerrors)},\n\t{\"rx_errors\", offsetof(struct rte_eth_stats, ierrors)},\n\t{\"alloc_rx_buff_failed\", offsetof(struct rte_eth_stats, rx_nombuf)},\n};\n#define RTE_NB_STATS (sizeof(rte_stats_strings) / sizeof(rte_stats_strings[0]))\n\nstatic const struct rte_eth_xstats_name_off rte_rxq_stats_strings[] = {\n\t{\"rx_packets\", offsetof(struct rte_eth_stats, q_ipackets)},\n\t{\"rx_bytes\", offsetof(struct rte_eth_stats, q_ibytes)},\n};\n#define RTE_NB_RXQ_STATS (sizeof(rte_rxq_stats_strings) /\t\\\n\t\tsizeof(rte_rxq_stats_strings[0]))\n\nstatic const struct rte_eth_xstats_name_off rte_txq_stats_strings[] = {\n\t{\"tx_packets\", offsetof(struct rte_eth_stats, q_opackets)},\n\t{\"tx_bytes\", offsetof(struct rte_eth_stats, q_obytes)},\n\t{\"tx_errors\", offsetof(struct rte_eth_stats, q_errors)},\n};\n#define RTE_NB_TXQ_STATS (sizeof(rte_txq_stats_strings) /\t\\\n\t\tsizeof(rte_txq_stats_strings[0]))\n\n\n/**\n * The user application callback description.\n *\n * It contains callback address to be registered by user application,\n * the pointer to the parameters for callback, and the event type.\n */\nstruct rte_eth_dev_callback {\n\tTAILQ_ENTRY(rte_eth_dev_callback) next; /**< Callbacks list */\n\trte_eth_dev_cb_fn cb_fn; /**< Callback address */\n\tvoid *cb_arg; /**< Parameter for callback */\n\tenum rte_eth_event_type event; /**< Interrupt event type */\n\tuint32_t active; /**< Callback is executing */\n};\n\nenum {\n\tSTAT_QMAP_TX = 0,\n\tSTAT_QMAP_RX\n};\n\nenum {\n\tDEV_DETACHED = 0,\n\tDEV_ATTACHED\n};\n\nstatic void\nrte_eth_dev_data_alloc(void)\n{\n\tconst unsigned flags = 0;\n\tconst struct rte_memzone *mz;\n\n\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n\t\tmz = rte_memzone_reserve(MZ_RTE_ETH_DEV_DATA,\n\t\t\t\tRTE_MAX_ETHPORTS * sizeof(*rte_eth_dev_data),\n\t\t\t\trte_socket_id(), flags);\n\t} else\n\t\tmz = rte_memzone_lookup(MZ_RTE_ETH_DEV_DATA);\n\tif (mz == NULL)\n\t\trte_panic(\"Cannot allocate memzone for ethernet port data\\n\");\n\n\trte_eth_dev_data = mz->addr;\n\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n\t\tmemset(rte_eth_dev_data, 0,\n\t\t\t\tRTE_MAX_ETHPORTS * sizeof(*rte_eth_dev_data));\n}\n\nstruct rte_eth_dev *\nrte_eth_dev_allocated(const char *name)\n{\n\tunsigned i;\n\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif ((rte_eth_devices[i].attached == DEV_ATTACHED) &&\n\t\t strcmp(rte_eth_devices[i].data->name, name) == 0)\n\t\t\treturn &rte_eth_devices[i];\n\t}\n\treturn NULL;\n}\n\nstatic uint8_t\nrte_eth_dev_find_free_port(void)\n{\n\tunsigned i;\n\n\tfor (i = 0; i < RTE_MAX_ETHPORTS; i++) {\n\t\tif (rte_eth_devices[i].attached == DEV_DETACHED)\n\t\t\treturn i;\n\t}\n\treturn RTE_MAX_ETHPORTS;\n}\n\nstruct rte_eth_dev *\nrte_eth_dev_allocate(const char *name, enum rte_eth_dev_type type)\n{\n\tuint8_t port_id;\n\tstruct rte_eth_dev *eth_dev;\n\n\tport_id = rte_eth_dev_find_free_port();\n\tif (port_id == RTE_MAX_ETHPORTS) {\n\t\tPMD_DEBUG_TRACE(\"Reached maximum number of Ethernet ports\\n\");\n\t\treturn NULL;\n\t}\n\n\tif (rte_eth_dev_data == NULL)\n\t\trte_eth_dev_data_alloc();\n\n\tif (rte_eth_dev_allocated(name) != NULL) {\n\t\tPMD_DEBUG_TRACE(\"Ethernet Device with name %s already allocated!\\n\",\n\t\t\t\tname);\n\t\treturn NULL;\n\t}\n\n\teth_dev = &rte_eth_devices[port_id];\n\teth_dev->data = &rte_eth_dev_data[port_id];\n\tsnprintf(eth_dev->data->name, sizeof(eth_dev->data->name), \"%s\", name);\n\teth_dev->data->port_id = port_id;\n\teth_dev->attached = DEV_ATTACHED;\n\teth_dev->dev_type = type;\n\tnb_ports++;\n\treturn eth_dev;\n}\n\nstatic int\nrte_eth_dev_create_unique_device_name(char *name, size_t size,\n\t\tstruct rte_pci_device *pci_dev)\n{\n\tint ret;\n\n\tif ((name == NULL) || (pci_dev == NULL))\n\t\treturn -EINVAL;\n\n\tret = snprintf(name, size, \"%d:%d.%d\",\n\t\t\tpci_dev->addr.bus, pci_dev->addr.devid,\n\t\t\tpci_dev->addr.function);\n\tif (ret < 0)\n\t\treturn ret;\n\treturn 0;\n}\n\nint\nrte_eth_dev_release_port(struct rte_eth_dev *eth_dev)\n{\n\tif (eth_dev == NULL)\n\t\treturn -EINVAL;\n\n\teth_dev->attached = DEV_DETACHED;\n\tnb_ports--;\n\treturn 0;\n}\n\nstatic int\nrte_eth_dev_init(struct rte_pci_driver *pci_drv,\n\t\t struct rte_pci_device *pci_dev)\n{\n\tstruct eth_driver *eth_drv;\n\tstruct rte_eth_dev *eth_dev;\n\tchar ethdev_name[RTE_ETH_NAME_MAX_LEN];\n\n\tint diag;\n\n\teth_drv = (struct eth_driver *)pci_drv;\n\n\t/* Create unique Ethernet device name using PCI address */\n\trte_eth_dev_create_unique_device_name(ethdev_name,\n\t\t\tsizeof(ethdev_name), pci_dev);\n\n\teth_dev = rte_eth_dev_allocate(ethdev_name, RTE_ETH_DEV_PCI);\n\tif (eth_dev == NULL)\n\t\treturn -ENOMEM;\n\n\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n\t\teth_dev->data->dev_private = rte_zmalloc(\"ethdev private structure\",\n\t\t\t\t eth_drv->dev_private_size,\n\t\t\t\t RTE_CACHE_LINE_SIZE);\n\t\tif (eth_dev->data->dev_private == NULL)\n\t\t\trte_panic(\"Cannot allocate memzone for private port data\\n\");\n\t}\n\teth_dev->pci_dev = pci_dev;\n\teth_dev->driver = eth_drv;\n\teth_dev->data->rx_mbuf_alloc_failed = 0;\n\n\t/* init user callbacks */\n\tTAILQ_INIT(&(eth_dev->link_intr_cbs));\n\n\t/*\n\t * Set the default MTU.\n\t */\n\teth_dev->data->mtu = ETHER_MTU;\n\n\t/* Invoke PMD device initialization function */\n\tdiag = (*eth_drv->eth_dev_init)(eth_dev);\n\tif (diag == 0)\n\t\treturn 0;\n\n\tPMD_DEBUG_TRACE(\"driver %s: eth_dev_init(vendor_id=0x%u device_id=0x%x) failed\\n\",\n\t\t\tpci_drv->name,\n\t\t\t(unsigned) pci_dev->id.vendor_id,\n\t\t\t(unsigned) pci_dev->id.device_id);\n\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n\t\trte_free(eth_dev->data->dev_private);\n\trte_eth_dev_release_port(eth_dev);\n\treturn diag;\n}\n\nstatic int\nrte_eth_dev_uninit(struct rte_pci_device *pci_dev)\n{\n\tconst struct eth_driver *eth_drv;\n\tstruct rte_eth_dev *eth_dev;\n\tchar ethdev_name[RTE_ETH_NAME_MAX_LEN];\n\tint ret;\n\n\tif (pci_dev == NULL)\n\t\treturn -EINVAL;\n\n\t/* Create unique Ethernet device name using PCI address */\n\trte_eth_dev_create_unique_device_name(ethdev_name,\n\t\t\tsizeof(ethdev_name), pci_dev);\n\n\teth_dev = rte_eth_dev_allocated(ethdev_name);\n\tif (eth_dev == NULL)\n\t\treturn -ENODEV;\n\n\teth_drv = (const struct eth_driver *)pci_dev->driver;\n\n\t/* Invoke PMD device uninit function */\n\tif (*eth_drv->eth_dev_uninit) {\n\t\tret = (*eth_drv->eth_dev_uninit)(eth_dev);\n\t\tif (ret)\n\t\t\treturn ret;\n\t}\n\n\t/* free ether device */\n\trte_eth_dev_release_port(eth_dev);\n\n\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n\t\trte_free(eth_dev->data->dev_private);\n\n\teth_dev->pci_dev = NULL;\n\teth_dev->driver = NULL;\n\teth_dev->data = NULL;\n\n\treturn 0;\n}\n\n/**\n * Register an Ethernet [Poll Mode] driver.\n *\n * Function invoked by the initialization function of an Ethernet driver\n * to simultaneously register itself as a PCI driver and as an Ethernet\n * Poll Mode Driver.\n * Invokes the rte_eal_pci_register() function to register the *pci_drv*\n * structure embedded in the *eth_drv* structure, after having stored the\n * address of the rte_eth_dev_init() function in the *devinit* field of\n * the *pci_drv* structure.\n * During the PCI probing phase, the rte_eth_dev_init() function is\n * invoked for each PCI [Ethernet device] matching the embedded PCI\n * identifiers provided by the driver.\n */\nvoid\nrte_eth_driver_register(struct eth_driver *eth_drv)\n{\n\teth_drv->pci_drv.devinit = rte_eth_dev_init;\n\teth_drv->pci_drv.devuninit = rte_eth_dev_uninit;\n\trte_eal_pci_register(ð_drv->pci_drv);\n}\n\nint\nrte_eth_dev_is_valid_port(uint8_t port_id)\n{\n\tif (port_id >= RTE_MAX_ETHPORTS ||\n\t rte_eth_devices[port_id].attached != DEV_ATTACHED)\n\t\treturn 0;\n\telse\n\t\treturn 1;\n}\n\nint\nrte_eth_dev_socket_id(uint8_t port_id)\n{\n\tif (!rte_eth_dev_is_valid_port(port_id))\n\t\treturn -1;\n\treturn rte_eth_devices[port_id].pci_dev->numa_node;\n}\n\nuint8_t\nrte_eth_dev_count(void)\n{\n\treturn nb_ports;\n}\n\nstatic enum rte_eth_dev_type\nrte_eth_dev_get_device_type(uint8_t port_id)\n{\n\tif (!rte_eth_dev_is_valid_port(port_id))\n\t\treturn RTE_ETH_DEV_UNKNOWN;\n\treturn rte_eth_devices[port_id].dev_type;\n}\n\nstatic int\nrte_eth_dev_save(struct rte_eth_dev *devs, size_t size)\n{\n\tif ((devs == NULL) ||\n\t (size != sizeof(struct rte_eth_dev) * RTE_MAX_ETHPORTS))\n\t\treturn -EINVAL;\n\n\t/* save current rte_eth_devices */\n\tmemcpy(devs, rte_eth_devices, size);\n\treturn 0;\n}\n\nstatic int\nrte_eth_dev_get_changed_port(struct rte_eth_dev *devs, uint8_t *port_id)\n{\n\tif ((devs == NULL) || (port_id == NULL))\n\t\treturn -EINVAL;\n\n\t/* check which port was attached or detached */\n\tfor (*port_id = 0; *port_id < RTE_MAX_ETHPORTS; (*port_id)++, devs++) {\n\t\tif (rte_eth_devices[*port_id].attached ^ devs->attached)\n\t\t\treturn 0;\n\t}\n\treturn -ENODEV;\n}\n\nstatic int\nrte_eth_dev_get_addr_by_port(uint8_t port_id, struct rte_pci_addr *addr)\n{\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tif (addr == NULL) {\n\t\tPMD_DEBUG_TRACE(\"Null pointer is specified\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t*addr = rte_eth_devices[port_id].pci_dev->addr;\n\treturn 0;\n}\n\nstatic int\nrte_eth_dev_get_name_by_port(uint8_t port_id, char *name)\n{\n\tchar *tmp;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tif (name == NULL) {\n\t\tPMD_DEBUG_TRACE(\"Null pointer is specified\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* shouldn't check 'rte_eth_devices[i].data',\n\t * because it might be overwritten by VDEV PMD */\n\ttmp = rte_eth_dev_data[port_id].name;\n\tstrcpy(name, tmp);\n\treturn 0;\n}\n\nstatic int\nrte_eth_dev_is_detachable(uint8_t port_id)\n{\n\tuint32_t drv_flags;\n\n\tif (!rte_eth_dev_is_valid_port(port_id)) {\n\t\tPMD_DEBUG_TRACE(\"Invalid port_id=%d\\n\", port_id);\n\t\treturn -EINVAL;\n\t}\n\n\tif (rte_eth_devices[port_id].dev_type == RTE_ETH_DEV_PCI) {\n\t\tswitch (rte_eth_devices[port_id].pci_dev->kdrv) {\n\t\tcase RTE_KDRV_IGB_UIO:\n\t\tcase RTE_KDRV_UIO_GENERIC:\n\t\tcase RTE_KDRV_NIC_UIO:\n\t\t\tbreak;\n\t\tcase RTE_KDRV_VFIO:\n\t\tdefault:\n\t\t\treturn -ENOTSUP;\n\t\t}\n\t}\n\n\tdrv_flags = rte_eth_devices[port_id].driver->pci_drv.drv_flags;\n\treturn !(drv_flags & RTE_PCI_DRV_DETACHABLE);\n}\n\n/* attach the new physical device, then store port_id of the device */\nstatic int\nrte_eth_dev_attach_pdev(struct rte_pci_addr *addr, uint8_t *port_id)\n{\n\tuint8_t new_port_id;\n\tstruct rte_eth_dev devs[RTE_MAX_ETHPORTS];\n\n\tif ((addr == NULL) || (port_id == NULL))\n\t\tgoto err;\n\n\t/* save current port status */\n\tif (rte_eth_dev_save(devs, sizeof(devs)))\n\t\tgoto err;\n\t/* re-construct pci_device_list */\n\tif (rte_eal_pci_scan())\n\t\tgoto err;\n\t/* invoke probe func of the driver can handle the new device.\n\t * TODO:\n\t * rte_eal_pci_probe_one() should return port_id.\n\t * And rte_eth_dev_save() and rte_eth_dev_get_changed_port()\n\t * should be removed. */\n\tif (rte_eal_pci_probe_one(addr))\n\t\tgoto err;\n\t/* get port_id enabled by above procedures */\n\tif (rte_eth_dev_get_changed_port(devs, &new_port_id))\n\t\tgoto err;\n\n\t*port_id = new_port_id;\n\treturn 0;\nerr:\n\tRTE_LOG(ERR, EAL, \"Driver, cannot attach the device\\n\");\n\treturn -1;\n}\n\n/* detach the new physical device, then store pci_addr of the device */\nstatic int\nrte_eth_dev_detach_pdev(uint8_t port_id, struct rte_pci_addr *addr)\n{\n\tstruct rte_pci_addr freed_addr;\n\tstruct rte_pci_addr vp;\n\n\tif (addr == NULL)\n\t\tgoto err;\n\n\t/* check whether the driver supports detach feature, or not */\n\tif (rte_eth_dev_is_detachable(port_id))\n\t\tgoto err;\n\n\t/* get pci address by port id */\n\tif (rte_eth_dev_get_addr_by_port(port_id, &freed_addr))\n\t\tgoto err;\n\n\t/* Zeroed pci addr means the port comes from virtual device */\n\tvp.domain = vp.bus = vp.devid = vp.function = 0;\n\tif (rte_eal_compare_pci_addr(&vp, &freed_addr) == 0)\n\t\tgoto err;\n\n\t/* invoke devuninit func of the pci driver,\n\t * also remove the device from pci_device_list */\n\tif (rte_eal_pci_detach(&freed_addr))\n\t\tgoto err;\n\n\t*addr = freed_addr;\n\treturn 0;\nerr:\n\tRTE_LOG(ERR, EAL, \"Driver, cannot detach the device\\n\");\n\treturn -1;\n}\n\n/* attach the new virtual device, then store port_id of the device */\nstatic int\nrte_eth_dev_attach_vdev(const char *vdevargs, uint8_t *port_id)\n{\n\tchar *name = NULL, *args = NULL;\n\tuint8_t new_port_id;\n\tstruct rte_eth_dev devs[RTE_MAX_ETHPORTS];\n\tint ret = -1;\n\n\tif ((vdevargs == NULL) || (port_id == NULL))\n\t\tgoto end;\n\n\t/* parse vdevargs, then retrieve device name and args */\n\tif (rte_eal_parse_devargs_str(vdevargs, &name, &args))\n\t\tgoto end;\n\n\t/* save current port status */\n\tif (rte_eth_dev_save(devs, sizeof(devs)))\n\t\tgoto end;\n\t/* walk around dev_driver_list to find the driver of the device,\n\t * then invoke probe function o the driver.\n\t * TODO:\n\t * rte_eal_vdev_init() should return port_id,\n\t * And rte_eth_dev_save() and rte_eth_dev_get_changed_port()\n\t * should be removed. */\n\tif (rte_eal_vdev_init(name, args))\n\t\tgoto end;\n\t/* get port_id enabled by above procedures */\n\tif (rte_eth_dev_get_changed_port(devs, &new_port_id))\n\t\tgoto end;\n\tret = 0;\n\t*port_id = new_port_id;\nend:\n\tif (name)\n\t\tfree(name);\n\tif (args)\n\t\tfree(args);\n\n\tif (ret < 0)\n\t\tRTE_LOG(ERR, EAL, \"Driver, cannot attach the device\\n\");\n\treturn ret;\n}\n\n/* detach the new virtual device, then store the name of the device */\nstatic int\nrte_eth_dev_detach_vdev(uint8_t port_id, char *vdevname)\n{\n\tchar name[RTE_ETH_NAME_MAX_LEN];\n\n\tif (vdevname == NULL)\n\t\tgoto err;\n\n\t/* check whether the driver supports detach feature, or not */\n\tif (rte_eth_dev_is_detachable(port_id))\n\t\tgoto err;\n\n\t/* get device name by port id */\n\tif (rte_eth_dev_get_name_by_port(port_id, name))\n\t\tgoto err;\n\t/* walk around dev_driver_list to find the driver of the device,\n\t * then invoke uninit function of the driver */\n\tif (rte_eal_vdev_uninit(name))\n\t\tgoto err;\n\n\tstrncpy(vdevname, name, sizeof(name));\n\treturn 0;\nerr:\n\tRTE_LOG(ERR, EAL, \"Driver, cannot detach the device\\n\");\n\treturn -1;\n}\n\n/* attach the new device, then store port_id of the device */\nint\nrte_eth_dev_attach(const char *devargs, uint8_t *port_id)\n{\n\tstruct rte_pci_addr addr;\n\n\tif ((devargs == NULL) || (port_id == NULL))\n\t\treturn -EINVAL;\n\n\tif (eal_parse_pci_DomBDF(devargs, &addr) == 0)\n\t\treturn rte_eth_dev_attach_pdev(&addr, port_id);\n\telse\n\t\treturn rte_eth_dev_attach_vdev(devargs, port_id);\n}\n\n/* detach the device, then store the name of the device */\nint\nrte_eth_dev_detach(uint8_t port_id, char *name)\n{\n\tstruct rte_pci_addr addr;\n\tint ret;\n\n\tif (name == NULL)\n\t\treturn -EINVAL;\n\n\tif (rte_eth_dev_get_device_type(port_id) == RTE_ETH_DEV_PCI) {\n\t\tret = rte_eth_dev_get_addr_by_port(port_id, &addr);\n\t\tif (ret < 0)\n\t\t\treturn ret;\n\n\t\tret = rte_eth_dev_detach_pdev(port_id, &addr);\n\t\tif (ret == 0)\n\t\t\tsnprintf(name, RTE_ETH_NAME_MAX_LEN,\n\t\t\t\t\"%04x:%02x:%02x.%d\",\n\t\t\t\taddr.domain, addr.bus,\n\t\t\t\taddr.devid, addr.function);\n\n\t\treturn ret;\n\t} else\n\t\treturn rte_eth_dev_detach_vdev(port_id, name);\n}\n\nstatic int\nrte_eth_dev_rx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues)\n{\n\tuint16_t old_nb_queues = dev->data->nb_rx_queues;\n\tvoid **rxq;\n\tunsigned i;\n\n\tif (dev->data->rx_queues == NULL) { /* first time configuration */\n\t\tdev->data->rx_queues = rte_zmalloc(\"ethdev->rx_queues\",\n\t\t\t\tsizeof(dev->data->rx_queues[0]) * nb_queues,\n\t\t\t\tRTE_CACHE_LINE_SIZE);\n\t\tif (dev->data->rx_queues == NULL) {\n\t\t\tdev->data->nb_rx_queues = 0;\n\t\t\treturn -(ENOMEM);\n\t\t}\n\t} else { /* re-configure */\n\t\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP);\n\n\t\trxq = dev->data->rx_queues;\n\n\t\tfor (i = nb_queues; i < old_nb_queues; i++)\n\t\t\t(*dev->dev_ops->rx_queue_release)(rxq[i]);\n\t\trxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,\n\t\t\t\tRTE_CACHE_LINE_SIZE);\n\t\tif (rxq == NULL)\n\t\t\treturn -(ENOMEM);\n\t\tif (nb_queues > old_nb_queues) {\n\t\t\tuint16_t new_qs = nb_queues - old_nb_queues;\n\n\t\t\tmemset(rxq + old_nb_queues, 0,\n\t\t\t\tsizeof(rxq[0]) * new_qs);\n\t\t}\n\n\t\tdev->data->rx_queues = rxq;\n\n\t}\n\tdev->data->nb_rx_queues = nb_queues;\n\treturn 0;\n}\n\nint\nrte_eth_dev_rx_queue_start(uint8_t port_id, uint16_t rx_queue_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\t/* This function is only safe when called from the primary process\n\t * in a multi-process setup*/\n\tPROC_PRIMARY_OR_ERR_RET(-E_RTE_SECONDARY);\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\tif (rx_queue_id >= dev->data->nb_rx_queues) {\n\t\tPMD_DEBUG_TRACE(\"Invalid RX queue_id=%d\\n\", rx_queue_id);\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_start, -ENOTSUP);\n\n\treturn dev->dev_ops->rx_queue_start(dev, rx_queue_id);\n\n}\n\nint\nrte_eth_dev_rx_queue_stop(uint8_t port_id, uint16_t rx_queue_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\t/* This function is only safe when called from the primary process\n\t * in a multi-process setup*/\n\tPROC_PRIMARY_OR_ERR_RET(-E_RTE_SECONDARY);\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\tif (rx_queue_id >= dev->data->nb_rx_queues) {\n\t\tPMD_DEBUG_TRACE(\"Invalid RX queue_id=%d\\n\", rx_queue_id);\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_stop, -ENOTSUP);\n\n\treturn dev->dev_ops->rx_queue_stop(dev, rx_queue_id);\n\n}\n\nint\nrte_eth_dev_tx_queue_start(uint8_t port_id, uint16_t tx_queue_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\t/* This function is only safe when called from the primary process\n\t * in a multi-process setup*/\n\tPROC_PRIMARY_OR_ERR_RET(-E_RTE_SECONDARY);\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\tif (tx_queue_id >= dev->data->nb_tx_queues) {\n\t\tPMD_DEBUG_TRACE(\"Invalid TX queue_id=%d\\n\", tx_queue_id);\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_start, -ENOTSUP);\n\n\treturn dev->dev_ops->tx_queue_start(dev, tx_queue_id);\n\n}\n\nint\nrte_eth_dev_tx_queue_stop(uint8_t port_id, uint16_t tx_queue_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\t/* This function is only safe when called from the primary process\n\t * in a multi-process setup*/\n\tPROC_PRIMARY_OR_ERR_RET(-E_RTE_SECONDARY);\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\tif (tx_queue_id >= dev->data->nb_tx_queues) {\n\t\tPMD_DEBUG_TRACE(\"Invalid TX queue_id=%d\\n\", tx_queue_id);\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_stop, -ENOTSUP);\n\n\treturn dev->dev_ops->tx_queue_stop(dev, tx_queue_id);\n\n}\n\nstatic int\nrte_eth_dev_tx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues)\n{\n\tuint16_t old_nb_queues = dev->data->nb_tx_queues;\n\tvoid **txq;\n\tunsigned i;\n\n\tif (dev->data->tx_queues == NULL) { /* first time configuration */\n\t\tdev->data->tx_queues = rte_zmalloc(\"ethdev->tx_queues\",\n\t\t\t\t\t\t sizeof(dev->data->tx_queues[0]) * nb_queues,\n\t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n\t\tif (dev->data->tx_queues == NULL) {\n\t\t\tdev->data->nb_tx_queues = 0;\n\t\t\treturn -(ENOMEM);\n\t\t}\n\t} else { /* re-configure */\n\t\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP);\n\n\t\ttxq = dev->data->tx_queues;\n\n\t\tfor (i = nb_queues; i < old_nb_queues; i++)\n\t\t\t(*dev->dev_ops->tx_queue_release)(txq[i]);\n\t\ttxq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,\n\t\t\t\t RTE_CACHE_LINE_SIZE);\n\t\tif (txq == NULL)\n\t\t\treturn -ENOMEM;\n\t\tif (nb_queues > old_nb_queues) {\n\t\t\tuint16_t new_qs = nb_queues - old_nb_queues;\n\n\t\t\tmemset(txq + old_nb_queues, 0,\n\t\t\t sizeof(txq[0]) * new_qs);\n\t\t}\n\n\t\tdev->data->tx_queues = txq;\n\n\t}\n\tdev->data->nb_tx_queues = nb_queues;\n\treturn 0;\n}\n\nstatic int\nrte_eth_dev_check_vf_rss_rxq_num(uint8_t port_id, uint16_t nb_rx_q)\n{\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\n\tswitch (nb_rx_q) {\n\tcase 1:\n\tcase 2:\n\t\tRTE_ETH_DEV_SRIOV(dev).active =\n\t\t\tETH_64_POOLS;\n\t\tbreak;\n\tcase 4:\n\t\tRTE_ETH_DEV_SRIOV(dev).active =\n\t\t\tETH_32_POOLS;\n\t\tbreak;\n\tdefault:\n\t\treturn -EINVAL;\n\t}\n\n\tRTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;\n\tRTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =\n\t\tdev->pci_dev->max_vfs * nb_rx_q;\n\n\treturn 0;\n}\n\nstatic int\nrte_eth_dev_check_mq_mode(uint8_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q,\n\t\t\t const struct rte_eth_conf *dev_conf)\n{\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\n\tif (RTE_ETH_DEV_SRIOV(dev).active != 0) {\n\t\t/* check multi-queue mode */\n\t\tif ((dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) ||\n\t\t (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB_RSS) ||\n\t\t (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB)) {\n\t\t\t/* SRIOV only works in VMDq enable mode */\n\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%\" PRIu8\n\t\t\t\t\t\" SRIOV active, \"\n\t\t\t\t\t\"wrong VMDQ mq_mode rx %u tx %u\\n\",\n\t\t\t\t\tport_id,\n\t\t\t\t\tdev_conf->rxmode.mq_mode,\n\t\t\t\t\tdev_conf->txmode.mq_mode);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tswitch (dev_conf->rxmode.mq_mode) {\n\t\tcase ETH_MQ_RX_VMDQ_DCB:\n\t\tcase ETH_MQ_RX_VMDQ_DCB_RSS:\n\t\t\t/* DCB/RSS VMDQ in SRIOV mode, not implement yet */\n\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%\" PRIu8\n\t\t\t\t\t\" SRIOV active, \"\n\t\t\t\t\t\"unsupported VMDQ mq_mode rx %u\\n\",\n\t\t\t\t\tport_id, dev_conf->rxmode.mq_mode);\n\t\t\treturn -EINVAL;\n\t\tcase ETH_MQ_RX_RSS:\n\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%\" PRIu8\n\t\t\t\t\t\" SRIOV active, \"\n\t\t\t\t\t\"Rx mq mode is changed from:\"\n\t\t\t\t\t\"mq_mode %u into VMDQ mq_mode %u\\n\",\n\t\t\t\t\tport_id,\n\t\t\t\t\tdev_conf->rxmode.mq_mode,\n\t\t\t\t\tdev->data->dev_conf.rxmode.mq_mode);\n\t\tcase ETH_MQ_RX_VMDQ_RSS:\n\t\t\tdev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;\n\t\t\tif (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)\n\t\t\t\tif (rte_eth_dev_check_vf_rss_rxq_num(port_id, nb_rx_q) != 0) {\n\t\t\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d\"\n\t\t\t\t\t\t\t\" SRIOV active, invalid queue\"\n\t\t\t\t\t\t\t\" number for VMDQ RSS, allowed\"\n\t\t\t\t\t\t\t\" value are 1, 2 or 4\\n\",\n\t\t\t\t\t\t\tport_id);\n\t\t\t\t\treturn -EINVAL;\n\t\t\t\t}\n\t\t\tbreak;\n\t\tdefault: /* ETH_MQ_RX_VMDQ_ONLY or ETH_MQ_RX_NONE */\n\t\t\t/* if nothing mq mode configure, use default scheme */\n\t\t\tdev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;\n\t\t\tif (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)\n\t\t\t\tRTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;\n\t\t\tbreak;\n\t\t}\n\n\t\tswitch (dev_conf->txmode.mq_mode) {\n\t\tcase ETH_MQ_TX_VMDQ_DCB:\n\t\t\t/* DCB VMDQ in SRIOV mode, not implement yet */\n\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%\" PRIu8\n\t\t\t\t\t\" SRIOV active, \"\n\t\t\t\t\t\"unsupported VMDQ mq_mode tx %u\\n\",\n\t\t\t\t\tport_id, dev_conf->txmode.mq_mode);\n\t\t\treturn -EINVAL;\n\t\tdefault: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */\n\t\t\t/* if nothing mq mode configure, use default scheme */\n\t\t\tdev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;\n\t\t\tbreak;\n\t\t}\n\n\t\t/* check valid queue number */\n\t\tif ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||\n\t\t (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {\n\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d SRIOV active, \"\n\t\t\t\t\t\"queue number must less equal to %d\\n\",\n\t\t\t\t\tport_id,\n\t\t\t\t\tRTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);\n\t\t\treturn -EINVAL;\n\t\t}\n\t} else {\n\t\t/* For vmdb+dcb mode check our configuration before we go further */\n\t\tif (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {\n\t\t\tconst struct rte_eth_vmdq_dcb_conf *conf;\n\n\t\t\tif (nb_rx_q != ETH_VMDQ_DCB_NUM_QUEUES) {\n\t\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d VMDQ+DCB, nb_rx_q \"\n\t\t\t\t\t\t\"!= %d\\n\",\n\t\t\t\t\t\tport_id, ETH_VMDQ_DCB_NUM_QUEUES);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t\tconf = &(dev_conf->rx_adv_conf.vmdq_dcb_conf);\n\t\t\tif (!(conf->nb_queue_pools == ETH_16_POOLS ||\n\t\t\t conf->nb_queue_pools == ETH_32_POOLS)) {\n\t\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d VMDQ+DCB selected, \"\n\t\t\t\t\t\t\"nb_queue_pools must be %d or %d\\n\",\n\t\t\t\t\t\tport_id, ETH_16_POOLS, ETH_32_POOLS);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t}\n\t\tif (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {\n\t\t\tconst struct rte_eth_vmdq_dcb_tx_conf *conf;\n\n\t\t\tif (nb_tx_q != ETH_VMDQ_DCB_NUM_QUEUES) {\n\t\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d VMDQ+DCB, nb_tx_q \"\n\t\t\t\t\t\t\"!= %d\\n\",\n\t\t\t\t\t\tport_id, ETH_VMDQ_DCB_NUM_QUEUES);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t\tconf = &(dev_conf->tx_adv_conf.vmdq_dcb_tx_conf);\n\t\t\tif (!(conf->nb_queue_pools == ETH_16_POOLS ||\n\t\t\t conf->nb_queue_pools == ETH_32_POOLS)) {\n\t\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d VMDQ+DCB selected, \"\n\t\t\t\t\t\t\"nb_queue_pools != %d or nb_queue_pools \"\n\t\t\t\t\t\t\"!= %d\\n\",\n\t\t\t\t\t\tport_id, ETH_16_POOLS, ETH_32_POOLS);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t}\n\n\t\t/* For DCB mode check our configuration before we go further */\n\t\tif (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {\n\t\t\tconst struct rte_eth_dcb_rx_conf *conf;\n\n\t\t\tif (nb_rx_q != ETH_DCB_NUM_QUEUES) {\n\t\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d DCB, nb_rx_q \"\n\t\t\t\t\t\t\"!= %d\\n\",\n\t\t\t\t\t\tport_id, ETH_DCB_NUM_QUEUES);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t\tconf = &(dev_conf->rx_adv_conf.dcb_rx_conf);\n\t\t\tif (!(conf->nb_tcs == ETH_4_TCS ||\n\t\t\t conf->nb_tcs == ETH_8_TCS)) {\n\t\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d DCB selected, \"\n\t\t\t\t\t\t\"nb_tcs != %d or nb_tcs \"\n\t\t\t\t\t\t\"!= %d\\n\",\n\t\t\t\t\t\tport_id, ETH_4_TCS, ETH_8_TCS);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t}\n\n\t\tif (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {\n\t\t\tconst struct rte_eth_dcb_tx_conf *conf;\n\n\t\t\tif (nb_tx_q != ETH_DCB_NUM_QUEUES) {\n\t\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d DCB, nb_tx_q \"\n\t\t\t\t\t\t\"!= %d\\n\",\n\t\t\t\t\t\tport_id, ETH_DCB_NUM_QUEUES);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t\tconf = &(dev_conf->tx_adv_conf.dcb_tx_conf);\n\t\t\tif (!(conf->nb_tcs == ETH_4_TCS ||\n\t\t\t conf->nb_tcs == ETH_8_TCS)) {\n\t\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d DCB selected, \"\n\t\t\t\t\t\t\"nb_tcs != %d or nb_tcs \"\n\t\t\t\t\t\t\"!= %d\\n\",\n\t\t\t\t\t\tport_id, ETH_4_TCS, ETH_8_TCS);\n\t\t\t\treturn -EINVAL;\n\t\t\t}\n\t\t}\n\t}\n\treturn 0;\n}\n\nint\nrte_eth_dev_configure(uint8_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q,\n\t\t const struct rte_eth_conf *dev_conf)\n{\n\tstruct rte_eth_dev *dev;\n\tstruct rte_eth_dev_info dev_info;\n\tint diag;\n\n\t/* This function is only safe when called from the primary process\n\t * in a multi-process setup*/\n\tPROC_PRIMARY_OR_ERR_RET(-E_RTE_SECONDARY);\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tif (nb_rx_q > RTE_MAX_QUEUES_PER_PORT) {\n\t\tPMD_DEBUG_TRACE(\n\t\t\t\"Number of RX queues requested (%u) is greater than max supported(%d)\\n\",\n\t\t\tnb_rx_q, RTE_MAX_QUEUES_PER_PORT);\n\t\treturn -EINVAL;\n\t}\n\n\tif (nb_tx_q > RTE_MAX_QUEUES_PER_PORT) {\n\t\tPMD_DEBUG_TRACE(\n\t\t\t\"Number of TX queues requested (%u) is greater than max supported(%d)\\n\",\n\t\t\tnb_tx_q, RTE_MAX_QUEUES_PER_PORT);\n\t\treturn -EINVAL;\n\t}\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP);\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_configure, -ENOTSUP);\n\n\tif (dev->data->dev_started) {\n\t\tPMD_DEBUG_TRACE(\n\t\t \"port %d must be stopped to allow configuration\\n\", port_id);\n\t\treturn -EBUSY;\n\t}\n\n\t/*\n\t * Check that the numbers of RX and TX queues are not greater\n\t * than the maximum number of RX and TX queues supported by the\n\t * configured device.\n\t */\n\t(*dev->dev_ops->dev_infos_get)(dev, &dev_info);\n\tif (nb_rx_q > dev_info.max_rx_queues) {\n\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d nb_rx_queues=%d > %d\\n\",\n\t\t\t\tport_id, nb_rx_q, dev_info.max_rx_queues);\n\t\treturn -EINVAL;\n\t}\n\tif (nb_rx_q == 0) {\n\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d nb_rx_q == 0\\n\", port_id);\n\t\treturn -EINVAL;\n\t}\n\n\tif (nb_tx_q > dev_info.max_tx_queues) {\n\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d nb_tx_queues=%d > %d\\n\",\n\t\t\t\tport_id, nb_tx_q, dev_info.max_tx_queues);\n\t\treturn -EINVAL;\n\t}\n\tif (nb_tx_q == 0) {\n\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d nb_tx_q == 0\\n\", port_id);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Copy the dev_conf parameter into the dev structure */\n\tmemcpy(&dev->data->dev_conf, dev_conf, sizeof(dev->data->dev_conf));\n\n\t/*\n\t * If link state interrupt is enabled, check that the\n\t * device supports it.\n\t */\n\tif (dev_conf->intr_conf.lsc == 1) {\n\t\tconst struct rte_pci_driver *pci_drv = &dev->driver->pci_drv;\n\n\t\tif (!(pci_drv->drv_flags & RTE_PCI_DRV_INTR_LSC)) {\n\t\t\tPMD_DEBUG_TRACE(\"driver %s does not support lsc\\n\",\n\t\t\t\t\tpci_drv->name);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\t/*\n\t * If jumbo frames are enabled, check that the maximum RX packet\n\t * length is supported by the configured device.\n\t */\n\tif (dev_conf->rxmode.jumbo_frame == 1) {\n\t\tif (dev_conf->rxmode.max_rx_pkt_len >\n\t\t dev_info.max_rx_pktlen) {\n\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d max_rx_pkt_len %u\"\n\t\t\t\t\" > max valid value %u\\n\",\n\t\t\t\tport_id,\n\t\t\t\t(unsigned)dev_conf->rxmode.max_rx_pkt_len,\n\t\t\t\t(unsigned)dev_info.max_rx_pktlen);\n\t\t\treturn -EINVAL;\n\t\t} else if (dev_conf->rxmode.max_rx_pkt_len < ETHER_MIN_LEN) {\n\t\t\tPMD_DEBUG_TRACE(\"ethdev port_id=%d max_rx_pkt_len %u\"\n\t\t\t\t\" < min valid value %u\\n\",\n\t\t\t\tport_id,\n\t\t\t\t(unsigned)dev_conf->rxmode.max_rx_pkt_len,\n\t\t\t\t(unsigned)ETHER_MIN_LEN);\n\t\t\treturn -EINVAL;\n\t\t}\n\t} else {\n\t\tif (dev_conf->rxmode.max_rx_pkt_len < ETHER_MIN_LEN ||\n\t\t\tdev_conf->rxmode.max_rx_pkt_len > ETHER_MAX_LEN)\n\t\t\t/* Use default value */\n\t\t\tdev->data->dev_conf.rxmode.max_rx_pkt_len =\n\t\t\t\t\t\t\tETHER_MAX_LEN;\n\t}\n\n\t/* multiple queue mode checking */\n\tdiag = rte_eth_dev_check_mq_mode(port_id, nb_rx_q, nb_tx_q, dev_conf);\n\tif (diag != 0) {\n\t\tPMD_DEBUG_TRACE(\"port%d rte_eth_dev_check_mq_mode = %d\\n\",\n\t\t\t\tport_id, diag);\n\t\treturn diag;\n\t}\n\n\t/*\n\t * Setup new number of RX/TX queues and reconfigure device.\n\t */\n\tdiag = rte_eth_dev_rx_queue_config(dev, nb_rx_q);\n\tif (diag != 0) {\n\t\tPMD_DEBUG_TRACE(\"port%d rte_eth_dev_rx_queue_config = %d\\n\",\n\t\t\t\tport_id, diag);\n\t\treturn diag;\n\t}\n\n\tdiag = rte_eth_dev_tx_queue_config(dev, nb_tx_q);\n\tif (diag != 0) {\n\t\tPMD_DEBUG_TRACE(\"port%d rte_eth_dev_tx_queue_config = %d\\n\",\n\t\t\t\tport_id, diag);\n\t\trte_eth_dev_rx_queue_config(dev, 0);\n\t\treturn diag;\n\t}\n\n\tdiag = (*dev->dev_ops->dev_configure)(dev);\n\tif (diag != 0) {\n\t\tPMD_DEBUG_TRACE(\"port%d dev_configure = %d\\n\",\n\t\t\t\tport_id, diag);\n\t\trte_eth_dev_rx_queue_config(dev, 0);\n\t\trte_eth_dev_tx_queue_config(dev, 0);\n\t\treturn diag;\n\t}\n\n\treturn 0;\n}\n\nstatic void\nrte_eth_dev_config_restore(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\tstruct rte_eth_dev_info dev_info;\n\tstruct ether_addr addr;\n\tuint16_t i;\n\tuint32_t pool = 0;\n\n\tdev = &rte_eth_devices[port_id];\n\n\trte_eth_dev_info_get(port_id, &dev_info);\n\n\tif (RTE_ETH_DEV_SRIOV(dev).active)\n\t\tpool = RTE_ETH_DEV_SRIOV(dev).def_vmdq_idx;\n\n\t/* replay MAC address configuration */\n\tfor (i = 0; i < dev_info.max_mac_addrs; i++) {\n\t\taddr = dev->data->mac_addrs[i];\n\n\t\t/* skip zero address */\n\t\tif (is_zero_ether_addr(&addr))\n\t\t\tcontinue;\n\n\t\t/* add address to the hardware */\n\t\tif (*dev->dev_ops->mac_addr_add &&\n\t\t\t(dev->data->mac_pool_sel[i] & (1ULL << pool)))\n\t\t\t(*dev->dev_ops->mac_addr_add)(dev, &addr, i, pool);\n\t\telse {\n\t\t\tPMD_DEBUG_TRACE(\"port %d: MAC address array not supported\\n\",\n\t\t\t\t\tport_id);\n\t\t\t/* exit the loop but not return an error */\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* replay promiscuous configuration */\n\tif (rte_eth_promiscuous_get(port_id) == 1)\n\t\trte_eth_promiscuous_enable(port_id);\n\telse if (rte_eth_promiscuous_get(port_id) == 0)\n\t\trte_eth_promiscuous_disable(port_id);\n\n\t/* replay all multicast configuration */\n\tif (rte_eth_allmulticast_get(port_id) == 1)\n\t\trte_eth_allmulticast_enable(port_id);\n\telse if (rte_eth_allmulticast_get(port_id) == 0)\n\t\trte_eth_allmulticast_disable(port_id);\n}\n\nint\nrte_eth_dev_start(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\tint diag;\n\n\t/* This function is only safe when called from the primary process\n\t * in a multi-process setup*/\n\tPROC_PRIMARY_OR_ERR_RET(-E_RTE_SECONDARY);\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_start, -ENOTSUP);\n\n\tif (dev->data->dev_started != 0) {\n\t\tPMD_DEBUG_TRACE(\"Device with port_id=%\" PRIu8\n\t\t\t\" already started\\n\",\n\t\t\tport_id);\n\t\treturn 0;\n\t}\n\n\tdiag = (*dev->dev_ops->dev_start)(dev);\n\tif (diag == 0)\n\t\tdev->data->dev_started = 1;\n\telse\n\t\treturn diag;\n\n\trte_eth_dev_config_restore(port_id);\n\n\tif (dev->data->dev_conf.intr_conf.lsc != 0) {\n\t\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP);\n\t\t(*dev->dev_ops->link_update)(dev, 0);\n\t}\n\treturn 0;\n}\n\nvoid\nrte_eth_dev_stop(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\t/* This function is only safe when called from the primary process\n\t * in a multi-process setup*/\n\tPROC_PRIMARY_OR_RET();\n\n\tVALID_PORTID_OR_RET(port_id);\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_RET(*dev->dev_ops->dev_stop);\n\n\tif (dev->data->dev_started == 0) {\n\t\tPMD_DEBUG_TRACE(\"Device with port_id=%\" PRIu8\n\t\t\t\" already stopped\\n\",\n\t\t\tport_id);\n\t\treturn;\n\t}\n\n\tdev->data->dev_started = 0;\n\t(*dev->dev_ops->dev_stop)(dev);\n}\n\nint\nrte_eth_dev_set_link_up(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\t/* This function is only safe when called from the primary process\n\t * in a multi-process setup*/\n\tPROC_PRIMARY_OR_ERR_RET(-E_RTE_SECONDARY);\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_up, -ENOTSUP);\n\treturn (*dev->dev_ops->dev_set_link_up)(dev);\n}\n\nint\nrte_eth_dev_set_link_down(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\t/* This function is only safe when called from the primary process\n\t * in a multi-process setup*/\n\tPROC_PRIMARY_OR_ERR_RET(-E_RTE_SECONDARY);\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_down, -ENOTSUP);\n\treturn (*dev->dev_ops->dev_set_link_down)(dev);\n}\n\nvoid\nrte_eth_dev_close(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\t/* This function is only safe when called from the primary process\n\t * in a multi-process setup*/\n\tPROC_PRIMARY_OR_RET();\n\n\tVALID_PORTID_OR_RET(port_id);\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_RET(*dev->dev_ops->dev_close);\n\tdev->data->dev_started = 0;\n\t(*dev->dev_ops->dev_close)(dev);\n\n\trte_free(dev->data->rx_queues);\n\tdev->data->rx_queues = NULL;\n\trte_free(dev->data->tx_queues);\n\tdev->data->tx_queues = NULL;\n}\n\nint\nrte_eth_rx_queue_setup(uint8_t port_id, uint16_t rx_queue_id,\n\t\t uint16_t nb_rx_desc, unsigned int socket_id,\n\t\t const struct rte_eth_rxconf *rx_conf,\n\t\t struct rte_mempool *mp)\n{\n\tint ret;\n\tuint32_t mbp_buf_size;\n\tstruct rte_eth_dev *dev;\n\tstruct rte_eth_dev_info dev_info;\n\n\t/* This function is only safe when called from the primary process\n\t * in a multi-process setup*/\n\tPROC_PRIMARY_OR_ERR_RET(-E_RTE_SECONDARY);\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\tif (rx_queue_id >= dev->data->nb_rx_queues) {\n\t\tPMD_DEBUG_TRACE(\"Invalid RX queue_id=%d\\n\", rx_queue_id);\n\t\treturn -EINVAL;\n\t}\n\n\tif (dev->data->dev_started) {\n\t\tPMD_DEBUG_TRACE(\n\t\t \"port %d must be stopped to allow configuration\\n\", port_id);\n\t\treturn -EBUSY;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP);\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_setup, -ENOTSUP);\n\n\t/*\n\t * Check the size of the mbuf data buffer.\n\t * This value must be provided in the private data of the memory pool.\n\t * First check that the memory pool has a valid private data.\n\t */\n\trte_eth_dev_info_get(port_id, &dev_info);\n\tif (mp->private_data_size < sizeof(struct rte_pktmbuf_pool_private)) {\n\t\tPMD_DEBUG_TRACE(\"%s private_data_size %d < %d\\n\",\n\t\t\t\tmp->name, (int) mp->private_data_size,\n\t\t\t\t(int) sizeof(struct rte_pktmbuf_pool_private));\n\t\treturn -ENOSPC;\n\t}\n\tmbp_buf_size = rte_pktmbuf_data_room_size(mp);\n\n\tif ((mbp_buf_size - RTE_PKTMBUF_HEADROOM) < dev_info.min_rx_bufsize) {\n\t\tPMD_DEBUG_TRACE(\"%s mbuf_data_room_size %d < %d \"\n\t\t\t\t\"(RTE_PKTMBUF_HEADROOM=%d + min_rx_bufsize(dev)\"\n\t\t\t\t\"=%d)\\n\",\n\t\t\t\tmp->name,\n\t\t\t\t(int)mbp_buf_size,\n\t\t\t\t(int)(RTE_PKTMBUF_HEADROOM +\n\t\t\t\t dev_info.min_rx_bufsize),\n\t\t\t\t(int)RTE_PKTMBUF_HEADROOM,\n\t\t\t\t(int)dev_info.min_rx_bufsize);\n\t\treturn -EINVAL;\n\t}\n\n\tif (rx_conf == NULL)\n\t\trx_conf = &dev_info.default_rxconf;\n\n\tret = (*dev->dev_ops->rx_queue_setup)(dev, rx_queue_id, nb_rx_desc,\n\t\t\t\t\t socket_id, rx_conf, mp);\n\tif (!ret) {\n\t\tif (!dev->data->min_rx_buf_size ||\n\t\t dev->data->min_rx_buf_size > mbp_buf_size)\n\t\t\tdev->data->min_rx_buf_size = mbp_buf_size;\n\t}\n\n\treturn ret;\n}\n\nint\nrte_eth_tx_queue_setup(uint8_t port_id, uint16_t tx_queue_id,\n\t\t uint16_t nb_tx_desc, unsigned int socket_id,\n\t\t const struct rte_eth_txconf *tx_conf)\n{\n\tstruct rte_eth_dev *dev;\n\tstruct rte_eth_dev_info dev_info;\n\n\t/* This function is only safe when called from the primary process\n\t * in a multi-process setup*/\n\tPROC_PRIMARY_OR_ERR_RET(-E_RTE_SECONDARY);\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\tif (tx_queue_id >= dev->data->nb_tx_queues) {\n\t\tPMD_DEBUG_TRACE(\"Invalid TX queue_id=%d\\n\", tx_queue_id);\n\t\treturn -EINVAL;\n\t}\n\n\tif (dev->data->dev_started) {\n\t\tPMD_DEBUG_TRACE(\n\t\t \"port %d must be stopped to allow configuration\\n\", port_id);\n\t\treturn -EBUSY;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP);\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_setup, -ENOTSUP);\n\n\trte_eth_dev_info_get(port_id, &dev_info);\n\n\tif (tx_conf == NULL)\n\t\ttx_conf = &dev_info.default_txconf;\n\n\treturn (*dev->dev_ops->tx_queue_setup)(dev, tx_queue_id, nb_tx_desc,\n\t\t\t\t\t socket_id, tx_conf);\n}\n\nvoid\nrte_eth_promiscuous_enable(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_RET(port_id);\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_RET(*dev->dev_ops->promiscuous_enable);\n\t(*dev->dev_ops->promiscuous_enable)(dev);\n\tdev->data->promiscuous = 1;\n}\n\nvoid\nrte_eth_promiscuous_disable(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_RET(port_id);\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_RET(*dev->dev_ops->promiscuous_disable);\n\tdev->data->promiscuous = 0;\n\t(*dev->dev_ops->promiscuous_disable)(dev);\n}\n\nint\nrte_eth_promiscuous_get(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\treturn dev->data->promiscuous;\n}\n\nvoid\nrte_eth_allmulticast_enable(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_RET(port_id);\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_RET(*dev->dev_ops->allmulticast_enable);\n\t(*dev->dev_ops->allmulticast_enable)(dev);\n\tdev->data->all_multicast = 1;\n}\n\nvoid\nrte_eth_allmulticast_disable(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_RET(port_id);\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_RET(*dev->dev_ops->allmulticast_disable);\n\tdev->data->all_multicast = 0;\n\t(*dev->dev_ops->allmulticast_disable)(dev);\n}\n\nint\nrte_eth_allmulticast_get(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\treturn dev->data->all_multicast;\n}\n\nstatic inline int\nrte_eth_dev_atomic_read_link_status(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_link *link)\n{\n\tstruct rte_eth_link *dst = link;\n\tstruct rte_eth_link *src = &(dev->data->dev_link);\n\n\tif (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,\n\t\t\t\t\t*(uint64_t *)src) == 0)\n\t\treturn -1;\n\n\treturn 0;\n}\n\nvoid\nrte_eth_link_get(uint8_t port_id, struct rte_eth_link *eth_link)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_RET(port_id);\n\tdev = &rte_eth_devices[port_id];\n\n\tif (dev->data->dev_conf.intr_conf.lsc != 0)\n\t\trte_eth_dev_atomic_read_link_status(dev, eth_link);\n\telse {\n\t\tFUNC_PTR_OR_RET(*dev->dev_ops->link_update);\n\t\t(*dev->dev_ops->link_update)(dev, 1);\n\t\t*eth_link = dev->data->dev_link;\n\t}\n}\n\nvoid\nrte_eth_link_get_nowait(uint8_t port_id, struct rte_eth_link *eth_link)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_RET(port_id);\n\tdev = &rte_eth_devices[port_id];\n\n\tif (dev->data->dev_conf.intr_conf.lsc != 0)\n\t\trte_eth_dev_atomic_read_link_status(dev, eth_link);\n\telse {\n\t\tFUNC_PTR_OR_RET(*dev->dev_ops->link_update);\n\t\t(*dev->dev_ops->link_update)(dev, 0);\n\t\t*eth_link = dev->data->dev_link;\n\t}\n}\n\nint\nrte_eth_stats_get(uint8_t port_id, struct rte_eth_stats *stats)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\tmemset(stats, 0, sizeof(*stats));\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_get, -ENOTSUP);\n\t(*dev->dev_ops->stats_get)(dev, stats);\n\tstats->rx_nombuf = dev->data->rx_mbuf_alloc_failed;\n\treturn 0;\n}\n\nvoid\nrte_eth_stats_reset(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_RET(port_id);\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_RET(*dev->dev_ops->stats_reset);\n\t(*dev->dev_ops->stats_reset)(dev);\n}\n\n/* retrieve ethdev extended statistics */\nint\nrte_eth_xstats_get(uint8_t port_id, struct rte_eth_xstats *xstats,\n\tunsigned n)\n{\n\tstruct rte_eth_stats eth_stats;\n\tstruct rte_eth_dev *dev;\n\tunsigned count = 0, i, q;\n\tsigned xcount = 0;\n\tuint64_t val, *stats_ptr;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\n\t/* Return generic statistics */\n\tcount = RTE_NB_STATS;\n\tcount += dev->data->nb_rx_queues * RTE_NB_RXQ_STATS;\n\tcount += dev->data->nb_tx_queues * RTE_NB_TXQ_STATS;\n\n\t/* implemented by the driver */\n\tif (dev->dev_ops->xstats_get != NULL) {\n\t\t/* Retrieve the xstats from the driver at the end of the\n\t\t * xstats struct.\n\t\t */\n\t\txcount = (*dev->dev_ops->xstats_get)(dev, &xstats[count],\n\t\t\t (n > count) ? n - count : 0);\n\n\t\tif (xcount < 0)\n\t\t\treturn xcount;\n\t}\n\n\tif (n < count + xcount)\n\t\treturn count + xcount;\n\n\t/* now fill the xstats structure */\n\tcount = 0;\n\trte_eth_stats_get(port_id, ð_stats);\n\n\t/* global stats */\n\tfor (i = 0; i < RTE_NB_STATS; i++) {\n\t\tstats_ptr = RTE_PTR_ADD(ð_stats,\n\t\t\t\t\trte_stats_strings[i].offset);\n\t\tval = *stats_ptr;\n\t\tsnprintf(xstats[count].name, sizeof(xstats[count].name),\n\t\t\t\"%s\", rte_stats_strings[i].name);\n\t\txstats[count++].value = val;\n\t}\n\n\t/* per-rxq stats */\n\tfor (q = 0; q < dev->data->nb_rx_queues; q++) {\n\t\tfor (i = 0; i < RTE_NB_RXQ_STATS; i++) {\n\t\t\tstats_ptr = RTE_PTR_ADD(ð_stats,\n\t\t\t\t\trte_rxq_stats_strings[i].offset +\n\t\t\t\t\tq * sizeof(uint64_t));\n\t\t\tval = *stats_ptr;\n\t\t\tsnprintf(xstats[count].name, sizeof(xstats[count].name),\n\t\t\t\t\"rx_queue_%u_%s\", q,\n\t\t\t\trte_rxq_stats_strings[i].name);\n\t\t\txstats[count++].value = val;\n\t\t}\n\t}\n\n\t/* per-txq stats */\n\tfor (q = 0; q < dev->data->nb_tx_queues; q++) {\n\t\tfor (i = 0; i < RTE_NB_TXQ_STATS; i++) {\n\t\t\tstats_ptr = RTE_PTR_ADD(ð_stats,\n\t\t\t\t\trte_txq_stats_strings[i].offset +\n\t\t\t\t\tq * sizeof(uint64_t));\n\t\t\tval = *stats_ptr;\n\t\t\tsnprintf(xstats[count].name, sizeof(xstats[count].name),\n\t\t\t\t\"tx_queue_%u_%s\", q,\n\t\t\t\trte_txq_stats_strings[i].name);\n\t\t\txstats[count++].value = val;\n\t\t}\n\t}\n\n\treturn count + xcount;\n}\n\n/* reset ethdev extended statistics */\nvoid\nrte_eth_xstats_reset(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_RET(port_id);\n\tdev = &rte_eth_devices[port_id];\n\n\t/* implemented by the driver */\n\tif (dev->dev_ops->xstats_reset != NULL) {\n\t\t(*dev->dev_ops->xstats_reset)(dev);\n\t\treturn;\n\t}\n\n\t/* fallback to default */\n\trte_eth_stats_reset(port_id);\n}\n\nstatic int\nset_queue_stats_mapping(uint8_t port_id, uint16_t queue_id, uint8_t stat_idx,\n\t\tuint8_t is_rx)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->queue_stats_mapping_set, -ENOTSUP);\n\treturn (*dev->dev_ops->queue_stats_mapping_set)\n\t\t\t(dev, queue_id, stat_idx, is_rx);\n}\n\n\nint\nrte_eth_dev_set_tx_queue_stats_mapping(uint8_t port_id, uint16_t tx_queue_id,\n\t\tuint8_t stat_idx)\n{\n\treturn set_queue_stats_mapping(port_id, tx_queue_id, stat_idx,\n\t\t\tSTAT_QMAP_TX);\n}\n\n\nint\nrte_eth_dev_set_rx_queue_stats_mapping(uint8_t port_id, uint16_t rx_queue_id,\n\t\tuint8_t stat_idx)\n{\n\treturn set_queue_stats_mapping(port_id, rx_queue_id, stat_idx,\n\t\t\tSTAT_QMAP_RX);\n}\n\n\nvoid\nrte_eth_dev_info_get(uint8_t port_id, struct rte_eth_dev_info *dev_info)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_RET(port_id);\n\tdev = &rte_eth_devices[port_id];\n\n\tmemset(dev_info, 0, sizeof(struct rte_eth_dev_info));\n\n\tFUNC_PTR_OR_RET(*dev->dev_ops->dev_infos_get);\n\t(*dev->dev_ops->dev_infos_get)(dev, dev_info);\n\tdev_info->pci_dev = dev->pci_dev;\n\tif (dev->driver)\n\t\tdev_info->driver_name = dev->driver->pci_drv.name;\n}\n\nvoid\nrte_eth_macaddr_get(uint8_t port_id, struct ether_addr *mac_addr)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_RET(port_id);\n\tdev = &rte_eth_devices[port_id];\n\tether_addr_copy(&dev->data->mac_addrs[0], mac_addr);\n}\n\n\nint\nrte_eth_dev_get_mtu(uint8_t port_id, uint16_t *mtu)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\t*mtu = dev->data->mtu;\n\treturn 0;\n}\n\nint\nrte_eth_dev_set_mtu(uint8_t port_id, uint16_t mtu)\n{\n\tint ret;\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->mtu_set, -ENOTSUP);\n\n\tret = (*dev->dev_ops->mtu_set)(dev, mtu);\n\tif (!ret)\n\t\tdev->data->mtu = mtu;\n\n\treturn ret;\n}\n\nint\nrte_eth_dev_vlan_filter(uint8_t port_id, uint16_t vlan_id, int on)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tif (!(dev->data->dev_conf.rxmode.hw_vlan_filter)) {\n\t\tPMD_DEBUG_TRACE(\"port %d: vlan-filtering disabled\\n\", port_id);\n\t\treturn -ENOSYS;\n\t}\n\n\tif (vlan_id > 4095) {\n\t\tPMD_DEBUG_TRACE(\"(port_id=%d) invalid vlan_id=%u > 4095\\n\",\n\t\t\t\tport_id, (unsigned) vlan_id);\n\t\treturn -EINVAL;\n\t}\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_filter_set, -ENOTSUP);\n\n\treturn (*dev->dev_ops->vlan_filter_set)(dev, vlan_id, on);\n}\n\nint\nrte_eth_dev_set_vlan_strip_on_queue(uint8_t port_id, uint16_t rx_queue_id, int on)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tif (rx_queue_id >= dev->data->nb_rx_queues) {\n\t\tPMD_DEBUG_TRACE(\"Invalid rx_queue_id=%d\\n\", port_id);\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);\n\t(*dev->dev_ops->vlan_strip_queue_set)(dev, rx_queue_id, on);\n\n\treturn 0;\n}\n\nint\nrte_eth_dev_set_vlan_ether_type(uint8_t port_id, uint16_t tpid)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_tpid_set, -ENOTSUP);\n\t(*dev->dev_ops->vlan_tpid_set)(dev, tpid);\n\n\treturn 0;\n}\n\nint\nrte_eth_dev_set_vlan_offload(uint8_t port_id, int offload_mask)\n{\n\tstruct rte_eth_dev *dev;\n\tint ret = 0;\n\tint mask = 0;\n\tint cur, org = 0;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\t/*check which option changed by application*/\n\tcur = !!(offload_mask & ETH_VLAN_STRIP_OFFLOAD);\n\torg = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);\n\tif (cur != org) {\n\t\tdev->data->dev_conf.rxmode.hw_vlan_strip = (uint8_t)cur;\n\t\tmask |= ETH_VLAN_STRIP_MASK;\n\t}\n\n\tcur = !!(offload_mask & ETH_VLAN_FILTER_OFFLOAD);\n\torg = !!(dev->data->dev_conf.rxmode.hw_vlan_filter);\n\tif (cur != org) {\n\t\tdev->data->dev_conf.rxmode.hw_vlan_filter = (uint8_t)cur;\n\t\tmask |= ETH_VLAN_FILTER_MASK;\n\t}\n\n\tcur = !!(offload_mask & ETH_VLAN_EXTEND_OFFLOAD);\n\torg = !!(dev->data->dev_conf.rxmode.hw_vlan_extend);\n\tif (cur != org) {\n\t\tdev->data->dev_conf.rxmode.hw_vlan_extend = (uint8_t)cur;\n\t\tmask |= ETH_VLAN_EXTEND_MASK;\n\t}\n\n\t/*no change*/\n\tif (mask == 0)\n\t\treturn ret;\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_offload_set, -ENOTSUP);\n\t(*dev->dev_ops->vlan_offload_set)(dev, mask);\n\n\treturn ret;\n}\n\nint\nrte_eth_dev_get_vlan_offload(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\tint ret = 0;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\tif (dev->data->dev_conf.rxmode.hw_vlan_strip)\n\t\tret |= ETH_VLAN_STRIP_OFFLOAD;\n\n\tif (dev->data->dev_conf.rxmode.hw_vlan_filter)\n\t\tret |= ETH_VLAN_FILTER_OFFLOAD;\n\n\tif (dev->data->dev_conf.rxmode.hw_vlan_extend)\n\t\tret |= ETH_VLAN_EXTEND_OFFLOAD;\n\n\treturn ret;\n}\n\nint\nrte_eth_dev_set_vlan_pvid(uint8_t port_id, uint16_t pvid, int on)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_pvid_set, -ENOTSUP);\n\t(*dev->dev_ops->vlan_pvid_set)(dev, pvid, on);\n\n\treturn 0;\n}\n\nint\nrte_eth_dev_fdir_add_signature_filter(uint8_t port_id,\n\t\t\t\t struct rte_fdir_filter *fdir_filter,\n\t\t\t\t uint8_t queue)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\tif (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_SIGNATURE) {\n\t\tPMD_DEBUG_TRACE(\"port %d: invalid FDIR mode=%u\\n\",\n\t\t\t\tport_id, dev->data->dev_conf.fdir_conf.mode);\n\t\treturn -ENOSYS;\n\t}\n\n\tif ((fdir_filter->l4type == RTE_FDIR_L4TYPE_SCTP\n\t || fdir_filter->l4type == RTE_FDIR_L4TYPE_NONE)\n\t && (fdir_filter->port_src || fdir_filter->port_dst)) {\n\t\tPMD_DEBUG_TRACE(\" Port are meaningless for SCTP and \"\n\t\t\t\t\"None l4type, source & destinations ports \"\n\t\t\t\t\"should be null!\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->fdir_add_signature_filter, -ENOTSUP);\n\treturn (*dev->dev_ops->fdir_add_signature_filter)(dev, fdir_filter,\n\t\t\t\t\t\t\t\tqueue);\n}\n\nint\nrte_eth_dev_fdir_update_signature_filter(uint8_t port_id,\n\t\t\t\t\t struct rte_fdir_filter *fdir_filter,\n\t\t\t\t\t uint8_t queue)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\tif (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_SIGNATURE) {\n\t\tPMD_DEBUG_TRACE(\"port %d: invalid FDIR mode=%u\\n\",\n\t\t\t\tport_id, dev->data->dev_conf.fdir_conf.mode);\n\t\treturn -ENOSYS;\n\t}\n\n\tif ((fdir_filter->l4type == RTE_FDIR_L4TYPE_SCTP\n\t || fdir_filter->l4type == RTE_FDIR_L4TYPE_NONE)\n\t && (fdir_filter->port_src || fdir_filter->port_dst)) {\n\t\tPMD_DEBUG_TRACE(\" Port are meaningless for SCTP and \"\n\t\t\t\t\"None l4type, source & destinations ports \"\n\t\t\t\t\"should be null!\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->fdir_update_signature_filter, -ENOTSUP);\n\treturn (*dev->dev_ops->fdir_update_signature_filter)(dev, fdir_filter,\n\t\t\t\t\t\t\t\tqueue);\n\n}\n\nint\nrte_eth_dev_fdir_remove_signature_filter(uint8_t port_id,\n\t\t\t\t\t struct rte_fdir_filter *fdir_filter)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\tif (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_SIGNATURE) {\n\t\tPMD_DEBUG_TRACE(\"port %d: invalid FDIR mode=%u\\n\",\n\t\t\t\tport_id, dev->data->dev_conf.fdir_conf.mode);\n\t\treturn -ENOSYS;\n\t}\n\n\tif ((fdir_filter->l4type == RTE_FDIR_L4TYPE_SCTP\n\t || fdir_filter->l4type == RTE_FDIR_L4TYPE_NONE)\n\t && (fdir_filter->port_src || fdir_filter->port_dst)) {\n\t\tPMD_DEBUG_TRACE(\" Port are meaningless for SCTP and \"\n\t\t\t\t\"None l4type source & destinations ports \"\n\t\t\t\t\"should be null!\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->fdir_remove_signature_filter, -ENOTSUP);\n\treturn (*dev->dev_ops->fdir_remove_signature_filter)(dev, fdir_filter);\n}\n\nint\nrte_eth_dev_fdir_get_infos(uint8_t port_id, struct rte_eth_fdir *fdir)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tif (!(dev->data->dev_conf.fdir_conf.mode)) {\n\t\tPMD_DEBUG_TRACE(\"port %d: pkt-filter disabled\\n\", port_id);\n\t\treturn -ENOSYS;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->fdir_infos_get, -ENOTSUP);\n\n\t(*dev->dev_ops->fdir_infos_get)(dev, fdir);\n\treturn 0;\n}\n\nint\nrte_eth_dev_fdir_add_perfect_filter(uint8_t port_id,\n\t\t\t\t struct rte_fdir_filter *fdir_filter,\n\t\t\t\t uint16_t soft_id, uint8_t queue,\n\t\t\t\t uint8_t drop)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\tif (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {\n\t\tPMD_DEBUG_TRACE(\"port %d: invalid FDIR mode=%u\\n\",\n\t\t\t\tport_id, dev->data->dev_conf.fdir_conf.mode);\n\t\treturn -ENOSYS;\n\t}\n\n\tif ((fdir_filter->l4type == RTE_FDIR_L4TYPE_SCTP\n\t || fdir_filter->l4type == RTE_FDIR_L4TYPE_NONE)\n\t && (fdir_filter->port_src || fdir_filter->port_dst)) {\n\t\tPMD_DEBUG_TRACE(\" Port are meaningless for SCTP and \"\n\t\t\t\t\"None l4type, source & destinations ports \"\n\t\t\t\t\"should be null!\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* For now IPv6 is not supported with perfect filter */\n\tif (fdir_filter->iptype == RTE_FDIR_IPTYPE_IPV6)\n\t\treturn -ENOTSUP;\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->fdir_add_perfect_filter, -ENOTSUP);\n\treturn (*dev->dev_ops->fdir_add_perfect_filter)(dev, fdir_filter,\n\t\t\t\t\t\t\t\tsoft_id, queue,\n\t\t\t\t\t\t\t\tdrop);\n}\n\nint\nrte_eth_dev_fdir_update_perfect_filter(uint8_t port_id,\n\t\t\t\t struct rte_fdir_filter *fdir_filter,\n\t\t\t\t uint16_t soft_id, uint8_t queue,\n\t\t\t\t uint8_t drop)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\tif (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {\n\t\tPMD_DEBUG_TRACE(\"port %d: invalid FDIR mode=%u\\n\",\n\t\t\t\tport_id, dev->data->dev_conf.fdir_conf.mode);\n\t\treturn -ENOSYS;\n\t}\n\n\tif ((fdir_filter->l4type == RTE_FDIR_L4TYPE_SCTP\n\t || fdir_filter->l4type == RTE_FDIR_L4TYPE_NONE)\n\t && (fdir_filter->port_src || fdir_filter->port_dst)) {\n\t\tPMD_DEBUG_TRACE(\" Port are meaningless for SCTP and \"\n\t\t\t\t\"None l4type, source & destinations ports \"\n\t\t\t\t\"should be null!\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* For now IPv6 is not supported with perfect filter */\n\tif (fdir_filter->iptype == RTE_FDIR_IPTYPE_IPV6)\n\t\treturn -ENOTSUP;\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->fdir_update_perfect_filter, -ENOTSUP);\n\treturn (*dev->dev_ops->fdir_update_perfect_filter)(dev, fdir_filter,\n\t\t\t\t\t\t\tsoft_id, queue, drop);\n}\n\nint\nrte_eth_dev_fdir_remove_perfect_filter(uint8_t port_id,\n\t\t\t\t struct rte_fdir_filter *fdir_filter,\n\t\t\t\t uint16_t soft_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\tif (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {\n\t\tPMD_DEBUG_TRACE(\"port %d: invalid FDIR mode=%u\\n\",\n\t\t\t\tport_id, dev->data->dev_conf.fdir_conf.mode);\n\t\treturn -ENOSYS;\n\t}\n\n\tif ((fdir_filter->l4type == RTE_FDIR_L4TYPE_SCTP\n\t || fdir_filter->l4type == RTE_FDIR_L4TYPE_NONE)\n\t && (fdir_filter->port_src || fdir_filter->port_dst)) {\n\t\tPMD_DEBUG_TRACE(\" Port are meaningless for SCTP and \"\n\t\t\t\t\"None l4type, source & destinations ports \"\n\t\t\t\t\"should be null!\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\t/* For now IPv6 is not supported with perfect filter */\n\tif (fdir_filter->iptype == RTE_FDIR_IPTYPE_IPV6)\n\t\treturn -ENOTSUP;\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->fdir_remove_perfect_filter, -ENOTSUP);\n\treturn (*dev->dev_ops->fdir_remove_perfect_filter)(dev, fdir_filter,\n\t\t\t\t\t\t\t\tsoft_id);\n}\n\nint\nrte_eth_dev_fdir_set_masks(uint8_t port_id, struct rte_fdir_masks *fdir_mask)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tif (!(dev->data->dev_conf.fdir_conf.mode)) {\n\t\tPMD_DEBUG_TRACE(\"port %d: pkt-filter disabled\\n\", port_id);\n\t\treturn -ENOSYS;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->fdir_set_masks, -ENOTSUP);\n\treturn (*dev->dev_ops->fdir_set_masks)(dev, fdir_mask);\n}\n\nint\nrte_eth_dev_flow_ctrl_get(uint8_t port_id, struct rte_eth_fc_conf *fc_conf)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_get, -ENOTSUP);\n\tmemset(fc_conf, 0, sizeof(*fc_conf));\n\treturn (*dev->dev_ops->flow_ctrl_get)(dev, fc_conf);\n}\n\nint\nrte_eth_dev_flow_ctrl_set(uint8_t port_id, struct rte_eth_fc_conf *fc_conf)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tif ((fc_conf->send_xon != 0) && (fc_conf->send_xon != 1)) {\n\t\tPMD_DEBUG_TRACE(\"Invalid send_xon, only 0/1 allowed\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_set, -ENOTSUP);\n\treturn (*dev->dev_ops->flow_ctrl_set)(dev, fc_conf);\n}\n\nint\nrte_eth_dev_priority_flow_ctrl_set(uint8_t port_id, struct rte_eth_pfc_conf *pfc_conf)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tif (pfc_conf->priority > (ETH_DCB_NUM_USER_PRIORITIES - 1)) {\n\t\tPMD_DEBUG_TRACE(\"Invalid priority, only 0-7 allowed\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tdev = &rte_eth_devices[port_id];\n\t/* High water, low water validation are device specific */\n\tif (*dev->dev_ops->priority_flow_ctrl_set)\n\t\treturn (*dev->dev_ops->priority_flow_ctrl_set)(dev, pfc_conf);\n\treturn -ENOTSUP;\n}\n\nstatic int\nrte_eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\tuint16_t reta_size)\n{\n\tuint16_t i, num;\n\n\tif (!reta_conf)\n\t\treturn -EINVAL;\n\n\tif (reta_size != RTE_ALIGN(reta_size, RTE_RETA_GROUP_SIZE)) {\n\t\tPMD_DEBUG_TRACE(\"Invalid reta size, should be %u aligned\\n\",\n\t\t\t\t\t\t\tRTE_RETA_GROUP_SIZE);\n\t\treturn -EINVAL;\n\t}\n\n\tnum = reta_size / RTE_RETA_GROUP_SIZE;\n\tfor (i = 0; i < num; i++) {\n\t\tif (reta_conf[i].mask)\n\t\t\treturn 0;\n\t}\n\n\treturn -EINVAL;\n}\n\nstatic int\nrte_eth_check_reta_entry(struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t uint16_t reta_size,\n\t\t\t uint8_t max_rxq)\n{\n\tuint16_t i, idx, shift;\n\n\tif (!reta_conf)\n\t\treturn -EINVAL;\n\n\tif (max_rxq == 0) {\n\t\tPMD_DEBUG_TRACE(\"No receive queue is available\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < reta_size; i++) {\n\t\tidx = i / RTE_RETA_GROUP_SIZE;\n\t\tshift = i % RTE_RETA_GROUP_SIZE;\n\t\tif ((reta_conf[idx].mask & (1ULL << shift)) &&\n\t\t\t(reta_conf[idx].reta[shift] >= max_rxq)) {\n\t\t\tPMD_DEBUG_TRACE(\"reta_conf[%u]->reta[%u]: %u exceeds \"\n\t\t\t\t\"the maximum rxq index: %u\\n\", idx, shift,\n\t\t\t\treta_conf[idx].reta[shift], max_rxq);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nint\nrte_eth_dev_rss_reta_update(uint8_t port_id,\n\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t uint16_t reta_size)\n{\n\tstruct rte_eth_dev *dev;\n\tint ret;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\t/* Check mask bits */\n\tret = rte_eth_check_reta_mask(reta_conf, reta_size);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tdev = &rte_eth_devices[port_id];\n\n\t/* Check entry value */\n\tret = rte_eth_check_reta_entry(reta_conf, reta_size,\n\t\t\t\tdev->data->nb_rx_queues);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_update, -ENOTSUP);\n\treturn (*dev->dev_ops->reta_update)(dev, reta_conf, reta_size);\n}\n\nint\nrte_eth_dev_rss_reta_query(uint8_t port_id,\n\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t uint16_t reta_size)\n{\n\tstruct rte_eth_dev *dev;\n\tint ret;\n\n\tif (port_id >= nb_ports) {\n\t\tPMD_DEBUG_TRACE(\"Invalid port_id=%d\\n\", port_id);\n\t\treturn -ENODEV;\n\t}\n\n\t/* Check mask bits */\n\tret = rte_eth_check_reta_mask(reta_conf, reta_size);\n\tif (ret < 0)\n\t\treturn ret;\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_query, -ENOTSUP);\n\treturn (*dev->dev_ops->reta_query)(dev, reta_conf, reta_size);\n}\n\nint\nrte_eth_dev_rss_hash_update(uint8_t port_id, struct rte_eth_rss_conf *rss_conf)\n{\n\tstruct rte_eth_dev *dev;\n\tuint16_t rss_hash_protos;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\trss_hash_protos = rss_conf->rss_hf;\n\tif ((rss_hash_protos != 0) &&\n\t ((rss_hash_protos & ETH_RSS_PROTO_MASK) == 0)) {\n\t\tPMD_DEBUG_TRACE(\"Invalid rss_hash_protos=0x%x\\n\",\n\t\t\t\trss_hash_protos);\n\t\treturn -EINVAL;\n\t}\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_update, -ENOTSUP);\n\treturn (*dev->dev_ops->rss_hash_update)(dev, rss_conf);\n}\n\nint\nrte_eth_dev_rss_hash_conf_get(uint8_t port_id,\n\t\t\t struct rte_eth_rss_conf *rss_conf)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_conf_get, -ENOTSUP);\n\treturn (*dev->dev_ops->rss_hash_conf_get)(dev, rss_conf);\n}\n\nint\nrte_eth_dev_udp_tunnel_add(uint8_t port_id,\n\t\t\t struct rte_eth_udp_tunnel *udp_tunnel)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tif (udp_tunnel == NULL) {\n\t\tPMD_DEBUG_TRACE(\"Invalid udp_tunnel parameter\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) {\n\t\tPMD_DEBUG_TRACE(\"Invalid tunnel type\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_add, -ENOTSUP);\n\treturn (*dev->dev_ops->udp_tunnel_add)(dev, udp_tunnel);\n}\n\nint\nrte_eth_dev_udp_tunnel_delete(uint8_t port_id,\n\t\t\t struct rte_eth_udp_tunnel *udp_tunnel)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\tif (udp_tunnel == NULL) {\n\t\tPMD_DEBUG_TRACE(\"Invalid udp_tunnel parameter\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) {\n\t\tPMD_DEBUG_TRACE(\"Invalid tunnel type\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_del, -ENOTSUP);\n\treturn (*dev->dev_ops->udp_tunnel_del)(dev, udp_tunnel);\n}\n\nint\nrte_eth_led_on(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_on, -ENOTSUP);\n\treturn (*dev->dev_ops->dev_led_on)(dev);\n}\n\nint\nrte_eth_led_off(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_off, -ENOTSUP);\n\treturn (*dev->dev_ops->dev_led_off)(dev);\n}\n\n/*\n * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find\n * an empty spot.\n */\nstatic int\nget_mac_addr_index(uint8_t port_id, const struct ether_addr *addr)\n{\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\tunsigned i;\n\n\trte_eth_dev_info_get(port_id, &dev_info);\n\n\tfor (i = 0; i < dev_info.max_mac_addrs; i++)\n\t\tif (memcmp(addr, &dev->data->mac_addrs[i], ETHER_ADDR_LEN) == 0)\n\t\t\treturn i;\n\n\treturn -1;\n}\n\nstatic const struct ether_addr null_mac_addr;\n\nint\nrte_eth_dev_mac_addr_add(uint8_t port_id, struct ether_addr *addr,\n\t\t\tuint32_t pool)\n{\n\tstruct rte_eth_dev *dev;\n\tint index;\n\tuint64_t pool_mask;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_add, -ENOTSUP);\n\n\tif (is_zero_ether_addr(addr)) {\n\t\tPMD_DEBUG_TRACE(\"port %d: Cannot add NULL MAC address\\n\",\n\t\t\tport_id);\n\t\treturn -EINVAL;\n\t}\n\tif (pool >= ETH_64_POOLS) {\n\t\tPMD_DEBUG_TRACE(\"pool id must be 0-%d\\n\", ETH_64_POOLS - 1);\n\t\treturn -EINVAL;\n\t}\n\n\tindex = get_mac_addr_index(port_id, addr);\n\tif (index < 0) {\n\t\tindex = get_mac_addr_index(port_id, &null_mac_addr);\n\t\tif (index < 0) {\n\t\t\tPMD_DEBUG_TRACE(\"port %d: MAC address array full\\n\",\n\t\t\t\tport_id);\n\t\t\treturn -ENOSPC;\n\t\t}\n\t} else {\n\t\tpool_mask = dev->data->mac_pool_sel[index];\n\n\t\t/* Check if both MAC address and pool is already there, and do nothing */\n\t\tif (pool_mask & (1ULL << pool))\n\t\t\treturn 0;\n\t}\n\n\t/* Update NIC */\n\t(*dev->dev_ops->mac_addr_add)(dev, addr, index, pool);\n\n\t/* Update address in NIC data structure */\n\tether_addr_copy(addr, &dev->data->mac_addrs[index]);\n\n\t/* Update pool bitmap in NIC data structure */\n\tdev->data->mac_pool_sel[index] |= (1ULL << pool);\n\n\treturn 0;\n}\n\nint\nrte_eth_dev_mac_addr_remove(uint8_t port_id, struct ether_addr *addr)\n{\n\tstruct rte_eth_dev *dev;\n\tint index;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_remove, -ENOTSUP);\n\n\tindex = get_mac_addr_index(port_id, addr);\n\tif (index == 0) {\n\t\tPMD_DEBUG_TRACE(\"port %d: Cannot remove default MAC address\\n\", port_id);\n\t\treturn -EADDRINUSE;\n\t} else if (index < 0)\n\t\treturn 0; /* Do nothing if address wasn't found */\n\n\t/* Update NIC */\n\t(*dev->dev_ops->mac_addr_remove)(dev, index);\n\n\t/* Update address in NIC data structure */\n\tether_addr_copy(&null_mac_addr, &dev->data->mac_addrs[index]);\n\n\t/* reset pool bitmap */\n\tdev->data->mac_pool_sel[index] = 0;\n\n\treturn 0;\n}\n\nint\nrte_eth_dev_default_mac_addr_set(uint8_t port_id, struct ether_addr *addr)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tif (!is_valid_assigned_ether_addr(addr))\n\t\treturn -EINVAL;\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_set, -ENOTSUP);\n\n\t/* Update default address in NIC data structure */\n\tether_addr_copy(addr, &dev->data->mac_addrs[0]);\n\n\t(*dev->dev_ops->mac_addr_set)(dev, addr);\n\n\treturn 0;\n}\n\nint\nrte_eth_dev_set_vf_rxmode(uint8_t port_id, uint16_t vf,\n\t\t\t\tuint16_t rx_mode, uint8_t on)\n{\n\tuint16_t num_vfs;\n\tstruct rte_eth_dev *dev;\n\tstruct rte_eth_dev_info dev_info;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\trte_eth_dev_info_get(port_id, &dev_info);\n\n\tnum_vfs = dev_info.max_vfs;\n\tif (vf > num_vfs) {\n\t\tPMD_DEBUG_TRACE(\"set VF RX mode:invalid VF id %d\\n\", vf);\n\t\treturn -EINVAL;\n\t}\n\n\tif (rx_mode == 0) {\n\t\tPMD_DEBUG_TRACE(\"set VF RX mode:mode mask ca not be zero\\n\");\n\t\treturn -EINVAL;\n\t}\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_vf_rx_mode, -ENOTSUP);\n\treturn (*dev->dev_ops->set_vf_rx_mode)(dev, vf, rx_mode, on);\n}\n\n/*\n * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find\n * an empty spot.\n */\nstatic int\nget_hash_mac_addr_index(uint8_t port_id, const struct ether_addr *addr)\n{\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\tunsigned i;\n\n\trte_eth_dev_info_get(port_id, &dev_info);\n\tif (!dev->data->hash_mac_addrs)\n\t\treturn -1;\n\n\tfor (i = 0; i < dev_info.max_hash_mac_addrs; i++)\n\t\tif (memcmp(addr, &dev->data->hash_mac_addrs[i],\n\t\t\tETHER_ADDR_LEN) == 0)\n\t\t\treturn i;\n\n\treturn -1;\n}\n\nint\nrte_eth_dev_uc_hash_table_set(uint8_t port_id, struct ether_addr *addr,\n\t\t\t\tuint8_t on)\n{\n\tint index;\n\tint ret;\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tif (is_zero_ether_addr(addr)) {\n\t\tPMD_DEBUG_TRACE(\"port %d: Cannot add NULL MAC address\\n\",\n\t\t\tport_id);\n\t\treturn -EINVAL;\n\t}\n\n\tindex = get_hash_mac_addr_index(port_id, addr);\n\t/* Check if it's already there, and do nothing */\n\tif ((index >= 0) && (on))\n\t\treturn 0;\n\n\tif (index < 0) {\n\t\tif (!on) {\n\t\t\tPMD_DEBUG_TRACE(\"port %d: the MAC address was not \"\n\t\t\t\t\"set in UTA\\n\", port_id);\n\t\t\treturn -EINVAL;\n\t\t}\n\n\t\tindex = get_hash_mac_addr_index(port_id, &null_mac_addr);\n\t\tif (index < 0) {\n\t\t\tPMD_DEBUG_TRACE(\"port %d: MAC address array full\\n\",\n\t\t\t\t\tport_id);\n\t\t\treturn -ENOSPC;\n\t\t}\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_hash_table_set, -ENOTSUP);\n\tret = (*dev->dev_ops->uc_hash_table_set)(dev, addr, on);\n\tif (ret == 0) {\n\t\t/* Update address in NIC data structure */\n\t\tif (on)\n\t\t\tether_addr_copy(addr,\n\t\t\t\t\t&dev->data->hash_mac_addrs[index]);\n\t\telse\n\t\t\tether_addr_copy(&null_mac_addr,\n\t\t\t\t\t&dev->data->hash_mac_addrs[index]);\n\t}\n\n\treturn ret;\n}\n\nint\nrte_eth_dev_uc_all_hash_table_set(uint8_t port_id, uint8_t on)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_all_hash_table_set, -ENOTSUP);\n\treturn (*dev->dev_ops->uc_all_hash_table_set)(dev, on);\n}\n\nint\nrte_eth_dev_set_vf_rx(uint8_t port_id, uint16_t vf, uint8_t on)\n{\n\tuint16_t num_vfs;\n\tstruct rte_eth_dev *dev;\n\tstruct rte_eth_dev_info dev_info;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\trte_eth_dev_info_get(port_id, &dev_info);\n\n\tnum_vfs = dev_info.max_vfs;\n\tif (vf > num_vfs) {\n\t\tPMD_DEBUG_TRACE(\"port %d: invalid vf id\\n\", port_id);\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_vf_rx, -ENOTSUP);\n\treturn (*dev->dev_ops->set_vf_rx)(dev, vf, on);\n}\n\nint\nrte_eth_dev_set_vf_tx(uint8_t port_id, uint16_t vf, uint8_t on)\n{\n\tuint16_t num_vfs;\n\tstruct rte_eth_dev *dev;\n\tstruct rte_eth_dev_info dev_info;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\trte_eth_dev_info_get(port_id, &dev_info);\n\n\tnum_vfs = dev_info.max_vfs;\n\tif (vf > num_vfs) {\n\t\tPMD_DEBUG_TRACE(\"set pool tx:invalid pool id=%d\\n\", vf);\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_vf_tx, -ENOTSUP);\n\treturn (*dev->dev_ops->set_vf_tx)(dev, vf, on);\n}\n\nint\nrte_eth_dev_set_vf_vlan_filter(uint8_t port_id, uint16_t vlan_id,\n\t\t\t uint64_t vf_mask, uint8_t vlan_on)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\n\tif (vlan_id > ETHER_MAX_VLAN_ID) {\n\t\tPMD_DEBUG_TRACE(\"VF VLAN filter:invalid VLAN id=%d\\n\",\n\t\t\tvlan_id);\n\t\treturn -EINVAL;\n\t}\n\n\tif (vf_mask == 0) {\n\t\tPMD_DEBUG_TRACE(\"VF VLAN filter:pool_mask can not be 0\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_vf_vlan_filter, -ENOTSUP);\n\treturn (*dev->dev_ops->set_vf_vlan_filter)(dev, vlan_id,\n\t\t\t\t\t\t vf_mask, vlan_on);\n}\n\nint rte_eth_set_queue_rate_limit(uint8_t port_id, uint16_t queue_idx,\n\t\t\t\t\tuint16_t tx_rate)\n{\n\tstruct rte_eth_dev *dev;\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_link link;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\trte_eth_dev_info_get(port_id, &dev_info);\n\tlink = dev->data->dev_link;\n\n\tif (queue_idx > dev_info.max_tx_queues) {\n\t\tPMD_DEBUG_TRACE(\"set queue rate limit:port %d: \"\n\t\t\t\t\"invalid queue id=%d\\n\", port_id, queue_idx);\n\t\treturn -EINVAL;\n\t}\n\n\tif (tx_rate > link.link_speed) {\n\t\tPMD_DEBUG_TRACE(\"set queue rate limit:invalid tx_rate=%d, \"\n\t\t\t\t\"bigger than link speed= %d\\n\",\n\t\t\ttx_rate, link.link_speed);\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_queue_rate_limit, -ENOTSUP);\n\treturn (*dev->dev_ops->set_queue_rate_limit)(dev, queue_idx, tx_rate);\n}\n\nint rte_eth_set_vf_rate_limit(uint8_t port_id, uint16_t vf, uint16_t tx_rate,\n\t\t\t\tuint64_t q_msk)\n{\n\tstruct rte_eth_dev *dev;\n\tstruct rte_eth_dev_info dev_info;\n\tstruct rte_eth_link link;\n\n\tif (q_msk == 0)\n\t\treturn 0;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\trte_eth_dev_info_get(port_id, &dev_info);\n\tlink = dev->data->dev_link;\n\n\tif (vf > dev_info.max_vfs) {\n\t\tPMD_DEBUG_TRACE(\"set VF rate limit:port %d: \"\n\t\t\t\t\"invalid vf id=%d\\n\", port_id, vf);\n\t\treturn -EINVAL;\n\t}\n\n\tif (tx_rate > link.link_speed) {\n\t\tPMD_DEBUG_TRACE(\"set VF rate limit:invalid tx_rate=%d, \"\n\t\t\t\t\"bigger than link speed= %d\\n\",\n\t\t\t\ttx_rate, link.link_speed);\n\t\treturn -EINVAL;\n\t}\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_vf_rate_limit, -ENOTSUP);\n\treturn (*dev->dev_ops->set_vf_rate_limit)(dev, vf, tx_rate, q_msk);\n}\n\nint\nrte_eth_mirror_rule_set(uint8_t port_id,\n\t\t\tstruct rte_eth_mirror_conf *mirror_conf,\n\t\t\tuint8_t rule_id, uint8_t on)\n{\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tif (mirror_conf->rule_type == 0) {\n\t\tPMD_DEBUG_TRACE(\"mirror rule type can not be 0.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif (mirror_conf->dst_pool >= ETH_64_POOLS) {\n\t\tPMD_DEBUG_TRACE(\"Invalid dst pool, pool id must be 0-%d\\n\",\n\t\t\t\tETH_64_POOLS - 1);\n\t\treturn -EINVAL;\n\t}\n\n\tif ((mirror_conf->rule_type & (ETH_MIRROR_VIRTUAL_POOL_UP |\n\t ETH_MIRROR_VIRTUAL_POOL_DOWN)) &&\n\t (mirror_conf->pool_mask == 0)) {\n\t\tPMD_DEBUG_TRACE(\"Invalid mirror pool, pool mask can not be 0.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tif ((mirror_conf->rule_type & ETH_MIRROR_VLAN) &&\n\t mirror_conf->vlan.vlan_mask == 0) {\n\t\tPMD_DEBUG_TRACE(\"Invalid vlan mask, vlan mask can not be 0.\\n\");\n\t\treturn -EINVAL;\n\t}\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_set, -ENOTSUP);\n\n\treturn (*dev->dev_ops->mirror_rule_set)(dev, mirror_conf, rule_id, on);\n}\n\nint\nrte_eth_mirror_rule_reset(uint8_t port_id, uint8_t rule_id)\n{\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_reset, -ENOTSUP);\n\n\treturn (*dev->dev_ops->mirror_rule_reset)(dev, rule_id);\n}\n\n#ifdef RTE_LIBRTE_ETHDEV_DEBUG\nuint16_t\nrte_eth_rx_burst(uint8_t port_id, uint16_t queue_id,\n\t\t struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, 0);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, 0);\n\tif (queue_id >= dev->data->nb_rx_queues) {\n\t\tPMD_DEBUG_TRACE(\"Invalid RX queue_id=%d\\n\", queue_id);\n\t\treturn 0;\n\t}\n\treturn (*dev->rx_pkt_burst)(dev->data->rx_queues[queue_id],\n\t\t\t\t\t\trx_pkts, nb_pkts);\n}\n\nuint16_t\nrte_eth_tx_burst(uint8_t port_id, uint16_t queue_id,\n\t\t struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, 0);\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->tx_pkt_burst, 0);\n\tif (queue_id >= dev->data->nb_tx_queues) {\n\t\tPMD_DEBUG_TRACE(\"Invalid TX queue_id=%d\\n\", queue_id);\n\t\treturn 0;\n\t}\n\treturn (*dev->tx_pkt_burst)(dev->data->tx_queues[queue_id],\n\t\t\t\t\t\ttx_pkts, nb_pkts);\n}\n\nuint32_t\nrte_eth_rx_queue_count(uint8_t port_id, uint16_t queue_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, 0);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_count, 0);\n\treturn (*dev->dev_ops->rx_queue_count)(dev, queue_id);\n}\n\nint\nrte_eth_rx_descriptor_done(uint8_t port_id, uint16_t queue_id, uint16_t offset)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_descriptor_done, -ENOTSUP);\n\treturn (*dev->dev_ops->rx_descriptor_done)(dev->data->rx_queues[queue_id],\n\t\t\t\t\t\t offset);\n}\n#endif\n\nint\nrte_eth_dev_callback_register(uint8_t port_id,\n\t\t\tenum rte_eth_event_type event,\n\t\t\trte_eth_dev_cb_fn cb_fn, void *cb_arg)\n{\n\tstruct rte_eth_dev *dev;\n\tstruct rte_eth_dev_callback *user_cb;\n\n\tif (!cb_fn)\n\t\treturn -EINVAL;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\trte_spinlock_lock(&rte_eth_dev_cb_lock);\n\n\tTAILQ_FOREACH(user_cb, &(dev->link_intr_cbs), next) {\n\t\tif (user_cb->cb_fn == cb_fn &&\n\t\t\tuser_cb->cb_arg == cb_arg &&\n\t\t\tuser_cb->event == event) {\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* create a new callback. */\n\tif (user_cb == NULL)\n\t\tuser_cb = rte_zmalloc(\"INTR_USER_CALLBACK\",\n\t\t sizeof(struct rte_eth_dev_callback), 0);\n\tif (user_cb != NULL) {\n\t\tuser_cb->cb_fn = cb_fn;\n\t\tuser_cb->cb_arg = cb_arg;\n\t\tuser_cb->event = event;\n\t\tTAILQ_INSERT_TAIL(&(dev->link_intr_cbs), user_cb, next);\n\t}\n\n\trte_spinlock_unlock(&rte_eth_dev_cb_lock);\n\treturn (user_cb == NULL) ? -ENOMEM : 0;\n}\n\nint\nrte_eth_dev_callback_unregister(uint8_t port_id,\n\t\t\tenum rte_eth_event_type event,\n\t\t\trte_eth_dev_cb_fn cb_fn, void *cb_arg)\n{\n\tint ret;\n\tstruct rte_eth_dev *dev;\n\tstruct rte_eth_dev_callback *cb, *next;\n\n\tif (!cb_fn)\n\t\treturn -EINVAL;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -EINVAL);\n\n\tdev = &rte_eth_devices[port_id];\n\trte_spinlock_lock(&rte_eth_dev_cb_lock);\n\n\tret = 0;\n\tfor (cb = TAILQ_FIRST(&dev->link_intr_cbs); cb != NULL; cb = next) {\n\n\t\tnext = TAILQ_NEXT(cb, next);\n\n\t\tif (cb->cb_fn != cb_fn || cb->event != event ||\n\t\t\t\t(cb->cb_arg != (void *)-1 &&\n\t\t\t\tcb->cb_arg != cb_arg))\n\t\t\tcontinue;\n\n\t\t/*\n\t\t * if this callback is not executing right now,\n\t\t * then remove it.\n\t\t */\n\t\tif (cb->active == 0) {\n\t\t\tTAILQ_REMOVE(&(dev->link_intr_cbs), cb, next);\n\t\t\trte_free(cb);\n\t\t} else {\n\t\t\tret = -EAGAIN;\n\t\t}\n\t}\n\n\trte_spinlock_unlock(&rte_eth_dev_cb_lock);\n\treturn ret;\n}\n\nvoid\n_rte_eth_dev_callback_process(struct rte_eth_dev *dev,\n\tenum rte_eth_event_type event)\n{\n\tstruct rte_eth_dev_callback *cb_lst;\n\tstruct rte_eth_dev_callback dev_cb;\n\n\trte_spinlock_lock(&rte_eth_dev_cb_lock);\n\tTAILQ_FOREACH(cb_lst, &(dev->link_intr_cbs), next) {\n\t\tif (cb_lst->cb_fn == NULL || cb_lst->event != event)\n\t\t\tcontinue;\n\t\tdev_cb = *cb_lst;\n\t\tcb_lst->active = 1;\n\t\trte_spinlock_unlock(&rte_eth_dev_cb_lock);\n\t\tdev_cb.cb_fn(dev->data->port_id, dev_cb.event,\n\t\t\t\t\t\tdev_cb.cb_arg);\n\t\trte_spinlock_lock(&rte_eth_dev_cb_lock);\n\t\tcb_lst->active = 0;\n\t}\n\trte_spinlock_unlock(&rte_eth_dev_cb_lock);\n}\n\n#ifdef RTE_NEXT_ABI\nint\nrte_eth_dev_rx_intr_ctl(uint8_t port_id, int epfd, int op, void *data)\n{\n\tuint32_t vec;\n\tstruct rte_eth_dev *dev;\n\tstruct rte_intr_handle *intr_handle;\n\tuint16_t qid;\n\tint rc;\n\n\tif (!rte_eth_dev_is_valid_port(port_id)) {\n\t\tPMD_DEBUG_TRACE(\"Invalid port_id=%u\\n\", port_id);\n\t\treturn -ENODEV;\n\t}\n\n\tdev = &rte_eth_devices[port_id];\n\tintr_handle = &dev->pci_dev->intr_handle;\n\tif (!intr_handle->intr_vec) {\n\t\tPMD_DEBUG_TRACE(\"RX Intr vector unset\\n\");\n\t\treturn -EPERM;\n\t}\n\n\tfor (qid = 0; qid < dev->data->nb_rx_queues; qid++) {\n\t\tvec = intr_handle->intr_vec[qid];\n\t\trc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data);\n\t\tif (rc && rc != -EEXIST) {\n\t\t\tPMD_DEBUG_TRACE(\"p %u q %u rx ctl error\"\n\t\t\t\t\t\" op %d epfd %d vec %u\\n\",\n\t\t\t\t\tport_id, qid, op, epfd, vec);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nint\nrte_eth_dev_rx_intr_ctl_q(uint8_t port_id, uint16_t queue_id,\n\t\t\t int epfd, int op, void *data)\n{\n\tuint32_t vec;\n\tstruct rte_eth_dev *dev;\n\tstruct rte_intr_handle *intr_handle;\n\tint rc;\n\n\tif (!rte_eth_dev_is_valid_port(port_id)) {\n\t\tPMD_DEBUG_TRACE(\"Invalid port_id=%u\\n\", port_id);\n\t\treturn -ENODEV;\n\t}\n\n\tdev = &rte_eth_devices[port_id];\n\tif (queue_id >= dev->data->nb_rx_queues) {\n\t\tPMD_DEBUG_TRACE(\"Invalid RX queue_id=%u\\n\", queue_id);\n\t\treturn -EINVAL;\n\t}\n\n\tintr_handle = &dev->pci_dev->intr_handle;\n\tif (!intr_handle->intr_vec) {\n\t\tPMD_DEBUG_TRACE(\"RX Intr vector unset\\n\");\n\t\treturn -EPERM;\n\t}\n\n\tvec = intr_handle->intr_vec[queue_id];\n\trc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data);\n\tif (rc && rc != -EEXIST) {\n\t\tPMD_DEBUG_TRACE(\"p %u q %u rx ctl error\"\n\t\t\t\t\" op %d epfd %d vec %u\\n\",\n\t\t\t\tport_id, queue_id, op, epfd, vec);\n\t\treturn rc;\n\t}\n\n\treturn 0;\n}\n\nint\nrte_eth_dev_rx_intr_enable(uint8_t port_id,\n\t\t\t uint16_t queue_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tif (!rte_eth_dev_is_valid_port(port_id)) {\n\t\tPMD_DEBUG_TRACE(\"Invalid port_id=%d\\n\", port_id);\n\t\treturn -ENODEV;\n\t}\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_enable, -ENOTSUP);\n\treturn (*dev->dev_ops->rx_queue_intr_enable)(dev, queue_id);\n}\n\nint\nrte_eth_dev_rx_intr_disable(uint8_t port_id,\n\t\t\t uint16_t queue_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tif (!rte_eth_dev_is_valid_port(port_id)) {\n\t\tPMD_DEBUG_TRACE(\"Invalid port_id=%d\\n\", port_id);\n\t\treturn -ENODEV;\n\t}\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_disable, -ENOTSUP);\n\treturn (*dev->dev_ops->rx_queue_intr_disable)(dev, queue_id);\n}\n#else\nint\nrte_eth_dev_rx_intr_enable(uint8_t port_id, uint16_t queue_id)\n{\n\tRTE_SET_USED(port_id);\n\tRTE_SET_USED(queue_id);\n\treturn -ENOTSUP;\n}\n\nint\nrte_eth_dev_rx_intr_disable(uint8_t port_id, uint16_t queue_id)\n{\n\tRTE_SET_USED(port_id);\n\tRTE_SET_USED(queue_id);\n\treturn -ENOTSUP;\n}\n\nint\nrte_eth_dev_rx_intr_ctl(uint8_t port_id, int epfd, int op, void *data)\n{\n\tRTE_SET_USED(port_id);\n\tRTE_SET_USED(epfd);\n\tRTE_SET_USED(op);\n\tRTE_SET_USED(data);\n\treturn -1;\n}\n\nint\nrte_eth_dev_rx_intr_ctl_q(uint8_t port_id, uint16_t queue_id,\n\t\t\t int epfd, int op, void *data)\n{\n\tRTE_SET_USED(port_id);\n\tRTE_SET_USED(queue_id);\n\tRTE_SET_USED(epfd);\n\tRTE_SET_USED(op);\n\tRTE_SET_USED(data);\n\treturn -1;\n}\n#endif\n\n#ifdef RTE_NIC_BYPASS\nint rte_eth_dev_bypass_init(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->bypass_init, -ENOTSUP);\n\t(*dev->dev_ops->bypass_init)(dev);\n\treturn 0;\n}\n\nint\nrte_eth_dev_bypass_state_show(uint8_t port_id, uint32_t *state)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->bypass_state_show, -ENOTSUP);\n\t(*dev->dev_ops->bypass_state_show)(dev, state);\n\treturn 0;\n}\n\nint\nrte_eth_dev_bypass_state_set(uint8_t port_id, uint32_t *new_state)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->bypass_state_set, -ENOTSUP);\n\t(*dev->dev_ops->bypass_state_set)(dev, new_state);\n\treturn 0;\n}\n\nint\nrte_eth_dev_bypass_event_show(uint8_t port_id, uint32_t event, uint32_t *state)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->bypass_state_show, -ENOTSUP);\n\t(*dev->dev_ops->bypass_event_show)(dev, event, state);\n\treturn 0;\n}\n\nint\nrte_eth_dev_bypass_event_store(uint8_t port_id, uint32_t event, uint32_t state)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->bypass_event_set, -ENOTSUP);\n\t(*dev->dev_ops->bypass_event_set)(dev, event, state);\n\treturn 0;\n}\n\nint\nrte_eth_dev_wd_timeout_store(uint8_t port_id, uint32_t timeout)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->bypass_wd_timeout_set, -ENOTSUP);\n\t(*dev->dev_ops->bypass_wd_timeout_set)(dev, timeout);\n\treturn 0;\n}\n\nint\nrte_eth_dev_bypass_ver_show(uint8_t port_id, uint32_t *ver)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->bypass_ver_show, -ENOTSUP);\n\t(*dev->dev_ops->bypass_ver_show)(dev, ver);\n\treturn 0;\n}\n\nint\nrte_eth_dev_bypass_wd_timeout_show(uint8_t port_id, uint32_t *wd_timeout)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->bypass_wd_timeout_show, -ENOTSUP);\n\t(*dev->dev_ops->bypass_wd_timeout_show)(dev, wd_timeout);\n\treturn 0;\n}\n\nint\nrte_eth_dev_bypass_wd_reset(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->bypass_wd_reset, -ENOTSUP);\n\t(*dev->dev_ops->bypass_wd_reset)(dev);\n\treturn 0;\n}\n#endif\n\nint\nrte_eth_dev_filter_supported(uint8_t port_id, enum rte_filter_type filter_type)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->filter_ctrl, -ENOTSUP);\n\treturn (*dev->dev_ops->filter_ctrl)(dev, filter_type,\n\t\t\t\tRTE_ETH_FILTER_NOP, NULL);\n}\n\nint\nrte_eth_dev_filter_ctrl(uint8_t port_id, enum rte_filter_type filter_type,\n\t\t enum rte_filter_op filter_op, void *arg)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->filter_ctrl, -ENOTSUP);\n\treturn (*dev->dev_ops->filter_ctrl)(dev, filter_type, filter_op, arg);\n}\n\nvoid *\nrte_eth_add_rx_callback(uint8_t port_id, uint16_t queue_id,\n\t\trte_rx_callback_fn fn, void *user_param)\n{\n#ifndef RTE_ETHDEV_RXTX_CALLBACKS\n\trte_errno = ENOTSUP;\n\treturn NULL;\n#endif\n\t/* check input parameters */\n\tif (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||\n\t\t queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) {\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\tstruct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);\n\n\tif (cb == NULL) {\n\t\trte_errno = ENOMEM;\n\t\treturn NULL;\n\t}\n\n\tcb->fn.rx = fn;\n\tcb->param = user_param;\n\n\t/* Add the callbacks in fifo order. */\n\tstruct rte_eth_rxtx_callback *tail =\n\t\trte_eth_devices[port_id].post_rx_burst_cbs[queue_id];\n\n\tif (!tail) {\n\t\trte_eth_devices[port_id].post_rx_burst_cbs[queue_id] = cb;\n\n\t} else {\n\t\twhile (tail->next)\n\t\t\ttail = tail->next;\n\t\ttail->next = cb;\n\t}\n\n\treturn cb;\n}\n\nvoid *\nrte_eth_add_tx_callback(uint8_t port_id, uint16_t queue_id,\n\t\trte_tx_callback_fn fn, void *user_param)\n{\n#ifndef RTE_ETHDEV_RXTX_CALLBACKS\n\trte_errno = ENOTSUP;\n\treturn NULL;\n#endif\n\t/* check input parameters */\n\tif (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||\n\t\t queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) {\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\tstruct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);\n\n\tif (cb == NULL) {\n\t\trte_errno = ENOMEM;\n\t\treturn NULL;\n\t}\n\n\tcb->fn.tx = fn;\n\tcb->param = user_param;\n\n\t/* Add the callbacks in fifo order. */\n\tstruct rte_eth_rxtx_callback *tail =\n\t\trte_eth_devices[port_id].pre_tx_burst_cbs[queue_id];\n\n\tif (!tail) {\n\t\trte_eth_devices[port_id].pre_tx_burst_cbs[queue_id] = cb;\n\n\t} else {\n\t\twhile (tail->next)\n\t\t\ttail = tail->next;\n\t\ttail->next = cb;\n\t}\n\n\treturn cb;\n}\n\nint\nrte_eth_remove_rx_callback(uint8_t port_id, uint16_t queue_id,\n\t\tstruct rte_eth_rxtx_callback *user_cb)\n{\n#ifndef RTE_ETHDEV_RXTX_CALLBACKS\n\treturn -ENOTSUP;\n#endif\n\t/* Check input parameters. */\n\tif (!rte_eth_dev_is_valid_port(port_id) || user_cb == NULL ||\n\t\t queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) {\n\t\treturn -EINVAL;\n\t}\n\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\tstruct rte_eth_rxtx_callback *cb = dev->post_rx_burst_cbs[queue_id];\n\tstruct rte_eth_rxtx_callback *prev_cb;\n\n\t/* Reset head pointer and remove user cb if first in the list. */\n\tif (cb == user_cb) {\n\t\tdev->post_rx_burst_cbs[queue_id] = user_cb->next;\n\t\treturn 0;\n\t}\n\n\t/* Remove the user cb from the callback list. */\n\tdo {\n\t\tprev_cb = cb;\n\t\tcb = cb->next;\n\n\t\tif (cb == user_cb) {\n\t\t\tprev_cb->next = user_cb->next;\n\t\t\treturn 0;\n\t\t}\n\n\t} while (cb != NULL);\n\n\t/* Callback wasn't found. */\n\treturn -EINVAL;\n}\n\nint\nrte_eth_remove_tx_callback(uint8_t port_id, uint16_t queue_id,\n\t\tstruct rte_eth_rxtx_callback *user_cb)\n{\n#ifndef RTE_ETHDEV_RXTX_CALLBACKS\n\treturn -ENOTSUP;\n#endif\n\t/* Check input parameters. */\n\tif (!rte_eth_dev_is_valid_port(port_id) || user_cb == NULL ||\n\t\t queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) {\n\t\treturn -EINVAL;\n\t}\n\n\tstruct rte_eth_dev *dev = &rte_eth_devices[port_id];\n\tstruct rte_eth_rxtx_callback *cb = dev->pre_tx_burst_cbs[queue_id];\n\tstruct rte_eth_rxtx_callback *prev_cb;\n\n\t/* Reset head pointer and remove user cb if first in the list. */\n\tif (cb == user_cb) {\n\t\tdev->pre_tx_burst_cbs[queue_id] = user_cb->next;\n\t\treturn 0;\n\t}\n\n\t/* Remove the user cb from the callback list. */\n\tdo {\n\t\tprev_cb = cb;\n\t\tcb = cb->next;\n\n\t\tif (cb == user_cb) {\n\t\t\tprev_cb->next = user_cb->next;\n\t\t\treturn 0;\n\t\t}\n\n\t} while (cb != NULL);\n\n\t/* Callback wasn't found. */\n\treturn -EINVAL;\n}\n\nint\nrte_eth_dev_set_mc_addr_list(uint8_t port_id,\n\t\t\t struct ether_addr *mc_addr_set,\n\t\t\t uint32_t nb_mc_addr)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_mc_addr_list, -ENOTSUP);\n\treturn dev->dev_ops->set_mc_addr_list(dev, mc_addr_set, nb_mc_addr);\n}\n\nint\nrte_eth_timesync_enable(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_enable, -ENOTSUP);\n\treturn (*dev->dev_ops->timesync_enable)(dev);\n}\n\nint\nrte_eth_timesync_disable(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_disable, -ENOTSUP);\n\treturn (*dev->dev_ops->timesync_disable)(dev);\n}\n\nint\nrte_eth_timesync_read_rx_timestamp(uint8_t port_id, struct timespec *timestamp,\n\t\t\t\t uint32_t flags)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_rx_timestamp, -ENOTSUP);\n\treturn (*dev->dev_ops->timesync_read_rx_timestamp)(dev, timestamp, flags);\n}\n\nint\nrte_eth_timesync_read_tx_timestamp(uint8_t port_id, struct timespec *timestamp)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\tdev = &rte_eth_devices[port_id];\n\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_tx_timestamp, -ENOTSUP);\n\treturn (*dev->dev_ops->timesync_read_tx_timestamp)(dev, timestamp);\n}\n\nint\nrte_eth_dev_get_reg_length(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_reg_length, -ENOTSUP);\n\treturn (*dev->dev_ops->get_reg_length)(dev);\n}\n\nint\nrte_eth_dev_get_reg_info(uint8_t port_id, struct rte_dev_reg_info *info)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_reg, -ENOTSUP);\n\treturn (*dev->dev_ops->get_reg)(dev, info);\n}\n\nint\nrte_eth_dev_get_eeprom_length(uint8_t port_id)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom_length, -ENOTSUP);\n\treturn (*dev->dev_ops->get_eeprom_length)(dev);\n}\n\nint\nrte_eth_dev_get_eeprom(uint8_t port_id, struct rte_dev_eeprom_info *info)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom, -ENOTSUP);\n\treturn (*dev->dev_ops->get_eeprom)(dev, info);\n}\n\nint\nrte_eth_dev_set_eeprom(uint8_t port_id, struct rte_dev_eeprom_info *info)\n{\n\tstruct rte_eth_dev *dev;\n\n\tVALID_PORTID_OR_ERR_RET(port_id, -ENODEV);\n\n\tdev = &rte_eth_devices[port_id];\n\tFUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_eeprom, -ENOTSUP);\n\treturn (*dev->dev_ops->set_eeprom)(dev, info);\n}\n" }, { "path": "lib/librte_ether/rte_ethdev.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ETHDEV_H_\n#define _RTE_ETHDEV_H_\n\n/**\n * @file\n *\n * RTE Ethernet Device API\n *\n * The Ethernet Device API is composed of two parts:\n *\n * - The application-oriented Ethernet API that includes functions to setup\n * an Ethernet device (configure it, setup its RX and TX queues and start it),\n * to get its MAC address, the speed and the status of its physical link,\n * to receive and to transmit packets, and so on.\n *\n * - The driver-oriented Ethernet API that exports a function allowing\n * an Ethernet Poll Mode Driver (PMD) to simultaneously register itself as\n * an Ethernet device driver and as a PCI driver for a set of matching PCI\n * [Ethernet] devices classes.\n *\n * By default, all the functions of the Ethernet Device API exported by a PMD\n * are lock-free functions which assume to not be invoked in parallel on\n * different logical cores to work on the same target object. For instance,\n * the receive function of a PMD cannot be invoked in parallel on two logical\n * cores to poll the same RX queue [of the same port]. Of course, this function\n * can be invoked in parallel by different logical cores on different RX queues.\n * It is the responsibility of the upper level application to enforce this rule.\n *\n * If needed, parallel accesses by multiple logical cores to shared queues\n * shall be explicitly protected by dedicated inline lock-aware functions\n * built on top of their corresponding lock-free functions of the PMD API.\n *\n * In all functions of the Ethernet API, the Ethernet device is\n * designated by an integer >= 0 named the device port identifier.\n *\n * At the Ethernet driver level, Ethernet devices are represented by a generic\n * data structure of type *rte_eth_dev*.\n *\n * Ethernet devices are dynamically registered during the PCI probing phase\n * performed at EAL initialization time.\n * When an Ethernet device is being probed, an *rte_eth_dev* structure and\n * a new port identifier are allocated for that device. Then, the eth_dev_init()\n * function supplied by the Ethernet driver matching the probed PCI\n * device is invoked to properly initialize the device.\n *\n * The role of the device init function consists of resetting the hardware,\n * checking access to Non-volatile Memory (NVM), reading the MAC address\n * from NVM etc.\n *\n * If the device init operation is successful, the correspondence between\n * the port identifier assigned to the new device and its associated\n * *rte_eth_dev* structure is effectively registered.\n * Otherwise, both the *rte_eth_dev* structure and the port identifier are\n * freed.\n *\n * The functions exported by the application Ethernet API to setup a device\n * designated by its port identifier must be invoked in the following order:\n * - rte_eth_dev_configure()\n * - rte_eth_tx_queue_setup()\n * - rte_eth_rx_queue_setup()\n * - rte_eth_dev_start()\n *\n * Then, the network application can invoke, in any order, the functions\n * exported by the Ethernet API to get the MAC address of a given device, to\n * get the speed and the status of a device physical link, to receive/transmit\n * [burst of] packets, and so on.\n *\n * If the application wants to change the configuration (i.e. call\n * rte_eth_dev_configure(), rte_eth_tx_queue_setup(), or\n * rte_eth_rx_queue_setup()), it must call rte_eth_dev_stop() first to stop the\n * device and then do the reconfiguration before calling rte_eth_dev_start()\n * again. The tramsit and receive functions should not be invoked when the\n * device is stopped.\n *\n * Please note that some configuration is not stored between calls to\n * rte_eth_dev_stop()/rte_eth_dev_start(). The following configuration will\n * be retained:\n *\n * - flow control settings\n * - receive mode configuration (promiscuous mode, hardware checksum mode,\n * RSS/VMDQ settings etc.)\n * - VLAN filtering configuration\n * - MAC addresses supplied to MAC address array\n * - flow director filtering mode (but not filtering rules)\n * - NIC queue statistics mappings\n *\n * Any other configuration will not be stored and will need to be re-entered\n * after a call to rte_eth_dev_start().\n *\n * Finally, a network application can close an Ethernet device by invoking the\n * rte_eth_dev_close() function.\n *\n * Each function of the application Ethernet API invokes a specific function\n * of the PMD that controls the target device designated by its port\n * identifier.\n * For this purpose, all device-specific functions of an Ethernet driver are\n * supplied through a set of pointers contained in a generic structure of type\n * *eth_dev_ops*.\n * The address of the *eth_dev_ops* structure is stored in the *rte_eth_dev*\n * structure by the device init function of the Ethernet driver, which is\n * invoked during the PCI probing phase, as explained earlier.\n *\n * In other words, each function of the Ethernet API simply retrieves the\n * *rte_eth_dev* structure associated with the device port identifier and\n * performs an indirect invocation of the corresponding driver function\n * supplied in the *eth_dev_ops* structure of the *rte_eth_dev* structure.\n *\n * For performance reasons, the address of the burst-oriented RX and TX\n * functions of the Ethernet driver are not contained in the *eth_dev_ops*\n * structure. Instead, they are directly stored at the beginning of the\n * *rte_eth_dev* structure to avoid an extra indirect memory access during\n * their invocation.\n *\n * RTE ethernet device drivers do not use interrupts for transmitting or\n * receiving. Instead, Ethernet drivers export Poll-Mode receive and transmit\n * functions to applications.\n * Both receive and transmit functions are packet-burst oriented to minimize\n * their cost per packet through the following optimizations:\n *\n * - Sharing among multiple packets the incompressible cost of the\n * invocation of receive/transmit functions.\n *\n * - Enabling receive/transmit functions to take advantage of burst-oriented\n * hardware features (L1 cache, prefetch instructions, NIC head/tail\n * registers) to minimize the number of CPU cycles per packet, for instance,\n * by avoiding useless read memory accesses to ring descriptors, or by\n * systematically using arrays of pointers that exactly fit L1 cache line\n * boundaries and sizes.\n *\n * The burst-oriented receive function does not provide any error notification,\n * to avoid the corresponding overhead. As a hint, the upper-level application\n * might check the status of the device link once being systematically returned\n * a 0 value by the receive function of the driver for a given number of tries.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n/* Use this macro to check if LRO API is supported */\n#define RTE_ETHDEV_HAS_LRO_SUPPORT\n\n#include \n#include \n#include \n#include \n#include \n#include \"rte_ether.h\"\n#include \"rte_eth_ctrl.h\"\n#include \"rte_dev_info.h\"\n\nstruct rte_mbuf;\n\n/**\n * A structure used to retrieve statistics for an Ethernet port.\n */\nstruct rte_eth_stats {\n\tuint64_t ipackets; /**< Total number of successfully received packets. */\n\tuint64_t opackets; /**< Total number of successfully transmitted packets.*/\n\tuint64_t ibytes; /**< Total number of successfully received bytes. */\n\tuint64_t obytes; /**< Total number of successfully transmitted bytes. */\n\tuint64_t imissed;\n\t/**< Deprecated; Total of RX missed packets (e.g full FIFO). */\n\tuint64_t ibadcrc;\n\t/**< Deprecated; Total of RX packets with CRC error. */\n\tuint64_t ibadlen;\n\t/**< Deprecated; Total of RX packets with bad length. */\n\tuint64_t ierrors; /**< Total number of erroneous received packets. */\n\tuint64_t oerrors; /**< Total number of failed transmitted packets. */\n\tuint64_t imcasts;\n\t/**< Deprecated; Total number of multicast received packets. */\n\tuint64_t rx_nombuf; /**< Total number of RX mbuf allocation failures. */\n\tuint64_t fdirmatch;\n\t/**< Deprecated; Total number of RX packets matching a filter. */\n\tuint64_t fdirmiss;\n\t/**< Deprecated; Total number of RX packets not matching any filter. */\n\tuint64_t tx_pause_xon;\n\t /**< Deprecated; Total nb. of XON pause frame sent. */\n\tuint64_t rx_pause_xon;\n\t/**< Deprecated; Total nb. of XON pause frame received. */\n\tuint64_t tx_pause_xoff;\n\t/**< Deprecated; Total nb. of XOFF pause frame sent. */\n\tuint64_t rx_pause_xoff;\n\t/**< Deprecated; Total nb. of XOFF pause frame received. */\n\tuint64_t q_ipackets[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n\t/**< Total number of queue RX packets. */\n\tuint64_t q_opackets[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n\t/**< Total number of queue TX packets. */\n\tuint64_t q_ibytes[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n\t/**< Total number of successfully received queue bytes. */\n\tuint64_t q_obytes[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n\t/**< Total number of successfully transmitted queue bytes. */\n\tuint64_t q_errors[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n\t/**< Total number of queue packets received that are dropped. */\n\tuint64_t ilbpackets;\n\t/**< Total number of good packets received from loopback,VF Only */\n\tuint64_t olbpackets;\n\t/**< Total number of good packets transmitted to loopback,VF Only */\n\tuint64_t ilbbytes;\n\t/**< Total number of good bytes received from loopback,VF Only */\n\tuint64_t olbbytes;\n\t/**< Total number of good bytes transmitted to loopback,VF Only */\n};\n\n/**\n * A structure used to retrieve link-level information of an Ethernet port.\n */\nstruct rte_eth_link {\n\tuint16_t link_speed; /**< ETH_LINK_SPEED_[10, 100, 1000, 10000] */\n\tuint16_t link_duplex; /**< ETH_LINK_[HALF_DUPLEX, FULL_DUPLEX] */\n\tuint8_t link_status : 1; /**< 1 -> link up, 0 -> link down */\n}__attribute__((aligned(8))); /**< aligned for atomic64 read/write */\n\n#define ETH_LINK_SPEED_AUTONEG 0 /**< Auto-negotiate link speed. */\n#define ETH_LINK_SPEED_10 10 /**< 10 megabits/second. */\n#define ETH_LINK_SPEED_100 100 /**< 100 megabits/second. */\n#define ETH_LINK_SPEED_1000 1000 /**< 1 gigabits/second. */\n#define ETH_LINK_SPEED_10000 10000 /**< 10 gigabits/second. */\n#define ETH_LINK_SPEED_10G 10000 /**< alias of 10 gigabits/second. */\n#define ETH_LINK_SPEED_20G 20000 /**< 20 gigabits/second. */\n#define ETH_LINK_SPEED_40G 40000 /**< 40 gigabits/second. */\n\n#define ETH_LINK_AUTONEG_DUPLEX 0 /**< Auto-negotiate duplex. */\n#define ETH_LINK_HALF_DUPLEX 1 /**< Half-duplex connection. */\n#define ETH_LINK_FULL_DUPLEX 2 /**< Full-duplex connection. */\n\n/**\n * A structure used to configure the ring threshold registers of an RX/TX\n * queue for an Ethernet port.\n */\nstruct rte_eth_thresh {\n\tuint8_t pthresh; /**< Ring prefetch threshold. */\n\tuint8_t hthresh; /**< Ring host threshold. */\n\tuint8_t wthresh; /**< Ring writeback threshold. */\n};\n\n/**\n * Simple flags are used for rte_eth_conf.rxmode.mq_mode.\n */\n#define ETH_MQ_RX_RSS_FLAG 0x1\n#define ETH_MQ_RX_DCB_FLAG 0x2\n#define ETH_MQ_RX_VMDQ_FLAG 0x4\n\n/**\n * A set of values to identify what method is to be used to route\n * packets to multiple queues.\n */\nenum rte_eth_rx_mq_mode {\n\t/** None of DCB,RSS or VMDQ mode */\n\tETH_MQ_RX_NONE = 0,\n\n\t/** For RX side, only RSS is on */\n\tETH_MQ_RX_RSS = ETH_MQ_RX_RSS_FLAG,\n\t/** For RX side,only DCB is on. */\n\tETH_MQ_RX_DCB = ETH_MQ_RX_DCB_FLAG,\n\t/** Both DCB and RSS enable */\n\tETH_MQ_RX_DCB_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_DCB_FLAG,\n\n\t/** Only VMDQ, no RSS nor DCB */\n\tETH_MQ_RX_VMDQ_ONLY = ETH_MQ_RX_VMDQ_FLAG,\n\t/** RSS mode with VMDQ */\n\tETH_MQ_RX_VMDQ_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_VMDQ_FLAG,\n\t/** Use VMDQ+DCB to route traffic to queues */\n\tETH_MQ_RX_VMDQ_DCB = ETH_MQ_RX_VMDQ_FLAG | ETH_MQ_RX_DCB_FLAG,\n\t/** Enable both VMDQ and DCB in VMDq */\n\tETH_MQ_RX_VMDQ_DCB_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_DCB_FLAG |\n\t\t\t\t ETH_MQ_RX_VMDQ_FLAG,\n};\n\n/**\n * for rx mq mode backward compatible\n */\n#define ETH_RSS ETH_MQ_RX_RSS\n#define VMDQ_DCB ETH_MQ_RX_VMDQ_DCB\n#define ETH_DCB_RX ETH_MQ_RX_DCB\n\n/**\n * A set of values to identify what method is to be used to transmit\n * packets using multi-TCs.\n */\nenum rte_eth_tx_mq_mode {\n\tETH_MQ_TX_NONE = 0, /**< It is in neither DCB nor VT mode. */\n\tETH_MQ_TX_DCB, /**< For TX side,only DCB is on. */\n\tETH_MQ_TX_VMDQ_DCB,\t/**< For TX side,both DCB and VT is on. */\n\tETH_MQ_TX_VMDQ_ONLY, /**< Only VT on, no DCB */\n};\n\n/**\n * for tx mq mode backward compatible\n */\n#define ETH_DCB_NONE ETH_MQ_TX_NONE\n#define ETH_VMDQ_DCB_TX ETH_MQ_TX_VMDQ_DCB\n#define ETH_DCB_TX ETH_MQ_TX_DCB\n\n/**\n * A structure used to configure the RX features of an Ethernet port.\n */\nstruct rte_eth_rxmode {\n\t/** The multi-queue packet distribution mode to be used, e.g. RSS. */\n\tenum rte_eth_rx_mq_mode mq_mode;\n\tuint32_t max_rx_pkt_len; /**< Only used if jumbo_frame enabled. */\n\tuint16_t split_hdr_size; /**< hdr buf size (header_split enabled).*/\n\tuint16_t header_split : 1, /**< Header Split enable. */\n\t\thw_ip_checksum : 1, /**< IP/UDP/TCP checksum offload enable. */\n\t\thw_vlan_filter : 1, /**< VLAN filter enable. */\n\t\thw_vlan_strip : 1, /**< VLAN strip enable. */\n\t\thw_vlan_extend : 1, /**< Extended VLAN enable. */\n\t\tjumbo_frame : 1, /**< Jumbo Frame Receipt enable. */\n\t\thw_strip_crc : 1, /**< Enable CRC stripping by hardware. */\n\t\tenable_scatter : 1, /**< Enable scatter packets rx handler */\n\t\tenable_lro : 1; /**< Enable LRO */\n};\n\n/**\n * A structure used to configure the Receive Side Scaling (RSS) feature\n * of an Ethernet port.\n * If not NULL, the *rss_key* pointer of the *rss_conf* structure points\n * to an array holding the RSS key to use for hashing specific header\n * fields of received packets. The length of this array should be indicated\n * by *rss_key_len* below. Otherwise, a default random hash key is used by\n * the device driver.\n *\n * The *rss_key_len* field of the *rss_conf* structure indicates the length\n * in bytes of the array pointed by *rss_key*. To be compatible, this length\n * will be checked in i40e only. Others assume 40 bytes to be used as before.\n *\n * The *rss_hf* field of the *rss_conf* structure indicates the different\n * types of IPv4/IPv6 packets to which the RSS hashing must be applied.\n * Supplying an *rss_hf* equal to zero disables the RSS feature.\n */\nstruct rte_eth_rss_conf {\n\tuint8_t *rss_key; /**< If not NULL, 40-byte hash key. */\n\tuint8_t rss_key_len; /**< hash key length in bytes. */\n\tuint64_t rss_hf; /**< Hash functions to apply - see below. */\n};\n\n/*\n * The RSS offload types are defined based on flow types which are defined\n * in rte_eth_ctrl.h. Different NIC hardwares may support different RSS offload\n * types. The supported flow types or RSS offload types can be queried by\n * rte_eth_dev_info_get().\n */\n#define ETH_RSS_IPV4 (1ULL << RTE_ETH_FLOW_IPV4)\n#define ETH_RSS_FRAG_IPV4 (1ULL << RTE_ETH_FLOW_FRAG_IPV4)\n#define ETH_RSS_NONFRAG_IPV4_TCP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP)\n#define ETH_RSS_NONFRAG_IPV4_UDP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP)\n#define ETH_RSS_NONFRAG_IPV4_SCTP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP)\n#define ETH_RSS_NONFRAG_IPV4_OTHER (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER)\n#define ETH_RSS_IPV6 (1ULL << RTE_ETH_FLOW_IPV6)\n#define ETH_RSS_FRAG_IPV6 (1ULL << RTE_ETH_FLOW_FRAG_IPV6)\n#define ETH_RSS_NONFRAG_IPV6_TCP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP)\n#define ETH_RSS_NONFRAG_IPV6_UDP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP)\n#define ETH_RSS_NONFRAG_IPV6_SCTP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP)\n#define ETH_RSS_NONFRAG_IPV6_OTHER (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER)\n#define ETH_RSS_L2_PAYLOAD (1ULL << RTE_ETH_FLOW_L2_PAYLOAD)\n#define ETH_RSS_IPV6_EX (1ULL << RTE_ETH_FLOW_IPV6_EX)\n#define ETH_RSS_IPV6_TCP_EX (1ULL << RTE_ETH_FLOW_IPV6_TCP_EX)\n#define ETH_RSS_IPV6_UDP_EX (1ULL << RTE_ETH_FLOW_IPV6_UDP_EX)\n\n#define ETH_RSS_IP ( \\\n\tETH_RSS_IPV4 | \\\n\tETH_RSS_FRAG_IPV4 | \\\n\tETH_RSS_NONFRAG_IPV4_OTHER | \\\n\tETH_RSS_IPV6 | \\\n\tETH_RSS_FRAG_IPV6 | \\\n\tETH_RSS_NONFRAG_IPV6_OTHER | \\\n\tETH_RSS_IPV6_EX)\n\n#define ETH_RSS_UDP ( \\\n\tETH_RSS_NONFRAG_IPV4_UDP | \\\n\tETH_RSS_NONFRAG_IPV6_UDP | \\\n\tETH_RSS_IPV6_UDP_EX)\n\n#define ETH_RSS_TCP ( \\\n\tETH_RSS_NONFRAG_IPV4_TCP | \\\n\tETH_RSS_NONFRAG_IPV6_TCP | \\\n\tETH_RSS_IPV6_TCP_EX)\n\n#define ETH_RSS_SCTP ( \\\n\tETH_RSS_NONFRAG_IPV4_SCTP | \\\n\tETH_RSS_NONFRAG_IPV6_SCTP)\n\n/**< Mask of valid RSS hash protocols */\n#define ETH_RSS_PROTO_MASK ( \\\n\tETH_RSS_IPV4 | \\\n\tETH_RSS_FRAG_IPV4 | \\\n\tETH_RSS_NONFRAG_IPV4_TCP | \\\n\tETH_RSS_NONFRAG_IPV4_UDP | \\\n\tETH_RSS_NONFRAG_IPV4_SCTP | \\\n\tETH_RSS_NONFRAG_IPV4_OTHER | \\\n\tETH_RSS_IPV6 | \\\n\tETH_RSS_FRAG_IPV6 | \\\n\tETH_RSS_NONFRAG_IPV6_TCP | \\\n\tETH_RSS_NONFRAG_IPV6_UDP | \\\n\tETH_RSS_NONFRAG_IPV6_SCTP | \\\n\tETH_RSS_NONFRAG_IPV6_OTHER | \\\n\tETH_RSS_L2_PAYLOAD | \\\n\tETH_RSS_IPV6_EX | \\\n\tETH_RSS_IPV6_TCP_EX | \\\n\tETH_RSS_IPV6_UDP_EX)\n\n/*\n * Definitions used for redirection table entry size.\n * Some RSS RETA sizes may not be supported by some drivers, check the\n * documentation or the description of relevant functions for more details.\n */\n#define ETH_RSS_RETA_SIZE_64 64\n#define ETH_RSS_RETA_SIZE_128 128\n#define ETH_RSS_RETA_SIZE_512 512\n#define RTE_RETA_GROUP_SIZE 64\n\n/* Definitions used for VMDQ and DCB functionality */\n#define ETH_VMDQ_MAX_VLAN_FILTERS 64 /**< Maximum nb. of VMDQ vlan filters. */\n#define ETH_DCB_NUM_USER_PRIORITIES 8 /**< Maximum nb. of DCB priorities. */\n#define ETH_VMDQ_DCB_NUM_QUEUES 128 /**< Maximum nb. of VMDQ DCB queues. */\n#define ETH_DCB_NUM_QUEUES 128 /**< Maximum nb. of DCB queues. */\n\n/* DCB capability defines */\n#define ETH_DCB_PG_SUPPORT 0x00000001 /**< Priority Group(ETS) support. */\n#define ETH_DCB_PFC_SUPPORT 0x00000002 /**< Priority Flow Control support. */\n\n/* Definitions used for VLAN Offload functionality */\n#define ETH_VLAN_STRIP_OFFLOAD 0x0001 /**< VLAN Strip On/Off */\n#define ETH_VLAN_FILTER_OFFLOAD 0x0002 /**< VLAN Filter On/Off */\n#define ETH_VLAN_EXTEND_OFFLOAD 0x0004 /**< VLAN Extend On/Off */\n\n/* Definitions used for mask VLAN setting */\n#define ETH_VLAN_STRIP_MASK 0x0001 /**< VLAN Strip setting mask */\n#define ETH_VLAN_FILTER_MASK 0x0002 /**< VLAN Filter setting mask*/\n#define ETH_VLAN_EXTEND_MASK 0x0004 /**< VLAN Extend setting mask*/\n#define ETH_VLAN_ID_MAX 0x0FFF /**< VLAN ID is in lower 12 bits*/\n\n/* Definitions used for receive MAC address */\n#define ETH_NUM_RECEIVE_MAC_ADDR 128 /**< Maximum nb. of receive mac addr. */\n\n/* Definitions used for unicast hash */\n#define ETH_VMDQ_NUM_UC_HASH_ARRAY 128 /**< Maximum nb. of UC hash array. */\n\n/* Definitions used for VMDQ pool rx mode setting */\n#define ETH_VMDQ_ACCEPT_UNTAG 0x0001 /**< accept untagged packets. */\n#define ETH_VMDQ_ACCEPT_HASH_MC 0x0002 /**< accept packets in multicast table . */\n#define ETH_VMDQ_ACCEPT_HASH_UC 0x0004 /**< accept packets in unicast table. */\n#define ETH_VMDQ_ACCEPT_BROADCAST 0x0008 /**< accept broadcast packets. */\n#define ETH_VMDQ_ACCEPT_MULTICAST 0x0010 /**< multicast promiscuous. */\n\n/** Maximum nb. of vlan per mirror rule */\n#define ETH_MIRROR_MAX_VLANS 64\n\n#define ETH_MIRROR_VIRTUAL_POOL_UP 0x01 /**< Virtual Pool uplink Mirroring. */\n#define ETH_MIRROR_UPLINK_PORT 0x02 /**< Uplink Port Mirroring. */\n#define ETH_MIRROR_DOWNLINK_PORT 0x04 /**< Downlink Port Mirroring. */\n#define ETH_MIRROR_VLAN 0x08 /**< VLAN Mirroring. */\n#define ETH_MIRROR_VIRTUAL_POOL_DOWN 0x10 /**< Virtual Pool downlink Mirroring. */\n\n/**\n * A structure used to configure VLAN traffic mirror of an Ethernet port.\n */\nstruct rte_eth_vlan_mirror {\n\tuint64_t vlan_mask; /**< mask for valid VLAN ID. */\n\t/** VLAN ID list for vlan mirroring. */\n\tuint16_t vlan_id[ETH_MIRROR_MAX_VLANS];\n};\n\n/**\n * A structure used to configure traffic mirror of an Ethernet port.\n */\nstruct rte_eth_mirror_conf {\n\tuint8_t rule_type; /**< Mirroring rule type */\n\tuint8_t dst_pool; /**< Destination pool for this mirror rule. */\n\tuint64_t pool_mask; /**< Bitmap of pool for pool mirroring */\n\t/** VLAN ID setting for VLAN mirroring. */\n\tstruct rte_eth_vlan_mirror vlan;\n};\n\n/**\n * A structure used to configure 64 entries of Redirection Table of the\n * Receive Side Scaling (RSS) feature of an Ethernet port. To configure\n * more than 64 entries supported by hardware, an array of this structure\n * is needed.\n */\nstruct rte_eth_rss_reta_entry64 {\n\tuint64_t mask;\n\t/**< Mask bits indicate which entries need to be updated/queried. */\n\tuint8_t reta[RTE_RETA_GROUP_SIZE];\n\t/**< Group of 64 redirection table entries. */\n};\n\n/**\n * This enum indicates the possible number of traffic classes\n * in DCB configratioins\n */\nenum rte_eth_nb_tcs {\n\tETH_4_TCS = 4, /**< 4 TCs with DCB. */\n\tETH_8_TCS = 8 /**< 8 TCs with DCB. */\n};\n\n/**\n * This enum indicates the possible number of queue pools\n * in VMDQ configurations.\n */\nenum rte_eth_nb_pools {\n\tETH_8_POOLS = 8, /**< 8 VMDq pools. */\n\tETH_16_POOLS = 16, /**< 16 VMDq pools. */\n\tETH_32_POOLS = 32, /**< 32 VMDq pools. */\n\tETH_64_POOLS = 64 /**< 64 VMDq pools. */\n};\n\n/* This structure may be extended in future. */\nstruct rte_eth_dcb_rx_conf {\n\tenum rte_eth_nb_tcs nb_tcs; /**< Possible DCB TCs, 4 or 8 TCs */\n\tuint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];\n\t/**< Possible DCB queue,4 or 8. */\n};\n\nstruct rte_eth_vmdq_dcb_tx_conf {\n\tenum rte_eth_nb_pools nb_queue_pools; /**< With DCB, 16 or 32 pools. */\n\tuint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];\n\t/**< Possible DCB queue,4 or 8. */\n};\n\nstruct rte_eth_dcb_tx_conf {\n\tenum rte_eth_nb_tcs nb_tcs; /**< Possible DCB TCs, 4 or 8 TCs. */\n\tuint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];\n\t/**< Possible DCB queue,4 or 8. */\n};\n\nstruct rte_eth_vmdq_tx_conf {\n\tenum rte_eth_nb_pools nb_queue_pools; /**< VMDq mode, 64 pools. */\n};\n\n/**\n * A structure used to configure the VMDQ+DCB feature\n * of an Ethernet port.\n *\n * Using this feature, packets are routed to a pool of queues, based\n * on the vlan id in the vlan tag, and then to a specific queue within\n * that pool, using the user priority vlan tag field.\n *\n * A default pool may be used, if desired, to route all traffic which\n * does not match the vlan filter rules.\n */\nstruct rte_eth_vmdq_dcb_conf {\n\tenum rte_eth_nb_pools nb_queue_pools; /**< With DCB, 16 or 32 pools */\n\tuint8_t enable_default_pool; /**< If non-zero, use a default pool */\n\tuint8_t default_pool; /**< The default pool, if applicable */\n\tuint8_t nb_pool_maps; /**< We can have up to 64 filters/mappings */\n\tstruct {\n\t\tuint16_t vlan_id; /**< The vlan id of the received frame */\n\t\tuint64_t pools; /**< Bitmask of pools for packet rx */\n\t} pool_map[ETH_VMDQ_MAX_VLAN_FILTERS]; /**< VMDq vlan pool maps. */\n\tuint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];\n\t/**< Selects a queue in a pool */\n};\n\nstruct rte_eth_vmdq_rx_conf {\n\tenum rte_eth_nb_pools nb_queue_pools; /**< VMDq only mode, 8 or 64 pools */\n\tuint8_t enable_default_pool; /**< If non-zero, use a default pool */\n\tuint8_t default_pool; /**< The default pool, if applicable */\n\tuint8_t enable_loop_back; /**< Enable VT loop back */\n\tuint8_t nb_pool_maps; /**< We can have up to 64 filters/mappings */\n\tuint32_t rx_mode; /**< Flags from ETH_VMDQ_ACCEPT_* */\n\tstruct {\n\t\tuint16_t vlan_id; /**< The vlan id of the received frame */\n\t\tuint64_t pools; /**< Bitmask of pools for packet rx */\n\t} pool_map[ETH_VMDQ_MAX_VLAN_FILTERS]; /**< VMDq vlan pool maps. */\n};\n\n/**\n * A structure used to configure the TX features of an Ethernet port.\n */\nstruct rte_eth_txmode {\n\tenum rte_eth_tx_mq_mode mq_mode; /**< TX multi-queues mode. */\n\n\t/* For i40e specifically */\n\tuint16_t pvid;\n\tuint8_t hw_vlan_reject_tagged : 1,\n\t\t/**< If set, reject sending out tagged pkts */\n\t\thw_vlan_reject_untagged : 1,\n\t\t/**< If set, reject sending out untagged pkts */\n\t\thw_vlan_insert_pvid : 1;\n\t\t/**< If set, enable port based VLAN insertion */\n};\n\n/**\n * A structure used to configure an RX ring of an Ethernet port.\n */\nstruct rte_eth_rxconf {\n\tstruct rte_eth_thresh rx_thresh; /**< RX ring threshold registers. */\n\tuint16_t rx_free_thresh; /**< Drives the freeing of RX descriptors. */\n\tuint8_t rx_drop_en; /**< Drop packets if no descriptors are available. */\n\tuint8_t rx_deferred_start; /**< Do not start queue with rte_eth_dev_start(). */\n};\n\n#define ETH_TXQ_FLAGS_NOMULTSEGS 0x0001 /**< nb_segs=1 for all mbufs */\n#define ETH_TXQ_FLAGS_NOREFCOUNT 0x0002 /**< refcnt can be ignored */\n#define ETH_TXQ_FLAGS_NOMULTMEMP 0x0004 /**< all bufs come from same mempool */\n#define ETH_TXQ_FLAGS_NOVLANOFFL 0x0100 /**< disable VLAN offload */\n#define ETH_TXQ_FLAGS_NOXSUMSCTP 0x0200 /**< disable SCTP checksum offload */\n#define ETH_TXQ_FLAGS_NOXSUMUDP 0x0400 /**< disable UDP checksum offload */\n#define ETH_TXQ_FLAGS_NOXSUMTCP 0x0800 /**< disable TCP checksum offload */\n#define ETH_TXQ_FLAGS_NOOFFLOADS \\\n\t\t(ETH_TXQ_FLAGS_NOVLANOFFL | ETH_TXQ_FLAGS_NOXSUMSCTP | \\\n\t\t ETH_TXQ_FLAGS_NOXSUMUDP | ETH_TXQ_FLAGS_NOXSUMTCP)\n#define ETH_TXQ_FLAGS_NOXSUMS \\\n\t\t(ETH_TXQ_FLAGS_NOXSUMSCTP | ETH_TXQ_FLAGS_NOXSUMUDP | \\\n\t\t ETH_TXQ_FLAGS_NOXSUMTCP)\n/**\n * A structure used to configure a TX ring of an Ethernet port.\n */\nstruct rte_eth_txconf {\n\tstruct rte_eth_thresh tx_thresh; /**< TX ring threshold registers. */\n\tuint16_t tx_rs_thresh; /**< Drives the setting of RS bit on TXDs. */\n\tuint16_t tx_free_thresh; /**< Start freeing TX buffers if there are\n\t\t\t\t less free descriptors than this value. */\n\n\tuint32_t txq_flags; /**< Set flags for the Tx queue */\n\tuint8_t tx_deferred_start; /**< Do not start queue with rte_eth_dev_start(). */\n};\n\n/**\n * This enum indicates the flow control mode\n */\nenum rte_eth_fc_mode {\n\tRTE_FC_NONE = 0, /**< Disable flow control. */\n\tRTE_FC_RX_PAUSE, /**< RX pause frame, enable flowctrl on TX side. */\n\tRTE_FC_TX_PAUSE, /**< TX pause frame, enable flowctrl on RX side. */\n\tRTE_FC_FULL /**< Enable flow control on both side. */\n};\n\n/**\n * A structure used to configure Ethernet flow control parameter.\n * These parameters will be configured into the register of the NIC.\n * Please refer to the corresponding data sheet for proper value.\n */\nstruct rte_eth_fc_conf {\n\tuint32_t high_water; /**< High threshold value to trigger XOFF */\n\tuint32_t low_water; /**< Low threshold value to trigger XON */\n\tuint16_t pause_time; /**< Pause quota in the Pause frame */\n\tuint16_t send_xon; /**< Is XON frame need be sent */\n\tenum rte_eth_fc_mode mode; /**< Link flow control mode */\n\tuint8_t mac_ctrl_frame_fwd; /**< Forward MAC control frames */\n\tuint8_t autoneg; /**< Use Pause autoneg */\n};\n\n/**\n * A structure used to configure Ethernet priority flow control parameter.\n * These parameters will be configured into the register of the NIC.\n * Please refer to the corresponding data sheet for proper value.\n */\nstruct rte_eth_pfc_conf {\n\tstruct rte_eth_fc_conf fc; /**< General flow control parameter. */\n\tuint8_t priority; /**< VLAN User Priority. */\n};\n\n/**\n * Memory space that can be configured to store Flow Director filters\n * in the board memory.\n */\nenum rte_fdir_pballoc_type {\n\tRTE_FDIR_PBALLOC_64K = 0, /**< 64k. */\n\tRTE_FDIR_PBALLOC_128K, /**< 128k. */\n\tRTE_FDIR_PBALLOC_256K, /**< 256k. */\n};\n\n/**\n * Select report mode of FDIR hash information in RX descriptors.\n */\nenum rte_fdir_status_mode {\n\tRTE_FDIR_NO_REPORT_STATUS = 0, /**< Never report FDIR hash. */\n\tRTE_FDIR_REPORT_STATUS, /**< Only report FDIR hash for matching pkts. */\n\tRTE_FDIR_REPORT_STATUS_ALWAYS, /**< Always report FDIR hash. */\n};\n\n/**\n * A structure used to configure the Flow Director (FDIR) feature\n * of an Ethernet port.\n *\n * If mode is RTE_FDIR_DISABLE, the pballoc value is ignored.\n */\nstruct rte_fdir_conf {\n\tenum rte_fdir_mode mode; /**< Flow Director mode. */\n\tenum rte_fdir_pballoc_type pballoc; /**< Space for FDIR filters. */\n\tenum rte_fdir_status_mode status; /**< How to report FDIR hash. */\n\t/** RX queue of packets matching a \"drop\" filter in perfect mode. */\n\tuint8_t drop_queue;\n\tstruct rte_eth_fdir_masks mask;\n\tstruct rte_eth_fdir_flex_conf flex_conf;\n\t/**< Flex payload configuration. */\n};\n\n/**\n * UDP tunneling configuration.\n */\nstruct rte_eth_udp_tunnel {\n\tuint16_t udp_port;\n\tuint8_t prot_type;\n};\n\n/**\n * Possible l4type of FDIR filters.\n */\nenum rte_l4type {\n\tRTE_FDIR_L4TYPE_NONE = 0, /**< None. */\n\tRTE_FDIR_L4TYPE_UDP, /**< UDP. */\n\tRTE_FDIR_L4TYPE_TCP, /**< TCP. */\n\tRTE_FDIR_L4TYPE_SCTP, /**< SCTP. */\n};\n\n/**\n * Select IPv4 or IPv6 FDIR filters.\n */\nenum rte_iptype {\n\tRTE_FDIR_IPTYPE_IPV4 = 0, /**< IPv4. */\n\tRTE_FDIR_IPTYPE_IPV6 , /**< IPv6. */\n};\n\n/**\n * A structure used to define a FDIR packet filter.\n */\nstruct rte_fdir_filter {\n\tuint16_t flex_bytes; /**< Flex bytes value to match. */\n\tuint16_t vlan_id; /**< VLAN ID value to match, 0 otherwise. */\n\tuint16_t port_src; /**< Source port to match, 0 otherwise. */\n\tuint16_t port_dst; /**< Destination port to match, 0 otherwise. */\n\tunion {\n\t\tuint32_t ipv4_addr; /**< IPv4 source address to match. */\n\t\tuint32_t ipv6_addr[4]; /**< IPv6 source address to match. */\n\t} ip_src; /**< IPv4/IPv6 source address to match (union of above). */\n\tunion {\n\t\tuint32_t ipv4_addr; /**< IPv4 destination address to match. */\n\t\tuint32_t ipv6_addr[4]; /**< IPv6 destination address to match */\n\t} ip_dst; /**< IPv4/IPv6 destination address to match (union of above). */\n\tenum rte_l4type l4type; /**< l4type to match: NONE/UDP/TCP/SCTP. */\n\tenum rte_iptype iptype; /**< IP packet type to match: IPv4 or IPv6. */\n};\n\n/**\n * A structure used to configure FDIR masks that are used by the device\n * to match the various fields of RX packet headers.\n * @note The only_ip_flow field has the opposite meaning compared to other\n * masks!\n */\nstruct rte_fdir_masks {\n\t/** When set to 1, packet l4type is \\b NOT relevant in filters, and\n\t source and destination port masks must be set to zero. */\n\tuint8_t only_ip_flow;\n\t/** If set to 1, vlan_id is relevant in filters. */\n\tuint8_t vlan_id;\n\t/** If set to 1, vlan_prio is relevant in filters. */\n\tuint8_t vlan_prio;\n\t/** If set to 1, flexbytes is relevant in filters. */\n\tuint8_t flexbytes;\n\t/** If set to 1, set the IPv6 masks. Otherwise set the IPv4 masks. */\n\tuint8_t set_ipv6_mask;\n\t/** When set to 1, comparison of destination IPv6 address with IP6AT\n\t registers is meaningful. */\n\tuint8_t comp_ipv6_dst;\n\t/** Mask of Destination IPv4 Address. All bits set to 1 define the\n\t relevant bits to use in the destination address of an IPv4 packet\n\t when matching it against FDIR filters. */\n\tuint32_t dst_ipv4_mask;\n\t/** Mask of Source IPv4 Address. All bits set to 1 define\n\t the relevant bits to use in the source address of an IPv4 packet\n\t when matching it against FDIR filters. */\n\tuint32_t src_ipv4_mask;\n\t/** Mask of Source IPv6 Address. All bits set to 1 define the\n\t relevant BYTES to use in the source address of an IPv6 packet\n\t when matching it against FDIR filters. */\n\tuint16_t dst_ipv6_mask;\n\t/** Mask of Destination IPv6 Address. All bits set to 1 define the\n\t relevant BYTES to use in the destination address of an IPv6 packet\n\t when matching it against FDIR filters. */\n\tuint16_t src_ipv6_mask;\n\t/** Mask of Source Port. All bits set to 1 define the relevant\n\t bits to use in the source port of an IP packets when matching it\n\t against FDIR filters. */\n\tuint16_t src_port_mask;\n\t/** Mask of Destination Port. All bits set to 1 define the relevant\n\t bits to use in the destination port of an IP packet when matching it\n\t against FDIR filters. */\n\tuint16_t dst_port_mask;\n};\n\n/**\n * A structure used to report the status of the flow director filters in use.\n */\nstruct rte_eth_fdir {\n\t/** Number of filters with collision indication. */\n\tuint16_t collision;\n\t/** Number of free (non programmed) filters. */\n\tuint16_t free;\n\t/** The Lookup hash value of the added filter that updated the value\n\t of the MAXLEN field */\n\tuint16_t maxhash;\n\t/** Longest linked list of filters in the table. */\n\tuint8_t maxlen;\n\t/** Number of added filters. */\n\tuint64_t add;\n\t/** Number of removed filters. */\n\tuint64_t remove;\n\t/** Number of failed added filters (no more space in device). */\n\tuint64_t f_add;\n\t/** Number of failed removed filters. */\n\tuint64_t f_remove;\n};\n\n/**\n * A structure used to enable/disable specific device interrupts.\n */\nstruct rte_intr_conf {\n\t/** enable/disable lsc interrupt. 0 (default) - disable, 1 enable */\n\tuint16_t lsc;\n#ifdef RTE_NEXT_ABI\n\t/** enable/disable rxq interrupt. 0 (default) - disable, 1 enable */\n\tuint16_t rxq;\n#endif\n};\n\n/**\n * A structure used to configure an Ethernet port.\n * Depending upon the RX multi-queue mode, extra advanced\n * configuration settings may be needed.\n */\nstruct rte_eth_conf {\n\tuint16_t link_speed;\n\t/**< ETH_LINK_SPEED_10[0|00|000], or 0 for autonegotation */\n\tuint16_t link_duplex;\n\t/**< ETH_LINK_[HALF_DUPLEX|FULL_DUPLEX], or 0 for autonegotation */\n\tstruct rte_eth_rxmode rxmode; /**< Port RX configuration. */\n\tstruct rte_eth_txmode txmode; /**< Port TX configuration. */\n\tuint32_t lpbk_mode; /**< Loopback operation mode. By default the value\n\t\t\t is 0, meaning the loopback mode is disabled.\n\t\t\t\t Read the datasheet of given ethernet controller\n\t\t\t\t for details. The possible values of this field\n\t\t\t\t are defined in implementation of each driver. */\n\tstruct {\n\t\tstruct rte_eth_rss_conf rss_conf; /**< Port RSS configuration */\n\t\tstruct rte_eth_vmdq_dcb_conf vmdq_dcb_conf;\n\t\t/**< Port vmdq+dcb configuration. */\n\t\tstruct rte_eth_dcb_rx_conf dcb_rx_conf;\n\t\t/**< Port dcb RX configuration. */\n\t\tstruct rte_eth_vmdq_rx_conf vmdq_rx_conf;\n\t\t/**< Port vmdq RX configuration. */\n\t} rx_adv_conf; /**< Port RX filtering configuration (union). */\n\tunion {\n\t\tstruct rte_eth_vmdq_dcb_tx_conf vmdq_dcb_tx_conf;\n\t\t/**< Port vmdq+dcb TX configuration. */\n\t\tstruct rte_eth_dcb_tx_conf dcb_tx_conf;\n\t\t/**< Port dcb TX configuration. */\n\t\tstruct rte_eth_vmdq_tx_conf vmdq_tx_conf;\n\t\t/**< Port vmdq TX configuration. */\n\t} tx_adv_conf; /**< Port TX DCB configuration (union). */\n\t/** Currently,Priority Flow Control(PFC) are supported,if DCB with PFC\n\t is needed,and the variable must be set ETH_DCB_PFC_SUPPORT. */\n\tuint32_t dcb_capability_en;\n\tstruct rte_fdir_conf fdir_conf; /**< FDIR configuration. */\n\tstruct rte_intr_conf intr_conf; /**< Interrupt mode configuration. */\n};\n\n/**\n * A structure used to retrieve the contextual information of\n * an Ethernet device, such as the controlling driver of the device,\n * its PCI context, etc...\n */\n\n/**\n * RX offload capabilities of a device.\n */\n#define DEV_RX_OFFLOAD_VLAN_STRIP 0x00000001\n#define DEV_RX_OFFLOAD_IPV4_CKSUM 0x00000002\n#define DEV_RX_OFFLOAD_UDP_CKSUM 0x00000004\n#define DEV_RX_OFFLOAD_TCP_CKSUM 0x00000008\n#define DEV_RX_OFFLOAD_TCP_LRO 0x00000010\n#define DEV_RX_OFFLOAD_QINQ_STRIP 0x00000020\n\n/**\n * TX offload capabilities of a device.\n */\n#define DEV_TX_OFFLOAD_VLAN_INSERT 0x00000001\n#define DEV_TX_OFFLOAD_IPV4_CKSUM 0x00000002\n#define DEV_TX_OFFLOAD_UDP_CKSUM 0x00000004\n#define DEV_TX_OFFLOAD_TCP_CKSUM 0x00000008\n#define DEV_TX_OFFLOAD_SCTP_CKSUM 0x00000010\n#define DEV_TX_OFFLOAD_TCP_TSO 0x00000020\n#define DEV_TX_OFFLOAD_UDP_TSO 0x00000040\n#define DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM 0x00000080 /**< Used for tunneling packet. */\n#define DEV_TX_OFFLOAD_QINQ_INSERT 0x00000100\n\nstruct rte_eth_dev_info {\n\tstruct rte_pci_device *pci_dev; /**< Device PCI information. */\n\tconst char *driver_name; /**< Device Driver name. */\n\tunsigned int if_index; /**< Index to bound host interface, or 0 if none.\n\t\tUse if_indextoname() to translate into an interface name. */\n\tuint32_t min_rx_bufsize; /**< Minimum size of RX buffer. */\n\tuint32_t max_rx_pktlen; /**< Maximum configurable length of RX pkt. */\n\tuint16_t max_rx_queues; /**< Maximum number of RX queues. */\n\tuint16_t max_tx_queues; /**< Maximum number of TX queues. */\n\tuint32_t max_mac_addrs; /**< Maximum number of MAC addresses. */\n\tuint32_t max_hash_mac_addrs;\n\t/** Maximum number of hash MAC addresses for MTA and UTA. */\n\tuint16_t max_vfs; /**< Maximum number of VFs. */\n\tuint16_t max_vmdq_pools; /**< Maximum number of VMDq pools. */\n\tuint32_t rx_offload_capa; /**< Device RX offload capabilities. */\n\tuint32_t tx_offload_capa; /**< Device TX offload capabilities. */\n\tuint16_t reta_size;\n\t/**< Device redirection table size, the total number of entries. */\n\tuint8_t hash_key_size; /**< Hash key size in bytes */\n\t/** Bit mask of RSS offloads, the bit offset also means flow type */\n\tuint64_t flow_type_rss_offloads;\n\tstruct rte_eth_rxconf default_rxconf; /**< Default RX configuration */\n\tstruct rte_eth_txconf default_txconf; /**< Default TX configuration */\n\tuint16_t vmdq_queue_base; /**< First queue ID for VMDQ pools. */\n\tuint16_t vmdq_queue_num; /**< Queue number for VMDQ pools. */\n\tuint16_t vmdq_pool_base; /**< First ID of VMDQ pools. */\n};\n\n/** Maximum name length for extended statistics counters */\n#define RTE_ETH_XSTATS_NAME_SIZE 64\n\n/**\n * An Ethernet device extended statistic structure\n *\n * This structure is used by ethdev->eth_xstats_get() to provide\n * statistics that are not provided in the generic rte_eth_stats\n * structure.\n */\nstruct rte_eth_xstats {\n\tchar name[RTE_ETH_XSTATS_NAME_SIZE];\n\tuint64_t value;\n};\n\nstruct rte_eth_dev;\n\nstruct rte_eth_dev_callback;\n/** @internal Structure to keep track of registered callbacks */\nTAILQ_HEAD(rte_eth_dev_cb_list, rte_eth_dev_callback);\n\n/*\n * Definitions of all functions exported by an Ethernet driver through the\n * the generic structure of type *eth_dev_ops* supplied in the *rte_eth_dev*\n * structure associated with an Ethernet device.\n */\n\ntypedef int (*eth_dev_configure_t)(struct rte_eth_dev *dev);\n/**< @internal Ethernet device configuration. */\n\ntypedef int (*eth_dev_start_t)(struct rte_eth_dev *dev);\n/**< @internal Function used to start a configured Ethernet device. */\n\ntypedef void (*eth_dev_stop_t)(struct rte_eth_dev *dev);\n/**< @internal Function used to stop a configured Ethernet device. */\n\ntypedef int (*eth_dev_set_link_up_t)(struct rte_eth_dev *dev);\n/**< @internal Function used to link up a configured Ethernet device. */\n\ntypedef int (*eth_dev_set_link_down_t)(struct rte_eth_dev *dev);\n/**< @internal Function used to link down a configured Ethernet device. */\n\ntypedef void (*eth_dev_close_t)(struct rte_eth_dev *dev);\n/**< @internal Function used to close a configured Ethernet device. */\n\ntypedef void (*eth_promiscuous_enable_t)(struct rte_eth_dev *dev);\n/**< @internal Function used to enable the RX promiscuous mode of an Ethernet device. */\n\ntypedef void (*eth_promiscuous_disable_t)(struct rte_eth_dev *dev);\n/**< @internal Function used to disable the RX promiscuous mode of an Ethernet device. */\n\ntypedef void (*eth_allmulticast_enable_t)(struct rte_eth_dev *dev);\n/**< @internal Enable the receipt of all multicast packets by an Ethernet device. */\n\ntypedef void (*eth_allmulticast_disable_t)(struct rte_eth_dev *dev);\n/**< @internal Disable the receipt of all multicast packets by an Ethernet device. */\n\ntypedef int (*eth_link_update_t)(struct rte_eth_dev *dev,\n\t\t\t\tint wait_to_complete);\n/**< @internal Get link speed, duplex mode and state (up/down) of an Ethernet device. */\n\ntypedef void (*eth_stats_get_t)(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_stats *igb_stats);\n/**< @internal Get global I/O statistics of an Ethernet device. */\n\ntypedef void (*eth_stats_reset_t)(struct rte_eth_dev *dev);\n/**< @internal Reset global I/O statistics of an Ethernet device to 0. */\n\ntypedef int (*eth_xstats_get_t)(struct rte_eth_dev *dev,\n\tstruct rte_eth_xstats *stats, unsigned n);\n/**< @internal Get extended stats of an Ethernet device. */\n\ntypedef void (*eth_xstats_reset_t)(struct rte_eth_dev *dev);\n/**< @internal Reset extended stats of an Ethernet device. */\n\ntypedef int (*eth_queue_stats_mapping_set_t)(struct rte_eth_dev *dev,\n\t\t\t\t\t uint16_t queue_id,\n\t\t\t\t\t uint8_t stat_idx,\n\t\t\t\t\t uint8_t is_rx);\n/**< @internal Set a queue statistics mapping for a tx/rx queue of an Ethernet device. */\n\ntypedef void (*eth_dev_infos_get_t)(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_dev_info *dev_info);\n/**< @internal Get specific informations of an Ethernet device. */\n\ntypedef int (*eth_queue_start_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t queue_id);\n/**< @internal Start rx and tx of a queue of an Ethernet device. */\n\ntypedef int (*eth_queue_stop_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t queue_id);\n/**< @internal Stop rx and tx of a queue of an Ethernet device. */\n\ntypedef int (*eth_rx_queue_setup_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t rx_queue_id,\n\t\t\t\t uint16_t nb_rx_desc,\n\t\t\t\t unsigned int socket_id,\n\t\t\t\t const struct rte_eth_rxconf *rx_conf,\n\t\t\t\t struct rte_mempool *mb_pool);\n/**< @internal Set up a receive queue of an Ethernet device. */\n\ntypedef int (*eth_tx_queue_setup_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t tx_queue_id,\n\t\t\t\t uint16_t nb_tx_desc,\n\t\t\t\t unsigned int socket_id,\n\t\t\t\t const struct rte_eth_txconf *tx_conf);\n/**< @internal Setup a transmit queue of an Ethernet device. */\n\ntypedef int (*eth_rx_enable_intr_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t rx_queue_id);\n/**< @internal Enable interrupt of a receive queue of an Ethernet device. */\n\ntypedef int (*eth_rx_disable_intr_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t rx_queue_id);\n/**< @internal Disable interrupt of a receive queue of an Ethernet device. */\n\ntypedef void (*eth_queue_release_t)(void *queue);\n/**< @internal Release memory resources allocated by given RX/TX queue. */\n\ntypedef uint32_t (*eth_rx_queue_count_t)(struct rte_eth_dev *dev,\n\t\t\t\t\t uint16_t rx_queue_id);\n/**< @internal Get number of available descriptors on a receive queue of an Ethernet device. */\n\ntypedef int (*eth_rx_descriptor_done_t)(void *rxq, uint16_t offset);\n/**< @internal Check DD bit of specific RX descriptor */\n\ntypedef int (*mtu_set_t)(struct rte_eth_dev *dev, uint16_t mtu);\n/**< @internal Set MTU. */\n\ntypedef int (*vlan_filter_set_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t vlan_id,\n\t\t\t\t int on);\n/**< @internal filtering of a VLAN Tag Identifier by an Ethernet device. */\n\ntypedef void (*vlan_tpid_set_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t tpid);\n/**< @internal set the outer VLAN-TPID by an Ethernet device. */\n\ntypedef void (*vlan_offload_set_t)(struct rte_eth_dev *dev, int mask);\n/**< @internal set VLAN offload function by an Ethernet device. */\n\ntypedef int (*vlan_pvid_set_t)(struct rte_eth_dev *dev,\n\t\t\t uint16_t vlan_id,\n\t\t\t int on);\n/**< @internal set port based TX VLAN insertion by an Ethernet device. */\n\ntypedef void (*vlan_strip_queue_set_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t rx_queue_id,\n\t\t\t\t int on);\n/**< @internal VLAN stripping enable/disable by an queue of Ethernet device. */\n\ntypedef uint16_t (*eth_rx_burst_t)(void *rxq,\n\t\t\t\t struct rte_mbuf **rx_pkts,\n\t\t\t\t uint16_t nb_pkts);\n/**< @internal Retrieve input packets from a receive queue of an Ethernet device. */\n\ntypedef uint16_t (*eth_tx_burst_t)(void *txq,\n\t\t\t\t struct rte_mbuf **tx_pkts,\n\t\t\t\t uint16_t nb_pkts);\n/**< @internal Send output packets on a transmit queue of an Ethernet device. */\n\ntypedef int (*fdir_add_signature_filter_t)(struct rte_eth_dev *dev,\n\t\t\t\t\t struct rte_fdir_filter *fdir_ftr,\n\t\t\t\t\t uint8_t rx_queue);\n/**< @internal Setup a new signature filter rule on an Ethernet device */\n\ntypedef int (*fdir_update_signature_filter_t)(struct rte_eth_dev *dev,\n\t\t\t\t\t struct rte_fdir_filter *fdir_ftr,\n\t\t\t\t\t uint8_t rx_queue);\n/**< @internal Update a signature filter rule on an Ethernet device */\n\ntypedef int (*fdir_remove_signature_filter_t)(struct rte_eth_dev *dev,\n\t\t\t\t\t struct rte_fdir_filter *fdir_ftr);\n/**< @internal Remove a signature filter rule on an Ethernet device */\n\ntypedef void (*fdir_infos_get_t)(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_fdir *fdir);\n/**< @internal Get information about fdir status */\n\ntypedef int (*fdir_add_perfect_filter_t)(struct rte_eth_dev *dev,\n\t\t\t\t\t struct rte_fdir_filter *fdir_ftr,\n\t\t\t\t\t uint16_t soft_id, uint8_t rx_queue,\n\t\t\t\t\t uint8_t drop);\n/**< @internal Setup a new perfect filter rule on an Ethernet device */\n\ntypedef int (*fdir_update_perfect_filter_t)(struct rte_eth_dev *dev,\n\t\t\t\t\t struct rte_fdir_filter *fdir_ftr,\n\t\t\t\t\t uint16_t soft_id, uint8_t rx_queue,\n\t\t\t\t\t uint8_t drop);\n/**< @internal Update a perfect filter rule on an Ethernet device */\n\ntypedef int (*fdir_remove_perfect_filter_t)(struct rte_eth_dev *dev,\n\t\t\t\t\t struct rte_fdir_filter *fdir_ftr,\n\t\t\t\t\t uint16_t soft_id);\n/**< @internal Remove a perfect filter rule on an Ethernet device */\n\ntypedef int (*fdir_set_masks_t)(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_fdir_masks *fdir_masks);\n/**< @internal Setup flow director masks on an Ethernet device */\n\ntypedef int (*flow_ctrl_get_t)(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_fc_conf *fc_conf);\n/**< @internal Get current flow control parameter on an Ethernet device */\n\ntypedef int (*flow_ctrl_set_t)(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_fc_conf *fc_conf);\n/**< @internal Setup flow control parameter on an Ethernet device */\n\ntypedef int (*priority_flow_ctrl_set_t)(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_eth_pfc_conf *pfc_conf);\n/**< @internal Setup priority flow control parameter on an Ethernet device */\n\ntypedef int (*reta_update_t)(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t uint16_t reta_size);\n/**< @internal Update RSS redirection table on an Ethernet device */\n\ntypedef int (*reta_query_t)(struct rte_eth_dev *dev,\n\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t uint16_t reta_size);\n/**< @internal Query RSS redirection table on an Ethernet device */\n\ntypedef int (*rss_hash_update_t)(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_rss_conf *rss_conf);\n/**< @internal Update RSS hash configuration of an Ethernet device */\n\ntypedef int (*rss_hash_conf_get_t)(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_rss_conf *rss_conf);\n/**< @internal Get current RSS hash configuration of an Ethernet device */\n\ntypedef int (*eth_dev_led_on_t)(struct rte_eth_dev *dev);\n/**< @internal Turn on SW controllable LED on an Ethernet device */\n\ntypedef int (*eth_dev_led_off_t)(struct rte_eth_dev *dev);\n/**< @internal Turn off SW controllable LED on an Ethernet device */\n\ntypedef void (*eth_mac_addr_remove_t)(struct rte_eth_dev *dev, uint32_t index);\n/**< @internal Remove MAC address from receive address register */\n\ntypedef void (*eth_mac_addr_add_t)(struct rte_eth_dev *dev,\n\t\t\t\t struct ether_addr *mac_addr,\n\t\t\t\t uint32_t index,\n\t\t\t\t uint32_t vmdq);\n/**< @internal Set a MAC address into Receive Address Address Register */\n\ntypedef void (*eth_mac_addr_set_t)(struct rte_eth_dev *dev,\n\t\t\t\t struct ether_addr *mac_addr);\n/**< @internal Set a MAC address into Receive Address Address Register */\n\ntypedef int (*eth_uc_hash_table_set_t)(struct rte_eth_dev *dev,\n\t\t\t\t struct ether_addr *mac_addr,\n\t\t\t\t uint8_t on);\n/**< @internal Set a Unicast Hash bitmap */\n\ntypedef int (*eth_uc_all_hash_table_set_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint8_t on);\n/**< @internal Set all Unicast Hash bitmap */\n\ntypedef int (*eth_set_vf_rx_mode_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t vf,\n\t\t\t\t uint16_t rx_mode,\n\t\t\t\t uint8_t on);\n/**< @internal Set a VF receive mode */\n\ntypedef int (*eth_set_vf_rx_t)(struct rte_eth_dev *dev,\n\t\t\t\tuint16_t vf,\n\t\t\t\tuint8_t on);\n/**< @internal Set a VF receive mode */\n\ntypedef int (*eth_set_vf_tx_t)(struct rte_eth_dev *dev,\n\t\t\t\tuint16_t vf,\n\t\t\t\tuint8_t on);\n/**< @internal Enable or disable a VF transmit */\n\ntypedef int (*eth_set_vf_vlan_filter_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint16_t vlan,\n\t\t\t\t uint64_t vf_mask,\n\t\t\t\t uint8_t vlan_on);\n/**< @internal Set VF VLAN pool filter */\n\ntypedef int (*eth_set_queue_rate_limit_t)(struct rte_eth_dev *dev,\n\t\t\t\tuint16_t queue_idx,\n\t\t\t\tuint16_t tx_rate);\n/**< @internal Set queue TX rate */\n\ntypedef int (*eth_set_vf_rate_limit_t)(struct rte_eth_dev *dev,\n\t\t\t\tuint16_t vf,\n\t\t\t\tuint16_t tx_rate,\n\t\t\t\tuint64_t q_msk);\n/**< @internal Set VF TX rate */\n\ntypedef int (*eth_mirror_rule_set_t)(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_mirror_conf *mirror_conf,\n\t\t\t\t uint8_t rule_id,\n\t\t\t\t uint8_t on);\n/**< @internal Add a traffic mirroring rule on an Ethernet device */\n\ntypedef int (*eth_mirror_rule_reset_t)(struct rte_eth_dev *dev,\n\t\t\t\t uint8_t rule_id);\n/**< @internal Remove a traffic mirroring rule on an Ethernet device */\n\ntypedef int (*eth_udp_tunnel_add_t)(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_udp_tunnel *tunnel_udp);\n/**< @internal Add tunneling UDP info */\n\ntypedef int (*eth_udp_tunnel_del_t)(struct rte_eth_dev *dev,\n\t\t\t\t struct rte_eth_udp_tunnel *tunnel_udp);\n/**< @internal Delete tunneling UDP info */\n\ntypedef int (*eth_set_mc_addr_list_t)(struct rte_eth_dev *dev,\n\t\t\t\t struct ether_addr *mc_addr_set,\n\t\t\t\t uint32_t nb_mc_addr);\n/**< @internal set the list of multicast addresses on an Ethernet device */\n\ntypedef int (*eth_timesync_enable_t)(struct rte_eth_dev *dev);\n/**< @internal Function used to enable IEEE1588/802.1AS timestamping. */\n\ntypedef int (*eth_timesync_disable_t)(struct rte_eth_dev *dev);\n/**< @internal Function used to disable IEEE1588/802.1AS timestamping. */\n\ntypedef int (*eth_timesync_read_rx_timestamp_t)(struct rte_eth_dev *dev,\n\t\t\t\t\t\tstruct timespec *timestamp,\n\t\t\t\t\t\tuint32_t flags);\n/**< @internal Function used to read an RX IEEE1588/802.1AS timestamp. */\n\ntypedef int (*eth_timesync_read_tx_timestamp_t)(struct rte_eth_dev *dev,\n\t\t\t\t\t\tstruct timespec *timestamp);\n/**< @internal Function used to read a TX IEEE1588/802.1AS timestamp. */\n\ntypedef int (*eth_get_reg_length_t)(struct rte_eth_dev *dev);\n/**< @internal Retrieve device register count */\n\ntypedef int (*eth_get_reg_t)(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_dev_reg_info *info);\n/**< @internal Retrieve registers */\n\ntypedef int (*eth_get_eeprom_length_t)(struct rte_eth_dev *dev);\n/**< @internal Retrieve eeprom size */\n\ntypedef int (*eth_get_eeprom_t)(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_dev_eeprom_info *info);\n/**< @internal Retrieve eeprom data */\n\ntypedef int (*eth_set_eeprom_t)(struct rte_eth_dev *dev,\n\t\t\t\tstruct rte_dev_eeprom_info *info);\n/**< @internal Program eeprom data */\n\n#ifdef RTE_NIC_BYPASS\n\nenum {\n\tRTE_BYPASS_MODE_NONE,\n\tRTE_BYPASS_MODE_NORMAL,\n\tRTE_BYPASS_MODE_BYPASS,\n\tRTE_BYPASS_MODE_ISOLATE,\n\tRTE_BYPASS_MODE_NUM,\n};\n\n#define\tRTE_BYPASS_MODE_VALID(x)\t\\\n\t((x) > RTE_BYPASS_MODE_NONE && (x) < RTE_BYPASS_MODE_NUM)\n\nenum {\n\tRTE_BYPASS_EVENT_NONE,\n\tRTE_BYPASS_EVENT_START,\n\tRTE_BYPASS_EVENT_OS_ON = RTE_BYPASS_EVENT_START,\n\tRTE_BYPASS_EVENT_POWER_ON,\n\tRTE_BYPASS_EVENT_OS_OFF,\n\tRTE_BYPASS_EVENT_POWER_OFF,\n\tRTE_BYPASS_EVENT_TIMEOUT,\n\tRTE_BYPASS_EVENT_NUM\n};\n\n#define\tRTE_BYPASS_EVENT_VALID(x)\t\\\n\t((x) > RTE_BYPASS_EVENT_NONE && (x) < RTE_BYPASS_MODE_NUM)\n\nenum {\n\tRTE_BYPASS_TMT_OFF, /* timeout disabled. */\n\tRTE_BYPASS_TMT_1_5_SEC, /* timeout for 1.5 seconds */\n\tRTE_BYPASS_TMT_2_SEC, /* timeout for 2 seconds */\n\tRTE_BYPASS_TMT_3_SEC, /* timeout for 3 seconds */\n\tRTE_BYPASS_TMT_4_SEC, /* timeout for 4 seconds */\n\tRTE_BYPASS_TMT_8_SEC, /* timeout for 8 seconds */\n\tRTE_BYPASS_TMT_16_SEC, /* timeout for 16 seconds */\n\tRTE_BYPASS_TMT_32_SEC, /* timeout for 32 seconds */\n\tRTE_BYPASS_TMT_NUM\n};\n\n#define\tRTE_BYPASS_TMT_VALID(x)\t\\\n\t((x) == RTE_BYPASS_TMT_OFF || \\\n\t((x) > RTE_BYPASS_TMT_OFF && (x) < RTE_BYPASS_TMT_NUM))\n\ntypedef void (*bypass_init_t)(struct rte_eth_dev *dev);\ntypedef int32_t (*bypass_state_set_t)(struct rte_eth_dev *dev, uint32_t *new_state);\ntypedef int32_t (*bypass_state_show_t)(struct rte_eth_dev *dev, uint32_t *state);\ntypedef int32_t (*bypass_event_set_t)(struct rte_eth_dev *dev, uint32_t state, uint32_t event);\ntypedef int32_t (*bypass_event_show_t)(struct rte_eth_dev *dev, uint32_t event_shift, uint32_t *event);\ntypedef int32_t (*bypass_wd_timeout_set_t)(struct rte_eth_dev *dev, uint32_t timeout);\ntypedef int32_t (*bypass_wd_timeout_show_t)(struct rte_eth_dev *dev, uint32_t *wd_timeout);\ntypedef int32_t (*bypass_ver_show_t)(struct rte_eth_dev *dev, uint32_t *ver);\ntypedef int32_t (*bypass_wd_reset_t)(struct rte_eth_dev *dev);\n#endif\n\ntypedef int (*eth_filter_ctrl_t)(struct rte_eth_dev *dev,\n\t\t\t\t enum rte_filter_type filter_type,\n\t\t\t\t enum rte_filter_op filter_op,\n\t\t\t\t void *arg);\n/**< @internal Take operations to assigned filter type on an Ethernet device */\n\n/**\n * @internal A structure containing the functions exported by an Ethernet driver.\n */\nstruct eth_dev_ops {\n\teth_dev_configure_t dev_configure; /**< Configure device. */\n\teth_dev_start_t dev_start; /**< Start device. */\n\teth_dev_stop_t dev_stop; /**< Stop device. */\n\teth_dev_set_link_up_t dev_set_link_up; /**< Device link up. */\n\teth_dev_set_link_down_t dev_set_link_down; /**< Device link down. */\n\teth_dev_close_t dev_close; /**< Close device. */\n\teth_promiscuous_enable_t promiscuous_enable; /**< Promiscuous ON. */\n\teth_promiscuous_disable_t promiscuous_disable;/**< Promiscuous OFF. */\n\teth_allmulticast_enable_t allmulticast_enable;/**< RX multicast ON. */\n\teth_allmulticast_disable_t allmulticast_disable;/**< RX multicast OF. */\n\teth_link_update_t link_update; /**< Get device link state. */\n\teth_stats_get_t stats_get; /**< Get generic device statistics. */\n\teth_stats_reset_t stats_reset; /**< Reset generic device statistics. */\n\teth_xstats_get_t xstats_get; /**< Get extended device statistics. */\n\teth_xstats_reset_t xstats_reset; /**< Reset extended device statistics. */\n\teth_queue_stats_mapping_set_t queue_stats_mapping_set;\n\t/**< Configure per queue stat counter mapping. */\n\teth_dev_infos_get_t dev_infos_get; /**< Get device info. */\n\tmtu_set_t mtu_set; /**< Set MTU. */\n\tvlan_filter_set_t vlan_filter_set; /**< Filter VLAN Setup. */\n\tvlan_tpid_set_t vlan_tpid_set; /**< Outer VLAN TPID Setup. */\n\tvlan_strip_queue_set_t vlan_strip_queue_set; /**< VLAN Stripping on queue. */\n\tvlan_offload_set_t vlan_offload_set; /**< Set VLAN Offload. */\n\tvlan_pvid_set_t vlan_pvid_set; /**< Set port based TX VLAN insertion */\n\teth_queue_start_t rx_queue_start;/**< Start RX for a queue.*/\n\teth_queue_stop_t rx_queue_stop;/**< Stop RX for a queue.*/\n\teth_queue_start_t tx_queue_start;/**< Start TX for a queue.*/\n\teth_queue_stop_t tx_queue_stop;/**< Stop TX for a queue.*/\n\teth_rx_queue_setup_t rx_queue_setup;/**< Set up device RX queue.*/\n\teth_queue_release_t rx_queue_release;/**< Release RX queue.*/\n\teth_rx_queue_count_t rx_queue_count; /**< Get Rx queue count. */\n\teth_rx_descriptor_done_t rx_descriptor_done; /**< Check rxd DD bit */\n#ifdef RTE_NEXT_ABI\n\t/**< Enable Rx queue interrupt. */\n\teth_rx_enable_intr_t rx_queue_intr_enable;\n\t/**< Disable Rx queue interrupt.*/\n\teth_rx_disable_intr_t rx_queue_intr_disable;\n#endif\n\teth_tx_queue_setup_t tx_queue_setup;/**< Set up device TX queue.*/\n\teth_queue_release_t tx_queue_release;/**< Release TX queue.*/\n\teth_dev_led_on_t dev_led_on; /**< Turn on LED. */\n\teth_dev_led_off_t dev_led_off; /**< Turn off LED. */\n\tflow_ctrl_get_t flow_ctrl_get; /**< Get flow control. */\n\tflow_ctrl_set_t flow_ctrl_set; /**< Setup flow control. */\n\tpriority_flow_ctrl_set_t priority_flow_ctrl_set; /**< Setup priority flow control.*/\n\teth_mac_addr_remove_t mac_addr_remove; /**< Remove MAC address */\n\teth_mac_addr_add_t mac_addr_add; /**< Add a MAC address */\n\teth_mac_addr_set_t mac_addr_set; /**< Set a MAC address */\n\teth_uc_hash_table_set_t uc_hash_table_set; /**< Set Unicast Table Array */\n\teth_uc_all_hash_table_set_t uc_all_hash_table_set; /**< Set Unicast hash bitmap */\n\teth_mirror_rule_set_t\t mirror_rule_set; /**< Add a traffic mirror rule.*/\n\teth_mirror_rule_reset_t\t mirror_rule_reset; /**< reset a traffic mirror rule.*/\n\teth_set_vf_rx_mode_t set_vf_rx_mode; /**< Set VF RX mode */\n\teth_set_vf_rx_t set_vf_rx; /**< enable/disable a VF receive */\n\teth_set_vf_tx_t set_vf_tx; /**< enable/disable a VF transmit */\n\teth_set_vf_vlan_filter_t set_vf_vlan_filter; /**< Set VF VLAN filter */\n\teth_udp_tunnel_add_t udp_tunnel_add;\n\teth_udp_tunnel_del_t udp_tunnel_del;\n\teth_set_queue_rate_limit_t set_queue_rate_limit; /**< Set queue rate limit */\n\teth_set_vf_rate_limit_t set_vf_rate_limit; /**< Set VF rate limit */\n\n\t/** Add a signature filter. */\n\tfdir_add_signature_filter_t fdir_add_signature_filter;\n\t/** Update a signature filter. */\n\tfdir_update_signature_filter_t fdir_update_signature_filter;\n\t/** Remove a signature filter. */\n\tfdir_remove_signature_filter_t fdir_remove_signature_filter;\n\t/** Get information about FDIR status. */\n\tfdir_infos_get_t fdir_infos_get;\n\t/** Add a perfect filter. */\n\tfdir_add_perfect_filter_t fdir_add_perfect_filter;\n\t/** Update a perfect filter. */\n\tfdir_update_perfect_filter_t fdir_update_perfect_filter;\n\t/** Remove a perfect filter. */\n\tfdir_remove_perfect_filter_t fdir_remove_perfect_filter;\n\t/** Setup masks for FDIR filtering. */\n\tfdir_set_masks_t fdir_set_masks;\n\t/** Update redirection table. */\n\treta_update_t reta_update;\n\t/** Query redirection table. */\n\treta_query_t reta_query;\n\n\teth_get_reg_length_t get_reg_length;\n\t/**< Get # of registers */\n\teth_get_reg_t get_reg;\n\t/**< Get registers */\n\teth_get_eeprom_length_t get_eeprom_length;\n\t/**< Get eeprom length */\n\teth_get_eeprom_t get_eeprom;\n\t/**< Get eeprom data */\n\teth_set_eeprom_t set_eeprom;\n\t/**< Set eeprom */\n /* bypass control */\n#ifdef RTE_NIC_BYPASS\n bypass_init_t bypass_init;\n bypass_state_set_t bypass_state_set;\n bypass_state_show_t bypass_state_show;\n bypass_event_set_t bypass_event_set;\n bypass_event_show_t bypass_event_show;\n bypass_wd_timeout_set_t bypass_wd_timeout_set;\n bypass_wd_timeout_show_t bypass_wd_timeout_show;\n bypass_ver_show_t bypass_ver_show;\n bypass_wd_reset_t bypass_wd_reset;\n#endif\n\n\t/** Configure RSS hash protocols. */\n\trss_hash_update_t rss_hash_update;\n\t/** Get current RSS hash configuration. */\n\trss_hash_conf_get_t rss_hash_conf_get;\n\teth_filter_ctrl_t filter_ctrl; /**< common filter control*/\n\teth_set_mc_addr_list_t set_mc_addr_list; /**< set list of mcast addrs */\n\n\t/** Turn IEEE1588/802.1AS timestamping on. */\n\teth_timesync_enable_t timesync_enable;\n\t/** Turn IEEE1588/802.1AS timestamping off. */\n\teth_timesync_disable_t timesync_disable;\n\t/** Read the IEEE1588/802.1AS RX timestamp. */\n\teth_timesync_read_rx_timestamp_t timesync_read_rx_timestamp;\n\t/** Read the IEEE1588/802.1AS TX timestamp. */\n\teth_timesync_read_tx_timestamp_t timesync_read_tx_timestamp;\n};\n\n/**\n * Function type used for RX packet processing packet callbacks.\n *\n * The callback function is called on RX with a burst of packets that have\n * been received on the given port and queue.\n *\n * @param port\n * The Ethernet port on which RX is being performed.\n * @param queue\n * The queue on the Ethernet port which is being used to receive the packets.\n * @param pkts\n * The burst of packets that have just been received.\n * @param nb_pkts\n * The number of packets in the burst pointed to by \"pkts\".\n * @param max_pkts\n * The max number of packets that can be stored in the \"pkts\" array.\n * @param user_param\n * The arbitrary user parameter passed in by the application when the callback\n * was originally configured.\n * @return\n * The number of packets returned to the user.\n */\ntypedef uint16_t (*rte_rx_callback_fn)(uint8_t port, uint16_t queue,\n\tstruct rte_mbuf *pkts[], uint16_t nb_pkts, uint16_t max_pkts,\n\tvoid *user_param);\n\n/**\n * Function type used for TX packet processing packet callbacks.\n *\n * The callback function is called on TX with a burst of packets immediately\n * before the packets are put onto the hardware queue for transmission.\n *\n * @param port\n * The Ethernet port on which TX is being performed.\n * @param queue\n * The queue on the Ethernet port which is being used to transmit the packets.\n * @param pkts\n * The burst of packets that are about to be transmitted.\n * @param nb_pkts\n * The number of packets in the burst pointed to by \"pkts\".\n * @param user_param\n * The arbitrary user parameter passed in by the application when the callback\n * was originally configured.\n * @return\n * The number of packets to be written to the NIC.\n */\ntypedef uint16_t (*rte_tx_callback_fn)(uint8_t port, uint16_t queue,\n\tstruct rte_mbuf *pkts[], uint16_t nb_pkts, void *user_param);\n\n/**\n * @internal\n * Structure used to hold information about the callbacks to be called for a\n * queue on RX and TX.\n */\nstruct rte_eth_rxtx_callback {\n\tstruct rte_eth_rxtx_callback *next;\n\tunion{\n\t\trte_rx_callback_fn rx;\n\t\trte_tx_callback_fn tx;\n\t} fn;\n\tvoid *param;\n};\n\n/**\n * The eth device type.\n */\nenum rte_eth_dev_type {\n\tRTE_ETH_DEV_UNKNOWN,\t/**< unknown device type */\n\tRTE_ETH_DEV_PCI,\n\t\t/**< Physical function and Virtual function of PCI devices */\n\tRTE_ETH_DEV_VIRTUAL,\t/**< non hardware device */\n\tRTE_ETH_DEV_MAX\t\t/**< max value of this enum */\n};\n\n/**\n * @internal\n * The generic data structure associated with each ethernet device.\n *\n * Pointers to burst-oriented packet receive and transmit functions are\n * located at the beginning of the structure, along with the pointer to\n * where all the data elements for the particular device are stored in shared\n * memory. This split allows the function pointer and driver data to be per-\n * process, while the actual configuration data for the device is shared.\n */\nstruct rte_eth_dev {\n\teth_rx_burst_t rx_pkt_burst; /**< Pointer to PMD receive function. */\n\teth_tx_burst_t tx_pkt_burst; /**< Pointer to PMD transmit function. */\n\tstruct rte_eth_dev_data *data; /**< Pointer to device data */\n\tconst struct eth_driver *driver;/**< Driver for this device */\n\tconst struct eth_dev_ops *dev_ops; /**< Functions exported by PMD */\n\tstruct rte_pci_device *pci_dev; /**< PCI info. supplied by probing */\n\t/** User application callbacks for NIC interrupts */\n\tstruct rte_eth_dev_cb_list link_intr_cbs;\n\t/**\n\t * User-supplied functions called from rx_burst to post-process\n\t * received packets before passing them to the user\n\t */\n\tstruct rte_eth_rxtx_callback *post_rx_burst_cbs[RTE_MAX_QUEUES_PER_PORT];\n\t/**\n\t * User-supplied functions called from tx_burst to pre-process\n\t * received packets before passing them to the driver for transmission.\n\t */\n\tstruct rte_eth_rxtx_callback *pre_tx_burst_cbs[RTE_MAX_QUEUES_PER_PORT];\n\tuint8_t attached; /**< Flag indicating the port is attached */\n\tenum rte_eth_dev_type dev_type; /**< Flag indicating the device type */\n};\n\nstruct rte_eth_dev_sriov {\n\tuint8_t active; /**< SRIOV is active with 16, 32 or 64 pools */\n\tuint8_t nb_q_per_pool; /**< rx queue number per pool */\n\tuint16_t def_vmdq_idx; /**< Default pool num used for PF */\n\tuint16_t def_pool_q_idx; /**< Default pool queue start reg index */\n};\n#define RTE_ETH_DEV_SRIOV(dev) ((dev)->data->sriov)\n\n#define RTE_ETH_NAME_MAX_LEN (32)\n\n/**\n * @internal\n * The data part, with no function pointers, associated with each ethernet device.\n *\n * This structure is safe to place in shared memory to be common among different\n * processes in a multi-process configuration.\n */\nstruct rte_eth_dev_data {\n\tchar name[RTE_ETH_NAME_MAX_LEN]; /**< Unique identifier name */\n\n\tvoid **rx_queues; /**< Array of pointers to RX queues. */\n\tvoid **tx_queues; /**< Array of pointers to TX queues. */\n\tuint16_t nb_rx_queues; /**< Number of RX queues. */\n\tuint16_t nb_tx_queues; /**< Number of TX queues. */\n\n\tstruct rte_eth_dev_sriov sriov; /**< SRIOV data */\n\n\tvoid *dev_private; /**< PMD-specific private data */\n\n\tstruct rte_eth_link dev_link;\n\t/**< Link-level information & status */\n\n\tstruct rte_eth_conf dev_conf; /**< Configuration applied to device. */\n\tuint16_t mtu; /**< Maximum Transmission Unit. */\n\n\tuint32_t min_rx_buf_size;\n\t/**< Common rx buffer size handled by all queues */\n\n\tuint64_t rx_mbuf_alloc_failed; /**< RX ring mbuf allocation failures. */\n\tstruct ether_addr* mac_addrs;/**< Device Ethernet Link address. */\n\tuint64_t mac_pool_sel[ETH_NUM_RECEIVE_MAC_ADDR];\n\t/** bitmap array of associating Ethernet MAC addresses to pools */\n\tstruct ether_addr* hash_mac_addrs;\n\t/** Device Ethernet MAC addresses of hash filtering. */\n\tuint8_t port_id; /**< Device [external] port identifier. */\n\tuint8_t promiscuous : 1, /**< RX promiscuous mode ON(1) / OFF(0). */\n\t\tscattered_rx : 1, /**< RX of scattered packets is ON(1) / OFF(0) */\n\t\tall_multicast : 1, /**< RX all multicast mode ON(1) / OFF(0). */\n\t\tdev_started : 1, /**< Device state: STARTED(1) / STOPPED(0). */\n\t\tlro : 1; /**< RX LRO is ON(1) / OFF(0) */\n};\n\n/**\n * @internal\n * The pool of *rte_eth_dev* structures. The size of the pool\n * is configured at compile-time in the file.\n */\nextern struct rte_eth_dev rte_eth_devices[];\n\n/**\n * Get the total number of Ethernet devices that have been successfully\n * initialized by the [matching] Ethernet driver during the PCI probing phase.\n * All devices whose port identifier is in the range\n * [0, rte_eth_dev_count() - 1] can be operated on by network applications\n * immediately after invoking rte_eal_init().\n * If the application unplugs a port using hotplug function, The enabled port\n * numbers may be noncontiguous. In the case, the applications need to manage\n * enabled port by themselves.\n *\n * @return\n * - The total number of usable Ethernet devices.\n */\nextern uint8_t rte_eth_dev_count(void);\n\n/**\n * @internal\n * Returns a ethdev slot specified by the unique identifier name.\n *\n * @param\tname\n * The pointer to the Unique identifier name for each Ethernet device\n * @return\n * - The pointer to the ethdev slot, on success. NULL on error\n */\nextern struct rte_eth_dev *rte_eth_dev_allocated(const char *name);\n\n/**\n * @internal\n * Allocates a new ethdev slot for an ethernet device and returns the pointer\n * to that slot for the driver to use.\n *\n * @param\tname\tUnique identifier name for each Ethernet device\n * @param\ttype\tDevice type of this Ethernet device\n * @return\n * - Slot in the rte_dev_devices array for a new device;\n */\nstruct rte_eth_dev *rte_eth_dev_allocate(const char *name,\n\t\tenum rte_eth_dev_type type);\n\n/**\n * @internal\n * Release the specified ethdev port.\n *\n * @param eth_dev\n * The *eth_dev* pointer is the address of the *rte_eth_dev* structure.\n * @return\n * - 0 on success, negative on error\n */\nint rte_eth_dev_release_port(struct rte_eth_dev *eth_dev);\n\n/**\n * Attach a new Ethernet device specified by aruguments.\n *\n * @param devargs\n * A pointer to a strings array describing the new device\n * to be attached. The strings should be a pci address like\n * '0000:01:00.0' or virtual device name like 'eth_pcap0'.\n * @param port_id\n * A pointer to a port identifier actually attached.\n * @return\n * 0 on success and port_id is filled, negative on error\n */\nint rte_eth_dev_attach(const char *devargs, uint8_t *port_id);\n\n/**\n * Detach a Ethernet device specified by port identifier.\n * This function must be called when the device is in the\n * closed state.\n *\n * @param port_id\n * The port identifier of the device to detach.\n * @param devname\n * A pointer to a device name actually detached.\n * @return\n * 0 on success and devname is filled, negative on error\n */\nint rte_eth_dev_detach(uint8_t port_id, char *devname);\n\nstruct eth_driver;\n/**\n * @internal\n * Initialization function of an Ethernet driver invoked for each matching\n * Ethernet PCI device detected during the PCI probing phase.\n *\n * @param eth_dev\n * The *eth_dev* pointer is the address of the *rte_eth_dev* structure\n * associated with the matching device and which have been [automatically]\n * allocated in the *rte_eth_devices* array.\n * The *eth_dev* structure is supplied to the driver initialization function\n * with the following fields already initialized:\n *\n * - *pci_dev*: Holds the pointers to the *rte_pci_device* structure which\n * contains the generic PCI information of the matching device.\n *\n * - *driver*: Holds the pointer to the *eth_driver* structure.\n *\n * - *dev_private*: Holds a pointer to the device private data structure.\n *\n * - *mtu*: Contains the default Ethernet maximum frame length (1500).\n *\n * - *port_id*: Contains the port index of the device (actually the index\n * of the *eth_dev* structure in the *rte_eth_devices* array).\n *\n * @return\n * - 0: Success, the device is properly initialized by the driver.\n * In particular, the driver MUST have set up the *dev_ops* pointer\n * of the *eth_dev* structure.\n * - <0: Error code of the device initialization failure.\n */\ntypedef int (*eth_dev_init_t)(struct rte_eth_dev *eth_dev);\n\n/**\n * @internal\n * Finalization function of an Ethernet driver invoked for each matching\n * Ethernet PCI device detected during the PCI closing phase.\n *\n * @param eth_dev\n * The *eth_dev* pointer is the address of the *rte_eth_dev* structure\n * associated with the matching device and which have been [automatically]\n * allocated in the *rte_eth_devices* array.\n * @return\n * - 0: Success, the device is properly finalized by the driver.\n * In particular, the driver MUST free the *dev_ops* pointer\n * of the *eth_dev* structure.\n * - <0: Error code of the device initialization failure.\n */\ntypedef int (*eth_dev_uninit_t)(struct rte_eth_dev *eth_dev);\n\n/**\n * @internal\n * The structure associated with a PMD Ethernet driver.\n *\n * Each Ethernet driver acts as a PCI driver and is represented by a generic\n * *eth_driver* structure that holds:\n *\n * - An *rte_pci_driver* structure (which must be the first field).\n *\n * - The *eth_dev_init* function invoked for each matching PCI device.\n *\n * - The *eth_dev_uninit* function invoked for each matching PCI device.\n *\n * - The size of the private data to allocate for each matching device.\n */\nstruct eth_driver {\n\tstruct rte_pci_driver pci_drv; /**< The PMD is also a PCI driver. */\n\teth_dev_init_t eth_dev_init; /**< Device init function. */\n\teth_dev_uninit_t eth_dev_uninit; /**< Device uninit function. */\n\tunsigned int dev_private_size; /**< Size of device private data. */\n};\n\n/**\n * @internal\n * A function invoked by the initialization function of an Ethernet driver\n * to simultaneously register itself as a PCI driver and as an Ethernet\n * Poll Mode Driver (PMD).\n *\n * @param eth_drv\n * The pointer to the *eth_driver* structure associated with\n * the Ethernet driver.\n */\nextern void rte_eth_driver_register(struct eth_driver *eth_drv);\n\n/**\n * Configure an Ethernet device.\n * This function must be invoked first before any other function in the\n * Ethernet API. This function can also be re-invoked when a device is in the\n * stopped state.\n *\n * @param port_id\n * The port identifier of the Ethernet device to configure.\n * @param nb_rx_queue\n * The number of receive queues to set up for the Ethernet device.\n * @param nb_tx_queue\n * The number of transmit queues to set up for the Ethernet device.\n * @param eth_conf\n * The pointer to the configuration data to be used for the Ethernet device.\n * The *rte_eth_conf* structure includes:\n * - the hardware offload features to activate, with dedicated fields for\n * each statically configurable offload hardware feature provided by\n * Ethernet devices, such as IP checksum or VLAN tag stripping for\n * example.\n * - the Receive Side Scaling (RSS) configuration when using multiple RX\n * queues per port.\n *\n * Embedding all configuration information in a single data structure\n * is the more flexible method that allows the addition of new features\n * without changing the syntax of the API.\n * @return\n * - 0: Success, device configured.\n * - <0: Error code returned by the driver configuration function.\n */\nextern int rte_eth_dev_configure(uint8_t port_id,\n\t\t\t\t uint16_t nb_rx_queue,\n\t\t\t\t uint16_t nb_tx_queue,\n\t\t\t\t const struct rte_eth_conf *eth_conf);\n\n/**\n * Allocate and set up a receive queue for an Ethernet device.\n *\n * The function allocates a contiguous block of memory for *nb_rx_desc*\n * receive descriptors from a memory zone associated with *socket_id*\n * and initializes each receive descriptor with a network buffer allocated\n * from the memory pool *mb_pool*.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param rx_queue_id\n * The index of the receive queue to set up.\n * The value must be in the range [0, nb_rx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @param nb_rx_desc\n * The number of receive descriptors to allocate for the receive ring.\n * @param socket_id\n * The *socket_id* argument is the socket identifier in case of NUMA.\n * The value can be *SOCKET_ID_ANY* if there is no NUMA constraint for\n * the DMA memory allocated for the receive descriptors of the ring.\n * @param rx_conf\n * The pointer to the configuration data to be used for the receive queue.\n * NULL value is allowed, in which case default RX configuration\n * will be used.\n * The *rx_conf* structure contains an *rx_thresh* structure with the values\n * of the Prefetch, Host, and Write-Back threshold registers of the receive\n * ring.\n * @param mb_pool\n * The pointer to the memory pool from which to allocate *rte_mbuf* network\n * memory buffers to populate each descriptor of the receive ring.\n * @return\n * - 0: Success, receive queue correctly set up.\n * - -EINVAL: The size of network buffers which can be allocated from the\n * memory pool does not fit the various buffer sizes allowed by the\n * device controller.\n * - -ENOMEM: Unable to allocate the receive ring descriptors or to\n * allocate network memory buffers from the memory pool when\n * initializing receive descriptors.\n */\nextern int rte_eth_rx_queue_setup(uint8_t port_id, uint16_t rx_queue_id,\n\t\t\t\t uint16_t nb_rx_desc, unsigned int socket_id,\n\t\t\t\t const struct rte_eth_rxconf *rx_conf,\n\t\t\t\t struct rte_mempool *mb_pool);\n\n/**\n * Allocate and set up a transmit queue for an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param tx_queue_id\n * The index of the transmit queue to set up.\n * The value must be in the range [0, nb_tx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @param nb_tx_desc\n * The number of transmit descriptors to allocate for the transmit ring.\n * @param socket_id\n * The *socket_id* argument is the socket identifier in case of NUMA.\n * Its value can be *SOCKET_ID_ANY* if there is no NUMA constraint for\n * the DMA memory allocated for the transmit descriptors of the ring.\n * @param tx_conf\n * The pointer to the configuration data to be used for the transmit queue.\n * NULL value is allowed, in which case default RX configuration\n * will be used.\n * The *tx_conf* structure contains the following data:\n * - The *tx_thresh* structure with the values of the Prefetch, Host, and\n * Write-Back threshold registers of the transmit ring.\n * When setting Write-Back threshold to the value greater then zero,\n * *tx_rs_thresh* value should be explicitly set to one.\n * - The *tx_free_thresh* value indicates the [minimum] number of network\n * buffers that must be pending in the transmit ring to trigger their\n * [implicit] freeing by the driver transmit function.\n * - The *tx_rs_thresh* value indicates the [minimum] number of transmit\n * descriptors that must be pending in the transmit ring before setting the\n * RS bit on a descriptor by the driver transmit function.\n * The *tx_rs_thresh* value should be less or equal then\n * *tx_free_thresh* value, and both of them should be less then\n * *nb_tx_desc* - 3.\n * - The *txq_flags* member contains flags to pass to the TX queue setup\n * function to configure the behavior of the TX queue. This should be set\n * to 0 if no special configuration is required.\n *\n * Note that setting *tx_free_thresh* or *tx_rs_thresh* value to 0 forces\n * the transmit function to use default values.\n * @return\n * - 0: Success, the transmit queue is correctly set up.\n * - -ENOMEM: Unable to allocate the transmit ring descriptors.\n */\nextern int rte_eth_tx_queue_setup(uint8_t port_id, uint16_t tx_queue_id,\n\t\t\t\t uint16_t nb_tx_desc, unsigned int socket_id,\n\t\t\t\t const struct rte_eth_txconf *tx_conf);\n\n/*\n * Return the NUMA socket to which an Ethernet device is connected\n *\n * @param port_id\n * The port identifier of the Ethernet device\n * @return\n * The NUMA socket id to which the Ethernet device is connected or\n * a default of zero if the socket could not be determined.\n * -1 is returned is the port_id value is out of range.\n */\nextern int rte_eth_dev_socket_id(uint8_t port_id);\n\n/*\n * Check if port_id of device is attached\n *\n * @param port_id\n * The port identifier of the Ethernet device\n * @return\n * - 0 if port is out of range or not attached\n * - 1 if device is attached\n */\nextern int rte_eth_dev_is_valid_port(uint8_t port_id);\n\n/*\n * Allocate mbuf from mempool, setup the DMA physical address\n * and then start RX for specified queue of a port. It is used\n * when rx_deferred_start flag of the specified queue is true.\n *\n * @param port_id\n * The port identifier of the Ethernet device\n * @param rx_queue_id\n * The index of the rx queue to update the ring.\n * The value must be in the range [0, nb_rx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @return\n * - 0: Success, the transmit queue is correctly set up.\n * - -EINVAL: The port_id or the queue_id out of range.\n * - -ENOTSUP: The function not supported in PMD driver.\n */\nextern int rte_eth_dev_rx_queue_start(uint8_t port_id, uint16_t rx_queue_id);\n\n/*\n * Stop specified RX queue of a port\n *\n * @param port_id\n * The port identifier of the Ethernet device\n * @param rx_queue_id\n * The index of the rx queue to update the ring.\n * The value must be in the range [0, nb_rx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @return\n * - 0: Success, the transmit queue is correctly set up.\n * - -EINVAL: The port_id or the queue_id out of range.\n * - -ENOTSUP: The function not supported in PMD driver.\n */\nextern int rte_eth_dev_rx_queue_stop(uint8_t port_id, uint16_t rx_queue_id);\n\n/*\n * Start TX for specified queue of a port. It is used when tx_deferred_start\n * flag of the specified queue is true.\n *\n * @param port_id\n * The port identifier of the Ethernet device\n * @param tx_queue_id\n * The index of the tx queue to update the ring.\n * The value must be in the range [0, nb_tx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @return\n * - 0: Success, the transmit queue is correctly set up.\n * - -EINVAL: The port_id or the queue_id out of range.\n * - -ENOTSUP: The function not supported in PMD driver.\n */\nextern int rte_eth_dev_tx_queue_start(uint8_t port_id, uint16_t tx_queue_id);\n\n/*\n * Stop specified TX queue of a port\n *\n * @param port_id\n * The port identifier of the Ethernet device\n * @param tx_queue_id\n * The index of the tx queue to update the ring.\n * The value must be in the range [0, nb_tx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @return\n * - 0: Success, the transmit queue is correctly set up.\n * - -EINVAL: The port_id or the queue_id out of range.\n * - -ENOTSUP: The function not supported in PMD driver.\n */\nextern int rte_eth_dev_tx_queue_stop(uint8_t port_id, uint16_t tx_queue_id);\n\n\n\n/**\n * Start an Ethernet device.\n *\n * The device start step is the last one and consists of setting the configured\n * offload features and in starting the transmit and the receive units of the\n * device.\n * On success, all basic functions exported by the Ethernet API (link status,\n * receive/transmit, and so on) can be invoked.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @return\n * - 0: Success, Ethernet device started.\n * - <0: Error code of the driver device start function.\n */\nextern int rte_eth_dev_start(uint8_t port_id);\n\n/**\n * Stop an Ethernet device. The device can be restarted with a call to\n * rte_eth_dev_start()\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n */\nextern void rte_eth_dev_stop(uint8_t port_id);\n\n\n/**\n * Link up an Ethernet device.\n *\n * Set device link up will re-enable the device rx/tx\n * functionality after it is previously set device linked down.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @return\n * - 0: Success, Ethernet device linked up.\n * - <0: Error code of the driver device link up function.\n */\nextern int rte_eth_dev_set_link_up(uint8_t port_id);\n\n/**\n * Link down an Ethernet device.\n * The device rx/tx functionality will be disabled if success,\n * and it can be re-enabled with a call to\n * rte_eth_dev_set_link_up()\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n */\nextern int rte_eth_dev_set_link_down(uint8_t port_id);\n\n/**\n * Close a stopped Ethernet device. The device cannot be restarted!\n * The function frees all resources except for needed by the\n * closed state. To free these resources, call rte_eth_dev_detach().\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n */\nextern void rte_eth_dev_close(uint8_t port_id);\n\n/**\n * Enable receipt in promiscuous mode for an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n */\nextern void rte_eth_promiscuous_enable(uint8_t port_id);\n\n/**\n * Disable receipt in promiscuous mode for an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n */\nextern void rte_eth_promiscuous_disable(uint8_t port_id);\n\n/**\n * Return the value of promiscuous mode for an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @return\n * - (1) if promiscuous is enabled\n * - (0) if promiscuous is disabled.\n * - (-1) on error\n */\nextern int rte_eth_promiscuous_get(uint8_t port_id);\n\n/**\n * Enable the receipt of any multicast frame by an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n */\nextern void rte_eth_allmulticast_enable(uint8_t port_id);\n\n/**\n * Disable the receipt of all multicast frames by an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n */\nextern void rte_eth_allmulticast_disable(uint8_t port_id);\n\n/**\n * Return the value of allmulticast mode for an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @return\n * - (1) if allmulticast is enabled\n * - (0) if allmulticast is disabled.\n * - (-1) on error\n */\nextern int rte_eth_allmulticast_get(uint8_t port_id);\n\n/**\n * Retrieve the status (ON/OFF), the speed (in Mbps) and the mode (HALF-DUPLEX\n * or FULL-DUPLEX) of the physical link of an Ethernet device. It might need\n * to wait up to 9 seconds in it.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param link\n * A pointer to an *rte_eth_link* structure to be filled with\n * the status, the speed and the mode of the Ethernet device link.\n */\nextern void rte_eth_link_get(uint8_t port_id, struct rte_eth_link *link);\n\n/**\n * Retrieve the status (ON/OFF), the speed (in Mbps) and the mode (HALF-DUPLEX\n * or FULL-DUPLEX) of the physical link of an Ethernet device. It is a no-wait\n * version of rte_eth_link_get().\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param link\n * A pointer to an *rte_eth_link* structure to be filled with\n * the status, the speed and the mode of the Ethernet device link.\n */\nextern void rte_eth_link_get_nowait(uint8_t port_id,\n\t\t\t\tstruct rte_eth_link *link);\n\n/**\n * Retrieve the general I/O statistics of an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param stats\n * A pointer to a structure of type *rte_eth_stats* to be filled with\n * the values of device counters for the following set of statistics:\n * - *ipackets* with the total of successfully received packets.\n * - *opackets* with the total of successfully transmitted packets.\n * - *ibytes* with the total of successfully received bytes.\n * - *obytes* with the total of successfully transmitted bytes.\n * - *ierrors* with the total of erroneous received packets.\n * - *oerrors* with the total of failed transmitted packets.\n * @return\n * Zero if successful. Non-zero otherwise.\n */\nextern int rte_eth_stats_get(uint8_t port_id, struct rte_eth_stats *stats);\n\n/**\n * Reset the general I/O statistics of an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n */\nextern void rte_eth_stats_reset(uint8_t port_id);\n\n/**\n * Retrieve extended statistics of an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param xstats\n * A pointer to a table of structure of type *rte_eth_xstats*\n * to be filled with device statistics names and values.\n * This parameter can be set to NULL if n is 0.\n * @param n\n * The size of the stats table, which should be large enough to store\n * all the statistics of the device.\n * @return\n * - positive value lower or equal to n: success. The return value\n * is the number of entries filled in the stats table.\n * - positive value higher than n: error, the given statistics table\n * is too small. The return value corresponds to the size that should\n * be given to succeed. The entries in the table are not valid and\n * shall not be used by the caller.\n * - negative value on error (invalid port id)\n */\nextern int rte_eth_xstats_get(uint8_t port_id,\n\tstruct rte_eth_xstats *xstats, unsigned n);\n\n/**\n * Reset extended statistics of an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n */\nextern void rte_eth_xstats_reset(uint8_t port_id);\n\n/**\n * Set a mapping for the specified transmit queue to the specified per-queue\n * statistics counter.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param tx_queue_id\n * The index of the transmit queue for which a queue stats mapping is required.\n * The value must be in the range [0, nb_tx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @param stat_idx\n * The per-queue packet statistics functionality number that the transmit\n * queue is to be assigned.\n * The value must be in the range [0, RTE_MAX_ETHPORT_QUEUE_STATS_MAPS - 1].\n * @return\n * Zero if successful. Non-zero otherwise.\n */\nextern int rte_eth_dev_set_tx_queue_stats_mapping(uint8_t port_id,\n\t\t\t\t\t\t uint16_t tx_queue_id,\n\t\t\t\t\t\t uint8_t stat_idx);\n\n/**\n * Set a mapping for the specified receive queue to the specified per-queue\n * statistics counter.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param rx_queue_id\n * The index of the receive queue for which a queue stats mapping is required.\n * The value must be in the range [0, nb_rx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @param stat_idx\n * The per-queue packet statistics functionality number that the receive\n * queue is to be assigned.\n * The value must be in the range [0, RTE_MAX_ETHPORT_QUEUE_STATS_MAPS - 1].\n * @return\n * Zero if successful. Non-zero otherwise.\n */\nextern int rte_eth_dev_set_rx_queue_stats_mapping(uint8_t port_id,\n\t\t\t\t\t\t uint16_t rx_queue_id,\n\t\t\t\t\t\t uint8_t stat_idx);\n\n/**\n * Retrieve the Ethernet address of an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param mac_addr\n * A pointer to a structure of type *ether_addr* to be filled with\n * the Ethernet address of the Ethernet device.\n */\nextern void rte_eth_macaddr_get(uint8_t port_id, struct ether_addr *mac_addr);\n\n/**\n * Retrieve the contextual information of an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param dev_info\n * A pointer to a structure of type *rte_eth_dev_info* to be filled with\n * the contextual information of the Ethernet device.\n */\nextern void rte_eth_dev_info_get(uint8_t port_id,\n\t\t\t\t struct rte_eth_dev_info *dev_info);\n\n/**\n * Retrieve the MTU of an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param mtu\n * A pointer to a uint16_t where the retrieved MTU is to be stored.\n * @return\n * - (0) if successful.\n * - (-ENODEV) if *port_id* invalid.\n */\nextern int rte_eth_dev_get_mtu(uint8_t port_id, uint16_t *mtu);\n\n/**\n * Change the MTU of an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param mtu\n * A uint16_t for the MTU to be applied.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if operation is not supported.\n * - (-ENODEV) if *port_id* invalid.\n * - (-EINVAL) if *mtu* invalid.\n */\nextern int rte_eth_dev_set_mtu(uint8_t port_id, uint16_t mtu);\n\n/**\n * Enable/Disable hardware filtering by an Ethernet device of received\n * VLAN packets tagged with a given VLAN Tag Identifier.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param vlan_id\n * The VLAN Tag Identifier whose filtering must be enabled or disabled.\n * @param on\n * If > 0, enable VLAN filtering of VLAN packets tagged with *vlan_id*.\n * Otherwise, disable VLAN filtering of VLAN packets tagged with *vlan_id*.\n * @return\n * - (0) if successful.\n * - (-ENOSUP) if hardware-assisted VLAN filtering not configured.\n * - (-ENODEV) if *port_id* invalid.\n * - (-ENOSYS) if VLAN filtering on *port_id* disabled.\n * - (-EINVAL) if *vlan_id* > 4095.\n */\nextern int rte_eth_dev_vlan_filter(uint8_t port_id, uint16_t vlan_id , int on);\n\n/**\n * Enable/Disable hardware VLAN Strip by a rx queue of an Ethernet device.\n * 82599/X540/X550 can support VLAN stripping at the rx queue level\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param rx_queue_id\n * The index of the receive queue for which a queue stats mapping is required.\n * The value must be in the range [0, nb_rx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @param on\n * If 1, Enable VLAN Stripping of the receive queue of the Ethernet port.\n * If 0, Disable VLAN Stripping of the receive queue of the Ethernet port.\n * @return\n * - (0) if successful.\n * - (-ENOSUP) if hardware-assisted VLAN stripping not configured.\n * - (-ENODEV) if *port_id* invalid.\n * - (-EINVAL) if *rx_queue_id* invalid.\n */\nextern int rte_eth_dev_set_vlan_strip_on_queue(uint8_t port_id,\n\t\tuint16_t rx_queue_id, int on);\n\n/**\n * Set the Outer VLAN Ether Type by an Ethernet device, it can be inserted to\n * the VLAN Header. This is a register setup available on some Intel NIC, not\n * but all, please check the data sheet for availability.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param tag_type\n * The Tag Protocol ID\n * @return\n * - (0) if successful.\n * - (-ENOSUP) if hardware-assisted VLAN TPID setup is not supported.\n * - (-ENODEV) if *port_id* invalid.\n */\nextern int rte_eth_dev_set_vlan_ether_type(uint8_t port_id, uint16_t tag_type);\n\n/**\n * Set VLAN offload configuration on an Ethernet device\n * Enable/Disable Extended VLAN by an Ethernet device, This is a register setup\n * available on some Intel NIC, not but all, please check the data sheet for\n * availability.\n * Enable/Disable VLAN Strip can be done on rx queue for certain NIC, but here\n * the configuration is applied on the port level.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param offload_mask\n * The VLAN Offload bit mask can be mixed use with \"OR\"\n * ETH_VLAN_STRIP_OFFLOAD\n * ETH_VLAN_FILTER_OFFLOAD\n * ETH_VLAN_EXTEND_OFFLOAD\n * @return\n * - (0) if successful.\n * - (-ENOSUP) if hardware-assisted VLAN filtering not configured.\n * - (-ENODEV) if *port_id* invalid.\n */\nextern int rte_eth_dev_set_vlan_offload(uint8_t port_id, int offload_mask);\n\n/**\n * Read VLAN Offload configuration from an Ethernet device\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @return\n * - (>0) if successful. Bit mask to indicate\n * ETH_VLAN_STRIP_OFFLOAD\n * ETH_VLAN_FILTER_OFFLOAD\n * ETH_VLAN_EXTEND_OFFLOAD\n * - (-ENODEV) if *port_id* invalid.\n */\nextern int rte_eth_dev_get_vlan_offload(uint8_t port_id);\n\n/**\n * Set port based TX VLAN insersion on or off.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param pvid\n * Port based TX VLAN identifier togeth with user priority.\n * @param on\n * Turn on or off the port based TX VLAN insertion.\n *\n * @return\n * - (0) if successful.\n * - negative if failed.\n */\nextern int rte_eth_dev_set_vlan_pvid(uint8_t port_id, uint16_t pvid, int on);\n\n/**\n *\n * Retrieve a burst of input packets from a receive queue of an Ethernet\n * device. The retrieved packets are stored in *rte_mbuf* structures whose\n * pointers are supplied in the *rx_pkts* array.\n *\n * The rte_eth_rx_burst() function loops, parsing the RX ring of the\n * receive queue, up to *nb_pkts* packets, and for each completed RX\n * descriptor in the ring, it performs the following operations:\n *\n * - Initialize the *rte_mbuf* data structure associated with the\n * RX descriptor according to the information provided by the NIC into\n * that RX descriptor.\n *\n * - Store the *rte_mbuf* data structure into the next entry of the\n * *rx_pkts* array.\n *\n * - Replenish the RX descriptor with a new *rte_mbuf* buffer\n * allocated from the memory pool associated with the receive queue at\n * initialization time.\n *\n * When retrieving an input packet that was scattered by the controller\n * into multiple receive descriptors, the rte_eth_rx_burst() function\n * appends the associated *rte_mbuf* buffers to the first buffer of the\n * packet.\n *\n * The rte_eth_rx_burst() function returns the number of packets\n * actually retrieved, which is the number of *rte_mbuf* data structures\n * effectively supplied into the *rx_pkts* array.\n * A return value equal to *nb_pkts* indicates that the RX queue contained\n * at least *rx_pkts* packets, and this is likely to signify that other\n * received packets remain in the input queue. Applications implementing\n * a \"retrieve as much received packets as possible\" policy can check this\n * specific case and keep invoking the rte_eth_rx_burst() function until\n * a value less than *nb_pkts* is returned.\n *\n * This receive method has the following advantages:\n *\n * - It allows a run-to-completion network stack engine to retrieve and\n * to immediately process received packets in a fast burst-oriented\n * approach, avoiding the overhead of unnecessary intermediate packet\n * queue/dequeue operations.\n *\n * - Conversely, it also allows an asynchronous-oriented processing\n * method to retrieve bursts of received packets and to immediately\n * queue them for further parallel processing by another logical core,\n * for instance. However, instead of having received packets being\n * individually queued by the driver, this approach allows the invoker\n * of the rte_eth_rx_burst() function to queue a burst of retrieved\n * packets at a time and therefore dramatically reduce the cost of\n * enqueue/dequeue operations per packet.\n *\n * - It allows the rte_eth_rx_burst() function of the driver to take\n * advantage of burst-oriented hardware features (CPU cache,\n * prefetch instructions, and so on) to minimize the number of CPU\n * cycles per packet.\n *\n * To summarize, the proposed receive API enables many\n * burst-oriented optimizations in both synchronous and asynchronous\n * packet processing environments with no overhead in both cases.\n *\n * The rte_eth_rx_burst() function does not provide any error\n * notification to avoid the corresponding overhead. As a hint, the\n * upper-level application might check the status of the device link once\n * being systematically returned a 0 value for a given number of tries.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param queue_id\n * The index of the receive queue from which to retrieve input packets.\n * The value must be in the range [0, nb_rx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @param rx_pkts\n * The address of an array of pointers to *rte_mbuf* structures that\n * must be large enough to store *nb_pkts* pointers in it.\n * @param nb_pkts\n * The maximum number of packets to retrieve.\n * @return\n * The number of packets actually retrieved, which is the number\n * of pointers to *rte_mbuf* structures effectively supplied to the\n * *rx_pkts* array.\n */\n#ifdef RTE_LIBRTE_ETHDEV_DEBUG\nextern uint16_t rte_eth_rx_burst(uint8_t port_id, uint16_t queue_id,\n\t\t\t\t struct rte_mbuf **rx_pkts, uint16_t nb_pkts);\n#else\nstatic inline uint16_t\nrte_eth_rx_burst(uint8_t port_id, uint16_t queue_id,\n\t\t struct rte_mbuf **rx_pkts, const uint16_t nb_pkts)\n{\n\tstruct rte_eth_dev *dev;\n\n\tdev = &rte_eth_devices[port_id];\n\n\tint16_t nb_rx = (*dev->rx_pkt_burst)(dev->data->rx_queues[queue_id],\n\t\t\trx_pkts, nb_pkts);\n\n#ifdef RTE_ETHDEV_RXTX_CALLBACKS\n\tstruct rte_eth_rxtx_callback *cb = dev->post_rx_burst_cbs[queue_id];\n\n\tif (unlikely(cb != NULL)) {\n\t\tdo {\n\t\t\tnb_rx = cb->fn.rx(port_id, queue_id, rx_pkts, nb_rx,\n\t\t\t\t\t\tnb_pkts, cb->param);\n\t\t\tcb = cb->next;\n\t\t} while (cb != NULL);\n\t}\n#endif\n\n\treturn nb_rx;\n}\n#endif\n\n/**\n * Get the number of used descriptors in a specific queue\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param queue_id\n * The queue id on the specific port.\n * @return\n * The number of used descriptors in the specific queue.\n */\n#ifdef RTE_LIBRTE_ETHDEV_DEBUG\nextern uint32_t rte_eth_rx_queue_count(uint8_t port_id, uint16_t queue_id);\n#else\nstatic inline uint32_t\nrte_eth_rx_queue_count(uint8_t port_id, uint16_t queue_id)\n{\n struct rte_eth_dev *dev;\n\n dev = &rte_eth_devices[port_id];\n return (*dev->dev_ops->rx_queue_count)(dev, queue_id);\n}\n#endif\n\n/**\n * Check if the DD bit of the specific RX descriptor in the queue has been set\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param queue_id\n * The queue id on the specific port.\n * @param offset\n * The offset of the descriptor ID from tail.\n * @return\n * - (1) if the specific DD bit is set.\n * - (0) if the specific DD bit is not set.\n * - (-ENODEV) if *port_id* invalid.\n */\n#ifdef RTE_LIBRTE_ETHDEV_DEBUG\nextern int rte_eth_rx_descriptor_done(uint8_t port_id,\n\t\t\t\t uint16_t queue_id,\n\t\t\t\t uint16_t offset);\n#else\nstatic inline int\nrte_eth_rx_descriptor_done(uint8_t port_id, uint16_t queue_id, uint16_t offset)\n{\n\tstruct rte_eth_dev *dev;\n\n\tdev = &rte_eth_devices[port_id];\n\treturn (*dev->dev_ops->rx_descriptor_done)( \\\n\t\tdev->data->rx_queues[queue_id], offset);\n}\n#endif\n\n/**\n * Send a burst of output packets on a transmit queue of an Ethernet device.\n *\n * The rte_eth_tx_burst() function is invoked to transmit output packets\n * on the output queue *queue_id* of the Ethernet device designated by its\n * *port_id*.\n * The *nb_pkts* parameter is the number of packets to send which are\n * supplied in the *tx_pkts* array of *rte_mbuf* structures.\n * The rte_eth_tx_burst() function loops, sending *nb_pkts* packets,\n * up to the number of transmit descriptors available in the TX ring of the\n * transmit queue.\n * For each packet to send, the rte_eth_tx_burst() function performs\n * the following operations:\n *\n * - Pick up the next available descriptor in the transmit ring.\n *\n * - Free the network buffer previously sent with that descriptor, if any.\n *\n * - Initialize the transmit descriptor with the information provided\n * in the *rte_mbuf data structure.\n *\n * In the case of a segmented packet composed of a list of *rte_mbuf* buffers,\n * the rte_eth_tx_burst() function uses several transmit descriptors\n * of the ring.\n *\n * The rte_eth_tx_burst() function returns the number of packets it\n * actually sent. A return value equal to *nb_pkts* means that all packets\n * have been sent, and this is likely to signify that other output packets\n * could be immediately transmitted again. Applications that implement a\n * \"send as many packets to transmit as possible\" policy can check this\n * specific case and keep invoking the rte_eth_tx_burst() function until\n * a value less than *nb_pkts* is returned.\n *\n * It is the responsibility of the rte_eth_tx_burst() function to\n * transparently free the memory buffers of packets previously sent.\n * This feature is driven by the *tx_free_thresh* value supplied to the\n * rte_eth_dev_configure() function at device configuration time.\n * When the number of free TX descriptors drops below this threshold, the\n * rte_eth_tx_burst() function must [attempt to] free the *rte_mbuf* buffers\n * of those packets whose transmission was effectively completed.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param queue_id\n * The index of the transmit queue through which output packets must be\n * sent.\n * The value must be in the range [0, nb_tx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @param tx_pkts\n * The address of an array of *nb_pkts* pointers to *rte_mbuf* structures\n * which contain the output packets.\n * @param nb_pkts\n * The maximum number of packets to transmit.\n * @return\n * The number of output packets actually stored in transmit descriptors of\n * the transmit ring. The return value can be less than the value of the\n * *tx_pkts* parameter when the transmit ring is full or has been filled up.\n */\n#ifdef RTE_LIBRTE_ETHDEV_DEBUG\nextern uint16_t rte_eth_tx_burst(uint8_t port_id, uint16_t queue_id,\n\t\t\t\t struct rte_mbuf **tx_pkts, uint16_t nb_pkts);\n#else\nstatic inline uint16_t\nrte_eth_tx_burst(uint8_t port_id, uint16_t queue_id,\n\t\t struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n{\n\tstruct rte_eth_dev *dev;\n\n\tdev = &rte_eth_devices[port_id];\n\n#ifdef RTE_ETHDEV_RXTX_CALLBACKS\n\tstruct rte_eth_rxtx_callback *cb = dev->pre_tx_burst_cbs[queue_id];\n\n\tif (unlikely(cb != NULL)) {\n\t\tdo {\n\t\t\tnb_pkts = cb->fn.tx(port_id, queue_id, tx_pkts, nb_pkts,\n\t\t\t\t\tcb->param);\n\t\t\tcb = cb->next;\n\t\t} while (cb != NULL);\n\t}\n#endif\n\n\treturn (*dev->tx_pkt_burst)(dev->data->tx_queues[queue_id], tx_pkts, nb_pkts);\n}\n#endif\n\n/**\n * Setup a new signature filter rule on an Ethernet device\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param fdir_filter\n * The pointer to the fdir filter structure describing the signature filter\n * rule.\n * The *rte_fdir_filter* structure includes the values of the different fields\n * to match: source and destination IP addresses, vlan id, flexbytes, source\n * and destination ports, and so on.\n * @param rx_queue\n * The index of the RX queue where to store RX packets matching the added\n * signature filter defined in fdir_filter.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support flow director mode.\n * - (-ENODEV) if *port_id* invalid.\n * - (-ENOSYS) if the FDIR mode is not configured in signature mode\n * on *port_id*.\n * - (-EINVAL) if the fdir_filter information is not correct.\n */\nint rte_eth_dev_fdir_add_signature_filter(uint8_t port_id,\n\t\t\t\t\t struct rte_fdir_filter *fdir_filter,\n\t\t\t\t\t uint8_t rx_queue);\n\n/**\n * Update a signature filter rule on an Ethernet device.\n * If the rule doesn't exits, it is created.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param fdir_ftr\n * The pointer to the structure describing the signature filter rule.\n * The *rte_fdir_filter* structure includes the values of the different fields\n * to match: source and destination IP addresses, vlan id, flexbytes, source\n * and destination ports, and so on.\n * @param rx_queue\n * The index of the RX queue where to store RX packets matching the added\n * signature filter defined in fdir_ftr.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support flow director mode.\n * - (-ENODEV) if *port_id* invalid.\n * - (-ENOSYS) if the flow director mode is not configured in signature mode\n * on *port_id*.\n * - (-EINVAL) if the fdir_filter information is not correct.\n */\nint rte_eth_dev_fdir_update_signature_filter(uint8_t port_id,\n\t\t\t\t\t struct rte_fdir_filter *fdir_ftr,\n\t\t\t\t\t uint8_t rx_queue);\n\n/**\n * Remove a signature filter rule on an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param fdir_ftr\n * The pointer to the structure describing the signature filter rule.\n * The *rte_fdir_filter* structure includes the values of the different fields\n * to match: source and destination IP addresses, vlan id, flexbytes, source\n * and destination ports, and so on.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support flow director mode.\n * - (-ENODEV) if *port_id* invalid.\n * - (-ENOSYS) if the flow director mode is not configured in signature mode\n * on *port_id*.\n * - (-EINVAL) if the fdir_filter information is not correct.\n */\nint rte_eth_dev_fdir_remove_signature_filter(uint8_t port_id,\n\t\t\t\t\t struct rte_fdir_filter *fdir_ftr);\n\n/**\n * Retrieve the flow director information of an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param fdir\n * A pointer to a structure of type *rte_eth_dev_fdir* to be filled with\n * the flow director information of the Ethernet device.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support flow director mode.\n * - (-ENODEV) if *port_id* invalid.\n * - (-ENOSYS) if the flow director mode is not configured on *port_id*.\n */\nint rte_eth_dev_fdir_get_infos(uint8_t port_id, struct rte_eth_fdir *fdir);\n\n/**\n * Add a new perfect filter rule on an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param fdir_filter\n * The pointer to the structure describing the perfect filter rule.\n * The *rte_fdir_filter* structure includes the values of the different fields\n * to match: source and destination IP addresses, vlan id, flexbytes, source\n * and destination ports, and so on.\n * IPv6 are not supported.\n * @param soft_id\n * The 16-bit value supplied in the field hash.fdir.id of mbuf for RX\n * packets matching the perfect filter.\n * @param rx_queue\n * The index of the RX queue where to store RX packets matching the added\n * perfect filter defined in fdir_filter.\n * @param drop\n * If drop is set to 1, matching RX packets are stored into the RX drop\n * queue defined in the rte_fdir_conf.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support flow director mode.\n * - (-ENODEV) if *port_id* invalid.\n * - (-ENOSYS) if the flow director mode is not configured in perfect mode\n * on *port_id*.\n * - (-EINVAL) if the fdir_filter information is not correct.\n */\nint rte_eth_dev_fdir_add_perfect_filter(uint8_t port_id,\n\t\t\t\t\tstruct rte_fdir_filter *fdir_filter,\n\t\t\t\t\tuint16_t soft_id, uint8_t rx_queue,\n\t\t\t\t\tuint8_t drop);\n\n/**\n * Update a perfect filter rule on an Ethernet device.\n * If the rule doesn't exits, it is created.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param fdir_filter\n * The pointer to the structure describing the perfect filter rule.\n * The *rte_fdir_filter* structure includes the values of the different fields\n * to match: source and destination IP addresses, vlan id, flexbytes, source\n * and destination ports, and so on.\n * IPv6 are not supported.\n * @param soft_id\n * The 16-bit value supplied in the field hash.fdir.id of mbuf for RX\n * packets matching the perfect filter.\n * @param rx_queue\n * The index of the RX queue where to store RX packets matching the added\n * perfect filter defined in fdir_filter.\n * @param drop\n * If drop is set to 1, matching RX packets are stored into the RX drop\n * queue defined in the rte_fdir_conf.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support flow director mode.\n * - (-ENODEV) if *port_id* invalid.\n * - (-ENOSYS) if the flow director mode is not configured in perfect mode\n * on *port_id*.\n * - (-EINVAL) if the fdir_filter information is not correct.\n */\nint rte_eth_dev_fdir_update_perfect_filter(uint8_t port_id,\n\t\t\t\t\t struct rte_fdir_filter *fdir_filter,\n\t\t\t\t\t uint16_t soft_id, uint8_t rx_queue,\n\t\t\t\t\t uint8_t drop);\n\n/**\n * Remove a perfect filter rule on an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param fdir_filter\n * The pointer to the structure describing the perfect filter rule.\n * The *rte_fdir_filter* structure includes the values of the different fields\n * to match: source and destination IP addresses, vlan id, flexbytes, source\n * and destination ports, and so on.\n * IPv6 are not supported.\n * @param soft_id\n * The soft_id value provided when adding/updating the removed filter.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support flow director mode.\n * - (-ENODEV) if *port_id* invalid.\n * - (-ENOSYS) if the flow director mode is not configured in perfect mode\n * on *port_id*.\n * - (-EINVAL) if the fdir_filter information is not correct.\n */\nint rte_eth_dev_fdir_remove_perfect_filter(uint8_t port_id,\n\t\t\t\t\t struct rte_fdir_filter *fdir_filter,\n\t\t\t\t\t uint16_t soft_id);\n/**\n * Configure globally the masks for flow director mode for an Ethernet device.\n * For example, the device can match packets with only the first 24 bits of\n * the IPv4 source address.\n *\n * The following fields can be masked: IPv4 addresses and L4 port numbers.\n * The following fields can be either enabled or disabled completely for the\n * matching functionality: VLAN ID tag; VLAN Priority + CFI bit; Flexible 2-byte\n * tuple.\n * IPv6 masks are not supported.\n *\n * All filters must comply with the masks previously configured.\n * For example, with a mask equal to 255.255.255.0 for the source IPv4 address,\n * all IPv4 filters must be created with a source IPv4 address that fits the\n * \"X.X.X.0\" format.\n *\n * This function flushes all filters that have been previously added in\n * the device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param fdir_mask\n * The pointer to the fdir mask structure describing relevant headers fields\n * and relevant bits to use when matching packets addresses and ports.\n * IPv6 masks are not supported.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support flow director mode.\n * - (-ENODEV) if *port_id* invalid.\n * - (-ENOSYS) if the flow director mode is not configured in perfect\n * mode on *port_id*.\n * - (-EINVAL) if the fdir_filter information is not correct\n */\nint rte_eth_dev_fdir_set_masks(uint8_t port_id,\n\t\t\t struct rte_fdir_masks *fdir_mask);\n\n/**\n * The eth device event type for interrupt, and maybe others in the future.\n */\nenum rte_eth_event_type {\n\tRTE_ETH_EVENT_UNKNOWN, /**< unknown event type */\n\tRTE_ETH_EVENT_INTR_LSC, /**< lsc interrupt event */\n\tRTE_ETH_EVENT_MAX /**< max value of this enum */\n};\n\ntypedef void (*rte_eth_dev_cb_fn)(uint8_t port_id, \\\n\t\tenum rte_eth_event_type event, void *cb_arg);\n/**< user application callback to be registered for interrupts */\n\n\n\n/**\n * Register a callback function for specific port id.\n *\n * @param port_id\n * Port id.\n * @param event\n * Event interested.\n * @param cb_fn\n * User supplied callback function to be called.\n * @param cb_arg\n * Pointer to the parameters for the registered callback.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nint rte_eth_dev_callback_register(uint8_t port_id,\n\t\t\tenum rte_eth_event_type event,\n\t\trte_eth_dev_cb_fn cb_fn, void *cb_arg);\n\n/**\n * Unregister a callback function for specific port id.\n *\n * @param port_id\n * Port id.\n * @param event\n * Event interested.\n * @param cb_fn\n * User supplied callback function to be called.\n * @param cb_arg\n * Pointer to the parameters for the registered callback. -1 means to\n * remove all for the same callback address and same event.\n *\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nint rte_eth_dev_callback_unregister(uint8_t port_id,\n\t\t\tenum rte_eth_event_type event,\n\t\trte_eth_dev_cb_fn cb_fn, void *cb_arg);\n\n/**\n * @internal Executes all the user application registered callbacks for\n * the specific device. It is for DPDK internal user only. User\n * application should not call it directly.\n *\n * @param dev\n * Pointer to struct rte_eth_dev.\n * @param event\n * Eth device interrupt event type.\n *\n * @return\n * void\n */\nvoid _rte_eth_dev_callback_process(struct rte_eth_dev *dev,\n\t\t\t\tenum rte_eth_event_type event);\n\n/**\n * When there is no rx packet coming in Rx Queue for a long time, we can\n * sleep lcore related to RX Queue for power saving, and enable rx interrupt\n * to be triggered when rx packect arrives.\n *\n * The rte_eth_dev_rx_intr_enable() function enables rx queue\n * interrupt on specific rx queue of a port.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param queue_id\n * The index of the receive queue from which to retrieve input packets.\n * The value must be in the range [0, nb_rx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if underlying hardware OR driver doesn't support\n * that operation.\n * - (-ENODEV) if *port_id* invalid.\n */\nint rte_eth_dev_rx_intr_enable(uint8_t port_id, uint16_t queue_id);\n\n/**\n * When lcore wakes up from rx interrupt indicating packet coming, disable rx\n * interrupt and returns to polling mode.\n *\n * The rte_eth_dev_rx_intr_disable() function disables rx queue\n * interrupt on specific rx queue of a port.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param queue_id\n * The index of the receive queue from which to retrieve input packets.\n * The value must be in the range [0, nb_rx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if underlying hardware OR driver doesn't support\n * that operation.\n * - (-ENODEV) if *port_id* invalid.\n */\nint rte_eth_dev_rx_intr_disable(uint8_t port_id, uint16_t queue_id);\n\n/**\n * RX Interrupt control per port.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param epfd\n * Epoll instance fd which the intr vector associated to.\n * Using RTE_EPOLL_PER_THREAD allows to use per thread epoll instance.\n * @param op\n * The operation be performed for the vector.\n * Operation type of {RTE_INTR_EVENT_ADD, RTE_INTR_EVENT_DEL}.\n * @param data\n * User raw data.\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nint rte_eth_dev_rx_intr_ctl(uint8_t port_id, int epfd, int op, void *data);\n\n/**\n * RX Interrupt control per queue.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param queue_id\n * The index of the receive queue from which to retrieve input packets.\n * The value must be in the range [0, nb_rx_queue - 1] previously supplied\n * to rte_eth_dev_configure().\n * @param epfd\n * Epoll instance fd which the intr vector associated to.\n * Using RTE_EPOLL_PER_THREAD allows to use per thread epoll instance.\n * @param op\n * The operation be performed for the vector.\n * Operation type of {RTE_INTR_EVENT_ADD, RTE_INTR_EVENT_DEL}.\n * @param data\n * User raw data.\n * @return\n * - On success, zero.\n * - On failure, a negative value.\n */\nint rte_eth_dev_rx_intr_ctl_q(uint8_t port_id, uint16_t queue_id,\n\t\t\t int epfd, int op, void *data);\n\n/**\n * Turn on the LED on the Ethernet device.\n * This function turns on the LED on the Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if underlying hardware OR driver doesn't support\n * that operation.\n * - (-ENODEV) if *port_id* invalid.\n */\nint rte_eth_led_on(uint8_t port_id);\n\n/**\n * Turn off the LED on the Ethernet device.\n * This function turns off the LED on the Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if underlying hardware OR driver doesn't support\n * that operation.\n * - (-ENODEV) if *port_id* invalid.\n */\nint rte_eth_led_off(uint8_t port_id);\n\n/**\n * Get current status of the Ethernet link flow control for Ethernet device\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param fc_conf\n * The pointer to the structure where to store the flow control parameters.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support flow control.\n * - (-ENODEV) if *port_id* invalid.\n */\nint rte_eth_dev_flow_ctrl_get(uint8_t port_id,\n\t\t\t struct rte_eth_fc_conf *fc_conf);\n\n/**\n * Configure the Ethernet link flow control for Ethernet device\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param fc_conf\n * The pointer to the structure of the flow control parameters.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support flow control mode.\n * - (-ENODEV) if *port_id* invalid.\n * - (-EINVAL) if bad parameter\n * - (-EIO) if flow control setup failure\n */\nint rte_eth_dev_flow_ctrl_set(uint8_t port_id,\n\t\t\t struct rte_eth_fc_conf *fc_conf);\n\n/**\n * Configure the Ethernet priority flow control under DCB environment\n * for Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param pfc_conf\n * The pointer to the structure of the priority flow control parameters.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support priority flow control mode.\n * - (-ENODEV) if *port_id* invalid.\n * - (-EINVAL) if bad parameter\n * - (-EIO) if flow control setup failure\n */\nint rte_eth_dev_priority_flow_ctrl_set(uint8_t port_id,\n\t\t\t\tstruct rte_eth_pfc_conf *pfc_conf);\n\n/**\n * Add a MAC address to an internal array of addresses used to enable whitelist\n * filtering to accept packets only if the destination MAC address matches.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param mac_addr\n * The MAC address to add.\n * @param pool\n * VMDq pool index to associate address with (if VMDq is enabled). If VMDq is\n * not enabled, this should be set to 0.\n * @return\n * - (0) if successfully added or *mac_addr\" was already added.\n * - (-ENOTSUP) if hardware doesn't support this feature.\n * - (-ENODEV) if *port* is invalid.\n * - (-ENOSPC) if no more MAC addresses can be added.\n * - (-EINVAL) if MAC address is invalid.\n */\nint rte_eth_dev_mac_addr_add(uint8_t port, struct ether_addr *mac_addr,\n\t\t\t\tuint32_t pool);\n\n/**\n * Remove a MAC address from the internal array of addresses.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param mac_addr\n * MAC address to remove.\n * @return\n * - (0) if successful, or *mac_addr* didn't exist.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-ENODEV) if *port* invalid.\n * - (-EADDRINUSE) if attempting to remove the default MAC address\n */\nint rte_eth_dev_mac_addr_remove(uint8_t port, struct ether_addr *mac_addr);\n\n/**\n * Set the default MAC address.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param mac_addr\n * New default MAC address.\n * @return\n * - (0) if successful, or *mac_addr* didn't exist.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-ENODEV) if *port* invalid.\n * - (-EINVAL) if MAC address is invalid.\n */\nint rte_eth_dev_default_mac_addr_set(uint8_t port, struct ether_addr *mac_addr);\n\n\n/**\n * Update Redirection Table(RETA) of Receive Side Scaling of Ethernet device.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param reta_conf\n * RETA to update.\n * @param reta_size\n * Redirection table size. The table size can be queried by\n * rte_eth_dev_info_get().\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_rss_reta_update(uint8_t port,\n\t\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t\tuint16_t reta_size);\n\n /**\n * Query Redirection Table(RETA) of Receive Side Scaling of Ethernet device.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param reta_conf\n * RETA to query.\n * @param reta_size\n * Redirection table size. The table size can be queried by\n * rte_eth_dev_info_get().\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_rss_reta_query(uint8_t port,\n\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n\t\t\t uint16_t reta_size);\n\n /**\n * Updates unicast hash table for receiving packet with the given destination\n * MAC address, and the packet is routed to all VFs for which the RX mode is\n * accept packets that match the unicast hash table.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param addr\n * Unicast MAC address.\n * @param on\n * 1 - Set an unicast hash bit for receiving packets with the MAC address.\n * 0 - Clear an unicast hash bit.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-ENODEV) if *port_id* invalid.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_uc_hash_table_set(uint8_t port,struct ether_addr *addr,\n\t\t\t\t\tuint8_t on);\n\n /**\n * Updates all unicast hash bitmaps for receiving packet with any Unicast\n * Ethernet MAC addresses,the packet is routed to all VFs for which the RX\n * mode is accept packets that match the unicast hash table.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param on\n * 1 - Set all unicast hash bitmaps for receiving all the Ethernet\n * MAC addresses\n * 0 - Clear all unicast hash bitmaps\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-ENODEV) if *port_id* invalid.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_uc_all_hash_table_set(uint8_t port,uint8_t on);\n\n /**\n * Set RX L2 Filtering mode of a VF of an Ethernet device.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param vf\n * VF id.\n * @param rx_mode\n * The RX mode mask, which is one or more of accepting Untagged Packets,\n * packets that match the PFUTA table, Broadcast and Multicast Promiscuous.\n * ETH_VMDQ_ACCEPT_UNTAG,ETH_VMDQ_ACCEPT_HASH_UC,\n * ETH_VMDQ_ACCEPT_BROADCAST and ETH_VMDQ_ACCEPT_MULTICAST will be used\n * in rx_mode.\n * @param on\n * 1 - Enable a VF RX mode.\n * 0 - Disable a VF RX mode.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mode,\n\t\t\t\tuint8_t on);\n\n/**\n* Enable or disable a VF traffic transmit of the Ethernet device.\n*\n* @param port\n* The port identifier of the Ethernet device.\n* @param vf\n* VF id.\n* @param on\n* 1 - Enable a VF traffic transmit.\n* 0 - Disable a VF traffic transmit.\n* @return\n* - (0) if successful.\n* - (-ENODEV) if *port_id* invalid.\n* - (-ENOTSUP) if hardware doesn't support.\n* - (-EINVAL) if bad parameter.\n*/\nint\nrte_eth_dev_set_vf_tx(uint8_t port,uint16_t vf, uint8_t on);\n\n/**\n* Enable or disable a VF traffic receive of an Ethernet device.\n*\n* @param port\n* The port identifier of the Ethernet device.\n* @param vf\n* VF id.\n* @param on\n* 1 - Enable a VF traffic receive.\n* 0 - Disable a VF traffic receive.\n* @return\n* - (0) if successful.\n* - (-ENOTSUP) if hardware doesn't support.\n* - (-ENODEV) if *port_id* invalid.\n* - (-EINVAL) if bad parameter.\n*/\nint\nrte_eth_dev_set_vf_rx(uint8_t port,uint16_t vf, uint8_t on);\n\n/**\n* Enable/Disable hardware VF VLAN filtering by an Ethernet device of\n* received VLAN packets tagged with a given VLAN Tag Identifier.\n*\n* @param port id\n* The port identifier of the Ethernet device.\n* @param vlan_id\n* The VLAN Tag Identifier whose filtering must be enabled or disabled.\n* @param vf_mask\n* Bitmap listing which VFs participate in the VLAN filtering.\n* @param vlan_on\n* 1 - Enable VFs VLAN filtering.\n* 0 - Disable VFs VLAN filtering.\n* @return\n* - (0) if successful.\n* - (-ENOTSUP) if hardware doesn't support.\n* - (-ENODEV) if *port_id* invalid.\n* - (-EINVAL) if bad parameter.\n*/\nint\nrte_eth_dev_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,\n\t\t\t\tuint64_t vf_mask,\n\t\t\t\tuint8_t vlan_on);\n\n/**\n * Set a traffic mirroring rule on an Ethernet device\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param mirror_conf\n * The pointer to the traffic mirroring structure describing the mirroring rule.\n * The *rte_eth_vm_mirror_conf* structure includes the type of mirroring rule,\n * destination pool and the value of rule if enable vlan or pool mirroring.\n *\n * @param rule_id\n * The index of traffic mirroring rule, we support four separated rules.\n * @param on\n * 1 - Enable a mirroring rule.\n * 0 - Disable a mirroring rule.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support this feature.\n * - (-ENODEV) if *port_id* invalid.\n * - (-EINVAL) if the mr_conf information is not correct.\n */\nint rte_eth_mirror_rule_set(uint8_t port_id,\n\t\t\tstruct rte_eth_mirror_conf *mirror_conf,\n\t\t\tuint8_t rule_id,\n\t\t\tuint8_t on);\n\n/**\n * Reset a traffic mirroring rule on an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param rule_id\n * The index of traffic mirroring rule, we support four separated rules.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support this feature.\n * - (-ENODEV) if *port_id* invalid.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_mirror_rule_reset(uint8_t port_id,\n\t\t\t\t\t uint8_t rule_id);\n\n/**\n * Set the rate limitation for a queue on an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param queue_idx\n * The queue id.\n * @param tx_rate\n * The tx rate allocated from the total link speed for this queue.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support this feature.\n * - (-ENODEV) if *port_id* invalid.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_set_queue_rate_limit(uint8_t port_id, uint16_t queue_idx,\n\t\t\tuint16_t tx_rate);\n\n/**\n * Set the rate limitation for a vf on an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param vf\n * VF id.\n * @param tx_rate\n * The tx rate allocated from the total link speed for this VF id.\n * @param q_msk\n * The queue mask which need to set the rate.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support this feature.\n * - (-ENODEV) if *port_id* invalid.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_set_vf_rate_limit(uint8_t port_id, uint16_t vf,\n\t\t\tuint16_t tx_rate, uint64_t q_msk);\n\n/**\n * Initialize bypass logic. This function needs to be called before\n * executing any other bypass API.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_bypass_init(uint8_t port);\n\n/**\n * Return bypass state.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param state\n * The return bypass state.\n * - (1) Normal mode\n * - (2) Bypass mode\n * - (3) Isolate mode\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_bypass_state_show(uint8_t port, uint32_t *state);\n\n/**\n * Set bypass state\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param new_state\n * The current bypass state.\n * - (1) Normal mode\n * - (2) Bypass mode\n * - (3) Isolate mode\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_bypass_state_set(uint8_t port, uint32_t *new_state);\n\n/**\n * Return bypass state when given event occurs.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param event\n * The bypass event\n * - (1) Main power on (power button is pushed)\n * - (2) Auxiliary power on (power supply is being plugged)\n * - (3) Main power off (system shutdown and power supply is left plugged in)\n * - (4) Auxiliary power off (power supply is being unplugged)\n * - (5) Display or set the watchdog timer\n * @param state\n * The bypass state when given event occurred.\n * - (1) Normal mode\n * - (2) Bypass mode\n * - (3) Isolate mode\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_bypass_event_show(uint8_t port, uint32_t event, uint32_t *state);\n\n/**\n * Set bypass state when given event occurs.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param event\n * The bypass event\n * - (1) Main power on (power button is pushed)\n * - (2) Auxiliary power on (power supply is being plugged)\n * - (3) Main power off (system shutdown and power supply is left plugged in)\n * - (4) Auxiliary power off (power supply is being unplugged)\n * - (5) Display or set the watchdog timer\n * @param state\n * The assigned state when given event occurs.\n * - (1) Normal mode\n * - (2) Bypass mode\n * - (3) Isolate mode\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_bypass_event_store(uint8_t port, uint32_t event, uint32_t state);\n\n/**\n * Set bypass watchdog timeout count.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param timeout\n * The timeout to be set.\n * - (0) 0 seconds (timer is off)\n * - (1) 1.5 seconds\n * - (2) 2 seconds\n * - (3) 3 seconds\n * - (4) 4 seconds\n * - (5) 8 seconds\n * - (6) 16 seconds\n * - (7) 32 seconds\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_wd_timeout_store(uint8_t port, uint32_t timeout);\n\n/**\n * Get bypass firmware version.\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param ver\n * The firmware version\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_bypass_ver_show(uint8_t port, uint32_t *ver);\n\n/**\n * Return bypass watchdog timeout in seconds\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @param wd_timeout\n * The return watchdog timeout. \"0\" represents timer expired\n * - (0) 0 seconds (timer is off)\n * - (1) 1.5 seconds\n * - (2) 2 seconds\n * - (3) 3 seconds\n * - (4) 4 seconds\n * - (5) 8 seconds\n * - (6) 16 seconds\n * - (7) 32 seconds\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_bypass_wd_timeout_show(uint8_t port, uint32_t *wd_timeout);\n\n/**\n * Reset bypass watchdog timer\n *\n * @param port\n * The port identifier of the Ethernet device.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_bypass_wd_reset(uint8_t port);\n\n /**\n * Configuration of Receive Side Scaling hash computation of Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param rss_conf\n * The new configuration to use for RSS hash computation on the port.\n * @return\n * - (0) if successful.\n * - (-ENODEV) if port identifier is invalid.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-EINVAL) if bad parameter.\n */\nint rte_eth_dev_rss_hash_update(uint8_t port_id,\n\t\t\t\tstruct rte_eth_rss_conf *rss_conf);\n\n /**\n * Retrieve current configuration of Receive Side Scaling hash computation\n * of Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param rss_conf\n * Where to store the current RSS hash configuration of the Ethernet device.\n * @return\n * - (0) if successful.\n * - (-ENODEV) if port identifier is invalid.\n * - (-ENOTSUP) if hardware doesn't support RSS.\n */\nint\nrte_eth_dev_rss_hash_conf_get(uint8_t port_id,\n\t\t\t struct rte_eth_rss_conf *rss_conf);\n\n /**\n * Add UDP tunneling port of an Ethernet device for filtering a specific\n * tunneling packet by UDP port number.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param tunnel_udp\n * UDP tunneling configuration.\n *\n * @return\n * - (0) if successful.\n * - (-ENODEV) if port identifier is invalid.\n * - (-ENOTSUP) if hardware doesn't support tunnel type.\n */\nint\nrte_eth_dev_udp_tunnel_add(uint8_t port_id,\n\t\t\t struct rte_eth_udp_tunnel *tunnel_udp);\n\n /**\n * Detete UDP tunneling port configuration of Ethernet device\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param tunnel_udp\n * UDP tunneling configuration.\n *\n * @return\n * - (0) if successful.\n * - (-ENODEV) if port identifier is invalid.\n * - (-ENOTSUP) if hardware doesn't support tunnel type.\n */\nint\nrte_eth_dev_udp_tunnel_delete(uint8_t port_id,\n\t\t\t struct rte_eth_udp_tunnel *tunnel_udp);\n\n/**\n * Check whether the filter type is supported on an Ethernet device.\n * All the supported filter types are defined in 'rte_eth_ctrl.h'.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param filter_type\n * Filter type.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support this filter type.\n * - (-ENODEV) if *port_id* invalid.\n */\nint rte_eth_dev_filter_supported(uint8_t port_id, enum rte_filter_type filter_type);\n\n/**\n * Take operations to assigned filter type on an Ethernet device.\n * All the supported operations and filter types are defined in 'rte_eth_ctrl.h'.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param filter_type\n * Filter type.\n * @param filter_op\n * Type of operation.\n * @param arg\n * A pointer to arguments defined specifically for the operation.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-ENODEV) if *port_id* invalid.\n * - others depends on the specific operations implementation.\n */\nint rte_eth_dev_filter_ctrl(uint8_t port_id, enum rte_filter_type filter_type,\n\t\t\tenum rte_filter_op filter_op, void *arg);\n\n/**\n * Add a callback to be called on packet RX on a given port and queue.\n *\n * This API configures a function to be called for each burst of\n * packets received on a given NIC port queue. The return value is a pointer\n * that can be used to later remove the callback using\n * rte_eth_remove_rx_callback().\n *\n * Multiple functions are called in the order that they are added.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param queue_id\n * The queue on the Ethernet device on which the callback is to be added.\n * @param fn\n * The callback function\n * @param user_param\n * A generic pointer parameter which will be passed to each invocation of the\n * callback function on this port and queue.\n *\n * @return\n * NULL on error.\n * On success, a pointer value which can later be used to remove the callback.\n */\nvoid *rte_eth_add_rx_callback(uint8_t port_id, uint16_t queue_id,\n\t\trte_rx_callback_fn fn, void *user_param);\n\n/**\n * Add a callback to be called on packet TX on a given port and queue.\n *\n * This API configures a function to be called for each burst of\n * packets sent on a given NIC port queue. The return value is a pointer\n * that can be used to later remove the callback using\n * rte_eth_remove_tx_callback().\n *\n * Multiple functions are called in the order that they are added.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param queue_id\n * The queue on the Ethernet device on which the callback is to be added.\n * @param fn\n * The callback function\n * @param user_param\n * A generic pointer parameter which will be passed to each invocation of the\n * callback function on this port and queue.\n *\n * @return\n * NULL on error.\n * On success, a pointer value which can later be used to remove the callback.\n */\nvoid *rte_eth_add_tx_callback(uint8_t port_id, uint16_t queue_id,\n\t\trte_tx_callback_fn fn, void *user_param);\n\n/**\n * Remove an RX packet callback from a given port and queue.\n *\n * This function is used to removed callbacks that were added to a NIC port\n * queue using rte_eth_add_rx_callback().\n *\n * Note: the callback is removed from the callback list but it isn't freed\n * since the it may still be in use. The memory for the callback can be\n * subsequently freed back by the application by calling rte_free():\n *\n * - Immediately - if the port is stopped, or the user knows that no\n * callbacks are in flight e.g. if called from the thread doing RX/TX\n * on that queue.\n *\n * - After a short delay - where the delay is sufficient to allow any\n * in-flight callbacks to complete.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param queue_id\n * The queue on the Ethernet device from which the callback is to be removed.\n * @param user_cb\n * User supplied callback created via rte_eth_add_rx_callback().\n *\n * @return\n * - 0: Success. Callback was removed.\n * - -ENOTSUP: Callback support is not available.\n * - -EINVAL: The port_id or the queue_id is out of range, or the callback\n * is NULL or not found for the port/queue.\n */\nint rte_eth_remove_rx_callback(uint8_t port_id, uint16_t queue_id,\n\t\tstruct rte_eth_rxtx_callback *user_cb);\n\n/**\n * Remove a TX packet callback from a given port and queue.\n *\n * This function is used to removed callbacks that were added to a NIC port\n * queue using rte_eth_add_tx_callback().\n *\n * Note: the callback is removed from the callback list but it isn't freed\n * since the it may still be in use. The memory for the callback can be\n * subsequently freed back by the application by calling rte_free():\n *\n * - Immediately - if the port is stopped, or the user knows that no\n * callbacks are in flight e.g. if called from the thread doing RX/TX\n * on that queue.\n *\n * - After a short delay - where the delay is sufficient to allow any\n * in-flight callbacks to complete.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param queue_id\n * The queue on the Ethernet device from which the callback is to be removed.\n * @param user_cb\n * User supplied callback created via rte_eth_add_tx_callback().\n *\n * @return\n * - 0: Success. Callback was removed.\n * - -ENOTSUP: Callback support is not available.\n * - -EINVAL: The port_id or the queue_id is out of range, or the callback\n * is NULL or not found for the port/queue.\n */\nint rte_eth_remove_tx_callback(uint8_t port_id, uint16_t queue_id,\n\t\tstruct rte_eth_rxtx_callback *user_cb);\n\n/**\n * Retrieve number of available registers for access\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @return\n * - (>=0) number of registers if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-ENODEV) if *port_id* invalid.\n * - others depends on the specific operations implementation.\n */\nint rte_eth_dev_get_reg_length(uint8_t port_id);\n\n/**\n * Retrieve device registers and register attributes\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param info\n * The template includes buffer for register data and attribute to be filled.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-ENODEV) if *port_id* invalid.\n * - others depends on the specific operations implementation.\n */\nint rte_eth_dev_get_reg_info(uint8_t port_id, struct rte_dev_reg_info *info);\n\n/**\n * Retrieve size of device EEPROM\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @return\n * - (>=0) EEPROM size if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-ENODEV) if *port_id* invalid.\n * - others depends on the specific operations implementation.\n */\nint rte_eth_dev_get_eeprom_length(uint8_t port_id);\n\n/**\n * Retrieve EEPROM and EEPROM attribute\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param info\n * The template includes buffer for return EEPROM data and\n * EEPROM attributes to be filled.\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-ENODEV) if *port_id* invalid.\n * - others depends on the specific operations implementation.\n */\nint rte_eth_dev_get_eeprom(uint8_t port_id, struct rte_dev_eeprom_info *info);\n\n/**\n * Program EEPROM with provided data\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param info\n * The template includes EEPROM data for programming and\n * EEPROM attributes to be filled\n * @return\n * - (0) if successful.\n * - (-ENOTSUP) if hardware doesn't support.\n * - (-ENODEV) if *port_id* invalid.\n * - others depends on the specific operations implementation.\n */\nint rte_eth_dev_set_eeprom(uint8_t port_id, struct rte_dev_eeprom_info *info);\n\n/**\n * Set the list of multicast addresses to filter on an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param mc_addr_set\n * The array of multicast addresses to set. Equal to NULL when the function\n * is invoked to flush the set of filtered addresses.\n * @param nb_mc_addr\n * The number of multicast addresses in the *mc_addr_set* array. Equal to 0\n * when the function is invoked to flush the set of filtered addresses.\n * @return\n * - (0) if successful.\n * - (-ENODEV) if *port_id* invalid.\n * - (-ENOTSUP) if PMD of *port_id* doesn't support multicast filtering.\n * - (-ENOSPC) if *port_id* has not enough multicast filtering resources.\n */\nint rte_eth_dev_set_mc_addr_list(uint8_t port_id,\n\t\t\t\t struct ether_addr *mc_addr_set,\n\t\t\t\t uint32_t nb_mc_addr);\n\n/**\n * Enable IEEE1588/802.1AS timestamping for an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n *\n * @return\n * - 0: Success.\n * - -ENODEV: The port ID is invalid.\n * - -ENOTSUP: The function is not supported by the Ethernet driver.\n */\nextern int rte_eth_timesync_enable(uint8_t port_id);\n\n/**\n * Disable IEEE1588/802.1AS timestamping for an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n *\n * @return\n * - 0: Success.\n * - -ENODEV: The port ID is invalid.\n * - -ENOTSUP: The function is not supported by the Ethernet driver.\n */\nextern int rte_eth_timesync_disable(uint8_t port_id);\n\n/**\n * Read an IEEE1588/802.1AS RX timestamp from an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param timestamp\n * Pointer to the timestamp struct.\n * @param flags\n * Device specific flags. Used to pass the RX timesync register index to\n * i40e. Unused in igb/ixgbe, pass 0 instead.\n *\n * @return\n * - 0: Success.\n * - -EINVAL: No timestamp is available.\n * - -ENODEV: The port ID is invalid.\n * - -ENOTSUP: The function is not supported by the Ethernet driver.\n */\nextern int rte_eth_timesync_read_rx_timestamp(uint8_t port_id,\n\t\t\t\t\t struct timespec *timestamp,\n\t\t\t\t\t uint32_t flags);\n\n/**\n * Read an IEEE1588/802.1AS TX timestamp from an Ethernet device.\n *\n * @param port_id\n * The port identifier of the Ethernet device.\n * @param timestamp\n * Pointer to the timestamp struct.\n *\n * @return\n * - 0: Success.\n * - -EINVAL: No timestamp is available.\n * - -ENODEV: The port ID is invalid.\n * - -ENOTSUP: The function is not supported by the Ethernet driver.\n */\nextern int rte_eth_timesync_read_tx_timestamp(uint8_t port_id,\n\t\t\t\t\t struct timespec *timestamp);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_ETHDEV_H_ */\n" }, { "path": "lib/librte_ether/rte_ether.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ETHER_H_\n#define _RTE_ETHER_H_\n\n/**\n * @file\n *\n * Ethernet Helpers in RTE\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#define ETHER_ADDR_LEN 6 /**< Length of Ethernet address. */\n#define ETHER_TYPE_LEN 2 /**< Length of Ethernet type field. */\n#define ETHER_CRC_LEN 4 /**< Length of Ethernet CRC. */\n#define ETHER_HDR_LEN \\\n\t(ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN) /**< Length of Ethernet header. */\n#define ETHER_MIN_LEN 64 /**< Minimum frame len, including CRC. */\n#define ETHER_MAX_LEN 1518 /**< Maximum frame len, including CRC. */\n#define ETHER_MTU \\\n\t(ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) /**< Ethernet MTU. */\n\n#define ETHER_MAX_VLAN_FRAME_LEN \\\n\t(ETHER_MAX_LEN + 4) /**< Maximum VLAN frame length, including CRC. */\n\n#define ETHER_MAX_JUMBO_FRAME_LEN \\\n\t0x3F00 /**< Maximum Jumbo frame length, including CRC. */\n\n#define ETHER_MAX_VLAN_ID 4095 /**< Maximum VLAN ID. */\n\n#define ETHER_MIN_MTU 68 /**< Minimum MTU for IPv4 packets, see RFC 791. */\n\n/**\n * Ethernet address:\n * A universally administered address is uniquely assigned to a device by its\n * manufacturer. The first three octets (in transmission order) contain the\n * Organizationally Unique Identifier (OUI). The following three (MAC-48 and\n * EUI-48) octets are assigned by that organization with the only constraint\n * of uniqueness.\n * A locally administered address is assigned to a device by a network\n * administrator and does not contain OUIs.\n * See http://standards.ieee.org/regauth/groupmac/tutorial.html\n */\nstruct ether_addr {\n\tuint8_t addr_bytes[ETHER_ADDR_LEN]; /**< Address bytes in transmission order */\n} __attribute__((__packed__));\n\n#define ETHER_LOCAL_ADMIN_ADDR 0x02 /**< Locally assigned Eth. address. */\n#define ETHER_GROUP_ADDR 0x01 /**< Multicast or broadcast Eth. address. */\n\n/**\n * Check if two Ethernet addresses are the same.\n *\n * @param ea1\n * A pointer to the first ether_addr structure containing\n * the ethernet address.\n * @param ea2\n * A pointer to the second ether_addr structure containing\n * the ethernet address.\n *\n * @return\n * True (1) if the given two ethernet address are the same;\n * False (0) otherwise.\n */\nstatic inline int is_same_ether_addr(const struct ether_addr *ea1,\n\t\t\t\t const struct ether_addr *ea2)\n{\n\tint i;\n\tfor (i = 0; i < ETHER_ADDR_LEN; i++)\n\t\tif (ea1->addr_bytes[i] != ea2->addr_bytes[i])\n\t\t\treturn 0;\n\treturn 1;\n}\n\n/**\n * Check if an Ethernet address is filled with zeros.\n *\n * @param ea\n * A pointer to a ether_addr structure containing the ethernet address\n * to check.\n * @return\n * True (1) if the given ethernet address is filled with zeros;\n * false (0) otherwise.\n */\nstatic inline int is_zero_ether_addr(const struct ether_addr *ea)\n{\n\tint i;\n\tfor (i = 0; i < ETHER_ADDR_LEN; i++)\n\t\tif (ea->addr_bytes[i] != 0x00)\n\t\t\treturn 0;\n\treturn 1;\n}\n\n/**\n * Check if an Ethernet address is a unicast address.\n *\n * @param ea\n * A pointer to a ether_addr structure containing the ethernet address\n * to check.\n * @return\n * True (1) if the given ethernet address is a unicast address;\n * false (0) otherwise.\n */\nstatic inline int is_unicast_ether_addr(const struct ether_addr *ea)\n{\n\treturn ((ea->addr_bytes[0] & ETHER_GROUP_ADDR) == 0);\n}\n\n/**\n * Check if an Ethernet address is a multicast address.\n *\n * @param ea\n * A pointer to a ether_addr structure containing the ethernet address\n * to check.\n * @return\n * True (1) if the given ethernet address is a multicast address;\n * false (0) otherwise.\n */\nstatic inline int is_multicast_ether_addr(const struct ether_addr *ea)\n{\n\treturn (ea->addr_bytes[0] & ETHER_GROUP_ADDR);\n}\n\n/**\n * Check if an Ethernet address is a broadcast address.\n *\n * @param ea\n * A pointer to a ether_addr structure containing the ethernet address\n * to check.\n * @return\n * True (1) if the given ethernet address is a broadcast address;\n * false (0) otherwise.\n */\nstatic inline int is_broadcast_ether_addr(const struct ether_addr *ea)\n{\n\tconst unaligned_uint16_t *ea_words = (const unaligned_uint16_t *)ea;\n\n\treturn (ea_words[0] == 0xFFFF && ea_words[1] == 0xFFFF &&\n\t\tea_words[2] == 0xFFFF);\n}\n\n/**\n * Check if an Ethernet address is a universally assigned address.\n *\n * @param ea\n * A pointer to a ether_addr structure containing the ethernet address\n * to check.\n * @return\n * True (1) if the given ethernet address is a universally assigned address;\n * false (0) otherwise.\n */\nstatic inline int is_universal_ether_addr(const struct ether_addr *ea)\n{\n\treturn ((ea->addr_bytes[0] & ETHER_LOCAL_ADMIN_ADDR) == 0);\n}\n\n/**\n * Check if an Ethernet address is a locally assigned address.\n *\n * @param ea\n * A pointer to a ether_addr structure containing the ethernet address\n * to check.\n * @return\n * True (1) if the given ethernet address is a locally assigned address;\n * false (0) otherwise.\n */\nstatic inline int is_local_admin_ether_addr(const struct ether_addr *ea)\n{\n\treturn ((ea->addr_bytes[0] & ETHER_LOCAL_ADMIN_ADDR) != 0);\n}\n\n/**\n * Check if an Ethernet address is a valid address. Checks that the address is a\n * unicast address and is not filled with zeros.\n *\n * @param ea\n * A pointer to a ether_addr structure containing the ethernet address\n * to check.\n * @return\n * True (1) if the given ethernet address is valid;\n * false (0) otherwise.\n */\nstatic inline int is_valid_assigned_ether_addr(const struct ether_addr *ea)\n{\n\treturn (is_unicast_ether_addr(ea) && (! is_zero_ether_addr(ea)));\n}\n\n/**\n * Generate a random Ethernet address that is locally administered\n * and not multicast.\n * @param addr\n * A pointer to Ethernet address.\n */\nstatic inline void eth_random_addr(uint8_t *addr)\n{\n\tuint64_t rand = rte_rand();\n\tuint8_t *p = (uint8_t*)&rand;\n\n\trte_memcpy(addr, p, ETHER_ADDR_LEN);\n\taddr[0] &= ~ETHER_GROUP_ADDR; /* clear multicast bit */\n\taddr[0] |= ETHER_LOCAL_ADMIN_ADDR; /* set local assignment bit */\n}\n\n/**\n * Fast copy an Ethernet address.\n *\n * @param ea_from\n * A pointer to a ether_addr structure holding the Ethernet address to copy.\n * @param ea_to\n * A pointer to a ether_addr structure where to copy the Ethernet address.\n */\nstatic inline void ether_addr_copy(const struct ether_addr *ea_from,\n\t\t\t\t struct ether_addr *ea_to)\n{\n#ifdef __INTEL_COMPILER\n\tuint16_t *from_words = (uint16_t *)(ea_from->addr_bytes);\n\tuint16_t *to_words = (uint16_t *)(ea_to->addr_bytes);\n\n\tto_words[0] = from_words[0];\n\tto_words[1] = from_words[1];\n\tto_words[2] = from_words[2];\n#else\n\t/*\n\t * Use the common way, because of a strange gcc warning.\n\t */\n\t*ea_to = *ea_from;\n#endif\n}\n\n#define ETHER_ADDR_FMT_SIZE 18\n/**\n * Format 48bits Ethernet address in pattern xx:xx:xx:xx:xx:xx.\n *\n * @param buf\n * A pointer to buffer contains the formatted MAC address.\n * @param size\n * The format buffer size.\n * @param eth_addr\n * A pointer to a ether_addr structure.\n */\nstatic inline void\nether_format_addr(char *buf, uint16_t size,\n\t\t const struct ether_addr *eth_addr)\n{\n\tsnprintf(buf, size, \"%02X:%02X:%02X:%02X:%02X:%02X\",\n\t\t eth_addr->addr_bytes[0],\n\t\t eth_addr->addr_bytes[1],\n\t\t eth_addr->addr_bytes[2],\n\t\t eth_addr->addr_bytes[3],\n\t\t eth_addr->addr_bytes[4],\n\t\t eth_addr->addr_bytes[5]);\n}\n\n/**\n * Ethernet header: Contains the destination address, source address\n * and frame type.\n */\nstruct ether_hdr {\n\tstruct ether_addr d_addr; /**< Destination address. */\n\tstruct ether_addr s_addr; /**< Source address. */\n\tuint16_t ether_type; /**< Frame type. */\n} __attribute__((__packed__));\n\n/**\n * Ethernet VLAN Header.\n * Contains the 16-bit VLAN Tag Control Identifier and the Ethernet type\n * of the encapsulated frame.\n */\nstruct vlan_hdr {\n\tuint16_t vlan_tci; /**< Priority (3) + CFI (1) + Identifier Code (12) */\n\tuint16_t eth_proto;/**< Ethernet type of encapsulated frame. */\n} __attribute__((__packed__));\n\n/**\n * VXLAN protocol header.\n * Contains the 8-bit flag, 24-bit VXLAN Network Identifier and\n * Reserved fields (24 bits and 8 bits)\n */\nstruct vxlan_hdr {\n\tuint32_t vx_flags; /**< flag (8) + Reserved (24). */\n\tuint32_t vx_vni; /**< VNI (24) + Reserved (8). */\n} __attribute__((__packed__));\n\n/* Ethernet frame types */\n#define ETHER_TYPE_IPv4 0x0800 /**< IPv4 Protocol. */\n#define ETHER_TYPE_IPv6 0x86DD /**< IPv6 Protocol. */\n#define ETHER_TYPE_ARP 0x0806 /**< Arp Protocol. */\n#define ETHER_TYPE_RARP 0x8035 /**< Reverse Arp Protocol. */\n#define ETHER_TYPE_VLAN 0x8100 /**< IEEE 802.1Q VLAN tagging. */\n#define ETHER_TYPE_1588 0x88F7 /**< IEEE 802.1AS 1588 Precise Time Protocol. */\n#define ETHER_TYPE_SLOW 0x8809 /**< Slow protocols (LACP and Marker). */\n#define ETHER_TYPE_TEB 0x6558 /**< Transparent Ethernet Bridging. */\n\n#define ETHER_VXLAN_HLEN (sizeof(struct udp_hdr) + sizeof(struct vxlan_hdr))\n/**< VXLAN tunnel header length. */\n\n/**\n * Extract VLAN tag information into mbuf\n *\n * Software version of VLAN stripping\n *\n * @param m\n * The packet mbuf.\n * @return\n * - 0: Success\n * - 1: not a vlan packet\n */\nstatic inline int rte_vlan_strip(struct rte_mbuf *m)\n{\n\tstruct ether_hdr *eh\n\t\t = rte_pktmbuf_mtod(m, struct ether_hdr *);\n\n\tif (eh->ether_type != rte_cpu_to_be_16(ETHER_TYPE_VLAN))\n\t\treturn -1;\n\n\tstruct vlan_hdr *vh = (struct vlan_hdr *)(eh + 1);\n\tm->ol_flags |= PKT_RX_VLAN_PKT;\n\tm->vlan_tci = rte_be_to_cpu_16(vh->vlan_tci);\n\n\t/* Copy ether header over rather than moving whole packet */\n\tmemmove(rte_pktmbuf_adj(m, sizeof(struct vlan_hdr)),\n\t\teh, 2 * ETHER_ADDR_LEN);\n\n\treturn 0;\n}\n\n/**\n * Insert VLAN tag into mbuf.\n *\n * Software version of VLAN unstripping\n *\n * @param m\n * The packet mbuf.\n * @return\n * - 0: On success\n * -EPERM: mbuf is is shared overwriting would be unsafe\n * -ENOSPC: not enough headroom in mbuf\n */\nstatic inline int rte_vlan_insert(struct rte_mbuf **m)\n{\n\tstruct ether_hdr *oh, *nh;\n\tstruct vlan_hdr *vh;\n\n\t/* Can't insert header if mbuf is shared */\n\tif (rte_mbuf_refcnt_read(*m) > 1) {\n\t\tstruct rte_mbuf *copy;\n\n\t\tcopy = rte_pktmbuf_clone(*m, (*m)->pool);\n\t\tif (unlikely(copy == NULL))\n\t\t\treturn -ENOMEM;\n\t\trte_pktmbuf_free(*m);\n\t\t*m = copy;\n\t}\n\n\toh = rte_pktmbuf_mtod(*m, struct ether_hdr *);\n\tnh = (struct ether_hdr *)\n\t\trte_pktmbuf_prepend(*m, sizeof(struct vlan_hdr));\n\tif (nh == NULL)\n\t\treturn -ENOSPC;\n\n\tmemmove(nh, oh, 2 * ETHER_ADDR_LEN);\n\tnh->ether_type = rte_cpu_to_be_16(ETHER_TYPE_VLAN);\n\n\tvh = (struct vlan_hdr *) (nh + 1);\n\tvh->vlan_tci = rte_cpu_to_be_16((*m)->vlan_tci);\n\n\treturn 0;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_ETHER_H_ */\n" }, { "path": "lib/librte_hash/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_hash.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR)\n\nEXPORT_MAP := rte_hash_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_HASH) := rte_cuckoo_hash.c\nSRCS-$(CONFIG_RTE_LIBRTE_HASH) += rte_fbk_hash.c\n\n# install this header file\nSYMLINK-$(CONFIG_RTE_LIBRTE_HASH)-include := rte_hash.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_HASH)-include += rte_hash_crc.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_HASH)-include += rte_jhash.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_HASH)-include += rte_thash.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_HASH)-include += rte_fbk_hash.h\n\n# this lib needs eal and ring\nDEPDIRS-$(CONFIG_RTE_LIBRTE_HASH) += lib/librte_eal lib/librte_ring\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_hash/rte_cmp_x86.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/* Functions to compare multiple of 16 byte keys (up to 128 bytes) */\nstatic int\nrte_hash_k16_cmp_eq(const void *key1, const void *key2, size_t key_len __rte_unused)\n{\n\tconst __m128i k1 = _mm_loadu_si128((const __m128i *) key1);\n\tconst __m128i k2 = _mm_loadu_si128((const __m128i *) key2);\n#ifdef RTE_MACHINE_CPUFLAG_SSE4_1\n\tconst __m128i x = _mm_xor_si128(k1, k2);\n\n\treturn !_mm_test_all_zeros(x, x);\n#else\n\tconst __m128i x = _mm_cmpeq_epi32(k1, k2);\n\n\treturn (_mm_movemask_epi8(x) != 0xffff);\n#endif\n}\n\nstatic int\nrte_hash_k32_cmp_eq(const void *key1, const void *key2, size_t key_len)\n{\n\treturn rte_hash_k16_cmp_eq(key1, key2, key_len) ||\n\t\trte_hash_k16_cmp_eq((const char *) key1 + 16,\n\t\t\t\t(const char *) key2 + 16, key_len);\n}\n\nstatic int\nrte_hash_k48_cmp_eq(const void *key1, const void *key2, size_t key_len)\n{\n\treturn rte_hash_k16_cmp_eq(key1, key2, key_len) ||\n\t\trte_hash_k16_cmp_eq((const char *) key1 + 16,\n\t\t\t\t(const char *) key2 + 16, key_len) ||\n\t\trte_hash_k16_cmp_eq((const char *) key1 + 32,\n\t\t\t\t(const char *) key2 + 32, key_len);\n}\n\nstatic int\nrte_hash_k64_cmp_eq(const void *key1, const void *key2, size_t key_len)\n{\n\treturn rte_hash_k32_cmp_eq(key1, key2, key_len) ||\n\t\trte_hash_k32_cmp_eq((const char *) key1 + 32,\n\t\t\t\t(const char *) key2 + 32, key_len);\n}\n\nstatic int\nrte_hash_k80_cmp_eq(const void *key1, const void *key2, size_t key_len)\n{\n\treturn rte_hash_k64_cmp_eq(key1, key2, key_len) ||\n\t\trte_hash_k16_cmp_eq((const char *) key1 + 64,\n\t\t\t\t(const char *) key2 + 64, key_len);\n}\n\nstatic int\nrte_hash_k96_cmp_eq(const void *key1, const void *key2, size_t key_len)\n{\n\treturn rte_hash_k64_cmp_eq(key1, key2, key_len) ||\n\t\trte_hash_k32_cmp_eq((const char *) key1 + 64,\n\t\t\t\t(const char *) key2 + 64, key_len);\n}\n\nstatic int\nrte_hash_k112_cmp_eq(const void *key1, const void *key2, size_t key_len)\n{\n\treturn rte_hash_k64_cmp_eq(key1, key2, key_len) ||\n\t\trte_hash_k32_cmp_eq((const char *) key1 + 64,\n\t\t\t\t(const char *) key2 + 64, key_len) ||\n\t\trte_hash_k16_cmp_eq((const char *) key1 + 96,\n\t\t\t\t(const char *) key2 + 96, key_len);\n}\n\nstatic int\nrte_hash_k128_cmp_eq(const void *key1, const void *key2, size_t key_len)\n{\n\treturn rte_hash_k64_cmp_eq(key1, key2, key_len) ||\n\t\trte_hash_k64_cmp_eq((const char *) key1 + 64,\n\t\t\t\t(const char *) key2 + 64, key_len);\n}\n" }, { "path": "lib/librte_hash/rte_cuckoo_hash.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include /* for definition of RTE_CACHE_LINE_SIZE */\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_hash.h\"\n#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_X32)\n#include \"rte_cmp_x86.h\"\n#endif\n\nTAILQ_HEAD(rte_hash_list, rte_tailq_entry);\n\nstatic struct rte_tailq_elem rte_hash_tailq = {\n\t.name = \"RTE_HASH\",\n};\nEAL_REGISTER_TAILQ(rte_hash_tailq)\n\n/* Macro to enable/disable run-time checking of function parameters */\n#if defined(RTE_LIBRTE_HASH_DEBUG)\n#define RETURN_IF_TRUE(cond, retval) do { \\\n\tif (cond) \\\n\t\treturn retval; \\\n} while (0)\n#else\n#define RETURN_IF_TRUE(cond, retval)\n#endif\n\n/* Hash function used if none is specified */\n#ifdef RTE_MACHINE_CPUFLAG_SSE4_2\n#include \n#define DEFAULT_HASH_FUNC rte_hash_crc\n#else\n#include \n#define DEFAULT_HASH_FUNC rte_jhash\n#endif\n\n/** Number of items per bucket. */\n#define RTE_HASH_BUCKET_ENTRIES\t\t4\n\n#define NULL_SIGNATURE\t\t\t0\n\n#define KEY_ALIGNMENT\t\t\t16\n\ntypedef int (*rte_hash_cmp_eq_t)(const void *key1, const void *key2, size_t key_len);\n\n/** A hash table structure. */\nstruct rte_hash {\n\tchar name[RTE_HASH_NAMESIZE]; /**< Name of the hash. */\n\tuint32_t entries; /**< Total table entries. */\n\tuint32_t num_buckets; /**< Number of buckets in table. */\n\tuint32_t key_len; /**< Length of hash key. */\n\trte_hash_function hash_func; /**< Function used to calculate hash. */\n\tuint32_t hash_func_init_val; /**< Init value used by hash_func. */\n\trte_hash_cmp_eq_t rte_hash_cmp_eq; /**< Function used to compare keys. */\n\tuint32_t bucket_bitmask; /**< Bitmask for getting bucket index\n\t\t\t\t\t\tfrom hash signature. */\n\tuint32_t key_entry_size; /**< Size of each key entry. */\n\n\tstruct rte_ring *free_slots; /**< Ring that stores all indexes\n\t\t\t\t\t\tof the free slots in the key table */\n\tvoid *key_store; /**< Table storing all keys and data */\n\tstruct rte_hash_bucket *buckets;\t/**< Table with buckets storing all the\n\t\t\t\t\t\t\thash values and key indexes\n\t\t\t\t\t\t\tto the key table*/\n} __rte_cache_aligned;\n\n/* Structure storing both primary and secondary hashes */\nstruct rte_hash_signatures {\n\tunion {\n\t\tstruct {\n\t\t\thash_sig_t current;\n\t\t\thash_sig_t alt;\n\t\t};\n\t\tuint64_t sig;\n\t};\n};\n\n/* Structure that stores key-value pair */\nstruct rte_hash_key {\n\tunion {\n\t\tuintptr_t idata;\n\t\tvoid *pdata;\n\t};\n\t/* Variable key size */\n\tchar key[0];\n} __attribute__((aligned(KEY_ALIGNMENT)));\n\n/** Bucket structure */\nstruct rte_hash_bucket {\n\tstruct rte_hash_signatures signatures[RTE_HASH_BUCKET_ENTRIES];\n\t/* Includes dummy key index that always contains index 0 */\n\tuint32_t key_idx[RTE_HASH_BUCKET_ENTRIES + 1];\n\tuint8_t flag[RTE_HASH_BUCKET_ENTRIES];\n} __rte_cache_aligned;\n\nstruct rte_hash *\nrte_hash_find_existing(const char *name)\n{\n\tstruct rte_hash *h = NULL;\n\tstruct rte_tailq_entry *te;\n\tstruct rte_hash_list *hash_list;\n\n\thash_list = RTE_TAILQ_CAST(rte_hash_tailq.head, rte_hash_list);\n\n\trte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);\n\tTAILQ_FOREACH(te, hash_list, next) {\n\t\th = (struct rte_hash *) te->data;\n\t\tif (strncmp(name, h->name, RTE_HASH_NAMESIZE) == 0)\n\t\t\tbreak;\n\t}\n\trte_rwlock_read_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\tif (te == NULL) {\n\t\trte_errno = ENOENT;\n\t\treturn NULL;\n\t}\n\treturn h;\n}\n\nstruct rte_hash *\nrte_hash_create(const struct rte_hash_parameters *params)\n{\n\tstruct rte_hash *h = NULL;\n\tstruct rte_tailq_entry *te = NULL;\n\tstruct rte_hash_list *hash_list;\n\tstruct rte_ring *r = NULL;\n\tchar hash_name[RTE_HASH_NAMESIZE];\n\tvoid *ptr, *k = NULL;\n\tvoid *buckets = NULL;\n\tchar ring_name[RTE_RING_NAMESIZE];\n\tunsigned i;\n\n\thash_list = RTE_TAILQ_CAST(rte_hash_tailq.head, rte_hash_list);\n\n\tif (params == NULL) {\n\t\tRTE_LOG(ERR, HASH, \"rte_hash_create has no parameters\\n\");\n\t\treturn NULL;\n\t}\n\n\t/* Check for valid parameters */\n\tif ((params->entries > RTE_HASH_ENTRIES_MAX) ||\n\t\t\t(params->entries < RTE_HASH_BUCKET_ENTRIES) ||\n\t\t\t!rte_is_power_of_2(RTE_HASH_BUCKET_ENTRIES) ||\n\t\t\t(params->key_len == 0)) {\n\t\trte_errno = EINVAL;\n\t\tRTE_LOG(ERR, HASH, \"rte_hash_create has invalid parameters\\n\");\n\t\treturn NULL;\n\t}\n\n\tsnprintf(hash_name, sizeof(hash_name), \"HT_%s\", params->name);\n\n\t/* Guarantee there's no existing */\n\th = rte_hash_find_existing(params->name);\n\tif (h != NULL)\n\t\treturn h;\n\n\tte = rte_zmalloc(\"HASH_TAILQ_ENTRY\", sizeof(*te), 0);\n\tif (te == NULL) {\n\t\tRTE_LOG(ERR, HASH, \"tailq entry allocation failed\\n\");\n\t\tgoto err;\n\t}\n\n\th = (struct rte_hash *)rte_zmalloc_socket(hash_name, sizeof(struct rte_hash),\n\t\t\t\t\tRTE_CACHE_LINE_SIZE, params->socket_id);\n\n\tif (h == NULL) {\n\t\tRTE_LOG(ERR, HASH, \"memory allocation failed\\n\");\n\t\tgoto err;\n\t}\n\n\tconst uint32_t num_buckets = rte_align32pow2(params->entries)\n\t\t\t\t\t/ RTE_HASH_BUCKET_ENTRIES;\n\n\tbuckets = rte_zmalloc_socket(NULL,\n\t\t\t\tnum_buckets * sizeof(struct rte_hash_bucket),\n\t\t\t\tRTE_CACHE_LINE_SIZE, params->socket_id);\n\n\tif (buckets == NULL) {\n\t\tRTE_LOG(ERR, HASH, \"memory allocation failed\\n\");\n\t\tgoto err;\n\t}\n\n\tconst uint32_t key_entry_size = sizeof(struct rte_hash_key) + params->key_len;\n\n\t/* Store all keys and leave the first entry as a dummy entry for lookup_bulk */\n\tconst uint64_t key_tbl_size = key_entry_size * (params->entries + 1);\n\n\tk = rte_zmalloc_socket(NULL, key_tbl_size,\n\t\t\tRTE_CACHE_LINE_SIZE, params->socket_id);\n\n\tif (k == NULL) {\n\t\tRTE_LOG(ERR, HASH, \"memory allocation failed\\n\");\n\t\tgoto err;\n\t}\n\n/*\n * If x86 architecture is used, select appropriate compare function,\n * which may use x86 instrinsics, otherwise use memcmp\n */\n#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_X32)\n\t/* Select function to compare keys */\n\tswitch (params->key_len) {\n\tcase 16:\n\t\th->rte_hash_cmp_eq = rte_hash_k16_cmp_eq;\n\t\tbreak;\n\tcase 32:\n\t\th->rte_hash_cmp_eq = rte_hash_k32_cmp_eq;\n\t\tbreak;\n\tcase 48:\n\t\th->rte_hash_cmp_eq = rte_hash_k48_cmp_eq;\n\t\tbreak;\n\tcase 64:\n\t\th->rte_hash_cmp_eq = rte_hash_k64_cmp_eq;\n\t\tbreak;\n\tcase 80:\n\t\th->rte_hash_cmp_eq = rte_hash_k80_cmp_eq;\n\t\tbreak;\n\tcase 96:\n\t\th->rte_hash_cmp_eq = rte_hash_k96_cmp_eq;\n\t\tbreak;\n\tcase 112:\n\t\th->rte_hash_cmp_eq = rte_hash_k112_cmp_eq;\n\t\tbreak;\n\tcase 128:\n\t\th->rte_hash_cmp_eq = rte_hash_k128_cmp_eq;\n\t\tbreak;\n\tdefault:\n\t\t/* If key is not multiple of 16, use generic memcmp */\n\t\th->rte_hash_cmp_eq = memcmp;\n\t}\n#else\n\th->rte_hash_cmp_eq = memcmp;\n#endif\n\n\tsnprintf(ring_name, sizeof(ring_name), \"HT_%s\", params->name);\n\tr = rte_ring_lookup(ring_name);\n\tif (r != NULL) {\n\t\t/* clear the free ring */\n\t\twhile (rte_ring_dequeue(r, &ptr) == 0)\n\t\t\trte_pause();\n\t} else\n\t\tr = rte_ring_create(ring_name, rte_align32pow2(params->entries + 1),\n\t\t\t\tparams->socket_id, 0);\n\tif (r == NULL) {\n\t\tRTE_LOG(ERR, HASH, \"memory allocation failed\\n\");\n\t\tgoto err;\n\t}\n\n\t/* Setup hash context */\n\tsnprintf(h->name, sizeof(h->name), \"%s\", params->name);\n\th->entries = params->entries;\n\th->key_len = params->key_len;\n\th->key_entry_size = key_entry_size;\n\th->hash_func_init_val = params->hash_func_init_val;\n\n\th->num_buckets = num_buckets;\n\th->bucket_bitmask = h->num_buckets - 1;\n\th->buckets = buckets;\n\th->hash_func = (params->hash_func == NULL) ?\n\t\tDEFAULT_HASH_FUNC : params->hash_func;\n\n\th->key_store = k;\n\th->free_slots = r;\n\n\t/* populate the free slots ring. Entry zero is reserved for key misses */\n\tfor (i = 1; i < params->entries + 1; i++)\n\t\trte_ring_sp_enqueue(r, (void *)((uintptr_t) i));\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\tte->data = (void *) h;\n\tTAILQ_INSERT_TAIL(hash_list, te, next);\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\treturn h;\nerr:\n\trte_free(te);\n\trte_free(h);\n\trte_free(buckets);\n\trte_free(k);\n\treturn NULL;\n}\n\nvoid\nrte_hash_free(struct rte_hash *h)\n{\n\tstruct rte_tailq_entry *te;\n\tstruct rte_hash_list *hash_list;\n\n\tif (h == NULL)\n\t\treturn;\n\n\thash_list = RTE_TAILQ_CAST(rte_hash_tailq.head, rte_hash_list);\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* find out tailq entry */\n\tTAILQ_FOREACH(te, hash_list, next) {\n\t\tif (te->data == (void *) h)\n\t\t\tbreak;\n\t}\n\n\tif (te == NULL) {\n\t\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\t\treturn;\n\t}\n\n\tTAILQ_REMOVE(hash_list, te, next);\n\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\trte_free(h->key_store);\n\trte_free(h->buckets);\n\trte_free(h);\n\trte_free(te);\n}\n\nhash_sig_t\nrte_hash_hash(const struct rte_hash *h, const void *key)\n{\n\t/* calc hash result by key */\n\treturn h->hash_func(key, h->key_len, h->hash_func_init_val);\n}\n\n/* Calc the secondary hash value from the primary hash value of a given key */\nstatic inline hash_sig_t\nrte_hash_secondary_hash(const hash_sig_t primary_hash)\n{\n\tstatic const unsigned all_bits_shift = 12;\n\tstatic const unsigned alt_bits_xor = 0x5bd1e995;\n\n\tuint32_t tag = primary_hash >> all_bits_shift;\n\n\treturn (primary_hash ^ ((tag + 1) * alt_bits_xor));\n}\n\nvoid\nrte_hash_reset(struct rte_hash *h)\n{\n\tvoid *ptr;\n\tunsigned i;\n\n\tif (h == NULL)\n\t\treturn;\n\n\tmemset(h->buckets, 0, h->num_buckets * sizeof(struct rte_hash_bucket));\n\tmemset(h->key_store, 0, h->key_entry_size * (h->entries + 1));\n\n\t/* clear the free ring */\n\twhile (rte_ring_dequeue(h->free_slots, &ptr) == 0)\n\t\trte_pause();\n\n\t/* Repopulate the free slots ring. Entry zero is reserved for key misses */\n\tfor (i = 1; i < h->entries + 1; i++)\n\t\trte_ring_sp_enqueue(h->free_slots, (void *)((uintptr_t) i));\n}\n\n/* Search for an entry that can be pushed to its alternative location */\nstatic inline int\nmake_space_bucket(const struct rte_hash *h, struct rte_hash_bucket *bkt)\n{\n\tunsigned i, j;\n\tint ret;\n\tuint32_t next_bucket_idx;\n\tstruct rte_hash_bucket *next_bkt[RTE_HASH_BUCKET_ENTRIES];\n\n\t/*\n\t * Push existing item (search for bucket with space in\n\t * alternative locations) to its alternative location\n\t */\n\tfor (i = 0; i < RTE_HASH_BUCKET_ENTRIES; i++) {\n\t\t/* Search for space in alternative locations */\n\t\tnext_bucket_idx = bkt->signatures[i].alt & h->bucket_bitmask;\n\t\tnext_bkt[i] = &h->buckets[next_bucket_idx];\n\t\tfor (j = 0; j < RTE_HASH_BUCKET_ENTRIES; j++) {\n\t\t\tif (next_bkt[i]->signatures[j].sig == NULL_SIGNATURE)\n\t\t\t\tbreak;\n\t\t}\n\n\t\tif (j != RTE_HASH_BUCKET_ENTRIES)\n\t\t\tbreak;\n\t}\n\n\t/* Alternative location has spare room (end of recursive function) */\n\tif (i != RTE_HASH_BUCKET_ENTRIES) {\n\t\tnext_bkt[i]->signatures[j].alt = bkt->signatures[i].current;\n\t\tnext_bkt[i]->signatures[j].current = bkt->signatures[i].alt;\n\t\tnext_bkt[i]->key_idx[j] = bkt->key_idx[i];\n\t\treturn i;\n\t}\n\n\t/* Pick entry that has not been pushed yet */\n\tfor (i = 0; i < RTE_HASH_BUCKET_ENTRIES; i++)\n\t\tif (bkt->flag[i] == 0)\n\t\t\tbreak;\n\n\t/* All entries have been pushed, so entry cannot be added */\n\tif (i == RTE_HASH_BUCKET_ENTRIES)\n\t\treturn -ENOSPC;\n\n\t/* Set flag to indicate that this entry is going to be pushed */\n\tbkt->flag[i] = 1;\n\t/* Need room in alternative bucket to insert the pushed entry */\n\tret = make_space_bucket(h, next_bkt[i]);\n\t/*\n\t * After recursive function.\n\t * Clear flags and insert the pushed entry\n\t * in its alternative location if successful,\n\t * or return error\n\t */\n\tbkt->flag[i] = 0;\n\tif (ret >= 0) {\n\t\tnext_bkt[i]->signatures[ret].alt = bkt->signatures[i].current;\n\t\tnext_bkt[i]->signatures[ret].current = bkt->signatures[i].alt;\n\t\tnext_bkt[i]->key_idx[ret] = bkt->key_idx[i];\n\t\treturn i;\n\t} else\n\t\treturn ret;\n\n}\n\nstatic inline int32_t\n__rte_hash_add_key_with_hash(const struct rte_hash *h, const void *key,\n\t\t\t\t\t\thash_sig_t sig, void *data)\n{\n\thash_sig_t alt_hash;\n\tuint32_t prim_bucket_idx, sec_bucket_idx;\n\tunsigned i;\n\tstruct rte_hash_bucket *prim_bkt, *sec_bkt;\n\tstruct rte_hash_key *new_k, *k, *keys = h->key_store;\n\tvoid *slot_id;\n\tuint32_t new_idx;\n\tint ret;\n\n\tprim_bucket_idx = sig & h->bucket_bitmask;\n\tprim_bkt = &h->buckets[prim_bucket_idx];\n\trte_prefetch0(prim_bkt);\n\n\talt_hash = rte_hash_secondary_hash(sig);\n\tsec_bucket_idx = alt_hash & h->bucket_bitmask;\n\tsec_bkt = &h->buckets[sec_bucket_idx];\n\trte_prefetch0(sec_bkt);\n\n\t/* Get a new slot for storing the new key */\n\tif (rte_ring_sc_dequeue(h->free_slots, &slot_id) != 0)\n\t\treturn -ENOSPC;\n\tnew_k = RTE_PTR_ADD(keys, (uintptr_t)slot_id * h->key_entry_size);\n\trte_prefetch0(new_k);\n\tnew_idx = (uint32_t)((uintptr_t) slot_id);\n\n\t/* Check if key is already inserted in primary location */\n\tfor (i = 0; i < RTE_HASH_BUCKET_ENTRIES; i++) {\n\t\tif (prim_bkt->signatures[i].current == sig &&\n\t\t\t\tprim_bkt->signatures[i].alt == alt_hash) {\n\t\t\tk = (struct rte_hash_key *) ((char *)keys +\n\t\t\t\t\tprim_bkt->key_idx[i] * h->key_entry_size);\n\t\t\tif (h->rte_hash_cmp_eq(key, k->key, h->key_len) == 0) {\n\t\t\t\trte_ring_sp_enqueue(h->free_slots, slot_id);\n\t\t\t\t/* Update data */\n\t\t\t\tk->pdata = data;\n\t\t\t\t/*\n\t\t\t\t * Return index where key is stored,\n\t\t\t\t * substracting the first dummy index\n\t\t\t\t */\n\t\t\t\treturn (prim_bkt->key_idx[i] - 1);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Check if key is already inserted in secondary location */\n\tfor (i = 0; i < RTE_HASH_BUCKET_ENTRIES; i++) {\n\t\tif (sec_bkt->signatures[i].alt == sig &&\n\t\t\t\tsec_bkt->signatures[i].current == alt_hash) {\n\t\t\tk = (struct rte_hash_key *) ((char *)keys +\n\t\t\t\t\tsec_bkt->key_idx[i] * h->key_entry_size);\n\t\t\tif (h->rte_hash_cmp_eq(key, k->key, h->key_len) == 0) {\n\t\t\t\trte_ring_sp_enqueue(h->free_slots, slot_id);\n\t\t\t\t/* Update data */\n\t\t\t\tk->pdata = data;\n\t\t\t\t/*\n\t\t\t\t * Return index where key is stored,\n\t\t\t\t * substracting the first dummy index\n\t\t\t\t */\n\t\t\t\treturn (sec_bkt->key_idx[i] - 1);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Copy key */\n\trte_memcpy(new_k->key, key, h->key_len);\n\tnew_k->pdata = data;\n\n\t/* Insert new entry is there is room in the primary bucket */\n\tfor (i = 0; i < RTE_HASH_BUCKET_ENTRIES; i++) {\n\t\t/* Check if slot is available */\n\t\tif (likely(prim_bkt->signatures[i].sig == NULL_SIGNATURE)) {\n\t\t\tprim_bkt->signatures[i].current = sig;\n\t\t\tprim_bkt->signatures[i].alt = alt_hash;\n\t\t\tprim_bkt->key_idx[i] = new_idx;\n\t\t\treturn new_idx - 1;\n\t\t}\n\t}\n\n\t/* Primary bucket is full, so we need to make space for new entry */\n\tret = make_space_bucket(h, prim_bkt);\n\t/*\n\t * After recursive function.\n\t * Insert the new entry in the position of the pushed entry\n\t * if successful or return error and\n\t * store the new slot back in the ring\n\t */\n\tif (ret >= 0) {\n\t\tprim_bkt->signatures[ret].current = sig;\n\t\tprim_bkt->signatures[ret].alt = alt_hash;\n\t\tprim_bkt->key_idx[ret] = new_idx;\n\t\treturn (new_idx - 1);\n\t}\n\n\t/* Error in addition, store new slot back in the ring and return error */\n\trte_ring_sp_enqueue(h->free_slots,\n\t\t(void *)((uintptr_t) new_idx));\n\treturn ret;\n\n}\n\nint32_t\nrte_hash_add_key_with_hash(const struct rte_hash *h,\n\t\t\tconst void *key, hash_sig_t sig)\n{\n\tRETURN_IF_TRUE(((h == NULL) || (key == NULL)), -EINVAL);\n\treturn __rte_hash_add_key_with_hash(h, key, sig, 0);\n}\n\nint32_t\nrte_hash_add_key(const struct rte_hash *h, const void *key)\n{\n\tRETURN_IF_TRUE(((h == NULL) || (key == NULL)), -EINVAL);\n\treturn __rte_hash_add_key_with_hash(h, key, rte_hash_hash(h, key), 0);\n}\n\nint\nrte_hash_add_key_with_hash_data(const struct rte_hash *h,\n\t\t\tconst void *key, hash_sig_t sig, void *data)\n{\n\tint ret;\n\n\tRETURN_IF_TRUE(((h == NULL) || (key == NULL)), -EINVAL);\n\tret = __rte_hash_add_key_with_hash(h, key, sig, data);\n\tif (ret >= 0)\n\t\treturn 0;\n\telse\n\t\treturn ret;\n}\n\nint\nrte_hash_add_key_data(const struct rte_hash *h, const void *key, void *data)\n{\n\tint ret;\n\n\tRETURN_IF_TRUE(((h == NULL) || (key == NULL)), -EINVAL);\n\n\tret = __rte_hash_add_key_with_hash(h, key, rte_hash_hash(h, key), data);\n\tif (ret >= 0)\n\t\treturn 0;\n\telse\n\t\treturn ret;\n}\nstatic inline int32_t\n__rte_hash_lookup_with_hash(const struct rte_hash *h, const void *key,\n\t\t\t\t\thash_sig_t sig, void **data)\n{\n\tuint32_t bucket_idx;\n\thash_sig_t alt_hash;\n\tunsigned i;\n\tstruct rte_hash_bucket *bkt;\n\tstruct rte_hash_key *k, *keys = h->key_store;\n\n\tbucket_idx = sig & h->bucket_bitmask;\n\tbkt = &h->buckets[bucket_idx];\n\n\t/* Check if key is in primary location */\n\tfor (i = 0; i < RTE_HASH_BUCKET_ENTRIES; i++) {\n\t\tif (bkt->signatures[i].current == sig &&\n\t\t\t\tbkt->signatures[i].sig != NULL_SIGNATURE) {\n\t\t\tk = (struct rte_hash_key *) ((char *)keys +\n\t\t\t\t\tbkt->key_idx[i] * h->key_entry_size);\n\t\t\tif (h->rte_hash_cmp_eq(key, k->key, h->key_len) == 0) {\n\t\t\t\tif (data != NULL)\n\t\t\t\t\t*data = k->pdata;\n\t\t\t\t/*\n\t\t\t\t * Return index where key is stored,\n\t\t\t\t * substracting the first dummy index\n\t\t\t\t */\n\t\t\t\treturn (bkt->key_idx[i] - 1);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Calculate secondary hash */\n\talt_hash = rte_hash_secondary_hash(sig);\n\tbucket_idx = alt_hash & h->bucket_bitmask;\n\tbkt = &h->buckets[bucket_idx];\n\n\t/* Check if key is in secondary location */\n\tfor (i = 0; i < RTE_HASH_BUCKET_ENTRIES; i++) {\n\t\tif (bkt->signatures[i].current == alt_hash &&\n\t\t\t\tbkt->signatures[i].alt == sig) {\n\t\t\tk = (struct rte_hash_key *) ((char *)keys +\n\t\t\t\t\tbkt->key_idx[i] * h->key_entry_size);\n\t\t\tif (h->rte_hash_cmp_eq(key, k->key, h->key_len) == 0) {\n\t\t\t\tif (data != NULL)\n\t\t\t\t\t*data = k->pdata;\n\t\t\t\t/*\n\t\t\t\t * Return index where key is stored,\n\t\t\t\t * substracting the first dummy index\n\t\t\t\t */\n\t\t\t\treturn (bkt->key_idx[i] - 1);\n\t\t\t}\n\t\t}\n\t}\n\n\treturn -ENOENT;\n}\n\nint32_t\nrte_hash_lookup_with_hash(const struct rte_hash *h,\n\t\t\tconst void *key, hash_sig_t sig)\n{\n\tRETURN_IF_TRUE(((h == NULL) || (key == NULL)), -EINVAL);\n\treturn __rte_hash_lookup_with_hash(h, key, sig, NULL);\n}\n\nint32_t\nrte_hash_lookup(const struct rte_hash *h, const void *key)\n{\n\tRETURN_IF_TRUE(((h == NULL) || (key == NULL)), -EINVAL);\n\treturn __rte_hash_lookup_with_hash(h, key, rte_hash_hash(h, key), NULL);\n}\n\nint\nrte_hash_lookup_with_hash_data(const struct rte_hash *h,\n\t\t\tconst void *key, hash_sig_t sig, void **data)\n{\n\tRETURN_IF_TRUE(((h == NULL) || (key == NULL)), -EINVAL);\n\treturn __rte_hash_lookup_with_hash(h, key, sig, data);\n}\n\nint\nrte_hash_lookup_data(const struct rte_hash *h, const void *key, void **data)\n{\n\tRETURN_IF_TRUE(((h == NULL) || (key == NULL)), -EINVAL);\n\treturn __rte_hash_lookup_with_hash(h, key, rte_hash_hash(h, key), data);\n}\n\nstatic inline int32_t\n__rte_hash_del_key_with_hash(const struct rte_hash *h, const void *key,\n\t\t\t\t\t\thash_sig_t sig)\n{\n\tuint32_t bucket_idx;\n\thash_sig_t alt_hash;\n\tunsigned i;\n\tstruct rte_hash_bucket *bkt;\n\tstruct rte_hash_key *k, *keys = h->key_store;\n\n\tbucket_idx = sig & h->bucket_bitmask;\n\tbkt = &h->buckets[bucket_idx];\n\n\t/* Check if key is in primary location */\n\tfor (i = 0; i < RTE_HASH_BUCKET_ENTRIES; i++) {\n\t\tif (bkt->signatures[i].current == sig &&\n\t\t\t\tbkt->signatures[i].sig != NULL_SIGNATURE) {\n\t\t\tk = (struct rte_hash_key *) ((char *)keys +\n\t\t\t\t\tbkt->key_idx[i] * h->key_entry_size);\n\t\t\tif (h->rte_hash_cmp_eq(key, k->key, h->key_len) == 0) {\n\t\t\t\tbkt->signatures[i].sig = NULL_SIGNATURE;\n\t\t\t\trte_ring_sp_enqueue(h->free_slots,\n\t\t\t\t\t\t(void *)((uintptr_t)bkt->key_idx[i]));\n\t\t\t\t/*\n\t\t\t\t * Return index where key is stored,\n\t\t\t\t * substracting the first dummy index\n\t\t\t\t */\n\t\t\t\treturn (bkt->key_idx[i] - 1);\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Calculate secondary hash */\n\talt_hash = rte_hash_secondary_hash(sig);\n\tbucket_idx = alt_hash & h->bucket_bitmask;\n\tbkt = &h->buckets[bucket_idx];\n\n\t/* Check if key is in secondary location */\n\tfor (i = 0; i < RTE_HASH_BUCKET_ENTRIES; i++) {\n\t\tif (bkt->signatures[i].current == alt_hash &&\n\t\t\t\tbkt->signatures[i].sig != NULL_SIGNATURE) {\n\t\t\tk = (struct rte_hash_key *) ((char *)keys +\n\t\t\t\t\tbkt->key_idx[i] * h->key_entry_size);\n\t\t\tif (h->rte_hash_cmp_eq(key, k->key, h->key_len) == 0) {\n\t\t\t\tbkt->signatures[i].sig = NULL_SIGNATURE;\n\t\t\t\trte_ring_sp_enqueue(h->free_slots,\n\t\t\t\t\t\t(void *)((uintptr_t)bkt->key_idx[i]));\n\t\t\t\t/*\n\t\t\t\t * Return index where key is stored,\n\t\t\t\t * substracting the first dummy index\n\t\t\t\t */\n\t\t\t\treturn (bkt->key_idx[i] - 1);\n\t\t\t}\n\t\t}\n\t}\n\n\treturn -ENOENT;\n}\n\nint32_t\nrte_hash_del_key_with_hash(const struct rte_hash *h,\n\t\t\tconst void *key, hash_sig_t sig)\n{\n\tRETURN_IF_TRUE(((h == NULL) || (key == NULL)), -EINVAL);\n\treturn __rte_hash_del_key_with_hash(h, key, sig);\n}\n\nint32_t\nrte_hash_del_key(const struct rte_hash *h, const void *key)\n{\n\tRETURN_IF_TRUE(((h == NULL) || (key == NULL)), -EINVAL);\n\treturn __rte_hash_del_key_with_hash(h, key, rte_hash_hash(h, key));\n}\n\n/* Lookup bulk stage 0: Prefetch input key */\nstatic inline void\nlookup_stage0(unsigned *idx, uint64_t *lookup_mask,\n\t\tconst void * const *keys)\n{\n\t*idx = __builtin_ctzl(*lookup_mask);\n\tif (*lookup_mask == 0)\n\t\t*idx = 0;\n\n\trte_prefetch0(keys[*idx]);\n\t*lookup_mask &= ~(1llu << *idx);\n}\n\n/*\n * Lookup bulk stage 1: Calculate primary/secondary hashes\n * and prefetch primary/secondary buckets\n */\nstatic inline void\nlookup_stage1(unsigned idx, hash_sig_t *prim_hash, hash_sig_t *sec_hash,\n\t\tconst struct rte_hash_bucket **primary_bkt,\n\t\tconst struct rte_hash_bucket **secondary_bkt,\n\t\thash_sig_t *hash_vals, const void * const *keys,\n\t\tconst struct rte_hash *h)\n{\n\t*prim_hash = rte_hash_hash(h, keys[idx]);\n\thash_vals[idx] = *prim_hash;\n\t*sec_hash = rte_hash_secondary_hash(*prim_hash);\n\n\t*primary_bkt = &h->buckets[*prim_hash & h->bucket_bitmask];\n\t*secondary_bkt = &h->buckets[*sec_hash & h->bucket_bitmask];\n\n\trte_prefetch0(*primary_bkt);\n\trte_prefetch0(*secondary_bkt);\n}\n\n/*\n * Lookup bulk stage 2: Search for match hashes in primary/secondary locations\n * and prefetch first key slot\n */\nstatic inline void\nlookup_stage2(unsigned idx, hash_sig_t prim_hash, hash_sig_t sec_hash,\n\t\tconst struct rte_hash_bucket *prim_bkt,\n\t\tconst struct rte_hash_bucket *sec_bkt,\n\t\tconst struct rte_hash_key **key_slot, int32_t *positions,\n\t\tuint64_t *extra_hits_mask, const void *keys,\n\t\tconst struct rte_hash *h)\n{\n\tunsigned prim_hash_matches, sec_hash_matches, key_idx, i;\n\tunsigned total_hash_matches;\n\n\tprim_hash_matches = 1 << RTE_HASH_BUCKET_ENTRIES;\n\tsec_hash_matches = 1 << RTE_HASH_BUCKET_ENTRIES;\n\tfor (i = 0; i < RTE_HASH_BUCKET_ENTRIES; i++) {\n\t\tprim_hash_matches |= ((prim_hash == prim_bkt->signatures[i].current) << i);\n\t\tsec_hash_matches |= ((sec_hash == sec_bkt->signatures[i].current) << i);\n\t}\n\n\tkey_idx = prim_bkt->key_idx[__builtin_ctzl(prim_hash_matches)];\n\tif (key_idx == 0)\n\t\tkey_idx = sec_bkt->key_idx[__builtin_ctzl(sec_hash_matches)];\n\n\ttotal_hash_matches = (prim_hash_matches |\n\t\t\t\t(sec_hash_matches << (RTE_HASH_BUCKET_ENTRIES + 1)));\n\t*key_slot = (const struct rte_hash_key *) ((const char *)keys +\n\t\t\t\t\tkey_idx * h->key_entry_size);\n\n\trte_prefetch0(*key_slot);\n\t/*\n\t * Return index where key is stored,\n\t * substracting the first dummy index\n\t */\n\tpositions[idx] = (key_idx - 1);\n\n\t*extra_hits_mask |= (uint64_t)(__builtin_popcount(total_hash_matches) > 3) << idx;\n\n}\n\n\n/* Lookup bulk stage 3: Check if key matches, update hit mask and return data */\nstatic inline void\nlookup_stage3(unsigned idx, const struct rte_hash_key *key_slot, const void * const *keys,\n\t\tvoid *data[], uint64_t *hits, const struct rte_hash *h)\n{\n\tunsigned hit;\n\n\thit = !h->rte_hash_cmp_eq(key_slot->key, keys[idx], h->key_len);\n\tif (data != NULL)\n\t\tdata[idx] = key_slot->pdata;\n\n\t*hits |= (uint64_t)(hit) << idx;\n}\n\nstatic inline void\n__rte_hash_lookup_bulk(const struct rte_hash *h, const void **keys,\n\t\t\tuint32_t num_keys, int32_t *positions,\n\t\t\tuint64_t *hit_mask, void *data[])\n{\n\tuint64_t hits = 0;\n\tuint64_t extra_hits_mask = 0;\n\tuint64_t lookup_mask, miss_mask;\n\tunsigned idx;\n\tconst void *key_store = h->key_store;\n\tint ret;\n\thash_sig_t hash_vals[RTE_HASH_LOOKUP_BULK_MAX];\n\n\tunsigned idx00, idx01, idx10, idx11, idx20, idx21, idx30, idx31;\n\tconst struct rte_hash_bucket *primary_bkt10, *primary_bkt11;\n\tconst struct rte_hash_bucket *secondary_bkt10, *secondary_bkt11;\n\tconst struct rte_hash_bucket *primary_bkt20, *primary_bkt21;\n\tconst struct rte_hash_bucket *secondary_bkt20, *secondary_bkt21;\n\tconst struct rte_hash_key *k_slot20, *k_slot21, *k_slot30, *k_slot31;\n\thash_sig_t primary_hash10, primary_hash11;\n\thash_sig_t secondary_hash10, secondary_hash11;\n\thash_sig_t primary_hash20, primary_hash21;\n\thash_sig_t secondary_hash20, secondary_hash21;\n\n\tlookup_mask = (uint64_t) -1 >> (64 - num_keys);\n\tmiss_mask = lookup_mask;\n\n\tlookup_stage0(&idx00, &lookup_mask, keys);\n\tlookup_stage0(&idx01, &lookup_mask, keys);\n\n\tidx10 = idx00, idx11 = idx01;\n\n\tlookup_stage0(&idx00, &lookup_mask, keys);\n\tlookup_stage0(&idx01, &lookup_mask, keys);\n\tlookup_stage1(idx10, &primary_hash10, &secondary_hash10,\n\t\t\t&primary_bkt10, &secondary_bkt10, hash_vals, keys, h);\n\tlookup_stage1(idx11, &primary_hash11, &secondary_hash11,\n\t\t\t&primary_bkt11,\t&secondary_bkt11, hash_vals, keys, h);\n\n\tprimary_bkt20 = primary_bkt10;\n\tprimary_bkt21 = primary_bkt11;\n\tsecondary_bkt20 = secondary_bkt10;\n\tsecondary_bkt21 = secondary_bkt11;\n\tprimary_hash20 = primary_hash10;\n\tprimary_hash21 = primary_hash11;\n\tsecondary_hash20 = secondary_hash10;\n\tsecondary_hash21 = secondary_hash11;\n\tidx20 = idx10, idx21 = idx11;\n\tidx10 = idx00, idx11 = idx01;\n\n\tlookup_stage0(&idx00, &lookup_mask, keys);\n\tlookup_stage0(&idx01, &lookup_mask, keys);\n\tlookup_stage1(idx10, &primary_hash10, &secondary_hash10,\n\t\t\t&primary_bkt10, &secondary_bkt10, hash_vals, keys, h);\n\tlookup_stage1(idx11, &primary_hash11, &secondary_hash11,\n\t\t\t&primary_bkt11,\t&secondary_bkt11, hash_vals, keys, h);\n\tlookup_stage2(idx20, primary_hash20, secondary_hash20, primary_bkt20,\n\t\t\tsecondary_bkt20, &k_slot20, positions, &extra_hits_mask,\n\t\t\tkey_store, h);\n\tlookup_stage2(idx21, primary_hash21, secondary_hash21, primary_bkt21,\n\t\t\tsecondary_bkt21, &k_slot21, positions, &extra_hits_mask,\n\t\t\tkey_store, h);\n\n\twhile (lookup_mask) {\n\t\tk_slot30 = k_slot20, k_slot31 = k_slot21;\n\t\tidx30 = idx20, idx31 = idx21;\n\t\tprimary_bkt20 = primary_bkt10;\n\t\tprimary_bkt21 = primary_bkt11;\n\t\tsecondary_bkt20 = secondary_bkt10;\n\t\tsecondary_bkt21 = secondary_bkt11;\n\t\tprimary_hash20 = primary_hash10;\n\t\tprimary_hash21 = primary_hash11;\n\t\tsecondary_hash20 = secondary_hash10;\n\t\tsecondary_hash21 = secondary_hash11;\n\t\tidx20 = idx10, idx21 = idx11;\n\t\tidx10 = idx00, idx11 = idx01;\n\n\t\tlookup_stage0(&idx00, &lookup_mask, keys);\n\t\tlookup_stage0(&idx01, &lookup_mask, keys);\n\t\tlookup_stage1(idx10, &primary_hash10, &secondary_hash10,\n\t\t\t&primary_bkt10, &secondary_bkt10, hash_vals, keys, h);\n\t\tlookup_stage1(idx11, &primary_hash11, &secondary_hash11,\n\t\t\t&primary_bkt11,\t&secondary_bkt11, hash_vals, keys, h);\n\t\tlookup_stage2(idx20, primary_hash20, secondary_hash20,\n\t\t\tprimary_bkt20, secondary_bkt20, &k_slot20, positions,\n\t\t\t&extra_hits_mask, key_store, h);\n\t\tlookup_stage2(idx21, primary_hash21, secondary_hash21,\n\t\t\tprimary_bkt21, secondary_bkt21,\t&k_slot21, positions,\n\t\t\t&extra_hits_mask, key_store, h);\n\t\tlookup_stage3(idx30, k_slot30, keys, data, &hits, h);\n\t\tlookup_stage3(idx31, k_slot31, keys, data, &hits, h);\n\t}\n\n\tk_slot30 = k_slot20, k_slot31 = k_slot21;\n\tidx30 = idx20, idx31 = idx21;\n\tprimary_bkt20 = primary_bkt10;\n\tprimary_bkt21 = primary_bkt11;\n\tsecondary_bkt20 = secondary_bkt10;\n\tsecondary_bkt21 = secondary_bkt11;\n\tprimary_hash20 = primary_hash10;\n\tprimary_hash21 = primary_hash11;\n\tsecondary_hash20 = secondary_hash10;\n\tsecondary_hash21 = secondary_hash11;\n\tidx20 = idx10, idx21 = idx11;\n\tidx10 = idx00, idx11 = idx01;\n\n\tlookup_stage1(idx10, &primary_hash10, &secondary_hash10,\n\t\t&primary_bkt10, &secondary_bkt10, hash_vals, keys, h);\n\tlookup_stage1(idx11, &primary_hash11, &secondary_hash11,\n\t\t&primary_bkt11,\t&secondary_bkt11, hash_vals, keys, h);\n\tlookup_stage2(idx20, primary_hash20, secondary_hash20, primary_bkt20,\n\t\tsecondary_bkt20, &k_slot20, positions, &extra_hits_mask,\n\t\tkey_store, h);\n\tlookup_stage2(idx21, primary_hash21, secondary_hash21, primary_bkt21,\n\t\tsecondary_bkt21, &k_slot21, positions, &extra_hits_mask,\n\t\tkey_store, h);\n\tlookup_stage3(idx30, k_slot30, keys, data, &hits, h);\n\tlookup_stage3(idx31, k_slot31, keys, data, &hits, h);\n\n\tk_slot30 = k_slot20, k_slot31 = k_slot21;\n\tidx30 = idx20, idx31 = idx21;\n\tprimary_bkt20 = primary_bkt10;\n\tprimary_bkt21 = primary_bkt11;\n\tsecondary_bkt20 = secondary_bkt10;\n\tsecondary_bkt21 = secondary_bkt11;\n\tprimary_hash20 = primary_hash10;\n\tprimary_hash21 = primary_hash11;\n\tsecondary_hash20 = secondary_hash10;\n\tsecondary_hash21 = secondary_hash11;\n\tidx20 = idx10, idx21 = idx11;\n\n\tlookup_stage2(idx20, primary_hash20, secondary_hash20, primary_bkt20,\n\t\tsecondary_bkt20, &k_slot20, positions, &extra_hits_mask,\n\t\tkey_store, h);\n\tlookup_stage2(idx21, primary_hash21, secondary_hash21, primary_bkt21,\n\t\tsecondary_bkt21, &k_slot21, positions, &extra_hits_mask,\n\t\tkey_store, h);\n\tlookup_stage3(idx30, k_slot30, keys, data, &hits, h);\n\tlookup_stage3(idx31, k_slot31, keys, data, &hits, h);\n\n\tk_slot30 = k_slot20, k_slot31 = k_slot21;\n\tidx30 = idx20, idx31 = idx21;\n\n\tlookup_stage3(idx30, k_slot30, keys, data, &hits, h);\n\tlookup_stage3(idx31, k_slot31, keys, data, &hits, h);\n\n\t/* ignore any items we have already found */\n\textra_hits_mask &= ~hits;\n\n\tif (unlikely(extra_hits_mask)) {\n\t\t/* run a single search for each remaining item */\n\t\tdo {\n\t\t\tidx = __builtin_ctzl(extra_hits_mask);\n\t\t\tif (data != NULL) {\n\t\t\t\tret = rte_hash_lookup_with_hash_data(h,\n\t\t\t\t\t\tkeys[idx], hash_vals[idx], &data[idx]);\n\t\t\t\tif (ret >= 0)\n\t\t\t\t\thits |= 1ULL << idx;\n\t\t\t} else {\n\t\t\t\tpositions[idx] = rte_hash_lookup_with_hash(h,\n\t\t\t\t\t\t\tkeys[idx], hash_vals[idx]);\n\t\t\t\tif (positions[idx] >= 0)\n\t\t\t\t\thits |= 1llu << idx;\n\t\t\t}\n\t\t\textra_hits_mask &= ~(1llu << idx);\n\t\t} while (extra_hits_mask);\n\t}\n\n\tmiss_mask &= ~hits;\n\tif (unlikely(miss_mask)) {\n\t\tdo {\n\t\t\tidx = __builtin_ctzl(miss_mask);\n\t\t\tpositions[idx] = -ENOENT;\n\t\t\tmiss_mask &= ~(1llu << idx);\n\t\t} while (miss_mask);\n\t}\n\n\tif (hit_mask != NULL)\n\t\t*hit_mask = hits;\n}\n\nint\nrte_hash_lookup_bulk(const struct rte_hash *h, const void **keys,\n\t\t uint32_t num_keys, int32_t *positions)\n{\n\tRETURN_IF_TRUE(((h == NULL) || (keys == NULL) || (num_keys == 0) ||\n\t\t\t(num_keys > RTE_HASH_LOOKUP_BULK_MAX) ||\n\t\t\t(positions == NULL)), -EINVAL);\n\n\t__rte_hash_lookup_bulk(h, keys, num_keys, positions, NULL, NULL);\n\treturn 0;\n}\n\nint\nrte_hash_lookup_bulk_data(const struct rte_hash *h, const void **keys,\n\t\t uint32_t num_keys, uint64_t *hit_mask, void *data[])\n{\n\tRETURN_IF_TRUE(((h == NULL) || (keys == NULL) || (num_keys == 0) ||\n\t\t\t(num_keys > RTE_HASH_LOOKUP_BULK_MAX) ||\n\t\t\t(hit_mask == NULL)), -EINVAL);\n\n\tint32_t positions[num_keys];\n\n\t__rte_hash_lookup_bulk(h, keys, num_keys, positions, hit_mask, data);\n\n\t/* Return number of hits */\n\treturn __builtin_popcountl(*hit_mask);\n}\n\nint32_t\nrte_hash_iterate(const struct rte_hash *h, const void **key, void **data, uint32_t *next)\n{\n\tuint32_t bucket_idx, idx, position;\n\tstruct rte_hash_key *next_key;\n\n\tRETURN_IF_TRUE(((h == NULL) || (next == NULL)), -EINVAL);\n\n\tconst uint32_t total_entries = h->num_buckets * RTE_HASH_BUCKET_ENTRIES;\n\t/* Out of bounds */\n\tif (*next >= total_entries)\n\t\treturn -ENOENT;\n\n\t/* Calculate bucket and index of current iterator */\n\tbucket_idx = *next / RTE_HASH_BUCKET_ENTRIES;\n\tidx = *next % RTE_HASH_BUCKET_ENTRIES;\n\n\t/* If current position is empty, go to the next one */\n\twhile (h->buckets[bucket_idx].signatures[idx].sig == NULL_SIGNATURE) {\n\t\t(*next)++;\n\t\t/* End of table */\n\t\tif (*next == total_entries)\n\t\t\treturn -ENOENT;\n\t\tbucket_idx = *next / RTE_HASH_BUCKET_ENTRIES;\n\t\tidx = *next % RTE_HASH_BUCKET_ENTRIES;\n\t}\n\n\t/* Get position of entry in key table */\n\tposition = h->buckets[bucket_idx].key_idx[idx];\n\tnext_key = (struct rte_hash_key *) ((char *)h->key_store +\n\t\t\t\tposition * h->key_entry_size);\n\t/* Return key and data */\n\t*key = next_key->key;\n\t*data = next_key->pdata;\n\n\t/* Increment iterator */\n\t(*next)++;\n\n\treturn (position - 1);\n}\n" }, { "path": "lib/librte_hash/rte_fbk_hash.c", "content": "/**\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_fbk_hash.h\"\n\nTAILQ_HEAD(rte_fbk_hash_list, rte_tailq_entry);\n\nstatic struct rte_tailq_elem rte_fbk_hash_tailq = {\n\t.name = \"RTE_FBK_HASH\",\n};\nEAL_REGISTER_TAILQ(rte_fbk_hash_tailq)\n\n/**\n * Performs a lookup for an existing hash table, and returns a pointer to\n * the table if found.\n *\n * @param name\n * Name of the hash table to find\n *\n * @return\n * pointer to hash table structure or NULL on error.\n */\nstruct rte_fbk_hash_table *\nrte_fbk_hash_find_existing(const char *name)\n{\n\tstruct rte_fbk_hash_table *h = NULL;\n\tstruct rte_tailq_entry *te;\n\tstruct rte_fbk_hash_list *fbk_hash_list;\n\n\tfbk_hash_list = RTE_TAILQ_CAST(rte_fbk_hash_tailq.head,\n\t\t\t\t rte_fbk_hash_list);\n\n\trte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);\n\tTAILQ_FOREACH(te, fbk_hash_list, next) {\n\t\th = (struct rte_fbk_hash_table *) te->data;\n\t\tif (strncmp(name, h->name, RTE_FBK_HASH_NAMESIZE) == 0)\n\t\t\tbreak;\n\t}\n\trte_rwlock_read_unlock(RTE_EAL_TAILQ_RWLOCK);\n\tif (te == NULL) {\n\t\trte_errno = ENOENT;\n\t\treturn NULL;\n\t}\n\treturn h;\n}\n\n/**\n * Create a new hash table for use with four byte keys.\n *\n * @param params\n * Parameters used in creation of hash table.\n *\n * @return\n * Pointer to hash table structure that is used in future hash table\n * operations, or NULL on error.\n */\nstruct rte_fbk_hash_table *\nrte_fbk_hash_create(const struct rte_fbk_hash_params *params)\n{\n\tstruct rte_fbk_hash_table *ht = NULL;\n\tstruct rte_tailq_entry *te;\n\tchar hash_name[RTE_FBK_HASH_NAMESIZE];\n\tconst uint32_t mem_size =\n\t\t\tsizeof(*ht) + (sizeof(ht->t[0]) * params->entries);\n\tuint32_t i;\n\tstruct rte_fbk_hash_list *fbk_hash_list;\n\n\tfbk_hash_list = RTE_TAILQ_CAST(rte_fbk_hash_tailq.head,\n\t\t\t\t rte_fbk_hash_list);\n\n\t/* Error checking of parameters. */\n\tif ((!rte_is_power_of_2(params->entries)) ||\n\t\t\t(!rte_is_power_of_2(params->entries_per_bucket)) ||\n\t\t\t(params->entries == 0) ||\n\t\t\t(params->entries_per_bucket == 0) ||\n\t\t\t(params->entries_per_bucket > params->entries) ||\n\t\t\t(params->entries > RTE_FBK_HASH_ENTRIES_MAX) ||\n\t\t\t(params->entries_per_bucket > RTE_FBK_HASH_ENTRIES_PER_BUCKET_MAX)){\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\tsnprintf(hash_name, sizeof(hash_name), \"FBK_%s\", params->name);\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* guarantee there's no existing */\n\tTAILQ_FOREACH(te, fbk_hash_list, next) {\n\t\tht = (struct rte_fbk_hash_table *) te->data;\n\t\tif (strncmp(params->name, ht->name, RTE_FBK_HASH_NAMESIZE) == 0)\n\t\t\tbreak;\n\t}\n\tif (te != NULL)\n\t\tgoto exit;\n\n\tte = rte_zmalloc(\"FBK_HASH_TAILQ_ENTRY\", sizeof(*te), 0);\n\tif (te == NULL) {\n\t\tRTE_LOG(ERR, HASH, \"Failed to allocate tailq entry\\n\");\n\t\tgoto exit;\n\t}\n\n\t/* Allocate memory for table. */\n\tht = (struct rte_fbk_hash_table *)rte_zmalloc_socket(hash_name, mem_size,\n\t\t\t0, params->socket_id);\n\tif (ht == NULL) {\n\t\tRTE_LOG(ERR, HASH, \"Failed to allocate fbk hash table\\n\");\n\t\trte_free(te);\n\t\tgoto exit;\n\t}\n\n\t/* Set up hash table context. */\n\tsnprintf(ht->name, sizeof(ht->name), \"%s\", params->name);\n\tht->entries = params->entries;\n\tht->entries_per_bucket = params->entries_per_bucket;\n\tht->used_entries = 0;\n\tht->bucket_mask = (params->entries / params->entries_per_bucket) - 1;\n\tfor (ht->bucket_shift = 0, i = 1;\n\t (params->entries_per_bucket & i) == 0;\n\t ht->bucket_shift++, i <<= 1)\n\t\t; /* empty loop body */\n\n\tif (params->hash_func != NULL) {\n\t\tht->hash_func = params->hash_func;\n\t\tht->init_val = params->init_val;\n\t}\n\telse {\n\t\tht->hash_func = RTE_FBK_HASH_FUNC_DEFAULT;\n\t\tht->init_val = RTE_FBK_HASH_INIT_VAL_DEFAULT;\n\t}\n\n\tte->data = (void *) ht;\n\n\tTAILQ_INSERT_TAIL(fbk_hash_list, te, next);\n\nexit:\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\treturn ht;\n}\n\n/**\n * Free all memory used by a hash table.\n *\n * @param ht\n * Hash table to deallocate.\n */\nvoid\nrte_fbk_hash_free(struct rte_fbk_hash_table *ht)\n{\n\tstruct rte_tailq_entry *te;\n\tstruct rte_fbk_hash_list *fbk_hash_list;\n\n\tif (ht == NULL)\n\t\treturn;\n\n\tfbk_hash_list = RTE_TAILQ_CAST(rte_fbk_hash_tailq.head,\n\t\t\t\t rte_fbk_hash_list);\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* find out tailq entry */\n\tTAILQ_FOREACH(te, fbk_hash_list, next) {\n\t\tif (te->data == (void *) ht)\n\t\t\tbreak;\n\t}\n\n\tif (te == NULL) {\n\t\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\t\treturn;\n\t}\n\n\tTAILQ_REMOVE(fbk_hash_list, te, next);\n\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\trte_free(ht);\n\trte_free(te);\n}\n" }, { "path": "lib/librte_hash/rte_fbk_hash.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_FBK_HASH_H_\n#define _RTE_FBK_HASH_H_\n\n/**\n * @file\n *\n * This is a hash table implementation for four byte keys (fbk).\n *\n * Note that the return value of the add function should always be checked as,\n * if a bucket is full, the key is not added even if there is space in other\n * buckets. This keeps the lookup function very simple and therefore fast.\n */\n\n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n#ifndef RTE_FBK_HASH_FUNC_DEFAULT\n#ifdef RTE_MACHINE_CPUFLAG_SSE4_2\n#include \n/** Default four-byte key hash function if none is specified. */\n#define RTE_FBK_HASH_FUNC_DEFAULT\t\trte_hash_crc_4byte\n#else\n#include \n#define RTE_FBK_HASH_FUNC_DEFAULT\t\trte_jhash_1word\n#endif\n#endif\n\n#ifndef RTE_FBK_HASH_INIT_VAL_DEFAULT\n/** Initialising value used when calculating hash. */\n#define RTE_FBK_HASH_INIT_VAL_DEFAULT\t\t0xFFFFFFFF\n#endif\n\n/** The maximum number of entries in the hash table that is supported. */\n#define RTE_FBK_HASH_ENTRIES_MAX\t\t(1 << 20)\n\n/** The maximum number of entries in each bucket that is supported. */\n#define RTE_FBK_HASH_ENTRIES_PER_BUCKET_MAX\t256\n\n/** Maximum size of string for naming the hash. */\n#define RTE_FBK_HASH_NAMESIZE\t\t\t32\n\n/** Type of function that can be used for calculating the hash value. */\ntypedef uint32_t (*rte_fbk_hash_fn)(uint32_t key, uint32_t init_val);\n\n/** Parameters used when creating four-byte key hash table. */\nstruct rte_fbk_hash_params {\n\tconst char *name;\t\t/**< Name of the hash table. */\n\tuint32_t entries;\t\t/**< Total number of entries. */\n\tuint32_t entries_per_bucket;\t/**< Number of entries in a bucket. */\n\tint socket_id;\t\t\t/**< Socket to allocate memory on. */\n\trte_fbk_hash_fn hash_func;\t/**< The hash function. */\n\tuint32_t init_val;\t\t/**< For initialising hash function. */\n};\n\n/** Individual entry in the four-byte key hash table. */\nunion rte_fbk_hash_entry {\n\tuint64_t whole_entry;\t\t/**< For accessing entire entry. */\n\tstruct {\n\t\tuint16_t is_entry;\t/**< Non-zero if entry is active. */\n\t\tuint16_t value;\t\t/**< Value returned by lookup. */\n\t\tuint32_t key;\t\t/**< Key used to find value. */\n\t} entry;\t\t\t/**< For accessing each entry part. */\n};\n\n\n/** The four-byte key hash table structure. */\nstruct rte_fbk_hash_table {\n\tchar name[RTE_FBK_HASH_NAMESIZE];\t/**< Name of the hash. */\n\tuint32_t entries;\t\t/**< Total number of entries. */\n\tuint32_t entries_per_bucket;\t/**< Number of entries in a bucket. */\n\tuint32_t used_entries;\t\t/**< How many entries are used. */\n\tuint32_t bucket_mask;\t\t/**< To find which bucket the key is in. */\n\tuint32_t bucket_shift;\t\t/**< Convert bucket to table offset. */\n\trte_fbk_hash_fn hash_func;\t/**< The hash function. */\n\tuint32_t init_val;\t\t/**< For initialising hash function. */\n\n\t/** A flat table of all buckets. */\n\tunion rte_fbk_hash_entry t[0];\n};\n\n/**\n * Find the offset into hash table of the bucket containing a particular key.\n *\n * @param ht\n * Pointer to hash table.\n * @param key\n * Key to calculate bucket for.\n * @return\n * Offset into hash table.\n */\nstatic inline uint32_t\nrte_fbk_hash_get_bucket(const struct rte_fbk_hash_table *ht, uint32_t key)\n{\n\treturn (ht->hash_func(key, ht->init_val) & ht->bucket_mask) <<\n\t\t\tht->bucket_shift;\n}\n\n/**\n * Add a key to an existing hash table with bucket id.\n * This operation is not multi-thread safe\n * and should only be called from one thread.\n *\n * @param ht\n * Hash table to add the key to.\n * @param key\n * Key to add to the hash table.\n * @param value\n * Value to associate with key.\n * @param bucket\n * Bucket to associate with key.\n * @return\n * 0 if ok, or negative value on error.\n */\nstatic inline int\nrte_fbk_hash_add_key_with_bucket(struct rte_fbk_hash_table *ht,\n\t\t\tuint32_t key, uint16_t value, uint32_t bucket)\n{\n\t/*\n\t * The writing of a new value to the hash table is done as a single\n\t * 64bit operation. This should help prevent individual entries being\n\t * corrupted due to race conditions, but it's still possible to\n\t * overwrite entries that have just been made valid.\n\t */\n\tconst uint64_t new_entry = ((uint64_t)(key) << 32) |\n\t\t\t((uint64_t)(value) << 16) |\n\t\t\t1; /* 1 = is_entry bit. */\n\tuint32_t i;\n\n\tfor (i = 0; i < ht->entries_per_bucket; i++) {\n\t\t/* Set entry if unused. */\n\t\tif (! ht->t[bucket + i].entry.is_entry) {\n\t\t\tht->t[bucket + i].whole_entry = new_entry;\n\t\t\tht->used_entries++;\n\t\t\treturn 0;\n\t\t}\n\t\t/* Change value if key already exists. */\n\t\tif (ht->t[bucket + i].entry.key == key) {\n\t\t\tht->t[bucket + i].entry.value = value;\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\treturn -ENOSPC; /* No space in bucket. */\n}\n\n/**\n * Add a key to an existing hash table. This operation is not multi-thread safe\n * and should only be called from one thread.\n *\n * @param ht\n * Hash table to add the key to.\n * @param key\n * Key to add to the hash table.\n * @param value\n * Value to associate with key.\n * @return\n * 0 if ok, or negative value on error.\n */\nstatic inline int\nrte_fbk_hash_add_key(struct rte_fbk_hash_table *ht,\n\t\t\tuint32_t key, uint16_t value)\n{\n\treturn rte_fbk_hash_add_key_with_bucket(ht,\n\t\t\t\tkey, value, rte_fbk_hash_get_bucket(ht, key));\n}\n\n/**\n * Remove a key with a given bucket id from an existing hash table.\n * This operation is not multi-thread\n * safe and should only be called from one thread.\n *\n * @param ht\n * Hash table to remove the key from.\n * @param key\n * Key to remove from the hash table.\n * @param bucket\n * Bucket id associate with key.\n * @return\n * 0 if ok, or negative value on error.\n */\nstatic inline int\nrte_fbk_hash_delete_key_with_bucket(struct rte_fbk_hash_table *ht,\n\t\t\t\t\tuint32_t key, uint32_t bucket)\n{\n\tuint32_t last_entry = ht->entries_per_bucket - 1;\n\tuint32_t i, j;\n\n\tfor (i = 0; i < ht->entries_per_bucket; i++) {\n\t\tif (ht->t[bucket + i].entry.key == key) {\n\t\t\t/* Find last key in bucket. */\n\t\t\tfor (j = ht->entries_per_bucket - 1; j > i; j-- ) {\n\t\t\t\tif (! ht->t[bucket + j].entry.is_entry) {\n\t\t\t\t\tlast_entry = j - 1;\n\t\t\t\t}\n\t\t\t}\n\t\t\t/*\n\t\t\t * Move the last key to the deleted key's position, and\n\t\t\t * delete the last key. lastEntry and i may be same but\n\t\t\t * it doesn't matter.\n\t\t\t */\n\t\t\tht->t[bucket + i].whole_entry =\n\t\t\t\t\tht->t[bucket + last_entry].whole_entry;\n\t\t\tht->t[bucket + last_entry].whole_entry = 0;\n\n\t\t\tht->used_entries--;\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\treturn -ENOENT; /* Key didn't exist. */\n}\n\n/**\n * Remove a key from an existing hash table. This operation is not multi-thread\n * safe and should only be called from one thread.\n *\n * @param ht\n * Hash table to remove the key from.\n * @param key\n * Key to remove from the hash table.\n * @return\n * 0 if ok, or negative value on error.\n */\nstatic inline int\nrte_fbk_hash_delete_key(struct rte_fbk_hash_table *ht, uint32_t key)\n{\n\treturn rte_fbk_hash_delete_key_with_bucket(ht,\n\t\t\t\tkey, rte_fbk_hash_get_bucket(ht, key));\n}\n\n/**\n * Find a key in the hash table with a given bucketid.\n * This operation is multi-thread safe.\n *\n * @param ht\n * Hash table to look in.\n * @param key\n * Key to find.\n * @param bucket\n * Bucket associate to the key.\n * @return\n * The value that was associated with the key, or negative value on error.\n */\nstatic inline int\nrte_fbk_hash_lookup_with_bucket(const struct rte_fbk_hash_table *ht,\n\t\t\t\tuint32_t key, uint32_t bucket)\n{\n\tunion rte_fbk_hash_entry current_entry;\n\tuint32_t i;\n\n\tfor (i = 0; i < ht->entries_per_bucket; i++) {\n\t\t/* Single read of entry, which should be atomic. */\n\t\tcurrent_entry.whole_entry = ht->t[bucket + i].whole_entry;\n\t\tif (! current_entry.entry.is_entry) {\n\t\t\treturn -ENOENT; /* Error once we hit an empty field. */\n\t\t}\n\t\tif (current_entry.entry.key == key) {\n\t\t\treturn current_entry.entry.value;\n\t\t}\n\t}\n\treturn -ENOENT; /* Key didn't exist. */\n}\n\n/**\n * Find a key in the hash table. This operation is multi-thread safe.\n *\n * @param ht\n * Hash table to look in.\n * @param key\n * Key to find.\n * @return\n * The value that was associated with the key, or negative value on error.\n */\nstatic inline int\nrte_fbk_hash_lookup(const struct rte_fbk_hash_table *ht, uint32_t key)\n{\n\treturn rte_fbk_hash_lookup_with_bucket(ht,\n\t\t\t\tkey, rte_fbk_hash_get_bucket(ht, key));\n}\n\n/**\n * Delete all entries in a hash table. This operation is not multi-thread\n * safe and should only be called from one thread.\n *\n * @param ht\n * Hash table to delete entries in.\n */\nstatic inline void\nrte_fbk_hash_clear_all(struct rte_fbk_hash_table *ht)\n{\n\tmemset(ht->t, 0, sizeof(ht->t[0]) * ht->entries);\n\tht->used_entries = 0;\n}\n\n/**\n * Find what fraction of entries are being used.\n *\n * @param ht\n * Hash table to find how many entries are being used in.\n * @return\n * Load factor of the hash table, or negative value on error.\n */\nstatic inline double\nrte_fbk_hash_get_load_factor(struct rte_fbk_hash_table *ht)\n{\n\treturn (double)ht->used_entries / (double)ht->entries;\n}\n\n/**\n * Performs a lookup for an existing hash table, and returns a pointer to\n * the table if found.\n *\n * @param name\n * Name of the hash table to find\n *\n * @return\n * pointer to hash table structure or NULL on error with rte_errno\n * set appropriately. Possible rte_errno values include:\n * - ENOENT - required entry not available to return.\n */\nstruct rte_fbk_hash_table *rte_fbk_hash_find_existing(const char *name);\n\n/**\n * Create a new hash table for use with four byte keys.\n *\n * @param params\n * Parameters used in creation of hash table.\n *\n * @return\n * Pointer to hash table structure that is used in future hash table\n * operations, or NULL on error with rte_errno set appropriately.\n * Possible rte_errno error values include:\n * - E_RTE_NO_CONFIG - function could not get pointer to rte_config structure\n * - E_RTE_SECONDARY - function was called from a secondary process instance\n * - EINVAL - invalid parameter value passed to function\n * - ENOSPC - the maximum number of memzones has already been allocated\n * - EEXIST - a memzone with the same name already exists\n * - ENOMEM - no appropriate memory area found in which to create memzone\n */\nstruct rte_fbk_hash_table * \\\nrte_fbk_hash_create(const struct rte_fbk_hash_params *params);\n\n/**\n * Free all memory used by a hash table.\n * Has no effect on hash tables allocated in memory zones\n *\n * @param ht\n * Hash table to deallocate.\n */\nvoid rte_fbk_hash_free(struct rte_fbk_hash_table *ht);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_FBK_HASH_H_ */\n" }, { "path": "lib/librte_hash/rte_hash.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_HASH_H_\n#define _RTE_HASH_H_\n\n/**\n * @file\n *\n * RTE Hash Table\n */\n\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/** Maximum size of hash table that can be created. */\n#define RTE_HASH_ENTRIES_MAX\t\t\t(1 << 30)\n\n/** @deprecated Maximum bucket size that can be created. */\n#define RTE_HASH_BUCKET_ENTRIES_MAX\t\t4\n\n/** @deprecated Maximum length of key that can be used. */\n#define RTE_HASH_KEY_LENGTH_MAX\t\t\t64\n\n/** Maximum number of characters in hash name.*/\n#define RTE_HASH_NAMESIZE\t\t\t32\n\n/** Maximum number of keys that can be searched for using rte_hash_lookup_bulk. */\n#define RTE_HASH_LOOKUP_BULK_MAX\t\t64\n#define RTE_HASH_LOOKUP_MULTI_MAX\t\tRTE_HASH_LOOKUP_BULK_MAX\n\n/** Signature of key that is stored internally. */\ntypedef uint32_t hash_sig_t;\n\n/** Type of function that can be used for calculating the hash value. */\ntypedef uint32_t (*rte_hash_function)(const void *key, uint32_t key_len,\n\t\t\t\t uint32_t init_val);\n\n/**\n * Parameters used when creating the hash table.\n */\nstruct rte_hash_parameters {\n\tconst char *name;\t\t/**< Name of the hash. */\n\tuint32_t entries;\t\t/**< Total hash table entries. */\n\tuint32_t reserved;\t\t/**< Unused field. Should be set to 0 */\n\tuint32_t key_len;\t\t/**< Length of hash key. */\n\trte_hash_function hash_func;\t/**< Primary Hash function used to calculate hash. */\n\tuint32_t hash_func_init_val;\t/**< Init value used by hash_func. */\n\tint socket_id;\t\t\t/**< NUMA Socket ID for memory. */\n\tuint8_t extra_flag;\t\t/**< Indicate if additional parameters are present. */\n};\n\n/** @internal A hash table structure. */\nstruct rte_hash;\n\n/**\n * Create a new hash table.\n *\n * @param params\n * Parameters used to create and initialise the hash table.\n * @return\n * Pointer to hash table structure that is used in future hash table\n * operations, or NULL on error, with error code set in rte_errno.\n * Possible rte_errno errors include:\n * - E_RTE_NO_CONFIG - function could not get pointer to rte_config structure\n * - E_RTE_SECONDARY - function was called from a secondary process instance\n * - ENOENT - missing entry\n * - EINVAL - invalid parameter passed to function\n * - ENOSPC - the maximum number of memzones has already been allocated\n * - EEXIST - a memzone with the same name already exists\n * - ENOMEM - no appropriate memory area found in which to create memzone\n */\nstruct rte_hash *\nrte_hash_create(const struct rte_hash_parameters *params);\n\n/**\n * Find an existing hash table object and return a pointer to it.\n *\n * @param name\n * Name of the hash table as passed to rte_hash_create()\n * @return\n * Pointer to hash table or NULL if object not found\n * with rte_errno set appropriately. Possible rte_errno values include:\n * - ENOENT - value not available for return\n */\nstruct rte_hash *\nrte_hash_find_existing(const char *name);\n\n/**\n * De-allocate all memory used by hash table.\n * @param h\n * Hash table to free\n */\nvoid\nrte_hash_free(struct rte_hash *h);\n\n/**\n * Reset all hash structure, by zeroing all entries\n * @param h\n * Hash table to reset\n */\nvoid\nrte_hash_reset(struct rte_hash *h);\n\n/**\n * Add a key-value pair to an existing hash table.\n * This operation is not multi-thread safe\n * and should only be called from one thread.\n *\n * @param h\n * Hash table to add the key to.\n * @param key\n * Key to add to the hash table.\n * @param data\n * Data to add to the hash table.\n * @return\n * - 0 if added successfully\n * - -EINVAL if the parameters are invalid.\n * - -ENOSPC if there is no space in the hash for this key.\n */\nint\nrte_hash_add_key_data(const struct rte_hash *h, const void *key, void *data);\n\n/**\n * Add a key-value pair with a pre-computed hash value\n * to an existing hash table.\n * This operation is not multi-thread safe\n * and should only be called from one thread.\n *\n * @param h\n * Hash table to add the key to.\n * @param key\n * Key to add to the hash table.\n * @param sig\n * Precomputed hash value for 'key'\n * @param data\n * Data to add to the hash table.\n * @return\n * - 0 if added successfully\n * - -EINVAL if the parameters are invalid.\n * - -ENOSPC if there is no space in the hash for this key.\n */\nint32_t\nrte_hash_add_key_with_hash_data(const struct rte_hash *h, const void *key,\n\t\t\t\t\t\thash_sig_t sig, void *data);\n\n/**\n * Add a key to an existing hash table. This operation is not multi-thread safe\n * and should only be called from one thread.\n *\n * @param h\n * Hash table to add the key to.\n * @param key\n * Key to add to the hash table.\n * @return\n * - -EINVAL if the parameters are invalid.\n * - -ENOSPC if there is no space in the hash for this key.\n * - A positive value that can be used by the caller as an offset into an\n * array of user data. This value is unique for this key.\n */\nint32_t\nrte_hash_add_key(const struct rte_hash *h, const void *key);\n\n/**\n * Add a key to an existing hash table.\n * This operation is not multi-thread safe\n * and should only be called from one thread.\n *\n * @param h\n * Hash table to add the key to.\n * @param key\n * Key to add to the hash table.\n * @param sig\n * Precomputed hash value for 'key'.\n * @return\n * - -EINVAL if the parameters are invalid.\n * - -ENOSPC if there is no space in the hash for this key.\n * - A positive value that can be used by the caller as an offset into an\n * array of user data. This value is unique for this key.\n */\nint32_t\nrte_hash_add_key_with_hash(const struct rte_hash *h, const void *key, hash_sig_t sig);\n\n/**\n * Remove a key from an existing hash table.\n * This operation is not multi-thread safe\n * and should only be called from one thread.\n *\n * @param h\n * Hash table to remove the key from.\n * @param key\n * Key to remove from the hash table.\n * @return\n * - -EINVAL if the parameters are invalid.\n * - -ENOENT if the key is not found.\n * - A positive value that can be used by the caller as an offset into an\n * array of user data. This value is unique for this key, and is the same\n * value that was returned when the key was added.\n */\nint32_t\nrte_hash_del_key(const struct rte_hash *h, const void *key);\n\n/**\n * Remove a key from an existing hash table.\n * This operation is not multi-thread safe\n * and should only be called from one thread.\n *\n * @param h\n * Hash table to remove the key from.\n * @param key\n * Key to remove from the hash table.\n * @param sig\n * Precomputed hash value for 'key'.\n * @return\n * - -EINVAL if the parameters are invalid.\n * - -ENOENT if the key is not found.\n * - A positive value that can be used by the caller as an offset into an\n * array of user data. This value is unique for this key, and is the same\n * value that was returned when the key was added.\n */\nint32_t\nrte_hash_del_key_with_hash(const struct rte_hash *h, const void *key, hash_sig_t sig);\n\n\n/**\n * Find a key-value pair in the hash table.\n * This operation is multi-thread safe.\n *\n * @param h\n * Hash table to look in.\n * @param key\n * Key to find.\n * @param data\n * Output with pointer to data returned from the hash table.\n * @return\n * 0 if successful lookup\n * - EINVAL if the parameters are invalid.\n * - ENOENT if the key is not found.\n */\nint\nrte_hash_lookup_data(const struct rte_hash *h, const void *key, void **data);\n\n/**\n * Find a key-value pair with a pre-computed hash value\n * to an existing hash table.\n * This operation is multi-thread safe.\n *\n * @param h\n * Hash table to look in.\n * @param key\n * Key to find.\n * @param sig\n * Precomputed hash value for 'key'\n * @param data\n * Output with pointer to data returned from the hash table.\n * @return\n * 0 if successful lookup\n * - EINVAL if the parameters are invalid.\n * - ENOENT if the key is not found.\n */\nint\nrte_hash_lookup_with_hash_data(const struct rte_hash *h, const void *key,\n\t\t\t\t\thash_sig_t sig, void **data);\n\n/**\n * Find a key in the hash table.\n * This operation is multi-thread safe.\n *\n * @param h\n * Hash table to look in.\n * @param key\n * Key to find.\n * @return\n * - -EINVAL if the parameters are invalid.\n * - -ENOENT if the key is not found.\n * - A positive value that can be used by the caller as an offset into an\n * array of user data. This value is unique for this key, and is the same\n * value that was returned when the key was added.\n */\nint32_t\nrte_hash_lookup(const struct rte_hash *h, const void *key);\n\n/**\n * Find a key in the hash table.\n * This operation is multi-thread safe.\n *\n * @param h\n * Hash table to look in.\n * @param key\n * Key to find.\n * @param sig\n * Hash value to remove from the hash table.\n * @return\n * - -EINVAL if the parameters are invalid.\n * - -ENOENT if the key is not found.\n * - A positive value that can be used by the caller as an offset into an\n * array of user data. This value is unique for this key, and is the same\n * value that was returned when the key was added.\n */\nint32_t\nrte_hash_lookup_with_hash(const struct rte_hash *h,\n\t\t\t\tconst void *key, hash_sig_t sig);\n\n/**\n * Calc a hash value by key.\n * This operation is not multi-thread safe.\n *\n * @param h\n * Hash table to look in.\n * @param key\n * Key to find.\n * @return\n * - hash value\n */\nhash_sig_t\nrte_hash_hash(const struct rte_hash *h, const void *key);\n\n#define rte_hash_lookup_multi rte_hash_lookup_bulk\n#define rte_hash_lookup_multi_data rte_hash_lookup_bulk_data\n/**\n * Find multiple keys in the hash table.\n * This operation is multi-thread safe.\n *\n * @param h\n * Hash table to look in.\n * @param keys\n * A pointer to a list of keys to look for.\n * @param num_keys\n * How many keys are in the keys list (less than RTE_HASH_LOOKUP_BULK_MAX).\n * @param hit_mask\n * Output containing a bitmask with all successful lookups.\n * @param data\n * Output containing array of data returned from all the successful lookups.\n * @return\n * -EINVAL if there's an error, otherwise number of successful lookups.\n */\nint\nrte_hash_lookup_bulk_data(const struct rte_hash *h, const void **keys,\n\t\t uint32_t num_keys, uint64_t *hit_mask, void *data[]);\n\n/**\n * Find multiple keys in the hash table.\n * This operation is multi-thread safe.\n *\n * @param h\n * Hash table to look in.\n * @param keys\n * A pointer to a list of keys to look for.\n * @param num_keys\n * How many keys are in the keys list (less than RTE_HASH_LOOKUP_BULK_MAX).\n * @param positions\n * Output containing a list of values, corresponding to the list of keys that\n * can be used by the caller as an offset into an array of user data. These\n * values are unique for each key, and are the same values that were returned\n * when each key was added. If a key in the list was not found, then -ENOENT\n * will be the value.\n * @return\n * -EINVAL if there's an error, otherwise 0.\n */\nint\nrte_hash_lookup_bulk(const struct rte_hash *h, const void **keys,\n\t\t uint32_t num_keys, int32_t *positions);\n\n/**\n * Iterate through the hash table, returning key-value pairs.\n *\n * @param h\n * Hash table to iterate\n * @param key\n * Output containing the key where current iterator\n * was pointing at\n * @param data\n * Output containing the data associated with key.\n * Returns NULL if data was not stored.\n * @param next\n * Pointer to iterator. Should be 0 to start iterating the hash table.\n * Iterator is incremented after each call of this function.\n * @return\n * Position where key was stored, if successful.\n * - -EINVAL if the parameters are invalid.\n * - -ENOENT if end of the hash table.\n */\nint32_t\nrte_hash_iterate(const struct rte_hash *h, const void **key, void **data, uint32_t *next);\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_HASH_H_ */\n" }, { "path": "lib/librte_hash/rte_hash_crc.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_HASH_CRC_H_\n#define _RTE_HASH_CRC_H_\n\n/**\n * @file\n *\n * RTE CRC Hash\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n#include \n#include \n\n/* Lookup tables for software implementation of CRC32C */\nstatic const uint32_t crc32c_tables[8][256] = {{\n 0x00000000, 0xF26B8303, 0xE13B70F7, 0x1350F3F4, 0xC79A971F, 0x35F1141C, 0x26A1E7E8, 0xD4CA64EB,\n 0x8AD958CF, 0x78B2DBCC, 0x6BE22838, 0x9989AB3B, 0x4D43CFD0, 0xBF284CD3, 0xAC78BF27, 0x5E133C24,\n 0x105EC76F, 0xE235446C, 0xF165B798, 0x030E349B, 0xD7C45070, 0x25AFD373, 0x36FF2087, 0xC494A384,\n 0x9A879FA0, 0x68EC1CA3, 0x7BBCEF57, 0x89D76C54, 0x5D1D08BF, 0xAF768BBC, 0xBC267848, 0x4E4DFB4B,\n 0x20BD8EDE, 0xD2D60DDD, 0xC186FE29, 0x33ED7D2A, 0xE72719C1, 0x154C9AC2, 0x061C6936, 0xF477EA35,\n 0xAA64D611, 0x580F5512, 0x4B5FA6E6, 0xB93425E5, 0x6DFE410E, 0x9F95C20D, 0x8CC531F9, 0x7EAEB2FA,\n 0x30E349B1, 0xC288CAB2, 0xD1D83946, 0x23B3BA45, 0xF779DEAE, 0x05125DAD, 0x1642AE59, 0xE4292D5A,\n 0xBA3A117E, 0x4851927D, 0x5B016189, 0xA96AE28A, 0x7DA08661, 0x8FCB0562, 0x9C9BF696, 0x6EF07595,\n 0x417B1DBC, 0xB3109EBF, 0xA0406D4B, 0x522BEE48, 0x86E18AA3, 0x748A09A0, 0x67DAFA54, 0x95B17957,\n 0xCBA24573, 0x39C9C670, 0x2A993584, 0xD8F2B687, 0x0C38D26C, 0xFE53516F, 0xED03A29B, 0x1F682198,\n 0x5125DAD3, 0xA34E59D0, 0xB01EAA24, 0x42752927, 0x96BF4DCC, 0x64D4CECF, 0x77843D3B, 0x85EFBE38,\n 0xDBFC821C, 0x2997011F, 0x3AC7F2EB, 0xC8AC71E8, 0x1C661503, 0xEE0D9600, 0xFD5D65F4, 0x0F36E6F7,\n 0x61C69362, 0x93AD1061, 0x80FDE395, 0x72966096, 0xA65C047D, 0x5437877E, 0x4767748A, 0xB50CF789,\n 0xEB1FCBAD, 0x197448AE, 0x0A24BB5A, 0xF84F3859, 0x2C855CB2, 0xDEEEDFB1, 0xCDBE2C45, 0x3FD5AF46,\n 0x7198540D, 0x83F3D70E, 0x90A324FA, 0x62C8A7F9, 0xB602C312, 0x44694011, 0x5739B3E5, 0xA55230E6,\n 0xFB410CC2, 0x092A8FC1, 0x1A7A7C35, 0xE811FF36, 0x3CDB9BDD, 0xCEB018DE, 0xDDE0EB2A, 0x2F8B6829,\n 0x82F63B78, 0x709DB87B, 0x63CD4B8F, 0x91A6C88C, 0x456CAC67, 0xB7072F64, 0xA457DC90, 0x563C5F93,\n 0x082F63B7, 0xFA44E0B4, 0xE9141340, 0x1B7F9043, 0xCFB5F4A8, 0x3DDE77AB, 0x2E8E845F, 0xDCE5075C,\n 0x92A8FC17, 0x60C37F14, 0x73938CE0, 0x81F80FE3, 0x55326B08, 0xA759E80B, 0xB4091BFF, 0x466298FC,\n 0x1871A4D8, 0xEA1A27DB, 0xF94AD42F, 0x0B21572C, 0xDFEB33C7, 0x2D80B0C4, 0x3ED04330, 0xCCBBC033,\n 0xA24BB5A6, 0x502036A5, 0x4370C551, 0xB11B4652, 0x65D122B9, 0x97BAA1BA, 0x84EA524E, 0x7681D14D,\n 0x2892ED69, 0xDAF96E6A, 0xC9A99D9E, 0x3BC21E9D, 0xEF087A76, 0x1D63F975, 0x0E330A81, 0xFC588982,\n 0xB21572C9, 0x407EF1CA, 0x532E023E, 0xA145813D, 0x758FE5D6, 0x87E466D5, 0x94B49521, 0x66DF1622,\n 0x38CC2A06, 0xCAA7A905, 0xD9F75AF1, 0x2B9CD9F2, 0xFF56BD19, 0x0D3D3E1A, 0x1E6DCDEE, 0xEC064EED,\n 0xC38D26C4, 0x31E6A5C7, 0x22B65633, 0xD0DDD530, 0x0417B1DB, 0xF67C32D8, 0xE52CC12C, 0x1747422F,\n 0x49547E0B, 0xBB3FFD08, 0xA86F0EFC, 0x5A048DFF, 0x8ECEE914, 0x7CA56A17, 0x6FF599E3, 0x9D9E1AE0,\n 0xD3D3E1AB, 0x21B862A8, 0x32E8915C, 0xC083125F, 0x144976B4, 0xE622F5B7, 0xF5720643, 0x07198540,\n 0x590AB964, 0xAB613A67, 0xB831C993, 0x4A5A4A90, 0x9E902E7B, 0x6CFBAD78, 0x7FAB5E8C, 0x8DC0DD8F,\n 0xE330A81A, 0x115B2B19, 0x020BD8ED, 0xF0605BEE, 0x24AA3F05, 0xD6C1BC06, 0xC5914FF2, 0x37FACCF1,\n 0x69E9F0D5, 0x9B8273D6, 0x88D28022, 0x7AB90321, 0xAE7367CA, 0x5C18E4C9, 0x4F48173D, 0xBD23943E,\n 0xF36E6F75, 0x0105EC76, 0x12551F82, 0xE03E9C81, 0x34F4F86A, 0xC69F7B69, 0xD5CF889D, 0x27A40B9E,\n 0x79B737BA, 0x8BDCB4B9, 0x988C474D, 0x6AE7C44E, 0xBE2DA0A5, 0x4C4623A6, 0x5F16D052, 0xAD7D5351\n},\n{\n 0x00000000, 0x13A29877, 0x274530EE, 0x34E7A899, 0x4E8A61DC, 0x5D28F9AB, 0x69CF5132, 0x7A6DC945,\n 0x9D14C3B8, 0x8EB65BCF, 0xBA51F356, 0xA9F36B21, 0xD39EA264, 0xC03C3A13, 0xF4DB928A, 0xE7790AFD,\n 0x3FC5F181, 0x2C6769F6, 0x1880C16F, 0x0B225918, 0x714F905D, 0x62ED082A, 0x560AA0B3, 0x45A838C4,\n 0xA2D13239, 0xB173AA4E, 0x859402D7, 0x96369AA0, 0xEC5B53E5, 0xFFF9CB92, 0xCB1E630B, 0xD8BCFB7C,\n 0x7F8BE302, 0x6C297B75, 0x58CED3EC, 0x4B6C4B9B, 0x310182DE, 0x22A31AA9, 0x1644B230, 0x05E62A47,\n 0xE29F20BA, 0xF13DB8CD, 0xC5DA1054, 0xD6788823, 0xAC154166, 0xBFB7D911, 0x8B507188, 0x98F2E9FF,\n 0x404E1283, 0x53EC8AF4, 0x670B226D, 0x74A9BA1A, 0x0EC4735F, 0x1D66EB28, 0x298143B1, 0x3A23DBC6,\n 0xDD5AD13B, 0xCEF8494C, 0xFA1FE1D5, 0xE9BD79A2, 0x93D0B0E7, 0x80722890, 0xB4958009, 0xA737187E,\n 0xFF17C604, 0xECB55E73, 0xD852F6EA, 0xCBF06E9D, 0xB19DA7D8, 0xA23F3FAF, 0x96D89736, 0x857A0F41,\n 0x620305BC, 0x71A19DCB, 0x45463552, 0x56E4AD25, 0x2C896460, 0x3F2BFC17, 0x0BCC548E, 0x186ECCF9,\n 0xC0D23785, 0xD370AFF2, 0xE797076B, 0xF4359F1C, 0x8E585659, 0x9DFACE2E, 0xA91D66B7, 0xBABFFEC0,\n 0x5DC6F43D, 0x4E646C4A, 0x7A83C4D3, 0x69215CA4, 0x134C95E1, 0x00EE0D96, 0x3409A50F, 0x27AB3D78,\n 0x809C2506, 0x933EBD71, 0xA7D915E8, 0xB47B8D9F, 0xCE1644DA, 0xDDB4DCAD, 0xE9537434, 0xFAF1EC43,\n 0x1D88E6BE, 0x0E2A7EC9, 0x3ACDD650, 0x296F4E27, 0x53028762, 0x40A01F15, 0x7447B78C, 0x67E52FFB,\n 0xBF59D487, 0xACFB4CF0, 0x981CE469, 0x8BBE7C1E, 0xF1D3B55B, 0xE2712D2C, 0xD69685B5, 0xC5341DC2,\n 0x224D173F, 0x31EF8F48, 0x050827D1, 0x16AABFA6, 0x6CC776E3, 0x7F65EE94, 0x4B82460D, 0x5820DE7A,\n 0xFBC3FAF9, 0xE861628E, 0xDC86CA17, 0xCF245260, 0xB5499B25, 0xA6EB0352, 0x920CABCB, 0x81AE33BC,\n 0x66D73941, 0x7575A136, 0x419209AF, 0x523091D8, 0x285D589D, 0x3BFFC0EA, 0x0F186873, 0x1CBAF004,\n 0xC4060B78, 0xD7A4930F, 0xE3433B96, 0xF0E1A3E1, 0x8A8C6AA4, 0x992EF2D3, 0xADC95A4A, 0xBE6BC23D,\n 0x5912C8C0, 0x4AB050B7, 0x7E57F82E, 0x6DF56059, 0x1798A91C, 0x043A316B, 0x30DD99F2, 0x237F0185,\n 0x844819FB, 0x97EA818C, 0xA30D2915, 0xB0AFB162, 0xCAC27827, 0xD960E050, 0xED8748C9, 0xFE25D0BE,\n 0x195CDA43, 0x0AFE4234, 0x3E19EAAD, 0x2DBB72DA, 0x57D6BB9F, 0x447423E8, 0x70938B71, 0x63311306,\n 0xBB8DE87A, 0xA82F700D, 0x9CC8D894, 0x8F6A40E3, 0xF50789A6, 0xE6A511D1, 0xD242B948, 0xC1E0213F,\n 0x26992BC2, 0x353BB3B5, 0x01DC1B2C, 0x127E835B, 0x68134A1E, 0x7BB1D269, 0x4F567AF0, 0x5CF4E287,\n 0x04D43CFD, 0x1776A48A, 0x23910C13, 0x30339464, 0x4A5E5D21, 0x59FCC556, 0x6D1B6DCF, 0x7EB9F5B8,\n 0x99C0FF45, 0x8A626732, 0xBE85CFAB, 0xAD2757DC, 0xD74A9E99, 0xC4E806EE, 0xF00FAE77, 0xE3AD3600,\n 0x3B11CD7C, 0x28B3550B, 0x1C54FD92, 0x0FF665E5, 0x759BACA0, 0x663934D7, 0x52DE9C4E, 0x417C0439,\n 0xA6050EC4, 0xB5A796B3, 0x81403E2A, 0x92E2A65D, 0xE88F6F18, 0xFB2DF76F, 0xCFCA5FF6, 0xDC68C781,\n 0x7B5FDFFF, 0x68FD4788, 0x5C1AEF11, 0x4FB87766, 0x35D5BE23, 0x26772654, 0x12908ECD, 0x013216BA,\n 0xE64B1C47, 0xF5E98430, 0xC10E2CA9, 0xD2ACB4DE, 0xA8C17D9B, 0xBB63E5EC, 0x8F844D75, 0x9C26D502,\n 0x449A2E7E, 0x5738B609, 0x63DF1E90, 0x707D86E7, 0x0A104FA2, 0x19B2D7D5, 0x2D557F4C, 0x3EF7E73B,\n 0xD98EEDC6, 0xCA2C75B1, 0xFECBDD28, 0xED69455F, 0x97048C1A, 0x84A6146D, 0xB041BCF4, 0xA3E32483\n},\n{\n 0x00000000, 0xA541927E, 0x4F6F520D, 0xEA2EC073, 0x9EDEA41A, 0x3B9F3664, 0xD1B1F617, 0x74F06469,\n 0x38513EC5, 0x9D10ACBB, 0x773E6CC8, 0xD27FFEB6, 0xA68F9ADF, 0x03CE08A1, 0xE9E0C8D2, 0x4CA15AAC,\n 0x70A27D8A, 0xD5E3EFF4, 0x3FCD2F87, 0x9A8CBDF9, 0xEE7CD990, 0x4B3D4BEE, 0xA1138B9D, 0x045219E3,\n 0x48F3434F, 0xEDB2D131, 0x079C1142, 0xA2DD833C, 0xD62DE755, 0x736C752B, 0x9942B558, 0x3C032726,\n 0xE144FB14, 0x4405696A, 0xAE2BA919, 0x0B6A3B67, 0x7F9A5F0E, 0xDADBCD70, 0x30F50D03, 0x95B49F7D,\n 0xD915C5D1, 0x7C5457AF, 0x967A97DC, 0x333B05A2, 0x47CB61CB, 0xE28AF3B5, 0x08A433C6, 0xADE5A1B8,\n 0x91E6869E, 0x34A714E0, 0xDE89D493, 0x7BC846ED, 0x0F382284, 0xAA79B0FA, 0x40577089, 0xE516E2F7,\n 0xA9B7B85B, 0x0CF62A25, 0xE6D8EA56, 0x43997828, 0x37691C41, 0x92288E3F, 0x78064E4C, 0xDD47DC32,\n 0xC76580D9, 0x622412A7, 0x880AD2D4, 0x2D4B40AA, 0x59BB24C3, 0xFCFAB6BD, 0x16D476CE, 0xB395E4B0,\n 0xFF34BE1C, 0x5A752C62, 0xB05BEC11, 0x151A7E6F, 0x61EA1A06, 0xC4AB8878, 0x2E85480B, 0x8BC4DA75,\n 0xB7C7FD53, 0x12866F2D, 0xF8A8AF5E, 0x5DE93D20, 0x29195949, 0x8C58CB37, 0x66760B44, 0xC337993A,\n 0x8F96C396, 0x2AD751E8, 0xC0F9919B, 0x65B803E5, 0x1148678C, 0xB409F5F2, 0x5E273581, 0xFB66A7FF,\n 0x26217BCD, 0x8360E9B3, 0x694E29C0, 0xCC0FBBBE, 0xB8FFDFD7, 0x1DBE4DA9, 0xF7908DDA, 0x52D11FA4,\n 0x1E704508, 0xBB31D776, 0x511F1705, 0xF45E857B, 0x80AEE112, 0x25EF736C, 0xCFC1B31F, 0x6A802161,\n 0x56830647, 0xF3C29439, 0x19EC544A, 0xBCADC634, 0xC85DA25D, 0x6D1C3023, 0x8732F050, 0x2273622E,\n 0x6ED23882, 0xCB93AAFC, 0x21BD6A8F, 0x84FCF8F1, 0xF00C9C98, 0x554D0EE6, 0xBF63CE95, 0x1A225CEB,\n 0x8B277743, 0x2E66E53D, 0xC448254E, 0x6109B730, 0x15F9D359, 0xB0B84127, 0x5A968154, 0xFFD7132A,\n 0xB3764986, 0x1637DBF8, 0xFC191B8B, 0x595889F5, 0x2DA8ED9C, 0x88E97FE2, 0x62C7BF91, 0xC7862DEF,\n 0xFB850AC9, 0x5EC498B7, 0xB4EA58C4, 0x11ABCABA, 0x655BAED3, 0xC01A3CAD, 0x2A34FCDE, 0x8F756EA0,\n 0xC3D4340C, 0x6695A672, 0x8CBB6601, 0x29FAF47F, 0x5D0A9016, 0xF84B0268, 0x1265C21B, 0xB7245065,\n 0x6A638C57, 0xCF221E29, 0x250CDE5A, 0x804D4C24, 0xF4BD284D, 0x51FCBA33, 0xBBD27A40, 0x1E93E83E,\n 0x5232B292, 0xF77320EC, 0x1D5DE09F, 0xB81C72E1, 0xCCEC1688, 0x69AD84F6, 0x83834485, 0x26C2D6FB,\n 0x1AC1F1DD, 0xBF8063A3, 0x55AEA3D0, 0xF0EF31AE, 0x841F55C7, 0x215EC7B9, 0xCB7007CA, 0x6E3195B4,\n 0x2290CF18, 0x87D15D66, 0x6DFF9D15, 0xC8BE0F6B, 0xBC4E6B02, 0x190FF97C, 0xF321390F, 0x5660AB71,\n 0x4C42F79A, 0xE90365E4, 0x032DA597, 0xA66C37E9, 0xD29C5380, 0x77DDC1FE, 0x9DF3018D, 0x38B293F3,\n 0x7413C95F, 0xD1525B21, 0x3B7C9B52, 0x9E3D092C, 0xEACD6D45, 0x4F8CFF3B, 0xA5A23F48, 0x00E3AD36,\n 0x3CE08A10, 0x99A1186E, 0x738FD81D, 0xD6CE4A63, 0xA23E2E0A, 0x077FBC74, 0xED517C07, 0x4810EE79,\n 0x04B1B4D5, 0xA1F026AB, 0x4BDEE6D8, 0xEE9F74A6, 0x9A6F10CF, 0x3F2E82B1, 0xD50042C2, 0x7041D0BC,\n 0xAD060C8E, 0x08479EF0, 0xE2695E83, 0x4728CCFD, 0x33D8A894, 0x96993AEA, 0x7CB7FA99, 0xD9F668E7,\n 0x9557324B, 0x3016A035, 0xDA386046, 0x7F79F238, 0x0B899651, 0xAEC8042F, 0x44E6C45C, 0xE1A75622,\n 0xDDA47104, 0x78E5E37A, 0x92CB2309, 0x378AB177, 0x437AD51E, 0xE63B4760, 0x0C158713, 0xA954156D,\n 0xE5F54FC1, 0x40B4DDBF, 0xAA9A1DCC, 0x0FDB8FB2, 0x7B2BEBDB, 0xDE6A79A5, 0x3444B9D6, 0x91052BA8\n},\n{\n 0x00000000, 0xDD45AAB8, 0xBF672381, 0x62228939, 0x7B2231F3, 0xA6679B4B, 0xC4451272, 0x1900B8CA,\n 0xF64463E6, 0x2B01C95E, 0x49234067, 0x9466EADF, 0x8D665215, 0x5023F8AD, 0x32017194, 0xEF44DB2C,\n 0xE964B13D, 0x34211B85, 0x560392BC, 0x8B463804, 0x924680CE, 0x4F032A76, 0x2D21A34F, 0xF06409F7,\n 0x1F20D2DB, 0xC2657863, 0xA047F15A, 0x7D025BE2, 0x6402E328, 0xB9474990, 0xDB65C0A9, 0x06206A11,\n 0xD725148B, 0x0A60BE33, 0x6842370A, 0xB5079DB2, 0xAC072578, 0x71428FC0, 0x136006F9, 0xCE25AC41,\n 0x2161776D, 0xFC24DDD5, 0x9E0654EC, 0x4343FE54, 0x5A43469E, 0x8706EC26, 0xE524651F, 0x3861CFA7,\n 0x3E41A5B6, 0xE3040F0E, 0x81268637, 0x5C632C8F, 0x45639445, 0x98263EFD, 0xFA04B7C4, 0x27411D7C,\n 0xC805C650, 0x15406CE8, 0x7762E5D1, 0xAA274F69, 0xB327F7A3, 0x6E625D1B, 0x0C40D422, 0xD1057E9A,\n 0xABA65FE7, 0x76E3F55F, 0x14C17C66, 0xC984D6DE, 0xD0846E14, 0x0DC1C4AC, 0x6FE34D95, 0xB2A6E72D,\n 0x5DE23C01, 0x80A796B9, 0xE2851F80, 0x3FC0B538, 0x26C00DF2, 0xFB85A74A, 0x99A72E73, 0x44E284CB,\n 0x42C2EEDA, 0x9F874462, 0xFDA5CD5B, 0x20E067E3, 0x39E0DF29, 0xE4A57591, 0x8687FCA8, 0x5BC25610,\n 0xB4868D3C, 0x69C32784, 0x0BE1AEBD, 0xD6A40405, 0xCFA4BCCF, 0x12E11677, 0x70C39F4E, 0xAD8635F6,\n 0x7C834B6C, 0xA1C6E1D4, 0xC3E468ED, 0x1EA1C255, 0x07A17A9F, 0xDAE4D027, 0xB8C6591E, 0x6583F3A6,\n 0x8AC7288A, 0x57828232, 0x35A00B0B, 0xE8E5A1B3, 0xF1E51979, 0x2CA0B3C1, 0x4E823AF8, 0x93C79040,\n 0x95E7FA51, 0x48A250E9, 0x2A80D9D0, 0xF7C57368, 0xEEC5CBA2, 0x3380611A, 0x51A2E823, 0x8CE7429B,\n 0x63A399B7, 0xBEE6330F, 0xDCC4BA36, 0x0181108E, 0x1881A844, 0xC5C402FC, 0xA7E68BC5, 0x7AA3217D,\n 0x52A0C93F, 0x8FE56387, 0xEDC7EABE, 0x30824006, 0x2982F8CC, 0xF4C75274, 0x96E5DB4D, 0x4BA071F5,\n 0xA4E4AAD9, 0x79A10061, 0x1B838958, 0xC6C623E0, 0xDFC69B2A, 0x02833192, 0x60A1B8AB, 0xBDE41213,\n 0xBBC47802, 0x6681D2BA, 0x04A35B83, 0xD9E6F13B, 0xC0E649F1, 0x1DA3E349, 0x7F816A70, 0xA2C4C0C8,\n 0x4D801BE4, 0x90C5B15C, 0xF2E73865, 0x2FA292DD, 0x36A22A17, 0xEBE780AF, 0x89C50996, 0x5480A32E,\n 0x8585DDB4, 0x58C0770C, 0x3AE2FE35, 0xE7A7548D, 0xFEA7EC47, 0x23E246FF, 0x41C0CFC6, 0x9C85657E,\n 0x73C1BE52, 0xAE8414EA, 0xCCA69DD3, 0x11E3376B, 0x08E38FA1, 0xD5A62519, 0xB784AC20, 0x6AC10698,\n 0x6CE16C89, 0xB1A4C631, 0xD3864F08, 0x0EC3E5B0, 0x17C35D7A, 0xCA86F7C2, 0xA8A47EFB, 0x75E1D443,\n 0x9AA50F6F, 0x47E0A5D7, 0x25C22CEE, 0xF8878656, 0xE1873E9C, 0x3CC29424, 0x5EE01D1D, 0x83A5B7A5,\n 0xF90696D8, 0x24433C60, 0x4661B559, 0x9B241FE1, 0x8224A72B, 0x5F610D93, 0x3D4384AA, 0xE0062E12,\n 0x0F42F53E, 0xD2075F86, 0xB025D6BF, 0x6D607C07, 0x7460C4CD, 0xA9256E75, 0xCB07E74C, 0x16424DF4,\n 0x106227E5, 0xCD278D5D, 0xAF050464, 0x7240AEDC, 0x6B401616, 0xB605BCAE, 0xD4273597, 0x09629F2F,\n 0xE6264403, 0x3B63EEBB, 0x59416782, 0x8404CD3A, 0x9D0475F0, 0x4041DF48, 0x22635671, 0xFF26FCC9,\n 0x2E238253, 0xF36628EB, 0x9144A1D2, 0x4C010B6A, 0x5501B3A0, 0x88441918, 0xEA669021, 0x37233A99,\n 0xD867E1B5, 0x05224B0D, 0x6700C234, 0xBA45688C, 0xA345D046, 0x7E007AFE, 0x1C22F3C7, 0xC167597F,\n 0xC747336E, 0x1A0299D6, 0x782010EF, 0xA565BA57, 0xBC65029D, 0x6120A825, 0x0302211C, 0xDE478BA4,\n 0x31035088, 0xEC46FA30, 0x8E647309, 0x5321D9B1, 0x4A21617B, 0x9764CBC3, 0xF54642FA, 0x2803E842\n},\n{\n 0x00000000, 0x38116FAC, 0x7022DF58, 0x4833B0F4, 0xE045BEB0, 0xD854D11C, 0x906761E8, 0xA8760E44,\n 0xC5670B91, 0xFD76643D, 0xB545D4C9, 0x8D54BB65, 0x2522B521, 0x1D33DA8D, 0x55006A79, 0x6D1105D5,\n 0x8F2261D3, 0xB7330E7F, 0xFF00BE8B, 0xC711D127, 0x6F67DF63, 0x5776B0CF, 0x1F45003B, 0x27546F97,\n 0x4A456A42, 0x725405EE, 0x3A67B51A, 0x0276DAB6, 0xAA00D4F2, 0x9211BB5E, 0xDA220BAA, 0xE2336406,\n 0x1BA8B557, 0x23B9DAFB, 0x6B8A6A0F, 0x539B05A3, 0xFBED0BE7, 0xC3FC644B, 0x8BCFD4BF, 0xB3DEBB13,\n 0xDECFBEC6, 0xE6DED16A, 0xAEED619E, 0x96FC0E32, 0x3E8A0076, 0x069B6FDA, 0x4EA8DF2E, 0x76B9B082,\n 0x948AD484, 0xAC9BBB28, 0xE4A80BDC, 0xDCB96470, 0x74CF6A34, 0x4CDE0598, 0x04EDB56C, 0x3CFCDAC0,\n 0x51EDDF15, 0x69FCB0B9, 0x21CF004D, 0x19DE6FE1, 0xB1A861A5, 0x89B90E09, 0xC18ABEFD, 0xF99BD151,\n 0x37516AAE, 0x0F400502, 0x4773B5F6, 0x7F62DA5A, 0xD714D41E, 0xEF05BBB2, 0xA7360B46, 0x9F2764EA,\n 0xF236613F, 0xCA270E93, 0x8214BE67, 0xBA05D1CB, 0x1273DF8F, 0x2A62B023, 0x625100D7, 0x5A406F7B,\n 0xB8730B7D, 0x806264D1, 0xC851D425, 0xF040BB89, 0x5836B5CD, 0x6027DA61, 0x28146A95, 0x10050539,\n 0x7D1400EC, 0x45056F40, 0x0D36DFB4, 0x3527B018, 0x9D51BE5C, 0xA540D1F0, 0xED736104, 0xD5620EA8,\n 0x2CF9DFF9, 0x14E8B055, 0x5CDB00A1, 0x64CA6F0D, 0xCCBC6149, 0xF4AD0EE5, 0xBC9EBE11, 0x848FD1BD,\n 0xE99ED468, 0xD18FBBC4, 0x99BC0B30, 0xA1AD649C, 0x09DB6AD8, 0x31CA0574, 0x79F9B580, 0x41E8DA2C,\n 0xA3DBBE2A, 0x9BCAD186, 0xD3F96172, 0xEBE80EDE, 0x439E009A, 0x7B8F6F36, 0x33BCDFC2, 0x0BADB06E,\n 0x66BCB5BB, 0x5EADDA17, 0x169E6AE3, 0x2E8F054F, 0x86F90B0B, 0xBEE864A7, 0xF6DBD453, 0xCECABBFF,\n 0x6EA2D55C, 0x56B3BAF0, 0x1E800A04, 0x269165A8, 0x8EE76BEC, 0xB6F60440, 0xFEC5B4B4, 0xC6D4DB18,\n 0xABC5DECD, 0x93D4B161, 0xDBE70195, 0xE3F66E39, 0x4B80607D, 0x73910FD1, 0x3BA2BF25, 0x03B3D089,\n 0xE180B48F, 0xD991DB23, 0x91A26BD7, 0xA9B3047B, 0x01C50A3F, 0x39D46593, 0x71E7D567, 0x49F6BACB,\n 0x24E7BF1E, 0x1CF6D0B2, 0x54C56046, 0x6CD40FEA, 0xC4A201AE, 0xFCB36E02, 0xB480DEF6, 0x8C91B15A,\n 0x750A600B, 0x4D1B0FA7, 0x0528BF53, 0x3D39D0FF, 0x954FDEBB, 0xAD5EB117, 0xE56D01E3, 0xDD7C6E4F,\n 0xB06D6B9A, 0x887C0436, 0xC04FB4C2, 0xF85EDB6E, 0x5028D52A, 0x6839BA86, 0x200A0A72, 0x181B65DE,\n 0xFA2801D8, 0xC2396E74, 0x8A0ADE80, 0xB21BB12C, 0x1A6DBF68, 0x227CD0C4, 0x6A4F6030, 0x525E0F9C,\n 0x3F4F0A49, 0x075E65E5, 0x4F6DD511, 0x777CBABD, 0xDF0AB4F9, 0xE71BDB55, 0xAF286BA1, 0x9739040D,\n 0x59F3BFF2, 0x61E2D05E, 0x29D160AA, 0x11C00F06, 0xB9B60142, 0x81A76EEE, 0xC994DE1A, 0xF185B1B6,\n 0x9C94B463, 0xA485DBCF, 0xECB66B3B, 0xD4A70497, 0x7CD10AD3, 0x44C0657F, 0x0CF3D58B, 0x34E2BA27,\n 0xD6D1DE21, 0xEEC0B18D, 0xA6F30179, 0x9EE26ED5, 0x36946091, 0x0E850F3D, 0x46B6BFC9, 0x7EA7D065,\n 0x13B6D5B0, 0x2BA7BA1C, 0x63940AE8, 0x5B856544, 0xF3F36B00, 0xCBE204AC, 0x83D1B458, 0xBBC0DBF4,\n 0x425B0AA5, 0x7A4A6509, 0x3279D5FD, 0x0A68BA51, 0xA21EB415, 0x9A0FDBB9, 0xD23C6B4D, 0xEA2D04E1,\n 0x873C0134, 0xBF2D6E98, 0xF71EDE6C, 0xCF0FB1C0, 0x6779BF84, 0x5F68D028, 0x175B60DC, 0x2F4A0F70,\n 0xCD796B76, 0xF56804DA, 0xBD5BB42E, 0x854ADB82, 0x2D3CD5C6, 0x152DBA6A, 0x5D1E0A9E, 0x650F6532,\n 0x081E60E7, 0x300F0F4B, 0x783CBFBF, 0x402DD013, 0xE85BDE57, 0xD04AB1FB, 0x9879010F, 0xA0686EA3\n},\n{\n 0x00000000, 0xEF306B19, 0xDB8CA0C3, 0x34BCCBDA, 0xB2F53777, 0x5DC55C6E, 0x697997B4, 0x8649FCAD,\n 0x6006181F, 0x8F367306, 0xBB8AB8DC, 0x54BAD3C5, 0xD2F32F68, 0x3DC34471, 0x097F8FAB, 0xE64FE4B2,\n 0xC00C303E, 0x2F3C5B27, 0x1B8090FD, 0xF4B0FBE4, 0x72F90749, 0x9DC96C50, 0xA975A78A, 0x4645CC93,\n 0xA00A2821, 0x4F3A4338, 0x7B8688E2, 0x94B6E3FB, 0x12FF1F56, 0xFDCF744F, 0xC973BF95, 0x2643D48C,\n 0x85F4168D, 0x6AC47D94, 0x5E78B64E, 0xB148DD57, 0x370121FA, 0xD8314AE3, 0xEC8D8139, 0x03BDEA20,\n 0xE5F20E92, 0x0AC2658B, 0x3E7EAE51, 0xD14EC548, 0x570739E5, 0xB83752FC, 0x8C8B9926, 0x63BBF23F,\n 0x45F826B3, 0xAAC84DAA, 0x9E748670, 0x7144ED69, 0xF70D11C4, 0x183D7ADD, 0x2C81B107, 0xC3B1DA1E,\n 0x25FE3EAC, 0xCACE55B5, 0xFE729E6F, 0x1142F576, 0x970B09DB, 0x783B62C2, 0x4C87A918, 0xA3B7C201,\n 0x0E045BEB, 0xE13430F2, 0xD588FB28, 0x3AB89031, 0xBCF16C9C, 0x53C10785, 0x677DCC5F, 0x884DA746,\n 0x6E0243F4, 0x813228ED, 0xB58EE337, 0x5ABE882E, 0xDCF77483, 0x33C71F9A, 0x077BD440, 0xE84BBF59,\n 0xCE086BD5, 0x213800CC, 0x1584CB16, 0xFAB4A00F, 0x7CFD5CA2, 0x93CD37BB, 0xA771FC61, 0x48419778,\n 0xAE0E73CA, 0x413E18D3, 0x7582D309, 0x9AB2B810, 0x1CFB44BD, 0xF3CB2FA4, 0xC777E47E, 0x28478F67,\n 0x8BF04D66, 0x64C0267F, 0x507CEDA5, 0xBF4C86BC, 0x39057A11, 0xD6351108, 0xE289DAD2, 0x0DB9B1CB,\n 0xEBF65579, 0x04C63E60, 0x307AF5BA, 0xDF4A9EA3, 0x5903620E, 0xB6330917, 0x828FC2CD, 0x6DBFA9D4,\n 0x4BFC7D58, 0xA4CC1641, 0x9070DD9B, 0x7F40B682, 0xF9094A2F, 0x16392136, 0x2285EAEC, 0xCDB581F5,\n 0x2BFA6547, 0xC4CA0E5E, 0xF076C584, 0x1F46AE9D, 0x990F5230, 0x763F3929, 0x4283F2F3, 0xADB399EA,\n 0x1C08B7D6, 0xF338DCCF, 0xC7841715, 0x28B47C0C, 0xAEFD80A1, 0x41CDEBB8, 0x75712062, 0x9A414B7B,\n 0x7C0EAFC9, 0x933EC4D0, 0xA7820F0A, 0x48B26413, 0xCEFB98BE, 0x21CBF3A7, 0x1577387D, 0xFA475364,\n 0xDC0487E8, 0x3334ECF1, 0x0788272B, 0xE8B84C32, 0x6EF1B09F, 0x81C1DB86, 0xB57D105C, 0x5A4D7B45,\n 0xBC029FF7, 0x5332F4EE, 0x678E3F34, 0x88BE542D, 0x0EF7A880, 0xE1C7C399, 0xD57B0843, 0x3A4B635A,\n 0x99FCA15B, 0x76CCCA42, 0x42700198, 0xAD406A81, 0x2B09962C, 0xC439FD35, 0xF08536EF, 0x1FB55DF6,\n 0xF9FAB944, 0x16CAD25D, 0x22761987, 0xCD46729E, 0x4B0F8E33, 0xA43FE52A, 0x90832EF0, 0x7FB345E9,\n 0x59F09165, 0xB6C0FA7C, 0x827C31A6, 0x6D4C5ABF, 0xEB05A612, 0x0435CD0B, 0x308906D1, 0xDFB96DC8,\n 0x39F6897A, 0xD6C6E263, 0xE27A29B9, 0x0D4A42A0, 0x8B03BE0D, 0x6433D514, 0x508F1ECE, 0xBFBF75D7,\n 0x120CEC3D, 0xFD3C8724, 0xC9804CFE, 0x26B027E7, 0xA0F9DB4A, 0x4FC9B053, 0x7B757B89, 0x94451090,\n 0x720AF422, 0x9D3A9F3B, 0xA98654E1, 0x46B63FF8, 0xC0FFC355, 0x2FCFA84C, 0x1B736396, 0xF443088F,\n 0xD200DC03, 0x3D30B71A, 0x098C7CC0, 0xE6BC17D9, 0x60F5EB74, 0x8FC5806D, 0xBB794BB7, 0x544920AE,\n 0xB206C41C, 0x5D36AF05, 0x698A64DF, 0x86BA0FC6, 0x00F3F36B, 0xEFC39872, 0xDB7F53A8, 0x344F38B1,\n 0x97F8FAB0, 0x78C891A9, 0x4C745A73, 0xA344316A, 0x250DCDC7, 0xCA3DA6DE, 0xFE816D04, 0x11B1061D,\n 0xF7FEE2AF, 0x18CE89B6, 0x2C72426C, 0xC3422975, 0x450BD5D8, 0xAA3BBEC1, 0x9E87751B, 0x71B71E02,\n 0x57F4CA8E, 0xB8C4A197, 0x8C786A4D, 0x63480154, 0xE501FDF9, 0x0A3196E0, 0x3E8D5D3A, 0xD1BD3623,\n 0x37F2D291, 0xD8C2B988, 0xEC7E7252, 0x034E194B, 0x8507E5E6, 0x6A378EFF, 0x5E8B4525, 0xB1BB2E3C\n},\n{\n 0x00000000, 0x68032CC8, 0xD0065990, 0xB8057558, 0xA5E0C5D1, 0xCDE3E919, 0x75E69C41, 0x1DE5B089,\n 0x4E2DFD53, 0x262ED19B, 0x9E2BA4C3, 0xF628880B, 0xEBCD3882, 0x83CE144A, 0x3BCB6112, 0x53C84DDA,\n 0x9C5BFAA6, 0xF458D66E, 0x4C5DA336, 0x245E8FFE, 0x39BB3F77, 0x51B813BF, 0xE9BD66E7, 0x81BE4A2F,\n 0xD27607F5, 0xBA752B3D, 0x02705E65, 0x6A7372AD, 0x7796C224, 0x1F95EEEC, 0xA7909BB4, 0xCF93B77C,\n 0x3D5B83BD, 0x5558AF75, 0xED5DDA2D, 0x855EF6E5, 0x98BB466C, 0xF0B86AA4, 0x48BD1FFC, 0x20BE3334,\n 0x73767EEE, 0x1B755226, 0xA370277E, 0xCB730BB6, 0xD696BB3F, 0xBE9597F7, 0x0690E2AF, 0x6E93CE67,\n 0xA100791B, 0xC90355D3, 0x7106208B, 0x19050C43, 0x04E0BCCA, 0x6CE39002, 0xD4E6E55A, 0xBCE5C992,\n 0xEF2D8448, 0x872EA880, 0x3F2BDDD8, 0x5728F110, 0x4ACD4199, 0x22CE6D51, 0x9ACB1809, 0xF2C834C1,\n 0x7AB7077A, 0x12B42BB2, 0xAAB15EEA, 0xC2B27222, 0xDF57C2AB, 0xB754EE63, 0x0F519B3B, 0x6752B7F3,\n 0x349AFA29, 0x5C99D6E1, 0xE49CA3B9, 0x8C9F8F71, 0x917A3FF8, 0xF9791330, 0x417C6668, 0x297F4AA0,\n 0xE6ECFDDC, 0x8EEFD114, 0x36EAA44C, 0x5EE98884, 0x430C380D, 0x2B0F14C5, 0x930A619D, 0xFB094D55,\n 0xA8C1008F, 0xC0C22C47, 0x78C7591F, 0x10C475D7, 0x0D21C55E, 0x6522E996, 0xDD279CCE, 0xB524B006,\n 0x47EC84C7, 0x2FEFA80F, 0x97EADD57, 0xFFE9F19F, 0xE20C4116, 0x8A0F6DDE, 0x320A1886, 0x5A09344E,\n 0x09C17994, 0x61C2555C, 0xD9C72004, 0xB1C40CCC, 0xAC21BC45, 0xC422908D, 0x7C27E5D5, 0x1424C91D,\n 0xDBB77E61, 0xB3B452A9, 0x0BB127F1, 0x63B20B39, 0x7E57BBB0, 0x16549778, 0xAE51E220, 0xC652CEE8,\n 0x959A8332, 0xFD99AFFA, 0x459CDAA2, 0x2D9FF66A, 0x307A46E3, 0x58796A2B, 0xE07C1F73, 0x887F33BB,\n 0xF56E0EF4, 0x9D6D223C, 0x25685764, 0x4D6B7BAC, 0x508ECB25, 0x388DE7ED, 0x808892B5, 0xE88BBE7D,\n 0xBB43F3A7, 0xD340DF6F, 0x6B45AA37, 0x034686FF, 0x1EA33676, 0x76A01ABE, 0xCEA56FE6, 0xA6A6432E,\n 0x6935F452, 0x0136D89A, 0xB933ADC2, 0xD130810A, 0xCCD53183, 0xA4D61D4B, 0x1CD36813, 0x74D044DB,\n 0x27180901, 0x4F1B25C9, 0xF71E5091, 0x9F1D7C59, 0x82F8CCD0, 0xEAFBE018, 0x52FE9540, 0x3AFDB988,\n 0xC8358D49, 0xA036A181, 0x1833D4D9, 0x7030F811, 0x6DD54898, 0x05D66450, 0xBDD31108, 0xD5D03DC0,\n 0x8618701A, 0xEE1B5CD2, 0x561E298A, 0x3E1D0542, 0x23F8B5CB, 0x4BFB9903, 0xF3FEEC5B, 0x9BFDC093,\n 0x546E77EF, 0x3C6D5B27, 0x84682E7F, 0xEC6B02B7, 0xF18EB23E, 0x998D9EF6, 0x2188EBAE, 0x498BC766,\n 0x1A438ABC, 0x7240A674, 0xCA45D32C, 0xA246FFE4, 0xBFA34F6D, 0xD7A063A5, 0x6FA516FD, 0x07A63A35,\n 0x8FD9098E, 0xE7DA2546, 0x5FDF501E, 0x37DC7CD6, 0x2A39CC5F, 0x423AE097, 0xFA3F95CF, 0x923CB907,\n 0xC1F4F4DD, 0xA9F7D815, 0x11F2AD4D, 0x79F18185, 0x6414310C, 0x0C171DC4, 0xB412689C, 0xDC114454,\n 0x1382F328, 0x7B81DFE0, 0xC384AAB8, 0xAB878670, 0xB66236F9, 0xDE611A31, 0x66646F69, 0x0E6743A1,\n 0x5DAF0E7B, 0x35AC22B3, 0x8DA957EB, 0xE5AA7B23, 0xF84FCBAA, 0x904CE762, 0x2849923A, 0x404ABEF2,\n 0xB2828A33, 0xDA81A6FB, 0x6284D3A3, 0x0A87FF6B, 0x17624FE2, 0x7F61632A, 0xC7641672, 0xAF673ABA,\n 0xFCAF7760, 0x94AC5BA8, 0x2CA92EF0, 0x44AA0238, 0x594FB2B1, 0x314C9E79, 0x8949EB21, 0xE14AC7E9,\n 0x2ED97095, 0x46DA5C5D, 0xFEDF2905, 0x96DC05CD, 0x8B39B544, 0xE33A998C, 0x5B3FECD4, 0x333CC01C,\n 0x60F48DC6, 0x08F7A10E, 0xB0F2D456, 0xD8F1F89E, 0xC5144817, 0xAD1764DF, 0x15121187, 0x7D113D4F\n},\n{\n 0x00000000, 0x493C7D27, 0x9278FA4E, 0xDB448769, 0x211D826D, 0x6821FF4A, 0xB3657823, 0xFA590504,\n 0x423B04DA, 0x0B0779FD, 0xD043FE94, 0x997F83B3, 0x632686B7, 0x2A1AFB90, 0xF15E7CF9, 0xB86201DE,\n 0x847609B4, 0xCD4A7493, 0x160EF3FA, 0x5F328EDD, 0xA56B8BD9, 0xEC57F6FE, 0x37137197, 0x7E2F0CB0,\n 0xC64D0D6E, 0x8F717049, 0x5435F720, 0x1D098A07, 0xE7508F03, 0xAE6CF224, 0x7528754D, 0x3C14086A,\n 0x0D006599, 0x443C18BE, 0x9F789FD7, 0xD644E2F0, 0x2C1DE7F4, 0x65219AD3, 0xBE651DBA, 0xF759609D,\n 0x4F3B6143, 0x06071C64, 0xDD439B0D, 0x947FE62A, 0x6E26E32E, 0x271A9E09, 0xFC5E1960, 0xB5626447,\n 0x89766C2D, 0xC04A110A, 0x1B0E9663, 0x5232EB44, 0xA86BEE40, 0xE1579367, 0x3A13140E, 0x732F6929,\n 0xCB4D68F7, 0x827115D0, 0x593592B9, 0x1009EF9E, 0xEA50EA9A, 0xA36C97BD, 0x782810D4, 0x31146DF3,\n 0x1A00CB32, 0x533CB615, 0x8878317C, 0xC1444C5B, 0x3B1D495F, 0x72213478, 0xA965B311, 0xE059CE36,\n 0x583BCFE8, 0x1107B2CF, 0xCA4335A6, 0x837F4881, 0x79264D85, 0x301A30A2, 0xEB5EB7CB, 0xA262CAEC,\n 0x9E76C286, 0xD74ABFA1, 0x0C0E38C8, 0x453245EF, 0xBF6B40EB, 0xF6573DCC, 0x2D13BAA5, 0x642FC782,\n 0xDC4DC65C, 0x9571BB7B, 0x4E353C12, 0x07094135, 0xFD504431, 0xB46C3916, 0x6F28BE7F, 0x2614C358,\n 0x1700AEAB, 0x5E3CD38C, 0x857854E5, 0xCC4429C2, 0x361D2CC6, 0x7F2151E1, 0xA465D688, 0xED59ABAF,\n 0x553BAA71, 0x1C07D756, 0xC743503F, 0x8E7F2D18, 0x7426281C, 0x3D1A553B, 0xE65ED252, 0xAF62AF75,\n 0x9376A71F, 0xDA4ADA38, 0x010E5D51, 0x48322076, 0xB26B2572, 0xFB575855, 0x2013DF3C, 0x692FA21B,\n 0xD14DA3C5, 0x9871DEE2, 0x4335598B, 0x0A0924AC, 0xF05021A8, 0xB96C5C8F, 0x6228DBE6, 0x2B14A6C1,\n 0x34019664, 0x7D3DEB43, 0xA6796C2A, 0xEF45110D, 0x151C1409, 0x5C20692E, 0x8764EE47, 0xCE589360,\n 0x763A92BE, 0x3F06EF99, 0xE44268F0, 0xAD7E15D7, 0x572710D3, 0x1E1B6DF4, 0xC55FEA9D, 0x8C6397BA,\n 0xB0779FD0, 0xF94BE2F7, 0x220F659E, 0x6B3318B9, 0x916A1DBD, 0xD856609A, 0x0312E7F3, 0x4A2E9AD4,\n 0xF24C9B0A, 0xBB70E62D, 0x60346144, 0x29081C63, 0xD3511967, 0x9A6D6440, 0x4129E329, 0x08159E0E,\n 0x3901F3FD, 0x703D8EDA, 0xAB7909B3, 0xE2457494, 0x181C7190, 0x51200CB7, 0x8A648BDE, 0xC358F6F9,\n 0x7B3AF727, 0x32068A00, 0xE9420D69, 0xA07E704E, 0x5A27754A, 0x131B086D, 0xC85F8F04, 0x8163F223,\n 0xBD77FA49, 0xF44B876E, 0x2F0F0007, 0x66337D20, 0x9C6A7824, 0xD5560503, 0x0E12826A, 0x472EFF4D,\n 0xFF4CFE93, 0xB67083B4, 0x6D3404DD, 0x240879FA, 0xDE517CFE, 0x976D01D9, 0x4C2986B0, 0x0515FB97,\n 0x2E015D56, 0x673D2071, 0xBC79A718, 0xF545DA3F, 0x0F1CDF3B, 0x4620A21C, 0x9D642575, 0xD4585852,\n 0x6C3A598C, 0x250624AB, 0xFE42A3C2, 0xB77EDEE5, 0x4D27DBE1, 0x041BA6C6, 0xDF5F21AF, 0x96635C88,\n 0xAA7754E2, 0xE34B29C5, 0x380FAEAC, 0x7133D38B, 0x8B6AD68F, 0xC256ABA8, 0x19122CC1, 0x502E51E6,\n 0xE84C5038, 0xA1702D1F, 0x7A34AA76, 0x3308D751, 0xC951D255, 0x806DAF72, 0x5B29281B, 0x1215553C,\n 0x230138CF, 0x6A3D45E8, 0xB179C281, 0xF845BFA6, 0x021CBAA2, 0x4B20C785, 0x906440EC, 0xD9583DCB,\n 0x613A3C15, 0x28064132, 0xF342C65B, 0xBA7EBB7C, 0x4027BE78, 0x091BC35F, 0xD25F4436, 0x9B633911,\n 0xA777317B, 0xEE4B4C5C, 0x350FCB35, 0x7C33B612, 0x866AB316, 0xCF56CE31, 0x14124958, 0x5D2E347F,\n 0xE54C35A1, 0xAC704886, 0x7734CFEF, 0x3E08B2C8, 0xC451B7CC, 0x8D6DCAEB, 0x56294D82, 0x1F1530A5\n}};\n\n#define CRC32_UPD(crc, n) \\\n\t(crc32c_tables[(n)][(crc) & 0xFF] ^ \\\n\t crc32c_tables[(n)-1][((crc) >> 8) & 0xFF])\n\nstatic inline uint32_t\ncrc32c_1word(uint32_t data, uint32_t init_val)\n{\n\tuint32_t crc, term1, term2;\n\tcrc = init_val;\n\tcrc ^= data;\n\n\tterm1 = CRC32_UPD(crc, 3);\n\tterm2 = crc >> 16;\n\tcrc = term1 ^ CRC32_UPD(term2, 1);\n\n\treturn crc;\n}\n\nstatic inline uint32_t\ncrc32c_2words(uint64_t data, uint32_t init_val)\n{\n\tunion {\n\t\tuint64_t u64;\n\t\tuint32_t u32[2];\n\t} d;\n\td.u64 = data;\n\n\tuint32_t crc, term1, term2;\n\n\tcrc = init_val;\n\tcrc ^= d.u32[0];\n\n\tterm1 = CRC32_UPD(crc, 7);\n\tterm2 = crc >> 16;\n\tcrc = term1 ^ CRC32_UPD(term2, 5);\n\tterm1 = CRC32_UPD(d.u32[1], 3);\n\tterm2 = d.u32[1] >> 16;\n\tcrc ^= term1 ^ CRC32_UPD(term2, 1);\n\n\treturn crc;\n}\n\n#if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64)\nstatic inline uint32_t\ncrc32c_sse42_u32(uint32_t data, uint32_t init_val)\n{\n\t__asm__ volatile(\n\t\t\t\"crc32l %[data], %[init_val];\"\n\t\t\t: [init_val] \"+r\" (init_val)\n\t\t\t: [data] \"rm\" (data));\n\treturn init_val;\n}\n\nstatic inline uint32_t\ncrc32c_sse42_u64_mimic(uint64_t data, uint64_t init_val)\n{\n\tunion {\n\t\tuint32_t u32[2];\n\t\tuint64_t u64;\n\t} d;\n\n\td.u64 = data;\n\tinit_val = crc32c_sse42_u32(d.u32[0], init_val);\n\tinit_val = crc32c_sse42_u32(d.u32[1], init_val);\n\treturn init_val;\n}\n#endif\n\n#ifdef RTE_ARCH_X86_64\nstatic inline uint32_t\ncrc32c_sse42_u64(uint64_t data, uint64_t init_val)\n{\n\t__asm__ volatile(\n\t\t\t\"crc32q %[data], %[init_val];\"\n\t\t\t: [init_val] \"+r\" (init_val)\n\t\t\t: [data] \"rm\" (data));\n\treturn init_val;\n}\n#endif\n\n#define CRC32_SW (1U << 0)\n#define CRC32_SSE42 (1U << 1)\n#define CRC32_x64 (1U << 2)\n#define CRC32_SSE42_x64 (CRC32_x64|CRC32_SSE42)\n\nstatic uint8_t crc32_alg = CRC32_SW;\n\n/**\n * Allow or disallow use of SSE4.2 instrinsics for CRC32 hash\n * calculation.\n *\n * @param alg\n * An OR of following flags:\n * - (CRC32_SW) Don't use SSE4.2 intrinsics\n * - (CRC32_SSE42) Use SSE4.2 intrinsics if available\n * - (CRC32_SSE42_x64) Use 64-bit SSE4.2 intrinsic if available (default)\n *\n */\nstatic inline void\nrte_hash_crc_set_alg(uint8_t alg)\n{\n\tswitch (alg) {\n#if defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_64)\n\tcase CRC32_SSE42_x64:\n\t\tif (! rte_cpu_get_flag_enabled(RTE_CPUFLAG_EM64T))\n\t\t\talg = CRC32_SSE42;\n\tcase CRC32_SSE42:\n\t\tif (! rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_2))\n\t\t\talg = CRC32_SW;\n#endif\n\tcase CRC32_SW:\n\t\tcrc32_alg = alg;\n\tdefault:\n\t\tbreak;\n\t}\n}\n\n/* Setting the best available algorithm */\nstatic inline void __attribute__((constructor))\nrte_hash_crc_init_alg(void)\n{\n\trte_hash_crc_set_alg(CRC32_SSE42_x64);\n}\n\n/**\n * Use single crc32 instruction to perform a hash on a 4 byte value.\n * Fall back to software crc32 implementation in case SSE4.2 is\n * not supported\n *\n * @param data\n * Data to perform hash on.\n * @param init_val\n * Value to initialise hash generator.\n * @return\n * 32bit calculated hash value.\n */\nstatic inline uint32_t\nrte_hash_crc_4byte(uint32_t data, uint32_t init_val)\n{\n#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64\n\tif (likely(crc32_alg & CRC32_SSE42))\n\t\treturn crc32c_sse42_u32(data, init_val);\n#endif\n\n\treturn crc32c_1word(data, init_val);\n}\n\n/**\n * Use single crc32 instruction to perform a hash on a 8 byte value.\n * Fall back to software crc32 implementation in case SSE4.2 is\n * not supported\n *\n * @param data\n * Data to perform hash on.\n * @param init_val\n * Value to initialise hash generator.\n * @return\n * 32bit calculated hash value.\n */\nstatic inline uint32_t\nrte_hash_crc_8byte(uint64_t data, uint32_t init_val)\n{\n#ifdef RTE_ARCH_X86_64\n\tif (likely(crc32_alg == CRC32_SSE42_x64))\n\t\treturn crc32c_sse42_u64(data, init_val);\n#endif\n\n#if defined RTE_ARCH_I686 || defined RTE_ARCH_X86_64\n\tif (likely(crc32_alg & CRC32_SSE42))\n\t\treturn crc32c_sse42_u64_mimic(data, init_val);\n#endif\n\n\treturn crc32c_2words(data, init_val);\n}\n\n/**\n * Calculate CRC32 hash on user-supplied byte array.\n *\n * @param data\n * Data to perform hash on.\n * @param data_len\n * How many bytes to use to calculate hash value.\n * @param init_val\n * Value to initialise hash generator.\n * @return\n * 32bit calculated hash value.\n */\nstatic inline uint32_t\nrte_hash_crc(const void *data, uint32_t data_len, uint32_t init_val)\n{\n\tunsigned i;\n\tuint64_t temp = 0;\n\tuintptr_t pd = (uintptr_t) data;\n\n\tfor (i = 0; i < data_len / 8; i++) {\n\t\tinit_val = rte_hash_crc_8byte(*(const uint64_t *)pd, init_val);\n\t\tpd += 8;\n\t}\n\n\tswitch (7 - (data_len & 0x07)) {\n\tcase 0:\n\t\ttemp |= (uint64_t) *((const uint8_t *)pd + 6) << 48;\n\t\t/* Fallthrough */\n\tcase 1:\n\t\ttemp |= (uint64_t) *((const uint8_t *)pd + 5) << 40;\n\t\t/* Fallthrough */\n\tcase 2:\n\t\ttemp |= (uint64_t) *((const uint8_t *)pd + 4) << 32;\n\t\ttemp |= *(const uint32_t *)pd;\n\t\tinit_val = rte_hash_crc_8byte(temp, init_val);\n\t\tbreak;\n\tcase 3:\n\t\tinit_val = rte_hash_crc_4byte(*(const uint32_t *)pd, init_val);\n\t\tbreak;\n\tcase 4:\n\t\ttemp |= *((const uint8_t *)pd + 2) << 16;\n\t\t/* Fallthrough */\n\tcase 5:\n\t\ttemp |= *((const uint8_t *)pd + 1) << 8;\n\t\t/* Fallthrough */\n\tcase 6:\n\t\ttemp |= *(const uint8_t *)pd;\n\t\tinit_val = rte_hash_crc_4byte(temp, init_val);\n\t\t/* Fallthrough */\n\tdefault:\n\t\tbreak;\n\t}\n\n\treturn init_val;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_HASH_CRC_H_ */\n" }, { "path": "lib/librte_hash/rte_jhash.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_JHASH_H\n#define _RTE_JHASH_H\n\n/**\n * @file\n *\n * jhash functions.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n#include \n\n#include \n#include \n\n/* jhash.h: Jenkins hash support.\n *\n * Copyright (C) 2006 Bob Jenkins (bob_jenkins@burtleburtle.net)\n *\n * http://burtleburtle.net/bob/hash/\n *\n * These are the credits from Bob's sources:\n *\n * lookup3.c, by Bob Jenkins, May 2006, Public Domain.\n *\n * These are functions for producing 32-bit hashes for hash table lookup.\n * hashword(), hashlittle(), hashlittle2(), hashbig(), mix(), and final()\n * are externally useful functions. Routines to test the hash are included\n * if SELF_TEST is defined. You can use this free for any purpose. It's in\n * the public domain. It has no warranty.\n *\n * $FreeBSD$\n */\n\n#define rot(x, k) (((x) << (k)) | ((x) >> (32-(k))))\n\n/** @internal Internal function. NOTE: Arguments are modified. */\n#define __rte_jhash_mix(a, b, c) do { \\\n\ta -= c; a ^= rot(c, 4); c += b; \\\n\tb -= a; b ^= rot(a, 6); a += c; \\\n\tc -= b; c ^= rot(b, 8); b += a; \\\n\ta -= c; a ^= rot(c, 16); c += b; \\\n\tb -= a; b ^= rot(a, 19); a += c; \\\n\tc -= b; c ^= rot(b, 4); b += a; \\\n} while (0)\n\n#define __rte_jhash_final(a, b, c) do { \\\n\tc ^= b; c -= rot(b, 14); \\\n\ta ^= c; a -= rot(c, 11); \\\n\tb ^= a; b -= rot(a, 25); \\\n\tc ^= b; c -= rot(b, 16); \\\n\ta ^= c; a -= rot(c, 4); \\\n\tb ^= a; b -= rot(a, 14); \\\n\tc ^= b; c -= rot(b, 24); \\\n} while (0)\n\n/** The golden ratio: an arbitrary value. */\n#define RTE_JHASH_GOLDEN_RATIO 0xdeadbeef\n\n#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n#define BIT_SHIFT(x, y, k) (((x) >> (k)) | ((uint64_t)(y) << (32-(k))))\n#else\n#define BIT_SHIFT(x, y, k) (((uint64_t)(x) << (k)) | ((y) >> (32-(k))))\n#endif\n\n#define LOWER8b_MASK rte_le_to_cpu_32(0xff)\n#define LOWER16b_MASK rte_le_to_cpu_32(0xffff)\n#define LOWER24b_MASK rte_le_to_cpu_32(0xffffff)\n\nstatic inline void\n__rte_jhash_2hashes(const void *key, uint32_t length, uint32_t *pc,\n\t\tuint32_t *pb, unsigned check_align)\n{\n\tuint32_t a, b, c;\n\n\t/* Set up the internal state */\n\ta = b = c = RTE_JHASH_GOLDEN_RATIO + ((uint32_t)length) + *pc;\n\tc += *pb;\n\n\t/*\n\t * Check key alignment. For x86 architecture, first case is always optimal\n\t * If check_align is not set, first case will be used\n\t */\n#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) || defined(RTE_ARCH_X86_X32)\n\tconst uint32_t *k = key;\n\tconst uint32_t s = 0;\n#else\n\tconst uint32_t *k = (uint32_t *)((uintptr_t)key & (uintptr_t)~3);\n\tconst uint32_t s = ((uintptr_t)key & 3) * CHAR_BIT;\n#endif\n\tif (!check_align || s == 0) {\n\t\twhile (length > 12) {\n\t\t\ta += k[0];\n\t\t\tb += k[1];\n\t\t\tc += k[2];\n\n\t\t\t__rte_jhash_mix(a, b, c);\n\n\t\t\tk += 3;\n\t\t\tlength -= 12;\n\t\t}\n\n\t\tswitch (length) {\n\t\tcase 12:\n\t\t\tc += k[2]; b += k[1]; a += k[0]; break;\n\t\tcase 11:\n\t\t\tc += k[2] & LOWER24b_MASK; b += k[1]; a += k[0]; break;\n\t\tcase 10:\n\t\t\tc += k[2] & LOWER16b_MASK; b += k[1]; a += k[0]; break;\n\t\tcase 9:\n\t\t\tc += k[2] & LOWER8b_MASK; b += k[1]; a += k[0]; break;\n\t\tcase 8:\n\t\t\tb += k[1]; a += k[0]; break;\n\t\tcase 7:\n\t\t\tb += k[1] & LOWER24b_MASK; a += k[0]; break;\n\t\tcase 6:\n\t\t\tb += k[1] & LOWER16b_MASK; a += k[0]; break;\n\t\tcase 5:\n\t\t\tb += k[1] & LOWER8b_MASK; a += k[0]; break;\n\t\tcase 4:\n\t\t\ta += k[0]; break;\n\t\tcase 3:\n\t\t\ta += k[0] & LOWER24b_MASK; break;\n\t\tcase 2:\n\t\t\ta += k[0] & LOWER16b_MASK; break;\n\t\tcase 1:\n\t\t\ta += k[0] & LOWER8b_MASK; break;\n\t\t/* zero length strings require no mixing */\n\t\tcase 0:\n\t\t\t*pc = c;\n\t\t\t*pb = b;\n\t\t\treturn;\n\t\t};\n\t} else {\n\t\t/* all but the last block: affect some 32 bits of (a, b, c) */\n\t\twhile (length > 12) {\n\t\t\ta += BIT_SHIFT(k[0], k[1], s);\n\t\t\tb += BIT_SHIFT(k[1], k[2], s);\n\t\t\tc += BIT_SHIFT(k[2], k[3], s);\n\t\t\t__rte_jhash_mix(a, b, c);\n\n\t\t\tk += 3;\n\t\t\tlength -= 12;\n\t\t}\n\n\t\t/* last block: affect all 32 bits of (c) */\n\t\tswitch (length) {\n\t\tcase 12:\n\t\t\ta += BIT_SHIFT(k[0], k[1], s);\n\t\t\tb += BIT_SHIFT(k[1], k[2], s);\n\t\t\tc += BIT_SHIFT(k[2], k[3], s);\n\t\t\tbreak;\n\t\tcase 11:\n\t\t\ta += BIT_SHIFT(k[0], k[1], s);\n\t\t\tb += BIT_SHIFT(k[1], k[2], s);\n\t\t\tc += BIT_SHIFT(k[2], k[3], s) & LOWER24b_MASK;\n\t\t\tbreak;\n\t\tcase 10:\n\t\t\ta += BIT_SHIFT(k[0], k[1], s);\n\t\t\tb += BIT_SHIFT(k[1], k[2], s);\n\t\t\tc += BIT_SHIFT(k[2], k[3], s) & LOWER16b_MASK;\n\t\t\tbreak;\n\t\tcase 9:\n\t\t\ta += BIT_SHIFT(k[0], k[1], s);\n\t\t\tb += BIT_SHIFT(k[1], k[2], s);\n\t\t\tc += BIT_SHIFT(k[2], k[3], s) & LOWER8b_MASK;\n\t\t\tbreak;\n\t\tcase 8:\n\t\t\ta += BIT_SHIFT(k[0], k[1], s);\n\t\t\tb += BIT_SHIFT(k[1], k[2], s);\n\t\t\tbreak;\n\t\tcase 7:\n\t\t\ta += BIT_SHIFT(k[0], k[1], s);\n\t\t\tb += BIT_SHIFT(k[1], k[2], s) & LOWER24b_MASK;\n\t\t\tbreak;\n\t\tcase 6:\n\t\t\ta += BIT_SHIFT(k[0], k[1], s);\n\t\t\tb += BIT_SHIFT(k[1], k[2], s) & LOWER16b_MASK;\n\t\t\tbreak;\n\t\tcase 5:\n\t\t\ta += BIT_SHIFT(k[0], k[1], s);\n\t\t\tb += BIT_SHIFT(k[1], k[2], s) & LOWER8b_MASK;\n\t\t\tbreak;\n\t\tcase 4:\n\t\t\ta += BIT_SHIFT(k[0], k[1], s);\n\t\t\tbreak;\n\t\tcase 3:\n\t\t\ta += BIT_SHIFT(k[0], k[1], s) & LOWER24b_MASK;\n\t\t\tbreak;\n\t\tcase 2:\n\t\t\ta += BIT_SHIFT(k[0], k[1], s) & LOWER16b_MASK;\n\t\t\tbreak;\n\t\tcase 1:\n\t\t\ta += BIT_SHIFT(k[0], k[1], s) & LOWER8b_MASK;\n\t\t\tbreak;\n\t\t/* zero length strings require no mixing */\n\t\tcase 0:\n\t\t\t*pc = c;\n\t\t\t*pb = b;\n\t\t\treturn;\n\t\t}\n\t}\n\n\t__rte_jhash_final(a, b, c);\n\n\t*pc = c;\n\t*pb = b;\n}\n\n/**\n * Same as rte_jhash, but takes two seeds and return two uint32_ts.\n * pc and pb must be non-null, and *pc and *pb must both be initialized\n * with seeds. If you pass in (*pb)=0, the output (*pc) will be\n * the same as the return value from rte_jhash.\n *\n * @param key\n * Key to calculate hash of.\n * @param length\n * Length of key in bytes.\n * @param pc\n * IN: seed OUT: primary hash value.\n * @param pb\n * IN: second seed OUT: secondary hash value.\n */\nstatic inline void\nrte_jhash_2hashes(const void *key, uint32_t length, uint32_t *pc, uint32_t *pb)\n{\n\t__rte_jhash_2hashes(key, length, pc, pb, 1);\n}\n\n/**\n * Same as rte_jhash2, but takes two seeds and return two uint32_ts.\n * pc and pb must be non-null, and *pc and *pb must both be initialized\n * with seeds. If you pass in (*pb)=0, the output (*pc) will be\n * the same as the return value from rte_jhash2.\n *\n * @param k\n * Key to calculate hash of.\n * @param length\n * Length of key in units of 4 bytes.\n * @param pc\n * IN: seed OUT: primary hash value.\n * @param pb\n * IN: second seed OUT: secondary hash value.\n */\nstatic inline void\nrte_jhash_32b_2hashes(const uint32_t *k, uint32_t length, uint32_t *pc, uint32_t *pb)\n{\n\t__rte_jhash_2hashes((const void *) k, (length << 2), pc, pb, 0);\n}\n\n/**\n * The most generic version, hashes an arbitrary sequence\n * of bytes. No alignment or length assumptions are made about\n * the input key.\n *\n * @param key\n * Key to calculate hash of.\n * @param length\n * Length of key in bytes.\n * @param initval\n * Initialising value of hash.\n * @return\n * Calculated hash value.\n */\nstatic inline uint32_t\nrte_jhash(const void *key, uint32_t length, uint32_t initval)\n{\n\tuint32_t initval2 = 0;\n\n\trte_jhash_2hashes(key, length, &initval, &initval2);\n\n\treturn initval;\n}\n\n/**\n * A special optimized version that handles 1 or more of uint32_ts.\n * The length parameter here is the number of uint32_ts in the key.\n *\n * @param k\n * Key to calculate hash of.\n * @param length\n * Length of key in units of 4 bytes.\n * @param initval\n * Initialising value of hash.\n * @return\n * Calculated hash value.\n */\nstatic inline uint32_t\nrte_jhash_32b(const uint32_t *k, uint32_t length, uint32_t initval)\n{\n\tuint32_t initval2 = 0;\n\n\trte_jhash_32b_2hashes(k, length, &initval, &initval2);\n\n\treturn initval;\n}\n\nstatic inline uint32_t\n__attribute__ ((deprecated))\nrte_jhash2(const uint32_t *k, uint32_t length, uint32_t initval)\n{\n\tuint32_t initval2 = 0;\n\n\trte_jhash_32b_2hashes(k, length, &initval, &initval2);\n\n\treturn initval;\n}\n\nstatic inline uint32_t\n__rte_jhash_3words(uint32_t a, uint32_t b, uint32_t c, uint32_t initval)\n{\n\ta += RTE_JHASH_GOLDEN_RATIO + initval;\n\tb += RTE_JHASH_GOLDEN_RATIO + initval;\n\tc += RTE_JHASH_GOLDEN_RATIO + initval;\n\n\t__rte_jhash_final(a, b, c);\n\n\treturn c;\n}\n\n/**\n * A special ultra-optimized versions that knows it is hashing exactly\n * 3 words.\n *\n * @param a\n * First word to calculate hash of.\n * @param b\n * Second word to calculate hash of.\n * @param c\n * Third word to calculate hash of.\n * @param initval\n * Initialising value of hash.\n * @return\n * Calculated hash value.\n */\nstatic inline uint32_t\nrte_jhash_3words(uint32_t a, uint32_t b, uint32_t c, uint32_t initval)\n{\n\treturn __rte_jhash_3words(a + 12, b + 12, c + 12, initval);\n}\n\n/**\n * A special ultra-optimized versions that knows it is hashing exactly\n * 2 words.\n *\n * @param a\n * First word to calculate hash of.\n * @param b\n * Second word to calculate hash of.\n * @param initval\n * Initialising value of hash.\n * @return\n * Calculated hash value.\n */\nstatic inline uint32_t\nrte_jhash_2words(uint32_t a, uint32_t b, uint32_t initval)\n{\n\treturn __rte_jhash_3words(a + 8, b + 8, 8, initval);\n}\n\n/**\n * A special ultra-optimized versions that knows it is hashing exactly\n * 1 word.\n *\n * @param a\n * Word to calculate hash of.\n * @param initval\n * Initialising value of hash.\n * @return\n * Calculated hash value.\n */\nstatic inline uint32_t\nrte_jhash_1word(uint32_t a, uint32_t initval)\n{\n\treturn __rte_jhash_3words(a + 4, 4, 4, initval);\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_JHASH_H */\n" }, { "path": "lib/librte_hash/rte_thash.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 Vladimir Medvedkin \n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_THASH_H\n#define _RTE_THASH_H\n\n/**\n * @file\n *\n * toeplitz hash functions.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Software implementation of the Toeplitz hash function used by RSS.\n * Can be used either for packet distribution on single queue NIC\n * or for simulating of RSS computation on specific NIC (for example\n * after GRE header decapsulating)\n */\n\n#include \n#include \n#include \n\n#ifdef __SSE3__\n#include \n#endif\n\n#ifdef __SSE3__\n/* Byte swap mask used for converting IPv6 address\n * 4-byte chunks to CPU byte order\n */\nstatic const __m128i rte_thash_ipv6_bswap_mask = {\n\t\t0x0405060700010203ULL, 0x0C0D0E0F08090A0BULL};\n#endif\n\n/**\n * length in dwords of input tuple to\n * calculate hash of ipv4 header only\n */\n#define RTE_THASH_V4_L3_LEN\t((sizeof(struct rte_ipv4_tuple) -\t\\\n\t\t\tsizeof(((struct rte_ipv4_tuple *)0)->sctp_tag)) / 4)\n\n/**\n * length in dwords of input tuple to\n * calculate hash of ipv4 header +\n * transport header\n */\n#define RTE_THASH_V4_L4_LEN\t ((sizeof(struct rte_ipv4_tuple)) / 4)\n\n/**\n * length in dwords of input tuple to\n * calculate hash of ipv6 header only\n */\n#define RTE_THASH_V6_L3_LEN\t((sizeof(struct rte_ipv6_tuple) - \\\n\t\t\tsizeof(((struct rte_ipv6_tuple *)0)->sctp_tag)) / 4)\n\n/**\n * length in dwords of input tuple to\n * calculate hash of ipv6 header +\n * transport header\n */\n#define RTE_THASH_V6_L4_LEN\t((sizeof(struct rte_ipv6_tuple)) / 4)\n\n/**\n * IPv4 tuple\n * addresses and ports/sctp_tag have to be CPU byte order\n */\nstruct rte_ipv4_tuple {\n\tuint32_t\tsrc_addr;\n\tuint32_t\tdst_addr;\n\tunion {\n\t\tstruct {\n\t\t\tuint16_t dport;\n\t\t\tuint16_t sport;\n\t\t};\n\t\tuint32_t sctp_tag;\n\t};\n};\n\n/**\n * IPv6 tuple\n * Addresses have to be filled by rte_thash_load_v6_addr()\n * ports/sctp_tag have to be CPU byte order\n */\nstruct rte_ipv6_tuple {\n\tuint8_t\t\tsrc_addr[16];\n\tuint8_t\t\tdst_addr[16];\n\tunion {\n\t\tstruct {\n\t\t\tuint16_t dport;\n\t\t\tuint16_t sport;\n\t\t};\n\t\tuint32_t sctp_tag;\n\t};\n};\n\nunion rte_thash_tuple {\n\tstruct rte_ipv4_tuple\tv4;\n\tstruct rte_ipv6_tuple\tv6;\n#ifdef __SSE3__\n} __attribute__((aligned(XMM_SIZE)));\n#else\n};\n#endif\n\n/**\n * Prepare special converted key to use with rte_softrss_be()\n * @param orig\n * pointer to original RSS key\n * @param targ\n * pointer to target RSS key\n * @param len\n * RSS key length\n */\nstatic inline void\nrte_convert_rss_key(const uint32_t *orig, uint32_t *targ, int len)\n{\n\tint i;\n\n\tfor (i = 0; i < (len >> 2); i++)\n\t\ttarg[i] = rte_be_to_cpu_32(orig[i]);\n}\n\n/**\n * Prepare and load IPv6 addresses (src and dst)\n * into target tuple\n * @param orig\n * Pointer to ipv6 header of the original packet\n * @param targ\n * Pointer to rte_ipv6_tuple structure\n */\nstatic inline void\nrte_thash_load_v6_addrs(const struct ipv6_hdr *orig, union rte_thash_tuple *targ)\n{\n#ifdef __SSE3__\n\t__m128i ipv6 = _mm_loadu_si128((const __m128i *)orig->src_addr);\n\t*(__m128i *)targ->v6.src_addr =\n\t\t\t_mm_shuffle_epi8(ipv6, rte_thash_ipv6_bswap_mask);\n\tipv6 = _mm_loadu_si128((const __m128i *)orig->dst_addr);\n\t*(__m128i *)targ->v6.dst_addr =\n\t\t\t_mm_shuffle_epi8(ipv6, rte_thash_ipv6_bswap_mask);\n#else\n\tint i;\n\tfor (i = 0; i < 4; i++) {\n\t\t*((uint32_t *)targ->v6.src_addr + i) =\n\t\t\trte_be_to_cpu_32(*((const uint32_t *)orig->src_addr + i));\n\t\t*((uint32_t *)targ->v6.dst_addr + i) =\n\t\t\trte_be_to_cpu_32(*((const uint32_t *)orig->dst_addr + i));\n\t}\n#endif\n}\n\n/**\n * Generic implementation. Can be used with original rss_key\n * @param input_tuple\n * Pointer to input tuple\n * @param input_len\n * Length of input_tuple in 4-bytes chunks\n * @param rss_key\n * Pointer to RSS hash key.\n * @return\n * Calculated hash value.\n */\nstatic inline uint32_t\nrte_softrss(uint32_t *input_tuple, uint32_t input_len,\n\t\tconst uint8_t *rss_key)\n{\n\tuint32_t i, j, ret = 0;\n\n\tfor (j = 0; j < input_len; j++) {\n\t\tfor (i = 0; i < 32; i++) {\n\t\t\tif (input_tuple[j] & (1 << (31 - i))) {\n\t\t\t\tret ^= rte_cpu_to_be_32(((const uint32_t *)rss_key)[j]) << i |\n\t\t\t\t\t(uint32_t)((uint64_t)(rte_cpu_to_be_32(((const uint32_t *)rss_key)[j + 1])) >>\n\t\t\t\t\t(32 - i));\n\t\t\t}\n\t\t}\n\t}\n\treturn ret;\n}\n\n/**\n * Optimized implementation.\n * If you want the calculated hash value matches NIC RSS value\n * you have to use special converted key with rte_convert_rss_key() fn.\n * @param input_tuple\n * Pointer to input tuple\n * @param input_len\n * Length of input_tuple in 4-bytes chunks\n * @param *rss_key\n * Pointer to RSS hash key.\n * @return\n * Calculated hash value.\n */\nstatic inline uint32_t\nrte_softrss_be(uint32_t *input_tuple, uint32_t input_len,\n\t\tconst uint8_t *rss_key)\n{\n\tuint32_t i, j, ret = 0;\n\n\tfor (j = 0; j < input_len; j++) {\n\t\tfor (i = 0; i < 32; i++) {\n\t\t\tif (input_tuple[j] & (1 << (31 - i))) {\n\t\t\t\tret ^= ((const uint32_t *)rss_key)[j] << i |\n\t\t\t\t\t(uint32_t)((uint64_t)(((const uint32_t *)rss_key)[j + 1]) >> (32 - i));\n\t\t\t}\n\t\t}\n\t}\n\treturn ret;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_THASH_H */\n" }, { "path": "lib/librte_ip_frag/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_ip_frag.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR)\n\nEXPORT_MAP := rte_ipfrag_version.map\n\nLIBABIVER := 1\n\n#source files\nSRCS-$(CONFIG_RTE_LIBRTE_IP_FRAG) += rte_ipv4_fragmentation.c\nSRCS-$(CONFIG_RTE_LIBRTE_IP_FRAG) += rte_ipv6_fragmentation.c\nSRCS-$(CONFIG_RTE_LIBRTE_IP_FRAG) += rte_ipv4_reassembly.c\nSRCS-$(CONFIG_RTE_LIBRTE_IP_FRAG) += rte_ipv6_reassembly.c\nSRCS-$(CONFIG_RTE_LIBRTE_IP_FRAG) += rte_ip_frag_common.c\nSRCS-$(CONFIG_RTE_LIBRTE_IP_FRAG) += ip_frag_internal.c\n\n# install this header file\nSYMLINK-$(CONFIG_RTE_LIBRTE_IP_FRAG)-include += rte_ip_frag.h\n\n\n# this library depends on rte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_IP_FRAG) += lib/librte_mempool lib/librte_ether\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_ip_frag/ip_frag_common.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _IP_FRAG_COMMON_H_\n#define _IP_FRAG_COMMON_H_\n\n#include \"rte_ip_frag.h\"\n\n/* logging macros. */\n#ifdef RTE_LIBRTE_IP_FRAG_DEBUG\n\n#define\tIP_FRAG_LOG(lvl, fmt, args...)\tRTE_LOG(lvl, USER1, fmt, ##args)\n\n#define\tIP_FRAG_ASSERT(exp)\t\t\t\t\t\\\nif (!(exp))\t{\t\t\t\t\t\t\t\\\n\trte_panic(\"function %s, line%d\\tassert \\\"\" #exp \"\\\" failed\\n\",\t\\\n\t\t__func__, __LINE__);\t\t\t\t\t\\\n}\n#else\n#define\tIP_FRAG_LOG(lvl, fmt, args...)\tdo {} while(0)\n#define IP_FRAG_ASSERT(exp)\tdo {} while (0)\n#endif /* IP_FRAG_DEBUG */\n\n#define IPV4_KEYLEN 1\n#define IPV6_KEYLEN 4\n\n/* helper macros */\n#define\tIP_FRAG_MBUF2DR(dr, mb)\t((dr)->row[(dr)->cnt++] = (mb))\n\n#define IPv6_KEY_BYTES(key) \\\n\t(key)[0], (key)[1], (key)[2], (key)[3]\n#define IPv6_KEY_BYTES_FMT \\\n\t\"%08\" PRIx64 \"%08\" PRIx64 \"%08\" PRIx64 \"%08\" PRIx64\n\n/* internal functions declarations */\nstruct rte_mbuf * ip_frag_process(struct ip_frag_pkt *fp,\n\t\tstruct rte_ip_frag_death_row *dr, struct rte_mbuf *mb,\n\t\tuint16_t ofs, uint16_t len, uint16_t more_frags);\n\nstruct ip_frag_pkt * ip_frag_find(struct rte_ip_frag_tbl *tbl,\n\t\tstruct rte_ip_frag_death_row *dr,\n\t\tconst struct ip_frag_key *key, uint64_t tms);\n\nstruct ip_frag_pkt * ip_frag_lookup(struct rte_ip_frag_tbl *tbl,\n\tconst struct ip_frag_key *key, uint64_t tms,\n\tstruct ip_frag_pkt **free, struct ip_frag_pkt **stale);\n\n/* these functions need to be declared here as ip_frag_process relies on them */\nstruct rte_mbuf * ipv4_frag_reassemble(const struct ip_frag_pkt *fp);\nstruct rte_mbuf * ipv6_frag_reassemble(const struct ip_frag_pkt *fp);\n\n\n\n/*\n * misc frag key functions\n */\n\n/* check if key is empty */\nstatic inline int\nip_frag_key_is_empty(const struct ip_frag_key * key)\n{\n\tuint32_t i;\n\tfor (i = 0; i < RTE_MIN(key->key_len, RTE_DIM(key->src_dst)); i++)\n\t\tif (key->src_dst[i] != 0)\n\t\t\treturn 0;\n\treturn 1;\n}\n\n/* empty the key */\nstatic inline void\nip_frag_key_invalidate(struct ip_frag_key * key)\n{\n\tuint32_t i;\n\tfor (i = 0; i < key->key_len; i++)\n\t\tkey->src_dst[i] = 0;\n}\n\n/* compare two keys */\nstatic inline int\nip_frag_key_cmp(const struct ip_frag_key * k1, const struct ip_frag_key * k2)\n{\n\tuint32_t i, val;\n\tval = k1->id ^ k2->id;\n\tfor (i = 0; i < k1->key_len; i++)\n\t\tval |= k1->src_dst[i] ^ k2->src_dst[i];\n\treturn val;\n}\n\n/*\n * misc fragment functions\n */\n\n/* put fragment on death row */\nstatic inline void\nip_frag_free(struct ip_frag_pkt *fp, struct rte_ip_frag_death_row *dr)\n{\n\tuint32_t i, k;\n\n\tk = dr->cnt;\n\tfor (i = 0; i != fp->last_idx; i++) {\n\t\tif (fp->frags[i].mb != NULL) {\n\t\t\tdr->row[k++] = fp->frags[i].mb;\n\t\t\tfp->frags[i].mb = NULL;\n\t\t}\n\t}\n\n\tfp->last_idx = 0;\n\tdr->cnt = k;\n}\n\n/* if key is empty, mark key as in use */\nstatic inline void\nip_frag_inuse(struct rte_ip_frag_tbl *tbl, const struct ip_frag_pkt *fp)\n{\n\tif (ip_frag_key_is_empty(&fp->key)) {\n\t\tTAILQ_REMOVE(&tbl->lru, fp, lru);\n\t\ttbl->use_entries--;\n\t}\n}\n\n/* reset the fragment */\nstatic inline void\nip_frag_reset(struct ip_frag_pkt *fp, uint64_t tms)\n{\n\tstatic const struct ip_frag zero_frag = {\n\t\t.ofs = 0,\n\t\t.len = 0,\n\t\t.mb = NULL,\n\t};\n\n\tfp->start = tms;\n\tfp->total_size = UINT32_MAX;\n\tfp->frag_size = 0;\n\tfp->last_idx = IP_MIN_FRAG_NUM;\n\tfp->frags[IP_LAST_FRAG_IDX] = zero_frag;\n\tfp->frags[IP_FIRST_FRAG_IDX] = zero_frag;\n}\n\n/* chain two mbufs */\nstatic inline void\nip_frag_chain(struct rte_mbuf *mn, struct rte_mbuf *mp)\n{\n\tstruct rte_mbuf *ms;\n\n\t/* adjust start of the last fragment data. */\n\trte_pktmbuf_adj(mp, (uint16_t)(mp->l2_len + mp->l3_len));\n\n\t/* chain two fragments. */\n\tms = rte_pktmbuf_lastseg(mn);\n\tms->next = mp;\n\n\t/* accumulate number of segments and total length. */\n\tmn->nb_segs = (uint8_t)(mn->nb_segs + mp->nb_segs);\n\tmn->pkt_len += mp->pkt_len;\n\n\t/* reset pkt_len and nb_segs for chained fragment. */\n\tmp->pkt_len = mp->data_len;\n\tmp->nb_segs = 1;\n}\n\n\n#endif /* _IP_FRAG_COMMON_H_ */\n" }, { "path": "lib/librte_ip_frag/ip_frag_internal.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#ifdef RTE_MACHINE_CPUFLAG_SSE4_2\n#include \n#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */\n\n#include \"ip_frag_common.h\"\n\n#define\tPRIME_VALUE\t0xeaad8405\n\n#define\tIP_FRAG_TBL_POS(tbl, sig)\t\\\n\t((tbl)->pkt + ((sig) & (tbl)->entry_mask))\n\n#ifdef RTE_LIBRTE_IP_FRAG_TBL_STAT\n#define\tIP_FRAG_TBL_STAT_UPDATE(s, f, v)\t((s)->f += (v))\n#else\n#define\tIP_FRAG_TBL_STAT_UPDATE(s, f, v)\tdo {} while (0)\n#endif /* IP_FRAG_TBL_STAT */\n\n/* local frag table helper functions */\nstatic inline void\nip_frag_tbl_del(struct rte_ip_frag_tbl *tbl, struct rte_ip_frag_death_row *dr,\n\tstruct ip_frag_pkt *fp)\n{\n\tip_frag_free(fp, dr);\n\tip_frag_key_invalidate(&fp->key);\n\tTAILQ_REMOVE(&tbl->lru, fp, lru);\n\ttbl->use_entries--;\n\tIP_FRAG_TBL_STAT_UPDATE(&tbl->stat, del_num, 1);\n}\n\nstatic inline void\nip_frag_tbl_add(struct rte_ip_frag_tbl *tbl, struct ip_frag_pkt *fp,\n\tconst struct ip_frag_key *key, uint64_t tms)\n{\n\tfp->key = key[0];\n\tip_frag_reset(fp, tms);\n\tTAILQ_INSERT_TAIL(&tbl->lru, fp, lru);\n\ttbl->use_entries++;\n\tIP_FRAG_TBL_STAT_UPDATE(&tbl->stat, add_num, 1);\n}\n\nstatic inline void\nip_frag_tbl_reuse(struct rte_ip_frag_tbl *tbl, struct rte_ip_frag_death_row *dr,\n\tstruct ip_frag_pkt *fp, uint64_t tms)\n{\n\tip_frag_free(fp, dr);\n\tip_frag_reset(fp, tms);\n\tTAILQ_REMOVE(&tbl->lru, fp, lru);\n\tTAILQ_INSERT_TAIL(&tbl->lru, fp, lru);\n\tIP_FRAG_TBL_STAT_UPDATE(&tbl->stat, reuse_num, 1);\n}\n\n\nstatic inline void\nipv4_frag_hash(const struct ip_frag_key *key, uint32_t *v1, uint32_t *v2)\n{\n\tuint32_t v;\n\tconst uint32_t *p;\n\n\tp = (const uint32_t *)&key->src_dst;\n\n#ifdef RTE_MACHINE_CPUFLAG_SSE4_2\n\tv = rte_hash_crc_4byte(p[0], PRIME_VALUE);\n\tv = rte_hash_crc_4byte(p[1], v);\n\tv = rte_hash_crc_4byte(key->id, v);\n#else\n\n\tv = rte_jhash_3words(p[0], p[1], key->id, PRIME_VALUE);\n#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */\n\n\t*v1 = v;\n\t*v2 = (v << 7) + (v >> 14);\n}\n\nstatic inline void\nipv6_frag_hash(const struct ip_frag_key *key, uint32_t *v1, uint32_t *v2)\n{\n\tuint32_t v;\n\tconst uint32_t *p;\n\n\tp = (const uint32_t *) &key->src_dst;\n\n#ifdef RTE_MACHINE_CPUFLAG_SSE4_2\n\tv = rte_hash_crc_4byte(p[0], PRIME_VALUE);\n\tv = rte_hash_crc_4byte(p[1], v);\n\tv = rte_hash_crc_4byte(p[2], v);\n\tv = rte_hash_crc_4byte(p[3], v);\n\tv = rte_hash_crc_4byte(p[4], v);\n\tv = rte_hash_crc_4byte(p[5], v);\n\tv = rte_hash_crc_4byte(p[6], v);\n\tv = rte_hash_crc_4byte(p[7], v);\n\tv = rte_hash_crc_4byte(key->id, v);\n#else\n\n\tv = rte_jhash_3words(p[0], p[1], p[2], PRIME_VALUE);\n\tv = rte_jhash_3words(p[3], p[4], p[5], v);\n\tv = rte_jhash_3words(p[6], p[7], key->id, v);\n#endif /* RTE_MACHINE_CPUFLAG_SSE4_2 */\n\n\t*v1 = v;\n\t*v2 = (v << 7) + (v >> 14);\n}\n\nstruct rte_mbuf *\nip_frag_process(struct ip_frag_pkt *fp, struct rte_ip_frag_death_row *dr,\n\tstruct rte_mbuf *mb, uint16_t ofs, uint16_t len, uint16_t more_frags)\n{\n\tuint32_t idx;\n\n\tfp->frag_size += len;\n\n\t/* this is the first fragment. */\n\tif (ofs == 0) {\n\t\tidx = (fp->frags[IP_FIRST_FRAG_IDX].mb == NULL) ?\n\t\t\t\tIP_FIRST_FRAG_IDX : UINT32_MAX;\n\n\t/* this is the last fragment. */\n\t} else if (more_frags == 0) {\n\t\tfp->total_size = ofs + len;\n\t\tidx = (fp->frags[IP_LAST_FRAG_IDX].mb == NULL) ?\n\t\t\t\tIP_LAST_FRAG_IDX : UINT32_MAX;\n\n\t/* this is the intermediate fragment. */\n\t} else if ((idx = fp->last_idx) <\n\t\tsizeof (fp->frags) / sizeof (fp->frags[0])) {\n\t\tfp->last_idx++;\n\t}\n\n\t/*\n\t * errorneous packet: either exceeed max allowed number of fragments,\n\t * or duplicate first/last fragment encountered.\n\t */\n\tif (idx >= sizeof (fp->frags) / sizeof (fp->frags[0])) {\n\n\t\t/* report an error. */\n\t\tif (fp->key.key_len == IPV4_KEYLEN)\n\t\t\tIP_FRAG_LOG(DEBUG, \"%s:%d invalid fragmented packet:\\n\"\n\t\t\t\t\"ipv4_frag_pkt: %p, key: <%\" PRIx64 \", %#x>, \"\n\t\t\t\t\"total_size: %u, frag_size: %u, last_idx: %u\\n\"\n\t\t\t\t\"first fragment: ofs: %u, len: %u\\n\"\n\t\t\t\t\"last fragment: ofs: %u, len: %u\\n\\n\",\n\t\t\t\t__func__, __LINE__,\n\t\t\t\tfp, fp->key.src_dst[0], fp->key.id,\n\t\t\t\tfp->total_size, fp->frag_size, fp->last_idx,\n\t\t\t\tfp->frags[IP_FIRST_FRAG_IDX].ofs,\n\t\t\t\tfp->frags[IP_FIRST_FRAG_IDX].len,\n\t\t\t\tfp->frags[IP_LAST_FRAG_IDX].ofs,\n\t\t\t\tfp->frags[IP_LAST_FRAG_IDX].len);\n\t\telse\n\t\t\tIP_FRAG_LOG(DEBUG, \"%s:%d invalid fragmented packet:\\n\"\n\t\t\t\t\"ipv4_frag_pkt: %p, key: <\" IPv6_KEY_BYTES_FMT \", %#x>, \"\n\t\t\t\t\"total_size: %u, frag_size: %u, last_idx: %u\\n\"\n\t\t\t\t\"first fragment: ofs: %u, len: %u\\n\"\n\t\t\t\t\"last fragment: ofs: %u, len: %u\\n\\n\",\n\t\t\t\t__func__, __LINE__,\n\t\t\t\tfp, IPv6_KEY_BYTES(fp->key.src_dst), fp->key.id,\n\t\t\t\tfp->total_size, fp->frag_size, fp->last_idx,\n\t\t\t\tfp->frags[IP_FIRST_FRAG_IDX].ofs,\n\t\t\t\tfp->frags[IP_FIRST_FRAG_IDX].len,\n\t\t\t\tfp->frags[IP_LAST_FRAG_IDX].ofs,\n\t\t\t\tfp->frags[IP_LAST_FRAG_IDX].len);\n\n\t\t/* free all fragments, invalidate the entry. */\n\t\tip_frag_free(fp, dr);\n\t\tip_frag_key_invalidate(&fp->key);\n\t\tIP_FRAG_MBUF2DR(dr, mb);\n\n\t\treturn NULL;\n\t}\n\n\tfp->frags[idx].ofs = ofs;\n\tfp->frags[idx].len = len;\n\tfp->frags[idx].mb = mb;\n\n\tmb = NULL;\n\n\t/* not all fragments are collected yet. */\n\tif (likely (fp->frag_size < fp->total_size)) {\n\t\treturn mb;\n\n\t/* if we collected all fragments, then try to reassemble. */\n\t} else if (fp->frag_size == fp->total_size &&\n\t\t\tfp->frags[IP_FIRST_FRAG_IDX].mb != NULL) {\n\t\tif (fp->key.key_len == IPV4_KEYLEN)\n\t\t\tmb = ipv4_frag_reassemble(fp);\n\t\telse\n\t\t\tmb = ipv6_frag_reassemble(fp);\n\t}\n\n\t/* errorenous set of fragments. */\n\tif (mb == NULL) {\n\n\t\t/* report an error. */\n\t\tif (fp->key.key_len == IPV4_KEYLEN)\n\t\t\tIP_FRAG_LOG(DEBUG, \"%s:%d invalid fragmented packet:\\n\"\n\t\t\t\t\"ipv4_frag_pkt: %p, key: <%\" PRIx64 \", %#x>, \"\n\t\t\t\t\"total_size: %u, frag_size: %u, last_idx: %u\\n\"\n\t\t\t\t\"first fragment: ofs: %u, len: %u\\n\"\n\t\t\t\t\"last fragment: ofs: %u, len: %u\\n\\n\",\n\t\t\t\t__func__, __LINE__,\n\t\t\t\tfp, fp->key.src_dst[0], fp->key.id,\n\t\t\t\tfp->total_size, fp->frag_size, fp->last_idx,\n\t\t\t\tfp->frags[IP_FIRST_FRAG_IDX].ofs,\n\t\t\t\tfp->frags[IP_FIRST_FRAG_IDX].len,\n\t\t\t\tfp->frags[IP_LAST_FRAG_IDX].ofs,\n\t\t\t\tfp->frags[IP_LAST_FRAG_IDX].len);\n\t\telse\n\t\t\tIP_FRAG_LOG(DEBUG, \"%s:%d invalid fragmented packet:\\n\"\n\t\t\t\t\"ipv4_frag_pkt: %p, key: <\" IPv6_KEY_BYTES_FMT \", %#x>, \"\n\t\t\t\t\"total_size: %u, frag_size: %u, last_idx: %u\\n\"\n\t\t\t\t\"first fragment: ofs: %u, len: %u\\n\"\n\t\t\t\t\"last fragment: ofs: %u, len: %u\\n\\n\",\n\t\t\t\t__func__, __LINE__,\n\t\t\t\tfp, IPv6_KEY_BYTES(fp->key.src_dst), fp->key.id,\n\t\t\t\tfp->total_size, fp->frag_size, fp->last_idx,\n\t\t\t\tfp->frags[IP_FIRST_FRAG_IDX].ofs,\n\t\t\t\tfp->frags[IP_FIRST_FRAG_IDX].len,\n\t\t\t\tfp->frags[IP_LAST_FRAG_IDX].ofs,\n\t\t\t\tfp->frags[IP_LAST_FRAG_IDX].len);\n\n\t\t/* free associated resources. */\n\t\tip_frag_free(fp, dr);\n\t}\n\n\t/* we are done with that entry, invalidate it. */\n\tip_frag_key_invalidate(&fp->key);\n\treturn mb;\n}\n\n\n/*\n * Find an entry in the table for the corresponding fragment.\n * If such entry is not present, then allocate a new one.\n * If the entry is stale, then free and reuse it.\n */\nstruct ip_frag_pkt *\nip_frag_find(struct rte_ip_frag_tbl *tbl, struct rte_ip_frag_death_row *dr,\n\tconst struct ip_frag_key *key, uint64_t tms)\n{\n\tstruct ip_frag_pkt *pkt, *free, *stale, *lru;\n\tuint64_t max_cycles;\n\n\t/*\n\t * Actually the two line below are totally redundant.\n\t * they are here, just to make gcc 4.6 happy.\n\t */\n\tfree = NULL;\n\tstale = NULL;\n\tmax_cycles = tbl->max_cycles;\n\n\tIP_FRAG_TBL_STAT_UPDATE(&tbl->stat, find_num, 1);\n\n\tif ((pkt = ip_frag_lookup(tbl, key, tms, &free, &stale)) == NULL) {\n\n\t\t/*timed-out entry, free and invalidate it*/\n\t\tif (stale != NULL) {\n\t\t\tip_frag_tbl_del(tbl, dr, stale);\n\t\t\tfree = stale;\n\n\t\t/*\n\t\t * we found a free entry, check if we can use it.\n\t\t * If we run out of free entries in the table, then\n\t\t * check if we have a timed out entry to delete.\n\t\t */\n\t\t} else if (free != NULL &&\n\t\t\t\ttbl->max_entries <= tbl->use_entries) {\n\t\t\tlru = TAILQ_FIRST(&tbl->lru);\n\t\t\tif (max_cycles + lru->start < tms) {\n\t\t\t\tip_frag_tbl_del(tbl, dr, lru);\n\t\t\t} else {\n\t\t\t\tfree = NULL;\n\t\t\t\tIP_FRAG_TBL_STAT_UPDATE(&tbl->stat,\n\t\t\t\t\tfail_nospace, 1);\n\t\t\t}\n\t\t}\n\n\t\t/* found a free entry to reuse. */\n\t\tif (free != NULL) {\n\t\t\tip_frag_tbl_add(tbl, free, key, tms);\n\t\t\tpkt = free;\n\t\t}\n\n\t/*\n\t * we found the flow, but it is already timed out,\n\t * so free associated resources, reposition it in the LRU list,\n\t * and reuse it.\n\t */\n\t} else if (max_cycles + pkt->start < tms) {\n\t\tip_frag_tbl_reuse(tbl, dr, pkt, tms);\n\t}\n\n\tIP_FRAG_TBL_STAT_UPDATE(&tbl->stat, fail_total, (pkt == NULL));\n\n\ttbl->last = pkt;\n\treturn pkt;\n}\n\nstruct ip_frag_pkt *\nip_frag_lookup(struct rte_ip_frag_tbl *tbl,\n\tconst struct ip_frag_key *key, uint64_t tms,\n\tstruct ip_frag_pkt **free, struct ip_frag_pkt **stale)\n{\n\tstruct ip_frag_pkt *p1, *p2;\n\tstruct ip_frag_pkt *empty, *old;\n\tuint64_t max_cycles;\n\tuint32_t i, assoc, sig1, sig2;\n\n\tempty = NULL;\n\told = NULL;\n\n\tmax_cycles = tbl->max_cycles;\n\tassoc = tbl->bucket_entries;\n\n\tif (tbl->last != NULL && ip_frag_key_cmp(key, &tbl->last->key) == 0)\n\t\treturn tbl->last;\n\n\t/* different hashing methods for IPv4 and IPv6 */\n\tif (key->key_len == IPV4_KEYLEN)\n\t\tipv4_frag_hash(key, &sig1, &sig2);\n\telse\n\t\tipv6_frag_hash(key, &sig1, &sig2);\n\n\tp1 = IP_FRAG_TBL_POS(tbl, sig1);\n\tp2 = IP_FRAG_TBL_POS(tbl, sig2);\n\n\tfor (i = 0; i != assoc; i++) {\n\t\tif (p1->key.key_len == IPV4_KEYLEN)\n\t\t\tIP_FRAG_LOG(DEBUG, \"%s:%d:\\n\"\n\t\t\t\t\t\"tbl: %p, max_entries: %u, use_entries: %u\\n\"\n\t\t\t\t\t\"ipv6_frag_pkt line0: %p, index: %u from %u\\n\"\n\t\t\t\"key: <%\" PRIx64 \", %#x>, start: %\" PRIu64 \"\\n\",\n\t\t\t\t\t__func__, __LINE__,\n\t\t\t\t\ttbl, tbl->max_entries, tbl->use_entries,\n\t\t\t\t\tp1, i, assoc,\n\t\t\tp1[i].key.src_dst[0], p1[i].key.id, p1[i].start);\n\t\telse\n\t\t\tIP_FRAG_LOG(DEBUG, \"%s:%d:\\n\"\n\t\t\t\t\t\"tbl: %p, max_entries: %u, use_entries: %u\\n\"\n\t\t\t\t\t\"ipv6_frag_pkt line0: %p, index: %u from %u\\n\"\n\t\t\t\"key: <\" IPv6_KEY_BYTES_FMT \", %#x>, start: %\" PRIu64 \"\\n\",\n\t\t\t\t\t__func__, __LINE__,\n\t\t\t\t\ttbl, tbl->max_entries, tbl->use_entries,\n\t\t\t\t\tp1, i, assoc,\n\t\t\tIPv6_KEY_BYTES(p1[i].key.src_dst), p1[i].key.id, p1[i].start);\n\n\t\tif (ip_frag_key_cmp(key, &p1[i].key) == 0)\n\t\t\treturn (p1 + i);\n\t\telse if (ip_frag_key_is_empty(&p1[i].key))\n\t\t\tempty = (empty == NULL) ? (p1 + i) : empty;\n\t\telse if (max_cycles + p1[i].start < tms)\n\t\t\told = (old == NULL) ? (p1 + i) : old;\n\n\t\tif (p2->key.key_len == IPV4_KEYLEN)\n\t\t\tIP_FRAG_LOG(DEBUG, \"%s:%d:\\n\"\n\t\t\t\t\t\"tbl: %p, max_entries: %u, use_entries: %u\\n\"\n\t\t\t\t\t\"ipv6_frag_pkt line1: %p, index: %u from %u\\n\"\n\t\t\t\"key: <%\" PRIx64 \", %#x>, start: %\" PRIu64 \"\\n\",\n\t\t\t\t\t__func__, __LINE__,\n\t\t\t\t\ttbl, tbl->max_entries, tbl->use_entries,\n\t\t\t\t\tp2, i, assoc,\n\t\t\tp2[i].key.src_dst[0], p2[i].key.id, p2[i].start);\n\t\telse\n\t\t\tIP_FRAG_LOG(DEBUG, \"%s:%d:\\n\"\n\t\t\t\t\t\"tbl: %p, max_entries: %u, use_entries: %u\\n\"\n\t\t\t\t\t\"ipv6_frag_pkt line1: %p, index: %u from %u\\n\"\n\t\t\t\"key: <\" IPv6_KEY_BYTES_FMT \", %#x>, start: %\" PRIu64 \"\\n\",\n\t\t\t\t\t__func__, __LINE__,\n\t\t\t\t\ttbl, tbl->max_entries, tbl->use_entries,\n\t\t\t\t\tp2, i, assoc,\n\t\t\tIPv6_KEY_BYTES(p2[i].key.src_dst), p2[i].key.id, p2[i].start);\n\n\t\tif (ip_frag_key_cmp(key, &p2[i].key) == 0)\n\t\t\treturn (p2 + i);\n\t\telse if (ip_frag_key_is_empty(&p2[i].key))\n\t\t\tempty = (empty == NULL) ?( p2 + i) : empty;\n\t\telse if (max_cycles + p2[i].start < tms)\n\t\t\told = (old == NULL) ? (p2 + i) : old;\n\t}\n\n\t*free = empty;\n\t*stale = old;\n\treturn NULL;\n}\n" }, { "path": "lib/librte_ip_frag/rte_ip_frag.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_IP_FRAG_H_\n#define _RTE_IP_FRAG_H_\n\n/**\n * @file\n * RTE IP Fragmentation and Reassembly\n *\n * Implementation of IP packet fragmentation and reassembly.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n\nstruct rte_mbuf;\n\nenum {\n\tIP_LAST_FRAG_IDX, /**< index of last fragment */\n\tIP_FIRST_FRAG_IDX, /**< index of first fragment */\n\tIP_MIN_FRAG_NUM, /**< minimum number of fragments */\n\tIP_MAX_FRAG_NUM = RTE_LIBRTE_IP_FRAG_MAX_FRAG,\n\t/**< maximum number of fragments per packet */\n};\n\n/** @internal fragmented mbuf */\nstruct ip_frag {\n\tuint16_t ofs; /**< offset into the packet */\n\tuint16_t len; /**< length of fragment */\n\tstruct rte_mbuf *mb; /**< fragment mbuf */\n};\n\n/** @internal to uniquely indetify fragmented datagram. */\nstruct ip_frag_key {\n\tuint64_t src_dst[4]; /**< src address, first 8 bytes used for IPv4 */\n\tuint32_t id; /**< dst address */\n\tuint32_t key_len; /**< src/dst key length */\n};\n\n/*\n * @internal Fragmented packet to reassemble.\n * First two entries in the frags[] array are for the last and first fragments.\n */\nstruct ip_frag_pkt {\n\tTAILQ_ENTRY(ip_frag_pkt) lru; /**< LRU list */\n\tstruct ip_frag_key key; /**< fragmentation key */\n\tuint64_t start; /**< creation timestamp */\n\tuint32_t total_size; /**< expected reassembled size */\n\tuint32_t frag_size; /**< size of fragments received */\n\tuint32_t last_idx; /**< index of next entry to fill */\n\tstruct ip_frag frags[IP_MAX_FRAG_NUM]; /**< fragments */\n} __rte_cache_aligned;\n\n#define IP_FRAG_DEATH_ROW_LEN 32 /**< death row size (in packets) */\n\n/** mbuf death row (packets to be freed) */\nstruct rte_ip_frag_death_row {\n\tuint32_t cnt; /**< number of mbufs currently on death row */\n\tstruct rte_mbuf *row[IP_FRAG_DEATH_ROW_LEN * (IP_MAX_FRAG_NUM + 1)];\n\t/**< mbufs to be freed */\n};\n\nTAILQ_HEAD(ip_pkt_list, ip_frag_pkt); /**< @internal fragments tailq */\n\n/** fragmentation table statistics */\nstruct ip_frag_tbl_stat {\n\tuint64_t find_num; /**< total # of find/insert attempts. */\n\tuint64_t add_num; /**< # of add ops. */\n\tuint64_t del_num; /**< # of del ops. */\n\tuint64_t reuse_num; /**< # of reuse (del/add) ops. */\n\tuint64_t fail_total; /**< total # of add failures. */\n\tuint64_t fail_nospace; /**< # of 'no space' add failures. */\n} __rte_cache_aligned;\n\n/** fragmentation table */\nstruct rte_ip_frag_tbl {\n\tuint64_t max_cycles; /**< ttl for table entries. */\n\tuint32_t entry_mask; /**< hash value mask. */\n\tuint32_t max_entries; /**< max entries allowed. */\n\tuint32_t use_entries; /**< entries in use. */\n\tuint32_t bucket_entries; /**< hash assocaitivity. */\n\tuint32_t nb_entries; /**< total size of the table. */\n\tuint32_t nb_buckets; /**< num of associativity lines. */\n\tstruct ip_frag_pkt *last; /**< last used entry. */\n\tstruct ip_pkt_list lru; /**< LRU list for table entries. */\n\tstruct ip_frag_tbl_stat stat; /**< statistics counters. */\n\tstruct ip_frag_pkt pkt[0]; /**< hash table. */\n};\n\n/** IPv6 fragment extension header */\nstruct ipv6_extension_fragment {\n\tuint8_t next_header; /**< Next header type */\n\tuint8_t reserved1; /**< Reserved */\n\tunion {\n\t\tstruct {\n\t\t\tuint16_t frag_offset:13; /**< Offset from the start of the packet */\n\t\t\tuint16_t reserved2:2; /**< Reserved */\n\t\t\tuint16_t more_frags:1;\n\t\t\t/**< 1 if more fragments left, 0 if last fragment */\n\t\t};\n\t\tuint16_t frag_data;\n\t\t/**< union of all fragmentation data */\n\t};\n\tuint32_t id; /**< Packet ID */\n} __attribute__((__packed__));\n\n\n\n/*\n * Create a new IP fragmentation table.\n *\n * @param bucket_num\n * Number of buckets in the hash table.\n * @param bucket_entries\n * Number of entries per bucket (e.g. hash associativity).\n * Should be power of two.\n * @param max_entries\n * Maximum number of entries that could be stored in the table.\n * The value should be less or equal then bucket_num * bucket_entries.\n * @param max_cycles\n * Maximum TTL in cycles for each fragmented packet.\n * @param socket_id\n * The *socket_id* argument is the socket identifier in the case of\n * NUMA. The value can be *SOCKET_ID_ANY* if there is no NUMA constraints.\n * @return\n * The pointer to the new allocated fragmentation table, on success. NULL on error.\n */\nstruct rte_ip_frag_tbl * rte_ip_frag_table_create(uint32_t bucket_num,\n\t\tuint32_t bucket_entries, uint32_t max_entries,\n\t\tuint64_t max_cycles, int socket_id);\n\n/*\n * Free allocated IP fragmentation table.\n *\n * @param btl\n * Fragmentation table to free.\n */\nstatic inline void\nrte_ip_frag_table_destroy( struct rte_ip_frag_tbl *tbl)\n{\n\trte_free(tbl);\n}\n\n/**\n * This function implements the fragmentation of IPv6 packets.\n *\n * @param pkt_in\n * The input packet.\n * @param pkts_out\n * Array storing the output fragments.\n * @param nb_pkts_out\n * Number of fragments.\n * @param mtu_size\n * Size in bytes of the Maximum Transfer Unit (MTU) for the outgoing IPv6\n * datagrams. This value includes the size of the IPv6 header.\n * @param pool_direct\n * MBUF pool used for allocating direct buffers for the output fragments.\n * @param pool_indirect\n * MBUF pool used for allocating indirect buffers for the output fragments.\n * @return\n * Upon successful completion - number of output fragments placed\n * in the pkts_out array.\n * Otherwise - (-1) * errno.\n */\nint32_t\nrte_ipv6_fragment_packet(struct rte_mbuf *pkt_in,\n\t\tstruct rte_mbuf **pkts_out,\n\t\tuint16_t nb_pkts_out,\n\t\tuint16_t mtu_size,\n\t\tstruct rte_mempool *pool_direct,\n\t\tstruct rte_mempool *pool_indirect);\n\n/*\n * This function implements reassembly of fragmented IPv6 packets.\n * Incoming mbuf should have its l2_len/l3_len fields setup correctly.\n *\n * @param tbl\n * Table where to lookup/add the fragmented packet.\n * @param dr\n * Death row to free buffers to\n * @param mb\n * Incoming mbuf with IPv6 fragment.\n * @param tms\n * Fragment arrival timestamp.\n * @param ip_hdr\n * Pointer to the IPv6 header.\n * @param frag_hdr\n * Pointer to the IPv6 fragment extension header.\n * @return\n * Pointer to mbuf for reassembled packet, or NULL if:\n * - an error occured.\n * - not all fragments of the packet are collected yet.\n */\nstruct rte_mbuf *rte_ipv6_frag_reassemble_packet(struct rte_ip_frag_tbl *tbl,\n\t\tstruct rte_ip_frag_death_row *dr,\n\t\tstruct rte_mbuf *mb, uint64_t tms, struct ipv6_hdr *ip_hdr,\n\t\tstruct ipv6_extension_fragment *frag_hdr);\n\n/*\n * Return a pointer to the packet's fragment header, if found.\n * It only looks at the extension header that's right after the fixed IPv6\n * header, and doesn't follow the whole chain of extension headers.\n *\n * @param hdr\n * Pointer to the IPv6 header.\n * @return\n * Pointer to the IPv6 fragment extension header, or NULL if it's not\n * present.\n */\nstatic inline struct ipv6_extension_fragment *\nrte_ipv6_frag_get_ipv6_fragment_header(struct ipv6_hdr *hdr)\n{\n\tif (hdr->proto == IPPROTO_FRAGMENT) {\n\t\treturn (struct ipv6_extension_fragment *) ++hdr;\n\t}\n\telse\n\t\treturn NULL;\n}\n\n/**\n * IPv4 fragmentation.\n *\n * This function implements the fragmentation of IPv4 packets.\n *\n * @param pkt_in\n * The input packet.\n * @param pkts_out\n * Array storing the output fragments.\n * @param nb_pkts_out\n * Number of fragments.\n * @param mtu_size\n * Size in bytes of the Maximum Transfer Unit (MTU) for the outgoing IPv4\n * datagrams. This value includes the size of the IPv4 header.\n * @param pool_direct\n * MBUF pool used for allocating direct buffers for the output fragments.\n * @param pool_indirect\n * MBUF pool used for allocating indirect buffers for the output fragments.\n * @return\n * Upon successful completion - number of output fragments placed\n * in the pkts_out array.\n * Otherwise - (-1) * errno.\n */\nint32_t rte_ipv4_fragment_packet(struct rte_mbuf *pkt_in,\n\t\t\tstruct rte_mbuf **pkts_out,\n\t\t\tuint16_t nb_pkts_out, uint16_t mtu_size,\n\t\t\tstruct rte_mempool *pool_direct,\n\t\t\tstruct rte_mempool *pool_indirect);\n\n/*\n * This function implements reassembly of fragmented IPv4 packets.\n * Incoming mbufs should have its l2_len/l3_len fields setup correclty.\n *\n * @param tbl\n * Table where to lookup/add the fragmented packet.\n * @param dr\n * Death row to free buffers to\n * @param mb\n * Incoming mbuf with IPv4 fragment.\n * @param tms\n * Fragment arrival timestamp.\n * @param ip_hdr\n * Pointer to the IPV4 header inside the fragment.\n * @return\n * Pointer to mbuf for reassebled packet, or NULL if:\n * - an error occured.\n * - not all fragments of the packet are collected yet.\n */\nstruct rte_mbuf * rte_ipv4_frag_reassemble_packet(struct rte_ip_frag_tbl *tbl,\n\t\tstruct rte_ip_frag_death_row *dr,\n\t\tstruct rte_mbuf *mb, uint64_t tms, struct ipv4_hdr *ip_hdr);\n\n/*\n * Check if the IPv4 packet is fragmented\n *\n * @param hdr\n * IPv4 header of the packet\n * @return\n * 1 if fragmented, 0 if not fragmented\n */\nstatic inline int\nrte_ipv4_frag_pkt_is_fragmented(const struct ipv4_hdr * hdr) {\n\tuint16_t flag_offset, ip_flag, ip_ofs;\n\n\tflag_offset = rte_be_to_cpu_16(hdr->fragment_offset);\n\tip_ofs = (uint16_t)(flag_offset & IPV4_HDR_OFFSET_MASK);\n\tip_flag = (uint16_t)(flag_offset & IPV4_HDR_MF_FLAG);\n\n\treturn ip_flag != 0 || ip_ofs != 0;\n}\n\n/*\n * Free mbufs on a given death row.\n *\n * @param dr\n * Death row to free mbufs in.\n * @param prefetch\n * How many buffers to prefetch before freeing.\n */\nvoid rte_ip_frag_free_death_row(struct rte_ip_frag_death_row *dr,\n\t\tuint32_t prefetch);\n\n\n/*\n * Dump fragmentation table statistics to file.\n *\n * @param f\n * File to dump statistics to\n * @param tbl\n * Fragmentation table to dump statistics from\n */\nvoid\nrte_ip_frag_table_statistics_dump(FILE * f, const struct rte_ip_frag_tbl *tbl);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_IP_FRAG_H_ */\n" }, { "path": "lib/librte_ip_frag/rte_ip_frag_common.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n\n#include \"ip_frag_common.h\"\n\n#define\tIP_FRAG_HASH_FNUM\t2\n\n/* free mbufs from death row */\nvoid\nrte_ip_frag_free_death_row(struct rte_ip_frag_death_row *dr,\n\t\tuint32_t prefetch)\n{\n\tuint32_t i, k, n;\n\n\tk = RTE_MIN(prefetch, dr->cnt);\n\tn = dr->cnt;\n\n\tfor (i = 0; i != k; i++)\n\t\trte_prefetch0(dr->row[i]);\n\n\tfor (i = 0; i != n - k; i++) {\n\t\trte_prefetch0(dr->row[i + k]);\n\t\trte_pktmbuf_free(dr->row[i]);\n\t}\n\n\tfor (; i != n; i++)\n\t\trte_pktmbuf_free(dr->row[i]);\n\n\tdr->cnt = 0;\n}\n\n/* create fragmentation table */\nstruct rte_ip_frag_tbl *\nrte_ip_frag_table_create(uint32_t bucket_num, uint32_t bucket_entries,\n\tuint32_t max_entries, uint64_t max_cycles, int socket_id)\n{\n\tstruct rte_ip_frag_tbl *tbl;\n\tsize_t sz;\n\tuint64_t nb_entries;\n\n\tnb_entries = rte_align32pow2(bucket_num);\n\tnb_entries *= bucket_entries;\n\tnb_entries *= IP_FRAG_HASH_FNUM;\n\n\t/* check input parameters. */\n\tif (rte_is_power_of_2(bucket_entries) == 0 ||\n\t\t\tnb_entries > UINT32_MAX || nb_entries == 0 ||\n\t\t\tnb_entries < max_entries) {\n\t\tRTE_LOG(ERR, USER1, \"%s: invalid input parameter\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\tsz = sizeof (*tbl) + nb_entries * sizeof (tbl->pkt[0]);\n\tif ((tbl = rte_zmalloc_socket(__func__, sz, RTE_CACHE_LINE_SIZE,\n\t\t\tsocket_id)) == NULL) {\n\t\tRTE_LOG(ERR, USER1,\n\t\t\t\"%s: allocation of %zu bytes at socket %d failed do\\n\",\n\t\t\t__func__, sz, socket_id);\n\t\treturn NULL;\n\t}\n\n\tRTE_LOG(INFO, USER1, \"%s: allocated of %zu bytes at socket %d\\n\",\n\t\t__func__, sz, socket_id);\n\n\ttbl->max_cycles = max_cycles;\n\ttbl->max_entries = max_entries;\n\ttbl->nb_entries = (uint32_t)nb_entries;\n\ttbl->nb_buckets = bucket_num;\n\ttbl->bucket_entries = bucket_entries;\n\ttbl->entry_mask = (tbl->nb_entries - 1) & ~(tbl->bucket_entries - 1);\n\n\tTAILQ_INIT(&(tbl->lru));\n\treturn tbl;\n}\n\n/* dump frag table statistics to file */\nvoid\nrte_ip_frag_table_statistics_dump(FILE *f, const struct rte_ip_frag_tbl *tbl)\n{\n\tuint64_t fail_total, fail_nospace;\n\n\tfail_total = tbl->stat.fail_total;\n\tfail_nospace = tbl->stat.fail_nospace;\n\n\tfprintf(f, \"max entries:\\t%u;\\n\"\n\t\t\"entries in use:\\t%u;\\n\"\n\t\t\"finds/inserts:\\t%\" PRIu64 \";\\n\"\n\t\t\"entries added:\\t%\" PRIu64 \";\\n\"\n\t\t\"entries deleted by timeout:\\t%\" PRIu64 \";\\n\"\n\t\t\"entries reused by timeout:\\t%\" PRIu64 \";\\n\"\n\t\t\"total add failures:\\t%\" PRIu64 \";\\n\"\n\t\t\"add no-space failures:\\t%\" PRIu64 \";\\n\"\n\t\t\"add hash-collisions failures:\\t%\" PRIu64 \";\\n\",\n\t\ttbl->max_entries,\n\t\ttbl->use_entries,\n\t\ttbl->stat.find_num,\n\t\ttbl->stat.add_num,\n\t\ttbl->stat.del_num,\n\t\ttbl->stat.reuse_num,\n\t\tfail_total,\n\t\tfail_nospace,\n\t\tfail_total - fail_nospace);\n}\n" }, { "path": "lib/librte_ip_frag/rte_ipv4_fragmentation.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n\n#include \"ip_frag_common.h\"\n\n/* Fragment Offset */\n#define\tIPV4_HDR_DF_SHIFT\t\t\t14\n#define\tIPV4_HDR_MF_SHIFT\t\t\t13\n#define\tIPV4_HDR_FO_SHIFT\t\t\t3\n\n#define\tIPV4_HDR_DF_MASK\t\t\t(1 << IPV4_HDR_DF_SHIFT)\n#define\tIPV4_HDR_MF_MASK\t\t\t(1 << IPV4_HDR_MF_SHIFT)\n\n#define\tIPV4_HDR_FO_MASK\t\t\t((1 << IPV4_HDR_FO_SHIFT) - 1)\n\nstatic inline void __fill_ipv4hdr_frag(struct ipv4_hdr *dst,\n\t\tconst struct ipv4_hdr *src, uint16_t len, uint16_t fofs,\n\t\tuint16_t dofs, uint32_t mf)\n{\n\trte_memcpy(dst, src, sizeof(*dst));\n\tfofs = (uint16_t)(fofs + (dofs >> IPV4_HDR_FO_SHIFT));\n\tfofs = (uint16_t)(fofs | mf << IPV4_HDR_MF_SHIFT);\n\tdst->fragment_offset = rte_cpu_to_be_16(fofs);\n\tdst->total_length = rte_cpu_to_be_16(len);\n\tdst->hdr_checksum = 0;\n}\n\nstatic inline void __free_fragments(struct rte_mbuf *mb[], uint32_t num)\n{\n\tuint32_t i;\n\tfor (i = 0; i != num; i++)\n\t\trte_pktmbuf_free(mb[i]);\n}\n\n/**\n * IPv4 fragmentation.\n *\n * This function implements the fragmentation of IPv4 packets.\n *\n * @param pkt_in\n * The input packet.\n * @param pkts_out\n * Array storing the output fragments.\n * @param mtu_size\n * Size in bytes of the Maximum Transfer Unit (MTU) for the outgoing IPv4\n * datagrams. This value includes the size of the IPv4 header.\n * @param pool_direct\n * MBUF pool used for allocating direct buffers for the output fragments.\n * @param pool_indirect\n * MBUF pool used for allocating indirect buffers for the output fragments.\n * @return\n * Upon successful completion - number of output fragments placed\n * in the pkts_out array.\n * Otherwise - (-1) * .\n */\nint32_t\nrte_ipv4_fragment_packet(struct rte_mbuf *pkt_in,\n\tstruct rte_mbuf **pkts_out,\n\tuint16_t nb_pkts_out,\n\tuint16_t mtu_size,\n\tstruct rte_mempool *pool_direct,\n\tstruct rte_mempool *pool_indirect)\n{\n\tstruct rte_mbuf *in_seg = NULL;\n\tstruct ipv4_hdr *in_hdr;\n\tuint32_t out_pkt_pos, in_seg_data_pos;\n\tuint32_t more_in_segs;\n\tuint16_t fragment_offset, flag_offset, frag_size;\n\n\tfrag_size = (uint16_t)(mtu_size - sizeof(struct ipv4_hdr));\n\n\t/* Fragment size should be a multiply of 8. */\n\tIP_FRAG_ASSERT((frag_size & IPV4_HDR_FO_MASK) == 0);\n\n\tin_hdr = rte_pktmbuf_mtod(pkt_in, struct ipv4_hdr *);\n\tflag_offset = rte_cpu_to_be_16(in_hdr->fragment_offset);\n\n\t/* If Don't Fragment flag is set */\n\tif (unlikely ((flag_offset & IPV4_HDR_DF_MASK) != 0))\n\t\treturn -ENOTSUP;\n\n\t/* Check that pkts_out is big enough to hold all fragments */\n\tif (unlikely(frag_size * nb_pkts_out <\n\t (uint16_t)(pkt_in->pkt_len - sizeof (struct ipv4_hdr))))\n\t\treturn -EINVAL;\n\n\tin_seg = pkt_in;\n\tin_seg_data_pos = sizeof(struct ipv4_hdr);\n\tout_pkt_pos = 0;\n\tfragment_offset = 0;\n\n\tmore_in_segs = 1;\n\twhile (likely(more_in_segs)) {\n\t\tstruct rte_mbuf *out_pkt = NULL, *out_seg_prev = NULL;\n\t\tuint32_t more_out_segs;\n\t\tstruct ipv4_hdr *out_hdr;\n\n\t\t/* Allocate direct buffer */\n\t\tout_pkt = rte_pktmbuf_alloc(pool_direct);\n\t\tif (unlikely(out_pkt == NULL)) {\n\t\t\t__free_fragments(pkts_out, out_pkt_pos);\n\t\t\treturn -ENOMEM;\n\t\t}\n\n\t\t/* Reserve space for the IP header that will be built later */\n\t\tout_pkt->data_len = sizeof(struct ipv4_hdr);\n\t\tout_pkt->pkt_len = sizeof(struct ipv4_hdr);\n\n\t\tout_seg_prev = out_pkt;\n\t\tmore_out_segs = 1;\n\t\twhile (likely(more_out_segs && more_in_segs)) {\n\t\t\tstruct rte_mbuf *out_seg = NULL;\n\t\t\tuint32_t len;\n\n\t\t\t/* Allocate indirect buffer */\n\t\t\tout_seg = rte_pktmbuf_alloc(pool_indirect);\n\t\t\tif (unlikely(out_seg == NULL)) {\n\t\t\t\trte_pktmbuf_free(out_pkt);\n\t\t\t\t__free_fragments(pkts_out, out_pkt_pos);\n\t\t\t\treturn -ENOMEM;\n\t\t\t}\n\t\t\tout_seg_prev->next = out_seg;\n\t\t\tout_seg_prev = out_seg;\n\n\t\t\t/* Prepare indirect buffer */\n\t\t\trte_pktmbuf_attach(out_seg, in_seg);\n\t\t\tlen = mtu_size - out_pkt->pkt_len;\n\t\t\tif (len > (in_seg->data_len - in_seg_data_pos)) {\n\t\t\t\tlen = in_seg->data_len - in_seg_data_pos;\n\t\t\t}\n\t\t\tout_seg->data_off = in_seg->data_off + in_seg_data_pos;\n\t\t\tout_seg->data_len = (uint16_t)len;\n\t\t\tout_pkt->pkt_len = (uint16_t)(len +\n\t\t\t out_pkt->pkt_len);\n\t\t\tout_pkt->nb_segs += 1;\n\t\t\tin_seg_data_pos += len;\n\n\t\t\t/* Current output packet (i.e. fragment) done ? */\n\t\t\tif (unlikely(out_pkt->pkt_len >= mtu_size))\n\t\t\t\tmore_out_segs = 0;\n\n\t\t\t/* Current input segment done ? */\n\t\t\tif (unlikely(in_seg_data_pos == in_seg->data_len)) {\n\t\t\t\tin_seg = in_seg->next;\n\t\t\t\tin_seg_data_pos = 0;\n\n\t\t\t\tif (unlikely(in_seg == NULL))\n\t\t\t\t\tmore_in_segs = 0;\n\t\t\t}\n\t\t}\n\n\t\t/* Build the IP header */\n\n\t\tout_hdr = rte_pktmbuf_mtod(out_pkt, struct ipv4_hdr *);\n\n\t\t__fill_ipv4hdr_frag(out_hdr, in_hdr,\n\t\t (uint16_t)out_pkt->pkt_len,\n\t\t flag_offset, fragment_offset, more_in_segs);\n\n\t\tfragment_offset = (uint16_t)(fragment_offset +\n\t\t out_pkt->pkt_len - sizeof(struct ipv4_hdr));\n\n\t\tout_pkt->ol_flags |= PKT_TX_IP_CKSUM;\n\t\tout_pkt->l3_len = sizeof(struct ipv4_hdr);\n\n\t\t/* Write the fragment to the output list */\n\t\tpkts_out[out_pkt_pos] = out_pkt;\n\t\tout_pkt_pos ++;\n\t}\n\n\treturn out_pkt_pos;\n}\n" }, { "path": "lib/librte_ip_frag/rte_ipv4_reassembly.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n\n#include \"ip_frag_common.h\"\n\n/*\n * Reassemble fragments into one packet.\n */\nstruct rte_mbuf *\nipv4_frag_reassemble(const struct ip_frag_pkt *fp)\n{\n\tstruct ipv4_hdr *ip_hdr;\n\tstruct rte_mbuf *m, *prev;\n\tuint32_t i, n, ofs, first_len;\n\n\tfirst_len = fp->frags[IP_FIRST_FRAG_IDX].len;\n\tn = fp->last_idx - 1;\n\n\t/*start from the last fragment. */\n\tm = fp->frags[IP_LAST_FRAG_IDX].mb;\n\tofs = fp->frags[IP_LAST_FRAG_IDX].ofs;\n\n\twhile (ofs != first_len) {\n\n\t\tprev = m;\n\n\t\tfor (i = n; i != IP_FIRST_FRAG_IDX && ofs != first_len; i--) {\n\n\t\t\t/* previous fragment found. */\n\t\t\tif(fp->frags[i].ofs + fp->frags[i].len == ofs) {\n\n\t\t\t\tip_frag_chain(fp->frags[i].mb, m);\n\n\t\t\t\t/* update our last fragment and offset. */\n\t\t\t\tm = fp->frags[i].mb;\n\t\t\t\tofs = fp->frags[i].ofs;\n\t\t\t}\n\t\t}\n\n\t\t/* error - hole in the packet. */\n\t\tif (m == prev) {\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* chain with the first fragment. */\n\tip_frag_chain(fp->frags[IP_FIRST_FRAG_IDX].mb, m);\n\tm = fp->frags[IP_FIRST_FRAG_IDX].mb;\n\n\t/* update mbuf fields for reassembled packet. */\n\tm->ol_flags |= PKT_TX_IP_CKSUM;\n\n\t/* update ipv4 header for the reassmebled packet */\n\tip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *, m->l2_len);\n\n\tip_hdr->total_length = rte_cpu_to_be_16((uint16_t)(fp->total_size +\n\t\tm->l3_len));\n\tip_hdr->fragment_offset = (uint16_t)(ip_hdr->fragment_offset &\n\t\trte_cpu_to_be_16(IPV4_HDR_DF_FLAG));\n\tip_hdr->hdr_checksum = 0;\n\n\treturn m;\n}\n\n/*\n * Process new mbuf with fragment of IPV4 packet.\n * Incoming mbuf should have it's l2_len/l3_len fields setuped correclty.\n * @param tbl\n * Table where to lookup/add the fragmented packet.\n * @param mb\n * Incoming mbuf with IPV4 fragment.\n * @param tms\n * Fragment arrival timestamp.\n * @param ip_hdr\n * Pointer to the IPV4 header inside the fragment.\n * @return\n * Pointer to mbuf for reassebled packet, or NULL if:\n * - an error occured.\n * - not all fragments of the packet are collected yet.\n */\nstruct rte_mbuf *\nrte_ipv4_frag_reassemble_packet(struct rte_ip_frag_tbl *tbl,\n\t\tstruct rte_ip_frag_death_row *dr, struct rte_mbuf *mb, uint64_t tms,\n\t\tstruct ipv4_hdr *ip_hdr)\n{\n\tstruct ip_frag_pkt *fp;\n\tstruct ip_frag_key key;\n\tconst unaligned_uint64_t *psd;\n\tuint16_t ip_len;\n\tuint16_t flag_offset, ip_ofs, ip_flag;\n\n\tflag_offset = rte_be_to_cpu_16(ip_hdr->fragment_offset);\n\tip_ofs = (uint16_t)(flag_offset & IPV4_HDR_OFFSET_MASK);\n\tip_flag = (uint16_t)(flag_offset & IPV4_HDR_MF_FLAG);\n\n\tpsd = (unaligned_uint64_t *)&ip_hdr->src_addr;\n\t/* use first 8 bytes only */\n\tkey.src_dst[0] = psd[0];\n\tkey.id = ip_hdr->packet_id;\n\tkey.key_len = IPV4_KEYLEN;\n\n\tip_ofs *= IPV4_HDR_OFFSET_UNITS;\n\tip_len = (uint16_t)(rte_be_to_cpu_16(ip_hdr->total_length) -\n\t\tmb->l3_len);\n\n\tIP_FRAG_LOG(DEBUG, \"%s:%d:\\n\"\n\t\t\"mbuf: %p, tms: %\" PRIu64\n\t\t\", key: <%\" PRIx64 \", %#x>, ofs: %u, len: %u, flags: %#x\\n\"\n\t\t\"tbl: %p, max_cycles: %\" PRIu64 \", entry_mask: %#x, \"\n\t\t\"max_entries: %u, use_entries: %u\\n\\n\",\n\t\t__func__, __LINE__,\n\t\tmb, tms, key.src_dst[0], key.id, ip_ofs, ip_len, ip_flag,\n\t\ttbl, tbl->max_cycles, tbl->entry_mask, tbl->max_entries,\n\t\ttbl->use_entries);\n\n\t/* try to find/add entry into the fragment's table. */\n\tif ((fp = ip_frag_find(tbl, dr, &key, tms)) == NULL) {\n\t\tIP_FRAG_MBUF2DR(dr, mb);\n\t\treturn NULL;\n\t}\n\n\tIP_FRAG_LOG(DEBUG, \"%s:%d:\\n\"\n\t\t\"tbl: %p, max_entries: %u, use_entries: %u\\n\"\n\t\t\"ipv4_frag_pkt: %p, key: <%\" PRIx64 \", %#x>, start: %\" PRIu64\n\t\t\", total_size: %u, frag_size: %u, last_idx: %u\\n\\n\",\n\t\t__func__, __LINE__,\n\t\ttbl, tbl->max_entries, tbl->use_entries,\n\t\tfp, fp->key.src_dst[0], fp->key.id, fp->start,\n\t\tfp->total_size, fp->frag_size, fp->last_idx);\n\n\n\t/* process the fragmented packet. */\n\tmb = ip_frag_process(fp, dr, mb, ip_ofs, ip_len, ip_flag);\n\tip_frag_inuse(tbl, fp);\n\n\tIP_FRAG_LOG(DEBUG, \"%s:%d:\\n\"\n\t\t\"mbuf: %p\\n\"\n\t\t\"tbl: %p, max_entries: %u, use_entries: %u\\n\"\n\t\t\"ipv4_frag_pkt: %p, key: <%\" PRIx64 \", %#x>, start: %\" PRIu64\n\t\t\", total_size: %u, frag_size: %u, last_idx: %u\\n\\n\",\n\t\t__func__, __LINE__, mb,\n\t\ttbl, tbl->max_entries, tbl->use_entries,\n\t\tfp, fp->key.src_dst[0], fp->key.id, fp->start,\n\t\tfp->total_size, fp->frag_size, fp->last_idx);\n\n\treturn mb;\n}\n" }, { "path": "lib/librte_ip_frag/rte_ipv6_fragmentation.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n\n#include \"ip_frag_common.h\"\n\n/**\n * @file\n * RTE IPv6 Fragmentation\n *\n * Implementation of IPv6 fragmentation.\n *\n */\n\n/* Fragment Extension Header */\n#define\tIPV6_HDR_MF_SHIFT\t\t\t0\n#define\tIPV6_HDR_FO_SHIFT\t\t\t3\n#define\tIPV6_HDR_MF_MASK\t\t\t(1 << IPV6_HDR_MF_SHIFT)\n#define\tIPV6_HDR_FO_MASK\t\t\t((1 << IPV6_HDR_FO_SHIFT) - 1)\n\nstatic inline void\n__fill_ipv6hdr_frag(struct ipv6_hdr *dst,\n\t\tconst struct ipv6_hdr *src, uint16_t len, uint16_t fofs,\n\t\tuint32_t mf)\n{\n\tstruct ipv6_extension_fragment *fh;\n\n\trte_memcpy(dst, src, sizeof(*dst));\n\tdst->payload_len = rte_cpu_to_be_16(len);\n\tdst->proto = IPPROTO_FRAGMENT;\n\n\tfh = (struct ipv6_extension_fragment *) ++dst;\n\tfh->next_header = src->proto;\n\tfh->reserved1 = 0;\n\tfh->frag_offset = rte_cpu_to_be_16(fofs);\n\tfh->reserved2 = 0;\n\tfh->more_frags = rte_cpu_to_be_16(mf);\n\tfh->id = 0;\n}\n\nstatic inline void\n__free_fragments(struct rte_mbuf *mb[], uint32_t num)\n{\n\tuint32_t i;\n\tfor (i = 0; i < num; i++)\n\t\trte_pktmbuf_free(mb[i]);\n}\n\n/**\n * IPv6 fragmentation.\n *\n * This function implements the fragmentation of IPv6 packets.\n *\n * @param pkt_in\n * The input packet.\n * @param pkts_out\n * Array storing the output fragments.\n * @param mtu_size\n * Size in bytes of the Maximum Transfer Unit (MTU) for the outgoing IPv6\n * datagrams. This value includes the size of the IPv6 header.\n * @param pool_direct\n * MBUF pool used for allocating direct buffers for the output fragments.\n * @param pool_indirect\n * MBUF pool used for allocating indirect buffers for the output fragments.\n * @return\n * Upon successful completion - number of output fragments placed\n * in the pkts_out array.\n * Otherwise - (-1) * .\n */\nint32_t\nrte_ipv6_fragment_packet(struct rte_mbuf *pkt_in,\n\tstruct rte_mbuf **pkts_out,\n\tuint16_t nb_pkts_out,\n\tuint16_t mtu_size,\n\tstruct rte_mempool *pool_direct,\n\tstruct rte_mempool *pool_indirect)\n{\n\tstruct rte_mbuf *in_seg = NULL;\n\tstruct ipv6_hdr *in_hdr;\n\tuint32_t out_pkt_pos, in_seg_data_pos;\n\tuint32_t more_in_segs;\n\tuint16_t fragment_offset, frag_size;\n\n\tfrag_size = (uint16_t)(mtu_size - sizeof(struct ipv6_hdr));\n\n\t/* Fragment size should be a multiple of 8. */\n\tIP_FRAG_ASSERT((frag_size & IPV6_HDR_FO_MASK) == 0);\n\n\t/* Check that pkts_out is big enough to hold all fragments */\n\tif (unlikely (frag_size * nb_pkts_out <\n\t (uint16_t)(pkt_in->pkt_len - sizeof (struct ipv6_hdr))))\n\t\treturn -EINVAL;\n\n\tin_hdr = rte_pktmbuf_mtod(pkt_in, struct ipv6_hdr *);\n\n\tin_seg = pkt_in;\n\tin_seg_data_pos = sizeof(struct ipv6_hdr);\n\tout_pkt_pos = 0;\n\tfragment_offset = 0;\n\n\tmore_in_segs = 1;\n\twhile (likely(more_in_segs)) {\n\t\tstruct rte_mbuf *out_pkt = NULL, *out_seg_prev = NULL;\n\t\tuint32_t more_out_segs;\n\t\tstruct ipv6_hdr *out_hdr;\n\n\t\t/* Allocate direct buffer */\n\t\tout_pkt = rte_pktmbuf_alloc(pool_direct);\n\t\tif (unlikely(out_pkt == NULL)) {\n\t\t\t__free_fragments(pkts_out, out_pkt_pos);\n\t\t\treturn -ENOMEM;\n\t\t}\n\n\t\t/* Reserve space for the IP header that will be built later */\n\t\tout_pkt->data_len = sizeof(struct ipv6_hdr) + sizeof(struct ipv6_extension_fragment);\n\t\tout_pkt->pkt_len = sizeof(struct ipv6_hdr) + sizeof(struct ipv6_extension_fragment);\n\n\t\tout_seg_prev = out_pkt;\n\t\tmore_out_segs = 1;\n\t\twhile (likely(more_out_segs && more_in_segs)) {\n\t\t\tstruct rte_mbuf *out_seg = NULL;\n\t\t\tuint32_t len;\n\n\t\t\t/* Allocate indirect buffer */\n\t\t\tout_seg = rte_pktmbuf_alloc(pool_indirect);\n\t\t\tif (unlikely(out_seg == NULL)) {\n\t\t\t\trte_pktmbuf_free(out_pkt);\n\t\t\t\t__free_fragments(pkts_out, out_pkt_pos);\n\t\t\t\treturn -ENOMEM;\n\t\t\t}\n\t\t\tout_seg_prev->next = out_seg;\n\t\t\tout_seg_prev = out_seg;\n\n\t\t\t/* Prepare indirect buffer */\n\t\t\trte_pktmbuf_attach(out_seg, in_seg);\n\t\t\tlen = mtu_size - out_pkt->pkt_len;\n\t\t\tif (len > (in_seg->data_len - in_seg_data_pos)) {\n\t\t\t\tlen = in_seg->data_len - in_seg_data_pos;\n\t\t\t}\n\t\t\tout_seg->data_off = in_seg->data_off + in_seg_data_pos;\n\t\t\tout_seg->data_len = (uint16_t)len;\n\t\t\tout_pkt->pkt_len = (uint16_t)(len +\n\t\t\t out_pkt->pkt_len);\n\t\t\tout_pkt->nb_segs += 1;\n\t\t\tin_seg_data_pos += len;\n\n\t\t\t/* Current output packet (i.e. fragment) done ? */\n\t\t\tif (unlikely(out_pkt->pkt_len >= mtu_size)) {\n\t\t\t\tmore_out_segs = 0;\n\t\t\t}\n\n\t\t\t/* Current input segment done ? */\n\t\t\tif (unlikely(in_seg_data_pos == in_seg->data_len)) {\n\t\t\t\tin_seg = in_seg->next;\n\t\t\t\tin_seg_data_pos = 0;\n\n\t\t\t\tif (unlikely(in_seg == NULL)) {\n\t\t\t\t\tmore_in_segs = 0;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* Build the IP header */\n\n\t\tout_hdr = rte_pktmbuf_mtod(out_pkt, struct ipv6_hdr *);\n\n\t\t__fill_ipv6hdr_frag(out_hdr, in_hdr,\n\t\t (uint16_t) out_pkt->pkt_len - sizeof(struct ipv6_hdr),\n\t\t fragment_offset, more_in_segs);\n\n\t\tfragment_offset = (uint16_t)(fragment_offset +\n\t\t out_pkt->pkt_len - sizeof(struct ipv6_hdr)\n\t\t\t- sizeof(struct ipv6_extension_fragment));\n\n\t\t/* Write the fragment to the output list */\n\t\tpkts_out[out_pkt_pos] = out_pkt;\n\t\tout_pkt_pos ++;\n\t}\n\n\treturn out_pkt_pos;\n}\n" }, { "path": "lib/librte_ip_frag/rte_ipv6_reassembly.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n\n#include \"ip_frag_common.h\"\n\n/**\n * @file\n * IPv6 reassemble\n *\n * Implementation of IPv6 reassembly.\n *\n */\n\nstatic inline void\nip_frag_memmove(char *dst, char *src, int len)\n{\n\tint i;\n\n\t/* go backwards to make sure we don't overwrite anything important */\n\tfor (i = len - 1; i >= 0; i--)\n\t\tdst[i] = src[i];\n}\n\n/*\n * Reassemble fragments into one packet.\n */\nstruct rte_mbuf *\nipv6_frag_reassemble(const struct ip_frag_pkt *fp)\n{\n\tstruct ipv6_hdr *ip_hdr;\n\tstruct ipv6_extension_fragment *frag_hdr;\n\tstruct rte_mbuf *m, *prev;\n\tuint32_t i, n, ofs, first_len;\n\tuint32_t last_len, move_len, payload_len;\n\n\tfirst_len = fp->frags[IP_FIRST_FRAG_IDX].len;\n\tn = fp->last_idx - 1;\n\n\t/*start from the last fragment. */\n\tm = fp->frags[IP_LAST_FRAG_IDX].mb;\n\tofs = fp->frags[IP_LAST_FRAG_IDX].ofs;\n\tlast_len = fp->frags[IP_LAST_FRAG_IDX].len;\n\n\tpayload_len = ofs + last_len;\n\n\twhile (ofs != first_len) {\n\n\t\tprev = m;\n\n\t\tfor (i = n; i != IP_FIRST_FRAG_IDX && ofs != first_len; i--) {\n\n\t\t\t/* previous fragment found. */\n\t\t\tif (fp->frags[i].ofs + fp->frags[i].len == ofs) {\n\n\t\t\t\tip_frag_chain(fp->frags[i].mb, m);\n\n\t\t\t\t/* update our last fragment and offset. */\n\t\t\t\tm = fp->frags[i].mb;\n\t\t\t\tofs = fp->frags[i].ofs;\n\t\t\t}\n\t\t}\n\n\t\t/* error - hole in the packet. */\n\t\tif (m == prev) {\n\t\t\treturn NULL;\n\t\t}\n\t}\n\n\t/* chain with the first fragment. */\n\tip_frag_chain(fp->frags[IP_FIRST_FRAG_IDX].mb, m);\n\tm = fp->frags[IP_FIRST_FRAG_IDX].mb;\n\n\t/* update mbuf fields for reassembled packet. */\n\tm->ol_flags |= PKT_TX_IP_CKSUM;\n\n\t/* update ipv6 header for the reassembled datagram */\n\tip_hdr = rte_pktmbuf_mtod_offset(m, struct ipv6_hdr *, m->l2_len);\n\n\tip_hdr->payload_len = rte_cpu_to_be_16(payload_len);\n\n\t/*\n\t * remove fragmentation header. note that per RFC2460, we need to update\n\t * the last non-fragmentable header with the \"next header\" field to contain\n\t * type of the first fragmentable header, but we currently don't support\n\t * other headers, so we assume there are no other headers and thus update\n\t * the main IPv6 header instead.\n\t */\n\tmove_len = m->l2_len + m->l3_len - sizeof(*frag_hdr);\n\tfrag_hdr = (struct ipv6_extension_fragment *) (ip_hdr + 1);\n\tip_hdr->proto = frag_hdr->next_header;\n\n\tip_frag_memmove(rte_pktmbuf_mtod_offset(m, char *, sizeof(*frag_hdr)),\n\t\t\trte_pktmbuf_mtod(m, char*), move_len);\n\n\trte_pktmbuf_adj(m, sizeof(*frag_hdr));\n\n\treturn m;\n}\n\n/*\n * Process new mbuf with fragment of IPV6 datagram.\n * Incoming mbuf should have its l2_len/l3_len fields setup correctly.\n * @param tbl\n * Table where to lookup/add the fragmented packet.\n * @param mb\n * Incoming mbuf with IPV6 fragment.\n * @param tms\n * Fragment arrival timestamp.\n * @param ip_hdr\n * Pointer to the IPV6 header.\n * @param frag_hdr\n * Pointer to the IPV6 fragment extension header.\n * @return\n * Pointer to mbuf for reassembled packet, or NULL if:\n * - an error occured.\n * - not all fragments of the packet are collected yet.\n */\n#define MORE_FRAGS(x) (((x) & 0x100) >> 8)\n#define FRAG_OFFSET(x) (rte_cpu_to_be_16(x) >> 3)\nstruct rte_mbuf *\nrte_ipv6_frag_reassemble_packet(struct rte_ip_frag_tbl *tbl,\n\t\tstruct rte_ip_frag_death_row *dr, struct rte_mbuf *mb, uint64_t tms,\n\t\tstruct ipv6_hdr *ip_hdr, struct ipv6_extension_fragment *frag_hdr)\n{\n\tstruct ip_frag_pkt *fp;\n\tstruct ip_frag_key key;\n\tuint16_t ip_len, ip_ofs;\n\n\trte_memcpy(&key.src_dst[0], ip_hdr->src_addr, 16);\n\trte_memcpy(&key.src_dst[2], ip_hdr->dst_addr, 16);\n\n\tkey.id = frag_hdr->id;\n\tkey.key_len = IPV6_KEYLEN;\n\n\tip_ofs = FRAG_OFFSET(frag_hdr->frag_data) * 8;\n\n\t/*\n\t * as per RFC2460, payload length contains all extension headers as well.\n\t * since we don't support anything but frag headers, this is what we remove\n\t * from the payload len.\n\t */\n\tip_len = rte_be_to_cpu_16(ip_hdr->payload_len) - sizeof(*frag_hdr);\n\n\tIP_FRAG_LOG(DEBUG, \"%s:%d:\\n\"\n\t\t\"mbuf: %p, tms: %\" PRIu64\n\t\t\", key: <\" IPv6_KEY_BYTES_FMT \", %#x>, ofs: %u, len: %u, flags: %#x\\n\"\n\t\t\"tbl: %p, max_cycles: %\" PRIu64 \", entry_mask: %#x, \"\n\t\t\"max_entries: %u, use_entries: %u\\n\\n\",\n\t\t__func__, __LINE__,\n\t\tmb, tms, IPv6_KEY_BYTES(key.src_dst), key.id, ip_ofs, ip_len, frag_hdr->more_frags,\n\t\ttbl, tbl->max_cycles, tbl->entry_mask, tbl->max_entries,\n\t\ttbl->use_entries);\n\n\t/* try to find/add entry into the fragment's table. */\n\tfp = ip_frag_find(tbl, dr, &key, tms);\n\tif (fp == NULL) {\n\t\tIP_FRAG_MBUF2DR(dr, mb);\n\t\treturn NULL;\n\t}\n\n\tIP_FRAG_LOG(DEBUG, \"%s:%d:\\n\"\n\t\t\"tbl: %p, max_entries: %u, use_entries: %u\\n\"\n\t\t\"ipv6_frag_pkt: %p, key: <\" IPv6_KEY_BYTES_FMT \", %#x>, start: %\" PRIu64\n\t\t\", total_size: %u, frag_size: %u, last_idx: %u\\n\\n\",\n\t\t__func__, __LINE__,\n\t\ttbl, tbl->max_entries, tbl->use_entries,\n\t\tfp, IPv6_KEY_BYTES(fp->key.src_dst), fp->key.id, fp->start,\n\t\tfp->total_size, fp->frag_size, fp->last_idx);\n\n\n\t/* process the fragmented packet. */\n\tmb = ip_frag_process(fp, dr, mb, ip_ofs, ip_len,\n\t\t\tMORE_FRAGS(frag_hdr->frag_data));\n\tip_frag_inuse(tbl, fp);\n\n\tIP_FRAG_LOG(DEBUG, \"%s:%d:\\n\"\n\t\t\"mbuf: %p\\n\"\n\t\t\"tbl: %p, max_entries: %u, use_entries: %u\\n\"\n\t\t\"ipv6_frag_pkt: %p, key: <\" IPv6_KEY_BYTES_FMT \", %#x>, start: %\" PRIu64\n\t\t\", total_size: %u, frag_size: %u, last_idx: %u\\n\\n\",\n\t\t__func__, __LINE__, mb,\n\t\ttbl, tbl->max_entries, tbl->use_entries,\n\t\tfp, IPv6_KEY_BYTES(fp->key.src_dst), fp->key.id, fp->start,\n\t\tfp->total_size, fp->frag_size, fp->last_idx);\n\n\treturn mb;\n}\n" }, { "path": "lib/librte_ivshmem/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_ivshmem.a\n\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3\n\nEXPORT_MAP := rte_ivshmem_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_IVSHMEM) := rte_ivshmem.c\n\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_IVSHMEM)-include := rte_ivshmem.h\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_IVSHMEM) += lib/librte_mempool\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_ivshmem/rte_ivshmem.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_ivshmem.h\"\n\n#define IVSHMEM_CONFIG_FILE_FMT \"/var/run/.dpdk_ivshmem_metadata_%s\"\n#define IVSHMEM_QEMU_CMD_LINE_HEADER_FMT \"-device ivshmem,size=%\" PRIu64 \"M,shm=fd%s\"\n#define IVSHMEM_QEMU_CMD_FD_FMT \":%s:0x%\" PRIx64 \":0x%\" PRIx64\n#define IVSHMEM_QEMU_CMDLINE_BUFSIZE 1024\n#define IVSHMEM_MAX_PAGES (1 << 12)\n#define adjacent(x,y) (((x).phys_addr+(x).len)==(y).phys_addr)\n#define METADATA_SIZE_ALIGNED \\\n\t(RTE_ALIGN_CEIL(sizeof(struct rte_ivshmem_metadata),pagesz))\n\n#define GET_PAGEMAP_ADDR(in,addr,dlm,err) \\\n{ \\\n\tchar *end; \\\n\terrno = 0; \\\n\taddr = strtoull((in), &end, 16); \\\n\tif (errno != 0 || *end != (dlm)) { \\\n\t\tRTE_LOG(ERR, EAL, err); \\\n\t\tgoto error; \\\n\t} \\\n\t(in) = end + 1; \\\n}\n\nstatic int pagesz;\n\nstruct memseg_cache_entry {\n\tchar filepath[PATH_MAX];\n\tuint64_t offset;\n\tuint64_t len;\n};\n\nstruct ivshmem_config {\n\tstruct rte_ivshmem_metadata * metadata;\n\tstruct memseg_cache_entry memseg_cache[IVSHMEM_MAX_PAGES];\n\t\t/**< account for multiple files per segment case */\n\tstruct flock lock;\n\trte_spinlock_t sl;\n};\n\nstatic struct ivshmem_config\nivshmem_global_config[RTE_LIBRTE_IVSHMEM_MAX_METADATA_FILES];\n\nstatic rte_spinlock_t global_cfg_sl;\n\nstatic struct ivshmem_config *\nget_config_by_name(const char * name)\n{\n\tstruct rte_ivshmem_metadata * config;\n\tunsigned i;\n\n\tfor (i = 0; i < RTE_DIM(ivshmem_global_config); i++) {\n\t\tconfig = ivshmem_global_config[i].metadata;\n\t\tif (config == NULL)\n\t\t\treturn NULL;\n\t\tif (strncmp(name, config->name, IVSHMEM_NAME_LEN) == 0)\n\t\t\treturn &ivshmem_global_config[i];\n\t}\n\n\treturn NULL;\n}\n\nstatic int\noverlap(const struct rte_memzone * s1, const struct rte_memzone * s2)\n{\n\tuint64_t start1, end1, start2, end2;\n\n\tstart1 = s1->addr_64;\n\tend1 = s1->addr_64 + s1->len;\n\tstart2 = s2->addr_64;\n\tend2 = s2->addr_64 + s2->len;\n\n\tif (start1 >= start2 && start1 < end2)\n\t\treturn 1;\n\tif (start2 >= start1 && start2 < end1)\n\t\treturn 1;\n\n\treturn 0;\n}\n\nstatic struct rte_memzone *\nget_memzone_by_addr(const void * addr)\n{\n\tstruct rte_memzone * tmp, * mz;\n\tstruct rte_mem_config * mcfg;\n\tint i;\n\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\tmz = NULL;\n\n\t/* find memzone for the ring */\n\tfor (i = 0; i < RTE_MAX_MEMZONE; i++) {\n\t\ttmp = &mcfg->memzone[i];\n\n\t\tif (tmp->addr_64 == (uint64_t) addr) {\n\t\t\tmz = tmp;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn mz;\n}\n\nstatic int\nentry_compare(const void * a, const void * b)\n{\n\tconst struct rte_ivshmem_metadata_entry * e1 =\n\t\t\t(const struct rte_ivshmem_metadata_entry*) a;\n\tconst struct rte_ivshmem_metadata_entry * e2 =\n\t\t\t(const struct rte_ivshmem_metadata_entry*) b;\n\n\t/* move unallocated zones to the end */\n\tif (e1->mz.addr == NULL && e2->mz.addr == NULL)\n\t\treturn 0;\n\tif (e1->mz.addr == 0)\n\t\treturn 1;\n\tif (e2->mz.addr == 0)\n\t\treturn -1;\n\n\treturn e1->mz.phys_addr > e2->mz.phys_addr;\n}\n\n/* fills hugepage cache entry for a given start virt_addr */\nstatic int\nget_hugefile_by_virt_addr(uint64_t virt_addr, struct memseg_cache_entry * e)\n{\n\tuint64_t start_addr, end_addr;\n\tchar *start,*path_end;\n\tchar buf[PATH_MAX*2];\n\tFILE *f;\n\n\tstart = NULL;\n\tpath_end = NULL;\n\tstart_addr = 0;\n\n\tmemset(e->filepath, 0, sizeof(e->filepath));\n\n\t/* open /proc/self/maps */\n\tf = fopen(\"/proc/self/maps\", \"r\");\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"cannot open /proc/self/maps!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* parse maps */\n\twhile (fgets(buf, sizeof(buf), f) != NULL) {\n\n\t\t/* get endptr to end of start addr */\n\t\tstart = buf;\n\n\t\tGET_PAGEMAP_ADDR(start,start_addr,'-',\n\t\t\t\t\"Cannot find start address in maps!\\n\");\n\n\t\t/* if start address is bigger than our address, skip */\n\t\tif (start_addr > virt_addr)\n\t\t\tcontinue;\n\n\t\tGET_PAGEMAP_ADDR(start,end_addr,' ',\n\t\t\t\t\"Cannot find end address in maps!\\n\");\n\n\t\t/* if end address is less than our address, skip */\n\t\tif (end_addr <= virt_addr)\n\t\t\tcontinue;\n\n\t\t/* find where the path starts */\n\t\tstart = strstr(start, \"/\");\n\n\t\tif (start == NULL)\n\t\t\tcontinue;\n\n\t\t/* at this point, we know that this is our map.\n\t\t * now let's find the file */\n\t\tpath_end = strstr(start, \"\\n\");\n\t\tbreak;\n\t}\n\n\tif (path_end == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Hugefile path not found!\\n\");\n\t\tgoto error;\n\t}\n\n\t/* calculate offset and copy the file path */\n\tsnprintf(e->filepath, RTE_PTR_DIFF(path_end, start) + 1, \"%s\", start);\n\n\te->offset = virt_addr - start_addr;\n\n\tfclose(f);\n\n\treturn 0;\nerror:\n\tfclose(f);\n\treturn -1;\n}\n\n/*\n * This is a complex function. What it does is the following:\n * 1. Goes through metadata and gets list of hugepages involved\n * 2. Sorts the hugepages by size (1G first)\n * 3. Goes through metadata again and writes correct offsets\n * 4. Goes through pages and finds out their filenames, offsets etc.\n */\nstatic int\nbuild_config(struct rte_ivshmem_metadata * metadata)\n{\n\tstruct rte_ivshmem_metadata_entry * e_local;\n\tstruct memseg_cache_entry * ms_local;\n\tstruct rte_memseg pages[IVSHMEM_MAX_PAGES];\n\tstruct rte_ivshmem_metadata_entry *entry;\n\tstruct memseg_cache_entry * c_entry, * prev_entry;\n\tstruct ivshmem_config * config;\n\tunsigned i, j, mz_iter, ms_iter;\n\tuint64_t biggest_len;\n\tint biggest_idx;\n\n\t/* return error if we try to use an unknown config file */\n\tconfig = get_config_by_name(metadata->name);\n\tif (config == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot find IVSHMEM config %s!\\n\", metadata->name);\n\t\tgoto fail_e;\n\t}\n\n\tmemset(pages, 0, sizeof(pages));\n\n\te_local = malloc(sizeof(config->metadata->entry));\n\tif (e_local == NULL)\n\t\tgoto fail_e;\n\tms_local = malloc(sizeof(config->memseg_cache));\n\tif (ms_local == NULL)\n\t\tgoto fail_ms;\n\n\n\t/* make local copies before doing anything */\n\tmemcpy(e_local, config->metadata->entry, sizeof(config->metadata->entry));\n\tmemcpy(ms_local, config->memseg_cache, sizeof(config->memseg_cache));\n\n\tqsort(e_local, RTE_DIM(config->metadata->entry), sizeof(struct rte_ivshmem_metadata_entry),\n\t\t\tentry_compare);\n\n\t/* first pass - collect all huge pages */\n\tfor (mz_iter = 0; mz_iter < RTE_DIM(config->metadata->entry); mz_iter++) {\n\n\t\tentry = &e_local[mz_iter];\n\n\t\tuint64_t start_addr = RTE_ALIGN_FLOOR(entry->mz.addr_64,\n\t\t\t\tentry->mz.hugepage_sz);\n\t\tuint64_t offset = entry->mz.addr_64 - start_addr;\n\t\tuint64_t len = RTE_ALIGN_CEIL(entry->mz.len + offset,\n\t\t\t\tentry->mz.hugepage_sz);\n\n\t\tif (entry->mz.addr_64 == 0 || start_addr == 0 || len == 0)\n\t\t\tcontinue;\n\n\t\tint start_page;\n\n\t\t/* find first unused page - mz are phys_addr sorted so we don't have to\n\t\t * look out for holes */\n\t\tfor (i = 0; i < RTE_DIM(pages); i++) {\n\n\t\t\t/* skip if we already have this page */\n\t\t\tif (pages[i].addr_64 == start_addr) {\n\t\t\t\tstart_addr += entry->mz.hugepage_sz;\n\t\t\t\tlen -= entry->mz.hugepage_sz;\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t\t/* we found a new page */\n\t\t\telse if (pages[i].addr_64 == 0) {\n\t\t\t\tstart_page = i;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (i == RTE_DIM(pages)) {\n\t\t\tRTE_LOG(ERR, EAL, \"Cannot find unused page!\\n\");\n\t\t\tgoto fail;\n\t\t}\n\n\t\t/* populate however many pages the memzone has */\n\t\tfor (i = start_page; i < RTE_DIM(pages) && len != 0; i++) {\n\n\t\t\tpages[i].addr_64 = start_addr;\n\t\t\tpages[i].len = entry->mz.hugepage_sz;\n\t\t\tstart_addr += entry->mz.hugepage_sz;\n\t\t\tlen -= entry->mz.hugepage_sz;\n\t\t}\n\t\t/* if there's still length left */\n\t\tif (len != 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"Not enough space for pages!\\n\");\n\t\t\tgoto fail;\n\t\t}\n\t}\n\n\t/* second pass - sort pages by size */\n\tfor (i = 0; i < RTE_DIM(pages); i++) {\n\n\t\tif (pages[i].addr == NULL)\n\t\t\tbreak;\n\n\t\tbiggest_len = 0;\n\t\tbiggest_idx = -1;\n\n\t\t/*\n\t\t * browse all entries starting at 'i', and find the\n\t\t * entry with the smallest addr\n\t\t */\n\t\tfor (j=i; j< RTE_DIM(pages); j++) {\n\t\t\tif (pages[j].addr == NULL)\n\t\t\t\t\tbreak;\n\t\t\tif (biggest_len == 0 ||\n\t\t\t\tpages[j].len > biggest_len) {\n\t\t\t\tbiggest_len = pages[j].len;\n\t\t\t\tbiggest_idx = j;\n\t\t\t}\n\t\t}\n\n\t\t/* should not happen */\n\t\tif (biggest_idx == -1) {\n\t\t\tRTE_LOG(ERR, EAL, \"Error sorting by size!\\n\");\n\t\t\tgoto fail;\n\t\t}\n\t\tif (i != (unsigned) biggest_idx) {\n\t\t\tstruct rte_memseg tmp;\n\n\t\t\tmemcpy(&tmp, &pages[biggest_idx], sizeof(struct rte_memseg));\n\n\t\t\t/* we don't want to break contiguousness, so instead of just\n\t\t\t * swapping segments, we move all the preceding segments to the\n\t\t\t * right and then put the old segment @ biggest_idx in place of\n\t\t\t * segment @ i */\n\t\t\tfor (j = biggest_idx - 1; j >= i; j--) {\n\t\t\t\tmemcpy(&pages[j+1], &pages[j], sizeof(struct rte_memseg));\n\t\t\t\tmemset(&pages[j], 0, sizeof(struct rte_memseg));\n\t\t\t\tif (j == 0)\n\t\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t/* put old biggest segment to its new place */\n\t\t\tmemcpy(&pages[i], &tmp, sizeof(struct rte_memseg));\n\t\t}\n\t}\n\n\t/* third pass - write correct offsets */\n\tfor (mz_iter = 0; mz_iter < RTE_DIM(config->metadata->entry); mz_iter++) {\n\n\t\tuint64_t offset = 0;\n\n\t\tentry = &e_local[mz_iter];\n\n\t\tif (entry->mz.addr_64 == 0)\n\t\t\tbreak;\n\n\t\t/* find page for current memzone */\n\t\tfor (i = 0; i < RTE_DIM(pages); i++) {\n\t\t\t/* we found our page */\n\t\t\tif (entry->mz.addr_64 >= pages[i].addr_64 &&\n\t\t\t\t\tentry->mz.addr_64 < pages[i].addr_64 + pages[i].len) {\n\t\t\t\tentry->offset = (entry->mz.addr_64 - pages[i].addr_64) +\n\t\t\t\t\t\toffset;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\toffset += pages[i].len;\n\t\t}\n\t\tif (i == RTE_DIM(pages)) {\n\t\t\tRTE_LOG(ERR, EAL, \"Page not found!\\n\");\n\t\t\tgoto fail;\n\t\t}\n\t}\n\n\tms_iter = 0;\n\tprev_entry = NULL;\n\n\t/* fourth pass - create proper memseg cache */\n\tfor (i = 0; i < RTE_DIM(pages) &&\n\t\t\tms_iter <= RTE_DIM(config->memseg_cache); i++) {\n\t\tif (pages[i].addr_64 == 0)\n\t\t\tbreak;\n\n\n\t\tif (ms_iter == RTE_DIM(pages)) {\n\t\t\tRTE_LOG(ERR, EAL, \"The universe has collapsed!\\n\");\n\t\t\tgoto fail;\n\t\t}\n\n\t\tc_entry = &ms_local[ms_iter];\n\t\tc_entry->len = pages[i].len;\n\n\t\tif (get_hugefile_by_virt_addr(pages[i].addr_64, c_entry) < 0)\n\t\t\tgoto fail;\n\n\t\t/* if previous entry has the same filename and is contiguous,\n\t\t * clear current entry and increase previous entry's length\n\t\t */\n\t\tif (prev_entry != NULL &&\n\t\t\t\tstrncmp(c_entry->filepath, prev_entry->filepath,\n\t\t\t\tsizeof(c_entry->filepath)) == 0 &&\n\t\t\t\tprev_entry->offset + prev_entry->len == c_entry->offset) {\n\t\t\tprev_entry->len += pages[i].len;\n\t\t\tmemset(c_entry, 0, sizeof(struct memseg_cache_entry));\n\t\t}\n\t\telse {\n\t\t\tprev_entry = c_entry;\n\t\t\tms_iter++;\n\t\t}\n\t}\n\n\t/* update current configuration with new valid data */\n\tmemcpy(config->metadata->entry, e_local, sizeof(config->metadata->entry));\n\tmemcpy(config->memseg_cache, ms_local, sizeof(config->memseg_cache));\n\n\tfree(ms_local);\n\tfree(e_local);\n\n\treturn 0;\nfail:\n\tfree(ms_local);\nfail_ms:\n\tfree(e_local);\nfail_e:\n\treturn -1;\n}\n\nstatic int\nadd_memzone_to_metadata(const struct rte_memzone * mz,\n\t\tstruct ivshmem_config * config)\n{\n\tstruct rte_ivshmem_metadata_entry * entry;\n\tunsigned i;\n\n\trte_spinlock_lock(&config->sl);\n\n\t/* find free slot in this config */\n\tfor (i = 0; i < RTE_DIM(config->metadata->entry); i++) {\n\t\tentry = &config->metadata->entry[i];\n\n\t\tif (&entry->mz.addr_64 != 0 && overlap(mz, &entry->mz)) {\n\t\t\tRTE_LOG(ERR, EAL, \"Overlapping memzones!\\n\");\n\t\t\tgoto fail;\n\t\t}\n\n\t\t/* if addr is zero, the memzone is probably free */\n\t\tif (entry->mz.addr_64 == 0) {\n\t\t\tRTE_LOG(DEBUG, EAL, \"Adding memzone '%s' at %p to metadata %s\\n\",\n\t\t\t\t\tmz->name, mz->addr, config->metadata->name);\n\t\t\tmemcpy(&entry->mz, mz, sizeof(struct rte_memzone));\n\n\t\t\t/* run config file parser */\n\t\t\tif (build_config(config->metadata) < 0)\n\t\t\t\tgoto fail;\n\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* if we reached the maximum, that means we have no place in config */\n\tif (i == RTE_DIM(config->metadata->entry)) {\n\t\tRTE_LOG(ERR, EAL, \"No space left in IVSHMEM metadata %s!\\n\",\n\t\t\t\tconfig->metadata->name);\n\t\tgoto fail;\n\t}\n#ifdef RTE_LIBRTE_IVSHMEM\n\tstruct rte_mem_config *mcfg;\n\tunsigned int idx;\n\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\n\trte_rwlock_write_lock(&mcfg->mlock);\n\n\tidx = ((uintptr_t)mz - (uintptr_t)mcfg->memzone);\n\tidx = idx / sizeof(struct rte_memzone);\n\n\t/* mark the memzone not freeable */\n\tmcfg->memzone[idx].ioremap_addr = mz->phys_addr;\n\n\trte_rwlock_write_unlock(&mcfg->mlock);\n#endif\n\trte_spinlock_unlock(&config->sl);\n\treturn 0;\nfail:\n\trte_spinlock_unlock(&config->sl);\n\treturn -1;\n}\n\nstatic int\nadd_ring_to_metadata(const struct rte_ring * r,\n\t\tstruct ivshmem_config * config)\n{\n\tstruct rte_memzone * mz;\n\n\tmz = get_memzone_by_addr(r);\n\n\tif (!mz) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot find memzone for ring!\\n\");\n\t\treturn -1;\n\t}\n\n\treturn add_memzone_to_metadata(mz, config);\n}\n\nstatic int\nadd_mempool_to_metadata(const struct rte_mempool * mp,\n\t\tstruct ivshmem_config * config)\n{\n\tstruct rte_memzone * mz;\n\tint ret;\n\n\tmz = get_memzone_by_addr(mp);\n\tret = 0;\n\n\tif (!mz) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot find memzone for mempool!\\n\");\n\t\treturn -1;\n\t}\n\n\t/* mempool consists of memzone and ring */\n\tret = add_memzone_to_metadata(mz, config);\n\tif (ret < 0)\n\t\treturn -1;\n\n\treturn add_ring_to_metadata(mp->ring, config);\n}\n\nint\nrte_ivshmem_metadata_add_ring(const struct rte_ring * r, const char * name)\n{\n\tstruct ivshmem_config * config;\n\n\tif (name == NULL || r == NULL)\n\t\treturn -1;\n\n\tconfig = get_config_by_name(name);\n\n\tif (config == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot find IVSHMEM config %s!\\n\", name);\n\t\treturn -1;\n\t}\n\n\treturn add_ring_to_metadata(r, config);\n}\n\nint\nrte_ivshmem_metadata_add_memzone(const struct rte_memzone * mz, const char * name)\n{\n\tstruct ivshmem_config * config;\n\n\tif (name == NULL || mz == NULL)\n\t\treturn -1;\n\n\tconfig = get_config_by_name(name);\n\n\tif (config == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot find IVSHMEM config %s!\\n\", name);\n\t\treturn -1;\n\t}\n\n\treturn add_memzone_to_metadata(mz, config);\n}\n\nint\nrte_ivshmem_metadata_add_mempool(const struct rte_mempool * mp, const char * name)\n{\n\tstruct ivshmem_config * config;\n\n\tif (name == NULL || mp == NULL)\n\t\treturn -1;\n\n\tconfig = get_config_by_name(name);\n\n\tif (config == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot find IVSHMEM config %s!\\n\", name);\n\t\treturn -1;\n\t}\n\n\treturn add_mempool_to_metadata(mp, config);\n}\n\nstatic inline void\nivshmem_config_path(char *buffer, size_t bufflen, const char *name)\n{\n\tsnprintf(buffer, bufflen, IVSHMEM_CONFIG_FILE_FMT, name);\n}\n\n\n\nstatic inline\nvoid *ivshmem_metadata_create(const char *name, size_t size,\n\t\tstruct flock *lock)\n{\n\tint retval, fd;\n\tvoid *metadata_addr;\n\tchar pathname[PATH_MAX];\n\n\tivshmem_config_path(pathname, sizeof(pathname), name);\n\n\tfd = open(pathname, O_RDWR | O_CREAT, 0660);\n\tif (fd < 0) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot open '%s'\\n\", pathname);\n\t\treturn NULL;\n\t}\n\n\tsize = METADATA_SIZE_ALIGNED;\n\n\tretval = fcntl(fd, F_SETLK, lock);\n\tif (retval < 0){\n\t\tclose(fd);\n\t\tRTE_LOG(ERR, EAL, \"Cannot create lock on '%s'. Is another \"\n\t\t\t\t\"process using it?\\n\", pathname);\n\t\treturn NULL;\n\t}\n\n\tretval = ftruncate(fd, size);\n\tif (retval < 0){\n\t\tclose(fd);\n\t\tRTE_LOG(ERR, EAL, \"Cannot resize '%s'\\n\", pathname);\n\t\treturn NULL;\n\t}\n\n\tmetadata_addr = mmap(NULL, size,\n\t\t\t\tPROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);\n\n\tif (metadata_addr == MAP_FAILED){\n\t\tRTE_LOG(ERR, EAL, \"Cannot mmap memory for '%s'\\n\", pathname);\n\n\t\t/* we don't care if we can't unlock */\n\t\tfcntl(fd, F_UNLCK, lock);\n\t\tclose(fd);\n\n\t\treturn NULL;\n\t}\n\n\treturn metadata_addr;\n}\n\nint rte_ivshmem_metadata_create(const char *name)\n{\n\tstruct ivshmem_config * ivshmem_config;\n\tunsigned index;\n\n\tif (pagesz == 0)\n\t\tpagesz = getpagesize();\n\n\tif (name == NULL)\n\t\treturn -1;\n\n\trte_spinlock_lock(&global_cfg_sl);\n\n\tfor (index = 0; index < RTE_DIM(ivshmem_global_config); index++) {\n\t\tif (ivshmem_global_config[index].metadata == NULL) {\n\t\t\tivshmem_config = &ivshmem_global_config[index];\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tif (index == RTE_DIM(ivshmem_global_config)) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot create more ivshmem config files. \"\n\t\t\"Maximum has been reached\\n\");\n\t\trte_spinlock_unlock(&global_cfg_sl);\n\t\treturn -1;\n\t}\n\n\tivshmem_config->lock.l_type = F_WRLCK;\n\tivshmem_config->lock.l_whence = SEEK_SET;\n\n\tivshmem_config->lock.l_start = 0;\n\tivshmem_config->lock.l_len = METADATA_SIZE_ALIGNED;\n\n\tivshmem_global_config[index].metadata = ((struct rte_ivshmem_metadata *)\n\t\t\tivshmem_metadata_create(\n\t\t\t\t\tname,\n\t\t\t\t\tsizeof(struct rte_ivshmem_metadata),\n\t\t\t\t\t&ivshmem_config->lock));\n\n\tif (ivshmem_global_config[index].metadata == NULL) {\n\t\trte_spinlock_unlock(&global_cfg_sl);\n\t\treturn -1;\n\t}\n\n\t/* Metadata setup */\n\tmemset(ivshmem_config->metadata, 0, sizeof(struct rte_ivshmem_metadata));\n\tivshmem_config->metadata->magic_number = IVSHMEM_MAGIC;\n\tsnprintf(ivshmem_config->metadata->name,\n\t\t\tsizeof(ivshmem_config->metadata->name), \"%s\", name);\n\n\trte_spinlock_unlock(&global_cfg_sl);\n\n\treturn 0;\n}\n\nint\nrte_ivshmem_metadata_cmdline_generate(char *buffer, unsigned size, const char *name)\n{\n\tconst struct memseg_cache_entry * ms_cache, *entry;\n\tstruct ivshmem_config * config;\n\tchar cmdline[IVSHMEM_QEMU_CMDLINE_BUFSIZE], *cmdline_ptr;\n\tchar cfg_file_path[PATH_MAX];\n\tunsigned remaining_len, tmplen, iter;\n\tuint64_t shared_mem_size, zero_size, total_size;\n\n\tif (buffer == NULL || name == NULL)\n\t\treturn -1;\n\n\tconfig = get_config_by_name(name);\n\n\tif (config == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Config %s not found!\\n\", name);\n\t\treturn -1;\n\t}\n\n\trte_spinlock_lock(&config->sl);\n\n\t/* prepare metadata file path */\n\tsnprintf(cfg_file_path, sizeof(cfg_file_path), IVSHMEM_CONFIG_FILE_FMT,\n\t\t\tconfig->metadata->name);\n\n\tms_cache = config->memseg_cache;\n\n\tcmdline_ptr = cmdline;\n\tremaining_len = sizeof(cmdline);\n\n\tshared_mem_size = 0;\n\titer = 0;\n\n\twhile ((ms_cache[iter].len != 0) && (iter < RTE_DIM(config->metadata->entry))) {\n\n\t\tentry = &ms_cache[iter];\n\n\t\t/* Offset and sizes within the current pathname */\n\t\ttmplen = snprintf(cmdline_ptr, remaining_len, IVSHMEM_QEMU_CMD_FD_FMT,\n\t\t\t\tentry->filepath, entry->offset, entry->len);\n\n\t\tshared_mem_size += entry->len;\n\n\t\tcmdline_ptr = RTE_PTR_ADD(cmdline_ptr, tmplen);\n\t\tremaining_len -= tmplen;\n\n\t\tif (remaining_len == 0) {\n\t\t\tRTE_LOG(ERR, EAL, \"Command line too long!\\n\");\n\t\t\trte_spinlock_unlock(&config->sl);\n\t\t\treturn -1;\n\t\t}\n\n\t\titer++;\n\t}\n\n\ttotal_size = rte_align64pow2(shared_mem_size + METADATA_SIZE_ALIGNED);\n\tzero_size = total_size - shared_mem_size - METADATA_SIZE_ALIGNED;\n\n\t/* add /dev/zero to command-line to fill the space */\n\ttmplen = snprintf(cmdline_ptr, remaining_len, IVSHMEM_QEMU_CMD_FD_FMT,\n\t\t\t\"/dev/zero\",\n\t\t\t(uint64_t)0x0,\n\t\t\tzero_size);\n\n\tcmdline_ptr = RTE_PTR_ADD(cmdline_ptr, tmplen);\n\tremaining_len -= tmplen;\n\n\tif (remaining_len == 0) {\n\t\tRTE_LOG(ERR, EAL, \"Command line too long!\\n\");\n\t\trte_spinlock_unlock(&config->sl);\n\t\treturn -1;\n\t}\n\n\t/* add metadata file to the end of command-line */\n\ttmplen = snprintf(cmdline_ptr, remaining_len, IVSHMEM_QEMU_CMD_FD_FMT,\n\t\t\tcfg_file_path,\n\t\t\t(uint64_t)0x0,\n\t\t\tMETADATA_SIZE_ALIGNED);\n\n\tcmdline_ptr = RTE_PTR_ADD(cmdline_ptr, tmplen);\n\tremaining_len -= tmplen;\n\n\tif (remaining_len == 0) {\n\t\tRTE_LOG(ERR, EAL, \"Command line too long!\\n\");\n\t\trte_spinlock_unlock(&config->sl);\n\t\treturn -1;\n\t}\n\n\t/* if current length of the command line is bigger than the buffer supplied\n\t * by the user, or if command-line is bigger than what IVSHMEM accepts */\n\tif ((sizeof(cmdline) - remaining_len) > size) {\n\t\tRTE_LOG(ERR, EAL, \"Buffer is too short!\\n\");\n\t\trte_spinlock_unlock(&config->sl);\n\t\treturn -1;\n\t}\n\t/* complete the command-line */\n\tsnprintf(buffer, size,\n\t\t\tIVSHMEM_QEMU_CMD_LINE_HEADER_FMT,\n\t\t\ttotal_size >> 20,\n\t\t\tcmdline);\n\n\trte_spinlock_unlock(&config->sl);\n\n\treturn 0;\n}\n\nvoid\nrte_ivshmem_metadata_dump(FILE *f, const char *name)\n{\n\tunsigned i = 0;\n\tstruct ivshmem_config * config;\n\tstruct rte_ivshmem_metadata_entry *entry;\n#ifdef RTE_LIBRTE_IVSHMEM_DEBUG\n\tuint64_t addr;\n\tuint64_t end, hugepage_sz;\n\tstruct memseg_cache_entry e;\n#endif\n\n\tif (name == NULL)\n\t\treturn;\n\n\t/* return error if we try to use an unknown config file */\n\tconfig = get_config_by_name(name);\n\tif (config == NULL) {\n\t\tRTE_LOG(ERR, EAL, \"Cannot find IVSHMEM config %s!\\n\", name);\n\t\treturn;\n\t}\n\n\trte_spinlock_lock(&config->sl);\n\n\tentry = &config->metadata->entry[0];\n\n\twhile (entry->mz.addr != NULL && i < RTE_DIM(config->metadata->entry)) {\n\n\t\tfprintf(f, \"Entry %u: name:<%-20s>, phys:0x%-15lx, len:0x%-15lx, \"\n\t\t\t\"virt:%-15p, off:0x%-15lx\\n\",\n\t\t\ti,\n\t\t\tentry->mz.name,\n\t\t\tentry->mz.phys_addr,\n\t\t\tentry->mz.len,\n\t\t\tentry->mz.addr,\n\t\t\tentry->offset);\n\t\ti++;\n\n#ifdef RTE_LIBRTE_IVSHMEM_DEBUG\n\t\tfprintf(f, \"\\tHugepage files:\\n\");\n\n\t\thugepage_sz = entry->mz.hugepage_sz;\n\t\taddr = RTE_ALIGN_FLOOR(entry->mz.addr_64, hugepage_sz);\n\t\tend = addr + RTE_ALIGN_CEIL(entry->mz.len + (entry->mz.addr_64 - addr),\n\t\t\t\thugepage_sz);\n\n\t\tfor (; addr < end; addr += hugepage_sz) {\n\t\t\tmemset(&e, 0, sizeof(e));\n\n\t\t\tget_hugefile_by_virt_addr(addr, &e);\n\n\t\t\tfprintf(f, \"\\t0x%\"PRIx64 \"-0x%\" PRIx64 \" offset: 0x%\" PRIx64 \" %s\\n\",\n\t\t\t\t\taddr, addr + hugepage_sz, e.offset, e.filepath);\n\t\t}\n#endif\n\t\tentry++;\n\t}\n\n\trte_spinlock_unlock(&config->sl);\n}\n" }, { "path": "lib/librte_ivshmem/rte_ivshmem.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef RTE_IVSHMEM_H_\n#define RTE_IVSHMEM_H_\n\n#include \n#include \n\n/**\n * @file\n *\n * The RTE IVSHMEM interface provides functions to create metadata files\n * describing memory segments to be shared via QEMU IVSHMEM.\n */\n\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define IVSHMEM_MAGIC 0x0BADC0DE\n#define IVSHMEM_NAME_LEN 32\n\n/**\n * Structure that holds IVSHMEM shared metadata entry.\n */\nstruct rte_ivshmem_metadata_entry {\n\tstruct rte_memzone mz;\t/**< shared memzone */\n\tuint64_t offset;\t/**< offset of memzone within IVSHMEM device */\n};\n\n/**\n * Structure that holds IVSHMEM metadata.\n */\nstruct rte_ivshmem_metadata {\n\tint magic_number;\t\t\t\t/**< magic number */\n\tchar name[IVSHMEM_NAME_LEN];\t/**< name of the metadata file */\n\tstruct rte_ivshmem_metadata_entry entry[RTE_LIBRTE_IVSHMEM_MAX_ENTRIES];\n\t\t\t/**< metadata entries */\n};\n\n/**\n * Creates metadata file with a given name\n *\n * @param name\n * Name of metadata file to be created\n *\n * @return\n * - On success, zero\n * - On failure, a negative value\n */\nint rte_ivshmem_metadata_create(const char * name);\n\n/**\n * Adds memzone to a specific metadata file\n *\n * @param mz\n * Memzone to be added\n * @param md_name\n * Name of metadata file for the memzone to be added to\n *\n * @return\n * - On success, zero\n * - On failure, a negative value\n */\nint rte_ivshmem_metadata_add_memzone(const struct rte_memzone * mz,\n\t\tconst char * md_name);\n\n/**\n * Adds a ring descriptor to a specific metadata file\n *\n * @param r\n * Ring descriptor to be added\n * @param md_name\n * Name of metadata file for the ring to be added to\n *\n * @return\n * - On success, zero\n * - On failure, a negative value\n */\nint rte_ivshmem_metadata_add_ring(const struct rte_ring * r,\n\t\tconst char * md_name);\n\n/**\n * Adds a mempool to a specific metadata file\n *\n * @param mp\n * Mempool to be added\n * @param md_name\n * Name of metadata file for the mempool to be added to\n *\n * @return\n * - On success, zero\n * - On failure, a negative value\n */\nint rte_ivshmem_metadata_add_mempool(const struct rte_mempool * mp,\n\t\tconst char * md_name);\n\n\n/**\n * Generates the QEMU command-line for IVSHMEM device for a given metadata file.\n * This function is to be called after all the objects were added.\n *\n * @param buffer\n * Buffer to be filled with the command line arguments.\n * @param size\n * Size of the buffer.\n * @param name\n * Name of metadata file to generate QEMU command-line parameters for\n *\n * @return\n * - On success, zero\n * - On failure, a negative value\n */\nint rte_ivshmem_metadata_cmdline_generate(char *buffer, unsigned size,\n\t\tconst char *name);\n\n\n/**\n * Dump all metadata entries from a given metadata file to the console.\n *\n * @param f\n * A pointer to a file for output\n * @name\n * Name of the metadata file to be dumped to console.\n */\nvoid rte_ivshmem_metadata_dump(FILE *f, const char *name);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* RTE_IVSHMEM_H_ */\n" }, { "path": "lib/librte_jobstats/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_jobstats.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR)\n\nEXPORT_MAP := rte_jobstats_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_JOBSTATS) := rte_jobstats.c\n\n# install this header file\nSYMLINK-$(CONFIG_RTE_LIBRTE_JOBSTATS)-include := rte_jobstats.h\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_JOBSTATS) += lib/librte_eal\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_jobstats/rte_jobstats.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_jobstats.h\"\n\n#define ADD_TIME_MIN_MAX(obj, type, value) do { \\\n\ttypeof(value) tmp = (value); \\\n\t(obj)->type ## _time += tmp; \\\n\tif (tmp < (obj)->min_ ## type ## _time) \\\n\t\t(obj)->min_ ## type ## _time = tmp; \\\n\tif (tmp > (obj)->max_ ## type ## _time) \\\n\t\t(obj)->max_ ## type ## _time = tmp; \\\n} while (0)\n\n#define RESET_TIME_MIN_MAX(obj, type) do { \\\n\t(obj)->type ## _time = 0; \\\n\t(obj)->min_ ## type ## _time = UINT64_MAX; \\\n\t(obj)->max_ ## type ## _time = 0; \\\n} while (0)\n\nstatic inline uint64_t\nget_time(void)\n{\n\trte_rmb();\n\treturn rte_get_timer_cycles();\n}\n\n/* Those are steps used to adjust job period.\n * Experiments show that for forwarding apps the up step must be less than down\n * step to achieve optimal performance.\n */\n#define JOB_UPDATE_STEP_UP 1\n#define JOB_UPDATE_STEP_DOWN 4\n\n/*\n * Default update function that implements simple period adjustment.\n */\nstatic void\ndefault_update_function(struct rte_jobstats *job, int64_t result)\n{\n\tint64_t err = job->target - result;\n\n\t/* Job is happy. Nothing to do */\n\tif (err == 0)\n\t\treturn;\n\n\tif (err > 0) {\n\t\tif (job->period + JOB_UPDATE_STEP_UP < job->max_period)\n\t\t\tjob->period += JOB_UPDATE_STEP_UP;\n\t} else {\n\t\tif (job->min_period + JOB_UPDATE_STEP_DOWN < job->period)\n\t\t\tjob->period -= JOB_UPDATE_STEP_DOWN;\n\t}\n}\n\nint\nrte_jobstats_context_init(struct rte_jobstats_context *ctx)\n{\n\tif (ctx == NULL)\n\t\treturn -EINVAL;\n\n\t/* Init only needed parameters. Zero out everything else. */\n\tmemset(ctx, 0, sizeof(struct rte_jobstats_context));\n\n\trte_jobstats_context_reset(ctx);\n\n\treturn 0;\n}\n\nvoid\nrte_jobstats_context_start(struct rte_jobstats_context *ctx)\n{\n\tuint64_t now;\n\n\tctx->loop_executed_jobs = 0;\n\n\tnow = get_time();\n\tADD_TIME_MIN_MAX(ctx, management, now - ctx->state_time);\n\tctx->state_time = now;\n}\n\nvoid\nrte_jobstats_context_finish(struct rte_jobstats_context *ctx)\n{\n\tuint64_t now;\n\n\tif (likely(ctx->loop_executed_jobs))\n\t\tctx->loop_cnt++;\n\n\tnow = get_time();\n\tADD_TIME_MIN_MAX(ctx, management, now - ctx->state_time);\n\tctx->state_time = now;\n}\n\nvoid\nrte_jobstats_context_reset(struct rte_jobstats_context *ctx)\n{\n\tRESET_TIME_MIN_MAX(ctx, exec);\n\tRESET_TIME_MIN_MAX(ctx, management);\n\tctx->start_time = get_time();\n\tctx->state_time = ctx->start_time;\n\tctx->job_exec_cnt = 0;\n\tctx->loop_cnt = 0;\n}\n\nvoid\nrte_jobstats_set_target(struct rte_jobstats *job, int64_t target)\n{\n\tjob->target = target;\n}\n\nint\nrte_jobstats_start(struct rte_jobstats_context *ctx, struct rte_jobstats *job)\n{\n\tuint64_t now;\n\n\t/* Some sanity check. */\n\tif (unlikely(ctx == NULL || job == NULL || job->context != NULL))\n\t\treturn -EINVAL;\n\n\t/* Link job with context object. */\n\tjob->context = ctx;\n\n\tnow = get_time();\n\tADD_TIME_MIN_MAX(ctx, management, now - ctx->state_time);\n\tctx->state_time = now;\n\n\treturn 0;\n}\n\nint\nrte_jobstats_finish(struct rte_jobstats *job, int64_t job_value)\n{\n\tstruct rte_jobstats_context *ctx;\n\tuint64_t now, exec_time;\n\tint need_update;\n\n\t/* Some sanity check. */\n\tif (unlikely(job == NULL || job->context == NULL))\n\t\treturn -EINVAL;\n\n\tneed_update = job->target != job_value;\n\t/* Adjust period only if job is unhappy of its current period. */\n\tif (need_update)\n\t\t(*job->update_period_cb)(job, job_value);\n\n\tctx = job->context;\n\n\t/* Update execution time is considered as runtime so get time after it is\n\t * executed. */\n\tnow = get_time();\n\texec_time = now - ctx->state_time;\n\tADD_TIME_MIN_MAX(job, exec, exec_time);\n\tADD_TIME_MIN_MAX(ctx, exec, exec_time);\n\n\tctx->state_time = now;\n\n\tctx->loop_executed_jobs++;\n\tctx->job_exec_cnt++;\n\n\tjob->exec_cnt++;\n\tjob->context = NULL;\n\n\treturn need_update;\n}\n\nvoid\nrte_jobstats_set_period(struct rte_jobstats *job, uint64_t period,\n\t\tuint8_t saturate)\n{\n\tif (saturate != 0) {\n\t\tif (period < job->min_period)\n\t\t\tperiod = job->min_period;\n\t\telse if (period > job->max_period)\n\t\t\tperiod = job->max_period;\n\t}\n\n\tjob->period = period;\n}\n\nvoid\nrte_jobstats_set_min(struct rte_jobstats *job, uint64_t period)\n{\n\tjob->min_period = period;\n\tif (job->period < period)\n\t\tjob->period = period;\n}\n\nvoid\nrte_jobstats_set_max(struct rte_jobstats *job, uint64_t period)\n{\n\tjob->max_period = period;\n\tif (job->period > period)\n\t\tjob->period = period;\n}\n\nint\nrte_jobstats_init(struct rte_jobstats *job, const char *name,\n\t\tuint64_t min_period, uint64_t max_period, uint64_t initial_period,\n\t\tint64_t target)\n{\n\tif (job == NULL)\n\t\treturn -EINVAL;\n\n\tjob->period = initial_period;\n\tjob->min_period = min_period;\n\tjob->max_period = max_period;\n\tjob->target = target;\n\tjob->update_period_cb = &default_update_function;\n\trte_jobstats_reset(job);\n\tsnprintf(job->name, RTE_DIM(job->name), \"%s\", name == NULL ? \"\" : name);\n\tjob->context = NULL;\n\n\treturn 0;\n}\n\nvoid\nrte_jobstats_set_update_period_function(struct rte_jobstats *job,\n\t\trte_job_update_period_cb_t update_period_cb)\n{\n\tif (update_period_cb == NULL)\n\t\tupdate_period_cb = default_update_function;\n\n\tjob->update_period_cb = update_period_cb;\n}\n\nvoid\nrte_jobstats_reset(struct rte_jobstats *job)\n{\n\tRESET_TIME_MIN_MAX(job, exec);\n\tjob->exec_cnt = 0;\n}\n" }, { "path": "lib/librte_jobstats/rte_jobstats.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef JOBSTATS_H_\n#define JOBSTATS_H_\n\n#include \n\n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define RTE_JOBSTATS_NAMESIZE 32\n\n/* Forward declarations. */\nstruct rte_jobstats_context;\nstruct rte_jobstats;\n\n/**\n * This function should calculate new period and set it using\n * rte_jobstats_set_period() function. Time spent in this function will be\n * added to job's runtime.\n *\n * @param job\n * The job data structure handler.\n * @param job_result\n * Result of calling job callback.\n */\ntypedef void (*rte_job_update_period_cb_t)(struct rte_jobstats *job,\n\t\tint64_t job_result);\n\nstruct rte_jobstats {\n\tuint64_t period;\n\t/**< Estimated period of execution. */\n\n\tuint64_t min_period;\n\t/**< Minimum period. */\n\n\tuint64_t max_period;\n\t/**< Maximum period. */\n\n\tint64_t target;\n\t/**< Desired value for this job. */\n\n\trte_job_update_period_cb_t update_period_cb;\n\t/**< Period update callback. */\n\n\tuint64_t exec_time;\n\t/**< Total time (sum) that this job was executing. */\n\n\tuint64_t min_exec_time;\n\t/**< Minimum execute time. */\n\n\tuint64_t max_exec_time;\n\t/**< Minimum execute time. */\n\n\tuint64_t exec_cnt;\n\t/**< Execute count. */\n\n\tchar name[RTE_JOBSTATS_NAMESIZE];\n\t/**< Name of this job */\n\n\tstruct rte_jobstats_context *context;\n\t/**< Job stats context object that is executing this job. */\n} __rte_cache_aligned;\n\nstruct rte_jobstats_context {\n\t/** Viariable holding time at different points:\n\t * -# loop start time if loop was started but no job executed yet.\n\t * -# job start time if job is currently executing.\n\t * -# job finish time if job finished its execution.\n\t * -# loop finish time if loop finished its execution. */\n\tuint64_t state_time;\n\n\tuint64_t loop_executed_jobs;\n\t/**< Count of executed jobs in this loop. */\n\n\t/* Statistics start. */\n\n\tuint64_t exec_time;\n\t/**< Total time taken to execute jobs, not including management time. */\n\n\tuint64_t min_exec_time;\n\t/**< Minimum loop execute time. */\n\n\tuint64_t max_exec_time;\n\t/**< Minimum loop execute time. */\n\n\t/**\n\t * Sum of time that is not the execute time (ex: from job finish to next\n\t * job start).\n\t *\n\t * This time might be considered as overhead of library + job scheduling.\n\t */\n\tuint64_t management_time;\n\n\tuint64_t min_management_time;\n\t/**< Minimum management time */\n\n\tuint64_t max_management_time;\n\t/**< Maximum management time */\n\n\tuint64_t start_time;\n\t/**< Time since last reset stats. */\n\n\tuint64_t job_exec_cnt;\n\t/**< Total count of executed jobs. */\n\n\tuint64_t loop_cnt;\n\t/**< Total count of executed loops with at least one executed job. */\n} __rte_cache_aligned;\n\n/**\n * Initialize given context object with default values.\n *\n * @param ctx\n * Job stats context object to initialize.\n *\n * @return\n * 0 on success\n * -EINVAL if *ctx* is NULL\n */\nint\nrte_jobstats_context_init(struct rte_jobstats_context *ctx);\n\n/**\n * Mark that new set of jobs start executing.\n *\n * @param ctx\n * Job stats context object.\n */\nvoid\nrte_jobstats_context_start(struct rte_jobstats_context *ctx);\n\n/**\n * Mark that there is no more jobs ready to execute in this turn. Calculate\n * stats for this loop turn.\n *\n * @param ctx\n * Job stats context.\n */\nvoid\nrte_jobstats_context_finish(struct rte_jobstats_context *ctx);\n\n/**\n * Function resets job context statistics.\n *\n * @param ctx\n * Job stats context which statistics will be reset.\n */\nvoid\nrte_jobstats_context_reset(struct rte_jobstats_context *ctx);\n\n/**\n * Initialize given job stats object.\n *\n * @param job\n * Job object.\n * @param name\n * Optional job name.\n * @param min_period\n * Minimum period that this job can accept.\n * @param max_period\n * Maximum period that this job can accept.\n * @param initial_period\n * Initial period. It will be checked against *min_period* and *max_period*.\n * @param target\n * Target value that this job try to achieve.\n *\n * @return\n * 0 on success\n * -EINVAL if *job* is NULL\n */\nint\nrte_jobstats_init(struct rte_jobstats *job, const char *name,\n\t\tuint64_t min_period, uint64_t max_period, uint64_t initial_period,\n\t\tint64_t target);\n\n/**\n * Set job desired target value. Difference between target and job value\n * value must be used to properly adjust job execute period value.\n *\n * @param job\n * The job object.\n * @param target\n * New target.\n */\nvoid\nrte_jobstats_set_target(struct rte_jobstats *job, int64_t target);\n\n/**\n * Mark that *job* is starting of its execution in context of *ctx* object.\n *\n * @param ctx\n * Job stats context.\n * @param job\n * Job object.\n * @return\n * 0 on success\n * -EINVAL if *ctx* or *job* is NULL or *job* is executing in another context\n * context already,\n */\nint\nrte_jobstats_start(struct rte_jobstats_context *ctx, struct rte_jobstats *job);\n\n/**\n * Mark that *job* finished its execution. Context in which it was executing\n * will receive stat update. After this function call *job* object is ready to\n * be executed in other context.\n *\n * @param job\n * Job object.\n * @param job_value\n * Job value. Job should pass in this parameter a value that it try to optimize\n * for example the number of packets it processed.\n *\n * @return\n * 0 if job's period was not updated (job target equals *job_value*)\n * 1 if job's period was updated\n * -EINVAL if job is NULL or job was not started (it have no context).\n */\nint\nrte_jobstats_finish(struct rte_jobstats *job, int64_t job_value);\n\n/**\n * Set execute period of given job.\n *\n * @param job\n * The job object.\n * @param period\n * New period value.\n * @param saturate\n * If zero, skip period saturation to min, max range.\n */\nvoid\nrte_jobstats_set_period(struct rte_jobstats *job, uint64_t period,\n\t\tuint8_t saturate);\n/**\n * Set minimum execute period of given job. Current period will be checked\n * against new minimum value.\n *\n * @param job\n * The job object.\n * @param period\n * New minimum period value.\n */\nvoid\nrte_jobstats_set_min(struct rte_jobstats *job, uint64_t period);\n/**\n * Set maximum execute period of given job. Current period will be checked\n * against new maximum value.\n *\n * @param job\n * The job object.\n * @param period\n * New maximum period value.\n */\nvoid\nrte_jobstats_set_max(struct rte_jobstats *job, uint64_t period);\n\n/**\n * Set update period callback that is invoked after job finish.\n *\n * If application wants to do more sophisticated calculations than default\n * it can provide this handler.\n *\n * @param job\n * Job object.\n * @param update_pedriod_cb\n * Callback to set. If NULL restore default update function.\n */\nvoid\nrte_jobstats_set_update_period_function(struct rte_jobstats *job,\n\t\trte_job_update_period_cb_t update_period_cb);\n\n/**\n * Function resets job statistics.\n *\n * @param job\n * Job which statistics will be reset.\n */\nvoid\nrte_jobstats_reset(struct rte_jobstats *job);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* JOBSTATS_H_ */\n" }, { "path": "lib/librte_kni/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_kni.a\n\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3 -fno-strict-aliasing\n\nEXPORT_MAP := rte_kni_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_KNI) := rte_kni.c\n\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_KNI)-include := rte_kni.h\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_KNI) += lib/librte_eal lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_KNI) += lib/librte_ether\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_kni/rte_kni.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef RTE_EXEC_ENV_LINUXAPP\n#error \"KNI is not supported\"\n#endif\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \"rte_kni_fifo.h\"\n\n#define MAX_MBUF_BURST_NUM 32\n\n/* Maximum number of ring entries */\n#define KNI_FIFO_COUNT_MAX 1024\n#define KNI_FIFO_SIZE (KNI_FIFO_COUNT_MAX * sizeof(void *) + \\\n\t\t\t\t\tsizeof(struct rte_kni_fifo))\n\n#define KNI_REQUEST_MBUF_NUM_MAX 32\n\n#define KNI_MEM_CHECK(cond) do { if (cond) goto kni_fail; } while (0)\n\n/**\n * KNI context\n */\nstruct rte_kni {\n\tchar name[RTE_KNI_NAMESIZE]; /**< KNI interface name */\n\tuint16_t group_id; /**< Group ID of KNI devices */\n\tuint32_t slot_id; /**< KNI pool slot ID */\n\tstruct rte_mempool *pktmbuf_pool; /**< pkt mbuf mempool */\n\tunsigned mbuf_size; /**< mbuf size */\n\n\tstruct rte_kni_fifo *tx_q; /**< TX queue */\n\tstruct rte_kni_fifo *rx_q; /**< RX queue */\n\tstruct rte_kni_fifo *alloc_q; /**< Allocated mbufs queue */\n\tstruct rte_kni_fifo *free_q; /**< To be freed mbufs queue */\n\n\t/* For request & response */\n\tstruct rte_kni_fifo *req_q; /**< Request queue */\n\tstruct rte_kni_fifo *resp_q; /**< Response queue */\n\tvoid * sync_addr; /**< Req/Resp Mem address */\n\n\tstruct rte_kni_ops ops; /**< operations for request */\n\tuint8_t in_use : 1; /**< kni in use */\n};\n\nenum kni_ops_status {\n\tKNI_REQ_NO_REGISTER = 0,\n\tKNI_REQ_REGISTERED,\n};\n\n/**\n * KNI memzone pool slot\n */\nstruct rte_kni_memzone_slot {\n\tuint32_t id;\n\tuint8_t in_use : 1; /**< slot in use */\n\n\t/* Memzones */\n\tconst struct rte_memzone *m_ctx; /**< KNI ctx */\n\tconst struct rte_memzone *m_tx_q; /**< TX queue */\n\tconst struct rte_memzone *m_rx_q; /**< RX queue */\n\tconst struct rte_memzone *m_alloc_q; /**< Allocated mbufs queue */\n\tconst struct rte_memzone *m_free_q; /**< To be freed mbufs queue */\n\tconst struct rte_memzone *m_req_q; /**< Request queue */\n\tconst struct rte_memzone *m_resp_q; /**< Response queue */\n\tconst struct rte_memzone *m_sync_addr;\n\n\t/* Free linked list */\n\tstruct rte_kni_memzone_slot *next; /**< Next slot link.list */\n};\n\n/**\n * KNI memzone pool\n */\nstruct rte_kni_memzone_pool {\n\tuint8_t initialized : 1; /**< Global KNI pool init flag */\n\n\tuint32_t max_ifaces; /**< Max. num of KNI ifaces */\n\tstruct rte_kni_memzone_slot *slots; /**< Pool slots */\n\trte_spinlock_t mutex; /**< alloc/relase mutex */\n\n\t/* Free memzone slots linked-list */\n\tstruct rte_kni_memzone_slot *free; /**< First empty slot */\n\tstruct rte_kni_memzone_slot *free_tail; /**< Last empty slot */\n};\n\n\nstatic void kni_free_mbufs(struct rte_kni *kni);\nstatic void kni_allocate_mbufs(struct rte_kni *kni);\n\nstatic volatile int kni_fd = -1;\nstatic struct rte_kni_memzone_pool kni_memzone_pool = {\n\t.initialized = 0,\n};\n\nstatic const struct rte_memzone *\nkni_memzone_reserve(const char *name, size_t len, int socket_id,\n\t\t\t\t\t\tunsigned flags)\n{\n\tconst struct rte_memzone *mz = rte_memzone_lookup(name);\n\n\tif (mz == NULL)\n\t\tmz = rte_memzone_reserve(name, len, socket_id, flags);\n\n\treturn mz;\n}\n\n/* Pool mgmt */\nstatic struct rte_kni_memzone_slot*\nkni_memzone_pool_alloc(void)\n{\n\tstruct rte_kni_memzone_slot *slot;\n\n\trte_spinlock_lock(&kni_memzone_pool.mutex);\n\n\tif (!kni_memzone_pool.free) {\n\t\trte_spinlock_unlock(&kni_memzone_pool.mutex);\n\t\treturn NULL;\n\t}\n\n\tslot = kni_memzone_pool.free;\n\tkni_memzone_pool.free = slot->next;\n\tslot->in_use = 1;\n\n\tif (!kni_memzone_pool.free)\n\t\tkni_memzone_pool.free_tail = NULL;\n\n\trte_spinlock_unlock(&kni_memzone_pool.mutex);\n\n\treturn slot;\n}\n\nstatic void\nkni_memzone_pool_release(struct rte_kni_memzone_slot *slot)\n{\n\trte_spinlock_lock(&kni_memzone_pool.mutex);\n\n\tif (kni_memzone_pool.free)\n\t\tkni_memzone_pool.free_tail->next = slot;\n\telse\n\t\tkni_memzone_pool.free = slot;\n\n\tkni_memzone_pool.free_tail = slot;\n\tslot->next = NULL;\n\tslot->in_use = 0;\n\n\trte_spinlock_unlock(&kni_memzone_pool.mutex);\n}\n\n\n/* Shall be called before any allocation happens */\nvoid\nrte_kni_init(unsigned int max_kni_ifaces)\n{\n\tuint32_t i;\n\tstruct rte_kni_memzone_slot *it;\n\tconst struct rte_memzone *mz;\n#define OBJNAMSIZ 32\n\tchar obj_name[OBJNAMSIZ];\n\tchar mz_name[RTE_MEMZONE_NAMESIZE];\n\n\t/* Immediately return if KNI is already initialized */\n\tif (kni_memzone_pool.initialized) {\n\t\tRTE_LOG(WARNING, KNI, \"Double call to rte_kni_init()\");\n\t\treturn;\n\t}\n\n\tif (max_kni_ifaces == 0) {\n\t\tRTE_LOG(ERR, KNI, \"Invalid number of max_kni_ifaces %d\\n\",\n\t\t\t\t\t\t\tmax_kni_ifaces);\n\t\trte_panic(\"Unable to initialize KNI\\n\");\n\t}\n\n\t/* Check FD and open */\n\tif (kni_fd < 0) {\n\t\tkni_fd = open(\"/dev/\" KNI_DEVICE, O_RDWR);\n\t\tif (kni_fd < 0)\n\t\t\trte_panic(\"Can not open /dev/%s\\n\", KNI_DEVICE);\n\t}\n\n\t/* Allocate slot objects */\n\tkni_memzone_pool.slots = (struct rte_kni_memzone_slot *)\n\t\t\t\t\trte_malloc(NULL,\n\t\t\t\t\tsizeof(struct rte_kni_memzone_slot) *\n\t\t\t\t\tmax_kni_ifaces,\n\t\t\t\t\t0);\n\tKNI_MEM_CHECK(kni_memzone_pool.slots == NULL);\n\n\t/* Initialize general pool variables */\n\tkni_memzone_pool.initialized = 1;\n\tkni_memzone_pool.max_ifaces = max_kni_ifaces;\n\tkni_memzone_pool.free = &kni_memzone_pool.slots[0];\n\trte_spinlock_init(&kni_memzone_pool.mutex);\n\n\t/* Pre-allocate all memzones of all the slots; panic on error */\n\tfor (i = 0; i < max_kni_ifaces; i++) {\n\n\t\t/* Recover current slot */\n\t\tit = &kni_memzone_pool.slots[i];\n\t\tit->id = i;\n\n\t\t/* Allocate KNI context */\n\t\tsnprintf(mz_name, RTE_MEMZONE_NAMESIZE, \"KNI_INFO_%d\", i);\n\t\tmz = kni_memzone_reserve(mz_name, sizeof(struct rte_kni),\n\t\t\t\t\tSOCKET_ID_ANY, 0);\n\t\tKNI_MEM_CHECK(mz == NULL);\n\t\tit->m_ctx = mz;\n\n\t\t/* TX RING */\n\t\tsnprintf(obj_name, OBJNAMSIZ, \"kni_tx_%d\", i);\n\t\tmz = kni_memzone_reserve(obj_name, KNI_FIFO_SIZE,\n\t\t\t\t\t\t\tSOCKET_ID_ANY, 0);\n\t\tKNI_MEM_CHECK(mz == NULL);\n\t\tit->m_tx_q = mz;\n\n\t\t/* RX RING */\n\t\tsnprintf(obj_name, OBJNAMSIZ, \"kni_rx_%d\", i);\n\t\tmz = kni_memzone_reserve(obj_name, KNI_FIFO_SIZE,\n\t\t\t\t\t\t\tSOCKET_ID_ANY, 0);\n\t\tKNI_MEM_CHECK(mz == NULL);\n\t\tit->m_rx_q = mz;\n\n\t\t/* ALLOC RING */\n\t\tsnprintf(obj_name, OBJNAMSIZ, \"kni_alloc_%d\", i);\n\t\tmz = kni_memzone_reserve(obj_name, KNI_FIFO_SIZE,\n\t\t\t\t\t\t\tSOCKET_ID_ANY, 0);\n\t\tKNI_MEM_CHECK(mz == NULL);\n\t\tit->m_alloc_q = mz;\n\n\t\t/* FREE RING */\n\t\tsnprintf(obj_name, OBJNAMSIZ, \"kni_free_%d\", i);\n\t\tmz = kni_memzone_reserve(obj_name, KNI_FIFO_SIZE,\n\t\t\t\t\t\t\tSOCKET_ID_ANY, 0);\n\t\tKNI_MEM_CHECK(mz == NULL);\n\t\tit->m_free_q = mz;\n\n\t\t/* Request RING */\n\t\tsnprintf(obj_name, OBJNAMSIZ, \"kni_req_%d\", i);\n\t\tmz = kni_memzone_reserve(obj_name, KNI_FIFO_SIZE,\n\t\t\t\t\t\t\tSOCKET_ID_ANY, 0);\n\t\tKNI_MEM_CHECK(mz == NULL);\n\t\tit->m_req_q = mz;\n\n\t\t/* Response RING */\n\t\tsnprintf(obj_name, OBJNAMSIZ, \"kni_resp_%d\", i);\n\t\tmz = kni_memzone_reserve(obj_name, KNI_FIFO_SIZE,\n\t\t\t\t\t\t\tSOCKET_ID_ANY, 0);\n\t\tKNI_MEM_CHECK(mz == NULL);\n\t\tit->m_resp_q = mz;\n\n\t\t/* Req/Resp sync mem area */\n\t\tsnprintf(obj_name, OBJNAMSIZ, \"kni_sync_%d\", i);\n\t\tmz = kni_memzone_reserve(obj_name, KNI_FIFO_SIZE,\n\t\t\t\t\t\t\tSOCKET_ID_ANY, 0);\n\t\tKNI_MEM_CHECK(mz == NULL);\n\t\tit->m_sync_addr = mz;\n\n\t\tif ((i+1) == max_kni_ifaces) {\n\t\t\tit->next = NULL;\n\t\t\tkni_memzone_pool.free_tail = it;\n\t\t} else\n\t\t\tit->next = &kni_memzone_pool.slots[i+1];\n\t}\n\n\treturn;\n\nkni_fail:\n\trte_panic(\"Unable to allocate memory for max_kni_ifaces:%d. Increase the amount of hugepages memory\\n\",\n\t\t\t max_kni_ifaces);\n}\n\n/* It is deprecated and just for backward compatibility */\nstruct rte_kni *\nrte_kni_create(uint8_t port_id,\n\t unsigned mbuf_size,\n\t struct rte_mempool *pktmbuf_pool,\n\t struct rte_kni_ops *ops)\n{\n\tstruct rte_kni_conf conf;\n\tstruct rte_eth_dev_info info;\n\n\tmemset(&info, 0, sizeof(info));\n\tmemset(&conf, 0, sizeof(conf));\n\trte_eth_dev_info_get(port_id, &info);\n\n\tsnprintf(conf.name, sizeof(conf.name), \"vEth%u\", port_id);\n\tconf.addr = info.pci_dev->addr;\n\tconf.id = info.pci_dev->id;\n\tconf.group_id = (uint16_t)port_id;\n\tconf.mbuf_size = mbuf_size;\n\n\t/* Save the port id for request handling */\n\tops->port_id = port_id;\n\n\treturn rte_kni_alloc(pktmbuf_pool, &conf, ops);\n}\n\nstruct rte_kni *\nrte_kni_alloc(struct rte_mempool *pktmbuf_pool,\n\t const struct rte_kni_conf *conf,\n\t struct rte_kni_ops *ops)\n{\n\tint ret;\n\tstruct rte_kni_device_info dev_info;\n\tstruct rte_kni *ctx;\n\tchar intf_name[RTE_KNI_NAMESIZE];\n\tchar mz_name[RTE_MEMZONE_NAMESIZE];\n\tconst struct rte_memzone *mz;\n\tstruct rte_kni_memzone_slot *slot = NULL;\n\n\tif (!pktmbuf_pool || !conf || !conf->name[0])\n\t\treturn NULL;\n\n\t/* Check if KNI subsystem has been initialized */\n\tif (kni_memzone_pool.initialized != 1) {\n\t\tRTE_LOG(ERR, KNI, \"KNI subsystem has not been initialized. Invoke rte_kni_init() first\\n\");\n\t\treturn NULL;\n\t}\n\n\t/* Get an available slot from the pool */\n\tslot = kni_memzone_pool_alloc();\n\tif (!slot) {\n\t\tRTE_LOG(ERR, KNI, \"Cannot allocate more KNI interfaces; increase the number of max_kni_ifaces(current %d) or release unusued ones.\\n\",\n\t\t\tkni_memzone_pool.max_ifaces);\n\t\treturn NULL;\n\t}\n\n\t/* Recover ctx */\n\tctx = slot->m_ctx->addr;\n\tsnprintf(intf_name, RTE_KNI_NAMESIZE, \"%s\", conf->name);\n\n\tif (ctx->in_use) {\n\t\tRTE_LOG(ERR, KNI, \"KNI %s is in use\\n\", ctx->name);\n\t\treturn NULL;\n\t}\n\tmemset(ctx, 0, sizeof(struct rte_kni));\n\tif (ops)\n\t\tmemcpy(&ctx->ops, ops, sizeof(struct rte_kni_ops));\n\n\tmemset(&dev_info, 0, sizeof(dev_info));\n\tdev_info.bus = conf->addr.bus;\n\tdev_info.devid = conf->addr.devid;\n\tdev_info.function = conf->addr.function;\n\tdev_info.vendor_id = conf->id.vendor_id;\n\tdev_info.device_id = conf->id.device_id;\n\tdev_info.core_id = conf->core_id;\n\tdev_info.force_bind = conf->force_bind;\n\tdev_info.group_id = conf->group_id;\n\tdev_info.mbuf_size = conf->mbuf_size;\n\n\tsnprintf(ctx->name, RTE_KNI_NAMESIZE, \"%s\", intf_name);\n\tsnprintf(dev_info.name, RTE_KNI_NAMESIZE, \"%s\", intf_name);\n\n\tRTE_LOG(INFO, KNI, \"pci: %02x:%02x:%02x \\t %02x:%02x\\n\",\n\t\tdev_info.bus, dev_info.devid, dev_info.function,\n\t\t\tdev_info.vendor_id, dev_info.device_id);\n\t/* TX RING */\n\tmz = slot->m_tx_q;\n\tctx->tx_q = mz->addr;\n\tkni_fifo_init(ctx->tx_q, KNI_FIFO_COUNT_MAX);\n\tdev_info.tx_phys = mz->phys_addr;\n\n\t/* RX RING */\n\tmz = slot->m_rx_q;\n\tctx->rx_q = mz->addr;\n\tkni_fifo_init(ctx->rx_q, KNI_FIFO_COUNT_MAX);\n\tdev_info.rx_phys = mz->phys_addr;\n\n\t/* ALLOC RING */\n\tmz = slot->m_alloc_q;\n\tctx->alloc_q = mz->addr;\n\tkni_fifo_init(ctx->alloc_q, KNI_FIFO_COUNT_MAX);\n\tdev_info.alloc_phys = mz->phys_addr;\n\n\t/* FREE RING */\n\tmz = slot->m_free_q;\n\tctx->free_q = mz->addr;\n\tkni_fifo_init(ctx->free_q, KNI_FIFO_COUNT_MAX);\n\tdev_info.free_phys = mz->phys_addr;\n\n\t/* Request RING */\n\tmz = slot->m_req_q;\n\tctx->req_q = mz->addr;\n\tkni_fifo_init(ctx->req_q, KNI_FIFO_COUNT_MAX);\n\tdev_info.req_phys = mz->phys_addr;\n\n\t/* Response RING */\n\tmz = slot->m_resp_q;\n\tctx->resp_q = mz->addr;\n\tkni_fifo_init(ctx->resp_q, KNI_FIFO_COUNT_MAX);\n\tdev_info.resp_phys = mz->phys_addr;\n\n\t/* Req/Resp sync mem area */\n\tmz = slot->m_sync_addr;\n\tctx->sync_addr = mz->addr;\n\tdev_info.sync_va = mz->addr;\n\tdev_info.sync_phys = mz->phys_addr;\n\n\n\t/* MBUF mempool */\n\tsnprintf(mz_name, sizeof(mz_name), RTE_MEMPOOL_OBJ_NAME,\n\t\tpktmbuf_pool->name);\n\tmz = rte_memzone_lookup(mz_name);\n\tKNI_MEM_CHECK(mz == NULL);\n\tdev_info.mbuf_va = mz->addr;\n\tdev_info.mbuf_phys = mz->phys_addr;\n\tctx->pktmbuf_pool = pktmbuf_pool;\n\tctx->group_id = conf->group_id;\n\tctx->slot_id = slot->id;\n\tctx->mbuf_size = conf->mbuf_size;\n\n\tret = ioctl(kni_fd, RTE_KNI_IOCTL_CREATE, &dev_info);\n\tKNI_MEM_CHECK(ret < 0);\n\n\tctx->in_use = 1;\n\n\t/* Allocate mbufs and then put them into alloc_q */\n\tkni_allocate_mbufs(ctx);\n\n\treturn ctx;\n\nkni_fail:\n\tif (slot)\n\t\tkni_memzone_pool_release(&kni_memzone_pool.slots[slot->id]);\n\n\treturn NULL;\n}\n\nstatic void\nkni_free_fifo(struct rte_kni_fifo *fifo)\n{\n\tint ret;\n\tstruct rte_mbuf *pkt;\n\n\tdo {\n\t\tret = kni_fifo_get(fifo, (void **)&pkt, 1);\n\t\tif (ret)\n\t\t\trte_pktmbuf_free(pkt);\n\t} while (ret);\n}\n\nint\nrte_kni_release(struct rte_kni *kni)\n{\n\tstruct rte_kni_device_info dev_info;\n\tuint32_t slot_id;\n\n\tif (!kni || !kni->in_use)\n\t\treturn -1;\n\n\tsnprintf(dev_info.name, sizeof(dev_info.name), \"%s\", kni->name);\n\tif (ioctl(kni_fd, RTE_KNI_IOCTL_RELEASE, &dev_info) < 0) {\n\t\tRTE_LOG(ERR, KNI, \"Fail to release kni device\\n\");\n\t\treturn -1;\n\t}\n\n\t/* mbufs in all fifo should be released, except request/response */\n\tkni_free_fifo(kni->tx_q);\n\tkni_free_fifo(kni->rx_q);\n\tkni_free_fifo(kni->alloc_q);\n\tkni_free_fifo(kni->free_q);\n\n\tslot_id = kni->slot_id;\n\n\t/* Memset the KNI struct */\n\tmemset(kni, 0, sizeof(struct rte_kni));\n\n\t/* Release memzone */\n\tif (slot_id > kni_memzone_pool.max_ifaces) {\n\t\trte_panic(\"KNI pool: corrupted slot ID: %d, max: %d\\n\",\n\t\t\tslot_id, kni_memzone_pool.max_ifaces);\n\t}\n\tkni_memzone_pool_release(&kni_memzone_pool.slots[slot_id]);\n\n\treturn 0;\n}\n\nint\nrte_kni_handle_request(struct rte_kni *kni)\n{\n\tunsigned ret;\n\tstruct rte_kni_request *req;\n\n\tif (kni == NULL)\n\t\treturn -1;\n\n\t/* Get request mbuf */\n\tret = kni_fifo_get(kni->req_q, (void **)&req, 1);\n\tif (ret != 1)\n\t\treturn 0; /* It is OK of can not getting the request mbuf */\n\n\tif (req != kni->sync_addr) {\n\t\trte_panic(\"Wrong req pointer %p\\n\", req);\n\t}\n\n\t/* Analyze the request and call the relevant actions for it */\n\tswitch (req->req_id) {\n\tcase RTE_KNI_REQ_CHANGE_MTU: /* Change MTU */\n\t\tif (kni->ops.change_mtu)\n\t\t\treq->result = kni->ops.change_mtu(kni->ops.port_id,\n\t\t\t\t\t\t\treq->new_mtu);\n\t\tbreak;\n\tcase RTE_KNI_REQ_CFG_NETWORK_IF: /* Set network interface up/down */\n\t\tif (kni->ops.config_network_if)\n\t\t\treq->result = kni->ops.config_network_if(\\\n\t\t\t\t\tkni->ops.port_id, req->if_up);\n\t\tbreak;\n\tdefault:\n\t\tRTE_LOG(ERR, KNI, \"Unknown request id %u\\n\", req->req_id);\n\t\treq->result = -EINVAL;\n\t\tbreak;\n\t}\n\n\t/* Construct response mbuf and put it back to resp_q */\n\tret = kni_fifo_put(kni->resp_q, (void **)&req, 1);\n\tif (ret != 1) {\n\t\tRTE_LOG(ERR, KNI, \"Fail to put the muf back to resp_q\\n\");\n\t\treturn -1; /* It is an error of can't putting the mbuf back */\n\t}\n\n\treturn 0;\n}\n\nunsigned\nrte_kni_tx_burst(struct rte_kni *kni, struct rte_mbuf **mbufs, unsigned num)\n{\n\tunsigned ret = kni_fifo_put(kni->rx_q, (void **)mbufs, num);\n\n\t/* Get mbufs from free_q and then free them */\n\tkni_free_mbufs(kni);\n\n\treturn ret;\n}\n\nunsigned\nrte_kni_rx_burst(struct rte_kni *kni, struct rte_mbuf **mbufs, unsigned num)\n{\n\tunsigned ret = kni_fifo_get(kni->tx_q, (void **)mbufs, num);\n\n\t/* If buffers removed, allocate mbufs and then put them into alloc_q */\n\tif (ret)\n\t\tkni_allocate_mbufs(kni);\n\n\treturn ret;\n}\n\nstatic void\nkni_free_mbufs(struct rte_kni *kni)\n{\n\tint i, ret;\n\tstruct rte_mbuf *pkts[MAX_MBUF_BURST_NUM];\n\n\tret = kni_fifo_get(kni->free_q, (void **)pkts, MAX_MBUF_BURST_NUM);\n\tif (likely(ret > 0)) {\n\t\tfor (i = 0; i < ret; i++)\n\t\t\trte_pktmbuf_free(pkts[i]);\n\t}\n}\n\nstatic void\nkni_allocate_mbufs(struct rte_kni *kni)\n{\n\tint i, ret;\n\tstruct rte_mbuf *pkts[MAX_MBUF_BURST_NUM];\n\n\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pool) !=\n\t\t\t offsetof(struct rte_kni_mbuf, pool));\n\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_addr) !=\n\t\t\t offsetof(struct rte_kni_mbuf, buf_addr));\n\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, next) !=\n\t\t\t offsetof(struct rte_kni_mbuf, next));\n\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=\n\t\t\t offsetof(struct rte_kni_mbuf, data_off));\n\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=\n\t\t\t offsetof(struct rte_kni_mbuf, data_len));\n\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n\t\t\t offsetof(struct rte_kni_mbuf, pkt_len));\n\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n\t\t\t offsetof(struct rte_kni_mbuf, ol_flags));\n\n\t/* Check if pktmbuf pool has been configured */\n\tif (kni->pktmbuf_pool == NULL) {\n\t\tRTE_LOG(ERR, KNI, \"No valid mempool for allocating mbufs\\n\");\n\t\treturn;\n\t}\n\n\tfor (i = 0; i < MAX_MBUF_BURST_NUM; i++) {\n\t\tpkts[i] = rte_pktmbuf_alloc(kni->pktmbuf_pool);\n\t\tif (unlikely(pkts[i] == NULL)) {\n\t\t\t/* Out of memory */\n\t\t\tRTE_LOG(ERR, KNI, \"Out of memory\\n\");\n\t\t\tbreak;\n\t\t}\n\t}\n\n\t/* No pkt mbuf alocated */\n\tif (i <= 0)\n\t\treturn;\n\n\tret = kni_fifo_put(kni->alloc_q, (void **)pkts, i);\n\n\t/* Check if any mbufs not put into alloc_q, and then free them */\n\tif (ret >= 0 && ret < i && ret < MAX_MBUF_BURST_NUM) {\n\t\tint j;\n\n\t\tfor (j = ret; j < i; j++)\n\t\t\trte_pktmbuf_free(pkts[j]);\n\t}\n}\n\n/* It is deprecated and just for backward compatibility */\nuint8_t\nrte_kni_get_port_id(struct rte_kni *kni)\n{\n\tif (!kni)\n\t\treturn ~0x0;\n\n\treturn kni->ops.port_id;\n}\n\nstruct rte_kni *\nrte_kni_get(const char *name)\n{\n\tuint32_t i;\n\tstruct rte_kni_memzone_slot *it;\n\tstruct rte_kni *kni;\n\n\t/* Note: could be improved perf-wise if necessary */\n\tfor (i = 0; i < kni_memzone_pool.max_ifaces; i++) {\n\t\tit = &kni_memzone_pool.slots[i];\n\t\tif (it->in_use == 0)\n\t\t\tcontinue;\n\t\tkni = it->m_ctx->addr;\n\t\tif (strncmp(kni->name, name, RTE_KNI_NAMESIZE) == 0)\n\t\t\treturn kni;\n\t}\n\n\treturn NULL;\n}\n\nconst char *\nrte_kni_get_name(const struct rte_kni *kni)\n{\n\treturn kni->name;\n}\n\n/*\n * It is deprecated and just for backward compatibility.\n */\nstruct rte_kni *\nrte_kni_info_get(uint8_t port_id)\n{\n\tchar name[RTE_MEMZONE_NAMESIZE];\n\n\tif (port_id >= RTE_MAX_ETHPORTS)\n\t\treturn NULL;\n\n\tsnprintf(name, RTE_MEMZONE_NAMESIZE, \"vEth%u\", port_id);\n\n\treturn rte_kni_get(name);\n}\n\nstatic enum kni_ops_status\nkni_check_request_register(struct rte_kni_ops *ops)\n{\n\t/* check if KNI request ops has been registered*/\n\tif( NULL == ops )\n\t\treturn KNI_REQ_NO_REGISTER;\n\n\tif((NULL == ops->change_mtu) && (NULL == ops->config_network_if))\n\t\treturn KNI_REQ_NO_REGISTER;\n\n\treturn KNI_REQ_REGISTERED;\n}\n\nint\nrte_kni_register_handlers(struct rte_kni *kni,struct rte_kni_ops *ops)\n{\n\tenum kni_ops_status req_status;\n\n\tif (NULL == ops) {\n\t\tRTE_LOG(ERR, KNI, \"Invalid KNI request operation.\\n\");\n\t\treturn -1;\n\t}\n\n\tif (NULL == kni) {\n\t\tRTE_LOG(ERR, KNI, \"Invalid kni info.\\n\");\n\t\treturn -1;\n\t}\n\n\treq_status = kni_check_request_register(&kni->ops);\n\tif ( KNI_REQ_REGISTERED == req_status) {\n\t\tRTE_LOG(ERR, KNI, \"The KNI request operation has already registered.\\n\");\n\t\treturn -1;\n\t}\n\n\tmemcpy(&kni->ops, ops, sizeof(struct rte_kni_ops));\n\treturn 0;\n}\n\nint\nrte_kni_unregister_handlers(struct rte_kni *kni)\n{\n\tif (NULL == kni) {\n\t\tRTE_LOG(ERR, KNI, \"Invalid kni info.\\n\");\n\t\treturn -1;\n\t}\n\n\tkni->ops.change_mtu = NULL;\n\tkni->ops.config_network_if = NULL;\n\treturn 0;\n}\nvoid\nrte_kni_close(void)\n{\n\tif (kni_fd < 0)\n\t\treturn;\n\n\tclose(kni_fd);\n\tkni_fd = -1;\n}\n" }, { "path": "lib/librte_kni/rte_kni.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_KNI_H_\n#define _RTE_KNI_H_\n\n/**\n * @file\n * RTE KNI\n *\n * The KNI library provides the ability to create and destroy kernel NIC\n * interfaces that may be used by the RTE application to receive/transmit\n * packets from/to Linux kernel net interfaces.\n *\n * This library provide two APIs to burst receive packets from KNI interfaces,\n * and burst transmit packets to KNI interfaces.\n */\n\n#include \n#include \n#include \n\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct rte_kni;\nstruct rte_mbuf;\n\n/**\n * Structure which has the function pointers for KNI interface.\n */\nstruct rte_kni_ops {\n\tuint8_t port_id; /* Port ID */\n\n\t/* Pointer to function of changing MTU */\n\tint (*change_mtu)(uint8_t port_id, unsigned new_mtu);\n\n\t/* Pointer to function of configuring network interface */\n\tint (*config_network_if)(uint8_t port_id, uint8_t if_up);\n};\n\n/**\n * Structure for configuring KNI device.\n */\nstruct rte_kni_conf {\n\t/*\n\t * KNI name which will be used in relevant network device.\n\t * Let the name as short as possible, as it will be part of\n\t * memzone name.\n\t */\n\tchar name[RTE_KNI_NAMESIZE];\n\tuint32_t core_id; /* Core ID to bind kernel thread on */\n\tuint16_t group_id; /* Group ID */\n\tunsigned mbuf_size; /* mbuf size */\n\tstruct rte_pci_addr addr;\n\tstruct rte_pci_id id;\n\n\tuint8_t force_bind : 1; /* Flag to bind kernel thread */\n};\n\n/**\n * Initialize and preallocate KNI subsystem\n *\n * This function is to be executed on the MASTER lcore only, after EAL\n * initialization and before any KNI interface is attempted to be\n * allocated\n *\n * @param max_kni_ifaces\n * The maximum number of KNI interfaces that can coexist concurrently\n */\nextern void rte_kni_init(unsigned int max_kni_ifaces);\n\n\n/**\n * Allocate KNI interface according to the port id, mbuf size, mbuf pool,\n * configurations and callbacks for kernel requests.The KNI interface created\n * in the kernel space is the net interface the traditional Linux application\n * talking to.\n *\n * The rte_kni_alloc shall not be called before rte_kni_init() has been\n * called. rte_kni_alloc is thread safe.\n *\n * @param pktmbuf_pool\n * The mempool for allocting mbufs for packets.\n * @param conf\n * The pointer to the configurations of the KNI device.\n * @param ops\n * The pointer to the callbacks for the KNI kernel requests.\n *\n * @return\n * - The pointer to the context of a KNI interface.\n * - NULL indicate error.\n */\nextern struct rte_kni *rte_kni_alloc(struct rte_mempool *pktmbuf_pool,\n\t\t\t\t const struct rte_kni_conf *conf,\n\t\t\t\t struct rte_kni_ops *ops);\n\n/**\n * It create a KNI device for specific port.\n *\n * Note: It is deprecated and just for backward compatibility.\n *\n * @param port_id\n * Port ID.\n * @param mbuf_size\n * mbuf size.\n * @param pktmbuf_pool\n * The mempool for allocting mbufs for packets.\n * @param ops\n * The pointer to the callbacks for the KNI kernel requests.\n *\n * @return\n * - The pointer to the context of a KNI interface.\n * - NULL indicate error.\n */\nextern struct rte_kni *rte_kni_create(uint8_t port_id,\n\t\t\t\t unsigned mbuf_size,\n\t\t\t\t struct rte_mempool *pktmbuf_pool,\n\t\t\t\t struct rte_kni_ops *ops) \\\n\t\t\t\t __attribute__ ((deprecated));\n\n/**\n * Release KNI interface according to the context. It will also release the\n * paired KNI interface in kernel space. All processing on the specific KNI\n * context need to be stopped before calling this interface.\n *\n * rte_kni_release is thread safe.\n *\n * @param kni\n * The pointer to the context of an existent KNI interface.\n *\n * @return\n * - 0 indicates success.\n * - negative value indicates failure.\n */\nextern int rte_kni_release(struct rte_kni *kni);\n\n/**\n * It is used to handle the request mbufs sent from kernel space.\n * Then analyzes it and calls the specific actions for the specific requests.\n * Finally constructs the response mbuf and puts it back to the resp_q.\n *\n * @param kni\n * The pointer to the context of an existent KNI interface.\n *\n * @return\n * - 0\n * - negative value indicates failure.\n */\nextern int rte_kni_handle_request(struct rte_kni *kni);\n\n/**\n * Retrieve a burst of packets from a KNI interface. The retrieved packets are\n * stored in rte_mbuf structures whose pointers are supplied in the array of\n * mbufs, and the maximum number is indicated by num. It handles the freeing of\n * the mbufs in the free queue of KNI interface.\n *\n * @param kni\n * The KNI interface context.\n * @param mbufs\n * The array to store the pointers of mbufs.\n * @param num\n * The maximum number per burst.\n *\n * @return\n * The actual number of packets retrieved.\n */\nextern unsigned rte_kni_rx_burst(struct rte_kni *kni,\n\t\tstruct rte_mbuf **mbufs, unsigned num);\n\n/**\n * Send a burst of packets to a KNI interface. The packets to be sent out are\n * stored in rte_mbuf structures whose pointers are supplied in the array of\n * mbufs, and the maximum number is indicated by num. It handles allocating\n * the mbufs for KNI interface alloc queue.\n *\n * @param kni\n * The KNI interface context.\n * @param mbufs\n * The array to store the pointers of mbufs.\n * @param num\n * The maximum number per burst.\n *\n * @return\n * The actual number of packets sent.\n */\nextern unsigned rte_kni_tx_burst(struct rte_kni *kni,\n\t\tstruct rte_mbuf **mbufs, unsigned num);\n\n/**\n * Get the port id from KNI interface.\n *\n * Note: It is deprecated and just for backward compatibility.\n *\n * @param kni\n * The KNI interface context.\n *\n * @return\n * On success: The port id.\n * On failure: ~0x0\n */\nextern uint8_t rte_kni_get_port_id(struct rte_kni *kni) \\\n\t\t\t\t__attribute__ ((deprecated));\n\n/**\n * Get the KNI context of its name.\n *\n * @param name\n * pointer to the KNI device name.\n *\n * @return\n * On success: Pointer to KNI interface.\n * On failure: NULL.\n */\nextern struct rte_kni *rte_kni_get(const char *name);\n\n/**\n * Get the name given to a KNI device\n *\n * @param kni\n * The KNI instance to query\n * @return\n * The pointer to the KNI name\n */\nextern const char *rte_kni_get_name(const struct rte_kni *kni);\n\n/**\n * Get the KNI context of the specific port.\n *\n * Note: It is deprecated and just for backward compatibility.\n *\n * @param port_id\n * the port id.\n *\n * @return\n * On success: Pointer to KNI interface.\n * On failure: NULL\n */\nextern struct rte_kni *rte_kni_info_get(uint8_t port_id) \\\n\t\t\t\t__attribute__ ((deprecated));\n\n/**\n * Register KNI request handling for a specified port,and it can\n * be called by master process or slave process.\n *\n * @param kni\n * pointer to struct rte_kni.\n * @param ops\n * ponter to struct rte_kni_ops.\n *\n * @return\n * On success: 0\n * On failure: -1\n */\nextern int rte_kni_register_handlers(struct rte_kni *kni,\n\t\t\tstruct rte_kni_ops *ops);\n\n/**\n * Unregister KNI request handling for a specified port.\n *\n * @param kni\n * pointer to struct rte_kni.\n *\n * @return\n * On success: 0\n * On failure: -1\n */\nextern int rte_kni_unregister_handlers(struct rte_kni *kni);\n\n/**\n * Close KNI device.\n */\nextern void rte_kni_close(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_KNI_H_ */\n" }, { "path": "lib/librte_kni/rte_kni_fifo.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n\n\n/**\n * Initializes the kni fifo structure\n */\nstatic void\nkni_fifo_init(struct rte_kni_fifo *fifo, unsigned size)\n{\n\t/* Ensure size is power of 2 */\n\tif (size & (size - 1))\n\t\trte_panic(\"KNI fifo size must be power of 2\\n\");\n\n\tfifo->write = 0;\n\tfifo->read = 0;\n\tfifo->len = size;\n\tfifo->elem_size = sizeof(void *);\n}\n\n/**\n * Adds num elements into the fifo. Return the number actually written\n */\nstatic inline unsigned\nkni_fifo_put(struct rte_kni_fifo *fifo, void **data, unsigned num)\n{\n\tunsigned i = 0;\n\tunsigned fifo_write = fifo->write;\n\tunsigned fifo_read = fifo->read;\n\tunsigned new_write = fifo_write;\n\n\tfor (i = 0; i < num; i++) {\n\t\tnew_write = (new_write + 1) & (fifo->len - 1);\n\n\t\tif (new_write == fifo_read)\n\t\t\tbreak;\n\t\tfifo->buffer[fifo_write] = data[i];\n\t\tfifo_write = new_write;\n\t}\n\tfifo->write = fifo_write;\n\treturn i;\n}\n\n/**\n * Get up to num elements from the fifo. Return the number actully read\n */\nstatic inline unsigned\nkni_fifo_get(struct rte_kni_fifo *fifo, void **data, unsigned num)\n{\n\tunsigned i = 0;\n\tunsigned new_read = fifo->read;\n\tunsigned fifo_write = fifo->write;\n\tfor (i = 0; i < num; i++) {\n\t\tif (new_read == fifo_write)\n\t\t\tbreak;\n\n\t\tdata[i] = fifo->buffer[new_read];\n\t\tnew_read = (new_read + 1) & (fifo->len - 1);\n\t}\n\tfifo->read = new_read;\n\treturn i;\n}\n" }, { "path": "lib/librte_kvargs/Makefile", "content": "# BSD LICENSE\n#\n# Copyright 2014 6WIND S.A.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# - Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n#\n# - Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n#\n# - Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n# OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_kvargs.a\n\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3\n\nEXPORT_MAP := rte_kvargs_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_KVARGS) := rte_kvargs.c\n\n# install includes\nINCS := rte_kvargs.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_KVARGS)-include := $(INCS)\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_KVARGS) += lib/librte_eal\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_kvargs/rte_kvargs.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.\n * Copyright(c) 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n\n#include \n#include \n\n#include \"rte_kvargs.h\"\n\n/*\n * Receive a string with a list of arguments following the pattern\n * key=value;key=value;... and insert them into the list.\n * strtok() is used so the params string will be copied to be modified.\n */\nstatic int\nrte_kvargs_tokenize(struct rte_kvargs *kvlist, const char *params)\n{\n\tunsigned i;\n\tchar *str;\n\tchar *ctx1 = NULL;\n\tchar *ctx2 = NULL;\n\n\t/* Copy the const char *params to a modifiable string\n\t * to pass to rte_strsplit\n\t */\n\tkvlist->str = strdup(params);\n\tif (kvlist->str == NULL) {\n\t\tRTE_LOG(ERR, PMD, \"Cannot parse arguments: not enough memory\\n\");\n\t\treturn -1;\n\t}\n\n\t/* browse each key/value pair and add it in kvlist */\n\tstr = kvlist->str;\n\twhile ((str = strtok_r(str, RTE_KVARGS_PAIRS_DELIM, &ctx1)) != NULL) {\n\n\t\ti = kvlist->count;\n\t\tif (i >= RTE_KVARGS_MAX) {\n\t\t\tRTE_LOG(ERR, PMD, \"Cannot parse arguments: list full\\n\");\n\t\t\treturn -1;\n\t\t}\n\n\t\tkvlist->pairs[i].key = strtok_r(str, RTE_KVARGS_KV_DELIM, &ctx2);\n\t\tkvlist->pairs[i].value = strtok_r(NULL, RTE_KVARGS_KV_DELIM, &ctx2);\n\t\tif (kvlist->pairs[i].key == NULL || kvlist->pairs[i].value == NULL) {\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\"Cannot parse arguments: wrong key or value\\n\"\n\t\t\t\t\"params=<%s>\\n\", params);\n\t\t\treturn -1;\n\t\t}\n\n\t\tkvlist->count++;\n\t\tstr = NULL;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Determine whether a key is valid or not by looking\n * into a list of valid keys.\n */\nstatic int\nis_valid_key(const char *valid[], const char *key_match)\n{\n\tconst char **valid_ptr;\n\n\tfor (valid_ptr = valid; *valid_ptr != NULL; valid_ptr++) {\n\t\tif (strcmp(key_match, *valid_ptr) == 0)\n\t\t\treturn 1;\n\t}\n\treturn 0;\n}\n\n/*\n * Determine whether all keys are valid or not by looking\n * into a list of valid keys.\n */\nstatic int\ncheck_for_valid_keys(struct rte_kvargs *kvlist,\n\t\tconst char *valid[])\n{\n\tunsigned i, ret;\n\tstruct rte_kvargs_pair *pair;\n\n\tfor (i = 0; i < kvlist->count; i++) {\n\t\tpair = &kvlist->pairs[i];\n\t\tret = is_valid_key(valid, pair->key);\n\t\tif (!ret) {\n\t\t\tRTE_LOG(ERR, PMD,\n\t\t\t\t\"Error parsing device, invalid key <%s>\\n\",\n\t\t\t\tpair->key);\n\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\n/*\n * Return the number of times a given arg_name exists in the key/value list.\n * E.g. given a list = { rx = 0, rx = 1, tx = 2 } the number of args for\n * arg \"rx\" will be 2.\n */\nunsigned\nrte_kvargs_count(const struct rte_kvargs *kvlist, const char *key_match)\n{\n\tconst struct rte_kvargs_pair *pair;\n\tunsigned i, ret;\n\n\tret = 0;\n\tfor (i = 0; i < kvlist->count; i++) {\n\t\tpair = &kvlist->pairs[i];\n\t\tif (key_match == NULL || strcmp(pair->key, key_match) == 0)\n\t\t\tret++;\n\t}\n\n\treturn ret;\n}\n\n/*\n * For each matching key, call the given handler function.\n */\nint\nrte_kvargs_process(const struct rte_kvargs *kvlist,\n\t\tconst char *key_match,\n\t\targ_handler_t handler,\n\t\tvoid *opaque_arg)\n{\n\tconst struct rte_kvargs_pair *pair;\n\tunsigned i;\n\n\tfor (i = 0; i < kvlist->count; i++) {\n\t\tpair = &kvlist->pairs[i];\n\t\tif (key_match == NULL || strcmp(pair->key, key_match) == 0) {\n\t\t\tif ((*handler)(pair->key, pair->value, opaque_arg) < 0)\n\t\t\t\treturn -1;\n\t\t}\n\t}\n\treturn 0;\n}\n\n/* free the rte_kvargs structure */\nvoid\nrte_kvargs_free(struct rte_kvargs *kvlist)\n{\n\tif (!kvlist)\n\t\treturn;\n\n\tif (kvlist->str != NULL)\n\t\tfree(kvlist->str);\n\n\tfree(kvlist);\n}\n\n/*\n * Parse the arguments \"key=value;key=value;...\" string and return\n * an allocated structure that contains a key/value list. Also\n * check if only valid keys were used.\n */\nstruct rte_kvargs *\nrte_kvargs_parse(const char *args, const char *valid_keys[])\n{\n\tstruct rte_kvargs *kvlist;\n\n\tkvlist = malloc(sizeof(*kvlist));\n\tif (kvlist == NULL)\n\t\treturn NULL;\n\tmemset(kvlist, 0, sizeof(*kvlist));\n\n\tif (rte_kvargs_tokenize(kvlist, args) < 0) {\n\t\trte_kvargs_free(kvlist);\n\t\treturn NULL;\n\t}\n\n\tif (valid_keys != NULL && check_for_valid_keys(kvlist, valid_keys) < 0) {\n\t\trte_kvargs_free(kvlist);\n\t\treturn NULL;\n\t}\n\n\treturn kvlist;\n}\n" }, { "path": "lib/librte_kvargs/rte_kvargs.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2013 Intel Corporation. All rights reserved.\n * Copyright(c) 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_KVARGS_H_\n#define _RTE_KVARGS_H_\n\n/**\n * @file\n * RTE Argument parsing\n *\n * This module can be used to parse arguments whose format is\n * key1=value1,key2=value2,key3=value3,...\n *\n * The same key can appear several times with the same or a different\n * value. Indeed, the arguments are stored as a list of key/values\n * associations and not as a dictionary.\n *\n * This file provides some helpers that are especially used by virtual\n * ethernet devices at initialization for arguments parsing.\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/** Maximum number of key/value associations */\n#define RTE_KVARGS_MAX 32\n\n/** separator character used between each pair */\n#define RTE_KVARGS_PAIRS_DELIM\t\",\"\n\n/** separator character used between key and value */\n#define RTE_KVARGS_KV_DELIM\t\"=\"\n\n/** Type of callback function used by rte_kvargs_process() */\ntypedef int (*arg_handler_t)(const char *key, const char *value, void *opaque);\n\n/** A key/value association */\nstruct rte_kvargs_pair {\n\tchar *key; /**< the name (key) of the association */\n\tchar *value; /**< the value associated to that key */\n};\n\n/** Store a list of key/value associations */\nstruct rte_kvargs {\n\tchar *str; /**< copy of the argument string */\n\tunsigned count; /**< number of entries in the list */\n\tstruct rte_kvargs_pair pairs[RTE_KVARGS_MAX]; /**< list of key/values */\n};\n\n/**\n * Allocate a rte_kvargs and store key/value associations from a string\n *\n * The function allocates and fills a rte_kvargs structure from a given\n * string whose format is key1=value1,key2=value2,...\n *\n * The structure can be freed with rte_kvargs_free().\n *\n * @param args\n * The input string containing the key/value associations\n * @param valid_keys\n * A list of valid keys (table of const char *, the last must be NULL).\n * This argument is ignored if NULL\n *\n * @return\n * - A pointer to an allocated rte_kvargs structure on success\n * - NULL on error\n */\nstruct rte_kvargs *rte_kvargs_parse(const char *args, const char *valid_keys[]);\n\n/**\n * Free a rte_kvargs structure\n *\n * Free a rte_kvargs structure previously allocated with\n * rte_kvargs_parse().\n *\n * @param kvlist\n * The rte_kvargs structure\n */\nvoid rte_kvargs_free(struct rte_kvargs *kvlist);\n\n/**\n * Call a handler function for each key/value matching the key\n *\n * For each key/value association that matches the given key, calls the\n * handler function with the for a given arg_name passing the value on the\n * dictionary for that key and a given extra argument. If *kvlist* is NULL\n * function does nothing.\n *\n * @param kvlist\n * The rte_kvargs structure\n * @param key_match\n * The key on which the handler should be called, or NULL to process handler\n * on all associations\n * @param handler\n * The function to call for each matching key\n * @param opaque_arg\n * A pointer passed unchanged to the handler\n *\n * @return\n * - 0 on success\n * - Negative on error\n */\nint rte_kvargs_process(const struct rte_kvargs *kvlist,\n\tconst char *key_match, arg_handler_t handler, void *opaque_arg);\n\n/**\n * Count the number of associations matching the given key\n *\n * @param kvlist\n * The rte_kvargs structure\n * @param key_match\n * The key that should match, or NULL to count all associations\n\n * @return\n * The number of entries\n */\nunsigned rte_kvargs_count(const struct rte_kvargs *kvlist,\n\tconst char *key_match);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_lpm/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_lpm.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR)\n\nEXPORT_MAP := rte_lpm_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_LPM) := rte_lpm.c rte_lpm6.c\n\n# install this header file\nSYMLINK-$(CONFIG_RTE_LIBRTE_LPM)-include := rte_lpm.h rte_lpm6.h\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_LPM) += lib/librte_eal\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_lpm/rte_lpm.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include /* for definition of RTE_CACHE_LINE_SIZE */\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_lpm.h\"\n\nTAILQ_HEAD(rte_lpm_list, rte_tailq_entry);\n\nstatic struct rte_tailq_elem rte_lpm_tailq = {\n\t.name = \"RTE_LPM\",\n};\nEAL_REGISTER_TAILQ(rte_lpm_tailq)\n\n#define MAX_DEPTH_TBL24 24\n\nenum valid_flag {\n\tINVALID = 0,\n\tVALID\n};\n\n/* Macro to enable/disable run-time checks. */\n#if defined(RTE_LIBRTE_LPM_DEBUG)\n#include \n#define VERIFY_DEPTH(depth) do { \\\n\tif ((depth == 0) || (depth > RTE_LPM_MAX_DEPTH)) \\\n\t\trte_panic(\"LPM: Invalid depth (%u) at line %d\", \\\n\t\t\t\t(unsigned)(depth), __LINE__); \\\n} while (0)\n#else\n#define VERIFY_DEPTH(depth)\n#endif\n\n/*\n * Converts a given depth value to its corresponding mask value.\n *\n * depth (IN)\t\t: range = 1 - 32\n * mask (OUT)\t\t: 32bit mask\n */\nstatic uint32_t __attribute__((pure))\ndepth_to_mask(uint8_t depth)\n{\n\tVERIFY_DEPTH(depth);\n\n\t/* To calculate a mask start with a 1 on the left hand side and right\n\t * shift while populating the left hand side with 1's\n\t */\n\treturn (int)0x80000000 >> (depth - 1);\n}\n\n/*\n * Converts given depth value to its corresponding range value.\n */\nstatic inline uint32_t __attribute__((pure))\ndepth_to_range(uint8_t depth)\n{\n\tVERIFY_DEPTH(depth);\n\n\t/*\n\t * Calculate tbl24 range. (Note: 2^depth = 1 << depth)\n\t */\n\tif (depth <= MAX_DEPTH_TBL24)\n\t\treturn 1 << (MAX_DEPTH_TBL24 - depth);\n\n\t/* Else if depth is greater than 24 */\n\treturn (1 << (RTE_LPM_MAX_DEPTH - depth));\n}\n\n/*\n * Find an existing lpm table and return a pointer to it.\n */\nstruct rte_lpm *\nrte_lpm_find_existing(const char *name)\n{\n\tstruct rte_lpm *l = NULL;\n\tstruct rte_tailq_entry *te;\n\tstruct rte_lpm_list *lpm_list;\n\n\tlpm_list = RTE_TAILQ_CAST(rte_lpm_tailq.head, rte_lpm_list);\n\n\trte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);\n\tTAILQ_FOREACH(te, lpm_list, next) {\n\t\tl = (struct rte_lpm *) te->data;\n\t\tif (strncmp(name, l->name, RTE_LPM_NAMESIZE) == 0)\n\t\t\tbreak;\n\t}\n\trte_rwlock_read_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\tif (te == NULL) {\n\t\trte_errno = ENOENT;\n\t\treturn NULL;\n\t}\n\n\treturn l;\n}\n\n/*\n * Allocates memory for LPM object\n */\nstruct rte_lpm *\nrte_lpm_create(const char *name, int socket_id, int max_rules,\n\t\t__rte_unused int flags)\n{\n\tchar mem_name[RTE_LPM_NAMESIZE];\n\tstruct rte_lpm *lpm = NULL;\n\tstruct rte_tailq_entry *te;\n\tuint32_t mem_size;\n\tstruct rte_lpm_list *lpm_list;\n\n\tlpm_list = RTE_TAILQ_CAST(rte_lpm_tailq.head, rte_lpm_list);\n\n\tRTE_BUILD_BUG_ON(sizeof(struct rte_lpm_tbl24_entry) != 2);\n\tRTE_BUILD_BUG_ON(sizeof(struct rte_lpm_tbl8_entry) != 2);\n\n\t/* Check user arguments. */\n\tif ((name == NULL) || (socket_id < -1) || (max_rules == 0)){\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\tsnprintf(mem_name, sizeof(mem_name), \"LPM_%s\", name);\n\n\t/* Determine the amount of memory to allocate. */\n\tmem_size = sizeof(*lpm) + (sizeof(lpm->rules_tbl[0]) * max_rules);\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* guarantee there's no existing */\n\tTAILQ_FOREACH(te, lpm_list, next) {\n\t\tlpm = (struct rte_lpm *) te->data;\n\t\tif (strncmp(name, lpm->name, RTE_LPM_NAMESIZE) == 0)\n\t\t\tbreak;\n\t}\n\tif (te != NULL)\n\t\tgoto exit;\n\n\t/* allocate tailq entry */\n\tte = rte_zmalloc(\"LPM_TAILQ_ENTRY\", sizeof(*te), 0);\n\tif (te == NULL) {\n\t\tRTE_LOG(ERR, LPM, \"Failed to allocate tailq entry\\n\");\n\t\tgoto exit;\n\t}\n\n\t/* Allocate memory to store the LPM data structures. */\n\tlpm = (struct rte_lpm *)rte_zmalloc_socket(mem_name, mem_size,\n\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (lpm == NULL) {\n\t\tRTE_LOG(ERR, LPM, \"LPM memory allocation failed\\n\");\n\t\trte_free(te);\n\t\tgoto exit;\n\t}\n\n\t/* Save user arguments. */\n\tlpm->max_rules = max_rules;\n\tsnprintf(lpm->name, sizeof(lpm->name), \"%s\", name);\n\n\tte->data = (void *) lpm;\n\n\tTAILQ_INSERT_TAIL(lpm_list, te, next);\n\nexit:\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\treturn lpm;\n}\n\n/*\n * Deallocates memory for given LPM table.\n */\nvoid\nrte_lpm_free(struct rte_lpm *lpm)\n{\n\tstruct rte_lpm_list *lpm_list;\n\tstruct rte_tailq_entry *te;\n\n\t/* Check user arguments. */\n\tif (lpm == NULL)\n\t\treturn;\n\n\tlpm_list = RTE_TAILQ_CAST(rte_lpm_tailq.head, rte_lpm_list);\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* find our tailq entry */\n\tTAILQ_FOREACH(te, lpm_list, next) {\n\t\tif (te->data == (void *) lpm)\n\t\t\tbreak;\n\t}\n\tif (te == NULL) {\n\t\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\t\treturn;\n\t}\n\n\tTAILQ_REMOVE(lpm_list, te, next);\n\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\trte_free(lpm);\n\trte_free(te);\n}\n\n/*\n * Adds a rule to the rule table.\n *\n * NOTE: The rule table is split into 32 groups. Each group contains rules that\n * apply to a specific prefix depth (i.e. group 1 contains rules that apply to\n * prefixes with a depth of 1 etc.). In the following code (depth - 1) is used\n * to refer to depth 1 because even though the depth range is 1 - 32, depths\n * are stored in the rule table from 0 - 31.\n * NOTE: Valid range for depth parameter is 1 .. 32 inclusive.\n */\nstatic inline int32_t\nrule_add(struct rte_lpm *lpm, uint32_t ip_masked, uint8_t depth,\n\tuint8_t next_hop)\n{\n\tuint32_t rule_gindex, rule_index, last_rule;\n\tint i;\n\n\tVERIFY_DEPTH(depth);\n\n\t/* Scan through rule group to see if rule already exists. */\n\tif (lpm->rule_info[depth - 1].used_rules > 0) {\n\n\t\t/* rule_gindex stands for rule group index. */\n\t\trule_gindex = lpm->rule_info[depth - 1].first_rule;\n\t\t/* Initialise rule_index to point to start of rule group. */\n\t\trule_index = rule_gindex;\n\t\t/* Last rule = Last used rule in this rule group. */\n\t\tlast_rule = rule_gindex + lpm->rule_info[depth - 1].used_rules;\n\n\t\tfor (; rule_index < last_rule; rule_index++) {\n\n\t\t\t/* If rule already exists update its next_hop and return. */\n\t\t\tif (lpm->rules_tbl[rule_index].ip == ip_masked) {\n\t\t\t\tlpm->rules_tbl[rule_index].next_hop = next_hop;\n\n\t\t\t\treturn rule_index;\n\t\t\t}\n\t\t}\n\n\t\tif (rule_index == lpm->max_rules)\n\t\t\treturn -ENOSPC;\n\t} else {\n\t\t/* Calculate the position in which the rule will be stored. */\n\t\trule_index = 0;\n\n\t\tfor (i = depth - 1; i > 0; i--) {\n\t\t\tif (lpm->rule_info[i - 1].used_rules > 0) {\n\t\t\t\trule_index = lpm->rule_info[i - 1].first_rule + lpm->rule_info[i - 1].used_rules;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tif (rule_index == lpm->max_rules)\n\t\t\treturn -ENOSPC;\n\n\t\tlpm->rule_info[depth - 1].first_rule = rule_index;\n\t}\n\n\t/* Make room for the new rule in the array. */\n\tfor (i = RTE_LPM_MAX_DEPTH; i > depth; i--) {\n\t\tif (lpm->rule_info[i - 1].first_rule + lpm->rule_info[i - 1].used_rules == lpm->max_rules)\n\t\t\treturn -ENOSPC;\n\n\t\tif (lpm->rule_info[i - 1].used_rules > 0) {\n\t\t\tlpm->rules_tbl[lpm->rule_info[i - 1].first_rule + lpm->rule_info[i - 1].used_rules]\n\t\t\t\t\t= lpm->rules_tbl[lpm->rule_info[i - 1].first_rule];\n\t\t\tlpm->rule_info[i - 1].first_rule++;\n\t\t}\n\t}\n\n\t/* Add the new rule. */\n\tlpm->rules_tbl[rule_index].ip = ip_masked;\n\tlpm->rules_tbl[rule_index].next_hop = next_hop;\n\n\t/* Increment the used rules counter for this rule group. */\n\tlpm->rule_info[depth - 1].used_rules++;\n\n\treturn rule_index;\n}\n\n/*\n * Delete a rule from the rule table.\n * NOTE: Valid range for depth parameter is 1 .. 32 inclusive.\n */\nstatic inline void\nrule_delete(struct rte_lpm *lpm, int32_t rule_index, uint8_t depth)\n{\n\tint i;\n\n\tVERIFY_DEPTH(depth);\n\n\tlpm->rules_tbl[rule_index] = lpm->rules_tbl[lpm->rule_info[depth - 1].first_rule\n\t\t\t+ lpm->rule_info[depth - 1].used_rules - 1];\n\n\tfor (i = depth; i < RTE_LPM_MAX_DEPTH; i++) {\n\t\tif (lpm->rule_info[i].used_rules > 0) {\n\t\t\tlpm->rules_tbl[lpm->rule_info[i].first_rule - 1] =\n\t\t\t\t\tlpm->rules_tbl[lpm->rule_info[i].first_rule + lpm->rule_info[i].used_rules - 1];\n\t\t\tlpm->rule_info[i].first_rule--;\n\t\t}\n\t}\n\n\tlpm->rule_info[depth - 1].used_rules--;\n}\n\n/*\n * Finds a rule in rule table.\n * NOTE: Valid range for depth parameter is 1 .. 32 inclusive.\n */\nstatic inline int32_t\nrule_find(struct rte_lpm *lpm, uint32_t ip_masked, uint8_t depth)\n{\n\tuint32_t rule_gindex, last_rule, rule_index;\n\n\tVERIFY_DEPTH(depth);\n\n\trule_gindex = lpm->rule_info[depth - 1].first_rule;\n\tlast_rule = rule_gindex + lpm->rule_info[depth - 1].used_rules;\n\n\t/* Scan used rules at given depth to find rule. */\n\tfor (rule_index = rule_gindex; rule_index < last_rule; rule_index++) {\n\t\t/* If rule is found return the rule index. */\n\t\tif (lpm->rules_tbl[rule_index].ip == ip_masked)\n\t\t\treturn rule_index;\n\t}\n\n\t/* If rule is not found return -EINVAL. */\n\treturn -EINVAL;\n}\n\n/*\n * Find, clean and allocate a tbl8.\n */\nstatic inline int32_t\ntbl8_alloc(struct rte_lpm_tbl8_entry *tbl8)\n{\n\tuint32_t tbl8_gindex; /* tbl8 group index. */\n\tstruct rte_lpm_tbl8_entry *tbl8_entry;\n\n\t/* Scan through tbl8 to find a free (i.e. INVALID) tbl8 group. */\n\tfor (tbl8_gindex = 0; tbl8_gindex < RTE_LPM_TBL8_NUM_GROUPS;\n\t\t\ttbl8_gindex++) {\n\t\ttbl8_entry = &tbl8[tbl8_gindex *\n\t\t RTE_LPM_TBL8_GROUP_NUM_ENTRIES];\n\t\t/* If a free tbl8 group is found clean it and set as VALID. */\n\t\tif (!tbl8_entry->valid_group) {\n\t\t\tmemset(&tbl8_entry[0], 0,\n\t\t\t\t\tRTE_LPM_TBL8_GROUP_NUM_ENTRIES *\n\t\t\t\t\tsizeof(tbl8_entry[0]));\n\n\t\t\ttbl8_entry->valid_group = VALID;\n\n\t\t\t/* Return group index for allocated tbl8 group. */\n\t\t\treturn tbl8_gindex;\n\t\t}\n\t}\n\n\t/* If there are no tbl8 groups free then return error. */\n\treturn -ENOSPC;\n}\n\nstatic inline void\ntbl8_free(struct rte_lpm_tbl8_entry *tbl8, uint32_t tbl8_group_start)\n{\n\t/* Set tbl8 group invalid*/\n\ttbl8[tbl8_group_start].valid_group = INVALID;\n}\n\nstatic inline int32_t\nadd_depth_small(struct rte_lpm *lpm, uint32_t ip, uint8_t depth,\n\t\tuint8_t next_hop)\n{\n\tuint32_t tbl24_index, tbl24_range, tbl8_index, tbl8_group_end, i, j;\n\n\t/* Calculate the index into Table24. */\n\ttbl24_index = ip >> 8;\n\ttbl24_range = depth_to_range(depth);\n\n\tfor (i = tbl24_index; i < (tbl24_index + tbl24_range); i++) {\n\t\t/*\n\t\t * For invalid OR valid and non-extended tbl 24 entries set\n\t\t * entry.\n\t\t */\n\t\tif (!lpm->tbl24[i].valid || (lpm->tbl24[i].ext_entry == 0 &&\n\t\t\t\tlpm->tbl24[i].depth <= depth)) {\n\n\t\t\tstruct rte_lpm_tbl24_entry new_tbl24_entry = {\n\t\t\t\t{ .next_hop = next_hop, },\n\t\t\t\t.valid = VALID,\n\t\t\t\t.ext_entry = 0,\n\t\t\t\t.depth = depth,\n\t\t\t};\n\n\t\t\t/* Setting tbl24 entry in one go to avoid race\n\t\t\t * conditions\n\t\t\t */\n\t\t\tlpm->tbl24[i] = new_tbl24_entry;\n\n\t\t\tcontinue;\n\t\t}\n\n\t\tif (lpm->tbl24[i].ext_entry == 1) {\n\t\t\t/* If tbl24 entry is valid and extended calculate the\n\t\t\t * index into tbl8.\n\t\t\t */\n\t\t\ttbl8_index = lpm->tbl24[i].tbl8_gindex *\n\t\t\t\t\tRTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\t\t\ttbl8_group_end = tbl8_index +\n\t\t\t\t\tRTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\n\t\t\tfor (j = tbl8_index; j < tbl8_group_end; j++) {\n\t\t\t\tif (!lpm->tbl8[j].valid ||\n\t\t\t\t\t\tlpm->tbl8[j].depth <= depth) {\n\t\t\t\t\tstruct rte_lpm_tbl8_entry\n\t\t\t\t\t\tnew_tbl8_entry = {\n\t\t\t\t\t\t.valid = VALID,\n\t\t\t\t\t\t.valid_group = VALID,\n\t\t\t\t\t\t.depth = depth,\n\t\t\t\t\t\t.next_hop = next_hop,\n\t\t\t\t\t};\n\n\t\t\t\t\t/*\n\t\t\t\t\t * Setting tbl8 entry in one go to avoid\n\t\t\t\t\t * race conditions\n\t\t\t\t\t */\n\t\t\t\t\tlpm->tbl8[j] = new_tbl8_entry;\n\n\t\t\t\t\tcontinue;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic inline int32_t\nadd_depth_big(struct rte_lpm *lpm, uint32_t ip_masked, uint8_t depth,\n\t\tuint8_t next_hop)\n{\n\tuint32_t tbl24_index;\n\tint32_t tbl8_group_index, tbl8_group_start, tbl8_group_end, tbl8_index,\n\t\ttbl8_range, i;\n\n\ttbl24_index = (ip_masked >> 8);\n\ttbl8_range = depth_to_range(depth);\n\n\tif (!lpm->tbl24[tbl24_index].valid) {\n\t\t/* Search for a free tbl8 group. */\n\t\ttbl8_group_index = tbl8_alloc(lpm->tbl8);\n\n\t\t/* Check tbl8 allocation was successful. */\n\t\tif (tbl8_group_index < 0) {\n\t\t\treturn tbl8_group_index;\n\t\t}\n\n\t\t/* Find index into tbl8 and range. */\n\t\ttbl8_index = (tbl8_group_index *\n\t\t\t\tRTE_LPM_TBL8_GROUP_NUM_ENTRIES) +\n\t\t\t\t(ip_masked & 0xFF);\n\n\t\t/* Set tbl8 entry. */\n\t\tfor (i = tbl8_index; i < (tbl8_index + tbl8_range); i++) {\n\t\t\tlpm->tbl8[i].depth = depth;\n\t\t\tlpm->tbl8[i].next_hop = next_hop;\n\t\t\tlpm->tbl8[i].valid = VALID;\n\t\t}\n\n\t\t/*\n\t\t * Update tbl24 entry to point to new tbl8 entry. Note: The\n\t\t * ext_flag and tbl8_index need to be updated simultaneously,\n\t\t * so assign whole structure in one go\n\t\t */\n\n\t\tstruct rte_lpm_tbl24_entry new_tbl24_entry = {\n\t\t\t{ .tbl8_gindex = (uint8_t)tbl8_group_index, },\n\t\t\t.valid = VALID,\n\t\t\t.ext_entry = 1,\n\t\t\t.depth = 0,\n\t\t};\n\n\t\tlpm->tbl24[tbl24_index] = new_tbl24_entry;\n\n\t}/* If valid entry but not extended calculate the index into Table8. */\n\telse if (lpm->tbl24[tbl24_index].ext_entry == 0) {\n\t\t/* Search for free tbl8 group. */\n\t\ttbl8_group_index = tbl8_alloc(lpm->tbl8);\n\n\t\tif (tbl8_group_index < 0) {\n\t\t\treturn tbl8_group_index;\n\t\t}\n\n\t\ttbl8_group_start = tbl8_group_index *\n\t\t\t\tRTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\t\ttbl8_group_end = tbl8_group_start +\n\t\t\t\tRTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\n\t\t/* Populate new tbl8 with tbl24 value. */\n\t\tfor (i = tbl8_group_start; i < tbl8_group_end; i++) {\n\t\t\tlpm->tbl8[i].valid = VALID;\n\t\t\tlpm->tbl8[i].depth = lpm->tbl24[tbl24_index].depth;\n\t\t\tlpm->tbl8[i].next_hop =\n\t\t\t\t\tlpm->tbl24[tbl24_index].next_hop;\n\t\t}\n\n\t\ttbl8_index = tbl8_group_start + (ip_masked & 0xFF);\n\n\t\t/* Insert new rule into the tbl8 entry. */\n\t\tfor (i = tbl8_index; i < tbl8_index + tbl8_range; i++) {\n\t\t\tif (!lpm->tbl8[i].valid ||\n\t\t\t\t\tlpm->tbl8[i].depth <= depth) {\n\t\t\t\tlpm->tbl8[i].valid = VALID;\n\t\t\t\tlpm->tbl8[i].depth = depth;\n\t\t\t\tlpm->tbl8[i].next_hop = next_hop;\n\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\n\t\t/*\n\t\t * Update tbl24 entry to point to new tbl8 entry. Note: The\n\t\t * ext_flag and tbl8_index need to be updated simultaneously,\n\t\t * so assign whole structure in one go.\n\t\t */\n\n\t\tstruct rte_lpm_tbl24_entry new_tbl24_entry = {\n\t\t\t\t{ .tbl8_gindex = (uint8_t)tbl8_group_index, },\n\t\t\t\t.valid = VALID,\n\t\t\t\t.ext_entry = 1,\n\t\t\t\t.depth = 0,\n\t\t};\n\n\t\tlpm->tbl24[tbl24_index] = new_tbl24_entry;\n\n\t}\n\telse { /*\n\t\t* If it is valid, extended entry calculate the index into tbl8.\n\t\t*/\n\t\ttbl8_group_index = lpm->tbl24[tbl24_index].tbl8_gindex;\n\t\ttbl8_group_start = tbl8_group_index *\n\t\t\t\tRTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\t\ttbl8_index = tbl8_group_start + (ip_masked & 0xFF);\n\n\t\tfor (i = tbl8_index; i < (tbl8_index + tbl8_range); i++) {\n\n\t\t\tif (!lpm->tbl8[i].valid ||\n\t\t\t\t\tlpm->tbl8[i].depth <= depth) {\n\t\t\t\tstruct rte_lpm_tbl8_entry new_tbl8_entry = {\n\t\t\t\t\t.valid = VALID,\n\t\t\t\t\t.depth = depth,\n\t\t\t\t\t.next_hop = next_hop,\n\t\t\t\t\t.valid_group = lpm->tbl8[i].valid_group,\n\t\t\t\t};\n\n\t\t\t\t/*\n\t\t\t\t * Setting tbl8 entry in one go to avoid race\n\t\t\t\t * condition\n\t\t\t\t */\n\t\t\t\tlpm->tbl8[i] = new_tbl8_entry;\n\n\t\t\t\tcontinue;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/*\n * Add a route\n */\nint\nrte_lpm_add(struct rte_lpm *lpm, uint32_t ip, uint8_t depth,\n\t\tuint8_t next_hop)\n{\n\tint32_t rule_index, status = 0;\n\tuint32_t ip_masked;\n\n\t/* Check user arguments. */\n\tif ((lpm == NULL) || (depth < 1) || (depth > RTE_LPM_MAX_DEPTH))\n\t\treturn -EINVAL;\n\n\tip_masked = ip & depth_to_mask(depth);\n\n\t/* Add the rule to the rule table. */\n\trule_index = rule_add(lpm, ip_masked, depth, next_hop);\n\n\t/* If the is no space available for new rule return error. */\n\tif (rule_index < 0) {\n\t\treturn rule_index;\n\t}\n\n\tif (depth <= MAX_DEPTH_TBL24) {\n\t\tstatus = add_depth_small(lpm, ip_masked, depth, next_hop);\n\t}\n\telse { /* If depth > RTE_LPM_MAX_DEPTH_TBL24 */\n\t\tstatus = add_depth_big(lpm, ip_masked, depth, next_hop);\n\n\t\t/*\n\t\t * If add fails due to exhaustion of tbl8 extensions delete\n\t\t * rule that was added to rule table.\n\t\t */\n\t\tif (status < 0) {\n\t\t\trule_delete(lpm, rule_index, depth);\n\n\t\t\treturn status;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/*\n * Look for a rule in the high-level rules table\n */\nint\nrte_lpm_is_rule_present(struct rte_lpm *lpm, uint32_t ip, uint8_t depth,\nuint8_t *next_hop)\n{\n\tuint32_t ip_masked;\n\tint32_t rule_index;\n\n\t/* Check user arguments. */\n\tif ((lpm == NULL) ||\n\t\t(next_hop == NULL) ||\n\t\t(depth < 1) || (depth > RTE_LPM_MAX_DEPTH))\n\t\treturn -EINVAL;\n\n\t/* Look for the rule using rule_find. */\n\tip_masked = ip & depth_to_mask(depth);\n\trule_index = rule_find(lpm, ip_masked, depth);\n\n\tif (rule_index >= 0) {\n\t\t*next_hop = lpm->rules_tbl[rule_index].next_hop;\n\t\treturn 1;\n\t}\n\n\t/* If rule is not found return 0. */\n\treturn 0;\n}\n\nstatic inline int32_t\nfind_previous_rule(struct rte_lpm *lpm, uint32_t ip, uint8_t depth, uint8_t *sub_rule_depth)\n{\n\tint32_t rule_index;\n\tuint32_t ip_masked;\n\tuint8_t prev_depth;\n\n\tfor (prev_depth = (uint8_t)(depth - 1); prev_depth > 0; prev_depth--) {\n\t\tip_masked = ip & depth_to_mask(prev_depth);\n\n\t\trule_index = rule_find(lpm, ip_masked, prev_depth);\n\n\t\tif (rule_index >= 0) {\n\t\t\t*sub_rule_depth = prev_depth;\n\t\t\treturn rule_index;\n\t\t}\n\t}\n\n\treturn -1;\n}\n\nstatic inline int32_t\ndelete_depth_small(struct rte_lpm *lpm, uint32_t ip_masked,\n\tuint8_t depth, int32_t sub_rule_index, uint8_t sub_rule_depth)\n{\n\tuint32_t tbl24_range, tbl24_index, tbl8_group_index, tbl8_index, i, j;\n\n\t/* Calculate the range and index into Table24. */\n\ttbl24_range = depth_to_range(depth);\n\ttbl24_index = (ip_masked >> 8);\n\n\t/*\n\t * Firstly check the sub_rule_index. A -1 indicates no replacement rule\n\t * and a positive number indicates a sub_rule_index.\n\t */\n\tif (sub_rule_index < 0) {\n\t\t/*\n\t\t * If no replacement rule exists then invalidate entries\n\t\t * associated with this rule.\n\t\t */\n\t\tfor (i = tbl24_index; i < (tbl24_index + tbl24_range); i++) {\n\n\t\t\tif (lpm->tbl24[i].ext_entry == 0 &&\n\t\t\t\t\tlpm->tbl24[i].depth <= depth ) {\n\t\t\t\tlpm->tbl24[i].valid = INVALID;\n\t\t\t}\n\t\t\telse {\n\t\t\t\t/*\n\t\t\t\t * If TBL24 entry is extended, then there has\n\t\t\t\t * to be a rule with depth >= 25 in the\n\t\t\t\t * associated TBL8 group.\n\t\t\t\t */\n\n\t\t\t\ttbl8_group_index = lpm->tbl24[i].tbl8_gindex;\n\t\t\t\ttbl8_index = tbl8_group_index *\n\t\t\t\t\t\tRTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\n\t\t\t\tfor (j = tbl8_index; j < (tbl8_index +\n\t\t\t\t\tRTE_LPM_TBL8_GROUP_NUM_ENTRIES); j++) {\n\n\t\t\t\t\tif (lpm->tbl8[j].depth <= depth)\n\t\t\t\t\t\tlpm->tbl8[j].valid = INVALID;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\telse {\n\t\t/*\n\t\t * If a replacement rule exists then modify entries\n\t\t * associated with this rule.\n\t\t */\n\n\t\tstruct rte_lpm_tbl24_entry new_tbl24_entry = {\n\t\t\t{.next_hop = lpm->rules_tbl[sub_rule_index].next_hop,},\n\t\t\t.valid = VALID,\n\t\t\t.ext_entry = 0,\n\t\t\t.depth = sub_rule_depth,\n\t\t};\n\n\t\tstruct rte_lpm_tbl8_entry new_tbl8_entry = {\n\t\t\t.valid = VALID,\n\t\t\t.depth = sub_rule_depth,\n\t\t\t.next_hop = lpm->rules_tbl\n\t\t\t[sub_rule_index].next_hop,\n\t\t};\n\n\t\tfor (i = tbl24_index; i < (tbl24_index + tbl24_range); i++) {\n\n\t\t\tif (lpm->tbl24[i].ext_entry == 0 &&\n\t\t\t\t\tlpm->tbl24[i].depth <= depth ) {\n\t\t\t\tlpm->tbl24[i] = new_tbl24_entry;\n\t\t\t}\n\t\t\telse {\n\t\t\t\t/*\n\t\t\t\t * If TBL24 entry is extended, then there has\n\t\t\t\t * to be a rule with depth >= 25 in the\n\t\t\t\t * associated TBL8 group.\n\t\t\t\t */\n\n\t\t\t\ttbl8_group_index = lpm->tbl24[i].tbl8_gindex;\n\t\t\t\ttbl8_index = tbl8_group_index *\n\t\t\t\t\t\tRTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\n\t\t\t\tfor (j = tbl8_index; j < (tbl8_index +\n\t\t\t\t\tRTE_LPM_TBL8_GROUP_NUM_ENTRIES); j++) {\n\n\t\t\t\t\tif (lpm->tbl8[j].depth <= depth)\n\t\t\t\t\t\tlpm->tbl8[j] = new_tbl8_entry;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/*\n * Checks if table 8 group can be recycled.\n *\n * Return of -EEXIST means tbl8 is in use and thus can not be recycled.\n * Return of -EINVAL means tbl8 is empty and thus can be recycled\n * Return of value > -1 means tbl8 is in use but has all the same values and\n * thus can be recycled\n */\nstatic inline int32_t\ntbl8_recycle_check(struct rte_lpm_tbl8_entry *tbl8, uint32_t tbl8_group_start)\n{\n\tuint32_t tbl8_group_end, i;\n\ttbl8_group_end = tbl8_group_start + RTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\n\t/*\n\t * Check the first entry of the given tbl8. If it is invalid we know\n\t * this tbl8 does not contain any rule with a depth < RTE_LPM_MAX_DEPTH\n\t * (As they would affect all entries in a tbl8) and thus this table\n\t * can not be recycled.\n\t */\n\tif (tbl8[tbl8_group_start].valid) {\n\t\t/*\n\t\t * If first entry is valid check if the depth is less than 24\n\t\t * and if so check the rest of the entries to verify that they\n\t\t * are all of this depth.\n\t\t */\n\t\tif (tbl8[tbl8_group_start].depth < MAX_DEPTH_TBL24) {\n\t\t\tfor (i = (tbl8_group_start + 1); i < tbl8_group_end;\n\t\t\t\t\ti++) {\n\n\t\t\t\tif (tbl8[i].depth !=\n\t\t\t\t\t\ttbl8[tbl8_group_start].depth) {\n\n\t\t\t\t\treturn -EEXIST;\n\t\t\t\t}\n\t\t\t}\n\t\t\t/* If all entries are the same return the tb8 index */\n\t\t\treturn tbl8_group_start;\n\t\t}\n\n\t\treturn -EEXIST;\n\t}\n\t/*\n\t * If the first entry is invalid check if the rest of the entries in\n\t * the tbl8 are invalid.\n\t */\n\tfor (i = (tbl8_group_start + 1); i < tbl8_group_end; i++) {\n\t\tif (tbl8[i].valid)\n\t\t\treturn -EEXIST;\n\t}\n\t/* If no valid entries are found then return -EINVAL. */\n\treturn -EINVAL;\n}\n\nstatic inline int32_t\ndelete_depth_big(struct rte_lpm *lpm, uint32_t ip_masked,\n\tuint8_t depth, int32_t sub_rule_index, uint8_t sub_rule_depth)\n{\n\tuint32_t tbl24_index, tbl8_group_index, tbl8_group_start, tbl8_index,\n\t\t\ttbl8_range, i;\n\tint32_t tbl8_recycle_index;\n\n\t/*\n\t * Calculate the index into tbl24 and range. Note: All depths larger\n\t * than MAX_DEPTH_TBL24 are associated with only one tbl24 entry.\n\t */\n\ttbl24_index = ip_masked >> 8;\n\n\t/* Calculate the index into tbl8 and range. */\n\ttbl8_group_index = lpm->tbl24[tbl24_index].tbl8_gindex;\n\ttbl8_group_start = tbl8_group_index * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\ttbl8_index = tbl8_group_start + (ip_masked & 0xFF);\n\ttbl8_range = depth_to_range(depth);\n\n\tif (sub_rule_index < 0) {\n\t\t/*\n\t\t * Loop through the range of entries on tbl8 for which the\n\t\t * rule_to_delete must be removed or modified.\n\t\t */\n\t\tfor (i = tbl8_index; i < (tbl8_index + tbl8_range); i++) {\n\t\t\tif (lpm->tbl8[i].depth <= depth)\n\t\t\t\tlpm->tbl8[i].valid = INVALID;\n\t\t}\n\t}\n\telse {\n\t\t/* Set new tbl8 entry. */\n\t\tstruct rte_lpm_tbl8_entry new_tbl8_entry = {\n\t\t\t.valid = VALID,\n\t\t\t.depth = sub_rule_depth,\n\t\t\t.valid_group = lpm->tbl8[tbl8_group_start].valid_group,\n\t\t\t.next_hop = lpm->rules_tbl[sub_rule_index].next_hop,\n\t\t};\n\n\t\t/*\n\t\t * Loop through the range of entries on tbl8 for which the\n\t\t * rule_to_delete must be modified.\n\t\t */\n\t\tfor (i = tbl8_index; i < (tbl8_index + tbl8_range); i++) {\n\t\t\tif (lpm->tbl8[i].depth <= depth)\n\t\t\t\tlpm->tbl8[i] = new_tbl8_entry;\n\t\t}\n\t}\n\n\t/*\n\t * Check if there are any valid entries in this tbl8 group. If all\n\t * tbl8 entries are invalid we can free the tbl8 and invalidate the\n\t * associated tbl24 entry.\n\t */\n\n\ttbl8_recycle_index = tbl8_recycle_check(lpm->tbl8, tbl8_group_start);\n\n\tif (tbl8_recycle_index == -EINVAL){\n\t\t/* Set tbl24 before freeing tbl8 to avoid race condition. */\n\t\tlpm->tbl24[tbl24_index].valid = 0;\n\t\ttbl8_free(lpm->tbl8, tbl8_group_start);\n\t}\n\telse if (tbl8_recycle_index > -1) {\n\t\t/* Update tbl24 entry. */\n\t\tstruct rte_lpm_tbl24_entry new_tbl24_entry = {\n\t\t\t{ .next_hop = lpm->tbl8[tbl8_recycle_index].next_hop, },\n\t\t\t.valid = VALID,\n\t\t\t.ext_entry = 0,\n\t\t\t.depth = lpm->tbl8[tbl8_recycle_index].depth,\n\t\t};\n\n\t\t/* Set tbl24 before freeing tbl8 to avoid race condition. */\n\t\tlpm->tbl24[tbl24_index] = new_tbl24_entry;\n\t\ttbl8_free(lpm->tbl8, tbl8_group_start);\n\t}\n\n\treturn 0;\n}\n\n/*\n * Deletes a rule\n */\nint\nrte_lpm_delete(struct rte_lpm *lpm, uint32_t ip, uint8_t depth)\n{\n\tint32_t rule_to_delete_index, sub_rule_index;\n\tuint32_t ip_masked;\n\tuint8_t sub_rule_depth;\n\t/*\n\t * Check input arguments. Note: IP must be a positive integer of 32\n\t * bits in length therefore it need not be checked.\n\t */\n\tif ((lpm == NULL) || (depth < 1) || (depth > RTE_LPM_MAX_DEPTH)) {\n\t\treturn -EINVAL;\n\t}\n\n\tip_masked = ip & depth_to_mask(depth);\n\n\t/*\n\t * Find the index of the input rule, that needs to be deleted, in the\n\t * rule table.\n\t */\n\trule_to_delete_index = rule_find(lpm, ip_masked, depth);\n\n\t/*\n\t * Check if rule_to_delete_index was found. If no rule was found the\n\t * function rule_find returns -EINVAL.\n\t */\n\tif (rule_to_delete_index < 0)\n\t\treturn -EINVAL;\n\n\t/* Delete the rule from the rule table. */\n\trule_delete(lpm, rule_to_delete_index, depth);\n\n\t/*\n\t * Find rule to replace the rule_to_delete. If there is no rule to\n\t * replace the rule_to_delete we return -1 and invalidate the table\n\t * entries associated with this rule.\n\t */\n\tsub_rule_depth = 0;\n\tsub_rule_index = find_previous_rule(lpm, ip, depth, &sub_rule_depth);\n\n\t/*\n\t * If the input depth value is less than 25 use function\n\t * delete_depth_small otherwise use delete_depth_big.\n\t */\n\tif (depth <= MAX_DEPTH_TBL24) {\n\t\treturn delete_depth_small(lpm, ip_masked, depth,\n\t\t\t\tsub_rule_index, sub_rule_depth);\n\t}\n\telse { /* If depth > MAX_DEPTH_TBL24 */\n\t\treturn delete_depth_big(lpm, ip_masked, depth, sub_rule_index, sub_rule_depth);\n\t}\n}\n\n/*\n * Delete all rules from the LPM table.\n */\nvoid\nrte_lpm_delete_all(struct rte_lpm *lpm)\n{\n\t/* Zero rule information. */\n\tmemset(lpm->rule_info, 0, sizeof(lpm->rule_info));\n\n\t/* Zero tbl24. */\n\tmemset(lpm->tbl24, 0, sizeof(lpm->tbl24));\n\n\t/* Zero tbl8. */\n\tmemset(lpm->tbl8, 0, sizeof(lpm->tbl8));\n\n\t/* Delete all rules form the rules table. */\n\tmemset(lpm->rules_tbl, 0, sizeof(lpm->rules_tbl[0]) * lpm->max_rules);\n}\n" }, { "path": "lib/librte_lpm/rte_lpm.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_LPM_H_\n#define _RTE_LPM_H_\n\n/**\n * @file\n * RTE Longest Prefix Match (LPM)\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/** Max number of characters in LPM name. */\n#define RTE_LPM_NAMESIZE 32\n\n/** @deprecated Possible location to allocate memory. This was for last\n * parameter of rte_lpm_create(), but is now redundant. The LPM table is always\n * allocated in memory using librte_malloc which uses a memzone. */\n#define RTE_LPM_HEAP 0\n\n/** @deprecated Possible location to allocate memory. This was for last\n * parameter of rte_lpm_create(), but is now redundant. The LPM table is always\n * allocated in memory using librte_malloc which uses a memzone. */\n#define RTE_LPM_MEMZONE 1\n\n/** Maximum depth value possible for IPv4 LPM. */\n#define RTE_LPM_MAX_DEPTH 32\n\n/** @internal Total number of tbl24 entries. */\n#define RTE_LPM_TBL24_NUM_ENTRIES (1 << 24)\n\n/** @internal Number of entries in a tbl8 group. */\n#define RTE_LPM_TBL8_GROUP_NUM_ENTRIES 256\n\n/** @internal Total number of tbl8 groups in the tbl8. */\n#define RTE_LPM_TBL8_NUM_GROUPS 256\n\n/** @internal Total number of tbl8 entries. */\n#define RTE_LPM_TBL8_NUM_ENTRIES (RTE_LPM_TBL8_NUM_GROUPS * \\\n\t\t\t\t\tRTE_LPM_TBL8_GROUP_NUM_ENTRIES)\n\n/** @internal Macro to enable/disable run-time checks. */\n#if defined(RTE_LIBRTE_LPM_DEBUG)\n#define RTE_LPM_RETURN_IF_TRUE(cond, retval) do { \\\n\tif (cond) return (retval); \\\n} while (0)\n#else\n#define RTE_LPM_RETURN_IF_TRUE(cond, retval)\n#endif\n\n/** @internal bitmask with valid and ext_entry/valid_group fields set */\n#define RTE_LPM_VALID_EXT_ENTRY_BITMASK 0x0300\n\n/** Bitmask used to indicate successful lookup */\n#define RTE_LPM_LOOKUP_SUCCESS 0x0100\n\n#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n/** @internal Tbl24 entry structure. */\nstruct rte_lpm_tbl24_entry {\n\t/* Stores Next hop or group index (i.e. gindex)into tbl8. */\n\tunion {\n\t\tuint8_t next_hop;\n\t\tuint8_t tbl8_gindex;\n\t};\n\t/* Using single uint8_t to store 3 values. */\n\tuint8_t valid :1; /**< Validation flag. */\n\tuint8_t ext_entry :1; /**< External entry. */\n\tuint8_t depth :6; /**< Rule depth. */\n};\n\n/** @internal Tbl8 entry structure. */\nstruct rte_lpm_tbl8_entry {\n\tuint8_t next_hop; /**< next hop. */\n\t/* Using single uint8_t to store 3 values. */\n\tuint8_t valid :1; /**< Validation flag. */\n\tuint8_t valid_group :1; /**< Group validation flag. */\n\tuint8_t depth :6; /**< Rule depth. */\n};\n#else\nstruct rte_lpm_tbl24_entry {\n\tuint8_t depth :6;\n\tuint8_t ext_entry :1;\n\tuint8_t valid :1;\n\tunion {\n\t\tuint8_t tbl8_gindex;\n\t\tuint8_t next_hop;\n\t};\n};\n\nstruct rte_lpm_tbl8_entry {\n\tuint8_t depth :6;\n\tuint8_t valid_group :1;\n\tuint8_t valid :1;\n\tuint8_t next_hop;\n};\n#endif\n\n/** @internal Rule structure. */\nstruct rte_lpm_rule {\n\tuint32_t ip; /**< Rule IP address. */\n\tuint8_t next_hop; /**< Rule next hop. */\n};\n\n/** @internal Contains metadata about the rules table. */\nstruct rte_lpm_rule_info {\n\tuint32_t used_rules; /**< Used rules so far. */\n\tuint32_t first_rule; /**< Indexes the first rule of a given depth. */\n};\n\n/** @internal LPM structure. */\nstruct rte_lpm {\n\t/* LPM metadata. */\n\tchar name[RTE_LPM_NAMESIZE]; /**< Name of the lpm. */\n\tint mem_location; /**< @deprecated @see RTE_LPM_HEAP and RTE_LPM_MEMZONE. */\n\tuint32_t max_rules; /**< Max. balanced rules per lpm. */\n\tstruct rte_lpm_rule_info rule_info[RTE_LPM_MAX_DEPTH]; /**< Rule info table. */\n\n\t/* LPM Tables. */\n\tstruct rte_lpm_tbl24_entry tbl24[RTE_LPM_TBL24_NUM_ENTRIES] \\\n\t\t\t__rte_cache_aligned; /**< LPM tbl24 table. */\n\tstruct rte_lpm_tbl8_entry tbl8[RTE_LPM_TBL8_NUM_ENTRIES] \\\n\t\t\t__rte_cache_aligned; /**< LPM tbl8 table. */\n\tstruct rte_lpm_rule rules_tbl[0] \\\n\t\t\t__rte_cache_aligned; /**< LPM rules. */\n};\n\n/**\n * Create an LPM object.\n *\n * @param name\n * LPM object name\n * @param socket_id\n * NUMA socket ID for LPM table memory allocation\n * @param max_rules\n * Maximum number of LPM rules that can be added\n * @param flags\n * This parameter is currently unused\n * @return\n * Handle to LPM object on success, NULL otherwise with rte_errno set\n * to an appropriate values. Possible rte_errno values include:\n * - E_RTE_NO_CONFIG - function could not get pointer to rte_config structure\n * - E_RTE_SECONDARY - function was called from a secondary process instance\n * - EINVAL - invalid parameter passed to function\n * - ENOSPC - the maximum number of memzones has already been allocated\n * - EEXIST - a memzone with the same name already exists\n * - ENOMEM - no appropriate memory area found in which to create memzone\n */\nstruct rte_lpm *\nrte_lpm_create(const char *name, int socket_id, int max_rules, int flags);\n\n/**\n * Find an existing LPM object and return a pointer to it.\n *\n * @param name\n * Name of the lpm object as passed to rte_lpm_create()\n * @return\n * Pointer to lpm object or NULL if object not found with rte_errno\n * set appropriately. Possible rte_errno values include:\n * - ENOENT - required entry not available to return.\n */\nstruct rte_lpm *\nrte_lpm_find_existing(const char *name);\n\n/**\n * Free an LPM object.\n *\n * @param lpm\n * LPM object handle\n * @return\n * None\n */\nvoid\nrte_lpm_free(struct rte_lpm *lpm);\n\n/**\n * Add a rule to the LPM table.\n *\n * @param lpm\n * LPM object handle\n * @param ip\n * IP of the rule to be added to the LPM table\n * @param depth\n * Depth of the rule to be added to the LPM table\n * @param next_hop\n * Next hop of the rule to be added to the LPM table\n * @return\n * 0 on success, negative value otherwise\n */\nint\nrte_lpm_add(struct rte_lpm *lpm, uint32_t ip, uint8_t depth, uint8_t next_hop);\n\n/**\n * Check if a rule is present in the LPM table,\n * and provide its next hop if it is.\n *\n * @param lpm\n * LPM object handle\n * @param ip\n * IP of the rule to be searched\n * @param depth\n * Depth of the rule to searched\n * @param next_hop\n * Next hop of the rule (valid only if it is found)\n * @return\n * 1 if the rule exists, 0 if it does not, a negative value on failure\n */\nint\nrte_lpm_is_rule_present(struct rte_lpm *lpm, uint32_t ip, uint8_t depth,\nuint8_t *next_hop);\n\n/**\n * Delete a rule from the LPM table.\n *\n * @param lpm\n * LPM object handle\n * @param ip\n * IP of the rule to be deleted from the LPM table\n * @param depth\n * Depth of the rule to be deleted from the LPM table\n * @return\n * 0 on success, negative value otherwise\n */\nint\nrte_lpm_delete(struct rte_lpm *lpm, uint32_t ip, uint8_t depth);\n\n/**\n * Delete all rules from the LPM table.\n *\n * @param lpm\n * LPM object handle\n */\nvoid\nrte_lpm_delete_all(struct rte_lpm *lpm);\n\n/**\n * Lookup an IP into the LPM table.\n *\n * @param lpm\n * LPM object handle\n * @param ip\n * IP to be looked up in the LPM table\n * @param next_hop\n * Next hop of the most specific rule found for IP (valid on lookup hit only)\n * @return\n * -EINVAL for incorrect arguments, -ENOENT on lookup miss, 0 on lookup hit\n */\nstatic inline int\nrte_lpm_lookup(struct rte_lpm *lpm, uint32_t ip, uint8_t *next_hop)\n{\n\tunsigned tbl24_index = (ip >> 8);\n\tuint16_t tbl_entry;\n\n\t/* DEBUG: Check user input arguments. */\n\tRTE_LPM_RETURN_IF_TRUE(((lpm == NULL) || (next_hop == NULL)), -EINVAL);\n\n\t/* Copy tbl24 entry */\n\ttbl_entry = *(const uint16_t *)&lpm->tbl24[tbl24_index];\n\n\t/* Copy tbl8 entry (only if needed) */\n\tif (unlikely((tbl_entry & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==\n\t\t\tRTE_LPM_VALID_EXT_ENTRY_BITMASK)) {\n\n\t\tunsigned tbl8_index = (uint8_t)ip +\n\t\t\t\t((uint8_t)tbl_entry * RTE_LPM_TBL8_GROUP_NUM_ENTRIES);\n\n\t\ttbl_entry = *(const uint16_t *)&lpm->tbl8[tbl8_index];\n\t}\n\n\t*next_hop = (uint8_t)tbl_entry;\n\treturn (tbl_entry & RTE_LPM_LOOKUP_SUCCESS) ? 0 : -ENOENT;\n}\n\n/**\n * Lookup multiple IP addresses in an LPM table. This may be implemented as a\n * macro, so the address of the function should not be used.\n *\n * @param lpm\n * LPM object handle\n * @param ips\n * Array of IPs to be looked up in the LPM table\n * @param next_hops\n * Next hop of the most specific rule found for IP (valid on lookup hit only).\n * This is an array of two byte values. The most significant byte in each\n * value says whether the lookup was successful (bitmask\n * RTE_LPM_LOOKUP_SUCCESS is set). The least significant byte is the\n * actual next hop.\n * @param n\n * Number of elements in ips (and next_hops) array to lookup. This should be a\n * compile time constant, and divisible by 8 for best performance.\n * @return\n * -EINVAL for incorrect arguments, otherwise 0\n */\n#define rte_lpm_lookup_bulk(lpm, ips, next_hops, n) \\\n\t\trte_lpm_lookup_bulk_func(lpm, ips, next_hops, n)\n\nstatic inline int\nrte_lpm_lookup_bulk_func(const struct rte_lpm *lpm, const uint32_t * ips,\n\t\tuint16_t * next_hops, const unsigned n)\n{\n\tunsigned i;\n\tunsigned tbl24_indexes[n];\n\n\t/* DEBUG: Check user input arguments. */\n\tRTE_LPM_RETURN_IF_TRUE(((lpm == NULL) || (ips == NULL) ||\n\t\t\t(next_hops == NULL)), -EINVAL);\n\n\tfor (i = 0; i < n; i++) {\n\t\ttbl24_indexes[i] = ips[i] >> 8;\n\t}\n\n\tfor (i = 0; i < n; i++) {\n\t\t/* Simply copy tbl24 entry to output */\n\t\tnext_hops[i] = *(const uint16_t *)&lpm->tbl24[tbl24_indexes[i]];\n\n\t\t/* Overwrite output with tbl8 entry if needed */\n\t\tif (unlikely((next_hops[i] & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==\n\t\t\t\tRTE_LPM_VALID_EXT_ENTRY_BITMASK)) {\n\n\t\t\tunsigned tbl8_index = (uint8_t)ips[i] +\n\t\t\t\t\t((uint8_t)next_hops[i] *\n\t\t\t\t\t RTE_LPM_TBL8_GROUP_NUM_ENTRIES);\n\n\t\t\tnext_hops[i] = *(const uint16_t *)&lpm->tbl8[tbl8_index];\n\t\t}\n\t}\n\treturn 0;\n}\n\n/* Mask four results. */\n#define\t RTE_LPM_MASKX4_RES\tUINT64_C(0x00ff00ff00ff00ff)\n\n/**\n * Lookup four IP addresses in an LPM table.\n *\n * @param lpm\n * LPM object handle\n * @param ip\n * Four IPs to be looked up in the LPM table\n * @param hop\n * Next hop of the most specific rule found for IP (valid on lookup hit only).\n * This is an 4 elements array of two byte values.\n * If the lookup was succesfull for the given IP, then least significant byte\n * of the corresponding element is the actual next hop and the most\n * significant byte is zero.\n * If the lookup for the given IP failed, then corresponding element would\n * contain default value, see description of then next parameter.\n * @param defv\n * Default value to populate into corresponding element of hop[] array,\n * if lookup would fail.\n */\nstatic inline void\nrte_lpm_lookupx4(const struct rte_lpm *lpm, __m128i ip, uint16_t hop[4],\n\tuint16_t defv)\n{\n\t__m128i i24;\n\trte_xmm_t i8;\n\tuint16_t tbl[4];\n\tuint64_t idx, pt;\n\n\tconst __m128i mask8 =\n\t\t_mm_set_epi32(UINT8_MAX, UINT8_MAX, UINT8_MAX, UINT8_MAX);\n\n\t/*\n\t * RTE_LPM_VALID_EXT_ENTRY_BITMASK for 4 LPM entries\n\t * as one 64-bit value (0x0300030003000300).\n\t */\n\tconst uint64_t mask_xv =\n\t\t((uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK |\n\t\t(uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK << 16 |\n\t\t(uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK << 32 |\n\t\t(uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK << 48);\n\n\t/*\n\t * RTE_LPM_LOOKUP_SUCCESS for 4 LPM entries\n\t * as one 64-bit value (0x0100010001000100).\n\t */\n\tconst uint64_t mask_v =\n\t\t((uint64_t)RTE_LPM_LOOKUP_SUCCESS |\n\t\t(uint64_t)RTE_LPM_LOOKUP_SUCCESS << 16 |\n\t\t(uint64_t)RTE_LPM_LOOKUP_SUCCESS << 32 |\n\t\t(uint64_t)RTE_LPM_LOOKUP_SUCCESS << 48);\n\n\t/* get 4 indexes for tbl24[]. */\n\ti24 = _mm_srli_epi32(ip, CHAR_BIT);\n\n\t/* extract values from tbl24[] */\n\tidx = _mm_cvtsi128_si64(i24);\n\ti24 = _mm_srli_si128(i24, sizeof(uint64_t));\n\n\ttbl[0] = *(const uint16_t *)&lpm->tbl24[(uint32_t)idx];\n\ttbl[1] = *(const uint16_t *)&lpm->tbl24[idx >> 32];\n\n\tidx = _mm_cvtsi128_si64(i24);\n\n\ttbl[2] = *(const uint16_t *)&lpm->tbl24[(uint32_t)idx];\n\ttbl[3] = *(const uint16_t *)&lpm->tbl24[idx >> 32];\n\n\t/* get 4 indexes for tbl8[]. */\n\ti8.x = _mm_and_si128(ip, mask8);\n\n\tpt = (uint64_t)tbl[0] |\n\t\t(uint64_t)tbl[1] << 16 |\n\t\t(uint64_t)tbl[2] << 32 |\n\t\t(uint64_t)tbl[3] << 48;\n\n\t/* search successfully finished for all 4 IP addresses. */\n\tif (likely((pt & mask_xv) == mask_v)) {\n\t\tuintptr_t ph = (uintptr_t)hop;\n\t\t*(uint64_t *)ph = pt & RTE_LPM_MASKX4_RES;\n\t\treturn;\n\t}\n\n\tif (unlikely((pt & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==\n\t\t\tRTE_LPM_VALID_EXT_ENTRY_BITMASK)) {\n\t\ti8.u32[0] = i8.u32[0] +\n\t\t\t(uint8_t)tbl[0] * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\t\ttbl[0] = *(const uint16_t *)&lpm->tbl8[i8.u32[0]];\n\t}\n\tif (unlikely((pt >> 16 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==\n\t\t\tRTE_LPM_VALID_EXT_ENTRY_BITMASK)) {\n\t\ti8.u32[1] = i8.u32[1] +\n\t\t\t(uint8_t)tbl[1] * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\t\ttbl[1] = *(const uint16_t *)&lpm->tbl8[i8.u32[1]];\n\t}\n\tif (unlikely((pt >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==\n\t\t\tRTE_LPM_VALID_EXT_ENTRY_BITMASK)) {\n\t\ti8.u32[2] = i8.u32[2] +\n\t\t\t(uint8_t)tbl[2] * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\t\ttbl[2] = *(const uint16_t *)&lpm->tbl8[i8.u32[2]];\n\t}\n\tif (unlikely((pt >> 48 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==\n\t\t\tRTE_LPM_VALID_EXT_ENTRY_BITMASK)) {\n\t\ti8.u32[3] = i8.u32[3] +\n\t\t\t(uint8_t)tbl[3] * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;\n\t\ttbl[3] = *(const uint16_t *)&lpm->tbl8[i8.u32[3]];\n\t}\n\n\thop[0] = (tbl[0] & RTE_LPM_LOOKUP_SUCCESS) ? (uint8_t)tbl[0] : defv;\n\thop[1] = (tbl[1] & RTE_LPM_LOOKUP_SUCCESS) ? (uint8_t)tbl[1] : defv;\n\thop[2] = (tbl[2] & RTE_LPM_LOOKUP_SUCCESS) ? (uint8_t)tbl[2] : defv;\n\thop[3] = (tbl[3] & RTE_LPM_LOOKUP_SUCCESS) ? (uint8_t)tbl[3] : defv;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_LPM_H_ */\n" }, { "path": "lib/librte_lpm/rte_lpm6.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_lpm6.h\"\n\n#define RTE_LPM6_TBL24_NUM_ENTRIES (1 << 24)\n#define RTE_LPM6_TBL8_GROUP_NUM_ENTRIES 256\n#define RTE_LPM6_TBL8_MAX_NUM_GROUPS (1 << 21)\n\n#define RTE_LPM6_VALID_EXT_ENTRY_BITMASK 0xA0000000\n#define RTE_LPM6_LOOKUP_SUCCESS 0x20000000\n#define RTE_LPM6_TBL8_BITMASK 0x001FFFFF\n\n#define ADD_FIRST_BYTE 3\n#define LOOKUP_FIRST_BYTE 4\n#define BYTE_SIZE 8\n#define BYTES2_SIZE 16\n\n#define lpm6_tbl8_gindex next_hop\n\n/** Flags for setting an entry as valid/invalid. */\nenum valid_flag {\n\tINVALID = 0,\n\tVALID\n};\n\nTAILQ_HEAD(rte_lpm6_list, rte_tailq_entry);\n\nstatic struct rte_tailq_elem rte_lpm6_tailq = {\n\t.name = \"RTE_LPM6\",\n};\nEAL_REGISTER_TAILQ(rte_lpm6_tailq)\n\n/** Tbl entry structure. It is the same for both tbl24 and tbl8 */\nstruct rte_lpm6_tbl_entry {\n\tuint32_t next_hop:\t21; /**< Next hop / next table to be checked. */\n\tuint32_t depth\t:8; /**< Rule depth. */\n\n\t/* Flags. */\n\tuint32_t valid :1; /**< Validation flag. */\n\tuint32_t valid_group :1; /**< Group validation flag. */\n\tuint32_t ext_entry :1; /**< External entry. */\n};\n\n/** Rules tbl entry structure. */\nstruct rte_lpm6_rule {\n\tuint8_t ip[RTE_LPM6_IPV6_ADDR_SIZE]; /**< Rule IP address. */\n\tuint8_t next_hop; /**< Rule next hop. */\n\tuint8_t depth; /**< Rule depth. */\n};\n\n/** LPM6 structure. */\nstruct rte_lpm6 {\n\t/* LPM metadata. */\n\tchar name[RTE_LPM6_NAMESIZE]; /**< Name of the lpm. */\n\tuint32_t max_rules; /**< Max number of rules. */\n\tuint32_t used_rules; /**< Used rules so far. */\n\tuint32_t number_tbl8s; /**< Number of tbl8s to allocate. */\n\tuint32_t next_tbl8; /**< Next tbl8 to be used. */\n\n\t/* LPM Tables. */\n\tstruct rte_lpm6_rule *rules_tbl; /**< LPM rules. */\n\tstruct rte_lpm6_tbl_entry tbl24[RTE_LPM6_TBL24_NUM_ENTRIES]\n\t\t\t__rte_cache_aligned; /**< LPM tbl24 table. */\n\tstruct rte_lpm6_tbl_entry tbl8[0]\n\t\t\t__rte_cache_aligned; /**< LPM tbl8 table. */\n};\n\n/*\n * Takes an array of uint8_t (IPv6 address) and masks it using the depth.\n * It leaves untouched one bit per unit in the depth variable\n * and set the rest to 0.\n */\nstatic inline void\nmask_ip(uint8_t *ip, uint8_t depth)\n{\n int16_t part_depth, mask;\n int i;\n\n\t\tpart_depth = depth;\n\n\t\tfor (i = 0; i < RTE_LPM6_IPV6_ADDR_SIZE; i++) {\n\t\t\tif (part_depth < BYTE_SIZE && part_depth >= 0) {\n\t\t\t\tmask = (uint16_t)(~(UINT8_MAX >> part_depth));\n\t\t\t\tip[i] = (uint8_t)(ip[i] & mask);\n\t\t\t} else if (part_depth < 0) {\n\t\t\t\tip[i] = 0;\n\t\t\t}\n\t\t\tpart_depth -= BYTE_SIZE;\n\t\t}\n}\n\n/*\n * Allocates memory for LPM object\n */\nstruct rte_lpm6 *\nrte_lpm6_create(const char *name, int socket_id,\n\t\tconst struct rte_lpm6_config *config)\n{\n\tchar mem_name[RTE_LPM6_NAMESIZE];\n\tstruct rte_lpm6 *lpm = NULL;\n\tstruct rte_tailq_entry *te;\n\tuint64_t mem_size, rules_size;\n\tstruct rte_lpm6_list *lpm_list;\n\n\tlpm_list = RTE_TAILQ_CAST(rte_lpm6_tailq.head, rte_lpm6_list);\n\n\tRTE_BUILD_BUG_ON(sizeof(struct rte_lpm6_tbl_entry) != sizeof(uint32_t));\n\n\t/* Check user arguments. */\n\tif ((name == NULL) || (socket_id < -1) || (config == NULL) ||\n\t\t\t(config->max_rules == 0) ||\n\t\t\tconfig->number_tbl8s > RTE_LPM6_TBL8_MAX_NUM_GROUPS) {\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\tsnprintf(mem_name, sizeof(mem_name), \"LPM_%s\", name);\n\n\t/* Determine the amount of memory to allocate. */\n\tmem_size = sizeof(*lpm) + (sizeof(lpm->tbl8[0]) *\n\t\t\tRTE_LPM6_TBL8_GROUP_NUM_ENTRIES * config->number_tbl8s);\n\trules_size = sizeof(struct rte_lpm6_rule) * config->max_rules;\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* Guarantee there's no existing */\n\tTAILQ_FOREACH(te, lpm_list, next) {\n\t\tlpm = (struct rte_lpm6 *) te->data;\n\t\tif (strncmp(name, lpm->name, RTE_LPM6_NAMESIZE) == 0)\n\t\t\tbreak;\n\t}\n\tif (te != NULL)\n\t\tgoto exit;\n\n\t/* allocate tailq entry */\n\tte = rte_zmalloc(\"LPM6_TAILQ_ENTRY\", sizeof(*te), 0);\n\tif (te == NULL) {\n\t\tRTE_LOG(ERR, LPM, \"Failed to allocate tailq entry!\\n\");\n\t\tgoto exit;\n\t}\n\n\t/* Allocate memory to store the LPM data structures. */\n\tlpm = (struct rte_lpm6 *)rte_zmalloc_socket(mem_name, (size_t)mem_size,\n\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\n\tif (lpm == NULL) {\n\t\tRTE_LOG(ERR, LPM, \"LPM memory allocation failed\\n\");\n\t\trte_free(te);\n\t\tgoto exit;\n\t}\n\n\tlpm->rules_tbl = (struct rte_lpm6_rule *)rte_zmalloc_socket(NULL,\n\t\t\t(size_t)rules_size, RTE_CACHE_LINE_SIZE, socket_id);\n\n\tif (lpm->rules_tbl == NULL) {\n\t\tRTE_LOG(ERR, LPM, \"LPM memory allocation failed\\n\");\n\t\trte_free(lpm);\n\t\trte_free(te);\n\t\tgoto exit;\n\t}\n\n\t/* Save user arguments. */\n\tlpm->max_rules = config->max_rules;\n\tlpm->number_tbl8s = config->number_tbl8s;\n\tsnprintf(lpm->name, sizeof(lpm->name), \"%s\", name);\n\n\tte->data = (void *) lpm;\n\n\tTAILQ_INSERT_TAIL(lpm_list, te, next);\n\nexit:\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\treturn lpm;\n}\n\n/*\n * Find an existing lpm table and return a pointer to it.\n */\nstruct rte_lpm6 *\nrte_lpm6_find_existing(const char *name)\n{\n\tstruct rte_lpm6 *l = NULL;\n\tstruct rte_tailq_entry *te;\n\tstruct rte_lpm6_list *lpm_list;\n\n\tlpm_list = RTE_TAILQ_CAST(rte_lpm6_tailq.head, rte_lpm6_list);\n\n\trte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);\n\tTAILQ_FOREACH(te, lpm_list, next) {\n\t\tl = (struct rte_lpm6 *) te->data;\n\t\tif (strncmp(name, l->name, RTE_LPM6_NAMESIZE) == 0)\n\t\t\tbreak;\n\t}\n\trte_rwlock_read_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\tif (te == NULL) {\n\t\trte_errno = ENOENT;\n\t\treturn NULL;\n\t}\n\n\treturn l;\n}\n\n/*\n * Deallocates memory for given LPM table.\n */\nvoid\nrte_lpm6_free(struct rte_lpm6 *lpm)\n{\n\tstruct rte_lpm6_list *lpm_list;\n\tstruct rte_tailq_entry *te;\n\n\t/* Check user arguments. */\n\tif (lpm == NULL)\n\t\treturn;\n\n\tlpm_list = RTE_TAILQ_CAST(rte_lpm6_tailq.head, rte_lpm6_list);\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* find our tailq entry */\n\tTAILQ_FOREACH(te, lpm_list, next) {\n\t\tif (te->data == (void *) lpm)\n\t\t\tbreak;\n\t}\n\tif (te == NULL) {\n\t\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\t\treturn;\n\t}\n\n\tTAILQ_REMOVE(lpm_list, te, next);\n\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\trte_free(lpm);\n\trte_free(te);\n}\n\n/*\n * Checks if a rule already exists in the rules table and updates\n * the nexthop if so. Otherwise it adds a new rule if enough space is available.\n */\nstatic inline int32_t\nrule_add(struct rte_lpm6 *lpm, uint8_t *ip, uint8_t next_hop, uint8_t depth)\n{\n\tuint32_t rule_index;\n\n\t/* Scan through rule list to see if rule already exists. */\n\tfor (rule_index = 0; rule_index < lpm->used_rules; rule_index++) {\n\n\t\t/* If rule already exists update its next_hop and return. */\n\t\tif ((memcmp (lpm->rules_tbl[rule_index].ip, ip,\n\t\t\t\tRTE_LPM6_IPV6_ADDR_SIZE) == 0) &&\n\t\t\t\tlpm->rules_tbl[rule_index].depth == depth) {\n\t\t\tlpm->rules_tbl[rule_index].next_hop = next_hop;\n\n\t\t\treturn rule_index;\n\t\t}\n\t}\n\n\t/*\n\t * If rule does not exist check if there is space to add a new rule to\n\t * this rule group. If there is no space return error.\n\t */\n\tif (lpm->used_rules == lpm->max_rules) {\n\t\treturn -ENOSPC;\n\t}\n\n\t/* If there is space for the new rule add it. */\n\trte_memcpy(lpm->rules_tbl[rule_index].ip, ip, RTE_LPM6_IPV6_ADDR_SIZE);\n\tlpm->rules_tbl[rule_index].next_hop = next_hop;\n\tlpm->rules_tbl[rule_index].depth = depth;\n\n\t/* Increment the used rules counter for this rule group. */\n\tlpm->used_rules++;\n\n\treturn rule_index;\n}\n\n/*\n * Function that expands a rule across the data structure when a less-generic\n * one has been added before. It assures that every possible combination of bits\n * in the IP address returns a match.\n */\nstatic void\nexpand_rule(struct rte_lpm6 *lpm, uint32_t tbl8_gindex, uint8_t depth,\n\t\tuint8_t next_hop)\n{\n\tuint32_t tbl8_group_end, tbl8_gindex_next, j;\n\n\ttbl8_group_end = tbl8_gindex + RTE_LPM6_TBL8_GROUP_NUM_ENTRIES;\n\n\tstruct rte_lpm6_tbl_entry new_tbl8_entry = {\n\t\t.valid = VALID,\n\t\t.valid_group = VALID,\n\t\t.depth = depth,\n\t\t.next_hop = next_hop,\n\t\t.ext_entry = 0,\n\t};\n\n\tfor (j = tbl8_gindex; j < tbl8_group_end; j++) {\n\t\tif (!lpm->tbl8[j].valid || (lpm->tbl8[j].ext_entry == 0\n\t\t\t\t&& lpm->tbl8[j].depth <= depth)) {\n\n\t\t\tlpm->tbl8[j] = new_tbl8_entry;\n\n\t\t} else if (lpm->tbl8[j].ext_entry == 1) {\n\n\t\t\ttbl8_gindex_next = lpm->tbl8[j].lpm6_tbl8_gindex\n\t\t\t\t\t* RTE_LPM6_TBL8_GROUP_NUM_ENTRIES;\n\t\t\texpand_rule(lpm, tbl8_gindex_next, depth, next_hop);\n\t\t}\n\t}\n}\n\n/*\n * Partially adds a new route to the data structure (tbl24+tbl8s).\n * It returns 0 on success, a negative number on failure, or 1 if\n * the process needs to be continued by calling the function again.\n */\nstatic inline int\nadd_step(struct rte_lpm6 *lpm, struct rte_lpm6_tbl_entry *tbl,\n\t\tstruct rte_lpm6_tbl_entry **tbl_next, uint8_t *ip, uint8_t bytes,\n\t\tuint8_t first_byte, uint8_t depth, uint8_t next_hop)\n{\n\tuint32_t tbl_index, tbl_range, tbl8_group_start, tbl8_group_end, i;\n\tint32_t tbl8_gindex;\n\tint8_t bitshift;\n\tuint8_t bits_covered;\n\n\t/*\n\t * Calculate index to the table based on the number and position\n\t * of the bytes being inspected in this step.\n\t */\n\ttbl_index = 0;\n\tfor (i = first_byte; i < (uint32_t)(first_byte + bytes); i++) {\n\t\tbitshift = (int8_t)((bytes - i)*BYTE_SIZE);\n\n\t\tif (bitshift < 0) bitshift = 0;\n\t\ttbl_index = tbl_index | ip[i-1] << bitshift;\n\t}\n\n\t/* Number of bits covered in this step */\n\tbits_covered = (uint8_t)((bytes+first_byte-1)*BYTE_SIZE);\n\n\t/*\n\t * If depth if smaller than this number (ie this is the last step)\n\t * expand the rule across the relevant positions in the table.\n\t */\n\tif (depth <= bits_covered) {\n\t\ttbl_range = 1 << (bits_covered - depth);\n\n\t\tfor (i = tbl_index; i < (tbl_index + tbl_range); i++) {\n\t\t\tif (!tbl[i].valid || (tbl[i].ext_entry == 0 &&\n\t\t\t\t\ttbl[i].depth <= depth)) {\n\n\t\t\t\tstruct rte_lpm6_tbl_entry new_tbl_entry = {\n\t\t\t\t\t.next_hop = next_hop,\n\t\t\t\t\t.depth = depth,\n\t\t\t\t\t.valid = VALID,\n\t\t\t\t\t.valid_group = VALID,\n\t\t\t\t\t.ext_entry = 0,\n\t\t\t\t};\n\n\t\t\t\ttbl[i] = new_tbl_entry;\n\n\t\t\t} else if (tbl[i].ext_entry == 1) {\n\n\t\t\t\t/*\n\t\t\t\t * If tbl entry is valid and extended calculate the index\n\t\t\t\t * into next tbl8 and expand the rule across the data structure.\n\t\t\t\t */\n\t\t\t\ttbl8_gindex = tbl[i].lpm6_tbl8_gindex *\n\t\t\t\t\t\tRTE_LPM6_TBL8_GROUP_NUM_ENTRIES;\n\t\t\t\texpand_rule(lpm, tbl8_gindex, depth, next_hop);\n\t\t\t}\n\t\t}\n\n\t\treturn 0;\n\t}\n\t/*\n\t * If this is not the last step just fill one position\n\t * and calculate the index to the next table.\n\t */\n\telse {\n\t\t/* If it's invalid a new tbl8 is needed */\n\t\tif (!tbl[tbl_index].valid) {\n\t\t\tif (lpm->next_tbl8 < lpm->number_tbl8s)\n\t\t\t\ttbl8_gindex = (lpm->next_tbl8)++;\n\t\t\telse\n\t\t\t\treturn -ENOSPC;\n\n\t\t\tstruct rte_lpm6_tbl_entry new_tbl_entry = {\n\t\t\t\t.lpm6_tbl8_gindex = tbl8_gindex,\n\t\t\t\t.depth = 0,\n\t\t\t\t.valid = VALID,\n\t\t\t\t.valid_group = VALID,\n\t\t\t\t.ext_entry = 1,\n\t\t\t};\n\n\t\t\ttbl[tbl_index] = new_tbl_entry;\n\t\t}\n\t\t/*\n\t\t * If it's valid but not extended the rule that was stored *\n\t\t * here needs to be moved to the next table.\n\t\t */\n\t\telse if (tbl[tbl_index].ext_entry == 0) {\n\t\t\t/* Search for free tbl8 group. */\n\t\t\tif (lpm->next_tbl8 < lpm->number_tbl8s)\n\t\t\t\ttbl8_gindex = (lpm->next_tbl8)++;\n\t\t\telse\n\t\t\t\treturn -ENOSPC;\n\n\t\t\ttbl8_group_start = tbl8_gindex *\n\t\t\t\t\tRTE_LPM6_TBL8_GROUP_NUM_ENTRIES;\n\t\t\ttbl8_group_end = tbl8_group_start +\n\t\t\t\t\tRTE_LPM6_TBL8_GROUP_NUM_ENTRIES;\n\n\t\t\t/* Populate new tbl8 with tbl value. */\n\t\t\tfor (i = tbl8_group_start; i < tbl8_group_end; i++) {\n\t\t\t\tlpm->tbl8[i].valid = VALID;\n\t\t\t\tlpm->tbl8[i].depth = tbl[tbl_index].depth;\n\t\t\t\tlpm->tbl8[i].next_hop = tbl[tbl_index].next_hop;\n\t\t\t\tlpm->tbl8[i].ext_entry = 0;\n\t\t\t}\n\n\t\t\t/*\n\t\t\t * Update tbl entry to point to new tbl8 entry. Note: The\n\t\t\t * ext_flag and tbl8_index need to be updated simultaneously,\n\t\t\t * so assign whole structure in one go.\n\t\t\t */\n\t\t\tstruct rte_lpm6_tbl_entry new_tbl_entry = {\n\t\t\t\t.lpm6_tbl8_gindex = tbl8_gindex,\n\t\t\t\t.depth = 0,\n\t\t\t\t.valid = VALID,\n\t\t\t\t.valid_group = VALID,\n\t\t\t\t.ext_entry = 1,\n\t\t\t};\n\n\t\t\ttbl[tbl_index] = new_tbl_entry;\n\t\t}\n\n\t\t*tbl_next = &(lpm->tbl8[tbl[tbl_index].lpm6_tbl8_gindex *\n\t\t\t\tRTE_LPM6_TBL8_GROUP_NUM_ENTRIES]);\n\t}\n\n\treturn 1;\n}\n\n/*\n * Add a route\n */\nint\nrte_lpm6_add(struct rte_lpm6 *lpm, uint8_t *ip, uint8_t depth,\n\t\tuint8_t next_hop)\n{\n\tstruct rte_lpm6_tbl_entry *tbl;\n\tstruct rte_lpm6_tbl_entry *tbl_next;\n\tint32_t rule_index;\n\tint status;\n\tuint8_t masked_ip[RTE_LPM6_IPV6_ADDR_SIZE];\n\tint i;\n\n\t/* Check user arguments. */\n\tif ((lpm == NULL) || (depth < 1) || (depth > RTE_LPM6_MAX_DEPTH))\n\t\treturn -EINVAL;\n\n\t/* Copy the IP and mask it to avoid modifying user's input data. */\n\tmemcpy(masked_ip, ip, RTE_LPM6_IPV6_ADDR_SIZE);\n\tmask_ip(masked_ip, depth);\n\n\t/* Add the rule to the rule table. */\n\trule_index = rule_add(lpm, masked_ip, next_hop, depth);\n\n\t/* If there is no space available for new rule return error. */\n\tif (rule_index < 0) {\n\t\treturn rule_index;\n\t}\n\n\t/* Inspect the first three bytes through tbl24 on the first step. */\n\ttbl = lpm->tbl24;\n\tstatus = add_step (lpm, tbl, &tbl_next, masked_ip, ADD_FIRST_BYTE, 1,\n\t\t\tdepth, next_hop);\n\tif (status < 0) {\n\t\trte_lpm6_delete(lpm, masked_ip, depth);\n\n\t\treturn status;\n\t}\n\n\t/*\n\t * Inspect one by one the rest of the bytes until\n\t * the process is completed.\n\t */\n\tfor (i = ADD_FIRST_BYTE; i < RTE_LPM6_IPV6_ADDR_SIZE && status == 1; i++) {\n\t\ttbl = tbl_next;\n\t\tstatus = add_step (lpm, tbl, &tbl_next, masked_ip, 1, (uint8_t)(i+1),\n\t\t\t\tdepth, next_hop);\n\t\tif (status < 0) {\n\t\t\trte_lpm6_delete(lpm, masked_ip, depth);\n\n\t\t\treturn status;\n\t\t}\n\t}\n\n\treturn status;\n}\n\n/*\n * Takes a pointer to a table entry and inspect one level.\n * The function returns 0 on lookup success, ENOENT if no match was found\n * or 1 if the process needs to be continued by calling the function again.\n */\nstatic inline int\nlookup_step(const struct rte_lpm6 *lpm, const struct rte_lpm6_tbl_entry *tbl,\n\t\tconst struct rte_lpm6_tbl_entry **tbl_next, uint8_t *ip,\n\t\tuint8_t first_byte, uint8_t *next_hop)\n{\n\tuint32_t tbl8_index, tbl_entry;\n\n\t/* Take the integer value from the pointer. */\n\ttbl_entry = *(const uint32_t *)tbl;\n\n\t/* If it is valid and extended we calculate the new pointer to return. */\n\tif ((tbl_entry & RTE_LPM6_VALID_EXT_ENTRY_BITMASK) ==\n\t\t\tRTE_LPM6_VALID_EXT_ENTRY_BITMASK) {\n\n\t\ttbl8_index = ip[first_byte-1] +\n\t\t\t\t((tbl_entry & RTE_LPM6_TBL8_BITMASK) *\n\t\t\t\tRTE_LPM6_TBL8_GROUP_NUM_ENTRIES);\n\n\t\t*tbl_next = &lpm->tbl8[tbl8_index];\n\n\t\treturn 1;\n\t} else {\n\t\t/* If not extended then we can have a match. */\n\t\t*next_hop = (uint8_t)tbl_entry;\n\t\treturn (tbl_entry & RTE_LPM6_LOOKUP_SUCCESS) ? 0 : -ENOENT;\n\t}\n}\n\n/*\n * Looks up an IP\n */\nint\nrte_lpm6_lookup(const struct rte_lpm6 *lpm, uint8_t *ip, uint8_t *next_hop)\n{\n\tconst struct rte_lpm6_tbl_entry *tbl;\n\tconst struct rte_lpm6_tbl_entry *tbl_next;\n\tint status;\n\tuint8_t first_byte;\n\tuint32_t tbl24_index;\n\n\t/* DEBUG: Check user input arguments. */\n\tif ((lpm == NULL) || (ip == NULL) || (next_hop == NULL)) {\n\t\treturn -EINVAL;\n\t}\n\n\tfirst_byte = LOOKUP_FIRST_BYTE;\n\ttbl24_index = (ip[0] << BYTES2_SIZE) | (ip[1] << BYTE_SIZE) | ip[2];\n\n\t/* Calculate pointer to the first entry to be inspected */\n\ttbl = &lpm->tbl24[tbl24_index];\n\n\tdo {\n\t\t/* Continue inspecting following levels until success or failure */\n\t\tstatus = lookup_step(lpm, tbl, &tbl_next, ip, first_byte++, next_hop);\n\t\ttbl = tbl_next;\n\t} while (status == 1);\n\n\treturn status;\n}\n\n/*\n * Looks up a group of IP addresses\n */\nint\nrte_lpm6_lookup_bulk_func(const struct rte_lpm6 *lpm,\n\t\tuint8_t ips[][RTE_LPM6_IPV6_ADDR_SIZE],\n\t\tint16_t * next_hops, unsigned n)\n{\n\tunsigned i;\n\tconst struct rte_lpm6_tbl_entry *tbl;\n\tconst struct rte_lpm6_tbl_entry *tbl_next;\n\tuint32_t tbl24_index;\n\tuint8_t first_byte, next_hop;\n\tint status;\n\n\t/* DEBUG: Check user input arguments. */\n\tif ((lpm == NULL) || (ips == NULL) || (next_hops == NULL)) {\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < n; i++) {\n\t\tfirst_byte = LOOKUP_FIRST_BYTE;\n\t\ttbl24_index = (ips[i][0] << BYTES2_SIZE) |\n\t\t\t\t(ips[i][1] << BYTE_SIZE) | ips[i][2];\n\n\t\t/* Calculate pointer to the first entry to be inspected */\n\t\ttbl = &lpm->tbl24[tbl24_index];\n\n\t\tdo {\n\t\t\t/* Continue inspecting following levels until success or failure */\n\t\t\tstatus = lookup_step(lpm, tbl, &tbl_next, ips[i], first_byte++,\n\t\t\t\t\t&next_hop);\n\t\t\ttbl = tbl_next;\n\t\t} while (status == 1);\n\n\t\tif (status < 0)\n\t\t\tnext_hops[i] = -1;\n\t\telse\n\t\t\tnext_hops[i] = next_hop;\n\t}\n\n\treturn 0;\n}\n\n/*\n * Finds a rule in rule table.\n * NOTE: Valid range for depth parameter is 1 .. 128 inclusive.\n */\nstatic inline int32_t\nrule_find(struct rte_lpm6 *lpm, uint8_t *ip, uint8_t depth)\n{\n\tuint32_t rule_index;\n\n\t/* Scan used rules at given depth to find rule. */\n\tfor (rule_index = 0; rule_index < lpm->used_rules; rule_index++) {\n\t\t/* If rule is found return the rule index. */\n\t\tif ((memcmp (lpm->rules_tbl[rule_index].ip, ip,\n\t\t\t\tRTE_LPM6_IPV6_ADDR_SIZE) == 0) &&\n\t\t\t\tlpm->rules_tbl[rule_index].depth == depth) {\n\n\t\t\treturn rule_index;\n\t\t}\n\t}\n\n\t/* If rule is not found return -ENOENT. */\n\treturn -ENOENT;\n}\n\n/*\n * Look for a rule in the high-level rules table\n */\nint\nrte_lpm6_is_rule_present(struct rte_lpm6 *lpm, uint8_t *ip, uint8_t depth,\nuint8_t *next_hop)\n{\n\tuint8_t ip_masked[RTE_LPM6_IPV6_ADDR_SIZE];\n\tint32_t rule_index;\n\n\t/* Check user arguments. */\n\tif ((lpm == NULL) || next_hop == NULL || ip == NULL ||\n\t\t\t(depth < 1) || (depth > RTE_LPM6_MAX_DEPTH))\n\t\treturn -EINVAL;\n\n\t/* Copy the IP and mask it to avoid modifying user's input data. */\n\tmemcpy(ip_masked, ip, RTE_LPM6_IPV6_ADDR_SIZE);\n\tmask_ip(ip_masked, depth);\n\n\t/* Look for the rule using rule_find. */\n\trule_index = rule_find(lpm, ip_masked, depth);\n\n\tif (rule_index >= 0) {\n\t\t*next_hop = lpm->rules_tbl[rule_index].next_hop;\n\t\treturn 1;\n\t}\n\n\t/* If rule is not found return 0. */\n\treturn 0;\n}\n\n/*\n * Delete a rule from the rule table.\n * NOTE: Valid range for depth parameter is 1 .. 128 inclusive.\n */\nstatic inline void\nrule_delete(struct rte_lpm6 *lpm, int32_t rule_index)\n{\n\t/*\n\t * Overwrite redundant rule with last rule in group and decrement rule\n\t * counter.\n\t */\n\tlpm->rules_tbl[rule_index] = lpm->rules_tbl[lpm->used_rules-1];\n\tlpm->used_rules--;\n}\n\n/*\n * Deletes a rule\n */\nint\nrte_lpm6_delete(struct rte_lpm6 *lpm, uint8_t *ip, uint8_t depth)\n{\n\tint32_t rule_to_delete_index;\n\tuint8_t ip_masked[RTE_LPM6_IPV6_ADDR_SIZE];\n\tunsigned i;\n\n\t/*\n\t * Check input arguments.\n\t */\n\tif ((lpm == NULL) || (depth < 1) || (depth > RTE_LPM6_MAX_DEPTH)) {\n\t\treturn -EINVAL;\n\t}\n\n\t/* Copy the IP and mask it to avoid modifying user's input data. */\n\tmemcpy(ip_masked, ip, RTE_LPM6_IPV6_ADDR_SIZE);\n\tmask_ip(ip_masked, depth);\n\n\t/*\n\t * Find the index of the input rule, that needs to be deleted, in the\n\t * rule table.\n\t */\n\trule_to_delete_index = rule_find(lpm, ip_masked, depth);\n\n\t/*\n\t * Check if rule_to_delete_index was found. If no rule was found the\n\t * function rule_find returns -ENOENT.\n\t */\n\tif (rule_to_delete_index < 0)\n\t\treturn rule_to_delete_index;\n\n\t/* Delete the rule from the rule table. */\n\trule_delete(lpm, rule_to_delete_index);\n\n\t/*\n\t * Set all the table entries to 0 (ie delete every rule\n\t * from the data structure.\n\t */\n\tlpm->next_tbl8 = 0;\n\tmemset(lpm->tbl24, 0, sizeof(lpm->tbl24));\n\tmemset(lpm->tbl8, 0, sizeof(lpm->tbl8[0])\n\t\t\t* RTE_LPM6_TBL8_GROUP_NUM_ENTRIES * lpm->number_tbl8s);\n\n\t/*\n\t * Add every rule again (except for the one that was removed from\n\t * the rules table).\n\t */\n\tfor (i = 0; i < lpm->used_rules; i++) {\n\t\trte_lpm6_add(lpm, lpm->rules_tbl[i].ip, lpm->rules_tbl[i].depth,\n\t\t\t\tlpm->rules_tbl[i].next_hop);\n\t}\n\n\treturn 0;\n}\n\n/*\n * Deletes a group of rules\n */\nint\nrte_lpm6_delete_bulk_func(struct rte_lpm6 *lpm,\n\t\tuint8_t ips[][RTE_LPM6_IPV6_ADDR_SIZE], uint8_t *depths, unsigned n)\n{\n\tint32_t rule_to_delete_index;\n\tuint8_t ip_masked[RTE_LPM6_IPV6_ADDR_SIZE];\n\tunsigned i;\n\n\t/*\n\t * Check input arguments.\n\t */\n\tif ((lpm == NULL) || (ips == NULL) || (depths == NULL)) {\n\t\treturn -EINVAL;\n\t}\n\n\tfor (i = 0; i < n; i++) {\n\t\t/* Copy the IP and mask it to avoid modifying user's input data. */\n\t\tmemcpy(ip_masked, ips[i], RTE_LPM6_IPV6_ADDR_SIZE);\n\t\tmask_ip(ip_masked, depths[i]);\n\n\t\t/*\n\t\t * Find the index of the input rule, that needs to be deleted, in the\n\t\t * rule table.\n\t\t */\n\t\trule_to_delete_index = rule_find(lpm, ip_masked, depths[i]);\n\n\t\t/*\n\t\t * Check if rule_to_delete_index was found. If no rule was found the\n\t\t * function rule_find returns -ENOENT.\n\t\t */\n\t\tif (rule_to_delete_index < 0)\n\t\t\tcontinue;\n\n\t\t/* Delete the rule from the rule table. */\n\t\trule_delete(lpm, rule_to_delete_index);\n\t}\n\n\t/*\n\t * Set all the table entries to 0 (ie delete every rule\n\t * from the data structure.\n\t */\n\tlpm->next_tbl8 = 0;\n\tmemset(lpm->tbl24, 0, sizeof(lpm->tbl24));\n\tmemset(lpm->tbl8, 0, sizeof(lpm->tbl8[0])\n\t\t\t* RTE_LPM6_TBL8_GROUP_NUM_ENTRIES * lpm->number_tbl8s);\n\n\t/*\n\t * Add every rule again (except for the ones that were removed from\n\t * the rules table).\n\t */\n\tfor (i = 0; i < lpm->used_rules; i++) {\n\t\trte_lpm6_add(lpm, lpm->rules_tbl[i].ip, lpm->rules_tbl[i].depth,\n\t\t\t\tlpm->rules_tbl[i].next_hop);\n\t}\n\n\treturn 0;\n}\n\n/*\n * Delete all rules from the LPM table.\n */\nvoid\nrte_lpm6_delete_all(struct rte_lpm6 *lpm)\n{\n\t/* Zero used rules counter. */\n\tlpm->used_rules = 0;\n\n\t/* Zero next tbl8 index. */\n\tlpm->next_tbl8 = 0;\n\n\t/* Zero tbl24. */\n\tmemset(lpm->tbl24, 0, sizeof(lpm->tbl24));\n\n\t/* Zero tbl8. */\n\tmemset(lpm->tbl8, 0, sizeof(lpm->tbl8[0]) *\n\t\t\tRTE_LPM6_TBL8_GROUP_NUM_ENTRIES * lpm->number_tbl8s);\n\n\t/* Delete all rules form the rules table. */\n\tmemset(lpm->rules_tbl, 0, sizeof(struct rte_lpm6_rule) * lpm->max_rules);\n}\n" }, { "path": "lib/librte_lpm/rte_lpm6.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef _RTE_LPM6_H_\n#define _RTE_LPM6_H_\n\n/**\n * @file\n * RTE Longest Prefix Match for IPv6 (LPM6)\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n#define RTE_LPM6_MAX_DEPTH 128\n#define RTE_LPM6_IPV6_ADDR_SIZE 16\n/** Max number of characters in LPM name. */\n#define RTE_LPM6_NAMESIZE 32\n\n/** LPM structure. */\nstruct rte_lpm6;\n\n/** LPM configuration structure. */\nstruct rte_lpm6_config {\n\tuint32_t max_rules; /**< Max number of rules. */\n\tuint32_t number_tbl8s; /**< Number of tbl8s to allocate. */\n\tint flags; /**< This field is currently unused. */\n};\n\n/**\n * Create an LPM object.\n *\n * @param name\n * LPM object name\n * @param socket_id\n * NUMA socket ID for LPM table memory allocation\n * @param config\n * Structure containing the configuration\n * @return\n * Handle to LPM object on success, NULL otherwise with rte_errno set\n * to an appropriate values. Possible rte_errno values include:\n * - E_RTE_NO_CONFIG - function could not get pointer to rte_config structure\n * - E_RTE_SECONDARY - function was called from a secondary process instance\n * - EINVAL - invalid parameter passed to function\n * - ENOSPC - the maximum number of memzones has already been allocated\n * - EEXIST - a memzone with the same name already exists\n * - ENOMEM - no appropriate memory area found in which to create memzone\n */\nstruct rte_lpm6 *\nrte_lpm6_create(const char *name, int socket_id,\n\t\tconst struct rte_lpm6_config *config);\n\n/**\n * Find an existing LPM object and return a pointer to it.\n *\n * @param name\n * Name of the lpm object as passed to rte_lpm6_create()\n * @return\n * Pointer to lpm object or NULL if object not found with rte_errno\n * set appropriately. Possible rte_errno values include:\n * - ENOENT - required entry not available to return.\n */\nstruct rte_lpm6 *\nrte_lpm6_find_existing(const char *name);\n\n/**\n * Free an LPM object.\n *\n * @param lpm\n * LPM object handle\n * @return\n * None\n */\nvoid\nrte_lpm6_free(struct rte_lpm6 *lpm);\n\n/**\n * Add a rule to the LPM table.\n *\n * @param lpm\n * LPM object handle\n * @param ip\n * IP of the rule to be added to the LPM table\n * @param depth\n * Depth of the rule to be added to the LPM table\n * @param next_hop\n * Next hop of the rule to be added to the LPM table\n * @return\n * 0 on success, negative value otherwise\n */\nint\nrte_lpm6_add(struct rte_lpm6 *lpm, uint8_t *ip, uint8_t depth,\n\t\tuint8_t next_hop);\n\n/**\n * Check if a rule is present in the LPM table,\n * and provide its next hop if it is.\n *\n * @param lpm\n * LPM object handle\n * @param ip\n * IP of the rule to be searched\n * @param depth\n * Depth of the rule to searched\n * @param next_hop\n * Next hop of the rule (valid only if it is found)\n * @return\n * 1 if the rule exists, 0 if it does not, a negative value on failure\n */\nint\nrte_lpm6_is_rule_present(struct rte_lpm6 *lpm, uint8_t *ip, uint8_t depth,\nuint8_t *next_hop);\n\n/**\n * Delete a rule from the LPM table.\n *\n * @param lpm\n * LPM object handle\n * @param ip\n * IP of the rule to be deleted from the LPM table\n * @param depth\n * Depth of the rule to be deleted from the LPM table\n * @return\n * 0 on success, negative value otherwise\n */\nint\nrte_lpm6_delete(struct rte_lpm6 *lpm, uint8_t *ip, uint8_t depth);\n\n/**\n * Delete a rule from the LPM table.\n *\n * @param lpm\n * LPM object handle\n * @param ips\n * Array of IPs to be deleted from the LPM table\n * @param depths\n * Array of depths of the rules to be deleted from the LPM table\n * @param n\n * Number of rules to be deleted from the LPM table\n * @return\n * 0 on success, negative value otherwise.\n */\nint\nrte_lpm6_delete_bulk_func(struct rte_lpm6 *lpm,\n\t\tuint8_t ips[][RTE_LPM6_IPV6_ADDR_SIZE], uint8_t *depths, unsigned n);\n\n/**\n * Delete all rules from the LPM table.\n *\n * @param lpm\n * LPM object handle\n */\nvoid\nrte_lpm6_delete_all(struct rte_lpm6 *lpm);\n\n/**\n * Lookup an IP into the LPM table.\n *\n * @param lpm\n * LPM object handle\n * @param ip\n * IP to be looked up in the LPM table\n * @param next_hop\n * Next hop of the most specific rule found for IP (valid on lookup hit only)\n * @return\n * -EINVAL for incorrect arguments, -ENOENT on lookup miss, 0 on lookup hit\n */\nint\nrte_lpm6_lookup(const struct rte_lpm6 *lpm, uint8_t *ip, uint8_t *next_hop);\n\n/**\n * Lookup multiple IP addresses in an LPM table.\n *\n * @param lpm\n * LPM object handle\n * @param ips\n * Array of IPs to be looked up in the LPM table\n * @param next_hops\n * Next hop of the most specific rule found for IP (valid on lookup hit only).\n * This is an array of two byte values. The next hop will be stored on\n * each position on success; otherwise the position will be set to -1.\n * @param n\n * Number of elements in ips (and next_hops) array to lookup.\n * @return\n * -EINVAL for incorrect arguments, otherwise 0\n */\nint\nrte_lpm6_lookup_bulk_func(const struct rte_lpm6 *lpm,\n\t\tuint8_t ips[][RTE_LPM6_IPV6_ADDR_SIZE],\n\t\tint16_t * next_hops, unsigned n);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_malloc/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_malloc.a\n\nLIBABIVER := 1\n\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3\n\nEXPORT_MAP := rte_malloc_version.map\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_EAL) := rte_malloc_empty.c\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_EAL) += lib/librte_eal\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_malloc/rte_malloc_empty.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/* Empty file to be able to create a dummy library for deprecation policy */\n" }, { "path": "lib/librte_mbuf/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_mbuf.a\n\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3\n\nEXPORT_MAP := rte_mbuf_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_MBUF) := rte_mbuf.c\n\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_MBUF)-include := rte_mbuf.h\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_MBUF) += lib/librte_eal lib/librte_mempool\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_mbuf/rte_mbuf.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n/*\n * ctrlmbuf constructor, given as a callback function to\n * rte_mempool_create()\n */\nvoid\nrte_ctrlmbuf_init(struct rte_mempool *mp,\n\t\t__attribute__((unused)) void *opaque_arg,\n\t\tvoid *_m,\n\t\t__attribute__((unused)) unsigned i)\n{\n\tstruct rte_mbuf *m = _m;\n\trte_pktmbuf_init(mp, opaque_arg, _m, i);\n\tm->ol_flags |= CTRL_MBUF_FLAG;\n}\n\n/*\n * pktmbuf pool constructor, given as a callback function to\n * rte_mempool_create()\n */\nvoid\nrte_pktmbuf_pool_init(struct rte_mempool *mp, void *opaque_arg)\n{\n\tstruct rte_pktmbuf_pool_private *user_mbp_priv, *mbp_priv;\n\tstruct rte_pktmbuf_pool_private default_mbp_priv;\n\tuint16_t roomsz;\n\n\tRTE_MBUF_ASSERT(mp->elt_size >= sizeof(struct rte_mbuf));\n\n\t/* if no structure is provided, assume no mbuf private area */\n\tuser_mbp_priv = opaque_arg;\n\tif (user_mbp_priv == NULL) {\n\t\tdefault_mbp_priv.mbuf_priv_size = 0;\n\t\tif (mp->elt_size > sizeof(struct rte_mbuf))\n\t\t\troomsz = mp->elt_size - sizeof(struct rte_mbuf);\n\t\telse\n\t\t\troomsz = 0;\n\t\tdefault_mbp_priv.mbuf_data_room_size = roomsz;\n\t\tuser_mbp_priv = &default_mbp_priv;\n\t}\n\n\tRTE_MBUF_ASSERT(mp->elt_size >= sizeof(struct rte_mbuf) +\n\t\tuser_mbp_priv->mbuf_data_room_size +\n\t\tuser_mbp_priv->mbuf_priv_size);\n\n\tmbp_priv = rte_mempool_get_priv(mp);\n\tmemcpy(mbp_priv, user_mbp_priv, sizeof(*mbp_priv));\n}\n\n/*\n * pktmbuf constructor, given as a callback function to\n * rte_mempool_create().\n * Set the fields of a packet mbuf to their default values.\n */\nvoid\nrte_pktmbuf_init(struct rte_mempool *mp,\n\t\t __attribute__((unused)) void *opaque_arg,\n\t\t void *_m,\n\t\t __attribute__((unused)) unsigned i)\n{\n\tstruct rte_mbuf *m = _m;\n\tuint32_t mbuf_size, buf_len, priv_size;\n\n\tpriv_size = rte_pktmbuf_priv_size(mp);\n\tmbuf_size = sizeof(struct rte_mbuf) + priv_size;\n\tbuf_len = rte_pktmbuf_data_room_size(mp);\n\n\tRTE_MBUF_ASSERT(RTE_ALIGN(priv_size, RTE_MBUF_PRIV_ALIGN) == priv_size);\n\tRTE_MBUF_ASSERT(mp->elt_size >= mbuf_size);\n\tRTE_MBUF_ASSERT(buf_len <= UINT16_MAX);\n\n\tmemset(m, 0, mp->elt_size);\n\n\t/* start of buffer is after mbuf structure and priv data */\n\tm->priv_size = priv_size;\n\tm->buf_addr = (char *)m + mbuf_size;\n\tm->buf_physaddr = rte_mempool_virt2phy(mp, m) + mbuf_size;\n\tm->buf_len = (uint16_t)buf_len;\n\n\t/* keep some headroom between start of buffer and data */\n\tm->data_off = RTE_MIN(RTE_PKTMBUF_HEADROOM, (uint16_t)m->buf_len);\n\n\t/* init some constant fields */\n\tm->pool = mp;\n\tm->nb_segs = 1;\n\tm->port = 0xff;\n}\n\n/* helper to create a mbuf pool */\nstruct rte_mempool *\nrte_pktmbuf_pool_create(const char *name, unsigned n,\n\tunsigned cache_size, uint16_t priv_size, uint16_t data_room_size,\n\tint socket_id)\n{\n\tstruct rte_pktmbuf_pool_private mbp_priv;\n\tunsigned elt_size;\n\n\tif (RTE_ALIGN(priv_size, RTE_MBUF_PRIV_ALIGN) != priv_size) {\n\t\tRTE_LOG(ERR, MBUF, \"mbuf priv_size=%u is not aligned\\n\",\n\t\t\tpriv_size);\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\telt_size = sizeof(struct rte_mbuf) + (unsigned)priv_size +\n\t\t(unsigned)data_room_size;\n\tmbp_priv.mbuf_data_room_size = data_room_size;\n\tmbp_priv.mbuf_priv_size = priv_size;\n\n\treturn rte_mempool_create(name, n, elt_size,\n\t\tcache_size, sizeof(struct rte_pktmbuf_pool_private),\n\t\trte_pktmbuf_pool_init, &mbp_priv, rte_pktmbuf_init, NULL,\n\t\tsocket_id, 0);\n}\n\n/* do some sanity checks on a mbuf: panic if it fails */\nvoid\nrte_mbuf_sanity_check(const struct rte_mbuf *m, int is_header)\n{\n\tconst struct rte_mbuf *m_seg;\n\tunsigned nb_segs;\n\n\tif (m == NULL)\n\t\trte_panic(\"mbuf is NULL\\n\");\n\n\t/* generic checks */\n\tif (m->pool == NULL)\n\t\trte_panic(\"bad mbuf pool\\n\");\n\tif (m->buf_physaddr == 0)\n\t\trte_panic(\"bad phys addr\\n\");\n\tif (m->buf_addr == NULL)\n\t\trte_panic(\"bad virt addr\\n\");\n\n\tuint16_t cnt = rte_mbuf_refcnt_read(m);\n\tif ((cnt == 0) || (cnt == UINT16_MAX))\n\t\trte_panic(\"bad ref cnt\\n\");\n\n\t/* nothing to check for sub-segments */\n\tif (is_header == 0)\n\t\treturn;\n\n\tnb_segs = m->nb_segs;\n\tm_seg = m;\n\twhile (m_seg && nb_segs != 0) {\n\t\tm_seg = m_seg->next;\n\t\tnb_segs--;\n\t}\n\tif (nb_segs != 0)\n\t\trte_panic(\"bad nb_segs\\n\");\n}\n\n/* dump a mbuf on console */\nvoid\nrte_pktmbuf_dump(FILE *f, const struct rte_mbuf *m, unsigned dump_len)\n{\n\tunsigned int len;\n\tunsigned nb_segs;\n\n\t__rte_mbuf_sanity_check(m, 1);\n\n\tfprintf(f, \"dump mbuf at 0x%p, phys=%\"PRIx64\", buf_len=%u\\n\",\n\t m, (uint64_t)m->buf_physaddr, (unsigned)m->buf_len);\n\tfprintf(f, \" pkt_len=%\"PRIu32\", ol_flags=%\"PRIx64\", nb_segs=%u, \"\n\t \"in_port=%u\\n\", m->pkt_len, m->ol_flags,\n\t (unsigned)m->nb_segs, (unsigned)m->port);\n\tnb_segs = m->nb_segs;\n\n\twhile (m && nb_segs != 0) {\n\t\t__rte_mbuf_sanity_check(m, 0);\n\n\t\tfprintf(f, \" segment at 0x%p, data=0x%p, data_len=%u\\n\",\n\t\t\tm, rte_pktmbuf_mtod(m, void *), (unsigned)m->data_len);\n\t\tlen = dump_len;\n\t\tif (len > m->data_len)\n\t\t\tlen = m->data_len;\n\t\tif (len != 0)\n\t\t\trte_hexdump(f, NULL, rte_pktmbuf_mtod(m, void *), len);\n\t\tdump_len -= len;\n\t\tm = m->next;\n\t\tnb_segs --;\n\t}\n}\n\n/*\n * Get the name of a RX offload flag. Must be kept synchronized with flag\n * definitions in rte_mbuf.h.\n */\nconst char *rte_get_rx_ol_flag_name(uint64_t mask)\n{\n\tswitch (mask) {\n\tcase PKT_RX_VLAN_PKT: return \"PKT_RX_VLAN_PKT\";\n\tcase PKT_RX_RSS_HASH: return \"PKT_RX_RSS_HASH\";\n\tcase PKT_RX_FDIR: return \"PKT_RX_FDIR\";\n\tcase PKT_RX_L4_CKSUM_BAD: return \"PKT_RX_L4_CKSUM_BAD\";\n\tcase PKT_RX_IP_CKSUM_BAD: return \"PKT_RX_IP_CKSUM_BAD\";\n\t/* case PKT_RX_EIP_CKSUM_BAD: return \"PKT_RX_EIP_CKSUM_BAD\"; */\n\t/* case PKT_RX_OVERSIZE: return \"PKT_RX_OVERSIZE\"; */\n\t/* case PKT_RX_HBUF_OVERFLOW: return \"PKT_RX_HBUF_OVERFLOW\"; */\n\t/* case PKT_RX_RECIP_ERR: return \"PKT_RX_RECIP_ERR\"; */\n\t/* case PKT_RX_MAC_ERR: return \"PKT_RX_MAC_ERR\"; */\n#ifndef RTE_NEXT_ABI\n\tcase PKT_RX_IPV4_HDR: return \"PKT_RX_IPV4_HDR\";\n\tcase PKT_RX_IPV4_HDR_EXT: return \"PKT_RX_IPV4_HDR_EXT\";\n\tcase PKT_RX_IPV6_HDR: return \"PKT_RX_IPV6_HDR\";\n\tcase PKT_RX_IPV6_HDR_EXT: return \"PKT_RX_IPV6_HDR_EXT\";\n#endif /* RTE_NEXT_ABI */\n\tcase PKT_RX_IEEE1588_PTP: return \"PKT_RX_IEEE1588_PTP\";\n\tcase PKT_RX_IEEE1588_TMST: return \"PKT_RX_IEEE1588_TMST\";\n#ifndef RTE_NEXT_ABI\n\tcase PKT_RX_TUNNEL_IPV4_HDR: return \"PKT_RX_TUNNEL_IPV4_HDR\";\n\tcase PKT_RX_TUNNEL_IPV6_HDR: return \"PKT_RX_TUNNEL_IPV6_HDR\";\n#endif /* RTE_NEXT_ABI */\n\tdefault: return NULL;\n\t}\n}\n\n/*\n * Get the name of a TX offload flag. Must be kept synchronized with flag\n * definitions in rte_mbuf.h.\n */\nconst char *rte_get_tx_ol_flag_name(uint64_t mask)\n{\n\tswitch (mask) {\n\tcase PKT_TX_VLAN_PKT: return \"PKT_TX_VLAN_PKT\";\n\tcase PKT_TX_IP_CKSUM: return \"PKT_TX_IP_CKSUM\";\n\tcase PKT_TX_TCP_CKSUM: return \"PKT_TX_TCP_CKSUM\";\n\tcase PKT_TX_SCTP_CKSUM: return \"PKT_TX_SCTP_CKSUM\";\n\tcase PKT_TX_UDP_CKSUM: return \"PKT_TX_UDP_CKSUM\";\n\tcase PKT_TX_IEEE1588_TMST: return \"PKT_TX_IEEE1588_TMST\";\n\tcase PKT_TX_TCP_SEG: return \"PKT_TX_TCP_SEG\";\n\tcase PKT_TX_IPV4: return \"PKT_TX_IPV4\";\n\tcase PKT_TX_IPV6: return \"PKT_TX_IPV6\";\n\tcase PKT_TX_OUTER_IP_CKSUM: return \"PKT_TX_OUTER_IP_CKSUM\";\n\tcase PKT_TX_OUTER_IPV4: return \"PKT_TX_OUTER_IPV4\";\n\tcase PKT_TX_OUTER_IPV6: return \"PKT_TX_OUTER_IPV6\";\n\tdefault: return NULL;\n\t}\n}\n" }, { "path": "lib/librte_mbuf/rte_mbuf.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_MBUF_H_\n#define _RTE_MBUF_H_\n\n/**\n * @file\n * RTE Mbuf\n *\n * The mbuf library provides the ability to create and destroy buffers\n * that may be used by the RTE application to store message\n * buffers. The message buffers are stored in a mempool, using the\n * RTE mempool library.\n *\n * This library provide an API to allocate/free packet mbufs, which are\n * used to carry network packets.\n *\n * To understand the concepts of packet buffers or mbufs, you\n * should read \"TCP/IP Illustrated, Volume 2: The Implementation,\n * Addison-Wesley, 1995, ISBN 0-201-63354-X from Richard Stevens\"\n * http://www.kohala.com/start/tcpipiv2.html\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* deprecated options */\n#pragma GCC poison RTE_MBUF_SCATTER_GATHER\n#pragma GCC poison RTE_MBUF_REFCNT\n\n/*\n * Packet Offload Features Flags. It also carry packet type information.\n * Critical resources. Both rx/tx shared these bits. Be cautious on any change\n *\n * - RX flags start at bit position zero, and get added to the left of previous\n * flags.\n * - The most-significant 3 bits are reserved for generic mbuf flags\n * - TX flags therefore start at bit position 60 (i.e. 63-3), and new flags get\n * added to the right of the previously defined flags i.e. they should count\n * downwards, not upwards.\n *\n * Keep these flags synchronized with rte_get_rx_ol_flag_name() and\n * rte_get_tx_ol_flag_name().\n */\n#define PKT_RX_VLAN_PKT (1ULL << 0) /**< RX packet is a 802.1q VLAN packet. */\n#define PKT_RX_RSS_HASH (1ULL << 1) /**< RX packet with RSS hash result. */\n#define PKT_RX_FDIR (1ULL << 2) /**< RX packet with FDIR match indicate. */\n#define PKT_RX_L4_CKSUM_BAD (1ULL << 3) /**< L4 cksum of RX pkt. is not OK. */\n#define PKT_RX_IP_CKSUM_BAD (1ULL << 4) /**< IP cksum of RX pkt. is not OK. */\n#define PKT_RX_EIP_CKSUM_BAD (0ULL << 0) /**< External IP header checksum error. */\n#define PKT_RX_OVERSIZE (0ULL << 0) /**< Num of desc of an RX pkt oversize. */\n#define PKT_RX_HBUF_OVERFLOW (0ULL << 0) /**< Header buffer overflow. */\n#define PKT_RX_RECIP_ERR (0ULL << 0) /**< Hardware processing error. */\n#define PKT_RX_MAC_ERR (0ULL << 0) /**< MAC error. */\n#ifndef RTE_NEXT_ABI\n#define PKT_RX_IPV4_HDR (1ULL << 5) /**< RX packet with IPv4 header. */\n#define PKT_RX_IPV4_HDR_EXT (1ULL << 6) /**< RX packet with extended IPv4 header. */\n#define PKT_RX_IPV6_HDR (1ULL << 7) /**< RX packet with IPv6 header. */\n#define PKT_RX_IPV6_HDR_EXT (1ULL << 8) /**< RX packet with extended IPv6 header. */\n#endif /* RTE_NEXT_ABI */\n#define PKT_RX_IEEE1588_PTP (1ULL << 9) /**< RX IEEE1588 L2 Ethernet PT Packet. */\n#define PKT_RX_IEEE1588_TMST (1ULL << 10) /**< RX IEEE1588 L2/L4 timestamped packet.*/\n#ifndef RTE_NEXT_ABI\n#define PKT_RX_TUNNEL_IPV4_HDR (1ULL << 11) /**< RX tunnel packet with IPv4 header.*/\n#define PKT_RX_TUNNEL_IPV6_HDR (1ULL << 12) /**< RX tunnel packet with IPv6 header. */\n#endif /* RTE_NEXT_ABI */\n#define PKT_RX_FDIR_ID (1ULL << 13) /**< FD id reported if FDIR match. */\n#define PKT_RX_FDIR_FLX (1ULL << 14) /**< Flexible bytes reported if FDIR match. */\n#define PKT_RX_QINQ_PKT (1ULL << 15) /**< RX packet with double VLAN stripped. */\n/* add new RX flags here */\n\n/* add new TX flags here */\n\n/**\n * Second VLAN insertion (QinQ) flag.\n */\n#define PKT_TX_QINQ_PKT (1ULL << 49) /**< TX packet with double VLAN inserted. */\n\n/**\n * TCP segmentation offload. To enable this offload feature for a\n * packet to be transmitted on hardware supporting TSO:\n * - set the PKT_TX_TCP_SEG flag in mbuf->ol_flags (this flag implies\n * PKT_TX_TCP_CKSUM)\n * - set the flag PKT_TX_IPV4 or PKT_TX_IPV6\n * - if it's IPv4, set the PKT_TX_IP_CKSUM flag and write the IP checksum\n * to 0 in the packet\n * - fill the mbuf offload information: l2_len, l3_len, l4_len, tso_segsz\n * - calculate the pseudo header checksum without taking ip_len in account,\n * and set it in the TCP header. Refer to rte_ipv4_phdr_cksum() and\n * rte_ipv6_phdr_cksum() that can be used as helpers.\n */\n#define PKT_TX_TCP_SEG (1ULL << 50)\n\n#define PKT_TX_IEEE1588_TMST (1ULL << 51) /**< TX IEEE1588 packet to timestamp. */\n\n/**\n * Bits 52+53 used for L4 packet type with checksum enabled: 00: Reserved,\n * 01: TCP checksum, 10: SCTP checksum, 11: UDP checksum. To use hardware\n * L4 checksum offload, the user needs to:\n * - fill l2_len and l3_len in mbuf\n * - set the flags PKT_TX_TCP_CKSUM, PKT_TX_SCTP_CKSUM or PKT_TX_UDP_CKSUM\n * - set the flag PKT_TX_IPV4 or PKT_TX_IPV6\n * - calculate the pseudo header checksum and set it in the L4 header (only\n * for TCP or UDP). See rte_ipv4_phdr_cksum() and rte_ipv6_phdr_cksum().\n * For SCTP, set the crc field to 0.\n */\n#define PKT_TX_L4_NO_CKSUM (0ULL << 52) /**< Disable L4 cksum of TX pkt. */\n#define PKT_TX_TCP_CKSUM (1ULL << 52) /**< TCP cksum of TX pkt. computed by NIC. */\n#define PKT_TX_SCTP_CKSUM (2ULL << 52) /**< SCTP cksum of TX pkt. computed by NIC. */\n#define PKT_TX_UDP_CKSUM (3ULL << 52) /**< UDP cksum of TX pkt. computed by NIC. */\n#define PKT_TX_L4_MASK (3ULL << 52) /**< Mask for L4 cksum offload request. */\n\n/**\n * Offload the IP checksum in the hardware. The flag PKT_TX_IPV4 should\n * also be set by the application, although a PMD will only check\n * PKT_TX_IP_CKSUM.\n * - set the IP checksum field in the packet to 0\n * - fill the mbuf offload information: l2_len, l3_len\n */\n#define PKT_TX_IP_CKSUM (1ULL << 54)\n\n/**\n * Packet is IPv4. This flag must be set when using any offload feature\n * (TSO, L3 or L4 checksum) to tell the NIC that the packet is an IPv4\n * packet. If the packet is a tunneled packet, this flag is related to\n * the inner headers.\n */\n#define PKT_TX_IPV4 (1ULL << 55)\n\n/**\n * Packet is IPv6. This flag must be set when using an offload feature\n * (TSO or L4 checksum) to tell the NIC that the packet is an IPv6\n * packet. If the packet is a tunneled packet, this flag is related to\n * the inner headers.\n */\n#define PKT_TX_IPV6 (1ULL << 56)\n\n#define PKT_TX_VLAN_PKT (1ULL << 57) /**< TX packet is a 802.1q VLAN packet. */\n\n/**\n * Offload the IP checksum of an external header in the hardware. The\n * flag PKT_TX_OUTER_IPV4 should also be set by the application, alto ugh\n * a PMD will only check PKT_TX_IP_CKSUM. The IP checksum field in the\n * packet must be set to 0.\n * - set the outer IP checksum field in the packet to 0\n * - fill the mbuf offload information: outer_l2_len, outer_l3_len\n */\n#define PKT_TX_OUTER_IP_CKSUM (1ULL << 58)\n\n/**\n * Packet outer header is IPv4. This flag must be set when using any\n * outer offload feature (L3 or L4 checksum) to tell the NIC that the\n * outer header of the tunneled packet is an IPv4 packet.\n */\n#define PKT_TX_OUTER_IPV4 (1ULL << 59)\n\n/**\n * Packet outer header is IPv6. This flag must be set when using any\n * outer offload feature (L4 checksum) to tell the NIC that the outer\n * header of the tunneled packet is an IPv6 packet.\n */\n#define PKT_TX_OUTER_IPV6 (1ULL << 60)\n\n#define __RESERVED (1ULL << 61) /**< reserved for future mbuf use */\n\n#define IND_ATTACHED_MBUF (1ULL << 62) /**< Indirect attached mbuf */\n\n/* Use final bit of flags to indicate a control mbuf */\n#define CTRL_MBUF_FLAG (1ULL << 63) /**< Mbuf contains control data */\n\n#ifdef RTE_NEXT_ABI\n/*\n * 32 bits are divided into several fields to mark packet types. Note that\n * each field is indexical.\n * - Bit 3:0 is for L2 types.\n * - Bit 7:4 is for L3 or outer L3 (for tunneling case) types.\n * - Bit 11:8 is for L4 or outer L4 (for tunneling case) types.\n * - Bit 15:12 is for tunnel types.\n * - Bit 19:16 is for inner L2 types.\n * - Bit 23:20 is for inner L3 types.\n * - Bit 27:24 is for inner L4 types.\n * - Bit 31:28 is reserved.\n *\n * To be compatible with Vector PMD, RTE_PTYPE_L3_IPV4, RTE_PTYPE_L3_IPV4_EXT,\n * RTE_PTYPE_L3_IPV6, RTE_PTYPE_L3_IPV6_EXT, RTE_PTYPE_L4_TCP, RTE_PTYPE_L4_UDP\n * and RTE_PTYPE_L4_SCTP should be kept as below in a contiguous 7 bits.\n *\n * Note that L3 types values are selected for checking IPV4/IPV6 header from\n * performance point of view. Reading annotations of RTE_ETH_IS_IPV4_HDR and\n * RTE_ETH_IS_IPV6_HDR is needed for any future changes of L3 type values.\n *\n * Note that the packet types of the same packet recognized by different\n * hardware may be different, as different hardware may have different\n * capability of packet type recognition.\n *\n * examples:\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=0x29\n * | 'version'=6, 'next header'=0x3A\n * | 'ICMPv6 header'>\n * will be recognized on i40e hardware as packet type combination of,\n * RTE_PTYPE_L2_ETHER |\n * RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |\n * RTE_PTYPE_TUNNEL_IP |\n * RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n * RTE_PTYPE_INNER_L4_ICMP.\n *\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=0x2F\n * | 'GRE header'\n * | 'version'=6, 'next header'=0x11\n * | 'UDP header'>\n * will be recognized on i40e hardware as packet type combination of,\n * RTE_PTYPE_L2_ETHER |\n * RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |\n * RTE_PTYPE_TUNNEL_GRENAT |\n * RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |\n * RTE_PTYPE_INNER_L4_UDP.\n */\n#define RTE_PTYPE_UNKNOWN 0x00000000\n/**\n * Ethernet packet type.\n * It is used for outer packet for tunneling cases.\n *\n * Packet format:\n * <'ether type'=[0x0800|0x86DD]>\n */\n#define RTE_PTYPE_L2_ETHER 0x00000001\n/**\n * Ethernet packet type for time sync.\n *\n * Packet format:\n * <'ether type'=0x88F7>\n */\n#define RTE_PTYPE_L2_ETHER_TIMESYNC 0x00000002\n/**\n * ARP (Address Resolution Protocol) packet type.\n *\n * Packet format:\n * <'ether type'=0x0806>\n */\n#define RTE_PTYPE_L2_ETHER_ARP 0x00000003\n/**\n * LLDP (Link Layer Discovery Protocol) packet type.\n *\n * Packet format:\n * <'ether type'=0x88CC>\n */\n#define RTE_PTYPE_L2_ETHER_LLDP 0x00000004\n/**\n * Mask of layer 2 packet types.\n * It is used for outer packet for tunneling cases.\n */\n#define RTE_PTYPE_L2_MASK 0x0000000f\n/**\n * IP (Internet Protocol) version 4 packet type.\n * It is used for outer packet for tunneling cases, and does not contain any\n * header option.\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'ihl'=5>\n */\n#define RTE_PTYPE_L3_IPV4 0x00000010\n/**\n * IP (Internet Protocol) version 4 packet type.\n * It is used for outer packet for tunneling cases, and contains header\n * options.\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'ihl'=[6-15], 'options'>\n */\n#define RTE_PTYPE_L3_IPV4_EXT 0x00000030\n/**\n * IP (Internet Protocol) version 6 packet type.\n * It is used for outer packet for tunneling cases, and does not contain any\n * extension header.\n *\n * Packet format:\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=0x3B>\n */\n#define RTE_PTYPE_L3_IPV6 0x00000040\n/**\n * IP (Internet Protocol) version 4 packet type.\n * It is used for outer packet for tunneling cases, and may or maynot contain\n * header options.\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'ihl'=[5-15], <'options'>>\n */\n#define RTE_PTYPE_L3_IPV4_EXT_UNKNOWN 0x00000090\n/**\n * IP (Internet Protocol) version 6 packet type.\n * It is used for outer packet for tunneling cases, and contains extension\n * headers.\n *\n * Packet format:\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=[0x0|0x2B|0x2C|0x32|0x33|0x3C|0x87],\n * 'extension headers'>\n */\n#define RTE_PTYPE_L3_IPV6_EXT 0x000000c0\n/**\n * IP (Internet Protocol) version 6 packet type.\n * It is used for outer packet for tunneling cases, and may or maynot contain\n * extension headers.\n *\n * Packet format:\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=[0x3B|0x0|0x2B|0x2C|0x32|0x33|0x3C|0x87],\n * <'extension headers'>>\n */\n#define RTE_PTYPE_L3_IPV6_EXT_UNKNOWN 0x000000e0\n/**\n * Mask of layer 3 packet types.\n * It is used for outer packet for tunneling cases.\n */\n#define RTE_PTYPE_L3_MASK 0x000000f0\n/**\n * TCP (Transmission Control Protocol) packet type.\n * It is used for outer packet for tunneling cases.\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=6, 'MF'=0>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=6>\n */\n#define RTE_PTYPE_L4_TCP 0x00000100\n/**\n * UDP (User Datagram Protocol) packet type.\n * It is used for outer packet for tunneling cases.\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=17, 'MF'=0>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=17>\n */\n#define RTE_PTYPE_L4_UDP 0x00000200\n/**\n * Fragmented IP (Internet Protocol) packet type.\n * It is used for outer packet for tunneling cases.\n *\n * It refers to those packets of any IP types, which can be recognized as\n * fragmented. A fragmented packet cannot be recognized as any other L4 types\n * (RTE_PTYPE_L4_TCP, RTE_PTYPE_L4_UDP, RTE_PTYPE_L4_SCTP, RTE_PTYPE_L4_ICMP,\n * RTE_PTYPE_L4_NONFRAG).\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'MF'=1>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=44>\n */\n#define RTE_PTYPE_L4_FRAG 0x00000300\n/**\n * SCTP (Stream Control Transmission Protocol) packet type.\n * It is used for outer packet for tunneling cases.\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=132, 'MF'=0>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=132>\n */\n#define RTE_PTYPE_L4_SCTP 0x00000400\n/**\n * ICMP (Internet Control Message Protocol) packet type.\n * It is used for outer packet for tunneling cases.\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=1, 'MF'=0>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=1>\n */\n#define RTE_PTYPE_L4_ICMP 0x00000500\n/**\n * Non-fragmented IP (Internet Protocol) packet type.\n * It is used for outer packet for tunneling cases.\n *\n * It refers to those packets of any IP types, while cannot be recognized as\n * any of above L4 types (RTE_PTYPE_L4_TCP, RTE_PTYPE_L4_UDP,\n * RTE_PTYPE_L4_FRAG, RTE_PTYPE_L4_SCTP, RTE_PTYPE_L4_ICMP).\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'!=[6|17|132|1], 'MF'=0>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'!=[6|17|44|132|1]>\n */\n#define RTE_PTYPE_L4_NONFRAG 0x00000600\n/**\n * Mask of layer 4 packet types.\n * It is used for outer packet for tunneling cases.\n */\n#define RTE_PTYPE_L4_MASK 0x00000f00\n/**\n * IP (Internet Protocol) in IP (Internet Protocol) tunneling packet type.\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=[4|41]>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=[4|41]>\n */\n#define RTE_PTYPE_TUNNEL_IP 0x00001000\n/**\n * GRE (Generic Routing Encapsulation) tunneling packet type.\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=47>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=47>\n */\n#define RTE_PTYPE_TUNNEL_GRE 0x00002000\n/**\n * VXLAN (Virtual eXtensible Local Area Network) tunneling packet type.\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=17\n * | 'destination port'=4798>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=17\n * | 'destination port'=4798>\n */\n#define RTE_PTYPE_TUNNEL_VXLAN 0x00003000\n/**\n * NVGRE (Network Virtualization using Generic Routing Encapsulation) tunneling\n * packet type.\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=47\n * | 'protocol type'=0x6558>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=47\n * | 'protocol type'=0x6558'>\n */\n#define RTE_PTYPE_TUNNEL_NVGRE 0x00004000\n/**\n * GENEVE (Generic Network Virtualization Encapsulation) tunneling packet type.\n *\n * Packet format:\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=17\n * | 'destination port'=6081>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=17\n * | 'destination port'=6081>\n */\n#define RTE_PTYPE_TUNNEL_GENEVE 0x00005000\n/**\n * Tunneling packet type of Teredo, VXLAN (Virtual eXtensible Local Area\n * Network) or GRE (Generic Routing Encapsulation) could be recognized as this\n * packet type, if they can not be recognized independently as of hardware\n * capability.\n */\n#define RTE_PTYPE_TUNNEL_GRENAT 0x00006000\n/**\n * Mask of tunneling packet types.\n */\n#define RTE_PTYPE_TUNNEL_MASK 0x0000f000\n/**\n * Ethernet packet type.\n * It is used for inner packet type only.\n *\n * Packet format (inner only):\n * <'ether type'=[0x800|0x86DD]>\n */\n#define RTE_PTYPE_INNER_L2_ETHER 0x00010000\n/**\n * Ethernet packet type with VLAN (Virtual Local Area Network) tag.\n *\n * Packet format (inner only):\n * <'ether type'=[0x800|0x86DD], vlan=[1-4095]>\n */\n#define RTE_PTYPE_INNER_L2_ETHER_VLAN 0x00020000\n/**\n * Mask of inner layer 2 packet types.\n */\n#define RTE_PTYPE_INNER_L2_MASK 0x000f0000\n/**\n * IP (Internet Protocol) version 4 packet type.\n * It is used for inner packet only, and does not contain any header option.\n *\n * Packet format (inner only):\n * <'ether type'=0x0800\n * | 'version'=4, 'ihl'=5>\n */\n#define RTE_PTYPE_INNER_L3_IPV4 0x00100000\n/**\n * IP (Internet Protocol) version 4 packet type.\n * It is used for inner packet only, and contains header options.\n *\n * Packet format (inner only):\n * <'ether type'=0x0800\n * | 'version'=4, 'ihl'=[6-15], 'options'>\n */\n#define RTE_PTYPE_INNER_L3_IPV4_EXT 0x00200000\n/**\n * IP (Internet Protocol) version 6 packet type.\n * It is used for inner packet only, and does not contain any extension header.\n *\n * Packet format (inner only):\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=0x3B>\n */\n#define RTE_PTYPE_INNER_L3_IPV6 0x00300000\n/**\n * IP (Internet Protocol) version 4 packet type.\n * It is used for inner packet only, and may or maynot contain header options.\n *\n * Packet format (inner only):\n * <'ether type'=0x0800\n * | 'version'=4, 'ihl'=[5-15], <'options'>>\n */\n#define RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN 0x00400000\n/**\n * IP (Internet Protocol) version 6 packet type.\n * It is used for inner packet only, and contains extension headers.\n *\n * Packet format (inner only):\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=[0x0|0x2B|0x2C|0x32|0x33|0x3C|0x87],\n * 'extension headers'>\n */\n#define RTE_PTYPE_INNER_L3_IPV6_EXT 0x00500000\n/**\n * IP (Internet Protocol) version 6 packet type.\n * It is used for inner packet only, and may or maynot contain extension\n * headers.\n *\n * Packet format (inner only):\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=[0x3B|0x0|0x2B|0x2C|0x32|0x33|0x3C|0x87],\n * <'extension headers'>>\n */\n#define RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN 0x00600000\n/**\n * Mask of inner layer 3 packet types.\n */\n#define RTE_PTYPE_INNER_L3_MASK 0x00f00000\n/**\n * TCP (Transmission Control Protocol) packet type.\n * It is used for inner packet only.\n *\n * Packet format (inner only):\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=6, 'MF'=0>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=6>\n */\n#define RTE_PTYPE_INNER_L4_TCP 0x01000000\n/**\n * UDP (User Datagram Protocol) packet type.\n * It is used for inner packet only.\n *\n * Packet format (inner only):\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=17, 'MF'=0>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=17>\n */\n#define RTE_PTYPE_INNER_L4_UDP 0x02000000\n/**\n * Fragmented IP (Internet Protocol) packet type.\n * It is used for inner packet only, and may or maynot have layer 4 packet.\n *\n * Packet format (inner only):\n * <'ether type'=0x0800\n * | 'version'=4, 'MF'=1>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=44>\n */\n#define RTE_PTYPE_INNER_L4_FRAG 0x03000000\n/**\n * SCTP (Stream Control Transmission Protocol) packet type.\n * It is used for inner packet only.\n *\n * Packet format (inner only):\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=132, 'MF'=0>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=132>\n */\n#define RTE_PTYPE_INNER_L4_SCTP 0x04000000\n/**\n * ICMP (Internet Control Message Protocol) packet type.\n * It is used for inner packet only.\n *\n * Packet format (inner only):\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'=1, 'MF'=0>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'=1>\n */\n#define RTE_PTYPE_INNER_L4_ICMP 0x05000000\n/**\n * Non-fragmented IP (Internet Protocol) packet type.\n * It is used for inner packet only, and may or maynot have other unknown layer\n * 4 packet types.\n *\n * Packet format (inner only):\n * <'ether type'=0x0800\n * | 'version'=4, 'protocol'!=[6|17|132|1], 'MF'=0>\n * or,\n * <'ether type'=0x86DD\n * | 'version'=6, 'next header'!=[6|17|44|132|1]>\n */\n#define RTE_PTYPE_INNER_L4_NONFRAG 0x06000000\n/**\n * Mask of inner layer 4 packet types.\n */\n#define RTE_PTYPE_INNER_L4_MASK 0x0f000000\n\n/**\n * Check if the (outer) L3 header is IPv4. To avoid comparing IPv4 types one by\n * one, bit 4 is selected to be used for IPv4 only. Then checking bit 4 can\n * determine if it is an IPV4 packet.\n */\n#define RTE_ETH_IS_IPV4_HDR(ptype) ((ptype) & RTE_PTYPE_L3_IPV4)\n\n/**\n * Check if the (outer) L3 header is IPv4. To avoid comparing IPv4 types one by\n * one, bit 6 is selected to be used for IPv4 only. Then checking bit 6 can\n * determine if it is an IPV4 packet.\n */\n#define RTE_ETH_IS_IPV6_HDR(ptype) ((ptype) & RTE_PTYPE_L3_IPV6)\n\n/* Check if it is a tunneling packet */\n#define RTE_ETH_IS_TUNNEL_PKT(ptype) ((ptype) & (RTE_PTYPE_TUNNEL_MASK | \\\n RTE_PTYPE_INNER_L2_MASK | \\\n RTE_PTYPE_INNER_L3_MASK | \\\n RTE_PTYPE_INNER_L4_MASK))\n#endif /* RTE_NEXT_ABI */\n\n/** Alignment constraint of mbuf private area. */\n#define RTE_MBUF_PRIV_ALIGN 8\n\n/**\n * Get the name of a RX offload flag\n *\n * @param mask\n * The mask describing the flag.\n * @return\n * The name of this flag, or NULL if it's not a valid RX flag.\n */\nconst char *rte_get_rx_ol_flag_name(uint64_t mask);\n\n/**\n * Get the name of a TX offload flag\n *\n * @param mask\n * The mask describing the flag. Usually only one bit must be set.\n * Several bits can be given if they belong to the same mask.\n * Ex: PKT_TX_L4_MASK.\n * @return\n * The name of this flag, or NULL if it's not a valid TX flag.\n */\nconst char *rte_get_tx_ol_flag_name(uint64_t mask);\n\n/**\n * Some NICs need at least 2KB buffer to RX standard Ethernet frame without\n * splitting it into multiple segments.\n * So, for mbufs that planned to be involved into RX/TX, the recommended\n * minimal buffer length is 2KB + RTE_PKTMBUF_HEADROOM.\n */\n#define\tRTE_MBUF_DEFAULT_DATAROOM\t2048\n#define\tRTE_MBUF_DEFAULT_BUF_SIZE\t\\\n\t(RTE_MBUF_DEFAULT_DATAROOM + RTE_PKTMBUF_HEADROOM)\n\n/* define a set of marker types that can be used to refer to set points in the\n * mbuf */\ntypedef void *MARKER[0]; /**< generic marker for a point in a structure */\ntypedef uint8_t MARKER8[0]; /**< generic marker with 1B alignment */\ntypedef uint64_t MARKER64[0]; /**< marker that allows us to overwrite 8 bytes\n * with a single assignment */\n\n/**\n * The generic rte_mbuf, containing a packet mbuf.\n */\nstruct rte_mbuf {\n\tMARKER cacheline0;\n\n\tvoid *buf_addr; /**< Virtual address of segment buffer. */\n\tphys_addr_t buf_physaddr; /**< Physical address of segment buffer. */\n\n\tuint16_t buf_len; /**< Length of segment buffer. */\n\n\t/* next 6 bytes are initialised on RX descriptor rearm */\n\tMARKER8 rearm_data;\n\tuint16_t data_off;\n\n\t/**\n\t * 16-bit Reference counter.\n\t * It should only be accessed using the following functions:\n\t * rte_mbuf_refcnt_update(), rte_mbuf_refcnt_read(), and\n\t * rte_mbuf_refcnt_set(). The functionality of these functions (atomic,\n\t * or non-atomic) is controlled by the CONFIG_RTE_MBUF_REFCNT_ATOMIC\n\t * config option.\n\t */\n\tunion {\n\t\trte_atomic16_t refcnt_atomic; /**< Atomically accessed refcnt */\n\t\tuint16_t refcnt; /**< Non-atomically accessed refcnt */\n\t};\n\tuint8_t nb_segs; /**< Number of segments. */\n\tuint8_t port; /**< Input port. */\n\n\tuint64_t ol_flags; /**< Offload features. */\n\n\t/* remaining bytes are set on RX when pulling packet from descriptor */\n\tMARKER rx_descriptor_fields1;\n\n#ifdef RTE_NEXT_ABI\n\t/*\n\t * The packet type, which is the combination of outer/inner L2, L3, L4\n\t * and tunnel types.\n\t */\n\tunion {\n\t\tuint32_t packet_type; /**< L2/L3/L4 and tunnel information. */\n\t\tstruct {\n\t\t\tuint32_t l2_type:4; /**< (Outer) L2 type. */\n\t\t\tuint32_t l3_type:4; /**< (Outer) L3 type. */\n\t\t\tuint32_t l4_type:4; /**< (Outer) L4 type. */\n\t\t\tuint32_t tun_type:4; /**< Tunnel type. */\n\t\t\tuint32_t inner_l2_type:4; /**< Inner L2 type. */\n\t\t\tuint32_t inner_l3_type:4; /**< Inner L3 type. */\n\t\t\tuint32_t inner_l4_type:4; /**< Inner L4 type. */\n\t\t};\n\t};\n\n\tuint32_t pkt_len; /**< Total pkt len: sum of all segments. */\n\tuint16_t data_len; /**< Amount of data in segment buffer. */\n\tuint16_t vlan_tci; /**< VLAN Tag Control Identifier (CPU order) */\n#else /* RTE_NEXT_ABI */\n\t/**\n\t * The packet type, which is used to indicate ordinary packet and also\n\t * tunneled packet format, i.e. each number is represented a type of\n\t * packet.\n\t */\n\tuint16_t packet_type;\n\n\tuint16_t data_len; /**< Amount of data in segment buffer. */\n\tuint32_t pkt_len; /**< Total pkt len: sum of all segments. */\n\tuint16_t vlan_tci; /**< VLAN Tag Control Identifier (CPU order) */\n\tuint16_t vlan_tci_outer; /**< Outer VLAN Tag Control Identifier (CPU order) */\n#endif /* RTE_NEXT_ABI */\n\tunion {\n\t\tuint32_t rss; /**< RSS hash result if RSS enabled */\n\t\tstruct {\n\t\t\tunion {\n\t\t\t\tstruct {\n\t\t\t\t\tuint16_t hash;\n\t\t\t\t\tuint16_t id;\n\t\t\t\t};\n\t\t\t\tuint32_t lo;\n\t\t\t\t/**< Second 4 flexible bytes */\n\t\t\t};\n\t\t\tuint32_t hi;\n\t\t\t/**< First 4 flexible bytes or FD ID, dependent on\n\t\t\t PKT_RX_FDIR_* flag in ol_flags. */\n\t\t} fdir; /**< Filter identifier if FDIR enabled */\n\t\tuint32_t sched; /**< Hierarchical scheduler */\n\t\tuint32_t usr;\t /**< User defined tags. See rte_distributor_process() */\n\t} hash; /**< hash information */\n\n\tuint32_t seqn; /**< Sequence number. See also rte_reorder_insert() */\n#ifdef RTE_NEXT_ABI\n\tuint16_t vlan_tci_outer; /**< Outer VLAN Tag Control Identifier (CPU order) */\n#endif /* RTE_NEXT_ABI */\n\n\t/* second cache line - fields only used in slow path or on TX */\n\tMARKER cacheline1 __rte_cache_aligned;\n\n\tunion {\n\t\tvoid *userdata; /**< Can be used for external metadata */\n\t\tuint64_t udata64; /**< Allow 8-byte userdata on 32-bit */\n\t};\n\n\tstruct rte_mempool *pool; /**< Pool from which mbuf was allocated. */\n\tstruct rte_mbuf *next; /**< Next segment of scattered packet. */\n\n\t/* fields to support TX offloads */\n\tunion {\n\t\tuint64_t tx_offload; /**< combined for easy fetch */\n\t\tstruct {\n\t\t\tuint64_t l2_len:7; /**< L2 (MAC) Header Length. */\n\t\t\tuint64_t l3_len:9; /**< L3 (IP) Header Length. */\n\t\t\tuint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */\n\t\t\tuint64_t tso_segsz:16; /**< TCP TSO segment size */\n\n\t\t\t/* fields for TX offloading of tunnels */\n\t\t\tuint64_t outer_l3_len:9; /**< Outer L3 (IP) Hdr Length. */\n\t\t\tuint64_t outer_l2_len:7; /**< Outer L2 (MAC) Hdr Length. */\n\n\t\t\t/* uint64_t unused:8; */\n\t\t};\n\t};\n\n\t/** Size of the application private data. In case of an indirect\n\t * mbuf, it stores the direct mbuf private data size. */\n\tuint16_t priv_size;\n\n\t/** Timesync flags for use with IEEE1588. */\n\tuint16_t timesync;\n} __rte_cache_aligned;\n\nstatic inline uint16_t rte_pktmbuf_priv_size(struct rte_mempool *mp);\n\n/**\n * Return the mbuf owning the data buffer address of an indirect mbuf.\n *\n * @param mi\n * The pointer to the indirect mbuf.\n * @return\n * The address of the direct mbuf corresponding to buffer_addr.\n */\nstatic inline struct rte_mbuf *\nrte_mbuf_from_indirect(struct rte_mbuf *mi)\n{\n\treturn (struct rte_mbuf *)RTE_PTR_SUB(mi->buf_addr, sizeof(*mi) + mi->priv_size);\n}\n\n/**\n * Return the buffer address embedded in the given mbuf.\n *\n * @param md\n * The pointer to the mbuf.\n * @return\n * The address of the data buffer owned by the mbuf.\n */\nstatic inline char *\nrte_mbuf_to_baddr(struct rte_mbuf *md)\n{\n\tchar *buffer_addr;\n\tbuffer_addr = (char *)md + sizeof(*md) + rte_pktmbuf_priv_size(md->pool);\n\treturn buffer_addr;\n}\n\n/**\n * Returns TRUE if given mbuf is indirect, or FALSE otherwise.\n */\n#define RTE_MBUF_INDIRECT(mb) ((mb)->ol_flags & IND_ATTACHED_MBUF)\n\n/**\n * Returns TRUE if given mbuf is direct, or FALSE otherwise.\n */\n#define RTE_MBUF_DIRECT(mb) (!RTE_MBUF_INDIRECT(mb))\n\n/**\n * Private data in case of pktmbuf pool.\n *\n * A structure that contains some pktmbuf_pool-specific data that are\n * appended after the mempool structure (in private data).\n */\nstruct rte_pktmbuf_pool_private {\n\tuint16_t mbuf_data_room_size; /**< Size of data space in each mbuf. */\n\tuint16_t mbuf_priv_size; /**< Size of private area in each mbuf. */\n};\n\n#ifdef RTE_LIBRTE_MBUF_DEBUG\n\n/** check mbuf type in debug mode */\n#define __rte_mbuf_sanity_check(m, is_h) rte_mbuf_sanity_check(m, is_h)\n\n/** check mbuf type in debug mode if mbuf pointer is not null */\n#define __rte_mbuf_sanity_check_raw(m, is_h)\tdo { \\\n\tif ((m) != NULL) \\\n\t\trte_mbuf_sanity_check(m, is_h); \\\n} while (0)\n\n/** MBUF asserts in debug mode */\n#define RTE_MBUF_ASSERT(exp) \\\nif (!(exp)) { \\\n\trte_panic(\"line%d\\tassert \\\"\" #exp \"\\\" failed\\n\", __LINE__); \\\n}\n\n#else /* RTE_LIBRTE_MBUF_DEBUG */\n\n/** check mbuf type in debug mode */\n#define __rte_mbuf_sanity_check(m, is_h) do { } while (0)\n\n/** check mbuf type in debug mode if mbuf pointer is not null */\n#define __rte_mbuf_sanity_check_raw(m, is_h) do { } while (0)\n\n/** MBUF asserts in debug mode */\n#define RTE_MBUF_ASSERT(exp) do { } while (0)\n\n#endif /* RTE_LIBRTE_MBUF_DEBUG */\n\n#ifdef RTE_MBUF_REFCNT_ATOMIC\n\n/**\n * Reads the value of an mbuf's refcnt.\n * @param m\n * Mbuf to read\n * @return\n * Reference count number.\n */\nstatic inline uint16_t\nrte_mbuf_refcnt_read(const struct rte_mbuf *m)\n{\n\treturn (uint16_t)(rte_atomic16_read(&m->refcnt_atomic));\n}\n\n/**\n * Sets an mbuf's refcnt to a defined value.\n * @param m\n * Mbuf to update\n * @param new_value\n * Value set\n */\nstatic inline void\nrte_mbuf_refcnt_set(struct rte_mbuf *m, uint16_t new_value)\n{\n\trte_atomic16_set(&m->refcnt_atomic, new_value);\n}\n\n/**\n * Adds given value to an mbuf's refcnt and returns its new value.\n * @param m\n * Mbuf to update\n * @param value\n * Value to add/subtract\n * @return\n * Updated value\n */\nstatic inline uint16_t\nrte_mbuf_refcnt_update(struct rte_mbuf *m, int16_t value)\n{\n\t/*\n\t * The atomic_add is an expensive operation, so we don't want to\n\t * call it in the case where we know we are the uniq holder of\n\t * this mbuf (i.e. ref_cnt == 1). Otherwise, an atomic\n\t * operation has to be used because concurrent accesses on the\n\t * reference counter can occur.\n\t */\n\tif (likely(rte_mbuf_refcnt_read(m) == 1)) {\n\t\trte_mbuf_refcnt_set(m, 1 + value);\n\t\treturn 1 + value;\n\t}\n\n\treturn (uint16_t)(rte_atomic16_add_return(&m->refcnt_atomic, value));\n}\n\n#else /* ! RTE_MBUF_REFCNT_ATOMIC */\n\n/**\n * Adds given value to an mbuf's refcnt and returns its new value.\n */\nstatic inline uint16_t\nrte_mbuf_refcnt_update(struct rte_mbuf *m, int16_t value)\n{\n\tm->refcnt = (uint16_t)(m->refcnt + value);\n\treturn m->refcnt;\n}\n\n/**\n * Reads the value of an mbuf's refcnt.\n */\nstatic inline uint16_t\nrte_mbuf_refcnt_read(const struct rte_mbuf *m)\n{\n\treturn m->refcnt;\n}\n\n/**\n * Sets an mbuf's refcnt to the defined value.\n */\nstatic inline void\nrte_mbuf_refcnt_set(struct rte_mbuf *m, uint16_t new_value)\n{\n\tm->refcnt = new_value;\n}\n\n#endif /* RTE_MBUF_REFCNT_ATOMIC */\n\n/** Mbuf prefetch */\n#define RTE_MBUF_PREFETCH_TO_FREE(m) do { \\\n\tif ((m) != NULL) \\\n\t\trte_prefetch0(m); \\\n} while (0)\n\n\n/**\n * Sanity checks on an mbuf.\n *\n * Check the consistency of the given mbuf. The function will cause a\n * panic if corruption is detected.\n *\n * @param m\n * The mbuf to be checked.\n * @param is_header\n * True if the mbuf is a packet header, false if it is a sub-segment\n * of a packet (in this case, some fields like nb_segs are not checked)\n */\nvoid\nrte_mbuf_sanity_check(const struct rte_mbuf *m, int is_header);\n\n/**\n * @internal Allocate a new mbuf from mempool *mp*.\n * The use of that function is reserved for RTE internal needs.\n * Please use rte_pktmbuf_alloc().\n *\n * @param mp\n * The mempool from which mbuf is allocated.\n * @return\n * - The pointer to the new mbuf on success.\n * - NULL if allocation failed.\n */\nstatic inline struct rte_mbuf *__rte_mbuf_raw_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\tvoid *mb = NULL;\n\tif (rte_mempool_get(mp, &mb) < 0)\n\t\treturn NULL;\n\tm = (struct rte_mbuf *)mb;\n\tRTE_MBUF_ASSERT(rte_mbuf_refcnt_read(m) == 0);\n\trte_mbuf_refcnt_set(m, 1);\n\treturn m;\n}\n\n/**\n * @internal Put mbuf back into its original mempool.\n * The use of that function is reserved for RTE internal needs.\n * Please use rte_pktmbuf_free().\n *\n * @param m\n * The mbuf to be freed.\n */\nstatic inline void __attribute__((always_inline))\n__rte_mbuf_raw_free(struct rte_mbuf *m)\n{\n\tRTE_MBUF_ASSERT(rte_mbuf_refcnt_read(m) == 0);\n\trte_mempool_put(m->pool, m);\n}\n\n/* Operations on ctrl mbuf */\n\n/**\n * The control mbuf constructor.\n *\n * This function initializes some fields in an mbuf structure that are\n * not modified by the user once created (mbuf type, origin pool, buffer\n * start address, and so on). This function is given as a callback function\n * to rte_mempool_create() at pool creation time.\n *\n * @param mp\n * The mempool from which the mbuf is allocated.\n * @param opaque_arg\n * A pointer that can be used by the user to retrieve useful information\n * for mbuf initialization. This pointer comes from the ``init_arg``\n * parameter of rte_mempool_create().\n * @param m\n * The mbuf to initialize.\n * @param i\n * The index of the mbuf in the pool table.\n */\nvoid rte_ctrlmbuf_init(struct rte_mempool *mp, void *opaque_arg,\n\t\tvoid *m, unsigned i);\n\n/**\n * Allocate a new mbuf (type is ctrl) from mempool *mp*.\n *\n * This new mbuf is initialized with data pointing to the beginning of\n * buffer, and with a length of zero.\n *\n * @param mp\n * The mempool from which the mbuf is allocated.\n * @return\n * - The pointer to the new mbuf on success.\n * - NULL if allocation failed.\n */\n#define rte_ctrlmbuf_alloc(mp) rte_pktmbuf_alloc(mp)\n\n/**\n * Free a control mbuf back into its original mempool.\n *\n * @param m\n * The control mbuf to be freed.\n */\n#define rte_ctrlmbuf_free(m) rte_pktmbuf_free(m)\n\n/**\n * A macro that returns the pointer to the carried data.\n *\n * The value that can be read or assigned.\n *\n * @param m\n * The control mbuf.\n */\n#define rte_ctrlmbuf_data(m) ((char *)((m)->buf_addr) + (m)->data_off)\n\n/**\n * A macro that returns the length of the carried data.\n *\n * The value that can be read or assigned.\n *\n * @param m\n * The control mbuf.\n */\n#define rte_ctrlmbuf_len(m) rte_pktmbuf_data_len(m)\n\n/**\n * Tests if an mbuf is a control mbuf\n *\n * @param m\n * The mbuf to be tested\n * @return\n * - True (1) if the mbuf is a control mbuf\n * - False(0) otherwise\n */\nstatic inline int\nrte_is_ctrlmbuf(struct rte_mbuf *m)\n{\n\treturn !!(m->ol_flags & CTRL_MBUF_FLAG);\n}\n\n/* Operations on pkt mbuf */\n\n/**\n * The packet mbuf constructor.\n *\n * This function initializes some fields in the mbuf structure that are\n * not modified by the user once created (origin pool, buffer start\n * address, and so on). This function is given as a callback function to\n * rte_mempool_create() at pool creation time.\n *\n * @param mp\n * The mempool from which mbufs originate.\n * @param opaque_arg\n * A pointer that can be used by the user to retrieve useful information\n * for mbuf initialization. This pointer comes from the ``init_arg``\n * parameter of rte_mempool_create().\n * @param m\n * The mbuf to initialize.\n * @param i\n * The index of the mbuf in the pool table.\n */\nvoid rte_pktmbuf_init(struct rte_mempool *mp, void *opaque_arg,\n\t\t void *m, unsigned i);\n\n\n/**\n * A packet mbuf pool constructor.\n *\n * This function initializes the mempool private data in the case of a\n * pktmbuf pool. This private data is needed by the driver. The\n * function is given as a callback function to rte_mempool_create() at\n * pool creation. It can be extended by the user, for example, to\n * provide another packet size.\n *\n * @param mp\n * The mempool from which mbufs originate.\n * @param opaque_arg\n * A pointer that can be used by the user to retrieve useful information\n * for mbuf initialization. This pointer comes from the ``init_arg``\n * parameter of rte_mempool_create().\n */\nvoid rte_pktmbuf_pool_init(struct rte_mempool *mp, void *opaque_arg);\n\n/**\n * Create a mbuf pool.\n *\n * This function creates and initializes a packet mbuf pool. It is\n * a wrapper to rte_mempool_create() with the proper packet constructor\n * and mempool constructor.\n *\n * @param name\n * The name of the mbuf pool.\n * @param n\n * The number of elements in the mbuf pool. The optimum size (in terms\n * of memory usage) for a mempool is when n is a power of two minus one:\n * n = (2^q - 1).\n * @param cache_size\n * Size of the per-core object cache. See rte_mempool_create() for\n * details.\n * @param priv_size\n * Size of application private are between the rte_mbuf structure\n * and the data buffer. This value must be aligned to RTE_MBUF_PRIV_ALIGN.\n * @param data_room_size\n * Size of data buffer in each mbuf, including RTE_PKTMBUF_HEADROOM.\n * @param socket_id\n * The socket identifier where the memory should be allocated. The\n * value can be *SOCKET_ID_ANY* if there is no NUMA constraint for the\n * reserved zone.\n * @return\n * The pointer to the new allocated mempool, on success. NULL on error\n * with rte_errno set appropriately. Possible rte_errno values include:\n * - E_RTE_NO_CONFIG - function could not get pointer to rte_config structure\n * - E_RTE_SECONDARY - function was called from a secondary process instance\n * - EINVAL - cache size provided is too large, or priv_size is not aligned.\n * - ENOSPC - the maximum number of memzones has already been allocated\n * - EEXIST - a memzone with the same name already exists\n * - ENOMEM - no appropriate memory area found in which to create memzone\n */\nstruct rte_mempool *\nrte_pktmbuf_pool_create(const char *name, unsigned n,\n\tunsigned cache_size, uint16_t priv_size, uint16_t data_room_size,\n\tint socket_id);\n\n/**\n * Get the data room size of mbufs stored in a pktmbuf_pool\n *\n * The data room size is the amount of data that can be stored in a\n * mbuf including the headroom (RTE_PKTMBUF_HEADROOM).\n *\n * @param mp\n * The packet mbuf pool.\n * @return\n * The data room size of mbufs stored in this mempool.\n */\nstatic inline uint16_t\nrte_pktmbuf_data_room_size(struct rte_mempool *mp)\n{\n\tstruct rte_pktmbuf_pool_private *mbp_priv;\n\n\tmbp_priv = (struct rte_pktmbuf_pool_private *)rte_mempool_get_priv(mp);\n\treturn mbp_priv->mbuf_data_room_size;\n}\n\n/**\n * Get the application private size of mbufs stored in a pktmbuf_pool\n *\n * The private size of mbuf is a zone located between the rte_mbuf\n * structure and the data buffer where an application can store data\n * associated to a packet.\n *\n * @param mp\n * The packet mbuf pool.\n * @return\n * The private size of mbufs stored in this mempool.\n */\nstatic inline uint16_t\nrte_pktmbuf_priv_size(struct rte_mempool *mp)\n{\n\tstruct rte_pktmbuf_pool_private *mbp_priv;\n\n\tmbp_priv = (struct rte_pktmbuf_pool_private *)rte_mempool_get_priv(mp);\n\treturn mbp_priv->mbuf_priv_size;\n}\n\n/**\n * Reset the fields of a packet mbuf to their default values.\n *\n * The given mbuf must have only one segment.\n *\n * @param m\n * The packet mbuf to be resetted.\n */\nstatic inline void rte_pktmbuf_reset(struct rte_mbuf *m)\n{\n\tm->next = NULL;\n\tm->pkt_len = 0;\n\tm->tx_offload = 0;\n\tm->vlan_tci = 0;\n\tm->vlan_tci_outer = 0;\n\tm->nb_segs = 1;\n\tm->port = 0xff;\n\n\tm->ol_flags = 0;\n\tm->packet_type = 0;\n\tm->data_off = (RTE_PKTMBUF_HEADROOM <= m->buf_len) ?\n\t\t\tRTE_PKTMBUF_HEADROOM : m->buf_len;\n\n\tm->data_len = 0;\n\t__rte_mbuf_sanity_check(m, 1);\n}\n\n/**\n * Allocate a new mbuf from a mempool.\n *\n * This new mbuf contains one segment, which has a length of 0. The pointer\n * to data is initialized to have some bytes of headroom in the buffer\n * (if buffer size allows).\n *\n * @param mp\n * The mempool from which the mbuf is allocated.\n * @return\n * - The pointer to the new mbuf on success.\n * - NULL if allocation failed.\n */\nstatic inline struct rte_mbuf *rte_pktmbuf_alloc(struct rte_mempool *mp)\n{\n\tstruct rte_mbuf *m;\n\tif ((m = __rte_mbuf_raw_alloc(mp)) != NULL)\n\t\trte_pktmbuf_reset(m);\n\treturn m;\n}\n\n/**\n * Attach packet mbuf to another packet mbuf.\n *\n * After attachment we refer the mbuf we attached as 'indirect',\n * while mbuf we attached to as 'direct'.\n * Right now, not supported:\n * - attachment for already indirect mbuf (e.g. - mi has to be direct).\n * - mbuf we trying to attach (mi) is used by someone else\n * e.g. it's reference counter is greater then 1.\n *\n * @param mi\n * The indirect packet mbuf.\n * @param m\n * The packet mbuf we're attaching to.\n */\nstatic inline void rte_pktmbuf_attach(struct rte_mbuf *mi, struct rte_mbuf *m)\n{\n\tstruct rte_mbuf *md;\n\n\tRTE_MBUF_ASSERT(RTE_MBUF_DIRECT(mi) &&\n\t rte_mbuf_refcnt_read(mi) == 1);\n\n\t/* if m is not direct, get the mbuf that embeds the data */\n\tif (RTE_MBUF_DIRECT(m))\n\t\tmd = m;\n\telse\n\t\tmd = rte_mbuf_from_indirect(m);\n\n\trte_mbuf_refcnt_update(md, 1);\n\tmi->priv_size = m->priv_size;\n\tmi->buf_physaddr = m->buf_physaddr;\n\tmi->buf_addr = m->buf_addr;\n\tmi->buf_len = m->buf_len;\n\n\tmi->next = m->next;\n\tmi->data_off = m->data_off;\n\tmi->data_len = m->data_len;\n\tmi->port = m->port;\n\tmi->vlan_tci = m->vlan_tci;\n\tmi->vlan_tci_outer = m->vlan_tci_outer;\n\tmi->tx_offload = m->tx_offload;\n\tmi->hash = m->hash;\n\n\tmi->next = NULL;\n\tmi->pkt_len = mi->data_len;\n\tmi->nb_segs = 1;\n\tmi->ol_flags = m->ol_flags | IND_ATTACHED_MBUF;\n\tmi->packet_type = m->packet_type;\n\n\t__rte_mbuf_sanity_check(mi, 1);\n\t__rte_mbuf_sanity_check(m, 0);\n}\n\n/**\n * Detach an indirect packet mbuf.\n *\n * - restore original mbuf address and length values.\n * - reset pktmbuf data and data_len to their default values.\n * All other fields of the given packet mbuf will be left intact.\n *\n * @param m\n * The indirect attached packet mbuf.\n */\nstatic inline void rte_pktmbuf_detach(struct rte_mbuf *m)\n{\n\tstruct rte_mempool *mp = m->pool;\n\tuint32_t mbuf_size, buf_len, priv_size;\n\n\tpriv_size = rte_pktmbuf_priv_size(mp);\n\tmbuf_size = sizeof(struct rte_mbuf) + priv_size;\n\tbuf_len = rte_pktmbuf_data_room_size(mp);\n\n\tm->priv_size = priv_size;\n\tm->buf_addr = (char *)m + mbuf_size;\n\tm->buf_physaddr = rte_mempool_virt2phy(mp, m) + mbuf_size;\n\tm->buf_len = (uint16_t)buf_len;\n\tm->data_off = RTE_MIN(RTE_PKTMBUF_HEADROOM, (uint16_t)m->buf_len);\n\tm->data_len = 0;\n\tm->ol_flags = 0;\n}\n\nstatic inline struct rte_mbuf* __attribute__((always_inline))\n__rte_pktmbuf_prefree_seg(struct rte_mbuf *m)\n{\n\t__rte_mbuf_sanity_check(m, 0);\n\n\tif (likely(rte_mbuf_refcnt_update(m, -1) == 0)) {\n\n\t\t/* if this is an indirect mbuf, then\n\t\t * - detach mbuf\n\t\t * - free attached mbuf segment\n\t\t */\n\t\tif (RTE_MBUF_INDIRECT(m)) {\n\t\t\tstruct rte_mbuf *md = rte_mbuf_from_indirect(m);\n\t\t\trte_pktmbuf_detach(m);\n\t\t\tif (rte_mbuf_refcnt_update(md, -1) == 0)\n\t\t\t\t__rte_mbuf_raw_free(md);\n\t\t}\n\t\treturn m;\n\t}\n\treturn NULL;\n}\n\n/**\n * Free a segment of a packet mbuf into its original mempool.\n *\n * Free an mbuf, without parsing other segments in case of chained\n * buffers.\n *\n * @param m\n * The packet mbuf segment to be freed.\n */\nstatic inline void __attribute__((always_inline))\nrte_pktmbuf_free_seg(struct rte_mbuf *m)\n{\n\tif (likely(NULL != (m = __rte_pktmbuf_prefree_seg(m)))) {\n\t\tm->next = NULL;\n\t\t__rte_mbuf_raw_free(m);\n\t}\n}\n\n/**\n * Free a packet mbuf back into its original mempool.\n *\n * Free an mbuf, and all its segments in case of chained buffers. Each\n * segment is added back into its original mempool.\n *\n * @param m\n * The packet mbuf to be freed.\n */\nstatic inline void rte_pktmbuf_free(struct rte_mbuf *m)\n{\n\tstruct rte_mbuf *m_next;\n\n\t__rte_mbuf_sanity_check(m, 1);\n\n\twhile (m != NULL) {\n\t\tm_next = m->next;\n\t\trte_pktmbuf_free_seg(m);\n\t\tm = m_next;\n\t}\n}\n\n/**\n * Creates a \"clone\" of the given packet mbuf.\n *\n * Walks through all segments of the given packet mbuf, and for each of them:\n * - Creates a new packet mbuf from the given pool.\n * - Attaches newly created mbuf to the segment.\n * Then updates pkt_len and nb_segs of the \"clone\" packet mbuf to match values\n * from the original packet mbuf.\n *\n * @param md\n * The packet mbuf to be cloned.\n * @param mp\n * The mempool from which the \"clone\" mbufs are allocated.\n * @return\n * - The pointer to the new \"clone\" mbuf on success.\n * - NULL if allocation fails.\n */\nstatic inline struct rte_mbuf *rte_pktmbuf_clone(struct rte_mbuf *md,\n\t\tstruct rte_mempool *mp)\n{\n\tstruct rte_mbuf *mc, *mi, **prev;\n\tuint32_t pktlen;\n\tuint8_t nseg;\n\n\tif (unlikely ((mc = rte_pktmbuf_alloc(mp)) == NULL))\n\t\treturn NULL;\n\n\tmi = mc;\n\tprev = &mi->next;\n\tpktlen = md->pkt_len;\n\tnseg = 0;\n\n\tdo {\n\t\tnseg++;\n\t\trte_pktmbuf_attach(mi, md);\n\t\t*prev = mi;\n\t\tprev = &mi->next;\n\t} while ((md = md->next) != NULL &&\n\t (mi = rte_pktmbuf_alloc(mp)) != NULL);\n\n\t*prev = NULL;\n\tmc->nb_segs = nseg;\n\tmc->pkt_len = pktlen;\n\n\t/* Allocation of new indirect segment failed */\n\tif (unlikely (mi == NULL)) {\n\t\trte_pktmbuf_free(mc);\n\t\treturn NULL;\n\t}\n\n\t__rte_mbuf_sanity_check(mc, 1);\n\treturn mc;\n}\n\n/**\n * Adds given value to the refcnt of all packet mbuf segments.\n *\n * Walks through all segments of given packet mbuf and for each of them\n * invokes rte_mbuf_refcnt_update().\n *\n * @param m\n * The packet mbuf whose refcnt to be updated.\n * @param v\n * The value to add to the mbuf's segments refcnt.\n */\nstatic inline void rte_pktmbuf_refcnt_update(struct rte_mbuf *m, int16_t v)\n{\n\t__rte_mbuf_sanity_check(m, 1);\n\n\tdo {\n\t\trte_mbuf_refcnt_update(m, v);\n\t} while ((m = m->next) != NULL);\n}\n\n/**\n * Get the headroom in a packet mbuf.\n *\n * @param m\n * The packet mbuf.\n * @return\n * The length of the headroom.\n */\nstatic inline uint16_t rte_pktmbuf_headroom(const struct rte_mbuf *m)\n{\n\t__rte_mbuf_sanity_check(m, 1);\n\treturn m->data_off;\n}\n\n/**\n * Get the tailroom of a packet mbuf.\n *\n * @param m\n * The packet mbuf.\n * @return\n * The length of the tailroom.\n */\nstatic inline uint16_t rte_pktmbuf_tailroom(const struct rte_mbuf *m)\n{\n\t__rte_mbuf_sanity_check(m, 1);\n\treturn (uint16_t)(m->buf_len - rte_pktmbuf_headroom(m) -\n\t\t\t m->data_len);\n}\n\n/**\n * Get the last segment of the packet.\n *\n * @param m\n * The packet mbuf.\n * @return\n * The last segment of the given mbuf.\n */\nstatic inline struct rte_mbuf *rte_pktmbuf_lastseg(struct rte_mbuf *m)\n{\n\tstruct rte_mbuf *m2 = (struct rte_mbuf *)m;\n\n\t__rte_mbuf_sanity_check(m, 1);\n\twhile (m2->next != NULL)\n\t\tm2 = m2->next;\n\treturn m2;\n}\n\n/**\n * A macro that points to an offset into the data in the mbuf.\n *\n * The returned pointer is cast to type t. Before using this\n * function, the user must ensure that the first segment is large\n * enough to accommodate its data.\n *\n * @param m\n * The packet mbuf.\n * @param o\n * The offset into the mbuf data.\n * @param t\n * The type to cast the result into.\n */\n#define rte_pktmbuf_mtod_offset(m, t, o)\t\\\n\t((t)((char *)(m)->buf_addr + (m)->data_off + (o)))\n\n/**\n * A macro that points to the start of the data in the mbuf.\n *\n * The returned pointer is cast to type t. Before using this\n * function, the user must ensure that the first segment is large\n * enough to accommodate its data.\n *\n * @param m\n * The packet mbuf.\n * @param t\n * The type to cast the result into.\n */\n#define rte_pktmbuf_mtod(m, t) rte_pktmbuf_mtod_offset(m, t, 0)\n\n/**\n * A macro that returns the length of the packet.\n *\n * The value can be read or assigned.\n *\n * @param m\n * The packet mbuf.\n */\n#define rte_pktmbuf_pkt_len(m) ((m)->pkt_len)\n\n/**\n * A macro that returns the length of the segment.\n *\n * The value can be read or assigned.\n *\n * @param m\n * The packet mbuf.\n */\n#define rte_pktmbuf_data_len(m) ((m)->data_len)\n\n/**\n * Prepend len bytes to an mbuf data area.\n *\n * Returns a pointer to the new\n * data start address. If there is not enough headroom in the first\n * segment, the function will return NULL, without modifying the mbuf.\n *\n * @param m\n * The pkt mbuf.\n * @param len\n * The amount of data to prepend (in bytes).\n * @return\n * A pointer to the start of the newly prepended data, or\n * NULL if there is not enough headroom space in the first segment\n */\nstatic inline char *rte_pktmbuf_prepend(struct rte_mbuf *m,\n\t\t\t\t\tuint16_t len)\n{\n\t__rte_mbuf_sanity_check(m, 1);\n\n\tif (unlikely(len > rte_pktmbuf_headroom(m)))\n\t\treturn NULL;\n\n\tm->data_off -= len;\n\tm->data_len = (uint16_t)(m->data_len + len);\n\tm->pkt_len = (m->pkt_len + len);\n\n\treturn (char *)m->buf_addr + m->data_off;\n}\n\n/**\n * Append len bytes to an mbuf.\n *\n * Append len bytes to an mbuf and return a pointer to the start address\n * of the added data. If there is not enough tailroom in the last\n * segment, the function will return NULL, without modifying the mbuf.\n *\n * @param m\n * The packet mbuf.\n * @param len\n * The amount of data to append (in bytes).\n * @return\n * A pointer to the start of the newly appended data, or\n * NULL if there is not enough tailroom space in the last segment\n */\nstatic inline char *rte_pktmbuf_append(struct rte_mbuf *m, uint16_t len)\n{\n\tvoid *tail;\n\tstruct rte_mbuf *m_last;\n\n\t__rte_mbuf_sanity_check(m, 1);\n\n\tm_last = rte_pktmbuf_lastseg(m);\n\tif (unlikely(len > rte_pktmbuf_tailroom(m_last)))\n\t\treturn NULL;\n\n\ttail = (char *)m_last->buf_addr + m_last->data_off + m_last->data_len;\n\tm_last->data_len = (uint16_t)(m_last->data_len + len);\n\tm->pkt_len = (m->pkt_len + len);\n\treturn (char*) tail;\n}\n\n/**\n * Remove len bytes at the beginning of an mbuf.\n *\n * Returns a pointer to the start address of the new data area. If the\n * length is greater than the length of the first segment, then the\n * function will fail and return NULL, without modifying the mbuf.\n *\n * @param m\n * The packet mbuf.\n * @param len\n * The amount of data to remove (in bytes).\n * @return\n * A pointer to the new start of the data.\n */\nstatic inline char *rte_pktmbuf_adj(struct rte_mbuf *m, uint16_t len)\n{\n\t__rte_mbuf_sanity_check(m, 1);\n\n\tif (unlikely(len > m->data_len))\n\t\treturn NULL;\n\n\tm->data_len = (uint16_t)(m->data_len - len);\n\tm->data_off += len;\n\tm->pkt_len = (m->pkt_len - len);\n\treturn (char *)m->buf_addr + m->data_off;\n}\n\n/**\n * Remove len bytes of data at the end of the mbuf.\n *\n * If the length is greater than the length of the last segment, the\n * function will fail and return -1 without modifying the mbuf.\n *\n * @param m\n * The packet mbuf.\n * @param len\n * The amount of data to remove (in bytes).\n * @return\n * - 0: On success.\n * - -1: On error.\n */\nstatic inline int rte_pktmbuf_trim(struct rte_mbuf *m, uint16_t len)\n{\n\tstruct rte_mbuf *m_last;\n\n\t__rte_mbuf_sanity_check(m, 1);\n\n\tm_last = rte_pktmbuf_lastseg(m);\n\tif (unlikely(len > m_last->data_len))\n\t\treturn -1;\n\n\tm_last->data_len = (uint16_t)(m_last->data_len - len);\n\tm->pkt_len = (m->pkt_len - len);\n\treturn 0;\n}\n\n/**\n * Test if mbuf data is contiguous.\n *\n * @param m\n * The packet mbuf.\n * @return\n * - 1, if all data is contiguous (one segment).\n * - 0, if there is several segments.\n */\nstatic inline int rte_pktmbuf_is_contiguous(const struct rte_mbuf *m)\n{\n\t__rte_mbuf_sanity_check(m, 1);\n\treturn !!(m->nb_segs == 1);\n}\n\n/**\n * Dump an mbuf structure to the console.\n *\n * Dump all fields for the given packet mbuf and all its associated\n * segments (in the case of a chained buffer).\n *\n * @param f\n * A pointer to a file for output\n * @param m\n * The packet mbuf.\n * @param dump_len\n * If dump_len != 0, also dump the \"dump_len\" first data bytes of\n * the packet.\n */\nvoid rte_pktmbuf_dump(FILE *f, const struct rte_mbuf *m, unsigned dump_len);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_MBUF_H_ */\n" }, { "path": "lib/librte_mempool/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_mempool.a\n\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3\n\nEXPORT_MAP := rte_mempool_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_MEMPOOL) += rte_mempool.c\nifeq ($(CONFIG_RTE_LIBRTE_XEN_DOM0),y)\nSRCS-$(CONFIG_RTE_LIBRTE_MEMPOOL) += rte_dom0_mempool.c\nendif\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_MEMPOOL)-include := rte_mempool.h\n\nDEPDIRS-$(CONFIG_RTE_LIBRTE_MEMPOOL) += lib/librte_eal lib/librte_ring\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_mempool/rte_dom0_mempool.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_mempool.h\"\n\nstatic void\nget_phys_map(void *va, phys_addr_t pa[], uint32_t pg_num,\n\tuint32_t pg_sz, uint32_t memseg_id)\n{\n\tuint32_t i;\n\tuint64_t virt_addr, mfn_id;\n\tstruct rte_mem_config *mcfg;\n\tuint32_t page_size = getpagesize();\n\n\t/* get pointer to global configuration */\n\tmcfg = rte_eal_get_configuration()->mem_config;\n\tvirt_addr = (uintptr_t) mcfg->memseg[memseg_id].addr;\n\n\tfor (i = 0; i != pg_num; i++) {\n\t\tmfn_id = ((uintptr_t)va + i * pg_sz - virt_addr) / RTE_PGSIZE_2M;\n\t\tpa[i] = mcfg->memseg[memseg_id].mfn[mfn_id] * page_size;\n\t}\n}\n\n/* create the mempool for supporting Dom0 */\nstruct rte_mempool *\nrte_dom0_mempool_create(const char *name, unsigned elt_num, unsigned elt_size,\n\tunsigned cache_size, unsigned private_data_size,\n\trte_mempool_ctor_t *mp_init, void *mp_init_arg,\n\trte_mempool_obj_ctor_t *obj_init, void *obj_init_arg,\n\tint socket_id, unsigned flags)\n{\n\tstruct rte_mempool *mp = NULL;\n\tphys_addr_t *pa;\n\tchar *va;\n\tsize_t sz;\n\tuint32_t pg_num, pg_shift, pg_sz, total_size;\n\tconst struct rte_memzone *mz;\n\tchar mz_name[RTE_MEMZONE_NAMESIZE];\n\tint mz_flags = RTE_MEMZONE_1GB|RTE_MEMZONE_SIZE_HINT_ONLY;\n\n\tpg_sz = RTE_PGSIZE_2M;\n\n\tpg_shift = rte_bsf32(pg_sz);\n\ttotal_size = rte_mempool_calc_obj_size(elt_size, flags, NULL);\n\n\t/* calc max memory size and max number of pages needed. */\n\tsz = rte_mempool_xmem_size(elt_num, total_size, pg_shift) +\n\t\tRTE_PGSIZE_2M;\n\tpg_num = sz >> pg_shift;\n\n\t/* extract physical mappings of the allocated memory. */\n\tpa = calloc(pg_num, sizeof (*pa));\n\tif (pa == NULL)\n\t\treturn mp;\n\n\tsnprintf(mz_name, sizeof(mz_name), RTE_MEMPOOL_OBJ_NAME, name);\n\tmz = rte_memzone_reserve(mz_name, sz, socket_id, mz_flags);\n\tif (mz == NULL) {\n\t\tfree(pa);\n\t\treturn mp;\n\t}\n\n\tva = (char *)RTE_ALIGN_CEIL((uintptr_t)mz->addr, RTE_PGSIZE_2M);\n\t/* extract physical mappings of the allocated memory. */\n\tget_phys_map(va, pa, pg_num, pg_sz, mz->memseg_id);\n\n\tmp = rte_mempool_xmem_create(name, elt_num, elt_size,\n\t\tcache_size, private_data_size,\n\t\tmp_init, mp_init_arg,\n\t\tobj_init, obj_init_arg,\n\t\tsocket_id, flags, va, pa, pg_num, pg_shift);\n\n\tfree(pa);\n\n\treturn mp;\n}\n" }, { "path": "lib/librte_mempool/rte_mempool.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_mempool.h\"\n\nTAILQ_HEAD(rte_mempool_list, rte_tailq_entry);\n\nstatic struct rte_tailq_elem rte_mempool_tailq = {\n\t.name = \"RTE_MEMPOOL\",\n};\nEAL_REGISTER_TAILQ(rte_mempool_tailq)\n\n#define CACHE_FLUSHTHRESH_MULTIPLIER 1.5\n#define CALC_CACHE_FLUSHTHRESH(c)\t\\\n\t((typeof(c))((c) * CACHE_FLUSHTHRESH_MULTIPLIER))\n\n/*\n * return the greatest common divisor between a and b (fast algorithm)\n *\n */\nstatic unsigned get_gcd(unsigned a, unsigned b)\n{\n\tunsigned c;\n\n\tif (0 == a)\n\t\treturn b;\n\tif (0 == b)\n\t\treturn a;\n\n\tif (a < b) {\n\t\tc = a;\n\t\ta = b;\n\t\tb = c;\n\t}\n\n\twhile (b != 0) {\n\t\tc = a % b;\n\t\ta = b;\n\t\tb = c;\n\t}\n\n\treturn a;\n}\n\n/*\n * Depending on memory configuration, objects addresses are spread\n * between channels and ranks in RAM: the pool allocator will add\n * padding between objects. This function return the new size of the\n * object.\n */\nstatic unsigned optimize_object_size(unsigned obj_size)\n{\n\tunsigned nrank, nchan;\n\tunsigned new_obj_size;\n\n\t/* get number of channels */\n\tnchan = rte_memory_get_nchannel();\n\tif (nchan == 0)\n\t\tnchan = 1;\n\n\tnrank = rte_memory_get_nrank();\n\tif (nrank == 0)\n\t\tnrank = 1;\n\n\t/* process new object size */\n\tnew_obj_size = (obj_size + RTE_MEMPOOL_ALIGN_MASK) / RTE_MEMPOOL_ALIGN;\n\twhile (get_gcd(new_obj_size, nrank * nchan) != 1)\n\t\tnew_obj_size++;\n\treturn new_obj_size * RTE_MEMPOOL_ALIGN;\n}\n\nstatic void\nmempool_add_elem(struct rte_mempool *mp, void *obj, uint32_t obj_idx,\n\trte_mempool_obj_ctor_t *obj_init, void *obj_init_arg)\n{\n\tstruct rte_mempool_objhdr *hdr;\n\tstruct rte_mempool_objtlr *tlr __rte_unused;\n\n\tobj = (char *)obj + mp->header_size;\n\n\t/* set mempool ptr in header */\n\thdr = RTE_PTR_SUB(obj, sizeof(*hdr));\n\thdr->mp = mp;\n\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n\thdr->cookie = RTE_MEMPOOL_HEADER_COOKIE2;\n\ttlr = __mempool_get_trailer(obj);\n\ttlr->cookie = RTE_MEMPOOL_TRAILER_COOKIE;\n#endif\n\t/* call the initializer */\n\tif (obj_init)\n\t\tobj_init(mp, obj_init_arg, obj, obj_idx);\n\n\t/* enqueue in ring */\n\trte_ring_sp_enqueue(mp->ring, obj);\n}\n\nuint32_t\nrte_mempool_obj_iter(void *vaddr, uint32_t elt_num, size_t elt_sz, size_t align,\n\tconst phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift,\n\trte_mempool_obj_iter_t obj_iter, void *obj_iter_arg)\n{\n\tuint32_t i, j, k;\n\tuint32_t pgn, pgf;\n\tuintptr_t end, start, va;\n\tuintptr_t pg_sz;\n\n\tpg_sz = (uintptr_t)1 << pg_shift;\n\tva = (uintptr_t)vaddr;\n\n\ti = 0;\n\tj = 0;\n\n\twhile (i != elt_num && j != pg_num) {\n\n\t\tstart = RTE_ALIGN_CEIL(va, align);\n\t\tend = start + elt_sz;\n\n\t\t/* index of the first page for the next element. */\n\t\tpgf = (end >> pg_shift) - (start >> pg_shift);\n\n\t\t/* index of the last page for the current element. */\n\t\tpgn = ((end - 1) >> pg_shift) - (start >> pg_shift);\n\t\tpgn += j;\n\n\t\t/* do we have enough space left for the element. */\n\t\tif (pgn >= pg_num)\n\t\t\tbreak;\n\n\t\tfor (k = j;\n\t\t\t\tk != pgn &&\n\t\t\t\tpaddr[k] + pg_sz == paddr[k + 1];\n\t\t\t\tk++)\n\t\t\t;\n\n\t\t/*\n\t\t * if next pgn chunks of memory physically continuous,\n\t\t * use it to create next element.\n\t\t * otherwise, just skip that chunk unused.\n\t\t */\n\t\tif (k == pgn) {\n\t\t\tif (obj_iter != NULL)\n\t\t\t\tobj_iter(obj_iter_arg, (void *)start,\n\t\t\t\t\t(void *)end, i);\n\t\t\tva = end;\n\t\t\tj += pgf;\n\t\t\ti++;\n\t\t} else {\n\t\t\tva = RTE_ALIGN_CEIL((va + 1), pg_sz);\n\t\t\tj++;\n\t\t}\n\t}\n\n\treturn i;\n}\n\n/*\n * Populate mempool with the objects.\n */\n\nstruct mempool_populate_arg {\n\tstruct rte_mempool *mp;\n\trte_mempool_obj_ctor_t *obj_init;\n\tvoid *obj_init_arg;\n};\n\nstatic void\nmempool_obj_populate(void *arg, void *start, void *end, uint32_t idx)\n{\n\tstruct mempool_populate_arg *pa = arg;\n\n\tmempool_add_elem(pa->mp, start, idx, pa->obj_init, pa->obj_init_arg);\n\tpa->mp->elt_va_end = (uintptr_t)end;\n}\n\nstatic void\nmempool_populate(struct rte_mempool *mp, size_t num, size_t align,\n\trte_mempool_obj_ctor_t *obj_init, void *obj_init_arg)\n{\n\tuint32_t elt_sz;\n\tstruct mempool_populate_arg arg;\n\n\telt_sz = mp->elt_size + mp->header_size + mp->trailer_size;\n\targ.mp = mp;\n\targ.obj_init = obj_init;\n\targ.obj_init_arg = obj_init_arg;\n\n\tmp->size = rte_mempool_obj_iter((void *)mp->elt_va_start,\n\t\tnum, elt_sz, align,\n\t\tmp->elt_pa, mp->pg_num, mp->pg_shift,\n\t\tmempool_obj_populate, &arg);\n}\n\nuint32_t\nrte_mempool_calc_obj_size(uint32_t elt_size, uint32_t flags,\n\tstruct rte_mempool_objsz *sz)\n{\n\tstruct rte_mempool_objsz lsz;\n\n\tsz = (sz != NULL) ? sz : &lsz;\n\n\t/*\n\t * In header, we have at least the pointer to the pool, and\n\t * optionaly a 64 bits cookie.\n\t */\n\tsz->header_size = 0;\n\tsz->header_size += sizeof(struct rte_mempool *); /* ptr to pool */\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n\tsz->header_size += sizeof(uint64_t); /* cookie */\n#endif\n\tif ((flags & MEMPOOL_F_NO_CACHE_ALIGN) == 0)\n\t\tsz->header_size = RTE_ALIGN_CEIL(sz->header_size,\n\t\t\tRTE_MEMPOOL_ALIGN);\n\n\t/* trailer contains the cookie in debug mode */\n\tsz->trailer_size = 0;\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n\tsz->trailer_size += sizeof(uint64_t); /* cookie */\n#endif\n\t/* element size is 8 bytes-aligned at least */\n\tsz->elt_size = RTE_ALIGN_CEIL(elt_size, sizeof(uint64_t));\n\n\t/* expand trailer to next cache line */\n\tif ((flags & MEMPOOL_F_NO_CACHE_ALIGN) == 0) {\n\t\tsz->total_size = sz->header_size + sz->elt_size +\n\t\t\tsz->trailer_size;\n\t\tsz->trailer_size += ((RTE_MEMPOOL_ALIGN -\n\t\t\t\t (sz->total_size & RTE_MEMPOOL_ALIGN_MASK)) &\n\t\t\t\t RTE_MEMPOOL_ALIGN_MASK);\n\t}\n\n\t/*\n\t * increase trailer to add padding between objects in order to\n\t * spread them across memory channels/ranks\n\t */\n\tif ((flags & MEMPOOL_F_NO_SPREAD) == 0) {\n\t\tunsigned new_size;\n\t\tnew_size = optimize_object_size(sz->header_size + sz->elt_size +\n\t\t\tsz->trailer_size);\n\t\tsz->trailer_size = new_size - sz->header_size - sz->elt_size;\n\t}\n\n\tif (! rte_eal_has_hugepages()) {\n\t\t/*\n\t\t * compute trailer size so that pool elements fit exactly in\n\t\t * a standard page\n\t\t */\n\t\tint page_size = getpagesize();\n\t\tint new_size = page_size - sz->header_size - sz->elt_size;\n\t\tif (new_size < 0 || (unsigned int)new_size < sz->trailer_size) {\n\t\t\tprintf(\"When hugepages are disabled, pool objects \"\n\t\t\t \"can't exceed PAGE_SIZE: %d + %d + %d > %d\\n\",\n\t\t\t sz->header_size, sz->elt_size, sz->trailer_size,\n\t\t\t page_size);\n\t\t\treturn 0;\n\t\t}\n\t\tsz->trailer_size = new_size;\n\t}\n\n\t/* this is the size of an object, including header and trailer */\n\tsz->total_size = sz->header_size + sz->elt_size + sz->trailer_size;\n\n\treturn sz->total_size;\n}\n\n\n/*\n * Calculate maximum amount of memory required to store given number of objects.\n */\nsize_t\nrte_mempool_xmem_size(uint32_t elt_num, size_t elt_sz, uint32_t pg_shift)\n{\n\tsize_t n, pg_num, pg_sz, sz;\n\n\tpg_sz = (size_t)1 << pg_shift;\n\n\tif ((n = pg_sz / elt_sz) > 0) {\n\t\tpg_num = (elt_num + n - 1) / n;\n\t\tsz = pg_num << pg_shift;\n\t} else {\n\t\tsz = RTE_ALIGN_CEIL(elt_sz, pg_sz) * elt_num;\n\t}\n\n\treturn sz;\n}\n\n/*\n * Calculate how much memory would be actually required with the\n * given memory footprint to store required number of elements.\n */\nstatic void\nmempool_lelem_iter(void *arg, __rte_unused void *start, void *end,\n\t__rte_unused uint32_t idx)\n{\n\t*(uintptr_t *)arg = (uintptr_t)end;\n}\n\nssize_t\nrte_mempool_xmem_usage(void *vaddr, uint32_t elt_num, size_t elt_sz,\n\tconst phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift)\n{\n\tuint32_t n;\n\tuintptr_t va, uv;\n\tsize_t pg_sz, usz;\n\n\tpg_sz = (size_t)1 << pg_shift;\n\tva = (uintptr_t)vaddr;\n\tuv = va;\n\n\tif ((n = rte_mempool_obj_iter(vaddr, elt_num, elt_sz, 1,\n\t\t\tpaddr, pg_num, pg_shift, mempool_lelem_iter,\n\t\t\t&uv)) != elt_num) {\n\t\treturn -(ssize_t)n;\n\t}\n\n\tuv = RTE_ALIGN_CEIL(uv, pg_sz);\n\tusz = uv - va;\n\treturn usz;\n}\n\n/* create the mempool */\nstruct rte_mempool *\nrte_mempool_create(const char *name, unsigned n, unsigned elt_size,\n\t\t unsigned cache_size, unsigned private_data_size,\n\t\t rte_mempool_ctor_t *mp_init, void *mp_init_arg,\n\t\t rte_mempool_obj_ctor_t *obj_init, void *obj_init_arg,\n\t\t int socket_id, unsigned flags)\n{\n#ifdef RTE_LIBRTE_XEN_DOM0\n\treturn rte_dom0_mempool_create(name, n, elt_size,\n\t\tcache_size, private_data_size,\n\t\tmp_init, mp_init_arg,\n\t\tobj_init, obj_init_arg,\n\t\tsocket_id, flags);\n#else\n\treturn rte_mempool_xmem_create(name, n, elt_size,\n\t\tcache_size, private_data_size,\n\t\tmp_init, mp_init_arg,\n\t\tobj_init, obj_init_arg,\n\t\tsocket_id, flags,\n\t\tNULL, NULL, MEMPOOL_PG_NUM_DEFAULT, MEMPOOL_PG_SHIFT_MAX);\n#endif\n}\n\n/*\n * Create the mempool over already allocated chunk of memory.\n * That external memory buffer can consists of physically disjoint pages.\n * Setting vaddr to NULL, makes mempool to fallback to original behaviour\n * and allocate space for mempool and it's elements as one big chunk of\n * physically continuos memory.\n * */\nstruct rte_mempool *\nrte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size,\n\t\tunsigned cache_size, unsigned private_data_size,\n\t\trte_mempool_ctor_t *mp_init, void *mp_init_arg,\n\t\trte_mempool_obj_ctor_t *obj_init, void *obj_init_arg,\n\t\tint socket_id, unsigned flags, void *vaddr,\n\t\tconst phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift)\n{\n\tchar mz_name[RTE_MEMZONE_NAMESIZE];\n\tchar rg_name[RTE_RING_NAMESIZE];\n\tstruct rte_mempool_list *mempool_list;\n\tstruct rte_mempool *mp = NULL;\n\tstruct rte_tailq_entry *te;\n\tstruct rte_ring *r;\n\tconst struct rte_memzone *mz;\n\tsize_t mempool_size;\n\tint mz_flags = RTE_MEMZONE_1GB|RTE_MEMZONE_SIZE_HINT_ONLY;\n\tint rg_flags = 0;\n\tvoid *obj;\n\tstruct rte_mempool_objsz objsz;\n\tvoid *startaddr;\n\tint page_size = getpagesize();\n\n\t/* compilation-time checks */\n\tRTE_BUILD_BUG_ON((sizeof(struct rte_mempool) &\n\t\t\t RTE_CACHE_LINE_MASK) != 0);\n#if RTE_MEMPOOL_CACHE_MAX_SIZE > 0\n\tRTE_BUILD_BUG_ON((sizeof(struct rte_mempool_cache) &\n\t\t\t RTE_CACHE_LINE_MASK) != 0);\n\tRTE_BUILD_BUG_ON((offsetof(struct rte_mempool, local_cache) &\n\t\t\t RTE_CACHE_LINE_MASK) != 0);\n#endif\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n\tRTE_BUILD_BUG_ON((sizeof(struct rte_mempool_debug_stats) &\n\t\t\t RTE_CACHE_LINE_MASK) != 0);\n\tRTE_BUILD_BUG_ON((offsetof(struct rte_mempool, stats) &\n\t\t\t RTE_CACHE_LINE_MASK) != 0);\n#endif\n\n\tmempool_list = RTE_TAILQ_CAST(rte_mempool_tailq.head, rte_mempool_list);\n\n\t/* asked cache too big */\n\tif (cache_size > RTE_MEMPOOL_CACHE_MAX_SIZE ||\n\t CALC_CACHE_FLUSHTHRESH(cache_size) > n) {\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\t/* check that we have both VA and PA */\n\tif (vaddr != NULL && paddr == NULL) {\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\t/* Check that pg_num and pg_shift parameters are valid. */\n\tif (pg_num < RTE_DIM(mp->elt_pa) || pg_shift > MEMPOOL_PG_SHIFT_MAX) {\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\t/* \"no cache align\" imply \"no spread\" */\n\tif (flags & MEMPOOL_F_NO_CACHE_ALIGN)\n\t\tflags |= MEMPOOL_F_NO_SPREAD;\n\n\t/* ring flags */\n\tif (flags & MEMPOOL_F_SP_PUT)\n\t\trg_flags |= RING_F_SP_ENQ;\n\tif (flags & MEMPOOL_F_SC_GET)\n\t\trg_flags |= RING_F_SC_DEQ;\n\n\t/* calculate mempool object sizes. */\n\tif (!rte_mempool_calc_obj_size(elt_size, flags, &objsz)) {\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\trte_rwlock_write_lock(RTE_EAL_MEMPOOL_RWLOCK);\n\n\t/* allocate the ring that will be used to store objects */\n\t/* Ring functions will return appropriate errors if we are\n\t * running as a secondary process etc., so no checks made\n\t * in this function for that condition */\n\tsnprintf(rg_name, sizeof(rg_name), RTE_MEMPOOL_MZ_FORMAT, name);\n\tr = rte_ring_create(rg_name, rte_align32pow2(n+1), socket_id, rg_flags);\n\tif (r == NULL)\n\t\tgoto exit;\n\n\t/*\n\t * reserve a memory zone for this mempool: private data is\n\t * cache-aligned\n\t */\n\tprivate_data_size = (private_data_size +\n\t\t\t RTE_MEMPOOL_ALIGN_MASK) & (~RTE_MEMPOOL_ALIGN_MASK);\n\n\tif (! rte_eal_has_hugepages()) {\n\t\t/*\n\t\t * expand private data size to a whole page, so that the\n\t\t * first pool element will start on a new standard page\n\t\t */\n\t\tint head = sizeof(struct rte_mempool);\n\t\tint new_size = (private_data_size + head) % page_size;\n\t\tif (new_size) {\n\t\t\tprivate_data_size += page_size - new_size;\n\t\t}\n\t}\n\n\t/* try to allocate tailq entry */\n\tte = rte_zmalloc(\"MEMPOOL_TAILQ_ENTRY\", sizeof(*te), 0);\n\tif (te == NULL) {\n\t\tRTE_LOG(ERR, MEMPOOL, \"Cannot allocate tailq entry!\\n\");\n\t\tgoto exit;\n\t}\n\n\t/*\n\t * If user provided an external memory buffer, then use it to\n\t * store mempool objects. Otherwise reserve a memzone that is large\n\t * enough to hold mempool header and metadata plus mempool objects.\n\t */\n\tmempool_size = MEMPOOL_HEADER_SIZE(mp, pg_num) + private_data_size;\n\tmempool_size = RTE_ALIGN_CEIL(mempool_size, RTE_MEMPOOL_ALIGN);\n\tif (vaddr == NULL)\n\t\tmempool_size += (size_t)objsz.total_size * n;\n\n\tif (! rte_eal_has_hugepages()) {\n\t\t/*\n\t\t * we want the memory pool to start on a page boundary,\n\t\t * because pool elements crossing page boundaries would\n\t\t * result in discontiguous physical addresses\n\t\t */\n\t\tmempool_size += page_size;\n\t}\n\n\tsnprintf(mz_name, sizeof(mz_name), RTE_MEMPOOL_MZ_FORMAT, name);\n\n\tmz = rte_memzone_reserve(mz_name, mempool_size, socket_id, mz_flags);\n\n\t/*\n\t * no more memory: in this case we loose previously reserved\n\t * space for the ring as we cannot free it\n\t */\n\tif (mz == NULL) {\n\t\trte_free(te);\n\t\tgoto exit;\n\t}\n\n\tif (rte_eal_has_hugepages()) {\n\t\tstartaddr = (void*)mz->addr;\n\t} else {\n\t\t/* align memory pool start address on a page boundary */\n\t\tunsigned long addr = (unsigned long)mz->addr;\n\t\tif (addr & (page_size - 1)) {\n\t\t\taddr += page_size;\n\t\t\taddr &= ~(page_size - 1);\n\t\t}\n\t\tstartaddr = (void*)addr;\n\t}\n\n\t/* init the mempool structure */\n\tmp = startaddr;\n\tmemset(mp, 0, sizeof(*mp));\n\tsnprintf(mp->name, sizeof(mp->name), \"%s\", name);\n\tmp->phys_addr = mz->phys_addr;\n\tmp->ring = r;\n\tmp->size = n;\n\tmp->flags = flags;\n\tmp->elt_size = objsz.elt_size;\n\tmp->header_size = objsz.header_size;\n\tmp->trailer_size = objsz.trailer_size;\n\tmp->cache_size = cache_size;\n\tmp->cache_flushthresh = CALC_CACHE_FLUSHTHRESH(cache_size);\n\tmp->private_data_size = private_data_size;\n\n\t/* calculate address of the first element for continuous mempool. */\n\tobj = (char *)mp + MEMPOOL_HEADER_SIZE(mp, pg_num) +\n\t\tprivate_data_size;\n\tobj = RTE_PTR_ALIGN_CEIL(obj, RTE_MEMPOOL_ALIGN);\n\n\t/* populate address translation fields. */\n\tmp->pg_num = pg_num;\n\tmp->pg_shift = pg_shift;\n\tmp->pg_mask = RTE_LEN2MASK(mp->pg_shift, typeof(mp->pg_mask));\n\n\t/* mempool elements allocated together with mempool */\n\tif (vaddr == NULL) {\n\t\tmp->elt_va_start = (uintptr_t)obj;\n\t\tmp->elt_pa[0] = mp->phys_addr +\n\t\t\t(mp->elt_va_start - (uintptr_t)mp);\n\n\t/* mempool elements in a separate chunk of memory. */\n\t} else {\n\t\tmp->elt_va_start = (uintptr_t)vaddr;\n\t\tmemcpy(mp->elt_pa, paddr, sizeof (mp->elt_pa[0]) * pg_num);\n\t}\n\n\tmp->elt_va_end = mp->elt_va_start;\n\n\t/* call the initializer */\n\tif (mp_init)\n\t\tmp_init(mp, mp_init_arg);\n\n\tmempool_populate(mp, n, 1, obj_init, obj_init_arg);\n\n\tte->data = (void *) mp;\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\tTAILQ_INSERT_TAIL(mempool_list, te, next);\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\nexit:\n\trte_rwlock_write_unlock(RTE_EAL_MEMPOOL_RWLOCK);\n\n\treturn mp;\n}\n\n/* Return the number of entries in the mempool */\nunsigned\nrte_mempool_count(const struct rte_mempool *mp)\n{\n\tunsigned count;\n\n\tcount = rte_ring_count(mp->ring);\n\n#if RTE_MEMPOOL_CACHE_MAX_SIZE > 0\n\t{\n\t\tunsigned lcore_id;\n\t\tif (mp->cache_size == 0)\n\t\t\treturn count;\n\n\t\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++)\n\t\t\tcount += mp->local_cache[lcore_id].len;\n\t}\n#endif\n\n\t/*\n\t * due to race condition (access to len is not locked), the\n\t * total can be greater than size... so fix the result\n\t */\n\tif (count > mp->size)\n\t\treturn mp->size;\n\treturn count;\n}\n\n/* dump the cache status */\nstatic unsigned\nrte_mempool_dump_cache(FILE *f, const struct rte_mempool *mp)\n{\n#if RTE_MEMPOOL_CACHE_MAX_SIZE > 0\n\tunsigned lcore_id;\n\tunsigned count = 0;\n\tunsigned cache_count;\n\n\tfprintf(f, \" cache infos:\\n\");\n\tfprintf(f, \" cache_size=%\"PRIu32\"\\n\", mp->cache_size);\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tcache_count = mp->local_cache[lcore_id].len;\n\t\tfprintf(f, \" cache_count[%u]=%u\\n\", lcore_id, cache_count);\n\t\tcount += cache_count;\n\t}\n\tfprintf(f, \" total_cache_count=%u\\n\", count);\n\treturn count;\n#else\n\tRTE_SET_USED(mp);\n\tfprintf(f, \" cache disabled\\n\");\n\treturn 0;\n#endif\n}\n\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n/* check cookies before and after objects */\n#ifndef __INTEL_COMPILER\n#pragma GCC diagnostic ignored \"-Wcast-qual\"\n#endif\n\nstruct mempool_audit_arg {\n\tconst struct rte_mempool *mp;\n\tuintptr_t obj_end;\n\tuint32_t obj_num;\n};\n\nstatic void\nmempool_obj_audit(void *arg, void *start, void *end, uint32_t idx)\n{\n\tstruct mempool_audit_arg *pa = arg;\n\tvoid *obj;\n\n\tobj = (char *)start + pa->mp->header_size;\n\tpa->obj_end = (uintptr_t)end;\n\tpa->obj_num = idx + 1;\n\t__mempool_check_cookies(pa->mp, &obj, 1, 2);\n}\n\nstatic void\nmempool_audit_cookies(const struct rte_mempool *mp)\n{\n\tuint32_t elt_sz, num;\n\tstruct mempool_audit_arg arg;\n\n\telt_sz = mp->elt_size + mp->header_size + mp->trailer_size;\n\n\targ.mp = mp;\n\targ.obj_end = mp->elt_va_start;\n\targ.obj_num = 0;\n\n\tnum = rte_mempool_obj_iter((void *)mp->elt_va_start,\n\t\tmp->size, elt_sz, 1,\n\t\tmp->elt_pa, mp->pg_num, mp->pg_shift,\n\t\tmempool_obj_audit, &arg);\n\n\tif (num != mp->size) {\n\t\t\trte_panic(\"rte_mempool_obj_iter(mempool=%p, size=%u) \"\n\t\t\t\"iterated only over %u elements\\n\",\n\t\t\tmp, mp->size, num);\n\t} else if (arg.obj_end != mp->elt_va_end || arg.obj_num != mp->size) {\n\t\t\trte_panic(\"rte_mempool_obj_iter(mempool=%p, size=%u) \"\n\t\t\t\"last callback va_end: %#tx (%#tx expeceted), \"\n\t\t\t\"num of objects: %u (%u expected)\\n\",\n\t\t\tmp, mp->size,\n\t\t\targ.obj_end, mp->elt_va_end,\n\t\t\targ.obj_num, mp->size);\n\t}\n}\n\n#ifndef __INTEL_COMPILER\n#pragma GCC diagnostic error \"-Wcast-qual\"\n#endif\n#else\n#define mempool_audit_cookies(mp) do {} while(0)\n#endif\n\n#if RTE_MEMPOOL_CACHE_MAX_SIZE > 0\n/* check cookies before and after objects */\nstatic void\nmempool_audit_cache(const struct rte_mempool *mp)\n{\n\t/* check cache size consistency */\n\tunsigned lcore_id;\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tif (mp->local_cache[lcore_id].len > mp->cache_flushthresh) {\n\t\t\tRTE_LOG(CRIT, MEMPOOL, \"badness on cache[%u]\\n\",\n\t\t\t\tlcore_id);\n\t\t\trte_panic(\"MEMPOOL: invalid cache len\\n\");\n\t\t}\n\t}\n}\n#else\n#define mempool_audit_cache(mp) do {} while(0)\n#endif\n\n\n/* check the consistency of mempool (size, cookies, ...) */\nvoid\nrte_mempool_audit(const struct rte_mempool *mp)\n{\n\tmempool_audit_cache(mp);\n\tmempool_audit_cookies(mp);\n\n\t/* For case where mempool DEBUG is not set, and cache size is 0 */\n\tRTE_SET_USED(mp);\n}\n\n/* dump the status of the mempool on the console */\nvoid\nrte_mempool_dump(FILE *f, const struct rte_mempool *mp)\n{\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n\tstruct rte_mempool_debug_stats sum;\n\tunsigned lcore_id;\n#endif\n\tunsigned common_count;\n\tunsigned cache_count;\n\n\tRTE_VERIFY(f != NULL);\n\tRTE_VERIFY(mp != NULL);\n\n\tfprintf(f, \"mempool <%s>@%p\\n\", mp->name, mp);\n\tfprintf(f, \" flags=%x\\n\", mp->flags);\n\tfprintf(f, \" ring=<%s>@%p\\n\", mp->ring->name, mp->ring);\n\tfprintf(f, \" phys_addr=0x%\" PRIx64 \"\\n\", mp->phys_addr);\n\tfprintf(f, \" size=%\"PRIu32\"\\n\", mp->size);\n\tfprintf(f, \" header_size=%\"PRIu32\"\\n\", mp->header_size);\n\tfprintf(f, \" elt_size=%\"PRIu32\"\\n\", mp->elt_size);\n\tfprintf(f, \" trailer_size=%\"PRIu32\"\\n\", mp->trailer_size);\n\tfprintf(f, \" total_obj_size=%\"PRIu32\"\\n\",\n\t mp->header_size + mp->elt_size + mp->trailer_size);\n\n\tfprintf(f, \" private_data_size=%\"PRIu32\"\\n\", mp->private_data_size);\n\tfprintf(f, \" pg_num=%\"PRIu32\"\\n\", mp->pg_num);\n\tfprintf(f, \" pg_shift=%\"PRIu32\"\\n\", mp->pg_shift);\n\tfprintf(f, \" pg_mask=%#tx\\n\", mp->pg_mask);\n\tfprintf(f, \" elt_va_start=%#tx\\n\", mp->elt_va_start);\n\tfprintf(f, \" elt_va_end=%#tx\\n\", mp->elt_va_end);\n\tfprintf(f, \" elt_pa[0]=0x%\" PRIx64 \"\\n\", mp->elt_pa[0]);\n\n\tif (mp->size != 0)\n\t\tfprintf(f, \" avg bytes/object=%#Lf\\n\",\n\t\t\t(long double)(mp->elt_va_end - mp->elt_va_start) /\n\t\t\tmp->size);\n\n\tcache_count = rte_mempool_dump_cache(f, mp);\n\tcommon_count = rte_ring_count(mp->ring);\n\tif ((cache_count + common_count) > mp->size)\n\t\tcommon_count = mp->size - cache_count;\n\tfprintf(f, \" common_pool_count=%u\\n\", common_count);\n\n\t/* sum and dump statistics */\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n\tmemset(&sum, 0, sizeof(sum));\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tsum.put_bulk += mp->stats[lcore_id].put_bulk;\n\t\tsum.put_objs += mp->stats[lcore_id].put_objs;\n\t\tsum.get_success_bulk += mp->stats[lcore_id].get_success_bulk;\n\t\tsum.get_success_objs += mp->stats[lcore_id].get_success_objs;\n\t\tsum.get_fail_bulk += mp->stats[lcore_id].get_fail_bulk;\n\t\tsum.get_fail_objs += mp->stats[lcore_id].get_fail_objs;\n\t}\n\tfprintf(f, \" stats:\\n\");\n\tfprintf(f, \" put_bulk=%\"PRIu64\"\\n\", sum.put_bulk);\n\tfprintf(f, \" put_objs=%\"PRIu64\"\\n\", sum.put_objs);\n\tfprintf(f, \" get_success_bulk=%\"PRIu64\"\\n\", sum.get_success_bulk);\n\tfprintf(f, \" get_success_objs=%\"PRIu64\"\\n\", sum.get_success_objs);\n\tfprintf(f, \" get_fail_bulk=%\"PRIu64\"\\n\", sum.get_fail_bulk);\n\tfprintf(f, \" get_fail_objs=%\"PRIu64\"\\n\", sum.get_fail_objs);\n#else\n\tfprintf(f, \" no statistics available\\n\");\n#endif\n\n\trte_mempool_audit(mp);\n}\n\n/* dump the status of all mempools on the console */\nvoid\nrte_mempool_list_dump(FILE *f)\n{\n\tconst struct rte_mempool *mp = NULL;\n\tstruct rte_tailq_entry *te;\n\tstruct rte_mempool_list *mempool_list;\n\n\tmempool_list = RTE_TAILQ_CAST(rte_mempool_tailq.head, rte_mempool_list);\n\n\trte_rwlock_read_lock(RTE_EAL_MEMPOOL_RWLOCK);\n\n\tTAILQ_FOREACH(te, mempool_list, next) {\n\t\tmp = (struct rte_mempool *) te->data;\n\t\trte_mempool_dump(f, mp);\n\t}\n\n\trte_rwlock_read_unlock(RTE_EAL_MEMPOOL_RWLOCK);\n}\n\n/* search a mempool from its name */\nstruct rte_mempool *\nrte_mempool_lookup(const char *name)\n{\n\tstruct rte_mempool *mp = NULL;\n\tstruct rte_tailq_entry *te;\n\tstruct rte_mempool_list *mempool_list;\n\n\tmempool_list = RTE_TAILQ_CAST(rte_mempool_tailq.head, rte_mempool_list);\n\n\trte_rwlock_read_lock(RTE_EAL_MEMPOOL_RWLOCK);\n\n\tTAILQ_FOREACH(te, mempool_list, next) {\n\t\tmp = (struct rte_mempool *) te->data;\n\t\tif (strncmp(name, mp->name, RTE_MEMPOOL_NAMESIZE) == 0)\n\t\t\tbreak;\n\t}\n\n\trte_rwlock_read_unlock(RTE_EAL_MEMPOOL_RWLOCK);\n\n\tif (te == NULL) {\n\t\trte_errno = ENOENT;\n\t\treturn NULL;\n\t}\n\n\treturn mp;\n}\n\nvoid rte_mempool_walk(void (*func)(const struct rte_mempool *, void *),\n\t\t void *arg)\n{\n\tstruct rte_tailq_entry *te = NULL;\n\tstruct rte_mempool_list *mempool_list;\n\n\tmempool_list = RTE_TAILQ_CAST(rte_mempool_tailq.head, rte_mempool_list);\n\n\trte_rwlock_read_lock(RTE_EAL_MEMPOOL_RWLOCK);\n\n\tTAILQ_FOREACH(te, mempool_list, next) {\n\t\t(*func)((struct rte_mempool *) te->data, arg);\n\t}\n\n\trte_rwlock_read_unlock(RTE_EAL_MEMPOOL_RWLOCK);\n}\n" }, { "path": "lib/librte_mempool/rte_mempool.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_MEMPOOL_H_\n#define _RTE_MEMPOOL_H_\n\n/**\n * @file\n * RTE Mempool.\n *\n * A memory pool is an allocator of fixed-size object. It is\n * identified by its name, and uses a ring to store free objects. It\n * provides some other optional services, like a per-core object\n * cache, and an alignment helper to ensure that objects are padded\n * to spread them equally on all RAM channels, ranks, and so on.\n *\n * Objects owned by a mempool should never be added in another\n * mempool. When an object is freed using rte_mempool_put() or\n * equivalent, the object data is not modified; the user can save some\n * meta-data in the object data and retrieve them when allocating a\n * new object.\n *\n * Note: the mempool implementation is not preemptable. A lcore must\n * not be interrupted by another task that uses the same mempool\n * (because it uses a ring which is not preemptable). Also, mempool\n * functions must not be used outside the DPDK environment: for\n * example, in linuxapp environment, a thread that is not created by\n * the EAL must not use mempools. This is due to the per-lcore cache\n * that won't work as rte_lcore_id() will not return a correct value.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define RTE_MEMPOOL_HEADER_COOKIE1 0xbadbadbadadd2e55ULL /**< Header cookie. */\n#define RTE_MEMPOOL_HEADER_COOKIE2 0xf2eef2eedadd2e55ULL /**< Header cookie. */\n#define RTE_MEMPOOL_TRAILER_COOKIE 0xadd2e55badbadbadULL /**< Trailer cookie.*/\n\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n/**\n * A structure that stores the mempool statistics (per-lcore).\n */\nstruct rte_mempool_debug_stats {\n\tuint64_t put_bulk; /**< Number of puts. */\n\tuint64_t put_objs; /**< Number of objects successfully put. */\n\tuint64_t get_success_bulk; /**< Successful allocation number. */\n\tuint64_t get_success_objs; /**< Objects successfully allocated. */\n\tuint64_t get_fail_bulk; /**< Failed allocation number. */\n\tuint64_t get_fail_objs; /**< Objects that failed to be allocated. */\n} __rte_cache_aligned;\n#endif\n\n#if RTE_MEMPOOL_CACHE_MAX_SIZE > 0\n/**\n * A structure that stores a per-core object cache.\n */\nstruct rte_mempool_cache {\n\tunsigned len; /**< Cache len */\n\t/*\n\t * Cache is allocated to this size to allow it to overflow in certain\n\t * cases to avoid needless emptying of cache.\n\t */\n\tvoid *objs[RTE_MEMPOOL_CACHE_MAX_SIZE * 3]; /**< Cache objects */\n} __rte_cache_aligned;\n#endif /* RTE_MEMPOOL_CACHE_MAX_SIZE > 0 */\n\n/**\n * A structure that stores the size of mempool elements.\n */\nstruct rte_mempool_objsz {\n\tuint32_t elt_size; /**< Size of an element. */\n\tuint32_t header_size; /**< Size of header (before elt). */\n\tuint32_t trailer_size; /**< Size of trailer (after elt). */\n\tuint32_t total_size;\n\t/**< Total size of an object (header + elt + trailer). */\n};\n\n#define RTE_MEMPOOL_NAMESIZE 32 /**< Maximum length of a memory pool. */\n#define RTE_MEMPOOL_MZ_PREFIX \"MP_\"\n\n/* \"MP_\" */\n#define\tRTE_MEMPOOL_MZ_FORMAT\tRTE_MEMPOOL_MZ_PREFIX \"%s\"\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n\n/* \"_MP_elt\" */\n#define\tRTE_MEMPOOL_OBJ_NAME\t\"%s_\" RTE_MEMPOOL_MZ_PREFIX \"elt\"\n\n#else\n\n#define\tRTE_MEMPOOL_OBJ_NAME\tRTE_MEMPOOL_MZ_FORMAT\n\n#endif /* RTE_LIBRTE_XEN_DOM0 */\n\n#define\tMEMPOOL_PG_SHIFT_MAX\t(sizeof(uintptr_t) * CHAR_BIT - 1)\n\n/** Mempool over one chunk of physically continuous memory */\n#define\tMEMPOOL_PG_NUM_DEFAULT\t1\n\n#ifndef RTE_MEMPOOL_ALIGN\n#define RTE_MEMPOOL_ALIGN\tRTE_CACHE_LINE_SIZE\n#endif\n\n#define RTE_MEMPOOL_ALIGN_MASK\t(RTE_MEMPOOL_ALIGN - 1)\n\n/**\n * Mempool object header structure\n *\n * Each object stored in mempools are prefixed by this header structure,\n * it allows to retrieve the mempool pointer from the object. When debug\n * is enabled, a cookie is also added in this structure preventing\n * corruptions and double-frees.\n */\nstruct rte_mempool_objhdr {\n\tstruct rte_mempool *mp; /**< The mempool owning the object. */\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n\tuint64_t cookie; /**< Debug cookie. */\n#endif\n};\n\n/**\n * Mempool object trailer structure\n *\n * In debug mode, each object stored in mempools are suffixed by this\n * trailer structure containing a cookie preventing memory corruptions.\n */\nstruct rte_mempool_objtlr {\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n\tuint64_t cookie; /**< Debug cookie. */\n#endif\n};\n\n/**\n * The RTE mempool structure.\n */\nstruct rte_mempool {\n\tchar name[RTE_MEMPOOL_NAMESIZE]; /**< Name of mempool. */\n\tstruct rte_ring *ring; /**< Ring to store objects. */\n\tphys_addr_t phys_addr; /**< Phys. addr. of mempool struct. */\n\tint flags; /**< Flags of the mempool. */\n\tuint32_t size; /**< Size of the mempool. */\n\tuint32_t cache_size; /**< Size of per-lcore local cache. */\n\tuint32_t cache_flushthresh;\n\t/**< Threshold before we flush excess elements. */\n\n\tuint32_t elt_size; /**< Size of an element. */\n\tuint32_t header_size; /**< Size of header (before elt). */\n\tuint32_t trailer_size; /**< Size of trailer (after elt). */\n\n\tunsigned private_data_size; /**< Size of private data. */\n\n#if RTE_MEMPOOL_CACHE_MAX_SIZE > 0\n\t/** Per-lcore local cache. */\n\tstruct rte_mempool_cache local_cache[RTE_MAX_LCORE];\n#endif\n\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n\t/** Per-lcore statistics. */\n\tstruct rte_mempool_debug_stats stats[RTE_MAX_LCORE];\n#endif\n\n\t/* Address translation support, starts from next cache line. */\n\n\t/** Number of elements in the elt_pa array. */\n\tuint32_t pg_num __rte_cache_aligned;\n\tuint32_t pg_shift; /**< LOG2 of the physical pages. */\n\tuintptr_t pg_mask; /**< physical page mask value. */\n\tuintptr_t elt_va_start;\n\t/**< Virtual address of the first mempool object. */\n\tuintptr_t elt_va_end;\n\t/**< Virtual address of the mempool object. */\n\tphys_addr_t elt_pa[MEMPOOL_PG_NUM_DEFAULT];\n\t/**< Array of physical page addresses for the mempool objects buffer. */\n\n} __rte_cache_aligned;\n\n#define MEMPOOL_F_NO_SPREAD 0x0001 /**< Do not spread in memory. */\n#define MEMPOOL_F_NO_CACHE_ALIGN 0x0002 /**< Do not align objs on cache lines.*/\n#define MEMPOOL_F_SP_PUT 0x0004 /**< Default put is \"single-producer\".*/\n#define MEMPOOL_F_SC_GET 0x0008 /**< Default get is \"single-consumer\".*/\n\n/**\n * @internal When debug is enabled, store some statistics.\n *\n * @param mp\n * Pointer to the memory pool.\n * @param name\n * Name of the statistics field to increment in the memory pool.\n * @param n\n * Number to add to the object-oriented statistics.\n */\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n#define __MEMPOOL_STAT_ADD(mp, name, n) do { \\\n\t\tunsigned __lcore_id = rte_lcore_id(); \\\n\t\tif (__lcore_id < RTE_MAX_LCORE) { \\\n\t\t\tmp->stats[__lcore_id].name##_objs += n;\t\\\n\t\t\tmp->stats[__lcore_id].name##_bulk += 1;\t\\\n\t\t} \\\n\t} while(0)\n#else\n#define __MEMPOOL_STAT_ADD(mp, name, n) do {} while(0)\n#endif\n\n/**\n * Calculate the size of the mempool header.\n *\n * @param mp\n * Pointer to the memory pool.\n * @param pgn\n * Number of pages used to store mempool objects.\n */\n#define\tMEMPOOL_HEADER_SIZE(mp, pgn)\t(sizeof(*(mp)) + \\\n\tRTE_ALIGN_CEIL(((pgn) - RTE_DIM((mp)->elt_pa)) * \\\n\tsizeof ((mp)->elt_pa[0]), RTE_CACHE_LINE_SIZE))\n\n/**\n * Return true if the whole mempool is in contiguous memory.\n */\n#define\tMEMPOOL_IS_CONTIG(mp) \\\n\t((mp)->pg_num == MEMPOOL_PG_NUM_DEFAULT && \\\n\t(mp)->phys_addr == (mp)->elt_pa[0])\n\n/* return the header of a mempool object (internal) */\nstatic inline struct rte_mempool_objhdr *__mempool_get_header(void *obj)\n{\n\treturn (struct rte_mempool_objhdr *)RTE_PTR_SUB(obj, sizeof(struct rte_mempool_objhdr));\n}\n\n/**\n * Return a pointer to the mempool owning this object.\n *\n * @param obj\n * An object that is owned by a pool. If this is not the case,\n * the behavior is undefined.\n * @return\n * A pointer to the mempool structure.\n */\nstatic inline struct rte_mempool *rte_mempool_from_obj(void *obj)\n{\n\tstruct rte_mempool_objhdr *hdr = __mempool_get_header(obj);\n\treturn hdr->mp;\n}\n\n/* return the trailer of a mempool object (internal) */\nstatic inline struct rte_mempool_objtlr *__mempool_get_trailer(void *obj)\n{\n\tstruct rte_mempool *mp = rte_mempool_from_obj(obj);\n\treturn (struct rte_mempool_objtlr *)RTE_PTR_ADD(obj, mp->elt_size);\n}\n\n/**\n * @internal Check and update cookies or panic.\n *\n * @param mp\n * Pointer to the memory pool.\n * @param obj_table_const\n * Pointer to a table of void * pointers (objects).\n * @param n\n * Index of object in object table.\n * @param free\n * - 0: object is supposed to be allocated, mark it as free\n * - 1: object is supposed to be free, mark it as allocated\n * - 2: just check that cookie is valid (free or allocated)\n */\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n#ifndef __INTEL_COMPILER\n#pragma GCC diagnostic ignored \"-Wcast-qual\"\n#endif\nstatic inline void __mempool_check_cookies(const struct rte_mempool *mp,\n\t\t\t\t\t void * const *obj_table_const,\n\t\t\t\t\t unsigned n, int free)\n{\n\tstruct rte_mempool_objhdr *hdr;\n\tstruct rte_mempool_objtlr *tlr;\n\tuint64_t cookie;\n\tvoid *tmp;\n\tvoid *obj;\n\tvoid **obj_table;\n\n\t/* Force to drop the \"const\" attribute. This is done only when\n\t * DEBUG is enabled */\n\ttmp = (void *) obj_table_const;\n\tobj_table = (void **) tmp;\n\n\twhile (n--) {\n\t\tobj = obj_table[n];\n\n\t\tif (rte_mempool_from_obj(obj) != mp)\n\t\t\trte_panic(\"MEMPOOL: object is owned by another \"\n\t\t\t\t \"mempool\\n\");\n\n\t\thdr = __mempool_get_header(obj);\n\t\tcookie = hdr->cookie;\n\n\t\tif (free == 0) {\n\t\t\tif (cookie != RTE_MEMPOOL_HEADER_COOKIE1) {\n\t\t\t\trte_log_set_history(0);\n\t\t\t\tRTE_LOG(CRIT, MEMPOOL,\n\t\t\t\t\t\"obj=%p, mempool=%p, cookie=%\" PRIx64 \"\\n\",\n\t\t\t\t\tobj, (const void *) mp, cookie);\n\t\t\t\trte_panic(\"MEMPOOL: bad header cookie (put)\\n\");\n\t\t\t}\n\t\t\thdr->cookie = RTE_MEMPOOL_HEADER_COOKIE2;\n\t\t}\n\t\telse if (free == 1) {\n\t\t\tif (cookie != RTE_MEMPOOL_HEADER_COOKIE2) {\n\t\t\t\trte_log_set_history(0);\n\t\t\t\tRTE_LOG(CRIT, MEMPOOL,\n\t\t\t\t\t\"obj=%p, mempool=%p, cookie=%\" PRIx64 \"\\n\",\n\t\t\t\t\tobj, (const void *) mp, cookie);\n\t\t\t\trte_panic(\"MEMPOOL: bad header cookie (get)\\n\");\n\t\t\t}\n\t\t\thdr->cookie = RTE_MEMPOOL_HEADER_COOKIE1;\n\t\t}\n\t\telse if (free == 2) {\n\t\t\tif (cookie != RTE_MEMPOOL_HEADER_COOKIE1 &&\n\t\t\t cookie != RTE_MEMPOOL_HEADER_COOKIE2) {\n\t\t\t\trte_log_set_history(0);\n\t\t\t\tRTE_LOG(CRIT, MEMPOOL,\n\t\t\t\t\t\"obj=%p, mempool=%p, cookie=%\" PRIx64 \"\\n\",\n\t\t\t\t\tobj, (const void *) mp, cookie);\n\t\t\t\trte_panic(\"MEMPOOL: bad header cookie (audit)\\n\");\n\t\t\t}\n\t\t}\n\t\ttlr = __mempool_get_trailer(obj);\n\t\tcookie = tlr->cookie;\n\t\tif (cookie != RTE_MEMPOOL_TRAILER_COOKIE) {\n\t\t\trte_log_set_history(0);\n\t\t\tRTE_LOG(CRIT, MEMPOOL,\n\t\t\t\t\"obj=%p, mempool=%p, cookie=%\" PRIx64 \"\\n\",\n\t\t\t\tobj, (const void *) mp, cookie);\n\t\t\trte_panic(\"MEMPOOL: bad trailer cookie\\n\");\n\t\t}\n\t}\n}\n#ifndef __INTEL_COMPILER\n#pragma GCC diagnostic error \"-Wcast-qual\"\n#endif\n#else\n#define __mempool_check_cookies(mp, obj_table_const, n, free) do {} while(0)\n#endif /* RTE_LIBRTE_MEMPOOL_DEBUG */\n\n/**\n * A mempool object iterator callback function.\n */\ntypedef void (*rte_mempool_obj_iter_t)(void * /*obj_iter_arg*/,\n\tvoid * /*obj_start*/,\n\tvoid * /*obj_end*/,\n\tuint32_t /*obj_index */);\n\n/**\n * Call a function for each mempool object in a memory chunk\n *\n * Iterate across objects of the given size and alignment in the\n * provided chunk of memory. The given memory buffer can consist of\n * disjointed physical pages.\n *\n * For each object, call the provided callback (if any). This function\n * is used to populate a mempool, or walk through all the elements of a\n * mempool, or estimate how many elements of the given size could be\n * created in the given memory buffer.\n *\n * @param vaddr\n * Virtual address of the memory buffer.\n * @param elt_num\n * Maximum number of objects to iterate through.\n * @param elt_sz\n * Size of each object.\n * @param align\n * Alignment of each object.\n * @param paddr\n * Array of physical addresses of the pages that comprises given memory\n * buffer.\n * @param pg_num\n * Number of elements in the paddr array.\n * @param pg_shift\n * LOG2 of the physical pages size.\n * @param obj_iter\n * Object iterator callback function (could be NULL).\n * @param obj_iter_arg\n * User defined parameter for the object iterator callback function.\n *\n * @return\n * Number of objects iterated through.\n */\nuint32_t rte_mempool_obj_iter(void *vaddr,\n\tuint32_t elt_num, size_t elt_sz, size_t align,\n\tconst phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift,\n\trte_mempool_obj_iter_t obj_iter, void *obj_iter_arg);\n\n/**\n * An object constructor callback function for mempool.\n *\n * Arguments are the mempool, the opaque pointer given by the user in\n * rte_mempool_create(), the pointer to the element and the index of\n * the element in the pool.\n */\ntypedef void (rte_mempool_obj_ctor_t)(struct rte_mempool *, void *,\n\t\t\t\t void *, unsigned);\n\n/**\n * A mempool constructor callback function.\n *\n * Arguments are the mempool and the opaque pointer given by the user in\n * rte_mempool_create().\n */\ntypedef void (rte_mempool_ctor_t)(struct rte_mempool *, void *);\n\n/**\n * Create a new mempool named *name* in memory.\n *\n * This function uses ``memzone_reserve()`` to allocate memory. The\n * pool contains n elements of elt_size. Its size is set to n.\n * All elements of the mempool are allocated together with the mempool header,\n * in one physically continuous chunk of memory.\n *\n * @param name\n * The name of the mempool.\n * @param n\n * The number of elements in the mempool. The optimum size (in terms of\n * memory usage) for a mempool is when n is a power of two minus one:\n * n = (2^q - 1).\n * @param elt_size\n * The size of each element.\n * @param cache_size\n * If cache_size is non-zero, the rte_mempool library will try to\n * limit the accesses to the common lockless pool, by maintaining a\n * per-lcore object cache. This argument must be lower or equal to\n * CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE and n / 1.5. It is advised to choose\n * cache_size to have \"n modulo cache_size == 0\": if this is\n * not the case, some elements will always stay in the pool and will\n * never be used. The access to the per-lcore table is of course\n * faster than the multi-producer/consumer pool. The cache can be\n * disabled if the cache_size argument is set to 0; it can be useful to\n * avoid losing objects in cache. Note that even if not used, the\n * memory space for cache is always reserved in a mempool structure,\n * except if CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE is set to 0.\n * @param private_data_size\n * The size of the private data appended after the mempool\n * structure. This is useful for storing some private data after the\n * mempool structure, as is done for rte_mbuf_pool for example.\n * @param mp_init\n * A function pointer that is called for initialization of the pool,\n * before object initialization. The user can initialize the private\n * data in this function if needed. This parameter can be NULL if\n * not needed.\n * @param mp_init_arg\n * An opaque pointer to data that can be used in the mempool\n * constructor function.\n * @param obj_init\n * A function pointer that is called for each object at\n * initialization of the pool. The user can set some meta data in\n * objects if needed. This parameter can be NULL if not needed.\n * The obj_init() function takes the mempool pointer, the init_arg,\n * the object pointer and the object number as parameters.\n * @param obj_init_arg\n * An opaque pointer to data that can be used as an argument for\n * each call to the object constructor function.\n * @param socket_id\n * The *socket_id* argument is the socket identifier in the case of\n * NUMA. The value can be *SOCKET_ID_ANY* if there is no NUMA\n * constraint for the reserved zone.\n * @param flags\n * The *flags* arguments is an OR of following flags:\n * - MEMPOOL_F_NO_SPREAD: By default, objects addresses are spread\n * between channels in RAM: the pool allocator will add padding\n * between objects depending on the hardware configuration. See\n * Memory alignment constraints for details. If this flag is set,\n * the allocator will just align them to a cache line.\n * - MEMPOOL_F_NO_CACHE_ALIGN: By default, the returned objects are\n * cache-aligned. This flag removes this constraint, and no\n * padding will be present between objects. This flag implies\n * MEMPOOL_F_NO_SPREAD.\n * - MEMPOOL_F_SP_PUT: If this flag is set, the default behavior\n * when using rte_mempool_put() or rte_mempool_put_bulk() is\n * \"single-producer\". Otherwise, it is \"multi-producers\".\n * - MEMPOOL_F_SC_GET: If this flag is set, the default behavior\n * when using rte_mempool_get() or rte_mempool_get_bulk() is\n * \"single-consumer\". Otherwise, it is \"multi-consumers\".\n * @return\n * The pointer to the new allocated mempool, on success. NULL on error\n * with rte_errno set appropriately. Possible rte_errno values include:\n * - E_RTE_NO_CONFIG - function could not get pointer to rte_config structure\n * - E_RTE_SECONDARY - function was called from a secondary process instance\n * - EINVAL - cache size provided is too large\n * - ENOSPC - the maximum number of memzones has already been allocated\n * - EEXIST - a memzone with the same name already exists\n * - ENOMEM - no appropriate memory area found in which to create memzone\n */\nstruct rte_mempool *\nrte_mempool_create(const char *name, unsigned n, unsigned elt_size,\n\t\t unsigned cache_size, unsigned private_data_size,\n\t\t rte_mempool_ctor_t *mp_init, void *mp_init_arg,\n\t\t rte_mempool_obj_ctor_t *obj_init, void *obj_init_arg,\n\t\t int socket_id, unsigned flags);\n\n/**\n * Create a new mempool named *name* in memory.\n *\n * This function uses ``memzone_reserve()`` to allocate memory. The\n * pool contains n elements of elt_size. Its size is set to n.\n * Depending on the input parameters, mempool elements can be either allocated\n * together with the mempool header, or an externally provided memory buffer\n * could be used to store mempool objects. In later case, that external\n * memory buffer can consist of set of disjoint physical pages.\n *\n * @param name\n * The name of the mempool.\n * @param n\n * The number of elements in the mempool. The optimum size (in terms of\n * memory usage) for a mempool is when n is a power of two minus one:\n * n = (2^q - 1).\n * @param elt_size\n * The size of each element.\n * @param cache_size\n * If cache_size is non-zero, the rte_mempool library will try to\n * limit the accesses to the common lockless pool, by maintaining a\n * per-lcore object cache. This argument must be lower or equal to\n * CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE. It is advised to choose\n * cache_size to have \"n modulo cache_size == 0\": if this is\n * not the case, some elements will always stay in the pool and will\n * never be used. The access to the per-lcore table is of course\n * faster than the multi-producer/consumer pool. The cache can be\n * disabled if the cache_size argument is set to 0; it can be useful to\n * avoid losing objects in cache. Note that even if not used, the\n * memory space for cache is always reserved in a mempool structure,\n * except if CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE is set to 0.\n * @param private_data_size\n * The size of the private data appended after the mempool\n * structure. This is useful for storing some private data after the\n * mempool structure, as is done for rte_mbuf_pool for example.\n * @param mp_init\n * A function pointer that is called for initialization of the pool,\n * before object initialization. The user can initialize the private\n * data in this function if needed. This parameter can be NULL if\n * not needed.\n * @param mp_init_arg\n * An opaque pointer to data that can be used in the mempool\n * constructor function.\n * @param obj_init\n * A function pointer that is called for each object at\n * initialization of the pool. The user can set some meta data in\n * objects if needed. This parameter can be NULL if not needed.\n * The obj_init() function takes the mempool pointer, the init_arg,\n * the object pointer and the object number as parameters.\n * @param obj_init_arg\n * An opaque pointer to data that can be used as an argument for\n * each call to the object constructor function.\n * @param socket_id\n * The *socket_id* argument is the socket identifier in the case of\n * NUMA. The value can be *SOCKET_ID_ANY* if there is no NUMA\n * constraint for the reserved zone.\n * @param flags\n * The *flags* arguments is an OR of following flags:\n * - MEMPOOL_F_NO_SPREAD: By default, objects addresses are spread\n * between channels in RAM: the pool allocator will add padding\n * between objects depending on the hardware configuration. See\n * Memory alignment constraints for details. If this flag is set,\n * the allocator will just align them to a cache line.\n * - MEMPOOL_F_NO_CACHE_ALIGN: By default, the returned objects are\n * cache-aligned. This flag removes this constraint, and no\n * padding will be present between objects. This flag implies\n * MEMPOOL_F_NO_SPREAD.\n * - MEMPOOL_F_SP_PUT: If this flag is set, the default behavior\n * when using rte_mempool_put() or rte_mempool_put_bulk() is\n * \"single-producer\". Otherwise, it is \"multi-producers\".\n * - MEMPOOL_F_SC_GET: If this flag is set, the default behavior\n * when using rte_mempool_get() or rte_mempool_get_bulk() is\n * \"single-consumer\". Otherwise, it is \"multi-consumers\".\n * @param vaddr\n * Virtual address of the externally allocated memory buffer.\n * Will be used to store mempool objects.\n * @param paddr\n * Array of physical addresses of the pages that comprises given memory\n * buffer.\n * @param pg_num\n * Number of elements in the paddr array.\n * @param pg_shift\n * LOG2 of the physical pages size.\n * @return\n * The pointer to the new allocated mempool, on success. NULL on error\n * with rte_errno set appropriately. Possible rte_errno values include:\n * - E_RTE_NO_CONFIG - function could not get pointer to rte_config structure\n * - E_RTE_SECONDARY - function was called from a secondary process instance\n * - EINVAL - cache size provided is too large\n * - ENOSPC - the maximum number of memzones has already been allocated\n * - EEXIST - a memzone with the same name already exists\n * - ENOMEM - no appropriate memory area found in which to create memzone\n */\nstruct rte_mempool *\nrte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size,\n\t\tunsigned cache_size, unsigned private_data_size,\n\t\trte_mempool_ctor_t *mp_init, void *mp_init_arg,\n\t\trte_mempool_obj_ctor_t *obj_init, void *obj_init_arg,\n\t\tint socket_id, unsigned flags, void *vaddr,\n\t\tconst phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift);\n\n#ifdef RTE_LIBRTE_XEN_DOM0\n/**\n * Create a new mempool named *name* in memory on Xen Dom0.\n *\n * This function uses ``rte_mempool_xmem_create()`` to allocate memory. The\n * pool contains n elements of elt_size. Its size is set to n.\n * All elements of the mempool are allocated together with the mempool header,\n * and memory buffer can consist of set of disjoint physical pages.\n *\n * @param name\n * The name of the mempool.\n * @param n\n * The number of elements in the mempool. The optimum size (in terms of\n * memory usage) for a mempool is when n is a power of two minus one:\n * n = (2^q - 1).\n * @param elt_size\n * The size of each element.\n * @param cache_size\n * If cache_size is non-zero, the rte_mempool library will try to\n * limit the accesses to the common lockless pool, by maintaining a\n * per-lcore object cache. This argument must be lower or equal to\n * CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE. It is advised to choose\n * cache_size to have \"n modulo cache_size == 0\": if this is\n * not the case, some elements will always stay in the pool and will\n * never be used. The access to the per-lcore table is of course\n * faster than the multi-producer/consumer pool. The cache can be\n * disabled if the cache_size argument is set to 0; it can be useful to\n * avoid losing objects in cache. Note that even if not used, the\n * memory space for cache is always reserved in a mempool structure,\n * except if CONFIG_RTE_MEMPOOL_CACHE_MAX_SIZE is set to 0.\n * @param private_data_size\n * The size of the private data appended after the mempool\n * structure. This is useful for storing some private data after the\n * mempool structure, as is done for rte_mbuf_pool for example.\n * @param mp_init\n * A function pointer that is called for initialization of the pool,\n * before object initialization. The user can initialize the private\n * data in this function if needed. This parameter can be NULL if\n * not needed.\n * @param mp_init_arg\n * An opaque pointer to data that can be used in the mempool\n * constructor function.\n * @param obj_init\n * A function pointer that is called for each object at\n * initialization of the pool. The user can set some meta data in\n * objects if needed. This parameter can be NULL if not needed.\n * The obj_init() function takes the mempool pointer, the init_arg,\n * the object pointer and the object number as parameters.\n * @param obj_init_arg\n * An opaque pointer to data that can be used as an argument for\n * each call to the object constructor function.\n * @param socket_id\n * The *socket_id* argument is the socket identifier in the case of\n * NUMA. The value can be *SOCKET_ID_ANY* if there is no NUMA\n * constraint for the reserved zone.\n * @param flags\n * The *flags* arguments is an OR of following flags:\n * - MEMPOOL_F_NO_SPREAD: By default, objects addresses are spread\n * between channels in RAM: the pool allocator will add padding\n * between objects depending on the hardware configuration. See\n * Memory alignment constraints for details. If this flag is set,\n * the allocator will just align them to a cache line.\n * - MEMPOOL_F_NO_CACHE_ALIGN: By default, the returned objects are\n * cache-aligned. This flag removes this constraint, and no\n * padding will be present between objects. This flag implies\n * MEMPOOL_F_NO_SPREAD.\n * - MEMPOOL_F_SP_PUT: If this flag is set, the default behavior\n * when using rte_mempool_put() or rte_mempool_put_bulk() is\n * \"single-producer\". Otherwise, it is \"multi-producers\".\n * - MEMPOOL_F_SC_GET: If this flag is set, the default behavior\n * when using rte_mempool_get() or rte_mempool_get_bulk() is\n * \"single-consumer\". Otherwise, it is \"multi-consumers\".\n * @return\n * The pointer to the new allocated mempool, on success. NULL on error\n * with rte_errno set appropriately. Possible rte_errno values include:\n * - E_RTE_NO_CONFIG - function could not get pointer to rte_config structure\n * - E_RTE_SECONDARY - function was called from a secondary process instance\n * - EINVAL - cache size provided is too large\n * - ENOSPC - the maximum number of memzones has already been allocated\n * - EEXIST - a memzone with the same name already exists\n * - ENOMEM - no appropriate memory area found in which to create memzone\n */\nstruct rte_mempool *\nrte_dom0_mempool_create(const char *name, unsigned n, unsigned elt_size,\n\t\tunsigned cache_size, unsigned private_data_size,\n\t\trte_mempool_ctor_t *mp_init, void *mp_init_arg,\n\t\trte_mempool_obj_ctor_t *obj_init, void *obj_init_arg,\n\t\tint socket_id, unsigned flags);\n#endif\n\n/**\n * Dump the status of the mempool to the console.\n *\n * @param f\n * A pointer to a file for output\n * @param mp\n * A pointer to the mempool structure.\n */\nvoid rte_mempool_dump(FILE *f, const struct rte_mempool *mp);\n\n/**\n * @internal Put several objects back in the mempool; used internally.\n * @param mp\n * A pointer to the mempool structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to store back in the mempool, must be strictly\n * positive.\n * @param is_mp\n * Mono-producer (0) or multi-producers (1).\n */\nstatic inline void __attribute__((always_inline))\n__mempool_put_bulk(struct rte_mempool *mp, void * const *obj_table,\n\t\t unsigned n, int is_mp)\n{\n#if RTE_MEMPOOL_CACHE_MAX_SIZE > 0\n\tstruct rte_mempool_cache *cache;\n\tuint32_t index;\n\tvoid **cache_objs;\n\tunsigned lcore_id = rte_lcore_id();\n\tuint32_t cache_size = mp->cache_size;\n\tuint32_t flushthresh = mp->cache_flushthresh;\n#endif /* RTE_MEMPOOL_CACHE_MAX_SIZE > 0 */\n\n\t/* increment stat now, adding in mempool always success */\n\t__MEMPOOL_STAT_ADD(mp, put, n);\n\n#if RTE_MEMPOOL_CACHE_MAX_SIZE > 0\n\t/* cache is not enabled or single producer or non-EAL thread */\n\tif (unlikely(cache_size == 0 || is_mp == 0 ||\n\t\t lcore_id >= RTE_MAX_LCORE))\n\t\tgoto ring_enqueue;\n\n\t/* Go straight to ring if put would overflow mem allocated for cache */\n\tif (unlikely(n > RTE_MEMPOOL_CACHE_MAX_SIZE))\n\t\tgoto ring_enqueue;\n\n\tcache = &mp->local_cache[lcore_id];\n\tcache_objs = &cache->objs[cache->len];\n\n\t/*\n\t * The cache follows the following algorithm\n\t * 1. Add the objects to the cache\n\t * 2. Anything greater than the cache min value (if it crosses the\n\t * cache flush threshold) is flushed to the ring.\n\t */\n\n\t/* Add elements back into the cache */\n\tfor (index = 0; index < n; ++index, obj_table++)\n\t\tcache_objs[index] = *obj_table;\n\n\tcache->len += n;\n\n\tif (cache->len >= flushthresh) {\n\t\trte_ring_mp_enqueue_bulk(mp->ring, &cache->objs[cache_size],\n\t\t\t\tcache->len - cache_size);\n\t\tcache->len = cache_size;\n\t}\n\n\treturn;\n\nring_enqueue:\n#endif /* RTE_MEMPOOL_CACHE_MAX_SIZE > 0 */\n\n\t/* push remaining objects in ring */\n#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n\tif (is_mp) {\n\t\tif (rte_ring_mp_enqueue_bulk(mp->ring, obj_table, n) < 0)\n\t\t\trte_panic(\"cannot put objects in mempool\\n\");\n\t}\n\telse {\n\t\tif (rte_ring_sp_enqueue_bulk(mp->ring, obj_table, n) < 0)\n\t\t\trte_panic(\"cannot put objects in mempool\\n\");\n\t}\n#else\n\tif (is_mp)\n\t\trte_ring_mp_enqueue_bulk(mp->ring, obj_table, n);\n\telse\n\t\trte_ring_sp_enqueue_bulk(mp->ring, obj_table, n);\n#endif\n}\n\n\n/**\n * Put several objects back in the mempool (multi-producers safe).\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to add in the mempool from the obj_table.\n */\nstatic inline void __attribute__((always_inline))\nrte_mempool_mp_put_bulk(struct rte_mempool *mp, void * const *obj_table,\n\t\t\tunsigned n)\n{\n\t__mempool_check_cookies(mp, obj_table, n, 0);\n\t__mempool_put_bulk(mp, obj_table, n, 1);\n}\n\n/**\n * Put several objects back in the mempool (NOT multi-producers safe).\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to add in the mempool from obj_table.\n */\nstatic inline void\nrte_mempool_sp_put_bulk(struct rte_mempool *mp, void * const *obj_table,\n\t\t\tunsigned n)\n{\n\t__mempool_check_cookies(mp, obj_table, n, 0);\n\t__mempool_put_bulk(mp, obj_table, n, 0);\n}\n\n/**\n * Put several objects back in the mempool.\n *\n * This function calls the multi-producer or the single-producer\n * version depending on the default behavior that was specified at\n * mempool creation time (see flags).\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to add in the mempool from obj_table.\n */\nstatic inline void __attribute__((always_inline))\nrte_mempool_put_bulk(struct rte_mempool *mp, void * const *obj_table,\n\t\t unsigned n)\n{\n\t__mempool_check_cookies(mp, obj_table, n, 0);\n\t__mempool_put_bulk(mp, obj_table, n, !(mp->flags & MEMPOOL_F_SP_PUT));\n}\n\n/**\n * Put one object in the mempool (multi-producers safe).\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param obj\n * A pointer to the object to be added.\n */\nstatic inline void __attribute__((always_inline))\nrte_mempool_mp_put(struct rte_mempool *mp, void *obj)\n{\n\trte_mempool_mp_put_bulk(mp, &obj, 1);\n}\n\n/**\n * Put one object back in the mempool (NOT multi-producers safe).\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param obj\n * A pointer to the object to be added.\n */\nstatic inline void __attribute__((always_inline))\nrte_mempool_sp_put(struct rte_mempool *mp, void *obj)\n{\n\trte_mempool_sp_put_bulk(mp, &obj, 1);\n}\n\n/**\n * Put one object back in the mempool.\n *\n * This function calls the multi-producer or the single-producer\n * version depending on the default behavior that was specified at\n * mempool creation time (see flags).\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param obj\n * A pointer to the object to be added.\n */\nstatic inline void __attribute__((always_inline))\nrte_mempool_put(struct rte_mempool *mp, void *obj)\n{\n\trte_mempool_put_bulk(mp, &obj, 1);\n}\n\n/**\n * @internal Get several objects from the mempool; used internally.\n * @param mp\n * A pointer to the mempool structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to get, must be strictly positive.\n * @param is_mc\n * Mono-consumer (0) or multi-consumers (1).\n * @return\n * - >=0: Success; number of objects supplied.\n * - <0: Error; code of ring dequeue function.\n */\nstatic inline int __attribute__((always_inline))\n__mempool_get_bulk(struct rte_mempool *mp, void **obj_table,\n\t\t unsigned n, int is_mc)\n{\n\tint ret;\n#if RTE_MEMPOOL_CACHE_MAX_SIZE > 0\n\tstruct rte_mempool_cache *cache;\n\tuint32_t index, len;\n\tvoid **cache_objs;\n\tunsigned lcore_id = rte_lcore_id();\n\tuint32_t cache_size = mp->cache_size;\n\n\t/* cache is not enabled or single consumer */\n\tif (unlikely(cache_size == 0 || is_mc == 0 ||\n\t\t n >= cache_size || lcore_id >= RTE_MAX_LCORE))\n\t\tgoto ring_dequeue;\n\n\tcache = &mp->local_cache[lcore_id];\n\tcache_objs = cache->objs;\n\n\t/* Can this be satisfied from the cache? */\n\tif (cache->len < n) {\n\t\t/* No. Backfill the cache first, and then fill from it */\n\t\tuint32_t req = n + (cache_size - cache->len);\n\n\t\t/* How many do we require i.e. number to fill the cache + the request */\n\t\tret = rte_ring_mc_dequeue_bulk(mp->ring, &cache->objs[cache->len], req);\n\t\tif (unlikely(ret < 0)) {\n\t\t\t/*\n\t\t\t * In the offchance that we are buffer constrained,\n\t\t\t * where we are not able to allocate cache + n, go to\n\t\t\t * the ring directly. If that fails, we are truly out of\n\t\t\t * buffers.\n\t\t\t */\n\t\t\tgoto ring_dequeue;\n\t\t}\n\n\t\tcache->len += req;\n\t}\n\n\t/* Now fill in the response ... */\n\tfor (index = 0, len = cache->len - 1; index < n; ++index, len--, obj_table++)\n\t\t*obj_table = cache_objs[len];\n\n\tcache->len -= n;\n\n\t__MEMPOOL_STAT_ADD(mp, get_success, n);\n\n\treturn 0;\n\nring_dequeue:\n#endif /* RTE_MEMPOOL_CACHE_MAX_SIZE > 0 */\n\n\t/* get remaining objects from ring */\n\tif (is_mc)\n\t\tret = rte_ring_mc_dequeue_bulk(mp->ring, obj_table, n);\n\telse\n\t\tret = rte_ring_sc_dequeue_bulk(mp->ring, obj_table, n);\n\n\tif (ret < 0)\n\t\t__MEMPOOL_STAT_ADD(mp, get_fail, n);\n\telse\n\t\t__MEMPOOL_STAT_ADD(mp, get_success, n);\n\n\treturn ret;\n}\n\n/**\n * Get several objects from the mempool (multi-consumers safe).\n *\n * If cache is enabled, objects will be retrieved first from cache,\n * subsequently from the common pool. Note that it can return -ENOENT when\n * the local cache and common pool are empty, even if cache from other\n * lcores are full.\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects) that will be filled.\n * @param n\n * The number of objects to get from mempool to obj_table.\n * @return\n * - 0: Success; objects taken.\n * - -ENOENT: Not enough entries in the mempool; no object is retrieved.\n */\nstatic inline int __attribute__((always_inline))\nrte_mempool_mc_get_bulk(struct rte_mempool *mp, void **obj_table, unsigned n)\n{\n\tint ret;\n\tret = __mempool_get_bulk(mp, obj_table, n, 1);\n\tif (ret == 0)\n\t\t__mempool_check_cookies(mp, obj_table, n, 1);\n\treturn ret;\n}\n\n/**\n * Get several objects from the mempool (NOT multi-consumers safe).\n *\n * If cache is enabled, objects will be retrieved first from cache,\n * subsequently from the common pool. Note that it can return -ENOENT when\n * the local cache and common pool are empty, even if cache from other\n * lcores are full.\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects) that will be filled.\n * @param n\n * The number of objects to get from the mempool to obj_table.\n * @return\n * - 0: Success; objects taken.\n * - -ENOENT: Not enough entries in the mempool; no object is\n * retrieved.\n */\nstatic inline int __attribute__((always_inline))\nrte_mempool_sc_get_bulk(struct rte_mempool *mp, void **obj_table, unsigned n)\n{\n\tint ret;\n\tret = __mempool_get_bulk(mp, obj_table, n, 0);\n\tif (ret == 0)\n\t\t__mempool_check_cookies(mp, obj_table, n, 1);\n\treturn ret;\n}\n\n/**\n * Get several objects from the mempool.\n *\n * This function calls the multi-consumers or the single-consumer\n * version, depending on the default behaviour that was specified at\n * mempool creation time (see flags).\n *\n * If cache is enabled, objects will be retrieved first from cache,\n * subsequently from the common pool. Note that it can return -ENOENT when\n * the local cache and common pool are empty, even if cache from other\n * lcores are full.\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects) that will be filled.\n * @param n\n * The number of objects to get from the mempool to obj_table.\n * @return\n * - 0: Success; objects taken\n * - -ENOENT: Not enough entries in the mempool; no object is retrieved.\n */\nstatic inline int __attribute__((always_inline))\nrte_mempool_get_bulk(struct rte_mempool *mp, void **obj_table, unsigned n)\n{\n\tint ret;\n\tret = __mempool_get_bulk(mp, obj_table, n,\n\t\t\t\t !(mp->flags & MEMPOOL_F_SC_GET));\n\tif (ret == 0)\n\t\t__mempool_check_cookies(mp, obj_table, n, 1);\n\treturn ret;\n}\n\n/**\n * Get one object from the mempool (multi-consumers safe).\n *\n * If cache is enabled, objects will be retrieved first from cache,\n * subsequently from the common pool. Note that it can return -ENOENT when\n * the local cache and common pool are empty, even if cache from other\n * lcores are full.\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param obj_p\n * A pointer to a void * pointer (object) that will be filled.\n * @return\n * - 0: Success; objects taken.\n * - -ENOENT: Not enough entries in the mempool; no object is retrieved.\n */\nstatic inline int __attribute__((always_inline))\nrte_mempool_mc_get(struct rte_mempool *mp, void **obj_p)\n{\n\treturn rte_mempool_mc_get_bulk(mp, obj_p, 1);\n}\n\n/**\n * Get one object from the mempool (NOT multi-consumers safe).\n *\n * If cache is enabled, objects will be retrieved first from cache,\n * subsequently from the common pool. Note that it can return -ENOENT when\n * the local cache and common pool are empty, even if cache from other\n * lcores are full.\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param obj_p\n * A pointer to a void * pointer (object) that will be filled.\n * @return\n * - 0: Success; objects taken.\n * - -ENOENT: Not enough entries in the mempool; no object is retrieved.\n */\nstatic inline int __attribute__((always_inline))\nrte_mempool_sc_get(struct rte_mempool *mp, void **obj_p)\n{\n\treturn rte_mempool_sc_get_bulk(mp, obj_p, 1);\n}\n\n/**\n * Get one object from the mempool.\n *\n * This function calls the multi-consumers or the single-consumer\n * version, depending on the default behavior that was specified at\n * mempool creation (see flags).\n *\n * If cache is enabled, objects will be retrieved first from cache,\n * subsequently from the common pool. Note that it can return -ENOENT when\n * the local cache and common pool are empty, even if cache from other\n * lcores are full.\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param obj_p\n * A pointer to a void * pointer (object) that will be filled.\n * @return\n * - 0: Success; objects taken.\n * - -ENOENT: Not enough entries in the mempool; no object is retrieved.\n */\nstatic inline int __attribute__((always_inline))\nrte_mempool_get(struct rte_mempool *mp, void **obj_p)\n{\n\treturn rte_mempool_get_bulk(mp, obj_p, 1);\n}\n\n/**\n * Return the number of entries in the mempool.\n *\n * When cache is enabled, this function has to browse the length of\n * all lcores, so it should not be used in a data path, but only for\n * debug purposes.\n *\n * @param mp\n * A pointer to the mempool structure.\n * @return\n * The number of entries in the mempool.\n */\nunsigned rte_mempool_count(const struct rte_mempool *mp);\n\n/**\n * Return the number of free entries in the mempool ring.\n * i.e. how many entries can be freed back to the mempool.\n *\n * NOTE: This corresponds to the number of elements *allocated* from the\n * memory pool, not the number of elements in the pool itself. To count\n * the number elements currently available in the pool, use \"rte_mempool_count\"\n *\n * When cache is enabled, this function has to browse the length of\n * all lcores, so it should not be used in a data path, but only for\n * debug purposes.\n *\n * @param mp\n * A pointer to the mempool structure.\n * @return\n * The number of free entries in the mempool.\n */\nstatic inline unsigned\nrte_mempool_free_count(const struct rte_mempool *mp)\n{\n\treturn mp->size - rte_mempool_count(mp);\n}\n\n/**\n * Test if the mempool is full.\n *\n * When cache is enabled, this function has to browse the length of all\n * lcores, so it should not be used in a data path, but only for debug\n * purposes.\n *\n * @param mp\n * A pointer to the mempool structure.\n * @return\n * - 1: The mempool is full.\n * - 0: The mempool is not full.\n */\nstatic inline int\nrte_mempool_full(const struct rte_mempool *mp)\n{\n\treturn !!(rte_mempool_count(mp) == mp->size);\n}\n\n/**\n * Test if the mempool is empty.\n *\n * When cache is enabled, this function has to browse the length of all\n * lcores, so it should not be used in a data path, but only for debug\n * purposes.\n *\n * @param mp\n * A pointer to the mempool structure.\n * @return\n * - 1: The mempool is empty.\n * - 0: The mempool is not empty.\n */\nstatic inline int\nrte_mempool_empty(const struct rte_mempool *mp)\n{\n\treturn !!(rte_mempool_count(mp) == 0);\n}\n\n/**\n * Return the physical address of elt, which is an element of the pool mp.\n *\n * @param mp\n * A pointer to the mempool structure.\n * @param elt\n * A pointer (virtual address) to the element of the pool.\n * @return\n * The physical address of the elt element.\n */\nstatic inline phys_addr_t\nrte_mempool_virt2phy(const struct rte_mempool *mp, const void *elt)\n{\n\tif (rte_eal_has_hugepages()) {\n\t\tuintptr_t off;\n\n\t\toff = (const char *)elt - (const char *)mp->elt_va_start;\n\t\treturn (mp->elt_pa[off >> mp->pg_shift] + (off & mp->pg_mask));\n\t} else {\n\t\t/*\n\t\t * If huge pages are disabled, we cannot assume the\n\t\t * memory region to be physically contiguous.\n\t\t * Lookup for each element.\n\t\t */\n\t\treturn rte_mem_virt2phy(elt);\n\t}\n}\n\n/**\n * Check the consistency of mempool objects.\n *\n * Verify the coherency of fields in the mempool structure. Also check\n * that the cookies of mempool objects (even the ones that are not\n * present in pool) have a correct value. If not, a panic will occur.\n *\n * @param mp\n * A pointer to the mempool structure.\n */\nvoid rte_mempool_audit(const struct rte_mempool *mp);\n\n/**\n * Return a pointer to the private data in an mempool structure.\n *\n * @param mp\n * A pointer to the mempool structure.\n * @return\n * A pointer to the private data.\n */\nstatic inline void *rte_mempool_get_priv(struct rte_mempool *mp)\n{\n\treturn (char *)mp + MEMPOOL_HEADER_SIZE(mp, mp->pg_num);\n}\n\n/**\n * Dump the status of all mempools on the console\n *\n * @param f\n * A pointer to a file for output\n */\nvoid rte_mempool_list_dump(FILE *f);\n\n/**\n * Search a mempool from its name\n *\n * @param name\n * The name of the mempool.\n * @return\n * The pointer to the mempool matching the name, or NULL if not found.\n * NULL on error\n * with rte_errno set appropriately. Possible rte_errno values include:\n * - ENOENT - required entry not available to return.\n *\n */\nstruct rte_mempool *rte_mempool_lookup(const char *name);\n\n/**\n * Get the header, trailer and total size of a mempool element.\n *\n * Given a desired size of the mempool element and mempool flags,\n * calculates header, trailer, body and total sizes of the mempool object.\n *\n * @param elt_size\n * The size of each element.\n * @param flags\n * The flags used for the mempool creation.\n * Consult rte_mempool_create() for more information about possible values.\n * The size of each element.\n * @param sz\n * The calculated detailed size the mempool object. May be NULL.\n * @return\n * Total size of the mempool object.\n */\nuint32_t rte_mempool_calc_obj_size(uint32_t elt_size, uint32_t flags,\n\tstruct rte_mempool_objsz *sz);\n\n/**\n * Get the size of memory required to store mempool elements.\n *\n * Calculate the maximum amount of memory required to store given number\n * of objects. Assume that the memory buffer will be aligned at page\n * boundary.\n *\n * Note that if object size is bigger then page size, then it assumes\n * that pages are grouped in subsets of physically continuous pages big\n * enough to store at least one object.\n *\n * @param elt_num\n * Number of elements.\n * @param elt_sz\n * The size of each element.\n * @param pg_shift\n * LOG2 of the physical pages size.\n * @return\n * Required memory size aligned at page boundary.\n */\nsize_t rte_mempool_xmem_size(uint32_t elt_num, size_t elt_sz,\n\tuint32_t pg_shift);\n\n/**\n * Get the size of memory required to store mempool elements.\n *\n * Calculate how much memory would be actually required with the given\n * memory footprint to store required number of objects.\n *\n * @param vaddr\n * Virtual address of the externally allocated memory buffer.\n * Will be used to store mempool objects.\n * @param elt_num\n * Number of elements.\n * @param elt_sz\n * The size of each element.\n * @param paddr\n * Array of physical addresses of the pages that comprises given memory\n * buffer.\n * @param pg_num\n * Number of elements in the paddr array.\n * @param pg_shift\n * LOG2 of the physical pages size.\n * @return\n * On success, the number of bytes needed to store given number of\n * objects, aligned to the given page size. If the provided memory\n * buffer is too small, return a negative value whose absolute value\n * is the actual number of elements that can be stored in that buffer.\n */\nssize_t rte_mempool_xmem_usage(void *vaddr, uint32_t elt_num, size_t elt_sz,\n\tconst phys_addr_t paddr[], uint32_t pg_num, uint32_t pg_shift);\n\n/**\n * Walk list of all memory pools\n *\n * @param func\n * Iterator function\n * @param arg\n * Argument passed to iterator\n */\nvoid rte_mempool_walk(void (*func)(const struct rte_mempool *, void *arg),\n\t\t void *arg);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_MEMPOOL_H_ */\n" }, { "path": "lib/librte_meter/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_meter.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_meter_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_METER) := rte_meter.c\n\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_METER)-include := rte_meter.h\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_METER) += lib/librte_eal\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_meter/rte_meter.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n\n#include \n#include \n#include \n\n#include \"rte_meter.h\"\n\n#ifndef RTE_METER_TB_PERIOD_MIN\n#define RTE_METER_TB_PERIOD_MIN 100\n#endif\n\nstatic void\nrte_meter_get_tb_params(uint64_t hz, uint64_t rate, uint64_t *tb_period, uint64_t *tb_bytes_per_period)\n{\n\tdouble period = ((double) hz) / ((double) rate);\n\n\tif (period >= RTE_METER_TB_PERIOD_MIN) {\n\t\t*tb_bytes_per_period = 1;\n\t\t*tb_period = (uint64_t) period;\n\t} else {\n\t\t*tb_bytes_per_period = (uint64_t) ceil(RTE_METER_TB_PERIOD_MIN / period);\n\t\t*tb_period = (hz * (*tb_bytes_per_period)) / rate;\n\t}\n}\n\nint\nrte_meter_srtcm_config(struct rte_meter_srtcm *m, struct rte_meter_srtcm_params *params)\n{\n\tuint64_t hz;\n\n\t/* Check input parameters */\n\tif ((m == NULL) || (params == NULL)) {\n\t\treturn -1;\n\t}\n\n\tif ((params->cir == 0) || ((params->cbs == 0) && (params->ebs == 0))) {\n\t\treturn -2;\n\t}\n\n\t/* Initialize srTCM run-time structure */\n\thz = rte_get_tsc_hz();\n\tm->time = rte_get_tsc_cycles();\n\tm->tc = m->cbs = params->cbs;\n\tm->te = m->ebs = params->ebs;\n\trte_meter_get_tb_params(hz, params->cir, &m->cir_period, &m->cir_bytes_per_period);\n\n\tRTE_LOG(INFO, METER, \"Low level srTCM config: \\n\"\n\t\t\"\\tCIR period = %\" PRIu64 \", CIR bytes per period = %\" PRIu64 \"\\n\",\n\t\tm->cir_period, m->cir_bytes_per_period);\n\n\treturn 0;\n}\n\nint\nrte_meter_trtcm_config(struct rte_meter_trtcm *m, struct rte_meter_trtcm_params *params)\n{\n\tuint64_t hz;\n\n\t/* Check input parameters */\n\tif ((m == NULL) || (params == NULL)) {\n\t\treturn -1;\n\t}\n\n\tif ((params->cir == 0) || (params->pir == 0) || (params->pir < params->cir) ||\n\t\t(params->cbs == 0) || (params->pbs == 0)) {\n\t\treturn -2;\n\t}\n\n\t/* Initialize trTCM run-time structure */\n\thz = rte_get_tsc_hz();\n\tm->time_tc = m->time_tp = rte_get_tsc_cycles();\n\tm->tc = m->cbs = params->cbs;\n\tm->tp = m->pbs = params->pbs;\n\trte_meter_get_tb_params(hz, params->cir, &m->cir_period, &m->cir_bytes_per_period);\n\trte_meter_get_tb_params(hz, params->pir, &m->pir_period, &m->pir_bytes_per_period);\n\n\tRTE_LOG(INFO, METER, \"Low level trTCM config: \\n\"\n\t\t\"\\tCIR period = %\" PRIu64 \", CIR bytes per period = %\" PRIu64 \"\\n\"\n\t\t\"\\tPIR period = %\" PRIu64 \", PIR bytes per period = %\" PRIu64 \"\\n\",\n\t\tm->cir_period, m->cir_bytes_per_period,\n\t\tm->pir_period, m->pir_bytes_per_period);\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_meter/rte_meter.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_METER_H__\n#define __INCLUDE_RTE_METER_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Traffic Metering\n *\n * Traffic metering algorithms:\n * 1. Single Rate Three Color Marker (srTCM): defined by IETF RFC 2697\n * 2. Two Rate Three Color Marker (trTCM): defined by IETF RFC 2698\n *\n ***/\n\n#include \n\n/*\n * Application Programmer's Interface (API)\n *\n ***/\n\n/** Packet Color Set */\nenum rte_meter_color {\n\te_RTE_METER_GREEN = 0, /**< Green */\n\te_RTE_METER_YELLOW, /**< Yellow */\n\te_RTE_METER_RED, /**< Red */\n\te_RTE_METER_COLORS /**< Number of available colors */\n};\n\n/** srTCM parameters per metered traffic flow. The CIR, CBS and EBS parameters only\ncount bytes of IP packets and do not include link specific headers. At least one of\nthe CBS or EBS parameters has to be greater than zero. */\nstruct rte_meter_srtcm_params {\n\tuint64_t cir; /**< Committed Information Rate (CIR). Measured in bytes per second. */\n\tuint64_t cbs; /**< Committed Burst Size (CBS). Measured in bytes. */\n\tuint64_t ebs; /**< Excess Burst Size (EBS). Measured in bytes. */\n};\n\n/** trTCM parameters per metered traffic flow. The CIR, PIR, CBS and PBS parameters\nonly count bytes of IP packets and do not include link specific headers. PIR has to\nbe greater than or equal to CIR. Both CBS or EBS have to be greater than zero. */\nstruct rte_meter_trtcm_params {\n\tuint64_t cir; /**< Committed Information Rate (CIR). Measured in bytes per second. */\n\tuint64_t pir; /**< Peak Information Rate (PIR). Measured in bytes per second. */\n\tuint64_t cbs; /**< Committed Burst Size (CBS). Measured in byes. */\n\tuint64_t pbs; /**< Peak Burst Size (PBS). Measured in bytes. */\n};\n\n/** Internal data structure storing the srTCM run-time context per metered traffic flow. */\nstruct rte_meter_srtcm;\n\n/** Internal data structure storing the trTCM run-time context per metered traffic flow. */\nstruct rte_meter_trtcm;\n\n/**\n * srTCM configuration per metered traffic flow\n *\n * @param m\n * Pointer to pre-allocated srTCM data structure\n * @param params\n * User parameters per srTCM metered traffic flow\n * @return\n * 0 upon success, error code otherwise\n */\nint\nrte_meter_srtcm_config(struct rte_meter_srtcm *m,\n\tstruct rte_meter_srtcm_params *params);\n\n/**\n * trTCM configuration per metered traffic flow\n *\n * @param m\n * Pointer to pre-allocated trTCM data structure\n * @param params\n * User parameters per trTCM metered traffic flow\n * @return\n * 0 upon success, error code otherwise\n */\nint\nrte_meter_trtcm_config(struct rte_meter_trtcm *m,\n\tstruct rte_meter_trtcm_params *params);\n\n/**\n * srTCM color blind traffic metering\n *\n * @param m\n * Handle to srTCM instance\n * @param time\n * Current CPU time stamp (measured in CPU cycles)\n * @param pkt_len\n * Length of the current IP packet (measured in bytes)\n * @return\n * Color assigned to the current IP packet\n */\nstatic inline enum rte_meter_color\nrte_meter_srtcm_color_blind_check(struct rte_meter_srtcm *m,\n\tuint64_t time,\n\tuint32_t pkt_len);\n\n/**\n * srTCM color aware traffic metering\n *\n * @param m\n * Handle to srTCM instance\n * @param time\n * Current CPU time stamp (measured in CPU cycles)\n * @param pkt_len\n * Length of the current IP packet (measured in bytes)\n * @param pkt_color\n * Input color of the current IP packet\n * @return\n * Color assigned to the current IP packet\n */\nstatic inline enum rte_meter_color\nrte_meter_srtcm_color_aware_check(struct rte_meter_srtcm *m,\n\tuint64_t time,\n\tuint32_t pkt_len,\n\tenum rte_meter_color pkt_color);\n\n/**\n * trTCM color blind traffic metering\n *\n * @param m\n * Handle to trTCM instance\n * @param time\n * Current CPU time stamp (measured in CPU cycles)\n * @param pkt_len\n * Length of the current IP packet (measured in bytes)\n * @return\n * Color assigned to the current IP packet\n */\nstatic inline enum rte_meter_color\nrte_meter_trtcm_color_blind_check(struct rte_meter_trtcm *m,\n\tuint64_t time,\n\tuint32_t pkt_len);\n\n/**\n * trTCM color aware traffic metering\n *\n * @param m\n * Handle to trTCM instance\n * @param time\n * Current CPU time stamp (measured in CPU cycles)\n * @param pkt_len\n * Length of the current IP packet (measured in bytes)\n * @param pkt_color\n * Input color of the current IP packet\n * @return\n * Color assigned to the current IP packet\n */\nstatic inline enum rte_meter_color\nrte_meter_trtcm_color_aware_check(struct rte_meter_trtcm *m,\n\tuint64_t time,\n\tuint32_t pkt_len,\n\tenum rte_meter_color pkt_color);\n\n/*\n * Inline implementation of run-time methods\n *\n ***/\n\n/* Internal data structure storing the srTCM run-time context per metered traffic flow. */\nstruct rte_meter_srtcm {\n\tuint64_t time; /* Time of latest update of C and E token buckets */\n\tuint64_t tc; /* Number of bytes currently available in the committed (C) token bucket */\n\tuint64_t te; /* Number of bytes currently available in the excess (E) token bucket */\n\tuint64_t cbs; /* Upper limit for C token bucket */\n\tuint64_t ebs; /* Upper limit for E token bucket */\n\tuint64_t cir_period; /* Number of CPU cycles for one update of C and E token buckets */\n\tuint64_t cir_bytes_per_period; /* Number of bytes to add to C and E token buckets on each update */\n};\n\n/* Internal data structure storing the trTCM run-time context per metered traffic flow. */\nstruct rte_meter_trtcm {\n\tuint64_t time_tc; /* Time of latest update of C token bucket */\n\tuint64_t time_tp; /* Time of latest update of E token bucket */\n\tuint64_t tc; /* Number of bytes currently available in the committed (C) token bucket */\n\tuint64_t tp; /* Number of bytes currently available in the peak (P) token bucket */\n\tuint64_t cbs; /* Upper limit for C token bucket */\n\tuint64_t pbs; /* Upper limit for P token bucket */\n\tuint64_t cir_period; /* Number of CPU cycles for one update of C token bucket */\n\tuint64_t cir_bytes_per_period; /* Number of bytes to add to C token bucket on each update */\n\tuint64_t pir_period; /* Number of CPU cycles for one update of P token bucket */\n\tuint64_t pir_bytes_per_period; /* Number of bytes to add to P token bucket on each update */\n};\n\nstatic inline enum rte_meter_color\nrte_meter_srtcm_color_blind_check(struct rte_meter_srtcm *m,\n\tuint64_t time,\n\tuint32_t pkt_len)\n{\n\tuint64_t time_diff, n_periods, tc, te;\n\n\t/* Bucket update */\n\ttime_diff = time - m->time;\n\tn_periods = time_diff / m->cir_period;\n\tm->time += n_periods * m->cir_period;\n\n\ttc = m->tc + n_periods * m->cir_bytes_per_period;\n\tif (tc > m->cbs)\n\t\ttc = m->cbs;\n\n\tte = m->te + n_periods * m->cir_bytes_per_period;\n\tif (te > m->ebs)\n\t\tte = m->ebs;\n\n\t/* Color logic */\n\tif (tc >= pkt_len) {\n\t\tm->tc = tc - pkt_len;\n\t\tm->te = te;\n\t\treturn e_RTE_METER_GREEN;\n\t}\n\n\tif (te >= pkt_len) {\n\t\tm->tc = tc;\n\t\tm->te = te - pkt_len;\n\t\treturn e_RTE_METER_YELLOW;\n\t}\n\n\tm->tc = tc;\n\tm->te = te;\n\treturn e_RTE_METER_RED;\n}\n\nstatic inline enum rte_meter_color\nrte_meter_srtcm_color_aware_check(struct rte_meter_srtcm *m,\n\tuint64_t time,\n\tuint32_t pkt_len,\n\tenum rte_meter_color pkt_color)\n{\n\tuint64_t time_diff, n_periods, tc, te;\n\n\t/* Bucket update */\n\ttime_diff = time - m->time;\n\tn_periods = time_diff / m->cir_period;\n\tm->time += n_periods * m->cir_period;\n\n\ttc = m->tc + n_periods * m->cir_bytes_per_period;\n\tif (tc > m->cbs)\n\t\ttc = m->cbs;\n\n\tte = m->te + n_periods * m->cir_bytes_per_period;\n\tif (te > m->ebs)\n\t\tte = m->ebs;\n\n\t/* Color logic */\n\tif ((pkt_color == e_RTE_METER_GREEN) && (tc >= pkt_len)) {\n\t\tm->tc = tc - pkt_len;\n\t\tm->te = te;\n\t\treturn e_RTE_METER_GREEN;\n\t}\n\n\tif ((pkt_color != e_RTE_METER_RED) && (te >= pkt_len)) {\n\t\tm->tc = tc;\n\t\tm->te = te - pkt_len;\n\t\treturn e_RTE_METER_YELLOW;\n\t}\n\n\tm->tc = tc;\n\tm->te = te;\n\treturn e_RTE_METER_RED;\n}\n\nstatic inline enum rte_meter_color\nrte_meter_trtcm_color_blind_check(struct rte_meter_trtcm *m,\n\tuint64_t time,\n\tuint32_t pkt_len)\n{\n\tuint64_t time_diff_tc, time_diff_tp, n_periods_tc, n_periods_tp, tc, tp;\n\n\t/* Bucket update */\n\ttime_diff_tc = time - m->time_tc;\n\ttime_diff_tp = time - m->time_tp;\n\tn_periods_tc = time_diff_tc / m->cir_period;\n\tn_periods_tp = time_diff_tp / m->pir_period;\n\tm->time_tc += n_periods_tc * m->cir_period;\n\tm->time_tp += n_periods_tp * m->pir_period;\n\n\ttc = m->tc + n_periods_tc * m->cir_bytes_per_period;\n\tif (tc > m->cbs)\n\t\ttc = m->cbs;\n\n\ttp = m->tp + n_periods_tp * m->pir_bytes_per_period;\n\tif (tp > m->pbs)\n\t\ttp = m->pbs;\n\n\t/* Color logic */\n\tif (tp < pkt_len) {\n\t\tm->tc = tc;\n\t\tm->tp = tp;\n\t\treturn e_RTE_METER_RED;\n\t}\n\n\tif (tc < pkt_len) {\n\t\tm->tc = tc;\n\t\tm->tp = tp - pkt_len;\n\t\treturn e_RTE_METER_YELLOW;\n\t}\n\n\tm->tc = tc - pkt_len;\n\tm->tp = tp - pkt_len;\n\treturn e_RTE_METER_GREEN;\n}\n\nstatic inline enum rte_meter_color\nrte_meter_trtcm_color_aware_check(struct rte_meter_trtcm *m,\n\tuint64_t time,\n\tuint32_t pkt_len,\n\tenum rte_meter_color pkt_color)\n{\n\tuint64_t time_diff_tc, time_diff_tp, n_periods_tc, n_periods_tp, tc, tp;\n\n\t/* Bucket update */\n\ttime_diff_tc = time - m->time_tc;\n\ttime_diff_tp = time - m->time_tp;\n\tn_periods_tc = time_diff_tc / m->cir_period;\n\tn_periods_tp = time_diff_tp / m->pir_period;\n\tm->time_tc += n_periods_tc * m->cir_period;\n\tm->time_tp += n_periods_tp * m->pir_period;\n\n\ttc = m->tc + n_periods_tc * m->cir_bytes_per_period;\n\tif (tc > m->cbs)\n\t\ttc = m->cbs;\n\n\ttp = m->tp + n_periods_tp * m->pir_bytes_per_period;\n\tif (tp > m->pbs)\n\t\ttp = m->pbs;\n\n\t/* Color logic */\n\tif ((pkt_color == e_RTE_METER_RED) || (tp < pkt_len)) {\n\t\tm->tc = tc;\n\t\tm->tp = tp;\n\t\treturn e_RTE_METER_RED;\n\t}\n\n\tif ((pkt_color == e_RTE_METER_YELLOW) || (tc < pkt_len)) {\n\t\tm->tc = tc;\n\t\tm->tp = tp - pkt_len;\n\t\treturn e_RTE_METER_YELLOW;\n\t}\n\n\tm->tc = tc - pkt_len;\n\tm->tp = tp - pkt_len;\n\treturn e_RTE_METER_GREEN;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __INCLUDE_RTE_METER_H__ */\n" }, { "path": "lib/librte_net/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3\n\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_NET)-include := rte_ip.h rte_tcp.h rte_udp.h rte_sctp.h rte_icmp.h rte_arp.h\n\n\ninclude $(RTE_SDK)/mk/rte.install.mk\n" }, { "path": "lib/librte_net/rte_arp.h", "content": "/* BSD LICENSE\n *\n * Copyright(c) 2013 6WIND.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_ARP_H_\n#define _RTE_ARP_H_\n\n/**\n * @file\n *\n * ARP-related defines\n */\n\n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * ARP header IPv4 payload.\n */\nstruct arp_ipv4 {\n\tstruct ether_addr arp_sha; /**< sender hardware address */\n\tuint32_t arp_sip; /**< sender IP address */\n\tstruct ether_addr arp_tha; /**< target hardware address */\n\tuint32_t arp_tip; /**< target IP address */\n} __attribute__((__packed__));\n\n/**\n * ARP header.\n */\nstruct arp_hdr {\n\tuint16_t arp_hrd; /* format of hardware address */\n#define ARP_HRD_ETHER 1 /* ARP Ethernet address format */\n\n\tuint16_t arp_pro; /* format of protocol address */\n\tuint8_t arp_hln; /* length of hardware address */\n\tuint8_t arp_pln; /* length of protocol address */\n\tuint16_t arp_op; /* ARP opcode (command) */\n#define\tARP_OP_REQUEST 1 /* request to resolve address */\n#define\tARP_OP_REPLY 2 /* response to previous request */\n#define\tARP_OP_REVREQUEST 3 /* request proto addr given hardware */\n#define\tARP_OP_REVREPLY 4 /* response giving protocol address */\n#define\tARP_OP_INVREQUEST 8 /* request to identify peer */\n#define\tARP_OP_INVREPLY 9 /* response identifying peer */\n\n\tstruct arp_ipv4 arp_data;\n} __attribute__((__packed__));\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_ARP_H_ */\n" }, { "path": "lib/librte_net/rte_icmp.h", "content": "/* BSD LICENSE\n *\n * Copyright(c) 2013 6WIND.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of 6WIND S.A. nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n/*\n * Copyright (c) 1982, 1986, 1990, 1993\n * The Regents of the University of California. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n * must display the following acknowledgement:\n * This product includes software developed by the University of\n * California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * @(#)in.h 8.3 (Berkeley) 1/3/94\n * $FreeBSD: src/sys/netinet/in.h,v 1.82 2003/10/25 09:37:10 ume Exp $\n */\n\n#ifndef _RTE_ICMP_H_\n#define _RTE_ICMP_H_\n\n/**\n * @file\n *\n * ICMP-related defines\n */\n\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * ICMP Header\n */\nstruct icmp_hdr {\n\tuint8_t icmp_type; /* ICMP packet type. */\n\tuint8_t icmp_code; /* ICMP packet code. */\n\tuint16_t icmp_cksum; /* ICMP packet checksum. */\n\tuint16_t icmp_ident; /* ICMP packet identifier. */\n\tuint16_t icmp_seq_nb; /* ICMP packet sequence number. */\n} __attribute__((__packed__));\n\n/* ICMP packet types */\n#define IP_ICMP_ECHO_REPLY 0\n#define IP_ICMP_ECHO_REQUEST 8\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* RTE_ICMP_H_ */\n" }, { "path": "lib/librte_net/rte_ip.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * Copyright 2014 6WIND S.A.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 1982, 1986, 1990, 1993\n * The Regents of the University of California. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n * must display the following acknowledgement:\n * This product includes software developed by the University of\n * California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * @(#)in.h 8.3 (Berkeley) 1/3/94\n * $FreeBSD: src/sys/netinet/in.h,v 1.82 2003/10/25 09:37:10 ume Exp $\n */\n\n#ifndef _RTE_IP_H_\n#define _RTE_IP_H_\n\n/**\n * @file\n *\n * IP-related defines\n */\n\n#include \n#include \n\n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * IPv4 Header\n */\nstruct ipv4_hdr {\n\tuint8_t version_ihl;\t\t/**< version and header length */\n\tuint8_t type_of_service;\t/**< type of service */\n\tuint16_t total_length;\t\t/**< length of packet */\n\tuint16_t packet_id;\t\t/**< packet ID */\n\tuint16_t fragment_offset;\t/**< fragmentation offset */\n\tuint8_t time_to_live;\t\t/**< time to live */\n\tuint8_t next_proto_id;\t\t/**< protocol ID */\n\tuint16_t hdr_checksum;\t\t/**< header checksum */\n\tuint32_t src_addr;\t\t/**< source address */\n\tuint32_t dst_addr;\t\t/**< destination address */\n} __attribute__((__packed__));\n\n/** Create IPv4 address */\n#define IPv4(a,b,c,d) ((uint32_t)(((a) & 0xff) << 24) | \\\n\t\t\t\t\t (((b) & 0xff) << 16) | \\\n\t\t\t\t\t (((c) & 0xff) << 8) | \\\n\t\t\t\t\t ((d) & 0xff))\n\n/** Maximal IPv4 packet length (including a header) */\n#define IPV4_MAX_PKT_LEN 65535\n\n/** Internet header length mask for version_ihl field */\n#define IPV4_HDR_IHL_MASK\t(0x0f)\n/**\n * Internet header length field multiplier (IHL field specifies overall header\n * length in number of 4-byte words)\n */\n#define IPV4_IHL_MULTIPLIER\t(4)\n\n/* Fragment Offset * Flags. */\n#define\tIPV4_HDR_DF_SHIFT\t14\n#define\tIPV4_HDR_MF_SHIFT\t13\n#define\tIPV4_HDR_FO_SHIFT\t3\n\n#define\tIPV4_HDR_DF_FLAG\t(1 << IPV4_HDR_DF_SHIFT)\n#define\tIPV4_HDR_MF_FLAG\t(1 << IPV4_HDR_MF_SHIFT)\n\n#define\tIPV4_HDR_OFFSET_MASK\t((1 << IPV4_HDR_MF_SHIFT) - 1)\n\n#define\tIPV4_HDR_OFFSET_UNITS\t8\n\n/*\n * IPv4 address types\n */\n#define IPV4_ANY ((uint32_t)0x00000000) /**< 0.0.0.0 */\n#define IPV4_LOOPBACK ((uint32_t)0x7f000001) /**< 127.0.0.1 */\n#define IPV4_BROADCAST ((uint32_t)0xe0000000) /**< 224.0.0.0 */\n#define IPV4_ALLHOSTS_GROUP ((uint32_t)0xe0000001) /**< 224.0.0.1 */\n#define IPV4_ALLRTRS_GROUP ((uint32_t)0xe0000002) /**< 224.0.0.2 */\n#define IPV4_MAX_LOCAL_GROUP ((uint32_t)0xe00000ff) /**< 224.0.0.255 */\n\n/*\n * IPv4 Multicast-related macros\n */\n#define IPV4_MIN_MCAST IPv4(224, 0, 0, 0) /**< Minimal IPv4-multicast address */\n#define IPV4_MAX_MCAST IPv4(239, 255, 255, 255) /**< Maximum IPv4 multicast address */\n\n#define IS_IPV4_MCAST(x) \\\n\t((x) >= IPV4_MIN_MCAST && (x) <= IPV4_MAX_MCAST) /**< check if IPv4 address is multicast */\n\n/**\n * @internal Calculate a sum of all words in the buffer.\n * Helper routine for the rte_raw_cksum().\n *\n * @param buf\n * Pointer to the buffer.\n * @param len\n * Length of the buffer.\n * @param sum\n * Initial value of the sum.\n * @return\n * sum += Sum of all words in the buffer.\n */\nstatic inline uint32_t\n__rte_raw_cksum(const void *buf, size_t len, uint32_t sum)\n{\n\t/* workaround gcc strict-aliasing warning */\n\tuintptr_t ptr = (uintptr_t)buf;\n\tconst uint16_t *u16 = (const uint16_t *)ptr;\n\n\twhile (len >= (sizeof(*u16) * 4)) {\n\t\tsum += u16[0];\n\t\tsum += u16[1];\n\t\tsum += u16[2];\n\t\tsum += u16[3];\n\t\tlen -= sizeof(*u16) * 4;\n\t\tu16 += 4;\n\t}\n\twhile (len >= sizeof(*u16)) {\n\t\tsum += *u16;\n\t\tlen -= sizeof(*u16);\n\t\tu16 += 1;\n\t}\n\n\t/* if length is in odd bytes */\n\tif (len == 1)\n\t\tsum += *((const uint8_t *)u16);\n\n\treturn sum;\n}\n\n/**\n * @internal Reduce a sum to the non-complemented checksum.\n * Helper routine for the rte_raw_cksum().\n *\n * @param sum\n * Value of the sum.\n * @return\n * The non-complemented checksum.\n */\nstatic inline uint16_t\n__rte_raw_cksum_reduce(uint32_t sum)\n{\n\tsum = ((sum & 0xffff0000) >> 16) + (sum & 0xffff);\n\tsum = ((sum & 0xffff0000) >> 16) + (sum & 0xffff);\n\treturn (uint16_t)sum;\n}\n\n/**\n * Process the non-complemented checksum of a buffer.\n *\n * @param buf\n * Pointer to the buffer.\n * @param len\n * Length of the buffer.\n * @return\n * The non-complemented checksum.\n */\nstatic inline uint16_t\nrte_raw_cksum(const void *buf, size_t len)\n{\n\tuint32_t sum;\n\n\tsum = __rte_raw_cksum(buf, len, 0);\n\treturn __rte_raw_cksum_reduce(sum);\n}\n\n/**\n * Process the IPv4 checksum of an IPv4 header.\n *\n * The checksum field must be set to 0 by the caller.\n *\n * @param ipv4_hdr\n * The pointer to the contiguous IPv4 header.\n * @return\n * The complemented checksum to set in the IP packet.\n */\nstatic inline uint16_t\nrte_ipv4_cksum(const struct ipv4_hdr *ipv4_hdr)\n{\n\tuint16_t cksum;\n\tcksum = rte_raw_cksum(ipv4_hdr, sizeof(struct ipv4_hdr));\n\treturn (cksum == 0xffff) ? cksum : ~cksum;\n}\n\n/**\n * Process the pseudo-header checksum of an IPv4 header.\n *\n * The checksum field must be set to 0 by the caller.\n *\n * Depending on the ol_flags, the pseudo-header checksum expected by the\n * drivers is not the same. For instance, when TSO is enabled, the IP\n * payload length must not be included in the packet.\n *\n * When ol_flags is 0, it computes the standard pseudo-header checksum.\n *\n * @param ipv4_hdr\n * The pointer to the contiguous IPv4 header.\n * @param ol_flags\n * The ol_flags of the associated mbuf.\n * @return\n * The non-complemented checksum to set in the L4 header.\n */\nstatic inline uint16_t\nrte_ipv4_phdr_cksum(const struct ipv4_hdr *ipv4_hdr, uint64_t ol_flags)\n{\n\tstruct ipv4_psd_header {\n\t\tuint32_t src_addr; /* IP address of source host. */\n\t\tuint32_t dst_addr; /* IP address of destination host. */\n\t\tuint8_t zero; /* zero. */\n\t\tuint8_t proto; /* L4 protocol type. */\n\t\tuint16_t len; /* L4 length. */\n\t} psd_hdr;\n\n\tpsd_hdr.src_addr = ipv4_hdr->src_addr;\n\tpsd_hdr.dst_addr = ipv4_hdr->dst_addr;\n\tpsd_hdr.zero = 0;\n\tpsd_hdr.proto = ipv4_hdr->next_proto_id;\n\tif (ol_flags & PKT_TX_TCP_SEG) {\n\t\tpsd_hdr.len = 0;\n\t} else {\n\t\tpsd_hdr.len = rte_cpu_to_be_16(\n\t\t\t(uint16_t)(rte_be_to_cpu_16(ipv4_hdr->total_length)\n\t\t\t\t- sizeof(struct ipv4_hdr)));\n\t}\n\treturn rte_raw_cksum(&psd_hdr, sizeof(psd_hdr));\n}\n\n/**\n * Process the IPv4 UDP or TCP checksum.\n *\n * The IPv4 header should not contains options. The IP and layer 4\n * checksum must be set to 0 in the packet by the caller.\n *\n * @param ipv4_hdr\n * The pointer to the contiguous IPv4 header.\n * @param l4_hdr\n * The pointer to the beginning of the L4 header.\n * @return\n * The complemented checksum to set in the IP packet.\n */\nstatic inline uint16_t\nrte_ipv4_udptcp_cksum(const struct ipv4_hdr *ipv4_hdr, const void *l4_hdr)\n{\n\tuint32_t cksum;\n\tuint32_t l4_len;\n\n\tl4_len = rte_be_to_cpu_16(ipv4_hdr->total_length) -\n\t\tsizeof(struct ipv4_hdr);\n\n\tcksum = rte_raw_cksum(l4_hdr, l4_len);\n\tcksum += rte_ipv4_phdr_cksum(ipv4_hdr, 0);\n\n\tcksum = ((cksum & 0xffff0000) >> 16) + (cksum & 0xffff);\n\tcksum = (~cksum) & 0xffff;\n\tif (cksum == 0)\n\t\tcksum = 0xffff;\n\n\treturn cksum;\n}\n\n/**\n * IPv6 Header\n */\nstruct ipv6_hdr {\n\tuint32_t vtc_flow; /**< IP version, traffic class & flow label. */\n\tuint16_t payload_len; /**< IP packet length - includes sizeof(ip_header). */\n\tuint8_t proto; /**< Protocol, next header. */\n\tuint8_t hop_limits; /**< Hop limits. */\n\tuint8_t src_addr[16]; /**< IP address of source host. */\n\tuint8_t dst_addr[16]; /**< IP address of destination host(s). */\n} __attribute__((__packed__));\n\n/**\n * Process the pseudo-header checksum of an IPv6 header.\n *\n * Depending on the ol_flags, the pseudo-header checksum expected by the\n * drivers is not the same. For instance, when TSO is enabled, the IPv6\n * payload length must not be included in the packet.\n *\n * When ol_flags is 0, it computes the standard pseudo-header checksum.\n *\n * @param ipv6_hdr\n * The pointer to the contiguous IPv6 header.\n * @param ol_flags\n * The ol_flags of the associated mbuf.\n * @return\n * The non-complemented checksum to set in the L4 header.\n */\nstatic inline uint16_t\nrte_ipv6_phdr_cksum(const struct ipv6_hdr *ipv6_hdr, uint64_t ol_flags)\n{\n\tuint32_t sum;\n\tstruct {\n\t\tuint32_t len; /* L4 length. */\n\t\tuint32_t proto; /* L4 protocol - top 3 bytes must be zero */\n\t} psd_hdr;\n\n\tpsd_hdr.proto = (ipv6_hdr->proto << 24);\n\tif (ol_flags & PKT_TX_TCP_SEG) {\n\t\tpsd_hdr.len = 0;\n\t} else {\n\t\tpsd_hdr.len = ipv6_hdr->payload_len;\n\t}\n\n\tsum = __rte_raw_cksum(ipv6_hdr->src_addr,\n\t\tsizeof(ipv6_hdr->src_addr) + sizeof(ipv6_hdr->dst_addr),\n\t\t0);\n\tsum = __rte_raw_cksum(&psd_hdr, sizeof(psd_hdr), sum);\n\treturn __rte_raw_cksum_reduce(sum);\n}\n\n/**\n * Process the IPv6 UDP or TCP checksum.\n *\n * The IPv4 header should not contains options. The layer 4 checksum\n * must be set to 0 in the packet by the caller.\n *\n * @param ipv6_hdr\n * The pointer to the contiguous IPv6 header.\n * @param l4_hdr\n * The pointer to the beginning of the L4 header.\n * @return\n * The complemented checksum to set in the IP packet.\n */\nstatic inline uint16_t\nrte_ipv6_udptcp_cksum(const struct ipv6_hdr *ipv6_hdr, const void *l4_hdr)\n{\n\tuint32_t cksum;\n\tuint32_t l4_len;\n\n\tl4_len = rte_be_to_cpu_16(ipv6_hdr->payload_len);\n\n\tcksum = rte_raw_cksum(l4_hdr, l4_len);\n\tcksum += rte_ipv6_phdr_cksum(ipv6_hdr, 0);\n\n\tcksum = ((cksum & 0xffff0000) >> 16) + (cksum & 0xffff);\n\tcksum = (~cksum) & 0xffff;\n\tif (cksum == 0)\n\t\tcksum = 0xffff;\n\n\treturn cksum;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_IP_H_ */\n" }, { "path": "lib/librte_net/rte_sctp.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 1982, 1986, 1990, 1993\n * The Regents of the University of California. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n * must display the following acknowledgement:\n * This product includes software developed by the University of\n * California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * @(#)in.h 8.3 (Berkeley) 1/3/94\n * $FreeBSD: src/sys/netinet/in.h,v 1.82 2003/10/25 09:37:10 ume Exp $\n */\n\n/**\n * @file\n *\n * SCTP-related defines\n */\n\n#ifndef _RTE_SCTP_H_\n#define _RTE_SCTP_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n/**\n * SCTP Header\n */\nstruct sctp_hdr {\n\tuint16_t src_port; /**< Source port. */\n\tuint16_t dst_port; /**< Destin port. */\n\tuint32_t tag; /**< Validation tag. */\n\tuint32_t cksum; /**< Checksum. */\n} __attribute__((__packed__));\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* RTE_SCTP_H_ */\n" }, { "path": "lib/librte_net/rte_tcp.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 1982, 1986, 1990, 1993\n * The Regents of the University of California. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n * must display the following acknowledgement:\n * This product includes software developed by the University of\n * California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * @(#)in.h 8.3 (Berkeley) 1/3/94\n * $FreeBSD: src/sys/netinet/in.h,v 1.82 2003/10/25 09:37:10 ume Exp $\n */\n\n#ifndef _RTE_TCP_H_\n#define _RTE_TCP_H_\n\n/**\n * @file\n *\n * TCP-related defines\n */\n\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * TCP Header\n */\nstruct tcp_hdr {\n\tuint16_t src_port; /**< TCP source port. */\n\tuint16_t dst_port; /**< TCP destination port. */\n\tuint32_t sent_seq; /**< TX data sequence number. */\n\tuint32_t recv_ack; /**< RX data acknowledgement sequence number. */\n\tuint8_t data_off; /**< Data offset. */\n\tuint8_t tcp_flags; /**< TCP flags */\n\tuint16_t rx_win; /**< RX flow control window. */\n\tuint16_t cksum; /**< TCP checksum. */\n\tuint16_t tcp_urp; /**< TCP urgent pointer, if any. */\n} __attribute__((__packed__));\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* RTE_TCP_H_ */\n" }, { "path": "lib/librte_net/rte_udp.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Copyright (c) 1982, 1986, 1990, 1993\n * The Regents of the University of California. All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n * 1. Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n * 3. All advertising materials mentioning features or use of this software\n * must display the following acknowledgement:\n * This product includes software developed by the University of\n * California, Berkeley and its contributors.\n * 4. Neither the name of the University nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND\n * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS\n * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY\n * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF\n * SUCH DAMAGE.\n *\n * @(#)in.h 8.3 (Berkeley) 1/3/94\n * $FreeBSD: src/sys/netinet/in.h,v 1.82 2003/10/25 09:37:10 ume Exp $\n */\n\n#ifndef _RTE_UDP_H_\n#define _RTE_UDP_H_\n\n/**\n * @file\n *\n * UDP-related defines\n */\n\n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * UDP Header\n */\nstruct udp_hdr {\n\tuint16_t src_port; /**< UDP source port. */\n\tuint16_t dst_port; /**< UDP destination port. */\n\tuint16_t dgram_len; /**< UDP datagram length */\n\tuint16_t dgram_cksum; /**< UDP datagram checksum */\n} __attribute__((__packed__));\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* RTE_UDP_H_ */\n" }, { "path": "lib/librte_pipeline/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_pipeline.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_pipeline_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_PIPELINE) := rte_pipeline.c\n\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_PIPELINE)-include += rte_pipeline.h\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PIPELINE) := lib/librte_table\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PIPELINE) += lib/librte_port\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_pipeline/rte_pipeline.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_pipeline.h\"\n\n#define RTE_TABLE_INVALID UINT32_MAX\n\n#ifdef RTE_PIPELINE_STATS_COLLECT\n#define RTE_PIPELINE_STATS_ADD(counter, val) \\\n\t({ (counter) += (val); })\n\n#define RTE_PIPELINE_STATS_ADD_M(counter, mask) \\\n\t({ (counter) += __builtin_popcountll(mask); })\n#else\n#define RTE_PIPELINE_STATS_ADD(counter, val)\n#define RTE_PIPELINE_STATS_ADD_M(counter, mask)\n#endif\n\nstruct rte_port_in {\n\t/* Input parameters */\n\tstruct rte_port_in_ops ops;\n\trte_pipeline_port_in_action_handler f_action;\n\tvoid *arg_ah;\n\tuint32_t burst_size;\n\n\t/* The table to which this port is connected */\n\tuint32_t table_id;\n\n\t/* Handle to low-level port */\n\tvoid *h_port;\n\n\t/* List of enabled ports */\n\tstruct rte_port_in *next;\n\n\tuint64_t n_pkts_dropped_by_ah;\n};\n\nstruct rte_port_out {\n\t/* Input parameters */\n\tstruct rte_port_out_ops ops;\n\trte_pipeline_port_out_action_handler f_action;\n\trte_pipeline_port_out_action_handler_bulk f_action_bulk;\n\tvoid *arg_ah;\n\n\t/* Handle to low-level port */\n\tvoid *h_port;\n\n\tuint64_t n_pkts_dropped_by_ah;\n};\n\nstruct rte_table {\n\t/* Input parameters */\n\tstruct rte_table_ops ops;\n\trte_pipeline_table_action_handler_hit f_action_hit;\n\trte_pipeline_table_action_handler_miss f_action_miss;\n\tvoid *arg_ah;\n\tstruct rte_pipeline_table_entry *default_entry;\n\tuint32_t entry_size;\n\n\tuint32_t table_next_id;\n\tuint32_t table_next_id_valid;\n\n\t/* Handle to the low-level table object */\n\tvoid *h_table;\n\n\t/* Stats for this table. */\n\tuint64_t n_pkts_dropped_by_lkp_hit_ah;\n\tuint64_t n_pkts_dropped_by_lkp_miss_ah;\n\tuint64_t n_pkts_dropped_lkp_hit;\n\tuint64_t n_pkts_dropped_lkp_miss;\n};\n\n#define RTE_PIPELINE_MAX_NAME_SZ 124\n\nstruct rte_pipeline {\n\t/* Input parameters */\n\tchar name[RTE_PIPELINE_MAX_NAME_SZ];\n\tint socket_id;\n\tuint32_t offset_port_id;\n\n\t/* Internal tables */\n\tstruct rte_port_in ports_in[RTE_PIPELINE_PORT_IN_MAX];\n\tstruct rte_port_out ports_out[RTE_PIPELINE_PORT_OUT_MAX];\n\tstruct rte_table tables[RTE_PIPELINE_TABLE_MAX];\n\n\t/* Occupancy of internal tables */\n\tuint32_t num_ports_in;\n\tuint32_t num_ports_out;\n\tuint32_t num_tables;\n\n\t/* List of enabled ports */\n\tuint64_t enabled_port_in_mask;\n\tstruct rte_port_in *port_in_first;\n\n\t/* Pipeline run structures */\n\tstruct rte_mbuf *pkts[RTE_PORT_IN_BURST_SIZE_MAX];\n\tstruct rte_pipeline_table_entry *entries[RTE_PORT_IN_BURST_SIZE_MAX];\n\tuint64_t action_mask0[RTE_PIPELINE_ACTIONS];\n\tuint64_t action_mask1[RTE_PIPELINE_ACTIONS];\n} __rte_cache_aligned;\n\nstatic inline uint32_t\nrte_mask_get_next(uint64_t mask, uint32_t pos)\n{\n\tuint64_t mask_rot = (mask << ((63 - pos) & 0x3F)) |\n\t\t\t(mask >> ((pos + 1) & 0x3F));\n\treturn (__builtin_ctzll(mask_rot) - (63 - pos)) & 0x3F;\n}\n\nstatic inline uint32_t\nrte_mask_get_prev(uint64_t mask, uint32_t pos)\n{\n\tuint64_t mask_rot = (mask >> (pos & 0x3F)) |\n\t\t\t(mask << ((64 - pos) & 0x3F));\n\treturn ((63 - __builtin_clzll(mask_rot)) + pos) & 0x3F;\n}\n\nstatic void\nrte_pipeline_table_free(struct rte_table *table);\n\nstatic void\nrte_pipeline_port_in_free(struct rte_port_in *port);\n\nstatic void\nrte_pipeline_port_out_free(struct rte_port_out *port);\n\n/*\n * Pipeline\n *\n */\nstatic int\nrte_pipeline_check_params(struct rte_pipeline_params *params)\n{\n\tif (params == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: Incorrect value for parameter params\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* name */\n\tif (params->name == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: Incorrect value for parameter name\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* socket */\n\tif ((params->socket_id < 0) ||\n\t (params->socket_id >= RTE_MAX_NUMA_NODES)) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: Incorrect value for parameter socket_id\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstruct rte_pipeline *\nrte_pipeline_create(struct rte_pipeline_params *params)\n{\n\tstruct rte_pipeline *p;\n\tint status;\n\n\t/* Check input parameters */\n\tstatus = rte_pipeline_check_params(params);\n\tif (status != 0) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: Pipeline params check failed (%d)\\n\",\n\t\t\t__func__, status);\n\t\treturn NULL;\n\t}\n\n\t/* Allocate memory for the pipeline on requested socket */\n\tp = rte_zmalloc_socket(\"PIPELINE\", sizeof(struct rte_pipeline),\n\t\t\tRTE_CACHE_LINE_SIZE, params->socket_id);\n\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: Pipeline memory allocation failed\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Save input parameters */\n\tsnprintf(p->name, RTE_PIPELINE_MAX_NAME_SZ, \"%s\", params->name);\n\tp->socket_id = params->socket_id;\n\tp->offset_port_id = params->offset_port_id;\n\n\t/* Initialize pipeline internal data structure */\n\tp->num_ports_in = 0;\n\tp->num_ports_out = 0;\n\tp->num_tables = 0;\n\tp->enabled_port_in_mask = 0;\n\tp->port_in_first = NULL;\n\n\treturn p;\n}\n\nint\nrte_pipeline_free(struct rte_pipeline *p)\n{\n\tuint32_t i;\n\n\t/* Check input parameters */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: rte_pipeline parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Free input ports */\n\tfor (i = 0; i < p->num_ports_in; i++) {\n\t\tstruct rte_port_in *port = &p->ports_in[i];\n\n\t\trte_pipeline_port_in_free(port);\n\t}\n\n\t/* Free tables */\n\tfor (i = 0; i < p->num_tables; i++) {\n\t\tstruct rte_table *table = &p->tables[i];\n\n\t\trte_pipeline_table_free(table);\n\t}\n\n\t/* Free output ports */\n\tfor (i = 0; i < p->num_ports_out; i++) {\n\t\tstruct rte_port_out *port = &p->ports_out[i];\n\n\t\trte_pipeline_port_out_free(port);\n\t}\n\n\t/* Free pipeline memory */\n\trte_free(p);\n\n\treturn 0;\n}\n\n/*\n * Table\n *\n */\nstatic int\nrte_table_check_params(struct rte_pipeline *p,\n\t\tstruct rte_pipeline_table_params *params,\n\t\tuint32_t *table_id)\n{\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\tif (params == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: params parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\tif (table_id == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: table_id parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* ops */\n\tif (params->ops == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: params->ops is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (params->ops->f_create == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: f_create function pointer is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (params->ops->f_lookup == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: f_lookup function pointer is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* De we have room for one more table? */\n\tif (p->num_tables == RTE_PIPELINE_TABLE_MAX) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: Incorrect value for num_tables parameter\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nint\nrte_pipeline_table_create(struct rte_pipeline *p,\n\t\tstruct rte_pipeline_table_params *params,\n\t\tuint32_t *table_id)\n{\n\tstruct rte_table *table;\n\tstruct rte_pipeline_table_entry *default_entry;\n\tvoid *h_table;\n\tuint32_t entry_size, id;\n\tint status;\n\n\t/* Check input arguments */\n\tstatus = rte_table_check_params(p, params, table_id);\n\tif (status != 0)\n\t\treturn status;\n\n\tid = p->num_tables;\n\ttable = &p->tables[id];\n\n\t/* Allocate space for the default table entry */\n\tentry_size = sizeof(struct rte_pipeline_table_entry) +\n\t\tparams->action_data_size;\n\tdefault_entry = (struct rte_pipeline_table_entry *) rte_zmalloc_socket(\n\t\t\"PIPELINE\", entry_size, RTE_CACHE_LINE_SIZE, p->socket_id);\n\tif (default_entry == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: Failed to allocate default entry\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Create the table */\n\th_table = params->ops->f_create(params->arg_create, p->socket_id,\n\t\tentry_size);\n\tif (h_table == NULL) {\n\t\trte_free(default_entry);\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: Table creation failed\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Commit current table to the pipeline */\n\tp->num_tables++;\n\t*table_id = id;\n\n\t/* Save input parameters */\n\tmemcpy(&table->ops, params->ops, sizeof(struct rte_table_ops));\n\ttable->f_action_hit = params->f_action_hit;\n\ttable->f_action_miss = params->f_action_miss;\n\ttable->arg_ah = params->arg_ah;\n\ttable->entry_size = entry_size;\n\n\t/* Clear the lookup miss actions (to be set later through API) */\n\ttable->default_entry = default_entry;\n\ttable->default_entry->action = RTE_PIPELINE_ACTION_DROP;\n\n\t/* Initialize table internal data structure */\n\ttable->h_table = h_table;\n\ttable->table_next_id = 0;\n\ttable->table_next_id_valid = 0;\n\n\treturn 0;\n}\n\nvoid\nrte_pipeline_table_free(struct rte_table *table)\n{\n\tif (table->ops.f_free != NULL)\n\t\ttable->ops.f_free(table->h_table);\n\n\trte_free(table->default_entry);\n}\n\nint\nrte_pipeline_table_default_entry_add(struct rte_pipeline *p,\n\tuint32_t table_id,\n\tstruct rte_pipeline_table_entry *default_entry,\n\tstruct rte_pipeline_table_entry **default_entry_ptr)\n{\n\tstruct rte_table *table;\n\n\t/* Check input arguments */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (default_entry == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: default_entry parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (table_id >= p->num_tables) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: table_id %d out of range\\n\", __func__, table_id);\n\t\treturn -EINVAL;\n\t}\n\n\ttable = &p->tables[table_id];\n\n\tif ((default_entry->action == RTE_PIPELINE_ACTION_TABLE) &&\n\t\ttable->table_next_id_valid &&\n\t\t(default_entry->table_id != table->table_next_id)) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: Tree-like topologies not allowed\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Set the lookup miss actions */\n\tif ((default_entry->action == RTE_PIPELINE_ACTION_TABLE) &&\n\t\t(table->table_next_id_valid == 0)) {\n\t\ttable->table_next_id = default_entry->table_id;\n\t\ttable->table_next_id_valid = 1;\n\t}\n\n\tmemcpy(table->default_entry, default_entry, table->entry_size);\n\n\t*default_entry_ptr = table->default_entry;\n\treturn 0;\n}\n\nint\nrte_pipeline_table_default_entry_delete(struct rte_pipeline *p,\n\t\tuint32_t table_id,\n\t\tstruct rte_pipeline_table_entry *entry)\n{\n\tstruct rte_table *table;\n\n\t/* Check input arguments */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: pipeline parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (table_id >= p->num_tables) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: table_id %d out of range\\n\", __func__, table_id);\n\t\treturn -EINVAL;\n\t}\n\n\ttable = &p->tables[table_id];\n\n\t/* Save the current contents of the default entry */\n\tif (entry)\n\t\tmemcpy(entry, table->default_entry, table->entry_size);\n\n\t/* Clear the lookup miss actions */\n\tmemset(table->default_entry, 0, table->entry_size);\n\ttable->default_entry->action = RTE_PIPELINE_ACTION_DROP;\n\n\treturn 0;\n}\n\nint\nrte_pipeline_table_entry_add(struct rte_pipeline *p,\n\t\tuint32_t table_id,\n\t\tvoid *key,\n\t\tstruct rte_pipeline_table_entry *entry,\n\t\tint *key_found,\n\t\tstruct rte_pipeline_table_entry **entry_ptr)\n{\n\tstruct rte_table *table;\n\n\t/* Check input arguments */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (key == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: key parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (entry == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: entry parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (table_id >= p->num_tables) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: table_id %d out of range\\n\", __func__, table_id);\n\t\treturn -EINVAL;\n\t}\n\n\ttable = &p->tables[table_id];\n\n\tif (table->ops.f_add == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: f_add function pointer NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif ((entry->action == RTE_PIPELINE_ACTION_TABLE) &&\n\t\ttable->table_next_id_valid &&\n\t\t(entry->table_id != table->table_next_id)) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: Tree-like topologies not allowed\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Add entry */\n\tif ((entry->action == RTE_PIPELINE_ACTION_TABLE) &&\n\t\t(table->table_next_id_valid == 0)) {\n\t\ttable->table_next_id = entry->table_id;\n\t\ttable->table_next_id_valid = 1;\n\t}\n\n\treturn (table->ops.f_add)(table->h_table, key, (void *) entry,\n\t\tkey_found, (void **) entry_ptr);\n}\n\nint\nrte_pipeline_table_entry_delete(struct rte_pipeline *p,\n\t\tuint32_t table_id,\n\t\tvoid *key,\n\t\tint *key_found,\n\t\tstruct rte_pipeline_table_entry *entry)\n{\n\tstruct rte_table *table;\n\n\t/* Check input arguments */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (key == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: key parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (table_id >= p->num_tables) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: table_id %d out of range\\n\", __func__, table_id);\n\t\treturn -EINVAL;\n\t}\n\n\ttable = &p->tables[table_id];\n\n\tif (table->ops.f_delete == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: f_delete function pointer NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn (table->ops.f_delete)(table->h_table, key, key_found, entry);\n}\n\n/*\n * Port\n *\n */\nstatic int\nrte_pipeline_port_in_check_params(struct rte_pipeline *p,\n\t\tstruct rte_pipeline_port_in_params *params,\n\t\tuint32_t *port_id)\n{\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\tif (params == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: params parameter NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (port_id == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: port_id parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* ops */\n\tif (params->ops == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: params->ops parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (params->ops->f_create == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: f_create function pointer NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (params->ops->f_rx == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: f_rx function pointer NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* burst_size */\n\tif ((params->burst_size == 0) ||\n\t\t(params->burst_size > RTE_PORT_IN_BURST_SIZE_MAX)) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: invalid value for burst_size\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Do we have room for one more port? */\n\tif (p->num_ports_in == RTE_PIPELINE_PORT_IN_MAX) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: invalid value for num_ports_in\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_pipeline_port_out_check_params(struct rte_pipeline *p,\n\t\tstruct rte_pipeline_port_out_params *params,\n\t\tuint32_t *port_id)\n{\n\trte_pipeline_port_out_action_handler f_ah;\n\trte_pipeline_port_out_action_handler_bulk f_ah_bulk;\n\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (params == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: params parameter NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (port_id == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: port_id parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* ops */\n\tif (params->ops == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: params->ops parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (params->ops->f_create == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: f_create function pointer NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (params->ops->f_tx == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\t\"%s: f_tx function pointer NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (params->ops->f_tx_bulk == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: f_tx_bulk function pointer NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tf_ah = params->f_action;\n\tf_ah_bulk = params->f_action_bulk;\n\tif (((f_ah != NULL) && (f_ah_bulk == NULL)) ||\n\t ((f_ah == NULL) && (f_ah_bulk != NULL))) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: Action handlers have to be either\"\n\t\t\t\"both enabled or both disabled\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Do we have room for one more port? */\n\tif (p->num_ports_out == RTE_PIPELINE_PORT_OUT_MAX) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: invalid value for num_ports_out\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nint\nrte_pipeline_port_in_create(struct rte_pipeline *p,\n\t\tstruct rte_pipeline_port_in_params *params,\n\t\tuint32_t *port_id)\n{\n\tstruct rte_port_in *port;\n\tvoid *h_port;\n\tuint32_t id;\n\tint status;\n\n\t/* Check input arguments */\n\tstatus = rte_pipeline_port_in_check_params(p, params, port_id);\n\tif (status != 0)\n\t\treturn status;\n\n\tid = p->num_ports_in;\n\tport = &p->ports_in[id];\n\n\t/* Create the port */\n\th_port = params->ops->f_create(params->arg_create, p->socket_id);\n\tif (h_port == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: Port creation failed\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Commit current table to the pipeline */\n\tp->num_ports_in++;\n\t*port_id = id;\n\n\t/* Save input parameters */\n\tmemcpy(&port->ops, params->ops, sizeof(struct rte_port_in_ops));\n\tport->f_action = params->f_action;\n\tport->arg_ah = params->arg_ah;\n\tport->burst_size = params->burst_size;\n\n\t/* Initialize port internal data structure */\n\tport->table_id = RTE_TABLE_INVALID;\n\tport->h_port = h_port;\n\tport->next = NULL;\n\n\treturn 0;\n}\n\nvoid\nrte_pipeline_port_in_free(struct rte_port_in *port)\n{\n\tif (port->ops.f_free != NULL)\n\t\tport->ops.f_free(port->h_port);\n}\n\nint\nrte_pipeline_port_out_create(struct rte_pipeline *p,\n\t\tstruct rte_pipeline_port_out_params *params,\n\t\tuint32_t *port_id)\n{\n\tstruct rte_port_out *port;\n\tvoid *h_port;\n\tuint32_t id;\n\tint status;\n\n\t/* Check input arguments */\n\tstatus = rte_pipeline_port_out_check_params(p, params, port_id);\n\tif (status != 0)\n\t\treturn status;\n\n\tid = p->num_ports_out;\n\tport = &p->ports_out[id];\n\n\t/* Create the port */\n\th_port = params->ops->f_create(params->arg_create, p->socket_id);\n\tif (h_port == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: Port creation failed\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Commit current table to the pipeline */\n\tp->num_ports_out++;\n\t*port_id = id;\n\n\t/* Save input parameters */\n\tmemcpy(&port->ops, params->ops, sizeof(struct rte_port_out_ops));\n\tport->f_action = params->f_action;\n\tport->f_action_bulk = params->f_action_bulk;\n\tport->arg_ah = params->arg_ah;\n\n\t/* Initialize port internal data structure */\n\tport->h_port = h_port;\n\n\treturn 0;\n}\n\nvoid\nrte_pipeline_port_out_free(struct rte_port_out *port)\n{\n\tif (port->ops.f_free != NULL)\n\t\tport->ops.f_free(port->h_port);\n}\n\nint\nrte_pipeline_port_in_connect_to_table(struct rte_pipeline *p,\n\t\tuint32_t port_id,\n\t\tuint32_t table_id)\n{\n\tstruct rte_port_in *port;\n\n\t/* Check input arguments */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (port_id >= p->num_ports_in) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: port IN ID %u is out of range\\n\",\n\t\t\t__func__, port_id);\n\t\treturn -EINVAL;\n\t}\n\n\tif (table_id >= p->num_tables) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: Table ID %u is out of range\\n\",\n\t\t\t__func__, table_id);\n\t\treturn -EINVAL;\n\t}\n\n\tport = &p->ports_in[port_id];\n\tport->table_id = table_id;\n\n\treturn 0;\n}\n\nint\nrte_pipeline_port_in_enable(struct rte_pipeline *p, uint32_t port_id)\n{\n\tstruct rte_port_in *port, *port_prev, *port_next;\n\tstruct rte_port_in *port_first, *port_last;\n\tuint64_t port_mask;\n\tuint32_t port_prev_id, port_next_id, port_first_id, port_last_id;\n\n\t/* Check input arguments */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (port_id >= p->num_ports_in) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: port IN ID %u is out of range\\n\",\n\t\t\t__func__, port_id);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Return if current input port is already enabled */\n\tport_mask = 1LLU << port_id;\n\tif (p->enabled_port_in_mask & port_mask)\n\t\treturn 0;\n\n\tp->enabled_port_in_mask |= port_mask;\n\n\t/* Add current input port to the pipeline chain of enabled ports */\n\tport_prev_id = rte_mask_get_prev(p->enabled_port_in_mask, port_id);\n\tport_next_id = rte_mask_get_next(p->enabled_port_in_mask, port_id);\n\n\tport_prev = &p->ports_in[port_prev_id];\n\tport_next = &p->ports_in[port_next_id];\n\tport = &p->ports_in[port_id];\n\n\tport_prev->next = port;\n\tport->next = port_next;\n\n\t/* Update the first and last input ports in the chain */\n\tport_first_id = __builtin_ctzll(p->enabled_port_in_mask);\n\tport_last_id = 63 - __builtin_clzll(p->enabled_port_in_mask);\n\n\tport_first = &p->ports_in[port_first_id];\n\tport_last = &p->ports_in[port_last_id];\n\n\tp->port_in_first = port_first;\n\tport_last->next = NULL;\n\n\treturn 0;\n}\n\nint\nrte_pipeline_port_in_disable(struct rte_pipeline *p, uint32_t port_id)\n{\n\tstruct rte_port_in *port_prev, *port_next, *port_first, *port_last;\n\tuint64_t port_mask;\n\tuint32_t port_prev_id, port_next_id, port_first_id, port_last_id;\n\n\t/* Check input arguments */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter NULL\\n\",\n\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (port_id >= p->num_ports_in) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: port IN ID %u is out of range\\n\",\n\t\t\t__func__, port_id);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Return if current input port is already disabled */\n\tport_mask = 1LLU << port_id;\n\tif ((p->enabled_port_in_mask & port_mask) == 0)\n\t\treturn 0;\n\n\t/* Return if no other enabled ports */\n\tif (__builtin_popcountll(p->enabled_port_in_mask) == 1) {\n\t\tp->enabled_port_in_mask &= ~port_mask;\n\t\tp->port_in_first = NULL;\n\n\t\treturn 0;\n\t}\n\n\t/* Add current input port to the pipeline chain of enabled ports */\n\tport_prev_id = rte_mask_get_prev(p->enabled_port_in_mask, port_id);\n\tport_next_id = rte_mask_get_next(p->enabled_port_in_mask, port_id);\n\n\tport_prev = &p->ports_in[port_prev_id];\n\tport_next = &p->ports_in[port_next_id];\n\n\tport_prev->next = port_next;\n\tp->enabled_port_in_mask &= ~port_mask;\n\n\t/* Update the first and last input ports in the chain */\n\tport_first_id = __builtin_ctzll(p->enabled_port_in_mask);\n\tport_last_id = 63 - __builtin_clzll(p->enabled_port_in_mask);\n\n\tport_first = &p->ports_in[port_first_id];\n\tport_last = &p->ports_in[port_last_id];\n\n\tp->port_in_first = port_first;\n\tport_last->next = NULL;\n\n\treturn 0;\n}\n\n/*\n * Pipeline run-time\n *\n */\nint\nrte_pipeline_check(struct rte_pipeline *p)\n{\n\tuint32_t port_in_id;\n\n\t/* Check input arguments */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Check that pipeline has at least one input port, one table and one\n\toutput port */\n\tif (p->num_ports_in == 0) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: must have at least 1 input port\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\tif (p->num_tables == 0) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: must have at least 1 table\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\tif (p->num_ports_out == 0) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: must have at least 1 output port\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Check that all input ports are connected */\n\tfor (port_in_id = 0; port_in_id < p->num_ports_in; port_in_id++) {\n\t\tstruct rte_port_in *port_in = &p->ports_in[port_in_id];\n\n\t\tif (port_in->table_id == RTE_TABLE_INVALID) {\n\t\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\t\"%s: Port IN ID %u is not connected\\n\",\n\t\t\t\t__func__, port_in_id);\n\t\t\treturn -EINVAL;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic inline void\nrte_pipeline_compute_masks(struct rte_pipeline *p, uint64_t pkts_mask)\n{\n\tp->action_mask1[RTE_PIPELINE_ACTION_DROP] = 0;\n\tp->action_mask1[RTE_PIPELINE_ACTION_PORT] = 0;\n\tp->action_mask1[RTE_PIPELINE_ACTION_PORT_META] = 0;\n\tp->action_mask1[RTE_PIPELINE_ACTION_TABLE] = 0;\n\n\tif ((pkts_mask & (pkts_mask + 1)) == 0) {\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_mask);\n\t\tuint32_t i;\n\n\t\tfor (i = 0; i < n_pkts; i++) {\n\t\t\tuint64_t pkt_mask = 1LLU << i;\n\t\t\tuint32_t pos = p->entries[i]->action;\n\n\t\t\tp->action_mask1[pos] |= pkt_mask;\n\t\t}\n\t} else {\n\t\tuint32_t i;\n\n\t\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++) {\n\t\t\tuint64_t pkt_mask = 1LLU << i;\n\t\t\tuint32_t pos;\n\n\t\t\tif ((pkt_mask & pkts_mask) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tpos = p->entries[i]->action;\n\t\t\tp->action_mask1[pos] |= pkt_mask;\n\t\t}\n\t}\n}\n\nstatic inline void\nrte_pipeline_action_handler_port_bulk(struct rte_pipeline *p,\n\t\tuint64_t pkts_mask, uint32_t port_id)\n{\n\tstruct rte_port_out *port_out = &p->ports_out[port_id];\n\n\t/* Output port user actions */\n\tif (port_out->f_action_bulk != NULL) {\n\t\tuint64_t mask = pkts_mask;\n\n\t\tport_out->f_action_bulk(p->pkts, &pkts_mask, port_out->arg_ah);\n\t\tp->action_mask0[RTE_PIPELINE_ACTION_DROP] |= pkts_mask ^ mask;\n\t\tRTE_PIPELINE_STATS_ADD_M(port_out->n_pkts_dropped_by_ah,\n\t\t\t\tpkts_mask ^ mask);\n\t}\n\n\t/* Output port TX */\n\tif (pkts_mask != 0)\n\t\tport_out->ops.f_tx_bulk(port_out->h_port, p->pkts, pkts_mask);\n}\n\nstatic inline void\nrte_pipeline_action_handler_port(struct rte_pipeline *p, uint64_t pkts_mask)\n{\n\tif ((pkts_mask & (pkts_mask + 1)) == 0) {\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_mask);\n\t\tuint32_t i;\n\n\t\tfor (i = 0; i < n_pkts; i++) {\n\t\t\tstruct rte_mbuf *pkt = p->pkts[i];\n\t\t\tuint32_t port_out_id = p->entries[i]->port_id;\n\t\t\tstruct rte_port_out *port_out =\n\t\t\t\t&p->ports_out[port_out_id];\n\n\t\t\t/* Output port user actions */\n\t\t\tif (port_out->f_action == NULL) /* Output port TX */\n\t\t\t\tport_out->ops.f_tx(port_out->h_port, pkt);\n\t\t\telse {\n\t\t\t\tuint64_t pkt_mask = 1LLU;\n\n\t\t\t\tport_out->f_action(pkt, &pkt_mask,\n\t\t\t\t\tport_out->arg_ah);\n\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_DROP] |=\n\t\t\t\t\t(pkt_mask ^ 1LLU) << i;\n\n\t\t\t\tRTE_PIPELINE_STATS_ADD(port_out->n_pkts_dropped_by_ah,\n\t\t\t\t\t\tpkt_mask ^ 1LLU);\n\n\t\t\t\t/* Output port TX */\n\t\t\t\tif (pkt_mask != 0)\n\t\t\t\t\tport_out->ops.f_tx(port_out->h_port,\n\t\t\t\t\t\tpkt);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tuint32_t i;\n\n\t\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++) {\n\t\t\tuint64_t pkt_mask = 1LLU << i;\n\t\t\tstruct rte_mbuf *pkt;\n\t\t\tstruct rte_port_out *port_out;\n\t\t\tuint32_t port_out_id;\n\n\t\t\tif ((pkt_mask & pkts_mask) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tpkt = p->pkts[i];\n\t\t\tport_out_id = p->entries[i]->port_id;\n\t\t\tport_out = &p->ports_out[port_out_id];\n\n\t\t\t/* Output port user actions */\n\t\t\tif (port_out->f_action == NULL) /* Output port TX */\n\t\t\t\tport_out->ops.f_tx(port_out->h_port, pkt);\n\t\t\telse {\n\t\t\t\tpkt_mask = 1LLU;\n\n\t\t\t\tport_out->f_action(pkt, &pkt_mask,\n\t\t\t\t\tport_out->arg_ah);\n\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_DROP] |=\n\t\t\t\t\t(pkt_mask ^ 1LLU) << i;\n\n\t\t\t\tRTE_PIPELINE_STATS_ADD(port_out->n_pkts_dropped_by_ah,\n\t\t\t\t\t\tpkt_mask ^ 1LLU);\n\n\t\t\t\t/* Output port TX */\n\t\t\t\tif (pkt_mask != 0)\n\t\t\t\t\tport_out->ops.f_tx(port_out->h_port,\n\t\t\t\t\t\tpkt);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic inline void\nrte_pipeline_action_handler_port_meta(struct rte_pipeline *p,\n\tuint64_t pkts_mask)\n{\n\tif ((pkts_mask & (pkts_mask + 1)) == 0) {\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_mask);\n\t\tuint32_t i;\n\n\t\tfor (i = 0; i < n_pkts; i++) {\n\t\t\tstruct rte_mbuf *pkt = p->pkts[i];\n\t\t\tuint32_t port_out_id =\n\t\t\t\tRTE_MBUF_METADATA_UINT32(pkt,\n\t\t\t\t\tp->offset_port_id);\n\t\t\tstruct rte_port_out *port_out = &p->ports_out[\n\t\t\t\tport_out_id];\n\n\t\t\t/* Output port user actions */\n\t\t\tif (port_out->f_action == NULL) /* Output port TX */\n\t\t\t\tport_out->ops.f_tx(port_out->h_port, pkt);\n\t\t\telse {\n\t\t\t\tuint64_t pkt_mask = 1LLU;\n\n\t\t\t\tport_out->f_action(pkt, &pkt_mask,\n\t\t\t\t\tport_out->arg_ah);\n\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_DROP] |=\n\t\t\t\t\t(pkt_mask ^ 1LLU) << i;\n\n\t\t\t\tRTE_PIPELINE_STATS_ADD(port_out->n_pkts_dropped_by_ah,\n\t\t\t\t\t\tpkt_mask ^ 1ULL);\n\n\t\t\t\t/* Output port TX */\n\t\t\t\tif (pkt_mask != 0)\n\t\t\t\t\tport_out->ops.f_tx(port_out->h_port,\n\t\t\t\t\t\tpkt);\n\t\t\t}\n\t\t}\n\t} else {\n\t\tuint32_t i;\n\n\t\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++) {\n\t\t\tuint64_t pkt_mask = 1LLU << i;\n\t\t\tstruct rte_mbuf *pkt;\n\t\t\tstruct rte_port_out *port_out;\n\t\t\tuint32_t port_out_id;\n\n\t\t\tif ((pkt_mask & pkts_mask) == 0)\n\t\t\t\tcontinue;\n\n\t\t\tpkt = p->pkts[i];\n\t\t\tport_out_id = RTE_MBUF_METADATA_UINT32(pkt,\n\t\t\t\tp->offset_port_id);\n\t\t\tport_out = &p->ports_out[port_out_id];\n\n\t\t\t/* Output port user actions */\n\t\t\tif (port_out->f_action == NULL) /* Output port TX */\n\t\t\t\tport_out->ops.f_tx(port_out->h_port, pkt);\n\t\t\telse {\n\t\t\t\tpkt_mask = 1LLU;\n\n\t\t\t\tport_out->f_action(pkt, &pkt_mask,\n\t\t\t\t\tport_out->arg_ah);\n\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_DROP] |=\n\t\t\t\t\t(pkt_mask ^ 1LLU) << i;\n\n\t\t\t\tRTE_PIPELINE_STATS_ADD(port_out->n_pkts_dropped_by_ah,\n\t\t\t\t\t\tpkt_mask ^ 1ULL);\n\n\t\t\t\t/* Output port TX */\n\t\t\t\tif (pkt_mask != 0)\n\t\t\t\t\tport_out->ops.f_tx(port_out->h_port,\n\t\t\t\t\t\tpkt);\n\t\t\t}\n\t\t}\n\t}\n}\n\nstatic inline void\nrte_pipeline_action_handler_drop(struct rte_pipeline *p, uint64_t pkts_mask)\n{\n\tif ((pkts_mask & (pkts_mask + 1)) == 0) {\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_mask);\n\t\tuint32_t i;\n\n\t\tfor (i = 0; i < n_pkts; i++)\n\t\t\trte_pktmbuf_free(p->pkts[i]);\n\t} else {\n\t\tuint32_t i;\n\n\t\tfor (i = 0; i < RTE_PORT_IN_BURST_SIZE_MAX; i++) {\n\t\t\tuint64_t pkt_mask = 1LLU << i;\n\n\t\t\tif ((pkt_mask & pkts_mask) == 0)\n\t\t\t\tcontinue;\n\n\t\t\trte_pktmbuf_free(p->pkts[i]);\n\t\t}\n\t}\n}\n\nint\nrte_pipeline_run(struct rte_pipeline *p)\n{\n\tstruct rte_port_in *port_in;\n\n\tfor (port_in = p->port_in_first; port_in != NULL;\n\t\tport_in = port_in->next) {\n\t\tuint64_t pkts_mask;\n\t\tuint32_t n_pkts, table_id;\n\n\t\t/* Input port RX */\n\t\tn_pkts = port_in->ops.f_rx(port_in->h_port, p->pkts,\n\t\t\tport_in->burst_size);\n\t\tif (n_pkts == 0)\n\t\t\tcontinue;\n\n\t\tpkts_mask = RTE_LEN2MASK(n_pkts, uint64_t);\n\t\tp->action_mask0[RTE_PIPELINE_ACTION_DROP] = 0;\n\t\tp->action_mask0[RTE_PIPELINE_ACTION_PORT] = 0;\n\t\tp->action_mask0[RTE_PIPELINE_ACTION_PORT_META] = 0;\n\t\tp->action_mask0[RTE_PIPELINE_ACTION_TABLE] = 0;\n\n\t\t/* Input port user actions */\n\t\tif (port_in->f_action != NULL) {\n\t\t\tuint64_t mask = pkts_mask;\n\n\t\t\tport_in->f_action(p->pkts, n_pkts, &pkts_mask, port_in->arg_ah);\n\t\t\tmask ^= pkts_mask;\n\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_DROP] |= mask;\n\t\t\tRTE_PIPELINE_STATS_ADD_M(port_in->n_pkts_dropped_by_ah, mask);\n\t\t}\n\n\t\t/* Table */\n\t\tfor (table_id = port_in->table_id; pkts_mask != 0; ) {\n\t\t\tstruct rte_table *table;\n\t\t\tuint64_t lookup_hit_mask, lookup_miss_mask;\n\n\t\t\t/* Lookup */\n\t\t\ttable = &p->tables[table_id];\n\t\t\ttable->ops.f_lookup(table->h_table, p->pkts, pkts_mask,\n\t\t\t\t\t&lookup_hit_mask, (void **) p->entries);\n\t\t\tlookup_miss_mask = pkts_mask & (~lookup_hit_mask);\n\n\t\t\t/* Lookup miss */\n\t\t\tif (lookup_miss_mask != 0) {\n\t\t\t\tstruct rte_pipeline_table_entry *default_entry =\n\t\t\t\t\ttable->default_entry;\n\n\t\t\t\t/* Table user actions */\n\t\t\t\tif (table->f_action_miss != NULL) {\n\t\t\t\t\tuint64_t mask = lookup_miss_mask;\n\n\t\t\t\t\ttable->f_action_miss(p->pkts,\n\t\t\t\t\t\t&lookup_miss_mask,\n\t\t\t\t\t\tdefault_entry, table->arg_ah);\n\t\t\t\t\tmask ^= lookup_miss_mask;\n\t\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_DROP] |= mask;\n\t\t\t\t\tRTE_PIPELINE_STATS_ADD_M(\n\t\t\t\t\t\ttable->n_pkts_dropped_by_lkp_miss_ah, mask);\n\t\t\t\t}\n\n\t\t\t\t/* Table reserved actions */\n\t\t\t\tif ((default_entry->action ==\n\t\t\t\t\tRTE_PIPELINE_ACTION_PORT) &&\n\t\t\t\t\t(lookup_miss_mask != 0))\n\t\t\t\t\trte_pipeline_action_handler_port_bulk(p,\n\t\t\t\t\t\tlookup_miss_mask,\n\t\t\t\t\t\tdefault_entry->port_id);\n\t\t\t\telse {\n\t\t\t\t\tuint32_t pos = default_entry->action;\n\n\t\t\t\t\tp->action_mask0[pos] = lookup_miss_mask;\n\t\t\t\t\tif (pos == RTE_PIPELINE_ACTION_DROP) {\n\t\t\t\t\t\tRTE_PIPELINE_STATS_ADD_M(table->n_pkts_dropped_lkp_miss,\n\t\t\t\t\t\t\tlookup_miss_mask);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Lookup hit */\n\t\t\tif (lookup_hit_mask != 0) {\n\t\t\t\t/* Table user actions */\n\t\t\t\tif (table->f_action_hit != NULL) {\n\t\t\t\t\tuint64_t mask = lookup_hit_mask;\n\n\t\t\t\t\ttable->f_action_hit(p->pkts,\n\t\t\t\t\t\t&lookup_hit_mask,\n\t\t\t\t\t\tp->entries, table->arg_ah);\n\t\t\t\t\tmask ^= lookup_hit_mask;\n\t\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_DROP] |= mask;\n\t\t\t\t\tRTE_PIPELINE_STATS_ADD_M(\n\t\t\t\t\t\ttable->n_pkts_dropped_by_lkp_hit_ah, mask);\n\t\t\t\t}\n\n\t\t\t\t/* Table reserved actions */\n\t\t\t\trte_pipeline_compute_masks(p, lookup_hit_mask);\n\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_DROP] |=\n\t\t\t\t\tp->action_mask1[\n\t\t\t\t\t\tRTE_PIPELINE_ACTION_DROP];\n\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_PORT] |=\n\t\t\t\t\tp->action_mask1[\n\t\t\t\t\t\tRTE_PIPELINE_ACTION_PORT];\n\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_PORT_META] |=\n\t\t\t\t\tp->action_mask1[\n\t\t\t\t\t\tRTE_PIPELINE_ACTION_PORT_META];\n\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_TABLE] |=\n\t\t\t\t\tp->action_mask1[\n\t\t\t\t\t\tRTE_PIPELINE_ACTION_TABLE];\n\n\t\t\t\tRTE_PIPELINE_STATS_ADD_M(table->n_pkts_dropped_lkp_hit,\n\t\t\t\t\t\tp->action_mask1[RTE_PIPELINE_ACTION_DROP]);\n\t\t\t}\n\n\t\t\t/* Prepare for next iteration */\n\t\t\tpkts_mask = p->action_mask0[RTE_PIPELINE_ACTION_TABLE];\n\t\t\ttable_id = table->table_next_id;\n\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_TABLE] = 0;\n\t\t}\n\n\t\t/* Table reserved action PORT */\n\t\trte_pipeline_action_handler_port(p,\n\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_PORT]);\n\n\t\t/* Table reserved action PORT META */\n\t\trte_pipeline_action_handler_port_meta(p,\n\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_PORT_META]);\n\n\t\t/* Table reserved action DROP */\n\t\trte_pipeline_action_handler_drop(p,\n\t\t\t\tp->action_mask0[RTE_PIPELINE_ACTION_DROP]);\n\t}\n\n\treturn 0;\n}\n\nint\nrte_pipeline_flush(struct rte_pipeline *p)\n{\n\tuint32_t port_id;\n\n\t/* Check input arguments */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tfor (port_id = 0; port_id < p->num_ports_out; port_id++) {\n\t\tstruct rte_port_out *port = &p->ports_out[port_id];\n\n\t\tif (port->ops.f_flush != NULL)\n\t\t\tport->ops.f_flush(port->h_port);\n\t}\n\n\treturn 0;\n}\n\nint\nrte_pipeline_port_out_packet_insert(struct rte_pipeline *p,\n\t\tuint32_t port_id, struct rte_mbuf *pkt)\n{\n\tstruct rte_port_out *port_out = &p->ports_out[port_id];\n\n\t/* Output port user actions */\n\tif (port_out->f_action == NULL)\n\t\tport_out->ops.f_tx(port_out->h_port, pkt); /* Output port TX */\n\telse {\n\t\tuint64_t pkt_mask = 1LLU;\n\n\t\tport_out->f_action(pkt, &pkt_mask, port_out->arg_ah);\n\n\t\tif (pkt_mask != 0) /* Output port TX */\n\t\t\tport_out->ops.f_tx(port_out->h_port, pkt);\n\t\telse {\n\t\t\trte_pktmbuf_free(pkt);\n\t\t\tRTE_PIPELINE_STATS_ADD(port_out->n_pkts_dropped_by_ah, 1);\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nint rte_pipeline_port_in_stats_read(struct rte_pipeline *p, uint32_t port_id,\n\tstruct rte_pipeline_port_in_stats *stats, int clear)\n{\n\tstruct rte_port_in *port;\n\tint retval;\n\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (port_id >= p->num_ports_in) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: port IN ID %u is out of range\\n\",\n\t\t\t__func__, port_id);\n\t\treturn -EINVAL;\n\t}\n\n\tport = &p->ports_in[port_id];\n\n\tif (port->ops.f_stats != NULL) {\n\t\tretval = port->ops.f_stats(port->h_port, &stats->stats, clear);\n\t\tif (retval)\n\t\t\treturn retval;\n\t} else if (stats != NULL)\n\t\tmemset(&stats->stats, 0, sizeof(stats->stats));\n\n\tif (stats != NULL)\n\t\tstats->n_pkts_dropped_by_ah = port->n_pkts_dropped_by_ah;\n\n\tif (clear != 0)\n\t\tport->n_pkts_dropped_by_ah = 0;\n\n\treturn 0;\n}\n\nint rte_pipeline_port_out_stats_read(struct rte_pipeline *p, uint32_t port_id,\n\tstruct rte_pipeline_port_out_stats *stats, int clear)\n{\n\tstruct rte_port_out *port;\n\tint retval;\n\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (port_id >= p->num_ports_out) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\"%s: port OUT ID %u is out of range\\n\", __func__, port_id);\n\t\treturn -EINVAL;\n\t}\n\n\tport = &p->ports_out[port_id];\n\tif (port->ops.f_stats != NULL) {\n\t\tretval = port->ops.f_stats(port->h_port, &stats->stats, clear);\n\t\tif (retval != 0)\n\t\t\treturn retval;\n\t} else if (stats != NULL)\n\t\tmemset(&stats->stats, 0, sizeof(stats->stats));\n\n\tif (stats != NULL)\n\t\tstats->n_pkts_dropped_by_ah = port->n_pkts_dropped_by_ah;\n\n\tif (clear != 0)\n\t\tport->n_pkts_dropped_by_ah = 0;\n\n\treturn 0;\n}\n\nint rte_pipeline_table_stats_read(struct rte_pipeline *p, uint32_t table_id,\n\tstruct rte_pipeline_table_stats *stats, int clear)\n{\n\tstruct rte_table *table;\n\tint retval;\n\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, PIPELINE, \"%s: pipeline parameter NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif (table_id >= p->num_tables) {\n\t\tRTE_LOG(ERR, PIPELINE,\n\t\t\t\t\"%s: table %u is out of range\\n\", __func__, table_id);\n\t\treturn -EINVAL;\n\t}\n\n\ttable = &p->tables[table_id];\n\tif (table->ops.f_stats != NULL) {\n\t\tretval = table->ops.f_stats(table->h_table, &stats->stats, clear);\n\t\tif (retval != 0)\n\t\t\treturn retval;\n\t} else if (stats != NULL)\n\t\tmemset(&stats->stats, 0, sizeof(stats->stats));\n\n\tif (stats != NULL) {\n\t\tstats->n_pkts_dropped_by_lkp_hit_ah =\n\t\t\ttable->n_pkts_dropped_by_lkp_hit_ah;\n\t\tstats->n_pkts_dropped_by_lkp_miss_ah =\n\t\t\ttable->n_pkts_dropped_by_lkp_miss_ah;\n\t\tstats->n_pkts_dropped_lkp_hit = table->n_pkts_dropped_lkp_hit;\n\t\tstats->n_pkts_dropped_lkp_miss = table->n_pkts_dropped_lkp_miss;\n\t}\n\n\tif (clear != 0) {\n\t\ttable->n_pkts_dropped_by_lkp_hit_ah = 0;\n\t\ttable->n_pkts_dropped_by_lkp_miss_ah = 0;\n\t\ttable->n_pkts_dropped_lkp_hit = 0;\n\t\ttable->n_pkts_dropped_lkp_miss = 0;\n\t}\n\n\treturn 0;\n}\n\n" }, { "path": "lib/librte_pipeline/rte_pipeline.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_PIPELINE_H__\n#define __INCLUDE_RTE_PIPELINE_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Pipeline\n *\n * This tool is part of the Intel DPDK Packet Framework tool suite and provides\n * a standard methodology (logically similar to OpenFlow) for rapid development\n * of complex packet processing pipelines out of ports, tables and actions.\n *\n * Basic operation. A pipeline is constructed by connecting its input\n * ports to its output ports through a chain of lookup tables. As result of\n * lookup operation into the current table, one of the table entries (or the\n * default table entry, in case of lookup miss) is identified to provide the\n * actions to be executed on the current packet and the associated action\n * meta-data. The behavior of user actions is defined through the configurable\n * table action handler, while the reserved actions define the next hop for the\n * current packet (either another table, an output port or packet drop) and are\n * handled transparently by the framework.\n *\n * Initialization and run-time flows. Once all the pipeline elements\n * (input ports, tables, output ports) have been created, input ports connected\n * to tables, table action handlers configured, tables populated with the\n * initial set of entries (actions and action meta-data) and input ports\n * enabled, the pipeline runs automatically, pushing packets from input ports\n * to tables and output ports. At each table, the identified user actions are\n * being executed, resulting in action meta-data (stored in the table entry)\n * and packet meta-data (stored with the packet descriptor) being updated. The\n * pipeline tables can have further updates and input ports can be disabled or\n * enabled later on as required.\n *\n * Multi-core scaling. Typically, each CPU core will run its own\n * pipeline instance. Complex application-level pipelines can be implemented by\n * interconnecting multiple CPU core-level pipelines in tree-like topologies,\n * as the same port devices (e.g. SW rings) can serve as output ports for the\n * pipeline running on CPU core A, as well as input ports for the pipeline\n * running on CPU core B. This approach enables the application development\n * using the pipeline (CPU cores connected serially), cluster/run-to-completion\n * (CPU cores connected in parallel) or mixed (pipeline of CPU core clusters)\n * programming models.\n *\n * Thread safety. It is possible to have multiple pipelines running on\n * the same CPU core, but it is not allowed (for thread safety reasons) to have\n * multiple CPU cores running the same pipeline instance.\n *\n ***/\n\n#include \n\n#include \n#include \n\nstruct rte_mbuf;\n\n/*\n * Pipeline\n *\n */\n/** Opaque data type for pipeline */\nstruct rte_pipeline;\n\n/** Parameters for pipeline creation */\nstruct rte_pipeline_params {\n\t/** Pipeline name */\n\tconst char *name;\n\n\t/** CPU socket ID where memory for the pipeline and its elements (ports\n\tand tables) should be allocated */\n\tint socket_id;\n\n\t/** Offset within packet meta-data to port_id to be used by action\n\t\"Send packet to output port read from packet meta-data\". Has to be\n\t4-byte aligned. */\n\tuint32_t offset_port_id;\n};\n\n/** Pipeline port in stats. */\nstruct rte_pipeline_port_in_stats {\n\t/** Port in stats. */\n\tstruct rte_port_in_stats stats;\n\n\t/** Number of packets dropped by action handler. */\n\tuint64_t n_pkts_dropped_by_ah;\n\n};\n\n/** Pipeline port out stats. */\nstruct rte_pipeline_port_out_stats {\n\t/** Port out stats. */\n\tstruct rte_port_out_stats stats;\n\n\t/** Number of packets dropped by action handler. */\n\tuint64_t n_pkts_dropped_by_ah;\n};\n\n/** Pipeline table stats. */\nstruct rte_pipeline_table_stats {\n\t/** Table stats. */\n\tstruct rte_table_stats stats;\n\n\t/** Number of packets dropped by lookup hit action handler. */\n\tuint64_t n_pkts_dropped_by_lkp_hit_ah;\n\n\t/** Number of packets dropped by lookup miss action handler. */\n\tuint64_t n_pkts_dropped_by_lkp_miss_ah;\n\n\t/** Number of packets dropped by pipeline in behalf of this table based on\n\t * on action specified in table entry. */\n\tuint64_t n_pkts_dropped_lkp_hit;\n\n\t/** Number of packets dropped by pipeline in behalf of this table based on\n\t * on action specified in table entry. */\n\tuint64_t n_pkts_dropped_lkp_miss;\n};\n\n/**\n * Pipeline create\n *\n * @param params\n * Parameters for pipeline creation\n * @return\n * Handle to pipeline instance on success or NULL otherwise\n */\nstruct rte_pipeline *rte_pipeline_create(struct rte_pipeline_params *params);\n\n/**\n * Pipeline free\n *\n * @param p\n * Handle to pipeline instance\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_free(struct rte_pipeline *p);\n\n/**\n * Pipeline consistency check\n *\n * @param p\n * Handle to pipeline instance\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_check(struct rte_pipeline *p);\n\n/**\n * Pipeline run\n *\n * @param p\n * Handle to pipeline instance\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_run(struct rte_pipeline *p);\n\n/**\n * Pipeline flush\n *\n * @param p\n * Handle to pipeline instance\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_flush(struct rte_pipeline *p);\n\n/*\n * Actions\n *\n */\n/** Reserved actions */\nenum rte_pipeline_action {\n\t/** Drop the packet */\n\tRTE_PIPELINE_ACTION_DROP = 0,\n\n\t/** Send packet to output port */\n\tRTE_PIPELINE_ACTION_PORT,\n\n\t/** Send packet to output port read from packet meta-data */\n\tRTE_PIPELINE_ACTION_PORT_META,\n\n\t/** Send packet to table */\n\tRTE_PIPELINE_ACTION_TABLE,\n\n\t/** Number of reserved actions */\n\tRTE_PIPELINE_ACTIONS\n};\n\n/*\n * Table\n *\n */\n/** Maximum number of tables allowed for any given pipeline instance. The\n\tvalue of this parameter cannot be changed. */\n#define RTE_PIPELINE_TABLE_MAX 64\n\n/**\n * Head format for the table entry of any pipeline table. For any given\n * pipeline table, all table entries should have the same size and format. For\n * any given pipeline table, the table entry has to start with a head of this\n * structure, which contains the reserved actions and their associated\n * meta-data, and then optionally continues with user actions and their\n * associated meta-data. As all the currently defined reserved actions are\n * mutually exclusive, only one reserved action can be set per table entry.\n */\nstruct rte_pipeline_table_entry {\n\t/** Reserved action */\n\tenum rte_pipeline_action action;\n\n\tunion {\n\t\t/** Output port ID (meta-data for \"Send packet to output port\"\n\t\taction) */\n\t\tuint32_t port_id;\n\t\t/** Table ID (meta-data for \"Send packet to table\" action) */\n\t\tuint32_t table_id;\n\t};\n\t/** Start of table entry area for user defined actions and meta-data */\n\tuint8_t action_data[0];\n};\n\n/**\n * Pipeline table action handler on lookup hit\n *\n * The action handler can decide to drop packets by resetting the associated\n * packet bit in the pkts_mask parameter. In this case, the action handler is\n * required not to free the packet buffer, which will be freed eventually by\n * the pipeline.\n *\n * @param pkts\n * Burst of input packets specified as array of up to 64 pointers to struct\n * rte_mbuf\n * @param pkts_mask\n * 64-bit bitmask specifying which packets in the input burst are valid. When\n * pkts_mask bit n is set, then element n of pkts array is pointing to a\n * valid packet and element n of entries array is pointing to a valid table\n * entry associated with the packet, with the association typically done by\n * the table lookup operation. Otherwise, element n of pkts array and element\n * n of entries array will not be accessed.\n * @param entries\n * Set of table entries specified as array of up to 64 pointers to struct\n * rte_pipeline_table_entry\n * @param arg\n * Opaque parameter registered by the user at the pipeline table creation\n * time\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_pipeline_table_action_handler_hit)(\n\tstruct rte_mbuf **pkts,\n\tuint64_t *pkts_mask,\n\tstruct rte_pipeline_table_entry **entries,\n\tvoid *arg);\n\n/**\n * Pipeline table action handler on lookup miss\n *\n * The action handler can decide to drop packets by resetting the associated\n * packet bit in the pkts_mask parameter. In this case, the action handler is\n * required not to free the packet buffer, which will be freed eventually by\n * the pipeline.\n *\n * @param pkts\n * Burst of input packets specified as array of up to 64 pointers to struct\n * rte_mbuf\n * @param pkts_mask\n * 64-bit bitmask specifying which packets in the input burst are valid. When\n * pkts_mask bit n is set, then element n of pkts array is pointing to a\n * valid packet. Otherwise, element n of pkts array will not be accessed.\n * @param entry\n * Single table entry associated with all the valid packets from the input\n * burst, specified as pointer to struct rte_pipeline_table_entry.\n * This entry is the pipeline table default entry that is associated by the\n * table lookup operation with the input packets that have resulted in lookup\n * miss.\n * @param arg\n * Opaque parameter registered by the user at the pipeline table creation\n * time\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_pipeline_table_action_handler_miss)(\n\tstruct rte_mbuf **pkts,\n\tuint64_t *pkts_mask,\n\tstruct rte_pipeline_table_entry *entry,\n\tvoid *arg);\n\n/** Parameters for pipeline table creation. Action handlers have to be either\n both enabled or both disabled (they can be disabled by setting them to\n NULL). */\nstruct rte_pipeline_table_params {\n\t/** Table operations (specific to each table type) */\n\tstruct rte_table_ops *ops;\n\t/** Opaque param to be passed to the table create operation when\n\tinvoked */\n\tvoid *arg_create;\n\t/** Callback function to execute the user actions on input packets in\n\tcase of lookup hit */\n\trte_pipeline_table_action_handler_hit f_action_hit;\n\t/** Callback function to execute the user actions on input packets in\n\tcase of lookup miss */\n\trte_pipeline_table_action_handler_miss f_action_miss;\n\n\t/** Opaque parameter to be passed to lookup hit and/or lookup miss\n\taction handlers when invoked */\n\tvoid *arg_ah;\n\t/** Memory size to be reserved per table entry for storing the user\n\tactions and their meta-data */\n\tuint32_t action_data_size;\n};\n\n/**\n * Pipeline table create\n *\n * @param p\n * Handle to pipeline instance\n * @param params\n * Parameters for pipeline table creation\n * @param table_id\n * Table ID. Valid only within the scope of table IDs of the current\n * pipeline. Only returned after a successful invocation.\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_table_create(struct rte_pipeline *p,\n\tstruct rte_pipeline_table_params *params,\n\tuint32_t *table_id);\n\n/**\n * Pipeline table default entry add\n *\n * The contents of the table default entry is updated with the provided actions\n * and meta-data. When the default entry is not configured (by using this\n * function), the built-in default entry has the action \"Drop\" and meta-data\n * set to all-zeros.\n *\n * @param p\n * Handle to pipeline instance\n * @param table_id\n * Table ID (returned by previous invocation of pipeline table create)\n * @param default_entry\n * New contents for the table default entry\n * @param default_entry_ptr\n * On successful invocation, pointer to the default table entry which can be\n * used for further read-write accesses to this table entry. This pointer\n * is valid until the default entry is deleted or re-added.\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_table_default_entry_add(struct rte_pipeline *p,\n\tuint32_t table_id,\n\tstruct rte_pipeline_table_entry *default_entry,\n\tstruct rte_pipeline_table_entry **default_entry_ptr);\n\n/**\n * Pipeline table default entry delete\n *\n * The new contents of the table default entry is set to reserved action \"Drop\n * the packet\" with meta-data cleared (i.e. set to all-zeros).\n *\n * @param p\n * Handle to pipeline instance\n * @param table_id\n * Table ID (returned by previous invocation of pipeline table create)\n * @param entry\n * On successful invocation, when entry points to a valid buffer, the\n * previous contents of the table default entry (as it was just before the\n * delete operation) is copied to this buffer\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_table_default_entry_delete(struct rte_pipeline *p,\n\tuint32_t table_id,\n\tstruct rte_pipeline_table_entry *entry);\n\n/**\n * Pipeline table entry add\n *\n * @param p\n * Handle to pipeline instance\n * @param table_id\n * Table ID (returned by previous invocation of pipeline table create)\n * @param key\n * Table entry key\n * @param entry\n * New contents for the table entry identified by key\n * @param key_found\n * On successful invocation, set to TRUE (value different than 0) if key was\n * already present in the table before the add operation and to FALSE (value\n * 0) if not\n * @param entry_ptr\n * On successful invocation, pointer to the table entry associated with key.\n * This can be used for further read-write accesses to this table entry and\n * is valid until the key is deleted from the table or re-added (usually for\n * associating different actions and/or action meta-data to the current key)\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_table_entry_add(struct rte_pipeline *p,\n\tuint32_t table_id,\n\tvoid *key,\n\tstruct rte_pipeline_table_entry *entry,\n\tint *key_found,\n\tstruct rte_pipeline_table_entry **entry_ptr);\n\n/**\n * Pipeline table entry delete\n *\n * @param p\n * Handle to pipeline instance\n * @param table_id\n * Table ID (returned by previous invocation of pipeline table create)\n * @param key\n * Table entry key\n * @param key_found\n * On successful invocation, set to TRUE (value different than 0) if key was\n * found in the table before the delete operation and to FALSE (value 0) if\n * not\n * @param entry\n * On successful invocation, when key is found in the table and entry points\n * to a valid buffer, the table entry contents (as it was before the delete\n * was performed) is copied to this buffer\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_table_entry_delete(struct rte_pipeline *p,\n\tuint32_t table_id,\n\tvoid *key,\n\tint *key_found,\n\tstruct rte_pipeline_table_entry *entry);\n\n/**\n * Read pipeline table stats.\n *\n * This function reads table statistics identified by *table_id* of given\n * pipeline *p*.\n *\n * @param p\n * Handle to pipeline instance.\n * @param table_id\n * Port ID what stats will be returned.\n * @param stats\n * Statistics buffer.\n * @param clear\n * If not 0 clear stats after reading.\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_table_stats_read(struct rte_pipeline *p, uint32_t table_id,\n\tstruct rte_pipeline_table_stats *stats, int clear);\n\n/*\n * Port IN\n *\n */\n/** Maximum number of input ports allowed for any given pipeline instance. The\n\tvalue of this parameter cannot be changed. */\n#define RTE_PIPELINE_PORT_IN_MAX 64\n\n/**\n * Pipeline input port action handler\n *\n * The action handler can decide to drop packets by resetting the associated\n * packet bit in the pkts_mask parameter. In this case, the action handler is\n * required not to free the packet buffer, which will be freed eventually by\n * the pipeline.\n *\n * @param pkts\n * Burst of input packets specified as array of up to 64 pointers to struct\n * rte_mbuf\n * @param n\n * Number of packets in the input burst. This parameter specifies that\n * elements 0 to (n-1) of pkts array are valid.\n * @param pkts_mask\n * 64-bit bitmask specifying which packets in the input burst are still valid\n * after the action handler is executed. When pkts_mask bit n is set, then\n * element n of pkts array is pointing to a valid packet.\n * @param arg\n * Opaque parameter registered by the user at the pipeline table creation\n * time\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_pipeline_port_in_action_handler)(\n\tstruct rte_mbuf **pkts,\n\tuint32_t n,\n\tuint64_t *pkts_mask,\n\tvoid *arg);\n\n/** Parameters for pipeline input port creation */\nstruct rte_pipeline_port_in_params {\n\t/** Input port operations (specific to each table type) */\n\tstruct rte_port_in_ops *ops;\n\t/** Opaque parameter to be passed to create operation when invoked */\n\tvoid *arg_create;\n\n\t/** Callback function to execute the user actions on input packets.\n\t\tDisabled if set to NULL. */\n\trte_pipeline_port_in_action_handler f_action;\n\t/** Opaque parameter to be passed to the action handler when invoked */\n\tvoid *arg_ah;\n\n\t/** Recommended burst size for the RX operation(in number of pkts) */\n\tuint32_t burst_size;\n};\n\n/**\n * Pipeline input port create\n *\n * @param p\n * Handle to pipeline instance\n * @param params\n * Parameters for pipeline input port creation\n * @param port_id\n * Input port ID. Valid only within the scope of input port IDs of the\n * current pipeline. Only returned after a successful invocation.\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_port_in_create(struct rte_pipeline *p,\n\tstruct rte_pipeline_port_in_params *params,\n\tuint32_t *port_id);\n\n/**\n * Pipeline input port connect to table\n *\n * @param p\n * Handle to pipeline instance\n * @param port_id\n * Port ID (returned by previous invocation of pipeline input port create)\n * @param table_id\n * Table ID (returned by previous invocation of pipeline table create)\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_port_in_connect_to_table(struct rte_pipeline *p,\n\tuint32_t port_id,\n\tuint32_t table_id);\n\n/**\n * Pipeline input port enable\n *\n * @param p\n * Handle to pipeline instance\n * @param port_id\n * Port ID (returned by previous invocation of pipeline input port create)\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_port_in_enable(struct rte_pipeline *p,\n\tuint32_t port_id);\n\n/**\n * Pipeline input port disable\n *\n * @param p\n * Handle to pipeline instance\n * @param port_id\n * Port ID (returned by previous invocation of pipeline input port create)\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_port_in_disable(struct rte_pipeline *p,\n\tuint32_t port_id);\n\n/**\n * Read pipeline port in stats.\n *\n * This function reads port in statistics identified by *port_id* of given\n * pipeline *p*.\n *\n * @param p\n * Handle to pipeline instance.\n * @param port_id\n * Port ID what stats will be returned.\n * @param stats\n * Statistics buffer.\n * @param clear\n * If not 0 clear stats after reading.\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_port_in_stats_read(struct rte_pipeline *p, uint32_t port_id,\n\tstruct rte_pipeline_port_in_stats *stats, int clear);\n\n/*\n * Port OUT\n *\n */\n/** Maximum number of output ports allowed for any given pipeline instance. The\n\tvalue of this parameter cannot be changed. */\n#define RTE_PIPELINE_PORT_OUT_MAX 64\n\n/**\n * Pipeline output port action handler for single packet\n *\n * The action handler can decide to drop packets by resetting the pkt_mask\n * argument. In this case, the action handler is required not to free the\n * packet buffer, which will be freed eventually by the pipeline.\n *\n * @param pkt\n * Input packet\n * @param pkt_mask\n * Output argument set to 0 when the action handler decides to drop the input\n * packet and to 1LLU otherwise\n * @param arg\n * Opaque parameter registered by the user at the pipeline table creation\n * time\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_pipeline_port_out_action_handler)(\n\tstruct rte_mbuf *pkt,\n\tuint64_t *pkt_mask,\n\tvoid *arg);\n\n/**\n * Pipeline output port action handler bulk\n *\n * The action handler can decide to drop packets by resetting the associated\n * packet bit in the pkts_mask parameter. In this case, the action handler is\n * required not to free the packet buffer, which will be freed eventually by\n * the pipeline.\n *\n * @param pkts\n * Burst of input packets specified as array of up to 64 pointers to struct\n * rte_mbuf\n * @param pkts_mask\n * 64-bit bitmask specifying which packets in the input burst are valid. When\n * pkts_mask bit n is set, then element n of pkts array is pointing to a\n * valid packet. Otherwise, element n of pkts array will not be accessed.\n * @param arg\n * Opaque parameter registered by the user at the pipeline table creation\n * time\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_pipeline_port_out_action_handler_bulk)(\n\tstruct rte_mbuf **pkts,\n\tuint64_t *pkts_mask,\n\tvoid *arg);\n\n/** Parameters for pipeline output port creation. The action handlers have to\nbe either both enabled or both disabled (by setting them to NULL). When\nenabled, the pipeline selects between them at different moments, based on the\nnumber of packets that have to be sent to the same output port. */\nstruct rte_pipeline_port_out_params {\n\t/** Output port operations (specific to each table type) */\n\tstruct rte_port_out_ops *ops;\n\t/** Opaque parameter to be passed to create operation when invoked */\n\tvoid *arg_create;\n\n\t/** Callback function executing the user actions on single input\n\tpacket */\n\trte_pipeline_port_out_action_handler f_action;\n\t/** Callback function executing the user actions on bust of input\n\tpackets */\n\trte_pipeline_port_out_action_handler_bulk f_action_bulk;\n\t/** Opaque parameter to be passed to the action handler when invoked */\n\tvoid *arg_ah;\n};\n\n/**\n * Pipeline output port create\n *\n * @param p\n * Handle to pipeline instance\n * @param params\n * Parameters for pipeline output port creation\n * @param port_id\n * Output port ID. Valid only within the scope of output port IDs of the\n * current pipeline. Only returned after a successful invocation.\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_port_out_create(struct rte_pipeline *p,\n\tstruct rte_pipeline_port_out_params *params,\n\tuint32_t *port_id);\n\n/**\n * Pipeline output port packet insert\n *\n * This function is called by the table action handler whenever it generates a\n * new packet to be sent out though one of the pipeline output ports. This\n * packet is not part of the burst of input packets read from any of the\n * pipeline input ports, so it is not an element of the pkts array input\n * parameter of the table action handler. This packet can be dropped by the\n * output port action handler.\n *\n * @param p\n * Handle to pipeline instance\n * @param port_id\n * Output port ID (returned by previous invocation of pipeline output port\n * create) to send the packet specified by pkt\n * @param pkt\n * New packet generated by the table action handler\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_port_out_packet_insert(struct rte_pipeline *p,\n\tuint32_t port_id,\n\tstruct rte_mbuf *pkt);\n\n/**\n * Read pipeline port out stats.\n *\n * This function reads port out statistics identified by *port_id* of given\n * pipeline *p*.\n *\n * @param p\n * Handle to pipeline instance.\n * @param port_id\n * Port ID what stats will be returned.\n * @param stats\n * Statistics buffer.\n * @param clear\n * If not 0 clear stats after reading.\n * @return\n * 0 on success, error code otherwise\n */\nint rte_pipeline_port_out_stats_read(struct rte_pipeline *p, uint32_t port_id,\n\tstruct rte_pipeline_port_out_stats *stats, int clear);\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_port/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_port.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_port_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_PORT) += rte_port_ethdev.c\nSRCS-$(CONFIG_RTE_LIBRTE_PORT) += rte_port_ring.c\nifeq ($(CONFIG_RTE_LIBRTE_IP_FRAG),y)\nSRCS-$(CONFIG_RTE_LIBRTE_PORT) += rte_port_frag.c\nSRCS-$(CONFIG_RTE_LIBRTE_PORT) += rte_port_ras.c\nendif\nSRCS-$(CONFIG_RTE_LIBRTE_PORT) += rte_port_sched.c\nSRCS-$(CONFIG_RTE_LIBRTE_PORT) += rte_port_source_sink.c\n\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_PORT)-include += rte_port.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_PORT)-include += rte_port_ethdev.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_PORT)-include += rte_port_ring.h\nifeq ($(CONFIG_RTE_LIBRTE_IP_FRAG),y)\nSYMLINK-$(CONFIG_RTE_LIBRTE_PORT)-include += rte_port_frag.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_PORT)-include += rte_port_ras.h\nendif\nSYMLINK-$(CONFIG_RTE_LIBRTE_PORT)-include += rte_port_sched.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_PORT)-include += rte_port_source_sink.h\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PORT) := lib/librte_eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PORT) += lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PORT) += lib/librte_mempool\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PORT) += lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_PORT) += lib/librte_ip_frag\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_port/rte_port.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_PORT_H__\n#define __INCLUDE_RTE_PORT_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Port\n *\n * This tool is part of the Intel DPDK Packet Framework tool suite and provides\n * a standard interface to implement different types of packet ports.\n *\n ***/\n\n#include \n#include \n\n/**@{\n * Macros to allow accessing metadata stored in the mbuf headroom\n * just beyond the end of the mbuf data structure returned by a port\n */\n#define RTE_MBUF_METADATA_UINT8_PTR(mbuf, offset) \\\n\t(&((uint8_t *) &(mbuf)[1])[offset])\n#define RTE_MBUF_METADATA_UINT16_PTR(mbuf, offset) \\\n\t((uint16_t *) RTE_MBUF_METADATA_UINT8_PTR(mbuf, offset))\n#define RTE_MBUF_METADATA_UINT32_PTR(mbuf, offset) \\\n\t((uint32_t *) RTE_MBUF_METADATA_UINT8_PTR(mbuf, offset))\n#define RTE_MBUF_METADATA_UINT64_PTR(mbuf, offset) \\\n\t((uint64_t *) RTE_MBUF_METADATA_UINT8_PTR(mbuf, offset))\n\n#define RTE_MBUF_METADATA_UINT8(mbuf, offset) \\\n\t(*RTE_MBUF_METADATA_UINT8_PTR(mbuf, offset))\n#define RTE_MBUF_METADATA_UINT16(mbuf, offset) \\\n\t(*RTE_MBUF_METADATA_UINT16_PTR(mbuf, offset))\n#define RTE_MBUF_METADATA_UINT32(mbuf, offset) \\\n\t(*RTE_MBUF_METADATA_UINT32_PTR(mbuf, offset))\n#define RTE_MBUF_METADATA_UINT64(mbuf, offset) \\\n\t(*RTE_MBUF_METADATA_UINT64_PTR(mbuf, offset))\n/**@}*/\n\n/*\n * Port IN\n *\n */\n/** Maximum number of packets read from any input port in a single burst.\nCannot be changed. */\n#define RTE_PORT_IN_BURST_SIZE_MAX 64\n\n/** Input port statistics */\nstruct rte_port_in_stats {\n\tuint64_t n_pkts_in;\n\tuint64_t n_pkts_drop;\n};\n\n/**\n * Input port create\n *\n * @param params\n * Parameters for input port creation\n * @param socket_id\n * CPU socket ID (e.g. for memory allocation purpose)\n * @return\n * Handle to input port instance\n */\ntypedef void* (*rte_port_in_op_create)(void *params, int socket_id);\n\n/**\n * Input port free\n *\n * @param port\n * Handle to input port instance\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_port_in_op_free)(void *port);\n\n/**\n * Input port packet burst RX\n *\n * @param port\n * Handle to input port instance\n * @param pkts\n * Burst of input packets\n * @param n_pkts\n * Number of packets in the input burst\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_port_in_op_rx)(\n\tvoid *port,\n\tstruct rte_mbuf **pkts,\n\tuint32_t n_pkts);\n\n/**\n * Input port stats get\n *\n * @param port\n * Handle to output port instance\n * @param stats\n * Handle to port_in stats struct to copy data\n * @param clear\n * Flag indicating that stats should be cleared after read\n *\n * @return\n * Error code or 0 on success.\n */\ntypedef int (*rte_port_in_op_stats_read)(\n\t\tvoid *port,\n\t\tstruct rte_port_in_stats *stats,\n\t\tint clear);\n\n/** Input port interface defining the input port operation */\nstruct rte_port_in_ops {\n\trte_port_in_op_create f_create; /**< Create */\n\trte_port_in_op_free f_free; /**< Free */\n\trte_port_in_op_rx f_rx; /**< Packet RX (packet burst) */\n\trte_port_in_op_stats_read f_stats; /**< Stats */\n};\n\n/*\n * Port OUT\n *\n */\n/** Output port statistics */\nstruct rte_port_out_stats {\n\tuint64_t n_pkts_in;\n\tuint64_t n_pkts_drop;\n};\n\n/**\n * Output port create\n *\n * @param params\n * Parameters for output port creation\n * @param socket_id\n * CPU socket ID (e.g. for memory allocation purpose)\n * @return\n * Handle to output port instance\n */\ntypedef void* (*rte_port_out_op_create)(void *params, int socket_id);\n\n/**\n * Output port free\n *\n * @param port\n * Handle to output port instance\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_port_out_op_free)(void *port);\n\n/**\n * Output port single packet TX\n *\n * @param port\n * Handle to output port instance\n * @param pkt\n * Input packet\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_port_out_op_tx)(\n\tvoid *port,\n\tstruct rte_mbuf *pkt);\n\n/**\n * Output port packet burst TX\n *\n * @param port\n * Handle to output port instance\n * @param pkts\n * Burst of input packets specified as array of up to 64 pointers to struct\n * rte_mbuf\n * @param pkts_mask\n * 64-bit bitmask specifying which packets in the input burst are valid. When\n * pkts_mask bit n is set, then element n of pkts array is pointing to a\n * valid packet. Otherwise, element n of pkts array will not be accessed.\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_port_out_op_tx_bulk)(\n\tvoid *port,\n\tstruct rte_mbuf **pkt,\n\tuint64_t pkts_mask);\n\n/**\n * Output port flush\n *\n * @param port\n * Handle to output port instance\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_port_out_op_flush)(void *port);\n\n/**\n * Output port stats read\n *\n * @param port\n * Handle to output port instance\n * @param stats\n * Handle to port_out stats struct to copy data\n * @param clear\n * Flag indicating that stats should be cleared after read\n *\n * @return\n * Error code or 0 on success.\n */\ntypedef int (*rte_port_out_op_stats_read)(\n\t\tvoid *port,\n\t\tstruct rte_port_out_stats *stats,\n\t\tint clear);\n\n/** Output port interface defining the output port operation */\nstruct rte_port_out_ops {\n\trte_port_out_op_create f_create; /**< Create */\n\trte_port_out_op_free f_free; /**< Free */\n\trte_port_out_op_tx f_tx; /**< Packet TX (single packet) */\n\trte_port_out_op_tx_bulk f_tx_bulk; /**< Packet TX (packet burst) */\n\trte_port_out_op_flush f_flush; /**< Flush */\n\trte_port_out_op_stats_read f_stats; /**< Stats */\n};\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_port/rte_port_ethdev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n\n#include \n#include \n#include \n\n#include \"rte_port_ethdev.h\"\n\n/*\n * Port ETHDEV Reader\n */\n#ifdef RTE_PORT_STATS_COLLECT\n\n#define RTE_PORT_ETHDEV_READER_STATS_PKTS_IN_ADD(port, val) \\\n\tport->stats.n_pkts_in += val\n#define RTE_PORT_ETHDEV_READER_STATS_PKTS_DROP_ADD(port, val) \\\n\tport->stats.n_pkts_drop += val\n\n#else\n\n#define RTE_PORT_ETHDEV_READER_STATS_PKTS_IN_ADD(port, val)\n#define RTE_PORT_ETHDEV_READER_STATS_PKTS_DROP_ADD(port, val)\n\n#endif\n\nstruct rte_port_ethdev_reader {\n\tstruct rte_port_in_stats stats;\n\n\tuint16_t queue_id;\n\tuint8_t port_id;\n};\n\nstatic void *\nrte_port_ethdev_reader_create(void *params, int socket_id)\n{\n\tstruct rte_port_ethdev_reader_params *conf =\n\t\t\t(struct rte_port_ethdev_reader_params *) params;\n\tstruct rte_port_ethdev_reader *port;\n\n\t/* Check input parameters */\n\tif (conf == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: params is NULL\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Memory allocation */\n\tport = rte_zmalloc_socket(\"PORT\", sizeof(*port),\n\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Failed to allocate port\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Initialization */\n\tport->port_id = conf->port_id;\n\tport->queue_id = conf->queue_id;\n\n\treturn port;\n}\n\nstatic int\nrte_port_ethdev_reader_rx(void *port, struct rte_mbuf **pkts, uint32_t n_pkts)\n{\n\tstruct rte_port_ethdev_reader *p =\n\t\t(struct rte_port_ethdev_reader *) port;\n\tuint16_t rx_pkt_cnt;\n\n\trx_pkt_cnt = rte_eth_rx_burst(p->port_id, p->queue_id, pkts, n_pkts);\n\tRTE_PORT_ETHDEV_READER_STATS_PKTS_IN_ADD(p, rx_pkt_cnt);\n\treturn rx_pkt_cnt;\n}\n\nstatic int\nrte_port_ethdev_reader_free(void *port)\n{\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: port is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_free(port);\n\n\treturn 0;\n}\n\nstatic int rte_port_ethdev_reader_stats_read(void *port,\n\t\tstruct rte_port_in_stats *stats, int clear)\n{\n\tstruct rte_port_ethdev_reader *p =\n\t\t\t(struct rte_port_ethdev_reader *) port;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &p->stats, sizeof(p->stats));\n\n\tif (clear)\n\t\tmemset(&p->stats, 0, sizeof(p->stats));\n\n\treturn 0;\n}\n\n/*\n * Port ETHDEV Writer\n */\n#ifdef RTE_PORT_STATS_COLLECT\n\n#define RTE_PORT_ETHDEV_WRITER_STATS_PKTS_IN_ADD(port, val) \\\n\tport->stats.n_pkts_in += val\n#define RTE_PORT_ETHDEV_WRITER_STATS_PKTS_DROP_ADD(port, val) \\\n\tport->stats.n_pkts_drop += val\n\n#else\n\n#define RTE_PORT_ETHDEV_WRITER_STATS_PKTS_IN_ADD(port, val)\n#define RTE_PORT_ETHDEV_WRITER_STATS_PKTS_DROP_ADD(port, val)\n\n#endif\n\nstruct rte_port_ethdev_writer {\n\tstruct rte_port_out_stats stats;\n\n\tstruct rte_mbuf *tx_buf[2 * RTE_PORT_IN_BURST_SIZE_MAX];\n\tuint32_t tx_burst_sz;\n\tuint16_t tx_buf_count;\n\tuint64_t bsz_mask;\n\tuint16_t queue_id;\n\tuint8_t port_id;\n};\n\nstatic void *\nrte_port_ethdev_writer_create(void *params, int socket_id)\n{\n\tstruct rte_port_ethdev_writer_params *conf =\n\t\t\t(struct rte_port_ethdev_writer_params *) params;\n\tstruct rte_port_ethdev_writer *port;\n\n\t/* Check input parameters */\n\tif ((conf == NULL) ||\n\t\t(conf->tx_burst_sz == 0) ||\n\t\t(conf->tx_burst_sz > RTE_PORT_IN_BURST_SIZE_MAX) ||\n\t\t(!rte_is_power_of_2(conf->tx_burst_sz))) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Invalid input parameters\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Memory allocation */\n\tport = rte_zmalloc_socket(\"PORT\", sizeof(*port),\n\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Failed to allocate port\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Initialization */\n\tport->port_id = conf->port_id;\n\tport->queue_id = conf->queue_id;\n\tport->tx_burst_sz = conf->tx_burst_sz;\n\tport->tx_buf_count = 0;\n\tport->bsz_mask = 1LLU << (conf->tx_burst_sz - 1);\n\n\treturn port;\n}\n\nstatic inline void\nsend_burst(struct rte_port_ethdev_writer *p)\n{\n\tuint32_t nb_tx;\n\n\tnb_tx = rte_eth_tx_burst(p->port_id, p->queue_id,\n\t\t\t p->tx_buf, p->tx_buf_count);\n\n\tRTE_PORT_ETHDEV_WRITER_STATS_PKTS_DROP_ADD(p, p->tx_buf_count - nb_tx);\n\tfor ( ; nb_tx < p->tx_buf_count; nb_tx++)\n\t\trte_pktmbuf_free(p->tx_buf[nb_tx]);\n\n\tp->tx_buf_count = 0;\n}\n\nstatic int\nrte_port_ethdev_writer_tx(void *port, struct rte_mbuf *pkt)\n{\n\tstruct rte_port_ethdev_writer *p =\n\t\t(struct rte_port_ethdev_writer *) port;\n\n\tp->tx_buf[p->tx_buf_count++] = pkt;\n\tRTE_PORT_ETHDEV_WRITER_STATS_PKTS_IN_ADD(p, 1);\n\tif (p->tx_buf_count >= p->tx_burst_sz)\n\t\tsend_burst(p);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ethdev_writer_tx_bulk(void *port,\n\t\tstruct rte_mbuf **pkts,\n\t\tuint64_t pkts_mask)\n{\n\tstruct rte_port_ethdev_writer *p =\n\t\t(struct rte_port_ethdev_writer *) port;\n\tuint32_t bsz_mask = p->bsz_mask;\n\tuint32_t tx_buf_count = p->tx_buf_count;\n\tuint64_t expr = (pkts_mask & (pkts_mask + 1)) |\n\t\t\t((pkts_mask & bsz_mask) ^ bsz_mask);\n\n\tif (expr == 0) {\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_mask);\n\t\tuint32_t n_pkts_ok;\n\n\t\tif (tx_buf_count)\n\t\t\tsend_burst(p);\n\n\t\tRTE_PORT_ETHDEV_WRITER_STATS_PKTS_IN_ADD(p, n_pkts);\n\t\tn_pkts_ok = rte_eth_tx_burst(p->port_id, p->queue_id, pkts,\n\t\t\tn_pkts);\n\n\t\tRTE_PORT_ETHDEV_WRITER_STATS_PKTS_DROP_ADD(p, n_pkts - n_pkts_ok);\n\t\tfor ( ; n_pkts_ok < n_pkts; n_pkts_ok++) {\n\t\t\tstruct rte_mbuf *pkt = pkts[n_pkts_ok];\n\n\t\t\trte_pktmbuf_free(pkt);\n\t\t}\n\t} else {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tuint32_t pkt_index = __builtin_ctzll(pkts_mask);\n\t\t\tuint64_t pkt_mask = 1LLU << pkt_index;\n\t\t\tstruct rte_mbuf *pkt = pkts[pkt_index];\n\n\t\t\tp->tx_buf[tx_buf_count++] = pkt;\n\t\t\tRTE_PORT_ETHDEV_WRITER_STATS_PKTS_IN_ADD(p, 1);\n\t\t\tpkts_mask &= ~pkt_mask;\n\t\t}\n\n\t\tp->tx_buf_count = tx_buf_count;\n\t\tif (tx_buf_count >= p->tx_burst_sz)\n\t\t\tsend_burst(p);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ethdev_writer_flush(void *port)\n{\n\tstruct rte_port_ethdev_writer *p =\n\t\t(struct rte_port_ethdev_writer *) port;\n\n\tif (p->tx_buf_count > 0)\n\t\tsend_burst(p);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ethdev_writer_free(void *port)\n{\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Port is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_port_ethdev_writer_flush(port);\n\trte_free(port);\n\n\treturn 0;\n}\n\nstatic int rte_port_ethdev_writer_stats_read(void *port,\n\t\tstruct rte_port_out_stats *stats, int clear)\n{\n\tstruct rte_port_ethdev_writer *p =\n\t\t(struct rte_port_ethdev_writer *) port;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &p->stats, sizeof(p->stats));\n\n\tif (clear)\n\t\tmemset(&p->stats, 0, sizeof(p->stats));\n\n\treturn 0;\n}\n\n/*\n * Port ETHDEV Writer Nodrop\n */\n#ifdef RTE_PORT_STATS_COLLECT\n\n#define RTE_PORT_ETHDEV_WRITER_NODROP_STATS_PKTS_IN_ADD(port, val) \\\n\tport->stats.n_pkts_in += val\n#define RTE_PORT_ETHDEV_WRITER_NODROP_STATS_PKTS_DROP_ADD(port, val) \\\n\tport->stats.n_pkts_drop += val\n\n#else\n\n#define RTE_PORT_ETHDEV_WRITER_NODROP_STATS_PKTS_IN_ADD(port, val)\n#define RTE_PORT_ETHDEV_WRITER_NODROP_STATS_PKTS_DROP_ADD(port, val)\n\n#endif\n\nstruct rte_port_ethdev_writer_nodrop {\n\tstruct rte_port_out_stats stats;\n\n\tstruct rte_mbuf *tx_buf[2 * RTE_PORT_IN_BURST_SIZE_MAX];\n\tuint32_t tx_burst_sz;\n\tuint16_t tx_buf_count;\n\tuint64_t bsz_mask;\n\tuint64_t n_retries;\n\tuint16_t queue_id;\n\tuint8_t port_id;\n};\n\nstatic void *\nrte_port_ethdev_writer_nodrop_create(void *params, int socket_id)\n{\n\tstruct rte_port_ethdev_writer_nodrop_params *conf =\n\t\t\t(struct rte_port_ethdev_writer_nodrop_params *) params;\n\tstruct rte_port_ethdev_writer_nodrop *port;\n\n\t/* Check input parameters */\n\tif ((conf == NULL) ||\n\t\t(conf->tx_burst_sz == 0) ||\n\t\t(conf->tx_burst_sz > RTE_PORT_IN_BURST_SIZE_MAX) ||\n\t\t(!rte_is_power_of_2(conf->tx_burst_sz))) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Invalid input parameters\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Memory allocation */\n\tport = rte_zmalloc_socket(\"PORT\", sizeof(*port),\n\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Failed to allocate port\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Initialization */\n\tport->port_id = conf->port_id;\n\tport->queue_id = conf->queue_id;\n\tport->tx_burst_sz = conf->tx_burst_sz;\n\tport->tx_buf_count = 0;\n\tport->bsz_mask = 1LLU << (conf->tx_burst_sz - 1);\n\n\t/*\n\t * When n_retries is 0 it means that we should wait for every packet to\n\t * send no matter how many retries should it take. To limit number of\n\t * branches in fast path, we use UINT64_MAX instead of branching.\n\t */\n\tport->n_retries = (conf->n_retries == 0) ? UINT64_MAX : conf->n_retries;\n\n\treturn port;\n}\n\nstatic inline void\nsend_burst_nodrop(struct rte_port_ethdev_writer_nodrop *p)\n{\n\tuint32_t nb_tx = 0, i;\n\n\tnb_tx = rte_eth_tx_burst(p->port_id, p->queue_id, p->tx_buf,\n\t\t\tp->tx_buf_count);\n\n\t/* We sent all the packets in a first try */\n\tif (nb_tx >= p->tx_buf_count)\n\t\treturn;\n\n\tfor (i = 0; i < p->n_retries; i++) {\n\t\tnb_tx += rte_eth_tx_burst(p->port_id, p->queue_id,\n\t\t\t\t\t\t\t p->tx_buf + nb_tx, p->tx_buf_count - nb_tx);\n\n\t\t/* We sent all the packets in more than one try */\n\t\tif (nb_tx >= p->tx_buf_count)\n\t\t\treturn;\n\t}\n\n\t/* We didn't send the packets in maximum allowed attempts */\n\tRTE_PORT_ETHDEV_WRITER_NODROP_STATS_PKTS_DROP_ADD(p, p->tx_buf_count - nb_tx);\n\tfor ( ; nb_tx < p->tx_buf_count; nb_tx++)\n\t\trte_pktmbuf_free(p->tx_buf[nb_tx]);\n\n\tp->tx_buf_count = 0;\n}\n\nstatic int\nrte_port_ethdev_writer_nodrop_tx(void *port, struct rte_mbuf *pkt)\n{\n\tstruct rte_port_ethdev_writer_nodrop *p =\n\t\t(struct rte_port_ethdev_writer_nodrop *) port;\n\n\tp->tx_buf[p->tx_buf_count++] = pkt;\n\tRTE_PORT_ETHDEV_WRITER_NODROP_STATS_PKTS_IN_ADD(p, 1);\n\tif (p->tx_buf_count >= p->tx_burst_sz)\n\t\tsend_burst_nodrop(p);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ethdev_writer_nodrop_tx_bulk(void *port,\n\t\tstruct rte_mbuf **pkts,\n\t\tuint64_t pkts_mask)\n{\n\tstruct rte_port_ethdev_writer_nodrop *p =\n\t\t(struct rte_port_ethdev_writer_nodrop *) port;\n\n\tuint32_t bsz_mask = p->bsz_mask;\n\tuint32_t tx_buf_count = p->tx_buf_count;\n\tuint64_t expr = (pkts_mask & (pkts_mask + 1)) |\n\t\t\t((pkts_mask & bsz_mask) ^ bsz_mask);\n\n\tif (expr == 0) {\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_mask);\n\t\tuint32_t n_pkts_ok;\n\n\t\tif (tx_buf_count)\n\t\t\tsend_burst_nodrop(p);\n\n\t\tRTE_PORT_ETHDEV_WRITER_NODROP_STATS_PKTS_IN_ADD(p, n_pkts);\n\t\tn_pkts_ok = rte_eth_tx_burst(p->port_id, p->queue_id, pkts,\n\t\t\tn_pkts);\n\n\t\tif (n_pkts_ok >= n_pkts)\n\t\t\treturn 0;\n\n\t\t/*\n\t\t * If we didnt manage to send all packets in single burst, move\n\t\t * remaining packets to the buffer and call send burst.\n\t\t */\n\t\tfor (; n_pkts_ok < n_pkts; n_pkts_ok++) {\n\t\t\tstruct rte_mbuf *pkt = pkts[n_pkts_ok];\n\t\t\tp->tx_buf[p->tx_buf_count++] = pkt;\n\t\t}\n\t\tsend_burst_nodrop(p);\n\t} else {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tuint32_t pkt_index = __builtin_ctzll(pkts_mask);\n\t\t\tuint64_t pkt_mask = 1LLU << pkt_index;\n\t\t\tstruct rte_mbuf *pkt = pkts[pkt_index];\n\n\t\t\tp->tx_buf[tx_buf_count++] = pkt;\n\t\t\tRTE_PORT_ETHDEV_WRITER_NODROP_STATS_PKTS_IN_ADD(p, 1);\n\t\t\tpkts_mask &= ~pkt_mask;\n\t\t}\n\n\t\tp->tx_buf_count = tx_buf_count;\n\t\tif (tx_buf_count >= p->tx_burst_sz)\n\t\t\tsend_burst_nodrop(p);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ethdev_writer_nodrop_flush(void *port)\n{\n\tstruct rte_port_ethdev_writer_nodrop *p =\n\t\t(struct rte_port_ethdev_writer_nodrop *) port;\n\n\tif (p->tx_buf_count > 0)\n\t\tsend_burst_nodrop(p);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ethdev_writer_nodrop_free(void *port)\n{\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Port is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_port_ethdev_writer_nodrop_flush(port);\n\trte_free(port);\n\n\treturn 0;\n}\n\nstatic int rte_port_ethdev_writer_nodrop_stats_read(void *port,\n\t\tstruct rte_port_out_stats *stats, int clear)\n{\n\tstruct rte_port_ethdev_writer_nodrop *p =\n\t\t(struct rte_port_ethdev_writer_nodrop *) port;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &p->stats, sizeof(p->stats));\n\n\tif (clear)\n\t\tmemset(&p->stats, 0, sizeof(p->stats));\n\n\treturn 0;\n}\n\n/*\n * Summary of port operations\n */\nstruct rte_port_in_ops rte_port_ethdev_reader_ops = {\n\t.f_create = rte_port_ethdev_reader_create,\n\t.f_free = rte_port_ethdev_reader_free,\n\t.f_rx = rte_port_ethdev_reader_rx,\n\t.f_stats = rte_port_ethdev_reader_stats_read,\n};\n\nstruct rte_port_out_ops rte_port_ethdev_writer_ops = {\n\t.f_create = rte_port_ethdev_writer_create,\n\t.f_free = rte_port_ethdev_writer_free,\n\t.f_tx = rte_port_ethdev_writer_tx,\n\t.f_tx_bulk = rte_port_ethdev_writer_tx_bulk,\n\t.f_flush = rte_port_ethdev_writer_flush,\n\t.f_stats = rte_port_ethdev_writer_stats_read,\n};\n\nstruct rte_port_out_ops rte_port_ethdev_writer_nodrop_ops = {\n\t.f_create = rte_port_ethdev_writer_nodrop_create,\n\t.f_free = rte_port_ethdev_writer_nodrop_free,\n\t.f_tx = rte_port_ethdev_writer_nodrop_tx,\n\t.f_tx_bulk = rte_port_ethdev_writer_nodrop_tx_bulk,\n\t.f_flush = rte_port_ethdev_writer_nodrop_flush,\n\t.f_stats = rte_port_ethdev_writer_nodrop_stats_read,\n};\n" }, { "path": "lib/librte_port/rte_port_ethdev.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_PORT_ETHDEV_H__\n#define __INCLUDE_RTE_PORT_ETHDEV_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Port Ethernet Device\n *\n * ethdev_reader: input port built on top of pre-initialized NIC RX queue\n * ethdev_writer: output port built on top of pre-initialized NIC TX queue\n *\n ***/\n\n#include \n\n#include \"rte_port.h\"\n\n/** ethdev_reader port parameters */\nstruct rte_port_ethdev_reader_params {\n\t/** NIC RX port ID */\n\tuint8_t port_id;\n\n\t/** NIC RX queue ID */\n\tuint16_t queue_id;\n};\n\n/** ethdev_reader port operations */\nextern struct rte_port_in_ops rte_port_ethdev_reader_ops;\n\n/** ethdev_writer port parameters */\nstruct rte_port_ethdev_writer_params {\n\t/** NIC RX port ID */\n\tuint8_t port_id;\n\n\t/** NIC RX queue ID */\n\tuint16_t queue_id;\n\n\t/** Recommended burst size to NIC TX queue. The actual burst size can be\n\tbigger or smaller than this value. */\n\tuint32_t tx_burst_sz;\n};\n\n/** ethdev_writer port operations */\nextern struct rte_port_out_ops rte_port_ethdev_writer_ops;\n\n/** ethdev_writer_nodrop port parameters */\nstruct rte_port_ethdev_writer_nodrop_params {\n\t/** NIC RX port ID */\n\tuint8_t port_id;\n\n\t/** NIC RX queue ID */\n\tuint16_t queue_id;\n\n\t/** Recommended burst size to NIC TX queue. The actual burst size can be\n\tbigger or smaller than this value. */\n\tuint32_t tx_burst_sz;\n\n\t/** Maximum number of retries, 0 for no limit */\n\tuint32_t n_retries;\n};\n\n/** ethdev_writer_nodrop port operations */\nextern struct rte_port_out_ops rte_port_ethdev_writer_nodrop_ops;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_port/rte_port_frag.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n\n#include \n#include \n#include \n\n#include \"rte_port_frag.h\"\n\n/* Max number of fragments per packet allowed */\n#define\tRTE_PORT_FRAG_MAX_FRAGS_PER_PACKET 0x80\n\n#ifdef RTE_PORT_STATS_COLLECT\n\n#define RTE_PORT_RING_READER_FRAG_STATS_PKTS_IN_ADD(port, val) \\\n\tport->stats.n_pkts_in += val\n#define RTE_PORT_RING_READER_FRAG_STATS_PKTS_DROP_ADD(port, val) \\\n\tport->stats.n_pkts_drop += val\n\n#else\n\n#define RTE_PORT_RING_READER_FRAG_STATS_PKTS_IN_ADD(port, val)\n#define RTE_PORT_RING_READER_FRAG_STATS_PKTS_DROP_ADD(port, val)\n\n#endif\n\ntypedef int32_t\n\t\t(*frag_op)(struct rte_mbuf *pkt_in,\n\t\t\tstruct rte_mbuf **pkts_out,\n\t\t\tuint16_t nb_pkts_out,\n\t\t\tuint16_t mtu_size,\n\t\t\tstruct rte_mempool *pool_direct,\n\t\t\tstruct rte_mempool *pool_indirect);\n\nstruct rte_port_ring_reader_frag {\n\tstruct rte_port_in_stats stats;\n\n\t/* Input parameters */\n\tstruct rte_ring *ring;\n\tuint32_t mtu;\n\tuint32_t metadata_size;\n\tstruct rte_mempool *pool_direct;\n\tstruct rte_mempool *pool_indirect;\n\n\t/* Internal buffers */\n\tstruct rte_mbuf *pkts[RTE_PORT_IN_BURST_SIZE_MAX];\n\tstruct rte_mbuf *frags[RTE_PORT_FRAG_MAX_FRAGS_PER_PACKET];\n\tuint32_t n_pkts;\n\tuint32_t pos_pkts;\n\tuint32_t n_frags;\n\tuint32_t pos_frags;\n\n\tfrag_op f_frag;\n} __rte_cache_aligned;\n\nstatic void *\nrte_port_ring_reader_frag_create(void *params, int socket_id, int is_ipv4)\n{\n\tstruct rte_port_ring_reader_frag_params *conf =\n\t\t\t(struct rte_port_ring_reader_frag_params *) params;\n\tstruct rte_port_ring_reader_frag *port;\n\n\t/* Check input parameters */\n\tif (conf == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Parameter conf is NULL\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tif (conf->ring == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Parameter ring is NULL\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tif (conf->mtu == 0) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Parameter mtu is invalid\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tif (conf->pool_direct == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Parameter pool_direct is NULL\\n\",\n\t\t\t__func__);\n\t\treturn NULL;\n\t}\n\tif (conf->pool_indirect == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Parameter pool_indirect is NULL\\n\",\n\t\t\t__func__);\n\t\treturn NULL;\n\t}\n\n\t/* Memory allocation */\n\tport = rte_zmalloc_socket(\"PORT\", sizeof(*port), RTE_CACHE_LINE_SIZE,\n\t\tsocket_id);\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: port is NULL\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Initialization */\n\tport->ring = conf->ring;\n\tport->mtu = conf->mtu;\n\tport->metadata_size = conf->metadata_size;\n\tport->pool_direct = conf->pool_direct;\n\tport->pool_indirect = conf->pool_indirect;\n\n\tport->n_pkts = 0;\n\tport->pos_pkts = 0;\n\tport->n_frags = 0;\n\tport->pos_frags = 0;\n\n\tport->f_frag = (is_ipv4) ?\n\t\t\trte_ipv4_fragment_packet : rte_ipv6_fragment_packet;\n\n\treturn port;\n}\n\nstatic void *\nrte_port_ring_reader_ipv4_frag_create(void *params, int socket_id)\n{\n\treturn rte_port_ring_reader_frag_create(params, socket_id, 1);\n}\n\nstatic void *\nrte_port_ring_reader_ipv6_frag_create(void *params, int socket_id)\n{\n\treturn rte_port_ring_reader_frag_create(params, socket_id, 0);\n}\n\nstatic int\nrte_port_ring_reader_frag_rx(void *port,\n\t\tstruct rte_mbuf **pkts,\n\t\tuint32_t n_pkts)\n{\n\tstruct rte_port_ring_reader_frag *p =\n\t\t\t(struct rte_port_ring_reader_frag *) port;\n\tuint32_t n_pkts_out;\n\n\tn_pkts_out = 0;\n\n\t/* Get packets from the \"frag\" buffer */\n\tif (p->n_frags >= n_pkts) {\n\t\tmemcpy(pkts, &p->frags[p->pos_frags], n_pkts * sizeof(void *));\n\t\tp->pos_frags += n_pkts;\n\t\tp->n_frags -= n_pkts;\n\n\t\treturn n_pkts;\n\t}\n\n\tmemcpy(pkts, &p->frags[p->pos_frags], p->n_frags * sizeof(void *));\n\tn_pkts_out = p->n_frags;\n\tp->n_frags = 0;\n\n\t/* Look to \"pkts\" buffer to get more packets */\n\tfor ( ; ; ) {\n\t\tstruct rte_mbuf *pkt;\n\t\tuint32_t n_pkts_to_provide, i;\n\t\tint status;\n\n\t\t/* If \"pkts\" buffer is empty, read packet burst from ring */\n\t\tif (p->n_pkts == 0) {\n\t\t\tp->n_pkts = rte_ring_sc_dequeue_burst(p->ring,\n\t\t\t\t(void **) p->pkts, RTE_PORT_IN_BURST_SIZE_MAX);\n\t\t\tRTE_PORT_RING_READER_FRAG_STATS_PKTS_IN_ADD(p, p->n_pkts);\n\t\t\tif (p->n_pkts == 0)\n\t\t\t\treturn n_pkts_out;\n\t\t\tp->pos_pkts = 0;\n\t\t}\n\n\t\t/* Read next packet from \"pkts\" buffer */\n\t\tpkt = p->pkts[p->pos_pkts++];\n\t\tp->n_pkts--;\n\n\t\t/* If not jumbo, pass current packet to output */\n\t\tif (pkt->pkt_len <= p->mtu) {\n\t\t\tpkts[n_pkts_out++] = pkt;\n\n\t\t\tn_pkts_to_provide = n_pkts - n_pkts_out;\n\t\t\tif (n_pkts_to_provide == 0)\n\t\t\t\treturn n_pkts;\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Fragment current packet into the \"frags\" buffer */\n\t\tstatus = p->f_frag(\n\t\t\tpkt,\n\t\t\tp->frags,\n\t\t\tRTE_PORT_FRAG_MAX_FRAGS_PER_PACKET,\n\t\t\tp->mtu,\n\t\t\tp->pool_direct,\n\t\t\tp->pool_indirect\n\t\t);\n\n\t\tif (status < 0) {\n\t\t\trte_pktmbuf_free(pkt);\n\t\t\tRTE_PORT_RING_READER_FRAG_STATS_PKTS_DROP_ADD(p, 1);\n\t\t\tcontinue;\n\t\t}\n\n\t\tp->n_frags = (uint32_t) status;\n\t\tp->pos_frags = 0;\n\n\t\t/* Copy meta-data from input jumbo packet to its fragments */\n\t\tfor (i = 0; i < p->n_frags; i++) {\n\t\t\tuint8_t *src = RTE_MBUF_METADATA_UINT8_PTR(pkt, 0);\n\t\t\tuint8_t *dst =\n\t\t\t\tRTE_MBUF_METADATA_UINT8_PTR(p->frags[i], 0);\n\n\t\t\tmemcpy(dst, src, p->metadata_size);\n\t\t}\n\n\t\t/* Free input jumbo packet */\n\t\trte_pktmbuf_free(pkt);\n\n\t\t/* Get packets from \"frag\" buffer */\n\t\tn_pkts_to_provide = n_pkts - n_pkts_out;\n\t\tif (p->n_frags >= n_pkts_to_provide) {\n\t\t\tmemcpy(&pkts[n_pkts_out], p->frags,\n\t\t\t\tn_pkts_to_provide * sizeof(void *));\n\t\t\tp->n_frags -= n_pkts_to_provide;\n\t\t\tp->pos_frags += n_pkts_to_provide;\n\n\t\t\treturn n_pkts;\n\t\t}\n\n\t\tmemcpy(&pkts[n_pkts_out], p->frags,\n\t\t\tp->n_frags * sizeof(void *));\n\t\tn_pkts_out += p->n_frags;\n\t\tp->n_frags = 0;\n\t}\n}\n\nstatic int\nrte_port_ring_reader_frag_free(void *port)\n{\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Parameter port is NULL\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\trte_free(port);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_frag_reader_stats_read(void *port,\n\t\tstruct rte_port_in_stats *stats, int clear)\n{\n\tstruct rte_port_ring_reader_frag *p =\n\t\t(struct rte_port_ring_reader_frag *) port;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &p->stats, sizeof(p->stats));\n\n\tif (clear)\n\t\tmemset(&p->stats, 0, sizeof(p->stats));\n\n\treturn 0;\n}\n\n/*\n * Summary of port operations\n */\nstruct rte_port_in_ops rte_port_ring_reader_ipv4_frag_ops = {\n\t.f_create = rte_port_ring_reader_ipv4_frag_create,\n\t.f_free = rte_port_ring_reader_frag_free,\n\t.f_rx = rte_port_ring_reader_frag_rx,\n\t.f_stats = rte_port_frag_reader_stats_read,\n};\n\nstruct rte_port_in_ops rte_port_ring_reader_ipv6_frag_ops = {\n\t.f_create = rte_port_ring_reader_ipv6_frag_create,\n\t.f_free = rte_port_ring_reader_frag_free,\n\t.f_rx = rte_port_ring_reader_frag_rx,\n\t.f_stats = rte_port_frag_reader_stats_read,\n};\n" }, { "path": "lib/librte_port/rte_port_frag.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_PORT_IP_FRAG_H__\n#define __INCLUDE_RTE_PORT_IP_FRAG_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Port for IPv4 Fragmentation\n *\n * This port is built on top of pre-initialized single consumer rte_ring. In\n * order to minimize the amount of packets stored in the ring at any given\n * time, the IP fragmentation functionality is executed on ring read operation,\n * hence this port is implemented as an input port. A regular ring_writer port\n * can be created to write to the same ring.\n *\n * The packets written to the ring are either complete IP datagrams or jumbo\n * frames (i.e. IP packets with length bigger than provided MTU value). The\n * packets read from the ring are all non-jumbo frames. The complete IP\n * datagrams written to the ring are not changed. The jumbo frames are\n * fragmented into several IP packets with length less or equal to MTU.\n *\n ***/\n\n#include \n\n#include \n\n#include \"rte_port.h\"\n\n/** ring_reader_ipv4_frag port parameters */\nstruct rte_port_ring_reader_frag_params {\n\t/** Underlying single consumer ring that has to be pre-initialized. */\n\tstruct rte_ring *ring;\n\n\t/** Maximum Transfer Unit (MTU). Maximum IP packet size (in bytes). */\n\tuint32_t mtu;\n\n\t/** Size of application dependent meta-data stored per each input packet\n\t that has to be copied to each of the fragments originating from the\n\t same input IP datagram. */\n\tuint32_t metadata_size;\n\n\t/** Pre-initialized buffer pool used for allocating direct buffers for\n\t the output fragments. */\n\tstruct rte_mempool *pool_direct;\n\n\t/** Pre-initialized buffer pool used for allocating indirect buffers for\n\t the output fragments. */\n\tstruct rte_mempool *pool_indirect;\n};\n\n#define rte_port_ring_reader_ipv4_frag_params rte_port_ring_reader_frag_params\n\n#define rte_port_ring_reader_ipv6_frag_params rte_port_ring_reader_frag_params\n\n/** ring_reader_ipv4_frag port operations */\nextern struct rte_port_in_ops rte_port_ring_reader_ipv4_frag_ops;\n\n/** ring_reader_ipv6_frag port operations */\nextern struct rte_port_in_ops rte_port_ring_reader_ipv6_frag_ops;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_port/rte_port_ras.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n\n#include \n#include \n#include \n#include \n\n#include \"rte_port_ras.h\"\n\n#ifndef RTE_PORT_RAS_N_BUCKETS\n#define RTE_PORT_RAS_N_BUCKETS 4094\n#endif\n\n#ifndef RTE_PORT_RAS_N_ENTRIES_PER_BUCKET\n#define RTE_PORT_RAS_N_ENTRIES_PER_BUCKET 8\n#endif\n\n#ifndef RTE_PORT_RAS_N_ENTRIES\n#define RTE_PORT_RAS_N_ENTRIES (RTE_PORT_RAS_N_BUCKETS * RTE_PORT_RAS_N_ENTRIES_PER_BUCKET)\n#endif\n\n#ifdef RTE_PORT_STATS_COLLECT\n\n#define RTE_PORT_RING_WRITER_RAS_STATS_PKTS_IN_ADD(port, val) \\\n\tport->stats.n_pkts_in += val\n#define RTE_PORT_RING_WRITER_RAS_STATS_PKTS_DROP_ADD(port, val) \\\n\tport->stats.n_pkts_drop += val\n\n#else\n\n#define RTE_PORT_RING_WRITER_RAS_STATS_PKTS_IN_ADD(port, val)\n#define RTE_PORT_RING_WRITER_RAS_STATS_PKTS_DROP_ADD(port, val)\n\n#endif\n\nstruct rte_port_ring_writer_ras;\n\ntypedef void (*ras_op)(\n\t\tstruct rte_port_ring_writer_ras *p,\n\t\tstruct rte_mbuf *pkt);\n\nstatic void\nprocess_ipv4(struct rte_port_ring_writer_ras *p, struct rte_mbuf *pkt);\nstatic void\nprocess_ipv6(struct rte_port_ring_writer_ras *p, struct rte_mbuf *pkt);\n\nstruct rte_port_ring_writer_ras {\n\tstruct rte_port_out_stats stats;\n\n\tstruct rte_mbuf *tx_buf[RTE_PORT_IN_BURST_SIZE_MAX];\n\tstruct rte_ring *ring;\n\tuint32_t tx_burst_sz;\n\tuint32_t tx_buf_count;\n\tstruct rte_ip_frag_tbl *frag_tbl;\n\tstruct rte_ip_frag_death_row death_row;\n\n\tras_op f_ras;\n};\n\nstatic void *\nrte_port_ring_writer_ras_create(void *params, int socket_id, int is_ipv4)\n{\n\tstruct rte_port_ring_writer_ras_params *conf =\n\t\t\t(struct rte_port_ring_writer_ras_params *) params;\n\tstruct rte_port_ring_writer_ras *port;\n\tuint64_t frag_cycles;\n\n\t/* Check input parameters */\n\tif (conf == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Parameter conf is NULL\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tif (conf->ring == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Parameter ring is NULL\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tif ((conf->tx_burst_sz == 0) ||\n\t (conf->tx_burst_sz > RTE_PORT_IN_BURST_SIZE_MAX)) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Parameter tx_burst_sz is invalid\\n\",\n\t\t\t__func__);\n\t\treturn NULL;\n\t}\n\n\t/* Memory allocation */\n\tport = rte_zmalloc_socket(\"PORT\", sizeof(*port),\n\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Failed to allocate socket\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Create fragmentation table */\n\tfrag_cycles = (rte_get_tsc_hz() + MS_PER_S - 1) / MS_PER_S * MS_PER_S;\n\tfrag_cycles *= 100;\n\n\tport->frag_tbl = rte_ip_frag_table_create(\n\t\tRTE_PORT_RAS_N_BUCKETS,\n\t\tRTE_PORT_RAS_N_ENTRIES_PER_BUCKET,\n\t\tRTE_PORT_RAS_N_ENTRIES,\n\t\tfrag_cycles,\n\t\tsocket_id);\n\n\tif (port->frag_tbl == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: rte_ip_frag_table_create failed\\n\",\n\t\t\t__func__);\n\t\trte_free(port);\n\t\treturn NULL;\n\t}\n\n\t/* Initialization */\n\tport->ring = conf->ring;\n\tport->tx_burst_sz = conf->tx_burst_sz;\n\tport->tx_buf_count = 0;\n\n\tport->f_ras = (is_ipv4 == 0) ? process_ipv4 : process_ipv6;\n\n\treturn port;\n}\n\nstatic void *\nrte_port_ring_writer_ipv4_ras_create(void *params, int socket_id)\n{\n\treturn rte_port_ring_writer_ras_create(params, socket_id, 1);\n}\n\nstatic void *\nrte_port_ring_writer_ipv6_ras_create(void *params, int socket_id)\n{\n\treturn rte_port_ring_writer_ras_create(params, socket_id, 0);\n}\n\nstatic inline void\nsend_burst(struct rte_port_ring_writer_ras *p)\n{\n\tuint32_t nb_tx;\n\n\tnb_tx = rte_ring_sp_enqueue_burst(p->ring, (void **)p->tx_buf,\n\t\t\tp->tx_buf_count);\n\n\tRTE_PORT_RING_WRITER_RAS_STATS_PKTS_DROP_ADD(p, p->tx_buf_count - nb_tx);\n\tfor ( ; nb_tx < p->tx_buf_count; nb_tx++)\n\t\trte_pktmbuf_free(p->tx_buf[nb_tx]);\n\n\tp->tx_buf_count = 0;\n}\n\nstatic void\nprocess_ipv4(struct rte_port_ring_writer_ras *p, struct rte_mbuf *pkt)\n{\n\t/* Assume there is no ethernet header */\n\tstruct ipv4_hdr *pkt_hdr = rte_pktmbuf_mtod(pkt, struct ipv4_hdr *);\n\n\t/* Get \"Do not fragment\" flag and fragment offset */\n\tuint16_t frag_field = rte_be_to_cpu_16(pkt_hdr->fragment_offset);\n\tuint16_t frag_offset = (uint16_t)(frag_field & IPV4_HDR_OFFSET_MASK);\n\tuint16_t frag_flag = (uint16_t)(frag_field & IPV4_HDR_MF_FLAG);\n\n\t/* If it is a fragmented packet, then try to reassemble */\n\tif ((frag_flag == 0) && (frag_offset == 0))\n\t\tp->tx_buf[p->tx_buf_count++] = pkt;\n\telse {\n\t\tstruct rte_mbuf *mo;\n\t\tstruct rte_ip_frag_tbl *tbl = p->frag_tbl;\n\t\tstruct rte_ip_frag_death_row *dr = &p->death_row;\n\n\t\t/* Process this fragment */\n\t\tmo = rte_ipv4_frag_reassemble_packet(tbl, dr, pkt, rte_rdtsc(),\n\t\t\t\tpkt_hdr);\n\t\tif (mo != NULL)\n\t\t\tp->tx_buf[p->tx_buf_count++] = mo;\n\n\t\trte_ip_frag_free_death_row(&p->death_row, 3);\n\t}\n}\n\nstatic void\nprocess_ipv6(struct rte_port_ring_writer_ras *p, struct rte_mbuf *pkt)\n{\n\t/* Assume there is no ethernet header */\n\tstruct ipv6_hdr *pkt_hdr = rte_pktmbuf_mtod(pkt, struct ipv6_hdr *);\n\n\tstruct ipv6_extension_fragment *frag_hdr;\n\tfrag_hdr = rte_ipv6_frag_get_ipv6_fragment_header(pkt_hdr);\n\tuint16_t frag_offset = frag_hdr->frag_offset;\n\tuint16_t frag_flag = frag_hdr->more_frags;\n\n\t/* If it is a fragmented packet, then try to reassemble */\n\tif ((frag_flag == 0) && (frag_offset == 0))\n\t\tp->tx_buf[p->tx_buf_count++] = pkt;\n\telse {\n\t\tstruct rte_mbuf *mo;\n\t\tstruct rte_ip_frag_tbl *tbl = p->frag_tbl;\n\t\tstruct rte_ip_frag_death_row *dr = &p->death_row;\n\n\t\t/* Process this fragment */\n\t\tmo = rte_ipv6_frag_reassemble_packet(tbl, dr, pkt, rte_rdtsc(), pkt_hdr,\n\t\t\t\tfrag_hdr);\n\t\tif (mo != NULL)\n\t\t\tp->tx_buf[p->tx_buf_count++] = mo;\n\n\t\trte_ip_frag_free_death_row(&p->death_row, 3);\n\t}\n}\n\nstatic int\nrte_port_ring_writer_ras_tx(void *port, struct rte_mbuf *pkt)\n{\n\tstruct rte_port_ring_writer_ras *p =\n\t\t\t(struct rte_port_ring_writer_ras *) port;\n\n\tRTE_PORT_RING_WRITER_RAS_STATS_PKTS_IN_ADD(p, 1);\n\tp->f_ras(p, pkt);\n\tif (p->tx_buf_count >= p->tx_burst_sz)\n\t\tsend_burst(p);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ring_writer_ras_tx_bulk(void *port,\n\t\tstruct rte_mbuf **pkts,\n\t\tuint64_t pkts_mask)\n{\n\tstruct rte_port_ring_writer_ras *p =\n\t\t\t(struct rte_port_ring_writer_ras *) port;\n\n\tif ((pkts_mask & (pkts_mask + 1)) == 0) {\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_mask);\n\t\tuint32_t i;\n\n\t\tfor (i = 0; i < n_pkts; i++) {\n\t\t\tstruct rte_mbuf *pkt = pkts[i];\n\n\t\t\tRTE_PORT_RING_WRITER_RAS_STATS_PKTS_IN_ADD(p, 1);\n\t\t\tp->f_ras(p, pkt);\n\t\t\tif (p->tx_buf_count >= p->tx_burst_sz)\n\t\t\t\tsend_burst(p);\n\t\t}\n\t} else {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tuint32_t pkt_index = __builtin_ctzll(pkts_mask);\n\t\t\tuint64_t pkt_mask = 1LLU << pkt_index;\n\t\t\tstruct rte_mbuf *pkt = pkts[pkt_index];\n\n\t\t\tRTE_PORT_RING_WRITER_RAS_STATS_PKTS_IN_ADD(p, 1);\n\t\t\tp->f_ras(p, pkt);\n\t\t\tif (p->tx_buf_count >= p->tx_burst_sz)\n\t\t\t\tsend_burst(p);\n\n\t\t\tpkts_mask &= ~pkt_mask;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ring_writer_ras_flush(void *port)\n{\n\tstruct rte_port_ring_writer_ras *p =\n\t\t\t(struct rte_port_ring_writer_ras *) port;\n\n\tif (p->tx_buf_count > 0)\n\t\tsend_burst(p);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ring_writer_ras_free(void *port)\n{\n\tstruct rte_port_ring_writer_ras *p =\n\t\t\t(struct rte_port_ring_writer_ras *) port;\n\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Parameter port is NULL\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\trte_port_ring_writer_ras_flush(port);\n\trte_ip_frag_table_destroy(p->frag_tbl);\n\trte_free(port);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ras_writer_stats_read(void *port,\n\t\tstruct rte_port_out_stats *stats, int clear)\n{\n\tstruct rte_port_ring_writer_ras *p =\n\t\t(struct rte_port_ring_writer_ras *) port;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &p->stats, sizeof(p->stats));\n\n\tif (clear)\n\t\tmemset(&p->stats, 0, sizeof(p->stats));\n\n\treturn 0;\n}\n\n/*\n * Summary of port operations\n */\nstruct rte_port_out_ops rte_port_ring_writer_ipv4_ras_ops = {\n\t.f_create = rte_port_ring_writer_ipv4_ras_create,\n\t.f_free = rte_port_ring_writer_ras_free,\n\t.f_tx = rte_port_ring_writer_ras_tx,\n\t.f_tx_bulk = rte_port_ring_writer_ras_tx_bulk,\n\t.f_flush = rte_port_ring_writer_ras_flush,\n\t.f_stats = rte_port_ras_writer_stats_read,\n};\n\nstruct rte_port_out_ops rte_port_ring_writer_ipv6_ras_ops = {\n\t.f_create = rte_port_ring_writer_ipv6_ras_create,\n\t.f_free = rte_port_ring_writer_ras_free,\n\t.f_tx = rte_port_ring_writer_ras_tx,\n\t.f_tx_bulk = rte_port_ring_writer_ras_tx_bulk,\n\t.f_flush = rte_port_ring_writer_ras_flush,\n\t.f_stats = rte_port_ras_writer_stats_read,\n};\n" }, { "path": "lib/librte_port/rte_port_ras.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_PORT_RAS_H__\n#define __INCLUDE_RTE_PORT_RAS_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Port for IPv4 Reassembly\n *\n * This port is built on top of pre-initialized single producer rte_ring. In\n * order to minimize the amount of packets stored in the ring at any given\n * time, the IP reassembly functionality is executed on ring write operation,\n * hence this port is implemented as an output port. A regular ring_reader port\n * can be created to read from the same ring.\n *\n * The packets written to the ring are either complete IP datagrams or IP\n * fragments. The packets read from the ring are all complete IP datagrams,\n * either jumbo frames (i.e. IP packets with length bigger than MTU) or not.\n * The complete IP datagrams written to the ring are not changed. The IP\n * fragments written to the ring are first reassembled and into complete IP\n * datagrams or dropped on error or IP reassembly time-out.\n *\n ***/\n\n#include \n\n#include \n\n#include \"rte_port.h\"\n\n/** ring_writer_ipv4_ras port parameters */\nstruct rte_port_ring_writer_ras_params {\n\t/** Underlying single consumer ring that has to be pre-initialized. */\n\tstruct rte_ring *ring;\n\n\t/** Recommended burst size to ring. The actual burst size can be bigger\n\tor smaller than this value. */\n\tuint32_t tx_burst_sz;\n};\n\n#define rte_port_ring_writer_ipv4_ras_params rte_port_ring_writer_ras_params\n\n#define rte_port_ring_writer_ipv6_ras_params rte_port_ring_writer_ras_params\n\n/** ring_writer_ipv4_ras port operations */\nextern struct rte_port_out_ops rte_port_ring_writer_ipv4_ras_ops;\n\n/** ring_writer_ipv6_ras port operations */\nextern struct rte_port_out_ops rte_port_ring_writer_ipv6_ras_ops;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_port/rte_port_ring.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n\n#include \n#include \n#include \n\n#include \"rte_port_ring.h\"\n\n/*\n * Port RING Reader\n */\n#ifdef RTE_PORT_STATS_COLLECT\n\n#define RTE_PORT_RING_READER_STATS_PKTS_IN_ADD(port, val) \\\n\tport->stats.n_pkts_in += val\n#define RTE_PORT_RING_READER_STATS_PKTS_DROP_ADD(port, val) \\\n\tport->stats.n_pkts_drop += val\n\n#else\n\n#define RTE_PORT_RING_READER_STATS_PKTS_IN_ADD(port, val)\n#define RTE_PORT_RING_READER_STATS_PKTS_DROP_ADD(port, val)\n\n#endif\n\nstruct rte_port_ring_reader {\n\tstruct rte_port_in_stats stats;\n\n\tstruct rte_ring *ring;\n};\n\nstatic void *\nrte_port_ring_reader_create(void *params, int socket_id)\n{\n\tstruct rte_port_ring_reader_params *conf =\n\t\t\t(struct rte_port_ring_reader_params *) params;\n\tstruct rte_port_ring_reader *port;\n\n\t/* Check input parameters */\n\tif (conf == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: params is NULL\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Memory allocation */\n\tport = rte_zmalloc_socket(\"PORT\", sizeof(*port),\n\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Failed to allocate port\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Initialization */\n\tport->ring = conf->ring;\n\n\treturn port;\n}\n\nstatic int\nrte_port_ring_reader_rx(void *port, struct rte_mbuf **pkts, uint32_t n_pkts)\n{\n\tstruct rte_port_ring_reader *p = (struct rte_port_ring_reader *) port;\n\tuint32_t nb_rx;\n\n\tnb_rx = rte_ring_sc_dequeue_burst(p->ring, (void **) pkts, n_pkts);\n\tRTE_PORT_RING_READER_STATS_PKTS_IN_ADD(p, nb_rx);\n\n\treturn nb_rx;\n}\n\nstatic int\nrte_port_ring_reader_free(void *port)\n{\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: port is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_free(port);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ring_reader_stats_read(void *port,\n\t\tstruct rte_port_in_stats *stats, int clear)\n{\n\tstruct rte_port_ring_reader *p =\n\t\t(struct rte_port_ring_reader *) port;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &p->stats, sizeof(p->stats));\n\n\tif (clear)\n\t\tmemset(&p->stats, 0, sizeof(p->stats));\n\n\treturn 0;\n}\n\n/*\n * Port RING Writer\n */\n#ifdef RTE_PORT_STATS_COLLECT\n\n#define RTE_PORT_RING_WRITER_STATS_PKTS_IN_ADD(port, val) \\\n\tport->stats.n_pkts_in += val\n#define RTE_PORT_RING_WRITER_STATS_PKTS_DROP_ADD(port, val) \\\n\tport->stats.n_pkts_drop += val\n\n#else\n\n#define RTE_PORT_RING_WRITER_STATS_PKTS_IN_ADD(port, val)\n#define RTE_PORT_RING_WRITER_STATS_PKTS_DROP_ADD(port, val)\n\n#endif\n\nstruct rte_port_ring_writer {\n\tstruct rte_port_out_stats stats;\n\n\tstruct rte_mbuf *tx_buf[RTE_PORT_IN_BURST_SIZE_MAX];\n\tstruct rte_ring *ring;\n\tuint32_t tx_burst_sz;\n\tuint32_t tx_buf_count;\n\tuint64_t bsz_mask;\n};\n\nstatic void *\nrte_port_ring_writer_create(void *params, int socket_id)\n{\n\tstruct rte_port_ring_writer_params *conf =\n\t\t\t(struct rte_port_ring_writer_params *) params;\n\tstruct rte_port_ring_writer *port;\n\n\t/* Check input parameters */\n\tif ((conf == NULL) ||\n\t (conf->ring == NULL) ||\n\t\t(conf->tx_burst_sz > RTE_PORT_IN_BURST_SIZE_MAX)) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Invalid Parameters\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Memory allocation */\n\tport = rte_zmalloc_socket(\"PORT\", sizeof(*port),\n\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Failed to allocate port\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Initialization */\n\tport->ring = conf->ring;\n\tport->tx_burst_sz = conf->tx_burst_sz;\n\tport->tx_buf_count = 0;\n\tport->bsz_mask = 1LLU << (conf->tx_burst_sz - 1);\n\n\treturn port;\n}\n\nstatic inline void\nsend_burst(struct rte_port_ring_writer *p)\n{\n\tuint32_t nb_tx;\n\n\tnb_tx = rte_ring_sp_enqueue_burst(p->ring, (void **)p->tx_buf,\n\t\t\tp->tx_buf_count);\n\n\tRTE_PORT_RING_WRITER_STATS_PKTS_DROP_ADD(p, p->tx_buf_count - nb_tx);\n\tfor ( ; nb_tx < p->tx_buf_count; nb_tx++)\n\t\trte_pktmbuf_free(p->tx_buf[nb_tx]);\n\n\tp->tx_buf_count = 0;\n}\n\nstatic int\nrte_port_ring_writer_tx(void *port, struct rte_mbuf *pkt)\n{\n\tstruct rte_port_ring_writer *p = (struct rte_port_ring_writer *) port;\n\n\tp->tx_buf[p->tx_buf_count++] = pkt;\n\tRTE_PORT_RING_WRITER_STATS_PKTS_IN_ADD(p, 1);\n\tif (p->tx_buf_count >= p->tx_burst_sz)\n\t\tsend_burst(p);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ring_writer_tx_bulk(void *port,\n\t\tstruct rte_mbuf **pkts,\n\t\tuint64_t pkts_mask)\n{\n\tstruct rte_port_ring_writer *p =\n\t\t(struct rte_port_ring_writer *) port;\n\n\tuint32_t bsz_mask = p->bsz_mask;\n\tuint32_t tx_buf_count = p->tx_buf_count;\n\tuint64_t expr = (pkts_mask & (pkts_mask + 1)) |\n\t\t\t((pkts_mask & bsz_mask) ^ bsz_mask);\n\n\tif (expr == 0) {\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_mask);\n\t\tuint32_t n_pkts_ok;\n\n\t\tif (tx_buf_count)\n\t\t\tsend_burst(p);\n\n\t\tRTE_PORT_RING_WRITER_STATS_PKTS_IN_ADD(p, n_pkts);\n\t\tn_pkts_ok = rte_ring_sp_enqueue_burst(p->ring, (void **)pkts, n_pkts);\n\n\t\tRTE_PORT_RING_WRITER_STATS_PKTS_DROP_ADD(p, n_pkts - n_pkts_ok);\n\t\tfor ( ; n_pkts_ok < n_pkts; n_pkts_ok++) {\n\t\t\tstruct rte_mbuf *pkt = pkts[n_pkts_ok];\n\n\t\t\trte_pktmbuf_free(pkt);\n\t\t}\n\t} else {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tuint32_t pkt_index = __builtin_ctzll(pkts_mask);\n\t\t\tuint64_t pkt_mask = 1LLU << pkt_index;\n\t\t\tstruct rte_mbuf *pkt = pkts[pkt_index];\n\n\t\t\tp->tx_buf[tx_buf_count++] = pkt;\n\t\t\tRTE_PORT_RING_WRITER_STATS_PKTS_IN_ADD(p, 1);\n\t\t\tpkts_mask &= ~pkt_mask;\n\t\t}\n\n\t\tp->tx_buf_count = tx_buf_count;\n\t\tif (tx_buf_count >= p->tx_burst_sz)\n\t\t\tsend_burst(p);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ring_writer_flush(void *port)\n{\n\tstruct rte_port_ring_writer *p = (struct rte_port_ring_writer *) port;\n\n\tif (p->tx_buf_count > 0)\n\t\tsend_burst(p);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ring_writer_free(void *port)\n{\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Port is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_port_ring_writer_flush(port);\n\trte_free(port);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ring_writer_stats_read(void *port,\n\t\tstruct rte_port_out_stats *stats, int clear)\n{\n\tstruct rte_port_ring_writer *p =\n\t\t(struct rte_port_ring_writer *) port;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &p->stats, sizeof(p->stats));\n\n\tif (clear)\n\t\tmemset(&p->stats, 0, sizeof(p->stats));\n\n\treturn 0;\n}\n\n/*\n * Port RING Writer Nodrop\n */\n#ifdef RTE_PORT_STATS_COLLECT\n\n#define RTE_PORT_RING_WRITER_NODROP_STATS_PKTS_IN_ADD(port, val) \\\n\tport->stats.n_pkts_in += val\n#define RTE_PORT_RING_WRITER_NODROP_STATS_PKTS_DROP_ADD(port, val) \\\n\tport->stats.n_pkts_drop += val\n\n#else\n\n#define RTE_PORT_RING_WRITER_NODROP_STATS_PKTS_IN_ADD(port, val)\n#define RTE_PORT_RING_WRITER_NODROP_STATS_PKTS_DROP_ADD(port, val)\n\n#endif\n\nstruct rte_port_ring_writer_nodrop {\n\tstruct rte_port_out_stats stats;\n\n\tstruct rte_mbuf *tx_buf[RTE_PORT_IN_BURST_SIZE_MAX];\n\tstruct rte_ring *ring;\n\tuint32_t tx_burst_sz;\n\tuint32_t tx_buf_count;\n\tuint64_t bsz_mask;\n\tuint64_t n_retries;\n};\n\nstatic void *\nrte_port_ring_writer_nodrop_create(void *params, int socket_id)\n{\n\tstruct rte_port_ring_writer_nodrop_params *conf =\n\t\t\t(struct rte_port_ring_writer_nodrop_params *) params;\n\tstruct rte_port_ring_writer_nodrop *port;\n\n\t/* Check input parameters */\n\tif ((conf == NULL) ||\n\t (conf->ring == NULL) ||\n\t\t(conf->tx_burst_sz > RTE_PORT_IN_BURST_SIZE_MAX)) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Invalid Parameters\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Memory allocation */\n\tport = rte_zmalloc_socket(\"PORT\", sizeof(*port),\n\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Failed to allocate port\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Initialization */\n\tport->ring = conf->ring;\n\tport->tx_burst_sz = conf->tx_burst_sz;\n\tport->tx_buf_count = 0;\n\tport->bsz_mask = 1LLU << (conf->tx_burst_sz - 1);\n\n\t/*\n\t * When n_retries is 0 it means that we should wait for every packet to\n\t * send no matter how many retries should it take. To limit number of\n\t * branches in fast path, we use UINT64_MAX instead of branching.\n\t */\n\tport->n_retries = (conf->n_retries == 0) ? UINT64_MAX : conf->n_retries;\n\n\treturn port;\n}\n\nstatic inline void\nsend_burst_nodrop(struct rte_port_ring_writer_nodrop *p)\n{\n\tuint32_t nb_tx = 0, i;\n\n\tnb_tx = rte_ring_sp_enqueue_burst(p->ring, (void **)p->tx_buf,\n\t\t\t\tp->tx_buf_count);\n\n\t/* We sent all the packets in a first try */\n\tif (nb_tx >= p->tx_buf_count)\n\t\treturn;\n\n\tfor (i = 0; i < p->n_retries; i++) {\n\t\tnb_tx += rte_ring_sp_enqueue_burst(p->ring,\n\t\t\t\t(void **) (p->tx_buf + nb_tx), p->tx_buf_count - nb_tx);\n\n\t\t/* We sent all the packets in more than one try */\n\t\tif (nb_tx >= p->tx_buf_count)\n\t\t\treturn;\n\t}\n\n\t/* We didn't send the packets in maximum allowed attempts */\n\tRTE_PORT_RING_WRITER_NODROP_STATS_PKTS_DROP_ADD(p, p->tx_buf_count - nb_tx);\n\tfor ( ; nb_tx < p->tx_buf_count; nb_tx++)\n\t\trte_pktmbuf_free(p->tx_buf[nb_tx]);\n\n\tp->tx_buf_count = 0;\n}\n\nstatic int\nrte_port_ring_writer_nodrop_tx(void *port, struct rte_mbuf *pkt)\n{\n\tstruct rte_port_ring_writer_nodrop *p =\n\t\t\t(struct rte_port_ring_writer_nodrop *) port;\n\n\tp->tx_buf[p->tx_buf_count++] = pkt;\n\tRTE_PORT_RING_WRITER_NODROP_STATS_PKTS_IN_ADD(p, 1);\n\tif (p->tx_buf_count >= p->tx_burst_sz)\n\t\tsend_burst_nodrop(p);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ring_writer_nodrop_tx_bulk(void *port,\n\t\tstruct rte_mbuf **pkts,\n\t\tuint64_t pkts_mask)\n{\n\tstruct rte_port_ring_writer_nodrop *p =\n\t\t(struct rte_port_ring_writer_nodrop *) port;\n\n\tuint32_t bsz_mask = p->bsz_mask;\n\tuint32_t tx_buf_count = p->tx_buf_count;\n\tuint64_t expr = (pkts_mask & (pkts_mask + 1)) |\n\t\t\t((pkts_mask & bsz_mask) ^ bsz_mask);\n\n\tif (expr == 0) {\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_mask);\n\t\tuint32_t n_pkts_ok;\n\n\t\tif (tx_buf_count)\n\t\t\tsend_burst_nodrop(p);\n\n\t\tRTE_PORT_RING_WRITER_NODROP_STATS_PKTS_IN_ADD(p, n_pkts);\n\t\tn_pkts_ok = rte_ring_sp_enqueue_burst(p->ring, (void **)pkts, n_pkts);\n\n\t\tif (n_pkts_ok >= n_pkts)\n\t\t\treturn 0;\n\n\t\t/*\n\t\t * If we didnt manage to send all packets in single burst, move\n\t\t * remaining packets to the buffer and call send burst.\n\t\t */\n\t\tfor (; n_pkts_ok < n_pkts; n_pkts_ok++) {\n\t\t\tstruct rte_mbuf *pkt = pkts[n_pkts_ok];\n\t\t\tp->tx_buf[p->tx_buf_count++] = pkt;\n\t\t}\n\t\tsend_burst_nodrop(p);\n\t} else {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tuint32_t pkt_index = __builtin_ctzll(pkts_mask);\n\t\t\tuint64_t pkt_mask = 1LLU << pkt_index;\n\t\t\tstruct rte_mbuf *pkt = pkts[pkt_index];\n\n\t\t\tp->tx_buf[tx_buf_count++] = pkt;\n\t\t\tRTE_PORT_RING_WRITER_NODROP_STATS_PKTS_IN_ADD(p, 1);\n\t\t\tpkts_mask &= ~pkt_mask;\n\t\t}\n\n\t\tp->tx_buf_count = tx_buf_count;\n\t\tif (tx_buf_count >= p->tx_burst_sz)\n\t\t\tsend_burst_nodrop(p);\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ring_writer_nodrop_flush(void *port)\n{\n\tstruct rte_port_ring_writer_nodrop *p =\n\t\t\t(struct rte_port_ring_writer_nodrop *) port;\n\n\tif (p->tx_buf_count > 0)\n\t\tsend_burst_nodrop(p);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ring_writer_nodrop_free(void *port)\n{\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Port is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_port_ring_writer_nodrop_flush(port);\n\trte_free(port);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_ring_writer_nodrop_stats_read(void *port,\n\t\tstruct rte_port_out_stats *stats, int clear)\n{\n\tstruct rte_port_ring_writer_nodrop *p =\n\t\t(struct rte_port_ring_writer_nodrop *) port;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &p->stats, sizeof(p->stats));\n\n\tif (clear)\n\t\tmemset(&p->stats, 0, sizeof(p->stats));\n\n\treturn 0;\n}\n\n/*\n * Summary of port operations\n */\nstruct rte_port_in_ops rte_port_ring_reader_ops = {\n\t.f_create = rte_port_ring_reader_create,\n\t.f_free = rte_port_ring_reader_free,\n\t.f_rx = rte_port_ring_reader_rx,\n\t.f_stats = rte_port_ring_reader_stats_read,\n};\n\nstruct rte_port_out_ops rte_port_ring_writer_ops = {\n\t.f_create = rte_port_ring_writer_create,\n\t.f_free = rte_port_ring_writer_free,\n\t.f_tx = rte_port_ring_writer_tx,\n\t.f_tx_bulk = rte_port_ring_writer_tx_bulk,\n\t.f_flush = rte_port_ring_writer_flush,\n\t.f_stats = rte_port_ring_writer_stats_read,\n};\n\nstruct rte_port_out_ops rte_port_ring_writer_nodrop_ops = {\n\t.f_create = rte_port_ring_writer_nodrop_create,\n\t.f_free = rte_port_ring_writer_nodrop_free,\n\t.f_tx = rte_port_ring_writer_nodrop_tx,\n\t.f_tx_bulk = rte_port_ring_writer_nodrop_tx_bulk,\n\t.f_flush = rte_port_ring_writer_nodrop_flush,\n\t.f_stats = rte_port_ring_writer_nodrop_stats_read,\n};\n" }, { "path": "lib/librte_port/rte_port_ring.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_PORT_RING_H__\n#define __INCLUDE_RTE_PORT_RING_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Port Ring\n *\n * ring_reader: input port built on top of pre-initialized single consumer ring\n * ring_writer: output port built on top of pre-initialized single producer ring\n *\n ***/\n\n#include \n\n#include \n\n#include \"rte_port.h\"\n\n/** ring_reader port parameters */\nstruct rte_port_ring_reader_params {\n\t/** Underlying single consumer ring that has to be pre-initialized */\n\tstruct rte_ring *ring;\n};\n\n/** ring_reader port operations */\nextern struct rte_port_in_ops rte_port_ring_reader_ops;\n\n/** ring_writer port parameters */\nstruct rte_port_ring_writer_params {\n\t/** Underlying single producer ring that has to be pre-initialized */\n\tstruct rte_ring *ring;\n\n\t/** Recommended burst size to ring. The actual burst size can be\n\t\tbigger or smaller than this value. */\n\tuint32_t tx_burst_sz;\n};\n\n/** ring_writer port operations */\nextern struct rte_port_out_ops rte_port_ring_writer_ops;\n\n/** ring_writer_nodrop port parameters */\nstruct rte_port_ring_writer_nodrop_params {\n\t/** Underlying single producer ring that has to be pre-initialized */\n\tstruct rte_ring *ring;\n\n\t/** Recommended burst size to ring. The actual burst size can be\n\t\tbigger or smaller than this value. */\n\tuint32_t tx_burst_sz;\n\n\t/** Maximum number of retries, 0 for no limit */\n\tuint32_t n_retries;\n};\n\n/** ring_writer_nodrop port operations */\nextern struct rte_port_out_ops rte_port_ring_writer_nodrop_ops;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_port/rte_port_sched.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n\n#include \n#include \n\n#include \"rte_port_sched.h\"\n\n/*\n * Reader\n */\n#ifdef RTE_PORT_STATS_COLLECT\n\n#define RTE_PORT_SCHED_READER_PKTS_IN_ADD(port, val) \\\n\tport->stats.n_pkts_in += val\n#define RTE_PORT_SCHED_READER_PKTS_DROP_ADD(port, val) \\\n\tport->stats.n_pkts_drop += val\n\n#else\n\n#define RTE_PORT_SCHED_READER_PKTS_IN_ADD(port, val)\n#define RTE_PORT_SCHED_READER_PKTS_DROP_ADD(port, val)\n\n#endif\n\nstruct rte_port_sched_reader {\n\tstruct rte_port_in_stats stats;\n\n\tstruct rte_sched_port *sched;\n};\n\nstatic void *\nrte_port_sched_reader_create(void *params, int socket_id)\n{\n\tstruct rte_port_sched_reader_params *conf =\n\t\t\t(struct rte_port_sched_reader_params *) params;\n\tstruct rte_port_sched_reader *port;\n\n\t/* Check input parameters */\n\tif ((conf == NULL) ||\n\t (conf->sched == NULL)) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Invalid params\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Memory allocation */\n\tport = rte_zmalloc_socket(\"PORT\", sizeof(*port),\n\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Failed to allocate port\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Initialization */\n\tport->sched = conf->sched;\n\n\treturn port;\n}\n\nstatic int\nrte_port_sched_reader_rx(void *port, struct rte_mbuf **pkts, uint32_t n_pkts)\n{\n\tstruct rte_port_sched_reader *p = (struct rte_port_sched_reader *) port;\n\tuint32_t nb_rx;\n\n\tnb_rx = rte_sched_port_dequeue(p->sched, pkts, n_pkts);\n\tRTE_PORT_SCHED_READER_PKTS_IN_ADD(p, nb_rx);\n\n\treturn nb_rx;\n}\n\nstatic int\nrte_port_sched_reader_free(void *port)\n{\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: port is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_free(port);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_sched_reader_stats_read(void *port,\n\t\tstruct rte_port_in_stats *stats, int clear)\n{\n\tstruct rte_port_sched_reader *p =\n\t\t(struct rte_port_sched_reader *) port;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &p->stats, sizeof(p->stats));\n\n\tif (clear)\n\t\tmemset(&p->stats, 0, sizeof(p->stats));\n\n\treturn 0;\n}\n\n/*\n * Writer\n */\n#ifdef RTE_PORT_STATS_COLLECT\n\n#define RTE_PORT_SCHED_WRITER_STATS_PKTS_IN_ADD(port, val) \\\n\tport->stats.n_pkts_in += val\n#define RTE_PORT_SCHED_WRITER_STATS_PKTS_DROP_ADD(port, val) \\\n\tport->stats.n_pkts_drop += val\n\n#else\n\n#define RTE_PORT_SCHED_WRITER_STATS_PKTS_IN_ADD(port, val)\n#define RTE_PORT_SCHED_WRITER_STATS_PKTS_DROP_ADD(port, val)\n\n#endif\n\nstruct rte_port_sched_writer {\n\tstruct rte_port_out_stats stats;\n\n\tstruct rte_mbuf *tx_buf[2 * RTE_PORT_IN_BURST_SIZE_MAX];\n\tstruct rte_sched_port *sched;\n\tuint32_t tx_burst_sz;\n\tuint32_t tx_buf_count;\n\tuint64_t bsz_mask;\n};\n\nstatic void *\nrte_port_sched_writer_create(void *params, int socket_id)\n{\n\tstruct rte_port_sched_writer_params *conf =\n\t\t\t(struct rte_port_sched_writer_params *) params;\n\tstruct rte_port_sched_writer *port;\n\n\t/* Check input parameters */\n\tif ((conf == NULL) ||\n\t (conf->sched == NULL) ||\n\t (conf->tx_burst_sz == 0) ||\n\t (conf->tx_burst_sz > RTE_PORT_IN_BURST_SIZE_MAX) ||\n\t\t(!rte_is_power_of_2(conf->tx_burst_sz))) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Invalid params\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Memory allocation */\n\tport = rte_zmalloc_socket(\"PORT\", sizeof(*port),\n\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Failed to allocate port\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Initialization */\n\tport->sched = conf->sched;\n\tport->tx_burst_sz = conf->tx_burst_sz;\n\tport->tx_buf_count = 0;\n\tport->bsz_mask = 1LLU << (conf->tx_burst_sz - 1);\n\n\treturn port;\n}\n\nstatic int\nrte_port_sched_writer_tx(void *port, struct rte_mbuf *pkt)\n{\n\tstruct rte_port_sched_writer *p = (struct rte_port_sched_writer *) port;\n\n\tp->tx_buf[p->tx_buf_count++] = pkt;\n\tRTE_PORT_SCHED_WRITER_STATS_PKTS_IN_ADD(p, 1);\n\tif (p->tx_buf_count >= p->tx_burst_sz) {\n\t\t__rte_unused uint32_t nb_tx;\n\n\t\tnb_tx = rte_sched_port_enqueue(p->sched, p->tx_buf, p->tx_buf_count);\n\t\tRTE_PORT_SCHED_WRITER_STATS_PKTS_DROP_ADD(p, p->tx_buf_count - nb_tx);\n\t\tp->tx_buf_count = 0;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_port_sched_writer_tx_bulk(void *port,\n\t\tstruct rte_mbuf **pkts,\n\t\tuint64_t pkts_mask)\n{\n\tstruct rte_port_sched_writer *p = (struct rte_port_sched_writer *) port;\n\tuint32_t bsz_mask = p->bsz_mask;\n\tuint32_t tx_buf_count = p->tx_buf_count;\n\tuint64_t expr = (pkts_mask & (pkts_mask + 1)) |\n\t\t\t((pkts_mask & bsz_mask) ^ bsz_mask);\n\n\tif (expr == 0) {\n\t\t__rte_unused uint32_t nb_tx;\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_mask);\n\n\t\tif (tx_buf_count) {\n\t\t\tnb_tx = rte_sched_port_enqueue(p->sched, p->tx_buf,\n\t\t\t\ttx_buf_count);\n\t\t\tRTE_PORT_SCHED_WRITER_STATS_PKTS_DROP_ADD(p, tx_buf_count - nb_tx);\n\t\t\tp->tx_buf_count = 0;\n\t\t}\n\n\t\tnb_tx = rte_sched_port_enqueue(p->sched, pkts, n_pkts);\n\t\tRTE_PORT_SCHED_WRITER_STATS_PKTS_DROP_ADD(p, n_pkts - nb_tx);\n\t} else {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tuint32_t pkt_index = __builtin_ctzll(pkts_mask);\n\t\t\tuint64_t pkt_mask = 1LLU << pkt_index;\n\t\t\tstruct rte_mbuf *pkt = pkts[pkt_index];\n\n\t\t\tp->tx_buf[tx_buf_count++] = pkt;\n\t\t\tRTE_PORT_SCHED_WRITER_STATS_PKTS_IN_ADD(p, 1);\n\t\t\tpkts_mask &= ~pkt_mask;\n\t\t}\n\t\tp->tx_buf_count = tx_buf_count;\n\n\t\tif (tx_buf_count >= p->tx_burst_sz) {\n\t\t\t__rte_unused uint32_t nb_tx;\n\n\t\t\tnb_tx = rte_sched_port_enqueue(p->sched, p->tx_buf,\n\t\t\t\ttx_buf_count);\n\t\t\tRTE_PORT_SCHED_WRITER_STATS_PKTS_DROP_ADD(p, tx_buf_count - nb_tx);\n\t\t\tp->tx_buf_count = 0;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_port_sched_writer_flush(void *port)\n{\n\tstruct rte_port_sched_writer *p = (struct rte_port_sched_writer *) port;\n\n\tif (p->tx_buf_count) {\n\t\t__rte_unused uint32_t nb_tx;\n\n\t\tnb_tx = rte_sched_port_enqueue(p->sched, p->tx_buf, p->tx_buf_count);\n\t\tRTE_PORT_SCHED_WRITER_STATS_PKTS_DROP_ADD(p, p->tx_buf_count - nb_tx);\n\t\tp->tx_buf_count = 0;\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_port_sched_writer_free(void *port)\n{\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: port is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_port_sched_writer_flush(port);\n\trte_free(port);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_sched_writer_stats_read(void *port,\n\t\tstruct rte_port_out_stats *stats, int clear)\n{\n\tstruct rte_port_sched_writer *p =\n\t\t(struct rte_port_sched_writer *) port;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &p->stats, sizeof(p->stats));\n\n\tif (clear)\n\t\tmemset(&p->stats, 0, sizeof(p->stats));\n\n\treturn 0;\n}\n\n/*\n * Summary of port operations\n */\nstruct rte_port_in_ops rte_port_sched_reader_ops = {\n\t.f_create = rte_port_sched_reader_create,\n\t.f_free = rte_port_sched_reader_free,\n\t.f_rx = rte_port_sched_reader_rx,\n\t.f_stats = rte_port_sched_reader_stats_read,\n};\n\nstruct rte_port_out_ops rte_port_sched_writer_ops = {\n\t.f_create = rte_port_sched_writer_create,\n\t.f_free = rte_port_sched_writer_free,\n\t.f_tx = rte_port_sched_writer_tx,\n\t.f_tx_bulk = rte_port_sched_writer_tx_bulk,\n\t.f_flush = rte_port_sched_writer_flush,\n\t.f_stats = rte_port_sched_writer_stats_read,\n};\n" }, { "path": "lib/librte_port/rte_port_sched.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_PORT_SCHED_H__\n#define __INCLUDE_RTE_PORT_SCHED_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Port Hierarchical Scheduler\n *\n * sched_reader: input port built on top of pre-initialized rte_sched_port\n * sched_writer: output port built on top of pre-initialized rte_sched_port\n *\n ***/\n\n#include \n\n#include \n\n#include \"rte_port.h\"\n\n/** sched_reader port parameters */\nstruct rte_port_sched_reader_params {\n\t/** Underlying pre-initialized rte_sched_port */\n\tstruct rte_sched_port *sched;\n};\n\n/** sched_reader port operations */\nextern struct rte_port_in_ops rte_port_sched_reader_ops;\n\n/** sched_writer port parameters */\nstruct rte_port_sched_writer_params {\n\t/** Underlying pre-initialized rte_sched_port */\n\tstruct rte_sched_port *sched;\n\n\t/** Recommended burst size. The actual burst size can be bigger or\n\tsmaller than this value. */\n\tuint32_t tx_burst_sz;\n};\n\n/** sched_writer port operations */\nextern struct rte_port_out_ops rte_port_sched_writer_ops;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_port/rte_port_source_sink.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n\n#include \n#include \n#include \n\n#include \"rte_port_source_sink.h\"\n\n/*\n * Port SOURCE\n */\n#ifdef RTE_PORT_STATS_COLLECT\n\n#define RTE_PORT_SOURCE_STATS_PKTS_IN_ADD(port, val) \\\n\tport->stats.n_pkts_in += val\n#define RTE_PORT_SOURCE_STATS_PKTS_DROP_ADD(port, val) \\\n\tport->stats.n_pkts_drop += val\n\n#else\n\n#define RTE_PORT_SOURCE_STATS_PKTS_IN_ADD(port, val)\n#define RTE_PORT_SOURCE_STATS_PKTS_DROP_ADD(port, val)\n\n#endif\n\nstruct rte_port_source {\n\tstruct rte_port_in_stats stats;\n\n\tstruct rte_mempool *mempool;\n};\n\nstatic void *\nrte_port_source_create(void *params, int socket_id)\n{\n\tstruct rte_port_source_params *p =\n\t\t\t(struct rte_port_source_params *) params;\n\tstruct rte_port_source *port;\n\n\t/* Check input arguments*/\n\tif ((p == NULL) || (p->mempool == NULL)) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Invalid params\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Memory allocation */\n\tport = rte_zmalloc_socket(\"PORT\", sizeof(*port),\n\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n\tif (port == NULL) {\n\t\tRTE_LOG(ERR, PORT, \"%s: Failed to allocate port\\n\", __func__);\n\t\treturn NULL;\n\t}\n\n\t/* Initialization */\n\tport->mempool = (struct rte_mempool *) p->mempool;\n\n\treturn port;\n}\n\nstatic int\nrte_port_source_free(void *port)\n{\n\t/* Check input parameters */\n\tif (port == NULL)\n\t\treturn 0;\n\n\trte_free(port);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_source_rx(void *port, struct rte_mbuf **pkts, uint32_t n_pkts)\n{\n\tstruct rte_port_source *p = (struct rte_port_source *) port;\n\n\tif (rte_mempool_get_bulk(p->mempool, (void **) pkts, n_pkts) != 0)\n\t\treturn 0;\n\n\tRTE_PORT_SOURCE_STATS_PKTS_IN_ADD(p, n_pkts);\n\n\treturn n_pkts;\n}\n\nstatic int\nrte_port_source_stats_read(void *port,\n\t\tstruct rte_port_in_stats *stats, int clear)\n{\n\tstruct rte_port_source *p =\n\t\t(struct rte_port_source *) port;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &p->stats, sizeof(p->stats));\n\n\tif (clear)\n\t\tmemset(&p->stats, 0, sizeof(p->stats));\n\n\treturn 0;\n}\n\n/*\n * Port SINK\n */\nstatic void *\nrte_port_sink_create(__rte_unused void *params, __rte_unused int socket_id)\n{\n\treturn (void *) 1;\n}\n\nstatic int\nrte_port_sink_tx(__rte_unused void *port, struct rte_mbuf *pkt)\n{\n\trte_pktmbuf_free(pkt);\n\n\treturn 0;\n}\n\nstatic int\nrte_port_sink_tx_bulk(__rte_unused void *port, struct rte_mbuf **pkts,\n\tuint64_t pkts_mask)\n{\n\tif ((pkts_mask & (pkts_mask + 1)) == 0) {\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_mask);\n\t\tuint32_t i;\n\n\t\tfor (i = 0; i < n_pkts; i++) {\n\t\t\tstruct rte_mbuf *pkt = pkts[i];\n\n\t\t\trte_pktmbuf_free(pkt);\n\t\t}\n\t} else {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tuint32_t pkt_index = __builtin_ctzll(pkts_mask);\n\t\t\tuint64_t pkt_mask = 1LLU << pkt_index;\n\t\t\tstruct rte_mbuf *pkt = pkts[pkt_index];\n\n\t\t\trte_pktmbuf_free(pkt);\n\t\t\tpkts_mask &= ~pkt_mask;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/*\n * Summary of port operations\n */\nstruct rte_port_in_ops rte_port_source_ops = {\n\t.f_create = rte_port_source_create,\n\t.f_free = rte_port_source_free,\n\t.f_rx = rte_port_source_rx,\n\t.f_stats = rte_port_source_stats_read,\n};\n\nstruct rte_port_out_ops rte_port_sink_ops = {\n\t.f_create = rte_port_sink_create,\n\t.f_free = NULL,\n\t.f_tx = rte_port_sink_tx,\n\t.f_tx_bulk = rte_port_sink_tx_bulk,\n\t.f_flush = NULL,\n};\n" }, { "path": "lib/librte_port/rte_port_source_sink.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_PORT_SOURCE_SINK_H__\n#define __INCLUDE_RTE_PORT_SOURCE_SINK_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Port Source/Sink\n *\n * source: input port that can be used to generate packets\n * sink: output port that drops all packets written to it\n *\n ***/\n\n#include \"rte_port.h\"\n\n/** source port parameters */\nstruct rte_port_source_params {\n\t/** Pre-initialized buffer pool */\n\tstruct rte_mempool *mempool;\n};\n\n/** source port operations */\nextern struct rte_port_in_ops rte_port_source_ops;\n\n/** sink port parameters: NONE */\n\n/** sink port operations */\nextern struct rte_port_out_ops rte_port_sink_ops;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_power/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_power.a\n\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3 -fno-strict-aliasing\n\nEXPORT_MAP := rte_power_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_POWER) := rte_power.c rte_power_acpi_cpufreq.c\nSRCS-$(CONFIG_RTE_LIBRTE_POWER) += rte_power_kvm_vm.c guest_channel.c\n\n# install this header file\nSYMLINK-$(CONFIG_RTE_LIBRTE_POWER)-include := rte_power.h\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_POWER) += lib/librte_eal\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_power/channel_commands.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef CHANNEL_COMMANDS_H_\n#define CHANNEL_COMMANDS_H_\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n/* Maximum number of CPUs */\n#define CHANNEL_CMDS_MAX_CPUS 64\n#if CHANNEL_CMDS_MAX_CPUS > 64\n#error Maximum number of cores is 64, overflow is guaranteed to \\\n\tcause problems with VM Power Management\n#endif\n\n/* Maximum number of channels per VM */\n#define CHANNEL_CMDS_MAX_VM_CHANNELS 64\n\n/* Maximum number of channels per VM */\n#define CHANNEL_CMDS_MAX_VM_CHANNELS 64\n\n/* Valid Commands */\n#define CPU_POWER 1\n#define CPU_POWER_CONNECT 2\n\n/* CPU Power Command Scaling */\n#define CPU_POWER_SCALE_UP 1\n#define CPU_POWER_SCALE_DOWN 2\n#define CPU_POWER_SCALE_MAX 3\n#define CPU_POWER_SCALE_MIN 4\n\nstruct channel_packet {\n\tuint64_t resource_id; /**< core_num, device */\n\tuint32_t unit; /**< scale down/up/min/max */\n\tuint32_t command; /**< Power, IO, etc */\n};\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* CHANNEL_COMMANDS_H_ */\n" }, { "path": "lib/librte_power/guest_channel.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n\n#include \n#include \n\n#include \"guest_channel.h\"\n#include \"channel_commands.h\"\n\n#define RTE_LOGTYPE_GUEST_CHANNEL RTE_LOGTYPE_USER1\n\nstatic int global_fds[RTE_MAX_LCORE];\n\nint\nguest_channel_host_connect(const char *path, unsigned lcore_id)\n{\n\tint flags, ret;\n\tstruct channel_packet pkt;\n\tchar fd_path[PATH_MAX];\n\tint fd = -1;\n\n\tif (lcore_id >= RTE_MAX_LCORE) {\n\t\tRTE_LOG(ERR, GUEST_CHANNEL, \"Channel(%u) is out of range 0...%d\\n\",\n\t\t\t\tlcore_id, RTE_MAX_LCORE-1);\n\t\treturn -1;\n\t}\n\t/* check if path is already open */\n\tif (global_fds[lcore_id] != 0) {\n\t\tRTE_LOG(ERR, GUEST_CHANNEL, \"Channel(%u) is already open with fd %d\\n\",\n\t\t\t\tlcore_id, global_fds[lcore_id]);\n\t\treturn -1;\n\t}\n\n\tsnprintf(fd_path, PATH_MAX, \"%s.%u\", path, lcore_id);\n\tRTE_LOG(INFO, GUEST_CHANNEL, \"Opening channel '%s' for lcore %u\\n\",\n\t\t\tfd_path, lcore_id);\n\tfd = open(fd_path, O_RDWR);\n\tif (fd < 0) {\n\t\tRTE_LOG(ERR, GUEST_CHANNEL, \"Unable to to connect to '%s' with error \"\n\t\t\t\t\"%s\\n\", fd_path, strerror(errno));\n\t\treturn -1;\n\t}\n\n\tflags = fcntl(fd, F_GETFL, 0);\n\tif (flags < 0) {\n\t\tRTE_LOG(ERR, GUEST_CHANNEL, \"Failed on fcntl get flags for file %s\\n\",\n\t\t\t\tfd_path);\n\t\tgoto error;\n\t}\n\n\tflags |= O_NONBLOCK;\n\tif (fcntl(fd, F_SETFL, flags) < 0) {\n\t\tRTE_LOG(ERR, GUEST_CHANNEL, \"Failed on setting non-blocking mode for \"\n\t\t\t\t\"file %s\", fd_path);\n\t\tgoto error;\n\t}\n\t/* QEMU needs a delay after connection */\n\tsleep(1);\n\n\t/* Send a test packet, this command is ignored by the host, but a successful\n\t * send indicates that the host endpoint is monitoring.\n\t */\n\tpkt.command = CPU_POWER_CONNECT;\n\tglobal_fds[lcore_id] = fd;\n\tret = guest_channel_send_msg(&pkt, lcore_id);\n\tif (ret != 0) {\n\t\tRTE_LOG(ERR, GUEST_CHANNEL, \"Error on channel '%s' communications \"\n\t\t\t\t\"test: %s\\n\", fd_path, strerror(ret));\n\t\tgoto error;\n\t}\n\tRTE_LOG(INFO, GUEST_CHANNEL, \"Channel '%s' is now connected\\n\", fd_path);\n\treturn 0;\nerror:\n\tclose(fd);\n\tglobal_fds[lcore_id] = 0;\n\treturn -1;\n}\n\nint\nguest_channel_send_msg(struct channel_packet *pkt, unsigned lcore_id)\n{\n\tint ret, buffer_len = sizeof(*pkt);\n\tvoid *buffer = pkt;\n\n\tif (lcore_id >= RTE_MAX_LCORE) {\n\t\tRTE_LOG(ERR, GUEST_CHANNEL, \"Channel(%u) is out of range 0...%d\\n\",\n\t\t\t\tlcore_id, RTE_MAX_LCORE-1);\n\t\treturn -1;\n\t}\n\n\tif (global_fds[lcore_id] == 0) {\n\t\tRTE_LOG(ERR, GUEST_CHANNEL, \"Channel is not connected\\n\");\n\t\treturn -1;\n\t}\n\twhile (buffer_len > 0) {\n\t\tret = write(global_fds[lcore_id], buffer, buffer_len);\n\t\tif (ret == buffer_len)\n\t\t\treturn 0;\n\t\tif (ret == -1) {\n\t\t\tif (errno == EINTR)\n\t\t\t\tcontinue;\n\t\t\treturn errno;\n\t\t}\n\t\tbuffer = (char *)buffer + ret;\n\t\tbuffer_len -= ret;\n\t}\n\treturn 0;\n}\n\nvoid\nguest_channel_host_disconnect(unsigned lcore_id)\n{\n\tif (lcore_id >= RTE_MAX_LCORE) {\n\t\tRTE_LOG(ERR, GUEST_CHANNEL, \"Channel(%u) is out of range 0...%d\\n\",\n\t\t\t\tlcore_id, RTE_MAX_LCORE-1);\n\t\treturn;\n\t}\n\tif (global_fds[lcore_id] == 0)\n\t\treturn;\n\tclose(global_fds[lcore_id]);\n\tglobal_fds[lcore_id] = 0;\n}\n" }, { "path": "lib/librte_power/guest_channel.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef _GUEST_CHANNEL_H\n#define _GUEST_CHANNEL_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n/**\n * Connect to the Virtio-Serial VM end-point located in path. It is\n * thread safe for unique lcore_ids. This function must be only called once from\n * each lcore.\n *\n * @param path\n * The path to the serial device on the filesystem\n * @param lcore_id\n * lcore_id.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint guest_channel_host_connect(const char *path, unsigned lcore_id);\n\n/**\n * Disconnect from an already connected Virtio-Serial Endpoint.\n *\n *\n * @param lcore_id\n * lcore_id.\n *\n */\nvoid guest_channel_host_disconnect(unsigned lcore_id);\n\n/**\n * Send a message contained in pkt over the Virtio-Serial to the host endpoint.\n *\n * @param pkt\n * Pointer to a populated struct guest_agent_pkt\n *\n * @param lcore_id\n * lcore_id.\n *\n * @return\n * - 0 on success.\n * - Negative on channel not connected.\n * - errno on write to channel error.\n */\nint guest_channel_send_msg(struct channel_packet *pkt, unsigned lcore_id);\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_power/rte_power.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \"rte_power.h\"\n#include \"rte_power_acpi_cpufreq.h\"\n#include \"rte_power_kvm_vm.h\"\n#include \"rte_power_common.h\"\n\nenum power_management_env global_default_env = PM_ENV_NOT_SET;\n\nvolatile uint32_t global_env_cfg_status = 0;\n\n/* function pointers */\nrte_power_freqs_t rte_power_freqs = NULL;\nrte_power_get_freq_t rte_power_get_freq = NULL;\nrte_power_set_freq_t rte_power_set_freq = NULL;\nrte_power_freq_change_t rte_power_freq_up = NULL;\nrte_power_freq_change_t rte_power_freq_down = NULL;\nrte_power_freq_change_t rte_power_freq_max = NULL;\nrte_power_freq_change_t rte_power_freq_min = NULL;\n\nint\nrte_power_set_env(enum power_management_env env)\n{\n\tif (rte_atomic32_cmpset(&global_env_cfg_status, 0, 1) == 0) {\n\t\treturn 0;\n\t}\n\tif (env == PM_ENV_ACPI_CPUFREQ) {\n\t\trte_power_freqs = rte_power_acpi_cpufreq_freqs;\n\t\trte_power_get_freq = rte_power_acpi_cpufreq_get_freq;\n\t\trte_power_set_freq = rte_power_acpi_cpufreq_set_freq;\n\t\trte_power_freq_up = rte_power_acpi_cpufreq_freq_up;\n\t\trte_power_freq_down = rte_power_acpi_cpufreq_freq_down;\n\t\trte_power_freq_min = rte_power_acpi_cpufreq_freq_min;\n\t\trte_power_freq_max = rte_power_acpi_cpufreq_freq_max;\n\t} else if (env == PM_ENV_KVM_VM) {\n\t\trte_power_freqs = rte_power_kvm_vm_freqs;\n\t\trte_power_get_freq = rte_power_kvm_vm_get_freq;\n\t\trte_power_set_freq = rte_power_kvm_vm_set_freq;\n\t\trte_power_freq_up = rte_power_kvm_vm_freq_up;\n\t\trte_power_freq_down = rte_power_kvm_vm_freq_down;\n\t\trte_power_freq_min = rte_power_kvm_vm_freq_min;\n\t\trte_power_freq_max = rte_power_kvm_vm_freq_max;\n\t} else {\n\t\tRTE_LOG(ERR, POWER, \"Invalid Power Management Environment(%d) set\\n\",\n\t\t\t\tenv);\n\t\trte_power_unset_env();\n\t\treturn -1;\n\t}\n\tglobal_default_env = env;\n\treturn 0;\n\n}\n\nvoid\nrte_power_unset_env(void)\n{\n\tif (rte_atomic32_cmpset(&global_env_cfg_status, 1, 0) != 0)\n\t\tglobal_default_env = PM_ENV_NOT_SET;\n}\n\nenum power_management_env\nrte_power_get_env(void) {\n\treturn global_default_env;\n}\n\nint\nrte_power_init(unsigned lcore_id)\n{\n\tint ret = -1;\n\n\tif (global_default_env == PM_ENV_ACPI_CPUFREQ) {\n\t\treturn rte_power_acpi_cpufreq_init(lcore_id);\n\t}\n\tif (global_default_env == PM_ENV_KVM_VM) {\n\t\treturn rte_power_kvm_vm_init(lcore_id);\n\t}\n\t/* Auto detect Environment */\n\tRTE_LOG(INFO, POWER, \"Attempting to initialise ACPI cpufreq power \"\n\t\t\t\"management...\\n\");\n\tret = rte_power_acpi_cpufreq_init(lcore_id);\n\tif (ret == 0) {\n\t\trte_power_set_env(PM_ENV_ACPI_CPUFREQ);\n\t\tgoto out;\n\t}\n\n\tRTE_LOG(INFO, POWER, \"Attempting to initialise VM power management...\\n\");\n\tret = rte_power_kvm_vm_init(lcore_id);\n\tif (ret == 0) {\n\t\trte_power_set_env(PM_ENV_KVM_VM);\n\t\tgoto out;\n\t}\n\tRTE_LOG(ERR, POWER, \"Unable to set Power Management Environment for lcore \"\n\t\t\t\"%u\\n\", lcore_id);\nout:\n\treturn ret;\n}\n\nint\nrte_power_exit(unsigned lcore_id)\n{\n\tif (global_default_env == PM_ENV_ACPI_CPUFREQ)\n\t\treturn rte_power_acpi_cpufreq_exit(lcore_id);\n\tif (global_default_env == PM_ENV_KVM_VM)\n\t\treturn rte_power_kvm_vm_exit(lcore_id);\n\n\tRTE_LOG(ERR, POWER, \"Environment has not been set, unable to exit \"\n\t\t\t\t\"gracefully\\n\");\n\treturn -1;\n\n}\n" }, { "path": "lib/librte_power/rte_power.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_POWER_H\n#define _RTE_POWER_H\n\n/**\n * @file\n * RTE Power Management\n */\n\n#include \n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Power Management Environment State */\nenum power_management_env {PM_ENV_NOT_SET, PM_ENV_ACPI_CPUFREQ, PM_ENV_KVM_VM};\n\n/**\n * Set the default power management implementation. If this is not called prior\n * to rte_power_init(), then auto-detect of the environment will take place.\n * It is not thread safe.\n *\n * @param env\n * env. The environment in which to initialise Power Management for.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint rte_power_set_env(enum power_management_env env);\n\n/**\n * Unset the global environment configuration.\n * This can only be called after all threads have completed.\n */\nvoid rte_power_unset_env(void);\n\n/**\n * Get the default power management implementation.\n *\n * @return\n * power_management_env The configured environment.\n */\nenum power_management_env rte_power_get_env(void);\n\n/**\n * Initialize power management for a specific lcore. If rte_power_set_env() has\n * not been called then an auto-detect of the environment will start and\n * initialise the corresponding resources.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint rte_power_init(unsigned lcore_id);\n\n/**\n * Exit power management on a specific lcore. This will call the environment\n * dependent exit function.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint rte_power_exit(unsigned lcore_id);\n\n/**\n * Get the available frequencies of a specific lcore.\n * Function pointer definition. Review each environments\n * specific documentation for usage.\n *\n * @param lcore_id\n * lcore id.\n * @param freqs\n * The buffer array to save the frequencies.\n * @param num\n * The number of frequencies to get.\n *\n * @return\n * The number of available frequencies.\n */\ntypedef uint32_t (*rte_power_freqs_t)(unsigned lcore_id, uint32_t *freqs,\n\t\tuint32_t num);\n\nextern rte_power_freqs_t rte_power_freqs;\n\n/**\n * Return the current index of available frequencies of a specific lcore.\n * Function pointer definition. Review each environments\n * specific documentation for usage.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * The current index of available frequencies.\n */\ntypedef uint32_t (*rte_power_get_freq_t)(unsigned lcore_id);\n\nextern rte_power_get_freq_t rte_power_get_freq;\n\n/**\n * Set the new frequency for a specific lcore by indicating the index of\n * available frequencies.\n * Function pointer definition. Review each environments\n * specific documentation for usage.\n *\n * @param lcore_id\n * lcore id.\n * @param index\n * The index of available frequencies.\n *\n * @return\n * - 1 on success with frequency changed.\n * - 0 on success without frequency changed.\n * - Negative on error.\n */\ntypedef int (*rte_power_set_freq_t)(unsigned lcore_id, uint32_t index);\n\nextern rte_power_set_freq_t rte_power_set_freq;\n\n/**\n * Function pointer definition for generic frequency change functions. Review\n * each environments specific documentation for usage.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success with frequency changed.\n * - 0 on success without frequency changed.\n * - Negative on error.\n */\ntypedef int (*rte_power_freq_change_t)(unsigned lcore_id);\n\n/**\n * Scale up the frequency of a specific lcore according to the available\n * frequencies.\n * Review each environments specific documentation for usage.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success with frequency changed.\n * - 0 on success without frequency changed.\n * - Negative on error.\n */\nextern rte_power_freq_change_t rte_power_freq_up;\n\n/**\n * Scale down the frequency of a specific lcore according to the available\n * frequencies.\n * Review each environments specific documentation for usage.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success with frequency changed.\n * - 0 on success without frequency changed.\n * - Negative on error.\n */\n\nextern rte_power_freq_change_t rte_power_freq_down;\n\n/**\n * Scale up the frequency of a specific lcore to the highest according to the\n * available frequencies.\n * Review each environments specific documentation for usage.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success with frequency changed.\n * - 0 on success without frequency changed.\n * - Negative on error.\n */\nextern rte_power_freq_change_t rte_power_freq_max;\n\n/**\n * Scale down the frequency of a specific lcore to the lowest according to the\n * available frequencies.\n * Review each environments specific documentation for usage..\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success with frequency changed.\n * - 0 on success without frequency changed.\n * - Negative on error.\n */\nextern rte_power_freq_change_t rte_power_freq_min;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_power/rte_power_acpi_cpufreq.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \"rte_power_acpi_cpufreq.h\"\n#include \"rte_power_common.h\"\n\n#ifdef RTE_LIBRTE_POWER_DEBUG\n#define POWER_DEBUG_TRACE(fmt, args...) do { \\\n\t\tRTE_LOG(ERR, POWER, \"%s: \" fmt, __func__, ## args); \\\n} while (0)\n#else\n#define POWER_DEBUG_TRACE(fmt, args...)\n#endif\n\n#define FOPEN_OR_ERR_RET(f, retval) do { \\\n\t\tif ((f) == NULL) { \\\n\t\t\tRTE_LOG(ERR, POWER, \"File not openned\\n\"); \\\n\t\t\treturn retval; \\\n\t\t} \\\n} while (0)\n\n#define FOPS_OR_NULL_GOTO(ret, label) do { \\\n\t\tif ((ret) == NULL) { \\\n\t\t\tRTE_LOG(ERR, POWER, \"fgets returns nothing\\n\"); \\\n\t\t\tgoto label; \\\n\t\t} \\\n} while (0)\n\n#define FOPS_OR_ERR_GOTO(ret, label) do { \\\n\t\tif ((ret) < 0) { \\\n\t\t\tRTE_LOG(ERR, POWER, \"File operations failed\\n\"); \\\n\t\t\tgoto label; \\\n\t\t} \\\n} while (0)\n\n#define STR_SIZE 1024\n#define POWER_CONVERT_TO_DECIMAL 10\n\n#define POWER_GOVERNOR_USERSPACE \"userspace\"\n#define POWER_SYSFILE_GOVERNOR \\\n\t\t\"/sys/devices/system/cpu/cpu%u/cpufreq/scaling_governor\"\n#define POWER_SYSFILE_AVAIL_FREQ \\\n\t\t\"/sys/devices/system/cpu/cpu%u/cpufreq/scaling_available_frequencies\"\n#define POWER_SYSFILE_SETSPEED \\\n\t\t\"/sys/devices/system/cpu/cpu%u/cpufreq/scaling_setspeed\"\n\nenum power_state {\n\tPOWER_IDLE = 0,\n\tPOWER_ONGOING,\n\tPOWER_USED,\n\tPOWER_UNKNOWN\n};\n\n/**\n * Power info per lcore.\n */\nstruct rte_power_info {\n\tunsigned lcore_id; /**< Logical core id */\n\tuint32_t freqs[RTE_MAX_LCORE_FREQS]; /**< Frequency array */\n\tuint32_t nb_freqs; /**< number of available freqs */\n\tFILE *f; /**< FD of scaling_setspeed */\n\tchar governor_ori[32]; /**< Original governor name */\n\tuint32_t curr_idx; /**< Freq index in freqs array */\n\tvolatile uint32_t state; /**< Power in use state */\n} __rte_cache_aligned;\n\nstatic struct rte_power_info lcore_power_info[RTE_MAX_LCORE];\n\n/**\n * It is to set specific freq for specific logical core, according to the index\n * of supported frequencies.\n */\nstatic int\nset_freq_internal(struct rte_power_info *pi, uint32_t idx)\n{\n\tif (idx >= RTE_MAX_LCORE_FREQS || idx >= pi->nb_freqs) {\n\t\tRTE_LOG(ERR, POWER, \"Invalid frequency index %u, which \"\n\t\t\t\t\"should be less than %u\\n\", idx, pi->nb_freqs);\n\t\treturn -1;\n\t}\n\n\t/* Check if it is the same as current */\n\tif (idx == pi->curr_idx)\n\t\treturn 0;\n\n\tPOWER_DEBUG_TRACE(\"Freqency[%u] %u to be set for lcore %u\\n\",\n\t\t\tidx, pi->freqs[idx], pi->lcore_id);\n\tif (fseek(pi->f, 0, SEEK_SET) < 0) {\n\t\tRTE_LOG(ERR, POWER, \"Fail to set file position indicator to 0 \"\n\t\t\t\t\"for setting frequency for lcore %u\\n\", pi->lcore_id);\n\t\treturn -1;\n\t}\n\tif (fprintf(pi->f, \"%u\", pi->freqs[idx]) < 0) {\n\t\tRTE_LOG(ERR, POWER, \"Fail to write new frequency for \"\n\t\t\t\t\"lcore %u\\n\", pi->lcore_id);\n\t\treturn -1;\n\t}\n\tfflush(pi->f);\n\tpi->curr_idx = idx;\n\n\treturn 1;\n}\n\n/**\n * It is to check the current scaling governor by reading sys file, and then\n * set it into 'userspace' if it is not by writing the sys file. The original\n * governor will be saved for rolling back.\n */\nstatic int\npower_set_governor_userspace(struct rte_power_info *pi)\n{\n\tFILE *f;\n\tint ret = -1;\n\tchar buf[BUFSIZ];\n\tchar fullpath[PATH_MAX];\n\tchar *s;\n\tint val;\n\n\tsnprintf(fullpath, sizeof(fullpath), POWER_SYSFILE_GOVERNOR,\n\t\t\tpi->lcore_id);\n\tf = fopen(fullpath, \"rw+\");\n\tFOPEN_OR_ERR_RET(f, ret);\n\n\ts = fgets(buf, sizeof(buf), f);\n\tFOPS_OR_NULL_GOTO(s, out);\n\n\t/* Check if current governor is userspace */\n\tif (strncmp(buf, POWER_GOVERNOR_USERSPACE,\n\t\t\tsizeof(POWER_GOVERNOR_USERSPACE)) == 0) {\n\t\tret = 0;\n\t\tPOWER_DEBUG_TRACE(\"Power management governor of lcore %u is \"\n\t\t\t\t\"already userspace\\n\", pi->lcore_id);\n\t\tgoto out;\n\t}\n\t/* Save the original governor */\n\tsnprintf(pi->governor_ori, sizeof(pi->governor_ori), \"%s\", buf);\n\n\t/* Write 'userspace' to the governor */\n\tval = fseek(f, 0, SEEK_SET);\n\tFOPS_OR_ERR_GOTO(val, out);\n\n\tval = fputs(POWER_GOVERNOR_USERSPACE, f);\n\tFOPS_OR_ERR_GOTO(val, out);\n\n\tret = 0;\n\tRTE_LOG(INFO, POWER, \"Power management governor of lcore %u has been \"\n\t\t\t\"set to user space successfully\\n\", pi->lcore_id);\nout:\n\tfclose(f);\n\n\treturn ret;\n}\n\n/**\n * It is to get the available frequencies of the specific lcore by reading the\n * sys file.\n */\nstatic int\npower_get_available_freqs(struct rte_power_info *pi)\n{\n\tFILE *f;\n\tint ret = -1, i, count;\n\tchar *p;\n\tchar buf[BUFSIZ];\n\tchar fullpath[PATH_MAX];\n\tchar *freqs[RTE_MAX_LCORE_FREQS];\n\tchar *s;\n\n\tsnprintf(fullpath, sizeof(fullpath), POWER_SYSFILE_AVAIL_FREQ,\n\t\t\tpi->lcore_id);\n\tf = fopen(fullpath, \"r\");\n\tFOPEN_OR_ERR_RET(f, ret);\n\n\ts = fgets(buf, sizeof(buf), f);\n\tFOPS_OR_NULL_GOTO(s, out);\n\n\t/* Strip the line break if there is */\n\tp = strchr(buf, '\\n');\n\tif (p != NULL)\n\t\t*p = 0;\n\n\t/* Split string into at most RTE_MAX_LCORE_FREQS frequencies */\n\tcount = rte_strsplit(buf, sizeof(buf), freqs,\n\t\t\tRTE_MAX_LCORE_FREQS, ' ');\n\tif (count <= 0) {\n\t\tRTE_LOG(ERR, POWER, \"No available frequency in \"\n\t\t\t\t\"\"POWER_SYSFILE_AVAIL_FREQ\"\\n\", pi->lcore_id);\n\t\tgoto out;\n\t}\n\tif (count >= RTE_MAX_LCORE_FREQS) {\n\t\tRTE_LOG(ERR, POWER, \"Too many available frequencies : %d\\n\",\n\t\t\t\tcount);\n\t\tgoto out;\n\t}\n\n\t/* Store the available frequncies into power context */\n\tfor (i = 0, pi->nb_freqs = 0; i < count; i++) {\n\t\tPOWER_DEBUG_TRACE(\"Lcore %u frequency[%d]: %s\\n\", pi->lcore_id,\n\t\t\t\ti, freqs[i]);\n\t\tpi->freqs[pi->nb_freqs++] = strtoul(freqs[i], &p,\n\t\t\t\tPOWER_CONVERT_TO_DECIMAL);\n\t}\n\n\tret = 0;\n\tPOWER_DEBUG_TRACE(\"%d frequencie(s) of lcore %u are available\\n\",\n\t\t\tcount, pi->lcore_id);\nout:\n\tfclose(f);\n\n\treturn ret;\n}\n\n/**\n * It is to fopen the sys file for the future setting the lcore frequency.\n */\nstatic int\npower_init_for_setting_freq(struct rte_power_info *pi)\n{\n\tFILE *f;\n\tchar fullpath[PATH_MAX];\n\tchar buf[BUFSIZ];\n\tuint32_t i, freq;\n\tchar *s;\n\n\tsnprintf(fullpath, sizeof(fullpath), POWER_SYSFILE_SETSPEED,\n\t\t\tpi->lcore_id);\n\tf = fopen(fullpath, \"rw+\");\n\tFOPEN_OR_ERR_RET(f, -1);\n\n\ts = fgets(buf, sizeof(buf), f);\n\tFOPS_OR_NULL_GOTO(s, out);\n\n\tfreq = strtoul(buf, NULL, POWER_CONVERT_TO_DECIMAL);\n\tfor (i = 0; i < pi->nb_freqs; i++) {\n\t\tif (freq == pi->freqs[i]) {\n\t\t\tpi->curr_idx = i;\n\t\t\tpi->f = f;\n\t\t\treturn 0;\n\t\t}\n\t}\n\nout:\n\tfclose(f);\n\n\treturn -1;\n}\n\nint\nrte_power_acpi_cpufreq_init(unsigned lcore_id)\n{\n\tstruct rte_power_info *pi;\n\n\tif (lcore_id >= RTE_MAX_LCORE) {\n\t\tRTE_LOG(ERR, POWER, \"Lcore id %u can not exceeds %u\\n\",\n\t\t\t\tlcore_id, RTE_MAX_LCORE - 1U);\n\t\treturn -1;\n\t}\n\n\tpi = &lcore_power_info[lcore_id];\n\tif (rte_atomic32_cmpset(&(pi->state), POWER_IDLE, POWER_ONGOING)\n\t\t\t== 0) {\n\t\tRTE_LOG(INFO, POWER, \"Power management of lcore %u is \"\n\t\t\t\t\"in use\\n\", lcore_id);\n\t\treturn -1;\n\t}\n\n\tpi->lcore_id = lcore_id;\n\t/* Check and set the governor */\n\tif (power_set_governor_userspace(pi) < 0) {\n\t\tRTE_LOG(ERR, POWER, \"Cannot set governor of lcore %u to \"\n\t\t\t\t\"userspace\\n\", lcore_id);\n\t\tgoto fail;\n\t}\n\n\t/* Get the available frequencies */\n\tif (power_get_available_freqs(pi) < 0) {\n\t\tRTE_LOG(ERR, POWER, \"Cannot get available frequencies of \"\n\t\t\t\t\"lcore %u\\n\", lcore_id);\n\t\tgoto fail;\n\t}\n\n\t/* Init for setting lcore frequency */\n\tif (power_init_for_setting_freq(pi) < 0) {\n\t\tRTE_LOG(ERR, POWER, \"Cannot init for setting frequency for \"\n\t\t\t\t\"lcore %u\\n\", lcore_id);\n\t\tgoto fail;\n\t}\n\n\t/* Set freq to max by default */\n\tif (rte_power_acpi_cpufreq_freq_max(lcore_id) < 0) {\n\t\tRTE_LOG(ERR, POWER, \"Cannot set frequency of lcore %u \"\n\t\t\t\t\"to max\\n\", lcore_id);\n\t\tgoto fail;\n\t}\n\n\tRTE_LOG(INFO, POWER, \"Initialized successfully for lcore %u \"\n\t\t\t\"power manamgement\\n\", lcore_id);\n\trte_atomic32_cmpset(&(pi->state), POWER_ONGOING, POWER_USED);\n\n\treturn 0;\n\nfail:\n\trte_atomic32_cmpset(&(pi->state), POWER_ONGOING, POWER_UNKNOWN);\n\n\treturn -1;\n}\n\n/**\n * It is to check the governor and then set the original governor back if\n * needed by writing the the sys file.\n */\nstatic int\npower_set_governor_original(struct rte_power_info *pi)\n{\n\tFILE *f;\n\tint ret = -1;\n\tchar buf[BUFSIZ];\n\tchar fullpath[PATH_MAX];\n\tchar *s;\n\tint val;\n\n\tsnprintf(fullpath, sizeof(fullpath), POWER_SYSFILE_GOVERNOR,\n\t\t\tpi->lcore_id);\n\tf = fopen(fullpath, \"rw+\");\n\tFOPEN_OR_ERR_RET(f, ret);\n\n\ts = fgets(buf, sizeof(buf), f);\n\tFOPS_OR_NULL_GOTO(s, out);\n\n\t/* Check if the governor to be set is the same as current */\n\tif (strncmp(buf, pi->governor_ori, sizeof(pi->governor_ori)) == 0) {\n\t\tret = 0;\n\t\tPOWER_DEBUG_TRACE(\"Power management governor of lcore %u \"\n\t\t\t\t\"has already been set to %s\\n\",\n\t\t\t\tpi->lcore_id, pi->governor_ori);\n\t\tgoto out;\n\t}\n\n\t/* Write back the original governor */\n\tval = fseek(f, 0, SEEK_SET);\n\tFOPS_OR_ERR_GOTO(val, out);\n\n\tval = fputs(pi->governor_ori, f);\n\tFOPS_OR_ERR_GOTO(val, out);\n\n\tret = 0;\n\tRTE_LOG(INFO, POWER, \"Power management governor of lcore %u \"\n\t\t\t\"has been set back to %s successfully\\n\",\n\t\t\tpi->lcore_id, pi->governor_ori);\nout:\n\tfclose(f);\n\n\treturn ret;\n}\n\nint\nrte_power_acpi_cpufreq_exit(unsigned lcore_id)\n{\n\tstruct rte_power_info *pi;\n\n\tif (lcore_id >= RTE_MAX_LCORE) {\n\t\tRTE_LOG(ERR, POWER, \"Lcore id %u can not exceeds %u\\n\",\n\t\t\t\tlcore_id, RTE_MAX_LCORE - 1U);\n\t\treturn -1;\n\t}\n\tpi = &lcore_power_info[lcore_id];\n\tif (rte_atomic32_cmpset(&(pi->state), POWER_USED, POWER_ONGOING)\n\t\t\t== 0) {\n\t\tRTE_LOG(INFO, POWER, \"Power management of lcore %u is \"\n\t\t\t\t\"not used\\n\", lcore_id);\n\t\treturn -1;\n\t}\n\n\t/* Close FD of setting freq */\n\tfclose(pi->f);\n\tpi->f = NULL;\n\n\t/* Set the governor back to the original */\n\tif (power_set_governor_original(pi) < 0) {\n\t\tRTE_LOG(ERR, POWER, \"Cannot set the governor of %u back \"\n\t\t\t\t\"to the original\\n\", lcore_id);\n\t\tgoto fail;\n\t}\n\n\tRTE_LOG(INFO, POWER, \"Power management of lcore %u has exited from \"\n\t\t\t\"'userspace' mode and been set back to the \"\n\t\t\t\"original\\n\", lcore_id);\n\trte_atomic32_cmpset(&(pi->state), POWER_ONGOING, POWER_IDLE);\n\n\treturn 0;\n\nfail:\n\trte_atomic32_cmpset(&(pi->state), POWER_ONGOING, POWER_UNKNOWN);\n\n\treturn -1;\n}\n\nuint32_t\nrte_power_acpi_cpufreq_freqs(unsigned lcore_id, uint32_t *freqs, uint32_t num)\n{\n\tstruct rte_power_info *pi;\n\n\tif (lcore_id >= RTE_MAX_LCORE || !freqs) {\n\t\tRTE_LOG(ERR, POWER, \"Invalid input parameter\\n\");\n\t\treturn 0;\n\t}\n\n\tpi = &lcore_power_info[lcore_id];\n\tif (num < pi->nb_freqs) {\n\t\tRTE_LOG(ERR, POWER, \"Buffer size is not enough\\n\");\n\t\treturn 0;\n\t}\n\trte_memcpy(freqs, pi->freqs, pi->nb_freqs * sizeof(uint32_t));\n\n\treturn pi->nb_freqs;\n}\n\nuint32_t\nrte_power_acpi_cpufreq_get_freq(unsigned lcore_id)\n{\n\tif (lcore_id >= RTE_MAX_LCORE) {\n\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n\t\treturn RTE_POWER_INVALID_FREQ_INDEX;\n\t}\n\n\treturn lcore_power_info[lcore_id].curr_idx;\n}\n\nint\nrte_power_acpi_cpufreq_set_freq(unsigned lcore_id, uint32_t index)\n{\n\tif (lcore_id >= RTE_MAX_LCORE) {\n\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n\t\treturn -1;\n\t}\n\n\treturn set_freq_internal(&(lcore_power_info[lcore_id]), index);\n}\n\nint\nrte_power_acpi_cpufreq_freq_down(unsigned lcore_id)\n{\n\tstruct rte_power_info *pi;\n\n\tif (lcore_id >= RTE_MAX_LCORE) {\n\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n\t\treturn -1;\n\t}\n\n\tpi = &lcore_power_info[lcore_id];\n\tif (pi->curr_idx + 1 == pi->nb_freqs)\n\t\treturn 0;\n\n\t/* Frequencies in the array are from high to low. */\n\treturn set_freq_internal(pi, pi->curr_idx + 1);\n}\n\nint\nrte_power_acpi_cpufreq_freq_up(unsigned lcore_id)\n{\n\tstruct rte_power_info *pi;\n\n\tif (lcore_id >= RTE_MAX_LCORE) {\n\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n\t\treturn -1;\n\t}\n\n\tpi = &lcore_power_info[lcore_id];\n\tif (pi->curr_idx == 0)\n\t\treturn 0;\n\n\t/* Frequencies in the array are from high to low. */\n\treturn set_freq_internal(pi, pi->curr_idx - 1);\n}\n\nint\nrte_power_acpi_cpufreq_freq_max(unsigned lcore_id)\n{\n\tif (lcore_id >= RTE_MAX_LCORE) {\n\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n\t\treturn -1;\n\t}\n\n\t/* Frequencies in the array are from high to low. */\n\treturn set_freq_internal(&lcore_power_info[lcore_id], 0);\n}\n\nint\nrte_power_acpi_cpufreq_freq_min(unsigned lcore_id)\n{\n\tstruct rte_power_info *pi;\n\n\tif (lcore_id >= RTE_MAX_LCORE) {\n\t\tRTE_LOG(ERR, POWER, \"Invalid lcore ID\\n\");\n\t\treturn -1;\n\t}\n\n\tpi = &lcore_power_info[lcore_id];\n\n\t/* Frequencies in the array are from high to low. */\n\treturn set_freq_internal(pi, pi->nb_freqs - 1);\n}\n" }, { "path": "lib/librte_power/rte_power_acpi_cpufreq.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_POWER_ACPI_CPUFREQ_H\n#define _RTE_POWER_ACPI_CPUFREQ_H\n\n/**\n * @file\n * RTE Power Management via userspace ACPI cpufreq\n */\n\n#include \n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Initialize power management for a specific lcore. It will check and set the\n * governor to userspace for the lcore, get the available frequencies, and\n * prepare to set new lcore frequency.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint rte_power_acpi_cpufreq_init(unsigned lcore_id);\n\n/**\n * Exit power management on a specific lcore. It will set the governor to which\n * is before initialized.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint rte_power_acpi_cpufreq_exit(unsigned lcore_id);\n\n/**\n * Get the available frequencies of a specific lcore. The return value will be\n * the minimal one of the total number of available frequencies and the number\n * of buffer. The index of available frequencies used in other interfaces\n * should be in the range of 0 to this return value.\n * It should be protected outside of this function for threadsafe.\n *\n * @param lcore_id\n * lcore id.\n * @param freqs\n * The buffer array to save the frequencies.\n * @param num\n * The number of frequencies to get.\n *\n * @return\n * The number of available frequencies.\n */\nuint32_t rte_power_acpi_cpufreq_freqs(unsigned lcore_id, uint32_t *freqs,\n\t\tuint32_t num);\n\n/**\n * Return the current index of available frequencies of a specific lcore. It\n * will return 'RTE_POWER_INVALID_FREQ_INDEX = (~0)' if error.\n * It should be protected outside of this function for threadsafe.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * The current index of available frequencies.\n */\nuint32_t rte_power_acpi_cpufreq_get_freq(unsigned lcore_id);\n\n/**\n * Set the new frequency for a specific lcore by indicating the index of\n * available frequencies.\n * It should be protected outside of this function for threadsafe.\n *\n * @param lcore_id\n * lcore id.\n * @param index\n * The index of available frequencies.\n *\n * @return\n * - 1 on success with frequency changed.\n * - 0 on success without frequency changed.\n * - Negative on error.\n */\nint rte_power_acpi_cpufreq_set_freq(unsigned lcore_id, uint32_t index);\n\n/**\n * Scale up the frequency of a specific lcore according to the available\n * frequencies.\n * It should be protected outside of this function for threadsafe.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success with frequency changed.\n * - 0 on success without frequency changed.\n * - Negative on error.\n */\nint rte_power_acpi_cpufreq_freq_up(unsigned lcore_id);\n\n/**\n * Scale down the frequency of a specific lcore according to the available\n * frequencies.\n * It should be protected outside of this function for threadsafe.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success with frequency changed.\n * - 0 on success without frequency changed.\n * - Negative on error.\n */\nint rte_power_acpi_cpufreq_freq_down(unsigned lcore_id);\n\n/**\n * Scale up the frequency of a specific lcore to the highest according to the\n * available frequencies.\n * It should be protected outside of this function for threadsafe.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success with frequency changed.\n * - 0 on success without frequency changed.\n * - Negative on error.\n */\nint rte_power_acpi_cpufreq_freq_max(unsigned lcore_id);\n\n/**\n * Scale down the frequency of a specific lcore to the lowest according to the\n * available frequencies.\n * It should be protected outside of this function for threadsafe.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success with frequency changed.\n * - 0 on success without frequency chnaged.\n * - Negative on error.\n */\nint rte_power_acpi_cpufreq_freq_min(unsigned lcore_id);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_power/rte_power_common.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef RTE_POWER_COMMON_H_\n#define RTE_POWER_COMMON_H_\n\n#define RTE_POWER_INVALID_FREQ_INDEX (~0)\n\n#endif /* RTE_POWER_COMMON_H_ */\n" }, { "path": "lib/librte_power/rte_power_kvm_vm.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n\n#include \n#include \n\n#include \"guest_channel.h\"\n#include \"channel_commands.h\"\n#include \"rte_power_kvm_vm.h\"\n#include \"rte_power_common.h\"\n\n#define FD_PATH \"/dev/virtio-ports/virtio.serial.port.poweragent\"\n\nstatic struct channel_packet pkt[CHANNEL_CMDS_MAX_VM_CHANNELS];\n\n\nint\nrte_power_kvm_vm_init(unsigned lcore_id)\n{\n\tif (lcore_id >= CHANNEL_CMDS_MAX_VM_CHANNELS) {\n\t\tRTE_LOG(ERR, POWER, \"Core(%u) is out of range 0...%d\\n\",\n\t\t\t\tlcore_id, CHANNEL_CMDS_MAX_VM_CHANNELS-1);\n\t\treturn -1;\n\t}\n\tpkt[lcore_id].command = CPU_POWER;\n\tpkt[lcore_id].resource_id = lcore_id;\n\treturn guest_channel_host_connect(FD_PATH, lcore_id);\n}\n\nint\nrte_power_kvm_vm_exit(unsigned lcore_id)\n{\n\tguest_channel_host_disconnect(lcore_id);\n\treturn 0;\n}\n\nuint32_t\nrte_power_kvm_vm_freqs(__attribute__((unused)) unsigned lcore_id,\n\t\t__attribute__((unused)) uint32_t *freqs,\n\t\t__attribute__((unused)) uint32_t num)\n{\n\tRTE_LOG(ERR, POWER, \"rte_power_freqs is not implemented \"\n\t\t\t\"for Virtual Machine Power Management\\n\");\n\treturn -ENOTSUP;\n}\n\nuint32_t\nrte_power_kvm_vm_get_freq(__attribute__((unused)) unsigned lcore_id)\n{\n\tRTE_LOG(ERR, POWER, \"rte_power_get_freq is not implemented \"\n\t\t\t\"for Virtual Machine Power Management\\n\");\n\treturn -ENOTSUP;\n}\n\nint\nrte_power_kvm_vm_set_freq(__attribute__((unused)) unsigned lcore_id,\n\t\t__attribute__((unused)) uint32_t index)\n{\n\tRTE_LOG(ERR, POWER, \"rte_power_set_freq is not implemented \"\n\t\t\t\"for Virtual Machine Power Management\\n\");\n\treturn -ENOTSUP;\n}\n\nstatic inline int\nsend_msg(unsigned lcore_id, uint32_t scale_direction)\n{\n\tint ret;\n\n\tif (lcore_id >= CHANNEL_CMDS_MAX_VM_CHANNELS) {\n\t\tRTE_LOG(ERR, POWER, \"Core(%u) is out of range 0...%d\\n\",\n\t\t\t\tlcore_id, CHANNEL_CMDS_MAX_VM_CHANNELS-1);\n\t\treturn -1;\n\t}\n\tpkt[lcore_id].unit = scale_direction;\n\tret = guest_channel_send_msg(&pkt[lcore_id], lcore_id);\n\tif (ret == 0)\n\t\treturn 1;\n\tRTE_LOG(DEBUG, POWER, \"Error sending message: %s\\n\", strerror(ret));\n\treturn -1;\n}\n\nint\nrte_power_kvm_vm_freq_up(unsigned lcore_id)\n{\n\treturn send_msg(lcore_id, CPU_POWER_SCALE_UP);\n}\n\nint\nrte_power_kvm_vm_freq_down(unsigned lcore_id)\n{\n\treturn send_msg(lcore_id, CPU_POWER_SCALE_DOWN);\n}\n\nint\nrte_power_kvm_vm_freq_max(unsigned lcore_id)\n{\n\treturn send_msg(lcore_id, CPU_POWER_SCALE_MAX);\n}\n\nint\nrte_power_kvm_vm_freq_min(unsigned lcore_id)\n{\n\treturn send_msg(lcore_id, CPU_POWER_SCALE_MIN);\n}\n" }, { "path": "lib/librte_power/rte_power_kvm_vm.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_POWER_KVM_VM_H\n#define _RTE_POWER_KVM_VM_H\n\n/**\n * @file\n * RTE Power Management KVM VM\n */\n\n#include \n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * Initialize power management for a specific lcore.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint rte_power_kvm_vm_init(unsigned lcore_id);\n\n/**\n * Exit power management on a specific lcore.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 0 on success.\n * - Negative on error.\n */\nint rte_power_kvm_vm_exit(unsigned lcore_id);\n\n/**\n * Get the available frequencies of a specific lcore.\n * It is not currently supported for VM Power Management.\n *\n * @param lcore_id\n * lcore id.\n * @param freqs\n * The buffer array to save the frequencies.\n * @param num\n * The number of frequencies to get.\n *\n * @return\n * -ENOTSUP\n */\nuint32_t rte_power_kvm_vm_freqs(unsigned lcore_id, uint32_t *freqs,\n\t\tuint32_t num);\n\n/**\n * Return the current index of available frequencies of a specific lcore.\n * It is not currently supported for VM Power Management.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * -ENOTSUP\n */\nuint32_t rte_power_kvm_vm_get_freq(unsigned lcore_id);\n\n/**\n * Set the new frequency for a specific lcore by indicating the index of\n * available frequencies.\n * It is not currently supported for VM Power Management.\n *\n * @param lcore_id\n * lcore id.\n * @param index\n * The index of available frequencies.\n *\n * @return\n * -ENOTSUP\n */\nint rte_power_kvm_vm_set_freq(unsigned lcore_id, uint32_t index);\n\n/**\n * Scale up the frequency of a specific lcore. This request is forwarded to the\n * host monitor.\n * It should be protected outside of this function for threadsafe.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success.\n * - Negative on error.\n */\nint rte_power_kvm_vm_freq_up(unsigned lcore_id);\n\n/**\n * Scale down the frequency of a specific lcore according to the available\n * frequencies.\n * It should be protected outside of this function for threadsafe.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success.\n * - Negative on error.\n */\nint rte_power_kvm_vm_freq_down(unsigned lcore_id);\n\n/**\n * Scale up the frequency of a specific lcore to the highest according to the\n * available frequencies.\n * It should be protected outside of this function for threadsafe.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success.\n * - Negative on error.\n */\nint rte_power_kvm_vm_freq_max(unsigned lcore_id);\n\n/**\n * Scale down the frequency of a specific lcore to the lowest according to the\n * available frequencies.\n * It should be protected outside of this function for threadsafe.\n *\n * @param lcore_id\n * lcore id.\n *\n * @return\n * - 1 on success.\n * - Negative on error.\n */\nint rte_power_kvm_vm_freq_min(unsigned lcore_id);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_reorder/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_reorder.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR)\n\nEXPORT_MAP := rte_reorder_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_REORDER) := rte_reorder.c\n\n# install this header file\nSYMLINK-$(CONFIG_RTE_LIBRTE_REORDER)-include := rte_reorder.h\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_REORDER) += lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_REORDER) += lib/librte_eal\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_reorder/rte_reorder.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_reorder.h\"\n\nTAILQ_HEAD(rte_reorder_list, rte_tailq_entry);\n\nstatic struct rte_tailq_elem rte_reorder_tailq = {\n\t.name = \"RTE_REORDER\",\n};\nEAL_REGISTER_TAILQ(rte_reorder_tailq)\n\n#define NO_FLAGS 0\n#define RTE_REORDER_PREFIX \"RO_\"\n#define RTE_REORDER_NAMESIZE 32\n\n/* Macros for printing using RTE_LOG */\n#define RTE_LOGTYPE_REORDER\tRTE_LOGTYPE_USER1\n\n/* A generic circular buffer */\nstruct cir_buffer {\n\tunsigned int size; /**< Number of entries that can be stored */\n\tunsigned int mask; /**< [buffer_size - 1]: used for wrap-around */\n\tunsigned int head; /**< insertion point in buffer */\n\tunsigned int tail; /**< extraction point in buffer */\n\tstruct rte_mbuf **entries;\n} __rte_cache_aligned;\n\n/* The reorder buffer data structure itself */\nstruct rte_reorder_buffer {\n\tchar name[RTE_REORDER_NAMESIZE];\n\tuint32_t min_seqn; /**< Lowest seq. number that can be in the buffer */\n\tunsigned int memsize; /**< memory area size of reorder buffer */\n\tstruct cir_buffer ready_buf; /**< temp buffer for dequeued entries */\n\tstruct cir_buffer order_buf; /**< buffer used to reorder entries */\n\tint is_initialized;\n} __rte_cache_aligned;\n\nstatic void\nrte_reorder_free_mbufs(struct rte_reorder_buffer *b);\n\nstruct rte_reorder_buffer *\nrte_reorder_init(struct rte_reorder_buffer *b, unsigned int bufsize,\n\t\tconst char *name, unsigned int size)\n{\n\tconst unsigned int min_bufsize = sizeof(*b) +\n\t\t\t\t\t(2 * size * sizeof(struct rte_mbuf *));\n\n\tif (b == NULL) {\n\t\tRTE_LOG(ERR, REORDER, \"Invalid reorder buffer parameter:\"\n\t\t\t\t\t\" NULL\\n\");\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\tif (!rte_is_power_of_2(size)) {\n\t\tRTE_LOG(ERR, REORDER, \"Invalid reorder buffer size\"\n\t\t\t\t\" - Not a power of 2\\n\");\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\tif (name == NULL) {\n\t\tRTE_LOG(ERR, REORDER, \"Invalid reorder buffer name ptr:\"\n\t\t\t\t\t\" NULL\\n\");\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\tif (bufsize < min_bufsize) {\n\t\tRTE_LOG(ERR, REORDER, \"Invalid reorder buffer memory size: %u, \"\n\t\t\t\"minimum required: %u\\n\", bufsize, min_bufsize);\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\tmemset(b, 0, bufsize);\n\tsnprintf(b->name, sizeof(b->name), \"%s\", name);\n\tb->memsize = bufsize;\n\tb->order_buf.size = b->ready_buf.size = size;\n\tb->order_buf.mask = b->ready_buf.mask = size - 1;\n\tb->ready_buf.entries = (void *)&b[1];\n\tb->order_buf.entries = RTE_PTR_ADD(&b[1],\n\t\t\tsize * sizeof(b->ready_buf.entries[0]));\n\n\treturn b;\n}\n\nstruct rte_reorder_buffer*\nrte_reorder_create(const char *name, unsigned socket_id, unsigned int size)\n{\n\tstruct rte_reorder_buffer *b = NULL;\n\tstruct rte_tailq_entry *te;\n\tstruct rte_reorder_list *reorder_list;\n\tconst unsigned int bufsize = sizeof(struct rte_reorder_buffer) +\n\t\t\t\t\t(2 * size * sizeof(struct rte_mbuf *));\n\n\treorder_list = RTE_TAILQ_CAST(rte_reorder_tailq.head, rte_reorder_list);\n\n\t/* Check user arguments. */\n\tif (!rte_is_power_of_2(size)) {\n\t\tRTE_LOG(ERR, REORDER, \"Invalid reorder buffer size\"\n\t\t\t\t\" - Not a power of 2\\n\");\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\tif (name == NULL) {\n\t\tRTE_LOG(ERR, REORDER, \"Invalid reorder buffer name ptr:\"\n\t\t\t\t\t\" NULL\\n\");\n\t\trte_errno = EINVAL;\n\t\treturn NULL;\n\t}\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* guarantee there's no existing */\n\tTAILQ_FOREACH(te, reorder_list, next) {\n\t\tb = (struct rte_reorder_buffer *) te->data;\n\t\tif (strncmp(name, b->name, RTE_REORDER_NAMESIZE) == 0)\n\t\t\tbreak;\n\t}\n\tif (te != NULL)\n\t\tgoto exit;\n\n\t/* allocate tailq entry */\n\tte = rte_zmalloc(\"REORDER_TAILQ_ENTRY\", sizeof(*te), 0);\n\tif (te == NULL) {\n\t\tRTE_LOG(ERR, REORDER, \"Failed to allocate tailq entry\\n\");\n\t\trte_errno = ENOMEM;\n\t\tb = NULL;\n\t\tgoto exit;\n\t}\n\n\t/* Allocate memory to store the reorder buffer structure. */\n\tb = rte_zmalloc_socket(\"REORDER_BUFFER\", bufsize, 0, socket_id);\n\tif (b == NULL) {\n\t\tRTE_LOG(ERR, REORDER, \"Memzone allocation failed\\n\");\n\t\trte_errno = ENOMEM;\n\t\trte_free(te);\n\t} else {\n\t\trte_reorder_init(b, bufsize, name, size);\n\t\tte->data = (void *)b;\n\t\tTAILQ_INSERT_TAIL(reorder_list, te, next);\n\t}\n\nexit:\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\treturn b;\n}\n\nvoid\nrte_reorder_reset(struct rte_reorder_buffer *b)\n{\n\tchar name[RTE_REORDER_NAMESIZE];\n\n\trte_reorder_free_mbufs(b);\n\tsnprintf(name, sizeof(name), \"%s\", b->name);\n\t/* No error checking as current values should be valid */\n\trte_reorder_init(b, b->memsize, name, b->order_buf.size);\n}\n\nstatic void\nrte_reorder_free_mbufs(struct rte_reorder_buffer *b)\n{\n\tunsigned i;\n\n\t/* Free up the mbufs of order buffer & ready buffer */\n\tfor (i = 0; i < b->order_buf.size; i++) {\n\t\tif (b->order_buf.entries[i])\n\t\t\trte_pktmbuf_free(b->order_buf.entries[i]);\n\t\tif (b->ready_buf.entries[i])\n\t\t\trte_pktmbuf_free(b->ready_buf.entries[i]);\n\t}\n}\n\nvoid\nrte_reorder_free(struct rte_reorder_buffer *b)\n{\n\tstruct rte_reorder_list *reorder_list;\n\tstruct rte_tailq_entry *te;\n\n\t/* Check user arguments. */\n\tif (b == NULL)\n\t\treturn;\n\n\treorder_list = RTE_TAILQ_CAST(rte_reorder_tailq.head, rte_reorder_list);\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* find our tailq entry */\n\tTAILQ_FOREACH(te, reorder_list, next) {\n\t\tif (te->data == (void *) b)\n\t\t\tbreak;\n\t}\n\tif (te == NULL) {\n\t\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\t\treturn;\n\t}\n\n\tTAILQ_REMOVE(reorder_list, te, next);\n\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\trte_reorder_free_mbufs(b);\n\n\trte_free(b);\n\trte_free(te);\n}\n\nstruct rte_reorder_buffer *\nrte_reorder_find_existing(const char *name)\n{\n\tstruct rte_reorder_buffer *b = NULL;\n\tstruct rte_tailq_entry *te;\n\tstruct rte_reorder_list *reorder_list;\n\n\treorder_list = RTE_TAILQ_CAST(rte_reorder_tailq.head, rte_reorder_list);\n\n\trte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);\n\tTAILQ_FOREACH(te, reorder_list, next) {\n\t\tb = (struct rte_reorder_buffer *) te->data;\n\t\tif (strncmp(name, b->name, RTE_REORDER_NAMESIZE) == 0)\n\t\t\tbreak;\n\t}\n\trte_rwlock_read_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\tif (te == NULL) {\n\t\trte_errno = ENOENT;\n\t\treturn NULL;\n\t}\n\n\treturn b;\n}\n\nstatic unsigned\nrte_reorder_fill_overflow(struct rte_reorder_buffer *b, unsigned n)\n{\n\t/*\n\t * 1. Move all ready entries that fit to the ready_buf\n\t * 2. check if we meet the minimum needed (n).\n\t * 3. If not, then skip any gaps and keep moving.\n\t * 4. If at any point the ready buffer is full, stop\n\t * 5. Return the number of positions the order_buf head has moved\n\t */\n\n\tstruct cir_buffer *order_buf = &b->order_buf,\n\t\t\t*ready_buf = &b->ready_buf;\n\n\tunsigned int order_head_adv = 0;\n\n\t/*\n\t * move at least n packets to ready buffer, assuming ready buffer\n\t * has room for those packets.\n\t */\n\twhile (order_head_adv < n &&\n\t\t\t((ready_buf->head + 1) & ready_buf->mask) != ready_buf->tail) {\n\n\t\t/* if we are blocked waiting on a packet, skip it */\n\t\tif (order_buf->entries[order_buf->head] == NULL) {\n\t\t\torder_buf->head = (order_buf->head + 1) & order_buf->mask;\n\t\t\torder_head_adv++;\n\t\t}\n\n\t\t/* Move all ready entries that fit to the ready_buf */\n\t\twhile (order_buf->entries[order_buf->head] != NULL) {\n\t\t\tready_buf->entries[ready_buf->head] =\n\t\t\t\t\torder_buf->entries[order_buf->head];\n\n\t\t\torder_buf->entries[order_buf->head] = NULL;\n\t\t\torder_head_adv++;\n\n\t\t\torder_buf->head = (order_buf->head + 1) & order_buf->mask;\n\n\t\t\tif (((ready_buf->head + 1) & ready_buf->mask) == ready_buf->tail)\n\t\t\t\tbreak;\n\n\t\t\tready_buf->head = (ready_buf->head + 1) & ready_buf->mask;\n\t\t}\n\t}\n\n\tb->min_seqn += order_head_adv;\n\t/* Return the number of positions the order_buf head has moved */\n\treturn order_head_adv;\n}\n\nint\nrte_reorder_insert(struct rte_reorder_buffer *b, struct rte_mbuf *mbuf)\n{\n\tuint32_t offset, position;\n\tstruct cir_buffer *order_buf = &b->order_buf;\n\n\tif (!b->is_initialized) {\n\t\tb->min_seqn = mbuf->seqn;\n\t\tb->is_initialized = 1;\n\t}\n\n\t/*\n\t * calculate the offset from the head pointer we need to go.\n\t * The subtraction takes care of the sequence number wrapping.\n\t * For example (using 16-bit for brevity):\n\t *\tmin_seqn = 0xFFFD\n\t *\tmbuf_seqn = 0x0010\n\t *\toffset = 0x0010 - 0xFFFD = 0x13\n\t */\n\toffset = mbuf->seqn - b->min_seqn;\n\n\t/*\n\t * action to take depends on offset.\n\t * offset < buffer->size: the mbuf fits within the current window of\n\t * sequence numbers we can reorder. EXPECTED CASE.\n\t * offset > buffer->size: the mbuf is outside the current window. There\n\t * are a number of cases to consider:\n\t * 1. The packet sequence is just outside the window, then we need\n\t * to see about shifting the head pointer and taking any ready\n\t * to return packets out of the ring. If there was a delayed\n\t * or dropped packet preventing drains from shifting the window\n\t * this case will skip over the dropped packet instead, and any\n\t * packets dequeued here will be returned on the next drain call.\n\t * 2. The packet sequence number is vastly outside our window, taken\n\t * here as having offset greater than twice the buffer size. In\n\t * this case, the packet is probably an old or late packet that\n\t * was previously skipped, so just enqueue the packet for\n\t * immediate return on the next drain call, or else return error.\n\t */\n\tif (offset < b->order_buf.size) {\n\t\tposition = (order_buf->head + offset) & order_buf->mask;\n\t\torder_buf->entries[position] = mbuf;\n\t} else if (offset < 2 * b->order_buf.size) {\n\t\tif (rte_reorder_fill_overflow(b, offset + 1 - order_buf->size)\n\t\t\t\t< (offset + 1 - order_buf->size)) {\n\t\t\t/* Put in handling for enqueue straight to output */\n\t\t\trte_errno = ENOSPC;\n\t\t\treturn -1;\n\t\t}\n\t\toffset = mbuf->seqn - b->min_seqn;\n\t\tposition = (order_buf->head + offset) & order_buf->mask;\n\t\torder_buf->entries[position] = mbuf;\n\t} else {\n\t\t/* Put in handling for enqueue straight to output */\n\t\trte_errno = ERANGE;\n\t\treturn -1;\n\t}\n\treturn 0;\n}\n\nunsigned int\nrte_reorder_drain(struct rte_reorder_buffer *b, struct rte_mbuf **mbufs,\n\t\tunsigned max_mbufs)\n{\n\tunsigned int drain_cnt = 0;\n\n\tstruct cir_buffer *order_buf = &b->order_buf,\n\t\t\t*ready_buf = &b->ready_buf;\n\n\t/* Try to fetch requested number of mbufs from ready buffer */\n\twhile ((drain_cnt < max_mbufs) && (ready_buf->tail != ready_buf->head)) {\n\t\tmbufs[drain_cnt++] = ready_buf->entries[ready_buf->tail];\n\t\tready_buf->tail = (ready_buf->tail + 1) & ready_buf->mask;\n\t}\n\n\t/*\n\t * If requested number of buffers not fetched from ready buffer, fetch\n\t * remaining buffers from order buffer\n\t */\n\twhile ((drain_cnt < max_mbufs) &&\n\t\t\t(order_buf->entries[order_buf->head] != NULL)) {\n\t\tmbufs[drain_cnt++] = order_buf->entries[order_buf->head];\n\t\torder_buf->entries[order_buf->head] = NULL;\n\t\tb->min_seqn++;\n\t\torder_buf->head = (order_buf->head + 1) & order_buf->mask;\n\t}\n\n\treturn drain_cnt;\n}\n" }, { "path": "lib/librte_reorder/rte_reorder.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_REORDER_H_\n#define _RTE_REORDER_H_\n\n/**\n * @file\n * RTE reorder\n *\n * Reorder library is a component which is designed to\n * provide ordering of out of ordered packets based on\n * sequence number present in mbuf.\n *\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct rte_reorder_buffer;\n\n/**\n * Create a new reorder buffer instance\n *\n * Allocate memory and initialize a new reorder buffer in that\n * memory, returning the reorder buffer pointer to the user\n *\n * @param name\n * The name to be given to the reorder buffer instance.\n * @param socket_id\n * The NUMA node on which the memory for the reorder buffer\n * instance is to be reserved.\n * @param size\n * Max number of elements that can be stored in the reorder buffer\n * @return\n * The initialized reorder buffer instance, or NULL on error\n * On error case, rte_errno will be set appropriately:\n * - ENOMEM - no appropriate memory area found in which to create memzone\n * - EINVAL - invalid parameters\n */\nstruct rte_reorder_buffer *\nrte_reorder_create(const char *name, unsigned socket_id, unsigned int size);\n\n/**\n * Initializes given reorder buffer instance\n *\n * @param b\n * Reorder buffer instance to initialize\n * @param bufsize\n * Size of the reorder buffer\n * @param name\n * The name to be given to the reorder buffer\n * @param size\n * Number of elements that can be stored in reorder buffer\n * @return\n * The initialized reorder buffer instance, or NULL on error\n * On error case, rte_errno will be set appropriately:\n * - EINVAL - invalid parameters\n */\nstruct rte_reorder_buffer *\nrte_reorder_init(struct rte_reorder_buffer *b, unsigned int bufsize,\n\t\tconst char *name, unsigned int size);\n\n/**\n * Find an existing reorder buffer instance\n * and return a pointer to it.\n *\n * @param name\n * Name of the reorder buffer instacne as passed to rte_reorder_create()\n * @return\n * Pointer to reorder buffer instance or NULL if object not found with rte_errno\n * set appropriately. Possible rte_errno values include:\n * - ENOENT - required entry not available to return.\n * reorder instance list\n */\nstruct rte_reorder_buffer *\nrte_reorder_find_existing(const char *name);\n\n/**\n * Reset the given reorder buffer instance with initial values.\n *\n * @param b\n * Reorder buffer instance which has to be reset\n */\nvoid\nrte_reorder_reset(struct rte_reorder_buffer *b);\n\n/**\n * Free reorder buffer instance.\n *\n * @param b\n * reorder buffer instance\n * @return\n * None\n */\nvoid\nrte_reorder_free(struct rte_reorder_buffer *b);\n\n/**\n * Insert given mbuf in reorder buffer in its correct position\n *\n * The given mbuf is to be reordered relative to other mbufs in the system.\n * The mbuf must contain a sequence number which is then used to place\n * the buffer in the correct position in the reorder buffer. Reordered\n * packets can later be taken from the buffer using the rte_reorder_drain()\n * API.\n *\n * @param b\n * Reorder buffer where the mbuf has to be inserted.\n * @param mbuf\n * mbuf of packet that needs to be inserted in reorder buffer.\n * @return\n * 0 on success\n * -1 on error\n * On error case, rte_errno will be set appropriately:\n * - ENOSPC - Cannot move existing mbufs from reorder buffer to accommodate\n * ealry mbuf, but it can be accomodated by performing drain and then insert.\n * - ERANGE - Too early or late mbuf which is vastly out of range of expected\n * window should be ingnored without any handling.\n */\nint\nrte_reorder_insert(struct rte_reorder_buffer *b, struct rte_mbuf *mbuf);\n\n/**\n * Fetch reordered buffers\n *\n * Returns a set of in-order buffers from the reorder buffer structure. Gaps\n * may be present in the sequence numbers of the mbuf if packets have been\n * delayed too long before reaching the reorder window, or have been previously\n * dropped by the system.\n *\n * @param b\n * Reorder buffer instance from which packets are to be drained\n * @param mbufs\n * array of mbufs where reordered packets will be inserted from reorder buffer\n * @param max_mbufs\n * the number of elements in the mbufs array.\n * @return\n * number of mbuf pointers written to mbufs. 0 <= N < max_mbufs.\n */\nunsigned int\nrte_reorder_drain(struct rte_reorder_buffer *b, struct rte_mbuf **mbufs,\n\t\tunsigned max_mbufs);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_REORDER_H_ */\n" }, { "path": "lib/librte_ring/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_ring.a\n\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3\n\nEXPORT_MAP := rte_ring_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_RING) := rte_ring.c\n\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_RING)-include := rte_ring.h\n\nDEPDIRS-$(CONFIG_RTE_LIBRTE_RING) += lib/librte_eal\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_ring/rte_ring.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Derived from FreeBSD's bufring.c\n *\n **************************************************************************\n *\n * Copyright (c) 2007,2008 Kip Macy kmacy@freebsd.org\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2. The name of Kip Macy nor the names of other\n * contributors may be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ***************************************************************************/\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_ring.h\"\n\nTAILQ_HEAD(rte_ring_list, rte_tailq_entry);\n\nstatic struct rte_tailq_elem rte_ring_tailq = {\n\t.name = RTE_TAILQ_RING_NAME,\n};\nEAL_REGISTER_TAILQ(rte_ring_tailq)\n\n/* true if x is a power of 2 */\n#define POWEROF2(x) ((((x)-1) & (x)) == 0)\n\n/* return the size of memory occupied by a ring */\nssize_t\nrte_ring_get_memsize(unsigned count)\n{\n\tssize_t sz;\n\n\t/* count must be a power of 2 */\n\tif ((!POWEROF2(count)) || (count > RTE_RING_SZ_MASK )) {\n\t\tRTE_LOG(ERR, RING,\n\t\t\t\"Requested size is invalid, must be power of 2, and \"\n\t\t\t\"do not exceed the size limit %u\\n\", RTE_RING_SZ_MASK);\n\t\treturn -EINVAL;\n\t}\n\n\tsz = sizeof(struct rte_ring) + count * sizeof(void *);\n\tsz = RTE_ALIGN(sz, RTE_CACHE_LINE_SIZE);\n\treturn sz;\n}\n\nint\nrte_ring_init(struct rte_ring *r, const char *name, unsigned count,\n\tunsigned flags)\n{\n\t/* compilation-time checks */\n\tRTE_BUILD_BUG_ON((sizeof(struct rte_ring) &\n\t\t\t RTE_CACHE_LINE_MASK) != 0);\n#ifdef RTE_RING_SPLIT_PROD_CONS\n\tRTE_BUILD_BUG_ON((offsetof(struct rte_ring, cons) &\n\t\t\t RTE_CACHE_LINE_MASK) != 0);\n#endif\n\tRTE_BUILD_BUG_ON((offsetof(struct rte_ring, prod) &\n\t\t\t RTE_CACHE_LINE_MASK) != 0);\n#ifdef RTE_LIBRTE_RING_DEBUG\n\tRTE_BUILD_BUG_ON((sizeof(struct rte_ring_debug_stats) &\n\t\t\t RTE_CACHE_LINE_MASK) != 0);\n\tRTE_BUILD_BUG_ON((offsetof(struct rte_ring, stats) &\n\t\t\t RTE_CACHE_LINE_MASK) != 0);\n#endif\n\n\t/* init the ring structure */\n\tmemset(r, 0, sizeof(*r));\n\tsnprintf(r->name, sizeof(r->name), \"%s\", name);\n\tr->flags = flags;\n\tr->prod.watermark = count;\n\tr->prod.sp_enqueue = !!(flags & RING_F_SP_ENQ);\n\tr->cons.sc_dequeue = !!(flags & RING_F_SC_DEQ);\n\tr->prod.size = r->cons.size = count;\n\tr->prod.mask = r->cons.mask = count-1;\n\tr->prod.head = r->cons.head = 0;\n\tr->prod.tail = r->cons.tail = 0;\n\n\treturn 0;\n}\n\n/* create the ring */\nstruct rte_ring *\nrte_ring_create(const char *name, unsigned count, int socket_id,\n\t\tunsigned flags)\n{\n\tchar mz_name[RTE_MEMZONE_NAMESIZE];\n\tstruct rte_ring *r;\n\tstruct rte_tailq_entry *te;\n\tconst struct rte_memzone *mz;\n\tssize_t ring_size;\n\tint mz_flags = 0;\n\tstruct rte_ring_list* ring_list = NULL;\n\n\tring_list = RTE_TAILQ_CAST(rte_ring_tailq.head, rte_ring_list);\n\n\tring_size = rte_ring_get_memsize(count);\n\tif (ring_size < 0) {\n\t\trte_errno = ring_size;\n\t\treturn NULL;\n\t}\n\n\tte = rte_zmalloc(\"RING_TAILQ_ENTRY\", sizeof(*te), 0);\n\tif (te == NULL) {\n\t\tRTE_LOG(ERR, RING, \"Cannot reserve memory for tailq\\n\");\n\t\trte_errno = ENOMEM;\n\t\treturn NULL;\n\t}\n\n\tsnprintf(mz_name, sizeof(mz_name), \"%s%s\", RTE_RING_MZ_PREFIX, name);\n\n\trte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\t/* reserve a memory zone for this ring. If we can't get rte_config or\n\t * we are secondary process, the memzone_reserve function will set\n\t * rte_errno for us appropriately - hence no check in this this function */\n\tmz = rte_memzone_reserve(mz_name, ring_size, socket_id, mz_flags);\n\tif (mz != NULL) {\n\t\tr = mz->addr;\n\t\t/* no need to check return value here, we already checked the\n\t\t * arguments above */\n\t\trte_ring_init(r, name, count, flags);\n\n\t\tte->data = (void *) r;\n\n\t\tTAILQ_INSERT_TAIL(ring_list, te, next);\n\t} else {\n\t\tr = NULL;\n\t\tRTE_LOG(ERR, RING, \"Cannot reserve memory\\n\");\n\t\trte_free(te);\n\t}\n\trte_rwlock_write_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\treturn r;\n}\n\n/*\n * change the high water mark. If *count* is 0, water marking is\n * disabled\n */\nint\nrte_ring_set_water_mark(struct rte_ring *r, unsigned count)\n{\n\tif (count >= r->prod.size)\n\t\treturn -EINVAL;\n\n\t/* if count is 0, disable the watermarking */\n\tif (count == 0)\n\t\tcount = r->prod.size;\n\n\tr->prod.watermark = count;\n\treturn 0;\n}\n\n/* dump the status of the ring on the console */\nvoid\nrte_ring_dump(FILE *f, const struct rte_ring *r)\n{\n#ifdef RTE_LIBRTE_RING_DEBUG\n\tstruct rte_ring_debug_stats sum;\n\tunsigned lcore_id;\n#endif\n\n\tfprintf(f, \"ring <%s>@%p\\n\", r->name, r);\n\tfprintf(f, \" flags=%x\\n\", r->flags);\n\tfprintf(f, \" size=%\"PRIu32\"\\n\", r->prod.size);\n\tfprintf(f, \" ct=%\"PRIu32\"\\n\", r->cons.tail);\n\tfprintf(f, \" ch=%\"PRIu32\"\\n\", r->cons.head);\n\tfprintf(f, \" pt=%\"PRIu32\"\\n\", r->prod.tail);\n\tfprintf(f, \" ph=%\"PRIu32\"\\n\", r->prod.head);\n\tfprintf(f, \" used=%u\\n\", rte_ring_count(r));\n\tfprintf(f, \" avail=%u\\n\", rte_ring_free_count(r));\n\tif (r->prod.watermark == r->prod.size)\n\t\tfprintf(f, \" watermark=0\\n\");\n\telse\n\t\tfprintf(f, \" watermark=%\"PRIu32\"\\n\", r->prod.watermark);\n\n\t/* sum and dump statistics */\n#ifdef RTE_LIBRTE_RING_DEBUG\n\tmemset(&sum, 0, sizeof(sum));\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tsum.enq_success_bulk += r->stats[lcore_id].enq_success_bulk;\n\t\tsum.enq_success_objs += r->stats[lcore_id].enq_success_objs;\n\t\tsum.enq_quota_bulk += r->stats[lcore_id].enq_quota_bulk;\n\t\tsum.enq_quota_objs += r->stats[lcore_id].enq_quota_objs;\n\t\tsum.enq_fail_bulk += r->stats[lcore_id].enq_fail_bulk;\n\t\tsum.enq_fail_objs += r->stats[lcore_id].enq_fail_objs;\n\t\tsum.deq_success_bulk += r->stats[lcore_id].deq_success_bulk;\n\t\tsum.deq_success_objs += r->stats[lcore_id].deq_success_objs;\n\t\tsum.deq_fail_bulk += r->stats[lcore_id].deq_fail_bulk;\n\t\tsum.deq_fail_objs += r->stats[lcore_id].deq_fail_objs;\n\t}\n\tfprintf(f, \" size=%\"PRIu32\"\\n\", r->prod.size);\n\tfprintf(f, \" enq_success_bulk=%\"PRIu64\"\\n\", sum.enq_success_bulk);\n\tfprintf(f, \" enq_success_objs=%\"PRIu64\"\\n\", sum.enq_success_objs);\n\tfprintf(f, \" enq_quota_bulk=%\"PRIu64\"\\n\", sum.enq_quota_bulk);\n\tfprintf(f, \" enq_quota_objs=%\"PRIu64\"\\n\", sum.enq_quota_objs);\n\tfprintf(f, \" enq_fail_bulk=%\"PRIu64\"\\n\", sum.enq_fail_bulk);\n\tfprintf(f, \" enq_fail_objs=%\"PRIu64\"\\n\", sum.enq_fail_objs);\n\tfprintf(f, \" deq_success_bulk=%\"PRIu64\"\\n\", sum.deq_success_bulk);\n\tfprintf(f, \" deq_success_objs=%\"PRIu64\"\\n\", sum.deq_success_objs);\n\tfprintf(f, \" deq_fail_bulk=%\"PRIu64\"\\n\", sum.deq_fail_bulk);\n\tfprintf(f, \" deq_fail_objs=%\"PRIu64\"\\n\", sum.deq_fail_objs);\n#else\n\tfprintf(f, \" no statistics available\\n\");\n#endif\n}\n\n/* dump the status of all rings on the console */\nvoid\nrte_ring_list_dump(FILE *f)\n{\n\tconst struct rte_tailq_entry *te;\n\tstruct rte_ring_list *ring_list;\n\n\tring_list = RTE_TAILQ_CAST(rte_ring_tailq.head, rte_ring_list);\n\n\trte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\tTAILQ_FOREACH(te, ring_list, next) {\n\t\trte_ring_dump(f, (struct rte_ring *) te->data);\n\t}\n\n\trte_rwlock_read_unlock(RTE_EAL_TAILQ_RWLOCK);\n}\n\n/* search a ring from its name */\nstruct rte_ring *\nrte_ring_lookup(const char *name)\n{\n\tstruct rte_tailq_entry *te;\n\tstruct rte_ring *r = NULL;\n\tstruct rte_ring_list *ring_list;\n\n\tring_list = RTE_TAILQ_CAST(rte_ring_tailq.head, rte_ring_list);\n\n\trte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);\n\n\tTAILQ_FOREACH(te, ring_list, next) {\n\t\tr = (struct rte_ring *) te->data;\n\t\tif (strncmp(name, r->name, RTE_RING_NAMESIZE) == 0)\n\t\t\tbreak;\n\t}\n\n\trte_rwlock_read_unlock(RTE_EAL_TAILQ_RWLOCK);\n\n\tif (te == NULL) {\n\t\trte_errno = ENOENT;\n\t\treturn NULL;\n\t}\n\n\treturn r;\n}\n" }, { "path": "lib/librte_ring/rte_ring.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n/*\n * Derived from FreeBSD's bufring.h\n *\n **************************************************************************\n *\n * Copyright (c) 2007-2009 Kip Macy kmacy@freebsd.org\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2. The name of Kip Macy nor the names of other\n * contributors may be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE\n * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n * POSSIBILITY OF SUCH DAMAGE.\n *\n ***************************************************************************/\n\n#ifndef _RTE_RING_H_\n#define _RTE_RING_H_\n\n/**\n * @file\n * RTE Ring\n *\n * The Ring Manager is a fixed-size queue, implemented as a table of\n * pointers. Head and tail pointers are modified atomically, allowing\n * concurrent access to it. It has the following features:\n *\n * - FIFO (First In First Out)\n * - Maximum size is fixed; the pointers are stored in a table.\n * - Lockless implementation.\n * - Multi- or single-consumer dequeue.\n * - Multi- or single-producer enqueue.\n * - Bulk dequeue.\n * - Bulk enqueue.\n *\n * Note: the ring implementation is not preemptable. A lcore must not\n * be interrupted by another task that uses the same ring.\n *\n */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#define RTE_TAILQ_RING_NAME \"RTE_RING\"\n\nenum rte_ring_queue_behavior {\n\tRTE_RING_QUEUE_FIXED = 0, /* Enq/Deq a fixed number of items from a ring */\n\tRTE_RING_QUEUE_VARIABLE /* Enq/Deq as many items a possible from ring */\n};\n\n#ifdef RTE_LIBRTE_RING_DEBUG\n/**\n * A structure that stores the ring statistics (per-lcore).\n */\nstruct rte_ring_debug_stats {\n\tuint64_t enq_success_bulk; /**< Successful enqueues number. */\n\tuint64_t enq_success_objs; /**< Objects successfully enqueued. */\n\tuint64_t enq_quota_bulk; /**< Successful enqueues above watermark. */\n\tuint64_t enq_quota_objs; /**< Objects enqueued above watermark. */\n\tuint64_t enq_fail_bulk; /**< Failed enqueues number. */\n\tuint64_t enq_fail_objs; /**< Objects that failed to be enqueued. */\n\tuint64_t deq_success_bulk; /**< Successful dequeues number. */\n\tuint64_t deq_success_objs; /**< Objects successfully dequeued. */\n\tuint64_t deq_fail_bulk; /**< Failed dequeues number. */\n\tuint64_t deq_fail_objs; /**< Objects that failed to be dequeued. */\n} __rte_cache_aligned;\n#endif\n\n#define RTE_RING_NAMESIZE 32 /**< The maximum length of a ring name. */\n#define RTE_RING_MZ_PREFIX \"RG_\"\n\n#ifndef RTE_RING_PAUSE_REP_COUNT\n#define RTE_RING_PAUSE_REP_COUNT 0 /**< Yield after pause num of times, no yield\n * if RTE_RING_PAUSE_REP not defined. */\n#endif\n\n/**\n * An RTE ring structure.\n *\n * The producer and the consumer have a head and a tail index. The particularity\n * of these index is that they are not between 0 and size(ring). These indexes\n * are between 0 and 2^32, and we mask their value when we access the ring[]\n * field. Thanks to this assumption, we can do subtractions between 2 index\n * values in a modulo-32bit base: that's why the overflow of the indexes is not\n * a problem.\n */\nstruct rte_ring {\n\tchar name[RTE_RING_NAMESIZE]; /**< Name of the ring. */\n\tint flags; /**< Flags supplied at creation. */\n\n\t/** Ring producer status. */\n\tstruct prod {\n\t\tuint32_t watermark; /**< Maximum items before EDQUOT. */\n\t\tuint32_t sp_enqueue; /**< True, if single producer. */\n\t\tuint32_t size; /**< Size of ring. */\n\t\tuint32_t mask; /**< Mask (size-1) of ring. */\n\t\tvolatile uint32_t head; /**< Producer head. */\n\t\tvolatile uint32_t tail; /**< Producer tail. */\n\t} prod __rte_cache_aligned;\n\n\t/** Ring consumer status. */\n\tstruct cons {\n\t\tuint32_t sc_dequeue; /**< True, if single consumer. */\n\t\tuint32_t size; /**< Size of the ring. */\n\t\tuint32_t mask; /**< Mask (size-1) of ring. */\n\t\tvolatile uint32_t head; /**< Consumer head. */\n\t\tvolatile uint32_t tail; /**< Consumer tail. */\n#ifdef RTE_RING_SPLIT_PROD_CONS\n\t} cons __rte_cache_aligned;\n#else\n\t} cons;\n#endif\n\n#ifdef RTE_LIBRTE_RING_DEBUG\n\tstruct rte_ring_debug_stats stats[RTE_MAX_LCORE];\n#endif\n\n\tvoid * ring[0] __rte_cache_aligned; /**< Memory space of ring starts here.\n\t * not volatile so need to be careful\n\t * about compiler re-ordering */\n};\n\n#define RING_F_SP_ENQ 0x0001 /**< The default enqueue is \"single-producer\". */\n#define RING_F_SC_DEQ 0x0002 /**< The default dequeue is \"single-consumer\". */\n#define RTE_RING_QUOT_EXCEED (1 << 31) /**< Quota exceed for burst ops */\n#define RTE_RING_SZ_MASK (unsigned)(0x0fffffff) /**< Ring size mask */\n\n/**\n * @internal When debug is enabled, store ring statistics.\n * @param r\n * A pointer to the ring.\n * @param name\n * The name of the statistics field to increment in the ring.\n * @param n\n * The number to add to the object-oriented statistics.\n */\n#ifdef RTE_LIBRTE_RING_DEBUG\n#define __RING_STAT_ADD(r, name, n) do { \\\n\t\tunsigned __lcore_id = rte_lcore_id(); \\\n\t\tif (__lcore_id < RTE_MAX_LCORE) { \\\n\t\t\tr->stats[__lcore_id].name##_objs += n; \\\n\t\t\tr->stats[__lcore_id].name##_bulk += 1; \\\n\t\t} \\\n\t} while(0)\n#else\n#define __RING_STAT_ADD(r, name, n) do {} while(0)\n#endif\n\n/**\n * Calculate the memory size needed for a ring\n *\n * This function returns the number of bytes needed for a ring, given\n * the number of elements in it. This value is the sum of the size of\n * the structure rte_ring and the size of the memory needed by the\n * objects pointers. The value is aligned to a cache line size.\n *\n * @param count\n * The number of elements in the ring (must be a power of 2).\n * @return\n * - The memory size needed for the ring on success.\n * - -EINVAL if count is not a power of 2.\n */\nssize_t rte_ring_get_memsize(unsigned count);\n\n/**\n * Initialize a ring structure.\n *\n * Initialize a ring structure in memory pointed by \"r\". The size of the\n * memory area must be large enough to store the ring structure and the\n * object table. It is advised to use rte_ring_get_memsize() to get the\n * appropriate size.\n *\n * The ring size is set to *count*, which must be a power of two. Water\n * marking is disabled by default. The real usable ring size is\n * *count-1* instead of *count* to differentiate a free ring from an\n * empty ring.\n *\n * The ring is not added in RTE_TAILQ_RING global list. Indeed, the\n * memory given by the caller may not be shareable among dpdk\n * processes.\n *\n * @param r\n * The pointer to the ring structure followed by the objects table.\n * @param name\n * The name of the ring.\n * @param count\n * The number of elements in the ring (must be a power of 2).\n * @param flags\n * An OR of the following:\n * - RING_F_SP_ENQ: If this flag is set, the default behavior when\n * using ``rte_ring_enqueue()`` or ``rte_ring_enqueue_bulk()``\n * is \"single-producer\". Otherwise, it is \"multi-producers\".\n * - RING_F_SC_DEQ: If this flag is set, the default behavior when\n * using ``rte_ring_dequeue()`` or ``rte_ring_dequeue_bulk()``\n * is \"single-consumer\". Otherwise, it is \"multi-consumers\".\n * @return\n * 0 on success, or a negative value on error.\n */\nint rte_ring_init(struct rte_ring *r, const char *name, unsigned count,\n\tunsigned flags);\n\n/**\n * Create a new ring named *name* in memory.\n *\n * This function uses ``memzone_reserve()`` to allocate memory. Then it\n * calls rte_ring_init() to initialize an empty ring.\n *\n * The new ring size is set to *count*, which must be a power of\n * two. Water marking is disabled by default. The real usable ring size\n * is *count-1* instead of *count* to differentiate a free ring from an\n * empty ring.\n *\n * The ring is added in RTE_TAILQ_RING list.\n *\n * @param name\n * The name of the ring.\n * @param count\n * The size of the ring (must be a power of 2).\n * @param socket_id\n * The *socket_id* argument is the socket identifier in case of\n * NUMA. The value can be *SOCKET_ID_ANY* if there is no NUMA\n * constraint for the reserved zone.\n * @param flags\n * An OR of the following:\n * - RING_F_SP_ENQ: If this flag is set, the default behavior when\n * using ``rte_ring_enqueue()`` or ``rte_ring_enqueue_bulk()``\n * is \"single-producer\". Otherwise, it is \"multi-producers\".\n * - RING_F_SC_DEQ: If this flag is set, the default behavior when\n * using ``rte_ring_dequeue()`` or ``rte_ring_dequeue_bulk()``\n * is \"single-consumer\". Otherwise, it is \"multi-consumers\".\n * @return\n * On success, the pointer to the new allocated ring. NULL on error with\n * rte_errno set appropriately. Possible errno values include:\n * - E_RTE_NO_CONFIG - function could not get pointer to rte_config structure\n * - E_RTE_SECONDARY - function was called from a secondary process instance\n * - EINVAL - count provided is not a power of 2\n * - ENOSPC - the maximum number of memzones has already been allocated\n * - EEXIST - a memzone with the same name already exists\n * - ENOMEM - no appropriate memory area found in which to create memzone\n */\nstruct rte_ring *rte_ring_create(const char *name, unsigned count,\n\t\t\t\t int socket_id, unsigned flags);\n\n/**\n * Change the high water mark.\n *\n * If *count* is 0, water marking is disabled. Otherwise, it is set to the\n * *count* value. The *count* value must be greater than 0 and less\n * than the ring size.\n *\n * This function can be called at any time (not necessarily at\n * initialization).\n *\n * @param r\n * A pointer to the ring structure.\n * @param count\n * The new water mark value.\n * @return\n * - 0: Success; water mark changed.\n * - -EINVAL: Invalid water mark value.\n */\nint rte_ring_set_water_mark(struct rte_ring *r, unsigned count);\n\n/**\n * Dump the status of the ring to the console.\n *\n * @param f\n * A pointer to a file for output\n * @param r\n * A pointer to the ring structure.\n */\nvoid rte_ring_dump(FILE *f, const struct rte_ring *r);\n\n/* the actual enqueue of pointers on the ring.\n * Placed here since identical code needed in both\n * single and multi producer enqueue functions */\n#define ENQUEUE_PTRS() do { \\\n\tconst uint32_t size = r->prod.size; \\\n\tuint32_t idx = prod_head & mask; \\\n\tif (likely(idx + n < size)) { \\\n\t\tfor (i = 0; i < (n & ((~(unsigned)0x3))); i+=4, idx+=4) { \\\n\t\t\tr->ring[idx] = obj_table[i]; \\\n\t\t\tr->ring[idx+1] = obj_table[i+1]; \\\n\t\t\tr->ring[idx+2] = obj_table[i+2]; \\\n\t\t\tr->ring[idx+3] = obj_table[i+3]; \\\n\t\t} \\\n\t\tswitch (n & 0x3) { \\\n\t\t\tcase 3: r->ring[idx++] = obj_table[i++]; \\\n\t\t\tcase 2: r->ring[idx++] = obj_table[i++]; \\\n\t\t\tcase 1: r->ring[idx++] = obj_table[i++]; \\\n\t\t} \\\n\t} else { \\\n\t\tfor (i = 0; idx < size; i++, idx++)\\\n\t\t\tr->ring[idx] = obj_table[i]; \\\n\t\tfor (idx = 0; i < n; i++, idx++) \\\n\t\t\tr->ring[idx] = obj_table[i]; \\\n\t} \\\n} while(0)\n\n/* the actual copy of pointers on the ring to obj_table.\n * Placed here since identical code needed in both\n * single and multi consumer dequeue functions */\n#define DEQUEUE_PTRS() do { \\\n\tuint32_t idx = cons_head & mask; \\\n\tconst uint32_t size = r->cons.size; \\\n\tif (likely(idx + n < size)) { \\\n\t\tfor (i = 0; i < (n & (~(unsigned)0x3)); i+=4, idx+=4) {\\\n\t\t\tobj_table[i] = r->ring[idx]; \\\n\t\t\tobj_table[i+1] = r->ring[idx+1]; \\\n\t\t\tobj_table[i+2] = r->ring[idx+2]; \\\n\t\t\tobj_table[i+3] = r->ring[idx+3]; \\\n\t\t} \\\n\t\tswitch (n & 0x3) { \\\n\t\t\tcase 3: obj_table[i++] = r->ring[idx++]; \\\n\t\t\tcase 2: obj_table[i++] = r->ring[idx++]; \\\n\t\t\tcase 1: obj_table[i++] = r->ring[idx++]; \\\n\t\t} \\\n\t} else { \\\n\t\tfor (i = 0; idx < size; i++, idx++) \\\n\t\t\tobj_table[i] = r->ring[idx]; \\\n\t\tfor (idx = 0; i < n; i++, idx++) \\\n\t\t\tobj_table[i] = r->ring[idx]; \\\n\t} \\\n} while (0)\n\n/**\n * @internal Enqueue several objects on the ring (multi-producers safe).\n *\n * This function uses a \"compare and set\" instruction to move the\n * producer index atomically.\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to add in the ring from the obj_table.\n * @param behavior\n * RTE_RING_QUEUE_FIXED: Enqueue a fixed number of items from a ring\n * RTE_RING_QUEUE_VARIABLE: Enqueue as many items a possible from ring\n * @return\n * Depend on the behavior value\n * if behavior = RTE_RING_QUEUE_FIXED\n * - 0: Success; objects enqueue.\n * - -EDQUOT: Quota exceeded. The objects have been enqueued, but the\n * high water mark is exceeded.\n * - -ENOBUFS: Not enough room in the ring to enqueue, no object is enqueued.\n * if behavior = RTE_RING_QUEUE_VARIABLE\n * - n: Actual number of objects enqueued.\n */\nstatic inline int __attribute__((always_inline))\n__rte_ring_mp_do_enqueue(struct rte_ring *r, void * const *obj_table,\n\t\t\t unsigned n, enum rte_ring_queue_behavior behavior)\n{\n\tuint32_t prod_head, prod_next;\n\tuint32_t cons_tail, free_entries;\n\tconst unsigned max = n;\n\tint success;\n\tunsigned i, rep = 0;\n\tuint32_t mask = r->prod.mask;\n\tint ret;\n\n\t/* move prod.head atomically */\n\tdo {\n\t\t/* Reset n to the initial burst count */\n\t\tn = max;\n\n\t\tprod_head = r->prod.head;\n\t\tcons_tail = r->cons.tail;\n\t\t/* The subtraction is done between two unsigned 32bits value\n\t\t * (the result is always modulo 32 bits even if we have\n\t\t * prod_head > cons_tail). So 'free_entries' is always between 0\n\t\t * and size(ring)-1. */\n\t\tfree_entries = (mask + cons_tail - prod_head);\n\n\t\t/* check that we have enough room in ring */\n\t\tif (unlikely(n > free_entries)) {\n\t\t\tif (behavior == RTE_RING_QUEUE_FIXED) {\n\t\t\t\t__RING_STAT_ADD(r, enq_fail, n);\n\t\t\t\treturn -ENOBUFS;\n\t\t\t}\n\t\t\telse {\n\t\t\t\t/* No free entry available */\n\t\t\t\tif (unlikely(free_entries == 0)) {\n\t\t\t\t\t__RING_STAT_ADD(r, enq_fail, n);\n\t\t\t\t\treturn 0;\n\t\t\t\t}\n\n\t\t\t\tn = free_entries;\n\t\t\t}\n\t\t}\n\n\t\tprod_next = prod_head + n;\n\t\tsuccess = rte_atomic32_cmpset(&r->prod.head, prod_head,\n\t\t\t\t\t prod_next);\n\t} while (unlikely(success == 0));\n\n\t/* write entries in ring */\n\tENQUEUE_PTRS();\n\trte_compiler_barrier();\n\n\t/* if we exceed the watermark */\n\tif (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) {\n\t\tret = (behavior == RTE_RING_QUEUE_FIXED) ? -EDQUOT :\n\t\t\t\t(int)(n | RTE_RING_QUOT_EXCEED);\n\t\t__RING_STAT_ADD(r, enq_quota, n);\n\t}\n\telse {\n\t\tret = (behavior == RTE_RING_QUEUE_FIXED) ? 0 : n;\n\t\t__RING_STAT_ADD(r, enq_success, n);\n\t}\n\n\t/*\n\t * If there are other enqueues in progress that preceded us,\n\t * we need to wait for them to complete\n\t */\n\twhile (unlikely(r->prod.tail != prod_head)) {\n\t\trte_pause();\n\n\t\t/* Set RTE_RING_PAUSE_REP_COUNT to avoid spin too long waiting\n\t\t * for other thread finish. It gives pre-empted thread a chance\n\t\t * to proceed and finish with ring dequeue operation. */\n\t\tif (RTE_RING_PAUSE_REP_COUNT &&\n\t\t ++rep == RTE_RING_PAUSE_REP_COUNT) {\n\t\t\trep = 0;\n\t\t\tsched_yield();\n\t\t}\n\t}\n\tr->prod.tail = prod_next;\n\treturn ret;\n}\n\n/**\n * @internal Enqueue several objects on a ring (NOT multi-producers safe).\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to add in the ring from the obj_table.\n * @param behavior\n * RTE_RING_QUEUE_FIXED: Enqueue a fixed number of items from a ring\n * RTE_RING_QUEUE_VARIABLE: Enqueue as many items a possible from ring\n * @return\n * Depend on the behavior value\n * if behavior = RTE_RING_QUEUE_FIXED\n * - 0: Success; objects enqueue.\n * - -EDQUOT: Quota exceeded. The objects have been enqueued, but the\n * high water mark is exceeded.\n * - -ENOBUFS: Not enough room in the ring to enqueue, no object is enqueued.\n * if behavior = RTE_RING_QUEUE_VARIABLE\n * - n: Actual number of objects enqueued.\n */\nstatic inline int __attribute__((always_inline))\n__rte_ring_sp_do_enqueue(struct rte_ring *r, void * const *obj_table,\n\t\t\t unsigned n, enum rte_ring_queue_behavior behavior)\n{\n\tuint32_t prod_head, cons_tail;\n\tuint32_t prod_next, free_entries;\n\tunsigned i;\n\tuint32_t mask = r->prod.mask;\n\tint ret;\n\n\tprod_head = r->prod.head;\n\tcons_tail = r->cons.tail;\n\t/* The subtraction is done between two unsigned 32bits value\n\t * (the result is always modulo 32 bits even if we have\n\t * prod_head > cons_tail). So 'free_entries' is always between 0\n\t * and size(ring)-1. */\n\tfree_entries = mask + cons_tail - prod_head;\n\n\t/* check that we have enough room in ring */\n\tif (unlikely(n > free_entries)) {\n\t\tif (behavior == RTE_RING_QUEUE_FIXED) {\n\t\t\t__RING_STAT_ADD(r, enq_fail, n);\n\t\t\treturn -ENOBUFS;\n\t\t}\n\t\telse {\n\t\t\t/* No free entry available */\n\t\t\tif (unlikely(free_entries == 0)) {\n\t\t\t\t__RING_STAT_ADD(r, enq_fail, n);\n\t\t\t\treturn 0;\n\t\t\t}\n\n\t\t\tn = free_entries;\n\t\t}\n\t}\n\n\tprod_next = prod_head + n;\n\tr->prod.head = prod_next;\n\n\t/* write entries in ring */\n\tENQUEUE_PTRS();\n\trte_compiler_barrier();\n\n\t/* if we exceed the watermark */\n\tif (unlikely(((mask + 1) - free_entries + n) > r->prod.watermark)) {\n\t\tret = (behavior == RTE_RING_QUEUE_FIXED) ? -EDQUOT :\n\t\t\t(int)(n | RTE_RING_QUOT_EXCEED);\n\t\t__RING_STAT_ADD(r, enq_quota, n);\n\t}\n\telse {\n\t\tret = (behavior == RTE_RING_QUEUE_FIXED) ? 0 : n;\n\t\t__RING_STAT_ADD(r, enq_success, n);\n\t}\n\n\tr->prod.tail = prod_next;\n\treturn ret;\n}\n\n/**\n * @internal Dequeue several objects from a ring (multi-consumers safe). When\n * the request objects are more than the available objects, only dequeue the\n * actual number of objects\n *\n * This function uses a \"compare and set\" instruction to move the\n * consumer index atomically.\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects) that will be filled.\n * @param n\n * The number of objects to dequeue from the ring to the obj_table.\n * @param behavior\n * RTE_RING_QUEUE_FIXED: Dequeue a fixed number of items from a ring\n * RTE_RING_QUEUE_VARIABLE: Dequeue as many items a possible from ring\n * @return\n * Depend on the behavior value\n * if behavior = RTE_RING_QUEUE_FIXED\n * - 0: Success; objects dequeued.\n * - -ENOENT: Not enough entries in the ring to dequeue; no object is\n * dequeued.\n * if behavior = RTE_RING_QUEUE_VARIABLE\n * - n: Actual number of objects dequeued.\n */\n\nstatic inline int __attribute__((always_inline))\n__rte_ring_mc_do_dequeue(struct rte_ring *r, void **obj_table,\n\t\t unsigned n, enum rte_ring_queue_behavior behavior)\n{\n\tuint32_t cons_head, prod_tail;\n\tuint32_t cons_next, entries;\n\tconst unsigned max = n;\n\tint success;\n\tunsigned i, rep = 0;\n\tuint32_t mask = r->prod.mask;\n\n\t/* move cons.head atomically */\n\tdo {\n\t\t/* Restore n as it may change every loop */\n\t\tn = max;\n\n\t\tcons_head = r->cons.head;\n\t\tprod_tail = r->prod.tail;\n\t\t/* The subtraction is done between two unsigned 32bits value\n\t\t * (the result is always modulo 32 bits even if we have\n\t\t * cons_head > prod_tail). So 'entries' is always between 0\n\t\t * and size(ring)-1. */\n\t\tentries = (prod_tail - cons_head);\n\n\t\t/* Set the actual entries for dequeue */\n\t\tif (n > entries) {\n\t\t\tif (behavior == RTE_RING_QUEUE_FIXED) {\n\t\t\t\t__RING_STAT_ADD(r, deq_fail, n);\n\t\t\t\treturn -ENOENT;\n\t\t\t}\n\t\t\telse {\n\t\t\t\tif (unlikely(entries == 0)){\n\t\t\t\t\t__RING_STAT_ADD(r, deq_fail, n);\n\t\t\t\t\treturn 0;\n\t\t\t\t}\n\n\t\t\t\tn = entries;\n\t\t\t}\n\t\t}\n\n\t\tcons_next = cons_head + n;\n\t\tsuccess = rte_atomic32_cmpset(&r->cons.head, cons_head,\n\t\t\t\t\t cons_next);\n\t} while (unlikely(success == 0));\n\n\t/* copy in table */\n\tDEQUEUE_PTRS();\n\trte_compiler_barrier();\n\n\t/*\n\t * If there are other dequeues in progress that preceded us,\n\t * we need to wait for them to complete\n\t */\n\twhile (unlikely(r->cons.tail != cons_head)) {\n\t\trte_pause();\n\n\t\t/* Set RTE_RING_PAUSE_REP_COUNT to avoid spin too long waiting\n\t\t * for other thread finish. It gives pre-empted thread a chance\n\t\t * to proceed and finish with ring dequeue operation. */\n\t\tif (RTE_RING_PAUSE_REP_COUNT &&\n\t\t ++rep == RTE_RING_PAUSE_REP_COUNT) {\n\t\t\trep = 0;\n\t\t\tsched_yield();\n\t\t}\n\t}\n\t__RING_STAT_ADD(r, deq_success, n);\n\tr->cons.tail = cons_next;\n\n\treturn behavior == RTE_RING_QUEUE_FIXED ? 0 : n;\n}\n\n/**\n * @internal Dequeue several objects from a ring (NOT multi-consumers safe).\n * When the request objects are more than the available objects, only dequeue\n * the actual number of objects\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects) that will be filled.\n * @param n\n * The number of objects to dequeue from the ring to the obj_table.\n * @param behavior\n * RTE_RING_QUEUE_FIXED: Dequeue a fixed number of items from a ring\n * RTE_RING_QUEUE_VARIABLE: Dequeue as many items a possible from ring\n * @return\n * Depend on the behavior value\n * if behavior = RTE_RING_QUEUE_FIXED\n * - 0: Success; objects dequeued.\n * - -ENOENT: Not enough entries in the ring to dequeue; no object is\n * dequeued.\n * if behavior = RTE_RING_QUEUE_VARIABLE\n * - n: Actual number of objects dequeued.\n */\nstatic inline int __attribute__((always_inline))\n__rte_ring_sc_do_dequeue(struct rte_ring *r, void **obj_table,\n\t\t unsigned n, enum rte_ring_queue_behavior behavior)\n{\n\tuint32_t cons_head, prod_tail;\n\tuint32_t cons_next, entries;\n\tunsigned i;\n\tuint32_t mask = r->prod.mask;\n\n\tcons_head = r->cons.head;\n\tprod_tail = r->prod.tail;\n\t/* The subtraction is done between two unsigned 32bits value\n\t * (the result is always modulo 32 bits even if we have\n\t * cons_head > prod_tail). So 'entries' is always between 0\n\t * and size(ring)-1. */\n\tentries = prod_tail - cons_head;\n\n\tif (n > entries) {\n\t\tif (behavior == RTE_RING_QUEUE_FIXED) {\n\t\t\t__RING_STAT_ADD(r, deq_fail, n);\n\t\t\treturn -ENOENT;\n\t\t}\n\t\telse {\n\t\t\tif (unlikely(entries == 0)){\n\t\t\t\t__RING_STAT_ADD(r, deq_fail, n);\n\t\t\t\treturn 0;\n\t\t\t}\n\n\t\t\tn = entries;\n\t\t}\n\t}\n\n\tcons_next = cons_head + n;\n\tr->cons.head = cons_next;\n\n\t/* copy in table */\n\tDEQUEUE_PTRS();\n\trte_compiler_barrier();\n\n\t__RING_STAT_ADD(r, deq_success, n);\n\tr->cons.tail = cons_next;\n\treturn behavior == RTE_RING_QUEUE_FIXED ? 0 : n;\n}\n\n/**\n * Enqueue several objects on the ring (multi-producers safe).\n *\n * This function uses a \"compare and set\" instruction to move the\n * producer index atomically.\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to add in the ring from the obj_table.\n * @return\n * - 0: Success; objects enqueue.\n * - -EDQUOT: Quota exceeded. The objects have been enqueued, but the\n * high water mark is exceeded.\n * - -ENOBUFS: Not enough room in the ring to enqueue, no object is enqueued.\n */\nstatic inline int __attribute__((always_inline))\nrte_ring_mp_enqueue_bulk(struct rte_ring *r, void * const *obj_table,\n\t\t\t unsigned n)\n{\n\treturn __rte_ring_mp_do_enqueue(r, obj_table, n, RTE_RING_QUEUE_FIXED);\n}\n\n/**\n * Enqueue several objects on a ring (NOT multi-producers safe).\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to add in the ring from the obj_table.\n * @return\n * - 0: Success; objects enqueued.\n * - -EDQUOT: Quota exceeded. The objects have been enqueued, but the\n * high water mark is exceeded.\n * - -ENOBUFS: Not enough room in the ring to enqueue; no object is enqueued.\n */\nstatic inline int __attribute__((always_inline))\nrte_ring_sp_enqueue_bulk(struct rte_ring *r, void * const *obj_table,\n\t\t\t unsigned n)\n{\n\treturn __rte_ring_sp_do_enqueue(r, obj_table, n, RTE_RING_QUEUE_FIXED);\n}\n\n/**\n * Enqueue several objects on a ring.\n *\n * This function calls the multi-producer or the single-producer\n * version depending on the default behavior that was specified at\n * ring creation time (see flags).\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to add in the ring from the obj_table.\n * @return\n * - 0: Success; objects enqueued.\n * - -EDQUOT: Quota exceeded. The objects have been enqueued, but the\n * high water mark is exceeded.\n * - -ENOBUFS: Not enough room in the ring to enqueue; no object is enqueued.\n */\nstatic inline int __attribute__((always_inline))\nrte_ring_enqueue_bulk(struct rte_ring *r, void * const *obj_table,\n\t\t unsigned n)\n{\n\tif (r->prod.sp_enqueue)\n\t\treturn rte_ring_sp_enqueue_bulk(r, obj_table, n);\n\telse\n\t\treturn rte_ring_mp_enqueue_bulk(r, obj_table, n);\n}\n\n/**\n * Enqueue one object on a ring (multi-producers safe).\n *\n * This function uses a \"compare and set\" instruction to move the\n * producer index atomically.\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj\n * A pointer to the object to be added.\n * @return\n * - 0: Success; objects enqueued.\n * - -EDQUOT: Quota exceeded. The objects have been enqueued, but the\n * high water mark is exceeded.\n * - -ENOBUFS: Not enough room in the ring to enqueue; no object is enqueued.\n */\nstatic inline int __attribute__((always_inline))\nrte_ring_mp_enqueue(struct rte_ring *r, void *obj)\n{\n\treturn rte_ring_mp_enqueue_bulk(r, &obj, 1);\n}\n\n/**\n * Enqueue one object on a ring (NOT multi-producers safe).\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj\n * A pointer to the object to be added.\n * @return\n * - 0: Success; objects enqueued.\n * - -EDQUOT: Quota exceeded. The objects have been enqueued, but the\n * high water mark is exceeded.\n * - -ENOBUFS: Not enough room in the ring to enqueue; no object is enqueued.\n */\nstatic inline int __attribute__((always_inline))\nrte_ring_sp_enqueue(struct rte_ring *r, void *obj)\n{\n\treturn rte_ring_sp_enqueue_bulk(r, &obj, 1);\n}\n\n/**\n * Enqueue one object on a ring.\n *\n * This function calls the multi-producer or the single-producer\n * version, depending on the default behaviour that was specified at\n * ring creation time (see flags).\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj\n * A pointer to the object to be added.\n * @return\n * - 0: Success; objects enqueued.\n * - -EDQUOT: Quota exceeded. The objects have been enqueued, but the\n * high water mark is exceeded.\n * - -ENOBUFS: Not enough room in the ring to enqueue; no object is enqueued.\n */\nstatic inline int __attribute__((always_inline))\nrte_ring_enqueue(struct rte_ring *r, void *obj)\n{\n\tif (r->prod.sp_enqueue)\n\t\treturn rte_ring_sp_enqueue(r, obj);\n\telse\n\t\treturn rte_ring_mp_enqueue(r, obj);\n}\n\n/**\n * Dequeue several objects from a ring (multi-consumers safe).\n *\n * This function uses a \"compare and set\" instruction to move the\n * consumer index atomically.\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects) that will be filled.\n * @param n\n * The number of objects to dequeue from the ring to the obj_table.\n * @return\n * - 0: Success; objects dequeued.\n * - -ENOENT: Not enough entries in the ring to dequeue; no object is\n * dequeued.\n */\nstatic inline int __attribute__((always_inline))\nrte_ring_mc_dequeue_bulk(struct rte_ring *r, void **obj_table, unsigned n)\n{\n\treturn __rte_ring_mc_do_dequeue(r, obj_table, n, RTE_RING_QUEUE_FIXED);\n}\n\n/**\n * Dequeue several objects from a ring (NOT multi-consumers safe).\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects) that will be filled.\n * @param n\n * The number of objects to dequeue from the ring to the obj_table,\n * must be strictly positive.\n * @return\n * - 0: Success; objects dequeued.\n * - -ENOENT: Not enough entries in the ring to dequeue; no object is\n * dequeued.\n */\nstatic inline int __attribute__((always_inline))\nrte_ring_sc_dequeue_bulk(struct rte_ring *r, void **obj_table, unsigned n)\n{\n\treturn __rte_ring_sc_do_dequeue(r, obj_table, n, RTE_RING_QUEUE_FIXED);\n}\n\n/**\n * Dequeue several objects from a ring.\n *\n * This function calls the multi-consumers or the single-consumer\n * version, depending on the default behaviour that was specified at\n * ring creation time (see flags).\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects) that will be filled.\n * @param n\n * The number of objects to dequeue from the ring to the obj_table.\n * @return\n * - 0: Success; objects dequeued.\n * - -ENOENT: Not enough entries in the ring to dequeue, no object is\n * dequeued.\n */\nstatic inline int __attribute__((always_inline))\nrte_ring_dequeue_bulk(struct rte_ring *r, void **obj_table, unsigned n)\n{\n\tif (r->cons.sc_dequeue)\n\t\treturn rte_ring_sc_dequeue_bulk(r, obj_table, n);\n\telse\n\t\treturn rte_ring_mc_dequeue_bulk(r, obj_table, n);\n}\n\n/**\n * Dequeue one object from a ring (multi-consumers safe).\n *\n * This function uses a \"compare and set\" instruction to move the\n * consumer index atomically.\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_p\n * A pointer to a void * pointer (object) that will be filled.\n * @return\n * - 0: Success; objects dequeued.\n * - -ENOENT: Not enough entries in the ring to dequeue; no object is\n * dequeued.\n */\nstatic inline int __attribute__((always_inline))\nrte_ring_mc_dequeue(struct rte_ring *r, void **obj_p)\n{\n\treturn rte_ring_mc_dequeue_bulk(r, obj_p, 1);\n}\n\n/**\n * Dequeue one object from a ring (NOT multi-consumers safe).\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_p\n * A pointer to a void * pointer (object) that will be filled.\n * @return\n * - 0: Success; objects dequeued.\n * - -ENOENT: Not enough entries in the ring to dequeue, no object is\n * dequeued.\n */\nstatic inline int __attribute__((always_inline))\nrte_ring_sc_dequeue(struct rte_ring *r, void **obj_p)\n{\n\treturn rte_ring_sc_dequeue_bulk(r, obj_p, 1);\n}\n\n/**\n * Dequeue one object from a ring.\n *\n * This function calls the multi-consumers or the single-consumer\n * version depending on the default behaviour that was specified at\n * ring creation time (see flags).\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_p\n * A pointer to a void * pointer (object) that will be filled.\n * @return\n * - 0: Success, objects dequeued.\n * - -ENOENT: Not enough entries in the ring to dequeue, no object is\n * dequeued.\n */\nstatic inline int __attribute__((always_inline))\nrte_ring_dequeue(struct rte_ring *r, void **obj_p)\n{\n\tif (r->cons.sc_dequeue)\n\t\treturn rte_ring_sc_dequeue(r, obj_p);\n\telse\n\t\treturn rte_ring_mc_dequeue(r, obj_p);\n}\n\n/**\n * Test if a ring is full.\n *\n * @param r\n * A pointer to the ring structure.\n * @return\n * - 1: The ring is full.\n * - 0: The ring is not full.\n */\nstatic inline int\nrte_ring_full(const struct rte_ring *r)\n{\n\tuint32_t prod_tail = r->prod.tail;\n\tuint32_t cons_tail = r->cons.tail;\n\treturn (((cons_tail - prod_tail - 1) & r->prod.mask) == 0);\n}\n\n/**\n * Test if a ring is empty.\n *\n * @param r\n * A pointer to the ring structure.\n * @return\n * - 1: The ring is empty.\n * - 0: The ring is not empty.\n */\nstatic inline int\nrte_ring_empty(const struct rte_ring *r)\n{\n\tuint32_t prod_tail = r->prod.tail;\n\tuint32_t cons_tail = r->cons.tail;\n\treturn !!(cons_tail == prod_tail);\n}\n\n/**\n * Return the number of entries in a ring.\n *\n * @param r\n * A pointer to the ring structure.\n * @return\n * The number of entries in the ring.\n */\nstatic inline unsigned\nrte_ring_count(const struct rte_ring *r)\n{\n\tuint32_t prod_tail = r->prod.tail;\n\tuint32_t cons_tail = r->cons.tail;\n\treturn ((prod_tail - cons_tail) & r->prod.mask);\n}\n\n/**\n * Return the number of free entries in a ring.\n *\n * @param r\n * A pointer to the ring structure.\n * @return\n * The number of free entries in the ring.\n */\nstatic inline unsigned\nrte_ring_free_count(const struct rte_ring *r)\n{\n\tuint32_t prod_tail = r->prod.tail;\n\tuint32_t cons_tail = r->cons.tail;\n\treturn ((cons_tail - prod_tail - 1) & r->prod.mask);\n}\n\n/**\n * Dump the status of all rings on the console\n *\n * @param f\n * A pointer to a file for output\n */\nvoid rte_ring_list_dump(FILE *f);\n\n/**\n * Search a ring from its name\n *\n * @param name\n * The name of the ring.\n * @return\n * The pointer to the ring matching the name, or NULL if not found,\n * with rte_errno set appropriately. Possible rte_errno values include:\n * - ENOENT - required entry not available to return.\n */\nstruct rte_ring *rte_ring_lookup(const char *name);\n\n/**\n * Enqueue several objects on the ring (multi-producers safe).\n *\n * This function uses a \"compare and set\" instruction to move the\n * producer index atomically.\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to add in the ring from the obj_table.\n * @return\n * - n: Actual number of objects enqueued.\n */\nstatic inline unsigned __attribute__((always_inline))\nrte_ring_mp_enqueue_burst(struct rte_ring *r, void * const *obj_table,\n\t\t\t unsigned n)\n{\n\treturn __rte_ring_mp_do_enqueue(r, obj_table, n, RTE_RING_QUEUE_VARIABLE);\n}\n\n/**\n * Enqueue several objects on a ring (NOT multi-producers safe).\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to add in the ring from the obj_table.\n * @return\n * - n: Actual number of objects enqueued.\n */\nstatic inline unsigned __attribute__((always_inline))\nrte_ring_sp_enqueue_burst(struct rte_ring *r, void * const *obj_table,\n\t\t\t unsigned n)\n{\n\treturn __rte_ring_sp_do_enqueue(r, obj_table, n, RTE_RING_QUEUE_VARIABLE);\n}\n\n/**\n * Enqueue several objects on a ring.\n *\n * This function calls the multi-producer or the single-producer\n * version depending on the default behavior that was specified at\n * ring creation time (see flags).\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects).\n * @param n\n * The number of objects to add in the ring from the obj_table.\n * @return\n * - n: Actual number of objects enqueued.\n */\nstatic inline unsigned __attribute__((always_inline))\nrte_ring_enqueue_burst(struct rte_ring *r, void * const *obj_table,\n\t\t unsigned n)\n{\n\tif (r->prod.sp_enqueue)\n\t\treturn rte_ring_sp_enqueue_burst(r, obj_table, n);\n\telse\n\t\treturn rte_ring_mp_enqueue_burst(r, obj_table, n);\n}\n\n/**\n * Dequeue several objects from a ring (multi-consumers safe). When the request\n * objects are more than the available objects, only dequeue the actual number\n * of objects\n *\n * This function uses a \"compare and set\" instruction to move the\n * consumer index atomically.\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects) that will be filled.\n * @param n\n * The number of objects to dequeue from the ring to the obj_table.\n * @return\n * - n: Actual number of objects dequeued, 0 if ring is empty\n */\nstatic inline unsigned __attribute__((always_inline))\nrte_ring_mc_dequeue_burst(struct rte_ring *r, void **obj_table, unsigned n)\n{\n\treturn __rte_ring_mc_do_dequeue(r, obj_table, n, RTE_RING_QUEUE_VARIABLE);\n}\n\n/**\n * Dequeue several objects from a ring (NOT multi-consumers safe).When the\n * request objects are more than the available objects, only dequeue the\n * actual number of objects\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects) that will be filled.\n * @param n\n * The number of objects to dequeue from the ring to the obj_table.\n * @return\n * - n: Actual number of objects dequeued, 0 if ring is empty\n */\nstatic inline unsigned __attribute__((always_inline))\nrte_ring_sc_dequeue_burst(struct rte_ring *r, void **obj_table, unsigned n)\n{\n\treturn __rte_ring_sc_do_dequeue(r, obj_table, n, RTE_RING_QUEUE_VARIABLE);\n}\n\n/**\n * Dequeue multiple objects from a ring up to a maximum number.\n *\n * This function calls the multi-consumers or the single-consumer\n * version, depending on the default behaviour that was specified at\n * ring creation time (see flags).\n *\n * @param r\n * A pointer to the ring structure.\n * @param obj_table\n * A pointer to a table of void * pointers (objects) that will be filled.\n * @param n\n * The number of objects to dequeue from the ring to the obj_table.\n * @return\n * - Number of objects dequeued\n */\nstatic inline unsigned __attribute__((always_inline))\nrte_ring_dequeue_burst(struct rte_ring *r, void **obj_table, unsigned n)\n{\n\tif (r->cons.sc_dequeue)\n\t\treturn rte_ring_sc_dequeue_burst(r, obj_table, n);\n\telse\n\t\treturn rte_ring_mc_dequeue_burst(r, obj_table, n);\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_RING_H_ */\n" }, { "path": "lib/librte_sched/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_sched.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nCFLAGS_rte_red.o := -D_GNU_SOURCE\n\nEXPORT_MAP := rte_sched_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_SCHED) += rte_sched.c rte_red.c rte_approx.c\n\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_SCHED)-include := rte_sched.h rte_bitmap.h rte_sched_common.h rte_red.h rte_approx.h\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_SCHED) += lib/librte_mempool lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_SCHED) += lib/librte_net lib/librte_timer\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_sched/rte_approx.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \"rte_approx.h\"\n\n/*\n * Based on paper \"Approximating Rational Numbers by Fractions\" by Michal\n * Forisek forisek@dcs.fmph.uniba.sk\n *\n * Given a rational number alpha with 0 < alpha < 1 and a precision d, the goal\n * is to find positive integers p, q such that alpha - d < p/q < alpha + d, and\n * q is minimal.\n *\n * http://people.ksp.sk/~misof/publications/2007approx.pdf\n */\n\n/* fraction comparison: compare (a/b) and (c/d) */\nstatic inline uint32_t\nless(uint32_t a, uint32_t b, uint32_t c, uint32_t d)\n{\n\treturn (a*d < b*c);\n}\n\nstatic inline uint32_t\nless_or_equal(uint32_t a, uint32_t b, uint32_t c, uint32_t d)\n{\n\treturn (a*d <= b*c);\n}\n\n/* check whether a/b is a valid approximation */\nstatic inline uint32_t\nmatches(uint32_t a, uint32_t b,\n\tuint32_t alpha_num, uint32_t d_num, uint32_t denum)\n{\n\tif (less_or_equal(a, b, alpha_num - d_num, denum))\n\t\treturn 0;\n\n\tif (less(a ,b, alpha_num + d_num, denum))\n\t\treturn 1;\n\n\treturn 0;\n}\n\nstatic inline void\nfind_exact_solution_left(uint32_t p_a, uint32_t q_a, uint32_t p_b, uint32_t q_b,\n\tuint32_t alpha_num, uint32_t d_num, uint32_t denum, uint32_t *p, uint32_t *q)\n{\n\tuint32_t k_num = denum * p_b - (alpha_num + d_num) * q_b;\n\tuint32_t k_denum = (alpha_num + d_num) * q_a - denum * p_a;\n\tuint32_t k = (k_num / k_denum) + 1;\n\n\t*p = p_b + k * p_a;\n\t*q = q_b + k * q_a;\n}\n\nstatic inline void\nfind_exact_solution_right(uint32_t p_a, uint32_t q_a, uint32_t p_b, uint32_t q_b,\n\tuint32_t alpha_num, uint32_t d_num, uint32_t denum, uint32_t *p, uint32_t *q)\n{\n\tuint32_t k_num = - denum * p_b + (alpha_num - d_num) * q_b;\n\tuint32_t k_denum = - (alpha_num - d_num) * q_a + denum * p_a;\n\tuint32_t k = (k_num / k_denum) + 1;\n\n\t*p = p_b + k * p_a;\n\t*q = q_b + k * q_a;\n}\n\nstatic int\nfind_best_rational_approximation(uint32_t alpha_num, uint32_t d_num, uint32_t denum, uint32_t *p, uint32_t *q)\n{\n\tuint32_t p_a, q_a, p_b, q_b;\n\n\t/* check assumptions on the inputs */\n\tif (!((0 < d_num) && (d_num < alpha_num) && (alpha_num < denum) && (d_num + alpha_num < denum))) {\n\t\treturn -1;\n\t}\n\n\t/* set initial bounds for the search */\n\tp_a = 0;\n\tq_a = 1;\n\tp_b = 1;\n\tq_b = 1;\n\n\twhile (1) {\n\t\tuint32_t new_p_a, new_q_a, new_p_b, new_q_b;\n\t\tuint32_t x_num, x_denum, x;\n\t\tint aa, bb;\n\n\t\t/* compute the number of steps to the left */\n\t\tx_num = denum * p_b - alpha_num * q_b;\n\t\tx_denum = - denum * p_a + alpha_num * q_a;\n\t\tx = (x_num + x_denum - 1) / x_denum; /* x = ceil(x_num / x_denum) */\n\n\t\t/* check whether we have a valid approximation */\n\t\taa = matches(p_b + x * p_a, q_b + x * q_a, alpha_num, d_num, denum);\n\t\tbb = matches(p_b + (x-1) * p_a, q_b + (x - 1) * q_a, alpha_num, d_num, denum);\n\t\tif (aa || bb) {\n\t\t\tfind_exact_solution_left(p_a, q_a, p_b, q_b, alpha_num, d_num, denum, p, q);\n\t\t\treturn 0;\n\t\t}\n\n\t\t/* update the interval */\n\t\tnew_p_a = p_b + (x - 1) * p_a ;\n\t\tnew_q_a = q_b + (x - 1) * q_a;\n\t\tnew_p_b = p_b + x * p_a ;\n\t\tnew_q_b = q_b + x * q_a;\n\n\t\tp_a = new_p_a ;\n\t\tq_a = new_q_a;\n\t\tp_b = new_p_b ;\n\t\tq_b = new_q_b;\n\n\t\t/* compute the number of steps to the right */\n\t\tx_num = alpha_num * q_b - denum * p_b;\n\t\tx_denum = - alpha_num * q_a + denum * p_a;\n\t\tx = (x_num + x_denum - 1) / x_denum; /* x = ceil(x_num / x_denum) */\n\n\t\t/* check whether we have a valid approximation */\n\t\taa = matches(p_b + x * p_a, q_b + x * q_a, alpha_num, d_num, denum);\n\t\tbb = matches(p_b + (x - 1) * p_a, q_b + (x - 1) * q_a, alpha_num, d_num, denum);\n\t\tif (aa || bb) {\n\t\t\tfind_exact_solution_right(p_a, q_a, p_b, q_b, alpha_num, d_num, denum, p, q);\n\t\t\treturn 0;\n\t\t }\n\n\t\t/* update the interval */\n\t\tnew_p_a = p_b + (x - 1) * p_a;\n\t\tnew_q_a = q_b + (x - 1) * q_a;\n\t\tnew_p_b = p_b + x * p_a;\n\t\tnew_q_b = q_b + x * q_a;\n\n\t\tp_a = new_p_a;\n\t\tq_a = new_q_a;\n\t\tp_b = new_p_b;\n\t\tq_b = new_q_b;\n\t}\n}\n\nint rte_approx(double alpha, double d, uint32_t *p, uint32_t *q)\n{\n\tuint32_t alpha_num, d_num, denum;\n\n\t/* Check input arguments */\n\tif (!((0.0 < d) && (d < alpha) && (alpha < 1.0))) {\n\t\treturn -1;\n\t}\n\n\tif ((p == NULL) || (q == NULL)) {\n\t\treturn -2;\n\t}\n\n\t/* Compute alpha_num, d_num and denum */\n\tdenum = 1;\n\twhile (d < 1) {\n\t\talpha *= 10;\n\t\td *= 10;\n\t\tdenum *= 10;\n\t}\n\talpha_num = (uint32_t) alpha;\n\td_num = (uint32_t) d;\n\n\t/* Perform approximation */\n\treturn find_best_rational_approximation(alpha_num, d_num, denum, p, q);\n}\n" }, { "path": "lib/librte_sched/rte_approx.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_APPROX_H__\n#define __INCLUDE_RTE_APPROX_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Rational Approximation\n *\n * Given a rational number alpha with 0 < alpha < 1 and a precision d, the goal\n * is to find positive integers p, q such that alpha - d < p/q < alpha + d, and\n * q is minimal.\n *\n ***/\n\n#include \n\n/**\n * Find best rational approximation\n *\n * @param alpha\n * Rational number to approximate\n * @param d\n * Precision for the rational approximation\n * @param p\n * Pointer to pre-allocated space where the numerator of the rational\n * approximation will be stored when operation is successful\n * @param q\n * Pointer to pre-allocated space where the denominator of the rational\n * approximation will be stored when operation is successful\n * @return\n * 0 upon success, error code otherwise\n */\nint rte_approx(double alpha, double d, uint32_t *p, uint32_t *q);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __INCLUDE_RTE_APPROX_H__ */\n" }, { "path": "lib/librte_sched/rte_bitmap.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_BITMAP_H__\n#define __INCLUDE_RTE_BITMAP_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Bitmap\n *\n * The bitmap component provides a mechanism to manage large arrays of bits\n * through bit get/set/clear and bit array scan operations.\n *\n * The bitmap scan operation is optimized for 64-bit CPUs using 64-byte cache\n * lines. The bitmap is hierarchically organized using two arrays (array1 and\n * array2), with each bit in array1 being associated with a full cache line\n * (512 bits) of bitmap bits, which are stored in array2: the bit in array1 is\n * set only when there is at least one bit set within its associated array2\n * bits, otherwise the bit in array1 is cleared. The read and write operations\n * for array1 and array2 are always done in slabs of 64 bits.\n *\n * This bitmap is not thread safe. For lock free operation on a specific bitmap\n * instance, a single writer thread performing bit set/clear operations is\n * allowed, only the writer thread can do bitmap scan operations, while there\n * can be several reader threads performing bit get operations in parallel with\n * the writer thread. When the use of locking primitives is acceptable, the\n * serialization of the bit set/clear and bitmap scan operations needs to be\n * enforced by the caller, while the bit get operation does not require locking\n * the bitmap.\n *\n ***/\n\n#include \n#include \n#include \n#include \n#include \n\n#ifndef RTE_BITMAP_OPTIMIZATIONS\n#define RTE_BITMAP_OPTIMIZATIONS\t\t 1\n#endif\n#if RTE_BITMAP_OPTIMIZATIONS\n#include \n#endif\n\n/* Slab */\n#define RTE_BITMAP_SLAB_BIT_SIZE 64\n#define RTE_BITMAP_SLAB_BIT_SIZE_LOG2 6\n#define RTE_BITMAP_SLAB_BIT_MASK (RTE_BITMAP_SLAB_BIT_SIZE - 1)\n\n/* Cache line (CL) */\n#define RTE_BITMAP_CL_BIT_SIZE (RTE_CACHE_LINE_SIZE * 8)\n#define RTE_BITMAP_CL_BIT_SIZE_LOG2 9\n#define RTE_BITMAP_CL_BIT_MASK (RTE_BITMAP_CL_BIT_SIZE - 1)\n\n#define RTE_BITMAP_CL_SLAB_SIZE (RTE_BITMAP_CL_BIT_SIZE / RTE_BITMAP_SLAB_BIT_SIZE)\n#define RTE_BITMAP_CL_SLAB_SIZE_LOG2 3\n#define RTE_BITMAP_CL_SLAB_MASK (RTE_BITMAP_CL_SLAB_SIZE - 1)\n\n/** Bitmap data structure */\nstruct rte_bitmap {\n\t/* Context for array1 and array2 */\n\tuint64_t *array1; /**< Bitmap array1 */\n\tuint64_t *array2; /**< Bitmap array2 */\n\tuint32_t array1_size; /**< Number of 64-bit slabs in array1 that are actually used */\n\tuint32_t array2_size; /**< Number of 64-bit slabs in array2 */\n\n\t/* Context for the \"scan next\" operation */\n\tuint32_t index1; /**< Bitmap scan: Index of current array1 slab */\n\tuint32_t offset1; /**< Bitmap scan: Offset of current bit within current array1 slab */\n\tuint32_t index2; /**< Bitmap scan: Index of current array2 slab */\n\tuint32_t go2; /**< Bitmap scan: Go/stop condition for current array2 cache line */\n\n\t/* Storage space for array1 and array2 */\n\tuint8_t memory[0];\n};\n\nstatic inline void\n__rte_bitmap_index1_inc(struct rte_bitmap *bmp)\n{\n\tbmp->index1 = (bmp->index1 + 1) & (bmp->array1_size - 1);\n}\n\nstatic inline uint64_t\n__rte_bitmap_mask1_get(struct rte_bitmap *bmp)\n{\n\treturn ((~1lu) << bmp->offset1);\n}\n\nstatic inline void\n__rte_bitmap_index2_set(struct rte_bitmap *bmp)\n{\n\tbmp->index2 = (((bmp->index1 << RTE_BITMAP_SLAB_BIT_SIZE_LOG2) + bmp->offset1) << RTE_BITMAP_CL_SLAB_SIZE_LOG2);\n}\n\n#if RTE_BITMAP_OPTIMIZATIONS\n\nstatic inline int\nrte_bsf64(uint64_t slab, uint32_t *pos)\n{\n\tif (likely(slab == 0)) {\n\t\treturn 0;\n\t}\n\n\t*pos = __builtin_ctzll(slab);\n\treturn 1;\n}\n\n#else\n\nstatic inline int\nrte_bsf64(uint64_t slab, uint32_t *pos)\n{\n\tuint64_t mask;\n\tuint32_t i;\n\n\tif (likely(slab == 0)) {\n\t\treturn 0;\n\t}\n\n\tfor (i = 0, mask = 1; i < RTE_BITMAP_SLAB_BIT_SIZE; i ++, mask <<= 1) {\n\t\tif (unlikely(slab & mask)) {\n\t\t\t*pos = i;\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n#endif\n\nstatic inline uint32_t\n__rte_bitmap_get_memory_footprint(uint32_t n_bits,\n\tuint32_t *array1_byte_offset, uint32_t *array1_slabs,\n\tuint32_t *array2_byte_offset, uint32_t *array2_slabs)\n{\n\tuint32_t n_slabs_context, n_slabs_array1, n_cache_lines_context_and_array1;\n\tuint32_t n_cache_lines_array2;\n\tuint32_t n_bytes_total;\n\n\tn_cache_lines_array2 = (n_bits + RTE_BITMAP_CL_BIT_SIZE - 1) / RTE_BITMAP_CL_BIT_SIZE;\n\tn_slabs_array1 = (n_cache_lines_array2 + RTE_BITMAP_SLAB_BIT_SIZE - 1) / RTE_BITMAP_SLAB_BIT_SIZE;\n\tn_slabs_array1 = rte_align32pow2(n_slabs_array1);\n\tn_slabs_context = (sizeof(struct rte_bitmap) + (RTE_BITMAP_SLAB_BIT_SIZE / 8) - 1) / (RTE_BITMAP_SLAB_BIT_SIZE / 8);\n\tn_cache_lines_context_and_array1 = (n_slabs_context + n_slabs_array1 + RTE_BITMAP_CL_SLAB_SIZE - 1) / RTE_BITMAP_CL_SLAB_SIZE;\n\tn_bytes_total = (n_cache_lines_context_and_array1 + n_cache_lines_array2) * RTE_CACHE_LINE_SIZE;\n\n\tif (array1_byte_offset) {\n\t\t*array1_byte_offset = n_slabs_context * (RTE_BITMAP_SLAB_BIT_SIZE / 8);\n\t}\n\tif (array1_slabs) {\n\t\t*array1_slabs = n_slabs_array1;\n\t}\n\tif (array2_byte_offset) {\n\t\t*array2_byte_offset = n_cache_lines_context_and_array1 * RTE_CACHE_LINE_SIZE;\n\t}\n\tif (array2_slabs) {\n\t\t*array2_slabs = n_cache_lines_array2 * RTE_BITMAP_CL_SLAB_SIZE;\n\t}\n\n\treturn n_bytes_total;\n}\n\nstatic inline void\n__rte_bitmap_scan_init(struct rte_bitmap *bmp)\n{\n\tbmp->index1 = bmp->array1_size - 1;\n\tbmp->offset1 = RTE_BITMAP_SLAB_BIT_SIZE - 1;\n\t__rte_bitmap_index2_set(bmp);\n\tbmp->index2 += RTE_BITMAP_CL_SLAB_SIZE;\n\n\tbmp->go2 = 0;\n}\n\n/**\n * Bitmap memory footprint calculation\n *\n * @param n_bits\n * Number of bits in the bitmap\n * @return\n * Bitmap memory footprint measured in bytes on success, 0 on error\n */\nstatic inline uint32_t\nrte_bitmap_get_memory_footprint(uint32_t n_bits) {\n\t/* Check input arguments */\n\tif (n_bits == 0) {\n\t\treturn 0;\n\t}\n\n\treturn __rte_bitmap_get_memory_footprint(n_bits, NULL, NULL, NULL, NULL);\n}\n\n/**\n * Bitmap initialization\n *\n * @param mem_size\n * Minimum expected size of bitmap.\n * @param mem\n * Base address of array1 and array2.\n * @param n_bits\n * Number of pre-allocated bits in array2. Must be non-zero and multiple of 512.\n * @return\n * Handle to bitmap instance.\n */\nstatic inline struct rte_bitmap *\nrte_bitmap_init(uint32_t n_bits, uint8_t *mem, uint32_t mem_size)\n{\n\tstruct rte_bitmap *bmp;\n\tuint32_t array1_byte_offset, array1_slabs, array2_byte_offset, array2_slabs;\n\tuint32_t size;\n\n\t/* Check input arguments */\n\tif (n_bits == 0) {\n\t\treturn NULL;\n\t}\n\n\tif ((mem == NULL) || (((uintptr_t) mem) & RTE_CACHE_LINE_MASK)) {\n\t\treturn NULL;\n\t}\n\n\tsize = __rte_bitmap_get_memory_footprint(n_bits,\n\t\t&array1_byte_offset, &array1_slabs,\n\t\t&array2_byte_offset, &array2_slabs);\n\tif (size < mem_size) {\n\t\treturn NULL;\n\t}\n\n\t/* Setup bitmap */\n\tmemset(mem, 0, size);\n\tbmp = (struct rte_bitmap *) mem;\n\n\tbmp->array1 = (uint64_t *) &mem[array1_byte_offset];\n\tbmp->array1_size = array1_slabs;\n\tbmp->array2 = (uint64_t *) &mem[array2_byte_offset];\n\tbmp->array2_size = array2_slabs;\n\n\t__rte_bitmap_scan_init(bmp);\n\n\treturn bmp;\n}\n\n/**\n * Bitmap free\n *\n * @param bmp\n * Handle to bitmap instance\n * @return\n * 0 upon success, error code otherwise\n */\nstatic inline int\nrte_bitmap_free(struct rte_bitmap *bmp)\n{\n\t/* Check input arguments */\n\tif (bmp == NULL) {\n\t\treturn -1;\n\t}\n\n\treturn 0;\n}\n\n/**\n * Bitmap reset\n *\n * @param bmp\n * Handle to bitmap instance\n */\nstatic inline void\nrte_bitmap_reset(struct rte_bitmap *bmp)\n{\n\tmemset(bmp->array1, 0, bmp->array1_size * sizeof(uint64_t));\n\tmemset(bmp->array2, 0, bmp->array2_size * sizeof(uint64_t));\n\t__rte_bitmap_scan_init(bmp);\n}\n\n/**\n * Bitmap location prefetch into CPU L1 cache\n *\n * @param bmp\n * Handle to bitmap instance\n * @param pos\n * Bit position\n * @return\n * 0 upon success, error code otherwise\n */\nstatic inline void\nrte_bitmap_prefetch0(struct rte_bitmap *bmp, uint32_t pos)\n{\n\tuint64_t *slab2;\n\tuint32_t index2;\n\n\tindex2 = pos >> RTE_BITMAP_SLAB_BIT_SIZE_LOG2;\n\tslab2 = bmp->array2 + index2;\n\trte_prefetch0((void *) slab2);\n}\n\n/**\n * Bitmap bit get\n *\n * @param bmp\n * Handle to bitmap instance\n * @param pos\n * Bit position\n * @return\n * 0 when bit is cleared, non-zero when bit is set\n */\nstatic inline uint64_t\nrte_bitmap_get(struct rte_bitmap *bmp, uint32_t pos)\n{\n\tuint64_t *slab2;\n\tuint32_t index2, offset2;\n\n\tindex2 = pos >> RTE_BITMAP_SLAB_BIT_SIZE_LOG2;\n\toffset2 = pos & RTE_BITMAP_SLAB_BIT_MASK;\n\tslab2 = bmp->array2 + index2;\n\treturn ((*slab2) & (1lu << offset2));\n}\n\n/**\n * Bitmap bit set\n *\n * @param bmp\n * Handle to bitmap instance\n * @param pos\n * Bit position\n */\nstatic inline void\nrte_bitmap_set(struct rte_bitmap *bmp, uint32_t pos)\n{\n\tuint64_t *slab1, *slab2;\n\tuint32_t index1, index2, offset1, offset2;\n\n\t/* Set bit in array2 slab and set bit in array1 slab */\n\tindex2 = pos >> RTE_BITMAP_SLAB_BIT_SIZE_LOG2;\n\toffset2 = pos & RTE_BITMAP_SLAB_BIT_MASK;\n\tindex1 = pos >> (RTE_BITMAP_SLAB_BIT_SIZE_LOG2 + RTE_BITMAP_CL_BIT_SIZE_LOG2);\n\toffset1 = (pos >> RTE_BITMAP_CL_BIT_SIZE_LOG2) & RTE_BITMAP_SLAB_BIT_MASK;\n\tslab2 = bmp->array2 + index2;\n\tslab1 = bmp->array1 + index1;\n\n\t*slab2 |= 1lu << offset2;\n\t*slab1 |= 1lu << offset1;\n}\n\n/**\n * Bitmap slab set\n *\n * @param bmp\n * Handle to bitmap instance\n * @param pos\n * Bit position identifying the array2 slab\n * @param slab\n * Value to be assigned to the 64-bit slab in array2\n */\nstatic inline void\nrte_bitmap_set_slab(struct rte_bitmap *bmp, uint32_t pos, uint64_t slab)\n{\n\tuint64_t *slab1, *slab2;\n\tuint32_t index1, index2, offset1;\n\n\t/* Set bits in array2 slab and set bit in array1 slab */\n\tindex2 = pos >> RTE_BITMAP_SLAB_BIT_SIZE_LOG2;\n\tindex1 = pos >> (RTE_BITMAP_SLAB_BIT_SIZE_LOG2 + RTE_BITMAP_CL_BIT_SIZE_LOG2);\n\toffset1 = (pos >> RTE_BITMAP_CL_BIT_SIZE_LOG2) & RTE_BITMAP_SLAB_BIT_MASK;\n\tslab2 = bmp->array2 + index2;\n\tslab1 = bmp->array1 + index1;\n\n\t*slab2 |= slab;\n\t*slab1 |= 1lu << offset1;\n}\n\nstatic inline uint64_t\n__rte_bitmap_line_not_empty(uint64_t *slab2)\n{\n\tuint64_t v1, v2, v3, v4;\n\n\tv1 = slab2[0] | slab2[1];\n\tv2 = slab2[2] | slab2[3];\n\tv3 = slab2[4] | slab2[5];\n\tv4 = slab2[6] | slab2[7];\n\tv1 |= v2;\n\tv3 |= v4;\n\n\treturn (v1 | v3);\n}\n\n/**\n * Bitmap bit clear\n *\n * @param bmp\n * Handle to bitmap instance\n * @param pos\n * Bit position\n */\nstatic inline void\nrte_bitmap_clear(struct rte_bitmap *bmp, uint32_t pos)\n{\n\tuint64_t *slab1, *slab2;\n\tuint32_t index1, index2, offset1, offset2;\n\n\t/* Clear bit in array2 slab */\n\tindex2 = pos >> RTE_BITMAP_SLAB_BIT_SIZE_LOG2;\n\toffset2 = pos & RTE_BITMAP_SLAB_BIT_MASK;\n\tslab2 = bmp->array2 + index2;\n\n\t/* Return if array2 slab is not all-zeros */\n\t*slab2 &= ~(1lu << offset2);\n\tif (*slab2){\n\t\treturn;\n\t}\n\n\t/* Check the entire cache line of array2 for all-zeros */\n\tindex2 &= ~ RTE_BITMAP_CL_SLAB_MASK;\n\tslab2 = bmp->array2 + index2;\n\tif (__rte_bitmap_line_not_empty(slab2)) {\n\t\treturn;\n\t}\n\n\t/* The array2 cache line is all-zeros, so clear bit in array1 slab */\n\tindex1 = pos >> (RTE_BITMAP_SLAB_BIT_SIZE_LOG2 + RTE_BITMAP_CL_BIT_SIZE_LOG2);\n\toffset1 = (pos >> RTE_BITMAP_CL_BIT_SIZE_LOG2) & RTE_BITMAP_SLAB_BIT_MASK;\n\tslab1 = bmp->array1 + index1;\n\t*slab1 &= ~(1lu << offset1);\n\n\treturn;\n}\n\nstatic inline int\n__rte_bitmap_scan_search(struct rte_bitmap *bmp)\n{\n\tuint64_t value1;\n\tuint32_t i;\n\n\t/* Check current array1 slab */\n\tvalue1 = bmp->array1[bmp->index1];\n\tvalue1 &= __rte_bitmap_mask1_get(bmp);\n\n\tif (rte_bsf64(value1, &bmp->offset1)) {\n\t\treturn 1;\n\t}\n\n\t__rte_bitmap_index1_inc(bmp);\n\tbmp->offset1 = 0;\n\n\t/* Look for another array1 slab */\n\tfor (i = 0; i < bmp->array1_size; i ++, __rte_bitmap_index1_inc(bmp)) {\n\t\tvalue1 = bmp->array1[bmp->index1];\n\n\t\tif (rte_bsf64(value1, &bmp->offset1)) {\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic inline void\n__rte_bitmap_scan_read_init(struct rte_bitmap *bmp)\n{\n\t__rte_bitmap_index2_set(bmp);\n\tbmp->go2 = 1;\n\trte_prefetch1((void *)(bmp->array2 + bmp->index2 + 8));\n}\n\nstatic inline int\n__rte_bitmap_scan_read(struct rte_bitmap *bmp, uint32_t *pos, uint64_t *slab)\n{\n\tuint64_t *slab2;\n\n\tslab2 = bmp->array2 + bmp->index2;\n\tfor ( ; bmp->go2 ; bmp->index2 ++, slab2 ++, bmp->go2 = bmp->index2 & RTE_BITMAP_CL_SLAB_MASK) {\n\t\tif (*slab2) {\n\t\t\t*pos = bmp->index2 << RTE_BITMAP_SLAB_BIT_SIZE_LOG2;\n\t\t\t*slab = *slab2;\n\n\t\t\tbmp->index2 ++;\n\t\t\tslab2 ++;\n\t\t\tbmp->go2 = bmp->index2 & RTE_BITMAP_CL_SLAB_MASK;\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n/**\n * Bitmap scan (with automatic wrap-around)\n *\n * @param bmp\n * Handle to bitmap instance\n * @param pos\n * When function call returns 1, pos contains the position of the next set\n * bit, otherwise not modified\n * @param slab\n * When function call returns 1, slab contains the value of the entire 64-bit\n * slab where the bit indicated by pos is located. Slabs are always 64-bit\n * aligned, so the position of the first bit of the slab (this bit is not\n * necessarily set) is pos / 64. Once a slab has been returned by the bitmap\n * scan operation, the internal pointers of the bitmap are updated to point\n * after this slab, so the same slab will not be returned again if it\n * contains more than one bit which is set. When function call returns 0,\n * slab is not modified.\n * @return\n * 0 if there is no bit set in the bitmap, 1 otherwise\n */\nstatic inline int\nrte_bitmap_scan(struct rte_bitmap *bmp, uint32_t *pos, uint64_t *slab)\n{\n\t/* Return data from current array2 line if available */\n\tif (__rte_bitmap_scan_read(bmp, pos, slab)) {\n\t\treturn 1;\n\t}\n\n\t/* Look for non-empty array2 line */\n\tif (__rte_bitmap_scan_search(bmp)) {\n\t\t__rte_bitmap_scan_read_init(bmp);\n\t\t__rte_bitmap_scan_read(bmp, pos, slab);\n\t\treturn 1;\n\t}\n\n\t/* Empty bitmap */\n\treturn 0;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __INCLUDE_RTE_BITMAP_H__ */\n" }, { "path": "lib/librte_sched/rte_red.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \"rte_red.h\"\n#include \n#include \n\n#ifdef __INTEL_COMPILER\n#pragma warning(disable:2259) /* conversion may lose significant bits */\n#endif\n\nstatic int rte_red_init_done = 0; /**< Flag to indicate that global initialisation is done */\nuint32_t rte_red_rand_val = 0; /**< Random value cache */\nuint32_t rte_red_rand_seed = 0; /**< Seed for random number generation */\n\n/**\n * table[i] = log2(1-Wq) * Scale * -1\n * Wq = 1/(2^i)\n */\nuint16_t rte_red_log2_1_minus_Wq[RTE_RED_WQ_LOG2_NUM];\n\n/**\n * table[i] = 2^(i/16) * Scale\n */\nuint16_t rte_red_pow2_frac_inv[16];\n\n/**\n * @brief Initialize tables used to compute average\n * queue size when queue is empty.\n */\nstatic void\n__rte_red_init_tables(void)\n{\n\tuint32_t i = 0;\n\tdouble scale = 0.0;\n\tdouble table_size = 0.0;\n\n\tscale = (double)(1 << RTE_RED_SCALING);\n\ttable_size = (double)(RTE_DIM(rte_red_pow2_frac_inv));\n\n\tfor (i = 0; i < RTE_DIM(rte_red_pow2_frac_inv); i++) {\n\t\tdouble m = (double)i;\n\n\t\trte_red_pow2_frac_inv[i] = (uint16_t) round(scale / pow(2, m / table_size));\n\t}\n\n\tscale = 1024.0;\n\n\tRTE_RED_ASSERT(RTE_RED_WQ_LOG2_NUM == RTE_DIM(rte_red_log2_1_minus_Wq));\n\n\tfor (i = RTE_RED_WQ_LOG2_MIN; i <= RTE_RED_WQ_LOG2_MAX; i++) {\n\t\tdouble n = (double)i;\n\t\tdouble Wq = pow(2, -n);\n\t\tuint32_t index = i - RTE_RED_WQ_LOG2_MIN;\n\n\t\trte_red_log2_1_minus_Wq[index] = (uint16_t) round(-1.0 * scale * log2(1.0 - Wq));\n\t\t/**\n\t\t* Table entry of zero, corresponds to a Wq of zero\n\t\t* which is not valid (avg would remain constant no\n\t\t* matter how long the queue is empty). So we have\n\t\t* to check for zero and round up to one.\n\t\t*/\n\t\tif (rte_red_log2_1_minus_Wq[index] == 0) {\n\t\t\trte_red_log2_1_minus_Wq[index] = 1;\n\t\t}\n\t}\n}\n\nint\nrte_red_rt_data_init(struct rte_red *red)\n{\n\tif (red == NULL)\n\t\treturn -1;\n\n\tred->avg = 0;\n\tred->count = 0;\n\tred->q_time = 0;\n\treturn 0;\n}\n\nint\nrte_red_config_init(struct rte_red_config *red_cfg,\n\tconst uint16_t wq_log2,\n\tconst uint16_t min_th,\n\tconst uint16_t max_th,\n\tconst uint16_t maxp_inv)\n{\n\tif (red_cfg == NULL) {\n\t\treturn -1;\n\t}\n\tif (max_th > RTE_RED_MAX_TH_MAX) {\n\t\treturn -2;\n\t}\n\tif (min_th >= max_th) {\n\t\treturn -3;\n\t}\n\tif (wq_log2 > RTE_RED_WQ_LOG2_MAX) {\n\t\treturn -4;\n\t}\n\tif (wq_log2 < RTE_RED_WQ_LOG2_MIN) {\n\t\treturn -5;\n\t}\n\tif (maxp_inv < RTE_RED_MAXP_INV_MIN) {\n\t\treturn -6;\n\t}\n\tif (maxp_inv > RTE_RED_MAXP_INV_MAX) {\n\t\treturn -7;\n\t}\n\n\t/**\n\t * Initialize the RED module if not already done\n\t */\n\tif (!rte_red_init_done) {\n\t\trte_red_rand_seed = rte_rand();\n\t\trte_red_rand_val = rte_fast_rand();\n\t\t__rte_red_init_tables();\n\t\trte_red_init_done = 1;\n\t}\n\n\tred_cfg->min_th = ((uint32_t) min_th) << (wq_log2 + RTE_RED_SCALING);\n\tred_cfg->max_th = ((uint32_t) max_th) << (wq_log2 + RTE_RED_SCALING);\n\tred_cfg->pa_const = (2 * (max_th - min_th) * maxp_inv) << RTE_RED_SCALING;\n\tred_cfg->maxp_inv = maxp_inv;\n\tred_cfg->wq_log2 = wq_log2;\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_sched/rte_red.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __RTE_RED_H_INCLUDED__\n#define __RTE_RED_H_INCLUDED__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Random Early Detection (RED)\n *\n *\n ***/\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#define RTE_RED_SCALING 10 /**< Fraction size for fixed-point */\n#define RTE_RED_S (1 << 22) /**< Packet size multiplied by number of leaf queues */\n#define RTE_RED_MAX_TH_MAX 1023 /**< Max threshold limit in fixed point format */\n#define RTE_RED_WQ_LOG2_MIN 1 /**< Min inverse filter weight value */\n#define RTE_RED_WQ_LOG2_MAX 12 /**< Max inverse filter weight value */\n#define RTE_RED_MAXP_INV_MIN 1 /**< Min inverse mark probability value */\n#define RTE_RED_MAXP_INV_MAX 255 /**< Max inverse mark probability value */\n#define RTE_RED_2POW16 (1<<16) /**< 2 power 16 */\n#define RTE_RED_INT16_NBITS (sizeof(uint16_t) * CHAR_BIT)\n#define RTE_RED_WQ_LOG2_NUM (RTE_RED_WQ_LOG2_MAX - RTE_RED_WQ_LOG2_MIN + 1)\n\n#ifdef RTE_RED_DEBUG\n\n#define RTE_RED_ASSERT(exp) \\\nif (!(exp)) { \\\n\trte_panic(\"line%d\\tassert \\\"\" #exp \"\\\" failed\\n\", __LINE__); \\\n}\n\n#else\n\n#define RTE_RED_ASSERT(exp) do { } while(0)\n\n#endif /* RTE_RED_DEBUG */\n\n/**\n * Externs\n *\n */\nextern uint32_t rte_red_rand_val;\nextern uint32_t rte_red_rand_seed;\nextern uint16_t rte_red_log2_1_minus_Wq[RTE_RED_WQ_LOG2_NUM];\nextern uint16_t rte_red_pow2_frac_inv[16];\n\n/**\n * RED configuration parameters passed by user\n *\n */\nstruct rte_red_params {\n\tuint16_t min_th; /**< Minimum threshold for queue (max_th) */\n\tuint16_t max_th; /**< Maximum threshold for queue (max_th) */\n\tuint16_t maxp_inv; /**< Inverse of packet marking probability maximum value (maxp = 1 / maxp_inv) */\n\tuint16_t wq_log2; /**< Negated log2 of queue weight (wq = 1 / (2 ^ wq_log2)) */\n};\n\n/**\n * RED configuration parameters\n */\nstruct rte_red_config {\n\tuint32_t min_th; /**< min_th scaled in fixed-point format */\n\tuint32_t max_th; /**< max_th scaled in fixed-point format */\n\tuint32_t pa_const; /**< Precomputed constant value used for pa calculation (scaled in fixed-point format) */\n\tuint8_t maxp_inv; /**< maxp_inv */\n\tuint8_t wq_log2; /**< wq_log2 */\n};\n\n/**\n * RED run-time data\n */\nstruct rte_red {\n\tuint32_t avg; /**< Average queue size (avg), scaled in fixed-point format */\n\tuint32_t count; /**< Number of packets since last marked packet (count) */\n\tuint64_t q_time; /**< Start of the queue idle time (q_time) */\n};\n\n/**\n * @brief Initialises run-time data\n *\n * @param red [in,out] data pointer to RED runtime data\n *\n * @return Operation status\n * @retval 0 success\n * @retval !0 error\n */\nint\nrte_red_rt_data_init(struct rte_red *red);\n\n/**\n * @brief Configures a single RED configuration parameter structure.\n *\n * @param red_cfg [in,out] config pointer to a RED configuration parameter structure\n * @param wq_log2 [in] log2 of the filter weight, valid range is:\n * RTE_RED_WQ_LOG2_MIN <= wq_log2 <= RTE_RED_WQ_LOG2_MAX\n * @param min_th [in] queue minimum threshold in number of packets\n * @param max_th [in] queue maximum threshold in number of packets\n * @param maxp_inv [in] inverse maximum mark probability\n *\n * @return Operation status\n * @retval 0 success\n * @retval !0 error\n */\nint\nrte_red_config_init(struct rte_red_config *red_cfg,\n\tconst uint16_t wq_log2,\n\tconst uint16_t min_th,\n\tconst uint16_t max_th,\n\tconst uint16_t maxp_inv);\n\n/**\n * @brief Generate random number for RED\n *\n * Implemenetation based on:\n * http://software.intel.com/en-us/articles/fast-random-number-generator-on-the-intel-pentiumr-4-processor/\n *\n * 10 bit shift has been found through empirical tests (was 16).\n *\n * @return Random number between 0 and (2^22 - 1)\n */\nstatic inline uint32_t\nrte_fast_rand(void)\n{\n\trte_red_rand_seed = (214013 * rte_red_rand_seed) + 2531011;\n\treturn (rte_red_rand_seed >> 10);\n}\n\n/**\n * @brief calculate factor to scale average queue size when queue\n * becomes empty\n *\n * @param wq_log2 [in] where EWMA filter weight wq = 1/(2 ^ wq_log2)\n * @param m [in] exponent in the computed value (1 - wq) ^ m\n *\n * @return computed value\n * @retval ((1 - wq) ^ m) scaled in fixed-point format\n */\nstatic inline uint16_t\n__rte_red_calc_qempty_factor(uint8_t wq_log2, uint16_t m)\n{\n\tuint32_t n = 0;\n\tuint32_t f = 0;\n\n\t/**\n\t * Basic math tells us that:\n\t * a^b = 2^(b * log2(a) )\n\t *\n\t * in our case:\n\t * a = (1-Wq)\n\t * b = m\n\t * Wq = 1/ (2^log2n)\n\t *\n\t * So we are computing this equation:\n\t * factor = 2 ^ ( m * log2(1-Wq))\n\t *\n\t * First we are computing:\n\t * n = m * log2(1-Wq)\n\t *\n\t * To avoid dealing with signed numbers log2 values are positive\n\t * but they should be negative because (1-Wq) is always < 1.\n\t * Contents of log2 table values are also scaled for precision.\n\t */\n\n\tn = m * rte_red_log2_1_minus_Wq[wq_log2 - RTE_RED_WQ_LOG2_MIN];\n\n\t/**\n\t * The tricky part is computing 2^n, for this I split n into\n\t * integer part and fraction part.\n\t * f - is fraction part of n\n\t * n - is integer part of original n\n\t *\n\t * Now using basic math we compute 2^n:\n\t * 2^(f+n) = 2^f * 2^n\n\t * 2^f - we use lookup table\n\t * 2^n - can be replaced with bit shift right oeprations\n\t */\n\n\tf = (n >> 6) & 0xf;\n\tn >>= 10;\n\n\tif (n < RTE_RED_SCALING)\n\t\treturn (uint16_t) ((rte_red_pow2_frac_inv[f] + (1 << (n - 1))) >> n);\n\n\treturn 0;\n}\n\n/**\n * @brief Updates queue average in condition when queue is empty\n *\n * Note: packet is never dropped in this particular case.\n *\n * @param red_cfg [in] config pointer to a RED configuration parameter structure\n * @param red [in,out] data pointer to RED runtime data\n * @param time [in] current time stamp\n *\n * @return Operation status\n * @retval 0 enqueue the packet\n * @retval 1 drop the packet based on max threshold criterion\n * @retval 2 drop the packet based on mark probability criterion\n */\nstatic inline int\nrte_red_enqueue_empty(const struct rte_red_config *red_cfg,\n\tstruct rte_red *red,\n\tconst uint64_t time)\n{\n\tuint64_t time_diff = 0, m = 0;\n\n\tRTE_RED_ASSERT(red_cfg != NULL);\n\tRTE_RED_ASSERT(red != NULL);\n\n\tred->count ++;\n\n\t/**\n\t * We compute avg but we don't compare avg against\n\t * min_th or max_th, nor calculate drop probability\n\t */\n\ttime_diff = time - red->q_time;\n\n\t/**\n\t * m is the number of packets that might have arrived while the queue was empty.\n\t * In this case we have time stamps provided by scheduler in byte units (bytes\n\t * transmitted on network port). Such time stamp translates into time units as\n\t * port speed is fixed but such approach simplifies the code.\n\t */\n\tm = time_diff / RTE_RED_S;\n\n\t/**\n\t * Check that m will fit into 16-bit unsigned integer\n\t */\n\tif (m >= RTE_RED_2POW16) {\n\t\tred->avg = 0;\n\t} else {\n\t\tred->avg = (red->avg >> RTE_RED_SCALING) * __rte_red_calc_qempty_factor(red_cfg->wq_log2, (uint16_t) m);\n\t}\n\n\treturn 0;\n}\n\n/**\n * Drop probability (Sally Floyd and Van Jacobson):\n *\n * pb = (1 / maxp_inv) * (avg - min_th) / (max_th - min_th)\n * pa = pb / (2 - count * pb)\n *\n *\n * (1 / maxp_inv) * (avg - min_th)\n * ---------------------------------\n * max_th - min_th\n * pa = -----------------------------------------------\n * count * (1 / maxp_inv) * (avg - min_th)\n * 2 - -----------------------------------------\n * max_th - min_th\n *\n *\n * avg - min_th\n * pa = -----------------------------------------------------------\n * 2 * (max_th - min_th) * maxp_inv - count * (avg - min_th)\n *\n *\n * We define pa_const as: pa_const = 2 * (max_th - min_th) * maxp_inv. Then:\n *\n *\n * avg - min_th\n * pa = -----------------------------------\n * pa_const - count * (avg - min_th)\n */\n\n/**\n * @brief make a decision to drop or enqueue a packet based on mark probability\n * criteria\n *\n * @param red_cfg [in] config pointer to structure defining RED parameters\n * @param red [in,out] data pointer to RED runtime data\n *\n * @return operation status\n * @retval 0 enqueue the packet\n * @retval 1 drop the packet\n */\nstatic inline int\n__rte_red_drop(const struct rte_red_config *red_cfg, struct rte_red *red)\n{\n\tuint32_t pa_num = 0; /* numerator of drop-probability */\n\tuint32_t pa_den = 0; /* denominator of drop-probability */\n\tuint32_t pa_num_count = 0;\n\n\tpa_num = (red->avg - red_cfg->min_th) >> (red_cfg->wq_log2);\n\n\tpa_num_count = red->count * pa_num;\n\n\tif (red_cfg->pa_const <= pa_num_count)\n\t\treturn 1;\n\n\tpa_den = red_cfg->pa_const - pa_num_count;\n\n\t/* If drop, generate and save random number to be used next time */\n\tif (unlikely((rte_red_rand_val % pa_den) < pa_num)) {\n\t\trte_red_rand_val = rte_fast_rand();\n\n\t\treturn 1;\n\t}\n\n\t/* No drop */\n\treturn 0;\n}\n\n/**\n * @brief Decides if new packet should be enqeued or dropped in queue non-empty case\n *\n * @param red_cfg [in] config pointer to a RED configuration parameter structure\n * @param red [in,out] data pointer to RED runtime data\n * @param q [in] current queue size (measured in packets)\n *\n * @return Operation status\n * @retval 0 enqueue the packet\n * @retval 1 drop the packet based on max threshold criterion\n * @retval 2 drop the packet based on mark probability criterion\n */\nstatic inline int\nrte_red_enqueue_nonempty(const struct rte_red_config *red_cfg,\n\tstruct rte_red *red,\n\tconst unsigned q)\n{\n\tRTE_RED_ASSERT(red_cfg != NULL);\n\tRTE_RED_ASSERT(red != NULL);\n\n\t/**\n\t* EWMA filter (Sally Floyd and Van Jacobson):\n\t* avg = (1 - wq) * avg + wq * q\n\t* avg = avg + q * wq - avg * wq\n\t*\n\t* We select: wq = 2^(-n). Let scaled version of avg be: avg_s = avg * 2^(N+n). We get:\n\t* avg_s = avg_s + q * 2^N - avg_s * 2^(-n)\n\t*\n\t* By using shift left/right operations, we get:\n\t* avg_s = avg_s + (q << N) - (avg_s >> n)\n\t* avg_s += (q << N) - (avg_s >> n)\n\t*/\n\n\t/* avg update */\n\tred->avg += (q << RTE_RED_SCALING) - (red->avg >> red_cfg->wq_log2);\n\n\t/* avg < min_th: do not mark the packet */\n\tif (red->avg < red_cfg->min_th) {\n\t\tred->count ++;\n\t\treturn 0;\n\t}\n\n\t/* min_th <= avg < max_th: mark the packet with pa probability */\n\tif (red->avg < red_cfg->max_th) {\n\t\tif (!__rte_red_drop(red_cfg, red)) {\n\t\t\tred->count ++;\n\t\t\treturn 0;\n\t\t}\n\n\t\tred->count = 0;\n\t\treturn 2;\n\t}\n\n\t/* max_th <= avg: always mark the packet */\n\tred->count = 0;\n\treturn 1;\n}\n\n/**\n * @brief Decides if new packet should be enqeued or dropped\n * Updates run time data based on new queue size value.\n * Based on new queue average and RED configuration parameters\n * gives verdict whether to enqueue or drop the packet.\n *\n * @param red_cfg [in] config pointer to a RED configuration parameter structure\n * @param red [in,out] data pointer to RED runtime data\n * @param q [in] updated queue size in packets\n * @param time [in] current time stamp\n *\n * @return Operation status\n * @retval 0 enqueue the packet\n * @retval 1 drop the packet based on max threshold criteria\n * @retval 2 drop the packet based on mark probability criteria\n */\nstatic inline int\nrte_red_enqueue(const struct rte_red_config *red_cfg,\n\tstruct rte_red *red,\n\tconst unsigned q,\n\tconst uint64_t time)\n{\n\tRTE_RED_ASSERT(red_cfg != NULL);\n\tRTE_RED_ASSERT(red != NULL);\n\n\tif (q != 0) {\n\t\treturn rte_red_enqueue_nonempty(red_cfg, red, q);\n\t} else {\n\t\treturn rte_red_enqueue_empty(red_cfg, red, time);\n\t}\n}\n\n/**\n * @brief Callback to records time that queue became empty\n *\n * @param red [in,out] data pointer to RED runtime data\n * @param time [in] current time stamp\n */\nstatic inline void\nrte_red_mark_queue_empty(struct rte_red *red, const uint64_t time)\n{\n\tred->q_time = time;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __RTE_RED_H_INCLUDED__ */\n" }, { "path": "lib/librte_sched/rte_sched.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_sched.h\"\n#include \"rte_bitmap.h\"\n#include \"rte_sched_common.h\"\n#include \"rte_approx.h\"\n\n#ifdef __INTEL_COMPILER\n#pragma warning(disable:2259) /* conversion may lose significant bits */\n#endif\n\n#ifndef RTE_SCHED_DEBUG\n#define RTE_SCHED_DEBUG 0\n#endif\n\n#ifndef RTE_SCHED_OPTIMIZATIONS\n#define RTE_SCHED_OPTIMIZATIONS\t\t 0\n#endif\n\n#if RTE_SCHED_OPTIMIZATIONS\n#include \n#endif\n\n#define RTE_SCHED_ENQUEUE 1\n\n#define RTE_SCHED_TS 1\n\n#if RTE_SCHED_TS == 0 /* Infinite credits. Traffic shaping disabled. */\n#define RTE_SCHED_TS_CREDITS_UPDATE 0\n#define RTE_SCHED_TS_CREDITS_CHECK 0\n#else /* Real Credits. Full traffic shaping implemented. */\n#define RTE_SCHED_TS_CREDITS_UPDATE 1\n#define RTE_SCHED_TS_CREDITS_CHECK 1\n#endif\n\n#ifndef RTE_SCHED_TB_RATE_CONFIG_ERR\n#define RTE_SCHED_TB_RATE_CONFIG_ERR (1e-7)\n#endif\n\n#define RTE_SCHED_WRR 1\n\n#ifndef RTE_SCHED_WRR_SHIFT\n#define RTE_SCHED_WRR_SHIFT 3\n#endif\n\n#ifndef RTE_SCHED_PORT_N_GRINDERS\n#define RTE_SCHED_PORT_N_GRINDERS 8\n#endif\n#if (RTE_SCHED_PORT_N_GRINDERS == 0) || (RTE_SCHED_PORT_N_GRINDERS & (RTE_SCHED_PORT_N_GRINDERS - 1))\n#error Number of grinders must be non-zero and a power of 2\n#endif\n#if (RTE_SCHED_OPTIMIZATIONS && (RTE_SCHED_PORT_N_GRINDERS != 8))\n#error Number of grinders must be 8 when RTE_SCHED_OPTIMIZATIONS is set\n#endif\n\n#define RTE_SCHED_GRINDER_PCACHE_SIZE (64 / RTE_SCHED_QUEUES_PER_PIPE)\n\n#define RTE_SCHED_PIPE_INVALID UINT32_MAX\n\n#define RTE_SCHED_BMP_POS_INVALID UINT32_MAX\n\nstruct rte_sched_subport {\n\t/* Token bucket (TB) */\n\tuint64_t tb_time; /* time of last update */\n\tuint32_t tb_period;\n\tuint32_t tb_credits_per_period;\n\tuint32_t tb_size;\n\tuint32_t tb_credits;\n\n\t/* Traffic classes (TCs) */\n\tuint64_t tc_time; /* time of next update */\n\tuint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n\tuint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n\tuint32_t tc_period;\n\n\t/* TC oversubscription */\n\tuint32_t tc_ov_wm;\n\tuint32_t tc_ov_wm_min;\n\tuint32_t tc_ov_wm_max;\n\tuint8_t tc_ov_period_id;\n\tuint8_t tc_ov;\n\tuint32_t tc_ov_n;\n\tdouble tc_ov_rate;\n\n\t/* Statistics */\n\tstruct rte_sched_subport_stats stats;\n};\n\nstruct rte_sched_pipe_profile {\n\t/* Token bucket (TB) */\n\tuint32_t tb_period;\n\tuint32_t tb_credits_per_period;\n\tuint32_t tb_size;\n\n\t/* Pipe traffic classes */\n\tuint32_t tc_period;\n\tuint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n\tuint8_t tc_ov_weight;\n\n\t/* Pipe queues */\n\tuint8_t wrr_cost[RTE_SCHED_QUEUES_PER_PIPE];\n};\n\nstruct rte_sched_pipe {\n\t/* Token bucket (TB) */\n\tuint64_t tb_time; /* time of last update */\n\tuint32_t tb_credits;\n\n\t/* Pipe profile and flags */\n\tuint32_t profile;\n\n\t/* Traffic classes (TCs) */\n\tuint64_t tc_time; /* time of next update */\n\tuint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n\n\t/* Weighted Round Robin (WRR) */\n\tuint8_t wrr_tokens[RTE_SCHED_QUEUES_PER_PIPE];\n\n\t/* TC oversubscription */\n\tuint32_t tc_ov_credits;\n\tuint8_t tc_ov_period_id;\n\tuint8_t reserved[3];\n} __rte_cache_aligned;\n\nstruct rte_sched_queue {\n\tuint16_t qw;\n\tuint16_t qr;\n};\n\nstruct rte_sched_queue_extra {\n\tstruct rte_sched_queue_stats stats;\n#ifdef RTE_SCHED_RED\n\tstruct rte_red red;\n#endif\n};\n\nenum grinder_state {\n\te_GRINDER_PREFETCH_PIPE = 0,\n\te_GRINDER_PREFETCH_TC_QUEUE_ARRAYS,\n\te_GRINDER_PREFETCH_MBUF,\n\te_GRINDER_READ_MBUF\n};\n\n/*\n * Path through the scheduler hierarchy used by the scheduler enqueue\n * operation to identify the destination queue for the current\n * packet. Stored in the field pkt.hash.sched of struct rte_mbuf of\n * each packet, typically written by the classification stage and read\n * by scheduler enqueue.\n */\nstruct __rte_sched_port_hierarchy {\n\tuint32_t queue:2; /**< Queue ID (0 .. 3) */\n\tuint32_t traffic_class:2; /**< Traffic class ID (0 .. 3)*/\n\tuint32_t pipe:20; /**< Pipe ID */\n\tuint32_t subport:6; /**< Subport ID */\n\tuint32_t color:2; /**< Color */\n};\n\nstruct rte_sched_grinder {\n\t/* Pipe cache */\n\tuint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];\n\tuint32_t pcache_qindex[RTE_SCHED_GRINDER_PCACHE_SIZE];\n\tuint32_t pcache_w;\n\tuint32_t pcache_r;\n\n\t/* Current pipe */\n\tenum grinder_state state;\n\tuint32_t productive;\n\tuint32_t pindex;\n\tstruct rte_sched_subport *subport;\n\tstruct rte_sched_pipe *pipe;\n\tstruct rte_sched_pipe_profile *pipe_params;\n\n\t/* TC cache */\n\tuint8_t tccache_qmask[4];\n\tuint32_t tccache_qindex[4];\n\tuint32_t tccache_w;\n\tuint32_t tccache_r;\n\n\t/* Current TC */\n\tuint32_t tc_index;\n\tstruct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n\tstruct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n\tuint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n\tuint16_t qsize;\n\tuint32_t qmask;\n\tuint32_t qpos;\n\tstruct rte_mbuf *pkt;\n\n\t/* WRR */\n\tuint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n\tuint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n\tuint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n};\n\nstruct rte_sched_port {\n\t/* User parameters */\n\tuint32_t n_subports_per_port;\n\tuint32_t n_pipes_per_subport;\n\tuint32_t rate;\n\tuint32_t mtu;\n\tuint32_t frame_overhead;\n\tuint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n\tuint32_t n_pipe_profiles;\n\tuint32_t pipe_tc3_rate_max;\n#ifdef RTE_SCHED_RED\n\tstruct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][e_RTE_METER_COLORS];\n#endif\n\n\t/* Timing */\n\tuint64_t time_cpu_cycles; /* Current CPU time measured in CPU cyles */\n\tuint64_t time_cpu_bytes; /* Current CPU time measured in bytes */\n\tuint64_t time; /* Current NIC TX time measured in bytes */\n\tdouble cycles_per_byte; /* CPU cycles per byte */\n\n\t/* Scheduling loop detection */\n\tuint32_t pipe_loop;\n\tuint32_t pipe_exhaustion;\n\n\t/* Bitmap */\n\tstruct rte_bitmap *bmp;\n\tuint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;\n\n\t/* Grinders */\n\tstruct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];\n\tuint32_t busy_grinders;\n\tstruct rte_mbuf **pkts_out;\n\tuint32_t n_pkts_out;\n\n\t/* Queue base calculation */\n\tuint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];\n\tuint32_t qsize_sum;\n\n\t/* Large data structures */\n\tstruct rte_sched_subport *subport;\n\tstruct rte_sched_pipe *pipe;\n\tstruct rte_sched_queue *queue;\n\tstruct rte_sched_queue_extra *queue_extra;\n\tstruct rte_sched_pipe_profile *pipe_profiles;\n\tuint8_t *bmp_array;\n\tstruct rte_mbuf **queue_array;\n\tuint8_t memory[0] __rte_cache_aligned;\n} __rte_cache_aligned;\n\nenum rte_sched_port_array {\n\te_RTE_SCHED_PORT_ARRAY_SUBPORT = 0,\n\te_RTE_SCHED_PORT_ARRAY_PIPE,\n\te_RTE_SCHED_PORT_ARRAY_QUEUE,\n\te_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA,\n\te_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES,\n\te_RTE_SCHED_PORT_ARRAY_BMP_ARRAY,\n\te_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY,\n\te_RTE_SCHED_PORT_ARRAY_TOTAL,\n};\n\n#ifdef RTE_SCHED_COLLECT_STATS\n\nstatic inline uint32_t\nrte_sched_port_queues_per_subport(struct rte_sched_port *port)\n{\n\treturn RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport;\n}\n\n#endif\n\nstatic inline uint32_t\nrte_sched_port_queues_per_port(struct rte_sched_port *port)\n{\n\treturn RTE_SCHED_QUEUES_PER_PIPE * port->n_pipes_per_subport * port->n_subports_per_port;\n}\n\nstatic int\nrte_sched_port_check_params(struct rte_sched_port_params *params)\n{\n\tuint32_t i, j;\n\n\tif (params == NULL) {\n\t\treturn -1;\n\t}\n\n\t/* socket */\n\tif ((params->socket < 0) || (params->socket >= RTE_MAX_NUMA_NODES)) {\n\t\treturn -3;\n\t}\n\n\t/* rate */\n\tif (params->rate == 0) {\n\t\treturn -4;\n\t}\n\n\t/* mtu */\n\tif (params->mtu == 0) {\n\t\treturn -5;\n\t}\n\n\t/* n_subports_per_port: non-zero, power of 2 */\n\tif ((params->n_subports_per_port == 0) || (!rte_is_power_of_2(params->n_subports_per_port))) {\n\t\treturn -6;\n\t}\n\n\t/* n_pipes_per_subport: non-zero, power of 2 */\n\tif ((params->n_pipes_per_subport == 0) || (!rte_is_power_of_2(params->n_pipes_per_subport))) {\n\t\treturn -7;\n\t}\n\n\t/* qsize: non-zero, power of 2, no bigger than 32K (due to 16-bit read/write pointers) */\n\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {\n\t\tuint16_t qsize = params->qsize[i];\n\n\t\tif ((qsize == 0) || (!rte_is_power_of_2(qsize))) {\n\t\t\treturn -8;\n\t\t}\n\t}\n\n\t/* pipe_profiles and n_pipe_profiles */\n\tif ((params->pipe_profiles == NULL) ||\n\t (params->n_pipe_profiles == 0) ||\n\t (params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_PORT)) {\n\t\treturn -9;\n\t}\n\n\tfor (i = 0; i < params->n_pipe_profiles; i ++) {\n\t\tstruct rte_sched_pipe_params *p = params->pipe_profiles + i;\n\n\t\t/* TB rate: non-zero, not greater than port rate */\n\t\tif ((p->tb_rate == 0) || (p->tb_rate > params->rate)) {\n\t\t\treturn -10;\n\t\t}\n\n\t\t/* TB size: non-zero */\n\t\tif (p->tb_size == 0) {\n\t\t\treturn -11;\n\t\t}\n\n\t\t/* TC rate: non-zero, less than pipe rate */\n\t\tfor (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {\n\t\t\tif ((p->tc_rate[j] == 0) || (p->tc_rate[j] > p->tb_rate)) {\n\t\t\t\treturn -12;\n\t\t\t}\n\t\t}\n\n\t\t/* TC period: non-zero */\n\t\tif (p->tc_period == 0) {\n\t\t\treturn -13;\n\t\t}\n\n#ifdef RTE_SCHED_SUBPORT_TC_OV\n\t\t/* TC3 oversubscription weight: non-zero */\n\t\tif (p->tc_ov_weight == 0) {\n\t\t\treturn -14;\n\t\t}\n#endif\n\n\t\t/* Queue WRR weights: non-zero */\n\t\tfor (j = 0; j < RTE_SCHED_QUEUES_PER_PIPE; j ++) {\n\t\t\tif (p->wrr_weights[j] == 0) {\n\t\t\t\treturn -15;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic uint32_t\nrte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sched_port_array array)\n{\n\tuint32_t n_subports_per_port = params->n_subports_per_port;\n\tuint32_t n_pipes_per_subport = params->n_pipes_per_subport;\n\tuint32_t n_pipes_per_port = n_pipes_per_subport * n_subports_per_port;\n\tuint32_t n_queues_per_port = RTE_SCHED_QUEUES_PER_PIPE * n_pipes_per_subport * n_subports_per_port;\n\n\tuint32_t size_subport = n_subports_per_port * sizeof(struct rte_sched_subport);\n\tuint32_t size_pipe = n_pipes_per_port * sizeof(struct rte_sched_pipe);\n\tuint32_t size_queue = n_queues_per_port * sizeof(struct rte_sched_queue);\n\tuint32_t size_queue_extra = n_queues_per_port * sizeof(struct rte_sched_queue_extra);\n\tuint32_t size_pipe_profiles = RTE_SCHED_PIPE_PROFILES_PER_PORT * sizeof(struct rte_sched_pipe_profile);\n\tuint32_t size_bmp_array = rte_bitmap_get_memory_footprint(n_queues_per_port);\n\tuint32_t size_per_pipe_queue_array, size_queue_array;\n\n\tuint32_t base, i;\n\n\tsize_per_pipe_queue_array = 0;\n\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {\n\t\tsize_per_pipe_queue_array += RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS * params->qsize[i] * sizeof(struct rte_mbuf *);\n\t}\n\tsize_queue_array = n_pipes_per_port * size_per_pipe_queue_array;\n\n\tbase = 0;\n\n\tif (array == e_RTE_SCHED_PORT_ARRAY_SUBPORT) return base;\n\tbase += RTE_CACHE_LINE_ROUNDUP(size_subport);\n\n\tif (array == e_RTE_SCHED_PORT_ARRAY_PIPE) return base;\n\tbase += RTE_CACHE_LINE_ROUNDUP(size_pipe);\n\n\tif (array == e_RTE_SCHED_PORT_ARRAY_QUEUE) return base;\n\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue);\n\n\tif (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA) return base;\n\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue_extra);\n\n\tif (array == e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES) return base;\n\tbase += RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles);\n\n\tif (array == e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY) return base;\n\tbase += RTE_CACHE_LINE_ROUNDUP(size_bmp_array);\n\n\tif (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY) return base;\n\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue_array);\n\n\treturn base;\n}\n\nuint32_t\nrte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)\n{\n\tuint32_t size0, size1;\n\tint status;\n\n\tstatus = rte_sched_port_check_params(params);\n\tif (status != 0) {\n\t\tRTE_LOG(NOTICE, SCHED,\n\t\t\t\"Port scheduler params check failed (%d)\\n\", status);\n\n\t\treturn 0;\n\t}\n\n\tsize0 = sizeof(struct rte_sched_port);\n\tsize1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);\n\n\treturn (size0 + size1);\n}\n\nstatic void\nrte_sched_port_config_qsize(struct rte_sched_port *port)\n{\n\t/* TC 0 */\n\tport->qsize_add[0] = 0;\n\tport->qsize_add[1] = port->qsize_add[0] + port->qsize[0];\n\tport->qsize_add[2] = port->qsize_add[1] + port->qsize[0];\n\tport->qsize_add[3] = port->qsize_add[2] + port->qsize[0];\n\n\t/* TC 1 */\n\tport->qsize_add[4] = port->qsize_add[3] + port->qsize[0];\n\tport->qsize_add[5] = port->qsize_add[4] + port->qsize[1];\n\tport->qsize_add[6] = port->qsize_add[5] + port->qsize[1];\n\tport->qsize_add[7] = port->qsize_add[6] + port->qsize[1];\n\n\t/* TC 2 */\n\tport->qsize_add[8] = port->qsize_add[7] + port->qsize[1];\n\tport->qsize_add[9] = port->qsize_add[8] + port->qsize[2];\n\tport->qsize_add[10] = port->qsize_add[9] + port->qsize[2];\n\tport->qsize_add[11] = port->qsize_add[10] + port->qsize[2];\n\n\t/* TC 3 */\n\tport->qsize_add[12] = port->qsize_add[11] + port->qsize[2];\n\tport->qsize_add[13] = port->qsize_add[12] + port->qsize[3];\n\tport->qsize_add[14] = port->qsize_add[13] + port->qsize[3];\n\tport->qsize_add[15] = port->qsize_add[14] + port->qsize[3];\n\n\tport->qsize_sum = port->qsize_add[15] + port->qsize[3];\n}\n\nstatic void\nrte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)\n{\n\tstruct rte_sched_pipe_profile *p = port->pipe_profiles + i;\n\n\tRTE_LOG(DEBUG, SCHED, \"Low level config for pipe profile %u:\\n\"\n\t\t\" Token bucket: period = %u, credits per period = %u, size = %u\\n\"\n\t\t\" Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\\n\"\n\t\t\" Traffic class 3 oversubscription: weight = %hhu\\n\"\n\t\t\" WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu]\\n\",\n\t\ti,\n\n\t\t/* Token bucket */\n\t\tp->tb_period,\n\t\tp->tb_credits_per_period,\n\t\tp->tb_size,\n\n\t\t/* Traffic classes */\n\t\tp->tc_period,\n\t\tp->tc_credits_per_period[0],\n\t\tp->tc_credits_per_period[1],\n\t\tp->tc_credits_per_period[2],\n\t\tp->tc_credits_per_period[3],\n\n\t\t/* Traffic class 3 oversubscription */\n\t\tp->tc_ov_weight,\n\n\t\t/* WRR */\n\t\tp->wrr_cost[ 0], p->wrr_cost[ 1], p->wrr_cost[ 2], p->wrr_cost[ 3],\n\t\tp->wrr_cost[ 4], p->wrr_cost[ 5], p->wrr_cost[ 6], p->wrr_cost[ 7],\n\t\tp->wrr_cost[ 8], p->wrr_cost[ 9], p->wrr_cost[10], p->wrr_cost[11],\n\t\tp->wrr_cost[12], p->wrr_cost[13], p->wrr_cost[14], p->wrr_cost[15]);\n}\n\nstatic inline uint64_t\nrte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)\n{\n\tuint64_t time = time_ms;\n\ttime = (time * rate) / 1000;\n\n\treturn time;\n}\n\nstatic void\nrte_sched_port_config_pipe_profile_table(struct rte_sched_port *port, struct rte_sched_port_params *params)\n{\n\tuint32_t i, j;\n\n\tfor (i = 0; i < port->n_pipe_profiles; i ++) {\n\t\tstruct rte_sched_pipe_params *src = params->pipe_profiles + i;\n\t\tstruct rte_sched_pipe_profile *dst = port->pipe_profiles + i;\n\n\t\t/* Token Bucket */\n\t\tif (src->tb_rate == params->rate) {\n\t\t\tdst->tb_credits_per_period = 1;\n\t\t\tdst->tb_period = 1;\n\t\t} else {\n\t\t\tdouble tb_rate = ((double) src->tb_rate) / ((double) params->rate);\n\t\t\tdouble d = RTE_SCHED_TB_RATE_CONFIG_ERR;\n\n\t\t\trte_approx(tb_rate, d, &dst->tb_credits_per_period, &dst->tb_period);\n\t\t}\n\t\tdst->tb_size = src->tb_size;\n\n\t\t/* Traffic Classes */\n\t\tdst->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, params->rate);\n\t\tfor (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {\n\t\t\tdst->tc_credits_per_period[j] = (uint32_t) rte_sched_time_ms_to_bytes(src->tc_period, src->tc_rate[j]);\n\t\t}\n#ifdef RTE_SCHED_SUBPORT_TC_OV\n\t\tdst->tc_ov_weight = src->tc_ov_weight;\n#endif\n\n\t\t/* WRR */\n\t\tfor (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j ++) {\n\t\t\tuint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n\t\t\tuint32_t lcd, lcd1, lcd2;\n\t\t\tuint32_t qindex;\n\n\t\t\tqindex = j * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;\n\n\t\t\twrr_cost[0] = src->wrr_weights[qindex];\n\t\t\twrr_cost[1] = src->wrr_weights[qindex + 1];\n\t\t\twrr_cost[2] = src->wrr_weights[qindex + 2];\n\t\t\twrr_cost[3] = src->wrr_weights[qindex + 3];\n\n\t\t\tlcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);\n\t\t\tlcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);\n\t\t\tlcd = rte_get_lcd(lcd1, lcd2);\n\n\t\t\twrr_cost[0] = lcd / wrr_cost[0];\n\t\t\twrr_cost[1] = lcd / wrr_cost[1];\n\t\t\twrr_cost[2] = lcd / wrr_cost[2];\n\t\t\twrr_cost[3] = lcd / wrr_cost[3];\n\n\t\t\tdst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];\n\t\t\tdst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];\n\t\t\tdst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];\n\t\t\tdst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];\n\t\t}\n\n\t\trte_sched_port_log_pipe_profile(port, i);\n\t}\n\n\tport->pipe_tc3_rate_max = 0;\n\tfor (i = 0; i < port->n_pipe_profiles; i ++) {\n\t\tstruct rte_sched_pipe_params *src = params->pipe_profiles + i;\n\t\tuint32_t pipe_tc3_rate = src->tc_rate[3];\n\n\t\tif (port->pipe_tc3_rate_max < pipe_tc3_rate) {\n\t\t\tport->pipe_tc3_rate_max = pipe_tc3_rate;\n\t\t}\n\t}\n}\n\nstruct rte_sched_port *\nrte_sched_port_config(struct rte_sched_port_params *params)\n{\n\tstruct rte_sched_port *port = NULL;\n\tuint32_t mem_size, bmp_mem_size, n_queues_per_port, i;\n\n\t/* Check user parameters. Determine the amount of memory to allocate */\n\tmem_size = rte_sched_port_get_memory_footprint(params);\n\tif (mem_size == 0) {\n\t\treturn NULL;\n\t}\n\n\t/* Allocate memory to store the data structures */\n\tport = rte_zmalloc(\"qos_params\", mem_size, RTE_CACHE_LINE_SIZE);\n\tif (port == NULL) {\n\t\treturn NULL;\n\t}\n\n\t/* User parameters */\n\tport->n_subports_per_port = params->n_subports_per_port;\n\tport->n_pipes_per_subport = params->n_pipes_per_subport;\n\tport->rate = params->rate;\n\tport->mtu = params->mtu + params->frame_overhead;\n\tport->frame_overhead = params->frame_overhead;\n\tmemcpy(port->qsize, params->qsize, sizeof(params->qsize));\n\tport->n_pipe_profiles = params->n_pipe_profiles;\n\n#ifdef RTE_SCHED_RED\n\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n\t\tuint32_t j;\n\n\t\tfor (j = 0; j < e_RTE_METER_COLORS; j++) {\n\t\t\t/* if min/max are both zero, then RED is disabled */\n\t\t\tif ((params->red_params[i][j].min_th |\n\t\t\t params->red_params[i][j].max_th) == 0) {\n\t\t\t\tcontinue;\n\t\t\t}\n\n\t\t\tif (rte_red_config_init(&port->red_config[i][j],\n\t\t\t\tparams->red_params[i][j].wq_log2,\n\t\t\t\tparams->red_params[i][j].min_th,\n\t\t\t\tparams->red_params[i][j].max_th,\n\t\t\t\tparams->red_params[i][j].maxp_inv) != 0) {\n\t\t\t\treturn NULL;\n\t\t\t}\n\t\t}\n\t}\n#endif\n\n\t/* Timing */\n\tport->time_cpu_cycles = rte_get_tsc_cycles();\n\tport->time_cpu_bytes = 0;\n\tport->time = 0;\n\tport->cycles_per_byte = ((double) rte_get_tsc_hz()) / ((double) params->rate);\n\n\t/* Scheduling loop detection */\n\tport->pipe_loop = RTE_SCHED_PIPE_INVALID;\n\tport->pipe_exhaustion = 0;\n\n\t/* Grinders */\n\tport->busy_grinders = 0;\n\tport->pkts_out = NULL;\n\tport->n_pkts_out = 0;\n\n\t/* Queue base calculation */\n\trte_sched_port_config_qsize(port);\n\n\t/* Large data structures */\n\tport->subport = (struct rte_sched_subport *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_SUBPORT));\n\tport->pipe = (struct rte_sched_pipe *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE));\n\tport->queue = (struct rte_sched_queue *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE));\n\tport->queue_extra = (struct rte_sched_queue_extra *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA));\n\tport->pipe_profiles = (struct rte_sched_pipe_profile *) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES));\n\tport->bmp_array = port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY);\n\tport->queue_array = (struct rte_mbuf **) (port->memory + rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY));\n\n\t/* Pipe profile table */\n\trte_sched_port_config_pipe_profile_table(port, params);\n\n\t/* Bitmap */\n\tn_queues_per_port = rte_sched_port_queues_per_port(port);\n\tbmp_mem_size = rte_bitmap_get_memory_footprint(n_queues_per_port);\n\tport->bmp = rte_bitmap_init(n_queues_per_port, port->bmp_array, bmp_mem_size);\n\tif (port->bmp == NULL) {\n\t\tRTE_LOG(ERR, SCHED, \"Bitmap init error\\n\");\n\t\treturn NULL;\n\t}\n\tfor (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {\n\t\tport->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;\n\t}\n\n\treturn port;\n}\n\nvoid\nrte_sched_port_free(struct rte_sched_port *port)\n{\n\t/* Check user parameters */\n\tif (port == NULL){\n\t\treturn;\n\t}\n\n\trte_bitmap_free(port->bmp);\n\trte_free(port);\n}\n\nstatic void\nrte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)\n{\n\tstruct rte_sched_subport *s = port->subport + i;\n\n\tRTE_LOG(DEBUG, SCHED, \"Low level config for subport %u:\\n\"\n\t\t\" Token bucket: period = %u, credits per period = %u, size = %u\\n\"\n\t\t\" Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\\n\"\n\t\t\" Traffic class 3 oversubscription: wm min = %u, wm max = %u\\n\",\n\t\ti,\n\n\t\t/* Token bucket */\n\t\ts->tb_period,\n\t\ts->tb_credits_per_period,\n\t\ts->tb_size,\n\n\t\t/* Traffic classes */\n\t\ts->tc_period,\n\t\ts->tc_credits_per_period[0],\n\t\ts->tc_credits_per_period[1],\n\t\ts->tc_credits_per_period[2],\n\t\ts->tc_credits_per_period[3],\n\n\t\t/* Traffic class 3 oversubscription */\n\t\ts->tc_ov_wm_min,\n\t\ts->tc_ov_wm_max);\n}\n\nint\nrte_sched_subport_config(struct rte_sched_port *port,\n\tuint32_t subport_id,\n\tstruct rte_sched_subport_params *params)\n{\n\tstruct rte_sched_subport *s;\n\tuint32_t i;\n\n\t/* Check user parameters */\n\tif ((port == NULL) ||\n\t (subport_id >= port->n_subports_per_port) ||\n\t\t(params == NULL)) {\n\t\treturn -1;\n\t}\n\n\tif ((params->tb_rate == 0) || (params->tb_rate > port->rate)) {\n\t\treturn -2;\n\t}\n\n\tif (params->tb_size == 0) {\n\t\treturn -3;\n\t}\n\n\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {\n\t\tif ((params->tc_rate[i] == 0) || (params->tc_rate[i] > params->tb_rate)) {\n\t\t\treturn -4;\n\t\t}\n\t}\n\n\tif (params->tc_period == 0) {\n\t\treturn -5;\n\t}\n\n\ts = port->subport + subport_id;\n\n\t/* Token Bucket (TB) */\n\tif (params->tb_rate == port->rate) {\n\t\ts->tb_credits_per_period = 1;\n\t\ts->tb_period = 1;\n\t} else {\n\t\tdouble tb_rate = ((double) params->tb_rate) / ((double) port->rate);\n\t\tdouble d = RTE_SCHED_TB_RATE_CONFIG_ERR;\n\n\t\trte_approx(tb_rate, d, &s->tb_credits_per_period, &s->tb_period);\n\t}\n\ts->tb_size = params->tb_size;\n\ts->tb_time = port->time;\n\ts->tb_credits = s->tb_size / 2;\n\n\t/* Traffic Classes (TCs) */\n\ts->tc_period = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, port->rate);\n\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {\n\t\ts->tc_credits_per_period[i] = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, params->tc_rate[i]);\n\t}\n\ts->tc_time = port->time + s->tc_period;\n\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {\n\t\ts->tc_credits[i] = s->tc_credits_per_period[i];\n\t}\n\n#ifdef RTE_SCHED_SUBPORT_TC_OV\n\t/* TC oversubscription */\n\ts->tc_ov_wm_min = port->mtu;\n\ts->tc_ov_wm_max = (uint32_t) rte_sched_time_ms_to_bytes(params->tc_period, port->pipe_tc3_rate_max);\n\ts->tc_ov_wm = s->tc_ov_wm_max;\n\ts->tc_ov_period_id = 0;\n\ts->tc_ov = 0;\n\ts->tc_ov_n = 0;\n\ts->tc_ov_rate = 0;\n#endif\n\n\trte_sched_port_log_subport_config(port, subport_id);\n\n\treturn 0;\n}\n\nint\nrte_sched_pipe_config(struct rte_sched_port *port,\n\tuint32_t subport_id,\n\tuint32_t pipe_id,\n\tint32_t pipe_profile)\n{\n\tstruct rte_sched_subport *s;\n\tstruct rte_sched_pipe *p;\n\tstruct rte_sched_pipe_profile *params;\n\tuint32_t deactivate, profile, i;\n\n\t/* Check user parameters */\n\tprofile = (uint32_t) pipe_profile;\n\tdeactivate = (pipe_profile < 0);\n\tif ((port == NULL) ||\n\t (subport_id >= port->n_subports_per_port) ||\n\t\t(pipe_id >= port->n_pipes_per_subport) ||\n\t\t((!deactivate) && (profile >= port->n_pipe_profiles))) {\n\t\treturn -1;\n\t}\n\n\t/* Check that subport configuration is valid */\n\ts = port->subport + subport_id;\n\tif (s->tb_period == 0) {\n\t\treturn -2;\n\t}\n\n\tp = port->pipe + (subport_id * port->n_pipes_per_subport + pipe_id);\n\n\t/* Handle the case when pipe already has a valid configuration */\n\tif (p->tb_time) {\n\t\tparams = port->pipe_profiles + p->profile;\n\n#ifdef RTE_SCHED_SUBPORT_TC_OV\n\t\tdouble subport_tc3_rate = ((double) s->tc_credits_per_period[3]) / ((double) s->tc_period);\n\t\tdouble pipe_tc3_rate = ((double) params->tc_credits_per_period[3]) / ((double) params->tc_period);\n\t\tuint32_t tc3_ov = s->tc_ov;\n\n\t\t/* Unplug pipe from its subport */\n\t\ts->tc_ov_n -= params->tc_ov_weight;\n\t\ts->tc_ov_rate -= pipe_tc3_rate;\n\t\ts->tc_ov = s->tc_ov_rate > subport_tc3_rate;\n\n\t\tif (s->tc_ov != tc3_ov) {\n\t\t\tRTE_LOG(DEBUG, SCHED,\n\t\t\t\t\"Subport %u TC3 oversubscription is OFF (%.4lf >= %.4lf)\\n\",\n\t\t\t\tsubport_id, subport_tc3_rate, s->tc_ov_rate);\n\t\t}\n#endif\n\n\t\t/* Reset the pipe */\n\t\tmemset(p, 0, sizeof(struct rte_sched_pipe));\n\t}\n\n\tif (deactivate) {\n\t\treturn 0;\n\t}\n\n\t/* Apply the new pipe configuration */\n\tp->profile = profile;\n\tparams = port->pipe_profiles + p->profile;\n\n\t/* Token Bucket (TB) */\n\tp->tb_time = port->time;\n\tp->tb_credits = params->tb_size / 2;\n\n\t/* Traffic Classes (TCs) */\n\tp->tc_time = port->time + params->tc_period;\n\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i ++) {\n\t\tp->tc_credits[i] = params->tc_credits_per_period[i];\n\t}\n\n#ifdef RTE_SCHED_SUBPORT_TC_OV\n\t{\n\t\t/* Subport TC3 oversubscription */\n\t\tdouble subport_tc3_rate = ((double) s->tc_credits_per_period[3]) / ((double) s->tc_period);\n\t\tdouble pipe_tc3_rate = ((double) params->tc_credits_per_period[3]) / ((double) params->tc_period);\n\t\tuint32_t tc3_ov = s->tc_ov;\n\n\t\ts->tc_ov_n += params->tc_ov_weight;\n\t\ts->tc_ov_rate += pipe_tc3_rate;\n\t\ts->tc_ov = s->tc_ov_rate > subport_tc3_rate;\n\n\t\tif (s->tc_ov != tc3_ov) {\n\t\t\tRTE_LOG(DEBUG, SCHED,\n\t\t\t\t\"Subport %u TC3 oversubscription is ON (%.4lf < %.4lf)\\n\",\n\t\t\t\tsubport_id, subport_tc3_rate, s->tc_ov_rate);\n\t\t}\n\t\tp->tc_ov_period_id = s->tc_ov_period_id;\n\t\tp->tc_ov_credits = s->tc_ov_wm;\n\t}\n#endif\n\n\treturn 0;\n}\n\nvoid\nrte_sched_port_pkt_write(struct rte_mbuf *pkt,\n\t\t\t uint32_t subport, uint32_t pipe, uint32_t traffic_class,\n\t\t\t uint32_t queue, enum rte_meter_color color)\n{\n\tstruct __rte_sched_port_hierarchy *sched\n\t\t= (struct __rte_sched_port_hierarchy *) &pkt->hash.sched;\n\n\tsched->color = (uint32_t) color;\n\tsched->subport = subport;\n\tsched->pipe = pipe;\n\tsched->traffic_class = traffic_class;\n\tsched->queue = queue;\n}\n\nvoid\nrte_sched_port_pkt_read_tree_path(const struct rte_mbuf *pkt,\n\t\t\t\t uint32_t *subport, uint32_t *pipe,\n\t\t\t\t uint32_t *traffic_class, uint32_t *queue)\n{\n\tconst struct __rte_sched_port_hierarchy *sched\n\t\t= (const struct __rte_sched_port_hierarchy *) &pkt->hash.sched;\n\n\t*subport = sched->subport;\n\t*pipe = sched->pipe;\n\t*traffic_class = sched->traffic_class;\n\t*queue = sched->queue;\n}\n\n\nenum rte_meter_color\nrte_sched_port_pkt_read_color(const struct rte_mbuf *pkt)\n{\n\tconst struct __rte_sched_port_hierarchy *sched\n\t\t= (const struct __rte_sched_port_hierarchy *) &pkt->hash.sched;\n\n\treturn (enum rte_meter_color) sched->color;\n}\n\nint\nrte_sched_subport_read_stats(struct rte_sched_port *port,\n\tuint32_t subport_id,\n\tstruct rte_sched_subport_stats *stats,\n\tuint32_t *tc_ov)\n{\n\tstruct rte_sched_subport *s;\n\n\t/* Check user parameters */\n\tif ((port == NULL) ||\n\t (subport_id >= port->n_subports_per_port) ||\n\t\t(stats == NULL) ||\n\t\t(tc_ov == NULL)) {\n\t\treturn -1;\n\t}\n\ts = port->subport + subport_id;\n\n\t/* Copy subport stats and clear */\n\tmemcpy(stats, &s->stats, sizeof(struct rte_sched_subport_stats));\n\tmemset(&s->stats, 0, sizeof(struct rte_sched_subport_stats));\n\n\t/* Subport TC ovesubscription status */\n\t*tc_ov = s->tc_ov;\n\n\treturn 0;\n}\n\nint\nrte_sched_queue_read_stats(struct rte_sched_port *port,\n\tuint32_t queue_id,\n\tstruct rte_sched_queue_stats *stats,\n\tuint16_t *qlen)\n{\n\tstruct rte_sched_queue *q;\n\tstruct rte_sched_queue_extra *qe;\n\n\t/* Check user parameters */\n\tif ((port == NULL) ||\n\t (queue_id >= rte_sched_port_queues_per_port(port)) ||\n\t\t(stats == NULL) ||\n\t\t(qlen == NULL)) {\n\t\treturn -1;\n\t}\n\tq = port->queue + queue_id;\n\tqe = port->queue_extra + queue_id;\n\n\t/* Copy queue stats and clear */\n\tmemcpy(stats, &qe->stats, sizeof(struct rte_sched_queue_stats));\n\tmemset(&qe->stats, 0, sizeof(struct rte_sched_queue_stats));\n\n\t/* Queue length */\n\t*qlen = q->qw - q->qr;\n\n\treturn 0;\n}\n\nstatic inline uint32_t\nrte_sched_port_qindex(struct rte_sched_port *port, uint32_t subport, uint32_t pipe, uint32_t traffic_class, uint32_t queue)\n{\n\tuint32_t result;\n\n\tresult = subport * port->n_pipes_per_subport + pipe;\n\tresult = result * RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE + traffic_class;\n\tresult = result * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS + queue;\n\n\treturn result;\n}\n\nstatic inline struct rte_mbuf **\nrte_sched_port_qbase(struct rte_sched_port *port, uint32_t qindex)\n{\n\tuint32_t pindex = qindex >> 4;\n\tuint32_t qpos = qindex & 0xF;\n\n\treturn (port->queue_array + pindex * port->qsize_sum + port->qsize_add[qpos]);\n}\n\nstatic inline uint16_t\nrte_sched_port_qsize(struct rte_sched_port *port, uint32_t qindex)\n{\n\tuint32_t tc = (qindex >> 2) & 0x3;\n\n\treturn port->qsize[tc];\n}\n\n#if RTE_SCHED_DEBUG\n\nstatic inline int\nrte_sched_port_queue_is_empty(struct rte_sched_port *port, uint32_t qindex)\n{\n\tstruct rte_sched_queue *queue = port->queue + qindex;\n\n\treturn (queue->qr == queue->qw);\n}\n\nstatic inline int\nrte_sched_port_queue_is_full(struct rte_sched_port *port, uint32_t qindex)\n{\n\tstruct rte_sched_queue *queue = port->queue + qindex;\n\tuint16_t qsize = rte_sched_port_qsize(port, qindex);\n\tuint16_t qlen = queue->qw - queue->qr;\n\n\treturn (qlen >= qsize);\n}\n\n#endif /* RTE_SCHED_DEBUG */\n\n#ifdef RTE_SCHED_COLLECT_STATS\n\nstatic inline void\nrte_sched_port_update_subport_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)\n{\n\tstruct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));\n\tuint32_t tc_index = (qindex >> 2) & 0x3;\n\tuint32_t pkt_len = pkt->pkt_len;\n\n\ts->stats.n_pkts_tc[tc_index] += 1;\n\ts->stats.n_bytes_tc[tc_index] += pkt_len;\n}\n\nstatic inline void\nrte_sched_port_update_subport_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)\n{\n\tstruct rte_sched_subport *s = port->subport + (qindex / rte_sched_port_queues_per_subport(port));\n\tuint32_t tc_index = (qindex >> 2) & 0x3;\n\tuint32_t pkt_len = pkt->pkt_len;\n\n\ts->stats.n_pkts_tc_dropped[tc_index] += 1;\n\ts->stats.n_bytes_tc_dropped[tc_index] += pkt_len;\n}\n\nstatic inline void\nrte_sched_port_update_queue_stats(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)\n{\n\tstruct rte_sched_queue_extra *qe = port->queue_extra + qindex;\n\tuint32_t pkt_len = pkt->pkt_len;\n\n\tqe->stats.n_pkts += 1;\n\tqe->stats.n_bytes += pkt_len;\n}\n\nstatic inline void\nrte_sched_port_update_queue_stats_on_drop(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf *pkt)\n{\n\tstruct rte_sched_queue_extra *qe = port->queue_extra + qindex;\n\tuint32_t pkt_len = pkt->pkt_len;\n\n\tqe->stats.n_pkts_dropped += 1;\n\tqe->stats.n_bytes_dropped += pkt_len;\n}\n\n#endif /* RTE_SCHED_COLLECT_STATS */\n\n#ifdef RTE_SCHED_RED\n\nstatic inline int\nrte_sched_port_red_drop(struct rte_sched_port *port, struct rte_mbuf *pkt, uint32_t qindex, uint16_t qlen)\n{\n\tstruct rte_sched_queue_extra *qe;\n\tstruct rte_red_config *red_cfg;\n struct rte_red *red;\n\tuint32_t tc_index;\n\tenum rte_meter_color color;\n\n\ttc_index = (qindex >> 2) & 0x3;\n\tcolor = rte_sched_port_pkt_read_color(pkt);\n\tred_cfg = &port->red_config[tc_index][color];\n\n\tif ((red_cfg->min_th | red_cfg->max_th) == 0)\n\t\treturn 0;\n\n\tqe = port->queue_extra + qindex;\n\tred = &qe->red;\n\n\treturn rte_red_enqueue(red_cfg, red, qlen, port->time);\n}\n\nstatic inline void\nrte_sched_port_set_queue_empty_timestamp(struct rte_sched_port *port, uint32_t qindex)\n{\n\tstruct rte_sched_queue_extra *qe;\n struct rte_red *red;\n\n\tqe = port->queue_extra + qindex;\n\tred = &qe->red;\n\n\trte_red_mark_queue_empty(red, port->time);\n}\n\n#else\n\n#define rte_sched_port_red_drop(port, pkt, qindex, qlen) 0\n\n#define rte_sched_port_set_queue_empty_timestamp(port, qindex)\n\n#endif /* RTE_SCHED_RED */\n\n#if RTE_SCHED_DEBUG\n\nstatic inline int\ndebug_pipe_is_empty(struct rte_sched_port *port, uint32_t pindex)\n{\n\tuint32_t qindex, i;\n\n\tqindex = pindex << 4;\n\n\tfor (i = 0; i < 16; i ++){\n\t\tuint32_t queue_empty = rte_sched_port_queue_is_empty(port, qindex + i);\n\t\tuint32_t bmp_bit_clear = (rte_bitmap_get(port->bmp, qindex + i) == 0);\n\n\t\tif (queue_empty != bmp_bit_clear){\n\t\t\trte_panic(\"Queue status mismatch for queue %u of pipe %u\\n\", i, pindex);\n\t\t}\n\n\t\tif (!queue_empty){\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\treturn 1;\n}\n\nstatic inline void\ndebug_check_queue_slab(struct rte_sched_port *port, uint32_t bmp_pos, uint64_t bmp_slab)\n{\n\tuint64_t mask;\n\tuint32_t i, panic;\n\n\tif (bmp_slab == 0){\n\t\trte_panic(\"Empty slab at position %u\\n\", bmp_pos);\n\t}\n\n\tpanic = 0;\n\tfor (i = 0, mask = 1; i < 64; i ++, mask <<= 1) {\n\t\tif (mask & bmp_slab){\n\t\t\tif (rte_sched_port_queue_is_empty(port, bmp_pos + i)) {\n\t\t\t\tprintf(\"Queue %u (slab offset %u) is empty\\n\", bmp_pos + i, i);\n\t\t\t\tpanic = 1;\n\t\t\t}\n\t\t}\n\t}\n\n\tif (panic){\n\t\trte_panic(\"Empty queues in slab 0x%\" PRIx64 \"starting at position %u\\n\",\n\t\t\tbmp_slab, bmp_pos);\n\t}\n}\n\n#endif /* RTE_SCHED_DEBUG */\n\nstatic inline uint32_t\nrte_sched_port_enqueue_qptrs_prefetch0(struct rte_sched_port *port, struct rte_mbuf *pkt)\n{\n\tstruct rte_sched_queue *q;\n#ifdef RTE_SCHED_COLLECT_STATS\n\tstruct rte_sched_queue_extra *qe;\n#endif\n\tuint32_t subport, pipe, traffic_class, queue, qindex;\n\n\trte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);\n\n\tqindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);\n\tq = port->queue + qindex;\n\trte_prefetch0(q);\n#ifdef RTE_SCHED_COLLECT_STATS\n\tqe = port->queue_extra + qindex;\n\trte_prefetch0(qe);\n#endif\n\n\treturn qindex;\n}\n\nstatic inline void\nrte_sched_port_enqueue_qwa_prefetch0(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase)\n{\n\tstruct rte_sched_queue *q;\n\tstruct rte_mbuf **q_qw;\n\tuint16_t qsize;\n\n\tq = port->queue + qindex;\n\tqsize = rte_sched_port_qsize(port, qindex);\n\tq_qw = qbase + (q->qw & (qsize - 1));\n\n\trte_prefetch0(q_qw);\n\trte_bitmap_prefetch0(port->bmp, qindex);\n}\n\nstatic inline int\nrte_sched_port_enqueue_qwa(struct rte_sched_port *port, uint32_t qindex, struct rte_mbuf **qbase, struct rte_mbuf *pkt)\n{\n\tstruct rte_sched_queue *q;\n\tuint16_t qsize;\n\tuint16_t qlen;\n\n\tq = port->queue + qindex;\n\tqsize = rte_sched_port_qsize(port, qindex);\n\tqlen = q->qw - q->qr;\n\n\t/* Drop the packet (and update drop stats) when queue is full */\n\tif (unlikely(rte_sched_port_red_drop(port, pkt, qindex, qlen) || (qlen >= qsize))) {\n\t\trte_pktmbuf_free(pkt);\n#ifdef RTE_SCHED_COLLECT_STATS\n\t\trte_sched_port_update_subport_stats_on_drop(port, qindex, pkt);\n\t\trte_sched_port_update_queue_stats_on_drop(port, qindex, pkt);\n#endif\n\t\treturn 0;\n\t}\n\n\t/* Enqueue packet */\n\tqbase[q->qw & (qsize - 1)] = pkt;\n\tq->qw ++;\n\n\t/* Activate queue in the port bitmap */\n\trte_bitmap_set(port->bmp, qindex);\n\n\t/* Statistics */\n#ifdef RTE_SCHED_COLLECT_STATS\n\trte_sched_port_update_subport_stats(port, qindex, pkt);\n\trte_sched_port_update_queue_stats(port, qindex, pkt);\n#endif\n\n\treturn 1;\n}\n\n#if RTE_SCHED_ENQUEUE == 0\n\nint\nrte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)\n{\n\tuint32_t result, i;\n\n\tresult = 0;\n\n\tfor (i = 0; i < n_pkts; i ++) {\n\t\tstruct rte_mbuf *pkt;\n\t\tstruct rte_mbuf **q_base;\n\t\tuint32_t subport, pipe, traffic_class, queue, qindex;\n\n\t\tpkt = pkts[i];\n\n\t\trte_sched_port_pkt_read_tree_path(pkt, &subport, &pipe, &traffic_class, &queue);\n\n\t\tqindex = rte_sched_port_qindex(port, subport, pipe, traffic_class, queue);\n\n\t\tq_base = rte_sched_port_qbase(port, qindex);\n\n\t\tresult += rte_sched_port_enqueue_qwa(port, qindex, q_base, pkt);\n\t}\n\n\treturn result;\n}\n\n#else\n\n/* The enqueue function implements a 4-level pipeline with each stage processing\n * two different packets. The purpose of using a pipeline is to hide the latency\n * of prefetching the data structures. The naming convention is presented in the\n * diagram below:\n *\n * p00 _______ p10 _______ p20 _______ p30 _______\n * ----->| |----->| |----->| |----->| |----->\n * | 0 | | 1 | | 2 | | 3 |\n * ----->|_______|----->|_______|----->|_______|----->|_______|----->\n * p01 p11 p21 p31\n *\n ***/\nint\nrte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)\n{\n\tstruct rte_mbuf *pkt00, *pkt01, *pkt10, *pkt11, *pkt20, *pkt21, *pkt30, *pkt31, *pkt_last;\n\tstruct rte_mbuf **q00_base, **q01_base, **q10_base, **q11_base, **q20_base, **q21_base, **q30_base, **q31_base, **q_last_base;\n\tuint32_t q00, q01, q10, q11, q20, q21, q30, q31, q_last;\n\tuint32_t r00, r01, r10, r11, r20, r21, r30, r31, r_last;\n\tuint32_t result, i;\n\n\tresult = 0;\n\n\t/* Less then 6 input packets available, which is not enough to feed the pipeline */\n\tif (unlikely(n_pkts < 6)) {\n\t\tstruct rte_mbuf **q_base[5];\n\t\tuint32_t q[5];\n\n\t\t/* Prefetch the mbuf structure of each packet */\n\t\tfor (i = 0; i < n_pkts; i ++) {\n\t\t\trte_prefetch0(pkts[i]);\n\t\t}\n\n\t\t/* Prefetch the queue structure for each queue */\n\t\tfor (i = 0; i < n_pkts; i ++) {\n\t\t\tq[i] = rte_sched_port_enqueue_qptrs_prefetch0(port, pkts[i]);\n\t\t}\n\n\t\t/* Prefetch the write pointer location of each queue */\n\t\tfor (i = 0; i < n_pkts; i ++) {\n\t\t\tq_base[i] = rte_sched_port_qbase(port, q[i]);\n\t\t\trte_sched_port_enqueue_qwa_prefetch0(port, q[i], q_base[i]);\n\t\t}\n\n\t\t/* Write each packet to its queue */\n\t\tfor (i = 0; i < n_pkts; i ++) {\n\t\t\tresult += rte_sched_port_enqueue_qwa(port, q[i], q_base[i], pkts[i]);\n\t\t}\n\n\t\treturn result;\n\t}\n\n\t/* Feed the first 3 stages of the pipeline (6 packets needed) */\n\tpkt20 = pkts[0];\n\tpkt21 = pkts[1];\n\trte_prefetch0(pkt20);\n\trte_prefetch0(pkt21);\n\n\tpkt10 = pkts[2];\n\tpkt11 = pkts[3];\n\trte_prefetch0(pkt10);\n\trte_prefetch0(pkt11);\n\n\tq20 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt20);\n\tq21 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt21);\n\n\tpkt00 = pkts[4];\n\tpkt01 = pkts[5];\n\trte_prefetch0(pkt00);\n\trte_prefetch0(pkt01);\n\n\tq10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);\n\tq11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);\n\n\tq20_base = rte_sched_port_qbase(port, q20);\n\tq21_base = rte_sched_port_qbase(port, q21);\n\trte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);\n\trte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);\n\n\t/* Run the pipeline */\n\tfor (i = 6; i < (n_pkts & (~1)); i += 2) {\n\t\t/* Propagate stage inputs */\n\t\tpkt30 = pkt20;\n\t\tpkt31 = pkt21;\n\t\tpkt20 = pkt10;\n\t\tpkt21 = pkt11;\n\t\tpkt10 = pkt00;\n\t\tpkt11 = pkt01;\n\t\tq30 = q20;\n\t\tq31 = q21;\n\t\tq20 = q10;\n\t\tq21 = q11;\n\t\tq30_base = q20_base;\n\t\tq31_base = q21_base;\n\n\t\t/* Stage 0: Get packets in */\n\t\tpkt00 = pkts[i];\n\t\tpkt01 = pkts[i + 1];\n\t\trte_prefetch0(pkt00);\n\t\trte_prefetch0(pkt01);\n\n\t\t/* Stage 1: Prefetch queue structure storing queue pointers */\n\t\tq10 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt10);\n\t\tq11 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt11);\n\n\t\t/* Stage 2: Prefetch queue write location */\n\t\tq20_base = rte_sched_port_qbase(port, q20);\n\t\tq21_base = rte_sched_port_qbase(port, q21);\n\t\trte_sched_port_enqueue_qwa_prefetch0(port, q20, q20_base);\n\t\trte_sched_port_enqueue_qwa_prefetch0(port, q21, q21_base);\n\n\t\t/* Stage 3: Write packet to queue and activate queue */\n\t\tr30 = rte_sched_port_enqueue_qwa(port, q30, q30_base, pkt30);\n\t\tr31 = rte_sched_port_enqueue_qwa(port, q31, q31_base, pkt31);\n\t\tresult += r30 + r31;\n\t}\n\n\t/* Drain the pipeline (exactly 6 packets). Handle the last packet in the case\n\tof an odd number of input packets. */\n\tpkt_last = pkts[n_pkts - 1];\n\trte_prefetch0(pkt_last);\n\n\tq00 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt00);\n\tq01 = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt01);\n\n\tq10_base = rte_sched_port_qbase(port, q10);\n\tq11_base = rte_sched_port_qbase(port, q11);\n\trte_sched_port_enqueue_qwa_prefetch0(port, q10, q10_base);\n\trte_sched_port_enqueue_qwa_prefetch0(port, q11, q11_base);\n\n\tr20 = rte_sched_port_enqueue_qwa(port, q20, q20_base, pkt20);\n\tr21 = rte_sched_port_enqueue_qwa(port, q21, q21_base, pkt21);\n\tresult += r20 + r21;\n\n\tq_last = rte_sched_port_enqueue_qptrs_prefetch0(port, pkt_last);\n\n\tq00_base = rte_sched_port_qbase(port, q00);\n\tq01_base = rte_sched_port_qbase(port, q01);\n\trte_sched_port_enqueue_qwa_prefetch0(port, q00, q00_base);\n\trte_sched_port_enqueue_qwa_prefetch0(port, q01, q01_base);\n\n\tr10 = rte_sched_port_enqueue_qwa(port, q10, q10_base, pkt10);\n\tr11 = rte_sched_port_enqueue_qwa(port, q11, q11_base, pkt11);\n\tresult += r10 + r11;\n\n\tq_last_base = rte_sched_port_qbase(port, q_last);\n\trte_sched_port_enqueue_qwa_prefetch0(port, q_last, q_last_base);\n\n\tr00 = rte_sched_port_enqueue_qwa(port, q00, q00_base, pkt00);\n\tr01 = rte_sched_port_enqueue_qwa(port, q01, q01_base, pkt01);\n\tresult += r00 + r01;\n\n\tif (n_pkts & 1) {\n\t\tr_last = rte_sched_port_enqueue_qwa(port, q_last, q_last_base, pkt_last);\n\t\tresult += r_last;\n\t}\n\n\treturn result;\n}\n\n#endif /* RTE_SCHED_ENQUEUE */\n\n#if RTE_SCHED_TS_CREDITS_UPDATE == 0\n\n#define grinder_credits_update(port, pos)\n\n#elif !defined(RTE_SCHED_SUBPORT_TC_OV)\n\nstatic inline void\ngrinder_credits_update(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tstruct rte_sched_subport *subport = grinder->subport;\n\tstruct rte_sched_pipe *pipe = grinder->pipe;\n\tstruct rte_sched_pipe_profile *params = grinder->pipe_params;\n\tuint64_t n_periods;\n\n\t/* Subport TB */\n\tn_periods = (port->time - subport->tb_time) / subport->tb_period;\n\tsubport->tb_credits += n_periods * subport->tb_credits_per_period;\n\tsubport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);\n\tsubport->tb_time += n_periods * subport->tb_period;\n\n\t/* Pipe TB */\n\tn_periods = (port->time - pipe->tb_time) / params->tb_period;\n\tpipe->tb_credits += n_periods * params->tb_credits_per_period;\n\tpipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);\n\tpipe->tb_time += n_periods * params->tb_period;\n\n\t/* Subport TCs */\n\tif (unlikely(port->time >= subport->tc_time)) {\n\t\tsubport->tc_credits[0] = subport->tc_credits_per_period[0];\n\t\tsubport->tc_credits[1] = subport->tc_credits_per_period[1];\n\t\tsubport->tc_credits[2] = subport->tc_credits_per_period[2];\n\t\tsubport->tc_credits[3] = subport->tc_credits_per_period[3];\n\t\tsubport->tc_time = port->time + subport->tc_period;\n\t}\n\n\t/* Pipe TCs */\n\tif (unlikely(port->time >= pipe->tc_time)) {\n\t\tpipe->tc_credits[0] = params->tc_credits_per_period[0];\n\t\tpipe->tc_credits[1] = params->tc_credits_per_period[1];\n\t\tpipe->tc_credits[2] = params->tc_credits_per_period[2];\n\t\tpipe->tc_credits[3] = params->tc_credits_per_period[3];\n\t\tpipe->tc_time = port->time + params->tc_period;\n\t}\n}\n\n#else\n\nstatic inline uint32_t\ngrinder_tc_ov_credits_update(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tstruct rte_sched_subport *subport = grinder->subport;\n\tuint32_t tc_ov_consumption[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n\tuint32_t tc_ov_consumption_max;\n\tuint32_t tc_ov_wm = subport->tc_ov_wm;\n\n\tif (subport->tc_ov == 0) {\n\t\treturn subport->tc_ov_wm_max;\n\t}\n\n\ttc_ov_consumption[0] = subport->tc_credits_per_period[0] - subport->tc_credits[0];\n\ttc_ov_consumption[1] = subport->tc_credits_per_period[1] - subport->tc_credits[1];\n\ttc_ov_consumption[2] = subport->tc_credits_per_period[2] - subport->tc_credits[2];\n\ttc_ov_consumption[3] = subport->tc_credits_per_period[3] - subport->tc_credits[3];\n\n\ttc_ov_consumption_max = subport->tc_credits_per_period[3] -\n\t\t(tc_ov_consumption[0] + tc_ov_consumption[1] + tc_ov_consumption[2]);\n\n\tif (tc_ov_consumption[3] > (tc_ov_consumption_max - port->mtu)) {\n\t\ttc_ov_wm -= tc_ov_wm >> 7;\n\t\tif (tc_ov_wm < subport->tc_ov_wm_min) {\n\t\t\ttc_ov_wm = subport->tc_ov_wm_min;\n\t\t}\n\t\treturn tc_ov_wm;\n\t}\n\n\ttc_ov_wm += (tc_ov_wm >> 7) + 1;\n\tif (tc_ov_wm > subport->tc_ov_wm_max) {\n\t\ttc_ov_wm = subport->tc_ov_wm_max;\n\t}\n\treturn tc_ov_wm;\n}\n\nstatic inline void\ngrinder_credits_update(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tstruct rte_sched_subport *subport = grinder->subport;\n\tstruct rte_sched_pipe *pipe = grinder->pipe;\n\tstruct rte_sched_pipe_profile *params = grinder->pipe_params;\n\tuint64_t n_periods;\n\n\t/* Subport TB */\n\tn_periods = (port->time - subport->tb_time) / subport->tb_period;\n\tsubport->tb_credits += n_periods * subport->tb_credits_per_period;\n\tsubport->tb_credits = rte_sched_min_val_2_u32(subport->tb_credits, subport->tb_size);\n\tsubport->tb_time += n_periods * subport->tb_period;\n\n\t/* Pipe TB */\n\tn_periods = (port->time - pipe->tb_time) / params->tb_period;\n\tpipe->tb_credits += n_periods * params->tb_credits_per_period;\n\tpipe->tb_credits = rte_sched_min_val_2_u32(pipe->tb_credits, params->tb_size);\n\tpipe->tb_time += n_periods * params->tb_period;\n\n\t/* Subport TCs */\n\tif (unlikely(port->time >= subport->tc_time)) {\n\t\tsubport->tc_ov_wm = grinder_tc_ov_credits_update(port, pos);\n\n\t\tsubport->tc_credits[0] = subport->tc_credits_per_period[0];\n\t\tsubport->tc_credits[1] = subport->tc_credits_per_period[1];\n\t\tsubport->tc_credits[2] = subport->tc_credits_per_period[2];\n\t\tsubport->tc_credits[3] = subport->tc_credits_per_period[3];\n\n\t\tsubport->tc_time = port->time + subport->tc_period;\n\t\tsubport->tc_ov_period_id ++;\n\t}\n\n\t/* Pipe TCs */\n\tif (unlikely(port->time >= pipe->tc_time)) {\n\t\tpipe->tc_credits[0] = params->tc_credits_per_period[0];\n\t\tpipe->tc_credits[1] = params->tc_credits_per_period[1];\n\t\tpipe->tc_credits[2] = params->tc_credits_per_period[2];\n\t\tpipe->tc_credits[3] = params->tc_credits_per_period[3];\n\t\tpipe->tc_time = port->time + params->tc_period;\n\t}\n\n\t/* Pipe TCs - Oversubscription */\n\tif (unlikely(pipe->tc_ov_period_id != subport->tc_ov_period_id)) {\n\t\tpipe->tc_ov_credits = subport->tc_ov_wm * params->tc_ov_weight;\n\n\t\tpipe->tc_ov_period_id = subport->tc_ov_period_id;\n\t}\n}\n\n#endif /* RTE_SCHED_TS_CREDITS_UPDATE, RTE_SCHED_SUBPORT_TC_OV */\n\n#if RTE_SCHED_TS_CREDITS_CHECK\n\n#ifndef RTE_SCHED_SUBPORT_TC_OV\n\nstatic inline int\ngrinder_credits_check(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tstruct rte_sched_subport *subport = grinder->subport;\n\tstruct rte_sched_pipe *pipe = grinder->pipe;\n\tstruct rte_mbuf *pkt = grinder->pkt;\n\tuint32_t tc_index = grinder->tc_index;\n\tuint32_t pkt_len = pkt->pkt_len + port->frame_overhead;\n\tuint32_t subport_tb_credits = subport->tb_credits;\n\tuint32_t subport_tc_credits = subport->tc_credits[tc_index];\n\tuint32_t pipe_tb_credits = pipe->tb_credits;\n\tuint32_t pipe_tc_credits = pipe->tc_credits[tc_index];\n\tint enough_credits;\n\n\t/* Check queue credits */\n\tenough_credits = (pkt_len <= subport_tb_credits) &&\n\t\t(pkt_len <= subport_tc_credits) &&\n\t\t(pkt_len <= pipe_tb_credits) &&\n\t\t(pkt_len <= pipe_tc_credits);\n\n\tif (!enough_credits) {\n\t\treturn 0;\n\t}\n\n\t/* Update port credits */\n\tsubport->tb_credits -= pkt_len;\n\tsubport->tc_credits[tc_index] -= pkt_len;\n\tpipe->tb_credits -= pkt_len;\n\tpipe->tc_credits[tc_index] -= pkt_len;\n\n\treturn 1;\n}\n\n#else\n\nstatic inline int\ngrinder_credits_check(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tstruct rte_sched_subport *subport = grinder->subport;\n\tstruct rte_sched_pipe *pipe = grinder->pipe;\n\tstruct rte_mbuf *pkt = grinder->pkt;\n\tuint32_t tc_index = grinder->tc_index;\n\tuint32_t pkt_len = pkt->pkt_len + port->frame_overhead;\n\tuint32_t subport_tb_credits = subport->tb_credits;\n\tuint32_t subport_tc_credits = subport->tc_credits[tc_index];\n\tuint32_t pipe_tb_credits = pipe->tb_credits;\n\tuint32_t pipe_tc_credits = pipe->tc_credits[tc_index];\n\tuint32_t pipe_tc_ov_mask1[] = {UINT32_MAX, UINT32_MAX, UINT32_MAX, pipe->tc_ov_credits};\n\tuint32_t pipe_tc_ov_mask2[] = {0, 0, 0, UINT32_MAX};\n\tuint32_t pipe_tc_ov_credits = pipe_tc_ov_mask1[tc_index];\n\tint enough_credits;\n\n\t/* Check pipe and subport credits */\n\tenough_credits = (pkt_len <= subport_tb_credits) &&\n\t\t(pkt_len <= subport_tc_credits) &&\n\t\t(pkt_len <= pipe_tb_credits) &&\n\t\t(pkt_len <= pipe_tc_credits) &&\n\t\t(pkt_len <= pipe_tc_ov_credits);\n\n\tif (!enough_credits) {\n\t\treturn 0;\n\t}\n\n\t/* Update pipe and subport credits */\n\tsubport->tb_credits -= pkt_len;\n\tsubport->tc_credits[tc_index] -= pkt_len;\n\tpipe->tb_credits -= pkt_len;\n\tpipe->tc_credits[tc_index] -= pkt_len;\n\tpipe->tc_ov_credits -= pipe_tc_ov_mask2[tc_index] & pkt_len;\n\n\treturn 1;\n}\n\n#endif /* RTE_SCHED_SUBPORT_TC_OV */\n\n#endif /* RTE_SCHED_TS_CREDITS_CHECK */\n\nstatic inline int\ngrinder_schedule(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tstruct rte_sched_queue *queue = grinder->queue[grinder->qpos];\n\tstruct rte_mbuf *pkt = grinder->pkt;\n\tuint32_t pkt_len = pkt->pkt_len + port->frame_overhead;\n\n#if RTE_SCHED_TS_CREDITS_CHECK\n\tif (!grinder_credits_check(port, pos)) {\n\t\treturn 0;\n\t}\n#endif\n\n\t/* Advance port time */\n\tport->time += pkt_len;\n\n\t/* Send packet */\n\tport->pkts_out[port->n_pkts_out ++] = pkt;\n\tqueue->qr ++;\n\tgrinder->wrr_tokens[grinder->qpos] += pkt_len * grinder->wrr_cost[grinder->qpos];\n\tif (queue->qr == queue->qw) {\n\t\tuint32_t qindex = grinder->qindex[grinder->qpos];\n\n\t\trte_bitmap_clear(port->bmp, qindex);\n\t\tgrinder->qmask &= ~(1 << grinder->qpos);\n\t\tgrinder->wrr_mask[grinder->qpos] = 0;\n\t\trte_sched_port_set_queue_empty_timestamp(port, qindex);\n\t}\n\n\t/* Reset pipe loop detection */\n\tport->pipe_loop = RTE_SCHED_PIPE_INVALID;\n\tgrinder->productive = 1;\n\n\treturn 1;\n}\n\n#if RTE_SCHED_OPTIMIZATIONS\n\nstatic inline int\ngrinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)\n{\n\t__m128i index = _mm_set1_epi32 (base_pipe);\n\t__m128i pipes = _mm_load_si128((__m128i *)port->grinder_base_bmp_pos);\n\t__m128i res = _mm_cmpeq_epi32(pipes, index);\n\tpipes = _mm_load_si128((__m128i *)(port->grinder_base_bmp_pos + 4));\n\tpipes = _mm_cmpeq_epi32(pipes, index);\n\tres = _mm_or_si128(res, pipes);\n\n\tif (_mm_testz_si128(res, res))\n\t\treturn 0;\n\n\treturn 1;\n}\n\n#else\n\nstatic inline int\ngrinder_pipe_exists(struct rte_sched_port *port, uint32_t base_pipe)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i ++) {\n\t\tif (port->grinder_base_bmp_pos[i] == base_pipe) {\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\n#endif /* RTE_SCHED_OPTIMIZATIONS */\n\nstatic inline void\ngrinder_pcache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t bmp_pos, uint64_t bmp_slab)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tuint16_t w[4];\n\n\tgrinder->pcache_w = 0;\n\tgrinder->pcache_r = 0;\n\n\tw[0] = (uint16_t) bmp_slab;\n\tw[1] = (uint16_t) (bmp_slab >> 16);\n\tw[2] = (uint16_t) (bmp_slab >> 32);\n\tw[3] = (uint16_t) (bmp_slab >> 48);\n\n\tgrinder->pcache_qmask[grinder->pcache_w] = w[0];\n\tgrinder->pcache_qindex[grinder->pcache_w] = bmp_pos;\n\tgrinder->pcache_w += (w[0] != 0);\n\n\tgrinder->pcache_qmask[grinder->pcache_w] = w[1];\n\tgrinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 16;\n\tgrinder->pcache_w += (w[1] != 0);\n\n\tgrinder->pcache_qmask[grinder->pcache_w] = w[2];\n\tgrinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 32;\n\tgrinder->pcache_w += (w[2] != 0);\n\n\tgrinder->pcache_qmask[grinder->pcache_w] = w[3];\n\tgrinder->pcache_qindex[grinder->pcache_w] = bmp_pos + 48;\n\tgrinder->pcache_w += (w[3] != 0);\n}\n\nstatic inline void\ngrinder_tccache_populate(struct rte_sched_port *port, uint32_t pos, uint32_t qindex, uint16_t qmask)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tuint8_t b[4];\n\n\tgrinder->tccache_w = 0;\n\tgrinder->tccache_r = 0;\n\n\tb[0] = (uint8_t) (qmask & 0xF);\n\tb[1] = (uint8_t) ((qmask >> 4) & 0xF);\n\tb[2] = (uint8_t) ((qmask >> 8) & 0xF);\n\tb[3] = (uint8_t) ((qmask >> 12) & 0xF);\n\n\tgrinder->tccache_qmask[grinder->tccache_w] = b[0];\n\tgrinder->tccache_qindex[grinder->tccache_w] = qindex;\n\tgrinder->tccache_w += (b[0] != 0);\n\n\tgrinder->tccache_qmask[grinder->tccache_w] = b[1];\n\tgrinder->tccache_qindex[grinder->tccache_w] = qindex + 4;\n\tgrinder->tccache_w += (b[1] != 0);\n\n\tgrinder->tccache_qmask[grinder->tccache_w] = b[2];\n\tgrinder->tccache_qindex[grinder->tccache_w] = qindex + 8;\n\tgrinder->tccache_w += (b[2] != 0);\n\n\tgrinder->tccache_qmask[grinder->tccache_w] = b[3];\n\tgrinder->tccache_qindex[grinder->tccache_w] = qindex + 12;\n\tgrinder->tccache_w += (b[3] != 0);\n}\n\nstatic inline int\ngrinder_next_tc(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tstruct rte_mbuf **qbase;\n\tuint32_t qindex;\n\tuint16_t qsize;\n\n\tif (grinder->tccache_r == grinder->tccache_w) {\n\t\treturn 0;\n\t}\n\n\tqindex = grinder->tccache_qindex[grinder->tccache_r];\n\tqbase = rte_sched_port_qbase(port, qindex);\n\tqsize = rte_sched_port_qsize(port, qindex);\n\n\tgrinder->tc_index = (qindex >> 2) & 0x3;\n\tgrinder->qmask = grinder->tccache_qmask[grinder->tccache_r];\n\tgrinder->qsize = qsize;\n\n\tgrinder->qindex[0] = qindex;\n\tgrinder->qindex[1] = qindex + 1;\n\tgrinder->qindex[2] = qindex + 2;\n\tgrinder->qindex[3] = qindex + 3;\n\n\tgrinder->queue[0] = port->queue + qindex;\n\tgrinder->queue[1] = port->queue + qindex + 1;\n\tgrinder->queue[2] = port->queue + qindex + 2;\n\tgrinder->queue[3] = port->queue + qindex + 3;\n\n\tgrinder->qbase[0] = qbase;\n\tgrinder->qbase[1] = qbase + qsize;\n\tgrinder->qbase[2] = qbase + 2 * qsize;\n\tgrinder->qbase[3] = qbase + 3 * qsize;\n\n\tgrinder->tccache_r ++;\n\treturn 1;\n}\n\nstatic inline int\ngrinder_next_pipe(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tuint32_t pipe_qindex;\n\tuint16_t pipe_qmask;\n\n\tif (grinder->pcache_r < grinder->pcache_w) {\n\t\tpipe_qmask = grinder->pcache_qmask[grinder->pcache_r];\n\t\tpipe_qindex = grinder->pcache_qindex[grinder->pcache_r];\n\t\tgrinder->pcache_r ++;\n\t} else {\n\t\tuint64_t bmp_slab = 0;\n\t\tuint32_t bmp_pos = 0;\n\n\t\t/* Get another non-empty pipe group */\n\t\tif (unlikely(rte_bitmap_scan(port->bmp, &bmp_pos, &bmp_slab) <= 0)) {\n\t\t\treturn 0;\n\t\t}\n\n#if RTE_SCHED_DEBUG\n\t\tdebug_check_queue_slab(port, bmp_pos, bmp_slab);\n#endif\n\n\t\t/* Return if pipe group already in one of the other grinders */\n\t\tport->grinder_base_bmp_pos[pos] = RTE_SCHED_BMP_POS_INVALID;\n\t\tif (unlikely(grinder_pipe_exists(port, bmp_pos))) {\n\t\t\treturn 0;\n\t\t}\n\t\tport->grinder_base_bmp_pos[pos] = bmp_pos;\n\n\t\t/* Install new pipe group into grinder's pipe cache */\n\t\tgrinder_pcache_populate(port, pos, bmp_pos, bmp_slab);\n\n\t\tpipe_qmask = grinder->pcache_qmask[0];\n\t\tpipe_qindex = grinder->pcache_qindex[0];\n\t\tgrinder->pcache_r = 1;\n\t}\n\n\t/* Install new pipe in the grinder */\n\tgrinder->pindex = pipe_qindex >> 4;\n\tgrinder->subport = port->subport + (grinder->pindex / port->n_pipes_per_subport);\n\tgrinder->pipe = port->pipe + grinder->pindex;\n\tgrinder->pipe_params = NULL; /* to be set after the pipe structure is prefetched */\n\tgrinder->productive = 0;\n\n\tgrinder_tccache_populate(port, pos, pipe_qindex, pipe_qmask);\n\tgrinder_next_tc(port, pos);\n\n\t/* Check for pipe exhaustion */\n\tif (grinder->pindex == port->pipe_loop) {\n\t\tport->pipe_exhaustion = 1;\n\t\tport->pipe_loop = RTE_SCHED_PIPE_INVALID;\n\t}\n\n\treturn 1;\n}\n\n#if RTE_SCHED_WRR == 0\n\n#define grinder_wrr_load(a,b)\n\n#define grinder_wrr_store(a,b)\n\nstatic inline void\ngrinder_wrr(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tuint64_t slab = grinder->qmask;\n\n\tif (rte_bsf64(slab, &grinder->qpos) == 0) {\n\t\trte_panic(\"grinder wrr\\n\");\n\t}\n}\n\n#elif RTE_SCHED_WRR == 1\n\nstatic inline void\ngrinder_wrr_load(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tstruct rte_sched_pipe *pipe = grinder->pipe;\n\tstruct rte_sched_pipe_profile *pipe_params = grinder->pipe_params;\n\tuint32_t tc_index = grinder->tc_index;\n\tuint32_t qmask = grinder->qmask;\n\tuint32_t qindex;\n\n\tqindex = tc_index * 4;\n\n\tgrinder->wrr_tokens[0] = ((uint16_t) pipe->wrr_tokens[qindex]) << RTE_SCHED_WRR_SHIFT;\n\tgrinder->wrr_tokens[1] = ((uint16_t) pipe->wrr_tokens[qindex + 1]) << RTE_SCHED_WRR_SHIFT;\n\tgrinder->wrr_tokens[2] = ((uint16_t) pipe->wrr_tokens[qindex + 2]) << RTE_SCHED_WRR_SHIFT;\n\tgrinder->wrr_tokens[3] = ((uint16_t) pipe->wrr_tokens[qindex + 3]) << RTE_SCHED_WRR_SHIFT;\n\n\tgrinder->wrr_mask[0] = (qmask & 0x1) * 0xFFFF;\n\tgrinder->wrr_mask[1] = ((qmask >> 1) & 0x1) * 0xFFFF;\n\tgrinder->wrr_mask[2] = ((qmask >> 2) & 0x1) * 0xFFFF;\n\tgrinder->wrr_mask[3] = ((qmask >> 3) & 0x1) * 0xFFFF;\n\n\tgrinder->wrr_cost[0] = pipe_params->wrr_cost[qindex];\n\tgrinder->wrr_cost[1] = pipe_params->wrr_cost[qindex + 1];\n\tgrinder->wrr_cost[2] = pipe_params->wrr_cost[qindex + 2];\n\tgrinder->wrr_cost[3] = pipe_params->wrr_cost[qindex + 3];\n}\n\nstatic inline void\ngrinder_wrr_store(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tstruct rte_sched_pipe *pipe = grinder->pipe;\n\tuint32_t tc_index = grinder->tc_index;\n\tuint32_t qindex;\n\n\tqindex = tc_index * 4;\n\n\tpipe->wrr_tokens[qindex] = (uint8_t) ((grinder->wrr_tokens[0] & grinder->wrr_mask[0]) >> RTE_SCHED_WRR_SHIFT);\n\tpipe->wrr_tokens[qindex + 1] = (uint8_t) ((grinder->wrr_tokens[1] & grinder->wrr_mask[1]) >> RTE_SCHED_WRR_SHIFT);\n\tpipe->wrr_tokens[qindex + 2] = (uint8_t) ((grinder->wrr_tokens[2] & grinder->wrr_mask[2]) >> RTE_SCHED_WRR_SHIFT);\n\tpipe->wrr_tokens[qindex + 3] = (uint8_t) ((grinder->wrr_tokens[3] & grinder->wrr_mask[3]) >> RTE_SCHED_WRR_SHIFT);\n}\n\nstatic inline void\ngrinder_wrr(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tuint16_t wrr_tokens_min;\n\n\tgrinder->wrr_tokens[0] |= ~grinder->wrr_mask[0];\n\tgrinder->wrr_tokens[1] |= ~grinder->wrr_mask[1];\n\tgrinder->wrr_tokens[2] |= ~grinder->wrr_mask[2];\n\tgrinder->wrr_tokens[3] |= ~grinder->wrr_mask[3];\n\n\tgrinder->qpos = rte_min_pos_4_u16(grinder->wrr_tokens);\n\twrr_tokens_min = grinder->wrr_tokens[grinder->qpos];\n\n\tgrinder->wrr_tokens[0] -= wrr_tokens_min;\n\tgrinder->wrr_tokens[1] -= wrr_tokens_min;\n\tgrinder->wrr_tokens[2] -= wrr_tokens_min;\n\tgrinder->wrr_tokens[3] -= wrr_tokens_min;\n}\n\n#else\n\n#error Invalid value for RTE_SCHED_WRR\n\n#endif /* RTE_SCHED_WRR */\n\n#define grinder_evict(port, pos)\n\nstatic inline void\ngrinder_prefetch_pipe(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\n\trte_prefetch0(grinder->pipe);\n\trte_prefetch0(grinder->queue[0]);\n}\n\nstatic inline void\ngrinder_prefetch_tc_queue_arrays(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tuint16_t qsize, qr[4];\n\n\tqsize = grinder->qsize;\n\tqr[0] = grinder->queue[0]->qr & (qsize - 1);\n\tqr[1] = grinder->queue[1]->qr & (qsize - 1);\n\tqr[2] = grinder->queue[2]->qr & (qsize - 1);\n\tqr[3] = grinder->queue[3]->qr & (qsize - 1);\n\n\trte_prefetch0(grinder->qbase[0] + qr[0]);\n\trte_prefetch0(grinder->qbase[1] + qr[1]);\n\n\tgrinder_wrr_load(port, pos);\n\tgrinder_wrr(port, pos);\n\n\trte_prefetch0(grinder->qbase[2] + qr[2]);\n\trte_prefetch0(grinder->qbase[3] + qr[3]);\n}\n\nstatic inline void\ngrinder_prefetch_mbuf(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\tuint32_t qpos = grinder->qpos;\n\tstruct rte_mbuf **qbase = grinder->qbase[qpos];\n\tuint16_t qsize = grinder->qsize;\n\tuint16_t qr = grinder->queue[qpos]->qr & (qsize - 1);\n\n\tgrinder->pkt = qbase[qr];\n\trte_prefetch0(grinder->pkt);\n\n\tif (unlikely((qr & 0x7) == 7)) {\n\t\tuint16_t qr_next = (grinder->queue[qpos]->qr + 1) & (qsize - 1);\n\n\t\trte_prefetch0(qbase + qr_next);\n\t}\n}\n\nstatic inline uint32_t\ngrinder_handle(struct rte_sched_port *port, uint32_t pos)\n{\n\tstruct rte_sched_grinder *grinder = port->grinder + pos;\n\n\tswitch (grinder->state) {\n\tcase e_GRINDER_PREFETCH_PIPE:\n\t{\n\t\tif (grinder_next_pipe(port, pos)) {\n\t\t\tgrinder_prefetch_pipe(port, pos);\n\t\t\tport->busy_grinders ++;\n\n\t\t\tgrinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;\n\t\t\treturn 0;\n\t\t}\n\n\t\treturn 0;\n\t}\n\n\tcase e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS:\n\t{\n\t\tstruct rte_sched_pipe *pipe = grinder->pipe;\n\n\t\tgrinder->pipe_params = port->pipe_profiles + pipe->profile;\n\t\tgrinder_prefetch_tc_queue_arrays(port, pos);\n\t\tgrinder_credits_update(port, pos);\n\n\t\tgrinder->state = e_GRINDER_PREFETCH_MBUF;\n\t\treturn 0;\n\t}\n\n\tcase e_GRINDER_PREFETCH_MBUF:\n\t{\n\t\tgrinder_prefetch_mbuf(port, pos);\n\n\t\tgrinder->state = e_GRINDER_READ_MBUF;\n\t\treturn 0;\n\t}\n\n\tcase e_GRINDER_READ_MBUF:\n\t{\n\t\tuint32_t result = 0;\n\n\t\tresult = grinder_schedule(port, pos);\n\n\t\t/* Look for next packet within the same TC */\n\t\tif (result && grinder->qmask) {\n\t\t\tgrinder_wrr(port, pos);\n\t\t\tgrinder_prefetch_mbuf(port, pos);\n\n\t\t\treturn 1;\n\t\t}\n\t\tgrinder_wrr_store(port, pos);\n\n\t\t/* Look for another active TC within same pipe */\n\t\tif (grinder_next_tc(port, pos)) {\n\t\t\tgrinder_prefetch_tc_queue_arrays(port, pos);\n\n\t\t\tgrinder->state = e_GRINDER_PREFETCH_MBUF;\n\t\t\treturn result;\n\t\t}\n\t\tif ((grinder->productive == 0) && (port->pipe_loop == RTE_SCHED_PIPE_INVALID)) {\n\t\t\tport->pipe_loop = grinder->pindex;\n\t\t}\n\t\tgrinder_evict(port, pos);\n\n\t\t/* Look for another active pipe */\n\t\tif (grinder_next_pipe(port, pos)) {\n\t\t\tgrinder_prefetch_pipe(port, pos);\n\n\t\t\tgrinder->state = e_GRINDER_PREFETCH_TC_QUEUE_ARRAYS;\n\t\t\treturn result;\n\t\t}\n\n\t\t/* No active pipe found */\n\t\tport->busy_grinders --;\n\n\t\tgrinder->state = e_GRINDER_PREFETCH_PIPE;\n\t\treturn result;\n\t}\n\n\tdefault:\n\t\trte_panic(\"Algorithmic error (invalid state)\\n\");\n\t\treturn 0;\n\t}\n}\n\nstatic inline void\nrte_sched_port_time_resync(struct rte_sched_port *port)\n{\n\tuint64_t cycles = rte_get_tsc_cycles();\n\tuint64_t cycles_diff = cycles - port->time_cpu_cycles;\n\tdouble bytes_diff = ((double) cycles_diff) / port->cycles_per_byte;\n\n\t/* Advance port time */\n\tport->time_cpu_cycles = cycles;\n\tport->time_cpu_bytes += (uint64_t) bytes_diff;\n\tif (port->time < port->time_cpu_bytes) {\n\t\tport->time = port->time_cpu_bytes;\n\t}\n\n\t/* Reset pipe loop detection */\n\tport->pipe_loop = RTE_SCHED_PIPE_INVALID;\n}\n\nstatic inline int\nrte_sched_port_exceptions(struct rte_sched_port *port, int second_pass)\n{\n\tint exceptions;\n\n\t/* Check if any exception flag is set */\n\texceptions = (second_pass && port->busy_grinders == 0) ||\n\t\t(port->pipe_exhaustion == 1);\n\n\t/* Clear exception flags */\n\tport->pipe_exhaustion = 0;\n\n\treturn exceptions;\n}\n\nint\nrte_sched_port_dequeue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts)\n{\n\tuint32_t i, count;\n\n\tport->pkts_out = pkts;\n\tport->n_pkts_out = 0;\n\n\trte_sched_port_time_resync(port);\n\n\t/* Take each queue in the grinder one step further */\n\tfor (i = 0, count = 0; ; i ++) {\n\t\tcount += grinder_handle(port, i & (RTE_SCHED_PORT_N_GRINDERS - 1));\n\t\tif ((count == n_pkts) ||\n\t\t rte_sched_port_exceptions(port, i >= RTE_SCHED_PORT_N_GRINDERS)) {\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn count;\n}\n" }, { "path": "lib/librte_sched/rte_sched.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_SCHED_H__\n#define __INCLUDE_RTE_SCHED_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Hierarchical Scheduler\n *\n * The hierarchical scheduler prioritizes the transmission of packets from different\n * users and traffic classes according to the Service Level Agreements (SLAs) defined\n * for the current network node.\n *\n * The scheduler supports thousands of packet queues grouped under a 5-level hierarchy:\n * 1. Port:\n * - Typical usage: output Ethernet port;\n * - Multiple ports are scheduled in round robin order with equal priority;\n * 2. Subport:\n * - Typical usage: group of users;\n * - Traffic shaping using the token bucket algorithm (one bucket per subport);\n * - Upper limit enforced per traffic class at subport level;\n * - Lower priority traffic classes able to reuse subport bandwidth currently\n * unused by higher priority traffic classes of the same subport;\n * - When any subport traffic class is oversubscribed (configuration time\n * event), the usage of subport member pipes with high demand for that\n * traffic class pipes is truncated to a dynamically adjusted value with no\n * impact to low demand pipes;\n * 3. Pipe:\n * - Typical usage: individual user/subscriber;\n * - Traffic shaping using the token bucket algorithm (one bucket per pipe);\n * 4. Traffic class:\n * - Traffic classes of the same pipe handled in strict priority order;\n * - Upper limit enforced per traffic class at the pipe level;\n * - Lower priority traffic classes able to reuse pipe bandwidth currently\n * unused by higher priority traffic classes of the same pipe;\n * 5. Queue:\n * - Typical usage: queue hosting packets from one or multiple connections\n * of same traffic class belonging to the same user;\n * - Weighted Round Robin (WRR) is used to service the queues within same\n * pipe traffic class.\n *\n ***/\n\n#include \n#include \n#include \n\n/** Random Early Detection (RED) */\n#ifdef RTE_SCHED_RED\n#include \"rte_red.h\"\n#endif\n\n/** Number of traffic classes per pipe (as well as subport). Cannot be changed. */\n#define RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE 4\n\n/** Number of queues per pipe traffic class. Cannot be changed. */\n#define RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS 4\n\n/** Number of queues per pipe. */\n#define RTE_SCHED_QUEUES_PER_PIPE \\\n\t(RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE * \\\n\tRTE_SCHED_QUEUES_PER_TRAFFIC_CLASS)\n\n/** Maximum number of pipe profiles that can be defined per port. Compile-time configurable.*/\n#ifndef RTE_SCHED_PIPE_PROFILES_PER_PORT\n#define RTE_SCHED_PIPE_PROFILES_PER_PORT 256\n#endif\n\n/** Ethernet framing overhead. Overhead fields per Ethernet frame:\n 1. Preamble: 7 bytes;\n 2. Start of Frame Delimiter (SFD): 1 byte;\n 3. Frame Check Sequence (FCS): 4 bytes;\n 4. Inter Frame Gap (IFG): 12 bytes.\nThe FCS is considered overhead only if not included in the packet length (field pkt_len\nof struct rte_mbuf). */\n#ifndef RTE_SCHED_FRAME_OVERHEAD_DEFAULT\n#define RTE_SCHED_FRAME_OVERHEAD_DEFAULT 24\n#endif\n\n/** Subport configuration parameters. The period and credits_per_period parameters are measured\nin bytes, with one byte meaning the time duration associated with the transmission of one byte\non the physical medium of the output port, with pipe or pipe traffic class rate (measured as\npercentage of output port rate) determined as credits_per_period divided by period. One credit\nrepresents one byte. */\nstruct rte_sched_subport_params {\n\t/* Subport token bucket */\n\tuint32_t tb_rate; /**< Subport token bucket rate (measured in bytes per second) */\n\tuint32_t tb_size; /**< Subport token bucket size (measured in credits) */\n\n\t/* Subport traffic classes */\n\tuint32_t tc_rate[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; /**< Subport traffic class rates (measured in bytes per second) */\n\tuint32_t tc_period; /**< Enforcement period for traffic class rates (measured in milliseconds) */\n};\n\n/** Subport statistics */\nstruct rte_sched_subport_stats {\n\t/* Packets */\n\tuint32_t n_pkts_tc[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; /**< Number of packets successfully written to current\n\t subport for each traffic class */\n\tuint32_t n_pkts_tc_dropped[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; /**< Number of packets dropped by the current\n\t subport for each traffic class due to subport queues being full or congested*/\n\n\t/* Bytes */\n\tuint32_t n_bytes_tc[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; /**< Number of bytes successfully written to current\n\t subport for each traffic class*/\n\tuint32_t n_bytes_tc_dropped[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; /**< Number of bytes dropped by the current\n subport for each traffic class due to subport queues being full or congested */\n};\n\n/** Pipe configuration parameters. The period and credits_per_period parameters are measured\nin bytes, with one byte meaning the time duration associated with the transmission of one byte\non the physical medium of the output port, with pipe or pipe traffic class rate (measured as\npercentage of output port rate) determined as credits_per_period divided by period. One credit\nrepresents one byte. */\nstruct rte_sched_pipe_params {\n\t/* Pipe token bucket */\n\tuint32_t tb_rate; /**< Pipe token bucket rate (measured in bytes per second) */\n\tuint32_t tb_size; /**< Pipe token bucket size (measured in credits) */\n\n\t/* Pipe traffic classes */\n\tuint32_t tc_rate[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; /**< Pipe traffic class rates (measured in bytes per second) */\n\tuint32_t tc_period; /**< Enforcement period for pipe traffic class rates (measured in milliseconds) */\n#ifdef RTE_SCHED_SUBPORT_TC_OV\n\tuint8_t tc_ov_weight; /**< Weight for the current pipe in the event of subport traffic class 3 oversubscription */\n#endif\n\n\t/* Pipe queues */\n\tuint8_t wrr_weights[RTE_SCHED_QUEUES_PER_PIPE]; /**< WRR weights for the queues of the current pipe */\n};\n\n/** Queue statistics */\nstruct rte_sched_queue_stats {\n\t/* Packets */\n\tuint32_t n_pkts; /**< Number of packets successfully written to current queue */\n\tuint32_t n_pkts_dropped; /**< Number of packets dropped due to current queue being full or congested */\n\n\t/* Bytes */\n\tuint32_t n_bytes; /**< Number of bytes successfully written to current queue */\n\tuint32_t n_bytes_dropped; /**< Number of bytes dropped due to current queue being full or congested */\n};\n\n/** Port configuration parameters. */\nstruct rte_sched_port_params {\n\tconst char *name; /**< Literal string to be associated to the current port scheduler instance */\n\tint socket; /**< CPU socket ID where the memory for port scheduler should be allocated */\n\tuint32_t rate; /**< Output port rate (measured in bytes per second) */\n\tuint32_t mtu; /**< Maximum Ethernet frame size (measured in bytes). Should not include the framing overhead. */\n\tuint32_t frame_overhead; /**< Framing overhead per packet (measured in bytes) */\n\tuint32_t n_subports_per_port; /**< Number of subports for the current port scheduler instance*/\n\tuint32_t n_pipes_per_subport; /**< Number of pipes for each port scheduler subport */\n\tuint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; /**< Packet queue size for each traffic class. All queues\n\t within the same pipe traffic class have the same size. Queues from\n\t\t\t\t\t\t\t\t\t\t different pipes serving the same traffic class have the same size. */\n\tstruct rte_sched_pipe_params *pipe_profiles; /**< Pipe profile table defined for current port scheduler instance.\n Every pipe of the current port scheduler is configured using one of the\n\t\t\t\t\t\t\t\t\t\t profiles from this table. */\n\tuint32_t n_pipe_profiles; /**< Number of profiles in the pipe profile table */\n#ifdef RTE_SCHED_RED\n\tstruct rte_red_params red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][e_RTE_METER_COLORS]; /**< RED parameters */\n#endif\n};\n\n/*\n * Path through scheduler hierarchy\n *\n * Note: direct access to internal bitfields is deprecated to allow for future expansion.\n * Use rte_sched_port_pkt_read/write API instead\n */\nstruct rte_sched_port_hierarchy {\n\tuint32_t queue:2; /**< Queue ID (0 .. 3) */\n\tuint32_t traffic_class:2; /**< Traffic class ID (0 .. 3)*/\n\tuint32_t pipe:20; /**< Pipe ID */\n\tuint32_t subport:6; /**< Subport ID */\n\tuint32_t color:2; /**< Color */\n} __attribute__ ((deprecated));\n\n/*\n * Configuration\n *\n ***/\n\n/**\n * Hierarchical scheduler port configuration\n *\n * @param params\n * Port scheduler configuration parameter structure\n * @return\n * Handle to port scheduler instance upon success or NULL otherwise.\n */\nstruct rte_sched_port *\nrte_sched_port_config(struct rte_sched_port_params *params);\n\n/**\n * Hierarchical scheduler port free\n *\n * @param port\n * Handle to port scheduler instance\n */\nvoid\nrte_sched_port_free(struct rte_sched_port *port);\n\n/**\n * Hierarchical scheduler subport configuration\n *\n * @param port\n * Handle to port scheduler instance\n * @param subport_id\n * Subport ID\n * @param params\n * Subport configuration parameters\n * @return\n * 0 upon success, error code otherwise\n */\nint\nrte_sched_subport_config(struct rte_sched_port *port,\n\tuint32_t subport_id,\n\tstruct rte_sched_subport_params *params);\n\n/**\n * Hierarchical scheduler pipe configuration\n *\n * @param port\n * Handle to port scheduler instance\n * @param subport_id\n * Subport ID\n * @param pipe_id\n * Pipe ID within subport\n * @param pipe_profile\n * ID of port-level pre-configured pipe profile\n * @return\n * 0 upon success, error code otherwise\n */\nint\nrte_sched_pipe_config(struct rte_sched_port *port,\n\tuint32_t subport_id,\n\tuint32_t pipe_id,\n\tint32_t pipe_profile);\n\n/**\n * Hierarchical scheduler memory footprint size per port\n *\n * @param params\n * Port scheduler configuration parameter structure\n * @return\n * Memory footprint size in bytes upon success, 0 otherwise\n */\nuint32_t\nrte_sched_port_get_memory_footprint(struct rte_sched_port_params *params);\n\n/*\n * Statistics\n *\n ***/\n\n/**\n * Hierarchical scheduler subport statistics read\n *\n * @param port\n * Handle to port scheduler instance\n * @param subport_id\n * Subport ID\n * @param stats\n * Pointer to pre-allocated subport statistics structure where the statistics\n * counters should be stored\n * @param tc_ov\n * Pointer to pre-allocated 4-entry array where the oversubscription status for\n * each of the 4 subport traffic classes should be stored.\n * @return\n * 0 upon success, error code otherwise\n */\nint\nrte_sched_subport_read_stats(struct rte_sched_port *port,\n\tuint32_t subport_id,\n\tstruct rte_sched_subport_stats *stats,\n\tuint32_t *tc_ov);\n\n/**\n * Hierarchical scheduler queue statistics read\n *\n * @param port\n * Handle to port scheduler instance\n * @param queue_id\n * Queue ID within port scheduler\n * @param stats\n * Pointer to pre-allocated subport statistics structure where the statistics\n * counters should be stored\n * @param qlen\n * Pointer to pre-allocated variable where the current queue length should be stored.\n * @return\n * 0 upon success, error code otherwise\n */\nint\nrte_sched_queue_read_stats(struct rte_sched_port *port,\n\tuint32_t queue_id,\n\tstruct rte_sched_queue_stats *stats,\n\tuint16_t *qlen);\n\n/**\n * Scheduler hierarchy path write to packet descriptor. Typically called by the\n * packet classification stage.\n *\n * @param pkt\n * Packet descriptor handle\n * @param subport\n * Subport ID\n * @param pipe\n * Pipe ID within subport\n * @param traffic_class\n * Traffic class ID within pipe (0 .. 3)\n * @param queue\n * Queue ID within pipe traffic class (0 .. 3)\n * @param color\n * Packet color set\n */\nvoid\nrte_sched_port_pkt_write(struct rte_mbuf *pkt,\n\t\t\t uint32_t subport, uint32_t pipe, uint32_t traffic_class,\n\t\t\t uint32_t queue, enum rte_meter_color color);\n\n/**\n * Scheduler hierarchy path read from packet descriptor (struct rte_mbuf). Typically\n * called as part of the hierarchical scheduler enqueue operation. The subport,\n * pipe, traffic class and queue parameters need to be pre-allocated by the caller.\n *\n * @param pkt\n * Packet descriptor handle\n * @param subport\n * Subport ID\n * @param pipe\n * Pipe ID within subport\n * @param traffic_class\n * Traffic class ID within pipe (0 .. 3)\n * @param queue\n * Queue ID within pipe traffic class (0 .. 3)\n *\n */\nvoid\nrte_sched_port_pkt_read_tree_path(const struct rte_mbuf *pkt,\n\t\t\t\t uint32_t *subport, uint32_t *pipe,\n\t\t\t\t uint32_t *traffic_class, uint32_t *queue);\n\nenum rte_meter_color\nrte_sched_port_pkt_read_color(const struct rte_mbuf *pkt);\n\n/**\n * Hierarchical scheduler port enqueue. Writes up to n_pkts to port scheduler and\n * returns the number of packets actually written. For each packet, the port scheduler\n * queue to write the packet to is identified by reading the hierarchy path from the\n * packet descriptor; if the queue is full or congested and the packet is not written\n * to the queue, then the packet is automatically dropped without any action required\n * from the caller.\n *\n * @param port\n * Handle to port scheduler instance\n * @param pkts\n * Array storing the packet descriptor handles\n * @param n_pkts\n * Number of packets to enqueue from the pkts array into the port scheduler\n * @return\n * Number of packets successfully enqueued\n */\nint\nrte_sched_port_enqueue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts);\n\n/**\n * Hierarchical scheduler port dequeue. Reads up to n_pkts from the port scheduler\n * and stores them in the pkts array and returns the number of packets actually read.\n * The pkts array needs to be pre-allocated by the caller with at least n_pkts entries.\n *\n * @param port\n * Handle to port scheduler instance\n * @param pkts\n * Pre-allocated packet descriptor array where the packets dequeued from the port\n * scheduler should be stored\n * @param n_pkts\n * Number of packets to dequeue from the port scheduler\n * @return\n * Number of packets successfully dequeued and placed in the pkts array\n */\nint\nrte_sched_port_dequeue(struct rte_sched_port *port, struct rte_mbuf **pkts, uint32_t n_pkts);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __INCLUDE_RTE_SCHED_H__ */\n" }, { "path": "lib/librte_sched/rte_sched_common.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_SCHED_COMMON_H__\n#define __INCLUDE_RTE_SCHED_COMMON_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n#define __rte_aligned_16 __attribute__((__aligned__(16)))\n\nstatic inline uint32_t\nrte_sched_min_val_2_u32(uint32_t x, uint32_t y)\n{\n\treturn (x < y)? x : y;\n}\n\n#if 0\nstatic inline uint32_t\nrte_min_pos_4_u16(uint16_t *x)\n{\n\tuint32_t pos0, pos1;\n\n\tpos0 = (x[0] <= x[1])? 0 : 1;\n\tpos1 = (x[2] <= x[3])? 2 : 3;\n\n\treturn (x[pos0] <= x[pos1])? pos0 : pos1;\n}\n\n#else\n\n/* simplified version to remove branches with CMOV instruction */\nstatic inline uint32_t\nrte_min_pos_4_u16(uint16_t *x)\n{\n\tuint32_t pos0 = 0;\n\tuint32_t pos1 = 2;\n\n\tif (x[1] <= x[0]) pos0 = 1;\n\tif (x[3] <= x[2]) pos1 = 3;\n\tif (x[pos1] <= x[pos0]) pos0 = pos1;\n\n\treturn pos0;\n}\n\n#endif\n\n/*\n * Compute the Greatest Common Divisor (GCD) of two numbers.\n * This implementation uses Euclid's algorithm:\n * gcd(a, 0) = a\n * gcd(a, b) = gcd(b, a mod b)\n *\n */\nstatic inline uint32_t\nrte_get_gcd(uint32_t a, uint32_t b)\n{\n\tuint32_t c;\n\n\tif (a == 0)\n\t\treturn b;\n\tif (b == 0)\n\t\treturn a;\n\n\tif (a < b) {\n\t\tc = a;\n\t\ta = b;\n\t\tb = c;\n\t}\n\n\twhile (b != 0) {\n\t\tc = a % b;\n\t\ta = b;\n\t\tb = c;\n\t}\n\n\treturn a;\n}\n\n/*\n * Compute the Lowest Common Denominator (LCD) of two numbers.\n * This implementation computes GCD first:\n * LCD(a, b) = (a * b) / GCD(a, b)\n *\n */\nstatic inline uint32_t\nrte_get_lcd(uint32_t a, uint32_t b)\n{\n\treturn (a * b) / rte_get_gcd(a, b);\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __INCLUDE_RTE_SCHED_COMMON_H__ */\n" }, { "path": "lib/librte_table/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n#\n# library name\n#\nLIB = librte_table.a\n\nCFLAGS += -O3\nCFLAGS += $(WERROR_FLAGS)\n\nEXPORT_MAP := rte_table_version.map\n\nLIBABIVER := 1\n\n#\n# all source are stored in SRCS-y\n#\nSRCS-$(CONFIG_RTE_LIBRTE_TABLE) += rte_table_lpm.c\nSRCS-$(CONFIG_RTE_LIBRTE_TABLE) += rte_table_lpm_ipv6.c\nifeq ($(CONFIG_RTE_LIBRTE_ACL),y)\nSRCS-$(CONFIG_RTE_LIBRTE_TABLE) += rte_table_acl.c\nendif\nSRCS-$(CONFIG_RTE_LIBRTE_TABLE) += rte_table_hash_key8.c\nSRCS-$(CONFIG_RTE_LIBRTE_TABLE) += rte_table_hash_key16.c\nSRCS-$(CONFIG_RTE_LIBRTE_TABLE) += rte_table_hash_key32.c\nSRCS-$(CONFIG_RTE_LIBRTE_TABLE) += rte_table_hash_ext.c\nSRCS-$(CONFIG_RTE_LIBRTE_TABLE) += rte_table_hash_lru.c\nSRCS-$(CONFIG_RTE_LIBRTE_TABLE) += rte_table_array.c\nSRCS-$(CONFIG_RTE_LIBRTE_TABLE) += rte_table_stub.c\n\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_table.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_table_lpm.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_table_lpm_ipv6.h\nifeq ($(CONFIG_RTE_LIBRTE_ACL),y)\nSYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_table_acl.h\nendif\nSYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_table_hash.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_lru.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_table_array.h\nSYMLINK-$(CONFIG_RTE_LIBRTE_TABLE)-include += rte_table_stub.h\n\n# this lib depends upon:\nDEPDIRS-$(CONFIG_RTE_LIBRTE_TABLE) := lib/librte_eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_TABLE) += lib/librte_mbuf\nDEPDIRS-$(CONFIG_RTE_LIBRTE_TABLE) += lib/librte_mempool\nDEPDIRS-$(CONFIG_RTE_LIBRTE_TABLE) += lib/librte_port\nDEPDIRS-$(CONFIG_RTE_LIBRTE_TABLE) += lib/librte_lpm\nifeq ($(CONFIG_RTE_LIBRTE_ACL),y)\nDEPDIRS-$(CONFIG_RTE_LIBRTE_TABLE) += lib/librte_acl\nendif\nDEPDIRS-$(CONFIG_RTE_LIBRTE_TABLE) += lib/librte_hash\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_table/rte_lru.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_LRU_H__\n#define __INCLUDE_RTE_LRU_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n#ifdef __INTEL_COMPILER\n#define GCC_VERSION (0)\n#else\n#define GCC_VERSION (__GNUC__ * 10000+__GNUC_MINOR__*100 + __GNUC_PATCHLEVEL__)\n#endif\n\n#ifndef RTE_TABLE_HASH_LRU_STRATEGY\n#ifdef __SSE4_2__\n#define RTE_TABLE_HASH_LRU_STRATEGY 2\n#else /* if no SSE, use simple scalar version */\n#define RTE_TABLE_HASH_LRU_STRATEGY 1\n#endif\n#endif\n\n#ifndef RTE_ARCH_X86_64\n#undef RTE_TABLE_HASH_LRU_STRATEGY\n#define RTE_TABLE_HASH_LRU_STRATEGY 1\n#endif\n\n#if (RTE_TABLE_HASH_LRU_STRATEGY < 0) || (RTE_TABLE_HASH_LRU_STRATEGY > 3)\n#error Invalid value for RTE_TABLE_HASH_LRU_STRATEGY\n#endif\n\n#if RTE_TABLE_HASH_LRU_STRATEGY == 0\n\n#define lru_init(bucket)\t\t\t\t\t\t\\\ndo\t\t\t\t\t\t\t\t\t\\\n\tbucket = bucket;\t\t\t\t\t\t\\\nwhile (0)\n\n#define lru_pos(bucket) (bucket->lru_list & 0xFFFFLLU)\n\n#define lru_update(bucket, mru_val)\t\t\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\tbucket = bucket;\t\t\t\t\t\t\\\n\tmru_val = mru_val;\t\t\t\t\t\t\\\n} while (0)\n\n#elif RTE_TABLE_HASH_LRU_STRATEGY == 1\n\n#define lru_init(bucket)\t\t\t\t\t\t\\\ndo\t\t\t\t\t\t\t\t\t\\\n\tbucket->lru_list = 0x0000000100020003LLU;\t\t\t\\\nwhile (0)\n\n#define lru_pos(bucket) (bucket->lru_list & 0xFFFFLLU)\n\n#define lru_update(bucket, mru_val)\t\t\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\tuint64_t x, pos, x0, x1, x2, mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tx = bucket->lru_list;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tpos = 4;\t\t\t\t\t\t\t\\\n\tif ((x >> 48) == ((uint64_t) mru_val))\t\t\t\t\\\n\t\tpos = 3;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tif (((x >> 32) & 0xFFFFLLU) == ((uint64_t) mru_val))\t\t\\\n\t\tpos = 2;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tif (((x >> 16) & 0xFFFFLLU) == ((uint64_t) mru_val))\t\t\\\n\t\tpos = 1;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tif ((x & 0xFFFFLLU) == ((uint64_t) mru_val))\t\t\t\\\n\t\tpos = 0;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tpos <<= 4;\t\t\t\t\t\t\t\\\n\tmask = (~0LLU) << pos;\t\t\t\t\t\t\\\n\tx0 = x & (~mask);\t\t\t\t\t\t\\\n\tx1 = (x >> 16) & mask;\t\t\t\t\t\t\\\n\tx2 = (x << (48 - pos)) & (0xFFFFLLU << 48);\t\t\t\\\n\tx = x0 | x1 | x2;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tif (pos != 64)\t\t\t\t\t\t\t\\\n\t\tbucket->lru_list = x;\t\t\t\t\t\\\n} while (0)\n\n#elif RTE_TABLE_HASH_LRU_STRATEGY == 2\n\n#if GCC_VERSION > 40306\n#include \n#else\n#include \n#include \n#include \n#endif\n\n#define lru_init(bucket)\t\t\t\t\t\t\\\ndo\t\t\t\t\t\t\t\t\t\\\n\tbucket->lru_list = 0x0000000100020003LLU;\t\t\t\\\nwhile (0)\n\n#define lru_pos(bucket) (bucket->lru_list & 0xFFFFLLU)\n\n#define lru_update(bucket, mru_val)\t\t\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\t/* set up the masks for all possible shuffles, depends on pos */\\\n\tstatic uint64_t masks[10] = {\t\t\t\t\t\\\n\t\t/* Shuffle order; Make Zero (see _mm_shuffle_epi8 manual) */\\\n\t\t0x0100070605040302, 0x8080808080808080,\t\t\t\\\n\t\t0x0302070605040100, 0x8080808080808080,\t\t\t\\\n\t\t0x0504070603020100, 0x8080808080808080,\t\t\t\\\n\t\t0x0706050403020100, 0x8080808080808080,\t\t\t\\\n\t\t0x0706050403020100, 0x8080808080808080};\t\t\\\n\t/* load up one register with repeats of mru-val */\t\t\\\n\tuint64_t mru2 = mru_val;\t\t\t\t\t\\\n\tuint64_t mru3 = mru2 | (mru2 << 16);\t\t\t\t\\\n\tuint64_t lru = bucket->lru_list;\t\t\t\t\\\n\t/* XOR to cause the word we're looking for to go to zero */\t\\\n\tuint64_t mru = lru ^ ((mru3 << 32) | mru3);\t\t\t\\\n\t__m128i c = _mm_cvtsi64_si128(mru);\t\t\t\t\\\n\t__m128i b = _mm_cvtsi64_si128(lru);\t\t\t\t\\\n\t/* Find the minimum value (first zero word, if it's in there) */\\\n\t__m128i d = _mm_minpos_epu16(c);\t\t\t\t\\\n\t/* Second word is the index to found word (first word is the value) */\\\n\tunsigned pos = _mm_extract_epi16(d, 1);\t\t\t\t\\\n\t/* move the recently used location to top of list */\t\t\\\n\t__m128i k = _mm_shuffle_epi8(b, *((__m128i *) &masks[2 * pos]));\\\n\t/* Finally, update the original list with the reordered data */\t\\\n\tbucket->lru_list = _mm_extract_epi64(k, 0);\t\t\t\\\n\t/* Phwew! */\t\t\t\t\t\t\t\\\n} while (0)\n\n#elif RTE_TABLE_HASH_LRU_STRATEGY == 3\n\n#if GCC_VERSION > 40306\n#include \n#else\n#include \n#include \n#include \n#endif\n\n#define lru_init(bucket)\t\t\t\t\t\t\\\ndo\t\t\t\t\t\t\t\t\t\\\n\tbucket->lru_list = ~0LLU;\t\t\t\t\t\\\nwhile (0)\n\n\nstatic inline int\nf_lru_pos(uint64_t lru_list)\n{\n\t__m128i lst = _mm_set_epi64x((uint64_t)-1, lru_list);\n\t__m128i min = _mm_minpos_epu16(lst);\n\treturn _mm_extract_epi16(min, 1);\n}\n#define lru_pos(bucket) f_lru_pos(bucket->lru_list)\n\n#define lru_update(bucket, mru_val)\t\t\t\t\t\\\ndo {\t\t\t\t\t\t\t\t\t\\\n\tconst uint64_t orvals[] = {0xFFFFLLU, 0xFFFFLLU << 16,\t\t\\\n\t\t0xFFFFLLU << 32, 0xFFFFLLU << 48, 0LLU};\t\t\\\n\tconst uint64_t decs[] = {0x1000100010001LLU, 0};\t\t\\\n\t__m128i lru = _mm_cvtsi64_si128(bucket->lru_list);\t\t\\\n\t__m128i vdec = _mm_cvtsi64_si128(decs[mru_val>>2]);\t\t\\\n\tlru = _mm_subs_epu16(lru, vdec);\t\t\t\t\\\n\tbucket->lru_list = _mm_extract_epi64(lru, 0) | orvals[mru_val];\t\\\n} while (0)\n\n#else\n\n#error \"Incorrect value for RTE_TABLE_HASH_LRU_STRATEGY\"\n\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_table/rte_table.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_TABLE_H__\n#define __INCLUDE_RTE_TABLE_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Table\n *\n * This tool is part of the Intel DPDK Packet Framework tool suite and provides\n * a standard interface to implement different types of lookup tables for data\n * plane processing.\n *\n * Virtually any search algorithm that can uniquely associate data to a lookup\n * key can be fitted under this lookup table abstraction. For the flow table\n * use-case, the lookup key is an n-tuple of packet fields that uniquely\n * identifies a traffic flow, while data represents actions and action\n * meta-data associated with the same traffic flow.\n *\n ***/\n\n#include \n#include \n\nstruct rte_mbuf;\n\n/** Lookup table statistics */\nstruct rte_table_stats {\n\tuint64_t n_pkts_in;\n\tuint64_t n_pkts_lookup_miss;\n};\n\n/**\n * Lookup table create\n *\n * @param params\n * Parameters for lookup table creation. The underlying data structure is\n * different for each lookup table type.\n * @param socket_id\n * CPU socket ID (e.g. for memory allocation purpose)\n * @param entry_size\n * Data size of each lookup table entry (measured in bytes)\n * @return\n * Handle to lookup table instance\n */\ntypedef void* (*rte_table_op_create)(void *params, int socket_id,\n\tuint32_t entry_size);\n\n/**\n * Lookup table free\n *\n * @param table\n * Handle to lookup table instance\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_table_op_free)(void *table);\n\n/**\n * Lookup table entry add\n *\n * @param table\n * Handle to lookup table instance\n * @param key\n * Lookup key\n * @param entry\n * Data to be associated with the current key. This parameter has to point to\n * a valid memory buffer where the first entry_size bytes (table create\n * parameter) are populated with the data.\n * @param key_found\n * After successful invocation, *key_found is set to a value different than 0\n * if the current key is already present in the table and to 0 if not. This\n * pointer has to be set to a valid memory location before the table entry add\n * function is called.\n * @param entry_ptr\n * After successful invocation, *entry_ptr stores the handle to the table\n * entry containing the data associated with the current key. This handle can\n * be used to perform further read-write accesses to this entry. This handle\n * is valid until the key is deleted from the table or the same key is\n * re-added to the table, typically to associate it with different data. This\n * pointer has to be set to a valid memory location before the function is\n * called.\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_table_op_entry_add)(\n\tvoid *table,\n\tvoid *key,\n\tvoid *entry,\n\tint *key_found,\n\tvoid **entry_ptr);\n\n/**\n * Lookup table entry delete\n *\n * @param table\n * Handle to lookup table instance\n * @param key\n * Lookup key\n * @param key_found\n * After successful invocation, *key_found is set to a value different than 0\n * if the current key was present in the table before the delete operation\n * was performed and to 0 if not. This pointer has to be set to a valid\n * memory location before the table entry delete function is called.\n * @param entry\n * After successful invocation, if the key is found in the table (*key found\n * is different than 0 after function call is completed) and entry points to\n * a valid buffer (entry is set to a value different than NULL before the\n * function is called), then the first entry_size bytes (table create\n * parameter) in *entry store a copy of table entry that contained the data\n * associated with the current key before the key was deleted.\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_table_op_entry_delete)(\n\tvoid *table,\n\tvoid *key,\n\tint *key_found,\n\tvoid *entry);\n\n/**\n * Lookup table lookup\n *\n * @param table\n * Handle to lookup table instance\n * @param pkts\n * Burst of input packets specified as array of up to 64 pointers to struct\n * rte_mbuf\n * @param pkts_mask\n * 64-bit bitmask specifying which packets in the input burst are valid. When\n * pkts_mask bit n is set, then element n of pkts array is pointing to a\n * valid packet. Otherwise, element n of pkts array does not point to a valid\n * packet, therefore it will not be accessed.\n * @param lookup_hit_mask\n * Once the table lookup operation is completed, this 64-bit bitmask\n * specifies which of the valid packets in the input burst resulted in lookup\n * hit. For each valid input packet (pkts_mask bit n is set), the following\n * are true on lookup hit: lookup_hit_mask bit n is set, element n of entries\n * array is valid and it points to the lookup table entry that was hit. For\n * each valid input packet (pkts_mask bit n is set), the following are true\n * on lookup miss: lookup_hit_mask bit n is not set and element n of entries\n * array is not valid.\n * @param entries\n * Once the table lookup operation is completed, this array provides the\n * lookup table entries that were hit, as described above. It is required\n * that this array is always pre-allocated by the caller of this function\n * with exactly 64 elements. The implementation is allowed to speculatively\n * modify the elements of this array, so elements marked as invalid in\n * lookup_hit_mask once the table lookup operation is completed might have\n * been modified by this function.\n * @return\n * 0 on success, error code otherwise\n */\ntypedef int (*rte_table_op_lookup)(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries);\n\n/**\n * Lookup table stats read\n *\n * @param table\n * Handle to lookup table instance\n * @param stats\n * Handle to table stats struct to copy data\n * @param clear\n * Flag indicating that stats should be cleared after read\n *\n * @return\n * Error code or 0 on success.\n */\ntypedef int (*rte_table_op_stats_read)(\n\tvoid *table,\n\tstruct rte_table_stats *stats,\n\tint clear);\n\n/** Lookup table interface defining the lookup table operation */\nstruct rte_table_ops {\n\trte_table_op_create f_create; /**< Create */\n\trte_table_op_free f_free; /**< Free */\n\trte_table_op_entry_add f_add; /**< Entry add */\n\trte_table_op_entry_delete f_delete; /**< Entry delete */\n\trte_table_op_lookup f_lookup; /**< Lookup */\n\trte_table_op_stats_read f_stats;\t/**< Stats */\n};\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_table/rte_table_acl.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_table_acl.h\"\n#include \n\n#ifdef RTE_TABLE_STATS_COLLECT\n\n#define RTE_TABLE_ACL_STATS_PKTS_IN_ADD(table, val) \\\n\ttable->stats.n_pkts_in += val\n#define RTE_TABLE_ACL_STATS_PKTS_LOOKUP_MISS(table, val) \\\n\ttable->stats.n_pkts_lookup_miss += val\n\n#else\n\n#define RTE_TABLE_ACL_STATS_PKTS_IN_ADD(table, val)\n#define RTE_TABLE_ACL_STATS_PKTS_LOOKUP_MISS(table, val)\n\n#endif\n\nstruct rte_table_acl {\n\tstruct rte_table_stats stats;\n\n\t/* Low-level ACL table */\n\tchar name[2][RTE_ACL_NAMESIZE];\n\tstruct rte_acl_param acl_params; /* for creating low level acl table */\n\tstruct rte_acl_config cfg; /* Holds the field definitions (metadata) */\n\tstruct rte_acl_ctx *ctx;\n\tuint32_t name_id;\n\n\t/* Input parameters */\n\tuint32_t n_rules;\n\tuint32_t entry_size;\n\n\t/* Internal tables */\n\tuint8_t *action_table;\n\tstruct rte_acl_rule **acl_rule_list; /* Array of pointers to rules */\n\tuint8_t *acl_rule_memory; /* Memory to store the rules */\n\n\t/* Memory to store the action table and stack of free entries */\n\tuint8_t memory[0] __rte_cache_aligned;\n};\n\n\nstatic void *\nrte_table_acl_create(\n\tvoid *params,\n\tint socket_id,\n\tuint32_t entry_size)\n{\n\tstruct rte_table_acl_params *p = (struct rte_table_acl_params *) params;\n\tstruct rte_table_acl *acl;\n\tuint32_t action_table_size, acl_rule_list_size, acl_rule_memory_size;\n\tuint32_t total_size;\n\n\tRTE_BUILD_BUG_ON(((sizeof(struct rte_table_acl) % RTE_CACHE_LINE_SIZE)\n\t\t!= 0));\n\n\t/* Check input parameters */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Invalid value for params\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tif (p->name == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Invalid value for name\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tif (p->n_rules == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Invalid value for n_rules\\n\",\n\t\t\t__func__);\n\t\treturn NULL;\n\t}\n\tif ((p->n_rule_fields == 0) ||\n\t (p->n_rule_fields > RTE_ACL_MAX_FIELDS)) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Invalid value for n_rule_fields\\n\",\n\t\t\t__func__);\n\t\treturn NULL;\n\t}\n\n\tentry_size = RTE_ALIGN(entry_size, sizeof(uint64_t));\n\n\t/* Memory allocation */\n\taction_table_size = RTE_CACHE_LINE_ROUNDUP(p->n_rules * entry_size);\n\tacl_rule_list_size =\n\t\tRTE_CACHE_LINE_ROUNDUP(p->n_rules * sizeof(struct rte_acl_rule *));\n\tacl_rule_memory_size = RTE_CACHE_LINE_ROUNDUP(p->n_rules *\n\t\tRTE_ACL_RULE_SZ(p->n_rule_fields));\n\ttotal_size = sizeof(struct rte_table_acl) + action_table_size +\n\t\tacl_rule_list_size + acl_rule_memory_size;\n\n\tacl = rte_zmalloc_socket(\"TABLE\", total_size, RTE_CACHE_LINE_SIZE,\n\t\tsocket_id);\n\tif (acl == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot allocate %u bytes for ACL table\\n\",\n\t\t\t__func__, total_size);\n\t\treturn NULL;\n\t}\n\n\tacl->action_table = &acl->memory[0];\n\tacl->acl_rule_list =\n\t\t(struct rte_acl_rule **) &acl->memory[action_table_size];\n\tacl->acl_rule_memory = (uint8_t *)\n\t\t&acl->memory[action_table_size + acl_rule_list_size];\n\n\t/* Initialization of internal fields */\n\tsnprintf(acl->name[0], RTE_ACL_NAMESIZE, \"%s_a\", p->name);\n\tsnprintf(acl->name[1], RTE_ACL_NAMESIZE, \"%s_b\", p->name);\n\tacl->name_id = 1;\n\n\tacl->acl_params.name = acl->name[acl->name_id];\n\tacl->acl_params.socket_id = socket_id;\n\tacl->acl_params.rule_size = RTE_ACL_RULE_SZ(p->n_rule_fields);\n\tacl->acl_params.max_rule_num = p->n_rules;\n\n\tacl->cfg.num_categories = 1;\n\tacl->cfg.num_fields = p->n_rule_fields;\n\tmemcpy(&acl->cfg.defs[0], &p->field_format[0],\n\t\tp->n_rule_fields * sizeof(struct rte_acl_field_def));\n\n\tacl->ctx = NULL;\n\n\tacl->n_rules = p->n_rules;\n\tacl->entry_size = entry_size;\n\n\treturn acl;\n}\n\nstatic int\nrte_table_acl_free(void *table)\n{\n\tstruct rte_table_acl *acl = (struct rte_table_acl *) table;\n\n\t/* Check input parameters */\n\tif (table == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Free previously allocated resources */\n\tif (acl->ctx != NULL)\n\t\trte_acl_free(acl->ctx);\n\n\trte_free(acl);\n\n\treturn 0;\n}\n\nRTE_ACL_RULE_DEF(rte_pipeline_acl_rule, RTE_ACL_MAX_FIELDS);\n\nstatic int\nrte_table_acl_build(struct rte_table_acl *acl, struct rte_acl_ctx **acl_ctx)\n{\n\tstruct rte_acl_ctx *ctx = NULL;\n\tuint32_t n_rules, i;\n\tint status;\n\n\t/* Create low level ACL table */\n\tctx = rte_acl_create(&acl->acl_params);\n\tif (ctx == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Cannot create low level ACL table\\n\",\n\t\t\t__func__);\n\t\treturn -1;\n\t}\n\n\t/* Add rules to low level ACL table */\n\tn_rules = 0;\n\tfor (i = 1; i < acl->n_rules; i++) {\n\t\tif (acl->acl_rule_list[i] != NULL) {\n\t\t\tstatus = rte_acl_add_rules(ctx, acl->acl_rule_list[i],\n\t\t\t\t1);\n\t\t\tif (status != 0) {\n\t\t\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\t\"%s: Cannot add rule to low level ACL table\\n\",\n\t\t\t\t\t__func__);\n\t\t\t\trte_acl_free(ctx);\n\t\t\t\treturn -1;\n\t\t\t}\n\n\t\t\tn_rules++;\n\t\t}\n\t}\n\n\tif (n_rules == 0) {\n\t\trte_acl_free(ctx);\n\t\t*acl_ctx = NULL;\n\t\treturn 0;\n\t}\n\n\t/* Build low level ACl table */\n\tstatus = rte_acl_build(ctx, &acl->cfg);\n\tif (status != 0) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot build the low level ACL table\\n\",\n\t\t\t__func__);\n\t\trte_acl_free(ctx);\n\t\treturn -1;\n\t}\n\n\trte_acl_dump(ctx);\n\n\t*acl_ctx = ctx;\n\treturn 0;\n}\n\nstatic int\nrte_table_acl_entry_add(\n\tvoid *table,\n\tvoid *key,\n\tvoid *entry,\n\tint *key_found,\n\tvoid **entry_ptr)\n{\n\tstruct rte_table_acl *acl = (struct rte_table_acl *) table;\n\tstruct rte_table_acl_rule_add_params *rule =\n\t\t(struct rte_table_acl_rule_add_params *) key;\n\tstruct rte_pipeline_acl_rule acl_rule;\n\tstruct rte_acl_rule *rule_location;\n\tstruct rte_acl_ctx *ctx;\n\tuint32_t free_pos, free_pos_valid, i;\n\tint status;\n\n\t/* Check input parameters */\n\tif (table == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (key == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: key parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (entry == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: entry parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (key_found == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: key_found parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\tif (entry_ptr == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: entry_ptr parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\tif (rule->priority > RTE_ACL_MAX_PRIORITY) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Priority is too high\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Setup rule data structure */\n\tmemset(&acl_rule, 0, sizeof(acl_rule));\n\tacl_rule.data.category_mask = 1;\n\tacl_rule.data.priority = RTE_ACL_MAX_PRIORITY - rule->priority;\n\tacl_rule.data.userdata = 0; /* To be set up later */\n\tmemcpy(&acl_rule.field[0],\n\t\t&rule->field_value[0],\n\t\tacl->cfg.num_fields * sizeof(struct rte_acl_field));\n\n\t/* Look to see if the rule exists already in the table */\n\tfree_pos = 0;\n\tfree_pos_valid = 0;\n\tfor (i = 1; i < acl->n_rules; i++) {\n\t\tif (acl->acl_rule_list[i] == NULL) {\n\t\t\tif (free_pos_valid == 0) {\n\t\t\t\tfree_pos = i;\n\t\t\t\tfree_pos_valid = 1;\n\t\t\t}\n\n\t\t\tcontinue;\n\t\t}\n\n\t\t/* Compare the key fields */\n\t\tstatus = memcmp(&acl->acl_rule_list[i]->field[0],\n\t\t\t&rule->field_value[0],\n\t\t\tacl->cfg.num_fields * sizeof(struct rte_acl_field));\n\n\t\t/* Rule found: update data associated with the rule */\n\t\tif (status == 0) {\n\t\t\t*key_found = 1;\n\t\t\t*entry_ptr = &acl->memory[i * acl->entry_size];\n\t\t\tmemcpy(*entry_ptr, entry, acl->entry_size);\n\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Return if max rules */\n\tif (free_pos_valid == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Max number of rules reached\\n\",\n\t\t\t__func__);\n\t\treturn -ENOSPC;\n\t}\n\n\t/* Add the new rule to the rule set */\n\tacl_rule.data.userdata = free_pos;\n\trule_location = (struct rte_acl_rule *)\n\t\t&acl->acl_rule_memory[free_pos * acl->acl_params.rule_size];\n\tmemcpy(rule_location, &acl_rule, acl->acl_params.rule_size);\n\tacl->acl_rule_list[free_pos] = rule_location;\n\n\t/* Build low level ACL table */\n\tacl->name_id ^= 1;\n\tacl->acl_params.name = acl->name[acl->name_id];\n\tstatus = rte_table_acl_build(acl, &ctx);\n\tif (status != 0) {\n\t\t/* Roll back changes */\n\t\tacl->acl_rule_list[free_pos] = NULL;\n\t\tacl->name_id ^= 1;\n\n\t\treturn -EINVAL;\n\t}\n\n\t/* Commit changes */\n\tif (acl->ctx != NULL)\n\t\trte_acl_free(acl->ctx);\n\tacl->ctx = ctx;\n\t*key_found = 0;\n\t*entry_ptr = &acl->memory[free_pos * acl->entry_size];\n\tmemcpy(*entry_ptr, entry, acl->entry_size);\n\n\treturn 0;\n}\n\nstatic int\nrte_table_acl_entry_delete(\n\tvoid *table,\n\tvoid *key,\n\tint *key_found,\n\tvoid *entry)\n{\n\tstruct rte_table_acl *acl = (struct rte_table_acl *) table;\n\tstruct rte_table_acl_rule_delete_params *rule =\n\t\t(struct rte_table_acl_rule_delete_params *) key;\n\tstruct rte_acl_rule *deleted_rule = NULL;\n\tstruct rte_acl_ctx *ctx;\n\tuint32_t pos, pos_valid, i;\n\tint status;\n\n\t/* Check input parameters */\n\tif (table == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (key == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: key parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (key_found == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: key_found parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Look for the rule in the table */\n\tpos = 0;\n\tpos_valid = 0;\n\tfor (i = 1; i < acl->n_rules; i++) {\n\t\tif (acl->acl_rule_list[i] != NULL) {\n\t\t\t/* Compare the key fields */\n\t\t\tstatus = memcmp(&acl->acl_rule_list[i]->field[0],\n\t\t\t\t&rule->field_value[0], acl->cfg.num_fields *\n\t\t\t\tsizeof(struct rte_acl_field));\n\n\t\t\t/* Rule found: remove from table */\n\t\t\tif (status == 0) {\n\t\t\t\tpos = i;\n\t\t\t\tpos_valid = 1;\n\n\t\t\t\tdeleted_rule = acl->acl_rule_list[i];\n\t\t\t\tacl->acl_rule_list[i] = NULL;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Return if rule not found */\n\tif (pos_valid == 0) {\n\t\t*key_found = 0;\n\t\treturn 0;\n\t}\n\n\t/* Build low level ACL table */\n\tacl->name_id ^= 1;\n\tacl->acl_params.name = acl->name[acl->name_id];\n\tstatus = rte_table_acl_build(acl, &ctx);\n\tif (status != 0) {\n\t\t/* Roll back changes */\n\t\tacl->acl_rule_list[pos] = deleted_rule;\n\t\tacl->name_id ^= 1;\n\n\t\treturn -EINVAL;\n\t}\n\n\t/* Commit changes */\n\tif (acl->ctx != NULL)\n\t\trte_acl_free(acl->ctx);\n\n\tacl->ctx = ctx;\n\t*key_found = 1;\n\tif (entry != NULL)\n\t\tmemcpy(entry, &acl->memory[pos * acl->entry_size],\n\t\t\tacl->entry_size);\n\n\treturn 0;\n}\n\nstatic int\nrte_table_acl_lookup(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_acl *acl = (struct rte_table_acl *) table;\n\tconst uint8_t *pkts_data[RTE_PORT_IN_BURST_SIZE_MAX];\n\tuint32_t results[RTE_PORT_IN_BURST_SIZE_MAX];\n\tuint64_t pkts_out_mask;\n\tuint32_t n_pkts, i, j;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_ACL_STATS_PKTS_IN_ADD(acl, n_pkts_in);\n\n\t/* Input conversion */\n\tfor (i = 0, j = 0; i < (uint32_t)(RTE_PORT_IN_BURST_SIZE_MAX -\n\t\t__builtin_clzll(pkts_mask)); i++) {\n\t\tuint64_t pkt_mask = 1LLU << i;\n\n\t\tif (pkt_mask & pkts_mask) {\n\t\t\tpkts_data[j] = rte_pktmbuf_mtod(pkts[i], uint8_t *);\n\t\t\tj++;\n\t\t}\n\t}\n\tn_pkts = j;\n\n\t/* Low-level ACL table lookup */\n\tif (acl->ctx != NULL)\n\t\trte_acl_classify(acl->ctx, pkts_data, results, n_pkts, 1);\n\telse\n\t\tn_pkts = 0;\n\n\t/* Output conversion */\n\tpkts_out_mask = 0;\n\tfor (i = 0; i < n_pkts; i++) {\n\t\tuint32_t action_table_pos = results[i];\n\t\tuint32_t pkt_pos = __builtin_ctzll(pkts_mask);\n\t\tuint64_t pkt_mask = 1LLU << pkt_pos;\n\n\t\tpkts_mask &= ~pkt_mask;\n\n\t\tif (action_table_pos != RTE_ACL_INVALID_USERDATA) {\n\t\t\tpkts_out_mask |= pkt_mask;\n\t\t\tentries[pkt_pos] = (void *)\n\t\t\t\t&acl->memory[action_table_pos *\n\t\t\t\tacl->entry_size];\n\t\t\trte_prefetch0(entries[pkt_pos]);\n\t\t}\n\t}\n\n\t*lookup_hit_mask = pkts_out_mask;\n\tRTE_TABLE_ACL_STATS_PKTS_LOOKUP_MISS(acl, n_pkts_in - __builtin_popcountll(pkts_out_mask));\n\n\treturn 0;\n}\n\nstatic int\nrte_table_acl_stats_read(void *table, struct rte_table_stats *stats, int clear)\n{\n\tstruct rte_table_acl *acl = (struct rte_table_acl *) table;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &acl->stats, sizeof(acl->stats));\n\n\tif (clear)\n\t\tmemset(&acl->stats, 0, sizeof(acl->stats));\n\n\treturn 0;\n}\n\nstruct rte_table_ops rte_table_acl_ops = {\n\t.f_create = rte_table_acl_create,\n\t.f_free = rte_table_acl_free,\n\t.f_add = rte_table_acl_entry_add,\n\t.f_delete = rte_table_acl_entry_delete,\n\t.f_lookup = rte_table_acl_lookup,\n\t.f_stats = rte_table_acl_stats_read,\n};\n" }, { "path": "lib/librte_table/rte_table_acl.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_TABLE_ACL_H__\n#define __INCLUDE_RTE_TABLE_ACL_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Table ACL\n *\n * This table uses the Access Control List (ACL) algorithm to uniquely\n * associate data to lookup keys.\n *\n * Use-cases: Firewall rule database, etc.\n *\n ***/\n\n#include \n\n#include \"rte_acl.h\"\n\n#include \"rte_table.h\"\n\n/** ACL table parameters */\nstruct rte_table_acl_params {\n\t/** Name */\n\tconst char *name;\n\n\t/** Maximum number of ACL rules in the table */\n\tuint32_t n_rules;\n\n\t/** Number of fields in the ACL rule specification */\n\tuint32_t n_rule_fields;\n\n\t/** Format specification of the fields of the ACL rule */\n\tstruct rte_acl_field_def field_format[RTE_ACL_MAX_FIELDS];\n};\n\n/** ACL rule specification for entry add operation */\nstruct rte_table_acl_rule_add_params {\n\t/** ACL rule priority, with 0 as the highest priority */\n\tint32_t priority;\n\n\t/** Values for the fields of the ACL rule to be added to the table */\n\tstruct rte_acl_field field_value[RTE_ACL_MAX_FIELDS];\n};\n\n/** ACL rule specification for entry delete operation */\nstruct rte_table_acl_rule_delete_params {\n\t/** Values for the fields of the ACL rule to be deleted from table */\n\tstruct rte_acl_field field_value[RTE_ACL_MAX_FIELDS];\n};\n\n/** ACL table operations */\nextern struct rte_table_ops rte_table_acl_ops;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_table/rte_table_array.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_table_array.h\"\n\n#ifdef RTE_TABLE_STATS_COLLECT\n\n#define RTE_TABLE_ARRAY_STATS_PKTS_IN_ADD(table, val) \\\n\ttable->stats.n_pkts_in += val\n#define RTE_TABLE_ARRAY_STATS_PKTS_LOOKUP_MISS(table, val) \\\n\ttable->stats.n_pkts_lookup_miss += val\n\n#else\n\n#define RTE_TABLE_ARRAY_STATS_PKTS_IN_ADD(table, val)\n#define RTE_TABLE_ARRAY_STATS_PKTS_LOOKUP_MISS(table, val)\n\n#endif\n\nstruct rte_table_array {\n\tstruct rte_table_stats stats;\n\n\t/* Input parameters */\n\tuint32_t entry_size;\n\tuint32_t n_entries;\n\tuint32_t offset;\n\n\t/* Internal fields */\n\tuint32_t entry_pos_mask;\n\n\t/* Internal table */\n\tuint8_t array[0] __rte_cache_aligned;\n} __rte_cache_aligned;\n\nstatic void *\nrte_table_array_create(void *params, int socket_id, uint32_t entry_size)\n{\n\tstruct rte_table_array_params *p =\n\t\t(struct rte_table_array_params *) params;\n\tstruct rte_table_array *t;\n\tuint32_t total_cl_size, total_size;\n\n\t/* Check input parameters */\n\tif ((p == NULL) ||\n\t (p->n_entries == 0) ||\n\t\t(!rte_is_power_of_2(p->n_entries)))\n\t\treturn NULL;\n\n\t/* Memory allocation */\n\ttotal_cl_size = (sizeof(struct rte_table_array) +\n\t\t\tRTE_CACHE_LINE_SIZE) / RTE_CACHE_LINE_SIZE;\n\ttotal_cl_size += (p->n_entries * entry_size +\n\t\t\tRTE_CACHE_LINE_SIZE) / RTE_CACHE_LINE_SIZE;\n\ttotal_size = total_cl_size * RTE_CACHE_LINE_SIZE;\n\tt = rte_zmalloc_socket(\"TABLE\", total_size, RTE_CACHE_LINE_SIZE, socket_id);\n\tif (t == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot allocate %u bytes for array table\\n\",\n\t\t\t__func__, total_size);\n\t\treturn NULL;\n\t}\n\n\t/* Memory initialization */\n\tt->entry_size = entry_size;\n\tt->n_entries = p->n_entries;\n\tt->offset = p->offset;\n\tt->entry_pos_mask = t->n_entries - 1;\n\n\treturn t;\n}\n\nstatic int\nrte_table_array_free(void *table)\n{\n\tstruct rte_table_array *t = (struct rte_table_array *) table;\n\n\t/* Check input parameters */\n\tif (t == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Free previously allocated resources */\n\trte_free(t);\n\n\treturn 0;\n}\n\nstatic int\nrte_table_array_entry_add(\n\tvoid *table,\n\tvoid *key,\n\tvoid *entry,\n\tint *key_found,\n\tvoid **entry_ptr)\n{\n\tstruct rte_table_array *t = (struct rte_table_array *) table;\n\tstruct rte_table_array_key *k = (struct rte_table_array_key *) key;\n\tuint8_t *table_entry;\n\n\t/* Check input parameters */\n\tif (table == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (key == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: key parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (entry == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: entry parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (key_found == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: key_found parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\tif (entry_ptr == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: entry_ptr parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\ttable_entry = &t->array[k->pos * t->entry_size];\n\tmemcpy(table_entry, entry, t->entry_size);\n\t*key_found = 1;\n\t*entry_ptr = (void *) table_entry;\n\n\treturn 0;\n}\n\nstatic int\nrte_table_array_lookup(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_array *t = (struct rte_table_array *) table;\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_ARRAY_STATS_PKTS_IN_ADD(t, n_pkts_in);\n\t*lookup_hit_mask = pkts_mask;\n\n\tif ((pkts_mask & (pkts_mask + 1)) == 0) {\n\t\tuint64_t n_pkts = __builtin_popcountll(pkts_mask);\n\t\tuint32_t i;\n\n\t\tfor (i = 0; i < n_pkts; i++) {\n\t\t\tstruct rte_mbuf *pkt = pkts[i];\n\t\t\tuint32_t entry_pos = RTE_MBUF_METADATA_UINT32(pkt,\n\t\t\t\tt->offset) & t->entry_pos_mask;\n\n\t\t\tentries[i] = (void *) &t->array[entry_pos *\n\t\t\t\tt->entry_size];\n\t\t}\n\t} else {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tuint32_t pkt_index = __builtin_ctzll(pkts_mask);\n\t\t\tuint64_t pkt_mask = 1LLU << pkt_index;\n\t\t\tstruct rte_mbuf *pkt = pkts[pkt_index];\n\t\t\tuint32_t entry_pos = RTE_MBUF_METADATA_UINT32(pkt,\n\t\t\t\tt->offset) & t->entry_pos_mask;\n\n\t\t\tentries[pkt_index] = (void *) &t->array[entry_pos *\n\t\t\t\tt->entry_size];\n\t\t\tpkts_mask &= ~pkt_mask;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_table_array_stats_read(void *table, struct rte_table_stats *stats, int clear)\n{\n\tstruct rte_table_array *array = (struct rte_table_array *) table;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &array->stats, sizeof(array->stats));\n\n\tif (clear)\n\t\tmemset(&array->stats, 0, sizeof(array->stats));\n\n\treturn 0;\n}\n\nstruct rte_table_ops rte_table_array_ops = {\n\t.f_create = rte_table_array_create,\n\t.f_free = rte_table_array_free,\n\t.f_add = rte_table_array_entry_add,\n\t.f_delete = NULL,\n\t.f_lookup = rte_table_array_lookup,\n\t.f_stats = rte_table_array_stats_read,\n};\n" }, { "path": "lib/librte_table/rte_table_array.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_TABLE_ARRAY_H__\n#define __INCLUDE_RTE_TABLE_ARRAY_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Table Array\n *\n * Simple array indexing. Lookup key is the array entry index.\n *\n ***/\n\n#include \n\n#include \"rte_table.h\"\n\n/** Array table parameters */\nstruct rte_table_array_params {\n\t/** Number of array entries. Has to be a power of two. */\n\tuint32_t n_entries;\n\n\t/** Byte offset within input packet meta-data where lookup key (i.e. the\n\t array entry index) is located. */\n\tuint32_t offset;\n};\n\n/** Array table key format */\nstruct rte_table_array_key {\n\t/** Array entry index */\n\tuint32_t pos;\n};\n\n/** Array table operations */\nextern struct rte_table_ops rte_table_array_ops;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_table/rte_table_hash.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_TABLE_HASH_H__\n#define __INCLUDE_RTE_TABLE_HASH_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Table Hash\n *\n * These tables use the exact match criterion to uniquely associate data to\n * lookup keys.\n *\n * Use-cases: Flow classification table, Address Resolution Protocol (ARP) table\n *\n * Hash table types:\n * 1. Entry add strategy on bucket full:\n * a. Least Recently Used (LRU): One of the existing keys in the bucket is\n * deleted and the new key is added in its place. The number of keys in\n * each bucket never grows bigger than 4. The logic to pick the key to\n * be dropped from the bucket is LRU. The hash table lookup operation\n * maintains the order in which the keys in the same bucket are hit, so\n * every time a key is hit, it becomes the new Most Recently Used (MRU)\n * key, i.e. the most unlikely candidate for drop. When a key is added\n * to the bucket, it also becomes the new MRU key. When a key needs to\n * be picked and dropped, the most likely candidate for drop, i.e. the\n * current LRU key, is always picked. The LRU logic requires maintaining\n * specific data structures per each bucket.\n * b. Extendible bucket (ext): The bucket is extended with space for 4 more\n * keys. This is done by allocating additional memory at table init time,\n * which is used to create a pool of free keys (the size of this pool is\n * configurable and always a multiple of 4). On key add operation, the\n * allocation of a group of 4 keys only happens successfully within the\n * limit of free keys, otherwise the key add operation fails. On key\n * delete operation, a group of 4 keys is freed back to the pool of free\n * keys when the key to be deleted is the only key that was used within\n * its group of 4 keys at that time. On key lookup operation, if the\n * current bucket is in extended state and a match is not found in the\n * first group of 4 keys, the search continues beyond the first group of\n * 4 keys, potentially until all keys in this bucket are examined. The\n * extendible bucket logic requires maintaining specific data structures\n * per table and per each bucket.\n * 2. Key signature computation:\n * a. Pre-computed key signature: The key lookup operation is split between\n * two CPU cores. The first CPU core (typically the CPU core performing\n * packet RX) extracts the key from the input packet, computes the key\n * signature and saves both the key and the key signature in the packet\n * buffer as packet meta-data. The second CPU core reads both the key and\n * the key signature from the packet meta-data and performs the bucket\n * search step of the key lookup operation.\n * b. Key signature computed on lookup (do-sig): The same CPU core reads\n * the key from the packet meta-data, uses it to compute the key\n * signature and also performs the bucket search step of the key lookup\n * operation.\n * 3. Key size:\n * a. Configurable key size\n * b. Single key size (8-byte, 16-byte or 32-byte key size)\n *\n ***/\n#include \n\n#include \"rte_table.h\"\n\n/** Hash function */\ntypedef uint64_t (*rte_table_hash_op_hash)(\n\tvoid *key,\n\tuint32_t key_size,\n\tuint64_t seed);\n\n/**\n * Hash tables with configurable key size\n *\n */\n/** Extendible bucket hash table parameters */\nstruct rte_table_hash_ext_params {\n\t/** Key size (number of bytes) */\n\tuint32_t key_size;\n\n\t/** Maximum number of keys */\n\tuint32_t n_keys;\n\n\t/** Number of hash table buckets. Each bucket stores up to 4 keys. */\n\tuint32_t n_buckets;\n\n\t/** Number of hash table bucket extensions. Each bucket extension has\n\tspace for 4 keys and each bucket can have 0, 1 or more extensions. */\n\tuint32_t n_buckets_ext;\n\n\t/** Hash function */\n\trte_table_hash_op_hash f_hash;\n\n\t/** Seed value for the hash function */\n\tuint64_t seed;\n\n\t/** Byte offset within packet meta-data where the 4-byte key signature\n\tis located. Valid for pre-computed key signature tables, ignored for\n\tdo-sig tables. */\n\tuint32_t signature_offset;\n\n\t/** Byte offset within packet meta-data where the key is located */\n\tuint32_t key_offset;\n};\n\n/** Extendible bucket hash table operations for pre-computed key signature */\nextern struct rte_table_ops rte_table_hash_ext_ops;\n\n/** Extendible bucket hash table operations for key signature computed on\n\tlookup (\"do-sig\") */\nextern struct rte_table_ops rte_table_hash_ext_dosig_ops;\n\n/** LRU hash table parameters */\nstruct rte_table_hash_lru_params {\n\t/** Key size (number of bytes) */\n\tuint32_t key_size;\n\n\t/** Maximum number of keys */\n\tuint32_t n_keys;\n\n\t/** Number of hash table buckets. Each bucket stores up to 4 keys. */\n\tuint32_t n_buckets;\n\n\t/** Hash function */\n\trte_table_hash_op_hash f_hash;\n\n\t/** Seed value for the hash function */\n\tuint64_t seed;\n\n\t/** Byte offset within packet meta-data where the 4-byte key signature\n\tis located. Valid for pre-computed key signature tables, ignored for\n\tdo-sig tables. */\n\tuint32_t signature_offset;\n\n\t/** Byte offset within packet meta-data where the key is located */\n\tuint32_t key_offset;\n};\n\n/** LRU hash table operations for pre-computed key signature */\nextern struct rte_table_ops rte_table_hash_lru_ops;\n\n/** LRU hash table operations for key signature computed on lookup (\"do-sig\") */\nextern struct rte_table_ops rte_table_hash_lru_dosig_ops;\n\n/**\n * 8-byte key hash tables\n *\n */\n/** LRU hash table parameters */\nstruct rte_table_hash_key8_lru_params {\n\t/** Maximum number of entries (and keys) in the table */\n\tuint32_t n_entries;\n\n\t/** Hash function */\n\trte_table_hash_op_hash f_hash;\n\n\t/** Seed for the hash function */\n\tuint64_t seed;\n\n\t/** Byte offset within packet meta-data where the 4-byte key signature\n\tis located. Valid for pre-computed key signature tables, ignored for\n\tdo-sig tables. */\n\tuint32_t signature_offset;\n\n\t/** Byte offset within packet meta-data where the key is located */\n\tuint32_t key_offset;\n};\n\n/** LRU hash table operations for pre-computed key signature */\nextern struct rte_table_ops rte_table_hash_key8_lru_ops;\n\n/** LRU hash table operations for key signature computed on lookup (\"do-sig\") */\nextern struct rte_table_ops rte_table_hash_key8_lru_dosig_ops;\n\n/** Extendible bucket hash table parameters */\nstruct rte_table_hash_key8_ext_params {\n\t/** Maximum number of entries (and keys) in the table */\n\tuint32_t n_entries;\n\n\t/** Number of entries (and keys) for hash table bucket extensions. Each\n\t\tbucket is extended in increments of 4 keys. */\n\tuint32_t n_entries_ext;\n\n\t/** Hash function */\n\trte_table_hash_op_hash f_hash;\n\n\t/** Seed for the hash function */\n\tuint64_t seed;\n\n\t/** Byte offset within packet meta-data where the 4-byte key signature\n\tis located. Valid for pre-computed key signature tables, ignored for\n\tdo-sig tables. */\n\tuint32_t signature_offset;\n\n\t/** Byte offset within packet meta-data where the key is located */\n\tuint32_t key_offset;\n};\n\n/** Extendible bucket hash table operations for pre-computed key signature */\nextern struct rte_table_ops rte_table_hash_key8_ext_ops;\n\n/** Extendible bucket hash table operations for key signature computed on\n lookup (\"do-sig\") */\nextern struct rte_table_ops rte_table_hash_key8_ext_dosig_ops;\n\n/**\n * 16-byte key hash tables\n *\n */\n/** LRU hash table parameters */\nstruct rte_table_hash_key16_lru_params {\n\t/** Maximum number of entries (and keys) in the table */\n\tuint32_t n_entries;\n\n\t/** Hash function */\n\trte_table_hash_op_hash f_hash;\n\n\t/** Seed for the hash function */\n\tuint64_t seed;\n\n\t/** Byte offset within packet meta-data where the 4-byte key signature\n\tis located. Valid for pre-computed key signature tables, ignored for\n\tdo-sig tables. */\n\tuint32_t signature_offset;\n\n\t/** Byte offset within packet meta-data where the key is located */\n\tuint32_t key_offset;\n};\n\n/** LRU hash table operations for pre-computed key signature */\nextern struct rte_table_ops rte_table_hash_key16_lru_ops;\n\n/** Extendible bucket hash table parameters */\nstruct rte_table_hash_key16_ext_params {\n\t/** Maximum number of entries (and keys) in the table */\n\tuint32_t n_entries;\n\n\t/** Number of entries (and keys) for hash table bucket extensions. Each\n\tbucket is extended in increments of 4 keys. */\n\tuint32_t n_entries_ext;\n\n\t/** Hash function */\n\trte_table_hash_op_hash f_hash;\n\n\t/** Seed for the hash function */\n\tuint64_t seed;\n\n\t/** Byte offset within packet meta-data where the 4-byte key signature\n\tis located. Valid for pre-computed key signature tables, ignored for\n\tdo-sig tables. */\n\tuint32_t signature_offset;\n\n\t/** Byte offset within packet meta-data where the key is located */\n\tuint32_t key_offset;\n};\n\n/** Extendible bucket operations for pre-computed key signature */\nextern struct rte_table_ops rte_table_hash_key16_ext_ops;\n\n/**\n * 32-byte key hash tables\n *\n */\n/** LRU hash table parameters */\nstruct rte_table_hash_key32_lru_params {\n\t/** Maximum number of entries (and keys) in the table */\n\tuint32_t n_entries;\n\n\t/** Hash function */\n\trte_table_hash_op_hash f_hash;\n\n\t/** Seed for the hash function */\n\tuint64_t seed;\n\n\t/** Byte offset within packet meta-data where the 4-byte key signature\n\tis located. Valid for pre-computed key signature tables, ignored for\n\tdo-sig tables. */\n\tuint32_t signature_offset;\n\n\t/** Byte offset within packet meta-data where the key is located */\n\tuint32_t key_offset;\n};\n\n/** LRU hash table operations for pre-computed key signature */\nextern struct rte_table_ops rte_table_hash_key32_lru_ops;\n\n/** Extendible bucket hash table parameters */\nstruct rte_table_hash_key32_ext_params {\n\t/** Maximum number of entries (and keys) in the table */\n\tuint32_t n_entries;\n\n\t/** Number of entries (and keys) for hash table bucket extensions. Each\n\t\tbucket is extended in increments of 4 keys. */\n\tuint32_t n_entries_ext;\n\n\t/** Hash function */\n\trte_table_hash_op_hash f_hash;\n\n\t/** Seed for the hash function */\n\tuint64_t seed;\n\n\t/** Byte offset within packet meta-data where the 4-byte key signature\n\tis located. Valid for pre-computed key signature tables, ignored for\n\tdo-sig tables. */\n\tuint32_t signature_offset;\n\n\t/** Byte offset within packet meta-data where the key is located */\n\tuint32_t key_offset;\n};\n\n/** Extendible bucket hash table operations */\nextern struct rte_table_ops rte_table_hash_key32_ext_ops;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_table/rte_table_hash_ext.c", "content": "/*-\n *\t BSD LICENSE\n *\n *\t Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\t All rights reserved.\n *\n *\t Redistribution and use in source and binary forms, with or without\n *\t modification, are permitted provided that the following conditions\n *\t are met:\n *\n *\t* Redistributions of source code must retain the above copyright\n *\t\t notice, this list of conditions and the following disclaimer.\n *\t* Redistributions in binary form must reproduce the above copyright\n *\t\t notice, this list of conditions and the following disclaimer in\n *\t\t the documentation and/or other materials provided with the\n *\t\t distribution.\n *\t* Neither the name of Intel Corporation nor the names of its\n *\t\t contributors may be used to endorse or promote products derived\n *\t\t from this software without specific prior written permission.\n *\n *\t THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n *\t \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n *\t LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n *\t A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n *\t OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n *\t SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n *\t LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n *\t DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n *\t THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n *\t (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n *\t OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_table_hash.h\"\n\n#define KEYS_PER_BUCKET\t4\n\nstruct bucket {\n\tunion {\n\t\tuintptr_t next;\n\t\tuint64_t lru_list;\n\t};\n\tuint16_t sig[KEYS_PER_BUCKET];\n\tuint32_t key_pos[KEYS_PER_BUCKET];\n};\n\n#define BUCKET_NEXT(bucket)\t\t\t\t\t\t\\\n\t((void *) ((bucket)->next & (~1LU)))\n\n#define BUCKET_NEXT_VALID(bucket)\t\t\t\t\t\\\n\t((bucket)->next & 1LU)\n\n#define BUCKET_NEXT_SET(bucket, bucket_next)\t\t\t\t\\\ndo\t\t\t\t\t\t\t\t\t\\\n\t(bucket)->next = (((uintptr_t) ((void *) (bucket_next))) | 1LU);\\\nwhile (0)\n\n#define BUCKET_NEXT_SET_NULL(bucket)\t\t\t\t\t\\\ndo\t\t\t\t\t\t\t\t\t\\\n\t(bucket)->next = 0;\t\t\t\t\t\t\\\nwhile (0)\n\n#define BUCKET_NEXT_COPY(bucket, bucket2)\t\t\t\t\\\ndo\t\t\t\t\t\t\t\t\t\\\n\t(bucket)->next = (bucket2)->next;\t\t\t\t\\\nwhile (0)\n\n#ifdef RTE_TABLE_STATS_COLLECT\n\n#define RTE_TABLE_HASH_EXT_STATS_PKTS_IN_ADD(table, val) \\\n\ttable->stats.n_pkts_in += val\n#define RTE_TABLE_HASH_EXT_STATS_PKTS_LOOKUP_MISS(table, val) \\\n\ttable->stats.n_pkts_lookup_miss += val\n\n#else\n\n#define RTE_TABLE_HASH_EXT_STATS_PKTS_IN_ADD(table, val)\n#define RTE_TABLE_HASH_EXT_STATS_PKTS_LOOKUP_MISS(table, val)\n\n#endif\n\nstruct grinder {\n\tstruct bucket *bkt;\n\tuint64_t sig;\n\tuint64_t match;\n\tuint32_t key_index;\n};\n\nstruct rte_table_hash {\n\tstruct rte_table_stats stats;\n\n\t/* Input parameters */\n\tuint32_t key_size;\n\tuint32_t entry_size;\n\tuint32_t n_keys;\n\tuint32_t n_buckets;\n\tuint32_t n_buckets_ext;\n\trte_table_hash_op_hash f_hash;\n\tuint64_t seed;\n\tuint32_t signature_offset;\n\tuint32_t key_offset;\n\n\t/* Internal */\n\tuint64_t bucket_mask;\n\tuint32_t key_size_shl;\n\tuint32_t data_size_shl;\n\tuint32_t key_stack_tos;\n\tuint32_t bkt_ext_stack_tos;\n\n\t/* Grinder */\n\tstruct grinder grinders[RTE_PORT_IN_BURST_SIZE_MAX];\n\n\t/* Tables */\n\tstruct bucket *buckets;\n\tstruct bucket *buckets_ext;\n\tuint8_t *key_mem;\n\tuint8_t *data_mem;\n\tuint32_t *key_stack;\n\tuint32_t *bkt_ext_stack;\n\n\t/* Table memory */\n\tuint8_t memory[0] __rte_cache_aligned;\n};\n\nstatic int\ncheck_params_create(struct rte_table_hash_ext_params *params)\n{\n\tuint32_t n_buckets_min;\n\n\t/* key_size */\n\tif ((params->key_size == 0) ||\n\t\t(!rte_is_power_of_2(params->key_size))) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: key_size invalid value\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* n_keys */\n\tif ((params->n_keys == 0) ||\n\t\t(!rte_is_power_of_2(params->n_keys))) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_keys invalid value\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* n_buckets */\n\tn_buckets_min = (params->n_keys + KEYS_PER_BUCKET - 1) / params->n_keys;\n\tif ((params->n_buckets == 0) ||\n\t\t(!rte_is_power_of_2(params->n_keys)) ||\n\t\t(params->n_buckets < n_buckets_min)) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_buckets invalid value\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* f_hash */\n\tif (params->f_hash == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: f_hash invalid value\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic void *\nrte_table_hash_ext_create(void *params, int socket_id, uint32_t entry_size)\n{\n\tstruct rte_table_hash_ext_params *p =\n\t\t(struct rte_table_hash_ext_params *) params;\n\tstruct rte_table_hash *t;\n\tuint32_t total_size, table_meta_sz;\n\tuint32_t bucket_sz, bucket_ext_sz, key_sz;\n\tuint32_t key_stack_sz, bkt_ext_stack_sz, data_sz;\n\tuint32_t bucket_offset, bucket_ext_offset, key_offset;\n\tuint32_t key_stack_offset, bkt_ext_stack_offset, data_offset;\n\tuint32_t i;\n\n\t/* Check input parameters */\n\tif ((check_params_create(p) != 0) ||\n\t\t(!rte_is_power_of_2(entry_size)) ||\n\t\t((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||\n\t\t(sizeof(struct bucket) != (RTE_CACHE_LINE_SIZE / 2)))\n\t\treturn NULL;\n\n\t/* Memory allocation */\n\ttable_meta_sz = RTE_CACHE_LINE_ROUNDUP(sizeof(struct rte_table_hash));\n\tbucket_sz = RTE_CACHE_LINE_ROUNDUP(p->n_buckets * sizeof(struct bucket));\n\tbucket_ext_sz =\n\t\tRTE_CACHE_LINE_ROUNDUP(p->n_buckets_ext * sizeof(struct bucket));\n\tkey_sz = RTE_CACHE_LINE_ROUNDUP(p->n_keys * p->key_size);\n\tkey_stack_sz = RTE_CACHE_LINE_ROUNDUP(p->n_keys * sizeof(uint32_t));\n\tbkt_ext_stack_sz =\n\t\tRTE_CACHE_LINE_ROUNDUP(p->n_buckets_ext * sizeof(uint32_t));\n\tdata_sz = RTE_CACHE_LINE_ROUNDUP(p->n_keys * entry_size);\n\ttotal_size = table_meta_sz + bucket_sz + bucket_ext_sz + key_sz +\n\t\tkey_stack_sz + bkt_ext_stack_sz + data_sz;\n\n\tt = rte_zmalloc_socket(\"TABLE\", total_size, RTE_CACHE_LINE_SIZE, socket_id);\n\tif (t == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot allocate %u bytes for hash table\\n\",\n\t\t\t__func__, total_size);\n\t\treturn NULL;\n\t}\n\tRTE_LOG(INFO, TABLE, \"%s (%u-byte key): Hash table memory footprint is \"\n\t\t\"%u bytes\\n\", __func__, p->key_size, total_size);\n\n\t/* Memory initialization */\n\tt->key_size = p->key_size;\n\tt->entry_size = entry_size;\n\tt->n_keys = p->n_keys;\n\tt->n_buckets = p->n_buckets;\n\tt->n_buckets_ext = p->n_buckets_ext;\n\tt->f_hash = p->f_hash;\n\tt->seed = p->seed;\n\tt->signature_offset = p->signature_offset;\n\tt->key_offset = p->key_offset;\n\n\t/* Internal */\n\tt->bucket_mask = t->n_buckets - 1;\n\tt->key_size_shl = __builtin_ctzl(p->key_size);\n\tt->data_size_shl = __builtin_ctzl(entry_size);\n\n\t/* Tables */\n\tbucket_offset = 0;\n\tbucket_ext_offset = bucket_offset + bucket_sz;\n\tkey_offset = bucket_ext_offset + bucket_ext_sz;\n\tkey_stack_offset = key_offset + key_sz;\n\tbkt_ext_stack_offset = key_stack_offset + key_stack_sz;\n\tdata_offset = bkt_ext_stack_offset + bkt_ext_stack_sz;\n\n\tt->buckets = (struct bucket *) &t->memory[bucket_offset];\n\tt->buckets_ext = (struct bucket *) &t->memory[bucket_ext_offset];\n\tt->key_mem = &t->memory[key_offset];\n\tt->key_stack = (uint32_t *) &t->memory[key_stack_offset];\n\tt->bkt_ext_stack = (uint32_t *) &t->memory[bkt_ext_stack_offset];\n\tt->data_mem = &t->memory[data_offset];\n\n\t/* Key stack */\n\tfor (i = 0; i < t->n_keys; i++)\n\t\tt->key_stack[i] = t->n_keys - 1 - i;\n\tt->key_stack_tos = t->n_keys;\n\n\t/* Bucket ext stack */\n\tfor (i = 0; i < t->n_buckets_ext; i++)\n\t\tt->bkt_ext_stack[i] = t->n_buckets_ext - 1 - i;\n\tt->bkt_ext_stack_tos = t->n_buckets_ext;\n\n\treturn t;\n}\n\nstatic int\nrte_table_hash_ext_free(void *table)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\n\t/* Check input parameters */\n\tif (t == NULL)\n\t\treturn -EINVAL;\n\n\trte_free(t);\n\treturn 0;\n}\n\nstatic int\nrte_table_hash_ext_entry_add(void *table, void *key, void *entry,\n\tint *key_found, void **entry_ptr)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\tstruct bucket *bkt0, *bkt, *bkt_prev;\n\tuint64_t sig;\n\tuint32_t bkt_index, i;\n\n\tsig = t->f_hash(key, t->key_size, t->seed);\n\tbkt_index = sig & t->bucket_mask;\n\tbkt0 = &t->buckets[bkt_index];\n\tsig = (sig >> 16) | 1LLU;\n\n\t/* Key is present in the bucket */\n\tfor (bkt = bkt0; bkt != NULL; bkt = BUCKET_NEXT(bkt))\n\t\tfor (i = 0; i < KEYS_PER_BUCKET; i++) {\n\t\t\tuint64_t bkt_sig = (uint64_t) bkt->sig[i];\n\t\t\tuint32_t bkt_key_index = bkt->key_pos[i];\n\t\t\tuint8_t *bkt_key =\n\t\t\t\t&t->key_mem[bkt_key_index << t->key_size_shl];\n\n\t\t\tif ((sig == bkt_sig) && (memcmp(key, bkt_key,\n\t\t\t\tt->key_size) == 0)) {\n\t\t\t\tuint8_t *data = &t->data_mem[bkt_key_index <<\n\t\t\t\t\tt->data_size_shl];\n\n\t\t\t\tmemcpy(data, entry, t->entry_size);\n\t\t\t\t*key_found = 1;\n\t\t\t\t*entry_ptr = (void *) data;\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\n\t/* Key is not present in the bucket */\n\tfor (bkt_prev = NULL, bkt = bkt0; bkt != NULL; bkt_prev = bkt,\n\t\tbkt = BUCKET_NEXT(bkt))\n\t\tfor (i = 0; i < KEYS_PER_BUCKET; i++) {\n\t\t\tuint64_t bkt_sig = (uint64_t) bkt->sig[i];\n\n\t\t\tif (bkt_sig == 0) {\n\t\t\t\tuint32_t bkt_key_index;\n\t\t\t\tuint8_t *bkt_key, *data;\n\n\t\t\t\t/* Allocate new key */\n\t\t\t\tif (t->key_stack_tos == 0) /* No free keys */\n\t\t\t\t\treturn -ENOSPC;\n\n\t\t\t\tbkt_key_index = t->key_stack[\n\t\t\t\t\t--t->key_stack_tos];\n\n\t\t\t\t/* Install new key */\n\t\t\t\tbkt_key = &t->key_mem[bkt_key_index <<\n\t\t\t\t\tt->key_size_shl];\n\t\t\t\tdata = &t->data_mem[bkt_key_index <<\n\t\t\t\t\tt->data_size_shl];\n\n\t\t\t\tbkt->sig[i] = (uint16_t) sig;\n\t\t\t\tbkt->key_pos[i] = bkt_key_index;\n\t\t\t\tmemcpy(bkt_key, key, t->key_size);\n\t\t\t\tmemcpy(data, entry, t->entry_size);\n\n\t\t\t\t*key_found = 0;\n\t\t\t\t*entry_ptr = (void *) data;\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\n\t/* Bucket full: extend bucket */\n\tif ((t->bkt_ext_stack_tos > 0) && (t->key_stack_tos > 0)) {\n\t\tuint32_t bkt_key_index;\n\t\tuint8_t *bkt_key, *data;\n\n\t\t/* Allocate new bucket ext */\n\t\tbkt_index = t->bkt_ext_stack[--t->bkt_ext_stack_tos];\n\t\tbkt = &t->buckets_ext[bkt_index];\n\n\t\t/* Chain the new bucket ext */\n\t\tBUCKET_NEXT_SET(bkt_prev, bkt);\n\t\tBUCKET_NEXT_SET_NULL(bkt);\n\n\t\t/* Allocate new key */\n\t\tbkt_key_index = t->key_stack[--t->key_stack_tos];\n\t\tbkt_key = &t->key_mem[bkt_key_index << t->key_size_shl];\n\n\t\tdata = &t->data_mem[bkt_key_index << t->data_size_shl];\n\n\t\t/* Install new key into bucket */\n\t\tbkt->sig[0] = (uint16_t) sig;\n\t\tbkt->key_pos[0] = bkt_key_index;\n\t\tmemcpy(bkt_key, key, t->key_size);\n\t\tmemcpy(data, entry, t->entry_size);\n\n\t\t*key_found = 0;\n\t\t*entry_ptr = (void *) data;\n\t\treturn 0;\n\t}\n\n\treturn -ENOSPC;\n}\n\nstatic int\nrte_table_hash_ext_entry_delete(void *table, void *key, int *key_found,\nvoid *entry)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\tstruct bucket *bkt0, *bkt, *bkt_prev;\n\tuint64_t sig;\n\tuint32_t bkt_index, i;\n\n\tsig = t->f_hash(key, t->key_size, t->seed);\n\tbkt_index = sig & t->bucket_mask;\n\tbkt0 = &t->buckets[bkt_index];\n\tsig = (sig >> 16) | 1LLU;\n\n\t/* Key is present in the bucket */\n\tfor (bkt_prev = NULL, bkt = bkt0; bkt != NULL; bkt_prev = bkt,\n\t\tbkt = BUCKET_NEXT(bkt))\n\t\tfor (i = 0; i < KEYS_PER_BUCKET; i++) {\n\t\t\tuint64_t bkt_sig = (uint64_t) bkt->sig[i];\n\t\t\tuint32_t bkt_key_index = bkt->key_pos[i];\n\t\t\tuint8_t *bkt_key = &t->key_mem[bkt_key_index <<\n\t\t\t\tt->key_size_shl];\n\n\t\t\tif ((sig == bkt_sig) && (memcmp(key, bkt_key,\n\t\t\t\tt->key_size) == 0)) {\n\t\t\t\tuint8_t *data = &t->data_mem[bkt_key_index <<\n\t\t\t\t\tt->data_size_shl];\n\n\t\t\t\t/* Uninstall key from bucket */\n\t\t\t\tbkt->sig[i] = 0;\n\t\t\t\t*key_found = 1;\n\t\t\t\tif (entry)\n\t\t\t\t\tmemcpy(entry, data, t->entry_size);\n\n\t\t\t\t/* Free key */\n\t\t\t\tt->key_stack[t->key_stack_tos++] =\n\t\t\t\t\tbkt_key_index;\n\n\t\t\t\t/*Check if bucket is unused */\n\t\t\t\tif ((bkt_prev != NULL) &&\n\t\t\t\t (bkt->sig[0] == 0) && (bkt->sig[1] == 0) &&\n\t\t\t\t (bkt->sig[2] == 0) && (bkt->sig[3] == 0)) {\n\t\t\t\t\t/* Unchain bucket */\n\t\t\t\t\tBUCKET_NEXT_COPY(bkt_prev, bkt);\n\n\t\t\t\t\t/* Clear bucket */\n\t\t\t\t\tmemset(bkt, 0, sizeof(struct bucket));\n\n\t\t\t\t\t/* Free bucket back to buckets ext */\n\t\t\t\t\tbkt_index = bkt - t->buckets_ext;\n\t\t\t\t\tt->bkt_ext_stack[t->bkt_ext_stack_tos++]\n\t\t\t\t\t\t= bkt_index;\n\t\t\t\t}\n\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\n\t/* Key is not present in the bucket */\n\t*key_found = 0;\n\treturn 0;\n}\n\nstatic int rte_table_hash_ext_lookup_unoptimized(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries,\n\tint dosig)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\tuint64_t pkts_mask_out = 0;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_EXT_STATS_PKTS_IN_ADD(t, n_pkts_in);\n\n\tfor ( ; pkts_mask; ) {\n\t\tstruct bucket *bkt0, *bkt;\n\t\tstruct rte_mbuf *pkt;\n\t\tuint8_t *key;\n\t\tuint64_t pkt_mask, sig;\n\t\tuint32_t pkt_index, bkt_index, i;\n\n\t\tpkt_index = __builtin_ctzll(pkts_mask);\n\t\tpkt_mask = 1LLU << pkt_index;\n\t\tpkts_mask &= ~pkt_mask;\n\n\t\tpkt = pkts[pkt_index];\n\t\tkey = RTE_MBUF_METADATA_UINT8_PTR(pkt, t->key_offset);\n\t\tif (dosig)\n\t\t\tsig = (uint64_t) t->f_hash(key, t->key_size, t->seed);\n\t\telse\n\t\t\tsig = RTE_MBUF_METADATA_UINT32(pkt,\n\t\t\t\tt->signature_offset);\n\n\t\tbkt_index = sig & t->bucket_mask;\n\t\tbkt0 = &t->buckets[bkt_index];\n\t\tsig = (sig >> 16) | 1LLU;\n\n\t\t/* Key is present in the bucket */\n\t\tfor (bkt = bkt0; bkt != NULL; bkt = BUCKET_NEXT(bkt))\n\t\t\tfor (i = 0; i < KEYS_PER_BUCKET; i++) {\n\t\t\t\tuint64_t bkt_sig = (uint64_t) bkt->sig[i];\n\t\t\t\tuint32_t bkt_key_index = bkt->key_pos[i];\n\t\t\t\tuint8_t *bkt_key = &t->key_mem[bkt_key_index <<\n\t\t\t\t\tt->key_size_shl];\n\n\t\t\t\tif ((sig == bkt_sig) && (memcmp(key, bkt_key,\n\t\t\t\t\tt->key_size) == 0)) {\n\t\t\t\t\tuint8_t *data = &t->data_mem[\n\t\t\t\t\tbkt_key_index << t->data_size_shl];\n\n\t\t\t\t\tpkts_mask_out |= pkt_mask;\n\t\t\t\t\tentries[pkt_index] = (void *) data;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t}\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_EXT_STATS_PKTS_LOOKUP_MISS(t, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn 0;\n}\n\n/***\n *\n * mask = match bitmask\n * match = at least one match\n * match_many = more than one match\n * match_pos = position of first match\n *\n *----------------------------------------\n * mask\t\t match\t match_many\t match_pos\n *----------------------------------------\n * 0000\t\t 0\t\t 0\t\t\t 00\n * 0001\t\t 1\t\t 0\t\t\t 00\n * 0010\t\t 1\t\t 0\t\t\t 01\n * 0011\t\t 1\t\t 1\t\t\t 00\n *----------------------------------------\n * 0100\t\t 1\t\t 0\t\t\t 10\n * 0101\t\t 1\t\t 1\t\t\t 00\n * 0110\t\t 1\t\t 1\t\t\t 01\n * 0111\t\t 1\t\t 1\t\t\t 00\n *----------------------------------------\n * 1000\t\t 1\t\t 0\t\t\t 11\n * 1001\t\t 1\t\t 1\t\t\t 00\n * 1010\t\t 1\t\t 1\t\t\t 01\n * 1011\t\t 1\t\t 1\t\t\t 00\n *----------------------------------------\n * 1100\t\t 1\t\t 1\t\t\t 10\n * 1101\t\t 1\t\t 1\t\t\t 00\n * 1110\t\t 1\t\t 1\t\t\t 01\n * 1111\t\t 1\t\t 1\t\t\t 00\n *----------------------------------------\n *\n * match = 1111_1111_1111_1110\n * match_many = 1111_1110_1110_1000\n * match_pos = 0001_0010_0001_0011__0001_0010_0001_0000\n *\n * match = 0xFFFELLU\n * match_many = 0xFEE8LLU\n * match_pos = 0x12131210LLU\n *\n ***/\n\n#define LUT_MATCH\t\t\t\t\t\t0xFFFELLU\n#define LUT_MATCH_MANY\t\t\t\t\t\t0xFEE8LLU\n#define LUT_MATCH_POS\t\t\t\t\t\t0x12131210LLU\n\n#define lookup_cmp_sig(mbuf_sig, bucket, match, match_many, match_pos)\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tuint64_t bucket_sig[4], mask[4], mask_all;\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tbucket_sig[0] = bucket->sig[0];\t\t\t\t\t\\\n\tbucket_sig[1] = bucket->sig[1];\t\t\t\t\t\\\n\tbucket_sig[2] = bucket->sig[2];\t\t\t\t\t\\\n\tbucket_sig[3] = bucket->sig[3];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tbucket_sig[0] ^= mbuf_sig;\t\t\t\t\t\\\n\tbucket_sig[1] ^= mbuf_sig;\t\t\t\t\t\\\n\tbucket_sig[2] ^= mbuf_sig;\t\t\t\t\t\\\n\tbucket_sig[3] ^= mbuf_sig;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tmask[0] = 0;\t\t\t\t\t\t\t\\\n\tmask[1] = 0;\t\t\t\t\t\t\t\\\n\tmask[2] = 0;\t\t\t\t\t\t\t\\\n\tmask[3] = 0;\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tif (bucket_sig[0] == 0)\t\t\t\t\t\t\\\n\t\tmask[0] = 1;\t\t\t\t\t\t\\\n\tif (bucket_sig[1] == 0)\t\t\t\t\t\t\\\n\t\tmask[1] = 2;\t\t\t\t\t\t\\\n\tif (bucket_sig[2] == 0)\t\t\t\t\t\t\\\n\t\tmask[2] = 4;\t\t\t\t\t\t\\\n\tif (bucket_sig[3] == 0)\t\t\t\t\t\t\\\n\t\tmask[3] = 8;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tmask_all = (mask[0] | mask[1]) | (mask[2] | mask[3]);\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tmatch = (LUT_MATCH >> mask_all) & 1;\t\t\t\t\\\n\tmatch_many = (LUT_MATCH_MANY >> mask_all) & 1;\t\t\t\\\n\tmatch_pos = (LUT_MATCH_POS >> (mask_all << 1)) & 3;\t\t\\\n}\n\n#define lookup_cmp_key(mbuf, key, match_key, f)\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tuint64_t *pkt_key = RTE_MBUF_METADATA_UINT64_PTR(mbuf, f->key_offset);\\\n\tuint64_t *bkt_key = (uint64_t *) key;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tswitch (f->key_size) {\t\t\t\t\t\t\\\n\tcase 8:\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\\\n\t\tuint64_t xor = pkt_key[0] ^ bkt_key[0];\t\t\t\\\n\t\tmatch_key = 0;\t\t\t\t\t\t\\\n\t\tif (xor == 0)\t\t\t\t\t\t\\\n\t\t\tmatch_key = 1;\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n\tbreak;\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tcase 16:\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\\\n\t\tuint64_t xor[2], or;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t\txor[0] = pkt_key[0] ^ bkt_key[0];\t\t\t\\\n\t\txor[1] = pkt_key[1] ^ bkt_key[1];\t\t\t\\\n\t\tor = xor[0] | xor[1];\t\t\t\t\t\\\n\t\tmatch_key = 0;\t\t\t\t\t\t\\\n\t\tif (or == 0)\t\t\t\t\t\t\\\n\t\t\tmatch_key = 1;\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n\tbreak;\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tcase 32:\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\\\n\t\tuint64_t xor[4], or;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t\txor[0] = pkt_key[0] ^ bkt_key[0];\t\t\t\\\n\t\txor[1] = pkt_key[1] ^ bkt_key[1];\t\t\t\\\n\t\txor[2] = pkt_key[2] ^ bkt_key[2];\t\t\t\\\n\t\txor[3] = pkt_key[3] ^ bkt_key[3];\t\t\t\\\n\t\tor = xor[0] | xor[1] | xor[2] | xor[3];\t\t\t\\\n\t\tmatch_key = 0;\t\t\t\t\t\t\\\n\t\tif (or == 0)\t\t\t\t\t\t\\\n\t\t\tmatch_key = 1;\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n\tbreak;\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tcase 64:\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\\\n\t\tuint64_t xor[8], or;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\t\txor[0] = pkt_key[0] ^ bkt_key[0];\t\t\t\\\n\t\txor[1] = pkt_key[1] ^ bkt_key[1];\t\t\t\\\n\t\txor[2] = pkt_key[2] ^ bkt_key[2];\t\t\t\\\n\t\txor[3] = pkt_key[3] ^ bkt_key[3];\t\t\t\\\n\t\txor[4] = pkt_key[4] ^ bkt_key[4];\t\t\t\\\n\t\txor[5] = pkt_key[5] ^ bkt_key[5];\t\t\t\\\n\t\txor[6] = pkt_key[6] ^ bkt_key[6];\t\t\t\\\n\t\txor[7] = pkt_key[7] ^ bkt_key[7];\t\t\t\\\n\t\tor = xor[0] | xor[1] | xor[2] | xor[3] |\t\t\\\n\t\t\txor[4] | xor[5] | xor[6] | xor[7];\t\t\\\n\t\tmatch_key = 0;\t\t\t\t\t\t\\\n\t\tif (or == 0)\t\t\t\t\t\t\\\n\t\t\tmatch_key = 1;\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n\tbreak;\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tdefault:\t\t\t\t\t\t\t\\\n\t\tmatch_key = 0;\t\t\t\t\t\t\\\n\t\tif (memcmp(pkt_key, bkt_key, f->key_size) == 0)\t\t\\\n\t\t\tmatch_key = 1;\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\\\n}\n\n#define lookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index)\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt00_mask, pkt01_mask;\t\t\t\t\\\n\tstruct rte_mbuf *mbuf00, *mbuf01;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tpkt00_index = __builtin_ctzll(pkts_mask);\t\t\t\\\n\tpkt00_mask = 1LLU << pkt00_index;\t\t\t\t\\\n\tpkts_mask &= ~pkt00_mask;\t\t\t\t\t\\\n\tmbuf00 = pkts[pkt00_index];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tpkt01_index = __builtin_ctzll(pkts_mask);\t\t\t\\\n\tpkt01_mask = 1LLU << pkt01_index;\t\t\t\t\\\n\tpkts_mask &= ~pkt01_mask;\t\t\t\t\t\\\n\tmbuf01 = pkts[pkt01_index];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf00, 0));\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf01, 0));\t\t\\\n}\n\n#define lookup2_stage0_with_odd_support(t, g, pkts, pkts_mask, pkt00_index, \\\n\tpkt01_index)\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt00_mask, pkt01_mask;\t\t\t\t\\\n\tstruct rte_mbuf *mbuf00, *mbuf01;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tpkt00_index = __builtin_ctzll(pkts_mask);\t\t\t\\\n\tpkt00_mask = 1LLU << pkt00_index;\t\t\t\t\\\n\tpkts_mask &= ~pkt00_mask;\t\t\t\t\t\\\n\tmbuf00 = pkts[pkt00_index];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tpkt01_index = __builtin_ctzll(pkts_mask);\t\t\t\\\n\tif (pkts_mask == 0)\t\t\t\t\t\t\\\n\t\tpkt01_index = pkt00_index;\t\t\t\t\\\n\tpkt01_mask = 1LLU << pkt01_index;\t\t\t\t\\\n\tpkts_mask &= ~pkt01_mask;\t\t\t\t\t\\\n\tmbuf01 = pkts[pkt01_index];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf00, 0));\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf01, 0));\t\t\\\n}\n\n#define lookup2_stage1(t, g, pkts, pkt10_index, pkt11_index)\t\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tstruct grinder *g10, *g11;\t\t\t\t\t\\\n\tuint64_t sig10, sig11, bkt10_index, bkt11_index;\t\t\\\n\tstruct rte_mbuf *mbuf10, *mbuf11;\t\t\t\t\\\n\tstruct bucket *bkt10, *bkt11, *buckets = t->buckets;\t\t\\\n\tuint64_t bucket_mask = t->bucket_mask;\t\t\t\t\\\n\tuint32_t signature_offset = t->signature_offset;\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tmbuf10 = pkts[pkt10_index];\t\t\t\t\t\\\n\tsig10 = (uint64_t) RTE_MBUF_METADATA_UINT32(mbuf10, signature_offset);\\\n\tbkt10_index = sig10 & bucket_mask;\t\t\t\t\\\n\tbkt10 = &buckets[bkt10_index];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tmbuf11 = pkts[pkt11_index];\t\t\t\t\t\\\n\tsig11 = (uint64_t) RTE_MBUF_METADATA_UINT32(mbuf11, signature_offset);\\\n\tbkt11_index = sig11 & bucket_mask;\t\t\t\t\\\n\tbkt11 = &buckets[bkt11_index];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\trte_prefetch0(bkt10);\t\t\t\t\t\t\\\n\trte_prefetch0(bkt11);\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tg10 = &g[pkt10_index];\t\t\t\t\t\t\\\n\tg10->sig = sig10;\t\t\t\t\t\t\\\n\tg10->bkt = bkt10;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tg11 = &g[pkt11_index];\t\t\t\t\t\t\\\n\tg11->sig = sig11;\t\t\t\t\t\t\\\n\tg11->bkt = bkt11;\t\t\t\t\t\t\\\n}\n\n#define lookup2_stage1_dosig(t, g, pkts, pkt10_index, pkt11_index)\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tstruct grinder *g10, *g11;\t\t\t\t\t\\\n\tuint64_t sig10, sig11, bkt10_index, bkt11_index;\t\t\\\n\tstruct rte_mbuf *mbuf10, *mbuf11;\t\t\t\t\\\n\tstruct bucket *bkt10, *bkt11, *buckets = t->buckets;\t\t\\\n\tuint8_t *key10, *key11;\t\t\t\t\t\t\\\n\tuint64_t bucket_mask = t->bucket_mask;\t\t\t\t\\\n\trte_table_hash_op_hash f_hash = t->f_hash;\t\t\t\\\n\tuint64_t seed = t->seed;\t\t\t\t\t\\\n\tuint32_t key_size = t->key_size;\t\t\t\t\\\n\tuint32_t key_offset = t->key_offset;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tmbuf10 = pkts[pkt10_index];\t\t\t\t\t\\\n\tkey10 = RTE_MBUF_METADATA_UINT8_PTR(mbuf10, key_offset);\t\\\n\tsig10 = (uint64_t) f_hash(key10, key_size, seed);\t\t\\\n\tbkt10_index = sig10 & bucket_mask;\t\t\t\t\\\n\tbkt10 = &buckets[bkt10_index];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tmbuf11 = pkts[pkt11_index];\t\t\t\t\t\\\n\tkey11 = RTE_MBUF_METADATA_UINT8_PTR(mbuf11, key_offset);\t\\\n\tsig11 = (uint64_t) f_hash(key11, key_size, seed);\t\t\\\n\tbkt11_index = sig11 & bucket_mask;\t\t\t\t\\\n\tbkt11 = &buckets[bkt11_index];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\trte_prefetch0(bkt10);\t\t\t\t\t\t\\\n\trte_prefetch0(bkt11);\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tg10 = &g[pkt10_index];\t\t\t\t\t\t\\\n\tg10->sig = sig10;\t\t\t\t\t\t\\\n\tg10->bkt = bkt10;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tg11 = &g[pkt11_index];\t\t\t\t\t\t\\\n\tg11->sig = sig11;\t\t\t\t\t\t\\\n\tg11->bkt = bkt11;\t\t\t\t\t\t\\\n}\n\n#define lookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many)\\\n{\t\t\t\t\t\t\t\t\t\\\n\tstruct grinder *g20, *g21;\t\t\t\t\t\\\n\tuint64_t sig20, sig21;\t\t\t\t\t\t\\\n\tstruct bucket *bkt20, *bkt21;\t\t\t\t\t\\\n\tuint8_t *key20, *key21, *key_mem = t->key_mem;\t\t\t\\\n\tuint64_t match20, match21, match_many20, match_many21;\t\t\\\n\tuint64_t match_pos20, match_pos21;\t\t\t\t\\\n\tuint32_t key20_index, key21_index, key_size_shl = t->key_size_shl;\\\n\t\t\t\t\t\t\t\t\t\\\n\tg20 = &g[pkt20_index];\t\t\t\t\t\t\\\n\tsig20 = g20->sig;\t\t\t\t\t\t\\\n\tbkt20 = g20->bkt;\t\t\t\t\t\t\\\n\tsig20 = (sig20 >> 16) | 1LLU;\t\t\t\t\t\\\n\tlookup_cmp_sig(sig20, bkt20, match20, match_many20, match_pos20);\\\n\tmatch20 <<= pkt20_index;\t\t\t\t\t\\\n\tmatch_many20 |= BUCKET_NEXT_VALID(bkt20);\t\t\t\\\n\tmatch_many20 <<= pkt20_index;\t\t\t\t\t\\\n\tkey20_index = bkt20->key_pos[match_pos20];\t\t\t\\\n\tkey20 = &key_mem[key20_index << key_size_shl];\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tg21 = &g[pkt21_index];\t\t\t\t\t\t\\\n\tsig21 = g21->sig;\t\t\t\t\t\t\\\n\tbkt21 = g21->bkt;\t\t\t\t\t\t\\\n\tsig21 = (sig21 >> 16) | 1LLU;\t\t\t\t\t\\\n\tlookup_cmp_sig(sig21, bkt21, match21, match_many21, match_pos21);\\\n\tmatch21 <<= pkt21_index;\t\t\t\t\t\\\n\tmatch_many21 |= BUCKET_NEXT_VALID(bkt21);\t\t\t\\\n\tmatch_many21 <<= pkt21_index;\t\t\t\t\t\\\n\tkey21_index = bkt21->key_pos[match_pos21];\t\t\t\\\n\tkey21 = &key_mem[key21_index << key_size_shl];\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\trte_prefetch0(key20);\t\t\t\t\t\t\\\n\trte_prefetch0(key21);\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tpkts_mask_match_many |= match_many20 | match_many21;\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tg20->match = match20;\t\t\t\t\t\t\\\n\tg20->key_index = key20_index;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tg21->match = match21;\t\t\t\t\t\t\\\n\tg21->key_index = key21_index;\t\t\t\t\t\\\n}\n\n#define lookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out, \\\n\tentries)\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\\\n\tstruct grinder *g30, *g31;\t\t\t\t\t\\\n\tstruct rte_mbuf *mbuf30, *mbuf31;\t\t\t\t\\\n\tuint8_t *key30, *key31, *key_mem = t->key_mem;\t\t\t\\\n\tuint8_t *data30, *data31, *data_mem = t->data_mem;\t\t\\\n\tuint64_t match30, match31, match_key30, match_key31, match_keys;\\\n\tuint32_t key30_index, key31_index;\t\t\t\t\\\n\tuint32_t key_size_shl = t->key_size_shl;\t\t\t\\\n\tuint32_t data_size_shl = t->data_size_shl;\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tmbuf30 = pkts[pkt30_index];\t\t\t\t\t\\\n\tg30 = &g[pkt30_index];\t\t\t\t\t\t\\\n\tmatch30 = g30->match;\t\t\t\t\t\t\\\n\tkey30_index = g30->key_index;\t\t\t\t\t\\\n\tkey30 = &key_mem[key30_index << key_size_shl];\t\t\t\\\n\tlookup_cmp_key(mbuf30, key30, match_key30, t);\t\t\t\\\n\tmatch_key30 <<= pkt30_index;\t\t\t\t\t\\\n\tmatch_key30 &= match30;\t\t\t\t\t\t\\\n\tdata30 = &data_mem[key30_index << data_size_shl];\t\t\\\n\tentries[pkt30_index] = data30;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tmbuf31 = pkts[pkt31_index];\t\t\t\t\t\\\n\tg31 = &g[pkt31_index];\t\t\t\t\t\t\\\n\tmatch31 = g31->match;\t\t\t\t\t\t\\\n\tkey31_index = g31->key_index;\t\t\t\t\t\\\n\tkey31 = &key_mem[key31_index << key_size_shl];\t\t\t\\\n\tlookup_cmp_key(mbuf31, key31, match_key31, t);\t\t\t\\\n\tmatch_key31 <<= pkt31_index;\t\t\t\t\t\\\n\tmatch_key31 &= match31;\t\t\t\t\t\t\\\n\tdata31 = &data_mem[key31_index << data_size_shl];\t\t\\\n\tentries[pkt31_index] = data31;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\trte_prefetch0(data30);\t\t\t\t\t\t\\\n\trte_prefetch0(data31);\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\\\n\tmatch_keys = match_key30 | match_key31;\t\t\t\t\\\n\tpkts_mask_out |= match_keys;\t\t\t\t\t\\\n}\n\n/***\n* The lookup function implements a 4-stage pipeline, with each stage processing\n* two different packets. The purpose of pipelined implementation is to hide the\n* latency of prefetching the data structures and loosen the data dependency\n* between instructions.\n*\n* p00 _______ p10 _______ p20 _______ p30 _______\n*----->| |----->| |----->| |----->| |----->\n* | 0 | | 1 | | 2 | | 3 |\n*----->|_______|----->|_______|----->|_______|----->|_______|----->\n* p01 p11 p21 p31\n*\n* The naming convention is:\n* pXY = packet Y of stage X, X = 0 .. 3, Y = 0 .. 1\n*\n***/\nstatic int rte_table_hash_ext_lookup(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\tstruct grinder *g = t->grinders;\n\tuint64_t pkt00_index, pkt01_index, pkt10_index, pkt11_index;\n\tuint64_t pkt20_index, pkt21_index, pkt30_index, pkt31_index;\n\tuint64_t pkts_mask_out = 0, pkts_mask_match_many = 0;\n\tint status = 0;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_EXT_STATS_PKTS_IN_ADD(t, n_pkts_in);\n\n\t/* Cannot run the pipeline with less than 7 packets */\n\tif (__builtin_popcountll(pkts_mask) < 7)\n\t\treturn rte_table_hash_ext_lookup_unoptimized(table, pkts,\n\t\t\tpkts_mask, lookup_hit_mask, entries, 0);\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index);\n\n\t/* Pipeline feed */\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(t, g, pkts, pkt10_index, pkt11_index);\n\n\t/* Pipeline feed */\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(t, g, pkts, pkt10_index, pkt11_index);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many);\n\n\t/*\n\t* Pipeline run\n\t*\n\t*/\n\tfor ( ; pkts_mask; ) {\n\t\t/* Pipeline feed */\n\t\tpkt30_index = pkt20_index;\n\t\tpkt31_index = pkt21_index;\n\t\tpkt20_index = pkt10_index;\n\t\tpkt21_index = pkt11_index;\n\t\tpkt10_index = pkt00_index;\n\t\tpkt11_index = pkt01_index;\n\n\t\t/* Pipeline stage 0 */\n\t\tlookup2_stage0_with_odd_support(t, g, pkts, pkts_mask,\n\t\t\tpkt00_index, pkt01_index);\n\n\t\t/* Pipeline stage 1 */\n\t\tlookup2_stage1(t, g, pkts, pkt10_index, pkt11_index);\n\n\t\t/* Pipeline stage 2 */\n\t\tlookup2_stage2(t, g, pkt20_index, pkt21_index,\n\t\t\tpkts_mask_match_many);\n\n\t\t/* Pipeline stage 3 */\n\t\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index,\n\t\t\tpkts_mask_out, entries);\n\t}\n\n\t/* Pipeline feed */\n\tpkt30_index = pkt20_index;\n\tpkt31_index = pkt21_index;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(t, g, pkts, pkt10_index, pkt11_index);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many);\n\n\t/* Pipeline stage 3 */\n\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out,\n\t\tentries);\n\n\t/* Pipeline feed */\n\tpkt30_index = pkt20_index;\n\tpkt31_index = pkt21_index;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many);\n\n\t/* Pipeline stage 3 */\n\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out,\n\t\tentries);\n\n\t/* Pipeline feed */\n\tpkt30_index = pkt20_index;\n\tpkt31_index = pkt21_index;\n\n\t/* Pipeline stage 3 */\n\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out,\n\t\tentries);\n\n\t/* Slow path */\n\tpkts_mask_match_many &= ~pkts_mask_out;\n\tif (pkts_mask_match_many) {\n\t\tuint64_t pkts_mask_out_slow = 0;\n\n\t\tstatus = rte_table_hash_ext_lookup_unoptimized(table, pkts,\n\t\t\tpkts_mask_match_many, &pkts_mask_out_slow, entries, 0);\n\t\tpkts_mask_out |= pkts_mask_out_slow;\n\t}\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_EXT_STATS_PKTS_LOOKUP_MISS(t, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn status;\n}\n\nstatic int rte_table_hash_ext_lookup_dosig(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\tstruct grinder *g = t->grinders;\n\tuint64_t pkt00_index, pkt01_index, pkt10_index, pkt11_index;\n\tuint64_t pkt20_index, pkt21_index, pkt30_index, pkt31_index;\n\tuint64_t pkts_mask_out = 0, pkts_mask_match_many = 0;\n\tint status = 0;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_EXT_STATS_PKTS_IN_ADD(t, n_pkts_in);\n\n\t/* Cannot run the pipeline with less than 7 packets */\n\tif (__builtin_popcountll(pkts_mask) < 7)\n\t\treturn rte_table_hash_ext_lookup_unoptimized(table, pkts,\n\t\t\tpkts_mask, lookup_hit_mask, entries, 1);\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index);\n\n\t/* Pipeline feed */\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1_dosig(t, g, pkts, pkt10_index, pkt11_index);\n\n\t/* Pipeline feed */\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1_dosig(t, g, pkts, pkt10_index, pkt11_index);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many);\n\n\t/*\n\t* Pipeline run\n\t*\n\t*/\n\tfor ( ; pkts_mask; ) {\n\t\t/* Pipeline feed */\n\t\tpkt30_index = pkt20_index;\n\t\tpkt31_index = pkt21_index;\n\t\tpkt20_index = pkt10_index;\n\t\tpkt21_index = pkt11_index;\n\t\tpkt10_index = pkt00_index;\n\t\tpkt11_index = pkt01_index;\n\n\t\t/* Pipeline stage 0 */\n\t\tlookup2_stage0_with_odd_support(t, g, pkts, pkts_mask,\n\t\t\tpkt00_index, pkt01_index);\n\n\t\t/* Pipeline stage 1 */\n\t\tlookup2_stage1_dosig(t, g, pkts, pkt10_index, pkt11_index);\n\n\t\t/* Pipeline stage 2 */\n\t\tlookup2_stage2(t, g, pkt20_index, pkt21_index,\n\t\t\tpkts_mask_match_many);\n\n\t\t/* Pipeline stage 3 */\n\t\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index,\n\t\t\tpkts_mask_out, entries);\n\t}\n\n\t/* Pipeline feed */\n\tpkt30_index = pkt20_index;\n\tpkt31_index = pkt21_index;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1_dosig(t, g, pkts, pkt10_index, pkt11_index);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many);\n\n\t/* Pipeline stage 3 */\n\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out,\n\t\tentries);\n\n\t/* Pipeline feed */\n\tpkt30_index = pkt20_index;\n\tpkt31_index = pkt21_index;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many);\n\n\t/* Pipeline stage 3 */\n\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out,\n\t\tentries);\n\n\t/* Pipeline feed */\n\tpkt30_index = pkt20_index;\n\tpkt31_index = pkt21_index;\n\n\t/* Pipeline stage 3 */\n\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out,\n\t\tentries);\n\n\t/* Slow path */\n\tpkts_mask_match_many &= ~pkts_mask_out;\n\tif (pkts_mask_match_many) {\n\t\tuint64_t pkts_mask_out_slow = 0;\n\n\t\tstatus = rte_table_hash_ext_lookup_unoptimized(table, pkts,\n\t\t\tpkts_mask_match_many, &pkts_mask_out_slow, entries, 1);\n\t\tpkts_mask_out |= pkts_mask_out_slow;\n\t}\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_EXT_STATS_PKTS_LOOKUP_MISS(t, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn status;\n}\n\nstatic int\nrte_table_hash_ext_stats_read(void *table, struct rte_table_stats *stats, int clear)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &t->stats, sizeof(t->stats));\n\n\tif (clear)\n\t\tmemset(&t->stats, 0, sizeof(t->stats));\n\n\treturn 0;\n}\n\nstruct rte_table_ops rte_table_hash_ext_ops\t = {\n\t.f_create = rte_table_hash_ext_create,\n\t.f_free = rte_table_hash_ext_free,\n\t.f_add = rte_table_hash_ext_entry_add,\n\t.f_delete = rte_table_hash_ext_entry_delete,\n\t.f_lookup = rte_table_hash_ext_lookup,\n\t.f_stats = rte_table_hash_ext_stats_read,\n};\n\nstruct rte_table_ops rte_table_hash_ext_dosig_ops = {\n\t.f_create = rte_table_hash_ext_create,\n\t.f_free = rte_table_hash_ext_free,\n\t.f_add = rte_table_hash_ext_entry_add,\n\t.f_delete = rte_table_hash_ext_entry_delete,\n\t.f_lookup = rte_table_hash_ext_lookup_dosig,\n\t.f_stats = rte_table_hash_ext_stats_read,\n};\n" }, { "path": "lib/librte_table/rte_table_hash_key16.c", "content": "/*-\n *\t BSD LICENSE\n *\n *\t Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\t All rights reserved.\n *\n *\t Redistribution and use in source and binary forms, with or without\n *\t modification, are permitted provided that the following conditions\n *\t are met:\n *\n *\t* Redistributions of source code must retain the above copyright\n *\t\t notice, this list of conditions and the following disclaimer.\n *\t* Redistributions in binary form must reproduce the above copyright\n *\t\t notice, this list of conditions and the following disclaimer in\n *\t\t the documentation and/or other materials provided with the\n *\t\t distribution.\n *\t* Neither the name of Intel Corporation nor the names of its\n *\t\t contributors may be used to endorse or promote products derived\n *\t\t from this software without specific prior written permission.\n *\n *\t THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n *\t \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n *\t LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n *\t A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n *\t OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n *\t SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n *\t LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n *\t DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n *\t THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n *\t (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n *\t OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_table_hash.h\"\n#include \"rte_lru.h\"\n\n#define RTE_TABLE_HASH_KEY_SIZE\t\t\t\t\t\t16\n\n#define RTE_BUCKET_ENTRY_VALID\t\t\t\t\t\t0x1LLU\n\n#ifdef RTE_TABLE_STATS_COLLECT\n\n#define RTE_TABLE_HASH_KEY16_STATS_PKTS_IN_ADD(table, val) \\\n\ttable->stats.n_pkts_in += val\n#define RTE_TABLE_HASH_KEY16_STATS_PKTS_LOOKUP_MISS(table, val) \\\n\ttable->stats.n_pkts_lookup_miss += val\n\n#else\n\n#define RTE_TABLE_HASH_KEY16_STATS_PKTS_IN_ADD(table, val)\n#define RTE_TABLE_HASH_KEY16_STATS_PKTS_LOOKUP_MISS(table, val)\n\n#endif\n\nstruct rte_bucket_4_16 {\n\t/* Cache line 0 */\n\tuint64_t signature[4 + 1];\n\tuint64_t lru_list;\n\tstruct rte_bucket_4_16 *next;\n\tuint64_t next_valid;\n\n\t/* Cache line 1 */\n\tuint64_t key[4][2];\n\n\t/* Cache line 2 */\n\tuint8_t data[0];\n};\n\nstruct rte_table_hash {\n\tstruct rte_table_stats stats;\n\n\t/* Input parameters */\n\tuint32_t n_buckets;\n\tuint32_t n_entries_per_bucket;\n\tuint32_t key_size;\n\tuint32_t entry_size;\n\tuint32_t bucket_size;\n\tuint32_t signature_offset;\n\tuint32_t key_offset;\n\trte_table_hash_op_hash f_hash;\n\tuint64_t seed;\n\n\t/* Extendible buckets */\n\tuint32_t n_buckets_ext;\n\tuint32_t stack_pos;\n\tuint32_t *stack;\n\n\t/* Lookup table */\n\tuint8_t memory[0] __rte_cache_aligned;\n};\n\nstatic int\ncheck_params_create_lru(struct rte_table_hash_key16_lru_params *params) {\n\t/* n_entries */\n\tif (params->n_entries == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_entries is zero\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* f_hash */\n\tif (params->f_hash == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: f_hash function pointer is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic void *\nrte_table_hash_create_key16_lru(void *params,\n\t\tint socket_id,\n\t\tuint32_t entry_size)\n{\n\tstruct rte_table_hash_key16_lru_params *p =\n\t\t\t(struct rte_table_hash_key16_lru_params *) params;\n\tstruct rte_table_hash *f;\n\tuint32_t n_buckets, n_entries_per_bucket,\n\t\t\tkey_size, bucket_size_cl, total_size, i;\n\n\t/* Check input parameters */\n\tif ((check_params_create_lru(p) != 0) ||\n\t\t((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||\n\t\t((sizeof(struct rte_bucket_4_16) % RTE_CACHE_LINE_SIZE) != 0))\n\t\treturn NULL;\n\tn_entries_per_bucket = 4;\n\tkey_size = 16;\n\n\t/* Memory allocation */\n\tn_buckets = rte_align32pow2((p->n_entries + n_entries_per_bucket - 1) /\n\t\tn_entries_per_bucket);\n\tbucket_size_cl = (sizeof(struct rte_bucket_4_16) + n_entries_per_bucket\n\t\t* entry_size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;\n\ttotal_size = sizeof(struct rte_table_hash) + n_buckets *\n\t\tbucket_size_cl * RTE_CACHE_LINE_SIZE;\n\n\tf = rte_zmalloc_socket(\"TABLE\", total_size, RTE_CACHE_LINE_SIZE, socket_id);\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\"%s: Cannot allocate %u bytes for hash table\\n\",\n\t\t__func__, total_size);\n\t\treturn NULL;\n\t}\n\tRTE_LOG(INFO, TABLE,\n\t\t\"%s: Hash table memory footprint is %u bytes\\n\",\n\t\t__func__, total_size);\n\n\t/* Memory initialization */\n\tf->n_buckets = n_buckets;\n\tf->n_entries_per_bucket = n_entries_per_bucket;\n\tf->key_size = key_size;\n\tf->entry_size = entry_size;\n\tf->bucket_size = bucket_size_cl * RTE_CACHE_LINE_SIZE;\n\tf->signature_offset = p->signature_offset;\n\tf->key_offset = p->key_offset;\n\tf->f_hash = p->f_hash;\n\tf->seed = p->seed;\n\n\tfor (i = 0; i < n_buckets; i++) {\n\t\tstruct rte_bucket_4_16 *bucket;\n\n\t\tbucket = (struct rte_bucket_4_16 *) &f->memory[i *\n\t\t\tf->bucket_size];\n\t\tlru_init(bucket);\n\t}\n\n\treturn f;\n}\n\nstatic int\nrte_table_hash_free_key16_lru(void *table)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\n\t/* Check input parameters */\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_free(f);\n\treturn 0;\n}\n\nstatic int\nrte_table_hash_entry_add_key16_lru(\n\tvoid *table,\n\tvoid *key,\n\tvoid *entry,\n\tint *key_found,\n\tvoid **entry_ptr)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_16 *bucket;\n\tuint64_t signature, pos;\n\tuint32_t bucket_index, i;\n\n\tsignature = f->f_hash(key, f->key_size, f->seed);\n\tbucket_index = signature & (f->n_buckets - 1);\n\tbucket = (struct rte_bucket_4_16 *)\n\t\t\t&f->memory[bucket_index * f->bucket_size];\n\tsignature |= RTE_BUCKET_ENTRY_VALID;\n\n\t/* Key is present in the bucket */\n\tfor (i = 0; i < 4; i++) {\n\t\tuint64_t bucket_signature = bucket->signature[i];\n\t\tuint8_t *bucket_key = (uint8_t *) bucket->key[i];\n\n\t\tif ((bucket_signature == signature) &&\n\t\t\t\t(memcmp(key, bucket_key, f->key_size) == 0)) {\n\t\t\tuint8_t *bucket_data = &bucket->data[i * f->entry_size];\n\n\t\t\tmemcpy(bucket_data, entry, f->entry_size);\n\t\t\tlru_update(bucket, i);\n\t\t\t*key_found = 1;\n\t\t\t*entry_ptr = (void *) bucket_data;\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Key is not present in the bucket */\n\tfor (i = 0; i < 4; i++) {\n\t\tuint64_t bucket_signature = bucket->signature[i];\n\t\tuint8_t *bucket_key = (uint8_t *) bucket->key[i];\n\n\t\tif (bucket_signature == 0) {\n\t\t\tuint8_t *bucket_data = &bucket->data[i * f->entry_size];\n\n\t\t\tbucket->signature[i] = signature;\n\t\t\tmemcpy(bucket_key, key, f->key_size);\n\t\t\tmemcpy(bucket_data, entry, f->entry_size);\n\t\t\tlru_update(bucket, i);\n\t\t\t*key_found = 0;\n\t\t\t*entry_ptr = (void *) bucket_data;\n\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Bucket full: replace LRU entry */\n\tpos = lru_pos(bucket);\n\tbucket->signature[pos] = signature;\n\tmemcpy(bucket->key[pos], key, f->key_size);\n\tmemcpy(&bucket->data[pos * f->entry_size], entry, f->entry_size);\n\tlru_update(bucket, pos);\n\t*key_found = 0;\n\t*entry_ptr = (void *) &bucket->data[pos * f->entry_size];\n\n\treturn 0;\n}\n\nstatic int\nrte_table_hash_entry_delete_key16_lru(\n\tvoid *table,\n\tvoid *key,\n\tint *key_found,\n\tvoid *entry)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_16 *bucket;\n\tuint64_t signature;\n\tuint32_t bucket_index, i;\n\n\tsignature = f->f_hash(key, f->key_size, f->seed);\n\tbucket_index = signature & (f->n_buckets - 1);\n\tbucket = (struct rte_bucket_4_16 *)\n\t\t\t&f->memory[bucket_index * f->bucket_size];\n\tsignature |= RTE_BUCKET_ENTRY_VALID;\n\n\t/* Key is present in the bucket */\n\tfor (i = 0; i < 4; i++) {\n\t\tuint64_t bucket_signature = bucket->signature[i];\n\t\tuint8_t *bucket_key = (uint8_t *) bucket->key[i];\n\n\t\tif ((bucket_signature == signature) &&\n\t\t\t\t(memcmp(key, bucket_key, f->key_size) == 0)) {\n\t\t\tuint8_t *bucket_data = &bucket->data[i * f->entry_size];\n\n\t\t\tbucket->signature[i] = 0;\n\t\t\t*key_found = 1;\n\t\t\tif (entry)\n\t\t\t\tmemcpy(entry, bucket_data, f->entry_size);\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Key is not present in the bucket */\n\t*key_found = 0;\n\treturn 0;\n}\n\nstatic int\ncheck_params_create_ext(struct rte_table_hash_key16_ext_params *params) {\n\t/* n_entries */\n\tif (params->n_entries == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_entries is zero\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* n_entries_ext */\n\tif (params->n_entries_ext == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_entries_ext is zero\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* f_hash */\n\tif (params->f_hash == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: f_hash function pointer is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic void *\nrte_table_hash_create_key16_ext(void *params,\n\t\tint socket_id,\n\t\tuint32_t entry_size)\n{\n\tstruct rte_table_hash_key16_ext_params *p =\n\t\t\t(struct rte_table_hash_key16_ext_params *) params;\n\tstruct rte_table_hash *f;\n\tuint32_t n_buckets, n_buckets_ext, n_entries_per_bucket, key_size,\n\t\t\tbucket_size_cl, stack_size_cl, total_size, i;\n\n\t/* Check input parameters */\n\tif ((check_params_create_ext(p) != 0) ||\n\t\t((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||\n\t\t((sizeof(struct rte_bucket_4_16) % RTE_CACHE_LINE_SIZE) != 0))\n\t\treturn NULL;\n\n\tn_entries_per_bucket = 4;\n\tkey_size = 16;\n\n\t/* Memory allocation */\n\tn_buckets = rte_align32pow2((p->n_entries + n_entries_per_bucket - 1) /\n\t\tn_entries_per_bucket);\n\tn_buckets_ext = (p->n_entries_ext + n_entries_per_bucket - 1) /\n\t\tn_entries_per_bucket;\n\tbucket_size_cl = (sizeof(struct rte_bucket_4_16) + n_entries_per_bucket\n\t\t* entry_size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;\n\tstack_size_cl = (n_buckets_ext * sizeof(uint32_t) + RTE_CACHE_LINE_SIZE - 1)\n\t\t/ RTE_CACHE_LINE_SIZE;\n\ttotal_size = sizeof(struct rte_table_hash) +\n\t\t((n_buckets + n_buckets_ext) * bucket_size_cl + stack_size_cl) *\n\t\tRTE_CACHE_LINE_SIZE;\n\n\tf = rte_zmalloc_socket(\"TABLE\", total_size, RTE_CACHE_LINE_SIZE, socket_id);\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot allocate %u bytes for hash table\\n\",\n\t\t\t__func__, total_size);\n\t\treturn NULL;\n\t}\n\tRTE_LOG(INFO, TABLE,\n\t\t\"%s: Hash table memory footprint is %u bytes\\n\",\n\t\t__func__, total_size);\n\n\t/* Memory initialization */\n\tf->n_buckets = n_buckets;\n\tf->n_entries_per_bucket = n_entries_per_bucket;\n\tf->key_size = key_size;\n\tf->entry_size = entry_size;\n\tf->bucket_size = bucket_size_cl * RTE_CACHE_LINE_SIZE;\n\tf->signature_offset = p->signature_offset;\n\tf->key_offset = p->key_offset;\n\tf->f_hash = p->f_hash;\n\tf->seed = p->seed;\n\n\tf->n_buckets_ext = n_buckets_ext;\n\tf->stack_pos = n_buckets_ext;\n\tf->stack = (uint32_t *)\n\t\t&f->memory[(n_buckets + n_buckets_ext) * f->bucket_size];\n\n\tfor (i = 0; i < n_buckets_ext; i++)\n\t\tf->stack[i] = i;\n\n\treturn f;\n}\n\nstatic int\nrte_table_hash_free_key16_ext(void *table)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\n\t/* Check input parameters */\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_free(f);\n\treturn 0;\n}\n\nstatic int\nrte_table_hash_entry_add_key16_ext(\n\tvoid *table,\n\tvoid *key,\n\tvoid *entry,\n\tint *key_found,\n\tvoid **entry_ptr)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_16 *bucket0, *bucket, *bucket_prev;\n\tuint64_t signature;\n\tuint32_t bucket_index, i;\n\n\tsignature = f->f_hash(key, f->key_size, f->seed);\n\tbucket_index = signature & (f->n_buckets - 1);\n\tbucket0 = (struct rte_bucket_4_16 *)\n\t\t\t&f->memory[bucket_index * f->bucket_size];\n\tsignature |= RTE_BUCKET_ENTRY_VALID;\n\n\t/* Key is present in the bucket */\n\tfor (bucket = bucket0; bucket != NULL; bucket = bucket->next)\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tuint64_t bucket_signature = bucket->signature[i];\n\t\t\tuint8_t *bucket_key = (uint8_t *) bucket->key[i];\n\n\t\t\tif ((bucket_signature == signature) &&\n\t\t\t\t(memcmp(key, bucket_key, f->key_size) == 0)) {\n\t\t\t\tuint8_t *bucket_data = &bucket->data[i *\n\t\t\t\t\tf->entry_size];\n\n\t\t\t\tmemcpy(bucket_data, entry, f->entry_size);\n\t\t\t\t*key_found = 1;\n\t\t\t\t*entry_ptr = (void *) bucket_data;\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\n\t/* Key is not present in the bucket */\n\tfor (bucket_prev = NULL, bucket = bucket0; bucket != NULL;\n\t\t\t bucket_prev = bucket, bucket = bucket->next)\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tuint64_t bucket_signature = bucket->signature[i];\n\t\t\tuint8_t *bucket_key = (uint8_t *) bucket->key[i];\n\n\t\t\tif (bucket_signature == 0) {\n\t\t\t\tuint8_t *bucket_data = &bucket->data[i *\n\t\t\t\t\tf->entry_size];\n\n\t\t\t\tbucket->signature[i] = signature;\n\t\t\t\tmemcpy(bucket_key, key, f->key_size);\n\t\t\t\tmemcpy(bucket_data, entry, f->entry_size);\n\t\t\t\t*key_found = 0;\n\t\t\t\t*entry_ptr = (void *) bucket_data;\n\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\n\t/* Bucket full: extend bucket */\n\tif (f->stack_pos > 0) {\n\t\tbucket_index = f->stack[--f->stack_pos];\n\n\t\tbucket = (struct rte_bucket_4_16 *) &f->memory[(f->n_buckets +\n\t\t\tbucket_index) * f->bucket_size];\n\t\tbucket_prev->next = bucket;\n\t\tbucket_prev->next_valid = 1;\n\n\t\tbucket->signature[0] = signature;\n\t\tmemcpy(bucket->key[0], key, f->key_size);\n\t\tmemcpy(&bucket->data[0], entry, f->entry_size);\n\t\t*key_found = 0;\n\t\t*entry_ptr = (void *) &bucket->data[0];\n\t\treturn 0;\n\t}\n\n\treturn -ENOSPC;\n}\n\nstatic int\nrte_table_hash_entry_delete_key16_ext(\n\tvoid *table,\n\tvoid *key,\n\tint *key_found,\n\tvoid *entry)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_16 *bucket0, *bucket, *bucket_prev;\n\tuint64_t signature;\n\tuint32_t bucket_index, i;\n\n\tsignature = f->f_hash(key, f->key_size, f->seed);\n\tbucket_index = signature & (f->n_buckets - 1);\n\tbucket0 = (struct rte_bucket_4_16 *)\n\t\t&f->memory[bucket_index * f->bucket_size];\n\tsignature |= RTE_BUCKET_ENTRY_VALID;\n\n\t/* Key is present in the bucket */\n\tfor (bucket_prev = NULL, bucket = bucket0; bucket != NULL;\n\t\tbucket_prev = bucket, bucket = bucket->next)\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tuint64_t bucket_signature = bucket->signature[i];\n\t\t\tuint8_t *bucket_key = (uint8_t *) bucket->key[i];\n\n\t\t\tif ((bucket_signature == signature) &&\n\t\t\t\t(memcmp(key, bucket_key, f->key_size) == 0)) {\n\t\t\t\tuint8_t *bucket_data = &bucket->data[i *\n\t\t\t\t\tf->entry_size];\n\n\t\t\t\tbucket->signature[i] = 0;\n\t\t\t\t*key_found = 1;\n\t\t\t\tif (entry)\n\t\t\t\t\tmemcpy(entry, bucket_data,\n\t\t\t\t\tf->entry_size);\n\n\t\t\t\tif ((bucket->signature[0] == 0) &&\n\t\t\t\t\t(bucket->signature[1] == 0) &&\n\t\t\t\t\t(bucket->signature[2] == 0) &&\n\t\t\t\t\t(bucket->signature[3] == 0) &&\n\t\t\t\t\t(bucket_prev != NULL)) {\n\t\t\t\t\tbucket_prev->next = bucket->next;\n\t\t\t\t\tbucket_prev->next_valid =\n\t\t\t\t\t\tbucket->next_valid;\n\n\t\t\t\t\tmemset(bucket, 0,\n\t\t\t\t\t\tsizeof(struct rte_bucket_4_16));\n\t\t\t\t\tbucket_index = (((uint8_t *)bucket -\n\t\t\t\t\t\t(uint8_t *)f->memory)/f->bucket_size) - f->n_buckets;\n\t\t\t\t\tf->stack[f->stack_pos++] = bucket_index;\n\t\t\t\t}\n\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\n\t/* Key is not present in the bucket */\n\t*key_found = 0;\n\treturn 0;\n}\n\n#define lookup_key16_cmp(key_in, bucket, pos)\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t xor[4][2], or[4], signature[4];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tsignature[0] = (~bucket->signature[0]) & 1;\t\t\\\n\tsignature[1] = (~bucket->signature[1]) & 1;\t\t\\\n\tsignature[2] = (~bucket->signature[2]) & 1;\t\t\\\n\tsignature[3] = (~bucket->signature[3]) & 1;\t\t\\\n\t\t\t\t\t\t\t\t\\\n\txor[0][0] = key_in[0] ^\t bucket->key[0][0];\t\t\\\n\txor[0][1] = key_in[1] ^\t bucket->key[0][1];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\txor[1][0] = key_in[0] ^\t bucket->key[1][0];\t\t\\\n\txor[1][1] = key_in[1] ^\t bucket->key[1][1];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\txor[2][0] = key_in[0] ^\t bucket->key[2][0];\t\t\\\n\txor[2][1] = key_in[1] ^\t bucket->key[2][1];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\txor[3][0] = key_in[0] ^\t bucket->key[3][0];\t\t\\\n\txor[3][1] = key_in[1] ^\t bucket->key[3][1];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tor[0] = xor[0][0] | xor[0][1] | signature[0];\t\t\\\n\tor[1] = xor[1][0] | xor[1][1] | signature[1];\t\t\\\n\tor[2] = xor[2][0] | xor[2][1] | signature[2];\t\t\\\n\tor[3] = xor[3][0] | xor[3][1] | signature[3];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpos = 4;\t\t\t\t\t\t\\\n\tif (or[0] == 0)\t\t\t\t\t\t\\\n\t\tpos = 0;\t\t\t\t\t\\\n\tif (or[1] == 0)\t\t\t\t\t\t\\\n\t\tpos = 1;\t\t\t\t\t\\\n\tif (or[2] == 0)\t\t\t\t\t\t\\\n\t\tpos = 2;\t\t\t\t\t\\\n\tif (or[3] == 0)\t\t\t\t\t\t\\\n\t\tpos = 3;\t\t\t\t\t\\\n}\n\n#define lookup1_stage0(pkt0_index, mbuf0, pkts, pkts_mask)\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt_mask;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt0_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt_mask = 1LLU << pkt0_index;\t\t\t\t\\\n\tpkts_mask &= ~pkt_mask;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf0 = pkts[pkt0_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf0, 0));\t\\\n}\n\n#define lookup1_stage1(mbuf1, bucket1, f)\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t signature;\t\t\t\t\t\\\n\tuint32_t bucket_index;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tsignature = RTE_MBUF_METADATA_UINT32(mbuf1, f->signature_offset);\\\n\tbucket_index = signature & (f->n_buckets - 1);\t\t\\\n\tbucket1 = (struct rte_bucket_4_16 *)\t\t\t\\\n\t\t&f->memory[bucket_index * f->bucket_size];\t\\\n\trte_prefetch0(bucket1);\t\t\t\t\t\\\n\trte_prefetch0((void *)(((uintptr_t) bucket1) + RTE_CACHE_LINE_SIZE));\\\n}\n\n#define lookup1_stage2_lru(pkt2_index, mbuf2, bucket2,\t\t\\\n\t\tpkts_mask_out, entries, f)\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tvoid *a;\t\t\t\t\t\t\\\n\tuint64_t pkt_mask;\t\t\t\t\t\\\n\tuint64_t *key;\t\t\t\t\t\t\\\n\tuint32_t pos;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey = RTE_MBUF_METADATA_UINT64_PTR(mbuf2, f->key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key16_cmp(key, bucket2, pos);\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt_mask = (bucket2->signature[pos] & 1LLU) << pkt2_index;\\\n\tpkts_mask_out |= pkt_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta = (void *) &bucket2->data[pos * f->entry_size];\t\\\n\trte_prefetch0(a);\t\t\t\t\t\\\n\tentries[pkt2_index] = a;\t\t\t\t\\\n\tlru_update(bucket2, pos);\t\t\t\t\\\n}\n\n#define lookup1_stage2_ext(pkt2_index, mbuf2, bucket2, pkts_mask_out, entries, \\\n\tbuckets_mask, buckets, keys, f)\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tstruct rte_bucket_4_16 *bucket_next;\t\t\t\\\n\tvoid *a;\t\t\t\t\t\t\\\n\tuint64_t pkt_mask, bucket_mask;\t\t\t\t\\\n\tuint64_t *key;\t\t\t\t\t\t\\\n\tuint32_t pos;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey = RTE_MBUF_METADATA_UINT64_PTR(mbuf2, f->key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key16_cmp(key, bucket2, pos);\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt_mask = (bucket2->signature[pos] & 1LLU) << pkt2_index;\\\n\tpkts_mask_out |= pkt_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta = (void *) &bucket2->data[pos * f->entry_size];\t\\\n\trte_prefetch0(a);\t\t\t\t\t\\\n\tentries[pkt2_index] = a;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket_mask = (~pkt_mask) & (bucket2->next_valid << pkt2_index);\\\n\tbuckets_mask |= bucket_mask;\t\t\t\t\\\n\tbucket_next = bucket2->next;\t\t\t\t\\\n\tbuckets[pkt2_index] = bucket_next;\t\t\t\\\n\tkeys[pkt2_index] = key;\t\t\t\t\t\\\n}\n\n#define lookup_grinder(pkt_index, buckets, keys, pkts_mask_out, entries,\\\n\tbuckets_mask, f)\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tstruct rte_bucket_4_16 *bucket, *bucket_next;\t\t\\\n\tvoid *a;\t\t\t\t\t\t\\\n\tuint64_t pkt_mask, bucket_mask;\t\t\t\t\\\n\tuint64_t *key;\t\t\t\t\t\t\\\n\tuint32_t pos;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket = buckets[pkt_index];\t\t\t\t\\\n\tkey = keys[pkt_index];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key16_cmp(key, bucket, pos);\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt_mask = (bucket->signature[pos] & 1LLU) << pkt_index;\\\n\tpkts_mask_out |= pkt_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta = (void *) &bucket->data[pos * f->entry_size];\t\\\n\trte_prefetch0(a);\t\t\t\t\t\\\n\tentries[pkt_index] = a;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket_mask = (~pkt_mask) & (bucket->next_valid << pkt_index);\\\n\tbuckets_mask |= bucket_mask;\t\t\t\t\\\n\tbucket_next = bucket->next;\t\t\t\t\\\n\trte_prefetch0(bucket_next);\t\t\t\t\\\n\trte_prefetch0((void *)(((uintptr_t) bucket_next) + RTE_CACHE_LINE_SIZE));\\\n\tbuckets[pkt_index] = bucket_next;\t\t\t\\\n\tkeys[pkt_index] = key;\t\t\t\t\t\\\n}\n\n#define lookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01,\\\n\t\tpkts, pkts_mask)\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt00_mask, pkt01_mask;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt00_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt00_mask = 1LLU << pkt00_index;\t\t\t\\\n\tpkts_mask &= ~pkt00_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf00 = pkts[pkt00_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf00, 0));\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt01_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt01_mask = 1LLU << pkt01_index;\t\t\t\\\n\tpkts_mask &= ~pkt01_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf01 = pkts[pkt01_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf01, 0));\t\\\n}\n\n#define lookup2_stage0_with_odd_support(pkt00_index, pkt01_index,\\\n\t\tmbuf00, mbuf01, pkts, pkts_mask)\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt00_mask, pkt01_mask;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt00_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt00_mask = 1LLU << pkt00_index;\t\t\t\\\n\tpkts_mask &= ~pkt00_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf00 = pkts[pkt00_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf00, 0));\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt01_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tif (pkts_mask == 0)\t\t\t\t\t\\\n\t\tpkt01_index = pkt00_index;\t\t\t\\\n\tpkt01_mask = 1LLU << pkt01_index;\t\t\t\\\n\tpkts_mask &= ~pkt01_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf01 = pkts[pkt01_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf01, 0));\t\\\n}\n\n#define lookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f)\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t signature10, signature11;\t\t\t\\\n\tuint32_t bucket10_index, bucket11_index;\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tsignature10 = RTE_MBUF_METADATA_UINT32(mbuf10, f->signature_offset);\\\n\tbucket10_index = signature10 & (f->n_buckets - 1);\t\\\n\tbucket10 = (struct rte_bucket_4_16 *)\t\t\t\\\n\t\t&f->memory[bucket10_index * f->bucket_size];\t\\\n\trte_prefetch0(bucket10);\t\t\t\t\\\n\trte_prefetch0((void *)(((uintptr_t) bucket10) + RTE_CACHE_LINE_SIZE));\\\n\t\t\t\t\t\t\t\t\\\n\tsignature11 = RTE_MBUF_METADATA_UINT32(mbuf11, f->signature_offset);\\\n\tbucket11_index = signature11 & (f->n_buckets - 1);\t\\\n\tbucket11 = (struct rte_bucket_4_16 *)\t\t\t\\\n\t\t&f->memory[bucket11_index * f->bucket_size];\t\\\n\trte_prefetch0(bucket11);\t\t\t\t\\\n\trte_prefetch0((void *)(((uintptr_t) bucket11) + RTE_CACHE_LINE_SIZE));\\\n}\n\n#define lookup2_stage2_lru(pkt20_index, pkt21_index, mbuf20, mbuf21,\\\n\t\tbucket20, bucket21, pkts_mask_out, entries, f)\t\\\n{\t\t\t\t\t\t\t\t\\\n\tvoid *a20, *a21;\t\t\t\t\t\\\n\tuint64_t pkt20_mask, pkt21_mask;\t\t\t\\\n\tuint64_t *key20, *key21;\t\t\t\t\\\n\tuint32_t pos20, pos21;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey20 = RTE_MBUF_METADATA_UINT64_PTR(mbuf20, f->key_offset);\\\n\tkey21 = RTE_MBUF_METADATA_UINT64_PTR(mbuf21, f->key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key16_cmp(key20, bucket20, pos20);\t\t\\\n\tlookup_key16_cmp(key21, bucket21, pos21);\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt20_mask = (bucket20->signature[pos20] & 1LLU) << pkt20_index;\\\n\tpkt21_mask = (bucket21->signature[pos21] & 1LLU) << pkt21_index;\\\n\tpkts_mask_out |= pkt20_mask | pkt21_mask;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta20 = (void *) &bucket20->data[pos20 * f->entry_size];\t\\\n\ta21 = (void *) &bucket21->data[pos21 * f->entry_size];\t\\\n\trte_prefetch0(a20);\t\t\t\t\t\\\n\trte_prefetch0(a21);\t\t\t\t\t\\\n\tentries[pkt20_index] = a20;\t\t\t\t\\\n\tentries[pkt21_index] = a21;\t\t\t\t\\\n\tlru_update(bucket20, pos20);\t\t\t\t\\\n\tlru_update(bucket21, pos21);\t\t\t\t\\\n}\n\n#define lookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21, bucket20, \\\n\tbucket21, pkts_mask_out, entries, buckets_mask, buckets, keys, f) \\\n{\t\t\t\t\t\t\t\t\\\n\tstruct rte_bucket_4_16 *bucket20_next, *bucket21_next;\t\\\n\tvoid *a20, *a21;\t\t\t\t\t\\\n\tuint64_t pkt20_mask, pkt21_mask, bucket20_mask, bucket21_mask;\\\n\tuint64_t *key20, *key21;\t\t\t\t\\\n\tuint32_t pos20, pos21;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey20 = RTE_MBUF_METADATA_UINT64_PTR(mbuf20, f->key_offset);\\\n\tkey21 = RTE_MBUF_METADATA_UINT64_PTR(mbuf21, f->key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key16_cmp(key20, bucket20, pos20);\t\t\\\n\tlookup_key16_cmp(key21, bucket21, pos21);\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt20_mask = (bucket20->signature[pos20] & 1LLU) << pkt20_index;\\\n\tpkt21_mask = (bucket21->signature[pos21] & 1LLU) << pkt21_index;\\\n\tpkts_mask_out |= pkt20_mask | pkt21_mask;\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta20 = (void *) &bucket20->data[pos20 * f->entry_size];\t\\\n\ta21 = (void *) &bucket21->data[pos21 * f->entry_size];\t\\\n\trte_prefetch0(a20);\t\t\t\t\t\\\n\trte_prefetch0(a21);\t\t\t\t\t\\\n\tentries[pkt20_index] = a20;\t\t\t\t\\\n\tentries[pkt21_index] = a21;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket20_mask = (~pkt20_mask) & (bucket20->next_valid << pkt20_index);\\\n\tbucket21_mask = (~pkt21_mask) & (bucket21->next_valid << pkt21_index);\\\n\tbuckets_mask |= bucket20_mask | bucket21_mask;\t\t\\\n\tbucket20_next = bucket20->next;\t\t\t\t\\\n\tbucket21_next = bucket21->next;\t\t\t\t\\\n\tbuckets[pkt20_index] = bucket20_next;\t\t\t\\\n\tbuckets[pkt21_index] = bucket21_next;\t\t\t\\\n\tkeys[pkt20_index] = key20;\t\t\t\t\\\n\tkeys[pkt21_index] = key21;\t\t\t\t\\\n}\n\nstatic int\nrte_table_hash_lookup_key16_lru(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_16 *bucket10, *bucket11, *bucket20, *bucket21;\n\tstruct rte_mbuf *mbuf00, *mbuf01, *mbuf10, *mbuf11, *mbuf20, *mbuf21;\n\tuint32_t pkt00_index, pkt01_index, pkt10_index;\n\tuint32_t pkt11_index, pkt20_index, pkt21_index;\n\tuint64_t pkts_mask_out = 0;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_KEY16_STATS_PKTS_IN_ADD(f, n_pkts_in);\n\n\t/* Cannot run the pipeline with less than 5 packets */\n\tif (__builtin_popcountll(pkts_mask) < 5) {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tstruct rte_bucket_4_16 *bucket;\n\t\t\tstruct rte_mbuf *mbuf;\n\t\t\tuint32_t pkt_index;\n\n\t\t\tlookup1_stage0(pkt_index, mbuf, pkts, pkts_mask);\n\t\t\tlookup1_stage1(mbuf, bucket, f);\n\t\t\tlookup1_stage2_lru(pkt_index, mbuf, bucket,\n\t\t\t\tpkts_mask_out, entries, f);\n\t\t}\n\n\t\t*lookup_hit_mask = pkts_mask_out;\n\t\tRTE_TABLE_HASH_KEY16_STATS_PKTS_LOOKUP_MISS(f, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\t\treturn 0;\n\t}\n\n\t/*\n\t * Pipeline fill\n\t *\n\t */\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline feed */\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/*\n\t * Pipeline run\n\t *\n\t */\n\tfor ( ; pkts_mask; ) {\n\t\t/* Pipeline feed */\n\t\tbucket20 = bucket10;\n\t\tbucket21 = bucket11;\n\t\tmbuf20 = mbuf10;\n\t\tmbuf21 = mbuf11;\n\t\tmbuf10 = mbuf00;\n\t\tmbuf11 = mbuf01;\n\t\tpkt20_index = pkt10_index;\n\t\tpkt21_index = pkt11_index;\n\t\tpkt10_index = pkt00_index;\n\t\tpkt11_index = pkt01_index;\n\n\t\t/* Pipeline stage 0 */\n\t\tlookup2_stage0_with_odd_support(pkt00_index, pkt01_index,\n\t\t\tmbuf00, mbuf01, pkts, pkts_mask);\n\n\t\t/* Pipeline stage 1 */\n\t\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t\t/* Pipeline stage 2 */\n\t\tlookup2_stage2_lru(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\t\tbucket20, bucket21, pkts_mask_out, entries, f);\n\t}\n\n\t/*\n\t * Pipeline flush\n\t *\n\t */\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_lru(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries, f);\n\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_lru(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries, f);\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_KEY16_STATS_PKTS_LOOKUP_MISS(f, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn 0;\n} /* rte_table_hash_lookup_key16_lru() */\n\nstatic int\nrte_table_hash_lookup_key16_ext(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_16 *bucket10, *bucket11, *bucket20, *bucket21;\n\tstruct rte_mbuf *mbuf00, *mbuf01, *mbuf10, *mbuf11, *mbuf20, *mbuf21;\n\tuint32_t pkt00_index, pkt01_index, pkt10_index;\n\tuint32_t pkt11_index, pkt20_index, pkt21_index;\n\tuint64_t pkts_mask_out = 0, buckets_mask = 0;\n\tstruct rte_bucket_4_16 *buckets[RTE_PORT_IN_BURST_SIZE_MAX];\n\tuint64_t *keys[RTE_PORT_IN_BURST_SIZE_MAX];\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_KEY16_STATS_PKTS_IN_ADD(f, n_pkts_in);\n\n\t/* Cannot run the pipeline with less than 5 packets */\n\tif (__builtin_popcountll(pkts_mask) < 5) {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tstruct rte_bucket_4_16 *bucket;\n\t\t\tstruct rte_mbuf *mbuf;\n\t\t\tuint32_t pkt_index;\n\n\t\t\tlookup1_stage0(pkt_index, mbuf, pkts, pkts_mask);\n\t\t\tlookup1_stage1(mbuf, bucket, f);\n\t\t\tlookup1_stage2_ext(pkt_index, mbuf, bucket,\n\t\t\t\tpkts_mask_out, entries, buckets_mask,\n\t\t\t\tbuckets, keys, f);\n\t\t}\n\n\t\tgoto grind_next_buckets;\n\t}\n\n\t/*\n\t * Pipeline fill\n\t *\n\t */\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline feed */\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/*\n\t * Pipeline run\n\t *\n\t */\n\tfor ( ; pkts_mask; ) {\n\t\t/* Pipeline feed */\n\t\tbucket20 = bucket10;\n\t\tbucket21 = bucket11;\n\t\tmbuf20 = mbuf10;\n\t\tmbuf21 = mbuf11;\n\t\tmbuf10 = mbuf00;\n\t\tmbuf11 = mbuf01;\n\t\tpkt20_index = pkt10_index;\n\t\tpkt21_index = pkt11_index;\n\t\tpkt10_index = pkt00_index;\n\t\tpkt11_index = pkt01_index;\n\n\t\t/* Pipeline stage 0 */\n\t\tlookup2_stage0_with_odd_support(pkt00_index, pkt01_index,\n\t\t\tmbuf00, mbuf01, pkts, pkts_mask);\n\n\t\t/* Pipeline stage 1 */\n\t\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t\t/* Pipeline stage 2 */\n\t\tlookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\t\tbucket20, bucket21, pkts_mask_out, entries,\n\t\t\tbuckets_mask, buckets, keys, f);\n\t}\n\n\t/*\n\t * Pipeline flush\n\t *\n\t */\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries,\n\t\tbuckets_mask, buckets, keys, f);\n\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries,\n\t\tbuckets_mask, buckets, keys, f);\n\ngrind_next_buckets:\n\t/* Grind next buckets */\n\tfor ( ; buckets_mask; ) {\n\t\tuint64_t buckets_mask_next = 0;\n\n\t\tfor ( ; buckets_mask; ) {\n\t\t\tuint64_t pkt_mask;\n\t\t\tuint32_t pkt_index;\n\n\t\t\tpkt_index = __builtin_ctzll(buckets_mask);\n\t\t\tpkt_mask = 1LLU << pkt_index;\n\t\t\tbuckets_mask &= ~pkt_mask;\n\n\t\t\tlookup_grinder(pkt_index, buckets, keys, pkts_mask_out,\n\t\t\t\tentries, buckets_mask_next, f);\n\t\t}\n\n\t\tbuckets_mask = buckets_mask_next;\n\t}\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_KEY16_STATS_PKTS_LOOKUP_MISS(f, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn 0;\n} /* rte_table_hash_lookup_key16_ext() */\n\nstatic int\nrte_table_hash_key16_stats_read(void *table, struct rte_table_stats *stats, int clear)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &t->stats, sizeof(t->stats));\n\n\tif (clear)\n\t\tmemset(&t->stats, 0, sizeof(t->stats));\n\n\treturn 0;\n}\n\nstruct rte_table_ops rte_table_hash_key16_lru_ops = {\n\t.f_create = rte_table_hash_create_key16_lru,\n\t.f_free = rte_table_hash_free_key16_lru,\n\t.f_add = rte_table_hash_entry_add_key16_lru,\n\t.f_delete = rte_table_hash_entry_delete_key16_lru,\n\t.f_lookup = rte_table_hash_lookup_key16_lru,\n\t.f_stats = rte_table_hash_key16_stats_read,\n};\n\nstruct rte_table_ops rte_table_hash_key16_ext_ops = {\n\t.f_create = rte_table_hash_create_key16_ext,\n\t.f_free = rte_table_hash_free_key16_ext,\n\t.f_add = rte_table_hash_entry_add_key16_ext,\n\t.f_delete = rte_table_hash_entry_delete_key16_ext,\n\t.f_lookup = rte_table_hash_lookup_key16_ext,\n\t.f_stats = rte_table_hash_key16_stats_read,\n};\n" }, { "path": "lib/librte_table/rte_table_hash_key32.c", "content": "/*-\n *\t BSD LICENSE\n *\n *\t Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\t All rights reserved.\n *\n *\t Redistribution and use in source and binary forms, with or without\n *\t modification, are permitted provided that the following conditions\n *\t are met:\n *\n *\t* Redistributions of source code must retain the above copyright\n *\t\t notice, this list of conditions and the following disclaimer.\n *\t* Redistributions in binary form must reproduce the above copyright\n *\t\t notice, this list of conditions and the following disclaimer in\n *\t\t the documentation and/or other materials provided with the\n *\t\t distribution.\n *\t* Neither the name of Intel Corporation nor the names of its\n *\t\t contributors may be used to endorse or promote products derived\n *\t\t from this software without specific prior written permission.\n *\n *\t THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n *\t \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n *\t LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n *\t A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n *\t OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n *\t SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n *\t LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n *\t DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n *\t THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n *\t (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n *\t OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_table_hash.h\"\n#include \"rte_lru.h\"\n\n#define RTE_TABLE_HASH_KEY_SIZE\t\t\t\t\t\t32\n\n#define RTE_BUCKET_ENTRY_VALID\t\t\t\t\t\t0x1LLU\n\n#ifdef RTE_TABLE_STATS_COLLECT\n\n#define RTE_TABLE_HASH_KEY32_STATS_PKTS_IN_ADD(table, val) \\\n\ttable->stats.n_pkts_in += val\n#define RTE_TABLE_HASH_KEY32_STATS_PKTS_LOOKUP_MISS(table, val) \\\n\ttable->stats.n_pkts_lookup_miss += val\n\n#else\n\n#define RTE_TABLE_HASH_KEY32_STATS_PKTS_IN_ADD(table, val)\n#define RTE_TABLE_HASH_KEY32_STATS_PKTS_LOOKUP_MISS(table, val)\n\n#endif\n\nstruct rte_bucket_4_32 {\n\t/* Cache line 0 */\n\tuint64_t signature[4 + 1];\n\tuint64_t lru_list;\n\tstruct rte_bucket_4_32 *next;\n\tuint64_t next_valid;\n\n\t/* Cache lines 1 and 2 */\n\tuint64_t key[4][4];\n\n\t/* Cache line 3 */\n\tuint8_t data[0];\n};\n\nstruct rte_table_hash {\n\tstruct rte_table_stats stats;\n\n\t/* Input parameters */\n\tuint32_t n_buckets;\n\tuint32_t n_entries_per_bucket;\n\tuint32_t key_size;\n\tuint32_t entry_size;\n\tuint32_t bucket_size;\n\tuint32_t signature_offset;\n\tuint32_t key_offset;\n\trte_table_hash_op_hash f_hash;\n\tuint64_t seed;\n\n\t/* Extendible buckets */\n\tuint32_t n_buckets_ext;\n\tuint32_t stack_pos;\n\tuint32_t *stack;\n\n\t/* Lookup table */\n\tuint8_t memory[0] __rte_cache_aligned;\n};\n\nstatic int\ncheck_params_create_lru(struct rte_table_hash_key32_lru_params *params) {\n\t/* n_entries */\n\tif (params->n_entries == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_entries is zero\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* f_hash */\n\tif (params->f_hash == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: f_hash function pointer is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic void *\nrte_table_hash_create_key32_lru(void *params,\n\t\tint socket_id,\n\t\tuint32_t entry_size)\n{\n\tstruct rte_table_hash_key32_lru_params *p =\n\t\t(struct rte_table_hash_key32_lru_params *) params;\n\tstruct rte_table_hash *f;\n\tuint32_t n_buckets, n_entries_per_bucket, key_size, bucket_size_cl;\n\tuint32_t total_size, i;\n\n\t/* Check input parameters */\n\tif ((check_params_create_lru(p) != 0) ||\n\t\t((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||\n\t\t((sizeof(struct rte_bucket_4_32) % RTE_CACHE_LINE_SIZE) != 0)) {\n\t\treturn NULL;\n\t}\n\tn_entries_per_bucket = 4;\n\tkey_size = 32;\n\n\t/* Memory allocation */\n\tn_buckets = rte_align32pow2((p->n_entries + n_entries_per_bucket - 1) /\n\t\tn_entries_per_bucket);\n\tbucket_size_cl = (sizeof(struct rte_bucket_4_32) + n_entries_per_bucket\n\t\t* entry_size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;\n\ttotal_size = sizeof(struct rte_table_hash) + n_buckets *\n\t\tbucket_size_cl * RTE_CACHE_LINE_SIZE;\n\n\tf = rte_zmalloc_socket(\"TABLE\", total_size, RTE_CACHE_LINE_SIZE, socket_id);\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot allocate %u bytes for hash table\\n\",\n\t\t\t__func__, total_size);\n\t\treturn NULL;\n\t}\n\tRTE_LOG(INFO, TABLE,\n\t\t\"%s: Hash table memory footprint is %u bytes\\n\", __func__,\n\t\ttotal_size);\n\n\t/* Memory initialization */\n\tf->n_buckets = n_buckets;\n\tf->n_entries_per_bucket = n_entries_per_bucket;\n\tf->key_size = key_size;\n\tf->entry_size = entry_size;\n\tf->bucket_size = bucket_size_cl * RTE_CACHE_LINE_SIZE;\n\tf->signature_offset = p->signature_offset;\n\tf->key_offset = p->key_offset;\n\tf->f_hash = p->f_hash;\n\tf->seed = p->seed;\n\n\tfor (i = 0; i < n_buckets; i++) {\n\t\tstruct rte_bucket_4_32 *bucket;\n\n\t\tbucket = (struct rte_bucket_4_32 *) &f->memory[i *\n\t\t\tf->bucket_size];\n\t\tbucket->lru_list = 0x0000000100020003LLU;\n\t}\n\n\treturn f;\n}\n\nstatic int\nrte_table_hash_free_key32_lru(void *table)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\n\t/* Check input parameters */\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_free(f);\n\treturn 0;\n}\n\nstatic int\nrte_table_hash_entry_add_key32_lru(\n\tvoid *table,\n\tvoid *key,\n\tvoid *entry,\n\tint *key_found,\n\tvoid **entry_ptr)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_32 *bucket;\n\tuint64_t signature, pos;\n\tuint32_t bucket_index, i;\n\n\tsignature = f->f_hash(key, f->key_size, f->seed);\n\tbucket_index = signature & (f->n_buckets - 1);\n\tbucket = (struct rte_bucket_4_32 *)\n\t\t&f->memory[bucket_index * f->bucket_size];\n\tsignature |= RTE_BUCKET_ENTRY_VALID;\n\n\t/* Key is present in the bucket */\n\tfor (i = 0; i < 4; i++) {\n\t\tuint64_t bucket_signature = bucket->signature[i];\n\t\tuint8_t *bucket_key = (uint8_t *) bucket->key[i];\n\n\t\tif ((bucket_signature == signature) &&\n\t\t\t(memcmp(key, bucket_key, f->key_size) == 0)) {\n\t\t\tuint8_t *bucket_data = &bucket->data[i * f->entry_size];\n\n\t\t\tmemcpy(bucket_data, entry, f->entry_size);\n\t\t\tlru_update(bucket, i);\n\t\t\t*key_found = 1;\n\t\t\t*entry_ptr = (void *) bucket_data;\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Key is not present in the bucket */\n\tfor (i = 0; i < 4; i++) {\n\t\tuint64_t bucket_signature = bucket->signature[i];\n\t\tuint8_t *bucket_key = (uint8_t *) bucket->key[i];\n\n\t\tif (bucket_signature == 0) {\n\t\t\tuint8_t *bucket_data = &bucket->data[i * f->entry_size];\n\n\t\t\tbucket->signature[i] = signature;\n\t\t\tmemcpy(bucket_key, key, f->key_size);\n\t\t\tmemcpy(bucket_data, entry, f->entry_size);\n\t\t\tlru_update(bucket, i);\n\t\t\t*key_found = 0;\n\t\t\t*entry_ptr = (void *) bucket_data;\n\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Bucket full: replace LRU entry */\n\tpos = lru_pos(bucket);\n\tbucket->signature[pos] = signature;\n\tmemcpy(bucket->key[pos], key, f->key_size);\n\tmemcpy(&bucket->data[pos * f->entry_size], entry, f->entry_size);\n\tlru_update(bucket, pos);\n\t*key_found\t= 0;\n\t*entry_ptr = (void *) &bucket->data[pos * f->entry_size];\n\n\treturn 0;\n}\n\nstatic int\nrte_table_hash_entry_delete_key32_lru(\n\tvoid *table,\n\tvoid *key,\n\tint *key_found,\n\tvoid *entry)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_32 *bucket;\n\tuint64_t signature;\n\tuint32_t bucket_index, i;\n\n\tsignature = f->f_hash(key, f->key_size, f->seed);\n\tbucket_index = signature & (f->n_buckets - 1);\n\tbucket = (struct rte_bucket_4_32 *)\n\t\t&f->memory[bucket_index * f->bucket_size];\n\tsignature |= RTE_BUCKET_ENTRY_VALID;\n\n\t/* Key is present in the bucket */\n\tfor (i = 0; i < 4; i++) {\n\t\tuint64_t bucket_signature = bucket->signature[i];\n\t\tuint8_t *bucket_key = (uint8_t *) bucket->key[i];\n\n\t\tif ((bucket_signature == signature) &&\n\t\t\t(memcmp(key, bucket_key, f->key_size) == 0)) {\n\t\t\tuint8_t *bucket_data = &bucket->data[i * f->entry_size];\n\n\t\t\tbucket->signature[i] = 0;\n\t\t\t*key_found = 1;\n\t\t\tif (entry)\n\t\t\t\tmemcpy(entry, bucket_data, f->entry_size);\n\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Key is not present in the bucket */\n\t*key_found = 0;\n\treturn 0;\n}\n\nstatic int\ncheck_params_create_ext(struct rte_table_hash_key32_ext_params *params) {\n\t/* n_entries */\n\tif (params->n_entries == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_entries is zero\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* n_entries_ext */\n\tif (params->n_entries_ext == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_entries_ext is zero\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* f_hash */\n\tif (params->f_hash == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: f_hash function pointer is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic void *\nrte_table_hash_create_key32_ext(void *params,\n\tint socket_id,\n\tuint32_t entry_size)\n{\n\tstruct rte_table_hash_key32_ext_params *p =\n\t\t\t(struct rte_table_hash_key32_ext_params *) params;\n\tstruct rte_table_hash *f;\n\tuint32_t n_buckets, n_buckets_ext, n_entries_per_bucket;\n\tuint32_t key_size, bucket_size_cl, stack_size_cl, total_size, i;\n\n\t/* Check input parameters */\n\tif ((check_params_create_ext(p) != 0) ||\n\t\t((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||\n\t\t((sizeof(struct rte_bucket_4_32) % RTE_CACHE_LINE_SIZE) != 0))\n\t\treturn NULL;\n\n\tn_entries_per_bucket = 4;\n\tkey_size = 32;\n\n\t/* Memory allocation */\n\tn_buckets = rte_align32pow2((p->n_entries + n_entries_per_bucket - 1) /\n\t\tn_entries_per_bucket);\n\tn_buckets_ext = (p->n_entries_ext + n_entries_per_bucket - 1) /\n\t\tn_entries_per_bucket;\n\tbucket_size_cl = (sizeof(struct rte_bucket_4_32) + n_entries_per_bucket\n\t\t* entry_size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;\n\tstack_size_cl = (n_buckets_ext * sizeof(uint32_t) + RTE_CACHE_LINE_SIZE - 1)\n\t\t/ RTE_CACHE_LINE_SIZE;\n\ttotal_size = sizeof(struct rte_table_hash) +\n\t\t((n_buckets + n_buckets_ext) * bucket_size_cl + stack_size_cl) *\n\t\tRTE_CACHE_LINE_SIZE;\n\n\tf = rte_zmalloc_socket(\"TABLE\", total_size, RTE_CACHE_LINE_SIZE, socket_id);\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot allocate %u bytes for hash table\\n\",\n\t\t\t__func__, total_size);\n\t\treturn NULL;\n\t}\n\tRTE_LOG(INFO, TABLE,\n\t\t\"%s: Hash table memory footprint is %u bytes\\n\", __func__,\n\t\ttotal_size);\n\n\t/* Memory initialization */\n\tf->n_buckets = n_buckets;\n\tf->n_entries_per_bucket = n_entries_per_bucket;\n\tf->key_size = key_size;\n\tf->entry_size = entry_size;\n\tf->bucket_size = bucket_size_cl * RTE_CACHE_LINE_SIZE;\n\tf->signature_offset = p->signature_offset;\n\tf->key_offset = p->key_offset;\n\tf->f_hash = p->f_hash;\n\tf->seed = p->seed;\n\n\tf->n_buckets_ext = n_buckets_ext;\n\tf->stack_pos = n_buckets_ext;\n\tf->stack = (uint32_t *)\n\t\t&f->memory[(n_buckets + n_buckets_ext) * f->bucket_size];\n\n\tfor (i = 0; i < n_buckets_ext; i++)\n\t\tf->stack[i] = i;\n\n\treturn f;\n}\n\nstatic int\nrte_table_hash_free_key32_ext(void *table)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\n\t/* Check input parameters */\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_free(f);\n\treturn 0;\n}\n\nstatic int\nrte_table_hash_entry_add_key32_ext(\n\tvoid *table,\n\tvoid *key,\n\tvoid *entry,\n\tint *key_found,\n\tvoid **entry_ptr)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_32 *bucket0, *bucket, *bucket_prev;\n\tuint64_t signature;\n\tuint32_t bucket_index, i;\n\n\tsignature = f->f_hash(key, f->key_size, f->seed);\n\tbucket_index = signature & (f->n_buckets - 1);\n\tbucket0 = (struct rte_bucket_4_32 *)\n\t\t\t&f->memory[bucket_index * f->bucket_size];\n\tsignature |= RTE_BUCKET_ENTRY_VALID;\n\n\t/* Key is present in the bucket */\n\tfor (bucket = bucket0; bucket != NULL; bucket = bucket->next) {\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tuint64_t bucket_signature = bucket->signature[i];\n\t\t\tuint8_t *bucket_key = (uint8_t *) bucket->key[i];\n\n\t\t\tif ((bucket_signature == signature) &&\n\t\t\t\t(memcmp(key, bucket_key, f->key_size) == 0)) {\n\t\t\t\tuint8_t *bucket_data = &bucket->data[i *\n\t\t\t\t\tf->entry_size];\n\n\t\t\t\tmemcpy(bucket_data, entry, f->entry_size);\n\t\t\t\t*key_found = 1;\n\t\t\t\t*entry_ptr = (void *) bucket_data;\n\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Key is not present in the bucket */\n\tfor (bucket_prev = NULL, bucket = bucket0; bucket != NULL;\n\t\tbucket_prev = bucket, bucket = bucket->next)\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tuint64_t bucket_signature = bucket->signature[i];\n\t\t\tuint8_t *bucket_key = (uint8_t *) bucket->key[i];\n\n\t\t\tif (bucket_signature == 0) {\n\t\t\t\tuint8_t *bucket_data = &bucket->data[i *\n\t\t\t\t\tf->entry_size];\n\n\t\t\t\tbucket->signature[i] = signature;\n\t\t\t\tmemcpy(bucket_key, key, f->key_size);\n\t\t\t\tmemcpy(bucket_data, entry, f->entry_size);\n\t\t\t\t*key_found = 0;\n\t\t\t\t*entry_ptr = (void *) bucket_data;\n\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\n\t/* Bucket full: extend bucket */\n\tif (f->stack_pos > 0) {\n\t\tbucket_index = f->stack[--f->stack_pos];\n\n\t\tbucket = (struct rte_bucket_4_32 *)\n\t\t\t&f->memory[(f->n_buckets + bucket_index) *\n\t\t\tf->bucket_size];\n\t\tbucket_prev->next = bucket;\n\t\tbucket_prev->next_valid = 1;\n\n\t\tbucket->signature[0] = signature;\n\t\tmemcpy(bucket->key[0], key, f->key_size);\n\t\tmemcpy(&bucket->data[0], entry, f->entry_size);\n\t\t*key_found = 0;\n\t\t*entry_ptr = (void *) &bucket->data[0];\n\t\treturn 0;\n\t}\n\n\treturn -ENOSPC;\n}\n\nstatic int\nrte_table_hash_entry_delete_key32_ext(\n\tvoid *table,\n\tvoid *key,\n\tint *key_found,\n\tvoid *entry)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_32 *bucket0, *bucket, *bucket_prev;\n\tuint64_t signature;\n\tuint32_t bucket_index, i;\n\n\tsignature = f->f_hash(key, f->key_size, f->seed);\n\tbucket_index = signature & (f->n_buckets - 1);\n\tbucket0 = (struct rte_bucket_4_32 *)\n\t\t&f->memory[bucket_index * f->bucket_size];\n\tsignature |= RTE_BUCKET_ENTRY_VALID;\n\n\t/* Key is present in the bucket */\n\tfor (bucket_prev = NULL, bucket = bucket0; bucket != NULL;\n\t\tbucket_prev = bucket, bucket = bucket->next)\n\t\tfor (i = 0; i < 4; i++) {\n\t\t\tuint64_t bucket_signature = bucket->signature[i];\n\t\t\tuint8_t *bucket_key = (uint8_t *) bucket->key[i];\n\n\t\t\tif ((bucket_signature == signature) &&\n\t\t\t\t(memcmp(key, bucket_key, f->key_size) == 0)) {\n\t\t\t\tuint8_t *bucket_data = &bucket->data[i *\n\t\t\t\t\tf->entry_size];\n\n\t\t\t\tbucket->signature[i] = 0;\n\t\t\t\t*key_found = 1;\n\t\t\t\tif (entry)\n\t\t\t\t\tmemcpy(entry, bucket_data,\n\t\t\t\t\t\tf->entry_size);\n\n\t\t\t\tif ((bucket->signature[0] == 0) &&\n\t\t\t\t\t\t(bucket->signature[1] == 0) &&\n\t\t\t\t\t\t(bucket->signature[2] == 0) &&\n\t\t\t\t\t\t(bucket->signature[3] == 0) &&\n\t\t\t\t\t\t(bucket_prev != NULL)) {\n\t\t\t\t\tbucket_prev->next = bucket->next;\n\t\t\t\t\tbucket_prev->next_valid =\n\t\t\t\t\t\tbucket->next_valid;\n\n\t\t\t\t\tmemset(bucket, 0,\n\t\t\t\t\t\tsizeof(struct rte_bucket_4_32));\n\t\t\t\t\tbucket_index = (((uint8_t *)bucket -\n\t\t\t\t\t\t(uint8_t *)f->memory)/f->bucket_size) - f->n_buckets;\n\t\t\t\t\tf->stack[f->stack_pos++] = bucket_index;\n\t\t\t\t}\n\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\n\t/* Key is not present in the bucket */\n\t*key_found = 0;\n\treturn 0;\n}\n\n#define lookup_key32_cmp(key_in, bucket, pos)\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t xor[4][4], or[4], signature[4];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tsignature[0] = ((~bucket->signature[0]) & 1);\t\t\\\n\tsignature[1] = ((~bucket->signature[1]) & 1);\t\t\\\n\tsignature[2] = ((~bucket->signature[2]) & 1);\t\t\\\n\tsignature[3] = ((~bucket->signature[3]) & 1);\t\t\\\n\t\t\t\t\t\t\t\t\\\n\txor[0][0] = key_in[0] ^\t bucket->key[0][0];\t\t\\\n\txor[0][1] = key_in[1] ^\t bucket->key[0][1];\t\t\\\n\txor[0][2] = key_in[2] ^\t bucket->key[0][2];\t\t\\\n\txor[0][3] = key_in[3] ^\t bucket->key[0][3];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\txor[1][0] = key_in[0] ^\t bucket->key[1][0];\t\t\\\n\txor[1][1] = key_in[1] ^\t bucket->key[1][1];\t\t\\\n\txor[1][2] = key_in[2] ^\t bucket->key[1][2];\t\t\\\n\txor[1][3] = key_in[3] ^\t bucket->key[1][3];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\txor[2][0] = key_in[0] ^\t bucket->key[2][0];\t\t\\\n\txor[2][1] = key_in[1] ^\t bucket->key[2][1];\t\t\\\n\txor[2][2] = key_in[2] ^\t bucket->key[2][2];\t\t\\\n\txor[2][3] = key_in[3] ^\t bucket->key[2][3];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\txor[3][0] = key_in[0] ^\t bucket->key[3][0];\t\t\\\n\txor[3][1] = key_in[1] ^\t bucket->key[3][1];\t\t\\\n\txor[3][2] = key_in[2] ^\t bucket->key[3][2];\t\t\\\n\txor[3][3] = key_in[3] ^\t bucket->key[3][3];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tor[0] = xor[0][0] | xor[0][1] | xor[0][2] | xor[0][3] | signature[0];\\\n\tor[1] = xor[1][0] | xor[1][1] | xor[1][2] | xor[1][3] | signature[1];\\\n\tor[2] = xor[2][0] | xor[2][1] | xor[2][2] | xor[2][3] | signature[2];\\\n\tor[3] = xor[3][0] | xor[3][1] | xor[3][2] | xor[3][3] | signature[3];\\\n\t\t\t\t\t\t\t\t\\\n\tpos = 4;\t\t\t\t\t\t\\\n\tif (or[0] == 0)\t\t\t\t\t\t\\\n\t\tpos = 0;\t\t\t\t\t\\\n\tif (or[1] == 0)\t\t\t\t\t\t\\\n\t\tpos = 1;\t\t\t\t\t\\\n\tif (or[2] == 0)\t\t\t\t\t\t\\\n\t\tpos = 2;\t\t\t\t\t\\\n\tif (or[3] == 0)\t\t\t\t\t\t\\\n\t\tpos = 3;\t\t\t\t\t\\\n}\n\n#define lookup1_stage0(pkt0_index, mbuf0, pkts, pkts_mask)\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt_mask;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt0_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt_mask = 1LLU << pkt0_index;\t\t\t\t\\\n\tpkts_mask &= ~pkt_mask;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf0 = pkts[pkt0_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf0, 0));\t\\\n}\n\n#define lookup1_stage1(mbuf1, bucket1, f)\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t signature;\t\t\t\t\t\\\n\tuint32_t bucket_index;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tsignature = RTE_MBUF_METADATA_UINT32(mbuf1, f->signature_offset);\\\n\tbucket_index = signature & (f->n_buckets - 1);\t\t\\\n\tbucket1 = (struct rte_bucket_4_32 *)\t\t\t\\\n\t\t&f->memory[bucket_index * f->bucket_size];\t\\\n\trte_prefetch0(bucket1);\t\t\t\t\t\\\n\trte_prefetch0((void *)(((uintptr_t) bucket1) + RTE_CACHE_LINE_SIZE));\\\n\trte_prefetch0((void *)(((uintptr_t) bucket1) + 2 * RTE_CACHE_LINE_SIZE));\\\n}\n\n#define lookup1_stage2_lru(pkt2_index, mbuf2, bucket2,\t\t\\\n\tpkts_mask_out, entries, f)\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tvoid *a;\t\t\t\t\t\t\\\n\tuint64_t pkt_mask;\t\t\t\t\t\\\n\tuint64_t *key;\t\t\t\t\t\t\\\n\tuint32_t pos;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey = RTE_MBUF_METADATA_UINT64_PTR(mbuf2, f->key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key32_cmp(key, bucket2, pos);\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt_mask = (bucket2->signature[pos] & 1LLU) << pkt2_index;\\\n\tpkts_mask_out |= pkt_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta = (void *) &bucket2->data[pos * f->entry_size];\t\\\n\trte_prefetch0(a);\t\t\t\t\t\\\n\tentries[pkt2_index] = a;\t\t\t\t\\\n\tlru_update(bucket2, pos);\t\t\t\t\\\n}\n\n#define lookup1_stage2_ext(pkt2_index, mbuf2, bucket2, pkts_mask_out,\\\n\tentries, buckets_mask, buckets, keys, f)\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tstruct rte_bucket_4_32 *bucket_next;\t\t\t\\\n\tvoid *a;\t\t\t\t\t\t\\\n\tuint64_t pkt_mask, bucket_mask;\t\t\t\t\\\n\tuint64_t *key;\t\t\t\t\t\t\\\n\tuint32_t pos;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey = RTE_MBUF_METADATA_UINT64_PTR(mbuf2, f->key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key32_cmp(key, bucket2, pos);\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt_mask = (bucket2->signature[pos] & 1LLU) << pkt2_index;\\\n\tpkts_mask_out |= pkt_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta = (void *) &bucket2->data[pos * f->entry_size];\t\\\n\trte_prefetch0(a);\t\t\t\t\t\\\n\tentries[pkt2_index] = a;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket_mask = (~pkt_mask) & (bucket2->next_valid << pkt2_index);\\\n\tbuckets_mask |= bucket_mask;\t\t\t\t\\\n\tbucket_next = bucket2->next;\t\t\t\t\\\n\tbuckets[pkt2_index] = bucket_next;\t\t\t\\\n\tkeys[pkt2_index] = key;\t\t\t\t\t\\\n}\n\n#define lookup_grinder(pkt_index, buckets, keys, pkts_mask_out,\t\\\n\tentries, buckets_mask, f)\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tstruct rte_bucket_4_32 *bucket, *bucket_next;\t\t\\\n\tvoid *a;\t\t\t\t\t\t\\\n\tuint64_t pkt_mask, bucket_mask;\t\t\t\t\\\n\tuint64_t *key;\t\t\t\t\t\t\\\n\tuint32_t pos;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket = buckets[pkt_index];\t\t\t\t\\\n\tkey = keys[pkt_index];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key32_cmp(key, bucket, pos);\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt_mask = (bucket->signature[pos] & 1LLU) << pkt_index;\\\n\tpkts_mask_out |= pkt_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta = (void *) &bucket->data[pos * f->entry_size];\t\\\n\trte_prefetch0(a);\t\t\t\t\t\\\n\tentries[pkt_index] = a;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket_mask = (~pkt_mask) & (bucket->next_valid << pkt_index);\\\n\tbuckets_mask |= bucket_mask;\t\t\t\t\\\n\tbucket_next = bucket->next;\t\t\t\t\\\n\trte_prefetch0(bucket_next);\t\t\t\t\\\n\trte_prefetch0((void *)(((uintptr_t) bucket_next) + RTE_CACHE_LINE_SIZE));\\\n\trte_prefetch0((void *)(((uintptr_t) bucket_next) +\t\\\n\t\t2 * RTE_CACHE_LINE_SIZE));\t\t\t\t\\\n\tbuckets[pkt_index] = bucket_next;\t\t\t\\\n\tkeys[pkt_index] = key;\t\t\t\t\t\\\n}\n\n#define lookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01,\\\n\tpkts, pkts_mask)\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt00_mask, pkt01_mask;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt00_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt00_mask = 1LLU << pkt00_index;\t\t\t\\\n\tpkts_mask &= ~pkt00_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf00 = pkts[pkt00_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf00, 0));\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt01_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt01_mask = 1LLU << pkt01_index;\t\t\t\\\n\tpkts_mask &= ~pkt01_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf01 = pkts[pkt01_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf01, 0));\t\\\n}\n\n#define lookup2_stage0_with_odd_support(pkt00_index, pkt01_index,\\\n\tmbuf00, mbuf01, pkts, pkts_mask)\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt00_mask, pkt01_mask;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt00_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt00_mask = 1LLU << pkt00_index;\t\t\t\\\n\tpkts_mask &= ~pkt00_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf00 = pkts[pkt00_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf00, 0));\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt01_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tif (pkts_mask == 0)\t\t\t\t\t\\\n\t\tpkt01_index = pkt00_index;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt01_mask = 1LLU << pkt01_index;\t\t\t\\\n\tpkts_mask &= ~pkt01_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf01 = pkts[pkt01_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf01, 0));\t\\\n}\n\n#define lookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f)\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t signature10, signature11;\t\t\t\\\n\tuint32_t bucket10_index, bucket11_index;\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tsignature10 = RTE_MBUF_METADATA_UINT32(mbuf10, f->signature_offset);\\\n\tbucket10_index = signature10 & (f->n_buckets - 1);\t\\\n\tbucket10 = (struct rte_bucket_4_32 *)\t\t\t\\\n\t\t&f->memory[bucket10_index * f->bucket_size];\t\\\n\trte_prefetch0(bucket10);\t\t\t\t\\\n\trte_prefetch0((void *)(((uintptr_t) bucket10) + RTE_CACHE_LINE_SIZE));\\\n\trte_prefetch0((void *)(((uintptr_t) bucket10) + 2 * RTE_CACHE_LINE_SIZE));\\\n\t\t\t\t\t\t\t\t\\\n\tsignature11 = RTE_MBUF_METADATA_UINT32(mbuf11, f->signature_offset);\\\n\tbucket11_index = signature11 & (f->n_buckets - 1);\t\\\n\tbucket11 = (struct rte_bucket_4_32 *)\t\t\t\\\n\t\t&f->memory[bucket11_index * f->bucket_size];\t\\\n\trte_prefetch0(bucket11);\t\t\t\t\\\n\trte_prefetch0((void *)(((uintptr_t) bucket11) + RTE_CACHE_LINE_SIZE));\\\n\trte_prefetch0((void *)(((uintptr_t) bucket11) + 2 * RTE_CACHE_LINE_SIZE));\\\n}\n\n#define lookup2_stage2_lru(pkt20_index, pkt21_index, mbuf20, mbuf21,\\\n\tbucket20, bucket21, pkts_mask_out, entries, f)\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tvoid *a20, *a21;\t\t\t\t\t\\\n\tuint64_t pkt20_mask, pkt21_mask;\t\t\t\\\n\tuint64_t *key20, *key21;\t\t\t\t\\\n\tuint32_t pos20, pos21;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey20 = RTE_MBUF_METADATA_UINT64_PTR(mbuf20, f->key_offset);\\\n\tkey21 = RTE_MBUF_METADATA_UINT64_PTR(mbuf21, f->key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key32_cmp(key20, bucket20, pos20);\t\t\\\n\tlookup_key32_cmp(key21, bucket21, pos21);\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt20_mask = (bucket20->signature[pos20] & 1LLU) << pkt20_index;\\\n\tpkt21_mask = (bucket21->signature[pos21] & 1LLU) << pkt21_index;\\\n\tpkts_mask_out |= pkt20_mask | pkt21_mask;\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta20 = (void *) &bucket20->data[pos20 * f->entry_size];\t\\\n\ta21 = (void *) &bucket21->data[pos21 * f->entry_size];\t\\\n\trte_prefetch0(a20);\t\t\t\t\t\\\n\trte_prefetch0(a21);\t\t\t\t\t\\\n\tentries[pkt20_index] = a20;\t\t\t\t\\\n\tentries[pkt21_index] = a21;\t\t\t\t\\\n\tlru_update(bucket20, pos20);\t\t\t\t\\\n\tlru_update(bucket21, pos21);\t\t\t\t\\\n}\n\n#define lookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21, bucket20, \\\n\tbucket21, pkts_mask_out, entries, buckets_mask, buckets, keys, f)\\\n{\t\t\t\t\t\t\t\t\\\n\tstruct rte_bucket_4_32 *bucket20_next, *bucket21_next;\t\\\n\tvoid *a20, *a21;\t\t\t\t\t\\\n\tuint64_t pkt20_mask, pkt21_mask, bucket20_mask, bucket21_mask;\\\n\tuint64_t *key20, *key21;\t\t\t\t\\\n\tuint32_t pos20, pos21;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey20 = RTE_MBUF_METADATA_UINT64_PTR(mbuf20, f->key_offset);\\\n\tkey21 = RTE_MBUF_METADATA_UINT64_PTR(mbuf21, f->key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key32_cmp(key20, bucket20, pos20);\t\t\\\n\tlookup_key32_cmp(key21, bucket21, pos21);\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt20_mask = (bucket20->signature[pos20] & 1LLU) << pkt20_index;\\\n\tpkt21_mask = (bucket21->signature[pos21] & 1LLU) << pkt21_index;\\\n\tpkts_mask_out |= pkt20_mask | pkt21_mask;\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta20 = (void *) &bucket20->data[pos20 * f->entry_size];\t\\\n\ta21 = (void *) &bucket21->data[pos21 * f->entry_size];\t\\\n\trte_prefetch0(a20);\t\t\t\t\t\\\n\trte_prefetch0(a21);\t\t\t\t\t\\\n\tentries[pkt20_index] = a20;\t\t\t\t\\\n\tentries[pkt21_index] = a21;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket20_mask = (~pkt20_mask) & (bucket20->next_valid << pkt20_index);\\\n\tbucket21_mask = (~pkt21_mask) & (bucket21->next_valid << pkt21_index);\\\n\tbuckets_mask |= bucket20_mask | bucket21_mask;\t\t\\\n\tbucket20_next = bucket20->next;\t\t\t\t\\\n\tbucket21_next = bucket21->next;\t\t\t\t\\\n\tbuckets[pkt20_index] = bucket20_next;\t\t\t\\\n\tbuckets[pkt21_index] = bucket21_next;\t\t\t\\\n\tkeys[pkt20_index] = key20;\t\t\t\t\\\n\tkeys[pkt21_index] = key21;\t\t\t\t\\\n}\n\nstatic int\nrte_table_hash_lookup_key32_lru(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_32 *bucket10, *bucket11, *bucket20, *bucket21;\n\tstruct rte_mbuf *mbuf00, *mbuf01, *mbuf10, *mbuf11, *mbuf20, *mbuf21;\n\tuint32_t pkt00_index, pkt01_index, pkt10_index;\n\tuint32_t pkt11_index, pkt20_index, pkt21_index;\n\tuint64_t pkts_mask_out = 0;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_KEY32_STATS_PKTS_IN_ADD(f, n_pkts_in);\n\n\t/* Cannot run the pipeline with less than 5 packets */\n\tif (__builtin_popcountll(pkts_mask) < 5) {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tstruct rte_bucket_4_32 *bucket;\n\t\t\tstruct rte_mbuf *mbuf;\n\t\t\tuint32_t pkt_index;\n\n\t\t\tlookup1_stage0(pkt_index, mbuf, pkts, pkts_mask);\n\t\t\tlookup1_stage1(mbuf, bucket, f);\n\t\t\tlookup1_stage2_lru(pkt_index, mbuf, bucket,\n\t\t\t\t\tpkts_mask_out, entries, f);\n\t\t}\n\n\t\t*lookup_hit_mask = pkts_mask_out;\n\t\tRTE_TABLE_HASH_KEY32_STATS_PKTS_LOOKUP_MISS(f, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\t\treturn 0;\n\t}\n\n\t/*\n\t * Pipeline fill\n\t *\n\t */\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline feed */\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/*\n\t * Pipeline run\n\t *\n\t */\n\tfor ( ; pkts_mask; ) {\n\t\t/* Pipeline feed */\n\t\tbucket20 = bucket10;\n\t\tbucket21 = bucket11;\n\t\tmbuf20 = mbuf10;\n\t\tmbuf21 = mbuf11;\n\t\tmbuf10 = mbuf00;\n\t\tmbuf11 = mbuf01;\n\t\tpkt20_index = pkt10_index;\n\t\tpkt21_index = pkt11_index;\n\t\tpkt10_index = pkt00_index;\n\t\tpkt11_index = pkt01_index;\n\n\t\t/* Pipeline stage 0 */\n\t\tlookup2_stage0_with_odd_support(pkt00_index, pkt01_index,\n\t\t\tmbuf00, mbuf01, pkts, pkts_mask);\n\n\t\t/* Pipeline stage 1 */\n\t\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t\t/* Pipeline stage 2 */\n\t\tlookup2_stage2_lru(pkt20_index, pkt21_index,\n\t\t\tmbuf20, mbuf21, bucket20, bucket21, pkts_mask_out,\n\t\t\tentries, f);\n\t}\n\n\t/*\n\t * Pipeline flush\n\t *\n\t */\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_lru(pkt20_index, pkt21_index,\n\t\tmbuf20, mbuf21, bucket20, bucket21, pkts_mask_out, entries, f);\n\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_lru(pkt20_index, pkt21_index,\n\t\tmbuf20, mbuf21, bucket20, bucket21, pkts_mask_out, entries, f);\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_KEY32_STATS_PKTS_LOOKUP_MISS(f, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn 0;\n} /* rte_table_hash_lookup_key32_lru() */\n\nstatic int\nrte_table_hash_lookup_key32_ext(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_32 *bucket10, *bucket11, *bucket20, *bucket21;\n\tstruct rte_mbuf *mbuf00, *mbuf01, *mbuf10, *mbuf11, *mbuf20, *mbuf21;\n\tuint32_t pkt00_index, pkt01_index, pkt10_index;\n\tuint32_t pkt11_index, pkt20_index, pkt21_index;\n\tuint64_t pkts_mask_out = 0, buckets_mask = 0;\n\tstruct rte_bucket_4_32 *buckets[RTE_PORT_IN_BURST_SIZE_MAX];\n\tuint64_t *keys[RTE_PORT_IN_BURST_SIZE_MAX];\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_KEY32_STATS_PKTS_IN_ADD(f, n_pkts_in);\n\n\t/* Cannot run the pipeline with less than 5 packets */\n\tif (__builtin_popcountll(pkts_mask) < 5) {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tstruct rte_bucket_4_32 *bucket;\n\t\t\tstruct rte_mbuf *mbuf;\n\t\t\tuint32_t pkt_index;\n\n\t\t\tlookup1_stage0(pkt_index, mbuf, pkts, pkts_mask);\n\t\t\tlookup1_stage1(mbuf, bucket, f);\n\t\t\tlookup1_stage2_ext(pkt_index, mbuf, bucket,\n\t\t\t\tpkts_mask_out, entries, buckets_mask, buckets,\n\t\t\t\tkeys, f);\n\t\t}\n\n\t\tgoto grind_next_buckets;\n\t}\n\n\t/*\n\t * Pipeline fill\n\t *\n\t */\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline feed */\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/*\n\t * Pipeline run\n\t *\n\t */\n\tfor ( ; pkts_mask; ) {\n\t\t/* Pipeline feed */\n\t\tbucket20 = bucket10;\n\t\tbucket21 = bucket11;\n\t\tmbuf20 = mbuf10;\n\t\tmbuf21 = mbuf11;\n\t\tmbuf10 = mbuf00;\n\t\tmbuf11 = mbuf01;\n\t\tpkt20_index = pkt10_index;\n\t\tpkt21_index = pkt11_index;\n\t\tpkt10_index = pkt00_index;\n\t\tpkt11_index = pkt01_index;\n\n\t\t/* Pipeline stage 0 */\n\t\tlookup2_stage0_with_odd_support(pkt00_index, pkt01_index,\n\t\t\tmbuf00, mbuf01, pkts, pkts_mask);\n\n\t\t/* Pipeline stage 1 */\n\t\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t\t/* Pipeline stage 2 */\n\t\tlookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\t\tbucket20, bucket21, pkts_mask_out, entries,\n\t\t\tbuckets_mask, buckets, keys, f);\n\t}\n\n\t/*\n\t * Pipeline flush\n\t *\n\t */\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries,\n\t\tbuckets_mask, buckets, keys, f);\n\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries,\n\t\tbuckets_mask, buckets, keys, f);\n\ngrind_next_buckets:\n\t/* Grind next buckets */\n\tfor ( ; buckets_mask; ) {\n\t\tuint64_t buckets_mask_next = 0;\n\n\t\tfor ( ; buckets_mask; ) {\n\t\t\tuint64_t pkt_mask;\n\t\t\tuint32_t pkt_index;\n\n\t\t\tpkt_index = __builtin_ctzll(buckets_mask);\n\t\t\tpkt_mask = 1LLU << pkt_index;\n\t\t\tbuckets_mask &= ~pkt_mask;\n\n\t\t\tlookup_grinder(pkt_index, buckets, keys, pkts_mask_out,\n\t\t\t\tentries, buckets_mask_next, f);\n\t\t}\n\n\t\tbuckets_mask = buckets_mask_next;\n\t}\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_KEY32_STATS_PKTS_LOOKUP_MISS(f, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn 0;\n} /* rte_table_hash_lookup_key32_ext() */\n\nstatic int\nrte_table_hash_key32_stats_read(void *table, struct rte_table_stats *stats, int clear)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &t->stats, sizeof(t->stats));\n\n\tif (clear)\n\t\tmemset(&t->stats, 0, sizeof(t->stats));\n\n\treturn 0;\n}\n\nstruct rte_table_ops rte_table_hash_key32_lru_ops = {\n\t.f_create = rte_table_hash_create_key32_lru,\n\t.f_free = rte_table_hash_free_key32_lru,\n\t.f_add = rte_table_hash_entry_add_key32_lru,\n\t.f_delete = rte_table_hash_entry_delete_key32_lru,\n\t.f_lookup = rte_table_hash_lookup_key32_lru,\n\t.f_stats = rte_table_hash_key32_stats_read,\n};\n\nstruct rte_table_ops rte_table_hash_key32_ext_ops = {\n\t.f_create = rte_table_hash_create_key32_ext,\n\t.f_free = rte_table_hash_free_key32_ext,\n\t.f_add = rte_table_hash_entry_add_key32_ext,\n\t.f_delete = rte_table_hash_entry_delete_key32_ext,\n\t.f_lookup = rte_table_hash_lookup_key32_ext,\n\t.f_stats = rte_table_hash_key32_stats_read,\n};\n" }, { "path": "lib/librte_table/rte_table_hash_key8.c", "content": "/*-\n *\t BSD LICENSE\n *\n *\t Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\t All rights reserved.\n *\n *\t Redistribution and use in source and binary forms, with or without\n *\t modification, are permitted provided that the following conditions\n *\t are met:\n *\n *\t* Redistributions of source code must retain the above copyright\n *\t\t notice, this list of conditions and the following disclaimer.\n *\t* Redistributions in binary form must reproduce the above copyright\n *\t\t notice, this list of conditions and the following disclaimer in\n *\t\t the documentation and/or other materials provided with the\n *\t\t distribution.\n *\t* Neither the name of Intel Corporation nor the names of its\n *\t\t contributors may be used to endorse or promote products derived\n *\t\t from this software without specific prior written permission.\n *\n *\t THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n *\t \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n *\t LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n *\t A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n *\t OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n *\t SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n *\t LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n *\t DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n *\t THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n *\t (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n *\t OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_table_hash.h\"\n#include \"rte_lru.h\"\n\n#define RTE_TABLE_HASH_KEY_SIZE\t\t\t\t\t\t8\n\n#ifdef RTE_TABLE_STATS_COLLECT\n\n#define RTE_TABLE_HASH_KEY8_STATS_PKTS_IN_ADD(table, val) \\\n\ttable->stats.n_pkts_in += val\n#define RTE_TABLE_HASH_KEY8_STATS_PKTS_LOOKUP_MISS(table, val) \\\n\ttable->stats.n_pkts_lookup_miss += val\n\n#else\n\n#define RTE_TABLE_HASH_KEY8_STATS_PKTS_IN_ADD(table, val)\n#define RTE_TABLE_HASH_KEY8_STATS_PKTS_LOOKUP_MISS(table, val)\n\n#endif\n\nstruct rte_bucket_4_8 {\n\t/* Cache line 0 */\n\tuint64_t signature;\n\tuint64_t lru_list;\n\tstruct rte_bucket_4_8 *next;\n\tuint64_t next_valid;\n\n\tuint64_t key[4];\n\n\t/* Cache line 1 */\n\tuint8_t data[0];\n};\n\nstruct rte_table_hash {\n\tstruct rte_table_stats stats;\n\n\t/* Input parameters */\n\tuint32_t n_buckets;\n\tuint32_t n_entries_per_bucket;\n\tuint32_t key_size;\n\tuint32_t entry_size;\n\tuint32_t bucket_size;\n\tuint32_t signature_offset;\n\tuint32_t key_offset;\n\trte_table_hash_op_hash f_hash;\n\tuint64_t seed;\n\n\t/* Extendible buckets */\n\tuint32_t n_buckets_ext;\n\tuint32_t stack_pos;\n\tuint32_t *stack;\n\n\t/* Lookup table */\n\tuint8_t memory[0] __rte_cache_aligned;\n};\n\nstatic int\ncheck_params_create_lru(struct rte_table_hash_key8_lru_params *params) {\n\t/* n_entries */\n\tif (params->n_entries == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_entries is zero\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* f_hash */\n\tif (params->f_hash == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: f_hash function pointer is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic void *\nrte_table_hash_create_key8_lru(void *params, int socket_id, uint32_t entry_size)\n{\n\tstruct rte_table_hash_key8_lru_params *p =\n\t\t(struct rte_table_hash_key8_lru_params *) params;\n\tstruct rte_table_hash *f;\n\tuint32_t n_buckets, n_entries_per_bucket, key_size, bucket_size_cl;\n\tuint32_t total_size, i;\n\n\t/* Check input parameters */\n\tif ((check_params_create_lru(p) != 0) ||\n\t\t((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||\n\t\t((sizeof(struct rte_bucket_4_8) % RTE_CACHE_LINE_SIZE) != 0)) {\n\t\treturn NULL;\n\t}\n\tn_entries_per_bucket = 4;\n\tkey_size = 8;\n\n\t/* Memory allocation */\n\tn_buckets = rte_align32pow2((p->n_entries + n_entries_per_bucket - 1) /\n\t\tn_entries_per_bucket);\n\tbucket_size_cl = (sizeof(struct rte_bucket_4_8) + n_entries_per_bucket *\n\t\tentry_size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;\n\ttotal_size = sizeof(struct rte_table_hash) + n_buckets *\n\t\tbucket_size_cl * RTE_CACHE_LINE_SIZE;\n\n\tf = rte_zmalloc_socket(\"TABLE\", total_size, RTE_CACHE_LINE_SIZE, socket_id);\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot allocate %u bytes for hash table\\n\",\n\t\t\t__func__, total_size);\n\t\treturn NULL;\n\t}\n\tRTE_LOG(INFO, TABLE,\n\t\t\"%s: Hash table memory footprint is %u bytes\\n\",\n\t\t__func__, total_size);\n\n\t/* Memory initialization */\n\tf->n_buckets = n_buckets;\n\tf->n_entries_per_bucket = n_entries_per_bucket;\n\tf->key_size = key_size;\n\tf->entry_size = entry_size;\n\tf->bucket_size = bucket_size_cl * RTE_CACHE_LINE_SIZE;\n\tf->signature_offset = p->signature_offset;\n\tf->key_offset = p->key_offset;\n\tf->f_hash = p->f_hash;\n\tf->seed = p->seed;\n\n\tfor (i = 0; i < n_buckets; i++) {\n\t\tstruct rte_bucket_4_8 *bucket;\n\n\t\tbucket = (struct rte_bucket_4_8 *) &f->memory[i *\n\t\t\tf->bucket_size];\n\t\tbucket->lru_list = 0x0000000100020003LLU;\n\t}\n\n\treturn f;\n}\n\nstatic int\nrte_table_hash_free_key8_lru(void *table)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\n\t/* Check input parameters */\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_free(f);\n\treturn 0;\n}\n\nstatic int\nrte_table_hash_entry_add_key8_lru(\n\tvoid *table,\n\tvoid *key,\n\tvoid *entry,\n\tint *key_found,\n\tvoid **entry_ptr)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_8 *bucket;\n\tuint64_t signature, mask, pos;\n\tuint32_t bucket_index, i;\n\n\tsignature = f->f_hash(key, f->key_size, f->seed);\n\tbucket_index = signature & (f->n_buckets - 1);\n\tbucket = (struct rte_bucket_4_8 *)\n\t\t&f->memory[bucket_index * f->bucket_size];\n\n\t/* Key is present in the bucket */\n\tfor (i = 0, mask = 1LLU; i < 4; i++, mask <<= 1) {\n\t\tuint64_t bucket_signature = bucket->signature;\n\t\tuint64_t bucket_key = bucket->key[i];\n\n\t\tif ((bucket_signature & mask) &&\n\t\t (*((uint64_t *) key) == bucket_key)) {\n\t\t\tuint8_t *bucket_data = &bucket->data[i * f->entry_size];\n\n\t\t\tmemcpy(bucket_data, entry, f->entry_size);\n\t\t\tlru_update(bucket, i);\n\t\t\t*key_found = 1;\n\t\t\t*entry_ptr = (void *) bucket_data;\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Key is not present in the bucket */\n\tfor (i = 0, mask = 1LLU; i < 4; i++, mask <<= 1) {\n\t\tuint64_t bucket_signature = bucket->signature;\n\n\t\tif ((bucket_signature & mask) == 0) {\n\t\t\tuint8_t *bucket_data = &bucket->data[i * f->entry_size];\n\n\t\t\tbucket->signature |= mask;\n\t\t\tbucket->key[i] = *((uint64_t *) key);\n\t\t\tmemcpy(bucket_data, entry, f->entry_size);\n\t\t\tlru_update(bucket, i);\n\t\t\t*key_found = 0;\n\t\t\t*entry_ptr = (void *) bucket_data;\n\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Bucket full: replace LRU entry */\n\tpos = lru_pos(bucket);\n\tbucket->key[pos] = *((uint64_t *) key);\n\tmemcpy(&bucket->data[pos * f->entry_size], entry, f->entry_size);\n\tlru_update(bucket, pos);\n\t*key_found\t= 0;\n\t*entry_ptr = (void *) &bucket->data[pos * f->entry_size];\n\n\treturn 0;\n}\n\nstatic int\nrte_table_hash_entry_delete_key8_lru(\n\tvoid *table,\n\tvoid *key,\n\tint *key_found,\n\tvoid *entry)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_8 *bucket;\n\tuint64_t signature, mask;\n\tuint32_t bucket_index, i;\n\n\tsignature = f->f_hash(key, f->key_size, f->seed);\n\tbucket_index = signature & (f->n_buckets - 1);\n\tbucket = (struct rte_bucket_4_8 *)\n\t\t&f->memory[bucket_index * f->bucket_size];\n\n\t/* Key is present in the bucket */\n\tfor (i = 0, mask = 1LLU; i < 4; i++, mask <<= 1) {\n\t\tuint64_t bucket_signature = bucket->signature;\n\t\tuint64_t bucket_key = bucket->key[i];\n\n\t\tif ((bucket_signature & mask) &&\n\t\t (*((uint64_t *) key) == bucket_key)) {\n\t\t\tuint8_t *bucket_data = &bucket->data[i * f->entry_size];\n\n\t\t\tbucket->signature &= ~mask;\n\t\t\t*key_found = 1;\n\t\t\tif (entry)\n\t\t\t\tmemcpy(entry, bucket_data, f->entry_size);\n\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Key is not present in the bucket */\n\t*key_found = 0;\n\treturn 0;\n}\n\nstatic int\ncheck_params_create_ext(struct rte_table_hash_key8_ext_params *params) {\n\t/* n_entries */\n\tif (params->n_entries == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_entries is zero\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* n_entries_ext */\n\tif (params->n_entries_ext == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_entries_ext is zero\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* f_hash */\n\tif (params->f_hash == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: f_hash function pointer is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic void *\nrte_table_hash_create_key8_ext(void *params, int socket_id, uint32_t entry_size)\n{\n\tstruct rte_table_hash_key8_ext_params *p =\n\t\t(struct rte_table_hash_key8_ext_params *) params;\n\tstruct rte_table_hash *f;\n\tuint32_t n_buckets, n_buckets_ext, n_entries_per_bucket, key_size;\n\tuint32_t bucket_size_cl, stack_size_cl, total_size, i;\n\n\t/* Check input parameters */\n\tif ((check_params_create_ext(p) != 0) ||\n\t\t((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||\n\t\t((sizeof(struct rte_bucket_4_8) % RTE_CACHE_LINE_SIZE) != 0))\n\t\treturn NULL;\n\n\tn_entries_per_bucket = 4;\n\tkey_size = 8;\n\n\t/* Memory allocation */\n\tn_buckets = rte_align32pow2((p->n_entries + n_entries_per_bucket - 1) /\n\t\tn_entries_per_bucket);\n\tn_buckets_ext = (p->n_entries_ext + n_entries_per_bucket - 1) /\n\t\tn_entries_per_bucket;\n\tbucket_size_cl = (sizeof(struct rte_bucket_4_8) + n_entries_per_bucket *\n\t\tentry_size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;\n\tstack_size_cl = (n_buckets_ext * sizeof(uint32_t) + RTE_CACHE_LINE_SIZE - 1)\n\t\t/ RTE_CACHE_LINE_SIZE;\n\ttotal_size = sizeof(struct rte_table_hash) + ((n_buckets +\n\t\tn_buckets_ext) * bucket_size_cl + stack_size_cl) *\n\t\tRTE_CACHE_LINE_SIZE;\n\n\tf = rte_zmalloc_socket(\"TABLE\", total_size, RTE_CACHE_LINE_SIZE, socket_id);\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot allocate %u bytes for hash table\\n\",\n\t\t\t__func__, total_size);\n\t\treturn NULL;\n\t}\n\tRTE_LOG(INFO, TABLE,\n\t\t\"%s: Hash table memory footprint is %u bytes\\n\",\n\t\t__func__, total_size);\n\n\t/* Memory initialization */\n\tf->n_buckets = n_buckets;\n\tf->n_entries_per_bucket = n_entries_per_bucket;\n\tf->key_size = key_size;\n\tf->entry_size = entry_size;\n\tf->bucket_size = bucket_size_cl * RTE_CACHE_LINE_SIZE;\n\tf->signature_offset = p->signature_offset;\n\tf->key_offset = p->key_offset;\n\tf->f_hash = p->f_hash;\n\tf->seed = p->seed;\n\n\tf->n_buckets_ext = n_buckets_ext;\n\tf->stack_pos = n_buckets_ext;\n\tf->stack = (uint32_t *)\n\t\t&f->memory[(n_buckets + n_buckets_ext) * f->bucket_size];\n\n\tfor (i = 0; i < n_buckets_ext; i++)\n\t\tf->stack[i] = i;\n\n\treturn f;\n}\n\nstatic int\nrte_table_hash_free_key8_ext(void *table)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\n\t/* Check input parameters */\n\tif (f == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\trte_free(f);\n\treturn 0;\n}\n\nstatic int\nrte_table_hash_entry_add_key8_ext(\n\tvoid *table,\n\tvoid *key,\n\tvoid *entry,\n\tint *key_found,\n\tvoid **entry_ptr)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_8 *bucket0, *bucket, *bucket_prev;\n\tuint64_t signature;\n\tuint32_t bucket_index, i;\n\n\tsignature = f->f_hash(key, f->key_size, f->seed);\n\tbucket_index = signature & (f->n_buckets - 1);\n\tbucket0 = (struct rte_bucket_4_8 *)\n\t\t&f->memory[bucket_index * f->bucket_size];\n\n\t/* Key is present in the bucket */\n\tfor (bucket = bucket0; bucket != NULL; bucket = bucket->next) {\n\t\tuint64_t mask;\n\n\t\tfor (i = 0, mask = 1LLU; i < 4; i++, mask <<= 1) {\n\t\t\tuint64_t bucket_signature = bucket->signature;\n\t\t\tuint64_t bucket_key = bucket->key[i];\n\n\t\t\tif ((bucket_signature & mask) &&\n\t\t\t\t\t(*((uint64_t *) key) == bucket_key)) {\n\t\t\t\tuint8_t *bucket_data = &bucket->data[i *\n\t\t\t\t\tf->entry_size];\n\n\t\t\t\tmemcpy(bucket_data, entry, f->entry_size);\n\t\t\t\t*key_found = 1;\n\t\t\t\t*entry_ptr = (void *) bucket_data;\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Key is not present in the bucket */\n\tfor (bucket_prev = NULL, bucket = bucket0;\n\t\tbucket != NULL; bucket_prev = bucket, bucket = bucket->next) {\n\t\tuint64_t mask;\n\n\t\tfor (i = 0, mask = 1LLU; i < 4; i++, mask <<= 1) {\n\t\t\tuint64_t bucket_signature = bucket->signature;\n\n\t\t\tif ((bucket_signature & mask) == 0) {\n\t\t\t\tuint8_t *bucket_data = &bucket->data[i *\n\t\t\t\t\tf->entry_size];\n\n\t\t\t\tbucket->signature |= mask;\n\t\t\t\tbucket->key[i] = *((uint64_t *) key);\n\t\t\t\tmemcpy(bucket_data, entry, f->entry_size);\n\t\t\t\t*key_found = 0;\n\t\t\t\t*entry_ptr = (void *) bucket_data;\n\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Bucket full: extend bucket */\n\tif (f->stack_pos > 0) {\n\t\tbucket_index = f->stack[--f->stack_pos];\n\n\t\tbucket = (struct rte_bucket_4_8 *) &f->memory[(f->n_buckets +\n\t\t\tbucket_index) * f->bucket_size];\n\t\tbucket_prev->next = bucket;\n\t\tbucket_prev->next_valid = 1;\n\n\t\tbucket->signature = 1;\n\t\tbucket->key[0] = *((uint64_t *) key);\n\t\tmemcpy(&bucket->data[0], entry, f->entry_size);\n\t\t*key_found = 0;\n\t\t*entry_ptr = (void *) &bucket->data[0];\n\t\treturn 0;\n\t}\n\n\treturn -ENOSPC;\n}\n\nstatic int\nrte_table_hash_entry_delete_key8_ext(\n\tvoid *table,\n\tvoid *key,\n\tint *key_found,\n\tvoid *entry)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_8 *bucket0, *bucket, *bucket_prev;\n\tuint64_t signature;\n\tuint32_t bucket_index, i;\n\n\tsignature = f->f_hash(key, f->key_size, f->seed);\n\tbucket_index = signature & (f->n_buckets - 1);\n\tbucket0 = (struct rte_bucket_4_8 *)\n\t\t&f->memory[bucket_index * f->bucket_size];\n\n\t/* Key is present in the bucket */\n\tfor (bucket_prev = NULL, bucket = bucket0; bucket != NULL;\n\t\tbucket_prev = bucket, bucket = bucket->next) {\n\t\tuint64_t mask;\n\n\t\tfor (i = 0, mask = 1LLU; i < 4; i++, mask <<= 1) {\n\t\t\tuint64_t bucket_signature = bucket->signature;\n\t\t\tuint64_t bucket_key = bucket->key[i];\n\n\t\t\tif ((bucket_signature & mask) &&\n\t\t\t\t(*((uint64_t *) key) == bucket_key)) {\n\t\t\t\tuint8_t *bucket_data = &bucket->data[i *\n\t\t\t\t\tf->entry_size];\n\n\t\t\t\tbucket->signature &= ~mask;\n\t\t\t\t*key_found = 1;\n\t\t\t\tif (entry)\n\t\t\t\t\tmemcpy(entry, bucket_data,\n\t\t\t\t\t\tf->entry_size);\n\n\t\t\t\tif ((bucket->signature == 0) &&\n\t\t\t\t (bucket_prev != NULL)) {\n\t\t\t\t\tbucket_prev->next = bucket->next;\n\t\t\t\t\tbucket_prev->next_valid =\n\t\t\t\t\t\tbucket->next_valid;\n\n\t\t\t\t\tmemset(bucket, 0,\n\t\t\t\t\t\tsizeof(struct rte_bucket_4_8));\n\t\t\t\t\tbucket_index = (((uint8_t *)bucket -\n\t\t\t\t\t\t(uint8_t *)f->memory)/f->bucket_size) - f->n_buckets;\n\t\t\t\t\tf->stack[f->stack_pos++] = bucket_index;\n\t\t\t\t}\n\n\t\t\t\treturn 0;\n\t\t\t}\n\t\t}\n\t}\n\n\t/* Key is not present in the bucket */\n\t*key_found = 0;\n\treturn 0;\n}\n\n#define lookup_key8_cmp(key_in, bucket, pos)\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t xor[4], signature;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tsignature = ~bucket->signature;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\txor[0] = (key_in[0] ^\t bucket->key[0]) | (signature & 1);\\\n\txor[1] = (key_in[0] ^\t bucket->key[1]) | (signature & 2);\\\n\txor[2] = (key_in[0] ^\t bucket->key[2]) | (signature & 4);\\\n\txor[3] = (key_in[0] ^\t bucket->key[3]) | (signature & 8);\\\n\t\t\t\t\t\t\t\t\\\n\tpos = 4;\t\t\t\t\t\t\\\n\tif (xor[0] == 0)\t\t\t\t\t\\\n\t\tpos = 0;\t\t\t\t\t\\\n\tif (xor[1] == 0)\t\t\t\t\t\\\n\t\tpos = 1;\t\t\t\t\t\\\n\tif (xor[2] == 0)\t\t\t\t\t\\\n\t\tpos = 2;\t\t\t\t\t\\\n\tif (xor[3] == 0)\t\t\t\t\t\\\n\t\tpos = 3;\t\t\t\t\t\\\n}\n\n#define lookup1_stage0(pkt0_index, mbuf0, pkts, pkts_mask)\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt_mask;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt0_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt_mask = 1LLU << pkt0_index;\t\t\t\t\\\n\tpkts_mask &= ~pkt_mask;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf0 = pkts[pkt0_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf0, 0));\t\\\n}\n\n#define lookup1_stage1(mbuf1, bucket1, f)\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t signature;\t\t\t\t\t\\\n\tuint32_t bucket_index;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tsignature = RTE_MBUF_METADATA_UINT32(mbuf1, f->signature_offset);\\\n\tbucket_index = signature & (f->n_buckets - 1);\t\t\\\n\tbucket1 = (struct rte_bucket_4_8 *)\t\t\t\\\n\t\t&f->memory[bucket_index * f->bucket_size];\t\\\n\trte_prefetch0(bucket1);\t\t\t\t\t\\\n}\n\n#define lookup1_stage1_dosig(mbuf1, bucket1, f)\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t *key;\t\t\t\t\t\t\\\n\tuint64_t signature;\t\t\t\t\t\\\n\tuint32_t bucket_index;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey = RTE_MBUF_METADATA_UINT64_PTR(mbuf1, f->key_offset);\\\n\tsignature = f->f_hash(key, RTE_TABLE_HASH_KEY_SIZE, f->seed);\\\n\tbucket_index = signature & (f->n_buckets - 1);\t\t\\\n\tbucket1 = (struct rte_bucket_4_8 *)\t\t\t\\\n\t\t&f->memory[bucket_index * f->bucket_size];\t\\\n\trte_prefetch0(bucket1);\t\t\t\t\t\\\n}\n\n#define lookup1_stage2_lru(pkt2_index, mbuf2, bucket2,\t\t\\\n\tpkts_mask_out, entries, f)\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tvoid *a;\t\t\t\t\t\t\\\n\tuint64_t pkt_mask;\t\t\t\t\t\\\n\tuint64_t *key;\t\t\t\t\t\t\\\n\tuint32_t pos;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey = RTE_MBUF_METADATA_UINT64_PTR(mbuf2, f->key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key8_cmp(key, bucket2, pos);\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt_mask = ((bucket2->signature >> pos) & 1LLU) << pkt2_index;\\\n\tpkts_mask_out |= pkt_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta = (void *) &bucket2->data[pos * f->entry_size];\t\\\n\trte_prefetch0(a);\t\t\t\t\t\\\n\tentries[pkt2_index] = a;\t\t\t\t\\\n\tlru_update(bucket2, pos);\t\t\t\t\\\n}\n\n#define lookup1_stage2_ext(pkt2_index, mbuf2, bucket2, pkts_mask_out,\\\n\tentries, buckets_mask, buckets, keys, f)\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tstruct rte_bucket_4_8 *bucket_next;\t\t\t\\\n\tvoid *a;\t\t\t\t\t\t\\\n\tuint64_t pkt_mask, bucket_mask;\t\t\t\t\\\n\tuint64_t *key;\t\t\t\t\t\t\\\n\tuint32_t pos;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey = RTE_MBUF_METADATA_UINT64_PTR(mbuf2, f->key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key8_cmp(key, bucket2, pos);\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt_mask = ((bucket2->signature >> pos) & 1LLU) << pkt2_index;\\\n\tpkts_mask_out |= pkt_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta = (void *) &bucket2->data[pos * f->entry_size];\t\\\n\trte_prefetch0(a);\t\t\t\t\t\\\n\tentries[pkt2_index] = a;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket_mask = (~pkt_mask) & (bucket2->next_valid << pkt2_index);\\\n\tbuckets_mask |= bucket_mask;\t\t\t\t\\\n\tbucket_next = bucket2->next;\t\t\t\t\\\n\tbuckets[pkt2_index] = bucket_next;\t\t\t\\\n\tkeys[pkt2_index] = key;\t\t\t\t\t\\\n}\n\n#define lookup_grinder(pkt_index, buckets, keys, pkts_mask_out, entries,\\\n\tbuckets_mask, f)\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tstruct rte_bucket_4_8 *bucket, *bucket_next;\t\t\\\n\tvoid *a;\t\t\t\t\t\t\\\n\tuint64_t pkt_mask, bucket_mask;\t\t\t\t\\\n\tuint64_t *key;\t\t\t\t\t\t\\\n\tuint32_t pos;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket = buckets[pkt_index];\t\t\t\t\\\n\tkey = keys[pkt_index];\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key8_cmp(key, bucket, pos);\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt_mask = ((bucket->signature >> pos) & 1LLU) << pkt_index;\\\n\tpkts_mask_out |= pkt_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta = (void *) &bucket->data[pos * f->entry_size];\t\\\n\trte_prefetch0(a);\t\t\t\t\t\\\n\tentries[pkt_index] = a;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket_mask = (~pkt_mask) & (bucket->next_valid << pkt_index);\\\n\tbuckets_mask |= bucket_mask;\t\t\t\t\\\n\tbucket_next = bucket->next;\t\t\t\t\\\n\trte_prefetch0(bucket_next);\t\t\t\t\\\n\tbuckets[pkt_index] = bucket_next;\t\t\t\\\n\tkeys[pkt_index] = key;\t\t\t\t\t\\\n}\n\n#define lookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01,\\\n\tpkts, pkts_mask)\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt00_mask, pkt01_mask;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt00_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt00_mask = 1LLU << pkt00_index;\t\t\t\\\n\tpkts_mask &= ~pkt00_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf00 = pkts[pkt00_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf00, 0));\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt01_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt01_mask = 1LLU << pkt01_index;\t\t\t\\\n\tpkts_mask &= ~pkt01_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf01 = pkts[pkt01_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf01, 0));\t\\\n}\n\n#define lookup2_stage0_with_odd_support(pkt00_index, pkt01_index,\\\n\tmbuf00, mbuf01, pkts, pkts_mask)\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt00_mask, pkt01_mask;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt00_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt00_mask = 1LLU << pkt00_index;\t\t\t\\\n\tpkts_mask &= ~pkt00_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf00 = pkts[pkt00_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf00, 0));\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt01_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tif (pkts_mask == 0)\t\t\t\t\t\\\n\t\tpkt01_index = pkt00_index;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt01_mask = 1LLU << pkt01_index;\t\t\t\\\n\tpkts_mask &= ~pkt01_mask;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf01 = pkts[pkt01_index];\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf01, 0));\t\\\n}\n\n#define lookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f)\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t signature10, signature11;\t\t\t\\\n\tuint32_t bucket10_index, bucket11_index;\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tsignature10 = RTE_MBUF_METADATA_UINT32(mbuf10, f->signature_offset);\\\n\tbucket10_index = signature10 & (f->n_buckets - 1);\t\\\n\tbucket10 = (struct rte_bucket_4_8 *)\t\t\t\\\n\t\t&f->memory[bucket10_index * f->bucket_size];\t\\\n\trte_prefetch0(bucket10);\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tsignature11 = RTE_MBUF_METADATA_UINT32(mbuf11, f->signature_offset);\\\n\tbucket11_index = signature11 & (f->n_buckets - 1);\t\\\n\tbucket11 = (struct rte_bucket_4_8 *)\t\t\t\\\n\t\t&f->memory[bucket11_index * f->bucket_size];\t\\\n\trte_prefetch0(bucket11);\t\t\t\t\\\n}\n\n#define lookup2_stage1_dosig(mbuf10, mbuf11, bucket10, bucket11, f)\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t *key10, *key11;\t\t\t\t\\\n\tuint64_t signature10, signature11;\t\t\t\\\n\tuint32_t bucket10_index, bucket11_index;\t\t\\\n\trte_table_hash_op_hash f_hash = f->f_hash;\t\t\\\n\tuint64_t seed = f->seed;\t\t\t\t\\\n\tuint32_t key_offset = f->key_offset;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey10 = RTE_MBUF_METADATA_UINT64_PTR(mbuf10, key_offset);\\\n\tkey11 = RTE_MBUF_METADATA_UINT64_PTR(mbuf11, key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tsignature10 = f_hash(key10, RTE_TABLE_HASH_KEY_SIZE, seed);\\\n\tbucket10_index = signature10 & (f->n_buckets - 1);\t\\\n\tbucket10 = (struct rte_bucket_4_8 *)\t\t\t\\\n\t\t&f->memory[bucket10_index * f->bucket_size];\t\\\n\trte_prefetch0(bucket10);\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tsignature11 = f_hash(key11, RTE_TABLE_HASH_KEY_SIZE, seed);\\\n\tbucket11_index = signature11 & (f->n_buckets - 1);\t\\\n\tbucket11 = (struct rte_bucket_4_8 *)\t\t\t\\\n\t\t&f->memory[bucket11_index * f->bucket_size];\t\\\n\trte_prefetch0(bucket11);\t\t\t\t\\\n}\n\n#define lookup2_stage2_lru(pkt20_index, pkt21_index, mbuf20, mbuf21,\\\n\tbucket20, bucket21, pkts_mask_out, entries, f)\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tvoid *a20, *a21;\t\t\t\t\t\\\n\tuint64_t pkt20_mask, pkt21_mask;\t\t\t\\\n\tuint64_t *key20, *key21;\t\t\t\t\\\n\tuint32_t pos20, pos21;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey20 = RTE_MBUF_METADATA_UINT64_PTR(mbuf20, f->key_offset);\\\n\tkey21 = RTE_MBUF_METADATA_UINT64_PTR(mbuf21, f->key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key8_cmp(key20, bucket20, pos20);\t\t\\\n\tlookup_key8_cmp(key21, bucket21, pos21);\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt20_mask = ((bucket20->signature >> pos20) & 1LLU) << pkt20_index;\\\n\tpkt21_mask = ((bucket21->signature >> pos21) & 1LLU) << pkt21_index;\\\n\tpkts_mask_out |= pkt20_mask | pkt21_mask;\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta20 = (void *) &bucket20->data[pos20 * f->entry_size];\t\\\n\ta21 = (void *) &bucket21->data[pos21 * f->entry_size];\t\\\n\trte_prefetch0(a20);\t\t\t\t\t\\\n\trte_prefetch0(a21);\t\t\t\t\t\\\n\tentries[pkt20_index] = a20;\t\t\t\t\\\n\tentries[pkt21_index] = a21;\t\t\t\t\\\n\tlru_update(bucket20, pos20);\t\t\t\t\\\n\tlru_update(bucket21, pos21);\t\t\t\t\\\n}\n\n#define lookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21, bucket20, \\\n\tbucket21, pkts_mask_out, entries, buckets_mask, buckets, keys, f)\\\n{\t\t\t\t\t\t\t\t\\\n\tstruct rte_bucket_4_8 *bucket20_next, *bucket21_next;\t\\\n\tvoid *a20, *a21;\t\t\t\t\t\\\n\tuint64_t pkt20_mask, pkt21_mask, bucket20_mask, bucket21_mask;\\\n\tuint64_t *key20, *key21;\t\t\t\t\\\n\tuint32_t pos20, pos21;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tkey20 = RTE_MBUF_METADATA_UINT64_PTR(mbuf20, f->key_offset);\\\n\tkey21 = RTE_MBUF_METADATA_UINT64_PTR(mbuf21, f->key_offset);\\\n\t\t\t\t\t\t\t\t\\\n\tlookup_key8_cmp(key20, bucket20, pos20);\t\t\\\n\tlookup_key8_cmp(key21, bucket21, pos21);\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt20_mask = ((bucket20->signature >> pos20) & 1LLU) << pkt20_index;\\\n\tpkt21_mask = ((bucket21->signature >> pos21) & 1LLU) << pkt21_index;\\\n\tpkts_mask_out |= pkt20_mask | pkt21_mask;\t\t\\\n\t\t\t\t\t\t\t\t\\\n\ta20 = (void *) &bucket20->data[pos20 * f->entry_size];\t\\\n\ta21 = (void *) &bucket21->data[pos21 * f->entry_size];\t\\\n\trte_prefetch0(a20);\t\t\t\t\t\\\n\trte_prefetch0(a21);\t\t\t\t\t\\\n\tentries[pkt20_index] = a20;\t\t\t\t\\\n\tentries[pkt21_index] = a21;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket20_mask = (~pkt20_mask) & (bucket20->next_valid << pkt20_index);\\\n\tbucket21_mask = (~pkt21_mask) & (bucket21->next_valid << pkt21_index);\\\n\tbuckets_mask |= bucket20_mask | bucket21_mask;\t\t\\\n\tbucket20_next = bucket20->next;\t\t\t\t\\\n\tbucket21_next = bucket21->next;\t\t\t\t\\\n\tbuckets[pkt20_index] = bucket20_next;\t\t\t\\\n\tbuckets[pkt21_index] = bucket21_next;\t\t\t\\\n\tkeys[pkt20_index] = key20;\t\t\t\t\\\n\tkeys[pkt21_index] = key21;\t\t\t\t\\\n}\n\nstatic int\nrte_table_hash_lookup_key8_lru(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_8 *bucket10, *bucket11, *bucket20, *bucket21;\n\tstruct rte_mbuf *mbuf00, *mbuf01, *mbuf10, *mbuf11, *mbuf20, *mbuf21;\n\tuint32_t pkt00_index, pkt01_index, pkt10_index,\n\t\t\tpkt11_index, pkt20_index, pkt21_index;\n\tuint64_t pkts_mask_out = 0;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_KEY8_STATS_PKTS_IN_ADD(f, n_pkts_in);\n\n\t/* Cannot run the pipeline with less than 5 packets */\n\tif (__builtin_popcountll(pkts_mask) < 5) {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tstruct rte_bucket_4_8 *bucket;\n\t\t\tstruct rte_mbuf *mbuf;\n\t\t\tuint32_t pkt_index;\n\n\t\t\tlookup1_stage0(pkt_index, mbuf, pkts, pkts_mask);\n\t\t\tlookup1_stage1(mbuf, bucket, f);\n\t\t\tlookup1_stage2_lru(pkt_index, mbuf, bucket,\n\t\t\t\t\tpkts_mask_out, entries, f);\n\t\t}\n\n\t\t*lookup_hit_mask = pkts_mask_out;\n\t\tRTE_TABLE_HASH_KEY8_STATS_PKTS_LOOKUP_MISS(f, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\t\treturn 0;\n\t}\n\n\t/*\n\t * Pipeline fill\n\t *\n\t */\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline feed */\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/*\n\t * Pipeline run\n\t *\n\t */\n\tfor ( ; pkts_mask; ) {\n\t\t/* Pipeline feed */\n\t\tbucket20 = bucket10;\n\t\tbucket21 = bucket11;\n\t\tmbuf20 = mbuf10;\n\t\tmbuf21 = mbuf11;\n\t\tmbuf10 = mbuf00;\n\t\tmbuf11 = mbuf01;\n\t\tpkt20_index = pkt10_index;\n\t\tpkt21_index = pkt11_index;\n\t\tpkt10_index = pkt00_index;\n\t\tpkt11_index = pkt01_index;\n\n\t\t/* Pipeline stage 0 */\n\t\tlookup2_stage0_with_odd_support(pkt00_index, pkt01_index,\n\t\t\tmbuf00, mbuf01, pkts, pkts_mask);\n\n\t\t/* Pipeline stage 1 */\n\t\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t\t/* Pipeline stage 2 */\n\t\tlookup2_stage2_lru(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\t\tbucket20, bucket21, pkts_mask_out, entries, f);\n\t}\n\n\t/*\n\t * Pipeline flush\n\t *\n\t */\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_lru(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries, f);\n\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_lru(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries, f);\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_KEY8_STATS_PKTS_LOOKUP_MISS(f, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn 0;\n} /* rte_table_hash_lookup_key8_lru() */\n\nstatic int\nrte_table_hash_lookup_key8_lru_dosig(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_8 *bucket10, *bucket11, *bucket20, *bucket21;\n\tstruct rte_mbuf *mbuf00, *mbuf01, *mbuf10, *mbuf11, *mbuf20, *mbuf21;\n\tuint32_t pkt00_index, pkt01_index, pkt10_index;\n\tuint32_t pkt11_index, pkt20_index, pkt21_index;\n\tuint64_t pkts_mask_out = 0;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_KEY8_STATS_PKTS_IN_ADD(f, n_pkts_in);\n\n\t/* Cannot run the pipeline with less than 5 packets */\n\tif (__builtin_popcountll(pkts_mask) < 5) {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tstruct rte_bucket_4_8 *bucket;\n\t\t\tstruct rte_mbuf *mbuf;\n\t\t\tuint32_t pkt_index;\n\n\t\t\tlookup1_stage0(pkt_index, mbuf, pkts, pkts_mask);\n\t\t\tlookup1_stage1_dosig(mbuf, bucket, f);\n\t\t\tlookup1_stage2_lru(pkt_index, mbuf, bucket,\n\t\t\t\tpkts_mask_out, entries, f);\n\t\t}\n\n\t\t*lookup_hit_mask = pkts_mask_out;\n\t\tRTE_TABLE_HASH_KEY8_STATS_PKTS_LOOKUP_MISS(f, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\t\treturn 0;\n\t}\n\n\t/*\n\t * Pipeline fill\n\t *\n\t */\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline feed */\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1_dosig(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/*\n\t * Pipeline run\n\t *\n\t */\n\tfor ( ; pkts_mask; ) {\n\t\t/* Pipeline feed */\n\t\tbucket20 = bucket10;\n\t\tbucket21 = bucket11;\n\t\tmbuf20 = mbuf10;\n\t\tmbuf21 = mbuf11;\n\t\tmbuf10 = mbuf00;\n\t\tmbuf11 = mbuf01;\n\t\tpkt20_index = pkt10_index;\n\t\tpkt21_index = pkt11_index;\n\t\tpkt10_index = pkt00_index;\n\t\tpkt11_index = pkt01_index;\n\n\t\t/* Pipeline stage 0 */\n\t\tlookup2_stage0_with_odd_support(pkt00_index, pkt01_index,\n\t\t\tmbuf00, mbuf01, pkts, pkts_mask);\n\n\t\t/* Pipeline stage 1 */\n\t\tlookup2_stage1_dosig(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t\t/* Pipeline stage 2 */\n\t\tlookup2_stage2_lru(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\t\tbucket20, bucket21, pkts_mask_out, entries, f);\n\t}\n\n\t/*\n\t * Pipeline flush\n\t *\n\t */\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1_dosig(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_lru(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries, f);\n\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_lru(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries, f);\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_KEY8_STATS_PKTS_LOOKUP_MISS(f, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn 0;\n} /* rte_table_hash_lookup_key8_lru_dosig() */\n\nstatic int\nrte_table_hash_lookup_key8_ext(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_8 *bucket10, *bucket11, *bucket20, *bucket21;\n\tstruct rte_mbuf *mbuf00, *mbuf01, *mbuf10, *mbuf11, *mbuf20, *mbuf21;\n\tuint32_t pkt00_index, pkt01_index, pkt10_index;\n\tuint32_t pkt11_index, pkt20_index, pkt21_index;\n\tuint64_t pkts_mask_out = 0, buckets_mask = 0;\n\tstruct rte_bucket_4_8 *buckets[RTE_PORT_IN_BURST_SIZE_MAX];\n\tuint64_t *keys[RTE_PORT_IN_BURST_SIZE_MAX];\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_KEY8_STATS_PKTS_IN_ADD(f, n_pkts_in);\n\n\t/* Cannot run the pipeline with less than 5 packets */\n\tif (__builtin_popcountll(pkts_mask) < 5) {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tstruct rte_bucket_4_8 *bucket;\n\t\t\tstruct rte_mbuf *mbuf;\n\t\t\tuint32_t pkt_index;\n\n\t\t\tlookup1_stage0(pkt_index, mbuf, pkts, pkts_mask);\n\t\t\tlookup1_stage1(mbuf, bucket, f);\n\t\t\tlookup1_stage2_ext(pkt_index, mbuf, bucket,\n\t\t\t\tpkts_mask_out, entries, buckets_mask, buckets,\n\t\t\t\tkeys, f);\n\t\t}\n\n\t\tgoto grind_next_buckets;\n\t}\n\n\t/*\n\t * Pipeline fill\n\t *\n\t */\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline feed */\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/*\n\t * Pipeline run\n\t *\n\t */\n\tfor ( ; pkts_mask; ) {\n\t\t/* Pipeline feed */\n\t\tbucket20 = bucket10;\n\t\tbucket21 = bucket11;\n\t\tmbuf20 = mbuf10;\n\t\tmbuf21 = mbuf11;\n\t\tmbuf10 = mbuf00;\n\t\tmbuf11 = mbuf01;\n\t\tpkt20_index = pkt10_index;\n\t\tpkt21_index = pkt11_index;\n\t\tpkt10_index = pkt00_index;\n\t\tpkt11_index = pkt01_index;\n\n\t\t/* Pipeline stage 0 */\n\t\tlookup2_stage0_with_odd_support(pkt00_index, pkt01_index,\n\t\t\tmbuf00, mbuf01, pkts, pkts_mask);\n\n\t\t/* Pipeline stage 1 */\n\t\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t\t/* Pipeline stage 2 */\n\t\tlookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\t\tbucket20, bucket21, pkts_mask_out, entries,\n\t\t\tbuckets_mask, buckets, keys, f);\n\t}\n\n\t/*\n\t * Pipeline flush\n\t *\n\t */\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries,\n\t\tbuckets_mask, buckets, keys, f);\n\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries,\n\t\tbuckets_mask, buckets, keys, f);\n\ngrind_next_buckets:\n\t/* Grind next buckets */\n\tfor ( ; buckets_mask; ) {\n\t\tuint64_t buckets_mask_next = 0;\n\n\t\tfor ( ; buckets_mask; ) {\n\t\t\tuint64_t pkt_mask;\n\t\t\tuint32_t pkt_index;\n\n\t\t\tpkt_index = __builtin_ctzll(buckets_mask);\n\t\t\tpkt_mask = 1LLU << pkt_index;\n\t\t\tbuckets_mask &= ~pkt_mask;\n\n\t\t\tlookup_grinder(pkt_index, buckets, keys, pkts_mask_out,\n\t\t\t\tentries, buckets_mask_next, f);\n\t\t}\n\n\t\tbuckets_mask = buckets_mask_next;\n\t}\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_KEY8_STATS_PKTS_LOOKUP_MISS(f, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn 0;\n} /* rte_table_hash_lookup_key8_ext() */\n\nstatic int\nrte_table_hash_lookup_key8_ext_dosig(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_hash *f = (struct rte_table_hash *) table;\n\tstruct rte_bucket_4_8 *bucket10, *bucket11, *bucket20, *bucket21;\n\tstruct rte_mbuf *mbuf00, *mbuf01, *mbuf10, *mbuf11, *mbuf20, *mbuf21;\n\tuint32_t pkt00_index, pkt01_index, pkt10_index;\n\tuint32_t pkt11_index, pkt20_index, pkt21_index;\n\tuint64_t pkts_mask_out = 0, buckets_mask = 0;\n\tstruct rte_bucket_4_8 *buckets[RTE_PORT_IN_BURST_SIZE_MAX];\n\tuint64_t *keys[RTE_PORT_IN_BURST_SIZE_MAX];\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_KEY8_STATS_PKTS_IN_ADD(f, n_pkts_in);\n\n\t/* Cannot run the pipeline with less than 5 packets */\n\tif (__builtin_popcountll(pkts_mask) < 5) {\n\t\tfor ( ; pkts_mask; ) {\n\t\t\tstruct rte_bucket_4_8 *bucket;\n\t\t\tstruct rte_mbuf *mbuf;\n\t\t\tuint32_t pkt_index;\n\n\t\t\tlookup1_stage0(pkt_index, mbuf, pkts, pkts_mask);\n\t\t\tlookup1_stage1_dosig(mbuf, bucket, f);\n\t\t\tlookup1_stage2_ext(pkt_index, mbuf, bucket,\n\t\t\t\tpkts_mask_out, entries, buckets_mask,\n\t\t\t\tbuckets, keys, f);\n\t\t}\n\n\t\tgoto grind_next_buckets;\n\t}\n\n\t/*\n\t * Pipeline fill\n\t *\n\t */\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline feed */\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(pkt00_index, pkt01_index, mbuf00, mbuf01, pkts,\n\t\tpkts_mask);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1_dosig(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/*\n\t * Pipeline run\n\t *\n\t */\n\tfor ( ; pkts_mask; ) {\n\t\t/* Pipeline feed */\n\t\tbucket20 = bucket10;\n\t\tbucket21 = bucket11;\n\t\tmbuf20 = mbuf10;\n\t\tmbuf21 = mbuf11;\n\t\tmbuf10 = mbuf00;\n\t\tmbuf11 = mbuf01;\n\t\tpkt20_index = pkt10_index;\n\t\tpkt21_index = pkt11_index;\n\t\tpkt10_index = pkt00_index;\n\t\tpkt11_index = pkt01_index;\n\n\t\t/* Pipeline stage 0 */\n\t\tlookup2_stage0_with_odd_support(pkt00_index, pkt01_index,\n\t\t\tmbuf00, mbuf01, pkts, pkts_mask);\n\n\t\t/* Pipeline stage 1 */\n\t\tlookup2_stage1_dosig(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t\t/* Pipeline stage 2 */\n\t\tlookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\t\tbucket20, bucket21, pkts_mask_out, entries,\n\t\t\tbuckets_mask, buckets, keys, f);\n\t}\n\n\t/*\n\t * Pipeline flush\n\t *\n\t */\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tmbuf10 = mbuf00;\n\tmbuf11 = mbuf01;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1_dosig(mbuf10, mbuf11, bucket10, bucket11, f);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries,\n\t\tbuckets_mask, buckets, keys, f);\n\n\t/* Pipeline feed */\n\tbucket20 = bucket10;\n\tbucket21 = bucket11;\n\tmbuf20 = mbuf10;\n\tmbuf21 = mbuf11;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2_ext(pkt20_index, pkt21_index, mbuf20, mbuf21,\n\t\tbucket20, bucket21, pkts_mask_out, entries,\n\t\tbuckets_mask, buckets, keys, f);\n\ngrind_next_buckets:\n\t/* Grind next buckets */\n\tfor ( ; buckets_mask; ) {\n\t\tuint64_t buckets_mask_next = 0;\n\n\t\tfor ( ; buckets_mask; ) {\n\t\t\tuint64_t pkt_mask;\n\t\t\tuint32_t pkt_index;\n\n\t\t\tpkt_index = __builtin_ctzll(buckets_mask);\n\t\t\tpkt_mask = 1LLU << pkt_index;\n\t\t\tbuckets_mask &= ~pkt_mask;\n\n\t\t\tlookup_grinder(pkt_index, buckets, keys, pkts_mask_out,\n\t\t\t\tentries, buckets_mask_next, f);\n\t\t}\n\n\t\tbuckets_mask = buckets_mask_next;\n\t}\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_KEY8_STATS_PKTS_LOOKUP_MISS(f, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn 0;\n} /* rte_table_hash_lookup_key8_dosig_ext() */\n\nstatic int\nrte_table_hash_key8_stats_read(void *table, struct rte_table_stats *stats, int clear)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &t->stats, sizeof(t->stats));\n\n\tif (clear)\n\t\tmemset(&t->stats, 0, sizeof(t->stats));\n\n\treturn 0;\n}\n\nstruct rte_table_ops rte_table_hash_key8_lru_ops = {\n\t.f_create = rte_table_hash_create_key8_lru,\n\t.f_free = rte_table_hash_free_key8_lru,\n\t.f_add = rte_table_hash_entry_add_key8_lru,\n\t.f_delete = rte_table_hash_entry_delete_key8_lru,\n\t.f_lookup = rte_table_hash_lookup_key8_lru,\n\t.f_stats = rte_table_hash_key8_stats_read,\n};\n\nstruct rte_table_ops rte_table_hash_key8_lru_dosig_ops = {\n\t.f_create = rte_table_hash_create_key8_lru,\n\t.f_free = rte_table_hash_free_key8_lru,\n\t.f_add = rte_table_hash_entry_add_key8_lru,\n\t.f_delete = rte_table_hash_entry_delete_key8_lru,\n\t.f_lookup = rte_table_hash_lookup_key8_lru_dosig,\n\t.f_stats = rte_table_hash_key8_stats_read,\n};\n\nstruct rte_table_ops rte_table_hash_key8_ext_ops = {\n\t.f_create = rte_table_hash_create_key8_ext,\n\t.f_free = rte_table_hash_free_key8_ext,\n\t.f_add = rte_table_hash_entry_add_key8_ext,\n\t.f_delete = rte_table_hash_entry_delete_key8_ext,\n\t.f_lookup = rte_table_hash_lookup_key8_ext,\n\t.f_stats = rte_table_hash_key8_stats_read,\n};\n\nstruct rte_table_ops rte_table_hash_key8_ext_dosig_ops = {\n\t.f_create = rte_table_hash_create_key8_ext,\n\t.f_free = rte_table_hash_free_key8_ext,\n\t.f_add = rte_table_hash_entry_add_key8_ext,\n\t.f_delete = rte_table_hash_entry_delete_key8_ext,\n\t.f_lookup = rte_table_hash_lookup_key8_ext_dosig,\n\t.f_stats = rte_table_hash_key8_stats_read,\n};\n" }, { "path": "lib/librte_table/rte_table_hash_lru.c", "content": "/*-\n *\t BSD LICENSE\n *\n *\t Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\t All rights reserved.\n *\n *\t Redistribution and use in source and binary forms, with or without\n *\t modification, are permitted provided that the following conditions\n *\t are met:\n *\n *\t* Redistributions of source code must retain the above copyright\n *\t\t notice, this list of conditions and the following disclaimer.\n *\t* Redistributions in binary form must reproduce the above copyright\n *\t\t notice, this list of conditions and the following disclaimer in\n *\t\t the documentation and/or other materials provided with the\n *\t\t distribution.\n *\t* Neither the name of Intel Corporation nor the names of its\n *\t\t contributors may be used to endorse or promote products derived\n *\t\t from this software without specific prior written permission.\n *\n *\t THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n *\t \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n *\t LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n *\t A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n *\t OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n *\t SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n *\t LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n *\t DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n *\t THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n *\t (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n *\t OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_table_hash.h\"\n#include \"rte_lru.h\"\n\n#define KEYS_PER_BUCKET\t4\n\n#ifdef RTE_TABLE_STATS_COLLECT\n\n#define RTE_TABLE_HASH_LRU_STATS_PKTS_IN_ADD(table, val) \\\n\ttable->stats.n_pkts_in += val\n#define RTE_TABLE_HASH_LRU_STATS_PKTS_LOOKUP_MISS(table, val) \\\n\ttable->stats.n_pkts_lookup_miss += val\n\n#else\n\n#define RTE_TABLE_HASH_LRU_STATS_PKTS_IN_ADD(table, val)\n#define RTE_TABLE_HASH_LRU_STATS_PKTS_LOOKUP_MISS(table, val)\n\n#endif\n\nstruct bucket {\n\tunion {\n\t\tstruct bucket *next;\n\t\tuint64_t lru_list;\n\t};\n\tuint16_t sig[KEYS_PER_BUCKET];\n\tuint32_t key_pos[KEYS_PER_BUCKET];\n};\n\nstruct grinder {\n\tstruct bucket *bkt;\n\tuint64_t sig;\n\tuint64_t match;\n\tuint64_t match_pos;\n\tuint32_t key_index;\n};\n\nstruct rte_table_hash {\n\tstruct rte_table_stats stats;\n\n\t/* Input parameters */\n\tuint32_t key_size;\n\tuint32_t entry_size;\n\tuint32_t n_keys;\n\tuint32_t n_buckets;\n\trte_table_hash_op_hash f_hash;\n\tuint64_t seed;\n\tuint32_t signature_offset;\n\tuint32_t key_offset;\n\n\t/* Internal */\n\tuint64_t bucket_mask;\n\tuint32_t key_size_shl;\n\tuint32_t data_size_shl;\n\tuint32_t key_stack_tos;\n\n\t/* Grinder */\n\tstruct grinder grinders[RTE_PORT_IN_BURST_SIZE_MAX];\n\n\t/* Tables */\n\tstruct bucket *buckets;\n\tuint8_t *key_mem;\n\tuint8_t *data_mem;\n\tuint32_t *key_stack;\n\n\t/* Table memory */\n\tuint8_t memory[0] __rte_cache_aligned;\n};\n\nstatic int\ncheck_params_create(struct rte_table_hash_lru_params *params)\n{\n\tuint32_t n_buckets_min;\n\n\t/* key_size */\n\tif ((params->key_size == 0) ||\n\t\t(!rte_is_power_of_2(params->key_size))) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: key_size invalid value\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* n_keys */\n\tif ((params->n_keys == 0) ||\n\t\t(!rte_is_power_of_2(params->n_keys))) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_keys invalid value\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* n_buckets */\n\tn_buckets_min = (params->n_keys + KEYS_PER_BUCKET - 1) / params->n_keys;\n\tif ((params->n_buckets == 0) ||\n\t\t(!rte_is_power_of_2(params->n_keys)) ||\n\t\t(params->n_buckets < n_buckets_min)) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: n_buckets invalid value\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* f_hash */\n\tif (params->f_hash == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: f_hash invalid value\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\treturn 0;\n}\n\nstatic void *\nrte_table_hash_lru_create(void *params, int socket_id, uint32_t entry_size)\n{\n\tstruct rte_table_hash_lru_params *p =\n\t\t(struct rte_table_hash_lru_params *) params;\n\tstruct rte_table_hash *t;\n\tuint32_t total_size, table_meta_sz;\n\tuint32_t bucket_sz, key_sz, key_stack_sz, data_sz;\n\tuint32_t bucket_offset, key_offset, key_stack_offset, data_offset;\n\tuint32_t i;\n\n\t/* Check input parameters */\n\tif ((check_params_create(p) != 0) ||\n\t\t(!rte_is_power_of_2(entry_size)) ||\n\t\t((sizeof(struct rte_table_hash) % RTE_CACHE_LINE_SIZE) != 0) ||\n\t\t(sizeof(struct bucket) != (RTE_CACHE_LINE_SIZE / 2))) {\n\t\treturn NULL;\n\t}\n\n\t/* Memory allocation */\n\ttable_meta_sz = RTE_CACHE_LINE_ROUNDUP(sizeof(struct rte_table_hash));\n\tbucket_sz = RTE_CACHE_LINE_ROUNDUP(p->n_buckets * sizeof(struct bucket));\n\tkey_sz = RTE_CACHE_LINE_ROUNDUP(p->n_keys * p->key_size);\n\tkey_stack_sz = RTE_CACHE_LINE_ROUNDUP(p->n_keys * sizeof(uint32_t));\n\tdata_sz = RTE_CACHE_LINE_ROUNDUP(p->n_keys * entry_size);\n\ttotal_size = table_meta_sz + bucket_sz + key_sz + key_stack_sz +\n\t\tdata_sz;\n\n\tt = rte_zmalloc_socket(\"TABLE\", total_size, RTE_CACHE_LINE_SIZE, socket_id);\n\tif (t == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot allocate %u bytes for hash table\\n\",\n\t\t\t__func__, total_size);\n\t\treturn NULL;\n\t}\n\tRTE_LOG(INFO, TABLE, \"%s (%u-byte key): Hash table memory footprint is \"\n\t\t\"%u bytes\\n\", __func__, p->key_size, total_size);\n\n\t/* Memory initialization */\n\tt->key_size = p->key_size;\n\tt->entry_size = entry_size;\n\tt->n_keys = p->n_keys;\n\tt->n_buckets = p->n_buckets;\n\tt->f_hash = p->f_hash;\n\tt->seed = p->seed;\n\tt->signature_offset = p->signature_offset;\n\tt->key_offset = p->key_offset;\n\n\t/* Internal */\n\tt->bucket_mask = t->n_buckets - 1;\n\tt->key_size_shl = __builtin_ctzl(p->key_size);\n\tt->data_size_shl = __builtin_ctzl(entry_size);\n\n\t/* Tables */\n\tbucket_offset = 0;\n\tkey_offset = bucket_offset + bucket_sz;\n\tkey_stack_offset = key_offset + key_sz;\n\tdata_offset = key_stack_offset + key_stack_sz;\n\n\tt->buckets = (struct bucket *) &t->memory[bucket_offset];\n\tt->key_mem = &t->memory[key_offset];\n\tt->key_stack = (uint32_t *) &t->memory[key_stack_offset];\n\tt->data_mem = &t->memory[data_offset];\n\n\t/* Key stack */\n\tfor (i = 0; i < t->n_keys; i++)\n\t\tt->key_stack[i] = t->n_keys - 1 - i;\n\tt->key_stack_tos = t->n_keys;\n\n\t/* LRU */\n\tfor (i = 0; i < t->n_buckets; i++) {\n\t\tstruct bucket *bkt = &t->buckets[i];\n\n\t\tlru_init(bkt);\n\t}\n\n\treturn t;\n}\n\nstatic int\nrte_table_hash_lru_free(void *table)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\n\t/* Check input parameters */\n\tif (t == NULL)\n\t\treturn -EINVAL;\n\n\trte_free(t);\n\treturn 0;\n}\n\nstatic int\nrte_table_hash_lru_entry_add(void *table, void *key, void *entry,\n\tint *key_found, void **entry_ptr)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\tstruct bucket *bkt;\n\tuint64_t sig;\n\tuint32_t bkt_index, i;\n\n\tsig = t->f_hash(key, t->key_size, t->seed);\n\tbkt_index = sig & t->bucket_mask;\n\tbkt = &t->buckets[bkt_index];\n\tsig = (sig >> 16) | 1LLU;\n\n\t/* Key is present in the bucket */\n\tfor (i = 0; i < KEYS_PER_BUCKET; i++) {\n\t\tuint64_t bkt_sig = (uint64_t) bkt->sig[i];\n\t\tuint32_t bkt_key_index = bkt->key_pos[i];\n\t\tuint8_t *bkt_key = &t->key_mem[bkt_key_index <<\n\t\t\tt->key_size_shl];\n\n\t\tif ((sig == bkt_sig) && (memcmp(key, bkt_key, t->key_size)\n\t\t\t== 0)) {\n\t\t\tuint8_t *data = &t->data_mem[bkt_key_index <<\n\t\t\t\tt->data_size_shl];\n\n\t\t\tmemcpy(data, entry, t->entry_size);\n\t\t\tlru_update(bkt, i);\n\t\t\t*key_found = 1;\n\t\t\t*entry_ptr = (void *) data;\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Key is not present in the bucket */\n\tfor (i = 0; i < KEYS_PER_BUCKET; i++) {\n\t\tuint64_t bkt_sig = (uint64_t) bkt->sig[i];\n\n\t\tif (bkt_sig == 0) {\n\t\t\tuint32_t bkt_key_index;\n\t\t\tuint8_t *bkt_key, *data;\n\n\t\t\t/* Allocate new key */\n\t\t\tif (t->key_stack_tos == 0) {\n\t\t\t\t/* No keys available */\n\t\t\t\treturn -ENOSPC;\n\t\t\t}\n\t\t\tbkt_key_index = t->key_stack[--t->key_stack_tos];\n\n\t\t\t/* Install new key */\n\t\t\tbkt_key = &t->key_mem[bkt_key_index << t->key_size_shl];\n\t\t\tdata = &t->data_mem[bkt_key_index << t->data_size_shl];\n\n\t\t\tbkt->sig[i] = (uint16_t) sig;\n\t\t\tbkt->key_pos[i] = bkt_key_index;\n\t\t\tmemcpy(bkt_key, key, t->key_size);\n\t\t\tmemcpy(data, entry, t->entry_size);\n\t\t\tlru_update(bkt, i);\n\n\t\t\t*key_found = 0;\n\t\t\t*entry_ptr = (void *) data;\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Bucket full */\n\t{\n\t\tuint64_t pos = lru_pos(bkt);\n\t\tuint32_t bkt_key_index = bkt->key_pos[pos];\n\t\tuint8_t *bkt_key = &t->key_mem[bkt_key_index <<\n\t\t\tt->key_size_shl];\n\t\tuint8_t *data = &t->data_mem[bkt_key_index << t->data_size_shl];\n\n\t\tbkt->sig[pos] = (uint16_t) sig;\n\t\tmemcpy(bkt_key, key, t->key_size);\n\t\tmemcpy(data, entry, t->entry_size);\n\t\tlru_update(bkt, pos);\n\n\t\t*key_found = 0;\n\t\t*entry_ptr = (void *) data;\n\t\treturn 0;\n\t}\n}\n\nstatic int\nrte_table_hash_lru_entry_delete(void *table, void *key, int *key_found,\n\tvoid *entry)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\tstruct bucket *bkt;\n\tuint64_t sig;\n\tuint32_t bkt_index, i;\n\n\tsig = t->f_hash(key, t->key_size, t->seed);\n\tbkt_index = sig & t->bucket_mask;\n\tbkt = &t->buckets[bkt_index];\n\tsig = (sig >> 16) | 1LLU;\n\n\t/* Key is present in the bucket */\n\tfor (i = 0; i < KEYS_PER_BUCKET; i++) {\n\t\tuint64_t bkt_sig = (uint64_t) bkt->sig[i];\n\t\tuint32_t bkt_key_index = bkt->key_pos[i];\n\t\tuint8_t *bkt_key = &t->key_mem[bkt_key_index <<\n\t\t\tt->key_size_shl];\n\n\t\tif ((sig == bkt_sig) &&\n\t\t\t(memcmp(key, bkt_key, t->key_size) == 0)) {\n\t\t\tuint8_t *data = &t->data_mem[bkt_key_index <<\n\t\t\t\tt->data_size_shl];\n\n\t\t\tbkt->sig[i] = 0;\n\t\t\tt->key_stack[t->key_stack_tos++] = bkt_key_index;\n\t\t\t*key_found = 1;\n\t\t\tmemcpy(entry, data, t->entry_size);\n\t\t\treturn 0;\n\t\t}\n\t}\n\n\t/* Key is not present in the bucket */\n\t*key_found = 0;\n\treturn 0;\n}\n\nstatic int rte_table_hash_lru_lookup_unoptimized(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries,\n\tint dosig)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\tuint64_t pkts_mask_out = 0;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_LRU_STATS_PKTS_IN_ADD(t, n_pkts_in);\n\n\tfor ( ; pkts_mask; ) {\n\t\tstruct bucket *bkt;\n\t\tstruct rte_mbuf *pkt;\n\t\tuint8_t *key;\n\t\tuint64_t pkt_mask, sig;\n\t\tuint32_t pkt_index, bkt_index, i;\n\n\t\tpkt_index = __builtin_ctzll(pkts_mask);\n\t\tpkt_mask = 1LLU << pkt_index;\n\t\tpkts_mask &= ~pkt_mask;\n\n\t\tpkt = pkts[pkt_index];\n\t\tkey = RTE_MBUF_METADATA_UINT8_PTR(pkt, t->key_offset);\n\t\tif (dosig)\n\t\t\tsig = (uint64_t) t->f_hash(key, t->key_size, t->seed);\n\t\telse\n\t\t\tsig = RTE_MBUF_METADATA_UINT32(pkt,\n\t\t\t\tt->signature_offset);\n\n\t\tbkt_index = sig & t->bucket_mask;\n\t\tbkt = &t->buckets[bkt_index];\n\t\tsig = (sig >> 16) | 1LLU;\n\n\t\t/* Key is present in the bucket */\n\t\tfor (i = 0; i < KEYS_PER_BUCKET; i++) {\n\t\t\tuint64_t bkt_sig = (uint64_t) bkt->sig[i];\n\t\t\tuint32_t bkt_key_index = bkt->key_pos[i];\n\t\t\tuint8_t *bkt_key = &t->key_mem[bkt_key_index <<\n\t\t\t\tt->key_size_shl];\n\n\t\t\tif ((sig == bkt_sig) && (memcmp(key, bkt_key,\n\t\t\t\tt->key_size) == 0)) {\n\t\t\t\tuint8_t *data = &t->data_mem[bkt_key_index <<\n\t\t\t\t\tt->data_size_shl];\n\n\t\t\t\tlru_update(bkt, i);\n\t\t\t\tpkts_mask_out |= pkt_mask;\n\t\t\t\tentries[pkt_index] = (void *) data;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_LRU_STATS_PKTS_LOOKUP_MISS(t, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn 0;\n}\n\n/***\n*\n* mask = match bitmask\n* match = at least one match\n* match_many = more than one match\n* match_pos = position of first match\n*\n* ----------------------------------------\n* mask\t\t match\t match_many\t match_pos\n* ----------------------------------------\n* 0000\t\t 0\t\t 0\t\t\t 00\n* 0001\t\t 1\t\t 0\t\t\t 00\n* 0010\t\t 1\t\t 0\t\t\t 01\n* 0011\t\t 1\t\t 1\t\t\t 00\n* ----------------------------------------\n* 0100\t\t 1\t\t 0\t\t\t 10\n* 0101\t\t 1\t\t 1\t\t\t 00\n* 0110\t\t 1\t\t 1\t\t\t 01\n* 0111\t\t 1\t\t 1\t\t\t 00\n* ----------------------------------------\n* 1000\t\t 1\t\t 0\t\t\t 11\n* 1001\t\t 1\t\t 1\t\t\t 00\n* 1010\t\t 1\t\t 1\t\t\t 01\n* 1011\t\t 1\t\t 1\t\t\t 00\n* ----------------------------------------\n* 1100\t\t 1\t\t 1\t\t\t 10\n* 1101\t\t 1\t\t 1\t\t\t 00\n* 1110\t\t 1\t\t 1\t\t\t 01\n* 1111\t\t 1\t\t 1\t\t\t 00\n* ----------------------------------------\n*\n* match = 1111_1111_1111_1110\n* match_many = 1111_1110_1110_1000\n* match_pos = 0001_0010_0001_0011__0001_0010_0001_0000\n*\n* match = 0xFFFELLU\n* match_many = 0xFEE8LLU\n* match_pos = 0x12131210LLU\n*\n***/\n\n#define LUT_MATCH\t\t\t\t\t\t0xFFFELLU\n#define LUT_MATCH_MANY\t\t\t\t\t\t0xFEE8LLU\n#define LUT_MATCH_POS\t\t\t\t\t\t0x12131210LLU\n\n#define lookup_cmp_sig(mbuf_sig, bucket, match, match_many, match_pos)\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t bucket_sig[4], mask[4], mask_all;\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket_sig[0] = bucket->sig[0];\t\t\t\t\\\n\tbucket_sig[1] = bucket->sig[1];\t\t\t\t\\\n\tbucket_sig[2] = bucket->sig[2];\t\t\t\t\\\n\tbucket_sig[3] = bucket->sig[3];\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tbucket_sig[0] ^= mbuf_sig;\t\t\t\t\\\n\tbucket_sig[1] ^= mbuf_sig;\t\t\t\t\\\n\tbucket_sig[2] ^= mbuf_sig;\t\t\t\t\\\n\tbucket_sig[3] ^= mbuf_sig;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmask[0] = 0;\t\t\t\t\t\t\\\n\tmask[1] = 0;\t\t\t\t\t\t\\\n\tmask[2] = 0;\t\t\t\t\t\t\\\n\tmask[3] = 0;\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tif (bucket_sig[0] == 0)\t\t\t\t\t\\\n\t\tmask[0] = 1;\t\t\t\t\t\\\n\tif (bucket_sig[1] == 0)\t\t\t\t\t\\\n\t\tmask[1] = 2;\t\t\t\t\t\\\n\tif (bucket_sig[2] == 0)\t\t\t\t\t\\\n\t\tmask[2] = 4;\t\t\t\t\t\\\n\tif (bucket_sig[3] == 0)\t\t\t\t\t\\\n\t\tmask[3] = 8;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmask_all = (mask[0] | mask[1]) | (mask[2] | mask[3]);\t\\\n\t\t\t\t\t\t\t\t\\\n\tmatch = (LUT_MATCH >> mask_all) & 1;\t\t\t\\\n\tmatch_many = (LUT_MATCH_MANY >> mask_all) & 1;\t\t\\\n\tmatch_pos = (LUT_MATCH_POS >> (mask_all << 1)) & 3;\t\\\n}\n\n#define lookup_cmp_key(mbuf, key, match_key, f)\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t *pkt_key = RTE_MBUF_METADATA_UINT64_PTR(mbuf, f->key_offset);\\\n\tuint64_t *bkt_key = (uint64_t *) key;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tswitch (f->key_size) {\t\t\t\t\t\\\n\tcase 8:\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\\\n\t\tuint64_t xor = pkt_key[0] ^ bkt_key[0];\t\t\\\n\t\tmatch_key = 0;\t\t\t\t\t\\\n\t\tif (xor == 0)\t\t\t\t\t\\\n\t\t\tmatch_key = 1;\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\\\n\tbreak;\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tcase 16:\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\\\n\t\tuint64_t xor[2], or;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\t\txor[0] = pkt_key[0] ^ bkt_key[0];\t\t\\\n\t\txor[1] = pkt_key[1] ^ bkt_key[1];\t\t\\\n\t\tor = xor[0] | xor[1];\t\t\t\t\\\n\t\tmatch_key = 0;\t\t\t\t\t\\\n\t\tif (or == 0)\t\t\t\t\t\\\n\t\t\tmatch_key = 1;\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\\\n\tbreak;\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tcase 32:\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\\\n\t\tuint64_t xor[4], or;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\t\txor[0] = pkt_key[0] ^ bkt_key[0];\t\t\\\n\t\txor[1] = pkt_key[1] ^ bkt_key[1];\t\t\\\n\t\txor[2] = pkt_key[2] ^ bkt_key[2];\t\t\\\n\t\txor[3] = pkt_key[3] ^ bkt_key[3];\t\t\\\n\t\tor = xor[0] | xor[1] | xor[2] | xor[3];\t\t\\\n\t\tmatch_key = 0;\t\t\t\t\t\\\n\t\tif (or == 0)\t\t\t\t\t\\\n\t\t\tmatch_key = 1;\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\\\n\tbreak;\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tcase 64:\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\\\n\t\tuint64_t xor[8], or;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\t\txor[0] = pkt_key[0] ^ bkt_key[0];\t\t\\\n\t\txor[1] = pkt_key[1] ^ bkt_key[1];\t\t\\\n\t\txor[2] = pkt_key[2] ^ bkt_key[2];\t\t\\\n\t\txor[3] = pkt_key[3] ^ bkt_key[3];\t\t\\\n\t\txor[4] = pkt_key[4] ^ bkt_key[4];\t\t\\\n\t\txor[5] = pkt_key[5] ^ bkt_key[5];\t\t\\\n\t\txor[6] = pkt_key[6] ^ bkt_key[6];\t\t\\\n\t\txor[7] = pkt_key[7] ^ bkt_key[7];\t\t\\\n\t\tor = xor[0] | xor[1] | xor[2] | xor[3] |\t\\\n\t\t\txor[4] | xor[5] | xor[6] | xor[7];\t\\\n\t\tmatch_key = 0;\t\t\t\t\t\\\n\t\tif (or == 0)\t\t\t\t\t\\\n\t\t\tmatch_key = 1;\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\\\n\tbreak;\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tdefault:\t\t\t\t\t\t\\\n\t\tmatch_key = 0;\t\t\t\t\t\\\n\t\tif (memcmp(pkt_key, bkt_key, f->key_size) == 0)\t\\\n\t\t\tmatch_key = 1;\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\\\n}\n\n#define lookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index)\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt00_mask, pkt01_mask;\t\t\t\\\n\tstruct rte_mbuf *mbuf00, *mbuf01;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt00_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt00_mask = 1LLU << pkt00_index;\t\t\t\\\n\tpkts_mask &= ~pkt00_mask;\t\t\t\t\\\n\tmbuf00 = pkts[pkt00_index];\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt01_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt01_mask = 1LLU << pkt01_index;\t\t\t\\\n\tpkts_mask &= ~pkt01_mask;\t\t\t\t\\\n\tmbuf01 = pkts[pkt01_index];\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf00, 0));\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf01, 0));\t\\\n}\n\n#define lookup2_stage0_with_odd_support(t, g, pkts, pkts_mask, pkt00_index, \\\n\tpkt01_index)\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tuint64_t pkt00_mask, pkt01_mask;\t\t\t\\\n\tstruct rte_mbuf *mbuf00, *mbuf01;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt00_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tpkt00_mask = 1LLU << pkt00_index;\t\t\t\\\n\tpkts_mask &= ~pkt00_mask;\t\t\t\t\\\n\tmbuf00 = pkts[pkt00_index];\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt01_index = __builtin_ctzll(pkts_mask);\t\t\\\n\tif (pkts_mask == 0)\t\t\t\t\t\\\n\t\tpkt01_index = pkt00_index;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkt01_mask = 1LLU << pkt01_index;\t\t\t\\\n\tpkts_mask &= ~pkt01_mask;\t\t\t\t\\\n\tmbuf01 = pkts[pkt01_index];\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf00, 0));\t\\\n\trte_prefetch0(RTE_MBUF_METADATA_UINT8_PTR(mbuf01, 0));\t\\\n}\n\n#define lookup2_stage1(t, g, pkts, pkt10_index, pkt11_index)\t\\\n{\t\t\t\t\t\t\t\t\\\n\tstruct grinder *g10, *g11;\t\t\t\t\\\n\tuint64_t sig10, sig11, bkt10_index, bkt11_index;\t\\\n\tstruct rte_mbuf *mbuf10, *mbuf11;\t\t\t\\\n\tstruct bucket *bkt10, *bkt11, *buckets = t->buckets;\t\\\n\tuint64_t bucket_mask = t->bucket_mask;\t\t\t\\\n\tuint32_t signature_offset = t->signature_offset;\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf10 = pkts[pkt10_index];\t\t\t\t\\\n\tsig10 = (uint64_t) RTE_MBUF_METADATA_UINT32(mbuf10, signature_offset);\\\n\tbkt10_index = sig10 & bucket_mask;\t\t\t\\\n\tbkt10 = &buckets[bkt10_index];\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf11 = pkts[pkt11_index];\t\t\t\t\\\n\tsig11 = (uint64_t) RTE_MBUF_METADATA_UINT32(mbuf11, signature_offset);\\\n\tbkt11_index = sig11 & bucket_mask;\t\t\t\\\n\tbkt11 = &buckets[bkt11_index];\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\trte_prefetch0(bkt10);\t\t\t\t\t\\\n\trte_prefetch0(bkt11);\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tg10 = &g[pkt10_index];\t\t\t\t\t\\\n\tg10->sig = sig10;\t\t\t\t\t\\\n\tg10->bkt = bkt10;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tg11 = &g[pkt11_index];\t\t\t\t\t\\\n\tg11->sig = sig11;\t\t\t\t\t\\\n\tg11->bkt = bkt11;\t\t\t\t\t\\\n}\n\n#define lookup2_stage1_dosig(t, g, pkts, pkt10_index, pkt11_index)\\\n{\t\t\t\t\t\t\t\t\\\n\tstruct grinder *g10, *g11;\t\t\t\t\\\n\tuint64_t sig10, sig11, bkt10_index, bkt11_index;\t\\\n\tstruct rte_mbuf *mbuf10, *mbuf11;\t\t\t\\\n\tstruct bucket *bkt10, *bkt11, *buckets = t->buckets;\t\\\n\tuint8_t *key10, *key11;\t\t\t\t\t\\\n\tuint64_t bucket_mask = t->bucket_mask;\t\t\t\\\n\trte_table_hash_op_hash f_hash = t->f_hash;\t\t\\\n\tuint64_t seed = t->seed;\t\t\t\t\\\n\tuint32_t key_size = t->key_size;\t\t\t\\\n\tuint32_t key_offset = t->key_offset;\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf10 = pkts[pkt10_index];\t\t\t\t\\\n\tkey10 = RTE_MBUF_METADATA_UINT8_PTR(mbuf10, key_offset);\\\n\tsig10 = (uint64_t) f_hash(key10, key_size, seed);\t\\\n\tbkt10_index = sig10 & bucket_mask;\t\t\t\\\n\tbkt10 = &buckets[bkt10_index];\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf11 = pkts[pkt11_index];\t\t\t\t\\\n\tkey11 = RTE_MBUF_METADATA_UINT8_PTR(mbuf11, key_offset);\\\n\tsig11 = (uint64_t) f_hash(key11, key_size, seed);\t\\\n\tbkt11_index = sig11 & bucket_mask;\t\t\t\\\n\tbkt11 = &buckets[bkt11_index];\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\trte_prefetch0(bkt10);\t\t\t\t\t\\\n\trte_prefetch0(bkt11);\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tg10 = &g[pkt10_index];\t\t\t\t\t\\\n\tg10->sig = sig10;\t\t\t\t\t\\\n\tg10->bkt = bkt10;\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tg11 = &g[pkt11_index];\t\t\t\t\t\\\n\tg11->sig = sig11;\t\t\t\t\t\\\n\tg11->bkt = bkt11;\t\t\t\t\t\\\n}\n\n#define lookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many)\\\n{\t\t\t\t\t\t\t\t\\\n\tstruct grinder *g20, *g21;\t\t\t\t\\\n\tuint64_t sig20, sig21;\t\t\t\t\t\\\n\tstruct bucket *bkt20, *bkt21;\t\t\t\t\\\n\tuint8_t *key20, *key21, *key_mem = t->key_mem;\t\t\\\n\tuint64_t match20, match21, match_many20, match_many21;\t\\\n\tuint64_t match_pos20, match_pos21;\t\t\t\\\n\tuint32_t key20_index, key21_index, key_size_shl = t->key_size_shl;\\\n\t\t\t\t\t\t\t\t\\\n\tg20 = &g[pkt20_index];\t\t\t\t\t\\\n\tsig20 = g20->sig;\t\t\t\t\t\\\n\tbkt20 = g20->bkt;\t\t\t\t\t\\\n\tsig20 = (sig20 >> 16) | 1LLU;\t\t\t\t\\\n\tlookup_cmp_sig(sig20, bkt20, match20, match_many20, match_pos20);\\\n\tmatch20 <<= pkt20_index;\t\t\t\t\\\n\tmatch_many20 <<= pkt20_index;\t\t\t\t\\\n\tkey20_index = bkt20->key_pos[match_pos20];\t\t\\\n\tkey20 = &key_mem[key20_index << key_size_shl];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tg21 = &g[pkt21_index];\t\t\t\t\t\\\n\tsig21 = g21->sig;\t\t\t\t\t\\\n\tbkt21 = g21->bkt;\t\t\t\t\t\\\n\tsig21 = (sig21 >> 16) | 1LLU;\t\t\t\t\\\n\tlookup_cmp_sig(sig21, bkt21, match21, match_many21, match_pos21);\\\n\tmatch21 <<= pkt21_index;\t\t\t\t\\\n\tmatch_many21 <<= pkt21_index;\t\t\t\t\\\n\tkey21_index = bkt21->key_pos[match_pos21];\t\t\\\n\tkey21 = &key_mem[key21_index << key_size_shl];\t\t\\\n\t\t\t\t\t\t\t\t\\\n\trte_prefetch0(key20);\t\t\t\t\t\\\n\trte_prefetch0(key21);\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tpkts_mask_match_many |= match_many20 | match_many21;\t\\\n\t\t\t\t\t\t\t\t\\\n\tg20->match = match20;\t\t\t\t\t\\\n\tg20->match_pos = match_pos20;\t\t\t\t\\\n\tg20->key_index = key20_index;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tg21->match = match21;\t\t\t\t\t\\\n\tg21->match_pos = match_pos21;\t\t\t\t\\\n\tg21->key_index = key21_index;\t\t\t\t\\\n}\n\n#define lookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out, \\\n\tentries)\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\\\n\tstruct grinder *g30, *g31;\t\t\t\t\\\n\tstruct rte_mbuf *mbuf30, *mbuf31;\t\t\t\\\n\tstruct bucket *bkt30, *bkt31;\t\t\t\t\\\n\tuint8_t *key30, *key31, *key_mem = t->key_mem;\t\t\\\n\tuint8_t *data30, *data31, *data_mem = t->data_mem;\t\\\n\tuint64_t match30, match31, match_pos30, match_pos31;\t\\\n\tuint64_t match_key30, match_key31, match_keys;\t\t\\\n\tuint32_t key30_index, key31_index;\t\t\t\\\n\tuint32_t key_size_shl = t->key_size_shl;\t\t\\\n\tuint32_t data_size_shl = t->data_size_shl;\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf30 = pkts[pkt30_index];\t\t\t\t\\\n\tg30 = &g[pkt30_index];\t\t\t\t\t\\\n\tbkt30 = g30->bkt;\t\t\t\t\t\\\n\tmatch30 = g30->match;\t\t\t\t\t\\\n\tmatch_pos30 = g30->match_pos;\t\t\t\t\\\n\tkey30_index = g30->key_index;\t\t\t\t\\\n\tkey30 = &key_mem[key30_index << key_size_shl];\t\t\\\n\tlookup_cmp_key(mbuf30, key30, match_key30, t);\t\t\\\n\tmatch_key30 <<= pkt30_index;\t\t\t\t\\\n\tmatch_key30 &= match30;\t\t\t\t\t\\\n\tdata30 = &data_mem[key30_index << data_size_shl];\t\\\n\tentries[pkt30_index] = data30;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmbuf31 = pkts[pkt31_index];\t\t\t\t\\\n\tg31 = &g[pkt31_index];\t\t\t\t\t\\\n\tbkt31 = g31->bkt;\t\t\t\t\t\\\n\tmatch31 = g31->match;\t\t\t\t\t\\\n\tmatch_pos31 = g31->match_pos;\t\t\t\t\\\n\tkey31_index = g31->key_index;\t\t\t\t\\\n\tkey31 = &key_mem[key31_index << key_size_shl];\t\t\\\n\tlookup_cmp_key(mbuf31, key31, match_key31, t);\t\t\\\n\tmatch_key31 <<= pkt31_index;\t\t\t\t\\\n\tmatch_key31 &= match31;\t\t\t\t\t\\\n\tdata31 = &data_mem[key31_index << data_size_shl];\t\\\n\tentries[pkt31_index] = data31;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\trte_prefetch0(data30);\t\t\t\t\t\\\n\trte_prefetch0(data31);\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tmatch_keys = match_key30 | match_key31;\t\t\t\\\n\tpkts_mask_out |= match_keys;\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tif (match_key30 == 0)\t\t\t\t\t\\\n\t\tmatch_pos30 = 4;\t\t\t\t\\\n\tlru_update(bkt30, match_pos30);\t\t\t\t\\\n\t\t\t\t\t\t\t\t\\\n\tif (match_key31 == 0)\t\t\t\t\t\\\n\t\tmatch_pos31 = 4;\t\t\t\t\\\n\tlru_update(bkt31, match_pos31);\t\t\t\t\\\n}\n\n/***\n* The lookup function implements a 4-stage pipeline, with each stage processing\n* two different packets. The purpose of pipelined implementation is to hide the\n* latency of prefetching the data structures and loosen the data dependency\n* between instructions.\n*\n* p00 _______ p10 _______ p20 _______ p30 _______\n* ----->| |----->| |----->| |----->| |----->\n* | 0 | | 1 | | 2 | | 3 |\n* ----->|_______|----->|_______|----->|_______|----->|_______|----->\n* p01 p11 p21 p31\n*\n* The naming convention is:\n*\t pXY = packet Y of stage X, X = 0 .. 3, Y = 0 .. 1\n*\n***/\nstatic int rte_table_hash_lru_lookup(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\tstruct grinder *g = t->grinders;\n\tuint64_t pkt00_index, pkt01_index, pkt10_index, pkt11_index;\n\tuint64_t pkt20_index, pkt21_index, pkt30_index, pkt31_index;\n\tuint64_t pkts_mask_out = 0, pkts_mask_match_many = 0;\n\tint status = 0;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_LRU_STATS_PKTS_IN_ADD(t, n_pkts_in);\n\n\t/* Cannot run the pipeline with less than 7 packets */\n\tif (__builtin_popcountll(pkts_mask) < 7)\n\t\treturn rte_table_hash_lru_lookup_unoptimized(table, pkts,\n\t\t\tpkts_mask, lookup_hit_mask, entries, 0);\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index);\n\n\t/* Pipeline feed */\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(t, g, pkts, pkt10_index, pkt11_index);\n\n\t/* Pipeline feed */\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(t, g, pkts, pkt10_index, pkt11_index);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many);\n\n\t/*\n\t* Pipeline run\n\t*\n\t*/\n\tfor ( ; pkts_mask; ) {\n\t\t/* Pipeline feed */\n\t\tpkt30_index = pkt20_index;\n\t\tpkt31_index = pkt21_index;\n\t\tpkt20_index = pkt10_index;\n\t\tpkt21_index = pkt11_index;\n\t\tpkt10_index = pkt00_index;\n\t\tpkt11_index = pkt01_index;\n\n\t\t/* Pipeline stage 0 */\n\t\tlookup2_stage0_with_odd_support(t, g, pkts, pkts_mask,\n\t\t\tpkt00_index, pkt01_index);\n\n\t\t/* Pipeline stage 1 */\n\t\tlookup2_stage1(t, g, pkts, pkt10_index, pkt11_index);\n\n\t\t/* Pipeline stage 2 */\n\t\tlookup2_stage2(t, g, pkt20_index, pkt21_index,\n\t\t\tpkts_mask_match_many);\n\n\t\t/* Pipeline stage 3 */\n\t\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index,\n\t\t\tpkts_mask_out, entries);\n\t}\n\n\t/* Pipeline feed */\n\tpkt30_index = pkt20_index;\n\tpkt31_index = pkt21_index;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1(t, g, pkts, pkt10_index, pkt11_index);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many);\n\n\t/* Pipeline stage 3 */\n\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out,\n\t\tentries);\n\n\t/* Pipeline feed */\n\tpkt30_index = pkt20_index;\n\tpkt31_index = pkt21_index;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many);\n\n\t/* Pipeline stage 3 */\n\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out,\n\t\tentries);\n\n\t/* Pipeline feed */\n\tpkt30_index = pkt20_index;\n\tpkt31_index = pkt21_index;\n\n\t/* Pipeline stage 3 */\n\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out,\n\t\tentries);\n\n\t/* Slow path */\n\tpkts_mask_match_many &= ~pkts_mask_out;\n\tif (pkts_mask_match_many) {\n\t\tuint64_t pkts_mask_out_slow = 0;\n\n\t\tstatus = rte_table_hash_lru_lookup_unoptimized(table, pkts,\n\t\t\tpkts_mask_match_many, &pkts_mask_out_slow, entries, 0);\n\t\tpkts_mask_out |= pkts_mask_out_slow;\n\t}\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_LRU_STATS_PKTS_LOOKUP_MISS(t, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn status;\n}\n\nstatic int rte_table_hash_lru_lookup_dosig(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\tstruct grinder *g = t->grinders;\n\tuint64_t pkt00_index, pkt01_index, pkt10_index, pkt11_index;\n\tuint64_t pkt20_index, pkt21_index, pkt30_index, pkt31_index;\n\tuint64_t pkts_mask_out = 0, pkts_mask_match_many = 0;\n\tint status = 0;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_HASH_LRU_STATS_PKTS_IN_ADD(t, n_pkts_in);\n\n\t/* Cannot run the pipeline with less than 7 packets */\n\tif (__builtin_popcountll(pkts_mask) < 7)\n\t\treturn rte_table_hash_lru_lookup_unoptimized(table, pkts,\n\t\t\tpkts_mask, lookup_hit_mask, entries, 1);\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index);\n\n\t/* Pipeline feed */\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1_dosig(t, g, pkts, pkt10_index, pkt11_index);\n\n\t/* Pipeline feed */\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 0 */\n\tlookup2_stage0(t, g, pkts, pkts_mask, pkt00_index, pkt01_index);\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1_dosig(t, g, pkts, pkt10_index, pkt11_index);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many);\n\n\t/*\n\t* Pipeline run\n\t*\n\t*/\n\tfor ( ; pkts_mask; ) {\n\t\t/* Pipeline feed */\n\t\tpkt30_index = pkt20_index;\n\t\tpkt31_index = pkt21_index;\n\t\tpkt20_index = pkt10_index;\n\t\tpkt21_index = pkt11_index;\n\t\tpkt10_index = pkt00_index;\n\t\tpkt11_index = pkt01_index;\n\n\t\t/* Pipeline stage 0 */\n\t\tlookup2_stage0_with_odd_support(t, g, pkts, pkts_mask,\n\t\t\tpkt00_index, pkt01_index);\n\n\t\t/* Pipeline stage 1 */\n\t\tlookup2_stage1_dosig(t, g, pkts, pkt10_index, pkt11_index);\n\n\t\t/* Pipeline stage 2 */\n\t\tlookup2_stage2(t, g, pkt20_index, pkt21_index,\n\t\t\tpkts_mask_match_many);\n\n\t\t/* Pipeline stage 3 */\n\t\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index,\n\t\t\tpkts_mask_out, entries);\n\t}\n\n\t/* Pipeline feed */\n\tpkt30_index = pkt20_index;\n\tpkt31_index = pkt21_index;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\tpkt10_index = pkt00_index;\n\tpkt11_index = pkt01_index;\n\n\t/* Pipeline stage 1 */\n\tlookup2_stage1_dosig(t, g, pkts, pkt10_index, pkt11_index);\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many);\n\n\t/* Pipeline stage 3 */\n\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out,\n\t\tentries);\n\n\t/* Pipeline feed */\n\tpkt30_index = pkt20_index;\n\tpkt31_index = pkt21_index;\n\tpkt20_index = pkt10_index;\n\tpkt21_index = pkt11_index;\n\n\t/* Pipeline stage 2 */\n\tlookup2_stage2(t, g, pkt20_index, pkt21_index, pkts_mask_match_many);\n\n\t/* Pipeline stage 3 */\n\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out,\n\t\tentries);\n\n\t/* Pipeline feed */\n\tpkt30_index = pkt20_index;\n\tpkt31_index = pkt21_index;\n\n\t/* Pipeline stage 3 */\n\tlookup2_stage3(t, g, pkts, pkt30_index, pkt31_index, pkts_mask_out,\n\t\tentries);\n\n\t/* Slow path */\n\tpkts_mask_match_many &= ~pkts_mask_out;\n\tif (pkts_mask_match_many) {\n\t\tuint64_t pkts_mask_out_slow = 0;\n\n\t\tstatus = rte_table_hash_lru_lookup_unoptimized(table, pkts,\n\t\t\tpkts_mask_match_many, &pkts_mask_out_slow, entries, 1);\n\t\tpkts_mask_out |= pkts_mask_out_slow;\n\t}\n\n\t*lookup_hit_mask = pkts_mask_out;\n\tRTE_TABLE_HASH_LRU_STATS_PKTS_LOOKUP_MISS(t, n_pkts_in - __builtin_popcountll(pkts_mask_out));\n\treturn status;\n}\n\nstatic int\nrte_table_hash_lru_stats_read(void *table, struct rte_table_stats *stats, int clear)\n{\n\tstruct rte_table_hash *t = (struct rte_table_hash *) table;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &t->stats, sizeof(t->stats));\n\n\tif (clear)\n\t\tmemset(&t->stats, 0, sizeof(t->stats));\n\n\treturn 0;\n}\n\nstruct rte_table_ops rte_table_hash_lru_ops = {\n\t.f_create = rte_table_hash_lru_create,\n\t.f_free = rte_table_hash_lru_free,\n\t.f_add = rte_table_hash_lru_entry_add,\n\t.f_delete = rte_table_hash_lru_entry_delete,\n\t.f_lookup = rte_table_hash_lru_lookup,\n\t.f_stats = rte_table_hash_lru_stats_read,\n};\n\nstruct rte_table_ops rte_table_hash_lru_dosig_ops = {\n\t.f_create = rte_table_hash_lru_create,\n\t.f_free = rte_table_hash_lru_free,\n\t.f_add = rte_table_hash_lru_entry_add,\n\t.f_delete = rte_table_hash_lru_entry_delete,\n\t.f_lookup = rte_table_hash_lru_lookup_dosig,\n\t.f_stats = rte_table_hash_lru_stats_read,\n};\n" }, { "path": "lib/librte_table/rte_table_lpm.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_table_lpm.h\"\n\n#define RTE_TABLE_LPM_MAX_NEXT_HOPS 256\n\n#ifdef RTE_TABLE_STATS_COLLECT\n\n#define RTE_TABLE_LPM_STATS_PKTS_IN_ADD(table, val) \\\n\ttable->stats.n_pkts_in += val\n#define RTE_TABLE_LPM_STATS_PKTS_LOOKUP_MISS(table, val) \\\n\ttable->stats.n_pkts_lookup_miss += val\n\n#else\n\n#define RTE_TABLE_LPM_STATS_PKTS_IN_ADD(table, val)\n#define RTE_TABLE_LPM_STATS_PKTS_LOOKUP_MISS(table, val)\n\n#endif\n\nstruct rte_table_lpm {\n\tstruct rte_table_stats stats;\n\n\t/* Input parameters */\n\tuint32_t entry_size;\n\tuint32_t entry_unique_size;\n\tuint32_t n_rules;\n\tuint32_t offset;\n\n\t/* Handle to low-level LPM table */\n\tstruct rte_lpm *lpm;\n\n\t/* Next Hop Table (NHT) */\n\tuint32_t nht_users[RTE_TABLE_LPM_MAX_NEXT_HOPS];\n\tuint8_t nht[0] __rte_cache_aligned;\n};\n\nstatic void *\nrte_table_lpm_create(void *params, int socket_id, uint32_t entry_size)\n{\n\tstruct rte_table_lpm_params *p = (struct rte_table_lpm_params *) params;\n\tstruct rte_table_lpm *lpm;\n\tuint32_t total_size, nht_size;\n\n\t/* Check input parameters */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: NULL input parameters\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tif (p->n_rules == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Invalid n_rules\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tif (p->entry_unique_size == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Invalid entry_unique_size\\n\",\n\t\t\t__func__);\n\t\treturn NULL;\n\t}\n\tif (p->entry_unique_size > entry_size) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Invalid entry_unique_size\\n\",\n\t\t\t__func__);\n\t\treturn NULL;\n\t}\n\n\tentry_size = RTE_ALIGN(entry_size, sizeof(uint64_t));\n\n\t/* Memory allocation */\n\tnht_size = RTE_TABLE_LPM_MAX_NEXT_HOPS * entry_size;\n\ttotal_size = sizeof(struct rte_table_lpm) + nht_size;\n\tlpm = rte_zmalloc_socket(\"TABLE\", total_size, RTE_CACHE_LINE_SIZE,\n\t\tsocket_id);\n\tif (lpm == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot allocate %u bytes for LPM table\\n\",\n\t\t\t__func__, total_size);\n\t\treturn NULL;\n\t}\n\n\t/* LPM low-level table creation */\n\tlpm->lpm = rte_lpm_create(\"LPM\", socket_id, p->n_rules, 0);\n\tif (lpm->lpm == NULL) {\n\t\trte_free(lpm);\n\t\tRTE_LOG(ERR, TABLE, \"Unable to create low-level LPM table\\n\");\n\t\treturn NULL;\n\t}\n\n\t/* Memory initialization */\n\tlpm->entry_size = entry_size;\n\tlpm->entry_unique_size = p->entry_unique_size;\n\tlpm->n_rules = p->n_rules;\n\tlpm->offset = p->offset;\n\n\treturn lpm;\n}\n\nstatic int\nrte_table_lpm_free(void *table)\n{\n\tstruct rte_table_lpm *lpm = (struct rte_table_lpm *) table;\n\n\t/* Check input parameters */\n\tif (lpm == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Free previously allocated resources */\n\trte_lpm_free(lpm->lpm);\n\trte_free(lpm);\n\n\treturn 0;\n}\n\nstatic int\nnht_find_free(struct rte_table_lpm *lpm, uint32_t *pos)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < RTE_TABLE_LPM_MAX_NEXT_HOPS; i++) {\n\t\tif (lpm->nht_users[i] == 0) {\n\t\t\t*pos = i;\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\nnht_find_existing(struct rte_table_lpm *lpm, void *entry, uint32_t *pos)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < RTE_TABLE_LPM_MAX_NEXT_HOPS; i++) {\n\t\tuint8_t *nht_entry = &lpm->nht[i * lpm->entry_size];\n\n\t\tif ((lpm->nht_users[i] > 0) && (memcmp(nht_entry, entry,\n\t\t\tlpm->entry_unique_size) == 0)) {\n\t\t\t*pos = i;\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_table_lpm_entry_add(\n\tvoid *table,\n\tvoid *key,\n\tvoid *entry,\n\tint *key_found,\n\tvoid **entry_ptr)\n{\n\tstruct rte_table_lpm *lpm = (struct rte_table_lpm *) table;\n\tstruct rte_table_lpm_key *ip_prefix = (struct rte_table_lpm_key *) key;\n\tuint32_t nht_pos, nht_pos0_valid;\n\tint status;\n\tuint8_t nht_pos0 = 0;\n\n\t/* Check input parameters */\n\tif (lpm == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (ip_prefix == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: ip_prefix parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\tif (entry == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: entry parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif ((ip_prefix->depth == 0) || (ip_prefix->depth > 32)) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: invalid depth (%d)\\n\",\n\t\t\t__func__, ip_prefix->depth);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Check if rule is already present in the table */\n\tstatus = rte_lpm_is_rule_present(lpm->lpm, ip_prefix->ip,\n\t\tip_prefix->depth, &nht_pos0);\n\tnht_pos0_valid = status > 0;\n\n\t/* Find existing or free NHT entry */\n\tif (nht_find_existing(lpm, entry, &nht_pos) == 0) {\n\t\tuint8_t *nht_entry;\n\n\t\tif (nht_find_free(lpm, &nht_pos) == 0) {\n\t\t\tRTE_LOG(ERR, TABLE, \"%s: NHT full\\n\", __func__);\n\t\t\treturn -1;\n\t\t}\n\n\t\tnht_entry = &lpm->nht[nht_pos * lpm->entry_size];\n\t\tmemcpy(nht_entry, entry, lpm->entry_size);\n\t}\n\n\t/* Add rule to low level LPM table */\n\tif (rte_lpm_add(lpm->lpm, ip_prefix->ip, ip_prefix->depth,\n\t\t(uint8_t) nht_pos) < 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: LPM rule add failed\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\t/* Commit NHT changes */\n\tlpm->nht_users[nht_pos]++;\n\tlpm->nht_users[nht_pos0] -= nht_pos0_valid;\n\n\t*key_found = nht_pos0_valid;\n\t*entry_ptr = (void *) &lpm->nht[nht_pos * lpm->entry_size];\n\treturn 0;\n}\n\nstatic int\nrte_table_lpm_entry_delete(\n\tvoid *table,\n\tvoid *key,\n\tint *key_found,\n\tvoid *entry)\n{\n\tstruct rte_table_lpm *lpm = (struct rte_table_lpm *) table;\n\tstruct rte_table_lpm_key *ip_prefix = (struct rte_table_lpm_key *) key;\n\tuint8_t nht_pos;\n\tint status;\n\n\t/* Check input parameters */\n\tif (lpm == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (ip_prefix == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: ip_prefix parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\tif ((ip_prefix->depth == 0) || (ip_prefix->depth > 32)) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: invalid depth (%d)\\n\", __func__,\n\t\t\tip_prefix->depth);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Return if rule is not present in the table */\n\tstatus = rte_lpm_is_rule_present(lpm->lpm, ip_prefix->ip,\n\t\tip_prefix->depth, &nht_pos);\n\tif (status < 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: LPM algorithmic error\\n\", __func__);\n\t\treturn -1;\n\t}\n\tif (status == 0) {\n\t\t*key_found = 0;\n\t\treturn 0;\n\t}\n\n\t/* Delete rule from the low-level LPM table */\n\tstatus = rte_lpm_delete(lpm->lpm, ip_prefix->ip, ip_prefix->depth);\n\tif (status) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: LPM rule delete failed\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\t/* Commit NHT changes */\n\tlpm->nht_users[nht_pos]--;\n\n\t*key_found = 1;\n\tif (entry)\n\t\tmemcpy(entry, &lpm->nht[nht_pos * lpm->entry_size],\n\t\t\tlpm->entry_size);\n\n\treturn 0;\n}\n\nstatic int\nrte_table_lpm_lookup(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_lpm *lpm = (struct rte_table_lpm *) table;\n\tuint64_t pkts_out_mask = 0;\n\tuint32_t i;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_LPM_STATS_PKTS_IN_ADD(lpm, n_pkts_in);\n\n\tpkts_out_mask = 0;\n\tfor (i = 0; i < (uint32_t)(RTE_PORT_IN_BURST_SIZE_MAX -\n\t\t__builtin_clzll(pkts_mask)); i++) {\n\t\tuint64_t pkt_mask = 1LLU << i;\n\n\t\tif (pkt_mask & pkts_mask) {\n\t\t\tstruct rte_mbuf *pkt = pkts[i];\n\t\t\tuint32_t ip = rte_bswap32(\n\t\t\t\tRTE_MBUF_METADATA_UINT32(pkt, lpm->offset));\n\t\t\tint status;\n\t\t\tuint8_t nht_pos;\n\n\t\t\tstatus = rte_lpm_lookup(lpm->lpm, ip, &nht_pos);\n\t\t\tif (status == 0) {\n\t\t\t\tpkts_out_mask |= pkt_mask;\n\t\t\t\tentries[i] = (void *) &lpm->nht[nht_pos *\n\t\t\t\t\tlpm->entry_size];\n\t\t\t}\n\t\t}\n\t}\n\n\t*lookup_hit_mask = pkts_out_mask;\n\tRTE_TABLE_LPM_STATS_PKTS_LOOKUP_MISS(lpm, n_pkts_in - __builtin_popcountll(pkts_out_mask));\n\treturn 0;\n}\n\nstatic int\nrte_table_lpm_stats_read(void *table, struct rte_table_stats *stats, int clear)\n{\n\tstruct rte_table_lpm *t = (struct rte_table_lpm *) table;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &t->stats, sizeof(t->stats));\n\n\tif (clear)\n\t\tmemset(&t->stats, 0, sizeof(t->stats));\n\n\treturn 0;\n}\n\nstruct rte_table_ops rte_table_lpm_ops = {\n\t.f_create = rte_table_lpm_create,\n\t.f_free = rte_table_lpm_free,\n\t.f_add = rte_table_lpm_entry_add,\n\t.f_delete = rte_table_lpm_entry_delete,\n\t.f_lookup = rte_table_lpm_lookup,\n\t.f_stats = rte_table_lpm_stats_read,\n};\n" }, { "path": "lib/librte_table/rte_table_lpm.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_TABLE_LPM_H__\n#define __INCLUDE_RTE_TABLE_LPM_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Table LPM for IPv4\n *\n * This table uses the Longest Prefix Match (LPM) algorithm to uniquely\n * associate data to lookup keys.\n *\n * Use-case: IP routing table. Routes that are added to the table associate a\n * next hop to an IP prefix. The IP prefix is specified as IP address and depth\n * and cover for a multitude of lookup keys (i.e. destination IP addresses)\n * that all share the same data (i.e. next hop). The next hop information\n * typically contains the output interface ID, the IP address of the next hop\n * station (which is part of the same IP network the output interface is\n * connected to) and other flags and counters.\n *\n * The LPM primitive only allows associating an 8-bit number (next hop ID) to\n * an IP prefix, while a routing table can potentially contain thousands of\n * routes or even more. This means that the same next hop ID (and next hop\n * information) has to be shared by multiple routes, which makes sense, as\n * multiple remote networks could be reached through the same next hop.\n * Therefore, when a route is added or updated, the LPM table has to check\n * whether the same next hop is already in use before using a new next hop ID\n * for this route.\n *\n * The comparison between different next hops is done for the first\n * “entry_unique_size” bytes of the next hop information (configurable\n * parameter), which have to uniquely identify the next hop, therefore the user\n * has to carefully manage the format of the LPM table entry (i.e. the next\n * hop information) so that any next hop data that changes value during\n * run-time (e.g. counters) is placed outside of this area.\n *\n ***/\n\n#include \n\n#include \"rte_table.h\"\n\n/** LPM table parameters */\nstruct rte_table_lpm_params {\n\t/** Maximum number of LPM rules (i.e. IP routes) */\n\tuint32_t n_rules;\n\n\t/** Number of bytes at the start of the table entry that uniquely\n\tidentify the entry. Cannot be bigger than table entry size. */\n\tuint32_t entry_unique_size;\n\n\t/** Byte offset within input packet meta-data where lookup key (i.e.\n\tthe destination IP address) is located. */\n\tuint32_t offset;\n};\n\n/** LPM table rule (i.e. route), specified as IP prefix. While the key used by\nthe lookup operation is the destination IP address (read from the input packet\nmeta-data), the entry add and entry delete operations work with LPM rules, with\neach rule covering for a multitude of lookup keys (destination IP addresses)\nthat share the same data (next hop). */\nstruct rte_table_lpm_key {\n\t/** IP address */\n\tuint32_t ip;\n\n\t/** IP address depth. The most significant \"depth\" bits of the IP\n\taddress specify the network part of the IP address, while the rest of\n\tthe bits specify the host part of the address and are ignored for the\n\tpurpose of route specification. */\n\tuint8_t depth;\n};\n\n/** LPM table operations */\nextern struct rte_table_ops rte_table_lpm_ops;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_table/rte_table_lpm_ipv6.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_table_lpm_ipv6.h\"\n\n#define RTE_TABLE_LPM_MAX_NEXT_HOPS 256\n\n#ifdef RTE_TABLE_STATS_COLLECT\n\n#define RTE_TABLE_LPM_IPV6_STATS_PKTS_IN_ADD(table, val) \\\n\ttable->stats.n_pkts_in += val\n#define RTE_TABLE_LPM_IPV6_STATS_PKTS_LOOKUP_MISS(table, val) \\\n\ttable->stats.n_pkts_lookup_miss += val\n\n#else\n\n#define RTE_TABLE_LPM_IPV6_STATS_PKTS_IN_ADD(table, val)\n#define RTE_TABLE_LPM_IPV6_STATS_PKTS_LOOKUP_MISS(table, val)\n\n#endif\n\nstruct rte_table_lpm_ipv6 {\n\tstruct rte_table_stats stats;\n\n\t/* Input parameters */\n\tuint32_t entry_size;\n\tuint32_t entry_unique_size;\n\tuint32_t n_rules;\n\tuint32_t offset;\n\n\t/* Handle to low-level LPM table */\n\tstruct rte_lpm6 *lpm;\n\n\t/* Next Hop Table (NHT) */\n\tuint32_t nht_users[RTE_TABLE_LPM_MAX_NEXT_HOPS];\n\tuint8_t nht[0] __rte_cache_aligned;\n};\n\nstatic void *\nrte_table_lpm_ipv6_create(void *params, int socket_id, uint32_t entry_size)\n{\n\tstruct rte_table_lpm_ipv6_params *p =\n\t\t(struct rte_table_lpm_ipv6_params *) params;\n\tstruct rte_table_lpm_ipv6 *lpm;\n\tstruct rte_lpm6_config lpm6_config;\n\tuint32_t total_size, nht_size;\n\n\t/* Check input parameters */\n\tif (p == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: NULL input parameters\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tif (p->n_rules == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Invalid n_rules\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tif (p->number_tbl8s == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Invalid n_rules\\n\", __func__);\n\t\treturn NULL;\n\t}\n\tif (p->entry_unique_size == 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Invalid entry_unique_size\\n\",\n\t\t\t__func__);\n\t\treturn NULL;\n\t}\n\tif (p->entry_unique_size > entry_size) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: Invalid entry_unique_size\\n\",\n\t\t\t__func__);\n\t\treturn NULL;\n\t}\n\n\tentry_size = RTE_ALIGN(entry_size, sizeof(uint64_t));\n\n\t/* Memory allocation */\n\tnht_size = RTE_TABLE_LPM_MAX_NEXT_HOPS * entry_size;\n\ttotal_size = sizeof(struct rte_table_lpm_ipv6) + nht_size;\n\tlpm = rte_zmalloc_socket(\"TABLE\", total_size, RTE_CACHE_LINE_SIZE,\n\t\tsocket_id);\n\tif (lpm == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot allocate %u bytes for LPM IPv6 table\\n\",\n\t\t\t__func__, total_size);\n\t\treturn NULL;\n\t}\n\n\t/* LPM low-level table creation */\n\tlpm6_config.max_rules = p->n_rules;\n\tlpm6_config.number_tbl8s = p->number_tbl8s;\n\tlpm6_config.flags = 0;\n\tlpm->lpm = rte_lpm6_create(\"LPM IPv6\", socket_id, &lpm6_config);\n\tif (lpm->lpm == NULL) {\n\t\trte_free(lpm);\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"Unable to create low-level LPM IPv6 table\\n\");\n\t\treturn NULL;\n\t}\n\n\t/* Memory initialization */\n\tlpm->entry_size = entry_size;\n\tlpm->entry_unique_size = p->entry_unique_size;\n\tlpm->n_rules = p->n_rules;\n\tlpm->offset = p->offset;\n\n\treturn lpm;\n}\n\nstatic int\nrte_table_lpm_ipv6_free(void *table)\n{\n\tstruct rte_table_lpm_ipv6 *lpm = (struct rte_table_lpm_ipv6 *) table;\n\n\t/* Check input parameters */\n\tif (lpm == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Free previously allocated resources */\n\trte_lpm6_free(lpm->lpm);\n\trte_free(lpm);\n\n\treturn 0;\n}\n\nstatic int\nnht_find_free(struct rte_table_lpm_ipv6 *lpm, uint32_t *pos)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < RTE_TABLE_LPM_MAX_NEXT_HOPS; i++) {\n\t\tif (lpm->nht_users[i] == 0) {\n\t\t\t*pos = i;\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\nnht_find_existing(struct rte_table_lpm_ipv6 *lpm, void *entry, uint32_t *pos)\n{\n\tuint32_t i;\n\n\tfor (i = 0; i < RTE_TABLE_LPM_MAX_NEXT_HOPS; i++) {\n\t\tuint8_t *nht_entry = &lpm->nht[i * lpm->entry_size];\n\n\t\tif ((lpm->nht_users[i] > 0) && (memcmp(nht_entry, entry,\n\t\t\tlpm->entry_unique_size) == 0)) {\n\t\t\t*pos = i;\n\t\t\treturn 1;\n\t\t}\n\t}\n\n\treturn 0;\n}\n\nstatic int\nrte_table_lpm_ipv6_entry_add(\n\tvoid *table,\n\tvoid *key,\n\tvoid *entry,\n\tint *key_found,\n\tvoid **entry_ptr)\n{\n\tstruct rte_table_lpm_ipv6 *lpm = (struct rte_table_lpm_ipv6 *) table;\n\tstruct rte_table_lpm_ipv6_key *ip_prefix =\n\t\t(struct rte_table_lpm_ipv6_key *) key;\n\tuint32_t nht_pos, nht_pos0_valid;\n\tint status;\n\tuint8_t nht_pos0;\n\n\t/* Check input parameters */\n\tif (lpm == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (ip_prefix == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: ip_prefix parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\tif (entry == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: entry parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\n\tif ((ip_prefix->depth == 0) || (ip_prefix->depth > 128)) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: invalid depth (%d)\\n\", __func__,\n\t\t\tip_prefix->depth);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Check if rule is already present in the table */\n\tstatus = rte_lpm6_is_rule_present(lpm->lpm, ip_prefix->ip,\n\t\tip_prefix->depth, &nht_pos0);\n\tnht_pos0_valid = status > 0;\n\n\t/* Find existing or free NHT entry */\n\tif (nht_find_existing(lpm, entry, &nht_pos) == 0) {\n\t\tuint8_t *nht_entry;\n\n\t\tif (nht_find_free(lpm, &nht_pos) == 0) {\n\t\t\tRTE_LOG(ERR, TABLE, \"%s: NHT full\\n\", __func__);\n\t\t\treturn -1;\n\t\t}\n\n\t\tnht_entry = &lpm->nht[nht_pos * lpm->entry_size];\n\t\tmemcpy(nht_entry, entry, lpm->entry_size);\n\t}\n\n\t/* Add rule to low level LPM table */\n\tif (rte_lpm6_add(lpm->lpm, ip_prefix->ip, ip_prefix->depth,\n\t\t(uint8_t) nht_pos) < 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: LPM IPv6 rule add failed\\n\", __func__);\n\t\treturn -1;\n\t}\n\n\t/* Commit NHT changes */\n\tlpm->nht_users[nht_pos]++;\n\tlpm->nht_users[nht_pos0] -= nht_pos0_valid;\n\n\t*key_found = nht_pos0_valid;\n\t*entry_ptr = (void *) &lpm->nht[nht_pos * lpm->entry_size];\n\treturn 0;\n}\n\nstatic int\nrte_table_lpm_ipv6_entry_delete(\n\tvoid *table,\n\tvoid *key,\n\tint *key_found,\n\tvoid *entry)\n{\n\tstruct rte_table_lpm_ipv6 *lpm = (struct rte_table_lpm_ipv6 *) table;\n\tstruct rte_table_lpm_ipv6_key *ip_prefix =\n\t\t(struct rte_table_lpm_ipv6_key *) key;\n\tuint8_t nht_pos;\n\tint status;\n\n\t/* Check input parameters */\n\tif (lpm == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: table parameter is NULL\\n\", __func__);\n\t\treturn -EINVAL;\n\t}\n\tif (ip_prefix == NULL) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: ip_prefix parameter is NULL\\n\",\n\t\t\t__func__);\n\t\treturn -EINVAL;\n\t}\n\tif ((ip_prefix->depth == 0) || (ip_prefix->depth > 128)) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: invalid depth (%d)\\n\", __func__,\n\t\t\tip_prefix->depth);\n\t\treturn -EINVAL;\n\t}\n\n\t/* Return if rule is not present in the table */\n\tstatus = rte_lpm6_is_rule_present(lpm->lpm, ip_prefix->ip,\n\t\tip_prefix->depth, &nht_pos);\n\tif (status < 0) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: LPM IPv6 algorithmic error\\n\",\n\t\t\t__func__);\n\t\treturn -1;\n\t}\n\tif (status == 0) {\n\t\t*key_found = 0;\n\t\treturn 0;\n\t}\n\n\t/* Delete rule from the low-level LPM table */\n\tstatus = rte_lpm6_delete(lpm->lpm, ip_prefix->ip, ip_prefix->depth);\n\tif (status) {\n\t\tRTE_LOG(ERR, TABLE, \"%s: LPM IPv6 rule delete failed\\n\",\n\t\t\t__func__);\n\t\treturn -1;\n\t}\n\n\t/* Commit NHT changes */\n\tlpm->nht_users[nht_pos]--;\n\n\t*key_found = 1;\n\tif (entry)\n\t\tmemcpy(entry, &lpm->nht[nht_pos * lpm->entry_size],\n\t\t\tlpm->entry_size);\n\n\treturn 0;\n}\n\nstatic int\nrte_table_lpm_ipv6_lookup(\n\tvoid *table,\n\tstruct rte_mbuf **pkts,\n\tuint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\tvoid **entries)\n{\n\tstruct rte_table_lpm_ipv6 *lpm = (struct rte_table_lpm_ipv6 *) table;\n\tuint64_t pkts_out_mask = 0;\n\tuint32_t i;\n\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\tRTE_TABLE_LPM_IPV6_STATS_PKTS_IN_ADD(lpm, n_pkts_in);\n\n\tpkts_out_mask = 0;\n\tfor (i = 0; i < (uint32_t)(RTE_PORT_IN_BURST_SIZE_MAX -\n\t\t__builtin_clzll(pkts_mask)); i++) {\n\t\tuint64_t pkt_mask = 1LLU << i;\n\n\t\tif (pkt_mask & pkts_mask) {\n\t\t\tstruct rte_mbuf *pkt = pkts[i];\n\t\t\tuint8_t *ip = RTE_MBUF_METADATA_UINT8_PTR(pkt,\n\t\t\t\tlpm->offset);\n\t\t\tint status;\n\t\t\tuint8_t nht_pos;\n\n\t\t\tstatus = rte_lpm6_lookup(lpm->lpm, ip, &nht_pos);\n\t\t\tif (status == 0) {\n\t\t\t\tpkts_out_mask |= pkt_mask;\n\t\t\t\tentries[i] = (void *) &lpm->nht[nht_pos *\n\t\t\t\t\tlpm->entry_size];\n\t\t\t}\n\t\t}\n\t}\n\n\t*lookup_hit_mask = pkts_out_mask;\n\tRTE_TABLE_LPM_IPV6_STATS_PKTS_LOOKUP_MISS(lpm, n_pkts_in - __builtin_popcountll(pkts_out_mask));\n\treturn 0;\n}\n\nstatic int\nrte_table_lpm_ipv6_stats_read(void *table, struct rte_table_stats *stats, int clear)\n{\n\tstruct rte_table_lpm_ipv6 *t = (struct rte_table_lpm_ipv6 *) table;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &t->stats, sizeof(t->stats));\n\n\tif (clear)\n\t\tmemset(&t->stats, 0, sizeof(t->stats));\n\n\treturn 0;\n}\n\nstruct rte_table_ops rte_table_lpm_ipv6_ops = {\n\t.f_create = rte_table_lpm_ipv6_create,\n\t.f_free = rte_table_lpm_ipv6_free,\n\t.f_add = rte_table_lpm_ipv6_entry_add,\n\t.f_delete = rte_table_lpm_ipv6_entry_delete,\n\t.f_lookup = rte_table_lpm_ipv6_lookup,\n\t.f_stats = rte_table_lpm_ipv6_stats_read,\n};\n" }, { "path": "lib/librte_table/rte_table_lpm_ipv6.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_TABLE_LPM_IPV6_H__\n#define __INCLUDE_RTE_TABLE_LPM_IPV6_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Table LPM for IPv6\n *\n * This table uses the Longest Prefix Match (LPM) algorithm to uniquely\n * associate data to lookup keys.\n *\n * Use-case: IP routing table. Routes that are added to the table associate a\n * next hop to an IP prefix. The IP prefix is specified as IP address and depth\n * and cover for a multitude of lookup keys (i.e. destination IP addresses)\n * that all share the same data (i.e. next hop). The next hop information\n * typically contains the output interface ID, the IP address of the next hop\n * station (which is part of the same IP network the output interface is\n * connected to) and other flags and counters.\n *\n * The LPM primitive only allows associating an 8-bit number (next hop ID) to\n * an IP prefix, while a routing table can potentially contain thousands of\n * routes or even more. This means that the same next hop ID (and next hop\n * information) has to be shared by multiple routes, which makes sense, as\n * multiple remote networks could be reached through the same next hop.\n * Therefore, when a route is added or updated, the LPM table has to check\n * whether the same next hop is already in use before using a new next hop ID\n * for this route.\n *\n * The comparison between different next hops is done for the first\n * “entry_unique_size” bytes of the next hop information (configurable\n * parameter), which have to uniquely identify the next hop, therefore the user\n * has to carefully manage the format of the LPM table entry (i.e. the next\n * hop information) so that any next hop data that changes value during\n * run-time (e.g. counters) is placed outside of this area.\n *\n ***/\n\n#include \n\n#include \"rte_table.h\"\n\n#define RTE_LPM_IPV6_ADDR_SIZE 16\n\n/** LPM table parameters */\nstruct rte_table_lpm_ipv6_params {\n\t/** Maximum number of LPM rules (i.e. IP routes) */\n\tuint32_t n_rules;\n\n\tuint32_t number_tbl8s;\n\n\t/** Number of bytes at the start of the table entry that uniquely\n\tidentify the entry. Cannot be bigger than table entry size. */\n\tuint32_t entry_unique_size;\n\n\t/** Byte offset within input packet meta-data where lookup key (i.e.\n\tthe destination IP address) is located. */\n\tuint32_t offset;\n};\n\n/** LPM table rule (i.e. route), specified as IP prefix. While the key used by\nthe lookup operation is the destination IP address (read from the input packet\nmeta-data), the entry add and entry delete operations work with LPM rules, with\neach rule covering for a multitude of lookup keys (destination IP addresses)\nthat share the same data (next hop). */\nstruct rte_table_lpm_ipv6_key {\n\t/** IP address */\n\tuint8_t ip[RTE_LPM_IPV6_ADDR_SIZE];\n\n\t/** IP address depth. The most significant \"depth\" bits of the IP\n\taddress specify the network part of the IP address, while the rest of\n\tthe bits specify the host part of the address and are ignored for the\n\tpurpose of route specification. */\n\tuint8_t depth;\n};\n\n/** LPM table operations */\nextern struct rte_table_ops rte_table_lpm_ipv6_ops;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_table/rte_table_stub.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n\n#include \n#include \n\n#include \"rte_table_stub.h\"\n\n#ifdef RTE_TABLE_STATS_COLLECT\n\n#define RTE_TABLE_LPM_STATS_PKTS_IN_ADD(table, val) \\\n\ttable->stats.n_pkts_in += val\n#define RTE_TABLE_LPM_STATS_PKTS_LOOKUP_MISS(table, val) \\\n\ttable->stats.n_pkts_lookup_miss += val\n\n#else\n\n#define RTE_TABLE_LPM_STATS_PKTS_IN_ADD(table, val)\n#define RTE_TABLE_LPM_STATS_PKTS_LOOKUP_MISS(table, val)\n\n#endif\n\nstruct rte_table_stub {\n\tstruct rte_table_stats stats;\n};\n\nstatic void *\nrte_table_stub_create(__rte_unused void *params,\n\t\t__rte_unused int socket_id,\n\t\t__rte_unused uint32_t entry_size)\n{\n\tstruct rte_table_stub *stub;\n\tuint32_t size;\n\n\tsize = sizeof(struct rte_table_stub);\n\tstub = rte_zmalloc_socket(\"TABLE\", size, RTE_CACHE_LINE_SIZE,\n\t\tsocket_id);\n\tif (stub == NULL) {\n\t\tRTE_LOG(ERR, TABLE,\n\t\t\t\"%s: Cannot allocate %u bytes for stub table\\n\",\n\t\t\t__func__, size);\n\t\treturn NULL;\n\t}\n\n\treturn stub;\n}\n\nstatic int\nrte_table_stub_lookup(\n\t__rte_unused void *table,\n\t__rte_unused struct rte_mbuf **pkts,\n\t__rte_unused uint64_t pkts_mask,\n\tuint64_t *lookup_hit_mask,\n\t__rte_unused void **entries)\n{\n\t__rte_unused struct rte_table_stub *stub = (struct rte_table_stub *) table;\n\t__rte_unused uint32_t n_pkts_in = __builtin_popcountll(pkts_mask);\n\n\tRTE_TABLE_LPM_STATS_PKTS_IN_ADD(stub, n_pkts_in);\n\t*lookup_hit_mask = 0;\n\tRTE_TABLE_LPM_STATS_PKTS_LOOKUP_MISS(stub, n_pkts_in);\n\n\treturn 0;\n}\n\nstatic int\nrte_table_stub_stats_read(void *table, struct rte_table_stats *stats, int clear)\n{\n\tstruct rte_table_stub *t = (struct rte_table_stub *) table;\n\n\tif (stats != NULL)\n\t\tmemcpy(stats, &t->stats, sizeof(t->stats));\n\n\tif (clear)\n\t\tmemset(&t->stats, 0, sizeof(t->stats));\n\n\treturn 0;\n}\n\nstruct rte_table_ops rte_table_stub_ops = {\n\t.f_create = rte_table_stub_create,\n\t.f_free = NULL,\n\t.f_add = NULL,\n\t.f_delete = NULL,\n\t.f_lookup = rte_table_stub_lookup,\n\t.f_stats = rte_table_stub_stats_read,\n};\n" }, { "path": "lib/librte_table/rte_table_stub.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef __INCLUDE_RTE_TABLE_STUB_H__\n#define __INCLUDE_RTE_TABLE_STUB_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * @file\n * RTE Table Stub\n *\n * The stub table lookup operation produces lookup miss for all input packets.\n *\n ***/\n\n#include \n\n#include \"rte_table.h\"\n\n/** Stub table parameters: NONE */\n\n/** Stub table operations */\nextern struct rte_table_ops rte_table_stub_ops;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "lib/librte_timer/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_timer.a\n\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3\n\nEXPORT_MAP := rte_timer_version.map\n\nLIBABIVER := 1\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_TIMER) := rte_timer.c\n\n# install this header file\nSYMLINK-$(CONFIG_RTE_LIBRTE_TIMER)-include := rte_timer.h\n\n# this lib needs eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_TIMER) += lib/librte_eal\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_timer/rte_timer.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"rte_timer.h\"\n\nLIST_HEAD(rte_timer_list, rte_timer);\n\nstruct priv_timer {\n\tstruct rte_timer pending_head; /**< dummy timer instance to head up list */\n\trte_spinlock_t list_lock; /**< lock to protect list access */\n\n\t/** per-core variable that true if a timer was updated on this\n\t * core since last reset of the variable */\n\tint updated;\n\n\t/** track the current depth of the skiplist */\n\tunsigned curr_skiplist_depth;\n\n\tunsigned prev_lcore; /**< used for lcore round robin */\n\n#ifdef RTE_LIBRTE_TIMER_DEBUG\n\t/** per-lcore statistics */\n\tstruct rte_timer_debug_stats stats;\n#endif\n} __rte_cache_aligned;\n\n/** per-lcore private info for timers */\nstatic struct priv_timer priv_timer[RTE_MAX_LCORE];\n\n/* when debug is enabled, store some statistics */\n#ifdef RTE_LIBRTE_TIMER_DEBUG\n#define __TIMER_STAT_ADD(name, n) do {\t\t\t\t\t\\\n\t\tunsigned __lcore_id = rte_lcore_id();\t\t\t\\\n\t\tif (__lcore_id < RTE_MAX_LCORE)\t\t\t\t\\\n\t\t\tpriv_timer[__lcore_id].stats.name += (n);\t\\\n\t} while(0)\n#else\n#define __TIMER_STAT_ADD(name, n) do {} while(0)\n#endif\n\n/* Init the timer library. */\nvoid\nrte_timer_subsystem_init(void)\n{\n\tunsigned lcore_id;\n\n\t/* since priv_timer is static, it's zeroed by default, so only init some\n\t * fields.\n\t */\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id ++) {\n\t\trte_spinlock_init(&priv_timer[lcore_id].list_lock);\n\t\tpriv_timer[lcore_id].prev_lcore = lcore_id;\n\t}\n}\n\n/* Initialize the timer handle tim for use */\nvoid\nrte_timer_init(struct rte_timer *tim)\n{\n\tunion rte_timer_status status;\n\n\tstatus.state = RTE_TIMER_STOP;\n\tstatus.owner = RTE_TIMER_NO_OWNER;\n\ttim->status.u32 = status.u32;\n}\n\n/*\n * if timer is pending or stopped (or running on the same core than\n * us), mark timer as configuring, and on success return the previous\n * status of the timer\n */\nstatic int\ntimer_set_config_state(struct rte_timer *tim,\n\t\t union rte_timer_status *ret_prev_status)\n{\n\tunion rte_timer_status prev_status, status;\n\tint success = 0;\n\tunsigned lcore_id;\n\n\tlcore_id = rte_lcore_id();\n\n\t/* wait that the timer is in correct status before update,\n\t * and mark it as being configured */\n\twhile (success == 0) {\n\t\tprev_status.u32 = tim->status.u32;\n\n\t\t/* timer is running on another core, exit */\n\t\tif (prev_status.state == RTE_TIMER_RUNNING &&\n\t\t prev_status.owner != (uint16_t)lcore_id)\n\t\t\treturn -1;\n\n\t\t/* timer is being configured on another core */\n\t\tif (prev_status.state == RTE_TIMER_CONFIG)\n\t\t\treturn -1;\n\n\t\t/* here, we know that timer is stopped or pending,\n\t\t * mark it atomically as being configured */\n\t\tstatus.state = RTE_TIMER_CONFIG;\n\t\tstatus.owner = (int16_t)lcore_id;\n\t\tsuccess = rte_atomic32_cmpset(&tim->status.u32,\n\t\t\t\t\t prev_status.u32,\n\t\t\t\t\t status.u32);\n\t}\n\n\tret_prev_status->u32 = prev_status.u32;\n\treturn 0;\n}\n\n/*\n * if timer is pending, mark timer as running\n */\nstatic int\ntimer_set_running_state(struct rte_timer *tim)\n{\n\tunion rte_timer_status prev_status, status;\n\tunsigned lcore_id = rte_lcore_id();\n\tint success = 0;\n\n\t/* wait that the timer is in correct status before update,\n\t * and mark it as running */\n\twhile (success == 0) {\n\t\tprev_status.u32 = tim->status.u32;\n\n\t\t/* timer is not pending anymore */\n\t\tif (prev_status.state != RTE_TIMER_PENDING)\n\t\t\treturn -1;\n\n\t\t/* here, we know that timer is stopped or pending,\n\t\t * mark it atomically as beeing configured */\n\t\tstatus.state = RTE_TIMER_RUNNING;\n\t\tstatus.owner = (int16_t)lcore_id;\n\t\tsuccess = rte_atomic32_cmpset(&tim->status.u32,\n\t\t\t\t\t prev_status.u32,\n\t\t\t\t\t status.u32);\n\t}\n\n\treturn 0;\n}\n\n/*\n * Return a skiplist level for a new entry.\n * This probabalistically gives a level with p=1/4 that an entry at level n\n * will also appear at level n+1.\n */\nstatic uint32_t\ntimer_get_skiplist_level(unsigned curr_depth)\n{\n#ifdef RTE_LIBRTE_TIMER_DEBUG\n\tstatic uint32_t i, count = 0;\n\tstatic uint32_t levels[MAX_SKIPLIST_DEPTH] = {0};\n#endif\n\n\t/* probability value is 1/4, i.e. all at level 0, 1 in 4 is at level 1,\n\t * 1 in 16 at level 2, 1 in 64 at level 3, etc. Calculated using lowest\n\t * bit position of a (pseudo)random number.\n\t */\n\tuint32_t rand = rte_rand() & (UINT32_MAX - 1);\n\tuint32_t level = rand == 0 ? MAX_SKIPLIST_DEPTH : (rte_bsf32(rand)-1) / 2;\n\n\t/* limit the levels used to one above our current level, so we don't,\n\t * for instance, have a level 0 and a level 7 without anything between\n\t */\n\tif (level > curr_depth)\n\t\tlevel = curr_depth;\n\tif (level >= MAX_SKIPLIST_DEPTH)\n\t\tlevel = MAX_SKIPLIST_DEPTH-1;\n#ifdef RTE_LIBRTE_TIMER_DEBUG\n\tcount ++;\n\tlevels[level]++;\n\tif (count % 10000 == 0)\n\t\tfor (i = 0; i < MAX_SKIPLIST_DEPTH; i++)\n\t\t\tprintf(\"Level %u: %u\\n\", (unsigned)i, (unsigned)levels[i]);\n#endif\n\treturn level;\n}\n\n/*\n * For a given time value, get the entries at each level which\n * are <= that time value.\n */\nstatic void\ntimer_get_prev_entries(uint64_t time_val, unsigned tim_lcore,\n\t\tstruct rte_timer **prev)\n{\n\tunsigned lvl = priv_timer[tim_lcore].curr_skiplist_depth;\n\tprev[lvl] = &priv_timer[tim_lcore].pending_head;\n\twhile(lvl != 0) {\n\t\tlvl--;\n\t\tprev[lvl] = prev[lvl+1];\n\t\twhile (prev[lvl]->sl_next[lvl] &&\n\t\t\t\tprev[lvl]->sl_next[lvl]->expire <= time_val)\n\t\t\tprev[lvl] = prev[lvl]->sl_next[lvl];\n\t}\n}\n\n/*\n * Given a timer node in the skiplist, find the previous entries for it at\n * all skiplist levels.\n */\nstatic void\ntimer_get_prev_entries_for_node(struct rte_timer *tim, unsigned tim_lcore,\n\t\tstruct rte_timer **prev)\n{\n\tint i;\n\t/* to get a specific entry in the list, look for just lower than the time\n\t * values, and then increment on each level individually if necessary\n\t */\n\ttimer_get_prev_entries(tim->expire - 1, tim_lcore, prev);\n\tfor (i = priv_timer[tim_lcore].curr_skiplist_depth - 1; i >= 0; i--) {\n\t\twhile (prev[i]->sl_next[i] != NULL &&\n\t\t\t\tprev[i]->sl_next[i] != tim &&\n\t\t\t\tprev[i]->sl_next[i]->expire <= tim->expire)\n\t\t\tprev[i] = prev[i]->sl_next[i];\n\t}\n}\n\n/*\n * add in list, lock if needed\n * timer must be in config state\n * timer must not be in a list\n */\nstatic void\ntimer_add(struct rte_timer *tim, unsigned tim_lcore, int local_is_locked)\n{\n\tunsigned lcore_id = rte_lcore_id();\n\tunsigned lvl;\n\tstruct rte_timer *prev[MAX_SKIPLIST_DEPTH+1];\n\n\t/* if timer needs to be scheduled on another core, we need to\n\t * lock the list; if it is on local core, we need to lock if\n\t * we are not called from rte_timer_manage() */\n\tif (tim_lcore != lcore_id || !local_is_locked)\n\t\trte_spinlock_lock(&priv_timer[tim_lcore].list_lock);\n\n\t/* find where exactly this element goes in the list of elements\n\t * for each depth. */\n\ttimer_get_prev_entries(tim->expire, tim_lcore, prev);\n\n\t/* now assign it a new level and add at that level */\n\tconst unsigned tim_level = timer_get_skiplist_level(\n\t\t\tpriv_timer[tim_lcore].curr_skiplist_depth);\n\tif (tim_level == priv_timer[tim_lcore].curr_skiplist_depth)\n\t\tpriv_timer[tim_lcore].curr_skiplist_depth++;\n\n\tlvl = tim_level;\n\twhile (lvl > 0) {\n\t\ttim->sl_next[lvl] = prev[lvl]->sl_next[lvl];\n\t\tprev[lvl]->sl_next[lvl] = tim;\n\t\tlvl--;\n\t}\n\ttim->sl_next[0] = prev[0]->sl_next[0];\n\tprev[0]->sl_next[0] = tim;\n\n\t/* save the lowest list entry into the expire field of the dummy hdr\n\t * NOTE: this is not atomic on 32-bit*/\n\tpriv_timer[tim_lcore].pending_head.expire = priv_timer[tim_lcore].\\\n\t\t\tpending_head.sl_next[0]->expire;\n\n\tif (tim_lcore != lcore_id || !local_is_locked)\n\t\trte_spinlock_unlock(&priv_timer[tim_lcore].list_lock);\n}\n\n/*\n * del from list, lock if needed\n * timer must be in config state\n * timer must be in a list\n */\nstatic void\ntimer_del(struct rte_timer *tim, union rte_timer_status prev_status,\n\t\tint local_is_locked)\n{\n\tunsigned lcore_id = rte_lcore_id();\n\tunsigned prev_owner = prev_status.owner;\n\tint i;\n\tstruct rte_timer *prev[MAX_SKIPLIST_DEPTH+1];\n\n\t/* if timer needs is pending another core, we need to lock the\n\t * list; if it is on local core, we need to lock if we are not\n\t * called from rte_timer_manage() */\n\tif (prev_owner != lcore_id || !local_is_locked)\n\t\trte_spinlock_lock(&priv_timer[prev_owner].list_lock);\n\n\t/* save the lowest list entry into the expire field of the dummy hdr.\n\t * NOTE: this is not atomic on 32-bit */\n\tif (tim == priv_timer[prev_owner].pending_head.sl_next[0])\n\t\tpriv_timer[prev_owner].pending_head.expire =\n\t\t\t\t((tim->sl_next[0] == NULL) ? 0 : tim->sl_next[0]->expire);\n\n\t/* adjust pointers from previous entries to point past this */\n\ttimer_get_prev_entries_for_node(tim, prev_owner, prev);\n\tfor (i = priv_timer[prev_owner].curr_skiplist_depth - 1; i >= 0; i--) {\n\t\tif (prev[i]->sl_next[i] == tim)\n\t\t\tprev[i]->sl_next[i] = tim->sl_next[i];\n\t}\n\n\t/* in case we deleted last entry at a level, adjust down max level */\n\tfor (i = priv_timer[prev_owner].curr_skiplist_depth - 1; i >= 0; i--)\n\t\tif (priv_timer[prev_owner].pending_head.sl_next[i] == NULL)\n\t\t\tpriv_timer[prev_owner].curr_skiplist_depth --;\n\t\telse\n\t\t\tbreak;\n\n\tif (prev_owner != lcore_id || !local_is_locked)\n\t\trte_spinlock_unlock(&priv_timer[prev_owner].list_lock);\n}\n\n/* Reset and start the timer associated with the timer handle (private func) */\nstatic int\n__rte_timer_reset(struct rte_timer *tim, uint64_t expire,\n\t\t uint64_t period, unsigned tim_lcore,\n\t\t rte_timer_cb_t fct, void *arg,\n\t\t int local_is_locked)\n{\n\tunion rte_timer_status prev_status, status;\n\tint ret;\n\tunsigned lcore_id = rte_lcore_id();\n\n\t/* round robin for tim_lcore */\n\tif (tim_lcore == (unsigned)LCORE_ID_ANY) {\n\t\tif (lcore_id < RTE_MAX_LCORE) {\n\t\t\t/* EAL thread with valid lcore_id */\n\t\t\ttim_lcore = rte_get_next_lcore(\n\t\t\t\tpriv_timer[lcore_id].prev_lcore,\n\t\t\t\t0, 1);\n\t\t\tpriv_timer[lcore_id].prev_lcore = tim_lcore;\n\t\t} else\n\t\t\t/* non-EAL thread do not run rte_timer_manage(),\n\t\t\t * so schedule the timer on the first enabled lcore. */\n\t\t\ttim_lcore = rte_get_next_lcore(LCORE_ID_ANY, 0, 1);\n\t}\n\n\t/* wait that the timer is in correct status before update,\n\t * and mark it as being configured */\n\tret = timer_set_config_state(tim, &prev_status);\n\tif (ret < 0)\n\t\treturn -1;\n\n\t__TIMER_STAT_ADD(reset, 1);\n\tif (prev_status.state == RTE_TIMER_RUNNING &&\n\t lcore_id < RTE_MAX_LCORE) {\n\t\tpriv_timer[lcore_id].updated = 1;\n\t}\n\n\t/* remove it from list */\n\tif (prev_status.state == RTE_TIMER_PENDING) {\n\t\ttimer_del(tim, prev_status, local_is_locked);\n\t\t__TIMER_STAT_ADD(pending, -1);\n\t}\n\n\ttim->period = period;\n\ttim->expire = expire;\n\ttim->f = fct;\n\ttim->arg = arg;\n\n\t__TIMER_STAT_ADD(pending, 1);\n\ttimer_add(tim, tim_lcore, local_is_locked);\n\n\t/* update state: as we are in CONFIG state, only us can modify\n\t * the state so we don't need to use cmpset() here */\n\trte_wmb();\n\tstatus.state = RTE_TIMER_PENDING;\n\tstatus.owner = (int16_t)tim_lcore;\n\ttim->status.u32 = status.u32;\n\n\treturn 0;\n}\n\n/* Reset and start the timer associated with the timer handle tim */\nint\nrte_timer_reset(struct rte_timer *tim, uint64_t ticks,\n\t\tenum rte_timer_type type, unsigned tim_lcore,\n\t\trte_timer_cb_t fct, void *arg)\n{\n\tuint64_t cur_time = rte_get_timer_cycles();\n\tuint64_t period;\n\n\tif (unlikely((tim_lcore != (unsigned)LCORE_ID_ANY) &&\n\t\t\t!rte_lcore_is_enabled(tim_lcore)))\n\t\treturn -1;\n\n\tif (type == PERIODICAL)\n\t\tperiod = ticks;\n\telse\n\t\tperiod = 0;\n\n\treturn __rte_timer_reset(tim, cur_time + ticks, period, tim_lcore,\n\t\t\t fct, arg, 0);\n}\n\n/* loop until rte_timer_reset() succeed */\nvoid\nrte_timer_reset_sync(struct rte_timer *tim, uint64_t ticks,\n\t\t enum rte_timer_type type, unsigned tim_lcore,\n\t\t rte_timer_cb_t fct, void *arg)\n{\n\twhile (rte_timer_reset(tim, ticks, type, tim_lcore,\n\t\t\t fct, arg) != 0)\n\t\trte_pause();\n}\n\n/* Stop the timer associated with the timer handle tim */\nint\nrte_timer_stop(struct rte_timer *tim)\n{\n\tunion rte_timer_status prev_status, status;\n\tunsigned lcore_id = rte_lcore_id();\n\tint ret;\n\n\t/* wait that the timer is in correct status before update,\n\t * and mark it as being configured */\n\tret = timer_set_config_state(tim, &prev_status);\n\tif (ret < 0)\n\t\treturn -1;\n\n\t__TIMER_STAT_ADD(stop, 1);\n\tif (prev_status.state == RTE_TIMER_RUNNING &&\n\t lcore_id < RTE_MAX_LCORE) {\n\t\tpriv_timer[lcore_id].updated = 1;\n\t}\n\n\t/* remove it from list */\n\tif (prev_status.state == RTE_TIMER_PENDING) {\n\t\ttimer_del(tim, prev_status, 0);\n\t\t__TIMER_STAT_ADD(pending, -1);\n\t}\n\n\t/* mark timer as stopped */\n\trte_wmb();\n\tstatus.state = RTE_TIMER_STOP;\n\tstatus.owner = RTE_TIMER_NO_OWNER;\n\ttim->status.u32 = status.u32;\n\n\treturn 0;\n}\n\n/* loop until rte_timer_stop() succeed */\nvoid\nrte_timer_stop_sync(struct rte_timer *tim)\n{\n\twhile (rte_timer_stop(tim) != 0)\n\t\trte_pause();\n}\n\n/* Test the PENDING status of the timer handle tim */\nint\nrte_timer_pending(struct rte_timer *tim)\n{\n\treturn tim->status.state == RTE_TIMER_PENDING;\n}\n\n/* must be called periodically, run all timer that expired */\nvoid rte_timer_manage(void)\n{\n\tunion rte_timer_status status;\n\tstruct rte_timer *tim, *next_tim;\n\tstruct rte_timer *run_first_tim, **pprev;\n\tunsigned lcore_id = rte_lcore_id();\n\tstruct rte_timer *prev[MAX_SKIPLIST_DEPTH + 1];\n\tuint64_t cur_time;\n\tint i, ret;\n\n\t/* timer manager only runs on EAL thread with valid lcore_id */\n\tassert(lcore_id < RTE_MAX_LCORE);\n\n\t__TIMER_STAT_ADD(manage, 1);\n\t/* optimize for the case where per-cpu list is empty */\n\tif (priv_timer[lcore_id].pending_head.sl_next[0] == NULL)\n\t\treturn;\n\tcur_time = rte_get_timer_cycles();\n\n#ifdef RTE_ARCH_X86_64\n\t/* on 64-bit the value cached in the pending_head.expired will be\n\t * updated atomically, so we can consult that for a quick check here\n\t * outside the lock */\n\tif (likely(priv_timer[lcore_id].pending_head.expire > cur_time))\n\t\treturn;\n#endif\n\n\t/* browse ordered list, add expired timers in 'expired' list */\n\trte_spinlock_lock(&priv_timer[lcore_id].list_lock);\n\n\t/* if nothing to do just unlock and return */\n\tif (priv_timer[lcore_id].pending_head.sl_next[0] == NULL ||\n\t priv_timer[lcore_id].pending_head.sl_next[0]->expire > cur_time) {\n\t\trte_spinlock_unlock(&priv_timer[lcore_id].list_lock);\n\t\treturn;\n\t}\n\n\t/* save start of list of expired timers */\n\ttim = priv_timer[lcore_id].pending_head.sl_next[0];\n\n\t/* break the existing list at current time point */\n\ttimer_get_prev_entries(cur_time, lcore_id, prev);\n\tfor (i = priv_timer[lcore_id].curr_skiplist_depth -1; i >= 0; i--) {\n\t\tpriv_timer[lcore_id].pending_head.sl_next[i] =\n\t\t prev[i]->sl_next[i];\n\t\tif (prev[i]->sl_next[i] == NULL)\n\t\t\tpriv_timer[lcore_id].curr_skiplist_depth--;\n\t\tprev[i] ->sl_next[i] = NULL;\n\t}\n\n\t/* transition run-list from PENDING to RUNNING */\n\trun_first_tim = tim;\n\tpprev = &run_first_tim;\n\n\tfor ( ; tim != NULL; tim = next_tim) {\n\t\tnext_tim = tim->sl_next[0];\n\n\t\tret = timer_set_running_state(tim);\n\t\tif (likely(ret == 0)) {\n\t\t\tpprev = &tim->sl_next[0];\n\t\t} else {\n\t\t\t/* another core is trying to re-config this one,\n\t\t\t * remove it from local expired list and put it\n\t\t\t * back on the priv_timer[] skip list */\n\t\t\t*pprev = next_tim;\n\t\t\ttimer_add(tim, lcore_id, 1);\n\t\t}\n\t}\n\n\t/* update the next to expire timer value */\n\tpriv_timer[lcore_id].pending_head.expire =\n\t (priv_timer[lcore_id].pending_head.sl_next[0] == NULL) ? 0 :\n\t\tpriv_timer[lcore_id].pending_head.sl_next[0]->expire;\n\n\trte_spinlock_unlock(&priv_timer[lcore_id].list_lock);\n\n\t/* now scan expired list and call callbacks */\n\tfor (tim = run_first_tim; tim != NULL; tim = next_tim) {\n\t\tnext_tim = tim->sl_next[0];\n\t\tpriv_timer[lcore_id].updated = 0;\n\n\t\t/* execute callback function with list unlocked */\n\t\ttim->f(tim, tim->arg);\n\n\t\t__TIMER_STAT_ADD(pending, -1);\n\t\t/* the timer was stopped or reloaded by the callback\n\t\t * function, we have nothing to do here */\n\t\tif (priv_timer[lcore_id].updated == 1)\n\t\t\tcontinue;\n\n\t\tif (tim->period == 0) {\n\t\t\t/* remove from done list and mark timer as stopped */\n\t\t\tstatus.state = RTE_TIMER_STOP;\n\t\t\tstatus.owner = RTE_TIMER_NO_OWNER;\n\t\t\trte_wmb();\n\t\t\ttim->status.u32 = status.u32;\n\t\t}\n\t\telse {\n\t\t\t/* keep it in list and mark timer as pending */\n\t\t\trte_spinlock_lock(&priv_timer[lcore_id].list_lock);\n\t\t\tstatus.state = RTE_TIMER_PENDING;\n\t\t\t__TIMER_STAT_ADD(pending, 1);\n\t\t\tstatus.owner = (int16_t)lcore_id;\n\t\t\trte_wmb();\n\t\t\ttim->status.u32 = status.u32;\n\t\t\t__rte_timer_reset(tim, cur_time + tim->period,\n\t\t\t\ttim->period, lcore_id, tim->f, tim->arg, 1);\n\t\t\trte_spinlock_unlock(&priv_timer[lcore_id].list_lock);\n\t\t}\n\t}\n}\n\n/* dump statistics about timers */\nvoid rte_timer_dump_stats(FILE *f)\n{\n#ifdef RTE_LIBRTE_TIMER_DEBUG\n\tstruct rte_timer_debug_stats sum;\n\tunsigned lcore_id;\n\n\tmemset(&sum, 0, sizeof(sum));\n\tfor (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {\n\t\tsum.reset += priv_timer[lcore_id].stats.reset;\n\t\tsum.stop += priv_timer[lcore_id].stats.stop;\n\t\tsum.manage += priv_timer[lcore_id].stats.manage;\n\t\tsum.pending += priv_timer[lcore_id].stats.pending;\n\t}\n\tfprintf(f, \"Timer statistics:\\n\");\n\tfprintf(f, \" reset = %\"PRIu64\"\\n\", sum.reset);\n\tfprintf(f, \" stop = %\"PRIu64\"\\n\", sum.stop);\n\tfprintf(f, \" manage = %\"PRIu64\"\\n\", sum.manage);\n\tfprintf(f, \" pending = %\"PRIu64\"\\n\", sum.pending);\n#else\n\tfprintf(f, \"No timer statistics, RTE_LIBRTE_TIMER_DEBUG is disabled\\n\");\n#endif\n}\n" }, { "path": "lib/librte_timer/rte_timer.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _RTE_TIMER_H_\n#define _RTE_TIMER_H_\n\n/**\n * @file\n RTE Timer\n *\n * This library provides a timer service to RTE Data Plane execution\n * units that allows the execution of callback functions asynchronously.\n *\n * - Timers can be periodic or single (one-shot).\n * - The timers can be loaded from one core and executed on another. This has\n * to be specified in the call to rte_timer_reset().\n * - High precision is possible. NOTE: this depends on the call frequency to\n * rte_timer_manage() that check the timer expiration for the local core.\n * - If not used in an application, for improved performance, it can be\n * disabled at compilation time by not calling the rte_timer_manage()\n * to improve performance.\n *\n * The timer library uses the rte_get_hpet_cycles() function that\n * uses the HPET, when available, to provide a reliable time reference. [HPET\n * routines are provided by EAL, which falls back to using the chip TSC (time-\n * stamp counter) as fallback when HPET is not available]\n *\n * This library provides an interface to add, delete and restart a\n * timer. The API is based on the BSD callout(9) API with a few\n * differences.\n *\n * See the RTE architecture documentation for more information about the\n * design of this library.\n */\n\n#include \n#include \n#include \n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#define RTE_TIMER_STOP 0 /**< State: timer is stopped. */\n#define RTE_TIMER_PENDING 1 /**< State: timer is scheduled. */\n#define RTE_TIMER_RUNNING 2 /**< State: timer function is running. */\n#define RTE_TIMER_CONFIG 3 /**< State: timer is being configured. */\n\n#define RTE_TIMER_NO_OWNER -2 /**< Timer has no owner. */\n\n/**\n * Timer type: Periodic or single (one-shot).\n */\nenum rte_timer_type {\n\tSINGLE,\n\tPERIODICAL\n};\n\n/**\n * Timer status: A union of the state (stopped, pending, running,\n * config) and an owner (the id of the lcore that owns the timer).\n */\nunion rte_timer_status {\n\tstruct {\n\t\tuint16_t state; /**< Stop, pending, running, config. */\n\t\tint16_t owner; /**< The lcore that owns the timer. */\n\t};\n\tuint32_t u32; /**< To atomic-set status + owner. */\n};\n\n#ifdef RTE_LIBRTE_TIMER_DEBUG\n/**\n * A structure that stores the timer statistics (per-lcore).\n */\nstruct rte_timer_debug_stats {\n\tuint64_t reset; /**< Number of success calls to rte_timer_reset(). */\n\tuint64_t stop; /**< Number of success calls to rte_timer_stop(). */\n\tuint64_t manage; /**< Number of calls to rte_timer_manage(). */\n\tuint64_t pending; /**< Number of pending/running timers. */\n};\n#endif\n\nstruct rte_timer;\n\n/**\n * Callback function type for timer expiry.\n */\ntypedef void (*rte_timer_cb_t)(struct rte_timer *, void *);\n\n#define MAX_SKIPLIST_DEPTH 10\n\n/**\n * A structure describing a timer in RTE.\n */\nstruct rte_timer\n{\n\tuint64_t expire; /**< Time when timer expire. */\n\tstruct rte_timer *sl_next[MAX_SKIPLIST_DEPTH];\n\tvolatile union rte_timer_status status; /**< Status of timer. */\n\tuint64_t period; /**< Period of timer (0 if not periodic). */\n\trte_timer_cb_t f; /**< Callback function. */\n\tvoid *arg; /**< Argument to callback function. */\n};\n\n\n#ifdef __cplusplus\n/**\n * A C++ static initializer for a timer structure.\n */\n#define RTE_TIMER_INITIALIZER { \\\n\t0, \\\n\t{NULL}, \\\n\t{{RTE_TIMER_STOP, RTE_TIMER_NO_OWNER}}, \\\n\t0, \\\n\tNULL, \\\n\tNULL, \\\n\t}\n#else\n/**\n * A static initializer for a timer structure.\n */\n#define RTE_TIMER_INITIALIZER { \\\n\t\t.status = {{ \\\n\t\t\t.state = RTE_TIMER_STOP, \\\n\t\t\t.owner = RTE_TIMER_NO_OWNER, \\\n\t\t}}, \\\n\t}\n#endif\n\n/**\n * Initialize the timer library.\n *\n * Initializes internal variables (list, locks and so on) for the RTE\n * timer library.\n */\nvoid rte_timer_subsystem_init(void);\n\n/**\n * Initialize a timer handle.\n *\n * The rte_timer_init() function initializes the timer handle *tim*\n * for use. No operations can be performed on a timer before it is\n * initialized.\n *\n * @param tim\n * The timer to initialize.\n */\nvoid rte_timer_init(struct rte_timer *tim);\n\n/**\n * Reset and start the timer associated with the timer handle.\n *\n * The rte_timer_reset() function resets and starts the timer\n * associated with the timer handle *tim*. When the timer expires after\n * *ticks* HPET cycles, the function specified by *fct* will be called\n * with the argument *arg* on core *tim_lcore*.\n *\n * If the timer associated with the timer handle is already running\n * (in the RUNNING state), the function will fail. The user has to check\n * the return value of the function to see if there is a chance that the\n * timer is in the RUNNING state.\n *\n * If the timer is being configured on another core (the CONFIG state),\n * it will also fail.\n *\n * If the timer is pending or stopped, it will be rescheduled with the\n * new parameters.\n *\n * @param tim\n * The timer handle.\n * @param ticks\n * The number of cycles (see rte_get_hpet_hz()) before the callback\n * function is called.\n * @param type\n * The type can be either:\n * - PERIODICAL: The timer is automatically reloaded after execution\n * (returns to the PENDING state)\n * - SINGLE: The timer is one-shot, that is, the timer goes to a\n * STOPPED state after execution.\n * @param tim_lcore\n * The ID of the lcore where the timer callback function has to be\n * executed. If tim_lcore is LCORE_ID_ANY, the timer library will\n * launch it on a different core for each call (round-robin).\n * @param fct\n * The callback function of the timer.\n * @param arg\n * The user argument of the callback function.\n * @return\n * - 0: Success; the timer is scheduled.\n * - (-1): Timer is in the RUNNING or CONFIG state.\n */\nint rte_timer_reset(struct rte_timer *tim, uint64_t ticks,\n\t\t enum rte_timer_type type, unsigned tim_lcore,\n\t\t rte_timer_cb_t fct, void *arg);\n\n\n/**\n * Loop until rte_timer_reset() succeeds.\n *\n * Reset and start the timer associated with the timer handle. Always\n * succeed. See rte_timer_reset() for details.\n *\n * @param tim\n * The timer handle.\n * @param ticks\n * The number of cycles (see rte_get_hpet_hz()) before the callback\n * function is called.\n * @param type\n * The type can be either:\n * - PERIODICAL: The timer is automatically reloaded after execution\n * (returns to the PENDING state)\n * - SINGLE: The timer is one-shot, that is, the timer goes to a\n * STOPPED state after execution.\n * @param tim_lcore\n * The ID of the lcore where the timer callback function has to be\n * executed. If tim_lcore is LCORE_ID_ANY, the timer library will\n * launch it on a different core for each call (round-robin).\n * @param fct\n * The callback function of the timer.\n * @param arg\n * The user argument of the callback function.\n */\nvoid\nrte_timer_reset_sync(struct rte_timer *tim, uint64_t ticks,\n\t\t enum rte_timer_type type, unsigned tim_lcore,\n\t\t rte_timer_cb_t fct, void *arg);\n\n/**\n * Stop a timer.\n *\n * The rte_timer_stop() function stops the timer associated with the\n * timer handle *tim*. It may fail if the timer is currently running or\n * being configured.\n *\n * If the timer is pending or stopped (for instance, already expired),\n * the function will succeed. The timer handle tim must have been\n * initialized using rte_timer_init(), otherwise, undefined behavior\n * will occur.\n *\n * This function can be called safely from a timer callback. If it\n * succeeds, the timer is not referenced anymore by the timer library\n * and the timer structure can be freed (even in the callback\n * function).\n *\n * @param tim\n * The timer handle.\n * @return\n * - 0: Success; the timer is stopped.\n * - (-1): The timer is in the RUNNING or CONFIG state.\n */\nint rte_timer_stop(struct rte_timer *tim);\n\n\n/**\n * Loop until rte_timer_stop() succeeds.\n *\n * After a call to this function, the timer identified by *tim* is\n * stopped. See rte_timer_stop() for details.\n *\n * @param tim\n * The timer handle.\n */\nvoid rte_timer_stop_sync(struct rte_timer *tim);\n\n/**\n * Test if a timer is pending.\n *\n * The rte_timer_pending() function tests the PENDING status\n * of the timer handle *tim*. A PENDING timer is one that has been\n * scheduled and whose function has not yet been called.\n *\n * @param tim\n * The timer handle.\n * @return\n * - 0: The timer is not pending.\n * - 1: The timer is pending.\n */\nint rte_timer_pending(struct rte_timer *tim);\n\n/**\n * Manage the timer list and execute callback functions.\n *\n * This function must be called periodically from EAL lcores\n * main_loop(). It browses the list of pending timers and runs all\n * timers that are expired.\n *\n * The precision of the timer depends on the call frequency of this\n * function. However, the more often the function is called, the more\n * CPU resources it will use.\n */\nvoid rte_timer_manage(void);\n\n/**\n * Dump statistics about timers.\n *\n * @param f\n * A pointer to a file for output\n */\nvoid rte_timer_dump_stats(FILE *f);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* _RTE_TIMER_H_ */\n" }, { "path": "lib/librte_vhost/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/rte.vars.mk\n\n# library name\nLIB = librte_vhost.a\n\nEXPORT_MAP := rte_vhost_version.map\n\nLIBABIVER := 1\n\nCFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3 -D_FILE_OFFSET_BITS=64\nifeq ($(CONFIG_RTE_LIBRTE_VHOST_USER),y)\nCFLAGS += -I vhost_user\nelse\nCFLAGS += -I vhost_cuse -lfuse\nLDFLAGS += -lfuse\nendif\n\nifeq ($(CONFIG_RTE_LIBRTE_VHOST_NUMA),y)\nLDFLAGS += -lnuma\nendif\n\n# all source are stored in SRCS-y\nSRCS-$(CONFIG_RTE_LIBRTE_VHOST) := virtio-net.c vhost_rxtx.c\nifeq ($(CONFIG_RTE_LIBRTE_VHOST_USER),y)\nSRCS-$(CONFIG_RTE_LIBRTE_VHOST) += vhost_user/vhost-net-user.c vhost_user/virtio-net-user.c vhost_user/fd_man.c\nelse\nSRCS-$(CONFIG_RTE_LIBRTE_VHOST) += vhost_cuse/vhost-net-cdev.c vhost_cuse/virtio-net-cdev.c vhost_cuse/eventfd_copy.c\nendif\n\n# install includes\nSYMLINK-$(CONFIG_RTE_LIBRTE_VHOST)-include += rte_virtio_net.h\n\n# dependencies\nDEPDIRS-$(CONFIG_RTE_LIBRTE_VHOST) += lib/librte_eal\nDEPDIRS-$(CONFIG_RTE_LIBRTE_VHOST) += lib/librte_ether\nDEPDIRS-$(CONFIG_RTE_LIBRTE_VHOST) += lib/librte_mbuf\n\ninclude $(RTE_SDK)/mk/rte.lib.mk\n" }, { "path": "lib/librte_vhost/eventfd_link/Makefile", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nobj-m += eventfd_link.o\n\n\nall:\n\tmake -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules\n\nclean:\n\tmake -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean\n" }, { "path": "lib/librte_vhost/eventfd_link/eventfd_link.c", "content": "/*-\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"eventfd_link.h\"\n\n\n/*\n * get_files_struct is copied from fs/file.c\n */\nstruct files_struct *\nget_files_struct(struct task_struct *task)\n{\n\tstruct files_struct *files;\n\n\ttask_lock(task);\n\tfiles = task->files;\n\tif (files)\n\t\tatomic_inc(&files->count);\n\ttask_unlock(task);\n\n\treturn files;\n}\n\n/*\n * put_files_struct is extracted from fs/file.c\n */\nvoid\nput_files_struct(struct files_struct *files)\n{\n\tif (atomic_dec_and_test(&files->count))\n\t\tBUG();\n}\n\n\nstatic long\neventfd_link_ioctl(struct file *f, unsigned int ioctl, unsigned long arg)\n{\n\tvoid __user *argp = (void __user *) arg;\n\tstruct task_struct *task_target = NULL;\n\tstruct file *file;\n\tstruct files_struct *files;\n\tstruct fdtable *fdt;\n\tstruct eventfd_copy eventfd_copy;\n\n\tswitch (ioctl) {\n\tcase EVENTFD_COPY:\n\t\tif (copy_from_user(&eventfd_copy, argp,\n\t\t\tsizeof(struct eventfd_copy)))\n\t\t\treturn -EFAULT;\n\n\t\t/*\n\t\t * Find the task struct for the target pid\n\t\t */\n\t\ttask_target =\n\t\t\tpid_task(find_vpid(eventfd_copy.target_pid), PIDTYPE_PID);\n\t\tif (task_target == NULL) {\n\t\t\tpr_debug(\"Failed to get mem ctx for target pid\\n\");\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\tfiles = get_files_struct(current);\n\t\tif (files == NULL) {\n\t\t\tpr_debug(\"Failed to get files struct\\n\");\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\trcu_read_lock();\n\t\tfile = fcheck_files(files, eventfd_copy.source_fd);\n\t\tif (file) {\n\t\t\tif (file->f_mode & FMODE_PATH ||\n\t\t\t\t!atomic_long_inc_not_zero(&file->f_count))\n\t\t\t\tfile = NULL;\n\t\t}\n\t\trcu_read_unlock();\n\t\tput_files_struct(files);\n\n\t\tif (file == NULL) {\n\t\t\tpr_debug(\"Failed to get file from source pid\\n\");\n\t\t\treturn 0;\n\t\t}\n\n\t\t/*\n\t\t * Release the existing eventfd in the source process\n\t\t */\n\t\tspin_lock(&files->file_lock);\n\t\tfput(file);\n\t\tfilp_close(file, files);\n\t\tfdt = files_fdtable(files);\n\t\tfdt->fd[eventfd_copy.source_fd] = NULL;\n\t\tspin_unlock(&files->file_lock);\n\n\t\t/*\n\t\t * Find the file struct associated with the target fd.\n\t\t */\n\n\t\tfiles = get_files_struct(task_target);\n\t\tif (files == NULL) {\n\t\t\tpr_debug(\"Failed to get files struct\\n\");\n\t\t\treturn -EFAULT;\n\t\t}\n\n\t\trcu_read_lock();\n\t\tfile = fcheck_files(files, eventfd_copy.target_fd);\n\t\tif (file) {\n\t\t\tif (file->f_mode & FMODE_PATH ||\n\t\t\t\t!atomic_long_inc_not_zero(&file->f_count))\n\t\t\t\t\tfile = NULL;\n\t\t}\n\t\trcu_read_unlock();\n\t\tput_files_struct(files);\n\n\t\tif (file == NULL) {\n\t\t\tpr_debug(\"Failed to get file from target pid\\n\");\n\t\t\treturn 0;\n\t\t}\n\n\t\t/*\n\t\t * Install the file struct from the target process into the\n\t\t * file desciptor of the source process,\n\t\t */\n\n\t\tfd_install(eventfd_copy.source_fd, file);\n\n\t\treturn 0;\n\n\tdefault:\n\t\treturn -ENOIOCTLCMD;\n\t}\n}\n\nstatic const struct file_operations eventfd_link_fops = {\n\t.owner = THIS_MODULE,\n\t.unlocked_ioctl = eventfd_link_ioctl,\n};\n\n\nstatic struct miscdevice eventfd_link_misc = {\n\t.name = \"eventfd-link\",\n\t.fops = &eventfd_link_fops,\n};\n\nstatic int __init\neventfd_link_init(void)\n{\n\treturn misc_register(&eventfd_link_misc);\n}\n\nmodule_init(eventfd_link_init);\n\nstatic void __exit\neventfd_link_exit(void)\n{\n\tmisc_deregister(&eventfd_link_misc);\n}\n\nmodule_exit(eventfd_link_exit);\n\nMODULE_VERSION(\"0.0.1\");\nMODULE_LICENSE(\"GPL v2\");\nMODULE_AUTHOR(\"Anthony Fee\");\nMODULE_DESCRIPTION(\"Link eventfd\");\nMODULE_ALIAS(\"devname:eventfd-link\");\n" }, { "path": "lib/librte_vhost/eventfd_link/eventfd_link.h", "content": "/*-\n * This file is provided under a dual BSD/GPLv2 license. When using or\n * redistributing this file, you may do so under either license.\n *\n * GPL LICENSE SUMMARY\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n *\n * This program is free software; you can redistribute it and/or modify\n * it under the terms of version 2 of the GNU General Public License as\n * published by the Free Software Foundation.\n *\n * This program is distributed in the hope that it will be useful, but\n * WITHOUT ANY WARRANTY; without even the implied warranty of\n * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n * General Public License for more details.\n *\n * You should have received a copy of the GNU General Public License\n * along with this program; if not, write to the Free Software\n * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.\n * The full GNU General Public License is included in this distribution\n * in the file called LICENSE.GPL.\n *\n * Contact Information:\n * Intel Corporation\n *\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n */\n\n#ifndef _EVENTFD_LINK_H_\n#define _EVENTFD_LINK_H_\n\n/*\n * ioctl to copy an fd entry in calling process to an fd in a target process\n */\n#define EVENTFD_COPY 1\n\n/*\n * arguements for the EVENTFD_COPY ioctl\n */\nstruct eventfd_copy {\n\tunsigned target_fd; /* fd in the target pid */\n\tunsigned source_fd; /* fd in the calling pid */\n\tpid_t target_pid; /* pid of the target pid */\n};\n#endif /* _EVENTFD_LINK_H_ */\n" }, { "path": "lib/librte_vhost/libvirt/qemu-wrap.py", "content": "#!/usr/bin/python\n#/*\n# * BSD LICENSE\n# *\n# * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# * All rights reserved.\n# *\n# * Redistribution and use in source and binary forms, with or without\n# * modification, are permitted provided that the following conditions\n# * are met:\n# *\n# * * Redistributions of source code must retain the above copyright\n# * notice, this list of conditions and the following disclaimer.\n# * * Redistributions in binary form must reproduce the above copyright\n# * notice, this list of conditions and the following disclaimer in\n# * the documentation and/or other materials provided with the\n# * distribution.\n# * * Neither the name of Intel Corporation nor the names of its\n# * contributors may be used to endorse or promote products derived\n# * from this software without specific prior written permission.\n# *\n# * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n# */\n\n#####################################################################\n# This script is designed to modify the call to the QEMU emulator\n# to support userspace vhost when starting a guest machine through\n# libvirt with vhost enabled. The steps to enable this are as follows\n# and should be run as root:\n#\n# 1. Place this script in a libvirtd's binary search PATH ($PATH)\n# A good location would be in the same directory that the QEMU\n# binary is located\n#\n# 2. Ensure that the script has the same owner/group and file\n# permissions as the QEMU binary\n#\n# 3. Update the VM xml file using \"virsh edit VM.xml\"\n#\n# 3.a) Set the VM to use the launch script\n#\n#\tSet the emulator path contained in the\n#\t\t tags\n#\n#\te.g replace /usr/bin/qemu-kvm\n# with /usr/bin/qemu-wrap.py\n#\n#\t 3.b) Set the VM's device's to use vhost-net offload\n#\n#\t\t\n#\t\n#\t\n#\t\t\n#\n# 4. Enable libvirt to access our userpace device file by adding it to\n# controllers cgroup for libvirtd using the following steps\n#\n# 4.a) In /etc/libvirt/qemu.conf add/edit the following lines:\n# 1) cgroup_controllers = [ ... \"devices\", ... ]\n#\t\t 2) clear_emulator_capabilities = 0\n# 3) user = \"root\"\n# 4) group = \"root\"\n# 5) cgroup_device_acl = [\n# \"/dev/null\", \"/dev/full\", \"/dev/zero\",\n# \"/dev/random\", \"/dev/urandom\",\n# \"/dev/ptmx\", \"/dev/kvm\", \"/dev/kqemu\",\n# \"/dev/rtc\", \"/dev/hpet\", \"/dev/net/tun\",\n# \"/dev/-\",\n# ]\n#\n# 4.b) Disable SELinux or set to permissive mode\n#\n# 4.c) Mount cgroup device controller\n# \"mkdir /dev/cgroup\"\n# \"mount -t cgroup none /dev/cgroup -o devices\"\n#\n# 4.d) Set hugetlbfs_mount variable - ( Optional )\n# VMs using userspace vhost must use hugepage backed\n# memory. This can be enabled in the libvirt XML\n# config by adding a memory backing section to the\n# XML config e.g.\n# \n# \n# \n# This memory backing section should be added after the\n# and sections. This will add\n# flags \"-mem-prealloc -mem-path \" to the QEMU\n# command line. The hugetlbfs_mount variable can be used\n# to override the default passed through by libvirt.\n#\n# if \"-mem-prealloc\" or \"-mem-path \" are not passed\n# through and a vhost device is detected then these options will\n# be automatically added by this script. This script will detect\n# the system hugetlbfs mount point to be used for . The\n# default for this script can be overidden by the\n# hugetlbfs_dir variable in the configuration section of this script.\n#\n#\n# 4.e) Restart the libvirtd system process\n# e.g. on Fedora \"systemctl restart libvirtd.service\"\n#\n#\n# 4.f) Edit the Configuration Parameters section of this script\n# to point to the correct emulator location and set any\n# addition options\n#\n# The script modifies the libvirtd Qemu call by modifying/adding\n# options based on the configuration parameters below.\n# NOTE:\n# emul_path and us_vhost_path must be set\n# All other parameters are optional\n#####################################################################\n\n\n#############################################\n# Configuration Parameters\n#############################################\n#Path to QEMU binary\nemul_path = \"/usr/local/bin/qemu-system-x86_64\"\n\n#Path to userspace vhost device file\n# This filename should match the --dev-basename --dev-index parameters of\n# the command used to launch the userspace vhost sample application e.g.\n# if the sample app lauch command is:\n# ./build/vhost-switch ..... --dev-basename usvhost --dev-index 1\n# then this variable should be set to:\n# us_vhost_path = \"/dev/usvhost-1\"\nus_vhost_path = \"/dev/usvhost-1\"\n\n#List of additional user defined emulation options. These options will\n#be added to all Qemu calls\nemul_opts_user = []\n\n#List of additional user defined emulation options for vhost only.\n#These options will only be added to vhost enabled guests\nemul_opts_user_vhost = []\n\n#For all VHOST enabled VMs, the VM memory is preallocated from hugetlbfs\n# Set this variable to one to enable this option for all VMs\nuse_huge_all = 0\n\n#Instead of autodetecting, override the hugetlbfs directory by setting\n#this variable\nhugetlbfs_dir = \"\"\n\n#############################################\n\n\n#############################################\n# ****** Do Not Modify Below this Line ******\n#############################################\n\nimport sys, os, subprocess\n\n\n#List of open userspace vhost file descriptors\nfd_list = []\n\n#additional virtio device flags when using userspace vhost\nvhost_flags = [ \"csum=off\",\n \"gso=off\",\n \"guest_tso4=off\",\n \"guest_tso6=off\",\n \"guest_ecn=off\"\n ]\n\n\n#############################################\n# Find the system hugefile mount point.\n# Note:\n# if multiple hugetlbfs mount points exist\n# then the first one found will be used\n#############################################\ndef find_huge_mount():\n\n if (len(hugetlbfs_dir)):\n return hugetlbfs_dir\n\n huge_mount = \"\"\n\n if (os.access(\"/proc/mounts\", os.F_OK)):\n f = open(\"/proc/mounts\", \"r\")\n line = f.readline()\n while line:\n line_split = line.split(\" \")\n if line_split[2] == 'hugetlbfs':\n huge_mount = line_split[1]\n break\n line = f.readline()\n else:\n print \"/proc/mounts not found\"\n exit (1)\n\n f.close\n if len(huge_mount) == 0:\n print \"Failed to find hugetlbfs mount point\"\n exit (1)\n\n return huge_mount\n\n\n#############################################\n# Get a userspace Vhost file descriptor\n#############################################\ndef get_vhost_fd():\n\n if (os.access(us_vhost_path, os.F_OK)):\n fd = os.open( us_vhost_path, os.O_RDWR)\n else:\n print (\"US-Vhost file %s not found\" %us_vhost_path)\n exit (1)\n\n return fd\n\n\n#############################################\n# Check for vhostfd. if found then replace\n# with our own vhost fd and append any vhost\n# flags onto the end\n#############################################\ndef modify_netdev_arg(arg):\n\n global fd_list\n vhost_in_use = 0\n s = ''\n new_opts = []\n netdev_opts = arg.split(\",\")\n\n for opt in netdev_opts:\n #check if vhost is used\n if \"vhost\" == opt[:5]:\n vhost_in_use = 1\n else:\n new_opts.append(opt)\n\n #if using vhost append vhost options\n if vhost_in_use == 1:\n #append vhost on option\n new_opts.append('vhost=on')\n #append vhostfd ption\n new_fd = get_vhost_fd()\n new_opts.append('vhostfd=' + str(new_fd))\n fd_list.append(new_fd)\n\n #concatenate all options\n for opt in new_opts:\n if len(s) > 0:\n\t\t\ts+=','\n\n s+=opt\n\n return s\n\n\n#############################################\n# Main\n#############################################\ndef main():\n\n global fd_list\n global vhost_in_use\n new_args = []\n num_cmd_args = len(sys.argv)\n emul_call = ''\n mem_prealloc_set = 0\n mem_path_set = 0\n num = 0;\n\n #parse the parameters\n while (num < num_cmd_args):\n arg = sys.argv[num]\n\n\t\t#Check netdev +1 parameter for vhostfd\n if arg == '-netdev':\n num_vhost_devs = len(fd_list)\n new_args.append(arg)\n\n num+=1\n arg = sys.argv[num]\n mod_arg = modify_netdev_arg(arg)\n new_args.append(mod_arg)\n\n #append vhost flags if this is a vhost device\n # and -device is the next arg\n # i.e -device -opt1,-opt2,...,-opt3,%vhost\n if (num_vhost_devs < len(fd_list)):\n num+=1\n arg = sys.argv[num]\n if arg == '-device':\n new_args.append(arg)\n num+=1\n new_arg = sys.argv[num]\n for flag in vhost_flags:\n new_arg = ''.join([new_arg,',',flag])\n new_args.append(new_arg)\n else:\n new_args.append(arg)\n elif arg == '-mem-prealloc':\n mem_prealloc_set = 1\n new_args.append(arg)\n elif arg == '-mem-path':\n mem_path_set = 1\n new_args.append(arg)\n\n else:\n new_args.append(arg)\n\n num+=1\n\n #Set Qemu binary location\n emul_call+=emul_path\n emul_call+=\" \"\n\n #Add prealloc mem options if using vhost and not already added\n if ((len(fd_list) > 0) and (mem_prealloc_set == 0)):\n emul_call += \"-mem-prealloc \"\n\n #Add mempath mem options if using vhost and not already added\n if ((len(fd_list) > 0) and (mem_path_set == 0)):\n #Detect and add hugetlbfs mount point\n mp = find_huge_mount()\n mp = \"\".join([\"-mem-path \", mp])\n emul_call += mp\n emul_call += \" \"\n\n\n #add user options\n for opt in emul_opts_user:\n emul_call += opt\n emul_call += \" \"\n\n #Add add user vhost only options\n if len(fd_list) > 0:\n for opt in emul_opts_user_vhost:\n emul_call += opt\n emul_call += \" \"\n\n #Add updated libvirt options\n iter_args = iter(new_args)\n #skip 1st arg i.e. call to this script\n next(iter_args)\n for arg in iter_args:\n emul_call+=str(arg)\n emul_call+= \" \"\n\n #Call QEMU\n subprocess.call(emul_call, shell=True)\n\n\n #Close usvhost files\n for fd in fd_list:\n os.close(fd)\n\n\nif __name__ == \"__main__\":\n main()\n" }, { "path": "lib/librte_vhost/rte_virtio_net.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VIRTIO_NET_H_\n#define _VIRTIO_NET_H_\n\n/**\n * @file\n * Interface to vhost net\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\nstruct rte_mbuf;\n\n#define VHOST_MEMORY_MAX_NREGIONS 8\n\n/* Used to indicate that the device is running on a data core */\n#define VIRTIO_DEV_RUNNING 1\n\n/* Backend value set by guest. */\n#define VIRTIO_DEV_STOPPED -1\n\n\n/* Enum for virtqueue management. */\nenum {VIRTIO_RXQ, VIRTIO_TXQ, VIRTIO_QNUM};\n\n#define BUF_VECTOR_MAX 256\n\n/**\n * Structure contains buffer address, length and descriptor index\n * from vring to do scatter RX.\n */\nstruct buf_vector {\n\tuint64_t buf_addr;\n\tuint32_t buf_len;\n\tuint32_t desc_idx;\n};\n\n/**\n * Structure contains variables relevant to RX/TX virtqueues.\n */\nstruct vhost_virtqueue {\n\tstruct vring_desc\t*desc;\t\t\t/**< Virtqueue descriptor ring. */\n\tstruct vring_avail\t*avail;\t\t\t/**< Virtqueue available ring. */\n\tstruct vring_used\t*used;\t\t\t/**< Virtqueue used ring. */\n\tuint32_t\t\tsize;\t\t\t/**< Size of descriptor ring. */\n\tuint32_t\t\tbackend;\t\t/**< Backend value to determine if device should started/stopped. */\n\tuint16_t\t\tvhost_hlen;\t\t/**< Vhost header length (varies depending on RX merge buffers. */\n\tvolatile uint16_t\tlast_used_idx;\t\t/**< Last index used on the available ring */\n\tvolatile uint16_t\tlast_used_idx_res;\t/**< Used for multiple devices reserving buffers. */\n\teventfd_t\t\tcallfd;\t\t\t/**< Used to notify the guest (trigger interrupt). */\n\teventfd_t\t\tkickfd;\t\t\t/**< Currently unused as polling mode is enabled. */\n\tstruct buf_vector\tbuf_vec[BUF_VECTOR_MAX];\t/**< for scatter RX. */\n} __rte_cache_aligned;\n\n/**\n * Device structure contains all configuration information relating to the device.\n */\nstruct virtio_net {\n\tstruct vhost_virtqueue\t*virtqueue[VIRTIO_QNUM];\t/**< Contains all virtqueue information. */\n\tstruct virtio_memory\t*mem;\t\t/**< QEMU memory and memory region information. */\n\tuint64_t\t\tfeatures;\t/**< Negotiated feature set. */\n\tuint64_t\t\tdevice_fh;\t/**< device identifier. */\n\tuint32_t\t\tflags;\t\t/**< Device flags. Only used to check if device is running on data core. */\n#define IF_NAME_SZ (PATH_MAX > IFNAMSIZ ? PATH_MAX : IFNAMSIZ)\n\tchar\t\t\tifname[IF_NAME_SZ];\t/**< Name of the tap device or socket path. */\n\tvoid\t\t\t*priv;\t\t/**< private context */\n} __rte_cache_aligned;\n\n/**\n * Information relating to memory regions including offsets to addresses in QEMUs memory file.\n */\nstruct virtio_memory_regions {\n\tuint64_t\tguest_phys_address;\t/**< Base guest physical address of region. */\n\tuint64_t\tguest_phys_address_end;\t/**< End guest physical address of region. */\n\tuint64_t\tmemory_size;\t\t/**< Size of region. */\n\tuint64_t\tuserspace_address;\t/**< Base userspace address of region. */\n\tuint64_t\taddress_offset;\t\t/**< Offset of region for address translation. */\n};\n\n\n/**\n * Memory structure includes region and mapping information.\n */\nstruct virtio_memory {\n\tuint64_t\tbase_address;\t/**< Base QEMU userspace address of the memory file. */\n\tuint64_t\tmapped_address;\t/**< Mapped address of memory file base in our applications memory space. */\n\tuint64_t\tmapped_size;\t/**< Total size of memory file. */\n\tuint32_t\tnregions;\t/**< Number of memory regions. */\n\tstruct virtio_memory_regions regions[0]; /**< Memory region information. */\n};\n\n/**\n * Device operations to add/remove device.\n *\n * Make sure to set VIRTIO_DEV_RUNNING to the device flags in new_device and\n * remove it in destroy_device.\n *\n */\nstruct virtio_net_device_ops {\n\tint (*new_device)(struct virtio_net *);\t/**< Add device. */\n\tvoid (*destroy_device)(volatile struct virtio_net *);\t/**< Remove device. */\n};\n\nstatic inline uint16_t __attribute__((always_inline))\nrte_vring_available_entries(struct virtio_net *dev, uint16_t queue_id)\n{\n\tstruct vhost_virtqueue *vq = dev->virtqueue[queue_id];\n\treturn *(volatile uint16_t *)&vq->avail->idx - vq->last_used_idx_res;\n}\n\n/**\n * Function to convert guest physical addresses to vhost virtual addresses.\n * This is used to convert guest virtio buffer addresses.\n */\nstatic inline uint64_t __attribute__((always_inline))\ngpa_to_vva(struct virtio_net *dev, uint64_t guest_pa)\n{\n\tstruct virtio_memory_regions *region;\n\tuint32_t regionidx;\n\tuint64_t vhost_va = 0;\n\n\tfor (regionidx = 0; regionidx < dev->mem->nregions; regionidx++) {\n\t\tregion = &dev->mem->regions[regionidx];\n\t\tif ((guest_pa >= region->guest_phys_address) &&\n\t\t\t(guest_pa <= region->guest_phys_address_end)) {\n\t\t\tvhost_va = region->address_offset + guest_pa;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn vhost_va;\n}\n\n/**\n * Disable features in feature_mask. Returns 0 on success.\n */\nint rte_vhost_feature_disable(uint64_t feature_mask);\n\n/**\n * Enable features in feature_mask. Returns 0 on success.\n */\nint rte_vhost_feature_enable(uint64_t feature_mask);\n\n/* Returns currently supported vhost features */\nuint64_t rte_vhost_feature_get(void);\n\nint rte_vhost_enable_guest_notification(struct virtio_net *dev, uint16_t queue_id, int enable);\n\n/* Register vhost driver. dev_name could be different for multiple instance support. */\nint rte_vhost_driver_register(const char *dev_name);\n\n/* Unregister vhost driver. This is only meaningful to vhost user. */\nint rte_vhost_driver_unregister(const char *dev_name);\n\n/* Register callbacks. */\nint rte_vhost_driver_callback_register(struct virtio_net_device_ops const * const);\n/* Start vhost driver session blocking loop. */\nint rte_vhost_driver_session_start(void);\n\n/**\n * This function adds buffers to the virtio devices RX virtqueue. Buffers can\n * be received from the physical port or from another virtual device. A packet\n * count is returned to indicate the number of packets that were succesfully\n * added to the RX queue.\n * @param dev\n * virtio-net device\n * @param queue_id\n * virtio queue index in mq case\n * @param pkts\n * array to contain packets to be enqueued\n * @param count\n * packets num to be enqueued\n * @return\n * num of packets enqueued\n */\nuint16_t rte_vhost_enqueue_burst(struct virtio_net *dev, uint16_t queue_id,\n\tstruct rte_mbuf **pkts, uint16_t count);\n\n/**\n * This function gets guest buffers from the virtio device TX virtqueue,\n * construct host mbufs, copies guest buffer content to host mbufs and\n * store them in pkts to be processed.\n * @param dev\n * virtio-net device\n * @param queue_id\n * virtio queue index in mq case\n * @param mbuf_pool\n * mbuf_pool where host mbuf is allocated.\n * @param pkts\n * array to contain packets to be dequeued\n * @param count\n * packets num to be dequeued\n * @return\n * num of packets dequeued\n */\nuint16_t rte_vhost_dequeue_burst(struct virtio_net *dev, uint16_t queue_id,\n\tstruct rte_mempool *mbuf_pool, struct rte_mbuf **pkts, uint16_t count);\n\n#endif /* _VIRTIO_NET_H_ */\n" }, { "path": "lib/librte_vhost/vhost-net.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VHOST_NET_CDEV_H_\n#define _VHOST_NET_CDEV_H_\n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"rte_virtio_net.h\"\n\nextern struct vhost_net_device_ops const *ops;\n\n/* Macros for printing using RTE_LOG */\n#define RTE_LOGTYPE_VHOST_CONFIG RTE_LOGTYPE_USER1\n#define RTE_LOGTYPE_VHOST_DATA RTE_LOGTYPE_USER1\n\n#ifdef RTE_LIBRTE_VHOST_DEBUG\n#define VHOST_MAX_PRINT_BUFF 6072\n#define LOG_LEVEL RTE_LOG_DEBUG\n#define LOG_DEBUG(log_type, fmt, args...) RTE_LOG(DEBUG, log_type, fmt, ##args)\n#define PRINT_PACKET(device, addr, size, header) do { \\\n\tchar *pkt_addr = (char *)(addr); \\\n\tunsigned int index; \\\n\tchar packet[VHOST_MAX_PRINT_BUFF]; \\\n\t\\\n\tif ((header)) \\\n\t\tsnprintf(packet, VHOST_MAX_PRINT_BUFF, \"(%\" PRIu64 \") Header size %d: \", (device->device_fh), (size)); \\\n\telse \\\n\t\tsnprintf(packet, VHOST_MAX_PRINT_BUFF, \"(%\" PRIu64 \") Packet size %d: \", (device->device_fh), (size)); \\\n\tfor (index = 0; index < (size); index++) { \\\n\t\tsnprintf(packet + strnlen(packet, VHOST_MAX_PRINT_BUFF), VHOST_MAX_PRINT_BUFF - strnlen(packet, VHOST_MAX_PRINT_BUFF), \\\n\t\t\t\"%02hhx \", pkt_addr[index]); \\\n\t} \\\n\tsnprintf(packet + strnlen(packet, VHOST_MAX_PRINT_BUFF), VHOST_MAX_PRINT_BUFF - strnlen(packet, VHOST_MAX_PRINT_BUFF), \"\\n\"); \\\n\t\\\n\tLOG_DEBUG(VHOST_DATA, \"%s\", packet); \\\n} while (0)\n#else\n#define LOG_LEVEL RTE_LOG_INFO\n#define LOG_DEBUG(log_type, fmt, args...) do {} while (0)\n#define PRINT_PACKET(device, addr, size, header) do {} while (0)\n#endif\n\n\n/*\n * Structure used to identify device context.\n */\nstruct vhost_device_ctx {\n\tpid_t\t\tpid;\t/* PID of process calling the IOCTL. */\n\tuint64_t\tfh;\t/* Populated with fi->fh to track the device index. */\n};\n\n/*\n * Structure contains function pointers to be defined in virtio-net.c. These\n * functions are called in CUSE context and are used to configure devices.\n */\nstruct vhost_net_device_ops {\n\tint (*new_device)(struct vhost_device_ctx);\n\tvoid (*destroy_device)(struct vhost_device_ctx);\n\n\tvoid (*set_ifname)(struct vhost_device_ctx,\n\t\tconst char *if_name, unsigned int if_len);\n\n\tint (*get_features)(struct vhost_device_ctx, uint64_t *);\n\tint (*set_features)(struct vhost_device_ctx, uint64_t *);\n\n\tint (*set_vring_num)(struct vhost_device_ctx, struct vhost_vring_state *);\n\tint (*set_vring_addr)(struct vhost_device_ctx, struct vhost_vring_addr *);\n\tint (*set_vring_base)(struct vhost_device_ctx, struct vhost_vring_state *);\n\tint (*get_vring_base)(struct vhost_device_ctx, uint32_t, struct vhost_vring_state *);\n\n\tint (*set_vring_kick)(struct vhost_device_ctx, struct vhost_vring_file *);\n\tint (*set_vring_call)(struct vhost_device_ctx, struct vhost_vring_file *);\n\n\tint (*set_backend)(struct vhost_device_ctx, struct vhost_vring_file *);\n\n\tint (*set_owner)(struct vhost_device_ctx);\n\tint (*reset_owner)(struct vhost_device_ctx);\n};\n\n\nstruct vhost_net_device_ops const *get_virtio_net_callbacks(void);\n#endif /* _VHOST_NET_CDEV_H_ */\n" }, { "path": "lib/librte_vhost/vhost_cuse/eventfd_copy.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"eventfd_link/eventfd_link.h\"\n#include \"eventfd_copy.h\"\n#include \"vhost-net.h\"\n\nstatic const char eventfd_cdev[] = \"/dev/eventfd-link\";\n\n/*\n * This function uses the eventfd_link kernel module to copy an eventfd file\n * descriptor provided by QEMU in to our process space.\n */\nint\neventfd_copy(int target_fd, int target_pid)\n{\n\tint eventfd_link, ret;\n\tstruct eventfd_copy eventfd_copy;\n\tint fd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);\n\n\tif (fd == -1)\n\t\treturn -1;\n\n\t/* Open the character device to the kernel module. */\n\t/* TODO: check this earlier rather than fail until VM boots! */\n\teventfd_link = open(eventfd_cdev, O_RDWR);\n\tif (eventfd_link < 0) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"eventfd_link module is not loaded\\n\");\n\t\tclose(fd);\n\t\treturn -1;\n\t}\n\n\teventfd_copy.source_fd = fd;\n\teventfd_copy.target_fd = target_fd;\n\teventfd_copy.target_pid = target_pid;\n\t/* Call the IOCTL to copy the eventfd. */\n\tret = ioctl(eventfd_link, EVENTFD_COPY, &eventfd_copy);\n\tclose(eventfd_link);\n\n\tif (ret < 0) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"EVENTFD_COPY ioctl failed\\n\");\n\t\tclose(fd);\n\t\treturn -1;\n\t}\n\n\treturn fd;\n}\n" }, { "path": "lib/librte_vhost/vhost_cuse/eventfd_copy.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef _EVENTFD_H\n#define _EVENTFD_H\n\nint\neventfd_copy(int target_fd, int target_pid);\n\n#endif\n" }, { "path": "lib/librte_vhost/vhost_cuse/vhost-net-cdev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n\n#include \"virtio-net-cdev.h\"\n#include \"vhost-net.h\"\n#include \"eventfd_copy.h\"\n\n#define FUSE_OPT_DUMMY \"\\0\\0\"\n#define FUSE_OPT_FORE \"-f\\0\\0\"\n#define FUSE_OPT_NOMULTI \"-s\\0\\0\"\n\nstatic const uint32_t default_major = 231;\nstatic const uint32_t default_minor = 1;\nstatic const char cuse_device_name[] = \"/dev/cuse\";\nstatic const char default_cdev[] = \"vhost-net\";\n\nstatic struct fuse_session *session;\nstruct vhost_net_device_ops const *ops;\n\n/*\n * Returns vhost_device_ctx from given fuse_req_t. The index is populated later\n * when the device is added to the device linked list.\n */\nstatic struct vhost_device_ctx\nfuse_req_to_vhost_ctx(fuse_req_t req, struct fuse_file_info *fi)\n{\n\tstruct vhost_device_ctx ctx;\n\tstruct fuse_ctx const *const req_ctx = fuse_req_ctx(req);\n\n\tctx.pid = req_ctx->pid;\n\tctx.fh = fi->fh;\n\n\treturn ctx;\n}\n\n/*\n * When the device is created in QEMU it gets initialised here and\n * added to the device linked list.\n */\nstatic void\nvhost_net_open(fuse_req_t req, struct fuse_file_info *fi)\n{\n\tstruct vhost_device_ctx ctx = fuse_req_to_vhost_ctx(req, fi);\n\tint err = 0;\n\n\terr = ops->new_device(ctx);\n\tif (err == -1) {\n\t\tfuse_reply_err(req, EPERM);\n\t\treturn;\n\t}\n\n\tfi->fh = err;\n\n\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\"(%\"PRIu64\") Device configuration started\\n\", fi->fh);\n\tfuse_reply_open(req, fi);\n}\n\n/*\n * When QEMU is shutdown or killed the device gets released.\n */\nstatic void\nvhost_net_release(fuse_req_t req, struct fuse_file_info *fi)\n{\n\tint err = 0;\n\tstruct vhost_device_ctx ctx = fuse_req_to_vhost_ctx(req, fi);\n\n\tops->destroy_device(ctx);\n\tRTE_LOG(INFO, VHOST_CONFIG, \"(%\"PRIu64\") Device released\\n\", ctx.fh);\n\tfuse_reply_err(req, err);\n}\n\n/*\n * Boilerplate code for CUSE IOCTL\n * Implicit arguments: ctx, req, result.\n */\n#define VHOST_IOCTL(func) do {\t\\\n\tresult = (func)(ctx);\t\\\n\tfuse_reply_ioctl(req, result, NULL, 0);\t\\\n} while (0)\n\n/*\n * Boilerplate IOCTL RETRY\n * Implicit arguments: req.\n */\n#define VHOST_IOCTL_RETRY(size_r, size_w) do {\t\\\n\tstruct iovec iov_r = { arg, (size_r) };\t\\\n\tstruct iovec iov_w = { arg, (size_w) };\t\\\n\tfuse_reply_ioctl_retry(req, &iov_r,\t\\\n\t\t(size_r) ? 1 : 0, &iov_w, (size_w) ? 1 : 0);\\\n} while (0)\n\n/*\n * Boilerplate code for CUSE Read IOCTL\n * Implicit arguments: ctx, req, result, in_bufsz, in_buf.\n */\n#define VHOST_IOCTL_R(type, var, func) do {\t\\\n\tif (!in_bufsz) {\t\\\n\t\tVHOST_IOCTL_RETRY(sizeof(type), 0);\\\n\t} else {\t\\\n\t\t(var) = *(const type*)in_buf;\t\\\n\t\tresult = func(ctx, &(var));\t\\\n\t\tfuse_reply_ioctl(req, result, NULL, 0);\\\n\t}\t\\\n} while (0)\n\n/*\n * Boilerplate code for CUSE Write IOCTL\n * Implicit arguments: ctx, req, result, out_bufsz.\n */\n#define VHOST_IOCTL_W(type, var, func) do {\t\\\n\tif (!out_bufsz) {\t\\\n\t\tVHOST_IOCTL_RETRY(0, sizeof(type));\\\n\t} else {\t\\\n\t\tresult = (func)(ctx, &(var));\\\n\t\tfuse_reply_ioctl(req, result, &(var), sizeof(type));\\\n\t} \\\n} while (0)\n\n/*\n * Boilerplate code for CUSE Read/Write IOCTL\n * Implicit arguments: ctx, req, result, in_bufsz, in_buf.\n */\n#define VHOST_IOCTL_RW(type1, var1, type2, var2, func) do {\t\\\n\tif (!in_bufsz) {\t\\\n\t\tVHOST_IOCTL_RETRY(sizeof(type1), sizeof(type2));\\\n\t} else {\t\\\n\t\t(var1) = *(const type1*) (in_buf);\t\\\n\t\tresult = (func)(ctx, (var1), &(var2));\t\\\n\t\tfuse_reply_ioctl(req, result, &(var2), sizeof(type2));\\\n\t}\t\\\n} while (0)\n\n/*\n * The IOCTLs are handled using CUSE/FUSE in userspace. Depending on the type\n * of IOCTL a buffer is requested to read or to write. This request is handled\n * by FUSE and the buffer is then given to CUSE.\n */\nstatic void\nvhost_net_ioctl(fuse_req_t req, int cmd, void *arg,\n\t\tstruct fuse_file_info *fi, __rte_unused unsigned flags,\n\t\tconst void *in_buf, size_t in_bufsz, size_t out_bufsz)\n{\n\tstruct vhost_device_ctx ctx = fuse_req_to_vhost_ctx(req, fi);\n\tstruct vhost_vring_file file;\n\tstruct vhost_vring_state state;\n\tstruct vhost_vring_addr addr;\n\tuint64_t features;\n\tuint32_t index;\n\tint result = 0;\n\n\tswitch (cmd) {\n\tcase VHOST_NET_SET_BACKEND:\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: VHOST_NET_SET_BACKEND\\n\", ctx.fh);\n\t\tif (!in_buf) {\n\t\t\tVHOST_IOCTL_RETRY(sizeof(file), 0);\n\t\t\tbreak;\n\t\t}\n\t\tfile = *(const struct vhost_vring_file *)in_buf;\n\t\tresult = cuse_set_backend(ctx, &file);\n\t\tfuse_reply_ioctl(req, result, NULL, 0);\n\t\tbreak;\n\n\tcase VHOST_GET_FEATURES:\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: VHOST_GET_FEATURES\\n\", ctx.fh);\n\t\tVHOST_IOCTL_W(uint64_t, features, ops->get_features);\n\t\tbreak;\n\n\tcase VHOST_SET_FEATURES:\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: VHOST_SET_FEATURES\\n\", ctx.fh);\n\t\tVHOST_IOCTL_R(uint64_t, features, ops->set_features);\n\t\tbreak;\n\n\tcase VHOST_RESET_OWNER:\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: VHOST_RESET_OWNER\\n\", ctx.fh);\n\t\tVHOST_IOCTL(ops->reset_owner);\n\t\tbreak;\n\n\tcase VHOST_SET_OWNER:\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: VHOST_SET_OWNER\\n\", ctx.fh);\n\t\tVHOST_IOCTL(ops->set_owner);\n\t\tbreak;\n\n\tcase VHOST_SET_MEM_TABLE:\n\t\t/*TODO fix race condition.*/\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: VHOST_SET_MEM_TABLE\\n\", ctx.fh);\n\t\tstatic struct vhost_memory mem_temp;\n\n\t\tswitch (in_bufsz) {\n\t\tcase 0:\n\t\t\tVHOST_IOCTL_RETRY(sizeof(struct vhost_memory), 0);\n\t\t\tbreak;\n\n\t\tcase sizeof(struct vhost_memory):\n\t\t\tmem_temp = *(const struct vhost_memory *) in_buf;\n\n\t\t\tif (mem_temp.nregions > 0) {\n\t\t\t\tVHOST_IOCTL_RETRY(sizeof(struct vhost_memory) +\n\t\t\t\t\t(sizeof(struct vhost_memory_region) *\n\t\t\t\t\t\tmem_temp.nregions), 0);\n\t\t\t} else {\n\t\t\t\tresult = -1;\n\t\t\t\tfuse_reply_ioctl(req, result, NULL, 0);\n\t\t\t}\n\t\t\tbreak;\n\n\t\tdefault:\n\t\t\tresult = cuse_set_mem_table(ctx, in_buf,\n\t\t\t\tmem_temp.nregions);\n\t\t\tif (result)\n\t\t\t\tfuse_reply_err(req, EINVAL);\n\t\t\telse\n\t\t\t\tfuse_reply_ioctl(req, result, NULL, 0);\n\t\t}\n\t\tbreak;\n\n\tcase VHOST_SET_VRING_NUM:\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: VHOST_SET_VRING_NUM\\n\", ctx.fh);\n\t\tVHOST_IOCTL_R(struct vhost_vring_state, state,\n\t\t\tops->set_vring_num);\n\t\tbreak;\n\n\tcase VHOST_SET_VRING_BASE:\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: VHOST_SET_VRING_BASE\\n\", ctx.fh);\n\t\tVHOST_IOCTL_R(struct vhost_vring_state, state,\n\t\t\tops->set_vring_base);\n\t\tbreak;\n\n\tcase VHOST_GET_VRING_BASE:\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: VHOST_GET_VRING_BASE\\n\", ctx.fh);\n\t\tVHOST_IOCTL_RW(uint32_t, index,\n\t\t\tstruct vhost_vring_state, state, ops->get_vring_base);\n\t\tbreak;\n\n\tcase VHOST_SET_VRING_ADDR:\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: VHOST_SET_VRING_ADDR\\n\", ctx.fh);\n\t\tVHOST_IOCTL_R(struct vhost_vring_addr, addr,\n\t\t\tops->set_vring_addr);\n\t\tbreak;\n\n\tcase VHOST_SET_VRING_KICK:\n\tcase VHOST_SET_VRING_CALL:\n\t\tif (cmd == VHOST_SET_VRING_KICK)\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"(%\"PRIu64\") IOCTL: VHOST_SET_VRING_KICK\\n\",\n\t\t\tctx.fh);\n\t\telse\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"(%\"PRIu64\") IOCTL: VHOST_SET_VRING_CALL\\n\",\n\t\t\tctx.fh);\n\t\tif (!in_buf)\n\t\t\tVHOST_IOCTL_RETRY(sizeof(struct vhost_vring_file), 0);\n\t\telse {\n\t\t\tint fd;\n\t\t\tfile = *(const struct vhost_vring_file *)in_buf;\n\t\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\t\"idx:%d fd:%d\\n\", file.index, file.fd);\n\t\t\tfd = eventfd_copy(file.fd, ctx.pid);\n\t\t\tif (fd < 0) {\n\t\t\t\tfuse_reply_ioctl(req, -1, NULL, 0);\n\t\t\t\tresult = -1;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tfile.fd = fd;\n\t\t\tif (cmd == VHOST_SET_VRING_KICK) {\n\t\t\t\tresult = ops->set_vring_kick(ctx, &file);\n\t\t\t\tfuse_reply_ioctl(req, result, NULL, 0);\n\t\t\t} else {\n\t\t\t\tresult = ops->set_vring_call(ctx, &file);\n\t\t\t\tfuse_reply_ioctl(req, result, NULL, 0);\n\t\t\t}\n\t\t}\n\t\tbreak;\n\n\tdefault:\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: DOESN NOT EXIST\\n\", ctx.fh);\n\t\tresult = -1;\n\t\tfuse_reply_ioctl(req, result, NULL, 0);\n\t}\n\n\tif (result < 0)\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: FAIL\\n\", ctx.fh);\n\telse\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") IOCTL: SUCCESS\\n\", ctx.fh);\n}\n\n/*\n * Structure handling open, release and ioctl function pointers is populated.\n */\nstatic const struct cuse_lowlevel_ops vhost_net_ops = {\n\t.open\t\t= vhost_net_open,\n\t.release\t= vhost_net_release,\n\t.ioctl\t\t= vhost_net_ioctl,\n};\n\n/*\n * cuse_info is populated and used to register the cuse device.\n * vhost_net_device_ops are also passed when the device is registered in app.\n */\nint\nrte_vhost_driver_register(const char *dev_name)\n{\n\tstruct cuse_info cuse_info;\n\tchar device_name[PATH_MAX] = \"\";\n\tchar char_device_name[PATH_MAX] = \"\";\n\tconst char *device_argv[] = { device_name };\n\n\tchar fuse_opt_dummy[] = FUSE_OPT_DUMMY;\n\tchar fuse_opt_fore[] = FUSE_OPT_FORE;\n\tchar fuse_opt_nomulti[] = FUSE_OPT_NOMULTI;\n\tchar *fuse_argv[] = {fuse_opt_dummy, fuse_opt_fore, fuse_opt_nomulti};\n\n\tif (access(cuse_device_name, R_OK | W_OK) < 0) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"char device %s can't be accessed, maybe not exist\\n\",\n\t\t\tcuse_device_name);\n\t\treturn -1;\n\t}\n\n\t/*\n\t * The device name is created. This is passed to QEMU so that it can\n\t * register the device with our application.\n\t */\n\tsnprintf(device_name, PATH_MAX, \"DEVNAME=%s\", dev_name);\n\tsnprintf(char_device_name, PATH_MAX, \"/dev/%s\", dev_name);\n\n\t/* Check if device already exists. */\n\tif (access(char_device_name, F_OK) != -1) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"char device %s already exists\\n\", char_device_name);\n\t\treturn -1;\n\t}\n\n\tmemset(&cuse_info, 0, sizeof(cuse_info));\n\tcuse_info.dev_major = default_major;\n\tcuse_info.dev_minor = default_minor;\n\tcuse_info.dev_info_argc = 1;\n\tcuse_info.dev_info_argv = device_argv;\n\tcuse_info.flags = CUSE_UNRESTRICTED_IOCTL;\n\n\tops = get_virtio_net_callbacks();\n\n\tsession = cuse_lowlevel_setup(3, fuse_argv,\n\t\t\t&cuse_info, &vhost_net_ops, 0, NULL);\n\tif (session == NULL)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/**\n * An empty function for unregister\n */\nint\nrte_vhost_driver_unregister(const char *dev_name __rte_unused)\n{\n\treturn 0;\n}\n\n/**\n * The CUSE session is launched allowing the application to receive open,\n * release and ioctl calls.\n */\nint\nrte_vhost_driver_session_start(void)\n{\n\tfuse_session_loop(session);\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_vhost/vhost_cuse/virtio-net-cdev.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \"rte_virtio_net.h\"\n#include \"vhost-net.h\"\n#include \"virtio-net-cdev.h\"\n#include \"virtio-net.h\"\n#include \"eventfd_copy.h\"\n\n/* Line size for reading maps file. */\nstatic const uint32_t BUFSIZE = PATH_MAX;\n\n/* Size of prot char array in procmap. */\n#define PROT_SZ 5\n\n/* Number of elements in procmap struct. */\n#define PROCMAP_SZ 8\n\n/* Structure containing information gathered from maps file. */\nstruct procmap {\n\tuint64_t va_start;\t/* Start virtual address in file. */\n\tuint64_t len;\t\t/* Size of file. */\n\tuint64_t pgoff;\t\t/* Not used. */\n\tuint32_t maj;\t\t/* Not used. */\n\tuint32_t min;\t\t/* Not used. */\n\tuint32_t ino;\t\t/* Not used. */\n\tchar prot[PROT_SZ];\t/* Not used. */\n\tchar fname[PATH_MAX];\t/* File name. */\n};\n\n/*\n * Locate the file containing QEMU's memory space and\n * map it to our address space.\n */\nstatic int\nhost_memory_map(pid_t pid, uint64_t addr,\n\tuint64_t *mapped_address, uint64_t *mapped_size)\n{\n\tstruct dirent *dptr = NULL;\n\tstruct procmap procmap;\n\tDIR *dp = NULL;\n\tint fd;\n\tint i;\n\tchar memfile[PATH_MAX];\n\tchar mapfile[PATH_MAX];\n\tchar procdir[PATH_MAX];\n\tchar resolved_path[PATH_MAX];\n\tchar *path = NULL;\n\tFILE *fmap;\n\tvoid *map;\n\tuint8_t found = 0;\n\tchar line[BUFSIZE];\n\tchar dlm[] = \"- : \";\n\tchar *str, *sp, *in[PROCMAP_SZ];\n\tchar *end = NULL;\n\n\t/* Path where mem files are located. */\n\tsnprintf(procdir, PATH_MAX, \"/proc/%u/fd/\", pid);\n\t/* Maps file used to locate mem file. */\n\tsnprintf(mapfile, PATH_MAX, \"/proc/%u/maps\", pid);\n\n\tfmap = fopen(mapfile, \"r\");\n\tif (fmap == NULL) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"Failed to open maps file for pid %d\\n\",\n\t\t\tpid);\n\t\treturn -1;\n\t}\n\n\t/* Read through maps file until we find out base_address. */\n\twhile (fgets(line, BUFSIZE, fmap) != 0) {\n\t\tstr = line;\n\t\terrno = 0;\n\t\t/* Split line into fields. */\n\t\tfor (i = 0; i < PROCMAP_SZ; i++) {\n\t\t\tin[i] = strtok_r(str, &dlm[i], &sp);\n\t\t\tif ((in[i] == NULL) || (errno != 0)) {\n\t\t\t\tfclose(fmap);\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tstr = NULL;\n\t\t}\n\n\t\t/* Convert/Copy each field as needed. */\n\t\tprocmap.va_start = strtoull(in[0], &end, 16);\n\t\tif ((in[0] == '\\0') || (end == NULL) || (*end != '\\0') ||\n\t\t\t(errno != 0)) {\n\t\t\tfclose(fmap);\n\t\t\treturn -1;\n\t\t}\n\n\t\tprocmap.len = strtoull(in[1], &end, 16);\n\t\tif ((in[1] == '\\0') || (end == NULL) || (*end != '\\0') ||\n\t\t\t(errno != 0)) {\n\t\t\tfclose(fmap);\n\t\t\treturn -1;\n\t\t}\n\n\t\tprocmap.pgoff = strtoull(in[3], &end, 16);\n\t\tif ((in[3] == '\\0') || (end == NULL) || (*end != '\\0') ||\n\t\t\t(errno != 0)) {\n\t\t\tfclose(fmap);\n\t\t\treturn -1;\n\t\t}\n\n\t\tprocmap.maj = strtoul(in[4], &end, 16);\n\t\tif ((in[4] == '\\0') || (end == NULL) || (*end != '\\0') ||\n\t\t\t(errno != 0)) {\n\t\t\tfclose(fmap);\n\t\t\treturn -1;\n\t\t}\n\n\t\tprocmap.min = strtoul(in[5], &end, 16);\n\t\tif ((in[5] == '\\0') || (end == NULL) || (*end != '\\0') ||\n\t\t\t(errno != 0)) {\n\t\t\tfclose(fmap);\n\t\t\treturn -1;\n\t\t}\n\n\t\tprocmap.ino = strtoul(in[6], &end, 16);\n\t\tif ((in[6] == '\\0') || (end == NULL) || (*end != '\\0') ||\n\t\t\t(errno != 0)) {\n\t\t\tfclose(fmap);\n\t\t\treturn -1;\n\t\t}\n\n\t\tmemcpy(&procmap.prot, in[2], PROT_SZ);\n\t\tmemcpy(&procmap.fname, in[7], PATH_MAX);\n\n\t\tif (procmap.va_start == addr) {\n\t\t\tprocmap.len = procmap.len - procmap.va_start;\n\t\t\tfound = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\tfclose(fmap);\n\n\tif (!found) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"Failed to find memory file in pid %d maps file\\n\",\n\t\t\tpid);\n\t\treturn -1;\n\t}\n\n\t/* Find the guest memory file among the process fds. */\n\tdp = opendir(procdir);\n\tif (dp == NULL) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"Cannot open pid %d process directory\\n\",\n\t\t\tpid);\n\t\treturn -1;\n\t}\n\n\tfound = 0;\n\n\t/* Read the fd directory contents. */\n\twhile (NULL != (dptr = readdir(dp))) {\n\t\tsnprintf(memfile, PATH_MAX, \"/proc/%u/fd/%s\",\n\t\t\t\tpid, dptr->d_name);\n\t\tpath = realpath(memfile, resolved_path);\n\t\tif ((path == NULL) && (strlen(resolved_path) == 0)) {\n\t\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\t\"Failed to resolve fd directory\\n\");\n\t\t\tclosedir(dp);\n\t\t\treturn -1;\n\t\t}\n\t\tif (strncmp(resolved_path, procmap.fname,\n\t\t\tstrnlen(procmap.fname, PATH_MAX)) == 0) {\n\t\t\tfound = 1;\n\t\t\tbreak;\n\t\t}\n\t}\n\n\tclosedir(dp);\n\n\tif (found == 0) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"Failed to find memory file for pid %d\\n\",\n\t\t\tpid);\n\t\treturn -1;\n\t}\n\t/* Open the shared memory file and map the memory into this process. */\n\tfd = open(memfile, O_RDWR);\n\n\tif (fd == -1) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"Failed to open %s for pid %d\\n\",\n\t\t\tmemfile, pid);\n\t\treturn -1;\n\t}\n\n\tmap = mmap(0, (size_t)procmap.len, PROT_READ|PROT_WRITE,\n\t\t\tMAP_POPULATE|MAP_SHARED, fd, 0);\n\tclose(fd);\n\n\tif (map == MAP_FAILED) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"Error mapping the file %s for pid %d\\n\",\n\t\t\tmemfile, pid);\n\t\treturn -1;\n\t}\n\n\t/* Store the memory address and size in the device data structure */\n\t*mapped_address = (uint64_t)(uintptr_t)map;\n\t*mapped_size = procmap.len;\n\n\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\"Mem File: %s->%s - Size: %llu - VA: %p\\n\",\n\t\tmemfile, resolved_path,\n\t\t(unsigned long long)*mapped_size, map);\n\n\treturn 0;\n}\n\nint\ncuse_set_mem_table(struct vhost_device_ctx ctx,\n\tconst struct vhost_memory *mem_regions_addr, uint32_t nregions)\n{\n\tuint64_t size = offsetof(struct vhost_memory, regions);\n\tuint32_t idx, valid_regions;\n\tstruct virtio_memory_regions *pregion;\n\tstruct vhost_memory_region *mem_regions = (void *)(uintptr_t)\n\t\t((uint64_t)(uintptr_t)mem_regions_addr + size);\n\tuint64_t base_address = 0, mapped_address, mapped_size;\n\tstruct virtio_net *dev;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\n\tif (dev->mem && dev->mem->mapped_address) {\n\t\tmunmap((void *)(uintptr_t)dev->mem->mapped_address,\n\t\t\t(size_t)dev->mem->mapped_size);\n\t\tfree(dev->mem);\n\t\tdev->mem = NULL;\n\t}\n\n\tdev->mem = calloc(1, sizeof(struct virtio_memory) +\n\t\tsizeof(struct virtio_memory_regions) * nregions);\n\tif (dev->mem == NULL) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") Failed to allocate memory for dev->mem\\n\",\n\t\t\tdev->device_fh);\n\t\treturn -1;\n\t}\n\n\tpregion = &dev->mem->regions[0];\n\n\tfor (idx = 0; idx < nregions; idx++) {\n\t\tpregion[idx].guest_phys_address =\n\t\t\tmem_regions[idx].guest_phys_addr;\n\t\tpregion[idx].guest_phys_address_end =\n\t\t\tpregion[idx].guest_phys_address +\n\t\t\tmem_regions[idx].memory_size;\n\t\tpregion[idx].memory_size =\n\t\t\tmem_regions[idx].memory_size;\n\t\tpregion[idx].userspace_address =\n\t\t\tmem_regions[idx].userspace_addr;\n\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"REGION: %u - GPA: %p - QVA: %p - SIZE (%\"PRIu64\")\\n\",\n\t\t\tidx,\n\t\t\t(void *)(uintptr_t)pregion[idx].guest_phys_address,\n\t\t\t(void *)(uintptr_t)pregion[idx].userspace_address,\n\t\t\tpregion[idx].memory_size);\n\n\t\t/*set the base address mapping*/\n\t\tif (pregion[idx].guest_phys_address == 0x0) {\n\t\t\tbase_address =\n\t\t\t\tpregion[idx].userspace_address;\n\t\t\t/* Map VM memory file */\n\t\t\tif (host_memory_map(ctx.pid, base_address,\n\t\t\t\t&mapped_address, &mapped_size) != 0) {\n\t\t\t\tfree(dev->mem);\n\t\t\t\tdev->mem = NULL;\n\t\t\t\treturn -1;\n\t\t\t}\n\t\t\tdev->mem->mapped_address = mapped_address;\n\t\t\tdev->mem->base_address = base_address;\n\t\t\tdev->mem->mapped_size = mapped_size;\n\t\t}\n\t}\n\n\t/* Check that we have a valid base address. */\n\tif (base_address == 0) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"Failed to find base address of qemu memory file.\\n\");\n\t\tfree(dev->mem);\n\t\tdev->mem = NULL;\n\t\treturn -1;\n\t}\n\n\tvalid_regions = nregions;\n\tfor (idx = 0; idx < nregions; idx++) {\n\t\tif ((pregion[idx].userspace_address < base_address) ||\n\t\t\t(pregion[idx].userspace_address >\n\t\t\t(base_address + mapped_size)))\n\t\t\tvalid_regions--;\n\t}\n\n\n\tif (valid_regions != nregions) {\n\t\tvalid_regions = 0;\n\t\tfor (idx = nregions; 0 != idx--; ) {\n\t\t\tif ((pregion[idx].userspace_address < base_address) ||\n\t\t\t(pregion[idx].userspace_address >\n\t\t\t(base_address + mapped_size))) {\n\t\t\t\tmemmove(&pregion[idx], &pregion[idx + 1],\n\t\t\t\t\tsizeof(struct virtio_memory_regions) *\n\t\t\t\t\tvalid_regions);\n\t\t\t} else\n\t\t\t\tvalid_regions++;\n\t\t}\n\t}\n\n\tfor (idx = 0; idx < valid_regions; idx++) {\n\t\tpregion[idx].address_offset =\n\t\t\tmapped_address - base_address +\n\t\t\tpregion[idx].userspace_address -\n\t\t\tpregion[idx].guest_phys_address;\n\t}\n\tdev->mem->nregions = valid_regions;\n\n\treturn 0;\n}\n\n/*\n * Function to get the tap device name from the provided file descriptor and\n * save it in the device structure.\n */\nstatic int\nget_ifname(struct vhost_device_ctx ctx, struct virtio_net *dev, int tap_fd, int pid)\n{\n\tint fd_tap;\n\tstruct ifreq ifr;\n\tuint32_t ifr_size;\n\tint ret;\n\n\tfd_tap = eventfd_copy(tap_fd, pid);\n\tif (fd_tap < 0)\n\t\treturn -1;\n\n\tret = ioctl(fd_tap, TUNGETIFF, &ifr);\n\n\tif (close(fd_tap) < 0)\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") fd close failed\\n\",\n\t\t\tdev->device_fh);\n\n\tif (ret >= 0) {\n\t\tifr_size = strnlen(ifr.ifr_name, sizeof(ifr.ifr_name));\n\t\tops->set_ifname(ctx, ifr.ifr_name, ifr_size);\n\t} else\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") TUNGETIFF ioctl failed\\n\",\n\t\t\tdev->device_fh);\n\n\treturn 0;\n}\n\nint cuse_set_backend(struct vhost_device_ctx ctx, struct vhost_vring_file *file)\n{\n\tstruct virtio_net *dev;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\n\tif (!(dev->flags & VIRTIO_DEV_RUNNING) && file->fd != VIRTIO_DEV_STOPPED)\n\t\tget_ifname(ctx, dev, file->fd, ctx.pid);\n\n\treturn ops->set_backend(ctx, file);\n}\n" }, { "path": "lib/librte_vhost/vhost_cuse/virtio-net-cdev.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n#ifndef _VIRTIO_NET_CDEV_H\n#define _VIRTIO_NET_CDEV_H\n\n#include \n#include \n\n#include \"vhost-net.h\"\n\nint\ncuse_set_mem_table(struct vhost_device_ctx ctx,\n\tconst struct vhost_memory *mem_regions_addr, uint32_t nregions);\n\nint\ncuse_set_backend(struct vhost_device_ctx ctx, struct vhost_vring_file *);\n\n#endif\n" }, { "path": "lib/librte_vhost/vhost_rxtx.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n\n#include \n#include \n#include \n\n#include \"vhost-net.h\"\n\n#define MAX_PKT_BURST 32\n\n/**\n * This function adds buffers to the virtio devices RX virtqueue. Buffers can\n * be received from the physical port or from another virtio device. A packet\n * count is returned to indicate the number of packets that are succesfully\n * added to the RX queue. This function works when the mbuf is scattered, but\n * it doesn't support the mergeable feature.\n */\nstatic inline uint32_t __attribute__((always_inline))\nvirtio_dev_rx(struct virtio_net *dev, uint16_t queue_id,\n\tstruct rte_mbuf **pkts, uint32_t count)\n{\n\tstruct vhost_virtqueue *vq;\n\tstruct vring_desc *desc;\n\tstruct rte_mbuf *buff;\n\t/* The virtio_hdr is initialised to 0. */\n\tstruct virtio_net_hdr_mrg_rxbuf virtio_hdr = {{0, 0, 0, 0, 0, 0}, 0};\n\tuint64_t buff_addr = 0;\n\tuint64_t buff_hdr_addr = 0;\n\tuint32_t head[MAX_PKT_BURST];\n\tuint32_t head_idx, packet_success = 0;\n\tuint16_t avail_idx, res_cur_idx;\n\tuint16_t res_base_idx, res_end_idx;\n\tuint16_t free_entries;\n\tuint8_t success = 0;\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") virtio_dev_rx()\\n\", dev->device_fh);\n\tif (unlikely(queue_id != VIRTIO_RXQ)) {\n\t\tLOG_DEBUG(VHOST_DATA, \"mq isn't supported in this version.\\n\");\n\t\treturn 0;\n\t}\n\n\tvq = dev->virtqueue[VIRTIO_RXQ];\n\tcount = (count > MAX_PKT_BURST) ? MAX_PKT_BURST : count;\n\n\t/*\n\t * As many data cores may want access to available buffers,\n\t * they need to be reserved.\n\t */\n\tdo {\n\t\tres_base_idx = vq->last_used_idx_res;\n\t\tavail_idx = *((volatile uint16_t *)&vq->avail->idx);\n\n\t\tfree_entries = (avail_idx - res_base_idx);\n\t\t/*check that we have enough buffers*/\n\t\tif (unlikely(count > free_entries))\n\t\t\tcount = free_entries;\n\n\t\tif (count == 0)\n\t\t\treturn 0;\n\n\t\tres_end_idx = res_base_idx + count;\n\t\t/* vq->last_used_idx_res is atomically updated. */\n\t\t/* TODO: Allow to disable cmpset if no concurrency in application. */\n\t\tsuccess = rte_atomic16_cmpset(&vq->last_used_idx_res,\n\t\t\t\tres_base_idx, res_end_idx);\n\t} while (unlikely(success == 0));\n\tres_cur_idx = res_base_idx;\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") Current Index %d| End Index %d\\n\",\n\t\t\tdev->device_fh, res_cur_idx, res_end_idx);\n\n\t/* Prefetch available ring to retrieve indexes. */\n\trte_prefetch0(&vq->avail->ring[res_cur_idx & (vq->size - 1)]);\n\n\t/* Retrieve all of the head indexes first to avoid caching issues. */\n\tfor (head_idx = 0; head_idx < count; head_idx++)\n\t\thead[head_idx] = vq->avail->ring[(res_cur_idx + head_idx) &\n\t\t\t\t\t(vq->size - 1)];\n\n\t/*Prefetch descriptor index. */\n\trte_prefetch0(&vq->desc[head[packet_success]]);\n\n\twhile (res_cur_idx != res_end_idx) {\n\t\tuint32_t offset = 0, vb_offset = 0;\n\t\tuint32_t pkt_len, len_to_cpy, data_len, total_copied = 0;\n\t\tuint8_t hdr = 0, uncompleted_pkt = 0;\n\n\t\t/* Get descriptor from available ring */\n\t\tdesc = &vq->desc[head[packet_success]];\n\n\t\tbuff = pkts[packet_success];\n\n\t\t/* Convert from gpa to vva (guest physical addr -> vhost virtual addr) */\n\t\tbuff_addr = gpa_to_vva(dev, desc->addr);\n\t\t/* Prefetch buffer address. */\n\t\trte_prefetch0((void *)(uintptr_t)buff_addr);\n\n\t\t/* Copy virtio_hdr to packet and increment buffer address */\n\t\tbuff_hdr_addr = buff_addr;\n\n\t\t/*\n\t\t * If the descriptors are chained the header and data are\n\t\t * placed in separate buffers.\n\t\t */\n\t\tif ((desc->flags & VRING_DESC_F_NEXT) &&\n\t\t\t(desc->len == vq->vhost_hlen)) {\n\t\t\tdesc = &vq->desc[desc->next];\n\t\t\t/* Buffer address translation. */\n\t\t\tbuff_addr = gpa_to_vva(dev, desc->addr);\n\t\t} else {\n\t\t\tvb_offset += vq->vhost_hlen;\n\t\t\thdr = 1;\n\t\t}\n\n\t\tpkt_len = rte_pktmbuf_pkt_len(buff);\n\t\tdata_len = rte_pktmbuf_data_len(buff);\n\t\tlen_to_cpy = RTE_MIN(data_len,\n\t\t\thdr ? desc->len - vq->vhost_hlen : desc->len);\n\t\twhile (total_copied < pkt_len) {\n\t\t\t/* Copy mbuf data to buffer */\n\t\t\trte_memcpy((void *)(uintptr_t)(buff_addr + vb_offset),\n\t\t\t\trte_pktmbuf_mtod_offset(buff, const void *, offset),\n\t\t\t\tlen_to_cpy);\n\t\t\tPRINT_PACKET(dev, (uintptr_t)(buff_addr + vb_offset),\n\t\t\t\tlen_to_cpy, 0);\n\n\t\t\toffset += len_to_cpy;\n\t\t\tvb_offset += len_to_cpy;\n\t\t\ttotal_copied += len_to_cpy;\n\n\t\t\t/* The whole packet completes */\n\t\t\tif (total_copied == pkt_len)\n\t\t\t\tbreak;\n\n\t\t\t/* The current segment completes */\n\t\t\tif (offset == data_len) {\n\t\t\t\tbuff = buff->next;\n\t\t\t\toffset = 0;\n\t\t\t\tdata_len = rte_pktmbuf_data_len(buff);\n\t\t\t}\n\n\t\t\t/* The current vring descriptor done */\n\t\t\tif (vb_offset == desc->len) {\n\t\t\t\tif (desc->flags & VRING_DESC_F_NEXT) {\n\t\t\t\t\tdesc = &vq->desc[desc->next];\n\t\t\t\t\tbuff_addr = gpa_to_vva(dev, desc->addr);\n\t\t\t\t\tvb_offset = 0;\n\t\t\t\t} else {\n\t\t\t\t\t/* Room in vring buffer is not enough */\n\t\t\t\t\tuncompleted_pkt = 1;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\tlen_to_cpy = RTE_MIN(data_len - offset, desc->len - vb_offset);\n\t\t};\n\n\t\t/* Update used ring with desc information */\n\t\tvq->used->ring[res_cur_idx & (vq->size - 1)].id =\n\t\t\t\t\t\t\thead[packet_success];\n\n\t\t/* Drop the packet if it is uncompleted */\n\t\tif (unlikely(uncompleted_pkt == 1))\n\t\t\tvq->used->ring[res_cur_idx & (vq->size - 1)].len =\n\t\t\t\t\t\t\tvq->vhost_hlen;\n\t\telse\n\t\t\tvq->used->ring[res_cur_idx & (vq->size - 1)].len =\n\t\t\t\t\t\t\tpkt_len + vq->vhost_hlen;\n\n\t\tres_cur_idx++;\n\t\tpacket_success++;\n\n\t\tif (unlikely(uncompleted_pkt == 1))\n\t\t\tcontinue;\n\n\t\trte_memcpy((void *)(uintptr_t)buff_hdr_addr,\n\t\t\t(const void *)&virtio_hdr, vq->vhost_hlen);\n\n\t\tPRINT_PACKET(dev, (uintptr_t)buff_hdr_addr, vq->vhost_hlen, 1);\n\n\t\tif (res_cur_idx < res_end_idx) {\n\t\t\t/* Prefetch descriptor index. */\n\t\t\trte_prefetch0(&vq->desc[head[packet_success]]);\n\t\t}\n\t}\n\n\trte_compiler_barrier();\n\n\t/* Wait until it's our turn to add our buffer to the used ring. */\n\twhile (unlikely(vq->last_used_idx != res_base_idx))\n\t\trte_pause();\n\n\t*(volatile uint16_t *)&vq->used->idx += count;\n\tvq->last_used_idx = res_end_idx;\n\n\t/* flush used->idx update before we read avail->flags. */\n\trte_mb();\n\n\t/* Kick the guest if necessary. */\n\tif (!(vq->avail->flags & VRING_AVAIL_F_NO_INTERRUPT))\n\t\teventfd_write((int)vq->callfd, 1);\n\treturn count;\n}\n\nstatic inline uint32_t __attribute__((always_inline))\ncopy_from_mbuf_to_vring(struct virtio_net *dev, uint16_t res_base_idx,\n\tuint16_t res_end_idx, struct rte_mbuf *pkt)\n{\n\tuint32_t vec_idx = 0;\n\tuint32_t entry_success = 0;\n\tstruct vhost_virtqueue *vq;\n\t/* The virtio_hdr is initialised to 0. */\n\tstruct virtio_net_hdr_mrg_rxbuf virtio_hdr = {\n\t\t{0, 0, 0, 0, 0, 0}, 0};\n\tuint16_t cur_idx = res_base_idx;\n\tuint64_t vb_addr = 0;\n\tuint64_t vb_hdr_addr = 0;\n\tuint32_t seg_offset = 0;\n\tuint32_t vb_offset = 0;\n\tuint32_t seg_avail;\n\tuint32_t vb_avail;\n\tuint32_t cpy_len, entry_len;\n\n\tif (pkt == NULL)\n\t\treturn 0;\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") Current Index %d| \"\n\t\t\"End Index %d\\n\",\n\t\tdev->device_fh, cur_idx, res_end_idx);\n\n\t/*\n\t * Convert from gpa to vva\n\t * (guest physical addr -> vhost virtual addr)\n\t */\n\tvq = dev->virtqueue[VIRTIO_RXQ];\n\tvb_addr = gpa_to_vva(dev, vq->buf_vec[vec_idx].buf_addr);\n\tvb_hdr_addr = vb_addr;\n\n\t/* Prefetch buffer address. */\n\trte_prefetch0((void *)(uintptr_t)vb_addr);\n\n\tvirtio_hdr.num_buffers = res_end_idx - res_base_idx;\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") RX: Num merge buffers %d\\n\",\n\t\tdev->device_fh, virtio_hdr.num_buffers);\n\n\trte_memcpy((void *)(uintptr_t)vb_hdr_addr,\n\t\t(const void *)&virtio_hdr, vq->vhost_hlen);\n\n\tPRINT_PACKET(dev, (uintptr_t)vb_hdr_addr, vq->vhost_hlen, 1);\n\n\tseg_avail = rte_pktmbuf_data_len(pkt);\n\tvb_offset = vq->vhost_hlen;\n\tvb_avail = vq->buf_vec[vec_idx].buf_len - vq->vhost_hlen;\n\n\tentry_len = vq->vhost_hlen;\n\n\tif (vb_avail == 0) {\n\t\tuint32_t desc_idx =\n\t\t\tvq->buf_vec[vec_idx].desc_idx;\n\n\t\tif ((vq->desc[desc_idx].flags\n\t\t\t& VRING_DESC_F_NEXT) == 0) {\n\t\t\t/* Update used ring with desc information */\n\t\t\tvq->used->ring[cur_idx & (vq->size - 1)].id\n\t\t\t\t= vq->buf_vec[vec_idx].desc_idx;\n\t\t\tvq->used->ring[cur_idx & (vq->size - 1)].len\n\t\t\t\t= entry_len;\n\n\t\t\tentry_len = 0;\n\t\t\tcur_idx++;\n\t\t\tentry_success++;\n\t\t}\n\n\t\tvec_idx++;\n\t\tvb_addr = gpa_to_vva(dev, vq->buf_vec[vec_idx].buf_addr);\n\n\t\t/* Prefetch buffer address. */\n\t\trte_prefetch0((void *)(uintptr_t)vb_addr);\n\t\tvb_offset = 0;\n\t\tvb_avail = vq->buf_vec[vec_idx].buf_len;\n\t}\n\n\tcpy_len = RTE_MIN(vb_avail, seg_avail);\n\n\twhile (cpy_len > 0) {\n\t\t/* Copy mbuf data to vring buffer */\n\t\trte_memcpy((void *)(uintptr_t)(vb_addr + vb_offset),\n\t\t\trte_pktmbuf_mtod_offset(pkt, const void *, seg_offset),\n\t\t\tcpy_len);\n\n\t\tPRINT_PACKET(dev,\n\t\t\t(uintptr_t)(vb_addr + vb_offset),\n\t\t\tcpy_len, 0);\n\n\t\tseg_offset += cpy_len;\n\t\tvb_offset += cpy_len;\n\t\tseg_avail -= cpy_len;\n\t\tvb_avail -= cpy_len;\n\t\tentry_len += cpy_len;\n\n\t\tif (seg_avail != 0) {\n\t\t\t/*\n\t\t\t * The virtio buffer in this vring\n\t\t\t * entry reach to its end.\n\t\t\t * But the segment doesn't complete.\n\t\t\t */\n\t\t\tif ((vq->desc[vq->buf_vec[vec_idx].desc_idx].flags &\n\t\t\t\tVRING_DESC_F_NEXT) == 0) {\n\t\t\t\t/* Update used ring with desc information */\n\t\t\t\tvq->used->ring[cur_idx & (vq->size - 1)].id\n\t\t\t\t\t= vq->buf_vec[vec_idx].desc_idx;\n\t\t\t\tvq->used->ring[cur_idx & (vq->size - 1)].len\n\t\t\t\t\t= entry_len;\n\t\t\t\tentry_len = 0;\n\t\t\t\tcur_idx++;\n\t\t\t\tentry_success++;\n\t\t\t}\n\n\t\t\tvec_idx++;\n\t\t\tvb_addr = gpa_to_vva(dev,\n\t\t\t\tvq->buf_vec[vec_idx].buf_addr);\n\t\t\tvb_offset = 0;\n\t\t\tvb_avail = vq->buf_vec[vec_idx].buf_len;\n\t\t\tcpy_len = RTE_MIN(vb_avail, seg_avail);\n\t\t} else {\n\t\t\t/*\n\t\t\t * This current segment complete, need continue to\n\t\t\t * check if the whole packet complete or not.\n\t\t\t */\n\t\t\tpkt = pkt->next;\n\t\t\tif (pkt != NULL) {\n\t\t\t\t/*\n\t\t\t\t * There are more segments.\n\t\t\t\t */\n\t\t\t\tif (vb_avail == 0) {\n\t\t\t\t\t/*\n\t\t\t\t\t * This current buffer from vring is\n\t\t\t\t\t * used up, need fetch next buffer\n\t\t\t\t\t * from buf_vec.\n\t\t\t\t\t */\n\t\t\t\t\tuint32_t desc_idx =\n\t\t\t\t\t\tvq->buf_vec[vec_idx].desc_idx;\n\n\t\t\t\t\tif ((vq->desc[desc_idx].flags &\n\t\t\t\t\t\tVRING_DESC_F_NEXT) == 0) {\n\t\t\t\t\t\tuint16_t wrapped_idx =\n\t\t\t\t\t\t\tcur_idx & (vq->size - 1);\n\t\t\t\t\t\t/*\n\t\t\t\t\t\t * Update used ring with the\n\t\t\t\t\t\t * descriptor information\n\t\t\t\t\t\t */\n\t\t\t\t\t\tvq->used->ring[wrapped_idx].id\n\t\t\t\t\t\t\t= desc_idx;\n\t\t\t\t\t\tvq->used->ring[wrapped_idx].len\n\t\t\t\t\t\t\t= entry_len;\n\t\t\t\t\t\tentry_success++;\n\t\t\t\t\t\tentry_len = 0;\n\t\t\t\t\t\tcur_idx++;\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Get next buffer from buf_vec. */\n\t\t\t\t\tvec_idx++;\n\t\t\t\t\tvb_addr = gpa_to_vva(dev,\n\t\t\t\t\t\tvq->buf_vec[vec_idx].buf_addr);\n\t\t\t\t\tvb_avail =\n\t\t\t\t\t\tvq->buf_vec[vec_idx].buf_len;\n\t\t\t\t\tvb_offset = 0;\n\t\t\t\t}\n\n\t\t\t\tseg_offset = 0;\n\t\t\t\tseg_avail = rte_pktmbuf_data_len(pkt);\n\t\t\t\tcpy_len = RTE_MIN(vb_avail, seg_avail);\n\t\t\t} else {\n\t\t\t\t/*\n\t\t\t\t * This whole packet completes.\n\t\t\t\t */\n\t\t\t\t/* Update used ring with desc information */\n\t\t\t\tvq->used->ring[cur_idx & (vq->size - 1)].id\n\t\t\t\t\t= vq->buf_vec[vec_idx].desc_idx;\n\t\t\t\tvq->used->ring[cur_idx & (vq->size - 1)].len\n\t\t\t\t\t= entry_len;\n\t\t\t\tentry_success++;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n\n\treturn entry_success;\n}\n\nstatic inline void __attribute__((always_inline))\nupdate_secure_len(struct vhost_virtqueue *vq, uint32_t id,\n\tuint32_t *secure_len, uint32_t *vec_idx)\n{\n\tuint16_t wrapped_idx = id & (vq->size - 1);\n\tuint32_t idx = vq->avail->ring[wrapped_idx];\n\tuint8_t next_desc;\n\tuint32_t len = *secure_len;\n\tuint32_t vec_id = *vec_idx;\n\n\tdo {\n\t\tnext_desc = 0;\n\t\tlen += vq->desc[idx].len;\n\t\tvq->buf_vec[vec_id].buf_addr = vq->desc[idx].addr;\n\t\tvq->buf_vec[vec_id].buf_len = vq->desc[idx].len;\n\t\tvq->buf_vec[vec_id].desc_idx = idx;\n\t\tvec_id++;\n\n\t\tif (vq->desc[idx].flags & VRING_DESC_F_NEXT) {\n\t\t\tidx = vq->desc[idx].next;\n\t\t\tnext_desc = 1;\n\t\t}\n\t} while (next_desc);\n\n\t*secure_len = len;\n\t*vec_idx = vec_id;\n}\n\n/*\n * This function works for mergeable RX.\n */\nstatic inline uint32_t __attribute__((always_inline))\nvirtio_dev_merge_rx(struct virtio_net *dev, uint16_t queue_id,\n\tstruct rte_mbuf **pkts, uint32_t count)\n{\n\tstruct vhost_virtqueue *vq;\n\tuint32_t pkt_idx = 0, entry_success = 0;\n\tuint16_t avail_idx;\n\tuint16_t res_base_idx, res_cur_idx;\n\tuint8_t success = 0;\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") virtio_dev_merge_rx()\\n\",\n\t\tdev->device_fh);\n\tif (unlikely(queue_id != VIRTIO_RXQ)) {\n\t\tLOG_DEBUG(VHOST_DATA, \"mq isn't supported in this version.\\n\");\n\t}\n\n\tvq = dev->virtqueue[VIRTIO_RXQ];\n\tcount = RTE_MIN((uint32_t)MAX_PKT_BURST, count);\n\n\tif (count == 0)\n\t\treturn 0;\n\n\tfor (pkt_idx = 0; pkt_idx < count; pkt_idx++) {\n\t\tuint32_t pkt_len = pkts[pkt_idx]->pkt_len + vq->vhost_hlen;\n\n\t\tdo {\n\t\t\t/*\n\t\t\t * As many data cores may want access to available\n\t\t\t * buffers, they need to be reserved.\n\t\t\t */\n\t\t\tuint32_t secure_len = 0;\n\t\t\tuint32_t vec_idx = 0;\n\n\t\t\tres_base_idx = vq->last_used_idx_res;\n\t\t\tres_cur_idx = res_base_idx;\n\n\t\t\tdo {\n\t\t\t\tavail_idx = *((volatile uint16_t *)&vq->avail->idx);\n\t\t\t\tif (unlikely(res_cur_idx == avail_idx)) {\n\t\t\t\t\tLOG_DEBUG(VHOST_DATA,\n\t\t\t\t\t\t\"(%\"PRIu64\") Failed \"\n\t\t\t\t\t\t\"to get enough desc from \"\n\t\t\t\t\t\t\"vring\\n\",\n\t\t\t\t\t\tdev->device_fh);\n\t\t\t\t\treturn pkt_idx;\n\t\t\t\t} else {\n\t\t\t\t\tupdate_secure_len(vq, res_cur_idx, &secure_len, &vec_idx);\n\t\t\t\t\tres_cur_idx++;\n\t\t\t\t}\n\t\t\t} while (pkt_len > secure_len);\n\n\t\t\t/* vq->last_used_idx_res is atomically updated. */\n\t\t\tsuccess = rte_atomic16_cmpset(&vq->last_used_idx_res,\n\t\t\t\t\t\t\tres_base_idx,\n\t\t\t\t\t\t\tres_cur_idx);\n\t\t} while (success == 0);\n\n\t\tentry_success = copy_from_mbuf_to_vring(dev, res_base_idx,\n\t\t\tres_cur_idx, pkts[pkt_idx]);\n\n\t\trte_compiler_barrier();\n\n\t\t/*\n\t\t * Wait until it's our turn to add our buffer\n\t\t * to the used ring.\n\t\t */\n\t\twhile (unlikely(vq->last_used_idx != res_base_idx))\n\t\t\trte_pause();\n\n\t\t*(volatile uint16_t *)&vq->used->idx += entry_success;\n\t\tvq->last_used_idx = res_cur_idx;\n\n\t\t/* flush used->idx update before we read avail->flags. */\n\t\trte_mb();\n\n\t\t/* Kick the guest if necessary. */\n\t\tif (!(vq->avail->flags & VRING_AVAIL_F_NO_INTERRUPT))\n\t\t\teventfd_write((int)vq->callfd, 1);\n\t}\n\n\treturn count;\n}\n\nuint16_t\nrte_vhost_enqueue_burst(struct virtio_net *dev, uint16_t queue_id,\n\tstruct rte_mbuf **pkts, uint16_t count)\n{\n\tif (unlikely(dev->features & (1 << VIRTIO_NET_F_MRG_RXBUF)))\n\t\treturn virtio_dev_merge_rx(dev, queue_id, pkts, count);\n\telse\n\t\treturn virtio_dev_rx(dev, queue_id, pkts, count);\n}\n\nuint16_t\nrte_vhost_dequeue_burst(struct virtio_net *dev, uint16_t queue_id,\n\tstruct rte_mempool *mbuf_pool, struct rte_mbuf **pkts, uint16_t count)\n{\n\tstruct rte_mbuf *m, *prev;\n\tstruct vhost_virtqueue *vq;\n\tstruct vring_desc *desc;\n\tuint64_t vb_addr = 0;\n\tuint32_t head[MAX_PKT_BURST];\n\tuint32_t used_idx;\n\tuint32_t i;\n\tuint16_t free_entries, entry_success = 0;\n\tuint16_t avail_idx;\n\n\tif (unlikely(queue_id != VIRTIO_TXQ)) {\n\t\tLOG_DEBUG(VHOST_DATA, \"mq isn't supported in this version.\\n\");\n\t\treturn 0;\n\t}\n\n\tvq = dev->virtqueue[VIRTIO_TXQ];\n\tavail_idx = *((volatile uint16_t *)&vq->avail->idx);\n\n\t/* If there are no available buffers then return. */\n\tif (vq->last_used_idx == avail_idx)\n\t\treturn 0;\n\n\tLOG_DEBUG(VHOST_DATA, \"%s (%\"PRIu64\")\\n\", __func__,\n\t\tdev->device_fh);\n\n\t/* Prefetch available ring to retrieve head indexes. */\n\trte_prefetch0(&vq->avail->ring[vq->last_used_idx & (vq->size - 1)]);\n\n\t/*get the number of free entries in the ring*/\n\tfree_entries = (avail_idx - vq->last_used_idx);\n\n\tfree_entries = RTE_MIN(free_entries, count);\n\t/* Limit to MAX_PKT_BURST. */\n\tfree_entries = RTE_MIN(free_entries, MAX_PKT_BURST);\n\n\tLOG_DEBUG(VHOST_DATA, \"(%\"PRIu64\") Buffers available %d\\n\",\n\t\t\tdev->device_fh, free_entries);\n\t/* Retrieve all of the head indexes first to avoid caching issues. */\n\tfor (i = 0; i < free_entries; i++)\n\t\thead[i] = vq->avail->ring[(vq->last_used_idx + i) & (vq->size - 1)];\n\n\t/* Prefetch descriptor index. */\n\trte_prefetch0(&vq->desc[head[entry_success]]);\n\trte_prefetch0(&vq->used->ring[vq->last_used_idx & (vq->size - 1)]);\n\n\twhile (entry_success < free_entries) {\n\t\tuint32_t vb_avail, vb_offset;\n\t\tuint32_t seg_avail, seg_offset;\n\t\tuint32_t cpy_len;\n\t\tuint32_t seg_num = 0;\n\t\tstruct rte_mbuf *cur;\n\t\tuint8_t alloc_err = 0;\n\n\t\tdesc = &vq->desc[head[entry_success]];\n\n\t\t/* Discard first buffer as it is the virtio header */\n\t\tif (desc->flags & VRING_DESC_F_NEXT) {\n\t\t\tdesc = &vq->desc[desc->next];\n\t\t\tvb_offset = 0;\n\t\t\tvb_avail = desc->len;\n\t\t} else {\n\t\t\tvb_offset = vq->vhost_hlen;\n\t\t\tvb_avail = desc->len - vb_offset;\n\t\t}\n\n\t\t/* Buffer address translation. */\n\t\tvb_addr = gpa_to_vva(dev, desc->addr);\n\t\t/* Prefetch buffer address. */\n\t\trte_prefetch0((void *)(uintptr_t)vb_addr);\n\n\t\tused_idx = vq->last_used_idx & (vq->size - 1);\n\n\t\tif (entry_success < (free_entries - 1)) {\n\t\t\t/* Prefetch descriptor index. */\n\t\t\trte_prefetch0(&vq->desc[head[entry_success+1]]);\n\t\t\trte_prefetch0(&vq->used->ring[(used_idx + 1) & (vq->size - 1)]);\n\t\t}\n\n\t\t/* Update used index buffer information. */\n\t\tvq->used->ring[used_idx].id = head[entry_success];\n\t\tvq->used->ring[used_idx].len = 0;\n\n\t\t/* Allocate an mbuf and populate the structure. */\n\t\tm = rte_pktmbuf_alloc(mbuf_pool);\n\t\tif (unlikely(m == NULL)) {\n\t\t\tRTE_LOG(ERR, VHOST_DATA,\n\t\t\t\t\"Failed to allocate memory for mbuf.\\n\");\n\t\t\tbreak;\n\t\t}\n\t\tseg_offset = 0;\n\t\tseg_avail = m->buf_len - RTE_PKTMBUF_HEADROOM;\n\t\tcpy_len = RTE_MIN(vb_avail, seg_avail);\n\n\t\tPRINT_PACKET(dev, (uintptr_t)vb_addr, desc->len, 0);\n\n\t\tseg_num++;\n\t\tcur = m;\n\t\tprev = m;\n\t\twhile (cpy_len != 0) {\n\t\t\trte_memcpy(rte_pktmbuf_mtod_offset(cur, void *, seg_offset),\n\t\t\t\t(void *)((uintptr_t)(vb_addr + vb_offset)),\n\t\t\t\tcpy_len);\n\n\t\t\tseg_offset += cpy_len;\n\t\t\tvb_offset += cpy_len;\n\t\t\tvb_avail -= cpy_len;\n\t\t\tseg_avail -= cpy_len;\n\n\t\t\tif (vb_avail != 0) {\n\t\t\t\t/*\n\t\t\t\t * The segment reachs to its end,\n\t\t\t\t * while the virtio buffer in TX vring has\n\t\t\t\t * more data to be copied.\n\t\t\t\t */\n\t\t\t\tcur->data_len = seg_offset;\n\t\t\t\tm->pkt_len += seg_offset;\n\t\t\t\t/* Allocate mbuf and populate the structure. */\n\t\t\t\tcur = rte_pktmbuf_alloc(mbuf_pool);\n\t\t\t\tif (unlikely(cur == NULL)) {\n\t\t\t\t\tRTE_LOG(ERR, VHOST_DATA, \"Failed to \"\n\t\t\t\t\t\t\"allocate memory for mbuf.\\n\");\n\t\t\t\t\trte_pktmbuf_free(m);\n\t\t\t\t\talloc_err = 1;\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\tseg_num++;\n\t\t\t\tprev->next = cur;\n\t\t\t\tprev = cur;\n\t\t\t\tseg_offset = 0;\n\t\t\t\tseg_avail = cur->buf_len - RTE_PKTMBUF_HEADROOM;\n\t\t\t} else {\n\t\t\t\tif (desc->flags & VRING_DESC_F_NEXT) {\n\t\t\t\t\t/*\n\t\t\t\t\t * There are more virtio buffers in\n\t\t\t\t\t * same vring entry need to be copied.\n\t\t\t\t\t */\n\t\t\t\t\tif (seg_avail == 0) {\n\t\t\t\t\t\t/*\n\t\t\t\t\t\t * The current segment hasn't\n\t\t\t\t\t\t * room to accomodate more\n\t\t\t\t\t\t * data.\n\t\t\t\t\t\t */\n\t\t\t\t\t\tcur->data_len = seg_offset;\n\t\t\t\t\t\tm->pkt_len += seg_offset;\n\t\t\t\t\t\t/*\n\t\t\t\t\t\t * Allocate an mbuf and\n\t\t\t\t\t\t * populate the structure.\n\t\t\t\t\t\t */\n\t\t\t\t\t\tcur = rte_pktmbuf_alloc(mbuf_pool);\n\t\t\t\t\t\tif (unlikely(cur == NULL)) {\n\t\t\t\t\t\t\tRTE_LOG(ERR,\n\t\t\t\t\t\t\t\tVHOST_DATA,\n\t\t\t\t\t\t\t\t\"Failed to \"\n\t\t\t\t\t\t\t\t\"allocate memory \"\n\t\t\t\t\t\t\t\t\"for mbuf\\n\");\n\t\t\t\t\t\t\trte_pktmbuf_free(m);\n\t\t\t\t\t\t\talloc_err = 1;\n\t\t\t\t\t\t\tbreak;\n\t\t\t\t\t\t}\n\t\t\t\t\t\tseg_num++;\n\t\t\t\t\t\tprev->next = cur;\n\t\t\t\t\t\tprev = cur;\n\t\t\t\t\t\tseg_offset = 0;\n\t\t\t\t\t\tseg_avail = cur->buf_len - RTE_PKTMBUF_HEADROOM;\n\t\t\t\t\t}\n\n\t\t\t\t\tdesc = &vq->desc[desc->next];\n\n\t\t\t\t\t/* Buffer address translation. */\n\t\t\t\t\tvb_addr = gpa_to_vva(dev, desc->addr);\n\t\t\t\t\t/* Prefetch buffer address. */\n\t\t\t\t\trte_prefetch0((void *)(uintptr_t)vb_addr);\n\t\t\t\t\tvb_offset = 0;\n\t\t\t\t\tvb_avail = desc->len;\n\n\t\t\t\t\tPRINT_PACKET(dev, (uintptr_t)vb_addr,\n\t\t\t\t\t\tdesc->len, 0);\n\t\t\t\t} else {\n\t\t\t\t\t/* The whole packet completes. */\n\t\t\t\t\tcur->data_len = seg_offset;\n\t\t\t\t\tm->pkt_len += seg_offset;\n\t\t\t\t\tvb_avail = 0;\n\t\t\t\t}\n\t\t\t}\n\n\t\t\tcpy_len = RTE_MIN(vb_avail, seg_avail);\n\t\t}\n\n\t\tif (unlikely(alloc_err == 1))\n\t\t\tbreak;\n\n\t\tm->nb_segs = seg_num;\n\n\t\tpkts[entry_success] = m;\n\t\tvq->last_used_idx++;\n\t\tentry_success++;\n\t}\n\n\trte_compiler_barrier();\n\tvq->used->idx += entry_success;\n\t/* Kick guest if required. */\n\tif (!(vq->avail->flags & VRING_AVAIL_F_NO_INTERRUPT))\n\t\teventfd_write((int)vq->callfd, 1);\n\treturn entry_success;\n}\n" }, { "path": "lib/librte_vhost/vhost_user/fd_man.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \"fd_man.h\"\n\n/**\n * Returns the index in the fdset for a given fd.\n * If fd is -1, it means to search for a free entry.\n * @return\n * index for the fd, or -1 if fd isn't in the fdset.\n */\nstatic int\nfdset_find_fd(struct fdset *pfdset, int fd)\n{\n\tint i;\n\n\tif (pfdset == NULL)\n\t\treturn -1;\n\n\tfor (i = 0; i < MAX_FDS && pfdset->fd[i].fd != fd; i++)\n\t\t;\n\n\treturn i == MAX_FDS ? -1 : i;\n}\n\nstatic int\nfdset_find_free_slot(struct fdset *pfdset)\n{\n\treturn fdset_find_fd(pfdset, -1);\n}\n\nstatic void\nfdset_add_fd(struct fdset *pfdset, int idx, int fd,\n\tfd_cb rcb, fd_cb wcb, void *dat)\n{\n\tstruct fdentry *pfdentry;\n\n\tif (pfdset == NULL || idx >= MAX_FDS)\n\t\treturn;\n\n\tpfdentry = &pfdset->fd[idx];\n\tpfdentry->fd = fd;\n\tpfdentry->rcb = rcb;\n\tpfdentry->wcb = wcb;\n\tpfdentry->dat = dat;\n}\n\n/**\n * Fill the read/write fd_set with the fds in the fdset.\n * @return\n * the maximum fds filled in the read/write fd_set.\n */\nstatic int\nfdset_fill(fd_set *rfset, fd_set *wfset, struct fdset *pfdset)\n{\n\tstruct fdentry *pfdentry;\n\tint i, maxfds = -1;\n\tint num = MAX_FDS;\n\n\tif (pfdset == NULL)\n\t\treturn -1;\n\n\tfor (i = 0; i < num; i++) {\n\t\tpfdentry = &pfdset->fd[i];\n\t\tif (pfdentry->fd != -1) {\n\t\t\tint added = 0;\n\t\t\tif (pfdentry->rcb && rfset) {\n\t\t\t\tFD_SET(pfdentry->fd, rfset);\n\t\t\t\tadded = 1;\n\t\t\t}\n\t\t\tif (pfdentry->wcb && wfset) {\n\t\t\t\tFD_SET(pfdentry->fd, wfset);\n\t\t\t\tadded = 1;\n\t\t\t}\n\t\t\tif (added)\n\t\t\t\tmaxfds = pfdentry->fd < maxfds ?\n\t\t\t\t\tmaxfds : pfdentry->fd;\n\t\t}\n\t}\n\treturn maxfds;\n}\n\nvoid\nfdset_init(struct fdset *pfdset)\n{\n\tint i;\n\n\tif (pfdset == NULL)\n\t\treturn;\n\n\tfor (i = 0; i < MAX_FDS; i++)\n\t\tpfdset->fd[i].fd = -1;\n\tpfdset->num = 0;\n}\n\n/**\n * Register the fd in the fdset with read/write handler and context.\n */\nint\nfdset_add(struct fdset *pfdset, int fd, fd_cb rcb, fd_cb wcb, void *dat)\n{\n\tint i;\n\n\tif (pfdset == NULL || fd == -1)\n\t\treturn -1;\n\n\tpthread_mutex_lock(&pfdset->fd_mutex);\n\n\t/* Find a free slot in the list. */\n\ti = fdset_find_free_slot(pfdset);\n\tif (i == -1)\n\t\treturn -2;\n\n\tfdset_add_fd(pfdset, i, fd, rcb, wcb, dat);\n\tpfdset->num++;\n\n\tpthread_mutex_unlock(&pfdset->fd_mutex);\n\n\treturn 0;\n}\n\n/**\n * Unregister the fd from the fdset.\n */\nvoid\nfdset_del(struct fdset *pfdset, int fd)\n{\n\tint i;\n\n\tif (pfdset == NULL || fd == -1)\n\t\treturn;\n\n\tdo {\n\t\tpthread_mutex_lock(&pfdset->fd_mutex);\n\n\t\ti = fdset_find_fd(pfdset, fd);\n\t\tif (i != -1 && pfdset->fd[i].busy == 0) {\n\t\t\t/* busy indicates r/wcb is executing! */\n\t\t\tpfdset->fd[i].fd = -1;\n\t\t\tpfdset->fd[i].rcb = pfdset->fd[i].wcb = NULL;\n\t\t\tpfdset->num--;\n\t\t\ti = -1;\n\t\t}\n\t\tpthread_mutex_unlock(&pfdset->fd_mutex);\n\t} while (i != -1);\n}\n\n/**\n * Unregister the fd at the specified slot from the fdset.\n */\nstatic void\nfdset_del_slot(struct fdset *pfdset, int index)\n{\n\tif (pfdset == NULL || index < 0 || index >= MAX_FDS)\n\t\treturn;\n\n\tpthread_mutex_lock(&pfdset->fd_mutex);\n\n\tpfdset->fd[index].fd = -1;\n\tpfdset->fd[index].rcb = pfdset->fd[index].wcb = NULL;\n\tpfdset->num--;\n\n\tpthread_mutex_unlock(&pfdset->fd_mutex);\n}\n\n/**\n * This functions runs in infinite blocking loop until there is no fd in\n * pfdset. It calls corresponding r/w handler if there is event on the fd.\n *\n * Before the callback is called, we set the flag to busy status; If other\n * thread(now rte_vhost_driver_unregister) calls fdset_del concurrently, it\n * will wait until the flag is reset to zero(which indicates the callback is\n * finished), then it could free the context after fdset_del.\n */\nvoid\nfdset_event_dispatch(struct fdset *pfdset)\n{\n\tfd_set rfds, wfds;\n\tint i, maxfds;\n\tstruct fdentry *pfdentry;\n\tint num = MAX_FDS;\n\tfd_cb rcb, wcb;\n\tvoid *dat;\n\tint fd;\n\tint remove1, remove2;\n\tint ret;\n\n\tif (pfdset == NULL)\n\t\treturn;\n\n\twhile (1) {\n\t\tstruct timeval tv;\n\t\ttv.tv_sec = 1;\n\t\ttv.tv_usec = 0;\n\t\tFD_ZERO(&rfds);\n\t\tFD_ZERO(&wfds);\n\t\tpthread_mutex_lock(&pfdset->fd_mutex);\n\n\t\tmaxfds = fdset_fill(&rfds, &wfds, pfdset);\n\n\t\tpthread_mutex_unlock(&pfdset->fd_mutex);\n\n\t\t/*\n\t\t * When select is blocked, other threads might unregister\n\t\t * listenfds from and register new listenfds into fdset.\n\t\t * When select returns, the entries for listenfds in the fdset\n\t\t * might have been updated. It is ok if there is unwanted call\n\t\t * for new listenfds.\n\t\t */\n\t\tret = select(maxfds + 1, &rfds, &wfds, NULL, &tv);\n\t\tif (ret <= 0)\n\t\t\tcontinue;\n\n\t\tfor (i = 0; i < num; i++) {\n\t\t\tremove1 = remove2 = 0;\n\t\t\tpthread_mutex_lock(&pfdset->fd_mutex);\n\t\t\tpfdentry = &pfdset->fd[i];\n\t\t\tfd = pfdentry->fd;\n\t\t\trcb = pfdentry->rcb;\n\t\t\twcb = pfdentry->wcb;\n\t\t\tdat = pfdentry->dat;\n\t\t\tpfdentry->busy = 1;\n\t\t\tpthread_mutex_unlock(&pfdset->fd_mutex);\n\t\t\tif (fd >= 0 && FD_ISSET(fd, &rfds) && rcb)\n\t\t\t\trcb(fd, dat, &remove1);\n\t\t\tif (fd >= 0 && FD_ISSET(fd, &wfds) && wcb)\n\t\t\t\twcb(fd, dat, &remove2);\n\t\t\tpfdentry->busy = 0;\n\t\t\t/*\n\t\t\t * fdset_del needs to check busy flag.\n\t\t\t * We don't allow fdset_del to be called in callback\n\t\t\t * directly.\n\t\t\t */\n\t\t\t/*\n\t\t\t * When we are to clean up the fd from fdset,\n\t\t\t * because the fd is closed in the cb,\n\t\t\t * the old fd val could be reused by when creates new\n\t\t\t * listen fd in another thread, we couldn't call\n\t\t\t * fd_set_del.\n\t\t\t */\n\t\t\tif (remove1 || remove2)\n\t\t\t\tfdset_del_slot(pfdset, i);\n\t\t}\n\t}\n}\n" }, { "path": "lib/librte_vhost/vhost_user/fd_man.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _FD_MAN_H_\n#define _FD_MAN_H_\n#include \n#include \n\n#define MAX_FDS 1024\n\ntypedef void (*fd_cb)(int fd, void *dat, int *remove);\n\nstruct fdentry {\n\tint fd;\t\t/* -1 indicates this entry is empty */\n\tfd_cb rcb;\t/* callback when this fd is readable. */\n\tfd_cb wcb;\t/* callback when this fd is writeable.*/\n\tvoid *dat;\t/* fd context */\n\tint busy;\t/* whether this entry is being used in cb. */\n};\n\nstruct fdset {\n\tstruct fdentry fd[MAX_FDS];\n\tpthread_mutex_t fd_mutex;\n\tint num;\t/* current fd number of this fdset */\n};\n\n\nvoid fdset_init(struct fdset *pfdset);\n\nint fdset_add(struct fdset *pfdset, int fd,\n\tfd_cb rcb, fd_cb wcb, void *dat);\n\nvoid fdset_del(struct fdset *pfdset, int fd);\n\nvoid fdset_event_dispatch(struct fdset *pfdset);\n\n#endif\n" }, { "path": "lib/librte_vhost/vhost_user/vhost-net-user.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \"fd_man.h\"\n#include \"vhost-net-user.h\"\n#include \"vhost-net.h\"\n#include \"virtio-net-user.h\"\n\n#define MAX_VIRTIO_BACKLOG 128\n\nstatic void vserver_new_vq_conn(int fd, void *data, int *remove);\nstatic void vserver_message_handler(int fd, void *dat, int *remove);\nstruct vhost_net_device_ops const *ops;\n\nstruct connfd_ctx {\n\tstruct vhost_server *vserver;\n\tuint32_t fh;\n};\n\n#define MAX_VHOST_SERVER 1024\nstruct _vhost_server {\n\tstruct vhost_server *server[MAX_VHOST_SERVER];\n\tstruct fdset fdset;\n\tint vserver_cnt;\n\tpthread_mutex_t server_mutex;\n};\n\nstatic struct _vhost_server g_vhost_server = {\n\t.fdset = {\n\t\t.fd = { [0 ... MAX_FDS - 1] = {-1, NULL, NULL, NULL, 0} },\n\t\t.fd_mutex = PTHREAD_MUTEX_INITIALIZER,\n\t\t.num = 0\n\t},\n\t.vserver_cnt = 0,\n\t.server_mutex = PTHREAD_MUTEX_INITIALIZER,\n};\n\nstatic const char *vhost_message_str[VHOST_USER_MAX] = {\n\t[VHOST_USER_NONE] = \"VHOST_USER_NONE\",\n\t[VHOST_USER_GET_FEATURES] = \"VHOST_USER_GET_FEATURES\",\n\t[VHOST_USER_SET_FEATURES] = \"VHOST_USER_SET_FEATURES\",\n\t[VHOST_USER_SET_OWNER] = \"VHOST_USER_SET_OWNER\",\n\t[VHOST_USER_RESET_OWNER] = \"VHOST_USER_RESET_OWNER\",\n\t[VHOST_USER_SET_MEM_TABLE] = \"VHOST_USER_SET_MEM_TABLE\",\n\t[VHOST_USER_SET_LOG_BASE] = \"VHOST_USER_SET_LOG_BASE\",\n\t[VHOST_USER_SET_LOG_FD] = \"VHOST_USER_SET_LOG_FD\",\n\t[VHOST_USER_SET_VRING_NUM] = \"VHOST_USER_SET_VRING_NUM\",\n\t[VHOST_USER_SET_VRING_ADDR] = \"VHOST_USER_SET_VRING_ADDR\",\n\t[VHOST_USER_SET_VRING_BASE] = \"VHOST_USER_SET_VRING_BASE\",\n\t[VHOST_USER_GET_VRING_BASE] = \"VHOST_USER_GET_VRING_BASE\",\n\t[VHOST_USER_SET_VRING_KICK] = \"VHOST_USER_SET_VRING_KICK\",\n\t[VHOST_USER_SET_VRING_CALL] = \"VHOST_USER_SET_VRING_CALL\",\n\t[VHOST_USER_SET_VRING_ERR] = \"VHOST_USER_SET_VRING_ERR\"\n};\n\n/**\n * Create a unix domain socket, bind to path and listen for connection.\n * @return\n * socket fd or -1 on failure\n */\nstatic int\nuds_socket(const char *path)\n{\n\tstruct sockaddr_un un;\n\tint sockfd;\n\tint ret;\n\n\tif (path == NULL)\n\t\treturn -1;\n\n\tsockfd = socket(AF_UNIX, SOCK_STREAM, 0);\n\tif (sockfd < 0)\n\t\treturn -1;\n\tRTE_LOG(INFO, VHOST_CONFIG, \"socket created, fd:%d\\n\", sockfd);\n\n\tmemset(&un, 0, sizeof(un));\n\tun.sun_family = AF_UNIX;\n\tsnprintf(un.sun_path, sizeof(un.sun_path), \"%s\", path);\n\tret = bind(sockfd, (struct sockaddr *)&un, sizeof(un));\n\tif (ret == -1) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG, \"fail to bind fd:%d, remove file:%s and try again.\\n\",\n\t\t\tsockfd, path);\n\t\tgoto err;\n\t}\n\tRTE_LOG(INFO, VHOST_CONFIG, \"bind to %s\\n\", path);\n\n\tret = listen(sockfd, MAX_VIRTIO_BACKLOG);\n\tif (ret == -1)\n\t\tgoto err;\n\n\treturn sockfd;\n\nerr:\n\tclose(sockfd);\n\treturn -1;\n}\n\n/* return bytes# of read on success or negative val on failure. */\nstatic int\nread_fd_message(int sockfd, char *buf, int buflen, int *fds, int fd_num)\n{\n\tstruct iovec iov;\n\tstruct msghdr msgh;\n\tsize_t fdsize = fd_num * sizeof(int);\n\tchar control[CMSG_SPACE(fdsize)];\n\tstruct cmsghdr *cmsg;\n\tint ret;\n\n\tmemset(&msgh, 0, sizeof(msgh));\n\tiov.iov_base = buf;\n\tiov.iov_len = buflen;\n\n\tmsgh.msg_iov = &iov;\n\tmsgh.msg_iovlen = 1;\n\tmsgh.msg_control = control;\n\tmsgh.msg_controllen = sizeof(control);\n\n\tret = recvmsg(sockfd, &msgh, 0);\n\tif (ret <= 0) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG, \"recvmsg failed\\n\");\n\t\treturn ret;\n\t}\n\n\tif (msgh.msg_flags & (MSG_TRUNC | MSG_CTRUNC)) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG, \"truncted msg\\n\");\n\t\treturn -1;\n\t}\n\n\tfor (cmsg = CMSG_FIRSTHDR(&msgh); cmsg != NULL;\n\t\tcmsg = CMSG_NXTHDR(&msgh, cmsg)) {\n\t\tif ((cmsg->cmsg_level == SOL_SOCKET) &&\n\t\t\t(cmsg->cmsg_type == SCM_RIGHTS)) {\n\t\t\tmemcpy(fds, CMSG_DATA(cmsg), fdsize);\n\t\t\tbreak;\n\t\t}\n\t}\n\n\treturn ret;\n}\n\n/* return bytes# of read on success or negative val on failure. */\nstatic int\nread_vhost_message(int sockfd, struct VhostUserMsg *msg)\n{\n\tint ret;\n\n\tret = read_fd_message(sockfd, (char *)msg, VHOST_USER_HDR_SIZE,\n\t\tmsg->fds, VHOST_MEMORY_MAX_NREGIONS);\n\tif (ret <= 0)\n\t\treturn ret;\n\n\tif (msg && msg->size) {\n\t\tif (msg->size > sizeof(msg->payload)) {\n\t\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\t\"invalid msg size: %d\\n\", msg->size);\n\t\t\treturn -1;\n\t\t}\n\t\tret = read(sockfd, &msg->payload, msg->size);\n\t\tif (ret <= 0)\n\t\t\treturn ret;\n\t\tif (ret != (int)msg->size) {\n\t\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\t\"read control message failed\\n\");\n\t\t\treturn -1;\n\t\t}\n\t}\n\n\treturn ret;\n}\n\nstatic int\nsend_fd_message(int sockfd, char *buf, int buflen, int *fds, int fd_num)\n{\n\n\tstruct iovec iov;\n\tstruct msghdr msgh;\n\tsize_t fdsize = fd_num * sizeof(int);\n\tchar control[CMSG_SPACE(fdsize)];\n\tstruct cmsghdr *cmsg;\n\tint ret;\n\n\tmemset(&msgh, 0, sizeof(msgh));\n\tiov.iov_base = buf;\n\tiov.iov_len = buflen;\n\n\tmsgh.msg_iov = &iov;\n\tmsgh.msg_iovlen = 1;\n\n\tif (fds && fd_num > 0) {\n\t\tmsgh.msg_control = control;\n\t\tmsgh.msg_controllen = sizeof(control);\n\t\tcmsg = CMSG_FIRSTHDR(&msgh);\n\t\tcmsg->cmsg_len = CMSG_LEN(fdsize);\n\t\tcmsg->cmsg_level = SOL_SOCKET;\n\t\tcmsg->cmsg_type = SCM_RIGHTS;\n\t\tmemcpy(CMSG_DATA(cmsg), fds, fdsize);\n\t} else {\n\t\tmsgh.msg_control = NULL;\n\t\tmsgh.msg_controllen = 0;\n\t}\n\n\tdo {\n\t\tret = sendmsg(sockfd, &msgh, 0);\n\t} while (ret < 0 && errno == EINTR);\n\n\tif (ret < 0) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG, \"sendmsg error\\n\");\n\t\treturn ret;\n\t}\n\n\treturn ret;\n}\n\nstatic int\nsend_vhost_message(int sockfd, struct VhostUserMsg *msg)\n{\n\tint ret;\n\n\tif (!msg)\n\t\treturn 0;\n\n\tmsg->flags &= ~VHOST_USER_VERSION_MASK;\n\tmsg->flags |= VHOST_USER_VERSION;\n\tmsg->flags |= VHOST_USER_REPLY_MASK;\n\n\tret = send_fd_message(sockfd, (char *)msg,\n\t\tVHOST_USER_HDR_SIZE + msg->size, NULL, 0);\n\n\treturn ret;\n}\n\n/* call back when there is new virtio connection. */\nstatic void\nvserver_new_vq_conn(int fd, void *dat, __rte_unused int *remove)\n{\n\tstruct vhost_server *vserver = (struct vhost_server *)dat;\n\tint conn_fd;\n\tstruct connfd_ctx *ctx;\n\tint fh;\n\tstruct vhost_device_ctx vdev_ctx = { (pid_t)0, 0 };\n\tunsigned int size;\n\n\tconn_fd = accept(fd, NULL, NULL);\n\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\"new virtio connection is %d\\n\", conn_fd);\n\tif (conn_fd < 0)\n\t\treturn;\n\n\tctx = calloc(1, sizeof(*ctx));\n\tif (ctx == NULL) {\n\t\tclose(conn_fd);\n\t\treturn;\n\t}\n\n\tfh = ops->new_device(vdev_ctx);\n\tif (fh == -1) {\n\t\tfree(ctx);\n\t\tclose(conn_fd);\n\t\treturn;\n\t}\n\n\tvdev_ctx.fh = fh;\n\tsize = strnlen(vserver->path, PATH_MAX);\n\tops->set_ifname(vdev_ctx, vserver->path,\n\t\tsize);\n\n\tRTE_LOG(INFO, VHOST_CONFIG, \"new device, handle is %d\\n\", fh);\n\n\tctx->vserver = vserver;\n\tctx->fh = fh;\n\tfdset_add(&g_vhost_server.fdset,\n\t\tconn_fd, vserver_message_handler, NULL, ctx);\n}\n\n/* callback when there is message on the connfd */\nstatic void\nvserver_message_handler(int connfd, void *dat, int *remove)\n{\n\tstruct vhost_device_ctx ctx;\n\tstruct connfd_ctx *cfd_ctx = (struct connfd_ctx *)dat;\n\tstruct VhostUserMsg msg;\n\tuint64_t features;\n\tint ret;\n\n\tctx.fh = cfd_ctx->fh;\n\tret = read_vhost_message(connfd, &msg);\n\tif (ret < 0) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"vhost read message failed\\n\");\n\n\t\tclose(connfd);\n\t\t*remove = 1;\n\t\tfree(cfd_ctx);\n\t\tuser_destroy_device(ctx);\n\t\tops->destroy_device(ctx);\n\n\t\treturn;\n\t} else if (ret == 0) {\n\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\"vhost peer closed\\n\");\n\n\t\tclose(connfd);\n\t\t*remove = 1;\n\t\tfree(cfd_ctx);\n\t\tuser_destroy_device(ctx);\n\t\tops->destroy_device(ctx);\n\n\t\treturn;\n\t}\n\tif (msg.request > VHOST_USER_MAX) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"vhost read incorrect message\\n\");\n\n\t\tclose(connfd);\n\t\t*remove = 1;\n\t\tfree(cfd_ctx);\n\t\tuser_destroy_device(ctx);\n\t\tops->destroy_device(ctx);\n\n\t\treturn;\n\t}\n\n\tRTE_LOG(INFO, VHOST_CONFIG, \"read message %s\\n\",\n\t\tvhost_message_str[msg.request]);\n\tswitch (msg.request) {\n\tcase VHOST_USER_GET_FEATURES:\n\t\tret = ops->get_features(ctx, &features);\n\t\tmsg.payload.u64 = features;\n\t\tmsg.size = sizeof(msg.payload.u64);\n\t\tsend_vhost_message(connfd, &msg);\n\t\tbreak;\n\tcase VHOST_USER_SET_FEATURES:\n\t\tfeatures = msg.payload.u64;\n\t\tops->set_features(ctx, &features);\n\t\tbreak;\n\n\tcase VHOST_USER_SET_OWNER:\n\t\tops->set_owner(ctx);\n\t\tbreak;\n\tcase VHOST_USER_RESET_OWNER:\n\t\tops->reset_owner(ctx);\n\t\tbreak;\n\n\tcase VHOST_USER_SET_MEM_TABLE:\n\t\tuser_set_mem_table(ctx, &msg);\n\t\tbreak;\n\n\tcase VHOST_USER_SET_LOG_BASE:\n\t\tRTE_LOG(INFO, VHOST_CONFIG, \"not implemented.\\n\");\n\tcase VHOST_USER_SET_LOG_FD:\n\t\tclose(msg.fds[0]);\n\t\tRTE_LOG(INFO, VHOST_CONFIG, \"not implemented.\\n\");\n\t\tbreak;\n\n\tcase VHOST_USER_SET_VRING_NUM:\n\t\tops->set_vring_num(ctx, &msg.payload.state);\n\t\tbreak;\n\tcase VHOST_USER_SET_VRING_ADDR:\n\t\tops->set_vring_addr(ctx, &msg.payload.addr);\n\t\tbreak;\n\tcase VHOST_USER_SET_VRING_BASE:\n\t\tops->set_vring_base(ctx, &msg.payload.state);\n\t\tbreak;\n\n\tcase VHOST_USER_GET_VRING_BASE:\n\t\tret = user_get_vring_base(ctx, &msg.payload.state);\n\t\tmsg.size = sizeof(msg.payload.state);\n\t\tsend_vhost_message(connfd, &msg);\n\t\tbreak;\n\n\tcase VHOST_USER_SET_VRING_KICK:\n\t\tuser_set_vring_kick(ctx, &msg);\n\t\tbreak;\n\tcase VHOST_USER_SET_VRING_CALL:\n\t\tuser_set_vring_call(ctx, &msg);\n\t\tbreak;\n\n\tcase VHOST_USER_SET_VRING_ERR:\n\t\tif (!(msg.payload.u64 & VHOST_USER_VRING_NOFD_MASK))\n\t\t\tclose(msg.fds[0]);\n\t\tRTE_LOG(INFO, VHOST_CONFIG, \"not implemented\\n\");\n\t\tbreak;\n\n\tdefault:\n\t\tbreak;\n\n\t}\n}\n\n/**\n * Creates and initialise the vhost server.\n */\nint\nrte_vhost_driver_register(const char *path)\n{\n\tstruct vhost_server *vserver;\n\n\tpthread_mutex_lock(&g_vhost_server.server_mutex);\n\tif (ops == NULL)\n\t\tops = get_virtio_net_callbacks();\n\n\tif (g_vhost_server.vserver_cnt == MAX_VHOST_SERVER) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"error: the number of servers reaches maximum\\n\");\n\t\tpthread_mutex_unlock(&g_vhost_server.server_mutex);\n\t\treturn -1;\n\t}\n\n\tvserver = calloc(sizeof(struct vhost_server), 1);\n\tif (vserver == NULL) {\n\t\tpthread_mutex_unlock(&g_vhost_server.server_mutex);\n\t\treturn -1;\n\t}\n\n\tvserver->listenfd = uds_socket(path);\n\tif (vserver->listenfd < 0) {\n\t\tfree(vserver);\n\t\tpthread_mutex_unlock(&g_vhost_server.server_mutex);\n\t\treturn -1;\n\t}\n\n\tvserver->path = strdup(path);\n\n\tfdset_add(&g_vhost_server.fdset, vserver->listenfd,\n\t\tvserver_new_vq_conn, NULL, vserver);\n\n\tg_vhost_server.server[g_vhost_server.vserver_cnt++] = vserver;\n\tpthread_mutex_unlock(&g_vhost_server.server_mutex);\n\n\treturn 0;\n}\n\n\n/**\n * Unregister the specified vhost server\n */\nint\nrte_vhost_driver_unregister(const char *path)\n{\n\tint i;\n\tint count;\n\n\tpthread_mutex_lock(&g_vhost_server.server_mutex);\n\n\tfor (i = 0; i < g_vhost_server.vserver_cnt; i++) {\n\t\tif (!strcmp(g_vhost_server.server[i]->path, path)) {\n\t\t\tfdset_del(&g_vhost_server.fdset,\n\t\t\t\tg_vhost_server.server[i]->listenfd);\n\n\t\t\tclose(g_vhost_server.server[i]->listenfd);\n\t\t\tfree(g_vhost_server.server[i]->path);\n\t\t\tfree(g_vhost_server.server[i]);\n\n\t\t\tunlink(path);\n\n\t\t\tcount = --g_vhost_server.vserver_cnt;\n\t\t\tg_vhost_server.server[i] = g_vhost_server.server[count];\n\t\t\tg_vhost_server.server[count] = NULL;\n\t\t\tpthread_mutex_unlock(&g_vhost_server.server_mutex);\n\n\t\t\treturn 0;\n\t\t}\n\t}\n\tpthread_mutex_unlock(&g_vhost_server.server_mutex);\n\n\treturn -1;\n}\n\nint\nrte_vhost_driver_session_start(void)\n{\n\tfdset_event_dispatch(&g_vhost_server.fdset);\n\treturn 0;\n}\n" }, { "path": "lib/librte_vhost/vhost_user/vhost-net-user.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VHOST_NET_USER_H\n#define _VHOST_NET_USER_H\n\n#include \n#include \n\n#include \"rte_virtio_net.h\"\n#include \"fd_man.h\"\n\nstruct vhost_server {\n\tchar *path; /**< The path the uds is bind to. */\n\tint listenfd; /**< The listener sockfd. */\n};\n\n/* refer to hw/virtio/vhost-user.c */\n\ntypedef enum VhostUserRequest {\n\tVHOST_USER_NONE = 0,\n\tVHOST_USER_GET_FEATURES = 1,\n\tVHOST_USER_SET_FEATURES = 2,\n\tVHOST_USER_SET_OWNER = 3,\n\tVHOST_USER_RESET_OWNER = 4,\n\tVHOST_USER_SET_MEM_TABLE = 5,\n\tVHOST_USER_SET_LOG_BASE = 6,\n\tVHOST_USER_SET_LOG_FD = 7,\n\tVHOST_USER_SET_VRING_NUM = 8,\n\tVHOST_USER_SET_VRING_ADDR = 9,\n\tVHOST_USER_SET_VRING_BASE = 10,\n\tVHOST_USER_GET_VRING_BASE = 11,\n\tVHOST_USER_SET_VRING_KICK = 12,\n\tVHOST_USER_SET_VRING_CALL = 13,\n\tVHOST_USER_SET_VRING_ERR = 14,\n\tVHOST_USER_MAX\n} VhostUserRequest;\n\ntypedef struct VhostUserMemoryRegion {\n\tuint64_t guest_phys_addr;\n\tuint64_t memory_size;\n\tuint64_t userspace_addr;\n\tuint64_t mmap_offset;\n} VhostUserMemoryRegion;\n\ntypedef struct VhostUserMemory {\n\tuint32_t nregions;\n\tuint32_t padding;\n\tVhostUserMemoryRegion regions[VHOST_MEMORY_MAX_NREGIONS];\n} VhostUserMemory;\n\ntypedef struct VhostUserMsg {\n\tVhostUserRequest request;\n\n#define VHOST_USER_VERSION_MASK 0x3\n#define VHOST_USER_REPLY_MASK (0x1 << 2)\n\tuint32_t flags;\n\tuint32_t size; /* the following payload size */\n\tunion {\n#define VHOST_USER_VRING_IDX_MASK 0xff\n#define VHOST_USER_VRING_NOFD_MASK (0x1<<8)\n\t\tuint64_t u64;\n\t\tstruct vhost_vring_state state;\n\t\tstruct vhost_vring_addr addr;\n\t\tVhostUserMemory memory;\n\t} payload;\n\tint fds[VHOST_MEMORY_MAX_NREGIONS];\n} __attribute((packed)) VhostUserMsg;\n\n#define VHOST_USER_HDR_SIZE offsetof(VhostUserMsg, payload.u64)\n\n/* The version of the protocol we support */\n#define VHOST_USER_VERSION 0x1\n\n/*****************************************************************************/\n#endif\n" }, { "path": "lib/librte_vhost/vhost_user/virtio-net-user.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \"virtio-net.h\"\n#include \"virtio-net-user.h\"\n#include \"vhost-net-user.h\"\n#include \"vhost-net.h\"\n\nstruct orig_region_map {\n\tint fd;\n\tuint64_t mapped_address;\n\tuint64_t mapped_size;\n\tuint64_t blksz;\n};\n\n#define orig_region(ptr, nregions) \\\n\t((struct orig_region_map *)RTE_PTR_ADD((ptr), \\\n\t\tsizeof(struct virtio_memory) + \\\n\t\tsizeof(struct virtio_memory_regions) * (nregions)))\n\nstatic uint64_t\nget_blk_size(int fd)\n{\n\tstruct stat stat;\n\n\tfstat(fd, &stat);\n\treturn (uint64_t)stat.st_blksize;\n}\n\nstatic void\nfree_mem_region(struct virtio_net *dev)\n{\n\tstruct orig_region_map *region;\n\tunsigned int idx;\n\tuint64_t alignment;\n\n\tif (!dev || !dev->mem)\n\t\treturn;\n\n\tregion = orig_region(dev->mem, dev->mem->nregions);\n\tfor (idx = 0; idx < dev->mem->nregions; idx++) {\n\t\tif (region[idx].mapped_address) {\n\t\t\talignment = region[idx].blksz;\n\t\t\tmunmap((void *)(uintptr_t)\n\t\t\t\tRTE_ALIGN_FLOOR(\n\t\t\t\t\tregion[idx].mapped_address, alignment),\n\t\t\t\tRTE_ALIGN_CEIL(\n\t\t\t\t\tregion[idx].mapped_size, alignment));\n\t\t\tclose(region[idx].fd);\n\t\t}\n\t}\n}\n\nint\nuser_set_mem_table(struct vhost_device_ctx ctx, struct VhostUserMsg *pmsg)\n{\n\tstruct VhostUserMemory memory = pmsg->payload.memory;\n\tstruct virtio_memory_regions *pregion;\n\tuint64_t mapped_address, mapped_size;\n\tstruct virtio_net *dev;\n\tunsigned int idx = 0;\n\tstruct orig_region_map *pregion_orig;\n\tuint64_t alignment;\n\n\t/* unmap old memory regions one by one*/\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\n\t/* Remove from the data plane. */\n\tif (dev->flags & VIRTIO_DEV_RUNNING)\n\t\tnotify_ops->destroy_device(dev);\n\n\tif (dev->mem) {\n\t\tfree_mem_region(dev);\n\t\tfree(dev->mem);\n\t\tdev->mem = NULL;\n\t}\n\n\tdev->mem = calloc(1,\n\t\tsizeof(struct virtio_memory) +\n\t\tsizeof(struct virtio_memory_regions) * memory.nregions +\n\t\tsizeof(struct orig_region_map) * memory.nregions);\n\tif (dev->mem == NULL) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") Failed to allocate memory for dev->mem\\n\",\n\t\t\tdev->device_fh);\n\t\treturn -1;\n\t}\n\tdev->mem->nregions = memory.nregions;\n\n\tpregion_orig = orig_region(dev->mem, memory.nregions);\n\tfor (idx = 0; idx < memory.nregions; idx++) {\n\t\tpregion = &dev->mem->regions[idx];\n\t\tpregion->guest_phys_address =\n\t\t\tmemory.regions[idx].guest_phys_addr;\n\t\tpregion->guest_phys_address_end =\n\t\t\tmemory.regions[idx].guest_phys_addr +\n\t\t\tmemory.regions[idx].memory_size;\n\t\tpregion->memory_size =\n\t\t\tmemory.regions[idx].memory_size;\n\t\tpregion->userspace_address =\n\t\t\tmemory.regions[idx].userspace_addr;\n\n\t\t/* This is ugly */\n\t\tmapped_size = memory.regions[idx].memory_size +\n\t\t\tmemory.regions[idx].mmap_offset;\n\t\tmapped_address = (uint64_t)(uintptr_t)mmap(NULL,\n\t\t\tmapped_size,\n\t\t\tPROT_READ | PROT_WRITE, MAP_SHARED,\n\t\t\tpmsg->fds[idx],\n\t\t\t0);\n\n\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\"mapped region %d fd:%d to %p sz:0x%\"PRIx64\" off:0x%\"PRIx64\"\\n\",\n\t\t\tidx, pmsg->fds[idx], (void *)(uintptr_t)mapped_address,\n\t\t\tmapped_size, memory.regions[idx].mmap_offset);\n\n\t\tif (mapped_address == (uint64_t)(uintptr_t)MAP_FAILED) {\n\t\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\t\"mmap qemu guest failed.\\n\");\n\t\t\tgoto err_mmap;\n\t\t}\n\n\t\tpregion_orig[idx].mapped_address = mapped_address;\n\t\tpregion_orig[idx].mapped_size = mapped_size;\n\t\tpregion_orig[idx].blksz = get_blk_size(pmsg->fds[idx]);\n\t\tpregion_orig[idx].fd = pmsg->fds[idx];\n\n\t\tmapped_address += memory.regions[idx].mmap_offset;\n\n\t\tpregion->address_offset = mapped_address -\n\t\t\tpregion->guest_phys_address;\n\n\t\tif (memory.regions[idx].guest_phys_addr == 0) {\n\t\t\tdev->mem->base_address =\n\t\t\t\tmemory.regions[idx].userspace_addr;\n\t\t\tdev->mem->mapped_address =\n\t\t\t\tpregion->address_offset;\n\t\t}\n\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"REGION: %u GPA: %p QEMU VA: %p SIZE (%\"PRIu64\")\\n\",\n\t\t\tidx,\n\t\t\t(void *)(uintptr_t)pregion->guest_phys_address,\n\t\t\t(void *)(uintptr_t)pregion->userspace_address,\n\t\t\t pregion->memory_size);\n\t}\n\n\treturn 0;\n\nerr_mmap:\n\twhile (idx--) {\n\t\talignment = pregion_orig[idx].blksz;\n\t\tmunmap((void *)(uintptr_t)RTE_ALIGN_FLOOR(\n\t\t\tpregion_orig[idx].mapped_address, alignment),\n\t\t\tRTE_ALIGN_CEIL(pregion_orig[idx].mapped_size,\n\t\t\t\t\talignment));\n\t\tclose(pregion_orig[idx].fd);\n\t}\n\tfree(dev->mem);\n\tdev->mem = NULL;\n\treturn -1;\n}\n\nstatic int\nvirtio_is_ready(struct virtio_net *dev)\n{\n\tstruct vhost_virtqueue *rvq, *tvq;\n\n\t/* mq support in future.*/\n\trvq = dev->virtqueue[VIRTIO_RXQ];\n\ttvq = dev->virtqueue[VIRTIO_TXQ];\n\tif (rvq && tvq && rvq->desc && tvq->desc &&\n\t\t(rvq->kickfd != (eventfd_t)-1) &&\n\t\t(rvq->callfd != (eventfd_t)-1) &&\n\t\t(tvq->kickfd != (eventfd_t)-1) &&\n\t\t(tvq->callfd != (eventfd_t)-1)) {\n\t\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\t\"virtio is now ready for processing.\\n\");\n\t\treturn 1;\n\t}\n\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\"virtio isn't ready for processing.\\n\");\n\treturn 0;\n}\n\nvoid\nuser_set_vring_call(struct vhost_device_ctx ctx, struct VhostUserMsg *pmsg)\n{\n\tstruct vhost_vring_file file;\n\n\tfile.index = pmsg->payload.u64 & VHOST_USER_VRING_IDX_MASK;\n\tif (pmsg->payload.u64 & VHOST_USER_VRING_NOFD_MASK)\n\t\tfile.fd = -1;\n\telse\n\t\tfile.fd = pmsg->fds[0];\n\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\"vring call idx:%d file:%d\\n\", file.index, file.fd);\n\tops->set_vring_call(ctx, &file);\n}\n\n\n/*\n * In vhost-user, when we receive kick message, will test whether virtio\n * device is ready for packet processing.\n */\nvoid\nuser_set_vring_kick(struct vhost_device_ctx ctx, struct VhostUserMsg *pmsg)\n{\n\tstruct vhost_vring_file file;\n\tstruct virtio_net *dev = get_device(ctx);\n\n\tfile.index = pmsg->payload.u64 & VHOST_USER_VRING_IDX_MASK;\n\tif (pmsg->payload.u64 & VHOST_USER_VRING_NOFD_MASK)\n\t\tfile.fd = -1;\n\telse\n\t\tfile.fd = pmsg->fds[0];\n\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\"vring kick idx:%d file:%d\\n\", file.index, file.fd);\n\tops->set_vring_kick(ctx, &file);\n\n\tif (virtio_is_ready(dev) &&\n\t\t!(dev->flags & VIRTIO_DEV_RUNNING))\n\t\t\tnotify_ops->new_device(dev);\n}\n\n/*\n * when virtio is stopped, qemu will send us the GET_VRING_BASE message.\n */\nint\nuser_get_vring_base(struct vhost_device_ctx ctx,\n\tstruct vhost_vring_state *state)\n{\n\tstruct virtio_net *dev = get_device(ctx);\n\n\t/* We have to stop the queue (virtio) if it is running. */\n\tif (dev->flags & VIRTIO_DEV_RUNNING)\n\t\tnotify_ops->destroy_device(dev);\n\n\t/* Here we are safe to get the last used index */\n\tops->get_vring_base(ctx, state->index, state);\n\n\tRTE_LOG(INFO, VHOST_CONFIG,\n\t\t\"vring base idx:%d file:%d\\n\", state->index, state->num);\n\t/*\n\t * Based on current qemu vhost-user implementation, this message is\n\t * sent and only sent in vhost_vring_stop.\n\t * TODO: cleanup the vring, it isn't usable since here.\n\t */\n\tif (((int)dev->virtqueue[VIRTIO_RXQ]->kickfd) >= 0) {\n\t\tclose(dev->virtqueue[VIRTIO_RXQ]->kickfd);\n\t\tdev->virtqueue[VIRTIO_RXQ]->kickfd = (eventfd_t)-1;\n\t}\n\tif (((int)dev->virtqueue[VIRTIO_TXQ]->kickfd) >= 0) {\n\t\tclose(dev->virtqueue[VIRTIO_TXQ]->kickfd);\n\t\tdev->virtqueue[VIRTIO_TXQ]->kickfd = (eventfd_t)-1;\n\t}\n\n\treturn 0;\n}\n\nvoid\nuser_destroy_device(struct vhost_device_ctx ctx)\n{\n\tstruct virtio_net *dev = get_device(ctx);\n\n\tif (dev && (dev->flags & VIRTIO_DEV_RUNNING))\n\t\tnotify_ops->destroy_device(dev);\n\n\tif (dev && dev->mem) {\n\t\tfree_mem_region(dev);\n\t\tfree(dev->mem);\n\t\tdev->mem = NULL;\n\t}\n}\n" }, { "path": "lib/librte_vhost/vhost_user/virtio-net-user.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VIRTIO_NET_USER_H\n#define _VIRTIO_NET_USER_H\n\n#include \"vhost-net.h\"\n#include \"vhost-net-user.h\"\n\nint user_set_mem_table(struct vhost_device_ctx, struct VhostUserMsg *);\n\nvoid user_set_vring_call(struct vhost_device_ctx, struct VhostUserMsg *);\n\nvoid user_set_vring_kick(struct vhost_device_ctx, struct VhostUserMsg *);\n\nint user_get_vring_base(struct vhost_device_ctx, struct vhost_vring_state *);\n\nvoid user_destroy_device(struct vhost_device_ctx);\n#endif\n" }, { "path": "lib/librte_vhost/virtio-net.c", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#ifdef RTE_LIBRTE_VHOST_NUMA\n#include \n#endif\n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \"vhost-net.h\"\n#include \"virtio-net.h\"\n\n/*\n * Device linked list structure for configuration.\n */\nstruct virtio_net_config_ll {\n\tstruct virtio_net dev;\t\t\t/* Virtio device.*/\n\tstruct virtio_net_config_ll *next;\t/* Next dev on linked list.*/\n};\n\n/* device ops to add/remove device to/from data core. */\nstruct virtio_net_device_ops const *notify_ops;\n/* root address of the linked list of managed virtio devices */\nstatic struct virtio_net_config_ll *ll_root;\n\n/* Features supported by this lib. */\n#define VHOST_SUPPORTED_FEATURES ((1ULL << VIRTIO_NET_F_MRG_RXBUF) | \\\n\t\t\t\t(1ULL << VIRTIO_NET_F_CTRL_VQ) | \\\n\t\t\t\t(1ULL << VIRTIO_NET_F_CTRL_RX) | \\\n\t\t\t\t(1ULL << VHOST_F_LOG_ALL))\nstatic uint64_t VHOST_FEATURES = VHOST_SUPPORTED_FEATURES;\n\n\n/*\n * Converts QEMU virtual address to Vhost virtual address. This function is\n * used to convert the ring addresses to our address space.\n */\nstatic uint64_t\nqva_to_vva(struct virtio_net *dev, uint64_t qemu_va)\n{\n\tstruct virtio_memory_regions *region;\n\tuint64_t vhost_va = 0;\n\tuint32_t regionidx = 0;\n\n\t/* Find the region where the address lives. */\n\tfor (regionidx = 0; regionidx < dev->mem->nregions; regionidx++) {\n\t\tregion = &dev->mem->regions[regionidx];\n\t\tif ((qemu_va >= region->userspace_address) &&\n\t\t\t(qemu_va <= region->userspace_address +\n\t\t\tregion->memory_size)) {\n\t\t\tvhost_va = qemu_va + region->guest_phys_address +\n\t\t\t\tregion->address_offset -\n\t\t\t\tregion->userspace_address;\n\t\t\tbreak;\n\t\t}\n\t}\n\treturn vhost_va;\n}\n\n\n/*\n * Retrieves an entry from the devices configuration linked list.\n */\nstatic struct virtio_net_config_ll *\nget_config_ll_entry(struct vhost_device_ctx ctx)\n{\n\tstruct virtio_net_config_ll *ll_dev = ll_root;\n\n\t/* Loop through linked list until the device_fh is found. */\n\twhile (ll_dev != NULL) {\n\t\tif (ll_dev->dev.device_fh == ctx.fh)\n\t\t\treturn ll_dev;\n\t\tll_dev = ll_dev->next;\n\t}\n\n\treturn NULL;\n}\n\n/*\n * Searches the configuration core linked list and\n * retrieves the device if it exists.\n */\nstruct virtio_net *\nget_device(struct vhost_device_ctx ctx)\n{\n\tstruct virtio_net_config_ll *ll_dev;\n\n\tll_dev = get_config_ll_entry(ctx);\n\n\tif (ll_dev)\n\t\treturn &ll_dev->dev;\n\n\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\"(%\"PRIu64\") Device not found in linked list.\\n\", ctx.fh);\n\treturn NULL;\n}\n\n/*\n * Add entry containing a device to the device configuration linked list.\n */\nstatic void\nadd_config_ll_entry(struct virtio_net_config_ll *new_ll_dev)\n{\n\tstruct virtio_net_config_ll *ll_dev = ll_root;\n\n\t/* If ll_dev == NULL then this is the first device so go to else */\n\tif (ll_dev) {\n\t\t/* If the 1st device_fh != 0 then we insert our device here. */\n\t\tif (ll_dev->dev.device_fh != 0) {\n\t\t\tnew_ll_dev->dev.device_fh = 0;\n\t\t\tnew_ll_dev->next = ll_dev;\n\t\t\tll_root = new_ll_dev;\n\t\t} else {\n\t\t\t/*\n\t\t\t * Increment through the ll until we find un unused\n\t\t\t * device_fh. Insert the device at that entry.\n\t\t\t */\n\t\t\twhile ((ll_dev->next != NULL) &&\n\t\t\t\t(ll_dev->dev.device_fh ==\n\t\t\t\t\t(ll_dev->next->dev.device_fh - 1)))\n\t\t\t\tll_dev = ll_dev->next;\n\n\t\t\tnew_ll_dev->dev.device_fh = ll_dev->dev.device_fh + 1;\n\t\t\tnew_ll_dev->next = ll_dev->next;\n\t\t\tll_dev->next = new_ll_dev;\n\t\t}\n\t} else {\n\t\tll_root = new_ll_dev;\n\t\tll_root->dev.device_fh = 0;\n\t}\n\n}\n\n/*\n * Unmap any memory, close any file descriptors and\n * free any memory owned by a device.\n */\nstatic void\ncleanup_device(struct virtio_net *dev)\n{\n\t/* Unmap QEMU memory file if mapped. */\n\tif (dev->mem) {\n\t\tmunmap((void *)(uintptr_t)dev->mem->mapped_address,\n\t\t\t(size_t)dev->mem->mapped_size);\n\t\tfree(dev->mem);\n\t}\n\n\t/* Close any event notifiers opened by device. */\n\tif ((int)dev->virtqueue[VIRTIO_RXQ]->callfd >= 0)\n\t\tclose((int)dev->virtqueue[VIRTIO_RXQ]->callfd);\n\tif ((int)dev->virtqueue[VIRTIO_RXQ]->kickfd >= 0)\n\t\tclose((int)dev->virtqueue[VIRTIO_RXQ]->kickfd);\n\tif ((int)dev->virtqueue[VIRTIO_TXQ]->callfd >= 0)\n\t\tclose((int)dev->virtqueue[VIRTIO_TXQ]->callfd);\n\tif ((int)dev->virtqueue[VIRTIO_TXQ]->kickfd >= 0)\n\t\tclose((int)dev->virtqueue[VIRTIO_TXQ]->kickfd);\n}\n\n/*\n * Release virtqueues and device memory.\n */\nstatic void\nfree_device(struct virtio_net_config_ll *ll_dev)\n{\n\t/* Free any malloc'd memory */\n\trte_free(ll_dev->dev.virtqueue[VIRTIO_RXQ]);\n\trte_free(ll_dev->dev.virtqueue[VIRTIO_TXQ]);\n\trte_free(ll_dev);\n}\n\n/*\n * Remove an entry from the device configuration linked list.\n */\nstatic struct virtio_net_config_ll *\nrm_config_ll_entry(struct virtio_net_config_ll *ll_dev,\n\tstruct virtio_net_config_ll *ll_dev_last)\n{\n\t/* First remove the device and then clean it up. */\n\tif (ll_dev == ll_root) {\n\t\tll_root = ll_dev->next;\n\t\tcleanup_device(&ll_dev->dev);\n\t\tfree_device(ll_dev);\n\t\treturn ll_root;\n\t} else {\n\t\tif (likely(ll_dev_last != NULL)) {\n\t\t\tll_dev_last->next = ll_dev->next;\n\t\t\tcleanup_device(&ll_dev->dev);\n\t\t\tfree_device(ll_dev);\n\t\t\treturn ll_dev_last->next;\n\t\t} else {\n\t\t\tcleanup_device(&ll_dev->dev);\n\t\t\tfree_device(ll_dev);\n\t\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\t\"Remove entry from config_ll failed\\n\");\n\t\t\treturn NULL;\n\t\t}\n\t}\n}\n\n/*\n * Initialise all variables in device structure.\n */\nstatic void\ninit_device(struct virtio_net *dev)\n{\n\tuint64_t vq_offset;\n\n\t/*\n\t * Virtqueues have already been malloced so\n\t * we don't want to set them to NULL.\n\t */\n\tvq_offset = offsetof(struct virtio_net, mem);\n\n\t/* Set everything to 0. */\n\tmemset((void *)(uintptr_t)((uint64_t)(uintptr_t)dev + vq_offset), 0,\n\t\t(sizeof(struct virtio_net) - (size_t)vq_offset));\n\tmemset(dev->virtqueue[VIRTIO_RXQ], 0, sizeof(struct vhost_virtqueue));\n\tmemset(dev->virtqueue[VIRTIO_TXQ], 0, sizeof(struct vhost_virtqueue));\n\n\tdev->virtqueue[VIRTIO_RXQ]->kickfd = (eventfd_t)-1;\n\tdev->virtqueue[VIRTIO_RXQ]->callfd = (eventfd_t)-1;\n\tdev->virtqueue[VIRTIO_TXQ]->kickfd = (eventfd_t)-1;\n\tdev->virtqueue[VIRTIO_TXQ]->callfd = (eventfd_t)-1;\n\n\t/* Backends are set to -1 indicating an inactive device. */\n\tdev->virtqueue[VIRTIO_RXQ]->backend = VIRTIO_DEV_STOPPED;\n\tdev->virtqueue[VIRTIO_TXQ]->backend = VIRTIO_DEV_STOPPED;\n}\n\n/*\n * Function is called from the CUSE open function. The device structure is\n * initialised and a new entry is added to the device configuration linked\n * list.\n */\nstatic int\nnew_device(struct vhost_device_ctx ctx)\n{\n\tstruct virtio_net_config_ll *new_ll_dev;\n\tstruct vhost_virtqueue *virtqueue_rx, *virtqueue_tx;\n\n\t/* Setup device and virtqueues. */\n\tnew_ll_dev = rte_malloc(NULL, sizeof(struct virtio_net_config_ll), 0);\n\tif (new_ll_dev == NULL) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") Failed to allocate memory for dev.\\n\",\n\t\t\tctx.fh);\n\t\treturn -1;\n\t}\n\n\tvirtqueue_rx = rte_malloc(NULL, sizeof(struct vhost_virtqueue), 0);\n\tif (virtqueue_rx == NULL) {\n\t\trte_free(new_ll_dev);\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") Failed to allocate memory for rxq.\\n\",\n\t\t\tctx.fh);\n\t\treturn -1;\n\t}\n\n\tvirtqueue_tx = rte_malloc(NULL, sizeof(struct vhost_virtqueue), 0);\n\tif (virtqueue_tx == NULL) {\n\t\trte_free(virtqueue_rx);\n\t\trte_free(new_ll_dev);\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") Failed to allocate memory for txq.\\n\",\n\t\t\tctx.fh);\n\t\treturn -1;\n\t}\n\n\tnew_ll_dev->dev.virtqueue[VIRTIO_RXQ] = virtqueue_rx;\n\tnew_ll_dev->dev.virtqueue[VIRTIO_TXQ] = virtqueue_tx;\n\n\t/* Initialise device and virtqueues. */\n\tinit_device(&new_ll_dev->dev);\n\n\tnew_ll_dev->next = NULL;\n\n\t/* Add entry to device configuration linked list. */\n\tadd_config_ll_entry(new_ll_dev);\n\n\treturn new_ll_dev->dev.device_fh;\n}\n\n/*\n * Function is called from the CUSE release function. This function will\n * cleanup the device and remove it from device configuration linked list.\n */\nstatic void\ndestroy_device(struct vhost_device_ctx ctx)\n{\n\tstruct virtio_net_config_ll *ll_dev_cur_ctx, *ll_dev_last = NULL;\n\tstruct virtio_net_config_ll *ll_dev_cur = ll_root;\n\n\t/* Find the linked list entry for the device to be removed. */\n\tll_dev_cur_ctx = get_config_ll_entry(ctx);\n\twhile (ll_dev_cur != NULL) {\n\t\t/*\n\t\t * If the device is found or\n\t\t * a device that doesn't exist is found then it is removed.\n\t\t */\n\t\tif (ll_dev_cur == ll_dev_cur_ctx) {\n\t\t\t/*\n\t\t\t * If the device is running on a data core then call\n\t\t\t * the function to remove it from the data core.\n\t\t\t */\n\t\t\tif ((ll_dev_cur->dev.flags & VIRTIO_DEV_RUNNING))\n\t\t\t\tnotify_ops->destroy_device(&(ll_dev_cur->dev));\n\t\t\tll_dev_cur = rm_config_ll_entry(ll_dev_cur,\n\t\t\t\t\tll_dev_last);\n\t\t} else {\n\t\t\tll_dev_last = ll_dev_cur;\n\t\t\tll_dev_cur = ll_dev_cur->next;\n\t\t}\n\t}\n}\n\nstatic void\nset_ifname(struct vhost_device_ctx ctx,\n\tconst char *if_name, unsigned int if_len)\n{\n\tstruct virtio_net *dev;\n\tunsigned int len;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn;\n\n\tlen = if_len > sizeof(dev->ifname) ?\n\t\tsizeof(dev->ifname) : if_len;\n\n\tstrncpy(dev->ifname, if_name, len);\n}\n\n\n/*\n * Called from CUSE IOCTL: VHOST_SET_OWNER\n * This function just returns success at the moment unless\n * the device hasn't been initialised.\n */\nstatic int\nset_owner(struct vhost_device_ctx ctx)\n{\n\tstruct virtio_net *dev;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\n\treturn 0;\n}\n\n/*\n * Called from CUSE IOCTL: VHOST_RESET_OWNER\n */\nstatic int\nreset_owner(struct vhost_device_ctx ctx)\n{\n\tstruct virtio_net_config_ll *ll_dev;\n\n\tll_dev = get_config_ll_entry(ctx);\n\n\tcleanup_device(&ll_dev->dev);\n\tinit_device(&ll_dev->dev);\n\n\treturn 0;\n}\n\n/*\n * Called from CUSE IOCTL: VHOST_GET_FEATURES\n * The features that we support are requested.\n */\nstatic int\nget_features(struct vhost_device_ctx ctx, uint64_t *pu)\n{\n\tstruct virtio_net *dev;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\n\t/* Send our supported features. */\n\t*pu = VHOST_FEATURES;\n\treturn 0;\n}\n\n/*\n * Called from CUSE IOCTL: VHOST_SET_FEATURES\n * We receive the negotiated features supported by us and the virtio device.\n */\nstatic int\nset_features(struct vhost_device_ctx ctx, uint64_t *pu)\n{\n\tstruct virtio_net *dev;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\tif (*pu & ~VHOST_FEATURES)\n\t\treturn -1;\n\n\t/* Store the negotiated feature list for the device. */\n\tdev->features = *pu;\n\n\t/* Set the vhost_hlen depending on if VIRTIO_NET_F_MRG_RXBUF is set. */\n\tif (dev->features & (1 << VIRTIO_NET_F_MRG_RXBUF)) {\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") Mergeable RX buffers enabled\\n\",\n\t\t\tdev->device_fh);\n\t\tdev->virtqueue[VIRTIO_RXQ]->vhost_hlen =\n\t\t\tsizeof(struct virtio_net_hdr_mrg_rxbuf);\n\t\tdev->virtqueue[VIRTIO_TXQ]->vhost_hlen =\n\t\t\tsizeof(struct virtio_net_hdr_mrg_rxbuf);\n\t} else {\n\t\tLOG_DEBUG(VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") Mergeable RX buffers disabled\\n\",\n\t\t\tdev->device_fh);\n\t\tdev->virtqueue[VIRTIO_RXQ]->vhost_hlen =\n\t\t\tsizeof(struct virtio_net_hdr);\n\t\tdev->virtqueue[VIRTIO_TXQ]->vhost_hlen =\n\t\t\tsizeof(struct virtio_net_hdr);\n\t}\n\treturn 0;\n}\n\n/*\n * Called from CUSE IOCTL: VHOST_SET_VRING_NUM\n * The virtio device sends us the size of the descriptor ring.\n */\nstatic int\nset_vring_num(struct vhost_device_ctx ctx, struct vhost_vring_state *state)\n{\n\tstruct virtio_net *dev;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\n\t/* State->index refers to the queue index. The txq is 1, rxq is 0. */\n\tdev->virtqueue[state->index]->size = state->num;\n\n\treturn 0;\n}\n\n/*\n * Reallocate virtio_det and vhost_virtqueue data structure to make them on the\n * same numa node as the memory of vring descriptor.\n */\n#ifdef RTE_LIBRTE_VHOST_NUMA\nstatic struct virtio_net*\nnuma_realloc(struct virtio_net *dev, int index)\n{\n\tint oldnode, newnode;\n\tstruct virtio_net_config_ll *old_ll_dev, *new_ll_dev = NULL;\n\tstruct vhost_virtqueue *old_vq, *new_vq = NULL;\n\tint ret;\n\tint realloc_dev = 0, realloc_vq = 0;\n\n\told_ll_dev = (struct virtio_net_config_ll *)dev;\n\told_vq = dev->virtqueue[index];\n\n\tret = get_mempolicy(&newnode, NULL, 0, old_vq->desc,\n\t\t\tMPOL_F_NODE | MPOL_F_ADDR);\n\tret = ret | get_mempolicy(&oldnode, NULL, 0, old_ll_dev,\n\t\t\tMPOL_F_NODE | MPOL_F_ADDR);\n\tif (ret) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"Unable to get vring desc or dev numa information.\\n\");\n\t\treturn dev;\n\t}\n\tif (oldnode != newnode)\n\t\trealloc_dev = 1;\n\n\tret = get_mempolicy(&oldnode, NULL, 0, old_vq,\n\t\t\tMPOL_F_NODE | MPOL_F_ADDR);\n\tif (ret) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"Unable to get vq numa information.\\n\");\n\t\treturn dev;\n\t}\n\tif (oldnode != newnode)\n\t\trealloc_vq = 1;\n\n\tif (realloc_dev == 0 && realloc_vq == 0)\n\t\treturn dev;\n\n\tif (realloc_dev)\n\t\tnew_ll_dev = rte_malloc_socket(NULL,\n\t\t\tsizeof(struct virtio_net_config_ll), 0, newnode);\n\tif (realloc_vq)\n\t\tnew_vq = rte_malloc_socket(NULL,\n\t\t\tsizeof(struct vhost_virtqueue), 0, newnode);\n\tif (!new_ll_dev && !new_vq)\n\t\treturn dev;\n\n\tif (realloc_vq)\n\t\tmemcpy(new_vq, old_vq, sizeof(*new_vq));\n\tif (realloc_dev)\n\t\tmemcpy(new_ll_dev, old_ll_dev, sizeof(*new_ll_dev));\n\t(new_ll_dev ? new_ll_dev : old_ll_dev)->dev.virtqueue[index] =\n\t\tnew_vq ? new_vq : old_vq;\n\tif (realloc_vq)\n\t\trte_free(old_vq);\n\tif (realloc_dev) {\n\t\tif (ll_root == old_ll_dev)\n\t\t\tll_root = new_ll_dev;\n\t\telse {\n\t\t\tstruct virtio_net_config_ll *prev = ll_root;\n\t\t\twhile (prev->next != old_ll_dev)\n\t\t\t\tprev = prev->next;\n\t\t\tprev->next = new_ll_dev;\n\t\t\tnew_ll_dev->next = old_ll_dev->next;\n\t\t}\n\t\trte_free(old_ll_dev);\n\t}\n\n\treturn realloc_dev ? &new_ll_dev->dev : dev;\n}\n#else\nstatic struct virtio_net*\nnuma_realloc(struct virtio_net *dev, int index __rte_unused)\n{\n\treturn dev;\n}\n#endif\n\n/*\n * Called from CUSE IOCTL: VHOST_SET_VRING_ADDR\n * The virtio device sends us the desc, used and avail ring addresses.\n * This function then converts these to our address space.\n */\nstatic int\nset_vring_addr(struct vhost_device_ctx ctx, struct vhost_vring_addr *addr)\n{\n\tstruct virtio_net *dev;\n\tstruct vhost_virtqueue *vq;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\n\t/* addr->index refers to the queue index. The txq 1, rxq is 0. */\n\tvq = dev->virtqueue[addr->index];\n\n\t/* The addresses are converted from QEMU virtual to Vhost virtual. */\n\tvq->desc = (struct vring_desc *)(uintptr_t)qva_to_vva(dev,\n\t\t\taddr->desc_user_addr);\n\tif (vq->desc == 0) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") Failed to find desc ring address.\\n\",\n\t\t\tdev->device_fh);\n\t\treturn -1;\n\t}\n\n\tdev = numa_realloc(dev, addr->index);\n\tvq = dev->virtqueue[addr->index];\n\n\tvq->avail = (struct vring_avail *)(uintptr_t)qva_to_vva(dev,\n\t\t\taddr->avail_user_addr);\n\tif (vq->avail == 0) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") Failed to find avail ring address.\\n\",\n\t\t\tdev->device_fh);\n\t\treturn -1;\n\t}\n\n\tvq->used = (struct vring_used *)(uintptr_t)qva_to_vva(dev,\n\t\t\taddr->used_user_addr);\n\tif (vq->used == 0) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"(%\"PRIu64\") Failed to find used ring address.\\n\",\n\t\t\tdev->device_fh);\n\t\treturn -1;\n\t}\n\n\tLOG_DEBUG(VHOST_CONFIG, \"(%\"PRIu64\") mapped address desc: %p\\n\",\n\t\t\tdev->device_fh, vq->desc);\n\tLOG_DEBUG(VHOST_CONFIG, \"(%\"PRIu64\") mapped address avail: %p\\n\",\n\t\t\tdev->device_fh, vq->avail);\n\tLOG_DEBUG(VHOST_CONFIG, \"(%\"PRIu64\") mapped address used: %p\\n\",\n\t\t\tdev->device_fh, vq->used);\n\n\treturn 0;\n}\n\n/*\n * Called from CUSE IOCTL: VHOST_SET_VRING_BASE\n * The virtio device sends us the available ring last used index.\n */\nstatic int\nset_vring_base(struct vhost_device_ctx ctx, struct vhost_vring_state *state)\n{\n\tstruct virtio_net *dev;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\n\t/* State->index refers to the queue index. The txq is 1, rxq is 0. */\n\tdev->virtqueue[state->index]->last_used_idx = state->num;\n\tdev->virtqueue[state->index]->last_used_idx_res = state->num;\n\n\treturn 0;\n}\n\n/*\n * Called from CUSE IOCTL: VHOST_GET_VRING_BASE\n * We send the virtio device our available ring last used index.\n */\nstatic int\nget_vring_base(struct vhost_device_ctx ctx, uint32_t index,\n\tstruct vhost_vring_state *state)\n{\n\tstruct virtio_net *dev;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\n\tstate->index = index;\n\t/* State->index refers to the queue index. The txq is 1, rxq is 0. */\n\tstate->num = dev->virtqueue[state->index]->last_used_idx;\n\n\treturn 0;\n}\n\n\n/*\n * Called from CUSE IOCTL: VHOST_SET_VRING_CALL\n * The virtio device sends an eventfd to interrupt the guest. This fd gets\n * copied into our process space.\n */\nstatic int\nset_vring_call(struct vhost_device_ctx ctx, struct vhost_vring_file *file)\n{\n\tstruct virtio_net *dev;\n\tstruct vhost_virtqueue *vq;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\n\t/* file->index refers to the queue index. The txq is 1, rxq is 0. */\n\tvq = dev->virtqueue[file->index];\n\n\tif ((int)vq->callfd >= 0)\n\t\tclose((int)vq->callfd);\n\n\tvq->callfd = file->fd;\n\n\treturn 0;\n}\n\n/*\n * Called from CUSE IOCTL: VHOST_SET_VRING_KICK\n * The virtio device sends an eventfd that it can use to notify us.\n * This fd gets copied into our process space.\n */\nstatic int\nset_vring_kick(struct vhost_device_ctx ctx, struct vhost_vring_file *file)\n{\n\tstruct virtio_net *dev;\n\tstruct vhost_virtqueue *vq;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\n\t/* file->index refers to the queue index. The txq is 1, rxq is 0. */\n\tvq = dev->virtqueue[file->index];\n\n\tif ((int)vq->kickfd >= 0)\n\t\tclose((int)vq->kickfd);\n\n\tvq->kickfd = file->fd;\n\n\treturn 0;\n}\n\n/*\n * Called from CUSE IOCTL: VHOST_NET_SET_BACKEND\n * To complete device initialisation when the virtio driver is loaded,\n * we are provided with a valid fd for a tap device (not used by us).\n * If this happens then we can add the device to a data core.\n * When the virtio driver is removed we get fd=-1.\n * At that point we remove the device from the data core.\n * The device will still exist in the device configuration linked list.\n */\nstatic int\nset_backend(struct vhost_device_ctx ctx, struct vhost_vring_file *file)\n{\n\tstruct virtio_net *dev;\n\n\tdev = get_device(ctx);\n\tif (dev == NULL)\n\t\treturn -1;\n\n\t/* file->index refers to the queue index. The txq is 1, rxq is 0. */\n\tdev->virtqueue[file->index]->backend = file->fd;\n\n\t/*\n\t * If the device isn't already running and both backend fds are set,\n\t * we add the device.\n\t */\n\tif (!(dev->flags & VIRTIO_DEV_RUNNING)) {\n\t\tif (((int)dev->virtqueue[VIRTIO_TXQ]->backend != VIRTIO_DEV_STOPPED) &&\n\t\t\t((int)dev->virtqueue[VIRTIO_RXQ]->backend != VIRTIO_DEV_STOPPED)) {\n\t\t\treturn notify_ops->new_device(dev);\n\t\t}\n\t/* Otherwise we remove it. */\n\t} else\n\t\tif (file->fd == VIRTIO_DEV_STOPPED)\n\t\t\tnotify_ops->destroy_device(dev);\n\treturn 0;\n}\n\n/*\n * Function pointers are set for the device operations to allow CUSE to call\n * functions when an IOCTL, device_add or device_release is received.\n */\nstatic const struct vhost_net_device_ops vhost_device_ops = {\n\t.new_device = new_device,\n\t.destroy_device = destroy_device,\n\n\t.set_ifname = set_ifname,\n\n\t.get_features = get_features,\n\t.set_features = set_features,\n\n\t.set_vring_num = set_vring_num,\n\t.set_vring_addr = set_vring_addr,\n\t.set_vring_base = set_vring_base,\n\t.get_vring_base = get_vring_base,\n\n\t.set_vring_kick = set_vring_kick,\n\t.set_vring_call = set_vring_call,\n\n\t.set_backend = set_backend,\n\n\t.set_owner = set_owner,\n\t.reset_owner = reset_owner,\n};\n\n/*\n * Called by main to setup callbacks when registering CUSE device.\n */\nstruct vhost_net_device_ops const *\nget_virtio_net_callbacks(void)\n{\n\treturn &vhost_device_ops;\n}\n\nint rte_vhost_enable_guest_notification(struct virtio_net *dev,\n\tuint16_t queue_id, int enable)\n{\n\tif (enable) {\n\t\tRTE_LOG(ERR, VHOST_CONFIG,\n\t\t\t\"guest notification isn't supported.\\n\");\n\t\treturn -1;\n\t}\n\n\tdev->virtqueue[queue_id]->used->flags =\n\t\tenable ? 0 : VRING_USED_F_NO_NOTIFY;\n\treturn 0;\n}\n\nuint64_t rte_vhost_feature_get(void)\n{\n\treturn VHOST_FEATURES;\n}\n\nint rte_vhost_feature_disable(uint64_t feature_mask)\n{\n\tVHOST_FEATURES = VHOST_FEATURES & ~feature_mask;\n\treturn 0;\n}\n\nint rte_vhost_feature_enable(uint64_t feature_mask)\n{\n\tif ((feature_mask & VHOST_SUPPORTED_FEATURES) == feature_mask) {\n\t\tVHOST_FEATURES = VHOST_FEATURES | feature_mask;\n\t\treturn 0;\n\t}\n\treturn -1;\n}\n\n/*\n * Register ops so that we can add/remove device to data core.\n */\nint\nrte_vhost_driver_callback_register(struct virtio_net_device_ops const * const ops)\n{\n\tnotify_ops = ops;\n\n\treturn 0;\n}\n" }, { "path": "lib/librte_vhost/virtio-net.h", "content": "/*-\n * BSD LICENSE\n *\n * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions\n * are met:\n *\n * * Redistributions of source code must retain the above copyright\n * notice, this list of conditions and the following disclaimer.\n * * Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in\n * the documentation and/or other materials provided with the\n * distribution.\n * * Neither the name of Intel Corporation nor the names of its\n * contributors may be used to endorse or promote products derived\n * from this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n */\n\n#ifndef _VIRTIO_NET_H\n#define _VIRTIO_NET_H\n\n#include \"vhost-net.h\"\n#include \"rte_virtio_net.h\"\n\nstruct virtio_net_device_ops const *notify_ops;\nstruct virtio_net *get_device(struct vhost_device_ctx ctx);\n\n#endif\n" }, { "path": "mk/arch/i686/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# arch:\n#\n# - define ARCH variable (overriden by cmdline or by previous\n# optional define in machine .mk)\n# - define CROSS variable (overriden by cmdline or previous define\n# in machine .mk)\n# - define CPU_CFLAGS variable (overriden by cmdline or previous\n# define in machine .mk)\n# - define CPU_LDFLAGS variable (overriden by cmdline or previous\n# define in machine .mk)\n# - define CPU_ASFLAGS variable (overriden by cmdline or previous\n# define in machine .mk)\n# - may override any previously defined variable\n#\n# examples for CONFIG_RTE_ARCH: i686, x86_64, x86_64_32\n#\n\nARCH ?= i386\n# common arch dir in eal headers\nARCH_DIR := x86\nCROSS ?=\n\nCPU_CFLAGS ?= -m32\nCPU_LDFLAGS ?= -melf_i386\nCPU_ASFLAGS ?= -felf\n\nexport ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS\n" }, { "path": "mk/arch/ppc_64/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright (C) IBM Corporation 2014.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of IBM Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nARCH ?= powerpc\nCROSS ?=\n\nCPU_CFLAGS ?= -m64 -DRTE_CACHE_LINE_SIZE=128\nCPU_LDFLAGS ?=\nCPU_ASFLAGS ?= -felf64\n\nexport ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS\n" }, { "path": "mk/arch/tile/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright (C) EZchip Semiconductor Ltd. 2015.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of EZchip Semiconductor nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n\nARCH ?= tile\nCROSS ?= tile-\n\nCPU_CFLAGS ?=\nCPU_LDFLAGS ?=\nCPU_ASFLAGS ?=\n\nexport ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS\n" }, { "path": "mk/arch/x86_64/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# arch:\n#\n# - define ARCH variable (overriden by cmdline or by previous\n# optional define in machine .mk)\n# - define CROSS variable (overriden by cmdline or previous define\n# in machine .mk)\n# - define CPU_CFLAGS variable (overriden by cmdline or previous\n# define in machine .mk)\n# - define CPU_LDFLAGS variable (overriden by cmdline or previous\n# define in machine .mk)\n# - define CPU_ASFLAGS variable (overriden by cmdline or previous\n# define in machine .mk)\n# - may override any previously defined variable\n#\n# examples for CONFIG_RTE_ARCH: i686, x86_64, x86_64_32\n#\n\nARCH ?= x86_64\n# common arch dir in eal headers\nARCH_DIR := x86\nCROSS ?=\n\nCPU_CFLAGS ?= -m64\nCPU_LDFLAGS ?=\nCPU_ASFLAGS ?= -felf64\n\nexport ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS\n" }, { "path": "mk/arch/x86_x32/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# arch:\n#\n# - define ARCH variable (overridden by cmdline or by previous\n# optional define in machine .mk)\n# - define CROSS variable (overridden by cmdline or previous define\n# in machine .mk)\n# - define CPU_CFLAGS variable (overridden by cmdline or previous\n# define in machine .mk)\n# - define CPU_LDFLAGS variable (overridden by cmdline or previous\n# define in machine .mk)\n# - define CPU_ASFLAGS variable (overridden by cmdline or previous\n# define in machine .mk)\n# - may override any previously defined variable\n#\n# examples for CONFIG_RTE_ARCH: i686, x86_64, x86_64_32\n#\n\nARCH ?= x86_64\nARCH_DIR := x86\nCROSS ?=\n\nCPU_CFLAGS ?= -mx32\nCPU_LDFLAGS ?= -melf32_x86_64\n#CPU_ASFLAGS ?= -felf64\n# x32 is supported by Linux distribution with gcc4.8 and newer in some\n# cases there is backported support in gcc4.6\nifneq ($(shell echo | $(CC) $(CPU_CFLAGS) -E - 2>/dev/null 1>/dev/null && echo 0), 0)\n\t$(error This version of GCC does not support x32 ABI)\nendif\n\nexport ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS\n" }, { "path": "mk/exec-env/bsdapp/rte.app.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nexec-env-appinstall:\n\t@true\n\nexec-env-appclean:\n\t@true\n" }, { "path": "mk/exec-env/bsdapp/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# exec-env:\n#\n# - define EXECENV_CFLAGS variable (overriden by cmdline)\n# - define EXECENV_LDFLAGS variable (overriden by cmdline)\n# - define EXECENV_ASFLAGS variable (overriden by cmdline)\n# - may override any previously defined variable\n#\n# examples for RTE_EXEC_ENV: linuxapp, bsdapp\n#\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),y)\nEXECENV_CFLAGS = -pthread -fPIC\nelse\nEXECENV_CFLAGS = -pthread\nendif\n\nEXECENV_LDFLAGS =\nEXECENV_LDLIBS = -lexecinfo\nEXECENV_ASFLAGS =\n\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),y)\nEXECENV_LDLIBS += -lgcc_s\nendif\n\n# force applications to link with gcc/icc instead of using ld\nLINK_USING_CC := 1\n\nBSDMAKE=/usr/bin/make\n\nexport EXECENV_CFLAGS EXECENV_LDFLAGS EXECENV_ASFLAGS\n" }, { "path": "mk/exec-env/linuxapp/rte.app.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nexec-env-appinstall:\n\t@true\n\nexec-env-appclean:\n\t@true\n" }, { "path": "mk/exec-env/linuxapp/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# exec-env:\n#\n# - define EXECENV_CFLAGS variable (overriden by cmdline)\n# - define EXECENV_LDFLAGS variable (overriden by cmdline)\n# - define EXECENV_ASFLAGS variable (overriden by cmdline)\n# - may override any previously defined variable\n#\n# examples for RTE_EXEC_ENV: linuxapp, bsdapp\n#\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),y)\nEXECENV_CFLAGS = -pthread -fPIC\nelse\nEXECENV_CFLAGS = -pthread\nendif\n\n# Workaround lack of DT_NEEDED entry\nEXECENV_LDFLAGS = --no-as-needed\n\nEXECENV_LDLIBS = -lrt -lm\nEXECENV_ASFLAGS =\n\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),y)\nEXECENV_LDLIBS += -lgcc_s\nendif\n\n# force applications to link with gcc/icc instead of using ld\nLINK_USING_CC := 1\n\n# For shared libraries\nEXECENV_LDFLAGS += -export-dynamic\n# Add library to the group to resolve symbols\nEXECENV_LDLIBS += -ldl\n\nexport EXECENV_CFLAGS EXECENV_LDFLAGS EXECENV_ASFLAGS EXECENV_LDLIBS\n" }, { "path": "mk/internal/rte.build-post.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# build helper .mk\n\n# fast way, no need to do prebuild and postbuild\nifeq ($(PREBUILD)$(POSTBUILD),)\n\n_postbuild: $(_BUILD)\n\t@touch _postbuild\n\nelse # slower way\n\n_prebuild: $(PREBUILD)\n\t@touch _prebuild\n\nifneq ($(_BUILD),)\n$(_BUILD): _prebuild\nelse\n_BUILD = _prebuild\nendif\n\n_build: $(_BUILD)\n\t@touch _build\n\nifneq ($(POSTBUILD),)\n$(POSTBUILD): _build\nelse\nPOSTBUILD = _build\nendif\n\n_postbuild: $(POSTBUILD)\n\t@touch _postbuild\nendif" }, { "path": "mk/internal/rte.build-pre.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n_BUILD_TARGETS := _prebuild _build _postbuild\n\ncomma := ,\nlinkerprefix = $(subst -Wl$(comma)-L,-L,$(addprefix -Wl$(comma),$1))\n" }, { "path": "mk/internal/rte.clean-post.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# clean helper .mk\n\n# fast way, no need to do preclean and postclean\nifeq ($(PRECLEAN)$(POSTCLEAN),)\n\n_postclean: $(_CLEAN)\n\t@touch _postclean\n\nelse # slower way\n\n_preclean: $(PRECLEAN)\n\t@touch _preclean\n\nifneq ($(_CLEAN),)\n$(_CLEAN): _preclean\nelse\n_CLEAN = _preclean\nendif\n\n_clean: $(_CLEAN)\n\t@touch _clean\n\nifneq ($(POSTCLEAN),)\n$(POSTCLEAN): _clean\nelse\nPOSTCLEAN = _clean\nendif\n\n_postclean: $(POSTCLEAN)\n\t@touch _postclean\nendif\n" }, { "path": "mk/internal/rte.clean-pre.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n_CLEAN_TARGETS := _preclean _clean _postclean\n" }, { "path": "mk/internal/rte.compile-post.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# no rule no build these files\n$(DEPS-y) $(CMDS-y):\n" }, { "path": "mk/internal/rte.compile-pre.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# Common to rte.lib.mk, rte.app.mk, rte.obj.mk\n#\n\nSRCS-all := $(SRCS-y) $(SRCS-n) $(SRCS-)\n\n# convert source to obj file\nsrc2obj = $(strip $(patsubst %.c,%.o,\\\n\t$(patsubst %.S,%_s.o,$(1))))\n\n# add a dot in front of the file name\ndotfile = $(strip $(foreach f,$(1),\\\n\t$(join $(dir $f),.$(notdir $f))))\n\n# convert source/obj files into dot-dep filename (does not\n# include .S files)\nsrc2dep = $(strip $(call dotfile,$(patsubst %.c,%.o.d, \\\n\t\t$(patsubst %.S,,$(1)))))\nobj2dep = $(strip $(call dotfile,$(patsubst %.o,%.o.d,$(1))))\n\n# convert source/obj files into dot-cmd filename\nsrc2cmd = $(strip $(call dotfile,$(patsubst %.c,%.o.cmd, \\\n\t\t$(patsubst %.S,%_s.o.cmd,$(1)))))\nobj2cmd = $(strip $(call dotfile,$(patsubst %.o,%.o.cmd,$(1))))\n\nOBJS-y := $(call src2obj,$(SRCS-y))\nOBJS-n := $(call src2obj,$(SRCS-n))\nOBJS- := $(call src2obj,$(SRCS-))\nOBJS-all := $(filter-out $(SRCS-all),$(OBJS-y) $(OBJS-n) $(OBJS-))\n\nDEPS-y := $(call src2dep,$(SRCS-y))\nDEPS-n := $(call src2dep,$(SRCS-n))\nDEPS- := $(call src2dep,$(SRCS-))\nDEPS-all := $(DEPS-y) $(DEPS-n) $(DEPS-)\nDEPSTMP-all := $(DEPS-all:%.d=%.d.tmp)\n\nCMDS-y := $(call src2cmd,$(SRCS-y))\nCMDS-n := $(call src2cmd,$(SRCS-n))\nCMDS- := $(call src2cmd,$(SRCS-))\nCMDS-all := $(CMDS-y) $(CMDS-n) $(CMDS-)\n\n-include $(DEPS-y) $(CMDS-y)\n\n# command to compile a .c file to generate an object\nifeq ($(USE_HOST),1)\nC_TO_O = $(HOSTCC) -Wp,-MD,$(call obj2dep,$(@)).tmp $(HOST_CFLAGS) \\\n\t$(CFLAGS_$(@)) $(HOST_EXTRA_CFLAGS) -o $@ -c $<\nC_TO_O_STR = $(subst ','\\'',$(C_TO_O)) #'# fix syntax highlight\nC_TO_O_DISP = $(if $(V),\"$(C_TO_O_STR)\",\" HOSTCC $(@)\")\nelse\nC_TO_O = $(CC) -Wp,-MD,$(call obj2dep,$(@)).tmp $(CFLAGS) \\\n\t$(CFLAGS_$(@)) $(EXTRA_CFLAGS) -o $@ -c $<\nC_TO_O_STR = $(subst ','\\'',$(C_TO_O)) #'# fix syntax highlight\nC_TO_O_DISP = $(if $(V),\"$(C_TO_O_STR)\",\" CC $(@)\")\nendif\nC_TO_O_CMD = 'cmd_$@ = $(C_TO_O_STR)'\nC_TO_O_DO = @set -e; \\\n\techo $(C_TO_O_DISP); \\\n\t$(C_TO_O) && \\\n\techo $(C_TO_O_CMD) > $(call obj2cmd,$(@)) && \\\n\tsed 's,'$@':,dep_'$@' =,' $(call obj2dep,$(@)).tmp > $(call obj2dep,$(@)) && \\\n\trm -f $(call obj2dep,$(@)).tmp\n\n# return an empty string if string are equal\ncompare = $(strip $(subst $(1),,$(2)) $(subst $(2),,$(1)))\n\n# return a non-empty string if the dst file does not exist\nfile_missing = $(call compare,$(wildcard $@),$@)\n\n# return a non-empty string if cmdline changed\ncmdline_changed = $(call compare,$(strip $(cmd_$@)),$(strip $(1)))\n\n# return a non-empty string if a dependency file does not exist\ndepfile_missing = $(call compare,$(wildcard $(dep_$@)),$(dep_$@))\n\n# return an empty string if no prereq is newer than target\n# - $^ -> names of all the prerequisites\n# - $(wildcard $^) -> every existing prereq\n# - $(filter-out $(wildcard $^),$^) -> every prereq that don't\n# exist (filter-out removes existing ones from the list)\n# - $? -> names of all the prerequisites newer than target\ndepfile_newer = $(strip $(filter-out FORCE,$? \\\n\t$(filter-out $(wildcard $^),$^)))\n\n# return 1 if parameter is a non-empty string, else 0\nboolean = $(if $1,1,0)\n\n#\n# Compile .c file if needed\n# Note: dep_$$@ is from the .d file and DEP_$$@ can be specified by\n# user (by default it is empty)\n#\n.SECONDEXPANSION:\n%.o: %.c $$(wildcard $$(dep_$$@)) $$(DEP_$$(@)) FORCE\n\t@[ -d $(dir $@) ] || mkdir -p $(dir $@)\n\t$(if $(D),\\\n\t\t@echo -n \"$< -> $@ \" ; \\\n\t\techo -n \"file_missing=$(call boolean,$(file_missing)) \" ; \\\n\t\techo -n \"cmdline_changed=$(call boolean,$(call cmdline_changed,$(C_TO_O))) \" ; \\\n\t\techo -n \"depfile_missing=$(call boolean,$(depfile_missing)) \" ; \\\n\t\techo \"depfile_newer=$(call boolean,$(depfile_newer))\")\n\t$(if $(or \\\n\t\t$(file_missing),\\\n\t\t$(call cmdline_changed,$(C_TO_O)),\\\n\t\t$(depfile_missing),\\\n\t\t$(depfile_newer)),\\\n\t\t$(C_TO_O_DO))\n\n# command to assemble a .S file to generate an object\nifeq ($(USE_HOST),1)\nS_TO_O = $(CPP) $(HOST_CPPFLAGS) $($(@)_CPPFLAGS) $(HOST_EXTRA_CPPFLAGS) $< $(@).tmp && \\\n\t$(HOSTAS) $(HOST_ASFLAGS) $($(@)_ASFLAGS) $(HOST_EXTRA_ASFLAGS) -o $@ $(@).tmp\nS_TO_O_STR = $(subst ','\\'',$(S_TO_O)) #'# fix syntax highlight\nS_TO_O_DISP = $(if $(V),\"$(S_TO_O_STR)\",\" HOSTAS $(@)\")\nelse\nS_TO_O = $(CPP) $(CPPFLAGS) $($(@)_CPPFLAGS) $(EXTRA_CPPFLAGS) $< -o $(@).tmp && \\\n\t$(AS) $(ASFLAGS) $($(@)_ASFLAGS) $(EXTRA_ASFLAGS) -o $@ $(@).tmp\nS_TO_O_STR = $(subst ','\\'',$(S_TO_O)) #'# fix syntax highlight\nS_TO_O_DISP = $(if $(V),\"$(S_TO_O_STR)\",\" AS $(@)\")\nendif\n\nS_TO_O_CMD = \"cmd_$@ = $(S_TO_O_STR)\"\nS_TO_O_DO = @set -e; \\\n\techo $(S_TO_O_DISP); \\\n\t$(S_TO_O) && \\\n\techo $(S_TO_O_CMD) > $(call obj2cmd,$(@))\n\n#\n# Compile .S file if needed\n# Note: DEP_$$@ can be specified by user (by default it is empty)\n#\n%_s.o: %.S $$(DEP_$$@) FORCE\n\t@[ ! -d $(dir $@) ] || mkdir -p $(dir $@)\n\t$(if $(D),\\\n\t\t@echo -n \"$< -> $@ \" ; \\\n\t\techo -n \"file_missing=$(call boolean,$(file_missing)) \" ; \\\n\t\techo -n \"cmdline_changed=$(call boolean,$(call cmdline_changed,$(S_TO_O_STR))) \" ; \\\n\t\techo -n \"depfile_missing=$(call boolean,$(depfile_missing)) \" ; \\\n\t\techo \"depfile_newer=$(call boolean,$(depfile_newer)) \")\n\t$(if $(or \\\n\t\t$(file_missing),\\\n\t\t$(call cmdline_changed,$(S_TO_O_STR)),\\\n\t\t$(depfile_missing),\\\n\t\t$(depfile_newer)),\\\n\t\t$(S_TO_O_DO))\n" }, { "path": "mk/internal/rte.depdirs-post.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.PHONY: depdirs\ndepdirs:\n\t@for d in $(DEPDIRS-y); do \\\n\t\t$(RTE_SDK)/scripts/depdirs-rule.sh $(S) $$d ; \\\n\tdone\n\n.PHONY: depgraph\ndepgraph:\n\t@for d in $(DEPDIRS-y); do \\\n\t\techo \" \\\"$(S)\\\" -> \\\"$$d\\\"\" ; \\\n\tdone\n" }, { "path": "mk/internal/rte.depdirs-pre.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# nothing\n" }, { "path": "mk/internal/rte.extvars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# directory where sources are located\n#\nifdef S\nifeq (\"$(origin S)\", \"command line\")\nRTE_SRCDIR := $(abspath $(S))\nendif\nendif\nRTE_SRCDIR ?= $(CURDIR)\nexport RTE_SRCDIR\n\n#\n# Makefile to call once $(RTE_OUTPUT) is created\n#\nifdef M\nifeq (\"$(origin M)\", \"command line\")\nRTE_EXTMK := $(abspath $(M))\nendif\nendif\nRTE_EXTMK ?= $(RTE_SRCDIR)/Makefile\nexport RTE_EXTMK\n\nRTE_SDK_BIN := $(RTE_SDK)/$(RTE_TARGET)\n\n#\n# Output files wil go in a separate directory: default output is\n# $(RTE_SRCDIR)/build\n# Output dir can be given as command line using \"O=\"\n#\nifdef O\nifeq (\"$(origin O)\", \"command line\")\nRTE_OUTPUT := $(abspath $(O))\nendif\nendif\nRTE_OUTPUT ?= $(RTE_SRCDIR)/build\nexport RTE_OUTPUT\n\n# if we are building an external application, include SDK\n# configuration and include project configuration if any\ninclude $(RTE_SDK_BIN)/.config\nifneq ($(wildcard $(RTE_OUTPUT)/.config),)\n include $(RTE_OUTPUT)/.config\nendif\n# remove double-quotes from config names\nRTE_ARCH := $(CONFIG_RTE_ARCH:\"%\"=%)\nRTE_MACHINE := $(CONFIG_RTE_MACHINE:\"%\"=%)\nRTE_EXEC_ENV := $(CONFIG_RTE_EXEC_ENV:\"%\"=%)\nRTE_TOOLCHAIN := $(CONFIG_RTE_TOOLCHAIN:\"%\"=%)\n" }, { "path": "mk/internal/rte.install-post.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# install helper .mk\n\n#\n# generate rules to install files in RTE_OUTPUT.\n#\n# arg1: relative install dir in RTE_OUTPUT\n# arg2: relative file name in a source dir (VPATH)\n#\ndefine install_rule\n$(addprefix $(RTE_OUTPUT)/$(1)/,$(notdir $(2))): $(2)\n\t@echo \" INSTALL-FILE $(addprefix $(1)/,$(notdir $(2)))\"\n\t@[ -d $(RTE_OUTPUT)/$(1) ] || mkdir -p $(RTE_OUTPUT)/$(1)\n\t$(Q)cp -rf $$(<) $(RTE_OUTPUT)/$(1)\nendef\n\n$(foreach dir,$(INSTALL-DIRS-y),\\\n\t$(foreach file,$(INSTALL-y-$(dir)),\\\n\t\t$(eval $(call install_rule,$(dir),$(file)))))\n\n\n#\n# generate rules to install symbolic links of files in RTE_OUTPUT.\n#\n# arg1: relative install dir in RTE_OUTPUT\n# arg2: relative file name in a source dir (VPATH)\n#\ndefine symlink_rule\n$(addprefix $(RTE_OUTPUT)/$(1)/,$(notdir $(2))): $(2)\n\t@echo \" SYMLINK-FILE $(addprefix $(1)/,$(notdir $(2)))\"\n\t@[ -d $(RTE_OUTPUT)/$(1) ] || mkdir -p $(RTE_OUTPUT)/$(1)\n\t$(Q)ln -nsf `$(RTE_SDK)/scripts/relpath.sh $$(<) $(RTE_OUTPUT)/$(1)` \\\n\t\t$(RTE_OUTPUT)/$(1)\nendef\n\n$(foreach dir,$(SYMLINK-DIRS-y),\\\n\t$(foreach file,$(SYMLINK-y-$(dir)),\\\n\t\t$(eval $(call symlink_rule,$(dir),$(file)))))\n\n\n# fast way, no need to do preinstall and postinstall\nifeq ($(PREINSTALL)$(POSTINSTALL),)\n\n_postinstall: $(_INSTALL)\n\t@touch _postinstall\n\nelse # slower way\n\n_preinstall: $(PREINSTALL)\n\t@touch _preinstall\n\nifneq ($(_INSTALL),)\n$(_INSTALL): _preinstall\nelse\n_INSTALL = _preinstall\nendif\n\n_install: $(_INSTALL)\n\t@touch _install\n\nifneq ($(POSTINSTALL),)\n$(POSTINSTALL): _install\nelse\nPOSTINSTALL = _install\nendif\n\n_postinstall: $(POSTINSTALL)\n\t@touch _postinstall\nendif\n" }, { "path": "mk/internal/rte.install-pre.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# get all variables starting with \"INSTALL-y-\", and extract the\n# installation dir and path\n#\nINSTALL-y := $(filter INSTALL-y-%,$(.VARIABLES))\nINSTALL-n := $(filter INSTALL-n-%,$(.VARIABLES))\nINSTALL- := $(filter INSTALL--%,$(.VARIABLES))\nINSTALL-DIRS-y := $(patsubst INSTALL-y-%,%,$(INSTALL-y))\nINSTALL-FILES-y := $(foreach i,$(INSTALL-DIRS-y),\\\n\t$(addprefix $(RTE_OUTPUT)/$(i)/,$(notdir $(INSTALL-y-$(i)))))\nINSTALL-FILES-all := $(foreach i,$(INSTALL-DIRS-y) $(INSTALL-DIRS-n) $(INSTALL-DIRS-),\\\n\t$(addprefix $(RTE_OUTPUT)/$(i)/,$(notdir $(INSTALL-y-$(i)))))\n\n_INSTALL_TARGETS := _preinstall _install _postinstall\n\n#\n# get all variables starting with \"SYMLINK-y-\", and extract the\n# installation dir and path\n#\nSYMLINK-y := $(filter SYMLINK-y-%,$(.VARIABLES))\nSYMLINK-n := $(filter SYMLINK-n-%,$(.VARIABLES))\nSYMLINK- := $(filter SYMLINK--%,$(.VARIABLES))\nSYMLINK-DIRS-y := $(patsubst SYMLINK-y-%,%,$(SYMLINK-y))\nSYMLINK-FILES-y := $(foreach i,$(SYMLINK-DIRS-y),\\\n\t$(addprefix $(RTE_OUTPUT)/$(i)/,$(notdir $(SYMLINK-y-$(i)))))\nSYMLINK-FILES-all := $(foreach i,$(SYMLINK-DIRS-y) $(SYMLINK-DIRS-n) $(SYMLINK-DIRS-),\\\n\t$(addprefix $(RTE_OUTPUT)/$(i)/,$(notdir $(SYMLINK-y-$(i)))))\n\n_SYMLINK_TARGETS := _presymlink _symlink _postsymlink\n" }, { "path": "mk/machine/atm/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# machine:\n#\n# - can define ARCH variable (overriden by cmdline value)\n# - can define CROSS variable (overriden by cmdline value)\n# - define MACHINE_CFLAGS variable (overriden by cmdline value)\n# - define MACHINE_LDFLAGS variable (overriden by cmdline value)\n# - define MACHINE_ASFLAGS variable (overriden by cmdline value)\n# - can define CPU_CFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_LDFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_ASFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - may override any previously defined variable\n#\n\n# ARCH =\n# CROSS =\n# MACHINE_CFLAGS =\n# MACHINE_LDFLAGS =\n# MACHINE_ASFLAGS =\n# CPU_CFLAGS =\n# CPU_LDFLAGS =\n# CPU_ASFLAGS =\n\nMACHINE_CFLAGS = -march=atom\n" }, { "path": "mk/machine/default/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# machine:\n#\n# - can define ARCH variable (overriden by cmdline value)\n# - can define CROSS variable (overriden by cmdline value)\n# - define MACHINE_CFLAGS variable (overriden by cmdline value)\n# - define MACHINE_LDFLAGS variable (overriden by cmdline value)\n# - define MACHINE_ASFLAGS variable (overriden by cmdline value)\n# - can define CPU_CFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_LDFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_ASFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - may override any previously defined variable\n#\n\n# ARCH =\n# CROSS =\n# MACHINE_CFLAGS =\n# MACHINE_LDFLAGS =\n# MACHINE_ASFLAGS =\n# CPU_CFLAGS =\n# CPU_LDFLAGS =\n# CPU_ASFLAGS =\n\nMACHINE_CFLAGS += -march=core2\n" }, { "path": "mk/machine/hsw/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# machine:\n#\n# - can define ARCH variable (overriden by cmdline value)\n# - can define CROSS variable (overriden by cmdline value)\n# - define MACHINE_CFLAGS variable (overriden by cmdline value)\n# - define MACHINE_LDFLAGS variable (overriden by cmdline value)\n# - define MACHINE_ASFLAGS variable (overriden by cmdline value)\n# - can define CPU_CFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_LDFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_ASFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - may override any previously defined variable\n#\n\n# ARCH =\n# CROSS =\n# MACHINE_CFLAGS =\n# MACHINE_LDFLAGS =\n# MACHINE_ASFLAGS =\n# CPU_CFLAGS =\n# CPU_LDFLAGS =\n# CPU_ASFLAGS =\n\nMACHINE_CFLAGS = -march=core-avx2\n" }, { "path": "mk/machine/ivb/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# machine:\n#\n# - can define ARCH variable (overriden by cmdline value)\n# - can define CROSS variable (overriden by cmdline value)\n# - define MACHINE_CFLAGS variable (overriden by cmdline value)\n# - define MACHINE_LDFLAGS variable (overriden by cmdline value)\n# - define MACHINE_ASFLAGS variable (overriden by cmdline value)\n# - can define CPU_CFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_LDFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_ASFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - may override any previously defined variable\n#\n\n# ARCH =\n# CROSS =\n# MACHINE_CFLAGS =\n# MACHINE_LDFLAGS =\n# MACHINE_ASFLAGS =\n# CPU_CFLAGS =\n# CPU_LDFLAGS =\n# CPU_ASFLAGS =\n\nMACHINE_CFLAGS = -march=core-avx-i\n" }, { "path": "mk/machine/native/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# machine:\n#\n# - can define ARCH variable (overriden by cmdline value)\n# - can define CROSS variable (overriden by cmdline value)\n# - define MACHINE_CFLAGS variable (overriden by cmdline value)\n# - define MACHINE_LDFLAGS variable (overriden by cmdline value)\n# - define MACHINE_ASFLAGS variable (overriden by cmdline value)\n# - can define CPU_CFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_LDFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_ASFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - may override any previously defined variable\n#\n\n# ARCH =\n# CROSS =\n# MACHINE_CFLAGS =\n# MACHINE_LDFLAGS =\n# MACHINE_ASFLAGS =\n# CPU_CFLAGS =\n# CPU_LDFLAGS =\n# CPU_ASFLAGS =\n\nMACHINE_CFLAGS = -march=native\n\n# On FreeBSD systems, sometimes the correct CPU type is not picked up.\n# To get everything to compile, we need SSE4.2 support, so check if that is\n# reported by compiler. If not, check if the CPU actually supports it, and if\n# so, set the compilation target to be a corei7, minimum target with SSE4.2.\nSSE42_SUPPORT=$(shell $(CC) -march=native -dM -E - /dev/null)\n ifneq ($(CPU_SSE42_SUPPORT),)\n MACHINE_CFLAGS = -march=corei7\n endif\nendif\n" }, { "path": "mk/machine/nhm/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# machine:\n#\n# - can define ARCH variable (overriden by cmdline value)\n# - can define CROSS variable (overriden by cmdline value)\n# - define MACHINE_CFLAGS variable (overriden by cmdline value)\n# - define MACHINE_LDFLAGS variable (overriden by cmdline value)\n# - define MACHINE_ASFLAGS variable (overriden by cmdline value)\n# - can define CPU_CFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_LDFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_ASFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - may override any previously defined variable\n#\n\n# ARCH =\n# CROSS =\n# MACHINE_CFLAGS =\n# MACHINE_LDFLAGS =\n# MACHINE_ASFLAGS =\n# CPU_CFLAGS =\n# CPU_LDFLAGS =\n# CPU_ASFLAGS =\n\nMACHINE_CFLAGS = -march=corei7\n" }, { "path": "mk/machine/power8/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright (C) IBM Corporation 2014.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of IBM Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# machine:\n#\n# - can define ARCH variable (overridden by cmdline value)\n# - can define CROSS variable (overridden by cmdline value)\n# - define MACHINE_CFLAGS variable (overridden by cmdline value)\n# - define MACHINE_LDFLAGS variable (overridden by cmdline value)\n# - define MACHINE_ASFLAGS variable (overridden by cmdline value)\n# - can define CPU_CFLAGS variable (overridden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_LDFLAGS variable (overridden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_ASFLAGS variable (overridden by cmdline value) that\n# overrides the one defined in arch.\n# - may override any previously defined variable\n#\n\n# ARCH =\n# CROSS =\n# MACHINE_CFLAGS =\n# MACHINE_LDFLAGS =\n# MACHINE_ASFLAGS =\n# CPU_CFLAGS =\n# CPU_LDFLAGS =\n# CPU_ASFLAGS =\n\nMACHINE_CFLAGS =\n" }, { "path": "mk/machine/snb/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# machine:\n#\n# - can define ARCH variable (overriden by cmdline value)\n# - can define CROSS variable (overriden by cmdline value)\n# - define MACHINE_CFLAGS variable (overriden by cmdline value)\n# - define MACHINE_LDFLAGS variable (overriden by cmdline value)\n# - define MACHINE_ASFLAGS variable (overriden by cmdline value)\n# - can define CPU_CFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_LDFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_ASFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - may override any previously defined variable\n#\n\n# ARCH =\n# CROSS =\n# MACHINE_CFLAGS =\n# MACHINE_LDFLAGS =\n# MACHINE_ASFLAGS =\n# CPU_CFLAGS =\n# CPU_LDFLAGS =\n# CPU_ASFLAGS =\n\nMACHINE_CFLAGS = -march=corei7-avx\n" }, { "path": "mk/machine/tilegx/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright (C) EZchip Semiconductor Ltd. 2015.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of EZchip Semiconductor nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# machine:\n#\n# - can define ARCH variable (overridden by cmdline value)\n# - can define CROSS variable (overridden by cmdline value)\n# - define MACHINE_CFLAGS variable (overridden by cmdline value)\n# - define MACHINE_LDFLAGS variable (overridden by cmdline value)\n# - define MACHINE_ASFLAGS variable (overridden by cmdline value)\n# - can define CPU_CFLAGS variable (overridden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_LDFLAGS variable (overridden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_ASFLAGS variable (overridden by cmdline value) that\n# overrides the one defined in arch.\n# - may override any previously defined variable\n#\n\n# ARCH =\n# CROSS =\n# MACHINE_CFLAGS =\n# MACHINE_LDFLAGS =\n# MACHINE_ASFLAGS =\n# CPU_CFLAGS =\n# CPU_LDFLAGS =\n# CPU_ASFLAGS =\n\nMACHINE_CFLAGS =\n" }, { "path": "mk/machine/wsm/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# machine:\n#\n# - can define ARCH variable (overriden by cmdline value)\n# - can define CROSS variable (overriden by cmdline value)\n# - define MACHINE_CFLAGS variable (overriden by cmdline value)\n# - define MACHINE_LDFLAGS variable (overriden by cmdline value)\n# - define MACHINE_ASFLAGS variable (overriden by cmdline value)\n# - can define CPU_CFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_LDFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_ASFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - may override any previously defined variable\n#\n\n# ARCH =\n# CROSS =\n# MACHINE_CFLAGS =\n# MACHINE_LDFLAGS =\n# MACHINE_ASFLAGS =\n# CPU_CFLAGS =\n# CPU_LDFLAGS =\n# CPU_ASFLAGS =\n\nMACHINE_CFLAGS = -march=corei7 -maes -mpclmul\n" }, { "path": "mk/rte.app.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# Copyright(c) 2014-2015 6WIND S.A.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/internal/rte.compile-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-pre.mk\n\n# VPATH contains at least SRCDIR\nVPATH += $(SRCDIR)\n\n_BUILD = $(APP)\n_INSTALL = $(INSTALL-FILES-y) $(SYMLINK-FILES-y)\n_INSTALL += $(RTE_OUTPUT)/app/$(APP) $(RTE_OUTPUT)/app/$(APP).map\nPOSTINSTALL += target-appinstall\n_CLEAN = doclean\nPOSTCLEAN += target-appclean\n\nifeq ($(NO_LDSCRIPT),)\nLDSCRIPT = $(RTE_LDSCRIPT)\nendif\n\n# default path for libs\n_LDLIBS-y += -L$(RTE_SDK_BIN)/lib\n\n#\n# Order is important: from higher level to lower level\n#\n\n_LDLIBS-y += --whole-archive\n\n_LDLIBS-$(CONFIG_RTE_BUILD_COMBINE_LIBS) += -l$(RTE_LIBNAME)\n\nifeq ($(CONFIG_RTE_BUILD_COMBINE_LIBS),n)\n\n_LDLIBS-$(CONFIG_RTE_LIBRTE_DISTRIBUTOR) += -lrte_distributor\n_LDLIBS-$(CONFIG_RTE_LIBRTE_REORDER) += -lrte_reorder\n\nifeq ($(CONFIG_RTE_EXEC_ENV_LINUXAPP),y)\n_LDLIBS-$(CONFIG_RTE_LIBRTE_KNI) += -lrte_kni\n_LDLIBS-$(CONFIG_RTE_LIBRTE_IVSHMEM) += -lrte_ivshmem\nendif\n\n_LDLIBS-$(CONFIG_RTE_LIBRTE_PIPELINE) += -lrte_pipeline\n_LDLIBS-$(CONFIG_RTE_LIBRTE_TABLE) += -lrte_table\n_LDLIBS-$(CONFIG_RTE_LIBRTE_PORT) += -lrte_port\n_LDLIBS-$(CONFIG_RTE_LIBRTE_TIMER) += -lrte_timer\n_LDLIBS-$(CONFIG_RTE_LIBRTE_HASH) += -lrte_hash\n_LDLIBS-$(CONFIG_RTE_LIBRTE_JOBSTATS) += -lrte_jobstats\n_LDLIBS-$(CONFIG_RTE_LIBRTE_LPM) += -lrte_lpm\n_LDLIBS-$(CONFIG_RTE_LIBRTE_POWER) += -lrte_power\n_LDLIBS-$(CONFIG_RTE_LIBRTE_ACL) += -lrte_acl\n_LDLIBS-$(CONFIG_RTE_LIBRTE_METER) += -lrte_meter\n\n_LDLIBS-$(CONFIG_RTE_LIBRTE_SCHED) += -lrte_sched\n_LDLIBS-$(CONFIG_RTE_LIBRTE_SCHED) += -lm\n_LDLIBS-$(CONFIG_RTE_LIBRTE_SCHED) += -lrt\n\n_LDLIBS-$(CONFIG_RTE_LIBRTE_VHOST) += -lrte_vhost\n\nendif # ! CONFIG_RTE_BUILD_COMBINE_LIBS\n\n_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_PCAP) += -lpcap\n\nifeq ($(CONFIG_RTE_LIBRTE_VHOST_NUMA),y)\n_LDLIBS-$(CONFIG_RTE_LIBRTE_VHOST) += -lnuma\nendif\n\nifeq ($(CONFIG_RTE_LIBRTE_VHOST_USER),n)\n_LDLIBS-$(CONFIG_RTE_LIBRTE_VHOST) += -lfuse\nendif\n\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),n)\n_LDLIBS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += -libverbs\nendif # ! CONFIG_RTE_BUILD_SHARED_LIBS\n\n_LDLIBS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += -lz\n\n_LDLIBS-y += --start-group\n\nifeq ($(CONFIG_RTE_BUILD_COMBINE_LIBS),n)\n\n_LDLIBS-$(CONFIG_RTE_LIBRTE_KVARGS) += -lrte_kvargs\n_LDLIBS-$(CONFIG_RTE_LIBRTE_MBUF) += -lrte_mbuf\n_LDLIBS-$(CONFIG_RTE_LIBRTE_IP_FRAG) += -lrte_ip_frag\n_LDLIBS-$(CONFIG_RTE_LIBRTE_ETHER) += -lethdev\n_LDLIBS-$(CONFIG_RTE_LIBRTE_MALLOC) += -lrte_malloc\n_LDLIBS-$(CONFIG_RTE_LIBRTE_MEMPOOL) += -lrte_mempool\n_LDLIBS-$(CONFIG_RTE_LIBRTE_RING) += -lrte_ring\n_LDLIBS-$(CONFIG_RTE_LIBRTE_EAL) += -lrte_eal\n_LDLIBS-$(CONFIG_RTE_LIBRTE_CMDLINE) += -lrte_cmdline\n_LDLIBS-$(CONFIG_RTE_LIBRTE_CFGFILE) += -lrte_cfgfile\n_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_BOND) += -lrte_pmd_bond\n\n_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_XENVIRT) += -lrte_pmd_xenvirt\n_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_XENVIRT) += -lxenstore\n\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),n)\n# plugins (link only if static libraries)\n\n_LDLIBS-$(CONFIG_RTE_LIBRTE_VMXNET3_PMD) += -lrte_pmd_vmxnet3_uio\n_LDLIBS-$(CONFIG_RTE_LIBRTE_VIRTIO_PMD) += -lrte_pmd_virtio\n_LDLIBS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += -lrte_pmd_bnx2x\n_LDLIBS-$(CONFIG_RTE_LIBRTE_CXGBE_PMD) += -lrte_pmd_cxgbe\n_LDLIBS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += -lrte_pmd_enic\n_LDLIBS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += -lrte_pmd_i40e\n_LDLIBS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += -lrte_pmd_fm10k\n_LDLIBS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += -lrte_pmd_ixgbe\n_LDLIBS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += -lrte_pmd_e1000\n_LDLIBS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += -lrte_pmd_mlx4\n_LDLIBS-$(CONFIG_RTE_LIBRTE_MPIPE_PMD) += -lrte_pmd_mpipe -lgxio\n_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_RING) += -lrte_pmd_ring\n_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_PCAP) += -lrte_pmd_pcap\n_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_AF_PACKET) += -lrte_pmd_af_packet\n_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NULL) += -lrte_pmd_null\n\nendif # ! $(CONFIG_RTE_BUILD_SHARED_LIB)\n\nendif # ! CONFIG_RTE_BUILD_COMBINE_LIBS\n\n_LDLIBS-y += $(EXECENV_LDLIBS)\n_LDLIBS-y += --end-group\n_LDLIBS-y += --no-whole-archive\n\nLDLIBS += $(_LDLIBS-y) $(CPU_LDLIBS) $(EXTRA_LDLIBS)\n\n.PHONY: all\nall: install\n\n.PHONY: install\ninstall: build _postinstall\n\n_postinstall: build\n\n.PHONY: build\nbuild: _postbuild\n\nexe2cmd = $(strip $(call dotfile,$(patsubst %,%.cmd,$(1))))\n\nifeq ($(LINK_USING_CC),1)\noverride EXTRA_LDFLAGS := $(call linkerprefix,$(EXTRA_LDFLAGS))\nO_TO_EXE = $(CC) $(CFLAGS) $(LDFLAGS_$(@)) \\\n\t-Wl,-Map=$(@).map,--cref -o $@ $(OBJS-y) $(call linkerprefix,$(LDFLAGS)) \\\n\t$(EXTRA_LDFLAGS) $(call linkerprefix,$(LDLIBS))\nelse\nO_TO_EXE = $(LD) $(LDFLAGS) $(LDFLAGS_$(@)) $(EXTRA_LDFLAGS) \\\n\t-Map=$(@).map --cref -o $@ $(OBJS-y) $(LDLIBS)\nendif\nO_TO_EXE_STR = $(subst ','\\'',$(O_TO_EXE)) #'# fix syntax highlight\nO_TO_EXE_DISP = $(if $(V),\"$(O_TO_EXE_STR)\",\" LD $(@)\")\nO_TO_EXE_CMD = \"cmd_$@ = $(O_TO_EXE_STR)\"\nO_TO_EXE_DO = @set -e; \\\n\techo $(O_TO_EXE_DISP); \\\n\t$(O_TO_EXE) && \\\n\techo $(O_TO_EXE_CMD) > $(call exe2cmd,$(@))\n\n-include .$(APP).cmd\n\n# path where libraries are retrieved\nLDLIBS_PATH := $(subst -Wl$(comma)-L,,$(filter -Wl$(comma)-L%,$(LDLIBS)))\nLDLIBS_PATH += $(subst -L,,$(filter -L%,$(LDLIBS)))\n\n# list of .a files that are linked to this application\nLDLIBS_NAMES := $(patsubst -l%,lib%.a,$(filter -l%,$(LDLIBS)))\nLDLIBS_NAMES += $(patsubst -Wl$(comma)-l%,lib%.a,$(filter -Wl$(comma)-l%,$(LDLIBS)))\n\n# list of found libraries files (useful for deps). If not found, the\n# library is silently ignored and dep won't be checked\nLDLIBS_FILES := $(wildcard $(foreach dir,$(LDLIBS_PATH),\\\n\t$(addprefix $(dir)/,$(LDLIBS_NAMES))))\n\n#\n# Compile executable file if needed\n#\n$(APP): $(OBJS-y) $(LDLIBS_FILES) $(DEP_$(APP)) $(LDSCRIPT) FORCE\n\t@[ -d $(dir $@) ] || mkdir -p $(dir $@)\n\t$(if $(D),\\\n\t\t@echo -n \"$< -> $@ \" ; \\\n\t\techo -n \"file_missing=$(call boolean,$(file_missing)) \" ; \\\n\t\techo -n \"cmdline_changed=$(call boolean,$(call cmdline_changed,$(O_TO_EXE_STR))) \" ; \\\n\t\techo -n \"depfile_missing=$(call boolean,$(depfile_missing)) \" ; \\\n\t\techo \"depfile_newer=$(call boolean,$(depfile_newer)) \")\n\t$(if $(or \\\n\t\t$(file_missing),\\\n\t\t$(call cmdline_changed,$(O_TO_EXE_STR)),\\\n\t\t$(depfile_missing),\\\n\t\t$(depfile_newer)),\\\n\t\t$(O_TO_EXE_DO))\n\n#\n# install app in $(RTE_OUTPUT)/app\n#\n$(RTE_OUTPUT)/app/$(APP): $(APP)\n\t@echo \" INSTALL-APP $(APP)\"\n\t@[ -d $(RTE_OUTPUT)/app ] || mkdir -p $(RTE_OUTPUT)/app\n\t$(Q)cp -f $(APP) $(RTE_OUTPUT)/app\n\n#\n# install app map file in $(RTE_OUTPUT)/app\n#\n$(RTE_OUTPUT)/app/$(APP).map: $(APP)\n\t@echo \" INSTALL-MAP $(APP).map\"\n\t@[ -d $(RTE_OUTPUT)/app ] || mkdir -p $(RTE_OUTPUT)/app\n\t$(Q)cp -f $(APP).map $(RTE_OUTPUT)/app\n\n#\n# Clean all generated files\n#\n.PHONY: clean\nclean: _postclean\n\t$(Q)rm -f $(_BUILD_TARGETS) $(_INSTALL_TARGETS) $(_CLEAN_TARGETS)\n\n.PHONY: doclean\ndoclean:\n\t$(Q)rm -rf $(APP) $(OBJS-all) $(DEPS-all) $(DEPSTMP-all) \\\n\t $(CMDS-all) $(INSTALL-FILES-all) .$(APP).cmd\n\n\ninclude $(RTE_SDK)/mk/internal/rte.compile-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-post.mk\n\nifneq ($(wildcard $(RTE_SDK)/mk/target/$(RTE_TARGET)/rte.app.mk),)\ninclude $(RTE_SDK)/mk/target/$(RTE_TARGET)/rte.app.mk\nelse\ninclude $(RTE_SDK)/mk/target/generic/rte.app.mk\nendif\n\n.PHONY: FORCE\nFORCE:\n" }, { "path": "mk/rte.bsdmodule.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n##### if sourced from kernel Kbuild system\nifneq ($(KERNELRELEASE),)\noverride EXTRA_CFLAGS = $(MODULE_CFLAGS) $(EXTRA_KERNEL_CFLAGS)\nobj-m += $(MODULE).o\nifneq ($(MODULE),$(notdir $(SRCS-y:%.c=%)))\n$(MODULE)-objs += $(notdir $(SRCS-y:%.c=%.o))\nendif\n\n##### if launched from rte build system\nelse\n\ninclude $(RTE_SDK)/mk/internal/rte.install-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-pre.mk\n\n# DPDK uses a more up-to-date gcc, so clear the override here.\nunexport CC\noverride CFLAGS = $(MODULE_CFLAGS)\n\n# VPATH contains at least SRCDIR\nVPATH += $(SRCDIR)\n\n_BUILD = $(MODULE).ko\n_INSTALL = $(INSTALL-FILES-y) $(SYMLINK-FILES-y) \\\n\t$(RTE_OUTPUT)/kmod/$(MODULE).ko\n_CLEAN = doclean\n\nSRCS_LINKS = $(addsuffix _link,$(SRCS-y))\n\ncompare = $(strip $(subst $(1),,$(2)) $(subst $(2),,$(1)))\n\n.PHONY: all\nall: install\n\n.PHONY: install\ninstall: build _postinstall\n\n_postinstall: build\n\n.PHONY: build\nbuild: _postbuild\n\n# Link all sources in build directory\n%_link: FORCE\n\t$(if $(call compare,$(notdir $*),$*),\\\n\t$(Q)if [ ! -f $(notdir $(*)) ]; then ln -nfs $(SRCDIR)/$(*) . ; fi,\\\n\t$(Q)if [ ! -f $(notdir $(*)) ]; then ln -nfs $(SRCDIR)/$(*) . ; fi)\n\n# build module\n$(MODULE).ko: $(SRCS_LINKS)\n\t$(Q)if [ ! -f $(notdir Makefile) ]; then ln -nfs $(SRCDIR)/Makefile . ; fi\n\t$(Q)if [ ! -f $(notdir BSDmakefile) ]; then ln -nfs $(SRCDIR)/BSDmakefile . ; fi\n\t$(Q)MAKEFLAGS= $(BSDMAKE)\n\n# install module in $(RTE_OUTPUT)/kmod\n$(RTE_OUTPUT)/kmod/$(MODULE).ko: $(MODULE).ko\n\t$(Q)echo INSTALL-MODULE $(MODULE).ko\n\t$(Q)[ -d $(RTE_OUTPUT)/kmod ] || mkdir -p $(RTE_OUTPUT)/kmod\n\t$(Q)cp -f $(MODULE).ko $(RTE_OUTPUT)/kmod\n\n# install module\nmodules_install:\n\t$(Q)MAKEFLAGS= $(BSDMAKE) install\n\n.PHONY: clean\nclean: _postclean\n\n# do a make clean and remove links\n.PHONY: doclean\ndoclean:\n\t$(Q)if [ ! -f $(notdir Makefile) ]; then ln -nfs $(SRCDIR)/Makefile . ; fi\n\t$(Q)$(MAKE) -C $(RTE_KERNELDIR) M=$(CURDIR) O=$(RTE_KERNELDIR) clean\n\t$(Q)$(foreach FILE,$(SRCS-y) $(SRCS-n) $(SRCS-),\\\n\t\tif [ -h $(notdir $(FILE)) ]; then rm -f $(notdir $(FILE)) ; fi ;)\n\t$(Q)if [ -h $(notdir Makefile) ]; then rm -f $(notdir Makefile) ; fi\n\t$(Q)rm -f $(_BUILD_TARGETS) $(_INSTALL_TARGETS) $(_CLEAN_TARGETS) \\\n\t\t$(INSTALL-FILES-all)\n\ninclude $(RTE_SDK)/mk/internal/rte.install-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-post.mk\n\n.PHONY: FORCE\nFORCE:\n\nendif\n" }, { "path": "mk/rte.cpuflags.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# this makefile is called from the generic rte.vars.mk and is\n# used to set the RTE_CPUFLAG_* environment variables giving details\n# of what instruction sets the target cpu supports.\n\nAUTO_CPUFLAGS := $(shell $(CC) $(MACHINE_CFLAGS) -dM -E - < /dev/null)\n\n# adding flags to CPUFLAGS\n\nifneq ($(filter $(AUTO_CPUFLAGS),__SSE__),)\nCPUFLAGS += SSE\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__SSE2__),)\nCPUFLAGS += SSE2\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__SSE3__),)\nCPUFLAGS += SSE3\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__SSSE3__),)\nCPUFLAGS += SSSE3\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__SSE4_1__),)\nCPUFLAGS += SSE4_1\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__SSE4_2__),)\nCPUFLAGS += SSE4_2\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__AES__),)\nCPUFLAGS += AES\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__PCLMUL__),)\nCPUFLAGS += PCLMULQDQ\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__AVX__),)\nCPUFLAGS += AVX\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__RDRND__),)\nCPUFLAGS += RDRAND\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__FSGSBASE__),)\nCPUFLAGS += FSGSBASE\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__F16C__),)\nCPUFLAGS += F16C\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__AVX2__),)\nCPUFLAGS += AVX2\nendif\n\n# IBM Power CPU flags\nifneq ($(filter $(AUTO_CPUFLAGS),__PPC64__),)\nCPUFLAGS += PPC64\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__PPC32__),)\nCPUFLAGS += PPC32\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__vector),)\nCPUFLAGS += ALTIVEC\nendif\n\nifneq ($(filter $(AUTO_CPUFLAGS),__builtin_vsx_xvnmaddadp),)\nCPUFLAGS += VSX\nendif\n\nMACHINE_CFLAGS += $(addprefix -DRTE_MACHINE_CPUFLAG_,$(CPUFLAGS))\n\n# To strip whitespace\ncomma:= ,\nempty:=\nspace:= $(empty) $(empty)\nCPUFLAGSTMP1 := $(addprefix RTE_CPUFLAG_,$(CPUFLAGS))\nCPUFLAGSTMP2 := $(subst $(space),$(comma),$(CPUFLAGSTMP1))\nMACHINE_CFLAGS += -DRTE_COMPILE_TIME_CPUFLAGS=$(CPUFLAGSTMP2)\n" }, { "path": "mk/rte.extapp.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nMAKEFLAGS += --no-print-directory\n\n# we must create the output dir first and recall the same Makefile\n# from this directory\nifeq ($(NOT_FIRST_CALL),)\n\nNOT_FIRST_CALL = 1\nexport NOT_FIRST_CALL\n\nall:\n\t$(Q)mkdir -p $(RTE_OUTPUT)\n\t$(Q)$(MAKE) -C $(RTE_OUTPUT) -f $(RTE_EXTMK) \\\n\t\tS=$(RTE_SRCDIR) O=$(RTE_OUTPUT) SRCDIR=$(RTE_SRCDIR)\n\n%::\n\t$(Q)mkdir -p $(RTE_OUTPUT)\n\t$(Q)$(MAKE) -C $(RTE_OUTPUT) -f $(RTE_EXTMK) $@ \\\n\t\tS=$(RTE_SRCDIR) O=$(RTE_OUTPUT) SRCDIR=$(RTE_SRCDIR)\nelse\ninclude $(RTE_SDK)/mk/rte.app.mk\nendif\n" }, { "path": "mk/rte.extlib.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nMAKEFLAGS += --no-print-directory\n\n# we must create the output dir first and recall the same Makefile\n# from this directory\nifeq ($(NOT_FIRST_CALL),)\n\nNOT_FIRST_CALL = 1\nexport NOT_FIRST_CALL\n\nall:\n\t$(Q)mkdir -p $(RTE_OUTPUT)\n\t$(Q)$(MAKE) -C $(RTE_OUTPUT) -f $(RTE_EXTMK) \\\n\t\tS=$(RTE_SRCDIR) O=$(RTE_OUTPUT) SRCDIR=$(RTE_SRCDIR)\n\n%::\n\t$(Q)mkdir -p $(RTE_OUTPUT)\n\t$(Q)$(MAKE) -C $(RTE_OUTPUT) -f $(RTE_EXTMK) $@ \\\n\t\tS=$(RTE_SRCDIR) O=$(RTE_OUTPUT) SRCDIR=$(RTE_SRCDIR)\nelse\ninclude $(RTE_SDK)/mk/rte.lib.mk\nendif\n" }, { "path": "mk/rte.extobj.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nMAKEFLAGS += --no-print-directory\n\n# we must create the output dir first and recall the same Makefile\n# from this directory\nifeq ($(NOT_FIRST_CALL),)\n\nNOT_FIRST_CALL = 1\nexport NOT_FIRST_CALL\n\nall:\n\t$(Q)mkdir -p $(RTE_OUTPUT)\n\t$(Q)$(MAKE) -C $(RTE_OUTPUT) -f $(RTE_EXTMK) \\\n\t\tS=$(RTE_SRCDIR) O=$(RTE_OUTPUT) SRCDIR=$(RTE_SRCDIR)\n\n%::\n\t$(Q)mkdir -p $(RTE_OUTPUT)\n\t$(Q)$(MAKE) -C $(RTE_OUTPUT) -f $(RTE_EXTMK) $@ \\\n\t\tS=$(RTE_SRCDIR) O=$(RTE_OUTPUT) SRCDIR=$(RTE_SRCDIR)\nelse\ninclude $(RTE_SDK)/mk/rte.obj.mk\nendif\n" }, { "path": "mk/rte.extshared.mk", "content": "# BSD LICENSE\n#\n# Copyright 2012-2013 6WIND S.A.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nMAKEFLAGS += --no-print-directory\n\n# we must create the output dir first and recall the same Makefile\n# from this directory\nifeq ($(NOT_FIRST_CALL),)\n\nNOT_FIRST_CALL = 1\nexport NOT_FIRST_CALL\n\nall:\n\t$(Q)mkdir -p $(RTE_OUTPUT)\n\t$(Q)$(MAKE) -C $(RTE_OUTPUT) -f $(RTE_EXTMK) \\\n\t\tS=$(RTE_SRCDIR) O=$(RTE_OUTPUT) SRCDIR=$(RTE_SRCDIR)\n\t@echo $(RTE_OUTPUT)/lib must be added to /etc/ld.so.conf or \\\n\t\tLD_LIBRARY_PATH variable to allow binary to link with dynamic library\n\n%::\n\t$(Q)mkdir -p $(RTE_OUTPUT)\n\t$(Q)$(MAKE) -C $(RTE_OUTPUT) -f $(RTE_EXTMK) $@ \\\n\t\tS=$(RTE_SRCDIR) O=$(RTE_OUTPUT) SRCDIR=$(RTE_SRCDIR)\nelse\ninclude $(RTE_SDK)/mk/rte.shared.mk\nendif\n" }, { "path": "mk/rte.extsubdir.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2014 6WIND S.A.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nMAKEFLAGS += --no-print-directory\n\n# output directory\nO ?= .\nBASE_OUTPUT ?= $(O)\nCUR_SUBDIR ?= .\n\n.PHONY: all\nall: $(DIRS-y)\n\n.PHONY: clean\nclean: $(DIRS-y)\n\n.PHONY: $(DIRS-y)\n$(DIRS-y):\n\t@echo \"== $@\"\n\t$(Q)$(MAKE) -C $(@) \\\n\t\tM=$(CURDIR)/$(@)/Makefile \\\n\t\tO=$(BASE_OUTPUT)/$(CUR_SUBDIR)/$(@)/$(RTE_TARGET) \\\n\t\tBASE_OUTPUT=$(BASE_OUTPUT) \\\n\t\tCUR_SUBDIR=$(CUR_SUBDIR)/$(@) \\\n\t\tS=$(CURDIR)/$(@) \\\n\t\t$(filter-out $(DIRS-y),$(MAKECMDGOALS))\n" }, { "path": "mk/rte.gnuconfigure.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/internal/rte.build-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-pre.mk\n\n# VPATH contains at least SRCDIR\nVPATH += $(SRCDIR)\n_BUILD = configure\n_INSTALL = $(INSTALL-FILES-y) $(SYMLINK-FILES-y)\n_CLEAN = doclean\n\n.PHONY: all\nall: install\n\n.PHONY: install\ninstall: build _postinstall\n\n_postinstall: build\n\n.PHONY: build\nbuild: _postbuild\n\nconfigure:\n\t$(Q)cd $(CONFIGURE_PATH) ; \\\n\t./configure --prefix $(CONFIGURE_PREFIX) $(CONFIGURE_ARGS) ; \\\n\tmake ; \\\n\tmake install\n\n.PHONY: clean\nclean: _postclean\n\n.PHONY: doclean\ndoclean:\n\t$(Q)cd $(CONFIGURE_PATH) ; make clean\n\t$(Q)rm -f $(_INSTALL_TARGETS) $(_CLEAN_TARGETS)\n\ninclude $(RTE_SDK)/mk/internal/rte.build-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-post.mk\n\n.PHONY: FORCE\nFORCE:\n" }, { "path": "mk/rte.hostapp.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# tell rte.compile-pre.mk to use HOSTCC instead of CC\nUSE_HOST := 1\ninclude $(RTE_SDK)/mk/internal/rte.compile-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-pre.mk\n\n# VPATH contains at least SRCDIR\nVPATH += $(SRCDIR)\n\n_BUILD = $(HOSTAPP)\n_INSTALL = $(INSTALL-FILES-y) $(SYMLINK-FILES-y) $(RTE_OUTPUT)/hostapp/$(HOSTAPP)\n_CLEAN = doclean\n\n.PHONY: all\nall: install\n\n.PHONY: install\ninstall: build _postinstall\n\n_postinstall: build\n\n.PHONY: build\nbuild: _postbuild\n\nexe2cmd = $(strip $(call dotfile,$(patsubst %,%.cmd,$(1))))\n\nO_TO_EXE = $(HOSTCC) $(HOST_LDFLAGS) $(LDFLAGS_$(@)) \\\n\t$(EXTRA_HOST_LDFLAGS) -o $@ $(OBJS-y) $(LDLIBS)\nO_TO_EXE_STR = $(subst ','\\'',$(O_TO_EXE)) #'# fix syntax highlight\nO_TO_EXE_DISP = $(if $(V),\"$(O_TO_EXE_STR)\",\" HOSTLD $(@)\")\nO_TO_EXE_CMD = \"cmd_$@ = $(O_TO_EXE_STR)\"\nO_TO_EXE_DO = @set -e; \\\n\techo $(O_TO_EXE_DISP); \\\n\t$(O_TO_EXE) && \\\n\techo $(O_TO_EXE_CMD) > $(call exe2cmd,$(@))\n\n-include .$(HOSTAPP).cmd\n\n# list of .a files that are linked to this application\nLDLIBS_FILES := $(wildcard \\\n\t$(addprefix $(RTE_OUTPUT)/lib/, \\\n\t$(patsubst -l%,lib%.a,$(filter -l%,$(LDLIBS)))))\n\n#\n# Compile executable file if needed\n#\n$(HOSTAPP): $(OBJS-y) $(LDLIBS_FILES) FORCE\n\t@[ -d $(dir $@) ] || mkdir -p $(dir $@)\n\t$(if $(D),\\\n\t\t@echo -n \"$@ -> $< \" ; \\\n\t\techo -n \"file_missing=$(call boolean,$(file_missing)) \" ; \\\n\t\techo -n \"cmdline_changed=$(call boolean,$(call cmdline_changed,$(O_TO_EXE_STR))) \" ; \\\n\t\techo -n \"depfile_missing=$(call boolean,$(depfile_missing)) \" ; \\\n\t\techo \"depfile_newer=$(call boolean,$(depfile_newer)) \")\n\t$(if $(or \\\n\t\t$(file_missing),\\\n\t\t$(call cmdline_changed,$(O_TO_EXE_STR)),\\\n\t\t$(depfile_missing),\\\n\t\t$(depfile_newer)),\\\n\t\t$(O_TO_EXE_DO))\n\n#\n# install app in $(RTE_OUTPUT)/hostapp\n#\n$(RTE_OUTPUT)/hostapp/$(HOSTAPP): $(HOSTAPP)\n\t@echo \" INSTALL-HOSTAPP $(HOSTAPP)\"\n\t@[ -d $(RTE_OUTPUT)/hostapp ] || mkdir -p $(RTE_OUTPUT)/hostapp\n\t$(Q)cp -f $(HOSTAPP) $(RTE_OUTPUT)/hostapp\n\n#\n# Clean all generated files\n#\n.PHONY: clean\nclean: _postclean\n\t$(Q)rm -f $(_BUILD_TARGETS) $(_INSTALL_TARGETS) $(_CLEAN_TARGETS)\n\n.PHONY: doclean\ndoclean:\n\t$(Q)rm -rf $(HOSTAPP) $(OBJS-all) $(DEPS-all) $(DEPSTMP-all) \\\n\t $(CMDS-all) $(INSTALL-FILES-all) .$(HOSTAPP).cmd\n\n\ninclude $(RTE_SDK)/mk/internal/rte.compile-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-post.mk\n\n.PHONY: FORCE\nFORCE:\n" }, { "path": "mk/rte.hostlib.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# tell rte.compile-pre.mk to use HOSTCC instead of CC\nUSE_HOST := 1\ninclude $(RTE_SDK)/mk/internal/rte.compile-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-pre.mk\n\n# VPATH contains at least SRCDIR\nVPATH += $(SRCDIR)\n\n_BUILD = $(HOSTLIB)\n_INSTALL = $(INSTALL-FILES-y) $(SYMLINK-FILES-y) $(RTE_OUTPUT)/hostlib/$(HOSTLIB)\n_CLEAN = doclean\n\n.PHONY: all\nall: install\n\n.PHONY: install\ninstall: build _postinstall\n\n_postinstall: build\n\n.PHONY: build\nbuild: _postbuild\n\nexe2cmd = $(strip $(call dotfile,$(patsubst %,%.cmd,$(1))))\n\nO_TO_A = $(AR) crus $(HOSTLIB) $(OBJS-y)\nO_TO_A_STR = $(subst ','\\'',$(O_TO_A)) #'# fix syntax highlight\nO_TO_A_DISP = $(if $(V),\"$(O_TO_A_STR)\",\" HOSTAR $(@)\")\nO_TO_A_CMD = \"cmd_$@ = $(O_TO_A_STR)\"\nO_TO_A_DO = @set -e; \\\n\techo $(O_TO_A_DISP); \\\n\t$(O_TO_A) && \\\n\techo $(O_TO_A_CMD) > $(call exe2cmd,$(@))\n\n-include .$(HOSTLIB).cmd\n\n#\n# Archive objects in .a file if needed\n#\n$(HOSTLIB): $(OBJS-y) FORCE\n\t@[ -d $(dir $@) ] || mkdir -p $(dir $@)\n\t$(if $(D),\\\n\t\t@echo -n \"$@ -> $< \" ; \\\n\t\techo -n \"file_missing=$(call boolean,$(file_missing)) \" ; \\\n\t\techo -n \"cmdline_changed=$(call boolean,$(call cmdline_changed,$(O_TO_A_STR))) \" ; \\\n\t\techo -n \"depfile_missing=$(call boolean,$(depfile_missing)) \" ; \\\n\t\techo \"depfile_newer=$(call boolean,$(depfile_newer)) \")\n\t$(if $(or \\\n\t\t$(file_missing),\\\n\t\t$(call cmdline_changed,$(O_TO_A_STR)),\\\n\t\t$(depfile_missing),\\\n\t\t$(depfile_newer)),\\\n\t\t$(O_TO_A_DO))\n\n#\n# install lib in $(RTE_OUTPUT)/hostlib\n#\n$(RTE_OUTPUT)/hostlib/$(HOSTLIB): $(HOSTLIB)\n\t@echo \" INSTALL-HOSTLIB $(HOSTLIB)\"\n\t@[ -d $(RTE_OUTPUT)/hostlib ] || mkdir -p $(RTE_OUTPUT)/hostlib\n\t$(Q)cp -f $(HOSTLIB) $(RTE_OUTPUT)/hostlib\n\n#\n# Clean all generated files\n#\n.PHONY: clean\nclean: _postclean\n\n.PHONY: doclean\ndoclean:\n\t$(Q)rm -rf $(HOSTLIB) $(OBJS-all) $(DEPS-all) $(DEPSTMP-all) \\\n\t $(CMDS-all) $(INSTALL-FILES-all)\n\t$(Q)rm -f $(_BUILD_TARGETS) $(_INSTALL_TARGETS) $(_CLEAN_TARGETS)\n\ninclude $(RTE_SDK)/mk/internal/rte.compile-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-post.mk\n\n.PHONY: FORCE\nFORCE:\n" }, { "path": "mk/rte.install.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# install-only makefile (no build target)\n\ninclude $(RTE_SDK)/mk/internal/rte.install-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-pre.mk\n\n# VPATH contains at least SRCDIR\nVPATH += $(SRCDIR)\n\n_INSTALL = $(INSTALL-FILES-y) $(SYMLINK-FILES-y)\n_CLEAN = doclean\n\n.PHONY: all\nall: _postinstall\n\t@true\n\n.PHONY: clean\nclean: _postclean\n\n.PHONY: doclean\ndoclean:\n\t@rm -rf $(INSTALL-FILES-all)\n\t@rm -f $(_INSTALL_TARGETS) $(_CLEAN_TARGETS)\n\ninclude $(RTE_SDK)/mk/internal/rte.install-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-post.mk\n" }, { "path": "mk/rte.lib.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/internal/rte.compile-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-pre.mk\n\n# VPATH contains at least SRCDIR\nVPATH += $(SRCDIR)\n\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),y)\nLIB := $(patsubst %.a,%.so.$(LIBABIVER),$(LIB))\nifeq ($(CONFIG_RTE_NEXT_ABI),y)\nLIB := $(LIB).1\nendif\nCPU_LDFLAGS += --version-script=$(SRCDIR)/$(EXPORT_MAP)\nendif\n\n\n_BUILD = $(LIB)\n_INSTALL = $(INSTALL-FILES-y) $(SYMLINK-FILES-y) $(RTE_OUTPUT)/lib/$(LIB)\n_CLEAN = doclean\n\n.PHONY: all\nall: install\n\n.PHONY: install\ninstall: build _postinstall\n\n_postinstall: build\n\n.PHONY: build\nbuild: _postbuild\n\nexe2cmd = $(strip $(call dotfile,$(patsubst %,%.cmd,$(1))))\n\nifeq ($(LINK_USING_CC),1)\n# Override the definition of LD here, since we're linking with CC\nLD := $(CC) $(CPU_CFLAGS)\n_CPU_LDFLAGS := $(call linkerprefix,$(CPU_LDFLAGS))\nelse\n_CPU_LDFLAGS := $(CPU_LDFLAGS)\nendif\n\nO_TO_A = $(AR) crDs $(LIB) $(OBJS-y)\nO_TO_A_STR = $(subst ','\\'',$(O_TO_A)) #'# fix syntax highlight\nO_TO_A_DISP = $(if $(V),\"$(O_TO_A_STR)\",\" AR $(@)\")\nO_TO_A_CMD = \"cmd_$@ = $(O_TO_A_STR)\"\nO_TO_A_DO = @set -e; \\\n\techo $(O_TO_A_DISP); \\\n\t$(O_TO_A) && \\\n\techo $(O_TO_A_CMD) > $(call exe2cmd,$(@))\n\nO_TO_S = $(LD) $(_CPU_LDFLAGS) $(EXTRA_LDFLAGS) $(LDLIBS) -shared $(OBJS-y) \\\n\t -Wl,-soname,$(LIB) -o $(LIB)\nO_TO_S_STR = $(subst ','\\'',$(O_TO_S)) #'# fix syntax highlight\nO_TO_S_DISP = $(if $(V),\"$(O_TO_S_STR)\",\" LD $(@)\")\nO_TO_S_DO = @set -e; \\\n\techo $(O_TO_S_DISP); \\\n\t$(O_TO_S) && \\\n\techo $(O_TO_S_CMD) > $(call exe2cmd,$(@))\n\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),n)\nO_TO_C = $(AR) crus $(LIB_ONE) $(OBJS-y)\nO_TO_C_STR = $(subst ','\\'',$(O_TO_C)) #'# fix syntax highlight\nO_TO_C_DISP = $(if $(V),\"$(O_TO_C_STR)\",\" AR_C $(@)\")\nO_TO_C_DO = @set -e; \\\n\t$(lib_dir) \\\n\t$(copy_obj)\nelse\nO_TO_C = $(LD) -shared $(OBJS-y) -o $(LIB_ONE)\nO_TO_C_STR = $(subst ','\\'',$(O_TO_C)) #'# fix syntax highlight\nO_TO_C_DISP = $(if $(V),\"$(O_TO_C_STR)\",\" LD_C $(@)\")\nO_TO_C_DO = @set -e; \\\n\t$(lib_dir) \\\n\t$(copy_obj)\nendif\n\ncopy_obj = cp -f $(OBJS-y) $(RTE_OUTPUT)/build/lib;\nlib_dir = [ -d $(RTE_OUTPUT)/lib ] || mkdir -p $(RTE_OUTPUT)/lib;\n-include .$(LIB).cmd\n\n#\n# Archive objects in .a file if needed\n#\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),y)\n$(LIB): $(OBJS-y) $(DEP_$(LIB)) FORCE\nifeq ($(LIBABIVER),)\n\t@echo \"Must Specify a $(LIB) ABI version\"\n\t@false\nendif\n\t@[ -d $(dir $@) ] || mkdir -p $(dir $@)\n\t$(if $(D),\\\n\t\t@echo -n \"$< -> $@ \" ; \\\n\t\techo -n \"file_missing=$(call boolean,$(file_missing)) \" ; \\\n\t\techo -n \"cmdline_changed=$(call boolean,$(call cmdline_changed,$(O_TO_S_STR))) \" ; \\\n\t\techo -n \"depfile_missing=$(call boolean,$(depfile_missing)) \" ; \\\n\t\techo \"depfile_newer=$(call boolean,$(depfile_newer)) \")\n\t$(if $(or \\\n\t\t$(file_missing),\\\n\t\t$(call cmdline_changed,$(O_TO_S_STR)),\\\n\t\t$(depfile_missing),\\\n\t\t$(depfile_newer)),\\\n\t\t$(O_TO_S_DO))\n\nifeq ($(CONFIG_RTE_BUILD_COMBINE_LIBS),y)\n\t$(if $(or \\\n $(file_missing),\\\n $(call cmdline_changed,$(O_TO_C_STR)),\\\n $(depfile_missing),\\\n $(depfile_newer)),\\\n $(O_TO_C_DO))\nendif\nelse\n$(LIB): $(OBJS-y) $(DEP_$(LIB)) FORCE\n\t@[ -d $(dir $@) ] || mkdir -p $(dir $@)\n\t$(if $(D),\\\n\t @echo -n \"$< -> $@ \" ; \\\n\t echo -n \"file_missing=$(call boolean,$(file_missing)) \" ; \\\n\t echo -n \"cmdline_changed=$(call boolean,$(call cmdline_changed,$(O_TO_A_STR))) \" ; \\\n\t echo -n \"depfile_missing=$(call boolean,$(depfile_missing)) \" ; \\\n\t echo \"depfile_newer=$(call boolean,$(depfile_newer)) \")\n\t$(if $(or \\\n\t $(file_missing),\\\n\t $(call cmdline_changed,$(O_TO_A_STR)),\\\n\t $(depfile_missing),\\\n\t $(depfile_newer)),\\\n\t $(O_TO_A_DO))\nifeq ($(CONFIG_RTE_BUILD_COMBINE_LIBS),y)\n\t$(if $(or \\\n $(file_missing),\\\n $(call cmdline_changed,$(O_TO_C_STR)),\\\n $(depfile_missing),\\\n $(depfile_newer)),\\\n $(O_TO_C_DO))\nendif\nendif\n\n#\n# install lib in $(RTE_OUTPUT)/lib\n#\n$(RTE_OUTPUT)/lib/$(LIB): $(LIB)\n\t@echo \" INSTALL-LIB $(LIB)\"\n\t@[ -d $(RTE_OUTPUT)/lib ] || mkdir -p $(RTE_OUTPUT)/lib\n\t$(Q)cp -f $(LIB) $(RTE_OUTPUT)/lib\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),y)\nifeq ($(CONFIG_RTE_NEXT_ABI),y)\n\t$(Q)ln -s -f $< $(basename $(basename $@))\nelse\n\t$(Q)ln -s -f $< $(basename $@)\nendif\nendif\n\n#\n# Clean all generated files\n#\n.PHONY: clean\nclean: _postclean\n\n.PHONY: doclean\ndoclean:\n\t$(Q)rm -rf $(LIB) $(OBJS-all) $(DEPS-all) $(DEPSTMP-all) \\\n\t $(CMDS-all) $(INSTALL-FILES-all)\n\t$(Q)rm -f $(_BUILD_TARGETS) $(_INSTALL_TARGETS) $(_CLEAN_TARGETS)\n\ninclude $(RTE_SDK)/mk/internal/rte.compile-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-post.mk\n\n.PHONY: FORCE\nFORCE:\n" }, { "path": "mk/rte.module.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n##### if sourced from kernel Kbuild system\nifneq ($(KERNELRELEASE),)\noverride EXTRA_CFLAGS = $(MODULE_CFLAGS) $(EXTRA_KERNEL_CFLAGS)\nobj-m += $(MODULE).o\nifneq ($(MODULE),$(notdir $(SRCS-y:%.c=%)))\n$(MODULE)-objs += $(notdir $(SRCS-y:%.c=%.o))\nendif\n\n##### if launched from rte build system\nelse\n\ninclude $(RTE_SDK)/mk/internal/rte.install-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-pre.mk\n\n# VPATH contains at least SRCDIR\nVPATH += $(SRCDIR)\n\n_BUILD = $(MODULE).ko\n_INSTALL = $(INSTALL-FILES-y) $(SYMLINK-FILES-y) \\\n\t$(RTE_OUTPUT)/kmod/$(MODULE).ko\n_CLEAN = doclean\n\nSRCS_LINKS = $(addsuffix _link,$(SRCS-y))\n\ncompare = $(strip $(subst $(1),,$(2)) $(subst $(2),,$(1)))\n\n.PHONY: all\nall: install\n\n.PHONY: install\ninstall: build _postinstall\n\n_postinstall: build\n\n.PHONY: build\nbuild: _postbuild\n\n# Link all sources in build directory\n%_link: FORCE\n\t$(if $(call compare,$(notdir $*),$*),\\\n\t@if [ ! -f $(notdir $(*)) ]; then ln -nfs $(SRCDIR)/$(*) . ; fi,\\\n\t@if [ ! -f $(notdir $(*)) ]; then ln -nfs $(SRCDIR)/$(*) . ; fi)\n\n# build module\n$(MODULE).ko: $(SRCS_LINKS)\n\t@if [ ! -f $(notdir Makefile) ]; then ln -nfs $(SRCDIR)/Makefile . ; fi\n\t@$(MAKE) -C $(RTE_KERNELDIR) M=$(CURDIR) O=$(RTE_KERNELDIR) \\\n\t\tCC=$(KERNELCC) CROSS_COMPILE=$(CROSS) V=$(if $V,1,0)\n\n# install module in $(RTE_OUTPUT)/kmod\n$(RTE_OUTPUT)/kmod/$(MODULE).ko: $(MODULE).ko\n\t@echo INSTALL-MODULE $(MODULE).ko\n\t@[ -d $(RTE_OUTPUT)/kmod ] || mkdir -p $(RTE_OUTPUT)/kmod\n\t@cp -f $(MODULE).ko $(RTE_OUTPUT)/kmod\n\n# install module\nmodules_install:\n\t@$(MAKE) -C $(RTE_KERNELDIR) M=$(CURDIR) O=$(RTE_KERNELDIR) \\\n\t\tmodules_install\n\n.PHONY: clean\nclean: _postclean\n\n# do a make clean and remove links\n.PHONY: doclean\ndoclean:\n\t@if [ ! -f $(notdir Makefile) ]; then ln -nfs $(SRCDIR)/Makefile . ; fi\n\t$(Q)$(MAKE) -C $(RTE_KERNELDIR) M=$(CURDIR) O=$(RTE_KERNELDIR) clean\n\t@$(foreach FILE,$(SRCS-y) $(SRCS-n) $(SRCS-),\\\n\t\tif [ -h $(notdir $(FILE)) ]; then rm -f $(notdir $(FILE)) ; fi ;)\n\t@if [ -h $(notdir Makefile) ]; then rm -f $(notdir Makefile) ; fi\n\t@rm -f $(_BUILD_TARGETS) $(_INSTALL_TARGETS) $(_CLEAN_TARGETS) \\\n\t\t$(INSTALL-FILES-all)\n\ninclude $(RTE_SDK)/mk/internal/rte.install-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-post.mk\n\n.PHONY: FORCE\nFORCE:\n\nendif\n" }, { "path": "mk/rte.obj.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/internal/rte.compile-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-pre.mk\n\n# VPATH contains at least SRCDIR\nVPATH += $(SRCDIR)\n\nifneq ($(OBJ),)\n_BUILD = $(OBJ)\nelse\n_BUILD = $(OBJS-y)\nendif\n_INSTALL = $(INSTALL-FILES-y) $(SYMLINK-FILES-y)\n_CLEAN = doclean\n\n.PHONY: all\nall: install\n\n.PHONY: install\ninstall: build _postinstall\n\n_postinstall: build\n\n.PHONY: build\nbuild: _postbuild\n\nifneq ($(OBJ),)\nexe2cmd = $(strip $(call dotfile,$(patsubst %,%.cmd,$(1))))\n\nO_TO_O = $(LD) -r -o $(OBJ) $(OBJS-y)\nO_TO_O_STR = $(subst ','\\'',$(O_TO_O)) #'# fix syntax highlight\nO_TO_O_DISP = $(if $(V),\"$(O_TO_O_STR)\",\" LD $(@)\")\nO_TO_O_CMD = \"cmd_$@ = $(O_TO_O_STR)\"\nO_TO_O_DO = @set -e; \\\n\techo $(O_TO_O_DISP); \\\n\t$(O_TO_O) && \\\n\techo $(O_TO_O_CMD) > $(call exe2cmd,$(@))\n\n-include .$(OBJ).cmd\n\n#\n# Archive objects in .a file if needed\n#\n$(OBJ): $(OBJS-y) FORCE\n\t@[ -d $(dir $@) ] || mkdir -p $(dir $@)\n\t$(if $(D),\\\n\t\t@echo -n \"$< -> $@ \" ; \\\n\t\techo -n \"file_missing=$(call boolean,$(file_missing)) \" ; \\\n\t\techo -n \"cmdline_changed=$(call boolean,$(call cmdline_changed,$(O_TO_O_STR))) \" ; \\\n\t\techo -n \"depfile_missing=$(call boolean,$(depfile_missing)) \" ; \\\n\t\techo \"depfile_newer=$(call boolean,$(depfile_newer)) \")\n\t$(if $(or \\\n\t\t$(file_missing),\\\n\t\t$(call cmdline_changed,$(O_TO_O_STR)),\\\n\t\t$(depfile_missing),\\\n\t\t$(depfile_newer)),\\\n\t\t$(O_TO_O_DO))\nendif\n\n#\n# Clean all generated files\n#\n.PHONY: clean\nclean: _postclean\n\n.PHONY: doclean\ndoclean:\n\t@rm -rf $(OBJ) $(OBJS-all) $(DEPS-all) $(DEPSTMP-all) \\\n\t $(CMDS-all) $(INSTALL-FILES-all)\n\t@rm -f $(_BUILD_TARGETS) $(_INSTALL_TARGETS) $(_CLEAN_TARGETS)\n\ninclude $(RTE_SDK)/mk/internal/rte.compile-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-post.mk\n\n.PHONY: FORCE\nFORCE:\n" }, { "path": "mk/rte.sdkbuild.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# If DESTDIR variable is given, install binary dpdk\n\n#\n# include rte.vars.mk if config file exists\n#\nifeq (,$(wildcard $(RTE_OUTPUT)/.config))\n $(error \"need a make config first\")\nelse\n include $(RTE_SDK)/mk/rte.vars.mk\nendif\n\n#\n# include .depdirs and define rules to order priorities between build\n# of directories.\n#\n-include $(RTE_OUTPUT)/.depdirs\n\ndefine depdirs_rule\n$(1): $(sort $(LOCAL_DEPDIRS-$(1)))\nendef\n\n$(foreach d,$(ROOTDIRS-y),$(eval $(call depdirs_rule,$(d))))\n\n#\n# build and clean targets\n#\n\nCLEANDIRS = $(addsuffix _clean,$(ROOTDIRS-y) $(ROOTDIRS-n) $(ROOTDIRS-))\n\n.PHONY: build\nbuild: $(ROOTDIRS-y)\n\t@echo \"Build complete [$(RTE_TARGET)]\"\nifneq ($(DESTDIR),)\n\t$(Q)mkdir -p $(DESTDIR)\n\t$(Q)tar -C $(RTE_SDK) -cf - mk scripts/*.sh | tar -C $(DESTDIR) -x \\\n\t --keep-newer-files --warning=no-ignore-newer -f -\n\t$(Q)mkdir -p $(DESTDIR)/`basename $(RTE_OUTPUT)`\n\t$(Q)tar -C $(RTE_OUTPUT) -chf - \\\n\t --exclude app --exclude hostapp --exclude build \\\n\t --exclude Makefile --exclude .depdirs . | \\\n\t tar -C $(DESTDIR)/`basename $(RTE_OUTPUT)` -x --keep-newer-files \\\n\t --warning=no-ignore-newer -f -\n\t$(Q)install -D $(RTE_OUTPUT)/app/testpmd \\\n\t $(DESTDIR)/`basename $(RTE_OUTPUT)`/app/testpmd\n\t@echo Installation in $(DESTDIR) complete\nendif\n\n.PHONY: clean\nclean: $(CLEANDIRS)\n\t@rm -rf $(RTE_OUTPUT)/include $(RTE_OUTPUT)/app \\\n\t\t$(RTE_OUTPUT)/hostapp $(RTE_OUTPUT)/lib \\\n\t\t$(RTE_OUTPUT)/hostlib $(RTE_OUTPUT)/kmod\n\t@[ -d $(RTE_OUTPUT)/include ] || mkdir -p $(RTE_OUTPUT)/include\n\t@$(RTE_SDK)/scripts/gen-config-h.sh $(RTE_OUTPUT)/.config \\\n\t\t> $(RTE_OUTPUT)/include/rte_config.h\n\t$(Q)$(MAKE) -f $(RTE_SDK)/GNUmakefile gcovclean\n\t@echo Clean complete\n\n.SECONDEXPANSION:\n.PHONY: $(ROOTDIRS-y)\n$(ROOTDIRS-y):\n\t@[ -d $(BUILDDIR)/$@ ] || mkdir -p $(BUILDDIR)/$@\n\t@echo \"== Build $@\"\n\t$(Q)$(MAKE) S=$@ -f $(RTE_SRCDIR)/$@/Makefile -C $(BUILDDIR)/$@ all\n\t@if [ $@ = drivers -a $(CONFIG_RTE_BUILD_COMBINE_LIBS) = y ]; then \\\n\t\t$(MAKE) -f $(RTE_SDK)/lib/Makefile sharelib; \\\n\tfi\n\n%_clean:\n\t@echo \"== Clean $*\"\n\t$(Q)if [ -f $(RTE_SRCDIR)/$*/Makefile -a -d $(BUILDDIR)/$* ]; then \\\n\t\t$(MAKE) S=$* -f $(RTE_SRCDIR)/$*/Makefile -C $(BUILDDIR)/$* clean ; \\\n\tfi\n\nRTE_MAKE_SUBTARGET ?= all\n\n%_sub: $(addsuffix _sub,$(FULL_DEPDIRS-$(*)))\n\t@echo $(addsuffix _sub,$(FULL_DEPDIRS-$(*)))\n\t@[ -d $(BUILDDIR)/$* ] || mkdir -p $(BUILDDIR)/$*\n\t@echo \"== Build $*\"\n\t$(Q)$(MAKE) S=$* -f $(RTE_SRCDIR)/$*/Makefile -C $(BUILDDIR)/$* \\\n\t\t$(RTE_MAKE_SUBTARGET)\n\n.PHONY: all\nall: build\n\n.PHONY: FORCE\nFORCE:\n" }, { "path": "mk/rte.sdkconfig.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n.PHONY: showversion\nshowversion:\n\t@set -- \\\n\t\t$$(sed -rne 's,^#define RTE_VER_[A-Z_]*[[:space:]]+([0-9]+).*,\\1,p' \\\n\t\t\t-e 's,^#define RTE_VER_SUFFIX[[:space:]]+\"(.*)\",\\1,p' \\\n\t\t\t$(RTE_SRCDIR)/lib/librte_eal/common/include/rte_version.h) ;\\\n\t\tprintf '%d.%d.%d' \"$$1\" \"$$2\" \"$$3\"; \\\n\t\tif [ -z \"$$5\" ]; then echo; \\\n\t\telse printf '%s' \"$$4\"; \\\n\t\t\tif [ $$5 -lt 16 ] ; then echo $$5; \\\n\t\t\telse echo $$(($$5 - 16)); fi; \\\n\t\tfi\n\nINSTALL_CONFIGS := $(sort $(filter-out %~,\\\n\t$(patsubst $(RTE_SRCDIR)/config/defconfig_%,%,\\\n\t$(wildcard $(RTE_SRCDIR)/config/defconfig_*))))\nINSTALL_TARGETS := $(addsuffix _install,$(INSTALL_CONFIGS))\n\n.PHONY: showconfigs\nshowconfigs:\n\t@$(foreach CONFIG, $(INSTALL_CONFIGS), echo $(CONFIG);)\n\n.PHONY: notemplate\nnotemplate:\n\t@printf \"No template specified. \"\n\t@echo \"Use T=template among the following list:\"\n\t@$(MAKE) -rR showconfigs | sed 's,^, ,'\n\n.PHONY: config\nifeq ($(RTE_CONFIG_TEMPLATE),)\nconfig: notemplate\nelse\nconfig: $(RTE_OUTPUT)/include/rte_config.h $(RTE_OUTPUT)/Makefile\n\t$(Q)$(MAKE) depdirs\n\t@echo \"Configuration done\"\nendif\n\n$(RTE_OUTPUT):\n\t$(Q)mkdir -p $@\n\nifdef NODOTCONF\n$(RTE_OUTPUT)/.config: ;\nelse\n$(RTE_OUTPUT)/.config: $(RTE_CONFIG_TEMPLATE) FORCE | $(RTE_OUTPUT)\n\t$(Q)if [ \"$(RTE_CONFIG_TEMPLATE)\" != \"\" -a -f \"$(RTE_CONFIG_TEMPLATE)\" ]; then \\\n\t\t$(CPP) -undef -P -x assembler-with-cpp \\\n\t\t-ffreestanding \\\n\t\t-o $(RTE_OUTPUT)/.config_tmp $(RTE_CONFIG_TEMPLATE) ; \\\n\t\tif ! cmp -s $(RTE_OUTPUT)/.config_tmp $(RTE_OUTPUT)/.config; then \\\n\t\t\tcp $(RTE_OUTPUT)/.config_tmp $(RTE_OUTPUT)/.config ; \\\n\t\t\tcp $(RTE_OUTPUT)/.config_tmp $(RTE_OUTPUT)/.config.orig ; \\\n\t\tfi ; \\\n\t\trm -f $(RTE_OUTPUT)/.config_tmp ; \\\n\telse \\\n\t\t$(MAKE) -rRf $(RTE_SDK)/mk/rte.sdkconfig.mk notemplate; \\\n\tfi\nendif\n\n# generate a Makefile for this build directory\n# use a relative path so it will continue to work even if we move the directory\nSDK_RELPATH=$(shell $(RTE_SDK)/scripts/relpath.sh $(abspath $(RTE_SRCDIR)) \\\n\t\t\t\t$(abspath $(RTE_OUTPUT)))\nOUTPUT_RELPATH=$(shell $(RTE_SDK)/scripts/relpath.sh $(abspath $(RTE_OUTPUT)) \\\n\t\t\t\t$(abspath $(RTE_SRCDIR)))\n$(RTE_OUTPUT)/Makefile: | $(RTE_OUTPUT)\n\t$(Q)$(RTE_SDK)/scripts/gen-build-mk.sh $(SDK_RELPATH) $(OUTPUT_RELPATH) \\\n\t\t> $(RTE_OUTPUT)/Makefile\n\n# clean installed files, and generate a new config header file\n# if NODOTCONF variable is defined, don't try to rebuild .config\n$(RTE_OUTPUT)/include/rte_config.h: $(RTE_OUTPUT)/.config\n\t$(Q)rm -rf $(RTE_OUTPUT)/include $(RTE_OUTPUT)/app \\\n\t\t$(RTE_OUTPUT)/hostapp $(RTE_OUTPUT)/lib \\\n\t\t$(RTE_OUTPUT)/hostlib $(RTE_OUTPUT)/kmod $(RTE_OUTPUT)/build\n\t$(Q)mkdir -p $(RTE_OUTPUT)/include\n\t$(Q)$(RTE_SDK)/scripts/gen-config-h.sh $(RTE_OUTPUT)/.config \\\n\t\t> $(RTE_OUTPUT)/include/rte_config.h\n\n# generate the rte_config.h\n.PHONY: headerconfig\nheaderconfig: $(RTE_OUTPUT)/include/rte_config.h\n\t@true\n\n# check that .config is present, and if yes, check that rte_config.h\n# is up to date\n.PHONY: checkconfig\ncheckconfig:\n\t@if [ ! -f $(RTE_OUTPUT)/.config ]; then \\\n\t\techo \"No .config in build directory\"; \\\n\t\texit 1; \\\n\tfi\n\t$(Q)$(MAKE) -f $(RTE_SDK)/mk/rte.sdkconfig.mk \\\n\t\theaderconfig NODOTCONF=1\n\t$(Q)$(MAKE) -s depdirs\n\n.PHONY: FORCE\nFORCE:\n" }, { "path": "mk/rte.sdkdepdirs.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq (,$(wildcard $(RTE_OUTPUT)/.config))\n $(error \"need a make config first\")\nendif\nifeq (,$(wildcard $(RTE_OUTPUT)/Makefile))\n $(error \"need a make config first\")\nendif\n\n# use a \"for\" in a shell to process dependencies: we don't want this\n# task to be run in parallel.\n.PHONY: depdirs\ndepdirs: $(RTE_OUTPUT)/.depdirs\n$(RTE_OUTPUT)/.depdirs: $(RTE_OUTPUT)/.config\n\t@rm -f $(RTE_OUTPUT)/.depdirs ; \\\n\tfor d in $(ROOTDIRS-y); do \\\n\t\tif [ -f $(RTE_SRCDIR)/$$d/Makefile ]; then \\\n\t\t\t[ -d $(BUILDDIR)/$$d ] || mkdir -p $(BUILDDIR)/$$d ; \\\n\t\t\t$(MAKE) S=$$d -f $(RTE_SRCDIR)/$$d/Makefile depdirs \\\n\t\t\t\t>> $(RTE_OUTPUT)/.depdirs ; \\\n\t\tfi ; \\\n\tdone\n\n.PHONY: depgraph\ndepgraph:\n\t@echo \"digraph unix {\" ; \\\n\techo \" size=\\\"6,6\\\";\" ; \\\n\techo \" node [color=lightblue2, style=filled];\" ; \\\n\tfor d in $(ROOTDIRS-y); do \\\n\t\techo \" \\\"root\\\" -> \\\"$$d\\\"\" ; \\\n\t\tif [ -f $(RTE_SRCDIR)/$$d/Makefile ]; then \\\n\t\t\t$(MAKE) S=$$d -f $(RTE_SRCDIR)/$$d/Makefile depgraph ; \\\n\t\tfi ; \\\n\tdone ; \\\n\techo \"}\"\n" }, { "path": "mk/rte.sdkdoc.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2015 Intel Corporation. All rights reserved.\n# Copyright(c) 2013-2015 6WIND S.A.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifdef T\nifeq (\"$(origin T)\", \"command line\")\n$(error \"Cannot use T= with doc target\")\nendif\nendif\n\nRTE_SPHINX_BUILD = sphinx-build\nRTE_PDFLATEX_VERBOSE := --interaction=nonstopmode\n\nifndef V\nRTE_SPHINX_VERBOSE := -q\nRTE_PDFLATEX_VERBOSE := --interaction=batchmode\nRTE_INKSCAPE_VERBOSE := >/dev/null 2>&1\nendif\nifeq '$V' '0'\nRTE_SPHINX_VERBOSE := -q\nRTE_PDFLATEX_VERBOSE := --interaction=batchmode\nRTE_INKSCAPE_VERBOSE := >/dev/null 2>&1\nendif\n\nRTE_PDF_DPI ?= 300\n\nRTE_GUIDES := $(filter %/, $(wildcard $(RTE_SDK)/doc/guides/*/))\n\n.PHONY: help\nhelp:\n\t@cat $(RTE_SDK)/doc/build-sdk-quick.txt\n\t@$(MAKE) -rR showconfigs | sed 's,^,\\t\\t\\t\\t,'\n\n.PHONY: all\nall: api-html guides-html guides-pdf\n\n.PHONY: clean\nclean: api-html-clean guides-html-clean guides-pdf-clean\n\n.PHONY: api-html\napi-html: api-html-clean\n\t@echo 'doxygen for API...'\n\t$(Q)mkdir -p $(RTE_OUTPUT)/doc/html\n\t$(Q)(cat $(RTE_SDK)/doc/api/doxy-api.conf && \\\n\t printf 'PROJECT_NUMBER = ' && \\\n\t $(MAKE) -rR showversion && \\\n\t echo OUTPUT_DIRECTORY = $(RTE_OUTPUT)/doc && \\\n\t echo HTML_OUTPUT = html/api && \\\n\t echo GENERATE_HTML = YES && \\\n\t echo GENERATE_LATEX = NO && \\\n\t echo GENERATE_MAN = NO )| \\\n\t doxygen -\n\t$(Q)$(RTE_SDK)/doc/api/doxy-html-custom.sh $(RTE_OUTPUT)/doc/html/api/doxygen.css\n\n.PHONY: api-html-clean\napi-html-clean:\n\t$(Q)rm -f $(RTE_OUTPUT)/doc/html/api/*\n\t$(Q)rmdir -p --ignore-fail-on-non-empty $(RTE_OUTPUT)/doc/html/api 2>&- || true\n\nguides-pdf-clean: guides-pdf-img-clean\nguides-pdf-img-clean:\n\t$(Q)rm -f $(RTE_SDK)/doc/guides/*/img/*.pdf\n\nguides-%-clean:\n\t$(Q)rm -rf $(RTE_OUTPUT)/doc/$*/guides\n\t$(Q)rmdir -p --ignore-fail-on-non-empty $(RTE_OUTPUT)/doc/$* 2>&- || true\n\nguides-pdf: $(addprefix guides-pdf-, $(notdir $(RTE_GUIDES:/=))) ;\nguides-pdf-%:\n\t@echo 'sphinx processing $@...'\n\t$(Q)$(RTE_SPHINX_BUILD) -b latex $(RTE_SPHINX_VERBOSE) \\\n\t\t-c $(RTE_SDK)/doc/guides $(RTE_SDK)/doc/guides/$* \\\n\t\t$(RTE_OUTPUT)/doc/pdf/guides/$*\n\t$(if $^,$(Q)rm -f $^)\n\t@echo 'pdflatex processing $@...'\n\t$(Q)$(MAKE) all-pdf -sC $(RTE_OUTPUT)/doc/pdf/guides/$* \\\n\t\tLATEXOPTS=$(RTE_PDFLATEX_VERBOSE)\n\t$(Q)mv $(RTE_OUTPUT)/doc/pdf/guides/$*/doc.pdf \\\n\t\t$(RTE_OUTPUT)/doc/pdf/guides/$*.pdf\n\nguides-%:\n\t@echo 'sphinx processing $@...'\n\t$(Q)$(RTE_SPHINX_BUILD) -b $* $(RTE_SPHINX_VERBOSE) \\\n\t\t-c $(RTE_SDK)/doc/guides $(RTE_SDK)/doc/guides \\\n\t\t$(RTE_OUTPUT)/doc/$*/guides\n\n# Each PDF depends on generated images *.pdf from *.svg\n$(foreach guide, $(RTE_GUIDES), $(foreach img, $(wildcard $(guide)img/*.svg), \\\n\t$(eval guides-pdf-$(notdir $(guide:/=)): $(img:svg=pdf))))\n%.pdf: %.svg\n\t$(Q)inkscape -d $(RTE_PDF_DPI) -D -f $< -A $@ $(RTE_INKSCAPE_VERBOSE)\n" }, { "path": "mk/rte.sdkexamples.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2014 6WIND S.A.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# examples application are seen as external applications which are\n# not part of SDK.\nBUILDING_RTE_SDK :=\nexport BUILDING_RTE_SDK\n\n# Build directory is given with O=\nO ?= $(RTE_SDK)/examples\n\n# Target for which examples should be built.\nT ?= *\n\n# list all available configurations\nEXAMPLES_CONFIGS := $(patsubst $(RTE_SRCDIR)/config/defconfig_%,%,\\\n\t$(wildcard $(RTE_SRCDIR)/config/defconfig_$(T)))\nEXAMPLES_TARGETS := $(addsuffix _examples,\\\n\t$(filter-out %~,$(EXAMPLES_CONFIGS)))\n\n.PHONY: examples\nexamples: $(EXAMPLES_TARGETS)\n\n%_examples:\n\t@echo ================== Build examples for $*\n\t$(Q)if [ ! -d \"${RTE_SDK}/${*}\" ]; then \\\n\t\techo \"Target ${*} does not exist in ${RTE_SDK}/${*}.\" ; \\\n\t\techo -n \"Please install DPDK first (make install) or use another \" ; \\\n\t\techo \"target argument (T=target).\" ; \\\n\t\tfalse ; \\\n\telse \\\n\t\t$(MAKE) -C examples O=$(abspath $(O)) RTE_TARGET=$(*); \\\n\tfi\n\nEXAMPLES_CLEAN_TARGETS := $(addsuffix _examples_clean,\\\n\t$(filter-out %~,$(EXAMPLES_CONFIGS)))\n\n.PHONY: examples_clean\nexamples_clean: $(EXAMPLES_CLEAN_TARGETS)\n\n%_examples_clean:\n\t@echo ================== Clean examples for $*\n\t$(Q)if [ ! -d \"${RTE_SDK}/${*}\" ]; then \\\n\t\techo \"Target ${*} does not exist in ${RTE_SDK}/${*}.\" ; \\\n\t\techo -n \"Please install DPDK first (make install) or use another \" ; \\\n\t\techo \"target argument (T=target).\" ; \\\n\t\tfalse ; \\\n\telse \\\n\t\t$(MAKE) -C examples O=$(abspath $(O)) RTE_TARGET=$(*) clean; \\\n\tfi\n" }, { "path": "mk/rte.sdkgcov.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifdef T\nifeq (\"$(origin T)\", \"command line\")\n$(error \"Cannot use T= with gcov target\")\nendif\nendif\n\nifeq (,$(wildcard $(RTE_OUTPUT)/.config))\n $(error \"need a make config first\")\nelse\n include $(RTE_SDK)/mk/rte.vars.mk\nendif\nifeq (,$(wildcard $(RTE_OUTPUT)/Makefile))\n $(error \"need a make config first\")\nendif\n\nINPUTDIR = $(RTE_OUTPUT)\nOUTPUTDIR = $(RTE_OUTPUT)/gcov\n\n.PHONY: gcovclean\ngcovclean:\n\t$(Q)find $(INPUTDIR)/build -name \"*.gcno\" -o -name \"*.gcda\" -exec rm {} \\;\n\t$(Q)rm -rf $(OUTPUTDIR)\n\n.PHONY: gcov\ngcov:\n\t$(Q)for APP in test ; do \\\n\t\tmkdir -p $(OUTPUTDIR)/$$APP ; cd $(OUTPUTDIR)/$$APP ; \\\n\t\tfor FIC in `strings $(RTE_OUTPUT)/app/$$APP | grep gcda | sed s,gcda,o,` ; do \\\n\t\t\tSUBDIR=`basename $$FIC`;\\\n\t\t\tmkdir $$SUBDIR ;\\\n\t\t\tcd $$SUBDIR ;\\\n\t\t\t$(GCOV) $(RTE_OUTPUT)/app/$$APP -o $$FIC > gcov.log; \\\n\t\t\tcd - >/dev/null;\\\n\t\tdone ; \\\n\t\tcd - >/dev/null; \\\n\tdone\n" }, { "path": "mk/rte.sdkinstall.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# Build directory is given with O=\nifdef O\nBUILD_DIR=$(O)\nelse\nBUILD_DIR=.\nendif\n\n# Targets to install can be specified in command line. It can be a\n# target name or a name containing jokers \"*\". Example:\n# x86_64-native-*-gcc\nifndef T\nT=*\nendif\n\n#\n# install: build sdk for all supported targets\n#\nINSTALL_CONFIGS := $(patsubst $(RTE_SRCDIR)/config/defconfig_%,%,\\\n\t$(wildcard $(RTE_SRCDIR)/config/defconfig_$(T)))\nINSTALL_TARGETS := $(addsuffix _install,\\\n\t$(filter-out %~,$(INSTALL_CONFIGS)))\n\n.PHONY: install\ninstall: $(INSTALL_TARGETS)\n\n%_install:\n\t@echo ================== Installing $*\n\t$(Q)if [ ! -f $(BUILD_DIR)/$*/.config ]; then \\\n\t\t$(MAKE) config T=$* O=$(BUILD_DIR)/$*; \\\n\telif cmp -s $(BUILD_DIR)/$*/.config.orig $(BUILD_DIR)/$*/.config; then \\\n\t\t$(MAKE) config T=$* O=$(BUILD_DIR)/$*; \\\n\telse \\\n\t\tif [ -f $(BUILD_DIR)/$*/.config.orig ] ; then \\\n\t\t\ttmp_build=$(BUILD_DIR)/$*/.config.tmp; \\\n\t\t\t$(MAKE) config T=$* O=$$tmp_build; \\\n\t\t\tif ! cmp -s $(BUILD_DIR)/$*/.config.orig $$tmp_build/.config ; then \\\n\t\t\t\techo \"Conflict: local config and template config have both changed\"; \\\n\t\t\t\texit 1; \\\n\t\t\tfi; \\\n\t\tfi; \\\n\t\techo \"Using local configuration\"; \\\n\tfi\n\t$(Q)$(MAKE) all O=$(BUILD_DIR)/$*\n\n#\n# uninstall: remove all built sdk\n#\nUNINSTALL_TARGETS := $(addsuffix _uninstall,\\\n\t$(filter-out %~,$(INSTALL_CONFIGS)))\n\n.PHONY: uninstall\nuninstall: $(UNINSTALL_TARGETS)\n\n%_uninstall:\n\t@echo ================== Uninstalling $*\n\t$(Q)rm -rf $(BUILD_DIR)/$*\n" }, { "path": "mk/rte.sdkroot.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nMAKEFLAGS += --no-print-directory\n\n# define Q to '@' or not. $(Q) is used to prefix all shell commands to\n# be executed silently.\nQ=@\nifdef V\nifeq (\"$(origin V)\", \"command line\")\nQ=\nendif\nendif\nexport Q\n\nifeq ($(RTE_SDK),)\n$(error RTE_SDK is not defined)\nendif\n\nRTE_SRCDIR = $(CURDIR)\nexport RTE_SRCDIR\n\nBUILDING_RTE_SDK := 1\nexport BUILDING_RTE_SDK\n\n#\n# We can specify the configuration template when doing the \"make\n# config\". For instance: make config T=x86_64-native-linuxapp-gcc\n#\nRTE_CONFIG_TEMPLATE :=\nifdef T\nifeq (\"$(origin T)\", \"command line\")\nRTE_CONFIG_TEMPLATE := $(RTE_SRCDIR)/config/defconfig_$(T)\nendif\nendif\nexport RTE_CONFIG_TEMPLATE\n\n#\n# Default output is $(RTE_SRCDIR)/build\n# output files wil go in a separate directory\n#\nifdef O\nifeq (\"$(origin O)\", \"command line\")\nRTE_OUTPUT := $(abspath $(O))\nendif\nendif\nRTE_OUTPUT ?= $(RTE_SRCDIR)/build\nexport RTE_OUTPUT\n\n# the directory where intermediate build files are stored, like *.o,\n# *.d, *.cmd, ...\nBUILDDIR = $(RTE_OUTPUT)/build\nexport BUILDDIR\n\nexport ROOTDIRS-y ROOTDIRS- ROOTDIRS-n\n\n.PHONY: default\ndefault: all\n\n.PHONY: config showconfigs showversion\nconfig showconfigs showversion:\n\t$(Q)$(MAKE) -f $(RTE_SDK)/mk/rte.sdkconfig.mk $@\n\n.PHONY: test fast_test ring_test mempool_test perf_test coverage\ntest fast_test ring_test mempool_test perf_test coverage:\n\t$(Q)$(MAKE) -f $(RTE_SDK)/mk/rte.sdktest.mk $@\n\n.PHONY: testall\ntestall:\n\t$(Q)$(MAKE) -f $(RTE_SDK)/mk/rte.sdktestall.mk $@\n\n.PHONY: install uninstall\ninstall uninstall:\n\t$(Q)$(MAKE) -f $(RTE_SDK)/mk/rte.sdkinstall.mk $@\n\n.PHONY: doc help\ndoc: doc-all\nhelp: doc-help\ndoc-%:\n\t$(Q)$(MAKE) -f $(RTE_SDK)/mk/rte.sdkdoc.mk $*\n\n.PHONY: depdirs depgraph\ndepdirs depgraph:\n\t$(Q)$(MAKE) -f $(RTE_SDK)/mk/rte.sdkdepdirs.mk $@\n\n.PHONY: gcov gcovclean\ngcov gcovclean:\n\t$(Q)$(MAKE) -f $(RTE_SDK)/mk/rte.sdkgcov.mk $@\n\n.PHONY: examples examples_clean\nexamples examples_clean:\n\t$(Q)$(MAKE) -f $(RTE_SDK)/mk/rte.sdkexamples.mk $@\n\n# all other build targets\n%:\n\t$(Q)$(MAKE) -f $(RTE_SDK)/mk/rte.sdkconfig.mk checkconfig\n\t$(Q)$(MAKE) -f $(RTE_SDK)/mk/rte.sdkbuild.mk $@\n" }, { "path": "mk/rte.sdktest.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifeq (,$(wildcard $(RTE_OUTPUT)/.config))\n $(error \"need a make config first\")\nelse\n include $(RTE_SDK)/mk/rte.vars.mk\nendif\nifeq (,$(wildcard $(RTE_OUTPUT)/Makefile))\n $(error \"need a make config first\")\nendif\n\nDATE := $(shell date '+%Y%m%d-%H%M')\nAUTOTEST_DIR := $(RTE_OUTPUT)/autotest-$(DATE)\n\nDIR := $(shell basename $(RTE_OUTPUT))\n\n#\n# test: launch auto-tests, very simple for now.\n#\nPHONY: test fast_test\n\ncoverage: BLACKLIST=-Mempool_perf,Memcpy_perf,Hash_perf\nfast_test: BLACKLIST=-Ring_perf,Mempool_perf,Memcpy_perf,Hash_perf,Lpm6\nring_test: WHITELIST=Ring,Ring_perf\nmempool_test: WHITELIST=Mempool,Mempool_perf\nperf_test:WHITELIST=Mempool_perf,Memcpy_perf,Hash_perf,Ring_perf\ntest fast_test ring_test mempool_test perf_test:\n\t@mkdir -p $(AUTOTEST_DIR) ; \\\n\tcd $(AUTOTEST_DIR) ; \\\n\tif [ -f $(RTE_OUTPUT)/app/test ]; then \\\n\t\tpython $(RTE_SDK)/app/test/autotest.py \\\n\t\t\t$(RTE_OUTPUT)/app/test \\\n\t\t\t$(RTE_TARGET) \\\n\t\t\t$(BLACKLIST) $(WHITELIST); \\\n\telse \\\n\t\techo \"No test found, please do a 'make build' first, or specify O=\" ; \\\n\tfi\n\n# this is a special target to ease the pain of running coverage tests\n# this runs all the autotests, cmdline_test script and proc_info\ncoverage:\n\t@mkdir -p $(AUTOTEST_DIR) ; \\\n\tcd $(AUTOTEST_DIR) ; \\\n\tif [ -f $(RTE_OUTPUT)/app/test ]; then \\\n\t\tpython $(RTE_SDK)/app/cmdline_test/cmdline_test.py \\\n\t\t\t$(RTE_OUTPUT)/app/cmdline_test; \\\n\t\tulimit -S -n 100 ; \\\n\t\tpython $(RTE_SDK)/app/test/autotest.py \\\n\t\t\t$(RTE_OUTPUT)/app/test \\\n\t\t\t$(RTE_TARGET) \\\n\t\t\t$(BLACKLIST) $(WHITELIST) ; \\\n\t\t$(RTE_OUTPUT)/app/proc_info --file-prefix=ring_perf -- -m; \\\n\telse \\\n\t\techo \"No test found, please do a 'make build' first, or specify O=\" ;\\\n\tfi\n" }, { "path": "mk/rte.sdktestall.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nifdef O\nifeq (\"$(origin O)\", \"command line\")\n$(error \"Cannot use O= with testall target\")\nendif\nendif\n\n# Targets to test can be specified in command line. It can be a\n# target name or a name containing jokers \"*\". Example:\n# x86_64-native-*-gcc\nifndef T\nT=*\nendif\n\n#\n# testall: launch test for all supported targets\n#\nTESTALL_CONFIGS := $(patsubst $(RTE_SRCDIR)/config/defconfig_%,%,\\\n\t$(wildcard $(RTE_SRCDIR)/config/defconfig_$(T)))\nTESTALL_TARGETS := $(addsuffix _testall,\\\n\t$(filter-out %~,$(TESTALL_CONFIGS)))\n.PHONY: testall\ntestall: $(TESTALL_TARGETS)\n\n%_testall:\n\t@echo ================== Test $*\n\t$(Q)$(MAKE) fast_test O=$*\n" }, { "path": "mk/rte.shared.mk", "content": "# BSD LICENSE\n#\n# Copyright 2012-2013 6WIND S.A.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/internal/rte.compile-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-pre.mk\n\n# VPATH contains at least SRCDIR\nVPATH += $(SRCDIR)\n\n_BUILD = $(SHARED)\n_INSTALL = $(INSTALL-FILES-y) $(SYMLINK-FILES-y) $(RTE_OUTPUT)/lib/$(SHARED)\n_CLEAN = doclean\n\n# Set fPIC in CFLAGS for .so generation\nCFLAGS += -fPIC\n\n.PHONY: all\nall: install\n\n.PHONY: install\ninstall: build _postinstall\n\n_postinstall: build\n\n.PHONY: build\nbuild: _postbuild\n\nexe2cmd = $(strip $(call dotfile,$(patsubst %,%.cmd,$(1))))\n\nifeq ($(LINK_USING_CC),1)\noverride EXTRA_LDFLAGS := $(call linkerprefix,$(EXTRA_LDFLAGS))\nO_TO_SO = $(CC) $(call linkerprefix,$(LDFLAGS)) $(LDFLAGS_$(@)) $(EXTRA_LDFLAGS) \\\n\t-shared -o $@ $(OBJS-y) $(call linkerprefix,$(LDLIBS))\nelse\nO_TO_SO = $(LD) $(LDFLAGS) $(LDFLAGS_$(@)) $(EXTRA_LDFLAGS) \\\n\t-shared -o $@ $(OBJS-y) $(LDLIBS)\nendif\n\nO_TO_SO_STR = $(subst ','\\'',$(O_TO_SO)) #'# fix syntax highlight\nO_TO_SO_DISP = $(if $(V),\"$(O_TO_SO_STR)\",\" LD $(@)\")\nO_TO_SO_CMD = \"cmd_$@ = $(O_TO_SO_STR)\"\nO_TO_SO_DO = @set -e; \\\n\techo $(O_TO_SO_DISP); \\\n\t$(O_TO_SO) && \\\n\techo $(O_TO_SO_CMD) > $(call exe2cmd,$(@))\n\n-include .$(SHARED).cmd\n\n# path where libraries are retrieved\nLDLIBS_PATH := $(subst -Wl$(comma)-L,,$(filter -Wl$(comma)-L%,$(LDLIBS)))\nLDLIBS_PATH += $(subst -L,,$(filter -L%,$(LDLIBS)))\n\n# list of .a files that are linked to this application\nLDLIBS_NAMES := $(patsubst -l%,lib%.a,$(filter -l%,$(LDLIBS)))\nLDLIBS_NAMES += $(patsubst -Wl$(comma)-l%,lib%.a,$(filter -Wl$(comma)-l%,$(LDLIBS)))\n\n# list of found libraries files (useful for deps). If not found, the\n# library is silently ignored and dep won't be checked\nLDLIBS_FILES := $(wildcard $(foreach dir,$(LDLIBS_PATH),\\\n\t$(addprefix $(dir)/,$(LDLIBS_NAMES))))\n\n#\n# Archive objects in .so file if needed\n#\n$(SHARED): $(OBJS-y) $(LDLIBS_FILES) $(DEP_$(SHARED)) FORCE\n\t@[ -d $(dir $@) ] || mkdir -p $(dir $@)\n\t$(if $(D),\\\n\t\t@echo -n \"$< -> $@ \" ; \\\n\t\techo -n \"file_missing=$(call boolean,$(file_missing)) \" ; \\\n\t\techo -n \"cmdline_changed=$(call boolean,$(call cmdline_changed,$(O_TO_SO_STR))) \" ; \\\n\t\techo -n \"depfile_missing=$(call boolean,$(depfile_missing)) \" ; \\\n\t\techo \"depfile_newer=$(call boolean,$(depfile_newer)) \")\n\t$(if $(or \\\n\t\t$(file_missing),\\\n\t\t$(call cmdline_changed,$(O_TO_SO_STR)),\\\n\t\t$(depfile_missing),\\\n\t\t$(depfile_newer)),\\\n\t\t$(O_TO_SO_DO))\n\n#\n# install lib in $(RTE_OUTPUT)/lib\n#\n$(RTE_OUTPUT)/lib/$(SHARED): $(SHARED)\n\t@echo \" INSTALL-SHARED $(SHARED)\"\n\t@[ -d $(RTE_OUTPUT)/lib ] || mkdir -p $(RTE_OUTPUT)/lib\n\t$(Q)cp -f $(SHARED) $(RTE_OUTPUT)/lib\n\n#\n# Clean all generated files\n#\n.PHONY: clean\nclean: _postclean\n\n.PHONY: doclean\ndoclean:\n\t$(Q)rm -rf $(SHARED) $(OBJS-all) $(DEPS-all) $(DEPSTMP-all) \\\n\t $(CMDS-all) $(INSTALL-FILES-all)\n\t$(Q)rm -f $(_BUILD_TARGETS) $(_INSTALL_TARGETS) $(_CLEAN_TARGETS)\n\ninclude $(RTE_SDK)/mk/internal/rte.compile-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.install-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.depdirs-post.mk\n\n.PHONY: FORCE\nFORCE:\n" }, { "path": "mk/rte.sharelib.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\ninclude $(RTE_SDK)/mk/internal/rte.build-pre.mk\n\n# VPATH contains at least SRCDIR\nVPATH += $(SRCDIR)\n\nifeq ($(CONFIG_RTE_BUILD_COMBINE_LIBS),y)\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),y)\nLIB_ONE := lib$(RTE_LIBNAME).so\nelse\nLIB_ONE := lib$(RTE_LIBNAME).a\nendif\nendif\n\n.PHONY:sharelib\nsharelib: $(LIB_ONE) FORCE\n\nOBJS = $(wildcard $(RTE_OUTPUT)/build/lib/*.o)\n\nifeq ($(LINK_USING_CC),1)\n# Override the definition of LD here, since we're linking with CC\nLD := $(CC) $(CPU_CFLAGS)\nO_TO_S = $(LD) $(call linkerprefix,$(CPU_LDFLAGS)) \\\n\t-shared $(OBJS) -o $(RTE_OUTPUT)/lib/$(LIB_ONE)\nelse\nO_TO_S = $(LD) $(CPU_LDFLAGS) \\\n\t-shared $(OBJS) -o $(RTE_OUTPUT)/lib/$(LIB_ONE)\nendif\n\nO_TO_S_STR = $(subst ','\\'',$(O_TO_S)) #'# fix syntax highlight\nO_TO_S_DISP = $(if $(V),\"$(O_TO_S_STR)\",\" LD $(@)\")\nO_TO_S_CMD = \"cmd_$@ = $(O_TO_S_STR)\"\nO_TO_S_DO = @set -e; \\\n echo $(O_TO_S_DISP); \\\n $(O_TO_S)\n\nO_TO_A = $(AR) crus $(RTE_OUTPUT)/lib/$(LIB_ONE) $(OBJS)\nO_TO_A_STR = $(subst ','\\'',$(O_TO_A)) #'# fix syntax highlight\nO_TO_A_DISP = $(if $(V),\"$(O_TO_A_STR)\",\" LD $(@)\")\nO_TO_A_CMD = \"cmd_$@ = $(O_TO_A_STR)\"\nO_TO_A_DO = @set -e; \\\n echo $(O_TO_A_DISP); \\\n $(O_TO_A)\n#\n# Archive objects to share library\n#\n\nifeq ($(CONFIG_RTE_BUILD_COMBINE_LIBS),y)\nifeq ($(CONFIG_RTE_BUILD_SHARED_LIB),y)\n$(LIB_ONE): FORCE\n\t@[ -d $(dir $@) ] || mkdir -p $(dir $@)\n\t$(O_TO_S_DO)\nelse\n$(LIB_ONE): FORCE\n\t@[ -d $(dir $@) ] || mkdir -p $(dir $@)\n\t$(O_TO_A_DO)\nendif\nendif\n\n#\n# Clean all generated files\n#\n.PHONY: clean\nclean: _postclean\n\n.PHONY: doclean\ndoclean:\n\t$(Q)rm -rf $(LIB_ONE)\n\n.PHONY: FORCE\nFORCE:\n" }, { "path": "mk/rte.subdir.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# .mk to build subdirectories\n#\n\ninclude $(RTE_SDK)/mk/internal/rte.install-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-pre.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-pre.mk\n\nCLEANDIRS = $(addsuffix _clean,$(DIRS-y) $(DIRS-n) $(DIRS-))\n\nVPATH += $(SRCDIR)\n_BUILD = $(DIRS-y)\n_INSTALL = $(INSTALL-FILES-y) $(SYMLINK-FILES-y)\n_CLEAN = $(CLEANDIRS)\n\n.PHONY: all\nall: install\n\n.PHONY: install\ninstall: build _postinstall\n\n_postinstall: build\n\n.PHONY: build\nbuild: _postbuild\n\n.SECONDEXPANSION:\n.PHONY: $(DIRS-y)\n$(DIRS-y):\n\t@[ -d $(CURDIR)/$@ ] || mkdir -p $(CURDIR)/$@\n\t@echo \"== Build $S/$@\"\n\t@$(MAKE) S=$S/$@ -f $(SRCDIR)/$@/Makefile -C $(CURDIR)/$@ all\n\n.PHONY: clean\nclean: _postclean\n\n%_clean:\n\t@echo \"== Clean $S/$*\"\n\t@if [ -f $(SRCDIR)/$*/Makefile -a -d $(CURDIR)/$* ]; then \\\n\t\t$(MAKE) S=$S/$* -f $(SRCDIR)/$*/Makefile -C $(CURDIR)/$* clean ; \\\n\tfi\n\t@rm -f $(_BUILD_TARGETS) $(_INSTALL_TARGETS) $(_CLEAN_TARGETS)\n\n#\n# include .depdirs and define rules to order priorities between build\n# of directories.\n#\ninclude $(RTE_OUTPUT)/.depdirs\n\ndefine depdirs_rule\n$(1): $(sort $(patsubst $(S)/%,%,$(LOCAL_DEPDIRS-$(S)/$(1))))\nendef\n\n$(foreach d,$(DIRS-y),$(eval $(call depdirs_rule,$(d))))\n\n\n# use a \"for\" in a shell to process dependencies: we don't want this\n# task to be run in parallel.\n.PHONY: depdirs\ndepdirs:\n\t@for d in $(DIRS-y); do \\\n\t\tif [ -f $(SRCDIR)/$$d/Makefile ]; then \\\n\t\t\t$(MAKE) S=$S/$$d -f $(SRCDIR)/$$d/Makefile depdirs ; \\\n\t\tfi ; \\\n\tdone\n\n.PHONY: depgraph\ndepgraph:\n\t@for d in $(DIRS-y); do \\\n\t\techo \" \\\"$(S)\\\" -> \\\"$(S)/$$d\\\"\" ; \\\n\t\tif [ -f $(SRCDIR)/$$d/Makefile ]; then \\\n\t\t\t$(MAKE) S=$S/$$d -f $(SRCDIR)/$$d/Makefile depgraph ; \\\n\t\tfi ; \\\n\tdone\n\ninclude $(RTE_SDK)/mk/internal/rte.install-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.clean-post.mk\ninclude $(RTE_SDK)/mk/internal/rte.build-post.mk\n\n.PHONY: FORCE\nFORCE:\n" }, { "path": "mk/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# To be included at the beginning of all RTE user Makefiles. This\n# .mk will define the RTE environment variables by including the\n# config file of SDK. It also includes the config file from external\n# application if any.\n#\n\nifeq ($(RTE_SDK),)\n$(error RTE_SDK is not defined)\nendif\nifeq ($(wildcard $(RTE_SDK)),)\n$(error RTE_SDK variable points to an invalid location)\nendif\n\n# define Q to '@' or not. $(Q) is used to prefix all shell commands to\n# be executed silently.\nQ=@\nifdef V\nifeq (\"$(origin V)\", \"command line\")\nQ=\nendif\nendif\nexport Q\n\n# if we are building SDK, only includes SDK configuration\nifneq ($(BUILDING_RTE_SDK),)\n include $(RTE_OUTPUT)/.config\n # remove double-quotes from config names\n RTE_ARCH := $(CONFIG_RTE_ARCH:\"%\"=%)\n RTE_MACHINE := $(CONFIG_RTE_MACHINE:\"%\"=%)\n RTE_EXEC_ENV := $(CONFIG_RTE_EXEC_ENV:\"%\"=%)\n RTE_TOOLCHAIN := $(CONFIG_RTE_TOOLCHAIN:\"%\"=%)\n RTE_TARGET := $(RTE_ARCH)-$(RTE_MACHINE)-$(RTE_EXEC_ENV)-$(RTE_TOOLCHAIN)\n RTE_SDK_BIN := $(RTE_OUTPUT)\nendif\n\nRTE_LIBNAME := dpdk\n\n# RTE_TARGET is deducted from config when we are building the SDK.\n# Else, when building an external app, RTE_TARGET must be specified\n# by the user.\nifeq ($(RTE_TARGET),)\n$(error RTE_TARGET is not defined)\nendif\n\nifeq ($(BUILDING_RTE_SDK),)\n# if we are building an external app/lib, include internal/rte.extvars.mk that will\n# define RTE_OUTPUT, RTE_SRCDIR, RTE_EXTMK, RTE_SDK_BIN, (etc ...)\ninclude $(RTE_SDK)/mk/internal/rte.extvars.mk\nendif\n\nCONFIG_RTE_LIBRTE_E1000_PMD = $(CONFIG_RTE_LIBRTE_IGB_PMD)\nifneq ($(CONFIG_RTE_LIBRTE_E1000_PMD),y)\n CONFIG_RTE_LIBRTE_E1000_PMD = $(CONFIG_RTE_LIBRTE_EM_PMD)\nendif\n\nifeq ($(RTE_ARCH),)\n$(error RTE_ARCH is not defined)\nendif\n\nifeq ($(RTE_MACHINE),)\n$(error RTE_MACHINE is not defined)\nendif\n\nifeq ($(RTE_EXEC_ENV),)\n$(error RTE_EXEC_ENV is not defined)\nendif\n\nifeq ($(RTE_TOOLCHAIN),)\n$(error RTE_TOOLCHAIN is not defined)\nendif\n\n# can be overriden by make command line or exported environment variable\nRTE_KERNELDIR ?= /lib/modules/$(shell uname -r)/build\n\nexport RTE_TARGET\nexport RTE_ARCH\nexport RTE_MACHINE\nexport RTE_EXEC_ENV\nexport RTE_TOOLCHAIN\n\n# SRCDIR is the current source directory\nifdef S\nSRCDIR := $(abspath $(RTE_SRCDIR)/$(S))\nelse\nSRCDIR := $(RTE_SRCDIR)\nendif\n\n# helper: return y if option is set to y, else return an empty string\ntestopt = $(if $(strip $(subst y,,$(1)) $(subst $(1),,y)),,y)\n\n# helper: return an empty string if option is set, else return y\nnot = $(if $(strip $(subst y,,$(1)) $(subst $(1),,y)),,y)\n\nifneq ($(wildcard $(RTE_SDK)/mk/target/$(RTE_TARGET)/rte.vars.mk),)\ninclude $(RTE_SDK)/mk/target/$(RTE_TARGET)/rte.vars.mk\nelse\ninclude $(RTE_SDK)/mk/target/generic/rte.vars.mk\nendif\n" }, { "path": "mk/target/generic/rte.app.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# define Makefile targets that are specific to an environment.\n#\ninclude $(RTE_SDK)/mk/exec-env/$(RTE_EXEC_ENV)/rte.app.mk\n\n.PHONY: exec-env-appinstall\ntarget-appinstall: exec-env-appinstall\n\n.PHONY: exec-env-appclean\ntarget-appclean: exec-env-appclean\n" }, { "path": "mk/target/generic/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# This .mk is the generic target rte.var.mk ; it includes .mk for\n# the specified machine, architecture, toolchain (compiler) and\n# executive environment.\n#\n\n#\n# machine:\n#\n# - can define ARCH variable (overriden by cmdline value)\n# - can define CROSS variable (overriden by cmdline value)\n# - define MACHINE_CFLAGS variable (overriden by cmdline value)\n# - define MACHINE_LDFLAGS variable (overriden by cmdline value)\n# - define MACHINE_ASFLAGS variable (overriden by cmdline value)\n# - can define CPU_CFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_LDFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n# - can define CPU_ASFLAGS variable (overriden by cmdline value) that\n# overrides the one defined in arch.\n#\n# examples for RTE_MACHINE: default, pc, bensley, tylesburg, ...\n#\ninclude $(RTE_SDK)/mk/machine/$(RTE_MACHINE)/rte.vars.mk\n\n#\n# arch:\n#\n# - define ARCH variable (overriden by cmdline or by previous\n# optional define in machine .mk)\n# - define CROSS variable (overriden by cmdline or previous define\n# in machine .mk)\n# - define CPU_CFLAGS variable (overriden by cmdline or previous\n# define in machine .mk)\n# - define CPU_LDFLAGS variable (overriden by cmdline or previous\n# define in machine .mk)\n# - define CPU_ASFLAGS variable (overriden by cmdline or previous\n# define in machine .mk)\n# - may override any previously defined variable\n#\n# examples for RTE_ARCH: i686, x86_64\n#\ninclude $(RTE_SDK)/mk/arch/$(RTE_ARCH)/rte.vars.mk\n\n#\n# toolchain:\n#\n# - define CC, LD, AR, AS, ...\n# - define TOOLCHAIN_CFLAGS variable (overriden by cmdline value)\n# - define TOOLCHAIN_LDFLAGS variable (overriden by cmdline value)\n# - define TOOLCHAIN_ASFLAGS variable (overriden by cmdline value)\n# - may override any previously defined variable\n#\n# examples for RTE_TOOLCHAIN: gcc, icc\n#\ninclude $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.vars.mk\n\n#\n# exec-env:\n#\n# - define EXECENV_CFLAGS variable (overriden by cmdline)\n# - define EXECENV_LDFLAGS variable (overriden by cmdline)\n# - define EXECENV_ASFLAGS variable (overriden by cmdline)\n# - may override any previously defined variable\n#\n# examples for RTE_EXEC_ENV: linuxapp, bsdapp\n#\ninclude $(RTE_SDK)/mk/exec-env/$(RTE_EXEC_ENV)/rte.vars.mk\n\n# Don't set CFLAGS/LDFLAGS flags for kernel module, all flags are\n# provided by Kbuild framework.\nifeq ($(KERNELRELEASE),)\n\n# now that the environment is mostly set up, including the machine type we will\n# be passing to the compiler, set up the specific CPU flags based on that info.\ninclude $(RTE_SDK)/mk/rte.cpuflags.mk\n\n# merge all CFLAGS\nCFLAGS := $(CPU_CFLAGS) $(EXECENV_CFLAGS) $(TOOLCHAIN_CFLAGS) $(MACHINE_CFLAGS)\nCFLAGS += $(TARGET_CFLAGS)\n\n# merge all LDFLAGS\nLDFLAGS := $(CPU_LDFLAGS) $(EXECENV_LDFLAGS) $(TOOLCHAIN_LDFLAGS) $(MACHINE_LDFLAGS)\nLDFLAGS += $(TARGET_LDFLAGS)\n\n# merge all ASFLAGS\nASFLAGS := $(CPU_ASFLAGS) $(EXECENV_ASFLAGS) $(TOOLCHAIN_ASFLAGS) $(MACHINE_ASFLAGS)\nASFLAGS += $(TARGET_ASFLAGS)\n\n# add default include and lib paths\nCFLAGS += -I$(RTE_OUTPUT)/include\nLDFLAGS += -L$(RTE_OUTPUT)/lib\n\n# always include rte_config.h: the one in $(RTE_OUTPUT)/include is\n# the configuration of SDK when $(BUILDING_RTE_SDK) is true, or the\n# configuration of the application if $(BUILDING_RTE_SDK) is not\n# defined.\nifeq ($(BUILDING_RTE_SDK),1)\n# building sdk\nCFLAGS += -include $(RTE_OUTPUT)/include/rte_config.h\nifeq ($(CONFIG_RTE_INSECURE_FUNCTION_WARNING),y)\nCFLAGS += -include rte_warnings.h\nendif\nelse\n# if we are building an external application, include SDK's lib and\n# includes too\nCFLAGS += -I$(RTE_SDK_BIN)/include\nifneq ($(wildcard $(RTE_OUTPUT)/include/rte_config.h),)\nCFLAGS += -include $(RTE_OUTPUT)/include/rte_config.h\nendif\nCFLAGS += -include $(RTE_SDK_BIN)/include/rte_config.h\nifeq ($(CONFIG_RTE_INSECURE_FUNCTION_WARNING),y)\nCFLAGS += -include rte_warnings.h\nendif\nLDFLAGS += -L$(RTE_SDK_BIN)/lib\nendif\n\nexport CFLAGS\nexport LDFLAGS\n\nendif\n" }, { "path": "mk/toolchain/clang/rte.toolchain-compat.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# CPUID-related options\n#\n# This was added to support compiler versions which might not support all the\n# flags we need\n#\n\n# find out CLANG version\n\nCLANG_MAJOR_VERSION = $(shell $(CC) -dumpversion | cut -f1 -d.)\n\nCLANG_MINOR_VERSION = $(shell $(CC) -dumpversion | cut -f2 -d.)\n" }, { "path": "mk/toolchain/clang/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# toolchain:\n#\n# - define CC, LD, AR, AS, ... (overriden by cmdline value)\n# - define TOOLCHAIN_CFLAGS variable (overriden by cmdline value)\n# - define TOOLCHAIN_LDFLAGS variable (overriden by cmdline value)\n# - define TOOLCHAIN_ASFLAGS variable (overriden by cmdline value)\n#\n\nCC = $(CROSS)clang\nKERNELCC = $(CROSS)gcc\nCPP = $(CROSS)cpp\n# for now, we don't use as but nasm.\n# AS = $(CROSS)as\nAS = nasm\nAR = $(CROSS)ar\nLD = $(CROSS)ld\nOBJCOPY = $(CROSS)objcopy\nOBJDUMP = $(CROSS)objdump\nSTRIP = $(CROSS)strip\nREADELF = $(CROSS)readelf\nGCOV = $(CROSS)gcov\n\nifeq (\"$(origin CC)\", \"command line\")\nHOSTCC = $(CC)\nelse\nHOSTCC = clang\nendif\nHOSTAS = as\n\nTOOLCHAIN_ASFLAGS =\nTOOLCHAIN_CFLAGS =\nTOOLCHAIN_LDFLAGS =\n\nWERROR_FLAGS := -W -Wall -Werror -Wstrict-prototypes -Wmissing-prototypes\nWERROR_FLAGS += -Wmissing-declarations -Wold-style-definition -Wpointer-arith\nWERROR_FLAGS += -Wnested-externs -Wcast-qual\nWERROR_FLAGS += -Wformat-nonliteral -Wformat-security\nWERROR_FLAGS += -Wundef -Wwrite-strings\n\n# process cpu flags\ninclude $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.toolchain-compat.mk\n\n# workaround clang bug with warning \"missing field initializer\" for \"= {0}\"\nWERROR_FLAGS += -Wno-missing-field-initializers\n\nexport CC AS AR LD OBJCOPY OBJDUMP STRIP READELF\nexport TOOLCHAIN_CFLAGS TOOLCHAIN_LDFLAGS TOOLCHAIN_ASFLAGS\n" }, { "path": "mk/toolchain/gcc/rte.toolchain-compat.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# CPUID-related options\n#\n# This was added to support compiler versions which might not support all the\n# flags we need\n#\n\n#find out GCC version\n\nGCC_VERSION = $(subst .,,$(shell $(CC) -dumpversion | cut -f1-2 -d.))\n\n# if GCC is older than 4.x\nifeq ($(shell test $(GCC_VERSION) -lt 40 && echo 1), 1)\n\tMACHINE_CFLAGS =\n$(warning You are using GCC < 4.x. This is neither supported, nor tested.)\n\n\nelse\n# GCC graceful degradation\n# GCC 4.2.x - added support for generic target\n# GCC 4.3.x - added support for core2, ssse3, sse4.1, sse4.2\n# GCC 4.4.x - added support for avx, aes, pclmul\n# GCC 4.5.x - added support for atom\n# GCC 4.6.x - added support for corei7, corei7-avx\n# GCC 4.7.x - added support for fsgsbase, rdrnd, f16c, core-avx-i, core-avx2\n\n\tifeq ($(shell test $(GCC_VERSION) -le 47 && echo 1), 1)\n\t\tMACHINE_CFLAGS := $(patsubst -march=core-avx-i,-march=corei7-avx,$(MACHINE_CFLAGS))\n\t\tMACHINE_CFLAGS := $(patsubst -march=core-avx2,-march=core-avx2,$(MACHINE_CFLAGS))\n\tendif\n\tifeq ($(shell test $(GCC_VERSION) -lt 46 && echo 1), 1)\n\t\tMACHINE_CFLAGS := $(patsubst -march=corei7-avx,-march=core2 -maes -mpclmul -mavx,$(MACHINE_CFLAGS))\n\t\tMACHINE_CFLAGS := $(patsubst -march=corei7,-march=core2 -maes -mpclmul,$(MACHINE_CFLAGS))\n\tendif\n\tifeq ($(shell test $(GCC_VERSION) -lt 45 && echo 1), 1)\n\t\tMACHINE_CFLAGS := $(patsubst -march=atom,-march=core2 -mssse3,$(MACHINE_CFLAGS))\n\tendif\n\tifeq ($(shell test $(GCC_VERSION) -lt 44 && echo 1), 1)\n\t\tMACHINE_CFLAGS := $(filter-out -mavx -mpclmul -maes,$(MACHINE_CFLAGS))\n\t\tifneq ($(findstring SSE4_2, $(CPUFLAGS)),)\n\t\t\tMACHINE_CFLAGS += -msse4.2\n\t\tendif\n\t\tifneq ($(findstring SSE4_1, $(CPUFLAGS)),)\n\t\t\tMACHINE_CFLAGS += -msse4.1\n\t\tendif\n\tendif\n\tifeq ($(shell test $(GCC_VERSION) -lt 43 && echo 1), 1)\n\t\tMACHINE_CFLAGS := $(filter-out -msse% -mssse%,$(MACHINE_CFLAGS))\n\t\tMACHINE_CFLAGS := $(patsubst -march=core2,-march=generic,$(MACHINE_CFLAGS))\n\t\tMACHINE_CFLAGS += -msse3\n\tendif\n\tifeq ($(shell test $(GCC_VERSION) -lt 42 && echo 1), 1)\n\t\tMACHINE_CFLAGS := $(filter-out -march% -mtune% -msse%,$(MACHINE_CFLAGS))\n\tendif\nendif\n" }, { "path": "mk/toolchain/gcc/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# toolchain:\n#\n# - define CC, LD, AR, AS, ... (overriden by cmdline value)\n# - define TOOLCHAIN_CFLAGS variable (overriden by cmdline value)\n# - define TOOLCHAIN_LDFLAGS variable (overriden by cmdline value)\n# - define TOOLCHAIN_ASFLAGS variable (overriden by cmdline value)\n#\n\nCC = $(CROSS)gcc\nKERNELCC = $(CROSS)gcc\nCPP = $(CROSS)cpp\n# for now, we don't use as but nasm.\n# AS = $(CROSS)as\nAS = nasm\nAR = $(CROSS)ar\nLD = $(CROSS)ld\nOBJCOPY = $(CROSS)objcopy\nOBJDUMP = $(CROSS)objdump\nSTRIP = $(CROSS)strip\nREADELF = $(CROSS)readelf\nGCOV = $(CROSS)gcov\n\nifeq (\"$(origin CC)\", \"command line\")\nHOSTCC = $(CC)\nelse\nHOSTCC = gcc\nendif\nHOSTAS = as\n\nTOOLCHAIN_ASFLAGS =\nTOOLCHAIN_CFLAGS =\nTOOLCHAIN_LDFLAGS =\n\nifeq ($(CONFIG_RTE_LIBRTE_GCOV),y)\nTOOLCHAIN_CFLAGS += --coverage\nTOOLCHAIN_LDFLAGS += --coverage\nifeq (,$(findstring -O0,$(EXTRA_CFLAGS)))\n $(warning \"EXTRA_CFLAGS doesn't contains -O0, coverage will be inaccurate with optimizations enabled\")\nendif\nendif\n\nWERROR_FLAGS := -W -Wall -Werror -Wstrict-prototypes -Wmissing-prototypes\nWERROR_FLAGS += -Wmissing-declarations -Wold-style-definition -Wpointer-arith\nWERROR_FLAGS += -Wcast-align -Wnested-externs -Wcast-qual\nWERROR_FLAGS += -Wformat-nonliteral -Wformat-security\nWERROR_FLAGS += -Wundef -Wwrite-strings\n\n# process cpu flags\ninclude $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.toolchain-compat.mk\n\n# workaround GCC bug with warning \"missing initializer\" for \"= {0}\"\nifeq ($(shell test $(GCC_VERSION) -lt 47 && echo 1), 1)\nWERROR_FLAGS += -Wno-missing-field-initializers\nendif\n# workaround GCC bug with warning \"may be used uninitialized\"\nifeq ($(shell test $(GCC_VERSION) -lt 47 && echo 1), 1)\nWERROR_FLAGS += - Wno-uninitialized\nendif\n# workaround to skipping GCC6 additional errors\nWERROR_FLAGS += -Wno-misleading-indentation -Wno-shift-negative-value -Wno-maybe-uninitialized\n\nexport CC AS AR LD OBJCOPY OBJDUMP STRIP READELF\nexport TOOLCHAIN_CFLAGS TOOLCHAIN_LDFLAGS TOOLCHAIN_ASFLAGS\n" }, { "path": "mk/toolchain/icc/rte.toolchain-compat.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# CPUID-related options\n#\n# This was added to support compiler versions which might not support all the\n# flags we need\n#\n\n# find out ICC version\n\nICC_MAJOR_VERSION = $(shell icc -dumpversion | cut -f1 -d.)\n\nifeq ($(shell test $(ICC_MAJOR_VERSION) -lt 12 && echo 1), 1)\n\tMACHINE_CFLAGS = -xSSE3\n$(warning You are not using ICC 12.x or higher. This is neither supported, nor tested.)\n\nelse\n# proceed to adjust compiler flags\n\n\tICC_MINOR_VERSION = $(shell icc -dumpversion | cut -f2 -d.)\n\n# replace GCC flags with ICC flags\n\t# if icc version >= 12\n\tifeq ($(shell test $(ICC_MAJOR_VERSION) -ge 12 && echo 1), 1)\n\t\t# Atom\n\t\tMACHINE_CFLAGS := $(patsubst -march=atom,-xSSSE3_ATOM -march=atom,$(MACHINE_CFLAGS))\n\t\t# nehalem/westmere\n\t\tMACHINE_CFLAGS := $(patsubst -march=corei7,-xSSE4.2 -march=corei7,$(MACHINE_CFLAGS))\n\t\t# sandy bridge\n\t\tMACHINE_CFLAGS := $(patsubst -march=corei7-avx,-xAVX,$(MACHINE_CFLAGS))\n\t\t# ivy bridge\n\t\tMACHINE_CFLAGS := $(patsubst -march=core-avx-i,-xCORE-AVX-I,$(MACHINE_CFLAGS))\n\t\t# hsw\n\t\tMACHINE_CFLAGS := $(patsubst -march=core-avx2,-xCORE-AVX2,$(MACHINE_CFLAGS))\n\t\t# remove westmere flags\n\t\tMACHINE_CFLAGS := $(filter-out -mpclmul -maes,$(MACHINE_CFLAGS))\n\tendif\n\t# if icc version == 12.0\n\tifeq ($(shell test $(ICC_MAJOR_VERSION) -eq 12 && test $(ICC_MINOR_VERSION) -eq 0 && echo 1), 1)\n\t\t# Atom\n\t\tMACHINE_CFLAGS := $(patsubst -xSSSE3_ATOM,-xSSE3_ATOM,$(MACHINE_CFLAGS))\n\t\t# remove march options\n\t\tMACHINE_CFLAGS := $(patsubst -march=%,-xSSE3,$(MACHINE_CFLAGS))\n\tendif\nendif\n" }, { "path": "mk/toolchain/icc/rte.vars.mk", "content": "# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# toolchain:\n#\n# - define CC, LD, AR, AS, ... (overriden by cmdline value)\n# - define TOOLCHAIN_CFLAGS variable (overriden by cmdline value)\n# - define TOOLCHAIN_LDFLAGS variable (overriden by cmdline value)\n# - define TOOLCHAIN_ASFLAGS variable (overriden by cmdline value)\n#\n\n# Warning: we do not use CROSS environment variable as icc is mainly a\n# x86->x86 compiler\n\nCC = icc\nKERNELCC = gcc\nCPP = cpp\nAS = nasm\nAR = ar\nLD = ld\nOBJCOPY = objcopy\nOBJDUMP = objdump\nSTRIP = strip\nREADELF = readelf\n\nifeq ($(KERNELRELEASE),)\nHOSTCC = icc\nelse\nHOSTCC = gcc\nendif\nHOSTAS = as\n\nTOOLCHAIN_CFLAGS =\nTOOLCHAIN_LDFLAGS =\nTOOLCHAIN_ASFLAGS =\n\n# Turn off some ICC warnings -\n# Remark #271 : trailing comma is nonstandard\n# Warning #1478 : function \"\" (declared at line N of \"\")\n# error #13368: loop was not vectorized with \"vector always assert\"\n# error #15527: loop was not vectorized: function call to fprintf cannot be vectorize\n# was declared \"deprecated\"\nWERROR_FLAGS := -Wall -Werror-all -w2 -diag-disable 271 -diag-warning 1478\nWERROR_FLAGS += -diag-disable 13368 -diag-disable 15527\n\n# process cpu flags\ninclude $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.toolchain-compat.mk\n# disable max-inline params boundaries for ICC 15 compiler\nifeq ($(shell test $(ICC_MAJOR_VERSION) -eq 15 && echo 1), 1)\n\tTOOLCHAIN_CFLAGS += -no-inline-max-size -no-inline-max-total-size\nendif\n\nexport CC AS AR LD OBJCOPY OBJDUMP STRIP READELF\nexport TOOLCHAIN_CFLAGS TOOLCHAIN_LDFLAGS TOOLCHAIN_ASFLAGS\n" }, { "path": "pkg/dpdk.spec", "content": "# Copyright 2014 6WIND S.A.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# - Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n#\n# - Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n#\n# - Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS\n# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n# OF THE POSSIBILITY OF SUCH DAMAGE.\n\nName: dpdk\nVersion: 2.1.0\nRelease: 1\nPackager: packaging@6wind.com\nURL: http://dpdk.org\nSource: http://dpdk.org/browse/dpdk/snapshot/dpdk-%{version}.tar.gz\n\nSummary: Data Plane Development Kit core\nGroup: System Environment/Libraries\nLicense: BSD and LGPLv2 and GPLv2\n\nExclusiveArch: i686, x86_64\n%global target %{_arch}-native-linuxapp-gcc\n%global machine default\n\nBuildRequires: kernel-devel, kernel-headers, libpcap-devel, xen-devel\nBuildRequires: doxygen, python-sphinx, inkscape\nBuildRequires: texlive-collection-latexextra, texlive-collection-fontsextra\n\n%description\nDPDK core includes kernel modules, core libraries and tools.\ntestpmd application allows to test fast packet processing environments\non x86 platforms. For instance, it can be used to check that environment\ncan support fast path applications such as 6WINDGate, pktgen, rumptcpip, etc.\nMore libraries are available as extensions in other packages.\n\n%package devel\nSummary: Data Plane Development Kit for development\nRequires: %{name}%{?_isa} = %{version}-%{release}\n%description devel\nDPDK devel is a set of makefiles, headers and examples\nfor fast packet processing on x86 platforms.\n\n%package doc\nSummary: Data Plane Development Kit API documentation\nBuildArch: noarch\n%description doc\nDPDK doc is divided in two parts: API details in doxygen HTML format\nand guides in sphinx HTML/PDF formats.\n\n%global destdir %{buildroot}%{_prefix}\n%global moddir /lib/modules/%(uname -r)/extra\n%global datadir %{_datadir}/dpdk\n%global docdir %{_docdir}/dpdk\n\n%prep\n%setup -q\n\n%build\nmake O=%{target} T=%{target} config\nsed -ri 's,(RTE_MACHINE=).*,\\1%{machine},' %{target}/.config\nsed -ri 's,(RTE_APP_TEST=).*,\\1n,' %{target}/.config\nsed -ri 's,(RTE_BUILD_SHARED_LIB=).*,\\1y,' %{target}/.config\nsed -ri 's,(RTE_NEXT_ABI=).*,\\1n,' %{target}/.config\nsed -ri 's,(LIBRTE_VHOST=).*,\\1y,' %{target}/.config\nsed -ri 's,(LIBRTE_PMD_PCAP=).*,\\1y,' %{target}/.config\nsed -ri 's,(LIBRTE_PMD_XENVIRT=).*,\\1y,' %{target}/.config\nsed -ri 's,(LIBRTE_XEN_DOM0=).*,\\1y,' %{target}/.config\nmake O=%{target} %{?_smp_mflags}\nmake O=%{target} doc\n\n%install\nrm -rf %{buildroot}\nmake O=%{target} DESTDIR=%{destdir}\nmkdir -p %{buildroot}%{moddir}\nmv %{destdir}/%{target}/kmod/*.ko %{buildroot}%{moddir}\nrmdir %{destdir}/%{target}/kmod\nmkdir -p %{buildroot}%{_sbindir}\nln -s %{datadir}/tools/*nic_bind.py %{buildroot}%{_sbindir}/dpdk_nic_bind\nmkdir -p %{buildroot}%{_bindir}\nmv %{destdir}/%{target}/app/testpmd %{buildroot}%{_bindir}\nrmdir %{destdir}/%{target}/app\nmv %{destdir}/%{target}/include %{buildroot}%{_includedir}\nmv %{destdir}/%{target}/lib %{buildroot}%{_libdir}\nmkdir -p %{buildroot}%{docdir}\nrm -rf %{destdir}/%{target}/doc/*/*/.{build,doc}*\nmv %{destdir}/%{target}/doc/html/* %{buildroot}%{docdir}\nmv %{destdir}/%{target}/doc/*/*/*pdf %{buildroot}%{docdir}/guides\nrm -rf %{destdir}/%{target}/doc\nmkdir -p %{buildroot}%{datadir}\nmv %{destdir}/%{target}/.config %{buildroot}%{datadir}/config\nmv %{destdir}/%{target} %{buildroot}%{datadir}\nmv %{destdir}/scripts %{buildroot}%{datadir}\nmv %{destdir}/mk %{buildroot}%{datadir}\ncp -a examples %{buildroot}%{datadir}\ncp -a tools %{buildroot}%{datadir}\nln -s %{datadir}/config %{buildroot}%{datadir}/%{target}/.config\nln -s %{_includedir} %{buildroot}%{datadir}/%{target}/include\nln -s %{_libdir} %{buildroot}%{datadir}/%{target}/lib\n\n%files\n%dir %{datadir}\n%{datadir}/config\n%{datadir}/tools\n%{moddir}/*\n%{_sbindir}/*\n%{_bindir}/*\n%{_libdir}/*\n\n%files devel\n%{_includedir}/*\n%{datadir}/mk\n%{datadir}/scripts\n%{datadir}/%{target}\n%{datadir}/examples\n\n%files doc\n%doc %{docdir}\n\n%post\n/sbin/ldconfig\n/sbin/depmod\n\n%postun\n/sbin/ldconfig\n/sbin/depmod\n" }, { "path": "scripts/auto-config-h.sh", "content": "#!/bin/sh\n#\n# BSD LICENSE\n#\n# Copyright 2014-2015 6WIND S.A.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n# Crude script to detect whether particular types, macros and functions are\n# defined by trying to compile a file with a given header. Can be used to\n# perform cross-platform checks since the resulting object file is not\n# executed.\n#\n# Set VERBOSE=1 in the environment to display compiler output and errors.\n#\n# CC, CPPFLAGS, CFLAGS, EXTRA_CPPFLAGS and EXTRA_CFLAGS are taken from the\n# environment.\n#\n# AUTO_CONFIG_CFLAGS may append additional CFLAGS without modifying the\n# above variables.\n\nfile=${1:?output file name required (config.h)}\nmacro=${2:?output macro name required (HAVE_*)}\ninclude=${3:?include name required (foo.h)}\ntype=${4:?object type required (define, enum, type, field, func)}\nname=${5:?define/type/function name required}\n\n: ${CC:=cc}\n\ntemp=/tmp/${0##*/}.$$.c\n\ncase $type in\ndefine)\n\tcode=\"\\\n#ifndef $name\n#error $name not defined\n#endif\n\"\n\t;;\nenum)\n\tcode=\"\\\nlong test____ = $name;\n\"\n\t;;\ntype)\n\tcode=\"\\\n$name test____;\n\"\n\t;;\nfield)\n\tcode=\"\\\nvoid test____(void)\n{\n\t${name%%.*} test_____;\n\n\t(void)test_____.${name#*.};\n}\n\"\n\t;;\nfunc)\n\tcode=\"\\\nvoid (*test____)() = (void (*)())$name;\n\"\n\t;;\n*)\n\tunset error\n\t: ${error:?unknown object type \\\"$type\\\"}\n\texit\nesac\n\nif [ \"${VERBOSE}\" = 1 ]\nthen\n\terr=2\n\tout=1\n\teol='\n'\nelse\n\texec 3> /dev/null ||\n\texit\n\terr=3\n\tout=3\n\teol=' '\nfi &&\nprintf 'Looking for %s %s in %s.%s' \\\n\t\"${name}\" \"${type}\" \"${include}\" \"${eol}\" &&\nprintf \"\\\n#include <%s>\n\n%s\n\" \"$include\" \"$code\" > \"${temp}\" &&\nif ${CC} ${CPPFLAGS} ${EXTRA_CPPFLAGS} ${CFLAGS} ${EXTRA_CFLAGS} \\\n\t${AUTO_CONFIG_CFLAGS} \\\n\t-c -o /dev/null \"${temp}\" 1>&${out} 2>&${err}\nthen\n\trm -f \"${temp}\"\n\tprintf \"\\\n#ifndef %s\n#define %s 1\n#endif /* %s */\n\n\" \"${macro}\" \"${macro}\" \"${macro}\" >> \"${file}\" &&\n\tprintf 'Defining %s.\\n' \"${macro}\"\nelse\n\trm -f \"${temp}\"\n\tprintf \"\\\n/* %s is not defined. */\n\n\" \"${macro}\" >> \"${file}\" &&\n\tprintf 'Not defining %s.\\n' \"${macro}\"\nfi\n\nexit\n" }, { "path": "scripts/check-maintainers.sh", "content": "#! /bin/sh\n\n# BSD LICENSE\n#\n# Copyright 2015 6WIND S.A.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# Do some basic checks in MAINTAINERS file\n\ncd $(dirname $0)/..\n\n# Get files matching paths with wildcards and / meaning recursing\nfiles () # [ ...]\n{\n\tif [ -z \"$1\" ] ; then\n\t\treturn\n\tfi\n\tif [ -d .git ] ; then\n\t\tgit ls-files \"$1\"\n\telse\n\t\tfind \"$1\" -type f |\n\t\tsed 's,^\\./,,'\n\tfi |\n\t# if not ended by /\n\tif ! echo \"$1\" | grep -q '/[[:space:]]*$' ; then\n\t\t# filter out deeper directories\n\t\tsed \"/\\(\\/[^/]*\\)\\{$(($(echo \"$1\" | grep -o / | wc -l) + 1))\\}/d\"\n\telse\n\t\tcat\n\tfi\n\t# next path\n\tshift\n\tfiles \"$@\"\n}\n\n# Get all files matching F: and X: fields\nparse_fx () # \n{\n\tIFS='\n'\n\t# parse each line excepted underlining\n\tfor line in $( (sed '/^-\\+$/d' $1 ; echo) | sed 's,^$,§,') ; do\n\t\tif echo \"$line\" | grep -q '^§$' ; then\n\t\t\t# empty line delimit end of section\n\t\t\twhitelist=$(files $flines)\n\t\t\tblacklist=$(files $xlines)\n\t\t\tmatch=$(aminusb \"$whitelist\" \"$blacklist\")\n\t\t\tif [ -n \"$whitelist\" ] ; then\n\t\t\t\tprintf \"# $title \"\n\t\t\t\tmaintainers=$(echo \"$maintainers\" | sed -r 's,.*<(.*)>.*,\\1,')\n\t\t\t\tmaintainers=$(printf \"$maintainers\" | sed -e 's,^,<,' -e 's,$,>,')\n\t\t\t\techo $maintainers\n\t\t\tfi\n\t\t\tif [ -n \"$match\" ] ; then\n\t\t\t\techo \"$match\"\n\t\t\tfi\n\t\t\t# flush section\n\t\t\tunset maintainers\n\t\t\tunset flines\n\t\t\tunset xlines\n\t\telif echo \"$line\" | grep -q '^[A-Z]: ' ; then\n\t\t\t# maintainer\n\t\t\tmaintainers=$(add_line_to_if \"$line\" \"$maintainers\" 'M: ')\n\t\t\t# file matching pattern\n\t\t\tflines=$(add_line_to_if \"$line\" \"$flines\" 'F: ')\n\t\t\t# file exclusion pattern\n\t\t\txlines=$(add_line_to_if \"$line\" \"$xlines\" 'X: ')\n\t\telse # assume it is a title\n\t\t\ttitle=\"$line\"\n\t\tfi\n\tdone\n}\n\n# Check patterns in F: and X:\ncheck_fx () # \n{\n\tIFS='\n'\n\tfor line in $(sed -n 's,^[FX]: ,,p' $1 | tr '*' '#') ; do\n\t\tline=$(printf \"$line\" | tr '#' '*')\n\t\tmatch=$(files \"$line\")\n\t\tif [ -z \"$match\" ] ; then\n\t\t\techo \"$line\"\n\t\tfi\n\tdone\n}\n\n# Add a line to a set of lines if it begins with right pattern\nadd_line_to_if () # \n{\n\t(\n\t\techo \"$2\"\n\t\techo \"$1\" | sed -rn \"s,^$3(.*),\\1,p\"\n\t) |\n\tsed '/^$/d'\n}\n\n# Subtract two sets of lines\naminusb () # \n{\n\tprintf \"$1\\n$2\\n$2\" | sort | uniq -u | sed '/^$/d'\n}\n\nprintf 'sections: '\nparsed=$(parse_fx MAINTAINERS)\necho \"$parsed\" | grep -c '^#'\nprintf 'with maintainer: '\necho \"$parsed\" | grep -c '^#.*@'\nprintf 'maintainers: '\ngrep '^M:.*<' MAINTAINERS | sort -u | wc -l\n\necho\necho '##########'\necho '# orphan areas'\necho '##########'\necho \"$parsed\" | sed -rn 's,^#([^@]*)$,\\1,p' | uniq\n\necho\necho '##########'\necho '# files not listed'\necho '##########'\nall=$(files ./)\nlisted=$(echo \"$parsed\" | sed '/^#/d' | sort -u)\naminusb \"$all\" \"$listed\"\n\necho\necho '##########'\necho '# wrong patterns'\necho '##########'\ncheck_fx MAINTAINERS\n\n# TODO: check overlaps\n" }, { "path": "scripts/cocci/mtod-offset.cocci", "content": "//\n// Replace explicit packet offset computations with rte_pktmbuf_mtod_offset().\n//\n@disable paren@\ntypedef uint8_t;\nexpression M, O;\n@@\n(\n- rte_pktmbuf_mtod(M, char *) + O\n+ rte_pktmbuf_mtod_offset(M, char *, O)\n|\n- rte_pktmbuf_mtod(M, char *) - O\n+ rte_pktmbuf_mtod_offset(M, char *, -O)\n|\n- rte_pktmbuf_mtod(M, unsigned char *) + O\n+ rte_pktmbuf_mtod_offset(M, unsigned char *, O)\n|\n- rte_pktmbuf_mtod(M, unsigned char *) - O\n+ rte_pktmbuf_mtod_offset(M, unsigned char *, -O)\n|\n- rte_pktmbuf_mtod(M, uint8_t *) + O\n+ rte_pktmbuf_mtod_offset(M, uint8_t *, O)\n|\n- rte_pktmbuf_mtod(M, uint8_t *) - O\n+ rte_pktmbuf_mtod_offset(M, uint8_t *, -O)\n)\n\n\n//\n// Fold subsequent offset terms into pre-existing offset used in\n// rte_pktmbuf_mtod_offset().\n//\n@disable paren@\nexpression M, O1, O2;\n@@\n(\n- rte_pktmbuf_mtod_offset(M, char *, O1) + O2\n+ rte_pktmbuf_mtod_offset(M, char *, O1 + O2)\n|\n- rte_pktmbuf_mtod_offset(M, char *, O1) - O2\n+ rte_pktmbuf_mtod_offset(M, char *, O1 - O2)\n|\n- rte_pktmbuf_mtod_offset(M, unsigned char *, O1) + O2\n+ rte_pktmbuf_mtod_offset(M, unsigned char *, O1 + O2)\n|\n- rte_pktmbuf_mtod_offset(M, unsigned char *, O1) - O2\n+ rte_pktmbuf_mtod_offset(M, unsigned char *, O1 - O2)\n|\n- rte_pktmbuf_mtod_offset(M, uint8_t *, O1) + O2\n+ rte_pktmbuf_mtod_offset(M, uint8_t *, O1 + O2)\n|\n- rte_pktmbuf_mtod_offset(M, uint8_t *, O1) - O2\n+ rte_pktmbuf_mtod_offset(M, uint8_t *, O1 - O2)\n)\n\n\n//\n// Cleanup rules. Fold in double casts, remove unnecessary paranthesis, etc.\n//\n@disable paren@\nexpression M, O;\ntype C, T;\n@@\n(\n- (C)rte_pktmbuf_mtod_offset(M, T, O)\n+ rte_pktmbuf_mtod_offset(M, C, O)\n|\n- (rte_pktmbuf_mtod_offset(M, T, O))\n+ rte_pktmbuf_mtod_offset(M, T, O)\n|\n- (C)rte_pktmbuf_mtod(M, T)\n+ rte_pktmbuf_mtod(M, C)\n|\n- (rte_pktmbuf_mtod(M, T))\n+ rte_pktmbuf_mtod(M, T)\n)\n" }, { "path": "scripts/cocci.sh", "content": "#! /bin/sh\n\n# BSD LICENSE\n#\n# Copyright 2015 EZchip Semiconductor Ltd.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of EZchip Semiconductor nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# Apply coccinelle transforms.\n\nSRCTREE=$(readlink -f $(dirname $0)/..)\nCOCCI=$SRCTREE/scripts/cocci\n[ -n \"$SPATCH\" ] || SPATCH=$(which spatch)\n\nPATCH_LIST=\"$@\"\n[ -n \"$PATCH_LIST\" ] || PATCH_LIST=$(echo $COCCI/*.cocci)\n\n[ -x \"$SPATCH\" ] || (\n\techo \"Coccinelle tools not installed.\"\n\texit 1\n)\n\ntmp=$(mktemp)\n\nfor c in $PATCH_LIST; do\n\twhile true; do\n\t\techo -n \"Applying $c...\"\n\t\t$SPATCH --sp-file $c -c --linux-spacing --very-quiet\t\\\n\t\t\t--include-headers --preprocess\t\t\t\\\n\t\t\t--in-place --dir $SRCTREE > $tmp\n\t\tif [ -s $tmp ]; then\n\t\t\techo \" changes applied, retrying.\"\n\t\telse\n\t\t\techo \" no change.\"\n\t\t\tbreak;\n\t\tfi\n\tdone\ndone\n\nrm -f $tmp\n" }, { "path": "scripts/depdirs-rule.sh", "content": "#!/bin/sh\n\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# This (obscure) bash script finds the smallest different path between\n# path1 and path2 given as command line argument. The given paths MUST\n# be relative paths, the script is not designed to work with absolute\n# paths.\n#\n# The script will then generate Makefile code that can be saved in a\n# file and included in build system.\n#\n# For instance:\n# depdirs-rule.sh a/b/c/d a/b/e/f\n# Will print:\n# FULL_DEPDIRS-a/b/c/d += a/b/e/f\n# LOCAL_DEPDIRS-a/b/c += a/b/e\n#\n# The script returns 0 except if invalid arguments are given.\n#\n\nif [ $# -ne 2 ]; then\n\techo \"Bad arguments\"\n\techo \"Usage:\"\n\techo \" $0 path1 path2\"\n\texit 1\nfi\n\nleft1=${1%%/*}\nright1=${1#*/}\nprev_right1=$1\nprev_left1=\n\nleft2=${2%%/*}\nright2=${2#*/}\nprev_right2=$2\nprev_left2=\n\nwhile [ \"${right1}\" != \"\" -a \"${right2}\" != \"\" ]; do\n\n\tif [ \"$left1\" != \"$left2\" ]; then\n\t\tbreak\n\tfi\n\n\tprev_left1=$left1\n\tleft1=$left1/${right1%%/*}\n\tprev_right1=$right1\n\tright1=${prev_right1#*/}\n\tif [ \"$right1\" = \"$prev_right1\" ]; then\n\t\tright1=\"\"\n\tfi\n\n\tprev_left2=$left2\n\tleft2=$left2/${right2%%/*}\n\tprev_right2=$right2\n\tright2=${prev_right2#*/}\n\tif [ \"$right2\" = \"$prev_right2\" ]; then\n\t\tright2=\"\"\n\tfi\ndone\n\necho FULL_DEPDIRS-$1 += $2\necho LOCAL_DEPDIRS-$left1 += $left2\n\nexit 0\n" }, { "path": "scripts/gen-build-mk.sh", "content": "#!/bin/sh\n\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# Auto-generate a Makefile in build directory\n# Args:\n# $1: path of project src root\n# $2: path of build dir (can be relative to $1)\n\necho \"# Automatically generated by gen-build-mk.sh\"\necho\necho \"ifdef O\"\necho \"ifeq (\\\"\\$(origin O)\\\", \\\"command line\\\")\"\necho \"\\$(error \\\"Cannot specify O= as you are already in a build directory\\\")\"\necho \"endif\"\necho \"endif\"\necho\necho \"MAKEFLAGS += --no-print-directory\"\necho\necho \"all:\"\necho \"\t@\\$(MAKE) -C $1 O=$2\"\necho\necho \"%::\"\necho \"\t@\\$(MAKE) -C $1 O=$2 \\$@\"\n" }, { "path": "scripts/gen-config-h.sh", "content": "#!/bin/sh\n\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\necho \"#ifndef __RTE_CONFIG_H\"\necho \"#define __RTE_CONFIG_H\"\ngrep CONFIG_ $1 |\ngrep -v '^[ \\t]*#' |\nsed 's,CONFIG_\\(.*\\)=y.*$,#undef \\1\\\n#define \\1 1,' |\nsed 's,CONFIG_\\(.*\\)=n.*$,#undef \\1,' |\nsed 's,CONFIG_\\(.*\\)=\\(.*\\)$,#undef \\1\\\n#define \\1 \\2,' |\nsed 's,\\# CONFIG_\\(.*\\) is not set$,#undef \\1,'\necho \"#endif /* __RTE_CONFIG_H */\"\n" }, { "path": "scripts/relpath.sh", "content": "#!/bin/sh\n\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# print the relative path of $1 from $2 directory\n# $1 and $2 MUST be absolute paths\n#\n\nif [ $# -ne 2 ]; then\n\techo \"Bad arguments\"\n\techo \"Usage:\"\n\techo \" $0 path1 path2\"\n\texit 1\nfi\n\n# get the real absolute path, derefencing symlinks\nABS1=$(readlink -f $1)\nABS2=$(readlink -f $2)\n\n# remove leading slash\nREL1=${ABS1#/}\nREL2=${ABS2#/}\n\nleft1=${REL1%%/*}\nright1=${REL1#*/}\nprev_right1=$REL1\nprev_left1=\n\nleft2=${REL2%%/*}\nright2=${REL2#*/}\nprev_right2=$REL2\nprev_left2=\n\nwhile [ \"${right1}\" != \"\" -a \"${right2}\" != \"\" ]; do\n\n\tif [ \"$left1\" != \"$left2\" ]; then\n\t\tbreak\n\tfi\n\n\tprev_left1=$left1\n\tleft1=$left1/${right1%%/*}\n\tprev_right1=$right1\n\tright1=${prev_right1#*/}\n\tif [ \"$right1\" = \"$prev_right1\" ]; then\n\t\tright1=\"\"\n\tfi\n\n\tprev_left2=$left2\n\tleft2=$left2/${right2%%/*}\n\tprev_right2=$right2\n\tright2=${prev_right2#*/}\n\tif [ \"$right2\" = \"$prev_right2\" ]; then\n\t\tright2=\"\"\n\tfi\ndone\n\nif [ \"${left1}\" != \"${left2}\" ]; then\n\tright2=${prev_right2}\n\tright1=${prev_right1}\nfi\n\nwhile [ \"${right2}\" != \"\" ]; do\n\tprefix=${prefix}../\n\tprev_right2=$right2\n\tright2=${right2#*/}\n\tif [ \"$right2\" = \"$prev_right2\" ]; then\n\t\tright2=\"\"\n\tfi\ndone\n\necho ${prefix}${right1}\n\nexit 0\n" }, { "path": "scripts/test-null.sh", "content": "#! /bin/sh -e\n\n# BSD LICENSE\n#\n# Copyright 2015 6WIND S.A.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of 6WIND S.A. nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n# Run a quick testpmd forwarding with null PMD without hugepage\n\nbuild=${1:-build}\ncoremask=${2:-3} # default using cores 0 and 1\n\nif grep -q SHARED_LIB=y $build/.config; then\n\texport LD_LIBRARY_PATH=$build/lib:$LD_LIBRARY_PATH\n\tpmd='-d librte_pmd_null.so'\nfi\n\n(sleep 1 && echo stop) |\n$build/app/testpmd -c $coremask -n 1 --no-huge \\\n\t$pmd --vdev eth_null1 --vdev eth_null2 -- \\\n\t--total-num-mbufs=2048 -ia\n" }, { "path": "scripts/validate-abi.sh", "content": "#!/bin/sh\n# BSD LICENSE\n#\n# Copyright(c) 2015 Neil Horman. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\nTAG1=$1\nTAG2=$2\nTARGET=$3\nABI_DIR=`mktemp -d -p /tmp ABI.XXXXXX`\n\nusage() {\n\techo \"$0 \"\n}\n\nlog() {\n\tlocal level=$1\n\tshift\n\techo \"$*\"\n}\n\nvalidate_tags() {\n\tgit tag -l | grep -q \"$TAG1\"\n\tif [ $? -ne 0 ]\n\tthen\n\t\techo \"$TAG1 is invalid\"\n\t\treturn\n\tfi\n\tgit tag -l | grep -q \"$TAG2\"\n\tif [ $? -ne 0 ]\n\tthen\n\t\techo \"$TAG2 is invalid\"\n\t\treturn\n\tfi\n}\n\nvalidate_args() {\n\tif [ -z \"$TAG1\" ]\n\tthen\n\t\techo \"Must Specify TAG1\"\n\t\treturn\n\tfi\n\tif [ -z \"$TAG2\" ]\n\tthen\n\t\techo \"Must Specify TAG2\"\n\t\treturn\n\tfi\n\tif [ -z \"$TARGET\" ]\n\tthen\n\t\techo \"Must Specify a build target\"\n\tfi\n}\n\n\ncleanup_and_exit() {\n\trm -rf $ABI_DIR\n\tgit checkout $CURRENT_BRANCH\n\texit $1\n}\n\n###########################################\n#START\n############################################\n\n#trap on ctrl-c to clean up\ntrap cleanup_and_exit SIGINT\n\n#Save the current branch\nCURRENT_BRANCH=`git branch | grep \\* | cut -d' ' -f2`\n\nif [ -z \"$CURRENT_BRANCH\" ]\nthen\n\tCURRENT_BRANCH=`git log --pretty=format:%H HEAD~1..HEAD`\nfi\n\nif [ -n \"$VERBOSE\" ]\nthen\n\texport VERBOSE=/dev/stdout\nelse\n\texport VERBOSE=/dev/null\nfi\n\n# Validate that we have all the arguments we need\nres=$(validate_args)\nif [ -n \"$res\" ]\nthen\n\techo $res\n\tusage\n\tcleanup_and_exit 1\nfi\n\n# Make sure our tags exist\nres=$(validate_tags)\nif [ -n \"$res\" ]\nthen\n\techo $res\n\tcleanup_and_exit 1\nfi\n\nABICHECK=`which abi-compliance-checker 2>/dev/null`\nif [ $? -ne 0 ]\nthen\n\tlog \"INFO\" \"Cant find abi-compliance-checker utility\"\n\tcleanup_and_exit 1\nfi\n\nABIDUMP=`which abi-dumper 2>/dev/null`\nif [ $? -ne 0 ]\nthen\n\tlog \"INFO\" \"Cant find abi-dumper utility\"\n\tcleanup_and_exit 1\nfi\n\nlog \"INFO\" \"We're going to check and make sure that applications built\"\nlog \"INFO\" \"against DPDK DSOs from tag $TAG1 will still run when executed\"\nlog \"INFO\" \"against DPDK DSOs built from tag $TAG2.\"\nlog \"INFO\" \"\"\n\n# Check to make sure we have a clean tree\ngit status | grep -q clean\nif [ $? -ne 0 ]\nthen\n\tlog \"WARN\" \"Working directory not clean, aborting\"\n\tcleanup_and_exit 1\nfi\n\n# Move to the root of the git tree\ncd $(dirname $0)/..\n\nlog \"INFO\" \"Checking out version $TAG1 of the dpdk\"\n# Move to the old version of the tree\ngit checkout $TAG1\n\n# Make sure we configure SHARED libraries\n# Also turn off IGB and KNI as those require kernel headers to build\nsed -i -e\"$ a\\CONFIG_RTE_BUILD_SHARED_LIB=y\" config/defconfig_$TARGET\nsed -i -e\"$ a\\CONFIG_RTE_NEXT_ABI=n\" config/defconfig_$TARGET\nsed -i -e\"$ a\\CONFIG_RTE_EAL_IGB_UIO=n\" config/defconfig_$TARGET\nsed -i -e\"$ a\\CONFIG_RTE_LIBRTE_KNI=n\" config/defconfig_$TARGET\n\n# Checking abi compliance relies on using the dwarf information in\n# The shared objects. Thats only included in the DSO's if we build\n# with -g\nexport EXTRA_CFLAGS=-g\nexport EXTRA_LDFLAGS=-g\n\n# Now configure the build\nlog \"INFO\" \"Configuring DPDK $TAG1\"\nmake config T=$TARGET O=$TARGET > $VERBOSE 2>&1\n\nlog \"INFO\" \"Building DPDK $TAG1. This might take a moment\"\nmake O=$TARGET > $VERBOSE 2>&1\n\nif [ $? -ne 0 ]\nthen\n\tlog \"INFO\" \"THE BUILD FAILED. ABORTING\"\n\tcleanup_and_exit 1\nfi\n\n# Move to the lib directory\ncd $TARGET/lib\nlog \"INFO\" \"COLLECTING ABI INFORMATION FOR $TAG1\"\nfor i in `ls *.so`\ndo\n\t$ABIDUMP $i -o $ABI_DIR/$i-ABI-0.dump -lver $TAG1\ndone\ncd ../..\n\n# Now clean the tree, checkout the second tag, and rebuild\ngit clean -f -d\ngit reset --hard\n# Move to the new version of the tree\nlog \"INFO\" \"Checking out version $TAG2 of the dpdk\"\ngit checkout $TAG2\n\n# Make sure we configure SHARED libraries\n# Also turn off IGB and KNI as those require kernel headers to build\nsed -i -e\"$ a\\CONFIG_RTE_BUILD_SHARED_LIB=y\" config/defconfig_$TARGET\nsed -i -e\"$ a\\CONFIG_RTE_NEXT_ABI=n\" config/defconfig_$TARGET\nsed -i -e\"$ a\\CONFIG_RTE_EAL_IGB_UIO=n\" config/defconfig_$TARGET\nsed -i -e\"$ a\\CONFIG_RTE_LIBRTE_KNI=n\" config/defconfig_$TARGET\n\n# Now configure the build\nlog \"INFO\" \"Configuring DPDK $TAG2\"\nmake config T=$TARGET O=$TARGET > $VERBOSE 2>&1\n\nlog \"INFO\" \"Building DPDK $TAG2. This might take a moment\"\nmake O=$TARGET > $VERBOSE 2>&1\n\nif [ $? -ne 0 ]\nthen\n\tlog \"INFO\" \"THE BUILD FAILED. ABORTING\"\n\tcleanup_and_exit 1\nfi\n\ncd $TARGET/lib\nlog \"INFO\" \"COLLECTING ABI INFORMATION FOR $TAG2\"\nfor i in `ls *.so`\ndo\n\t$ABIDUMP $i -o $ABI_DIR/$i-ABI-1.dump -lver $TAG2\ndone\ncd ../..\n\n# Start comparison of ABI dumps\nfor i in `ls $ABI_DIR/*-1.dump`\ndo\n\tNEWNAME=`basename $i`\n\tOLDNAME=`basename $i | sed -e\"s/1.dump/0.dump/\"`\n\tLIBNAME=`basename $i | sed -e\"s/-ABI-1.dump//\"`\n\n\tif [ ! -f $ABI_DIR/$OLDNAME ]\n\tthen\n\t\tlog \"INFO\" \"$OLDNAME DOES NOT EXIST IN $TAG1. SKIPPING...\"\n\tfi\n\n\t#compare the abi dumps\n\t$ABICHECK -l $LIBNAME -old $ABI_DIR/$OLDNAME -new $ABI_DIR/$NEWNAME\ndone\n\ngit reset --hard\nlog \"INFO\" \"ABI CHECK COMPLETE. REPORTS ARE IN compat_report directory\"\ncleanup_and_exit 0\n" }, { "path": "tools/cpu_layout.py", "content": "#! /usr/bin/python\n#\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\nimport sys\n\nsockets = []\ncores = []\ncore_map = {}\n\nfd=open(\"/proc/cpuinfo\")\nlines = fd.readlines()\nfd.close()\n\ncore_details = []\ncore_lines = {}\nfor line in lines:\n\tif len(line.strip()) != 0:\n\t\tname, value = line.split(\":\", 1)\n\t\tcore_lines[name.strip()] = value.strip()\n\telse:\n\t\tcore_details.append(core_lines)\n\t\tcore_lines = {}\n\nfor core in core_details:\n\tfor field in [\"processor\", \"core id\", \"physical id\"]:\n\t\tif field not in core:\n\t\t\tprint \"Error getting '%s' value from /proc/cpuinfo\" % field\n\t\t\tsys.exit(1)\n\t\tcore[field] = int(core[field])\n\n\tif core[\"core id\"] not in cores:\n\t\tcores.append(core[\"core id\"])\n\tif core[\"physical id\"] not in sockets:\n\t\tsockets.append(core[\"physical id\"])\n\tkey = (core[\"physical id\"], core[\"core id\"])\n\tif key not in core_map:\n\t\tcore_map[key] = []\n\tcore_map[key].append(core[\"processor\"])\n\nprint \"============================================================\"\nprint \"Core and Socket Information (as reported by '/proc/cpuinfo')\"\nprint \"============================================================\\n\"\nprint \"cores = \",cores\nprint \"sockets = \", sockets\nprint \"\"\n\nmax_processor_len = len(str(len(cores) * len(sockets) * 2 - 1))\nmax_core_map_len = max_processor_len * 2 + len('[, ]') + len('Socket ')\nmax_core_id_len = len(str(max(cores)))\n\nprint \" \".ljust(max_core_id_len + len('Core ')),\nfor s in sockets:\n print \"Socket %s\" % str(s).ljust(max_core_map_len - len('Socket ')),\nprint \"\"\nprint \" \".ljust(max_core_id_len + len('Core ')),\nfor s in sockets:\n print \"--------\".ljust(max_core_map_len),\nprint \"\"\n\nfor c in cores:\n print \"Core %s\" % str(c).ljust(max_core_id_len),\n for s in sockets:\n print str(core_map[(s,c)]).ljust(max_core_map_len),\n print \"\\n\"\n" }, { "path": "tools/dpdk_nic_bind.py", "content": "#! /usr/bin/python\n#\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n\nimport sys, os, getopt, subprocess\nfrom os.path import exists, abspath, dirname, basename\n\n\n# The PCI device class for ETHERNET devices\nETHERNET_CLASS = \"0200\"\n\n# global dict ethernet devices present. Dictionary indexed by PCI address.\n# Each device within this is itself a dictionary of device properties\ndevices = {}\n# list of supported DPDK drivers\ndpdk_drivers = [ \"igb_uio\", \"vfio-pci\", \"uio_pci_generic\" ]\n\n# command-line arg flags\nb_flag = None\nstatus_flag = False\nforce_flag = False\nargs = []\n\ndef usage():\n '''Print usage information for the program'''\n argv0 = basename(sys.argv[0])\n print \"\"\"\nUsage:\n------\n\n %(argv0)s [options] DEVICE1 DEVICE2 ....\n\nwhere DEVICE1, DEVICE2 etc, are specified via PCI \"domain:bus:slot.func\" syntax\nor \"bus:slot.func\" syntax. For devices bound to Linux kernel drivers, they may\nalso be referred to by Linux interface name e.g. eth0, eth1, em0, em1, etc.\n\nOptions:\n --help, --usage:\n Display usage information and quit\n\n --status:\n Print the current status of all known network interfaces.\n For each device, it displays the PCI domain, bus, slot and function,\n along with a text description of the device. Depending upon whether the\n device is being used by a kernel driver, the igb_uio driver, or no\n driver, other relevant information will be displayed:\n * the Linux interface name e.g. if=eth0\n * the driver being used e.g. drv=igb_uio\n * any suitable drivers not currently using that device\n e.g. unused=igb_uio\n NOTE: if this flag is passed along with a bind/unbind option, the status\n display will always occur after the other operations have taken place.\n\n -b driver, --bind=driver:\n Select the driver to use or \\\"none\\\" to unbind the device\n\n -u, --unbind:\n Unbind a device (Equivalent to \\\"-b none\\\")\n\n --force:\n By default, devices which are used by Linux - as indicated by having\n routes in the routing table - cannot be modified. Using the --force\n flag overrides this behavior, allowing active links to be forcibly\n unbound.\n WARNING: This can lead to loss of network connection and should be used\n with caution.\n\nExamples:\n---------\n\nTo display current device status:\n %(argv0)s --status\n\nTo bind eth1 from the current driver and move to use igb_uio\n %(argv0)s --bind=igb_uio eth1\n\nTo unbind 0000:01:00.0 from using any driver\n %(argv0)s -u 0000:01:00.0\n\nTo bind 0000:02:00.0 and 0000:02:00.1 to the ixgbe kernel driver\n %(argv0)s -b ixgbe 02:00.0 02:00.1\n\n \"\"\" % locals() # replace items from local variables\n\n# This is roughly compatible with check_output function in subprocess module\n# which is only available in python 2.7.\ndef check_output(args, stderr=None):\n '''Run a command and capture its output'''\n return subprocess.Popen(args, stdout=subprocess.PIPE,\n stderr=stderr).communicate()[0]\n\ndef find_module(mod):\n '''find the .ko file for kernel module named mod.\n Searches the $RTE_SDK/$RTE_TARGET directory, the kernel\n modules directory and finally under the parent directory of\n the script '''\n # check $RTE_SDK/$RTE_TARGET directory\n if 'RTE_SDK' in os.environ and 'RTE_TARGET' in os.environ:\n path = \"%s/%s/kmod/%s.ko\" % (os.environ['RTE_SDK'],\\\n os.environ['RTE_TARGET'], mod)\n if exists(path):\n return path\n\n # check using depmod\n try:\n depmod_out = check_output([\"modinfo\", \"-n\", mod], \\\n stderr=subprocess.STDOUT).lower()\n if \"error\" not in depmod_out:\n path = depmod_out.strip()\n if exists(path):\n return path\n except: # if modinfo can't find module, it fails, so continue\n pass\n\n # check for a copy based off current path\n tools_dir = dirname(abspath(sys.argv[0]))\n if (tools_dir.endswith(\"tools\")):\n base_dir = dirname(tools_dir)\n find_out = check_output([\"find\", base_dir, \"-name\", mod + \".ko\"])\n if len(find_out) > 0: #something matched\n path = find_out.splitlines()[0]\n if exists(path):\n return path\n\ndef check_modules():\n '''Checks that igb_uio is loaded'''\n global dpdk_drivers\n\n fd = file(\"/proc/modules\")\n loaded_mods = fd.readlines()\n fd.close()\n\n # list of supported modules\n mods = [{\"Name\" : driver, \"Found\" : False} for driver in dpdk_drivers]\n\n # first check if module is loaded\n for line in loaded_mods:\n for mod in mods:\n if line.startswith(mod[\"Name\"]):\n mod[\"Found\"] = True\n # special case for vfio_pci (module is named vfio-pci,\n # but its .ko is named vfio_pci)\n elif line.replace(\"_\", \"-\").startswith(mod[\"Name\"]):\n mod[\"Found\"] = True\n\n # check if we have at least one loaded module\n if True not in [mod[\"Found\"] for mod in mods] and b_flag is not None:\n if b_flag in dpdk_drivers:\n print \"Error - no supported modules(DPDK driver) are loaded\"\n sys.exit(1)\n else:\n print \"Warning - no supported modules(DPDK driver) are loaded\"\n\n # change DPDK driver list to only contain drivers that are loaded\n dpdk_drivers = [mod[\"Name\"] for mod in mods if mod[\"Found\"]]\n\ndef has_driver(dev_id):\n '''return true if a device is assigned to a driver. False otherwise'''\n return \"Driver_str\" in devices[dev_id]\n\ndef get_pci_device_details(dev_id):\n '''This function gets additional details for a PCI device'''\n device = {}\n\n extra_info = check_output([\"lspci\", \"-vmmks\", dev_id]).splitlines()\n\n # parse lspci details\n for line in extra_info:\n if len(line) == 0:\n continue\n name, value = line.split(\"\\t\", 1)\n name = name.strip(\":\") + \"_str\"\n device[name] = value\n # check for a unix interface name\n sys_path = \"/sys/bus/pci/devices/%s/net/\" % dev_id\n if exists(sys_path):\n device[\"Interface\"] = \",\".join(os.listdir(sys_path))\n else:\n device[\"Interface\"] = \"\"\n # check if a port is used for ssh connection\n device[\"Ssh_if\"] = False\n device[\"Active\"] = \"\"\n\n return device\n\ndef get_nic_details():\n '''This function populates the \"devices\" dictionary. The keys used are\n the pci addresses (domain:bus:slot.func). The values are themselves\n dictionaries - one for each NIC.'''\n global devices\n global dpdk_drivers\n\n # clear any old data\n devices = {}\n # first loop through and read details for all devices\n # request machine readable format, with numeric IDs\n dev = {};\n dev_lines = check_output([\"lspci\", \"-Dvmmn\"]).splitlines()\n for dev_line in dev_lines:\n if (len(dev_line) == 0):\n if dev[\"Class\"] == ETHERNET_CLASS:\n #convert device and vendor ids to numbers, then add to global\n dev[\"Vendor\"] = int(dev[\"Vendor\"],16)\n dev[\"Device\"] = int(dev[\"Device\"],16)\n devices[dev[\"Slot\"]] = dict(dev) # use dict to make copy of dev\n else:\n name, value = dev_line.split(\"\\t\", 1)\n dev[name.rstrip(\":\")] = value\n\n # check what is the interface if any for an ssh connection if\n # any to this host, so we can mark it later.\n ssh_if = []\n route = check_output([\"ip\", \"-o\", \"route\"])\n # filter out all lines for 169.254 routes\n route = \"\\n\".join(filter(lambda ln: not ln.startswith(\"169.254\"),\n route.splitlines()))\n rt_info = route.split()\n for i in xrange(len(rt_info) - 1):\n if rt_info[i] == \"dev\":\n ssh_if.append(rt_info[i+1])\n\n # based on the basic info, get extended text details\n for d in devices.keys():\n # get additional info and add it to existing data\n devices[d] = dict(devices[d].items() +\n get_pci_device_details(d).items())\n\n for _if in ssh_if:\n if _if in devices[d][\"Interface\"].split(\",\"):\n devices[d][\"Ssh_if\"] = True\n devices[d][\"Active\"] = \"*Active*\"\n break;\n\n # add igb_uio to list of supporting modules if needed\n if \"Module_str\" in devices[d]:\n for driver in dpdk_drivers:\n if driver not in devices[d][\"Module_str\"]:\n devices[d][\"Module_str\"] = devices[d][\"Module_str\"] + \",%s\" % driver\n else:\n devices[d][\"Module_str\"] = \",\".join(dpdk_drivers)\n\n # make sure the driver and module strings do not have any duplicates\n if has_driver(d):\n modules = devices[d][\"Module_str\"].split(\",\")\n if devices[d][\"Driver_str\"] in modules:\n modules.remove(devices[d][\"Driver_str\"])\n devices[d][\"Module_str\"] = \",\".join(modules)\n\ndef dev_id_from_dev_name(dev_name):\n '''Take a device \"name\" - a string passed in by user to identify a NIC\n device, and determine the device id - i.e. the domain:bus:slot.func - for\n it, which can then be used to index into the devices array'''\n dev = None\n # check if it's already a suitable index\n if dev_name in devices:\n return dev_name\n # check if it's an index just missing the domain part\n elif \"0000:\" + dev_name in devices:\n return \"0000:\" + dev_name\n else:\n # check if it's an interface name, e.g. eth1\n for d in devices.keys():\n if dev_name in devices[d][\"Interface\"].split(\",\"):\n return devices[d][\"Slot\"]\n # if nothing else matches - error\n print \"Unknown device: %s. \" \\\n \"Please specify device in \\\"bus:slot.func\\\" format\" % dev_name\n sys.exit(1)\n\ndef unbind_one(dev_id, force):\n '''Unbind the device identified by \"dev_id\" from its current driver'''\n dev = devices[dev_id]\n if not has_driver(dev_id):\n print \"%s %s %s is not currently managed by any driver\\n\" % \\\n (dev[\"Slot\"], dev[\"Device_str\"], dev[\"Interface\"])\n return\n\n # prevent us disconnecting ourselves\n if dev[\"Ssh_if\"] and not force:\n print \"Routing table indicates that interface %s is active\" \\\n \". Skipping unbind\" % (dev_id)\n return\n\n # write to /sys to unbind\n filename = \"/sys/bus/pci/drivers/%s/unbind\" % dev[\"Driver_str\"]\n try:\n f = open(filename, \"a\")\n except:\n print \"Error: unbind failed for %s - Cannot open %s\" % (dev_id, filename)\n sys/exit(1)\n f.write(dev_id)\n f.close()\n\ndef bind_one(dev_id, driver, force):\n '''Bind the device given by \"dev_id\" to the driver \"driver\". If the device\n is already bound to a different driver, it will be unbound first'''\n dev = devices[dev_id]\n saved_driver = None # used to rollback any unbind in case of failure\n\n # prevent disconnection of our ssh session\n if dev[\"Ssh_if\"] and not force:\n print \"Routing table indicates that interface %s is active\" \\\n \". Not modifying\" % (dev_id)\n return\n\n # unbind any existing drivers we don't want\n if has_driver(dev_id):\n if dev[\"Driver_str\"] == driver:\n print \"%s already bound to driver %s, skipping\\n\" % (dev_id, driver)\n return\n else:\n saved_driver = dev[\"Driver_str\"]\n unbind_one(dev_id, force)\n dev[\"Driver_str\"] = \"\" # clear driver string\n\n # if we are binding to one of DPDK drivers, add PCI id's to that driver\n if driver in dpdk_drivers:\n filename = \"/sys/bus/pci/drivers/%s/new_id\" % driver\n try:\n f = open(filename, \"w\")\n except:\n print \"Error: bind failed for %s - Cannot open %s\" % (dev_id, filename)\n return\n try:\n f.write(\"%04x %04x\" % (dev[\"Vendor\"], dev[\"Device\"]))\n f.close()\n except:\n print \"Error: bind failed for %s - Cannot write new PCI ID to \" \\\n \"driver %s\" % (dev_id, driver)\n return\n\n # do the bind by writing to /sys\n filename = \"/sys/bus/pci/drivers/%s/bind\" % driver\n try:\n f = open(filename, \"a\")\n except:\n print \"Error: bind failed for %s - Cannot open %s\" % (dev_id, filename)\n if saved_driver is not None: # restore any previous driver\n bind_one(dev_id, saved_driver, force)\n return\n try:\n f.write(dev_id)\n f.close()\n except:\n # for some reason, closing dev_id after adding a new PCI ID to new_id\n # results in IOError. however, if the device was successfully bound,\n # we don't care for any errors and can safely ignore IOError\n tmp = get_pci_device_details(dev_id)\n if \"Driver_str\" in tmp and tmp[\"Driver_str\"] == driver:\n return\n print \"Error: bind failed for %s - Cannot bind to driver %s\" % (dev_id, driver)\n if saved_driver is not None: # restore any previous driver\n bind_one(dev_id, saved_driver, force)\n return\n\n\ndef unbind_all(dev_list, force=False):\n \"\"\"Unbind method, takes a list of device locations\"\"\"\n dev_list = map(dev_id_from_dev_name, dev_list)\n for d in dev_list:\n unbind_one(d, force)\n\ndef bind_all(dev_list, driver, force=False):\n \"\"\"Bind method, takes a list of device locations\"\"\"\n global devices\n\n dev_list = map(dev_id_from_dev_name, dev_list)\n\n for d in dev_list:\n bind_one(d, driver, force)\n\n # when binding devices to a generic driver (i.e. one that doesn't have a\n # PCI ID table), some devices that are not bound to any other driver could\n # be bound even if no one has asked them to. hence, we check the list of\n # drivers again, and see if some of the previously-unbound devices were\n # erroneously bound.\n for d in devices.keys():\n # skip devices that were already bound or that we know should be bound\n if \"Driver_str\" in devices[d] or d in dev_list:\n continue\n\n # update information about this device\n devices[d] = dict(devices[d].items() +\n get_pci_device_details(d).items())\n\n # check if updated information indicates that the device was bound\n if \"Driver_str\" in devices[d]:\n unbind_one(d, force)\n\ndef display_devices(title, dev_list, extra_params = None):\n '''Displays to the user the details of a list of devices given in \"dev_list\"\n The \"extra_params\" parameter, if given, should contain a string with\n %()s fields in it for replacement by the named fields in each device's\n dictionary.'''\n strings = [] # this holds the strings to print. We sort before printing\n print \"\\n%s\" % title\n print \"=\"*len(title)\n if len(dev_list) == 0:\n strings.append(\"\")\n else:\n for dev in dev_list:\n if extra_params is not None:\n strings.append(\"%s '%s' %s\" % (dev[\"Slot\"], \\\n dev[\"Device_str\"], extra_params % dev))\n else:\n strings.append(\"%s '%s'\" % (dev[\"Slot\"], dev[\"Device_str\"]))\n # sort before printing, so that the entries appear in PCI order\n strings.sort()\n print \"\\n\".join(strings) # print one per line\n\ndef show_status():\n '''Function called when the script is passed the \"--status\" option. Displays\n to the user what devices are bound to the igb_uio driver, the kernel driver\n or to no driver'''\n global dpdk_drivers\n kernel_drv = []\n dpdk_drv = []\n no_drv = []\n\n # split our list of devices into the three categories above\n for d in devices.keys():\n if not has_driver(d):\n no_drv.append(devices[d])\n continue\n if devices[d][\"Driver_str\"] in dpdk_drivers:\n dpdk_drv.append(devices[d])\n else:\n kernel_drv.append(devices[d])\n\n # print each category separately, so we can clearly see what's used by DPDK\n display_devices(\"Network devices using DPDK-compatible driver\", dpdk_drv, \\\n \"drv=%(Driver_str)s unused=%(Module_str)s\")\n display_devices(\"Network devices using kernel driver\", kernel_drv,\n \"if=%(Interface)s drv=%(Driver_str)s unused=%(Module_str)s %(Active)s\")\n display_devices(\"Other network devices\", no_drv,\\\n \"unused=%(Module_str)s\")\n\ndef parse_args():\n '''Parses the command-line arguments given by the user and takes the\n appropriate action for each'''\n global b_flag\n global status_flag\n global force_flag\n global args\n if len(sys.argv) <= 1:\n usage()\n sys.exit(0)\n\n try:\n opts, args = getopt.getopt(sys.argv[1:], \"b:u\",\n [\"help\", \"usage\", \"status\", \"force\",\n \"bind=\", \"unbind\"])\n except getopt.GetoptError, error:\n print str(error)\n print \"Run '%s --usage' for further information\" % sys.argv[0]\n sys.exit(1)\n\n for opt, arg in opts:\n if opt == \"--help\" or opt == \"--usage\":\n usage()\n sys.exit(0)\n if opt == \"--status\":\n status_flag = True\n if opt == \"--force\":\n force_flag = True\n if opt == \"-b\" or opt == \"-u\" or opt == \"--bind\" or opt == \"--unbind\":\n if b_flag is not None:\n print \"Error - Only one bind or unbind may be specified\\n\"\n sys.exit(1)\n if opt == \"-u\" or opt == \"--unbind\":\n b_flag = \"none\"\n else:\n b_flag = arg\n\ndef do_arg_actions():\n '''do the actual action requested by the user'''\n global b_flag\n global status_flag\n global force_flag\n global args\n\n if b_flag is None and not status_flag:\n print \"Error: No action specified for devices. Please give a -b or -u option\"\n print \"Run '%s --usage' for further information\" % sys.argv[0]\n sys.exit(1)\n\n if b_flag is not None and len(args) == 0:\n print \"Error: No devices specified.\"\n print \"Run '%s --usage' for further information\" % sys.argv[0]\n sys.exit(1)\n\n if b_flag == \"none\" or b_flag == \"None\":\n unbind_all(args, force_flag)\n elif b_flag is not None:\n bind_all(args, b_flag, force_flag)\n if status_flag:\n if b_flag is not None:\n get_nic_details() # refresh if we have changed anything\n show_status()\n\ndef main():\n '''program main function'''\n parse_args()\n check_modules()\n get_nic_details()\n do_arg_actions()\n\nif __name__ == \"__main__\":\n main()\n" }, { "path": "tools/setup.sh", "content": "#! /bin/bash\n\n# BSD LICENSE\n#\n# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions\n# are met:\n#\n# * Redistributions of source code must retain the above copyright\n# notice, this list of conditions and the following disclaimer.\n# * Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in\n# the documentation and/or other materials provided with the\n# distribution.\n# * Neither the name of Intel Corporation nor the names of its\n# contributors may be used to endorse or promote products derived\n# from this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n#\n# Run with \"source /path/to/setup.sh\"\n#\n\n#\n# Change to DPDK directory ( /.. ), and export it as RTE_SDK\n#\ncd $(dirname ${BASH_SOURCE[0]})/..\nexport RTE_SDK=$PWD\necho \"------------------------------------------------------------------------------\"\necho \" RTE_SDK exported as $RTE_SDK\"\necho \"------------------------------------------------------------------------------\"\n\n#\n# Application EAL parameters for setting memory options (amount/channels/ranks).\n#\nEAL_PARAMS='-n 4'\n\n#\n# Sets QUIT variable so script will finish.\n#\nquit()\n{\n\tQUIT=$1\n}\n\n#\n# Sets up environmental variables for ICC.\n#\nsetup_icc()\n{\n\tDEFAULT_PATH=/opt/intel/bin/iccvars.sh\n\tparam=$1\n\tshpath=`which iccvars.sh 2> /dev/null`\n\tif [ $? -eq 0 ] ; then\n\t\techo \"Loading iccvars.sh from $shpath for $param\"\n\t\tsource $shpath $param\n\telif [ -f $DEFAULT_PATH ] ; then\n\t\techo \"Loading iccvars.sh from $DEFAULT_PATH for $param\"\n\t\tsource $DEFAULT_PATH $param\n\telse\n\t\techo \"## ERROR: cannot find 'iccvars.sh' script to set up ICC.\"\n\t\techo \"## To fix, please add the directory that contains\"\n\t\techo \"## iccvars.sh to your 'PATH' environment variable.\"\n\t\tquit\n\tfi\n}\n\n#\n# Sets RTE_TARGET and does a \"make install\".\n#\nsetup_target()\n{\n\toption=$1\n\texport RTE_TARGET=${TARGETS[option]}\n\n\tcompiler=${RTE_TARGET##*-}\n\tif [ \"$compiler\" == \"icc\" ] ; then\n\t\tplatform=${RTE_TARGET%%-*}\n\t\tif [ \"$platform\" == \"x86_64\" ] ; then\n\t\t\tsetup_icc intel64\n\t\telse\n\t\t\tsetup_icc ia32\n\t\tfi\n\tfi\n\tif [ \"$QUIT\" == \"0\" ] ; then\n\t\tmake install T=${RTE_TARGET}\n\tfi\n\techo \"------------------------------------------------------------------------------\"\n\techo \" RTE_TARGET exported as $RTE_TARGET\"\n\techo \"------------------------------------------------------------------------------\"\n}\n\n#\n# Uninstall all targets.\n#\nuninstall_targets()\n{\n\tmake uninstall\n}\n\n#\n# Creates hugepage filesystem.\n#\ncreate_mnt_huge()\n{\n\techo \"Creating /mnt/huge and mounting as hugetlbfs\"\n\tsudo mkdir -p /mnt/huge\n\n\tgrep -s '/mnt/huge' /proc/mounts > /dev/null\n\tif [ $? -ne 0 ] ; then\n\t\tsudo mount -t hugetlbfs nodev /mnt/huge\n\tfi\n}\n\n#\n# Removes hugepage filesystem.\n#\nremove_mnt_huge()\n{\n\techo \"Unmounting /mnt/huge and removing directory\"\n\tgrep -s '/mnt/huge' /proc/mounts > /dev/null\n\tif [ $? -eq 0 ] ; then\n\t\tsudo umount /mnt/huge\n\tfi\n\n\tif [ -d /mnt/huge ] ; then\n\t\tsudo rm -R /mnt/huge\n\tfi\n}\n\n#\n# Unloads igb_uio.ko.\n#\nremove_igb_uio_module()\n{\n\techo \"Unloading any existing DPDK UIO module\"\n\t/sbin/lsmod | grep -s igb_uio > /dev/null\n\tif [ $? -eq 0 ] ; then\n\t\tsudo /sbin/rmmod igb_uio\n\tfi\n}\n\n#\n# Loads new igb_uio.ko (and uio module if needed).\n#\nload_igb_uio_module()\n{\n\tif [ ! -f $RTE_SDK/$RTE_TARGET/kmod/igb_uio.ko ];then\n\t\techo \"## ERROR: Target does not have the DPDK UIO Kernel Module.\"\n\t\techo \" To fix, please try to rebuild target.\"\n\t\treturn\n\tfi\n\n\tremove_igb_uio_module\n\n\t/sbin/lsmod | grep -s uio > /dev/null\n\tif [ $? -ne 0 ] ; then\n\t\tmodinfo uio > /dev/null\n\t\tif [ $? -eq 0 ]; then\n\t\t\techo \"Loading uio module\"\n\t\t\tsudo /sbin/modprobe uio\n\t\tfi\n\tfi\n\n\t# UIO may be compiled into kernel, so it may not be an error if it can't\n\t# be loaded.\n\n\techo \"Loading DPDK UIO module\"\n\tsudo /sbin/insmod $RTE_SDK/$RTE_TARGET/kmod/igb_uio.ko\n\tif [ $? -ne 0 ] ; then\n\t\techo \"## ERROR: Could not load kmod/igb_uio.ko.\"\n\t\tquit\n\tfi\n}\n\n#\n# Unloads VFIO modules.\n#\nremove_vfio_module()\n{\n\techo \"Unloading any existing VFIO module\"\n\t/sbin/lsmod | grep -s vfio > /dev/null\n\tif [ $? -eq 0 ] ; then\n\t\tsudo /sbin/rmmod vfio-pci\n\t\tsudo /sbin/rmmod vfio_iommu_type1\n\t\tsudo /sbin/rmmod vfio\n\tfi\n}\n\n#\n# Loads new vfio-pci (and vfio module if needed).\n#\nload_vfio_module()\n{\n\tremove_vfio_module\n\n\tVFIO_PATH=\"kernel/drivers/vfio/pci/vfio-pci.ko\"\n\n\techo \"Loading VFIO module\"\n\t/sbin/lsmod | grep -s vfio_pci > /dev/null\n\tif [ $? -ne 0 ] ; then\n\t\tif [ -f /lib/modules/$(uname -r)/$VFIO_PATH ] ; then\n\t\t\tsudo /sbin/modprobe vfio-pci\n\t\tfi\n\tfi\n\n\t# make sure regular users can read /dev/vfio\n\techo \"chmod /dev/vfio\"\n\tsudo chmod a+x /dev/vfio\n\tif [ $? -ne 0 ] ; then\n\t\techo \"FAIL\"\n\t\tquit\n\tfi\n\techo \"OK\"\n\n\t# check if /dev/vfio/vfio exists - that way we\n\t# know we either loaded the module, or it was\n\t# compiled into the kernel\n\tif [ ! -e /dev/vfio/vfio ] ; then\n\t\techo \"## ERROR: VFIO not found!\"\n\tfi\n}\n\n#\n# Unloads the rte_kni.ko module.\n#\nremove_kni_module()\n{\n\techo \"Unloading any existing DPDK KNI module\"\n\t/sbin/lsmod | grep -s rte_kni > /dev/null\n\tif [ $? -eq 0 ] ; then\n\t\tsudo /sbin/rmmod rte_kni\n\tfi\n}\n\n#\n# Loads the rte_kni.ko module.\n#\nload_kni_module()\n{\n # Check that the KNI module is already built.\n\tif [ ! -f $RTE_SDK/$RTE_TARGET/kmod/rte_kni.ko ];then\n\t\techo \"## ERROR: Target does not have the DPDK KNI Module.\"\n\t\techo \" To fix, please try to rebuild target.\"\n\t\treturn\n\tfi\n\n # Unload existing version if present.\n\tremove_kni_module\n\n # Now try load the KNI module.\n\techo \"Loading DPDK KNI module\"\n\tsudo /sbin/insmod $RTE_SDK/$RTE_TARGET/kmod/rte_kni.ko\n\tif [ $? -ne 0 ] ; then\n\t\techo \"## ERROR: Could not load kmod/rte_kni.ko.\"\n\t\tquit\n\tfi\n}\n\n#\n# Sets appropriate permissions on /dev/vfio/* files\n#\nset_vfio_permissions()\n{\n\t# make sure regular users can read /dev/vfio\n\techo \"chmod /dev/vfio\"\n\tsudo chmod a+x /dev/vfio\n\tif [ $? -ne 0 ] ; then\n\t\techo \"FAIL\"\n\t\tquit\n\tfi\n\techo \"OK\"\n\n\t# make sure regular user can access everything inside /dev/vfio\n\techo \"chmod /dev/vfio/*\"\n\tsudo chmod 0666 /dev/vfio/*\n\tif [ $? -ne 0 ] ; then\n\t\techo \"FAIL\"\n\t\tquit\n\tfi\n\techo \"OK\"\n\n\t# since permissions are only to be set when running as\n\t# regular user, we only check ulimit here\n\t#\n\t# warn if regular user is only allowed\n\t# to memlock <64M of memory\n\tMEMLOCK_AMNT=`ulimit -l`\n\n\tif [ \"$MEMLOCK_AMNT\" != \"unlimited\" ] ; then\n\t\tMEMLOCK_MB=`expr $MEMLOCK_AMNT / 1024`\n\t\techo \"\"\n\t\techo \"Current user memlock limit: ${MEMLOCK_MB} MB\"\n\t\techo \"\"\n\t\techo \"This is the maximum amount of memory you will be\"\n\t\techo \"able to use with DPDK and VFIO if run as current user.\"\n\t\techo -n \"To change this, please adjust limits.conf memlock \"\n\t\techo \"limit for current user.\"\n\n\t\tif [ $MEMLOCK_AMNT -lt 65536 ] ; then\n\t\t\techo \"\"\n\t\t\techo \"## WARNING: memlock limit is less than 64MB\"\n\t\t\techo -n \"## DPDK with VFIO may not be able to initialize \"\n\t\t\techo \"if run as current user.\"\n\t\tfi\n\tfi\n}\n\n#\n# Removes all reserved hugepages.\n#\nclear_huge_pages()\n{\n\techo > .echo_tmp\n\tfor d in /sys/devices/system/node/node? ; do\n\t\techo \"echo 0 > $d/hugepages/hugepages-2048kB/nr_hugepages\" >> .echo_tmp\n\tdone\n\techo \"Removing currently reserved hugepages\"\n\tsudo sh .echo_tmp\n\trm -f .echo_tmp\n\n\tremove_mnt_huge\n}\n\n#\n# Creates hugepages.\n#\nset_non_numa_pages()\n{\n\tclear_huge_pages\n\n\techo \"\"\n\techo \" Input the number of 2MB pages\"\n\techo \" Example: to have 128MB of hugepages available, enter '64' to\"\n\techo \" reserve 64 * 2MB pages\"\n\techo -n \"Number of pages: \"\n\tread Pages\n\n\techo \"echo $Pages > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages\" > .echo_tmp\n\n\techo \"Reserving hugepages\"\n\tsudo sh .echo_tmp\n\trm -f .echo_tmp\n\n\tcreate_mnt_huge\n}\n\n#\n# Creates hugepages on specific NUMA nodes.\n#\nset_numa_pages()\n{\n\tclear_huge_pages\n\n\techo \"\"\n\techo \" Input the number of 2MB pages for each node\"\n\techo \" Example: to have 128MB of hugepages available per node,\"\n\techo \" enter '64' to reserve 64 * 2MB pages on each node\"\n\n\techo > .echo_tmp\n\tfor d in /sys/devices/system/node/node? ; do\n\t\tnode=$(basename $d)\n\t\techo -n \"Number of pages for $node: \"\n\t\tread Pages\n\t\techo \"echo $Pages > $d/hugepages/hugepages-2048kB/nr_hugepages\" >> .echo_tmp\n\tdone\n\techo \"Reserving hugepages\"\n\tsudo sh .echo_tmp\n\trm -f .echo_tmp\n\n\tcreate_mnt_huge\n}\n\n#\n# Run unit test application.\n#\nrun_test_app()\n{\n\techo \"\"\n\techo \" Enter hex bitmask of cores to execute test app on\"\n\techo \" Example: to execute app on cores 0 to 7, enter 0xff\"\n\techo -n \"bitmask: \"\n\tread Bitmask\n\techo \"Launching app\"\n\tsudo ${RTE_TARGET}/app/test -c $Bitmask $EAL_PARAMS\n}\n\n#\n# Run unit testpmd application.\n#\nrun_testpmd_app()\n{\n\techo \"\"\n\techo \" Enter hex bitmask of cores to execute testpmd app on\"\n\techo \" Example: to execute app on cores 0 to 7, enter 0xff\"\n\techo -n \"bitmask: \"\n\tread Bitmask\n\techo \"Launching app\"\n\tsudo ${RTE_TARGET}/app/testpmd -c $Bitmask $EAL_PARAMS -- -i\n}\n\n#\n# Print hugepage information.\n#\ngrep_meminfo()\n{\n\tgrep -i huge /proc/meminfo\n}\n\n#\n# Calls dpdk_nic_bind.py --status to show the NIC and what they\n# are all bound to, in terms of drivers.\n#\nshow_nics()\n{\n\tif /sbin/lsmod | grep -q -e igb_uio -e vfio_pci; then\n\t\t${RTE_SDK}/tools/dpdk_nic_bind.py --status\n\telse\n\t\techo \"# Please load the 'igb_uio' or 'vfio-pci' kernel module before \"\n\t\techo \"# querying or adjusting NIC device bindings\"\n\tfi\n}\n\n#\n# Uses dpdk_nic_bind.py to move devices to work with vfio-pci\n#\nbind_nics_to_vfio()\n{\n\tif /sbin/lsmod | grep -q vfio_pci ; then\n\t\t${RTE_SDK}/tools/dpdk_nic_bind.py --status\n\t\techo \"\"\n\t\techo -n \"Enter PCI address of device to bind to VFIO driver: \"\n\t\tread PCI_PATH\n\t\tsudo ${RTE_SDK}/tools/dpdk_nic_bind.py -b vfio-pci $PCI_PATH &&\n\t\t\techo \"OK\"\n\telse\n\t\techo \"# Please load the 'vfio-pci' kernel module before querying or \"\n\t\techo \"# adjusting NIC device bindings\"\n\tfi\n}\n\n#\n# Uses dpdk_nic_bind.py to move devices to work with igb_uio\n#\nbind_nics_to_igb_uio()\n{\n\tif /sbin/lsmod | grep -q igb_uio ; then\n\t\t${RTE_SDK}/tools/dpdk_nic_bind.py --status\n\t\techo \"\"\n\t\techo -n \"Enter PCI address of device to bind to IGB UIO driver: \"\n\t\tread PCI_PATH\n\t\tsudo ${RTE_SDK}/tools/dpdk_nic_bind.py -b igb_uio $PCI_PATH && echo \"OK\"\n\telse\n\t\techo \"# Please load the 'igb_uio' kernel module before querying or \"\n\t\techo \"# adjusting NIC device bindings\"\n\tfi\n}\n\n#\n# Uses dpdk_nic_bind.py to move devices to work with kernel drivers again\n#\nunbind_nics()\n{\n\t${RTE_SDK}/tools/dpdk_nic_bind.py --status\n\techo \"\"\n\techo -n \"Enter PCI address of device to unbind: \"\n\tread PCI_PATH\n\techo \"\"\n\techo -n \"Enter name of kernel driver to bind the device to: \"\n\tread DRV\n\tsudo ${RTE_SDK}/tools/dpdk_nic_bind.py -b $DRV $PCI_PATH && echo \"OK\"\n}\n\n#\n# Options for building a target. Note that this step MUST be first as it sets\n# up TARGETS[] starting from 1, and this is accessed in setup_target using the\n# user entered option.\n#\nstep1_func()\n{\n\tTITLE=\"Select the DPDK environment to build\"\n\tCONFIG_NUM=1\n\tfor cfg in config/defconfig_* ; do\n\t\tcfg=${cfg/config\\/defconfig_/}\n\t\tTEXT[$CONFIG_NUM]=\"$cfg\"\n\t\tTARGETS[$CONFIG_NUM]=$cfg\n\t\tFUNC[$CONFIG_NUM]=\"setup_target\"\n\t\tlet \"CONFIG_NUM+=1\"\n\tdone\n}\n\n#\n# Options for setting up environment.\n#\nstep2_func()\n{\n\tTITLE=\"Setup linuxapp environment\"\n\n\tTEXT[1]=\"Insert IGB UIO module\"\n\tFUNC[1]=\"load_igb_uio_module\"\n\n\tTEXT[2]=\"Insert VFIO module\"\n\tFUNC[2]=\"load_vfio_module\"\n\n\tTEXT[3]=\"Insert KNI module\"\n\tFUNC[3]=\"load_kni_module\"\n\n\tTEXT[4]=\"Setup hugepage mappings for non-NUMA systems\"\n\tFUNC[4]=\"set_non_numa_pages\"\n\n\tTEXT[5]=\"Setup hugepage mappings for NUMA systems\"\n\tFUNC[5]=\"set_numa_pages\"\n\n\tTEXT[6]=\"Display current Ethernet device settings\"\n\tFUNC[6]=\"show_nics\"\n\n\tTEXT[7]=\"Bind Ethernet device to IGB UIO module\"\n\tFUNC[7]=\"bind_nics_to_igb_uio\"\n\n\tTEXT[8]=\"Bind Ethernet device to VFIO module\"\n\tFUNC[8]=\"bind_nics_to_vfio\"\n\n\tTEXT[9]=\"Setup VFIO permissions\"\n\tFUNC[9]=\"set_vfio_permissions\"\n}\n\n#\n# Options for running applications.\n#\nstep3_func()\n{\n\tTITLE=\"Run test application for linuxapp environment\"\n\n\tTEXT[1]=\"Run test application (\\$RTE_TARGET/app/test)\"\n\tFUNC[1]=\"run_test_app\"\n\n\tTEXT[2]=\"Run testpmd application in interactive mode (\\$RTE_TARGET/app/testpmd)\"\n\tFUNC[2]=\"run_testpmd_app\"\n}\n\n#\n# Other options\n#\nstep4_func()\n{\n\tTITLE=\"Other tools\"\n\n\tTEXT[1]=\"List hugepage info from /proc/meminfo\"\n\tFUNC[1]=\"grep_meminfo\"\n\n}\n\n#\n# Options for cleaning up the system\n#\nstep5_func()\n{\n\tTITLE=\"Uninstall and system cleanup\"\n\n\tTEXT[1]=\"Uninstall all targets\"\n\tFUNC[1]=\"uninstall_targets\"\n\n\tTEXT[2]=\"Unbind NICs from IGB UIO or VFIO driver\"\n\tFUNC[2]=\"unbind_nics\"\n\n\tTEXT[3]=\"Remove IGB UIO module\"\n\tFUNC[3]=\"remove_igb_uio_module\"\n\n\tTEXT[4]=\"Remove VFIO module\"\n\tFUNC[4]=\"remove_vfio_module\"\n\n\tTEXT[5]=\"Remove KNI module\"\n\tFUNC[5]=\"remove_kni_module\"\n\n\tTEXT[6]=\"Remove hugepage mappings\"\n\tFUNC[6]=\"clear_huge_pages\"\n}\n\nSTEPS[1]=\"step1_func\"\nSTEPS[2]=\"step2_func\"\nSTEPS[3]=\"step3_func\"\nSTEPS[4]=\"step4_func\"\nSTEPS[5]=\"step5_func\"\n\nQUIT=0\n\nwhile [ \"$QUIT\" == \"0\" ]; do\n\tOPTION_NUM=1\n\n\tfor s in $(seq ${#STEPS[@]}) ; do\n\t\t${STEPS[s]}\n\n\t\techo \"----------------------------------------------------------\"\n\t\techo \" Step $s: ${TITLE}\"\n\t\techo \"----------------------------------------------------------\"\n\n\t\tfor i in $(seq ${#TEXT[@]}) ; do\n\t\t\techo \"[$OPTION_NUM] ${TEXT[i]}\"\n\t\t\tOPTIONS[$OPTION_NUM]=${FUNC[i]}\n\t\t\tlet \"OPTION_NUM+=1\"\n\t\tdone\n\n\t\t# Clear TEXT and FUNC arrays before next step\n\t\tunset TEXT\n\t\tunset FUNC\n\n\t\techo \"\"\n\tdone\n\n\techo \"[$OPTION_NUM] Exit Script\"\n\tOPTIONS[$OPTION_NUM]=\"quit\"\n\techo \"\"\n\techo -n \"Option: \"\n\tread our_entry\n\techo \"\"\n\t${OPTIONS[our_entry]} ${our_entry}\n\techo\n\techo -n \"Press enter to continue ...\"; read\ndone\n" } ]